From c5599650343928607ee3ee8c126535a285ae1527 Mon Sep 17 00:00:00 2001
From: svcmobrel-release <svcmobrel-release@nvidia.com>
Date: Tue, 21 Jan 2025 05:25:03 -0800
Subject: [PATCH] Updating prebuilts and/or headers

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3e0485b2ab91a71ec11ece327d699961e52a1701 - spe-freertos-bsp/fsp/source/include/car/car-clk.h
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0e72a366294f2aebd9bee9618484d9f617e06053 - spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/aodmic-port.h
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9838197ab8cdf8fcb5b7dc2e66505346a14cb557 - spe-freertos-bsp/fsp/source/include/soc/t234/bpmp/processor/cache-hw.h
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3f7814f3fd7b5587598377b257af07b192fcb7b0 - spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-fmon.h
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9838197ab8cdf8fcb5b7dc2e66505346a14cb557 - spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/cache-hw.h
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Change-Id: I7366cb2d516eedb2728bf0d464f46baa772df7bf
---
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diff --git a/commitFile.txt b/commitFile.txt
new file mode 100644
index 0000000..6d92aa5
--- /dev/null
+++ b/commitFile.txt
@@ -0,0 +1,1220 @@
+Updating prebuilts and/or headers 
+
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diff --git a/push_info.txt b/push_info.txt
new file mode 100644
index 0000000..eefca6d
--- /dev/null
+++ b/push_info.txt
@@ -0,0 +1 @@
+jetson_36.4.3
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/GitHub-FreeRTOS-Kernel-Home.url b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/GitHub-FreeRTOS-Kernel-Home.url
new file mode 100644
index 0000000..ee675d6
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/GitHub-FreeRTOS-Kernel-Home.url
@@ -0,0 +1,8 @@
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2
+[InternetShortcut]
+URL=https://github.com/FreeRTOS/FreeRTOS-Kernel
+IconIndex=0
+IDList=
+HotKey=0
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/History.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/History.txt
new file mode 100644
index 0000000..6dcf3ce
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/History.txt
@@ -0,0 +1,2831 @@
+Documentation and download available at https://www.FreeRTOS.org/
+
+Changes between FreeRTOS V10.4.2 and FreeRTOS V10.4.3 released December 14 2020
+
+	V10.4.3 is included in the 202012.00 LTS release.  Learn more at https:/freertos.org/lts-libraries.html
+
+	See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html
+
+	+ Changes to improve robustness and consistency for buffer allocation in
+	  the heap, queue and stream buffer.
+	+ The following functions can no longer be called from unprivileged code.
+	  - xTaskCreateRestricted
+	  - xTaskCreateRestrictedStatic
+	  - vTaskAllocateMPURegions
+
+
+Changes between FreeRTOS V10.4.1 and FreeRTOS V10.4.2 released November 10 2020
+	
+	See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html
+
+	+ Fix an issue in the ARMv8-M ports that caused BASEPRI to be masked 
+	  between the first task starting to execute and that task making 
+	  a FreeRTOS API call.
+	+ Introduced xTaskDelayUntil(), which is functionally equivalent to
+	  vTaskDelayUntil(), with the addition of returning a value to 
+	  indicating whether or not the function placed the calling task into
+	  the Blocked state or not.
+	+ Update WolfSSL to 4.5.0 and add the FIPS ready demo.
+	+ Add support for ESP IDF 4.2 to ThirdParty Xtensa port.
+	+ Re-introduce uxTopUsedPriority to support OpenOCD debugging.
+	+ Convert most dependent libraries in FreeRTOS/FreeRTOS to submodules.
+	+ Various general maintenance and improvements to MISRA compliance.
+
+
+Changes between FreeRTOS V10.4.0 and FreeRTOS V10.4.1 released September 17 2020
+
+	See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html
+
+	+ Fixed an incorrectly named parameter that prevented the 
+	  ulTaskNotifyTakeIndexed macro compiling, and the name space clash in the 
+	  test code that prevented this error causing test failures.
+
+
+Changes between FreeRTOS V10.3.1 and FreeRTOS V10.4.0 released September 10 2020
+
+	See https://www.FreeRTOS.org/FreeRTOS-V10.4.x.html
+
+	Major enhancements:
+
+	+ Task notifications:  Prior to FreeRTOS V10.4.0 each created task had a
+	  single direct to task notification.  From FreeRTOS V10.4.0 each task has
+	  an array of notifications.  The direct to task notification API has been
+	  extended with API functions postfixed with "Indexed" to enable the API to
+	  operate on a task notification at any array index.  See
+	  https://www.freertos.org/RTOS-task-notifications.html for more information.
+	+ Kernel ports that support memory protection units (MPUs): The ARMv7-M and
+	  ARMv8-M MPU ports now support a privilege access only heap. The ARMv7-M
+	  MPU ports now support devices that have 16 MPU regions, have the ability
+	  to override default memory attributes for privileged code and data
+	  regions, and have the ability to place the FreeRTOS kernel code outside of
+	  the Flash memory. The ARMv8-M MPU ports now support tickless idle mode.
+	  See https://www.freertos.org/FreeRTOS-MPU-memory-protection-unit.html
+	  for more information.
+
+	Additional noteworthy updates:
+
+	+ Code formatting is now automated to facilitate the increase in
+	  collaborative development in Git.  The auto-formated code is not identical
+	  to the original formatting conventions.  Most notably spaces are now used
+	  in place of tabs.
+	+ The prototypes for callback functions (those that start with "Application",
+	  such as vApplicationStackOverflowHook()) are now in the FreeRTOS header
+	  files, removing the need for application writers to add prototypes into
+	  the C files in which they define the functions.
+	+ New Renesas RXv3 port layer.
+	+ Updates to the Synopsys ARC code, including support for EM and HS cores,
+	  and updated BSP.
+	+ Added new POSIX port layer that allows FreeRTOS to run on Linux hosts in
+	  the same way the Windows port layer enables FreeRTOS to run on Windows
+	  hosts.
+	+ Many other minor optimisations and enhancements. For full details  
+	  see https://github.com/FreeRTOS/FreeRTOS-Kernel/commits/master
+
+
+Changes between FreeRTOS V10.3.0 and FreeRTOS V10.3.1 released February 18 2020
+
+	See https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html
+
+	+ ./FreeRTOS-Labs directory was removed from this file. The libraries it
+	contained are now available as a separate download.
+
+Changes between FreeRTOS V10.2.1 and FreeRTOS V10.3.0 released February 7 2020
+
+	See https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html
+
+	New and updated kernel ports:
+
+	+ Added RISC-V port for the IAR compiler.
+	+ Update the Windows simulator port to use a synchronous object to prevent
+	  a user reported error whereby a task continues to run for a short time
+	  after being moved to the Blocked state.  Note we were not able to
+	  replicate the reported issue and it likely depends on your CPU model.
+	+ Correct alignment of stack top in RISC-V port when
+	  configISR_STACK_SIZE_WORDS is defined to a non zero value, which causes
+	  the interrupt stack to be statically allocated.
+	+ The RISC-V machine timer compare register can now be for any HART, whereas
+	  previously it was always assumed FreeRTOS was running on HART 0.
+	+ Update the sequence used to update the 64-bit machine timer
+	  compare register on 32-bit cores to match that suggested in RISC-V
+	  documentation.
+	+ Added tickless low power modes into the ARM, IAR and GCC Cortex-M0 compiler
+	  ports.
+	+ Updated the behaviour of the ARMv7-M MPU (Memory Protection Unit) ports to
+	  match that of the ARMv8-M ports whereby privilege escalations can only
+	  originate from within the kernel's own memory segment.  Added
+	  configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY configuration constant.
+	+ Update existing MPU ports to correctly disable the MPU before it is
+	  updated.
+	+ Added contributed port and demo application for a T-Head (formally C-SKY)
+	  microcontroller.
+
+	New API functions:
+
+	+ Added the vPortGetHeapStats() API function which returns information on
+	  the heap_4 and heap_5 state.
+	+ Added xTaskCatchUpTicks(), which corrects the tick count value after the
+	  application code has held interrupts disabled for an extended period.
+	+ Added xTaskNotifyValueClear() API function.
+	+ Added uxTimerGetReloadMode() API function.
+
+	Other miscellaneous changes:
+	+ Change type of uxPendedTicks from UBaseType_t to TickType_t to ensure it
+	  has the same type as variables with which it is compared to, and therefore
+	  also renamed the variable xPendingTicks.
+	+ Update Keil projects that use the MPU so memory regions come from linker
+	  script (scatter file) variables instead of being hard coded.
+	+ Added LPC51U68 Cortex-M0+ demos for GCC (MCUXpresso), Keil and IAR
+	  compilers.
+	+ Added CORTEX_MPU_STM32L4_Discovery_Keil_STM32Cube demo.
+	+ Added LPC54018 MPU demo.
+	+ Rename xTaskGetIdleRunTimeCounter() to ulTaskGetIdleRunTimeCounter().
+
+
+Changes between FreeRTOS V10.2.1 and FreeRTOS V10.2.0 released May 13 2019:
+
+	+ Added ARM Cortex-M23 port layer to complement the pre-existing ARM
+	  Cortex-M33 port layer.
+	+ The RISC-V port now automatically switches between 32-bit and 64-bit
+	  cores.
+	+ Introduced the portMEMORY_BARRIER macro to prevent instruction re-ordering
+	  when GCC link time optimisation is used.
+	+ Introduced the portDONT_DISCARD macro to the ARMv8-M ports to try and
+	  prevent the secure side builds from removing symbols required by the
+	  non secure side build.
+	+ Introduced the portARCH_NAME to provide additional data to select semi-
+	  automated build environments.
+	+ Cortex-M33 and Cortex-M23 ports now correctly disable the MPU before
+	  updating the MPU registers.
+
+	+ Added Nuvoton NuMaker-PFM-M2351 ARM Cortex-M23 demo.
+	+ Added LPC55S69 ARM Cortex-M33 demo.
+	+ Added an STM32 dual core AMP stress test demo.
+
+
+Changes between FreeRTOS V10.1.1 and FreeRTOS V10.2.0 released February 25 2019:
+
+	+ Added GCC RISC-V MCU port with three separate demo applications.
+	+ Included pre-existing ARM Cortex-M33 (ARMv8-M) GCC/ARMclang and IAR ports
+	  with Keil simulator demo.
+	+ Update the method used to detect if a timer is active.  Previously the
+	  timer was deemed to be inactive if it was not referenced from a list.
+	  However, when a timer is updated it is temporarily removed from, then
+	  re-added to a list, so now the timer's active status is stored separately.
+	+ Add vTimerSetReloadMode(), xTaskGetIdleRunTimeCounter(), and
+	  xTaskGetApplicationTaskTagFromISR() API functions.
+	+ Updated third party Xtensa port so it is MIT licensed.
+	+ Added configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H to the Renesas
+	  compiler RX600v2 port to enable switching between platform.h and
+	  iodefine.h includes within that port's port.c file.
+	+ Removed the 'FromISR' functions from the MPU ports as ISRs run privileged
+	  anyway.
+	+ Added uxTaskGetStackHighWaterMark2() function to enable the return type to
+	  be changed without breaking backward compatibility.
+	  uxTaskGetStackHighWaterMark() returns a UBaseType_t as always,
+	  uxTaskGetStackHighWaterMark2() returns configSTACK_DEPTH_TYPE to allow the
+	  user to determine the return type.
+	+ Fixed issues in memory protected ports related to different combinations
+	  of static memory only and dynamic memory only builds.  As a result the
+	  definition of tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE became more
+	  complex and was moved to FreeRTOS.h with a table explaining its definition.
+	+ Added a 'get task tag from ISR' function.
+	+ Change the method used to determine if a timer is active or not from just
+	  seeing if it is referenced from the active timer list to storing its
+	  active state explicitly.  The change prevents the timer reporting that it
+	  is inactive while it is being moved from one list to another.
+	+ The pcName parameter passed into the task create functions can be NULL,
+	  previously a name had to be provided.
+	+ When using tickless idle, prvResetNextTaskUnblockTime() is now only called
+	  in xTaskRemoveFromEventList() if the scheduler is not suspended.
+	+ Introduced portHAS_STACK_OVERFLOW_CHECKING, which should be set to 1 for
+	  FreeRTOS ports that run on architectures that have stack limit registers.
+
+
+Changes between FreeRTOS V10.1.0 and FreeRTOS V10.1.1 released 7 September 2018
+
+	+ Reverted a few structure name changes that broke several kernel aware
+	  debugger plug-ins.
+	+ Updated to the latest trace recorder code.
+	+ Fixed some formatting in the FreeRTOS+TCP TCP/IP stack code.
+	+ Reverted moving some variables from file to function scope as doing so
+	  broke debug scenarios that require the static qualifier to be removed.
+
+Changes between FreeRTOS V10.0.1 and FreeRTOS V10.1.0 released 22 August 2018
+
+	FreeRTOS Kernel Changes:
+
+	+ Update lint checked MISRA compliance to use the latest MISRA standard, was
+	  previously using the original MISRA standard.
+	+ Updated all object handles (TaskHandle_t, QueueHandle_t, etc.) to be
+	  unique types instead of void pointers, improving type safety.  (this was
+	  attempted some years back but had to be backed out due to bugs in some
+	  debuggers).  Note this required the pvContainer member of a ListItem_t
+	  struct to be renamed - set configENABLE_BACKWARD_COMPATIBILITY to 1 if
+	  this causes an issue.
+	+ Added configUSE_POSIX_ERRNO to enable per task POSIX style errno
+	  functionality in a more user friendly way - previously the generic thread
+	  local storage feature was used for this purpose.
+	+ Added Xtensa port and demo application for the XCC compiler.
+	+ Changed the implementation of vPortEndScheduler() for the Win32 port to
+	  simply call exit( 0 ).
+	+ Bug fix in vPortEnableInterrupt() for the GCC Microblaze port to protect
+	  the read modify write access to an internal Microblaze register.
+	+ Fix minor niggles when the MPU is used with regards to prototype
+	  differences, static struct size differences, etc.
+	+ The usStackHighWaterMark member of the TaskStatus_t structure now has type
+	  configSTACK_DEPTH_TYPE in place of uint16_t - that change should have been
+	  made when the configSTACK_DEPTH_TYPE type (which gets around the previous
+	  16-bit limit on stack size specifications) was introduced.
+	+ Added the xMessageBufferNextLengthBytes() API function and likewise stream
+	  buffer equivalent.
+	+ Introduce configMESSAGE_BUFFER_LENGTH_TYPE to allow the number of bytes
+	  used to hold the length of a message in the message buffer to be reduced.
+	  configMESSAGE_BUFFER_LENGTH_TYPE default to size_t, but if, for example,
+	  messages can never be more than 255 bytes it could be set to uint8_t,
+	  saving 3 bytes each time a message is written into the message buffer
+	  (assuming sizeof( size_t ) is 4).
+	+ Updated the StaticTimer_t structure to ensure it matches the size of the
+	  Timer_t structure when the size of TaskFunction_t does not equal the size
+	  of void *.
+	+ Update various Xilinx demos to use 2018.1 version of the SDK tools.
+	+ Various updates to demo tasks to maintain test coverage.
+	+ FreeRTOS+UDP was removed in FreeRTOS V10.1.0 as it was replaced by
+	  FreeRTOS+TCP, which was brought into the main download in FreeRTOS
+	  V10.0.0.  FreeRTOS+TCP can be configured as a UDP only stack, and
+	  FreeRTOS+UDP does not contain the patches applied to FreeRTOS+TCP.
+
+	FreeRTOS+TCP Changes:
+
+	+ Multiple security improvements and fixes in packet parsing routines, DNS
+	  caching, and TCP sequence number and ID generation.
+	+ Disable NBNS and LLMNR by default.
+	+ Add TCP hang protection by default.
+
+	We thank Ori Karliner of Zimperium zLabs Team for reporting these issues.
+
+
+Changes between FreeRTOS V10.0.0 and FreeRTOS V10.0.1, released December 20 2017
+
+	+ Fix position of "#if defined( __cplusplus )" in stream_buffer.h.
+	+ Correct declarations of MPU_xQueuePeek() and MPU_xQueueSemaphoreTake() in
+	  mpu_prototypes.h.
+	+ Correct formatting in vTaskList() helper function when it prints the state
+	  of the currently executing task.
+	+ Introduce #error if stream_buffer.c is built without
+	  configUSE_TASK_NOTIFICATIONS set to 1.
+	+ Update FreeRTOS+TCP to V2.0.0
+		- Improve the formatting of text that displays the available netword
+		  interfaces when FreeRTOS+TCP is used on Windows with WinPCap.
+		- Introduce ipconfigSOCKET_HAS_USER_WAKE_CALLBACK option to enable a user
+		  definable callback to execute when data arrives on a socket.
+
+Changes between FreeRTOS V9.0.1 and FreeRTOS V10.0.0:
+
+	The FreeRTOS kernel is now MIT licensed: https://www.FreeRTOS.org/license
+
+	New Features and components:
+
+	+ Stream Buffers - see https://www.FreeRTOS.org/RTOS-stream-buffer-example.html
+	+ Message Buffers - see https://www.FreeRTOS.org//RTOS-message-buffer-example.html
+	+ Move FreeRTOS+TCP into the main repository, along with the basic Win32
+	  TCP demo FreeRTOS_Plus_TCP_Minimal_Windows_Simulator.
+
+	New ports or demos:
+
+	+ Added demo for TI SimpleLink CC3220 MCU.
+	+ Added MPU and non MPU projects for Microchip CEC and MEC 17xx and 51xx
+	  MCUs.
+	+ Added CORTEX_MPU_Static_Simulator_Keil_GCC demo to test static allocation
+	  in the MPU port.
+
+	Fixes or enhancements:
+
+	+ Cortex-M ports push additional register prior to calling
+	  vTaskSwitchContext to ensure 8-byte alignment is maintained.  Only
+	  important if a user defined tick hook function performs an operation that
+	  requires 8-byte alignment.
+	+ Optimisations to the implementation of the standard tickless idle mode on
+	  Cortex-M devices.
+	+ Improvements to the Win32 port including using higher priority threads.
+	+ Ensure interrupt stack alignment on PIC32 ports.
+	+ Updated GCC TriCore port to build with later compiler versions.
+	+ Update mpu_wrappers.c to support static allocation.
+	+ The uxNumberOfItems member of List_t is now volatile - solving an issue
+	  when the IAR compiler was used with maximum optimization.
+	+ Introduced configRECORD_STACK_HIGH_ADDRESS.  When set to 1 the stack start
+	  address is saved into each task's TCB (assuming stack grows down).
+	+ Introduced configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H to allow user defined
+	  functionality, and user defined initialisation, to be added to FreeRTOS's
+	  tasks.c source file.  When configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H is
+	  set to 1 a user provided header file called freertos_task_c_additions.h
+	  will be included at the bottom of tasks.c.  Functions defined in that
+	  header file can call freertos_tasks_c_additions_init(), which in turn
+	  calls a macro called FREERTOS_TASKS_C_ADDITIONS_INIT(), if it is defined.
+	  FREERTOS_TASKS_C_ADDITIONS_INIT() can be defined in FreeRTOSConfig.h.
+	+ Introduced configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) which can be
+	  defined by a user in FreeRTOSConfig.h.  The macro is called before
+	  assessing whether to enter tickless idle mode or not.  If the macro sets
+	  x to zero then tickless idle mode will not be entered.  This allows users
+	  to abort tickless idle mode entry before the tickless idle function is
+	  even called - previously it was only possible to abort from within the
+	  tickless idle function itself.
+	+ Added configPRINTF(), which can be defined by users to allow all libraries
+	  to use the same print formatter.
+	+ Introduced configMAX() and configMIN() macros which default to standard
+	  max( x, y ) and min( x, y ) macro behaviour, but can be overridden if the
+	  application writer defines the same macros in FreeRTOSConfig.h.
+	+ Corrected the definition of StaticTask_t in the case where
+	  INCLUDE_xTaskAbortDelay is set to 1.
+	+ Introduced configTIMER_SERVICE_TASK_NAME and configIDLE_TASK_NAME, both of
+	  which can be defined to strings in FreeRTOSConfig.h to change the default
+	  names of the timer service and idle tasks respectively.
+	+ Only fill the stack of a newly created task with a known value if stack
+	  checking, or high water mark checking/viewing, is in use - removing the
+	  dependency on memset() in other cases.
+	+ Introduced xTaskCreateRestrictedStatic() so static allocation can be used
+	  with the MPU.
+	+ Ensure suspended tasks cannot be unsuspended by a received task
+	  notification.
+	+ Fix race condition in vTaskSetTimeOutState().
+	+ Updated trace recorder files to the latest version.
+
+Changes since FreeRTOS V9.0.0:
+
+	+ Priority dis-inheritance behaviour has been enhanced in the case where a
+	  task that attempted to take a mutex that was held by a lower priority task
+	  timed out before it was able to obtain the mutex (causing the task that
+	  holds the mutex to have its priority raised, then lowered again, in
+	  accordance with the priority inheritance protocol).
+	+ Split the overloaded xQueueGenericReceive() function into three separate
+	  dedicated functions.
+	+ Allow the default human readable text names given to the Idle and Timer
+	  tasks to be overridden by defining the configIDLE_TASK_NAME and
+	  configTIMER_SERVICE_TASK_NAME definitions respectively in FreeRTOSConfig.h.
+	+ Introduced configINITIAL_TICK_COUNT to allow the tick count to take a
+	  value of than than 0 when the system boots.  This can be useful for
+	  testing purposes - although setting configUSE_16_BIT_TICKS to 1 can also
+	  be used to test frequent tick overflows.
+	+ Ensure the Cortex-M SysTick count is cleared to zero before starting the
+	  first task.
+	+ Add configASSERT() into ARM Cortex-M ports to check the number of priority
+	  bit settings.
+	+ Clear the 'control' register before starting ARM Cortex-M4F ports in case
+	  the FPU is used before the scheduler is started.  This just saves a few
+	  bytes on the main stack as it prevents space being left for a later save
+	  of FPU registers.
+	+ Added xSemaphoreGetMutexHolderFromISR().
+	+ Corrected use of portNVIC_PENDSVSET to portNVIC_PENDSVSET_BIT in MPU ports.
+	+ Introduced configSTACK_DEPTH_TYPE to allow users to change the type used
+	  to specify the stack size when using xTaskCreate().  For historic reasons,
+	  when FreeRTOS was only used on small MCUs, the type was set to uint16_t,
+	  but that can be too restrictive when FreeRTOS is used on larger
+	  processors.  configSTACK_DEPTH_TYPE defaults to uint16_t.
+	  xTaskCreateStatic(), being a newer function, used a uint32_t.
+	+ Increase the priority of the Windows threads used by the Win32 port.  As
+	  all the threads run on the same core, and the threads run with very high
+	  priority, there is a risk that the host will become unresponsive, so also
+	  prevent the Windows port executing on single core hosts.
+
+Changes between FreeRTOS V9.0.0 and FreeRTOS V9.0.0rc2 released May 25 2016:
+
+	See https://www.FreeRTOS.org/FreeRTOS-V9.html
+
+	RTOS kernel updates:
+
+	+ The prototype of the new xTaskCreateStatic() API function was modified to
+	  remove a parameter and improve compatibility with other new
+	  "CreateStatic()" API functions.  The stack size parameter in
+	  xTaskCreateStatic() is now uint32_t, which changes the prototype of the
+	  callback functions.  See the following URL:
+	  https://www.FreeRTOS.org/xTaskCreateStatic.html
+	+ GCC ARM Cortex-A port:  Introduced the configUSE_TASK_FPU_SUPPORT
+	  constant.  When configUSE_TASK_FPU_SUPPORT is set to 2 every task is
+	  automatically given a floating point (FPU) context.
+	+ GCC ARM Cortex-A port:  It is now possible to automatically save and
+	  restore all floating point (FPU) registers on entry to each potentially
+	  nested interrupt by defining vApplicationFPUSafeIRQHandler() instead of
+	  vApplicationIRQHandler().
+	+ All ARM Cortex-M3/4F/7 ports:  Clear the least significant bit of the task
+	  entry address placed onto the stack of a task when the task is created for
+	  strict compliance with the ARM Cortex-M3/4/7 architecture documentation
+	  (no noticeable effect unless using the QMEU emulator).
+	+ Added GCC and Keil ARM Cortex-M4F MPU ports - previously the MPU was only
+	  supported on ARM Cortex-M3.
+	+ ARM Cortex-M3/4F MPU ports:  Update to fully support the FreeRTOS V9.0.0
+	  API (other than static object creation) and added the
+	  FreeRTOS/Demo/CORTEX_MPU_Simulator_Keil_GCC demo application to
+	  demonstrate how to use the updated MPU port.
+	+ All ARM Cortex-M3/4F/7 ports:  Add additional barrier instructions to the
+	  default low power tickless implementation.
+	+ All ARM Cortex-M0 ports:  Prevent an item being left on the stack of the
+	  first task that executes.
+	+ Win32 ports:  Reduce the amount of stack used and change the way Windows
+	  threads are deleted to increase the maximum execution time.
+	+ Add an ARM Cortex-M4F port for the MikroC compiler.  Ensure to read the
+	  documentation page for this port before use.
+	+ MPS430X IAR port:  Update to be compatible with the latest EW430 tools
+	  release.
+	+ IAR32 GCC port:  Correct vPortExitCritical() when
+	  configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY.
+	+ For consistency vTaskGetTaskInfo() now has the alias vTaskGetInfo(),
+	  xTaskGetTaskHandle() now has the alias xTaskGetHandle() and
+	  pcQueueGetQueueName() now has an alias pcQueueGetName().
+	+ Fix various errors in comments and compiler warnings.
+
+	Demo application updates:
+
+	+ Update Atmel Studio projects to use Atmel Studio 7.
+	+ Update Xilinx SDK projects to use the 2016.1 version of the SDK.
+	+ Remove dependency on legacy IO libraries from the PIC32 demos.
+	+ Move the Xilinx UltraScale Cortex-R5 demo into the main distribution.
+	+ Update the MSP432 libraries to the latest version.
+	+ Add Microchip CEC1302 (ARM Cortex-M4F) demos for GCC, Keil and MikroC
+	  compilers.
+	+ Move the Atmel SAMA5D2 demo into the main distribution.
+
+Changes between FreeRTOS V9.0.0rc1 and FreeRTOS V9.0.0rc2 (release candidate 2)
+released March 30 2016:
+
+	NOTE - See https://www.FreeRTOS.org/FreeRTOS-V9.html for details
+
+	+ The functions that create RTOS objects using static memory allocation have
+	  been simplified and will not revert to using dynamic allocation if a
+	  buffer is passed into a function as NULL.
+	+ Introduced the configSUPPORT_DYNAMIC_ALLOCATION configuration constant to
+	  allow a FreeRTOS application to be built without a heap even being being
+	  defined. The Win32 example located in the
+	  /FreeRTOS/demo/WIN32-MSVC-Static-Allocation-Only directory is provided as
+	  a reference for projects that do not include a FreeRTOS heap.
+	+ Minor run-time optimisations.
+	+ Two new low power tickless implementations that target Silicon Labs EFM32
+	  microcontrollers.
+	+ Addition of the xTimerGetPeriod() and xTimerGetExpireTime() API functions.
+
+Changes between FreeRTOS V8.2.3 and FreeRTOS V9.0.0rc1 (release candidate 1)
+released February 19 2016:
+
+	RTOS Kernel Updates:
+
+	+ Major new feature - tasks, semaphores, queues, timers and event groups can
+	  now be created using statically allocated memory, so without any calls to
+	  pvPortMalloc().
+	+ Major new features - Added the xTaskAbortDelay() API function which allows
+	  one task to force another task to immediately leave the Blocked state,
+	  even if the event the blocked task is waiting for has not occurred, or the
+	  blocked task's timeout has not expired.
+	+ Updates necessary to allow FreeRTOS to run on 64-bit architectures.
+	+ Added vApplicationDaemonTaskStartupHook() which executes when the RTOS
+	  daemon task (which used to be called the timer service task) starts
+	  running.  This is useful if the application includes initialisation code
+	  that would benefit from executing after the scheduler has been started.
+	+ Added the xTaskGetTaskHandle() API function, which obtains a task handle
+	  from the task's name.  xTaskGetTaskHandle() uses multiple string compare
+	  operations, so it is recommended that it is called only once per task.
+	  The handle returned by xTaskGetTaskHandle() can then be stored locally for
+	  later re-use.
+	+ Added the pcQueueGetQueueName() API function, which obtains the name of
+	  a queue from the queue's handle.
+	+ Tickless idling (for low power applications) can now also be used when
+	  configUSE_PREEMPTION is 0.
+	+ If one task deletes another task, then the stack and TCB of the deleted
+	  task is now freed immediately.  If a task deletes itself, then the stack
+	  and TCB of the deleted task are freed by the Idle task as before.
+	+ If a task notification is used to unblock a task from an ISR, but the
+	  xHigherPriorityTaskWoken parameter is not used, then pend a context switch
+	  that will then occur during the next tick interrupt.
+	+ Heap_1.c and Heap_2.c now use the configAPPLICATION_ALLOCATED_HEAP
+	  settings, which previously was only used by heap_4.c.
+	  configAPPLICATION_ALLOCATED_HEAP allows the application writer to declare
+	  the array that will be used as the FreeRTOS heap, and in-so-doing, place
+	  the heap at a specific memory location.
+	+ TaskStatus_t structures are used to obtain details of a task.
+	  TaskStatus_t now includes the bae address of the task's stack.
+	+ Added the vTaskGetTaskInfo() API function, which returns a TaskStatus_t
+	  structure that contains information about a single task.  Previously this
+	  information could only be obtained for all the tasks at once, as an array
+	  of TaskStatus_t structures.
+	+ Added the uxSemaphoreGetCount() API function.
+	+ Replicate previous Cortex-M4F and Cortex-M7 optimisations in some
+	  Cortex-M3 port layers.
+
+	Demo Application Updates:
+
+	Further demo applications will be added prior to the final FreeRTOS V9
+	release.
+
+	+ Updated SAM4L Atmel Studio project to use Atmel Studio 7.
+	+ Added ARM Cortex-A53 64-bit port.
+	+ Added a port and demo for the ARM Cortex-A53 64-bit cores on the Xilinx
+	  Ultrascale MPSoC.
+	+ Added Cortex-M7 SAME70 GCC demo.
+	+ Added EFM32 Giant and Wonder Gecko demos.
+
+
+Changes between V8.2.2 and V8.2.3 released October 16, 2015
+
+	RTOS kernel updates:
+
+	+ Fix bug identified in a modification made in V8.2.2 to the software timer
+	  code that allows tickless low power applications to sleep indefinitely
+	  when software timers are used.
+	+ Simplify and improve efficiency of stack overflow checking.
+	+ Add xTaskNotifyStateClear() API function.
+	+ New IAR and GCC Cortex-R ports for microprocessors that do not use an ARM
+	  generic interrupt controller (GIC).
+	+ New PIC32MEC14xx port.
+	+ Add support for PIC32MZ EF parts (with floating point) into the PIC32MZ
+	  port.
+	+ Zynq7000 port layer now declares the functions that setup and clear the
+	  tick interrupt as weak symbols so they can be overridden by the
+	  application, and uses a global XScuGic object so the same object can be
+	  used by the application code.
+	+ Introduced configUSE_TASK_FPU_SUPPORT, although the PIC32MZ EF port is
+	  currently the only port that uses it.
+	+ Updates to RL78 and 78K0 IAR port layers to improve support for
+	  combinations of memory models.
+	+ Minor updates to heap_5.c to remove compiler warnings generated by some
+	  compilers.
+	+ License simplifications.  See /FreeRTOS/License/license.txt in the
+	  official distribution.
+
+	FreeRTOS+ updates:
+
+	+ Update directory names to use WolfSSL instead of CyaSSL, inline with
+	  WolfSSL's re-branding.
+	+ Update to latest WolfSSL code.
+	+ Update to latest FreeRTOS+Trace recorder code.
+	+ Add in the FreeRTOS+Trace recorder library required for streaming trace.
+
+	Demo application changes:
+
+	+ Add demo applications for Renesas RZ/T (Cortex-R), PIC32MZ EF (PIC32 with
+	  floating point hardware), PIC32MEC14xx, RX71M, RX113 and RX231.
+	+ General tidy up of spelling and compiler warnings.
+
+
+Changes between V8.2.1 and V8.2.2 released August 12, 2015
+
+	RTOS kernel updates:
+
+	+ Added Intel IA32/x86 32-bit port.
+	+ General maintenance.
+	+ PRIVILEGED_FUNCTION and PRIVILEGED_DATA macros, which are used in memory
+	  protected systems, have been added to the newer event group and software
+	  timer functions.
+	+ Add the errno definitions used by FreeRTOS+ components into projdefs.h.
+	+ Remove the restriction that prevented tick-less idle implementations
+	  waiting indefinitely when software timers were used in the same
+	  application.
+	+ Introduce xTaskNotifyAndQueryFromISR() as the interrupt safe version of
+	  xTaskNotifyAndQuery().
+	+ Add additional NOPs to the MSP430X port layers to ensure strict compliance
+	  with the hardware documentation.
+	+ Microblaze port: Added option for port optimised task selection.
+	+ Microblaze port: Previously tasks inherited the exception enable state
+	  at the time the task was created.  Now all tasks are created with
+	  exceptions enabled if the Microblaze design supports exceptions.
+	+ Windows port: Add additional safe guards to ensure the correct start up
+	  sequence and thread switching timing.
+	+ Windows port: Improve the implementation of the port optimised task
+	  selection assembly code.
+	+ Update heap_4 and heap_5 to allow use on 64-bit processors.
+	+ Simplify the code that creates a queue.
+	+ General improved tick-less idle behaviour.
+	+ Ensure none of the variables in the common kernel files are initialised to
+	  anything other than zero.
+	+ Correct calculation of xHeapStructSize in heap_4 and heap_5.
+
+	Demo application updates:
+
+	+ Added demo project for the new IA32/x86 port that targets the Galileo
+	  hardware.
+	+ Added MSP430FR5969 demos (previously provided as a separate download).
+	+ Added FreeRTOS BSP repository for automatic creation of FreeRTOS
+	  applications in the Xilinx SDK.
+	+ Added Atmel Studio / GCC project for the SAMV71 (ARM Cortex-M7)
+	+ Update Xilinx SDK projects to use version 2015.2 of the SDK.
+	+ Remove Microblaze demos that were using obsolete tools.
+	+ Add MSP43FR5969 IAR and CCS demos.
+
+	FreeRTOS+ Updates:
+
+	+ Updated FreeRTOS+Trace recorder library, which requires an update to the
+	  FreeRTOS+Trace application.
+	+ Added Reliance Edge source code and demo application.  Reliance edge is
+	  a fail safe transactional file system ideal for applications that require
+	  file storage, and especially when high reliability is essential.
+	+ Introduce configAPPLICATION_PROVIDES_cOutputBuffer to allow FreeRTOS+CLI
+	  users to place the output buffer at a fixed memory address.
+	+ Improve the NetworkInterface.c file provided for the Windows port of
+	  FreeRTOS+UDP.
+
+Changes between V8.2.0 and V8.2.1 released 24th March 2015.
+
+	RTOS kernel updates:
+
+	+ Added user definable and flexible thread local storage facility.
+	+ Added vTimerSetTimerID() API function to complement the pvTimerGetTimerID()
+	  function to allow the timer's ID to be used as timer local storage.
+	+ Fixed a potential issue related to the use of queue sets from an ISR.
+	+ Some updates to the Xilinx Microblaze GCC port.
+	+ Added ARM Cortex-M4F port for Texas Instruments Code Composer Studio.
+	+ Added ARM Cortex-M7 r0p1 port layer for IAR, GCC and Keil which contains a
+	  minor errata work around.  All other ARM Cortex-M7 core revisions should
+	  use the ARM Cortex-M4F port.
+	+ Exclude the whole of croutine.c if configUSE_CO_ROUTINES is set to 0.
+	+ Change some data types from uint32_t to size_t in preparation for 64-bit
+	  Windows port.
+	+ Update the PIC32 port to remove deprecation warnings output by the latest
+	  XC32 compilers.
+	+ Fix bug when xQueueOverwrite() and xQueueOverwrite() from ISR are used to
+	  overwrite items in two queues that are part of the same set.
+
+	Demo application updates:
+
+	+ Added demo application for TI's ARM Cortex-M4F based MSP432
+	  microcontroller using IAR, Keil and CCS compilers.
+	+ Added demo application for STM32F ARM Cortex-M7 based microcontroller
+	  using IAR and Keil.
+	+ Added demo application for Atmel SAMV71 ARM Cortex-M7 based
+	  microcontroller using IAR and Keil.
+	+ Added Microblaze demo that uses the 2014.4 version of the Xilinx SDK and
+	  runs on the KC705 evaluation board (Kintex FPGA).
+
+Changes between V8.1.2 and V8.2.0 released 16th January 2015
+
+	Changes between release candidate 1 and the official release are restricted
+	to maintenance only.
+
+	Significant RTOS kernel updates:
+
+	+ MAJOR NEW FEATURE!  Task notifications.  Please see the following URL for
+	  details: https://www.FreeRTOS.org/RTOS-task-notifications.html
+	+ NEW HEADER FILE REQUIRED!  Obsolete definitions have been separated into
+	  a new header file called FreeRTOS/Source/include/deprecated_definitions.h.
+	  This header file must be present to build.  Note some of the obsolete
+	  definitions are still used by very old demo application projects.
+
+	Other RTOS kernel updates:
+
+	+ Made xSemaphoreGiveFromISR() a function rather than a macro that calls
+	  xQueueGenericSendFromISR().  This allows for major performance
+	  enhancements at the expense of some additional code size if both functions
+	  are used in the same application.  NOTE:  In most uses cases such use of
+	  a semaphore can now be replaced with a task notification which is smaller
+	  and faster still.
+	+ The TCB is now always allocated such that the task's stack grows away from
+	  the TCB (improves debugging of stack overflows as the overflow will not
+	  overwrite the task's name).
+	+ GCC, IAR and Keil Cortex-M4F ports now use more inlining (performance
+	  enhancements at the cost of a little additional code space).
+	+ Queues are now allocated with a single call to pvPortMalloc() which
+	  allocates both the queue structure and the queue storage area.
+	+ Introduced a new critical section macro for reading the tick count that
+	  defines away to nothing in cases where the width of the tick allows the
+	  tick count to be read atomically (performance benefits - especially when
+	  optimisation is on).
+	+ Introduced configAPPLICATION_ALLOCATED_HEAP in heap_4.c to allow the
+	  application writer to provide their own heap array - and in so doing
+	  control the location of the heap.
+	+ Introduced configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES which, when set, will
+	  include known values in both list and list item structures.  The values
+	  are intended to assist debugging.  If the values get overwritten then it
+	  is likely application code has written over RAM used by the kernel.
+	+ configASSERT()s in all Cortex-M ports used to test the lowest 5 bits of
+	  the interrupt control register to detect taskENTER_CRITICAL() being called
+	  from an interrupt.  This has been changed to test all 8 bits.
+	+ Introduced uxTaskPriorityGetFromISR().
+	+ Microblze V8 port now tests XPAR_MICROBLAZE_0_USE_FPU for inequality to 0
+	  rather than equality to 1, and 2 and 3 are also valid values.
+	+ Cortex-A5 GIC-less port no longer passes the address of the interrupting
+	  peripheral into the interrupt handler.
+	+ Fix an issue in FreeRTOS-MPU where an attempt was made to free the stack
+	  belonging to a task when the task was deleted, even when the stack was
+	  allocated statically.
+	+ Utility (helper) functions that format task statistic information into
+	  human readable tables now pad task names with spaces to ensure columns
+	  line up correctly even where task name lengths vary greatly.
+	+ Update FreeRTOS+Trace recorder library to version 2.7.0.
+
+	Demo application updates:
+
+	+ Added two new standard demo task sets:  IntSemTest and TaskNotify.
+	+ Added port and demo application for Atmel SAMA5D4 Cortex-A5 MPU.
+	+ Added demo application for Altera Cyclone V Cortex-A9 MPU.
+	+ Updated Zynq demo to use version 2014.4 of Xilinx's SDK and added in
+	  demo tasks for new RTOS features.
+	+ Updated Atmel SAM4E and SAM4S demos to include a lot of additional test
+	  and demo tasks.
+	+ Fixed a corner case issue in Atmel SAM4L low power tickless
+	  implementation, and added button interrupt handling.
+	+ Make the interrupt queue tests more tolerant to heave CPU loads.
+	+ Updated MSVC FreeRTOS simulator demo to include the latest standard test
+	  and demo tasks.
+	+ Updated MingW/Eclipse FreeRTOS simulator demo to match the FreeRTOS MSVC
+	  simulator demo.
+	+ Updated all demos that use FreeRTOS+Trace to work with the latest trace
+	  recorder code.
+
+
+Changes between V8.1.1 and V8.1.2 released September 2nd 2014
+
+	Move the defaulting of configUSE_PORT_OPTIMISED_TASK_SELECTION into the
+	individual port layers where necessary so it does not affect ports that do
+	not support the definition.
+
+Changes between V8.1.0 and V8.1.1 released August 29th 2014
+
+	By popular requests - a minor patch to V8.1.0 to re-instate the ability to
+	give a mutex type semaphore (with priority inheritance) from an interrupt
+	handler.
+
+Changes between V8.0.1 and V8.1.0 released August 26th 2014
+
+	FreeRTOS scheduler, kernel, demo and test updates:
+
+	+ Improved the priority inheritance algorithms to assist integration with
+	  off the shelf middleware that may hold multiple mutexes simultaneously.
+	+ Introduce heap_5.c, which is similar to heap_4.c but allows the heap to
+	  span multiple non-contiguous memory regions.
+	+ Updated all Cortex-A9 ports to help trap a couple of common usage errors -
+	  the first being when a task incorrectly attempts to exit its implementing
+	  function and the second being when a non interrupt safe API function is
+	  called from an interrupt.
+	+ Update all Cortex-A9 ports to remove obsolete mode switches prior to
+	  restoring a task context.
+	+ configUSE_PORT_OPTIMISED_TASK_SELECTION now defaults to 1 instead of 0.
+	+ Update all Cortex-M3/4F ports to trap a non interrupt safe API function
+	  being called from an interrupt handler.
+	+ Simplify the alignment checks in heap_4.c.
+	+ Update the MSVC Windows simulator demo to use heap_5.c in place of
+	  heap_4.c to ensure end users have an example to refer to.
+	+ Updated standard demo test code to test the new priority inheritance
+	  algorithms.
+	+ Updated the standard demo tasks to make use of stdint and the FreeRTOS
+	  specific typedefs that were introduced in FreeRTOS V8.0.0.
+	+ Introduce the pdMS_TO_TICKS() macro as a more user friendly and intuitive
+	  alternative to pdTICKS_PER_MS - both of which can be used to convert a
+	  time specified in milliseconds to a time specified in RTOS ticks.
+	+ Fix a bug in the Tasking compiler's Cortex-M port that resulted in an
+	  incorrect value being written to the basepri register.  This only effects
+	  users of the Tasking compiler.
+	+ Update the Zynq demo to use version 2014.2 of the SDK and add in an lwIP
+	  example that demonstrates lwIP being used with both its raw and sockets
+	  interfaces.
+	+ Updated the CCS Cortex-R4 port to enable it to be built with the latest
+	  CCS compiler.
+
+	New ports and demo applications:
+
+	+ Two Renesas RX64M ports (RXv2 core) and demos introduced, one for the GCC
+	  compiler and one for the Renesas compiler.  Both demos use e2 studio.
+	+ Generic IAR Cortex-A5 port (without any reliance on a GIC) introduced.
+	  The new port is demonstrated on an Atmel SAMA5D3 XPlained board.
+
+	FreeRTOS+ component updates:
+
+	+ Update CyaSSL to the latest version.
+	+ Updated the FreeRTOS+ components supplied directly by Real Time Engineers
+	  Ltd. to make use of stdint and the FreeRTOS specific typedefs that were
+	  introduced in FreeRTOS V8.0.0.
+	+ Rework and simplify the FreeRTOS+FAT SL RAM disk driver.
+
+	Miscellaneous updates and maintenance:
+
+	+ Update the IAR and DS-5/ARM RZ demos to target the official RZ RSK
+	  hardware in place of the previously targeted Renesas internal (not
+	  publicly available) hardware.
+	+ Various other maintenance tasks.
+
+
+Changes between V8.0.0 and V8.0.1 released 2nd May 2014
+
+	+ Minor fixes to the event group functionality that was released in V8.0.0.
+	  The 'clear bits from ISR' functionality is now implemented using a
+	  deferred interrupt callback instead of a function, and the 'wait bits' and
+	  'task sync' functions now correctly clear internal control bits before
+	  returning a value in every possible path through the respective functions.
+	+ Ensure the updating of internal control data is protected by a critical
+	  section after a task is deleted or suspended.
+	+ Minor fixes to FreeRTOS+FAT SL - namely seeking beyond the end of a file
+	  when the offset was not a multiple of the sector size.
+	+ Ensure Cortex-A9 system registers are only ever accessed as 32-bit values,
+	  even when only the lest significant byte of the register is implemented.
+
+	Other updates:
+
+	+ Updated the XMC4200 IAR project so it links with version 7.x of the IAR
+	  tools.
+	+ Add RL78L1C demo.
+	+ Add pcTimerGetName() API function.
+	+ Call _reclaim_reent() when a task is deleted if configUSE_NEWLIB_REENTRANT
+	  is defined.
+
+Changes between V7.6.0 and V8.0.0 released 19th Feb 2014
+
+	https://www.FreeRTOS.org/upgrading-to-FreeRTOS-V8.html
+
+	FreeRTOS V8.x.x is a drop-in compatible replacement for FreeRTOS V7.x.x,
+	although a change to the type used to reference character strings may result
+	in application code generating a few (easily clearable) compiler warnings
+	after the upgrade, and an updated typedef naming convention means use of the
+	old typedef names is now discouraged.
+	See https://www.FreeRTOS.org/upgrading-to-FreeRTOS-V8.html for full
+	information.
+
+	New features and functionality:
+
+	+ Event groups - see https://www.FreeRTOS.org/FreeRTOS-Event-Groups.html
+	+ Centralised deferred interrupt processing - see
+	  https://www.FreeRTOS.org/xTimerPendFunctionCallFromISR.html
+
+	Other updates:
+
+	+ Previously, when a task left the Blocked state, a context switch was
+	  performed if the priority of the unblocked task was greater than or equal
+	  to the priority of the Running task.  Now a context switch is only
+	  performed if the priority of the unblocked task is greater than the
+	  priority of the Running task.
+	+ New low power tickless demonstration project that targets the ST STM32L
+	  microcontroller - see
+	  https://www.FreeRTOS.org/STM32L-discovery-low-power-tickless-RTOS-demo.html
+	+ Add xPortGetMinimumEverFreeHeapSize() to heap_4.c.
+	+ Small change to the tickless low power implementation on the SAM4L to
+	  ensure the alarm value (compare match value) cannot be set to zero when a
+	  tickless period is exited due to an interrupt originating from a source
+	  other than the RTOS tick.
+	+ Update the GCC/Eclipse Win32 simulator demo to make better use of Eclipse
+	  resource filters and match the functionality of the MSVC equivalent.
+	+ xTaskIsTaskSuspended() is no longer a public function.  Use
+	  eTaskGetState() in its place.
+	+ Improved trace macros, including tracing of heap usage.
+	+ Remove one level of indirection when accepting interrupts on the PIC32MZ.
+	+ Add Cortex-A9 GCC port layer.
+	+ Add Xilinx Zynq demo application.
+
+
+Changes between V7.5.3 and V7.6.0 released 18th November 2013
+
+	V7.6.0 changes some behaviour when the co-operative scheduler is used (when
+	configUSE_PREEMPTION is set to 0).  It is important to note that the
+	behaviour of the pre-emptive scheduler is unchanged - the following
+	description only applies when configUSE_PREEMPTION is set to 0:
+
+	WHEN configUSE_PREEMPTION IS SET TO 0 (which is in a small minority of
+	cases) a context switch will now only occur when a task places itself into
+	the Blocked state, or explicitly calls taskYIELD().  This differs from
+	previous versions, where a context switch would also occur when implicitly
+	moving a higher priority task out of the Blocked state.  For example,
+	previously, WHEN PREEMPTION WAS TURNED OFF, if task A unblocks task B by
+	writing to a queue, then the scheduler would switch to the higher priority
+	task.  Now, WHEN PREEMPTION IS TURNED OFF, if task A unblocks task B by
+	writing to a queue, task B will not start running until task A enters the
+	Blocked state or task A calls taskYIELD().  [If configUSE_PREEMPTION is not
+	set to 0, so the normal pre-emptive scheduler is being used, then task B
+	will start running immediately that it is moved out of the Blocked state].
+
+	Other changes:
+
+	+ Added a port layer and a demo project for the new PIC32MZ architecture.
+	+ Update the PIC32MX port layer to re-introduce some ehb instructions that
+	  were previously removed, add the ability to catch interrupt stack
+	  overflows (previously only task stack overflows were trapped), and also
+	  add the ability to catch an application task incorrectly attempting to
+	  return from its implementing function.
+	+ Make dramatic improvements to the performance of the Win32 simulator port
+	  layer.
+	+ Ensure tasks that are blocked indefinitely report their state as Blocked
+	  instead of Suspended.
+	+ Slight improvement to the Cortex-M4F port layers where previously one
+	  register was inadvertently being saved twice.
+	+ Introduce the xSemaphoreCreateBinary() API function to ensure consistency
+	  in the semantics of how each semaphore type is created.  It is no longer
+	  recommended to use vSemaphoreCreateBinary() (the version prefixed with a
+	  'v'), although it will remain in the code for backward compatibility.
+	+ Update the Cortex-M0 port layers to allow the scheduler to be started
+	  without using the SVC handler.
+	+ Added a build configuration to the PIC32MX MPLAB X demo project that
+	  targets the PIC32 USB II starter kit.  Previously all the build
+	  configurations required the Explorer 16 hardware.
+	+ Some of the standard demo tasks have been updated to ensure they execute
+	  correctly with the updated co-operative scheduling behaviour.
+	+ Added comprehensive demo for the Atmel SAM4E, including use of
+	  FreeRTOS+UDP, FreeRTOS+FAT SL and FreeRTOS+CLI.
+
+	FreeRTOS+ Changes:
+
+	+ Minor maintenance on FreeRTOS+UDP.
+
+Changes between V7.5.2 and V7.5.3 released October 14 2013
+
+	Kernel changes:
+
+	+ Prior to V7.5.x yields requested from the tick hook would occur in the
+	  same tick interrupt - revert to that original behaviour.
+	+ New API function uxQueueSpacesAvailable().
+	+ Introduced the prvTaskExitError() function to Cortex-M0, Cortex-M3/4
+	  and Cortex-M4F ports.  prvTaskExitError() is used to trap tasks that
+	  attempt to return from their implementing functions (tasks should call
+	  vTaskDelete( NULL ); if they want to exit).
+	+ The Cortex-M0 version of portSET_INTERRUPT_MASK_FROM_ISR and
+	  portCLEAR_INTERRUPT_MASK_FROM_ISR are now fully nestable.
+	+ Improved behaviour and robustness of the default Cortex-M tickless idle
+	  behaviour.
+	+ Add workaround for silicon errata PMU_CM001 in Infineon XMC4000 devices to
+	  all Cortex-M4F ports.
+	+ Add Cortex-M0 port for Keil.
+	+ Updated Cortus port.
+	+ Ensure _impure_ptr is initialised before the scheduler is started.
+	  Previously it was not set until the first context switch.
+
+	FreeRTOS+ changes:
+
+	+ Update FreeRTOS+UDP to V1.0.1 - including direct integration of the
+	  FreeRTOS+Nabto task, improvements to the DHCP behaviour, and a correction
+	  to the test that prevents the network event hook being called on the first
+	  network down event.  The FreeRTOS+UDP change history is maintained
+	  separately.
+	+ Correct the __NVIC_PRIO_BITS setting in the LPC18xx.h header files
+	  provided in the NXP CMSIS library, then update the interrupts used by the
+	  LPC18xx demos accordingly.
+	+ Replace double quotes (") with single quotes (') in FreeRTOS+CLI help
+	  strings to ensure the strings can be used with the JSON descriptions used
+	  in the FreeRTOS+Nabto demos.
+
+	Demo and miscellaneous changes:
+
+	+ Added demo for the Atmel SAMD20 Cortex-M0+.  The demo includes
+	  FreeRTOS+CLI
+	+ Added a demo for the Infineon Cortex-M0 that can be built with the IAR
+	  Keil and GCC tools.
+	+ Updated the Infineon XMC4000 demos for IAR, Keil, GCC and Tasking tools,
+	  with additional build configurations to directly support the XMC4200 and
+	  XMC4400 devices, in addition to the previously supported XMC4500.
+	+ Updated the demo application.
+	+ Added additional trace macros traceMALLOC and traceFREE to track heap
+	  usage.
+
+Changes between V7.5.0 and V7.5.2 released July 24 2013
+
+	V7.5.2 makes the new Cortex-M vPortCheckInterruptPriority() function
+	compatible with the STM32 standard peripheral driver library, and adds
+	an extra critical section to the default low power tickless mode
+	implementation.  Only users of the STM32 peripheral library or the default
+	tickless implementation need update from version 7.5.0.
+
+Changes between V7.4.2 and V7.5.0 released July 19 2013
+
+	V7.5.0 is a major upgrade that includes multiple scheduling and efficiency
+	improvements, and some new API functions.
+
+	Compatibility information for FreeRTOS users:
+	  FreeRTOS V7.5.0 is backward compatible with FreeRTOS V7.4.0 with one
+	  exception; the vTaskList() and vTaskGetRunTimeStats() functions are now
+	  considered legacy, having been replaced by the single uxTaskGetSystemState()
+	  function.  configUSE_STATS_FORMATTING_FUNCTIONS must be set to 1 in
+	  FreeRTOSConfig.h for vTaskList() and vTaskGetRunTimeStats() to be
+	  available.
+
+	Compatibility information for FreeRTOS port writers:
+	  vTaskIncrementTick() is now called xTaskIncrementTick() (because it now
+	  returns a value).
+
+	Headline changes:
+
+	+ Multiple scheduling and efficiency improvements.
+	+ Core kernel files now pass PC-Lint V8 static checking without outputting
+	  any warnings (information on the test conditions will follow).
+
+	New API functions:
+
+	+ uxTaskGetSystemState() https://www.FreeRTOS.org/uxTaskGetSystemState.html
+	+ xQueueOverwrite() https://www.FreeRTOS.org/xQueueOverwrite.html
+	+ xQueueOverwriteFromISR()
+	+ xQueuePeekFromISR()
+
+	The following ports and demos, which were previously available separately,
+	are now incorporated into the main FreeRTOS zip file download:
+
+	+ ARM Cortex-A9 IAR
+	+ ARM Cortex-A9 ARM compiler
+	+ Renesas RZ
+	+ Microsemi SmartFusion2
+
+	New FreeRTOSConfig.h settings
+	https://freertos.org/a00110.html
+
+	+ configUSE_TIME_SLICING
+	+ configUSE_NEWLIB_REENTRANT
+	+ configUSE_STATS_FORMATTING_FUNCTIONS
+	+ configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
+
+	Other changes:
+
+	+ (MPU port only) The configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
+	  options provides a mechanism that allows application writers to execute
+	  certain functions in privileged mode even when a task is running in user
+	  mode.
+	+ Ports that support interrupt nesting now include a configASSERT() that
+	  will trigger if an interrupt safe FreeRTOS function is called from an
+	  interrupt that has a priority designated as above the maximum system/API
+	  call interrupt priority.
+	+ The included FreeRTOS+Trace recorder code has been updated to the latest
+	  version, and the demo applications that use the trace recorder code have
+	  been updated accordingly.
+	+ The FreeRTOS Windows Simulator (MSVC version only) has been updated to
+	  include a new basic 'blinky' build option in addition to the original
+	  comprehensive build option.
+	+ Improve RAM usage efficiency of heap_4.c and heap_2.c.
+	+ Prevent heap_4.c from attempting to free memory blocks that were not
+	  allocated by heap_4.c, or have already been freed.
+	+ As FreeRTOS now comes with FreeRTOS+FAT SL (donated by HCC) the Chan FATfs
+	  files have been removed from FreeRTOS/Demo/Common.
+	+ Fix build error when R4 port is build in co-operative mode.
+	+ Multiple port and demo application maintenance activities.
+
+Changes between V7.4.1 and V7.4.2 released May 1 2013
+
+	NOTE: There are no changes in the FreeRTOS kernel between V7.4.1 and V7.4.2
+
+	+ Added FreeRTOS+FAT SL source code and demo project.  The demo project
+	  runs in the FreeRTOS Windows simulator for easy and hardware independent
+	  experimentation and evaluation.  See https://www.FreeRTOS.org/fat_sl
+
+Changes between V7.4.0 and V7.4.1 released April 18 2013
+
+	+ To ensure strict conformance with the spec and ensure compatibility with
+	  future chips data and instruction barrier instructions have been added to
+	  the yield macros of Cortex-M and Cortex-R port layers.  For efficiency
+	  the Cortex-M port layer "yield" and "yield" from ISR are now implemented
+	  separately as the barrier instructions are not required in the ISR case.
+	+ Added FreeRTOS+UDP into main download.
+	+ Reorganised the FreeRTOS+ directory so it now matches the FreeRTOS
+	  directory with Source and Demo subdirectories.
+	+ Implemented the Berkeley sockets select() function in FreeRTOS+UDP.
+	+ Changed (unsigned) casting in calls to standard library functions with
+	  (size_t) casting.
+	+ Added the Atmel SAM4L and Renesas RX100 demos that demonstrates the
+	  tickless (tick suppression) low power FreeRTOS features.
+	+ Add a new RL78 IAR demo that targets numerous new RL78 chips and
+	  evaluation boards.
+	+ Adjusted stack alignment on RX200 ports to ensure an assert was not
+	  falsely triggered when configASSERT() is defined.
+	+ Updated the Cortex_M4F_Infineon_XMC4500_IAR demo to build with the latest
+	  version of EWARM.
+	+ Corrected header comments in the het.c and het.h files (RM48/TMS570 demo).
+
+
+Changes between V7.3.0 and V7.4.0 released February 20 2013
+
+	+ New feature:  Queue sets.  See:
+	  https://www.FreeRTOS.org/Pend-on-multiple-rtos-objects.html
+	+ Overhauled the default tickless idle mode implementation provided with the
+	  ARM Cortex-M3 port layers.
+	+ Enhanced tickless support in the core kernel code with the introduction of
+	  the configEXPECTED_IDLE_TIME_BEFORE_SLEEP macro and the
+	  eTaskConfirmSleepModeStatus() function.
+	+ Added the QueueSet.c common demo/test file.  Several demo applications
+	  have been updated to use the new demo/test tasks.
+	+ Removed reliance on the PLIB libraries from the MPLAB PIC32 port layer and
+	  demo applications.
+	+ Added the FreeRTOS+Trace recorder code to the MSVC Win32 demo.
+	+ Renamed eTaskStateGet() to eTaskGetState() for consistency, and added a
+	  pre-processor macro for backward compatibility with the previous name.
+	+ Updated functions implemented in the core queue.c source file to allow
+	  queue.h to be included from the .c file directly (this prevents compiler
+	  warnings that were generated by some compilers).
+	+ Updated the CCS Cortex-R4 port layer to replace the CLZ assembler function
+	  with the CLZ compiler intrinsic that is provided by the latest versions of
+	  the CCS ARM compiler.
+	+ Updated all heap_x.c implementations to replace the structure that was
+	  used to ensure the start of the heap was aligned with a more portable
+	  direct C code implementation.
+	+ Added support for PIC24 devices that include EDS.
+	+ Minor optimisations to the PIC32 port layer.
+	+ Minor changes to tasks.c that allow the state viewer plug-ins to display
+	  additional information.
+	+ Bug fix:  Update prvProcessReceivedCommands() in timers.c to remove an
+	  issue that could occur if the priority of the timer daemon task was set
+	  below the priority of tasks that used timer services.
+	+ Update the FreeRTOS+Trace recorder code to the latest version.
+
+Changes between V7.2.0 and V7.3.0 released October 31 2012
+
+	+ Added ability to override the default scheduler task selection mechanism
+	  with implementations that make use of architecture specific instructions.
+	+ Added ability to suppress tick interrupts during idle time, and in so
+	  doing, provide the ability to make use of architecture specific low power
+	  functionality.
+	+ Added the portSUPPRESS_TICKS_AND_SLEEP() macro and vTaskStepTick() helper
+	  function.
+	+ Added the configSYSTICK_CLOCK_HZ configuration constant.
+	+ Reworked the Cortex-M3 and Cortex-M4F port layers for GCC, Keil and IAR to
+	  directly support basic power saving functionality.
+	+ Added hooks to allow basic power saving to be augmented in the application
+	  by making use of chip specific functionality.
+	+ Minor change to allow mutex type semaphores to be used from interrupts
+	  (which would not be a normal usage model for a mutex).
+	+ Change the behaviour of the interrupt safe interrupt mask save and restore
+	  macros in the Cortex-M ports.  The save macro now returns the previous
+	  mask value.  The restore macro now uses the previous mask value.  These
+	  changes are not necessary for the kernel's own implementation, and are
+	  made purely because the macros were being used by application writers.
+	+ Added eTaskStateGet() API function.
+	+ Added port specific optimisations to the PIC32 port layer, and updated the
+	  PIC32 demo applications to make use of this new feature.
+	+ Added port specific optimisations to the Win32 simulator port.
+	+ Added new ports and demo applications for the TI Hercules RM48 and TMS570
+	  safety microcontrollers.
+	+ Added SAM3 demos targeting the ATSAM3S-EK2 and ATSAM3X-EK evaluation
+	  boards.
+	+ Updated the PIC32 MPLAB X project to manually set the compiler include
+	  paths instead of using the IDE entry box following reports that the
+	  include paths were somehow being deleted.
+	+ Improved character handling in FreeRTOS+CLI.
+
+Changes between V7.1.1 and V7.2.0 released 14 August 2012
+
+	FreeRTOS V7.2.0 is backward compatible with FreeRTOS V7.1.2.
+
+	+ Added a FreeRTOS+ sub-directory.  The directory contains some FreeRTOS+
+	  source code, and example projects that use the FreeRTOS Win32 simulator.
+	+ Added a new example heap allocation implementation (heap_4.c) that
+	  includes memory block coalescence.
+	+ Added a demo that targets the Atmel SAM4S Cortex-M4 based microcontroller.
+	  The demo is preconfigured to build using the free Atmel Studio 6 IDE and
+	  GCC compiler.
+	+ Added xSemaphoreTakeFromISR() implementation.
+	+ The last parameter in ISR safe FreeRTOS queue and semaphore functions
+	  (xHigherPriorityTaskWoken) is now optional and can be set to NULL if it
+	  is not required.
+	+ Update the IAR and MSP430X ports to clear all lower power mode bits before
+	  exiting the tick interrupt [bug fix].
+	+ Allow xQueueReset() to be used, even when the queues event lists are not
+	  empty.
+	+ Added a vQueueDelete() handler for the FreeRTOS MPU port (this was
+	  previously missing).
+	+ Updated the vPortSVCHandler() functions in the FreeRTOS MPU port layer to
+	  ensure it compiles with the latest ARM GCC compilers from Linaro.
+	+ Updated the prvReadGP() function in the NIOS II port to ensure the compiler
+	  can choose any register for the functions parameter (required at high
+	  compiler optimisation levels).
+	+ Add #error macros into the Keil and IAR Cortex-M ports to ensure they
+	  cannot be built if the user has set configMAX_SYSCALL_INTERRUPT_PRIORITY
+	  to 0.
+	+ Added comments in the FreeRTOSConfig.h files associated with Cortex-M3 and
+	  Cortex-M4 demos stating that the configMAX_SYSCALL_INTERRUPT_PRIORITY
+	  parameter must not be set to 0.
+	+ Introduce new INCLUDE_xQueueGetMutexHolder configuration constant
+	  (defaulted to 0).
+	+ Added two new list handling macros - for internal use only in upcoming new
+	  products.
+	+ Removed all mention of the legacy vTaskStartTrace and ulTaskEndTrace
+	  macros.  FreeRTOS+Trace supersedes the legacy trace.
+	+ Added a configASSERT() into the vPortFree() function in heap_1.c as it is
+	  invalid for the function to be called.
+	+ Made the xRxLock and xTxLock members of the queue structure volatile.
+	  This is probably not necessary, and is included as a precautionary
+	  measure.
+	+ Modify the assert() that checks to see if the priority passed into an
+	  xTaskCreate() function is within valid bounds to permit the assert to be
+	  used in the FreeRTOS MPU port.
+	+ The software timer service (daemon) task is now created in a way that
+	  to ensure compatibility with FreeRTOS MPU.
+
+Changes between V7.1.0 and V7.1.1 released May 1 2012
+
+	New ports:
+
+	The following ports are brand new:
+	+ Cortex-M3 Tasking
+
+	The following ports have been available as separate downloads for a number
+	of months, but are now included in the main FreeRTOS download.
+	+ Cortex-M0 IAR
+	+ Cortex-M0 GCC
+	+ Cortex-M4F GCC (with full floating point support)
+
+
+	New demos:
+
+	The following demos are brand new:
+	+ Renesas RX63N RDK (Renesas compiler)
+
+	The following demos have been available as separate downloads for a number
+	of months, but are now included in the main FreeRTOS download.
+	+ NXP LPC1114 GCC/LPCXpresso
+	+ ST STM32F0518 IAR
+	+ Infineon XMC4500 GCC/Atollic
+	+ Infineon XMC4500 IAR
+	+ Infineon XMC4500 Keil
+	+ Infineon XMC4500 Tasking
+
+
+	Kernel miscellaneous / maintenance:
+
+	+ Introduced the portSETUP_TCB() macro to remove the requirement for the
+	  Windows simulator to use the traceTASK_CREATE() macro, leaving the trace
+	  macro available for use by FreeRTOS+Trace (https://www.FreeRTOS.org/trace).
+	+ Added a new trace macro, traceMOVE_TASK_TO_READY_STATE(), to allow future
+	  FreeRTOS+Trace versions to provide even more information to users.
+	+ Updated the FreeRTOS MPU port to be correct for changes that were
+	  introduced in FreeRTOS V7.1.0.
+	+ Introduced the xQueueReset() API function.
+	+ Introduced the xSemaphoreGetMutexHolder() API function.
+	+ Tidy up various port implementations to add the static key word where
+	  appropriate, and remove obsolete code.
+	+ Slight change to the initial stack frame given to the RX600 ports to allow
+	  them to be used in the Eclipse based E2Studio IDE without confusing GDB.
+	+ Correct the alignment given to the initial stack of Cortex-M4F tasks.
+	+ Added a NOP following each DINT instruction on MSP430 devices for strict
+	  conformance with the instructions on using DINT.
+	+ Changed the implementation of thread deletes in the Win32 port to prevent
+	  the port making use of the traceTASK_DELETE() trace macros - leaving this
+	  macro free for use by FreeRTOS+Trace.
+	+ Made some benign changes to the RX600 Renesas compiler port layer to
+	  ensure the code can be built to a library without essential code being
+	  removed by the linker.
+	+ Reverted the change in the name of the uxTaskNumber variable made in
+	  V7.1.0 as it broke the IAR plug-in.
+
+
+	Demo miscellaneous / maintenance:
+
+	+ The command interpreter has now been formally released as FreeRTOS+CLI,
+	  and been moved out of the main FreeRTOS download, to instead be available
+	  from the FreeRTOS+ Ecosystem site https://www.FreeRTOS.org/plus.
+	+ flash_timer.c/h has been added to the list of standard demo tasks.  This
+	  performs the same functionality as the flash.c tasks, but using software
+	  timers in place of tasks.
+	+ Upgraded the PIC32 demo as follows:  Changes to how the library functions
+	  are called necessitated by the new compiler version, addition of MPLAB X
+	  project with PIC32MX360, PIC32MX460 and PIC32MX795 configurations,
+	  addition of simply blinky demo, updated FreeRTOSConfig.h to include more
+	  parameters, addition of hook function stubs.
+	+ The MSP430X IAR and CCS demos have been updated to ensure the power
+	  settings are correct for the configured CPU frequency.
+	+ Rowley CrossWorks projects have been updated to correct the "multiple
+	  definition of ..." warnings introduced when the toolchain was updated.
+	+ Updated various FreeRTOSConfig.h header files associated with projects
+	  that build with Eclipse to include a #error statement informing the user
+	  that the CreateProjectDirectoryStructure.bat batch file needs to be
+	  executed before the projects can be opened.
+	+ Renamed directories that included "CCS4" in their name to remove the '4'
+	  and instead just be "CCS".  This is because the demo was updated and
+	  tested to also work with later Code Composer Studio versions.
+	+ Updated the TCP/IP periodic timer frequency in numerous uIP demos to be
+	  50ms instead of 500ms.
+
+Changes between V7.0.2 and V7.1.0 released December 13 2011
+
+	New ports:
+
+	+ Cortex-M4F IAR port.
+	+ Cortex-M4F Keil/RVDS port.
+	+ TriCore GCC port.
+
+	New demos:
+
+	+ NXP LPC4350 using the Keil MDK, and demonstrated on a Hitex development
+	  board.
+	+ ST STM32F407 using the IAR Embedded Workbench for ARM, and demonstrated on
+	  the IAR STM32F407ZG-SK starter kit.
+	+ Infineon TriCore TC1782, using the GCC compiler, demonstrated on the
+	  TriBoard TC1782 evaluation board.
+	+ Renesas RX630, using the Renesas compiler and HEW, demonstrated on an
+	  RX630 RSK (Renesas Starter Kit).
+
+	Miscellaneous / maintenance:
+
+	+ Removed all calls to printf() from the K60/IAR Kinetis demo so the project
+	  can execute stand alone - without being connected to the debugger.
+	+ Completed the command interpreter framework.  Command handlers now receive
+	  the entire command string, giving them direct access to parameters.
+	  Utility functions are provided to check the number of parameters, and
+	  return parameter sub-strings.
+	+ The previously documented fix for the bug in xTaskResumeFromISR() that
+	  effected (only) ports supporting interrupt nesting has now been
+	  incorporated into the main release.
+	+ The portALIGNMENT_ASSERT_pxCurrentTCB() definition has been added to allow
+	  specific ports to skip the second stack alignment check when a task is
+	  created.  This is because the second check is not appropriate for some
+	  ports - including the new TriCore port where the checked pointer does not
+	  actually point to a stack.
+	+ The portCLEAN_UP_TCB() macro has been added to allow port specific clean
+	  up when a task is deleted - again this is required by the TriCore port.
+	+ Various other minor changes to ensure warning free builds on a growing
+	  number of microcontroller and toolchain platforms.  This includes a
+	  (benign) correction to the prototype of the
+	  vApplicationStackOverflowHook() definition found in lots of recent demos.
+
+	Trace system:
+
+	+ The legacy trace mechanism has been completely removed - it has been
+	  obsolete for the years since the trace macros were introduced.  The
+	  configuration constant configUSE_TRACE_FACILITY is now used to optionally
+	  include additional queue and task information.  The additional information
+	  is intended to make the trace mechanism more generic, and allow the trace
+	  output to provide more information.  When configUSE_TRACE_FACILITY is set
+	  to 1:
+		- the queue structure includes an additional member to hold the queue
+		  type, which can be base, mutex, counting semaphore, binary semaphore
+		  or recursive mutex.
+		- the queue structure includes an additional member to hold a queue
+		  number.  A trace tool can set and query the queue number for its own
+		  purposes.  The kernel does not use the queue number itself.
+		- the TCB structure includes an additional member to hold a task number
+		  number.  A trace tool can set and query the task number for its own
+		  purposes.  The kernel does not use the task number itself.
+	+ Queues and all types of semaphores are now automatically allocated their
+	  type as they are created.
+	+ Added two new trace macros - traceTASK_PRIORITY_INHERIT() and
+	  traskTASK_PRIORITY_DISINHERIT().
+	+ Updated the traceQUEUE_CREATE_FAILED() macro to take a parameter that
+	  indicates the type of queue, mutex, or semaphore that failed to be
+	  created.
+	+ The position from which traceCREATE_MUTEX() is called has been moved from
+	  after the call to xQueueGenericSend() [within the same function] to before
+	  the call.  This ensures the trace events occur in the correct order.
+	+ The value passed into tracePRIORITY_SET() has been corrected for the case
+	  where vTaskPrioritySet() is called with a null parameter.
+
+Changes between V7.0.1 and V7.0.2 released September 20 2011
+
+	New ports:
+
+	+ The official FreeRTOS Renesas RX200 port and demo application have been
+	  incorporated into the main FreeRTOS zip file download.
+	+ The official FreeRTOS Renesas RL78 port and demo application have been
+	  incorporated into the main FreeRTOS zip file download.
+	+ The official FreeRTOS Freescale Kinetis K60 tower demo application has
+	  been incorporated into the main FreeRTOS zip file download.  This includes
+	  an embedded web server example.
+	+ A new Microblaze V8 port layer has been created to replace the older, now
+	  deprecated, port layer.  The V8 port supports V8.x of the Microblaze IP,
+	  including exceptions, caches, and the floating point unit.  A new
+	  Microblaze demo has also been added to demonstrate the new Microblaze V8
+	  port layer.  The demo application was created using V13.1 of the Xilinx
+	  EDK, and includes a basic embedded web server that uses lwIP V1.4.0.
+	+ The official FreeRTOS Fujitsu FM3 MB9A310 demo application has been
+	  incorporated into the main FreeRTOS zip file download.  Projects are
+	  provided for both the IAR and Keil toolchains.
+
+
+	API additions:
+
+	+ xTaskGetIdleTaskHandle() has been added.
+	+ xTaskGetTimerDaemonTaskHandle() has been added.
+	+ pcTaskGetTaskName() has been added.
+	+ vSemaphoreDelete() macro has been added to make it obvious how to delete
+	  a semaphore.  In previous versions vQueueDelete() had to be used.
+	+ vTaskCleanUpResources() has been removed.  It has been obsolete for a
+	  while.
+	+ portPOINTER_SIZE_TYPE has been introduced to prevent compiler warnings
+	  being generated when the size of a pointer does not match the size of
+	  the stack type.  This will (has already) be used in new ports, but will
+	  not be retrofitted to existing ports until the existing port itself is
+	  updated.
+
+	Other updates and news:
+
+	+ The core files have all been modified to tighten the coding standard even
+	  further.  These are style, not functional changes.
+	+ All ARM7 port layers have been slightly modified to prevent erroneous
+	  assert() failures when tasks are created and configASSERT() is defined.
+	+ All ARM IAR projects have been updated to build with the latest V6.2.x
+	  versions of the IAR Embedded Workbench for ARM tools (EWARM).  This was
+	  necessary due to a change in the way EWARM uses the CMSIS libraries.
+	+ The PIC32 port layer has been updated in preparation for V2 of the C32
+	  compiler.
+	+ The old Virtex-4 Microblaze demo has been marked as deprecated.  Please
+	  use the brand new Spartan-6 port and demo in its place.
+	+ The bones of a new generic command interpreter is located in
+	  FreeRTOS/Demo/Common/Utils/CommandInterpreter.c.  This is still a work in
+	  progress, and not documented.  It is however already in use.  It will be
+	  documented in full when the projects that are already using it are
+	  completed.
+	+ A couple of new standard demos have been included.  First, a version of
+	  flop.c called sp_flop.c.  This is similar to flop.c, but uses single
+	  precision floats in place of double precision doubles.  This allows the
+	  for testing ports to processors that have only single precision floating
+	  point units, and revert to using emulated calculations whenever a double
+	  is used.  Second, comtest_strings.c has been included to allow the test
+	  of UART drivers when an entire string is transmitted at once.  The
+	  previous comtest.c only used single character transmission and reception.
+	+ lwIP V1.4.0 is now included in the FreeRTOS/Demo/Common directory, and
+	  used by a couple of new demos.
+
+Changes between V7.0.0 and V7.0.1 released May 13 2011
+
+	+ Added a Fujitsu FM3 demo application for both the IAR and Keil tool
+	  chains.
+	+ Added a SmartFusion demo application for all of the IAR, Keil and
+	  SoftConsole (GCC/Eclipse) tool chains.
+	+ Updated the RX600 port and demo applications to take into account the
+	  different semantics required when using the latest (V1.0.2.0) version of
+	  the Renesas compiler.
+	+ Modified the RX600 Ethernet driver slightly to make it more robust under
+	  heavy load, and updated the uIP handling task to make use of the FreeRTOS
+	  software timers.
+	+ Slightly changed the PIC32 port layer to move an ehb instruction in line
+	  with the recommendations of the MIPS core manual, and ensure 8 byte stack
+	  alignment is truly always obtained.
+	+ Changed the behaviour when tasks are suspended before the scheduler has
+	  been started.  Before, there needed to be at least one task that was not
+	  in the suspended state.  This is no longer the case.
+
+Changes between V6.1.1 and V7.0.0 released April 8 2011
+
+	FreeRTOS V7.0.0 is backward compatible with FreeRTOS V6.x.x
+
+	Main changes:
+
+	+ Introduced a new software timer implementation.
+	+ Introduced a new common demo application file to exercise the new timer
+	  implementation.
+	+ Updated the Win32/MSVC simulator project to include the new software timer
+	  demo tasks and software timer tick hook test.  Much simpler software timer
+	  demonstrations are included in the demo projects for both of the new ports
+	  (MSP430X with CCS4 and STM32 with TrueStudio).
+	+ Various enhancements to the kernel implementation in tasks.c.  These are
+	  transparent to users and do not effect the pre-existing API.
+	+ Added calls to configASSERT() within the kernel code.  configASSERT() is
+	  functionally equivalent to the standard C assert() macro, but does not
+	  rely on the compiler providing assert.h.
+
+	Other changes:
+
+	+ Updated the MSP430X IAR port and demo project to include support for the
+	  medium memory model.
+	+ Added a demo project for the MSP430X that targets the MSP430X Discovery
+	  board and uses the Code Composer Studio 4 tools.  This demo includes use
+	  of the new software timer implementation.
+	+ Added an STM32F100RB demo project that targets the STM32 Discovery Board
+	  and uses the TrueStudio Eclipse based IDE from Atollic.
+	+ Removed some compiler warnings from the PSoC demo application.
+	+ Updated the PIC32 port layer to ensure the
+	  configMAX_SYSCALL_INTERRUPT_PRIORITY constant works as expected no matter
+	  what its value is (within the valid range set by the microcontroller
+	  kernel).
+	+ Updated the PIC24, dsPIC and PIC32 projects so they work with the latest
+	  MPLAB compiler versions from Microchip.
+	+ Various cosmetic changes to prepare for a standards compliance statement
+	  that will be published after the software release.
+
+
+Changes between V6.1.0 and V6.1.1 released January 14 2011
+
+	+ Added two new Windows simulator ports.  One uses the free Microsoft Visual
+	  Studio 2010 express edition, and the other the free MingW/Eclipse
+	  environment.  Demo projects are provided for both.
+	+ Added three demo projects for the PSoC 5 (CYAC5588).  These are for the
+	  GCC, Keil, and RVDS build tools, and all use the PSoC Creator IDE.
+	+ Added a demo for the low power STM32L152 microcontroller using the IAR
+	  Embedded Workbench.
+	+ Added a new port for the MSP430X core using the IAR Embedded Workbench.
+	+ Updated all the RX62N demo projects that target the Renesas Demonstration
+	  Kit (RDK) to take into account the revered LED wiring on later hardware
+	  revisions, and the new J-Link debug interface DLL.
+	+ Updated all the RX62N demo projects so the IO page served by the example
+	  embedded web server works with all web browsers.
+	+ Updated the Red Suite projects to work with the up coming Red Suite
+	  release, and to use a more recent version of the CMSIS libraries.
+	+ Added the traceTAKE_MUTEX_RECURSIVE_FAILED() trace macro.
+	+ Removed the (pointless) parameter from the traceTASK_CREATE_FAILED()
+	  trace macro.
+	+ Introduced the portALT_GET_RUN_TIME_COUNTER_VALUE() macro to compliment
+	  the already existing portGET_RUN_TIME_COUNTER_VALUE().  This allows for
+	  more flexibility in how the time base for the run time statistics feature
+	  can be implemented.
+	+ Added a "cpsie i" instruction before the "svc 0" instruction used to start
+	  the scheduler in each of the Cortex M3 ports.  This is to ensure that
+	  interrupts are globally enabled prior to the "svc 0" instruction being
+	  executed in cases where interrupts are left disabled by the C start up
+	  code.
+	+ Slight optimisation in the run time stats calculation.
+
+Changes between V6.0.5 and V6.1.0 released October 6 2010
+
+	+ Added xTaskGetTickCountFromISR() function.
+	+ Modified vTaskSuspend() to allow tasks that have just been created to be
+	  immediately suspended even when the kernel has not been started.  This
+	  allows them to effectively start in the Suspended state - a feature that
+	  has been asked for on numerous occasions to assist with initialisation
+	  procedures.
+	+ Added ports for the Renesas RX62N using IAR, GCC and Renesas tool suites.
+	+ Added a STM32F103 demo application that uses the Rowley tools.
+	+ Under specific conditions xFreeBytesRemaining within heap_2.c could end up
+	  with an incorrect	value.  This has been fixed.
+	+ xTaskCreateGeneric() has a parameter that can be used to pass the handle
+	  of the task just created out to the calling task.  The assignment to this
+	  parameter has been moved to ensure it is assigned prior to the newly
+	  created having any possibility of executing.  This takes into account the
+	  case where the assignment is made to a global variable that is accessed by
+	  the newly created task.
+	+ Fixed some build time compiler warnings in various FreeTCPIP (based on
+	  uIP) files.
+	+ Fixed some build time compiler warnings in Demo/Common/Minimal/IntQueue.c.
+
+Changes between V6.0.4 and V6.0.5 released May 17 2010
+
+	+ Added port and demo application for the Cortus APS3 processor.
+
+Changes between V6.0.3 and V6.0.4 released March 14 2010
+
+	+ All the contributed files that were located in the Demo/Unsupported_Demos
+	  directory have been removed.  These files are instead now available in the
+	  new  Community Contributions section of the FreeRTOS website.  See
+	  https://www.FreeRTOS.org/RTOS-contributed-ports.html
+	+ The project file located in the Demo/CORTEX_STM32F107_GCC_Rowley directory
+	  has been upgraded to use V2.x of the Rowley Crossworks STM32 support
+	  package.
+	+ An initial Energy Micro EFM32 demo has been included.  This will be
+	  updated over the coming months to make better use of the low power modes
+	  the EFM32 provides.
+
+Changes between V6.0.2 and V6.0.3 released February 26 2010
+
+	+ SuperH SH7216 (SH2A-FPU) port and demo application added.
+	+ Slight modification made to the default implementation of
+	  pvPortMallocAligned() and vPortFreeAligned() macros so by default they
+	  just call pvPortMalloc() and vPortFree().  The macros are only needed to
+	  be defined when a memory protection unit (MPU) is being used - and then
+	  only depending on other configuration settings.
+
+Changes between V6.0.1 and V6.0.2 released January 9th 2010
+
+	+ Changed all GCC ARM 7 ports to use 0 as the SWI instruction parameter.
+	  Previously the parameter was blank and therefore only an implicit 0 but
+	  newer GCC releases do not permit this.
+	+ Updated IAR SAM7S and SAM7X ports to work with IAR V5.40.
+	+ Changed the stack alignment requirement for PIC32 from 4 bytes to 8 bytes.
+	+ Updated prvListTaskWithinSingleList() is it works on processors where the
+	  stack grows up from low memory.
+	+ Corrected some comments.
+	+ Updated the startup file for the RVDS LPC21xx demo.
+
+Changes between V6.0.0 and V6.0.1 released November 15th 2009
+
+	+ Altered pxPortInitialiseStack() for all Cortex-M3 ports to ensure the
+	  stack pointer is where the compiler expects it to be when a task first
+	  starts executing.
+
+	  The following minor changes only effect the Cortex-M3 MPU port:
+
+	+ portRESET_PRIVILEGE() assembly macro updated to include a clobber list.
+	+ Added prototypes for all the privileged function wrappers to ensure no
+	  compile time warnings are generated no matter what the warning level
+	  setting.
+	+ Corrected the name of portSVC_prvRaisePrivilege to
+	  portSVC_RAISE_PRIVILEGE.
+	+ Added conditional compilation into xTaskGenericCreate() to prevent some
+	  compilers issuing warnings when portPRIVILEGE_BIT is defined as zero.
+
+
+Changes between V5.4.2 and V6.0.0 released October 16th 2009
+
+	FreeRTOS V6 is backward compatible with FreeRTOS V5.x.
+
+	Main changes:
+
+	+ FreeRTOS V6 is the first version to include memory protection unit (MPU)
+	  support.  Two ports now exist for the Cortex M3, the standard FreeRTOS
+	  which does not include MPU support, and FreeRTOS-MPU which does.
+	+ xTaskCreateRestricted() and vTaskAllocateMPURegions() API functions added
+	  in support of FreeRTOS-MPU.
+	+ Wording for the GPL exception has been (hopefully) clarified.  Also the
+	  license.txt file included in the download has been fixed (the previous
+	  version contained some corruption).
+
+	Other changes:
+
+	+ New API function xPortGetFreeHeapSize() added to heap_1.c and heap_2.c.
+	+ ARM7 GCC demo interrupt service routines wrappers have been modified to
+	  call the C portion using an __asm statement.  This prevents the function
+	  call being inlined at higher optimisation levels.
+	+ ARM7 ports now automatically set the THUMB bit if necessary when
+	  setting up the initial stack of a task - removing the need for
+	  THUMB_INTERWORK to be defined.  This also allows THUMB mode and ARM mode
+	  tasks to be mixed more easily.
+	+ All ARM7/9 ports now have portBYTE_ALIGNMENT set to 8 by default.
+	+ Various demo application project files have been updated to be up to date
+	  with the latest IDE versions.
+	+ The linker scripts used with command line GCC demos have been updated to
+	  include an eh_frame section to allow their use with the latest Yagarto
+	  release.  Likewise the demo makefiles have been updated to include
+	  command line options to reduce or eliminate the eh_frame section all
+	  together.
+	+ The definition of portBYTE_ALIGNMENT_MASK has been moved out of the
+	  various memory allocation files and into the common portable.h header
+	  file.
+	+ Removed unnecessary use of portLONG, portSHORT and portCHAR.
+	+ Added LM3Sxxxx demo for Rowley CrossWorks.
+	+ Posix simulator has been upgraded - see the corresponding WEB page on the
+	  FreeRTOS.org site.
+
+
+Changes between V5.4.1 and V5.4.2 released August 9th 2009
+
+	+ Added a new port and demo app for the Altera Nios2 soft core.
+	+ Added LPC1768 demo for IAR.
+	+ Added a USB CDC demo to all LPC1768 demos (Code Red, CrossWorks and IAR).
+	+ Changed clock frequency of LPC1768 demos to 99MHz.
+
+Changes between V5.4.0 and V5.4.1 released July 25th 2009
+
+	+ New hook function added.  vApplicationMallocFailedHook() is (optionally)
+	  called if pvPortMalloc() returns NULL.
+	+ Additional casting added to xTaskCheckForTimeOut().  This prevents
+	  problems that can arise should configUSE_16_BIT_TICKS be set to 1 on a
+	  32 bit architecture (which would probably be a mistake, anyway).
+	+ Corrected the parameter passed to NVIC_SetPriority() to set the MAC
+	  interrupt priority in both LPC1768 demos.
+	+ Decreased the default setting of configMINIMAL_STACK_SIZE in the PIC32
+	  demo application to ensure the heap space was not completely consumed
+	  before the scheduler was started.
+
+Changes between V5.3.1 and V5.4.0 released July 13th 2009
+
+	+ Added Virtex5 / PPC440 port and demos.
+	+ Replaced the LPC1766 Red Suite demo with an LPC1768 Red Suite demo.  The
+	  original demo was configured to use engineering samples of the CPU.  The
+	  new demo has an improved Ethernet driver.
+	+ Added LPC1768 Rowley demo with zero copy Ethernet driver.
+	+ Reworked byte alignment code to ensure 8 byte alignment works correctly.
+	+ Set configUSE_16_BIT_TICKS to 0 in the PPC405 demo projects.
+	+ Changed the initial stack setup for the PPC405 to ensure the small data
+	  area pointers are setup correctly.
+
+Changes between V5.3.0 and V5.3.1 released June 21st 2009
+
+	+ Added ColdFire V1 MCF51CN128 port and WEB server demo.
+	+ Added STM32 Connectivity Line STM32107 Cortex M3 WEB server demo.
+	+ Changed the Cortex M3 port.c asm statements to __asm so it can be
+	  compiled using Rowley CrossWorks V2 in its default configuration.
+	+ Updated the Posix/Linux simulator contributed port.
+
+Changes between V5.2.0 and V5.3.0 released June 1st 2009
+
+	Main changes:
+
+	+ Added new (optional) feature that gathers statistics on the amount of CPU
+	  time used by each task.
+	+ Added a new demo application for the Atmel AT91SAM3U Cortex-M3 based
+	  microcontroller.
+	+ Added a new demo application for the NXP LPC1766 Cortex-M3 based
+	  microcontroller.
+	+ Added a contributed port/demo that allows FreeRTOS to be 'simulated' in a
+	  Linux environment.
+
+	Minor changes:
+	+ Updated the Stellaris uIP WEB server demos to include the new run time
+	  statistics gathering feature - and include a served WEB page that
+	  presents the information in a tabular format.
+	+ Added in the lwIP port layer for the Coldfire MCF52259.
+	+ Updated the CrossWorks LPC2368 WEB server to include an image in the
+	  served content.
+	+ Changed some of the timing in the initialisation of the LPC2368 MAC to
+	  permit its use on all part revisions.
+	+ Minor modifications to the core uIP code to remove some compiler warnings.
+	+ Added xTaskGetApplicationTaskTag() function and updated the OpenWatcom
+	  demo to make use of the new function.
+	+ Added contributed demos for AVR32 AP7000, STM32 Primer 2 and STM32 using
+	  Rowley Crossworks.
+	+ Heap_1.c and Heap_2.c used to define structures for the purpose of data
+	  alignment.  These have been converted to unions to save a few bytes of
+	  RAM that would otherwise be wasted.
+	+ Remove the call to strncpy() used to copy the task name into the TCB when
+	  the maximum task name is configured to be 1 byte long.
+
+Changes between V5.1.2 and V5.2.0 released March 14th 2009
+
+	+ Optimised the queue send and receive functions (also used by semaphores).
+	+ Replaced the standard critical sections used to protect BIOS calls in the
+	  PC port to instead use scheduler locks.  This is because the BIOS calls
+	  always return with interrupts enabled.
+	+ Corrected unclosed comments in boot.s.
+
+Changes between V5.1.1 and V5.1.2 released February 9th 2009
+
+	+ Added NEC V850ES port and demo.
+	+ Added NEC 78K0R port and demo.
+	+ Added MCF52259 port and demo.
+	+ Added the AT91SAM9XE port and demo.
+	+ Updated the MCF52233 FEC driver to work around a silicon bug that
+	  prevents the part auto negotiating some network parameters.
+	+ Minor modifications to the MCF52233 makefile to permit it to be used
+	  on Linux hosts.
+	+ Updated the STM32 primer files to allow them to be built with the latest
+	  version of the RIDE tools.
+	+ Updated the threads.js Java script used for kernel aware debugging in
+	  the Rowley CrossWorks IDE.
+
+
+Changes between V5.1.0 and V5.1.1 released November 20, 2008
+
+	+ Added Coldfire MCF52233 WEB server demo using GCC and Eclipse.
+	+ Added IAR MSP430 port and demo.
+	+ Corrected several compiler time issues that had crept in as tool versions
+	  change.
+	+ Included FreeRTOS-uIP - a faster uIP.  This is not yet complete.
+
+Changes between V5.0.4 and V5.1.0 released October 24, 2008
+
+	+ Added a new port and demo application for the ColdFire V2 core using the
+	  CodeWarrior development tools.
+	+ Replaced the ARM7 demo that used the old (and now no longer supported)
+	  Keil compiler with a new port that uses the new Keil/RVDS combo.
+	+ Stack overflow checking now works for stacks that grow up from low
+	  memory (PIC24 and dsPIC).
+	+ BUG FIX - set the PIC32 definition of portSTACK_GROWTH to the correct
+	  value of -1.
+	+ MSP430 port layers have been updated to permit tasks to place the
+	  microcontroller into power down modes 1 to 3.  The demo applications have
+	  likewise been updated to demonstrate the new feature.
+	+ Replaced the two separate MSP430/Rowley port layers with a single and more
+	  flexible version.
+	+ Added more contributed ports, including ports for NEC and SAM9
+	  microcontrollers.
+	+ Changed the linker script used in the LPC2368 Eclipse demo.
+
+Changes between V5.0.3 and V5.0.4 released September 22, 2008
+
+	+ Completely re-written port for ColdFire GCC.
+	+ Bug fix:  All Cortex M3 ports have a minor change to the code that sets
+	  the pending interrupt.
+	+ Some header files require that FreeRTOS.h be included prior to their
+	  inclusion.  #error message have been added to all such header file
+	  informing users to the cause of the compilation error should the headers
+	  not be included in the correct order.
+
+Changes between V5.0.2 and V5.0.3 released July 31, 2008
+
+	Changes relating to the Cortex M3:
+
+	+ Added configMAX_SYSCALL_INTERRUPT_PRIORITY usage to all the Cortex M3
+	  ports and demos.  See the port documentation pages on the FreeRTOS.org
+	  WEB site for full usage information.
+	+ Improved efficiency of Cortex M3 port even further.
+	+ Ensure the Cortex M3 port works no matter where the vector table is
+	  located.
+	+ Added the IntQTimer demo/test tasks to a demo project for each CM3 port
+	  (Keil, GCC and IAR) to test the new configMAX_SYSCALL_INTERRUPT_PRIORITY
+	  functionality.
+	+ Added the mainINCLUDE_WEB_SERVER definition to the LM3SXXXX IAR and Keil
+	  projects to allow the WEB server to be conditionally excluded from the
+	  build and therefore allow use of the KickStart (code size limited)
+	  compiler version.
+
+	Other changes:
+
+	+ Moved the PIC24 and dsPIC versions of vPortYield() from the C file to
+	  an assembly file to allow use with all MPLAB compiler versions.  This also
+	  allows the omit-frame-pointer optimisation to be turned off.
+
+Changes between V5.0.0 and V5.0.2 released May 30, 2008
+
+	+ Updated the PIC32 port to allow queue API calls to be used from
+	  interrupts above the kernel interrupt priority, and to allow full
+	  interrupt nesting.  Task stack usages has also been reduced.
+	+ Added a new PowerPC port that demonstrates how the trace macros can be
+	  used to allow the use of a floating point co-processor.  The
+	  traceTASK_SWITCHED_OUT() and traceTASK_SWITCHED_INT() macros are used to
+	  save and restore the floating point context respectively for those tasks
+	  that actually use floating point operations.
+	+ BUG FIX:  The first PPC405 port contained a bug in that it did not leave
+	  adequate space above the stack for the backchain to be saved when a task
+	  started to execute for the first time.
+	+ Updated queue.c to add in the means to allow interrupt nesting and for
+	  queue API functions to be called from interrupts that have a priority
+	  above the kernel priority.  This is only supported on PIC32 ports thus
+	  far.
+	+ Fixed the compiler warnings that were generated when the latest version
+	  of WinAVR was used.
+	+ Remove all inline usage of 'inline' from the core kernel code.
+	+ Added the queue registry feature.  The queue registry is provided as a
+	  means for kernel aware debuggers to locate queue definitions.  It has no
+	  purpose unless you are using a kernel aware debugger.  The queue registry
+	  will only be used when configQUEUE_REGISTRY_SIZE is greater than zero.
+	+ Added the ST Cortex-M3 drivers into the Demo/Common/Drivers directory to
+	  prevent them from having to be included in multiple demos.
+	+ Added a Keil STM32 demo application.
+	+ Changed the blocktim.c test files as it is no longer legitimate for all
+	  ports to call queue API functions from within a critical section.
+	+ Added the IntQueue.c test file to test the calling of queue API functions
+	  from different interrupt priority levels, and test interrupt nesting.
+
+Changes between V5.0.0 and V5.0.1
+
+	+ V5.0.1 was a customer specific release.
+
+Changes between V4.8.0 and V5.0.0 released April 15, 2008
+
+	*** VERY IMPORTANT INFORMATION ON UPGRADING TO FREERTOS.ORG V5.0.0 ***
+
+	The parameters to the functions xQueueSendFromISR(), xQueueSendToFrontFromISR(),
+	xQueueSendToBackFromISR() and xSemaphoreGiveFromISR() have changed.  You must
+	update all calls to these functions to use the new calling convention!  Your
+	compiler might not issue any type mismatch warnings!
+
+
+	Other changes:
+
+	+ Support added for the new Luminary Micro LM3S3768 and LM3S3748 Cortex-M3
+	  microcontrollers.
+	+ New task hook feature added.
+	+ PowerPC demo updated to use version 10.1 of the Xilinx EDK.
+	+ Efficiency gains within the PIC32 port layer.
+
+Changes between V4.7.2 and V4.8.0 released March 26 2008
+
+	+ Added a Virtex4 PowerPC 405 port and demo application.
+	+ Added optional stack overflow checking and new
+	  uxTaskGetStackHighWaterMark() function.
+	+ Added new xQueueIsQueueEmptyFromISR(), xQueueIsQueueFullFromISR() and
+	  uxQueueMessagesWaitingFromISR() API functions.
+	+ Efficiency improvements to the Cortex-M3 port layer.  NOTE: This
+	  requires that an SVC handler be installed in the application.
+	+ Efficiency improvements to the queue send and receive functions.
+	+ Added new trace macros.  These are application definable to provide
+	  a flexible trace facility.
+	+ Implemented the configKERNEL_INTERRUPT_PRIORITY within the Keil Cortex
+	  M3 port layer (bringing it up to the same standard as the IAR and GCC
+	  versions).
+	+ Ports that used the arm-stellaris-eabi-gcc tools have been converted to
+	  use the arm-non-eabi-gcc tools.
+
+Changes between V4.7.1 and V4.7.2 released February 21, 2008
+
+	+ Added Fujitsu MB91460 port and demo.
+	+ Added Fujitsu MB96340 port and demo.
+	+ Tidied up the capitalisation of include files to facilitate builds on
+	  Linux hosts.
+	+ Removed some redundant casting that was generating warnings - but was
+	  included to remove warnings on other compilers.
+
+Changes between V4.7.0 and V4.7.1 released February 3, 2008
+
+	+ Updated all IAR ARM projects to use V5.11 of the IAR Embedded Workbench
+	  for ARM.
+	+ Introduced recursive semaphore feature.
+	+ Updated LPC2368 demos to take into account silicon bugs in old chip
+	  revisions.
+	+ Updated STR9 uIP port to manually set the net mask and gateway addresses.
+	+ Updating demos to allow more to run with the co-operative scheduler.
+	+ Fixed co-operative scheduler behaviour upon the occurrence of a tick
+	  interrupt while the scheduler was suspended.
+	+ Updated documentation contained within semphr.h.
+	+ ARM7 GCC ports no longer use the IRQ attribute.
+
+Changes between V4.6.1 and V4.7.0 released December 6, 2007
+
+	+ Introduced the counting semaphore macros and demo source files.  The
+          Open Watcom PC project has been updated to include the new demo.  See
+          the online documentation for more information.
+	+ Introduced the 'alternative' queue handling API and demo source files.
+	  The Open Watcom PC project has been updated to include the new demo
+	  source files.  See the online documentation for more information.
+	+ Added AT91SAM7X Eclipse demo project.
+	+ Added the STM32 primer demo project for the GCC compiler and Ride IDE.
+	+ Removed the .lock files that were mistakenly included in the V4.6.1
+	  eclipse workspaces.
+
+Changes between V4.6.0 and V4.6.1 released November 5 2007
+
+	+ Added support for the MIPS M4K based PIC32.
+	+ Added 'extern "C"' to all the header files to facilitate use with C++.
+
+Changes between V4.5.0 and V4.6.0 released October 28 2007
+
+	+ Changed the method used to force a context switch within an ISR for the
+	  ARM7/9 GCC ports only.  The portENTER_SWITCHING_ISR() and
+	  portEXIT_SWITCHING_ISR() macros are no longer supported.  This is to
+	  ensure correct behaviour no matter which GCC version is used, with or
+	  without the -fomit-frame-pointer option, and at all optimisation levels.
+	+ Corrected the prototype for xQueueGenericSend() within queue.h.
+
+Changes between V4.4.0 and V4.5.0 released September 17 2007
+
+	+ Added the xQueueSendToFront(), xQueueSendToBack() and xQueuePeek()
+	  functionality.  These should now be used in preference to the old
+	  xQueueSend() function - which is maintained for backward compatibility.
+	+ Added Mutex functionality.  The behaviour of mutexes is subtly different
+	  to the already existing binary semaphores as mutexes automatically
+	  include a priority inheritance mechanism.
+	+ Added the GenQTest.c and QPeek.c to test and demonstrate the behaviour
+	  of the new functionality.
+	+ Updated the LM3Sxxxx and PC ports to include the new GenQTest.c and
+	  QPeek.c files.
+	+ Updated the GCC port for the Cortex M3 to include the
+	  configKERNEL_INTERRUPT_PRIORITY functionality.  This was previously only
+	  included in the IAR port.
+	+ Optimised the GCC and IAR port layer code - specifically the context
+	  switch code.
+	+ Consolidated the LM3Sxxxx EK demos for all development tools into a
+	  single project that automatically detects which version of the EK the
+	  application is executing on.
+	+ Added Eclipse support for LM3Sxxxx evaluation kits.
+	+ Added Eclipse support for the Keil LPC2368 evaluation kit.
+	+ Added the Demo/Drivers directory to hold code that is common to multiple
+	  demo application projects.
+	+ Included some minor bug fixes in the uIP 1.0 code.
+	+ Added an lwIP demo for the STR9 - thanks ST for assistance.
+	+ Updated the AVR32 port to ensure correct behaviour with full compiler
+	  optimisation.
+	+ Included binaries for OpenOCD FTDI and parallel port interfaces.
+
+Changes between V4.4.0 and V4.3.1 released July 31, 2007
+
+	+ Added AVR32 UC3B demo application.
+	+ Updated AVR32 UC3A port and demo applications.
+	+ Added IAR lwIP demo for AVR32 UC3A.
+	+ Updated listGET_OWNER_OF_NEXT_ENTRY() to assist compiler optimisation
+	  (thanks Niu Yong for making the suggestion).
+	+ Added xTaskGetSchedulerState() API function.
+	+ BUG FIX:  Corrected behaviour when tasks that are blocked indefinitely
+	  have their block time adjusted (within xQueueSend() and xQueueReceive()),
+	  and are the subject of a call the vTaskResume() when they are not
+	  actually in the Suspended state (thanks Dan Searles for reporting the
+	  issues).
+
+
+Changes between V4.3.0 and V4.3.1 released June 11, 2007
+
+	+ Added STMicroelectronics STM32 Cortex-M3 demo application.
+	+ Updated ustdlib.c for the GCC LM3S6965 demo.
+
+Changes between V4.2.1 and V4.3.0 released June 5, 2007
+
+	+ Introduced configKERNEL_INTERRUPT_PRIORITY to the IAR Cortex-M3, PIC24
+	  and dsPIC ports.  See the LM3S6965 and PIC24 demo application
+	  documentation pages for more information.
+	+ Updated the PIC24 and dsPIC demos to build with V3.0 of the PIC30 GCC
+	  tools, and changed the demo applications.
+	+ Added demos for the new Ethernet and CAN enabled Luminary Micro Stellaris
+	  microcontrollers.
+	+ Corrected bug in uIP the demos that prevented frames of approximately 1480
+	  bytes and over from being transmitted.
+	+ Included the LPC2368/uIP/Rowley demo into the main FreeRTOS.org
+	  download.
+	+ Update to WizC PIC18 port to permit its use with version 14 of the
+	  compiler.  Thanks Marcel!
+
+Changes between V4.2.1 and V4.2.0 released April 2, 2007
+
+	+ Added AVR32 AT32UC3A ports for GCC and IAR.
+	+ Added -fomit-frame-pointer option to lwIP SAM7X demo makefile.
+	+ Moved location of call to LCD_Init() in STR9 demo to ensure it is only
+	  called after the scheduler has been started.
+
+Changes between V4.1.3 and V4.2.0 released February 8, 2007
+
+	+ Changes to both task.c and queue.c as a result of testing performed on
+	  the SafeRTOS code base.
+	+ Added Cortex-M3 LM3S811 demos for GCC and IAR tools.
+
+Changes between V4.1.2 and V4.1.3 released November 19, 2006
+
+	+ Added STR750 ARM7 port using the Raisonance RIDE/GCC tools.
+	+ Added -fomit-frame-pointer option to Rowley ARM7 demos as work around
+	  to GCC bug at some optimisation levels.
+	+ Altered the way the heap is defined in the LM3S811 Keil demo to prevent
+	  the RAM usage from counting toward the code size limit calculation.
+	+ CO-ROUTINE BUG FIX:  Removed the call to prvIsQueueEmpty from within
+	  xQueueCRReceive as it exited with interrupts enabled.  Thanks Paul Katz.
+	+ Tasks that block on events with a timeout of portMAX_DELAY are now
+	  blocked indefinitely if configINCLUDE_vTaskSuspend is defined.
+	  Previously portMAX_DELAY was just the longest block time possible. This
+	  is still the case if configINCLUDE_vTaskSuspend is not defined.
+	+ Minor changes to some demo application files.
+
+Changes between V4.1.1 and V4.1.2 released October 21, 2006
+
+	+ Added 16bit PIC ports and demos.
+	+ Added STR750 port and demo.
+
+
+Changes between V4.1.0 and V4.1.1 released September 24, 2006
+
+	+ Added the Luminary Micro Stellaris LM3S811 demo application.
+
+Changes between V4.0.5 and V4.1.0 released August 28, 2006
+
+	+ Prior to V4.1.0, under certain documented circumstances, it was possible
+	  for xQueueSend() and xQueueReceive() to return without having completed
+	  and without their block time expiring.  The block time effectively
+	  stated a maximum block time, and the return value of the function needed
+	  to be checked to determine the reason for returning.  This is no longer
+	  the case as the functions will only return once the block time has
+	  expired or they are able to complete their operation.  It is therefore no
+	  longer necessary to wrap calls within loops.
+	+ Changed the critical section handling in the IAR AVR port to correct the
+	  behaviour when used with later compiler versions.
+	+ Added the LPC2138 CrossWorks demo into the zip file.  Previously this was
+	  only available as a separate download.
+	+ Modified the AVR demo applications to demonstrate the use of co-routines.
+
+Changes between V4.0.4 and V4.0.5 released August 13, 2006
+
+	+ Introduced API function xTaskResumeFromISR().  Same functionality as
+	  xTaskResume(), but can be called from within an interrupt service routine.
+	+ Optimised vListInsert() in the case when the wake time is the maximum
+	  tick count value.
+	+ Bug fix:  The 'value' of the event list item is updated when the priority
+	  of a task is changed.  Previously only the priority of the TCB itself was
+	  changed.
+	+ vTaskPrioritySet() and vTaskResume() no longer use the event list item.
+	  This has not been necessary since V4.0.1 when the xMissedYield handling
+	  was added.
+	+ Lowered the PCLK setting on the ARM9 STR9 demo from 96MHz to 48MHz.
+	+ When ending the scheduler - do not try to attempt a context switch when
+	  deleting the current task.
+	+ SAM7X EMAC drivers:  Corrected the Rx frame length mask when obtaining
+	  the length from the rx descriptor.
+
+
+Changes between V4.0.3 and V4.0.4 released June 22, 2006
+
+	+ Added a port and demo application for the STR9 ARM9 based processors from
+	  ST.
+	+ Slight optimisation to the vTaskPrioritySet() function.
+	+ Included the latest uIP version (1.0) in the demo/common/ethernet
+	  directory.
+
+Changes between V4.0.2 and V4.0.3 released June 7, 2006
+
+	+ Added a port and demo application for the Cortex-M3 target using the IAR
+	  development tools.
+	+ The ARM Cortex-m3 Rowley projects have been updated to use V1.6 of the
+	  CrossStudio tools.
+	+ The heap size defined for the lwIP Rowley demo has been reduced so that
+	  the project will link correctly when using the command line GCC tools
+	  also.  The makefile has also been modified to allow debugging.
+	+ The lwIP Rowley demo not includes a 'kernel aware' debug window.
+	+ The uIP Rowley project has been updated to build with V1.6 of CrossWorks.
+	+ The second set of tasks in the blockQ demo were created the wrong way
+	  around (inconsistent to the description in the file).  This has been
+	  corrected.
+
+Changes between V4.0.1 and V4.0.2 released May 28, 2006
+
+	+ Port and demo application added for the Tern Ethernet Engine controller.
+	+ Port and demo application added for MC9S12 using GCC, thanks to
+	  Jefferson "imajeff" Smith.
+	+ The function vTaskList() now suspends the scheduler rather than disabling
+	  interrupts during the creation of the task list.
+	+ Allow a task to delete itself by passing in its own handle.  Previously
+	  this could only be done by passing in NULL.
+	+ Corrected the value passed to the WDG_PeriodValueConfig() library
+	  function in the STR71x demo.
+	+ The tick hook function is now called only within a tick isr.  Previously
+	  it was also called when the tick function was called during the scheduler
+	  unlocking process.
+	+ The EMAC driver in the SAM7X lwIP demo has been made more robust as per
+	  the thread: https://sourceforge.net/forum/message.php?msg_id=3714405
+	+ In the PC ports:  Add function prvSetTickFrequencyDefault() to set the
+	  DOS tick back to its proper value when the scheduler exits.  Thanks
+	  Raynald!
+	+ In the Borland x86 ports there was a mistake in the portFIRST_CONTEXT
+	  macro where the BP register was not popped from the stack correctly.  The
+	  BP value would never get used so this did not cause a problem, but it has
+	  been corrected all the same.
+
+
+Changes between V4.0.0 and V4.0.1 released April 7 2006
+
+	+ Improved the ARM CORTEX M3 ports so they now only have to service
+	  pendSV interrupts.
+	+ Added a Luminary Micro port and demo for use with Rowley CrossWorks.
+	+ Added the xMissedYield handling to tasks.c.
+
+Changes between V3.2.4 and V4.0.0
+
+	Major changes:
+
+	+ Added new RTOS port for Luminary Micros ARM CORTEX M3 microcontrollers.
+	+ Added new co-routine functionality.
+
+	Other kernel changes:
+
+	+ An optional tick hook call is now included in the tick function.
+	+ Introduced the xMiniListItem structure and removed the list pxHead
+	  member in order to reduce RAM usage.
+	+ Added the following definitions to the FreeRTOSConfig.h file included
+	  with every port:
+		configUSE_TICK_HOOK
+		configUSE_CO_ROUTINES
+		configMAX_CO_ROUTINE_PRIORITIES
+	+ The volatile qualification has been changed on the list members to allow
+	  the task.c code to be tidied up a bit.
+	+ The scheduler can now be started even if no tasks have been created!
+	  This is to allow co-routines to run when there are no tasks.
+	+ A task being woken by an event will now preempt the currently running task
+	  even if its priority is only equal to the currently running task.
+
+	Port and demo application changes:
+
+	+ Updated the WinAVR demo to compile with the latest version of WinAVR
+	  with no warnings generated.
+	+ Changed the WinAVR makefile to make chars signed - needed for the
+	  co-routine code if BaseType_t is set to char.
+	+ Added new demo application file crflash.c.  This demonstrates co-routine
+	  functionality including passing data between co-routines.
+	+ Added new demo application file crhook.c.  This demonstrates co-routine
+	  and tick hook functionality including passing data between and ISR and
+	  a co-routine.
+	+ Some NOP's were missing following stmdb{}^ instructions in various ARM7
+	  ports.  These have been added.
+	+ Updated the Open Watcom PC demo project to include the crflash and crhook
+	  demo co-routines as an example of their use.
+	+ Updated the H8S demo to compile with the latest version of GCC.
+	+ Updated the SAM7X EMAC drivers to take into account the hardware errata
+	  regarding lost packets.
+	+ Changed the default MAC address used by some WEB server demos as the
+	  original addresses used was not liked by some routers.
+	+ Modified the SAM7X/IAR startup code slightly to prevent it hanging on
+	  some systems when the code is executed using a j-link debugger.  The
+	  j-link macro file configures the PLL before the code executes so
+	  attempting to configure it again in the startup code was causing a
+	  problem for some user.  Now a check is performed first to see if the
+	  PLL is already set up.
+	+ GCC port now contain all assembler code in a single asm block rather than
+	  individual blocks as before.
+	+ GCC LPC2000 code now explicitly uses R0 rather than letting the assembler
+	  choose the register to use as a temporary register during the context
+	  switch.
+	+ Added portNOP() macro.
+	+ The compare match load value on LPC2000 ports now has 1 added to correct
+	  the value used.
+	+ The minimal stack depth has been increased slightly on the WIZC PIC18
+	  port.
+
+Changes between V3.2.3 and V3.2.4
+
+	+ Modified the GCC ARM7 port layer to allow use with GCC V4.0.0 and above.
+	  Many thanks to Glen Biagioni for the provided update.
+	+ Added a new Microblaze port and demo application.
+	+ Modified the SAM7X EMAC demo to default to use the MII interface rather
+	  than the RMII interface.
+	+ Modified the startup sequence of the SAM7X demo slightly to allow the
+	  EMAC longer to auto negotiate.
+
+Changes between V3.2.2 and V3.2.3
+
+	+ Added MII interface support to the SAM7X EMAC peripheral driver.
+	  Previously versions worked with the RMII interface only.
+	+ Added command line GCC support to the SAM7X lwIP demo.  Previously the
+	  project could only be built using the CrossWorks IDE.  Modifications to
+	  this end include the addition of a standard makefile and linker script to
+	  the download, and some adjustments to the stacks allocated to each task.
+	+ Changed the page returned by the lwIP WEB server demo to display the
+	  task status table rather than the TCP/IP statistics.
+	+ Corrected the capitalisation of some header file includes and makefile
+	  dependencies to facilitate use on Linux host computers.
+	+ The various LPC2000 ports had a mistake in the timer setup where the
+	  prescale value was written to T0_PC instead of T0_PR.  This would have
+	  no effect unless a prescale value was actually required.  This has been
+	  corrected.
+
+Changes between V3.2.1 and V3.2.2 - Released 23 September, 2005
+
+	+ Added an IAR port for the Philips LPC2129
+	+ The Atmel ARM7 IAR demo project files are now saved in the IAR Embedded
+	  Workbench V4.30a format.
+	+ Updated the J-Link macro file included with the SAM7X uIP demo project
+	  to allow the demo board to be reset over the J-Link.
+
+Changes between V3.2.0 and V3.2.1 - Released 1 September, 2005
+
+	+ Added lwIP demo for AT91SAM7X using Rowley tools.
+	+ Added uIP demo for AT91SAM7X using IAR tools.
+	+ Added function xTaskGetCurrentTaskHandle().
+	+ Renamed events.h to mevents.h to prevent it conflicting with the events.h
+	  generated automatically by the HCS12 processor expert utility.  events.h
+	  is only used by the PC demo application.
+	+ Both PIC18 ports now initialise the TBLPTRU to 0 as this is the value
+	  expected by the compiler, and the compilers do not write to this
+	  register.
+	+ The HCS12 banked model demo now creates the 'suicide' tasks immediately
+	  prior to starting the scheduler.  These tasks should be the last tasks to
+	  get started in order for the test to function correctly.
+
+Changes between V3.1.1 and V3.2.0 - Released 29 June, 2005
+
+	V3.2.0 introduces two new MSP430 ports and corrects a minor kernel
+	issues.  Thanks to Ares.qi for his input.
+
+	+ Added two MSP430 ports that use the Rowley CrossWorks development tools.
+	  One port just mirrors the existing GCC port.  The other port was provided
+	  by Milos Prokic.  Thanks!
+	+ V3.2.0 corrects the behavior when vTaskPrioritySet() or vTaskResume()
+	  are called while the scheduler is locked (by a call to
+	  vTaskSuspendAll()).  When this is done the subject task now starts to
+	  execute immediately when the scheduler is unlocked if it has the highest
+	  priority that is ready to run.  Previously there was a possibility that
+	  the task would not run until the next RTOS tick or call to portYIELD().
+	+ Another similar small correction ensures that in the case where more than
+	  one task is blocked on a semaphore or queue, the task with the highest
+	  priority is guaranteed to be unblocked first.
+	+ Added a couple of more test tasks to the PC demo which cover the points
+	  above.
+
+Changes between V3.1.0 and V3.1.1 - Released 21st June, 2005
+
+	This release updates the HCS12 port.  The common kernel code
+	remains unchanged.
+
+	+ Updated the HCS12 port to support banking and introduced a demo
+	  application for the MC9S12DP256.  The new demo application is
+	  located in the Demo/HCS12_CodeWarrior_banked directory.
+	+ The name of the directory containing the MC9S12F32 demo application
+	  has been changed to Demo/HCS12_CodeWarrior_small (as in 'small'
+	  memory model).
+	+ MC9S12F32 demo updated slightly to use the PLL.  The CPU speed for the
+	  demo application is now 24MHz.  Previously it was 8MHz.
+	+ The demo application file Demo/Common/Minimal/death.c has a slight
+	  alteration to prevent it using floating point variables.
+
+
+Changes between V3.0.0 and V3.1.0 - Released 11th June, 2005
+
+	+ Added new ports for ST Microsystems STR71x, and Freescale HCS12
+	  microcontrollers.  Currently the HCS12 port is limited to the small
+	  memory model.  Large memory models will be supported in the next
+	  release.
+	+ PIC18 wizC port updated.  Thanks to Marcel van Lieshout for his
+	  continuing contribution.
+	+ The accuracy of the AVR port timer setup has been improved.  Thanks to
+	  Thomas Krutmann for this contribution.
+	+ Added a new conditional compilation macro configIDLE_SHOULD_YIELD.
+	  See the WEB documentation for details.
+	+ Updated the CrossWorks uIP demo to build with V1.4 of CrossWorks.
+	+ Slight modification to the SAM7 release build configuration to correct
+	  an include path definition.
+	+ Updated the MPLAB PIC18 documentation to provide extra details on linker
+	  file configuration.
+
+Changes between V3.0.0 and V2.6.1 - Released 23rd April, 2005
+
+	V3.0.0 includes many enhancements, so this history list is broken into
+	subsections as follows:
+
+		API changes
+		New ports
+		Directory name changes
+		Kernel and miscellaneous changes changes
+
+	- API changes
+
+		+ Each port now defines BaseType_t as the data type that is most
+		  efficient for that architecture.  The type BaseType_t is used
+		  extensively in API calls necessitating the following changes to the
+		  FreeRTOS API function prototypes.
+
+		  See the "New for V3.0.0" section of the FreeRTOS online
+		  documentation for full details of API changes.
+
+	- New ports
+
+		+ The AT91FR40008 ARM7 port contributed by John Feller is now included
+		  in the download (thanks John!).
+		+ The PIC18 port for the wizC/fedC compiler contributed by Marcel van
+		  Lieshout is now included in the download (thanks Marcel!).
+		+ The IAR port for the AVR microcontroller has been upgraded to V3.0.0
+		  and is now a supported port.
+
+	- Directory name changes
+
+		For consistency, and to allow integration of the new ports, the
+		following directory names have been changed.
+
+		+ The source/portable/GCC/ARM7 directory has been renamed
+		  source/portable/GCC/ARM7_LPC2000 so it is compatible with the naming
+		  of other GCC ARM7 ports.
+		+ The Demo/PIC directory has been renamed Demo/PIC18_MPLAB to
+		  accommodate the wizC/fedC PIC port.
+		+ The demo applications for the two AVR ports no longer share the same
+		  directory.  The WinAVR demo is in the Demo/AVR_ATMega323_WinAVR
+		  directory and the IAR port in the Demo/AVR_ATMega323_IAR directory.
+
+
+	- Kernel and miscellaneous changes changes
+
+		  See the "New for V3.0.0" section of the FreeRTOS online
+		  documentation for more information.
+
+		+ Previously 'portmacro.h' contained some user editable definitions
+		  relating to the user application, and some fixed definitions relating
+		  specifically to the port being used.  The application specific
+		  definitions have been removed from 'portmacro.h' and placed inside a
+		  new header file called 'FreeRTOSConfig.h'.  'portmacro.h' should now
+		  never be modified by the user.  A 'FreeRTOSConfig.h' is now included
+		  in each of FreeRTOS/Demo subdirectories - as it's settings relate to
+		  the demo application rather than being specific to the port.
+		+ Introduced configUSE_IDLE_HOOK in idle task.
+		+ The idle task will yield when another idle priority task is ready to
+		  run. Previously the idle task would run to the end of its time slice
+		  regardless.
+		+ The idle task is now created when the scheduler is started.  This
+		  requires less stack than the previous scheme where it was created upon
+		  creation of the first application task.
+		+ The function usPortCheckFreeStackSpace() has been renamed
+		  usTaskCheckFreeStackSpace() and moved from the portable layer to
+		  tasks.c.
+		+ Corrected spelling of portMINMAL_STACK_SIZE to portMINIMAL_STACK_SIZE.
+		+ The portheap.c file included with the AVR port has been deleted.  The
+		  AVR demo now uses the standard heap1 sample memory allocator.
+		+ The GCC AVR port is now build using the standard make utility.  The
+		  batch files used previously have been deleted.  This means a recent
+		  version of WinAVR is required in order to create a binary suitable for
+		  source level debugging.
+		+ vTaskStartScheduler() no longer takes the configUSE_PREEMPTION
+		  constant as a parameter.  Instead the constant is used directly within
+		  tasks.c  and no parameter is required.
+		+ The header file 'FreeRTOS.h' has been created and is used to include
+		  'projdefs.h', 'FreeRTOSConfig.h' and 'portable.h' in the necessary
+		  order.  FreeRTOS.h can now be included in place of these other
+		  headers.
+		+ The header file 'errors.h' has been deleted.  The definitions it
+		  contained are now located within 'projdefs.h'.
+		+ pvPortMalloc() now takes a size_t parameter as per the ANSI malloc().
+		  Previously an unsigned short was used.
+		+ When resuming the scheduler a yield is performed if either a tick has
+		  been missed, or a task is moved from the pending ready list into a
+		  ready list.  Previously a yield was not performed on this second
+		  condition.
+		+ In heap1.c an overflow check has been added to ensure the next free
+		  byte variable does not wrap around.
+		+ Introduced the portTASK_FUNCTION() and portTASK_FUNCTION_PROTO()
+		  macros.
+		+ The MPLAB PIC port now saved the TABLAT register in interrupt service
+		  routines.
+
+Changes between V2.6.0 and V2.6.1 - Released Feb 22, 2005
+
+	This version adds support for the H8 processor.
+
+	Other changes:
+
+	+ tskMAX_TASK_NAME_LEN removed from the task.h header and added to each
+	  individual portmacro.h file as portMAX_TASK_NAME_LEN.  This allows RAM
+	  limited ports to allocate fewer characters to the task name.
+	+ AVR port - Replaced the inb() and outb() functions with direct memory
+	  access.  This allows the port to be built with the 20050414 build of
+	  WinAVR.
+	+ GCC LPC2106 port - removed the 'static' from the definition of
+	  vNonPreemptiveTick() to allow the demo to link when using the cooperative
+	  scheduler.
+	+ GCC LPC2106 port - Corrected the optimisation options in the batch files
+	  ROM_THUMB.bat, RAM_THUMB.bat, ROM_ARM.bat and RAM_ARM.bat.  The lower case
+	  -o is replaced by an uppercase -O.
+	+ Tasks.c - The strcpy call has been removed when copying across the task
+	  name into the TCB.
+	+ Updated the trace visualisation to always be 4 byte aligned so it can be
+	  used on ARM architectures.
+	+ There are now two tracecon executables (that convert the trace file binary
+	  into an ASCII file).  One for big endian targets and one for little endian
+	  targets.
+	+ Added ucTasksDeleted variable to prevent vTaskSuspendAll() being called
+	  too often in the idle task.
+	+ SAM7 USB driver - Replaced the duplicated RX_DATA_BK0 in the interrupt
+	  mask with the RX_DATA_BK1.
+
+
+Changes between V2.5.5 and V2.6.0 - Released January 16, 2005
+
+	+ Added the API function vTaskDelayUntil().  The demo app file
+	  Demo/Common/Minimal/flash.c has been updated to demonstrate its use.
+	+ Added INCLUDE_vTaskDelay conditional compilation.
+	+ Changed the name of the Demo/ARM7_AtmelSAM7S64_IAR directory to
+	  Demo/ARM7_AT91SAM7S64_IAR for consistency.
+	+ Modified the AT91SAM7S USB driver to allow descriptors that have
+	  a length that is an exact multiple of the FIFO to be transmitted.
+
+Changes between V2.5.4 and V2.5.5 - Released January 3, 2005
+
+	This version adds support for the Atmel SAM7 ARM7 microcontrollers
+	along with the IAR development tools.
+
+	Other changes:
+
+	+ Renamed the Demo/ARM7 directory to Demo/ARM7_LPC2106_GCC.
+	+ Renamed the Demo/ARM7_Keil directory to Demo/ARM7_LPC2129_Keil.
+	+ Modified the Philips ARM7 serial interrupt service routines to only
+	  process one interrupt per call.  This seems to enable the ISR to
+	  operate more quickly.
+	+ Removed the 'far' keyword from the Open Watcom portable layer source
+	  files.  This allows their use with V1.3 of Open Watcom.
+	+ Minor modifications to the SDCC build files to allow their use under
+	  Linux.  Thanks to Frieder Ferlemann for this contribution.
+	+ Small change to sTaskCreate() to allow a context switch even when
+	  pxCreatedTask is NULL.  Thanks to Kamil for this contribution.
+	+ inline keyword removed from vTaskSwitchContext() and VTaskIncrementTick()
+	  definitions.
+
+Changes between V2.5.3 and V2.5.4 - Released Dec 1, 2004
+
+	This is an important maintenance release.
+
+	The function cTaskResumeAll() has been modified so it can be used safely
+	prior to the kernel being initialised.  This was an issue as
+	cTaskResumeAll() is called from pvPortMalloc().  Thanks to Daniel Braun
+	for highlighting this issue.
+
+Changes between V2.5.2 and V2.5.3 - Released Nov 2, 2004
+
+	The critical section handling functions have been changed for the GCC ARM7
+	port.   Some optimisation levels use the stack differently to others.  This
+	means the interrupt flags cannot always be stored on the stack and are
+	instead now stored in a variable, which is then saved as part of the
+	tasks context.  This allows the GCC ARM7 port to be used at all
+	optimisation levels - including -Os.
+
+	Other minor changes:
+
+	+ MSP430 definition of usCriticalNesting now uses the volatile qualifier.
+	  This is probably not required but added just in case.
+
+Changes between V2.5.1 and V2.5.2 - Released Oct 26, 2004
+
+	+ Added the Keil ARM7 port.
+	+ Slight modification to comtest.c to make the delay periods more random.
+	  This creates a better test condition.
+
+Changes between V2.5.0 and V2.5.1 - Released Oct 9, 2004
+
+	+ Added the MSP430 port.
+	+ Extra comments added to the GCC ARM7 port.c and portISR.c files.
+	+ The memory pool allocated within heap_1.c has been placed within a
+	  structure to ensure correct memory alignment on 32bit systems.
+	+ Within the GCC ARM7 serial drivers an extra check is made to ensure
+	  the post to the queue was successful if then attempting immediately
+	  retrieve the posted character.
+	+ Changed the name of the constant portTICKS_PER_MS to portTICK_PERIOD_MS
+	  as the old name was misleading.
+
+
+Changes between V2.4.2 and V2.5.0 - Released Aug 12, 2004
+
+	The RTOS source code download now includes three separate memory allocation
+	schemes - so you can choose the most appropriate for your application.
+	These are found in the Source/Portable/MemMang directory.  The demo
+	application projects have also been updated to demonstrate the new schemes.
+	See the "Memory Management" page of the API documentation for more details.
+
+	+ Added heap_1.c, heap_2.c and heap_3.c in the Source/Portable/MemMang
+	  directory.
+	+ Replaced the portheap.c files for each demo application with one of the
+	  new memory allocation files.
+	+ Updated the portmacro.h file for each demo application to include the
+	  constants required for the new memory allocators: portTOTAL_HEAP_SIZE and
+	  portBYTE_ALIGNMENT.
+	+ Added a new test to the ARM7 demo application that tests the operation
+	  of the heap_2 memory allocator.
+
+
+Changes between V2.4.1 and V2.4.2 - Released July 14, 2004
+
+	+ The ARM7 port now supports THUMB mode.
+	+ Modification to the ARM7 demo application serial port driver.
+
+Changes between V2.4.0 and V2.4.1 - Released July 2, 2004
+
+	+ Rationalised the ARM7 port version of portEXIT_CRITICAL() -
+	  improvements provided by Bill Knight.
+	+ Made demo serial driver more complete and robust.
+
+
+Changes between V2.4.0 and V2.3.1 - Released June 30, 2004
+
+	+ Added the first ARM7 port - thanks to Bill Knight for the assistance
+	  provided.
+	+ Added extra files to the Demo/Common/Minimal directory.  These are
+	  equivalent to their Demo/Common/Full counterparts but with the
+	  calls to the functions defined in print.c removed.
+	+ Added TABLAT to the list of registers saved as part of a PIC18 context.
+
+Changes between V2.3.0 and V2.3.1 - Released June 25, 2004
+
+	+ Changed the way the vector table is defined to be more portable.
+	+ Corrected the definitions of SPH and SPL in portmacro.s90.
+	  The previous definitions prevented V2.3.0 operating if the iom323.h
+	  header file was included in portmacro.s90.
+
+Changes between V2.2.0 and V2.3.0 - Released June 19, 2004
+
+	+ Added an AVR port that uses the IAR compiler.
+	+ Explicit use of 'signed' qualifier on plain char types.
+	+ Modified the Open Watcom project files to use 'signed' as the
+	  default char type.
+	+ Changed odd calculation of initial pxTopOfStack value when
+	  portSTACK_GROWTH < 0.
+	+ Added inline qualifier to context switch functions within task.c.
+	  Ports that do not support the (non ANSI) inline keyword have the
+	  inline #define'd away in  their respective portmacro.h files.
+
+Changes between V2.1.1 and V2.2.0 - Released May 18, 2004
+
+	+ Added Cygnal 8051 port.
+	+ PCLATU and PCLATH are now saved as part of the PIC18 context.  This
+	  allows function pointers to be used within tasks.  Thanks to Javier
+	  Espeche for the enhancement.
+	+ Minor changes to demo application files to reduce stack usage.
+	+ Minor changes to prevent compiler warnings when compiling the new port.
+
+Changes between V2.1.0 and V2.1.1 - Released March 12, 2004
+
+	+ Bug fix - pxCurrentTCB is now initialised before the call to
+	  prvInitialiseTaskLists().  Previously pxCurrentTCB could be accessed
+	  while null during the initialisation sequence.  Thanks to Giuseppe
+	  Franco for the correction.
+
+Changes between V2.0.0 and V2.1.0 - Released Feb 29, 2004
+
+	V2.1.0 has significant reworks that greatly reduce the amount of time
+	the kernel has interrupts disabled.  The first section of modifications
+	listed here must be taken into account by users.  The second section
+	are related to the kernel implementation and as such are transparent.
+
+	Section1 :
+
+	+ The typedef TickType_t has been introduced.  All delay times should
+	  now use a variable of type TickType_t in place of the unsigned long's
+	  used previously.  API function prototypes have been updated
+	  appropriately.
+	+ The configuration macro USE_16_BIT_TICKS has been introduced.  If set
+	  to 1 TickType_t is defined as an unsigned short.  If set to 0
+	  TickType_t is defined as an unsigned long.  See the configuration
+	  section of the API documentation for more details.
+	+ The configuration macro INCLUDE_vTaskSuspendAll is now obsolete.
+	+ vTaskResumeAll() has been renamed cTaskResumeAll() as it now returns a
+	  value (see the API documentation).
+	+ ulTaskGetTickCount() has been renamed xTaskGetTickCount() as the type
+	  it returns now depends on the USE_16_BIT_TICKS definition.
+	+ cQueueReceive() must now >never< be used from within an ISR.  Use the new
+	  cQueueReceiveFromISR() function instead.
+
+	Section 2:
+
+	+ A mechanism has been introduced that allows a queue to be accessed by
+	  a task and ISR simultaneously.
+	+ A "pending ready" queue has been introduced that enables interrupts to
+	  be processed when the scheduler is suspended.
+	+ The list implementation has been improved to provide faster item
+	  removal.
+	+ The scheduler now makes use of the scheduler suspend mechanism in places
+	  where previously interrupts were disabled.
+
+Changes between V1.2.6 and V2.0.0 - Released Jan 31, 2004
+
+	+ Introduced new API functions:
+		vTaskPriorityGet ()
+		vTaskPrioritySet ()
+		vTaskSuspend ()
+		vTaskResume ()
+		vTaskSuspendAll ()
+		vTaskResumeAll ()
+	+ Added conditional compilation options that allow the components of the
+	  kernel that are unused by an application to be excluded from the build.
+	  See the Configuration section on the WEB site for more information (on
+	  the API pages).  The macros have been added to each portmacro.h file (
+	  sometimes called prtmacro.h).
+	+ Rearranged tasks.c.
+	+ Added demo application file dynamic.c.
+	+ Updated the PC demo application to make use of dynamic.c.
+	+ Updated the documentation contained in the kernel header files.
+	+ Creating a task now causes a context switch if the task being created
+	  has a higher priority than the calling task - assuming the kernel is
+	  running.
+	+ vTaskDelete() now only causes a context switch if the calling task is
+	  the task being deleted.
+
+Changes between V1.2.5 and V1.2.6 - Released December 31, 2003
+
+	Barring the change to the interrupt vector (PIC port) these are minor
+	enhancements.
+
+	+ The interrupt vector used for the PIC master ISR has been changed from
+	  0x18 to 0x08 - where it should have always been.  The incorrect address
+	  still works but probably executes a number of NOP's before getting to the
+	  ISR.
+	+ Changed the baud rate used by the AVR demo application to 38400.  This
+	  has an error percentage of less than one percent with an 8MHz clock.
+	+ Raised the priority of the Rx task in demo\full\comtest.c.  This only
+	  affects the Flashlite and PC ports.  This was done to prevent the Rx
+	  buffer becoming full.
+	+ Reverted the Flashlite COM port driver back so it does not use the DMA.
+	  The DMA appears to miss characters under stress.  The Borland Flashlite
+	  port was also calculating a register value incorrectly resulting in the
+	  wrong DMA source address being used.  The same code worked fine when
+	  compiling with Open Watcom.  Other minor enhancements were made to the
+	  interrupt handling.
+	+ Modified the PIC serial Rx ISR to check for and clear overrun errors.
+	  Overrun errors seem to prevent any further characters being received.
+	+ The PIC demo projects now have some optimisation switched on.
+
+
+Changes between V1.2.4 and V1.2.5
+
+	Small fix made to the PIC specific port.c file described below.
+
+	+ Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global
+	  interrupt flag setting.  Using the two bits defined within
+	  portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
+	  before the test was performed.
+
+Changes between V1.2.3 and V1.2.4
+
+	V1.2.4 contains a release version of the PIC18 port.
+	An optional exception has been included with the GPL.  See the licensing
+	section of www.FreeRTOS.org for details.
+
+	+ The function xPortInitMinimal() has been renamed to
+	  xSerialPortInitMinimal() and the function xPortInit() has been renamed
+	  to xSerialPortInit().
+	+ The function sSerialPutChar() has been renamed cSerialPutChar() and
+	  the function return type chaned to portCHAR.
+	+ The integer and flop tasks now include calls to tskYIELD(), allowing
+	  them to be used with the cooperative scheduler.
+	+ All the demo applications now use the integer and comtest tasks when the
+ 	  cooperative scheduler is being used.  Previously they were only used with
+	  the preemptive scheduler.
+	+ Minor changes made to operation of minimal versions of comtest.c and
+	  integer.c.
+	+ The ATMega port definition of portCPU_CLOSK_HZ definition changed to
+	  8MHz base 10, previously it base 16.
+
+
+
+Changes between V1.2.2a and V1.2.3
+
+	The only change of any significance is to the license, which has changed
+	from the Open Software License to the GNU GPL.
+
+	The zip file also contains a pre-release version of the PIC18 port.  This
+	has not yet completed testing and as such does not constitute part of the
+	V1.2.3 release.  It is still however covered by the GNU GPL.
+
+	There are minor source code changes to accommodate the PIC C compiler.
+	These mainly involve more explicit casting.
+
+	+ sTaskCreate() has been modified slightly to make use of the
+	  portSTACK_GROWTH macro.  This is required for the PIC port where the
+	  stack grows in the opposite direction to the other existing ports.
+	+ prvCheckTasksWaitingTermination() has been modified slightly to bring
+	  the decrementing of usCurrentNumberOfTasks within the critical section,
+	  where it should have been since the creation of an eight bit port.
+
+Changes between V1.2.2 and V1.2.2a
+
+	The makefile and buildcoff.bat files included with the AVR demo application
+	have been modified for use with the September 2003 build of WinAVR.  No
+	source files have changed.
+
+Changes between V1.2.1 and V1.2.2
+
+	There are only minor changes here to allow the PC and Flashlite 186 ports
+	to use the Borland V4.52 compiler, as supplied with the Flashlite 186
+	development kit.
+
+	+ Introduced a BCC directory under source\portable.  This contains all the
+	  files specific to the Borland compiler port.
+	+ Corrected the macro naming of portMS_PER_TICK to portTICKS_PER_MS.
+	+ Modified comtest.c to increase the rate at which the string is
+	  transmitted and received on the serial port.  The Flashlite 186 demo
+	  app baud rate has also been increased.
+	+ The values of the constants used in both integer.c files have been
+          increased to force the Borland compiler to use 32 bit values.  The
+          Borland optimiser placed the previous values in 16 bit registers, and in
+          So doing invalidated the test.
+
+Changes between V1.2.0 and V1.2.1
+
+	This version includes some minor changes to the list implementation aimed
+	at improving the context switch time - with is now approximately 10% faster.
+	Changes include the removal of some null pointer assignment checks.  These
+	were redundant where the scheduler uses the list functions, but means any
+	user application choosing to use the same list functions must now check
+	that no NULL pointers are passed as a parameter.
+
+	The Flashlite 186 serial port driver has also been modified to use a DMA
+	channel for transmissions.  The serial driver is fully functional but still
+	under development.  Flashlite users may prefer to use V1.2.0 for now.
+
+	Details:
+
+	+ Changed the baud rate for the ATMega323 serial test from 19200 to 57600.
+	+ Use vSerialPutString() instead of single character puts in
+	  Demo\Full\Comtest.c.  This allows the use of the flashlite DMA serial
+	  driver.  Also the check variable only stops incrementing after two
+	  consecutive failures.
+	+ semtest.c creates four tasks, two of which operate at the idle priority.
+	  The tasks that operate at the idle priority now use a lower expected
+	  count than those running at a higher priority.  This prevents the low
+	  priority tasks from signalling an error because they have not been
+	  scheduled enough time for each of them to count the shared variable to
+	  the higher original value.
+	+ The flashlite 186 serial driver now uses a DMA channel for transmissions.
+	+ Removed the volatile modifier from the list function parameters.  This was
+	  only ever included to prevent compiler warnings.  Now warnings are
+	  removed by casting parameters where the calls are made.
+	+ prvListGetOwnerOfNextEntry() and prvListGetOwnerOfHeadEntry() have been
+	  removed from list.c and added as macros in list.h.
+	+ usNumberOfItems has been added to the list structure.  This removes the
+	  need for a pointer comparison when checking if a list is empty, and so
+	  is slightly faster.
+	+ Removed the NULL check in vListRemove().  This makes the call faster but
+	  necessitates any application code utilising the list implementation to
+	  ensure NULL pointers are not passed.
+	+ Renamed portTICKS_PER_MS definition to portMS_PER_TICK (milli seconds
+	  per tick).  This is what it always should have been.
+
+Changes between V1.01 and V1.2.0
+
+	The majority of these changes were made to accommodate the 8bit AVR port.
+	The scheduler workings have not changed, but some of the data types used
+	have been made more friendly to an eight bit environment.
+
+	Details:
+
+	+ Changed the version numbering format.
+	+ Added AVR port.
+	+ Split the directory demo\common into demo\common\minimal and
+	  demo\common\full.  The files in the full directory are for systems with
+	  a display (currently PC and Flashlite 186 demo's).  The files in the
+	  minimal directory are for systems with limited RAM and no display
+	  (currently MegaAVR).
+	+ Minor changes to demo application function prototypes to make more use
+	  of 8bit data types.
+	+ Within the scheduler itself the following functions have slightly
+	  modified declarations to make use of 8bit data types where possible:
+		xQueueCreate(),
+		sQueueReceive(),
+		sQUeueReceive(),
+		usQueueMessageWaiting(),
+		sQueueSendFromISR(),
+		sSemaphoreTake(),
+		sSemaphoreGive(),
+		sSemaphoreGiveFromISR(),
+		sTaskCreate(),
+		sTaskMoveFromEventList().
+
+	  Where the return type has changed the function name has also changed in
+	  accordance with the naming convention.  For example
+	  usQueueMessageWaiting() has become ucQueueMessageWaiting().
+	+ The definition tskMAX_PRIORITIES has been moved from task.h to
+	  portmacro.h and renamed portMAX_PRIORITIES.  This allows different
+	  ports to allocate a different maximum number of priorities.
+	+ By default the trace facility is off, previously USE_TRACE_FACILITY
+	  was defined.
+	+ comtest.c now uses a psuedo random delay between sends.  This allows for
+	  better testing as the interrupts do not arrive at regular intervals.
+	+ Minor change to the Flashlite serial port driver.  The driver is written
+	  to demonstrate the scheduler and is not written to be efficient.
+
+
+
+Changes between V1.00 and V1.01
+
+	These changes improve the ports.  The scheduler itself has not changed.
+
+	Improved context switch mechanism used when performing a context
+	switch from an ISR (both the tick ISR and the serial comms ISR's within
+	the demo application).  The new mechanism is faster and uses less stack.
+
+	The assembler file portasm.asm has been replaced by a header file
+	portasm.h.  This includes a few assembler macro definitions.
+
+	All saving and restoring of registers onto/off of the stack is now handled
+	by the compiler.  This means the initial stack setup for a task has to
+	mimic the stack used by the compiler, which is different for debug and
+	release builds.
+
+	Slightly changed the operation of the demo application, details below.
+
+	Details:
+
+	+ portSWITCH_CONTEXT() replaced by vPortFirstContext().
+	+ pxPortInitialiseStack() modified to replicate the stack used by the
+	  compiler.
+	+ portasm.asm file removed.
+	+ portasm.h introduced.  This contains macro definitions for
+	  portSWITCH_CONTEXT() and portFIRST_CONTEXT().
+	+ Context switch from ISR now uses the compiler generated interrupt
+	  mechanism.  This is done simply by calling portSWITCH_CONTEXT and leaving
+	  the save/restore to compiler generated code.
+	+ Calls to taskYIELD() during ISR's have been replaced by calling the
+	  simpler and faster portSWITCH_CONTEXT().
+	+ The Flashlite 186 port now uses 186 instruction set (used to use 80x86
+	  instructions only).
+	+ The blocking queue tasks within the demo application did not operate
+	  quite as described.  This has been corrected.
+	+ The priority of the comtest Rx task within the demo application has been
+	  lowered.  Received characters are now processed (read from the queue) at
+	  the idle priority, allowing low priority tasks to run evenly at times of
+	  a high communications overhead.
+	+ Prevent the call to kbhit() in main.c for debug builds as the debugger
+	  seems to have problems stepping over the call.  This if for the PC port
+	  only.
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/LICENSE.md b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/LICENSE.md
new file mode 100644
index 0000000..9cf1062
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/LICENSE.md
@@ -0,0 +1,19 @@
+MIT License
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/Quick_Start_Guide.url b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/Quick_Start_Guide.url
new file mode 100644
index 0000000..0aa68ed
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/Quick_Start_Guide.url
@@ -0,0 +1,5 @@
+[InternetShortcut]
+URL=https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html
+IDList=
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/README.md b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/README.md
new file mode 100644
index 0000000..1cc1b84
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/README.md
@@ -0,0 +1,39 @@
+## Getting started
+This repository contains FreeRTOS kernel source/header files and kernel ports only. This repository is referenced as a submodule in [FreeRTOS/FreeRTOS](https://github.com/FreeRTOS/FreeRTOS) repository, which contains pre-configured demo application projects under ```FreeRTOS/Demo``` directory. 
+
+The easiest way to use FreeRTOS is to start with one of the pre-configured demo application projects.  That way you will have the correct FreeRTOS source files included, and the correct include paths configured.  Once a demo application is building and executing you can remove the demo application files, and start to add in your own application source files.  See the [FreeRTOS Kernel Quick Start Guide](https://www.FreeRTOS.org/FreeRTOS-quick-start-guide.html) for detailed instructions and other useful links.
+
+Additionally, for FreeRTOS kernel feature information refer to the [Developer Documentation](https://www.FreeRTOS.org/features.html), and [API Reference](https://www.FreeRTOS.org/a00106.html).
+
+### Getting help
+If you have any questions or need assistance troubleshooting your FreeRTOS project, we have an active community that can help on the [FreeRTOS Community Support Forum](https://forums.freertos.org).
+
+## Cloning this repository
+
+To clone using HTTPS:
+```
+git clone https://github.com/FreeRTOS/FreeRTOS-Kernel.git
+```
+Using SSH:
+```
+git clone git@github.com:FreeRTOS/FreeRTOS-Kernel.git
+```
+
+## Repository structure
+- The root of this repository contains the three files that are common to 
+every port - list.c, queue.c and tasks.c.  The kernel is contained within these 
+three files.  croutine.c implements the optional co-routine functionality - which
+is normally only used on very memory limited systems.
+
+- The ```./portable``` directory contains the files that are specific to a particular microcontroller and/or compiler. 
+See the readme file in the ```./portable``` directory for more information.
+
+- The ```./include``` directory contains the real time kernel header files.
+
+### Code Formatting
+FreeRTOS files are formatted using the "uncrustify" tool. The configuration file used by uncrustify can be found in the [FreeRTOS/FreeRTOS repository](https://github.com/FreeRTOS/FreeRTOS/blob/master/tools/uncrustify.cfg). 
+
+### Spelling
+*lexicon.txt* contains words that are not traditionally found in an English dictionary. It is used by the spellchecker to verify the various jargon, variable names, and other odd words used in the FreeRTOS code base. If your pull request fails to pass the spelling and you believe this is a mistake, then add the word to *lexicon.txt*. 
+Note that only the FreeRTOS Kernel source files are checked for proper spelling, the portable section is ignored.
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/croutine.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/croutine.c
new file mode 100644
index 0000000..64574e3
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/croutine.c
@@ -0,0 +1,361 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "croutine.h"
+
+/* Remove the whole file is co-routines are not being used. */
+#if ( configUSE_CO_ROUTINES != 0 )
+
+/*
+ * Some kernel aware debuggers require data to be viewed to be global, rather
+ * than file scope.
+ */
+    #ifdef portREMOVE_STATIC_QUALIFIER
+        #define static
+    #endif
+
+
+/* Lists for ready and blocked co-routines. --------------------*/
+    static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ]; /*< Prioritised ready co-routines. */
+    static List_t xDelayedCoRoutineList1;                                   /*< Delayed co-routines. */
+    static List_t xDelayedCoRoutineList2;                                   /*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
+    static List_t * pxDelayedCoRoutineList = NULL;                          /*< Points to the delayed co-routine list currently being used. */
+    static List_t * pxOverflowDelayedCoRoutineList = NULL;                  /*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
+    static List_t xPendingReadyCoRoutineList;                               /*< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
+
+/* Other file private variables. --------------------------------*/
+    CRCB_t * pxCurrentCoRoutine = NULL;
+    static UBaseType_t uxTopCoRoutineReadyPriority = 0;
+    static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
+
+/* The initial state of the co-routine when it is created. */
+    #define corINITIAL_STATE    ( 0 )
+
+/*
+ * Place the co-routine represented by pxCRCB into the appropriate ready queue
+ * for the priority.  It is inserted at the end of the list.
+ *
+ * This macro accesses the co-routine ready lists and therefore must not be
+ * used from within an ISR.
+ */
+    #define prvAddCoRoutineToReadyQueue( pxCRCB )                                                                       \
+    {                                                                                                                   \
+        if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority )                                                          \
+        {                                                                                                               \
+            uxTopCoRoutineReadyPriority = pxCRCB->uxPriority;                                                           \
+        }                                                                                                               \
+        vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) ); \
+    }
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first co-routine.
+ */
+    static void prvInitialiseCoRoutineLists( void );
+
+/*
+ * Co-routines that are readied by an interrupt cannot be placed directly into
+ * the ready lists (there is no mutual exclusion).  Instead they are placed in
+ * in the pending ready list in order that they can later be moved to the ready
+ * list by the co-routine scheduler.
+ */
+    static void prvCheckPendingReadyList( void );
+
+/*
+ * Macro that looks at the list of co-routines that are currently delayed to
+ * see if any require waking.
+ *
+ * Co-routines are stored in the queue in the order of their wake time -
+ * meaning once one co-routine has been found whose timer has not expired
+ * we need not look any further down the list.
+ */
+    static void prvCheckDelayedList( void );
+
+/*-----------------------------------------------------------*/
+
+    BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode,
+                                 UBaseType_t uxPriority,
+                                 UBaseType_t uxIndex )
+    {
+        BaseType_t xReturn;
+        CRCB_t * pxCoRoutine;
+
+        /* Allocate the memory that will store the co-routine control block. */
+        pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
+
+        if( pxCoRoutine )
+        {
+            /* If pxCurrentCoRoutine is NULL then this is the first co-routine to
+            * be created and the co-routine data structures need initialising. */
+            if( pxCurrentCoRoutine == NULL )
+            {
+                pxCurrentCoRoutine = pxCoRoutine;
+                prvInitialiseCoRoutineLists();
+            }
+
+            /* Check the priority is within limits. */
+            if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )
+            {
+                uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;
+            }
+
+            /* Fill out the co-routine control block from the function parameters. */
+            pxCoRoutine->uxState = corINITIAL_STATE;
+            pxCoRoutine->uxPriority = uxPriority;
+            pxCoRoutine->uxIndex = uxIndex;
+            pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;
+
+            /* Initialise all the other co-routine control block parameters. */
+            vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );
+            vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );
+
+            /* Set the co-routine control block as a link back from the ListItem_t.
+             * This is so we can get back to the containing CRCB from a generic item
+             * in a list. */
+            listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );
+            listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );
+
+            /* Event lists are always in priority order. */
+            listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );
+
+            /* Now the co-routine has been initialised it can be added to the ready
+             * list at the correct priority. */
+            prvAddCoRoutineToReadyQueue( pxCoRoutine );
+
+            xReturn = pdPASS;
+        }
+        else
+        {
+            xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+        }
+
+        return xReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay,
+                                     List_t * pxEventList )
+    {
+        TickType_t xTimeToWake;
+
+        /* Calculate the time to wake - this may overflow but this is
+         * not a problem. */
+        xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
+
+        /* We must remove ourselves from the ready list before adding
+         * ourselves to the blocked list as the same list item is used for
+         * both lists. */
+        ( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+
+        /* The list item will be inserted in wake time order. */
+        listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );
+
+        if( xTimeToWake < xCoRoutineTickCount )
+        {
+            /* Wake time has overflowed.  Place this item in the
+             * overflow list. */
+            vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+        }
+        else
+        {
+            /* The wake time has not overflowed, so we can use the
+             * current block list. */
+            vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+        }
+
+        if( pxEventList )
+        {
+            /* Also add the co-routine to an event list.  If this is done then the
+             * function must be called with interrupts disabled. */
+            vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static void prvCheckPendingReadyList( void )
+    {
+        /* Are there any co-routines waiting to get moved to the ready list?  These
+         * are co-routines that have been readied by an ISR.  The ISR cannot access
+         * the ready lists itself. */
+        while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )
+        {
+            CRCB_t * pxUnblockedCRCB;
+
+            /* The pending ready list can be accessed by an ISR. */
+            portDISABLE_INTERRUPTS();
+            {
+                pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyCoRoutineList ) );
+                ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+            }
+            portENABLE_INTERRUPTS();
+
+            ( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );
+            prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static void prvCheckDelayedList( void )
+    {
+        CRCB_t * pxCRCB;
+
+        xPassedTicks = xTaskGetTickCount() - xLastTickCount;
+
+        while( xPassedTicks )
+        {
+            xCoRoutineTickCount++;
+            xPassedTicks--;
+
+            /* If the tick count has overflowed we need to swap the ready lists. */
+            if( xCoRoutineTickCount == 0 )
+            {
+                List_t * pxTemp;
+
+                /* Tick count has overflowed so we need to swap the delay lists.  If there are
+                 * any items in pxDelayedCoRoutineList here then there is an error! */
+                pxTemp = pxDelayedCoRoutineList;
+                pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;
+                pxOverflowDelayedCoRoutineList = pxTemp;
+            }
+
+            /* See if this tick has made a timeout expire. */
+            while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )
+            {
+                pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );
+
+                if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )
+                {
+                    /* Timeout not yet expired. */
+                    break;
+                }
+
+                portDISABLE_INTERRUPTS();
+                {
+                    /* The event could have occurred just before this critical
+                     *  section.  If this is the case then the generic list item will
+                     *  have been moved to the pending ready list and the following
+                     *  line is still valid.  Also the pvContainer parameter will have
+                     *  been set to NULL so the following lines are also valid. */
+                    ( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );
+
+                    /* Is the co-routine waiting on an event also? */
+                    if( pxCRCB->xEventListItem.pxContainer )
+                    {
+                        ( void ) uxListRemove( &( pxCRCB->xEventListItem ) );
+                    }
+                }
+                portENABLE_INTERRUPTS();
+
+                prvAddCoRoutineToReadyQueue( pxCRCB );
+            }
+        }
+
+        xLastTickCount = xCoRoutineTickCount;
+    }
+/*-----------------------------------------------------------*/
+
+    void vCoRoutineSchedule( void )
+    {
+        /* Only run a co-routine after prvInitialiseCoRoutineLists() has been
+         * called.  prvInitialiseCoRoutineLists() is called automatically when a
+         * co-routine is created. */
+        if( pxDelayedCoRoutineList != NULL )
+        {
+            /* See if any co-routines readied by events need moving to the ready lists. */
+            prvCheckPendingReadyList();
+
+            /* See if any delayed co-routines have timed out. */
+            prvCheckDelayedList();
+
+            /* Find the highest priority queue that contains ready co-routines. */
+            while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )
+            {
+                if( uxTopCoRoutineReadyPriority == 0 )
+                {
+                    /* No more co-routines to check. */
+                    return;
+                }
+
+                --uxTopCoRoutineReadyPriority;
+            }
+
+            /* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines
+             * of the same priority get an equal share of the processor time. */
+            listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );
+
+            /* Call the co-routine. */
+            ( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static void prvInitialiseCoRoutineLists( void )
+    {
+        UBaseType_t uxPriority;
+
+        for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )
+        {
+            vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );
+        }
+
+        vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );
+        vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );
+        vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );
+
+        /* Start with pxDelayedCoRoutineList using list1 and the
+         * pxOverflowDelayedCoRoutineList using list2. */
+        pxDelayedCoRoutineList = &xDelayedCoRoutineList1;
+        pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList )
+    {
+        CRCB_t * pxUnblockedCRCB;
+        BaseType_t xReturn;
+
+        /* This function is called from within an interrupt.  It can only access
+         * event lists and the pending ready list.  This function assumes that a
+         * check has already been made to ensure pxEventList is not empty. */
+        pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+        ( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+        vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );
+
+        if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )
+        {
+            xReturn = pdTRUE;
+        }
+        else
+        {
+            xReturn = pdFALSE;
+        }
+
+        return xReturn;
+    }
+
+#endif /* configUSE_CO_ROUTINES == 0 */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/event_groups.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/event_groups.c
new file mode 100644
index 0000000..0ee7990
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/event_groups.c
@@ -0,0 +1,771 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "event_groups.h"
+
+/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified
+ * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+ * for the header files above, but not in this file, in order to generate the
+ * correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */
+
+/* The following bit fields convey control information in a task's event list
+ * item value.  It is important they don't clash with the
+ * taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
+#if configUSE_16_BIT_TICKS == 1
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    0x0100U
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    0x0200U
+    #define eventWAIT_FOR_ALL_BITS           0x0400U
+    #define eventEVENT_BITS_CONTROL_BYTES    0xff00U
+#else
+    #define eventCLEAR_EVENTS_ON_EXIT_BIT    0x01000000UL
+    #define eventUNBLOCKED_DUE_TO_BIT_SET    0x02000000UL
+    #define eventWAIT_FOR_ALL_BITS           0x04000000UL
+    #define eventEVENT_BITS_CONTROL_BYTES    0xff000000UL
+#endif
+
+typedef struct EventGroupDef_t
+{
+    EventBits_t uxEventBits;
+    List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxEventGroupNumber;
+    #endif
+
+    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+        uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */
+    #endif
+} EventGroup_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Test the bits set in uxCurrentEventBits to see if the wait condition is met.
+ * The wait condition is defined by xWaitForAllBits.  If xWaitForAllBits is
+ * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor
+ * are also set in uxCurrentEventBits.  If xWaitForAllBits is pdFALSE then the
+ * wait condition is met if any of the bits set in uxBitsToWait for are also set
+ * in uxCurrentEventBits.
+ */
+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
+                                        const EventBits_t uxBitsToWaitFor,
+                                        const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+    EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer )
+    {
+        EventGroup_t * pxEventBits;
+
+        /* A StaticEventGroup_t object must be provided. */
+        configASSERT( pxEventGroupBuffer );
+
+        #if ( configASSERT_DEFINED == 1 )
+            {
+                /* Sanity check that the size of the structure used to declare a
+                 * variable of type StaticEventGroup_t equals the size of the real
+                 * event group structure. */
+                volatile size_t xSize = sizeof( StaticEventGroup_t );
+                configASSERT( xSize == sizeof( EventGroup_t ) );
+            } /*lint !e529 xSize is referenced if configASSERT() is defined. */
+        #endif /* configASSERT_DEFINED */
+
+        /* The user has provided a statically allocated event group - use it. */
+        pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */
+
+        if( pxEventBits != NULL )
+        {
+            pxEventBits->uxEventBits = 0;
+            vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+
+            #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+                {
+                    /* Both static and dynamic allocation can be used, so note that
+                     * this event group was created statically in case the event group
+                     * is later deleted. */
+                    pxEventBits->ucStaticallyAllocated = pdTRUE;
+                }
+            #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+            traceEVENT_GROUP_CREATE( pxEventBits );
+        }
+        else
+        {
+            /* xEventGroupCreateStatic should only ever be called with
+             * pxEventGroupBuffer pointing to a pre-allocated (compile time
+             * allocated) StaticEventGroup_t variable. */
+            traceEVENT_GROUP_CREATE_FAILED();
+        }
+
+        return pxEventBits;
+    }
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+    EventGroupHandle_t xEventGroupCreate( void )
+    {
+        EventGroup_t * pxEventBits;
+
+        /* Allocate the event group.  Justification for MISRA deviation as
+         * follows:  pvPortMalloc() always ensures returned memory blocks are
+         * aligned per the requirements of the MCU stack.  In this case
+         * pvPortMalloc() must return a pointer that is guaranteed to meet the
+         * alignment requirements of the EventGroup_t structure - which (if you
+         * follow it through) is the alignment requirements of the TickType_t type
+         * (EventBits_t being of TickType_t itself).  Therefore, whenever the
+         * stack alignment requirements are greater than or equal to the
+         * TickType_t alignment requirements the cast is safe.  In other cases,
+         * where the natural word size of the architecture is less than
+         * sizeof( TickType_t ), the TickType_t variables will be accessed in two
+         * or more reads operations, and the alignment requirements is only that
+         * of each individual read. */
+        pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */
+
+        if( pxEventBits != NULL )
+        {
+            pxEventBits->uxEventBits = 0;
+            vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+
+            #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+                {
+                    /* Both static and dynamic allocation can be used, so note this
+                     * event group was allocated statically in case the event group is
+                     * later deleted. */
+                    pxEventBits->ucStaticallyAllocated = pdFALSE;
+                }
+            #endif /* configSUPPORT_STATIC_ALLOCATION */
+
+            traceEVENT_GROUP_CREATE( pxEventBits );
+        }
+        else
+        {
+            traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */
+        }
+
+        return pxEventBits;
+    }
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
+                             const EventBits_t uxBitsToSet,
+                             const EventBits_t uxBitsToWaitFor,
+                             TickType_t xTicksToWait )
+{
+    EventBits_t uxOriginalBitValue, uxReturn;
+    EventGroup_t * pxEventBits = xEventGroup;
+    BaseType_t xAlreadyYielded;
+    BaseType_t xTimeoutOccurred = pdFALSE;
+
+    configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+    configASSERT( uxBitsToWaitFor != 0 );
+    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+        {
+            configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+        }
+    #endif
+
+    vTaskSuspendAll();
+    {
+        uxOriginalBitValue = pxEventBits->uxEventBits;
+
+        ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );
+
+        if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )
+        {
+            /* All the rendezvous bits are now set - no need to block. */
+            uxReturn = ( uxOriginalBitValue | uxBitsToSet );
+
+            /* Rendezvous always clear the bits.  They will have been cleared
+             * already unless this is the only task in the rendezvous. */
+            pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+
+            xTicksToWait = 0;
+        }
+        else
+        {
+            if( xTicksToWait != ( TickType_t ) 0 )
+            {
+                traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );
+
+                /* Store the bits that the calling task is waiting for in the
+                 * task's event list item so the kernel knows when a match is
+                 * found.  Then enter the blocked state. */
+                vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );
+
+                /* This assignment is obsolete as uxReturn will get set after
+                 * the task unblocks, but some compilers mistakenly generate a
+                 * warning about uxReturn being returned without being set if the
+                 * assignment is omitted. */
+                uxReturn = 0;
+            }
+            else
+            {
+                /* The rendezvous bits were not set, but no block time was
+                 * specified - just return the current event bit value. */
+                uxReturn = pxEventBits->uxEventBits;
+                xTimeoutOccurred = pdTRUE;
+            }
+        }
+    }
+    xAlreadyYielded = xTaskResumeAll();
+
+    if( xTicksToWait != ( TickType_t ) 0 )
+    {
+        if( xAlreadyYielded == pdFALSE )
+        {
+            portYIELD_WITHIN_API();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        /* The task blocked to wait for its required bits to be set - at this
+         * point either the required bits were set or the block time expired.  If
+         * the required bits were set they will have been stored in the task's
+         * event list item, and they should now be retrieved then cleared. */
+        uxReturn = uxTaskResetEventItemValue();
+
+        if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+        {
+            /* The task timed out, just return the current event bit value. */
+            taskENTER_CRITICAL();
+            {
+                uxReturn = pxEventBits->uxEventBits;
+
+                /* Although the task got here because it timed out before the
+                 * bits it was waiting for were set, it is possible that since it
+                 * unblocked another task has set the bits.  If this is the case
+                 * then it needs to clear the bits before exiting. */
+                if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )
+                {
+                    pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            taskEXIT_CRITICAL();
+
+            xTimeoutOccurred = pdTRUE;
+        }
+        else
+        {
+            /* The task unblocked because the bits were set. */
+        }
+
+        /* Control bits might be set as the task had blocked should not be
+         * returned. */
+        uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+    }
+
+    traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );
+
+    /* Prevent compiler warnings when trace macros are not used. */
+    ( void ) xTimeoutOccurred;
+
+    return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                 const EventBits_t uxBitsToWaitFor,
+                                 const BaseType_t xClearOnExit,
+                                 const BaseType_t xWaitForAllBits,
+                                 TickType_t xTicksToWait )
+{
+    EventGroup_t * pxEventBits = xEventGroup;
+    EventBits_t uxReturn, uxControlBits = 0;
+    BaseType_t xWaitConditionMet, xAlreadyYielded;
+    BaseType_t xTimeoutOccurred = pdFALSE;
+
+    /* Check the user is not attempting to wait on the bits used by the kernel
+     * itself, and that at least one bit is being requested. */
+    configASSERT( xEventGroup );
+    configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+    configASSERT( uxBitsToWaitFor != 0 );
+    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+        {
+            configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+        }
+    #endif
+
+    vTaskSuspendAll();
+    {
+        const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;
+
+        /* Check to see if the wait condition is already met or not. */
+        xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );
+
+        if( xWaitConditionMet != pdFALSE )
+        {
+            /* The wait condition has already been met so there is no need to
+             * block. */
+            uxReturn = uxCurrentEventBits;
+            xTicksToWait = ( TickType_t ) 0;
+
+            /* Clear the wait bits if requested to do so. */
+            if( xClearOnExit != pdFALSE )
+            {
+                pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else if( xTicksToWait == ( TickType_t ) 0 )
+        {
+            /* The wait condition has not been met, but no block time was
+             * specified, so just return the current value. */
+            uxReturn = uxCurrentEventBits;
+            xTimeoutOccurred = pdTRUE;
+        }
+        else
+        {
+            /* The task is going to block to wait for its required bits to be
+             * set.  uxControlBits are used to remember the specified behaviour of
+             * this call to xEventGroupWaitBits() - for use when the event bits
+             * unblock the task. */
+            if( xClearOnExit != pdFALSE )
+            {
+                uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            if( xWaitForAllBits != pdFALSE )
+            {
+                uxControlBits |= eventWAIT_FOR_ALL_BITS;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            /* Store the bits that the calling task is waiting for in the
+             * task's event list item so the kernel knows when a match is
+             * found.  Then enter the blocked state. */
+            vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );
+
+            /* This is obsolete as it will get set after the task unblocks, but
+             * some compilers mistakenly generate a warning about the variable
+             * being returned without being set if it is not done. */
+            uxReturn = 0;
+
+            traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );
+        }
+    }
+    xAlreadyYielded = xTaskResumeAll();
+
+    if( xTicksToWait != ( TickType_t ) 0 )
+    {
+        if( xAlreadyYielded == pdFALSE )
+        {
+            portYIELD_WITHIN_API();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        /* The task blocked to wait for its required bits to be set - at this
+         * point either the required bits were set or the block time expired.  If
+         * the required bits were set they will have been stored in the task's
+         * event list item, and they should now be retrieved then cleared. */
+        uxReturn = uxTaskResetEventItemValue();
+
+        if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+        {
+            taskENTER_CRITICAL();
+            {
+                /* The task timed out, just return the current event bit value. */
+                uxReturn = pxEventBits->uxEventBits;
+
+                /* It is possible that the event bits were updated between this
+                 * task leaving the Blocked state and running again. */
+                if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )
+                {
+                    if( xClearOnExit != pdFALSE )
+                    {
+                        pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                xTimeoutOccurred = pdTRUE;
+            }
+            taskEXIT_CRITICAL();
+        }
+        else
+        {
+            /* The task unblocked because the bits were set. */
+        }
+
+        /* The task blocked so control bits may have been set. */
+        uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+    }
+
+    traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );
+
+    /* Prevent compiler warnings when trace macros are not used. */
+    ( void ) xTimeoutOccurred;
+
+    return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                  const EventBits_t uxBitsToClear )
+{
+    EventGroup_t * pxEventBits = xEventGroup;
+    EventBits_t uxReturn;
+
+    /* Check the user is not attempting to clear the bits used by the kernel
+     * itself. */
+    configASSERT( xEventGroup );
+    configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+    taskENTER_CRITICAL();
+    {
+        traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );
+
+        /* The value returned is the event group value prior to the bits being
+         * cleared. */
+        uxReturn = pxEventBits->uxEventBits;
+
+        /* Clear the bits. */
+        pxEventBits->uxEventBits &= ~uxBitsToClear;
+    }
+    taskEXIT_CRITICAL();
+
+    return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+    BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToClear )
+    {
+        BaseType_t xReturn;
+
+        traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
+        xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
+
+        return xReturn;
+    }
+
+#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
+{
+    UBaseType_t uxSavedInterruptStatus;
+    EventGroup_t const * const pxEventBits = xEventGroup;
+    EventBits_t uxReturn;
+
+    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        uxReturn = pxEventBits->uxEventBits;
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+    return uxReturn;
+} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                const EventBits_t uxBitsToSet )
+{
+    ListItem_t * pxListItem, * pxNext;
+    ListItem_t const * pxListEnd;
+    List_t const * pxList;
+    EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
+    EventGroup_t * pxEventBits = xEventGroup;
+    BaseType_t xMatchFound = pdFALSE;
+
+    /* Check the user is not attempting to set the bits used by the kernel
+     * itself. */
+    configASSERT( xEventGroup );
+    configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+    pxList = &( pxEventBits->xTasksWaitingForBits );
+    pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+    vTaskSuspendAll();
+    {
+        traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
+
+        pxListItem = listGET_HEAD_ENTRY( pxList );
+
+        /* Set the bits. */
+        pxEventBits->uxEventBits |= uxBitsToSet;
+
+        /* See if the new bit value should unblock any tasks. */
+        while( pxListItem != pxListEnd )
+        {
+            pxNext = listGET_NEXT( pxListItem );
+            uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );
+            xMatchFound = pdFALSE;
+
+            /* Split the bits waited for from the control bits. */
+            uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;
+            uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;
+
+            if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )
+            {
+                /* Just looking for single bit being set. */
+                if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )
+                {
+                    xMatchFound = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )
+            {
+                /* All bits are set. */
+                xMatchFound = pdTRUE;
+            }
+            else
+            {
+                /* Need all bits to be set, but not all the bits were set. */
+            }
+
+            if( xMatchFound != pdFALSE )
+            {
+                /* The bits match.  Should the bits be cleared on exit? */
+                if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )
+                {
+                    uxBitsToClear |= uxBitsWaitedFor;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                /* Store the actual event flag value in the task's event list
+                 * item before removing the task from the event list.  The
+                 * eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows
+                 * that is was unblocked due to its required bits matching, rather
+                 * than because it timed out. */
+                vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );
+            }
+
+            /* Move onto the next list item.  Note pxListItem->pxNext is not
+             * used here as the list item may have been removed from the event list
+             * and inserted into the ready/pending reading list. */
+            pxListItem = pxNext;
+        }
+
+        /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
+         * bit was set in the control word. */
+        pxEventBits->uxEventBits &= ~uxBitsToClear;
+    }
+    ( void ) xTaskResumeAll();
+
+    return pxEventBits->uxEventBits;
+}
+/*-----------------------------------------------------------*/
+
+void vEventGroupDelete( EventGroupHandle_t xEventGroup )
+{
+    EventGroup_t * pxEventBits = xEventGroup;
+    const List_t * pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
+
+    vTaskSuspendAll();
+    {
+        traceEVENT_GROUP_DELETE( xEventGroup );
+
+        while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )
+        {
+            /* Unblock the task, returning 0 as the event list is being deleted
+             * and cannot therefore have any bits set. */
+            configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
+            vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
+        }
+
+        #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+            {
+                /* The event group can only have been allocated dynamically - free
+                 * it again. */
+                vPortFree( pxEventBits );
+            }
+        #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+            {
+                /* The event group could have been allocated statically or
+                 * dynamically, so check before attempting to free the memory. */
+                if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+                {
+                    vPortFree( pxEventBits );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+    }
+    ( void ) xTaskResumeAll();
+}
+/*-----------------------------------------------------------*/
+
+/* For internal use only - execute a 'set bits' command that was pended from
+ * an interrupt. */
+void vEventGroupSetBitsCallback( void * pvEventGroup,
+                                 const uint32_t ulBitsToSet )
+{
+    ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
+}
+/*-----------------------------------------------------------*/
+
+/* For internal use only - execute a 'clear bits' command that was pended from
+ * an interrupt. */
+void vEventGroupClearBitsCallback( void * pvEventGroup,
+                                   const uint32_t ulBitsToClear )
+{
+    ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits,
+                                        const EventBits_t uxBitsToWaitFor,
+                                        const BaseType_t xWaitForAllBits )
+{
+    BaseType_t xWaitConditionMet = pdFALSE;
+
+    if( xWaitForAllBits == pdFALSE )
+    {
+        /* Task only has to wait for one bit within uxBitsToWaitFor to be
+         * set.  Is one already set? */
+        if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )
+        {
+            xWaitConditionMet = pdTRUE;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        /* Task has to wait for all the bits in uxBitsToWaitFor to be set.
+         * Are they set already? */
+        if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )
+        {
+            xWaitConditionMet = pdTRUE;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+    return xWaitConditionMet;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+    BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToSet,
+                                          BaseType_t * pxHigherPriorityTaskWoken )
+    {
+        BaseType_t xReturn;
+
+        traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
+        xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */
+
+        return xReturn;
+    }
+
+#endif /* if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    UBaseType_t uxEventGroupGetNumber( void * xEventGroup )
+    {
+        UBaseType_t xReturn;
+        EventGroup_t const * pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
+
+        if( xEventGroup == NULL )
+        {
+            xReturn = 0;
+        }
+        else
+        {
+            xReturn = pxEventBits->uxEventGroupNumber;
+        }
+
+        return xReturn;
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    void vEventGroupSetNumber( void * xEventGroup,
+                               UBaseType_t uxEventGroupNumber )
+    {
+        ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/FreeRTOS.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/FreeRTOS.h
new file mode 100644
index 0000000..5e443a6
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/FreeRTOS.h
@@ -0,0 +1,1345 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef INC_FREERTOS_H
+#define INC_FREERTOS_H
+
+/*
+ * Include the generic headers required for the FreeRTOS port being used.
+ */
+#include <stddef.h>
+
+/*
+ * If stdint.h cannot be located then:
+ *   + If using GCC ensure the -nostdint options is *not* being used.
+ *   + Ensure the project's include path includes the directory in which your
+ *     compiler stores stdint.h.
+ *   + Set any compiler options necessary for it to support C99, as technically
+ *     stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any
+ *     other way).
+ *   + The FreeRTOS download includes a simple stdint.h definition that can be
+ *     used in cases where none is provided by the compiler.  The files only
+ *     contains the typedefs required to build FreeRTOS.  Read the instructions
+ *     in FreeRTOS/source/stdint.readme for more information.
+ */
+#include <stdint.h>     /* READ COMMENT ABOVE. */
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/* Application specific configuration options. */
+#include "FreeRTOSConfig.h"
+
+/* Basic FreeRTOS definitions. */
+#include "projdefs.h"
+
+/* Definitions specific to the port being used. */
+#include "portable.h"
+
+/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */
+#ifndef configUSE_NEWLIB_REENTRANT
+    #define configUSE_NEWLIB_REENTRANT    0
+#endif
+
+/* Required if struct _reent is used. */
+#if ( configUSE_NEWLIB_REENTRANT == 1 )
+    #include <reent.h>
+#endif
+
+/*
+ * Check all the required application specific macros have been defined.
+ * These macros are application specific and (as downloaded) are defined
+ * within FreeRTOSConfig.h.
+ */
+
+#ifndef configMINIMAL_STACK_SIZE
+    #error Missing definition:  configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h.  configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task.  Refer to the demo project provided for your port for a suitable value.
+#endif
+
+#ifndef configMAX_PRIORITIES
+    #error Missing definition:  configMAX_PRIORITIES must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#if configMAX_PRIORITIES < 1
+    #error configMAX_PRIORITIES must be defined to be greater than or equal to 1.
+#endif
+
+#ifndef configUSE_PREEMPTION
+    #error Missing definition:  configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_IDLE_HOOK
+    #error Missing definition:  configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_TICK_HOOK
+    #error Missing definition:  configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_16_BIT_TICKS
+    #error Missing definition:  configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_CO_ROUTINES
+    #define configUSE_CO_ROUTINES    0
+#endif
+
+#ifndef INCLUDE_vTaskPrioritySet
+    #define INCLUDE_vTaskPrioritySet    0
+#endif
+
+#ifndef INCLUDE_uxTaskPriorityGet
+    #define INCLUDE_uxTaskPriorityGet    0
+#endif
+
+#ifndef INCLUDE_vTaskDelete
+    #define INCLUDE_vTaskDelete    0
+#endif
+
+#ifndef INCLUDE_vTaskSuspend
+    #define INCLUDE_vTaskSuspend    0
+#endif
+
+#ifdef INCLUDE_xTaskDelayUntil
+    #ifdef INCLUDE_vTaskDelayUntil
+        /* INCLUDE_vTaskDelayUntil was replaced by INCLUDE_xTaskDelayUntil.  Backward
+         * compatibility is maintained if only one or the other is defined, but
+         * there is a conflict if both are defined. */
+        #error INCLUDE_vTaskDelayUntil and INCLUDE_xTaskDelayUntil are both defined.  INCLUDE_vTaskDelayUntil is no longer required and should be removed
+    #endif
+#endif
+
+#ifndef INCLUDE_xTaskDelayUntil
+    #ifdef INCLUDE_vTaskDelayUntil
+        /* If INCLUDE_vTaskDelayUntil is set but INCLUDE_xTaskDelayUntil is not then
+         * the project's FreeRTOSConfig.h probably pre-dates the introduction of
+         * xTaskDelayUntil and setting INCLUDE_xTaskDelayUntil to whatever
+         * INCLUDE_vTaskDelayUntil is set to will ensure backward compatibility.
+         */
+        #define INCLUDE_xTaskDelayUntil INCLUDE_vTaskDelayUntil
+    #endif
+#endif
+
+#ifndef INCLUDE_xTaskDelayUntil
+    #define INCLUDE_xTaskDelayUntil    0
+#endif
+
+#ifndef INCLUDE_vTaskDelay
+    #define INCLUDE_vTaskDelay    0
+#endif
+
+#ifndef INCLUDE_xTaskGetIdleTaskHandle
+    #define INCLUDE_xTaskGetIdleTaskHandle    0
+#endif
+
+#ifndef INCLUDE_xTaskAbortDelay
+    #define INCLUDE_xTaskAbortDelay    0
+#endif
+
+#ifndef INCLUDE_xQueueGetMutexHolder
+    #define INCLUDE_xQueueGetMutexHolder    0
+#endif
+
+#ifndef INCLUDE_xSemaphoreGetMutexHolder
+    #define INCLUDE_xSemaphoreGetMutexHolder    INCLUDE_xQueueGetMutexHolder
+#endif
+
+#ifndef INCLUDE_xTaskGetHandle
+    #define INCLUDE_xTaskGetHandle    0
+#endif
+
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark
+    #define INCLUDE_uxTaskGetStackHighWaterMark    0
+#endif
+
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark2
+    #define INCLUDE_uxTaskGetStackHighWaterMark2    0
+#endif
+
+#ifndef INCLUDE_eTaskGetState
+    #define INCLUDE_eTaskGetState    0
+#endif
+
+#ifndef INCLUDE_xTaskResumeFromISR
+    #define INCLUDE_xTaskResumeFromISR    1
+#endif
+
+#ifndef INCLUDE_xTimerPendFunctionCall
+    #define INCLUDE_xTimerPendFunctionCall    0
+#endif
+
+#ifndef INCLUDE_xTaskGetSchedulerState
+    #define INCLUDE_xTaskGetSchedulerState    0
+#endif
+
+#ifndef INCLUDE_xTaskGetCurrentTaskHandle
+    #define INCLUDE_xTaskGetCurrentTaskHandle    0
+#endif
+
+#if configUSE_CO_ROUTINES != 0
+    #ifndef configMAX_CO_ROUTINE_PRIORITIES
+        #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1.
+    #endif
+#endif
+
+#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK
+    #define configUSE_DAEMON_TASK_STARTUP_HOOK    0
+#endif
+
+#ifndef configUSE_APPLICATION_TASK_TAG
+    #define configUSE_APPLICATION_TASK_TAG    0
+#endif
+
+#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS
+    #define configNUM_THREAD_LOCAL_STORAGE_POINTERS    0
+#endif
+
+#ifndef configUSE_RECURSIVE_MUTEXES
+    #define configUSE_RECURSIVE_MUTEXES    0
+#endif
+
+#ifndef configUSE_MUTEXES
+    #define configUSE_MUTEXES    0
+#endif
+
+#ifndef configUSE_TIMERS
+    #define configUSE_TIMERS    0
+#endif
+
+#ifndef configUSE_COUNTING_SEMAPHORES
+    #define configUSE_COUNTING_SEMAPHORES    0
+#endif
+
+#ifndef configUSE_ALTERNATIVE_API
+    #define configUSE_ALTERNATIVE_API    0
+#endif
+
+#ifndef portCRITICAL_NESTING_IN_TCB
+    #define portCRITICAL_NESTING_IN_TCB    0
+#endif
+
+#ifndef configMAX_TASK_NAME_LEN
+    #define configMAX_TASK_NAME_LEN    16
+#endif
+
+#ifndef configIDLE_SHOULD_YIELD
+    #define configIDLE_SHOULD_YIELD    1
+#endif
+
+#if configMAX_TASK_NAME_LEN < 1
+    #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h
+#endif
+
+#ifndef configASSERT
+    #define configASSERT( x )
+    #define configASSERT_DEFINED    0
+#else
+    #define configASSERT_DEFINED    1
+#endif
+
+/* configPRECONDITION should be defined as configASSERT.
+ * The CBMC proofs need a way to track assumptions and assertions.
+ * A configPRECONDITION statement should express an implicit invariant or
+ * assumption made.  A configASSERT statement should express an invariant that must
+ * hold explicit before calling the code. */
+#ifndef configPRECONDITION
+    #define configPRECONDITION( X )    configASSERT( X )
+    #define configPRECONDITION_DEFINED    0
+#else
+    #define configPRECONDITION_DEFINED    1
+#endif
+
+#ifndef portMEMORY_BARRIER
+    #define portMEMORY_BARRIER()
+#endif
+
+#ifndef portSOFTWARE_BARRIER
+    #define portSOFTWARE_BARRIER()
+#endif
+
+/* The timers module relies on xTaskGetSchedulerState(). */
+#if configUSE_TIMERS == 1
+
+    #ifndef configTIMER_TASK_PRIORITY
+        #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.
+    #endif /* configTIMER_TASK_PRIORITY */
+
+    #ifndef configTIMER_QUEUE_LENGTH
+        #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.
+    #endif /* configTIMER_QUEUE_LENGTH */
+
+    #ifndef configTIMER_TASK_STACK_DEPTH
+        #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.
+    #endif /* configTIMER_TASK_STACK_DEPTH */
+
+#endif /* configUSE_TIMERS */
+
+#ifndef portSET_INTERRUPT_MASK_FROM_ISR
+    #define portSET_INTERRUPT_MASK_FROM_ISR()    0
+#endif
+
+#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue )    ( void ) uxSavedStatusValue
+#endif
+
+#ifndef portCLEAN_UP_TCB
+    #define portCLEAN_UP_TCB( pxTCB )    ( void ) pxTCB
+#endif
+
+#ifndef portPRE_TASK_DELETE_HOOK
+    #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending )
+#endif
+
+#ifndef portSETUP_TCB
+    #define portSETUP_TCB( pxTCB )    ( void ) pxTCB
+#endif
+
+#ifndef configQUEUE_REGISTRY_SIZE
+    #define configQUEUE_REGISTRY_SIZE    0U
+#endif
+
+#if ( configQUEUE_REGISTRY_SIZE < 1 )
+    #define vQueueAddToRegistry( xQueue, pcName )
+    #define vQueueUnregisterQueue( xQueue )
+    #define pcQueueGetName( xQueue )
+#endif
+
+#ifndef portPOINTER_SIZE_TYPE
+    #define portPOINTER_SIZE_TYPE    uint32_t
+#endif
+
+/* Remove any unused trace macros. */
+#ifndef traceSTART
+
+/* Used to perform any necessary initialisation - for example, open a file
+ * into which trace is to be written. */
+    #define traceSTART()
+#endif
+
+#ifndef traceEND
+
+/* Use to close a trace, for example close a file into which trace has been
+ * written. */
+    #define traceEND()
+#endif
+
+#ifndef traceTASK_SWITCHED_IN
+
+/* Called after a task has been selected to run.  pxCurrentTCB holds a pointer
+ * to the task control block of the selected task. */
+    #define traceTASK_SWITCHED_IN()
+#endif
+
+#ifndef traceINCREASE_TICK_COUNT
+
+/* Called before stepping the tick count after waking from tickless idle
+ * sleep. */
+    #define traceINCREASE_TICK_COUNT( x )
+#endif
+
+#ifndef traceLOW_POWER_IDLE_BEGIN
+    /* Called immediately before entering tickless idle. */
+    #define traceLOW_POWER_IDLE_BEGIN()
+#endif
+
+#ifndef traceLOW_POWER_IDLE_END
+    /* Called when returning to the Idle task after a tickless idle. */
+    #define traceLOW_POWER_IDLE_END()
+#endif
+
+#ifndef traceTASK_SWITCHED_OUT
+
+/* Called before a task has been selected to run.  pxCurrentTCB holds a pointer
+ * to the task control block of the task being switched out. */
+    #define traceTASK_SWITCHED_OUT()
+#endif
+
+#ifndef traceTASK_PRIORITY_INHERIT
+
+/* Called when a task attempts to take a mutex that is already held by a
+ * lower priority task.  pxTCBOfMutexHolder is a pointer to the TCB of the task
+ * that holds the mutex.  uxInheritedPriority is the priority the mutex holder
+ * will inherit (the priority of the task that is attempting to obtain the
+ * muted. */
+    #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority )
+#endif
+
+#ifndef traceTASK_PRIORITY_DISINHERIT
+
+/* Called when a task releases a mutex, the holding of which had resulted in
+ * the task inheriting the priority of a higher priority task.
+ * pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the
+ * mutex.  uxOriginalPriority is the task's configured (base) priority. */
+    #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_RECEIVE
+
+/* Task is about to block because it cannot read from a
+ * queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
+ * upon which the read was attempted.  pxCurrentTCB points to the TCB of the
+ * task that attempted the read. */
+    #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_PEEK
+
+/* Task is about to block because it cannot read from a
+ * queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
+ * upon which the read was attempted.  pxCurrentTCB points to the TCB of the
+ * task that attempted the read. */
+    #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_SEND
+
+/* Task is about to block because it cannot write to a
+ * queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
+ * upon which the write was attempted.  pxCurrentTCB points to the TCB of the
+ * task that attempted the write. */
+    #define traceBLOCKING_ON_QUEUE_SEND( pxQueue )
+#endif
+
+#ifndef configCHECK_FOR_STACK_OVERFLOW
+    #define configCHECK_FOR_STACK_OVERFLOW    0
+#endif
+
+#ifndef configRECORD_STACK_HIGH_ADDRESS
+    #define configRECORD_STACK_HIGH_ADDRESS    0
+#endif
+
+#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H
+    #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H    0
+#endif
+
+/* The following event macros are embedded in the kernel API calls. */
+
+#ifndef traceMOVED_TASK_TO_READY_STATE
+    #define traceMOVED_TASK_TO_READY_STATE( pxTCB )
+#endif
+
+#ifndef tracePOST_MOVED_TASK_TO_READY_STATE
+    #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+#endif
+
+#ifndef traceQUEUE_CREATE
+    #define traceQUEUE_CREATE( pxNewQueue )
+#endif
+
+#ifndef traceQUEUE_CREATE_FAILED
+    #define traceQUEUE_CREATE_FAILED( ucQueueType )
+#endif
+
+#ifndef traceCREATE_MUTEX
+    #define traceCREATE_MUTEX( pxNewQueue )
+#endif
+
+#ifndef traceCREATE_MUTEX_FAILED
+    #define traceCREATE_MUTEX_FAILED()
+#endif
+
+#ifndef traceGIVE_MUTEX_RECURSIVE
+    #define traceGIVE_MUTEX_RECURSIVE( pxMutex )
+#endif
+
+#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED
+    #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )
+#endif
+
+#ifndef traceTAKE_MUTEX_RECURSIVE
+    #define traceTAKE_MUTEX_RECURSIVE( pxMutex )
+#endif
+
+#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED
+    #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )
+#endif
+
+#ifndef traceCREATE_COUNTING_SEMAPHORE
+    #define traceCREATE_COUNTING_SEMAPHORE()
+#endif
+
+#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED
+    #define traceCREATE_COUNTING_SEMAPHORE_FAILED()
+#endif
+
+#ifndef traceQUEUE_SET_SEND
+    #define traceQUEUE_SET_SEND    traceQUEUE_SEND
+#endif
+
+#ifndef traceQUEUE_SEND
+    #define traceQUEUE_SEND( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FAILED
+    #define traceQUEUE_SEND_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE
+    #define traceQUEUE_RECEIVE( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK
+    #define traceQUEUE_PEEK( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FAILED
+    #define traceQUEUE_PEEK_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FROM_ISR
+    #define traceQUEUE_PEEK_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FAILED
+    #define traceQUEUE_RECEIVE_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FROM_ISR
+    #define traceQUEUE_SEND_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FROM_ISR_FAILED
+    #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FROM_ISR
+    #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED
+    #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED
+    #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_DELETE
+    #define traceQUEUE_DELETE( pxQueue )
+#endif
+
+#ifndef traceTASK_CREATE
+    #define traceTASK_CREATE( pxNewTCB )
+#endif
+
+#ifndef traceTASK_CREATE_FAILED
+    #define traceTASK_CREATE_FAILED()
+#endif
+
+#ifndef traceTASK_DELETE
+    #define traceTASK_DELETE( pxTaskToDelete )
+#endif
+
+#ifndef traceTASK_DELAY_UNTIL
+    #define traceTASK_DELAY_UNTIL( x )
+#endif
+
+#ifndef traceTASK_DELAY
+    #define traceTASK_DELAY()
+#endif
+
+#ifndef traceTASK_PRIORITY_SET
+    #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )
+#endif
+
+#ifndef traceTASK_SUSPEND
+    #define traceTASK_SUSPEND( pxTaskToSuspend )
+#endif
+
+#ifndef traceTASK_RESUME
+    #define traceTASK_RESUME( pxTaskToResume )
+#endif
+
+#ifndef traceTASK_RESUME_FROM_ISR
+    #define traceTASK_RESUME_FROM_ISR( pxTaskToResume )
+#endif
+
+#ifndef traceTASK_INCREMENT_TICK
+    #define traceTASK_INCREMENT_TICK( xTickCount )
+#endif
+
+#ifndef traceTIMER_CREATE
+    #define traceTIMER_CREATE( pxNewTimer )
+#endif
+
+#ifndef traceTIMER_CREATE_FAILED
+    #define traceTIMER_CREATE_FAILED()
+#endif
+
+#ifndef traceTIMER_COMMAND_SEND
+    #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )
+#endif
+
+#ifndef traceTIMER_EXPIRED
+    #define traceTIMER_EXPIRED( pxTimer )
+#endif
+
+#ifndef traceTIMER_COMMAND_RECEIVED
+    #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )
+#endif
+
+#ifndef traceMALLOC
+    #define traceMALLOC( pvAddress, uiSize )
+#endif
+
+#ifndef traceFREE
+    #define traceFREE( pvAddress, uiSize )
+#endif
+
+#ifndef traceEVENT_GROUP_CREATE
+    #define traceEVENT_GROUP_CREATE( xEventGroup )
+#endif
+
+#ifndef traceEVENT_GROUP_CREATE_FAILED
+    #define traceEVENT_GROUP_CREATE_FAILED()
+#endif
+
+#ifndef traceEVENT_GROUP_SYNC_BLOCK
+    #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor )
+#endif
+
+#ifndef traceEVENT_GROUP_SYNC_END
+    #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred )    ( void ) xTimeoutOccurred
+#endif
+
+#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK
+    #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor )
+#endif
+
+#ifndef traceEVENT_GROUP_WAIT_BITS_END
+    #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred )    ( void ) xTimeoutOccurred
+#endif
+
+#ifndef traceEVENT_GROUP_CLEAR_BITS
+    #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR
+    #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceEVENT_GROUP_SET_BITS
+    #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR
+    #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceEVENT_GROUP_DELETE
+    #define traceEVENT_GROUP_DELETE( xEventGroup )
+#endif
+
+#ifndef tracePEND_FUNC_CALL
+    #define tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, ret )
+#endif
+
+#ifndef tracePEND_FUNC_CALL_FROM_ISR
+    #define tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, ret )
+#endif
+
+#ifndef traceQUEUE_REGISTRY_ADD
+    #define traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName )
+#endif
+
+#ifndef traceTASK_NOTIFY_TAKE_BLOCK
+    #define traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait )
+#endif
+
+#ifndef traceTASK_NOTIFY_TAKE
+    #define traceTASK_NOTIFY_TAKE( uxIndexToWait )
+#endif
+
+#ifndef traceTASK_NOTIFY_WAIT_BLOCK
+    #define traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait )
+#endif
+
+#ifndef traceTASK_NOTIFY_WAIT
+    #define traceTASK_NOTIFY_WAIT( uxIndexToWait )
+#endif
+
+#ifndef traceTASK_NOTIFY
+    #define traceTASK_NOTIFY( uxIndexToNotify )
+#endif
+
+#ifndef traceTASK_NOTIFY_FROM_ISR
+    #define traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify )
+#endif
+
+#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR
+    #define traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify )
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE_FAILED
+    #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED
+    #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_CREATE
+    #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_DELETE
+    #define traceSTREAM_BUFFER_DELETE( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RESET
+    #define traceSTREAM_BUFFER_RESET( xStreamBuffer )
+#endif
+
+#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND
+    #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND
+    #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND_FAILED
+    #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR
+    #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent )
+#endif
+
+#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE
+    #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE
+    #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED
+    #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer )
+#endif
+
+#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR
+    #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength )
+#endif
+
+#ifndef configGENERATE_RUN_TIME_STATS
+    #define configGENERATE_RUN_TIME_STATS    0
+#endif
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+    #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
+        #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined.  portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.
+    #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */
+
+    #ifndef portGET_RUN_TIME_COUNTER_VALUE
+        #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE
+            #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined.  See the examples provided and the FreeRTOS web site for more information.
+        #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */
+    #endif /* portGET_RUN_TIME_COUNTER_VALUE */
+
+#endif /* configGENERATE_RUN_TIME_STATS */
+
+#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
+    #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
+#endif
+
+#ifndef configUSE_MALLOC_FAILED_HOOK
+    #define configUSE_MALLOC_FAILED_HOOK    0
+#endif
+
+#ifndef portPRIVILEGE_BIT
+    #define portPRIVILEGE_BIT    ( ( UBaseType_t ) 0x00 )
+#endif
+
+#ifndef portYIELD_WITHIN_API
+    #define portYIELD_WITHIN_API    portYIELD
+#endif
+
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )
+#endif
+
+#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP
+    #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP    2
+#endif
+
+#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2
+    #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2
+#endif
+
+#ifndef configUSE_TICKLESS_IDLE
+    #define configUSE_TICKLESS_IDLE    0
+#endif
+
+#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING
+    #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configPRE_SLEEP_PROCESSING
+    #define configPRE_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configPOST_SLEEP_PROCESSING
+    #define configPOST_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configUSE_QUEUE_SETS
+    #define configUSE_QUEUE_SETS    0
+#endif
+
+#ifndef portTASK_USES_FLOATING_POINT
+    #define portTASK_USES_FLOATING_POINT()
+#endif
+
+#ifndef portALLOCATE_SECURE_CONTEXT
+    #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+#endif
+
+#ifndef portDONT_DISCARD
+    #define portDONT_DISCARD
+#endif
+
+#ifndef configUSE_TIME_SLICING
+    #define configUSE_TIME_SLICING    1
+#endif
+
+#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
+    #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS    0
+#endif
+
+#ifndef configUSE_STATS_FORMATTING_FUNCTIONS
+    #define configUSE_STATS_FORMATTING_FUNCTIONS    0
+#endif
+
+#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()
+#endif
+
+#ifndef configUSE_TRACE_FACILITY
+    #define configUSE_TRACE_FACILITY    0
+#endif
+
+#ifndef mtCOVERAGE_TEST_MARKER
+    #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+#ifndef mtCOVERAGE_TEST_DELAY
+    #define mtCOVERAGE_TEST_DELAY()
+#endif
+
+#ifndef portASSERT_IF_IN_ISR
+    #define portASSERT_IF_IN_ISR()
+#endif
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    0
+#endif
+
+#ifndef configAPPLICATION_ALLOCATED_HEAP
+    #define configAPPLICATION_ALLOCATED_HEAP    0
+#endif
+
+#ifndef configUSE_TASK_NOTIFICATIONS
+    #define configUSE_TASK_NOTIFICATIONS    1
+#endif
+
+#ifndef configTASK_NOTIFICATION_ARRAY_ENTRIES
+    #define configTASK_NOTIFICATION_ARRAY_ENTRIES    1
+#endif
+
+#if configTASK_NOTIFICATION_ARRAY_ENTRIES < 1
+    #error configTASK_NOTIFICATION_ARRAY_ENTRIES must be at least 1
+#endif
+
+#ifndef configUSE_POSIX_ERRNO
+    #define configUSE_POSIX_ERRNO    0
+#endif
+
+#ifndef portTICK_TYPE_IS_ATOMIC
+    #define portTICK_TYPE_IS_ATOMIC    0
+#endif
+
+#ifndef configSUPPORT_STATIC_ALLOCATION
+    /* Defaults to 0 for backward compatibility. */
+    #define configSUPPORT_STATIC_ALLOCATION    0
+#endif
+
+#ifndef configSUPPORT_DYNAMIC_ALLOCATION
+    /* Defaults to 1 for backward compatibility. */
+    #define configSUPPORT_DYNAMIC_ALLOCATION    1
+#endif
+
+#ifndef configSTACK_DEPTH_TYPE
+
+/* Defaults to uint16_t for backward compatibility, but can be overridden
+ * in FreeRTOSConfig.h if uint16_t is too restrictive. */
+    #define configSTACK_DEPTH_TYPE    uint16_t
+#endif
+
+#ifndef configMESSAGE_BUFFER_LENGTH_TYPE
+
+/* Defaults to size_t for backward compatibility, but can be overridden
+ * in FreeRTOSConfig.h if lengths will always be less than the number of bytes
+ * in a size_t. */
+    #define configMESSAGE_BUFFER_LENGTH_TYPE    size_t
+#endif
+
+/* Sanity check the configuration. */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+    #if ( INCLUDE_vTaskSuspend != 1 )
+        #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0
+    #endif /* INCLUDE_vTaskSuspend */
+#endif /* configUSE_TICKLESS_IDLE */
+
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
+    #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1.
+#endif
+
+#if ( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) )
+    #error configUSE_MUTEXES must be set to 1 to use recursive mutexes
+#endif
+
+#ifndef configINITIAL_TICK_COUNT
+    #define configINITIAL_TICK_COUNT    0
+#endif
+
+#if ( portTICK_TYPE_IS_ATOMIC == 0 )
+
+/* Either variables of tick type cannot be read atomically, or
+ * portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when
+ * the tick count is returned to the standard critical section macros. */
+    #define portTICK_TYPE_ENTER_CRITICAL()                      portENTER_CRITICAL()
+    #define portTICK_TYPE_EXIT_CRITICAL()                       portEXIT_CRITICAL()
+    #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR()         portSET_INTERRUPT_MASK_FROM_ISR()
+    #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x )    portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) )
+#else
+
+/* The tick type can be read atomically, so critical sections used when the
+ * tick count is returned can be defined away. */
+    #define portTICK_TYPE_ENTER_CRITICAL()
+    #define portTICK_TYPE_EXIT_CRITICAL()
+    #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR()         0
+    #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x )    ( void ) x
+#endif /* if ( portTICK_TYPE_IS_ATOMIC == 0 ) */
+
+/* Definitions to allow backward compatibility with FreeRTOS versions prior to
+ * V8 if desired. */
+#ifndef configENABLE_BACKWARD_COMPATIBILITY
+    #define configENABLE_BACKWARD_COMPATIBILITY    1
+#endif
+
+#ifndef configPRINTF
+
+/* configPRINTF() was not defined, so define it away to nothing.  To use
+ * configPRINTF() then define it as follows (where MyPrintFunction() is
+ * provided by the application writer):
+ *
+ * void MyPrintFunction(const char *pcFormat, ... );
+ #define configPRINTF( X )   MyPrintFunction X
+ *
+ * Then call like a standard printf() function, but placing brackets around
+ * all parameters so they are passed as a single parameter.  For example:
+ * configPRINTF( ("Value = %d", MyVariable) ); */
+    #define configPRINTF( X )
+#endif
+
+#ifndef configMAX
+
+/* The application writer has not provided their own MAX macro, so define
+ * the following generic implementation. */
+    #define configMAX( a, b )    ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) )
+#endif
+
+#ifndef configMIN
+
+/* The application writer has not provided their own MAX macro, so define
+ * the following generic implementation. */
+    #define configMIN( a, b )    ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) )
+#endif
+
+#if configENABLE_BACKWARD_COMPATIBILITY == 1
+    #define eTaskStateGet                 eTaskGetState
+    #define portTickType                  TickType_t
+    #define xTaskHandle                   TaskHandle_t
+    #define xQueueHandle                  QueueHandle_t
+    #define xSemaphoreHandle              SemaphoreHandle_t
+    #define xQueueSetHandle               QueueSetHandle_t
+    #define xQueueSetMemberHandle         QueueSetMemberHandle_t
+    #define xTimeOutType                  TimeOut_t
+    #define xMemoryRegion                 MemoryRegion_t
+    #define xTaskParameters               TaskParameters_t
+    #define xTaskStatusType               TaskStatus_t
+    #define xTimerHandle                  TimerHandle_t
+    #define xCoRoutineHandle              CoRoutineHandle_t
+    #define pdTASK_HOOK_CODE              TaskHookFunction_t
+    #define portTICK_RATE_MS              portTICK_PERIOD_MS
+    #define pcTaskGetTaskName             pcTaskGetName
+    #define pcTimerGetTimerName           pcTimerGetName
+    #define pcQueueGetQueueName           pcQueueGetName
+    #define vTaskGetTaskInfo              vTaskGetInfo
+    #define xTaskGetIdleRunTimeCounter    ulTaskGetIdleRunTimeCounter
+
+/* Backward compatibility within the scheduler code only - these definitions
+ * are not really required but are included for completeness. */
+    #define tmrTIMER_CALLBACK             TimerCallbackFunction_t
+    #define pdTASK_CODE                   TaskFunction_t
+    #define xListItem                     ListItem_t
+    #define xList                         List_t
+
+/* For libraries that break the list data hiding, and access list structure
+ * members directly (which is not supposed to be done). */
+    #define pxContainer                   pvContainer
+#endif /* configENABLE_BACKWARD_COMPATIBILITY */
+
+#if ( configUSE_ALTERNATIVE_API != 0 )
+    #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0
+#endif
+
+/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even
+ * if floating point hardware is otherwise supported by the FreeRTOS port in use.
+ * This constant is not supported by all FreeRTOS ports that include floating
+ * point support. */
+#ifndef configUSE_TASK_FPU_SUPPORT
+    #define configUSE_TASK_FPU_SUPPORT    1
+#endif
+
+/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is
+ * currently used in ARMv8M ports. */
+#ifndef configENABLE_MPU
+    #define configENABLE_MPU    0
+#endif
+
+/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is
+ * currently used in ARMv8M ports. */
+#ifndef configENABLE_FPU
+    #define configENABLE_FPU    1
+#endif
+
+/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it.
+ * This is currently used in ARMv8M ports. */
+#ifndef configENABLE_TRUSTZONE
+    #define configENABLE_TRUSTZONE    1
+#endif
+
+/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on
+ * the Secure Side only. */
+#ifndef configRUN_FREERTOS_SECURE_ONLY
+    #define configRUN_FREERTOS_SECURE_ONLY    0
+#endif
+
+/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
+ * dynamically allocated RAM, in which case when any task is deleted it is known
+ * that both the task's stack and TCB need to be freed.  Sometimes the
+ * FreeRTOSConfig.h settings only allow a task to be created using statically
+ * allocated RAM, in which case when any task is deleted it is known that neither
+ * the task's stack or TCB should be freed.  Sometimes the FreeRTOSConfig.h
+ * settings allow a task to be created using either statically or dynamically
+ * allocated RAM, in which case a member of the TCB is used to record whether the
+ * stack and/or TCB were allocated statically or dynamically, so when a task is
+ * deleted the RAM that was allocated dynamically is freed again and no attempt is
+ * made to free the RAM that was allocated statically.
+ * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a
+ * task to be created using either statically or dynamically allocated RAM.  Note
+ * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with
+ * a statically allocated stack and a dynamically allocated TCB.
+ *
+ * The following table lists various combinations of portUSING_MPU_WRAPPERS,
+ * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and
+ * when it is possible to have both static and dynamic allocation:
+ *  +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ * | MPU | Dynamic | Static |     Available Functions     |       Possible Allocations        | Both Dynamic and | Need Free |
+ * |     |         |        |                             |                                   | Static Possible  |           |
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ * | 0   | 0       | 1      | xTaskCreateStatic           | TCB - Static, Stack - Static      | No               | No        |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 0   | 1       | 0      | xTaskCreate                 | TCB - Dynamic, Stack - Dynamic    | No               | Yes       |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 0   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateStatic           | 2. TCB - Static, Stack - Static   |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 0       | 1      | xTaskCreateStatic,          | TCB - Static, Stack - Static      | No               | No        |
+ * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 1       | 0      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateRestricted       | 2. TCB - Dynamic, Stack - Static  |                  |           |
+ * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------|
+ * | 1   | 1       | 1      | xTaskCreate,                | 1. TCB - Dynamic, Stack - Dynamic | Yes              | Yes       |
+ * |     |         |        | xTaskCreateStatic,          | 2. TCB - Dynamic, Stack - Static  |                  |           |
+ * |     |         |        | xTaskCreateRestricted,      | 3. TCB - Static, Stack - Static   |                  |           |
+ * |     |         |        | xTaskCreateRestrictedStatic |                                   |                  |           |
+ * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+
+ */
+#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE                                                                                     \
+    ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \
+      ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) )
+
+/*
+ * In line with software engineering best practice, FreeRTOS implements a strict
+ * data hiding policy, so the real structures used by FreeRTOS to maintain the
+ * state of tasks, queues, semaphores, etc. are not accessible to the application
+ * code.  However, if the application writer wants to statically allocate such
+ * an object then the size of the object needs to be know.  Dummy structures
+ * that are guaranteed to have the same size and alignment requirements of the
+ * real objects are used for this purpose.  The dummy list and list item
+ * structures below are used for inclusion in such a dummy structure.
+ */
+struct xSTATIC_LIST_ITEM
+{
+    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+        TickType_t xDummy1;
+    #endif
+    TickType_t xDummy2;
+    void * pvDummy3[ 4 ];
+    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+        TickType_t xDummy4;
+    #endif
+};
+typedef struct xSTATIC_LIST_ITEM StaticListItem_t;
+
+/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
+struct xSTATIC_MINI_LIST_ITEM
+{
+    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+        TickType_t xDummy1;
+    #endif
+    TickType_t xDummy2;
+    void * pvDummy3[ 2 ];
+};
+typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t;
+
+/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
+typedef struct xSTATIC_LIST
+{
+    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+        TickType_t xDummy1;
+    #endif
+    UBaseType_t uxDummy2;
+    void * pvDummy3;
+    StaticMiniListItem_t xDummy4;
+    #if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 )
+        TickType_t xDummy5;
+    #endif
+} StaticList_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the Task structure used internally by
+ * FreeRTOS is not accessible to application code.  However, if the application
+ * writer wants to statically allocate the memory required to create a task then
+ * the size of the task object needs to be know.  The StaticTask_t structure
+ * below is provided for this purpose.  Its sizes and alignment requirements are
+ * guaranteed to match those of the genuine structure, no matter which
+ * architecture is being used, and no matter how the values in FreeRTOSConfig.h
+ * are set.  Its contents are somewhat obfuscated in the hope users will
+ * recognise that it would be unwise to make direct use of the structure members.
+ */
+typedef struct xSTATIC_TCB
+{
+    void * pxDummy1;
+    #if ( portUSING_MPU_WRAPPERS == 1 )
+        xMPU_SETTINGS xDummy2;
+    #endif
+    StaticListItem_t xDummy3[ 2 ];
+    UBaseType_t uxDummy5;
+    void * pxDummy6;
+    uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ];
+    #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+        void * pxDummy8;
+    #endif
+    #if ( portCRITICAL_NESTING_IN_TCB == 1 )
+        UBaseType_t uxDummy9;
+    #endif
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxDummy10[ 2 ];
+    #endif
+    #if ( configUSE_MUTEXES == 1 )
+        UBaseType_t uxDummy12[ 2 ];
+    #endif
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+        void * pxDummy14;
+    #endif
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+        void * pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+    #endif
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
+        uint32_t ulDummy16;
+    #endif
+    #if ( configUSE_NEWLIB_REENTRANT == 1 )
+        struct  _reent xDummy17;
+    #endif
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+        uint32_t ulDummy18[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];
+        uint8_t ucDummy19[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];
+    #endif
+    #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+        uint8_t uxDummy20;
+    #endif
+
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
+        uint8_t ucDummy21;
+    #endif
+    #if ( configUSE_POSIX_ERRNO == 1 )
+        int iDummy22;
+    #endif
+} StaticTask_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the Queue structure used internally by
+ * FreeRTOS is not accessible to application code.  However, if the application
+ * writer wants to statically allocate the memory required to create a queue
+ * then the size of the queue object needs to be know.  The StaticQueue_t
+ * structure below is provided for this purpose.  Its sizes and alignment
+ * requirements are guaranteed to match those of the genuine structure, no
+ * matter which architecture is being used, and no matter how the values in
+ * FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in the hope
+ * users will recognise that it would be unwise to make direct use of the
+ * structure members.
+ */
+typedef struct xSTATIC_QUEUE
+{
+    void * pvDummy1[ 3 ];
+
+    union
+    {
+        void * pvDummy2;
+        UBaseType_t uxDummy2;
+    } u;
+
+    StaticList_t xDummy3[ 2 ];
+    UBaseType_t uxDummy4[ 3 ];
+    uint8_t ucDummy5[ 2 ];
+
+    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+        uint8_t ucDummy6;
+    #endif
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+        void * pvDummy7;
+    #endif
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxDummy8;
+        uint8_t ucDummy9;
+    #endif
+} StaticQueue_t;
+typedef StaticQueue_t StaticSemaphore_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the event group structure used
+ * internally by FreeRTOS is not accessible to application code.  However, if
+ * the application writer wants to statically allocate the memory required to
+ * create an event group then the size of the event group object needs to be
+ * know.  The StaticEventGroup_t structure below is provided for this purpose.
+ * Its sizes and alignment requirements are guaranteed to match those of the
+ * genuine structure, no matter which architecture is being used, and no matter
+ * how the values in FreeRTOSConfig.h are set.  Its contents are somewhat
+ * obfuscated in the hope users will recognise that it would be unwise to make
+ * direct use of the structure members.
+ */
+typedef struct xSTATIC_EVENT_GROUP
+{
+    TickType_t xDummy1;
+    StaticList_t xDummy2;
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxDummy3;
+    #endif
+
+    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+        uint8_t ucDummy4;
+    #endif
+} StaticEventGroup_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the software timer structure used
+ * internally by FreeRTOS is not accessible to application code.  However, if
+ * the application writer wants to statically allocate the memory required to
+ * create a software timer then the size of the queue object needs to be know.
+ * The StaticTimer_t structure below is provided for this purpose.  Its sizes
+ * and alignment requirements are guaranteed to match those of the genuine
+ * structure, no matter which architecture is being used, and no matter how the
+ * values in FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in
+ * the hope users will recognise that it would be unwise to make direct use of
+ * the structure members.
+ */
+typedef struct xSTATIC_TIMER
+{
+    void * pvDummy1;
+    StaticListItem_t xDummy2;
+    TickType_t xDummy3;
+    void * pvDummy5;
+    TaskFunction_t pvDummy6;
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxDummy7;
+    #endif
+    uint8_t ucDummy8;
+} StaticTimer_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the stream buffer structure used
+ * internally by FreeRTOS is not accessible to application code.  However, if
+ * the application writer wants to statically allocate the memory required to
+ * create a stream buffer then the size of the stream buffer object needs to be
+ * know.  The StaticStreamBuffer_t structure below is provided for this purpose.
+ * Its size and alignment requirements are guaranteed to match those of the
+ * genuine structure, no matter which architecture is being used, and no matter
+ * how the values in FreeRTOSConfig.h are set.  Its contents are somewhat
+ * obfuscated in the hope users will recognise that it would be unwise to make
+ * direct use of the structure members.
+ */
+typedef struct xSTATIC_STREAM_BUFFER
+{
+    size_t uxDummy1[ 4 ];
+    void * pvDummy2[ 3 ];
+    uint8_t ucDummy3;
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxDummy4;
+    #endif
+} StaticStreamBuffer_t;
+
+/* Message buffers are built on stream buffers. */
+typedef StaticStreamBuffer_t StaticMessageBuffer_t;
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* INC_FREERTOS_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/StackMacros.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/StackMacros.h
new file mode 100644
index 0000000..dde8136
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/StackMacros.h
@@ -0,0 +1,32 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef _MSC_VER /* Visual Studio doesn't support #warning. */
+    #warning The name of this file has changed to stack_macros.h.  Please update your code accordingly.  This source file (which has the original name) will be removed in future released.
+#endif
+
+#include "stack_macros.h"
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/atomic.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/atomic.h
new file mode 100644
index 0000000..cd1fd1b
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/atomic.h
@@ -0,0 +1,417 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/**
+ * @file atomic.h
+ * @brief FreeRTOS atomic operation support.
+ *
+ * This file implements atomic functions by disabling interrupts globally.
+ * Implementations with architecture specific atomic instructions can be
+ * provided under each compiler directory.
+ */
+
+#ifndef ATOMIC_H
+#define ATOMIC_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h must appear in source files before include atomic.h"
+#endif
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*
+ * Port specific definitions -- entering/exiting critical section.
+ * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h
+ *
+ * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with
+ * ATOMIC_ENTER_CRITICAL().
+ *
+ */
+#if defined( portSET_INTERRUPT_MASK_FROM_ISR )
+
+/* Nested interrupt scheme is supported in this port. */
+    #define ATOMIC_ENTER_CRITICAL() \
+    UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR()
+
+    #define ATOMIC_EXIT_CRITICAL() \
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType )
+
+#else
+
+/* Nested interrupt scheme is NOT supported in this port. */
+    #define ATOMIC_ENTER_CRITICAL()    portENTER_CRITICAL()
+    #define ATOMIC_EXIT_CRITICAL()     portEXIT_CRITICAL()
+
+#endif /* portSET_INTERRUPT_MASK_FROM_ISR() */
+
+/*
+ * Port specific definition -- "always inline".
+ * Inline is compiler specific, and may not always get inlined depending on your
+ * optimization level.  Also, inline is considered as performance optimization
+ * for atomic.  Thus, if portFORCE_INLINE is not provided by portmacro.h,
+ * instead of resulting error, simply define it away.
+ */
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE
+#endif
+
+#define ATOMIC_COMPARE_AND_SWAP_SUCCESS    0x1U     /**< Compare and swap succeeded, swapped. */
+#define ATOMIC_COMPARE_AND_SWAP_FAILURE    0x0U     /**< Compare and swap failed, did not swap. */
+
+/*----------------------------- Swap && CAS ------------------------------*/
+
+/**
+ * Atomic compare-and-swap
+ *
+ * @brief Performs an atomic compare-and-swap operation on the specified values.
+ *
+ * @param[in, out] pulDestination  Pointer to memory location from where value is
+ *                               to be loaded and checked.
+ * @param[in] ulExchange         If condition meets, write this value to memory.
+ * @param[in] ulComparand        Swap condition.
+ *
+ * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.
+ *
+ * @note This function only swaps *pulDestination with ulExchange, if previous
+ *       *pulDestination value equals ulComparand.
+ */
+static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( uint32_t volatile * pulDestination,
+                                                            uint32_t ulExchange,
+                                                            uint32_t ulComparand )
+{
+    uint32_t ulReturnValue;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        if( *pulDestination == ulComparand )
+        {
+            *pulDestination = ulExchange;
+            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
+        }
+        else
+        {
+            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
+        }
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulReturnValue;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic swap (pointers)
+ *
+ * @brief Atomically sets the address pointed to by *ppvDestination to the value
+ *        of *pvExchange.
+ *
+ * @param[in, out] ppvDestination  Pointer to memory location from where a pointer
+ *                                 value is to be loaded and written back to.
+ * @param[in] pvExchange           Pointer value to be written to *ppvDestination.
+ *
+ * @return The initial value of *ppvDestination.
+ */
+static portFORCE_INLINE void * Atomic_SwapPointers_p32( void * volatile * ppvDestination,
+                                                        void * pvExchange )
+{
+    void * pReturnValue;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        pReturnValue = *ppvDestination;
+        *ppvDestination = pvExchange;
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return pReturnValue;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic compare-and-swap (pointers)
+ *
+ * @brief Performs an atomic compare-and-swap operation on the specified pointer
+ *        values.
+ *
+ * @param[in, out] ppvDestination  Pointer to memory location from where a pointer
+ *                                 value is to be loaded and checked.
+ * @param[in] pvExchange           If condition meets, write this value to memory.
+ * @param[in] pvComparand          Swap condition.
+ *
+ * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped.
+ *
+ * @note This function only swaps *ppvDestination with pvExchange, if previous
+ *       *ppvDestination value equals pvComparand.
+ */
+static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( void * volatile * ppvDestination,
+                                                                    void * pvExchange,
+                                                                    void * pvComparand )
+{
+    uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        if( *ppvDestination == pvComparand )
+        {
+            *ppvDestination = pvExchange;
+            ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS;
+        }
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulReturnValue;
+}
+
+
+/*----------------------------- Arithmetic ------------------------------*/
+
+/**
+ * Atomic add
+ *
+ * @brief Atomically adds count to the value of the specified pointer points to.
+ *
+ * @param[in,out] pulAddend  Pointer to memory location from where value is to be
+ *                         loaded and written back to.
+ * @param[in] ulCount      Value to be added to *pulAddend.
+ *
+ * @return previous *pulAddend value.
+ */
+static portFORCE_INLINE uint32_t Atomic_Add_u32( uint32_t volatile * pulAddend,
+                                                 uint32_t ulCount )
+{
+    uint32_t ulCurrent;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulAddend;
+        *pulAddend += ulCount;
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic subtract
+ *
+ * @brief Atomically subtracts count from the value of the specified pointer
+ *        pointers to.
+ *
+ * @param[in,out] pulAddend  Pointer to memory location from where value is to be
+ *                         loaded and written back to.
+ * @param[in] ulCount      Value to be subtract from *pulAddend.
+ *
+ * @return previous *pulAddend value.
+ */
+static portFORCE_INLINE uint32_t Atomic_Subtract_u32( uint32_t volatile * pulAddend,
+                                                      uint32_t ulCount )
+{
+    uint32_t ulCurrent;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulAddend;
+        *pulAddend -= ulCount;
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic increment
+ *
+ * @brief Atomically increments the value of the specified pointer points to.
+ *
+ * @param[in,out] pulAddend  Pointer to memory location from where value is to be
+ *                         loaded and written back to.
+ *
+ * @return *pulAddend value before increment.
+ */
+static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pulAddend )
+{
+    uint32_t ulCurrent;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulAddend;
+        *pulAddend += 1;
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic decrement
+ *
+ * @brief Atomically decrements the value of the specified pointer points to
+ *
+ * @param[in,out] pulAddend  Pointer to memory location from where value is to be
+ *                         loaded and written back to.
+ *
+ * @return *pulAddend value before decrement.
+ */
+static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pulAddend )
+{
+    uint32_t ulCurrent;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulAddend;
+        *pulAddend -= 1;
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulCurrent;
+}
+
+/*----------------------------- Bitwise Logical ------------------------------*/
+
+/**
+ * Atomic OR
+ *
+ * @brief Performs an atomic OR operation on the specified values.
+ *
+ * @param [in, out] pulDestination  Pointer to memory location from where value is
+ *                                to be loaded and written back to.
+ * @param [in] ulValue            Value to be ORed with *pulDestination.
+ *
+ * @return The original value of *pulDestination.
+ */
+static portFORCE_INLINE uint32_t Atomic_OR_u32( uint32_t volatile * pulDestination,
+                                                uint32_t ulValue )
+{
+    uint32_t ulCurrent;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulDestination;
+        *pulDestination |= ulValue;
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic AND
+ *
+ * @brief Performs an atomic AND operation on the specified values.
+ *
+ * @param [in, out] pulDestination  Pointer to memory location from where value is
+ *                                to be loaded and written back to.
+ * @param [in] ulValue            Value to be ANDed with *pulDestination.
+ *
+ * @return The original value of *pulDestination.
+ */
+static portFORCE_INLINE uint32_t Atomic_AND_u32( uint32_t volatile * pulDestination,
+                                                 uint32_t ulValue )
+{
+    uint32_t ulCurrent;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulDestination;
+        *pulDestination &= ulValue;
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic NAND
+ *
+ * @brief Performs an atomic NAND operation on the specified values.
+ *
+ * @param [in, out] pulDestination  Pointer to memory location from where value is
+ *                                to be loaded and written back to.
+ * @param [in] ulValue            Value to be NANDed with *pulDestination.
+ *
+ * @return The original value of *pulDestination.
+ */
+static portFORCE_INLINE uint32_t Atomic_NAND_u32( uint32_t volatile * pulDestination,
+                                                  uint32_t ulValue )
+{
+    uint32_t ulCurrent;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulDestination;
+        *pulDestination = ~( ulCurrent & ulValue );
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulCurrent;
+}
+/*-----------------------------------------------------------*/
+
+/**
+ * Atomic XOR
+ *
+ * @brief Performs an atomic XOR operation on the specified values.
+ *
+ * @param [in, out] pulDestination  Pointer to memory location from where value is
+ *                                to be loaded and written back to.
+ * @param [in] ulValue            Value to be XORed with *pulDestination.
+ *
+ * @return The original value of *pulDestination.
+ */
+static portFORCE_INLINE uint32_t Atomic_XOR_u32( uint32_t volatile * pulDestination,
+                                                 uint32_t ulValue )
+{
+    uint32_t ulCurrent;
+
+    ATOMIC_ENTER_CRITICAL();
+    {
+        ulCurrent = *pulDestination;
+        *pulDestination ^= ulValue;
+    }
+    ATOMIC_EXIT_CRITICAL();
+
+    return ulCurrent;
+}
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* ATOMIC_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/croutine.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/croutine.h
new file mode 100644
index 0000000..4e7b534
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/croutine.h
@@ -0,0 +1,751 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef CO_ROUTINE_H
+#define CO_ROUTINE_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h must appear in source files before include croutine.h"
+#endif
+
+#include "list.h"
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/* Used to hide the implementation of the co-routine control block.  The
+ * control block structure however has to be included in the header due to
+ * the macro implementation of the co-routine functionality. */
+typedef void * CoRoutineHandle_t;
+
+/* Defines the prototype to which co-routine functions must conform. */
+typedef void (* crCOROUTINE_CODE)( CoRoutineHandle_t,
+                                   UBaseType_t );
+
+typedef struct corCoRoutineControlBlock
+{
+    crCOROUTINE_CODE pxCoRoutineFunction;
+    ListItem_t xGenericListItem; /*< List item used to place the CRCB in ready and blocked queues. */
+    ListItem_t xEventListItem;   /*< List item used to place the CRCB in event lists. */
+    UBaseType_t uxPriority;      /*< The priority of the co-routine in relation to other co-routines. */
+    UBaseType_t uxIndex;         /*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */
+    uint16_t uxState;            /*< Used internally by the co-routine implementation. */
+} CRCB_t;                        /* Co-routine control block.  Note must be identical in size down to uxPriority with TCB_t. */
+
+/**
+ * croutine. h
+ * <pre>
+ * BaseType_t xCoRoutineCreate(
+ *                               crCOROUTINE_CODE pxCoRoutineCode,
+ *                               UBaseType_t uxPriority,
+ *                               UBaseType_t uxIndex
+ *                             ); 
+ * </pre>
+ *
+ * Create a new co-routine and add it to the list of co-routines that are
+ * ready to run.
+ *
+ * @param pxCoRoutineCode Pointer to the co-routine function.  Co-routine
+ * functions require special syntax - see the co-routine section of the WEB
+ * documentation for more information.
+ *
+ * @param uxPriority The priority with respect to other co-routines at which
+ *  the co-routine will run.
+ *
+ * @param uxIndex Used to distinguish between different co-routines that
+ * execute the same function.  See the example below and the co-routine section
+ * of the WEB documentation for further information.
+ *
+ * @return pdPASS if the co-routine was successfully created and added to a ready
+ * list, otherwise an error code defined with ProjDefs.h.
+ *
+ * Example usage:
+ * <pre>
+ * // Co-routine to be created.
+ * void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * // This may not be necessary for const variables.
+ * static const char cLedToFlash[ 2 ] = { 5, 6 };
+ * static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *       // This co-routine just delays for a fixed period, then toggles
+ *       // an LED.  Two co-routines are created using this function, so
+ *       // the uxIndex parameter is used to tell the co-routine which
+ *       // LED to flash and how int32_t to delay.  This assumes xQueue has
+ *       // already been created.
+ *       vParTestToggleLED( cLedToFlash[ uxIndex ] );
+ *       crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ *
+ * // Function that creates two co-routines.
+ * void vOtherFunction( void )
+ * {
+ * uint8_t ucParameterToPass;
+ * TaskHandle_t xHandle;
+ *
+ *   // Create two co-routines at priority 0.  The first is given index 0
+ *   // so (from the code above) toggles LED 5 every 200 ticks.  The second
+ *   // is given index 1 so toggles LED 6 every 400 ticks.
+ *   for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+ *   {
+ *       xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+ *   }
+ * }
+ * </pre>
+ * \defgroup xCoRoutineCreate xCoRoutineCreate
+ * \ingroup Tasks
+ */
+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode,
+                             UBaseType_t uxPriority,
+                             UBaseType_t uxIndex );
+
+
+/**
+ * croutine. h
+ * <pre>
+ * void vCoRoutineSchedule( void );
+ * </pre>
+ *
+ * Run a co-routine.
+ *
+ * vCoRoutineSchedule() executes the highest priority co-routine that is able
+ * to run.  The co-routine will execute until it either blocks, yields or is
+ * preempted by a task.  Co-routines execute cooperatively so one
+ * co-routine cannot be preempted by another, but can be preempted by a task.
+ *
+ * If an application comprises of both tasks and co-routines then
+ * vCoRoutineSchedule should be called from the idle task (in an idle task
+ * hook).
+ *
+ * Example usage:
+ * <pre>
+ * // This idle task hook will schedule a co-routine each time it is called.
+ * // The rest of the idle task will execute between co-routine calls.
+ * void vApplicationIdleHook( void )
+ * {
+ *  vCoRoutineSchedule();
+ * }
+ *
+ * // Alternatively, if you do not require any other part of the idle task to
+ * // execute, the idle task hook can call vCoRoutineSchedule() within an
+ * // infinite loop.
+ * void vApplicationIdleHook( void )
+ * {
+ *  for( ;; )
+ *  {
+ *      vCoRoutineSchedule();
+ *  }
+ * }
+ * </pre>
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule
+ * \ingroup Tasks
+ */
+void vCoRoutineSchedule( void );
+
+/**
+ * croutine. h
+ * <pre>
+ * crSTART( CoRoutineHandle_t xHandle );
+ * </pre>
+ *
+ * This macro MUST always be called at the start of a co-routine function.
+ *
+ * Example usage:
+ * <pre>
+ * // Co-routine to be created.
+ * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static int32_t ulAVariable;
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *        // Co-routine functionality goes here.
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ * </pre>
+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crSTART( pxCRCB )                            \
+    switch( ( ( CRCB_t * ) ( pxCRCB ) )->uxState ) { \
+        case 0:
+
+/**
+ * croutine. h
+ * <pre>
+ * crEND();
+ * </pre>
+ *
+ * This macro MUST always be called at the end of a co-routine function.
+ *
+ * Example usage:
+ * <pre>
+ * // Co-routine to be created.
+ * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static int32_t ulAVariable;
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *        // Co-routine functionality goes here.
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ * </pre>
+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crEND()    }
+
+/*
+ * These macros are intended for internal use by the co-routine implementation
+ * only.  The macros should not be used directly by application writers.
+ */
+#define crSET_STATE0( xHandle )                                       \
+    ( ( CRCB_t * ) ( xHandle ) )->uxState = ( __LINE__ * 2 ); return; \
+    case ( __LINE__ * 2 ):
+#define crSET_STATE1( xHandle )                                               \
+    ( ( CRCB_t * ) ( xHandle ) )->uxState = ( ( __LINE__ * 2 ) + 1 ); return; \
+    case ( ( __LINE__ * 2 ) + 1 ):
+
+/**
+ * croutine. h
+ * <pre>
+ * crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );
+ * </pre>
+ *
+ * Delay a co-routine for a fixed period of time.
+ *
+ * crDELAY can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * @param xHandle The handle of the co-routine to delay.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should delay
+ * for.  The actual amount of time this equates to is defined by
+ * configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant portTICK_PERIOD_MS
+ * can be used to convert ticks to milliseconds.
+ *
+ * Example usage:
+ * <pre>
+ * // Co-routine to be created.
+ * void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * // This may not be necessary for const variables.
+ * // We are to delay for 200ms.
+ * static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+ *
+ *   // Must start every co-routine with a call to crSTART();
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *      // Delay for 200ms.
+ *      crDELAY( xHandle, xDelayTime );
+ *
+ *      // Do something here.
+ *   }
+ *
+ *   // Must end every co-routine with a call to crEND();
+ *   crEND();
+ * }
+ * </pre>
+ * \defgroup crDELAY crDELAY
+ * \ingroup Tasks
+ */
+#define crDELAY( xHandle, xTicksToDelay )                      \
+    if( ( xTicksToDelay ) > 0 )                                \
+    {                                                          \
+        vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL ); \
+    }                                                          \
+    crSET_STATE0( ( xHandle ) );
+
+/**
+ * <pre>
+ * crQUEUE_SEND(
+ *                CoRoutineHandle_t xHandle,
+ *                QueueHandle_t pxQueue,
+ *                void *pvItemToQueue,
+ *                TickType_t xTicksToWait,
+ *                BaseType_t *pxResult
+ *           )
+ * </pre>
+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_SEND can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue on which the data will be posted.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvItemToQueue A pointer to the data being posted onto the queue.
+ * The number of bytes of each queued item is specified when the queue is
+ * created.  This number of bytes is copied from pvItemToQueue into the queue
+ * itself.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for space to become available on the queue, should space not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example
+ * below).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully posted onto the queue, otherwise it will be set to an
+ * error defined within ProjDefs.h.
+ *
+ * Example usage:
+ * <pre>
+ * // Co-routine function that blocks for a fixed period then posts a number onto
+ * // a queue.
+ * static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static BaseType_t xNumberToPost = 0;
+ * static BaseType_t xResult;
+ *
+ *  // Co-routines must begin with a call to crSTART().
+ *  crSTART( xHandle );
+ *
+ *  for( ;; )
+ *  {
+ *      // This assumes the queue has already been created.
+ *      crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+ *
+ *      if( xResult != pdPASS )
+ *      {
+ *          // The message was not posted!
+ *      }
+ *
+ *      // Increment the number to be posted onto the queue.
+ *      xNumberToPost++;
+ *
+ *      // Delay for 100 ticks.
+ *      crDELAY( xHandle, 100 );
+ *  }
+ *
+ *  // Co-routines must end with a call to crEND().
+ *  crEND();
+ * }
+ * </pre>
+ * \defgroup crQUEUE_SEND crQUEUE_SEND
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )           \
+    {                                                                                     \
+        *( pxResult ) = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), ( xTicksToWait ) ); \
+        if( *( pxResult ) == errQUEUE_BLOCKED )                                           \
+        {                                                                                 \
+            crSET_STATE0( ( xHandle ) );                                                  \
+            *pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 );                \
+        }                                                                                 \
+        if( *pxResult == errQUEUE_YIELD )                                                 \
+        {                                                                                 \
+            crSET_STATE1( ( xHandle ) );                                                  \
+            *pxResult = pdPASS;                                                           \
+        }                                                                                 \
+    }
+
+/**
+ * croutine. h
+ * <pre>
+ * crQUEUE_RECEIVE(
+ *                   CoRoutineHandle_t xHandle,
+ *                   QueueHandle_t pxQueue,
+ *                   void *pvBuffer,
+ *                   TickType_t xTicksToWait,
+ *                   BaseType_t *pxResult
+ *               )
+ * </pre>
+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_RECEIVE can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue from which the data will be received.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvBuffer The buffer into which the received item is to be copied.
+ * The number of bytes of each queued item is specified when the queue is
+ * created.  This number of bytes is copied into pvBuffer.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for data to become available from the queue, should data not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the
+ * crQUEUE_SEND example).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully retrieved from the queue, otherwise it will be set to
+ * an error code as defined within ProjDefs.h.
+ *
+ * Example usage:
+ * <pre>
+ * // A co-routine receives the number of an LED to flash from a queue.  It
+ * // blocks on the queue until the number is received.
+ * static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ * static BaseType_t xResult;
+ * static UBaseType_t uxLEDToFlash;
+ *
+ *  // All co-routines must start with a call to crSTART().
+ *  crSTART( xHandle );
+ *
+ *  for( ;; )
+ *  {
+ *      // Wait for data to become available on the queue.
+ *      crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+ *
+ *      if( xResult == pdPASS )
+ *      {
+ *          // We received the LED to flash - flash it!
+ *          vParTestToggleLED( uxLEDToFlash );
+ *      }
+ *  }
+ *
+ *  crEND();
+ * }
+ * </pre>
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )           \
+    {                                                                                   \
+        *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), ( xTicksToWait ) ); \
+        if( *( pxResult ) == errQUEUE_BLOCKED )                                         \
+        {                                                                               \
+            crSET_STATE0( ( xHandle ) );                                                \
+            *( pxResult ) = xQueueCRReceive( ( pxQueue ), ( pvBuffer ), 0 );            \
+        }                                                                               \
+        if( *( pxResult ) == errQUEUE_YIELD )                                           \
+        {                                                                               \
+            crSET_STATE1( ( xHandle ) );                                                \
+            *( pxResult ) = pdPASS;                                                     \
+        }                                                                               \
+    }
+
+/**
+ * croutine. h
+ * <pre>
+ * crQUEUE_SEND_FROM_ISR(
+ *                          QueueHandle_t pxQueue,
+ *                          void *pvItemToQueue,
+ *                          BaseType_t xCoRoutinePreviouslyWoken
+ *                     )
+ * </pre>
+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue
+ * that is being used from within a co-routine.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto
+ * the same queue multiple times from a single interrupt.  The first call
+ * should always pass in pdFALSE.  Subsequent calls should pass in
+ * the value returned from the previous call.
+ *
+ * @return pdTRUE if a co-routine was woken by posting onto the queue.  This is
+ * used by the ISR to determine if a context switch may be required following
+ * the ISR.
+ *
+ * Example usage:
+ * <pre>
+ * // A co-routine that blocks on a queue waiting for characters to be received.
+ * static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * char cRxedChar;
+ * BaseType_t xResult;
+ *
+ *   // All co-routines must start with a call to crSTART().
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *       // Wait for data to become available on the queue.  This assumes the
+ *       // queue xCommsRxQueue has already been created!
+ *       crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+ *
+ *       // Was a character received?
+ *       if( xResult == pdPASS )
+ *       {
+ *           // Process the character here.
+ *       }
+ *   }
+ *
+ *   // All co-routines must end with a call to crEND().
+ *   crEND();
+ * }
+ *
+ * // An ISR that uses a queue to send characters received on a serial port to
+ * // a co-routine.
+ * void vUART_ISR( void )
+ * {
+ * char cRxedChar;
+ * BaseType_t xCRWokenByPost = pdFALSE;
+ *
+ *   // We loop around reading characters until there are none left in the UART.
+ *   while( UART_RX_REG_NOT_EMPTY() )
+ *   {
+ *       // Obtain the character from the UART.
+ *       cRxedChar = UART_RX_REG;
+ *
+ *       // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+ *       // the first time around the loop.  If the post causes a co-routine
+ *       // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+ *       // In this manner we can ensure that if more than one co-routine is
+ *       // blocked on the queue only one is woken by this ISR no matter how
+ *       // many characters are posted to the queue.
+ *       xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+ *   }
+ * }
+ * </pre>
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) \
+    xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )
+
+
+/**
+ * croutine. h
+ * <pre>
+ * crQUEUE_SEND_FROM_ISR(
+ *                          QueueHandle_t pxQueue,
+ *                          void *pvBuffer,
+ *                          BaseType_t * pxCoRoutineWoken
+ *                     )
+ * </pre>
+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data
+ * from a queue that is being used from within a co-routine (a co-routine
+ * posted to the queue).
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvBuffer A pointer to a buffer into which the received item will be
+ * placed.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from the queue into
+ * pvBuffer.
+ *
+ * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become
+ * available on the queue.  If crQUEUE_RECEIVE_FROM_ISR causes such a
+ * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise
+ * *pxCoRoutineWoken will remain unchanged.
+ *
+ * @return pdTRUE an item was successfully received from the queue, otherwise
+ * pdFALSE.
+ *
+ * Example usage:
+ * <pre>
+ * // A co-routine that posts a character to a queue then blocks for a fixed
+ * // period.  The character is incremented each time.
+ * static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ * {
+ * // cChar holds its value while this co-routine is blocked and must therefore
+ * // be declared static.
+ * static char cCharToTx = 'a';
+ * BaseType_t xResult;
+ *
+ *   // All co-routines must start with a call to crSTART().
+ *   crSTART( xHandle );
+ *
+ *   for( ;; )
+ *   {
+ *       // Send the next character to the queue.
+ *       crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+ *
+ *       if( xResult == pdPASS )
+ *       {
+ *           // The character was successfully posted to the queue.
+ *       }
+ *       else
+ *       {
+ *          // Could not post the character to the queue.
+ *       }
+ *
+ *       // Enable the UART Tx interrupt to cause an interrupt in this
+ *       // hypothetical UART.  The interrupt will obtain the character
+ *       // from the queue and send it.
+ *       ENABLE_RX_INTERRUPT();
+ *
+ *       // Increment to the next character then block for a fixed period.
+ *       // cCharToTx will maintain its value across the delay as it is
+ *       // declared static.
+ *       cCharToTx++;
+ *       if( cCharToTx > 'x' )
+ *       {
+ *          cCharToTx = 'a';
+ *       }
+ *       crDELAY( 100 );
+ *   }
+ *
+ *   // All co-routines must end with a call to crEND().
+ *   crEND();
+ * }
+ *
+ * // An ISR that uses a queue to receive characters to send on a UART.
+ * void vUART_ISR( void )
+ * {
+ * char cCharToTx;
+ * BaseType_t xCRWokenByPost = pdFALSE;
+ *
+ *   while( UART_TX_REG_EMPTY() )
+ *   {
+ *       // Are there any characters in the queue waiting to be sent?
+ *       // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+ *       // is woken by the post - ensuring that only a single co-routine is
+ *       // woken no matter how many times we go around this loop.
+ *       if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+ *       {
+ *           SEND_CHARACTER( cCharToTx );
+ *       }
+ *   }
+ * }
+ * </pre>
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) \
+    xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )
+
+/*
+ * This function is intended for internal use by the co-routine macros only.
+ * The macro nature of the co-routine implementation requires that the
+ * prototype appears here.  The function should not be used by application
+ * writers.
+ *
+ * Removes the current co-routine from its ready list and places it in the
+ * appropriate delayed list.
+ */
+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay,
+                                 List_t * pxEventList );
+
+/*
+ * This function is intended for internal use by the queue implementation only.
+ * The function should not be used by application writers.
+ *
+ * Removes the highest priority co-routine from the event list and places it in
+ * the pending ready list.
+ */
+BaseType_t xCoRoutineRemoveFromEventList( const List_t * pxEventList );
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* CO_ROUTINE_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/deprecated_definitions.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/deprecated_definitions.h
new file mode 100644
index 0000000..efa8a87
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/deprecated_definitions.h
@@ -0,0 +1,279 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef DEPRECATED_DEFINITIONS_H
+#define DEPRECATED_DEFINITIONS_H
+
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+ * pre-processor definition was used to ensure the pre-processor found the correct
+ * portmacro.h file for the port being used.  That scheme was deprecated in favour
+ * of setting the compiler's include path such that it found the correct
+ * portmacro.h file - removing the need for the constant and allowing the
+ * portmacro.h file to be located anywhere in relation to the port being used.  The
+ * definitions below remain in the code for backward compatibility only.  New
+ * projects should not use them. */
+
+#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT
+    #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h"
+    typedef void ( __interrupt __far * pxISR )();
+#endif
+
+#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT
+    #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h"
+    typedef void ( __interrupt __far * pxISR )();
+#endif
+
+#ifdef GCC_MEGA_AVR
+    #include "../portable/GCC/ATMega323/portmacro.h"
+#endif
+
+#ifdef IAR_MEGA_AVR
+    #include "../portable/IAR/ATMega323/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC24_PORT
+    #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_DSPIC_PORT
+    #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC18F_PORT
+    #include "../../Source/portable/MPLAB/PIC18F/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC32MX_PORT
+    #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h"
+#endif
+
+#ifdef _FEDPICC
+    #include "libFreeRTOS/Include/portmacro.h"
+#endif
+
+#ifdef SDCC_CYGNAL
+    #include "../../Source/portable/SDCC/Cygnal/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7
+    #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7_ECLIPSE
+    #include "portmacro.h"
+#endif
+
+#ifdef ROWLEY_LPC23xx
+    #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h"
+#endif
+
+#ifdef IAR_MSP430
+    #include "..\..\Source\portable\IAR\MSP430\portmacro.h"
+#endif
+
+#ifdef GCC_MSP430
+    #include "../../Source/portable/GCC/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ROWLEY_MSP430
+    #include "../../Source/portable/Rowley/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ARM7_LPC21xx_KEIL_RVDS
+    #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h"
+#endif
+
+#ifdef SAM7_GCC
+    #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"
+#endif
+
+#ifdef SAM7_IAR
+    #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"
+#endif
+
+#ifdef SAM9XE_IAR
+    #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h"
+#endif
+
+#ifdef LPC2000_IAR
+    #include "..\..\Source\portable\IAR\LPC2000\portmacro.h"
+#endif
+
+#ifdef STR71X_IAR
+    #include "..\..\Source\portable\IAR\STR71x\portmacro.h"
+#endif
+
+#ifdef STR75X_IAR
+    #include "..\..\Source\portable\IAR\STR75x\portmacro.h"
+#endif
+
+#ifdef STR75X_GCC
+    #include "..\..\Source\portable\GCC\STR75x\portmacro.h"
+#endif
+
+#ifdef STR91X_IAR
+    #include "..\..\Source\portable\IAR\STR91x\portmacro.h"
+#endif
+
+#ifdef GCC_H8S
+    #include "../../Source/portable/GCC/H8S2329/portmacro.h"
+#endif
+
+#ifdef GCC_AT91FR40008
+    #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"
+#endif
+
+#ifdef RVDS_ARMCM3_LM3S102
+    #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3_LM3S102
+    #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3
+    #include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef IAR_ARM_CM3
+    #include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef IAR_ARMCM3_LM
+    #include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef HCS12_CODE_WARRIOR
+    #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"
+#endif
+
+#ifdef MICROBLAZE_GCC
+    #include "../../Source/portable/GCC/MicroBlaze/portmacro.h"
+#endif
+
+#ifdef TERN_EE
+    #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h"
+#endif
+
+#ifdef GCC_HCS12
+    #include "../../Source/portable/GCC/HCS12/portmacro.h"
+#endif
+
+#ifdef GCC_MCF5235
+    #include "../../Source/portable/GCC/MCF5235/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_GCC
+    #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_CODEWARRIOR
+    #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef GCC_PPC405
+    #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h"
+#endif
+
+#ifdef GCC_PPC440
+    #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h"
+#endif
+
+#ifdef _16FX_SOFTUNE
+    #include "..\..\Source\portable\Softune\MB96340\portmacro.h"
+#endif
+
+#ifdef BCC_INDUSTRIAL_PC_PORT
+
+/* A short file name has to be used in place of the normal
+ * FreeRTOSConfig.h when using the Borland compiler. */
+    #include "frconfig.h"
+    #include "..\portable\BCC\16BitDOS\PC\prtmacro.h"
+    typedef void ( __interrupt __far * pxISR )();
+#endif
+
+#ifdef BCC_FLASH_LITE_186_PORT
+
+/* A short file name has to be used in place of the normal
+ * FreeRTOSConfig.h when using the Borland compiler. */
+    #include "frconfig.h"
+    #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"
+    typedef void ( __interrupt __far * pxISR )();
+#endif
+
+#ifdef __GNUC__
+    #ifdef __AVR32_AVR32A__
+        #include "portmacro.h"
+    #endif
+#endif
+
+#ifdef __ICCAVR32__
+    #ifdef __CORE__
+        #if __CORE__ == __AVR32A__
+            #include "portmacro.h"
+        #endif
+    #endif
+#endif
+
+#ifdef __91467D
+    #include "portmacro.h"
+#endif
+
+#ifdef __96340
+    #include "portmacro.h"
+#endif
+
+
+#ifdef __IAR_V850ES_Fx3__
+    #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3__
+    #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3_L__
+    #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx2__
+    #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Hx2__
+    #include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3__
+    #include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3L__
+    #include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+#endif /* DEPRECATED_DEFINITIONS_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/event_groups.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/event_groups.h
new file mode 100644
index 0000000..70ba8d1
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/event_groups.h
@@ -0,0 +1,775 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef EVENT_GROUPS_H
+#define EVENT_GROUPS_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h" must appear in source files before "include event_groups.h"
+#endif
+
+/* FreeRTOS includes. */
+#include "timers.h"
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/**
+ * An event group is a collection of bits to which an application can assign a
+ * meaning.  For example, an application may create an event group to convey
+ * the status of various CAN bus related events in which bit 0 might mean "A CAN
+ * message has been received and is ready for processing", bit 1 might mean "The
+ * application has queued a message that is ready for sending onto the CAN
+ * network", and bit 2 might mean "It is time to send a SYNC message onto the
+ * CAN network" etc.  A task can then test the bit values to see which events
+ * are active, and optionally enter the Blocked state to wait for a specified
+ * bit or a group of specified bits to be active.  To continue the CAN bus
+ * example, a CAN controlling task can enter the Blocked state (and therefore
+ * not consume any processing time) until either bit 0, bit 1 or bit 2 are
+ * active, at which time the bit that was actually active would inform the task
+ * which action it had to take (process a received message, send a message, or
+ * send a SYNC).
+ *
+ * The event groups implementation contains intelligence to avoid race
+ * conditions that would otherwise occur were an application to use a simple
+ * variable for the same purpose.  This is particularly important with respect
+ * to when a bit within an event group is to be cleared, and when bits have to
+ * be set and then tested atomically - as is the case where event groups are
+ * used to create a synchronisation point between multiple tasks (a
+ * 'rendezvous').
+ *
+ * \defgroup EventGroup
+ */
+
+
+
+/**
+ * event_groups.h
+ *
+ * Type by which event groups are referenced.  For example, a call to
+ * xEventGroupCreate() returns an EventGroupHandle_t variable that can then
+ * be used as a parameter to other event group functions.
+ *
+ * \defgroup EventGroupHandle_t EventGroupHandle_t
+ * \ingroup EventGroup
+ */
+struct EventGroupDef_t;
+typedef struct EventGroupDef_t   * EventGroupHandle_t;
+
+/*
+ * The type that holds event bits always matches TickType_t - therefore the
+ * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1,
+ * 32 bits if set to 0.
+ *
+ * \defgroup EventBits_t EventBits_t
+ * \ingroup EventGroup
+ */
+typedef TickType_t               EventBits_t;
+
+/**
+ * event_groups.h
+ * <pre>
+ * EventGroupHandle_t xEventGroupCreate( void );
+ * </pre>
+ *
+ * Create a new event group.
+ *
+ * Internally, within the FreeRTOS implementation, event groups use a [small]
+ * block of memory, in which the event group's structure is stored.  If an event
+ * groups is created using xEventGropuCreate() then the required memory is
+ * automatically dynamically allocated inside the xEventGroupCreate() function.
+ * (see https://www.FreeRTOS.org/a00111.html).  If an event group is created
+ * using xEventGropuCreateStatic() then the application writer must instead
+ * provide the memory that will get used by the event group.
+ * xEventGroupCreateStatic() therefore allows an event group to be created
+ * without using any dynamic memory allocation.
+ *
+ * Although event groups are not related to ticks, for internal implementation
+ * reasons the number of bits available for use in an event group is dependent
+ * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If
+ * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
+ * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has
+ * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store
+ * event bits within an event group.
+ *
+ * @return If the event group was created then a handle to the event group is
+ * returned.  If there was insufficient FreeRTOS heap available to create the
+ * event group then NULL is returned.  See https://www.FreeRTOS.org/a00111.html
+ *
+ * Example usage:
+ * <pre>
+ *  // Declare a variable to hold the created event group.
+ *  EventGroupHandle_t xCreatedEventGroup;
+ *
+ *  // Attempt to create the event group.
+ *  xCreatedEventGroup = xEventGroupCreate();
+ *
+ *  // Was the event group created successfully?
+ *  if( xCreatedEventGroup == NULL )
+ *  {
+ *      // The event group was not created because there was insufficient
+ *      // FreeRTOS heap available.
+ *  }
+ *  else
+ *  {
+ *      // The event group was created.
+ *  }
+ * </pre>
+ * \defgroup xEventGroupCreate xEventGroupCreate
+ * \ingroup EventGroup
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * event_groups.h
+ * <pre>
+ * EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
+ * </pre>
+ *
+ * Create a new event group.
+ *
+ * Internally, within the FreeRTOS implementation, event groups use a [small]
+ * block of memory, in which the event group's structure is stored.  If an event
+ * groups is created using xEventGropuCreate() then the required memory is
+ * automatically dynamically allocated inside the xEventGroupCreate() function.
+ * (see https://www.FreeRTOS.org/a00111.html).  If an event group is created
+ * using xEventGropuCreateStatic() then the application writer must instead
+ * provide the memory that will get used by the event group.
+ * xEventGroupCreateStatic() therefore allows an event group to be created
+ * without using any dynamic memory allocation.
+ *
+ * Although event groups are not related to ticks, for internal implementation
+ * reasons the number of bits available for use in an event group is dependent
+ * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If
+ * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
+ * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has
+ * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store
+ * event bits within an event group.
+ *
+ * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type
+ * StaticEventGroup_t, which will be then be used to hold the event group's data
+ * structures, removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the event group was created then a handle to the event group is
+ * returned.  If pxEventGroupBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * <pre>
+ *  // StaticEventGroup_t is a publicly accessible structure that has the same
+ *  // size and alignment requirements as the real event group structure.  It is
+ *  // provided as a mechanism for applications to know the size of the event
+ *  // group (which is dependent on the architecture and configuration file
+ *  // settings) without breaking the strict data hiding policy by exposing the
+ *  // real event group internals.  This StaticEventGroup_t variable is passed
+ *  // into the xSemaphoreCreateEventGroupStatic() function and is used to store
+ *  // the event group's data structures
+ *  StaticEventGroup_t xEventGroupBuffer;
+ *
+ *  // Create the event group without dynamically allocating any memory.
+ *  xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+ * </pre>
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * event_groups.h
+ * <pre>
+ *  EventBits_t xEventGroupWaitBits(    EventGroupHandle_t xEventGroup,
+ *                                      const EventBits_t uxBitsToWaitFor,
+ *                                      const BaseType_t xClearOnExit,
+ *                                      const BaseType_t xWaitForAllBits,
+ *                                      const TickType_t xTicksToWait );
+ * </pre>
+ *
+ * [Potentially] block to wait for one or more bits to be set within a
+ * previously created event group.
+ *
+ * This function cannot be called from an interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are being tested.  The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group.  For example, to wait for bit 0 and/or bit 2 set
+ * uxBitsToWaitFor to 0x05.  To wait for bits 0 and/or bit 1 and/or bit 2 set
+ * uxBitsToWaitFor to 0x07.  Etc.
+ *
+ * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within
+ * uxBitsToWaitFor that are set within the event group will be cleared before
+ * xEventGroupWaitBits() returns if the wait condition was met (if the function
+ * returns for a reason other than a timeout).  If xClearOnExit is set to
+ * pdFALSE then the bits set in the event group are not altered when the call to
+ * xEventGroupWaitBits() returns.
+ *
+ * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then
+ * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor
+ * are set or the specified block time expires.  If xWaitForAllBits is set to
+ * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set
+ * in uxBitsToWaitFor is set or the specified block time expires.  The block
+ * time is specified by the xTicksToWait parameter.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for one/all (depending on the xWaitForAllBits value) of the bits specified by
+ * uxBitsToWaitFor to become set.
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired.  Test the return value to know
+ * which bits were set.  If xEventGroupWaitBits() returned because its timeout
+ * expired then not all the bits being waited for will be set.  If
+ * xEventGroupWaitBits() returned because the bits it was waiting for were set
+ * then the returned value is the event group value before any bits were
+ * automatically cleared in the case that xClearOnExit parameter was set to
+ * pdTRUE.
+ *
+ * Example usage:
+ * <pre>
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+ *
+ * void aFunction( EventGroupHandle_t xEventGroup )
+ * {
+ * EventBits_t uxBits;
+ * const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+ *
+ *      // Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+ *      // the event group.  Clear the bits before exiting.
+ *      uxBits = xEventGroupWaitBits(
+ *                  xEventGroup,    // The event group being tested.
+ *                  BIT_0 | BIT_4,  // The bits within the event group to wait for.
+ *                  pdTRUE,         // BIT_0 and BIT_4 should be cleared before returning.
+ *                  pdFALSE,        // Don't wait for both bits, either bit will do.
+ *                  xTicksToWait ); // Wait a maximum of 100ms for either bit to be set.
+ *
+ *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ *      {
+ *          // xEventGroupWaitBits() returned because both bits were set.
+ *      }
+ *      else if( ( uxBits & BIT_0 ) != 0 )
+ *      {
+ *          // xEventGroupWaitBits() returned because just BIT_0 was set.
+ *      }
+ *      else if( ( uxBits & BIT_4 ) != 0 )
+ *      {
+ *          // xEventGroupWaitBits() returned because just BIT_4 was set.
+ *      }
+ *      else
+ *      {
+ *          // xEventGroupWaitBits() returned because xTicksToWait ticks passed
+ *          // without either BIT_0 or BIT_4 becoming set.
+ *      }
+ * }
+ * </pre>
+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                 const EventBits_t uxBitsToWaitFor,
+                                 const BaseType_t xClearOnExit,
+                                 const BaseType_t xWaitForAllBits,
+                                 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ * <pre>
+ *  EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+ * </pre>
+ *
+ * Clear bits within an event group.  This function cannot be called from an
+ * interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear
+ * in the event group.  For example, to clear bit 3 only, set uxBitsToClear to
+ * 0x08.  To clear bit 3 and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return The value of the event group before the specified bits were cleared.
+ *
+ * Example usage:
+ * <pre>
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+ *
+ * void aFunction( EventGroupHandle_t xEventGroup )
+ * {
+ * EventBits_t uxBits;
+ *
+ *      // Clear bit 0 and bit 4 in xEventGroup.
+ *      uxBits = xEventGroupClearBits(
+ *                              xEventGroup,    // The event group being updated.
+ *                              BIT_0 | BIT_4 );// The bits being cleared.
+ *
+ *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ *      {
+ *          // Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+ *          // called.  Both will now be clear (not set).
+ *      }
+ *      else if( ( uxBits & BIT_0 ) != 0 )
+ *      {
+ *          // Bit 0 was set before xEventGroupClearBits() was called.  It will
+ *          // now be clear.
+ *      }
+ *      else if( ( uxBits & BIT_4 ) != 0 )
+ *      {
+ *          // Bit 4 was set before xEventGroupClearBits() was called.  It will
+ *          // now be clear.
+ *      }
+ *      else
+ *      {
+ *          // Neither bit 0 nor bit 4 were set in the first place.
+ *      }
+ * }
+ * </pre>
+ * \defgroup xEventGroupClearBits xEventGroupClearBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                  const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ * <pre>
+ *  BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ * </pre>
+ *
+ * A version of xEventGroupClearBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set.  FreeRTOS does not allow nondeterministic operations to be performed
+ * while interrupts are disabled, so protects event groups that are accessed
+ * from tasks by suspending the scheduler rather than disabling interrupts.  As
+ * a result event groups cannot be accessed directly from an interrupt service
+ * routine.  Therefore xEventGroupClearBitsFromISR() sends a message to the
+ * timer task to have the clear operation performed in the context of the timer
+ * task.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.
+ * For example, to clear bit 3 only, set uxBitsToClear to 0x08.  To clear bit 3
+ * and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+ * <pre>
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+ *
+ * // An event group which it is assumed has already been created by a call to
+ * // xEventGroupCreate().
+ * EventGroupHandle_t xEventGroup;
+ *
+ * void anInterruptHandler( void )
+ * {
+ *      // Clear bit 0 and bit 4 in xEventGroup.
+ *      xResult = xEventGroupClearBitsFromISR(
+ *                          xEventGroup,     // The event group being updated.
+ *                          BIT_0 | BIT_4 ); // The bits being set.
+ *
+ *      if( xResult == pdPASS )
+ *      {
+ *          // The message was posted successfully.
+ *      }
+ * }
+ * </pre>
+ * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR
+ * \ingroup EventGroup
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup,
+                                            const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+#else
+    #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) \
+    xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL )
+#endif
+
+/**
+ * event_groups.h
+ * <pre>
+ *  EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ * </pre>
+ *
+ * Set bits within an event group.
+ * This function cannot be called from an interrupt.  xEventGroupSetBitsFromISR()
+ * is a version that can be called from an interrupt.
+ *
+ * Setting bits in an event group will automatically unblock tasks that are
+ * blocked waiting for the bits.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @return The value of the event group at the time the call to
+ * xEventGroupSetBits() returns.  There are two reasons why the returned value
+ * might have the bits specified by the uxBitsToSet parameter cleared.  First,
+ * if setting a bit results in a task that was waiting for the bit leaving the
+ * blocked state then it is possible the bit will be cleared automatically
+ * (see the xClearBitOnExit parameter of xEventGroupWaitBits()).  Second, any
+ * unblocked (or otherwise Ready state) task that has a priority above that of
+ * the task that called xEventGroupSetBits() will execute and may change the
+ * event group value before the call to xEventGroupSetBits() returns.
+ *
+ * Example usage:
+ * <pre>
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+ *
+ * void aFunction( EventGroupHandle_t xEventGroup )
+ * {
+ * EventBits_t uxBits;
+ *
+ *      // Set bit 0 and bit 4 in xEventGroup.
+ *      uxBits = xEventGroupSetBits(
+ *                          xEventGroup,    // The event group being updated.
+ *                          BIT_0 | BIT_4 );// The bits being set.
+ *
+ *      if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+ *      {
+ *          // Both bit 0 and bit 4 remained set when the function returned.
+ *      }
+ *      else if( ( uxBits & BIT_0 ) != 0 )
+ *      {
+ *          // Bit 0 remained set when the function returned, but bit 4 was
+ *          // cleared.  It might be that bit 4 was cleared automatically as a
+ *          // task that was waiting for bit 4 was removed from the Blocked
+ *          // state.
+ *      }
+ *      else if( ( uxBits & BIT_4 ) != 0 )
+ *      {
+ *          // Bit 4 remained set when the function returned, but bit 0 was
+ *          // cleared.  It might be that bit 0 was cleared automatically as a
+ *          // task that was waiting for bit 0 was removed from the Blocked
+ *          // state.
+ *      }
+ *      else
+ *      {
+ *          // Neither bit 0 nor bit 4 remained set.  It might be that a task
+ *          // was waiting for both of the bits to be set, and the bits were
+ *          // cleared as the task left the Blocked state.
+ *      }
+ * }
+ * </pre>
+ * \defgroup xEventGroupSetBits xEventGroupSetBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ * <pre>
+ *  BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+ * </pre>
+ *
+ * A version of xEventGroupSetBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set.  FreeRTOS does not allow nondeterministic operations to be performed in
+ * interrupts or from critical sections.  Therefore xEventGroupSetBitsFromISR()
+ * sends a message to the timer task to have the set operation performed in the
+ * context of the timer task - where a scheduler lock is used in place of a
+ * critical section.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task is higher than the priority of the
+ * currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE by
+ * xEventGroupSetBitsFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+ * <pre>
+ #define BIT_0 ( 1 << 0 )
+ #define BIT_4 ( 1 << 4 )
+ *
+ * // An event group which it is assumed has already been created by a call to
+ * // xEventGroupCreate().
+ * EventGroupHandle_t xEventGroup;
+ *
+ * void anInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken, xResult;
+ *
+ *      // xHigherPriorityTaskWoken must be initialised to pdFALSE.
+ *      xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *      // Set bit 0 and bit 4 in xEventGroup.
+ *      xResult = xEventGroupSetBitsFromISR(
+ *                          xEventGroup,    // The event group being updated.
+ *                          BIT_0 | BIT_4   // The bits being set.
+ *                          &xHigherPriorityTaskWoken );
+ *
+ *      // Was the message posted successfully?
+ *      if( xResult == pdPASS )
+ *      {
+ *          // If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *          // switch should be requested.  The macro used is port specific and
+ *          // will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+ *          // refer to the documentation page for the port being used.
+ *          portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *      }
+ * }
+ * </pre>
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR
+ * \ingroup EventGroup
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+    BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup,
+                                          const EventBits_t uxBitsToSet,
+                                          BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#else
+    #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) \
+    xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken )
+#endif
+
+/**
+ * event_groups.h
+ * <pre>
+ *  EventBits_t xEventGroupSync(    EventGroupHandle_t xEventGroup,
+ *                                  const EventBits_t uxBitsToSet,
+ *                                  const EventBits_t uxBitsToWaitFor,
+ *                                  TickType_t xTicksToWait );
+ * </pre>
+ *
+ * Atomically set bits within an event group, then wait for a combination of
+ * bits to be set within the same event group.  This functionality is typically
+ * used to synchronise multiple tasks, where each task has to wait for the other
+ * tasks to reach a synchronisation point before proceeding.
+ *
+ * This function cannot be used from an interrupt.
+ *
+ * The function will return before its block time expires if the bits specified
+ * by the uxBitsToWait parameter are set, or become set within that time.  In
+ * this case all the bits specified by uxBitsToWait will be automatically
+ * cleared before the function returns.
+ *
+ * @param xEventGroup The event group in which the bits are being tested.  The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToSet The bits to set in the event group before determining
+ * if, and possibly waiting for, all the bits specified by the uxBitsToWait
+ * parameter are set.
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group.  For example, to wait for bit 0 and bit 2 set
+ * uxBitsToWaitFor to 0x05.  To wait for bits 0 and bit 1 and bit 2 set
+ * uxBitsToWaitFor to 0x07.  Etc.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for all of the bits specified by uxBitsToWaitFor to become set.
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired.  Test the return value to know
+ * which bits were set.  If xEventGroupSync() returned because its timeout
+ * expired then not all the bits being waited for will be set.  If
+ * xEventGroupSync() returned because all the bits it was waiting for were
+ * set then the returned value is the event group value before any bits were
+ * automatically cleared.
+ *
+ * Example usage:
+ * <pre>
+ * // Bits used by the three tasks.
+ #define TASK_0_BIT     ( 1 << 0 )
+ #define TASK_1_BIT     ( 1 << 1 )
+ #define TASK_2_BIT     ( 1 << 2 )
+ *
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+ *
+ * // Use an event group to synchronise three tasks.  It is assumed this event
+ * // group has already been created elsewhere.
+ * EventGroupHandle_t xEventBits;
+ *
+ * void vTask0( void *pvParameters )
+ * {
+ * EventBits_t uxReturn;
+ * TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+ *
+ *   for( ;; )
+ *   {
+ *      // Perform task functionality here.
+ *
+ *      // Set bit 0 in the event flag to note this task has reached the
+ *      // sync point.  The other two tasks will set the other two bits defined
+ *      // by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
+ *      // point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
+ *      // for this to happen.
+ *      uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+ *
+ *      if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+ *      {
+ *          // All three tasks reached the synchronisation point before the call
+ *          // to xEventGroupSync() timed out.
+ *      }
+ *  }
+ * }
+ *
+ * void vTask1( void *pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *      // Perform task functionality here.
+ *
+ *      // Set bit 1 in the event flag to note this task has reached the
+ *      // synchronisation point.  The other two tasks will set the other two
+ *      // bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+ *      // synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+ *      // indefinitely for this to happen.
+ *      xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+ *
+ *      // xEventGroupSync() was called with an indefinite block time, so
+ *      // this task will only reach here if the synchronisation was made by all
+ *      // three tasks, so there is no need to test the return value.
+ *   }
+ * }
+ *
+ * void vTask2( void *pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *      // Perform task functionality here.
+ *
+ *      // Set bit 2 in the event flag to note this task has reached the
+ *      // synchronisation point.  The other two tasks will set the other two
+ *      // bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+ *      // synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+ *      // indefinitely for this to happen.
+ *      xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+ *
+ *      // xEventGroupSync() was called with an indefinite block time, so
+ *      // this task will only reach here if the synchronisation was made by all
+ *      // three tasks, so there is no need to test the return value.
+ *  }
+ * }
+ *
+ * </pre>
+ * \defgroup xEventGroupSync xEventGroupSync
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup,
+                             const EventBits_t uxBitsToSet,
+                             const EventBits_t uxBitsToWaitFor,
+                             TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+
+/**
+ * event_groups.h
+ * <pre>
+ *  EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+ * </pre>
+ *
+ * Returns the current value of the bits in an event group.  This function
+ * cannot be used from an interrupt.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBits() was called.
+ *
+ * \defgroup xEventGroupGetBits xEventGroupGetBits
+ * \ingroup EventGroup
+ */
+#define xEventGroupGetBits( xEventGroup )    xEventGroupClearBits( xEventGroup, 0 )
+
+/**
+ * event_groups.h
+ * <pre>
+ *  EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+ * </pre>
+ *
+ * A version of xEventGroupGetBits() that can be called from an ISR.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.
+ *
+ * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ * <pre>
+ *  void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+ * </pre>
+ *
+ * Delete an event group that was previously created by a call to
+ * xEventGroupCreate().  Tasks that are blocked on the event group will be
+ * unblocked and obtain 0 as the event group's value.
+ *
+ * @param xEventGroup The event group being deleted.
+ */
+void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+/* For internal use only. */
+void vEventGroupSetBitsCallback( void * pvEventGroup,
+                                 const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
+void vEventGroupClearBitsCallback( void * pvEventGroup,
+                                   const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+    UBaseType_t uxEventGroupGetNumber( void * xEventGroup ) PRIVILEGED_FUNCTION;
+    void vEventGroupSetNumber( void * xEventGroup,
+                               UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION;
+#endif
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* EVENT_GROUPS_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/list.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/list.h
new file mode 100644
index 0000000..d8a4988
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/list.h
@@ -0,0 +1,417 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * This is the list implementation used by the scheduler.  While it is tailored
+ * heavily for the schedulers needs, it is also available for use by
+ * application code.
+ *
+ * list_ts can only store pointers to list_item_ts.  Each ListItem_t contains a
+ * numeric value (xItemValue).  Most of the time the lists are sorted in
+ * descending item value order.
+ *
+ * Lists are created already containing one list item.  The value of this
+ * item is the maximum possible that can be stored, it is therefore always at
+ * the end of the list and acts as a marker.  The list member pxHead always
+ * points to this marker - even though it is at the tail of the list.  This
+ * is because the tail contains a wrap back pointer to the true head of
+ * the list.
+ *
+ * In addition to it's value, each list item contains a pointer to the next
+ * item in the list (pxNext), a pointer to the list it is in (pxContainer)
+ * and a pointer to back to the object that contains it.  These later two
+ * pointers are included for efficiency of list manipulation.  There is
+ * effectively a two way link between the object containing the list item and
+ * the list item itself.
+ *
+ *
+ * \page ListIntroduction List Implementation
+ * \ingroup FreeRTOSIntro
+ */
+
+
+#ifndef LIST_H
+#define LIST_H
+
+#ifndef INC_FREERTOS_H
+    #error "FreeRTOS.h must be included before list.h"
+#endif
+
+/*
+ * The list structure members are modified from within interrupts, and therefore
+ * by rights should be declared volatile.  However, they are only modified in a
+ * functionally atomic way (within critical sections of with the scheduler
+ * suspended) and are either passed by reference into a function or indexed via
+ * a volatile variable.  Therefore, in all use cases tested so far, the volatile
+ * qualifier can be omitted in order to provide a moderate performance
+ * improvement without adversely affecting functional behaviour.  The assembly
+ * instructions generated by the IAR, ARM and GCC compilers when the respective
+ * compiler's options were set for maximum optimisation has been inspected and
+ * deemed to be as intended.  That said, as compiler technology advances, and
+ * especially if aggressive cross module optimisation is used (a use case that
+ * has not been exercised to any great extend) then it is feasible that the
+ * volatile qualifier will be needed for correct optimisation.  It is expected
+ * that a compiler removing essential code because, without the volatile
+ * qualifier on the list structure members and with aggressive cross module
+ * optimisation, the compiler deemed the code unnecessary will result in
+ * complete and obvious failure of the scheduler.  If this is ever experienced
+ * then the volatile qualifier can be inserted in the relevant places within the
+ * list structures by simply defining configLIST_VOLATILE to volatile in
+ * FreeRTOSConfig.h (as per the example at the bottom of this comment block).
+ * If configLIST_VOLATILE is not defined then the preprocessor directives below
+ * will simply #define configLIST_VOLATILE away completely.
+ *
+ * To use volatile list structure members then add the following line to
+ * FreeRTOSConfig.h (without the quotes):
+ * "#define configLIST_VOLATILE volatile"
+ */
+#ifndef configLIST_VOLATILE
+    #define configLIST_VOLATILE
+#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/* Macros that can be used to place known values within the list structures,
+ * then check that the known values do not get corrupted during the execution of
+ * the application.   These may catch the list data structures being overwritten in
+ * memory.  They will not catch data errors caused by incorrect configuration or
+ * use of FreeRTOS.*/
+#if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )
+    /* Define the macros to do nothing. */
+    #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE
+    #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE
+    #define listFIRST_LIST_INTEGRITY_CHECK_VALUE
+    #define listSECOND_LIST_INTEGRITY_CHECK_VALUE
+    #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+    #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+    #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )
+    #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )
+    #define listTEST_LIST_ITEM_INTEGRITY( pxItem )
+    #define listTEST_LIST_INTEGRITY( pxList )
+#else /* if ( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) */
+    /* Define macros that add new members into the list structures. */
+    #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE     TickType_t xListItemIntegrityValue1;
+    #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE    TickType_t xListItemIntegrityValue2;
+    #define listFIRST_LIST_INTEGRITY_CHECK_VALUE          TickType_t xListIntegrityValue1;
+    #define listSECOND_LIST_INTEGRITY_CHECK_VALUE         TickType_t xListIntegrityValue2;
+
+/* Define macros that set the new structure members to known values. */
+    #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )     ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+    #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )    ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+    #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )              ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+    #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )              ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+
+/* Define macros that will assert if one of the structure members does not
+ * contain its expected value. */
+    #define listTEST_LIST_ITEM_INTEGRITY( pxItem )                      configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+    #define listTEST_LIST_INTEGRITY( pxList )                           configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */
+
+
+/*
+ * Definition of the only type of object that a list can contain.
+ */
+struct xLIST;
+struct xLIST_ITEM
+{
+    listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE               /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+    configLIST_VOLATILE TickType_t xItemValue;              /*< The value being listed.  In most cases this is used to sort the list in descending order. */
+    struct xLIST_ITEM * configLIST_VOLATILE pxNext;         /*< Pointer to the next ListItem_t in the list. */
+    struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;     /*< Pointer to the previous ListItem_t in the list. */
+    void * pvOwner;                                         /*< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */
+    struct xLIST * configLIST_VOLATILE pxContainer;         /*< Pointer to the list in which this list item is placed (if any). */
+    listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE              /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+};
+typedef struct xLIST_ITEM ListItem_t;                       /* For some reason lint wants this as two separate definitions. */
+
+struct xMINI_LIST_ITEM
+{
+    listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE     /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+    configLIST_VOLATILE TickType_t xItemValue;
+    struct xLIST_ITEM * configLIST_VOLATILE pxNext;
+    struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
+};
+typedef struct xMINI_LIST_ITEM MiniListItem_t;
+
+/*
+ * Definition of the type of queue used by the scheduler.
+ */
+typedef struct xLIST
+{
+    listFIRST_LIST_INTEGRITY_CHECK_VALUE          /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+    volatile UBaseType_t uxNumberOfItems;
+    ListItem_t * configLIST_VOLATILE pxIndex;     /*< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
+    MiniListItem_t xListEnd;                      /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
+    listSECOND_LIST_INTEGRITY_CHECK_VALUE         /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+} List_t;
+
+/*
+ * Access macro to set the owner of a list item.  The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )    ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )
+
+/*
+ * Access macro to get the owner of a list item.  The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listGET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_OWNER( pxListItem )             ( ( pxListItem )->pvOwner )
+
+/*
+ * Access macro to set the value of the list item.  In most cases the value is
+ * used to sort the list in descending order.
+ *
+ * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )     ( ( pxListItem )->xItemValue = ( xValue ) )
+
+/*
+ * Access macro to retrieve the value of the list item.  The value can
+ * represent anything - for example the priority of a task, or the time at
+ * which a task should be unblocked.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_VALUE( pxListItem )             ( ( pxListItem )->xItemValue )
+
+/*
+ * Access macro to retrieve the value of the list item at the head of a given
+ * list.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList )        ( ( ( pxList )->xListEnd ).pxNext->xItemValue )
+
+/*
+ * Return the list item at the head of the list.
+ *
+ * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_HEAD_ENTRY( pxList )                      ( ( ( pxList )->xListEnd ).pxNext )
+
+/*
+ * Return the next list item.
+ *
+ * \page listGET_NEXT listGET_NEXT
+ * \ingroup LinkedList
+ */
+#define listGET_NEXT( pxListItem )                        ( ( pxListItem )->pxNext )
+
+/*
+ * Return the list item that marks the end of the list
+ *
+ * \page listGET_END_MARKER listGET_END_MARKER
+ * \ingroup LinkedList
+ */
+#define listGET_END_MARKER( pxList )                      ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )
+
+/*
+ * Access macro to determine if a list contains any items.  The macro will
+ * only have the value true if the list is empty.
+ *
+ * \page listLIST_IS_EMPTY listLIST_IS_EMPTY
+ * \ingroup LinkedList
+ */
+#define listLIST_IS_EMPTY( pxList )                       ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE )
+
+/*
+ * Access macro to return the number of items in the list.
+ */
+#define listCURRENT_LIST_LENGTH( pxList )                 ( ( pxList )->uxNumberOfItems )
+
+/*
+ * Access function to obtain the owner of the next entry in a list.
+ *
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list
+ * and returns that entry's pxOwner parameter.  Using multiple calls to this
+ * function it is therefore possible to move through every item contained in
+ * a list.
+ *
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item.  In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxTCB pxTCB is set to the address of the owner of the next list item.
+ * @param pxList The list from which the next item owner is to be returned.
+ *
+ * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )                                           \
+    {                                                                                          \
+        List_t * const pxConstList = ( pxList );                                               \
+        /* Increment the index to the next item and return the item, ensuring */               \
+        /* we don't return the marker used at the end of the list.  */                         \
+        ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;                           \
+        if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \
+        {                                                                                      \
+            ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;                       \
+        }                                                                                      \
+        ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;                                         \
+    }
+
+
+/*
+ * Access function to obtain the owner of the first entry in a list.  Lists
+ * are normally sorted in ascending item value order.
+ *
+ * This function returns the pxOwner member of the first item in the list.
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item.  In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxList The list from which the owner of the head item is to be
+ * returned.
+ *
+ * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_HEAD_ENTRY( pxList )            ( ( &( ( pxList )->xListEnd ) )->pxNext->pvOwner )
+
+/*
+ * Check to see if a list item is within a list.  The list item maintains a
+ * "container" pointer that points to the list it is in.  All this macro does
+ * is check to see if the container and the list match.
+ *
+ * @param pxList The list we want to know if the list item is within.
+ * @param pxListItem The list item we want to know if is in the list.
+ * @return pdTRUE if the list item is in the list, otherwise pdFALSE.
+ */
+#define listIS_CONTAINED_WITHIN( pxList, pxListItem )    ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) )
+
+/*
+ * Return the list a list item is contained within (referenced from).
+ *
+ * @param pxListItem The list item being queried.
+ * @return A pointer to the List_t object that references the pxListItem
+ */
+#define listLIST_ITEM_CONTAINER( pxListItem )            ( ( pxListItem )->pxContainer )
+
+/*
+ * This provides a crude means of knowing if a list has been initialised, as
+ * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()
+ * function.
+ */
+#define listLIST_IS_INITIALISED( pxList )                ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )
+
+/*
+ * Must be called before a list is used!  This initialises all the members
+ * of the list structure and inserts the xListEnd item into the list as a
+ * marker to the back of the list.
+ *
+ * @param pxList Pointer to the list being initialised.
+ *
+ * \page vListInitialise vListInitialise
+ * \ingroup LinkedList
+ */
+void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION;
+
+/*
+ * Must be called before a list item is used.  This sets the list container to
+ * null so the item does not think that it is already contained in a list.
+ *
+ * @param pxItem Pointer to the list item being initialised.
+ *
+ * \page vListInitialiseItem vListInitialiseItem
+ * \ingroup LinkedList
+ */
+void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert a list item into a list.  The item will be inserted into the list in
+ * a position determined by its item value (descending item value order).
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The item that is to be placed in the list.
+ *
+ * \page vListInsert vListInsert
+ * \ingroup LinkedList
+ */
+void vListInsert( List_t * const pxList,
+                  ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert a list item into a list.  The item will be inserted in a position
+ * such that it will be the last item within the list returned by multiple
+ * calls to listGET_OWNER_OF_NEXT_ENTRY.
+ *
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.
+ * Placing an item in a list using vListInsertEnd effectively places the item
+ * in the list position pointed to by pxIndex.  This means that every other
+ * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
+ * the pxIndex parameter again points to the item being inserted.
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The list item to be inserted into the list.
+ *
+ * \page vListInsertEnd vListInsertEnd
+ * \ingroup LinkedList
+ */
+void vListInsertEnd( List_t * const pxList,
+                     ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Remove an item from a list.  The list item has a pointer to the list that
+ * it is in, so only the list item need be passed into the function.
+ *
+ * @param uxListRemove The item to be removed.  The item will remove itself from
+ * the list pointed to by it's pxContainer parameter.
+ *
+ * @return The number of items that remain in the list after the list item has
+ * been removed.
+ *
+ * \page uxListRemove uxListRemove
+ * \ingroup LinkedList
+ */
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION;
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* ifndef LIST_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/message_buffer.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/message_buffer.h
new file mode 100644
index 0000000..a9d21ce
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/message_buffer.h
@@ -0,0 +1,821 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+/*
+ * Message buffers build functionality on top of FreeRTOS stream buffers.
+ * Whereas stream buffers are used to send a continuous stream of data from one
+ * task or interrupt to another, message buffers are used to send variable
+ * length discrete messages from one task or interrupt to another.  Their
+ * implementation is light weight, making them particularly suited for interrupt
+ * to task and core to core communication scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * timeout to 0.
+ *
+ * Message buffers hold variable length messages.  To enable that, when a
+ * message is written to the message buffer an additional sizeof( size_t ) bytes
+ * are also written to store the message's length (that happens internally, with
+ * the API function).  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so writing a 10 byte message to a message buffer on a 32-bit
+ * architecture will actually reduce the available space in the message buffer
+ * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length
+ * of the message).
+ */
+
+#ifndef FREERTOS_MESSAGE_BUFFER_H
+#define FREERTOS_MESSAGE_BUFFER_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h must appear in source files before include message_buffer.h"
+#endif
+
+/* Message buffers are built onto of stream buffers. */
+#include "stream_buffer.h"
+
+/* *INDENT-OFF* */
+#if defined( __cplusplus )
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/**
+ * Type by which message buffers are referenced.  For example, a call to
+ * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can
+ * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(),
+ * etc.
+ */
+typedef void * MessageBufferHandle_t;
+
+/*-----------------------------------------------------------*/
+
+/**
+ * message_buffer.h
+ *
+ * <pre>
+ * MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
+ * </pre>
+ *
+ * Creates a new message buffer using dynamically allocated memory.  See
+ * xMessageBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xMessageBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes (not messages) the message
+ * buffer will be able to hold at any one time.  When a message is written to
+ * the message buffer an additional sizeof( size_t ) bytes are also written to
+ * store the message's length.  sizeof( size_t ) is typically 4 bytes on a
+ * 32-bit architecture, so on most 32-bit architectures a 10 byte message will
+ * take up 14 bytes of message buffer space.
+ *
+ * @return If NULL is returned, then the message buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the message buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the message buffer has been created successfully -
+ * the returned value should be stored as the handle to the created message
+ * buffer.
+ *
+ * Example use:
+ * <pre>
+ *
+ * void vAFunction( void )
+ * {
+ * MessageBufferHandle_t xMessageBuffer;
+ * const size_t xMessageBufferSizeBytes = 100;
+ *
+ *  // Create a message buffer that can hold 100 bytes.  The memory used to hold
+ *  // both the message buffer structure and the messages themselves is allocated
+ *  // dynamically.  Each message added to the buffer consumes an additional 4
+ *  // bytes which are used to hold the lengh of the message.
+ *  xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
+ *
+ *  if( xMessageBuffer == NULL )
+ *  {
+ *      // There was not enough heap memory space available to create the
+ *      // message buffer.
+ *  }
+ *  else
+ *  {
+ *      // The message buffer was created successfully and can now be used.
+ *  }
+ *
+ * </pre>
+ * \defgroup xMessageBufferCreate xMessageBufferCreate
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferCreate( xBufferSizeBytes ) \
+    ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE )
+
+/**
+ * message_buffer.h
+ *
+ * <pre>
+ * MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
+ *                                                uint8_t *pucMessageBufferStorageArea,
+ *                                                StaticMessageBuffer_t *pxStaticMessageBuffer );
+ * </pre>
+ * Creates a new message buffer using statically allocated memory.  See
+ * xMessageBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucMessageBufferStorageArea parameter.  When a message is written to the
+ * message buffer an additional sizeof( size_t ) bytes are also written to store
+ * the message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so on most 32-bit architecture a 10 byte message will take up
+ * 14 bytes of message buffer space.  The maximum number of bytes that can be
+ * stored in the message buffer is actually (xBufferSizeBytes - 1).
+ *
+ * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big.  This is the array to which messages are
+ * copied when they are written to the message buffer.
+ *
+ * @param pxStaticMessageBuffer Must point to a variable of type
+ * StaticMessageBuffer_t, which will be used to hold the message buffer's data
+ * structure.
+ *
+ * @return If the message buffer is created successfully then a handle to the
+ * created message buffer is returned. If either pucMessageBufferStorageArea or
+ * pxStaticmessageBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+ * <pre>
+ *
+ * // Used to dimension the array used to hold the messages.  The available space
+ * // will actually be one less than this, so 999.
+ #define STORAGE_SIZE_BYTES 1000
+ *
+ * // Defines the memory that will actually hold the messages within the message
+ * // buffer.
+ * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+ *
+ * // The variable used to hold the message buffer structure.
+ * StaticMessageBuffer_t xMessageBufferStruct;
+ *
+ * void MyFunction( void )
+ * {
+ * MessageBufferHandle_t xMessageBuffer;
+ *
+ *  xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
+ *                                               ucBufferStorage,
+ *                                               &xMessageBufferStruct );
+ *
+ *  // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
+ *  // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
+ *  // reference the created message buffer in other message buffer API calls.
+ *
+ *  // Other code that uses the message buffer can go here.
+ * }
+ *
+ * </pre>
+ * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) \
+    ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer )
+
+/**
+ * message_buffer.h
+ *
+ * <pre>
+ * size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
+ *                         const void *pvTxData,
+ *                         size_t xDataLengthBytes,
+ *                         TickType_t xTicksToWait );
+ * </pre>
+ *
+ * Sends a discrete message to the message buffer.  The message can be any
+ * length that fits within the buffer's free space, and is copied into the
+ * buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param xTicksToWait The maximum amount of time the calling task should remain
+ * in the Blocked state to wait for enough space to become available in the
+ * message buffer, should the message buffer have insufficient space when
+ * xMessageBufferSend() is called.  The calling task will never block if
+ * xTicksToWait is zero.  The block time is specified in tick periods, so the
+ * absolute time it represents is dependent on the tick frequency.  The macro
+ * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
+ * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause
+ * the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The number of bytes written to the message buffer.  If the call to
+ * xMessageBufferSend() times out before there was enough space to write the
+ * message into the message buffer then zero is returned.  If the call did not
+ * time out then xDataLengthBytes is returned.
+ *
+ * Example use:
+ * <pre>
+ * void vAFunction( MessageBufferHandle_t xMessageBuffer )
+ * {
+ * size_t xBytesSent;
+ * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+ * char *pcStringToSend = "String to send";
+ * const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+ *
+ *  // Send an array to the message buffer, blocking for a maximum of 100ms to
+ *  // wait for enough space to be available in the message buffer.
+ *  xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+ *
+ *  if( xBytesSent != sizeof( ucArrayToSend ) )
+ *  {
+ *      // The call to xMessageBufferSend() times out before there was enough
+ *      // space in the buffer for the data to be written.
+ *  }
+ *
+ *  // Send the string to the message buffer.  Return immediately if there is
+ *  // not enough space in the buffer.
+ *  xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // The string could not be added to the message buffer because there was
+ *      // not enough free space in the buffer.
+ *  }
+ * }
+ * </pre>
+ * \defgroup xMessageBufferSend xMessageBufferSend
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) \
+    xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
+
+/**
+ * message_buffer.h
+ *
+ * <pre>
+ * size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
+ *                                const void *pvTxData,
+ *                                size_t xDataLengthBytes,
+ *                                BaseType_t *pxHigherPriorityTaskWoken );
+ * </pre>
+ *
+ * Interrupt safe version of the API function that sends a discrete message to
+ * the message buffer.  The message can be any length that fits within the
+ * buffer's free space, and is copied into the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferSend() to write to a message buffer from a task.  Use
+ * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer to which a message is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the message that is to be copied into the
+ * message buffer.
+ *
+ * @param xDataLengthBytes The length of the message.  That is, the number of
+ * bytes to copy from pvTxData into the message buffer.  When a message is
+ * written to the message buffer an additional sizeof( size_t ) bytes are also
+ * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
+ * on a 32-bit architecture, so on most 32-bit architecture setting
+ * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
+ * bytes (20 bytes of message data and 4 bytes to hold the message length).
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xMessageBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xMessageBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes actually written to the message buffer.  If the
+ * message buffer didn't have enough free space for the message to be stored
+ * then 0 is returned, otherwise xDataLengthBytes is returned.
+ *
+ * Example use:
+ * <pre>
+ * // A message buffer that has already been created.
+ * MessageBufferHandle_t xMessageBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * size_t xBytesSent;
+ * char *pcStringToSend = "String to send";
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+ *
+ *  // Attempt to send the string to the message buffer.
+ *  xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
+ *                                          ( void * ) pcStringToSend,
+ *                                          strlen( pcStringToSend ),
+ *                                          &xHigherPriorityTaskWoken );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // The string could not be added to the message buffer because there was
+ *      // not enough free space in the buffer.
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xMessageBufferSendFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ * </pre>
+ * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) \
+    xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+ * <pre>
+ * size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
+ *                            void *pvRxData,
+ *                            size_t xBufferLengthBytes,
+ *                            TickType_t xTicksToWait );
+ * </pre>
+ *
+ * Receives a discrete message from a message buffer.  Messages can be of
+ * variable length and are copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for a message, should the message buffer be empty.
+ * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
+ * the message buffer is empty.  The block time is specified in tick periods, so
+ * the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
+ * CPU time when they are in the Blocked state.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.  If xMessageBufferReceive() times out before a message became available
+ * then zero is returned.  If the length of the message is greater than
+ * xBufferLengthBytes then the message will be left in the message buffer and
+ * zero is returned.
+ *
+ * Example use:
+ * <pre>
+ * void vAFunction( MessageBuffer_t xMessageBuffer )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+ *
+ *  // Receive the next message from the message buffer.  Wait in the Blocked
+ *  // state (so not using any CPU processing time) for a maximum of 100ms for
+ *  // a message to become available.
+ *  xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
+ *                                          ( void * ) ucRxData,
+ *                                          sizeof( ucRxData ),
+ *                                          xBlockTime );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // A ucRxData contains a message that is xReceivedBytes long.  Process
+ *      // the message here....
+ *  }
+ * }
+ * </pre>
+ * \defgroup xMessageBufferReceive xMessageBufferReceive
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) \
+    xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
+
+
+/**
+ * message_buffer.h
+ *
+ * <pre>
+ * size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
+ *                                   void *pvRxData,
+ *                                   size_t xBufferLengthBytes,
+ *                                   BaseType_t *pxHigherPriorityTaskWoken );
+ * </pre>
+ *
+ * An interrupt safe version of the API function that receives a discrete
+ * message from a message buffer.  Messages can be of variable length and are
+ * copied out of the buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xMessageBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xMessageBufferRead()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
+ * xMessageBufferReceiveFromISR() to read from a message buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xMessageBuffer The handle of the message buffer from which a message
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received message is
+ * to be copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
+ * parameter.  This sets the maximum length of the message that can be received.
+ * If xBufferLengthBytes is too small to hold the next message then the message
+ * will be left in the message buffer and 0 will be returned.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xMessageBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The length, in bytes, of the message read from the message buffer, if
+ * any.
+ *
+ * Example use:
+ * <pre>
+ * // A message buffer that has already been created.
+ * MessageBuffer_t xMessageBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+ *
+ *  // Receive the next message from the message buffer.
+ *  xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
+ *                                                ( void * ) ucRxData,
+ *                                                sizeof( ucRxData ),
+ *                                                &xHigherPriorityTaskWoken );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // A ucRxData contains a message that is xReceivedBytes long.  Process
+ *      // the message here....
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xMessageBufferReceiveFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into portYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ * </pre>
+ * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) \
+    xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+ * <pre>
+ * void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
+ * </pre>
+ *
+ * Deletes a message buffer that was previously created using a call to
+ * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
+ * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A message buffer handle must not be used after the message buffer has been
+ * deleted.
+ *
+ * @param xMessageBuffer The handle of the message buffer to be deleted.
+ *
+ */
+#define vMessageBufferDelete( xMessageBuffer ) \
+    vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+ * <pre>
+ * BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
+ * </pre>
+ *
+ * Tests to see if a message buffer is full.  A message buffer is full if it
+ * cannot accept any more messages, of any size, until space is made available
+ * by a message being removed from the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is full then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ */
+#define xMessageBufferIsFull( xMessageBuffer ) \
+    xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+ * <pre>
+ * BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
+ * </pre>
+ *
+ * Tests to see if a message buffer is empty (does not contain any messages).
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return If the message buffer referenced by xMessageBuffer is empty then
+ * pdTRUE is returned.  Otherwise pdFALSE is returned.
+ *
+ */
+#define xMessageBufferIsEmpty( xMessageBuffer ) \
+    xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
+
+/**
+ * message_buffer.h
+ * <pre>
+ * BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
+ * </pre>
+ *
+ * Resets a message buffer to its initial empty state, discarding any message it
+ * contained.
+ *
+ * A message buffer can only be reset if there are no tasks blocked on it.
+ *
+ * @param xMessageBuffer The handle of the message buffer being reset.
+ *
+ * @return If the message buffer was reset then pdPASS is returned.  If the
+ * message buffer could not be reset because either there was a task blocked on
+ * the message queue to wait for space to become available, or to wait for a
+ * a message to be available, then pdFAIL is returned.
+ *
+ * \defgroup xMessageBufferReset xMessageBufferReset
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferReset( xMessageBuffer ) \
+    xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
+
+
+/**
+ * message_buffer.h
+ * <pre>
+ * size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
+ * </pre>
+ * Returns the number of bytes of free space in the message buffer.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The number of bytes that can be written to the message buffer before
+ * the message buffer would be full.  When a message is written to the message
+ * buffer an additional sizeof( size_t ) bytes are also written to store the
+ * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
+ * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
+ * of the largest message that can be written to the message buffer is 6 bytes.
+ *
+ * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferSpaceAvailable( xMessageBuffer ) \
+    xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
+#define xMessageBufferSpacesAvailable( xMessageBuffer ) \
+    xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */
+
+/**
+ * message_buffer.h
+ * <pre>
+ * size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
+ * </pre>
+ * Returns the length (in bytes) of the next message in a message buffer.
+ * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
+ * passed into xMessageBufferReceive() was too small to hold the next message.
+ *
+ * @param xMessageBuffer The handle of the message buffer being queried.
+ *
+ * @return The length (in bytes) of the next message in the message buffer, or 0
+ * if the message buffer is empty.
+ *
+ * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
+ * \ingroup MessageBufferManagement
+ */
+#define xMessageBufferNextLengthBytes( xMessageBuffer ) \
+    xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * message_buffer.h
+ *
+ * <pre>
+ * BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ * </pre>
+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferSendCompletedFromISR().  If calling
+ * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \
+    xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+/**
+ * message_buffer.h
+ *
+ * <pre>
+ * BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ * </pre>
+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xMessageBufferReceiveCompletedFromISR().  If calling
+ * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) \
+    xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
+
+/* *INDENT-OFF* */
+#if defined( __cplusplus )
+    } /* extern "C" */
+#endif
+/* *INDENT-ON* */
+
+#endif /* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/mpu_prototypes.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/mpu_prototypes.h
new file mode 100644
index 0000000..61f885d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/mpu_prototypes.h
@@ -0,0 +1,257 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * When the MPU is used the standard (non MPU) API functions are mapped to
+ * equivalents that start "MPU_", the prototypes for which are defined in this
+ * header files.  This will cause the application code to call the MPU_ version
+ * which wraps the non-MPU version with privilege promoting then demoting code,
+ * so the kernel code always runs will full privileges.
+ */
+
+
+#ifndef MPU_PROTOTYPES_H
+#define MPU_PROTOTYPES_H
+
+/* MPU versions of tasks.h API functions. */
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode,
+                            const char * const pcName,
+                            const uint16_t usStackDepth,
+                            void * const pvParameters,
+                            UBaseType_t uxPriority,
+                            TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
+                                    const char * const pcName,
+                                    const uint32_t ulStackDepth,
+                                    void * const pvParameters,
+                                    UBaseType_t uxPriority,
+                                    StackType_t * const puxStackBuffer,
+                                    StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                          const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                       TaskStatus_t * pxTaskStatus,
+                       BaseType_t xGetFreeStackSpace,
+                       eTaskState eState ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskPrioritySet( TaskHandle_t xTask,
+                           UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                     TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                            BaseType_t xIndex,
+                                            void * pvValue ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                               BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
+                                             void * pvParameter ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                      const UBaseType_t uxArraySize,
+                                      uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                   UBaseType_t uxIndexToNotify,
+                                   uint32_t ulValue,
+                                   eNotifyAction eAction,
+                                   uint32_t * pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                       uint32_t ulBitsToClearOnEntry,
+                                       uint32_t ulBitsToClearOnExit,
+                                       uint32_t * pulNotificationValue,
+                                       TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                      BaseType_t xClearCountOnExit,
+                                      TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                             UBaseType_t uxIndexToClear ) FREERTOS_SYSTEM_CALL;
+uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                            UBaseType_t uxIndexToClear,
+                                            uint32_t ulBitsToClear ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                     TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of queue.h API functions. */
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                  const void * const pvItemToQueue,
+                                  TickType_t xTicksToWait,
+                                  const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue,
+                              void * const pvBuffer,
+                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                           void * const pvBuffer,
+                           TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                    TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,
+                                           StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
+                                                 const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
+                                                       const UBaseType_t uxInitialCount,
+                                                       StaticQueue_t * pxStaticQueue ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                         TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                              const char * pcName ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength,
+                                       const UBaseType_t uxItemSize,
+                                       const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
+                                             const UBaseType_t uxItemSize,
+                                             uint8_t * pucQueueStorage,
+                                             StaticQueue_t * pxStaticQueue,
+                                             const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                               QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                    QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue,
+                                   BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue,
+                               UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of timers.h API functions. */
+TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName,
+                                const TickType_t xTimerPeriodInTicks,
+                                const UBaseType_t uxAutoReload,
+                                void * const pvTimerID,
+                                TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
+TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName,
+                                      const TickType_t xTimerPeriodInTicks,
+                                      const UBaseType_t uxAutoReload,
+                                      void * const pvTimerID,
+                                      TimerCallbackFunction_t pxCallbackFunction,
+                                      StaticTimer_t * pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                           void * pvNewID ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+                                       void * pvParameter1,
+                                       uint32_t ulParameter2,
+                                       TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                              const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
+                                     const BaseType_t xCommandID,
+                                     const TickType_t xOptionalValue,
+                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                     const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of event_group.h API functions. */
+EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToWaitFor,
+                                     const BaseType_t xClearOnExit,
+                                     const BaseType_t xWaitForAllBits,
+                                     TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                      const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                    const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                 const EventBits_t uxBitsToSet,
+                                 const EventBits_t uxBitsToWaitFor,
+                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
+UBaseType_t MPU_uxEventGroupGetNumber( void * xEventGroup ) FREERTOS_SYSTEM_CALL;
+
+/* MPU versions of message/stream_buffer.h API functions. */
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                              const void * pvTxData,
+                              size_t xDataLengthBytes,
+                              TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                 void * pvRxData,
+                                 size_t xBufferLengthBytes,
+                                 TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                             size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+                                                     size_t xTriggerLevelBytes,
+                                                     BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
+StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+                                                           size_t xTriggerLevelBytes,
+                                                           BaseType_t xIsMessageBuffer,
+                                                           uint8_t * const pucStreamBufferStorageArea,
+                                                           StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
+
+
+
+#endif /* MPU_PROTOTYPES_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/mpu_wrappers.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/mpu_wrappers.h
new file mode 100644
index 0000000..a5c081f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/mpu_wrappers.h
@@ -0,0 +1,185 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef MPU_WRAPPERS_H
+#define MPU_WRAPPERS_H
+
+/* This file redefines API functions to be called through a wrapper macro, but
+ * only for ports that are using the MPU. */
+#ifdef portUSING_MPU_WRAPPERS
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
+ * included from queue.c or task.c to prevent it from having an effect within
+ * those files. */
+    #ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/*
+ * Map standard (non MPU) API functions to equivalents that start
+ * "MPU_".  This will cause the application code to call the MPU_
+ * version, which wraps the non-MPU version with privilege promoting
+ * then demoting code, so the kernel code always runs will full
+ * privileges.
+ */
+
+/* Map standard tasks.h API functions to the MPU equivalents. */
+        #define xTaskCreate                            MPU_xTaskCreate
+        #define xTaskCreateStatic                      MPU_xTaskCreateStatic
+        #define vTaskDelete                            MPU_vTaskDelete
+        #define vTaskDelay                             MPU_vTaskDelay
+        #define xTaskDelayUntil                        MPU_xTaskDelayUntil
+        #define xTaskAbortDelay                        MPU_xTaskAbortDelay
+        #define uxTaskPriorityGet                      MPU_uxTaskPriorityGet
+        #define eTaskGetState                          MPU_eTaskGetState
+        #define vTaskGetInfo                           MPU_vTaskGetInfo
+        #define vTaskPrioritySet                       MPU_vTaskPrioritySet
+        #define vTaskSuspend                           MPU_vTaskSuspend
+        #define vTaskResume                            MPU_vTaskResume
+        #define vTaskSuspendAll                        MPU_vTaskSuspendAll
+        #define xTaskResumeAll                         MPU_xTaskResumeAll
+        #define xTaskGetTickCount                      MPU_xTaskGetTickCount
+        #define uxTaskGetNumberOfTasks                 MPU_uxTaskGetNumberOfTasks
+        #define pcTaskGetName                          MPU_pcTaskGetName
+        #define xTaskGetHandle                         MPU_xTaskGetHandle
+        #define uxTaskGetStackHighWaterMark            MPU_uxTaskGetStackHighWaterMark
+        #define uxTaskGetStackHighWaterMark2           MPU_uxTaskGetStackHighWaterMark2
+        #define vTaskSetApplicationTaskTag             MPU_vTaskSetApplicationTaskTag
+        #define xTaskGetApplicationTaskTag             MPU_xTaskGetApplicationTaskTag
+        #define vTaskSetThreadLocalStoragePointer      MPU_vTaskSetThreadLocalStoragePointer
+        #define pvTaskGetThreadLocalStoragePointer     MPU_pvTaskGetThreadLocalStoragePointer
+        #define xTaskCallApplicationTaskHook           MPU_xTaskCallApplicationTaskHook
+        #define xTaskGetIdleTaskHandle                 MPU_xTaskGetIdleTaskHandle
+        #define uxTaskGetSystemState                   MPU_uxTaskGetSystemState
+        #define vTaskList                              MPU_vTaskList
+        #define vTaskGetRunTimeStats                   MPU_vTaskGetRunTimeStats
+        #define ulTaskGetIdleRunTimeCounter            MPU_ulTaskGetIdleRunTimeCounter
+        #define xTaskGenericNotify                     MPU_xTaskGenericNotify
+        #define xTaskGenericNotifyWait                 MPU_xTaskGenericNotifyWait
+        #define ulTaskGenericNotifyTake                MPU_ulTaskGenericNotifyTake
+        #define xTaskGenericNotifyStateClear           MPU_xTaskGenericNotifyStateClear
+        #define ulTaskGenericNotifyValueClear          MPU_ulTaskGenericNotifyValueClear
+        #define xTaskCatchUpTicks                      MPU_xTaskCatchUpTicks
+
+        #define xTaskGetCurrentTaskHandle              MPU_xTaskGetCurrentTaskHandle
+        #define vTaskSetTimeOutState                   MPU_vTaskSetTimeOutState
+        #define xTaskCheckForTimeOut                   MPU_xTaskCheckForTimeOut
+        #define xTaskGetSchedulerState                 MPU_xTaskGetSchedulerState
+
+/* Map standard queue.h API functions to the MPU equivalents. */
+        #define xQueueGenericSend                      MPU_xQueueGenericSend
+        #define xQueueReceive                          MPU_xQueueReceive
+        #define xQueuePeek                             MPU_xQueuePeek
+        #define xQueueSemaphoreTake                    MPU_xQueueSemaphoreTake
+        #define uxQueueMessagesWaiting                 MPU_uxQueueMessagesWaiting
+        #define uxQueueSpacesAvailable                 MPU_uxQueueSpacesAvailable
+        #define vQueueDelete                           MPU_vQueueDelete
+        #define xQueueCreateMutex                      MPU_xQueueCreateMutex
+        #define xQueueCreateMutexStatic                MPU_xQueueCreateMutexStatic
+        #define xQueueCreateCountingSemaphore          MPU_xQueueCreateCountingSemaphore
+        #define xQueueCreateCountingSemaphoreStatic    MPU_xQueueCreateCountingSemaphoreStatic
+        #define xQueueGetMutexHolder                   MPU_xQueueGetMutexHolder
+        #define xQueueTakeMutexRecursive               MPU_xQueueTakeMutexRecursive
+        #define xQueueGiveMutexRecursive               MPU_xQueueGiveMutexRecursive
+        #define xQueueGenericCreate                    MPU_xQueueGenericCreate
+        #define xQueueGenericCreateStatic              MPU_xQueueGenericCreateStatic
+        #define xQueueCreateSet                        MPU_xQueueCreateSet
+        #define xQueueAddToSet                         MPU_xQueueAddToSet
+        #define xQueueRemoveFromSet                    MPU_xQueueRemoveFromSet
+        #define xQueueSelectFromSet                    MPU_xQueueSelectFromSet
+        #define xQueueGenericReset                     MPU_xQueueGenericReset
+
+        #if ( configQUEUE_REGISTRY_SIZE > 0 )
+            #define vQueueAddToRegistry                MPU_vQueueAddToRegistry
+            #define vQueueUnregisterQueue              MPU_vQueueUnregisterQueue
+            #define pcQueueGetName                     MPU_pcQueueGetName
+        #endif
+
+/* Map standard timer.h API functions to the MPU equivalents. */
+        #define xTimerCreate                           MPU_xTimerCreate
+        #define xTimerCreateStatic                     MPU_xTimerCreateStatic
+        #define pvTimerGetTimerID                      MPU_pvTimerGetTimerID
+        #define vTimerSetTimerID                       MPU_vTimerSetTimerID
+        #define xTimerIsTimerActive                    MPU_xTimerIsTimerActive
+        #define xTimerGetTimerDaemonTaskHandle         MPU_xTimerGetTimerDaemonTaskHandle
+        #define xTimerPendFunctionCall                 MPU_xTimerPendFunctionCall
+        #define pcTimerGetName                         MPU_pcTimerGetName
+        #define vTimerSetReloadMode                    MPU_vTimerSetReloadMode
+        #define uxTimerGetReloadMode                   MPU_uxTimerGetReloadMode
+        #define xTimerGetPeriod                        MPU_xTimerGetPeriod
+        #define xTimerGetExpiryTime                    MPU_xTimerGetExpiryTime
+        #define xTimerGenericCommand                   MPU_xTimerGenericCommand
+
+/* Map standard event_group.h API functions to the MPU equivalents. */
+        #define xEventGroupCreate                      MPU_xEventGroupCreate
+        #define xEventGroupCreateStatic                MPU_xEventGroupCreateStatic
+        #define xEventGroupWaitBits                    MPU_xEventGroupWaitBits
+        #define xEventGroupClearBits                   MPU_xEventGroupClearBits
+        #define xEventGroupSetBits                     MPU_xEventGroupSetBits
+        #define xEventGroupSync                        MPU_xEventGroupSync
+        #define vEventGroupDelete                      MPU_vEventGroupDelete
+
+/* Map standard message/stream_buffer.h API functions to the MPU
+ * equivalents. */
+        #define xStreamBufferSend                      MPU_xStreamBufferSend
+        #define xStreamBufferReceive                   MPU_xStreamBufferReceive
+        #define xStreamBufferNextMessageLengthBytes    MPU_xStreamBufferNextMessageLengthBytes
+        #define vStreamBufferDelete                    MPU_vStreamBufferDelete
+        #define xStreamBufferIsFull                    MPU_xStreamBufferIsFull
+        #define xStreamBufferIsEmpty                   MPU_xStreamBufferIsEmpty
+        #define xStreamBufferReset                     MPU_xStreamBufferReset
+        #define xStreamBufferSpacesAvailable           MPU_xStreamBufferSpacesAvailable
+        #define xStreamBufferBytesAvailable            MPU_xStreamBufferBytesAvailable
+        #define xStreamBufferSetTriggerLevel           MPU_xStreamBufferSetTriggerLevel
+        #define xStreamBufferGenericCreate             MPU_xStreamBufferGenericCreate
+        #define xStreamBufferGenericCreateStatic       MPU_xStreamBufferGenericCreateStatic
+
+
+/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
+ * macro so applications can place data in privileged access sections
+ * (useful when using statically allocated objects). */
+        #define PRIVILEGED_FUNCTION
+        #define PRIVILEGED_DATA    __attribute__( ( section( "privileged_data" ) ) )
+        #define FREERTOS_SYSTEM_CALL
+
+    #else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+/* Ensure API functions go in the privileged execution section. */
+        #define PRIVILEGED_FUNCTION     __attribute__( ( section( "privileged_functions" ) ) )
+        #define PRIVILEGED_DATA         __attribute__( ( section( "privileged_data" ) ) )
+        #define FREERTOS_SYSTEM_CALL    __attribute__( ( section( "freertos_system_calls" ) ) )
+
+    #endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+#else /* portUSING_MPU_WRAPPERS */
+
+    #define PRIVILEGED_FUNCTION
+    #define PRIVILEGED_DATA
+    #define FREERTOS_SYSTEM_CALL
+    #define portUSING_MPU_WRAPPERS    0
+
+#endif /* portUSING_MPU_WRAPPERS */
+
+
+#endif /* MPU_WRAPPERS_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/portable.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/portable.h
new file mode 100644
index 0000000..4f4c1d5
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/portable.h
@@ -0,0 +1,216 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Portable layer API.  Each function must be defined for each port.
+*----------------------------------------------------------*/
+
+#ifndef PORTABLE_H
+#define PORTABLE_H
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+ * pre-processor definition was used to ensure the pre-processor found the correct
+ * portmacro.h file for the port being used.  That scheme was deprecated in favour
+ * of setting the compiler's include path such that it found the correct
+ * portmacro.h file - removing the need for the constant and allowing the
+ * portmacro.h file to be located anywhere in relation to the port being used.
+ * Purely for reasons of backward compatibility the old method is still valid, but
+ * to make it clear that new projects should not use it, support for the port
+ * specific constants has been moved into the deprecated_definitions.h header
+ * file. */
+#include "deprecated_definitions.h"
+
+/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
+ * did not result in a portmacro.h header file being included - and it should be
+ * included here.  In this case the path to the correct portmacro.h header file
+ * must be set in the compiler's include path. */
+#ifndef portENTER_CRITICAL
+    #include "portmacro.h"
+#endif
+
+#if portBYTE_ALIGNMENT == 32
+    #define portBYTE_ALIGNMENT_MASK    ( 0x001f )
+#endif
+
+#if portBYTE_ALIGNMENT == 16
+    #define portBYTE_ALIGNMENT_MASK    ( 0x000f )
+#endif
+
+#if portBYTE_ALIGNMENT == 8
+    #define portBYTE_ALIGNMENT_MASK    ( 0x0007 )
+#endif
+
+#if portBYTE_ALIGNMENT == 4
+    #define portBYTE_ALIGNMENT_MASK    ( 0x0003 )
+#endif
+
+#if portBYTE_ALIGNMENT == 2
+    #define portBYTE_ALIGNMENT_MASK    ( 0x0001 )
+#endif
+
+#if portBYTE_ALIGNMENT == 1
+    #define portBYTE_ALIGNMENT_MASK    ( 0x0000 )
+#endif
+
+#ifndef portBYTE_ALIGNMENT_MASK
+    #error "Invalid portBYTE_ALIGNMENT definition"
+#endif
+
+#ifndef portNUM_CONFIGURABLE_REGIONS
+    #define portNUM_CONFIGURABLE_REGIONS    1
+#endif
+
+#ifndef portHAS_STACK_OVERFLOW_CHECKING
+    #define portHAS_STACK_OVERFLOW_CHECKING    0
+#endif
+
+#ifndef portARCH_NAME
+    #define portARCH_NAME    NULL
+#endif
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+#include "mpu_wrappers.h"
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ */
+#if ( portUSING_MPU_WRAPPERS == 1 )
+    #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                             StackType_t * pxEndOfStack,
+                                             TaskFunction_t pxCode,
+                                             void * pvParameters,
+                                             BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+    #else
+        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                             TaskFunction_t pxCode,
+                                             void * pvParameters,
+                                             BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+    #endif
+#else /* if ( portUSING_MPU_WRAPPERS == 1 ) */
+    #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                             StackType_t * pxEndOfStack,
+                                             TaskFunction_t pxCode,
+                                             void * pvParameters ) PRIVILEGED_FUNCTION;
+    #else
+        StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                             TaskFunction_t pxCode,
+                                             void * pvParameters ) PRIVILEGED_FUNCTION;
+    #endif
+#endif /* if ( portUSING_MPU_WRAPPERS == 1 ) */
+
+/* Used by heap_5.c to define the start address and size of each memory region
+ * that together comprise the total FreeRTOS heap space. */
+typedef struct HeapRegion
+{
+    uint8_t * pucStartAddress;
+    size_t xSizeInBytes;
+} HeapRegion_t;
+
+/* Used to pass information about the heap out of vPortGetHeapStats(). */
+typedef struct xHeapStats
+{
+    size_t xAvailableHeapSpaceInBytes;          /* The total heap size currently available - this is the sum of all the free blocks, not the largest block that can be allocated. */
+    size_t xSizeOfLargestFreeBlockInBytes;      /* The maximum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+    size_t xSizeOfSmallestFreeBlockInBytes;     /* The minimum size, in bytes, of all the free blocks within the heap at the time vPortGetHeapStats() is called. */
+    size_t xNumberOfFreeBlocks;                 /* The number of free memory blocks within the heap at the time vPortGetHeapStats() is called. */
+    size_t xMinimumEverFreeBytesRemaining;      /* The minimum amount of total free memory (sum of all free blocks) there has been in the heap since the system booted. */
+    size_t xNumberOfSuccessfulAllocations;      /* The number of calls to pvPortMalloc() that have returned a valid memory block. */
+    size_t xNumberOfSuccessfulFrees;            /* The number of calls to vPortFree() that has successfully freed a block of memory. */
+} HeapStats_t;
+
+/*
+ * Used to define multiple heap regions for use by heap_5.c.  This function
+ * must be called before any calls to pvPortMalloc() - not creating a task,
+ * queue, semaphore, mutex, software timer, event group, etc. will result in
+ * pvPortMalloc being called.
+ *
+ * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
+ * defines a region of memory that can be used as the heap.  The array is
+ * terminated by a HeapRegions_t structure that has a size of 0.  The region
+ * with the lowest start address must appear first in the array.
+ */
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns a HeapStats_t structure filled with information about the current
+ * heap state.
+ */
+void vPortGetHeapStats( HeapStats_t * pxHeapStats );
+
+/*
+ * Map to the memory management routines required for the port.
+ */
+void * pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void vPortFree( void * pv ) PRIVILEGED_FUNCTION;
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the hardware ready for the scheduler to take control.  This generally
+ * sets up a tick interrupt and sets timers for the correct tick frequency.
+ */
+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
+ * the hardware is left in its original condition after the scheduler stops
+ * executing.
+ */
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+#if ( portUSING_MPU_WRAPPERS == 1 )
+    struct xMEMORY_REGION;
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+#endif
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTABLE_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/projdefs.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/projdefs.h
new file mode 100644
index 0000000..fd9072c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/projdefs.h
@@ -0,0 +1,120 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/*
+ * Defines the prototype to which task functions must conform.  Defined in this
+ * file to ensure the type is known before portable.h is included.
+ */
+typedef void (* TaskFunction_t)( void * );
+
+/* Converts a time in milliseconds to a time in ticks.  This macro can be
+ * overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+ * definition here is not suitable for your application. */
+#ifndef pdMS_TO_TICKS
+    #define pdMS_TO_TICKS( xTimeInMs )    ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000U ) )
+#endif
+
+#define pdFALSE                                  ( ( BaseType_t ) 0 )
+#define pdTRUE                                   ( ( BaseType_t ) 1 )
+
+#define pdPASS                                   ( pdTRUE )
+#define pdFAIL                                   ( pdFALSE )
+#define errQUEUE_EMPTY                           ( ( BaseType_t ) 0 )
+#define errQUEUE_FULL                            ( ( BaseType_t ) 0 )
+
+/* FreeRTOS error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY    ( -1 )
+#define errQUEUE_BLOCKED                         ( -4 )
+#define errQUEUE_YIELD                           ( -5 )
+
+/* Macros used for basic data corruption checks. */
+#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
+    #define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES    0
+#endif
+
+#if ( configUSE_16_BIT_TICKS == 1 )
+    #define pdINTEGRITY_CHECK_VALUE    0x5a5a
+#else
+    #define pdINTEGRITY_CHECK_VALUE    0x5a5a5a5aUL
+#endif
+
+/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
+ * itself. */
+#define pdFREERTOS_ERRNO_NONE             0   /* No errors */
+#define pdFREERTOS_ERRNO_ENOENT           2   /* No such file or directory */
+#define pdFREERTOS_ERRNO_EINTR            4   /* Interrupted system call */
+#define pdFREERTOS_ERRNO_EIO              5   /* I/O error */
+#define pdFREERTOS_ERRNO_ENXIO            6   /* No such device or address */
+#define pdFREERTOS_ERRNO_EBADF            9   /* Bad file number */
+#define pdFREERTOS_ERRNO_EAGAIN           11  /* No more processes */
+#define pdFREERTOS_ERRNO_EWOULDBLOCK      11  /* Operation would block */
+#define pdFREERTOS_ERRNO_ENOMEM           12  /* Not enough memory */
+#define pdFREERTOS_ERRNO_EACCES           13  /* Permission denied */
+#define pdFREERTOS_ERRNO_EFAULT           14  /* Bad address */
+#define pdFREERTOS_ERRNO_EBUSY            16  /* Mount device busy */
+#define pdFREERTOS_ERRNO_EEXIST           17  /* File exists */
+#define pdFREERTOS_ERRNO_EXDEV            18  /* Cross-device link */
+#define pdFREERTOS_ERRNO_ENODEV           19  /* No such device */
+#define pdFREERTOS_ERRNO_ENOTDIR          20  /* Not a directory */
+#define pdFREERTOS_ERRNO_EISDIR           21  /* Is a directory */
+#define pdFREERTOS_ERRNO_EINVAL           22  /* Invalid argument */
+#define pdFREERTOS_ERRNO_ENOSPC           28  /* No space left on device */
+#define pdFREERTOS_ERRNO_ESPIPE           29  /* Illegal seek */
+#define pdFREERTOS_ERRNO_EROFS            30  /* Read only file system */
+#define pdFREERTOS_ERRNO_EUNATCH          42  /* Protocol driver not attached */
+#define pdFREERTOS_ERRNO_EBADE            50  /* Invalid exchange */
+#define pdFREERTOS_ERRNO_EFTYPE           79  /* Inappropriate file type or format */
+#define pdFREERTOS_ERRNO_ENMFILE          89  /* No more files */
+#define pdFREERTOS_ERRNO_ENOTEMPTY        90  /* Directory not empty */
+#define pdFREERTOS_ERRNO_ENAMETOOLONG     91  /* File or path name too long */
+#define pdFREERTOS_ERRNO_EOPNOTSUPP       95  /* Operation not supported on transport endpoint */
+#define pdFREERTOS_ERRNO_ENOBUFS          105 /* No buffer space available */
+#define pdFREERTOS_ERRNO_ENOPROTOOPT      109 /* Protocol not available */
+#define pdFREERTOS_ERRNO_EADDRINUSE       112 /* Address already in use */
+#define pdFREERTOS_ERRNO_ETIMEDOUT        116 /* Connection timed out */
+#define pdFREERTOS_ERRNO_EINPROGRESS      119 /* Connection already in progress */
+#define pdFREERTOS_ERRNO_EALREADY         120 /* Socket already connected */
+#define pdFREERTOS_ERRNO_EADDRNOTAVAIL    125 /* Address not available */
+#define pdFREERTOS_ERRNO_EISCONN          127 /* Socket is already connected */
+#define pdFREERTOS_ERRNO_ENOTCONN         128 /* Socket is not connected */
+#define pdFREERTOS_ERRNO_ENOMEDIUM        135 /* No medium inserted */
+#define pdFREERTOS_ERRNO_EILSEQ           138 /* An invalid UTF-16 sequence was encountered. */
+#define pdFREERTOS_ERRNO_ECANCELED        140 /* Operation canceled. */
+
+/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
+ * itself. */
+#define pdFREERTOS_LITTLE_ENDIAN          0
+#define pdFREERTOS_BIG_ENDIAN             1
+
+/* Re-defining endian values for generic naming. */
+#define pdLITTLE_ENDIAN                   pdFREERTOS_LITTLE_ENDIAN
+#define pdBIG_ENDIAN                      pdFREERTOS_BIG_ENDIAN
+
+
+#endif /* PROJDEFS_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/queue.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/queue.h
new file mode 100644
index 0000000..37ad23c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/queue.h
@@ -0,0 +1,1716 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h" must appear in source files before "include queue.h"
+#endif
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+#include "task.h"
+
+/**
+ * Type by which queues are referenced.  For example, a call to xQueueCreate()
+ * returns an QueueHandle_t variable that can then be used as a parameter to
+ * xQueueSend(), xQueueReceive(), etc.
+ */
+struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */
+typedef struct QueueDefinition   * QueueHandle_t;
+
+/**
+ * Type by which queue sets are referenced.  For example, a call to
+ * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
+ * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
+ */
+typedef struct QueueDefinition   * QueueSetHandle_t;
+
+/**
+ * Queue sets can contain both queues and semaphores, so the
+ * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
+ * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
+ */
+typedef struct QueueDefinition   * QueueSetMemberHandle_t;
+
+/* For internal use only. */
+#define queueSEND_TO_BACK                     ( ( BaseType_t ) 0 )
+#define queueSEND_TO_FRONT                    ( ( BaseType_t ) 1 )
+#define queueOVERWRITE                        ( ( BaseType_t ) 2 )
+
+/* For internal use only.  These definitions *must* match those in queue.c. */
+#define queueQUEUE_TYPE_BASE                  ( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_SET                   ( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_MUTEX                 ( ( uint8_t ) 1U )
+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE    ( ( uint8_t ) 2U )
+#define queueQUEUE_TYPE_BINARY_SEMAPHORE      ( ( uint8_t ) 3U )
+#define queueQUEUE_TYPE_RECURSIVE_MUTEX       ( ( uint8_t ) 4U )
+
+/**
+ * queue. h
+ * <pre>
+ * QueueHandle_t xQueueCreate(
+ *                            UBaseType_t uxQueueLength,
+ *                            UBaseType_t uxItemSize
+ *                        );
+ * </pre>
+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @return If the queue is successfully create then a handle to the newly
+ * created queue is returned.  If the queue cannot be created then 0 is
+ * returned.
+ *
+ * Example usage:
+ * <pre>
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * };
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *  if( xQueue1 == 0 )
+ *  {
+ *      // Queue was not created and must not be used.
+ *  }
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *  if( xQueue2 == 0 )
+ *  {
+ *      // Queue was not created and must not be used.
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ * </pre>
+ * \defgroup xQueueCreate xQueueCreate
+ * \ingroup QueueManagement
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    #define xQueueCreate( uxQueueLength, uxItemSize )    xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
+#endif
+
+/**
+ * queue. h
+ * <pre>
+ * QueueHandle_t xQueueCreateStatic(
+ *                            UBaseType_t uxQueueLength,
+ *                            UBaseType_t uxItemSize,
+ *                            uint8_t *pucQueueStorageBuffer,
+ *                            StaticQueue_t *pxQueueBuffer
+ *                        );
+ * </pre>
+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * https://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @param pucQueueStorageBuffer If uxItemSize is not zero then
+ * pucQueueStorageBuffer must point to a uint8_t array that is at least large
+ * enough to hold the maximum number of items that can be in the queue at any
+ * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
+ * zero then pucQueueStorageBuffer can be NULL.
+ *
+ * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
+ * will be used to hold the queue's data structure.
+ *
+ * @return If the queue is created then a handle to the created queue is
+ * returned.  If pxQueueBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+ * <pre>
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * };
+ *
+ #define QUEUE_LENGTH 10
+ #define ITEM_SIZE sizeof( uint32_t )
+ *
+ * // xQueueBuffer will hold the queue structure.
+ * StaticQueue_t xQueueBuffer;
+ *
+ * // ucQueueStorage will hold the items posted to the queue.  Must be at least
+ * // [(queue length) * ( queue item size)] bytes long.
+ * uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
+ *                          ITEM_SIZE     // The size of each item in the queue
+ *                          &( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
+ *                          &xQueueBuffer ); // The buffer that will hold the queue structure.
+ *
+ *  // The queue is guaranteed to be created successfully as no dynamic memory
+ *  // allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
+ *
+ *  // ... Rest of task code.
+ * }
+ * </pre>
+ * \defgroup xQueueCreateStatic xQueueCreateStatic
+ * \ingroup QueueManagement
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer )    xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * queue. h
+ * <pre>
+ * BaseType_t xQueueSendToToFront(
+ *                                 QueueHandle_t    xQueue,
+ *                                 const void       *pvItemToQueue,
+ *                                 TickType_t       xTicksToWait
+ *                             );
+ * </pre>
+ *
+ * Post an item to the front of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ * <pre>
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * uint32_t ulVar = 10UL;
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *
+ *  // ...
+ *
+ *  if( xQueue1 != 0 )
+ *  {
+ *      // Send an uint32_t.  Wait for 10 ticks for space to become
+ *      // available if necessary.
+ *      if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ *      {
+ *          // Failed to post the message, even after 10 ticks.
+ *      }
+ *  }
+ *
+ *  if( xQueue2 != 0 )
+ *  {
+ *      // Send a pointer to a struct AMessage object.  Don't block if the
+ *      // queue is already full.
+ *      pxMessage = & xMessage;
+ *      xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ * </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) \
+    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
+
+/**
+ * queue. h
+ * <pre>
+ * BaseType_t xQueueSendToBack(
+ *                                 QueueHandle_t    xQueue,
+ *                                 const void       *pvItemToQueue,
+ *                                 TickType_t       xTicksToWait
+ *                             );
+ * </pre>
+ *
+ * This is a macro that calls xQueueGenericSend().
+ *
+ * Post an item to the back of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the queue
+ * is full.  The  time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ * <pre>
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * uint32_t ulVar = 10UL;
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *
+ *  // ...
+ *
+ *  if( xQueue1 != 0 )
+ *  {
+ *      // Send an uint32_t.  Wait for 10 ticks for space to become
+ *      // available if necessary.
+ *      if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ *      {
+ *          // Failed to post the message, even after 10 ticks.
+ *      }
+ *  }
+ *
+ *  if( xQueue2 != 0 )
+ *  {
+ *      // Send a pointer to a struct AMessage object.  Don't block if the
+ *      // queue is already full.
+ *      pxMessage = & xMessage;
+ *      xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ * </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) \
+    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ * BaseType_t xQueueSend(
+ *                            QueueHandle_t xQueue,
+ *                            const void * pvItemToQueue,
+ *                            TickType_t xTicksToWait
+ *                       );
+ * </pre>
+ *
+ * This is a macro that calls xQueueGenericSend().  It is included for
+ * backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
+ * equivalent to xQueueSendToBack().
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ * <pre>
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * uint32_t ulVar = 10UL;
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *
+ *  // ...
+ *
+ *  if( xQueue1 != 0 )
+ *  {
+ *      // Send an uint32_t.  Wait for 10 ticks for space to become
+ *      // available if necessary.
+ *      if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+ *      {
+ *          // Failed to post the message, even after 10 ticks.
+ *      }
+ *  }
+ *
+ *  if( xQueue2 != 0 )
+ *  {
+ *      // Send a pointer to a struct AMessage object.  Don't block if the
+ *      // queue is already full.
+ *      pxMessage = & xMessage;
+ *      xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ * </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) \
+    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ * BaseType_t xQueueOverwrite(
+ *                            QueueHandle_t xQueue,
+ *                            const void * pvItemToQueue
+ *                       );
+ * </pre>
+ *
+ * Only for use with queues that have a length of one - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * This function must not be called from an interrupt service routine.
+ * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle of the queue to which the data is being sent.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
+ * therefore has the same return values as xQueueSendToFront().  However, pdPASS
+ * is the only value that can be returned because xQueueOverwrite() will write
+ * to the queue even when the queue is already full.
+ *
+ * Example usage:
+ * <pre>
+ *
+ * void vFunction( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue;
+ * uint32_t ulVarToSend, ulValReceived;
+ *
+ *  // Create a queue to hold one uint32_t value.  It is strongly
+ *  // recommended *not* to use xQueueOverwrite() on queues that can
+ *  // contain more than one value, and doing so will trigger an assertion
+ *  // if configASSERT() is defined.
+ *  xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+ *
+ *  // Write the value 10 to the queue using xQueueOverwrite().
+ *  ulVarToSend = 10;
+ *  xQueueOverwrite( xQueue, &ulVarToSend );
+ *
+ *  // Peeking the queue should now return 10, but leave the value 10 in
+ *  // the queue.  A block time of zero is used as it is known that the
+ *  // queue holds a value.
+ *  ulValReceived = 0;
+ *  xQueuePeek( xQueue, &ulValReceived, 0 );
+ *
+ *  if( ulValReceived != 10 )
+ *  {
+ *      // Error unless the item was removed by a different task.
+ *  }
+ *
+ *  // The queue is still full.  Use xQueueOverwrite() to overwrite the
+ *  // value held in the queue with 100.
+ *  ulVarToSend = 100;
+ *  xQueueOverwrite( xQueue, &ulVarToSend );
+ *
+ *  // This time read from the queue, leaving the queue empty once more.
+ *  // A block time of 0 is used again.
+ *  xQueueReceive( xQueue, &ulValReceived, 0 );
+ *
+ *  // The value read should be the last value written, even though the
+ *  // queue was already full when the value was written.
+ *  if( ulValReceived != 100 )
+ *  {
+ *      // Error!
+ *  }
+ *
+ *  // ...
+ * }
+ * </pre>
+ * \defgroup xQueueOverwrite xQueueOverwrite
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwrite( xQueue, pvItemToQueue ) \
+    xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
+
+
+/**
+ * queue. h
+ * <pre>
+ * BaseType_t xQueueGenericSend(
+ *                                  QueueHandle_t xQueue,
+ *                                  const void * pvItemToQueue,
+ *                                  TickType_t xTicksToWait
+ *                                  BaseType_t xCopyPosition
+ *                              );
+ * </pre>
+ *
+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
+ * xQueueSendToBack() are used in place of calling this function directly.
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ * <pre>
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * uint32_t ulVar = 10UL;
+ *
+ * void vATask( void *pvParameters )
+ * {
+ * QueueHandle_t xQueue1, xQueue2;
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 uint32_t values.
+ *  xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *
+ *  // ...
+ *
+ *  if( xQueue1 != 0 )
+ *  {
+ *      // Send an uint32_t.  Wait for 10 ticks for space to become
+ *      // available if necessary.
+ *      if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+ *      {
+ *          // Failed to post the message, even after 10 ticks.
+ *      }
+ *  }
+ *
+ *  if( xQueue2 != 0 )
+ *  {
+ *      // Send a pointer to a struct AMessage object.  Don't block if the
+ *      // queue is already full.
+ *      pxMessage = & xMessage;
+ *      xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ * </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
+                              const void * const pvItemToQueue,
+                              TickType_t xTicksToWait,
+                              const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ * BaseType_t xQueuePeek(
+ *                           QueueHandle_t xQueue,
+ *                           void * const pvBuffer,
+ *                           TickType_t xTicksToWait
+ *                       );
+ * </pre>
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * This macro must not be used in an interrupt service routine.  See
+ * xQueuePeekFromISR() for an alternative that can be called from an interrupt
+ * service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call. The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
+ * is empty.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+ * <pre>
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * QueueHandle_t xQueue;
+ *
+ * // Task to create a queue and post a value.
+ * void vATask( void *pvParameters )
+ * {
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *  if( xQueue == 0 )
+ *  {
+ *      // Failed to create the queue.
+ *  }
+ *
+ *  // ...
+ *
+ *  // Send a pointer to a struct AMessage object.  Don't block if the
+ *  // queue is already full.
+ *  pxMessage = & xMessage;
+ *  xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * // Task to peek the data from the queue.
+ * void vADifferentTask( void *pvParameters )
+ * {
+ * struct AMessage *pxRxedMessage;
+ *
+ *  if( xQueue != 0 )
+ *  {
+ *      // Peek a message on the created queue.  Block for 10 ticks if a
+ *      // message is not immediately available.
+ *      if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+ *      {
+ *          // pcRxedMessage now points to the struct AMessage variable posted
+ *          // by vATask, but the item still remains on the queue.
+ *      }
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ * </pre>
+ * \defgroup xQueuePeek xQueuePeek
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeek( QueueHandle_t xQueue,
+                       void * const pvBuffer,
+                       TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ * BaseType_t xQueuePeekFromISR(
+ *                                  QueueHandle_t xQueue,
+ *                                  void *pvBuffer,
+ *                              );
+ * </pre>
+ *
+ * A version of xQueuePeek() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * \defgroup xQueuePeekFromISR xQueuePeekFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
+                              void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ * BaseType_t xQueueReceive(
+ *                               QueueHandle_t xQueue,
+ *                               void *pvBuffer,
+ *                               TickType_t xTicksToWait
+ *                          );
+ * </pre>
+ *
+ * Receive an item from a queue.  The item is received by copy so a buffer of
+ * adequate size must be provided.  The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * Successfully received items are removed from the queue.
+ *
+ * This function must not be used in an interrupt service routine.  See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call. xQueueReceive() will return immediately if xTicksToWait
+ * is zero and the queue is empty.  The time is defined in tick periods so the
+ * constant portTICK_PERIOD_MS should be used to convert to real time if this is
+ * required.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+ * <pre>
+ * struct AMessage
+ * {
+ *  char ucMessageID;
+ *  char ucData[ 20 ];
+ * } xMessage;
+ *
+ * QueueHandle_t xQueue;
+ *
+ * // Task to create a queue and post a value.
+ * void vATask( void *pvParameters )
+ * {
+ * struct AMessage *pxMessage;
+ *
+ *  // Create a queue capable of containing 10 pointers to AMessage structures.
+ *  // These should be passed by pointer as they contain a lot of data.
+ *  xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+ *  if( xQueue == 0 )
+ *  {
+ *      // Failed to create the queue.
+ *  }
+ *
+ *  // ...
+ *
+ *  // Send a pointer to a struct AMessage object.  Don't block if the
+ *  // queue is already full.
+ *  pxMessage = & xMessage;
+ *  xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+ *
+ *  // ... Rest of task code.
+ * }
+ *
+ * // Task to receive from the queue.
+ * void vADifferentTask( void *pvParameters )
+ * {
+ * struct AMessage *pxRxedMessage;
+ *
+ *  if( xQueue != 0 )
+ *  {
+ *      // Receive a message on the created queue.  Block for 10 ticks if a
+ *      // message is not immediately available.
+ *      if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+ *      {
+ *          // pcRxedMessage now points to the struct AMessage variable posted
+ *          // by vATask.
+ *      }
+ *  }
+ *
+ *  // ... Rest of task code.
+ * }
+ * </pre>
+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceive( QueueHandle_t xQueue,
+                          void * const pvBuffer,
+                          TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ * UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );
+ * </pre>
+ *
+ * Return the number of messages stored in a queue.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of messages available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ * UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );
+ * </pre>
+ *
+ * Return the number of free spaces available in a queue.  This is equal to the
+ * number of items that can be sent to the queue before the queue becomes full
+ * if no items are removed.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of spaces available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ * void vQueueDelete( QueueHandle_t xQueue );
+ * </pre>
+ *
+ * Delete a queue - freeing all the memory allocated for storing of items
+ * placed on the queue.
+ *
+ * @param xQueue A handle to the queue to be deleted.
+ *
+ * \defgroup vQueueDelete vQueueDelete
+ * \ingroup QueueManagement
+ */
+void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ * BaseType_t xQueueSendToFrontFromISR(
+ *                                       QueueHandle_t xQueue,
+ *                                       const void *pvItemToQueue,
+ *                                       BaseType_t *pxHigherPriorityTaskWoken
+ *                                    );
+ * </pre>
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the front of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+ * <pre>
+ * void vBufferISR( void )
+ * {
+ * char cIn;
+ * BaseType_t xHigherPrioritTaskWoken;
+ *
+ *  // We have not woken a task at the start of the ISR.
+ *  xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *  // Loop until the buffer is empty.
+ *  do
+ *  {
+ *      // Obtain a byte from the buffer.
+ *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+ *
+ *      // Post the byte.
+ *      xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+ *
+ *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
+ *
+ *  // Now the buffer is empty we can switch context if necessary.
+ *  if( xHigherPriorityTaskWoken )
+ *  {
+ *      taskYIELD ();
+ *  }
+ * }
+ * </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \
+    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
+
+
+/**
+ * queue. h
+ * <pre>
+ * BaseType_t xQueueSendToBackFromISR(
+ *                                       QueueHandle_t xQueue,
+ *                                       const void *pvItemToQueue,
+ *                                       BaseType_t *pxHigherPriorityTaskWoken
+ *                                    );
+ * </pre>
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the back of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+ * <pre>
+ * void vBufferISR( void )
+ * {
+ * char cIn;
+ * BaseType_t xHigherPriorityTaskWoken;
+ *
+ *  // We have not woken a task at the start of the ISR.
+ *  xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *  // Loop until the buffer is empty.
+ *  do
+ *  {
+ *      // Obtain a byte from the buffer.
+ *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+ *
+ *      // Post the byte.
+ *      xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+ *
+ *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
+ *
+ *  // Now the buffer is empty we can switch context if necessary.
+ *  if( xHigherPriorityTaskWoken )
+ *  {
+ *      taskYIELD ();
+ *  }
+ * }
+ * </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \
+    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ * BaseType_t xQueueOverwriteFromISR(
+ *                            QueueHandle_t xQueue,
+ *                            const void * pvItemToQueue,
+ *                            BaseType_t *pxHigherPriorityTaskWoken
+ *                       );
+ * </pre>
+ *
+ * A version of xQueueOverwrite() that can be used in an interrupt service
+ * routine (ISR).
+ *
+ * Only for use with queues that can hold a single item - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return xQueueOverwriteFromISR() is a macro that calls
+ * xQueueGenericSendFromISR(), and therefore has the same return values as
+ * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
+ * returned because xQueueOverwriteFromISR() will write to the queue even when
+ * the queue is already full.
+ *
+ * Example usage:
+ * <pre>
+ *
+ * QueueHandle_t xQueue;
+ *
+ * void vFunction( void *pvParameters )
+ * {
+ *  // Create a queue to hold one uint32_t value.  It is strongly
+ *  // recommended *not* to use xQueueOverwriteFromISR() on queues that can
+ *  // contain more than one value, and doing so will trigger an assertion
+ *  // if configASSERT() is defined.
+ *  xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+ * }
+ *
+ * void vAnInterruptHandler( void )
+ * {
+ * // xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ * uint32_t ulVarToSend, ulValReceived;
+ *
+ *  // Write the value 10 to the queue using xQueueOverwriteFromISR().
+ *  ulVarToSend = 10;
+ *  xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+ *
+ *  // The queue is full, but calling xQueueOverwriteFromISR() again will still
+ *  // pass because the value held in the queue will be overwritten with the
+ *  // new value.
+ *  ulVarToSend = 100;
+ *  xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+ *
+ *  // Reading from the queue will now return 100.
+ *
+ *  // ...
+ *
+ *  if( xHigherPrioritytaskWoken == pdTRUE )
+ *  {
+ *      // Writing to the queue caused a task to unblock and the unblocked task
+ *      // has a priority higher than or equal to the priority of the currently
+ *      // executing task (the task this interrupt interrupted).  Perform a context
+ *      // switch so this interrupt returns directly to the unblocked task.
+ *      portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+ *  }
+ * }
+ * </pre>
+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \
+    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
+
+/**
+ * queue. h
+ * <pre>
+ * BaseType_t xQueueSendFromISR(
+ *                                   QueueHandle_t xQueue,
+ *                                   const void *pvItemToQueue,
+ *                                   BaseType_t *pxHigherPriorityTaskWoken
+ *                              );
+ * </pre>
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().  It is included
+ * for backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
+ * macros.
+ *
+ * Post an item to the back of a queue.  It is safe to use this function from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+ * <pre>
+ * void vBufferISR( void )
+ * {
+ * char cIn;
+ * BaseType_t xHigherPriorityTaskWoken;
+ *
+ *  // We have not woken a task at the start of the ISR.
+ *  xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *  // Loop until the buffer is empty.
+ *  do
+ *  {
+ *      // Obtain a byte from the buffer.
+ *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+ *
+ *      // Post the byte.
+ *      xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+ *
+ *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
+ *
+ *  // Now the buffer is empty we can switch context if necessary.
+ *  if( xHigherPriorityTaskWoken )
+ *  {
+ *      // Actual macro used here is port specific.
+ *      portYIELD_FROM_ISR ();
+ *  }
+ * }
+ * </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) \
+    xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ * BaseType_t xQueueGenericSendFromISR(
+ *                                         QueueHandle_t    xQueue,
+ *                                         const    void    *pvItemToQueue,
+ *                                         BaseType_t  *pxHigherPriorityTaskWoken,
+ *                                         BaseType_t  xCopyPosition
+ *                                     );
+ * </pre>
+ *
+ * It is preferred that the macros xQueueSendFromISR(),
+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
+ * of calling this function directly.  xQueueGiveFromISR() is an
+ * equivalent for use by semaphores that don't actually copy any data.
+ *
+ * Post an item on a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+ * <pre>
+ * void vBufferISR( void )
+ * {
+ * char cIn;
+ * BaseType_t xHigherPriorityTaskWokenByPost;
+ *
+ *  // We have not woken a task at the start of the ISR.
+ *  xHigherPriorityTaskWokenByPost = pdFALSE;
+ *
+ *  // Loop until the buffer is empty.
+ *  do
+ *  {
+ *      // Obtain a byte from the buffer.
+ *      cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+ *
+ *      // Post each byte.
+ *      xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+ *
+ *  } while( portINPUT_BYTE( BUFFER_COUNT ) );
+ *
+ *  // Now the buffer is empty we can switch context if necessary.  Note that the
+ *  // name of the yield function required is port specific.
+ *  if( xHigherPriorityTaskWokenByPost )
+ *  {
+ *      portYIELD_FROM_ISR();
+ *  }
+ * }
+ * </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
+                                     const void * const pvItemToQueue,
+                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                     const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
+                              BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ * BaseType_t xQueueReceiveFromISR(
+ *                                     QueueHandle_t    xQueue,
+ *                                     void             *pvBuffer,
+ *                                     BaseType_t       *pxTaskWoken
+ *                                 );
+ * </pre>
+ *
+ * Receive an item from a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param pxTaskWoken A task may be blocked waiting for space to become
+ * available on the queue.  If xQueueReceiveFromISR causes such a task to
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
+ * remain unchanged.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+ * <pre>
+ *
+ * QueueHandle_t xQueue;
+ *
+ * // Function to create a queue and post some values.
+ * void vAFunction( void *pvParameters )
+ * {
+ * char cValueToPost;
+ * const TickType_t xTicksToWait = ( TickType_t )0xff;
+ *
+ *  // Create a queue capable of containing 10 characters.
+ *  xQueue = xQueueCreate( 10, sizeof( char ) );
+ *  if( xQueue == 0 )
+ *  {
+ *      // Failed to create the queue.
+ *  }
+ *
+ *  // ...
+ *
+ *  // Post some characters that will be used within an ISR.  If the queue
+ *  // is full then this task will block for xTicksToWait ticks.
+ *  cValueToPost = 'a';
+ *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ *  cValueToPost = 'b';
+ *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ *
+ *  // ... keep posting characters ... this task may block when the queue
+ *  // becomes full.
+ *
+ *  cValueToPost = 'c';
+ *  xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ * }
+ *
+ * // ISR that outputs all the characters received on the queue.
+ * void vISR_Routine( void )
+ * {
+ * BaseType_t xTaskWokenByReceive = pdFALSE;
+ * char cRxedChar;
+ *
+ *  while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+ *  {
+ *      // A character was received.  Output the character now.
+ *      vOutputCharacter( cRxedChar );
+ *
+ *      // If removing the character from the queue woke the task that was
+ *      // posting onto the queue cTaskWokenByReceive will have been set to
+ *      // pdTRUE.  No matter how many times this loop iterates only one
+ *      // task will be woken.
+ *  }
+ *
+ *  if( cTaskWokenByPost != ( char ) pdFALSE;
+ *  {
+ *      taskYIELD ();
+ *  }
+ * }
+ * </pre>
+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
+                                 void * const pvBuffer,
+                                 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/*
+ * Utilities to query queues that are safe to use from an ISR.  These utilities
+ * should be used only from witin an ISR, or within a critical section.
+ */
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * The functions defined above are for passing data to and from tasks.  The
+ * functions below are the equivalents for passing data to and from
+ * co-routines.
+ *
+ * These functions are called from the co-routine macro implementation and
+ * should not be called directly from application code.  Instead use the macro
+ * wrappers defined within croutine.h.
+ */
+BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue,
+                                const void * pvItemToQueue,
+                                BaseType_t xCoRoutinePreviouslyWoken );
+BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue,
+                                   void * pvBuffer,
+                                   BaseType_t * pxTaskWoken );
+BaseType_t xQueueCRSend( QueueHandle_t xQueue,
+                         const void * pvItemToQueue,
+                         TickType_t xTicksToWait );
+BaseType_t xQueueCRReceive( QueueHandle_t xQueue,
+                            void * pvBuffer,
+                            TickType_t xTicksToWait );
+
+/*
+ * For internal use only.  Use xSemaphoreCreateMutex(),
+ * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
+ * these functions directly.
+ */
+QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,
+                                       StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
+                                             const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
+                                                   const UBaseType_t uxInitialCount,
+                                                   StaticQueue_t * pxStaticQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ */
+BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                     TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
+
+/*
+ * Reset a queue back to its original empty state.  The return value is now
+ * obsolete and is always set to pdPASS.
+ */
+#define xQueueReset( xQueue )    xQueueGenericReset( xQueue, pdFALSE )
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger.  If you are not using a kernel
+ * aware debugger then this function can be ignored.
+ *
+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
+ * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
+ * within FreeRTOSConfig.h for the registry to be available.  Its value
+ * does not effect the number of queues, semaphores and mutexes that can be
+ * created - just the number that the registry can hold.
+ *
+ * @param xQueue The handle of the queue being added to the registry.  This
+ * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
+ * handles can also be passed in here.
+ *
+ * @param pcName The name to be associated with the handle.  This is the
+ * name that the kernel aware debugger will display.  The queue registry only
+ * stores a pointer to the string - so the string must be persistent (global or
+ * preferably in ROM/Flash), not on the stack.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+    void vQueueAddToRegistry( QueueHandle_t xQueue,
+                              const char * pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
+ * remove the queue, semaphore or mutex from the register.  If you are not using
+ * a kernel aware debugger then this function can be ignored.
+ *
+ * @param xQueue The handle of the queue being removed from the registry.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+    void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * The queue registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
+ * up and return the name of a queue in the queue registry from the queue's
+ * handle.
+ *
+ * @param xQueue The handle of the queue the name of which will be returned.
+ * @return If the queue is in the registry then a pointer to the name of the
+ * queue is returned.  If the queue is not in the registry then NULL is
+ * returned.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+    const char * pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * Generic version of the function used to create a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength,
+                                       const UBaseType_t uxItemSize,
+                                       const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Generic version of the function used to create a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
+                                             const UBaseType_t uxItemSize,
+                                             uint8_t * pucQueueStorage,
+                                             StaticQueue_t * pxStaticQueue,
+                                             const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * before it can be used.  Once created, standard FreeRTOS queues and semaphores
+ * can be added to the set using calls to xQueueAddToSet().
+ * xQueueSelectFromSet() is then used to determine which, if any, of the queues
+ * or semaphores contained in the set is in a state where a queue read or
+ * semaphore take operation would be successful.
+ *
+ * Note 1:  See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set.  Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set.  uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once.  To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value.  Examples:
+ *  + If a queue set is to hold a queue of length 5, another queue of length 12,
+ *    and a binary semaphore, then uxEventQueueLength should be set to
+ *    (5 + 12 + 1), or 18.
+ *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ *    should be set to (1 + 1 + 1 ), or 3.
+ *  + If a queue set is to hold a counting semaphore that has a maximum count of
+ *    5, and a counting semaphore that has a maximum count of 3, then
+ *    uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned.  Otherwise NULL is returned.
+ */
+QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * Adds a queue or semaphore to a queue set that was previously created by a
+ * call to xQueueCreateSet().
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
+ * the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set to which the queue or semaphore
+ * is being added.
+ *
+ * @return If the queue or semaphore was successfully added to the queue set
+ * then pdPASS is returned.  If the queue could not be successfully added to the
+ * queue set because it is already a member of a different queue set then pdFAIL
+ * is returned.
+ */
+BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                           QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
+ * be removed from a set if the queue or semaphore is empty.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
+ * from the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set in which the queue or semaphore
+ * is included.
+ *
+ * @return If the queue or semaphore was successfully removed from the queue set
+ * then pdPASS is returned.  If the queue was not in the queue set, or the
+ * queue (or semaphore) was not empty, then pdFAIL is returned.
+ */
+BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * xQueueSelectFromSet() selects from the members of a queue set a queue or
+ * semaphore that either contains data (in the case of a queue) or is available
+ * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
+ * allows a task to block (pend) on a read operation on all the queues and
+ * semaphores in a queue set simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  See the documentation on https://www.FreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueSet The queue set on which the task will (potentially) block.
+ *
+ * @param xTicksToWait The maximum time, in ticks, that the calling task will
+ * remain in the Blocked state (with other tasks executing) to wait for a member
+ * of the queue set to be ready for a successful queue read or semaphore take
+ * operation.
+ *
+ * @return xQueueSelectFromSet() will return the handle of a queue (cast to
+ * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
+ * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
+ * in the queue set that is available, or NULL if no such queue or semaphore
+ * exists before before the specified block time expires.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                            const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * A version of xQueueSelectFromSet() that can be used from an ISR.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/* Not public API functions. */
+void vQueueWaitForMessageRestricted( QueueHandle_t xQueue,
+                                     TickType_t xTicksToWait,
+                                     const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
+                               BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+void vQueueSetQueueNumber( QueueHandle_t xQueue,
+                           UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* QUEUE_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/semphr.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/semphr.h
new file mode 100644
index 0000000..525a8ec
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/semphr.h
@@ -0,0 +1,1173 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h" must appear in source files before "include semphr.h"
+#endif
+
+#include "queue.h"
+
+typedef QueueHandle_t SemaphoreHandle_t;
+
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH    ( ( uint8_t ) 1U )
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH      ( ( uint8_t ) 0U )
+#define semGIVE_BLOCK_TIME                  ( ( TickType_t ) 0U )
+
+
+/**
+ * semphr. h
+ * <pre>
+ * vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore );
+ * </pre>
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * https://www.FreeRTOS.org/RTOS-task-notifications.html
+ *
+ * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * <i>Macro</i> that implements a semaphore by using the existing queue mechanism.
+ * The queue length is 1 as this is a binary semaphore.  The data size is 0
+ * as we don't want to actually store any data - we just want to know if the
+ * queue is empty or full.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
+ *
+ * Example usage:
+ * <pre>
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+ *  // This is a macro so pass the variable in directly.
+ *  vSemaphoreCreateBinary( xSemaphore );
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ * </pre>
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    #define vSemaphoreCreateBinary( xSemaphore )                                                                                     \
+    {                                                                                                                                \
+        ( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE ); \
+        if( ( xSemaphore ) != NULL )                                                                                                 \
+        {                                                                                                                            \
+            ( void ) xSemaphoreGive( ( xSemaphore ) );                                                                               \
+        }                                                                                                                            \
+    }
+#endif
+
+/**
+ * semphr. h
+ * <pre>
+ * SemaphoreHandle_t xSemaphoreCreateBinary( void );
+ * </pre>
+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * https://www.FreeRTOS.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see https://www.FreeRTOS.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @return Handle to the created semaphore, or NULL if the memory required to
+ * hold the semaphore's data structures could not be allocated.
+ *
+ * Example usage:
+ * <pre>
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+ *  // This is a macro so pass the variable in directly.
+ *  xSemaphore = xSemaphoreCreateBinary();
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ * </pre>
+ * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    #define xSemaphoreCreateBinary()    xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif
+
+/**
+ * semphr. h
+ * <pre>
+ * SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer );
+ * </pre>
+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * NOTE: In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * https://www.FreeRTOS.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see https://www.FreeRTOS.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the semaphore is created then a handle to the created semaphore is
+ * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+ * <pre>
+ * SemaphoreHandle_t xSemaphore = NULL;
+ * StaticSemaphore_t xSemaphoreBuffer;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+ *  // The semaphore's data structures will be placed in the xSemaphoreBuffer
+ *  // variable, the address of which is passed into the function.  The
+ *  // function's parameter is not NULL, so the function will not attempt any
+ *  // dynamic memory allocation, and therefore the function will not return
+ *  // return NULL.
+ *  xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
+ *
+ *  // Rest of task code goes here.
+ * }
+ * </pre>
+ * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
+ * \ingroup Semaphores
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #define xSemaphoreCreateBinaryStatic( pxStaticSemaphore )    xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * <pre>
+ * xSemaphoreTake(
+ *                   SemaphoreHandle_t xSemaphore,
+ *                   TickType_t xBlockTime
+ *               );
+ * </pre>
+ *
+ * <i>Macro</i> to obtain a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting().
+ *
+ * @param xSemaphore A handle to the semaphore being taken - obtained when
+ * the semaphore was created.
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  A block
+ * time of portMAX_DELAY can be used to block indefinitely (provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE
+ * if xBlockTime expired without the semaphore becoming available.
+ *
+ * Example usage:
+ * <pre>
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * // A task that creates a semaphore.
+ * void vATask( void * pvParameters )
+ * {
+ *  // Create the semaphore to guard a shared resource.
+ *  xSemaphore = xSemaphoreCreateBinary();
+ * }
+ *
+ * // A task that uses the semaphore.
+ * void vAnotherTask( void * pvParameters )
+ * {
+ *  // ... Do other things.
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // See if we can obtain the semaphore.  If the semaphore is not available
+ *      // wait 10 ticks to see if it becomes free.
+ *      if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+ *      {
+ *          // We were able to obtain the semaphore and can now access the
+ *          // shared resource.
+ *
+ *          // ...
+ *
+ *          // We have finished accessing the shared resource.  Release the
+ *          // semaphore.
+ *          xSemaphoreGive( xSemaphore );
+ *      }
+ *      else
+ *      {
+ *          // We could not obtain the semaphore and can therefore not access
+ *          // the shared resource safely.
+ *      }
+ *  }
+ * }
+ * </pre>
+ * \defgroup xSemaphoreTake xSemaphoreTake
+ * \ingroup Semaphores
+ */
+#define xSemaphoreTake( xSemaphore, xBlockTime )    xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
+
+/**
+ * semphr. h
+ * <pre>
+ * xSemaphoreTakeRecursive(
+ *                          SemaphoreHandle_t xMutex,
+ *                          TickType_t xBlockTime
+ *                        );
+ * </pre>
+ *
+ * <i>Macro</i> to recursively obtain, or 'take', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being obtained.  This is the
+ * handle returned by xSemaphoreCreateRecursiveMutex();
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  If
+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will
+ * return immediately no matter what the value of xBlockTime.
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
+ * expired without the semaphore becoming available.
+ *
+ * Example usage:
+ * <pre>
+ * SemaphoreHandle_t xMutex = NULL;
+ *
+ * // A task that creates a mutex.
+ * void vATask( void * pvParameters )
+ * {
+ *  // Create the mutex to guard a shared resource.
+ *  xMutex = xSemaphoreCreateRecursiveMutex();
+ * }
+ *
+ * // A task that uses the mutex.
+ * void vAnotherTask( void * pvParameters )
+ * {
+ *  // ... Do other things.
+ *
+ *  if( xMutex != NULL )
+ *  {
+ *      // See if we can obtain the mutex.  If the mutex is not available
+ *      // wait 10 ticks to see if it becomes free.
+ *      if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+ *      {
+ *          // We were able to obtain the mutex and can now access the
+ *          // shared resource.
+ *
+ *          // ...
+ *          // For some reason due to the nature of the code further calls to
+ *          // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+ *          // code these would not be just sequential calls as this would make
+ *          // no sense.  Instead the calls are likely to be buried inside
+ *          // a more complex call structure.
+ *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ *
+ *          // The mutex has now been 'taken' three times, so will not be
+ *          // available to another task until it has also been given back
+ *          // three times.  Again it is unlikely that real code would have
+ *          // these calls sequentially, but instead buried in a more complex
+ *          // call structure.  This is just for illustrative purposes.
+ *          xSemaphoreGiveRecursive( xMutex );
+ *          xSemaphoreGiveRecursive( xMutex );
+ *          xSemaphoreGiveRecursive( xMutex );
+ *
+ *          // Now the mutex can be taken by other tasks.
+ *      }
+ *      else
+ *      {
+ *          // We could not obtain the mutex and can therefore not access
+ *          // the shared resource safely.
+ *      }
+ *  }
+ * }
+ * </pre>
+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
+ * \ingroup Semaphores
+ */
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #define xSemaphoreTakeRecursive( xMutex, xBlockTime )    xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
+#endif
+
+/**
+ * semphr. h
+ * <pre>
+ * xSemaphoreGive( SemaphoreHandle_t xSemaphore );
+ * </pre>
+ *
+ * <i>Macro</i> to release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
+ *
+ * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
+ * an alternative which can be used from an ISR.
+ *
+ * This macro must also not be used on semaphores created using
+ * xSemaphoreCreateRecursiveMutex().
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
+ * Semaphores are implemented using queues.  An error can occur if there is
+ * no space on the queue to post a message - indicating that the
+ * semaphore was not first obtained correctly.
+ *
+ * Example usage:
+ * <pre>
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Create the semaphore to guard a shared resource.
+ *  xSemaphore = vSemaphoreCreateBinary();
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+ *      {
+ *          // We would expect this call to fail because we cannot give
+ *          // a semaphore without first "taking" it!
+ *      }
+ *
+ *      // Obtain the semaphore - don't block if the semaphore is not
+ *      // immediately available.
+ *      if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+ *      {
+ *          // We now have the semaphore and can access the shared resource.
+ *
+ *          // ...
+ *
+ *          // We have finished accessing the shared resource so can free the
+ *          // semaphore.
+ *          if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+ *          {
+ *              // We would not expect this call to fail because we must have
+ *              // obtained the semaphore to get here.
+ *          }
+ *      }
+ *  }
+ * }
+ * </pre>
+ * \defgroup xSemaphoreGive xSemaphoreGive
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGive( xSemaphore )    xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
+
+/**
+ * semphr. h
+ * <pre>
+ * xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex );
+ * </pre>
+ *
+ * <i>Macro</i> to recursively release, or 'give', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being released, or 'given'.  This is the
+ * handle returned by xSemaphoreCreateMutex();
+ *
+ * @return pdTRUE if the semaphore was given.
+ *
+ * Example usage:
+ * <pre>
+ * SemaphoreHandle_t xMutex = NULL;
+ *
+ * // A task that creates a mutex.
+ * void vATask( void * pvParameters )
+ * {
+ *  // Create the mutex to guard a shared resource.
+ *  xMutex = xSemaphoreCreateRecursiveMutex();
+ * }
+ *
+ * // A task that uses the mutex.
+ * void vAnotherTask( void * pvParameters )
+ * {
+ *  // ... Do other things.
+ *
+ *  if( xMutex != NULL )
+ *  {
+ *      // See if we can obtain the mutex.  If the mutex is not available
+ *      // wait 10 ticks to see if it becomes free.
+ *      if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+ *      {
+ *          // We were able to obtain the mutex and can now access the
+ *          // shared resource.
+ *
+ *          // ...
+ *          // For some reason due to the nature of the code further calls to
+ *          // xSemaphoreTakeRecursive() are made on the same mutex.  In real
+ *          // code these would not be just sequential calls as this would make
+ *          // no sense.  Instead the calls are likely to be buried inside
+ *          // a more complex call structure.
+ *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ *          xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+ *
+ *          // The mutex has now been 'taken' three times, so will not be
+ *          // available to another task until it has also been given back
+ *          // three times.  Again it is unlikely that real code would have
+ *          // these calls sequentially, it would be more likely that the calls
+ *          // to xSemaphoreGiveRecursive() would be called as a call stack
+ *          // unwound.  This is just for demonstrative purposes.
+ *          xSemaphoreGiveRecursive( xMutex );
+ *          xSemaphoreGiveRecursive( xMutex );
+ *          xSemaphoreGiveRecursive( xMutex );
+ *
+ *          // Now the mutex can be taken by other tasks.
+ *      }
+ *      else
+ *      {
+ *          // We could not obtain the mutex and can therefore not access
+ *          // the shared resource safely.
+ *      }
+ *  }
+ * }
+ * </pre>
+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
+ * \ingroup Semaphores
+ */
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    #define xSemaphoreGiveRecursive( xMutex )    xQueueGiveMutexRecursive( ( xMutex ) )
+#endif
+
+/**
+ * semphr. h
+ * <pre>
+ * xSemaphoreGiveFromISR(
+ *                        SemaphoreHandle_t xSemaphore,
+ *                        BaseType_t *pxHigherPriorityTaskWoken
+ *                    );
+ * </pre>
+ *
+ * <i>Macro</i> to  release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR.
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ * <pre>
+ \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT 10
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ * // Repetitive task.
+ * void vATask( void * pvParameters )
+ * {
+ *  for( ;; )
+ *  {
+ *      // We want this task to run every 10 ticks of a timer.  The semaphore
+ *      // was created before this task was started.
+ *
+ *      // Block waiting for the semaphore to become available.
+ *      if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+ *      {
+ *          // It is time to execute.
+ *
+ *          // ...
+ *
+ *          // We have finished our task.  Return to the top of the loop where
+ *          // we will block on the semaphore until it is time to execute
+ *          // again.  Note when using the semaphore for synchronisation with an
+ *          // ISR in this manner there is no need to 'give' the semaphore back.
+ *      }
+ *  }
+ * }
+ *
+ * // Timer ISR
+ * void vTimerISR( void * pvParameters )
+ * {
+ * static uint8_t ucLocalTickCount = 0;
+ * static BaseType_t xHigherPriorityTaskWoken;
+ *
+ *  // A timer tick has occurred.
+ *
+ *  // ... Do other time functions.
+ *
+ *  // Is it time for vATask () to run?
+ *  xHigherPriorityTaskWoken = pdFALSE;
+ *  ucLocalTickCount++;
+ *  if( ucLocalTickCount >= TICKS_TO_WAIT )
+ *  {
+ *      // Unblock the task by releasing the semaphore.
+ *      xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+ *
+ *      // Reset the count so we release the semaphore again in 10 ticks time.
+ *      ucLocalTickCount = 0;
+ *  }
+ *
+ *  if( xHigherPriorityTaskWoken != pdFALSE )
+ *  {
+ *      // We can force a context switch here.  Context switching from an
+ *      // ISR uses port specific syntax.  Check the demo task for your port
+ *      // to find the syntax required.
+ *  }
+ * }
+ * </pre>
+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )    xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * <pre>
+ * xSemaphoreTakeFromISR(
+ *                        SemaphoreHandle_t xSemaphore,
+ *                        BaseType_t *pxHigherPriorityTaskWoken
+ *                    );
+ * </pre>
+ *
+ * <i>Macro</i> to  take a semaphore from an ISR.  The semaphore must have
+ * previously been created with a call to xSemaphoreCreateBinary() or
+ * xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR, however taking a semaphore from an ISR
+ * is not a common operation.  It is likely to only be useful when taking a
+ * counting semaphore when an interrupt is obtaining an object from a resource
+ * pool (when the semaphore count indicates the number of resources available).
+ *
+ * @param xSemaphore A handle to the semaphore being taken.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully taken, otherwise
+ * pdFALSE
+ */
+#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )    xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * <pre>
+ * SemaphoreHandle_t xSemaphoreCreateMutex( void );
+ * </pre>
+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * semaphore is returned.  If there was not enough heap to allocate the mutex
+ * data structures then NULL is returned.
+ *
+ * Example usage:
+ * <pre>
+ * SemaphoreHandle_t xSemaphore;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+ *  // This is a macro so pass the variable in directly.
+ *  xSemaphore = xSemaphoreCreateMutex();
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ * </pre>
+ * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
+ * \ingroup Semaphores
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    #define xSemaphoreCreateMutex()    xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * <pre>
+ * SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer );
+ * </pre>
+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will be used to hold the mutex's data structure, removing the need for
+ * the memory to be allocated dynamically.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * <pre>
+ * SemaphoreHandle_t xSemaphore;
+ * StaticSemaphore_t xMutexBuffer;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // A mutex cannot be used before it has been created.  xMutexBuffer is
+ *  // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
+ *  // attempted.
+ *  xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
+ *
+ *  // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+ *  // so there is no need to check it.
+ * }
+ * </pre>
+ * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
+ * \ingroup Semaphores
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #define xSemaphoreCreateMutexStatic( pxMutexBuffer )    xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+
+/**
+ * semphr. h
+ * <pre>
+ * SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void );
+ * </pre>
+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
+ * SemaphoreHandle_t.
+ *
+ * Example usage:
+ * <pre>
+ * SemaphoreHandle_t xSemaphore;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+ *  // This is a macro so pass the variable in directly.
+ *  xSemaphore = xSemaphoreCreateRecursiveMutex();
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ * </pre>
+ * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
+ * \ingroup Semaphores
+ */
+#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+    #define xSemaphoreCreateRecursiveMutex()    xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * <pre>
+ * SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer );
+ * </pre>
+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the recursive mutex's data structure,
+ * removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the recursive mutex was successfully created then a handle to the
+ * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
+ * returned.
+ *
+ * Example usage:
+ * <pre>
+ * SemaphoreHandle_t xSemaphore;
+ * StaticSemaphore_t xMutexBuffer;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ *  // A recursive semaphore cannot be used before it is created.  Here a
+ *  // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
+ *  // The address of xMutexBuffer is passed into the function, and will hold
+ *  // the mutexes data structures - so no dynamic memory allocation will be
+ *  // attempted.
+ *  xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
+ *
+ *  // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+ *  // so there is no need to check it.
+ * }
+ * </pre>
+ * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
+ * \ingroup Semaphores
+ */
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+    #define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore )    xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * <pre>
+ * SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount );
+ * </pre>
+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * https://www.FreeRTOS.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer can
+ * instead optionally provide the memory that will get used by the counting
+ * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
+ * semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @return Handle to the created semaphore.  Null if the semaphore could not be
+ *         created.
+ *
+ * Example usage:
+ * <pre>
+ * SemaphoreHandle_t xSemaphore;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ *  // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+ *  // The max value to which the semaphore can count should be 10, and the
+ *  // initial value assigned to the count should be 0.
+ *  xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+ *
+ *  if( xSemaphore != NULL )
+ *  {
+ *      // The semaphore was created successfully.
+ *      // The semaphore can now be used.
+ *  }
+ * }
+ * </pre>
+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
+ * \ingroup Semaphores
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    #define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount )    xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
+#endif
+
+/**
+ * semphr. h
+ * <pre>
+ * SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer );
+ * </pre>
+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * https://www.FreeRTOS.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer must
+ * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
+ * counting semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the counting semaphore was successfully created then a handle to
+ * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
+ * then NULL is returned.
+ *
+ * Example usage:
+ * <pre>
+ * SemaphoreHandle_t xSemaphore;
+ * StaticSemaphore_t xSemaphoreBuffer;
+ *
+ * void vATask( void * pvParameters )
+ * {
+ * SemaphoreHandle_t xSemaphore = NULL;
+ *
+ *  // Counting semaphore cannot be used before they have been created.  Create
+ *  // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
+ *  // value to which the semaphore can count is 10, and the initial value
+ *  // assigned to the count will be 0.  The address of xSemaphoreBuffer is
+ *  // passed in and will be used to hold the semaphore structure, so no dynamic
+ *  // memory allocation will be used.
+ *  xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
+ *
+ *  // No memory allocation was attempted so xSemaphore cannot be NULL, so there
+ *  // is no need to check its value.
+ * }
+ * </pre>
+ * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
+ * \ingroup Semaphores
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    #define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer )    xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * <pre>
+ * void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );
+ * </pre>
+ *
+ * Delete a semaphore.  This function must be used with care.  For example,
+ * do not delete a mutex type semaphore if the mutex is held by a task.
+ *
+ * @param xSemaphore A handle to the semaphore to be deleted.
+ *
+ * \defgroup vSemaphoreDelete vSemaphoreDelete
+ * \ingroup Semaphores
+ */
+#define vSemaphoreDelete( xSemaphore )                   vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * <pre>
+ * TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );
+ * </pre>
+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ * Note: This is a good way of determining if the calling task is the mutex
+ * holder, but not a good way of determining the identity of the mutex holder as
+ * the holder may change between the function exiting and the returned value
+ * being tested.
+ */
+#define xSemaphoreGetMutexHolder( xSemaphore )           xQueueGetMutexHolder( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * <pre>
+ * TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );
+ * </pre>
+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ */
+#define xSemaphoreGetMutexHolderFromISR( xSemaphore )    xQueueGetMutexHolderFromISR( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * <pre>
+ * UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );
+ * </pre>
+ *
+ * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
+ * its current count value.  If the semaphore is a binary semaphore then
+ * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
+ * semaphore is not available.
+ *
+ */
+#define uxSemaphoreGetCount( xSemaphore )                uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
+
+#endif /* SEMAPHORE_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/stack_macros.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/stack_macros.h
new file mode 100644
index 0000000..c8ef4bd
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/stack_macros.h
@@ -0,0 +1,127 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+/* Only the current stack state is to be checked. */
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \
+    {                                                                                                 \
+        /* Is the currently saved stack pointer within the stack limit? */                            \
+        if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )                                     \
+        {                                                                                             \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+        }                                                                                             \
+    }
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if ( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+/* Only the current stack state is to be checked. */
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \
+    {                                                                                                 \
+                                                                                                      \
+        /* Is the currently saved stack pointer within the stack limit? */                            \
+        if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )                                \
+        {                                                                                             \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+        }                                                                                             \
+    }
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                            \
+    {                                                                                                 \
+        const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;                       \
+        const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;                                        \
+                                                                                                      \
+        if( ( pulStack[ 0 ] != ulCheckValue ) ||                                                      \
+            ( pulStack[ 1 ] != ulCheckValue ) ||                                                      \
+            ( pulStack[ 2 ] != ulCheckValue ) ||                                                      \
+            ( pulStack[ 3 ] != ulCheckValue ) )                                                       \
+        {                                                                                             \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName ); \
+        }                                                                                             \
+    }
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+    #define taskCHECK_FOR_STACK_OVERFLOW()                                                                                                \
+    {                                                                                                                                     \
+        int8_t * pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;                                                                  \
+        static const uint8_t ucExpectedStackBytes[] = { tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
+                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
+                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
+                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,   \
+                                                        tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE }; \
+                                                                                                                                          \
+                                                                                                                                          \
+        pcEndOfStack -= sizeof( ucExpectedStackBytes );                                                                                   \
+                                                                                                                                          \
+        /* Has the extremity of the task stack ever been written over? */                                                                 \
+        if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )                     \
+        {                                                                                                                                 \
+            vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );                                     \
+        }                                                                                                                                 \
+    }
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+    #define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/stdint.readme b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/stdint.readme
new file mode 100644
index 0000000..b1bb60e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/stdint.readme
@@ -0,0 +1,52 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef FREERTOS_STDINT
+#define FREERTOS_STDINT
+
+/*******************************************************************************
+ * THIS IS NOT A FULL stdint.h IMPLEMENTATION - It only contains the definitions
+ * necessary to build the FreeRTOS code.  It is provided to allow FreeRTOS to be
+ * built using compilers that do not provide their own stdint.h definition.
+ *
+ * To use this file:
+ *
+ *    1) Copy this file into the directory that contains your FreeRTOSConfig.h
+ *       header file, as that directory will already be in the compiler's include
+ *       path.
+ *
+ *    2) Rename the copied file stdint.h.
+ *
+ */
+
+typedef signed char int8_t;
+typedef unsigned char uint8_t;
+typedef short int16_t;
+typedef unsigned short uint16_t;
+typedef long int32_t;
+typedef unsigned long uint32_t;
+
+#endif /* FREERTOS_STDINT */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/stream_buffer.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/stream_buffer.h
new file mode 100644
index 0000000..89f6dfb
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/stream_buffer.h
@@ -0,0 +1,867 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * Stream buffers are used to send a continuous stream of data from one task or
+ * interrupt to another.  Their implementation is light weight, making them
+ * particularly suited for interrupt to task and core to core communication
+ * scenarios.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section section and set the
+ * receive block time to 0.
+ *
+ */
+
+#ifndef STREAM_BUFFER_H
+#define STREAM_BUFFER_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h must appear in source files before include stream_buffer.h"
+#endif
+
+/* *INDENT-OFF* */
+#if defined( __cplusplus )
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/**
+ * Type by which stream buffers are referenced.  For example, a call to
+ * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
+ * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
+ * etc.
+ */
+struct StreamBufferDef_t;
+typedef struct StreamBufferDef_t * StreamBufferHandle_t;
+
+
+/**
+ * message_buffer.h
+ *
+ * <pre>
+ * StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
+ * </pre>
+ *
+ * Creates a new stream buffer using dynamically allocated memory.  See
+ * xStreamBufferCreateStatic() for a version that uses statically allocated
+ * memory (memory that is allocated at compile time).
+ *
+ * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
+ * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
+ *
+ * @param xBufferSizeBytes The total number of bytes the stream buffer will be
+ * able to hold at any one time.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @return If NULL is returned, then the stream buffer cannot be created
+ * because there is insufficient heap memory available for FreeRTOS to allocate
+ * the stream buffer data structures and storage area.  A non-NULL value being
+ * returned indicates that the stream buffer has been created successfully -
+ * the returned value should be stored as the handle to the created stream
+ * buffer.
+ *
+ * Example use:
+ * <pre>
+ *
+ * void vAFunction( void )
+ * {
+ * StreamBufferHandle_t xStreamBuffer;
+ * const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
+ *
+ *  // Create a stream buffer that can hold 100 bytes.  The memory used to hold
+ *  // both the stream buffer structure and the data in the stream buffer is
+ *  // allocated dynamically.
+ *  xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
+ *
+ *  if( xStreamBuffer == NULL )
+ *  {
+ *      // There was not enough heap memory space available to create the
+ *      // stream buffer.
+ *  }
+ *  else
+ *  {
+ *      // The stream buffer was created successfully and can now be used.
+ *  }
+ * }
+ * </pre>
+ * \defgroup xStreamBufferCreate xStreamBufferCreate
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes )    xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
+
+/**
+ * stream_buffer.h
+ *
+ * <pre>
+ * StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
+ *                                              size_t xTriggerLevelBytes,
+ *                                              uint8_t *pucStreamBufferStorageArea,
+ *                                              StaticStreamBuffer_t *pxStaticStreamBuffer );
+ * </pre>
+ * Creates a new stream buffer using statically allocated memory.  See
+ * xStreamBufferCreate() for a version that uses dynamically allocated memory.
+ *
+ * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
+ * xStreamBufferCreateStatic() to be available.
+ *
+ * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
+ * pucStreamBufferStorageArea parameter.
+ *
+ * @param xTriggerLevelBytes The number of bytes that must be in the stream
+ * buffer before a task that is blocked on the stream buffer to wait for data is
+ * moved out of the blocked state.  For example, if a task is blocked on a read
+ * of an empty stream buffer that has a trigger level of 1 then the task will be
+ * unblocked when a single byte is written to the buffer or the task's block
+ * time expires.  As another example, if a task is blocked on a read of an empty
+ * stream buffer that has a trigger level of 10 then the task will not be
+ * unblocked until the stream buffer contains at least 10 bytes or the task's
+ * block time expires.  If a reading task's block time expires before the
+ * trigger level is reached then the task will still receive however many bytes
+ * are actually available.  Setting a trigger level of 0 will result in a
+ * trigger level of 1 being used.  It is not valid to specify a trigger level
+ * that is greater than the buffer size.
+ *
+ * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
+ * least xBufferSizeBytes + 1 big.  This is the array to which streams are
+ * copied when they are written to the stream buffer.
+ *
+ * @param pxStaticStreamBuffer Must point to a variable of type
+ * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
+ * structure.
+ *
+ * @return If the stream buffer is created successfully then a handle to the
+ * created stream buffer is returned. If either pucStreamBufferStorageArea or
+ * pxStaticstreamBuffer are NULL then NULL is returned.
+ *
+ * Example use:
+ * <pre>
+ *
+ * // Used to dimension the array used to hold the streams.  The available space
+ * // will actually be one less than this, so 999.
+ #define STORAGE_SIZE_BYTES 1000
+ *
+ * // Defines the memory that will actually hold the streams within the stream
+ * // buffer.
+ * static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
+ *
+ * // The variable used to hold the stream buffer structure.
+ * StaticStreamBuffer_t xStreamBufferStruct;
+ *
+ * void MyFunction( void )
+ * {
+ * StreamBufferHandle_t xStreamBuffer;
+ * const size_t xTriggerLevel = 1;
+ *
+ *  xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
+ *                                             xTriggerLevel,
+ *                                             ucBufferStorage,
+ *                                             &xStreamBufferStruct );
+ *
+ *  // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
+ *  // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
+ *  // reference the created stream buffer in other stream buffer API calls.
+ *
+ *  // Other code that uses the stream buffer can go here.
+ * }
+ *
+ * </pre>
+ * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
+ * \ingroup StreamBufferManagement
+ */
+#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) \
+    xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
+
+/**
+ * stream_buffer.h
+ *
+ * <pre>
+ * size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+ *                        const void *pvTxData,
+ *                        size_t xDataLengthBytes,
+ *                        TickType_t xTicksToWait );
+ * </pre>
+ *
+ * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the buffer that holds the bytes to be copied
+ * into the stream buffer.
+ *
+ * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for enough space to become available in the stream
+ * buffer, should the stream buffer contain too little space to hold the
+ * another xDataLengthBytes bytes.  The block time is specified in tick periods,
+ * so the absolute time it represents is dependent on the tick frequency.  The
+ * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
+ * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
+ * cause the task to wait indefinitely (without timing out), provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out
+ * before it can write all xDataLengthBytes into the buffer it will still write
+ * as many bytes as possible.  A task does not use any CPU time when it is in
+ * the blocked state.
+ *
+ * @return The number of bytes written to the stream buffer.  If a task times
+ * out before it can write all xDataLengthBytes into the buffer it will still
+ * write as many bytes as possible.
+ *
+ * Example use:
+ * <pre>
+ * void vAFunction( StreamBufferHandle_t xStreamBuffer )
+ * {
+ * size_t xBytesSent;
+ * uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
+ * char *pcStringToSend = "String to send";
+ * const TickType_t x100ms = pdMS_TO_TICKS( 100 );
+ *
+ *  // Send an array to the stream buffer, blocking for a maximum of 100ms to
+ *  // wait for enough space to be available in the stream buffer.
+ *  xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
+ *
+ *  if( xBytesSent != sizeof( ucArrayToSend ) )
+ *  {
+ *      // The call to xStreamBufferSend() times out before there was enough
+ *      // space in the buffer for the data to be written, but it did
+ *      // successfully write xBytesSent bytes.
+ *  }
+ *
+ *  // Send the string to the stream buffer.  Return immediately if there is not
+ *  // enough space in the buffer.
+ *  xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // The entire string could not be added to the stream buffer because
+ *      // there was not enough free space in the buffer, but xBytesSent bytes
+ *      // were sent.  Could try again to send the remaining bytes.
+ *  }
+ * }
+ * </pre>
+ * \defgroup xStreamBufferSend xStreamBufferSend
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                          const void * pvTxData,
+                          size_t xDataLengthBytes,
+                          TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * <pre>
+ * size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+ *                               const void *pvTxData,
+ *                               size_t xDataLengthBytes,
+ *                               BaseType_t *pxHigherPriorityTaskWoken );
+ * </pre>
+ *
+ * Interrupt safe version of the API function that sends a stream of bytes to
+ * the stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
+ * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
+ * service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which a stream is
+ * being sent.
+ *
+ * @param pvTxData A pointer to the data that is to be copied into the stream
+ * buffer.
+ *
+ * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
+ * into the stream buffer.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for data.  Calling
+ * xStreamBufferSendFromISR() can make data available, and so cause a task that
+ * was waiting for data to leave the Blocked state.  If calling
+ * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently executing task (the
+ * task that was interrupted), then, internally, xStreamBufferSendFromISR()
+ * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
+ * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  This will
+ * ensure that the interrupt returns directly to the highest priority Ready
+ * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
+ * is passed into the function.  See the example code below for an example.
+ *
+ * @return The number of bytes actually written to the stream buffer, which will
+ * be less than xDataLengthBytes if the stream buffer didn't have enough free
+ * space for all the bytes to be written.
+ *
+ * Example use:
+ * <pre>
+ * // A stream buffer that has already been created.
+ * StreamBufferHandle_t xStreamBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * size_t xBytesSent;
+ * char *pcStringToSend = "String to send";
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
+ *
+ *  // Attempt to send the string to the stream buffer.
+ *  xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
+ *                                         ( void * ) pcStringToSend,
+ *                                         strlen( pcStringToSend ),
+ *                                         &xHigherPriorityTaskWoken );
+ *
+ *  if( xBytesSent != strlen( pcStringToSend ) )
+ *  {
+ *      // There was not enough free space in the stream buffer for the entire
+ *      // string to be written, ut xBytesSent bytes were written.
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xStreamBufferSendFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ * </pre>
+ * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+                                 const void * pvTxData,
+                                 size_t xDataLengthBytes,
+                                 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * <pre>
+ * size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+ *                           void *pvRxData,
+ *                           size_t xBufferLengthBytes,
+ *                           TickType_t xTicksToWait );
+ * </pre>
+ *
+ * Receives bytes from a stream buffer.
+ *
+ * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
+ * implementation (so also the message buffer implementation, as message buffers
+ * are built on top of stream buffers) assumes there is only one task or
+ * interrupt that will write to the buffer (the writer), and only one task or
+ * interrupt that will read from the buffer (the reader).  It is safe for the
+ * writer and reader to be different tasks or interrupts, but, unlike other
+ * FreeRTOS objects, it is not safe to have multiple different writers or
+ * multiple different readers.  If there are to be multiple different writers
+ * then the application writer must place each call to a writing API function
+ * (such as xStreamBufferSend()) inside a critical section and set the send
+ * block time to 0.  Likewise, if there are to be multiple different readers
+ * then the application writer must place each call to a reading API function
+ * (such as xStreamBufferReceive()) inside a critical section and set the receive
+ * block time to 0.
+ *
+ * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
+ * xStreamBufferReceiveFromISR() to read from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which bytes are to
+ * be received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes will be
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param xTicksToWait The maximum amount of time the task should remain in the
+ * Blocked state to wait for data to become available if the stream buffer is
+ * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is
+ * zero.  The block time is specified in tick periods, so the absolute time it
+ * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can
+ * be used to convert a time specified in milliseconds into a time specified in
+ * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait
+ * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
+ * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the
+ * Blocked state.
+ *
+ * @return The number of bytes actually read from the stream buffer, which will
+ * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
+ * out before xBufferLengthBytes were available.
+ *
+ * Example use:
+ * <pre>
+ * void vAFunction( StreamBuffer_t xStreamBuffer )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
+ *
+ *  // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
+ *  // Wait in the Blocked state (so not using any CPU processing time) for a
+ *  // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
+ *  // available.
+ *  xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
+ *                                         ( void * ) ucRxData,
+ *                                         sizeof( ucRxData ),
+ *                                         xBlockTime );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // A ucRxData contains another xRecievedBytes bytes of data, which can
+ *      // be processed here....
+ *  }
+ * }
+ * </pre>
+ * \defgroup xStreamBufferReceive xStreamBufferReceive
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                             void * pvRxData,
+                             size_t xBufferLengthBytes,
+                             TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * <pre>
+ * size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+ *                                  void *pvRxData,
+ *                                  size_t xBufferLengthBytes,
+ *                                  BaseType_t *pxHigherPriorityTaskWoken );
+ * </pre>
+ *
+ * An interrupt safe version of the API function that receives bytes from a
+ * stream buffer.
+ *
+ * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
+ * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
+ * interrupt service routine (ISR).
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which a stream
+ * is being received.
+ *
+ * @param pvRxData A pointer to the buffer into which the received bytes are
+ * copied.
+ *
+ * @param xBufferLengthBytes The length of the buffer pointed to by the
+ * pvRxData parameter.  This sets the maximum number of bytes to receive in one
+ * call.  xStreamBufferReceive will return as many bytes as possible up to a
+ * maximum set by xBufferLengthBytes.
+ *
+ * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
+ * have a task blocked on it waiting for space to become available.  Calling
+ * xStreamBufferReceiveFromISR() can make space available, and so cause a task
+ * that is waiting for space to leave the Blocked state.  If calling
+ * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
+ * the unblocked task has a priority higher than the currently executing task
+ * (the task that was interrupted), then, internally,
+ * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
+ * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
+ * context switch should be performed before the interrupt is exited.  That will
+ * ensure the interrupt returns directly to the highest priority Ready state
+ * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
+ * passed into the function.  See the code example below for an example.
+ *
+ * @return The number of bytes read from the stream buffer, if any.
+ *
+ * Example use:
+ * <pre>
+ * // A stream buffer that has already been created.
+ * StreamBuffer_t xStreamBuffer;
+ *
+ * void vAnInterruptServiceRoutine( void )
+ * {
+ * uint8_t ucRxData[ 20 ];
+ * size_t xReceivedBytes;
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
+ *
+ *  // Receive the next stream from the stream buffer.
+ *  xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
+ *                                                ( void * ) ucRxData,
+ *                                                sizeof( ucRxData ),
+ *                                                &xHigherPriorityTaskWoken );
+ *
+ *  if( xReceivedBytes > 0 )
+ *  {
+ *      // ucRxData contains xReceivedBytes read from the stream buffer.
+ *      // Process the stream here....
+ *  }
+ *
+ *  // If xHigherPriorityTaskWoken was set to pdTRUE inside
+ *  // xStreamBufferReceiveFromISR() then a task that has a priority above the
+ *  // priority of the currently executing task was unblocked and a context
+ *  // switch should be performed to ensure the ISR returns to the unblocked
+ *  // task.  In most FreeRTOS ports this is done by simply passing
+ *  // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
+ *  // variables value, and perform the context switch if necessary.  Check the
+ *  // documentation for the port in use for port specific instructions.
+ *  taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ * }
+ * </pre>
+ * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+                                    void * pvRxData,
+                                    size_t xBufferLengthBytes,
+                                    BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * <pre>
+ * void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
+ * </pre>
+ *
+ * Deletes a stream buffer that was previously created using a call to
+ * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
+ * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
+ * then the allocated memory is freed.
+ *
+ * A stream buffer handle must not be used after the stream buffer has been
+ * deleted.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to be deleted.
+ *
+ * \defgroup vStreamBufferDelete vStreamBufferDelete
+ * \ingroup StreamBufferManagement
+ */
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * <pre>
+ * BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
+ * </pre>
+ *
+ * Queries a stream buffer to see if it is full.  A stream buffer is full if it
+ * does not have any free space, and therefore cannot accept any more data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsFull xStreamBufferIsFull
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * <pre>
+ * BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
+ * </pre>
+ *
+ * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
+ * it does not contain any data.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * <pre>
+ * BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
+ * </pre>
+ *
+ * Resets a stream buffer to its initial, empty, state.  Any data that was in
+ * the stream buffer is discarded.  A stream buffer can only be reset if there
+ * are no tasks blocked waiting to either send to or receive from the stream
+ * buffer.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being reset.
+ *
+ * @return If the stream buffer is reset then pdPASS is returned.  If there was
+ * a task blocked waiting to send to or read from the stream buffer then the
+ * stream buffer is not reset and pdFAIL is returned.
+ *
+ * \defgroup xStreamBufferReset xStreamBufferReset
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * <pre>
+ * size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
+ * </pre>
+ *
+ * Queries a stream buffer to see how much free space it contains, which is
+ * equal to the amount of data that can be sent to the stream buffer before it
+ * is full.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be written to the stream buffer before
+ * the stream buffer would be full.
+ *
+ * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * <pre>
+ * size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
+ * </pre>
+ *
+ * Queries a stream buffer to see how much data it contains, which is equal to
+ * the number of bytes that can be read from the stream buffer before the stream
+ * buffer would be empty.
+ *
+ * @param xStreamBuffer The handle of the stream buffer being queried.
+ *
+ * @return The number of bytes that can be read from the stream buffer before
+ * the stream buffer would be empty.
+ *
+ * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
+ * \ingroup StreamBufferManagement
+ */
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * <pre>
+ * BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
+ * </pre>
+ *
+ * A stream buffer's trigger level is the number of bytes that must be in the
+ * stream buffer before a task that is blocked on the stream buffer to
+ * wait for data is moved out of the blocked state.  For example, if a task is
+ * blocked on a read of an empty stream buffer that has a trigger level of 1
+ * then the task will be unblocked when a single byte is written to the buffer
+ * or the task's block time expires.  As another example, if a task is blocked
+ * on a read of an empty stream buffer that has a trigger level of 10 then the
+ * task will not be unblocked until the stream buffer contains at least 10 bytes
+ * or the task's block time expires.  If a reading task's block time expires
+ * before the trigger level is reached then the task will still receive however
+ * many bytes are actually available.  Setting a trigger level of 0 will result
+ * in a trigger level of 1 being used.  It is not valid to specify a trigger
+ * level that is greater than the buffer size.
+ *
+ * A trigger level is set when the stream buffer is created, and can be modified
+ * using xStreamBufferSetTriggerLevel().
+ *
+ * @param xStreamBuffer The handle of the stream buffer being updated.
+ *
+ * @param xTriggerLevel The new trigger level for the stream buffer.
+ *
+ * @return If xTriggerLevel was less than or equal to the stream buffer's length
+ * then the trigger level will be updated and pdTRUE is returned.  Otherwise
+ * pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                         size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * <pre>
+ * BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ * </pre>
+ *
+ * For advanced users only.
+ *
+ * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is sent to a message buffer or stream buffer.  If there was a task that
+ * was blocked on the message or stream buffer waiting for data to arrive then
+ * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
+ * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same
+ * thing.  It is provided to enable application writers to implement their own
+ * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer to which data was
+ * written.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferSendCompletedFromISR().  If calling
+ * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
+                                              BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * stream_buffer.h
+ *
+ * <pre>
+ * BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
+ * </pre>
+ *
+ * For advanced users only.
+ *
+ * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
+ * data is read out of a message buffer or stream buffer.  If there was a task
+ * that was blocked on the message or stream buffer waiting for data to arrive
+ * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
+ * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()
+ * does the same thing.  It is provided to enable application writers to
+ * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
+ * ANY OTHER TIME.
+ *
+ * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
+ * additional information.
+ *
+ * @param xStreamBuffer The handle of the stream buffer from which data was
+ * read.
+ *
+ * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
+ * initialised to pdFALSE before it is passed into
+ * xStreamBufferReceiveCompletedFromISR().  If calling
+ * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
+ * and the task has a priority above the priority of the currently running task,
+ * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
+ * context switch should be performed before exiting the ISR.
+ *
+ * @return If a task was removed from the Blocked state then pdTRUE is returned.
+ * Otherwise pdFALSE is returned.
+ *
+ * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
+ * \ingroup StreamBufferManagement
+ */
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
+                                                 BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/* Functions below here are not part of the public API. */
+StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+                                                 size_t xTriggerLevelBytes,
+                                                 BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
+
+StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+                                                       size_t xTriggerLevelBytes,
+                                                       BaseType_t xIsMessageBuffer,
+                                                       uint8_t * const pucStreamBufferStorageArea,
+                                                       StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+    void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer,
+                                             UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
+    UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+    uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+/* *INDENT-OFF* */
+#if defined( __cplusplus )
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* !defined( STREAM_BUFFER_H ) */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/task.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/task.h
new file mode 100644
index 0000000..66c99c5
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/task.h
@@ -0,0 +1,3053 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef INC_TASK_H
+#define INC_TASK_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h must appear in source files before include task.h"
+#endif
+
+#include "list.h"
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*-----------------------------------------------------------
+* MACROS AND DEFINITIONS
+*----------------------------------------------------------*/
+
+#define tskKERNEL_VERSION_NUMBER       "V10.4.3"
+#define tskKERNEL_VERSION_MAJOR        10
+#define tskKERNEL_VERSION_MINOR        4
+#define tskKERNEL_VERSION_BUILD        3
+
+/* MPU region parameters passed in ulParameters
+ * of MemoryRegion_t struct. */
+#define tskMPU_REGION_READ_ONLY        ( 1UL << 0UL )
+#define tskMPU_REGION_READ_WRITE       ( 1UL << 1UL )
+#define tskMPU_REGION_EXECUTE_NEVER    ( 1UL << 2UL )
+#define tskMPU_REGION_NORMAL_MEMORY    ( 1UL << 3UL )
+#define tskMPU_REGION_DEVICE_MEMORY    ( 1UL << 4UL )
+
+/* The direct to task notification feature used to have only a single notification
+ * per task.  Now there is an array of notifications per task that is dimensioned by
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES.  For backward compatibility, any use of the
+ * original direct to task notification defaults to using the first index in the
+ * array. */
+#define tskDEFAULT_INDEX_TO_NOTIFY     ( 0 )
+
+/**
+ * task. h
+ *
+ * Type by which tasks are referenced.  For example, a call to xTaskCreate
+ * returns (via a pointer parameter) an TaskHandle_t variable that can then
+ * be used as a parameter to vTaskDelete to delete the task.
+ *
+ * \defgroup TaskHandle_t TaskHandle_t
+ * \ingroup Tasks
+ */
+struct tskTaskControlBlock;     /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tskTaskControlBlock * TaskHandle_t;
+
+/*
+ * Defines the prototype to which the application task hook function must
+ * conform.
+ */
+typedef BaseType_t (* TaskHookFunction_t)( void * );
+
+/* Task states returned by eTaskGetState. */
+typedef enum
+{
+    eRunning = 0,     /* A task is querying the state of itself, so must be running. */
+    eReady,           /* The task being queried is in a read or pending ready list. */
+    eBlocked,         /* The task being queried is in the Blocked state. */
+    eSuspended,       /* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
+    eDeleted,         /* The task being queried has been deleted, but its TCB has not yet been freed. */
+    eInvalid          /* Used as an 'invalid state' value. */
+} eTaskState;
+
+/* Actions that can be performed when vTaskNotify() is called. */
+typedef enum
+{
+    eNoAction = 0,                /* Notify the task without updating its notify value. */
+    eSetBits,                     /* Set bits in the task's notification value. */
+    eIncrement,                   /* Increment the task's notification value. */
+    eSetValueWithOverwrite,       /* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
+    eSetValueWithoutOverwrite     /* Set the task's notification value if the previous value has been read by the task. */
+} eNotifyAction;
+
+/*
+ * Used internally only.
+ */
+typedef struct xTIME_OUT
+{
+    BaseType_t xOverflowCount;
+    TickType_t xTimeOnEntering;
+} TimeOut_t;
+
+/*
+ * Defines the memory ranges allocated to the task when an MPU is used.
+ */
+typedef struct xMEMORY_REGION
+{
+    void * pvBaseAddress;
+    uint32_t ulLengthInBytes;
+    uint32_t ulParameters;
+} MemoryRegion_t;
+
+/*
+ * Parameters required to create an MPU protected task.
+ */
+typedef struct xTASK_PARAMETERS
+{
+    TaskFunction_t pvTaskCode;
+    const char * pcName;     /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    configSTACK_DEPTH_TYPE usStackDepth;
+    void * pvParameters;
+    UBaseType_t uxPriority;
+    StackType_t * puxStackBuffer;
+    MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
+    #if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+        StaticTask_t * const pxTaskBuffer;
+    #endif
+} TaskParameters_t;
+
+/* Used with the uxTaskGetSystemState() function to return the state of each task
+ * in the system. */
+typedef struct xTASK_STATUS
+{
+    TaskHandle_t xHandle;                            /* The handle of the task to which the rest of the information in the structure relates. */
+    const char * pcTaskName;                         /* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    UBaseType_t xTaskNumber;                         /* A number unique to the task. */
+    eTaskState eCurrentState;                        /* The state in which the task existed when the structure was populated. */
+    UBaseType_t uxCurrentPriority;                   /* The priority at which the task was running (may be inherited) when the structure was populated. */
+    UBaseType_t uxBasePriority;                      /* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
+    uint32_t ulRunTimeCounter;                       /* The total run time allocated to the task so far, as defined by the run time stats clock.  See https://www.FreeRTOS.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
+    StackType_t * pxStackBase;                       /* Points to the lowest address of the task's stack area. */
+    configSTACK_DEPTH_TYPE usStackHighWaterMark;     /* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
+} TaskStatus_t;
+
+/* Possible return values for eTaskConfirmSleepModeStatus(). */
+typedef enum
+{
+    eAbortSleep = 0,           /* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+    eStandardSleep,            /* Enter a sleep mode that will not last any longer than the expected idle time. */
+    eNoTasksWaitingTimeout     /* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
+} eSleepModeStatus;
+
+/**
+ * Defines the priority used by the idle task.  This must not be modified.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskIDLE_PRIORITY    ( ( UBaseType_t ) 0U )
+
+/**
+ * task. h
+ *
+ * Macro for forcing a context switch.
+ *
+ * \defgroup taskYIELD taskYIELD
+ * \ingroup SchedulerControl
+ */
+#define taskYIELD()                        portYIELD()
+
+/**
+ * task. h
+ *
+ * Macro to mark the start of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskENTER_CRITICAL()               portENTER_CRITICAL()
+#define taskENTER_CRITICAL_FROM_ISR()      portSET_INTERRUPT_MASK_FROM_ISR()
+
+/**
+ * task. h
+ *
+ * Macro to mark the end of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskEXIT_CRITICAL()                portEXIT_CRITICAL()
+#define taskEXIT_CRITICAL_FROM_ISR( x )    portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+
+/**
+ * task. h
+ *
+ * Macro to disable all maskable interrupts.
+ *
+ * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskDISABLE_INTERRUPTS()           portDISABLE_INTERRUPTS()
+
+/**
+ * task. h
+ *
+ * Macro to enable microcontroller interrupts.
+ *
+ * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskENABLE_INTERRUPTS()            portENABLE_INTERRUPTS()
+
+/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
+ * 0 to generate more optimal code when configASSERT() is defined as the constant
+ * is used in assert() statements. */
+#define taskSCHEDULER_SUSPENDED      ( ( BaseType_t ) 0 )
+#define taskSCHEDULER_NOT_STARTED    ( ( BaseType_t ) 1 )
+#define taskSCHEDULER_RUNNING        ( ( BaseType_t ) 2 )
+
+
+/*-----------------------------------------------------------
+* TASK CREATION API
+*----------------------------------------------------------*/
+
+/**
+ * task. h
+ * <pre>
+ * BaseType_t xTaskCreate(
+ *                            TaskFunction_t pvTaskCode,
+ *                            const char * const pcName,
+ *                            configSTACK_DEPTH_TYPE usStackDepth,
+ *                            void *pvParameters,
+ *                            UBaseType_t uxPriority,
+ *                            TaskHandle_t *pvCreatedTask
+ *                        );
+ * </pre>
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * See xTaskCreateStatic() for a version that does not use any dynamic memory
+ * allocation.
+ *
+ * xTaskCreate() can only be used to create a task that has unrestricted
+ * access to the entire microcontroller memory map.  Systems that include MPU
+ * support can alternatively create an MPU constrained task using
+ * xTaskCreateRestricted().
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
+ * is 16.
+ *
+ * @param usStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task should run.  Systems that
+ * include MPU support can optionally create tasks in a privileged (system)
+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
+ * example, to create a privileged task at priority 2 the uxPriority parameter
+ * should be set to ( 2 | portPRIVILEGE_BIT ).
+ *
+ * @param pvCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+ * <pre>
+ * // Task to be created.
+ * void vTaskCode( void * pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *       // Task code goes here.
+ *   }
+ * }
+ *
+ * // Function that creates a task.
+ * void vOtherFunction( void )
+ * {
+ * static uint8_t ucParameterToPass;
+ * TaskHandle_t xHandle = NULL;
+ *
+ *   // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
+ *   // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
+ *   // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+ *   // the new task attempts to access it.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+ *   configASSERT( xHandle );
+ *
+ *   // Use the handle to delete the task.
+ *   if( xHandle != NULL )
+ *   {
+ *      vTaskDelete( xHandle );
+ *   }
+ * }
+ * </pre>
+ * \defgroup xTaskCreate xTaskCreate
+ * \ingroup Tasks
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
+                            const char * const pcName,     /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                            const configSTACK_DEPTH_TYPE usStackDepth,
+                            void * const pvParameters,
+                            UBaseType_t uxPriority,
+                            TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * <pre>
+ * TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
+ *                               const char * const pcName,
+ *                               uint32_t ulStackDepth,
+ *                               void *pvParameters,
+ *                               UBaseType_t uxPriority,
+ *                               StackType_t *pxStackBuffer,
+ *                               StaticTask_t *pxTaskBuffer );
+ * </pre>
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  The maximum length of the string is defined by
+ * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
+ *
+ * @param ulStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task will run.
+ *
+ * @param pxStackBuffer Must point to a StackType_t array that has at least
+ * ulStackDepth indexes - the array will then be used as the task's stack,
+ * removing the need for the stack to be allocated dynamically.
+ *
+ * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
+ * then be used to hold the task's data structures, removing the need for the
+ * memory to be allocated dynamically.
+ *
+ * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
+ * be created and a handle to the created task is returned.  If either
+ * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and
+ * NULL is returned.
+ *
+ * Example usage:
+ * <pre>
+ *
+ *  // Dimensions the buffer that the task being created will use as its stack.
+ *  // NOTE:  This is the number of words the stack will hold, not the number of
+ *  // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
+ *  // then 400 bytes (100 * 32-bits) will be allocated.
+ #define STACK_SIZE 200
+ *
+ *  // Structure that will hold the TCB of the task being created.
+ *  StaticTask_t xTaskBuffer;
+ *
+ *  // Buffer that the task being created will use as its stack.  Note this is
+ *  // an array of StackType_t variables.  The size of StackType_t is dependent on
+ *  // the RTOS port.
+ *  StackType_t xStack[ STACK_SIZE ];
+ *
+ *  // Function that implements the task being created.
+ *  void vTaskCode( void * pvParameters )
+ *  {
+ *      // The parameter value is expected to be 1 as 1 is passed in the
+ *      // pvParameters value in the call to xTaskCreateStatic().
+ *      configASSERT( ( uint32_t ) pvParameters == 1UL );
+ *
+ *      for( ;; )
+ *      {
+ *          // Task code goes here.
+ *      }
+ *  }
+ *
+ *  // Function that creates a task.
+ *  void vOtherFunction( void )
+ *  {
+ *      TaskHandle_t xHandle = NULL;
+ *
+ *      // Create the task without using any dynamic memory allocation.
+ *      xHandle = xTaskCreateStatic(
+ *                    vTaskCode,       // Function that implements the task.
+ *                    "NAME",          // Text name for the task.
+ *                    STACK_SIZE,      // Stack size in words, not bytes.
+ *                    ( void * ) 1,    // Parameter passed into the task.
+ *                    tskIDLE_PRIORITY,// Priority at which the task is created.
+ *                    xStack,          // Array to use as the task's stack.
+ *                    &xTaskBuffer );  // Variable to hold the task's data structure.
+ *
+ *      // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
+ *      // been created, and xHandle will be the task's handle.  Use the handle
+ *      // to suspend the task.
+ *      vTaskSuspend( xHandle );
+ *  }
+ * </pre>
+ * \defgroup xTaskCreateStatic xTaskCreateStatic
+ * \ingroup Tasks
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
+                                    const char * const pcName,     /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                    const uint32_t ulStackDepth,
+                                    void * const pvParameters,
+                                    UBaseType_t uxPriority,
+                                    StackType_t * const puxStackBuffer,
+                                    StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * task. h
+ * <pre>
+ * BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
+ * </pre>
+ *
+ * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestricted() should only be used in systems that include an MPU
+ * implementation.
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ * The function parameters define the memory regions and associated access
+ * permissions allocated to the task.
+ *
+ * See xTaskCreateRestrictedStatic() for a version that does not use any
+ * dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+ * <pre>
+ * // Create an TaskParameters_t structure that defines the task to be created.
+ * static const TaskParameters_t xCheckTaskParameters =
+ * {
+ *  vATask,     // pvTaskCode - the function that implements the task.
+ *  "ATask",    // pcName - just a text name for the task to assist debugging.
+ *  100,        // usStackDepth - the stack size DEFINED IN WORDS.
+ *  NULL,       // pvParameters - passed into the task function as the function parameters.
+ *  ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+ *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+ *
+ *  // xRegions - Allocate up to three separate memory regions for access by
+ *  // the task, with appropriate access permissions.  Different processors have
+ *  // different memory alignment requirements - refer to the FreeRTOS documentation
+ *  // for full information.
+ *  {
+ *      // Base address                 Length  Parameters
+ *      { cReadWriteArray,              32,     portMPU_REGION_READ_WRITE },
+ *      { cReadOnlyArray,               32,     portMPU_REGION_READ_ONLY },
+ *      { cPrivilegedOnlyAccessArray,   128,    portMPU_REGION_PRIVILEGED_READ_WRITE }
+ *  }
+ * };
+ *
+ * int main( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *  // Create a task from the const structure defined above.  The task handle
+ *  // is requested (the second parameter is not NULL) but in this case just for
+ *  // demonstration purposes as its not actually used.
+ *  xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+ *
+ *  // Start the scheduler.
+ *  vTaskStartScheduler();
+ *
+ *  // Will only get here if there was insufficient memory to create the idle
+ *  // and/or timer task.
+ *  for( ;; );
+ * }
+ * </pre>
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+#if ( portUSING_MPU_WRAPPERS == 1 )
+    BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
+                                      TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * <pre>
+ * BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );
+ * </pre>
+ *
+ * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
+ *
+ * xTaskCreateRestrictedStatic() should only be used in systems that include an
+ * MPU implementation.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreateRestricted() then the stack is provided by the application writer,
+ * and the memory used to hold the task's data structure is automatically
+ * dynamically allocated inside the xTaskCreateRestricted() function.  If a task
+ * is created using xTaskCreateRestrictedStatic() then the application writer
+ * must provide the memory used to hold the task's data structures too.
+ * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
+ * created without using any dynamic memory allocation.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
+ * contains an additional member, which is used to point to a variable of type
+ * StaticTask_t - which is then used to hold the task's data structure.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+ * <pre>
+ * // Create an TaskParameters_t structure that defines the task to be created.
+ * // The StaticTask_t variable is only included in the structure when
+ * // configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
+ * // be used to force the variable into the RTOS kernel's privileged data area.
+ * static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
+ * static const TaskParameters_t xCheckTaskParameters =
+ * {
+ *  vATask,     // pvTaskCode - the function that implements the task.
+ *  "ATask",    // pcName - just a text name for the task to assist debugging.
+ *  100,        // usStackDepth - the stack size DEFINED IN WORDS.
+ *  NULL,       // pvParameters - passed into the task function as the function parameters.
+ *  ( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+ *  cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+ *
+ *  // xRegions - Allocate up to three separate memory regions for access by
+ *  // the task, with appropriate access permissions.  Different processors have
+ *  // different memory alignment requirements - refer to the FreeRTOS documentation
+ *  // for full information.
+ *  {
+ *      // Base address                 Length  Parameters
+ *      { cReadWriteArray,              32,     portMPU_REGION_READ_WRITE },
+ *      { cReadOnlyArray,               32,     portMPU_REGION_READ_ONLY },
+ *      { cPrivilegedOnlyAccessArray,   128,    portMPU_REGION_PRIVILEGED_READ_WRITE }
+ *  }
+ *
+ *  &xTaskBuffer; // Holds the task's data structure.
+ * };
+ *
+ * int main( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *  // Create a task from the const structure defined above.  The task handle
+ *  // is requested (the second parameter is not NULL) but in this case just for
+ *  // demonstration purposes as its not actually used.
+ *  xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+ *
+ *  // Start the scheduler.
+ *  vTaskStartScheduler();
+ *
+ *  // Will only get here if there was insufficient memory to create the idle
+ *  // and/or timer task.
+ *  for( ;; );
+ * }
+ * </pre>
+ * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
+ * \ingroup Tasks
+ */
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+    BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
+                                            TaskHandle_t * pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ * <pre>
+ * void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
+ * </pre>
+ *
+ * Memory regions are assigned to a restricted task when the task is created by
+ * a call to xTaskCreateRestricted().  These regions can be redefined using
+ * vTaskAllocateMPURegions().
+ *
+ * @param xTask The handle of the task being updated.
+ *
+ * @param xRegions A pointer to an MemoryRegion_t structure that contains the
+ * new memory region definitions.
+ *
+ * Example usage:
+ * <pre>
+ * // Define an array of MemoryRegion_t structures that configures an MPU region
+ * // allowing read/write access for 1024 bytes starting at the beginning of the
+ * // ucOneKByte array.  The other two of the maximum 3 definable regions are
+ * // unused so set to zero.
+ * static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+ * {
+ *  // Base address     Length      Parameters
+ *  { ucOneKByte,       1024,       portMPU_REGION_READ_WRITE },
+ *  { 0,                0,          0 },
+ *  { 0,                0,          0 }
+ * };
+ *
+ * void vATask( void *pvParameters )
+ * {
+ *  // This task was created such that it has access to certain regions of
+ *  // memory as defined by the MPU configuration.  At some point it is
+ *  // desired that these MPU regions are replaced with that defined in the
+ *  // xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
+ *  // for this purpose.  NULL is used as the task handle to indicate that this
+ *  // function should modify the MPU regions of the calling task.
+ *  vTaskAllocateMPURegions( NULL, xAltRegions );
+ *
+ *  // Now the task can continue its function, but from this point on can only
+ *  // access its stack and the ucOneKByte array (unless any other statically
+ *  // defined or shared regions have been declared elsewhere).
+ * }
+ * </pre>
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+void vTaskAllocateMPURegions( TaskHandle_t xTask,
+                              const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>
+ * void vTaskDelete( TaskHandle_t xTask );
+ * </pre>
+ *
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Remove a task from the RTOS real time kernel's management.  The task being
+ * deleted will be removed from all ready, blocked, suspended and event lists.
+ *
+ * NOTE:  The idle task is responsible for freeing the kernel allocated
+ * memory from tasks that have been deleted.  It is therefore important that
+ * the idle task is not starved of microcontroller processing time if your
+ * application makes any calls to vTaskDelete ().  Memory allocated by the
+ * task code is not automatically freed, and should be freed before the task
+ * is deleted.
+ *
+ * See the demo application file death.c for sample code that utilises
+ * vTaskDelete ().
+ *
+ * @param xTask The handle of the task to be deleted.  Passing NULL will
+ * cause the calling task to be deleted.
+ *
+ * Example usage:
+ * <pre>
+ * void vOtherFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create the task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // Use the handle to delete the task.
+ *   vTaskDelete( xHandle );
+ * }
+ * </pre>
+ * \defgroup vTaskDelete vTaskDelete
+ * \ingroup Tasks
+ */
+void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+* TASK CONTROL API
+*----------------------------------------------------------*/
+
+/**
+ * task. h
+ * <pre>
+ * void vTaskDelay( const TickType_t xTicksToDelay );
+ * </pre>
+ *
+ * Delay a task for a given number of ticks.  The actual time that the
+ * task remains blocked depends on the tick rate.  The constant
+ * portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ *
+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to
+ * the time at which vTaskDelay() is called.  For example, specifying a block
+ * period of 100 ticks will cause the task to unblock 100 ticks after
+ * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
+ * of controlling the frequency of a periodic task as the path taken through the
+ * code, as well as other task and interrupt activity, will effect the frequency
+ * at which vTaskDelay() gets called and therefore the time at which the task
+ * next executes.  See xTaskDelayUntil() for an alternative API function designed
+ * to facilitate fixed frequency execution.  It does this by specifying an
+ * absolute time (rather than a relative time) at which the calling task should
+ * unblock.
+ *
+ * @param xTicksToDelay The amount of time, in tick periods, that
+ * the calling task should block.
+ *
+ * Example usage:
+ *
+ * void vTaskFunction( void * pvParameters )
+ * {
+ * // Block for 500ms.
+ * const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
+ *
+ *   for( ;; )
+ *   {
+ *       // Simply toggle the LED every 500ms, blocking between each toggle.
+ *       vToggleLED();
+ *       vTaskDelay( xDelay );
+ *   }
+ * }
+ *
+ * \defgroup vTaskDelay vTaskDelay
+ * \ingroup TaskCtrl
+ */
+void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>
+ * BaseType_t xTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );
+ * </pre>
+ *
+ * INCLUDE_xTaskDelayUntil must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Delay a task until a specified time.  This function can be used by periodic
+ * tasks to ensure a constant execution frequency.
+ *
+ * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is
+ * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
+ * execution frequency as the time between a task starting to execute and that task
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the
+ * code between calls, or may get interrupted or preempted a different number of times
+ * each time it executes].
+ *
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
+ * is called, xTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
+ * unblock.
+ *
+ * The macro pdMS_TO_TICKS() can be used to calculate the number of ticks from a
+ * time specified in milliseconds with a resolution of one tick period.
+ *
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
+ * task was last unblocked.  The variable must be initialised with the current time
+ * prior to its first use (see the example below).  Following this the variable is
+ * automatically updated within xTaskDelayUntil ().
+ *
+ * @param xTimeIncrement The cycle time period.  The task will be unblocked at
+ * time *pxPreviousWakeTime + xTimeIncrement.  Calling xTaskDelayUntil with the
+ * same xTimeIncrement parameter value will cause the task to execute with
+ * a fixed interface period.
+ *
+ * @return Value which can be used to check whether the task was actually delayed.
+ * Will be pdTRUE if the task way delayed and pdFALSE otherwise.  A task will not
+ * be delayed if the next expected wake time is in the past.
+ *
+ * Example usage:
+ * <pre>
+ * // Perform an action every 10 ticks.
+ * void vTaskFunction( void * pvParameters )
+ * {
+ * TickType_t xLastWakeTime;
+ * const TickType_t xFrequency = 10;
+ * BaseType_t xWasDelayed;
+ *
+ *     // Initialise the xLastWakeTime variable with the current time.
+ *     xLastWakeTime = xTaskGetTickCount ();
+ *     for( ;; )
+ *     {
+ *         // Wait for the next cycle.
+ *         xWasDelayed = xTaskDelayUntil( &xLastWakeTime, xFrequency );
+ *
+ *         // Perform action here. xWasDelayed value can be used to determine
+ *         // whether a deadline was missed if the code here took too long.
+ *     }
+ * }
+ * </pre>
+ * \defgroup xTaskDelayUntil xTaskDelayUntil
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                            const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
+
+/*
+ * vTaskDelayUntil() is the older version of xTaskDelayUntil() and does not
+ * return a value.
+ */
+#define vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement )       \
+{                                                                   \
+    ( void ) xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement ); \
+}
+
+
+/**
+ * task. h
+ * <pre>
+ * BaseType_t xTaskAbortDelay( TaskHandle_t xTask );
+ * </pre>
+ *
+ * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
+ * function to be available.
+ *
+ * A task will enter the Blocked state when it is waiting for an event.  The
+ * event it is waiting for can be a temporal event (waiting for a time), such
+ * as when vTaskDelay() is called, or an event on an object, such as when
+ * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task
+ * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
+ * task will leave the Blocked state, and return from whichever function call
+ * placed the task into the Blocked state.
+ *
+ * There is no 'FromISR' version of this function as an interrupt would need to
+ * know which object a task was blocked on in order to know which actions to
+ * take.  For example, if the task was blocked on a queue the interrupt handler
+ * would then need to know if the queue was locked.
+ *
+ * @param xTask The handle of the task to remove from the Blocked state.
+ *
+ * @return If the task referenced by xTask was not in the Blocked state then
+ * pdFAIL is returned.  Otherwise pdPASS is returned.
+ *
+ * \defgroup xTaskAbortDelay xTaskAbortDelay
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>
+ * UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );
+ * </pre>
+ *
+ * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the priority of any task.
+ *
+ * @param xTask Handle of the task to be queried.  Passing a NULL
+ * handle results in the priority of the calling task being returned.
+ *
+ * @return The priority of xTask.
+ *
+ * Example usage:
+ * <pre>
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create a task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // ...
+ *
+ *   // Use the handle to obtain the priority of the created task.
+ *   // It was created with tskIDLE_PRIORITY, but may have changed
+ *   // it itself.
+ *   if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+ *   {
+ *       // The task has changed it's priority.
+ *   }
+ *
+ *   // ...
+ *
+ *   // Is our priority higher than the created task?
+ *   if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+ *   {
+ *       // Our priority (obtained using NULL handle) is higher.
+ *   }
+ * }
+ * </pre>
+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>
+ * UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );
+ * </pre>
+ *
+ * A version of uxTaskPriorityGet() that can be used from an ISR.
+ */
+UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>
+ * eTaskState eTaskGetState( TaskHandle_t xTask );
+ * </pre>
+ *
+ * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the state of any task.  States are encoded by the eTaskState
+ * enumerated type.
+ *
+ * @param xTask Handle of the task to be queried.
+ *
+ * @return The state of xTask at the time the function was called.  Note the
+ * state of the task might change between the function being called, and the
+ * functions return value being tested by the calling task.
+ */
+eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>
+ * void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );
+ * </pre>
+ *
+ * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * Populates a TaskStatus_t structure with information about a task.
+ *
+ * @param xTask Handle of the task being queried.  If xTask is NULL then
+ * information will be returned about the calling task.
+ *
+ * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
+ * filled with information about the task referenced by the handle passed using
+ * the xTask parameter.
+ *
+ * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report
+ * the stack high water mark of the task being queried.  Calculating the stack
+ * high water mark takes a relatively long time, and can make the system
+ * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
+ * allow the high water mark checking to be skipped.  The high watermark value
+ * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
+ * not set to pdFALSE;
+ *
+ * @param eState The TaskStatus_t structure contains a member to report the
+ * state of the task being queried.  Obtaining the task state is not as fast as
+ * a simple assignment - so the eState parameter is provided to allow the state
+ * information to be omitted from the TaskStatus_t structure.  To obtain state
+ * information then set eState to eInvalid - otherwise the value passed in
+ * eState will be reported as the task state in the TaskStatus_t structure.
+ *
+ * Example usage:
+ * <pre>
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ * TaskStatus_t xTaskDetails;
+ *
+ *  // Obtain the handle of a task from its name.
+ *  xHandle = xTaskGetHandle( "Task_Name" );
+ *
+ *  // Check the handle is not NULL.
+ *  configASSERT( xHandle );
+ *
+ *  // Use the handle to obtain further information about the task.
+ *  vTaskGetInfo( xHandle,
+ *                &xTaskDetails,
+ *                pdTRUE, // Include the high water mark in xTaskDetails.
+ *                eInvalid ); // Include the task state in xTaskDetails.
+ * }
+ * </pre>
+ * \defgroup vTaskGetInfo vTaskGetInfo
+ * \ingroup TaskCtrl
+ */
+void vTaskGetInfo( TaskHandle_t xTask,
+                   TaskStatus_t * pxTaskStatus,
+                   BaseType_t xGetFreeStackSpace,
+                   eTaskState eState ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>
+ * void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
+ * </pre>
+ *
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Set the priority of any task.
+ *
+ * A context switch will occur before the function returns if the priority
+ * being set is higher than the currently executing task.
+ *
+ * @param xTask Handle to the task for which the priority is being set.
+ * Passing a NULL handle results in the priority of the calling task being set.
+ *
+ * @param uxNewPriority The priority to which the task will be set.
+ *
+ * Example usage:
+ * <pre>
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create a task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // ...
+ *
+ *   // Use the handle to raise the priority of the created task.
+ *   vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+ *
+ *   // ...
+ *
+ *   // Use a NULL handle to raise our priority to the same value.
+ *   vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ * }
+ * </pre>
+ * \defgroup vTaskPrioritySet vTaskPrioritySet
+ * \ingroup TaskCtrl
+ */
+void vTaskPrioritySet( TaskHandle_t xTask,
+                       UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>
+ * void vTaskSuspend( TaskHandle_t xTaskToSuspend );
+ * </pre>
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Suspend any task.  When suspended a task will never get any microcontroller
+ * processing time, no matter what its priority.
+ *
+ * Calls to vTaskSuspend are not accumulative -
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one
+ * call to vTaskResume () to ready the suspended task.
+ *
+ * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
+ * handle will cause the calling task to be suspended.
+ *
+ * Example usage:
+ * <pre>
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create a task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // ...
+ *
+ *   // Use the handle to suspend the created task.
+ *   vTaskSuspend( xHandle );
+ *
+ *   // ...
+ *
+ *   // The created task will not run during this period, unless
+ *   // another task calls vTaskResume( xHandle ).
+ *
+ *   //...
+ *
+ *
+ *   // Suspend ourselves.
+ *   vTaskSuspend( NULL );
+ *
+ *   // We cannot get here unless another task calls vTaskResume
+ *   // with our handle as the parameter.
+ * }
+ * </pre>
+ * \defgroup vTaskSuspend vTaskSuspend
+ * \ingroup TaskCtrl
+ */
+void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>
+ * void vTaskResume( TaskHandle_t xTaskToResume );
+ * </pre>
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Resumes a suspended task.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * vTaskResume ().
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * Example usage:
+ * <pre>
+ * void vAFunction( void )
+ * {
+ * TaskHandle_t xHandle;
+ *
+ *   // Create a task, storing the handle.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+ *
+ *   // ...
+ *
+ *   // Use the handle to suspend the created task.
+ *   vTaskSuspend( xHandle );
+ *
+ *   // ...
+ *
+ *   // The created task will not run during this period, unless
+ *   // another task calls vTaskResume( xHandle ).
+ *
+ *   //...
+ *
+ *
+ *   // Resume the suspended task ourselves.
+ *   vTaskResume( xHandle );
+ *
+ *   // The created task will once again get microcontroller processing
+ *   // time in accordance with its priority within the system.
+ * }
+ * </pre>
+ * \defgroup vTaskResume vTaskResume
+ * \ingroup TaskCtrl
+ */
+void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>
+ * void xTaskResumeFromISR( TaskHandle_t xTaskToResume );
+ * </pre>
+ *
+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * An implementation of vTaskResume() that can be called from within an ISR.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * xTaskResumeFromISR ().
+ *
+ * xTaskResumeFromISR() should not be used to synchronise a task with an
+ * interrupt if there is a chance that the interrupt could arrive prior to the
+ * task being suspended - as this can lead to interrupts being missed. Use of a
+ * semaphore as a synchronisation mechanism would avoid this eventuality.
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * @return pdTRUE if resuming the task should result in a context switch,
+ * otherwise pdFALSE. This is used by the ISR to determine if a context switch
+ * may be required following the ISR.
+ *
+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+* SCHEDULER CONTROL
+*----------------------------------------------------------*/
+
+/**
+ * task. h
+ * <pre>
+ * void vTaskStartScheduler( void );
+ * </pre>
+ *
+ * Starts the real time kernel tick processing.  After calling the kernel
+ * has control over which tasks are executed and when.
+ *
+ * See the demo application file main.c for an example of creating
+ * tasks and starting the kernel.
+ *
+ * Example usage:
+ * <pre>
+ * void vAFunction( void )
+ * {
+ *   // Create at least one task before starting the kernel.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ *
+ *   // Start the real time kernel with preemption.
+ *   vTaskStartScheduler ();
+ *
+ *   // Will not get here unless a task calls vTaskEndScheduler ()
+ * }
+ * </pre>
+ *
+ * \defgroup vTaskStartScheduler vTaskStartScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>
+ * void vTaskEndScheduler( void );
+ * </pre>
+ *
+ * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC
+ * in place of DOS, implements this function.
+ *
+ * Stops the real time kernel tick.  All created tasks will be automatically
+ * deleted and multitasking (either preemptive or cooperative) will
+ * stop.  Execution then resumes from the point where vTaskStartScheduler ()
+ * was called, as if vTaskStartScheduler () had just returned.
+ *
+ * See the demo application file main. c in the demo/PC directory for an
+ * example that uses vTaskEndScheduler ().
+ *
+ * vTaskEndScheduler () requires an exit function to be defined within the
+ * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
+ * performs hardware specific operations such as stopping the kernel tick.
+ *
+ * vTaskEndScheduler () will cause all of the resources allocated by the
+ * kernel to be freed - but will not free resources allocated by application
+ * tasks.
+ *
+ * Example usage:
+ * <pre>
+ * void vTaskCode( void * pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *       // Task code goes here.
+ *
+ *       // At some point we want to end the real time kernel processing
+ *       // so call ...
+ *       vTaskEndScheduler ();
+ *   }
+ * }
+ *
+ * void vAFunction( void )
+ * {
+ *   // Create at least one task before starting the kernel.
+ *   xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+ *
+ *   // Start the real time kernel with preemption.
+ *   vTaskStartScheduler ();
+ *
+ *   // Will only get here when the vTaskCode () task has called
+ *   // vTaskEndScheduler ().  When we get here we are back to single task
+ *   // execution.
+ * }
+ * </pre>
+ *
+ * \defgroup vTaskEndScheduler vTaskEndScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>
+ * void vTaskSuspendAll( void );
+ * </pre>
+ *
+ * Suspends the scheduler without disabling interrupts.  Context switches will
+ * not occur while the scheduler is suspended.
+ *
+ * After calling vTaskSuspendAll () the calling task will continue to execute
+ * without risk of being swapped out until a call to xTaskResumeAll () has been
+ * made.
+ *
+ * API functions that have the potential to cause a context switch (for example,
+ * xTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
+ * is suspended.
+ *
+ * Example usage:
+ * <pre>
+ * void vTask1( void * pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *       // Task code goes here.
+ *
+ *       // ...
+ *
+ *       // At some point the task wants to perform a long operation during
+ *       // which it does not want to get swapped out.  It cannot use
+ *       // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+ *       // operation may cause interrupts to be missed - including the
+ *       // ticks.
+ *
+ *       // Prevent the real time kernel swapping out the task.
+ *       vTaskSuspendAll ();
+ *
+ *       // Perform the operation here.  There is no need to use critical
+ *       // sections as we have all the microcontroller processing time.
+ *       // During this time interrupts will still operate and the kernel
+ *       // tick count will be maintained.
+ *
+ *       // ...
+ *
+ *       // The operation is complete.  Restart the kernel.
+ *       xTaskResumeAll ();
+ *   }
+ * }
+ * </pre>
+ * \defgroup vTaskSuspendAll vTaskSuspendAll
+ * \ingroup SchedulerControl
+ */
+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>
+ * BaseType_t xTaskResumeAll( void );
+ * </pre>
+ *
+ * Resumes scheduler activity after it was suspended by a call to
+ * vTaskSuspendAll().
+ *
+ * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
+ * that were previously suspended by a call to vTaskSuspend().
+ *
+ * @return If resuming the scheduler caused a context switch then pdTRUE is
+ *         returned, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * <pre>
+ * void vTask1( void * pvParameters )
+ * {
+ *   for( ;; )
+ *   {
+ *       // Task code goes here.
+ *
+ *       // ...
+ *
+ *       // At some point the task wants to perform a long operation during
+ *       // which it does not want to get swapped out.  It cannot use
+ *       // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+ *       // operation may cause interrupts to be missed - including the
+ *       // ticks.
+ *
+ *       // Prevent the real time kernel swapping out the task.
+ *       vTaskSuspendAll ();
+ *
+ *       // Perform the operation here.  There is no need to use critical
+ *       // sections as we have all the microcontroller processing time.
+ *       // During this time interrupts will still operate and the real
+ *       // time kernel tick count will be maintained.
+ *
+ *       // ...
+ *
+ *       // The operation is complete.  Restart the kernel.  We want to force
+ *       // a context switch - but there is no point if resuming the scheduler
+ *       // caused a context switch already.
+ *       if( !xTaskResumeAll () )
+ *       {
+ *            taskYIELD ();
+ *       }
+ *   }
+ * }
+ * </pre>
+ * \defgroup xTaskResumeAll xTaskResumeAll
+ * \ingroup SchedulerControl
+ */
+BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+* TASK UTILITIES
+*----------------------------------------------------------*/
+
+/**
+ * task. h
+ * <PRE>TickType_t xTaskGetTickCount( void );</PRE>
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * \defgroup xTaskGetTickCount xTaskGetTickCount
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>TickType_t xTaskGetTickCountFromISR( void );</PRE>
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * This is a version of xTaskGetTickCount() that is safe to be called from an
+ * ISR - provided that TickType_t is the natural word size of the
+ * microcontroller being used or interrupt nesting is either not supported or
+ * not being used.
+ *
+ * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>uint16_t uxTaskGetNumberOfTasks( void );</PRE>
+ *
+ * @return The number of tasks that the real time kernel is currently managing.
+ * This includes all ready, blocked and suspended tasks.  A task that
+ * has been deleted but not yet freed by the idle task will also be
+ * included in the count.
+ *
+ * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
+ * \ingroup TaskUtils
+ */
+UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>char *pcTaskGetName( TaskHandle_t xTaskToQuery );</PRE>
+ *
+ * @return The text (human readable) name of the task referenced by the handle
+ * xTaskToQuery.  A task can query its own name by either passing in its own
+ * handle, or by setting xTaskToQuery to NULL.
+ *
+ * \defgroup pcTaskGetName pcTaskGetName
+ * \ingroup TaskUtils
+ */
+char * pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION;     /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * <PRE>TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );</PRE>
+ *
+ * NOTE:  This function takes a relatively long time to complete and should be
+ * used sparingly.
+ *
+ * @return The handle of the task that has the human readable name pcNameToQuery.
+ * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle
+ * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
+ *
+ * \defgroup pcTaskGetHandle pcTaskGetHandle
+ * \ingroup TaskUtils
+ */
+TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) PRIVILEGED_FUNCTION;     /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task.h
+ * <PRE>UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );</PRE>
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * <PRE>configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );</PRE>
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/* When using trace macros it is sometimes necessary to include task.h before
+ * FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
+ * so the following two prototypes will cause a compilation error.  This can be
+ * fixed by simply guarding against the inclusion of these two prototypes unless
+ * they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
+ * constant. */
+#ifdef configUSE_APPLICATION_TASK_TAG
+    #if configUSE_APPLICATION_TASK_TAG == 1
+
+/**
+ * task.h
+ * <pre>
+ * void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );
+ * </pre>
+ *
+ * Sets pxHookFunction to be the task hook function used by the task xTask.
+ * Passing xTask as NULL has the effect of setting the calling tasks hook
+ * function.
+ */
+        void vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                         TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * <pre>
+ * void xTaskGetApplicationTaskTag( TaskHandle_t xTask );
+ * </pre>
+ *
+ * Returns the pxHookFunction value assigned to the task xTask.  Do not
+ * call from an interrupt service routine - call
+ * xTaskGetApplicationTaskTagFromISR() instead.
+ */
+        TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * <pre>
+ * void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );
+ * </pre>
+ *
+ * Returns the pxHookFunction value assigned to the task xTask.  Can
+ * be called from an interrupt service routine.
+ */
+        TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+    #endif /* configUSE_APPLICATION_TASK_TAG ==1 */
+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+
+/* Each task contains an array of pointers that is dimensioned by the
+ * configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The
+ * kernel does not use the pointers itself, so the application writer can use
+ * the pointers for any purpose they wish.  The following two functions are
+ * used to set and query a pointer respectively. */
+    void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                            BaseType_t xIndex,
+                                            void * pvValue ) PRIVILEGED_FUNCTION;
+    void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                               BaseType_t xIndex ) PRIVILEGED_FUNCTION;
+
+#endif
+
+#if ( configCHECK_FOR_STACK_OVERFLOW > 0 )
+
+     /**
+      * task.h
+      * <pre>void vApplicationStackOverflowHook( TaskHandle_t xTask char *pcTaskName); </pre>
+      *
+      * The application stack overflow hook is called when a stack overflow is detected for a task.
+      *
+      * Details on stack overflow detection can be found here: https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html
+      *
+      * @param xTask the task that just exceeded its stack boundaries.
+      * @param pcTaskName A character string containing the name of the offending task.
+      */
+     void vApplicationStackOverflowHook( TaskHandle_t xTask,
+                                               char * pcTaskName );
+
+#endif
+
+#if  (  configUSE_TICK_HOOK > 0 )
+    /**
+     *  task.h
+     *  <pre>void vApplicationTickHook( void ); </pre>
+     *
+     * This hook function is called in the system tick handler after any OS work is completed.
+     */
+    void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
+
+#endif
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    /**
+     * task.h
+     * <pre>void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer, StackType_t ** ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ) </pre>
+     *
+     * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Idle Task TCB.  This function is required when
+     * configSUPPORT_STATIC_ALLOCATION is set.  For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION
+     *
+     * @param ppxIdleTaskTCBBuffer A handle to a statically allocated TCB buffer
+     * @param ppxIdleTaskStackBuffer A handle to a statically allocated Stack buffer for thie idle task
+     * @param pulIdleTaskStackSize A pointer to the number of elements that will fit in the allocated stack buffer
+     */
+    void vApplicationGetIdleTaskMemory( StaticTask_t ** ppxIdleTaskTCBBuffer,
+                                               StackType_t ** ppxIdleTaskStackBuffer,
+                                               uint32_t * pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
+#endif
+
+/**
+ * task.h
+ * <pre>
+ * BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );
+ * </pre>
+ *
+ * Calls the hook function associated with xTask.  Passing xTask as NULL has
+ * the effect of calling the Running tasks (the calling task) hook function.
+ *
+ * pvParameter is passed to the hook function for the task to interpret as it
+ * wants.  The return value is the value returned by the task hook function
+ * registered by the user.
+ */
+BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask,
+                                         void * pvParameter ) PRIVILEGED_FUNCTION;
+
+/**
+ * xTaskGetIdleTaskHandle() is only available if
+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
+ *
+ * Simply returns the handle of the idle task.  It is not valid to call
+ * xTaskGetIdleTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
+ * uxTaskGetSystemState() to be available.
+ *
+ * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
+ * the system.  TaskStatus_t structures contain, among other things, members
+ * for the task handle, task name, task priority, task state, and total amount
+ * of run time consumed by the task.  See the TaskStatus_t structure
+ * definition in this file for the full member list.
+ *
+ * NOTE:  This function is intended for debugging use only as its use results in
+ * the scheduler remaining suspended for an extended period.
+ *
+ * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
+ * The array must contain at least one TaskStatus_t structure for each task
+ * that is under the control of the RTOS.  The number of tasks under the control
+ * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
+ *
+ * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
+ * parameter.  The size is specified as the number of indexes in the array, or
+ * the number of TaskStatus_t structures contained in the array, not by the
+ * number of bytes in the array.
+ *
+ * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
+ * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
+ * total run time (as defined by the run time stats clock, see
+ * https://www.FreeRTOS.org/rtos-run-time-stats.html) since the target booted.
+ * pulTotalRunTime can be set to NULL to omit the total run time information.
+ *
+ * @return The number of TaskStatus_t structures that were populated by
+ * uxTaskGetSystemState().  This should equal the number returned by the
+ * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
+ * in the uxArraySize parameter was too small.
+ *
+ * Example usage:
+ * <pre>
+ *  // This example demonstrates how a human readable table of run time stats
+ *  // information is generated from raw data provided by uxTaskGetSystemState().
+ *  // The human readable table is written to pcWriteBuffer
+ *  void vTaskGetRunTimeStats( char *pcWriteBuffer )
+ *  {
+ *  TaskStatus_t *pxTaskStatusArray;
+ *  volatile UBaseType_t uxArraySize, x;
+ *  uint32_t ulTotalRunTime, ulStatsAsPercentage;
+ *
+ *      // Make sure the write buffer does not contain a string.
+ * pcWriteBuffer = 0x00;
+ *
+ *      // Take a snapshot of the number of tasks in case it changes while this
+ *      // function is executing.
+ *      uxArraySize = uxTaskGetNumberOfTasks();
+ *
+ *      // Allocate a TaskStatus_t structure for each task.  An array could be
+ *      // allocated statically at compile time.
+ *      pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+ *
+ *      if( pxTaskStatusArray != NULL )
+ *      {
+ *          // Generate raw status information about each task.
+ *          uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+ *
+ *          // For percentage calculations.
+ *          ulTotalRunTime /= 100UL;
+ *
+ *          // Avoid divide by zero errors.
+ *          if( ulTotalRunTime > 0 )
+ *          {
+ *              // For each populated position in the pxTaskStatusArray array,
+ *              // format the raw data as human readable ASCII data
+ *              for( x = 0; x < uxArraySize; x++ )
+ *              {
+ *                  // What percentage of the total run time has the task used?
+ *                  // This will always be rounded down to the nearest integer.
+ *                  // ulTotalRunTimeDiv100 has already been divided by 100.
+ *                  ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+ *
+ *                  if( ulStatsAsPercentage > 0UL )
+ *                  {
+ *                      sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+ *                  }
+ *                  else
+ *                  {
+ *                      // If the percentage is zero here then the task has
+ *                      // consumed less than 1% of the total run time.
+ *                      sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+ *                  }
+ *
+ *                  pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+ *              }
+ *          }
+ *
+ *          // The array is no longer needed, free the memory it consumes.
+ *          vPortFree( pxTaskStatusArray );
+ *      }
+ *  }
+ *  </pre>
+ */
+UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                  const UBaseType_t uxArraySize,
+                                  uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>void vTaskList( char *pcWriteBuffer );</PRE>
+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available.  See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
+ * suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * names, states and stack usage.
+ *
+ * vTaskList() has a dependency on the sprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms.  An alternative, tiny, third party, and limited
+ * functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskList().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form.  This buffer is assumed to be large
+ * enough to contain the generated report.  Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * \defgroup vTaskList vTaskList
+ * \ingroup TaskUtils
+ */
+void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION;     /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * <PRE>void vTaskGetRunTimeStats( char *pcWriteBuffer );</PRE>
+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available.  The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively.  The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStats() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms.  An alternative, tiny, third party, and
+ * limited functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStats().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form.  This buffer is assumed to be large enough to
+ * contain the generated report.  Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
+ * \ingroup TaskUtils
+ */
+void vTaskGetRunTimeStats( char * pcWriteBuffer ) PRIVILEGED_FUNCTION;     /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * <PRE>uint32_t ulTaskGetIdleRunTimeCounter( void );</PRE>
+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available.  The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively.  The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
+ * execution time of each task into a buffer, ulTaskGetIdleRunTimeCounter()
+ * returns the total execution time of just the idle task.
+ *
+ * @return The total run time of the idle task.  This is the amount of time the
+ * idle task has actually been executing.  The unit of time is dependent on the
+ * frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
+ * portGET_RUN_TIME_COUNTER_VALUE() macros.
+ *
+ * \defgroup ulTaskGetIdleRunTimeCounter ulTaskGetIdleRunTimeCounter
+ * \ingroup TaskUtils
+ */
+uint32_t ulTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction );</PRE>
+ * <PRE>BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );</PRE>
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
+ * functions to be available.
+ *
+ * Sends a direct to task notification to a task, with an optional value and
+ * action.
+ *
+ * Each task has a private array of "notification values" (or 'notifications'),
+ * each of which is a 32-bit unsigned integer (uint32_t).  The constant
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array, and (for backward compatibility) defaults to 1 if left undefined.
+ * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment one of the task's notification values.  In
+ * that way task notifications can be used to send data to a task, or be used as
+ * light weight and fast binary or counting semaphores.
+ *
+ * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block
+ * to wait for a notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their
+ * un-indexed equivalents).  If the task was already in the Blocked state to
+ * wait for a notification when the notification arrives then the task will
+ * automatically be removed from the Blocked state (unblocked) and the
+ * notification cleared.
+ *
+ * **NOTE** Each notification within the array operates independently - a task
+ * can only block on one notification within the array at a time and will not be
+ * unblocked by a notification sent to any other array index.
+ *
+ * Backward compatibility information:
+ * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
+ * all task notification API functions operated on that value. Replacing the
+ * single notification value with an array of notification values necessitated a
+ * new set of API functions that could address specific notifications within the
+ * array.  xTaskNotify() is the original API function, and remains backward
+ * compatible by always operating on the notification value at index 0 in the
+ * array. Calling xTaskNotify() is equivalent to calling xTaskNotifyIndexed()
+ * with the uxIndexToNotify parameter set to 0.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param uxIndexToNotify The index within the target task's array of
+ * notification values to which the notification is to be sent.  uxIndexToNotify
+ * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotify() does
+ * not have this parameter and always sends notifications to index 0.
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The target notification value is bitwise ORed with ulValue.
+ * xTaskNofifyIndexed() always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The target notification value is incremented.  ulValue is not used and
+ * xTaskNotifyIndexed() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The target notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification at the
+ * same array index (the task already had a notification pending at that index).
+ * xTaskNotifyIndexed() always returns pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending at the
+ * same array index then the target notification value is set to ulValue and
+ * xTaskNotifyIndexed() will return pdPASS.  If the task being notified already
+ * had a notification pending at the same array index then no action is
+ * performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification at the specified array index without the
+ * notification value at that index being updated.  ulValue is not used and
+ * xTaskNotifyIndexed() always returns pdPASS in this case.
+ *
+ * pulPreviousNotificationValue -
+ * Can be used to pass out the subject task's notification value before any
+ * bits are modified by the notify function.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotifyIndexed xTaskNotifyIndexed
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                               UBaseType_t uxIndexToNotify,
+                               uint32_t ulValue,
+                               eNotifyAction eAction,
+                               uint32_t * pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
+#define xTaskNotify( xTaskToNotify, ulValue, eAction ) \
+    xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL )
+#define xTaskNotifyIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction ) \
+    xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL )
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyAndQueryIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue );</PRE>
+ * <PRE>BaseType_t xTaskNotifyAndQuery( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotifyValue );</PRE>
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * xTaskNotifyAndQueryIndexed() performs the same operation as
+ * xTaskNotifyIndexed() with the addition that it also returns the subject
+ * task's prior notification value (the notification value at the time the
+ * function is called rather than when the function returns) in the additional
+ * pulPreviousNotifyValue parameter.
+ *
+ * xTaskNotifyAndQuery() performs the same operation as xTaskNotify() with the
+ * addition that it also returns the subject task's prior notification value
+ * (the notification value as it was at the time the function is called, rather
+ * than when the function returns) in the additional pulPreviousNotifyValue
+ * parameter.
+ *
+ * \defgroup xTaskNotifyAndQueryIndexed xTaskNotifyAndQueryIndexed
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) \
+    xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
+#define xTaskNotifyAndQueryIndexed( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotifyValue ) \
+    xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );</PRE>
+ * <PRE>BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );</PRE>
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
+ * functions to be available.
+ *
+ * A version of xTaskNotifyIndexed() that can be used from an interrupt service
+ * routine (ISR).
+ *
+ * Each task has a private array of "notification values" (or 'notifications'),
+ * each of which is a 32-bit unsigned integer (uint32_t).  The constant
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array, and (for backward compatibility) defaults to 1 if left undefined.
+ * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment one of the task's notification values.  In
+ * that way task notifications can be used to send data to a task, or be used as
+ * light weight and fast binary or counting semaphores.
+ *
+ * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block
+ * to wait for a notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their
+ * un-indexed equivalents).  If the task was already in the Blocked state to
+ * wait for a notification when the notification arrives then the task will
+ * automatically be removed from the Blocked state (unblocked) and the
+ * notification cleared.
+ *
+ * **NOTE** Each notification within the array operates independently - a task
+ * can only block on one notification within the array at a time and will not be
+ * unblocked by a notification sent to any other array index.
+ *
+ * Backward compatibility information:
+ * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
+ * all task notification API functions operated on that value. Replacing the
+ * single notification value with an array of notification values necessitated a
+ * new set of API functions that could address specific notifications within the
+ * array.  xTaskNotifyFromISR() is the original API function, and remains
+ * backward compatible by always operating on the notification value at index 0
+ * within the array. Calling xTaskNotifyFromISR() is equivalent to calling
+ * xTaskNotifyIndexedFromISR() with the uxIndexToNotify parameter set to 0.
+ *
+ * @param uxIndexToNotify The index within the target task's array of
+ * notification values to which the notification is to be sent.  uxIndexToNotify
+ * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyFromISR()
+ * does not have this parameter and always sends notifications to index 0.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
+ * be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotifyIndexedFromISR xTaskNotifyIndexedFromISR
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify,
+                                      UBaseType_t uxIndexToNotify,
+                                      uint32_t ulValue,
+                                      eNotifyAction eAction,
+                                      uint32_t * pulPreviousNotificationValue,
+                                      BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \
+    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
+#define xTaskNotifyIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) \
+    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyAndQueryIndexedFromISR( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken );</PRE>
+ * <PRE>BaseType_t xTaskNotifyAndQueryFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken );</PRE>
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * xTaskNotifyAndQueryIndexedFromISR() performs the same operation as
+ * xTaskNotifyIndexedFromISR() with the addition that it also returns the
+ * subject task's prior notification value (the notification value at the time
+ * the function is called rather than at the time the function returns) in the
+ * additional pulPreviousNotifyValue parameter.
+ *
+ * xTaskNotifyAndQueryFromISR() performs the same operation as
+ * xTaskNotifyFromISR() with the addition that it also returns the subject
+ * task's prior notification value (the notification value at the time the
+ * function is called rather than at the time the function returns) in the
+ * additional pulPreviousNotifyValue parameter.
+ *
+ * \defgroup xTaskNotifyAndQueryIndexedFromISR xTaskNotifyAndQueryIndexedFromISR
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyAndQueryIndexedFromISR( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \
+    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
+#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) \
+    xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * task. h
+ * <pre>
+ * BaseType_t xTaskNotifyWaitIndexed( UBaseType_t uxIndexToWaitOn, uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
+ *
+ * BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
+ * </pre>
+ *
+ * Waits for a direct to task notification to be pending at a given index within
+ * an array of direct to task notifications.
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * Each task has a private array of "notification values" (or 'notifications'),
+ * each of which is a 32-bit unsigned integer (uint32_t).  The constant
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array, and (for backward compatibility) defaults to 1 if left undefined.
+ * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment one of the task's notification values.  In
+ * that way task notifications can be used to send data to a task, or be used as
+ * light weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWaitIndexed() or ulTaskNotifyTakeIndexed() (or their
+ * un-indexed equivalents).  If the task was already in the Blocked state to
+ * wait for a notification when the notification arrives then the task will
+ * automatically be removed from the Blocked state (unblocked) and the
+ * notification cleared.
+ *
+ * A task can use xTaskNotifyWaitIndexed() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTakeIndexed() to [optionally] block
+ * to wait for a notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * **NOTE** Each notification within the array operates independently - a task
+ * can only block on one notification within the array at a time and will not be
+ * unblocked by a notification sent to any other array index.
+ *
+ * Backward compatibility information:
+ * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
+ * all task notification API functions operated on that value. Replacing the
+ * single notification value with an array of notification values necessitated a
+ * new set of API functions that could address specific notifications within the
+ * array.  xTaskNotifyWait() is the original API function, and remains backward
+ * compatible by always operating on the notification value at index 0 in the
+ * array. Calling xTaskNotifyWait() is equivalent to calling
+ * xTaskNotifyWaitIndexed() with the uxIndexToWaitOn parameter set to 0.
+ *
+ * @param uxIndexToWaitOn The index within the calling task's array of
+ * notification values on which the calling task will wait for a notification to
+ * be received.  uxIndexToWaitOn must be less than
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyWait() does
+ * not have this parameter and always waits for notifications on index 0.
+ *
+ * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
+ * will be cleared in the calling task's notification value before the task
+ * checks to see if any notifications are pending, and optionally blocks if no
+ * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
+ * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
+ * the effect of resetting the task's notification value to 0.  Setting
+ * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
+ *
+ * @param ulBitsToClearOnExit If a notification is pending or received before
+ * the calling task exits the xTaskNotifyWait() function then the task's
+ * notification value (see the xTaskNotify() API function) is passed out using
+ * the pulNotificationValue parameter.  Then any bits that are set in
+ * ulBitsToClearOnExit will be cleared in the task's notification value (note
+ * *pulNotificationValue is set before any bits are cleared).  Setting
+ * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
+ * (if limits.h is not included) will have the effect of resetting the task's
+ * notification value to 0 before the function exits.  Setting
+ * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
+ * when the function exits (in which case the value passed out in
+ * pulNotificationValue will match the task's notification value).
+ *
+ * @param pulNotificationValue Used to pass the task's notification value out
+ * of the function.  Note the value passed out will not be effected by the
+ * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for a notification to be received, should a notification
+ * not already be pending when xTaskNotifyWait() was called.  The task
+ * will not consume any processing time while it is in the Blocked state.  This
+ * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be
+ * used to convert a time specified in milliseconds to a time specified in
+ * ticks.
+ *
+ * @return If a notification was received (including notifications that were
+ * already pending when xTaskNotifyWait was called) then pdPASS is
+ * returned.  Otherwise pdFAIL is returned.
+ *
+ * \defgroup xTaskNotifyWaitIndexed xTaskNotifyWaitIndexed
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                   uint32_t ulBitsToClearOnEntry,
+                                   uint32_t ulBitsToClearOnExit,
+                                   uint32_t * pulNotificationValue,
+                                   TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyWait( ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \
+    xTaskGenericNotifyWait( tskDEFAULT_INDEX_TO_NOTIFY, ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) )
+#define xTaskNotifyWaitIndexed( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait ) \
+    xTaskGenericNotifyWait( ( uxIndexToWaitOn ), ( ulBitsToClearOnEntry ), ( ulBitsToClearOnExit ), ( pulNotificationValue ), ( xTicksToWait ) )
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyGiveIndexed( TaskHandle_t xTaskToNotify, UBaseType_t uxIndexToNotify );</PRE>
+ * <PRE>BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );</PRE>
+ *
+ * Sends a direct to task notification to a particular index in the target
+ * task's notification array in a manner similar to giving a counting semaphore.
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
+ * macros to be available.
+ *
+ * Each task has a private array of "notification values" (or 'notifications'),
+ * each of which is a 32-bit unsigned integer (uint32_t).  The constant
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array, and (for backward compatibility) defaults to 1 if left undefined.
+ * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment one of the task's notification values.  In
+ * that way task notifications can be used to send data to a task, or be used as
+ * light weight and fast binary or counting semaphores.
+ *
+ * xTaskNotifyGiveIndexed() is a helper macro intended for use when task
+ * notifications are used as light weight and faster binary or counting
+ * semaphore equivalents.  Actual FreeRTOS semaphores are given using the
+ * xSemaphoreGive() API function, the equivalent action that instead uses a task
+ * notification is xTaskNotifyGiveIndexed().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTakeIndexed() API function rather than the
+ * xTaskNotifyWaitIndexed() API function.
+ *
+ * **NOTE** Each notification within the array operates independently - a task
+ * can only block on one notification within the array at a time and will not be
+ * unblocked by a notification sent to any other array index.
+ *
+ * Backward compatibility information:
+ * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
+ * all task notification API functions operated on that value. Replacing the
+ * single notification value with an array of notification values necessitated a
+ * new set of API functions that could address specific notifications within the
+ * array.  xTaskNotifyGive() is the original API function, and remains backward
+ * compatible by always operating on the notification value at index 0 in the
+ * array. Calling xTaskNotifyGive() is equivalent to calling
+ * xTaskNotifyGiveIndexed() with the uxIndexToNotify parameter set to 0.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param uxIndexToNotify The index within the target task's array of
+ * notification values to which the notification is to be sent.  uxIndexToNotify
+ * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyGive()
+ * does not have this parameter and always sends notifications to index 0.
+ *
+ * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
+ * eAction parameter set to eIncrement - so pdPASS is always returned.
+ *
+ * \defgroup xTaskNotifyGiveIndexed xTaskNotifyGiveIndexed
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyGive( xTaskToNotify ) \
+    xTaskGenericNotify( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( 0 ), eIncrement, NULL )
+#define xTaskNotifyGiveIndexed( xTaskToNotify, uxIndexToNotify ) \
+    xTaskGenericNotify( ( xTaskToNotify ), ( uxIndexToNotify ), ( 0 ), eIncrement, NULL )
+
+/**
+ * task. h
+ * <PRE>void vTaskNotifyGiveIndexedFromISR( TaskHandle_t xTaskHandle, UBaseType_t uxIndexToNotify, BaseType_t *pxHigherPriorityTaskWoken );</PRE>
+ * <PRE>void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );</PRE>
+ *
+ * A version of xTaskNotifyGiveIndexed() that can be called from an interrupt
+ * service routine (ISR).
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * Each task has a private array of "notification values" (or 'notifications'),
+ * each of which is a 32-bit unsigned integer (uint32_t).  The constant
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array, and (for backward compatibility) defaults to 1 if left undefined.
+ * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment one of the task's notification values.  In
+ * that way task notifications can be used to send data to a task, or be used as
+ * light weight and fast binary or counting semaphores.
+ *
+ * vTaskNotifyGiveIndexedFromISR() is intended for use when task notifications
+ * are used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given from an ISR using the
+ * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
+ * a task notification is vTaskNotifyGiveIndexedFromISR().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTakeIndexed() API function rather than the
+ * xTaskNotifyWaitIndexed() API function.
+ *
+ * **NOTE** Each notification within the array operates independently - a task
+ * can only block on one notification within the array at a time and will not be
+ * unblocked by a notification sent to any other array index.
+ *
+ * Backward compatibility information:
+ * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
+ * all task notification API functions operated on that value. Replacing the
+ * single notification value with an array of notification values necessitated a
+ * new set of API functions that could address specific notifications within the
+ * array.  xTaskNotifyFromISR() is the original API function, and remains
+ * backward compatible by always operating on the notification value at index 0
+ * within the array. Calling xTaskNotifyGiveFromISR() is equivalent to calling
+ * xTaskNotifyGiveIndexedFromISR() with the uxIndexToNotify parameter set to 0.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param uxIndexToNotify The index within the target task's array of
+ * notification values to which the notification is to be sent.  uxIndexToNotify
+ * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.
+ * xTaskNotifyGiveFromISR() does not have this parameter and always sends
+ * notifications to index 0.
+ *
+ * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
+ * should be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * \defgroup vTaskNotifyGiveIndexedFromISR vTaskNotifyGiveIndexedFromISR
+ * \ingroup TaskNotifications
+ */
+void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify,
+                                    UBaseType_t uxIndexToNotify,
+                                    BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#define vTaskNotifyGiveFromISR( xTaskToNotify, pxHigherPriorityTaskWoken ) \
+    vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( pxHigherPriorityTaskWoken ) );
+#define vTaskNotifyGiveIndexedFromISR( xTaskToNotify, uxIndexToNotify, pxHigherPriorityTaskWoken ) \
+    vTaskGenericNotifyGiveFromISR( ( xTaskToNotify ), ( uxIndexToNotify ), ( pxHigherPriorityTaskWoken ) );
+
+/**
+ * task. h
+ * <pre>
+ * uint32_t ulTaskNotifyTakeIndexed( UBaseType_t uxIndexToWaitOn, BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
+ *
+ * uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
+ * </pre>
+ *
+ * Waits for a direct to task notification on a particular index in the calling
+ * task's notification array in a manner similar to taking a counting semaphore.
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * Each task has a private array of "notification values" (or 'notifications'),
+ * each of which is a 32-bit unsigned integer (uint32_t).  The constant
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array, and (for backward compatibility) defaults to 1 if left undefined.
+ * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment one of the task's notification values.  In
+ * that way task notifications can be used to send data to a task, or be used as
+ * light weight and fast binary or counting semaphores.
+ *
+ * ulTaskNotifyTakeIndexed() is intended for use when a task notification is
+ * used as a faster and lighter weight binary or counting semaphore alternative.
+ * Actual FreeRTOS semaphores are taken using the xSemaphoreTake() API function,
+ * the equivalent action that instead uses a task notification is
+ * ulTaskNotifyTakeIndexed().
+ *
+ * When a task is using its notification value as a binary or counting semaphore
+ * other tasks should send notifications to it using the xTaskNotifyGiveIndexed()
+ * macro, or xTaskNotifyIndex() function with the eAction parameter set to
+ * eIncrement.
+ *
+ * ulTaskNotifyTakeIndexed() can either clear the task's notification value at
+ * the array index specified by the uxIndexToWaitOn parameter to zero on exit,
+ * in which case the notification value acts like a binary semaphore, or
+ * decrement the notification value on exit, in which case the notification
+ * value acts like a counting semaphore.
+ *
+ * A task can use ulTaskNotifyTakeIndexed() to [optionally] block to wait for
+ * the task's notification value to be non-zero.  The task does not consume any
+ * CPU time while it is in the Blocked state.
+ *
+ * Where as xTaskNotifyWaitIndexed() will return when a notification is pending,
+ * ulTaskNotifyTakeIndexed() will return when the task's notification value is
+ * not zero.
+ *
+ * **NOTE** Each notification within the array operates independently - a task
+ * can only block on one notification within the array at a time and will not be
+ * unblocked by a notification sent to any other array index.
+ *
+ * Backward compatibility information:
+ * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
+ * all task notification API functions operated on that value. Replacing the
+ * single notification value with an array of notification values necessitated a
+ * new set of API functions that could address specific notifications within the
+ * array.  ulTaskNotifyTake() is the original API function, and remains backward
+ * compatible by always operating on the notification value at index 0 in the
+ * array. Calling ulTaskNotifyTake() is equivalent to calling
+ * ulTaskNotifyTakeIndexed() with the uxIndexToWaitOn parameter set to 0.
+ *
+ * @param uxIndexToWaitOn The index within the calling task's array of
+ * notification values on which the calling task will wait for a notification to
+ * be non-zero.  uxIndexToWaitOn must be less than
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES.  xTaskNotifyTake() does
+ * not have this parameter and always waits for notifications on index 0.
+ *
+ * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
+ * notification value is decremented when the function exits.  In this way the
+ * notification value acts like a counting semaphore.  If xClearCountOnExit is
+ * not pdFALSE then the task's notification value is cleared to zero when the
+ * function exits.  In this way the notification value acts like a binary
+ * semaphore.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for the task's notification value to be greater than zero,
+ * should the count not already be greater than zero when
+ * ulTaskNotifyTake() was called.  The task will not consume any processing
+ * time while it is in the Blocked state.  This is specified in kernel ticks,
+ * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
+ * specified in milliseconds to a time specified in ticks.
+ *
+ * @return The task's notification count before it is either cleared to zero or
+ * decremented (see the xClearCountOnExit parameter).
+ *
+ * \defgroup ulTaskNotifyTakeIndexed ulTaskNotifyTakeIndexed
+ * \ingroup TaskNotifications
+ */
+uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                  BaseType_t xClearCountOnExit,
+                                  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+#define ulTaskNotifyTake( xClearCountOnExit, xTicksToWait ) \
+    ulTaskGenericNotifyTake( ( tskDEFAULT_INDEX_TO_NOTIFY ), ( xClearCountOnExit ), ( xTicksToWait ) )
+#define ulTaskNotifyTakeIndexed( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait ) \
+    ulTaskGenericNotifyTake( ( uxIndexToWaitOn ), ( xClearCountOnExit ), ( xTicksToWait ) )
+
+/**
+ * task. h
+ * <pre>
+ * BaseType_t xTaskNotifyStateClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToCLear );
+ *
+ * BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
+ * </pre>
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
+ * functions to be available.
+ *
+ * Each task has a private array of "notification values" (or 'notifications'),
+ * each of which is a 32-bit unsigned integer (uint32_t).  The constant
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array, and (for backward compatibility) defaults to 1 if left undefined.
+ * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
+ *
+ * If a notification is sent to an index within the array of notifications then
+ * the notification at that index is said to be 'pending' until it is read or
+ * explicitly cleared by the receiving task.  xTaskNotifyStateClearIndexed()
+ * is the function that clears a pending notification without reading the
+ * notification value.  The notification value at the same array index is not
+ * altered.  Set xTask to NULL to clear the notification state of the calling
+ * task.
+ *
+ * Backward compatibility information:
+ * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
+ * all task notification API functions operated on that value. Replacing the
+ * single notification value with an array of notification values necessitated a
+ * new set of API functions that could address specific notifications within the
+ * array.  xTaskNotifyStateClear() is the original API function, and remains
+ * backward compatible by always operating on the notification value at index 0
+ * within the array. Calling xTaskNotifyStateClear() is equivalent to calling
+ * xTaskNotifyStateClearIndexed() with the uxIndexToNotify parameter set to 0.
+ *
+ * @param xTask The handle of the RTOS task that will have a notification state
+ * cleared.  Set xTask to NULL to clear a notification state in the calling
+ * task.  To obtain a task's handle create the task using xTaskCreate() and
+ * make use of the pxCreatedTask parameter, or create the task using
+ * xTaskCreateStatic() and store the returned value, or use the task's name in
+ * a call to xTaskGetHandle().
+ *
+ * @param uxIndexToClear The index within the target task's array of
+ * notification values to act upon.  For example, setting uxIndexToClear to 1
+ * will clear the state of the notification at index 1 within the array.
+ * uxIndexToClear must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.
+ * ulTaskNotifyStateClear() does not have this parameter and always acts on the
+ * notification at index 0.
+ *
+ * @return pdTRUE if the task's notification state was set to
+ * eNotWaitingNotification, otherwise pdFALSE.
+ *
+ * \defgroup xTaskNotifyStateClearIndexed xTaskNotifyStateClearIndexed
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                         UBaseType_t uxIndexToClear ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyStateClear( xTask ) \
+    xTaskGenericNotifyStateClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ) )
+#define xTaskNotifyStateClearIndexed( xTask, uxIndexToClear ) \
+    xTaskGenericNotifyStateClear( ( xTask ), ( uxIndexToClear ) )
+
+/**
+ * task. h
+ * <pre>
+ * uint32_t ulTaskNotifyValueClearIndexed( TaskHandle_t xTask, UBaseType_t uxIndexToClear, uint32_t ulBitsToClear );
+ *
+ * uint32_t ulTaskNotifyValueClear( TaskHandle_t xTask, uint32_t ulBitsToClear );
+ * </pre>
+ *
+ * See https://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for these
+ * functions to be available.
+ *
+ * Each task has a private array of "notification values" (or 'notifications'),
+ * each of which is a 32-bit unsigned integer (uint32_t).  The constant
+ * configTASK_NOTIFICATION_ARRAY_ENTRIES sets the number of indexes in the
+ * array, and (for backward compatibility) defaults to 1 if left undefined.
+ * Prior to FreeRTOS V10.4.0 there was only one notification value per task.
+ *
+ * ulTaskNotifyValueClearIndexed() clears the bits specified by the
+ * ulBitsToClear bit mask in the notification value at array index uxIndexToClear
+ * of the task referenced by xTask.
+ *
+ * Backward compatibility information:
+ * Prior to FreeRTOS V10.4.0 each task had a single "notification value", and
+ * all task notification API functions operated on that value. Replacing the
+ * single notification value with an array of notification values necessitated a
+ * new set of API functions that could address specific notifications within the
+ * array.  ulTaskNotifyValueClear() is the original API function, and remains
+ * backward compatible by always operating on the notification value at index 0
+ * within the array. Calling ulTaskNotifyValueClear() is equivalent to calling
+ * ulTaskNotifyValueClearIndexed() with the uxIndexToClear parameter set to 0.
+ *
+ * @param xTask The handle of the RTOS task that will have bits in one of its
+ * notification values cleared. Set xTask to NULL to clear bits in a
+ * notification value of the calling task.  To obtain a task's handle create the
+ * task using xTaskCreate() and make use of the pxCreatedTask parameter, or
+ * create the task using xTaskCreateStatic() and store the returned value, or
+ * use the task's name in a call to xTaskGetHandle().
+ *
+ * @param uxIndexToClear The index within the target task's array of
+ * notification values in which to clear the bits.  uxIndexToClear
+ * must be less than configTASK_NOTIFICATION_ARRAY_ENTRIES.
+ * ulTaskNotifyValueClear() does not have this parameter and always clears bits
+ * in the notification value at index 0.
+ *
+ * @param ulBitsToClear Bit mask of the bits to clear in the notification value of
+ * xTask. Set a bit to 1 to clear the corresponding bits in the task's notification
+ * value. Set ulBitsToClear to 0xffffffff (UINT_MAX on 32-bit architectures) to clear
+ * the notification value to 0.  Set ulBitsToClear to 0 to query the task's
+ * notification value without clearing any bits.
+ *
+ *
+ * @return The value of the target task's notification value before the bits
+ * specified by ulBitsToClear were cleared.
+ * \defgroup ulTaskNotifyValueClear ulTaskNotifyValueClear
+ * \ingroup TaskNotifications
+ */
+uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                        UBaseType_t uxIndexToClear,
+                                        uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+#define ulTaskNotifyValueClear( xTask, ulBitsToClear ) \
+    ulTaskGenericNotifyValueClear( ( xTask ), ( tskDEFAULT_INDEX_TO_NOTIFY ), ( ulBitsToClear ) )
+#define ulTaskNotifyValueClearIndexed( xTask, uxIndexToClear, ulBitsToClear ) \
+    ulTaskGenericNotifyValueClear( ( xTask ), ( uxIndexToClear ), ( ulBitsToClear ) )
+
+/**
+ * task.h
+ * <pre>
+ * void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut );
+ * </pre>
+ *
+ * Capture the current time for future use with xTaskCheckForTimeOut().
+ *
+ * @param pxTimeOut Pointer to a timeout object into which the current time
+ * is to be captured.  The captured time includes the tick count and the number
+ * of times the tick count has overflowed since the system first booted.
+ * \defgroup vTaskSetTimeOutState vTaskSetTimeOutState
+ * \ingroup TaskCtrl
+ */
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * <pre>
+ * BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );
+ * </pre>
+ *
+ * Determines if pxTicksToWait ticks has passed since a time was captured
+ * using a call to vTaskSetTimeOutState().  The captured time includes the tick
+ * count and the number of times the tick count has overflowed.
+ *
+ * @param pxTimeOut The time status as captured previously using
+ * vTaskSetTimeOutState. If the timeout has not yet occurred, it is updated
+ * to reflect the current time status.
+ * @param pxTicksToWait The number of ticks to check for timeout i.e. if
+ * pxTicksToWait ticks have passed since pxTimeOut was last updated (either by
+ * vTaskSetTimeOutState() or xTaskCheckForTimeOut()), the timeout has occurred.
+ * If the timeout has not occurred, pxTIcksToWait is updated to reflect the
+ * number of remaining ticks.
+ *
+ * @return If timeout has occurred, pdTRUE is returned. Otherwise pdFALSE is
+ * returned and pxTicksToWait is updated to reflect the number of remaining
+ * ticks.
+ *
+ * @see https://www.FreeRTOS.org/xTaskCheckForTimeOut.html
+ *
+ * Example Usage:
+ * <pre>
+ *  // Driver library function used to receive uxWantedBytes from an Rx buffer
+ *  // that is filled by a UART interrupt. If there are not enough bytes in the
+ *  // Rx buffer then the task enters the Blocked state until it is notified that
+ *  // more data has been placed into the buffer. If there is still not enough
+ *  // data then the task re-enters the Blocked state, and xTaskCheckForTimeOut()
+ *  // is used to re-calculate the Block time to ensure the total amount of time
+ *  // spent in the Blocked state does not exceed MAX_TIME_TO_WAIT. This
+ *  // continues until either the buffer contains at least uxWantedBytes bytes,
+ *  // or the total amount of time spent in the Blocked state reaches
+ *  // MAX_TIME_TO_WAIT – at which point the task reads however many bytes are
+ *  // available up to a maximum of uxWantedBytes.
+ *
+ *  size_t xUART_Receive( uint8_t *pucBuffer, size_t uxWantedBytes )
+ *  {
+ *  size_t uxReceived = 0;
+ *  TickType_t xTicksToWait = MAX_TIME_TO_WAIT;
+ *  TimeOut_t xTimeOut;
+ *
+ *      // Initialize xTimeOut.  This records the time at which this function
+ *      // was entered.
+ *      vTaskSetTimeOutState( &xTimeOut );
+ *
+ *      // Loop until the buffer contains the wanted number of bytes, or a
+ *      // timeout occurs.
+ *      while( UART_bytes_in_rx_buffer( pxUARTInstance ) < uxWantedBytes )
+ *      {
+ *          // The buffer didn't contain enough data so this task is going to
+ *          // enter the Blocked state. Adjusting xTicksToWait to account for
+ *          // any time that has been spent in the Blocked state within this
+ *          // function so far to ensure the total amount of time spent in the
+ *          // Blocked state does not exceed MAX_TIME_TO_WAIT.
+ *          if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) != pdFALSE )
+ *          {
+ *              //Timed out before the wanted number of bytes were available,
+ *              // exit the loop.
+ *              break;
+ *          }
+ *
+ *          // Wait for a maximum of xTicksToWait ticks to be notified that the
+ *          // receive interrupt has placed more data into the buffer.
+ *          ulTaskNotifyTake( pdTRUE, xTicksToWait );
+ *      }
+ *
+ *      // Attempt to read uxWantedBytes from the receive buffer into pucBuffer.
+ *      // The actual number of bytes read (which might be less than
+ *      // uxWantedBytes) is returned.
+ *      uxReceived = UART_read_from_receive_buffer( pxUARTInstance,
+ *                                                  pucBuffer,
+ *                                                  uxWantedBytes );
+ *
+ *      return uxReceived;
+ *  }
+ * </pre>
+ * \defgroup xTaskCheckForTimeOut xTaskCheckForTimeOut
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                 TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task.h
+ * <pre>
+ * BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp );
+ * </pre>
+ *
+ * This function corrects the tick count value after the application code has held
+ * interrupts disabled for an extended period resulting in tick interrupts having
+ * been missed.
+ *
+ * This function is similar to vTaskStepTick(), however, unlike
+ * vTaskStepTick(), xTaskCatchUpTicks() may move the tick count forward past a
+ * time at which a task should be removed from the blocked state.  That means
+ * tasks may have to be removed from the blocked state as the tick count is
+ * moved.
+ *
+ * @param xTicksToCatchUp The number of tick interrupts that have been missed due to
+ * interrupts being disabled.  Its value is not computed automatically, so must be
+ * computed by the application writer.
+ *
+ * @return pdTRUE if moving the tick count forward resulted in a task leaving the
+ * blocked state and a context switch being performed.  Otherwise pdFALSE.
+ *
+ * \defgroup xTaskCatchUpTicks xTaskCatchUpTicks
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) PRIVILEGED_FUNCTION;
+
+
+/*-----------------------------------------------------------
+* SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
+*----------------------------------------------------------*/
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Called from the real time kernel tick (either preemptive or cooperative),
+ * this increments the tick count and checks if any tasks that are blocked
+ * for a finite period required removing from a blocked list and placing on
+ * a ready list.  If a non-zero value is returned then a context switch is
+ * required because either:
+ *   + A task was removed from a blocked list because its timeout had expired,
+ *     or
+ *   + Time slicing is in use and there is a task of equal priority to the
+ *     currently running task.
+ */
+BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes the calling task from the ready list and places it both
+ * on the list of tasks waiting for a particular event, and the
+ * list of delayed tasks.  The task will be removed from both lists
+ * and replaced on the ready list should either the event occur (and
+ * there be no higher priority tasks waiting on the same event) or
+ * the delay period expires.
+ *
+ * The 'unordered' version replaces the event list item value with the
+ * xItemValue value, and inserts the list item at the end of the list.
+ *
+ * The 'ordered' version uses the existing event list item value (which is the
+ * owning tasks priority) to insert the list item into the event list is task
+ * priority order.
+ *
+ * @param pxEventList The list containing tasks that are blocked waiting
+ * for the event to occur.
+ *
+ * @param xItemValue The item value to use for the event list item when the
+ * event list is not ordered by task priority.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait
+ * for the event to occur.  This is specified in kernel ticks,the constant
+ * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
+ * period.
+ */
+void vTaskPlaceOnEventList( List_t * const pxEventList,
+                            const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList,
+                                     const TickType_t xItemValue,
+                                     const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * This function performs nearly the same function as vTaskPlaceOnEventList().
+ * The difference being that this function does not permit tasks to block
+ * indefinitely, whereas vTaskPlaceOnEventList() does.
+ *
+ */
+void vTaskPlaceOnEventListRestricted( List_t * const pxEventList,
+                                      TickType_t xTicksToWait,
+                                      const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes a task from both the specified event list and the list of blocked
+ * tasks, and places it on a ready queue.
+ *
+ * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
+ * if either an event occurs to unblock a task, or the block timeout period
+ * expires.
+ *
+ * xTaskRemoveFromEventList() is used when the event list is in task priority
+ * order.  It removes the list item from the head of the event list as that will
+ * have the highest priority owning task of all the tasks on the event list.
+ * vTaskRemoveFromUnorderedEventList() is used when the event list is not
+ * ordered and the event list items hold something other than the owning tasks
+ * priority.  In this case the event list item value is updated to the value
+ * passed in the xItemValue parameter.
+ *
+ * @return pdTRUE if the task being removed has a higher priority than the task
+ * making the call, otherwise pdFALSE.
+ */
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem,
+                                        const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Sets the pointer to the current TCB to the TCB of the highest priority task
+ * that is ready to run.
+ */
+portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
+ * THE EVENT BITS MODULE.
+ */
+TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the handle of the calling task.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Shortcut used by the queue implementation to prevent unnecessary call to
+ * taskYIELD();
+ */
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
+ */
+BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Raises the priority of the mutex holder to that of the calling task should
+ * the mutex holder have a priority less than the calling task.
+ */
+BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the priority of a task back to its proper priority in the case that it
+ * inherited a higher priority while it was holding a semaphore.
+ */
+BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a higher priority task attempting to obtain a mutex caused a lower
+ * priority task to inherit the higher priority task's priority - but the higher
+ * priority task then timed out without obtaining the mutex, then the lower
+ * priority task will disinherit the priority again - but only down as far as
+ * the highest priority task that is still waiting for the mutex (if there were
+ * more than one task waiting for the mutex).
+ */
+void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder,
+                                          UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
+ */
+UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the uxTaskNumber of the task referenced by the xTask parameter to
+ * uxHandle.
+ */
+void vTaskSetTaskNumber( TaskHandle_t xTask,
+                         const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * If tickless mode is being used, or a low power mode is implemented, then
+ * the tick interrupt will not execute during idle periods.  When this is the
+ * case, the tick count value maintained by the scheduler needs to be kept up
+ * to date with the actual execution time by being skipped forward by a time
+ * equal to the idle period.
+ */
+void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
+ * specific sleep function to determine if it is ok to proceed with the sleep,
+ * and if it is ok to proceed, if it is ok to sleep indefinitely.
+ *
+ * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
+ * called with the scheduler suspended, not from within a critical section.  It
+ * is therefore possible for an interrupt to request a context switch between
+ * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
+ * entered.  eTaskConfirmSleepModeStatus() should be called from a short
+ * critical section between the timer being stopped and the sleep mode being
+ * entered to ensure it is ok to proceed into the sleep mode.
+ */
+eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Increment the mutex held count when a mutex is
+ * taken and return the handle of the task that has taken the mutex.
+ */
+TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Same as vTaskSetTimeOutState(), but without a critical
+ * section.
+ */
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+#endif /* INC_TASK_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/timers.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/timers.h
new file mode 100644
index 0000000..f767d5c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/include/timers.h
@@ -0,0 +1,1351 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef TIMERS_H
+#define TIMERS_H
+
+#ifndef INC_FREERTOS_H
+    #error "include FreeRTOS.h must appear in source files before include timers.h"
+#endif
+
+/*lint -save -e537 This headers are only multiply included if the application code
+ * happens to also be including task.h. */
+#include "task.h"
+/*lint -restore */
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*-----------------------------------------------------------
+* MACROS AND DEFINITIONS
+*----------------------------------------------------------*/
+
+/* IDs for commands that can be sent/received on the timer queue.  These are to
+ * be used solely through the macros that make up the public software timer API,
+ * as defined below.  The commands that are sent from interrupts must use the
+ * highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
+ * or interrupt version of the queue send function should be used. */
+#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR    ( ( BaseType_t ) -2 )
+#define tmrCOMMAND_EXECUTE_CALLBACK             ( ( BaseType_t ) -1 )
+#define tmrCOMMAND_START_DONT_TRACE             ( ( BaseType_t ) 0 )
+#define tmrCOMMAND_START                        ( ( BaseType_t ) 1 )
+#define tmrCOMMAND_RESET                        ( ( BaseType_t ) 2 )
+#define tmrCOMMAND_STOP                         ( ( BaseType_t ) 3 )
+#define tmrCOMMAND_CHANGE_PERIOD                ( ( BaseType_t ) 4 )
+#define tmrCOMMAND_DELETE                       ( ( BaseType_t ) 5 )
+
+#define tmrFIRST_FROM_ISR_COMMAND               ( ( BaseType_t ) 6 )
+#define tmrCOMMAND_START_FROM_ISR               ( ( BaseType_t ) 6 )
+#define tmrCOMMAND_RESET_FROM_ISR               ( ( BaseType_t ) 7 )
+#define tmrCOMMAND_STOP_FROM_ISR                ( ( BaseType_t ) 8 )
+#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR       ( ( BaseType_t ) 9 )
+
+
+/**
+ * Type by which software timers are referenced.  For example, a call to
+ * xTimerCreate() returns an TimerHandle_t variable that can then be used to
+ * reference the subject timer in calls to other software timer API functions
+ * (for example, xTimerStart(), xTimerReset(), etc.).
+ */
+struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+typedef struct tmrTimerControl * TimerHandle_t;
+
+/*
+ * Defines the prototype to which timer callback functions must conform.
+ */
+typedef void (* TimerCallbackFunction_t)( TimerHandle_t xTimer );
+
+/*
+ * Defines the prototype to which functions used with the
+ * xTimerPendFunctionCallFromISR() function must conform.
+ */
+typedef void (* PendedFunction_t)( void *,
+                                   uint32_t );
+
+/**
+ * TimerHandle_t xTimerCreate(  const char * const pcTimerName,
+ *                              TickType_t xTimerPeriodInTicks,
+ *                              UBaseType_t uxAutoReload,
+ *                              void * pvTimerID,
+ *                              TimerCallbackFunction_t pxCallbackFunction );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.  Time timer period must be greater than 0.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @return If the timer is successfully created then a handle to the newly
+ * created timer is returned.  If the timer cannot be created because there is
+ * insufficient FreeRTOS heap remaining to allocate the timer
+ * structures then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ * #define NUM_TIMERS 5
+ *
+ * // An array to hold handles to the created timers.
+ * TimerHandle_t xTimers[ NUM_TIMERS ];
+ *
+ * // An array to hold a count of the number of times each timer expires.
+ * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
+ *
+ * // Define a callback function that will be used by multiple timer instances.
+ * // The callback function does nothing but count the number of times the
+ * // associated timer expires, and stop the timer once the timer has expired
+ * // 10 times.
+ * void vTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * int32_t lArrayIndex;
+ * const int32_t xMaxExpiryCountBeforeStopping = 10;
+ *
+ *     // Optionally do something if the pxTimer parameter is NULL.
+ *     configASSERT( pxTimer );
+ *
+ *     // Which timer expired?
+ *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
+ *
+ *     // Increment the number of times that pxTimer has expired.
+ *     lExpireCounters[ lArrayIndex ] += 1;
+ *
+ *     // If the timer has expired 10 times then stop it from running.
+ *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
+ *     {
+ *         // Do not use a block time if calling a timer API function from a
+ *         // timer callback function, as doing so could cause a deadlock!
+ *         xTimerStop( pxTimer, 0 );
+ *     }
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start some timers.  Starting the timers before the scheduler
+ *     // has been started means the timers will start running immediately that
+ *     // the scheduler starts.
+ *     for( x = 0; x < NUM_TIMERS; x++ )
+ *     {
+ *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.
+ *                                         ( 100 * x ),   // The timer period in ticks.
+ *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.
+ *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.
+ *                                         vTimerCallback // Each timer calls the same callback when it expires.
+ *                                     );
+ *
+ *         if( xTimers[ x ] == NULL )
+ *         {
+ *             // The timer was not created.
+ *         }
+ *         else
+ *         {
+ *             // Start the timer.  No block time is specified, and even if one was
+ *             // it would be ignored because the scheduler has not yet been
+ *             // started.
+ *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
+ *             {
+ *                 // The timer could not be set into the Active state.
+ *             }
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                const TickType_t xTimerPeriodInTicks,
+                                const UBaseType_t uxAutoReload,
+                                void * const pvTimerID,
+                                TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
+ *                                  TickType_t xTimerPeriodInTicks,
+ *                                  UBaseType_t uxAutoReload,
+ *                                  void * pvTimerID,
+ *                                  TimerCallbackFunction_t pxCallbackFunction,
+ *                                  StaticTimer_t *pxTimerBuffer );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * https://www.FreeRTOS.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.  The timer period must be greater than 0.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
+ * will be then be used to hold the software timer's data structures, removing
+ * the need for the memory to be allocated dynamically.
+ *
+ * @return If the timer is created then a handle to the created timer is
+ * returned.  If pxTimerBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ * // The buffer used to hold the software timer's data structure.
+ * static StaticTimer_t xTimerBuffer;
+ *
+ * // A variable that will be incremented by the software timer's callback
+ * // function.
+ * UBaseType_t uxVariableToIncrement = 0;
+ *
+ * // A software timer callback function that increments a variable passed to
+ * // it when the software timer was created.  After the 5th increment the
+ * // callback function stops the software timer.
+ * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
+ * {
+ * UBaseType_t *puxVariableToIncrement;
+ * BaseType_t xReturned;
+ *
+ *     // Obtain the address of the variable to increment from the timer ID.
+ *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
+ *
+ *     // Increment the variable to show the timer callback has executed.
+ *     ( *puxVariableToIncrement )++;
+ *
+ *     // If this callback has executed the required number of times, stop the
+ *     // timer.
+ *     if( *puxVariableToIncrement == 5 )
+ *     {
+ *         // This is called from a timer callback so must not block.
+ *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
+ *     }
+ * }
+ *
+ *
+ * void main( void )
+ * {
+ *     // Create the software time.  xTimerCreateStatic() has an extra parameter
+ *     // than the normal xTimerCreate() API function.  The parameter is a pointer
+ *     // to the StaticTimer_t structure that will hold the software timer
+ *     // structure.  If the parameter is passed as NULL then the structure will be
+ *     // allocated dynamically, just as if xTimerCreate() had been called.
+ *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
+ *                                  xTimerPeriod,     // The period of the timer in ticks.
+ *                                  pdTRUE,           // This is an auto-reload timer.
+ *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
+ *                                  prvTimerCallback, // The function to execute when the timer expires.
+ *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
+ *
+ *     // The scheduler has not started yet so a block time is not used.
+ *     xReturned = xTimerStart( xTimer, 0 );
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                      const TickType_t xTimerPeriodInTicks,
+                                      const UBaseType_t uxAutoReload,
+                                      void * const pvTimerID,
+                                      TimerCallbackFunction_t pxCallbackFunction,
+                                      StaticTimer_t * pxTimerBuffer ) PRIVILEGED_FUNCTION;
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * void *pvTimerGetTimerID( TimerHandle_t xTimer );
+ *
+ * Returns the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer, and by calling the
+ * vTimerSetTimerID() API function.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return The ID assigned to the timer being queried.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void * pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+ *
+ * Sets the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being updated.
+ *
+ * @param pvNewID The ID to assign to the timer.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void vTimerSetTimerID( TimerHandle_t xTimer,
+                       void * pvNewID ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
+ *
+ * Queries a timer to see if it is active or dormant.
+ *
+ * A timer will be dormant if:
+ *     1) It has been created but not started, or
+ *     2) It is an expired one-shot timer that has not been restarted.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
+ * active state.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return pdFALSE will be returned if the timer is dormant.  A value other than
+ * pdFALSE will be returned if the timer is active.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is active, do something.
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, do something else.
+ *     }
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+ *
+ * Simply returns the handle of the timer service/daemon task.  It it not valid
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStart() starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerStart() has equivalent functionality
+ * to the xTimerReset() API function.
+ *
+ * Starting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerStart() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerStart() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerStart() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the start command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStart( xTimer, xTicksToWait ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStop() stops a timer that was previously started using either of the
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
+ *
+ * Stopping a timer ensures the timer is not in the active state.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the stop command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStop( xTimer, xTicksToWait ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerChangePeriod(   TimerHandle_t xTimer,
+ *                                  TickType_t xNewPeriod,
+ *                                  TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerChangePeriod() changes the period of a timer that was previously
+ * created using the xTimerCreate() API function.
+ *
+ * xTimerChangePeriod() can be called to change the period of an active or
+ * dormant state timer.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerChangePeriod() to be available.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the change period command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
+ * xTimerChangePeriod() is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the change period command could not be
+ * sent to the timer command queue even after xTicksToWait ticks had passed.
+ * pdPASS will be returned if the command was successfully sent to the timer
+ * command queue.  When the command is actually processed will depend on the
+ * priority of the timer service/daemon task relative to other tasks in the
+ * system.  The timer service/daemon task priority is set by the
+ * configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.  If the timer
+ * // referenced by xTimer is already active when it is called, then the timer
+ * // is deleted.  If the timer referenced by xTimer is not active when it is
+ * // called, then the period of the timer is set to 500ms and the timer is
+ * // started.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is already active - delete it.
+ *         xTimerDelete( xTimer );
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, change its period to 500ms.  This will also
+ *         // cause the timer to start.  Block for a maximum of 100 ticks if the
+ *         // change period command cannot immediately be sent to the timer
+ *         // command queue.
+ *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
+ *         {
+ *             // The command was successfully sent.
+ *         }
+ *         else
+ *         {
+ *             // The command could not be sent, even after waiting for 100 ticks
+ *             // to pass.  Take appropriate action here.
+ *         }
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerDelete() deletes a timer that was previously created using the
+ * xTimerCreate() API function.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerDelete() to be available.
+ *
+ * @param xTimer The handle of the timer being deleted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the delete command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
+ * is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the delete command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerChangePeriod() API function example usage scenario.
+ */
+#define xTimerDelete( xTimer, xTicksToWait ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerReset() re-starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerReset() will cause the timer to
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was
+ * called.  If the timer was in the dormant state then xTimerReset() has
+ * equivalent functionality to the xTimerStart() API function.
+ *
+ * Resetting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerReset() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerReset() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerReset() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being reset/started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the reset command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer.
+ *
+ * TimerHandle_t xBacklightTimer = NULL;
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press event handler.
+ * void vKeyPressEventHandler( char cKey )
+ * {
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
+ *     // if it cannot be sent immediately.
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start the one-shot timer that is responsible for turning
+ *     // the back-light off if no keys are pressed within a 5 second period.
+ *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
+ *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ *                                     pdFALSE,                    // The timer is a one-shot timer.
+ *                                     0,                          // The id is not used by the callback so can take any value.
+ *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
+ *                                   );
+ *
+ *     if( xBacklightTimer == NULL )
+ *     {
+ *         // The timer was not created.
+ *     }
+ *     else
+ *     {
+ *         // Start the timer.  No block time is specified, and even if one was
+ *         // it would be ignored because the scheduler has not yet been
+ *         // started.
+ *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
+ *         {
+ *             // The timer could not be set into the Active state.
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timer running as it has already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#define xTimerReset( xTimer, xTicksToWait ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStartFromISR(   TimerHandle_t xTimer,
+ *                                  BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStart() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStartFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerStartFromISR() is actually called.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then restart the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The start command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerStopFromISR(    TimerHandle_t xTimer,
+ *                                  BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStop() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStopFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the timer should be simply stopped.
+ *
+ * // The interrupt service routine that stops the timer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - simply stop the timer.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The stop command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
+ *                                       TickType_t xNewPeriod,
+ *                                       BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerChangePeriod() that can be called from an interrupt
+ * service routine.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
+ * timer command queue, so has the potential to transition the timer service/
+ * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
+ * causes the timer service/daemon task to leave the Blocked state, and the
+ * timer service/daemon task has a priority equal to or greater than the
+ * currently executing task (the task that was interrupted), then
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
+ * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
+ * this value to pdTRUE then a context switch should be performed before the
+ * interrupt exits.
+ *
+ * @return pdFAIL will be returned if the command to change the timers period
+ * could not be sent to the timer command queue.  pdPASS will be returned if the
+ * command was successfully sent to the timer command queue.  When the command
+ * is actually processed will depend on the priority of the timer service/daemon
+ * task relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.
+ *
+ * // The interrupt service routine that changes the period of xTimer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - change the period of xTimer to 500ms.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The command to change the timers period was not executed
+ *         // successfully.  Take appropriate action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerResetFromISR(   TimerHandle_t xTimer,
+ *                                  BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerReset() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer that is to be started, reset, or
+ * restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerResetFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) \
+    xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+
+/**
+ * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+ *                                          void *pvParameter1,
+ *                                          uint32_t ulParameter2,
+ *                                          BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ *
+ * Used from application interrupt service routines to defer the execution of a
+ * function to the RTOS daemon task (the timer service task, hence this function
+ * is implemented in timers.c and is prefixed with 'Timer').
+ *
+ * Ideally an interrupt service routine (ISR) is kept as short as possible, but
+ * sometimes an ISR either has a lot of processing to do, or needs to perform
+ * processing that is not deterministic.  In these cases
+ * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
+ * to the RTOS daemon task.
+ *
+ * A mechanism is provided that allows the interrupt to return directly to the
+ * task that will subsequently execute the pended callback function.  This
+ * allows the callback function to execute contiguously in time with the
+ * interrupt - just as if the callback had executed in the interrupt itself.
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task.  The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task (which is set using
+ * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
+ * the currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE within
+ * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ *  // The callback function that will execute in the context of the daemon task.
+ *  // Note callback functions must all use this same prototype.
+ *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
+ *  {
+ *      BaseType_t xInterfaceToService;
+ *
+ *      // The interface that requires servicing is passed in the second
+ *      // parameter.  The first parameter is not used in this case.
+ *      xInterfaceToService = ( BaseType_t ) ulParameter2;
+ *
+ *      // ...Perform the processing here...
+ *  }
+ *
+ *  // An ISR that receives data packets from multiple interfaces
+ *  void vAnISR( void )
+ *  {
+ *      BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
+ *
+ *      // Query the hardware to determine which interface needs processing.
+ *      xInterfaceToService = prvCheckInterfaces();
+ *
+ *      // The actual processing is to be deferred to a task.  Request the
+ *      // vProcessInterface() callback function is executed, passing in the
+ *      // number of the interface that needs processing.  The interface to
+ *      // service is passed in the second parameter.  The first parameter is
+ *      // not used in this case.
+ *      xHigherPriorityTaskWoken = pdFALSE;
+ *      xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
+ *
+ *      // If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *      // switch should be requested.  The macro used is port specific and will
+ *      // be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
+ *      // the documentation page for the port being used.
+ *      portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *
+ *  }
+ * @endverbatim
+ */
+BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+                                          void * pvParameter1,
+                                          uint32_t ulParameter2,
+                                          BaseType_t * pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+ *                                    void *pvParameter1,
+ *                                    uint32_t ulParameter2,
+ *                                    TickType_t xTicksToWait );
+ *
+ *
+ * Used to defer the execution of a function to the RTOS daemon task (the timer
+ * service task, hence this function is implemented in timers.c and is prefixed
+ * with 'Timer').
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task.  The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param xTicksToWait Calling this function will result in a message being
+ * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
+ * time the calling task should remain in the Blocked state (so not using any
+ * processing time) for space to become available on the timer queue if the
+ * queue is found to be full.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ */
+BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+                                   void * pvParameter1,
+                                   uint32_t ulParameter2,
+                                   TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * const char * const pcTimerGetName( TimerHandle_t xTimer );
+ *
+ * Returns the name that was assigned to a timer when the timer was created.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The name assigned to the timer specified by the xTimer parameter.
+ */
+const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );
+ *
+ * Updates a timer to be either an auto-reload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one-shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being updated.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the timer's period (see the
+ * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If
+ * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ */
+void vTimerSetReloadMode( TimerHandle_t xTimer,
+                          const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
+
+/**
+ * UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer );
+ *
+ * Queries a timer to determine if it is an auto-reload timer, in which case the timer
+ * automatically resets itself each time it expires, or a one-shot timer, in
+ * which case the timer will only expire once unless it is manually restarted.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return If the timer is an auto-reload timer then pdTRUE is returned, otherwise
+ * pdFALSE is returned.
+ */
+UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
+ *
+ * Returns the period of a timer.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The period of the timer in ticks.
+ */
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
+ *
+ * Returns the time in ticks at which the timer will expire.  If this is less
+ * than the current tick count then the expiry time has overflowed from the
+ * current time.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return If the timer is running then the time in ticks at which the timer
+ * will next expire is returned.  If the timer is not running then the return
+ * value is undefined.
+ */
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Functions beyond this part are not part of the public API and are intended
+ * for use by the kernel only.
+ */
+BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer,
+                                 const BaseType_t xCommandID,
+                                 const TickType_t xOptionalValue,
+                                 BaseType_t * const pxHigherPriorityTaskWoken,
+                                 const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+    void vTimerSetTimerNumber( TimerHandle_t xTimer,
+                               UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
+    UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+    /**
+     * task.h
+     * <pre>void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer, StackType_t ** ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize ) </pre>
+     * 
+     * This function is used to provide a statically allocated block of memory to FreeRTOS to hold the Timer Task TCB.  This function is required when 
+     * configSUPPORT_STATIC_ALLOCATION is set.  For more information see this URI: https://www.FreeRTOS.org/a00110.html#configSUPPORT_STATIC_ALLOCATION
+     * 
+     * @param ppxTimerTaskTCBBuffer   A handle to a statically allocated TCB buffer
+     * @param ppxTimerTaskStackBuffer A handle to a statically allocated Stack buffer for thie idle task
+     * @param pulTimerTaskStackSize   A pointer to the number of elements that will fit in the allocated stack buffer
+     */
+    void vApplicationGetTimerTaskMemory( StaticTask_t ** ppxTimerTaskTCBBuffer,
+                                          StackType_t ** ppxTimerTaskStackBuffer,
+                                              uint32_t * pulTimerTaskStackSize );
+
+#endif
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+#endif /* TIMERS_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/list.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/list.c
new file mode 100644
index 0000000..17a4e90
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/list.c
@@ -0,0 +1,210 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "list.h"
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+ * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be
+ * defined for the header files above, but not in this file, in order to
+ * generate the correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/*-----------------------------------------------------------
+* PUBLIC LIST API documented in list.h
+*----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+    /* The list structure contains a list item which is used to mark the
+     * end of the list.  To initialise the list the list end is inserted
+     * as the only list entry. */
+    pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+    /* The list end value is the highest possible value in the list to
+     * ensure it remains at the end of the list. */
+    pxList->xListEnd.xItemValue = portMAX_DELAY;
+
+    /* The list end next and previous pointers point to itself so we know
+     * when the list is empty. */
+    pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );     /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+    pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+    pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+
+    /* Write known values into the list if
+     * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+    listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+    listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+}
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+    /* Make sure the list item is not recorded as being on a list. */
+    pxItem->pxContainer = NULL;
+
+    /* Write known values into the list item if
+     * configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+    listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+    listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+}
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList,
+                     ListItem_t * const pxNewListItem )
+{
+    ListItem_t * const pxIndex = pxList->pxIndex;
+
+    /* Only effective when configASSERT() is also defined, these tests may catch
+     * the list data structures being overwritten in memory.  They will not catch
+     * data errors caused by incorrect configuration or use of FreeRTOS. */
+    listTEST_LIST_INTEGRITY( pxList );
+    listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+    /* Insert a new list item into pxList, but rather than sort the list,
+     * makes the new list item the last item to be removed by a call to
+     * listGET_OWNER_OF_NEXT_ENTRY(). */
+    pxNewListItem->pxNext = pxIndex;
+    pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+
+    /* Only used during decision coverage testing. */
+    mtCOVERAGE_TEST_DELAY();
+
+    pxIndex->pxPrevious->pxNext = pxNewListItem;
+    pxIndex->pxPrevious = pxNewListItem;
+
+    /* Remember which list the item is in. */
+    pxNewListItem->pxContainer = pxList;
+
+    ( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList,
+                  ListItem_t * const pxNewListItem )
+{
+    ListItem_t * pxIterator;
+    const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+
+    /* Only effective when configASSERT() is also defined, these tests may catch
+     * the list data structures being overwritten in memory.  They will not catch
+     * data errors caused by incorrect configuration or use of FreeRTOS. */
+    listTEST_LIST_INTEGRITY( pxList );
+    listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+    /* Insert the new list item into the list, sorted in xItemValue order.
+     *
+     * If the list already contains a list item with the same item value then the
+     * new list item should be placed after it.  This ensures that TCBs which are
+     * stored in ready lists (all of which have the same xItemValue value) get a
+     * share of the CPU.  However, if the xItemValue is the same as the back marker
+     * the iteration loop below will not end.  Therefore the value is checked
+     * first, and the algorithm slightly modified if necessary. */
+    if( xValueOfInsertion == portMAX_DELAY )
+    {
+        pxIterator = pxList->xListEnd.pxPrevious;
+    }
+    else
+    {
+        /* *** NOTE ***********************************************************
+        *  If you find your application is crashing here then likely causes are
+        *  listed below.  In addition see https://www.FreeRTOS.org/FAQHelp.html for
+        *  more tips, and ensure configASSERT() is defined!
+        *  https://www.FreeRTOS.org/a00110.html#configASSERT
+        *
+        *   1) Stack overflow -
+        *      see https://www.FreeRTOS.org/Stacks-and-stack-overflow-checking.html
+        *   2) Incorrect interrupt priority assignment, especially on Cortex-M
+        *      parts where numerically high priority values denote low actual
+        *      interrupt priorities, which can seem counter intuitive.  See
+        *      https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html and the definition
+        *      of configMAX_SYSCALL_INTERRUPT_PRIORITY on
+        *      https://www.FreeRTOS.org/a00110.html
+        *   3) Calling an API function from within a critical section or when
+        *      the scheduler is suspended, or calling an API function that does
+        *      not end in "FromISR" from an interrupt.
+        *   4) Using a queue or semaphore before it has been initialised or
+        *      before the scheduler has been started (are interrupts firing
+        *      before vTaskStartScheduler() has been called?).
+        **********************************************************************/
+
+        for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
+        {
+            /* There is nothing to do here, just iterating to the wanted
+             * insertion position. */
+        }
+    }
+
+    pxNewListItem->pxNext = pxIterator->pxNext;
+    pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+    pxNewListItem->pxPrevious = pxIterator;
+    pxIterator->pxNext = pxNewListItem;
+
+    /* Remember which list the item is in.  This allows fast removal of the
+     * item later. */
+    pxNewListItem->pxContainer = pxList;
+
+    ( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+/* The list item knows which list it is in.  Obtain the list from the list
+ * item. */
+    List_t * const pxList = pxItemToRemove->pxContainer;
+
+    pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+    pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+
+    /* Only used during decision coverage testing. */
+    mtCOVERAGE_TEST_DELAY();
+
+    /* Make sure the index is left pointing to a valid item. */
+    if( pxList->pxIndex == pxItemToRemove )
+    {
+        pxList->pxIndex = pxItemToRemove->pxPrevious;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    pxItemToRemove->pxContainer = NULL;
+    ( pxList->uxNumberOfItems )--;
+
+    return pxList->uxNumberOfItems;
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMClang/Use-the-GCC-ports.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMClang/Use-the-GCC-ports.txt
new file mode 100644
index 0000000..4a23ecd
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMClang/Use-the-GCC-ports.txt
@@ -0,0 +1,2 @@
+The FreeRTOS GCC port layer also builds and works with the ARMClang compiler.
+To use the ARMClang compiler build the port files from FreeRTOS/Source/portable/GCC.
\ No newline at end of file
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/ReadMe.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/ReadMe.txt
new file mode 100644
index 0000000..0bb046a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/ReadMe.txt
@@ -0,0 +1,10 @@
+This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
+Do not use the files located here!  These file are copied into separate
+FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
+FreeRTOS release.
+
+If your Cortex-M33 application uses TrustZone then use the files from the
+FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
+
+If your Cortex-M33 application does not use TrustZone then use the files from
+the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/copy_files.py b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/copy_files.py
new file mode 100644
index 0000000..73252e8
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/copy_files.py
@@ -0,0 +1,103 @@
+#/*
+# * FreeRTOS Kernel V10.4.3
+# * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+# *
+# * Permission is hereby granted, free of charge, to any person obtaining a copy of
+# * this software and associated documentation files (the "Software"), to deal in
+# * the Software without restriction, including without limitation the rights to
+# * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+# * the Software, and to permit persons to whom the Software is furnished to do so,
+# * subject to the following conditions:
+# *
+# * The above copyright notice and this permission notice shall be included in all
+# * copies or substantial portions of the Software.
+# *
+# * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+# * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+# * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+# * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+# * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+# *
+# * https://www.FreeRTOS.org
+# * https://github.com/FreeRTOS
+# *
+# * 1 tab == 4 spaces!
+# */
+
+import os
+import shutil
+
+_THIS_FILE_DIRECTORY_ = os.path.dirname(os.path.realpath(__file__))
+_FREERTOS_PORTABLE_DIRECTORY_ = os.path.dirname(_THIS_FILE_DIRECTORY_)
+
+_COMPILERS_ = ['GCC', 'IAR']
+_ARCH_NS_ = ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']
+_ARCH_S_ = ['ARM_CM33', 'ARM_CM23']
+
+_SUPPORTED_CONFIGS_ =   {
+                            'GCC' : ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ'],
+                            'IAR' : ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']
+                        }
+
+# Files to be complied in the Secure Project
+_SECURE_FILE_PATHS_ = [
+    os.path.join('secure', 'context'),
+    os.path.join('secure', 'context', 'portable', '_COMPILER_ARCH_'),
+    os.path.join('secure', 'heap'),
+    os.path.join('secure', 'init'),
+    os.path.join('secure', 'macros')
+]
+
+# Files to be complied in the Non-Secure Project
+_NONSECURE_FILE_PATHS_ = [
+    'non_secure',
+    os.path.join('non_secure', 'portable', '_COMPILER_ARCH_')
+]
+
+
+def is_supported_config(compiler, arch):
+    return arch in _SUPPORTED_CONFIGS_[compiler]
+
+
+def copy_files_in_dir(src_abs_path, dst_abs_path):
+    for src_file in os.listdir(src_abs_path):
+        src_file_abs_path = os.path.join(src_abs_path, src_file)
+        if os.path.isfile(src_file_abs_path) and src_file != 'ReadMe.txt':
+            if not os.path.exists(dst_abs_path):
+                os.makedirs(dst_abs_path)
+            print('Copying {}...'.format(os.path.basename(src_file_abs_path)))
+            shutil.copy2(src_file_abs_path, dst_abs_path)
+
+
+def copy_files_for_compiler_and_arch(compiler, arch, src_paths, dst_path):
+    _COMPILER_ARCH_ = os.path.join(compiler, arch)
+    for src_path in src_paths:
+        src_path_sanitized = src_path.replace('_COMPILER_ARCH_', _COMPILER_ARCH_ )
+
+        src_abs_path = os.path.join(_THIS_FILE_DIRECTORY_, src_path_sanitized)
+        dst_abs_path = os.path.join(_FREERTOS_PORTABLE_DIRECTORY_, _COMPILER_ARCH_, dst_path)
+
+        copy_files_in_dir(src_abs_path, dst_abs_path)
+
+
+def copy_files():
+    # Copy Secure Files
+    for compiler in _COMPILERS_:
+        for arch in _ARCH_S_:
+            if is_supported_config(compiler, arch):
+                copy_files_for_compiler_and_arch(compiler, arch, _SECURE_FILE_PATHS_, 'secure')
+
+    # Copy Non-Secure Files
+    for compiler in _COMPILERS_:
+        for arch in _ARCH_NS_:
+            if is_supported_config(compiler, arch):
+                copy_files_for_compiler_and_arch(compiler, arch, _NONSECURE_FILE_PATHS_, 'non_secure')
+
+
+def main():
+    copy_files()
+
+
+if __name__ == '__main__':
+    main()
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/ReadMe.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/ReadMe.txt
new file mode 100644
index 0000000..994d937
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/ReadMe.txt
@@ -0,0 +1,11 @@
+This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
+Do not use the files located here!  These file are copied into separate
+FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
+FreeRTOS release.
+
+If your Cortex-M33 application uses TrustZone then use the files from the
+FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
+
+If your Cortex-M33 application does not use TrustZone then use the files from
+the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/port.c
new file mode 100644
index 0000000..b4639df
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/port.c
@@ -0,0 +1,1192 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if ( configENABLE_TRUSTZONE == 1 )
+    /* Secure components includes. */
+    #include "secure_context.h"
+    #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
+#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ            configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT          ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the
+ * same a the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE    ( 3UL )
+#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS      ( 20UL )
+#define portCPACR_CP11_POS      ( 22UL )
+
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS     ( 31UL )
+#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS     ( 30UL )
+#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS                ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS                ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS                ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS                ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS                ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS                ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS                ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS                ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE           ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The maximum 24-bit number.
+ *
+ * It is needed because the systick is a 24-bit counter.
+ */
+#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )
+
+/**
+ * @brief A fiddle factor to estimate the number of SysTick counts that would
+ * have occurred while the SysTick counter is stopped during tickless idle
+ * calculations.
+ */
+#define portMISSED_COUNTS_FACTOR    ( 45UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR    ( 0x01000000 )
+
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         FD
+ * 1111 1111  1111 1111  1111 1111  1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
+#else
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         BC
+ * 1111 1111  1111 1111  1111 1111  1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS    1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT    0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+
+/**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ *
+ * The implementation in this file is weak to allow application writers to
+ * change the timer used to generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether the current execution context is interrupt.
+ *
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE
+ * otherwise.
+ */
+BaseType_t xPortIsInsideInterrupt( void );
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+/**
+ * @brief The number of SysTick increments that make up one tick period.
+ */
+    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
+
+/**
+ * @brief The maximum number of tick periods that can be suppressed is
+ * limited by the 24 bit resolution of the SysTick timer.
+ */
+    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
+
+/**
+ * @brief Compensate for the CPU cycles that pass while the SysTick is
+ * stopped (low power functionality only).
+ */
+    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily. The time the SysTick is stopped for is
+         * accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods. -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm volatile ( "cpsid i" ::: "memory" );
+        __asm volatile ( "dsb" );
+        __asm volatile ( "isb" );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be un-suspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above the cpsid instruction()
+             * above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation
+             * contains its own wait for interrupt or wait for event
+             * instruction, and so wfi should not be executed again. However,
+             * the original expected idle time variable must remain unmodified,
+             * so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm volatile ( "dsb" ::: "memory" );
+                __asm volatile ( "wfi" );
+                __asm volatile ( "isb" );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately. See comments above
+             * the cpsid instruction above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will
+             * increase any slippage between the time maintained by the RTOS and
+             * calendar time. */
+            __asm volatile ( "cpsid i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
+             * Again, the time the SysTick is stopped for is accounted for as
+             * best it can be, but using the tickless mode will inevitably
+             * result in some tiny drift of the time maintained by the kernel
+             * with respect to calendar time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is
+             * yet to count to zero (in which case an interrupt other than the
+             * SysTick must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is
+                 * stepped forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+    }
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and reset the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    volatile uint32_t ulDummy = 0UL;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to. If a task wants to exit it
+     * should instead call vTaskDelete( NULL ). Artificially force an assert()
+     * to be triggered if configASSERT() is defined, then stop here so
+     * application writers can catch the error. */
+    configASSERT( ulCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being
+         * defined but never called.  ulDummy is used purely to quieten other
+         * warnings about code appearing after this function is called - making
+         * ulDummy volatile makes the compiler think the function could return
+         * and therefore not output an 'unreachable code' warning for code that
+         * appears after it. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __unprivileged_flash_start__;
+            extern uint32_t * __unprivileged_flash_end__;
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else /* if defined( __ARMCC_VERSION ) */
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __unprivileged_flash_start__[];
+            extern uint32_t __unprivileged_flash_end__[];
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Check that the MPU is present. */
+        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+        {
+            /* MAIR0 - Index 0. */
+            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+            /* MAIR0 - Index 1. */
+            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+            /* Setup privileged flash as Read Only so that privileged tasks can
+             * read it but not modify. */
+            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged flash as Read Only by both privileged and
+             * unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged syscalls flash as Read Only by both privileged
+             * and unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup RAM containing kernel data for privileged access only. */
+            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                               ( portMPU_REGION_EXECUTE_NEVER );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Enable mem fault. */
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
+
+            /* Enable MPU with privileged background access i.e. unmapped
+             * regions have privileged access. */
+            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_FPU == 1 )
+    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                /* Enable non-secure access to the FPU. */
+                SecureInit_EnableNSFPUAccess();
+            }
+        #endif /* configENABLE_TRUSTZONE */
+
+        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+         * unprivileged code should be able to access FPU. CP11 should be
+         * programmed to the same value as CP10. */
+        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+                            );
+
+        /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+         * context on exception entry and restore on exception return.
+         * LSPEN = 1 ==> Enable lazy context save of FP state. */
+        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+    }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Set a PendSV to request a context switch. */
+    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    portDISABLE_INTERRUPTS();
+    ulCriticalNesting++;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    configASSERT( ulCriticalNesting );
+    ulCriticalNesting--;
+
+    if( ulCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+    uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+    #if ( configENABLE_MPU == 1 )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+    #endif /* configENABLE_MPU */
+
+    uint32_t ulPC;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        uint32_t ulR0;
+        #if ( configENABLE_MPU == 1 )
+            uint32_t ulControl, ulIsTaskPrivileged;
+        #endif /* configENABLE_MPU */
+    #endif /* configENABLE_TRUSTZONE */
+    uint8_t ucSVCNumber;
+
+    /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+     * R12, LR, PC, xPSR. */
+    ulPC = pulCallerStackAddress[ 6 ];
+    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            case portSVC_ALLOCATE_SECURE_CONTEXT:
+
+                /* R0 contains the stack size passed as parameter to the
+                 * vPortAllocateSecureContext function. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                #if ( configENABLE_MPU == 1 )
+                    {
+                        /* Read the CONTROL register value. */
+                        __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+                        /* The task that raised the SVC is privileged if Bit[0]
+                         * in the CONTROL register is 0. */
+                        ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+                    }
+                #else /* if ( configENABLE_MPU == 1 ) */
+                    {
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0 );
+                    }
+                #endif /* configENABLE_MPU */
+
+                configASSERT( xSecureContext != NULL );
+                SecureContext_LoadContext( xSecureContext );
+                break;
+
+            case portSVC_FREE_SECURE_CONTEXT:
+                /* R0 contains the secure context handle to be freed. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                /* Free the secure context. */
+                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+                break;
+        #endif /* configENABLE_TRUSTZONE */
+
+        case portSVC_START_SCHEDULER:
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    /* De-prioritize the non-secure exceptions so that the
+                     * non-secure pendSV runs at the lowest priority. */
+                    SecureInit_DePrioritizeNSExceptions();
+
+                    /* Initialize the secure context management system. */
+                    SecureContext_Init();
+                }
+            #endif /* configENABLE_TRUSTZONE */
+
+            #if ( configENABLE_FPU == 1 )
+                {
+                    /* Setup the Floating Point Unit (FPU). */
+                    prvSetupFPU();
+                }
+            #endif /* configENABLE_FPU */
+
+            /* Setup the context of the first task so that the first task starts
+             * executing. */
+            vRestoreContextOfFirstTask();
+            break;
+
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_RAISE_PRIVILEGE:
+
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* configENABLE_MPU */
+
+        default:
+            /* Incorrect SVC call. */
+            configASSERT( pdFALSE );
+    }
+}
+/*-----------------------------------------------------------*/
+/* *INDENT-OFF* */
+#if ( configENABLE_MPU == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+/* *INDENT-ON* */
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    #if ( portPRELOAD_REGISTERS == 0 )
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #else /* portPRELOAD_REGISTERS */
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #endif /* portPRELOAD_REGISTERS */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    #if ( configENABLE_MPU == 1 )
+        {
+            /* Setup the Memory Protection Unit (MPU). */
+            prvSetupMPU();
+        }
+    #endif /* configENABLE_MPU */
+
+    /* Start the timer that generates the tick ISR. Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialize the critical nesting count ready for the first task. */
+    ulCriticalNesting = 0;
+
+    /* Start the first task. */
+    vStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing. Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. Call
+     * vTaskSwitchContext() so link time optimization does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here. */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    uint32_t ulStackDepth )
+    {
+        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+        int32_t lIndex = 0;
+
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Setup MAIR0. */
+        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid.  At all other
+         * times the stack parameters will not be valid and it is assumed that
+         * the stack region has already been configured. */
+        if( ulStackDepth > 0 )
+        {
+            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+
+            /* If the stack is within the privileged SRAM, do not protect it
+             * using a separate MPU region. This is needed because privileged
+             * SRAM is already protected using an MPU region and ARMv8-M does
+             * not allow overlapping MPU regions. */
+            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
+            {
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
+            }
+            else
+            {
+                /* Define the region that allows access to the stack. */
+                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+                                                             ( portMPU_REGION_NON_SHAREABLE ) |
+                                                             ( portMPU_REGION_READ_WRITE ) |
+                                                             ( portMPU_REGION_EXECUTE_NEVER );
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                                             ( portMPU_RLAR_REGION_ENABLE );
+            }
+        }
+
+        /* User supplied configurable regions. */
+        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+        {
+            /* If xRegions is NULL i.e. the task has not specified any MPU
+             * region, the else part ensures that all the configurable MPU
+             * regions are invalidated. */
+            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+            {
+                /* Translate the generic region definition contained in xRegions
+                 * into the ARMv8 specific MPU settings that are then stored in
+                 * xMPUSettings. */
+                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                /* Start address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+                                                                          ( portMPU_REGION_NON_SHAREABLE );
+
+                /* RO/RW. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+                }
+                else
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+                }
+
+                /* XN. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+                }
+
+                /* End Address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+                                                                          ( portMPU_RLAR_REGION_ENABLE );
+
+                /* Normal memory/ Device memory. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+                {
+                    /* Attr1 in MAIR0 is configured as device memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+                }
+                else
+                {
+                    /* Attr1 in MAIR0 is configured as normal memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+                }
+            }
+            else
+            {
+                /* Invalidate the region. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+            }
+
+            lIndex++;
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. Interrupt Program
+     * Status Register (IPSR) holds the exception number of the currently-executing
+     * exception or zero for Thread mode.*/
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
new file mode 100644
index 0000000..5276d8f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
@@ -0,0 +1,453 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configENABLE_FPU == 1 )
+    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr  r2, pxCurrentTCBConst2						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr  r3, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr  r0, [r3]									\n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r5, #1										\n"/* r5 = 1. */
+            "	bics r4, r5										\n"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+            "	ldr  r4, [r3]									\n"/* r4 = *r3 i.e. r4 = MAIR0. */
+            "	ldr  r2, xMAIR0Const2							\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str  r4, [r2]									\n"/* Program MAIR0. */
+            "	ldr  r2, xRNRConst2								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+            "	movs r5, #4										\n"/* r5 = 4. */
+            "	str  r5, [r2]									\n"/* Program RNR = 4. */
+            "	ldmia r3!, {r6,r7}								\n"/* Read first set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst2							\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}								\n"/* Write first set of RBAR/RLAR registers. */
+            "	movs r5, #5										\n"/* r5 = 5. */
+            "	str  r5, [r2]									\n"/* Program RNR = 5. */
+            "	ldmia r3!, {r6,r7}								\n"/* Read second set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst2							\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}								\n"/* Write second set of RBAR/RLAR registers. */
+            "	movs r5, #6										\n"/* r5 = 6. */
+            "	str  r5, [r2]									\n"/* Program RNR = 6. */
+            "	ldmia r3!, {r6,r7}								\n"/* Read third set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst2							\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}								\n"/* Write third set of RBAR/RLAR registers. */
+            "	movs r5, #7										\n"/* r5 = 7. */
+            "	str  r5, [r2]									\n"/* Program RNR = 7. */
+            "	ldmia r3!, {r6,r7}								\n"/* Read fourth set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst2							\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}								\n"/* Write fourth set of RBAR/RLAR registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r5, #1										\n"/* r5 = 1. */
+            "	orrs r4, r5										\n"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldm  r0!, {r1-r4}								\n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+            "	ldr  r5, xSecureContextConst2					\n"
+            "	str  r1, [r5]									\n"/* Set xSecureContext to this task's value for the same. */
+            "	msr  psplim, r2									\n"/* Set this task's PSPLIM value. */
+            "	msr  control, r3								\n"/* Set this task's CONTROL value. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	bx   r4											\n"/* Finally, branch to EXC_RETURN. */
+        #else /* configENABLE_MPU */
+            "	ldm  r0!, {r1-r3}								\n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+            "	ldr  r4, xSecureContextConst2					\n"
+            "	str  r1, [r4]									\n"/* Set xSecureContext to this task's value for the same. */
+            "	msr  psplim, r2									\n"/* Set this task's PSPLIM value. */
+            "	movs r1, #2										\n"/* r1 = 2. */
+            "	msr  CONTROL, r1								\n"/* Switch to use PSP in the thread mode. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	bx   r3											\n"/* Finally, branch to EXC_RETURN. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+        "xSecureContextConst2: .word xSecureContext			\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst2: .word 0xe000ed94					\n"
+            "xMAIR0Const2: .word 0xe000edc0						\n"
+            "xRNRConst2: .word 0xe000ed98						\n"
+            "xRBARConst2: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	tst r0, r1										\n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+        "	beq running_privileged							\n"/* If the result of previous AND operation was 0, branch. */
+        "	movs r0, #0										\n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "	bx lr											\n"/* Return. */
+        " running_privileged:								\n"
+        "	movs r0, #1										\n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "	bx lr											\n"/* Return. */
+        "													\n"
+        "	.align 4										\n"
+        ::: "r0", "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* Read the CONTROL register. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	bics r0, r1										\n"/* Clear the bit 0. */
+        "	msr control, r0									\n"/* Write back the new CONTROL value. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	orrs r0, r1										\n"/* r0 = r0 | r1. */
+        "	msr control, r0									\n"/* CONTROL = r0. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	ldr r0, xVTORConst								\n"/* Use the NVIC offset register to locate the stack. */
+        "	ldr r0, [r0]									\n"/* Read the VTOR register which gives the address of vector table. */
+        "	ldr r0, [r0]									\n"/* The first entry in vector table is stack pointer. */
+        "	msr msp, r0										\n"/* Set the MSP back to the start of the stack. */
+        "	cpsie i											\n"/* Globally enable interrupts. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	svc %0											\n"/* System call to start the first task. */
+        "	nop												\n"
+        "													\n"
+        "   .align 4										\n"
+        "xVTORConst: .word 0xe000ed08						\n"
+        ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	mrs r0, PRIMASK									\n"
+        "	cpsid i											\n"
+        "	bx lr											\n"
+        ::: "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	msr PRIMASK, r0									\n"
+        "	bx lr											\n"
+        ::: "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "	.extern SecureContext_SaveContext				\n"
+        "	.extern SecureContext_LoadContext				\n"
+        "													\n"
+        "	mrs r1, psp										\n"/* Read PSP in r1. */
+        "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+        "	ldr r0, [r2]									\n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+        "													\n"
+        "	cbz r0, save_ns_context							\n"/* No secure context to save. */
+        "	push {r0-r2, r14}								\n"
+        "	bl SecureContext_SaveContext					\n"
+        "	pop {r0-r3}										\n"/* LR is now in r3. */
+        "	mov lr, r3										\n"/* LR = r3. */
+        "	lsls r2, r3, #25								\n"/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        "	bpl save_ns_context								\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r2, [r3]									\n"/* Read pxCurrentTCB. */
+        #if ( configENABLE_MPU == 1 )
+            "	subs r1, r1, #16								\n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mrs r3, control									\n"/* r3 = CONTROL. */
+            "	mov r4, lr										\n"/* r4 = LR/EXC_RETURN. */
+            "	stmia r1!, {r0, r2-r4}							\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+        #else /* configENABLE_MPU */
+            "	subs r1, r1, #12								\n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmia r1!, {r0, r2-r3}							\n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+        #endif /* configENABLE_MPU */
+        "	b select_next_task								\n"
+        "													\n"
+        " save_ns_context:									\n"
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r2, [r3]									\n"/* Read pxCurrentTCB. */
+        #if ( configENABLE_MPU == 1 )
+            "	subs r1, r1, #48								\n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	adds r1, r1, #16								\n"/* r1 = r1 + 16. */
+            "	stmia r1!, {r4-r7}								\n"/* Store the low registers that are not saved automatically. */
+            "	mov r4, r8										\n"/* r4 = r8. */
+            "	mov r5, r9										\n"/* r5 = r9. */
+            "	mov r6, r10										\n"/* r6 = r10. */
+            "	mov r7, r11										\n"/* r7 = r11. */
+            "	stmia r1!, {r4-r7}								\n"/* Store the high registers that are not saved automatically. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mrs r3, control									\n"/* r3 = CONTROL. */
+            "	mov r4, lr										\n"/* r4 = LR/EXC_RETURN. */
+            "	subs r1, r1, #48								\n"/* r1 = r1 - 48. */
+            "	stmia r1!, {r0, r2-r4}							\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+        #else /* configENABLE_MPU */
+            "	subs r1, r1, #44								\n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmia r1!, {r0, r2-r7}							\n"/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+            "	mov r4, r8										\n"/* r4 = r8. */
+            "	mov r5, r9										\n"/* r5 = r9. */
+            "	mov r6, r10										\n"/* r6 = r10. */
+            "	mov r7, r11										\n"/* r7 = r11. */
+            "	stmia r1!, {r4-r7}								\n"/* Store the high registers that are not saved automatically. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        " select_next_task:									\n"
+        "	cpsid i											\n"
+        "	bl vTaskSwitchContext							\n"
+        "	cpsie i											\n"
+        "													\n"
+        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r3, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr r1, [r3]									\n"/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r5, #1										\n"/* r5 = 1. */
+            "	bics r4, r5										\n"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+            "	ldr r4, [r3]									\n"/* r4 = *r3 i.e. r4 = MAIR0. */
+            "	ldr r2, xMAIR0Const								\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str r4, [r2]									\n"/* Program MAIR0. */
+            "	ldr r2, xRNRConst								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+            "	movs r5, #4										\n"/* r5 = 4. */
+            "	str  r5, [r2]									\n"/* Program RNR = 4. */
+            "	ldmia r3!, {r6,r7}								\n"/* Read first set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst								\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}								\n"/* Write first set of RBAR/RLAR registers. */
+            "	movs r5, #5										\n"/* r5 = 5. */
+            "	str  r5, [r2]									\n"/* Program RNR = 5. */
+            "	ldmia r3!, {r6,r7}								\n"/* Read second set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst								\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}								\n"/* Write second set of RBAR/RLAR registers. */
+            "	movs r5, #6										\n"/* r5 = 6. */
+            "	str  r5, [r2]									\n"/* Program RNR = 6. */
+            "	ldmia r3!, {r6,r7}								\n"/* Read third set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst								\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}								\n"/* Write third set of RBAR/RLAR registers. */
+            "	movs r5, #7										\n"/* r5 = 7. */
+            "	str  r5, [r2]									\n"/* Program RNR = 7. */
+            "	ldmia r3!, {r6,r7}								\n"/* Read fourth set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst								\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}								\n"/* Write fourth set of RBAR/RLAR registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r5, #1										\n"/* r5 = 1. */
+            "	orrs r4, r5										\n"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldmia r1!, {r0, r2-r4}							\n"/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+            "	msr control, r3									\n"/* Restore the CONTROL register value for the task. */
+            "	mov lr, r4										\n"/* LR = r4. */
+            "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "	str r0, [r2]									\n"/* Restore the task's xSecureContext. */
+            "	cbz r0, restore_ns_context						\n"/* If there is no secure context for the task, restore the non-secure context. */
+            "	push {r1,r4}									\n"
+            "	bl SecureContext_LoadContext					\n"/* Restore the secure context. */
+            "	pop {r1,r4}										\n"
+            "	mov lr, r4										\n"/* LR = r4. */
+            "	lsls r2, r4, #25								\n"/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "	bpl restore_ns_context							\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+            "	bx lr											\n"
+        #else /* configENABLE_MPU */
+            "	ldmia r1!, {r0, r2-r3}							\n"/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+            "	mov lr, r3										\n"/* LR = r3. */
+            "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "	str r0, [r2]									\n"/* Restore the task's xSecureContext. */
+            "	cbz r0, restore_ns_context						\n"/* If there is no secure context for the task, restore the non-secure context. */
+            "	push {r1,r3}									\n"
+            "	bl SecureContext_LoadContext					\n"/* Restore the secure context. */
+            "	pop {r1,r3}										\n"
+            "	mov lr, r3										\n"/* LR = r3. */
+            "	lsls r2, r3, #25								\n"/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "	bpl restore_ns_context							\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+            "	bx lr											\n"
+        #endif /* configENABLE_MPU */
+        "													\n"
+        " restore_ns_context:								\n"
+        "	adds r1, r1, #16								\n"/* Move to the high registers. */
+        "	ldmia r1!, {r4-r7}								\n"/* Restore the high registers that are not automatically restored. */
+        "	mov r8, r4										\n"/* r8 = r4. */
+        "	mov r9, r5										\n"/* r9 = r5. */
+        "	mov r10, r6										\n"/* r10 = r6. */
+        "	mov r11, r7										\n"/* r11 = r7. */
+        "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+        "	subs r1, r1, #32								\n"/* Go back to the low registers. */
+        "	ldmia r1!, {r4-r7}								\n"/* Restore the low registers that are not automatically restored. */
+        "	bx lr											\n"
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB				\n"
+        "xSecureContextConst: .word xSecureContext			\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst: .word 0xe000ed94					\n"
+            "xMAIR0Const: .word 0xe000edc0						\n"
+            "xRNRConst: .word 0xe000ed98						\n"
+            "xRBARConst: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	movs r0, #4										\n"
+        "	mov r1, lr										\n"
+        "	tst r0, r1										\n"
+        "	beq stacking_used_msp							\n"
+        "	mrs r0, psp										\n"
+        "	ldr r2, svchandler_address_const				\n"
+        "	bx r2											\n"
+        " stacking_used_msp:								\n"
+        "	mrs r0, msp										\n"
+        "	ldr r2, svchandler_address_const				\n"
+        "	bx r2											\n"
+        "													\n"
+        "	.align 4										\n"
+        "svchandler_address_const: .word vPortSVCHandler_C	\n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	svc %0											\n"/* Secure context is allocated in the supervisor call. */
+        "	bx lr											\n"/* Return. */
+        ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	ldr r1, [r0]									\n"/* The first item in the TCB is the top of the stack. */
+        "	ldr r0, [r1]									\n"/* The first item on the stack is the task's xSecureContext. */
+        "	cmp r0, #0										\n"/* Raise svc if task's xSecureContext is not NULL. */
+        "	beq free_secure_context							\n"
+        "	bx lr											\n"/* There is no secure context (xSecureContext is NULL). */
+        " free_secure_context:								\n"
+        "	svc %0											\n"/* Secure context is freed in the supervisor call. */
+        "	bx lr											\n"/* Return. */
+        ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
new file mode 100644
index 0000000..61cd152
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
@@ -0,0 +1,312 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+    #ifndef configENABLE_FPU
+        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+    #endif /* configENABLE_FPU */
+
+    #ifndef configENABLE_MPU
+        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+    #endif /* configENABLE_MPU */
+
+    #ifndef configENABLE_TRUSTZONE
+        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+    #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+    #define portARCH_NAME                      "Cortex-M23"
+    #define portSTACK_GROWTH                   ( -1 )
+    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT                 8
+    #define portNOP()
+    #define portINLINE                         __inline
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+    #endif
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
+    #define portDONT_DISCARD                   __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+    extern BaseType_t xPortIsInsideInterrupt( void );
+
+    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+    #endif /* configENABLE_TRUSTZONE */
+
+    #if ( configENABLE_MPU == 1 )
+        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+    #if ( configENABLE_MPU == 1 )
+        #define portUSING_MPU_WRAPPERS    1
+        #define portPRIVILEGE_BIT         ( 0x80000000UL )
+    #else
+        #define portPRIVILEGE_BIT         ( 0x0UL )
+    #endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
+    #define portSTACK_REGION                              ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
+    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
+    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
+    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
+    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
+    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+    } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
+    #define portSVC_FREE_SECURE_CONTEXT        1
+    #define portSVC_START_SCHEDULER            2
+    #define portSVC_RAISE_PRIVILEGE            3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+    #define portYIELD()                                 vPortYield()
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+    #define portDISABLE_INTERRUPTS()                  __asm volatile ( " cpsid i " ::: "memory" )
+    #define portENABLE_INTERRUPTS()                   __asm volatile ( " cpsie i " ::: "memory" )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+    #else
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+        #define portCLEAN_UP_TCB( pxTCB )
+    #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+        #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+        #define portRESET_PRIVILEGE()    vResetPrivilege()
+    #else
+        #define portIS_PRIVILEGED()
+        #define portRAISE_PRIVILEGE()
+        #define portRESET_PRIVILEGE()
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
new file mode 100644
index 0000000..ef8f3e4
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
@@ -0,0 +1,366 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configENABLE_FPU == 1 )
+    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr  r2, pxCurrentTCBConst2						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr  r1, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr  r0, [r1]									\n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r3, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r4, #1										\n"/* r4 = 1. */
+            "	bics r3, r4										\n"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+            "	str r3, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+            "	ldr  r4, [r1]									\n"/* r4 = *r1 i.e. r4 = MAIR0. */
+            "	ldr  r2, xMAIR0Const2							\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str  r4, [r2]									\n"/* Program MAIR0. */
+            "	ldr  r2, xRNRConst2								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+            "	movs r4, #4										\n"/* r4 = 4. */
+            "	str  r4, [r2]									\n"/* Program RNR = 4. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read first set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst2							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write first set of RBAR/RLAR registers. */
+            "	movs r4, #5										\n"/* r4 = 5. */
+            "	str  r4, [r2]									\n"/* Program RNR = 5. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read second set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst2							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write second set of RBAR/RLAR registers. */
+            "	movs r4, #6										\n"/* r4 = 6. */
+            "	str  r4, [r2]									\n"/* Program RNR = 6. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read third set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst2							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write third set of RBAR/RLAR registers. */
+            "	movs r4, #7										\n"/* r4 = 7. */
+            "	str  r4, [r2]									\n"/* Program RNR = 7. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read fourth set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst2							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write fourth set of RBAR/RLAR registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r3, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r4, #1										\n"/* r4 = 1. */
+            "	orrs r3, r4										\n"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+            "	str r3, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldm  r0!, {r1-r3}								\n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+            "	msr  psplim, r1									\n"/* Set this task's PSPLIM value. */
+            "	msr  control, r2								\n"/* Set this task's CONTROL value. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	bx   r3											\n"/* Finally, branch to EXC_RETURN. */
+        #else /* configENABLE_MPU */
+            "	ldm  r0!, {r1-r2}								\n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+            "	msr  psplim, r1									\n"/* Set this task's PSPLIM value. */
+            "	movs r1, #2										\n"/* r1 = 2. */
+            "	msr  CONTROL, r1								\n"/* Switch to use PSP in the thread mode. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	bx   r2											\n"/* Finally, branch to EXC_RETURN. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst2: .word 0xe000ed94					\n"
+            "xMAIR0Const2: .word 0xe000edc0						\n"
+            "xRNRConst2: .word 0xe000ed98						\n"
+            "xRBARConst2: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	tst r0, r1										\n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+        "	beq running_privileged							\n"/* If the result of previous AND operation was 0, branch. */
+        "	movs r0, #0										\n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "	bx lr											\n"/* Return. */
+        " running_privileged:								\n"
+        "	movs r0, #1										\n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "	bx lr											\n"/* Return. */
+        "													\n"
+        "	.align 4										\n"
+        ::: "r0", "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	mrs  r0, control								\n"/* Read the CONTROL register. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	bics r0, r1										\n"/* Clear the bit 0. */
+        "	msr  control, r0								\n"/* Write back the new CONTROL value. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	orrs r0, r1										\n"/* r0 = r0 | r1. */
+        "	msr control, r0									\n"/* CONTROL = r0. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	ldr r0, xVTORConst								\n"/* Use the NVIC offset register to locate the stack. */
+        "	ldr r0, [r0]									\n"/* Read the VTOR register which gives the address of vector table. */
+        "	ldr r0, [r0]									\n"/* The first entry in vector table is stack pointer. */
+        "	msr msp, r0										\n"/* Set the MSP back to the start of the stack. */
+        "	cpsie i											\n"/* Globally enable interrupts. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	svc %0											\n"/* System call to start the first task. */
+        "	nop												\n"
+        "													\n"
+        "   .align 4										\n"
+        "xVTORConst: .word 0xe000ed08						\n"
+        ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	mrs r0, PRIMASK									\n"
+        "	cpsid i											\n"
+        "	bx lr											\n"
+        ::: "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	msr PRIMASK, r0									\n"
+        "	bx lr											\n"
+        ::: "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, psp										\n"/* Read PSP in r0. */
+        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r2]									\n"/* Read pxCurrentTCB. */
+        #if ( configENABLE_MPU == 1 )
+            "	subs r0, r0, #44								\n"/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+            "	str r0, [r1]									\n"/* Save the new top of stack in TCB. */
+            "	mrs r1, psplim									\n"/* r1 = PSPLIM. */
+            "	mrs r2, control									\n"/* r2 = CONTROL. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmia r0!, {r1-r7}								\n"/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
+            "	mov r4, r8										\n"/* r4 = r8. */
+            "	mov r5, r9										\n"/* r5 = r9. */
+            "	mov r6, r10										\n"/* r6 = r10. */
+            "	mov r7, r11										\n"/* r7 = r11. */
+            "	stmia r0!, {r4-r7}								\n"/* Store the high registers that are not saved automatically. */
+        #else /* configENABLE_MPU */
+            "	subs r0, r0, #40								\n"/* Make space for PSPLIM, LR and the remaining registers on the stack. */
+            "	str r0, [r1]									\n"/* Save the new top of stack in TCB. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmia r0!, {r2-r7}								\n"/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
+            "	mov r4, r8										\n"/* r4 = r8. */
+            "	mov r5, r9										\n"/* r5 = r9. */
+            "	mov r6, r10										\n"/* r6 = r10. */
+            "	mov r7, r11										\n"/* r7 = r11. */
+            "	stmia r0!, {r4-r7}								\n"/* Store the high registers that are not saved automatically. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	cpsid i											\n"
+        "	bl vTaskSwitchContext							\n"
+        "	cpsie i											\n"
+        "													\n"
+        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr r0, [r1]									\n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r3, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r4, #1										\n"/* r4 = 1. */
+            "	bics r3, r4										\n"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+            "	str r3, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+            "	ldr  r4, [r1]									\n"/* r4 = *r1 i.e. r4 = MAIR0. */
+            "	ldr  r2, xMAIR0Const							\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str  r4, [r2]									\n"/* Program MAIR0. */
+            "	ldr  r2, xRNRConst								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+            "	movs r4, #4										\n"/* r4 = 4. */
+            "	str  r4, [r2]									\n"/* Program RNR = 4. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read first set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst								\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write first set of RBAR/RLAR registers. */
+            "	movs r4, #5										\n"/* r4 = 5. */
+            "	str  r4, [r2]									\n"/* Program RNR = 5. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read second set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst								\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write second set of RBAR/RLAR registers. */
+            "	movs r4, #6										\n"/* r4 = 6. */
+            "	str  r4, [r2]									\n"/* Program RNR = 6. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read third set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst								\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write third set of RBAR/RLAR registers. */
+            "	movs r4, #7										\n"/* r4 = 7. */
+            "	str  r4, [r2]									\n"/* Program RNR = 7. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read fourth set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst								\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write fourth set of RBAR/RLAR registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r3, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r4, #1										\n"/* r4 = 1. */
+            "	orrs r3, r4										\n"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+            "	str r3, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	adds r0, r0, #28								\n"/* Move to the high registers. */
+            "	ldmia r0!, {r4-r7}								\n"/* Restore the high registers that are not automatically restored. */
+            "	mov r8, r4										\n"/* r8 = r4. */
+            "	mov r9, r5										\n"/* r9 = r5. */
+            "	mov r10, r6										\n"/* r10 = r6. */
+            "	mov r11, r7										\n"/* r11 = r7. */
+            "	msr psp, r0										\n"/* Remember the new top of stack for the task. */
+            "	subs r0, r0, #44								\n"/* Move to the starting of the saved context. */
+            "	ldmia r0!, {r1-r7}								\n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
+            "	msr psplim, r1									\n"/* Restore the PSPLIM register value for the task. */
+            "	msr control, r2									\n"/* Restore the CONTROL register value for the task. */
+            "	bx r3											\n"
+        #else /* configENABLE_MPU */
+            "	adds r0, r0, #24								\n"/* Move to the high registers. */
+            "	ldmia r0!, {r4-r7}								\n"/* Restore the high registers that are not automatically restored. */
+            "	mov r8, r4										\n"/* r8 = r4. */
+            "	mov r9, r5										\n"/* r9 = r5. */
+            "	mov r10, r6										\n"/* r10 = r6. */
+            "	mov r11, r7										\n"/* r11 = r7. */
+            "	msr psp, r0										\n"/* Remember the new top of stack for the task. */
+            "	subs r0, r0, #40								\n"/* Move to the starting of the saved context. */
+            "	ldmia r0!, {r2-r7}								\n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+            "	bx r3											\n"
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB				\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst: .word 0xe000ed94					\n"
+            "xMAIR0Const: .word 0xe000edc0						\n"
+            "xRNRConst: .word 0xe000ed98						\n"
+            "xRBARConst: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	movs r0, #4										\n"
+        "	mov r1, lr										\n"
+        "	tst r0, r1										\n"
+        "	beq stacking_used_msp							\n"
+        "	mrs r0, psp										\n"
+        "	ldr r2, svchandler_address_const				\n"
+        "	bx r2											\n"
+        " stacking_used_msp:								\n"
+        "	mrs r0, msp										\n"
+        "	ldr r2, svchandler_address_const				\n"
+        "	bx r2											\n"
+        "													\n"
+        "	.align 4										\n"
+        "svchandler_address_const: .word vPortSVCHandler_C	\n"
+    );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
new file mode 100644
index 0000000..61cd152
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
@@ -0,0 +1,312 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+    #ifndef configENABLE_FPU
+        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+    #endif /* configENABLE_FPU */
+
+    #ifndef configENABLE_MPU
+        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+    #endif /* configENABLE_MPU */
+
+    #ifndef configENABLE_TRUSTZONE
+        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+    #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+    #define portARCH_NAME                      "Cortex-M23"
+    #define portSTACK_GROWTH                   ( -1 )
+    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT                 8
+    #define portNOP()
+    #define portINLINE                         __inline
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+    #endif
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
+    #define portDONT_DISCARD                   __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+    extern BaseType_t xPortIsInsideInterrupt( void );
+
+    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+    #endif /* configENABLE_TRUSTZONE */
+
+    #if ( configENABLE_MPU == 1 )
+        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+    #if ( configENABLE_MPU == 1 )
+        #define portUSING_MPU_WRAPPERS    1
+        #define portPRIVILEGE_BIT         ( 0x80000000UL )
+    #else
+        #define portPRIVILEGE_BIT         ( 0x0UL )
+    #endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
+    #define portSTACK_REGION                              ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
+    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
+    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
+    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
+    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
+    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+    } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
+    #define portSVC_FREE_SECURE_CONTEXT        1
+    #define portSVC_START_SCHEDULER            2
+    #define portSVC_RAISE_PRIVILEGE            3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+    #define portYIELD()                                 vPortYield()
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+    #define portDISABLE_INTERRUPTS()                  __asm volatile ( " cpsid i " ::: "memory" )
+    #define portENABLE_INTERRUPTS()                   __asm volatile ( " cpsie i " ::: "memory" )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+    #else
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+        #define portCLEAN_UP_TCB( pxTCB )
+    #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+        #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+        #define portRESET_PRIVILEGE()    vResetPrivilege()
+    #else
+        #define portIS_PRIVILEGED()
+        #define portRAISE_PRIVILEGE()
+        #define portRESET_PRIVILEGE()
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
new file mode 100644
index 0000000..aaab4cf
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
@@ -0,0 +1,414 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr  r2, pxCurrentTCBConst2						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr  r3, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr  r0, [r3]									\n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	bic r4, #1										\n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+            "	ldr  r4, [r3]									\n"/* r4 = *r3 i.e. r4 = MAIR0. */
+            "	ldr  r2, xMAIR0Const2							\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str  r4, [r2]									\n"/* Program MAIR0. */
+            "	ldr  r2, xRNRConst2								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	movs r4, #4										\n"/* r4 = 4. */
+            "	str  r4, [r2]									\n"/* Program RNR = 4. */
+            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+            "	ldr  r2, xRBARConst2							\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r3!, {r4-r11}								\n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+            "	stmia r2!, {r4-r11}								\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	orr r4, #1										\n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldm  r0!, {r1-r4}								\n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+            "	ldr  r5, xSecureContextConst2					\n"
+            "	str  r1, [r5]									\n"/* Set xSecureContext to this task's value for the same. */
+            "	msr  psplim, r2									\n"/* Set this task's PSPLIM value. */
+            "	msr  control, r3								\n"/* Set this task's CONTROL value. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	mov  r0, #0										\n"
+            "	msr  basepri, r0								\n"/* Ensure that interrupts are enabled when the first task starts. */
+            "	bx   r4											\n"/* Finally, branch to EXC_RETURN. */
+        #else /* configENABLE_MPU */
+            "	ldm  r0!, {r1-r3}								\n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+            "	ldr  r4, xSecureContextConst2					\n"
+            "	str  r1, [r4]									\n"/* Set xSecureContext to this task's value for the same. */
+            "	msr  psplim, r2									\n"/* Set this task's PSPLIM value. */
+            "	movs r1, #2										\n"/* r1 = 2. */
+            "	msr  CONTROL, r1								\n"/* Switch to use PSP in the thread mode. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	mov  r0, #0										\n"
+            "	msr  basepri, r0								\n"/* Ensure that interrupts are enabled when the first task starts. */
+            "	bx   r3											\n"/* Finally, branch to EXC_RETURN. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+        "xSecureContextConst2: .word xSecureContext			\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst2: .word 0xe000ed94					\n"
+            "xMAIR0Const2: .word 0xe000edc0						\n"
+            "xRNRConst2: .word 0xe000ed98						\n"
+            "xRBARConst2: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	tst r0, #1										\n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "	ite ne											\n"
+        "	movne r0, #0									\n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "	moveq r0, #1									\n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "	bx lr											\n"/* Return. */
+        "													\n"
+        "	.align 4										\n"
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* Read the CONTROL register. */
+        "	bic r0, #1										\n"/* Clear the bit 0. */
+        "	msr control, r0									\n"/* Write back the new CONTROL value. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	orr r0, #1										\n"/* r0 = r0 | 1. */
+        "	msr control, r0									\n"/* CONTROL = r0. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	ldr r0, xVTORConst								\n"/* Use the NVIC offset register to locate the stack. */
+        "	ldr r0, [r0]									\n"/* Read the VTOR register which gives the address of vector table. */
+        "	ldr r0, [r0]									\n"/* The first entry in vector table is stack pointer. */
+        "	msr msp, r0										\n"/* Set the MSP back to the start of the stack. */
+        "	cpsie i											\n"/* Globally enable interrupts. */
+        "	cpsie f											\n"
+        "	dsb												\n"
+        "	isb												\n"
+        "	svc %0											\n"/* System call to start the first task. */
+        "	nop												\n"
+        "													\n"
+        "   .align 4										\n"
+        "xVTORConst: .word 0xe000ed08						\n"
+        ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	mrs r0, basepri									\n"/* r0 = basepri. Return original basepri value. */
+        "	mov r1, %0										\n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	msr basepri, r1									\n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bx lr											\n"/* Return. */
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	msr basepri, r0									\n"/* basepri = ulMask. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bx lr											\n"/* Return. */
+        ::: "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "	.extern SecureContext_SaveContext				\n"
+        "	.extern SecureContext_LoadContext				\n"
+        "													\n"
+        "	mrs r1, psp										\n"/* Read PSP in r1. */
+        "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+        "	ldr r0, [r2]									\n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+        "													\n"
+        "	cbz r0, save_ns_context							\n"/* No secure context to save. */
+        "	push {r0-r2, r14}								\n"
+        "	bl SecureContext_SaveContext					\n"
+        "	pop {r0-r3}										\n"/* LR is now in r3. */
+        "	mov lr, r3										\n"/* LR = r3. */
+        "	lsls r2, r3, #25								\n"/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        "	bpl save_ns_context								\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r2, [r3]									\n"/* Read pxCurrentTCB. */
+        #if ( configENABLE_MPU == 1 )
+            "	subs r1, r1, #16								\n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mrs r3, control									\n"/* r3 = CONTROL. */
+            "	mov r4, lr										\n"/* r4 = LR/EXC_RETURN. */
+            "	stmia r1!, {r0, r2-r4}							\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+        #else /* configENABLE_MPU */
+            "	subs r1, r1, #12								\n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmia r1!, {r0, r2-r3}							\n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+        #endif /* configENABLE_MPU */
+        "	b select_next_task								\n"
+        "													\n"
+        " save_ns_context:									\n"
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r2, [r3]									\n"/* Read pxCurrentTCB. */
+        #if ( configENABLE_FPU == 1 )
+            "	tst lr, #0x10									\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+            "	it eq											\n"
+            "	vstmdbeq r1!, {s16-s31}							\n"/* Store the FPU registers which are not saved automatically. */
+        #endif /* configENABLE_FPU */
+        #if ( configENABLE_MPU == 1 )
+            "	subs r1, r1, #48								\n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	adds r1, r1, #16								\n"/* r1 = r1 + 16. */
+            "	stm r1, {r4-r11}								\n"/* Store the registers that are not saved automatically. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mrs r3, control									\n"/* r3 = CONTROL. */
+            "	mov r4, lr										\n"/* r4 = LR/EXC_RETURN. */
+            "	subs r1, r1, #16								\n"/* r1 = r1 - 16. */
+            "	stm r1, {r0, r2-r4}								\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+        #else /* configENABLE_MPU */
+            "	subs r1, r1, #44								\n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	adds r1, r1, #12								\n"/* r1 = r1 + 12. */
+            "	stm r1, {r4-r11}								\n"/* Store the registers that are not saved automatically. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	subs r1, r1, #12								\n"/* r1 = r1 - 12. */
+            "	stmia r1!, {r0, r2-r3}							\n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        " select_next_task:									\n"
+        "	mov r0, %0										\n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+        "	msr basepri, r0									\n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bl vTaskSwitchContext							\n"
+        "	mov r0, #0										\n"/* r0 = 0. */
+        "	msr basepri, r0									\n"/* Enable interrupts. */
+        "													\n"
+        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r3, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr r1, [r3]									\n"/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	bic r4, #1										\n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+            "	ldr r4, [r3]									\n"/* r4 = *r3 i.e. r4 = MAIR0. */
+            "	ldr r2, xMAIR0Const								\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str r4, [r2]									\n"/* Program MAIR0. */
+            "	ldr r2, xRNRConst								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	movs r4, #4										\n"/* r4 = 4. */
+            "	str r4, [r2]									\n"/* Program RNR = 4. */
+            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+            "	ldr  r2, xRBARConst								\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r3!, {r4-r11}								\n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "	stmia r2!, {r4-r11}								\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	orr r4, #1										\n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldmia r1!, {r0, r2-r4}							\n"/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+            "	msr control, r3									\n"/* Restore the CONTROL register value for the task. */
+            "	mov lr, r4										\n"/* LR = r4. */
+            "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "	str r0, [r2]									\n"/* Restore the task's xSecureContext. */
+            "	cbz r0, restore_ns_context						\n"/* If there is no secure context for the task, restore the non-secure context. */
+            "	push {r1,r4}									\n"
+            "	bl SecureContext_LoadContext					\n"/* Restore the secure context. */
+            "	pop {r1,r4}										\n"
+            "	mov lr, r4										\n"/* LR = r4. */
+            "	lsls r2, r4, #25								\n"/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "	bpl restore_ns_context							\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+            "	bx lr											\n"
+        #else /* configENABLE_MPU */
+            "	ldmia r1!, {r0, r2-r3}							\n"/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+            "	mov lr, r3										\n"/* LR = r3. */
+            "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "	str r0, [r2]									\n"/* Restore the task's xSecureContext. */
+            "	cbz r0, restore_ns_context						\n"/* If there is no secure context for the task, restore the non-secure context. */
+            "	push {r1,r3}									\n"
+            "	bl SecureContext_LoadContext					\n"/* Restore the secure context. */
+            "	pop {r1,r3}										\n"
+            "	mov lr, r3										\n"/* LR = r3. */
+            "	lsls r2, r3, #25								\n"/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "	bpl restore_ns_context							\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+            "	bx lr											\n"
+        #endif /* configENABLE_MPU */
+        "													\n"
+        " restore_ns_context:								\n"
+        "	ldmia r1!, {r4-r11}								\n"/* Restore the registers that are not automatically restored. */
+        #if ( configENABLE_FPU == 1 )
+            "	tst lr, #0x10									\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+            "	it eq											\n"
+            "	vldmiaeq r1!, {s16-s31}							\n"/* Restore the FPU registers which are not restored automatically. */
+        #endif /* configENABLE_FPU */
+        "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+        "	bx lr											\n"
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB				\n"
+        "xSecureContextConst: .word xSecureContext			\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst: .word 0xe000ed94					\n"
+            "xMAIR0Const: .word 0xe000edc0						\n"
+            "xRNRConst: .word 0xe000ed98						\n"
+            "xRBARConst: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	tst lr, #4										\n"
+        "	ite eq											\n"
+        "	mrseq r0, msp									\n"
+        "	mrsne r0, psp									\n"
+        "	ldr r1, svchandler_address_const				\n"
+        "	bx r1											\n"
+        "													\n"
+        "	.align 4										\n"
+        "svchandler_address_const: .word vPortSVCHandler_C	\n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	svc %0											\n"/* Secure context is allocated in the supervisor call. */
+        "	bx lr											\n"/* Return. */
+        ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	ldr r1, [r0]									\n"/* The first item in the TCB is the top of the stack. */
+        "	ldr r0, [r1]									\n"/* The first item on the stack is the task's xSecureContext. */
+        "	cmp r0, #0										\n"/* Raise svc if task's xSecureContext is not NULL. */
+        "	it ne											\n"
+        "	svcne %0										\n"/* Secure context is freed in the supervisor call. */
+        "	bx lr											\n"/* Return. */
+        ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
new file mode 100644
index 0000000..8e3b0b3
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
@@ -0,0 +1,312 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+    #ifndef configENABLE_FPU
+        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+    #endif /* configENABLE_FPU */
+
+    #ifndef configENABLE_MPU
+        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+    #endif /* configENABLE_MPU */
+
+    #ifndef configENABLE_TRUSTZONE
+        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+    #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+    #define portARCH_NAME                      "Cortex-M33"
+    #define portSTACK_GROWTH                   ( -1 )
+    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT                 8
+    #define portNOP()
+    #define portINLINE                         __inline
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+    #endif
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
+    #define portDONT_DISCARD                   __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+    extern BaseType_t xPortIsInsideInterrupt( void );
+
+    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+    #endif /* configENABLE_TRUSTZONE */
+
+    #if ( configENABLE_MPU == 1 )
+        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+    #if ( configENABLE_MPU == 1 )
+        #define portUSING_MPU_WRAPPERS    1
+        #define portPRIVILEGE_BIT         ( 0x80000000UL )
+    #else
+        #define portPRIVILEGE_BIT         ( 0x0UL )
+    #endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
+    #define portSTACK_REGION                              ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
+    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
+    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
+    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
+    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
+    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+    } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
+    #define portSVC_FREE_SECURE_CONTEXT        1
+    #define portSVC_START_SCHEDULER            2
+    #define portSVC_RAISE_PRIVILEGE            3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+    #define portYIELD()                                 vPortYield()
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+    #define portDISABLE_INTERRUPTS()                  ulSetInterruptMask()
+    #define portENABLE_INTERRUPTS()                   vClearInterruptMask( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+    #else
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+        #define portCLEAN_UP_TCB( pxTCB )
+    #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+        #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+        #define portRESET_PRIVILEGE()    vResetPrivilege()
+    #else
+        #define portIS_PRIVILEGED()
+        #define portRAISE_PRIVILEGE()
+        #define portRESET_PRIVILEGE()
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
new file mode 100644
index 0000000..98927a7
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
@@ -0,0 +1,320 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr  r2, pxCurrentTCBConst2						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr  r1, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr  r0, [r1]									\n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	bic r4, #1										\n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+            "	ldr  r3, [r1]									\n"/* r3 = *r1 i.e. r3 = MAIR0. */
+            "	ldr  r2, xMAIR0Const2							\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str  r3, [r2]									\n"/* Program MAIR0. */
+            "	ldr  r2, xRNRConst2								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	movs r3, #4										\n"/* r3 = 4. */
+            "	str  r3, [r2]									\n"/* Program RNR = 4. */
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+            "	ldr  r2, xRBARConst2							\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r1!, {r4-r11}								\n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+            "	stmia r2!, {r4-r11}								\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	orr r4, #1										\n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldm  r0!, {r1-r3}								\n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+            "	msr  psplim, r1									\n"/* Set this task's PSPLIM value. */
+            "	msr  control, r2								\n"/* Set this task's CONTROL value. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	mov  r0, #0										\n"
+            "	msr  basepri, r0								\n"/* Ensure that interrupts are enabled when the first task starts. */
+            "	bx   r3											\n"/* Finally, branch to EXC_RETURN. */
+        #else /* configENABLE_MPU */
+            "	ldm  r0!, {r1-r2}								\n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+            "	msr  psplim, r1									\n"/* Set this task's PSPLIM value. */
+            "	movs r1, #2										\n"/* r1 = 2. */
+            "	msr  CONTROL, r1								\n"/* Switch to use PSP in the thread mode. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	mov  r0, #0										\n"
+            "	msr  basepri, r0								\n"/* Ensure that interrupts are enabled when the first task starts. */
+            "	bx   r2											\n"/* Finally, branch to EXC_RETURN. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst2: .word 0xe000ed94					\n"
+            "xMAIR0Const2: .word 0xe000edc0						\n"
+            "xRNRConst2: .word 0xe000ed98						\n"
+            "xRBARConst2: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	tst r0, #1										\n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "	ite ne											\n"
+        "	movne r0, #0									\n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "	moveq r0, #1									\n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "	bx lr											\n"/* Return. */
+        "													\n"
+        "	.align 4										\n"
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	mrs  r0, control								\n"/* Read the CONTROL register. */
+        "	bic r0, #1										\n"/* Clear the bit 0. */
+        "	msr  control, r0								\n"/* Write back the new CONTROL value. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	orr r0, #1										\n"/* r0 = r0 | 1. */
+        "	msr control, r0									\n"/* CONTROL = r0. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	ldr r0, xVTORConst								\n"/* Use the NVIC offset register to locate the stack. */
+        "	ldr r0, [r0]									\n"/* Read the VTOR register which gives the address of vector table. */
+        "	ldr r0, [r0]									\n"/* The first entry in vector table is stack pointer. */
+        "	msr msp, r0										\n"/* Set the MSP back to the start of the stack. */
+        "	cpsie i											\n"/* Globally enable interrupts. */
+        "	cpsie f											\n"
+        "	dsb												\n"
+        "	isb												\n"
+        "	svc %0											\n"/* System call to start the first task. */
+        "	nop												\n"
+        "													\n"
+        "   .align 4										\n"
+        "xVTORConst: .word 0xe000ed08						\n"
+        ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	mrs r0, basepri									\n"/* r0 = basepri. Return original basepri value. */
+        "	mov r1, %0										\n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	msr basepri, r1									\n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bx lr											\n"/* Return. */
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	msr basepri, r0									\n"/* basepri = ulMask. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bx lr											\n"/* Return. */
+        ::: "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, psp										\n"/* Read PSP in r0. */
+        #if ( configENABLE_FPU == 1 )
+            "	tst lr, #0x10									\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+            "	it eq											\n"
+            "	vstmdbeq r0!, {s16-s31}							\n"/* Store the FPU registers which are not saved automatically. */
+        #endif /* configENABLE_FPU */
+        #if ( configENABLE_MPU == 1 )
+            "	mrs r1, psplim									\n"/* r1 = PSPLIM. */
+            "	mrs r2, control									\n"/* r2 = CONTROL. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmdb r0!, {r1-r11}								\n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+        #else /* configENABLE_MPU */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmdb r0!, {r2-r11}								\n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r2]									\n"/* Read pxCurrentTCB. */
+        "	str r0, [r1]									\n"/* Save the new top of stack in TCB. */
+        "													\n"
+        "	mov r0, %0										\n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+        "	msr basepri, r0									\n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bl vTaskSwitchContext							\n"
+        "	mov r0, #0										\n"/* r0 = 0. */
+        "	msr basepri, r0									\n"/* Enable interrupts. */
+        "													\n"
+        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr r0, [r1]									\n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	bic r4, #1										\n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+            "	ldr r3, [r1]									\n"/* r3 = *r1 i.e. r3 = MAIR0. */
+            "	ldr r2, xMAIR0Const								\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str r3, [r2]									\n"/* Program MAIR0. */
+            "	ldr r2, xRNRConst								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	movs r3, #4										\n"/* r3 = 4. */
+            "	str r3, [r2]									\n"/* Program RNR = 4. */
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+            "	ldr r2, xRBARConst								\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r1!, {r4-r11}								\n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "	stmia r2!, {r4-r11}								\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	orr r4, #1										\n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldmia r0!, {r1-r11}								\n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+        #else /* configENABLE_MPU */
+            "	ldmia r0!, {r2-r11}								\n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_FPU == 1 )
+            "	tst r3, #0x10									\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+            "	it eq											\n"
+            "	vldmiaeq r0!, {s16-s31}							\n"/* Restore the FPU registers which are not restored automatically. */
+        #endif /* configENABLE_FPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	msr psplim, r1									\n"/* Restore the PSPLIM register value for the task. */
+            "	msr control, r2									\n"/* Restore the CONTROL register value for the task. */
+        #else /* configENABLE_MPU */
+            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+        #endif /* configENABLE_MPU */
+        "	msr psp, r0										\n"/* Remember the new top of stack for the task. */
+        "	bx r3											\n"
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB				\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst: .word 0xe000ed94					\n"
+            "xMAIR0Const: .word 0xe000edc0						\n"
+            "xRNRConst: .word 0xe000ed98						\n"
+            "xRBARConst: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	tst lr, #4										\n"
+        "	ite eq											\n"
+        "	mrseq r0, msp									\n"
+        "	mrsne r0, psp									\n"
+        "	ldr r1, svchandler_address_const				\n"
+        "	bx r1											\n"
+        "													\n"
+        "	.align 4										\n"
+        "svchandler_address_const: .word vPortSVCHandler_C	\n"
+    );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
new file mode 100644
index 0000000..8e3b0b3
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
@@ -0,0 +1,312 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+    #ifndef configENABLE_FPU
+        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+    #endif /* configENABLE_FPU */
+
+    #ifndef configENABLE_MPU
+        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+    #endif /* configENABLE_MPU */
+
+    #ifndef configENABLE_TRUSTZONE
+        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+    #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+    #define portARCH_NAME                      "Cortex-M33"
+    #define portSTACK_GROWTH                   ( -1 )
+    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT                 8
+    #define portNOP()
+    #define portINLINE                         __inline
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+    #endif
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
+    #define portDONT_DISCARD                   __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+    extern BaseType_t xPortIsInsideInterrupt( void );
+
+    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+    #endif /* configENABLE_TRUSTZONE */
+
+    #if ( configENABLE_MPU == 1 )
+        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+    #if ( configENABLE_MPU == 1 )
+        #define portUSING_MPU_WRAPPERS    1
+        #define portPRIVILEGE_BIT         ( 0x80000000UL )
+    #else
+        #define portPRIVILEGE_BIT         ( 0x0UL )
+    #endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
+    #define portSTACK_REGION                              ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
+    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
+    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
+    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
+    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
+    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+    } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
+    #define portSVC_FREE_SECURE_CONTEXT        1
+    #define portSVC_START_SCHEDULER            2
+    #define portSVC_RAISE_PRIVILEGE            3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+    #define portYIELD()                                 vPortYield()
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+    #define portDISABLE_INTERRUPTS()                  ulSetInterruptMask()
+    #define portENABLE_INTERRUPTS()                   vClearInterruptMask( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+    #else
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+        #define portCLEAN_UP_TCB( pxTCB )
+    #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+        #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+        #define portRESET_PRIVILEGE()    vResetPrivilege()
+    #else
+        #define portIS_PRIVILEGED()
+        #define portRAISE_PRIVILEGE()
+        #define portRESET_PRIVILEGE()
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s
new file mode 100644
index 0000000..8003b45
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s
@@ -0,0 +1,377 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN xSecureContext
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+	EXTERN SecureContext_SaveContext
+	EXTERN SecureContext_LoadContext
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vPortAllocateSecureContext
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMask
+	PUBLIC vClearInterruptMask
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+	PUBLIC vPortFreeSecureContext
+
+#if ( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	tst r0, r1								/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+	beq running_privileged					/* If the result of previous AND operation was 0, branch. */
+	movs r0, #0								/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+	running_privileged:
+		movs r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+		bx lr								/* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	orrs r0, r1								/* r0 = r0 | r1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vPortAllocateSecureContext:
+	svc 0									/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r3, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r3]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	movs r5, #1								/* r5 = 1. */
+	bics r4, r5								/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	ldr  r4, [r3]							/* r4 = *r3 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	movs r5, #4								/* r5 = 4. */
+	str  r5, [r2]							/* Program RNR = 4. */
+	ldmia r3!, {r6,r7}						/* Read first set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write first set of RBAR/RLAR registers. */
+	movs r5, #5								/* r5 = 5. */
+	str  r5, [r2]							/* Program RNR = 5. */
+	ldmia r3!, {r6,r7}						/* Read second set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write second set of RBAR/RLAR registers. */
+	movs r5, #6								/* r5 = 6. */
+	str  r5, [r2]							/* Program RNR = 6. */
+	ldmia r3!, {r6,r7}						/* Read third set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write third set of RBAR/RLAR registers. */
+	movs r5, #7								/* r5 = 7. */
+	str  r5, [r2]							/* Program RNR = 7. */
+	ldmia r3!, {r6,r7}						/* Read fourth set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write fourth set of RBAR/RLAR registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	movs r5, #1								/* r5 = 1. */
+	orrs r4, r5								/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r4}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+	ldr  r5, =xSecureContext
+	str  r1, [r5]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	msr  control, r3						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r4									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+	ldr  r4, =xSecureContext
+	str  r1, [r4]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs r0, control							/* Read the CONTROL register. */
+	movs r1, #1								/* r1 = 1. */
+	bics r0, r1								/* Clear the bit 0. */
+	msr control, r0							/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMask:
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMask:
+	msr PRIMASK, r0
+	bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r1, psp								/* Read PSP in r1. */
+	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+
+	cbz r0, save_ns_context					/* No secure context to save. */
+	push {r0-r2, r14}
+	bl SecureContext_SaveContext
+	pop {r0-r3}								/* LR is now in r3. */
+	mov lr, r3								/* LR = r3. */
+	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r2, [r3]							/* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mrs r3, control							/* r3 = CONTROL. */
+	mov r4, lr								/* r4 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+#else /* configENABLE_MPU */
+	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
+#endif /* configENABLE_MPU */
+	b select_next_task
+
+	save_ns_context:
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r2, [r3]						/* Read pxCurrentTCB. */
+	#if ( configENABLE_MPU == 1 )
+		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		adds r1, r1, #16					/* r1 = r1 + 16. */
+		stmia r1!, {r4-r7}					/* Store the low registers that are not saved automatically. */
+		mov r4, r8							/* r4 = r8. */
+		mov r5, r9							/* r5 = r9. */
+		mov r6, r10							/* r6 = r10. */
+		mov r7, r11							/* r7 = r11. */
+		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mrs r3, control						/* r3 = CONTROL. */
+		mov r4, lr							/* r4 = LR/EXC_RETURN. */
+		subs r1, r1, #48					/* r1 = r1 - 48. */
+		stmia r1!, {r0, r2-r4}				/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mov r3, lr							/* r3 = LR/EXC_RETURN. */
+		stmia r1!, {r0, r2-r7}				/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+		mov r4, r8							/* r4 = r8. */
+		mov r5, r9							/* r5 = r9. */
+		mov r6, r10							/* r6 = r10. */
+		mov r7, r11							/* r7 = r11. */
+		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
+	#endif /* configENABLE_MPU */
+
+	select_next_task:
+		cpsid i
+		bl vTaskSwitchContext
+		cpsie i
+
+		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r3, [r2]						/* Read pxCurrentTCB. */
+		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+
+	#if ( configENABLE_MPU == 1 )
+		dmb									/* Complete outstanding transfers before disabling MPU. */
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		movs r5, #1							/* r5 = 1. */
+		bics r4, r5							/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+		str r4, [r2]						/* Disable MPU. */
+
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
+		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+		str r4, [r2]						/* Program MAIR0. */
+		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+		movs r5, #4							/* r5 = 4. */
+		str  r5, [r2]						/* Program RNR = 4. */
+		ldmia r3!, {r6,r7}					/* Read first set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write first set of RBAR/RLAR registers. */
+		movs r5, #5							/* r5 = 5. */
+		str  r5, [r2]						/* Program RNR = 5. */
+		ldmia r3!, {r6,r7}					/* Read second set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write second set of RBAR/RLAR registers. */
+		movs r5, #6							/* r5 = 6. */
+		str  r5, [r2]						/* Program RNR = 6. */
+		ldmia r3!, {r6,r7}					/* Read third set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write third set of RBAR/RLAR registers. */
+		movs r5, #7							/* r5 = 7. */
+		str  r5, [r2]						/* Program RNR = 7. */
+		ldmia r3!, {r6,r7}					/* Read fourth set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write fourth set of RBAR/RLAR registers. */
+
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		movs r5, #1							/* r5 = 1. */
+		orrs r4, r5							/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+		str r4, [r2]						/* Enable MPU. */
+		dsb									/* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+
+	#if ( configENABLE_MPU == 1 )
+		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		msr control, r3						/* Restore the CONTROL register value for the task. */
+		mov lr, r4							/* LR = r4. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r4}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r4}
+		mov lr, r4							/* LR = r4. */
+		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#else /* configENABLE_MPU */
+		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		mov lr, r3							/* LR = r3. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r3}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r3}
+		mov lr, r3							/* LR = r3. */
+		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#endif /* configENABLE_MPU */
+
+	restore_ns_context:
+		adds r1, r1, #16					/* Move to the high registers. */
+		ldmia r1!, {r4-r7}					/* Restore the high registers that are not automatically restored. */
+		mov r8, r4							/* r8 = r4. */
+		mov r9, r5							/* r9 = r5. */
+		mov r10, r6							/* r10 = r6. */
+		mov r11, r7							/* r11 = r7. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		subs r1, r1, #32					/* Go back to the low registers. */
+		ldmia r1!, {r4-r7}					/* Restore the low registers that are not automatically restored. */
+		bx lr
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	movs r0, #4
+	mov r1, lr
+	tst r0, r1
+	beq stacking_used_msp
+	mrs r0, psp
+	b vPortSVCHandler_C
+	stacking_used_msp:
+		mrs r0, msp
+		b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+vPortFreeSecureContext:
+	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
+	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
+	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
+	beq free_secure_context
+	bx lr									/* There is no secure context (xSecureContext is NULL). */
+	free_secure_context:
+		svc 1								/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+		bx lr								/* Return. */
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
new file mode 100644
index 0000000..b36dc1f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
@@ -0,0 +1,319 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+    #ifndef configENABLE_FPU
+        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+    #endif /* configENABLE_FPU */
+
+    #ifndef configENABLE_MPU
+        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+    #endif /* configENABLE_MPU */
+
+    #ifndef configENABLE_TRUSTZONE
+        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+    #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+    #define portARCH_NAME                      "Cortex-M23"
+    #define portSTACK_GROWTH                   ( -1 )
+    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT                 8
+    #define portNOP()
+    #define portINLINE                         __inline
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+    #endif
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
+    #define portDONT_DISCARD                   __root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+    extern BaseType_t xPortIsInsideInterrupt( void );
+
+    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+    #endif /* configENABLE_TRUSTZONE */
+
+    #if ( configENABLE_MPU == 1 )
+        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+    #if ( configENABLE_MPU == 1 )
+        #define portUSING_MPU_WRAPPERS    1
+        #define portPRIVILEGE_BIT         ( 0x80000000UL )
+    #else
+        #define portPRIVILEGE_BIT         ( 0x0UL )
+    #endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
+    #define portSTACK_REGION                              ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
+    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
+    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
+    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
+    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
+    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+    } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
+    #define portSVC_FREE_SECURE_CONTEXT        1
+    #define portSVC_START_SCHEDULER            2
+    #define portSVC_RAISE_PRIVILEGE            3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+    #define portYIELD()                                 vPortYield()
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+    #define portDISABLE_INTERRUPTS()                  __asm volatile ( " cpsid i " ::: "memory" )
+    #define portENABLE_INTERRUPTS()                   __asm volatile ( " cpsie i " ::: "memory" )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+    #else
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+        #define portCLEAN_UP_TCB( pxTCB )
+    #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+        #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+        #define portRESET_PRIVILEGE()    vResetPrivilege()
+    #else
+        #define portIS_PRIVILEGED()
+        #define portRAISE_PRIVILEGE()
+        #define portRESET_PRIVILEGE()
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+    #pragma diag_suppress=Be006
+    #pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s
new file mode 100644
index 0000000..6e911bd
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s
@@ -0,0 +1,303 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMask
+	PUBLIC vClearInterruptMask
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+
+#if ( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	tst r0, r1								/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+	beq running_privileged					/* If the result of previous AND operation was 0, branch. */
+	movs r0, #0								/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+	running_privileged:
+		movs r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+		bx lr								/* Return. */
+
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	orrs r0, r1								/* r0 = r0 | r1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r1, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r1]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	bics r3, r4								/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+	str r3, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr  r4, [r1]							/* r4 = *r1 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	movs r4, #4								/* r4 = 4. */
+	str  r4, [r2]							/* Program RNR = 4. */
+	ldmia r1!, {r5,r6}						/* Read first set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write first set of RBAR/RLAR registers. */
+	movs r4, #5								/* r4 = 5. */
+	str  r4, [r2]							/* Program RNR = 5. */
+	ldmia r1!, {r5,r6}						/* Read second set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write second set of RBAR/RLAR registers. */
+	movs r4, #6								/* r4 = 6. */
+	str  r4, [r2]							/* Program RNR = 6. */
+	ldmia r1!, {r5,r6}						/* Read third set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write third set of RBAR/RLAR registers. */
+	movs r4, #7								/* r4 = 7. */
+	str  r4, [r2]							/* Program RNR = 7. */
+	ldmia r1!, {r5,r6}						/* Read fourth set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write fourth set of RBAR/RLAR registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	orrs r3, r4								/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+	str r3, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	msr  control, r2						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r2									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs  r0, control						/* Read the CONTROL register. */
+	movs r1, #1								/* r1 = 1. */
+	bics r0, r1								/* Clear the bit 0. */
+	msr  control, r0						/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+	nop
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMask:
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMask:
+	msr PRIMASK, r0
+	bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r0, psp								/* Read PSP in r0. */
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+	subs r0, r0, #44						/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+	str r0, [r1]							/* Save the new top of stack in TCB. */
+	mrs r1, psplim							/* r1 = PSPLIM. */
+	mrs r2, control							/* r2 = CONTROL. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r0!, {r1-r7}						/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
+	mov r4, r8								/* r4 = r8. */
+	mov r5, r9								/* r5 = r9. */
+	mov r6, r10								/* r6 = r10. */
+	mov r7, r11								/* r7 = r11. */
+	stmia r0!, {r4-r7}						/* Store the high registers that are not saved automatically. */
+#else /* configENABLE_MPU */
+	subs r0, r0, #40						/* Make space for PSPLIM, LR and the remaining registers on the stack. */
+	str r0, [r1]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r0!, {r2-r7}						/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
+	mov r4, r8								/* r4 = r8. */
+	mov r5, r9								/* r5 = r9. */
+	mov r6, r10								/* r6 = r10. */
+	mov r7, r11								/* r7 = r11. */
+	stmia r0!, {r4-r7}						/* Store the high registers that are not saved automatically. */
+#endif /* configENABLE_MPU */
+
+	cpsid i
+	bl vTaskSwitchContext
+	cpsie i
+
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+	ldr r0, [r1]							/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	bics r3, r4								/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+	str r3, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr  r4, [r1]							/* r4 = *r1 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	movs r4, #4								/* r4 = 4. */
+	str  r4, [r2]							/* Program RNR = 4. */
+	ldmia r1!, {r5,r6}						/* Read first set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write first set of RBAR/RLAR registers. */
+	movs r4, #5								/* r4 = 5. */
+	str  r4, [r2]							/* Program RNR = 5. */
+	ldmia r1!, {r5,r6}						/* Read second set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write second set of RBAR/RLAR registers. */
+	movs r4, #6								/* r4 = 6. */
+	str  r4, [r2]							/* Program RNR = 6. */
+	ldmia r1!, {r5,r6}						/* Read third set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write third set of RBAR/RLAR registers. */
+	movs r4, #7								/* r4 = 7. */
+	str  r4, [r2]							/* Program RNR = 7. */
+	ldmia r1!, {r5,r6}						/* Read fourth set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write fourth set of RBAR/RLAR registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	orrs r3, r4								/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+	str r3, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	adds r0, r0, #28						/* Move to the high registers. */
+	ldmia r0!, {r4-r7}						/* Restore the high registers that are not automatically restored. */
+	mov r8, r4								/* r8 = r4. */
+	mov r9, r5								/* r9 = r5. */
+	mov r10, r6								/* r10 = r6. */
+	mov r11, r7								/* r11 = r7. */
+	msr psp, r0								/* Remember the new top of stack for the task. */
+	subs r0, r0, #44						/* Move to the starting of the saved context. */
+	ldmia r0!, {r1-r7}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
+	msr psplim, r1							/* Restore the PSPLIM register value for the task. */
+	msr control, r2							/* Restore the CONTROL register value for the task. */
+	bx r3
+#else /* configENABLE_MPU */
+	adds r0, r0, #24						/* Move to the high registers. */
+	ldmia r0!, {r4-r7}						/* Restore the high registers that are not automatically restored. */
+	mov r8, r4								/* r8 = r4. */
+	mov r9, r5								/* r9 = r5. */
+	mov r10, r6								/* r10 = r6. */
+	mov r11, r7								/* r11 = r7. */
+	msr psp, r0								/* Remember the new top of stack for the task. */
+	subs r0, r0, #40						/* Move to the starting of the saved context. */
+	ldmia r0!, {r2-r7}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+	msr psplim, r2							/* Restore the PSPLIM register value for the task. */
+	bx r3
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	movs r0, #4
+	mov r1, lr
+	tst r0, r1
+	beq stacking_used_msp
+	mrs r0, psp
+	b vPortSVCHandler_C
+	stacking_used_msp:
+		mrs r0, msp
+		b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
new file mode 100644
index 0000000..315e712
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
@@ -0,0 +1,319 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+    #ifndef configENABLE_FPU
+        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+    #endif /* configENABLE_FPU */
+
+    #ifndef configENABLE_MPU
+        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+    #endif /* configENABLE_MPU */
+
+    #ifndef configENABLE_TRUSTZONE
+        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+    #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+    #define portARCH_NAME                      "Cortex-M23"
+    #define portSTACK_GROWTH                   ( -1 )
+    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT                 8
+    #define portNOP()
+    #define portINLINE                         __inline
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+    #endif
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
+    #define portDONT_DISCARD                   __root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+    extern BaseType_t xPortIsInsideInterrupt( void );
+
+    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+    #endif /* configENABLE_TRUSTZONE */
+
+    #if ( configENABLE_MPU == 1 )
+        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+    #if ( configENABLE_MPU == 1 )
+        #define portUSING_MPU_WRAPPERS    1
+        #define portPRIVILEGE_BIT         ( 0x80000000UL )
+    #else
+        #define portPRIVILEGE_BIT         ( 0x0UL )
+    #endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
+    #define portSTACK_REGION                              ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
+    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
+    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
+    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
+    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
+    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+    } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
+    #define portSVC_FREE_SECURE_CONTEXT        1
+    #define portSVC_START_SCHEDULER            2
+    #define portSVC_RAISE_PRIVILEGE            3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+    #define portYIELD()                                 vPortYield()
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+    #define portDISABLE_INTERRUPTS()                  __asm volatile ( " cpsid i " ::: "memory" )
+    #define portENABLE_INTERRUPTS()                   __asm volatile ( " cpsie i " ::: "memory" )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+    #else
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+        #define portCLEAN_UP_TCB( pxTCB )
+    #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+        #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+        #define portRESET_PRIVILEGE()    vResetPrivilege()
+    #else
+        #define portIS_PRIVILEGED()
+        #define portRAISE_PRIVILEGE()
+        #define portRESET_PRIVILEGE()
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+    #pragma diag_suppress=Be006
+    #pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
new file mode 100644
index 0000000..6b125b2
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
@@ -0,0 +1,345 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+/* Including FreeRTOSConfig.h here will cause build errors if the header file
+contains code not understood by the assembler - for example the 'extern' keyword.
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
+the code is included in C files but excluded by the preprocessor in assembly
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
+#include "FreeRTOSConfig.h"
+
+	EXTERN pxCurrentTCB
+	EXTERN xSecureContext
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+	EXTERN SecureContext_SaveContext
+	EXTERN SecureContext_LoadContext
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vPortAllocateSecureContext
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMask
+	PUBLIC vClearInterruptMask
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+	PUBLIC vPortFreeSecureContext
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	ite ne
+	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	orr r0, r0, #1							/* r0 = r0 | 1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vPortAllocateSecureContext:
+	svc 0									/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r3, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r3]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	ldr  r4, [r3]							/* r4 = *r3 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	movs r4, #4								/* r4 = 4. */
+	str  r4, [r2]							/* Program RNR = 4. */
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	ldr  r2, =0xe000ed9c					/* r2 = 0xe000ed9c [Location of RBAR]. */
+	ldmia r3!, {r4-r11}						/* Read 4 set of RBAR/RLAR registers from TCB. */
+	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r4}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+	ldr  r5, =xSecureContext
+	str  r1, [r5]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	msr  control, r3						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	mov  r0, #0
+	msr  basepri, r0						/* Ensure that interrupts are enabled when the first task starts. */
+	bx   r4									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+	ldr  r4, =xSecureContext
+	str  r1, [r4]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	mov  r0, #0
+	msr  basepri, r0						/* Ensure that interrupts are enabled when the first task starts. */
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs  r0, control						/* Read the CONTROL register. */
+	bic r0, r0, #1							/* Clear the bit 0. */
+	msr  control, r0						/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	cpsie f
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMask:
+	mrs r0, basepri							/* r0 = basepri. Return original basepri value. */
+	mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr basepri, r1							/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+	dsb
+	isb
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+vClearInterruptMask:
+	msr basepri, r0							/* basepri = ulMask. */
+	dsb
+	isb
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r1, psp								/* Read PSP in r1. */
+	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+
+	cbz r0, save_ns_context					/* No secure context to save. */
+	push {r0-r2, r14}
+	bl SecureContext_SaveContext
+	pop {r0-r3}								/* LR is now in r3. */
+	mov lr, r3								/* LR = r3. */
+	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r2, [r3]							/* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mrs r3, control							/* r3 = CONTROL. */
+	mov r4, lr								/* r4 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+#else /* configENABLE_MPU */
+	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
+#endif /* configENABLE_MPU */
+	b select_next_task
+
+	save_ns_context:
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r2, [r3]						/* Read pxCurrentTCB. */
+	#if ( configENABLE_FPU == 1 )
+		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+		it eq
+		vstmdbeq r1!, {s16-s31}				/* Store the FPU registers which are not saved automatically. */
+	#endif /* configENABLE_FPU */
+	#if ( configENABLE_MPU == 1 )
+		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		adds r1, r1, #16					/* r1 = r1 + 16. */
+		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mrs r3, control						/* r3 = CONTROL. */
+		mov r4, lr							/* r4 = LR/EXC_RETURN. */
+		subs r1, r1, #16					/* r1 = r1 - 16. */
+		stm r1, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		adds r1, r1, #12					/* r1 = r1 + 12. */
+		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mov r3, lr							/* r3 = LR/EXC_RETURN. */
+		subs r1, r1, #12					/* r1 = r1 - 12. */
+		stmia r1!, {r0, r2-r3}				/* Store xSecureContext, PSPLIM and LR on the stack. */
+	#endif /* configENABLE_MPU */
+
+	select_next_task:
+		mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+		msr basepri, r0						/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+		dsb
+		isb
+		bl vTaskSwitchContext
+		mov r0, #0							/* r0 = 0. */
+		msr basepri, r0						/* Enable interrupts. */
+
+		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r3, [r2]						/* Read pxCurrentTCB. */
+		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+
+	#if ( configENABLE_MPU == 1 )
+		dmb									/* Complete outstanding transfers before disabling MPU. */
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		bic r4, r4, #1						/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+		str r4, [r2]						/* Disable MPU. */
+
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
+		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+		str r4, [r2]						/* Program MAIR0. */
+		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+		movs r4, #4							/* r4 = 4. */
+		str r4, [r2]						/* Program RNR = 4. */
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+		ldr  r2, =0xe000ed9c				/* r2 = 0xe000ed9c [Location of RBAR]. */
+		ldmia r3!, {r4-r11}					/* Read 4 sets of RBAR/RLAR registers from TCB. */
+		stmia r2!, {r4-r11}					/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		orr r4, r4, #1						/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+		str r4, [r2]						/* Enable MPU. */
+		dsb									/* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+
+	#if ( configENABLE_MPU == 1 )
+		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		msr control, r3						/* Restore the CONTROL register value for the task. */
+		mov lr, r4							/* LR = r4. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r4}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r4}
+		mov lr, r4							/* LR = r4. */
+		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#else /* configENABLE_MPU */
+		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		mov lr, r3							/* LR = r3. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r3}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r3}
+		mov lr, r3							/* LR = r3. */
+		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#endif /* configENABLE_MPU */
+
+	restore_ns_context:
+		ldmia r1!, {r4-r11}					/* Restore the registers that are not automatically restored. */
+	#if ( configENABLE_FPU == 1 )
+		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+		it eq
+		vldmiaeq r1!, {s16-s31}				/* Restore the FPU registers which are not restored automatically. */
+	#endif /* configENABLE_FPU */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	tst lr, #4
+	ite eq
+	mrseq r0, msp
+	mrsne r0, psp
+	b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+vPortFreeSecureContext:
+	/* r0 = uint32_t *pulTCB. */
+	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
+	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
+	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
+	it ne
+	svcne 1									/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
new file mode 100644
index 0000000..e3fa10a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
@@ -0,0 +1,319 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+    #ifndef configENABLE_FPU
+        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+    #endif /* configENABLE_FPU */
+
+    #ifndef configENABLE_MPU
+        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+    #endif /* configENABLE_MPU */
+
+    #ifndef configENABLE_TRUSTZONE
+        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+    #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+    #define portARCH_NAME                      "Cortex-M33"
+    #define portSTACK_GROWTH                   ( -1 )
+    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT                 8
+    #define portNOP()
+    #define portINLINE                         __inline
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+    #endif
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
+    #define portDONT_DISCARD                   __root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+    extern BaseType_t xPortIsInsideInterrupt( void );
+
+    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+    #endif /* configENABLE_TRUSTZONE */
+
+    #if ( configENABLE_MPU == 1 )
+        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+    #if ( configENABLE_MPU == 1 )
+        #define portUSING_MPU_WRAPPERS    1
+        #define portPRIVILEGE_BIT         ( 0x80000000UL )
+    #else
+        #define portPRIVILEGE_BIT         ( 0x0UL )
+    #endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
+    #define portSTACK_REGION                              ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
+    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
+    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
+    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
+    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
+    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+    } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
+    #define portSVC_FREE_SECURE_CONTEXT        1
+    #define portSVC_START_SCHEDULER            2
+    #define portSVC_RAISE_PRIVILEGE            3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+    #define portYIELD()                                 vPortYield()
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+    #define portDISABLE_INTERRUPTS()                  ulSetInterruptMask()
+    #define portENABLE_INTERRUPTS()                   vClearInterruptMask( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+    #else
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+        #define portCLEAN_UP_TCB( pxTCB )
+    #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+        #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+        #define portRESET_PRIVILEGE()    vResetPrivilege()
+    #else
+        #define portIS_PRIVILEGED()
+        #define portRAISE_PRIVILEGE()
+        #define portRESET_PRIVILEGE()
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+    #pragma diag_suppress=Be006
+    #pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
new file mode 100644
index 0000000..b65f0f4
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
@@ -0,0 +1,261 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+/* Including FreeRTOSConfig.h here will cause build errors if the header file
+contains code not understood by the assembler - for example the 'extern' keyword.
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
+the code is included in C files but excluded by the preprocessor in assembly
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
+#include "FreeRTOSConfig.h"
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMask
+	PUBLIC vClearInterruptMask
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	ite ne
+	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	orr r0, r0, #1							/* r0 = r0 | 1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r1, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r1]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
+	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str r3, [r2]							/* Program MAIR0. */
+	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
+	movs r3, #4								/* r3 = 4. */
+	str r3, [r2]							/* Program RNR = 4. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
+	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
+	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	msr  control, r2						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	mov  r0, #0
+	msr  basepri, r0						/* Ensure that interrupts are enabled when the first task starts. */
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	mov  r0, #0
+	msr  basepri, r0						/* Ensure that interrupts are enabled when the first task starts. */
+	bx   r2									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs  r0, control						/* Read the CONTROL register. */
+	bic r0, r0, #1							/* Clear the bit 0. */
+	msr  control, r0						/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	cpsie f
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMask:
+	mrs r0, basepri							/* r0 = basepri. Return original basepri value. */
+	mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr basepri, r1							/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+	dsb
+	isb
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+vClearInterruptMask:
+	msr basepri, r0							/* basepri = ulMask. */
+	dsb
+	isb
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r0, psp								/* Read PSP in r0. */
+#if ( configENABLE_FPU == 1 )
+	tst lr, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	it eq
+	vstmdbeq r0!, {s16-s31}					/* Store the FPU registers which are not saved automatically. */
+#endif /* configENABLE_FPU */
+#if ( configENABLE_MPU == 1 )
+	mrs r1, psplim							/* r1 = PSPLIM. */
+	mrs r2, control							/* r2 = CONTROL. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmdb r0!, {r1-r11}						/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+#else /* configENABLE_MPU */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmdb r0!, {r2-r11}						/* Store on the stack - PSPLIM, LR and registers that are not automatically. */
+#endif /* configENABLE_MPU */
+
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+	str r0, [r1]							/* Save the new top of stack in TCB. */
+
+	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr basepri, r0							/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+	dsb
+	isb
+	bl vTaskSwitchContext
+	mov r0, #0								/* r0 = 0. */
+	msr basepri, r0							/* Enable interrupts. */
+
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+	ldr r0, [r1]							/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
+	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str r3, [r2]							/* Program MAIR0. */
+	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
+	movs r3, #4								/* r3 = 4. */
+	str r3, [r2]							/* Program RNR = 4. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
+	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
+	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldmia r0!, {r1-r11}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+#else /* configENABLE_MPU */
+	ldmia r0!, {r2-r11}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+	tst r3, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	it eq
+	vldmiaeq r0!, {s16-s31}					/* Restore the FPU registers which are not restored automatically. */
+#endif /* configENABLE_FPU */
+
+ #if ( configENABLE_MPU == 1 )
+	msr psplim, r1							/* Restore the PSPLIM register value for the task. */
+	msr control, r2							/* Restore the CONTROL register value for the task. */
+#else /* configENABLE_MPU */
+	msr psplim, r2							/* Restore the PSPLIM register value for the task. */
+#endif /* configENABLE_MPU */
+	msr psp, r0								/* Remember the new top of stack for the task. */
+	bx r3
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	tst lr, #4
+	ite eq
+	mrseq r0, msp
+	mrsne r0, psp
+	b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
new file mode 100644
index 0000000..e3fa10a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
@@ -0,0 +1,319 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+    #ifndef configENABLE_FPU
+        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+    #endif /* configENABLE_FPU */
+
+    #ifndef configENABLE_MPU
+        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+    #endif /* configENABLE_MPU */
+
+    #ifndef configENABLE_TRUSTZONE
+        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+    #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+    #define portARCH_NAME                      "Cortex-M33"
+    #define portSTACK_GROWTH                   ( -1 )
+    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT                 8
+    #define portNOP()
+    #define portINLINE                         __inline
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+    #endif
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
+    #define portDONT_DISCARD                   __root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+    extern BaseType_t xPortIsInsideInterrupt( void );
+
+    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+    #endif /* configENABLE_TRUSTZONE */
+
+    #if ( configENABLE_MPU == 1 )
+        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+    #if ( configENABLE_MPU == 1 )
+        #define portUSING_MPU_WRAPPERS    1
+        #define portPRIVILEGE_BIT         ( 0x80000000UL )
+    #else
+        #define portPRIVILEGE_BIT         ( 0x0UL )
+    #endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
+    #define portSTACK_REGION                              ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
+    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
+    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
+    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
+    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
+    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+    } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
+    #define portSVC_FREE_SECURE_CONTEXT        1
+    #define portSVC_START_SCHEDULER            2
+    #define portSVC_RAISE_PRIVILEGE            3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+    #define portYIELD()                                 vPortYield()
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+    #define portDISABLE_INTERRUPTS()                  ulSetInterruptMask()
+    #define portENABLE_INTERRUPTS()                   vClearInterruptMask( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+    #else
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+        #define portCLEAN_UP_TCB( pxTCB )
+    #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+        #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+        #define portRESET_PRIVILEGE()    vResetPrivilege()
+    #else
+        #define portIS_PRIVILEGED()
+        #define portRAISE_PRIVILEGE()
+        #define portRESET_PRIVILEGE()
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+    #pragma diag_suppress=Be006
+    #pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portasm.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portasm.h
new file mode 100644
index 0000000..b01f171
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/ReadMe.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/ReadMe.txt
new file mode 100644
index 0000000..0bb046a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/ReadMe.txt
@@ -0,0 +1,10 @@
+This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
+Do not use the files located here!  These file are copied into separate
+FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
+FreeRTOS release.
+
+If your Cortex-M33 application uses TrustZone then use the files from the
+FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
+
+If your Cortex-M33 application does not use TrustZone then use the files from
+the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c
new file mode 100644
index 0000000..ade0abf
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c
@@ -0,0 +1,91 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+#if ( configENABLE_FPU == 1 )
+    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+    /* xSecureContextHandle value is in r0. */
+    __asm volatile
+    (
+        "	.syntax unified							\n"
+        "											\n"
+        "	mrs r1, ipsr							\n"/* r1 = IPSR. */
+        "	cbz r1, load_ctx_therad_mode			\n"/* Do nothing if the processor is running in the Thread Mode. */
+        "	ldmia r0!, {r1, r2}						\n"/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+        #if ( configENABLE_MPU == 1 )
+            "	ldmia r1!, {r3}							\n"/* Read CONTROL register value from task's stack. r3 = CONTROL. */
+            "	msr control, r3							\n"/* CONTROL = r3. */
+        #endif /* configENABLE_MPU */
+        "	msr psplim, r2							\n"/* PSPLIM = r2. */
+        "	msr psp, r1								\n"/* PSP = r1. */
+        "											\n"
+        " load_ctx_therad_mode:						\n"
+        "	nop										\n"
+        "											\n"
+        ::: "r0", "r1", "r2"
+    );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+    /* xSecureContextHandle value is in r0. */
+    __asm volatile
+    (
+        "	.syntax unified							\n"
+        "											\n"
+        "	mrs r1, ipsr							\n"/* r1 = IPSR. */
+        "	cbz r1, save_ctx_therad_mode			\n"/* Do nothing if the processor is running in the Thread Mode. */
+        "	mrs r1, psp								\n"/* r1 = PSP. */
+        #if ( configENABLE_MPU == 1 )
+            "	mrs r2, control							\n"/* r2 = CONTROL. */
+            "	subs r1, r1, #4							\n"/* Make space for the CONTROL value on the stack. */
+            "	str r1, [r0]							\n"/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+            "	stmia r1!, {r2}							\n"/* Store CONTROL value on the stack. */
+        #else /* configENABLE_MPU */
+            "	str r1, [r0]							\n"/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+        #endif /* configENABLE_MPU */
+        "	movs r1, %0								\n"/* r1 = securecontextNO_STACK. */
+        "	msr psplim, r1							\n"/* PSPLIM = securecontextNO_STACK. */
+        "	msr psp, r1								\n"/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+        "											\n"
+        " save_ctx_therad_mode:						\n"
+        "	nop										\n"
+        "											\n"
+        ::"i" ( securecontextNO_STACK ) : "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c
new file mode 100644
index 0000000..64b2e7a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c
@@ -0,0 +1,88 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+    /* xSecureContextHandle value is in r0. */
+    __asm volatile
+    (
+        "	.syntax unified							\n"
+        "											\n"
+        "	mrs r1, ipsr							\n"/* r1 = IPSR. */
+        "	cbz r1, load_ctx_therad_mode			\n"/* Do nothing if the processor is running in the Thread Mode. */
+        "	ldmia r0!, {r1, r2}						\n"/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+        #if ( configENABLE_MPU == 1 )
+            "	ldmia r1!, {r3}							\n"/* Read CONTROL register value from task's stack. r3 = CONTROL. */
+            "	msr control, r3							\n"/* CONTROL = r3. */
+        #endif /* configENABLE_MPU */
+        "	msr psplim, r2							\n"/* PSPLIM = r2. */
+        "	msr psp, r1								\n"/* PSP = r1. */
+        "											\n"
+        " load_ctx_therad_mode:						\n"
+        "	nop										\n"
+        "											\n"
+        ::: "r0", "r1", "r2"
+    );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+    /* xSecureContextHandle value is in r0. */
+    __asm volatile
+    (
+        "	.syntax unified							\n"
+        "											\n"
+        "	mrs r1, ipsr							\n"/* r1 = IPSR. */
+        "	cbz r1, save_ctx_therad_mode			\n"/* Do nothing if the processor is running in the Thread Mode. */
+        "	mrs r1, psp								\n"/* r1 = PSP. */
+        #if ( configENABLE_FPU == 1 )
+            "	vstmdb r1!, {s0}						\n"/* Trigger the defferred stacking of FPU registers. */
+            "	vldmia r1!, {s0}						\n"/* Nullify the effect of the pervious statement. */
+        #endif /* configENABLE_FPU */
+        #if ( configENABLE_MPU == 1 )
+            "	mrs r2, control							\n"/* r2 = CONTROL. */
+            "	stmdb r1!, {r2}							\n"/* Store CONTROL value on the stack. */
+        #endif /* configENABLE_MPU */
+        "	str r1, [r0]							\n"/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+        "	movs r1, %0								\n"/* r1 = securecontextNO_STACK. */
+        "	msr psplim, r1							\n"/* PSPLIM = securecontextNO_STACK. */
+        "	msr psp, r1								\n"/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+        "											\n"
+        " save_ctx_therad_mode:						\n"
+        "	nop										\n"
+        "											\n"
+        ::"i" ( securecontextNO_STACK ) : "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port.c
new file mode 100644
index 0000000..455b90c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port.c
@@ -0,0 +1,48 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/* Functions implemented in assembler file. */
+extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
+extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+    SecureContext_LoadContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+    SecureContext_SaveContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s
new file mode 100644
index 0000000..1f793f2
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s
@@ -0,0 +1,76 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+
+	PUBLIC SecureContext_LoadContextAsm
+	PUBLIC SecureContext_SaveContextAsm
+
+#if ( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+SecureContext_LoadContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+#if ( configENABLE_MPU == 1 )
+	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
+	msr control, r3							/* CONTROL = r3. */
+#endif /* configENABLE_MPU */
+	msr psplim, r2							/* PSPLIM = r2. */
+	msr psp, r1								/* PSP = r1. */
+
+	load_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+SecureContext_SaveContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	mrs r1, psp								/* r1 = PSP. */
+#if ( configENABLE_MPU == 1 )
+	mrs r2, control							/* r2 = CONTROL. */
+	subs r1, r1, #4							/* Make space for the CONTROL value on the stack. */
+	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	stmia r1!, {r2}							/* Store CONTROL value on the stack. */
+#else /* configENABLE_MPU */
+	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+#endif /* configENABLE_MPU */
+	movs r1, #0								/* r1 = securecontextNO_STACK. */
+	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
+	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+
+	save_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port.c
new file mode 100644
index 0000000..455b90c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port.c
@@ -0,0 +1,48 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/* Functions implemented in assembler file. */
+extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
+extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+    SecureContext_LoadContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+    SecureContext_SaveContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s
new file mode 100644
index 0000000..d2c599d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s
@@ -0,0 +1,73 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+
+	PUBLIC SecureContext_LoadContextAsm
+	PUBLIC SecureContext_SaveContextAsm
+/*-----------------------------------------------------------*/
+
+SecureContext_LoadContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+#if ( configENABLE_MPU == 1 )
+	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
+	msr control, r3							/* CONTROL = r3. */
+#endif /* configENABLE_MPU */
+	msr psplim, r2							/* PSPLIM = r2. */
+	msr psp, r1								/* PSP = r1. */
+
+	load_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+SecureContext_SaveContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	mrs r1, psp								/* r1 = PSP. */
+#if ( configENABLE_FPU == 1 )
+	vstmdb r1!, {s0}						/* Trigger the defferred stacking of FPU registers. */
+	vldmia r1!, {s0}						/* Nullify the effect of the pervious statement. */
+#endif /* configENABLE_FPU */
+#if ( configENABLE_MPU == 1 )
+	mrs r2, control							/* r2 = CONTROL. */
+	stmdb r1!, {r2}							/* Store CONTROL value on the stack. */
+#endif /* configENABLE_MPU */
+	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	movs r1, #0								/* r1 = securecontextNO_STACK. */
+	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
+	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+
+	save_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.c
new file mode 100644
index 0000000..046bf4e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.c
@@ -0,0 +1,206 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED      0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED    0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
+    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */
+    uint8_t * pucStackStart;          /**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* No stack for thread mode until a task's context is loaded. */
+        secureportSET_PSPLIM( securecontextNO_STACK );
+        secureportSET_PSP( securecontextNO_STACK );
+
+        #if ( configENABLE_MPU == 1 )
+            {
+                /* Configure thread mode to use PSP and to be unprivileged. */
+                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+            }
+        #else /* configENABLE_MPU */
+            {
+                /* Configure thread mode to use PSP and to be privileged.. */
+                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+            }
+        #endif /* configENABLE_MPU */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+                                                                                       uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+    uint8_t * pucStackMemory = NULL;
+    uint32_t ulIPSR;
+    SecureContextHandle_t xSecureContextHandle = NULL;
+
+    #if ( configENABLE_MPU == 1 )
+        uint32_t * pulCurrentStackPointer = NULL;
+    #endif /* configENABLE_MPU */
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* Allocate the context structure. */
+        xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+        if( xSecureContextHandle != NULL )
+        {
+            /* Allocate the stack space. */
+            pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+            if( pucStackMemory != NULL )
+            {
+                /* Since stack grows down, the starting point will be the last
+                 * location. Note that this location is next to the last
+                 * allocated byte because the hardware decrements the stack
+                 * pointer before writing i.e. if stack pointer is 0x2, a push
+                 * operation will decrement the stack pointer to 0x1 and then
+                 * write at 0x1. */
+                xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+                /* The stack cannot go beyond this location. This value is
+                 * programmed in the PSPLIM register on context switch.*/
+                xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+                #if ( configENABLE_MPU == 1 )
+                    {
+                        /* Store the correct CONTROL value for the task on the stack.
+                         * This value is programmed in the CONTROL register on
+                         * context switch. */
+                        pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+                        pulCurrentStackPointer--;
+
+                        if( ulIsTaskPrivileged )
+                        {
+                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+                        }
+                        else
+                        {
+                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                        }
+
+                        /* Store the current stack pointer. This value is programmed in
+                         * the PSP register on context switch. */
+                        xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                    }
+                #else /* configENABLE_MPU */
+                    {
+                        /* Current SP is set to the starting of the stack. This
+                         * value programmed in the PSP register on context switch. */
+                        xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+                    }
+                #endif /* configENABLE_MPU */
+            }
+            else
+            {
+                /* Free the context to avoid memory leak and make sure to return
+                 * NULL to indicate failure. */
+                vPortFree( xSecureContextHandle );
+                xSecureContextHandle = NULL;
+            }
+        }
+    }
+
+    return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* Ensure that valid parameters are passed. */
+        secureportASSERT( xSecureContextHandle != NULL );
+
+        /* Free the stack space. */
+        vPortFree( xSecureContextHandle->pucStackLimit );
+
+        /* Free the context itself. */
+        vPortFree( xSecureContextHandle );
+    }
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.h
new file mode 100644
index 0000000..532a407
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.h
@@ -0,0 +1,112 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK    0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext * SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if ( configENABLE_MPU == 1 )
+    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+                                                         uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.c
new file mode 100644
index 0000000..82dbd9e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.c
@@ -0,0 +1,454 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+    #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+    #define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+    #define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
+
+/* The application writer has already defined the array used for the RTOS
+* heap - probably so it can be placed in a special segment or address. */
+    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
+    size_t xBlockSize;                     /**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, * pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+    BlockLink_t * pxFirstFreeBlock;
+    uint8_t * pucAlignedHeap;
+    size_t uxAddress;
+    size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+    /* Ensure the heap starts on a correctly aligned boundary. */
+    uxAddress = ( size_t ) ucHeap;
+
+    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+    {
+        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+    }
+
+    pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+    /* xStart is used to hold a pointer to the first item in the list of free
+     * blocks.  The void cast is used to prevent compiler warnings. */
+    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+    xStart.xBlockSize = ( size_t ) 0;
+
+    /* pxEnd is used to mark the end of the list of free blocks and is inserted
+     * at the end of the heap space. */
+    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+    uxAddress -= xHeapStructSize;
+    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+    pxEnd = ( void * ) uxAddress;
+    pxEnd->xBlockSize = 0;
+    pxEnd->pxNextFreeBlock = NULL;
+
+    /* To start with there is a single free block that is sized to take up the
+     * entire heap space, minus the space taken by pxEnd. */
+    pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+    /* Only one block exists - and it covers the entire usable heap space. */
+    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+    /* Work out the position of the top bit in a size_t variable. */
+    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
+{
+    BlockLink_t * pxIterator;
+    uint8_t * puc;
+
+    /* Iterate through the list until a block is found that has a higher address
+     * than the block being inserted. */
+    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+    {
+        /* Nothing to do here, just iterate to the right position. */
+    }
+
+    /* Do the block being inserted, and the block it is being inserted after
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxIterator;
+
+    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+    {
+        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+        pxBlockToInsert = pxIterator;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Do the block being inserted, and the block it is being inserted before
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxBlockToInsert;
+
+    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+    {
+        if( pxIterator->pxNextFreeBlock != pxEnd )
+        {
+            /* Form one big block from the two blocks. */
+            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+        }
+        else
+        {
+            pxBlockToInsert->pxNextFreeBlock = pxEnd;
+        }
+    }
+    else
+    {
+        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+    }
+
+    /* If the block being inserted plugged a gab, so was merged with the block
+     * before and the block after, then it's pxNextFreeBlock pointer will have
+     * already been set, and should not be set here as that would make it point
+     * to itself. */
+    if( pxIterator != pxBlockToInsert )
+    {
+        pxIterator->pxNextFreeBlock = pxBlockToInsert;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void * pvPortMalloc( size_t xWantedSize )
+{
+    BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
+    void * pvReturn = NULL;
+
+    /* If this is the first call to malloc then the heap will require
+     * initialisation to setup the list of free blocks. */
+    if( pxEnd == NULL )
+    {
+        prvHeapInit();
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    {
+        /* The wanted size is increased so it can contain a BlockLink_t
+         * structure in addition to the requested amount of bytes. */
+        if( xWantedSize > 0 )
+        {
+            xWantedSize += xHeapStructSize;
+
+            /* Ensure that blocks are always aligned to the required number of
+             * bytes. */
+            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+            {
+                /* Byte alignment required. */
+                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+        {
+            /* Traverse the list from the start (lowest address) block until
+             * one of adequate size is found. */
+            pxPreviousBlock = &xStart;
+            pxBlock = xStart.pxNextFreeBlock;
+
+            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+            {
+                pxPreviousBlock = pxBlock;
+                pxBlock = pxBlock->pxNextFreeBlock;
+            }
+
+            /* If the end marker was reached then a block of adequate size was
+             * not found. */
+            if( pxBlock != pxEnd )
+            {
+                /* Return the memory space pointed to - jumping over the
+                 * BlockLink_t structure at its start. */
+                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+                /* This block is being returned for use so must be taken out
+                 * of the list of free blocks. */
+                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+                /* If the block is larger than required it can be split into
+                 * two. */
+                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+                {
+                    /* This block is to be split into two.  Create a new
+                     * block following the number of bytes requested. The void
+                     * cast is used to prevent byte alignment warnings from the
+                     * compiler. */
+                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+                    /* Calculate the sizes of two blocks split from the single
+                     * block. */
+                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+                    pxBlock->xBlockSize = xWantedSize;
+
+                    /* Insert the new block into the list of free blocks. */
+                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+                {
+                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                /* The block is being returned - it is allocated and owned by
+                 * the application and has no "next" block. */
+                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                pxBlock->pxNextFreeBlock = NULL;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    traceMALLOC( pvReturn, xWantedSize );
+
+    #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+        {
+            if( pvReturn == NULL )
+            {
+                extern void vApplicationMallocFailedHook( void );
+                vApplicationMallocFailedHook();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
+
+    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+    return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void * pv )
+{
+    uint8_t * puc = ( uint8_t * ) pv;
+    BlockLink_t * pxLink;
+
+    if( pv != NULL )
+    {
+        /* The memory being freed will have an BlockLink_t structure immediately
+         * before it. */
+        puc -= xHeapStructSize;
+
+        /* This casting is to keep the compiler from issuing warnings. */
+        pxLink = ( void * ) puc;
+
+        /* Check the block is actually allocated. */
+        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        {
+            if( pxLink->pxNextFreeBlock == NULL )
+            {
+                /* The block is being returned to the heap - it is no longer
+                 * allocated. */
+                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+                secureportDISABLE_NON_SECURE_INTERRUPTS();
+                {
+                    /* Add this block to the list of free blocks. */
+                    xFreeBytesRemaining += pxLink->xBlockSize;
+                    traceFREE( pv, pxLink->xBlockSize );
+                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+                }
+                secureportENABLE_NON_SECURE_INTERRUPTS();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+    return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+    return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+    /* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.h
new file mode 100644
index 0000000..fa78046
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void * pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void * pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.c
new file mode 100644
index 0000000..4e6018d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS          ( 29UL )
+#define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS              ( 26UL )
+#define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS            ( 10UL )
+#define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS            ( 11UL )
+#define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+                                   ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+                                   ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
+    }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+         * permitted. CP11 should be programmed to the same value as CP10. */
+        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+         * that we can enable/disable lazy stacking in port.c file. */
+        *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
+
+        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+         * registers (S16-S31) are also pushed to stack on exception entry and
+         * restored on exception return. */
+        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+    }
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.h
new file mode 100644
index 0000000..39deb36
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/macros/secure_port_macros.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/macros/secure_port_macros.h
new file mode 100644
index 0000000..7b8dbed
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ARMv8M/secure/macros/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT         8
+#define secureportBYTE_ALIGNMENT_MASK    ( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+    #define secureportNON_SECURE_CALLABLE    __cmse_nonsecure_entry __root
+#else
+    #define secureportNON_SECURE_CALLABLE    __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+    __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+    __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+    __asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+    __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+    __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+    __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+    __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+    __asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL     0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS()     secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x )                      \
+    if( ( x ) == 0 )                               \
+    {                                              \
+        secureportDISABLE_SECURE_INTERRUPTS();     \
+        secureportDISABLE_NON_SECURE_INTERRUPTS(); \
+        for( ; ; ) {; }                            \
+    }
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/port.c
new file mode 100644
index 0000000..dba83d2
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/port.c
@@ -0,0 +1,244 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V1.00:
+
+	+ Call to taskYIELD() from within tick ISR has been replaced by the more
+	  efficient portSWITCH_CONTEXT().
+	+ ISR function definitions renamed to include the prv prefix.
+
+Changes from V2.6.1
+
+	+ Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+	  macro to be consistent with the later ports.
+*/
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Flashlite 186
+ * port.
+ *----------------------------------------------------------*/
+
+#include <dos.h>
+#include <stdlib.h>
+#include <setjmp.h>
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portasm.h"
+
+/*lint -e950 Non ANSI reserved words okay in this file only. */
+
+#define portTIMER_EOI_TYPE		( 8 )
+#define portRESET_PIC()			portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
+#define portTIMER_INT_NUMBER	0x12
+
+#define portTIMER_1_CONTROL_REGISTER	( ( uint16_t ) 0xff5e )
+#define portTIMER_0_CONTROL_REGISTER	( ( uint16_t ) 0xff56 )
+#define portTIMER_INTERRUPT_ENABLE		( ( uint16_t ) 0x2000 )
+
+/* Setup the hardware to generate the required tick frequency. */
+static void prvSetTickFrequency( uint32_t ulTickRateHz );
+
+/* Set the hardware back to the state as per before the scheduler started. */
+static void prvExitFunction( void );
+
+/* The ISR used depends on whether the preemptive or cooperative scheduler
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+	/* Tick service routine used by the scheduler when preemptive scheduling is
+	being used. */
+	static void __interrupt __far prvPreemptiveTick( void );
+#else
+	/* Tick service routine used by the scheduler when cooperative scheduling is
+	being used. */
+	static void __interrupt __far prvNonPreemptiveTick( void );
+#endif
+
+/* Trap routine used by taskYIELD() to manually cause a context switch. */
+static void __interrupt __far prvYieldProcessor( void );
+
+/*lint -e956 File scopes necessary here. */
+
+/* Set true when the vectors are set so the scheduler will service the tick. */
+static BaseType_t xSchedulerRunning = pdFALSE;
+
+/* Points to the original routine installed on the vector we use for manual
+context switches.  This is then used to restore the original routine during
+prvExitFunction(). */
+static void ( __interrupt __far *pxOldSwitchISR )();
+
+/* Used to restore the original DOS context when the scheduler is ended. */
+static jmp_buf xJumpBuf;
+
+/*lint +e956 */
+
+/*-----------------------------------------------------------*/
+BaseType_t xPortStartScheduler( void )
+{
+	/* This is called with interrupts already disabled. */
+
+	/* Remember what was on the interrupts we are going to use
+	so we can put them back later if required. */
+	pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
+
+	/* Put our manual switch (yield) function on a known
+	vector. */
+	_dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+
+	#if( configUSE_PREEMPTION == 1 )
+	{
+		/* Put our tick switch function on the timer interrupt. */
+		_dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
+	}
+	#else
+	{
+		/* We want the timer interrupt to just increment the tick count. */
+		_dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
+	}
+	#endif
+
+	prvSetTickFrequency( configTICK_RATE_HZ );
+
+	/* Clean up function if we want to return to DOS. */
+	if( setjmp( xJumpBuf ) != 0 )
+	{
+		prvExitFunction();
+		xSchedulerRunning = pdFALSE;
+	}
+	else
+	{
+		xSchedulerRunning = pdTRUE;
+
+		/* Kick off the scheduler by setting up the context of the first task. */
+		portFIRST_CONTEXT();
+	}
+
+	return xSchedulerRunning;
+}
+/*-----------------------------------------------------------*/
+
+/* The ISR used depends on whether the preemptive or cooperative scheduler
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+	static void __interrupt __far prvPreemptiveTick( void )
+	{
+		/* Get the scheduler to update the task states following the tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Switch in the context of the next task to be run. */
+			portSWITCH_CONTEXT();
+		}
+
+		/* Reset the PIC ready for the next time. */
+		portRESET_PIC();
+	}
+#else
+	static void __interrupt __far prvNonPreemptiveTick( void )
+	{
+		/* Same as preemptive tick, but the cooperative scheduler is being used
+		so we don't have to switch in the context of the next task. */
+		xTaskIncrementTick();
+		portRESET_PIC();
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+static void __interrupt __far prvYieldProcessor( void )
+{
+	/* Switch in the context of the next task to be run. */
+	portSWITCH_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Jump back to the processor state prior to starting the
+	scheduler.  This means we are not going to be using a
+	task stack frame so the task can be deleted. */
+	longjmp( xJumpBuf, 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvExitFunction( void )
+{
+const uint16_t usTimerDisable = 0x0000;
+uint16_t usTimer0Control;
+
+	/* Interrupts should be disabled here anyway - but no
+	harm in making sure. */
+	portDISABLE_INTERRUPTS();
+	if( xSchedulerRunning == pdTRUE )
+	{
+		/* Put back the switch interrupt routines that was in place
+		before the scheduler started. */
+		_dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
+	}
+
+	/* Disable the timer used for the tick to ensure the scheduler is
+	not called before restoring interrupts.  There was previously nothing
+	on this timer so there is no old ISR to restore. */
+	portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );
+
+	/* Restart the DOS tick. */
+	usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
+	usTimer0Control |= portTIMER_INTERRUPT_ENABLE;
+	portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
+
+
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetTickFrequency( uint32_t ulTickRateHz )
+{
+const uint16_t usMaxCountRegister = 0xff5a;
+const uint16_t usTimerPriorityRegister = 0xff32;
+const uint16_t usTimerEnable = 0xC000;
+const uint16_t usRetrigger = 0x0001;
+const uint16_t usTimerHighPriority = 0x0000;
+uint16_t usTimer0Control;
+
+/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */
+
+const uint32_t ulClockFrequency = ( uint32_t ) 0x7f31a0UL;
+
+uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
+
+	portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger );
+	portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount );
+	portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority );
+
+	/* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */
+	usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
+	usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE;
+	portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
+}
+
+
+/*lint +e950 */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h
new file mode 100644
index 0000000..57ae421
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h
@@ -0,0 +1,97 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		long
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	portSHORT
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#define portENTER_CRITICAL()			__asm{ pushf }  \
+										__asm{ cli 	 }	\
+
+#define portEXIT_CRITICAL()				__asm{ popf }
+
+#define portDISABLE_INTERRUPTS()		__asm{ cli }
+
+#define portENABLE_INTERRUPTS()			__asm{ sti }
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portNOP()						__asm{ nop }
+#define portSTACK_GROWTH				( -1 )
+#define portSWITCH_INT_NUMBER 			0x80
+#define portYIELD()						__asm{ int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS		( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT      2
+#define portINITIAL_SW		( ( portSTACK_TYPE ) 0x0202 )	/* Start the tasks with interrupts enabled. */
+/*-----------------------------------------------------------*/
+
+/* Compiler specifics. */
+#define portINPUT_BYTE( xAddr )				inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )	outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr )				inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue )	outpw( xAddr, usValue )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/PC/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/PC/port.c
new file mode 100644
index 0000000..c837ad7
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/PC/port.c
@@ -0,0 +1,288 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V2.6.1
+
+	+ Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+	  macro to be consistent with the later ports.
+
+Changes from V4.0.1
+	
+	+ Add function prvSetTickFrequencyDefault() to set the DOS tick back to
+	  its proper value when the scheduler exits. 
+*/
+
+#include <stdlib.h>
+#include <dos.h>
+#include <setjmp.h>
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portasm.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the industrial
+ * PC port.
+ *----------------------------------------------------------*/
+
+/*lint -e950 Non ANSI reserved words okay in this file only. */
+
+#define portTIMER_INT_NUMBER	0x08
+
+/* Setup hardware for required tick interrupt rate. */
+static void prvSetTickFrequency( uint32_t ulTickRateHz );
+
+/* Restore hardware to as it was prior to starting the scheduler. */
+static void prvExitFunction( void );
+
+/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC
+directly.  We chain to the DOS tick as close as possible to the standard DOS
+tick rate. */
+static void prvPortResetPIC( void );
+
+/* The ISR used depends on whether the preemptive or cooperative
+scheduler is being used. */
+#if( configUSE_PREEMPTION == 1 )
+	/* Tick service routine used by the scheduler when preemptive scheduling is
+	being used. */
+	static void __interrupt __far prvPreemptiveTick( void );
+#else
+	/* Tick service routine used by the scheduler when cooperative scheduling is
+	being used. */
+	static void __interrupt __far prvNonPreemptiveTick( void );
+#endif
+
+/* Trap routine used by taskYIELD() to manually cause a context switch. */
+static void __interrupt __far prvYieldProcessor( void );
+
+/* Set the tick frequency back so the floppy drive works correctly when the
+scheduler exits. */
+static void prvSetTickFrequencyDefault( void );
+
+/*lint -e956 File scopes necessary here. */
+
+/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */
+static int16_t sDOSTickCounter;
+
+/* Set true when the vectors are set so the scheduler will service the tick. */
+static BaseType_t xSchedulerRunning = pdFALSE;				
+
+/* Points to the original routine installed on the vector we use for manual context switches.  This is then used to restore the original routine during prvExitFunction(). */
+static void ( __interrupt __far *pxOldSwitchISR )();		
+
+/* Points to the original routine installed on the vector we use to chain to the DOS tick.  This is then used to restore the original routine during prvExitFunction(). */
+static void ( __interrupt __far *pxOldSwitchISRPlus1 )();	
+
+/* Used to restore the original DOS context when the scheduler is ended. */
+static jmp_buf xJumpBuf;
+
+/*lint +e956 */
+
+/*-----------------------------------------------------------*/
+BaseType_t xPortStartScheduler( void )
+{
+pxISR pxOriginalTickISR;
+	
+	/* This is called with interrupts already disabled. */
+
+	/* Remember what was on the interrupts we are going to use
+	so we can put them back later if required. */
+	pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
+	pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );
+	pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
+
+	prvSetTickFrequency( configTICK_RATE_HZ );
+
+	/* Put our manual switch (yield) function on a known
+	vector. */
+	_dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+
+	/* Put the old tick on a different interrupt number so we can
+	call it when we want. */
+	_dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );
+
+	/* The ISR used depends on whether the preemptive or cooperative
+	scheduler is being used. */
+	#if( configUSE_PREEMPTION == 1 )
+	{
+		/* Put our tick switch function on the timer interrupt. */
+		_dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
+	}
+	#else
+	{
+		/* We want the timer interrupt to just increment the tick count. */
+		_dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
+	}
+    #endif
+
+	/* Setup a counter that is used to call the DOS interrupt as close
+	to it's original frequency as can be achieved given our chosen tick
+	frequency. */
+	sDOSTickCounter = portTICKS_PER_DOS_TICK;
+
+	/* Clean up function if we want to return to DOS. */
+	if( setjmp( xJumpBuf ) != 0 )
+	{
+		prvExitFunction();
+		xSchedulerRunning = pdFALSE;
+	}
+	else
+	{
+		xSchedulerRunning = pdTRUE;
+
+		/* Kick off the scheduler by setting up the context of the first task. */
+		portFIRST_CONTEXT();
+	}
+
+	return xSchedulerRunning;
+}
+/*-----------------------------------------------------------*/
+
+/* The ISR used depends on whether the preemptive or cooperative
+scheduler is being used. */
+#if( configUSE_PREEMPTION == 1 )
+	static void __interrupt __far prvPreemptiveTick( void )
+	{
+		/* Get the scheduler to update the task states following the tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Switch in the context of the next task to be run. */
+			portSWITCH_CONTEXT();
+		}
+
+		/* Reset the PIC ready for the next time. */
+		prvPortResetPIC();
+	}
+#else
+	static void __interrupt __far prvNonPreemptiveTick( void )
+	{
+		/* Same as preemptive tick, but the cooperative scheduler is being used
+		so we don't have to switch in the context of the next task. */
+		xTaskIncrementTick();
+		prvPortResetPIC();
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+static void __interrupt __far prvYieldProcessor( void )
+{
+	/* Switch in the context of the next task to be run. */
+	portSWITCH_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortResetPIC( void )
+{
+	/* We are going to call the DOS tick interrupt at as close a
+	frequency to the normal DOS tick as possible. */
+
+	/* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */
+	--sDOSTickCounter;
+	if( sDOSTickCounter <= 0 )
+	{
+		sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK;
+		__asm{ int	portSWITCH_INT_NUMBER + 1 };		 
+	}
+	else
+	{
+		/* Reset the PIC as the DOS tick is not being called to
+		do it. */
+		__asm
+		{
+			mov	al, 20H
+			out 20H, al
+		};
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Jump back to the processor state prior to starting the
+	scheduler.  This means we are not going to be using a
+	task stack frame so the task can be deleted. */
+	longjmp( xJumpBuf, 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvExitFunction( void )
+{
+void ( __interrupt __far *pxOriginalTickISR )();
+
+	/* Interrupts should be disabled here anyway - but no 
+	harm in making sure. */
+	portDISABLE_INTERRUPTS();
+	if( xSchedulerRunning == pdTRUE )
+	{
+		/* Set the DOS tick back onto the timer ticker. */
+		pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
+		_dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR );
+		prvSetTickFrequencyDefault();
+
+		/* Put back the switch interrupt routines that was in place
+		before the scheduler started. */
+		_dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
+		_dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );
+	}
+	/* The tick timer is back how DOS wants it.  We can re-enable
+	interrupts without the scheduler being called. */
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetTickFrequency( uint32_t ulTickRateHz )
+{
+const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+const uint16_t usPIT0 = ( uint16_t ) 0x40;
+const uint32_t ulPIT_CONST = ( uint32_t ) 1193180UL;
+const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+uint32_t ulOutput;
+
+	/* Setup the 8245 to tick at the wanted frequency. */
+	portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
+	ulOutput = ulPIT_CONST / ulTickRateHz;
+	portOUTPUT_BYTE( usPIT0, ( uint16_t )( ulOutput & ( uint32_t ) 0xff ) );
+	ulOutput >>= 8;
+	portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetTickFrequencyDefault( void )
+{
+const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+const uint16_t usPIT0 = ( uint16_t ) 0x40;
+const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+
+	portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
+	portOUTPUT_BYTE( usPIT0,0 );
+	portOUTPUT_BYTE( usPIT0,0 );
+}
+
+
+/*lint +e950 */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/PC/prtmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/PC/prtmacro.h
new file mode 100644
index 0000000..0daf400
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/PC/prtmacro.h
@@ -0,0 +1,97 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		long
+#define portDOUBLE		long
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	portSHORT
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portENTER_CRITICAL()			__asm{ pushf }  \
+										__asm{ cli 	 }	\
+
+#define portEXIT_CRITICAL()				__asm{ popf }
+
+#define portDISABLE_INTERRUPTS()		__asm{ cli }
+
+#define portENABLE_INTERRUPTS()			__asm{ sti }
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portNOP()				__asm{ nop }
+#define portSTACK_GROWTH		( -1 )
+#define portSWITCH_INT_NUMBER 	0x80
+#define portYIELD()				__asm{ int portSWITCH_INT_NUMBER }
+#define portDOS_TICK_RATE		( 18.20648 )
+#define portTICK_PERIOD_MS		( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portTICKS_PER_DOS_TICK	( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
+#define portINITIAL_SW			( ( portSTACK_TYPE ) 0x0202 )	/* Start the tasks with interrupts enabled. */
+#define portBYTE_ALIGNMENT		( 2 )
+/*-----------------------------------------------------------*/
+
+/* Compiler specifics. */
+#define portINPUT_BYTE( xAddr )				inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )	outp( xAddr, ucValue )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/common/portasm.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/common/portasm.h
new file mode 100644
index 0000000..83193de
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/common/portasm.h
@@ -0,0 +1,87 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORT_ASM_H
+#define PORT_ASM_H
+
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/*
+ * Saves the stack pointer for one task into its TCB, calls
+ * vTaskSwitchContext() to update the TCB being used, then restores the stack
+ * from the new TCB read to run the task.
+ */
+void portSWITCH_CONTEXT( void );
+
+/*
+ * Load the stack pointer from the TCB of the task which is going to be first
+ * to execute.  Then force an IRET so the registers and IP are popped off the
+ * stack.
+ */
+void portFIRST_CONTEXT( void );
+
+/* There are slightly different versions depending on whether you are building
+to include debugger information.  If debugger information is used then there
+are a couple of extra bytes left of the ISR stack (presumably for use by the
+debugger).  The true stack pointer is then stored in the bp register.  We add
+2 to the stack pointer to remove the extra bytes before we restore our context. */
+
+#define portSWITCH_CONTEXT()											\
+							asm { mov	ax, seg pxCurrentTCB		}	\
+							asm { mov	ds, ax						}	\
+							asm { les	bx, pxCurrentTCB			}	/* Save the stack pointer into the TCB. */		\
+							asm { mov	es:0x2[ bx ], ss			}	\
+							asm { mov	es:[ bx ], sp				}	\
+							asm { call  far ptr vTaskSwitchContext	}	/* Perform the switch. */						\
+							asm { mov	ax, seg pxCurrentTCB		}	/* Restore the stack pointer from the TCB. */	\
+							asm { mov	ds, ax						}	\
+							asm { les	bx, dword ptr pxCurrentTCB	}	\
+							asm { mov	ss, es:[ bx + 2 ]			}	\
+							asm { mov	sp, es:[ bx ]				}
+
+#define portFIRST_CONTEXT()												\
+							__asm { mov	ax, seg pxCurrentTCB		}	\
+							__asm { mov	ds, ax						}	\
+							__asm { les	bx, dword ptr pxCurrentTCB	}	\
+							__asm { mov	ss, es:[ bx + 2 ]			}	\
+							__asm { mov	sp, es:[ bx ]				}	\
+							__asm { pop	bp							}	\
+							__asm { pop	di							}	\
+							__asm { pop	si							}	\
+							__asm { pop	ds							}	\
+							__asm { pop	es							}	\
+							__asm { pop	dx							}	\
+							__asm { pop	cx							}	\
+							__asm { pop	bx							}	\
+							__asm { pop	ax							}	\
+							__asm { iret							}
+
+
+#endif
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/common/portcomn.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/common/portcomn.c
new file mode 100644
index 0000000..be7e2e1
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/BCC/16BitDOS/common/portcomn.c
@@ -0,0 +1,120 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V1.00:
+
+	+ pxPortInitialiseStack() now initialises the stack of new tasks to the
+	  same format used by the compiler.  This allows the compiler generated
+	  interrupt mechanism to be used for context switches.
+
+Changes from V2.6.1
+
+	+ Move usPortCheckFreeStackSpace() to tasks.c.
+*/
+
+
+#include <dos.h>
+#include <stdlib.h>
+#include "FreeRTOS.h"
+
+/*-----------------------------------------------------------*/
+
+/* See header file for description. */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t DS_Reg = 0;
+
+	/* Place a few bytes of known values on the bottom of the stack.
+	This is just useful for debugging. */
+
+	*pxTopOfStack = 0x1111;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2222;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x3333;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x4444;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x5555;
+	pxTopOfStack--;
+
+
+	/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+
+	/* We are going to start the scheduler using a return from interrupt
+	instruction to load the program counter, so first there would be the
+	function call with parameters preamble. */
+	
+	*pxTopOfStack = FP_SEG( pvParameters );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pvParameters );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_SEG( pxCode );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pxCode );
+	pxTopOfStack--;
+
+	/* Next the status register and interrupt return address. */
+	*pxTopOfStack = portINITIAL_SW; 
+	pxTopOfStack--;
+	*pxTopOfStack = FP_SEG( pxCode );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pxCode );
+	pxTopOfStack--;
+
+	/* The remaining registers would be pushed on the stack by our context
+	switch function.  These are loaded with values simply to make debugging
+	easier. */
+	*pxTopOfStack = ( StackType_t ) 0xAAAA;	/* AX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xCCCC;	/* CX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xEEEE;	/* ES */
+	pxTopOfStack--;
+
+	/* We need the true data segment. */
+	__asm{	MOV DS_Reg, DS };
+
+	*pxTopOfStack = DS_Reg;						/* DS */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0123;	/* SI */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DI */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BP */
+
+	/*lint +e950 +e611 +e923 */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM3/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM3/port.c
new file mode 100644
index 0000000..790b262
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM3/port.c
@@ -0,0 +1,607 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM3 port.
+*----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
+    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
+#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                    ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK                   ( 0xFFUL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                      ( 0x01000000 )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#define portMISSED_COUNTS_FACTOR              ( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortSysTickHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Required to allow portasm.asm access the configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * setting. */
+const uint32_t ulMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+
+    /* Offset added to account for the way the MCU uses the stack on entry/exit
+     * of interrupts, and to ensure alignment. */
+    pxTopOfStack--;
+
+    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) prvTaskExitError;                    /* LR */
+
+    /* Save code space by skipping register initialisation. */
+    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+    pxTopOfStack -= 8;                            /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( uxCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    for( ; ; )
+    {
+    }
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+            volatile uint8_t ucMaxPriorityValue;
+
+            /* Determine the maximum priority from which ISR safe FreeRTOS API
+             * functions can be called.  ISR safe functions are those that end in
+             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+             * ensure interrupt entry is as fast and simple as possible.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+            /* Determine the number of priority bits available.  First write to all
+             * possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+            /* Use the same mask on the maximum system call priority. */
+            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+            /* Calculate the maximum acceptable priority group value for the number
+             * of bits read back. */
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+            {
+                ulMaxPRIGROUPValue--;
+                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+            }
+
+            #ifdef __NVIC_PRIO_BITS
+                {
+                    /* Check the CMSIS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+                }
+            #endif
+
+            #ifdef configPRIO_BITS
+                {
+                    /* Check the FreeRTOS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+                }
+            #endif
+
+            /* Shift the priority group value back to its position within the AIRCR
+             * register. */
+            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* conifgASSERT_DEFINED */
+
+    /* Make PendSV and SysTick the lowest priority interrupts. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Start the first task. */
+    vPortStartFirstTask();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
+    if( uxCriticalNesting == 1 )
+    {
+        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+     * executes all interrupts must be unmasked.  There is therefore no need to
+     * save and then restore the interrupt mask value as its value is already
+     * known. */
+    ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* A context switch is required.  Context switching is performed in
+             * the PendSV interrupt.  Pend the PendSV interrupt. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+    #pragma WEAK( vPortSuppressTicksAndSleep )
+    void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+         * is accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods.  -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm( "	cpsid i");
+        __asm( "	dsb");
+        __asm( "	isb");
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above __disable_interrupt()
+             * call above. */
+            __asm( "	cpsie i");
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again.  However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm( "	dsb");
+                __asm( "	wfi");
+                __asm( "	isb");
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately.  see comments above
+             * __disable_interrupt() call above. */
+            __asm( "	cpsie i");
+            __asm( "	dsb");
+            __asm( "	isb");
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __asm( "	cpsid i");
+            __asm( "	dsb");
+            __asm( "	isb");
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is yet
+             * to count to zero (in which case an interrupt other than the SysTick
+             * must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __asm( "	cpsie i");
+        }
+    }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+#pragma WEAK( vPortSetupTimerInterrupt )
+void vPortSetupTimerInterrupt( void )
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and clear the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+    void vPortValidateInterruptPriority( void )
+    {
+        extern uint32_t ulPortGetIPSR( void );
+        uint32_t ulCurrentInterrupt;
+        uint8_t ucCurrentPriority;
+
+        ulCurrentInterrupt = ulPortGetIPSR();
+
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that	use the FreeRTOS API must not be left at their
+             * default priority of	zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and	therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
+
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredictable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
+
+#endif /* configASSERT_DEFINED */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM3/portasm.asm b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM3/portasm.asm
new file mode 100644
index 0000000..940e1b0
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM3/portasm.asm
@@ -0,0 +1,144 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	.thumb
+
+	.ref pxCurrentTCB
+	.ref vTaskSwitchContext
+	.ref ulMaxSyscallInterruptPriority
+
+	.def xPortPendSVHandler
+	.def ulPortGetIPSR
+	.def vPortSVCHandler
+	.def vPortStartFirstTask
+
+NVICOffsetConst:					.word 	0xE000ED08
+CPACRConst:							.word 	0xE000ED88
+pxCurrentTCBConst:					.word	pxCurrentTCB
+ulMaxSyscallInterruptPriorityConst: .word ulMaxSyscallInterruptPriority
+
+; -----------------------------------------------------------
+
+	.align 4
+ulPortGetIPSR: .asmfunc
+ 	mrs r0, ipsr
+ 	bx r14
+ 	.endasmfunc
+ ; -----------------------------------------------------------
+
+	.align 4
+vPortSetInterruptMask: .asmfunc
+	push {r0}
+	ldr r0, ulMaxSyscallInterruptPriorityConst
+	msr basepri, r0
+	pop {r0}
+	bx r14
+	.endasmfunc
+; -----------------------------------------------------------
+
+	.align 4
+xPortPendSVHandler: .asmfunc
+	mrs r0, psp
+	isb
+
+	;/* Get the location of the current TCB. */
+	ldr	r3, pxCurrentTCBConst
+	ldr	r2, [r3]
+
+	;/* Save the core registers. */
+	stmdb r0!, {r4-r11}
+
+	;/* Save the new top of stack into the first member of the TCB. */
+	str r0, [r2]
+
+	stmdb sp!, {r3, r14}
+	ldr r0, ulMaxSyscallInterruptPriorityConst
+	ldr r1, [r0]
+	msr basepri, r1
+	dsb
+	isb
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r3, r14}
+
+	;/* The first item in pxCurrentTCB is the task top of stack. */
+	ldr r1, [r3]
+	ldr r0, [r1]
+
+	;/* Pop the core registers. */
+	ldmia r0!, {r4-r11}
+
+	msr psp, r0
+	isb
+	bx r14
+	.endasmfunc
+
+; -----------------------------------------------------------
+
+	.align 4
+vPortSVCHandler: .asmfunc
+	;/* Get the location of the current TCB. */
+	ldr	r3, pxCurrentTCBConst
+	ldr r1, [r3]
+	ldr r0, [r1]
+	;/* Pop the core registers. */
+	ldmia r0!, {r4-r11}
+	msr psp, r0
+	isb
+	mov r0, #0
+	msr	basepri, r0
+	orr r14, #0xd
+	bx r14
+	.endasmfunc
+
+; -----------------------------------------------------------
+
+	.align 4
+vPortStartFirstTask: .asmfunc
+	;/* Use the NVIC offset register to locate the stack. */
+	ldr r0, NVICOffsetConst
+	ldr r0, [r0]
+	ldr r0, [r0]
+	;/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	;/* Clear the bit that indicates the FPU is in use in case the FPU was used
+	;before the scheduler was started - which would otherwise result in the
+	;unnecessary leaving of space in the SVC stack for lazy saving of FPU
+	;registers. */
+	mov r0, #0
+	msr control, r0
+	;/* Call SVC to start the first task. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	svc #0
+	.endasmfunc
+
+; -----------------------------------------------------------
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM3/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM3/portmacro.h
new file mode 100644
index 0000000..3bbf3ce
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM3/portmacro.h
@@ -0,0 +1,170 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
+
+/*-----------------------------------------------------------*/
+
+/* Compiler directives. */
+    #define portWEAK_SYMBOL    __attribute__( ( weak ) )
+
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+    #define portYIELD()                                 \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        __asm( "	dsb");                                \
+        __asm( "	isb");                                \
+    }
+
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired != pdFALSE ) portYIELD()
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #endif
+
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
+
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
+
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+
+    #define portDISABLE_INTERRUPTS()                                     \
+    {                                                                    \
+        _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
+        __asm( "	dsb");                                                 \
+        __asm( "	isb");                                                 \
+    }
+
+    #define portENABLE_INTERRUPTS()                   _set_interrupt_priority( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( "	dsb" ); __asm( "	isb")
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    _set_interrupt_priority( x )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
+
+/* portNOP() is not required by this port. */
+    #define portNOP()
+
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM4F/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM4F/port.c
new file mode 100644
index 0000000..15fcdc5
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM4F/port.c
@@ -0,0 +1,632 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM4F port.
+*----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __TI_VFP_SUPPORT__
+    #error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
+    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
+#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                    ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK                   ( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR                             ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS              ( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                      ( 0x01000000 )
+#define portINITIAL_EXC_RETURN                ( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#define portMISSED_COUNTS_FACTOR              ( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortSysTickHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Turn the VFP on.
+ */
+extern void vPortEnableVFP( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Required to allow portasm.asm access the configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * setting. */
+const uint32_t ulMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+
+    /* Offset added to account for the way the MCU uses the stack on entry/exit
+     * of interrupts, and to ensure alignment. */
+    pxTopOfStack--;
+
+    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) prvTaskExitError;                    /* LR */
+
+    /* Save code space by skipping register initialisation. */
+    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+    /* A save method is being used that requires each task to maintain its
+     * own exec return value. */
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+    pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( uxCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    for( ; ; )
+    {
+    }
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+            volatile uint8_t ucMaxPriorityValue;
+
+            /* Determine the maximum priority from which ISR safe FreeRTOS API
+             * functions can be called.  ISR safe functions are those that end in
+             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+             * ensure interrupt entry is as fast and simple as possible.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+            /* Determine the number of priority bits available.  First write to all
+             * possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+            /* Use the same mask on the maximum system call priority. */
+            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+            /* Calculate the maximum acceptable priority group value for the number
+             * of bits read back. */
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+            {
+                ulMaxPRIGROUPValue--;
+                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+            }
+
+            #ifdef __NVIC_PRIO_BITS
+                {
+                    /* Check the CMSIS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+                }
+            #endif
+
+            #ifdef configPRIO_BITS
+                {
+                    /* Check the FreeRTOS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+                }
+            #endif
+
+            /* Shift the priority group value back to its position within the AIRCR
+             * register. */
+            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* conifgASSERT_DEFINED */
+
+    /* Make PendSV and SysTick the lowest priority interrupts. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Ensure the VFP is enabled - it should be anyway. */
+    vPortEnableVFP();
+
+    /* Lazy save always. */
+    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+    /* Start the first task. */
+    vPortStartFirstTask();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
+    if( uxCriticalNesting == 1 )
+    {
+        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+     * executes all interrupts must be unmasked.  There is therefore no need to
+     * save and then restore the interrupt mask value as its value is already
+     * known. */
+    ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* A context switch is required.  Context switching is performed in
+             * the PendSV interrupt.  Pend the PendSV interrupt. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+    #pragma WEAK( vPortSuppressTicksAndSleep )
+    void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+         * is accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods.  -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm( "	cpsid i");
+        __asm( "	dsb");
+        __asm( "	isb");
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above __disable_interrupt()
+             * call above. */
+            __asm( "	cpsie i");
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again.  However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm( "	dsb");
+                __asm( "	wfi");
+                __asm( "	isb");
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately.  see comments above
+             * __disable_interrupt() call above. */
+            __asm( "	cpsie i");
+            __asm( "	dsb");
+            __asm( "	isb");
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __asm( "	cpsid i");
+            __asm( "	dsb");
+            __asm( "	isb");
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is yet
+             * to count to zero (in which case an interrupt other than the SysTick
+             * must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __asm( "	cpsie i");
+        }
+    }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+#pragma WEAK( vPortSetupTimerInterrupt )
+void vPortSetupTimerInterrupt( void )
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and clear the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+    void vPortValidateInterruptPriority( void )
+    {
+        extern uint32_t ulPortGetIPSR( void );
+        uint32_t ulCurrentInterrupt;
+        uint8_t ucCurrentPriority;
+
+        ulCurrentInterrupt = ulPortGetIPSR();
+
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that	use the FreeRTOS API must not be left at their
+             * default priority of	zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and	therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
+
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredictable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
+
+#endif /* configASSERT_DEFINED */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM4F/portasm.asm b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM4F/portasm.asm
new file mode 100644
index 0000000..20cbdd4
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM4F/portasm.asm
@@ -0,0 +1,171 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	.thumb
+
+	.ref pxCurrentTCB
+	.ref vTaskSwitchContext
+	.ref ulMaxSyscallInterruptPriority
+
+	.def xPortPendSVHandler
+	.def ulPortGetIPSR
+	.def vPortSVCHandler
+	.def vPortStartFirstTask
+	.def vPortEnableVFP
+
+NVICOffsetConst:					.word 	0xE000ED08
+CPACRConst:							.word 	0xE000ED88
+pxCurrentTCBConst:					.word	pxCurrentTCB
+ulMaxSyscallInterruptPriorityConst: .word ulMaxSyscallInterruptPriority
+
+; -----------------------------------------------------------
+
+	.align 4
+ulPortGetIPSR: .asmfunc
+ 	mrs r0, ipsr
+ 	bx r14
+ 	.endasmfunc
+ ; -----------------------------------------------------------
+
+	.align 4
+vPortSetInterruptMask: .asmfunc
+	push {r0}
+	ldr r0, ulMaxSyscallInterruptPriorityConst
+	msr basepri, r0
+	pop {r0}
+	bx r14
+	.endasmfunc
+; -----------------------------------------------------------
+
+	.align 4
+xPortPendSVHandler: .asmfunc
+	mrs r0, psp
+	isb
+
+	;/* Get the location of the current TCB. */
+	ldr	r3, pxCurrentTCBConst
+	ldr	r2, [r3]
+
+	;/* Is the task using the FPU context?  If so, push high vfp registers. */
+	tst r14, #0x10
+	it eq
+	vstmdbeq r0!, {s16-s31}
+
+	;/* Save the core registers. */
+	stmdb r0!, {r4-r11, r14}
+
+	;/* Save the new top of stack into the first member of the TCB. */
+	str r0, [r2]
+
+	stmdb sp!, {r0, r3}
+	ldr r0, ulMaxSyscallInterruptPriorityConst
+	ldr r1, [r0]
+	msr basepri, r1
+	dsb
+	isb
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r0, r3}
+
+	;/* The first item in pxCurrentTCB is the task top of stack. */
+	ldr r1, [r3]
+	ldr r0, [r1]
+
+	;/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+
+	;/* Is the task using the FPU context?  If so, pop the high vfp registers
+	;too. */
+	tst r14, #0x10
+	it eq
+	vldmiaeq r0!, {s16-s31}
+
+	msr psp, r0
+	isb
+	bx r14
+	.endasmfunc
+
+; -----------------------------------------------------------
+
+	.align 4
+vPortSVCHandler: .asmfunc
+	;/* Get the location of the current TCB. */
+	ldr	r3, pxCurrentTCBConst
+	ldr r1, [r3]
+	ldr r0, [r1]
+	;/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+	msr psp, r0
+	isb
+	mov r0, #0
+	msr	basepri, r0
+	bx r14
+	.endasmfunc
+
+; -----------------------------------------------------------
+
+	.align 4
+vPortStartFirstTask: .asmfunc
+	;/* Use the NVIC offset register to locate the stack. */
+	ldr r0, NVICOffsetConst
+	ldr r0, [r0]
+	ldr r0, [r0]
+	;/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	;/* Clear the bit that indicates the FPU is in use in case the FPU was used
+	;before the scheduler was started - which would otherwise result in the
+	;unnecessary leaving of space in the SVC stack for lazy saving of FPU
+	;registers. */
+	mov r0, #0
+	msr control, r0
+	;/* Call SVC to start the first task. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	svc #0
+	.endasmfunc
+
+; -----------------------------------------------------------
+
+	.align 4
+vPortEnableVFP: .asmfunc
+	;/* The FPU enable bits are in the CPACR. */
+	ldr.w r0, CPACRConst
+	ldr	r1, [r0]
+
+	;/* Enable CP10 and CP11 coprocessors, then save back. */
+	orr	r1, r1, #( 0xf << 20 )
+	str r1, [r0]
+	bx	r14
+	.endasmfunc
+
+	.end
+
+; -----------------------------------------------------------
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM4F/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..f13537d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_CM4F/portmacro.h
@@ -0,0 +1,164 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+    #define portYIELD()                                 \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        __asm( "	dsb");                                \
+        __asm( "	isb");                                \
+    }
+
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired != pdFALSE ) portYIELD()
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #endif
+
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
+
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
+
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+
+    #define portDISABLE_INTERRUPTS()                                     \
+    {                                                                    \
+        _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
+        __asm( "	dsb");                                                 \
+        __asm( "	isb");                                                 \
+    }
+
+    #define portENABLE_INTERRUPTS()                   _set_interrupt_priority( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         _set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( "	dsb" ); __asm( "	isb")
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    _set_interrupt_priority( x )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
+
+/* portNOP() is not required by this port. */
+    #define portNOP()
+
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/port.c
new file mode 100644
index 0000000..698f1c8
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/port.c
@@ -0,0 +1,312 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------*/
+
+/* Count of the critical section nesting depth. */
+uint32_t ulCriticalNesting = 9999;
+
+/*-----------------------------------------------------------*/
+
+/* Registers required to configure the RTI. */
+#define portRTI_GCTRL_REG  		( * ( ( volatile uint32_t * ) 0xFFFFFC00 ) )
+#define portRTI_TBCTRL_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC04 ) )
+#define portRTI_COMPCTRL_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC0C ) )
+#define portRTI_CNT0_FRC0_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC10 ) )
+#define portRTI_CNT0_UC0_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC14 ) )
+#define portRTI_CNT0_CPUC0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC18 ) )
+#define portRTI_CNT0_COMP0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC50 ) )
+#define portRTI_CNT0_UDCP0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC54 ) )
+#define portRTI_SETINTENA_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC80 ) )
+#define portRTI_CLEARINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC84 ) )
+#define portRTI_INTFLAG_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC88 ) )
+
+
+/* Constants required to set up the initial stack of each task. */
+#define portINITIAL_SPSR	   	( ( StackType_t ) 0x1F )
+#define portINITIAL_FPSCR	  	( ( StackType_t ) 0x00 )
+#define portINSTRUCTION_SIZE   	( ( StackType_t ) 0x04 )
+#define portTHUMB_MODE_BIT		( ( StackType_t ) 0x20 )
+
+/* The number of words on the stack frame between the saved Top Of Stack and
+R0 (in which the parameters are passed. */
+#define portSPACE_BETWEEN_TOS_AND_PARAMETERS	( 12 )
+
+/*-----------------------------------------------------------*/
+
+/* vPortStartFirstSTask() is defined in portASM.asm */
+extern void vPortStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* Saved as part of the task context.  Set to pdFALSE if the task does not
+require an FPU context. */
+uint32_t ulTaskHasFPUContext = 0;
+
+/*-----------------------------------------------------------*/
+
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	#if __TI_VFP_SUPPORT__
+	{
+		/* Ensure the stack is correctly aligned on exit. */
+		pxTopOfStack--;
+	}
+	#endif
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which is the start of the as
+	the task has not executed yet.  The offset is added to make the return
+	address appear as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x00000000;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+
+	#ifdef portPRELOAD_TASK_REGISTERS
+	{
+		*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS;
+	}
+	#endif
+
+	/* Function parameters are passed in R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* Set the status register for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) ( ( _get_CPSR() & ~0xFF ) | portINITIAL_SPSR );
+
+	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
+	{
+		/* The task will start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	#ifdef __TI_VFP_SUPPORT__
+	{
+		pxTopOfStack--;
+
+		/* The last thing on the stack is the tasks ulUsingFPU value, which by
+		default is set to indicate that the stack frame does not include FPU
+		registers. */
+		*pxTopOfStack = pdFALSE;
+	}
+	#endif
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt(void)
+{
+	/* Disable timer 0. */
+	portRTI_GCTRL_REG &= 0xFFFFFFFEUL;
+
+	/* Use the internal counter. */
+	portRTI_TBCTRL_REG = 0x00000000U;
+
+	/* COMPSEL0 will use the RTIFRC0 counter. */
+	portRTI_COMPCTRL_REG = 0x00000000U;
+
+	/* Initialise the counter and the prescale counter registers. */
+	portRTI_CNT0_UC0_REG =  0x00000000U;
+	portRTI_CNT0_FRC0_REG =  0x00000000U;
+
+	/* Set Prescalar for RTI clock. */
+	portRTI_CNT0_CPUC0_REG = 0x00000001U;
+	portRTI_CNT0_COMP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
+	portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
+
+	/* Clear interrupts. */
+	portRTI_INTFLAG_REG =  0x0007000FU;
+	portRTI_CLEARINTENA_REG	= 0x00070F0FU;
+
+	/* Enable the compare 0 interrupt. */
+	portRTI_SETINTENA_REG = 0x00000001U;
+	portRTI_GCTRL_REG |= 0x00000001U;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler(void)
+{
+	/* Start the timer that generates the tick ISR. */
+	prvSetupTimerInterrupt();
+
+	/* Reset the critical section nesting count read to execute the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task.  This is done from portASM.asm as ARM mode must be
+	used. */
+	vPortStartFirstTask();
+
+	/* Should not get here! */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+void vPortEndScheduler(void)
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 0
+
+	/* The cooperative scheduler requires a normal IRQ service routine to
+	 * simply increment the system tick. */
+	__interrupt void vPortNonPreemptiveTick( void )
+	{
+		/* clear clock interrupt flag */
+		portRTI_INTFLAG_REG = 0x00000001;
+
+		/* Increment the tick count - this may make a delaying task ready
+		to run - but a context switch is not performed. */
+		xTaskIncrementTick();
+	}
+
+ #else
+
+	/*
+	 **************************************************************************
+	 * The preemptive scheduler ISR is written in assembler and can be found
+	 * in the portASM.asm file. This will only get used if portUSE_PREEMPTION
+	 * is set to 1 in portmacro.h
+	 **************************************************************************
+	 */
+	void vPortPreemptiveTick( void );
+
+#endif
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Disable interrupts, and keep a count of the nesting depth.
+ */
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
+	portDISABLE_INTERRUPTS();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Decrement the critical nesting count, and if it has reached zero, re-enable
+ * interrupts.
+ */
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > 0 )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == 0 )
+		{
+			/* Enable interrupts as per portENABLE_INTERRUPTS(). */
+			portENABLE_INTERRUPTS();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if __TI_VFP_SUPPORT__
+
+	void vPortTaskUsesFPU( void )
+	{
+	extern void vPortInitialiseFPSCR( void );
+
+		/* A task is registering the fact that it needs an FPU context.  Set the
+		FPU flag (saved as part of the task context. */
+		ulTaskHasFPUContext = pdTRUE;
+
+		/* Initialise the floating point status register. */
+		vPortInitialiseFPSCR();
+	}
+
+#endif /* __TI_VFP_SUPPORT__ */
+
+/*-----------------------------------------------------------*/
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portASM.asm b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portASM.asm
new file mode 100644
index 0000000..76e2b71
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portASM.asm
@@ -0,0 +1,229 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+        .text
+        .arm
+        .ref vTaskSwitchContext
+        .ref xTaskIncrementTick
+        .ref ulTaskHasFPUContext
+		.ref pxCurrentTCB
+
+;/*-----------------------------------------------------------*/
+;
+; Save Task Context
+;
+portSAVE_CONTEXT .macro
+		DSB
+
+		; Push R0 as we are going to use it
+		STMDB	SP!, {R0}
+
+		; Set R0 to point to the task stack pointer.
+		STMDB	SP,{SP}^
+		SUB	SP, SP, #4
+		LDMIA	SP!,{R0}
+
+		; Push the return address onto the stack.
+		STMDB	R0!, {LR}
+
+		; Now LR has been saved, it can be used instead of R0.
+		MOV	LR, R0
+
+		; Pop R0 so it can be saved onto the task stack.
+		LDMIA	SP!, {R0}
+
+		; Push all the system mode registers onto the task stack.
+		STMDB	LR,{R0-LR}^
+		SUB	LR, LR, #60
+
+		; Push the SPSR onto the task stack.
+		MRS	R0, SPSR
+		STMDB	LR!, {R0}
+
+    .if (__TI_VFP_SUPPORT__)
+		;Determine if the task maintains an FPU context.
+		LDR	R0, ulFPUContextConst
+		LDR	R0, [R0]
+
+		; Test the flag
+		CMP		R0, #0
+
+		; If the task is not using a floating point context then skip the
+		; saving of the FPU registers.
+		BEQ		$+16
+		FSTMDBD	LR!, {D0-D15}
+		FMRX    R1,  FPSCR
+		STMFD   LR!, {R1}
+
+		; Save the flag
+		STMDB	LR!, {R0}
+	.endif
+
+		; Store the new top of stack for the task.
+		LDR	R0, pxCurrentTCBConst
+		LDR	R0, [R0]
+		STR	LR, [R0]
+
+        .endm
+
+;/*-----------------------------------------------------------*/
+;
+; Restore Task Context
+;
+portRESTORE_CONTEXT .macro
+		LDR		R0, pxCurrentTCBConst
+		LDR		R0, [R0]
+		LDR		LR, [R0]
+
+	.if (__TI_VFP_SUPPORT__)
+		; The floating point context flag is the first thing on the stack.
+		LDR		R0, ulFPUContextConst
+		LDMFD	LR!, {R1}
+		STR		R1, [R0]
+
+		; Test the flag
+		CMP		R1, #0
+
+		; If the task is not using a floating point context then skip the
+		; VFP register loads.
+		BEQ		$+16
+
+		; Restore the floating point context.
+		LDMFD   LR!, {R0}
+		FLDMIAD	LR!, {D0-D15}
+		FMXR    FPSCR, R0
+	.endif
+
+		; Get the SPSR from the stack.
+		LDMFD	LR!, {R0}
+		MSR		SPSR_CSXF, R0
+
+		; Restore all system mode registers for the task.
+		LDMFD	LR, {R0-R14}^
+
+		; Restore the return address.
+		LDR		LR, [LR, #+60]
+
+		; And return - correcting the offset in the LR to obtain the
+		; correct address.
+		SUBS	PC, LR, #4
+        .endm
+
+;/*-----------------------------------------------------------*/
+; Start the first task by restoring its context.
+
+        .def vPortStartFirstTask
+
+vPortStartFirstTask:
+        portRESTORE_CONTEXT
+
+;/*-----------------------------------------------------------*/
+; Yield to another task.
+
+        .def vPortYieldProcessor
+
+vPortYieldProcessor:
+		; Within an IRQ ISR the link register has an offset from the true return
+		; address.  SWI doesn't do this. Add the offset manually so the ISR
+		; return code can be used.
+        ADD     LR, LR, #4
+
+        ; First save the context of the current task.
+        portSAVE_CONTEXT
+
+        ; Select the next task to execute. */
+        BL      vTaskSwitchContext
+
+        ; Restore the context of the task selected to execute.
+        portRESTORE_CONTEXT
+
+;/*-----------------------------------------------------------*/
+; Yield to another task from within the FreeRTOS API
+
+		.def vPortYeildWithinAPI
+
+vPortYeildWithinAPI:
+		; Save the context of the current task.
+
+        portSAVE_CONTEXT
+		; Clear SSI flag.
+		MOVW    R0, #0xFFF4
+		MOVT 	R0, #0xFFFF
+		LDR     R0, [R0]
+
+		; Select the next task to execute. */
+        BL      vTaskSwitchContext
+
+        ; Restore the context of the task selected to execute.
+        portRESTORE_CONTEXT
+
+;/*-----------------------------------------------------------*/
+; Preemptive Tick
+
+        .def vPortPreemptiveTick
+
+vPortPreemptiveTick:
+
+		; Save the context of the current task.
+        portSAVE_CONTEXT
+
+        ; Clear interrupt flag
+        MOVW    R0, #0xFC88
+        MOVT    R0, #0xFFFF
+        MOV     R1, #1
+        STR     R1, [R0]
+
+        ; Increment the tick count, making any adjustments to the blocked lists
+        ; that may be necessary.
+        BL      xTaskIncrementTick
+
+        ; Select the next task to execute.
+        CMP	R0, #0
+        BLNE    vTaskSwitchContext
+
+        ; Restore the context of the task selected to execute.
+        portRESTORE_CONTEXT
+
+;-------------------------------------------------------------------------------
+
+	.if (__TI_VFP_SUPPORT__)
+
+		.def vPortInitialiseFPSCR
+
+vPortInitialiseFPSCR:
+
+		MOV		R0, #0
+		FMXR    FPSCR, R0
+		BX		LR
+
+	.endif ;__TI_VFP_SUPPORT__
+
+
+pxCurrentTCBConst	.word	pxCurrentTCB
+ulFPUContextConst 	.word   ulTaskHasFPUContext
+;-------------------------------------------------------------------------------
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h
new file mode 100644
index 0000000..7989f18
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h
@@ -0,0 +1,117 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORTMACRO_H__
+#define __PORTMACRO_H__
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if (configUSE_16_BIT_TICKS == 1)
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY (TickType_t) 0xFFFF
+#else
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY (TickType_t) 0xFFFFFFFFF
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH    (-1)
+#define portTICK_PERIOD_MS    ((TickType_t) 1000 / configTICK_RATE_HZ)
+#define portBYTE_ALIGNMENT  8
+
+/* Critical section handling. */
+extern void vPortEnterCritical(void);
+extern void vPortExitCritical(void);
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+#define portDISABLE_INTERRUPTS()	asm( " CPSID I" )
+#define portENABLE_INTERRUPTS()		asm( " CPSIE I" )
+
+/* Scheduler utilities. */
+#pragma SWI_ALIAS( vPortYield, 0 )
+extern void vPortYield( void );
+#define portYIELD()             	vPortYield()
+#define portSYS_SSIR1_REG			( * ( ( volatile uint32_t * ) 0xFFFFFFB0 ) )
+#define portSYS_SSIR1_SSKEY			( 0x7500UL )
+#define portYIELD_WITHIN_API()		{ portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  asm( " DSB " ); asm( " ISB " ); }
+#define portYIELD_FROM_ISR( x )		if( x != pdFALSE ){ portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  ( void ) portSYS_SSIR1_REG; }
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+/* Architecture specific optimisations. */
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION(vFunction, pvParameters)       void vFunction(void *pvParameters)
+#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
+
+#endif /* __PORTMACRO_H__ */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/MSP430X/data_model.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/MSP430X/data_model.h
new file mode 100644
index 0000000..400705c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/MSP430X/data_model.h
@@ -0,0 +1,53 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	.if $DEFINED( __LARGE_DATA_MODEL__ )
+		.define "pushm.a", pushm_x
+		.define "popm.a", popm_x
+		.define "push.a", push_x
+		.define "pop.a", pop_x
+		.define "mov.a", mov_x
+	.else
+		.define "pushm.w", pushm_x
+		.define "popm.w", popm_x
+		.define "push.w", push_x
+		.define "pop.w", pop_x
+		.define "mov.w", mov_x
+	.endif
+
+	.if $DEFINED( __LARGE_CODE_MODEL__ )
+		.define "calla", call_x
+		.define "reta", ret_x
+	.else
+		.define "call", call_x
+		.define "ret", ret_x
+	.endif
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/MSP430X/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/MSP430X/port.c
new file mode 100644
index 0000000..5536c4e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/MSP430X/port.c
@@ -0,0 +1,187 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MSP430X port.
+ *----------------------------------------------------------*/
+
+/* Constants required for hardware setup.  The tick ISR runs off the ACLK,
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ			( ( TickType_t ) 32768 )
+#define portINITIAL_CRITICAL_NESTING	( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED			( ( StackType_t ) 0x08 )
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Each task maintains a count of the critical section nesting depth.  Each
+time a critical section is entered the count is incremented.  Each time a
+critical section is exited the count is decremented - with interrupts only
+being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+void vPortSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint16_t *pusTopOfStack;
+uint32_t *pulTopOfStack, ulTemp;
+
+	/*
+		Place a few bytes of known values on the bottom of the stack.
+		This is just useful for debugging and can be included if required.
+
+		*pxTopOfStack = ( StackType_t ) 0x1111;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x2222;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x3333;
+		pxTopOfStack--;
+	*/
+
+	/* Data types are need either 16 bits or 32 bits depending on the data 
+	and code model used. */
+	if( sizeof( pxCode ) == sizeof( uint16_t ) )
+	{
+		pusTopOfStack = ( uint16_t * ) pxTopOfStack;
+		ulTemp = ( uint32_t ) pxCode;
+		*pusTopOfStack = ( uint16_t ) ulTemp;
+	}
+	else
+	{
+		/* Make room for a 20 bit value stored as a 32 bit value. */
+		pusTopOfStack = ( uint16_t * ) pxTopOfStack;		
+		pusTopOfStack--;
+		pulTopOfStack = ( uint32_t * ) pusTopOfStack;
+		*pulTopOfStack = ( uint32_t ) pxCode;
+	}
+
+	pusTopOfStack--;
+	*pusTopOfStack = portFLAGS_INT_ENABLED;
+	pusTopOfStack -= ( sizeof( StackType_t ) / 2 );
+	
+	/* From here on the size of stacked items depends on the memory model. */
+	pxTopOfStack = ( StackType_t * ) pusTopOfStack;
+
+	/* Next the general purpose registers. */
+	#ifdef PRELOAD_REGISTER_VALUES
+		*pxTopOfStack = ( StackType_t ) 0xffff;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xeeee;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xdddd;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x9999;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x8888;
+		pxTopOfStack--;	
+		*pxTopOfStack = ( StackType_t ) 0x5555;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x6666;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x5555;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x4444;
+		pxTopOfStack--;
+	#else
+		pxTopOfStack -= 3;
+		*pxTopOfStack = ( StackType_t ) pvParameters;
+		pxTopOfStack -= 9;
+	#endif
+
+	/* A variable is used to keep track of the critical section nesting.
+	This variable has to be stored as part of the task context and is
+	initially set to zero. */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the MSP430 port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.
+ */
+void vPortSetupTimerInterrupt( void )
+{
+	vApplicationSetupTimerInterrupt();
+}
+/*-----------------------------------------------------------*/
+
+#pragma vector=configTICK_VECTOR
+interrupt void vTickISREntry( void )
+{
+extern void vPortTickISR( void );
+
+	__bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );
+	#if configUSE_PREEMPTION == 1
+		extern void vPortPreemptiveTickISR( void );
+		vPortPreemptiveTickISR();
+	#else
+		extern void vPortCooperativeTickISR( void );
+		vPortCooperativeTickISR();
+	#endif
+}
+
+	
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/MSP430X/portext.asm b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/MSP430X/portext.asm
new file mode 100644
index 0000000..81de6ea
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/MSP430X/portext.asm
@@ -0,0 +1,159 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+; * The definition of the "register test" tasks, as described at the top of
+; * main.c
+
+	.include data_model.h
+
+	.global xTaskIncrementTick
+	.global vTaskSwitchContext
+	.global vPortSetupTimerInterrupt
+	.global pxCurrentTCB
+	.global usCriticalNesting
+
+	.def vPortPreemptiveTickISR
+	.def vPortCooperativeTickISR
+	.def vPortYield
+	.def xPortStartScheduler
+
+;-----------------------------------------------------------
+
+portSAVE_CONTEXT .macro
+
+	;Save the remaining registers.
+	pushm_x	#12, r15
+	mov.w	&usCriticalNesting, r14
+	push_x r14
+	mov_x	&pxCurrentTCB, r12
+	mov_x	sp, 0( r12 )
+	.endm
+;-----------------------------------------------------------
+
+portRESTORE_CONTEXT .macro
+
+	mov_x	&pxCurrentTCB, r12
+	mov_x	@r12, sp
+	pop_x	r15
+	mov.w	r15, &usCriticalNesting
+	popm_x	#12, r15
+	nop
+	pop.w	sr
+	nop
+	ret_x
+	.endm
+;-----------------------------------------------------------
+
+;*
+;* The RTOS tick ISR.
+;*
+;* If the cooperative scheduler is in use this simply increments the tick
+;* count.
+;*
+;* If the preemptive scheduler is in use a context switch can also occur.
+;*/
+
+	.text
+	.align 2
+
+vPortPreemptiveTickISR: .asmfunc
+
+	; The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs
+	;to save it manually before it gets modified (interrupts get disabled).
+	push.w sr
+	portSAVE_CONTEXT
+
+	call_x	#xTaskIncrementTick
+	call_x	#vTaskSwitchContext
+
+	portRESTORE_CONTEXT
+	.endasmfunc
+;-----------------------------------------------------------
+
+	.align 2
+
+vPortCooperativeTickISR: .asmfunc
+
+	; The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs
+	;to save it manually before it gets modified (interrupts get disabled).
+	push.w sr
+	portSAVE_CONTEXT
+
+	call_x	#xTaskIncrementTick
+
+	portRESTORE_CONTEXT
+
+	.endasmfunc
+;-----------------------------------------------------------
+
+;
+; Manual context switch called by the portYIELD() macro.
+;
+
+	.align 2
+
+vPortYield: .asmfunc
+
+	; The sr needs saving before it is modified.
+	push.w	sr
+
+	; Now the SR is stacked we can disable interrupts.
+	dint
+	nop
+
+	; Save the context of the current task.
+	portSAVE_CONTEXT
+
+	; Select the next task to run.
+	call_x	#vTaskSwitchContext
+
+	; Restore the context of the new task.
+	portRESTORE_CONTEXT
+	.endasmfunc
+;-----------------------------------------------------------
+
+
+;
+; Start off the scheduler by initialising the RTOS tick timer, then restoring
+; the context of the first task.
+;
+
+	.align 2
+
+xPortStartScheduler: .asmfunc
+
+	; Setup the hardware to generate the tick.  Interrupts are disabled
+	; when this function is called.
+	call_x	#vPortSetupTimerInterrupt
+
+	; Restore the context of the first task that is going to run.
+	portRESTORE_CONTEXT
+	.endasmfunc
+;-----------------------------------------------------------
+
+	.end
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/MSP430X/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/MSP430X/portmacro.h
new file mode 100644
index 0000000..83daecf
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CCS/MSP430X/portmacro.h
@@ -0,0 +1,143 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Hardware includes. */
+#include "msp430.h"
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portBASE_TYPE	portSHORT
+
+/* The stack type changes depending on the data model. */
+#ifdef __LARGE_DATA_MODEL__
+	#define portSTACK_TYPE uint32_t
+#else
+	#define portSTACK_TYPE uint16_t
+	#define portPOINTER_SIZE_TYPE uint16_t
+#endif
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS()	_disable_interrupt(); _nop()
+#define portENABLE_INTERRUPTS()		_enable_interrupt(); _nop()
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
+
+#define portENTER_CRITICAL()													\
+{																				\
+extern volatile uint16_t usCriticalNesting;										\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	/* Now interrupts are disabled usCriticalNesting can be accessed */			\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
+	/* times portENTER_CRITICAL() has been called. */							\
+	usCriticalNesting++;														\
+}
+
+#define portEXIT_CRITICAL()														\
+{																				\
+extern volatile uint16_t usCriticalNesting;										\
+																				\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
+	{																			\
+		/* Decrement the nesting count as we are leaving a critical section. */	\
+		usCriticalNesting--;													\
+																				\
+		/* If the nesting level has reached zero then interrupts should be */	\
+		/* re-enabled. */														\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
+		{																		\
+			portENABLE_INTERRUPTS();											\
+		}																		\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+extern void vPortYield( void );
+#define portYIELD() vPortYield()
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			2
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					__no_operation()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR( x ) if( x ) vPortYield()
+
+void vApplicationSetupTimerInterrupt( void );
+
+/* sizeof( int ) != sizeof( long ) so a full printf() library is required if
+run time stats information is to be displayed. */
+#define portLU_PRINTF_SPECIFIER_REQUIRED
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/port.c
new file mode 100644
index 0000000..502ccb2
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/port.c
@@ -0,0 +1,183 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+
+#define portINITIAL_FORMAT_VECTOR		( ( StackType_t ) 0x4000 )
+
+/* Supervisor mode set. */
+#define portINITIAL_STATUS_REGISTER		( ( StackType_t ) 0x2000)
+
+/* The clock prescale into the timer peripheral. */
+#define portPRESCALE_VALUE				( ( uint8_t ) 10 )
+
+/* The clock frequency into the RTC. */
+#define portRTC_CLOCK_HZ				( ( uint32_t ) 1000 )
+
+asm void interrupt VectorNumber_VL1swi vPortYieldISR( void );
+static void prvSetupTimerInterrupt( void );
+
+/* Used to keep track of the number of nested calls to taskENTER_CRITICAL().  This
+will be set to 0 prior to the first task being started. */
+static uint32_t ulCriticalNesting = 0x9999UL;
+
+/*-----------------------------------------------------------*/
+
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+
+uint32_t ulOriginalA5;
+
+	__asm{ MOVE.L A5, ulOriginalA5 };
+
+
+	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
+	pxTopOfStack--;
+
+	/* Exception stack frame starts with the return address. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
+	pxTopOfStack -= 14; /* A5 to D0. */
+
+	/* Parameter in A0. */
+	*( pxTopOfStack + 8 ) = ( StackType_t ) pvParameters;
+
+	/* A5 must be maintained as it is resurved by the compiler. */
+	*( pxTopOfStack + 13 ) = ulOriginalA5;
+
+	return pxTopOfStack;  
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	ulCriticalNesting = 0UL;
+
+	/* Configure a timer to generate the tick interrupt. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task executing. */
+	vPortStartFirstTask();
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{				
+	/* Prescale by 1 - ie no prescale. */
+	RTCSC |= 8;
+	
+	/* Compare match value. */
+	RTCMOD = portRTC_CLOCK_HZ / configTICK_RATE_HZ;
+	
+	/* Enable the RTC to generate interrupts - interrupts are already disabled
+	when this code executes. */
+	RTCSC_RTIE = 1;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented as there is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	if( ulCriticalNesting == 0UL )
+	{
+		/* Guard against context switches being pended simultaneously with a
+		critical section being entered. */
+		do
+		{
+			portDISABLE_INTERRUPTS();
+			if( INTC_FRC == 0UL )
+			{
+				break;
+			}
+
+			portENABLE_INTERRUPTS();
+
+		} while( 1 );
+	}
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	ulCriticalNesting--;
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortYieldHandler( void )
+{
+uint32_t ulSavedInterruptMask;
+
+	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Note this will clear all forced interrupts - this is done for speed. */
+		INTC_CFRC = 0x3E;
+		vTaskSwitchContext();
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+}
+/*-----------------------------------------------------------*/
+
+void interrupt VectorNumber_Vrtc vPortTickISR( void )
+{
+uint32_t ulSavedInterruptMask;
+
+	/* Clear the interrupt. */
+	RTCSC |= RTCSC_RTIF_MASK;
+
+	/* Increment the RTOS tick. */
+	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+}
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portasm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portasm.S
new file mode 100644
index 0000000..b722b31
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portasm.S
@@ -0,0 +1,130 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Purpose: Lowest level routines for all ColdFire processors.
+ *
+ * Notes:
+ * 
+ * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale
+ * supplied source files.
+ */
+
+    .global ulPortSetIPL
+    .global _ulPortSetIPL
+    .global mcf5xxx_wr_cacrx
+    .global _mcf5xxx_wr_cacrx
+    .global vPortYieldISR
+    .global _vPortYieldISR
+    .global vPortStartFirstTask
+    .global _vPortStartFirstTask
+    .extern _pxCurrentTCB
+    .extern _vPortYieldHandler
+
+    .text
+
+.macro portSAVE_CONTEXT
+
+	lea.l		(-60, sp), sp
+	movem.l		d0-a6, (sp)
+	move.l		_pxCurrentTCB, a0
+	move.l		sp, (a0)
+
+	.endm
+
+.macro portRESTORE_CONTEXT
+
+	move.l		_pxCurrentTCB, a0
+	move.l		(a0), sp
+	movem.l		(sp), d0-a6
+	lea.l		(60, sp), sp
+	rte
+
+	.endm
+
+/********************************************************************/
+/*
+ * This routines changes the IPL to the value passed into the routine.
+ * It also returns the old IPL value back.
+ * Calling convention from C:
+ *   old_ipl = asm_set_ipl(new_ipl);
+ * For the Diab Data C compiler, it passes return value thru D0.
+ * Note that only the least significant three bits of the passed
+ * value are used.
+ */
+
+ulPortSetIPL:
+_ulPortSetIPL:
+    link    A6,#-8
+    movem.l D6-D7,(SP)
+
+    move.w  SR,D7       /* current sr    */
+
+    move.l  D7,D6       /* prepare return value  */
+    andi.l  #0x0700,D6  /* mask out IPL  */
+    lsr.l   #8,D6       /* IPL   */
+
+    andi.l  #0x07,D0    /* least significant three bits  */
+    lsl.l   #8,D0       /* move over to make mask    */
+
+    andi.l  #0x0000F8FF,D7  /* zero out current IPL  */
+    or.l    D0,D7           /* place new IPL in sr   */
+    move.w  D7,SR
+
+	move.l	D6, D0		/* Return value in D0. */
+    movem.l (SP),D6-D7
+    lea     8(SP),SP
+    unlk    A6
+    rts
+/********************************************************************/
+
+mcf5xxx_wr_cacrx:
+_mcf5xxx_wr_cacrx:
+    move.l  4(sp),d0
+    .long   0x4e7b0002  /* movec d0,cacr   */
+    nop
+    rts
+
+/********************************************************************/
+
+/* Yield interrupt. */
+_vPortYieldISR:
+vPortYieldISR:
+	portSAVE_CONTEXT
+	jsr _vPortYieldHandler
+	portRESTORE_CONTEXT
+
+/********************************************************************/
+
+
+vPortStartFirstTask:
+_vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+    .end
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portmacro.h
new file mode 100644
index 0000000..0edd3a1
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portmacro.h
@@ -0,0 +1,115 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			4
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortSetIPL( uint32_t );
+#define portDISABLE_INTERRUPTS()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portENABLE_INTERRUPTS()		ulPortSetIPL( 0 )
+
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+
+extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portNOP()	asm volatile ( "nop" )
+
+/* Context switches are requested using the force register. */
+#define portYIELD()	INTC_SFRC = 0x3E; portNOP(); portNOP(); portNOP(); portNOP(); portNOP()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#define portEND_SWITCHING_ISR( xSwitchRequired )	if( xSwitchRequired != pdFALSE )	\
+													{									\
+														portYIELD();					\
+													}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/port.c
new file mode 100644
index 0000000..28692f4
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/port.c
@@ -0,0 +1,147 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+
+#define portINITIAL_FORMAT_VECTOR		( ( StackType_t ) 0x4000 )
+
+/* Supervisor mode set. */
+#define portINITIAL_STATUS_REGISTER		( ( StackType_t ) 0x2000)
+
+/* Used to keep track of the number of nested calls to taskENTER_CRITICAL().  This
+will be set to 0 prior to the first task being started. */
+static uint32_t ulCriticalNesting = 0x9999UL;
+
+
+#define portSAVE_CONTEXT()				\
+	lea.l		(-60, %sp), %sp;		\
+	movem.l		%d0-%fp, (%sp);			\
+	move.l		pxCurrentTCB, %a0;		\
+	move.l		%sp, (%a0);
+
+#define portRESTORE_CONTEXT()			\
+	move.l		pxCurrentTCB, %a0;		\
+	move.l		(%a0), %sp;				\
+	movem.l		(%sp), %d0-%fp;			\
+	lea.l		%sp@(60), %sp;			\
+	rte
+
+
+
+/*-----------------------------------------------------------*/
+
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
+	pxTopOfStack--;
+
+	/* Exception stack frame starts with the return address. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
+	pxTopOfStack -= 14; /* A5 to D0. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	ulCriticalNesting = 0UL;
+
+	/* Configure the interrupts used by this port. */
+	vApplicationSetupInterrupts();
+
+	/* Start the first task executing. */
+	vPortStartFirstTask();
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented as there is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	if( ulCriticalNesting == 0UL )
+	{
+		/* Guard against context switches being pended simultaneously with a
+		critical section being entered. */
+		do
+		{
+			portDISABLE_INTERRUPTS();
+			if( MCF_INTC0_INTFRCH == 0UL )
+			{
+				break;
+			}
+
+			portENABLE_INTERRUPTS();
+
+		} while( 1 );
+	}
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	ulCriticalNesting--;
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortYieldHandler( void )
+{
+uint32_t ulSavedInterruptMask;
+
+	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+		/* Note this will clear all forced interrupts - this is done for speed. */
+		MCF_INTC0_INTFRCL = 0;
+		vTaskSwitchContext();
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+}
+/*-----------------------------------------------------------*/
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portasm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portasm.S
new file mode 100644
index 0000000..0e7e581
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portasm.S
@@ -0,0 +1,130 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Purpose: Lowest level routines for all ColdFire processors.
+ *
+ * Notes:
+ * 
+ * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale
+ * supplied source files.
+ */
+
+    .global ulPortSetIPL
+    .global _ulPortSetIPL
+    .global mcf5xxx_wr_cacrx
+    .global _mcf5xxx_wr_cacrx
+    .global vPortYieldISR
+    .global _vPortYieldISR
+    .global vPortStartFirstTask
+    .global _vPortStartFirstTask
+    .extern _pxCurrentTCB
+    .extern _vPortYieldHandler
+
+    .text
+
+.macro portSAVE_CONTEXT
+
+	lea.l		(-60, sp), sp
+	movem.l		d0-a6, (sp)
+	move.l		_pxCurrentTCB, a0
+	move.l		sp, (a0)
+
+	.endm
+
+.macro portRESTORE_CONTEXT
+
+	move.l		_pxCurrentTCB, a0
+	move.l		(a0), sp
+	movem.l		(sp), d0-a6
+	lea.l		(60, sp), sp
+	rte
+
+	.endm
+
+/********************************************************************/
+/*
+ * This routines changes the IPL to the value passed into the routine.
+ * It also returns the old IPL value back.
+ * Calling convention from C:
+ *   old_ipl = asm_set_ipl(new_ipl);
+ * For the Diab Data C compiler, it passes return value thru D0.
+ * Note that only the least significant three bits of the passed
+ * value are used.
+ */
+
+ulPortSetIPL:
+_ulPortSetIPL:
+    link    A6,#-8
+    movem.l D6-D7,(SP)
+
+    move.w  SR,D7       /* current sr    */
+
+    move.l  D7,D0       /* prepare return value  */
+    andi.l  #0x0700,D0  /* mask out IPL  */
+    lsr.l   #8,D0       /* IPL   */
+
+    move.l  8(A6),D6    /* get argument  */
+    andi.l  #0x07,D6    /* least significant three bits  */
+    lsl.l   #8,D6       /* move over to make mask    */
+
+    andi.l  #0x0000F8FF,D7  /* zero out current IPL  */
+    or.l    D6,D7           /* place new IPL in sr   */
+    move.w  D7,SR
+
+    movem.l (SP),D6-D7
+    lea     8(SP),SP
+    unlk    A6
+    rts
+/********************************************************************/
+
+mcf5xxx_wr_cacrx:
+_mcf5xxx_wr_cacrx:
+    move.l  4(sp),d0
+    .long   0x4e7b0002  /* movec d0,cacr   */
+    nop
+    rts
+
+/********************************************************************/
+
+/* Yield interrupt. */
+_vPortYieldISR:
+vPortYieldISR:
+	portSAVE_CONTEXT
+	jsr _vPortYieldHandler
+	portRESTORE_CONTEXT
+
+/********************************************************************/
+
+
+vPortStartFirstTask:
+_vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+    .end
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portmacro.h
new file mode 100644
index 0000000..6afa38d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portmacro.h
@@ -0,0 +1,114 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			4
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+uint32_t ulPortSetIPL( uint32_t );
+#define portDISABLE_INTERRUPTS()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portENABLE_INTERRUPTS()		ulPortSetIPL( 0 )
+
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+
+extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+#define portNOP()	asm volatile ( 	"nop" )
+
+/* Note this will overwrite all other bits in the force register, it is done this way for speed. */
+#define portYIELD()			MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP() /* -32 as we are using the high word of the 64bit mask. */
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#define portEND_SWITCHING_ISR( xSwitchRequired )	if( xSwitchRequired != pdFALSE )	\
+													{									\
+														portYIELD();					\
+													}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/HCS12/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/HCS12/port.c
new file mode 100644
index 0000000..94caaae
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/HCS12/port.c
@@ -0,0 +1,237 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the HCS12 port.
+ *----------------------------------------------------------*/
+
+
+/*
+ * Configure a timer to generate the RTOS tick at the frequency specified 
+ * within FreeRTOSConfig.h.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/* Interrupt service routines have to be in non-banked memory - as does the
+scheduler startup function. */
+#pragma CODE_SEG __NEAR_SEG NON_BANKED
+
+	/* Manual context switch function.  This is the SWI ISR. */
+	void interrupt vPortYield( void );
+
+	/* Tick context switch function.  This is the timer ISR. */
+	void interrupt vPortTickInterrupt( void );
+	
+	/* Simply called by xPortStartScheduler().  xPortStartScheduler() does not
+	start the scheduler directly because the header file containing the 
+	xPortStartScheduler() prototype is part of the common kernel code, and 
+	therefore cannot use the CODE_SEG pragma. */
+	static BaseType_t xBankedStartScheduler( void );
+
+#pragma CODE_SEG DEFAULT
+
+/* Calls to portENTER_CRITICAL() can be nested.  When they are nested the 
+critical section should not be left (i.e. interrupts should not be re-enabled)
+until the nesting depth reaches 0.  This variable simply tracks the nesting 
+depth.  Each task maintains it's own critical nesting depth variable so 
+uxCriticalNesting is saved and restored from the task stack during a context
+switch. */
+volatile UBaseType_t uxCriticalNesting = 0xff;
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* 
+		Place a few bytes of known values on the bottom of the stack.
+		This can be uncommented to provide useful stack markers when debugging.
+
+		*pxTopOfStack = ( StackType_t ) 0x11;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x22;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x33;
+		pxTopOfStack--;
+	*/
+
+
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro.  In this case the stack as
+	expected by the HCS12 RTI instruction. */
+
+
+	/* The address of the task function is placed in the stack byte at a time. */
+	*pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 );
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 );
+	pxTopOfStack--;
+
+	/* Next are all the registers that form part of the task context. */
+
+	/* Y register */
+	*pxTopOfStack = ( StackType_t ) 0xff;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xee;
+	pxTopOfStack--;
+
+	/* X register */
+	*pxTopOfStack = ( StackType_t ) 0xdd;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xcc;
+	pxTopOfStack--;
+ 
+	/* A register contains parameter high byte. */
+	*pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 );
+	pxTopOfStack--;
+
+	/* B register contains parameter low byte. */
+	*pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 );
+	pxTopOfStack--;
+
+	/* CCR: Note that when the task starts interrupts will be enabled since
+	"I" bit of CCR is cleared */
+	*pxTopOfStack = ( StackType_t ) 0x00;
+	pxTopOfStack--;
+	
+	#ifdef BANKED_MODEL
+		/* The page of the task. */
+		*pxTopOfStack = ( StackType_t ) ( ( int ) pxCode );
+		pxTopOfStack--;
+	#endif
+	
+	/* Finally the critical nesting depth is initialised with 0 (not within
+	a critical section). */
+	*pxTopOfStack = ( StackType_t ) 0x00;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the HCS12 port will get stopped. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	TickTimer_SetFreqHz( configTICK_RATE_HZ );
+	TickTimer_Enable();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* xPortStartScheduler() does not start the scheduler directly because 
+	the header file containing the xPortStartScheduler() prototype is part 
+	of the common kernel code, and therefore cannot use the CODE_SEG pragma. 
+	Instead it simply calls the locally defined xBankedStartScheduler() - 
+	which does use the CODE_SEG pragma. */
+
+	return xBankedStartScheduler();
+}
+/*-----------------------------------------------------------*/
+
+#pragma CODE_SEG __NEAR_SEG NON_BANKED
+
+static BaseType_t xBankedStartScheduler( void )
+{
+	/* Configure the timer that will generate the RTOS tick.  Interrupts are
+	disabled when this function is called. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task. */
+	portRESTORE_CONTEXT();
+
+	/* Simulate the end of an interrupt to start the scheduler off. */
+	__asm( "rti" );
+
+	/* Should not get here! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Context switch functions.  These are both interrupt service routines.
+ */
+
+/*
+ * Manual context switch forced by calling portYIELD().  This is the SWI
+ * handler.
+ */
+void interrupt vPortYield( void )
+{
+	portSAVE_CONTEXT();
+	vTaskSwitchContext();
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * RTOS tick interrupt service routine.  If the cooperative scheduler is 
+ * being used then this simply increments the tick count.  If the 
+ * preemptive scheduler is being used a context switch can occur.
+ */
+void interrupt vPortTickInterrupt( void )
+{
+	#if configUSE_PREEMPTION == 1
+	{
+		/* A context switch might happen so save the context. */
+		portSAVE_CONTEXT();
+
+		/* Increment the tick ... */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			vTaskSwitchContext();
+		}
+
+		TFLG1 = 1;								   
+
+		/* Restore the context of a task - which may be a different task
+		to that interrupted. */
+		portRESTORE_CONTEXT();	
+	}
+	#else
+	{
+		xTaskIncrementTick();
+		TFLG1 = 1;
+	}
+	#endif
+}
+
+#pragma CODE_SEG DEFAULT
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/HCS12/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/HCS12/portmacro.h
new file mode 100644
index 0000000..f231d77
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/CodeWarrior/HCS12/portmacro.h
@@ -0,0 +1,202 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint8_t
+#define portBASE_TYPE	char
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			1
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portYIELD()					__asm( "swi" );
+#define portNOP()					__asm( "nop" );
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#define portENABLE_INTERRUPTS()				__asm( "cli" )
+#define portDISABLE_INTERRUPTS()			__asm( "sei" )
+
+/*
+ * Disable interrupts before incrementing the count of critical section nesting.
+ * The nesting count is maintained so we know when interrupts should be
+ * re-enabled.  Once interrupts are disabled the nesting count can be accessed
+ * directly.  Each task maintains its own nesting count.
+ */
+#define portENTER_CRITICAL()  									\
+{																\
+	extern volatile UBaseType_t uxCriticalNesting;	\
+																\
+	portDISABLE_INTERRUPTS();									\
+	uxCriticalNesting++;										\
+}
+
+/*
+ * Interrupts are disabled so we can access the nesting count directly.  If the
+ * nesting is found to be 0 (no nesting) then we are leaving the critical
+ * section and interrupts can be re-enabled.
+ */
+#define  portEXIT_CRITICAL()									\
+{																\
+	extern volatile UBaseType_t uxCriticalNesting;	\
+																\
+	uxCriticalNesting--;										\
+	if( uxCriticalNesting == 0 )								\
+	{															\
+		portENABLE_INTERRUPTS();								\
+	}															\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*
+ * These macros are very simple as the processor automatically saves and
+ * restores its registers as interrupts are entered and exited.  In
+ * addition to the (automatically stacked) registers we also stack the
+ * critical nesting count.  Each task maintains its own critical nesting
+ * count as it is legitimate for a task to yield from within a critical
+ * section.  If the banked memory model is being used then the PPAGE
+ * register is also stored as part of the tasks context.
+ */
+
+#ifdef BANKED_MODEL
+	/*
+	 * Load the stack pointer for the task, then pull the critical nesting
+	 * count and PPAGE register from the stack.  The remains of the
+	 * context are restored by the RTI instruction.
+	 */
+	#define portRESTORE_CONTEXT()									\
+	{																\
+		extern volatile void * pxCurrentTCB;						\
+		extern volatile UBaseType_t uxCriticalNesting;	\
+																	\
+		__asm( "ldx pxCurrentTCB" );								\
+		__asm( "lds 0, x" );										\
+		__asm( "pula" );											\
+		__asm( "staa uxCriticalNesting" );							\
+		__asm( "pula" );											\
+		__asm( "staa 0x30" ); /* 0x30 = PPAGE */					\
+	}
+
+	/*
+	 * By the time this macro is called the processor has already stacked the
+	 * registers.  Simply stack the nesting count and PPAGE value, then save
+	 * the task stack pointer.
+	 */
+	#define portSAVE_CONTEXT()										\
+	{																\
+		extern volatile void * pxCurrentTCB;						\
+		extern volatile UBaseType_t uxCriticalNesting;	\
+																	\
+		__asm( "ldaa 0x30" );  /* 0x30 = PPAGE */					\
+		__asm( "psha" );											\
+		__asm( "ldaa uxCriticalNesting" );							\
+		__asm( "psha" );											\
+		__asm( "ldx pxCurrentTCB" );								\
+		__asm( "sts 0, x" );										\
+	}
+#else
+
+	/*
+	 * These macros are as per the BANKED versions above, but without saving
+	 * and restoring the PPAGE register.
+	 */
+
+	#define portRESTORE_CONTEXT()									\
+	{																\
+		extern volatile void * pxCurrentTCB;						\
+		extern volatile UBaseType_t uxCriticalNesting;	\
+																	\
+		__asm( "ldx pxCurrentTCB" );								\
+		__asm( "lds 0, x" );										\
+		__asm( "pula" );											\
+		__asm( "staa uxCriticalNesting" );							\
+	}
+
+	#define portSAVE_CONTEXT()										\
+	{																\
+		extern volatile void * pxCurrentTCB;						\
+		extern volatile UBaseType_t uxCriticalNesting;	\
+																	\
+		__asm( "ldaa uxCriticalNesting" );							\
+		__asm( "psha" );											\
+		__asm( "ldx pxCurrentTCB" );								\
+		__asm( "sts 0, x" );										\
+	}
+#endif
+
+/*
+ * Utility macro to call macros above in correct order in order to perform a
+ * task switch from within a standard ISR.  This macro can only be used if
+ * the ISR does not use any local (stack) variables.  If the ISR uses stack
+ * variables portYIELD() should be used in it's place.
+ */
+#define portTASK_SWITCH_FROM_ISR()								\
+	portSAVE_CONTEXT();											\
+	vTaskSwitchContext();										\
+	portRESTORE_CONTEXT();
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Common/mpu_wrappers.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Common/mpu_wrappers.c
new file mode 100644
index 0000000..ec82c67
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Common/mpu_wrappers.c
@@ -0,0 +1,1414 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * Implementation of the wrapper functions used to raise the processor privilege
+ * before calling a standard FreeRTOS API function.
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+#include "event_groups.h"
+#include "stream_buffer.h"
+#include "mpu_prototypes.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+BaseType_t xPortRaisePrivilege( void ) FREERTOS_SYSTEM_CALL;
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortRaisePrivilege( void ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xRunningPrivileged;
+
+    /* Check whether the processor is already privileged. */
+    xRunningPrivileged = portIS_PRIVILEGED();
+
+    /* If the processor is not already privileged, raise privilege. */
+    if( xRunningPrivileged == pdFALSE )
+    {
+        portRAISE_PRIVILEGE();
+    }
+
+    return xRunningPrivileged;
+}
+/*-----------------------------------------------------------*/
+
+void vPortResetPrivilege( BaseType_t xRunningPrivileged )
+{
+    if( xRunningPrivileged == pdFALSE )
+    {
+        portRESET_PRIVILEGE();
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode,
+                                const char * const pcName,
+                                uint16_t usStackDepth,
+                                void * pvParameters,
+                                UBaseType_t uxPriority,
+                                TaskHandle_t * pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode,
+                                        const char * const pcName,
+                                        const uint32_t ulStackDepth,
+                                        void * const pvParameters,
+                                        UBaseType_t uxPriority,
+                                        StackType_t * const puxStackBuffer,
+                                        StaticTask_t * const pxTaskBuffer ) /* FREERTOS_SYSTEM_CALL */
+    {
+        TaskHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+    void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        vTaskDelete( pxTaskToDelete );
+        vPortResetPrivilege( xRunningPrivileged );
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskDelayUntil == 1 )
+    BaseType_t MPU_xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                    TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+        BaseType_t xReturn;
+
+        xReturn = xTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+    BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTaskAbortDelay( xTask );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+    void MPU_vTaskDelay( TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        vTaskDelay( xTicksToDelay );
+        vPortResetPrivilege( xRunningPrivileged );
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+    UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
+    {
+        UBaseType_t uxReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        uxReturn = uxTaskPriorityGet( pxTask );
+        vPortResetPrivilege( xRunningPrivileged );
+        return uxReturn;
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+    void MPU_vTaskPrioritySet( TaskHandle_t pxTask,
+                               UBaseType_t uxNewPriority ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        vTaskPrioritySet( pxTask, uxNewPriority );
+        vPortResetPrivilege( xRunningPrivileged );
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_eTaskGetState == 1 )
+    eTaskState MPU_eTaskGetState( TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+        eTaskState eReturn;
+
+        eReturn = eTaskGetState( pxTask );
+        vPortResetPrivilege( xRunningPrivileged );
+        return eReturn;
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+    void MPU_vTaskGetInfo( TaskHandle_t xTask,
+                           TaskStatus_t * pxTaskStatus,
+                           BaseType_t xGetFreeStackSpace,
+                           eTaskState eState ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState );
+        vPortResetPrivilege( xRunningPrivileged );
+    }
+#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
+    {
+        TaskHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTaskGetIdleTaskHandle();
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+    void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        vTaskSuspend( pxTaskToSuspend );
+        vPortResetPrivilege( xRunningPrivileged );
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+    void MPU_vTaskResume( TaskHandle_t pxTaskToResume ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        vTaskResume( pxTaskToResume );
+        vPortResetPrivilege( xRunningPrivileged );
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+void MPU_vTaskSuspendAll( void ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    vTaskSuspendAll();
+    vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xTaskResumeAll( void ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xTaskResumeAll();
+    vPortResetPrivilege( xRunningPrivileged );
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */
+{
+    TickType_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xTaskGetTickCount();
+    vPortResetPrivilege( xRunningPrivileged );
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */
+{
+    UBaseType_t uxReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    uxReturn = uxTaskGetNumberOfTasks();
+    vPortResetPrivilege( xRunningPrivileged );
+    return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */
+{
+    char * pcReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    pcReturn = pcTaskGetName( xTaskToQuery );
+    vPortResetPrivilege( xRunningPrivileged );
+    return pcReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+    TaskHandle_t MPU_xTaskGetHandle( const char * pcNameToQuery ) /* FREERTOS_SYSTEM_CALL */
+    {
+        TaskHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTaskGetHandle( pcNameToQuery );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+    void MPU_vTaskList( char * pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        vTaskList( pcWriteBuffer );
+        vPortResetPrivilege( xRunningPrivileged );
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+    void MPU_vTaskGetRunTimeStats( char * pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        vTaskGetRunTimeStats( pcWriteBuffer );
+        vPortResetPrivilege( xRunningPrivileged );
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+    uint32_t MPU_ulTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */
+    {
+        uint32_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = ulTaskGetIdleRunTimeCounter();
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                         TaskHookFunction_t pxTagValue ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        vTaskSetApplicationTaskTag( xTask, pxTagValue );
+        vPortResetPrivilege( xRunningPrivileged );
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+    {
+        TaskHookFunction_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTaskGetApplicationTaskTag( xTask );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                                BaseType_t xIndex,
+                                                void * pvValue ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue );
+        vPortResetPrivilege( xRunningPrivileged );
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+    void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                                   BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */
+    {
+        void * pvReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        pvReturn = pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex );
+        vPortResetPrivilege( xRunningPrivileged );
+        return pvReturn;
+    }
+#endif /* if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+    BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask,
+                                                 void * pvParameter ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif /* if ( configUSE_APPLICATION_TASK_TAG == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+    UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * pxTaskStatusArray,
+                                          UBaseType_t uxArraySize,
+                                          uint32_t * pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */
+    {
+        UBaseType_t uxReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );
+        vPortResetPrivilege( xRunningPrivileged );
+        return uxReturn;
+    }
+#endif /* if ( configUSE_TRACE_FACILITY == 1 ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xTaskCatchUpTicks( TickType_t xTicksToCatchUp ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xTaskCatchUpTicks( xTicksToCatchUp );
+    vPortResetPrivilege( xRunningPrivileged );
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+    UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+    {
+        UBaseType_t uxReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        uxReturn = uxTaskGetStackHighWaterMark( xTask );
+        vPortResetPrivilege( xRunningPrivileged );
+        return uxReturn;
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+    configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
+    {
+        configSTACK_DEPTH_TYPE uxReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        uxReturn = uxTaskGetStackHighWaterMark2( xTask );
+        vPortResetPrivilege( xRunningPrivileged );
+        return uxReturn;
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ))
+    TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
+    {
+        TaskHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTaskGetCurrentTaskHandle();
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetSchedulerState == 1 )
+    BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTaskGetSchedulerState();
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    vTaskSetTimeOutState( pxTimeOut );
+    vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                     TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait );
+    vPortResetPrivilege( xRunningPrivileged );
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                       UBaseType_t uxIndexToNotify,
+                                       uint32_t ulValue,
+                                       eNotifyAction eAction,
+                                       uint32_t * pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTaskGenericNotify( xTaskToNotify, uxIndexToNotify, ulValue, eAction, pulPreviousNotificationValue );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    BaseType_t MPU_xTaskGenericNotifyWait( UBaseType_t uxIndexToWaitOn,
+                                           uint32_t ulBitsToClearOnEntry,
+                                           uint32_t ulBitsToClearOnExit,
+                                           uint32_t * pulNotificationValue,
+                                           TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTaskGenericNotifyWait( uxIndexToWaitOn, ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    uint32_t MPU_ulTaskGenericNotifyTake( UBaseType_t uxIndexToWaitOn,
+                                          BaseType_t xClearCountOnExit,
+                                          TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+    {
+        uint32_t ulReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        ulReturn = ulTaskGenericNotifyTake( uxIndexToWaitOn, xClearCountOnExit, xTicksToWait );
+        vPortResetPrivilege( xRunningPrivileged );
+        return ulReturn;
+    }
+#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    BaseType_t MPU_xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                                 UBaseType_t uxIndexToClear ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTaskGenericNotifyStateClear( xTask, uxIndexToClear );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+    uint32_t MPU_ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                                UBaseType_t uxIndexToClear,
+                                                uint32_t ulBitsToClear ) /* FREERTOS_SYSTEM_CALL */
+    {
+        uint32_t ulReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        ulReturn = ulTaskGenericNotifyValueClear( xTask, uxIndexToClear, ulBitsToClear );
+        vPortResetPrivilege( xRunningPrivileged );
+        return ulReturn;
+    }
+#endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength,
+                                           UBaseType_t uxItemSize,
+                                           uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
+    {
+        QueueHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
+                                                 const UBaseType_t uxItemSize,
+                                                 uint8_t * pucQueueStorage,
+                                                 StaticQueue_t * pxStaticQueue,
+                                                 const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
+    {
+        QueueHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue,
+                                   BaseType_t xNewQueue ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xQueueGenericReset( pxQueue, xNewQueue );
+    vPortResetPrivilege( xRunningPrivileged );
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue,
+                                  const void * const pvItemToQueue,
+                                  TickType_t xTicksToWait,
+                                  BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );
+    vPortResetPrivilege( xRunningPrivileged );
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+    UBaseType_t uxReturn;
+
+    uxReturn = uxQueueMessagesWaiting( pxQueue );
+    vPortResetPrivilege( xRunningPrivileged );
+    return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+    UBaseType_t uxReturn;
+
+    uxReturn = uxQueueSpacesAvailable( xQueue );
+    vPortResetPrivilege( xRunningPrivileged );
+    return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue,
+                              void * const pvBuffer,
+                              TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+    BaseType_t xReturn;
+
+    xReturn = xQueueReceive( pxQueue, pvBuffer, xTicksToWait );
+    vPortResetPrivilege( xRunningPrivileged );
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue,
+                           void * const pvBuffer,
+                           TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+    BaseType_t xReturn;
+
+    xReturn = xQueuePeek( xQueue, pvBuffer, xTicksToWait );
+    vPortResetPrivilege( xRunningPrivileged );
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                    TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+    BaseType_t xReturn;
+
+    xReturn = xQueueSemaphoreTake( xQueue, xTicksToWait );
+    vPortResetPrivilege( xRunningPrivileged );
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+    TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+        void * xReturn;
+
+        xReturn = xQueueGetMutexHolder( xSemaphore );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+    QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
+    {
+        QueueHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xQueueCreateMutex( ucQueueType );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+    QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType,
+                                               StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
+    {
+        QueueHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xQueueCreateMutexStatic( ucQueueType, pxStaticQueue );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+    QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue,
+                                                     UBaseType_t uxInitialCount ) /* FREERTOS_SYSTEM_CALL */
+    {
+        QueueHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif /* if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+    QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
+                                                           const UBaseType_t uxInitialCount,
+                                                           StaticQueue_t * pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
+    {
+        QueueHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif /* if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                             TickType_t xBlockTime ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif /* if ( configUSE_RECURSIVE_MUTEXES == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+    BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xQueueGiveMutexRecursive( xMutex );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+    QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength ) /* FREERTOS_SYSTEM_CALL */
+    {
+        QueueSetHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xQueueCreateSet( uxEventQueueLength );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+    QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                    TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */
+    {
+        QueueSetMemberHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+    BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                   QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+    BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                        QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );
+        vPortResetPrivilege( xRunningPrivileged );
+        return xReturn;
+    }
+#endif /* if ( configUSE_QUEUE_SETS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if configQUEUE_REGISTRY_SIZE > 0
+    void MPU_vQueueAddToRegistry( QueueHandle_t xQueue,
+                                  const char * pcName ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        vQueueAddToRegistry( xQueue, pcName );
+
+        vPortResetPrivilege( xRunningPrivileged );
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if configQUEUE_REGISTRY_SIZE > 0
+    void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        vQueueUnregisterQueue( xQueue );
+
+        vPortResetPrivilege( xRunningPrivileged );
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if configQUEUE_REGISTRY_SIZE > 0
+    const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+        const char * pcReturn;
+
+        pcReturn = pcQueueGetName( xQueue );
+
+        vPortResetPrivilege( xRunningPrivileged );
+        return pcReturn;
+    }
+#endif /* if configQUEUE_REGISTRY_SIZE > 0 */
+/*-----------------------------------------------------------*/
+
+void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    vQueueDelete( xQueue );
+
+    vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    void MPU_vPortInitialiseBlocks( void ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        vPortInitialiseBlocks();
+
+        vPortResetPrivilege( xRunningPrivileged );
+    }
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    size_t MPU_xPortGetFreeHeapSize( void ) /* FREERTOS_SYSTEM_CALL */
+    {
+        size_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xPortGetFreeHeapSize();
+
+        vPortResetPrivilege( xRunningPrivileged );
+
+        return xReturn;
+    }
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )
+    TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName,
+                                    const TickType_t xTimerPeriodInTicks,
+                                    const UBaseType_t uxAutoReload,
+                                    void * const pvTimerID,
+                                    TimerCallbackFunction_t pxCallbackFunction ) /* FREERTOS_SYSTEM_CALL */
+    {
+        TimerHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTimerCreate( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction );
+        vPortResetPrivilege( xRunningPrivileged );
+
+        return xReturn;
+    }
+#endif /* if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )
+    TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName,
+                                          const TickType_t xTimerPeriodInTicks,
+                                          const UBaseType_t uxAutoReload,
+                                          void * const pvTimerID,
+                                          TimerCallbackFunction_t pxCallbackFunction,
+                                          StaticTimer_t * pxTimerBuffer ) /* FREERTOS_SYSTEM_CALL */
+    {
+        TimerHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer );
+        vPortResetPrivilege( xRunningPrivileged );
+
+        return xReturn;
+    }
+#endif /* if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+    void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+    {
+        void * pvReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        pvReturn = pvTimerGetTimerID( xTimer );
+        vPortResetPrivilege( xRunningPrivileged );
+
+        return pvReturn;
+    }
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+    void MPU_vTimerSetTimerID( TimerHandle_t xTimer,
+                               void * pvNewID ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        vTimerSetTimerID( xTimer, pvNewID );
+        vPortResetPrivilege( xRunningPrivileged );
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+    BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTimerIsTimerActive( xTimer );
+        vPortResetPrivilege( xRunningPrivileged );
+
+        return xReturn;
+    }
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+    TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
+    {
+        TaskHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTimerGetTimerDaemonTaskHandle();
+        vPortResetPrivilege( xRunningPrivileged );
+
+        return xReturn;
+    }
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+    BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+                                           void * pvParameter1,
+                                           uint32_t ulParameter2,
+                                           TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait );
+        vPortResetPrivilege( xRunningPrivileged );
+
+        return xReturn;
+    }
+#endif /* if ( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+    void MPU_vTimerSetReloadMode( TimerHandle_t xTimer,
+                                  const UBaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        vTimerSetReloadMode( xTimer, uxAutoReload );
+        vPortResetPrivilege( xRunningPrivileged );
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+    UBaseType_t MPU_uxTimerGetReloadMode( TimerHandle_t xTimer )
+    {
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+        UBaseType_t uxReturn;
+
+        uxReturn = uxTimerGetReloadMode( xTimer );
+        vPortResetPrivilege( xRunningPrivileged );
+        return uxReturn;
+    }
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+    const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+    {
+        const char * pcReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        pcReturn = pcTimerGetName( xTimer );
+        vPortResetPrivilege( xRunningPrivileged );
+
+        return pcReturn;
+    }
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+    TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+    {
+        TickType_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTimerGetPeriod( xTimer );
+        vPortResetPrivilege( xRunningPrivileged );
+
+        return xReturn;
+    }
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+    TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
+    {
+        TickType_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTimerGetExpiryTime( xTimer );
+        vPortResetPrivilege( xRunningPrivileged );
+
+        return xReturn;
+    }
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+    BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer,
+                                         const BaseType_t xCommandID,
+                                         const TickType_t xOptionalValue,
+                                         BaseType_t * const pxHigherPriorityTaskWoken,
+                                         const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+    {
+        BaseType_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
+        vPortResetPrivilege( xRunningPrivileged );
+
+        return xReturn;
+    }
+#endif /* if ( configUSE_TIMERS == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    EventGroupHandle_t MPU_xEventGroupCreate( void ) /* FREERTOS_SYSTEM_CALL */
+    {
+        EventGroupHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xEventGroupCreate();
+        vPortResetPrivilege( xRunningPrivileged );
+
+        return xReturn;
+    }
+#endif /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t * pxEventGroupBuffer ) /* FREERTOS_SYSTEM_CALL */
+    {
+        EventGroupHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xEventGroupCreateStatic( pxEventGroupBuffer );
+        vPortResetPrivilege( xRunningPrivileged );
+
+        return xReturn;
+    }
+#endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup,
+                                     const EventBits_t uxBitsToWaitFor,
+                                     const BaseType_t xClearOnExit,
+                                     const BaseType_t xWaitForAllBits,
+                                     TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+    EventBits_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
+    vPortResetPrivilege( xRunningPrivileged );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup,
+                                      const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */
+{
+    EventBits_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );
+    vPortResetPrivilege( xRunningPrivileged );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup,
+                                    const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */
+{
+    EventBits_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );
+    vPortResetPrivilege( xRunningPrivileged );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup,
+                                 const EventBits_t uxBitsToSet,
+                                 const EventBits_t uxBitsToWaitFor,
+                                 TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+    EventBits_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
+    vPortResetPrivilege( xRunningPrivileged );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    vEventGroupDelete( xEventGroup );
+    vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                              const void * pvTxData,
+                              size_t xDataLengthBytes,
+                              TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+    size_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
+    vPortResetPrivilege( xRunningPrivileged );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+    size_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
+    vPortResetPrivilege( xRunningPrivileged );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                                 void * pvRxData,
+                                 size_t xBufferLengthBytes,
+                                 TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
+{
+    size_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
+    vPortResetPrivilege( xRunningPrivileged );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    vStreamBufferDelete( xStreamBuffer );
+    vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xStreamBufferIsFull( xStreamBuffer );
+    vPortResetPrivilege( xRunningPrivileged );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xStreamBufferIsEmpty( xStreamBuffer );
+    vPortResetPrivilege( xRunningPrivileged );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xStreamBufferReset( xStreamBuffer );
+    vPortResetPrivilege( xRunningPrivileged );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+    size_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );
+    vPortResetPrivilege( xRunningPrivileged );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+{
+    size_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xStreamBufferBytesAvailable( xStreamBuffer );
+    vPortResetPrivilege( xRunningPrivileged );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                             size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */
+{
+    BaseType_t xReturn;
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
+    vPortResetPrivilege( xRunningPrivileged );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+    StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+                                                         size_t xTriggerLevelBytes,
+                                                         BaseType_t xIsMessageBuffer ) /* FREERTOS_SYSTEM_CALL */
+    {
+        StreamBufferHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer );
+        vPortResetPrivilege( xRunningPrivileged );
+
+        return xReturn;
+    }
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+    StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+                                                               size_t xTriggerLevelBytes,
+                                                               BaseType_t xIsMessageBuffer,
+                                                               uint8_t * const pucStreamBufferStorageArea,
+                                                               StaticStreamBuffer_t * const pxStaticStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
+    {
+        StreamBufferHandle_t xReturn;
+        BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+        xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pucStreamBufferStorageArea, pxStaticStreamBuffer );
+        vPortResetPrivilege( xRunningPrivileged );
+
+        return xReturn;
+    }
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+
+/* Functions that the application writer wants to execute in privileged mode
+ * can be defined in application_defined_privileged_functions.h.  The functions
+ * must take the same format as those above whereby the privilege state on exit
+ * equals the privilege state on entry.  For example:
+ *
+ * void MPU_FunctionName( [parameters ] )
+ * {
+ * BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+ *
+ *  FunctionName( [parameters ] );
+ *
+ *  vPortResetPrivilege( xRunningPrivileged );
+ * }
+ */
+
+#if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1
+    #include "application_defined_privileged_functions.h"
+#endif
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/port.c
new file mode 100644
index 0000000..4b71df5
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/port.c
@@ -0,0 +1,238 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Atmel AT91R40008
+ * port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file.  The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Hardware specific definitions. */
+#include "AT91R40008.h"
+#include "pio.h"
+#include "aic.h"
+#include "tc.h"
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING	( ( StackType_t ) 0 )
+#define portTICK_PRIORITY_6				( 6 )
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* 
+ * The scheduler can only be started from ARM mode, so 
+ * vPortISRStartFirstSTask() is defined in portISR.c. 
+ */
+extern void vPortISRStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+	
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The last thing onto the stack is the status register, which is set for
+	system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	#ifdef THUMB_INTERWORK
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+	#endif
+
+	pxTopOfStack--;
+
+	/* Some optimisation levels use the stack differently to others.  This 
+	means the interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortISRStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the tick timer to generate the tick interrupts at the required frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+volatile uint32_t ulDummy;
+
+	/* Enable clock to the tick timer... */
+	AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT;
+
+	/* Stop the tick timer... */
+	portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS;
+
+	/* Start with tick timer interrupts disabled... */
+	portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF;
+
+	/* Clear any pending tick timer interrupts... */
+	ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
+
+	/* Store interrupt handler function address in tick timer vector register...
+	The ISR installed depends on whether the preemptive or cooperative
+	scheduler is being used. */
+	#if configUSE_PREEMPTION == 1
+	{
+		extern void ( vPreemptiveTick )( void );
+		AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vPreemptiveTick;
+	}
+	#else  // else use cooperative scheduler
+	{
+		extern void ( vNonPreemptiveTick )( void );
+		AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vNonPreemptiveTick;
+	}
+	#endif
+
+	/* Tick timer interrupt level-sensitive, priority 6... */
+	AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6;
+
+	/* Enable the tick timer interrupt...
+
+	First at timer level */
+	portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
+
+	/* Then at the AIC level. */
+	AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL);
+
+	/* Calculate timer compare value to achieve the desired tick rate... */
+	if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF )
+	{
+		/* The tick rate is fast enough for us to use the faster timer input
+		clock (main clock / 2). */
+		portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;
+		portTIMER_REG_BASE_PTR->TC_RC  = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2);
+	}
+	else
+	{
+		/* We must use a slower timer input clock (main clock / 8) because the
+		tick rate is too slow for the faster input clock. */
+		portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;
+		portTIMER_REG_BASE_PTR->TC_RC  = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8);
+	}
+
+	/* Start tick timer... */
+	portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portISR.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portISR.c
new file mode 100644
index 0000000..32498c6
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portISR.c
@@ -0,0 +1,233 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c  The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/*
+	Changes from V3.2.4
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to handle interrupts. */
+#define portCLEAR_AIC_INTERRUPT		( ( uint32_t ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* ISR to handle manual context switches (from a call to taskYIELD()). */
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+
+/* 
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+	/* Simply start the scheduler.  This is included here as it can only be
+	called from ARM mode. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ *
+ * When a context switch is performed from the task level the saved task 
+ * context is made to look as if it occurred from within the tick ISR.  This
+ * way the same restore context function can be used when restoring the context
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.
+ */
+void vPortYieldProcessor( void )
+{
+	/* Within an IRQ ISR the link register has an offset from the true return 
+	address, but an SWI ISR does not.  Add the offset manually so the same 
+	ISR return code can be used in both cases. */
+	asm volatile ( "ADD		LR, LR, #4" );
+
+	/* Perform the context switch.  First save the context of the current task. */
+	portSAVE_CONTEXT();
+
+	/* Find the highest priority task that is ready to run. */
+	vTaskSwitchContext();
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();	
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+
+#if configUSE_PREEMPTION == 0
+
+	/* The cooperative scheduler requires a normal IRQ service routine to 
+	simply increment the system tick. */
+	void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+	void vNonPreemptiveTick( void )
+	{		
+	static volatile uint32_t ulDummy;
+
+		/* Clear tick timer interrupt indication. */
+		ulDummy = portTIMER_REG_BASE_PTR->TC_SR;  
+
+		xTaskIncrementTick();
+
+		/* Acknowledge the interrupt at AIC level... */
+		AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
+	}
+
+#else  /* else preemption is turned on */
+
+	/* The preemptive scheduler is defined as "naked" as the full context is
+	saved on entry as part of the context switch. */
+	void vPreemptiveTick( void ) __attribute__((naked));
+	void vPreemptiveTick( void )
+	{
+		/* Save the context of the interrupted task. */
+		portSAVE_CONTEXT();	
+
+		/* WARNING - Do not use local (stack) variables here.  Use globals
+					 if you must! */
+		static volatile uint32_t ulDummy;
+
+		/* Clear tick timer interrupt indication. */
+		ulDummy = portTIMER_REG_BASE_PTR->TC_SR;  
+
+		/* Increment the RTOS tick count, then look for the highest priority 
+		task that is ready to run. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			vTaskSwitchContext();
+		}
+
+		/* Acknowledge the interrupt at AIC level... */
+		AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
+
+		/* Restore the context of the new task. */
+		portRESTORE_CONTEXT();
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+#ifdef THUMB_INTERWORK
+
+	void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	void vPortDisableInterruptsFromThumb( void )
+	{
+		asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+			
+	void vPortEnableInterruptsFromThumb( void )
+	{
+		asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/	
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/	
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/	
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/	
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+
+#endif /* THUMB_INTERWORK */
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels.  The interrupt flags can therefore not always
+be saved to the stack.  Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
+	asm volatile ( 
+		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
+		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
+		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
+		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
+		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed 
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable interrupts as per portEXIT_CRITICAL().				*/
+			asm volatile ( 
+				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	
+				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	
+				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	
+				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	
+				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
+		}
+	}
+}
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h
new file mode 100644
index 0000000..a72538f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h
@@ -0,0 +1,255 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+	Changes from V3.2.3
+
+	+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+	Changes from V3.2.4
+
+	+ Removed the use of the %0 parameter within the assembler macros and
+	  replaced them with hard coded registers.  This will ensure the
+	  assembler does not select the link register as the temp register as
+	  was occasionally happening previously.
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+
+	Changes from V4.5.0
+
+	+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+	  and replaced them with portYIELD_FROM_ISR() macro.  Application code
+	  should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+	  macros as per the V4.5.1 demo code.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portYIELD()					asm volatile ( "SWI 0" )
+#define portNOP()					asm volatile ( "NOP" )
+
+/*
+ * These define the timer to use for generating the tick interrupt.
+ * They are put in this file so they can be shared between "port.c"
+ * and "portisr.c".
+ */
+#define portTIMER_REG_BASE_PTR		AT91C_BASE_TC0
+#define portTIMER_CLK_ENABLE_BIT	AT91C_PS_TC0
+#define portTIMER_AIC_CHANNEL		( ( uint32_t ) 4 )
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
+ * are included here for efficiency.  An attempt to call one from
+ * THUMB mode code will result in a compile time error.
+ */
+
+#define portRESTORE_CONTEXT()											\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile uint32_t ulCriticalNesting;					\
+																		\
+	/* Set the LR to the task stack. */									\
+	asm volatile (														\
+	"LDR		R0, =pxCurrentTCB								\n\t"	\
+	"LDR		R0, [R0]										\n\t"	\
+	"LDR		LR, [R0]										\n\t"	\
+																		\
+	/* The critical nesting depth is the first item on the stack. */	\
+	/* Load it into the ulCriticalNesting variable. */					\
+	"LDR		R0, =ulCriticalNesting							\n\t"	\
+	"LDMFD	LR!, {R1}											\n\t"	\
+	"STR		R1, [R0]										\n\t"	\
+																		\
+	/* Get the SPSR from the stack. */									\
+	"LDMFD	LR!, {R0}											\n\t"	\
+	"MSR		SPSR, R0										\n\t"	\
+																		\
+	/* Restore all system mode registers for the task. */				\
+	"LDMFD	LR, {R0-R14}^										\n\t"	\
+	"NOP														\n\t"	\
+																		\
+	/* Restore the return address. */									\
+	"LDR		LR, [LR, #+60]									\n\t"	\
+																		\
+	/* And return - correcting the offset in the LR to obtain the */	\
+	/* correct address. */												\
+	"SUBS	PC, LR, #4											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+/*-----------------------------------------------------------*/
+
+#define portSAVE_CONTEXT()												\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile uint32_t ulCriticalNesting;					\
+																		\
+	/* Push R0 as we are going to use the register. */					\
+	asm volatile (														\
+	"STMDB	SP!, {R0}											\n\t"	\
+																		\
+	/* Set R0 to point to the task stack pointer. */					\
+	"STMDB	SP,{SP}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	SP, SP, #4											\n\t"	\
+	"LDMIA	SP!,{R0}											\n\t"	\
+																		\
+	/* Push the return address onto the stack. */						\
+	"STMDB	R0!, {LR}											\n\t"	\
+																		\
+	/* Now we have saved LR we can use it instead of R0. */				\
+	"MOV	LR, R0												\n\t"	\
+																		\
+	/* Pop R0 so we can save it onto the system mode stack. */			\
+	"LDMIA	SP!, {R0}											\n\t"	\
+																		\
+	/* Push all the system mode registers onto the task stack. */		\
+	"STMDB	LR,{R0-LR}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	LR, LR, #60											\n\t"	\
+																		\
+	/* Push the SPSR onto the task stack. */							\
+	"MRS	R0, SPSR											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	"LDR	R0, =ulCriticalNesting								\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	/* Store the new top of stack for the task. */						\
+	"LDR	R0, =pxCurrentTCB									\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STR	LR, [R0]											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+
+/* Critical section handling. */
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in
+ * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
+	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
+
+#else
+
+	#define portDISABLE_INTERRUPTS()											\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+	#define portENABLE_INTERRUPTS()												\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
new file mode 100644
index 0000000..a14279e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
@@ -0,0 +1,2731 @@
+//  ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+//  ----------------------------------------------------------------------------
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  ----------------------------------------------------------------------------
+// File Name           : AT91SAM7X256.h
+// Object              : AT91SAM7X256 definitions
+// Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
+// 
+// CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
+// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
+// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
+// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
+// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
+// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
+// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
+// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
+// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
+// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
+// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
+// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
+// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
+// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+//  ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7X256_H
+#define AT91SAM7X256_H
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved2[45]; 	// 
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved3[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved4[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved5[54]; 	// 
+	AT91_REG	 PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved6[1]; 	// 
+	AT91_REG	 PIOA_OER; 	// Output Enable Register
+	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved7[1]; 	// 
+	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved8[1]; 	// 
+	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved9[1]; 	// 
+	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved10[1]; 	// 
+	AT91_REG	 PIOA_ASR; 	// Select A Register
+	AT91_REG	 PIOA_BSR; 	// Select B Register
+	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved11[9]; 	// 
+	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved12[85]; 	// 
+	AT91_REG	 PIOB_PER; 	// PIO Enable Register
+	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOB_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved13[1]; 	// 
+	AT91_REG	 PIOB_OER; 	// Output Enable Register
+	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOB_OSR; 	// Output Status Register
+	AT91_REG	 Reserved14[1]; 	// 
+	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved15[1]; 	// 
+	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved16[1]; 	// 
+	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved17[1]; 	// 
+	AT91_REG	 PIOB_ASR; 	// Select A Register
+	AT91_REG	 PIOB_BSR; 	// Select B Register
+	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved18[9]; 	// 
+	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved19[341]; 	// 
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved20[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved21[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved22[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved23[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved24[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved25[36]; 	// 
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+	AT91_REG	 Reserved26[5]; 	// 
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+	AT91_REG	 Reserved27[5]; 	// 
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
+#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved0[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved1[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved3[1]; 	// 
+	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved4[1]; 	// 
+	AT91_REG	 PIO_ASR; 	// Select A Register
+	AT91_REG	 PIO_BSR; 	// Select B Register
+	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved5[9]; 	// 
+	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 CKGR_PLLR; 	// PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved3[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved4[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
+
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+	AT91_REG	 MC_RCR; 	// MC Remap Control Register
+	AT91_REG	 MC_ASR; 	// MC Abort Status Register
+	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
+	AT91_REG	 Reserved0[21]; 	// 
+	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
+	AT91_REG	 MC_FCR; 	// MC Flash Command Register
+	AT91_REG	 MC_FSR; 	// MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91_REG	 Reserved1[48]; 	// 
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	// 
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved3[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved1[3]; 	// 
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
+	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
+	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
+	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
+	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
+	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
+	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
+	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
+	AT91_REG	 PWMC_SR; 	// PWMC Status Register
+	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
+	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
+	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
+	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
+	AT91_REG	 Reserved0[55]; 	// 
+	AT91_REG	 PWMC_VR; 	// PWMC Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
+	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
+	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
+	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
+	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
+	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
+	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
+	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
+
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+	AT91_REG	 CAN_MR; 	// Mode Register
+	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
+	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
+	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
+	AT91_REG	 CAN_SR; 	// Status Register
+	AT91_REG	 CAN_BR; 	// Baudrate Register
+	AT91_REG	 CAN_TIM; 	// Timer Register
+	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
+	AT91_REG	 CAN_ECR; 	// Error Counter Register
+	AT91_REG	 CAN_TCR; 	// Transfer Command Register
+	AT91_REG	 CAN_ACR; 	// Abort Command Register
+	AT91_REG	 Reserved0[52]; 	// 
+	AT91_REG	 CAN_VR; 	// Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
+	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
+	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
+	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
+	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
+	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
+	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
+	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
+	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
+	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
+	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
+	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
+	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
+	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
+	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
+	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
+
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+	AT91_REG	 EMAC_NCR; 	// Network Control Register
+	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
+	AT91_REG	 EMAC_NSR; 	// Network Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
+	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
+	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
+	AT91_REG	 EMAC_RSR; 	// Receive Status Register
+	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
+	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
+	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
+	AT91_REG	 EMAC_PTR; 	// Pause Time Register
+	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
+	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
+	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
+	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
+	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
+	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
+	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
+	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
+	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
+	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
+	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
+	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
+	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
+	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
+	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
+	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
+	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
+	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
+	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
+	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
+	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
+	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
+	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
+	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
+	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
+	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
+	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
+	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
+	AT91_REG	 Reserved1[13]; 	// 
+	AT91_REG	 EMAC_REV; 	// Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+	AT91_REG	 ADC_CR; 	// ADC Control Register
+	AT91_REG	 ADC_MR; 	// ADC Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
+	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
+	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
+	AT91_REG	 ADC_SR; 	// ADC Status Register
+	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
+	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
+	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
+	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
+	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
+	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
+	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
+	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
+	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
+	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
+	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
+	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
+	AT91_REG	 ADC_RCR; 	// Receive Counter Register
+	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
+	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+	AT91_REG	 AES_CR; 	// Control Register
+	AT91_REG	 AES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AES_IER; 	// Interrupt Enable Register
+	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AES_ISR; 	// Interrupt Status Register
+	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
+	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
+	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved2[35]; 	// 
+	AT91_REG	 AES_VR; 	// AES Version Register
+	AT91_REG	 AES_RPR; 	// Receive Pointer Register
+	AT91_REG	 AES_RCR; 	// Receive Counter Register
+	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 AES_TCR; 	// Transmit Counter Register
+	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
+
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
+#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
+#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
+#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
+#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+	AT91_REG	 TDES_CR; 	// Control Register
+	AT91_REG	 TDES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
+	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
+	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
+	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
+	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved4[37]; 	// 
+	AT91_REG	 TDES_VR; 	// TDES Version Register
+	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
+	AT91_REG	 TDES_RCR; 	// Receive Counter Register
+	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
+	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
+
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
+#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ========== 
+#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ========== 
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ========== 
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ========== 
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ========== 
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ========== 
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ========== 
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ========== 
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ========== 
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ========== 
+#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ========== 
+#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ========== 
+#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ========== 
+#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ========== 
+#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ========== 
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
+#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
+#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
+#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
+#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
+#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
+#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
+#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
+#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
+#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
+#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
+#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
+#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
+#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
+#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
+#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
+#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
+#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
+#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
+#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
+#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
+#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
+#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
+#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
+#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
+#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
+#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
+#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
+#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
+#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
+#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
+#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
+#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
+#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
+#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
+#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
+#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
+#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
+#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
+#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
+#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
+#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
+#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
+#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
+#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
+
+#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler )		\
+{																			\
+    unsigned int mask ;														\
+																			\
+    mask = 0x1 << irq_id;													\
+    /* Disable the interrupt on the interrupt controller */					\
+    AT91C_BASE_AIC->AIC_IDCR = mask ;										\
+    /* Save the interrupt handler routine pointer and the interrupt priority */	\
+    AT91C_BASE_AIC->AIC_SVR[irq_id] = (unsigned int) newHandler ;			\
+    /* Store the Source Mode Register */									\
+    AT91C_BASE_AIC->AIC_SMR[irq_id] = src_type | priority  ;				\
+    /* Clear the interrupt on the interrupt controller */					\
+    AT91C_BASE_AIC->AIC_ICCR = mask ;										\
+}
+
+
+#endif
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
new file mode 100644
index 0000000..8ea721e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
@@ -0,0 +1,4698 @@
+// - ----------------------------------------------------------------------------
+// -          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// - ----------------------------------------------------------------------------
+// -  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+// -  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+// -  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+// -  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+// -  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// -  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+// -  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// -  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// -  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+// -  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// - ----------------------------------------------------------------------------
+// - File Name           : AT91SAM7X256.h
+// - Object              : AT91SAM7X256 definitions
+// - Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
+// - 
+// - CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
+// - CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
+// - CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// - CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
+// - CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
+// - CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// - CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// - CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// - CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
+// - CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
+// - CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
+// - CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
+// - CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
+// - CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
+// - CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// - CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// - CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// - CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// - CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// - CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// - CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
+// - CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
+// - CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// - CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
+// - CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+// - ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7X256_H
+#define AT91SAM7X256_H
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved2[45]; 	// 
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved3[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved4[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved5[54]; 	// 
+	AT91_REG	 PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved6[1]; 	// 
+	AT91_REG	 PIOA_OER; 	// Output Enable Register
+	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved7[1]; 	// 
+	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved8[1]; 	// 
+	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved9[1]; 	// 
+	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved10[1]; 	// 
+	AT91_REG	 PIOA_ASR; 	// Select A Register
+	AT91_REG	 PIOA_BSR; 	// Select B Register
+	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved11[9]; 	// 
+	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved12[85]; 	// 
+	AT91_REG	 PIOB_PER; 	// PIO Enable Register
+	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOB_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved13[1]; 	// 
+	AT91_REG	 PIOB_OER; 	// Output Enable Register
+	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOB_OSR; 	// Output Status Register
+	AT91_REG	 Reserved14[1]; 	// 
+	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved15[1]; 	// 
+	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved16[1]; 	// 
+	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved17[1]; 	// 
+	AT91_REG	 PIOB_ASR; 	// Select A Register
+	AT91_REG	 PIOB_BSR; 	// Select B Register
+	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved18[9]; 	// 
+	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved19[341]; 	// 
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved20[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved21[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved22[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved23[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved24[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved25[36]; 	// 
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+	AT91_REG	 Reserved26[5]; 	// 
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+	AT91_REG	 Reserved27[5]; 	// 
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
+#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved0[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved1[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved3[1]; 	// 
+	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved4[1]; 	// 
+	AT91_REG	 PIO_ASR; 	// Select A Register
+	AT91_REG	 PIO_BSR; 	// Select B Register
+	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved5[9]; 	// 
+	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 CKGR_PLLR; 	// PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved3[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved4[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
+
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+	AT91_REG	 MC_RCR; 	// MC Remap Control Register
+	AT91_REG	 MC_ASR; 	// MC Abort Status Register
+	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
+	AT91_REG	 Reserved0[21]; 	// 
+	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
+	AT91_REG	 MC_FCR; 	// MC Flash Command Register
+	AT91_REG	 MC_FSR; 	// MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91_REG	 Reserved1[48]; 	// 
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	// 
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved3[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved1[3]; 	// 
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
+	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
+	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
+	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
+	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
+	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
+	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
+	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
+	AT91_REG	 PWMC_SR; 	// PWMC Status Register
+	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
+	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
+	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
+	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
+	AT91_REG	 Reserved0[55]; 	// 
+	AT91_REG	 PWMC_VR; 	// PWMC Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
+	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
+	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
+	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
+	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
+	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
+	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
+	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
+
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+	AT91_REG	 CAN_MR; 	// Mode Register
+	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
+	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
+	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
+	AT91_REG	 CAN_SR; 	// Status Register
+	AT91_REG	 CAN_BR; 	// Baudrate Register
+	AT91_REG	 CAN_TIM; 	// Timer Register
+	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
+	AT91_REG	 CAN_ECR; 	// Error Counter Register
+	AT91_REG	 CAN_TCR; 	// Transfer Command Register
+	AT91_REG	 CAN_ACR; 	// Abort Command Register
+	AT91_REG	 Reserved0[52]; 	// 
+	AT91_REG	 CAN_VR; 	// Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
+	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
+	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
+	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
+	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
+	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
+	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
+	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
+	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
+	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
+	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
+	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
+	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
+	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
+	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
+	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
+
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+	AT91_REG	 EMAC_NCR; 	// Network Control Register
+	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
+	AT91_REG	 EMAC_NSR; 	// Network Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
+	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
+	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
+	AT91_REG	 EMAC_RSR; 	// Receive Status Register
+	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
+	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
+	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
+	AT91_REG	 EMAC_PTR; 	// Pause Time Register
+	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
+	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
+	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
+	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
+	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
+	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
+	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
+	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
+	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
+	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
+	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
+	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
+	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
+	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
+	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
+	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
+	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
+	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
+	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
+	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
+	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
+	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
+	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
+	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
+	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
+	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
+	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
+	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
+	AT91_REG	 Reserved1[13]; 	// 
+	AT91_REG	 EMAC_REV; 	// Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+	AT91_REG	 ADC_CR; 	// ADC Control Register
+	AT91_REG	 ADC_MR; 	// ADC Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
+	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
+	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
+	AT91_REG	 ADC_SR; 	// ADC Status Register
+	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
+	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
+	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
+	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
+	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
+	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
+	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
+	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
+	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
+	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
+	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
+	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
+	AT91_REG	 ADC_RCR; 	// Receive Counter Register
+	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
+	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+	AT91_REG	 AES_CR; 	// Control Register
+	AT91_REG	 AES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AES_IER; 	// Interrupt Enable Register
+	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AES_ISR; 	// Interrupt Status Register
+	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
+	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
+	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved2[35]; 	// 
+	AT91_REG	 AES_VR; 	// AES Version Register
+	AT91_REG	 AES_RPR; 	// Receive Pointer Register
+	AT91_REG	 AES_RCR; 	// Receive Counter Register
+	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 AES_TCR; 	// Transmit Counter Register
+	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
+
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
+#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
+#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
+#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
+#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+	AT91_REG	 TDES_CR; 	// Control Register
+	AT91_REG	 TDES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
+	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
+	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
+	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
+	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved4[37]; 	// 
+	AT91_REG	 TDES_VR; 	// TDES Version Register
+	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
+	AT91_REG	 TDES_RCR; 	// Receive Counter Register
+	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
+	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
+
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
+#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ========== 
+#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ========== 
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ========== 
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ========== 
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ========== 
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ========== 
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ========== 
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ========== 
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ========== 
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ========== 
+#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ========== 
+#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ========== 
+#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ========== 
+#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ========== 
+#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ========== 
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
+#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
+#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
+#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
+#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
+#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
+#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
+#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
+#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
+#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
+#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
+#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
+#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
+#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
+#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
+#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
+#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
+#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
+#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
+#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
+#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
+#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
+#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
+#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
+#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
+#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
+#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
+#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
+#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
+#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
+#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
+#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
+#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
+#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
+#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
+#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
+#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
+#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
+#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
+#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
+#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
+#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
+#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
+#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
+#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
+
+
+
+// - Hardware register definition
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR System Peripherals
+// - *****************************************************************************
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// - *****************************************************************************
+// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#if 0 /*_RB_*/
+AT91C_AIC_PRIOR           EQU (0x7 <<  0) ;- (AIC) Priority Level
+AT91C_AIC_PRIOR_LOWEST    EQU (0x0) ;- (AIC) Lowest priority level
+AT91C_AIC_PRIOR_HIGHEST   EQU (0x7) ;- (AIC) Highest priority level
+AT91C_AIC_SRCTYPE         EQU (0x3 <<  5) ;- (AIC) Interrupt Source Type
+AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 <<  5) ;- (AIC) Internal Sources Code Label High-level Sensitive
+AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 <<  5) ;- (AIC) External Sources Code Label Low-level Sensitive
+AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 <<  5) ;- (AIC) Internal Sources Code Label Positive Edge triggered
+AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 <<  5) ;- (AIC) External Sources Code Label Negative Edge triggered
+AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 <<  5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive
+AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 <<  5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+AT91C_AIC_NFIQ            EQU (0x1 <<  0) ;- (AIC) NFIQ Status
+AT91C_AIC_NIRQ            EQU (0x1 <<  1) ;- (AIC) NIRQ Status
+// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+AT91C_AIC_DCR_PROT        EQU (0x1 <<  0) ;- (AIC) Protection Mode
+AT91C_AIC_DCR_GMSK        EQU (0x1 <<  1) ;- (AIC) General Mask
+#endif
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// - *****************************************************************************
+// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+AT91C_PDC_RXTEN           EQU (0x1 <<  0) ;- (PDC) Receiver Transfer Enable
+AT91C_PDC_RXTDIS          EQU (0x1 <<  1) ;- (PDC) Receiver Transfer Disable
+AT91C_PDC_TXTEN           EQU (0x1 <<  8) ;- (PDC) Transmitter Transfer Enable
+AT91C_PDC_TXTDIS          EQU (0x1 <<  9) ;- (PDC) Transmitter Transfer Disable
+// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Debug Unit
+// - *****************************************************************************
+// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+AT91C_US_RSTRX            EQU (0x1 <<  2) ;- (DBGU) Reset Receiver
+AT91C_US_RSTTX            EQU (0x1 <<  3) ;- (DBGU) Reset Transmitter
+AT91C_US_RXEN             EQU (0x1 <<  4) ;- (DBGU) Receiver Enable
+AT91C_US_RXDIS            EQU (0x1 <<  5) ;- (DBGU) Receiver Disable
+AT91C_US_TXEN             EQU (0x1 <<  6) ;- (DBGU) Transmitter Enable
+AT91C_US_TXDIS            EQU (0x1 <<  7) ;- (DBGU) Transmitter Disable
+AT91C_US_RSTSTA           EQU (0x1 <<  8) ;- (DBGU) Reset Status Bits
+// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+AT91C_US_PAR              EQU (0x7 <<  9) ;- (DBGU) Parity type
+AT91C_US_PAR_EVEN         EQU (0x0 <<  9) ;- (DBGU) Even Parity
+AT91C_US_PAR_ODD          EQU (0x1 <<  9) ;- (DBGU) Odd Parity
+AT91C_US_PAR_SPACE        EQU (0x2 <<  9) ;- (DBGU) Parity forced to 0 (Space)
+AT91C_US_PAR_MARK         EQU (0x3 <<  9) ;- (DBGU) Parity forced to 1 (Mark)
+AT91C_US_PAR_NONE         EQU (0x4 <<  9) ;- (DBGU) No Parity
+AT91C_US_PAR_MULTI_DROP   EQU (0x6 <<  9) ;- (DBGU) Multi-drop mode
+AT91C_US_CHMODE           EQU (0x3 << 14) ;- (DBGU) Channel Mode
+AT91C_US_CHMODE_NORMAL    EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+AT91C_US_CHMODE_AUTO      EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+AT91C_US_CHMODE_LOCAL     EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+AT91C_US_CHMODE_REMOTE    EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+AT91C_US_RXRDY            EQU (0x1 <<  0) ;- (DBGU) RXRDY Interrupt
+AT91C_US_TXRDY            EQU (0x1 <<  1) ;- (DBGU) TXRDY Interrupt
+AT91C_US_ENDRX            EQU (0x1 <<  3) ;- (DBGU) End of Receive Transfer Interrupt
+AT91C_US_ENDTX            EQU (0x1 <<  4) ;- (DBGU) End of Transmit Interrupt
+AT91C_US_OVRE             EQU (0x1 <<  5) ;- (DBGU) Overrun Interrupt
+AT91C_US_FRAME            EQU (0x1 <<  6) ;- (DBGU) Framing Error Interrupt
+AT91C_US_PARE             EQU (0x1 <<  7) ;- (DBGU) Parity Error Interrupt
+AT91C_US_TXEMPTY          EQU (0x1 <<  9) ;- (DBGU) TXEMPTY Interrupt
+AT91C_US_TXBUFE           EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt
+AT91C_US_RXBUFF           EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt
+AT91C_US_COMM_TX          EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt
+AT91C_US_COMM_RX          EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt
+// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+AT91C_US_FORCE_NTRST      EQU (0x1 <<  0) ;- (DBGU) Force NTRST in JTAG
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// - *****************************************************************************
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// - *****************************************************************************
+// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+AT91C_CKGR_MOSCEN         EQU (0x1 <<  0) ;- (CKGR) Main Oscillator Enable
+AT91C_CKGR_OSCBYPASS      EQU (0x1 <<  1) ;- (CKGR) Main Oscillator Bypass
+AT91C_CKGR_OSCOUNT        EQU (0xFF <<  8) ;- (CKGR) Main Oscillator Start-up Time
+// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+AT91C_CKGR_MAINF          EQU (0xFFFF <<  0) ;- (CKGR) Main Clock Frequency
+AT91C_CKGR_MAINRDY        EQU (0x1 << 16) ;- (CKGR) Main Clock Ready
+// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+AT91C_CKGR_DIV            EQU (0xFF <<  0) ;- (CKGR) Divider Selected
+AT91C_CKGR_DIV_0          EQU (0x0) ;- (CKGR) Divider output is 0
+AT91C_CKGR_DIV_BYPASS     EQU (0x1) ;- (CKGR) Divider is bypassed
+AT91C_CKGR_PLLCOUNT       EQU (0x3F <<  8) ;- (CKGR) PLL Counter
+AT91C_CKGR_OUT            EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range
+AT91C_CKGR_OUT_0          EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_1          EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_2          EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_OUT_3          EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet
+AT91C_CKGR_MUL            EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier
+AT91C_CKGR_USBDIV         EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks
+AT91C_CKGR_USBDIV_0       EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output
+AT91C_CKGR_USBDIV_1       EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2
+AT91C_CKGR_USBDIV_2       EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Power Management Controler
+// - *****************************************************************************
+// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+AT91C_PMC_PCK             EQU (0x1 <<  0) ;- (PMC) Processor Clock
+AT91C_PMC_UDP             EQU (0x1 <<  7) ;- (PMC) USB Device Port Clock
+AT91C_PMC_PCK0            EQU (0x1 <<  8) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK1            EQU (0x1 <<  9) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK2            EQU (0x1 << 10) ;- (PMC) Programmable Clock Output
+AT91C_PMC_PCK3            EQU (0x1 << 11) ;- (PMC) Programmable Clock Output
+// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+AT91C_PMC_CSS             EQU (0x3 <<  0) ;- (PMC) Programmable Clock Selection
+AT91C_PMC_CSS_SLOW_CLK    EQU (0x0) ;- (PMC) Slow Clock is selected
+AT91C_PMC_CSS_MAIN_CLK    EQU (0x1) ;- (PMC) Main Clock is selected
+AT91C_PMC_CSS_PLL_CLK     EQU (0x3) ;- (PMC) Clock from PLL is selected
+AT91C_PMC_PRES            EQU (0x7 <<  2) ;- (PMC) Programmable Clock Prescaler
+AT91C_PMC_PRES_CLK        EQU (0x0 <<  2) ;- (PMC) Selected clock
+AT91C_PMC_PRES_CLK_2      EQU (0x1 <<  2) ;- (PMC) Selected clock divided by 2
+AT91C_PMC_PRES_CLK_4      EQU (0x2 <<  2) ;- (PMC) Selected clock divided by 4
+AT91C_PMC_PRES_CLK_8      EQU (0x3 <<  2) ;- (PMC) Selected clock divided by 8
+AT91C_PMC_PRES_CLK_16     EQU (0x4 <<  2) ;- (PMC) Selected clock divided by 16
+AT91C_PMC_PRES_CLK_32     EQU (0x5 <<  2) ;- (PMC) Selected clock divided by 32
+AT91C_PMC_PRES_CLK_64     EQU (0x6 <<  2) ;- (PMC) Selected clock divided by 64
+// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+AT91C_PMC_MOSCS           EQU (0x1 <<  0) ;- (PMC) MOSC Status/Enable/Disable/Mask
+AT91C_PMC_LOCK            EQU (0x1 <<  2) ;- (PMC) PLL Status/Enable/Disable/Mask
+AT91C_PMC_MCKRDY          EQU (0x1 <<  3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK0RDY         EQU (0x1 <<  8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK1RDY         EQU (0x1 <<  9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK2RDY         EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
+AT91C_PMC_PCK3RDY         EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// - *****************************************************************************
+// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+AT91C_RSTC_PROCRST        EQU (0x1 <<  0) ;- (RSTC) Processor Reset
+AT91C_RSTC_PERRST         EQU (0x1 <<  2) ;- (RSTC) Peripheral Reset
+AT91C_RSTC_EXTRST         EQU (0x1 <<  3) ;- (RSTC) External Reset
+AT91C_RSTC_KEY            EQU (0xFF << 24) ;- (RSTC) Password
+// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+AT91C_RSTC_URSTS          EQU (0x1 <<  0) ;- (RSTC) User Reset Status
+AT91C_RSTC_BODSTS         EQU (0x1 <<  1) ;- (RSTC) Brownout Detection Status
+AT91C_RSTC_RSTTYP         EQU (0x7 <<  8) ;- (RSTC) Reset Type
+AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 <<  8) ;- (RSTC) Power-up Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WAKEUP  EQU (0x1 <<  8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
+AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 <<  8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
+AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 <<  8) ;- (RSTC) Software Reset. Processor reset required by the software.
+AT91C_RSTC_RSTTYP_USER    EQU (0x4 <<  8) ;- (RSTC) User Reset. NRST pin detected low.
+AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 <<  8) ;- (RSTC) Brownout Reset occured.
+AT91C_RSTC_NRSTL          EQU (0x1 << 16) ;- (RSTC) NRST pin level
+AT91C_RSTC_SRCMP          EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.
+// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+AT91C_RSTC_URSTEN         EQU (0x1 <<  0) ;- (RSTC) User Reset Enable
+AT91C_RSTC_URSTIEN        EQU (0x1 <<  4) ;- (RSTC) User Reset Interrupt Enable
+AT91C_RSTC_ERSTL          EQU (0xF <<  8) ;- (RSTC) User Reset Enable
+AT91C_RSTC_BODIEN         EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// - *****************************************************************************
+// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+AT91C_RTTC_RTPRES         EQU (0xFFFF <<  0) ;- (RTTC) Real-time Timer Prescaler Value
+AT91C_RTTC_ALMIEN         EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable
+AT91C_RTTC_RTTINCIEN      EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
+AT91C_RTTC_RTTRST         EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart
+// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+AT91C_RTTC_ALMV           EQU (0x0 <<  0) ;- (RTTC) Alarm Value
+// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+AT91C_RTTC_CRTV           EQU (0x0 <<  0) ;- (RTTC) Current Real-time Value
+// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+AT91C_RTTC_ALMS           EQU (0x1 <<  0) ;- (RTTC) Real-time Alarm Status
+AT91C_RTTC_RTTINC         EQU (0x1 <<  1) ;- (RTTC) Real-time Timer Increment
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// - *****************************************************************************
+// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+AT91C_PITC_PIV            EQU (0xFFFFF <<  0) ;- (PITC) Periodic Interval Value
+AT91C_PITC_PITEN          EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled
+AT91C_PITC_PITIEN         EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable
+// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+AT91C_PITC_PITS           EQU (0x1 <<  0) ;- (PITC) Periodic Interval Timer Status
+// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+AT91C_PITC_CPIV           EQU (0xFFFFF <<  0) ;- (PITC) Current Periodic Interval Value
+AT91C_PITC_PICNT          EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter
+// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// - *****************************************************************************
+// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+AT91C_WDTC_WDRSTT         EQU (0x1 <<  0) ;- (WDTC) Watchdog Restart
+AT91C_WDTC_KEY            EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password
+// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+AT91C_WDTC_WDV            EQU (0xFFF <<  0) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDFIEN         EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable
+AT91C_WDTC_WDRSTEN        EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable
+AT91C_WDTC_WDRPROC        EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart
+AT91C_WDTC_WDDIS          EQU (0x1 << 15) ;- (WDTC) Watchdog Disable
+AT91C_WDTC_WDD            EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value
+AT91C_WDTC_WDDBGHLT       EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt
+AT91C_WDTC_WDIDLEHLT      EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt
+// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+AT91C_WDTC_WDUNF          EQU (0x1 <<  0) ;- (WDTC) Watchdog Underflow
+AT91C_WDTC_WDERR          EQU (0x1 <<  1) ;- (WDTC) Watchdog Error
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// - *****************************************************************************
+// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+AT91C_VREG_PSTDBY         EQU (0x1 <<  0) ;- (VREG) Voltage Regulator Power Standby Mode
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// - *****************************************************************************
+// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+AT91C_MC_RCB              EQU (0x1 <<  0) ;- (MC) Remap Command Bit
+// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+AT91C_MC_UNDADD           EQU (0x1 <<  0) ;- (MC) Undefined Addess Abort Status
+AT91C_MC_MISADD           EQU (0x1 <<  1) ;- (MC) Misaligned Addess Abort Status
+AT91C_MC_ABTSZ            EQU (0x3 <<  8) ;- (MC) Abort Size Status
+AT91C_MC_ABTSZ_BYTE       EQU (0x0 <<  8) ;- (MC) Byte
+AT91C_MC_ABTSZ_HWORD      EQU (0x1 <<  8) ;- (MC) Half-word
+AT91C_MC_ABTSZ_WORD       EQU (0x2 <<  8) ;- (MC) Word
+AT91C_MC_ABTTYP           EQU (0x3 << 10) ;- (MC) Abort Type Status
+AT91C_MC_ABTTYP_DATAR     EQU (0x0 << 10) ;- (MC) Data Read
+AT91C_MC_ABTTYP_DATAW     EQU (0x1 << 10) ;- (MC) Data Write
+AT91C_MC_ABTTYP_FETCH     EQU (0x2 << 10) ;- (MC) Code Fetch
+AT91C_MC_MST0             EQU (0x1 << 16) ;- (MC) Master 0 Abort Source
+AT91C_MC_MST1             EQU (0x1 << 17) ;- (MC) Master 1 Abort Source
+AT91C_MC_SVMST0           EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source
+AT91C_MC_SVMST1           EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source
+// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+AT91C_MC_FRDY             EQU (0x1 <<  0) ;- (MC) Flash Ready
+AT91C_MC_LOCKE            EQU (0x1 <<  2) ;- (MC) Lock Error
+AT91C_MC_PROGE            EQU (0x1 <<  3) ;- (MC) Programming Error
+AT91C_MC_NEBP             EQU (0x1 <<  7) ;- (MC) No Erase Before Programming
+AT91C_MC_FWS              EQU (0x3 <<  8) ;- (MC) Flash Wait State
+AT91C_MC_FWS_0FWS         EQU (0x0 <<  8) ;- (MC) 1 cycle for Read, 2 for Write operations
+AT91C_MC_FWS_1FWS         EQU (0x1 <<  8) ;- (MC) 2 cycles for Read, 3 for Write operations
+AT91C_MC_FWS_2FWS         EQU (0x2 <<  8) ;- (MC) 3 cycles for Read, 4 for Write operations
+AT91C_MC_FWS_3FWS         EQU (0x3 <<  8) ;- (MC) 4 cycles for Read, 4 for Write operations
+AT91C_MC_FMCN             EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number
+// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+AT91C_MC_FCMD             EQU (0xF <<  0) ;- (MC) Flash Command
+AT91C_MC_FCMD_START_PROG  EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
+AT91C_MC_FCMD_LOCK        EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
+AT91C_MC_FCMD_UNLOCK      EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+AT91C_MC_FCMD_ERASE_ALL   EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+AT91C_MC_FCMD_SET_GP_NVM  EQU (0xB) ;- (MC) Set General Purpose NVM bits.
+AT91C_MC_FCMD_CLR_GP_NVM  EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
+AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
+AT91C_MC_PAGEN            EQU (0x3FF <<  8) ;- (MC) Page Number
+AT91C_MC_KEY              EQU (0xFF << 24) ;- (MC) Writing Protect Key
+// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+AT91C_MC_SECURITY         EQU (0x1 <<  4) ;- (MC) Security Bit Status
+AT91C_MC_GPNVM0           EQU (0x1 <<  8) ;- (MC) Sector 0 Lock Status
+AT91C_MC_GPNVM1           EQU (0x1 <<  9) ;- (MC) Sector 1 Lock Status
+AT91C_MC_GPNVM2           EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status
+AT91C_MC_GPNVM3           EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status
+AT91C_MC_GPNVM4           EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status
+AT91C_MC_GPNVM5           EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status
+AT91C_MC_GPNVM6           EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status
+AT91C_MC_GPNVM7           EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS0           EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status
+AT91C_MC_LOCKS1           EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status
+AT91C_MC_LOCKS2           EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status
+AT91C_MC_LOCKS3           EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status
+AT91C_MC_LOCKS4           EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status
+AT91C_MC_LOCKS5           EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status
+AT91C_MC_LOCKS6           EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status
+AT91C_MC_LOCKS7           EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status
+AT91C_MC_LOCKS8           EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status
+AT91C_MC_LOCKS9           EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status
+AT91C_MC_LOCKS10          EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status
+AT91C_MC_LOCKS11          EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status
+AT91C_MC_LOCKS12          EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status
+AT91C_MC_LOCKS13          EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status
+AT91C_MC_LOCKS14          EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status
+AT91C_MC_LOCKS15          EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// - *****************************************************************************
+// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+AT91C_SPI_SPIEN           EQU (0x1 <<  0) ;- (SPI) SPI Enable
+AT91C_SPI_SPIDIS          EQU (0x1 <<  1) ;- (SPI) SPI Disable
+AT91C_SPI_SWRST           EQU (0x1 <<  7) ;- (SPI) SPI Software reset
+AT91C_SPI_LASTXFER        EQU (0x1 << 24) ;- (SPI) SPI Last Transfer
+// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+AT91C_SPI_MSTR            EQU (0x1 <<  0) ;- (SPI) Master/Slave Mode
+AT91C_SPI_PS              EQU (0x1 <<  1) ;- (SPI) Peripheral Select
+AT91C_SPI_PS_FIXED        EQU (0x0 <<  1) ;- (SPI) Fixed Peripheral Select
+AT91C_SPI_PS_VARIABLE     EQU (0x1 <<  1) ;- (SPI) Variable Peripheral Select
+AT91C_SPI_PCSDEC          EQU (0x1 <<  2) ;- (SPI) Chip Select Decode
+AT91C_SPI_FDIV            EQU (0x1 <<  3) ;- (SPI) Clock Selection
+AT91C_SPI_MODFDIS         EQU (0x1 <<  4) ;- (SPI) Mode Fault Detection
+AT91C_SPI_LLB             EQU (0x1 <<  7) ;- (SPI) Clock Selection
+AT91C_SPI_PCS             EQU (0xF << 16) ;- (SPI) Peripheral Chip Select
+AT91C_SPI_DLYBCS          EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects
+// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+AT91C_SPI_RD              EQU (0xFFFF <<  0) ;- (SPI) Receive Data
+AT91C_SPI_RPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+AT91C_SPI_TD              EQU (0xFFFF <<  0) ;- (SPI) Transmit Data
+AT91C_SPI_TPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
+// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+AT91C_SPI_RDRF            EQU (0x1 <<  0) ;- (SPI) Receive Data Register Full
+AT91C_SPI_TDRE            EQU (0x1 <<  1) ;- (SPI) Transmit Data Register Empty
+AT91C_SPI_MODF            EQU (0x1 <<  2) ;- (SPI) Mode Fault Error
+AT91C_SPI_OVRES           EQU (0x1 <<  3) ;- (SPI) Overrun Error Status
+AT91C_SPI_ENDRX           EQU (0x1 <<  4) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_ENDTX           EQU (0x1 <<  5) ;- (SPI) End of Receiver Transfer
+AT91C_SPI_RXBUFF          EQU (0x1 <<  6) ;- (SPI) RXBUFF Interrupt
+AT91C_SPI_TXBUFE          EQU (0x1 <<  7) ;- (SPI) TXBUFE Interrupt
+AT91C_SPI_NSSR            EQU (0x1 <<  8) ;- (SPI) NSSR Interrupt
+AT91C_SPI_TXEMPTY         EQU (0x1 <<  9) ;- (SPI) TXEMPTY Interrupt
+AT91C_SPI_SPIENS          EQU (0x1 << 16) ;- (SPI) Enable Status
+// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+AT91C_SPI_CPOL            EQU (0x1 <<  0) ;- (SPI) Clock Polarity
+AT91C_SPI_NCPHA           EQU (0x1 <<  1) ;- (SPI) Clock Phase
+AT91C_SPI_CSAAT           EQU (0x1 <<  3) ;- (SPI) Chip Select Active After Transfer
+AT91C_SPI_BITS            EQU (0xF <<  4) ;- (SPI) Bits Per Transfer
+AT91C_SPI_BITS_8          EQU (0x0 <<  4) ;- (SPI) 8 Bits Per transfer
+AT91C_SPI_BITS_9          EQU (0x1 <<  4) ;- (SPI) 9 Bits Per transfer
+AT91C_SPI_BITS_10         EQU (0x2 <<  4) ;- (SPI) 10 Bits Per transfer
+AT91C_SPI_BITS_11         EQU (0x3 <<  4) ;- (SPI) 11 Bits Per transfer
+AT91C_SPI_BITS_12         EQU (0x4 <<  4) ;- (SPI) 12 Bits Per transfer
+AT91C_SPI_BITS_13         EQU (0x5 <<  4) ;- (SPI) 13 Bits Per transfer
+AT91C_SPI_BITS_14         EQU (0x6 <<  4) ;- (SPI) 14 Bits Per transfer
+AT91C_SPI_BITS_15         EQU (0x7 <<  4) ;- (SPI) 15 Bits Per transfer
+AT91C_SPI_BITS_16         EQU (0x8 <<  4) ;- (SPI) 16 Bits Per transfer
+AT91C_SPI_SCBR            EQU (0xFF <<  8) ;- (SPI) Serial Clock Baud Rate
+AT91C_SPI_DLYBS           EQU (0xFF << 16) ;- (SPI) Delay Before SPCK
+AT91C_SPI_DLYBCT          EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Usart
+// - *****************************************************************************
+// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+AT91C_US_STTBRK           EQU (0x1 <<  9) ;- (USART) Start Break
+AT91C_US_STPBRK           EQU (0x1 << 10) ;- (USART) Stop Break
+AT91C_US_STTTO            EQU (0x1 << 11) ;- (USART) Start Time-out
+AT91C_US_SENDA            EQU (0x1 << 12) ;- (USART) Send Address
+AT91C_US_RSTIT            EQU (0x1 << 13) ;- (USART) Reset Iterations
+AT91C_US_RSTNACK          EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge
+AT91C_US_RETTO            EQU (0x1 << 15) ;- (USART) Rearm Time-out
+AT91C_US_DTREN            EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable
+AT91C_US_DTRDIS           EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable
+AT91C_US_RTSEN            EQU (0x1 << 18) ;- (USART) Request to Send enable
+AT91C_US_RTSDIS           EQU (0x1 << 19) ;- (USART) Request to Send Disable
+// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+AT91C_US_USMODE           EQU (0xF <<  0) ;- (USART) Usart mode
+AT91C_US_USMODE_NORMAL    EQU (0x0) ;- (USART) Normal
+AT91C_US_USMODE_RS485     EQU (0x1) ;- (USART) RS485
+AT91C_US_USMODE_HWHSH     EQU (0x2) ;- (USART) Hardware Handshaking
+AT91C_US_USMODE_MODEM     EQU (0x3) ;- (USART) Modem
+AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
+AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
+AT91C_US_USMODE_IRDA      EQU (0x8) ;- (USART) IrDA
+AT91C_US_USMODE_SWHSH     EQU (0xC) ;- (USART) Software Handshaking
+AT91C_US_CLKS             EQU (0x3 <<  4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CLKS_CLOCK       EQU (0x0 <<  4) ;- (USART) Clock
+AT91C_US_CLKS_FDIV1       EQU (0x1 <<  4) ;- (USART) fdiv1
+AT91C_US_CLKS_SLOW        EQU (0x2 <<  4) ;- (USART) slow_clock (ARM)
+AT91C_US_CLKS_EXT         EQU (0x3 <<  4) ;- (USART) External (SCK)
+AT91C_US_CHRL             EQU (0x3 <<  6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
+AT91C_US_CHRL_5_BITS      EQU (0x0 <<  6) ;- (USART) Character Length: 5 bits
+AT91C_US_CHRL_6_BITS      EQU (0x1 <<  6) ;- (USART) Character Length: 6 bits
+AT91C_US_CHRL_7_BITS      EQU (0x2 <<  6) ;- (USART) Character Length: 7 bits
+AT91C_US_CHRL_8_BITS      EQU (0x3 <<  6) ;- (USART) Character Length: 8 bits
+AT91C_US_SYNC             EQU (0x1 <<  8) ;- (USART) Synchronous Mode Select
+AT91C_US_NBSTOP           EQU (0x3 << 12) ;- (USART) Number of Stop bits
+AT91C_US_NBSTOP_1_BIT     EQU (0x0 << 12) ;- (USART) 1 stop bit
+AT91C_US_NBSTOP_15_BIT    EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+AT91C_US_NBSTOP_2_BIT     EQU (0x2 << 12) ;- (USART) 2 stop bits
+AT91C_US_MSBF             EQU (0x1 << 16) ;- (USART) Bit Order
+AT91C_US_MODE9            EQU (0x1 << 17) ;- (USART) 9-bit Character length
+AT91C_US_CKLO             EQU (0x1 << 18) ;- (USART) Clock Output Select
+AT91C_US_OVER             EQU (0x1 << 19) ;- (USART) Over Sampling Mode
+AT91C_US_INACK            EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge
+AT91C_US_DSNACK           EQU (0x1 << 21) ;- (USART) Disable Successive NACK
+AT91C_US_MAX_ITER         EQU (0x1 << 24) ;- (USART) Number of Repetitions
+AT91C_US_FILTER           EQU (0x1 << 28) ;- (USART) Receive Line Filter
+// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+AT91C_US_RXBRK            EQU (0x1 <<  2) ;- (USART) Break Received/End of Break
+AT91C_US_TIMEOUT          EQU (0x1 <<  8) ;- (USART) Receiver Time-out
+AT91C_US_ITERATION        EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached
+AT91C_US_NACK             EQU (0x1 << 13) ;- (USART) Non Acknowledge
+AT91C_US_RIIC             EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag
+AT91C_US_DSRIC            EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag
+AT91C_US_DCDIC            EQU (0x1 << 18) ;- (USART) Data Carrier Flag
+AT91C_US_CTSIC            EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag
+// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+AT91C_US_RI               EQU (0x1 << 20) ;- (USART) Image of RI Input
+AT91C_US_DSR              EQU (0x1 << 21) ;- (USART) Image of DSR Input
+AT91C_US_DCD              EQU (0x1 << 22) ;- (USART) Image of DCD Input
+AT91C_US_CTS              EQU (0x1 << 23) ;- (USART) Image of CTS Input
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// - *****************************************************************************
+// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+AT91C_SSC_RXEN            EQU (0x1 <<  0) ;- (SSC) Receive Enable
+AT91C_SSC_RXDIS           EQU (0x1 <<  1) ;- (SSC) Receive Disable
+AT91C_SSC_TXEN            EQU (0x1 <<  8) ;- (SSC) Transmit Enable
+AT91C_SSC_TXDIS           EQU (0x1 <<  9) ;- (SSC) Transmit Disable
+AT91C_SSC_SWRST           EQU (0x1 << 15) ;- (SSC) Software Reset
+// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+AT91C_SSC_CKS             EQU (0x3 <<  0) ;- (SSC) Receive/Transmit Clock Selection
+AT91C_SSC_CKS_DIV         EQU (0x0) ;- (SSC) Divided Clock
+AT91C_SSC_CKS_TK          EQU (0x1) ;- (SSC) TK Clock signal
+AT91C_SSC_CKS_RK          EQU (0x2) ;- (SSC) RK pin
+AT91C_SSC_CKO             EQU (0x7 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
+AT91C_SSC_CKO_NONE        EQU (0x0 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+AT91C_SSC_CKO_CONTINOUS   EQU (0x1 <<  2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
+AT91C_SSC_CKO_DATA_TX     EQU (0x2 <<  2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+AT91C_SSC_CKI             EQU (0x1 <<  5) ;- (SSC) Receive/Transmit Clock Inversion
+AT91C_SSC_START           EQU (0xF <<  8) ;- (SSC) Receive/Transmit Start Selection
+AT91C_SSC_START_CONTINOUS EQU (0x0 <<  8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+AT91C_SSC_START_TX        EQU (0x1 <<  8) ;- (SSC) Transmit/Receive start
+AT91C_SSC_START_LOW_RF    EQU (0x2 <<  8) ;- (SSC) Detection of a low level on RF input
+AT91C_SSC_START_HIGH_RF   EQU (0x3 <<  8) ;- (SSC) Detection of a high level on RF input
+AT91C_SSC_START_FALL_RF   EQU (0x4 <<  8) ;- (SSC) Detection of a falling edge on RF input
+AT91C_SSC_START_RISE_RF   EQU (0x5 <<  8) ;- (SSC) Detection of a rising edge on RF input
+AT91C_SSC_START_LEVEL_RF  EQU (0x6 <<  8) ;- (SSC) Detection of any level change on RF input
+AT91C_SSC_START_EDGE_RF   EQU (0x7 <<  8) ;- (SSC) Detection of any edge on RF input
+AT91C_SSC_START_0         EQU (0x8 <<  8) ;- (SSC) Compare 0
+AT91C_SSC_STTDLY          EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay
+AT91C_SSC_PERIOD          EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection
+// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+AT91C_SSC_DATLEN          EQU (0x1F <<  0) ;- (SSC) Data Length
+AT91C_SSC_LOOP            EQU (0x1 <<  5) ;- (SSC) Loop Mode
+AT91C_SSC_MSBF            EQU (0x1 <<  7) ;- (SSC) Most Significant Bit First
+AT91C_SSC_DATNB           EQU (0xF <<  8) ;- (SSC) Data Number per Frame
+AT91C_SSC_FSLEN           EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length
+AT91C_SSC_FSOS            EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
+AT91C_SSC_FSOS_NONE       EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+AT91C_SSC_FSOS_NEGATIVE   EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+AT91C_SSC_FSOS_POSITIVE   EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+AT91C_SSC_FSOS_LOW        EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+AT91C_SSC_FSOS_HIGH       EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+AT91C_SSC_FSOS_TOGGLE     EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+AT91C_SSC_FSEDGE          EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection
+// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+AT91C_SSC_DATDEF          EQU (0x1 <<  5) ;- (SSC) Data Default Value
+AT91C_SSC_FSDEN           EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable
+// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+AT91C_SSC_TXRDY           EQU (0x1 <<  0) ;- (SSC) Transmit Ready
+AT91C_SSC_TXEMPTY         EQU (0x1 <<  1) ;- (SSC) Transmit Empty
+AT91C_SSC_ENDTX           EQU (0x1 <<  2) ;- (SSC) End Of Transmission
+AT91C_SSC_TXBUFE          EQU (0x1 <<  3) ;- (SSC) Transmit Buffer Empty
+AT91C_SSC_RXRDY           EQU (0x1 <<  4) ;- (SSC) Receive Ready
+AT91C_SSC_OVRUN           EQU (0x1 <<  5) ;- (SSC) Receive Overrun
+AT91C_SSC_ENDRX           EQU (0x1 <<  6) ;- (SSC) End of Reception
+AT91C_SSC_RXBUFF          EQU (0x1 <<  7) ;- (SSC) Receive Buffer Full
+AT91C_SSC_TXSYN           EQU (0x1 << 10) ;- (SSC) Transmit Sync
+AT91C_SSC_RXSYN           EQU (0x1 << 11) ;- (SSC) Receive Sync
+AT91C_SSC_TXENA           EQU (0x1 << 16) ;- (SSC) Transmit Enable
+AT91C_SSC_RXENA           EQU (0x1 << 17) ;- (SSC) Receive Enable
+// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// - *****************************************************************************
+// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+AT91C_TWI_START           EQU (0x1 <<  0) ;- (TWI) Send a START Condition
+AT91C_TWI_STOP            EQU (0x1 <<  1) ;- (TWI) Send a STOP Condition
+AT91C_TWI_MSEN            EQU (0x1 <<  2) ;- (TWI) TWI Master Transfer Enabled
+AT91C_TWI_MSDIS           EQU (0x1 <<  3) ;- (TWI) TWI Master Transfer Disabled
+AT91C_TWI_SWRST           EQU (0x1 <<  7) ;- (TWI) Software Reset
+// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+AT91C_TWI_IADRSZ          EQU (0x3 <<  8) ;- (TWI) Internal Device Address Size
+AT91C_TWI_IADRSZ_NO       EQU (0x0 <<  8) ;- (TWI) No internal device address
+AT91C_TWI_IADRSZ_1_BYTE   EQU (0x1 <<  8) ;- (TWI) One-byte internal device address
+AT91C_TWI_IADRSZ_2_BYTE   EQU (0x2 <<  8) ;- (TWI) Two-byte internal device address
+AT91C_TWI_IADRSZ_3_BYTE   EQU (0x3 <<  8) ;- (TWI) Three-byte internal device address
+AT91C_TWI_MREAD           EQU (0x1 << 12) ;- (TWI) Master Read Direction
+AT91C_TWI_DADR            EQU (0x7F << 16) ;- (TWI) Device Address
+// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+AT91C_TWI_CLDIV           EQU (0xFF <<  0) ;- (TWI) Clock Low Divider
+AT91C_TWI_CHDIV           EQU (0xFF <<  8) ;- (TWI) Clock High Divider
+AT91C_TWI_CKDIV           EQU (0x7 << 16) ;- (TWI) Clock Divider
+// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+AT91C_TWI_TXCOMP          EQU (0x1 <<  0) ;- (TWI) Transmission Completed
+AT91C_TWI_RXRDY           EQU (0x1 <<  1) ;- (TWI) Receive holding register ReaDY
+AT91C_TWI_TXRDY           EQU (0x1 <<  2) ;- (TWI) Transmit holding register ReaDY
+AT91C_TWI_OVRE            EQU (0x1 <<  6) ;- (TWI) Overrun Error
+AT91C_TWI_UNRE            EQU (0x1 <<  7) ;- (TWI) Underrun Error
+AT91C_TWI_NACK            EQU (0x1 <<  8) ;- (TWI) Not Acknowledged
+// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// - *****************************************************************************
+// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+AT91C_PWMC_CPRE           EQU (0xF <<  0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+AT91C_PWMC_CPRE_MCK       EQU (0x0) ;- (PWMC_CH) 
+AT91C_PWMC_CPRE_MCKA      EQU (0xB) ;- (PWMC_CH) 
+AT91C_PWMC_CPRE_MCKB      EQU (0xC) ;- (PWMC_CH) 
+AT91C_PWMC_CALG           EQU (0x1 <<  8) ;- (PWMC_CH) Channel Alignment
+AT91C_PWMC_CPOL           EQU (0x1 <<  9) ;- (PWMC_CH) Channel Polarity
+AT91C_PWMC_CPD            EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period
+// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+AT91C_PWMC_CDTY           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Duty Cycle
+// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+AT91C_PWMC_CPRD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Period
+// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+AT91C_PWMC_CCNT           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Counter
+// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+AT91C_PWMC_CUPD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Update
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// - *****************************************************************************
+// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+AT91C_PWMC_DIVA           EQU (0xFF <<  0) ;- (PWMC) CLKA divide factor.
+AT91C_PWMC_PREA           EQU (0xF <<  8) ;- (PWMC) Divider Input Clock Prescaler A
+AT91C_PWMC_PREA_MCK       EQU (0x0 <<  8) ;- (PWMC) 
+AT91C_PWMC_DIVB           EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.
+AT91C_PWMC_PREB           EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B
+AT91C_PWMC_PREB_MCK       EQU (0x0 << 24) ;- (PWMC) 
+// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+AT91C_PWMC_CHID0          EQU (0x1 <<  0) ;- (PWMC) Channel ID 0
+AT91C_PWMC_CHID1          EQU (0x1 <<  1) ;- (PWMC) Channel ID 1
+AT91C_PWMC_CHID2          EQU (0x1 <<  2) ;- (PWMC) Channel ID 2
+AT91C_PWMC_CHID3          EQU (0x1 <<  3) ;- (PWMC) Channel ID 3
+// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR USB Device Interface
+// - *****************************************************************************
+// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+AT91C_UDP_FRM_NUM         EQU (0x7FF <<  0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
+AT91C_UDP_FRM_ERR         EQU (0x1 << 16) ;- (UDP) Frame Error
+AT91C_UDP_FRM_OK          EQU (0x1 << 17) ;- (UDP) Frame OK
+// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+AT91C_UDP_FADDEN          EQU (0x1 <<  0) ;- (UDP) Function Address Enable
+AT91C_UDP_CONFG           EQU (0x1 <<  1) ;- (UDP) Configured
+AT91C_UDP_ESR             EQU (0x1 <<  2) ;- (UDP) Enable Send Resume
+AT91C_UDP_RSMINPR         EQU (0x1 <<  3) ;- (UDP) A Resume Has Been Sent to the Host
+AT91C_UDP_RMWUPE          EQU (0x1 <<  4) ;- (UDP) Remote Wake Up Enable
+// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+AT91C_UDP_FADD            EQU (0xFF <<  0) ;- (UDP) Function Address Value
+AT91C_UDP_FEN             EQU (0x1 <<  8) ;- (UDP) Function Enable
+// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+AT91C_UDP_EPINT0          EQU (0x1 <<  0) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT1          EQU (0x1 <<  1) ;- (UDP) Endpoint 0 Interrupt
+AT91C_UDP_EPINT2          EQU (0x1 <<  2) ;- (UDP) Endpoint 2 Interrupt
+AT91C_UDP_EPINT3          EQU (0x1 <<  3) ;- (UDP) Endpoint 3 Interrupt
+AT91C_UDP_EPINT4          EQU (0x1 <<  4) ;- (UDP) Endpoint 4 Interrupt
+AT91C_UDP_EPINT5          EQU (0x1 <<  5) ;- (UDP) Endpoint 5 Interrupt
+AT91C_UDP_RXSUSP          EQU (0x1 <<  8) ;- (UDP) USB Suspend Interrupt
+AT91C_UDP_RXRSM           EQU (0x1 <<  9) ;- (UDP) USB Resume Interrupt
+AT91C_UDP_EXTRSM          EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt
+AT91C_UDP_SOFINT          EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt
+AT91C_UDP_WAKEUP          EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt
+// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+AT91C_UDP_ENDBUSRES       EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt
+// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+AT91C_UDP_EP0             EQU (0x1 <<  0) ;- (UDP) Reset Endpoint 0
+AT91C_UDP_EP1             EQU (0x1 <<  1) ;- (UDP) Reset Endpoint 1
+AT91C_UDP_EP2             EQU (0x1 <<  2) ;- (UDP) Reset Endpoint 2
+AT91C_UDP_EP3             EQU (0x1 <<  3) ;- (UDP) Reset Endpoint 3
+AT91C_UDP_EP4             EQU (0x1 <<  4) ;- (UDP) Reset Endpoint 4
+AT91C_UDP_EP5             EQU (0x1 <<  5) ;- (UDP) Reset Endpoint 5
+// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+AT91C_UDP_TXCOMP          EQU (0x1 <<  0) ;- (UDP) Generates an IN packet with data previously written in the DPR
+AT91C_UDP_RX_DATA_BK0     EQU (0x1 <<  1) ;- (UDP) Receive Data Bank 0
+AT91C_UDP_RXSETUP         EQU (0x1 <<  2) ;- (UDP) Sends STALL to the Host (Control endpoints)
+AT91C_UDP_ISOERROR        EQU (0x1 <<  3) ;- (UDP) Isochronous error (Isochronous endpoints)
+AT91C_UDP_TXPKTRDY        EQU (0x1 <<  4) ;- (UDP) Transmit Packet Ready
+AT91C_UDP_FORCESTALL      EQU (0x1 <<  5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+AT91C_UDP_RX_DATA_BK1     EQU (0x1 <<  6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+AT91C_UDP_DIR             EQU (0x1 <<  7) ;- (UDP) Transfer Direction
+AT91C_UDP_EPTYPE          EQU (0x7 <<  8) ;- (UDP) Endpoint type
+AT91C_UDP_EPTYPE_CTRL     EQU (0x0 <<  8) ;- (UDP) Control
+AT91C_UDP_EPTYPE_ISO_OUT  EQU (0x1 <<  8) ;- (UDP) Isochronous OUT
+AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 <<  8) ;- (UDP) Bulk OUT
+AT91C_UDP_EPTYPE_INT_OUT  EQU (0x3 <<  8) ;- (UDP) Interrupt OUT
+AT91C_UDP_EPTYPE_ISO_IN   EQU (0x5 <<  8) ;- (UDP) Isochronous IN
+AT91C_UDP_EPTYPE_BULK_IN  EQU (0x6 <<  8) ;- (UDP) Bulk IN
+AT91C_UDP_EPTYPE_INT_IN   EQU (0x7 <<  8) ;- (UDP) Interrupt IN
+AT91C_UDP_DTGLE           EQU (0x1 << 11) ;- (UDP) Data Toggle
+AT91C_UDP_EPEDS           EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable
+AT91C_UDP_RXBYTECNT       EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO
+// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+AT91C_UDP_TXVDIS          EQU (0x1 <<  8) ;- (UDP) 
+AT91C_UDP_PUON            EQU (0x1 <<  9) ;- (UDP) Pull-up ON
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// - *****************************************************************************
+// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+AT91C_TC_CLKEN            EQU (0x1 <<  0) ;- (TC) Counter Clock Enable Command
+AT91C_TC_CLKDIS           EQU (0x1 <<  1) ;- (TC) Counter Clock Disable Command
+AT91C_TC_SWTRG            EQU (0x1 <<  2) ;- (TC) Software Trigger Command
+// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+AT91C_TC_CLKS             EQU (0x7 <<  0) ;- (TC) Clock Selection
+AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
+AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
+AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
+AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
+AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
+AT91C_TC_CLKS_XC0         EQU (0x5) ;- (TC) Clock selected: XC0
+AT91C_TC_CLKS_XC1         EQU (0x6) ;- (TC) Clock selected: XC1
+AT91C_TC_CLKS_XC2         EQU (0x7) ;- (TC) Clock selected: XC2
+AT91C_TC_CLKI             EQU (0x1 <<  3) ;- (TC) Clock Invert
+AT91C_TC_BURST            EQU (0x3 <<  4) ;- (TC) Burst Signal Selection
+AT91C_TC_BURST_NONE       EQU (0x0 <<  4) ;- (TC) The clock is not gated by an external signal
+AT91C_TC_BURST_XC0        EQU (0x1 <<  4) ;- (TC) XC0 is ANDed with the selected clock
+AT91C_TC_BURST_XC1        EQU (0x2 <<  4) ;- (TC) XC1 is ANDed with the selected clock
+AT91C_TC_BURST_XC2        EQU (0x3 <<  4) ;- (TC) XC2 is ANDed with the selected clock
+AT91C_TC_CPCSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RC Compare
+AT91C_TC_LDBSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RB Loading
+AT91C_TC_CPCDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disable with RC Compare
+AT91C_TC_LDBDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disabled with RB Loading
+AT91C_TC_ETRGEDG          EQU (0x3 <<  8) ;- (TC) External Trigger Edge Selection
+AT91C_TC_ETRGEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
+AT91C_TC_ETRGEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
+AT91C_TC_ETRGEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
+AT91C_TC_ETRGEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
+AT91C_TC_EEVTEDG          EQU (0x3 <<  8) ;- (TC) External Event Edge Selection
+AT91C_TC_EEVTEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
+AT91C_TC_EEVTEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
+AT91C_TC_EEVTEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
+AT91C_TC_EEVTEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
+AT91C_TC_EEVT             EQU (0x3 << 10) ;- (TC) External Event  Selection
+AT91C_TC_EEVT_TIOB        EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
+AT91C_TC_EEVT_XC0         EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
+AT91C_TC_EEVT_XC1         EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
+AT91C_TC_EEVT_XC2         EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
+AT91C_TC_ABETRG           EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection
+AT91C_TC_ENETRG           EQU (0x1 << 12) ;- (TC) External Event Trigger enable
+AT91C_TC_WAVESEL          EQU (0x3 << 13) ;- (TC) Waveform  Selection
+AT91C_TC_WAVESEL_UP       EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN   EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UP_AUTO  EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare
+AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
+AT91C_TC_CPCTRG           EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable
+AT91C_TC_WAVE             EQU (0x1 << 15) ;- (TC) 
+AT91C_TC_ACPA             EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA
+AT91C_TC_ACPA_NONE        EQU (0x0 << 16) ;- (TC) Effect: none
+AT91C_TC_ACPA_SET         EQU (0x1 << 16) ;- (TC) Effect: set
+AT91C_TC_ACPA_CLEAR       EQU (0x2 << 16) ;- (TC) Effect: clear
+AT91C_TC_ACPA_TOGGLE      EQU (0x3 << 16) ;- (TC) Effect: toggle
+AT91C_TC_LDRA             EQU (0x3 << 16) ;- (TC) RA Loading Selection
+AT91C_TC_LDRA_NONE        EQU (0x0 << 16) ;- (TC) Edge: None
+AT91C_TC_LDRA_RISING      EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRA_FALLING     EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRA_BOTH        EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_ACPC             EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA
+AT91C_TC_ACPC_NONE        EQU (0x0 << 18) ;- (TC) Effect: none
+AT91C_TC_ACPC_SET         EQU (0x1 << 18) ;- (TC) Effect: set
+AT91C_TC_ACPC_CLEAR       EQU (0x2 << 18) ;- (TC) Effect: clear
+AT91C_TC_ACPC_TOGGLE      EQU (0x3 << 18) ;- (TC) Effect: toggle
+AT91C_TC_LDRB             EQU (0x3 << 18) ;- (TC) RB Loading Selection
+AT91C_TC_LDRB_NONE        EQU (0x0 << 18) ;- (TC) Edge: None
+AT91C_TC_LDRB_RISING      EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA
+AT91C_TC_LDRB_FALLING     EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA
+AT91C_TC_LDRB_BOTH        EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA
+AT91C_TC_AEEVT            EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA
+AT91C_TC_AEEVT_NONE       EQU (0x0 << 20) ;- (TC) Effect: none
+AT91C_TC_AEEVT_SET        EQU (0x1 << 20) ;- (TC) Effect: set
+AT91C_TC_AEEVT_CLEAR      EQU (0x2 << 20) ;- (TC) Effect: clear
+AT91C_TC_AEEVT_TOGGLE     EQU (0x3 << 20) ;- (TC) Effect: toggle
+AT91C_TC_ASWTRG           EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA
+AT91C_TC_ASWTRG_NONE      EQU (0x0 << 22) ;- (TC) Effect: none
+AT91C_TC_ASWTRG_SET       EQU (0x1 << 22) ;- (TC) Effect: set
+AT91C_TC_ASWTRG_CLEAR     EQU (0x2 << 22) ;- (TC) Effect: clear
+AT91C_TC_ASWTRG_TOGGLE    EQU (0x3 << 22) ;- (TC) Effect: toggle
+AT91C_TC_BCPB             EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB
+AT91C_TC_BCPB_NONE        EQU (0x0 << 24) ;- (TC) Effect: none
+AT91C_TC_BCPB_SET         EQU (0x1 << 24) ;- (TC) Effect: set
+AT91C_TC_BCPB_CLEAR       EQU (0x2 << 24) ;- (TC) Effect: clear
+AT91C_TC_BCPB_TOGGLE      EQU (0x3 << 24) ;- (TC) Effect: toggle
+AT91C_TC_BCPC             EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB
+AT91C_TC_BCPC_NONE        EQU (0x0 << 26) ;- (TC) Effect: none
+AT91C_TC_BCPC_SET         EQU (0x1 << 26) ;- (TC) Effect: set
+AT91C_TC_BCPC_CLEAR       EQU (0x2 << 26) ;- (TC) Effect: clear
+AT91C_TC_BCPC_TOGGLE      EQU (0x3 << 26) ;- (TC) Effect: toggle
+AT91C_TC_BEEVT            EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB
+AT91C_TC_BEEVT_NONE       EQU (0x0 << 28) ;- (TC) Effect: none
+AT91C_TC_BEEVT_SET        EQU (0x1 << 28) ;- (TC) Effect: set
+AT91C_TC_BEEVT_CLEAR      EQU (0x2 << 28) ;- (TC) Effect: clear
+AT91C_TC_BEEVT_TOGGLE     EQU (0x3 << 28) ;- (TC) Effect: toggle
+AT91C_TC_BSWTRG           EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB
+AT91C_TC_BSWTRG_NONE      EQU (0x0 << 30) ;- (TC) Effect: none
+AT91C_TC_BSWTRG_SET       EQU (0x1 << 30) ;- (TC) Effect: set
+AT91C_TC_BSWTRG_CLEAR     EQU (0x2 << 30) ;- (TC) Effect: clear
+AT91C_TC_BSWTRG_TOGGLE    EQU (0x3 << 30) ;- (TC) Effect: toggle
+// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+AT91C_TC_COVFS            EQU (0x1 <<  0) ;- (TC) Counter Overflow
+AT91C_TC_LOVRS            EQU (0x1 <<  1) ;- (TC) Load Overrun
+AT91C_TC_CPAS             EQU (0x1 <<  2) ;- (TC) RA Compare
+AT91C_TC_CPBS             EQU (0x1 <<  3) ;- (TC) RB Compare
+AT91C_TC_CPCS             EQU (0x1 <<  4) ;- (TC) RC Compare
+AT91C_TC_LDRAS            EQU (0x1 <<  5) ;- (TC) RA Loading
+AT91C_TC_LDRBS            EQU (0x1 <<  6) ;- (TC) RB Loading
+AT91C_TC_ETRGS            EQU (0x1 <<  7) ;- (TC) External Trigger
+AT91C_TC_CLKSTA           EQU (0x1 << 16) ;- (TC) Clock Enabling
+AT91C_TC_MTIOA            EQU (0x1 << 17) ;- (TC) TIOA Mirror
+AT91C_TC_MTIOB            EQU (0x1 << 18) ;- (TC) TIOA Mirror
+// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// - *****************************************************************************
+// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+AT91C_TCB_SYNC            EQU (0x1 <<  0) ;- (TCB) Synchro Command
+// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+AT91C_TCB_TC0XC0S         EQU (0x3 <<  0) ;- (TCB) External Clock Signal 0 Selection
+AT91C_TCB_TC0XC0S_TCLK0   EQU (0x0) ;- (TCB) TCLK0 connected to XC0
+AT91C_TCB_TC0XC0S_NONE    EQU (0x1) ;- (TCB) None signal connected to XC0
+AT91C_TCB_TC0XC0S_TIOA1   EQU (0x2) ;- (TCB) TIOA1 connected to XC0
+AT91C_TCB_TC0XC0S_TIOA2   EQU (0x3) ;- (TCB) TIOA2 connected to XC0
+AT91C_TCB_TC1XC1S         EQU (0x3 <<  2) ;- (TCB) External Clock Signal 1 Selection
+AT91C_TCB_TC1XC1S_TCLK1   EQU (0x0 <<  2) ;- (TCB) TCLK1 connected to XC1
+AT91C_TCB_TC1XC1S_NONE    EQU (0x1 <<  2) ;- (TCB) None signal connected to XC1
+AT91C_TCB_TC1XC1S_TIOA0   EQU (0x2 <<  2) ;- (TCB) TIOA0 connected to XC1
+AT91C_TCB_TC1XC1S_TIOA2   EQU (0x3 <<  2) ;- (TCB) TIOA2 connected to XC1
+AT91C_TCB_TC2XC2S         EQU (0x3 <<  4) ;- (TCB) External Clock Signal 2 Selection
+AT91C_TCB_TC2XC2S_TCLK2   EQU (0x0 <<  4) ;- (TCB) TCLK2 connected to XC2
+AT91C_TCB_TC2XC2S_NONE    EQU (0x1 <<  4) ;- (TCB) None signal connected to XC2
+AT91C_TCB_TC2XC2S_TIOA0   EQU (0x2 <<  4) ;- (TCB) TIOA0 connected to XC2
+AT91C_TCB_TC2XC2S_TIOA1   EQU (0x3 <<  4) ;- (TCB) TIOA2 connected to XC2
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// - *****************************************************************************
+// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+AT91C_CAN_MTIMEMARK       EQU (0xFFFF <<  0) ;- (CAN_MB) Mailbox Timemark
+AT91C_CAN_PRIOR           EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority
+AT91C_CAN_MOT             EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type
+AT91C_CAN_MOT_DIS         EQU (0x0 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_RX          EQU (0x1 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_TX          EQU (0x3 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_CONSUMER    EQU (0x4 << 24) ;- (CAN_MB) 
+AT91C_CAN_MOT_PRODUCER    EQU (0x5 << 24) ;- (CAN_MB) 
+// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+AT91C_CAN_MIDvB           EQU (0x3FFFF <<  0) ;- (CAN_MB) Complementary bits for identifier in extended mode
+AT91C_CAN_MIDvA           EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode
+AT91C_CAN_MIDE            EQU (0x1 << 29) ;- (CAN_MB) Identifier Version
+// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+AT91C_CAN_MTIMESTAMP      EQU (0xFFFF <<  0) ;- (CAN_MB) Timer Value
+AT91C_CAN_MDLC            EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code
+AT91C_CAN_MRTR            EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request
+AT91C_CAN_MABT            EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort
+AT91C_CAN_MRDY            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready
+AT91C_CAN_MMI             EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored
+// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+AT91C_CAN_MACR            EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox
+AT91C_CAN_MTCR            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// - *****************************************************************************
+// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+AT91C_CAN_CANEN           EQU (0x1 <<  0) ;- (CAN) CAN Controller Enable
+AT91C_CAN_LPM             EQU (0x1 <<  1) ;- (CAN) Disable/Enable Low Power Mode
+AT91C_CAN_ABM             EQU (0x1 <<  2) ;- (CAN) Disable/Enable Autobaud/Listen Mode
+AT91C_CAN_OVL             EQU (0x1 <<  3) ;- (CAN) Disable/Enable Overload Frame
+AT91C_CAN_TEOF            EQU (0x1 <<  4) ;- (CAN) Time Stamp messages at each end of Frame
+AT91C_CAN_TTM             EQU (0x1 <<  5) ;- (CAN) Disable/Enable Time Trigger Mode
+AT91C_CAN_TIMFRZ          EQU (0x1 <<  6) ;- (CAN) Enable Timer Freeze
+AT91C_CAN_DRPT            EQU (0x1 <<  7) ;- (CAN) Disable Repeat
+// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+AT91C_CAN_MB0             EQU (0x1 <<  0) ;- (CAN) Mailbox 0 Flag
+AT91C_CAN_MB1             EQU (0x1 <<  1) ;- (CAN) Mailbox 1 Flag
+AT91C_CAN_MB2             EQU (0x1 <<  2) ;- (CAN) Mailbox 2 Flag
+AT91C_CAN_MB3             EQU (0x1 <<  3) ;- (CAN) Mailbox 3 Flag
+AT91C_CAN_MB4             EQU (0x1 <<  4) ;- (CAN) Mailbox 4 Flag
+AT91C_CAN_MB5             EQU (0x1 <<  5) ;- (CAN) Mailbox 5 Flag
+AT91C_CAN_MB6             EQU (0x1 <<  6) ;- (CAN) Mailbox 6 Flag
+AT91C_CAN_MB7             EQU (0x1 <<  7) ;- (CAN) Mailbox 7 Flag
+AT91C_CAN_MB8             EQU (0x1 <<  8) ;- (CAN) Mailbox 8 Flag
+AT91C_CAN_MB9             EQU (0x1 <<  9) ;- (CAN) Mailbox 9 Flag
+AT91C_CAN_MB10            EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag
+AT91C_CAN_MB11            EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag
+AT91C_CAN_MB12            EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag
+AT91C_CAN_MB13            EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag
+AT91C_CAN_MB14            EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag
+AT91C_CAN_MB15            EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag
+AT91C_CAN_ERRA            EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag
+AT91C_CAN_WARN            EQU (0x1 << 17) ;- (CAN) Warning Limit Flag
+AT91C_CAN_ERRP            EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag
+AT91C_CAN_BOFF            EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag
+AT91C_CAN_SLEEP           EQU (0x1 << 20) ;- (CAN) Sleep Flag
+AT91C_CAN_WAKEUP          EQU (0x1 << 21) ;- (CAN) Wakeup Flag
+AT91C_CAN_TOVF            EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag
+AT91C_CAN_TSTP            EQU (0x1 << 23) ;- (CAN) Timestamp Flag
+AT91C_CAN_CERR            EQU (0x1 << 24) ;- (CAN) CRC Error
+AT91C_CAN_SERR            EQU (0x1 << 25) ;- (CAN) Stuffing Error
+AT91C_CAN_AERR            EQU (0x1 << 26) ;- (CAN) Acknowledgment Error
+AT91C_CAN_FERR            EQU (0x1 << 27) ;- (CAN) Form Error
+AT91C_CAN_BERR            EQU (0x1 << 28) ;- (CAN) Bit Error
+// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+AT91C_CAN_RBSY            EQU (0x1 << 29) ;- (CAN) Receiver Busy
+AT91C_CAN_TBSY            EQU (0x1 << 30) ;- (CAN) Transmitter Busy
+AT91C_CAN_OVLY            EQU (0x1 << 31) ;- (CAN) Overload Busy
+// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+AT91C_CAN_PHASE2          EQU (0x7 <<  0) ;- (CAN) Phase 2 segment
+AT91C_CAN_PHASE1          EQU (0x7 <<  4) ;- (CAN) Phase 1 segment
+AT91C_CAN_PROPAG          EQU (0x7 <<  8) ;- (CAN) Programmation time segment
+AT91C_CAN_SYNC            EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment
+AT91C_CAN_BRP             EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler
+AT91C_CAN_SMP             EQU (0x1 << 24) ;- (CAN) Sampling mode
+// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+AT91C_CAN_TIMER           EQU (0xFFFF <<  0) ;- (CAN) Timer field
+// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+AT91C_CAN_REC             EQU (0xFF <<  0) ;- (CAN) Receive Error Counter
+AT91C_CAN_TEC             EQU (0xFF << 16) ;- (CAN) Transmit Error Counter
+// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+AT91C_CAN_TIMRST          EQU (0x1 << 31) ;- (CAN) Timer Reset Field
+// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// - *****************************************************************************
+// - -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+AT91C_EMAC_LB             EQU (0x1 <<  0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+AT91C_EMAC_LLB            EQU (0x1 <<  1) ;- (EMAC) Loopback local. 
+AT91C_EMAC_RE             EQU (0x1 <<  2) ;- (EMAC) Receive enable. 
+AT91C_EMAC_TE             EQU (0x1 <<  3) ;- (EMAC) Transmit enable. 
+AT91C_EMAC_MPE            EQU (0x1 <<  4) ;- (EMAC) Management port enable. 
+AT91C_EMAC_CLRSTAT        EQU (0x1 <<  5) ;- (EMAC) Clear statistics registers. 
+AT91C_EMAC_INCSTAT        EQU (0x1 <<  6) ;- (EMAC) Increment statistics registers. 
+AT91C_EMAC_WESTAT         EQU (0x1 <<  7) ;- (EMAC) Write enable for statistics registers. 
+AT91C_EMAC_BP             EQU (0x1 <<  8) ;- (EMAC) Back pressure. 
+AT91C_EMAC_TSTART         EQU (0x1 <<  9) ;- (EMAC) Start Transmission. 
+AT91C_EMAC_THALT          EQU (0x1 << 10) ;- (EMAC) Transmission Halt. 
+AT91C_EMAC_TPFR           EQU (0x1 << 11) ;- (EMAC) Transmit pause frame 
+AT91C_EMAC_TZQ            EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame
+// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+AT91C_EMAC_SPD            EQU (0x1 <<  0) ;- (EMAC) Speed. 
+AT91C_EMAC_FD             EQU (0x1 <<  1) ;- (EMAC) Full duplex. 
+AT91C_EMAC_JFRAME         EQU (0x1 <<  3) ;- (EMAC) Jumbo Frames. 
+AT91C_EMAC_CAF            EQU (0x1 <<  4) ;- (EMAC) Copy all frames. 
+AT91C_EMAC_NBC            EQU (0x1 <<  5) ;- (EMAC) No broadcast. 
+AT91C_EMAC_MTI            EQU (0x1 <<  6) ;- (EMAC) Multicast hash event enable
+AT91C_EMAC_UNI            EQU (0x1 <<  7) ;- (EMAC) Unicast hash enable. 
+AT91C_EMAC_BIG            EQU (0x1 <<  8) ;- (EMAC) Receive 1522 bytes. 
+AT91C_EMAC_EAE            EQU (0x1 <<  9) ;- (EMAC) External address match enable. 
+AT91C_EMAC_CLK            EQU (0x3 << 10) ;- (EMAC) 
+AT91C_EMAC_CLK_HCLK_8     EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8
+AT91C_EMAC_CLK_HCLK_16    EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16
+AT91C_EMAC_CLK_HCLK_32    EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32
+AT91C_EMAC_CLK_HCLK_64    EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64
+AT91C_EMAC_RTY            EQU (0x1 << 12) ;- (EMAC) 
+AT91C_EMAC_PAE            EQU (0x1 << 13) ;- (EMAC) 
+AT91C_EMAC_RBOF           EQU (0x3 << 14) ;- (EMAC) 
+AT91C_EMAC_RBOF_OFFSET_0  EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_1  EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_2  EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer
+AT91C_EMAC_RBOF_OFFSET_3  EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer
+AT91C_EMAC_RLCE           EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable
+AT91C_EMAC_DRFCS          EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS
+AT91C_EMAC_EFRHD          EQU (0x1 << 18) ;- (EMAC) 
+AT91C_EMAC_IRXFCS         EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS
+// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+AT91C_EMAC_LINKR          EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_MDIO           EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_IDLE           EQU (0x1 <<  2) ;- (EMAC) 
+// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+AT91C_EMAC_UBR            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_COL            EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_RLES           EQU (0x1 <<  2) ;- (EMAC) 
+AT91C_EMAC_TGO            EQU (0x1 <<  3) ;- (EMAC) Transmit Go
+AT91C_EMAC_BEX            EQU (0x1 <<  4) ;- (EMAC) Buffers exhausted mid frame
+AT91C_EMAC_COMP           EQU (0x1 <<  5) ;- (EMAC) 
+AT91C_EMAC_UND            EQU (0x1 <<  6) ;- (EMAC) 
+// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+AT91C_EMAC_BNA            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_REC            EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_OVR            EQU (0x1 <<  2) ;- (EMAC) 
+// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+AT91C_EMAC_MFD            EQU (0x1 <<  0) ;- (EMAC) 
+AT91C_EMAC_RCOMP          EQU (0x1 <<  1) ;- (EMAC) 
+AT91C_EMAC_RXUBR          EQU (0x1 <<  2) ;- (EMAC) 
+AT91C_EMAC_TXUBR          EQU (0x1 <<  3) ;- (EMAC) 
+AT91C_EMAC_TUNDR          EQU (0x1 <<  4) ;- (EMAC) 
+AT91C_EMAC_RLEX           EQU (0x1 <<  5) ;- (EMAC) 
+AT91C_EMAC_TXERR          EQU (0x1 <<  6) ;- (EMAC) 
+AT91C_EMAC_TCOMP          EQU (0x1 <<  7) ;- (EMAC) 
+AT91C_EMAC_LINK           EQU (0x1 <<  9) ;- (EMAC) 
+AT91C_EMAC_ROVR           EQU (0x1 << 10) ;- (EMAC) 
+AT91C_EMAC_HRESP          EQU (0x1 << 11) ;- (EMAC) 
+AT91C_EMAC_PFRE           EQU (0x1 << 12) ;- (EMAC) 
+AT91C_EMAC_PTZ            EQU (0x1 << 13) ;- (EMAC) 
+// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+AT91C_EMAC_DATA           EQU (0xFFFF <<  0) ;- (EMAC) 
+AT91C_EMAC_CODE           EQU (0x3 << 16) ;- (EMAC) 
+AT91C_EMAC_REGA           EQU (0x1F << 18) ;- (EMAC) 
+AT91C_EMAC_PHYA           EQU (0x1F << 23) ;- (EMAC) 
+AT91C_EMAC_RW             EQU (0x3 << 28) ;- (EMAC) 
+AT91C_EMAC_SOF            EQU (0x3 << 30) ;- (EMAC) 
+// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+AT91C_EMAC_RMII           EQU (0x1 <<  0) ;- (EMAC) Reduce MII
+// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+AT91C_EMAC_IP             EQU (0xFFFF <<  0) ;- (EMAC) ARP request IP address
+AT91C_EMAC_MAG            EQU (0x1 << 16) ;- (EMAC) Magic packet event enable
+AT91C_EMAC_ARP            EQU (0x1 << 17) ;- (EMAC) ARP request event enable
+AT91C_EMAC_SA1            EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable
+// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+AT91C_EMAC_REVREF         EQU (0xFFFF <<  0) ;- (EMAC) 
+AT91C_EMAC_PARTREF        EQU (0xFFFF << 16) ;- (EMAC) 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// - *****************************************************************************
+// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+AT91C_ADC_SWRST           EQU (0x1 <<  0) ;- (ADC) Software Reset
+AT91C_ADC_START           EQU (0x1 <<  1) ;- (ADC) Start Conversion
+// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+AT91C_ADC_TRGEN           EQU (0x1 <<  0) ;- (ADC) Trigger Enable
+AT91C_ADC_TRGEN_DIS       EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+AT91C_ADC_TRGEN_EN        EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
+AT91C_ADC_TRGSEL          EQU (0x7 <<  1) ;- (ADC) Trigger Selection
+AT91C_ADC_TRGSEL_TIOA0    EQU (0x0 <<  1) ;- (ADC) Selected TRGSEL = TIAO0
+AT91C_ADC_TRGSEL_TIOA1    EQU (0x1 <<  1) ;- (ADC) Selected TRGSEL = TIAO1
+AT91C_ADC_TRGSEL_TIOA2    EQU (0x2 <<  1) ;- (ADC) Selected TRGSEL = TIAO2
+AT91C_ADC_TRGSEL_TIOA3    EQU (0x3 <<  1) ;- (ADC) Selected TRGSEL = TIAO3
+AT91C_ADC_TRGSEL_TIOA4    EQU (0x4 <<  1) ;- (ADC) Selected TRGSEL = TIAO4
+AT91C_ADC_TRGSEL_TIOA5    EQU (0x5 <<  1) ;- (ADC) Selected TRGSEL = TIAO5
+AT91C_ADC_TRGSEL_EXT      EQU (0x6 <<  1) ;- (ADC) Selected TRGSEL = External Trigger
+AT91C_ADC_LOWRES          EQU (0x1 <<  4) ;- (ADC) Resolution.
+AT91C_ADC_LOWRES_10_BIT   EQU (0x0 <<  4) ;- (ADC) 10-bit resolution
+AT91C_ADC_LOWRES_8_BIT    EQU (0x1 <<  4) ;- (ADC) 8-bit resolution
+AT91C_ADC_SLEEP           EQU (0x1 <<  5) ;- (ADC) Sleep Mode
+AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 <<  5) ;- (ADC) Normal Mode
+AT91C_ADC_SLEEP_MODE      EQU (0x1 <<  5) ;- (ADC) Sleep Mode
+AT91C_ADC_PRESCAL         EQU (0x3F <<  8) ;- (ADC) Prescaler rate selection
+AT91C_ADC_STARTUP         EQU (0x1F << 16) ;- (ADC) Startup Time
+AT91C_ADC_SHTIM           EQU (0xF << 24) ;- (ADC) Sample & Hold Time
+// - -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+AT91C_ADC_CH0             EQU (0x1 <<  0) ;- (ADC) Channel 0
+AT91C_ADC_CH1             EQU (0x1 <<  1) ;- (ADC) Channel 1
+AT91C_ADC_CH2             EQU (0x1 <<  2) ;- (ADC) Channel 2
+AT91C_ADC_CH3             EQU (0x1 <<  3) ;- (ADC) Channel 3
+AT91C_ADC_CH4             EQU (0x1 <<  4) ;- (ADC) Channel 4
+AT91C_ADC_CH5             EQU (0x1 <<  5) ;- (ADC) Channel 5
+AT91C_ADC_CH6             EQU (0x1 <<  6) ;- (ADC) Channel 6
+AT91C_ADC_CH7             EQU (0x1 <<  7) ;- (ADC) Channel 7
+// - -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// - -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+AT91C_ADC_EOC0            EQU (0x1 <<  0) ;- (ADC) End of Conversion
+AT91C_ADC_EOC1            EQU (0x1 <<  1) ;- (ADC) End of Conversion
+AT91C_ADC_EOC2            EQU (0x1 <<  2) ;- (ADC) End of Conversion
+AT91C_ADC_EOC3            EQU (0x1 <<  3) ;- (ADC) End of Conversion
+AT91C_ADC_EOC4            EQU (0x1 <<  4) ;- (ADC) End of Conversion
+AT91C_ADC_EOC5            EQU (0x1 <<  5) ;- (ADC) End of Conversion
+AT91C_ADC_EOC6            EQU (0x1 <<  6) ;- (ADC) End of Conversion
+AT91C_ADC_EOC7            EQU (0x1 <<  7) ;- (ADC) End of Conversion
+AT91C_ADC_OVRE0           EQU (0x1 <<  8) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE1           EQU (0x1 <<  9) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE2           EQU (0x1 << 10) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE3           EQU (0x1 << 11) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE4           EQU (0x1 << 12) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE5           EQU (0x1 << 13) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE6           EQU (0x1 << 14) ;- (ADC) Overrun Error
+AT91C_ADC_OVRE7           EQU (0x1 << 15) ;- (ADC) Overrun Error
+AT91C_ADC_DRDY            EQU (0x1 << 16) ;- (ADC) Data Ready
+AT91C_ADC_GOVRE           EQU (0x1 << 17) ;- (ADC) General Overrun
+AT91C_ADC_ENDRX           EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer
+AT91C_ADC_RXBUFF          EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt
+// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+AT91C_ADC_LDATA           EQU (0x3FF <<  0) ;- (ADC) Last Data Converted
+// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+AT91C_ADC_DATA            EQU (0x3FF <<  0) ;- (ADC) Converted Data
+// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// - *****************************************************************************
+// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+AT91C_AES_START           EQU (0x1 <<  0) ;- (AES) Starts Processing
+AT91C_AES_SWRST           EQU (0x1 <<  8) ;- (AES) Software Reset
+AT91C_AES_LOADSEED        EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading
+// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+AT91C_AES_CIPHER          EQU (0x1 <<  0) ;- (AES) Processing Mode
+AT91C_AES_PROCDLY         EQU (0xF <<  4) ;- (AES) Processing Delay
+AT91C_AES_SMOD            EQU (0x3 <<  8) ;- (AES) Start Mode
+AT91C_AES_SMOD_MANUAL     EQU (0x0 <<  8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+AT91C_AES_SMOD_AUTO       EQU (0x1 <<  8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+AT91C_AES_SMOD_PDC        EQU (0x2 <<  8) ;- (AES) PDC Mode (cf datasheet).
+AT91C_AES_OPMOD           EQU (0x7 << 12) ;- (AES) Operation Mode
+AT91C_AES_OPMOD_ECB       EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode.
+AT91C_AES_OPMOD_CBC       EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode.
+AT91C_AES_OPMOD_OFB       EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode.
+AT91C_AES_OPMOD_CFB       EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode.
+AT91C_AES_OPMOD_CTR       EQU (0x4 << 12) ;- (AES) CTR Counter mode.
+AT91C_AES_LOD             EQU (0x1 << 15) ;- (AES) Last Output Data Mode
+AT91C_AES_CFBS            EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size
+AT91C_AES_CFBS_128_BIT    EQU (0x0 << 16) ;- (AES) 128-bit.
+AT91C_AES_CFBS_64_BIT     EQU (0x1 << 16) ;- (AES) 64-bit.
+AT91C_AES_CFBS_32_BIT     EQU (0x2 << 16) ;- (AES) 32-bit.
+AT91C_AES_CFBS_16_BIT     EQU (0x3 << 16) ;- (AES) 16-bit.
+AT91C_AES_CFBS_8_BIT      EQU (0x4 << 16) ;- (AES) 8-bit.
+AT91C_AES_CKEY            EQU (0xF << 20) ;- (AES) Countermeasure Key
+AT91C_AES_CTYPE           EQU (0x1F << 24) ;- (AES) Countermeasure Type
+AT91C_AES_CTYPE_TYPE1_EN  EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled.
+AT91C_AES_CTYPE_TYPE2_EN  EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled.
+AT91C_AES_CTYPE_TYPE3_EN  EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled.
+AT91C_AES_CTYPE_TYPE4_EN  EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled.
+AT91C_AES_CTYPE_TYPE5_EN  EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled.
+// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+AT91C_AES_DATRDY          EQU (0x1 <<  0) ;- (AES) DATRDY
+AT91C_AES_ENDRX           EQU (0x1 <<  1) ;- (AES) PDC Read Buffer End
+AT91C_AES_ENDTX           EQU (0x1 <<  2) ;- (AES) PDC Write Buffer End
+AT91C_AES_RXBUFF          EQU (0x1 <<  3) ;- (AES) PDC Read Buffer Full
+AT91C_AES_TXBUFE          EQU (0x1 <<  4) ;- (AES) PDC Write Buffer Empty
+AT91C_AES_URAD            EQU (0x1 <<  8) ;- (AES) Unspecified Register Access Detection
+// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+AT91C_AES_URAT            EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status
+AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode.
+AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing.
+AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing.
+AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation.
+AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation.
+AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access.
+
+// - *****************************************************************************
+// -              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// - *****************************************************************************
+// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+AT91C_TDES_START          EQU (0x1 <<  0) ;- (TDES) Starts Processing
+AT91C_TDES_SWRST          EQU (0x1 <<  8) ;- (TDES) Software Reset
+// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+AT91C_TDES_CIPHER         EQU (0x1 <<  0) ;- (TDES) Processing Mode
+AT91C_TDES_TDESMOD        EQU (0x1 <<  1) ;- (TDES) Single or Triple DES Mode
+AT91C_TDES_KEYMOD         EQU (0x1 <<  4) ;- (TDES) Key Mode
+AT91C_TDES_SMOD           EQU (0x3 <<  8) ;- (TDES) Start Mode
+AT91C_TDES_SMOD_MANUAL    EQU (0x0 <<  8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+AT91C_TDES_SMOD_AUTO      EQU (0x1 <<  8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+AT91C_TDES_SMOD_PDC       EQU (0x2 <<  8) ;- (TDES) PDC Mode (cf datasheet).
+AT91C_TDES_OPMOD          EQU (0x3 << 12) ;- (TDES) Operation Mode
+AT91C_TDES_OPMOD_ECB      EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode.
+AT91C_TDES_OPMOD_CBC      EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode.
+AT91C_TDES_OPMOD_OFB      EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode.
+AT91C_TDES_OPMOD_CFB      EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode.
+AT91C_TDES_LOD            EQU (0x1 << 15) ;- (TDES) Last Output Data Mode
+AT91C_TDES_CFBS           EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size
+AT91C_TDES_CFBS_64_BIT    EQU (0x0 << 16) ;- (TDES) 64-bit.
+AT91C_TDES_CFBS_32_BIT    EQU (0x1 << 16) ;- (TDES) 32-bit.
+AT91C_TDES_CFBS_16_BIT    EQU (0x2 << 16) ;- (TDES) 16-bit.
+AT91C_TDES_CFBS_8_BIT     EQU (0x3 << 16) ;- (TDES) 8-bit.
+// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+AT91C_TDES_DATRDY         EQU (0x1 <<  0) ;- (TDES) DATRDY
+AT91C_TDES_ENDRX          EQU (0x1 <<  1) ;- (TDES) PDC Read Buffer End
+AT91C_TDES_ENDTX          EQU (0x1 <<  2) ;- (TDES) PDC Write Buffer End
+AT91C_TDES_RXBUFF         EQU (0x1 <<  3) ;- (TDES) PDC Read Buffer Full
+AT91C_TDES_TXBUFE         EQU (0x1 <<  4) ;- (TDES) PDC Write Buffer Empty
+AT91C_TDES_URAD           EQU (0x1 <<  8) ;- (TDES) Unspecified Register Access Detection
+// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+AT91C_TDES_URAT           EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status
+AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode.
+AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing.
+AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing.
+AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access.
+
+// - *****************************************************************************
+// -               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// - *****************************************************************************
+// - ========== Register definition for SYS peripheral ========== 
+// - ========== Register definition for AIC peripheral ========== 
+AT91C_AIC_IVR             EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
+AT91C_AIC_SMR             EQU (0xFFFFF000) ;- (AIC) Source Mode Register
+AT91C_AIC_FVR             EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
+AT91C_AIC_DCR             EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
+AT91C_AIC_EOICR           EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
+AT91C_AIC_SVR             EQU (0xFFFFF080) ;- (AIC) Source Vector Register
+AT91C_AIC_FFSR            EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
+AT91C_AIC_ICCR            EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
+AT91C_AIC_ISR             EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
+AT91C_AIC_IMR             EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
+AT91C_AIC_IPR             EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
+AT91C_AIC_FFER            EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
+AT91C_AIC_IECR            EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
+AT91C_AIC_ISCR            EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
+AT91C_AIC_FFDR            EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
+AT91C_AIC_CISR            EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
+AT91C_AIC_IDCR            EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
+AT91C_AIC_SPU             EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
+// - ========== Register definition for PDC_DBGU peripheral ========== 
+AT91C_DBGU_TCR            EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
+AT91C_DBGU_RNPR           EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
+AT91C_DBGU_TNPR           EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
+AT91C_DBGU_TPR            EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
+AT91C_DBGU_RPR            EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
+AT91C_DBGU_RCR            EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
+AT91C_DBGU_RNCR           EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
+AT91C_DBGU_PTCR           EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
+AT91C_DBGU_PTSR           EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
+AT91C_DBGU_TNCR           EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
+// - ========== Register definition for DBGU peripheral ========== 
+AT91C_DBGU_EXID           EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
+AT91C_DBGU_BRGR           EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
+AT91C_DBGU_IDR            EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
+AT91C_DBGU_CSR            EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
+AT91C_DBGU_CIDR           EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
+AT91C_DBGU_MR             EQU (0xFFFFF204) ;- (DBGU) Mode Register
+AT91C_DBGU_IMR            EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
+AT91C_DBGU_CR             EQU (0xFFFFF200) ;- (DBGU) Control Register
+AT91C_DBGU_FNTR           EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
+AT91C_DBGU_THR            EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
+AT91C_DBGU_RHR            EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
+AT91C_DBGU_IER            EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
+// - ========== Register definition for PIOA peripheral ========== 
+AT91C_PIOA_ODR            EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
+AT91C_PIOA_SODR           EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
+AT91C_PIOA_ISR            EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
+AT91C_PIOA_ABSR           EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
+AT91C_PIOA_IER            EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
+AT91C_PIOA_PPUDR          EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
+AT91C_PIOA_IMR            EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
+AT91C_PIOA_PER            EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
+AT91C_PIOA_IFDR           EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
+AT91C_PIOA_OWDR           EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
+AT91C_PIOA_MDSR           EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
+AT91C_PIOA_IDR            EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
+AT91C_PIOA_ODSR           EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
+AT91C_PIOA_PPUSR          EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
+AT91C_PIOA_OWSR           EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
+AT91C_PIOA_BSR            EQU (0xFFFFF474) ;- (PIOA) Select B Register
+AT91C_PIOA_OWER           EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
+AT91C_PIOA_IFER           EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
+AT91C_PIOA_PDSR           EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
+AT91C_PIOA_PPUER          EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
+AT91C_PIOA_OSR            EQU (0xFFFFF418) ;- (PIOA) Output Status Register
+AT91C_PIOA_ASR            EQU (0xFFFFF470) ;- (PIOA) Select A Register
+AT91C_PIOA_MDDR           EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
+AT91C_PIOA_CODR           EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
+AT91C_PIOA_MDER           EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
+AT91C_PIOA_PDR            EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
+AT91C_PIOA_IFSR           EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
+AT91C_PIOA_OER            EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
+AT91C_PIOA_PSR            EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
+// - ========== Register definition for PIOB peripheral ========== 
+AT91C_PIOB_OWDR           EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register
+AT91C_PIOB_MDER           EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register
+AT91C_PIOB_PPUSR          EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register
+AT91C_PIOB_IMR            EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register
+AT91C_PIOB_ASR            EQU (0xFFFFF670) ;- (PIOB) Select A Register
+AT91C_PIOB_PPUDR          EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register
+AT91C_PIOB_PSR            EQU (0xFFFFF608) ;- (PIOB) PIO Status Register
+AT91C_PIOB_IER            EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register
+AT91C_PIOB_CODR           EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register
+AT91C_PIOB_OWER           EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register
+AT91C_PIOB_ABSR           EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register
+AT91C_PIOB_IFDR           EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register
+AT91C_PIOB_PDSR           EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register
+AT91C_PIOB_IDR            EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register
+AT91C_PIOB_OWSR           EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register
+AT91C_PIOB_PDR            EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register
+AT91C_PIOB_ODR            EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr
+AT91C_PIOB_IFSR           EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register
+AT91C_PIOB_PPUER          EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register
+AT91C_PIOB_SODR           EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register
+AT91C_PIOB_ISR            EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register
+AT91C_PIOB_ODSR           EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register
+AT91C_PIOB_OSR            EQU (0xFFFFF618) ;- (PIOB) Output Status Register
+AT91C_PIOB_MDSR           EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register
+AT91C_PIOB_IFER           EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register
+AT91C_PIOB_BSR            EQU (0xFFFFF674) ;- (PIOB) Select B Register
+AT91C_PIOB_MDDR           EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register
+AT91C_PIOB_OER            EQU (0xFFFFF610) ;- (PIOB) Output Enable Register
+AT91C_PIOB_PER            EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register
+// - ========== Register definition for CKGR peripheral ========== 
+AT91C_CKGR_MOR            EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
+AT91C_CKGR_PLLR           EQU (0xFFFFFC2C) ;- (CKGR) PLL Register
+AT91C_CKGR_MCFR           EQU (0xFFFFFC24) ;- (CKGR) Main Clock  Frequency Register
+// - ========== Register definition for PMC peripheral ========== 
+AT91C_PMC_IDR             EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
+AT91C_PMC_MOR             EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register
+AT91C_PMC_PLLR            EQU (0xFFFFFC2C) ;- (PMC) PLL Register
+AT91C_PMC_PCER            EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
+AT91C_PMC_PCKR            EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
+AT91C_PMC_MCKR            EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
+AT91C_PMC_SCDR            EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
+AT91C_PMC_PCDR            EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
+AT91C_PMC_SCSR            EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
+AT91C_PMC_PCSR            EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
+AT91C_PMC_MCFR            EQU (0xFFFFFC24) ;- (PMC) Main Clock  Frequency Register
+AT91C_PMC_SCER            EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
+AT91C_PMC_IMR             EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
+AT91C_PMC_IER             EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
+AT91C_PMC_SR              EQU (0xFFFFFC68) ;- (PMC) Status Register
+// - ========== Register definition for RSTC peripheral ========== 
+AT91C_RSTC_RCR            EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register
+AT91C_RSTC_RMR            EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register
+AT91C_RSTC_RSR            EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register
+// - ========== Register definition for RTTC peripheral ========== 
+AT91C_RTTC_RTSR           EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register
+AT91C_RTTC_RTMR           EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register
+AT91C_RTTC_RTVR           EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register
+AT91C_RTTC_RTAR           EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register
+// - ========== Register definition for PITC peripheral ========== 
+AT91C_PITC_PIVR           EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register
+AT91C_PITC_PISR           EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register
+AT91C_PITC_PIIR           EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register
+AT91C_PITC_PIMR           EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register
+// - ========== Register definition for WDTC peripheral ========== 
+AT91C_WDTC_WDCR           EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register
+AT91C_WDTC_WDSR           EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register
+AT91C_WDTC_WDMR           EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register
+// - ========== Register definition for VREG peripheral ========== 
+AT91C_VREG_MR             EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register
+// - ========== Register definition for MC peripheral ========== 
+AT91C_MC_ASR              EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
+AT91C_MC_RCR              EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
+AT91C_MC_FCR              EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register
+AT91C_MC_AASR             EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
+AT91C_MC_FSR              EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register
+AT91C_MC_FMR              EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register
+// - ========== Register definition for PDC_SPI1 peripheral ========== 
+AT91C_SPI1_PTCR           EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register
+AT91C_SPI1_RPR            EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register
+AT91C_SPI1_TNCR           EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register
+AT91C_SPI1_TPR            EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register
+AT91C_SPI1_TNPR           EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register
+AT91C_SPI1_TCR            EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register
+AT91C_SPI1_RCR            EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register
+AT91C_SPI1_RNPR           EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register
+AT91C_SPI1_RNCR           EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register
+AT91C_SPI1_PTSR           EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register
+// - ========== Register definition for SPI1 peripheral ========== 
+AT91C_SPI1_IMR            EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register
+AT91C_SPI1_IER            EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register
+AT91C_SPI1_MR             EQU (0xFFFE4004) ;- (SPI1) Mode Register
+AT91C_SPI1_RDR            EQU (0xFFFE4008) ;- (SPI1) Receive Data Register
+AT91C_SPI1_IDR            EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register
+AT91C_SPI1_SR             EQU (0xFFFE4010) ;- (SPI1) Status Register
+AT91C_SPI1_TDR            EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register
+AT91C_SPI1_CR             EQU (0xFFFE4000) ;- (SPI1) Control Register
+AT91C_SPI1_CSR            EQU (0xFFFE4030) ;- (SPI1) Chip Select Register
+// - ========== Register definition for PDC_SPI0 peripheral ========== 
+AT91C_SPI0_PTCR           EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register
+AT91C_SPI0_TPR            EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register
+AT91C_SPI0_TCR            EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register
+AT91C_SPI0_RCR            EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register
+AT91C_SPI0_PTSR           EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register
+AT91C_SPI0_RNPR           EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register
+AT91C_SPI0_RPR            EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register
+AT91C_SPI0_TNCR           EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register
+AT91C_SPI0_RNCR           EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register
+AT91C_SPI0_TNPR           EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register
+// - ========== Register definition for SPI0 peripheral ========== 
+AT91C_SPI0_IER            EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register
+AT91C_SPI0_SR             EQU (0xFFFE0010) ;- (SPI0) Status Register
+AT91C_SPI0_IDR            EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register
+AT91C_SPI0_CR             EQU (0xFFFE0000) ;- (SPI0) Control Register
+AT91C_SPI0_MR             EQU (0xFFFE0004) ;- (SPI0) Mode Register
+AT91C_SPI0_IMR            EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register
+AT91C_SPI0_TDR            EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register
+AT91C_SPI0_RDR            EQU (0xFFFE0008) ;- (SPI0) Receive Data Register
+AT91C_SPI0_CSR            EQU (0xFFFE0030) ;- (SPI0) Chip Select Register
+// - ========== Register definition for PDC_US1 peripheral ========== 
+AT91C_US1_RNCR            EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
+AT91C_US1_PTCR            EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
+AT91C_US1_TCR             EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
+AT91C_US1_PTSR            EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
+AT91C_US1_TNPR            EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
+AT91C_US1_RCR             EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
+AT91C_US1_RNPR            EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
+AT91C_US1_RPR             EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
+AT91C_US1_TNCR            EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
+AT91C_US1_TPR             EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
+// - ========== Register definition for US1 peripheral ========== 
+AT91C_US1_IF              EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
+AT91C_US1_NER             EQU (0xFFFC4044) ;- (US1) Nb Errors Register
+AT91C_US1_RTOR            EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
+AT91C_US1_CSR             EQU (0xFFFC4014) ;- (US1) Channel Status Register
+AT91C_US1_IDR             EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
+AT91C_US1_IER             EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
+AT91C_US1_THR             EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
+AT91C_US1_TTGR            EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
+AT91C_US1_RHR             EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
+AT91C_US1_BRGR            EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
+AT91C_US1_IMR             EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
+AT91C_US1_FIDI            EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
+AT91C_US1_CR              EQU (0xFFFC4000) ;- (US1) Control Register
+AT91C_US1_MR              EQU (0xFFFC4004) ;- (US1) Mode Register
+// - ========== Register definition for PDC_US0 peripheral ========== 
+AT91C_US0_TNPR            EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
+AT91C_US0_RNPR            EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
+AT91C_US0_TCR             EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
+AT91C_US0_PTCR            EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
+AT91C_US0_PTSR            EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
+AT91C_US0_TNCR            EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
+AT91C_US0_TPR             EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
+AT91C_US0_RCR             EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
+AT91C_US0_RPR             EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
+AT91C_US0_RNCR            EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
+// - ========== Register definition for US0 peripheral ========== 
+AT91C_US0_BRGR            EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
+AT91C_US0_NER             EQU (0xFFFC0044) ;- (US0) Nb Errors Register
+AT91C_US0_CR              EQU (0xFFFC0000) ;- (US0) Control Register
+AT91C_US0_IMR             EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
+AT91C_US0_FIDI            EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
+AT91C_US0_TTGR            EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
+AT91C_US0_MR              EQU (0xFFFC0004) ;- (US0) Mode Register
+AT91C_US0_RTOR            EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
+AT91C_US0_CSR             EQU (0xFFFC0014) ;- (US0) Channel Status Register
+AT91C_US0_RHR             EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
+AT91C_US0_IDR             EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
+AT91C_US0_THR             EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
+AT91C_US0_IF              EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
+AT91C_US0_IER             EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
+// - ========== Register definition for PDC_SSC peripheral ========== 
+AT91C_SSC_TNCR            EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register
+AT91C_SSC_RPR             EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register
+AT91C_SSC_RNCR            EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register
+AT91C_SSC_TPR             EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register
+AT91C_SSC_PTCR            EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register
+AT91C_SSC_TCR             EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register
+AT91C_SSC_RCR             EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register
+AT91C_SSC_RNPR            EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register
+AT91C_SSC_TNPR            EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register
+AT91C_SSC_PTSR            EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register
+// - ========== Register definition for SSC peripheral ========== 
+AT91C_SSC_RHR             EQU (0xFFFD4020) ;- (SSC) Receive Holding Register
+AT91C_SSC_RSHR            EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register
+AT91C_SSC_TFMR            EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register
+AT91C_SSC_IDR             EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register
+AT91C_SSC_THR             EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register
+AT91C_SSC_RCMR            EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister
+AT91C_SSC_IER             EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register
+AT91C_SSC_TSHR            EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register
+AT91C_SSC_SR              EQU (0xFFFD4040) ;- (SSC) Status Register
+AT91C_SSC_CMR             EQU (0xFFFD4004) ;- (SSC) Clock Mode Register
+AT91C_SSC_TCMR            EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register
+AT91C_SSC_CR              EQU (0xFFFD4000) ;- (SSC) Control Register
+AT91C_SSC_IMR             EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register
+AT91C_SSC_RFMR            EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register
+// - ========== Register definition for TWI peripheral ========== 
+AT91C_TWI_IER             EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
+AT91C_TWI_CR              EQU (0xFFFB8000) ;- (TWI) Control Register
+AT91C_TWI_SR              EQU (0xFFFB8020) ;- (TWI) Status Register
+AT91C_TWI_IMR             EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
+AT91C_TWI_THR             EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
+AT91C_TWI_IDR             EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
+AT91C_TWI_IADR            EQU (0xFFFB800C) ;- (TWI) Internal Address Register
+AT91C_TWI_MMR             EQU (0xFFFB8004) ;- (TWI) Master Mode Register
+AT91C_TWI_CWGR            EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
+AT91C_TWI_RHR             EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
+// - ========== Register definition for PWMC_CH3 peripheral ========== 
+AT91C_PWMC_CH3_CUPDR      EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register
+AT91C_PWMC_CH3_Reserved   EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved
+AT91C_PWMC_CH3_CPRDR      EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register
+AT91C_PWMC_CH3_CDTYR      EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register
+AT91C_PWMC_CH3_CCNTR      EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register
+AT91C_PWMC_CH3_CMR        EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register
+// - ========== Register definition for PWMC_CH2 peripheral ========== 
+AT91C_PWMC_CH2_Reserved   EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved
+AT91C_PWMC_CH2_CMR        EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register
+AT91C_PWMC_CH2_CCNTR      EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register
+AT91C_PWMC_CH2_CPRDR      EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register
+AT91C_PWMC_CH2_CUPDR      EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register
+AT91C_PWMC_CH2_CDTYR      EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register
+// - ========== Register definition for PWMC_CH1 peripheral ========== 
+AT91C_PWMC_CH1_Reserved   EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved
+AT91C_PWMC_CH1_CUPDR      EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register
+AT91C_PWMC_CH1_CPRDR      EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register
+AT91C_PWMC_CH1_CCNTR      EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register
+AT91C_PWMC_CH1_CDTYR      EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register
+AT91C_PWMC_CH1_CMR        EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register
+// - ========== Register definition for PWMC_CH0 peripheral ========== 
+AT91C_PWMC_CH0_Reserved   EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved
+AT91C_PWMC_CH0_CPRDR      EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register
+AT91C_PWMC_CH0_CDTYR      EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register
+AT91C_PWMC_CH0_CMR        EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register
+AT91C_PWMC_CH0_CUPDR      EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register
+AT91C_PWMC_CH0_CCNTR      EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register
+// - ========== Register definition for PWMC peripheral ========== 
+AT91C_PWMC_IDR            EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register
+AT91C_PWMC_DIS            EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register
+AT91C_PWMC_IER            EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register
+AT91C_PWMC_VR             EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register
+AT91C_PWMC_ISR            EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register
+AT91C_PWMC_SR             EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register
+AT91C_PWMC_IMR            EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register
+AT91C_PWMC_MR             EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register
+AT91C_PWMC_ENA            EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register
+// - ========== Register definition for UDP peripheral ========== 
+AT91C_UDP_IMR             EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
+AT91C_UDP_FADDR           EQU (0xFFFB0008) ;- (UDP) Function Address Register
+AT91C_UDP_NUM             EQU (0xFFFB0000) ;- (UDP) Frame Number Register
+AT91C_UDP_FDR             EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
+AT91C_UDP_ISR             EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
+AT91C_UDP_CSR             EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
+AT91C_UDP_IDR             EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
+AT91C_UDP_ICR             EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
+AT91C_UDP_RSTEP           EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
+AT91C_UDP_TXVC            EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register
+AT91C_UDP_GLBSTATE        EQU (0xFFFB0004) ;- (UDP) Global State Register
+AT91C_UDP_IER             EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
+// - ========== Register definition for TC0 peripheral ========== 
+AT91C_TC0_SR              EQU (0xFFFA0020) ;- (TC0) Status Register
+AT91C_TC0_RC              EQU (0xFFFA001C) ;- (TC0) Register C
+AT91C_TC0_RB              EQU (0xFFFA0018) ;- (TC0) Register B
+AT91C_TC0_CCR             EQU (0xFFFA0000) ;- (TC0) Channel Control Register
+AT91C_TC0_CMR             EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC0_IER             EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
+AT91C_TC0_RA              EQU (0xFFFA0014) ;- (TC0) Register A
+AT91C_TC0_IDR             EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
+AT91C_TC0_CV              EQU (0xFFFA0010) ;- (TC0) Counter Value
+AT91C_TC0_IMR             EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
+// - ========== Register definition for TC1 peripheral ========== 
+AT91C_TC1_RB              EQU (0xFFFA0058) ;- (TC1) Register B
+AT91C_TC1_CCR             EQU (0xFFFA0040) ;- (TC1) Channel Control Register
+AT91C_TC1_IER             EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
+AT91C_TC1_IDR             EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
+AT91C_TC1_SR              EQU (0xFFFA0060) ;- (TC1) Status Register
+AT91C_TC1_CMR             EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC1_RA              EQU (0xFFFA0054) ;- (TC1) Register A
+AT91C_TC1_RC              EQU (0xFFFA005C) ;- (TC1) Register C
+AT91C_TC1_IMR             EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
+AT91C_TC1_CV              EQU (0xFFFA0050) ;- (TC1) Counter Value
+// - ========== Register definition for TC2 peripheral ========== 
+AT91C_TC2_CMR             EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+AT91C_TC2_CCR             EQU (0xFFFA0080) ;- (TC2) Channel Control Register
+AT91C_TC2_CV              EQU (0xFFFA0090) ;- (TC2) Counter Value
+AT91C_TC2_RA              EQU (0xFFFA0094) ;- (TC2) Register A
+AT91C_TC2_RB              EQU (0xFFFA0098) ;- (TC2) Register B
+AT91C_TC2_IDR             EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
+AT91C_TC2_IMR             EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
+AT91C_TC2_RC              EQU (0xFFFA009C) ;- (TC2) Register C
+AT91C_TC2_IER             EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
+AT91C_TC2_SR              EQU (0xFFFA00A0) ;- (TC2) Status Register
+// - ========== Register definition for TCB peripheral ========== 
+AT91C_TCB_BMR             EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register
+AT91C_TCB_BCR             EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register
+// - ========== Register definition for CAN_MB0 peripheral ========== 
+AT91C_CAN_MB0_MDL         EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register
+AT91C_CAN_MB0_MAM         EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register
+AT91C_CAN_MB0_MCR         EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register
+AT91C_CAN_MB0_MID         EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register
+AT91C_CAN_MB0_MSR         EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register
+AT91C_CAN_MB0_MFID        EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register
+AT91C_CAN_MB0_MDH         EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register
+AT91C_CAN_MB0_MMR         EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register
+// - ========== Register definition for CAN_MB1 peripheral ========== 
+AT91C_CAN_MB1_MDL         EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register
+AT91C_CAN_MB1_MID         EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register
+AT91C_CAN_MB1_MMR         EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register
+AT91C_CAN_MB1_MSR         EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register
+AT91C_CAN_MB1_MAM         EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register
+AT91C_CAN_MB1_MDH         EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register
+AT91C_CAN_MB1_MCR         EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register
+AT91C_CAN_MB1_MFID        EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register
+// - ========== Register definition for CAN_MB2 peripheral ========== 
+AT91C_CAN_MB2_MCR         EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register
+AT91C_CAN_MB2_MDH         EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register
+AT91C_CAN_MB2_MID         EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register
+AT91C_CAN_MB2_MDL         EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register
+AT91C_CAN_MB2_MMR         EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register
+AT91C_CAN_MB2_MAM         EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register
+AT91C_CAN_MB2_MFID        EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register
+AT91C_CAN_MB2_MSR         EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register
+// - ========== Register definition for CAN_MB3 peripheral ========== 
+AT91C_CAN_MB3_MFID        EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register
+AT91C_CAN_MB3_MAM         EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register
+AT91C_CAN_MB3_MID         EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register
+AT91C_CAN_MB3_MCR         EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register
+AT91C_CAN_MB3_MMR         EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register
+AT91C_CAN_MB3_MSR         EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register
+AT91C_CAN_MB3_MDL         EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register
+AT91C_CAN_MB3_MDH         EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register
+// - ========== Register definition for CAN_MB4 peripheral ========== 
+AT91C_CAN_MB4_MID         EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register
+AT91C_CAN_MB4_MMR         EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register
+AT91C_CAN_MB4_MDH         EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register
+AT91C_CAN_MB4_MFID        EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register
+AT91C_CAN_MB4_MSR         EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register
+AT91C_CAN_MB4_MCR         EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register
+AT91C_CAN_MB4_MDL         EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register
+AT91C_CAN_MB4_MAM         EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register
+// - ========== Register definition for CAN_MB5 peripheral ========== 
+AT91C_CAN_MB5_MSR         EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register
+AT91C_CAN_MB5_MCR         EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register
+AT91C_CAN_MB5_MFID        EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register
+AT91C_CAN_MB5_MDH         EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register
+AT91C_CAN_MB5_MID         EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register
+AT91C_CAN_MB5_MMR         EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register
+AT91C_CAN_MB5_MDL         EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register
+AT91C_CAN_MB5_MAM         EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register
+// - ========== Register definition for CAN_MB6 peripheral ========== 
+AT91C_CAN_MB6_MFID        EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register
+AT91C_CAN_MB6_MID         EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register
+AT91C_CAN_MB6_MAM         EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register
+AT91C_CAN_MB6_MSR         EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register
+AT91C_CAN_MB6_MDL         EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register
+AT91C_CAN_MB6_MCR         EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register
+AT91C_CAN_MB6_MDH         EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register
+AT91C_CAN_MB6_MMR         EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register
+// - ========== Register definition for CAN_MB7 peripheral ========== 
+AT91C_CAN_MB7_MCR         EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register
+AT91C_CAN_MB7_MDH         EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register
+AT91C_CAN_MB7_MFID        EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register
+AT91C_CAN_MB7_MDL         EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register
+AT91C_CAN_MB7_MID         EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register
+AT91C_CAN_MB7_MMR         EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register
+AT91C_CAN_MB7_MAM         EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register
+AT91C_CAN_MB7_MSR         EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register
+// - ========== Register definition for CAN peripheral ========== 
+AT91C_CAN_TCR             EQU (0xFFFD0024) ;- (CAN) Transfer Command Register
+AT91C_CAN_IMR             EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register
+AT91C_CAN_IER             EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register
+AT91C_CAN_ECR             EQU (0xFFFD0020) ;- (CAN) Error Counter Register
+AT91C_CAN_TIMESTP         EQU (0xFFFD001C) ;- (CAN) Time Stamp Register
+AT91C_CAN_MR              EQU (0xFFFD0000) ;- (CAN) Mode Register
+AT91C_CAN_IDR             EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register
+AT91C_CAN_ACR             EQU (0xFFFD0028) ;- (CAN) Abort Command Register
+AT91C_CAN_TIM             EQU (0xFFFD0018) ;- (CAN) Timer Register
+AT91C_CAN_SR              EQU (0xFFFD0010) ;- (CAN) Status Register
+AT91C_CAN_BR              EQU (0xFFFD0014) ;- (CAN) Baudrate Register
+AT91C_CAN_VR              EQU (0xFFFD00FC) ;- (CAN) Version Register
+// - ========== Register definition for EMAC peripheral ========== 
+AT91C_EMAC_ISR            EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register
+AT91C_EMAC_SA4H           EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes
+AT91C_EMAC_SA1L           EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes
+AT91C_EMAC_ELE            EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register
+AT91C_EMAC_LCOL           EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register
+AT91C_EMAC_RLE            EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register
+AT91C_EMAC_WOL            EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register
+AT91C_EMAC_DTF            EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register
+AT91C_EMAC_TUND           EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register
+AT91C_EMAC_NCR            EQU (0xFFFDC000) ;- (EMAC) Network Control Register
+AT91C_EMAC_SA4L           EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes
+AT91C_EMAC_RSR            EQU (0xFFFDC020) ;- (EMAC) Receive Status Register
+AT91C_EMAC_SA3L           EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes
+AT91C_EMAC_TSR            EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register
+AT91C_EMAC_IDR            EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register
+AT91C_EMAC_RSE            EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register
+AT91C_EMAC_ECOL           EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register
+AT91C_EMAC_TID            EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register
+AT91C_EMAC_HRB            EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]
+AT91C_EMAC_TBQP           EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer
+AT91C_EMAC_USRIO          EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register
+AT91C_EMAC_PTR            EQU (0xFFFDC038) ;- (EMAC) Pause Time Register
+AT91C_EMAC_SA2H           EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes
+AT91C_EMAC_ROV            EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register
+AT91C_EMAC_ALE            EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register
+AT91C_EMAC_RJA            EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register
+AT91C_EMAC_RBQP           EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer
+AT91C_EMAC_TPF            EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register
+AT91C_EMAC_NCFGR          EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register
+AT91C_EMAC_HRT            EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]
+AT91C_EMAC_USF            EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register
+AT91C_EMAC_FCSE           EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register
+AT91C_EMAC_TPQ            EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register
+AT91C_EMAC_MAN            EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register
+AT91C_EMAC_FTO            EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register
+AT91C_EMAC_REV            EQU (0xFFFDC0FC) ;- (EMAC) Revision Register
+AT91C_EMAC_IMR            EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register
+AT91C_EMAC_SCF            EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register
+AT91C_EMAC_PFR            EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register
+AT91C_EMAC_MCF            EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register
+AT91C_EMAC_NSR            EQU (0xFFFDC008) ;- (EMAC) Network Status Register
+AT91C_EMAC_SA2L           EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes
+AT91C_EMAC_FRO            EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register
+AT91C_EMAC_IER            EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register
+AT91C_EMAC_SA1H           EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes
+AT91C_EMAC_CSE            EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register
+AT91C_EMAC_SA3H           EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes
+AT91C_EMAC_RRE            EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register
+AT91C_EMAC_STE            EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register
+// - ========== Register definition for PDC_ADC peripheral ========== 
+AT91C_ADC_PTSR            EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register
+AT91C_ADC_PTCR            EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register
+AT91C_ADC_TNPR            EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register
+AT91C_ADC_TNCR            EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register
+AT91C_ADC_RNPR            EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register
+AT91C_ADC_RNCR            EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register
+AT91C_ADC_RPR             EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register
+AT91C_ADC_TCR             EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register
+AT91C_ADC_TPR             EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register
+AT91C_ADC_RCR             EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register
+// - ========== Register definition for ADC peripheral ========== 
+AT91C_ADC_CDR2            EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2
+AT91C_ADC_CDR3            EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3
+AT91C_ADC_CDR0            EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0
+AT91C_ADC_CDR5            EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5
+AT91C_ADC_CHDR            EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register
+AT91C_ADC_SR              EQU (0xFFFD801C) ;- (ADC) ADC Status Register
+AT91C_ADC_CDR4            EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4
+AT91C_ADC_CDR1            EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1
+AT91C_ADC_LCDR            EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register
+AT91C_ADC_IDR             EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register
+AT91C_ADC_CR              EQU (0xFFFD8000) ;- (ADC) ADC Control Register
+AT91C_ADC_CDR7            EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7
+AT91C_ADC_CDR6            EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6
+AT91C_ADC_IER             EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register
+AT91C_ADC_CHER            EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register
+AT91C_ADC_CHSR            EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register
+AT91C_ADC_MR              EQU (0xFFFD8004) ;- (ADC) ADC Mode Register
+AT91C_ADC_IMR             EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register
+// - ========== Register definition for PDC_AES peripheral ========== 
+AT91C_AES_TPR             EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register
+AT91C_AES_PTCR            EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register
+AT91C_AES_RNPR            EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register
+AT91C_AES_TNCR            EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register
+AT91C_AES_TCR             EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register
+AT91C_AES_RCR             EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register
+AT91C_AES_RNCR            EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register
+AT91C_AES_TNPR            EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register
+AT91C_AES_RPR             EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register
+AT91C_AES_PTSR            EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register
+// - ========== Register definition for AES peripheral ========== 
+AT91C_AES_IVxR            EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register
+AT91C_AES_MR              EQU (0xFFFA4004) ;- (AES) Mode Register
+AT91C_AES_VR              EQU (0xFFFA40FC) ;- (AES) AES Version Register
+AT91C_AES_ODATAxR         EQU (0xFFFA4050) ;- (AES) Output Data x Register
+AT91C_AES_IDATAxR         EQU (0xFFFA4040) ;- (AES) Input Data x Register
+AT91C_AES_CR              EQU (0xFFFA4000) ;- (AES) Control Register
+AT91C_AES_IDR             EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register
+AT91C_AES_IMR             EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register
+AT91C_AES_IER             EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register
+AT91C_AES_KEYWxR          EQU (0xFFFA4020) ;- (AES) Key Word x Register
+AT91C_AES_ISR             EQU (0xFFFA401C) ;- (AES) Interrupt Status Register
+// - ========== Register definition for PDC_TDES peripheral ========== 
+AT91C_TDES_RNCR           EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register
+AT91C_TDES_TCR            EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register
+AT91C_TDES_RCR            EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register
+AT91C_TDES_TNPR           EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register
+AT91C_TDES_RNPR           EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register
+AT91C_TDES_RPR            EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register
+AT91C_TDES_TNCR           EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register
+AT91C_TDES_TPR            EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register
+AT91C_TDES_PTSR           EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register
+AT91C_TDES_PTCR           EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register
+// - ========== Register definition for TDES peripheral ========== 
+AT91C_TDES_KEY2WxR        EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register
+AT91C_TDES_KEY3WxR        EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register
+AT91C_TDES_IDR            EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register
+AT91C_TDES_VR             EQU (0xFFFA80FC) ;- (TDES) TDES Version Register
+AT91C_TDES_IVxR           EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register
+AT91C_TDES_ODATAxR        EQU (0xFFFA8050) ;- (TDES) Output Data x Register
+AT91C_TDES_IMR            EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register
+AT91C_TDES_MR             EQU (0xFFFA8004) ;- (TDES) Mode Register
+AT91C_TDES_CR             EQU (0xFFFA8000) ;- (TDES) Control Register
+AT91C_TDES_IER            EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register
+AT91C_TDES_ISR            EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register
+AT91C_TDES_IDATAxR        EQU (0xFFFA8040) ;- (TDES) Input Data x Register
+AT91C_TDES_KEY1WxR        EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register
+
+// - *****************************************************************************
+// -               PIO DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_PIO_PA0             EQU (1 <<  0) ;- Pin Controlled by PA0
+AT91C_PA0_RXD0            EQU (AT91C_PIO_PA0) ;-  USART 0 Receive Data
+AT91C_PIO_PA1             EQU (1 <<  1) ;- Pin Controlled by PA1
+AT91C_PA1_TXD0            EQU (AT91C_PIO_PA1) ;-  USART 0 Transmit Data
+AT91C_PIO_PA10            EQU (1 << 10) ;- Pin Controlled by PA10
+AT91C_PA10_TWD            EQU (AT91C_PIO_PA10) ;-  TWI Two-wire Serial Data
+AT91C_PIO_PA11            EQU (1 << 11) ;- Pin Controlled by PA11
+AT91C_PA11_TWCK           EQU (AT91C_PIO_PA11) ;-  TWI Two-wire Serial Clock
+AT91C_PIO_PA12            EQU (1 << 12) ;- Pin Controlled by PA12
+AT91C_PA12_NPCS00         EQU (AT91C_PIO_PA12) ;-  SPI 0 Peripheral Chip Select 0
+AT91C_PIO_PA13            EQU (1 << 13) ;- Pin Controlled by PA13
+AT91C_PA13_NPCS01         EQU (AT91C_PIO_PA13) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PA13_PCK1           EQU (AT91C_PIO_PA13) ;-  PMC Programmable Clock Output 1
+AT91C_PIO_PA14            EQU (1 << 14) ;- Pin Controlled by PA14
+AT91C_PA14_NPCS02         EQU (AT91C_PIO_PA14) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PA14_IRQ1           EQU (AT91C_PIO_PA14) ;-  External Interrupt 1
+AT91C_PIO_PA15            EQU (1 << 15) ;- Pin Controlled by PA15
+AT91C_PA15_NPCS03         EQU (AT91C_PIO_PA15) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PA15_TCLK2          EQU (AT91C_PIO_PA15) ;-  Timer Counter 2 external clock input
+AT91C_PIO_PA16            EQU (1 << 16) ;- Pin Controlled by PA16
+AT91C_PA16_MISO0          EQU (AT91C_PIO_PA16) ;-  SPI 0 Master In Slave
+AT91C_PIO_PA17            EQU (1 << 17) ;- Pin Controlled by PA17
+AT91C_PA17_MOSI0          EQU (AT91C_PIO_PA17) ;-  SPI 0 Master Out Slave
+AT91C_PIO_PA18            EQU (1 << 18) ;- Pin Controlled by PA18
+AT91C_PA18_SPCK0          EQU (AT91C_PIO_PA18) ;-  SPI 0 Serial Clock
+AT91C_PIO_PA19            EQU (1 << 19) ;- Pin Controlled by PA19
+AT91C_PA19_CANRX          EQU (AT91C_PIO_PA19) ;-  CAN Receive
+AT91C_PIO_PA2             EQU (1 <<  2) ;- Pin Controlled by PA2
+AT91C_PA2_SCK0            EQU (AT91C_PIO_PA2) ;-  USART 0 Serial Clock
+AT91C_PA2_NPCS11          EQU (AT91C_PIO_PA2) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PA20            EQU (1 << 20) ;- Pin Controlled by PA20
+AT91C_PA20_CANTX          EQU (AT91C_PIO_PA20) ;-  CAN Transmit
+AT91C_PIO_PA21            EQU (1 << 21) ;- Pin Controlled by PA21
+AT91C_PA21_TF             EQU (AT91C_PIO_PA21) ;-  SSC Transmit Frame Sync
+AT91C_PA21_NPCS10         EQU (AT91C_PIO_PA21) ;-  SPI 1 Peripheral Chip Select 0
+AT91C_PIO_PA22            EQU (1 << 22) ;- Pin Controlled by PA22
+AT91C_PA22_TK             EQU (AT91C_PIO_PA22) ;-  SSC Transmit Clock
+AT91C_PA22_SPCK1          EQU (AT91C_PIO_PA22) ;-  SPI 1 Serial Clock
+AT91C_PIO_PA23            EQU (1 << 23) ;- Pin Controlled by PA23
+AT91C_PA23_TD             EQU (AT91C_PIO_PA23) ;-  SSC Transmit data
+AT91C_PA23_MOSI1          EQU (AT91C_PIO_PA23) ;-  SPI 1 Master Out Slave
+AT91C_PIO_PA24            EQU (1 << 24) ;- Pin Controlled by PA24
+AT91C_PA24_RD             EQU (AT91C_PIO_PA24) ;-  SSC Receive Data
+AT91C_PA24_MISO1          EQU (AT91C_PIO_PA24) ;-  SPI 1 Master In Slave
+AT91C_PIO_PA25            EQU (1 << 25) ;- Pin Controlled by PA25
+AT91C_PA25_RK             EQU (AT91C_PIO_PA25) ;-  SSC Receive Clock
+AT91C_PA25_NPCS11         EQU (AT91C_PIO_PA25) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PA26            EQU (1 << 26) ;- Pin Controlled by PA26
+AT91C_PA26_RF             EQU (AT91C_PIO_PA26) ;-  SSC Receive Frame Sync
+AT91C_PA26_NPCS12         EQU (AT91C_PIO_PA26) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PA27            EQU (1 << 27) ;- Pin Controlled by PA27
+AT91C_PA27_DRXD           EQU (AT91C_PIO_PA27) ;-  DBGU Debug Receive Data
+AT91C_PA27_PCK3           EQU (AT91C_PIO_PA27) ;-  PMC Programmable Clock Output 3
+AT91C_PIO_PA28            EQU (1 << 28) ;- Pin Controlled by PA28
+AT91C_PA28_DTXD           EQU (AT91C_PIO_PA28) ;-  DBGU Debug Transmit Data
+AT91C_PIO_PA29            EQU (1 << 29) ;- Pin Controlled by PA29
+AT91C_PA29_FIQ            EQU (AT91C_PIO_PA29) ;-  AIC Fast Interrupt Input
+AT91C_PA29_NPCS13         EQU (AT91C_PIO_PA29) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PA3             EQU (1 <<  3) ;- Pin Controlled by PA3
+AT91C_PA3_RTS0            EQU (AT91C_PIO_PA3) ;-  USART 0 Ready To Send
+AT91C_PA3_NPCS12          EQU (AT91C_PIO_PA3) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PA30            EQU (1 << 30) ;- Pin Controlled by PA30
+AT91C_PA30_IRQ0           EQU (AT91C_PIO_PA30) ;-  External Interrupt 0
+AT91C_PA30_PCK2           EQU (AT91C_PIO_PA30) ;-  PMC Programmable Clock Output 2
+AT91C_PIO_PA4             EQU (1 <<  4) ;- Pin Controlled by PA4
+AT91C_PA4_CTS0            EQU (AT91C_PIO_PA4) ;-  USART 0 Clear To Send
+AT91C_PA4_NPCS13          EQU (AT91C_PIO_PA4) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PA5             EQU (1 <<  5) ;- Pin Controlled by PA5
+AT91C_PA5_RXD1            EQU (AT91C_PIO_PA5) ;-  USART 1 Receive Data
+AT91C_PIO_PA6             EQU (1 <<  6) ;- Pin Controlled by PA6
+AT91C_PA6_TXD1            EQU (AT91C_PIO_PA6) ;-  USART 1 Transmit Data
+AT91C_PIO_PA7             EQU (1 <<  7) ;- Pin Controlled by PA7
+AT91C_PA7_SCK1            EQU (AT91C_PIO_PA7) ;-  USART 1 Serial Clock
+AT91C_PA7_NPCS01          EQU (AT91C_PIO_PA7) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PIO_PA8             EQU (1 <<  8) ;- Pin Controlled by PA8
+AT91C_PA8_RTS1            EQU (AT91C_PIO_PA8) ;-  USART 1 Ready To Send
+AT91C_PA8_NPCS02          EQU (AT91C_PIO_PA8) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PIO_PA9             EQU (1 <<  9) ;- Pin Controlled by PA9
+AT91C_PA9_CTS1            EQU (AT91C_PIO_PA9) ;-  USART 1 Clear To Send
+AT91C_PA9_NPCS03          EQU (AT91C_PIO_PA9) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PIO_PB0             EQU (1 <<  0) ;- Pin Controlled by PB0
+AT91C_PB0_ETXCK_EREFCK    EQU (AT91C_PIO_PB0) ;-  Ethernet MAC Transmit Clock/Reference Clock
+AT91C_PB0_PCK0            EQU (AT91C_PIO_PB0) ;-  PMC Programmable Clock Output 0
+AT91C_PIO_PB1             EQU (1 <<  1) ;- Pin Controlled by PB1
+AT91C_PB1_ETXEN           EQU (AT91C_PIO_PB1) ;-  Ethernet MAC Transmit Enable
+AT91C_PIO_PB10            EQU (1 << 10) ;- Pin Controlled by PB10
+AT91C_PB10_ETX2           EQU (AT91C_PIO_PB10) ;-  Ethernet MAC Transmit Data 2
+AT91C_PB10_NPCS11         EQU (AT91C_PIO_PB10) ;-  SPI 1 Peripheral Chip Select 1
+AT91C_PIO_PB11            EQU (1 << 11) ;- Pin Controlled by PB11
+AT91C_PB11_ETX3           EQU (AT91C_PIO_PB11) ;-  Ethernet MAC Transmit Data 3
+AT91C_PB11_NPCS12         EQU (AT91C_PIO_PB11) ;-  SPI 1 Peripheral Chip Select 2
+AT91C_PIO_PB12            EQU (1 << 12) ;- Pin Controlled by PB12
+AT91C_PB12_ETXER          EQU (AT91C_PIO_PB12) ;-  Ethernet MAC Transmikt Coding Error
+AT91C_PB12_TCLK0          EQU (AT91C_PIO_PB12) ;-  Timer Counter 0 external clock input
+AT91C_PIO_PB13            EQU (1 << 13) ;- Pin Controlled by PB13
+AT91C_PB13_ERX2           EQU (AT91C_PIO_PB13) ;-  Ethernet MAC Receive Data 2
+AT91C_PB13_NPCS01         EQU (AT91C_PIO_PB13) ;-  SPI 0 Peripheral Chip Select 1
+AT91C_PIO_PB14            EQU (1 << 14) ;- Pin Controlled by PB14
+AT91C_PB14_ERX3           EQU (AT91C_PIO_PB14) ;-  Ethernet MAC Receive Data 3
+AT91C_PB14_NPCS02         EQU (AT91C_PIO_PB14) ;-  SPI 0 Peripheral Chip Select 2
+AT91C_PIO_PB15            EQU (1 << 15) ;- Pin Controlled by PB15
+AT91C_PB15_ERXDV          EQU (AT91C_PIO_PB15) ;-  Ethernet MAC Receive Data Valid
+AT91C_PIO_PB16            EQU (1 << 16) ;- Pin Controlled by PB16
+AT91C_PB16_ECOL           EQU (AT91C_PIO_PB16) ;-  Ethernet MAC Collision Detected
+AT91C_PB16_NPCS13         EQU (AT91C_PIO_PB16) ;-  SPI 1 Peripheral Chip Select 3
+AT91C_PIO_PB17            EQU (1 << 17) ;- Pin Controlled by PB17
+AT91C_PB17_ERXCK          EQU (AT91C_PIO_PB17) ;-  Ethernet MAC Receive Clock
+AT91C_PB17_NPCS03         EQU (AT91C_PIO_PB17) ;-  SPI 0 Peripheral Chip Select 3
+AT91C_PIO_PB18            EQU (1 << 18) ;- Pin Controlled by PB18
+AT91C_PB18_EF100          EQU (AT91C_PIO_PB18) ;-  Ethernet MAC Force 100 Mbits/sec
+AT91C_PB18_ADTRG          EQU (AT91C_PIO_PB18) ;-  ADC External Trigger
+AT91C_PIO_PB19            EQU (1 << 19) ;- Pin Controlled by PB19
+AT91C_PB19_PWM0           EQU (AT91C_PIO_PB19) ;-  PWM Channel 0
+AT91C_PB19_TCLK1          EQU (AT91C_PIO_PB19) ;-  Timer Counter 1 external clock input
+AT91C_PIO_PB2             EQU (1 <<  2) ;- Pin Controlled by PB2
+AT91C_PB2_ETX0            EQU (AT91C_PIO_PB2) ;-  Ethernet MAC Transmit Data 0
+AT91C_PIO_PB20            EQU (1 << 20) ;- Pin Controlled by PB20
+AT91C_PB20_PWM1           EQU (AT91C_PIO_PB20) ;-  PWM Channel 1
+AT91C_PB20_PCK0           EQU (AT91C_PIO_PB20) ;-  PMC Programmable Clock Output 0
+AT91C_PIO_PB21            EQU (1 << 21) ;- Pin Controlled by PB21
+AT91C_PB21_PWM2           EQU (AT91C_PIO_PB21) ;-  PWM Channel 2
+AT91C_PB21_PCK1           EQU (AT91C_PIO_PB21) ;-  PMC Programmable Clock Output 1
+AT91C_PIO_PB22            EQU (1 << 22) ;- Pin Controlled by PB22
+AT91C_PB22_PWM3           EQU (AT91C_PIO_PB22) ;-  PWM Channel 3
+AT91C_PB22_PCK2           EQU (AT91C_PIO_PB22) ;-  PMC Programmable Clock Output 2
+AT91C_PIO_PB23            EQU (1 << 23) ;- Pin Controlled by PB23
+AT91C_PB23_TIOA0          EQU (AT91C_PIO_PB23) ;-  Timer Counter 0 Multipurpose Timer I/O Pin A
+AT91C_PB23_DCD1           EQU (AT91C_PIO_PB23) ;-  USART 1 Data Carrier Detect
+AT91C_PIO_PB24            EQU (1 << 24) ;- Pin Controlled by PB24
+AT91C_PB24_TIOB0          EQU (AT91C_PIO_PB24) ;-  Timer Counter 0 Multipurpose Timer I/O Pin B
+AT91C_PB24_DSR1           EQU (AT91C_PIO_PB24) ;-  USART 1 Data Set ready
+AT91C_PIO_PB25            EQU (1 << 25) ;- Pin Controlled by PB25
+AT91C_PB25_TIOA1          EQU (AT91C_PIO_PB25) ;-  Timer Counter 1 Multipurpose Timer I/O Pin A
+AT91C_PB25_DTR1           EQU (AT91C_PIO_PB25) ;-  USART 1 Data Terminal ready
+AT91C_PIO_PB26            EQU (1 << 26) ;- Pin Controlled by PB26
+AT91C_PB26_TIOB1          EQU (AT91C_PIO_PB26) ;-  Timer Counter 1 Multipurpose Timer I/O Pin B
+AT91C_PB26_RI1            EQU (AT91C_PIO_PB26) ;-  USART 1 Ring Indicator
+AT91C_PIO_PB27            EQU (1 << 27) ;- Pin Controlled by PB27
+AT91C_PB27_TIOA2          EQU (AT91C_PIO_PB27) ;-  Timer Counter 2 Multipurpose Timer I/O Pin A
+AT91C_PB27_PWM0           EQU (AT91C_PIO_PB27) ;-  PWM Channel 0
+AT91C_PIO_PB28            EQU (1 << 28) ;- Pin Controlled by PB28
+AT91C_PB28_TIOB2          EQU (AT91C_PIO_PB28) ;-  Timer Counter 2 Multipurpose Timer I/O Pin B
+AT91C_PB28_PWM1           EQU (AT91C_PIO_PB28) ;-  PWM Channel 1
+AT91C_PIO_PB29            EQU (1 << 29) ;- Pin Controlled by PB29
+AT91C_PB29_PCK1           EQU (AT91C_PIO_PB29) ;-  PMC Programmable Clock Output 1
+AT91C_PB29_PWM2           EQU (AT91C_PIO_PB29) ;-  PWM Channel 2
+AT91C_PIO_PB3             EQU (1 <<  3) ;- Pin Controlled by PB3
+AT91C_PB3_ETX1            EQU (AT91C_PIO_PB3) ;-  Ethernet MAC Transmit Data 1
+AT91C_PIO_PB30            EQU (1 << 30) ;- Pin Controlled by PB30
+AT91C_PB30_PCK2           EQU (AT91C_PIO_PB30) ;-  PMC Programmable Clock Output 2
+AT91C_PB30_PWM3           EQU (AT91C_PIO_PB30) ;-  PWM Channel 3
+AT91C_PIO_PB4             EQU (1 <<  4) ;- Pin Controlled by PB4
+AT91C_PB4_ECRS_ECRSDV     EQU (AT91C_PIO_PB4) ;-  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+AT91C_PIO_PB5             EQU (1 <<  5) ;- Pin Controlled by PB5
+AT91C_PB5_ERX0            EQU (AT91C_PIO_PB5) ;-  Ethernet MAC Receive Data 0
+AT91C_PIO_PB6             EQU (1 <<  6) ;- Pin Controlled by PB6
+AT91C_PB6_ERX1            EQU (AT91C_PIO_PB6) ;-  Ethernet MAC Receive Data 1
+AT91C_PIO_PB7             EQU (1 <<  7) ;- Pin Controlled by PB7
+AT91C_PB7_ERXER           EQU (AT91C_PIO_PB7) ;-  Ethernet MAC Receive Error
+AT91C_PIO_PB8             EQU (1 <<  8) ;- Pin Controlled by PB8
+AT91C_PB8_EMDC            EQU (AT91C_PIO_PB8) ;-  Ethernet MAC Management Data Clock
+AT91C_PIO_PB9             EQU (1 <<  9) ;- Pin Controlled by PB9
+AT91C_PB9_EMDIO           EQU (AT91C_PIO_PB9) ;-  Ethernet MAC Management Data Input/Output
+
+// - *****************************************************************************
+// -               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_ID_FIQ              EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
+AT91C_ID_SYS              EQU ( 1) ;- System Peripheral
+AT91C_ID_PIOA             EQU ( 2) ;- Parallel IO Controller A
+AT91C_ID_PIOB             EQU ( 3) ;- Parallel IO Controller B
+AT91C_ID_SPI0             EQU ( 4) ;- Serial Peripheral Interface 0
+AT91C_ID_SPI1             EQU ( 5) ;- Serial Peripheral Interface 1
+AT91C_ID_US0              EQU ( 6) ;- USART 0
+AT91C_ID_US1              EQU ( 7) ;- USART 1
+AT91C_ID_SSC              EQU ( 8) ;- Serial Synchronous Controller
+AT91C_ID_TWI              EQU ( 9) ;- Two-Wire Interface
+AT91C_ID_PWMC             EQU (10) ;- PWM Controller
+AT91C_ID_UDP              EQU (11) ;- USB Device Port
+AT91C_ID_TC0              EQU (12) ;- Timer Counter 0
+AT91C_ID_TC1              EQU (13) ;- Timer Counter 1
+AT91C_ID_TC2              EQU (14) ;- Timer Counter 2
+AT91C_ID_CAN              EQU (15) ;- Control Area Network Controller
+AT91C_ID_EMAC             EQU (16) ;- Ethernet MAC
+AT91C_ID_ADC              EQU (17) ;- Analog-to-Digital Converter
+AT91C_ID_AES              EQU (18) ;- Advanced Encryption Standard 128-bit
+AT91C_ID_TDES             EQU (19) ;- Triple Data Encryption Standard
+AT91C_ID_20_Reserved      EQU (20) ;- Reserved
+AT91C_ID_21_Reserved      EQU (21) ;- Reserved
+AT91C_ID_22_Reserved      EQU (22) ;- Reserved
+AT91C_ID_23_Reserved      EQU (23) ;- Reserved
+AT91C_ID_24_Reserved      EQU (24) ;- Reserved
+AT91C_ID_25_Reserved      EQU (25) ;- Reserved
+AT91C_ID_26_Reserved      EQU (26) ;- Reserved
+AT91C_ID_27_Reserved      EQU (27) ;- Reserved
+AT91C_ID_28_Reserved      EQU (28) ;- Reserved
+AT91C_ID_29_Reserved      EQU (29) ;- Reserved
+AT91C_ID_IRQ0             EQU (30) ;- Advanced Interrupt Controller (IRQ0)
+AT91C_ID_IRQ1             EQU (31) ;- Advanced Interrupt Controller (IRQ1)
+
+// - *****************************************************************************
+// -               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_BASE_SYS            EQU (0xFFFFF000) ;- (SYS) Base Address
+AT91C_BASE_AIC            EQU (0xFFFFF000) ;- (AIC) Base Address
+AT91C_BASE_PDC_DBGU       EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
+AT91C_BASE_DBGU           EQU (0xFFFFF200) ;- (DBGU) Base Address
+AT91C_BASE_PIOA           EQU (0xFFFFF400) ;- (PIOA) Base Address
+AT91C_BASE_PIOB           EQU (0xFFFFF600) ;- (PIOB) Base Address
+AT91C_BASE_CKGR           EQU (0xFFFFFC20) ;- (CKGR) Base Address
+AT91C_BASE_PMC            EQU (0xFFFFFC00) ;- (PMC) Base Address
+AT91C_BASE_RSTC           EQU (0xFFFFFD00) ;- (RSTC) Base Address
+AT91C_BASE_RTTC           EQU (0xFFFFFD20) ;- (RTTC) Base Address
+AT91C_BASE_PITC           EQU (0xFFFFFD30) ;- (PITC) Base Address
+AT91C_BASE_WDTC           EQU (0xFFFFFD40) ;- (WDTC) Base Address
+AT91C_BASE_VREG           EQU (0xFFFFFD60) ;- (VREG) Base Address
+AT91C_BASE_MC             EQU (0xFFFFFF00) ;- (MC) Base Address
+AT91C_BASE_PDC_SPI1       EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address
+AT91C_BASE_SPI1           EQU (0xFFFE4000) ;- (SPI1) Base Address
+AT91C_BASE_PDC_SPI0       EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address
+AT91C_BASE_SPI0           EQU (0xFFFE0000) ;- (SPI0) Base Address
+AT91C_BASE_PDC_US1        EQU (0xFFFC4100) ;- (PDC_US1) Base Address
+AT91C_BASE_US1            EQU (0xFFFC4000) ;- (US1) Base Address
+AT91C_BASE_PDC_US0        EQU (0xFFFC0100) ;- (PDC_US0) Base Address
+AT91C_BASE_US0            EQU (0xFFFC0000) ;- (US0) Base Address
+AT91C_BASE_PDC_SSC        EQU (0xFFFD4100) ;- (PDC_SSC) Base Address
+AT91C_BASE_SSC            EQU (0xFFFD4000) ;- (SSC) Base Address
+AT91C_BASE_TWI            EQU (0xFFFB8000) ;- (TWI) Base Address
+AT91C_BASE_PWMC_CH3       EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address
+AT91C_BASE_PWMC_CH2       EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address
+AT91C_BASE_PWMC_CH1       EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address
+AT91C_BASE_PWMC_CH0       EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address
+AT91C_BASE_PWMC           EQU (0xFFFCC000) ;- (PWMC) Base Address
+AT91C_BASE_UDP            EQU (0xFFFB0000) ;- (UDP) Base Address
+AT91C_BASE_TC0            EQU (0xFFFA0000) ;- (TC0) Base Address
+AT91C_BASE_TC1            EQU (0xFFFA0040) ;- (TC1) Base Address
+AT91C_BASE_TC2            EQU (0xFFFA0080) ;- (TC2) Base Address
+AT91C_BASE_TCB            EQU (0xFFFA0000) ;- (TCB) Base Address
+AT91C_BASE_CAN_MB0        EQU (0xFFFD0200) ;- (CAN_MB0) Base Address
+AT91C_BASE_CAN_MB1        EQU (0xFFFD0220) ;- (CAN_MB1) Base Address
+AT91C_BASE_CAN_MB2        EQU (0xFFFD0240) ;- (CAN_MB2) Base Address
+AT91C_BASE_CAN_MB3        EQU (0xFFFD0260) ;- (CAN_MB3) Base Address
+AT91C_BASE_CAN_MB4        EQU (0xFFFD0280) ;- (CAN_MB4) Base Address
+AT91C_BASE_CAN_MB5        EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address
+AT91C_BASE_CAN_MB6        EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address
+AT91C_BASE_CAN_MB7        EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address
+AT91C_BASE_CAN            EQU (0xFFFD0000) ;- (CAN) Base Address
+AT91C_BASE_EMAC           EQU (0xFFFDC000) ;- (EMAC) Base Address
+AT91C_BASE_PDC_ADC        EQU (0xFFFD8100) ;- (PDC_ADC) Base Address
+AT91C_BASE_ADC            EQU (0xFFFD8000) ;- (ADC) Base Address
+AT91C_BASE_PDC_AES        EQU (0xFFFA4100) ;- (PDC_AES) Base Address
+AT91C_BASE_AES            EQU (0xFFFA4000) ;- (AES) Base Address
+AT91C_BASE_PDC_TDES       EQU (0xFFFA8100) ;- (PDC_TDES) Base Address
+AT91C_BASE_TDES           EQU (0xFFFA8000) ;- (TDES) Base Address
+
+// - *****************************************************************************
+// -               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// - *****************************************************************************
+AT91C_ISRAM               EQU (0x00200000) ;- Internal SRAM base address
+AT91C_ISRAM_SIZE          EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte)
+AT91C_IFLASH              EQU (0x00100000) ;- Internal ROM base address
+AT91C_IFLASH_SIZE         EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte)
+
+
+
+#endif /* AT91SAM7X256_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c
new file mode 100644
index 0000000..9cbd823
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c
@@ -0,0 +1,51 @@
+//* ----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//* ----------------------------------------------------------------------------
+//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//* ----------------------------------------------------------------------------
+//* File Name           : lib_AT91SAM7X256.h
+//* Object              : AT91SAM7X256 inlined functions
+//* Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
+//*
+//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005//
+//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
+//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
+//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
+//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
+//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
+//* CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
+//* CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
+//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
+//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
+//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
+//* CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
+//* CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
+//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
+//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
+//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
+//* ----------------------------------------------------------------------------
+
+
+#include "AT91SAM7X256.h"
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
new file mode 100644
index 0000000..e66b4e1
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
@@ -0,0 +1,4558 @@
+//* ----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//* ----------------------------------------------------------------------------
+//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//* ----------------------------------------------------------------------------
+//* File Name           : lib_AT91SAM7X256.h
+//* Object              : AT91SAM7X256 inlined functions
+//* Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
+//*
+//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005//
+//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
+//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
+//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
+//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
+//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
+//* CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
+//* CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
+//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
+//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
+//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
+//* CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
+//* CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
+//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
+//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
+//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
+//* ----------------------------------------------------------------------------
+
+#ifndef lib_AT91SAM7X256_H
+#define lib_AT91SAM7X256_H
+
+/* *****************************************************************************
+                SOFTWARE API FOR AIC
+   ***************************************************************************** */
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_ConfigureIt (
+	AT91PS_AIC pAic,  // \arg pointer to the AIC registers
+	unsigned int irq_id,     // \arg interrupt number to initialize
+	unsigned int priority,   // \arg priority to give to the interrupt
+	unsigned int src_type,   // \arg activation and sense of activation
+	void (*newHandler) (void) ) // \arg address of the interrupt handler
+{
+	unsigned int oldHandler;
+    unsigned int mask ;
+
+    oldHandler = pAic->AIC_SVR[irq_id];
+
+    mask = 0x1 << irq_id ;
+    //* Disable the interrupt on the interrupt controller
+    pAic->AIC_IDCR = mask ;
+    //* Save the interrupt handler routine pointer and the interrupt priority
+    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
+    //* Store the Source Mode Register
+    pAic->AIC_SMR[irq_id] = src_type | priority  ;
+    //* Clear the interrupt on the interrupt controller
+    pAic->AIC_ICCR = mask ;
+
+	return oldHandler;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_EnableIt
+//* \brief Enable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_EnableIt (
+	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
+	unsigned int irq_id ) // \arg interrupt number to initialize
+{
+    //* Enable the interrupt on the interrupt controller
+    pAic->AIC_IECR = 0x1 << irq_id ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_DisableIt
+//* \brief Disable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_DisableIt (
+	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
+	unsigned int irq_id ) // \arg interrupt number to initialize
+{
+    unsigned int mask = 0x1 << irq_id;
+    //* Disable the interrupt on the interrupt controller
+    pAic->AIC_IDCR = mask ;
+    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+    pAic->AIC_ICCR = mask ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ClearIt
+//* \brief Clear corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_ClearIt (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg interrupt number to initialize
+{
+    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+    pAic->AIC_ICCR = (0x1 << irq_id);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_AcknowledgeIt
+//* \brief Acknowledge corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_AcknowledgeIt (
+	AT91PS_AIC pAic)     // \arg pointer to the AIC registers
+{
+    pAic->AIC_EOICR = pAic->AIC_EOICR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_SetExceptionVector
+//* \brief Configure vector handler
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_SetExceptionVector (
+	unsigned int *pVector, // \arg pointer to the AIC registers
+	void (*Handler) () )   // \arg Interrupt Handler
+{
+	unsigned int oldVector = *pVector;
+
+	if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
+		*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
+	else
+		*pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
+
+	return oldVector;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_Trig
+//* \brief Trig an IT
+//*----------------------------------------------------------------------------
+__inline void  AT91F_AIC_Trig (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg interrupt number
+{
+	pAic->AIC_ISCR = (0x1 << irq_id) ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_IsActive
+//* \brief Test if an IT is active
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_IsActive (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg Interrupt Number
+{
+	return (pAic->AIC_ISR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_IsPending
+//* \brief Test if an IT is pending
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_IsPending (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg Interrupt Number
+{
+	return (pAic->AIC_IPR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_Open
+//* \brief Set exception vectors and AIC registers to default values
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Open(
+	AT91PS_AIC pAic,        // \arg pointer to the AIC registers
+	void (*IrqHandler) (),  // \arg Default IRQ vector exception
+	void (*FiqHandler) (),  // \arg Default FIQ vector exception
+	void (*DefaultHandler)  (), // \arg Default Handler set in ISR
+	void (*SpuriousHandler) (), // \arg Default Spurious Handler
+	unsigned int protectMode)   // \arg Debug Control Register
+{
+	int i;
+
+	// Disable all interrupts and set IVR to the default handler
+	for (i = 0; i < 32; ++i) {
+		AT91F_AIC_DisableIt(pAic, i);
+		AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
+	}
+
+	// Set the IRQ exception vector
+	AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
+	// Set the Fast Interrupt exception vector
+	AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
+
+	pAic->AIC_SPU = (unsigned int) SpuriousHandler;
+	pAic->AIC_DCR = protectMode;
+}
+/* *****************************************************************************
+                SOFTWARE API FOR PDC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetNextRx
+//* \brief Set the next receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextRx (
+	AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
+	char *address,       // \arg address to the next bloc to be received
+	unsigned int bytes)  // \arg number of bytes to be received
+{
+	pPDC->PDC_RNPR = (unsigned int) address;
+	pPDC->PDC_RNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetNextTx
+//* \brief Set the next transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextTx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be transmitted
+	unsigned int bytes)    // \arg number of bytes to be transmitted
+{
+	pPDC->PDC_TNPR = (unsigned int) address;
+	pPDC->PDC_TNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetRx
+//* \brief Set the receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetRx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be received
+	unsigned int bytes)    // \arg number of bytes to be received
+{
+	pPDC->PDC_RPR = (unsigned int) address;
+	pPDC->PDC_RCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetTx
+//* \brief Set the transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetTx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be transmitted
+	unsigned int bytes)    // \arg number of bytes to be transmitted
+{
+	pPDC->PDC_TPR = (unsigned int) address;
+	pPDC->PDC_TCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_EnableTx
+//* \brief Enable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableTx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_EnableRx
+//* \brief Enable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableRx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_DisableTx
+//* \brief Disable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableTx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_DisableRx
+//* \brief Disable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableRx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsTxEmpty
+//* \brief Test if the current transfer descriptor has been sent
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_TCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsNextTxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_TNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsRxEmpty
+//* \brief Test if the current transfer descriptor has been filled
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_RCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsNextRxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_RNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_Open
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Open (
+	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+{
+    //* Disable the RX and TX PDC transfer requests
+	AT91F_PDC_DisableRx(pPDC);
+	AT91F_PDC_DisableTx(pPDC);
+
+	//* Reset all Counter register Next buffer first
+	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+    //* Enable the RX and TX PDC transfer requests
+	AT91F_PDC_EnableRx(pPDC);
+	AT91F_PDC_EnableTx(pPDC);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_Close
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Close (
+	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+{
+    //* Disable the RX and TX PDC transfer requests
+	AT91F_PDC_DisableRx(pPDC);
+	AT91F_PDC_DisableTx(pPDC);
+
+	//* Reset all Counter register Next buffer first
+	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SendFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_SendFrame(
+	AT91PS_PDC pPDC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	if (AT91F_PDC_IsTxEmpty(pPDC)) {
+		//* Buffer and next buffer can be initialized
+		AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
+		AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
+		return 2;
+	}
+	else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
+		//* Only one buffer can be initialized
+		AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
+		return 1;
+	}
+	else {
+		//* All buffer are in use...
+		return 0;
+	}
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_ReceiveFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_ReceiveFrame (
+	AT91PS_PDC pPDC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	if (AT91F_PDC_IsRxEmpty(pPDC)) {
+		//* Buffer and next buffer can be initialized
+		AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
+		AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
+		return 2;
+	}
+	else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
+		//* Only one buffer can be initialized
+		AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
+		return 1;
+	}
+	else {
+		//* All buffer are in use...
+		return 0;
+	}
+}
+/* *****************************************************************************
+                SOFTWARE API FOR DBGU
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_InterruptEnable
+//* \brief Enable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptEnable(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  dbgu interrupt to be enabled
+{
+        pDbgu->DBGU_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_InterruptDisable
+//* \brief Disable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptDisable(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  dbgu interrupt to be disabled
+{
+        pDbgu->DBGU_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_GetInterruptMaskStatus
+//* \brief Return DBGU Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
+        AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
+{
+        return pDbgu->DBGU_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_IsInterruptMasked
+//* \brief Test if DBGU Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_DBGU_IsInterruptMasked(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PIO
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgPeriph
+//* \brief Enable pins to be drived by peripheral
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPeriph(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int periphAEnable,  // \arg PERIPH A to enable
+	unsigned int periphBEnable)  // \arg PERIPH B to enable
+
+{
+	pPio->PIO_ASR = periphAEnable;
+	pPio->PIO_BSR = periphBEnable;
+	pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgOutput
+//* \brief Enable PIO in output mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOutput(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int pioEnable)      // \arg PIO to be enabled
+{
+	pPio->PIO_PER = pioEnable; // Set in PIO mode
+	pPio->PIO_OER = pioEnable; // Configure in Output
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgInput
+//* \brief Enable PIO in input mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInput(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int inputEnable)      // \arg PIO to be enabled
+{
+	// Disable output
+	pPio->PIO_ODR  = inputEnable;
+	pPio->PIO_PER  = inputEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgOpendrain
+//* \brief Configure PIO in open drain
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOpendrain(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int multiDrvEnable) // \arg pio to be configured in open drain
+{
+	// Configure the multi-drive option
+	pPio->PIO_MDDR = ~multiDrvEnable;
+	pPio->PIO_MDER = multiDrvEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgPullup
+//* \brief Enable pullup on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPullup(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int pullupEnable)   // \arg enable pullup on PIO
+{
+		// Connect or not Pullup
+	pPio->PIO_PPUDR = ~pullupEnable;
+	pPio->PIO_PPUER = pullupEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgDirectDrive
+//* \brief Enable direct drive on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgDirectDrive(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int directDrive)    // \arg PIO to be configured with direct drive
+
+{
+	// Configure the Direct Drive
+	pPio->PIO_OWDR  = ~directDrive;
+	pPio->PIO_OWER  = directDrive;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgInputFilter
+//* \brief Enable input filter on input PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInputFilter(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int inputFilter)    // \arg PIO to be configured with input filter
+
+{
+	// Configure the Direct Drive
+	pPio->PIO_IFDR  = ~inputFilter;
+	pPio->PIO_IFER  = inputFilter;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInput
+//* \brief Return PIO input value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
+	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+	return pPio->PIO_PDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInputSet
+//* \brief Test if PIO is input flag is active
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputSet(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PIO_GetInput(pPio) & flag);
+}
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_SetOutput
+//* \brief Set to 1 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_SetOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be set
+{
+	pPio->PIO_SODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_ClearOutput
+//* \brief Set to 0 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ClearOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be cleared
+{
+	pPio->PIO_CODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_ForceOutput
+//* \brief Force output when Direct drive option is enabled
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ForceOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be forced
+{
+	pPio->PIO_ODSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Enable
+//* \brief Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Enable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be enabled 
+{
+        pPio->PIO_PER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Disable
+//* \brief Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Disable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be disabled 
+{
+        pPio->PIO_PDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetStatus
+//* \brief Return PIO Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_PSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsSet
+//* \brief Test if PIO is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputEnable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output to be enabled
+{
+        pPio->PIO_OER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputDisable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output to be disabled
+{
+        pPio->PIO_ODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputStatus
+//* \brief Return PIO Output Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_OSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOuputSet
+//* \brief Test if PIO Output is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InputFilterEnable
+//* \brief Input Filter Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio input filter to be enabled
+{
+        pPio->PIO_IFER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InputFilterDisable
+//* \brief Input Filter Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio input filter to be disabled
+{
+        pPio->PIO_IFDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInputFilterStatus
+//* \brief Return PIO Input Filter Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_IFSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInputFilterSet
+//* \brief Test if PIO Input filter is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputFilterSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputDataStatus
+//* \brief Return PIO Output Data Status 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status 
+	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ODSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InterruptEnable
+//* \brief Enable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio interrupt to be enabled
+{
+        pPio->PIO_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InterruptDisable
+//* \brief Disable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio interrupt to be disabled
+{
+        pPio->PIO_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInterruptMaskStatus
+//* \brief Return PIO Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInterruptStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInterruptMasked
+//* \brief Test if PIO Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptMasked(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInterruptSet
+//* \brief Test if PIO Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_MultiDriverEnable
+//* \brief Multi Driver Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be enabled
+{
+        pPio->PIO_MDER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_MultiDriverDisable
+//* \brief Multi Driver Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be disabled
+{
+        pPio->PIO_MDDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetMultiDriverStatus
+//* \brief Return PIO Multi Driver Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_MDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsMultiDriverSet
+//* \brief Test if PIO MultiDriver is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsMultiDriverSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_A_RegisterSelection
+//* \brief PIO A Register Selection 
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_A_RegisterSelection(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio A register selection
+{
+        pPio->PIO_ASR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_B_RegisterSelection
+//* \brief PIO B Register Selection 
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_B_RegisterSelection(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio B register selection 
+{
+        pPio->PIO_BSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Get_AB_RegisterStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ABSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsAB_RegisterSet
+//* \brief Test if PIO AB Register is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsAB_RegisterSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputWriteEnable
+//* \brief Output Write Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output write to be enabled
+{
+        pPio->PIO_OWER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputWriteDisable
+//* \brief Output Write Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output write to be disabled
+{
+        pPio->PIO_OWDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputWriteStatus
+//* \brief Return PIO Output Write Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_OWSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOutputWriteSet
+//* \brief Test if PIO OutputWrite is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputWriteSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetCfgPullup
+//* \brief Return PIO Configuration Pullup
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup 
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_PPUSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOutputDataStatusSet
+//* \brief Test if PIO Output Data Status is Set 
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputDataStatusSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsCfgPullupStatusSet
+//* \brief Test if PIO Configuration Pullup Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsCfgPullupStatusSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PMC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgSysClkEnableReg
+//* \brief Configure the System Clock Enable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkEnableReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	//* Write to the SCER register
+	pPMC->PMC_SCER = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgSysClkDisableReg
+//* \brief Configure the System Clock Disable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkDisableReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	//* Write to the SCDR register
+	pPMC->PMC_SCDR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetSysClkStatusReg
+//* \brief Return the System Clock Status Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
+	AT91PS_PMC pPMC // pointer to a CAN controller
+	)
+{
+	return pPMC->PMC_SCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnablePeriphClock
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePeriphClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int periphIds)  // \arg IDs of peripherals to enable
+{
+	pPMC->PMC_PCER = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisablePeriphClock
+//* \brief Disable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePeriphClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int periphIds)  // \arg IDs of peripherals to enable
+{
+	pPMC->PMC_PCDR = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetPeriphClock
+//* \brief Get peripheral clock status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetPeriphClock (
+	AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+	return pPMC->PMC_PCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_CfgMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscillatorReg (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int mode)
+{
+	pCKGR->CKGR_MOR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	return pCKGR->CKGR_MOR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_EnableMainOscillator
+//* \brief Enable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_EnableMainOscillator(
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_DisableMainOscillator
+//* \brief Disable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_DisableMainOscillator (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
+//* \brief Cfg MOR Register according to the main osc startup time
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
+	pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainClockFreqReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	return pCKGR->CKGR_MCFR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainClock
+//* \brief Return Main clock in Hz
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClock (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgMCKReg
+//* \brief Cfg Master Clock Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgMCKReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	pPMC->PMC_MCKR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetMCKReg
+//* \brief Return Master Clock Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMCKReg(
+	AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+	return pPMC->PMC_MCKR;
+}
+
+//*------------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetMasterClock
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7
+//*------------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMasterClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	unsigned int reg = pPMC->PMC_MCKR;
+	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
+	unsigned int pllDivider, pllMultiplier;
+
+	switch (reg & AT91C_PMC_CSS) {
+		case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
+			return slowClock / prescaler;
+		case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
+			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
+		case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
+			reg = pCKGR->CKGR_PLLR;
+			pllDivider    = (reg  & AT91C_CKGR_DIV);
+			pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
+			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
+	}
+	return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePCK (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
+	unsigned int mode)
+{
+	pPMC->PMC_PCKR[pck] = mode;
+	pPMC->PMC_SCER = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePCK (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
+{
+	pPMC->PMC_SCDR = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnableIt
+//* \brief Enable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnableIt (
+	AT91PS_PMC pPMC,     // pointer to a PMC controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pPMC->PMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisableIt
+//* \brief Disable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisableIt (
+	AT91PS_PMC pPMC, // pointer to a PMC controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pPMC->PMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetStatus
+//* \brief Return PMC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
+	AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+	return pPMC->PMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetInterruptMaskStatus
+//* \brief Return PMC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
+	AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+	return pPMC->PMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_IsInterruptMasked
+//* \brief Test if PMC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsInterruptMasked(
+        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_IsStatusSet
+//* \brief Test if PMC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsStatusSet(
+        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PMC_GetStatus(pPMC) & flag);
+}/* *****************************************************************************
+                SOFTWARE API FOR RSTC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTSoftReset
+//* \brief Start Software Reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSoftReset(
+        AT91PS_RSTC pRSTC,
+        unsigned int reset)
+{
+	pRSTC->RSTC_RCR = (0xA5000000 | reset);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTSetMode
+//* \brief Set Reset Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSetMode(
+        AT91PS_RSTC pRSTC,
+        unsigned int mode)
+{
+	pRSTC->RSTC_RMR = (0xA5000000 | mode);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTGetMode
+//* \brief Get Reset Mode
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetMode(
+        AT91PS_RSTC pRSTC)
+{
+	return (pRSTC->RSTC_RMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTGetStatus
+//* \brief Get Reset Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetStatus(
+        AT91PS_RSTC pRSTC)
+{
+	return (pRSTC->RSTC_RSR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTIsSoftRstActive
+//* \brief Return !=0 if software reset is still not completed
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTIsSoftRstActive(
+        AT91PS_RSTC pRSTC)
+{
+	return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR RTTC
+   ***************************************************************************** */
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_SetRTT_TimeBase()
+//* \brief  Set the RTT prescaler according to the TimeBase in ms
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetTimeBase(
+        AT91PS_RTTC pRTTC, 
+        unsigned int ms)
+{
+	if (ms > 2000)
+		return 1;   // AT91C_TIME_OUT_OF_RANGE
+	pRTTC->RTTC_RTMR &= ~0xFFFF;	
+	pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);	
+	return 0;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTSetPrescaler()
+//* \brief  Set the new prescaler value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetPrescaler(
+        AT91PS_RTTC pRTTC, 
+        unsigned int rtpres)
+{
+	pRTTC->RTTC_RTMR &= ~0xFFFF;	
+	pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);	
+	return (pRTTC->RTTC_RTMR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTRestart()
+//* \brief  Restart the RTT prescaler
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTRestart(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;	
+}
+
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetAlarmINT()
+//* \brief  Enable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ClearAlarmINT()
+//* \brief  Disable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearAlarmINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetRttIncINT()
+//* \brief  Enable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetRttIncINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ClearRttIncINT()
+//* \brief  Disable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearRttIncINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetAlarmValue()
+//* \brief  Set RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmValue(
+        AT91PS_RTTC pRTTC, unsigned int alarm)
+{
+	pRTTC->RTTC_RTAR = alarm;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_GetAlarmValue()
+//* \brief  Get RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetAlarmValue(
+        AT91PS_RTTC pRTTC)
+{
+	return(pRTTC->RTTC_RTAR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTGetStatus()
+//* \brief  Read the RTT status
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetStatus(
+        AT91PS_RTTC pRTTC)
+{
+	return(pRTTC->RTTC_RTSR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ReadValue()
+//* \brief  Read the RTT value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTReadValue(
+        AT91PS_RTTC pRTTC)
+{
+        register volatile unsigned int val1,val2;
+	do
+	{
+		val1 = pRTTC->RTTC_RTVR;
+		val2 = pRTTC->RTTC_RTVR;
+	}	
+	while(val1 != val2);
+	return(val1);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR PITC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITInit
+//* \brief System timer init : period in µsecond, system clock freq in MHz
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITInit(
+        AT91PS_PITC pPITC,
+        unsigned int period,
+        unsigned int pit_frequency)
+{
+	pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
+	pPITC->PITC_PIMR |= AT91C_PITC_PITEN;	 
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITSetPIV
+//* \brief Set the PIT Periodic Interval Value 
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITSetPIV(
+        AT91PS_PITC pPITC,
+        unsigned int piv)
+{
+	pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITEnableInt
+//* \brief Enable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITEnableInt(
+        AT91PS_PITC pPITC)
+{
+	pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;	 
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITDisableInt
+//* \brief Disable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITDisableInt(
+        AT91PS_PITC pPITC)
+{
+	pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;	 
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetMode
+//* \brief Read PIT mode register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetMode(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetStatus
+//* \brief Read PIT status register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetStatus(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PISR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetPIIR
+//* \brief Read PIT CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIIR(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIIR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetPIVR
+//* \brief Read System timer CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIVR(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIVR);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR WDTC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTSetMode
+//* \brief Set Watchdog Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTSetMode(
+        AT91PS_WDTC pWDTC,
+        unsigned int Mode)
+{
+	pWDTC->WDTC_WDMR = Mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTRestart
+//* \brief Restart Watchdog
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTRestart(
+        AT91PS_WDTC pWDTC)
+{
+	pWDTC->WDTC_WDCR = 0xA5000001;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTSGettatus
+//* \brief Get Watchdog Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTSGettatus(
+        AT91PS_WDTC pWDTC)
+{
+	return(pWDTC->WDTC_WDSR & 0x3);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTGetPeriod
+//* \brief Translate ms into Watchdog Compatible value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)
+{
+	if ((ms < 4) || (ms > 16000))
+		return 0;
+	return((ms << 8) / 1000);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR VREG
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_Enable_LowPowerMode
+//* \brief Enable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Enable_LowPowerMode(
+        AT91PS_VREG pVREG)
+{
+	pVREG->VREG_MR |= AT91C_VREG_PSTDBY;	 
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_Disable_LowPowerMode
+//* \brief Disable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Disable_LowPowerMode(
+        AT91PS_VREG pVREG)
+{
+	pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;	 
+}/* *****************************************************************************
+                SOFTWARE API FOR MC
+   ***************************************************************************** */
+
+#define AT91C_MC_CORRECT_KEY  ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_Remap
+//* \brief Make Remap
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_Remap (void)     //  
+{
+    AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
+    
+    pMC->MC_RCR = AT91C_MC_RCB;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_CfgModeReg
+//* \brief Configure the EFC Mode Register of the MC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_CfgModeReg (
+	AT91PS_MC pMC, // pointer to a MC controller
+	unsigned int mode)        // mode register 
+{
+	// Write to the FMR register
+	pMC->MC_FMR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_GetModeReg
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetModeReg(
+	AT91PS_MC pMC) // pointer to a MC controller
+{
+	return pMC->MC_FMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_ComputeFMCN
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
+	int master_clock) // master clock in Hz
+{
+	return (master_clock/1000000 +2);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_PerformCmd
+//* \brief Perform EFC Command
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_PerformCmd (
+	AT91PS_MC pMC, // pointer to a MC controller
+    unsigned int transfer_cmd)
+{
+	pMC->MC_FCR = transfer_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_GetStatus
+//* \brief Return MC EFC Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetStatus(
+	AT91PS_MC pMC) // pointer to a MC controller
+{
+	return pMC->MC_FSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_IsInterruptMasked
+//* \brief Test if EFC MC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
+        AT91PS_MC pMC,   // \arg  pointer to a MC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_IsInterruptSet
+//* \brief Test if EFC MC Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
+        AT91PS_MC pMC,   // \arg  pointer to a MC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_MC_EFC_GetStatus(pMC) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR SPI
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Open
+//* \brief Open a SPI Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_Open (
+        const unsigned int null)  // \arg
+{
+        /* NOT DEFINED AT THIS MOMENT */
+        return ( 0 );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgCs
+//* \brief Configure SPI chip select register
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgCs (
+	AT91PS_SPI pSPI,     // pointer to a SPI controller
+	int cs,     // SPI cs number (0 to 3)
+ 	int val)   //  chip select register
+{
+	//* Write to the CSR register
+	*(pSPI->SPI_CSR + cs) = val;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_EnableIt
+//* \brief Enable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_EnableIt (
+	AT91PS_SPI pSPI,     // pointer to a SPI controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pSPI->SPI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_DisableIt
+//* \brief Disable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_DisableIt (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pSPI->SPI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Reset
+//* \brief Reset the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Reset (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SWRST;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Enable
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Enable (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SPIEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Disable
+//* \brief Disable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Disable (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgMode
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgMode (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	int mode)        // mode register 
+{
+	//* Write to the MR register
+	pSPI->SPI_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgPCS
+//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPCS (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	char PCS_Device) // PCS of the Device
+{	
+ 	//* Write to the MR register
+	pSPI->SPI_MR &= 0xFFF0FFFF;
+	pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_ReceiveFrame (
+	AT91PS_SPI pSPI,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pSPI->SPI_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_SendFrame(
+	AT91PS_SPI pSPI,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pSPI->SPI_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Close
+//* \brief Close SPI: disable IT disable transfert, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Close (
+	AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
+{
+    //* Reset all the Chip Select register
+    pSPI->SPI_CSR[0] = 0 ;
+    pSPI->SPI_CSR[1] = 0 ;
+    pSPI->SPI_CSR[2] = 0 ;
+    pSPI->SPI_CSR[3] = 0 ;
+
+    //* Reset the SPI mode
+    pSPI->SPI_MR = 0  ;
+
+    //* Disable all interrupts
+    pSPI->SPI_IDR = 0xFFFFFFFF ;
+
+    //* Abort the Peripheral Data Transfers
+    AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
+
+    //* Disable receiver and transmitter and stop any activity immediately
+    pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_PutChar (
+	AT91PS_SPI pSPI,
+	unsigned int character,
+             unsigned int cs_number )
+{
+    unsigned int value_for_cs;
+    value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number
+    pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_GetChar (
+	const AT91PS_SPI pSPI)
+{
+    return((pSPI->SPI_RDR) & 0xFFFF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_GetInterruptMaskStatus
+//* \brief Return SPI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
+        AT91PS_SPI pSpi) // \arg  pointer to a SPI controller
+{
+        return pSpi->SPI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_IsInterruptMasked
+//* \brief Test if SPI Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_IsInterruptMasked(
+        AT91PS_SPI pSpi,   // \arg  pointer to a SPI controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR USART
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Baudrate
+//* \brief Calculate the baudrate
+//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
+                        AT91C_US_NBSTOP_1_BIT + \
+                        AT91C_US_PAR_NONE + \
+                        AT91C_US_CHRL_8_BITS + \
+                        AT91C_US_CLKS_CLOCK )
+
+//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
+                            AT91C_US_NBSTOP_1_BIT + \
+                            AT91C_US_PAR_NONE + \
+                            AT91C_US_CHRL_8_BITS + \
+                            AT91C_US_CLKS_EXT )
+
+//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
+                       AT91C_US_USMODE_NORMAL + \
+                       AT91C_US_NBSTOP_1_BIT + \
+                       AT91C_US_PAR_NONE + \
+                       AT91C_US_CHRL_8_BITS + \
+                       AT91C_US_CLKS_CLOCK )
+
+//* SCK used Label
+#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
+
+//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
+#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
+					   		 AT91C_US_CLKS_CLOCK +\
+                       		 AT91C_US_NBSTOP_1_BIT + \
+                       		 AT91C_US_PAR_EVEN + \
+                       		 AT91C_US_CHRL_8_BITS + \
+                       		 AT91C_US_CKLO +\
+                       		 AT91C_US_OVER)
+
+//* Standard IRDA mode
+#define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \
+                            AT91C_US_NBSTOP_1_BIT + \
+                            AT91C_US_PAR_NONE + \
+                            AT91C_US_CHRL_8_BITS + \
+                            AT91C_US_CLKS_CLOCK )
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Baudrate
+//* \brief Caluculate baud_value according to the main clock and the baud rate
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Baudrate (
+	const unsigned int main_clock, // \arg peripheral clock
+	const unsigned int baud_rate)  // \arg UART baudrate
+{
+	unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
+	if ((baud_value % 10) >= 5)
+		baud_value = (baud_value / 10) + 1;
+	else
+		baud_value /= 10;
+	return baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetBaudrate (
+	AT91PS_USART pUSART,    // \arg pointer to a USART controller
+	unsigned int mainClock, // \arg peripheral clock
+	unsigned int speed)     // \arg UART baudrate
+{
+	//* Define the baud rate divisor register
+	pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetTimeguard
+//* \brief Set USART timeguard
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetTimeguard (
+	AT91PS_USART pUSART,    // \arg pointer to a USART controller
+	unsigned int timeguard) // \arg timeguard value
+{
+	//* Write the Timeguard Register
+	pUSART->US_TTGR = timeguard ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableIt
+//* \brief Enable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableIt (
+	AT91PS_USART pUSART, // \arg pointer to a USART controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pUSART->US_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableIt
+//* \brief Disable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableIt (
+	AT91PS_USART pUSART, // \arg pointer to a USART controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IER register
+	pUSART->US_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Configure
+//* \brief Configure USART
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Configure (
+	AT91PS_USART pUSART,     // \arg pointer to a USART controller
+	unsigned int mainClock,  // \arg peripheral clock
+	unsigned int mode ,      // \arg mode Register to be programmed
+	unsigned int baudRate ,  // \arg baudrate to be programmed
+	unsigned int timeguard ) // \arg timeguard to be programmed
+{
+    //* Disable interrupts
+    pUSART->US_IDR = (unsigned int) -1;
+
+    //* Reset receiver and transmitter
+    pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
+
+	//* Define the baud rate divisor register
+	AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
+
+	//* Write the Timeguard Register
+	AT91F_US_SetTimeguard(pUSART, timeguard);
+
+    //* Clear Transmit and Receive Counters
+    AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
+
+    //* Define the USART mode
+    pUSART->US_MR = mode  ;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableRx
+//* \brief Enable receiving characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Enable receiver
+    pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableTx
+//* \brief Enable sending characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Enable  transmitter
+    pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ResetRx
+//* \brief Reset Receiver and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+	//* Reset receiver
+	pUSART->US_CR = AT91C_US_RSTRX;
+    //* Re-Enable receiver
+    pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ResetTx
+//* \brief Reset Transmitter and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+	//* Reset transmitter
+	pUSART->US_CR = AT91C_US_RSTTX;
+    //* Enable transmitter
+    pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableRx
+//* \brief Disable Receiver
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Disable receiver
+    pUSART->US_CR = AT91C_US_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableTx
+//* \brief Disable Transmitter
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Disable transmitter
+    pUSART->US_CR = AT91C_US_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Close
+//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Close (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Reset the baud rate divisor register
+    pUSART->US_BRGR = 0 ;
+
+    //* Reset the USART mode
+    pUSART->US_MR = 0  ;
+
+    //* Reset the Timeguard Register
+    pUSART->US_TTGR = 0;
+
+    //* Disable all interrupts
+    pUSART->US_IDR = 0xFFFFFFFF ;
+
+    //* Abort the Peripheral Data Transfers
+    AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
+
+    //* Disable receiver and transmitter and stop any activity immediately
+    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_TxReady
+//* \brief Return 1 if a character can be written in US_THR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_TxReady (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR & AT91C_US_TXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_RxReady
+//* \brief Return 1 if a character can be read in US_RHR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_RxReady (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR & AT91C_US_RXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Error
+//* \brief Return the error flag
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Error (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR &
+    	(AT91C_US_OVRE |  // Overrun error
+    	 AT91C_US_FRAME | // Framing error
+    	 AT91C_US_PARE));  // Parity error
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_PutChar (
+	AT91PS_USART pUSART,
+	int character )
+{
+    pUSART->US_THR = (character & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_US_GetChar (
+	const AT91PS_USART pUSART)
+{
+    return((pUSART->US_RHR) & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_SendFrame(
+	AT91PS_USART pUSART,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pUSART->US_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_ReceiveFrame (
+	AT91PS_USART pUSART,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pUSART->US_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetIrdaFilter
+//* \brief Set the value of IrDa filter tregister
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetIrdaFilter (
+	AT91PS_USART pUSART,
+	unsigned char value
+)
+{
+	pUSART->US_IF = value;
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR SSC
+   ***************************************************************************** */
+//* Define the standard I2S mode configuration
+
+//* Configuration to set in the SSC Transmit Clock Mode Register
+//* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
+//* 			  nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+									   AT91C_SSC_CKS_DIV   +\
+                            		   AT91C_SSC_CKO_CONTINOUS      +\
+                            		   AT91C_SSC_CKG_NONE    +\
+                                       AT91C_SSC_START_FALL_RF +\
+                           			   AT91C_SSC_STTOUT  +\
+                            		   ((1<<16) & AT91C_SSC_STTDLY) +\
+                            		   ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
+
+
+//* Configuration to set in the SSC Transmit Frame Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* 			 nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+									(nb_bit_by_slot-1)  +\
+                            		AT91C_SSC_MSBF   +\
+                            		(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
+                            		(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
+                            		AT91C_SSC_FSOS_NEGATIVE)
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_SetBaudrate (
+        AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
+        unsigned int mainClock, // \arg peripheral clock
+        unsigned int speed)     // \arg SSC baudrate
+{
+        unsigned int baud_value;
+        //* Define the baud rate divisor register
+        if (speed == 0)
+           baud_value = 0;
+        else
+        {
+           baud_value = (unsigned int) (mainClock * 10)/(2*speed);
+           if ((baud_value % 10) >= 5)
+                  baud_value = (baud_value / 10) + 1;
+           else
+                  baud_value /= 10;
+        }
+
+        pSSC->SSC_CMR = baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_Configure
+//* \brief Configure SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_Configure (
+             AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
+             unsigned int syst_clock,  // \arg System Clock Frequency
+             unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
+             unsigned int clock_rx,    // \arg Receiver Clock Parameters
+             unsigned int mode_rx,     // \arg mode Register to be programmed
+             unsigned int clock_tx,    // \arg Transmitter Clock Parameters
+             unsigned int mode_tx)     // \arg mode Register to be programmed
+{
+    //* Disable interrupts
+	pSSC->SSC_IDR = (unsigned int) -1;
+
+    //* Reset receiver and transmitter
+	pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
+
+    //* Define the Clock Mode Register
+	AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
+
+     //* Write the Receive Clock Mode Register
+	pSSC->SSC_RCMR =  clock_rx;
+
+     //* Write the Transmit Clock Mode Register
+	pSSC->SSC_TCMR =  clock_tx;
+
+     //* Write the Receive Frame Mode Register
+	pSSC->SSC_RFMR =  mode_rx;
+
+     //* Write the Transmit Frame Mode Register
+	pSSC->SSC_TFMR =  mode_tx;
+
+    //* Clear Transmit and Receive Counters
+	AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
+
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableRx
+//* \brief Enable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableRx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Enable receiver
+    pSSC->SSC_CR = AT91C_SSC_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableRx
+//* \brief Disable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableRx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Disable receiver
+    pSSC->SSC_CR = AT91C_SSC_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableTx
+//* \brief Enable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableTx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Enable  transmitter
+    pSSC->SSC_CR = AT91C_SSC_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableTx
+//* \brief Disable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableTx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Disable  transmitter
+    pSSC->SSC_CR = AT91C_SSC_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableIt
+//* \brief Enable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableIt (
+	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pSSC->SSC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableIt
+//* \brief Disable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableIt (
+	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pSSC->SSC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_ReceiveFrame (
+	AT91PS_SSC pSSC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pSSC->SSC_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_SendFrame(
+	AT91PS_SSC pSSC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pSSC->SSC_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_GetInterruptMaskStatus
+//* \brief Return SSC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
+        AT91PS_SSC pSsc) // \arg  pointer to a SSC controller
+{
+        return pSsc->SSC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_IsInterruptMasked
+//* \brief Test if SSC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_SSC_IsInterruptMasked(
+        AT91PS_SSC pSsc,   // \arg  pointer to a SSC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TWI
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_EnableIt
+//* \brief Enable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_EnableIt (
+	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pTWI->TWI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_DisableIt
+//* \brief Disable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_DisableIt (
+	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pTWI->TWI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_Configure
+//* \brief Configure TWI in master mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \arg pointer to a TWI controller
+{
+    //* Disable interrupts
+	pTWI->TWI_IDR = (unsigned int) -1;
+
+    //* Reset peripheral
+	pTWI->TWI_CR = AT91C_TWI_SWRST;
+
+	//* Set Master mode
+	pTWI->TWI_CR = AT91C_TWI_MSEN;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_GetInterruptMaskStatus
+//* \brief Return TWI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
+        AT91PS_TWI pTwi) // \arg  pointer to a TWI controller
+{
+        return pTwi->TWI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_IsInterruptMasked
+//* \brief Test if TWI Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_TWI_IsInterruptMasked(
+        AT91PS_TWI pTwi,   // \arg  pointer to a TWI controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PWMC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_GetStatus
+//* \brief Return PWM Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
+	AT91PS_PWMC pPWM) // pointer to a PWM controller
+{
+	return pPWM->PWMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_InterruptEnable
+//* \brief Enable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptEnable(
+        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  PWM interrupt to be enabled
+{
+        pPwm->PWMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_InterruptDisable
+//* \brief Disable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptDisable(
+        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  PWM interrupt to be disabled
+{
+        pPwm->PWMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_GetInterruptMaskStatus
+//* \brief Return PWM Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
+        AT91PS_PWMC pPwm) // \arg  pointer to a PWM controller
+{
+        return pPwm->PWMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_IsInterruptMasked
+//* \brief Test if PWM Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsInterruptMasked(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_IsStatusSet
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsStatusSet(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PWMC_GetStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_CfgChannel
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int channelId, // \arg PWM channel ID
+        unsigned int mode, // \arg  PWM mode
+        unsigned int period, // \arg PWM period
+        unsigned int duty) // \arg PWM duty cycle
+{
+	pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
+	pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
+	pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_StartChannel
+//* \brief Enable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StartChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_ENA = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_StopChannel
+//* \brief Disable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StopChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_DIS = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_UpdateChannel
+//* \brief Update Period or Duty Cycle
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_UpdateChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int channelId, // \arg PWM channel ID
+        unsigned int update) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR UDP
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EnableIt
+//* \brief Enable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableIt (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pUDP->UDP_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_DisableIt
+//* \brief Disable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableIt (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pUDP->UDP_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_SetAddress
+//* \brief Set UDP functional address
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetAddress (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char address)   // \arg new UDP address
+{
+	pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EnableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableEp (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_DisableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableEp (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_SetState
+//* \brief Set UDP Device state
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetState (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg new UDP address
+{
+	pUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
+	pUDP->UDP_GLBSTATE  |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_GetState
+//* \brief return UDP Device state
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
+	AT91PS_UDP pUDP)     // \arg pointer to a UDP controller
+{
+	return (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_ResetEp
+//* \brief Reset UDP endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg Endpoints to be reset
+{
+	pUDP->UDP_RSTEP = flag;
+	pUDP->UDP_RSTEP = 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpStall
+//* \brief Endpoint will STALL requests
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpStall(
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpWrite
+//* \brief Write value in the DPR
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpWrite(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned char value)     // \arg value to be written in the DPR
+{
+	pUDP->UDP_FDR[endpoint] = value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpRead
+//* \brief Return value from the DPR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpRead(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	return pUDP->UDP_FDR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpEndOfWr
+//* \brief Notify the UDP that values in DPR are ready to be sent
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpEndOfWr(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpClear
+//* \brief Clear flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpClear(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned int flag)       // \arg flag to be cleared
+{
+	pUDP->UDP_CSR[endpoint] &= ~(flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpSet
+//* \brief Set flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpSet(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned int flag)       // \arg flag to be cleared
+{
+	pUDP->UDP_CSR[endpoint] |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpStatus
+//* \brief Return the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpStatus(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	return pUDP->UDP_CSR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_GetInterruptMaskStatus
+//* \brief Return UDP Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
+        AT91PS_UDP pUdp) // \arg  pointer to a UDP controller
+{
+        return pUdp->UDP_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_IsInterruptMasked
+//* \brief Test if UDP Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_UDP_IsInterruptMasked(
+        AT91PS_UDP pUdp,   // \arg  pointer to a UDP controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_InterruptEnable
+//* \brief Enable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptEnable(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  TC interrupt to be enabled
+{
+        pTc->TC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_InterruptDisable
+//* \brief Disable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptDisable(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  TC interrupt to be disabled
+{
+        pTc->TC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_GetInterruptMaskStatus
+//* \brief Return TC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
+        AT91PS_TC pTc) // \arg  pointer to a TC controller
+{
+        return pTc->TC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_IsInterruptMasked
+//* \brief Test if TC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_TC_IsInterruptMasked(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR CAN
+   ***************************************************************************** */
+#define	STANDARD_FORMAT 0
+#define	EXTENDED_FORMAT 1
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_InitMailboxRegisters()
+//* \brief Configure the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB	CAN_Mailbox,
+								int  			mode_reg,
+								int 			acceptance_mask_reg,
+								int  			id_reg,
+								int  			data_low_reg,
+								int  			data_high_reg,
+								int  			control_reg)
+{
+	CAN_Mailbox->CAN_MB_MCR 	= 0x0;
+	CAN_Mailbox->CAN_MB_MMR 	= mode_reg;
+	CAN_Mailbox->CAN_MB_MAM 	= acceptance_mask_reg;
+	CAN_Mailbox->CAN_MB_MID 	= id_reg;
+	CAN_Mailbox->CAN_MB_MDL 	= data_low_reg; 		
+	CAN_Mailbox->CAN_MB_MDH 	= data_high_reg;
+	CAN_Mailbox->CAN_MB_MCR 	= control_reg;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EnableCAN()
+//* \brief 
+//*----------------------------------------------------------------------------
+__inline void AT91F_EnableCAN(
+	AT91PS_CAN pCAN)     // pointer to a CAN controller
+{
+	pCAN->CAN_MR |= AT91C_CAN_CANEN;
+
+	// Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver
+	while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DisableCAN()
+//* \brief 
+//*----------------------------------------------------------------------------
+__inline void AT91F_DisableCAN(
+	AT91PS_CAN pCAN)     // pointer to a CAN controller
+{
+	pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_EnableIt
+//* \brief Enable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_EnableIt (
+	AT91PS_CAN pCAN,     // pointer to a CAN controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pCAN->CAN_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_DisableIt
+//* \brief Disable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_DisableIt (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pCAN->CAN_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetStatus
+//* \brief Return CAN Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status
+	AT91PS_CAN pCAN) // pointer to a CAN controller
+{
+	return pCAN->CAN_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetInterruptMaskStatus
+//* \brief Return CAN Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status
+	AT91PS_CAN pCAN) // pointer to a CAN controller
+{
+	return pCAN->CAN_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_IsInterruptMasked
+//* \brief Test if CAN Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsInterruptMasked(
+        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_IsStatusSet
+//* \brief Test if CAN Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsStatusSet(
+        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_CAN_GetStatus(pCAN) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgModeReg
+//* \brief Configure the Mode Register of the CAN controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgModeReg (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pCAN->CAN_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetModeReg
+//* \brief Return the Mode Register of the CAN controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetModeReg (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgBaudrateReg
+//* \brief Configure the Baudrate of the CAN controller for the network
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgBaudrateReg (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int baudrate_cfg)
+{
+	//* Write to the BR register
+	pCAN->CAN_BR = baudrate_cfg;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetBaudrate
+//* \brief Return the Baudrate of the CAN controller for the network value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetBaudrate (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_BR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetInternalCounter
+//* \brief Return CAN Timer Regsiter Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInternalCounter (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_TIM;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetTimestamp
+//* \brief Return CAN Timestamp Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetTimestamp (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_TIMESTP;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetErrorCounter
+//* \brief Return CAN Error Counter Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetErrorCounter (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_ECR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_InitTransferRequest
+//* \brief Request for a transfer on the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitTransferRequest (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+    unsigned int transfer_cmd)
+{
+	pCAN->CAN_TCR = transfer_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_InitAbortRequest
+//* \brief Abort the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitAbortRequest (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+    unsigned int abort_cmd)
+{
+	pCAN->CAN_ACR = abort_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageModeReg
+//* \brief Program the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageModeReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int mode)
+{
+	CAN_Mailbox->CAN_MB_MMR = mode;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageModeReg
+//* \brief Return the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageModeReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MMR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageIDReg
+//* \brief Program the Message ID Register
+//* \brief Version == 0 for Standard messsage, Version == 1 for Extended  
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageIDReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int id,
+    unsigned char version)
+{
+	if(version==0)	// IDvA Standard Format
+		CAN_Mailbox->CAN_MB_MID = id<<18;
+	else	// IDvB Extended Format
+		CAN_Mailbox->CAN_MB_MID = id | (1<<29);	// set MIDE bit
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageIDReg
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageIDReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MID;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageAcceptanceMaskReg
+//* \brief Program the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int mask)
+{
+	CAN_Mailbox->CAN_MB_MAM = mask;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageAcceptanceMaskReg
+//* \brief Return the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MAM;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetFamilyID
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetFamilyID (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MFID;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageCtrl
+//* \brief Request and config for a transfer on the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageCtrlReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int message_ctrl_cmd)
+{
+	CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageStatus
+//* \brief Return CAN Mailbox Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageStatus (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MSR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageDataLow
+//* \brief Program data low value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataLow (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int data)
+{
+	CAN_Mailbox->CAN_MB_MDL = data;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageDataLow
+//* \brief Return data low value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataLow (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MDL;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageDataHigh
+//* \brief Program data high value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataHigh (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int data)
+{
+	CAN_Mailbox->CAN_MB_MDH = data;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageDataHigh
+//* \brief Return data high value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataHigh (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MDH;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_Open
+//* \brief Open a CAN Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_Open (
+        const unsigned int null)  // \arg
+{
+        /* NOT DEFINED AT THIS MOMENT */
+        return ( 0 );
+}
+/* *****************************************************************************
+                SOFTWARE API FOR ADC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_EnableIt
+//* \brief Enable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableIt (
+	AT91PS_ADC pADC,     // pointer to a ADC controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pADC->ADC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_DisableIt
+//* \brief Disable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableIt (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pADC->ADC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetStatus
+//* \brief Return ADC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
+	AT91PS_ADC pADC) // pointer to a ADC controller
+{
+	return pADC->ADC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetInterruptMaskStatus
+//* \brief Return ADC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
+	AT91PS_ADC pADC) // pointer to a ADC controller
+{
+	return pADC->ADC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_IsInterruptMasked
+//* \brief Test if ADC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsInterruptMasked(
+        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_IsStatusSet
+//* \brief Test if ADC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsStatusSet(
+        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_ADC_GetStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgModeReg
+//* \brief Configure the Mode Register of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgModeReg (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pADC->ADC_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetModeReg
+//* \brief Return the Mode Register of the ADC controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetModeReg (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgTimings
+//* \brief Configure the different necessary timings of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgTimings (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int mck_clock, // in MHz 
+	unsigned int adc_clock, // in MHz 
+	unsigned int startup_time, // in us 
+	unsigned int sample_and_hold_time)	// in ns  
+{
+	unsigned int prescal,startup,shtim;
+	
+	prescal = mck_clock/(2*adc_clock) - 1;
+	startup = adc_clock*startup_time/8 - 1;
+	shtim = adc_clock*sample_and_hold_time/1000 - 1;
+	
+	//* Write to the MR register
+	pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_EnableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableChannel (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int channel)        // mode register 
+{
+	//* Write to the CHER register
+	pADC->ADC_CHER = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_DisableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableChannel (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int channel)        // mode register 
+{
+	//* Write to the CHDR register
+	pADC->ADC_CHDR = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetChannelStatus
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetChannelStatus (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CHSR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_StartConversion
+//* \brief Software request for a analog to digital conversion 
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_StartConversion (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	pADC->ADC_CR = AT91C_ADC_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_SoftReset
+//* \brief Software reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_SoftReset (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	pADC->ADC_CR = AT91C_ADC_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetLastConvertedData
+//* \brief Return the Last Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetLastConvertedData (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_LCDR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH0
+//* \brief Return the Channel 0 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR0;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH1
+//* \brief Return the Channel 1 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR1;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH2
+//* \brief Return the Channel 2 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR2;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH3
+//* \brief Return the Channel 3 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR3;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH4
+//* \brief Return the Channel 4 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR4;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH5
+//* \brief Return the Channel 5 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR5;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH6
+//* \brief Return the Channel 6 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR6;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH7
+//* \brief Return the Channel 7 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR7;	
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR AES
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_EnableIt
+//* \brief Enable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_EnableIt (
+	AT91PS_AES pAES,     // pointer to a AES controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pAES->AES_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_DisableIt
+//* \brief Disable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_DisableIt (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pAES->AES_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetStatus
+//* \brief Return AES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status
+	AT91PS_AES pAES) // pointer to a AES controller
+{
+	return pAES->AES_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetInterruptMaskStatus
+//* \brief Return AES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status
+	AT91PS_AES pAES) // pointer to a AES controller
+{
+	return pAES->AES_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_IsInterruptMasked
+//* \brief Test if AES Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsInterruptMasked(
+        AT91PS_AES pAES,   // \arg  pointer to a AES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_IsStatusSet
+//* \brief Test if AES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsStatusSet(
+        AT91PS_AES pAES,   // \arg  pointer to a AES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_AES_GetStatus(pAES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_CfgModeReg
+//* \brief Configure the Mode Register of the AES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgModeReg (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pAES->AES_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetModeReg
+//* \brief Return the Mode Register of the AES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetModeReg (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	return pAES->AES_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_StartProcessing (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SoftReset
+//* \brief Reset AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SoftReset (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_LoadNewSeed
+//* \brief Load New Seed in the random number generator
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_LoadNewSeed (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_LOADSEED;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SetCryptoKey
+//* \brief Set Cryptographic Key x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetCryptoKey (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pAES->AES_KEYWxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_InputData (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int indata
+	)
+{
+	pAES->AES_IDATAxR[index] = indata;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetOutputData (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index
+	)
+{
+	return pAES->AES_ODATAxR[index];	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SetInitializationVector
+//* \brief Set Initialization Vector (or Counter) x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetInitializationVector (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int initvector
+	)
+{
+	pAES->AES_IVxR[index] = initvector;	
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TDES
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_EnableIt
+//* \brief Enable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_EnableIt (
+	AT91PS_TDES pTDES,     // pointer to a TDES controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pTDES->TDES_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_DisableIt
+//* \brief Disable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_DisableIt (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pTDES->TDES_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetStatus
+//* \brief Return TDES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status
+	AT91PS_TDES pTDES) // pointer to a TDES controller
+{
+	return pTDES->TDES_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetInterruptMaskStatus
+//* \brief Return TDES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status
+	AT91PS_TDES pTDES) // pointer to a TDES controller
+{
+	return pTDES->TDES_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_IsInterruptMasked
+//* \brief Test if TDES Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsInterruptMasked(
+        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_IsStatusSet
+//* \brief Test if TDES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsStatusSet(
+        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_TDES_GetStatus(pTDES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_CfgModeReg
+//* \brief Configure the Mode Register of the TDES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgModeReg (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pTDES->TDES_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetModeReg
+//* \brief Return the Mode Register of the TDES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetModeReg (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	return pTDES->TDES_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_StartProcessing (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	pTDES->TDES_CR = AT91C_TDES_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SoftReset
+//* \brief Reset TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SoftReset (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	pTDES->TDES_CR = AT91C_TDES_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey1
+//* \brief Set Cryptographic Key 1 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey1 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY1WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey2
+//* \brief Set Cryptographic Key 2 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey2 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY2WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey3
+//* \brief Set Cryptographic Key 3 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey3 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY3WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_InputData (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int indata
+	)
+{
+	pTDES->TDES_IDATAxR[index] = indata;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetOutputData (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index
+	)
+{
+	return pTDES->TDES_ODATAxR[index];	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetInitializationVector
+//* \brief Set Initialization Vector x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetInitializationVector (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int initvector
+	)
+{
+	pTDES->TDES_IVxR[index] = initvector;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  DBGU
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_CfgPIO
+//* \brief Configure PIO controllers to drive DBGU signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA27_DRXD    ) |
+		((unsigned int) AT91C_PA28_DTXD    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgPIO
+//* \brief Configure PIO controllers to drive PMC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB30_PCK2    ) |
+		((unsigned int) AT91C_PB29_PCK1    ), // Peripheral A
+		((unsigned int) AT91C_PB20_PCK0    ) |
+		((unsigned int) AT91C_PB0_PCK0    ) |
+		((unsigned int) AT91C_PB22_PCK2    ) |
+		((unsigned int) AT91C_PB21_PCK1    )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA30_PCK2    ) |
+		((unsigned int) AT91C_PA13_PCK1    ) |
+		((unsigned int) AT91C_PA27_PCK3    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  VREG
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  RSTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SSC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_CfgPIO
+//* \brief Configure PIO controllers to drive SSC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA25_RK      ) |
+		((unsigned int) AT91C_PA22_TK      ) |
+		((unsigned int) AT91C_PA21_TF      ) |
+		((unsigned int) AT91C_PA24_RD      ) |
+		((unsigned int) AT91C_PA26_RF      ) |
+		((unsigned int) AT91C_PA23_TD      ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  WDTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  US1
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_US1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US1_CfgPIO
+//* \brief Configure PIO controllers to drive US1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB26_RI1     ) |
+		((unsigned int) AT91C_PB24_DSR1    ) |
+		((unsigned int) AT91C_PB23_DCD1    ) |
+		((unsigned int) AT91C_PB25_DTR1    )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA7_SCK1    ) |
+		((unsigned int) AT91C_PA8_RTS1    ) |
+		((unsigned int) AT91C_PA6_TXD1    ) |
+		((unsigned int) AT91C_PA5_RXD1    ) |
+		((unsigned int) AT91C_PA9_CTS1    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  US0
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_US0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US0_CfgPIO
+//* \brief Configure PIO controllers to drive US0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA0_RXD0    ) |
+		((unsigned int) AT91C_PA4_CTS0    ) |
+		((unsigned int) AT91C_PA3_RTS0    ) |
+		((unsigned int) AT91C_PA2_SCK0    ) |
+		((unsigned int) AT91C_PA1_TXD0    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SPI1
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SPI1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI1_CfgPIO
+//* \brief Configure PIO controllers to drive SPI1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB16_NPCS13  ) |
+		((unsigned int) AT91C_PB10_NPCS11  ) |
+		((unsigned int) AT91C_PB11_NPCS12  )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA4_NPCS13  ) |
+		((unsigned int) AT91C_PA29_NPCS13  ) |
+		((unsigned int) AT91C_PA21_NPCS10  ) |
+		((unsigned int) AT91C_PA22_SPCK1   ) |
+		((unsigned int) AT91C_PA25_NPCS11  ) |
+		((unsigned int) AT91C_PA2_NPCS11  ) |
+		((unsigned int) AT91C_PA24_MISO1   ) |
+		((unsigned int) AT91C_PA3_NPCS12  ) |
+		((unsigned int) AT91C_PA26_NPCS12  ) |
+		((unsigned int) AT91C_PA23_MOSI1   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SPI0
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SPI0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI0_CfgPIO
+//* \brief Configure PIO controllers to drive SPI0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB13_NPCS01  ) |
+		((unsigned int) AT91C_PB17_NPCS03  ) |
+		((unsigned int) AT91C_PB14_NPCS02  )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA16_MISO0   ) |
+		((unsigned int) AT91C_PA13_NPCS01  ) |
+		((unsigned int) AT91C_PA15_NPCS03  ) |
+		((unsigned int) AT91C_PA17_MOSI0   ) |
+		((unsigned int) AT91C_PA18_SPCK0   ) |
+		((unsigned int) AT91C_PA14_NPCS02  ) |
+		((unsigned int) AT91C_PA12_NPCS00  ), // Peripheral A
+		((unsigned int) AT91C_PA7_NPCS01  ) |
+		((unsigned int) AT91C_PA9_NPCS03  ) |
+		((unsigned int) AT91C_PA8_NPCS02  )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PITC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  AIC
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_FIQ) |
+		((unsigned int) 1 << AT91C_ID_IRQ0) |
+		((unsigned int) 1 << AT91C_ID_IRQ1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_CfgPIO
+//* \brief Configure PIO controllers to drive AIC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA30_IRQ0    ) |
+		((unsigned int) AT91C_PA29_FIQ     ), // Peripheral A
+		((unsigned int) AT91C_PA14_IRQ1    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_AES));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TWI
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TWI));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_CfgPIO
+//* \brief Configure PIO controllers to drive TWI signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA11_TWCK    ) |
+		((unsigned int) AT91C_PA10_TWD     ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  ADC
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_ADC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgPIO
+//* \brief Configure PIO controllers to drive ADC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB18_ADTRG   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH3_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH3 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH3_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB22_PWM3    ), // Peripheral A
+		((unsigned int) AT91C_PB30_PWM3    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH2_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH2_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB21_PWM2    ), // Peripheral A
+		((unsigned int) AT91C_PB29_PWM2    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH1_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB20_PWM1    ), // Peripheral A
+		((unsigned int) AT91C_PB28_PWM1    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH0_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB19_PWM0    ), // Peripheral A
+		((unsigned int) AT91C_PB27_PWM0    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RTTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  RTTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RTTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  UDP
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_UDP));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TDES));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EMAC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  EMAC
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_EMAC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EMAC_CfgPIO
+//* \brief Configure PIO controllers to drive EMAC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB2_ETX0    ) |
+		((unsigned int) AT91C_PB12_ETXER   ) |
+		((unsigned int) AT91C_PB16_ECOL    ) |
+		((unsigned int) AT91C_PB11_ETX3    ) |
+		((unsigned int) AT91C_PB6_ERX1    ) |
+		((unsigned int) AT91C_PB15_ERXDV   ) |
+		((unsigned int) AT91C_PB13_ERX2    ) |
+		((unsigned int) AT91C_PB3_ETX1    ) |
+		((unsigned int) AT91C_PB8_EMDC    ) |
+		((unsigned int) AT91C_PB5_ERX0    ) |
+		//((unsigned int) AT91C_PB18_EF100   ) |
+		((unsigned int) AT91C_PB14_ERX3    ) |
+		((unsigned int) AT91C_PB4_ECRS_ECRSDV) |
+		((unsigned int) AT91C_PB1_ETXEN   ) |
+		((unsigned int) AT91C_PB10_ETX2    ) |
+		((unsigned int) AT91C_PB0_ETXCK_EREFCK) |
+		((unsigned int) AT91C_PB9_EMDIO   ) |
+		((unsigned int) AT91C_PB7_ERXER   ) |
+		((unsigned int) AT91C_PB17_ERXCK   ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC0
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC0_CfgPIO
+//* \brief Configure PIO controllers to drive TC0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB23_TIOA0   ) |
+		((unsigned int) AT91C_PB24_TIOB0   ), // Peripheral A
+		((unsigned int) AT91C_PB12_TCLK0   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC1
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC1_CfgPIO
+//* \brief Configure PIO controllers to drive TC1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB25_TIOA1   ) |
+		((unsigned int) AT91C_PB26_TIOB1   ), // Peripheral A
+		((unsigned int) AT91C_PB19_TCLK1   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC2_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC2
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC2));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC2_CfgPIO
+//* \brief Configure PIO controllers to drive TC2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB28_TIOB2   ) |
+		((unsigned int) AT91C_PB27_TIOA2   ), // Peripheral A
+		0); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA15_TCLK2   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  MC
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIOA_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PIOA
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOA_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PIOA));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIOB_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PIOB
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOB_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PIOB));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  CAN
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_CAN));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgPIO
+//* \brief Configure PIO controllers to drive CAN signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA20_CANTX   ) |
+		((unsigned int) AT91C_PA19_CANRX   ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PWMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PWMC));
+}
+
+#endif // lib_AT91SAM7X256_H
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/port.c
new file mode 100644
index 0000000..fca0dc7
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/port.c
@@ -0,0 +1,213 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM7 port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file.  The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Processor constants. */
+#include "AT91SAM7X256.h"
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING	( ( StackType_t ) 0 )
+
+/* Constants required to setup the tick ISR. */
+#define portENABLE_TIMER			( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE			0x00
+#define portINTERRUPT_ON_MATCH		( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH	( ( uint32_t ) 0x02 )
+
+/* Constants required to setup the PIT. */
+#define portPIT_CLOCK_DIVISOR			( ( uint32_t ) 16 )
+#define portPIT_COUNTER_VALUE			( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
+
+#define portINT_LEVEL_SENSITIVE  0
+#define portPIT_ENABLE      	( ( uint16_t ) 0x1 << 24 )
+#define portPIT_INT_ENABLE     	( ( uint16_t ) 0x1 << 25 )
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* 
+ * The scheduler can only be started from ARM mode, so 
+ * vPortISRStartFirstSTask() is defined in portISR.c. 
+ */
+extern void vPortISRStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x00000000;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The last thing onto the stack is the status register, which is set for
+	system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	#ifdef THUMB_INTERWORK
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+	#endif
+
+	pxTopOfStack--;
+
+	/* Some optimisation levels use the stack differently to others.  This 
+	means the interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortISRStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the timer 0 to generate the tick interrupts at the required frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+AT91PS_PITC pxPIT = AT91C_BASE_PITC;
+
+	/* Setup the AIC for PIT interrupts.  The interrupt routine chosen depends
+	on whether the preemptive or cooperative scheduler is being used. */
+	#if configUSE_PREEMPTION == 0
+
+		extern void ( vNonPreemptiveTick ) ( void );
+		AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick );
+
+	#else
+		
+		extern void ( vPreemptiveTick )( void );
+		AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick );
+
+	#endif
+
+	/* Configure the PIT period. */
+	pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
+
+	/* Enable the interrupt.  Global interrupts are disables at this point so 
+	this is safe. */
+    AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS;
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c
new file mode 100644
index 0000000..197e201
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c
@@ -0,0 +1,227 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c  The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/*
+	Changes from V3.2.4
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#include "AT91SAM7X256.h"
+
+/* Constants required to handle interrupts. */
+#define portTIMER_MATCH_ISR_BIT		( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT		( ( uint32_t ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* ISR to handle manual context switches (from a call to taskYIELD()). */
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+
+/*
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+	/* Simply start the scheduler.  This is included here as it can only be
+	called from ARM mode. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ *
+ * When a context switch is performed from the task level the saved task
+ * context is made to look as if it occurred from within the tick ISR.  This
+ * way the same restore context function can be used when restoring the context
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.
+ */
+void vPortYieldProcessor( void )
+{
+	/* Within an IRQ ISR the link register has an offset from the true return
+	address, but an SWI ISR does not.  Add the offset manually so the same
+	ISR return code can be used in both cases. */
+	__asm volatile ( "ADD		LR, LR, #4" );
+
+	/* Perform the context switch.  First save the context of the current task. */
+	portSAVE_CONTEXT();
+
+	/* Find the highest priority task that is ready to run. */
+	vTaskSwitchContext();
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+
+#if configUSE_PREEMPTION == 0
+
+	/* The cooperative scheduler requires a normal IRQ service routine to
+	simply increment the system tick. */
+	void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+	void vNonPreemptiveTick( void )
+	{
+		uint32_t ulDummy;
+
+		/* Increment the tick count - which may wake some tasks but as the
+		preemptive scheduler is not being used any woken task is not given
+		processor time no matter what its priority. */
+		xTaskIncrementTick();
+
+		/* Clear the PIT interrupt. */
+		ulDummy = AT91C_BASE_PITC->PITC_PIVR;
+
+		/* End the interrupt in the AIC. */
+		AT91C_BASE_AIC->AIC_EOICR = ulDummy;
+	}
+
+#else
+
+	/* The preemptive scheduler is defined as "naked" as the full context is
+	saved on entry as part of the context switch. */
+	void vPreemptiveTick( void ) __attribute__((naked));
+	void vPreemptiveTick( void )
+	{
+		/* Save the context of the current task. */
+		portSAVE_CONTEXT();
+
+		/* Increment the tick count - this may wake a task. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Find the highest priority task that is ready to run. */
+			vTaskSwitchContext();
+		}
+
+		/* End the interrupt in the AIC. */
+		AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;
+
+		portRESTORE_CONTEXT();
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+void vPortDisableInterruptsFromThumb( void )
+{
+	__asm volatile (
+		"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+		"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+		"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
+		"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+		"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+		"BX		R14" );					/* Return back to thumb.					*/
+}
+
+void vPortEnableInterruptsFromThumb( void )
+{
+	__asm volatile (
+		"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+		"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+		"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/
+		"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+		"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+		"BX		R14" );					/* Return back to thumb.					*/
+}
+
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels.  The interrupt flags can therefore not always
+be saved to the stack.  Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
+	__asm volatile (
+		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
+		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
+		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
+		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
+		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable interrupts as per portEXIT_CRITICAL().					*/
+			__asm volatile (
+				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/
+				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/
+				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/
+				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/
+				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
+		}
+	}
+}
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h
new file mode 100644
index 0000000..97ab4de
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h
@@ -0,0 +1,249 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+	Changes from V3.2.3
+
+	+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+	Changes from V3.2.4
+
+	+ Removed the use of the %0 parameter within the assembler macros and
+	  replaced them with hard coded registers.  This will ensure the
+	  assembler does not select the link register as the temp register as
+	  was occasionally happening previously.
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+
+	Changes from V4.5.0
+
+	+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+	  and replaced them with portYIELD_FROM_ISR() macro.  Application code
+	  should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+	  macros as per the V4.5.1 demo code.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	portLONG
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portNOP()					__asm volatile ( "NOP" );
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+
+/*
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
+ * are included here for efficiency.  An attempt to call one from
+ * THUMB mode code will result in a compile time error.
+ */
+
+#define portRESTORE_CONTEXT()											\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile uint32_t ulCriticalNesting;					\
+																		\
+	/* Set the LR to the task stack. */									\
+	__asm volatile (													\
+	"LDR		R0, =pxCurrentTCB								\n\t"	\
+	"LDR		R0, [R0]										\n\t"	\
+	"LDR		LR, [R0]										\n\t"	\
+																		\
+	/* The critical nesting depth is the first item on the stack. */	\
+	/* Load it into the ulCriticalNesting variable. */					\
+	"LDR		R0, =ulCriticalNesting							\n\t"	\
+	"LDMFD	LR!, {R1}											\n\t"	\
+	"STR		R1, [R0]										\n\t"	\
+																		\
+	/* Get the SPSR from the stack. */									\
+	"LDMFD	LR!, {R0}											\n\t"	\
+	"MSR		SPSR, R0										\n\t"	\
+																		\
+	/* Restore all system mode registers for the task. */				\
+	"LDMFD	LR, {R0-R14}^										\n\t"	\
+	"NOP														\n\t"	\
+																		\
+	/* Restore the return address. */									\
+	"LDR		LR, [LR, #+60]									\n\t"	\
+																		\
+	/* And return - correcting the offset in the LR to obtain the */	\
+	/* correct address. */												\
+	"SUBS	PC, LR, #4											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+/*-----------------------------------------------------------*/
+
+#define portSAVE_CONTEXT()												\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile uint32_t ulCriticalNesting;					\
+																		\
+	/* Push R0 as we are going to use the register. */					\
+	__asm volatile (													\
+	"STMDB	SP!, {R0}											\n\t"	\
+																		\
+	/* Set R0 to point to the task stack pointer. */					\
+	"STMDB	SP,{SP}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	SP, SP, #4											\n\t"	\
+	"LDMIA	SP!,{R0}											\n\t"	\
+																		\
+	/* Push the return address onto the stack. */						\
+	"STMDB	R0!, {LR}											\n\t"	\
+																		\
+	/* Now we have saved LR we can use it instead of R0. */				\
+	"MOV	LR, R0												\n\t"	\
+																		\
+	/* Pop R0 so we can save it onto the system mode stack. */			\
+	"LDMIA	SP!, {R0}											\n\t"	\
+																		\
+	/* Push all the system mode registers onto the task stack. */		\
+	"STMDB	LR,{R0-LR}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	LR, LR, #60											\n\t"	\
+																		\
+	/* Push the SPSR onto the task stack. */							\
+	"MRS	R0, SPSR											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	"LDR	R0, =ulCriticalNesting								\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	/* Store the new top of stack for the task. */						\
+	"LDR	R0, =pxCurrentTCB									\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STR	LR, [R0]											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+
+
+#define portYIELD_FROM_ISR()		vTaskSwitchContext()
+#define portYIELD()					__asm volatile ( "SWI 0" )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in
+ * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
+	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
+
+#else
+
+	#define portDISABLE_INTERRUPTS()											\
+		__asm volatile (														\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+	#define portENABLE_INTERRUPTS()												\
+		__asm volatile (														\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/port.c
new file mode 100644
index 0000000..abc4810
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/port.c
@@ -0,0 +1,221 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM7 port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file.  The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
+
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING	( ( StackType_t ) 0 )
+
+/* Constants required to setup the tick ISR. */
+#define portENABLE_TIMER			( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE			0x00
+#define portINTERRUPT_ON_MATCH		( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH	( ( uint32_t ) 0x02 )
+
+/* Constants required to setup the VIC for the tick ISR. */
+#define portTIMER_VIC_CHANNEL		( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT	( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE		( ( uint32_t ) 0x0020 )
+
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* 
+ * The scheduler can only be started from ARM mode, so 
+ * vPortISRStartFirstSTask() is defined in portISR.c. 
+ */
+extern void vPortISRStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The last thing onto the stack is the status register, which is set for
+	system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* Some optimisation levels use the stack differently to others.  This 
+	means the interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortISRStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the timer 0 to generate the tick interrupts at the required frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+extern void ( vTickISR )( void );
+
+	/* A 1ms tick does not require the use of the timer prescale.  This is
+	defaulted to zero but can be used if necessary. */
+	T0_PR = portPRESCALE_VALUE;
+
+	/* Calculate the match value required for our wanted tick rate. */
+	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+	/* Protect against divide by zero.  Using an if() statement still results
+	in a warning - hence the #if. */
+	#if portPRESCALE_VALUE != 0
+	{
+		ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
+	}
+	#endif
+	T0_MR0 = ulCompareMatch;
+
+	/* Generate tick with timer 0 compare match. */
+	T0_MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
+
+	/* Setup the VIC for the timer. */
+	VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
+	VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
+	
+	/* The ISR installed depends on whether the preemptive or cooperative
+	scheduler is being used. */
+
+	VICVectAddr0 = ( int32_t ) vTickISR;
+	VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
+
+	/* Start the timer - interrupts are disabled when this function is called
+	so it is okay to do this here. */
+	T0_TCR = portENABLE_TIMER;
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portISR.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portISR.c
new file mode 100644
index 0000000..4b5c8b2
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portISR.c
@@ -0,0 +1,215 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c  The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/*
+	Changes from V2.5.2
+
+	+ The critical section management functions have been changed.  These no
+	  longer modify the stack and are safe to use at all optimisation levels.
+	  The functions are now also the same for both ARM and THUMB modes.
+
+	Changes from V2.6.0
+
+	+ Removed the 'static' from the definition of vNonPreemptiveTick() to
+	  allow the demo to link when using the cooperative scheduler.
+
+	Changes from V3.2.4
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* Constants required to handle interrupts. */
+#define portTIMER_MATCH_ISR_BIT		( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT		( ( uint32_t ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* ISR to handle manual context switches (from a call to taskYIELD()). */
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+
+/*
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+	/* Simply start the scheduler.  This is included here as it can only be
+	called from ARM mode. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ *
+ * When a context switch is performed from the task level the saved task
+ * context is made to look as if it occurred from within the tick ISR.  This
+ * way the same restore context function can be used when restoring the context
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.
+ */
+void vPortYieldProcessor( void )
+{
+	/* Within an IRQ ISR the link register has an offset from the true return
+	address, but an SWI ISR does not.  Add the offset manually so the same
+	ISR return code can be used in both cases. */
+	__asm volatile ( "ADD		LR, LR, #4" );
+
+	/* Perform the context switch.  First save the context of the current task. */
+	portSAVE_CONTEXT();
+
+	/* Find the highest priority task that is ready to run. */
+	__asm volatile ( "bl vTaskSwitchContext" );
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The ISR used for the scheduler tick.
+ */
+void vTickISR( void ) __attribute__((naked));
+void vTickISR( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT();
+
+	/* Increment the RTOS tick count, then look for the highest priority
+	task that is ready to run. */
+	__asm volatile
+	(
+		"	bl xTaskIncrementTick	\t\n" \
+		"	cmp r0, #0				\t\n" \
+		"	beq SkipContextSwitch	\t\n" \
+		"	bl vTaskSwitchContext	\t\n" \
+		"SkipContextSwitch:			\t\n"
+	);
+
+	/* Ready for the next interrupt. */
+	T0_IR = portTIMER_MATCH_ISR_BIT;
+	VICVectAddr = portCLEAR_VIC_INTERRUPT;
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+#ifdef THUMB_INTERWORK
+
+	void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	void vPortDisableInterruptsFromThumb( void )
+	{
+		__asm volatile (
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+
+	void vPortEnableInterruptsFromThumb( void )
+	{
+		__asm volatile (
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+
+#endif /* THUMB_INTERWORK */
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels.  The interrupt flags can therefore not always
+be saved to the stack.  Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
+	__asm volatile (
+		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
+		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
+		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
+		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
+		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable interrupts as per portEXIT_CRITICAL().					*/
+			__asm volatile (
+				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/
+				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/
+				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/
+				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/
+				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
+		}
+	}
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portmacro.h
new file mode 100644
index 0000000..7ee62d1
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portmacro.h
@@ -0,0 +1,226 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	portLONG
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portNOP()					__asm volatile ( "NOP" );
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+
+/*
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
+ * are included here for efficiency.  An attempt to call one from
+ * THUMB mode code will result in a compile time error.
+ */
+
+#define portRESTORE_CONTEXT()											\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile uint32_t ulCriticalNesting;					\
+																		\
+	/* Set the LR to the task stack. */									\
+	__asm volatile (													\
+	"LDR		R0, =pxCurrentTCB								\n\t"	\
+	"LDR		R0, [R0]										\n\t"	\
+	"LDR		LR, [R0]										\n\t"	\
+																		\
+	/* The critical nesting depth is the first item on the stack. */	\
+	/* Load it into the ulCriticalNesting variable. */					\
+	"LDR		R0, =ulCriticalNesting							\n\t"	\
+	"LDMFD	LR!, {R1}											\n\t"	\
+	"STR		R1, [R0]										\n\t"	\
+																		\
+	/* Get the SPSR from the stack. */									\
+	"LDMFD	LR!, {R0}											\n\t"	\
+	"MSR		SPSR, R0										\n\t"	\
+																		\
+	/* Restore all system mode registers for the task. */				\
+	"LDMFD	LR, {R0-R14}^										\n\t"	\
+	"NOP														\n\t"	\
+																		\
+	/* Restore the return address. */									\
+	"LDR		LR, [LR, #+60]									\n\t"	\
+																		\
+	/* And return - correcting the offset in the LR to obtain the */	\
+	/* correct address. */												\
+	"SUBS	PC, LR, #4											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+/*-----------------------------------------------------------*/
+
+#define portSAVE_CONTEXT()												\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile uint32_t ulCriticalNesting;					\
+																		\
+	/* Push R0 as we are going to use the register. */					\
+	__asm volatile (													\
+	"STMDB	SP!, {R0}											\n\t"	\
+																		\
+	/* Set R0 to point to the task stack pointer. */					\
+	"STMDB	SP,{SP}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	SP, SP, #4											\n\t"	\
+	"LDMIA	SP!,{R0}											\n\t"	\
+																		\
+	/* Push the return address onto the stack. */						\
+	"STMDB	R0!, {LR}											\n\t"	\
+																		\
+	/* Now we have saved LR we can use it instead of R0. */				\
+	"MOV	LR, R0												\n\t"	\
+																		\
+	/* Pop R0 so we can save it onto the system mode stack. */			\
+	"LDMIA	SP!, {R0}											\n\t"	\
+																		\
+	/* Push all the system mode registers onto the task stack. */		\
+	"STMDB	LR,{R0-LR}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	LR, LR, #60											\n\t"	\
+																		\
+	/* Push the SPSR onto the task stack. */							\
+	"MRS	R0, SPSR											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	"LDR	R0, =ulCriticalNesting								\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	/* Store the new top of stack for the task. */						\
+	"LDR	R0, =pxCurrentTCB									\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STR	LR, [R0]											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR()		vTaskSwitchContext()
+#define portYIELD()					__asm volatile ( "SWI 0" )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in
+ * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
+	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
+
+#else
+
+	#define portDISABLE_INTERRUPTS()											\
+		__asm volatile (														\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+	#define portENABLE_INTERRUPTS()												\
+		__asm volatile (														\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/port.c
new file mode 100644
index 0000000..f93d04a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/port.c
@@ -0,0 +1,233 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM7 port.
+ *
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in this file.  The ISR routines, which can only be compiled
+ * to ARM mode are contained in portISR.c.
+ *----------------------------------------------------------*/
+
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING	( ( StackType_t ) 0 )
+
+/* Constants required to setup the tick ISR. */
+#define portENABLE_TIMER                ( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE              0x00
+#define portINTERRUPT_ON_MATCH          ( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH        ( ( uint32_t ) 0x02 )
+
+/* Constants required to setup the VIC for the tick ISR. */
+#define portTIMER_VIC_CHANNEL           ( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT       ( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE            ( ( uint32_t ) 0x0020 )
+
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* 
+ * The scheduler can only be started from ARM mode, so 
+ * vPortISRStartFirstSTask() is defined in portISR.c. 
+ */
+extern void vPortISRStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+	
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x00000000;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The last thing onto the stack is the status register, which is set for
+	system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* Some optimisation levels use the stack differently to others.  This 
+	means the interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortISRStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the timer 0 to generate the tick interrupts at the required frequency.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+
+	PCLKSEL0 = (PCLKSEL0 & (~(0x3<<2))) | (0x01 << 2);
+	T0TCR  = 2;         /* Stop and reset the timer */
+	T0CTCR = 0;         /* Timer mode               */
+	
+	/* A 1ms tick does not require the use of the timer prescale.  This is
+	defaulted to zero but can be used if necessary. */
+	T0PR = portPRESCALE_VALUE;
+
+	/* Calculate the match value required for our wanted tick rate. */
+	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+	/* Protect against divide by zero.  Using an if() statement still results
+	in a warning - hence the #if. */
+	#if portPRESCALE_VALUE != 0
+	{
+		ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
+	}
+	#endif
+	T0MR1 = ulCompareMatch;
+
+	/* Generate tick with timer 0 compare match. */
+	T0MCR  = (3 << 3);  /* Reset timer on match and generate interrupt */
+
+	/* Setup the VIC for the timer. */
+	VICIntEnable = 0x00000010;
+	
+	/* The ISR installed depends on whether the preemptive or cooperative
+	scheduler is being used. */
+	#if configUSE_PREEMPTION == 1
+	{
+		extern void ( vPreemptiveTick )( void );
+		VICVectAddr4 = ( int32_t ) vPreemptiveTick;
+	}
+	#else
+	{
+		extern void ( vNonPreemptiveTick )( void );
+		VICVectAddr4 = ( int32_t ) vNonPreemptiveTick;
+	}
+	#endif
+
+	VICVectCntl4 = 1;
+
+	/* Start the timer - interrupts are disabled when this function is called
+	so it is okay to do this here. */
+	T0TCR = portENABLE_TIMER;
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portISR.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portISR.c
new file mode 100644
index 0000000..99d4803
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portISR.c
@@ -0,0 +1,218 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c  The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to handle interrupts. */
+#define portTIMER_MATCH_ISR_BIT		( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT		( ( uint32_t ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* ISR to handle manual context switches (from a call to taskYIELD()). */
+void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
+
+/* 
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+	/* Simply start the scheduler.  This is included here as it can only be
+	called from ARM mode. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ *
+ * When a context switch is performed from the task level the saved task 
+ * context is made to look as if it occurred from within the tick ISR.  This
+ * way the same restore context function can be used when restoring the context
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.
+ */
+void vPortYieldProcessor( void )
+{
+	/* Within an IRQ ISR the link register has an offset from the true return 
+	address, but an SWI ISR does not.  Add the offset manually so the same 
+	ISR return code can be used in both cases. */
+	__asm volatile ( "ADD		LR, LR, #4" );
+
+	/* Perform the context switch.  First save the context of the current task. */
+	portSAVE_CONTEXT();
+
+	/* Find the highest priority task that is ready to run. */
+	__asm volatile( "bl			vTaskSwitchContext" );
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();	
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+
+
+#if configUSE_PREEMPTION == 0
+
+	/* The cooperative scheduler requires a normal IRQ service routine to 
+	simply increment the system tick. */
+	void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
+	void vNonPreemptiveTick( void )
+	{	
+		xTaskIncrementTick();
+		T0IR = 2;
+		VICVectAddr = portCLEAR_VIC_INTERRUPT;
+	}
+
+#else
+
+	/* The preemptive scheduler is defined as "naked" as the full context is
+	saved on entry as part of the context switch. */
+	void vPreemptiveTick( void ) __attribute__((naked));
+	void vPreemptiveTick( void )
+	{
+		/* Save the context of the interrupted task. */
+		portSAVE_CONTEXT();	
+
+		/* Increment the RTOS tick count, then look for the highest priority 
+		task that is ready to run. */
+		__asm volatile
+		(
+			"	bl xTaskIncrementTick	\t\n" \
+			"	cmp r0, #0				\t\n" \
+			"	beq SkipContextSwitch	\t\n" \
+			"	bl vTaskSwitchContext	\t\n" \
+			"SkipContextSwitch:			\t\n"
+		);
+
+		/* Ready for the next interrupt. */
+		T0IR = 2;
+		VICVectAddr = portCLEAR_VIC_INTERRUPT;
+		
+		/* Restore the context of the new task. */
+		portRESTORE_CONTEXT();
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+#ifdef THUMB_INTERWORK
+
+	void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	void vPortDisableInterruptsFromThumb( void )
+	{
+		__asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+			
+	void vPortEnableInterruptsFromThumb( void )
+	{
+		__asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/	
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/	
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/	
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/	
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+
+#endif /* THUMB_INTERWORK */
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels.  The interrupt flags can therefore not always
+be saved to the stack.  Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
+	__asm volatile ( 
+		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
+		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
+		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
+		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
+		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed 
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable interrupts as per portEXIT_CRITICAL().					*/
+			__asm volatile ( 
+				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	
+				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	
+				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	
+				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	
+				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
+		}
+	}
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portmacro.h
new file mode 100644
index 0000000..db8331f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portmacro.h
@@ -0,0 +1,249 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+	Changes from V3.2.3
+
+	+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
+
+	Changes from V3.2.4
+
+	+ Removed the use of the %0 parameter within the assembler macros and
+	  replaced them with hard coded registers.  This will ensure the
+	  assembler does not select the link register as the temp register as
+	  was occasionally happening previously.
+
+	+ The assembler statements are now included in a single asm block rather
+	  than each line having its own asm block.
+
+	Changes from V4.5.0
+
+	+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
+	  and replaced them with portYIELD_FROM_ISR() macro.  Application code
+	  should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
+	  macros as per the V4.5.1 demo code.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	portLONG
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portNOP()					__asm volatile ( "NOP" );
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+
+/*
+ * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
+ * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
+ * are included here for efficiency.  An attempt to call one from
+ * THUMB mode code will result in a compile time error.
+ */
+
+#define portRESTORE_CONTEXT()											\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile uint32_t ulCriticalNesting;					\
+																		\
+	/* Set the LR to the task stack. */									\
+	__asm volatile (													\
+	"LDR		R0, =pxCurrentTCB								\n\t"	\
+	"LDR		R0, [R0]										\n\t"	\
+	"LDR		LR, [R0]										\n\t"	\
+																		\
+	/* The critical nesting depth is the first item on the stack. */	\
+	/* Load it into the ulCriticalNesting variable. */					\
+	"LDR		R0, =ulCriticalNesting							\n\t"	\
+	"LDMFD	LR!, {R1}											\n\t"	\
+	"STR		R1, [R0]										\n\t"	\
+																		\
+	/* Get the SPSR from the stack. */									\
+	"LDMFD	LR!, {R0}											\n\t"	\
+	"MSR		SPSR, R0										\n\t"	\
+																		\
+	/* Restore all system mode registers for the task. */				\
+	"LDMFD	LR, {R0-R14}^										\n\t"	\
+	"NOP														\n\t"	\
+																		\
+	/* Restore the return address. */									\
+	"LDR		LR, [LR, #+60]									\n\t"	\
+																		\
+	/* And return - correcting the offset in the LR to obtain the */	\
+	/* correct address. */												\
+	"SUBS	PC, LR, #4											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+/*-----------------------------------------------------------*/
+
+#define portSAVE_CONTEXT()												\
+{																		\
+extern volatile void * volatile pxCurrentTCB;							\
+extern volatile uint32_t ulCriticalNesting;					\
+																		\
+	/* Push R0 as we are going to use the register. */					\
+	__asm volatile (													\
+	"STMDB	SP!, {R0}											\n\t"	\
+																		\
+	/* Set R0 to point to the task stack pointer. */					\
+	"STMDB	SP,{SP}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	SP, SP, #4											\n\t"	\
+	"LDMIA	SP!,{R0}											\n\t"	\
+																		\
+	/* Push the return address onto the stack. */						\
+	"STMDB	R0!, {LR}											\n\t"	\
+																		\
+	/* Now we have saved LR we can use it instead of R0. */				\
+	"MOV	LR, R0												\n\t"	\
+																		\
+	/* Pop R0 so we can save it onto the system mode stack. */			\
+	"LDMIA	SP!, {R0}											\n\t"	\
+																		\
+	/* Push all the system mode registers onto the task stack. */		\
+	"STMDB	LR,{R0-LR}^											\n\t"	\
+	"NOP														\n\t"	\
+	"SUB	LR, LR, #60											\n\t"	\
+																		\
+	/* Push the SPSR onto the task stack. */							\
+	"MRS	R0, SPSR											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	"LDR	R0, =ulCriticalNesting								\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STMDB	LR!, {R0}											\n\t"	\
+																		\
+	/* Store the new top of stack for the task. */						\
+	"LDR	R0, =pxCurrentTCB									\n\t"	\
+	"LDR	R0, [R0]											\n\t"	\
+	"STR	LR, [R0]											\n\t"	\
+	);																	\
+	( void ) ulCriticalNesting;											\
+	( void ) pxCurrentTCB;												\
+}
+
+
+#define portYIELD_FROM_ISR()		vTaskSwitchContext()
+#define portYIELD()					__asm volatile ( "SWI 0" )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in
+ * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
+	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
+
+#else
+
+	#define portDISABLE_INTERRUPTS()											\
+		__asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+	#define portENABLE_INTERRUPTS()												\
+		__asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
new file mode 100644
index 0000000..63ea94c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
@@ -0,0 +1,518 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
+	#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
+	#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configUNIQUE_INTERRUPT_PRIORITIES
+	#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configSETUP_TICK_INTERRUPT
+	#error configSETUP_TICK_INTERRUPT() must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif /* configSETUP_TICK_INTERRUPT */
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/* In case security extensions are implemented. */
+#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+#endif
+
+/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
+portmacro.h. */
+#ifndef configCLEAR_TICK_INTERRUPT
+	#define configCLEAR_TICK_INTERRUPT()
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING			( ( size_t ) 0 )
+
+/* In all GICs 255 can be written to the priority mask register to unmask all
+(but the lowest) interrupt priority. */
+#define portUNMASK_VALUE				( 0xFFUL )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created.  A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portSP_ELx						( ( StackType_t ) 0x01 )
+#define portSP_EL0						( ( StackType_t ) 0x00 )
+
+#if defined( GUEST )
+	#define portEL1						( ( StackType_t ) 0x04 )
+	#define portINITIAL_PSTATE				( portEL1 | portSP_EL0 )
+#else
+	#define portEL3						( ( StackType_t ) 0x0c )
+	/* At the time of writing, the BSP only supports EL3. */
+	#define portINITIAL_PSTATE			( portEL3 | portSP_EL0 )
+#endif
+
+
+/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
+point is zero. */
+#define portBINARY_POINT_BITS			( ( uint8_t ) 0x03 )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK			( 0x0C )
+
+/* The I bit in the DAIF bits. */
+#define portDAIF_I						( 0x80 )
+
+/* Macro to unmask all interrupt priorities. */
+#define portCLEAR_INTERRUPT_MASK()									\
+{																	\
+	portDISABLE_INTERRUPTS();										\
+	portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;			\
+	__asm volatile (	"DSB SY		\n"								\
+						"ISB SY		\n" );							\
+	portENABLE_INTERRUPTS();										\
+}
+
+/* Hardware specifics used when sanity checking the configuration. */
+#define portINTERRUPT_PRIORITY_REGISTER_OFFSET		0x400UL
+#define portMAX_8_BIT_VALUE							( ( uint8_t ) 0xff )
+#define portBIT_0_SET								( ( uint8_t ) 0x01 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.  This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts.  As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint64_t ullCriticalNesting = 9999ULL;
+
+/* Saved as part of the task context.  If ullPortTaskHasFPUContext is non-zero
+then floating point context must be saved and restored for the task. */
+uint64_t ullPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+uint64_t ullPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth.  A context switch is only performed if
+if the nesting depth is 0. */
+uint64_t ullPortInterruptNesting = 0;
+
+/* Used in the ASM code. */
+__attribute__(( used )) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
+__attribute__(( used )) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
+__attribute__(( used )) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
+__attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First all the general purpose registers. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0101010101010101ULL;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0303030303030303ULL;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0202020202020202ULL;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0505050505050505ULL;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0404040404040404ULL;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0707070707070707ULL;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0606060606060606ULL;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0909090909090909ULL;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x0808080808080808ULL;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1111111111111111ULL;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1010101010101010ULL;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1313131313131313ULL;	/* R13 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1212121212121212ULL;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1515151515151515ULL;	/* R15 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1414141414141414ULL;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1717171717171717ULL;	/* R17 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1616161616161616ULL;	/* R16 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1919191919191919ULL;	/* R19 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x1818181818181818ULL;	/* R18 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2121212121212121ULL;	/* R21 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2020202020202020ULL;	/* R20 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2323232323232323ULL;	/* R23 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2222222222222222ULL;	/* R22 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2525252525252525ULL;	/* R25 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2424242424242424ULL;	/* R24 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2727272727272727ULL;	/* R27 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2626262626262626ULL;	/* R26 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2929292929292929ULL;	/* R29 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2828282828282828ULL;	/* R28 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00;	/* XZR - has no effect, used so there are an even number of registers. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00;	/* R30 - procedure call link register. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = portINITIAL_PSTATE;
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
+	pxTopOfStack--;
+
+	/* The task will start with a critical nesting count of 0 as interrupts are
+	enabled. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+	pxTopOfStack--;
+
+	/* The task will start without a floating point context.  A task that uses
+	the floating point hardware must call vPortTaskUsesFPU() before executing
+	any floating point instructions. */
+	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine how many priority bits are implemented in the GIC.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to
+		all possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Shift to the least significant bits. */
+		while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
+		{
+			ucMaxPriorityValue >>= ( uint8_t ) 0x01;
+		}
+
+		/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
+		value. */
+
+		configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
+
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+
+	/* At the time of writing, the BSP only supports EL3. */
+	__asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
+	ulAPSR &= portAPSR_MODE_BITS_MASK;
+
+#if defined( GUEST )
+	#warning Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH.
+	configASSERT( ulAPSR == portEL1 );
+	if( ulAPSR == portEL1 )
+#else
+	configASSERT( ulAPSR == portEL3 );
+	if( ulAPSR == portEL3 )
+#endif
+	{
+		/* Only continue if the binary point value is set to its lowest possible
+		setting.  See the comments in vPortValidateInterruptPriority() below for
+		more information. */
+		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+
+		if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+		{
+			/* Interrupts are turned off in the CPU itself to ensure a tick does
+			not execute	while the scheduler is being started.  Interrupts are
+			automatically turned back on in the CPU when the first task starts
+			executing. */
+			portDISABLE_INTERRUPTS();
+
+			/* Start the timer that generates the tick ISR. */
+			configSETUP_TICK_INTERRUPT();
+
+			/* Start the first task executing. */
+			vPortRestoreTaskContext();
+		}
+	}
+
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ullCriticalNesting == 1000ULL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Mask interrupts up to the max syscall interrupt priority. */
+	uxPortSetInterruptMask();
+
+	/* Now interrupts are disabled ullCriticalNesting can be accessed
+	directly.  Increment ullCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ullCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( ullCriticalNesting == 1ULL )
+	{
+		configASSERT( ullPortInterruptNesting == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ullCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as the critical section is being
+		exited. */
+		ullCriticalNesting--;
+
+		/* If the nesting level has reached zero then all interrupt
+		priorities must be re-enabled. */
+		if( ullCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Critical nesting has reached zero so all interrupt priorities
+			should be unmasked. */
+			portCLEAR_INTERRUPT_MASK();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+	/* Must be the lowest possible priority. */
+	#if !defined( QEMU )
+	{
+		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+	}
+	#endif
+
+	/* Interrupts should not be enabled before this point. */
+	#if( configASSERT_DEFINED == 1 )
+	{
+		uint32_t ulMaskBits;
+
+		__asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) :: "memory" );
+		configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );
+	}
+	#endif /* configASSERT_DEFINED */
+
+	/* Set interrupt mask before altering scheduler structures.   The tick
+	handler runs at the lowest priority, so interrupts cannot already be masked,
+	so there is no need to save and restore the current mask value.  It is
+	necessary to turn off interrupts in the CPU itself while the ICCPMR is being
+	updated. */
+	portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+	__asm volatile (	"dsb sy		\n"
+						"isb sy		\n" ::: "memory" );
+
+	/* Ok to enable interrupts after the interrupt source has been cleared. */
+	configCLEAR_TICK_INTERRUPT();
+	portENABLE_INTERRUPTS();
+
+	/* Increment the RTOS tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		ullPortYieldRequired = pdTRUE;
+	}
+
+	/* Ensure all interrupt priorities are active again. */
+	portCLEAR_INTERRUPT_MASK();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+	/* A task is registering the fact that it needs an FPU context.  Set the
+	FPU flag (which is saved as part of the task context). */
+	ullPortTaskHasFPUContext = pdTRUE;
+
+	/* Consider initialising the FPSR here - but probably not necessary in
+	AArch64. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
+{
+	if( uxNewMaskValue == pdFALSE )
+	{
+		portCLEAR_INTERRUPT_MASK();
+	}
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxPortSetInterruptMask( void )
+{
+uint32_t ulReturn;
+
+	/* Interrupt in the CPU must be turned off while the ICCPMR is being
+	updated. */
+	portDISABLE_INTERRUPTS();
+	if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+	{
+		/* Interrupts were already masked. */
+		ulReturn = pdTRUE;
+	}
+	else
+	{
+		ulReturn = pdFALSE;
+		portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+		__asm volatile (	"dsb sy		\n"
+							"isb sy		\n" ::: "memory" );
+	}
+	portENABLE_INTERRUPTS();
+
+	return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+		/* The following assertion will fail if a service routine (ISR) for
+		an interrupt that has been assigned a priority above
+		configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+		function.  ISR safe FreeRTOS API functions must *only* be called
+		from interrupts that have been assigned a priority at or below
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		Numerically low interrupt priority numbers represent logically high
+		interrupt priorities, therefore the priority of the interrupt must
+		be set to a value equal to or numerically *higher* than
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		FreeRTOS maintains separate thread and ISR API functions to ensure
+		interrupt entry is as fast and simple as possible. */
+		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+		/* Priority grouping:  The interrupt controller (GIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		The priority grouping is configured by the GIC's binary point register
+		(ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
+		possible value (which may be above 0). */
+		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+	}
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S
new file mode 100644
index 0000000..80cb574
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S
@@ -0,0 +1,431 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	.text
+
+	/* Variables and functions. */
+	.extern ullMaxAPIPriorityMask
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern vApplicationIRQHandler
+	.extern ullPortInterruptNesting
+	.extern ullPortTaskHasFPUContext
+	.extern ullCriticalNesting
+	.extern ullPortYieldRequired
+	.extern ullICCEOIR
+	.extern ullICCIAR
+	.extern _freertos_vector_table
+
+	.global FreeRTOS_IRQ_Handler
+	.global FreeRTOS_SWI_Handler
+	.global vPortRestoreTaskContext
+
+
+.macro portSAVE_CONTEXT
+
+	/* Switch to use the EL0 stack pointer. */
+	MSR 	SPSEL, #0
+
+	/* Save the entire context. */
+	STP 	X0, X1, [SP, #-0x10]!
+	STP 	X2, X3, [SP, #-0x10]!
+	STP 	X4, X5, [SP, #-0x10]!
+	STP 	X6, X7, [SP, #-0x10]!
+	STP 	X8, X9, [SP, #-0x10]!
+	STP 	X10, X11, [SP, #-0x10]!
+	STP 	X12, X13, [SP, #-0x10]!
+	STP 	X14, X15, [SP, #-0x10]!
+	STP 	X16, X17, [SP, #-0x10]!
+	STP 	X18, X19, [SP, #-0x10]!
+	STP 	X20, X21, [SP, #-0x10]!
+	STP 	X22, X23, [SP, #-0x10]!
+	STP 	X24, X25, [SP, #-0x10]!
+	STP 	X26, X27, [SP, #-0x10]!
+	STP 	X28, X29, [SP, #-0x10]!
+	STP 	X30, XZR, [SP, #-0x10]!
+
+	/* Save the SPSR. */
+#if defined( GUEST )
+	MRS		X3, SPSR_EL1
+	MRS		X2, ELR_EL1
+#else
+	MRS		X3, SPSR_EL3
+	/* Save the ELR. */
+	MRS		X2, ELR_EL3
+#endif
+
+	STP 	X2, X3, [SP, #-0x10]!
+
+	/* Save the critical section nesting depth. */
+	LDR		X0, ullCriticalNestingConst
+	LDR		X3, [X0]
+
+	/* Save the FPU context indicator. */
+	LDR		X0, ullPortTaskHasFPUContextConst
+	LDR		X2, [X0]
+
+	/* Save the FPU context, if any (32 128-bit registers). */
+	CMP		X2, #0
+	B.EQ	1f
+	STP		Q0, Q1, [SP,#-0x20]!
+	STP		Q2, Q3, [SP,#-0x20]!
+	STP		Q4, Q5, [SP,#-0x20]!
+	STP		Q6, Q7, [SP,#-0x20]!
+	STP		Q8, Q9, [SP,#-0x20]!
+	STP		Q10, Q11, [SP,#-0x20]!
+	STP		Q12, Q13, [SP,#-0x20]!
+	STP		Q14, Q15, [SP,#-0x20]!
+	STP		Q16, Q17, [SP,#-0x20]!
+	STP		Q18, Q19, [SP,#-0x20]!
+	STP		Q20, Q21, [SP,#-0x20]!
+	STP		Q22, Q23, [SP,#-0x20]!
+	STP		Q24, Q25, [SP,#-0x20]!
+	STP		Q26, Q27, [SP,#-0x20]!
+	STP		Q28, Q29, [SP,#-0x20]!
+	STP		Q30, Q31, [SP,#-0x20]!
+
+1:
+	/* Store the critical nesting count and FPU context indicator. */
+	STP 	X2, X3, [SP, #-0x10]!
+
+	LDR 	X0, pxCurrentTCBConst
+	LDR 	X1, [X0]
+	MOV 	X0, SP   /* Move SP into X0 for saving. */
+	STR 	X0, [X1]
+
+	/* Switch to use the ELx stack pointer. */
+	MSR 	SPSEL, #1
+
+	.endm
+
+; /**********************************************************************/
+
+.macro portRESTORE_CONTEXT
+
+	/* Switch to use the EL0 stack pointer. */
+	MSR 	SPSEL, #0
+
+	/* Set the SP to point to the stack of the task being restored. */
+	LDR		X0, pxCurrentTCBConst
+	LDR		X1, [X0]
+	LDR		X0, [X1]
+	MOV		SP, X0
+
+	LDP 	X2, X3, [SP], #0x10  /* Critical nesting and FPU context. */
+
+	/* Set the PMR register to be correct for the current critical nesting
+	depth. */
+	LDR		X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
+	MOV		X1, #255					/* X1 holds the unmask value. */
+	LDR		X4, ullICCPMRConst			/* X4 holds the address of the ICCPMR constant. */
+	CMP		X3, #0
+	LDR		X5, [X4] 					/* X5 holds the address of the ICCPMR register. */
+	B.EQ	1f
+	LDR		X6, ullMaxAPIPriorityMaskConst
+	LDR		X1, [X6]					/* X1 holds the mask value. */
+1:
+	STR		W1, [X5]					/* Write the mask value to ICCPMR. */
+	DSB 	SY							/* _RB_Barriers probably not required here. */
+	ISB 	SY
+	STR		X3, [X0]					/* Restore the task's critical nesting count. */
+
+	/* Restore the FPU context indicator. */
+	LDR		X0, ullPortTaskHasFPUContextConst
+	STR		X2, [X0]
+
+	/* Restore the FPU context, if any. */
+	CMP		X2, #0
+	B.EQ	1f
+	LDP		Q30, Q31, [SP], #0x20
+	LDP		Q28, Q29, [SP], #0x20
+	LDP		Q26, Q27, [SP], #0x20
+	LDP		Q24, Q25, [SP], #0x20
+	LDP		Q22, Q23, [SP], #0x20
+	LDP		Q20, Q21, [SP], #0x20
+	LDP		Q18, Q19, [SP], #0x20
+	LDP		Q16, Q17, [SP], #0x20
+	LDP		Q14, Q15, [SP], #0x20
+	LDP		Q12, Q13, [SP], #0x20
+	LDP		Q10, Q11, [SP], #0x20
+	LDP		Q8, Q9, [SP], #0x20
+	LDP		Q6, Q7, [SP], #0x20
+	LDP		Q4, Q5, [SP], #0x20
+	LDP		Q2, Q3, [SP], #0x20
+	LDP		Q0, Q1, [SP], #0x20
+1:
+	LDP 	X2, X3, [SP], #0x10  /* SPSR and ELR. */
+
+#if defined( GUEST )
+	/* Restore the SPSR. */
+	MSR		SPSR_EL1, X3
+	/* Restore the ELR. */
+	MSR		ELR_EL1, X2
+#else
+	/* Restore the SPSR. */
+	MSR		SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
+	/* Restore the ELR. */
+	MSR		ELR_EL3, X2
+#endif
+
+	LDP 	X30, XZR, [SP], #0x10
+	LDP 	X28, X29, [SP], #0x10
+	LDP 	X26, X27, [SP], #0x10
+	LDP 	X24, X25, [SP], #0x10
+	LDP 	X22, X23, [SP], #0x10
+	LDP 	X20, X21, [SP], #0x10
+	LDP 	X18, X19, [SP], #0x10
+	LDP 	X16, X17, [SP], #0x10
+	LDP 	X14, X15, [SP], #0x10
+	LDP 	X12, X13, [SP], #0x10
+	LDP 	X10, X11, [SP], #0x10
+	LDP 	X8, X9, [SP], #0x10
+	LDP 	X6, X7, [SP], #0x10
+	LDP 	X4, X5, [SP], #0x10
+	LDP 	X2, X3, [SP], #0x10
+	LDP 	X0, X1, [SP], #0x10
+
+	/* Switch to use the ELx stack pointer.  _RB_ Might not be required. */
+	MSR 	SPSEL, #1
+
+	ERET
+
+	.endm
+
+
+/******************************************************************************
+ * FreeRTOS_SWI_Handler handler is used to perform a context switch.
+ *****************************************************************************/
+.align 8
+.type FreeRTOS_SWI_Handler, %function
+FreeRTOS_SWI_Handler:
+	/* Save the context of the current task and select a new task to run. */
+	portSAVE_CONTEXT
+#if defined( GUEST )
+	MRS		X0, ESR_EL1
+#else
+	MRS		X0, ESR_EL3
+#endif
+
+	LSR		X1, X0, #26
+
+#if defined( GUEST )
+	CMP		X1, #0x15 	/* 0x15 = SVC instruction. */
+#else
+	CMP		X1, #0x17 	/* 0x17 = SMC instruction. */
+#endif
+	B.NE	FreeRTOS_Abort
+	BL 		vTaskSwitchContext
+
+	portRESTORE_CONTEXT
+
+FreeRTOS_Abort:
+	/* Full ESR is in X0, exception class code is in X1. */
+	B		.
+
+/******************************************************************************
+ * vPortRestoreTaskContext is used to start the scheduler.
+ *****************************************************************************/
+.align 8
+.type vPortRestoreTaskContext, %function
+vPortRestoreTaskContext:
+.set freertos_vector_base,	_freertos_vector_table
+
+	/* Install the FreeRTOS interrupt handlers. */
+	LDR		X1, =freertos_vector_base
+#if defined( GUEST )
+	MSR		VBAR_EL1, X1
+#else
+	MSR		VBAR_EL3, X1
+#endif
+	DSB		SY
+	ISB		SY
+
+	/* Start the first task. */
+	portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * FreeRTOS_IRQ_Handler handles IRQ entry and exit.
+ *****************************************************************************/
+.align 8
+.type FreeRTOS_IRQ_Handler, %function
+FreeRTOS_IRQ_Handler:
+	/* Save volatile registers. */
+	STP		X0, X1, [SP, #-0x10]!
+	STP		X2, X3, [SP, #-0x10]!
+	STP		X4, X5, [SP, #-0x10]!
+	STP		X6, X7, [SP, #-0x10]!
+	STP		X8, X9, [SP, #-0x10]!
+	STP		X10, X11, [SP, #-0x10]!
+	STP		X12, X13, [SP, #-0x10]!
+	STP		X14, X15, [SP, #-0x10]!
+	STP		X16, X17, [SP, #-0x10]!
+	STP		X18, X19, [SP, #-0x10]!
+	STP		X29, X30, [SP, #-0x10]!
+
+	/* Save the SPSR and ELR. */
+#if defined( GUEST )
+	MRS		X3, SPSR_EL1
+	MRS		X2, ELR_EL1
+#else
+	MRS		X3, SPSR_EL3
+	MRS		X2, ELR_EL3
+#endif
+	STP 	X2, X3, [SP, #-0x10]!
+
+	/* Increment the interrupt nesting counter. */
+	LDR		X5, ullPortInterruptNestingConst
+	LDR		X1, [X5]	/* Old nesting count in X1. */
+	ADD		X6, X1, #1
+	STR		X6, [X5]	/* Address of nesting count variable in X5. */
+
+	/* Maintain the interrupt nesting information across the function call. */
+	STP		X1, X5, [SP, #-0x10]!
+
+	/* Read value from the interrupt acknowledge register, which is stored in W0
+	for future parameter and interrupt clearing use. */
+	LDR 	X2, ullICCIARConst
+	LDR		X3, [X2]
+	LDR		W0, [X3]	/* ICCIAR in W0 as parameter. */
+
+	/* Maintain the ICCIAR value across the function call. */
+	STP		X0, X1, [SP, #-0x10]!
+
+	/* Call the C handler. */
+	BL vApplicationIRQHandler
+
+	/* Disable interrupts. */
+	MSR 	DAIFSET, #2
+	DSB		SY
+	ISB		SY
+
+	/* Restore the ICCIAR value. */
+	LDP		X0, X1, [SP], #0x10
+
+	/* End IRQ processing by writing ICCIAR to the EOI register. */
+	LDR 	X4, ullICCEOIRConst
+	LDR		X4, [X4]
+	STR		W0, [X4]
+
+	/* Restore the critical nesting count. */
+	LDP		X1, X5, [SP], #0x10
+	STR		X1, [X5]
+
+	/* Has interrupt nesting unwound? */
+	CMP		X1, #0
+	B.NE	Exit_IRQ_No_Context_Switch
+
+	/* Is a context switch required? */
+	LDR		X0, ullPortYieldRequiredConst
+	LDR		X1, [X0]
+	CMP		X1, #0
+	B.EQ	Exit_IRQ_No_Context_Switch
+
+	/* Reset ullPortYieldRequired to 0. */
+	MOV		X2, #0
+	STR		X2, [X0]
+
+	/* Restore volatile registers. */
+	LDP 	X4, X5, [SP], #0x10  /* SPSR and ELR. */
+#if defined( GUEST )
+	MSR		SPSR_EL1, X5
+	MSR		ELR_EL1, X4
+#else
+	MSR		SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
+	MSR		ELR_EL3, X4
+#endif
+	DSB		SY
+	ISB		SY
+
+	LDP		X29, X30, [SP], #0x10
+	LDP		X18, X19, [SP], #0x10
+	LDP		X16, X17, [SP], #0x10
+	LDP		X14, X15, [SP], #0x10
+	LDP		X12, X13, [SP], #0x10
+	LDP		X10, X11, [SP], #0x10
+	LDP		X8, X9, [SP], #0x10
+	LDP		X6, X7, [SP], #0x10
+	LDP		X4, X5, [SP], #0x10
+	LDP		X2, X3, [SP], #0x10
+	LDP		X0, X1, [SP], #0x10
+
+	/* Save the context of the current task and select a new task to run. */
+	portSAVE_CONTEXT
+	BL vTaskSwitchContext
+	portRESTORE_CONTEXT
+
+Exit_IRQ_No_Context_Switch:
+	/* Restore volatile registers. */
+	LDP 	X4, X5, [SP], #0x10  /* SPSR and ELR. */
+#if defined( GUEST )
+	MSR		SPSR_EL1, X5
+	MSR		ELR_EL1, X4
+#else
+	MSR		SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
+	MSR		ELR_EL3, X4
+#endif
+	DSB		SY
+	ISB		SY
+
+	LDP		X29, X30, [SP], #0x10
+	LDP		X18, X19, [SP], #0x10
+	LDP		X16, X17, [SP], #0x10
+	LDP		X14, X15, [SP], #0x10
+	LDP		X12, X13, [SP], #0x10
+	LDP		X10, X11, [SP], #0x10
+	LDP		X8, X9, [SP], #0x10
+	LDP		X6, X7, [SP], #0x10
+	LDP		X4, X5, [SP], #0x10
+	LDP		X2, X3, [SP], #0x10
+	LDP		X0, X1, [SP], #0x10
+
+	ERET
+
+
+
+
+.align 8
+pxCurrentTCBConst: .dword pxCurrentTCB
+ullCriticalNestingConst: .dword ullCriticalNesting
+ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext
+
+ullICCPMRConst: .dword ullICCPMR
+ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask
+vApplicationIRQHandlerConst: .word vApplicationIRQHandler
+ullPortInterruptNestingConst: .dword ullPortInterruptNesting
+ullPortYieldRequiredConst: .dword ullPortYieldRequired
+ullICCIARConst:	.dword ullICCIAR
+ullICCEOIRConst: .dword ullICCEOIR
+
+
+
+.end
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
new file mode 100644
index 0000000..8215504
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
@@ -0,0 +1,211 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+	extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	size_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef portBASE_TYPE BaseType_t;
+typedef uint64_t UBaseType_t;
+
+typedef uint64_t TickType_t;
+#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			16
+#define portPOINTER_SIZE_TYPE 		uint64_t
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{												\
+extern uint64_t ullPortYieldRequired;			\
+												\
+	if( xSwitchRequired != pdFALSE )			\
+	{											\
+		ullPortYieldRequired = pdTRUE;			\
+	}											\
+}
+
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#if defined( GUEST )
+	#define portYIELD() __asm volatile ( "SVC 0" ::: "memory" )
+#else
+	#define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )
+#endif
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern UBaseType_t uxPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
+
+#define portDISABLE_INTERRUPTS()									\
+	__asm volatile ( "MSR DAIFSET, #2" ::: "memory" );				\
+	__asm volatile ( "DSB SY" );									\
+	__asm volatile ( "ISB SY" );
+
+#define portENABLE_INTERRUPTS()										\
+	__asm volatile ( "MSR DAIFCLR, #2" ::: "memory" );				\
+	__asm volatile ( "DSB SY" );									\
+	__asm volatile ( "ISB SY" );
+
+
+/* These macros do not globally disable/enable interrupts.  They do mask off
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+#define portSET_INTERRUPT_MASK_FROM_ISR()		uxPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask(x)
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif /* configASSERT */
+
+#define portNOP() __asm volatile( "NOP" )
+#define portINLINE __inline
+
+#ifdef __cplusplus
+	} /* extern C */
+#endif
+
+
+/* The number of bits to shift for an interrupt priority is dependent on the
+number of bits implemented by the interrupt controller. */
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16
+	#define portPRIORITY_SHIFT 4
+	#define portMAX_BINARY_POINT_VALUE	3
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
+	#define portPRIORITY_SHIFT 3
+	#define portMAX_BINARY_POINT_VALUE	2
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
+	#define portPRIORITY_SHIFT 2
+	#define portMAX_BINARY_POINT_VALUE	1
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
+	#define portPRIORITY_SHIFT 1
+	#define portMAX_BINARY_POINT_VALUE	0
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
+	#define portPRIORITY_SHIFT 0
+	#define portMAX_BINARY_POINT_VALUE	0
+#else
+	#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+#endif
+
+/* Interrupt controller access addresses. */
+#define portICCPMR_PRIORITY_MASK_OFFSET  						( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET 				( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET 					( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET							( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET						( 0x14 )
+
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS 		( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER 					( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS 	( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS 		( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS 			( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER 					( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER 				( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c
new file mode 100644
index 0000000..3b62283
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c
@@ -0,0 +1,568 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
+	#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
+	#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configUNIQUE_INTERRUPT_PRIORITIES
+	#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configSETUP_TICK_INTERRUPT
+	#error configSETUP_TICK_INTERRUPT() must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif /* configSETUP_TICK_INTERRUPT */
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/* In case security extensions are implemented. */
+#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+#endif
+
+/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
+portmacro.h. */
+#ifndef configCLEAR_TICK_INTERRUPT
+	#define configCLEAR_TICK_INTERRUPT()
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
+
+/* In all GICs 255 can be written to the priority mask register to unmask all
+(but the lowest) interrupt priority. */
+#define portUNMASK_VALUE				( 0xFFUL )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created.  A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINTERRUPT_ENABLE_BIT		( 0x80UL )
+#define portTHUMB_MODE_ADDRESS			( 0x01UL )
+
+/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
+point is zero. */
+#define portBINARY_POINT_BITS			( ( uint8_t ) 0x03 )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK			( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+mode. */
+#define portAPSR_USER_MODE				( 0x10 )
+
+/* The critical section macros only mask interrupts up to an application
+determined priority level.  Sometimes it is necessary to turn interrupt off in
+the CPU itself before modifying certain hardware registers. */
+#define portCPU_IRQ_DISABLE()										\
+	__asm volatile ( "CPSID i" ::: "memory" );						\
+	__asm volatile ( "DSB" );										\
+	__asm volatile ( "ISB" );
+
+#define portCPU_IRQ_ENABLE()										\
+	__asm volatile ( "CPSIE i" ::: "memory" );						\
+	__asm volatile ( "DSB" );										\
+	__asm volatile ( "ISB" );
+
+
+/* Macro to unmask all interrupt priorities. */
+#define portCLEAR_INTERRUPT_MASK()									\
+{																	\
+	portCPU_IRQ_DISABLE();											\
+	portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;			\
+	__asm volatile (	"DSB		\n"								\
+						"ISB		\n" );							\
+	portCPU_IRQ_ENABLE();											\
+}
+
+#define portINTERRUPT_PRIORITY_REGISTER_OFFSET		0x400UL
+#define portMAX_8_BIT_VALUE							( ( uint8_t ) 0xff )
+#define portBIT_0_SET								( ( uint8_t ) 0x01 )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/* The space on the stack required to hold the FPU registers.  This is 32 64-bit
+registers, plus a 32-bit status register. */
+#define portFPU_REGISTER_WORDS	( ( 32 * 2 ) + 1 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.  This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*
+ * If the application provides an implementation of vApplicationIRQHandler(),
+ * then it will get called directly without saving the FPU registers on
+ * interrupt entry, and this weak implementation of
+ * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -
+ * it should never actually get called so its implementation contains a
+ * call to configASSERT() that will always fail.
+ *
+ * If the application provides its own implementation of
+ * vApplicationFPUSafeIRQHandler() then the implementation of
+ * vApplicationIRQHandler() provided in portASM.S will save the FPU registers
+ * before calling it.
+ *
+ * Therefore, if the application writer wants FPU registers to be saved on
+ * interrupt entry their IRQ handler must be called
+ * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
+ * FPU registers to be saved on interrupt entry their IRQ handler must be
+ * called vApplicationIRQHandler().
+ */
+void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts.  As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
+a floating point context must be saved and restored for the task. */
+volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+volatile uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth.  A context switch is only performed if
+if the nesting depth is 0. */
+volatile uint32_t ulPortInterruptNesting = 0UL;
+
+/* Used in the asm file. */
+__attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
+__attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
+__attribute__(( used )) const uint32_t ulICCPMR	= portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
+__attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro.
+
+	The fist real value on the stack is the status register, which is set for
+	system mode, with interrupts enabled.  A few NULLs are added first to ensure
+	GDB does not try decoding a non-existent return address. */
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+	{
+		/* The task will start in THUMB mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* Next the return address, which in this case is the start of the task. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	/* Next all the registers other than the stack pointer. */
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The task will start with a critical nesting count of 0 as interrupts are
+	enabled. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+
+	#if( configUSE_TASK_FPU_SUPPORT == 1 )
+	{
+		/* The task will start without a floating point context.  A task that
+		uses the floating point hardware must call vPortTaskUsesFPU() before
+		executing any floating point instructions. */
+		pxTopOfStack--;
+		*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+	}
+	#elif( configUSE_TASK_FPU_SUPPORT == 2 )
+	{
+		/* The task will start with a floating point context.  Leave enough
+		space for the registers - and ensure they are initialised to 0. */
+		pxTopOfStack -= portFPU_REGISTER_WORDS;
+		memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
+
+		pxTopOfStack--;
+		*pxTopOfStack = pdTRUE;
+		ulPortTaskHasFPUContext = pdTRUE;
+	}
+	#else
+	{
+		#error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.
+	}
+	#endif
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( ulPortInterruptNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine how many priority bits are implemented in the GIC.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to
+		all possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Shift to the least significant bits. */
+		while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
+		{
+			ucMaxPriorityValue >>= ( uint8_t ) 0x01;
+		}
+
+		/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
+		value. */
+		configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+
+	/* Only continue if the CPU is not in User mode.  The CPU must be in a
+	Privileged mode for the scheduler to start. */
+	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
+	ulAPSR &= portAPSR_MODE_BITS_MASK;
+	configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+	if( ulAPSR != portAPSR_USER_MODE )
+	{
+		/* Only continue if the binary point value is set to its lowest possible
+		setting.  See the comments in vPortValidateInterruptPriority() below for
+		more information. */
+		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+
+		if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+		{
+			/* Interrupts are turned off in the CPU itself to ensure tick does
+			not execute	while the scheduler is being started.  Interrupts are
+			automatically turned back on in the CPU when the first task starts
+			executing. */
+			portCPU_IRQ_DISABLE();
+
+			/* Start the timer that generates the tick ISR. */
+			configSETUP_TICK_INTERRUPT();
+
+			/* Start the first task executing. */
+			vPortRestoreTaskContext();
+		}
+	}
+
+	/* Will only get here if vTaskStartScheduler() was called with the CPU in
+	a non-privileged mode or the binary point register was not set to its lowest
+	possible value.  prvTaskExitError() is referenced to prevent a compiler
+	warning about it being defined but not referenced in the case that the user
+	defines their own exit address. */
+	( void ) prvTaskExitError;
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Mask interrupts up to the max syscall interrupt priority. */
+	ulPortSetInterruptMask();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( ulCriticalNesting == 1 )
+	{
+		configASSERT( ulPortInterruptNesting == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as the critical section is being
+		exited. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then all interrupt
+		priorities must be re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Critical nesting has reached zero so all interrupt priorities
+			should be unmasked. */
+			portCLEAR_INTERRUPT_MASK();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+	/* Set interrupt mask before altering scheduler structures.   The tick
+	handler runs at the lowest priority, so interrupts cannot already be masked,
+	so there is no need to save and restore the current mask value.  It is
+	necessary to turn off interrupts in the CPU itself while the ICCPMR is being
+	updated. */
+	portCPU_IRQ_DISABLE();
+	portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+	__asm volatile (	"dsb		\n"
+						"isb		\n" ::: "memory" );
+	portCPU_IRQ_ENABLE();
+
+	/* Increment the RTOS tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		ulPortYieldRequired = pdTRUE;
+	}
+
+	/* Ensure all interrupt priorities are active again. */
+	portCLEAR_INTERRUPT_MASK();
+	configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_FPU_SUPPORT != 2 )
+
+	void vPortTaskUsesFPU( void )
+	{
+	uint32_t ulInitialFPSCR = 0;
+
+		/* A task is registering the fact that it needs an FPU context.  Set the
+		FPU flag (which is saved as part of the task context). */
+		ulPortTaskHasFPUContext = pdTRUE;
+
+		/* Initialise the floating point status register. */
+		__asm volatile ( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
+	}
+
+#endif /* configUSE_TASK_FPU_SUPPORT */
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( uint32_t ulNewMaskValue )
+{
+	if( ulNewMaskValue == pdFALSE )
+	{
+		portCLEAR_INTERRUPT_MASK();
+	}
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortSetInterruptMask( void )
+{
+uint32_t ulReturn;
+
+	/* Interrupt in the CPU must be turned off while the ICCPMR is being
+	updated. */
+	portCPU_IRQ_DISABLE();
+	if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+	{
+		/* Interrupts were already masked. */
+		ulReturn = pdTRUE;
+	}
+	else
+	{
+		ulReturn = pdFALSE;
+		portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+		__asm volatile (	"dsb		\n"
+							"isb		\n" ::: "memory" );
+	}
+	portCPU_IRQ_ENABLE();
+
+	return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+		/* The following assertion will fail if a service routine (ISR) for
+		an interrupt that has been assigned a priority above
+		configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+		function.  ISR safe FreeRTOS API functions must *only* be called
+		from interrupts that have been assigned a priority at or below
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		Numerically low interrupt priority numbers represent logically high
+		interrupt priorities, therefore the priority of the interrupt must
+		be set to a value equal to or numerically *higher* than
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		FreeRTOS maintains separate thread and ISR API functions to ensure
+		interrupt entry is as fast and simple as possible. */
+		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+		/* Priority grouping:  The interrupt controller (GIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		The priority grouping is configured by the GIC's binary point register
+		(ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
+		possible value (which may be above 0). */
+		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+	}
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
+
+void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR )
+{
+	( void ) ulICCIAR;
+	configASSERT( ( volatile void * ) NULL );
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA9/portASM.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA9/portASM.S
new file mode 100644
index 0000000..d3aff1e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA9/portASM.S
@@ -0,0 +1,323 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+	.eabi_attribute Tag_ABI_align_preserved, 1
+	.text
+	.arm
+
+	.set SYS_MODE,	0x1f
+	.set SVC_MODE,	0x13
+	.set IRQ_MODE,	0x12
+
+	/* Hardware registers. */
+	.extern ulICCIAR
+	.extern ulICCEOIR
+	.extern ulICCPMR
+
+	/* Variables and functions. */
+	.extern ulMaxAPIPriorityMask
+	.extern _freertos_vector_table
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern vApplicationIRQHandler
+	.extern ulPortInterruptNesting
+	.extern ulPortTaskHasFPUContext
+
+	.global FreeRTOS_IRQ_Handler
+	.global FreeRTOS_SWI_Handler
+	.global vPortRestoreTaskContext
+
+
+
+
+.macro portSAVE_CONTEXT
+
+	/* Save the LR and SPSR onto the system mode stack before switching to
+	system mode to save the remaining system mode registers. */
+	SRSDB	sp!, #SYS_MODE
+	CPS		#SYS_MODE
+	PUSH	{R0-R12, R14}
+
+	/* Push the critical nesting count. */
+	LDR		R2, ulCriticalNestingConst
+	LDR		R1, [R2]
+	PUSH	{R1}
+
+	/* Does the task have a floating point context that needs saving?  If
+	ulPortTaskHasFPUContext is 0 then no. */
+	LDR		R2, ulPortTaskHasFPUContextConst
+	LDR		R3, [R2]
+	CMP		R3, #0
+
+	/* Save the floating point context, if any. */
+	FMRXNE  R1,  FPSCR
+	VPUSHNE {D0-D15}
+	VPUSHNE	{D16-D31}
+	PUSHNE	{R1}
+
+	/* Save ulPortTaskHasFPUContext itself. */
+	PUSH	{R3}
+
+	/* Save the stack pointer in the TCB. */
+	LDR		R0, pxCurrentTCBConst
+	LDR		R1, [R0]
+	STR		SP, [R1]
+
+	.endm
+
+; /**********************************************************************/
+
+.macro portRESTORE_CONTEXT
+
+	/* Set the SP to point to the stack of the task being restored. */
+	LDR		R0, pxCurrentTCBConst
+	LDR		R1, [R0]
+	LDR		SP, [R1]
+
+	/* Is there a floating point context to restore?  If the restored
+	ulPortTaskHasFPUContext is zero then no. */
+	LDR		R0, ulPortTaskHasFPUContextConst
+	POP		{R1}
+	STR		R1, [R0]
+	CMP		R1, #0
+
+	/* Restore the floating point context, if any. */
+	POPNE 	{R0}
+	VPOPNE	{D16-D31}
+	VPOPNE	{D0-D15}
+	VMSRNE  FPSCR, R0
+
+	/* Restore the critical section nesting depth. */
+	LDR		R0, ulCriticalNestingConst
+	POP		{R1}
+	STR		R1, [R0]
+
+	/* Ensure the priority mask is correct for the critical nesting depth. */
+	LDR		R2, ulICCPMRConst
+	LDR		R2, [R2]
+	CMP		R1, #0
+	MOVEQ	R4, #255
+	LDRNE	R4, ulMaxAPIPriorityMaskConst
+	LDRNE	R4, [R4]
+	STR		R4, [R2]
+
+	/* Restore all system mode registers other than the SP (which is already
+	being used). */
+	POP		{R0-R12, R14}
+
+	/* Return to the task code, loading CPSR on the way. */
+	RFEIA	sp!
+
+	.endm
+
+
+
+
+/******************************************************************************
+ * SVC handler is used to start the scheduler.
+ *****************************************************************************/
+.align 4
+.type FreeRTOS_SWI_Handler, %function
+FreeRTOS_SWI_Handler:
+	/* Save the context of the current task and select a new task to run. */
+	portSAVE_CONTEXT
+	LDR R0, vTaskSwitchContextConst
+	BLX	R0
+	portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * vPortRestoreTaskContext is used to start the scheduler.
+ *****************************************************************************/
+.type vPortRestoreTaskContext, %function
+vPortRestoreTaskContext:
+	/* Switch to system mode. */
+	CPS		#SYS_MODE
+	portRESTORE_CONTEXT
+
+.align 4
+.type FreeRTOS_IRQ_Handler, %function
+FreeRTOS_IRQ_Handler:
+	/* Return to the interrupted instruction. */
+	SUB		lr, lr, #4
+
+	/* Push the return address and SPSR. */
+	PUSH	{lr}
+	MRS		lr, SPSR
+	PUSH	{lr}
+
+	/* Change to supervisor mode to allow reentry. */
+	CPS		#SVC_MODE
+
+	/* Push used registers. */
+	PUSH	{r0-r4, r12}
+
+	/* Increment nesting count.  r3 holds the address of ulPortInterruptNesting
+	for future use.  r1 holds the original ulPortInterruptNesting value for
+	future use. */
+	LDR		r3, ulPortInterruptNestingConst
+	LDR		r1, [r3]
+	ADD		r4, r1, #1
+	STR		r4, [r3]
+
+	/* Read value from the interrupt acknowledge register, which is stored in r0
+	for future parameter and interrupt clearing use. */
+	LDR 	r2, ulICCIARConst
+	LDR		r2, [r2]
+	LDR		r0, [r2]
+
+	/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
+	future use.  _RB_ Does this ever actually need to be done provided the start
+	of the stack is 8-byte aligned? */
+	MOV		r2, sp
+	AND		r2, r2, #4
+	SUB		sp, sp, r2
+
+	/* Call the interrupt handler.  r4 pushed to maintain alignment. */
+	PUSH	{r0-r4, lr}
+	LDR		r1, vApplicationIRQHandlerConst
+	BLX		r1
+	POP		{r0-r4, lr}
+	ADD		sp, sp, r2
+
+	CPSID	i
+	DSB
+	ISB
+
+	/* Write the value read from ICCIAR to ICCEOIR. */
+	LDR 	r4, ulICCEOIRConst
+	LDR		r4, [r4]
+	STR		r0, [r4]
+
+	/* Restore the old nesting count. */
+	STR		r1, [r3]
+
+	/* A context switch is never performed if the nesting count is not 0. */
+	CMP		r1, #0
+	BNE		exit_without_switch
+
+	/* Did the interrupt request a context switch?  r1 holds the address of
+	ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+	use. */
+	LDR		r1, =ulPortYieldRequired
+	LDR		r0, [r1]
+	CMP		r0, #0
+	BNE		switch_before_exit
+
+exit_without_switch:
+	/* No context switch.  Restore used registers, LR_irq and SPSR before
+	returning. */
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	MOVS	PC, LR
+
+switch_before_exit:
+	/* A context swtich is to be performed.  Clear the context switch pending
+	flag. */
+	MOV		r0, #0
+	STR		r0, [r1]
+
+	/* Restore used registers, LR-irq and SPSR before saving the context
+	to the task stack. */
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	portSAVE_CONTEXT
+
+	/* Call the function that selects the new task to execute.
+	vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+	instructions, or 8 byte aligned stack allocated data.  LR does not need
+	saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
+	LDR		R0, vTaskSwitchContextConst
+	BLX		R0
+
+	/* Restore the context of, and branch to, the task selected to execute
+	next. */
+	portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * If the application provides an implementation of vApplicationIRQHandler(),
+ * then it will get called directly without saving the FPU registers on
+ * interrupt entry, and this weak implementation of
+ * vApplicationIRQHandler() will not get called.
+ *
+ * If the application provides its own implementation of
+ * vApplicationFPUSafeIRQHandler() then this implementation of
+ * vApplicationIRQHandler() will be called, save the FPU registers, and then
+ * call vApplicationFPUSafeIRQHandler().
+ *
+ * Therefore, if the application writer wants FPU registers to be saved on
+ * interrupt entry their IRQ handler must be called
+ * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
+ * FPU registers to be saved on interrupt entry their IRQ handler must be
+ * called vApplicationIRQHandler().
+ *****************************************************************************/
+
+.align 4
+.weak vApplicationIRQHandler
+.type vApplicationIRQHandler, %function
+vApplicationIRQHandler:
+	PUSH	{LR}
+	FMRX	R1,  FPSCR
+	VPUSH	{D0-D15}
+	VPUSH	{D16-D31}
+	PUSH	{R1}
+
+	LDR		r1, vApplicationFPUSafeIRQHandlerConst
+	BLX		r1
+
+	POP		{R0}
+	VPOP	{D16-D31}
+	VPOP	{D0-D15}
+	VMSR	FPSCR, R0
+
+	POP {PC}
+
+
+ulICCIARConst:	.word ulICCIAR
+ulICCEOIRConst:	.word ulICCEOIR
+ulICCPMRConst: .word ulICCPMR
+pxCurrentTCBConst: .word pxCurrentTCB
+ulCriticalNestingConst: .word ulCriticalNesting
+ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
+ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask
+vTaskSwitchContextConst: .word vTaskSwitchContext
+vApplicationIRQHandlerConst: .word vApplicationIRQHandler
+ulPortInterruptNestingConst: .word ulPortInterruptNesting
+vApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler
+
+.end
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h
new file mode 100644
index 0000000..3da0b91
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h
@@ -0,0 +1,208 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+	extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{												\
+extern uint32_t ulPortYieldRequired;			\
+												\
+	if( xSwitchRequired != pdFALSE )			\
+	{											\
+		ulPortYieldRequired = pdTRUE;			\
+	}											\
+}
+
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );
+
+
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
+
+/* These macros do not globally disable/enable interrupts.  They do mask off
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+#define portDISABLE_INTERRUPTS()	ulPortSetInterruptMask()
+#define portENABLE_INTERRUPTS()		vPortClearInterruptMask( 0 )
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask(x)
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
+
+/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are
+created without an FPU context and must call vPortTaskUsesFPU() to give
+themselves an FPU context before using any FPU instructions.  If
+configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
+by default. */
+#if( configUSE_TASK_FPU_SUPPORT != 2 )
+	void vPortTaskUsesFPU( void );
+#else
+	/* Each task has an FPU context already, so define this function away to
+	nothing to prevent it being called accidentally. */
+	#define vPortTaskUsesFPU()
+#endif
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif /* configASSERT */
+
+#define portNOP() __asm volatile( "NOP" )
+#define portINLINE __inline
+
+#ifdef __cplusplus
+	} /* extern C */
+#endif
+
+
+/* The number of bits to shift for an interrupt priority is dependent on the
+number of bits implemented by the interrupt controller. */
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16
+	#define portPRIORITY_SHIFT 4
+	#define portMAX_BINARY_POINT_VALUE	3
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
+	#define portPRIORITY_SHIFT 3
+	#define portMAX_BINARY_POINT_VALUE	2
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
+	#define portPRIORITY_SHIFT 2
+	#define portMAX_BINARY_POINT_VALUE	1
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
+	#define portPRIORITY_SHIFT 1
+	#define portMAX_BINARY_POINT_VALUE	0
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
+	#define portPRIORITY_SHIFT 0
+	#define portMAX_BINARY_POINT_VALUE	0
+#else
+	#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+#endif
+
+/* Interrupt controller access addresses. */
+#define portICCPMR_PRIORITY_MASK_OFFSET  						( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET 				( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET 					( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET							( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET						( 0x14 )
+
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS 		( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER 					( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS 	( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS 		( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS 			( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER 					( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER 				( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
new file mode 100644
index 0000000..bad10db
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
@@ -0,0 +1,566 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM0 port.
+*----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_INT_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portNVIC_PENDSVSET_BIT                ( 1UL << 28UL )
+#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
+#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                      ( 0x01000000 )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#ifndef portMISSED_COUNTS_FACTOR
+    #define portMISSED_COUNTS_FACTOR    ( 45UL )
+#endif
+
+/* Let the user override the pre-loading of the initial LR with the address of
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__( ( naked ) );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void vPortStartFirstTask( void ) __attribute__( ( naked ) );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+    *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+    pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+    pxTopOfStack -= 8;                                       /* R11..R4. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    volatile uint32_t ulDummy = 0UL;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( uxCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being defined
+         * but never called.  ulDummy is used purely to quieten other warnings
+         * about code appearing after this function is called - making ulDummy
+         * volatile makes the compiler think the function could return and
+         * therefore not output an 'unreachable code' warning for code that appears
+         * after it. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+    /* This function is no longer used, but retained for backward
+     * compatibility. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortStartFirstTask( void )
+{
+    /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
+     * table offset register that can be used to locate the initial stack value.
+     * Not all M0 parts have the application vector table at address 0. */
+    __asm volatile (
+        "	.syntax unified				\n"
+        "	ldr  r2, pxCurrentTCBConst2	\n"/* Obtain location of pxCurrentTCB. */
+        "	ldr  r3, [r2]				\n"
+        "	ldr  r0, [r3]				\n"/* The first item in pxCurrentTCB is the task top of stack. */
+        "	adds r0, #32					\n"/* Discard everything up to r0. */
+        "	msr  psp, r0					\n"/* This is now the new top of stack to use in the task. */
+        "	movs r0, #2					\n"/* Switch to the psp stack. */
+        "	msr  CONTROL, r0				\n"
+        "	isb							\n"
+        "	pop  {r0-r5}					\n"/* Pop the registers that are saved automatically. */
+        "	mov  lr, r5					\n"/* lr is now in r5. */
+        "	pop  {r3}					\n"/* Return address is now in r3. */
+        "	pop  {r2}					\n"/* Pop and discard XPSR. */
+        "	cpsie i						\n"/* The first task has its context and interrupts can be enabled. */
+        "	bx   r3						\n"/* Finally, jump to the user defined task code. */
+        "								\n"
+        "	.align 4					\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB	  "
+        );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Start the first task. */
+    vPortStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing!  Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS.  Call
+     * vTaskSwitchContext() so link time optimisation does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortYield( void )
+{
+    /* Set a PendSV to request a context switch. */
+    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+    /* Barriers are normally not required but do ensure the code is completely
+     * within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMaskFromISR( void )
+{
+    __asm volatile (
+        " mrs r0, PRIMASK	\n"
+        " cpsid i			\n"
+        " bx lr				  "
+        ::: "memory"
+        );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask )
+{
+    __asm volatile (
+        " msr PRIMASK, r0	\n"
+        " bx lr				  "
+        ::: "memory"
+        );
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+    /* This is a naked function. */
+
+    __asm volatile
+    (
+        "	.syntax unified						\n"
+        "	mrs r0, psp							\n"
+        "										\n"
+        "	ldr	r3, pxCurrentTCBConst			\n"/* Get the location of the current TCB. */
+        "	ldr	r2, [r3]						\n"
+        "										\n"
+        "	subs r0, r0, #32					\n"/* Make space for the remaining low registers. */
+        "	str r0, [r2]						\n"/* Save the new top of stack. */
+        "	stmia r0!, {r4-r7}					\n"/* Store the low registers that are not saved automatically. */
+        " 	mov r4, r8							\n"/* Store the high registers. */
+        " 	mov r5, r9							\n"
+        " 	mov r6, r10							\n"
+        " 	mov r7, r11							\n"
+        " 	stmia r0!, {r4-r7}					\n"
+        "										\n"
+        "	push {r3, r14}						\n"
+        "	cpsid i								\n"
+        "	bl vTaskSwitchContext				\n"
+        "	cpsie i								\n"
+        "	pop {r2, r3}						\n"/* lr goes in r3. r2 now holds tcb pointer. */
+        "										\n"
+        "	ldr r1, [r2]						\n"
+        "	ldr r0, [r1]						\n"/* The first item in pxCurrentTCB is the task top of stack. */
+        "	adds r0, r0, #16					\n"/* Move to the high registers. */
+        "	ldmia r0!, {r4-r7}					\n"/* Pop the high registers. */
+        " 	mov r8, r4							\n"
+        " 	mov r9, r5							\n"
+        " 	mov r10, r6							\n"
+        " 	mov r11, r7							\n"
+        "										\n"
+        "	msr psp, r0							\n"/* Remember the new top of stack for the task. */
+        "										\n"
+        "	subs r0, r0, #32					\n"/* Go back for the low registers that are not automatically restored. */
+        " 	ldmia r0!, {r4-r7}					\n"/* Pop low registers.  */
+        "										\n"
+        "	bx r3								\n"
+        "										\n"
+        "	.align 4							\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB	  "
+    );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR;
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and reset the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+         * is accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods.  -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm volatile ( "cpsid i" ::: "memory" );
+        __asm volatile ( "dsb" );
+        __asm volatile ( "isb" );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above the cpsid instruction()
+             * above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again.  However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm volatile ( "dsb" ::: "memory" );
+                __asm volatile ( "wfi" );
+                __asm volatile ( "isb" );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately.  see comments above
+             * __disable_interrupt() call above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __asm volatile ( "cpsid i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is yet
+             * to count to zero (in which case an interrupt other than the SysTick
+             * must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrpts enabled. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+    }
+
+#endif /* configUSE_TICKLESS_IDLE */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
new file mode 100644
index 0000000..29806b6
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
@@ -0,0 +1,124 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
+    #define portDONT_DISCARD      __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+    extern void vPortYield( void );
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portYIELD()                                 vPortYield()
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+    extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__( ( naked ) );
+    extern void vClearInterruptMaskFromISR( uint32_t ulMask )  __attribute__( ( naked ) );
+
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMaskFromISR()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMaskFromISR( x )
+    #define portDISABLE_INTERRUPTS()                  __asm volatile ( " cpsid i " ::: "memory" )
+    #define portENABLE_INTERRUPTS()                   __asm volatile ( " cpsie i " ::: "memory" )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+    #define portNOP()
+
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/port.c
new file mode 100644
index 0000000..852a11c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/port.c
@@ -0,0 +1,1192 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if ( configENABLE_TRUSTZONE == 1 )
+    /* Secure components includes. */
+    #include "secure_context.h"
+    #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
+#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ            configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT          ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the
+ * same a the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE    ( 3UL )
+#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS      ( 20UL )
+#define portCPACR_CP11_POS      ( 22UL )
+
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS     ( 31UL )
+#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS     ( 30UL )
+#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS                ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS                ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS                ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS                ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS                ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS                ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS                ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS                ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE           ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The maximum 24-bit number.
+ *
+ * It is needed because the systick is a 24-bit counter.
+ */
+#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )
+
+/**
+ * @brief A fiddle factor to estimate the number of SysTick counts that would
+ * have occurred while the SysTick counter is stopped during tickless idle
+ * calculations.
+ */
+#define portMISSED_COUNTS_FACTOR    ( 45UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR    ( 0x01000000 )
+
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         FD
+ * 1111 1111  1111 1111  1111 1111  1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
+#else
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         BC
+ * 1111 1111  1111 1111  1111 1111  1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS    1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT    0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+
+/**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ *
+ * The implementation in this file is weak to allow application writers to
+ * change the timer used to generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether the current execution context is interrupt.
+ *
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE
+ * otherwise.
+ */
+BaseType_t xPortIsInsideInterrupt( void );
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+/**
+ * @brief The number of SysTick increments that make up one tick period.
+ */
+    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
+
+/**
+ * @brief The maximum number of tick periods that can be suppressed is
+ * limited by the 24 bit resolution of the SysTick timer.
+ */
+    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
+
+/**
+ * @brief Compensate for the CPU cycles that pass while the SysTick is
+ * stopped (low power functionality only).
+ */
+    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily. The time the SysTick is stopped for is
+         * accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods. -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm volatile ( "cpsid i" ::: "memory" );
+        __asm volatile ( "dsb" );
+        __asm volatile ( "isb" );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be un-suspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above the cpsid instruction()
+             * above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation
+             * contains its own wait for interrupt or wait for event
+             * instruction, and so wfi should not be executed again. However,
+             * the original expected idle time variable must remain unmodified,
+             * so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm volatile ( "dsb" ::: "memory" );
+                __asm volatile ( "wfi" );
+                __asm volatile ( "isb" );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately. See comments above
+             * the cpsid instruction above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will
+             * increase any slippage between the time maintained by the RTOS and
+             * calendar time. */
+            __asm volatile ( "cpsid i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
+             * Again, the time the SysTick is stopped for is accounted for as
+             * best it can be, but using the tickless mode will inevitably
+             * result in some tiny drift of the time maintained by the kernel
+             * with respect to calendar time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is
+             * yet to count to zero (in which case an interrupt other than the
+             * SysTick must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is
+                 * stepped forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+    }
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and reset the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    volatile uint32_t ulDummy = 0UL;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to. If a task wants to exit it
+     * should instead call vTaskDelete( NULL ). Artificially force an assert()
+     * to be triggered if configASSERT() is defined, then stop here so
+     * application writers can catch the error. */
+    configASSERT( ulCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being
+         * defined but never called.  ulDummy is used purely to quieten other
+         * warnings about code appearing after this function is called - making
+         * ulDummy volatile makes the compiler think the function could return
+         * and therefore not output an 'unreachable code' warning for code that
+         * appears after it. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __unprivileged_flash_start__;
+            extern uint32_t * __unprivileged_flash_end__;
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else /* if defined( __ARMCC_VERSION ) */
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __unprivileged_flash_start__[];
+            extern uint32_t __unprivileged_flash_end__[];
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Check that the MPU is present. */
+        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+        {
+            /* MAIR0 - Index 0. */
+            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+            /* MAIR0 - Index 1. */
+            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+            /* Setup privileged flash as Read Only so that privileged tasks can
+             * read it but not modify. */
+            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged flash as Read Only by both privileged and
+             * unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged syscalls flash as Read Only by both privileged
+             * and unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup RAM containing kernel data for privileged access only. */
+            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                               ( portMPU_REGION_EXECUTE_NEVER );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Enable mem fault. */
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
+
+            /* Enable MPU with privileged background access i.e. unmapped
+             * regions have privileged access. */
+            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_FPU == 1 )
+    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                /* Enable non-secure access to the FPU. */
+                SecureInit_EnableNSFPUAccess();
+            }
+        #endif /* configENABLE_TRUSTZONE */
+
+        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+         * unprivileged code should be able to access FPU. CP11 should be
+         * programmed to the same value as CP10. */
+        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+                            );
+
+        /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+         * context on exception entry and restore on exception return.
+         * LSPEN = 1 ==> Enable lazy context save of FP state. */
+        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+    }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Set a PendSV to request a context switch. */
+    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    portDISABLE_INTERRUPTS();
+    ulCriticalNesting++;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    configASSERT( ulCriticalNesting );
+    ulCriticalNesting--;
+
+    if( ulCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+    uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+    #if ( configENABLE_MPU == 1 )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+    #endif /* configENABLE_MPU */
+
+    uint32_t ulPC;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        uint32_t ulR0;
+        #if ( configENABLE_MPU == 1 )
+            uint32_t ulControl, ulIsTaskPrivileged;
+        #endif /* configENABLE_MPU */
+    #endif /* configENABLE_TRUSTZONE */
+    uint8_t ucSVCNumber;
+
+    /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+     * R12, LR, PC, xPSR. */
+    ulPC = pulCallerStackAddress[ 6 ];
+    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            case portSVC_ALLOCATE_SECURE_CONTEXT:
+
+                /* R0 contains the stack size passed as parameter to the
+                 * vPortAllocateSecureContext function. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                #if ( configENABLE_MPU == 1 )
+                    {
+                        /* Read the CONTROL register value. */
+                        __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+                        /* The task that raised the SVC is privileged if Bit[0]
+                         * in the CONTROL register is 0. */
+                        ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+                    }
+                #else /* if ( configENABLE_MPU == 1 ) */
+                    {
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0 );
+                    }
+                #endif /* configENABLE_MPU */
+
+                configASSERT( xSecureContext != NULL );
+                SecureContext_LoadContext( xSecureContext );
+                break;
+
+            case portSVC_FREE_SECURE_CONTEXT:
+                /* R0 contains the secure context handle to be freed. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                /* Free the secure context. */
+                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+                break;
+        #endif /* configENABLE_TRUSTZONE */
+
+        case portSVC_START_SCHEDULER:
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    /* De-prioritize the non-secure exceptions so that the
+                     * non-secure pendSV runs at the lowest priority. */
+                    SecureInit_DePrioritizeNSExceptions();
+
+                    /* Initialize the secure context management system. */
+                    SecureContext_Init();
+                }
+            #endif /* configENABLE_TRUSTZONE */
+
+            #if ( configENABLE_FPU == 1 )
+                {
+                    /* Setup the Floating Point Unit (FPU). */
+                    prvSetupFPU();
+                }
+            #endif /* configENABLE_FPU */
+
+            /* Setup the context of the first task so that the first task starts
+             * executing. */
+            vRestoreContextOfFirstTask();
+            break;
+
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_RAISE_PRIVILEGE:
+
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* configENABLE_MPU */
+
+        default:
+            /* Incorrect SVC call. */
+            configASSERT( pdFALSE );
+    }
+}
+/*-----------------------------------------------------------*/
+/* *INDENT-OFF* */
+#if ( configENABLE_MPU == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+/* *INDENT-ON* */
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    #if ( portPRELOAD_REGISTERS == 0 )
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #else /* portPRELOAD_REGISTERS */
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #endif /* portPRELOAD_REGISTERS */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    #if ( configENABLE_MPU == 1 )
+        {
+            /* Setup the Memory Protection Unit (MPU). */
+            prvSetupMPU();
+        }
+    #endif /* configENABLE_MPU */
+
+    /* Start the timer that generates the tick ISR. Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialize the critical nesting count ready for the first task. */
+    ulCriticalNesting = 0;
+
+    /* Start the first task. */
+    vStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing. Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. Call
+     * vTaskSwitchContext() so link time optimization does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here. */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    uint32_t ulStackDepth )
+    {
+        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+        int32_t lIndex = 0;
+
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Setup MAIR0. */
+        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid.  At all other
+         * times the stack parameters will not be valid and it is assumed that
+         * the stack region has already been configured. */
+        if( ulStackDepth > 0 )
+        {
+            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+
+            /* If the stack is within the privileged SRAM, do not protect it
+             * using a separate MPU region. This is needed because privileged
+             * SRAM is already protected using an MPU region and ARMv8-M does
+             * not allow overlapping MPU regions. */
+            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
+            {
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
+            }
+            else
+            {
+                /* Define the region that allows access to the stack. */
+                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+                                                             ( portMPU_REGION_NON_SHAREABLE ) |
+                                                             ( portMPU_REGION_READ_WRITE ) |
+                                                             ( portMPU_REGION_EXECUTE_NEVER );
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                                             ( portMPU_RLAR_REGION_ENABLE );
+            }
+        }
+
+        /* User supplied configurable regions. */
+        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+        {
+            /* If xRegions is NULL i.e. the task has not specified any MPU
+             * region, the else part ensures that all the configurable MPU
+             * regions are invalidated. */
+            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+            {
+                /* Translate the generic region definition contained in xRegions
+                 * into the ARMv8 specific MPU settings that are then stored in
+                 * xMPUSettings. */
+                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                /* Start address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+                                                                          ( portMPU_REGION_NON_SHAREABLE );
+
+                /* RO/RW. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+                }
+                else
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+                }
+
+                /* XN. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+                }
+
+                /* End Address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+                                                                          ( portMPU_RLAR_REGION_ENABLE );
+
+                /* Normal memory/ Device memory. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+                {
+                    /* Attr1 in MAIR0 is configured as device memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+                }
+                else
+                {
+                    /* Attr1 in MAIR0 is configured as normal memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+                }
+            }
+            else
+            {
+                /* Invalidate the region. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+            }
+
+            lIndex++;
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. Interrupt Program
+     * Status Register (IPSR) holds the exception number of the currently-executing
+     * exception or zero for Thread mode.*/
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.c
new file mode 100644
index 0000000..5276d8f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.c
@@ -0,0 +1,453 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configENABLE_FPU == 1 )
+    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr  r2, pxCurrentTCBConst2						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr  r3, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr  r0, [r3]									\n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r5, #1										\n"/* r5 = 1. */
+            "	bics r4, r5										\n"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+            "	ldr  r4, [r3]									\n"/* r4 = *r3 i.e. r4 = MAIR0. */
+            "	ldr  r2, xMAIR0Const2							\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str  r4, [r2]									\n"/* Program MAIR0. */
+            "	ldr  r2, xRNRConst2								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+            "	movs r5, #4										\n"/* r5 = 4. */
+            "	str  r5, [r2]									\n"/* Program RNR = 4. */
+            "	ldmia r3!, {r6,r7}								\n"/* Read first set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst2							\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}								\n"/* Write first set of RBAR/RLAR registers. */
+            "	movs r5, #5										\n"/* r5 = 5. */
+            "	str  r5, [r2]									\n"/* Program RNR = 5. */
+            "	ldmia r3!, {r6,r7}								\n"/* Read second set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst2							\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}								\n"/* Write second set of RBAR/RLAR registers. */
+            "	movs r5, #6										\n"/* r5 = 6. */
+            "	str  r5, [r2]									\n"/* Program RNR = 6. */
+            "	ldmia r3!, {r6,r7}								\n"/* Read third set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst2							\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}								\n"/* Write third set of RBAR/RLAR registers. */
+            "	movs r5, #7										\n"/* r5 = 7. */
+            "	str  r5, [r2]									\n"/* Program RNR = 7. */
+            "	ldmia r3!, {r6,r7}								\n"/* Read fourth set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst2							\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}								\n"/* Write fourth set of RBAR/RLAR registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r5, #1										\n"/* r5 = 1. */
+            "	orrs r4, r5										\n"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldm  r0!, {r1-r4}								\n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+            "	ldr  r5, xSecureContextConst2					\n"
+            "	str  r1, [r5]									\n"/* Set xSecureContext to this task's value for the same. */
+            "	msr  psplim, r2									\n"/* Set this task's PSPLIM value. */
+            "	msr  control, r3								\n"/* Set this task's CONTROL value. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	bx   r4											\n"/* Finally, branch to EXC_RETURN. */
+        #else /* configENABLE_MPU */
+            "	ldm  r0!, {r1-r3}								\n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+            "	ldr  r4, xSecureContextConst2					\n"
+            "	str  r1, [r4]									\n"/* Set xSecureContext to this task's value for the same. */
+            "	msr  psplim, r2									\n"/* Set this task's PSPLIM value. */
+            "	movs r1, #2										\n"/* r1 = 2. */
+            "	msr  CONTROL, r1								\n"/* Switch to use PSP in the thread mode. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	bx   r3											\n"/* Finally, branch to EXC_RETURN. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+        "xSecureContextConst2: .word xSecureContext			\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst2: .word 0xe000ed94					\n"
+            "xMAIR0Const2: .word 0xe000edc0						\n"
+            "xRNRConst2: .word 0xe000ed98						\n"
+            "xRBARConst2: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	tst r0, r1										\n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+        "	beq running_privileged							\n"/* If the result of previous AND operation was 0, branch. */
+        "	movs r0, #0										\n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "	bx lr											\n"/* Return. */
+        " running_privileged:								\n"
+        "	movs r0, #1										\n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "	bx lr											\n"/* Return. */
+        "													\n"
+        "	.align 4										\n"
+        ::: "r0", "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* Read the CONTROL register. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	bics r0, r1										\n"/* Clear the bit 0. */
+        "	msr control, r0									\n"/* Write back the new CONTROL value. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	orrs r0, r1										\n"/* r0 = r0 | r1. */
+        "	msr control, r0									\n"/* CONTROL = r0. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	ldr r0, xVTORConst								\n"/* Use the NVIC offset register to locate the stack. */
+        "	ldr r0, [r0]									\n"/* Read the VTOR register which gives the address of vector table. */
+        "	ldr r0, [r0]									\n"/* The first entry in vector table is stack pointer. */
+        "	msr msp, r0										\n"/* Set the MSP back to the start of the stack. */
+        "	cpsie i											\n"/* Globally enable interrupts. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	svc %0											\n"/* System call to start the first task. */
+        "	nop												\n"
+        "													\n"
+        "   .align 4										\n"
+        "xVTORConst: .word 0xe000ed08						\n"
+        ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	mrs r0, PRIMASK									\n"
+        "	cpsid i											\n"
+        "	bx lr											\n"
+        ::: "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	msr PRIMASK, r0									\n"
+        "	bx lr											\n"
+        ::: "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "	.extern SecureContext_SaveContext				\n"
+        "	.extern SecureContext_LoadContext				\n"
+        "													\n"
+        "	mrs r1, psp										\n"/* Read PSP in r1. */
+        "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+        "	ldr r0, [r2]									\n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+        "													\n"
+        "	cbz r0, save_ns_context							\n"/* No secure context to save. */
+        "	push {r0-r2, r14}								\n"
+        "	bl SecureContext_SaveContext					\n"
+        "	pop {r0-r3}										\n"/* LR is now in r3. */
+        "	mov lr, r3										\n"/* LR = r3. */
+        "	lsls r2, r3, #25								\n"/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        "	bpl save_ns_context								\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r2, [r3]									\n"/* Read pxCurrentTCB. */
+        #if ( configENABLE_MPU == 1 )
+            "	subs r1, r1, #16								\n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mrs r3, control									\n"/* r3 = CONTROL. */
+            "	mov r4, lr										\n"/* r4 = LR/EXC_RETURN. */
+            "	stmia r1!, {r0, r2-r4}							\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+        #else /* configENABLE_MPU */
+            "	subs r1, r1, #12								\n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmia r1!, {r0, r2-r3}							\n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+        #endif /* configENABLE_MPU */
+        "	b select_next_task								\n"
+        "													\n"
+        " save_ns_context:									\n"
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r2, [r3]									\n"/* Read pxCurrentTCB. */
+        #if ( configENABLE_MPU == 1 )
+            "	subs r1, r1, #48								\n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	adds r1, r1, #16								\n"/* r1 = r1 + 16. */
+            "	stmia r1!, {r4-r7}								\n"/* Store the low registers that are not saved automatically. */
+            "	mov r4, r8										\n"/* r4 = r8. */
+            "	mov r5, r9										\n"/* r5 = r9. */
+            "	mov r6, r10										\n"/* r6 = r10. */
+            "	mov r7, r11										\n"/* r7 = r11. */
+            "	stmia r1!, {r4-r7}								\n"/* Store the high registers that are not saved automatically. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mrs r3, control									\n"/* r3 = CONTROL. */
+            "	mov r4, lr										\n"/* r4 = LR/EXC_RETURN. */
+            "	subs r1, r1, #48								\n"/* r1 = r1 - 48. */
+            "	stmia r1!, {r0, r2-r4}							\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+        #else /* configENABLE_MPU */
+            "	subs r1, r1, #44								\n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmia r1!, {r0, r2-r7}							\n"/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+            "	mov r4, r8										\n"/* r4 = r8. */
+            "	mov r5, r9										\n"/* r5 = r9. */
+            "	mov r6, r10										\n"/* r6 = r10. */
+            "	mov r7, r11										\n"/* r7 = r11. */
+            "	stmia r1!, {r4-r7}								\n"/* Store the high registers that are not saved automatically. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        " select_next_task:									\n"
+        "	cpsid i											\n"
+        "	bl vTaskSwitchContext							\n"
+        "	cpsie i											\n"
+        "													\n"
+        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r3, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr r1, [r3]									\n"/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r5, #1										\n"/* r5 = 1. */
+            "	bics r4, r5										\n"/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+            "	ldr r4, [r3]									\n"/* r4 = *r3 i.e. r4 = MAIR0. */
+            "	ldr r2, xMAIR0Const								\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str r4, [r2]									\n"/* Program MAIR0. */
+            "	ldr r2, xRNRConst								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+            "	movs r5, #4										\n"/* r5 = 4. */
+            "	str  r5, [r2]									\n"/* Program RNR = 4. */
+            "	ldmia r3!, {r6,r7}								\n"/* Read first set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst								\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}								\n"/* Write first set of RBAR/RLAR registers. */
+            "	movs r5, #5										\n"/* r5 = 5. */
+            "	str  r5, [r2]									\n"/* Program RNR = 5. */
+            "	ldmia r3!, {r6,r7}								\n"/* Read second set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst								\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}								\n"/* Write second set of RBAR/RLAR registers. */
+            "	movs r5, #6										\n"/* r5 = 6. */
+            "	str  r5, [r2]									\n"/* Program RNR = 6. */
+            "	ldmia r3!, {r6,r7}								\n"/* Read third set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst								\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}								\n"/* Write third set of RBAR/RLAR registers. */
+            "	movs r5, #7										\n"/* r5 = 7. */
+            "	str  r5, [r2]									\n"/* Program RNR = 7. */
+            "	ldmia r3!, {r6,r7}								\n"/* Read fourth set of RBAR/RLAR from TCB. */
+            "	ldr  r4, xRBARConst								\n"/* r4 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r4!, {r6,r7}								\n"/* Write fourth set of RBAR/RLAR registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r5, #1										\n"/* r5 = 1. */
+            "	orrs r4, r5										\n"/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldmia r1!, {r0, r2-r4}							\n"/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+            "	msr control, r3									\n"/* Restore the CONTROL register value for the task. */
+            "	mov lr, r4										\n"/* LR = r4. */
+            "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "	str r0, [r2]									\n"/* Restore the task's xSecureContext. */
+            "	cbz r0, restore_ns_context						\n"/* If there is no secure context for the task, restore the non-secure context. */
+            "	push {r1,r4}									\n"
+            "	bl SecureContext_LoadContext					\n"/* Restore the secure context. */
+            "	pop {r1,r4}										\n"
+            "	mov lr, r4										\n"/* LR = r4. */
+            "	lsls r2, r4, #25								\n"/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "	bpl restore_ns_context							\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+            "	bx lr											\n"
+        #else /* configENABLE_MPU */
+            "	ldmia r1!, {r0, r2-r3}							\n"/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+            "	mov lr, r3										\n"/* LR = r3. */
+            "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "	str r0, [r2]									\n"/* Restore the task's xSecureContext. */
+            "	cbz r0, restore_ns_context						\n"/* If there is no secure context for the task, restore the non-secure context. */
+            "	push {r1,r3}									\n"
+            "	bl SecureContext_LoadContext					\n"/* Restore the secure context. */
+            "	pop {r1,r3}										\n"
+            "	mov lr, r3										\n"/* LR = r3. */
+            "	lsls r2, r3, #25								\n"/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "	bpl restore_ns_context							\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+            "	bx lr											\n"
+        #endif /* configENABLE_MPU */
+        "													\n"
+        " restore_ns_context:								\n"
+        "	adds r1, r1, #16								\n"/* Move to the high registers. */
+        "	ldmia r1!, {r4-r7}								\n"/* Restore the high registers that are not automatically restored. */
+        "	mov r8, r4										\n"/* r8 = r4. */
+        "	mov r9, r5										\n"/* r9 = r5. */
+        "	mov r10, r6										\n"/* r10 = r6. */
+        "	mov r11, r7										\n"/* r11 = r7. */
+        "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+        "	subs r1, r1, #32								\n"/* Go back to the low registers. */
+        "	ldmia r1!, {r4-r7}								\n"/* Restore the low registers that are not automatically restored. */
+        "	bx lr											\n"
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB				\n"
+        "xSecureContextConst: .word xSecureContext			\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst: .word 0xe000ed94					\n"
+            "xMAIR0Const: .word 0xe000edc0						\n"
+            "xRNRConst: .word 0xe000ed98						\n"
+            "xRBARConst: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	movs r0, #4										\n"
+        "	mov r1, lr										\n"
+        "	tst r0, r1										\n"
+        "	beq stacking_used_msp							\n"
+        "	mrs r0, psp										\n"
+        "	ldr r2, svchandler_address_const				\n"
+        "	bx r2											\n"
+        " stacking_used_msp:								\n"
+        "	mrs r0, msp										\n"
+        "	ldr r2, svchandler_address_const				\n"
+        "	bx r2											\n"
+        "													\n"
+        "	.align 4										\n"
+        "svchandler_address_const: .word vPortSVCHandler_C	\n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	svc %0											\n"/* Secure context is allocated in the supervisor call. */
+        "	bx lr											\n"/* Return. */
+        ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	ldr r1, [r0]									\n"/* The first item in the TCB is the top of the stack. */
+        "	ldr r0, [r1]									\n"/* The first item on the stack is the task's xSecureContext. */
+        "	cmp r0, #0										\n"/* Raise svc if task's xSecureContext is not NULL. */
+        "	beq free_secure_context							\n"
+        "	bx lr											\n"/* There is no secure context (xSecureContext is NULL). */
+        " free_secure_context:								\n"
+        "	svc %0											\n"/* Secure context is freed in the supervisor call. */
+        "	bx lr											\n"/* Return. */
+        ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.h
new file mode 100644
index 0000000..b01f171
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h
new file mode 100644
index 0000000..61cd152
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h
@@ -0,0 +1,312 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+    #ifndef configENABLE_FPU
+        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+    #endif /* configENABLE_FPU */
+
+    #ifndef configENABLE_MPU
+        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+    #endif /* configENABLE_MPU */
+
+    #ifndef configENABLE_TRUSTZONE
+        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+    #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+    #define portARCH_NAME                      "Cortex-M23"
+    #define portSTACK_GROWTH                   ( -1 )
+    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT                 8
+    #define portNOP()
+    #define portINLINE                         __inline
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+    #endif
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
+    #define portDONT_DISCARD                   __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+    extern BaseType_t xPortIsInsideInterrupt( void );
+
+    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+    #endif /* configENABLE_TRUSTZONE */
+
+    #if ( configENABLE_MPU == 1 )
+        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+    #if ( configENABLE_MPU == 1 )
+        #define portUSING_MPU_WRAPPERS    1
+        #define portPRIVILEGE_BIT         ( 0x80000000UL )
+    #else
+        #define portPRIVILEGE_BIT         ( 0x0UL )
+    #endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
+    #define portSTACK_REGION                              ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
+    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
+    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
+    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
+    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
+    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+    } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
+    #define portSVC_FREE_SECURE_CONTEXT        1
+    #define portSVC_START_SCHEDULER            2
+    #define portSVC_RAISE_PRIVILEGE            3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+    #define portYIELD()                                 vPortYield()
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+    #define portDISABLE_INTERRUPTS()                  __asm volatile ( " cpsid i " ::: "memory" )
+    #define portENABLE_INTERRUPTS()                   __asm volatile ( " cpsie i " ::: "memory" )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+    #else
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+        #define portCLEAN_UP_TCB( pxTCB )
+    #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+        #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+        #define portRESET_PRIVILEGE()    vResetPrivilege()
+    #else
+        #define portIS_PRIVILEGED()
+        #define portRAISE_PRIVILEGE()
+        #define portRESET_PRIVILEGE()
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.c
new file mode 100644
index 0000000..046bf4e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.c
@@ -0,0 +1,206 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED      0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED    0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
+    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */
+    uint8_t * pucStackStart;          /**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* No stack for thread mode until a task's context is loaded. */
+        secureportSET_PSPLIM( securecontextNO_STACK );
+        secureportSET_PSP( securecontextNO_STACK );
+
+        #if ( configENABLE_MPU == 1 )
+            {
+                /* Configure thread mode to use PSP and to be unprivileged. */
+                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+            }
+        #else /* configENABLE_MPU */
+            {
+                /* Configure thread mode to use PSP and to be privileged.. */
+                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+            }
+        #endif /* configENABLE_MPU */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+                                                                                       uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+    uint8_t * pucStackMemory = NULL;
+    uint32_t ulIPSR;
+    SecureContextHandle_t xSecureContextHandle = NULL;
+
+    #if ( configENABLE_MPU == 1 )
+        uint32_t * pulCurrentStackPointer = NULL;
+    #endif /* configENABLE_MPU */
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* Allocate the context structure. */
+        xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+        if( xSecureContextHandle != NULL )
+        {
+            /* Allocate the stack space. */
+            pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+            if( pucStackMemory != NULL )
+            {
+                /* Since stack grows down, the starting point will be the last
+                 * location. Note that this location is next to the last
+                 * allocated byte because the hardware decrements the stack
+                 * pointer before writing i.e. if stack pointer is 0x2, a push
+                 * operation will decrement the stack pointer to 0x1 and then
+                 * write at 0x1. */
+                xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+                /* The stack cannot go beyond this location. This value is
+                 * programmed in the PSPLIM register on context switch.*/
+                xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+                #if ( configENABLE_MPU == 1 )
+                    {
+                        /* Store the correct CONTROL value for the task on the stack.
+                         * This value is programmed in the CONTROL register on
+                         * context switch. */
+                        pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+                        pulCurrentStackPointer--;
+
+                        if( ulIsTaskPrivileged )
+                        {
+                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+                        }
+                        else
+                        {
+                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                        }
+
+                        /* Store the current stack pointer. This value is programmed in
+                         * the PSP register on context switch. */
+                        xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                    }
+                #else /* configENABLE_MPU */
+                    {
+                        /* Current SP is set to the starting of the stack. This
+                         * value programmed in the PSP register on context switch. */
+                        xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+                    }
+                #endif /* configENABLE_MPU */
+            }
+            else
+            {
+                /* Free the context to avoid memory leak and make sure to return
+                 * NULL to indicate failure. */
+                vPortFree( xSecureContextHandle );
+                xSecureContextHandle = NULL;
+            }
+        }
+    }
+
+    return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* Ensure that valid parameters are passed. */
+        secureportASSERT( xSecureContextHandle != NULL );
+
+        /* Free the stack space. */
+        vPortFree( xSecureContextHandle->pucStackLimit );
+
+        /* Free the context itself. */
+        vPortFree( xSecureContextHandle );
+    }
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.h
new file mode 100644
index 0000000..532a407
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.h
@@ -0,0 +1,112 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK    0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext * SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if ( configENABLE_MPU == 1 )
+    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+                                                         uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c
new file mode 100644
index 0000000..ade0abf
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c
@@ -0,0 +1,91 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+#if ( configENABLE_FPU == 1 )
+    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+    /* xSecureContextHandle value is in r0. */
+    __asm volatile
+    (
+        "	.syntax unified							\n"
+        "											\n"
+        "	mrs r1, ipsr							\n"/* r1 = IPSR. */
+        "	cbz r1, load_ctx_therad_mode			\n"/* Do nothing if the processor is running in the Thread Mode. */
+        "	ldmia r0!, {r1, r2}						\n"/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+        #if ( configENABLE_MPU == 1 )
+            "	ldmia r1!, {r3}							\n"/* Read CONTROL register value from task's stack. r3 = CONTROL. */
+            "	msr control, r3							\n"/* CONTROL = r3. */
+        #endif /* configENABLE_MPU */
+        "	msr psplim, r2							\n"/* PSPLIM = r2. */
+        "	msr psp, r1								\n"/* PSP = r1. */
+        "											\n"
+        " load_ctx_therad_mode:						\n"
+        "	nop										\n"
+        "											\n"
+        ::: "r0", "r1", "r2"
+    );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+    /* xSecureContextHandle value is in r0. */
+    __asm volatile
+    (
+        "	.syntax unified							\n"
+        "											\n"
+        "	mrs r1, ipsr							\n"/* r1 = IPSR. */
+        "	cbz r1, save_ctx_therad_mode			\n"/* Do nothing if the processor is running in the Thread Mode. */
+        "	mrs r1, psp								\n"/* r1 = PSP. */
+        #if ( configENABLE_MPU == 1 )
+            "	mrs r2, control							\n"/* r2 = CONTROL. */
+            "	subs r1, r1, #4							\n"/* Make space for the CONTROL value on the stack. */
+            "	str r1, [r0]							\n"/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+            "	stmia r1!, {r2}							\n"/* Store CONTROL value on the stack. */
+        #else /* configENABLE_MPU */
+            "	str r1, [r0]							\n"/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+        #endif /* configENABLE_MPU */
+        "	movs r1, %0								\n"/* r1 = securecontextNO_STACK. */
+        "	msr psplim, r1							\n"/* PSPLIM = securecontextNO_STACK. */
+        "	msr psp, r1								\n"/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+        "											\n"
+        " save_ctx_therad_mode:						\n"
+        "	nop										\n"
+        "											\n"
+        ::"i" ( securecontextNO_STACK ) : "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.c
new file mode 100644
index 0000000..82dbd9e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.c
@@ -0,0 +1,454 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+    #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+    #define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+    #define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
+
+/* The application writer has already defined the array used for the RTOS
+* heap - probably so it can be placed in a special segment or address. */
+    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
+    size_t xBlockSize;                     /**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, * pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+    BlockLink_t * pxFirstFreeBlock;
+    uint8_t * pucAlignedHeap;
+    size_t uxAddress;
+    size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+    /* Ensure the heap starts on a correctly aligned boundary. */
+    uxAddress = ( size_t ) ucHeap;
+
+    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+    {
+        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+    }
+
+    pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+    /* xStart is used to hold a pointer to the first item in the list of free
+     * blocks.  The void cast is used to prevent compiler warnings. */
+    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+    xStart.xBlockSize = ( size_t ) 0;
+
+    /* pxEnd is used to mark the end of the list of free blocks and is inserted
+     * at the end of the heap space. */
+    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+    uxAddress -= xHeapStructSize;
+    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+    pxEnd = ( void * ) uxAddress;
+    pxEnd->xBlockSize = 0;
+    pxEnd->pxNextFreeBlock = NULL;
+
+    /* To start with there is a single free block that is sized to take up the
+     * entire heap space, minus the space taken by pxEnd. */
+    pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+    /* Only one block exists - and it covers the entire usable heap space. */
+    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+    /* Work out the position of the top bit in a size_t variable. */
+    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
+{
+    BlockLink_t * pxIterator;
+    uint8_t * puc;
+
+    /* Iterate through the list until a block is found that has a higher address
+     * than the block being inserted. */
+    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+    {
+        /* Nothing to do here, just iterate to the right position. */
+    }
+
+    /* Do the block being inserted, and the block it is being inserted after
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxIterator;
+
+    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+    {
+        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+        pxBlockToInsert = pxIterator;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Do the block being inserted, and the block it is being inserted before
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxBlockToInsert;
+
+    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+    {
+        if( pxIterator->pxNextFreeBlock != pxEnd )
+        {
+            /* Form one big block from the two blocks. */
+            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+        }
+        else
+        {
+            pxBlockToInsert->pxNextFreeBlock = pxEnd;
+        }
+    }
+    else
+    {
+        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+    }
+
+    /* If the block being inserted plugged a gab, so was merged with the block
+     * before and the block after, then it's pxNextFreeBlock pointer will have
+     * already been set, and should not be set here as that would make it point
+     * to itself. */
+    if( pxIterator != pxBlockToInsert )
+    {
+        pxIterator->pxNextFreeBlock = pxBlockToInsert;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void * pvPortMalloc( size_t xWantedSize )
+{
+    BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
+    void * pvReturn = NULL;
+
+    /* If this is the first call to malloc then the heap will require
+     * initialisation to setup the list of free blocks. */
+    if( pxEnd == NULL )
+    {
+        prvHeapInit();
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    {
+        /* The wanted size is increased so it can contain a BlockLink_t
+         * structure in addition to the requested amount of bytes. */
+        if( xWantedSize > 0 )
+        {
+            xWantedSize += xHeapStructSize;
+
+            /* Ensure that blocks are always aligned to the required number of
+             * bytes. */
+            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+            {
+                /* Byte alignment required. */
+                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+        {
+            /* Traverse the list from the start (lowest address) block until
+             * one of adequate size is found. */
+            pxPreviousBlock = &xStart;
+            pxBlock = xStart.pxNextFreeBlock;
+
+            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+            {
+                pxPreviousBlock = pxBlock;
+                pxBlock = pxBlock->pxNextFreeBlock;
+            }
+
+            /* If the end marker was reached then a block of adequate size was
+             * not found. */
+            if( pxBlock != pxEnd )
+            {
+                /* Return the memory space pointed to - jumping over the
+                 * BlockLink_t structure at its start. */
+                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+                /* This block is being returned for use so must be taken out
+                 * of the list of free blocks. */
+                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+                /* If the block is larger than required it can be split into
+                 * two. */
+                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+                {
+                    /* This block is to be split into two.  Create a new
+                     * block following the number of bytes requested. The void
+                     * cast is used to prevent byte alignment warnings from the
+                     * compiler. */
+                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+                    /* Calculate the sizes of two blocks split from the single
+                     * block. */
+                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+                    pxBlock->xBlockSize = xWantedSize;
+
+                    /* Insert the new block into the list of free blocks. */
+                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+                {
+                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                /* The block is being returned - it is allocated and owned by
+                 * the application and has no "next" block. */
+                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                pxBlock->pxNextFreeBlock = NULL;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    traceMALLOC( pvReturn, xWantedSize );
+
+    #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+        {
+            if( pvReturn == NULL )
+            {
+                extern void vApplicationMallocFailedHook( void );
+                vApplicationMallocFailedHook();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
+
+    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+    return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void * pv )
+{
+    uint8_t * puc = ( uint8_t * ) pv;
+    BlockLink_t * pxLink;
+
+    if( pv != NULL )
+    {
+        /* The memory being freed will have an BlockLink_t structure immediately
+         * before it. */
+        puc -= xHeapStructSize;
+
+        /* This casting is to keep the compiler from issuing warnings. */
+        pxLink = ( void * ) puc;
+
+        /* Check the block is actually allocated. */
+        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        {
+            if( pxLink->pxNextFreeBlock == NULL )
+            {
+                /* The block is being returned to the heap - it is no longer
+                 * allocated. */
+                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+                secureportDISABLE_NON_SECURE_INTERRUPTS();
+                {
+                    /* Add this block to the list of free blocks. */
+                    xFreeBytesRemaining += pxLink->xBlockSize;
+                    traceFREE( pv, pxLink->xBlockSize );
+                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+                }
+                secureportENABLE_NON_SECURE_INTERRUPTS();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+    return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+    return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+    /* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.h
new file mode 100644
index 0000000..fa78046
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void * pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void * pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.c
new file mode 100644
index 0000000..4e6018d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS          ( 29UL )
+#define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS              ( 26UL )
+#define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS            ( 10UL )
+#define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS            ( 11UL )
+#define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+                                   ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+                                   ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
+    }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+         * permitted. CP11 should be programmed to the same value as CP10. */
+        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+         * that we can enable/disable lazy stacking in port.c file. */
+        *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
+
+        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+         * registers (S16-S31) are also pushed to stack on exception entry and
+         * restored on exception return. */
+        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+    }
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.h
new file mode 100644
index 0000000..39deb36
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h
new file mode 100644
index 0000000..7b8dbed
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT         8
+#define secureportBYTE_ALIGNMENT_MASK    ( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+    #define secureportNON_SECURE_CALLABLE    __cmse_nonsecure_entry __root
+#else
+    #define secureportNON_SECURE_CALLABLE    __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+    __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+    __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+    __asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+    __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+    __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+    __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+    __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+    __asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL     0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS()     secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x )                      \
+    if( ( x ) == 0 )                               \
+    {                                              \
+        secureportDISABLE_SECURE_INTERRUPTS();     \
+        secureportDISABLE_NON_SECURE_INTERRUPTS(); \
+        for( ; ; ) {; }                            \
+    }
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
new file mode 100644
index 0000000..b4639df
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
@@ -0,0 +1,1192 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if ( configENABLE_TRUSTZONE == 1 )
+    /* Secure components includes. */
+    #include "secure_context.h"
+    #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
+#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ            configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT          ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the
+ * same a the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE    ( 3UL )
+#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS      ( 20UL )
+#define portCPACR_CP11_POS      ( 22UL )
+
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS     ( 31UL )
+#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS     ( 30UL )
+#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS                ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS                ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS                ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS                ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS                ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS                ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS                ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS                ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE           ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The maximum 24-bit number.
+ *
+ * It is needed because the systick is a 24-bit counter.
+ */
+#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )
+
+/**
+ * @brief A fiddle factor to estimate the number of SysTick counts that would
+ * have occurred while the SysTick counter is stopped during tickless idle
+ * calculations.
+ */
+#define portMISSED_COUNTS_FACTOR    ( 45UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR    ( 0x01000000 )
+
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         FD
+ * 1111 1111  1111 1111  1111 1111  1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
+#else
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         BC
+ * 1111 1111  1111 1111  1111 1111  1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS    1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT    0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+
+/**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ *
+ * The implementation in this file is weak to allow application writers to
+ * change the timer used to generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether the current execution context is interrupt.
+ *
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE
+ * otherwise.
+ */
+BaseType_t xPortIsInsideInterrupt( void );
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+/**
+ * @brief The number of SysTick increments that make up one tick period.
+ */
+    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
+
+/**
+ * @brief The maximum number of tick periods that can be suppressed is
+ * limited by the 24 bit resolution of the SysTick timer.
+ */
+    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
+
+/**
+ * @brief Compensate for the CPU cycles that pass while the SysTick is
+ * stopped (low power functionality only).
+ */
+    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily. The time the SysTick is stopped for is
+         * accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods. -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm volatile ( "cpsid i" ::: "memory" );
+        __asm volatile ( "dsb" );
+        __asm volatile ( "isb" );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be un-suspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above the cpsid instruction()
+             * above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation
+             * contains its own wait for interrupt or wait for event
+             * instruction, and so wfi should not be executed again. However,
+             * the original expected idle time variable must remain unmodified,
+             * so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm volatile ( "dsb" ::: "memory" );
+                __asm volatile ( "wfi" );
+                __asm volatile ( "isb" );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately. See comments above
+             * the cpsid instruction above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will
+             * increase any slippage between the time maintained by the RTOS and
+             * calendar time. */
+            __asm volatile ( "cpsid i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
+             * Again, the time the SysTick is stopped for is accounted for as
+             * best it can be, but using the tickless mode will inevitably
+             * result in some tiny drift of the time maintained by the kernel
+             * with respect to calendar time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is
+             * yet to count to zero (in which case an interrupt other than the
+             * SysTick must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is
+                 * stepped forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+    }
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and reset the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    volatile uint32_t ulDummy = 0UL;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to. If a task wants to exit it
+     * should instead call vTaskDelete( NULL ). Artificially force an assert()
+     * to be triggered if configASSERT() is defined, then stop here so
+     * application writers can catch the error. */
+    configASSERT( ulCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being
+         * defined but never called.  ulDummy is used purely to quieten other
+         * warnings about code appearing after this function is called - making
+         * ulDummy volatile makes the compiler think the function could return
+         * and therefore not output an 'unreachable code' warning for code that
+         * appears after it. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __unprivileged_flash_start__;
+            extern uint32_t * __unprivileged_flash_end__;
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else /* if defined( __ARMCC_VERSION ) */
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __unprivileged_flash_start__[];
+            extern uint32_t __unprivileged_flash_end__[];
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Check that the MPU is present. */
+        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+        {
+            /* MAIR0 - Index 0. */
+            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+            /* MAIR0 - Index 1. */
+            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+            /* Setup privileged flash as Read Only so that privileged tasks can
+             * read it but not modify. */
+            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged flash as Read Only by both privileged and
+             * unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged syscalls flash as Read Only by both privileged
+             * and unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup RAM containing kernel data for privileged access only. */
+            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                               ( portMPU_REGION_EXECUTE_NEVER );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Enable mem fault. */
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
+
+            /* Enable MPU with privileged background access i.e. unmapped
+             * regions have privileged access. */
+            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_FPU == 1 )
+    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                /* Enable non-secure access to the FPU. */
+                SecureInit_EnableNSFPUAccess();
+            }
+        #endif /* configENABLE_TRUSTZONE */
+
+        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+         * unprivileged code should be able to access FPU. CP11 should be
+         * programmed to the same value as CP10. */
+        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+                            );
+
+        /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+         * context on exception entry and restore on exception return.
+         * LSPEN = 1 ==> Enable lazy context save of FP state. */
+        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+    }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Set a PendSV to request a context switch. */
+    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    portDISABLE_INTERRUPTS();
+    ulCriticalNesting++;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    configASSERT( ulCriticalNesting );
+    ulCriticalNesting--;
+
+    if( ulCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+    uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+    #if ( configENABLE_MPU == 1 )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+    #endif /* configENABLE_MPU */
+
+    uint32_t ulPC;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        uint32_t ulR0;
+        #if ( configENABLE_MPU == 1 )
+            uint32_t ulControl, ulIsTaskPrivileged;
+        #endif /* configENABLE_MPU */
+    #endif /* configENABLE_TRUSTZONE */
+    uint8_t ucSVCNumber;
+
+    /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+     * R12, LR, PC, xPSR. */
+    ulPC = pulCallerStackAddress[ 6 ];
+    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            case portSVC_ALLOCATE_SECURE_CONTEXT:
+
+                /* R0 contains the stack size passed as parameter to the
+                 * vPortAllocateSecureContext function. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                #if ( configENABLE_MPU == 1 )
+                    {
+                        /* Read the CONTROL register value. */
+                        __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+                        /* The task that raised the SVC is privileged if Bit[0]
+                         * in the CONTROL register is 0. */
+                        ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+                    }
+                #else /* if ( configENABLE_MPU == 1 ) */
+                    {
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0 );
+                    }
+                #endif /* configENABLE_MPU */
+
+                configASSERT( xSecureContext != NULL );
+                SecureContext_LoadContext( xSecureContext );
+                break;
+
+            case portSVC_FREE_SECURE_CONTEXT:
+                /* R0 contains the secure context handle to be freed. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                /* Free the secure context. */
+                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+                break;
+        #endif /* configENABLE_TRUSTZONE */
+
+        case portSVC_START_SCHEDULER:
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    /* De-prioritize the non-secure exceptions so that the
+                     * non-secure pendSV runs at the lowest priority. */
+                    SecureInit_DePrioritizeNSExceptions();
+
+                    /* Initialize the secure context management system. */
+                    SecureContext_Init();
+                }
+            #endif /* configENABLE_TRUSTZONE */
+
+            #if ( configENABLE_FPU == 1 )
+                {
+                    /* Setup the Floating Point Unit (FPU). */
+                    prvSetupFPU();
+                }
+            #endif /* configENABLE_FPU */
+
+            /* Setup the context of the first task so that the first task starts
+             * executing. */
+            vRestoreContextOfFirstTask();
+            break;
+
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_RAISE_PRIVILEGE:
+
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* configENABLE_MPU */
+
+        default:
+            /* Incorrect SVC call. */
+            configASSERT( pdFALSE );
+    }
+}
+/*-----------------------------------------------------------*/
+/* *INDENT-OFF* */
+#if ( configENABLE_MPU == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+/* *INDENT-ON* */
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    #if ( portPRELOAD_REGISTERS == 0 )
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #else /* portPRELOAD_REGISTERS */
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #endif /* portPRELOAD_REGISTERS */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    #if ( configENABLE_MPU == 1 )
+        {
+            /* Setup the Memory Protection Unit (MPU). */
+            prvSetupMPU();
+        }
+    #endif /* configENABLE_MPU */
+
+    /* Start the timer that generates the tick ISR. Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialize the critical nesting count ready for the first task. */
+    ulCriticalNesting = 0;
+
+    /* Start the first task. */
+    vStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing. Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. Call
+     * vTaskSwitchContext() so link time optimization does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here. */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    uint32_t ulStackDepth )
+    {
+        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+        int32_t lIndex = 0;
+
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Setup MAIR0. */
+        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid.  At all other
+         * times the stack parameters will not be valid and it is assumed that
+         * the stack region has already been configured. */
+        if( ulStackDepth > 0 )
+        {
+            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+
+            /* If the stack is within the privileged SRAM, do not protect it
+             * using a separate MPU region. This is needed because privileged
+             * SRAM is already protected using an MPU region and ARMv8-M does
+             * not allow overlapping MPU regions. */
+            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
+            {
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
+            }
+            else
+            {
+                /* Define the region that allows access to the stack. */
+                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+                                                             ( portMPU_REGION_NON_SHAREABLE ) |
+                                                             ( portMPU_REGION_READ_WRITE ) |
+                                                             ( portMPU_REGION_EXECUTE_NEVER );
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                                             ( portMPU_RLAR_REGION_ENABLE );
+            }
+        }
+
+        /* User supplied configurable regions. */
+        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+        {
+            /* If xRegions is NULL i.e. the task has not specified any MPU
+             * region, the else part ensures that all the configurable MPU
+             * regions are invalidated. */
+            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+            {
+                /* Translate the generic region definition contained in xRegions
+                 * into the ARMv8 specific MPU settings that are then stored in
+                 * xMPUSettings. */
+                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                /* Start address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+                                                                          ( portMPU_REGION_NON_SHAREABLE );
+
+                /* RO/RW. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+                }
+                else
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+                }
+
+                /* XN. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+                }
+
+                /* End Address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+                                                                          ( portMPU_RLAR_REGION_ENABLE );
+
+                /* Normal memory/ Device memory. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+                {
+                    /* Attr1 in MAIR0 is configured as device memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+                }
+                else
+                {
+                    /* Attr1 in MAIR0 is configured as normal memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+                }
+            }
+            else
+            {
+                /* Invalidate the region. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+            }
+
+            lIndex++;
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. Interrupt Program
+     * Status Register (IPSR) holds the exception number of the currently-executing
+     * exception or zero for Thread mode.*/
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
new file mode 100644
index 0000000..ef8f3e4
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
@@ -0,0 +1,366 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configENABLE_FPU == 1 )
+    #error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr  r2, pxCurrentTCBConst2						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr  r1, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr  r0, [r1]									\n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r3, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r4, #1										\n"/* r4 = 1. */
+            "	bics r3, r4										\n"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+            "	str r3, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+            "	ldr  r4, [r1]									\n"/* r4 = *r1 i.e. r4 = MAIR0. */
+            "	ldr  r2, xMAIR0Const2							\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str  r4, [r2]									\n"/* Program MAIR0. */
+            "	ldr  r2, xRNRConst2								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+            "	movs r4, #4										\n"/* r4 = 4. */
+            "	str  r4, [r2]									\n"/* Program RNR = 4. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read first set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst2							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write first set of RBAR/RLAR registers. */
+            "	movs r4, #5										\n"/* r4 = 5. */
+            "	str  r4, [r2]									\n"/* Program RNR = 5. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read second set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst2							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write second set of RBAR/RLAR registers. */
+            "	movs r4, #6										\n"/* r4 = 6. */
+            "	str  r4, [r2]									\n"/* Program RNR = 6. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read third set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst2							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write third set of RBAR/RLAR registers. */
+            "	movs r4, #7										\n"/* r4 = 7. */
+            "	str  r4, [r2]									\n"/* Program RNR = 7. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read fourth set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst2							\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write fourth set of RBAR/RLAR registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r3, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r4, #1										\n"/* r4 = 1. */
+            "	orrs r3, r4										\n"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+            "	str r3, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldm  r0!, {r1-r3}								\n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+            "	msr  psplim, r1									\n"/* Set this task's PSPLIM value. */
+            "	msr  control, r2								\n"/* Set this task's CONTROL value. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	bx   r3											\n"/* Finally, branch to EXC_RETURN. */
+        #else /* configENABLE_MPU */
+            "	ldm  r0!, {r1-r2}								\n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+            "	msr  psplim, r1									\n"/* Set this task's PSPLIM value. */
+            "	movs r1, #2										\n"/* r1 = 2. */
+            "	msr  CONTROL, r1								\n"/* Switch to use PSP in the thread mode. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	bx   r2											\n"/* Finally, branch to EXC_RETURN. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst2: .word 0xe000ed94					\n"
+            "xMAIR0Const2: .word 0xe000edc0						\n"
+            "xRNRConst2: .word 0xe000ed98						\n"
+            "xRBARConst2: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	tst r0, r1										\n"/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+        "	beq running_privileged							\n"/* If the result of previous AND operation was 0, branch. */
+        "	movs r0, #0										\n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "	bx lr											\n"/* Return. */
+        " running_privileged:								\n"
+        "	movs r0, #1										\n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "	bx lr											\n"/* Return. */
+        "													\n"
+        "	.align 4										\n"
+        ::: "r0", "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	mrs  r0, control								\n"/* Read the CONTROL register. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	bics r0, r1										\n"/* Clear the bit 0. */
+        "	msr  control, r0								\n"/* Write back the new CONTROL value. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	movs r1, #1										\n"/* r1 = 1. */
+        "	orrs r0, r1										\n"/* r0 = r0 | r1. */
+        "	msr control, r0									\n"/* CONTROL = r0. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	ldr r0, xVTORConst								\n"/* Use the NVIC offset register to locate the stack. */
+        "	ldr r0, [r0]									\n"/* Read the VTOR register which gives the address of vector table. */
+        "	ldr r0, [r0]									\n"/* The first entry in vector table is stack pointer. */
+        "	msr msp, r0										\n"/* Set the MSP back to the start of the stack. */
+        "	cpsie i											\n"/* Globally enable interrupts. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	svc %0											\n"/* System call to start the first task. */
+        "	nop												\n"
+        "													\n"
+        "   .align 4										\n"
+        "xVTORConst: .word 0xe000ed08						\n"
+        ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	mrs r0, PRIMASK									\n"
+        "	cpsid i											\n"
+        "	bx lr											\n"
+        ::: "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	msr PRIMASK, r0									\n"
+        "	bx lr											\n"
+        ::: "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, psp										\n"/* Read PSP in r0. */
+        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r2]									\n"/* Read pxCurrentTCB. */
+        #if ( configENABLE_MPU == 1 )
+            "	subs r0, r0, #44								\n"/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+            "	str r0, [r1]									\n"/* Save the new top of stack in TCB. */
+            "	mrs r1, psplim									\n"/* r1 = PSPLIM. */
+            "	mrs r2, control									\n"/* r2 = CONTROL. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmia r0!, {r1-r7}								\n"/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
+            "	mov r4, r8										\n"/* r4 = r8. */
+            "	mov r5, r9										\n"/* r5 = r9. */
+            "	mov r6, r10										\n"/* r6 = r10. */
+            "	mov r7, r11										\n"/* r7 = r11. */
+            "	stmia r0!, {r4-r7}								\n"/* Store the high registers that are not saved automatically. */
+        #else /* configENABLE_MPU */
+            "	subs r0, r0, #40								\n"/* Make space for PSPLIM, LR and the remaining registers on the stack. */
+            "	str r0, [r1]									\n"/* Save the new top of stack in TCB. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmia r0!, {r2-r7}								\n"/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
+            "	mov r4, r8										\n"/* r4 = r8. */
+            "	mov r5, r9										\n"/* r5 = r9. */
+            "	mov r6, r10										\n"/* r6 = r10. */
+            "	mov r7, r11										\n"/* r7 = r11. */
+            "	stmia r0!, {r4-r7}								\n"/* Store the high registers that are not saved automatically. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	cpsid i											\n"
+        "	bl vTaskSwitchContext							\n"
+        "	cpsie i											\n"
+        "													\n"
+        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr r0, [r1]									\n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r3, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r4, #1										\n"/* r4 = 1. */
+            "	bics r3, r4										\n"/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+            "	str r3, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+            "	ldr  r4, [r1]									\n"/* r4 = *r1 i.e. r4 = MAIR0. */
+            "	ldr  r2, xMAIR0Const							\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str  r4, [r2]									\n"/* Program MAIR0. */
+            "	ldr  r2, xRNRConst								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+            "	movs r4, #4										\n"/* r4 = 4. */
+            "	str  r4, [r2]									\n"/* Program RNR = 4. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read first set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst								\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write first set of RBAR/RLAR registers. */
+            "	movs r4, #5										\n"/* r4 = 5. */
+            "	str  r4, [r2]									\n"/* Program RNR = 5. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read second set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst								\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write second set of RBAR/RLAR registers. */
+            "	movs r4, #6										\n"/* r4 = 6. */
+            "	str  r4, [r2]									\n"/* Program RNR = 6. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read third set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst								\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write third set of RBAR/RLAR registers. */
+            "	movs r4, #7										\n"/* r4 = 7. */
+            "	str  r4, [r2]									\n"/* Program RNR = 7. */
+            "	ldmia r1!, {r5,r6}								\n"/* Read fourth set of RBAR/RLAR from TCB. */
+            "	ldr  r3, xRBARConst								\n"/* r3 = 0xe000ed9c [Location of RBAR]. */
+            "	stmia r3!, {r5,r6}								\n"/* Write fourth set of RBAR/RLAR registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r3, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	movs r4, #1										\n"/* r4 = 1. */
+            "	orrs r3, r4										\n"/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+            "	str r3, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	adds r0, r0, #28								\n"/* Move to the high registers. */
+            "	ldmia r0!, {r4-r7}								\n"/* Restore the high registers that are not automatically restored. */
+            "	mov r8, r4										\n"/* r8 = r4. */
+            "	mov r9, r5										\n"/* r9 = r5. */
+            "	mov r10, r6										\n"/* r10 = r6. */
+            "	mov r11, r7										\n"/* r11 = r7. */
+            "	msr psp, r0										\n"/* Remember the new top of stack for the task. */
+            "	subs r0, r0, #44								\n"/* Move to the starting of the saved context. */
+            "	ldmia r0!, {r1-r7}								\n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
+            "	msr psplim, r1									\n"/* Restore the PSPLIM register value for the task. */
+            "	msr control, r2									\n"/* Restore the CONTROL register value for the task. */
+            "	bx r3											\n"
+        #else /* configENABLE_MPU */
+            "	adds r0, r0, #24								\n"/* Move to the high registers. */
+            "	ldmia r0!, {r4-r7}								\n"/* Restore the high registers that are not automatically restored. */
+            "	mov r8, r4										\n"/* r8 = r4. */
+            "	mov r9, r5										\n"/* r9 = r5. */
+            "	mov r10, r6										\n"/* r10 = r6. */
+            "	mov r11, r7										\n"/* r11 = r7. */
+            "	msr psp, r0										\n"/* Remember the new top of stack for the task. */
+            "	subs r0, r0, #40								\n"/* Move to the starting of the saved context. */
+            "	ldmia r0!, {r2-r7}								\n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+            "	bx r3											\n"
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB				\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst: .word 0xe000ed94					\n"
+            "xMAIR0Const: .word 0xe000edc0						\n"
+            "xRNRConst: .word 0xe000ed98						\n"
+            "xRBARConst: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	movs r0, #4										\n"
+        "	mov r1, lr										\n"
+        "	tst r0, r1										\n"
+        "	beq stacking_used_msp							\n"
+        "	mrs r0, psp										\n"
+        "	ldr r2, svchandler_address_const				\n"
+        "	bx r2											\n"
+        " stacking_used_msp:								\n"
+        "	mrs r0, msp										\n"
+        "	ldr r2, svchandler_address_const				\n"
+        "	bx r2											\n"
+        "													\n"
+        "	.align 4										\n"
+        "svchandler_address_const: .word vPortSVCHandler_C	\n"
+    );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
new file mode 100644
index 0000000..b01f171
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
new file mode 100644
index 0000000..61cd152
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -0,0 +1,312 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+    #ifndef configENABLE_FPU
+        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+    #endif /* configENABLE_FPU */
+
+    #ifndef configENABLE_MPU
+        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+    #endif /* configENABLE_MPU */
+
+    #ifndef configENABLE_TRUSTZONE
+        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+    #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+    #define portARCH_NAME                      "Cortex-M23"
+    #define portSTACK_GROWTH                   ( -1 )
+    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT                 8
+    #define portNOP()
+    #define portINLINE                         __inline
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+    #endif
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
+    #define portDONT_DISCARD                   __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+    extern BaseType_t xPortIsInsideInterrupt( void );
+
+    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+    #endif /* configENABLE_TRUSTZONE */
+
+    #if ( configENABLE_MPU == 1 )
+        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+    #if ( configENABLE_MPU == 1 )
+        #define portUSING_MPU_WRAPPERS    1
+        #define portPRIVILEGE_BIT         ( 0x80000000UL )
+    #else
+        #define portPRIVILEGE_BIT         ( 0x0UL )
+    #endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
+    #define portSTACK_REGION                              ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
+    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
+    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
+    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
+    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
+    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+    } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
+    #define portSVC_FREE_SECURE_CONTEXT        1
+    #define portSVC_START_SCHEDULER            2
+    #define portSVC_RAISE_PRIVILEGE            3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+    #define portYIELD()                                 vPortYield()
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+    #define portDISABLE_INTERRUPTS()                  __asm volatile ( " cpsid i " ::: "memory" )
+    #define portENABLE_INTERRUPTS()                   __asm volatile ( " cpsie i " ::: "memory" )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+    #else
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+        #define portCLEAN_UP_TCB( pxTCB )
+    #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+        #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+        #define portRESET_PRIVILEGE()    vResetPrivilege()
+    #else
+        #define portIS_PRIVILEGED()
+        #define portRAISE_PRIVILEGE()
+        #define portRESET_PRIVILEGE()
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
new file mode 100644
index 0000000..c8c3c5f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
@@ -0,0 +1,705 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM3 port.
+*----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
+ * defined.  The value should also ensure backward compatibility.
+ * FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+    #define configKERNEL_INTERRUPT_PRIORITY    255
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
+#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                    ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK                   ( 0xFFUL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                      ( 0x01000000UL )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#define portMISSED_COUNTS_FACTOR              ( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__( ( naked ) );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__( ( naked ) );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__( ( naked ) );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    pxTopOfStack--;                                                      /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;             /* LR */
+    pxTopOfStack -= 5;                                                   /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters;                        /* R0 */
+    pxTopOfStack -= 8;                                                   /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    volatile uint32_t ulDummy = 0UL;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( uxCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being defined
+         * but never called.  ulDummy is used purely to quieten other warnings
+         * about code appearing after this function is called - making ulDummy
+         * volatile makes the compiler think the function could return and
+         * therefore not output an 'unreachable code' warning for code that appears
+         * after it. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+    __asm volatile (
+        "	ldr	r3, pxCurrentTCBConst2		\n"/* Restore the context. */
+        "	ldr r1, [r3]					\n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+        "	ldr r0, [r1]					\n"/* The first item in pxCurrentTCB is the task top of stack. */
+        "	ldmia r0!, {r4-r11}				\n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+        "	msr psp, r0						\n"/* Restore the task stack pointer. */
+        "	isb								\n"
+        "	mov r0, #0 						\n"
+        "	msr	basepri, r0					\n"
+        "	orr r14, #0xd					\n"
+        "	bx r14							\n"
+        "									\n"
+        "	.align 4						\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+        );
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+    __asm volatile (
+        " ldr r0, =0xE000ED08 	\n"/* Use the NVIC offset register to locate the stack. */
+        " ldr r0, [r0] 			\n"
+        " ldr r0, [r0] 			\n"
+        " msr msp, r0			\n"/* Set the msp back to the start of the stack. */
+        " cpsie i				\n"/* Globally enable interrupts. */
+        " cpsie f				\n"
+        " dsb					\n"
+        " isb					\n"
+        " svc 0					\n"/* System call to start first task. */
+        " nop					\n"
+        " .ltorg				\n"
+        );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+            volatile uint8_t ucMaxPriorityValue;
+
+            /* Determine the maximum priority from which ISR safe FreeRTOS API
+             * functions can be called.  ISR safe functions are those that end in
+             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+             * ensure interrupt entry is as fast and simple as possible.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+            /* Determine the number of priority bits available.  First write to all
+             * possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+            /* Use the same mask on the maximum system call priority. */
+            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+            /* Calculate the maximum acceptable priority group value for the number
+             * of bits read back. */
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+            {
+                ulMaxPRIGROUPValue--;
+                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+            }
+
+            #ifdef __NVIC_PRIO_BITS
+                {
+                    /* Check the CMSIS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+                }
+            #endif
+
+            #ifdef configPRIO_BITS
+                {
+                    /* Check the FreeRTOS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+                }
+            #endif
+
+            /* Shift the priority group value back to its position within the AIRCR
+             * register. */
+            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* conifgASSERT_DEFINED */
+
+    /* Make PendSV and SysTick the lowest priority interrupts. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Start the first task. */
+    prvPortStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing!  Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS.  Call
+     * vTaskSwitchContext() so link time optimisation does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
+    if( uxCriticalNesting == 1 )
+    {
+        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+    /* This is a naked function. */
+
+    __asm volatile
+    (
+        "	mrs r0, psp							\n"
+        "	isb									\n"
+        "										\n"
+        "	ldr	r3, pxCurrentTCBConst			\n"/* Get the location of the current TCB. */
+        "	ldr	r2, [r3]						\n"
+        "										\n"
+        "	stmdb r0!, {r4-r11}					\n"/* Save the remaining registers. */
+        "	str r0, [r2]						\n"/* Save the new top of stack into the first member of the TCB. */
+        "										\n"
+        "	stmdb sp!, {r3, r14}				\n"
+        "	mov r0, %0							\n"
+        "	msr basepri, r0						\n"
+        "	bl vTaskSwitchContext				\n"
+        "	mov r0, #0							\n"
+        "	msr basepri, r0						\n"
+        "	ldmia sp!, {r3, r14}				\n"
+        "										\n"/* Restore the context, including the critical nesting count. */
+        "	ldr r1, [r3]						\n"
+        "	ldr r0, [r1]						\n"/* The first item in pxCurrentTCB is the task top of stack. */
+        "	ldmia r0!, {r4-r11}					\n"/* Pop the registers. */
+        "	msr psp, r0							\n"
+        "	isb									\n"
+        "	bx r14								\n"
+        "										\n"
+        "	.align 4							\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB	\n"
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+     * executes all interrupts must be unmasked.  There is therefore no need to
+     * save and then restore the interrupt mask value as its value is already
+     * known. */
+    portDISABLE_INTERRUPTS();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* A context switch is required.  Context switching is performed in
+             * the PendSV interrupt.  Pend the PendSV interrupt. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+         * is accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods.  -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm volatile ( "cpsid i" ::: "memory" );
+        __asm volatile ( "dsb" );
+        __asm volatile ( "isb" );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above the cpsid instruction()
+             * above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again.  However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm volatile ( "dsb" ::: "memory" );
+                __asm volatile ( "wfi" );
+                __asm volatile ( "isb" );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately.  see comments above
+             * __disable_interrupt() call above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __asm volatile ( "cpsid i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is yet
+             * to count to zero (in which case an interrupt other than the SysTick
+             * must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+    }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and clear the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+    void vPortValidateInterruptPriority( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        uint8_t ucCurrentPriority;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that	use the FreeRTOS API must not be left at their
+             * default priority of	zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and	therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
+
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredictable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
+
+#endif /* configASSERT_DEFINED */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
new file mode 100644
index 0000000..3140278
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
@@ -0,0 +1,246 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
+    #define portDONT_DISCARD      __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+    #define portYIELD()                                 \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+                                                        \
+        /* Barriers are normally not required but do ensure the code is completely \
+         * within the specified behaviour for the architecture. */ \
+        __asm volatile ( "dsb" ::: "memory" );                     \
+        __asm volatile ( "isb" );                                  \
+    }
+
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired != pdFALSE ) portYIELD()
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
+    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
+    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #endif
+
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Generic helper function. */
+        __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+        {
+            uint8_t ucReturn;
+
+            __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+
+            return ucReturn;
+        }
+
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
+
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
+
+/* portNOP() is not required by this port. */
+    #define portNOP()
+
+    #define portINLINE              __inline
+
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
+    #endif
+
+/*-----------------------------------------------------------*/
+
+    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        BaseType_t xReturn;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+        if( ulCurrentInterrupt == 0 )
+        {
+            xReturn = pdFALSE;
+        }
+        else
+        {
+            xReturn = pdTRUE;
+        }
+
+        return xReturn;
+    }
+
+/*-----------------------------------------------------------*/
+
+    portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+    {
+        uint32_t ulNewBASEPRI;
+
+        __asm volatile
+        (
+            "	mov %0, %1												\n"\
+            "	msr basepri, %0											\n"\
+            "	isb														\n"\
+            "	dsb														\n"\
+            : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+        );
+    }
+
+/*-----------------------------------------------------------*/
+
+    portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+    {
+        uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+        __asm volatile
+        (
+            "	mrs %0, basepri											\n"\
+            "	mov %1, %2												\n"\
+            "	msr basepri, %1											\n"\
+            "	isb														\n"\
+            "	dsb														\n"\
+            : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+        );
+
+        /* This return will not be reached but is necessary to prevent compiler
+         * warnings. */
+        return ulOriginalBASEPRI;
+    }
+/*-----------------------------------------------------------*/
+
+    portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+    {
+        __asm volatile
+        (
+            "	msr basepri, %0	"::"r" ( ulNewMaskValue ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/port.c
new file mode 100644
index 0000000..b4639df
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/port.c
@@ -0,0 +1,1192 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if ( configENABLE_TRUSTZONE == 1 )
+    /* Secure components includes. */
+    #include "secure_context.h"
+    #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
+#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ            configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT          ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the
+ * same a the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE    ( 3UL )
+#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS      ( 20UL )
+#define portCPACR_CP11_POS      ( 22UL )
+
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS     ( 31UL )
+#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS     ( 30UL )
+#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS                ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS                ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS                ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS                ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS                ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS                ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS                ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS                ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE           ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The maximum 24-bit number.
+ *
+ * It is needed because the systick is a 24-bit counter.
+ */
+#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )
+
+/**
+ * @brief A fiddle factor to estimate the number of SysTick counts that would
+ * have occurred while the SysTick counter is stopped during tickless idle
+ * calculations.
+ */
+#define portMISSED_COUNTS_FACTOR    ( 45UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR    ( 0x01000000 )
+
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         FD
+ * 1111 1111  1111 1111  1111 1111  1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
+#else
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         BC
+ * 1111 1111  1111 1111  1111 1111  1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS    1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT    0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+
+/**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ *
+ * The implementation in this file is weak to allow application writers to
+ * change the timer used to generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether the current execution context is interrupt.
+ *
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE
+ * otherwise.
+ */
+BaseType_t xPortIsInsideInterrupt( void );
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+/**
+ * @brief The number of SysTick increments that make up one tick period.
+ */
+    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
+
+/**
+ * @brief The maximum number of tick periods that can be suppressed is
+ * limited by the 24 bit resolution of the SysTick timer.
+ */
+    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
+
+/**
+ * @brief Compensate for the CPU cycles that pass while the SysTick is
+ * stopped (low power functionality only).
+ */
+    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily. The time the SysTick is stopped for is
+         * accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods. -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm volatile ( "cpsid i" ::: "memory" );
+        __asm volatile ( "dsb" );
+        __asm volatile ( "isb" );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be un-suspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above the cpsid instruction()
+             * above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation
+             * contains its own wait for interrupt or wait for event
+             * instruction, and so wfi should not be executed again. However,
+             * the original expected idle time variable must remain unmodified,
+             * so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm volatile ( "dsb" ::: "memory" );
+                __asm volatile ( "wfi" );
+                __asm volatile ( "isb" );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately. See comments above
+             * the cpsid instruction above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will
+             * increase any slippage between the time maintained by the RTOS and
+             * calendar time. */
+            __asm volatile ( "cpsid i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
+             * Again, the time the SysTick is stopped for is accounted for as
+             * best it can be, but using the tickless mode will inevitably
+             * result in some tiny drift of the time maintained by the kernel
+             * with respect to calendar time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is
+             * yet to count to zero (in which case an interrupt other than the
+             * SysTick must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is
+                 * stepped forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+    }
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and reset the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    volatile uint32_t ulDummy = 0UL;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to. If a task wants to exit it
+     * should instead call vTaskDelete( NULL ). Artificially force an assert()
+     * to be triggered if configASSERT() is defined, then stop here so
+     * application writers can catch the error. */
+    configASSERT( ulCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being
+         * defined but never called.  ulDummy is used purely to quieten other
+         * warnings about code appearing after this function is called - making
+         * ulDummy volatile makes the compiler think the function could return
+         * and therefore not output an 'unreachable code' warning for code that
+         * appears after it. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __unprivileged_flash_start__;
+            extern uint32_t * __unprivileged_flash_end__;
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else /* if defined( __ARMCC_VERSION ) */
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __unprivileged_flash_start__[];
+            extern uint32_t __unprivileged_flash_end__[];
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Check that the MPU is present. */
+        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+        {
+            /* MAIR0 - Index 0. */
+            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+            /* MAIR0 - Index 1. */
+            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+            /* Setup privileged flash as Read Only so that privileged tasks can
+             * read it but not modify. */
+            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged flash as Read Only by both privileged and
+             * unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged syscalls flash as Read Only by both privileged
+             * and unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup RAM containing kernel data for privileged access only. */
+            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                               ( portMPU_REGION_EXECUTE_NEVER );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Enable mem fault. */
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
+
+            /* Enable MPU with privileged background access i.e. unmapped
+             * regions have privileged access. */
+            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_FPU == 1 )
+    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                /* Enable non-secure access to the FPU. */
+                SecureInit_EnableNSFPUAccess();
+            }
+        #endif /* configENABLE_TRUSTZONE */
+
+        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+         * unprivileged code should be able to access FPU. CP11 should be
+         * programmed to the same value as CP10. */
+        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+                            );
+
+        /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+         * context on exception entry and restore on exception return.
+         * LSPEN = 1 ==> Enable lazy context save of FP state. */
+        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+    }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Set a PendSV to request a context switch. */
+    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    portDISABLE_INTERRUPTS();
+    ulCriticalNesting++;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    configASSERT( ulCriticalNesting );
+    ulCriticalNesting--;
+
+    if( ulCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+    uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+    #if ( configENABLE_MPU == 1 )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+    #endif /* configENABLE_MPU */
+
+    uint32_t ulPC;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        uint32_t ulR0;
+        #if ( configENABLE_MPU == 1 )
+            uint32_t ulControl, ulIsTaskPrivileged;
+        #endif /* configENABLE_MPU */
+    #endif /* configENABLE_TRUSTZONE */
+    uint8_t ucSVCNumber;
+
+    /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+     * R12, LR, PC, xPSR. */
+    ulPC = pulCallerStackAddress[ 6 ];
+    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            case portSVC_ALLOCATE_SECURE_CONTEXT:
+
+                /* R0 contains the stack size passed as parameter to the
+                 * vPortAllocateSecureContext function. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                #if ( configENABLE_MPU == 1 )
+                    {
+                        /* Read the CONTROL register value. */
+                        __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+                        /* The task that raised the SVC is privileged if Bit[0]
+                         * in the CONTROL register is 0. */
+                        ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+                    }
+                #else /* if ( configENABLE_MPU == 1 ) */
+                    {
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0 );
+                    }
+                #endif /* configENABLE_MPU */
+
+                configASSERT( xSecureContext != NULL );
+                SecureContext_LoadContext( xSecureContext );
+                break;
+
+            case portSVC_FREE_SECURE_CONTEXT:
+                /* R0 contains the secure context handle to be freed. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                /* Free the secure context. */
+                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+                break;
+        #endif /* configENABLE_TRUSTZONE */
+
+        case portSVC_START_SCHEDULER:
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    /* De-prioritize the non-secure exceptions so that the
+                     * non-secure pendSV runs at the lowest priority. */
+                    SecureInit_DePrioritizeNSExceptions();
+
+                    /* Initialize the secure context management system. */
+                    SecureContext_Init();
+                }
+            #endif /* configENABLE_TRUSTZONE */
+
+            #if ( configENABLE_FPU == 1 )
+                {
+                    /* Setup the Floating Point Unit (FPU). */
+                    prvSetupFPU();
+                }
+            #endif /* configENABLE_FPU */
+
+            /* Setup the context of the first task so that the first task starts
+             * executing. */
+            vRestoreContextOfFirstTask();
+            break;
+
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_RAISE_PRIVILEGE:
+
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* configENABLE_MPU */
+
+        default:
+            /* Incorrect SVC call. */
+            configASSERT( pdFALSE );
+    }
+}
+/*-----------------------------------------------------------*/
+/* *INDENT-OFF* */
+#if ( configENABLE_MPU == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+/* *INDENT-ON* */
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    #if ( portPRELOAD_REGISTERS == 0 )
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #else /* portPRELOAD_REGISTERS */
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #endif /* portPRELOAD_REGISTERS */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    #if ( configENABLE_MPU == 1 )
+        {
+            /* Setup the Memory Protection Unit (MPU). */
+            prvSetupMPU();
+        }
+    #endif /* configENABLE_MPU */
+
+    /* Start the timer that generates the tick ISR. Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialize the critical nesting count ready for the first task. */
+    ulCriticalNesting = 0;
+
+    /* Start the first task. */
+    vStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing. Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. Call
+     * vTaskSwitchContext() so link time optimization does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here. */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    uint32_t ulStackDepth )
+    {
+        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+        int32_t lIndex = 0;
+
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Setup MAIR0. */
+        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid.  At all other
+         * times the stack parameters will not be valid and it is assumed that
+         * the stack region has already been configured. */
+        if( ulStackDepth > 0 )
+        {
+            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+
+            /* If the stack is within the privileged SRAM, do not protect it
+             * using a separate MPU region. This is needed because privileged
+             * SRAM is already protected using an MPU region and ARMv8-M does
+             * not allow overlapping MPU regions. */
+            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
+            {
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
+            }
+            else
+            {
+                /* Define the region that allows access to the stack. */
+                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+                                                             ( portMPU_REGION_NON_SHAREABLE ) |
+                                                             ( portMPU_REGION_READ_WRITE ) |
+                                                             ( portMPU_REGION_EXECUTE_NEVER );
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                                             ( portMPU_RLAR_REGION_ENABLE );
+            }
+        }
+
+        /* User supplied configurable regions. */
+        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+        {
+            /* If xRegions is NULL i.e. the task has not specified any MPU
+             * region, the else part ensures that all the configurable MPU
+             * regions are invalidated. */
+            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+            {
+                /* Translate the generic region definition contained in xRegions
+                 * into the ARMv8 specific MPU settings that are then stored in
+                 * xMPUSettings. */
+                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                /* Start address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+                                                                          ( portMPU_REGION_NON_SHAREABLE );
+
+                /* RO/RW. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+                }
+                else
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+                }
+
+                /* XN. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+                }
+
+                /* End Address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+                                                                          ( portMPU_RLAR_REGION_ENABLE );
+
+                /* Normal memory/ Device memory. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+                {
+                    /* Attr1 in MAIR0 is configured as device memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+                }
+                else
+                {
+                    /* Attr1 in MAIR0 is configured as normal memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+                }
+            }
+            else
+            {
+                /* Invalidate the region. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+            }
+
+            lIndex++;
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. Interrupt Program
+     * Status Register (IPSR) holds the exception number of the currently-executing
+     * exception or zero for Thread mode.*/
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c
new file mode 100644
index 0000000..aaab4cf
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c
@@ -0,0 +1,414 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr  r2, pxCurrentTCBConst2						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr  r3, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr  r0, [r3]									\n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	bic r4, #1										\n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+            "	ldr  r4, [r3]									\n"/* r4 = *r3 i.e. r4 = MAIR0. */
+            "	ldr  r2, xMAIR0Const2							\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str  r4, [r2]									\n"/* Program MAIR0. */
+            "	ldr  r2, xRNRConst2								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	movs r4, #4										\n"/* r4 = 4. */
+            "	str  r4, [r2]									\n"/* Program RNR = 4. */
+            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+            "	ldr  r2, xRBARConst2							\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r3!, {r4-r11}								\n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+            "	stmia r2!, {r4-r11}								\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	orr r4, #1										\n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldm  r0!, {r1-r4}								\n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+            "	ldr  r5, xSecureContextConst2					\n"
+            "	str  r1, [r5]									\n"/* Set xSecureContext to this task's value for the same. */
+            "	msr  psplim, r2									\n"/* Set this task's PSPLIM value. */
+            "	msr  control, r3								\n"/* Set this task's CONTROL value. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	mov  r0, #0										\n"
+            "	msr  basepri, r0								\n"/* Ensure that interrupts are enabled when the first task starts. */
+            "	bx   r4											\n"/* Finally, branch to EXC_RETURN. */
+        #else /* configENABLE_MPU */
+            "	ldm  r0!, {r1-r3}								\n"/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+            "	ldr  r4, xSecureContextConst2					\n"
+            "	str  r1, [r4]									\n"/* Set xSecureContext to this task's value for the same. */
+            "	msr  psplim, r2									\n"/* Set this task's PSPLIM value. */
+            "	movs r1, #2										\n"/* r1 = 2. */
+            "	msr  CONTROL, r1								\n"/* Switch to use PSP in the thread mode. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	mov  r0, #0										\n"
+            "	msr  basepri, r0								\n"/* Ensure that interrupts are enabled when the first task starts. */
+            "	bx   r3											\n"/* Finally, branch to EXC_RETURN. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+        "xSecureContextConst2: .word xSecureContext			\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst2: .word 0xe000ed94					\n"
+            "xMAIR0Const2: .word 0xe000edc0						\n"
+            "xRNRConst2: .word 0xe000ed98						\n"
+            "xRBARConst2: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	tst r0, #1										\n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "	ite ne											\n"
+        "	movne r0, #0									\n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "	moveq r0, #1									\n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "	bx lr											\n"/* Return. */
+        "													\n"
+        "	.align 4										\n"
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* Read the CONTROL register. */
+        "	bic r0, #1										\n"/* Clear the bit 0. */
+        "	msr control, r0									\n"/* Write back the new CONTROL value. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	orr r0, #1										\n"/* r0 = r0 | 1. */
+        "	msr control, r0									\n"/* CONTROL = r0. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	ldr r0, xVTORConst								\n"/* Use the NVIC offset register to locate the stack. */
+        "	ldr r0, [r0]									\n"/* Read the VTOR register which gives the address of vector table. */
+        "	ldr r0, [r0]									\n"/* The first entry in vector table is stack pointer. */
+        "	msr msp, r0										\n"/* Set the MSP back to the start of the stack. */
+        "	cpsie i											\n"/* Globally enable interrupts. */
+        "	cpsie f											\n"
+        "	dsb												\n"
+        "	isb												\n"
+        "	svc %0											\n"/* System call to start the first task. */
+        "	nop												\n"
+        "													\n"
+        "   .align 4										\n"
+        "xVTORConst: .word 0xe000ed08						\n"
+        ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	mrs r0, basepri									\n"/* r0 = basepri. Return original basepri value. */
+        "	mov r1, %0										\n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	msr basepri, r1									\n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bx lr											\n"/* Return. */
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	msr basepri, r0									\n"/* basepri = ulMask. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bx lr											\n"/* Return. */
+        ::: "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "	.extern SecureContext_SaveContext				\n"
+        "	.extern SecureContext_LoadContext				\n"
+        "													\n"
+        "	mrs r1, psp										\n"/* Read PSP in r1. */
+        "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+        "	ldr r0, [r2]									\n"/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+        "													\n"
+        "	cbz r0, save_ns_context							\n"/* No secure context to save. */
+        "	push {r0-r2, r14}								\n"
+        "	bl SecureContext_SaveContext					\n"
+        "	pop {r0-r3}										\n"/* LR is now in r3. */
+        "	mov lr, r3										\n"/* LR = r3. */
+        "	lsls r2, r3, #25								\n"/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+        "	bpl save_ns_context								\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r2, [r3]									\n"/* Read pxCurrentTCB. */
+        #if ( configENABLE_MPU == 1 )
+            "	subs r1, r1, #16								\n"/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mrs r3, control									\n"/* r3 = CONTROL. */
+            "	mov r4, lr										\n"/* r4 = LR/EXC_RETURN. */
+            "	stmia r1!, {r0, r2-r4}							\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+        #else /* configENABLE_MPU */
+            "	subs r1, r1, #12								\n"/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmia r1!, {r0, r2-r3}							\n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+        #endif /* configENABLE_MPU */
+        "	b select_next_task								\n"
+        "													\n"
+        " save_ns_context:									\n"
+        "	ldr r3, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r2, [r3]									\n"/* Read pxCurrentTCB. */
+        #if ( configENABLE_FPU == 1 )
+            "	tst lr, #0x10									\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+            "	it eq											\n"
+            "	vstmdbeq r1!, {s16-s31}							\n"/* Store the FPU registers which are not saved automatically. */
+        #endif /* configENABLE_FPU */
+        #if ( configENABLE_MPU == 1 )
+            "	subs r1, r1, #48								\n"/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	adds r1, r1, #16								\n"/* r1 = r1 + 16. */
+            "	stm r1, {r4-r11}								\n"/* Store the registers that are not saved automatically. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mrs r3, control									\n"/* r3 = CONTROL. */
+            "	mov r4, lr										\n"/* r4 = LR/EXC_RETURN. */
+            "	subs r1, r1, #16								\n"/* r1 = r1 - 16. */
+            "	stm r1, {r0, r2-r4}								\n"/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+        #else /* configENABLE_MPU */
+            "	subs r1, r1, #44								\n"/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+            "	str r1, [r2]									\n"/* Save the new top of stack in TCB. */
+            "	adds r1, r1, #12								\n"/* r1 = r1 + 12. */
+            "	stm r1, {r4-r11}								\n"/* Store the registers that are not saved automatically. */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	subs r1, r1, #12								\n"/* r1 = r1 - 12. */
+            "	stmia r1!, {r0, r2-r3}							\n"/* Store xSecureContext, PSPLIM and LR on the stack. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        " select_next_task:									\n"
+        "	mov r0, %0										\n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+        "	msr basepri, r0									\n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bl vTaskSwitchContext							\n"
+        "	mov r0, #0										\n"/* r0 = 0. */
+        "	msr basepri, r0									\n"/* Enable interrupts. */
+        "													\n"
+        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r3, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr r1, [r3]									\n"/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	bic r4, #1										\n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+            "	ldr r4, [r3]									\n"/* r4 = *r3 i.e. r4 = MAIR0. */
+            "	ldr r2, xMAIR0Const								\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str r4, [r2]									\n"/* Program MAIR0. */
+            "	ldr r2, xRNRConst								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	movs r4, #4										\n"/* r4 = 4. */
+            "	str r4, [r2]									\n"/* Program RNR = 4. */
+            "	adds r3, #4										\n"/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+            "	ldr  r2, xRBARConst								\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r3!, {r4-r11}								\n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "	stmia r2!, {r4-r11}								\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	orr r4, #1										\n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldmia r1!, {r0, r2-r4}							\n"/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+            "	msr control, r3									\n"/* Restore the CONTROL register value for the task. */
+            "	mov lr, r4										\n"/* LR = r4. */
+            "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "	str r0, [r2]									\n"/* Restore the task's xSecureContext. */
+            "	cbz r0, restore_ns_context						\n"/* If there is no secure context for the task, restore the non-secure context. */
+            "	push {r1,r4}									\n"
+            "	bl SecureContext_LoadContext					\n"/* Restore the secure context. */
+            "	pop {r1,r4}										\n"
+            "	mov lr, r4										\n"/* LR = r4. */
+            "	lsls r2, r4, #25								\n"/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "	bpl restore_ns_context							\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+            "	bx lr											\n"
+        #else /* configENABLE_MPU */
+            "	ldmia r1!, {r0, r2-r3}							\n"/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+            "	mov lr, r3										\n"/* LR = r3. */
+            "	ldr r2, xSecureContextConst						\n"/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+            "	str r0, [r2]									\n"/* Restore the task's xSecureContext. */
+            "	cbz r0, restore_ns_context						\n"/* If there is no secure context for the task, restore the non-secure context. */
+            "	push {r1,r3}									\n"
+            "	bl SecureContext_LoadContext					\n"/* Restore the secure context. */
+            "	pop {r1,r3}										\n"
+            "	mov lr, r3										\n"/* LR = r3. */
+            "	lsls r2, r3, #25								\n"/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+            "	bpl restore_ns_context							\n"/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+            "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+            "	bx lr											\n"
+        #endif /* configENABLE_MPU */
+        "													\n"
+        " restore_ns_context:								\n"
+        "	ldmia r1!, {r4-r11}								\n"/* Restore the registers that are not automatically restored. */
+        #if ( configENABLE_FPU == 1 )
+            "	tst lr, #0x10									\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+            "	it eq											\n"
+            "	vldmiaeq r1!, {s16-s31}							\n"/* Restore the FPU registers which are not restored automatically. */
+        #endif /* configENABLE_FPU */
+        "	msr psp, r1										\n"/* Remember the new top of stack for the task. */
+        "	bx lr											\n"
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB				\n"
+        "xSecureContextConst: .word xSecureContext			\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst: .word 0xe000ed94					\n"
+            "xMAIR0Const: .word 0xe000edc0						\n"
+            "xRNRConst: .word 0xe000ed98						\n"
+            "xRBARConst: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	tst lr, #4										\n"
+        "	ite eq											\n"
+        "	mrseq r0, msp									\n"
+        "	mrsne r0, psp									\n"
+        "	ldr r1, svchandler_address_const				\n"
+        "	bx r1											\n"
+        "													\n"
+        "	.align 4										\n"
+        "svchandler_address_const: .word vPortSVCHandler_C	\n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	svc %0											\n"/* Secure context is allocated in the supervisor call. */
+        "	bx lr											\n"/* Return. */
+        ::"i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	ldr r1, [r0]									\n"/* The first item in the TCB is the top of the stack. */
+        "	ldr r0, [r1]									\n"/* The first item on the stack is the task's xSecureContext. */
+        "	cmp r0, #0										\n"/* Raise svc if task's xSecureContext is not NULL. */
+        "	it ne											\n"
+        "	svcne %0										\n"/* Secure context is freed in the supervisor call. */
+        "	bx lr											\n"/* Return. */
+        ::"i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.h
new file mode 100644
index 0000000..b01f171
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h
new file mode 100644
index 0000000..8e3b0b3
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h
@@ -0,0 +1,312 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+    #ifndef configENABLE_FPU
+        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+    #endif /* configENABLE_FPU */
+
+    #ifndef configENABLE_MPU
+        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+    #endif /* configENABLE_MPU */
+
+    #ifndef configENABLE_TRUSTZONE
+        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+    #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+    #define portARCH_NAME                      "Cortex-M33"
+    #define portSTACK_GROWTH                   ( -1 )
+    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT                 8
+    #define portNOP()
+    #define portINLINE                         __inline
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+    #endif
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
+    #define portDONT_DISCARD                   __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+    extern BaseType_t xPortIsInsideInterrupt( void );
+
+    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+    #endif /* configENABLE_TRUSTZONE */
+
+    #if ( configENABLE_MPU == 1 )
+        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+    #if ( configENABLE_MPU == 1 )
+        #define portUSING_MPU_WRAPPERS    1
+        #define portPRIVILEGE_BIT         ( 0x80000000UL )
+    #else
+        #define portPRIVILEGE_BIT         ( 0x0UL )
+    #endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
+    #define portSTACK_REGION                              ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
+    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
+    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
+    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
+    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
+    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+    } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
+    #define portSVC_FREE_SECURE_CONTEXT        1
+    #define portSVC_START_SCHEDULER            2
+    #define portSVC_RAISE_PRIVILEGE            3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+    #define portYIELD()                                 vPortYield()
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+    #define portDISABLE_INTERRUPTS()                  ulSetInterruptMask()
+    #define portENABLE_INTERRUPTS()                   vClearInterruptMask( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+    #else
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+        #define portCLEAN_UP_TCB( pxTCB )
+    #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+        #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+        #define portRESET_PRIVILEGE()    vResetPrivilege()
+    #else
+        #define portIS_PRIVILEGED()
+        #define portRAISE_PRIVILEGE()
+        #define portRESET_PRIVILEGE()
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.c
new file mode 100644
index 0000000..046bf4e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.c
@@ -0,0 +1,206 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED      0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED    0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
+    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */
+    uint8_t * pucStackStart;          /**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* No stack for thread mode until a task's context is loaded. */
+        secureportSET_PSPLIM( securecontextNO_STACK );
+        secureportSET_PSP( securecontextNO_STACK );
+
+        #if ( configENABLE_MPU == 1 )
+            {
+                /* Configure thread mode to use PSP and to be unprivileged. */
+                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+            }
+        #else /* configENABLE_MPU */
+            {
+                /* Configure thread mode to use PSP and to be privileged.. */
+                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+            }
+        #endif /* configENABLE_MPU */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+                                                                                       uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+    uint8_t * pucStackMemory = NULL;
+    uint32_t ulIPSR;
+    SecureContextHandle_t xSecureContextHandle = NULL;
+
+    #if ( configENABLE_MPU == 1 )
+        uint32_t * pulCurrentStackPointer = NULL;
+    #endif /* configENABLE_MPU */
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* Allocate the context structure. */
+        xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+        if( xSecureContextHandle != NULL )
+        {
+            /* Allocate the stack space. */
+            pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+            if( pucStackMemory != NULL )
+            {
+                /* Since stack grows down, the starting point will be the last
+                 * location. Note that this location is next to the last
+                 * allocated byte because the hardware decrements the stack
+                 * pointer before writing i.e. if stack pointer is 0x2, a push
+                 * operation will decrement the stack pointer to 0x1 and then
+                 * write at 0x1. */
+                xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+                /* The stack cannot go beyond this location. This value is
+                 * programmed in the PSPLIM register on context switch.*/
+                xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+                #if ( configENABLE_MPU == 1 )
+                    {
+                        /* Store the correct CONTROL value for the task on the stack.
+                         * This value is programmed in the CONTROL register on
+                         * context switch. */
+                        pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+                        pulCurrentStackPointer--;
+
+                        if( ulIsTaskPrivileged )
+                        {
+                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+                        }
+                        else
+                        {
+                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                        }
+
+                        /* Store the current stack pointer. This value is programmed in
+                         * the PSP register on context switch. */
+                        xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                    }
+                #else /* configENABLE_MPU */
+                    {
+                        /* Current SP is set to the starting of the stack. This
+                         * value programmed in the PSP register on context switch. */
+                        xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+                    }
+                #endif /* configENABLE_MPU */
+            }
+            else
+            {
+                /* Free the context to avoid memory leak and make sure to return
+                 * NULL to indicate failure. */
+                vPortFree( xSecureContextHandle );
+                xSecureContextHandle = NULL;
+            }
+        }
+    }
+
+    return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* Ensure that valid parameters are passed. */
+        secureportASSERT( xSecureContextHandle != NULL );
+
+        /* Free the stack space. */
+        vPortFree( xSecureContextHandle->pucStackLimit );
+
+        /* Free the context itself. */
+        vPortFree( xSecureContextHandle );
+    }
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.h
new file mode 100644
index 0000000..532a407
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.h
@@ -0,0 +1,112 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK    0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext * SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if ( configENABLE_MPU == 1 )
+    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+                                                         uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
new file mode 100644
index 0000000..64b2e7a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
@@ -0,0 +1,88 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+    /* xSecureContextHandle value is in r0. */
+    __asm volatile
+    (
+        "	.syntax unified							\n"
+        "											\n"
+        "	mrs r1, ipsr							\n"/* r1 = IPSR. */
+        "	cbz r1, load_ctx_therad_mode			\n"/* Do nothing if the processor is running in the Thread Mode. */
+        "	ldmia r0!, {r1, r2}						\n"/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+        #if ( configENABLE_MPU == 1 )
+            "	ldmia r1!, {r3}							\n"/* Read CONTROL register value from task's stack. r3 = CONTROL. */
+            "	msr control, r3							\n"/* CONTROL = r3. */
+        #endif /* configENABLE_MPU */
+        "	msr psplim, r2							\n"/* PSPLIM = r2. */
+        "	msr psp, r1								\n"/* PSP = r1. */
+        "											\n"
+        " load_ctx_therad_mode:						\n"
+        "	nop										\n"
+        "											\n"
+        ::: "r0", "r1", "r2"
+    );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+    /* xSecureContextHandle value is in r0. */
+    __asm volatile
+    (
+        "	.syntax unified							\n"
+        "											\n"
+        "	mrs r1, ipsr							\n"/* r1 = IPSR. */
+        "	cbz r1, save_ctx_therad_mode			\n"/* Do nothing if the processor is running in the Thread Mode. */
+        "	mrs r1, psp								\n"/* r1 = PSP. */
+        #if ( configENABLE_FPU == 1 )
+            "	vstmdb r1!, {s0}						\n"/* Trigger the defferred stacking of FPU registers. */
+            "	vldmia r1!, {s0}						\n"/* Nullify the effect of the pervious statement. */
+        #endif /* configENABLE_FPU */
+        #if ( configENABLE_MPU == 1 )
+            "	mrs r2, control							\n"/* r2 = CONTROL. */
+            "	stmdb r1!, {r2}							\n"/* Store CONTROL value on the stack. */
+        #endif /* configENABLE_MPU */
+        "	str r1, [r0]							\n"/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+        "	movs r1, %0								\n"/* r1 = securecontextNO_STACK. */
+        "	msr psplim, r1							\n"/* PSPLIM = securecontextNO_STACK. */
+        "	msr psp, r1								\n"/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+        "											\n"
+        " save_ctx_therad_mode:						\n"
+        "	nop										\n"
+        "											\n"
+        ::"i" ( securecontextNO_STACK ) : "r1", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.c
new file mode 100644
index 0000000..82dbd9e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.c
@@ -0,0 +1,454 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+    #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+    #define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+    #define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
+
+/* The application writer has already defined the array used for the RTOS
+* heap - probably so it can be placed in a special segment or address. */
+    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
+    size_t xBlockSize;                     /**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, * pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+    BlockLink_t * pxFirstFreeBlock;
+    uint8_t * pucAlignedHeap;
+    size_t uxAddress;
+    size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+    /* Ensure the heap starts on a correctly aligned boundary. */
+    uxAddress = ( size_t ) ucHeap;
+
+    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+    {
+        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+    }
+
+    pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+    /* xStart is used to hold a pointer to the first item in the list of free
+     * blocks.  The void cast is used to prevent compiler warnings. */
+    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+    xStart.xBlockSize = ( size_t ) 0;
+
+    /* pxEnd is used to mark the end of the list of free blocks and is inserted
+     * at the end of the heap space. */
+    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+    uxAddress -= xHeapStructSize;
+    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+    pxEnd = ( void * ) uxAddress;
+    pxEnd->xBlockSize = 0;
+    pxEnd->pxNextFreeBlock = NULL;
+
+    /* To start with there is a single free block that is sized to take up the
+     * entire heap space, minus the space taken by pxEnd. */
+    pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+    /* Only one block exists - and it covers the entire usable heap space. */
+    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+    /* Work out the position of the top bit in a size_t variable. */
+    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
+{
+    BlockLink_t * pxIterator;
+    uint8_t * puc;
+
+    /* Iterate through the list until a block is found that has a higher address
+     * than the block being inserted. */
+    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+    {
+        /* Nothing to do here, just iterate to the right position. */
+    }
+
+    /* Do the block being inserted, and the block it is being inserted after
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxIterator;
+
+    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+    {
+        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+        pxBlockToInsert = pxIterator;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Do the block being inserted, and the block it is being inserted before
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxBlockToInsert;
+
+    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+    {
+        if( pxIterator->pxNextFreeBlock != pxEnd )
+        {
+            /* Form one big block from the two blocks. */
+            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+        }
+        else
+        {
+            pxBlockToInsert->pxNextFreeBlock = pxEnd;
+        }
+    }
+    else
+    {
+        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+    }
+
+    /* If the block being inserted plugged a gab, so was merged with the block
+     * before and the block after, then it's pxNextFreeBlock pointer will have
+     * already been set, and should not be set here as that would make it point
+     * to itself. */
+    if( pxIterator != pxBlockToInsert )
+    {
+        pxIterator->pxNextFreeBlock = pxBlockToInsert;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void * pvPortMalloc( size_t xWantedSize )
+{
+    BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
+    void * pvReturn = NULL;
+
+    /* If this is the first call to malloc then the heap will require
+     * initialisation to setup the list of free blocks. */
+    if( pxEnd == NULL )
+    {
+        prvHeapInit();
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    {
+        /* The wanted size is increased so it can contain a BlockLink_t
+         * structure in addition to the requested amount of bytes. */
+        if( xWantedSize > 0 )
+        {
+            xWantedSize += xHeapStructSize;
+
+            /* Ensure that blocks are always aligned to the required number of
+             * bytes. */
+            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+            {
+                /* Byte alignment required. */
+                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+        {
+            /* Traverse the list from the start (lowest address) block until
+             * one of adequate size is found. */
+            pxPreviousBlock = &xStart;
+            pxBlock = xStart.pxNextFreeBlock;
+
+            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+            {
+                pxPreviousBlock = pxBlock;
+                pxBlock = pxBlock->pxNextFreeBlock;
+            }
+
+            /* If the end marker was reached then a block of adequate size was
+             * not found. */
+            if( pxBlock != pxEnd )
+            {
+                /* Return the memory space pointed to - jumping over the
+                 * BlockLink_t structure at its start. */
+                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+                /* This block is being returned for use so must be taken out
+                 * of the list of free blocks. */
+                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+                /* If the block is larger than required it can be split into
+                 * two. */
+                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+                {
+                    /* This block is to be split into two.  Create a new
+                     * block following the number of bytes requested. The void
+                     * cast is used to prevent byte alignment warnings from the
+                     * compiler. */
+                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+                    /* Calculate the sizes of two blocks split from the single
+                     * block. */
+                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+                    pxBlock->xBlockSize = xWantedSize;
+
+                    /* Insert the new block into the list of free blocks. */
+                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+                {
+                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                /* The block is being returned - it is allocated and owned by
+                 * the application and has no "next" block. */
+                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                pxBlock->pxNextFreeBlock = NULL;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    traceMALLOC( pvReturn, xWantedSize );
+
+    #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+        {
+            if( pvReturn == NULL )
+            {
+                extern void vApplicationMallocFailedHook( void );
+                vApplicationMallocFailedHook();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
+
+    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+    return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void * pv )
+{
+    uint8_t * puc = ( uint8_t * ) pv;
+    BlockLink_t * pxLink;
+
+    if( pv != NULL )
+    {
+        /* The memory being freed will have an BlockLink_t structure immediately
+         * before it. */
+        puc -= xHeapStructSize;
+
+        /* This casting is to keep the compiler from issuing warnings. */
+        pxLink = ( void * ) puc;
+
+        /* Check the block is actually allocated. */
+        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        {
+            if( pxLink->pxNextFreeBlock == NULL )
+            {
+                /* The block is being returned to the heap - it is no longer
+                 * allocated. */
+                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+                secureportDISABLE_NON_SECURE_INTERRUPTS();
+                {
+                    /* Add this block to the list of free blocks. */
+                    xFreeBytesRemaining += pxLink->xBlockSize;
+                    traceFREE( pv, pxLink->xBlockSize );
+                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+                }
+                secureportENABLE_NON_SECURE_INTERRUPTS();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+    return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+    return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+    /* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.h
new file mode 100644
index 0000000..fa78046
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void * pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void * pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.c
new file mode 100644
index 0000000..4e6018d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS          ( 29UL )
+#define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS              ( 26UL )
+#define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS            ( 10UL )
+#define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS            ( 11UL )
+#define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+                                   ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+                                   ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
+    }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+         * permitted. CP11 should be programmed to the same value as CP10. */
+        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+         * that we can enable/disable lazy stacking in port.c file. */
+        *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
+
+        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+         * registers (S16-S31) are also pushed to stack on exception entry and
+         * restored on exception return. */
+        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+    }
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.h
new file mode 100644
index 0000000..39deb36
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h
new file mode 100644
index 0000000..7b8dbed
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT         8
+#define secureportBYTE_ALIGNMENT_MASK    ( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+    #define secureportNON_SECURE_CALLABLE    __cmse_nonsecure_entry __root
+#else
+    #define secureportNON_SECURE_CALLABLE    __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+    __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+    __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+    __asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+    __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+    __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+    __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+    __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+    __asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL     0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS()     secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x )                      \
+    if( ( x ) == 0 )                               \
+    {                                              \
+        secureportDISABLE_SECURE_INTERRUPTS();     \
+        secureportDISABLE_NON_SECURE_INTERRUPTS(); \
+        for( ; ; ) {; }                            \
+    }
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
new file mode 100644
index 0000000..852a11c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
@@ -0,0 +1,1192 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if ( configENABLE_TRUSTZONE == 1 )
+    /* Secure components includes. */
+    #include "secure_context.h"
+    #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
+#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ            configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT          ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the
+ * same a the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE    ( 3UL )
+#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS      ( 20UL )
+#define portCPACR_CP11_POS      ( 22UL )
+
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS     ( 31UL )
+#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS     ( 30UL )
+#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS                ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS                ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS                ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS                ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS                ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS                ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS                ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS                ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE           ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The maximum 24-bit number.
+ *
+ * It is needed because the systick is a 24-bit counter.
+ */
+#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )
+
+/**
+ * @brief A fiddle factor to estimate the number of SysTick counts that would
+ * have occurred while the SysTick counter is stopped during tickless idle
+ * calculations.
+ */
+#define portMISSED_COUNTS_FACTOR    ( 45UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR    ( 0x01000000 )
+
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         FD
+ * 1111 1111  1111 1111  1111 1111  1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
+#else
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         BC
+ * 1111 1111  1111 1111  1111 1111  1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS    1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT    0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+
+/**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ *
+ * The implementation in this file is weak to allow application writers to
+ * change the timer used to generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether the current execution context is interrupt.
+ *
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE
+ * otherwise.
+ */
+BaseType_t xPortIsInsideInterrupt( void );
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+/**
+ * @brief The number of SysTick increments that make up one tick period.
+ */
+    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
+
+/**
+ * @brief The maximum number of tick periods that can be suppressed is
+ * limited by the 24 bit resolution of the SysTick timer.
+ */
+    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
+
+/**
+ * @brief Compensate for the CPU cycles that pass while the SysTick is
+ * stopped (low power functionality only).
+ */
+    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily. The time the SysTick is stopped for is
+         * accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods. -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm volatile ( "cpsid i" ::: "memory" );
+        __asm volatile ( "dsb" );
+        __asm volatile ( "isb" );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be un-suspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above the cpsid instruction()
+             * above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation
+             * contains its own wait for interrupt or wait for event
+             * instruction, and so wfi should not be executed again. However,
+             * the original expected idle time variable must remain unmodified,
+             * so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm volatile ( "dsb" ::: "memory" );
+                __asm volatile ( "wfi" );
+                __asm volatile ( "isb" );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately. See comments above
+             * the cpsid instruction above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will
+             * increase any slippage between the time maintained by the RTOS and
+             * calendar time. */
+            __asm volatile ( "cpsid i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
+             * Again, the time the SysTick is stopped for is accounted for as
+             * best it can be, but using the tickless mode will inevitably
+             * result in some tiny drift of the time maintained by the kernel
+             * with respect to calendar time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is
+             * yet to count to zero (in which case an interrupt other than the
+             * SysTick must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is
+                 * stepped forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+    }
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and reset the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    volatile uint32_t ulDummy = 0UL;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to. If a task wants to exit it
+     * should instead call vTaskDelete( NULL ). Artificially force an assert()
+     * to be triggered if configASSERT() is defined, then stop here so
+     * application writers can catch the error. */
+    configASSERT( ulCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being
+         * defined but never called.  ulDummy is used purely to quieten other
+         * warnings about code appearing after this function is called - making
+         * ulDummy volatile makes the compiler think the function could return
+         * and therefore not output an 'unreachable code' warning for code that
+         * appears after it. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __unprivileged_flash_start__;
+            extern uint32_t * __unprivileged_flash_end__;
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else /* if defined( __ARMCC_VERSION ) */
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __unprivileged_flash_start__[];
+            extern uint32_t __unprivileged_flash_end__[];
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Check that the MPU is present. */
+        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+        {
+            /* MAIR0 - Index 0. */
+            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+            /* MAIR0 - Index 1. */
+            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+            /* Setup privileged flash as Read Only so that privileged tasks can
+             * read it but not modify. */
+            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged flash as Read Only by both privileged and
+             * unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged syscalls flash as Read Only by both privileged
+             * and unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup RAM containing kernel data for privileged access only. */
+            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                               ( portMPU_REGION_EXECUTE_NEVER );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Enable mem fault. */
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
+
+            /* Enable MPU with privileged background access i.e. unmapped
+             * regions have privileged access. */
+            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_FPU == 1 )
+    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                /* Enable non-secure access to the FPU. */
+                SecureInit_EnableNSFPUAccess();
+            }
+        #endif /* configENABLE_TRUSTZONE */
+
+        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+         * unprivileged code should be able to access FPU. CP11 should be
+         * programmed to the same value as CP10. */
+        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+                            );
+
+        /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+         * context on exception entry and restore on exception return.
+         * LSPEN = 1 ==> Enable lazy context save of FP state. */
+        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+    }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Set a PendSV to request a context switch. */
+    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    portDISABLE_INTERRUPTS();
+    ulCriticalNesting++;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    configASSERT( ulCriticalNesting );
+    ulCriticalNesting--;
+
+    if( ulCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+    uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+    #if ( configENABLE_MPU == 1 )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+    #endif /* configENABLE_MPU */
+
+    uint32_t ulPC;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        uint32_t ulR0;
+        #if ( configENABLE_MPU == 1 )
+            uint32_t ulControl, ulIsTaskPrivileged;
+        #endif /* configENABLE_MPU */
+    #endif /* configENABLE_TRUSTZONE */
+    uint8_t ucSVCNumber;
+
+    /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+     * R12, LR, PC, xPSR. */
+    ulPC = pulCallerStackAddress[ 6 ];
+    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            case portSVC_ALLOCATE_SECURE_CONTEXT:
+
+                /* R0 contains the stack size passed as parameter to the
+                 * vPortAllocateSecureContext function. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                #if ( configENABLE_MPU == 1 )
+                    {
+                        /* Read the CONTROL register value. */
+                        __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+                        /* The task that raised the SVC is privileged if Bit[0]
+                         * in the CONTROL register is 0. */
+                        ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+                    }
+                #else /* if ( configENABLE_MPU == 1 ) */
+                    {
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0 );
+                    }
+                #endif /* configENABLE_MPU */
+
+                configASSERT( xSecureContext != NULL );
+                SecureContext_LoadContext( xSecureContext );
+                break;
+
+            case portSVC_FREE_SECURE_CONTEXT:
+                /* R0 contains the secure context handle to be freed. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                /* Free the secure context. */
+                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+                break;
+        #endif /* configENABLE_TRUSTZONE */
+
+        case portSVC_START_SCHEDULER:
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    /* De-prioritize the non-secure exceptions so that the
+                     * non-secure pendSV runs at the lowest priority. */
+                    SecureInit_DePrioritizeNSExceptions();
+
+                    /* Initialize the secure context management system. */
+                    SecureContext_Init();
+                }
+            #endif /* configENABLE_TRUSTZONE */
+
+            #if ( configENABLE_FPU == 1 )
+                {
+                    /* Setup the Floating Point Unit (FPU). */
+                    prvSetupFPU();
+                }
+            #endif /* configENABLE_FPU */
+
+            /* Setup the context of the first task so that the first task starts
+             * executing. */
+            vRestoreContextOfFirstTask();
+            break;
+
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_RAISE_PRIVILEGE:
+
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* configENABLE_MPU */
+
+        default:
+            /* Incorrect SVC call. */
+            configASSERT( pdFALSE );
+    }
+}
+/*-----------------------------------------------------------*/
+/* *INDENT-OFF* */
+#if ( configENABLE_MPU == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+/* *INDENT-ON* */
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    #if ( portPRELOAD_REGISTERS == 0 )
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #else /* portPRELOAD_REGISTERS */
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #endif /* portPRELOAD_REGISTERS */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    #if ( configENABLE_MPU == 1 )
+        {
+            /* Setup the Memory Protection Unit (MPU). */
+            prvSetupMPU();
+        }
+    #endif /* configENABLE_MPU */
+
+    /* Start the timer that generates the tick ISR. Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialize the critical nesting count ready for the first task. */
+    ulCriticalNesting = 0;
+
+    /* Start the first task. */
+    vStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing. Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. Call
+     * vTaskSwitchContext() so link time optimization does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here. */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    uint32_t ulStackDepth )
+    {
+        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+        int32_t lIndex = 0;
+
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Setup MAIR0. */
+        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid.  At all other
+         * times the stack parameters will not be valid and it is assumed that
+         * the stack region has already been configured. */
+        if( ulStackDepth > 0 )
+        {
+            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+
+            /* If the stack is within the privileged SRAM, do not protect it
+             * using a separate MPU region. This is needed because privileged
+             * SRAM is already protected using an MPU region and ARMv8-M does
+             * not allow overlapping MPU regions. */
+            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
+            {
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
+            }
+            else
+            {
+                /* Define the region that allows access to the stack. */
+                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+                                                             ( portMPU_REGION_NON_SHAREABLE ) |
+                                                             ( portMPU_REGION_READ_WRITE ) |
+                                                             ( portMPU_REGION_EXECUTE_NEVER );
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                                             ( portMPU_RLAR_REGION_ENABLE );
+            }
+        }
+
+        /* User supplied configurable regions. */
+        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+        {
+            /* If xRegions is NULL i.e. the task has not specified any MPU
+             * region, the else part ensures that all the configurable MPU
+             * regions are invalidated. */
+            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+            {
+                /* Translate the generic region definition contained in xRegions
+                 * into the ARMv8 specific MPU settings that are then stored in
+                 * xMPUSettings. */
+                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                /* Start address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+                                                                          ( portMPU_REGION_NON_SHAREABLE );
+
+                /* RO/RW. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+                }
+                else
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+                }
+
+                /* XN. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+                }
+
+                /* End Address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+                                                                          ( portMPU_RLAR_REGION_ENABLE );
+
+                /* Normal memory/ Device memory. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+                {
+                    /* Attr1 in MAIR0 is configured as device memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+                }
+                else
+                {
+                    /* Attr1 in MAIR0 is configured as normal memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+                }
+            }
+            else
+            {
+                /* Invalidate the region. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+            }
+
+            lIndex++;
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. Interrupt Program
+     * Status Register (IPSR) holds the exception number of the currently-executing
+     * exception or zero for Thread mode.*/
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
new file mode 100644
index 0000000..98927a7
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
@@ -0,0 +1,320 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
+ * is defined correctly and privileged functions are placed in correct sections. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Portasm includes. */
+#include "portasm.h"
+
+/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
+ * header files. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	ldr  r2, pxCurrentTCBConst2						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr  r1, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr  r0, [r1]									\n"/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	bic r4, #1										\n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+            "	ldr  r3, [r1]									\n"/* r3 = *r1 i.e. r3 = MAIR0. */
+            "	ldr  r2, xMAIR0Const2							\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str  r3, [r2]									\n"/* Program MAIR0. */
+            "	ldr  r2, xRNRConst2								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	movs r3, #4										\n"/* r3 = 4. */
+            "	str  r3, [r2]									\n"/* Program RNR = 4. */
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+            "	ldr  r2, xRBARConst2							\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r1!, {r4-r11}								\n"/* Read 4 set of RBAR/RLAR registers from TCB. */
+            "	stmia r2!, {r4-r11}								\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst2							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	orr r4, #1										\n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldm  r0!, {r1-r3}								\n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+            "	msr  psplim, r1									\n"/* Set this task's PSPLIM value. */
+            "	msr  control, r2								\n"/* Set this task's CONTROL value. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	mov  r0, #0										\n"
+            "	msr  basepri, r0								\n"/* Ensure that interrupts are enabled when the first task starts. */
+            "	bx   r3											\n"/* Finally, branch to EXC_RETURN. */
+        #else /* configENABLE_MPU */
+            "	ldm  r0!, {r1-r2}								\n"/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+            "	msr  psplim, r1									\n"/* Set this task's PSPLIM value. */
+            "	movs r1, #2										\n"/* r1 = 2. */
+            "	msr  CONTROL, r1								\n"/* Switch to use PSP in the thread mode. */
+            "	adds r0, #32									\n"/* Discard everything up to r0. */
+            "	msr  psp, r0									\n"/* This is now the new top of stack to use in the task. */
+            "	isb												\n"
+            "	mov  r0, #0										\n"
+            "	msr  basepri, r0								\n"/* Ensure that interrupts are enabled when the first task starts. */
+            "	bx   r2											\n"/* Finally, branch to EXC_RETURN. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst2: .word 0xe000ed94					\n"
+            "xMAIR0Const2: .word 0xe000edc0						\n"
+            "xRNRConst2: .word 0xe000ed98						\n"
+            "xRBARConst2: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+    );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	tst r0, #1										\n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "	ite ne											\n"
+        "	movne r0, #0									\n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "	moveq r0, #1									\n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "	bx lr											\n"/* Return. */
+        "													\n"
+        "	.align 4										\n"
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	mrs  r0, control								\n"/* Read the CONTROL register. */
+        "	bic r0, #1										\n"/* Clear the bit 0. */
+        "	msr  control, r0								\n"/* Write back the new CONTROL value. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control									\n"/* r0 = CONTROL. */
+        "	orr r0, #1										\n"/* r0 = r0 | 1. */
+        "	msr control, r0									\n"/* CONTROL = r0. */
+        "	bx lr											\n"/* Return to the caller. */
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	ldr r0, xVTORConst								\n"/* Use the NVIC offset register to locate the stack. */
+        "	ldr r0, [r0]									\n"/* Read the VTOR register which gives the address of vector table. */
+        "	ldr r0, [r0]									\n"/* The first entry in vector table is stack pointer. */
+        "	msr msp, r0										\n"/* Set the MSP back to the start of the stack. */
+        "	cpsie i											\n"/* Globally enable interrupts. */
+        "	cpsie f											\n"
+        "	dsb												\n"
+        "	isb												\n"
+        "	svc %0											\n"/* System call to start the first task. */
+        "	nop												\n"
+        "													\n"
+        "   .align 4										\n"
+        "xVTORConst: .word 0xe000ed08						\n"
+        ::"i" ( portSVC_START_SCHEDULER ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	mrs r0, basepri									\n"/* r0 = basepri. Return original basepri value. */
+        "	mov r1, %0										\n"/* r1 = configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	msr basepri, r1									\n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bx lr											\n"/* Return. */
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vClearInterruptMask( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	msr basepri, r0									\n"/* basepri = ulMask. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bx lr											\n"/* Return. */
+        ::: "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	.syntax unified									\n"
+        "													\n"
+        "	mrs r0, psp										\n"/* Read PSP in r0. */
+        #if ( configENABLE_FPU == 1 )
+            "	tst lr, #0x10									\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+            "	it eq											\n"
+            "	vstmdbeq r0!, {s16-s31}							\n"/* Store the FPU registers which are not saved automatically. */
+        #endif /* configENABLE_FPU */
+        #if ( configENABLE_MPU == 1 )
+            "	mrs r1, psplim									\n"/* r1 = PSPLIM. */
+            "	mrs r2, control									\n"/* r2 = CONTROL. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmdb r0!, {r1-r11}								\n"/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+        #else /* configENABLE_MPU */
+            "	mrs r2, psplim									\n"/* r2 = PSPLIM. */
+            "	mov r3, lr										\n"/* r3 = LR/EXC_RETURN. */
+            "	stmdb r0!, {r2-r11}								\n"/* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r2]									\n"/* Read pxCurrentTCB. */
+        "	str r0, [r1]									\n"/* Save the new top of stack in TCB. */
+        "													\n"
+        "	mov r0, %0										\n"/* r0 = configMAX_SYSCALL_INTERRUPT_PRIORITY */
+        "	msr basepri, r0									\n"/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+        "	dsb												\n"
+        "	isb												\n"
+        "	bl vTaskSwitchContext							\n"
+        "	mov r0, #0										\n"/* r0 = 0. */
+        "	msr basepri, r0									\n"/* Enable interrupts. */
+        "													\n"
+        "	ldr r2, pxCurrentTCBConst						\n"/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+        "	ldr r1, [r2]									\n"/* Read pxCurrentTCB. */
+        "	ldr r0, [r1]									\n"/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	dmb												\n"/* Complete outstanding transfers before disabling MPU. */
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	bic r4, #1										\n"/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Disable MPU. */
+            "													\n"
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+            "	ldr r3, [r1]									\n"/* r3 = *r1 i.e. r3 = MAIR0. */
+            "	ldr r2, xMAIR0Const								\n"/* r2 = 0xe000edc0 [Location of MAIR0]. */
+            "	str r3, [r2]									\n"/* Program MAIR0. */
+            "	ldr r2, xRNRConst								\n"/* r2 = 0xe000ed98 [Location of RNR]. */
+            "	movs r3, #4										\n"/* r3 = 4. */
+            "	str r3, [r2]									\n"/* Program RNR = 4. */
+            "	adds r1, #4										\n"/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+            "	ldr r2, xRBARConst								\n"/* r2 = 0xe000ed9c [Location of RBAR]. */
+            "	ldmia r1!, {r4-r11}								\n"/* Read 4 sets of RBAR/RLAR registers from TCB. */
+            "	stmia r2!, {r4-r11}								\n"/* Write 4 set of RBAR/RLAR registers using alias registers. */
+            "													\n"
+            "	ldr r2, xMPUCTRLConst							\n"/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+            "	ldr r4, [r2]									\n"/* Read the value of MPU_CTRL. */
+            "	orr r4, #1										\n"/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+            "	str r4, [r2]									\n"/* Enable MPU. */
+            "	dsb												\n"/* Force memory writes before continuing. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	ldmia r0!, {r1-r11}								\n"/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+        #else /* configENABLE_MPU */
+            "	ldmia r0!, {r2-r11}								\n"/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+        #endif /* configENABLE_MPU */
+        "													\n"
+        #if ( configENABLE_FPU == 1 )
+            "	tst r3, #0x10									\n"/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+            "	it eq											\n"
+            "	vldmiaeq r0!, {s16-s31}							\n"/* Restore the FPU registers which are not restored automatically. */
+        #endif /* configENABLE_FPU */
+        "													\n"
+        #if ( configENABLE_MPU == 1 )
+            "	msr psplim, r1									\n"/* Restore the PSPLIM register value for the task. */
+            "	msr control, r2									\n"/* Restore the CONTROL register value for the task. */
+        #else /* configENABLE_MPU */
+            "	msr psplim, r2									\n"/* Restore the PSPLIM register value for the task. */
+        #endif /* configENABLE_MPU */
+        "	msr psp, r0										\n"/* Remember the new top of stack for the task. */
+        "	bx r3											\n"
+        "													\n"
+        "	.align 4										\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB				\n"
+        #if ( configENABLE_MPU == 1 )
+            "xMPUCTRLConst: .word 0xe000ed94					\n"
+            "xMAIR0Const: .word 0xe000edc0						\n"
+            "xRNRConst: .word 0xe000ed98						\n"
+            "xRBARConst: .word 0xe000ed9c						\n"
+        #endif /* configENABLE_MPU */
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    );
+}
+/*-----------------------------------------------------------*/
+
+void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
+{
+    __asm volatile
+    (
+        "	tst lr, #4										\n"
+        "	ite eq											\n"
+        "	mrseq r0, msp									\n"
+        "	mrsne r0, psp									\n"
+        "	ldr r1, svchandler_address_const				\n"
+        "	bx r1											\n"
+        "													\n"
+        "	.align 4										\n"
+        "svchandler_address_const: .word vPortSVCHandler_C	\n"
+    );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
new file mode 100644
index 0000000..b01f171
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
new file mode 100644
index 0000000..8e3b0b3
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -0,0 +1,312 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+    #ifndef configENABLE_FPU
+        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+    #endif /* configENABLE_FPU */
+
+    #ifndef configENABLE_MPU
+        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+    #endif /* configENABLE_MPU */
+
+    #ifndef configENABLE_TRUSTZONE
+        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+    #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+    #define portARCH_NAME                      "Cortex-M33"
+    #define portSTACK_GROWTH                   ( -1 )
+    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT                 8
+    #define portNOP()
+    #define portINLINE                         __inline
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+    #endif
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
+    #define portDONT_DISCARD                   __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+    extern BaseType_t xPortIsInsideInterrupt( void );
+
+    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+    #endif /* configENABLE_TRUSTZONE */
+
+    #if ( configENABLE_MPU == 1 )
+        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+    #if ( configENABLE_MPU == 1 )
+        #define portUSING_MPU_WRAPPERS    1
+        #define portPRIVILEGE_BIT         ( 0x80000000UL )
+    #else
+        #define portPRIVILEGE_BIT         ( 0x0UL )
+    #endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
+    #define portSTACK_REGION                              ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
+    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
+    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
+    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
+    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
+    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+    } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
+    #define portSVC_FREE_SECURE_CONTEXT        1
+    #define portSVC_START_SCHEDULER            2
+    #define portSVC_RAISE_PRIVILEGE            3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+    #define portYIELD()                                 vPortYield()
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+    #define portDISABLE_INTERRUPTS()                  ulSetInterruptMask()
+    #define portENABLE_INTERRUPTS()                   vClearInterruptMask( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+    #else
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+        #define portCLEAN_UP_TCB( pxTCB )
+    #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+        #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+        #define portRESET_PRIVILEGE()    vResetPrivilege()
+    #else
+        #define portIS_PRIVILEGED()
+        #define portRAISE_PRIVILEGE()
+        #define portRESET_PRIVILEGE()
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
new file mode 100644
index 0000000..a1f70dd
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
@@ -0,0 +1,875 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM3 MPU port.
+*----------------------------------------------------------*/
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ    configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK      ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+    #define portNVIC_SYSTICK_CLK    ( 0 )
+#endif
+
+/* Constants required to access and manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG                 ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG        ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                        ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SHPR2_REG                        ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
+#define portNVIC_SYS_CTRL_STATE_REG               ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
+#define portNVIC_MEM_FAULT_ENABLE                 ( 1UL << 16UL )
+
+/* Constants required to access and manipulate the MPU. */
+#define portMPU_TYPE_REG                          ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_REGION_BASE_ADDRESS_REG           ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
+#define portMPU_REGION_ATTRIBUTE_REG              ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
+#define portMPU_CTRL_REG                          ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portEXPECTED_MPU_TYPE_VALUE               ( 8UL << 8UL ) /* 8 regions, unified. */
+#define portMPU_ENABLE                            ( 0x01UL )
+#define portMPU_BACKGROUND_ENABLE                 ( 1UL << 2UL )
+#define portPRIVILEGED_EXECUTION_START_ADDRESS    ( 0UL )
+#define portMPU_REGION_VALID                      ( 0x10UL )
+#define portMPU_REGION_ENABLE                     ( 0x01UL )
+#define portPERIPHERALS_START_ADDRESS             0x40000000UL
+#define portPERIPHERALS_END_ADDRESS               0x5FFFFFFFUL
+
+/* Constants required to access and manipulate the SysTick. */
+#define portNVIC_SYSTICK_INT                      ( 0x00000002UL )
+#define portNVIC_SYSTICK_ENABLE                   ( 0x00000001UL )
+#define portNVIC_PENDSV_PRI                       ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI                      ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portNVIC_SVC_PRI                          ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                          ( 0x01000000 )
+#define portINITIAL_CONTROL_IF_UNPRIVILEGED       ( 0x03 )
+#define portINITIAL_CONTROL_IF_PRIVILEGED         ( 0x02 )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER           ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16           ( 0xE000E3F0 )
+#define portAIRCR_REG                             ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE                       ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE                       ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS                     ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK                   ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                        ( 8UL )
+
+/* Offsets in the stack to the parameters when inside the SVC handler. */
+#define portOFFSET_TO_PC                          ( 6 )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK                    ( ( StackType_t ) 0xfffffffeUL )
+/*-----------------------------------------------------------*/
+
+/*
+ * Configure a number of standard MPU regions that are used by all tasks.
+ */
+static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the smallest MPU region size that a given number of bytes will fit
+ * into.  The region size is returned as the value that should be programmed
+ * into the region attribute register for that region.
+ */
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Standard FreeRTOS exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+void xPortSysTickHandler( void )  __attribute__( ( optimize( "3" ) ) ) PRIVILEGED_FUNCTION;
+void vPortSVCHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/*
+ * Starts the scheduler by restoring the context of the first task to run.
+ */
+static void prvRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/*
+ * C portion of the SVC handler.  The SVC handler is split between an asm entry
+ * and a C wrapper for simplicity of coding and maintenance.
+ */
+static void prvSVCHandler( uint32_t * pulRegisters ) __attribute__( ( noinline ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable.  Note this is not saved as part of the task context as context
+ * switches can only occur when uxCriticalNesting is zero. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters,
+                                     BaseType_t xRunPrivileged )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    pxTopOfStack--;                                                      /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = 0;                                                   /* LR */
+    pxTopOfStack -= 5;                                                   /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters;                        /* R0 */
+    pxTopOfStack -= 9;                                                   /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    if( xRunPrivileged == pdTRUE )
+    {
+        *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
+    }
+    else
+    {
+        *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
+    }
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+    /* Assumes psp was in use. */
+    __asm volatile
+    (
+        #ifndef USE_PROCESS_STACK   /* Code should not be required if a main() is using the process stack. */
+            "	tst lr, #4						\n"
+            "	ite eq							\n"
+            "	mrseq r0, msp					\n"
+            "	mrsne r0, psp					\n"
+        #else
+            "	mrs r0, psp						\n"
+        #endif
+        "	b %0							\n"
+        ::"i" ( prvSVCHandler ) : "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSVCHandler( uint32_t * pulParam )
+{
+    uint8_t ucSVCNumber;
+    uint32_t ulPC;
+
+    #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+
+    /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR.  The first
+     * argument (r0) is pulParam[ 0 ]. */
+    ulPC = pulParam[ portOFFSET_TO_PC ];
+    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        case portSVC_START_SCHEDULER:
+            portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
+            prvRestoreContextOfFirstTask();
+            break;
+
+        case portSVC_YIELD:
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+            /* Barriers are normally not required
+             * but do ensure the code is completely
+             * within the specified behaviour for the
+             * architecture. */
+            __asm volatile ( "dsb" ::: "memory" );
+            __asm volatile ( "isb" );
+
+            break;
+
+
+            #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+                case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
+                                               * svc was raised from any of the
+                                               * system calls. */
+
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        __asm volatile
+                        (
+                            "	mrs r1, control		\n"/* Obtain current control value. */
+                            "	bic r1, #1			\n"/* Set privilege bit. */
+                            "	msr control, r1		\n"/* Write back new control value. */
+                            ::: "r1", "memory"
+                        );
+                    }
+
+                    break;
+            #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+                case portSVC_RAISE_PRIVILEGE:
+                    __asm volatile
+                    (
+                        "	mrs r1, control		\n"/* Obtain current control value. */
+                        "	bic r1, #1			\n"/* Set privilege bit. */
+                        "	msr control, r1		\n"/* Write back new control value. */
+                        ::: "r1", "memory"
+                    );
+                    break;
+                    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+
+                default: /* Unknown SVC call. */
+                    break;
+    }
+}
+/*-----------------------------------------------------------*/
+
+static void prvRestoreContextOfFirstTask( void )
+{
+    __asm volatile
+    (
+        "	ldr r0, =0xE000ED08				\n"/* Use the NVIC offset register to locate the stack. */
+        "	ldr r0, [r0]					\n"
+        "	ldr r0, [r0]					\n"
+        "	msr msp, r0						\n"/* Set the msp back to the start of the stack. */
+        "	ldr	r3, pxCurrentTCBConst2		\n"/* Restore the context. */
+        "	ldr r1, [r3]					\n"
+        "	ldr r0, [r1]					\n"/* The first item in the TCB is the task top of stack. */
+        "	add r1, r1, #4					\n"/* Move onto the second item in the TCB... */
+        "									\n"
+        "	dmb								\n"/* Complete outstanding transfers before disabling MPU. */
+        "	ldr r2, =0xe000ed94				\n"/* MPU_CTRL register. */
+        "	ldr r3, [r2]					\n"/* Read the value of MPU_CTRL. */
+        "	bic r3, #1						\n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
+        "	str r3, [r2]					\n"/* Disable MPU. */
+        "									\n"
+        "	ldr r2, =0xe000ed9c				\n"/* Region Base Address register. */
+        "	ldmia r1!, {r4-r11}				\n"/* Read 4 sets of MPU registers. */
+        "	stmia r2!, {r4-r11}				\n"/* Write 4 sets of MPU registers. */
+        "									\n"
+        "	ldr r2, =0xe000ed94				\n"/* MPU_CTRL register. */
+        "	ldr r3, [r2]					\n"/* Read the value of MPU_CTRL. */
+        "	orr r3, #1						\n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
+        "	str r3, [r2]					\n"/* Enable MPU. */
+        "	dsb								\n"/* Force memory writes before continuing. */
+        "									\n"
+        "	ldmia r0!, {r3, r4-r11}			\n"/* Pop the registers that are not automatically saved on exception entry. */
+        "	msr control, r3					\n"
+        "	msr psp, r0						\n"/* Restore the task stack pointer. */
+        "	mov r0, #0						\n"
+        "	msr	basepri, r0					\n"
+        "	ldr r14, =0xfffffffd			\n"/* Load exec return code. */
+        "	bx r14							\n"
+        "									\n"
+        "	.align 4						\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB	\n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See
+     * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
+
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+            volatile uint8_t ucMaxPriorityValue;
+
+            /* Determine the maximum priority from which ISR safe FreeRTOS API
+             * functions can be called.  ISR safe functions are those that end in
+             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions
+             * to ensure interrupt entry is as fast and simple as possible.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+            /* Determine the number of priority bits available.  First write to all
+             * possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+            /* Use the same mask on the maximum system call priority. */
+            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+            /* Calculate the maximum acceptable priority group value for the number
+             * of bits read back. */
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+            {
+                ulMaxPRIGROUPValue--;
+                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+            }
+
+            #ifdef __NVIC_PRIO_BITS
+                {
+                    /* Check the CMSIS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+                }
+            #endif
+
+            #ifdef configPRIO_BITS
+                {
+                    /* Check the FreeRTOS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+                }
+            #endif
+
+            /* Shift the priority group value back to its position within the AIRCR
+             * register. */
+            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* conifgASSERT_DEFINED */
+
+    /* Make PendSV and SysTick the same priority as the kernel, and the SVC
+     * handler higher priority so it can be used to exit a critical section (where
+     * lower priorities are masked). */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Configure the regions in the MPU that are common to all tasks. */
+    prvSetupMPU();
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Start the first task. */
+    __asm volatile (
+        " ldr r0, =0xE000ED08 	\n"/* Use the NVIC offset register to locate the stack. */
+        " ldr r0, [r0] 			\n"
+        " ldr r0, [r0] 			\n"
+        " msr msp, r0			\n"/* Set the msp back to the start of the stack. */
+        " cpsie i				\n"/* Globally enable interrupts. */
+        " cpsie f				\n"
+        " dsb					\n"
+        " isb					\n"
+        " svc %0				\n"/* System call to start first task. */
+        " nop					\n"
+        " .ltorg				\n"
+        ::"i" ( portSVC_START_SCHEDULER ) : "memory" );
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+
+    vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+
+    vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+    /* This is a naked function. */
+
+    __asm volatile
+    (
+        "	mrs r0, psp							\n"
+        "										\n"
+        "	ldr	r3, pxCurrentTCBConst			\n"/* Get the location of the current TCB. */
+        "	ldr	r2, [r3]						\n"
+        "										\n"
+        "	mrs r1, control						\n"
+        "	stmdb r0!, {r1, r4-r11}				\n"/* Save the remaining registers. */
+        "	str r0, [r2]						\n"/* Save the new top of stack into the first member of the TCB. */
+        "										\n"
+        "	stmdb sp!, {r3, r14}				\n"
+        "	mov r0, %0							\n"
+        "	msr basepri, r0						\n"
+        "	dsb									\n"
+        "	isb									\n"
+        "	bl vTaskSwitchContext				\n"
+        "	mov r0, #0							\n"
+        "	msr basepri, r0						\n"
+        "	ldmia sp!, {r3, r14}				\n"
+        "										\n"/* Restore the context. */
+        "	ldr r1, [r3]						\n"
+        "	ldr r0, [r1]						\n"/* The first item in the TCB is the task top of stack. */
+        "	add r1, r1, #4						\n"/* Move onto the second item in the TCB... */
+        "										\n"
+        "	dmb									\n"/* Complete outstanding transfers before disabling MPU. */
+        "	ldr r2, =0xe000ed94					\n"/* MPU_CTRL register. */
+        "	ldr r3, [r2]						\n"/* Read the value of MPU_CTRL. */
+        "	bic r3, #1							\n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
+        "	str r3, [r2]						\n"/* Disable MPU. */
+        "										\n"
+        "	ldr r2, =0xe000ed9c					\n"/* Region Base Address register. */
+        "	ldmia r1!, {r4-r11}					\n"/* Read 4 sets of MPU registers. */
+        "	stmia r2!, {r4-r11}					\n"/* Write 4 sets of MPU registers. */
+        "										\n"
+        "	ldr r2, =0xe000ed94					\n"/* MPU_CTRL register. */
+        "	ldr r3, [r2]						\n"/* Read the value of MPU_CTRL. */
+        "	orr r3, #1							\n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
+        "	str r3, [r2]						\n"/* Enable MPU. */
+        "	dsb									\n"/* Force memory writes before continuing. */
+        "										\n"
+        "	ldmia r0!, {r3, r4-r11}				\n"/* Pop the registers that are not automatically saved on exception entry. */
+        "	msr control, r3						\n"
+        "										\n"
+        "	msr psp, r0							\n"
+        "	bx r14								\n"
+        "										\n"
+        "	.align 4							\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB	\n"
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    uint32_t ulDummy;
+
+    ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
+{
+    /* Stop and clear the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupMPU( void )
+{
+    extern uint32_t __privileged_functions_start__[];
+    extern uint32_t __privileged_functions_end__[];
+    extern uint32_t __FLASH_segment_start__[];
+    extern uint32_t __FLASH_segment_end__[];
+    extern uint32_t __privileged_data_start__[];
+    extern uint32_t __privileged_data_end__[];
+
+    /* Check the expected MPU is present. */
+    if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+    {
+        /* First setup the unprivileged flash for unprivileged read only access. */
+        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
+                                          ( portMPU_REGION_VALID ) |
+                                          ( portUNPRIVILEGED_FLASH_REGION );
+
+        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
+                                       ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+                                       ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
+                                       ( portMPU_REGION_ENABLE );
+
+        /* Setup the privileged flash for privileged only access.  This is where
+         * the kernel code is * placed. */
+        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
+                                          ( portMPU_REGION_VALID ) |
+                                          ( portPRIVILEGED_FLASH_REGION );
+
+        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
+                                       ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+                                       ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
+                                       ( portMPU_REGION_ENABLE );
+
+        /* Setup the privileged data RAM region.  This is where the kernel data
+         * is placed. */
+        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+                                          ( portMPU_REGION_VALID ) |
+                                          ( portPRIVILEGED_RAM_REGION );
+
+        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                                       ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+                                       prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+                                       ( portMPU_REGION_ENABLE );
+
+        /* By default allow everything to access the general peripherals.  The
+         * system peripherals and registers are protected. */
+        portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
+                                          ( portMPU_REGION_VALID ) |
+                                          ( portGENERAL_PERIPHERALS_REGION );
+
+        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
+                                       ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
+                                       ( portMPU_REGION_ENABLE );
+
+        /* Enable the memory fault exception. */
+        portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
+
+        /* Enable the MPU with the background region configured. */
+        portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+    }
+}
+/*-----------------------------------------------------------*/
+
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
+{
+    uint32_t ulRegionSize, ulReturnValue = 4;
+
+    /* 32 is the smallest region size, 31 is the largest valid value for
+     * ulReturnValue. */
+    for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
+    {
+        if( ulActualSizeInBytes <= ulRegionSize )
+        {
+            break;
+        }
+        else
+        {
+            ulReturnValue++;
+        }
+    }
+
+    /* Shift the code by one before returning so it can be written directly
+     * into the the correct bit position of the attribute register. */
+    return( ulReturnValue << 1UL );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control							\n"/* r0 = CONTROL. */
+        "	tst r0, #1								\n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "	ite ne									\n"
+        "	movne r0, #0							\n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "	moveq r0, #1							\n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "	bx lr									\n"/* Return. */
+        "											\n"
+        "	.align 4								\n"
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control							\n"/* r0 = CONTROL. */
+        "	orr r0, #1								\n"/* r0 = r0 | 1. */
+        "	msr control, r0							\n"/* CONTROL = r0. */
+        "	bx lr									\n"/* Return to the caller. */
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                const struct xMEMORY_REGION * const xRegions,
+                                StackType_t * pxBottomOfStack,
+                                uint32_t ulStackDepth )
+{
+    extern uint32_t __SRAM_segment_start__[];
+    extern uint32_t __SRAM_segment_end__[];
+    extern uint32_t __privileged_data_start__[];
+    extern uint32_t __privileged_data_end__[];
+    int32_t lIndex;
+    uint32_t ul;
+
+    if( xRegions == NULL )
+    {
+        /* No MPU regions are specified so allow access to all RAM. */
+        xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+            ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
+            ( portMPU_REGION_VALID ) |
+            ( portSTACK_REGION );
+
+        xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+            ( portMPU_REGION_READ_WRITE ) |
+            ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+            ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
+            ( portMPU_REGION_ENABLE );
+
+        /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
+         * just removed the privileged only parameters. */
+        xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
+            ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+            ( portMPU_REGION_VALID ) |
+            ( portSTACK_REGION + 1 );
+
+        xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
+            ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+            ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+            prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+            ( portMPU_REGION_ENABLE );
+
+        /* Invalidate all other regions. */
+        for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+        {
+            xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+            xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+        }
+    }
+    else
+    {
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid.  At all other
+         * times the stack parameters will not be valid and it is assumed that the
+         * stack region has already been configured. */
+        if( ulStackDepth > 0 )
+        {
+            /* Define the region that allows access to the stack. */
+            xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+                ( ( uint32_t ) pxBottomOfStack ) |
+                ( portMPU_REGION_VALID ) |
+                ( portSTACK_REGION ); /* Region number. */
+
+            xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+                ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
+                ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+                ( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
+                ( portMPU_REGION_ENABLE );
+        }
+
+        lIndex = 0;
+
+        for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+        {
+            if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
+            {
+                /* Translate the generic region definition contained in
+                 * xRegions into the CM3 specific MPU settings that are then
+                 * stored in xMPUSettings. */
+                xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
+                    ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
+                    ( portMPU_REGION_VALID ) |
+                    ( portSTACK_REGION + ul ); /* Region number. */
+
+                xMPUSettings->xRegion[ ul ].ulRegionAttribute =
+                    ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
+                    ( xRegions[ lIndex ].ulParameters ) |
+                    ( portMPU_REGION_ENABLE );
+            }
+            else
+            {
+                /* Invalidate the region. */
+                xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+                xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+            }
+
+            lIndex++;
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+    void vPortValidateInterruptPriority( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        uint8_t ucCurrentPriority;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that	use the FreeRTOS API must not be left at their
+             * default priority of	zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and	therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
+
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredicable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
new file mode 100644
index 0000000..865a9cb
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
@@ -0,0 +1,308 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* MPU specific constants. */
+    #define portUSING_MPU_WRAPPERS                                   1
+    #define portPRIVILEGE_BIT                                        ( 0x80000000UL )
+
+    #define portMPU_REGION_READ_WRITE                                ( 0x03UL << 24UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY                      ( 0x05UL << 24UL )
+    #define portMPU_REGION_READ_ONLY                                 ( 0x06UL << 24UL )
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE                     ( 0x01UL << 24UL )
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY    ( 0x02UL << 24UL )
+    #define portMPU_REGION_CACHEABLE_BUFFERABLE                      ( 0x07UL << 16UL )
+    #define portMPU_REGION_EXECUTE_NEVER                             ( 0x01UL << 28UL )
+
+    #define portUNPRIVILEGED_FLASH_REGION                            ( 0UL )
+    #define portPRIVILEGED_FLASH_REGION                              ( 1UL )
+    #define portPRIVILEGED_RAM_REGION                                ( 2UL )
+    #define portGENERAL_PERIPHERALS_REGION                           ( 3UL )
+    #define portSTACK_REGION                                         ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                            ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                             ( 7UL )
+    #define portNUM_CONFIGURABLE_REGIONS                             ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                                    ( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
+
+    #define portSWITCH_TO_USER_MODE()    __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
+
+    typedef struct MPU_REGION_REGISTERS
+    {
+        uint32_t ulRegionBaseAddress;
+        uint32_t ulRegionAttribute;
+    } xMPU_REGION_REGISTERS;
+
+/* Plus 1 to create space for the stack region. */
+    typedef struct MPU_SETTINGS
+    {
+        xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
+    } xMPU_SETTINGS;
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
+    #define portDONT_DISCARD      __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/* SVC numbers for various services. */
+    #define portSVC_START_SCHEDULER    0
+    #define portSVC_YIELD              1
+    #define portSVC_RAISE_PRIVILEGE    2
+
+/* Scheduler utilities. */
+
+    #define portYIELD()    __asm volatile ( "	SVC	%0	\n"::"i" ( portSVC_YIELD ) : "memory" )
+    #define portYIELD_WITHIN_API()                      \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+                                                        \
+        /* Barriers are normally not required but do ensure the code is completely \
+         * within the specified behaviour for the architecture. */ \
+        __asm volatile ( "dsb" ::: "memory" );                     \
+        __asm volatile ( "isb" );                                  \
+    }
+
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
+    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
+    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #endif
+
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Generic helper function. */
+        __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+        {
+            uint8_t ucReturn;
+
+            __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+
+            return ucReturn;
+        }
+
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
+
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
+
+/* portNOP() is not required by this port. */
+    #define portNOP()
+
+    #define portINLINE              __inline
+
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
+    #endif
+/*-----------------------------------------------------------*/
+
+    extern BaseType_t xIsPrivileged( void );
+    extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+    #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ */
+    #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+    #define portRESET_PRIVILEGE()    vResetPrivilege()
+/*-----------------------------------------------------------*/
+
+    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        BaseType_t xReturn;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+        if( ulCurrentInterrupt == 0 )
+        {
+            xReturn = pdFALSE;
+        }
+        else
+        {
+            xReturn = pdTRUE;
+        }
+
+        return xReturn;
+    }
+
+/*-----------------------------------------------------------*/
+
+    portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+    {
+        uint32_t ulNewBASEPRI;
+
+        __asm volatile
+        (
+            "	mov %0, %1												\n"\
+            "	msr basepri, %0											\n"\
+            "	isb														\n"\
+            "	dsb														\n"\
+            : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+        );
+    }
+
+/*-----------------------------------------------------------*/
+
+    portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+    {
+        uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+        __asm volatile
+        (
+            "	mrs %0, basepri											\n"\
+            "	mov %1, %2												\n"\
+            "	msr basepri, %1											\n"\
+            "	isb														\n"\
+            "	dsb														\n"\
+            : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+        );
+
+        /* This return will not be reached but is necessary to prevent compiler
+         * warnings. */
+        return ulOriginalBASEPRI;
+    }
+/*-----------------------------------------------------------*/
+
+    portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+    {
+        __asm volatile
+        (
+            "	msr basepri, %0	"::"r" ( ulNewMaskValue ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+
+    #ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
+        #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
+        #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY    0
+    #endif
+/*-----------------------------------------------------------*/
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
new file mode 100644
index 0000000..9f7fb08
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
@@ -0,0 +1,783 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM4F port.
+*----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __VFP_FP__
+    #error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )
+
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
+ * r0p1 port. */
+#define portCPUID                             ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID                 ( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID                 ( 0x410FC270UL )
+
+#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
+#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                    ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK                   ( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR                             ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS              ( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                      ( 0x01000000 )
+#define portINITIAL_EXC_RETURN                ( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#define portMISSED_COUNTS_FACTOR              ( 45UL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__( ( naked ) );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__( ( naked ) );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__( ( naked ) );
+
+/*
+ * Function to enable the VFP.
+ */
+static void vPortEnableVFP( void ) __attribute__( ( naked ) );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+
+    /* Offset added to account for the way the MCU uses the stack on entry/exit
+     * of interrupts, and to ensure alignment. */
+    pxTopOfStack--;
+
+    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;             /* LR */
+
+    /* Save code space by skipping register initialisation. */
+    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+    /* A save method is being used that requires each task to maintain its
+     * own exec return value. */
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+    pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    volatile uint32_t ulDummy = 0;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( uxCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being defined
+         * but never called.  ulDummy is used purely to quieten other warnings
+         * about code appearing after this function is called - making ulDummy
+         * volatile makes the compiler think the function could return and
+         * therefore not output an 'unreachable code' warning for code that appears
+         * after it. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+    __asm volatile (
+        "	ldr	r3, pxCurrentTCBConst2		\n"/* Restore the context. */
+        "	ldr r1, [r3]					\n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+        "	ldr r0, [r1]					\n"/* The first item in pxCurrentTCB is the task top of stack. */
+        "	ldmia r0!, {r4-r11, r14}		\n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+        "	msr psp, r0						\n"/* Restore the task stack pointer. */
+        "	isb								\n"
+        "	mov r0, #0 						\n"
+        "	msr	basepri, r0					\n"
+        "	bx r14							\n"
+        "									\n"
+        "	.align 4						\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+        );
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+    /* Start the first task.  This also clears the bit that indicates the FPU is
+     * in use in case the FPU was used before the scheduler was started - which
+     * would otherwise result in the unnecessary leaving of space in the SVC stack
+     * for lazy saving of FPU registers. */
+    __asm volatile (
+        " ldr r0, =0xE000ED08 	\n"/* Use the NVIC offset register to locate the stack. */
+        " ldr r0, [r0] 			\n"
+        " ldr r0, [r0] 			\n"
+        " msr msp, r0			\n"/* Set the msp back to the start of the stack. */
+        " mov r0, #0			\n"/* Clear the bit that indicates the FPU is in use, see comment above. */
+        " msr control, r0		\n"
+        " cpsie i				\n"/* Globally enable interrupts. */
+        " cpsie f				\n"
+        " dsb					\n"
+        " isb					\n"
+        " svc 0					\n"/* System call to start first task. */
+        " nop					\n"
+        " .ltorg				\n"
+        );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+    /* This port can be used on all revisions of the Cortex-M7 core other than
+     * the r0p1 parts.  r0p1 parts should use the port from the
+     * /source/portable/GCC/ARM_CM7/r0p1 directory. */
+    configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+    configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+            volatile uint8_t ucMaxPriorityValue;
+
+            /* Determine the maximum priority from which ISR safe FreeRTOS API
+             * functions can be called.  ISR safe functions are those that end in
+             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+             * ensure interrupt entry is as fast and simple as possible.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+            /* Determine the number of priority bits available.  First write to all
+             * possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+            /* Use the same mask on the maximum system call priority. */
+            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+            /* Calculate the maximum acceptable priority group value for the number
+             * of bits read back. */
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+            {
+                ulMaxPRIGROUPValue--;
+                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+            }
+
+            #ifdef __NVIC_PRIO_BITS
+                {
+                    /* Check the CMSIS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+                }
+            #endif
+
+            #ifdef configPRIO_BITS
+                {
+                    /* Check the FreeRTOS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+                }
+            #endif
+
+            /* Shift the priority group value back to its position within the AIRCR
+             * register. */
+            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* conifgASSERT_DEFINED */
+
+    /* Make PendSV and SysTick the lowest priority interrupts. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Ensure the VFP is enabled - it should be anyway. */
+    vPortEnableVFP();
+
+    /* Lazy save always. */
+    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+    /* Start the first task. */
+    prvPortStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing!  Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS.  Call
+     * vTaskSwitchContext() so link time optimisation does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
+    if( uxCriticalNesting == 1 )
+    {
+        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+    /* This is a naked function. */
+
+    __asm volatile
+    (
+        "	mrs r0, psp							\n"
+        "	isb									\n"
+        "										\n"
+        "	ldr	r3, pxCurrentTCBConst			\n"/* Get the location of the current TCB. */
+        "	ldr	r2, [r3]						\n"
+        "										\n"
+        "	tst r14, #0x10						\n"/* Is the task using the FPU context?  If so, push high vfp registers. */
+        "	it eq								\n"
+        "	vstmdbeq r0!, {s16-s31}				\n"
+        "										\n"
+        "	stmdb r0!, {r4-r11, r14}			\n"/* Save the core registers. */
+        "	str r0, [r2]						\n"/* Save the new top of stack into the first member of the TCB. */
+        "										\n"
+        "	stmdb sp!, {r0, r3}					\n"
+        "	mov r0, %0 							\n"
+        "	msr basepri, r0						\n"
+        "	dsb									\n"
+        "	isb									\n"
+        "	bl vTaskSwitchContext				\n"
+        "	mov r0, #0							\n"
+        "	msr basepri, r0						\n"
+        "	ldmia sp!, {r0, r3}					\n"
+        "										\n"
+        "	ldr r1, [r3]						\n"/* The first item in pxCurrentTCB is the task top of stack. */
+        "	ldr r0, [r1]						\n"
+        "										\n"
+        "	ldmia r0!, {r4-r11, r14}			\n"/* Pop the core registers. */
+        "										\n"
+        "	tst r14, #0x10						\n"/* Is the task using the FPU context?  If so, pop the high vfp registers too. */
+        "	it eq								\n"
+        "	vldmiaeq r0!, {s16-s31}				\n"
+        "										\n"
+        "	msr psp, r0							\n"
+        "	isb									\n"
+        "										\n"
+        #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
+            #if WORKAROUND_PMU_CM001 == 1
+                "			push { r14 }				\n"
+                "			pop { pc }					\n"
+            #endif
+        #endif
+        "										\n"
+        "	bx r14								\n"
+        "										\n"
+        "	.align 4							\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB	\n"
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+     * executes all interrupts must be unmasked.  There is therefore no need to
+     * save and then restore the interrupt mask value as its value is already
+     * known. */
+    portDISABLE_INTERRUPTS();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* A context switch is required.  Context switching is performed in
+             * the PendSV interrupt.  Pend the PendSV interrupt. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+         * is accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods.  -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm volatile ( "cpsid i" ::: "memory" );
+        __asm volatile ( "dsb" );
+        __asm volatile ( "isb" );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above the cpsid instruction()
+             * above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again.  However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm volatile ( "dsb" ::: "memory" );
+                __asm volatile ( "wfi" );
+                __asm volatile ( "isb" );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately.  see comments above
+             * __disable_interrupt() call above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __asm volatile ( "cpsid i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is yet
+             * to count to zero (in which case an interrupt other than the SysTick
+             * must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+    }
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and clear the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+    __asm volatile
+    (
+        "	ldr.w r0, =0xE000ED88		\n"/* The FPU enable bits are in the CPACR. */
+        "	ldr r1, [r0]				\n"
+        "								\n"
+        "	orr r1, r1, #( 0xf << 20 )	\n"/* Enable CP10 and CP11 coprocessors, then save back. */
+        "	str r1, [r0]				\n"
+        "	bx r14						\n"
+        "	.ltorg						\n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+    void vPortValidateInterruptPriority( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        uint8_t ucCurrentPriority;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that	use the FreeRTOS API must not be left at their
+             * default priority of	zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and	therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
+
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredictable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
+
+#endif /* configASSERT_DEFINED */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..46e4677
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
@@ -0,0 +1,244 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
+    #define portDONT_DISCARD      __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+    #define portYIELD()                                 \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+                                                        \
+        /* Barriers are normally not required but do ensure the code is completely \
+         * within the specified behaviour for the architecture. */ \
+        __asm volatile ( "dsb" ::: "memory" );                     \
+        __asm volatile ( "isb" );                                  \
+    }
+
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired != pdFALSE ) portYIELD()
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
+    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
+    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #endif
+
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Generic helper function. */
+        __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+        {
+            uint8_t ucReturn;
+
+            __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+
+            return ucReturn;
+        }
+
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
+
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
+
+/* portNOP() is not required by this port. */
+    #define portNOP()
+
+    #define portINLINE              __inline
+
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
+    #endif
+
+    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        BaseType_t xReturn;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+        if( ulCurrentInterrupt == 0 )
+        {
+            xReturn = pdFALSE;
+        }
+        else
+        {
+            xReturn = pdTRUE;
+        }
+
+        return xReturn;
+    }
+
+/*-----------------------------------------------------------*/
+
+    portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+    {
+        uint32_t ulNewBASEPRI;
+
+        __asm volatile
+        (
+            "	mov %0, %1												\n"\
+            "	msr basepri, %0											\n"\
+            "	isb														\n"\
+            "	dsb														\n"\
+            : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+        );
+    }
+
+/*-----------------------------------------------------------*/
+
+    portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+    {
+        uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+        __asm volatile
+        (
+            "	mrs %0, basepri											\n"\
+            "	mov %1, %2												\n"\
+            "	msr basepri, %1											\n"\
+            "	isb														\n"\
+            "	dsb														\n"\
+            : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+        );
+
+        /* This return will not be reached but is necessary to prevent compiler
+         * warnings. */
+        return ulOriginalBASEPRI;
+    }
+/*-----------------------------------------------------------*/
+
+    portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+    {
+        __asm volatile
+        (
+            "	msr basepri, %0	"::"r" ( ulNewMaskValue ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c
new file mode 100644
index 0000000..8ca0ab5
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c
@@ -0,0 +1,974 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM4 MPU port.
+*----------------------------------------------------------*/
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __VFP_FP__
+    #error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ    configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK      ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+    #define portNVIC_SYSTICK_CLK    ( 0 )
+#endif
+
+/* Constants required to access and manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG                 ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG        ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                        ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SHPR2_REG                        ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
+#define portNVIC_SYS_CTRL_STATE_REG               ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
+#define portNVIC_MEM_FAULT_ENABLE                 ( 1UL << 16UL )
+
+/* Constants required to access and manipulate the MPU. */
+#define portMPU_TYPE_REG                          ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_REGION_BASE_ADDRESS_REG           ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
+#define portMPU_REGION_ATTRIBUTE_REG              ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
+#define portMPU_CTRL_REG                          ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portEXPECTED_MPU_TYPE_VALUE               ( portTOTAL_NUM_REGIONS << 8UL )
+#define portMPU_ENABLE                            ( 0x01UL )
+#define portMPU_BACKGROUND_ENABLE                 ( 1UL << 2UL )
+#define portPRIVILEGED_EXECUTION_START_ADDRESS    ( 0UL )
+#define portMPU_REGION_VALID                      ( 0x10UL )
+#define portMPU_REGION_ENABLE                     ( 0x01UL )
+#define portPERIPHERALS_START_ADDRESS             0x40000000UL
+#define portPERIPHERALS_END_ADDRESS               0x5FFFFFFFUL
+
+/* Constants required to access and manipulate the SysTick. */
+#define portNVIC_SYSTICK_INT                      ( 0x00000002UL )
+#define portNVIC_SYSTICK_ENABLE                   ( 0x00000001UL )
+#define portNVIC_PENDSV_PRI                       ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI                      ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portNVIC_SVC_PRI                          ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR                                 ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS                  ( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                          ( 0x01000000UL )
+#define portINITIAL_EXC_RETURN                    ( 0xfffffffdUL )
+#define portINITIAL_CONTROL_IF_UNPRIVILEGED       ( 0x03 )
+#define portINITIAL_CONTROL_IF_PRIVILEGED         ( 0x02 )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER           ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16           ( 0xE000E3F0 )
+#define portAIRCR_REG                             ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE                       ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE                       ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS                     ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK                   ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                        ( 8UL )
+
+/* Offsets in the stack to the parameters when inside the SVC handler. */
+#define portOFFSET_TO_PC                          ( 6 )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK                    ( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Configure a number of standard MPU regions that are used by all tasks.
+ */
+static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the smallest MPU region size that a given number of bytes will fit
+ * into.  The region size is returned as the value that should be programmed
+ * into the region attribute register for that region.
+ */
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Standard FreeRTOS exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
+void vPortSVCHandler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/*
+ * Starts the scheduler by restoring the context of the first task to run.
+ */
+static void prvRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/*
+ * C portion of the SVC handler.  The SVC handler is split between an asm entry
+ * and a C wrapper for simplicity of coding and maintenance.
+ */
+static void prvSVCHandler( uint32_t * pulRegisters ) __attribute__( ( noinline ) ) PRIVILEGED_FUNCTION;
+
+/*
+ * Function to enable the VFP.
+ */
+static void vPortEnableVFP( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable.  Note this is not saved as part of the task context as context
+ * switches can only occur when uxCriticalNesting is zero. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters,
+                                     BaseType_t xRunPrivileged )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    pxTopOfStack--;                                                      /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = 0;                                                   /* LR */
+    pxTopOfStack -= 5;                                                   /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters;                        /* R0 */
+
+    /* A save method is being used that requires each task to maintain its
+     * own exec return value. */
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+    pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    if( xRunPrivileged == pdTRUE )
+    {
+        *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
+    }
+    else
+    {
+        *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
+    }
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+    /* Assumes psp was in use. */
+    __asm volatile
+    (
+        #ifndef USE_PROCESS_STACK   /* Code should not be required if a main() is using the process stack. */
+            "	tst lr, #4						\n"
+            "	ite eq							\n"
+            "	mrseq r0, msp					\n"
+            "	mrsne r0, psp					\n"
+        #else
+            "	mrs r0, psp						\n"
+        #endif
+        "	b %0							\n"
+        ::"i" ( prvSVCHandler ) : "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSVCHandler( uint32_t * pulParam )
+{
+    uint8_t ucSVCNumber;
+    uint32_t ulPC;
+
+    #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* #if defined( __ARMCC_VERSION ) */
+    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+
+    /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR.  The first
+     * argument (r0) is pulParam[ 0 ]. */
+    ulPC = pulParam[ portOFFSET_TO_PC ];
+    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        case portSVC_START_SCHEDULER:
+            portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
+            prvRestoreContextOfFirstTask();
+            break;
+
+        case portSVC_YIELD:
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+            /* Barriers are normally not required
+             * but do ensure the code is completely
+             * within the specified behaviour for the
+             * architecture. */
+            __asm volatile ( "dsb" ::: "memory" );
+            __asm volatile ( "isb" );
+
+            break;
+
+            #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+                case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
+                                               * svc was raised from any of the
+                                               * system calls. */
+
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        __asm volatile
+                        (
+                            "	mrs r1, control		\n"/* Obtain current control value. */
+                            "	bic r1, #1			\n"/* Set privilege bit. */
+                            "	msr control, r1		\n"/* Write back new control value. */
+                            ::: "r1", "memory"
+                        );
+                    }
+
+                    break;
+            #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+                case portSVC_RAISE_PRIVILEGE:
+                    __asm volatile
+                    (
+                        "	mrs r1, control		\n"/* Obtain current control value. */
+                        "	bic r1, #1			\n"/* Set privilege bit. */
+                        "	msr control, r1		\n"/* Write back new control value. */
+                        ::: "r1", "memory"
+                    );
+                    break;
+                    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+
+                default: /* Unknown SVC call. */
+                    break;
+    }
+}
+/*-----------------------------------------------------------*/
+
+static void prvRestoreContextOfFirstTask( void )
+{
+    __asm volatile
+    (
+        "	ldr r0, =0xE000ED08				\n"/* Use the NVIC offset register to locate the stack. */
+        "	ldr r0, [r0]					\n"
+        "	ldr r0, [r0]					\n"
+        "	msr msp, r0						\n"/* Set the msp back to the start of the stack. */
+        "	ldr	r3, pxCurrentTCBConst2		\n"/* Restore the context. */
+        "	ldr r1, [r3]					\n"
+        "	ldr r0, [r1]					\n"/* The first item in the TCB is the task top of stack. */
+        "	add r1, r1, #4					\n"/* Move onto the second item in the TCB... */
+        "									\n"
+        "	dmb								\n"/* Complete outstanding transfers before disabling MPU. */
+        "	ldr r2, =0xe000ed94				\n"/* MPU_CTRL register. */
+        "	ldr r3, [r2]					\n"/* Read the value of MPU_CTRL. */
+        "	bic r3, #1						\n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
+        "	str r3, [r2]					\n"/* Disable MPU. */
+        "									\n"
+        "	ldr r2, =0xe000ed9c				\n"/* Region Base Address register. */
+        "	ldmia r1!, {r4-r11}				\n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+        "	stmia r2, {r4-r11}				\n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+        "									\n"
+        #if ( portTOTAL_NUM_REGIONS == 16 )
+            "	ldmia r1!, {r4-r11}				\n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
+            "	stmia r2, {r4-r11}				\n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
+            "	ldmia r1!, {r4-r11}				\n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
+            "	stmia r2, {r4-r11}				\n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
+        #endif /* portTOTAL_NUM_REGIONS == 16. */
+        "									\n"
+        "	ldr r2, =0xe000ed94				\n"/* MPU_CTRL register. */
+        "	ldr r3, [r2]					\n"/* Read the value of MPU_CTRL. */
+        "	orr r3, #1						\n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
+        "	str r3, [r2]					\n"/* Enable MPU. */
+        "	dsb								\n"/* Force memory writes before continuing. */
+        "									\n"
+        "	ldmia r0!, {r3-r11, r14}		\n"/* Pop the registers that are not automatically saved on exception entry. */
+        "	msr control, r3					\n"
+        "	msr psp, r0						\n"/* Restore the task stack pointer. */
+        "	mov r0, #0						\n"
+        "	msr	basepri, r0					\n"
+        "	bx r14							\n"
+        "									\n"
+        "	.align 4						\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB	\n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See
+     * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
+
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+            volatile uint8_t ucMaxPriorityValue;
+
+            /* Determine the maximum priority from which ISR safe FreeRTOS API
+             * functions can be called.  ISR safe functions are those that end in
+             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+             * ensure interrupt entry is as fast and simple as possible.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+            /* Determine the number of priority bits available.  First write to all
+             * possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+            /* Use the same mask on the maximum system call priority. */
+            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+            /* Calculate the maximum acceptable priority group value for the number
+             * of bits read back. */
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+            {
+                ulMaxPRIGROUPValue--;
+                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+            }
+
+            #ifdef __NVIC_PRIO_BITS
+                {
+                    /* Check the CMSIS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+                }
+            #endif
+
+            #ifdef configPRIO_BITS
+                {
+                    /* Check the FreeRTOS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+                }
+            #endif
+
+            /* Shift the priority group value back to its position within the AIRCR
+             * register. */
+            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* conifgASSERT_DEFINED */
+
+    /* Make PendSV and SysTick the same priority as the kernel, and the SVC
+     * handler higher priority so it can be used to exit a critical section (where
+     * lower priorities are masked). */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Configure the regions in the MPU that are common to all tasks. */
+    prvSetupMPU();
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Ensure the VFP is enabled - it should be anyway. */
+    vPortEnableVFP();
+
+    /* Lazy save always. */
+    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+    /* Start the first task.  This also clears the bit that indicates the FPU is
+     * in use in case the FPU was used before the scheduler was started - which
+     * would otherwise result in the unnecessary leaving of space in the SVC stack
+     * for lazy saving of FPU registers. */
+    __asm volatile (
+        " ldr r0, =0xE000ED08 	\n"/* Use the NVIC offset register to locate the stack. */
+        " ldr r0, [r0] 			\n"
+        " ldr r0, [r0] 			\n"
+        " msr msp, r0			\n"/* Set the msp back to the start of the stack. */
+        " mov r0, #0			\n"/* Clear the bit that indicates the FPU is in use, see comment above. */
+        " msr control, r0		\n"
+        " cpsie i				\n"/* Globally enable interrupts. */
+        " cpsie f				\n"
+        " dsb					\n"
+        " isb					\n"
+        " svc %0				\n"/* System call to start first task. */
+        " nop					\n"
+        " .ltorg				\n"
+        ::"i" ( portSVC_START_SCHEDULER ) : "memory" );
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+
+    vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+
+    vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+    /* This is a naked function. */
+
+    __asm volatile
+    (
+        "	mrs r0, psp							\n"
+        "	isb									\n"
+        "										\n"
+        "	ldr	r3, pxCurrentTCBConst			\n"/* Get the location of the current TCB. */
+        "	ldr	r2, [r3]						\n"
+        "										\n"
+        "	tst r14, #0x10						\n"/* Is the task using the FPU context?  If so, push high vfp registers. */
+        "	it eq								\n"
+        "	vstmdbeq r0!, {s16-s31}				\n"
+        "										\n"
+        "	mrs r1, control						\n"
+        "	stmdb r0!, {r1, r4-r11, r14}		\n"/* Save the remaining registers. */
+        "	str r0, [r2]						\n"/* Save the new top of stack into the first member of the TCB. */
+        "										\n"
+        "	stmdb sp!, {r0, r3}					\n"
+        "	mov r0, %0							\n"
+        "	msr basepri, r0						\n"
+        "	dsb									\n"
+        "	isb									\n"
+        "	bl vTaskSwitchContext				\n"
+        "	mov r0, #0							\n"
+        "	msr basepri, r0						\n"
+        "	ldmia sp!, {r0, r3}					\n"
+        "										\n"/* Restore the context. */
+        "	ldr r1, [r3]						\n"
+        "	ldr r0, [r1]						\n"/* The first item in the TCB is the task top of stack. */
+        "	add r1, r1, #4						\n"/* Move onto the second item in the TCB... */
+        "										\n"
+        "	dmb									\n"/* Complete outstanding transfers before disabling MPU. */
+        "	ldr r2, =0xe000ed94					\n"/* MPU_CTRL register. */
+        "	ldr r3, [r2]						\n"/* Read the value of MPU_CTRL. */
+        "	bic r3, #1							\n"/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
+        "	str r3, [r2]						\n"/* Disable MPU. */
+        "										\n"
+        "	ldr r2, =0xe000ed9c					\n"/* Region Base Address register. */
+        "	ldmia r1!, {r4-r11}					\n"/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+        "	stmia r2, {r4-r11}					\n"/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+        "										\n"
+        #if ( portTOTAL_NUM_REGIONS == 16 )
+            "	ldmia r1!, {r4-r11}					\n"/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
+            "	stmia r2, {r4-r11}					\n"/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
+            "	ldmia r1!, {r4-r11}					\n"/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
+            "	stmia r2, {r4-r11}					\n"/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
+        #endif /* portTOTAL_NUM_REGIONS == 16. */
+        "										\n"
+        "	ldr r2, =0xe000ed94					\n"/* MPU_CTRL register. */
+        "	ldr r3, [r2]						\n"/* Read the value of MPU_CTRL. */
+        "	orr r3, #1							\n"/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
+        "	str r3, [r2]						\n"/* Enable MPU. */
+        "	dsb									\n"/* Force memory writes before continuing. */
+        "										\n"
+        "	ldmia r0!, {r3-r11, r14}			\n"/* Pop the registers that are not automatically saved on exception entry. */
+        "	msr control, r3						\n"
+        "										\n"
+        "	tst r14, #0x10						\n"/* Is the task using the FPU context?  If so, pop the high vfp registers too. */
+        "	it eq								\n"
+        "	vldmiaeq r0!, {s16-s31}				\n"
+        "										\n"
+        "	msr psp, r0							\n"
+        "	bx r14								\n"
+        "										\n"
+        "	.align 4							\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB	\n"
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    uint32_t ulDummy;
+
+    ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
+{
+    /* Stop and clear the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
+}
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+    __asm volatile
+    (
+        "	ldr.w r0, =0xE000ED88		\n"/* The FPU enable bits are in the CPACR. */
+        "	ldr r1, [r0]				\n"
+        "								\n"
+        "	orr r1, r1, #( 0xf << 20 )	\n"/* Enable CP10 and CP11 coprocessors, then save back. */
+        "	str r1, [r0]				\n"
+        "	bx r14						\n"
+        "	.ltorg						\n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupMPU( void )
+{
+    #if defined( __ARMCC_VERSION )
+
+        /* Declaration when these variable are defined in code instead of being
+         * exported from linker scripts. */
+        extern uint32_t * __privileged_functions_start__;
+        extern uint32_t * __privileged_functions_end__;
+        extern uint32_t * __FLASH_segment_start__;
+        extern uint32_t * __FLASH_segment_end__;
+        extern uint32_t * __privileged_data_start__;
+        extern uint32_t * __privileged_data_end__;
+    #else
+        /* Declaration when these variable are exported from linker scripts. */
+        extern uint32_t __privileged_functions_start__[];
+        extern uint32_t __privileged_functions_end__[];
+        extern uint32_t __FLASH_segment_start__[];
+        extern uint32_t __FLASH_segment_end__[];
+        extern uint32_t __privileged_data_start__[];
+        extern uint32_t __privileged_data_end__[];
+    #endif /* if defined( __ARMCC_VERSION ) */
+
+    /* The only permitted number of regions are 8 or 16. */
+    configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
+
+    /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
+    configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+
+    /* Check the expected MPU is present. */
+    if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+    {
+        /* First setup the unprivileged flash for unprivileged read only access. */
+        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
+                                          ( portMPU_REGION_VALID ) |
+                                          ( portUNPRIVILEGED_FLASH_REGION );
+
+        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
+                                       ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+                                       ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
+                                       ( portMPU_REGION_ENABLE );
+
+        /* Setup the privileged flash for privileged only access.  This is where
+         * the kernel code is placed. */
+        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
+                                          ( portMPU_REGION_VALID ) |
+                                          ( portPRIVILEGED_FLASH_REGION );
+
+        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
+                                       ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+                                       ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
+                                       ( portMPU_REGION_ENABLE );
+
+        /* Setup the privileged data RAM region.  This is where the kernel data
+         * is placed. */
+        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+                                          ( portMPU_REGION_VALID ) |
+                                          ( portPRIVILEGED_RAM_REGION );
+
+        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                                       ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+                                       prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+                                       ( portMPU_REGION_ENABLE );
+
+        /* By default allow everything to access the general peripherals.  The
+         * system peripherals and registers are protected. */
+        portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
+                                          ( portMPU_REGION_VALID ) |
+                                          ( portGENERAL_PERIPHERALS_REGION );
+
+        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
+                                       ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
+                                       ( portMPU_REGION_ENABLE );
+
+        /* Enable the memory fault exception. */
+        portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
+
+        /* Enable the MPU with the background region configured. */
+        portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+    }
+}
+/*-----------------------------------------------------------*/
+
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
+{
+    uint32_t ulRegionSize, ulReturnValue = 4;
+
+    /* 32 is the smallest region size, 31 is the largest valid value for
+     * ulReturnValue. */
+    for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
+    {
+        if( ulActualSizeInBytes <= ulRegionSize )
+        {
+            break;
+        }
+        else
+        {
+            ulReturnValue++;
+        }
+    }
+
+    /* Shift the code by one before returning so it can be written directly
+     * into the the correct bit position of the attribute register. */
+    return( ulReturnValue << 1UL );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control							\n"/* r0 = CONTROL. */
+        "	tst r0, #1								\n"/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+        "	ite ne									\n"
+        "	movne r0, #0							\n"/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+        "	moveq r0, #1							\n"/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+        "	bx lr									\n"/* Return. */
+        "											\n"
+        "	.align 4								\n"
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vResetPrivilege( void ) /* __attribute__ (( naked )) */
+{
+    __asm volatile
+    (
+        "	mrs r0, control							\n"/* r0 = CONTROL. */
+        "	orr r0, #1								\n"/* r0 = r0 | 1. */
+        "	msr control, r0							\n"/* CONTROL = r0. */
+        "	bx lr									\n"/* Return to the caller. */
+        ::: "r0", "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                const struct xMEMORY_REGION * const xRegions,
+                                StackType_t * pxBottomOfStack,
+                                uint32_t ulStackDepth )
+{
+    #if defined( __ARMCC_VERSION )
+
+        /* Declaration when these variable are defined in code instead of being
+         * exported from linker scripts. */
+        extern uint32_t * __SRAM_segment_start__;
+        extern uint32_t * __SRAM_segment_end__;
+        extern uint32_t * __privileged_data_start__;
+        extern uint32_t * __privileged_data_end__;
+    #else
+        /* Declaration when these variable are exported from linker scripts. */
+        extern uint32_t __SRAM_segment_start__[];
+        extern uint32_t __SRAM_segment_end__[];
+        extern uint32_t __privileged_data_start__[];
+        extern uint32_t __privileged_data_end__[];
+    #endif /* if defined( __ARMCC_VERSION ) */
+
+    int32_t lIndex;
+    uint32_t ul;
+
+    if( xRegions == NULL )
+    {
+        /* No MPU regions are specified so allow access to all RAM. */
+        xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+            ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
+            ( portMPU_REGION_VALID ) |
+            ( portSTACK_REGION );
+
+        xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+            ( portMPU_REGION_READ_WRITE ) |
+            ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+            ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
+            ( portMPU_REGION_ENABLE );
+
+        /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
+         * just removed the privileged only parameters. */
+        xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
+            ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+            ( portMPU_REGION_VALID ) |
+            ( portSTACK_REGION + 1 );
+
+        xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
+            ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+            ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+            prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+            ( portMPU_REGION_ENABLE );
+
+        /* Invalidate all other regions. */
+        for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+        {
+            xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+            xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+        }
+    }
+    else
+    {
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid.  At all other
+         * times the stack parameters will not be valid and it is assumed that the
+         * stack region has already been configured. */
+        if( ulStackDepth > 0 )
+        {
+            /* Define the region that allows access to the stack. */
+            xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+                ( ( uint32_t ) pxBottomOfStack ) |
+                ( portMPU_REGION_VALID ) |
+                ( portSTACK_REGION ); /* Region number. */
+
+            xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+                ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
+                ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+                ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+                ( portMPU_REGION_ENABLE );
+        }
+
+        lIndex = 0;
+
+        for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+        {
+            if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
+            {
+                /* Translate the generic region definition contained in
+                 * xRegions into the CM4 specific MPU settings that are then
+                 * stored in xMPUSettings. */
+                xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
+                    ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
+                    ( portMPU_REGION_VALID ) |
+                    ( portSTACK_REGION + ul ); /* Region number. */
+
+                xMPUSettings->xRegion[ ul ].ulRegionAttribute =
+                    ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
+                    ( xRegions[ lIndex ].ulParameters ) |
+                    ( portMPU_REGION_ENABLE );
+            }
+            else
+            {
+                /* Invalidate the region. */
+                xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+                xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+            }
+
+            lIndex++;
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+    void vPortValidateInterruptPriority( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        uint8_t ucCurrentPriority;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that use the FreeRTOS API must not be left at their
+             * default priority of zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
+
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredicable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
new file mode 100644
index 0000000..a070356
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
@@ -0,0 +1,400 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
+
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
+
+#if ( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#else
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
+#endif
+/*-----------------------------------------------------------*/
+
+/* MPU specific constants. */
+#define portUSING_MPU_WRAPPERS                                   1
+#define portPRIVILEGE_BIT                                        ( 0x80000000UL )
+
+#define portMPU_REGION_READ_WRITE                                ( 0x03UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY                      ( 0x05UL << 24UL )
+#define portMPU_REGION_READ_ONLY                                 ( 0x06UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE                     ( 0x01UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY    ( 0x02UL << 24UL )
+#define portMPU_REGION_CACHEABLE_BUFFERABLE                      ( 0x07UL << 16UL )
+#define portMPU_REGION_EXECUTE_NEVER                             ( 0x01UL << 28UL )
+
+/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
+ * Register (RASR). */
+#define portMPU_RASR_TEX_S_C_B_LOCATION                          ( 16UL )
+#define portMPU_RASR_TEX_S_C_B_MASK                              ( 0x3FUL )
+
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+    /* Define to 8 for backward compatibility. */
+    #define configTOTAL_MPU_REGIONS    ( 8UL )
+#endif
+
+/*
+ * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
+ * memory type, and where necessary the cacheable and shareable properties
+ * of the memory region.
+ *
+ * The TEX, C, and B bits together indicate the memory type of the region,
+ * and:
+ * - For Normal memory, the cacheable properties of the region.
+ * - For Device memory, whether the region is shareable.
+ *
+ * For Normal memory regions, the S bit indicates whether the region is
+ * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
+ *
+ * See the following two tables for setting TEX, S, C and B bits for
+ * unprivileged flash, privileged flash and privileged RAM regions.
+ *
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | TEX | C | B | Memory type            |  Description or Normal region cacheability             |  Shareable?             |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 0 | 0 | Strongly-ordered       |  Strongly ordered                                      |  Shareable              |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 0 | 1 | Device                 |  Shared device                                         |  Shareable              |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 1 | 0 | Normal                 |  Outer and inner   write-through; no write allocate    |  S bit                  |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 1 | 1 | Normal                 |  Outer and inner   write-back; no write allocate       |  S bit                  |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 0 | 0 | Normal                 |  Outer and inner   Non-cacheable                       |  S bit                  |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 0 | 1 | Reserved               |  Reserved                                              |  Reserved               |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 1 | 0 | IMPLEMENTATION DEFINED |  IMPLEMENTATION DEFINED                                |  IMPLEMENTATION DEFINED |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 1 | 1 | Normal                 |  Outer and inner   write-back; write and read allocate |  S bit                  |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 0 | 0 | Device                 |  Non-shared device                                     |  Not shareable          |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 0 | 1 | Reserved               |  Reserved                                              |  Reserved               |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 1 | X | Reserved               |  Reserved                                              |  Reserved               |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 011 | X | X | Reserved               |  Reserved                                              |  Reserved               |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 1BB | A | A | Normal                 | Cached memory, with AA and BB indicating the inner and |  Reserved               |
+ |     |   |   |                        | outer cacheability rules that must be exported on the  |                         |
+ |     |   |   |                        | bus. See the table below for the cacheability policy   |                         |
+ |     |   |   |                        | encoding. memory, BB=Outer policy, AA=Inner policy.    |                         |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ |
+ +-----------------------------------------+----------------------------------------+
+ | AA or BB subfield of {TEX,C,B} encoding |  Cacheability policy                   |
+ +-----------------------------------------+----------------------------------------+
+ | 00                                      |  Non-cacheable                         |
+ +-----------------------------------------+----------------------------------------+
+ | 01                                      |  Write-back, write and   read allocate |
+ +-----------------------------------------+----------------------------------------+
+ | 10                                      |  Write-through, no write   allocate    |
+ +-----------------------------------------+----------------------------------------+
+ | 11                                      |  Write-back, no write   allocate       |
+ +-----------------------------------------+----------------------------------------+
+ */
+
+/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
+ * region. */
+#ifndef configTEX_S_C_B_FLASH
+    /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
+    #define configTEX_S_C_B_FLASH    ( 0x07UL )
+#endif
+
+/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM
+ * region. */
+#ifndef configTEX_S_C_B_SRAM
+    /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
+    #define configTEX_S_C_B_SRAM          ( 0x07UL )
+#endif
+
+#define portUNPRIVILEGED_FLASH_REGION     ( 0UL )
+#define portPRIVILEGED_FLASH_REGION       ( 1UL )
+#define portPRIVILEGED_RAM_REGION         ( 2UL )
+#define portGENERAL_PERIPHERALS_REGION    ( 3UL )
+#define portSTACK_REGION                  ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION     ( 5UL )
+#define portTOTAL_NUM_REGIONS             ( configTOTAL_MPU_REGIONS )
+#define portNUM_CONFIGURABLE_REGIONS      ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
+#define portLAST_CONFIGURABLE_REGION      ( portTOTAL_NUM_REGIONS - 1 )
+
+#define portSWITCH_TO_USER_MODE()    __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
+
+typedef struct MPU_REGION_REGISTERS
+{
+    uint32_t ulRegionBaseAddress;
+    uint32_t ulRegionAttribute;
+} xMPU_REGION_REGISTERS;
+
+/* Plus 1 to create space for the stack region. */
+typedef struct MPU_SETTINGS
+{
+    xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
+} xMPU_SETTINGS;
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+#define portDONT_DISCARD      __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/* SVC numbers for various services. */
+#define portSVC_START_SCHEDULER    0
+#define portSVC_YIELD              1
+#define portSVC_RAISE_PRIVILEGE    2
+
+/* Scheduler utilities. */
+
+#define portYIELD()    __asm volatile ( "	SVC	%0	\n"::"i" ( portSVC_YIELD ) : "memory" )
+#define portYIELD_WITHIN_API()                          \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+                                                        \
+        /* Barriers are normally not required but do ensure the code is completely \
+         * within the specified behaviour for the architecture. */ \
+        __asm volatile ( "dsb" ::: "memory" );                     \
+        __asm volatile ( "isb" );                                  \
+    }
+
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
+#define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Generic helper function. */
+    __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+    {
+        uint8_t ucReturn;
+
+        __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+
+        return ucReturn;
+    }
+
+/* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
+
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+    void vPortValidateInterruptPriority( void );
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE              __inline
+
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
+#endif
+/*-----------------------------------------------------------*/
+
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ */
+#define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE()    vResetPrivilege()
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. */
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+    uint32_t ulNewBASEPRI;
+
+    __asm volatile
+    (
+        "	mov %0, %1												\n"\
+        "	msr basepri, %0											\n"\
+        "	isb														\n"\
+        "	dsb														\n"\
+        : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+    );
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+    uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+    __asm volatile
+    (
+        "	mrs %0, basepri											\n"\
+        "	mov %1, %2												\n"\
+        "	msr basepri, %1											\n"\
+        "	isb														\n"\
+        "	dsb														\n"\
+        : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+    );
+
+    /* This return will not be reached but is necessary to prevent compiler
+     * warnings. */
+    return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+    __asm volatile
+    (
+        "	msr basepri, %0	"::"r" ( ulNewMaskValue ) : "memory"
+    );
+}
+/*-----------------------------------------------------------*/
+
+#define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+
+#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
+    #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
+    #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY    0
+#endif
+/*-----------------------------------------------------------*/
+
+/* *INDENT-OFF* */
+    #ifdef __cplusplus
+        }
+    #endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM7/ReadMe.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM7/ReadMe.txt
new file mode 100644
index 0000000..d661449
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM7/ReadMe.txt
@@ -0,0 +1,18 @@
+There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.
+The best option depends on the revision of the ARM Cortex-M7 core in use.  The
+revision is specified by an 'r' number, and a 'p' number, so will look something
+like 'r0p1'.  Check the documentation for the microcontroller in use to find the 
+revision of the Cortex-M7 core used in that microcontroller.  If in doubt, use 
+the FreeRTOS port provided specifically for r0p1 revisions, as that can be used
+with all core revisions.
+
+The first option is to use the ARM Cortex-M4F port, and the second option is to
+use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.
+
+If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be
+used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in 
+the /FreeRTOS/Source/portable/GCC/ARM_CM4F directory.
+
+If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM
+Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1
+directory.
\ No newline at end of file
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
new file mode 100644
index 0000000..e30e076
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
@@ -0,0 +1,773 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM7 port.
+*----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __VFP_FP__
+    #error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
+#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                    ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK                   ( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR                             ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS              ( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                      ( 0x01000000 )
+#define portINITIAL_EXC_RETURN                ( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#define portMISSED_COUNTS_FACTOR              ( 45UL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__( ( naked ) );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__( ( naked ) );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__( ( naked ) );
+
+/*
+ * Function to enable the VFP.
+ */
+static void vPortEnableVFP( void ) __attribute__( ( naked ) );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+
+    /* Offset added to account for the way the MCU uses the stack on entry/exit
+     * of interrupts, and to ensure alignment. */
+    pxTopOfStack--;
+
+    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;             /* LR */
+
+    /* Save code space by skipping register initialisation. */
+    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+    /* A save method is being used that requires each task to maintain its
+     * own exec return value. */
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+    pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    volatile uint32_t ulDummy = 0;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( uxCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being defined
+         * but never called.  ulDummy is used purely to quieten other warnings
+         * about code appearing after this function is called - making ulDummy
+         * volatile makes the compiler think the function could return and
+         * therefore not output an 'unreachable code' warning for code that appears
+         * after it. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+    __asm volatile (
+        "	ldr	r3, pxCurrentTCBConst2		\n"/* Restore the context. */
+        "	ldr r1, [r3]					\n"/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+        "	ldr r0, [r1]					\n"/* The first item in pxCurrentTCB is the task top of stack. */
+        "	ldmia r0!, {r4-r11, r14}		\n"/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+        "	msr psp, r0						\n"/* Restore the task stack pointer. */
+        "	isb								\n"
+        "	mov r0, #0 						\n"
+        "	msr	basepri, r0					\n"
+        "	bx r14							\n"
+        "									\n"
+        "	.align 4						\n"
+        "pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+        );
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+    /* Start the first task.  This also clears the bit that indicates the FPU is
+     * in use in case the FPU was used before the scheduler was started - which
+     * would otherwise result in the unnecessary leaving of space in the SVC stack
+     * for lazy saving of FPU registers. */
+    __asm volatile (
+        " ldr r0, =0xE000ED08 	\n"/* Use the NVIC offset register to locate the stack. */
+        " ldr r0, [r0] 			\n"
+        " ldr r0, [r0] 			\n"
+        " msr msp, r0			\n"/* Set the msp back to the start of the stack. */
+        " mov r0, #0			\n"/* Clear the bit that indicates the FPU is in use, see comment above. */
+        " msr control, r0		\n"
+        " cpsie i				\n"/* Globally enable interrupts. */
+        " cpsie f				\n"
+        " dsb					\n"
+        " isb					\n"
+        " svc 0					\n"/* System call to start first task. */
+        " nop					\n"
+        " .ltorg				\n"
+        );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+            volatile uint8_t ucMaxPriorityValue;
+
+            /* Determine the maximum priority from which ISR safe FreeRTOS API
+             * functions can be called.  ISR safe functions are those that end in
+             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+             * ensure interrupt entry is as fast and simple as possible.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+            /* Determine the number of priority bits available.  First write to all
+             * possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+            /* Use the same mask on the maximum system call priority. */
+            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+            /* Calculate the maximum acceptable priority group value for the number
+             * of bits read back. */
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+            {
+                ulMaxPRIGROUPValue--;
+                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+            }
+
+            #ifdef __NVIC_PRIO_BITS
+                {
+                    /* Check the CMSIS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+                }
+            #endif
+
+            #ifdef configPRIO_BITS
+                {
+                    /* Check the FreeRTOS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+                }
+            #endif
+
+            /* Shift the priority group value back to its position within the AIRCR
+             * register. */
+            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* conifgASSERT_DEFINED */
+
+    /* Make PendSV and SysTick the lowest priority interrupts. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Ensure the VFP is enabled - it should be anyway. */
+    vPortEnableVFP();
+
+    /* Lazy save always. */
+    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+    /* Start the first task. */
+    prvPortStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing!  Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS.  Call
+     * vTaskSwitchContext() so link time optimisation does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
+    if( uxCriticalNesting == 1 )
+    {
+        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void xPortPendSVHandler( void )
+{
+    /* This is a naked function. */
+
+    __asm volatile
+    (
+        "	mrs r0, psp							\n"
+        "	isb									\n"
+        "										\n"
+        "	ldr	r3, pxCurrentTCBConst			\n"/* Get the location of the current TCB. */
+        "	ldr	r2, [r3]						\n"
+        "										\n"
+        "	tst r14, #0x10						\n"/* Is the task using the FPU context?  If so, push high vfp registers. */
+        "	it eq								\n"
+        "	vstmdbeq r0!, {s16-s31}				\n"
+        "										\n"
+        "	stmdb r0!, {r4-r11, r14}			\n"/* Save the core registers. */
+        "	str r0, [r2]						\n"/* Save the new top of stack into the first member of the TCB. */
+        "										\n"
+        "	stmdb sp!, {r0, r3}					\n"
+        "	mov r0, %0 							\n"
+        "	cpsid i								\n"/* Errata workaround. */
+        "	msr basepri, r0						\n"
+        "	dsb									\n"
+        "	isb									\n"
+        "	cpsie i								\n"/* Errata workaround. */
+        "	bl vTaskSwitchContext				\n"
+        "	mov r0, #0							\n"
+        "	msr basepri, r0						\n"
+        "	ldmia sp!, {r0, r3}					\n"
+        "										\n"
+        "	ldr r1, [r3]						\n"/* The first item in pxCurrentTCB is the task top of stack. */
+        "	ldr r0, [r1]						\n"
+        "										\n"
+        "	ldmia r0!, {r4-r11, r14}			\n"/* Pop the core registers. */
+        "										\n"
+        "	tst r14, #0x10						\n"/* Is the task using the FPU context?  If so, pop the high vfp registers too. */
+        "	it eq								\n"
+        "	vldmiaeq r0!, {s16-s31}				\n"
+        "										\n"
+        "	msr psp, r0							\n"
+        "	isb									\n"
+        "										\n"
+        #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
+            #if WORKAROUND_PMU_CM001 == 1
+                "			push { r14 }				\n"
+                "			pop { pc }					\n"
+            #endif
+        #endif
+        "										\n"
+        "	bx r14								\n"
+        "										\n"
+        "	.align 4							\n"
+        "pxCurrentTCBConst: .word pxCurrentTCB	\n"
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+     * executes all interrupts must be unmasked.  There is therefore no need to
+     * save and then restore the interrupt mask value as its value is already
+     * known. */
+    portDISABLE_INTERRUPTS();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* A context switch is required.  Context switching is performed in
+             * the PendSV interrupt.  Pend the PendSV interrupt. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+         * is accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods.  -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm volatile ( "cpsid i" ::: "memory" );
+        __asm volatile ( "dsb" );
+        __asm volatile ( "isb" );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above the cpsid instruction()
+             * above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again.  However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm volatile ( "dsb" ::: "memory" );
+                __asm volatile ( "wfi" );
+                __asm volatile ( "isb" );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately.  see comments above
+             * __disable_interrupt() call above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __asm volatile ( "cpsid i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is yet
+             * to count to zero (in which case an interrupt other than the SysTick
+             * must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+    }
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void )
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and clear the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+    __asm volatile
+    (
+        "	ldr.w r0, =0xE000ED88		\n"/* The FPU enable bits are in the CPACR. */
+        "	ldr r1, [r0]				\n"
+        "								\n"
+        "	orr r1, r1, #( 0xf << 20 )	\n"/* Enable CP10 and CP11 coprocessors, then save back. */
+        "	str r1, [r0]				\n"
+        "	bx r14						\n"
+        "	.ltorg						\n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+    void vPortValidateInterruptPriority( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        uint8_t ucCurrentPriority;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that	use the FreeRTOS API must not be left at their
+             * default priority of	zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and	therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
+
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredictable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
+
+#endif /* configASSERT_DEFINED */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
new file mode 100644
index 0000000..4aae2be
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
@@ -0,0 +1,248 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
+    #define portDONT_DISCARD      __attribute__( ( used ) )
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+    #define portYIELD()                                 \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+                                                        \
+        /* Barriers are normally not required but do ensure the code is completely \
+         * within the specified behaviour for the architecture. */ \
+        __asm volatile ( "dsb" ::: "memory" );                     \
+        __asm volatile ( "isb" );                                  \
+    }
+
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired != pdFALSE ) portYIELD()
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
+    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
+    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #endif
+
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Generic helper function. */
+        __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+        {
+            uint8_t ucReturn;
+
+            __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
+
+            return ucReturn;
+        }
+
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
+
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
+
+/* portNOP() is not required by this port. */
+    #define portNOP()
+
+    #define portINLINE              __inline
+
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
+    #endif
+
+    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        BaseType_t xReturn;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+        if( ulCurrentInterrupt == 0 )
+        {
+            xReturn = pdFALSE;
+        }
+        else
+        {
+            xReturn = pdTRUE;
+        }
+
+        return xReturn;
+    }
+
+/*-----------------------------------------------------------*/
+
+    portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+    {
+        uint32_t ulNewBASEPRI;
+
+        __asm volatile
+        (
+            "	mov %0, %1												\n"\
+            "	cpsid i													\n"\
+            "	msr basepri, %0											\n"\
+            "	isb														\n"\
+            "	dsb														\n"\
+            "	cpsie i													\n"\
+            : "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+        );
+    }
+
+/*-----------------------------------------------------------*/
+
+    portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+    {
+        uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+        __asm volatile
+        (
+            "	mrs %0, basepri											\n"\
+            "	mov %1, %2												\n"\
+            "	cpsid i													\n"\
+            "	msr basepri, %1											\n"\
+            "	isb														\n"\
+            "	dsb														\n"\
+            "	cpsie i													\n"\
+            : "=r" ( ulOriginalBASEPRI ), "=r" ( ulNewBASEPRI ) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
+        );
+
+        /* This return will not be reached but is necessary to prevent compiler
+         * warnings. */
+        return ulOriginalBASEPRI;
+    }
+/*-----------------------------------------------------------*/
+
+    portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+    {
+        __asm volatile
+        (
+            "	msr basepri, %0	"::"r" ( ulNewMaskValue ) : "memory"
+        );
+    }
+/*-----------------------------------------------------------*/
+
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c
new file mode 100644
index 0000000..de80c2e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c
@@ -0,0 +1,529 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
+    #error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+#endif
+
+#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
+    #error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+#endif
+
+#ifndef configUNIQUE_INTERRUPT_PRIORITIES
+    #error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+#endif
+
+#ifndef configSETUP_TICK_INTERRUPT
+    #error configSETUP_TICK_INTERRUPT() must be defined.  Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+#endif /* configSETUP_TICK_INTERRUPT */
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  Refer to Cortex-A equivalent: http: /*www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html */
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
+    #error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
+    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+    /* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/* In case security extensions are implemented. */
+#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+    #error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+#endif
+
+/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
+ * portmacro.h. */
+#ifndef configCLEAR_TICK_INTERRUPT
+    #define configCLEAR_TICK_INTERRUPT()
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+ * this value. */
+#define portNO_CRITICAL_NESTING          ( ( uint32_t ) 0 )
+
+/* In all GICs 255 can be written to the priority mask register to unmask all
+ * (but the lowest) interrupt priority. */
+#define portUNMASK_VALUE                 ( 0xFFUL )
+
+/* Tasks are not created with a floating point context, but can be given a
+ * floating point context after they have been created.  A variable is stored as
+ * part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+ * does not have an FPU context, or any other value if the task does have an FPU
+ * context. */
+#define portNO_FLOATING_POINT_CONTEXT    ( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR                 ( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT               ( ( StackType_t ) 0x20 )
+#define portINTERRUPT_ENABLE_BIT         ( 0x80UL )
+#define portTHUMB_MODE_ADDRESS           ( 0x01UL )
+
+/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
+ * point is zero. */
+#define portBINARY_POINT_BITS            ( ( uint8_t ) 0x03 )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK          ( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+ * mode. */
+#define portAPSR_USER_MODE               ( 0x10 )
+
+/* The critical section macros only mask interrupts up to an application
+ * determined priority level.  Sometimes it is necessary to turn interrupt off in
+ * the CPU itself before modifying certain hardware registers. */
+#define portCPU_IRQ_DISABLE()                  \
+    __asm volatile ( "CPSID i" ::: "memory" ); \
+    __asm volatile ( "DSB" );                  \
+    __asm volatile ( "ISB" );
+
+#define portCPU_IRQ_ENABLE()                   \
+    __asm volatile ( "CPSIE i" ::: "memory" ); \
+    __asm volatile ( "DSB" );                  \
+    __asm volatile ( "ISB" );
+
+
+/* Macro to unmask all interrupt priorities. */
+#define portCLEAR_INTERRUPT_MASK()                            \
+    {                                                         \
+        portCPU_IRQ_DISABLE();                                \
+        portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE; \
+        __asm volatile ( "DSB		\n"                       \
+                         "ISB		\n");                         \
+        portCPU_IRQ_ENABLE();                                 \
+    }
+
+#define portINTERRUPT_PRIORITY_REGISTER_OFFSET    0x400UL
+#define portMAX_8_BIT_VALUE                       ( ( uint8_t ) 0xff )
+#define portBIT_0_SET                             ( ( uint8_t ) 0x01 )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+ * prvTaskExitError() in case is messes up unwinding of the stack in the
+ * debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.  This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+ * variable has to be stored as part of the task context and must be initialised to
+ * a non zero value to ensure interrupts don't inadvertently become unmasked before
+ * the scheduler starts.  As it is stored as part of the task context it will
+ * automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
+ * a floating point context must be saved and restored for the task. */
+uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth.  A context switch is only performed if
+ * if the nesting depth is 0. */
+uint32_t ulPortInterruptNesting = 0UL;
+
+/* Used in asm code. */
+__attribute__( ( used ) ) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint32_t ulICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
+__attribute__( ( used ) ) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Setup the initial stack of the task.  The stack is set exactly as
+     * expected by the portRESTORE_CONTEXT() macro.
+     *
+     * The fist real value on the stack is the status register, which is set for
+     * system mode, with interrupts enabled.  A few NULLs are added first to ensure
+     * GDB does not try decoding a non-existent return address. */
+    *pxTopOfStack = ( StackType_t ) NULL;
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) NULL;
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) NULL;
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+    if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+    {
+        /* The task will start in THUMB mode. */
+        *pxTopOfStack |= portTHUMB_MODE_BIT;
+    }
+
+    pxTopOfStack--;
+
+    /* Next the return address, which in this case is the start of the task. */
+    *pxTopOfStack = ( StackType_t ) pxCode;
+    pxTopOfStack--;
+
+    /* Next all the registers other than the stack pointer. */
+    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* R14 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x12121212;              /* R12 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x11111111;              /* R11 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x10101010;              /* R10 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x09090909;              /* R9 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x08080808;              /* R8 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x07070707;              /* R7 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x06060606;              /* R6 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x05050505;              /* R5 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x04040404;              /* R4 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x03030303;              /* R3 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x02020202;              /* R2 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x01010101;              /* R1 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+    pxTopOfStack--;
+
+    /* The task will start with a critical nesting count of 0 as interrupts are
+     * enabled. */
+    *pxTopOfStack = portNO_CRITICAL_NESTING;
+    pxTopOfStack--;
+
+    /* The task will start without a floating point context.  A task that uses
+     * the floating point hardware must call vPortTaskUsesFPU() before executing
+     * any floating point instructions. */
+    *pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( ulPortInterruptNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    for( ; ; )
+    {
+    }
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+    uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */
+
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
+            volatile uint8_t ucMaxPriorityValue;
+
+            /* Determine how many priority bits are implemented in the GIC.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+            /* Determine the number of priority bits available.  First write to
+             * all possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+            /* Shift to the least significant bits. */
+            while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
+            {
+                ucMaxPriorityValue >>= ( uint8_t ) 0x01;
+
+                /* If ulCycles reaches 0 then ucMaxPriorityValue must have been
+                 * read as 0, indicating a misconfiguration. */
+                ulCycles--;
+
+                if( ulCycles == 0 )
+                {
+                    break;
+                }
+            }
+
+            /* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
+             * value. */
+            configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
+
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* conifgASSERT_DEFINED */
+
+    /* Only continue if the CPU is not in User mode.  The CPU must be in a
+     * Privileged mode for the scheduler to start. */
+    __asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR )::"memory" );
+    ulAPSR &= portAPSR_MODE_BITS_MASK;
+    configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+    if( ulAPSR != portAPSR_USER_MODE )
+    {
+        /* Only continue if the binary point value is set to its lowest possible
+         * setting.  See the comments in vPortValidateInterruptPriority() below for
+         * more information. */
+        configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+
+        if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+        {
+            /* Interrupts are turned off in the CPU itself to ensure tick does
+             * not execute	while the scheduler is being started.  Interrupts are
+             * automatically turned back on in the CPU when the first task starts
+             * executing. */
+            portCPU_IRQ_DISABLE();
+
+            /* Start the timer that generates the tick ISR. */
+            configSETUP_TICK_INTERRUPT();
+
+            /* Start the first task executing. */
+            vPortRestoreTaskContext();
+        }
+    }
+
+    /* Will only get here if vTaskStartScheduler() was called with the CPU in
+     * a non-privileged mode or the binary point register was not set to its lowest
+     * possible value.  prvTaskExitError() is referenced to prevent a compiler
+     * warning about it being defined but not referenced in the case that the user
+     * defines their own exit address. */
+    ( void ) prvTaskExitError;
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    /* Mask interrupts up to the max syscall interrupt priority. */
+    ulPortSetInterruptMask();
+
+    /* Now interrupts are disabled ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
+    ulCriticalNesting++;
+
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
+    if( ulCriticalNesting == 1 )
+    {
+        configASSERT( ulPortInterruptNesting == 0 );
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+    {
+        /* Decrement the nesting count as the critical section is being
+         * exited. */
+        ulCriticalNesting--;
+
+        /* If the nesting level has reached zero then all interrupt
+         * priorities must be re-enabled. */
+        if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+        {
+            /* Critical nesting has reached zero so all interrupt priorities
+             * should be unmasked. */
+            portCLEAR_INTERRUPT_MASK();
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+    /* Set interrupt mask before altering scheduler structures.   The tick
+     * handler runs at the lowest priority, so interrupts cannot already be masked,
+     * so there is no need to save and restore the current mask value.  It is
+     * necessary to turn off interrupts in the CPU itself while the ICCPMR is being
+     * updated. */
+    portCPU_IRQ_DISABLE();
+    portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+    __asm volatile ( "dsb		\n"
+                     "isb		\n"::: "memory" );
+    portCPU_IRQ_ENABLE();
+
+    /* Increment the RTOS tick. */
+    if( xTaskIncrementTick() != pdFALSE )
+    {
+        ulPortYieldRequired = pdTRUE;
+    }
+
+    /* Ensure all interrupt priorities are active again. */
+    portCLEAR_INTERRUPT_MASK();
+    configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+    uint32_t ulInitialFPSCR = 0;
+
+    /* A task is registering the fact that it needs an FPU context.  Set the
+     * FPU flag (which is saved as part of the task context). */
+    ulPortTaskHasFPUContext = pdTRUE;
+
+    /* Initialise the floating point status register. */
+    __asm volatile ( "FMXR 	FPSCR, %0" ::"r" ( ulInitialFPSCR ) : "memory" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( uint32_t ulNewMaskValue )
+{
+    if( ulNewMaskValue == pdFALSE )
+    {
+        portCLEAR_INTERRUPT_MASK();
+    }
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortSetInterruptMask( void )
+{
+    uint32_t ulReturn;
+
+    /* Interrupt in the CPU must be turned off while the ICCPMR is being
+     * updated. */
+    portCPU_IRQ_DISABLE();
+
+    if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+    {
+        /* Interrupts were already masked. */
+        ulReturn = pdTRUE;
+    }
+    else
+    {
+        ulReturn = pdFALSE;
+        portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+        __asm volatile ( "dsb		\n"
+                         "isb		\n"::: "memory" );
+    }
+
+    portCPU_IRQ_ENABLE();
+
+    return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+    void vPortValidateInterruptPriority( void )
+    {
+        /* The following assertion will fail if a service routine (ISR) for
+         * an interrupt that has been assigned a priority above
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+         * function.  ISR safe FreeRTOS API functions must *only* be called
+         * from interrupts that have been assigned a priority at or below
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+         *
+         * Numerically low interrupt priority numbers represent logically high
+         * interrupt priorities, therefore the priority of the interrupt must
+         * be set to a value equal to or numerically *higher* than
+         * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+         *
+         * FreeRTOS maintains separate thread and ISR API functions to ensure
+         * interrupt entry is as fast and simple as possible. */
+
+        configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+        /* Priority grouping:  The interrupt controller (GIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * The priority grouping is configured by the GIC's binary point register
+         * (ICCBPR).  Writing 0 to ICCBPR will ensure it is set to its lowest
+         * possible value (which may be above 0). */
+        configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+    }
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S
new file mode 100644
index 0000000..4925911
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S
@@ -0,0 +1,280 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	.text
+	.arm
+
+	.set SYS_MODE,	0x1f
+	.set SVC_MODE,	0x13
+	.set IRQ_MODE,	0x12
+
+	/* Hardware registers. */
+	.extern ulICCIAR
+	.extern ulICCEOIR
+	.extern ulICCPMR
+
+	/* Variables and functions. */
+	.extern ulMaxAPIPriorityMask
+	.extern _freertos_vector_table
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern vApplicationIRQHandler
+	.extern ulPortInterruptNesting
+	.extern ulPortTaskHasFPUContext
+
+	.global FreeRTOS_IRQ_Handler
+	.global FreeRTOS_SWI_Handler
+	.global vPortRestoreTaskContext
+
+.macro portSAVE_CONTEXT
+
+	/* Save the LR and SPSR onto the system mode stack before switching to
+	system mode to save the remaining system mode registers. */
+	SRSDB	sp!, #SYS_MODE
+	CPS		#SYS_MODE
+	PUSH	{R0-R12, R14}
+
+	/* Push the critical nesting count. */
+	LDR		R2, ulCriticalNestingConst
+	LDR		R1, [R2]
+	PUSH	{R1}
+
+	/* Does the task have a floating point context that needs saving?  If
+	ulPortTaskHasFPUContext is 0 then no. */
+	LDR		R2, ulPortTaskHasFPUContextConst
+	LDR		R3, [R2]
+	CMP		R3, #0
+
+	/* Save the floating point context, if any. */
+	FMRXNE  R1,  FPSCR
+	VPUSHNE {D0-D15}
+	/*VPUSHNE	{D16-D31}*/
+	PUSHNE	{R1}
+
+	/* Save ulPortTaskHasFPUContext itself. */
+	PUSH	{R3}
+
+	/* Save the stack pointer in the TCB. */
+	LDR		R0, pxCurrentTCBConst
+	LDR		R1, [R0]
+	STR		SP, [R1]
+
+	.endm
+
+; /**********************************************************************/
+
+.macro portRESTORE_CONTEXT
+
+	/* Set the SP to point to the stack of the task being restored. */
+	LDR		R0, pxCurrentTCBConst
+	LDR		R1, [R0]
+	LDR		SP, [R1]
+
+	/* Is there a floating point context to restore?  If the restored
+	ulPortTaskHasFPUContext is zero then no. */
+	LDR		R0, ulPortTaskHasFPUContextConst
+	POP		{R1}
+	STR		R1, [R0]
+	CMP		R1, #0
+
+	/* Restore the floating point context, if any. */
+	POPNE 	{R0}
+	/*VPOPNE	{D16-D31}*/
+	VPOPNE	{D0-D15}
+	VMSRNE  FPSCR, R0
+
+	/* Restore the critical section nesting depth. */
+	LDR		R0, ulCriticalNestingConst
+	POP		{R1}
+	STR		R1, [R0]
+
+	/* Ensure the priority mask is correct for the critical nesting depth. */
+	LDR		R2, ulICCPMRConst
+	LDR		R2, [R2]
+	CMP		R1, #0
+	MOVEQ	R4, #255
+	LDRNE	R4, ulMaxAPIPriorityMaskConst
+	LDRNE	R4, [R4]
+	STR		R4, [R2]
+
+	/* Restore all system mode registers other than the SP (which is already
+	being used). */
+	POP		{R0-R12, R14}
+
+	/* Return to the task code, loading CPSR on the way. */
+	RFEIA	sp!
+
+	.endm
+
+
+
+
+/******************************************************************************
+ * SVC handler is used to start the scheduler.
+ *****************************************************************************/
+.align 4
+.type FreeRTOS_SWI_Handler, %function
+FreeRTOS_SWI_Handler:
+	/* Save the context of the current task and select a new task to run. */
+	portSAVE_CONTEXT
+	LDR R0, vTaskSwitchContextConst
+	BLX	R0
+	portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * vPortRestoreTaskContext is used to start the scheduler.
+ *****************************************************************************/
+.type vPortRestoreTaskContext, %function
+vPortRestoreTaskContext:
+	/* Switch to system mode. */
+	CPS		#SYS_MODE
+	portRESTORE_CONTEXT
+
+.align 4
+.type FreeRTOS_IRQ_Handler, %function
+FreeRTOS_IRQ_Handler:
+
+	/* Return to the interrupted instruction. */
+	SUB		lr, lr, #4
+
+	/* Push the return address and SPSR. */
+	PUSH	{lr}
+	MRS		lr, SPSR
+	PUSH	{lr}
+
+	/* Change to supervisor mode to allow reentry. */
+	CPS		#SVC_MODE
+
+	/* Push used registers. */
+	PUSH	{r0-r4, r12}
+
+	/* Increment nesting count.  r3 holds the address of ulPortInterruptNesting
+	for future use.  r1 holds the original ulPortInterruptNesting value for
+	future use. */
+	LDR		r3, ulPortInterruptNestingConst
+	LDR		r1, [r3]
+	ADD		r4, r1, #1
+	STR		r4, [r3]
+
+	/* Read value from the interrupt acknowledge register, which is stored in r0
+	for future parameter and interrupt clearing use. */
+	LDR 	r2, ulICCIARConst
+	LDR		r2, [r2]
+	LDR		r0, [r2]
+
+	/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
+	future use.  _RB_ Is this ever needed provided the start of the stack is
+	alligned on an 8-byte boundary? */
+	MOV		r2, sp
+	AND		r2, r2, #4
+	SUB		sp, sp, r2
+
+	/* Call the interrupt handler. */
+	PUSH	{r0-r4, lr}
+	LDR		r1, vApplicationIRQHandlerConst
+	BLX		r1
+	POP		{r0-r4, lr}
+	ADD		sp, sp, r2
+
+	CPSID	i
+	DSB
+	ISB
+
+	/* Write the value read from ICCIAR to ICCEOIR. */
+	LDR 	r4, ulICCEOIRConst
+	LDR		r4, [r4]
+	STR		r0, [r4]
+
+	/* Restore the old nesting count. */
+	STR		r1, [r3]
+
+	/* A context switch is never performed if the nesting count is not 0. */
+	CMP		r1, #0
+	BNE		exit_without_switch
+
+	/* Did the interrupt request a context switch?  r1 holds the address of
+	ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+	use. */
+	LDR		r1, =ulPortYieldRequired
+	LDR		r0, [r1]
+	CMP		r0, #0
+	BNE		switch_before_exit
+
+exit_without_switch:
+	/* No context switch.  Restore used registers, LR_irq and SPSR before
+	returning. */
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	MOVS	PC, LR
+
+switch_before_exit:
+	/* A context swtich is to be performed.  Clear the context switch pending
+	flag. */
+	MOV		r0, #0
+	STR		r0, [r1]
+
+	/* Restore used registers, LR-irq and SPSR before saving the context
+	to the task stack. */
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	portSAVE_CONTEXT
+
+	/* Call the function that selects the new task to execute.
+	vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+	instructions, or 8 byte aligned stack allocated data.  LR does not need
+	saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
+	LDR		R0, vTaskSwitchContextConst
+	BLX		R0
+
+	/* Restore the context of, and branch to, the task selected to execute
+	next. */
+	portRESTORE_CONTEXT
+
+ulICCIARConst:	.word ulICCIAR
+ulICCEOIRConst:	.word ulICCEOIR
+ulICCPMRConst: .word ulICCPMR
+pxCurrentTCBConst: .word pxCurrentTCB
+ulCriticalNestingConst: .word ulCriticalNesting
+ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
+ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask
+vTaskSwitchContextConst: .word vTaskSwitchContext
+vApplicationIRQHandlerConst: .word vApplicationIRQHandler
+ulPortInterruptNestingConst: .word ulPortInterruptNesting
+
+.end
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h
new file mode 100644
index 0000000..200fcc0
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h
@@ -0,0 +1,194 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    typedef uint32_t         TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+    #define portEND_SWITCHING_ISR( xSwitchRequired ) \
+    {                                                \
+        extern uint32_t ulPortYieldRequired;         \
+                                                     \
+        if( xSwitchRequired != pdFALSE )             \
+        {                                            \
+            ulPortYieldRequired = pdTRUE;            \
+        }                                            \
+    }
+
+    #define portYIELD_FROM_ISR( x )    portEND_SWITCHING_ISR( x )
+    #define portYIELD()                __asm volatile ( "SWI 0" ::: "memory" );
+
+
+/*-----------------------------------------------------------
+* Critical section control
+*----------------------------------------------------------*/
+
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+    extern uint32_t ulPortSetInterruptMask( void );
+    extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+    extern void vPortInstallFreeRTOSVectorTable( void );
+
+/* These macros do not globally disable/enable interrupts.  They do mask off
+ * interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+    #define portENTER_CRITICAL()                      vPortEnterCritical();
+    #define portEXIT_CRITICAL()                       vPortExitCritical();
+    #define portDISABLE_INTERRUPTS()                  ulPortSetInterruptMask()
+    #define portENABLE_INTERRUPTS()                   vPortClearInterruptMask( 0 )
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortClearInterruptMask( x )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not required for this port but included in case common demo code that uses these
+ * macros is used. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+ * handler for whichever peripheral is used to generate the RTOS tick. */
+    void FreeRTOS_Tick_Handler( void );
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+ * before any floating point instructions are executed. */
+    void vPortTaskUsesFPU( void );
+    #define portTASK_USES_FLOATING_POINT()    vPortTaskUsesFPU()
+
+    #define portLOWEST_INTERRUPT_PRIORITY           ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+    #define portLOWEST_USABLE_INTERRUPT_PRIORITY    ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #endif
+
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
+
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif /* configASSERT */
+
+    #define portNOP()                                         __asm volatile ( "NOP" )
+
+
+    #ifdef __cplusplus
+        } /* extern C */
+    #endif
+
+
+/* The number of bits to shift for an interrupt priority is dependent on the
+ * number of bits implemented by the interrupt controller. */
+    #if configUNIQUE_INTERRUPT_PRIORITIES == 16
+        #define portPRIORITY_SHIFT            4
+        #define portMAX_BINARY_POINT_VALUE    3
+    #elif configUNIQUE_INTERRUPT_PRIORITIES == 32
+        #define portPRIORITY_SHIFT            3
+        #define portMAX_BINARY_POINT_VALUE    2
+    #elif configUNIQUE_INTERRUPT_PRIORITIES == 64
+        #define portPRIORITY_SHIFT            2
+        #define portMAX_BINARY_POINT_VALUE    1
+    #elif configUNIQUE_INTERRUPT_PRIORITIES == 128
+        #define portPRIORITY_SHIFT            1
+        #define portMAX_BINARY_POINT_VALUE    0
+    #elif configUNIQUE_INTERRUPT_PRIORITIES == 256
+        #define portPRIORITY_SHIFT            0
+        #define portMAX_BINARY_POINT_VALUE    0
+    #else /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
+        #error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+    #endif /* if configUNIQUE_INTERRUPT_PRIORITIES == 16 */
+
+/* Interrupt controller access addresses. */
+    #define portICCPMR_PRIORITY_MASK_OFFSET                      ( 0x04 )
+    #define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET              ( 0x0C )
+    #define portICCEOIR_END_OF_INTERRUPT_OFFSET                  ( 0x10 )
+    #define portICCBPR_BINARY_POINT_OFFSET                       ( 0x08 )
+    #define portICCRPR_RUNNING_PRIORITY_OFFSET                   ( 0x14 )
+
+    #define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS       ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+    #define portICCPMR_PRIORITY_MASK_REGISTER                    ( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+    #define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS    ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+    #define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS        ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+    #define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS            ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+    #define portICCBPR_BINARY_POINT_REGISTER                     ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+    #define portICCRPR_RUNNING_PRIORITY_REGISTER                 ( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c
new file mode 100644
index 0000000..6f18723
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c
@@ -0,0 +1,319 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifndef configSETUP_TICK_INTERRUPT
+	#error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.
+#endif
+
+#ifndef configCLEAR_TICK_INTERRUPT
+	#error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created.  A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS			( 0x01UL )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK			( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+mode. */
+#define portAPSR_USER_MODE				( 0x10 )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.  This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts.  As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
+a floating point context must be saved and restored for the task. */
+volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+volatile uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth.  A context switch is only performed if
+if the nesting depth is 0. */
+volatile uint32_t ulPortInterruptNesting = 0UL;
+
+/* Used in the asm file to clear an interrupt. */
+__attribute__(( used )) const uint32_t ulICCEOIR = configEOI_ADDRESS;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro.
+
+	The fist real value on the stack is the status register, which is set for
+	system mode, with interrupts enabled.  A few NULLs are added first to ensure
+	GDB does not try decoding a non-existent return address. */
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+	{
+		/* The task will start in THUMB mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* Next the return address, which in this case is the start of the task. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	/* Next all the registers other than the stack pointer. */
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The task will start with a critical nesting count of 0 as interrupts are
+	enabled. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+	pxTopOfStack--;
+
+	/* The task will start without a floating point context.  A task that uses
+	the floating point hardware must call vPortTaskUsesFPU() before executing
+	any floating point instructions. */
+	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( ulPortInterruptNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+	/* Only continue if the CPU is not in User mode.  The CPU must be in a
+	Privileged mode for the scheduler to start. */
+	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
+	ulAPSR &= portAPSR_MODE_BITS_MASK;
+	configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+	if( ulAPSR != portAPSR_USER_MODE )
+	{
+		/* Start the timer that generates the tick ISR. */
+		portDISABLE_INTERRUPTS();
+		configSETUP_TICK_INTERRUPT();
+
+		/* Start the first task executing. */
+		vPortRestoreTaskContext();
+	}
+
+	/* Will only get here if vTaskStartScheduler() was called with the CPU in
+	a non-privileged mode or the binary point register was not set to its lowest
+	possible value.  prvTaskExitError() is referenced to prevent a compiler
+	warning about it being defined but not referenced in the case that the user
+	defines their own exit address. */
+	( void ) prvTaskExitError;
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( ulCriticalNesting == 1 )
+	{
+		configASSERT( ulPortInterruptNesting == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as the critical section is being
+		exited. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then all interrupt
+		priorities must be re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Critical nesting has reached zero so all interrupt priorities
+			should be unmasked. */
+			portENABLE_INTERRUPTS();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+uint32_t ulInterruptStatus;
+
+	ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+
+	/* Increment the RTOS tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		ulPortYieldRequired = pdTRUE;
+	}
+
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus );
+
+	configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+uint32_t ulInitialFPSCR = 0;
+
+	/* A task is registering the fact that it needs an FPU context.  Set the
+	FPU flag (which is saved as part of the task context). */
+	ulPortTaskHasFPUContext = pdTRUE;
+
+	/* Initialise the floating point status register. */
+	__asm volatile ( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S
new file mode 100644
index 0000000..415f8d9
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S
@@ -0,0 +1,264 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	.text
+	.arm
+
+	.set SYS_MODE,	0x1f
+	.set SVC_MODE,	0x13
+	.set IRQ_MODE,	0x12
+
+	/* Variables and functions. */
+	.extern ulMaxAPIPriorityMask
+	.extern _freertos_vector_table
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern vApplicationIRQHandler
+	.extern ulPortInterruptNesting
+	.extern ulPortTaskHasFPUContext
+	.extern ulICCEOIR
+	.extern ulPortYieldRequired
+
+	.global FreeRTOS_IRQ_Handler
+	.global FreeRTOS_SVC_Handler
+	.global vPortRestoreTaskContext
+
+
+.macro portSAVE_CONTEXT
+
+	/* Save the LR and SPSR onto the system mode stack before switching to
+	system mode to save the remaining system mode registers. */
+	SRSDB	sp!, #SYS_MODE
+	CPS		#SYS_MODE
+	PUSH	{R0-R12, R14}
+
+	/* Push the critical nesting count. */
+	LDR		R2, ulCriticalNestingConst
+	LDR		R1, [R2]
+	PUSH	{R1}
+
+	/* Does the task have a floating point context that needs saving?  If
+	ulPortTaskHasFPUContext is 0 then no. */
+	LDR		R2, ulPortTaskHasFPUContextConst
+	LDR		R3, [R2]
+	CMP		R3, #0
+
+	/* Save the floating point context, if any. */
+	FMRXNE  R1,  FPSCR
+	VPUSHNE {D0-D15}
+#if configFPU_D32 == 1
+	VPUSHNE	{D16-D31}
+#endif /* configFPU_D32 */
+	PUSHNE	{R1}
+
+	/* Save ulPortTaskHasFPUContext itself. */
+	PUSH	{R3}
+
+	/* Save the stack pointer in the TCB. */
+	LDR		R0, pxCurrentTCBConst
+	LDR		R1, [R0]
+	STR		SP, [R1]
+
+	.endm
+
+; /**********************************************************************/
+
+.macro portRESTORE_CONTEXT
+
+	/* Set the SP to point to the stack of the task being restored. */
+	LDR		R0, pxCurrentTCBConst
+	LDR		R1, [R0]
+	LDR		SP, [R1]
+
+	/* Is there a floating point context to restore?  If the restored
+	ulPortTaskHasFPUContext is zero then no. */
+	LDR		R0, ulPortTaskHasFPUContextConst
+	POP		{R1}
+	STR		R1, [R0]
+	CMP		R1, #0
+
+	/* Restore the floating point context, if any. */
+	POPNE 	{R0}
+#if configFPU_D32 == 1
+	VPOPNE	{D16-D31}
+#endif /* configFPU_D32 */
+	VPOPNE	{D0-D15}
+	VMSRNE  FPSCR, R0
+
+	/* Restore the critical section nesting depth. */
+	LDR		R0, ulCriticalNestingConst
+	POP		{R1}
+	STR		R1, [R0]
+
+	/* Restore all system mode registers other than the SP (which is already
+	being used). */
+	POP		{R0-R12, R14}
+
+	/* Return to the task code, loading CPSR on the way. */
+	RFEIA	sp!
+
+	.endm
+
+
+
+
+/******************************************************************************
+ * SVC handler is used to yield.
+ *****************************************************************************/
+.align 4
+.type FreeRTOS_SVC_Handler, %function
+FreeRTOS_SVC_Handler:
+	/* Save the context of the current task and select a new task to run. */
+	portSAVE_CONTEXT
+	LDR R0, vTaskSwitchContextConst
+	BLX	R0
+	portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * vPortRestoreTaskContext is used to start the scheduler.
+ *****************************************************************************/
+.align 4
+.type vPortRestoreTaskContext, %function
+vPortRestoreTaskContext:
+	/* Switch to system mode. */
+	CPS		#SYS_MODE
+	portRESTORE_CONTEXT
+
+.align 4
+.type FreeRTOS_IRQ_Handler, %function
+FreeRTOS_IRQ_Handler:
+	/* Return to the interrupted instruction. */
+	SUB		lr, lr, #4
+
+	/* Push the return address and SPSR. */
+	PUSH	{lr}
+	MRS		lr, SPSR
+	PUSH	{lr}
+
+	/* Change to supervisor mode to allow reentry. */
+	CPS		#0x13
+
+	/* Push used registers. */
+	PUSH	{r0-r3, r12}
+
+	/* Increment nesting count.  r3 holds the address of ulPortInterruptNesting
+	for future use.  r1 holds the original ulPortInterruptNesting value for
+	future use. */
+	LDR		r3, ulPortInterruptNestingConst
+	LDR		r1, [r3]
+	ADD		r0, r1, #1
+	STR		r0, [r3]
+
+	/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
+	future use. */
+	MOV		r0, sp
+	AND		r2, r0, #4
+	SUB		sp, sp, r2
+
+	/* Call the interrupt handler. */
+	PUSH	{r0-r3, lr}
+	LDR		r1, vApplicationIRQHandlerConst
+	BLX		r1
+	POP		{r0-r3, lr}
+	ADD		sp, sp, r2
+
+	CPSID	i
+	DSB
+	ISB
+
+	/* Write to the EOI register. */
+	LDR 	r0, ulICCEOIRConst
+	LDR		r2, [r0]
+	STR		r0, [r2]
+
+	/* Restore the old nesting count. */
+	STR		r1, [r3]
+
+	/* A context switch is never performed if the nesting count is not 0. */
+	CMP		r1, #0
+	BNE		exit_without_switch
+
+	/* Did the interrupt request a context switch?  r1 holds the address of
+	ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+	use. */
+	LDR		r1, ulPortYieldRequiredConst
+	LDR		r0, [r1]
+	CMP		r0, #0
+	BNE		switch_before_exit
+
+exit_without_switch:
+	/* No context switch.  Restore used registers, LR_irq and SPSR before
+	returning. */
+	POP		{r0-r3, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	MOVS	PC, LR
+
+switch_before_exit:
+	/* A context swtich is to be performed.  Clear the context switch pending
+	flag. */
+	MOV		r0, #0
+	STR		r0, [r1]
+
+	/* Restore used registers, LR-irq and SPSR before saving the context
+	to the task stack. */
+	POP		{r0-r3, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	portSAVE_CONTEXT
+
+	/* Call the function that selects the new task to execute.
+	vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+	instructions, or 8 byte aligned stack allocated data.  LR does not need
+	saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
+	LDR		R0, vTaskSwitchContextConst
+	BLX		R0
+
+	/* Restore the context of, and branch to, the task selected to execute
+	next. */
+	portRESTORE_CONTEXT
+
+ulICCEOIRConst:	.word ulICCEOIR
+pxCurrentTCBConst: .word pxCurrentTCB
+ulCriticalNestingConst: .word ulCriticalNesting
+ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
+vTaskSwitchContextConst: .word vTaskSwitchContext
+vApplicationIRQHandlerConst: .word vApplicationIRQHandler
+ulPortInterruptNestingConst: .word ulPortInterruptNesting
+ulPortYieldRequiredConst: .word ulPortYieldRequired
+
+.end
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
new file mode 100644
index 0000000..51c5c95
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
@@ -0,0 +1,181 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+	extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{												\
+extern volatile uint32_t ulPortYieldRequired;	\
+												\
+	if( xSwitchRequired != pdFALSE )			\
+	{											\
+		ulPortYieldRequired = pdTRUE;			\
+	}											\
+}
+
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm volatile ( "SWI 0		\n"				\
+									 "ISB		  " ::: "memory" );
+
+
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
+
+/* The I bit within the CPSR. */
+#define portINTERRUPT_ENABLE_BIT	( 1 << 7 )
+
+/* In the absence of a priority mask register, these functions and macros
+globally enable and disable interrupts. */
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+#define portENABLE_INTERRUPTS()		__asm volatile ( "CPSIE i 	\n"	::: "memory" );
+#define portDISABLE_INTERRUPTS()	__asm volatile ( "CPSID i 	\n"		\
+													 "DSB		\n"		\
+													 "ISB		  " ::: "memory" );
+
+__attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
+{
+volatile uint32_t ulCPSR;
+
+	__asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) :: "memory" );
+	ulCPSR &= portINTERRUPT_ENABLE_BIT;
+	portDISABLE_INTERRUPTS();
+	return ulCPSR;
+}
+
+#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	if( x == 0 ) portENABLE_INTERRUPTS()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+
+/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#define portNOP() __asm volatile( "NOP" )
+#define portINLINE __inline
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+#ifdef __cplusplus
+	} /* extern C */
+#endif
+
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_R5/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_R5/port.c
new file mode 100644
index 0000000..288bfb2
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_R5/port.c
@@ -0,0 +1,287 @@
+/*
+    FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+    All rights reserved
+    Copyright (c) 2014-2016 NVIDIA CORPORATION.  All rights reserved.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------*/
+
+/* Count of the critical section nesting depth. */
+uint32_t ulCriticalNesting = 9999;
+
+/*-----------------------------------------------------------*/
+
+/* Constants required to set up the initial stack of each task. */
+#define portINITIAL_SPSR		( ( StackType_t ) 0x1F )
+#define portINITIAL_FPSCR		( ( StackType_t ) 0x00 )
+#define portINSTRUCTION_SIZE	( ( StackType_t ) 0x04 )
+#define portTHUMB_MODE_BIT		( ( StackType_t ) 0x20 )
+
+/* The number of words on the stack frame between the saved Top Of Stack and
+R0 (in which the parameters are passed. */
+#define portSPACE_BETWEEN_TOS_AND_PARAMETERS	( 12 )
+
+/*-----------------------------------------------------------*/
+
+/* vPortStartFirstSTask() is defined in portASM.asm */
+extern void vPortStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* Saved as part of the task context.  Set to pdFALSE if the task does not
+require an FPU context. */
+uint32_t ulTaskHasFPUContext = 0;
+
+/* Set to 1 to pend a context switch from an ISR. */
+uint32_t ulPortYieldRequired = pdFALSE;
+
+/*-----------------------------------------------------------*/
+
+/** \brief  Get CPSR
+
+    This function returns the current value of the CPSR
+    register.
+
+    \return               CPSR register value
+*/
+__attribute__( ( always_inline ) ) static inline unsigned long _get_CPSR(void)
+{
+unsigned long result;
+
+	__asm volatile ("MRS %0, cpsr" : "=r" (result) );
+	return(result);
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which is the start of the as
+	the task has not executed yet.  The offset is added to make the return
+	address appear as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x00000000;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+
+	#ifdef portPRELOAD_TASK_REGISTERS
+	{
+		*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS;
+	}
+	#endif
+
+	/* Function parameters are passed in R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* Set the status register for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) ( ( _get_CPSR() & ~0xFF ) | portINITIAL_SPSR );
+
+	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
+	{
+		/* The task will start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	/* ulUsingFPU, which by default is set to indicate
+	that the stack frame does not include FPU registers. */
+	pxTopOfStack--;
+	*pxTopOfStack = pdFALSE;
+
+	/*  ulCriticalNesting, which by default is set to 0 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler(void)
+{
+	configSETUP_TICK_INTERRUPT();
+
+	/* Reset the critical section nesting count read to execute the first task. */
+	ulCriticalNesting = 0;
+
+	/* Start the first task.  This is done from portASM.S as ARM mode must be
+	used. */
+	vPortStartFirstTask();
+
+	/* Should not get here! */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+void vPortEndScheduler(void)
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Disable interrupts, and keep a count of the nesting depth.
+ */
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
+	portDISABLE_INTERRUPTS();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Decrement the critical nesting count, and if it has reached zero, re-enable
+ * interrupts.
+ */
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > 0 )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == 0 )
+		{
+			/* Enable interrupts as per portENABLE_INTERRUPTS(). */
+			portENABLE_INTERRUPTS();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+	/* A task is registering the fact that it needs an FPU context.  Set the
+	FPU flag (saved as part of the task context. */
+	ulTaskHasFPUContext = pdTRUE;
+
+	/* Initialise the floating point status register. */
+	__asm ( "MOV     r0, #0     \n\t"\
+	        "VMSR    FPSCR, r0  \n\t");
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+	/* Increment the RTOS tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+		ulPortYieldRequired = pdTRUE;
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_R5/portASM.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_R5/portASM.S
new file mode 100644
index 0000000..372c47b
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_R5/portASM.S
@@ -0,0 +1,244 @@
+/*
+    FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+    All rights reserved
+    Copyright (c) 2014, NVIDIA CORPORATION.  All rights reserved.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>! NOTE: The modification to the GPL is included to allow you to distribute
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/* FreeRTOS includes. */
+/*
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+#include "FreeRTOSConfig.h"
+
+    .global vPortStartFirstTask
+    .global vPortYieldProcessor
+    .global vPortPreemptiveTick
+    .global irq_end
+
+    .text
+
+.macro portSAVE_CONTEXT
+    DSB
+    /* Push R0 as we are going to use it */
+    STMDB   SP!, {R0}
+
+    /* Set R0 to point to the task stack pointer.*/
+    STMDB   SP,{SP}^
+    SUB     SP, SP, #4
+    LDMIA   SP!,{R0}
+
+    /* Push the return address onto the stack. */
+    STMDB   R0!, {LR}
+
+    /* Now LR has been saved, it can be used instead of R0.*/
+    MOV     LR, R0
+
+    /* Pop R0 so it can be saved onto the task stack.*/
+    LDMIA   SP!, {R0}
+
+    /* Push all the system mode registers onto the task stack.*/
+    STMDB   LR,{R0-LR}^
+    SUB     LR, LR, #60
+
+    /* Push the SPSR onto the task stack.*/
+    MRS     R0, SPSR
+    STMDB   LR!, {R0}
+
+    /*Determine if the task maintains an FPU context.*/
+    LDR     R0, =ulTaskHasFPUContext
+    LDR     R0, [R0]
+
+    /* Test the flag */
+    CMP     R0, #0
+
+    /*If the task is not using a floating point context then skip the*/
+    /* saving of the FPU registers. */
+    BEQ     1f
+    FSTMDBD LR!, {D0-D15}
+    FMRX    R1,  FPSCR
+    STMFD   LR!, {R1}
+1:
+    /* Save the flag */
+    STMDB   LR!, {R0}
+
+    /* Save ulCriticalNesting */
+    LDR     R0, =ulCriticalNesting
+    LDR     R0, [R0]
+    STMDB   LR!, {R0}
+
+    /* Store the new top of stack for the task.*/
+    LDR     R0, =pxCurrentTCB
+    LDR     R0, [R0]
+    STR     LR, [R0]
+    .endm
+
+vPortStartFirstTask:
+portRESTORE_CONTEXT:
+    LDR     R0, =pxCurrentTCB
+    LDR     R0, [R0]
+    LDR     LR, [R0]
+
+    /* The critical nest context counter is the first thing on the stack.*/
+    LDR     R0, =ulCriticalNesting
+    LDMFD   LR!, {R1}
+    STR     R1, [R0]
+
+    /* The floating point context flag is the second thing on the stack.*/
+    LDR     R0, =ulTaskHasFPUContext
+    LDMFD   LR!, {R1}
+    STR     R1, [R0]
+
+    /* Test the flag */
+    CMP     R1, #0
+
+    /*If the task is not using a floating point context then */
+    /*skip the VFP register loads. */
+    BEQ     1f
+
+    /* Restore the floating point context. */
+    LDMFD   LR!, {R0}
+    FLDMIAD LR!, {D0-D15}
+    FMXR    FPSCR, R0
+1:
+    /* Get the SPSR from the stack.*/
+    LDMFD   LR!, {R0}
+    MSR     spsr_csxf, R0
+
+    /* Restore all system mode registers for the task.*/
+    LDMFD   LR, {R0-R14}^
+
+    /*  Restore the return address.*/
+    LDR     LR, [LR, #+60]
+
+    /* And return - correcting the offset in the LR to obtain the*/
+    /* correct address. */
+    SUBS    PC, LR, #4
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ *
+ * When a context switch is performed from the task level the saved task
+ * context is made to look as if it occurred from within the tick ISR.  This
+ * way the same restore context function can be used when restoring the context
+ * saved from the ISR or that saved from a call to vPortYieldProcessor.
+ */
+vPortYieldProcessor:
+    /* Within an IRQ ISR the link register has an offset from the true return
+    address, but an SWI ISR does not.  Add the offset manually so the same
+    ISR return code can be used in both cases. */
+    ADD     LR, LR, #4
+
+    /* Perform the context switch.  First save the context of the current task. */
+    portSAVE_CONTEXT
+
+    /* Find the highest priority task that is ready to run. */
+    BLX     vTaskSwitchContext
+
+    /* Restore the context of the new task. */
+    b portRESTORE_CONTEXT
+
+vPortPreemptiveTick:
+    PUSH    { R0-R3, IP, LR }
+
+    /* Clear tick IRQ status early */
+    configCLEAR_TICK_INTERRUPT
+
+    /* Increment the tick count, making any adjustments to the blocked lists
+    that may be necessary.*/
+    BLX     xTaskIncrementTick
+
+    LDR     R1, =ulPortYieldRequired
+    STR     R0, [R1]
+
+    configACKNOWLEDGE_TICK_INTERRUPT
+
+/* irq_end can be used in end of an irq handler and do a context switch if required.
+ * "PUSH { R0-R3, IP, LR }" must be used in irq handler before jumping to irq_end.
+ *
+ * An example to use irq_end:
+ * IRQ_Handler:
+ *     PUSH    { R0-R3, IP, LR }
+ *     BLX     Application_IRQ_Handler
+ *     B       irq_end
+ */
+irq_end:
+    LDR     R1, =ulPortYieldRequired
+    LDR     R0, [R1]
+    CMP     R0, #0
+    BNE     irq_end_with_context_switch
+
+    POP     { R0-R3, IP, LR }
+    SUBS    PC, LR, #4
+
+irq_end_with_context_switch:
+    /* Clear context swtich pending flag. */
+    MOV     R0, #0
+    STR     R0, [R1]
+    POP     { R0-R3, IP, LR }
+
+    /* Save the context of the current task.*/
+    portSAVE_CONTEXT
+    BLX     vTaskSwitchContext
+    /* Restore the context of the task selected to execute.*/
+    b       portRESTORE_CONTEXT
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_R5/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_R5/portmacro.h
new file mode 100644
index 0000000..8eec452
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ARM_R5/portmacro.h
@@ -0,0 +1,164 @@
+/*
+    FreeRTOS V8.1.2 - Copyright (C) 2014 Real Time Engineers Ltd.
+    All rights reserved
+    Copyright (c) 2014-2016 NVIDIA CORPORATION.  All rights reserved.
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that has become a de facto standard.             *
+     *                                                                       *
+     *    Help yourself get started quickly and support the FreeRTOS         *
+     *    project by purchasing a FreeRTOS tutorial book, reference          *
+     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
+     *                                                                       *
+     *    Thank you!                                                         *
+     *                                                                       *
+    ***************************************************************************
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+    link: http://www.freertos.org/a00114.html
+
+    1 tab == 4 spaces!
+
+    ***************************************************************************
+     *                                                                       *
+     *    Having a problem?  Start by reading the FAQ "My application does   *
+     *    not run, what could be wrong?"                                     *
+     *                                                                       *
+     *    http://www.FreeRTOS.org/FAQHelp.html                               *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
+    license and Real Time Engineers Ltd. contact details.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
+    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef __PORTMACRO_H__
+#define __PORTMACRO_H__
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if (configUSE_16_BIT_TICKS == 1)
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY (TickType_t) 0xFFFF
+#else
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY (TickType_t) 0xFFFFFFFF
+#endif
+
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH    (-1)
+#define portTICK_PERIOD_MS  ((TickType_t) 1000 / configTICK_RATE_HZ)
+#define portBYTE_ALIGNMENT  8
+
+/* Critical section handling. */
+extern void vPortEnterCritical(void);
+extern void vPortExitCritical(void);
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+#define portDISABLE_INTERRUPTS()	__asm__( " CPSID I" )
+#define portENABLE_INTERRUPTS()		__asm__( " CPSIE I" )
+
+extern uint32_t ulPortYieldRequired;
+
+/* Scheduler utilities. */
+/* Called at the end of an ISR that can cause a context switch. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{												\
+	if( xSwitchRequired != pdFALSE )			\
+	{											\
+		ulPortYieldRequired = pdTRUE;			\
+	}											\
+}
+
+#define portYIELD()					__asm__ volatile ( "SWI 0" )
+#define portYIELD_FROM_ISR( x )		portEND_SWITCHING_ISR( x )
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+void FreeRTOS_Tick_Handler( void );
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+/* Architecture specific optimisations. */
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION(vFunction, pvParameters)       void vFunction(void *pvParameters)
+#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
+
+#endif /* __PORTMACRO_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ATMega323/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ATMega323/port.c
new file mode 100644
index 0000000..e423ab6
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ATMega323/port.c
@@ -0,0 +1,426 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* 
+
+Changes from V2.6.0
+
+	+ AVR port - Replaced the inb() and outb() functions with direct memory
+	  access.  This allows the port to be built with the 20050414 build of
+	  WinAVR.
+*/
+
+#include <stdlib.h>
+#include <avr/interrupt.h>
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the AVR port.
+ *----------------------------------------------------------*/
+
+/* Start tasks with interrupts enables. */
+#define portFLAGS_INT_ENABLED					( ( StackType_t ) 0x80 )
+
+/* Hardware constants for timer 1. */
+#define portCLEAR_COUNTER_ON_MATCH				( ( uint8_t ) 0x08 )
+#define portPRESCALE_64							( ( uint8_t ) 0x03 )
+#define portCLOCK_PRESCALER						( ( uint32_t ) 64 )
+#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE	( ( uint8_t ) 0x10 )
+
+/*-----------------------------------------------------------*/
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Macro to save all the general purpose registers, the save the stack pointer
+ * into the TCB.  
+ * 
+ * The first thing we do is save the flags then disable interrupts.  This is to 
+ * guard our stack against having a context switch interrupt after we have already 
+ * pushed the registers onto the stack - causing the 32 registers to be on the 
+ * stack twice. 
+ * 
+ * r1 is set to zero as the compiler expects it to be thus, however some
+ * of the math routines make use of R1. 
+ * 
+ * The interrupts will have been disabled during the call to portSAVE_CONTEXT()
+ * so we need not worry about reading/writing to the stack pointer. 
+ */
+
+#define portSAVE_CONTEXT()									\
+	asm volatile (	"push	r0						\n\t"	\
+					"in		r0, __SREG__			\n\t"	\
+					"cli							\n\t"	\
+					"push	r0						\n\t"	\
+					"push	r1						\n\t"	\
+					"clr	r1						\n\t"	\
+					"push	r2						\n\t"	\
+					"push	r3						\n\t"	\
+					"push	r4						\n\t"	\
+					"push	r5						\n\t"	\
+					"push	r6						\n\t"	\
+					"push	r7						\n\t"	\
+					"push	r8						\n\t"	\
+					"push	r9						\n\t"	\
+					"push	r10						\n\t"	\
+					"push	r11						\n\t"	\
+					"push	r12						\n\t"	\
+					"push	r13						\n\t"	\
+					"push	r14						\n\t"	\
+					"push	r15						\n\t"	\
+					"push	r16						\n\t"	\
+					"push	r17						\n\t"	\
+					"push	r18						\n\t"	\
+					"push	r19						\n\t"	\
+					"push	r20						\n\t"	\
+					"push	r21						\n\t"	\
+					"push	r22						\n\t"	\
+					"push	r23						\n\t"	\
+					"push	r24						\n\t"	\
+					"push	r25						\n\t"	\
+					"push	r26						\n\t"	\
+					"push	r27						\n\t"	\
+					"push	r28						\n\t"	\
+					"push	r29						\n\t"	\
+					"push	r30						\n\t"	\
+					"push	r31						\n\t"	\
+					"lds	r26, pxCurrentTCB		\n\t"	\
+					"lds	r27, pxCurrentTCB + 1	\n\t"	\
+					"in		r0, 0x3d				\n\t"	\
+					"st		x+, r0					\n\t"	\
+					"in		r0, 0x3e				\n\t"	\
+					"st		x+, r0					\n\t"	\
+				);
+
+/* 
+ * Opposite to portSAVE_CONTEXT().  Interrupts will have been disabled during
+ * the context save so we can write to the stack pointer. 
+ */
+
+#define portRESTORE_CONTEXT()								\
+	asm volatile (	"lds	r26, pxCurrentTCB		\n\t"	\
+					"lds	r27, pxCurrentTCB + 1	\n\t"	\
+					"ld		r28, x+					\n\t"	\
+					"out	__SP_L__, r28			\n\t"	\
+					"ld		r29, x+					\n\t"	\
+					"out	__SP_H__, r29			\n\t"	\
+					"pop	r31						\n\t"	\
+					"pop	r30						\n\t"	\
+					"pop	r29						\n\t"	\
+					"pop	r28						\n\t"	\
+					"pop	r27						\n\t"	\
+					"pop	r26						\n\t"	\
+					"pop	r25						\n\t"	\
+					"pop	r24						\n\t"	\
+					"pop	r23						\n\t"	\
+					"pop	r22						\n\t"	\
+					"pop	r21						\n\t"	\
+					"pop	r20						\n\t"	\
+					"pop	r19						\n\t"	\
+					"pop	r18						\n\t"	\
+					"pop	r17						\n\t"	\
+					"pop	r16						\n\t"	\
+					"pop	r15						\n\t"	\
+					"pop	r14						\n\t"	\
+					"pop	r13						\n\t"	\
+					"pop	r12						\n\t"	\
+					"pop	r11						\n\t"	\
+					"pop	r10						\n\t"	\
+					"pop	r9						\n\t"	\
+					"pop	r8						\n\t"	\
+					"pop	r7						\n\t"	\
+					"pop	r6						\n\t"	\
+					"pop	r5						\n\t"	\
+					"pop	r4						\n\t"	\
+					"pop	r3						\n\t"	\
+					"pop	r2						\n\t"	\
+					"pop	r1						\n\t"	\
+					"pop	r0						\n\t"	\
+					"out	__SREG__, r0			\n\t"	\
+					"pop	r0						\n\t"	\
+				);
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform hardware setup to enable ticks from timer 1, compare match A.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint16_t usAddress;
+
+	/* Place a few bytes of known values on the bottom of the stack. 
+	This is just useful for debugging. */
+
+	*pxTopOfStack = 0x11;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack--;
+
+	/* Simulate how the stack would look after a call to vPortYield() generated by 
+	the compiler. */
+
+	/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+
+	/* The start of the task code will be popped off the stack last, so place
+	it on first. */
+	usAddress = ( uint16_t ) pxCode;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+	usAddress >>= 8;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+	/* Next simulate the stack as if after a call to portSAVE_CONTEXT().  
+	portSAVE_CONTEXT places the flags on the stack immediately after r0
+	to ensure the interrupts get disabled as soon as possible, and so ensuring
+	the stack use is minimal should a context switch interrupt occur. */
+	*pxTopOfStack = ( StackType_t ) 0x00;	/* R0 */
+	pxTopOfStack--;
+	*pxTopOfStack = portFLAGS_INT_ENABLED;
+	pxTopOfStack--;
+
+
+	/* Now the remaining registers.   The compiler expects R1 to be 0. */
+	*pxTopOfStack = ( StackType_t ) 0x00;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x02;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x05;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x13;	/* R13 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x14;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x15;	/* R15 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x16;	/* R16 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x17;	/* R17 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x18;	/* R18 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x19;	/* R19 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x20;	/* R20 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x21;	/* R21 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x22;	/* R22 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x23;	/* R23 */
+	pxTopOfStack--;
+
+	/* Place the parameter on the stack in the expected location. */
+	usAddress = ( uint16_t ) pvParameters;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+	usAddress >>= 8;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x26;	/* R26 X */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x27;	/* R27 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x28;	/* R28 Y */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x29;	/* R29 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x30;	/* R30 Z */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x031;	/* R31 */
+	pxTopOfStack--;
+
+	/*lint +e950 +e611 +e923 */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run. */
+	portRESTORE_CONTEXT();
+
+	/* Simulate a function call end as generated by the compiler.  We will now
+	jump to the start of the task the context of which we have just restored. */
+	asm volatile ( "ret" );
+
+	/* Should not get here. */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the AVR port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch.  The first thing we do is save the registers so we
+ * can use a naked attribute.
+ */
+void vPortYield( void ) __attribute__ ( ( naked ) );
+void vPortYield( void )
+{
+	portSAVE_CONTEXT();
+	vTaskSwitchContext();
+	portRESTORE_CONTEXT();
+
+	asm volatile ( "ret" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Context switch function used by the tick.  This must be identical to 
+ * vPortYield() from the call to vTaskSwitchContext() onwards.  The only
+ * difference from vPortYield() is the tick count is incremented as the
+ * call comes from the tick ISR.
+ */
+void vPortYieldFromTick( void ) __attribute__ ( ( naked ) );
+void vPortYieldFromTick( void )
+{
+	portSAVE_CONTEXT();
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		vTaskSwitchContext();
+	}
+	portRESTORE_CONTEXT();
+
+	asm volatile ( "ret" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup timer 1 compare match A to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+uint8_t ucHighByte, ucLowByte;
+
+	/* Using 16bit timer 1 to generate the tick.  Correct fuses must be
+	selected for the configCPU_CLOCK_HZ clock. */
+
+	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+	/* We only have 16 bits so have to scale to get our required tick rate. */
+	ulCompareMatch /= portCLOCK_PRESCALER;
+
+	/* Adjust for correct value. */
+	ulCompareMatch -= ( uint32_t ) 1;
+
+	/* Setup compare match value for compare match A.  Interrupts are disabled 
+	before this is called so we need not worry here. */
+	ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+	ulCompareMatch >>= 8;
+	ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+	OCR1AH = ucHighByte;
+	OCR1AL = ucLowByte;
+
+	/* Setup clock source and compare match behaviour. */
+	ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64;
+	TCCR1B = ucLowByte;
+
+	/* Enable the interrupt - this is okay as interrupt are currently globally
+	disabled. */
+	ucLowByte = TIMSK;
+	ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
+	TIMSK = ucLowByte;
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 1
+
+	/*
+	 * Tick ISR for preemptive scheduler.  We can use a naked attribute as
+	 * the context is saved at the start of vPortYieldFromTick().  The tick
+	 * count is incremented after the context is saved.
+	 */
+	void TIMER1_COMPA_vect( void ) __attribute__ ( ( signal, naked ) );
+	void TIMER1_COMPA_vect( void )
+	{
+		vPortYieldFromTick();
+		asm volatile ( "reti" );
+	}
+#else
+
+	/*
+	 * Tick ISR for the cooperative scheduler.  All this does is increment the
+	 * tick count.  We don't need to switch context, this can only be done by
+	 * manual calls to taskYIELD();
+	 */
+	void TIMER1_COMPA_vect( void ) __attribute__ ( ( signal ) );
+	void TIMER1_COMPA_vect( void )
+	{
+		xTaskIncrementTick();
+	}
+#endif
+
+
+	
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ATMega323/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ATMega323/portmacro.h
new file mode 100644
index 0000000..482fc8e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ATMega323/portmacro.h
@@ -0,0 +1,107 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V1.2.3
+
+	+ portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it
+	  base 16.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint8_t
+#define portBASE_TYPE	char
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portENTER_CRITICAL()		asm volatile ( "in		__tmp_reg__, __SREG__" :: );	\
+									asm volatile ( "cli" :: );								\
+									asm volatile ( "push	__tmp_reg__" :: )
+
+#define portEXIT_CRITICAL()			asm volatile ( "pop		__tmp_reg__" :: );				\
+									asm volatile ( "out		__SREG__, __tmp_reg__" :: )
+
+#define portDISABLE_INTERRUPTS()	asm volatile ( "cli" :: );
+#define portENABLE_INTERRUPTS()		asm volatile ( "sei" :: );
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			1
+#define portNOP()					asm volatile ( "nop" );
+/*-----------------------------------------------------------*/
+
+/* Kernel utilities. */
+extern void vPortYield( void ) __attribute__ ( ( naked ) );
+#define portYIELD()					vPortYield()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR32_UC3/exception.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR32_UC3/exception.S
new file mode 100644
index 0000000..79cca31
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR32_UC3/exception.S
@@ -0,0 +1,298 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Exception and interrupt vectors.
+ *
+ * This file maps all events supported by an AVR32UC.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32UC devices with an INTC module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation (Now Microchip):
+ *                                        https://www.microchip.com \n
+ *                       Support and FAQ: https://www.microchip.com/support/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include <avr32/io.h>
+#include "intc.h"
+
+
+//! @{
+//! \verbatim
+
+
+  .section  .exception, "ax", @progbits
+
+
+// Start of Exception Vector Table.
+
+  // EVBA must be aligned with a power of two strictly greater than the EVBA-
+  // relative offset of the last vector.
+  .balign 0x200
+
+  // Export symbol.
+  .global _evba
+  .type _evba, @function
+_evba:
+
+        .org  0x000
+        // Unrecoverable Exception.
+_handle_Unrecoverable_Exception:
+        rjmp $
+
+        .org  0x004
+        // TLB Multiple Hit: UNUSED IN AVR32UC.
+_handle_TLB_Multiple_Hit:
+        rjmp $
+
+        .org  0x008
+        // Bus Error Data Fetch.
+_handle_Bus_Error_Data_Fetch:
+        rjmp $
+
+        .org  0x00C
+         // Bus Error Instruction Fetch.
+_handle_Bus_Error_Instruction_Fetch:
+        rjmp $
+
+        .org  0x010
+        // NMI.
+_handle_NMI:
+        rjmp $
+
+        .org  0x014
+        // Instruction Address.
+_handle_Instruction_Address:
+        rjmp $
+
+        .org  0x018
+        // ITLB Protection.
+_handle_ITLB_Protection:
+        rjmp $
+
+        .org  0x01C
+        // Breakpoint.
+_handle_Breakpoint:
+        rjmp $
+
+        .org  0x020
+        // Illegal Opcode.
+_handle_Illegal_Opcode:
+        rjmp $
+
+        .org  0x024
+        // Unimplemented Instruction.
+_handle_Unimplemented_Instruction:
+        rjmp $
+
+        .org  0x028
+        // Privilege Violation.
+_handle_Privilege_Violation:
+        rjmp $
+
+        .org  0x02C
+        // Floating-Point: UNUSED IN AVR32UC.
+_handle_Floating_Point:
+        rjmp $
+
+        .org  0x030
+        // Coprocessor Absent: UNUSED IN AVR32UC.
+_handle_Coprocessor_Absent:
+        rjmp $
+
+        .org  0x034
+        // Data Address (Read).
+_handle_Data_Address_Read:
+        rjmp $
+
+        .org  0x038
+        // Data Address (Write).
+_handle_Data_Address_Write:
+        rjmp $
+
+        .org  0x03C
+        // DTLB Protection (Read).
+_handle_DTLB_Protection_Read:
+        rjmp $
+
+        .org  0x040
+        // DTLB Protection (Write).
+_handle_DTLB_Protection_Write:
+        rjmp $
+
+        .org  0x044
+        // DTLB Modified: UNUSED IN AVR32UC.
+_handle_DTLB_Modified:
+        rjmp $
+
+        .org  0x050
+        // ITLB Miss: UNUSED IN AVR32UC.
+_handle_ITLB_Miss:
+        rjmp $
+
+        .org  0x060
+        // DTLB Miss (Read): UNUSED IN AVR32UC.
+_handle_DTLB_Miss_Read:
+        rjmp $
+
+        .org  0x070
+        // DTLB Miss (Write): UNUSED IN AVR32UC.
+_handle_DTLB_Miss_Write:
+        rjmp $
+
+        .org  0x100
+        // Supervisor Call.
+_handle_Supervisor_Call:
+        lda.w   pc, SCALLYield
+
+
+// Interrupt support.
+// The interrupt controller must provide the offset address relative to EVBA.
+// Important note:
+//   All interrupts call a C function named _get_interrupt_handler.
+//   This function will read group and interrupt line number to then return in
+//   R12 a pointer to a user-provided interrupt handler.
+
+  .balign 4
+
+_int0:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 0b110
+  brlo    _int0_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int0_normal:
+#endif
+  mov     r12, 0  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  call    _get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int1:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 0b110
+  brlo    _int1_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int1_normal:
+#endif
+  mov     r12, 1  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  call    _get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int2:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 0b110
+  brlo    _int2_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int2_normal:
+#endif
+  mov     r12, 2  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  call    _get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int3:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 0b110
+  brlo    _int3_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int3_normal:
+#endif
+  mov     r12, 3  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  call    _get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+
+// Constant data area.
+
+  .balign 4
+
+  // Values to store in the interrupt priority registers for the various interrupt priority levels.
+  // The interrupt priority registers contain the interrupt priority level and
+  // the EVBA-relative interrupt vector offset.
+  .global ipr_val
+  .type ipr_val, @object
+ipr_val:
+  .word (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\
+        (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\
+        (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\
+        (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba)
+
+
+//! \endverbatim
+//! @}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR32_UC3/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR32_UC3/port.c
new file mode 100644
index 0000000..0603c91
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR32_UC3/port.c
@@ -0,0 +1,436 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS port source for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation (Now Microchip):
+ *                                        https://www.microchip.com \n
+ *                       Support and FAQ: https://www.microchip.com/support/
+ *
+ *****************************************************************************/
+
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/* Standard includes. */
+#include <sys/cpu.h>
+#include <sys/usart.h>
+#include <malloc.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* AVR32 UC3 includes. */
+#include <avr32/io.h>
+#include "gpio.h"
+#if( configTICK_USE_TC==1 )
+	#include "tc.h"
+#endif
+
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SR            ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
+#define portINSTRUCTION_SIZE      ( ( StackType_t ) 0 )
+
+/* Each task maintains its own critical nesting variable. */
+#define portNO_CRITICAL_NESTING   ( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+#if( configTICK_USE_TC==0 )
+	static void prvScheduleNextTick( void );
+#else
+	static void prvClearTcInt( void );
+#endif
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Low-level initialization routine called during startup, before the main
+ * function.
+ * This version comes in replacement to the default one provided by Newlib.
+ * Newlib's _init_startup only calls init_exceptions, but Newlib's exception
+ * vectors are not compatible with the SCALL management in the current FreeRTOS
+ * port. More low-level initializations are besides added here.
+ */
+void _init_startup(void)
+{
+	/* Import the Exception Vector Base Address. */
+	extern void _evba;
+
+	#if configHEAP_INIT
+		extern void __heap_start__;
+		extern void __heap_end__;
+		BaseType_t *pxMem;
+	#endif
+
+	/* Load the Exception Vector Base Address in the corresponding system register. */
+	Set_system_register( AVR32_EVBA, ( int ) &_evba );
+
+	/* Enable exceptions. */
+	ENABLE_ALL_EXCEPTIONS();
+
+	/* Initialize interrupt handling. */
+	INTC_init_interrupts();
+
+	#if configHEAP_INIT
+
+		/* Initialize the heap used by malloc. */
+		for( pxMem = &__heap_start__; pxMem < ( BaseType_t * )&__heap_end__; )
+		{
+			*pxMem++ = 0xA5A5A5A5;
+		}
+
+	#endif
+
+	/* Give the used CPU clock frequency to Newlib, so it can work properly. */
+	set_cpu_hz( configCPU_CLOCK_HZ );
+
+	/* Code section present if and only if the debug trace is activated. */
+	#if configDBG
+	{
+		static const gpio_map_t DBG_USART_GPIO_MAP =
+		{
+			{ configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
+			{ configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
+		};
+
+		/* Initialize the USART used for the debug trace with the configured parameters. */
+		set_usart_base( ( void * ) configDBG_USART );
+		gpio_enable_module( DBG_USART_GPIO_MAP,
+		                    sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
+		usart_init( configDBG_USART_BAUDRATE );
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * malloc, realloc and free are meant to be called through respectively
+ * pvPortMalloc, pvPortRealloc and vPortFree.
+ * The latter functions call the former ones from within sections where tasks
+ * are suspended, so the latter functions are task-safe. __malloc_lock and
+ * __malloc_unlock use the same mechanism to also keep the former functions
+ * task-safe as they may be called directly from Newlib's functions.
+ * However, all these functions are interrupt-unsafe and SHALL THEREFORE NOT BE
+ * CALLED FROM WITHIN AN INTERRUPT, because __malloc_lock and __malloc_unlock do
+ * not call portENTER_CRITICAL and portEXIT_CRITICAL in order not to disable
+ * interrupts during memory allocation management as this may be a very time-
+ * consuming process.
+ */
+
+/*
+ * Lock routine called by Newlib on malloc / realloc / free entry to guarantee a
+ * safe section as memory allocation management uses global data.
+ * See the aforementioned details.
+ */
+void __malloc_lock(struct _reent *ptr)
+{
+	vTaskSuspendAll();
+}
+
+/*
+ * Unlock routine called by Newlib on malloc / realloc / free exit to guarantee
+ * a safe section as memory allocation management uses global data.
+ * See the aforementioned details.
+ */
+void __malloc_unlock(struct _reent *ptr)
+{
+	xTaskResumeAll();
+}
+/*-----------------------------------------------------------*/
+
+/* Added as there is no such function in FreeRTOS. */
+void *pvPortRealloc( void *pv, size_t xWantedSize )
+{
+void *pvReturn;
+
+	vTaskSuspendAll();
+	{
+		pvReturn = realloc( pv, xWantedSize );
+	}
+	xTaskResumeAll();
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+/* The cooperative scheduler requires a normal IRQ service routine to
+simply increment the system tick. */
+/* The preemptive scheduler is defined as "naked" as the full context is saved
+on entry as part of the context switch. */
+__attribute__((__naked__)) static void vTick( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT_OS_INT();
+
+	#if( configTICK_USE_TC==1 )
+		/* Clear the interrupt flag. */
+		prvClearTcInt();
+	#else
+		/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
+		clock cycles from now. */
+		prvScheduleNextTick();
+	#endif
+
+	/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
+	calls in a critical section . */
+	portENTER_CRITICAL();
+		xTaskIncrementTick();
+	portEXIT_CRITICAL();
+
+	/* Restore the context of the "elected task". */
+	portRESTORE_CONTEXT_OS_INT();
+}
+/*-----------------------------------------------------------*/
+
+__attribute__((__naked__)) void SCALLYield( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT_SCALL();
+	vTaskSwitchContext();
+	portRESTORE_CONTEXT_SCALL();
+}
+/*-----------------------------------------------------------*/
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels.  The interrupt flags can therefore not always
+be saved to the stack.  Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+__attribute__((__noinline__)) void vPortEnterCritical( void )
+{
+	/* Disable interrupts */
+	portDISABLE_INTERRUPTS();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	 directly.  Increment ulCriticalNesting to keep a count of how many times
+	 portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+__attribute__((__noinline__)) void vPortExitCritical( void )
+{
+	if(ulCriticalNesting > portNO_CRITICAL_NESTING)
+	{
+		ulCriticalNesting--;
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable all interrupt/exception. */
+			portENABLE_INTERRUPTS();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* When the task starts, it will expect to find the function parameter in R12. */
+	pxTopOfStack--;
+	*pxTopOfStack-- = ( StackType_t ) 0x08080808;					/* R8 */
+	*pxTopOfStack-- = ( StackType_t ) 0x09090909;					/* R9 */
+	*pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A;					/* R10 */
+	*pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B;					/* R11 */
+	*pxTopOfStack-- = ( StackType_t ) pvParameters;					/* R12 */
+	*pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF;					/* R14/LR */
+	*pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
+	*pxTopOfStack-- = ( StackType_t ) portINITIAL_SR;				/* SR */
+	*pxTopOfStack-- = ( StackType_t ) 0xFF0000FF;					/* R0 */
+	*pxTopOfStack-- = ( StackType_t ) 0x01010101;					/* R1 */
+	*pxTopOfStack-- = ( StackType_t ) 0x02020202;					/* R2 */
+	*pxTopOfStack-- = ( StackType_t ) 0x03030303;					/* R3 */
+	*pxTopOfStack-- = ( StackType_t ) 0x04040404;					/* R4 */
+	*pxTopOfStack-- = ( StackType_t ) 0x05050505;					/* R5 */
+	*pxTopOfStack-- = ( StackType_t ) 0x06060606;					/* R6 */
+	*pxTopOfStack-- = ( StackType_t ) 0x07070707;					/* R7 */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING;			/* ulCriticalNesting */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	portRESTORE_CONTEXT();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the AVR32 port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
+clock cycles from now. */
+#if( configTICK_USE_TC==0 )
+	static void prvScheduleFirstTick(void)
+	{
+		uint32_t lCycles;
+
+		lCycles = Get_system_register(AVR32_COUNT);
+		lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+		// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
+		// generation feature does not get disabled.
+		if(0 == lCycles)
+		{
+			lCycles++;
+		}
+		Set_system_register(AVR32_COMPARE, lCycles);
+	}
+	
+	__attribute__((__noinline__)) static void prvScheduleNextTick(void)
+	{
+		uint32_t lCycles, lCount;
+
+		lCycles = Get_system_register(AVR32_COMPARE);
+		lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+		// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
+		// generation feature does not get disabled.
+		if(0 == lCycles)
+		{
+			lCycles++;
+		}
+		lCount = Get_system_register(AVR32_COUNT);
+		if( lCycles < lCount )
+		{		// We missed a tick, recover for the next.
+			lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+		}
+		Set_system_register(AVR32_COMPARE, lCycles);
+	}
+#else
+	__attribute__((__noinline__)) static void prvClearTcInt(void)
+	{
+		AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt(void)
+{
+#if( configTICK_USE_TC==1 )
+
+	volatile avr32_tc_t *tc = &AVR32_TC;
+
+	// Options for waveform genration.
+	tc_waveform_opt_t waveform_opt =
+	{
+	.channel  = configTICK_TC_CHANNEL,             /* Channel selection. */
+
+	.bswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOB. */
+	.beevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOB. */
+	.bcpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOB. */
+	.bcpb     = TC_EVT_EFFECT_NOOP,                /* RB compare effect on TIOB. */
+
+	.aswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOA. */
+	.aeevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOA. */
+	.acpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOA: toggle. */
+	.acpa     = TC_EVT_EFFECT_NOOP,                /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
+
+	.wavsel   = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
+	.enetrg   = FALSE,                             /* External event trigger enable. */
+	.eevt     = 0,                                 /* External event selection. */
+	.eevtedg  = TC_SEL_NO_EDGE,                    /* External event edge selection. */
+	.cpcdis   = FALSE,                             /* Counter disable when RC compare. */
+	.cpcstop  = FALSE,                             /* Counter clock stopped with RC compare. */
+
+	.burst    = FALSE,                             /* Burst signal selection. */
+	.clki     = FALSE,                             /* Clock inversion. */
+	.tcclks   = TC_CLOCK_SOURCE_TC2                /* Internal source clock 2. */
+	};
+
+	tc_interrupt_t tc_interrupt =
+	{
+		.etrgs=0,
+		.ldrbs=0,
+		.ldras=0,
+		.cpcs =1,
+		.cpbs =0,
+		.cpas =0,
+		.lovrs=0,
+		.covfs=0,
+	};
+
+#endif
+
+	/* Disable all interrupt/exception. */
+	portDISABLE_INTERRUPTS();
+
+	/* Register the compare interrupt handler to the interrupt controller and
+	enable the compare interrupt. */
+
+	#if( configTICK_USE_TC==1 )
+	{
+		INTC_register_interrupt(&vTick, configTICK_TC_IRQ, INT0);
+
+		/* Initialize the timer/counter. */
+		tc_init_waveform(tc, &waveform_opt);
+
+		/* Set the compare triggers.
+		Remember TC counter is 16-bits, so counting second is not possible!
+		That's why we configure it to count ms. */
+		tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
+
+		tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
+
+		/* Start the timer/counter. */
+		tc_start(tc, configTICK_TC_CHANNEL);
+	}
+	#else
+	{
+		INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
+		prvScheduleFirstTick();
+	}
+	#endif
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR32_UC3/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR32_UC3/portmacro.h
new file mode 100644
index 0000000..ad26b87
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR32_UC3/portmacro.h
@@ -0,0 +1,668 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS port source for AVR32 UC3.
+ *
+ * - Compiler:           GNU GCC for AVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation (Now Microchip):
+ *                                        https://www.microchip.com \n
+ *                       Support and FAQ: https://www.microchip.com/support/
+ *
+ *****************************************************************************/
+
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+#include <avr32/io.h>
+#include "intc.h"
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#define TASK_DELAY_MS(x)   ( (x)        /portTICK_PERIOD_MS )
+#define TASK_DELAY_S(x)    ( (x)*1000   /portTICK_PERIOD_MS )
+#define TASK_DELAY_MIN(x)  ( (x)*60*1000/portTICK_PERIOD_MS )
+
+#define configTICK_TC_IRQ             ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS      ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    4
+#define portNOP()             {__asm__ __volatile__ ("nop");}
+/*-----------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------*/
+
+/* INTC-specific. */
+#define DISABLE_ALL_EXCEPTIONS()    Disable_global_exception()
+#define ENABLE_ALL_EXCEPTIONS()     Enable_global_exception()
+
+#define DISABLE_ALL_INTERRUPTS()    Disable_global_interrupt()
+#define ENABLE_ALL_INTERRUPTS()     Enable_global_interrupt()
+
+#define DISABLE_INT_LEVEL(int_lev)  Disable_interrupt_level(int_lev)
+#define ENABLE_INT_LEVEL(int_lev)   Enable_interrupt_level(int_lev)
+
+
+/*
+ * Debug trace.
+ * Activated if and only if configDBG is nonzero.
+ * Prints a formatted string to stdout.
+ * The current source file name and line number are output with a colon before
+ * the formatted string.
+ * A carriage return and a linefeed are appended to the output.
+ * stdout is redirected to the USART configured by configDBG_USART.
+ * The parameters are the same as for the standard printf function.
+ * There is no return value.
+ * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
+ * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
+ */
+#if configDBG
+#define portDBG_TRACE(...) \
+{\
+  fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\
+  printf(__VA_ARGS__);\
+  fputs("\r\n", stdout);\
+}
+#else
+#define portDBG_TRACE(...)
+#endif
+
+
+/* Critical section management. */
+#define portDISABLE_INTERRUPTS()  DISABLE_ALL_INTERRUPTS()
+#define portENABLE_INTERRUPTS()   ENABLE_ALL_INTERRUPTS()
+
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()      vPortEnterCritical();
+#define portEXIT_CRITICAL()       vPortExitCritical();
+
+
+/* Added as there is no such function in FreeRTOS. */
+extern void *pvPortRealloc( void *pv, size_t xSize );
+/*-----------------------------------------------------------*/
+
+
+/*=============================================================================================*/
+
+/*
+ * Restore Context for cases other than INTi.
+ */
+#define portRESTORE_CONTEXT()															\
+{																						\
+  extern volatile uint32_t ulCriticalNesting;									\
+  extern volatile void *volatile pxCurrentTCB;											\
+																						\
+  __asm__ __volatile__ (																\
+    /* Set SP to point to new stack */													\
+    "mov     r8, LO(%[pxCurrentTCB])													\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])													\n\t"\
+    "ld.w    r0, r8[0]																	\n\t"\
+    "ld.w    sp, r0[0]																	\n\t"\
+																						\
+    /* Restore ulCriticalNesting variable */											\
+    "ld.w    r0, sp++																	\n\t"\
+    "mov     r8, LO(%[ulCriticalNesting])												\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])												\n\t"\
+    "st.w    r8[0], r0																	\n\t"\
+																						\
+    /* Restore R0..R7 */																\
+    "ldm     sp++, r0-r7																\n\t"\
+    /* R0-R7 should not be used below this line */										\
+    /* Skip PC and SR (will do it at the end) */										\
+    "sub     sp, -2*4																	\n\t"\
+    /* Restore R8..R12 and LR */														\
+    "ldm     sp++, r8-r12, lr															\n\t"\
+    /* Restore SR */																	\
+    "ld.w    r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */					\
+    "mtsr    %[SR], r0																	\n\t"\
+    /* Restore r0 */																	\
+    "ld.w    r0, sp[-9*4]																\n\t"\
+    /* Restore PC */																	\
+    "ld.w    pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */		\
+    :																					\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting),										\
+      [pxCurrentTCB] "i" (&pxCurrentTCB),												\
+      [SR] "i" (AVR32_SR)																\
+  );																					\
+}
+
+
+/*
+ * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
+ * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
+ *
+ * Had to make different versions because registers saved on the system stack
+ * are not the same between INT0..3 exceptions and the scall exception.
+ */
+
+// Task context stack layout:
+  // R8  (*)
+  // R9  (*)
+  // R10 (*)
+  // R11 (*)
+  // R12 (*)
+  // R14/LR (*)
+  // R15/PC (*)
+  // SR (*)
+  // R0
+  // R1
+  // R2
+  // R3
+  // R4
+  // R5
+  // R6
+  // R7
+  // ulCriticalNesting
+// (*) automatically done for INT0..INT3, but not for SCALL
+
+/*
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+#if configUSE_PREEMPTION == 0
+
+/*
+ * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
+ */
+#define portSAVE_CONTEXT_OS_INT()														\
+{																						\
+  /* Save R0..R7 */																		\
+  __asm__ __volatile__ ("stm     --sp, r0-r7");											\
+																						\
+  /* With the cooperative scheduler, as there is no context switch by interrupt, */		\
+  /* there is also no context save. */													\
+}
+
+/*
+ * portRESTORE_CONTEXT_OS_INT() for Tick exception.
+ */
+#define portRESTORE_CONTEXT_OS_INT()													\
+{																						\
+  __asm__ __volatile__ (																\
+    /* Restore R0..R7 */																\
+    "ldm     sp++, r0-r7\n\t"															\
+																						\
+    /* With the cooperative scheduler, as there is no context switch by interrupt, */	\
+    /* there is also no context restore. */												\
+    "rete"																				\
+  );																					\
+}
+
+#else
+
+/*
+ * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
+ */
+#define portSAVE_CONTEXT_OS_INT()																	\
+{																									\
+  extern volatile uint32_t ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  /* When we come here */																			\
+  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */					\
+																									\
+  __asm__ __volatile__ (																			\
+    /* Save R0..R7 */																				\
+    "stm     --sp, r0-r7																			\n\t"\
+																									\
+    /* Save ulCriticalNesting variable  - R0 is overwritten */										\
+    "mov     r8, LO(%[ulCriticalNesting])\n\t"														\
+    "orh     r8, HI(%[ulCriticalNesting])\n\t"														\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "st.w    --sp, r0																				\n\t"\
+																									\
+    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */	\
+    /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
+    /* level and allow other lower interrupt level to occur). */									\
+    /* In this case we don't want to do a task switch because we don't know what the stack */		\
+    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */	\
+    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */		\
+    /* will just be restoring the interrupt handler, no way!!! */									\
+    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */					\
+    "ld.w    r0, sp[9*4]\n\t" /* Read SR in stack */												\
+    "bfextu  r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */									\
+    "cp.w    r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */						\
+    "brhi    LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]													\n\t"\
+																									\
+    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */					\
+    /* NOTE: we don't enter a critical section here because all interrupt handlers */				\
+    /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */							\
+    /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */			\
+    /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */		\
+    "mov     r8, LO(%[pxCurrentTCB])\n\t"															\
+    "orh     r8, HI(%[pxCurrentTCB])\n\t"															\
+    "ld.w    r0, r8[0]\n\t"																			\
+    "st.w    r0[0], sp\n"																			\
+																									\
+    "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:"															\
+    :																								\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting),													\
+      [pxCurrentTCB] "i" (&pxCurrentTCB),															\
+      [LINE] "i" (__LINE__)																			\
+  );																								\
+}
+
+/*
+ * portRESTORE_CONTEXT_OS_INT() for Tick exception.
+ */
+#define portRESTORE_CONTEXT_OS_INT()																\
+{																									\
+  extern volatile uint32_t ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */		\
+  /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
+  /* level and allow other lower interrupt level to occur). */										\
+  /* In this case we don't want to do a task switch because we don't know what the stack */			\
+  /* currently looks like (we don't know what the interrupted interrupt handler was doing). */		\
+  /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */			\
+  /* will just be restoring the interrupt handler, no way!!! */										\
+  __asm__ __volatile__ (																			\
+    "ld.w    r0, sp[9*4]\n\t" /* Read SR in stack */												\
+    "bfextu  r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */									\
+    "cp.w    r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */						\
+    "brhi    LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]"												\
+    :																								\
+    : [LINE] "i" (__LINE__)																			\
+  );																								\
+																									\
+  /* Else */																						\
+  /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */		\
+  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
+  portENTER_CRITICAL();																				\
+  vTaskSwitchContext();																				\
+  portEXIT_CRITICAL();																				\
+																									\
+  /* Restore all registers */																		\
+																									\
+  __asm__ __volatile__ (																			\
+    /* Set SP to point to new stack */																\
+    "mov     r8, LO(%[pxCurrentTCB])																\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])																\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "ld.w    sp, r0[0]																				\n"\
+																									\
+    "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]:														\n\t"\
+																									\
+    /* Restore ulCriticalNesting variable */														\
+    "ld.w    r0, sp++																				\n\t"																			\
+    "mov     r8, LO(%[ulCriticalNesting])															\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])															\n\t"\
+    "st.w    r8[0], r0																				\n\t"\
+																									\
+    /* Restore R0..R7 */																			\
+    "ldm     sp++, r0-r7																			\n\t"\
+																									\
+    /* Now, the stack should be R8..R12, LR, PC and SR */											\
+    "rete"																							\
+    :																								\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting),													\
+      [pxCurrentTCB] "i" (&pxCurrentTCB),															\
+      [LINE] "i" (__LINE__)																			\
+  );																								\
+}
+
+#endif
+
+
+/*
+ * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
+ *
+ * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
+ *
+ */
+#define portSAVE_CONTEXT_SCALL()															\
+{																							\
+  extern volatile uint32_t ulCriticalNesting;										\
+  extern volatile void *volatile pxCurrentTCB;												\
+																							\
+  /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */		\
+  /* If SR[M2:M0] == 001 */																	\
+  /*    PC and SR are on the stack.  */														\
+  /* Else (other modes) */																	\
+  /*    Nothing on the stack. */															\
+																							\
+  /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */		\
+  /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */		\
+  /* in an interrupt|exception handler. */													\
+																							\
+  __asm__ __volatile__ (																	\
+    /* in order to save R0-R7 */															\
+    "sub     sp, 6*4																		\n\t"\
+    /* Save R0..R7 */																		\
+    "stm     --sp, r0-r7																	\n\t"\
+																							\
+    /* in order to save R8-R12 and LR */													\
+    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */			\
+    "sub     r7, sp,-16*4																	\n\t"\
+    /* Copy PC and SR in other places in the stack. */										\
+    "ld.w    r0, r7[-2*4]																	\n\t" /* Read SR */\
+    "st.w    r7[-8*4], r0																	\n\t" /* Copy SR */\
+    "ld.w    r0, r7[-1*4]																	\n\t" /* Read PC */\
+    "st.w    r7[-7*4], r0																	\n\t" /* Copy PC */\
+																							\
+    /* Save R8..R12 and LR on the stack. */													\
+    "stm     --r7, r8-r12, lr																\n\t"\
+																							\
+    /* Arriving here we have the following stack organizations: */							\
+    /* R8..R12, LR, PC, SR, R0..R7. */														\
+																							\
+    /* Now we can finalize the save. */														\
+																							\
+    /* Save ulCriticalNesting variable  - R0 is overwritten */								\
+    "mov     r8, LO(%[ulCriticalNesting])													\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])													\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "st.w    --sp, r0"																		\
+    :																						\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting)											\
+  );																						\
+																							\
+  /* Disable the its which may cause a context switch (i.e. cause a change of */			\
+  /* pxCurrentTCB). */																		\
+  /* Basically, all accesses to the pxCurrentTCB structure should be put in a */			\
+  /* critical section because it is a global structure. */									\
+  portENTER_CRITICAL();																		\
+																							\
+  /* Store SP in the first member of the structure pointed to by pxCurrentTCB */			\
+  __asm__ __volatile__ (																	\
+    "mov     r8, LO(%[pxCurrentTCB])														\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])														\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "st.w    r0[0], sp"																		\
+    :																						\
+    : [pxCurrentTCB] "i" (&pxCurrentTCB)													\
+  );																						\
+}
+
+/*
+ * portRESTORE_CONTEXT() for SupervisorCALL exception.
+ */
+#define portRESTORE_CONTEXT_SCALL()															\
+{																							\
+  extern volatile uint32_t ulCriticalNesting;										\
+  extern volatile void *volatile pxCurrentTCB;												\
+																							\
+  /* Restore all registers */																\
+																							\
+  /* Set SP to point to new stack */														\
+  __asm__ __volatile__ (																	\
+    "mov     r8, LO(%[pxCurrentTCB])														\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])														\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "ld.w    sp, r0[0]"																		\
+    :																						\
+    : [pxCurrentTCB] "i" (&pxCurrentTCB)													\
+  );																						\
+																							\
+  /* Leave pxCurrentTCB variable access critical section */									\
+  portEXIT_CRITICAL();																		\
+																							\
+  __asm__ __volatile__ (																	\
+    /* Restore ulCriticalNesting variable */												\
+    "ld.w    r0, sp++																		\n\t"\
+    "mov     r8, LO(%[ulCriticalNesting])													\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])													\n\t"\
+    "st.w    r8[0], r0																		\n\t"\
+																							\
+    /* skip PC and SR */																	\
+    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */			\
+    "sub     r7, sp, -10*4																	\n\t"\
+    /* Restore r8-r12 and LR */																\
+    "ldm     r7++, r8-r12, lr																\n\t"\
+																							\
+    /* RETS will take care of the extra PC and SR restore. */								\
+    /* So, we have to prepare the stack for this. */										\
+    "ld.w    r0, r7[-8*4]																	\n\t" /* Read SR */\
+    "st.w    r7[-2*4], r0																	\n\t" /* Copy SR */\
+    "ld.w    r0, r7[-7*4]																	\n\t" /* Read PC */\
+    "st.w    r7[-1*4], r0																	\n\t" /* Copy PC */\
+																							\
+    /* Restore R0..R7 */																	\
+    "ldm     sp++, r0-r7																	\n\t"\
+																							\
+    "sub     sp, -6*4																		\n\t"\
+																							\
+    "rets"																					\
+    :																						\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting)											\
+  );																						\
+}
+
+
+/*
+ * The ISR used depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+#if configUSE_PREEMPTION == 0
+
+/*
+ * ISR entry and exit macros.  These are only required if a task switch
+ * is required from the ISR.
+ */
+#define portENTER_SWITCHING_ISR()															\
+{																							\
+  /* Save R0..R7 */																			\
+  __asm__ __volatile__ ("stm     --sp, r0-r7");												\
+																							\
+  /* With the cooperative scheduler, as there is no context switch by interrupt, */			\
+  /* there is also no context save. */														\
+}
+
+/*
+ * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
+ */
+#define portEXIT_SWITCHING_ISR()															\
+{																							\
+  __asm__ __volatile__ (																	\
+    /* Restore R0..R7 */																	\
+    "ldm     sp++, r0-r7																	\n\t"\
+																							\
+    /* With the cooperative scheduler, as there is no context switch by interrupt, */		\
+    /* there is also no context restore. */													\
+    "rete"																					\
+  );																						\
+}
+
+#else
+
+/*
+ * ISR entry and exit macros.  These are only required if a task switch
+ * is required from the ISR.
+ */
+#define portENTER_SWITCHING_ISR()															\
+{																							\
+  extern volatile uint32_t ulCriticalNesting;										\
+  extern volatile void *volatile pxCurrentTCB;												\
+																							\
+  /* When we come here */																	\
+  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */			\
+																							\
+  __asm__ __volatile__ (																	\
+    /* Save R0..R7 */																		\
+    "stm     --sp, r0-r7																	\n\t"\
+																							\
+    /* Save ulCriticalNesting variable  - R0 is overwritten */								\
+    "mov     r8, LO(%[ulCriticalNesting])													\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])													\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "st.w    --sp, r0																		\n\t"\
+																									\
+    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */	\
+    /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
+    /* level and allow other lower interrupt level to occur). */									\
+    /* In this case we don't want to do a task switch because we don't know what the stack */		\
+    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */	\
+    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */		\
+    /* will just be restoring the interrupt handler, no way!!! */									\
+    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */					\
+    "ld.w    r0, sp[9*4]																	\n\t" /* Read SR in stack */\
+    "bfextu  r0, r0, 22, 3																	\n\t" /* Extract the mode bits to R0. */\
+    "cp.w    r0, 1																			\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+    "brhi    LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]											\n\t"\
+																							\
+    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */			\
+    "mov     r8, LO(%[pxCurrentTCB])														\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])														\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "st.w    r0[0], sp																		\n"\
+																							\
+    "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:"													\
+    :																						\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting),											\
+      [pxCurrentTCB] "i" (&pxCurrentTCB),													\
+      [LINE] "i" (__LINE__)																	\
+  );																						\
+}
+
+/*
+ * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
+ */
+#define portEXIT_SWITCHING_ISR()															\
+{																							\
+  extern volatile uint32_t ulCriticalNesting;										\
+  extern volatile void *volatile pxCurrentTCB;												\
+																							\
+  __asm__ __volatile__ (																	\
+    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */		\
+    /* interrupt handler (which was of a higher priority level but decided to lower its priority */		\
+    /* level and allow other lower interrupt level to occur). */										\
+    /* In this case it's of no use to switch context and restore a new SP because we purposedly */		\
+    /* did not previously save SP in its TCB. */																				\
+    "ld.w    r0, sp[9*4]																	\n\t" /* Read SR in stack */\
+    "bfextu  r0, r0, 22, 3																	\n\t" /* Extract the mode bits to R0. */\
+    "cp.w    r0, 1																			\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+    "brhi    LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]											\n\t"\
+																							\
+    /* If a switch is required then we just need to call */									\
+    /* vTaskSwitchContext() as the context has already been */								\
+    /* saved. */																			\
+    "cp.w    r12, 1																			\n\t" /* Check if Switch context is required. */\
+    "brne    LABEL_ISR_RESTORE_CONTEXT_%[LINE]"												\
+    :																						\
+    : [LINE] "i" (__LINE__)																	\
+  );																						\
+																							\
+  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */	\
+  portENTER_CRITICAL();																		\
+  vTaskSwitchContext();																		\
+  portEXIT_CRITICAL();																		\
+																							\
+  __asm__ __volatile__ (																	\
+    "LABEL_ISR_RESTORE_CONTEXT_%[LINE]:														\n\t"\
+    /* Restore the context of which ever task is now the highest */							\
+    /* priority that is ready to run. */													\
+																							\
+    /* Restore all registers */																\
+																							\
+    /* Set SP to point to new stack */														\
+    "mov     r8, LO(%[pxCurrentTCB])														\n\t"\
+    "orh     r8, HI(%[pxCurrentTCB])														\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "ld.w    sp, r0[0]																		\n"\
+																							\
+    "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]:												\n\t"\
+																							\
+    /* Restore ulCriticalNesting variable */												\
+    "ld.w    r0, sp++																		\n\t"\
+    "mov     r8, LO(%[ulCriticalNesting])													\n\t"\
+    "orh     r8, HI(%[ulCriticalNesting])													\n\t"\
+    "st.w    r8[0], r0																		\n\t"\
+																							\
+    /* Restore R0..R7 */																	\
+    "ldm     sp++, r0-r7																	\n\t"\
+																							\
+    /* Now, the stack should be R8..R12, LR, PC and SR  */									\
+    "rete"																					\
+    :																						\
+    : [ulCriticalNesting] "i" (&ulCriticalNesting),											\
+      [pxCurrentTCB] "i" (&pxCurrentTCB),													\
+      [LINE] "i" (__LINE__)																	\
+  );																						\
+}
+
+#endif
+
+
+#define portYIELD()                 {__asm__ __volatile__ ("scall");}
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_AVRDx/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_AVRDx/port.c
new file mode 100644
index 0000000..8bf9474
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_AVRDx/port.c
@@ -0,0 +1,345 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include <stdlib.h>
+
+#include <avr/interrupt.h>
+#include "porthardware.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the AVR port.
+*----------------------------------------------------------*/
+
+/* Start tasks with interrupts enables. */
+#define portFLAGS_INT_ENABLED    ( ( StackType_t ) 0x80 )
+
+/*-----------------------------------------------------------*/
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+ * any details of its type. */
+typedef void RTOS_TCB_t;
+extern volatile RTOS_TCB_t * volatile pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to save all the general purpose registers, the save the stack pointer
+ * into the TCB.
+ *
+ * The first thing we do is save the flags then disable interrupts.  This is to
+ * guard our stack against having a context switch interrupt after we have already
+ * pushed the registers onto the stack - causing the 32 registers to be on the
+ * stack twice.
+ *
+ * r1 is set to zero as the compiler expects it to be thus, however some
+ * of the math routines make use of R1.
+ *
+ * The interrupts will have been disabled during the call to portSAVE_CONTEXT()
+ * so we need not worry about reading/writing to the stack pointer.
+ */
+
+#define portSAVE_CONTEXT()                              \
+    asm volatile ( "push  r0                      \n\t" \
+                   "in    r0, __SREG__            \n\t" \
+                   "cli                           \n\t" \
+                   "push  r0                      \n\t" \
+                   "in    r0, __RAMPZ__           \n\t" \
+                   "push  r0                      \n\t" \
+                   "push  r1                      \n\t" \
+                   "clr   r1                      \n\t" \
+                   "push  r2                      \n\t" \
+                   "push  r3                      \n\t" \
+                   "push  r4                      \n\t" \
+                   "push  r5                      \n\t" \
+                   "push  r6                      \n\t" \
+                   "push  r7                      \n\t" \
+                   "push  r8                      \n\t" \
+                   "push  r9                      \n\t" \
+                   "push  r10                     \n\t" \
+                   "push  r11                     \n\t" \
+                   "push  r12                     \n\t" \
+                   "push  r13                     \n\t" \
+                   "push  r14                     \n\t" \
+                   "push  r15                     \n\t" \
+                   "push  r16                     \n\t" \
+                   "push  r17                     \n\t" \
+                   "push  r18                     \n\t" \
+                   "push  r19                     \n\t" \
+                   "push  r20                     \n\t" \
+                   "push  r21                     \n\t" \
+                   "push  r22                     \n\t" \
+                   "push  r23                     \n\t" \
+                   "push  r24                     \n\t" \
+                   "push  r25                     \n\t" \
+                   "push  r26                     \n\t" \
+                   "push  r27                     \n\t" \
+                   "push  r28                     \n\t" \
+                   "push  r29                     \n\t" \
+                   "push  r30                     \n\t" \
+                   "push  r31                     \n\t" \
+                   "lds   r26, pxCurrentTCB       \n\t" \
+                   "lds   r27, pxCurrentTCB + 1   \n\t" \
+                   "in    r0, __SP_L__            \n\t" \
+                   "st    x+, r0                  \n\t" \
+                   "in    r0, __SP_H__            \n\t" \
+                   "st    x+, r0                  \n\t" );
+
+/*
+ * Opposite to portSAVE_CONTEXT().  Interrupts will have been disabled during
+ * the context save so we can write to the stack pointer.
+ */
+
+#define portRESTORE_CONTEXT()                           \
+    asm volatile ( "lds   r26, pxCurrentTCB       \n\t" \
+                   "lds   r27, pxCurrentTCB + 1   \n\t" \
+                   "ld    r28, x+                 \n\t" \
+                   "out   __SP_L__, r28           \n\t" \
+                   "ld    r29, x+                 \n\t" \
+                   "out   __SP_H__, r29           \n\t" \
+                   "pop   r31                     \n\t" \
+                   "pop   r30                     \n\t" \
+                   "pop   r29                     \n\t" \
+                   "pop   r28                     \n\t" \
+                   "pop   r27                     \n\t" \
+                   "pop   r26                     \n\t" \
+                   "pop   r25                     \n\t" \
+                   "pop   r24                     \n\t" \
+                   "pop   r23                     \n\t" \
+                   "pop   r22                     \n\t" \
+                   "pop   r21                     \n\t" \
+                   "pop   r20                     \n\t" \
+                   "pop   r19                     \n\t" \
+                   "pop   r18                     \n\t" \
+                   "pop   r17                     \n\t" \
+                   "pop   r16                     \n\t" \
+                   "pop   r15                     \n\t" \
+                   "pop   r14                     \n\t" \
+                   "pop   r13                     \n\t" \
+                   "pop   r12                     \n\t" \
+                   "pop   r11                     \n\t" \
+                   "pop   r10                     \n\t" \
+                   "pop   r9                      \n\t" \
+                   "pop   r8                      \n\t" \
+                   "pop   r7                      \n\t" \
+                   "pop   r6                      \n\t" \
+                   "pop   r5                      \n\t" \
+                   "pop   r4                      \n\t" \
+                   "pop   r3                      \n\t" \
+                   "pop   r2                      \n\t" \
+                   "pop   r1                      \n\t" \
+                   "pop   r0                      \n\t" \
+                   "out   __RAMPZ__, r0           \n\t" \
+                   "pop   r0                      \n\t" \
+                   "out   __SREG__, r0            \n\t" \
+                   "pop   r0                      \n\t" );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform hardware setup to enable ticks from timer.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    uint16_t usAddress;
+
+    /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+
+    /* Place a few bytes of known values on the bottom of the stack.
+     * This is just useful for debugging. Uncomment if needed. */
+    /* *pxTopOfStack = 0x11; */
+    /* pxTopOfStack--; */
+    /* *pxTopOfStack = 0x22; */
+    /* pxTopOfStack--; */
+    /* *pxTopOfStack = 0x33; */
+    /* pxTopOfStack--; */
+
+    /* The start of the task code will be popped off the stack last, so place
+     * it on first. */
+    usAddress = ( uint16_t ) pxCode;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
+    *  portSAVE_CONTEXT places the flags on the stack immediately after r0
+    *  to ensure the interrupts get disabled as soon as possible, and so ensuring
+    *  the stack use is minimal should a context switch interrupt occur. */
+    *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
+    pxTopOfStack--;
+    *pxTopOfStack = portFLAGS_INT_ENABLED;
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */
+    pxTopOfStack--;
+
+    /* Now the remaining registers.   The compiler expects R1 to be 0. */
+    *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */
+
+    /* Leave R2 - R23 untouched */
+    pxTopOfStack -= 23;
+
+    /* Place the parameter on the stack in the expected location. */
+    usAddress = ( uint16_t ) pvParameters;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+
+    /* Leave register R26 - R31 untouched */
+    pxTopOfStack -= 7;
+
+    /*lint +e950 +e611 +e923 */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+    /* Setup the hardware to generate the tick. */
+    prvSetupTimerInterrupt();
+
+    /* Restore the context of the first task that is going to run. */
+    portRESTORE_CONTEXT();
+
+    /* Simulate a function call end as generated by the compiler.  We will now
+     * jump to the start of the task the context of which we have just restored. */
+    asm volatile ( "ret" );
+
+    /* Should not get here. */
+    return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* vPortEndScheduler is not implemented in this port. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch.  The first thing we do is save the registers so we
+ * can use a naked attribute.
+ */
+void vPortYield( void ) __attribute__( ( naked ) );
+void vPortYield( void )
+{
+    portSAVE_CONTEXT();
+    vTaskSwitchContext();
+    portRESTORE_CONTEXT();
+    asm volatile ( "ret" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch callable from ISRs. The first thing
+ * we do is save the registers so we can use a naked attribute.
+ */
+void vPortYieldFromISR( void ) __attribute__( ( naked ) );
+void vPortYieldFromISR( void )
+{
+    portSAVE_CONTEXT();
+    vTaskSwitchContext();
+    portRESTORE_CONTEXT();
+    asm volatile ( "reti" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Context switch function used by the tick.  This must be identical to
+ * vPortYield() from the call to vTaskSwitchContext() onwards.  The only
+ * difference from vPortYield() is the tick count is incremented as the
+ * call comes from the tick ISR.
+ */
+void vPortYieldFromTick( void ) __attribute__( ( naked ) );
+void vPortYieldFromTick( void )
+{
+    portSAVE_CONTEXT();
+
+    if( xTaskIncrementTick() != pdFALSE )
+    {
+        vTaskSwitchContext();
+    }
+
+    portRESTORE_CONTEXT();
+
+    asm volatile ( "reti" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup timer to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+    TICK_init();
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 1
+
+/*
+ * Tick ISR for preemptive scheduler.  We can use a naked attribute as
+ * the context is saved at the start of vPortYieldFromTick().  The tick
+ * count is incremented after the context is saved.
+ */
+    ISR( TICK_INT_vect, ISR_NAKED )
+    {
+        /* Clear tick interrupt flag. */
+        CLR_INT( INT_FLAGS, INT_MASK );
+
+        vPortYieldFromTick();
+
+        asm volatile ( "reti" );
+    }
+#else  /* if configUSE_PREEMPTION == 1 */
+
+/*
+ * Tick ISR for the cooperative scheduler.  All this does is increment the
+ * tick count.  We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ */
+    ISR( TICK_INT_vect )
+    {
+        /* Clear tick interrupt flag. */
+        INT_FLAGS = INT_MASK;
+        xTaskIncrementTick();
+    }
+#endif /* if configUSE_PREEMPTION == 1 */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_AVRDx/porthardware.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_AVRDx/porthardware.h
new file mode 100644
index 0000000..7e670d9
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_AVRDx/porthardware.h
@@ -0,0 +1,109 @@
+#ifndef PORTHARDWARE_H
+#define PORTHARDWARE_H
+
+#include "FreeRTOSConfig.h"
+
+/*-----------------------------------------------------------*/
+
+#define CLR_INT( FLAG_REG, FLAG_MASK )                                         \
+    asm volatile (                                                             \
+        "push r16\n\t"                                                         \
+        "ldi r16, %1\n\t"                                                      \
+        "sts %0, r16\n\t"                                                      \
+        "pop r16\n\t"                                                          \
+        :                                                                      \
+        : "i" ( _SFR_MEM_ADDR( FLAG_REG ) ), "i" ( ( uint8_t ) ( FLAG_MASK ) ) \
+        );
+
+#if ( configUSE_TIMER_INSTANCE == 0 )
+
+    #define TICK_INT_vect    TCB0_INT_vect
+    #define INT_FLAGS        TCB0_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB0.INTCTRL = TCB_CAPT_bm;                          \
+        TCB0.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 1 )
+
+    #define TICK_INT_vect    TCB1_INT_vect
+    #define INT_FLAGS        TCB1_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB1.INTCTRL = TCB_CAPT_bm;                          \
+        TCB1.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 2 )
+
+    #define TICK_INT_vect    TCB2_INT_vect
+    #define INT_FLAGS        TCB2_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB2.INTCTRL = TCB_CAPT_bm;                          \
+        TCB2.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 3 )
+
+    #define TICK_INT_vect    TCB3_INT_vect
+    #define INT_FLAGS        TCB3_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB3.INTCTRL = TCB_CAPT_bm;                          \
+        TCB3.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 4 )
+
+    #define TICK_INT_vect    TCB4_INT_vect
+    #define INT_FLAGS        TCB4_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB4.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB4.INTCTRL = TCB_CAPT_bm;                          \
+        TCB4.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 5 )
+
+    #define TICK_INT_vect    RTC_CNT_vect
+    #define INT_FLAGS        RTC_INTFLAGS
+    #define INT_MASK         RTC_OVF_bm
+
+/* Hertz to period for RTC setup */
+    #define RTC_PERIOD_HZ( x )    ( 32768 * ( ( 1.0 / x ) ) )
+    #define TICK_init()                                        \
+    {                                                          \
+        while( RTC.STATUS > 0 ) {; }                           \
+        RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \
+        RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ );         \
+        RTC.INTCTRL |= 1 << RTC_OVF_bp;                        \
+    }
+
+#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */
+    #undef TICK_INT_vect
+    #undef INT_FLAGS
+    #undef INT_MASK
+    #undef TICK_init()
+    #error Invalid timer setting.
+#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */
+
+/*-----------------------------------------------------------*/
+
+#endif /* PORTHARDWARE_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_AVRDx/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_AVRDx/portmacro.h
new file mode 100644
index 0000000..93fa73c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_AVRDx/portmacro.h
@@ -0,0 +1,109 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+/* *INDENT-ON* */
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR                 char
+#define portFLOAT                float
+#define portDOUBLE               double
+#define portLONG                 long
+#define portSHORT                int
+#define portSTACK_TYPE           uint8_t
+#define portBASE_TYPE            char
+
+#define portPOINTER_SIZE_TYPE    uint16_t
+
+typedef portSTACK_TYPE   StackType_t;
+typedef signed char      BaseType_t;
+typedef unsigned char    UBaseType_t;
+
+#if ( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#else
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portENTER_CRITICAL()                     \
+    asm volatile ( "in __tmp_reg__, __SREG__" ); \
+    asm volatile ( "cli" );                      \
+    asm volatile ( "push __tmp_reg__" )
+
+#define portEXIT_CRITICAL()             \
+    asm volatile ( "pop __tmp_reg__" ); \
+    asm volatile ( "out __SREG__, __tmp_reg__" )
+
+#define portDISABLE_INTERRUPTS()    asm volatile ( "cli" ::);
+#define portENABLE_INTERRUPTS()     asm volatile ( "sei" ::);
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    1
+#define portNOP()    asm volatile ( "nop" );
+/*-----------------------------------------------------------*/
+
+/* Kernel utilities. */
+extern void vPortYield( void ) __attribute__( ( naked ) );
+#define portYIELD()             vPortYield()
+
+extern void vPortYieldFromISR( void ) __attribute__( ( naked ) );
+#define portYIELD_FROM_ISR()    vPortYieldFromISR()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+/* *INDENT-OFF* */
+    #ifdef __cplusplus
+        }
+    #endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_Mega0/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_Mega0/port.c
new file mode 100644
index 0000000..2d80384
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_Mega0/port.c
@@ -0,0 +1,339 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include <stdlib.h>
+
+#include <avr/interrupt.h>
+#include "porthardware.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the AVR port.
+*----------------------------------------------------------*/
+
+/* Start tasks with interrupts enables. */
+#define portFLAGS_INT_ENABLED    ( ( StackType_t ) 0x80 )
+
+/*-----------------------------------------------------------*/
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+ * any details of its type. */
+typedef void RTOS_TCB_t;
+extern volatile RTOS_TCB_t * volatile pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to save all the general purpose registers, the save the stack pointer
+ * into the TCB.
+ *
+ * The first thing we do is save the flags then disable interrupts.  This is to
+ * guard our stack against having a context switch interrupt after we have already
+ * pushed the registers onto the stack - causing the 32 registers to be on the
+ * stack twice.
+ *
+ * r1 is set to zero as the compiler expects it to be thus, however some
+ * of the math routines make use of R1.
+ *
+ * The interrupts will have been disabled during the call to portSAVE_CONTEXT()
+ * so we need not worry about reading/writing to the stack pointer.
+ */
+
+#define portSAVE_CONTEXT()                              \
+    asm volatile ( "push  r0                      \n\t" \
+                   "in    r0, __SREG__            \n\t" \
+                   "cli                           \n\t" \
+                   "push  r0                      \n\t" \
+                   "push  r1                      \n\t" \
+                   "clr   r1                      \n\t" \
+                   "push  r2                      \n\t" \
+                   "push  r3                      \n\t" \
+                   "push  r4                      \n\t" \
+                   "push  r5                      \n\t" \
+                   "push  r6                      \n\t" \
+                   "push  r7                      \n\t" \
+                   "push  r8                      \n\t" \
+                   "push  r9                      \n\t" \
+                   "push  r10                     \n\t" \
+                   "push  r11                     \n\t" \
+                   "push  r12                     \n\t" \
+                   "push  r13                     \n\t" \
+                   "push  r14                     \n\t" \
+                   "push  r15                     \n\t" \
+                   "push  r16                     \n\t" \
+                   "push  r17                     \n\t" \
+                   "push  r18                     \n\t" \
+                   "push  r19                     \n\t" \
+                   "push  r20                     \n\t" \
+                   "push  r21                     \n\t" \
+                   "push  r22                     \n\t" \
+                   "push  r23                     \n\t" \
+                   "push  r24                     \n\t" \
+                   "push  r25                     \n\t" \
+                   "push  r26                     \n\t" \
+                   "push  r27                     \n\t" \
+                   "push  r28                     \n\t" \
+                   "push  r29                     \n\t" \
+                   "push  r30                     \n\t" \
+                   "push  r31                     \n\t" \
+                   "lds   r26, pxCurrentTCB       \n\t" \
+                   "lds   r27, pxCurrentTCB + 1   \n\t" \
+                   "in    r0, __SP_L__            \n\t" \
+                   "st    x+, r0                  \n\t" \
+                   "in    r0, __SP_H__            \n\t" \
+                   "st    x+, r0                  \n\t" );
+
+/*
+ * Opposite to portSAVE_CONTEXT().  Interrupts will have been disabled during
+ * the context save so we can write to the stack pointer.
+ */
+
+#define portRESTORE_CONTEXT()                           \
+    asm volatile ( "lds   r26, pxCurrentTCB       \n\t" \
+                   "lds   r27, pxCurrentTCB + 1   \n\t" \
+                   "ld    r28, x+                 \n\t" \
+                   "out   __SP_L__, r28           \n\t" \
+                   "ld    r29, x+                 \n\t" \
+                   "out   __SP_H__, r29           \n\t" \
+                   "pop   r31                     \n\t" \
+                   "pop   r30                     \n\t" \
+                   "pop   r29                     \n\t" \
+                   "pop   r28                     \n\t" \
+                   "pop   r27                     \n\t" \
+                   "pop   r26                     \n\t" \
+                   "pop   r25                     \n\t" \
+                   "pop   r24                     \n\t" \
+                   "pop   r23                     \n\t" \
+                   "pop   r22                     \n\t" \
+                   "pop   r21                     \n\t" \
+                   "pop   r20                     \n\t" \
+                   "pop   r19                     \n\t" \
+                   "pop   r18                     \n\t" \
+                   "pop   r17                     \n\t" \
+                   "pop   r16                     \n\t" \
+                   "pop   r15                     \n\t" \
+                   "pop   r14                     \n\t" \
+                   "pop   r13                     \n\t" \
+                   "pop   r12                     \n\t" \
+                   "pop   r11                     \n\t" \
+                   "pop   r10                     \n\t" \
+                   "pop   r9                      \n\t" \
+                   "pop   r8                      \n\t" \
+                   "pop   r7                      \n\t" \
+                   "pop   r6                      \n\t" \
+                   "pop   r5                      \n\t" \
+                   "pop   r4                      \n\t" \
+                   "pop   r3                      \n\t" \
+                   "pop   r2                      \n\t" \
+                   "pop   r1                      \n\t" \
+                   "pop   r0                      \n\t" \
+                   "out   __SREG__, r0            \n\t" \
+                   "pop   r0                      \n\t" );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform hardware setup to enable ticks from timer.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    uint16_t usAddress;
+
+    /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+
+    /* Place a few bytes of known values on the bottom of the stack.
+     * This is just useful for debugging. Uncomment if needed. */
+    /* *pxTopOfStack = 0x11; */
+    /* pxTopOfStack--; */
+    /* *pxTopOfStack = 0x22; */
+    /* pxTopOfStack--; */
+    /* *pxTopOfStack = 0x33; */
+    /* pxTopOfStack--; */
+
+    /* The start of the task code will be popped off the stack last, so place
+     * it on first. */
+    usAddress = ( uint16_t ) pxCode;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
+    *  portSAVE_CONTEXT places the flags on the stack immediately after r0
+    *  to ensure the interrupts get disabled as soon as possible, and so ensuring
+    *  the stack use is minimal should a context switch interrupt occur. */
+    *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
+    pxTopOfStack--;
+    *pxTopOfStack = portFLAGS_INT_ENABLED;
+    pxTopOfStack--;
+
+    /* Now the remaining registers.   The compiler expects R1 to be 0. */
+    *pxTopOfStack = ( StackType_t ) 0x00; /* R1 */
+
+    /* Leave R2 - R23 untouched */
+    pxTopOfStack -= 23;
+
+    /* Place the parameter on the stack in the expected location. */
+    usAddress = ( uint16_t ) pvParameters;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+
+    /* Leave register R26 - R31 untouched */
+    pxTopOfStack -= 7;
+
+    /*lint +e950 +e611 +e923 */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+    /* Setup the hardware to generate the tick. */
+    prvSetupTimerInterrupt();
+
+    /* Restore the context of the first task that is going to run. */
+    portRESTORE_CONTEXT();
+
+    /* Simulate a function call end as generated by the compiler.  We will now
+     * jump to the start of the task the context of which we have just restored. */
+    asm volatile ( "ret" );
+
+    /* Should not get here. */
+    return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* vPortEndScheduler is not implemented in this port. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch.  The first thing we do is save the registers so we
+ * can use a naked attribute.
+ */
+void vPortYield( void ) __attribute__( ( naked ) );
+void vPortYield( void )
+{
+    portSAVE_CONTEXT();
+    vTaskSwitchContext();
+    portRESTORE_CONTEXT();
+    asm volatile ( "ret" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch callable from ISRs. The first thing
+ * we do is save the registers so we can use a naked attribute.
+ */
+void vPortYieldFromISR( void ) __attribute__( ( naked ) );
+void vPortYieldFromISR( void )
+{
+    portSAVE_CONTEXT();
+    vTaskSwitchContext();
+    portRESTORE_CONTEXT();
+    asm volatile ( "reti" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Context switch function used by the tick.  This must be identical to
+ * vPortYield() from the call to vTaskSwitchContext() onwards.  The only
+ * difference from vPortYield() is the tick count is incremented as the
+ * call comes from the tick ISR.
+ */
+void vPortYieldFromTick( void ) __attribute__( ( naked ) );
+void vPortYieldFromTick( void )
+{
+    portSAVE_CONTEXT();
+
+    if( xTaskIncrementTick() != pdFALSE )
+    {
+        vTaskSwitchContext();
+    }
+
+    portRESTORE_CONTEXT();
+
+    asm volatile ( "reti" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup timer to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+    TICK_init();
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 1
+
+/*
+ * Tick ISR for preemptive scheduler.  We can use a naked attribute as
+ * the context is saved at the start of vPortYieldFromTick().  The tick
+ * count is incremented after the context is saved.
+ */
+    ISR( TICK_INT_vect, ISR_NAKED )
+    {
+        /* Clear tick interrupt flag. */
+        CLR_INT( INT_FLAGS, INT_MASK );
+
+        vPortYieldFromTick();
+
+        asm volatile ( "reti" );
+    }
+#else  /* if configUSE_PREEMPTION == 1 */
+
+/*
+ * Tick ISR for the cooperative scheduler.  All this does is increment the
+ * tick count.  We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ */
+    ISR( TICK_INT_vect )
+    {
+        /* Clear tick interrupt flag. */
+        INT_FLAGS = INT_MASK;
+        xTaskIncrementTick();
+    }
+#endif /* if configUSE_PREEMPTION == 1 */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_Mega0/porthardware.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_Mega0/porthardware.h
new file mode 100644
index 0000000..8d4f1bc
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_Mega0/porthardware.h
@@ -0,0 +1,96 @@
+#ifndef PORTHARDWARE_H
+#define PORTHARDWARE_H
+
+#include "FreeRTOSConfig.h"
+
+/*-----------------------------------------------------------*/
+
+#define CLR_INT( FLAG_REG, FLAG_MASK )                                         \
+    asm volatile (                                                             \
+        "push r16\n\t"                                                         \
+        "ldi r16, %1\n\t"                                                      \
+        "sts %0, r16\n\t"                                                      \
+        "pop r16\n\t"                                                          \
+        :                                                                      \
+        : "i" ( _SFR_MEM_ADDR( FLAG_REG ) ), "i" ( ( uint8_t ) ( FLAG_MASK ) ) \
+        );
+
+#if ( configUSE_TIMER_INSTANCE == 0 )
+
+    #define TICK_INT_vect    TCB0_INT_vect
+    #define INT_FLAGS        TCB0_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB0.INTCTRL = TCB_CAPT_bm;                          \
+        TCB0.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 1 )
+
+    #define TICK_INT_vect    TCB1_INT_vect
+    #define INT_FLAGS        TCB1_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB1.INTCTRL = TCB_CAPT_bm;                          \
+        TCB1.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 2 )
+
+    #define TICK_INT_vect    TCB2_INT_vect
+    #define INT_FLAGS        TCB2_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB2.INTCTRL = TCB_CAPT_bm;                          \
+        TCB2.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 3 )
+
+    #define TICK_INT_vect    TCB3_INT_vect
+    #define INT_FLAGS        TCB3_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB3.INTCTRL = TCB_CAPT_bm;                          \
+        TCB3.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 4 )
+
+    #define TICK_INT_vect    RTC_CNT_vect
+    #define INT_FLAGS        RTC_INTFLAGS
+    #define INT_MASK         RTC_OVF_bm
+
+/* Hertz to period for RTC setup */
+    #define RTC_PERIOD_HZ( x )    ( 32768 * ( ( 1.0 / x ) ) )
+    #define TICK_init()                                        \
+    {                                                          \
+        while( RTC.STATUS > 0 ) {; }                           \
+        RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \
+        RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ );         \
+        RTC.INTCTRL |= 1 << RTC_OVF_bp;                        \
+    }
+
+#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */
+    #undef TICK_INT_vect
+    #undef INT_FLAGS
+    #undef INT_MASK
+    #undef TICK_init()
+    #error Invalid timer setting.
+#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */
+
+/*-----------------------------------------------------------*/
+
+#endif /* PORTHARDWARE_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_Mega0/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_Mega0/portmacro.h
new file mode 100644
index 0000000..1181d71
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/AVR_Mega0/portmacro.h
@@ -0,0 +1,109 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR                 char
+#define portFLOAT                float
+#define portDOUBLE               double
+#define portLONG                 long
+#define portSHORT                int
+#define portSTACK_TYPE           uint8_t
+#define portBASE_TYPE            char
+
+#define portPOINTER_SIZE_TYPE    uint16_t
+
+typedef portSTACK_TYPE   StackType_t;
+typedef signed char      BaseType_t;
+typedef unsigned char    UBaseType_t;
+
+#if ( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#else
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portENTER_CRITICAL()                     \
+    asm volatile ( "in __tmp_reg__, __SREG__" ); \
+    asm volatile ( "cli" );                      \
+    asm volatile ( "push __tmp_reg__" )
+
+#define portEXIT_CRITICAL()             \
+    asm volatile ( "pop __tmp_reg__" ); \
+    asm volatile ( "out __SREG__, __tmp_reg__" )
+
+#define portDISABLE_INTERRUPTS()    asm volatile ( "cli" ::);
+#define portENABLE_INTERRUPTS()     asm volatile ( "sei" ::);
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    1
+#define portNOP()    asm volatile ( "nop" );
+/*-----------------------------------------------------------*/
+
+/* Kernel utilities. */
+extern void vPortYield( void ) __attribute__( ( naked ) );
+#define portYIELD()             vPortYield()
+
+extern void vPortYieldFromISR( void ) __attribute__( ( naked ) );
+#define portYIELD_FROM_ISR()    vPortYieldFromISR()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/CORTUS_APS3/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/CORTUS_APS3/port.c
new file mode 100644
index 0000000..04ff764
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/CORTUS_APS3/port.c
@@ -0,0 +1,145 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Machine includes */
+#include <machine/counter.h>
+#include <machine/ic.h>
+/*-----------------------------------------------------------*/
+
+/* The initial PSR has the Previous Interrupt Enabled (PIEN) flag set. */
+#define portINITIAL_PSR			( 0x00020000 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform any hardware configuration necessary to generate the tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Make space on the stack for the context - this leaves a couple of spaces
+	empty.  */
+	pxTopOfStack -= 20;
+
+	/* Fill the registers with known values to assist debugging. */
+	pxTopOfStack[ 16 ] = 0;
+	pxTopOfStack[ 15 ] = portINITIAL_PSR;
+	pxTopOfStack[ 14 ] = ( uint32_t ) pxCode;
+	pxTopOfStack[ 13 ] = 0x00000000UL; /* R15. */
+	pxTopOfStack[ 12 ] = 0x00000000UL; /* R14. */
+	pxTopOfStack[ 11 ] = 0x0d0d0d0dUL;
+	pxTopOfStack[ 10 ] = 0x0c0c0c0cUL;
+	pxTopOfStack[ 9 ] = 0x0b0b0b0bUL;
+	pxTopOfStack[ 8 ] = 0x0a0a0a0aUL;
+	pxTopOfStack[ 7 ] = 0x09090909UL;
+	pxTopOfStack[ 6 ] = 0x08080808UL;
+	pxTopOfStack[ 5 ] = 0x07070707UL;
+	pxTopOfStack[ 4 ] = 0x06060606UL;
+	pxTopOfStack[ 3 ] = 0x05050505UL;
+	pxTopOfStack[ 2 ] = 0x04040404UL;
+	pxTopOfStack[ 1 ] = 0x03030303UL;
+	pxTopOfStack[ 0 ] = ( uint32_t ) pvParameters;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Set-up the timer interrupt. */
+	prvSetupTimerInterrupt();
+
+	/* Integrated Interrupt Controller: Enable all interrupts. */
+	ic->ien = 1;
+
+	/* Restore callee saved registers. */
+	portRESTORE_CONTEXT();
+
+	/* Should not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	/* Enable timer interrupts */
+	counter1->reload = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1;
+	counter1->value = counter1->reload;
+	counter1->mask = 1;
+
+	/* Set the IRQ Handler priority and enable it. */
+	irq[ IRQ_COUNTER1 ].ien = 1;
+}
+/*-----------------------------------------------------------*/
+
+/* Trap 31 handler. */
+void interrupt31_handler( void ) __attribute__((naked));
+void interrupt31_handler( void )
+{
+	portSAVE_CONTEXT();
+	__asm volatile ( "call vTaskSwitchContext" );
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTick( void ) __attribute__((noinline));
+static void prvProcessTick( void )
+{
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		vTaskSwitchContext();
+	}
+		
+	/* Clear the Tick Interrupt. */
+	counter1->expired = 0;
+}
+/*-----------------------------------------------------------*/
+
+/* Timer 1 interrupt handler, used for tick interrupt. */
+void interrupt7_handler( void ) __attribute__((naked));
+void interrupt7_handler( void )
+{
+	portSAVE_CONTEXT();
+	prvProcessTick();
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Nothing to do. Unlikely to want to end. */
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/CORTUS_APS3/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/CORTUS_APS3/portmacro.h
new file mode 100644
index 0000000..f0ac6b0
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/CORTUS_APS3/portmacro.h
@@ -0,0 +1,152 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <machine/cpu.h>
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH							( -1 )
+#define portTICK_PERIOD_MS							( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT							4
+#define portNOP()									__asm__ volatile ( "mov r0, r0" )
+#define portCRITICAL_NESTING_IN_TCB					1
+#define portIRQ_TRAP_YIELD							31
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+extern void vPortYield( void );
+
+/*---------------------------------------------------------------------------*/
+
+#define portYIELD()		asm __volatile__( " trap #%0 "::"i"(portIRQ_TRAP_YIELD):"memory")
+/*---------------------------------------------------------------------------*/
+
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()		vTaskEnterCritical()
+#define portEXIT_CRITICAL()			vTaskExitCritical()
+/*---------------------------------------------------------------------------*/
+
+/* Critical section management. */
+#define portDISABLE_INTERRUPTS() 	cpu_int_disable()
+#define portENABLE_INTERRUPTS() 	cpu_int_enable()
+
+/*---------------------------------------------------------------------------*/
+
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext()
+
+/*---------------------------------------------------------------------------*/
+
+#define portSAVE_CONTEXT()				\
+	asm __volatile__																								\
+	(																												\
+		"sub	r1, #68					\n" /* Make space on the stack for the context. */							\
+		"std	r2, [r1] + 	0			\n"																			\
+		"stq	r4, [r1] +	8			\n"																			\
+		"stq	r8, [r1] +	24			\n"																			\
+		"stq	r12, [r1] +	40			\n"																			\
+		"mov	r6, rtt					\n"																			\
+		"mov	r7, psr					\n"																			\
+		"std	r6, [r1] +	56			\n"																			\
+		"movhi	r2, #16384				\n"	/* Set the pointer to the IC. */										\
+		"ldub	r3, [r2] + 2			\n"	/* Load the current interrupt mask. */									\
+		"st		r3, [r1]+ 64			\n"	/* Store the interrupt mask on the stack. */ 							\
+		"ld		r2, [r0]+short(pxCurrentTCB)	\n"	/* Load the pointer to the TCB. */								\
+		"st		r1, [r2]				\n"	/* Save the stack pointer into the TCB. */								\
+		"mov	r14, r1					\n"	/* Compiler expects r14 to be set to the function stack. */				\
+	);
+/*---------------------------------------------------------------------------*/
+
+#define portRESTORE_CONTEXT()																						\
+	asm __volatile__(																								\
+		"ld		r2, [r0]+short(pxCurrentTCB)	\n"	/* Load the TCB to find the stack pointer and context. */		\
+		"ld		r1, [r2]				\n"																			\
+		"movhi	r2, #16384				\n"	/* Set the pointer to the IC. */										\
+		"ld		r3, [r1] + 64			\n"	/* Load the previous interrupt mask. */									\
+		"stb	r3, [r2] + 2  			\n"	/* Set the current interrupt mask to be the previous. */				\
+		"ldd	r6, [r1] + 56			\n"	/* Restore context. */													\
+		"mov	rtt, r6					\n"																			\
+		"mov	psr, r7					\n"																			\
+		"ldd	r2, [r1] + 0			\n"																			\
+		"ldq	r4, [r1] +	8			\n"																			\
+		"ldq	r8, [r1] +	24			\n"																			\
+		"ldq	r12, [r1] +	40			\n"																			\
+		"add	r1, #68					\n"																			\
+		"rti							\n"																			\
+	 );
+
+/*---------------------------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*---------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ColdFire_V2/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ColdFire_V2/port.c
new file mode 100644
index 0000000..5c513ee
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ColdFire_V2/port.c
@@ -0,0 +1,134 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#define portINITIAL_FORMAT_VECTOR		( ( StackType_t ) 0x4000 )
+
+/* Supervisor mode set. */
+#define portINITIAL_STATUS_REGISTER		( ( StackType_t ) 0x2000)
+
+/* Used to keep track of the number of nested calls to taskENTER_CRITICAL().  This
+will be set to 0 prior to the first task being started. */
+static uint32_t ulCriticalNesting = 0x9999UL;
+
+/*-----------------------------------------------------------*/
+
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
+	pxTopOfStack--;
+
+	/* Exception stack frame starts with the return address. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
+	pxTopOfStack -= 14; /* A5 to D0. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	ulCriticalNesting = 0UL;
+
+	/* Configure the interrupts used by this port. */
+	vApplicationSetupInterrupts();
+
+	/* Start the first task executing. */
+	vPortStartFirstTask();
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented as there is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	if( ulCriticalNesting == 0UL )
+	{
+		/* Guard against context switches being pended simultaneously with a
+		critical section being entered. */
+		do
+		{
+			portDISABLE_INTERRUPTS();
+			if( MCF_INTC0_INTFRCL == 0UL )
+			{
+				break;
+			}
+
+			portENABLE_INTERRUPTS();
+
+		} while( 1 );
+	}
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	ulCriticalNesting--;
+	if( ulCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortYieldHandler( void )
+{
+uint32_t ulSavedInterruptMask;
+
+	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+		/* Note this will clear all forced interrupts - this is done for speed. */
+		MCF_INTC0_INTFRCL = 0;
+		vTaskSwitchContext();
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+}
+
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ColdFire_V2/portasm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ColdFire_V2/portasm.S
new file mode 100644
index 0000000..e929c62
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ColdFire_V2/portasm.S
@@ -0,0 +1,120 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Purpose: Lowest level routines for all ColdFire processors.
+ *
+ * Notes:
+ * 
+ * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale
+ * supplied source files.
+ */
+
+    .global ulPortSetIPL
+    .global mcf5xxx_wr_cacr
+    .global __cs3_isr_interrupt_80
+    .global vPortStartFirstTask
+
+    .text
+
+.macro portSAVE_CONTEXT
+
+	lea.l		(-60, %sp), %sp
+	movem.l		%d0-%fp, (%sp)
+	move.l		pxCurrentTCB, %a0
+	move.l		%sp, (%a0)
+
+	.endm
+
+.macro portRESTORE_CONTEXT
+
+	move.l		pxCurrentTCB, %a0
+	move.l		(%a0), %sp
+	movem.l		(%sp), %d0-%fp
+	lea.l		%sp@(60), %sp
+	rte
+
+	.endm
+
+/********************************************************************/
+/*
+ * This routines changes the IPL to the value passed into the routine.
+ * It also returns the old IPL value back.
+ * Calling convention from C:
+ *   old_ipl = asm_set_ipl(new_ipl);
+ * For the Diab Data C compiler, it passes return value thru D0.
+ * Note that only the least significant three bits of the passed
+ * value are used.
+ */
+
+ulPortSetIPL:
+    link    A6,#-8
+    movem.l D6-D7,(SP)
+
+    move.w  SR,D7       /* current sr    */
+
+    move.l  D7,D0       /* prepare return value  */
+    andi.l  #0x0700,D0  /* mask out IPL  */
+    lsr.l   #8,D0       /* IPL   */
+
+    move.l  8(A6),D6    /* get argument  */
+    andi.l  #0x07,D6    /* least significant three bits  */
+    lsl.l   #8,D6       /* move over to make mask    */
+
+    andi.l  #0x0000F8FF,D7  /* zero out current IPL  */
+    or.l    D6,D7           /* place new IPL in sr   */
+    move.w  D7,SR
+
+    movem.l (SP),D6-D7
+    lea     8(SP),SP
+    unlk    A6
+    rts
+/********************************************************************/
+
+mcf5xxx_wr_cacr:
+    move.l  4(sp),d0
+    .long   0x4e7b0002  /* movec d0,cacr   */
+    nop
+    rts
+
+/********************************************************************/
+
+/* Yield interrupt. */
+__cs3_isr_interrupt_80:
+	portSAVE_CONTEXT
+	jsr vPortYieldHandler
+	portRESTORE_CONTEXT
+
+/********************************************************************/
+
+
+vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+    .end
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ColdFire_V2/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ColdFire_V2/portmacro.h
new file mode 100644
index 0000000..69f9b4d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/ColdFire_V2/portmacro.h
@@ -0,0 +1,114 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			4
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+uint32_t ulPortSetIPL( uint32_t );
+#define portDISABLE_INTERRUPTS()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portENABLE_INTERRUPTS()		ulPortSetIPL( 0 )
+
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+
+extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+#define portNOP()	asm volatile ( 	"nop" )
+
+/* Note this will overwrite all other bits in the force register, it is done this way for speed. */
+#define portYIELD()			MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#define portEND_SWITCHING_ISR( xSwitchRequired )	if( xSwitchRequired != pdFALSE )	\
+													{									\
+														portYIELD();					\
+													}
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/H8S2329/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/H8S2329/port.c
new file mode 100644
index 0000000..f357a64
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/H8S2329/port.c
@@ -0,0 +1,303 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the H8S port.
+ *----------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------*/
+
+/* When the task starts interrupts should be enabled. */
+#define portINITIAL_CCR			( ( StackType_t ) 0x00 )
+
+/* Hardware specific constants used to generate the RTOS tick from the TPU. */
+#define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( uint8_t ) 0x20 )
+#define portCLOCK_DIV_64				( ( uint8_t ) 0x03 )
+#define portCLOCK_DIV					( ( uint32_t ) 64 )
+#define portTGRA_INTERRUPT_ENABLE		( ( uint8_t ) 0x01 )
+#define portTIMER_CHANNEL				( ( uint8_t ) 0x02 )
+#define portMSTP13						( ( uint16_t ) 0x2000 )
+
+/*
+ * Setup TPU channel one for the RTOS tick at the requested frequency.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The ISR used by portYIELD(). This is installed as a trap handler.
+ */
+void vPortYield( void ) __attribute__ ( ( saveall, interrupt_handler ) );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t ulValue;
+
+	/* This requires an even address. */
+	ulValue = ( uint32_t ) pxTopOfStack;
+	if( ulValue & 1UL )
+	{
+		pxTopOfStack = pxTopOfStack - 1;
+	}
+
+	/* Place a few bytes of known values on the bottom of the stack. 
+	This is just useful for debugging. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0xaa;
+	pxTopOfStack--;
+	*pxTopOfStack = 0xbb;
+	pxTopOfStack--;
+	*pxTopOfStack = 0xcc;
+	pxTopOfStack--;
+	*pxTopOfStack = 0xdd;
+
+	/* The initial stack mimics an interrupt stack.  First there is the program
+	counter (24 bits). */
+	ulValue = ( uint32_t ) pxCode;
+
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+	pxTopOfStack--;
+	ulValue >>= 8UL;
+	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+	pxTopOfStack--;
+	ulValue >>= 8UL;
+	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+
+	/* Followed by the CCR. */	
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_CCR;
+
+	/* Next all the general purpose registers - with the parameters being passed
+	in ER0.  The parameter order must match that used by the compiler when the
+	"saveall" function attribute is used. */
+
+	/* ER6 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66;
+	
+	/* ER0 */
+	ulValue = ( uint32_t ) pvParameters;
+
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+	pxTopOfStack--;
+	ulValue >>= 8UL;
+	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+	pxTopOfStack--;
+	ulValue >>= 8UL;
+	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+	pxTopOfStack--;
+	ulValue >>= 8UL;
+	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
+	
+	/* ER1 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11;
+
+	/* ER2 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22;
+
+	/* ER3 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33;
+
+	/* ER4 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44;
+
+	/* ER5 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void * pxCurrentTCB;
+
+	/* Setup the hardware to generate the tick. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run.  This
+	mirrors the function epilogue code generated by the compiler when the
+	"saveall" function attribute is used. */
+	asm volatile ( 
+					"MOV.L		@_pxCurrentTCB, ER6			\n\t"
+					"MOV.L		@ER6, ER7					\n\t"
+					"LDM.L     	@SP+, (ER4-ER5)				\n\t"
+					"LDM.L     	@SP+, (ER0-ER3)				\n\t"
+					"MOV.L     	@ER7+, ER6					\n\t"
+					"RTE									\n\t"
+				);
+
+	( void ) pxCurrentTCB;
+
+	/* Should not get here. */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the h8 port will get stopped. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch.  This is a trap handler.  The "saveall" function
+ * attribute is used so the context is saved by the compiler prologue.  All
+ * we have to do is save the stack pointer.
+ */
+void vPortYield( void )
+{
+	portSAVE_STACK_POINTER();
+		vTaskSwitchContext();
+	portRESTORE_STACK_POINTER();
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * The interrupt handler installed for the RTOS tick depends on whether the 
+ * preemptive or cooperative scheduler is being used. 
+ */
+#if( configUSE_PREEMPTION == 1 )
+
+	/* 
+	 * The preemptive scheduler is used so the ISR calls vTaskSwitchContext().
+	 * The function prologue saves the context so all we have to do is save
+	 * the stack pointer.
+	 */
+	void vTickISR( void ) __attribute__ ( ( saveall, interrupt_handler ) );
+	void vTickISR( void )
+	{
+		portSAVE_STACK_POINTER();
+		
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			vTaskSwitchContext();
+		}
+
+		/* Clear the interrupt. */
+		TSR1 &= ~0x01;
+
+		portRESTORE_STACK_POINTER();
+	}
+
+#else
+
+	/*
+	 * The cooperative scheduler is being used so all we have to do is 
+	 * periodically increment the tick.  This can just be a normal ISR and
+	 * the "saveall" attribute is not required.
+	 */
+	void vTickISR( void ) __attribute__ ( ( interrupt_handler ) );
+	void vTickISR( void )
+	{
+		xTaskIncrementTick();
+
+		/* Clear the interrupt. */
+		TSR1 &= ~0x01;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup timer 1 compare match to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+const uint32_t ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV;
+
+	/* Turn the module on. */
+	MSTPCR &= ~portMSTP13;
+
+	/* Configure timer 1. */
+	TCR1 = portCLEAR_ON_TGRA_COMPARE_MATCH | portCLOCK_DIV_64;
+
+	/* Configure the compare match value for a tick of configTICK_RATE_HZ. */
+	TGR1A = ulCompareMatch;
+
+	/* Start the timer and enable the interrupt - we can do this here as 
+	interrupts are globally disabled when this function is called. */
+	TIER1 |= portTGRA_INTERRUPT_ENABLE;
+	TSTR |= portTIMER_CHANNEL;
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/H8S2329/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/H8S2329/portmacro.h
new file mode 100644
index 0000000..27159c2
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/H8S2329/portmacro.h
@@ -0,0 +1,138 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint8_t
+#define portBASE_TYPE	char
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			2
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portYIELD()					asm volatile( "TRAPA #0" )
+#define portNOP()					asm volatile( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#define portENABLE_INTERRUPTS()		asm volatile( "ANDC	#0x7F, CCR" );
+#define portDISABLE_INTERRUPTS()	asm volatile( "ORC  #0x80, CCR" );
+
+/* Push the CCR then disable interrupts. */
+#define portENTER_CRITICAL()  		asm volatile( "STC	CCR, @-ER7" ); \
+                               		portDISABLE_INTERRUPTS();
+
+/* Pop the CCR to set the interrupt masking back to its previous state. */
+#define  portEXIT_CRITICAL()    	asm volatile( "LDC  @ER7+, CCR" );
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Context switch macros.  These macros are very simple as the context
+is saved simply by selecting the saveall attribute of the context switch
+interrupt service routines.  These macros save and restore the stack
+pointer to the TCB. */
+
+#define portSAVE_STACK_POINTER()								\
+extern void* pxCurrentTCB;										\
+																\
+	asm volatile(												\
+					"MOV.L	@_pxCurrentTCB, ER5			\n\t" 	\
+					"MOV.L	ER7, @ER5					\n\t"	\
+				);												\
+	( void ) pxCurrentTCB;
+
+
+#define	portRESTORE_STACK_POINTER()								\
+extern void* pxCurrentTCB;										\
+																\
+	asm volatile(												\
+					"MOV.L	@_pxCurrentTCB, ER5			\n\t"	\
+					"MOV.L	@ER5, ER7					\n\t"	\
+				);												\
+	( void ) pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/* Macros to allow a context switch from within an application ISR. */
+
+#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); {
+
+#define portEXIT_SWITCHING_ISR( x )							\
+	if( x )													\
+	{														\
+		extern void vTaskSwitchContext( void );				\
+		vTaskSwitchContext();								\
+	}														\
+	} portRESTORE_STACK_POINTER();
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/HCS12/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/HCS12/port.c
new file mode 100644
index 0000000..78b541a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/HCS12/port.c
@@ -0,0 +1,237 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* GCC/HCS12 port by Jefferson L Smith, 2005 */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Port includes */
+#include <sys/ports_def.h>
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the HCS12 port.
+ *----------------------------------------------------------*/
+
+
+/*
+ * Configure a timer to generate the RTOS tick at the frequency specified 
+ * within FreeRTOSConfig.h.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/* NOTE: Interrupt service routines must be in non-banked memory - as does the
+scheduler startup function. */
+#define ATTR_NEAR	__attribute__((near))
+
+/* Manual context switch function.  This is the SWI ISR. */
+// __attribute__((interrupt))
+void ATTR_NEAR vPortYield( void );
+
+/* Tick context switch function.  This is the timer ISR. */
+// __attribute__((interrupt))
+void ATTR_NEAR vPortTickInterrupt( void );
+
+/* Function in non-banked memory which actually switches to first task. */
+BaseType_t ATTR_NEAR xStartSchedulerNear( void );
+
+/* Calls to portENTER_CRITICAL() can be nested.  When they are nested the 
+critical section should not be left (i.e. interrupts should not be re-enabled)
+until the nesting depth reaches 0.  This variable simply tracks the nesting 
+depth.  Each task maintains it's own critical nesting depth variable so 
+uxCriticalNesting is saved and restored from the task stack during a context
+switch. */
+volatile UBaseType_t uxCriticalNesting = 0x80;  // un-initialized
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro.  In this case the stack as
+	expected by the HCS12 RTI instruction. */
+
+
+	/* The address of the task function is placed in the stack byte at a time. */
+	*pxTopOfStack   = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 );
+	*--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 );
+
+	/* Next are all the registers that form part of the task context. */
+
+	/* Y register */
+	*--pxTopOfStack = ( StackType_t ) 0xff;
+	*--pxTopOfStack = ( StackType_t ) 0xee;
+
+	/* X register */
+	*--pxTopOfStack = ( StackType_t ) 0xdd;
+	*--pxTopOfStack = ( StackType_t ) 0xcc;
+ 
+	/* A register contains parameter high byte. */
+	*--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 );
+
+	/* B register contains parameter low byte. */
+	*--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 );
+
+	/* CCR: Note that when the task starts interrupts will be enabled since
+	"I" bit of CCR is cleared */
+	*--pxTopOfStack = ( StackType_t ) 0x80;		// keeps Stop disabled (MCU default)
+	
+	/* tmp softregs used by GCC. Values right now don't	matter. */
+	__asm("\n\
+		movw _.frame, 2,-%0							\n\
+		movw _.tmp, 2,-%0							\n\
+		movw _.z, 2,-%0								\n\
+		movw _.xy, 2,-%0							\n\
+		;movw _.d2, 2,-%0							\n\
+		;movw _.d1, 2,-%0							\n\
+	": "=A"(pxTopOfStack) : "0"(pxTopOfStack) );
+
+	#ifdef BANKED_MODEL
+		/* The page of the task. */
+		*--pxTopOfStack = 0x30;      // can only directly start in PPAGE 0x30
+	#endif
+	
+	/* The critical nesting depth is initialised with 0 (meaning not in
+	a critical section). */
+	*--pxTopOfStack = ( StackType_t ) 0x00;
+
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the HCS12 port will get stopped. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	/* Enable hardware RTI timer */
+	/* Ignores configTICK_RATE_HZ */
+	RTICTL = 0x50;			// 16 MHz xtal: 976.56 Hz, 1024mS 
+	CRGINT |= 0x80;			// RTIE
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* xPortStartScheduler() does not start the scheduler directly because 
+	the header file containing the xPortStartScheduler() prototype is part 
+	of the common kernel code, and therefore cannot use the CODE_SEG pragma. 
+	Instead it simply calls the locally defined xNearStartScheduler() - 
+	which does use the CODE_SEG pragma. */
+
+	int16_t register d;
+	__asm ("jmp  xStartSchedulerNear		; will never return": "=d"(d));
+	return d;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStartSchedulerNear( void )
+{
+	/* Configure the timer that will generate the RTOS tick.  Interrupts are
+	disabled when this function is called. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task. */
+	portRESTORE_CONTEXT();
+
+	portISR_TAIL();
+
+	/* Should not get here! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Context switch functions.  These are interrupt service routines.
+ */
+
+/*
+ * Manual context switch forced by calling portYIELD().  This is the SWI
+ * handler.
+ */
+void vPortYield( void )
+{
+	portISR_HEAD();
+	/* NOTE: This is the trap routine (swi) although not defined as a trap.
+	   It will fill the stack the same way as an ISR in order to mix preemtion
+	   and cooperative yield. */
+
+	portSAVE_CONTEXT();
+	vTaskSwitchContext();
+	portRESTORE_CONTEXT();
+
+	portISR_TAIL();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * RTOS tick interrupt service routine.  If the cooperative scheduler is 
+ * being used then this simply increments the tick count.  If the 
+ * preemptive scheduler is being used a context switch can occur.
+ */
+void vPortTickInterrupt( void )
+{
+	portISR_HEAD();
+
+	/* Clear tick timer flag */
+	CRGFLG = 0x80;
+
+	#if configUSE_PREEMPTION == 1
+	{
+		/* A context switch might happen so save the context. */
+		portSAVE_CONTEXT();
+
+		/* Increment the tick ... */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is necessary. */
+			vTaskSwitchContext();
+		}
+
+		/* Restore the context of a task - which may be a different task
+		to that interrupted. */
+		portRESTORE_CONTEXT();
+	}
+	#else
+	{
+		xTaskIncrementTick();
+	}
+	#endif
+
+	portISR_TAIL();
+}
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/HCS12/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/HCS12/portmacro.h
new file mode 100644
index 0000000..bbfe2da
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/HCS12/portmacro.h
@@ -0,0 +1,246 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint8_t
+#define portBASE_TYPE	char
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			1
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portYIELD()					__asm( "swi" );
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#define portENABLE_INTERRUPTS()				__asm( "cli" )
+#define portDISABLE_INTERRUPTS()			__asm( "sei" )
+
+/*
+ * Disable interrupts before incrementing the count of critical section nesting.
+ * The nesting count is maintained so we know when interrupts should be
+ * re-enabled.  Once interrupts are disabled the nesting count can be accessed
+ * directly.  Each task maintains its own nesting count.
+ */
+#define portENTER_CRITICAL()  									\
+{																\
+	extern volatile UBaseType_t uxCriticalNesting;	\
+																\
+	portDISABLE_INTERRUPTS();									\
+	uxCriticalNesting++;										\
+}
+
+/*
+ * Interrupts are disabled so we can access the nesting count directly.  If the
+ * nesting is found to be 0 (no nesting) then we are leaving the critical
+ * section and interrupts can be re-enabled.
+ */
+#define  portEXIT_CRITICAL()									\
+{																\
+	extern volatile UBaseType_t uxCriticalNesting;	\
+																\
+	uxCriticalNesting--;										\
+	if( uxCriticalNesting == 0 )								\
+	{															\
+		portENABLE_INTERRUPTS();								\
+	}															\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*
+ * These macros are very simple as the processor automatically saves and
+ * restores its registers as interrupts are entered and exited.  In
+ * addition to the (automatically stacked) registers we also stack the
+ * critical nesting count.  Each task maintains its own critical nesting
+ * count as it is legitimate for a task to yield from within a critical
+ * section.  If the banked memory model is being used then the PPAGE
+ * register is also stored as part of the tasks context.
+ */
+
+#ifdef BANKED_MODEL
+	/*
+	 * Load the stack pointer for the task, then pull the critical nesting
+	 * count and PPAGE register from the stack.  The remains of the
+	 * context are restored by the RTI instruction.
+	 */
+	#define portRESTORE_CONTEXT()							\
+	{										\
+		__asm( "								\n\
+		.globl pxCurrentTCB			; void *			\n\
+		.globl uxCriticalNesting		; char				\n\
+											\n\
+		ldx  pxCurrentTCB							\n\
+		lds  0,x				; Stack				\n\
+											\n\
+		movb 1,sp+,uxCriticalNesting						\n\
+		movb 1,sp+,0x30				; PPAGE				\n\
+		" );									\
+	}
+
+	/*
+	 * By the time this macro is called the processor has already stacked the
+	 * registers.  Simply stack the nesting count and PPAGE value, then save
+	 * the task stack pointer.
+	 */
+	#define portSAVE_CONTEXT()							\
+	{										\
+		__asm( "								\n\
+		.globl pxCurrentTCB			; void *			\n\
+		.globl uxCriticalNesting		; char				\n\
+											\n\
+		movb 0x30, 1,-sp			; PPAGE				\n\
+		movb uxCriticalNesting, 1,-sp						\n\
+											\n\
+		ldx  pxCurrentTCB							\n\
+		sts  0,x				; Stack				\n\
+		" );									\
+	}
+#else
+
+	/*
+	 * These macros are as per the BANKED versions above, but without saving
+	 * and restoring the PPAGE register.
+	 */
+
+	#define portRESTORE_CONTEXT()							\
+	{										\
+		__asm( "								\n\
+		.globl pxCurrentTCB			; void *			\n\
+		.globl uxCriticalNesting		; char				\n\
+											\n\
+		ldx  pxCurrentTCB							\n\
+		lds  0,x				; Stack				\n\
+											\n\
+		movb 1,sp+,uxCriticalNesting						\n\
+		" );									\
+	}
+
+	#define portSAVE_CONTEXT()							\
+	{										\
+		__asm( "								\n\
+		.globl pxCurrentTCB			; void *			\n\
+		.globl uxCriticalNesting		; char				\n\
+											\n\
+		movb uxCriticalNesting, 1,-sp						\n\
+											\n\
+		ldx  pxCurrentTCB							\n\
+		sts  0,x				; Stack				\n\
+		" );									\
+	}
+#endif
+
+/*
+ * Utility macros to save/restore correct software registers for GCC. This is
+ * useful when GCC does not generate appropriate ISR head/tail code.
+ */
+#define portISR_HEAD()									\
+{											\
+		__asm("									\n\
+		movw _.frame, 2,-sp							\n\
+		movw _.tmp, 2,-sp							\n\
+		movw _.z, 2,-sp								\n\
+		movw _.xy, 2,-sp							\n\
+		;movw _.d2, 2,-sp							\n\
+		;movw _.d1, 2,-sp							\n\
+		");									\
+}
+
+#define portISR_TAIL()									\
+{											\
+		__asm("									\n\
+		movw 2,sp+, _.xy							\n\
+		movw 2,sp+, _.z								\n\
+		movw 2,sp+, _.tmp							\n\
+		movw 2,sp+, _.frame							\n\
+		;movw 2,sp+, _.d1							\n\
+		;movw 2,sp+, _.d2							\n\
+		rti									\n\
+		");									\
+}
+
+/*
+ * Utility macro to call macros above in correct order in order to perform a
+ * task switch from within a standard ISR.  This macro can only be used if
+ * the ISR does not use any local (stack) variables.  If the ISR uses stack
+ * variables portYIELD() should be used in it's place.
+ */
+
+#define portTASK_SWITCH_FROM_ISR()								\
+	portSAVE_CONTEXT();											\
+	vTaskSwitchContext();										\
+	portRESTORE_CONTEXT();
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/IA32_flat/ISR_Support.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/IA32_flat/ISR_Support.h
new file mode 100644
index 0000000..df07dac
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/IA32_flat/ISR_Support.h
@@ -0,0 +1,127 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	.extern ulTopOfSystemStack
+	.extern ulInterruptNesting
+
+/*-----------------------------------------------------------*/
+
+.macro portFREERTOS_INTERRUPT_ENTRY
+
+	/* Save general purpose registers. */
+	pusha
+
+	/* If ulInterruptNesting is zero the rest of the task context will need
+	saving and a stack switch might be required. */
+	movl	ulInterruptNesting, %eax
+	test	%eax, %eax
+	jne		2f
+
+	/* Interrupts are not nested, so save the rest of the task context. */
+	.if configSUPPORT_FPU == 1
+
+		/* If the task has a buffer allocated to save the FPU context then
+		save the FPU context now. */
+		movl	pucPortTaskFPUContextBuffer, %eax
+		test	%eax, %eax
+		je		1f
+		fnsave	( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */
+		fwait
+
+		1:
+		/* Save the address of the FPU context, if any. */
+		push	pucPortTaskFPUContextBuffer
+
+	.endif /* configSUPPORT_FPU */
+
+	/* Find the TCB. */
+	movl 	pxCurrentTCB, %eax
+
+	/* Stack location is first item in the TCB. */
+	movl	%esp, (%eax)
+
+	/* Switch stacks. */
+	movl 	ulTopOfSystemStack, %esp
+	movl	%esp, %ebp
+
+	2:
+	/* Increment nesting count. */
+	add 	$1, ulInterruptNesting
+
+.endm
+/*-----------------------------------------------------------*/
+
+.macro portINTERRUPT_EPILOGUE
+
+	cli
+	sub		$1, ulInterruptNesting
+
+	/* If the nesting has unwound to zero. */
+	movl	ulInterruptNesting, %eax
+	test	%eax, %eax
+	jne		2f
+
+	/* If a yield was requested then select a new TCB now. */
+	movl	ulPortYieldPending, %eax
+	test	%eax, %eax
+	je		1f
+	movl	$0, ulPortYieldPending
+	call	vTaskSwitchContext
+
+	1:
+	/* Stack location is first item in the TCB. */
+	movl 	pxCurrentTCB, %eax
+	movl	(%eax), %esp
+
+	.if configSUPPORT_FPU == 1
+
+		/* Restore address of task's FPU context buffer. */
+		pop 	pucPortTaskFPUContextBuffer
+
+		/* If the task has a buffer allocated in which its FPU context is saved,
+		then restore it now. */
+		movl	pucPortTaskFPUContextBuffer, %eax
+		test	%eax, %eax
+		je		1f
+		frstor	( %eax )
+		1:
+	.endif
+
+	2:
+	popa
+
+.endm
+/*-----------------------------------------------------------*/
+
+.macro portFREERTOS_INTERRUPT_EXIT
+
+	portINTERRUPT_EPILOGUE
+	/* EOI. */
+	movl	$0x00, (0xFEE000B0)
+	iret
+
+.endm
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/IA32_flat/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/IA32_flat/port.c
new file mode 100644
index 0000000..d9f5013
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/IA32_flat/port.c
@@ -0,0 +1,686 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <limits.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#if( configISR_STACK_SIZE < ( configMINIMAL_STACK_SIZE * 2 ) )
+	#warning configISR_STACK_SIZE is probably too small!
+#endif /* ( configISR_STACK_SIZE < configMINIMAL_STACK_SIZE * 2 ) */
+
+#if( ( configMAX_API_CALL_INTERRUPT_PRIORITY > portMAX_PRIORITY ) || ( configMAX_API_CALL_INTERRUPT_PRIORITY < 2 ) )
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be between 2 and 15
+#endif
+
+#if( ( configSUPPORT_FPU == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
+	#error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port with an FPU
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created.  A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
+
+/* Only the IF bit is set so tasks start with interrupts enabled. */
+#define portINITIAL_EFLAGS				( 0x200UL )
+
+/* Error interrupts are at the highest priority vectors. */
+#define portAPIC_LVT_ERROR_VECTOR 		( 0xfe )
+#define portAPIC_SPURIOUS_INT_VECTOR 	( 0xff )
+
+/* EFLAGS bits. */
+#define portEFLAGS_IF					( 0x200UL )
+
+/* FPU context size if FSAVE is used. */
+#define portFPU_CONTEXT_SIZE_BYTES 		108
+
+/* The expected size of each entry in the IDT.  Used to check structure packing
+ is set correctly. */
+#define portEXPECTED_IDT_ENTRY_SIZE		8
+
+/* Default flags setting for entries in the IDT. */
+#define portIDT_FLAGS					( 0x8E )
+
+/* This is the lowest possible ISR vector available to application code. */
+#define portAPIC_MIN_ALLOWABLE_VECTOR	( 0x20 )
+
+/* If configASSERT() is defined then the system stack is filled with this value
+to allow for a crude stack overflow check. */
+#define portSTACK_WORD					( 0xecececec )
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*
+ * Complete one descriptor in the IDT.
+ */
+static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags );
+
+/*
+ * The default handler installed in each IDT position.
+ */
+extern void vPortCentralInterruptWrapper( void );
+
+/*
+ * Handler for portYIELD().
+ */
+extern void vPortYieldCall( void );
+
+/*
+ * Configure the APIC to generate the RTOS tick.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * Tick interrupt handler.
+ */
+extern void vPortTimerHandler( void );
+
+/*
+ * Check an interrupt vector is not too high, too low, in use by FreeRTOS, or
+ * already in use by the application.
+ */
+static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+variable must be initialised to a non zero value to ensure interrupts don't
+inadvertently become unmasked before the scheduler starts. It is set to zero
+before the first task starts executing. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* A structure used to map the various fields of an IDT entry into separate
+structure members. */
+struct IDTEntry
+{
+	uint16_t usISRLow;				/* Low 16 bits of handler address. */
+	uint16_t usSegmentSelector;		/* Flat model means this is not changed. */
+	uint8_t ucZero;					/* Must be set to zero. */
+	uint8_t ucFlags;				/* Flags for this entry. */
+	uint16_t usISRHigh;				/* High 16 bits of handler address. */
+} __attribute__( ( packed ) );
+typedef struct IDTEntry IDTEntry_t;
+
+
+/* Use to pass the location of the IDT to the CPU. */
+struct IDTPointer
+{
+   uint16_t usTableLimit;
+   uint32_t ulTableBase;                /* The address of the first entry in xInterruptDescriptorTable. */
+} __attribute__( ( __packed__ ) );
+typedef struct IDTPointer IDTPointer_t;
+
+/* The IDT itself. */
+static __attribute__ ( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[ portNUM_VECTORS ];
+
+#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
+
+	/* A table in which application defined interrupt handlers are stored.  These
+	are called by the central interrupt handler if a common interrupt entry
+	point it used. */
+	static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL };
+
+#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
+
+#if ( configSUPPORT_FPU == 1 )
+
+	/* Saved as part of the task context.  If pucPortTaskFPUContextBuffer is NULL
+	then the task does not have an FPU context.  If pucPortTaskFPUContextBuffer is
+	not NULL then it points to a buffer into which the FPU context can be saved. */
+	uint8_t *pucPortTaskFPUContextBuffer __attribute__((used)) = pdFALSE;
+
+#endif /* configSUPPORT_FPU */
+
+/* The stack used by interrupt handlers. */
+static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__((used))  = { 0 };
+
+/* Don't use the very top of the system stack so the return address
+appears as 0 if the debugger tries to unwind the stack. */
+volatile uint32_t ulTopOfSystemStack __attribute__((used)) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] );
+
+/* If a yield is requested from an interrupt or from a critical section then
+the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE
+instead to indicate the yield should be performed at the end of the interrupt
+when the critical section is exited. */
+volatile uint32_t ulPortYieldPending __attribute__((used)) = pdFALSE;
+
+/* Counts the interrupt nesting depth.  Used to know when to switch to the
+interrupt/system stack and when to save/restore a complete context. */
+volatile uint32_t ulInterruptNesting __attribute__((used)) = 0;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t ulCodeSegment;
+
+	/* Setup the initial stack as expected by the portFREERTOS_INTERRUPT_EXIT macro. */
+
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+
+	/* Parameters first. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+
+	/* There is nothing to return to so assert if attempting to use the return
+	address. */
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;
+	pxTopOfStack--;
+
+	/* iret used to start the task pops up to here. */
+	*pxTopOfStack = portINITIAL_EFLAGS;
+	pxTopOfStack--;
+
+	/* CS */
+	__asm volatile( "movl %%cs, %0" : "=r" ( ulCodeSegment ) );
+	*pxTopOfStack = ulCodeSegment;
+	pxTopOfStack--;
+
+	/* First instruction in the task. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	/* General purpose registers as expected by a POPA instruction. */
+	*pxTopOfStack = 0xEA;
+	pxTopOfStack--;
+
+	*pxTopOfStack = 0xEC;
+	pxTopOfStack--;
+
+	*pxTopOfStack = 0xED1; /* EDX */
+	pxTopOfStack--;
+
+	*pxTopOfStack = 0xEB1; /* EBX */
+	pxTopOfStack--;
+
+	/* Hole for ESP. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = 0x00; /* EBP */
+	pxTopOfStack--;
+
+	*pxTopOfStack = 0xE5; /* ESI */
+	pxTopOfStack--;
+
+	*pxTopOfStack = 0xeeeeeeee; /* EDI */
+
+	#if ( configSUPPORT_FPU == 1 )
+	{
+		pxTopOfStack--;
+
+		/* Buffer for FPU context, which is initialised to NULL as tasks are not
+		created with an FPU context. */
+		*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+	}
+	#endif /* configSUPPORT_FPU */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags )
+{
+uint16_t usCodeSegment;
+uint32_t ulBase = ( uint32_t ) pxHandlerFunction;
+
+	xInterruptDescriptorTable[ ucNumber ].usISRLow = ( uint16_t ) ( ulBase & USHRT_MAX );
+	xInterruptDescriptorTable[ ucNumber ].usISRHigh = ( uint16_t ) ( ( ulBase >> 16UL ) & USHRT_MAX );
+
+	/* When the flat model is used the CS will never change. */
+	__asm volatile( "mov %%cs, %0" : "=r" ( usCodeSegment ) );
+	xInterruptDescriptorTable[ ucNumber ].usSegmentSelector = usCodeSegment;
+	xInterruptDescriptorTable[ ucNumber ].ucZero = 0;
+	xInterruptDescriptorTable[ ucNumber ].ucFlags = ucFlags;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetupIDT( void )
+{
+uint32_t ulNum;
+IDTPointer_t xIDT;
+
+	#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
+	{
+		for( ulNum = 0; ulNum < portNUM_VECTORS; ulNum++ )
+		{
+			/* If a handler has not already been installed on this vector. */
+			if( ( xInterruptDescriptorTable[ ulNum ].usISRLow == 0x00 ) && ( xInterruptDescriptorTable[ ulNum ].usISRHigh == 0x00 ) )
+			{
+				prvSetInterruptGate( ( uint8_t ) ulNum, vPortCentralInterruptWrapper, portIDT_FLAGS );
+			}
+		}
+	}
+	#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
+
+	/* Set IDT address. */
+	xIDT.ulTableBase = ( uint32_t ) xInterruptDescriptorTable;
+	xIDT.usTableLimit = sizeof( xInterruptDescriptorTable ) - 1;
+
+	/* Set IDT in CPU. */
+	__asm volatile( "lidt %0" :: "m" (xIDT) );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( ulCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+extern void vPortAPICErrorHandlerWrapper( void );
+extern void vPortAPICSpuriousHandler( void );
+
+	/* Initialise LAPIC to a well known state. */
+	portAPIC_LDR = 0xFFFFFFFF;
+	portAPIC_LDR = ( ( portAPIC_LDR & 0x00FFFFFF ) | 0x00000001 );
+	portAPIC_LVT_TIMER = portAPIC_DISABLE;
+	portAPIC_LVT_PERF = portAPIC_NMI;
+	portAPIC_LVT_LINT0 = portAPIC_DISABLE;
+	portAPIC_LVT_LINT1 = portAPIC_DISABLE;
+	portAPIC_TASK_PRIORITY = 0;
+
+	/* Install APIC timer ISR vector. */
+	prvSetInterruptGate( ( uint8_t ) portAPIC_TIMER_INT_VECTOR, vPortTimerHandler, portIDT_FLAGS );
+
+	/* Install API error handler. */
+	prvSetInterruptGate( ( uint8_t ) portAPIC_LVT_ERROR_VECTOR, vPortAPICErrorHandlerWrapper, portIDT_FLAGS );
+
+	/* Install Yield handler. */
+	prvSetInterruptGate( ( uint8_t ) portAPIC_YIELD_INT_VECTOR, vPortYieldCall, portIDT_FLAGS );
+
+	/* Install spurious interrupt vector. */
+	prvSetInterruptGate( ( uint8_t ) portAPIC_SPURIOUS_INT_VECTOR, vPortAPICSpuriousHandler, portIDT_FLAGS );
+
+	/* Enable the APIC, mapping the spurious interrupt at the same time. */
+	portAPIC_SPURIOUS_INT = portAPIC_SPURIOUS_INT_VECTOR | portAPIC_ENABLE_BIT;
+
+	/* Set timer error vector. */
+	portAPIC_LVT_ERROR = portAPIC_LVT_ERROR_VECTOR;
+
+	/* Set the interrupt frequency. */
+	portAPIC_TMRDIV = portAPIC_DIV_16;
+	portAPIC_TIMER_INITIAL_COUNT = ( ( configCPU_CLOCK_HZ >> 4UL ) / configTICK_RATE_HZ ) - 1UL;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+BaseType_t xWord;
+
+	/* Some versions of GCC require the -mno-ms-bitfields command line option
+	for packing to work. */
+	configASSERT( sizeof( struct IDTEntry ) == portEXPECTED_IDT_ENTRY_SIZE );
+
+	/* Fill part of the system stack with a known value to help detect stack
+	overflow.  A few zeros are left so GDB doesn't get confused unwinding
+	the stack. */
+	for( xWord = 0; xWord < configISR_STACK_SIZE - 20; xWord++ )
+	{
+		ulSystemStack[ xWord ] = portSTACK_WORD;
+	}
+
+	/* Initialise Interrupt Descriptor Table (IDT). */
+	vPortSetupIDT();
+
+	/* Initialise LAPIC and install system handlers. */
+	prvSetupTimerInterrupt();
+
+	/* Make sure the stack used by interrupts is aligned. */
+	ulTopOfSystemStack &= ~portBYTE_ALIGNMENT_MASK;
+
+	ulCriticalNesting = 0;
+
+	/* Enable LAPIC Counter.*/
+	portAPIC_LVT_TIMER = portAPIC_TIMER_PERIODIC | portAPIC_TIMER_INT_VECTOR;
+
+	/* Sometimes needed. */
+	portAPIC_TMRDIV = portAPIC_DIV_16;
+
+	/* Should not return from the following function as the scheduler will then
+	be executing the tasks. */
+	vPortStartFirstTask();
+
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	if( ulCriticalNesting == 0 )
+	{
+		#if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+		{
+			__asm volatile( "cli" );
+		}
+		#else
+		{
+			portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
+			configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
+		}
+		#endif
+	}
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as the critical section is being
+		exited. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then all interrupt
+		priorities must be re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Critical nesting has reached zero so all interrupt priorities
+			should be unmasked. */
+			#if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+			{
+				__asm volatile( "sti" );
+			}
+			#else
+			{
+				portAPIC_TASK_PRIORITY = 0;
+			}
+			#endif
+
+			/* If a yield was pended from within the critical section then
+			perform the yield now. */
+			if( ulPortYieldPending != pdFALSE )
+			{
+				ulPortYieldPending = pdFALSE;
+				__asm volatile( portYIELD_INTERRUPT );
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortSetInterruptMask( void )
+{
+volatile uint32_t ulOriginalMask;
+
+	/* Set mask to max syscall priority. */
+	#if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+	{
+		/* Return whether interrupts were already enabled or not.  Pop adjusts
+		the stack first. */
+		__asm volatile( "pushf		\t\n"
+						"pop %0		\t\n"
+						"cli			"
+						: "=rm" (ulOriginalMask) :: "memory" );
+
+		ulOriginalMask &= portEFLAGS_IF;
+	}
+	#else
+	{
+		/* Return original mask. */
+		ulOriginalMask = portAPIC_TASK_PRIORITY;
+		portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
+		configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
+	}
+	#endif
+
+	return ulOriginalMask;
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( uint32_t ulNewMaskValue )
+{
+	#if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
+	{
+		if( ulNewMaskValue != pdFALSE )
+		{
+			__asm volatile( "sti" );
+		}
+	}
+	#else
+	{
+		portAPIC_TASK_PRIORITY = ulNewMaskValue;
+		configASSERT( portAPIC_TASK_PRIORITY == ulNewMaskValue );
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_FPU == 1 )
+
+	void vPortTaskUsesFPU( void )
+	{
+		/* A task is registering the fact that it needs an FPU context.  Allocate a
+		buffer into which the context can be saved. */
+		pucPortTaskFPUContextBuffer = ( uint8_t * ) pvPortMalloc( portFPU_CONTEXT_SIZE_BYTES );
+		configASSERT( pucPortTaskFPUContextBuffer );
+
+		/* Initialise the floating point registers. */
+		__asm volatile(	"fninit" );
+	}
+
+#endif /* configSUPPORT_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortAPICErrorHandler( void )
+{
+/* Variable to hold the APIC error status for viewing in the debugger. */
+volatile uint32_t ulErrorStatus = 0;
+
+	portAPIC_ERROR_STATUS = 0;
+	ulErrorStatus = portAPIC_ERROR_STATUS;
+	( void ) ulErrorStatus;
+
+	/* Force an assert. */
+	configASSERT( ulCriticalNesting == ~0UL );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
+
+	void vPortCentralInterruptHandler( uint32_t ulVector )
+	{
+		if( ulVector < portNUM_VECTORS )
+		{
+			if( xInterruptHandlerTable[ ulVector ] != NULL )
+			{
+				( xInterruptHandlerTable[ ulVector ] )();
+			}
+		}
+
+		/* Check for a system stack overflow. */
+		configASSERT( ulSystemStack[ 10 ] == portSTACK_WORD );
+		configASSERT( ulSystemStack[ 12 ] == portSTACK_WORD );
+		configASSERT( ulSystemStack[ 14 ] == portSTACK_WORD );
+	}
+
+#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
+
+	BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )
+	{
+	BaseType_t xReturn;
+
+		xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
+
+		if( xReturn != pdFAIL )
+		{
+			/* Save the handler passed in by the application in the vector number
+			passed in.  The addresses are then called from the central interrupt
+			handler. */
+			xInterruptHandlerTable[ ulVectorNumber ] = pxHandler;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )
+{
+BaseType_t xReturn;
+
+	xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
+
+	if( xReturn != pdFAIL )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Update the IDT to include the application defined handler. */
+			prvSetInterruptGate( ( uint8_t ) ulVectorNumber, ( ISR_Handler_t ) pxHandler, portIDT_FLAGS );
+		}
+		taskEXIT_CRITICAL();
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber )
+{
+BaseType_t xReturn;
+
+	/* Check validity of vector number. */
+	if( ulVectorNumber >= portNUM_VECTORS )
+	{
+		/* Too high. */
+		xReturn = pdFAIL;
+	}
+	else if( ulVectorNumber < portAPIC_MIN_ALLOWABLE_VECTOR )
+	{
+		/* Too low. */
+		xReturn = pdFAIL;
+	}
+	else if( ulVectorNumber == portAPIC_TIMER_INT_VECTOR )
+	{
+		/* In use by FreeRTOS. */
+		xReturn = pdFAIL;
+	}
+	else if( ulVectorNumber == portAPIC_YIELD_INT_VECTOR )
+	{
+		/* In use by FreeRTOS. */
+		xReturn = pdFAIL;
+	}
+	else if( ulVectorNumber == portAPIC_LVT_ERROR_VECTOR )
+	{
+		/* In use by FreeRTOS. */
+		xReturn = pdFAIL;
+	}
+	else if( ulVectorNumber == portAPIC_SPURIOUS_INT_VECTOR )
+	{
+		/* In use by FreeRTOS. */
+		xReturn = pdFAIL;
+	}
+	else if( xInterruptHandlerTable[ ulVectorNumber ] != NULL )
+	{
+		/* Already in use by the application. */
+		xReturn = pdFAIL;
+	}
+	else
+	{
+		xReturn = pdPASS;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vGenerateYieldInterrupt( void )
+{
+	__asm volatile( portYIELD_INTERRUPT );
+}
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/IA32_flat/portASM.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/IA32_flat/portASM.S
new file mode 100644
index 0000000..af682cd
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/IA32_flat/portASM.S
@@ -0,0 +1,274 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+.file "portASM.S"
+#include "FreeRTOSConfig.h"
+#include "ISR_Support.h"
+
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern vPortCentralInterruptHandler
+	.extern xTaskIncrementTick
+	.extern vPortAPICErrorHandler
+	.extern pucPortTaskFPUContextBuffer
+	.extern ulPortYieldPending
+
+	.global vPortStartFirstTask
+	.global vPortCentralInterruptWrapper
+	.global vPortAPICErrorHandlerWrapper
+	.global vPortTimerHandler
+	.global vPortYieldCall
+	.global vPortAPICSpuriousHandler
+
+	.text
+
+/*-----------------------------------------------------------*/
+
+.align 4
+.func vPortYieldCall
+vPortYieldCall:
+	/* Save general purpose registers. */
+	pusha
+
+	.if configSUPPORT_FPU == 1
+
+		/* If the task has a buffer allocated to save the FPU context then save
+		the FPU context now. */
+		movl	pucPortTaskFPUContextBuffer, %eax
+		test	%eax, %eax
+		je		1f
+		fnsave	( %eax )
+		fwait
+
+		1:
+
+		/* Save the address of the FPU context, if any. */
+		push	pucPortTaskFPUContextBuffer
+
+	.endif /* configSUPPORT_FPU */
+
+	/* Find the TCB. */
+	movl 	pxCurrentTCB, %eax
+
+	/* Stack location is first item in the TCB. */
+	movl	%esp, (%eax)
+
+	call vTaskSwitchContext
+
+	/* Find the location of pxCurrentTCB again - a callee saved register could
+	be used in place of eax to prevent this second load, but that then relies
+	on the compiler and other asm code. */
+	movl 	pxCurrentTCB, %eax
+	movl	(%eax), %esp
+
+	.if configSUPPORT_FPU == 1
+
+		/* Restore address of task's FPU context buffer. */
+		pop 	pucPortTaskFPUContextBuffer
+
+		/* If the task has a buffer allocated in which its FPU context is saved,
+		then restore it now. */
+		movl	pucPortTaskFPUContextBuffer, %eax
+		test	%eax, %eax
+		je		1f
+		frstor	( %eax )
+		1:
+	.endif
+
+	popa
+	iret
+
+.endfunc
+/*-----------------------------------------------------------*/
+
+.align 4
+.func vPortStartFirstTask
+vPortStartFirstTask:
+
+	/* Find the TCB. */
+	movl 	pxCurrentTCB, %eax
+
+	/* Stack location is first item in the TCB. */
+	movl	(%eax), %esp
+
+	/* Restore FPU context flag. */
+	.if configSUPPORT_FPU == 1
+
+		pop 	pucPortTaskFPUContextBuffer
+
+	.endif /* configSUPPORT_FPU */
+
+	/* Restore general purpose registers. */
+	popa
+	iret
+.endfunc
+/*-----------------------------------------------------------*/
+
+.align 4
+.func vPortAPICErrorHandlerWrapper
+vPortAPICErrorHandlerWrapper:
+	pusha
+	call	vPortAPICErrorHandler
+	popa
+	/* EOI. */
+	movl	$0x00, (0xFEE000B0)
+	iret
+.endfunc
+/*-----------------------------------------------------------*/
+
+.align 4
+.func vPortTimerHandler
+vPortTimerHandler:
+
+	/* Save general purpose registers. */
+	pusha
+
+	/* Interrupts are not nested, so save the rest of the task context. */
+	.if configSUPPORT_FPU == 1
+
+		/* If the task has a buffer allocated to save the FPU context then save the
+		FPU context now. */
+		movl	pucPortTaskFPUContextBuffer, %eax
+		test	%eax, %eax
+		je		1f
+		fnsave	( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */
+		fwait
+
+		1:
+		/* Save the address of the FPU context, if any. */
+		push	pucPortTaskFPUContextBuffer
+
+	.endif /* configSUPPORT_FPU */
+
+	/* Find the TCB. */
+	movl 	pxCurrentTCB, %eax
+
+	/* Stack location is first item in the TCB. */
+	movl	%esp, (%eax)
+
+	/* Switch stacks. */
+	movl 	ulTopOfSystemStack, %esp
+	movl	%esp, %ebp
+
+	/* Increment nesting count. */
+	add 	$1, ulInterruptNesting
+
+	call 	xTaskIncrementTick
+
+	sti
+
+	/* Is a switch to another task required? */
+	test	%eax, %eax
+	je		_skip_context_switch
+	cli
+	call	vTaskSwitchContext
+
+_skip_context_switch:
+	cli
+
+	/* Decrement the variable used to determine if a switch to a system
+	stack is necessary. */
+	sub		$1, ulInterruptNesting
+
+	/* Stack location is first item in the TCB. */
+	movl 	pxCurrentTCB, %eax
+	movl	(%eax), %esp
+
+	.if configSUPPORT_FPU == 1
+
+		/* Restore address of task's FPU context buffer. */
+		pop 	pucPortTaskFPUContextBuffer
+
+		/* If the task has a buffer allocated in which its FPU context is saved,
+		then restore it now. */
+		movl	pucPortTaskFPUContextBuffer, %eax
+		test	%eax, %eax
+		je		1f
+		frstor	( %eax )
+		1:
+	.endif
+
+	popa
+
+	/* EOI. */
+	movl	$0x00, (0xFEE000B0)
+	iret
+
+.endfunc
+/*-----------------------------------------------------------*/
+
+.if configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1
+
+	.align 4
+	.func vPortCentralInterruptWrapper
+	vPortCentralInterruptWrapper:
+
+		portFREERTOS_INTERRUPT_ENTRY
+
+		movl $0xFEE00170, %eax 			/* Highest In Service Register (ISR) long word. */
+		movl $8, %ecx					/* Loop counter. */
+
+	next_isr_long_word:
+		test %ecx, %ecx					/* Loop counter reached 0? */
+		je wrapper_epilogue				/* Looked at all ISR registers without finding a bit set. */
+		sub $1, %ecx					/* Sub 1 from loop counter. */
+		movl (%eax), %ebx				/* Load next ISR long word. */
+		sub $0x10, %eax					/* Point to next ISR long word in case no bits are set in the current long word. */
+		test %ebx, %ebx					/* Are there any bits set? */
+		je next_isr_long_word			/* Look at next ISR long word if no bits were set. */
+		sti
+		bsr %ebx, %ebx					/* A bit was set, which one? */
+		movl $32, %eax					/* Destination operand for following multiplication. */
+		mul %ecx						/* Calculate base vector for current register, 32 vectors per register. */
+		add %ebx, %eax					/* Add bit offset into register to get final vector number. */
+		push %eax						/* Vector number is function parameter. */
+		call vPortCentralInterruptHandler
+		pop %eax						/* Remove parameter. */
+
+	wrapper_epilogue:
+		portFREERTOS_INTERRUPT_EXIT
+
+	.endfunc
+
+.endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
+/*-----------------------------------------------------------*/
+
+.align 4
+.func vPortAPISpuriousHandler
+vPortAPICSpuriousHandler:
+	iret
+
+.endfunc
+
+.end
+
+
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/IA32_flat/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/IA32_flat/portmacro.h
new file mode 100644
index 0000000..5420d65
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/IA32_flat/portmacro.h
@@ -0,0 +1,291 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+	extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( ( TickType_t ) 0xffffffffUL )
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			32
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* The interrupt priority (for vectors 16 to 255) is determined using vector/16.
+The quotient is rounded to the nearest integer with 1 being the lowest priority
+and 15 is the highest.  Therefore the following two interrupts are at the lowest
+priority.  *NOTE 1* If the yield vector is changed then it must also be changed
+in the portYIELD_INTERRUPT definition immediately below. */
+#define portAPIC_TIMER_INT_VECTOR 		( 0x21 )
+#define portAPIC_YIELD_INT_VECTOR 		( 0x20 )
+
+/* Build yield interrupt instruction. */
+#define portYIELD_INTERRUPT "int $0x20"
+
+/* APIC register addresses. */
+#define portAPIC_EOI					( *( ( volatile uint32_t * ) 0xFEE000B0UL ) )
+
+/* APIC bit definitions. */
+#define portAPIC_ENABLE_BIT				( 1UL << 8UL )
+#define portAPIC_TIMER_PERIODIC 		( 1UL << 17UL )
+#define portAPIC_DISABLE 				( 1UL << 16UL )
+#define portAPIC_NMI 					( 4 << 8)
+#define portAPIC_DIV_16 				( 0x03 )
+
+/* Define local API register addresses. */
+#define portAPIC_ID_REGISTER			( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x20UL  ) ) )
+#define portAPIC_SPURIOUS_INT			( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xF0UL  ) ) )
+#define portAPIC_LVT_TIMER				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x320UL ) ) )
+#define portAPIC_TIMER_INITIAL_COUNT	( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x380UL ) ) )
+#define portAPIC_TIMER_CURRENT_COUNT	( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x390UL ) ) )
+#define portAPIC_TASK_PRIORITY			( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x80UL  ) ) )
+#define portAPIC_LVT_ERROR				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x370UL ) ) )
+#define portAPIC_ERROR_STATUS			( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x280UL ) ) )
+#define portAPIC_LDR	 				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xD0UL  ) ) )
+#define portAPIC_TMRDIV 				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x3E0UL ) ) )
+#define portAPIC_LVT_PERF 				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x340UL ) ) )
+#define portAPIC_LVT_LINT0 				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x350UL ) ) )
+#define portAPIC_LVT_LINT1 				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x360UL ) ) )
+
+/* Don't yield if inside a critical section - instead hold the yield pending
+so it is performed when the critical section is exited. */
+#define portYIELD() 								\
+{													\
+extern volatile uint32_t ulCriticalNesting;			\
+extern volatile uint32_t ulPortYieldPending;		\
+	if( ulCriticalNesting != 0 )					\
+	{												\
+		ulPortYieldPending = pdTRUE;				\
+	}												\
+	else											\
+	{												\
+		__asm volatile( portYIELD_INTERRUPT );		\
+	}												\
+}
+
+/* Called at the end of an ISR that can cause a context switch - pend a yield if
+xSwithcRequired is not false. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )	\
+{													\
+extern volatile uint32_t ulPortYieldPending;		\
+	if( xSwitchRequired != pdFALSE )				\
+	{												\
+		ulPortYieldPending = 1; 				 	\
+	}												\
+}
+
+/* Same as portEND_SWITCHING_ISR() - take your pick which name to use. */
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+/* Critical sections for use in interrupts. */
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask( x )
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+
+/* These macros do not globally disable/enable interrupts.  They do mask off
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+#define portDISABLE_INTERRUPTS()	__asm volatile( "cli" )
+#define portENABLE_INTERRUPTS()		__asm volatile( "sti" )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+/* Architecture specific optimisations. */
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )	\
+		__asm volatile(	"bsr %1, %0\n\t" 									\
+						:"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" )
+
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#define portNOP() __asm volatile( "NOP" )
+
+/*-----------------------------------------------------------
+ * Misc
+ *----------------------------------------------------------*/
+
+#define portNUM_VECTORS		256
+#define portMAX_PRIORITY	15
+typedef void ( *ISR_Handler_t ) ( void );
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+#ifndef configSUPPORT_FPU
+	#define configSUPPORT_FPU 0
+#endif
+
+#if configSUPPORT_FPU == 1
+	void vPortTaskUsesFPU( void );
+	#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+#endif
+
+/* See the comments under the configUSE_COMMON_INTERRUPT_ENTRY_POINT definition
+below. */
+BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );
+BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );
+
+#ifndef configAPIC_BASE
+	/* configAPIC_BASE_ADDRESS sets the base address of the local APIC.  It can
+	be overridden in FreeRTOSConfig.h should it not be constant. */
+	#define configAPIC_BASE	0xFEE00000UL
+#endif
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	/* The FreeRTOS scheduling algorithm selects the task that will enter the
+	Running state.  configUSE_PORT_OPTIMISED_TASK_SELECTION is used to set how
+	that is done.
+
+	If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 0 then the task to
+	enter the Running state is selected using a portable algorithm written in
+	C.  This is the slowest method, but the algorithm does not restrict the
+	maximum number of unique RTOS task priorities that are available.
+
+	If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 then the task to
+	enter the Running state is selected using a single assembly instruction.
+	This is the fastest method, but restricts the maximum number of unique RTOS
+	task priorities to 32 (the same task priority can be assigned to any number
+	of RTOS	tasks). */
+	#warning configUSE_PORT_OPTIMISED_TASK_SELECTION was not defined in FreeRTOSConfig.h and has been defaulted to 1
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#ifndef configUSE_COMMON_INTERRUPT_ENTRY_POINT
+	/* There are two ways of implementing interrupt handlers:
+
+		1) As standard C functions -
+
+		This method can only be used if configUSE_COMMON_INTERRUPT_ENTRY_POINT
+		is set to 1.  The C function is installed using
+		xPortRegisterCInterruptHandler().
+
+		This is the simplest of the two methods but incurs a slightly longer
+		interrupt entry time.
+
+		2) By using an assembly stub that wraps the handler in the FreeRTOS
+		   portFREERTOS_INTERRUPT_ENTRY and portFREERTOS_INTERRUPT_EXIT macros.
+
+		This method can always be used.  It is slightly more complex than
+		method 1 but benefits from a faster interrupt entry time. */
+	#warning configUSE_COMMON_INTERRUPT_ENTRY_POINT was not defined in FreeRTOSConfig.h and has been defaulted to 1.
+	#define configUSE_COMMON_INTERRUPT_ENTRY_POINT	1
+#endif
+
+#ifndef configISR_STACK_SIZE
+	/* Interrupt entry code will switch the stack in use to a dedicated system
+	stack.
+
+	configISR_STACK_SIZE defines the number of 32-bit values that can be stored
+	on the system stack, and must be large enough to hold a potentially nested
+	interrupt stack frame. */
+
+	#error configISR_STACK_SIZE was not defined in FreeRTOSConfig.h.
+#endif
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+	/* Interrupt safe FreeRTOS functions (those that end in "FromISR" must not
+	be called from an interrupt that has a priority above that set by
+	configMAX_API_CALL_INTERRUPT_PRIORITY.  */
+	#warning configMAX_API_CALL_INTERRUPT_PRIORITY was not defined in FreeRTOSConfig.h and has been defaulted to 10
+	#define configMAX_API_CALL_INTERRUPT_PRIORITY 10
+#endif
+
+#ifndef configSUPPORT_FPU
+	#warning configSUPPORT_FPU was not defined in FreeRTOSConfig.h and has been defaulted to 0
+	#define configSUPPORT_FPU 0
+#endif
+
+/* The value written to the task priority register to raise the interrupt mask
+to the maximum from which FreeRTOS API calls can be made. */
+#define portAPIC_PRIORITY_SHIFT		( 4UL )
+#define portAPIC_MAX_SUB_PRIORITY	( 0x0fUL )
+#define portMAX_API_CALL_PRIORITY		( ( configMAX_API_CALL_INTERRUPT_PRIORITY << portAPIC_PRIORITY_SHIFT ) | portAPIC_MAX_SUB_PRIORITY )
+
+/* Asserts if interrupt safe FreeRTOS functions are called from a priority
+above the max system call interrupt priority. */
+#define portAPIC_PROCESSOR_PRIORITY	( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xA0UL  ) ) )
+#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( portAPIC_PROCESSOR_PRIORITY ) <= ( portMAX_API_CALL_PRIORITY ) )
+
+#ifdef __cplusplus
+	} /* extern C */
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MCF5235/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MCF5235/port.c
new file mode 100644
index 0000000..9c7e84e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MCF5235/port.c
@@ -0,0 +1,285 @@
+/*
+    FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry.
+    MCF5235 Port - Copyright (C) 2006 Christian Walter.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License** as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    FreeRTOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with FreeRTOS; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes FreeRTOS, without being obliged to provide
+    the source code for any proprietary components.  See the licensing section
+    of https://www.FreeRTOS.org for full details of how and when the exception
+    can be applied.
+
+    ***************************************************************************
+    ***************************************************************************
+    *                                                                         *
+    * Get the FreeRTOS eBook!  See https://www.FreeRTOS.org/Documentation     *
+    *                                                                         *
+    * This is a concise, step by step, 'hands on' guide that describes both   *
+    * general multitasking concepts and FreeRTOS specifics. It presents and   *
+    * explains numerous examples that are written using the FreeRTOS API.     *
+    * Full source code for all the examples is provided in an accompanying    *
+    * .zip file.                                                              *
+    *                                                                         *
+    ***************************************************************************
+    ***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the
+	online documentation.
+
+	https://www.FreeRTOS.org - Documentation, latest information, license and 
+	contact details.
+
+        https://www.highintegritysystems.com/safertos/ - A version that is
+        certified for use in safety critical systems.
+
+        https://www.highintegritysystems.com/openrtos/ - Commercial support,
+        development, porting, licensing and training services.
+*/
+
+#include <stdlib.h>
+
+#include "FreeRTOS.h"
+#include "FreeRTOSConfig.h"
+#include "task.h"
+
+/* ------------------------ Types ----------------------------------------- */
+typedef volatile uint32_t vuint32;
+typedef volatile uint16_t vuint16;
+typedef volatile uint8_t vuint8;
+
+/* ------------------------ Defines --------------------------------------- */
+#define portVECTOR_TABLE                __RAMVEC
+#define portVECTOR_SYSCALL              ( 32 + portTRAP_YIELD )
+#define portVECTOR_TIMER                ( 64 + 36 )
+
+#define MCF_PIT_PRESCALER               512UL
+#define MCF_PIT_TIMER_TICKS             ( FSYS_2 / MCF_PIT_PRESCALER )
+#define MCF_PIT_MODULUS_REGISTER(freq)  ( MCF_PIT_TIMER_TICKS / ( freq ) - 1UL)
+
+#define MCF_PIT_PMR0                    ( *( vuint16 * )( void * )( &__IPSBAR[ 0x150002 ] ) )
+#define MCF_PIT_PCSR0                   ( *( vuint16 * )( void * )( &__IPSBAR[ 0x150000 ] ) )
+#define MCF_PIT_PCSR_PRE(x)             ( ( ( x ) & 0x000F ) << 8 )
+#define MCF_PIT_PCSR_EN                 ( 0x0001 )
+#define MCF_PIT_PCSR_RLD                ( 0x0002 )
+#define MCF_PIT_PCSR_PIF                ( 0x0004 )
+#define MCF_PIT_PCSR_PIE                ( 0x0008 )
+#define MCF_PIT_PCSR_OVW                ( 0x0010 )
+#define MCF_INTC0_ICR36                 ( *( vuint8 * )( void * )( &__IPSBAR[ 0x000C64 ] ) )
+#define MCF_INTC0_IMRH                  ( *( vuint32 * )( void * )( &__IPSBAR[ 0x000C08 ] ) )
+#define MCF_INTC0_IMRH_INT_MASK36       ( 0x00000010 )
+#define MCF_INTC0_IMRH_MASKALL          ( 0x00000001 )
+#define MCF_INTC0_ICRn_IP(x)            ( ( ( x ) & 0x07 ) << 0 )
+#define MCF_INTC0_ICRn_IL(x)            ( ( ( x ) & 0x07 ) << 3 )
+
+#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
+#define portINITIAL_CRITICAL_NESTING    ( ( uint32_t ) 10 )
+
+/* ------------------------ Static variables ------------------------------ */
+volatile uint32_t              ulCriticalNesting = portINITIAL_CRITICAL_NESTING;
+
+/* ------------------------ Static functions ------------------------------ */
+#if configUSE_PREEMPTION == 0
+static void prvPortPreemptiveTick ( void ) __attribute__ ((interrupt_handler));
+#else
+static void prvPortPreemptiveTick ( void );
+#endif
+
+/* ------------------------ Start implementation -------------------------- */
+
+StackType_t *
+pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode,
+                       void *pvParameters )
+{
+    /* Place the parameter on the stack in the expected location. */
+    *pxTopOfStack = ( StackType_t ) pvParameters;
+    pxTopOfStack--;
+
+    /* Place dummy return address on stack. Tasks should never terminate so
+     * we can set this to anything. */
+    *pxTopOfStack = ( StackType_t ) 0;
+    pxTopOfStack--;
+
+    /* Create a Motorola Coldfire exception stack frame. First comes the return
+     * address. */
+    *pxTopOfStack = ( StackType_t ) pxCode;
+    pxTopOfStack--;
+
+    /* Format, fault-status, vector number for exception stack frame. Task
+     * run in supervisor mode. */
+    *pxTopOfStack = 0x40002000UL | ( portVECTOR_SYSCALL + 32 ) << 18;
+    pxTopOfStack--;
+
+    /* Set the initial critical section nesting counter to zero. This value
+     * is used to restore the value of ulCriticalNesting. */
+    *pxTopOfStack = 0;
+    *pxTopOfStack--;
+
+    *pxTopOfStack = ( StackType_t ) 0xA6;    /* A6 / FP */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xA5;    /* A5 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xA4;    /* A4 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xA3;    /* A3 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xA2;    /* A2 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xA1;    /* A1 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xA0;    /* A0 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xD7;    /* D7 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xD6;    /* D6 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xD5;    /* D5 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xD4;    /* D4 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xD3;    /* D3 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xD2;    /* D2 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xD1;    /* D1 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0xD0;    /* D0 */
+
+    return pxTopOfStack;
+}
+
+/*
+ * Called by portYIELD() or taskYIELD() to manually force a context switch.
+ */
+static void
+prvPortYield( void )
+{
+    asm volatile ( "move.w  #0x2700, %sr\n\t" );
+#if _GCC_USES_FP == 1
+    asm volatile ( "unlk %fp\n\t" );
+#endif
+     /* Perform the context switch.  First save the context of the current task. */
+    portSAVE_CONTEXT(  );
+
+    /* Find the highest priority task that is ready to run. */
+    vTaskSwitchContext(  );
+
+    /* Restore the context of the new task. */
+    portRESTORE_CONTEXT(  );
+}
+
+#if configUSE_PREEMPTION == 0
+/*
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+static void
+prvPortPreemptiveTick ( void )
+{
+    /* The cooperative scheduler requires a normal IRQ service routine to
+     * simply increment the system tick.
+     */
+
+    xTaskIncrementTick();
+    MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF;
+}
+
+#else
+
+static void
+prvPortPreemptiveTick( void )
+{
+    asm volatile ( "move.w  #0x2700, %sr\n\t" );
+#if _GCC_USES_FP == 1
+    asm volatile ( "unlk %fp\n\t" );
+#endif
+    portSAVE_CONTEXT(  );
+    MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF;
+    if( xTaskIncrementTick() != pdFALSE )
+	{
+		vTaskSwitchContext(  );
+	}
+    portRESTORE_CONTEXT(  );
+}
+#endif
+
+void
+vPortEnterCritical()
+{
+    /* FIXME: We should store the old IPL here - How are we supposed to do
+     * this.
+     */
+    ( void )portSET_IPL( portIPL_MAX );
+
+    /* Now interrupts are disabled ulCriticalNesting can be accessed
+     * directly.  Increment ulCriticalNesting to keep a count of how many times
+     * portENTER_CRITICAL() has been called. */
+    ulCriticalNesting++;
+}
+
+void
+vPortExitCritical()
+{
+    if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+    {
+        /* Decrement the nesting count as we are leaving a critical section. */
+        ulCriticalNesting--;
+
+        /* If the nesting level has reached zero then interrupts should be
+        re-enabled. */
+        if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+        {
+            ( void )portSET_IPL( 0 );
+        }
+    }
+}
+
+BaseType_t
+xPortStartScheduler( void )
+{
+    extern void     ( *portVECTOR_TABLE[  ] ) (  );
+
+    /* Add entry in vector table for yield system call. */
+    portVECTOR_TABLE[ portVECTOR_SYSCALL ] = prvPortYield;
+    /* Add entry in vector table for periodic timer. */
+    portVECTOR_TABLE[ portVECTOR_TIMER ] = prvPortPreemptiveTick;
+
+    /* Configure the timer for the system clock. */
+    if ( configTICK_RATE_HZ > 0)
+    {
+        /* Configure prescaler */
+        MCF_PIT_PCSR0 = MCF_PIT_PCSR_PRE( 0x9 ) | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_OVW;
+        /* Initialize the periodic timer interrupt. */
+        MCF_PIT_PMR0 = MCF_PIT_MODULUS_REGISTER( configTICK_RATE_HZ );
+        /* Configure interrupt priority and level and unmask interrupt. */
+        MCF_INTC0_ICR36 = MCF_INTC0_ICRn_IL( 0x1 ) | MCF_INTC0_ICRn_IP( 0x1 );
+        MCF_INTC0_IMRH &= ~( MCF_INTC0_IMRH_INT_MASK36 | MCF_INTC0_IMRH_MASKALL );
+        /* Enable interrupts */
+        MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_EN | MCF_PIT_PCSR_PIF;
+    }
+
+    /* Restore the context of the first task that is going to run. */
+    portRESTORE_CONTEXT(  );
+
+    /* Should not get here. */
+    return pdTRUE;
+}
+
+void
+vPortEndScheduler( void )
+{
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MCF5235/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MCF5235/portmacro.h
new file mode 100644
index 0000000..065667f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MCF5235/portmacro.h
@@ -0,0 +1,183 @@
+/*
+    FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry.
+    MCF5235 Port - Copyright (C) 2006 Christian Walter.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License** as published by
+    the Free Software Foundation; either version 2 of the License, or
+    (at your option) any later version.
+
+    FreeRTOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with FreeRTOS; if not, write to the Free Software
+    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+
+    A special exception to the GPL can be applied should you wish to distribute
+    a combined work that includes FreeRTOS, without being obliged to provide
+    the source code for any proprietary components.  See the licensing section
+    of https://www.FreeRTOS.org for full details of how and when the exception
+    can be applied.
+
+    ***************************************************************************
+    ***************************************************************************
+    *                                                                         *
+    * Get the FreeRTOS eBook!  See https://www.FreeRTOS.org/Documentation      *
+	*                                                                         *
+	* This is a concise, step by step, 'hands on' guide that describes both   *
+	* general multitasking concepts and FreeRTOS specifics. It presents and   *
+	* explains numerous examples that are written using the FreeRTOS API.     *
+	* Full source code for all the examples is provided in an accompanying    *
+	* .zip file.                                                              *
+    *                                                                         *
+    ***************************************************************************
+    ***************************************************************************
+
+	Please ensure to read the configuration and relevant port sections of the
+	online documentation.
+
+	https://www.FreeRTOS.org - Documentation, latest information, license and
+	contact details.
+
+        https://www.highintegritysystems.com/safertos/ - A version that is
+        certified for use in safety critical systems.
+
+        https://www.highintegritysystems.com/openrtos/ - Commercial support,
+        development, porting,
+	licensing and training services.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* ------------------------ Data types for Coldfire ----------------------- */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  unsigned int
+#define portBASE_TYPE   int
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+
+/* ------------------------ Architecture specifics ------------------------ */
+#define portSTACK_GROWTH                ( -1 )
+#define portTICK_PERIOD_MS                ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT              4
+
+#define portTRAP_YIELD                  0   /* Trap 0 */
+#define portIPL_MAX                     7   /* Only NMI interrupt 7 allowed. */
+
+/* ------------------------ FreeRTOS macros for port ---------------------- */
+
+/*
+ * This function must be called when the current state of the active task
+ * should be stored. It must be called immediately after exception
+ * processing from the CPU, i.e. there exists a Coldfire exception frame at
+ * the current position in the stack. The function reserves space on
+ * the stack for the CPU registers and other task dependent values (e.g
+ * ulCriticalNesting) and updates the top of the stack in the TCB.
+ */
+#define portSAVE_CONTEXT()                                                   \
+    asm volatile ( /* reserve space for task state. */                       \
+                   "lea.l   (-64, %sp), %sp\n\t"                             \
+                   /* push data register %d0-%d7/%a0-%a6 on stack. */        \
+                   "movem.l %d0-%d7/%a0-%a6, (%sp)\n\t"                      \
+                   /* push ulCriticalNesting counter on stack. */            \
+                   "lea.l  (60, %sp), %a0\n\t"                               \
+                   "move.l  ulCriticalNesting, (%a0)\n\t"                    \
+                   /* set the new top of the stack in the TCB. */            \
+                   "move.l  pxCurrentTCB, %a0\n\t"                           \
+                   "move.l  %sp, (%a0)");
+
+/*.
+ * This function restores the current active and continues its execution.
+ * It loads the current TCB and restores the processor registers, the
+ * task dependent values (e.g ulCriticalNesting). Finally execution
+ * is continued by executing an rte instruction.
+ */
+#define portRESTORE_CONTEXT()                                                \
+    asm volatile ( "move.l  pxCurrentTCB, %sp\n\t"                           \
+                   "move.l  (%sp), %sp\n\t"                                  \
+                   /* stack pointer now points to the saved registers. */    \
+                   "movem.l (%sp), %d0-%d7/%a0-%a6\n\t"                      \
+                   /* restore ulCriticalNesting counter from stack. */       \
+                   "lea.l   (%sp, 60), %sp\n\t"                              \
+                   "move.l  (%sp)+, ulCriticalNesting\n\t"                   \
+                   /* stack pointer now points to exception frame. */        \
+                   "rte\n\t" );
+
+#define portENTER_CRITICAL()                                                 \
+    vPortEnterCritical();
+
+#define portEXIT_CRITICAL()                                                  \
+    vPortExitCritical();
+
+#define portSET_IPL( xIPL )                                                  \
+    asm_set_ipl( xIPL )
+
+#define portDISABLE_INTERRUPTS() \
+    do { ( void )portSET_IPL( portIPL_MAX ); } while( 0 )
+#define portENABLE_INTERRUPTS() \
+    do { ( void )portSET_IPL( 0 ); } while( 0 )
+
+#define portYIELD()                                                          \
+    asm volatile ( " trap   %0\n\t" : : "i"(portTRAP_YIELD) )
+
+#define portNOP()                                                            \
+    asm volatile ( "nop\n\t" )
+
+#define portENTER_SWITCHING_ISR()                                            \
+    asm volatile ( "move.w  #0x2700, %sr" );                                 \
+    /* Save the context of the interrupted task. */                          \
+    portSAVE_CONTEXT(  );                                                    \
+    {
+
+#define portEXIT_SWITCHING_ISR( SwitchRequired )                             \
+        /* If a switch is required we call vTaskSwitchContext(). */          \
+        if( SwitchRequired )                                                 \
+        {                                                                    \
+            vTaskSwitchContext(  );                                          \
+        }                                                                    \
+    }                                                                        \
+    portRESTORE_CONTEXT(  );
+
+/* ------------------------ Function prototypes --------------------------- */
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+int asm_set_ipl( uint32_t int uiNewIPL );
+
+/* ------------------------ Compiler specifics ---------------------------- */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )                   \
+    void vFunction( void *pvParameters )
+
+#define portTASK_FUNCTION( vFunction, pvParameters )                         \
+    void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MSP430F449/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MSP430F449/port.c
new file mode 100644
index 0000000..1d2e23f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MSP430F449/port.c
@@ -0,0 +1,328 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+	Changes from V2.5.2
+		
+	+ usCriticalNesting now has a volatile qualifier.
+*/
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <signal.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MSP430 port.
+ *----------------------------------------------------------*/
+
+/* Constants required for hardware setup.  The tick ISR runs off the ACLK, 
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ			( ( TickType_t ) 32768 )
+#define portINITIAL_CRITICAL_NESTING	( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED	( ( StackType_t ) 0x08 )
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Most ports implement critical sections by placing the interrupt flags on
+the stack before disabling interrupts.  Exiting the critical section is then
+simply a case of popping the flags from the stack.  As mspgcc does not use
+a frame pointer this cannot be done as modifying the stack will clobber all
+the stack variables.  Instead each task maintains a count of the critical
+section nesting depth.  Each time a critical section is entered the count is
+incremented.  Each time a critical section is left the count is decremented -
+with interrupts only being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+/*-----------------------------------------------------------*/
+
+/* 
+ * Macro to save a task context to the task stack.  This simply pushes all the 
+ * general purpose msp430 registers onto the stack, followed by the 
+ * usCriticalNesting value used by the task.  Finally the resultant stack 
+ * pointer value is saved into the task control block so it can be retrieved 
+ * the next time the task executes.
+ */
+#define portSAVE_CONTEXT()									\
+	asm volatile (	"push	r4						\n\t"	\
+					"push	r5						\n\t"	\
+					"push	r6						\n\t"	\
+					"push	r7						\n\t"	\
+					"push	r8						\n\t"	\
+					"push	r9						\n\t"	\
+					"push	r10						\n\t"	\
+					"push	r11						\n\t"	\
+					"push	r12						\n\t"	\
+					"push	r13						\n\t"	\
+					"push	r14						\n\t"	\
+					"push	r15						\n\t"	\
+					"mov.w	usCriticalNesting, r14	\n\t"	\
+					"push	r14						\n\t"	\
+					"mov.w	pxCurrentTCB, r12		\n\t"	\
+					"mov.w	r1, @r12				\n\t"	\
+				);
+
+/* 
+ * Macro to restore a task context from the task stack.  This is effectively
+ * the reverse of portSAVE_CONTEXT().  First the stack pointer value is
+ * loaded from the task control block.  Next the value for usCriticalNesting
+ * used by the task is retrieved from the stack - followed by the value of all
+ * the general purpose msp430 registers.
+ *
+ * The bic instruction ensures there are no low power bits set in the status
+ * register that is about to be popped from the stack.
+ */
+#define portRESTORE_CONTEXT()								\
+	asm volatile (	"mov.w	pxCurrentTCB, r12		\n\t"	\
+					"mov.w	@r12, r1				\n\t"	\
+					"pop	r15						\n\t"	\
+					"mov.w	r15, usCriticalNesting	\n\t"	\
+					"pop	r15						\n\t"	\
+					"pop	r14						\n\t"	\
+					"pop	r13						\n\t"	\
+					"pop	r12						\n\t"	\
+					"pop	r11						\n\t"	\
+					"pop	r10						\n\t"	\
+					"pop	r9						\n\t"	\
+					"pop	r8						\n\t"	\
+					"pop	r7						\n\t"	\
+					"pop	r6						\n\t"	\
+					"pop	r5						\n\t"	\
+					"pop	r4						\n\t"	\
+					"bic	#(0xf0),0(r1)			\n\t"	\
+					"reti							\n\t"	\
+				);
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ * 
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* 
+		Place a few bytes of known values on the bottom of the stack. 
+		This is just useful for debugging and can be included if required.
+
+		*pxTopOfStack = ( StackType_t ) 0x1111;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x2222;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x3333;
+		pxTopOfStack--; 
+	*/
+
+	/* The msp430 automatically pushes the PC then SR onto the stack before 
+	executing an ISR.  We want the stack to look just as if this has happened
+	so place a pointer to the start of the task on the stack first - followed
+	by the flags we want the task to use when it starts up. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+	*pxTopOfStack = portFLAGS_INT_ENABLED;
+	pxTopOfStack--;
+
+	/* Next the general purpose registers. */
+	*pxTopOfStack = ( StackType_t ) 0x4444;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x5555;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x6666;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x7777;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x8888;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x9999;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xaaaa;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xbbbb;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xcccc;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xdddd;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xeeee;
+	pxTopOfStack--;
+
+	/* When the task starts is will expect to find the function parameter in
+	R15. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+
+	/* The code generated by the mspgcc compiler does not maintain separate
+	stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+	use the stack as per other ports.  Instead a variable is used to keep
+	track of the critical section nesting.  This variable has to be stored
+	as part of the task context and is initially set to zero. */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run. */
+	portRESTORE_CONTEXT();
+
+	/* Should not get here as the tasks are now running! */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the MSP430 port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.  
+ *
+ * The first thing we do is save the registers so we can use a naked attribute.
+ */
+void vPortYield( void ) __attribute__ ( ( naked ) );
+void vPortYield( void )
+{
+	/* We want the stack of the task being saved to look exactly as if the task
+	was saved during a pre-emptive RTOS tick ISR.  Before calling an ISR the 
+	msp430 places the status register onto the stack.  As this is a function 
+	call and not an ISR we have to do this manually. */
+	asm volatile ( "push	r2" );
+	_DINT();
+
+	/* Save the context of the current task. */
+	portSAVE_CONTEXT();
+
+	/* Switch to the highest priority task that is ready to run. */
+	vTaskSwitchContext();
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.  This uses timer 0
+ * but could alternatively use the watchdog timer or timer 1. 
+ */
+static void prvSetupTimerInterrupt( void )
+{
+	/* Ensure the timer is stopped. */
+	TACTL = 0;
+
+	/* Run the timer of the ACLK. */
+	TACTL = TASSEL_1;
+
+	/* Clear everything to start with. */
+	TACTL |= TACLR;
+
+	/* Set the compare match value according to the tick rate we want. */
+	TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
+
+	/* Enable the interrupts. */
+	TACCTL0 = CCIE;
+
+	/* Start up clean. */
+	TACTL |= TACLR;
+
+	/* Up mode. */
+	TACTL |= MC_1;
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * The interrupt service routine used depends on whether the pre-emptive
+ * scheduler is being used or not.
+ */
+
+#if configUSE_PREEMPTION == 1
+
+	/*
+	 * Tick ISR for preemptive scheduler.  We can use a naked attribute as
+	 * the context is saved at the start of vPortYieldFromTick().  The tick
+	 * count is incremented after the context is saved.
+	 */
+	interrupt (TIMERA0_VECTOR) prvTickISR( void ) __attribute__ ( ( naked ) );
+	interrupt (TIMERA0_VECTOR) prvTickISR( void )
+	{
+		/* Save the context of the interrupted task. */
+		portSAVE_CONTEXT();
+
+		/* Increment the tick count then switch to the highest priority task
+		that is ready to run. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			vTaskSwitchContext();
+		}
+
+		/* Restore the context of the new task. */
+		portRESTORE_CONTEXT();
+	}
+
+#else
+
+	/*
+	 * Tick ISR for the cooperative scheduler.  All this does is increment the
+	 * tick count.  We don't need to switch context, this can only be done by
+	 * manual calls to taskYIELD();
+	 */
+	interrupt (TIMERA0_VECTOR) prvTickISR( void );
+	interrupt (TIMERA0_VECTOR) prvTickISR( void )
+	{
+		xTaskIncrementTick();
+	}
+#endif
+
+
+	
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MSP430F449/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MSP430F449/portmacro.h
new file mode 100644
index 0000000..e2c0f7e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MSP430F449/portmacro.h
@@ -0,0 +1,127 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS()	asm volatile ( "DINT" ); asm volatile ( "NOP" )
+#define portENABLE_INTERRUPTS()		asm volatile ( "EINT" ); asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
+
+#define portENTER_CRITICAL()													\
+{																				\
+extern volatile uint16_t usCriticalNesting;							\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	/* Now interrupts are disabled ulCriticalNesting can be accessed */			\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
+	/* times portENTER_CRITICAL() has been called. */							\
+	usCriticalNesting++;														\
+}
+
+#define portEXIT_CRITICAL()														\
+{																				\
+extern volatile uint16_t usCriticalNesting;							\
+																				\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
+	{																			\
+		/* Decrement the nesting count as we are leaving a critical section. */	\
+		usCriticalNesting--;													\
+																				\
+		/* If the nesting level has reached zero then interrupts should be */	\
+		/* re-enabled. */														\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
+		{																		\
+			portENABLE_INTERRUPTS();											\
+		}																		\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+extern void vPortYield( void ) __attribute__ ( ( naked ) );
+#define portYIELD()			vPortYield()
+#define portNOP()			asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Hardwware specifics. */
+#define portBYTE_ALIGNMENT			2
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlaze/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlaze/port.c
new file mode 100644
index 0000000..41bd5b8
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlaze/port.c
@@ -0,0 +1,333 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MicroBlaze port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <string.h>
+
+/* Hardware includes. */
+#include <xintc.h>
+#include <xintc_i.h>
+#include <xtmrctr.h>
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port.
+#endif
+
+/* Tasks are started with interrupts enabled. */
+#define portINITIAL_MSR_STATE		( ( StackType_t ) 0x02 )
+
+/* Tasks are started with a critical section nesting of 0 - however prior
+to the scheduler being commenced we don't want the critical nesting level
+to reach zero, so it is initialised to a high value. */
+#define portINITIAL_NESTING_VALUE	( 0xff )
+
+/* Our hardware setup only uses one counter. */
+#define portCOUNTER_0 				0
+
+/* The stack used by the ISR is filled with a known value to assist in
+debugging. */
+#define portISR_STACK_FILL_VALUE	0x55555555
+
+/* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task
+maintains it's own count, so this variable is saved as part of the task
+context. */
+volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
+
+/* To limit the amount of stack required by each task, this port uses a
+separate stack for interrupts. */
+uint32_t *pulISRStack;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been made.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+extern void *_SDA2_BASE_, *_SDA_BASE_;
+const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
+const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
+
+	/* Place a few bytes of known values on the bottom of the stack.
+	This is essential for the Microblaze port and these lines must
+	not be omitted.  The parameter value will overwrite the
+	0x22222222 value during the function prologue. */
+	*pxTopOfStack = ( StackType_t ) 0x11111111;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x22222222;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x33333333;
+	pxTopOfStack--;
+
+	/* First stack an initial value for the critical section nesting.  This
+	is initialised to zero as tasks are started with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) 0x00;	/* R0. */
+
+	/* Place an initial value for all the general purpose registers. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) ulR2;	/* R2 - small data area. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03;	/* R3. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04;	/* R4. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06;	/* R6. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07;	/* R7. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08;	/* R8. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09;	/* R9. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0a;	/* R10. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0b;	/* R11. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0c;	/* R12. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) ulR13;	/* R13 - small data read write area. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;	/* R14. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0f;	/* R15. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10;	/* R16. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11;	/* R17. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12;	/* R18. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x13;	/* R19. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x14;	/* R20. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x15;	/* R21. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x16;	/* R22. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x17;	/* R23. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x18;	/* R24. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x19;	/* R25. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x1a;	/* R26. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x1b;	/* R27. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x1c;	/* R28. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x1d;	/* R29. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x1e;	/* R30. */
+	pxTopOfStack--;
+
+	/* The MSR is stacked between R30 and R31. */
+	*pxTopOfStack = portINITIAL_MSR_STATE;
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x1f;	/* R31. */
+	pxTopOfStack--;
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void ( __FreeRTOS_interrupt_Handler )( void );
+extern void ( vStartFirstTask )( void );
+
+
+	/* Setup the FreeRTOS interrupt handler.  Code copied from crt0.s. */
+	asm volatile ( 	"la	r6, r0, __FreeRTOS_interrupt_handler		\n\t" \
+					"sw	r6, r1, r0									\n\t" \
+					"lhu r7, r1, r0									\n\t" \
+					"shi r7, r0, 0x12								\n\t" \
+					"shi r6, r0, 0x16 " );
+
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called. */
+	prvSetupTimerInterrupt();
+
+	/* Allocate the stack to be used by the interrupt handler. */
+	pulISRStack = ( uint32_t * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
+
+	/* Restore the context of the first task that is going to run. */
+	if( pulISRStack != NULL )
+	{
+		/* Fill the ISR stack with a known value to facilitate debugging. */
+		memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
+		pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );
+
+		/* Kick off the first task. */
+		vStartFirstTask();
+	}
+
+	/* Should not get here as the tasks are now running! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+void vPortYield( void )
+{
+extern void VPortYieldASM( void );
+
+	/* Perform the context switch in a critical section to assure it is
+	not interrupted by the tick ISR.  It is not a problem to do this as
+	each task maintains it's own interrupt status. */
+	portENTER_CRITICAL();
+		/* Jump directly to the yield function to ensure there is no
+		compiler generated prologue code. */
+		asm volatile (	"bralid r14, VPortYieldASM		\n\t" \
+						"or r0, r0, r0					\n\t" );
+	portEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+XTmrCtr xTimer;
+const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+UBaseType_t uxMask;
+
+	/* The OPB timer1 is used to generate the tick.  Use the provided library
+	functions to enable the timer and set the tick frequency. */
+	XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID );
+	XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
+   	XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );
+	XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );
+
+	/* Set the timer interrupt enable bit while maintaining the other bit
+	states. */
+	uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
+	uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
+	XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );
+
+	XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
+	XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );
+	XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt handler placed in the interrupt vector when the scheduler is
+ * started.  The task context has already been saved when this is called.
+ * This handler determines the interrupt source and calls the relevant
+ * peripheral handler.
+ */
+void vTaskISRHandler( void )
+{
+static uint32_t ulPending;
+
+	/* Which interrupts are pending? */
+	ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );
+
+	if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS )
+	{
+		static XIntc_VectorTableEntry *pxTablePtr;
+		static XIntc_Config *pxConfig;
+		static uint32_t ulInterruptMask;
+
+		ulInterruptMask = ( uint32_t ) 1 << ulPending;
+
+		/* Get the configuration data using the device ID */
+		pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ];
+
+		pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
+		if( pxConfig->AckBeforeService & ( ulInterruptMask  ) )
+		{
+			XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
+			pxTablePtr->Handler( pxTablePtr->CallBackRef );
+		}
+		else
+		{
+			pxTablePtr->Handler( pxTablePtr->CallBackRef );
+			XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Handler for the timer interrupt.
+ */
+void vTickISR( void *pvBaseAddress )
+{
+uint32_t ulCSR;
+
+	/* Increment the RTOS tick - this might cause a task to unblock. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		vTaskSwitchContext();
+	}
+
+	/* Clear the timer interrupt */
+	ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0);
+	XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlaze/portasm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlaze/portasm.s
new file mode 100644
index 0000000..ddb525e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlaze/portasm.s
@@ -0,0 +1,197 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+	.extern pxCurrentTCB
+	.extern vTaskISRHandler
+	.extern vTaskSwitchContext
+	.extern uxCriticalNesting
+	.extern pulISRStack
+
+	.global __FreeRTOS_interrupt_handler
+	.global VPortYieldASM
+	.global vStartFirstTask
+
+
+.macro portSAVE_CONTEXT
+	/* Make room for the context on the stack. */
+	addik r1, r1, -132
+	/* Save r31 so it can then be used. */
+	swi r31, r1, 4
+	/* Copy the msr into r31 - this is stacked later. */
+	mfs r31, rmsr
+	/* Stack general registers. */
+	swi r30, r1, 12
+	swi r29, r1, 16
+	swi r28, r1, 20
+	swi r27, r1, 24
+	swi r26, r1, 28
+	swi r25, r1, 32
+	swi r24, r1, 36
+	swi r23, r1, 40
+	swi r22, r1, 44
+	swi r21, r1, 48
+	swi r20, r1, 52
+	swi r19, r1, 56
+	swi r18, r1, 60
+	swi r17, r1, 64
+	swi r16, r1, 68
+	swi r15, r1, 72
+	swi r13, r1, 80
+	swi r12, r1, 84
+	swi r11, r1, 88
+	swi r10, r1, 92
+	swi r9, r1, 96
+	swi r8, r1, 100
+	swi r7, r1, 104
+	swi r6, r1, 108
+	swi r5, r1, 112
+	swi r4, r1, 116
+	swi r3, r1, 120
+	swi r2, r1, 124
+	/* Stack the critical section nesting value. */
+	lwi r3, r0, uxCriticalNesting
+	swi r3, r1, 128
+	/* Save the top of stack value to the TCB. */
+	lwi r3, r0, pxCurrentTCB
+	sw	r1, r0, r3
+	
+	.endm
+
+.macro portRESTORE_CONTEXT
+	/* Load the top of stack value from the TCB. */
+	lwi r3, r0, pxCurrentTCB
+	lw	r1, r0, r3	
+	/* Restore the general registers. */
+	lwi r31, r1, 4		
+	lwi r30, r1, 12		
+	lwi r29, r1, 16	
+	lwi r28, r1, 20	
+	lwi r27, r1, 24	
+	lwi r26, r1, 28	
+	lwi r25, r1, 32	
+	lwi r24, r1, 36	
+	lwi r23, r1, 40	
+	lwi r22, r1, 44	
+	lwi r21, r1, 48	
+	lwi r20, r1, 52	
+	lwi r19, r1, 56	
+	lwi r18, r1, 60	
+	lwi r17, r1, 64	
+	lwi r16, r1, 68	
+	lwi r15, r1, 72	
+	lwi r14, r1, 76	
+	lwi r13, r1, 80	
+	lwi r12, r1, 84	
+	lwi r11, r1, 88	
+	lwi r10, r1, 92	
+	lwi r9, r1, 96	
+	lwi r8, r1, 100	
+	lwi r7, r1, 104
+	lwi r6, r1, 108
+	lwi r5, r1, 112
+	lwi r4, r1, 116
+	lwi r2, r1, 124
+
+	/* Load the critical nesting value. */
+	lwi r3, r1, 128
+	swi r3, r0, uxCriticalNesting
+
+	/* Obtain the MSR value from the stack. */
+	lwi r3, r1, 8
+
+	/* Are interrupts enabled in the MSR?  If so return using an return from 
+	interrupt instruction to ensure interrupts are enabled only once the task
+	is running again. */
+	andi r3, r3, 2
+	beqid r3, 36
+	or r0, r0, r0
+
+	/* Reload the rmsr from the stack, clear the enable interrupt bit in the
+	value before saving back to rmsr register, then return enabling interrupts
+	as we return. */
+	lwi r3, r1, 8
+	andi r3, r3, ~2
+	mts rmsr, r3
+	lwi r3, r1, 120
+	addik r1, r1, 132
+	rtid r14, 0
+	or r0, r0, r0
+
+	/* Reload the rmsr from the stack, place it in the rmsr register, and
+	return without enabling interrupts. */
+	lwi r3, r1, 8
+	mts rmsr, r3
+	lwi r3, r1, 120
+	addik r1, r1, 132
+	rtsd r14, 0
+	or r0, r0, r0
+
+	.endm
+
+	.text
+	.align  2
+
+
+__FreeRTOS_interrupt_handler:
+	portSAVE_CONTEXT
+	/* Entered via an interrupt so interrupts must be enabled in msr. */
+	ori r31, r31, 2
+	/* Stack msr. */
+	swi r31, r1, 8
+	/* Stack the return address.  As we entered via an interrupt we do
+	not need to modify the return address prior to stacking. */
+	swi r14, r1, 76
+	/* Now switch to use the ISR stack. */
+	lwi r3, r0, pulISRStack
+	add r1, r3, r0
+	bralid r15, vTaskISRHandler
+	or r0, r0, r0
+	portRESTORE_CONTEXT
+
+
+VPortYieldASM:
+	portSAVE_CONTEXT
+	/* Stack msr. */
+	swi r31, r1, 8
+	/* Modify the return address so we return to the instruction after the
+	exception. */
+	addi r14, r14, 8
+	swi r14, r1, 76
+	/* Now switch to use the ISR stack. */
+	lwi r3, r0, pulISRStack
+	add r1, r3, r0
+	bralid r15, vTaskSwitchContext
+	or r0, r0, r0
+	portRESTORE_CONTEXT
+
+vStartFirstTask:
+	portRESTORE_CONTEXT
+	
+	
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlaze/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlaze/portmacro.h
new file mode 100644
index 0000000..0c1f0bd
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlaze/portmacro.h
@@ -0,0 +1,126 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+void microblaze_disable_interrupts( void );
+void microblaze_enable_interrupts( void );
+#define portDISABLE_INTERRUPTS()	microblaze_disable_interrupts()
+#define portENABLE_INTERRUPTS()		microblaze_enable_interrupts()
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+#define portENTER_CRITICAL()		{														\
+										extern UBaseType_t uxCriticalNesting;	\
+										microblaze_disable_interrupts();					\
+										uxCriticalNesting++;								\
+									}
+
+#define portEXIT_CRITICAL()			{														\
+										extern UBaseType_t uxCriticalNesting;	\
+										/* Interrupts are disabled, so we can */			\
+										/* access the variable directly. */					\
+										uxCriticalNesting--;								\
+										if( uxCriticalNesting == 0 )			\
+										{													\
+											/* The nesting has unwound and we 				\
+											can enable interrupts again. */					\
+											portENABLE_INTERRUPTS();						\
+										}													\
+									}
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+void vPortYield( void );
+#define portYIELD() vPortYield()
+
+void vTaskSwitchContext();
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			4
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port.c
new file mode 100644
index 0000000..03ff93c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port.c
@@ -0,0 +1,452 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MicroBlaze port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <string.h>
+
+/* Hardware includes. */
+#include <xintc_i.h>
+#include <xil_exception.h>
+#include <microblaze_exceptions_g.h>
+
+/* Tasks are started with a critical section nesting of 0 - however, prior to
+the scheduler being commenced interrupts should not be enabled, so the critical
+nesting variable is initialised to a non-zero value. */
+#define portINITIAL_NESTING_VALUE	( 0xff )
+
+/* The bit within the MSR register that enabled/disables interrupts and 
+exceptions respectively. */
+#define portMSR_IE					( 0x02U )
+#define portMSR_EE					( 0x100U )
+
+/* If the floating point unit is included in the MicroBlaze build, then the
+FSR register is saved as part of the task context.  portINITIAL_FSR is the value
+given to the FSR register when the initial context is set up for a task being
+created. */
+#define portINITIAL_FSR				( 0U )
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the interrupt controller instance.
+ */
+static int32_t prvInitialiseInterruptController( void );
+
+/* Ensure the interrupt controller instance variable is initialised before it is
+ * used, and that the initialisation only happens once.
+ */
+static int32_t prvEnsureInterruptControllerIsInitialised( void );
+
+/*-----------------------------------------------------------*/
+
+/* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task
+maintains its own count, so this variable is saved as part of the task
+context. */
+volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
+
+/* This port uses a separate stack for interrupts.  This prevents the stack of
+every task needing to be large enough to hold an entire interrupt stack on top
+of the task stack. */
+uint32_t *pulISRStack;
+
+/* If an interrupt requests a context switch, then ulTaskSwitchRequested will
+get set to 1.  ulTaskSwitchRequested is inspected just before the main interrupt
+handler exits.  If, at that time, ulTaskSwitchRequested is set to 1, the kernel
+will call vTaskSwitchContext() to ensure the task that runs immediately after
+the interrupt exists is the highest priority task that is able to run.  This is
+an unusual mechanism, but is used for this port because a single interrupt can
+cause the servicing of multiple peripherals - and it is inefficient to call
+vTaskSwitchContext() multiple times as each peripheral is serviced. */
+volatile uint32_t ulTaskSwitchRequested = 0UL;
+
+/* The instance of the interrupt controller used by this port.  This is required
+by the Xilinx library API functions. */
+static XIntc xInterruptControllerInstance;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been made.
+ *
+ * See the portable.h header file.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+extern void *_SDA2_BASE_, *_SDA_BASE_;
+const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
+const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
+
+	/* Place a few bytes of known values on the bottom of the stack.
+	This is essential for the Microblaze port and these lines must
+	not be omitted. */
+	*pxTopOfStack = ( StackType_t ) 0x00000000;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00000000;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00000000;
+	pxTopOfStack--;
+
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+		/* The FSR value placed in the initial task context is just 0. */
+		*pxTopOfStack = portINITIAL_FSR;
+		pxTopOfStack--;
+	#endif
+
+	/* The MSR value placed in the initial task context should have interrupts
+	disabled.  Each task will enable interrupts automatically when it enters
+	the running state for the first time. */
+	*pxTopOfStack = mfmsr() & ~portMSR_IE;
+	
+	#if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
+	{
+		/* Ensure exceptions are enabled for the task. */
+		*pxTopOfStack |= portMSR_EE;
+	}
+	#endif
+
+	pxTopOfStack--;
+
+	/* First stack an initial value for the critical section nesting.  This
+	is initialised to zero. */
+	*pxTopOfStack = ( StackType_t ) 0x00;
+
+	/* R0 is always zero. */
+	/* R1 is the SP. */
+
+	/* Place an initial value for all the general purpose registers. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) ulR2;	/* R2 - read only small data area. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03;	/* R3 - return values and temporaries. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04;	/* R4 - return values and temporaries. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
+
+	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06;	/* R6 - other parameters and temporaries.  Used as the return address from vPortTaskEntryPoint. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07;	/* R7 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x08;	/* R8 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09;	/* R9 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x0a;	/* R10 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x0b;	/* R11 - temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x0c;	/* R12 - temporaries. */
+		pxTopOfStack--;
+	#else
+		pxTopOfStack-= 8;
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) ulR13;	/* R13 - read/write small data area. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;	/* R14 - return address for interrupt. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) NULL;	/* R15 - return address for subroutine. */
+
+	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10;	/* R16 - return address for trap (debugger). */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11;	/* R17 - return address for exceptions, if configured. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12;	/* R18 - reserved for assembler and compiler temporaries. */
+		pxTopOfStack--;
+	#else
+		pxTopOfStack -= 4;
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) 0x00;	/* R19 - must be saved across function calls. Callee-save.  Seems to be interpreted as the frame pointer. */
+
+	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x14;	/* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save.  Not used by FreeRTOS. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x15;	/* R21 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x16;	/* R22 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x17;	/* R23 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x18;	/* R24 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x19;	/* R25 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1a;	/* R26 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1b;	/* R27 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1c;	/* R28 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1d;	/* R29 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1e;	/* R30 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1f;	/* R31 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+	#else
+		pxTopOfStack -= 13;
+	#endif
+
+	/* Return a pointer to the top of the stack that has been generated so this
+	can	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void ( vPortStartFirstTask )( void );
+extern uint32_t _stack[];
+
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called.
+
+	This port uses an application defined callback function to install the tick
+	interrupt handler because the kernel will run on lots of different
+	MicroBlaze and FPGA configurations - not all of	which will have the same
+	timer peripherals defined or available.  An example definition of
+	vApplicationSetupTimerInterrupt() is provided in the official demo
+	application that accompanies this port. */
+	vApplicationSetupTimerInterrupt();
+
+	/* Reuse the stack from main() as the stack for the interrupts/exceptions. */
+	pulISRStack = ( uint32_t * ) _stack;
+
+	/* Ensure there is enough space for the functions called from the interrupt
+	service routines to write back into the stack frame of the caller. */
+	pulISRStack -= 2;
+
+	/* Restore the context of the first task that is going to run.  From here
+	on, the created tasks will be executing. */
+	vPortStartFirstTask();
+
+	/* Should not get here as the tasks are now running! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+void vPortYield( void )
+{
+extern void VPortYieldASM( void );
+
+	/* Perform the context switch in a critical section to assure it is
+	not interrupted by the tick ISR.  It is not a problem to do this as
+	each task maintains its own interrupt status. */
+	portENTER_CRITICAL();
+	{
+		/* Jump directly to the yield function to ensure there is no
+		compiler generated prologue code. */
+		asm volatile (	"bralid r14, VPortYieldASM		\n\t" \
+						"or r0, r0, r0					\n\t" );
+	}
+	portEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnableInterrupt( uint8_t ucInterruptID )
+{
+int32_t lReturn;
+
+	/* An API function is provided to enable an interrupt in the interrupt
+	controller because the interrupt controller instance variable is private
+	to this file. */
+	lReturn = prvEnsureInterruptControllerIsInitialised();
+	if( lReturn == pdPASS )
+	{
+		XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
+	}
+
+	configASSERT( lReturn );
+}
+/*-----------------------------------------------------------*/
+
+void vPortDisableInterrupt( uint8_t ucInterruptID )
+{
+int32_t lReturn;
+
+	/* An API function is provided to disable an interrupt in the interrupt
+	controller because the interrupt controller instance variable is private
+	to this file. */
+	lReturn = prvEnsureInterruptControllerIsInitialised();
+
+	if( lReturn == pdPASS )
+	{
+		XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
+	}
+
+	configASSERT( lReturn );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
+{
+int32_t lReturn;
+
+	/* An API function is provided to install an interrupt handler because the
+	interrupt controller instance variable is private to this file. */
+
+	lReturn = prvEnsureInterruptControllerIsInitialised();
+
+	if( lReturn == pdPASS )
+	{
+		lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
+	}
+
+	if( lReturn == XST_SUCCESS )
+	{
+		lReturn = pdPASS;
+	}
+
+	configASSERT( lReturn == pdPASS );
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+static int32_t prvEnsureInterruptControllerIsInitialised( void )
+{
+static int32_t lInterruptControllerInitialised = pdFALSE;
+int32_t lReturn;
+
+	/* Ensure the interrupt controller instance variable is initialised before
+	it is used, and that the initialisation only happens once. */
+	if( lInterruptControllerInitialised != pdTRUE )
+	{
+		lReturn = prvInitialiseInterruptController();
+
+		if( lReturn == pdPASS )
+		{
+			lInterruptControllerInitialised = pdTRUE;
+		}
+	}
+	else
+	{
+		lReturn = pdPASS;
+	}
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Handler for the timer interrupt.  This is the handler that the application
+ * defined callback function vApplicationSetupTimerInterrupt() should install.
+ */
+void vPortTickISR( void *pvUnused )
+{
+extern void vApplicationClearTimerInterrupt( void );
+
+	/* Ensure the unused parameter does not generate a compiler warning. */
+	( void ) pvUnused;
+
+	/* This port uses an application defined callback function to clear the tick
+	interrupt because the kernel will run on lots of different MicroBlaze and
+	FPGA configurations - not all of which will have the same timer peripherals
+	defined or available.  An example definition of
+	vApplicationClearTimerInterrupt() is provided in the official demo
+	application that accompanies this port. */
+	vApplicationClearTimerInterrupt();
+
+	/* Increment the RTOS tick - this might cause a task to unblock. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		/* Force vTaskSwitchContext() to be called as the interrupt exits. */
+		ulTaskSwitchRequested = 1;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static int32_t prvInitialiseInterruptController( void )
+{
+int32_t lStatus;
+
+	lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
+
+	if( lStatus == XST_SUCCESS )
+	{
+		/* Initialise the exception table. */
+		Xil_ExceptionInit();
+
+	    /* Service all pending interrupts each time the handler is entered. */
+	    XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
+
+	    /* Install exception handlers if the MicroBlaze is configured to handle
+	    exceptions, and the application defined constant
+	    configINSTALL_EXCEPTION_HANDLERS is set to 1. */
+		#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+	    {
+	    	vPortExceptionsInstallHandlers();
+	    }
+		#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
+
+		/* Start the interrupt controller.  Interrupts are enabled when the
+		scheduler starts. */
+		lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
+
+		if( lStatus == XST_SUCCESS )
+		{
+			lStatus = pdPASS;
+		}
+		else
+		{
+			lStatus = pdFAIL;
+		}
+	}
+
+	configASSERT( lStatus == pdPASS );
+
+	return lStatus;
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port_exceptions.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port_exceptions.c
new file mode 100644
index 0000000..47a639d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port_exceptions.c
@@ -0,0 +1,282 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Hardware includes. */
+#include <microblaze_exceptions_i.h>
+#include <microblaze_exceptions_g.h>
+
+/* The Xilinx library defined exception entry point stacks a number of
+registers.  These definitions are offsets from the stack pointer to the various
+stacked register values. */
+#define portexR3_STACK_OFFSET	4
+#define portexR4_STACK_OFFSET	5
+#define portexR5_STACK_OFFSET	6
+#define portexR6_STACK_OFFSET	7
+#define portexR7_STACK_OFFSET	8
+#define portexR8_STACK_OFFSET	9
+#define portexR9_STACK_OFFSET	10
+#define portexR10_STACK_OFFSET	11
+#define portexR11_STACK_OFFSET	12
+#define portexR12_STACK_OFFSET	13
+#define portexR15_STACK_OFFSET	16
+#define portexR18_STACK_OFFSET  19
+#define portexMSR_STACK_OFFSET	20
+#define portexR19_STACK_OFFSET  -1
+
+/* This is defined to equal the size, in bytes, of the stack frame generated by
+the Xilinx standard library exception entry point.  It is required to determine
+the stack pointer value prior to the exception being entered. */
+#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
+
+/* The number of bytes a MicroBlaze instruction consumes. */
+#define portexINSTRUCTION_SIZE	4
+
+/* Exclude this entire file if the MicroBlaze is not configured to handle
+exceptions, or the application defined configuration constant
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+
+/* This variable is set in the exception entry code, before
+vPortExceptionHandler is called. */
+uint32_t *pulStackPointerOnFunctionEntry = NULL;
+
+/* This is the structure that is filled with the MicroBlaze context as it
+existed immediately prior to the exception occurrence.  A pointer to this
+structure is passed into the vApplicationExceptionRegisterDump() callback
+function, if one is defined. */
+static xPortRegisterDump xRegisterDump;
+
+/* This is the FreeRTOS exception handler that is installed for all exception
+types.  It is called from vPortExceptionHanlderEntry() - which is itself defined
+in portasm.S. */
+void vPortExceptionHandler( void *pvExceptionID );
+extern void vPortExceptionHandlerEntry( void *pvExceptionID );
+
+/*-----------------------------------------------------------*/
+
+/* vApplicationExceptionRegisterDump() is a callback function that the
+application can optionally define to receive a populated xPortRegisterDump
+structure.  If the application chooses not to define a version of
+vApplicationExceptionRegisterDump() then this weekly defined default
+implementation will be called instead. */
+extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
+{
+	( void ) xRegisterDump;
+
+	for( ;; )
+	{
+		portNOP();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExceptionHandler( void *pvExceptionID )
+{
+extern void *pxCurrentTCB;
+
+	/* Fill an xPortRegisterDump structure with the MicroBlaze context as it
+	was immediately before the exception occurrence. */
+
+	/* First fill in the name and handle of the task that was in the Running
+	state when the exception occurred. */
+	xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
+	xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
+
+	configASSERT( pulStackPointerOnFunctionEntry );
+
+	/* Obtain the values of registers that were stacked prior to this function
+	being called, and may have changed since they were stacked. */
+	xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
+	xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
+	xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
+	xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
+	xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
+	xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
+	xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
+	xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
+	xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
+	xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
+	xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
+	xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
+	xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
+	xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
+
+	/* Obtain the value of all other registers. */
+	xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
+	xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
+	xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
+	xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
+	xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
+	xRegisterDump.ulR20 = mfgpr( R20 );
+	xRegisterDump.ulR21 = mfgpr( R21 );
+	xRegisterDump.ulR22 = mfgpr( R22 );
+	xRegisterDump.ulR23 = mfgpr( R23 );
+	xRegisterDump.ulR24 = mfgpr( R24 );
+	xRegisterDump.ulR25 = mfgpr( R25 );
+	xRegisterDump.ulR26 = mfgpr( R26 );
+	xRegisterDump.ulR27 = mfgpr( R27 );
+	xRegisterDump.ulR28 = mfgpr( R28 );
+	xRegisterDump.ulR29 = mfgpr( R29 );
+	xRegisterDump.ulR30 = mfgpr( R30 );
+	xRegisterDump.ulR31 = mfgpr( R31 );
+	xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
+	xRegisterDump.ulEAR = mfear();
+	xRegisterDump.ulESR = mfesr();
+	xRegisterDump.ulEDR = mfedr();
+
+	/* Move the saved program counter back to the instruction that was executed
+	when the exception occurred.  This is only valid for certain types of
+	exception. */
+	xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
+
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+	{
+		xRegisterDump.ulFSR = mffsr();
+	}
+	#else
+	{
+		xRegisterDump.ulFSR = 0UL;
+	}
+	#endif
+
+	/* Also fill in a string that describes what type of exception this is.
+	The string uses the same ID names as defined in the MicroBlaze standard
+	library exception header files. */
+	switch( ( uint32_t ) pvExceptionID )
+	{
+		case XEXC_ID_FSL :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
+				break;
+
+		case XEXC_ID_UNALIGNED_ACCESS :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
+				break;
+
+		case XEXC_ID_ILLEGAL_OPCODE :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
+				break;
+
+		case XEXC_ID_M_AXI_I_EXCEPTION :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
+				break;
+
+		case XEXC_ID_M_AXI_D_EXCEPTION :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
+				break;
+
+		case XEXC_ID_DIV_BY_ZERO :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
+				break;
+
+		case XEXC_ID_STACK_VIOLATION :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
+				break;
+
+		#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+
+			case XEXC_ID_FPU :
+						xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
+						break;
+
+		#endif /* XPAR_MICROBLAZE_USE_FPU */
+	}
+
+	/* vApplicationExceptionRegisterDump() is a callback function that the
+	application can optionally define to receive the populated xPortRegisterDump
+	structure.  If the application chooses not to define a version of
+	vApplicationExceptionRegisterDump() then the weekly defined default
+	implementation within this file will be called instead. */
+	vApplicationExceptionRegisterDump( &xRegisterDump );
+
+	/* Must not attempt to leave this function! */
+	for( ;; )
+	{
+		portNOP();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExceptionsInstallHandlers( void )
+{
+static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
+
+	if( ulHandlersAlreadyInstalled == pdFALSE )
+	{
+		ulHandlersAlreadyInstalled = pdTRUE;
+
+		#if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
+			microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
+		#endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
+
+		#if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
+		#endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
+		#endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
+		#endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
+		#endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
+		#endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
+		#endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
+		#endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
+		#endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
+
+		microblaze_enable_exceptions();
+	}
+}
+
+/* Exclude the entire file if the MicroBlaze is not configured to handle
+exceptions, or the application defined configuration item
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portasm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portasm.S
new file mode 100644
index 0000000..9243703
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portasm.S
@@ -0,0 +1,328 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/* Xilinx library includes. */
+#include "microblaze_exceptions_g.h"
+#include "xparameters.h"
+
+/* The context is oversized to allow functions called from the ISR to write
+back into the caller stack. */
+#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+	#define portCONTEXT_SIZE 136
+	#define portMINUS_CONTEXT_SIZE -136
+#else
+	#define portCONTEXT_SIZE 132
+	#define portMINUS_CONTEXT_SIZE -132
+#endif
+
+/* Offsets from the stack pointer at which saved registers are placed. */
+#define portR31_OFFSET	4
+#define portR30_OFFSET	8
+#define portR29_OFFSET	12
+#define portR28_OFFSET	16
+#define portR27_OFFSET	20
+#define portR26_OFFSET	24
+#define portR25_OFFSET	28
+#define portR24_OFFSET	32
+#define portR23_OFFSET	36
+#define portR22_OFFSET	40
+#define portR21_OFFSET	44
+#define portR20_OFFSET	48
+#define portR19_OFFSET	52
+#define portR18_OFFSET	56
+#define portR17_OFFSET	60
+#define portR16_OFFSET	64
+#define portR15_OFFSET	68
+#define portR14_OFFSET	72
+#define portR13_OFFSET	76
+#define portR12_OFFSET	80
+#define portR11_OFFSET	84
+#define portR10_OFFSET	88
+#define portR9_OFFSET	92
+#define portR8_OFFSET	96
+#define portR7_OFFSET	100
+#define portR6_OFFSET	104
+#define portR5_OFFSET	108
+#define portR4_OFFSET	112
+#define portR3_OFFSET	116
+#define portR2_OFFSET	120
+#define portCRITICAL_NESTING_OFFSET 124
+#define portMSR_OFFSET 128
+#define portFSR_OFFSET 132
+
+	.extern pxCurrentTCB
+	.extern XIntc_DeviceInterruptHandler
+	.extern vTaskSwitchContext
+	.extern uxCriticalNesting
+	.extern pulISRStack
+	.extern ulTaskSwitchRequested
+	.extern vPortExceptionHandler
+	.extern pulStackPointerOnFunctionEntry
+
+	.global _interrupt_handler
+	.global VPortYieldASM
+	.global vPortStartFirstTask
+	.global vPortExceptionHandlerEntry
+
+
+.macro portSAVE_CONTEXT
+
+	/* Make room for the context on the stack. */
+	addik r1, r1, portMINUS_CONTEXT_SIZE
+
+	/* Stack general registers. */
+	swi r31, r1, portR31_OFFSET
+	swi r30, r1, portR30_OFFSET
+	swi r29, r1, portR29_OFFSET
+	swi r28, r1, portR28_OFFSET
+	swi r27, r1, portR27_OFFSET
+	swi r26, r1, portR26_OFFSET
+	swi r25, r1, portR25_OFFSET
+	swi r24, r1, portR24_OFFSET
+	swi r23, r1, portR23_OFFSET
+	swi r22, r1, portR22_OFFSET
+	swi r21, r1, portR21_OFFSET
+	swi r20, r1, portR20_OFFSET
+	swi r19, r1, portR19_OFFSET
+	swi r18, r1, portR18_OFFSET
+	swi r17, r1, portR17_OFFSET
+	swi r16, r1, portR16_OFFSET
+	swi r15, r1, portR15_OFFSET
+	/* R14 is saved later as it needs adjustment if a yield is performed. */
+	swi r13, r1, portR13_OFFSET
+	swi r12, r1, portR12_OFFSET
+	swi r11, r1, portR11_OFFSET
+	swi r10, r1, portR10_OFFSET
+	swi r9, r1, portR9_OFFSET
+	swi r8, r1, portR8_OFFSET
+	swi r7, r1, portR7_OFFSET
+	swi r6, r1, portR6_OFFSET
+	swi r5, r1, portR5_OFFSET
+	swi r4, r1, portR4_OFFSET
+	swi r3, r1, portR3_OFFSET
+	swi r2, r1, portR2_OFFSET
+
+	/* Stack the critical section nesting value. */
+	lwi r18, r0, uxCriticalNesting
+	swi r18, r1, portCRITICAL_NESTING_OFFSET
+
+	/* Stack MSR. */
+	mfs r18, rmsr
+	swi r18, r1, portMSR_OFFSET
+
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+		/* Stack FSR. */
+		mfs r18, rfsr
+		swi r18, r1, portFSR_OFFSET
+	#endif
+
+	/* Save the top of stack value to the TCB. */
+	lwi r3, r0, pxCurrentTCB
+	sw	r1, r0, r3
+
+	.endm
+
+.macro portRESTORE_CONTEXT
+
+	/* Load the top of stack value from the TCB. */
+	lwi r18, r0, pxCurrentTCB
+	lw	r1, r0, r18
+
+	/* Restore the general registers. */
+	lwi r31, r1, portR31_OFFSET
+	lwi r30, r1, portR30_OFFSET
+	lwi r29, r1, portR29_OFFSET
+	lwi r28, r1, portR28_OFFSET
+	lwi r27, r1, portR27_OFFSET
+	lwi r26, r1, portR26_OFFSET
+	lwi r25, r1, portR25_OFFSET
+	lwi r24, r1, portR24_OFFSET
+	lwi r23, r1, portR23_OFFSET
+	lwi r22, r1, portR22_OFFSET
+	lwi r21, r1, portR21_OFFSET
+	lwi r20, r1, portR20_OFFSET
+	lwi r19, r1, portR19_OFFSET
+	lwi r17, r1, portR17_OFFSET
+	lwi r16, r1, portR16_OFFSET
+	lwi r15, r1, portR15_OFFSET
+	lwi r14, r1, portR14_OFFSET
+	lwi r13, r1, portR13_OFFSET
+	lwi r12, r1, portR12_OFFSET
+	lwi r11, r1, portR11_OFFSET
+	lwi r10, r1, portR10_OFFSET
+	lwi r9, r1, portR9_OFFSET
+	lwi r8, r1, portR8_OFFSET
+	lwi r7, r1, portR7_OFFSET
+	lwi r6, r1, portR6_OFFSET
+	lwi r5, r1, portR5_OFFSET
+	lwi r4, r1, portR4_OFFSET
+	lwi r3, r1, portR3_OFFSET
+	lwi r2, r1, portR2_OFFSET
+
+	/* Reload the rmsr from the stack. */
+	lwi r18, r1, portMSR_OFFSET
+	mts rmsr, r18
+
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+		/* Reload the FSR from the stack. */
+		lwi r18, r1, portFSR_OFFSET
+		mts rfsr, r18
+	#endif
+
+	/* Load the critical nesting value. */
+	lwi r18, r1, portCRITICAL_NESTING_OFFSET
+	swi r18, r0, uxCriticalNesting
+
+	/* Test the critical nesting value.  If it is non zero then the task last
+	exited the running state using a yield.  If it is zero, then the task
+	last exited the running state through an interrupt. */
+	xori r18, r18, 0
+	bnei r18, exit_from_yield
+
+	/* r18 was being used as a temporary.  Now restore its true value from the
+	stack. */
+	lwi r18, r1, portR18_OFFSET
+
+	/* Remove the stack frame. */
+	addik r1, r1, portCONTEXT_SIZE
+
+	/* Return using rtid so interrupts are re-enabled as this function is
+	exited. */
+	rtid r14, 0
+	or r0, r0, r0
+
+	.endm
+
+/* This function is used to exit portRESTORE_CONTEXT() if the task being
+returned to last left the Running state by calling taskYIELD() (rather than
+being preempted by an interrupt). */
+	.text
+	.align  4
+exit_from_yield:
+
+	/* r18 was being used as a temporary.  Now restore its true value from the
+	stack. */
+	lwi r18, r1, portR18_OFFSET
+
+	/* Remove the stack frame. */
+	addik r1, r1, portCONTEXT_SIZE
+
+	/* Return to the task. */
+	rtsd r14, 0
+	or r0, r0, r0
+
+
+	.text
+	.align  4
+_interrupt_handler:
+
+	portSAVE_CONTEXT
+
+	/* Stack the return address. */
+	swi r14, r1, portR14_OFFSET
+
+	/* Switch to the ISR stack. */
+	lwi r1, r0, pulISRStack
+
+	/* The parameter to the interrupt handler. */
+	ori r5, r0, configINTERRUPT_CONTROLLER_TO_USE
+
+	/* Execute any pending interrupts. */
+	bralid r15, XIntc_DeviceInterruptHandler
+	or r0, r0, r0
+
+	/* See if a new task should be selected to execute. */
+	lwi r18, r0, ulTaskSwitchRequested
+	or r18, r18, r0
+
+	/* If ulTaskSwitchRequested is already zero, then jump straight to
+	restoring the task that is already in the Running state. */
+	beqi r18, task_switch_not_requested
+
+	/* Set ulTaskSwitchRequested back to zero as a task switch is about to be
+	performed. */
+	swi r0, r0, ulTaskSwitchRequested
+
+	/* ulTaskSwitchRequested was not 0 when tested.  Select the next task to
+	execute. */
+	bralid r15, vTaskSwitchContext
+	or r0, r0, r0
+
+task_switch_not_requested:
+
+	/* Restore the context of the next task scheduled to execute. */
+	portRESTORE_CONTEXT
+
+
+	.text
+	.align  4
+VPortYieldASM:
+
+	portSAVE_CONTEXT
+
+	/* Modify the return address so a return is done to the instruction after
+	the call to VPortYieldASM. */
+	addi r14, r14, 8
+	swi r14, r1, portR14_OFFSET
+
+	/* Switch to use the ISR stack. */
+	lwi r1, r0, pulISRStack
+
+	/* Select the next task to execute. */
+	bralid r15, vTaskSwitchContext
+	or r0, r0, r0
+
+	/* Restore the context of the next task scheduled to execute. */
+	portRESTORE_CONTEXT
+
+	.text
+	.align  4
+vPortStartFirstTask:
+
+	portRESTORE_CONTEXT
+
+
+
+#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+
+	.text
+	.align 4
+vPortExceptionHandlerEntry:
+
+	/* Take a copy of the stack pointer before vPortExecptionHandler is called,
+	storing its value prior to the function stack frame being created. */
+	swi r1, r0, pulStackPointerOnFunctionEntry
+	bralid r15, vPortExceptionHandler
+	or r0, r0, r0
+
+#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portmacro.h
new file mode 100644
index 0000000..2985761
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portmacro.h
@@ -0,0 +1,369 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* BSP includes. */
+#include <mb_interface.h>
+#include <xparameters.h>
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros and functions. */
+void microblaze_disable_interrupts( void );
+void microblaze_enable_interrupts( void );
+#define portDISABLE_INTERRUPTS()	microblaze_disable_interrupts()
+#define portENABLE_INTERRUPTS()		microblaze_enable_interrupts()
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+#define portENTER_CRITICAL()		{																\
+										extern volatile UBaseType_t uxCriticalNesting;				\
+										microblaze_disable_interrupts();							\
+										uxCriticalNesting++;										\
+									}
+
+#define portEXIT_CRITICAL()			{																\
+										extern volatile UBaseType_t uxCriticalNesting;				\
+										/* Interrupts are disabled, so we can */					\
+										/* access the variable directly. */							\
+										uxCriticalNesting--;										\
+										if( uxCriticalNesting == 0 )								\
+										{															\
+											/* The nesting has unwound and we 						\
+											can enable interrupts again. */							\
+											portENABLE_INTERRUPTS();								\
+										}															\
+									}
+
+/*-----------------------------------------------------------*/
+
+/* The yield macro maps directly to the vPortYield() function. */
+void vPortYield( void );
+#define portYIELD() vPortYield()
+
+/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead
+sets a flag to say that a yield has been requested.  The interrupt exit code
+then checks this flag, and calls vTaskSwitchContext() before restoring a task
+context, if the flag is not false.  This is done to prevent multiple calls to
+vTaskSwitchContext() being made from a single interrupt, as a single interrupt
+can result in multiple peripherals being serviced. */
+extern volatile uint32_t ulTaskSwitchRequested;
+#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
+
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+	/* Generic helper function. */
+	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+	{
+	uint8_t ucReturn;
+
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+		return ucReturn;
+	}
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			4
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* The following structure is used by the FreeRTOS exception handler.  It is
+filled with the MicroBlaze context as it was at the time the exception occurred.
+This is done as an aid to debugging exception occurrences. */
+typedef struct PORT_REGISTER_DUMP
+{
+	/* The following structure members hold the values of the MicroBlaze
+	registers at the time the exception was raised. */
+	uint32_t ulR1_SP;
+	uint32_t ulR2_small_data_area;
+	uint32_t ulR3;
+	uint32_t ulR4;
+	uint32_t ulR5;
+	uint32_t ulR6;
+	uint32_t ulR7;
+	uint32_t ulR8;
+	uint32_t ulR9;
+	uint32_t ulR10;
+	uint32_t ulR11;
+	uint32_t ulR12;
+	uint32_t ulR13_read_write_small_data_area;
+	uint32_t ulR14_return_address_from_interrupt;
+	uint32_t ulR15_return_address_from_subroutine;
+	uint32_t ulR16_return_address_from_trap;
+	uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
+	uint32_t ulR18;
+	uint32_t ulR19;
+	uint32_t ulR20;
+	uint32_t ulR21;
+	uint32_t ulR22;
+	uint32_t ulR23;
+	uint32_t ulR24;
+	uint32_t ulR25;
+	uint32_t ulR26;
+	uint32_t ulR27;
+	uint32_t ulR28;
+	uint32_t ulR29;
+	uint32_t ulR30;
+	uint32_t ulR31;
+	uint32_t ulPC;
+	uint32_t ulESR;
+	uint32_t ulMSR;
+	uint32_t ulEAR;
+	uint32_t ulFSR;
+	uint32_t ulEDR;
+
+	/* A human readable description of the exception cause.  The strings used
+	are the same as the #define constant names found in the
+	microblaze_exceptions_i.h header file */
+	int8_t *pcExceptionCause;
+
+	/* The human readable name of the task that was running at the time the
+	exception occurred.  This is the name that was given to the task when the
+	task was created using the FreeRTOS xTaskCreate() API function. */
+	char *pcCurrentTaskName;
+
+	/* The handle of the task that was running a the time the exception
+	occurred. */
+	void * xCurrentTaskHandle;
+
+} xPortRegisterDump;
+
+
+/*
+ * Installs pxHandler as the interrupt handler for the peripheral specified by
+ * the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have pxHandler assigned as its interrupt
+ * handler.  Peripheral IDs are defined in the xparameters.h header file, which
+ * is itself part of the BSP project.  For example, in the official demo
+ * application for this port, xparameters.h defines the following IDs for the
+ * four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
+ *
+ *
+ * pxHandler:
+ *
+ * A pointer to the interrupt handler function itself.  This must be a void
+ * function that takes a (void *) parameter.
+ *
+ *
+ * pvCallBackRef:
+ *
+ * The parameter passed into the handler function.  In many cases this will not
+ * be used and can be NULL.  Some times it is used to pass in a reference to
+ * the peripheral instance variable, so it can be accessed from inside the
+ * handler function.
+ *
+ *
+ * pdPASS is returned if the function executes successfully.  Any other value
+ * being returned indicates that the function did not execute correctly.
+ */
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
+
+
+/*
+ * Enables the interrupt, within the interrupt controller, for the peripheral
+ * specified by the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have its interrupt enabled in the
+ * interrupt controller.  Peripheral IDs are defined in the xparameters.h header
+ * file, which is itself part of the BSP project.  For example, in the official
+ * demo application for this port, xparameters.h defines the following IDs for
+ * the four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
+ *
+ */
+void vPortEnableInterrupt( uint8_t ucInterruptID );
+
+/*
+ * Disables the interrupt, within the interrupt controller, for the peripheral
+ * specified by the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have its interrupt disabled in the
+ * interrupt controller.  Peripheral IDs are defined in the xparameters.h header
+ * file, which is itself part of the BSP project.  For example, in the official
+ * demo application for this port, xparameters.h defines the following IDs for
+ * the four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
+ *
+ */
+void vPortDisableInterrupt( uint8_t ucInterruptID );
+
+/*
+ * This is an application defined callback function used to install the tick
+ * interrupt handler.  It is provided as an application callback because the
+ * kernel will run on lots of different MicroBlaze and FPGA configurations - not
+ * all of which will have the same timer peripherals defined or available.  This
+ * example uses the AXI Timer 0.  If that is available on your hardware platform
+ * then this example callback implementation should not require modification.
+ * The name of the interrupt handler that should be installed is vPortTickISR(),
+ * which the function below declares as an extern.
+ */
+void vApplicationSetupTimerInterrupt( void );
+
+/*
+ * This is an application defined callback function used to clear whichever
+ * interrupt was installed by the the vApplicationSetupTimerInterrupt() callback
+ * function - in this case the interrupt generated by the AXI timer.  It is
+ * provided as an application callback because the kernel will run on lots of
+ * different MicroBlaze and FPGA configurations - not all of which will have the
+ * same timer peripherals defined or available.  This example uses the AXI Timer 0.
+ * If that is available on your hardware platform then this example callback
+ * implementation should not require modification provided the example definition
+ * of vApplicationSetupTimerInterrupt() is also not modified.
+ */
+void vApplicationClearTimerInterrupt( void );
+
+/*
+ * vPortExceptionsInstallHandlers() is only available when the MicroBlaze
+ * is configured to include exception functionality, and
+ * configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h.
+ *
+ * vPortExceptionsInstallHandlers() installs the FreeRTOS exception handler
+ * for every possible exception cause.
+ *
+ * vPortExceptionsInstallHandlers() can be called explicitly from application
+ * code.  After that is done, the default FreeRTOS exception handler that will
+ * have been installed can be replaced for any specific exception cause by using
+ * the standard Xilinx library function microblaze_register_exception_handler().
+ *
+ * If vPortExceptionsInstallHandlers() is not called explicitly by the
+ * application, it will be called automatically by the kernel the first time
+ * xPortInstallInterruptHandler() is called.  At that time, any exception
+ * handlers that may have already been installed will be replaced.
+ *
+ * See the description of vApplicationExceptionRegisterDump() for information
+ * on the processing performed by the FreeRTOS exception handler.
+ */
+void vPortExceptionsInstallHandlers( void );
+
+/*
+ * The FreeRTOS exception handler fills an xPortRegisterDump structure (defined
+ * in portmacro.h) with the MicroBlaze context, as it was at the time the
+ * exception occurred.  The exception handler then calls
+ * vApplicationExceptionRegisterDump(), passing in the completed
+ * xPortRegisterDump structure as its parameter.
+ *
+ * The FreeRTOS kernel provides its own implementation of
+ * vApplicationExceptionRegisterDump(), but the kernel provided implementation
+ * is declared as being 'weak'.  The weak definition allows the application
+ * writer to provide their own implementation, should they wish to use the
+ * register dump information.  For example, an implementation could be provided
+ * that wrote the register dump data to a display, or a UART port.
+ */
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump );
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c
new file mode 100644
index 0000000..8035415
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c
@@ -0,0 +1,460 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MicroBlaze port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Standard includes. */
+#include <string.h>
+
+/* Hardware includes. */
+#include <xintc_i.h>
+#include <xil_exception.h>
+#include <microblaze_exceptions_g.h>
+
+/* Tasks are started with a critical section nesting of 0 - however, prior to
+the scheduler being commenced interrupts should not be enabled, so the critical
+nesting variable is initialised to a non-zero value. */
+#define portINITIAL_NESTING_VALUE	( 0xff )
+
+/* The bit within the MSR register that enabled/disables interrupts and
+exceptions respectively. */
+#define portMSR_IE					( 0x02U )
+#define portMSR_EE					( 0x100U )
+
+/* If the floating point unit is included in the MicroBlaze build, then the
+FSR register is saved as part of the task context.  portINITIAL_FSR is the value
+given to the FSR register when the initial context is set up for a task being
+created. */
+#define portINITIAL_FSR				( 0U )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the interrupt controller instance.
+ */
+static int32_t prvInitialiseInterruptController( void );
+
+/* Ensure the interrupt controller instance variable is initialised before it is
+ * used, and that the initialisation only happens once.
+ */
+static int32_t prvEnsureInterruptControllerIsInitialised( void );
+
+/*-----------------------------------------------------------*/
+
+/* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task
+maintains its own count, so this variable is saved as part of the task
+context. */
+volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
+
+/* This port uses a separate stack for interrupts.  This prevents the stack of
+every task needing to be large enough to hold an entire interrupt stack on top
+of the task stack. */
+uint32_t *pulISRStack;
+
+/* If an interrupt requests a context switch, then ulTaskSwitchRequested will
+get set to 1.  ulTaskSwitchRequested is inspected just before the main interrupt
+handler exits.  If, at that time, ulTaskSwitchRequested is set to 1, the kernel
+will call vTaskSwitchContext() to ensure the task that runs immediately after
+the interrupt exists is the highest priority task that is able to run.  This is
+an unusual mechanism, but is used for this port because a single interrupt can
+cause the servicing of multiple peripherals - and it is inefficient to call
+vTaskSwitchContext() multiple times as each peripheral is serviced. */
+volatile uint32_t ulTaskSwitchRequested = 0UL;
+
+/* The instance of the interrupt controller used by this port.  This is required
+by the Xilinx library API functions. */
+static XIntc xInterruptControllerInstance;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been made.
+ *
+ * See the portable.h header file.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+extern void *_SDA2_BASE_, *_SDA_BASE_;
+const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
+const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
+extern void _start1( void );
+
+	/* Place a few bytes of known values on the bottom of the stack.
+	This is essential for the Microblaze port and these lines must
+	not be omitted. */
+	*pxTopOfStack = ( StackType_t ) 0x00000000;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00000000;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00000000;
+	pxTopOfStack--;
+
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+		/* The FSR value placed in the initial task context is just 0. */
+		*pxTopOfStack = portINITIAL_FSR;
+		pxTopOfStack--;
+	#endif
+
+	/* The MSR value placed in the initial task context should have interrupts
+	disabled.  Each task will enable interrupts automatically when it enters
+	the running state for the first time. */
+	*pxTopOfStack = mfmsr() & ~portMSR_IE;
+
+	#if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
+	{
+		/* Ensure exceptions are enabled for the task. */
+		*pxTopOfStack |= portMSR_EE;
+	}
+	#endif
+
+	pxTopOfStack--;
+
+	/* First stack an initial value for the critical section nesting.  This
+	is initialised to zero. */
+	*pxTopOfStack = ( StackType_t ) 0x00;
+
+	/* R0 is always zero. */
+	/* R1 is the SP. */
+
+	/* Place an initial value for all the general purpose registers. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) ulR2;	/* R2 - read only small data area. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03;	/* R3 - return values and temporaries. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04;	/* R4 - return values and temporaries. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
+
+	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x06;	/* R6 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x07;	/* R7 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) NULL;	/* R8 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x09;	/* R9 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x0a;	/* R10 - other parameters and temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x0b;	/* R11 - temporaries. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x0c;	/* R12 - temporaries. */
+		pxTopOfStack--;
+	#else
+		pxTopOfStack-= 8;
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) ulR13;	/* R13 - read/write small data area. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;	/* R14 - return address for interrupt. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) _start1;	/* R15 - return address for subroutine. */
+
+	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x10;	/* R16 - return address for trap (debugger). */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x11;	/* R17 - return address for exceptions, if configured. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x12;	/* R18 - reserved for assembler and compiler temporaries. */
+		pxTopOfStack--;
+	#else
+		pxTopOfStack -= 4;
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) 0x00;	/* R19 - must be saved across function calls. Callee-save.  Seems to be interpreted as the frame pointer. */
+
+	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x14;	/* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save.  Not used by FreeRTOS. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x15;	/* R21 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x16;	/* R22 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x17;	/* R23 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x18;	/* R24 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x19;	/* R25 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1a;	/* R26 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1b;	/* R27 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1c;	/* R28 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1d;	/* R29 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1e;	/* R30 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x1f;	/* R31 - must be saved across function calls. Callee-save. */
+		pxTopOfStack--;
+	#else
+		pxTopOfStack -= 13;
+	#endif
+
+	/* Return a pointer to the top of the stack that has been generated so this
+	can	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void ( vPortStartFirstTask )( void );
+extern uint32_t _stack[];
+
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called.
+
+	This port uses an application defined callback function to install the tick
+	interrupt handler because the kernel will run on lots of different
+	MicroBlaze and FPGA configurations - not all of	which will have the same
+	timer peripherals defined or available.  An example definition of
+	vApplicationSetupTimerInterrupt() is provided in the official demo
+	application that accompanies this port. */
+	vApplicationSetupTimerInterrupt();
+
+	/* Reuse the stack from main() as the stack for the interrupts/exceptions. */
+	pulISRStack = ( uint32_t * ) _stack;
+
+	/* Ensure there is enough space for the functions called from the interrupt
+	service routines to write back into the stack frame of the caller. */
+	pulISRStack -= 2;
+
+	/* Restore the context of the first task that is going to run.  From here
+	on, the created tasks will be executing. */
+	vPortStartFirstTask();
+
+	/* Should not get here as the tasks are now running! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+void vPortYield( void )
+{
+extern void VPortYieldASM( void );
+
+	/* Perform the context switch in a critical section to assure it is
+	not interrupted by the tick ISR.  It is not a problem to do this as
+	each task maintains its own interrupt status. */
+	portENTER_CRITICAL();
+	{
+		/* Jump directly to the yield function to ensure there is no
+		compiler generated prologue code. */
+		asm volatile (	"bralid r14, VPortYieldASM		\n\t" \
+						"or r0, r0, r0					\n\t" );
+	}
+	portEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnableInterrupt( uint8_t ucInterruptID )
+{
+int32_t lReturn;
+
+	/* An API function is provided to enable an interrupt in the interrupt
+	controller because the interrupt controller instance variable is private
+	to this file. */
+	lReturn = prvEnsureInterruptControllerIsInitialised();
+	if( lReturn == pdPASS )
+	{
+		/* Critical section protects read/modify/writer operation inside
+		XIntc_Enable(). */
+		portENTER_CRITICAL();
+		{
+			XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
+		}
+		portEXIT_CRITICAL();
+	}
+
+	configASSERT( lReturn );
+}
+/*-----------------------------------------------------------*/
+
+void vPortDisableInterrupt( uint8_t ucInterruptID )
+{
+int32_t lReturn;
+
+	/* An API function is provided to disable an interrupt in the interrupt
+	controller because the interrupt controller instance variable is private
+	to this file. */
+	lReturn = prvEnsureInterruptControllerIsInitialised();
+
+	if( lReturn == pdPASS )
+	{
+		XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
+	}
+
+	configASSERT( lReturn );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
+{
+int32_t lReturn;
+
+	/* An API function is provided to install an interrupt handler because the
+	interrupt controller instance variable is private to this file. */
+
+	lReturn = prvEnsureInterruptControllerIsInitialised();
+
+	if( lReturn == pdPASS )
+	{
+		lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
+	}
+
+	if( lReturn == XST_SUCCESS )
+	{
+		lReturn = pdPASS;
+	}
+
+	configASSERT( lReturn == pdPASS );
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+static int32_t prvEnsureInterruptControllerIsInitialised( void )
+{
+static int32_t lInterruptControllerInitialised = pdFALSE;
+int32_t lReturn;
+
+	/* Ensure the interrupt controller instance variable is initialised before
+	it is used, and that the initialisation only happens once. */
+	if( lInterruptControllerInitialised != pdTRUE )
+	{
+		lReturn = prvInitialiseInterruptController();
+
+		if( lReturn == pdPASS )
+		{
+			lInterruptControllerInitialised = pdTRUE;
+		}
+	}
+	else
+	{
+		lReturn = pdPASS;
+	}
+
+	return lReturn;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Handler for the timer interrupt.  This is the handler that the application
+ * defined callback function vApplicationSetupTimerInterrupt() should install.
+ */
+void vPortTickISR( void *pvUnused )
+{
+extern void vApplicationClearTimerInterrupt( void );
+
+	/* Ensure the unused parameter does not generate a compiler warning. */
+	( void ) pvUnused;
+
+	/* This port uses an application defined callback function to clear the tick
+	interrupt because the kernel will run on lots of different MicroBlaze and
+	FPGA configurations - not all of which will have the same timer peripherals
+	defined or available.  An example definition of
+	vApplicationClearTimerInterrupt() is provided in the official demo
+	application that accompanies this port. */
+	vApplicationClearTimerInterrupt();
+
+	/* Increment the RTOS tick - this might cause a task to unblock. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		/* Force vTaskSwitchContext() to be called as the interrupt exits. */
+		ulTaskSwitchRequested = 1;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static int32_t prvInitialiseInterruptController( void )
+{
+int32_t lStatus;
+
+	lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
+
+	if( lStatus == XST_SUCCESS )
+	{
+		/* Initialise the exception table. */
+		Xil_ExceptionInit();
+
+	    /* Service all pending interrupts each time the handler is entered. */
+	    XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
+
+	    /* Install exception handlers if the MicroBlaze is configured to handle
+	    exceptions, and the application defined constant
+	    configINSTALL_EXCEPTION_HANDLERS is set to 1. */
+		#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+	    {
+	    	vPortExceptionsInstallHandlers();
+	    }
+		#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
+
+		/* Start the interrupt controller.  Interrupts are enabled when the
+		scheduler starts. */
+		lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
+
+		if( lStatus == XST_SUCCESS )
+		{
+			lStatus = pdPASS;
+		}
+		else
+		{
+			lStatus = pdFAIL;
+		}
+	}
+
+	configASSERT( lStatus == pdPASS );
+
+	return lStatus;
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port_exceptions.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port_exceptions.c
new file mode 100644
index 0000000..47a639d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port_exceptions.c
@@ -0,0 +1,282 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Hardware includes. */
+#include <microblaze_exceptions_i.h>
+#include <microblaze_exceptions_g.h>
+
+/* The Xilinx library defined exception entry point stacks a number of
+registers.  These definitions are offsets from the stack pointer to the various
+stacked register values. */
+#define portexR3_STACK_OFFSET	4
+#define portexR4_STACK_OFFSET	5
+#define portexR5_STACK_OFFSET	6
+#define portexR6_STACK_OFFSET	7
+#define portexR7_STACK_OFFSET	8
+#define portexR8_STACK_OFFSET	9
+#define portexR9_STACK_OFFSET	10
+#define portexR10_STACK_OFFSET	11
+#define portexR11_STACK_OFFSET	12
+#define portexR12_STACK_OFFSET	13
+#define portexR15_STACK_OFFSET	16
+#define portexR18_STACK_OFFSET  19
+#define portexMSR_STACK_OFFSET	20
+#define portexR19_STACK_OFFSET  -1
+
+/* This is defined to equal the size, in bytes, of the stack frame generated by
+the Xilinx standard library exception entry point.  It is required to determine
+the stack pointer value prior to the exception being entered. */
+#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
+
+/* The number of bytes a MicroBlaze instruction consumes. */
+#define portexINSTRUCTION_SIZE	4
+
+/* Exclude this entire file if the MicroBlaze is not configured to handle
+exceptions, or the application defined configuration constant
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+
+/* This variable is set in the exception entry code, before
+vPortExceptionHandler is called. */
+uint32_t *pulStackPointerOnFunctionEntry = NULL;
+
+/* This is the structure that is filled with the MicroBlaze context as it
+existed immediately prior to the exception occurrence.  A pointer to this
+structure is passed into the vApplicationExceptionRegisterDump() callback
+function, if one is defined. */
+static xPortRegisterDump xRegisterDump;
+
+/* This is the FreeRTOS exception handler that is installed for all exception
+types.  It is called from vPortExceptionHanlderEntry() - which is itself defined
+in portasm.S. */
+void vPortExceptionHandler( void *pvExceptionID );
+extern void vPortExceptionHandlerEntry( void *pvExceptionID );
+
+/*-----------------------------------------------------------*/
+
+/* vApplicationExceptionRegisterDump() is a callback function that the
+application can optionally define to receive a populated xPortRegisterDump
+structure.  If the application chooses not to define a version of
+vApplicationExceptionRegisterDump() then this weekly defined default
+implementation will be called instead. */
+extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
+{
+	( void ) xRegisterDump;
+
+	for( ;; )
+	{
+		portNOP();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExceptionHandler( void *pvExceptionID )
+{
+extern void *pxCurrentTCB;
+
+	/* Fill an xPortRegisterDump structure with the MicroBlaze context as it
+	was immediately before the exception occurrence. */
+
+	/* First fill in the name and handle of the task that was in the Running
+	state when the exception occurred. */
+	xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
+	xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
+
+	configASSERT( pulStackPointerOnFunctionEntry );
+
+	/* Obtain the values of registers that were stacked prior to this function
+	being called, and may have changed since they were stacked. */
+	xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
+	xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
+	xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
+	xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
+	xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
+	xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
+	xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
+	xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
+	xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
+	xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
+	xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
+	xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
+	xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
+	xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
+
+	/* Obtain the value of all other registers. */
+	xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
+	xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
+	xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
+	xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
+	xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
+	xRegisterDump.ulR20 = mfgpr( R20 );
+	xRegisterDump.ulR21 = mfgpr( R21 );
+	xRegisterDump.ulR22 = mfgpr( R22 );
+	xRegisterDump.ulR23 = mfgpr( R23 );
+	xRegisterDump.ulR24 = mfgpr( R24 );
+	xRegisterDump.ulR25 = mfgpr( R25 );
+	xRegisterDump.ulR26 = mfgpr( R26 );
+	xRegisterDump.ulR27 = mfgpr( R27 );
+	xRegisterDump.ulR28 = mfgpr( R28 );
+	xRegisterDump.ulR29 = mfgpr( R29 );
+	xRegisterDump.ulR30 = mfgpr( R30 );
+	xRegisterDump.ulR31 = mfgpr( R31 );
+	xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
+	xRegisterDump.ulEAR = mfear();
+	xRegisterDump.ulESR = mfesr();
+	xRegisterDump.ulEDR = mfedr();
+
+	/* Move the saved program counter back to the instruction that was executed
+	when the exception occurred.  This is only valid for certain types of
+	exception. */
+	xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
+
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+	{
+		xRegisterDump.ulFSR = mffsr();
+	}
+	#else
+	{
+		xRegisterDump.ulFSR = 0UL;
+	}
+	#endif
+
+	/* Also fill in a string that describes what type of exception this is.
+	The string uses the same ID names as defined in the MicroBlaze standard
+	library exception header files. */
+	switch( ( uint32_t ) pvExceptionID )
+	{
+		case XEXC_ID_FSL :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
+				break;
+
+		case XEXC_ID_UNALIGNED_ACCESS :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
+				break;
+
+		case XEXC_ID_ILLEGAL_OPCODE :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
+				break;
+
+		case XEXC_ID_M_AXI_I_EXCEPTION :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
+				break;
+
+		case XEXC_ID_M_AXI_D_EXCEPTION :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
+				break;
+
+		case XEXC_ID_DIV_BY_ZERO :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
+				break;
+
+		case XEXC_ID_STACK_VIOLATION :
+				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
+				break;
+
+		#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+
+			case XEXC_ID_FPU :
+						xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
+						break;
+
+		#endif /* XPAR_MICROBLAZE_USE_FPU */
+	}
+
+	/* vApplicationExceptionRegisterDump() is a callback function that the
+	application can optionally define to receive the populated xPortRegisterDump
+	structure.  If the application chooses not to define a version of
+	vApplicationExceptionRegisterDump() then the weekly defined default
+	implementation within this file will be called instead. */
+	vApplicationExceptionRegisterDump( &xRegisterDump );
+
+	/* Must not attempt to leave this function! */
+	for( ;; )
+	{
+		portNOP();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExceptionsInstallHandlers( void )
+{
+static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
+
+	if( ulHandlersAlreadyInstalled == pdFALSE )
+	{
+		ulHandlersAlreadyInstalled = pdTRUE;
+
+		#if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
+			microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
+		#endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
+
+		#if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
+		#endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
+		#endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
+		#endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
+		#endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
+		#endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
+		#endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
+		#endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
+
+		#if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
+			microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
+		#endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
+
+		microblaze_enable_exceptions();
+	}
+}
+
+/* Exclude the entire file if the MicroBlaze is not configured to handle
+exceptions, or the application defined configuration item
+configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
+#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portasm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portasm.S
new file mode 100644
index 0000000..9243703
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portasm.S
@@ -0,0 +1,328 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/* Xilinx library includes. */
+#include "microblaze_exceptions_g.h"
+#include "xparameters.h"
+
+/* The context is oversized to allow functions called from the ISR to write
+back into the caller stack. */
+#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+	#define portCONTEXT_SIZE 136
+	#define portMINUS_CONTEXT_SIZE -136
+#else
+	#define portCONTEXT_SIZE 132
+	#define portMINUS_CONTEXT_SIZE -132
+#endif
+
+/* Offsets from the stack pointer at which saved registers are placed. */
+#define portR31_OFFSET	4
+#define portR30_OFFSET	8
+#define portR29_OFFSET	12
+#define portR28_OFFSET	16
+#define portR27_OFFSET	20
+#define portR26_OFFSET	24
+#define portR25_OFFSET	28
+#define portR24_OFFSET	32
+#define portR23_OFFSET	36
+#define portR22_OFFSET	40
+#define portR21_OFFSET	44
+#define portR20_OFFSET	48
+#define portR19_OFFSET	52
+#define portR18_OFFSET	56
+#define portR17_OFFSET	60
+#define portR16_OFFSET	64
+#define portR15_OFFSET	68
+#define portR14_OFFSET	72
+#define portR13_OFFSET	76
+#define portR12_OFFSET	80
+#define portR11_OFFSET	84
+#define portR10_OFFSET	88
+#define portR9_OFFSET	92
+#define portR8_OFFSET	96
+#define portR7_OFFSET	100
+#define portR6_OFFSET	104
+#define portR5_OFFSET	108
+#define portR4_OFFSET	112
+#define portR3_OFFSET	116
+#define portR2_OFFSET	120
+#define portCRITICAL_NESTING_OFFSET 124
+#define portMSR_OFFSET 128
+#define portFSR_OFFSET 132
+
+	.extern pxCurrentTCB
+	.extern XIntc_DeviceInterruptHandler
+	.extern vTaskSwitchContext
+	.extern uxCriticalNesting
+	.extern pulISRStack
+	.extern ulTaskSwitchRequested
+	.extern vPortExceptionHandler
+	.extern pulStackPointerOnFunctionEntry
+
+	.global _interrupt_handler
+	.global VPortYieldASM
+	.global vPortStartFirstTask
+	.global vPortExceptionHandlerEntry
+
+
+.macro portSAVE_CONTEXT
+
+	/* Make room for the context on the stack. */
+	addik r1, r1, portMINUS_CONTEXT_SIZE
+
+	/* Stack general registers. */
+	swi r31, r1, portR31_OFFSET
+	swi r30, r1, portR30_OFFSET
+	swi r29, r1, portR29_OFFSET
+	swi r28, r1, portR28_OFFSET
+	swi r27, r1, portR27_OFFSET
+	swi r26, r1, portR26_OFFSET
+	swi r25, r1, portR25_OFFSET
+	swi r24, r1, portR24_OFFSET
+	swi r23, r1, portR23_OFFSET
+	swi r22, r1, portR22_OFFSET
+	swi r21, r1, portR21_OFFSET
+	swi r20, r1, portR20_OFFSET
+	swi r19, r1, portR19_OFFSET
+	swi r18, r1, portR18_OFFSET
+	swi r17, r1, portR17_OFFSET
+	swi r16, r1, portR16_OFFSET
+	swi r15, r1, portR15_OFFSET
+	/* R14 is saved later as it needs adjustment if a yield is performed. */
+	swi r13, r1, portR13_OFFSET
+	swi r12, r1, portR12_OFFSET
+	swi r11, r1, portR11_OFFSET
+	swi r10, r1, portR10_OFFSET
+	swi r9, r1, portR9_OFFSET
+	swi r8, r1, portR8_OFFSET
+	swi r7, r1, portR7_OFFSET
+	swi r6, r1, portR6_OFFSET
+	swi r5, r1, portR5_OFFSET
+	swi r4, r1, portR4_OFFSET
+	swi r3, r1, portR3_OFFSET
+	swi r2, r1, portR2_OFFSET
+
+	/* Stack the critical section nesting value. */
+	lwi r18, r0, uxCriticalNesting
+	swi r18, r1, portCRITICAL_NESTING_OFFSET
+
+	/* Stack MSR. */
+	mfs r18, rmsr
+	swi r18, r1, portMSR_OFFSET
+
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+		/* Stack FSR. */
+		mfs r18, rfsr
+		swi r18, r1, portFSR_OFFSET
+	#endif
+
+	/* Save the top of stack value to the TCB. */
+	lwi r3, r0, pxCurrentTCB
+	sw	r1, r0, r3
+
+	.endm
+
+.macro portRESTORE_CONTEXT
+
+	/* Load the top of stack value from the TCB. */
+	lwi r18, r0, pxCurrentTCB
+	lw	r1, r0, r18
+
+	/* Restore the general registers. */
+	lwi r31, r1, portR31_OFFSET
+	lwi r30, r1, portR30_OFFSET
+	lwi r29, r1, portR29_OFFSET
+	lwi r28, r1, portR28_OFFSET
+	lwi r27, r1, portR27_OFFSET
+	lwi r26, r1, portR26_OFFSET
+	lwi r25, r1, portR25_OFFSET
+	lwi r24, r1, portR24_OFFSET
+	lwi r23, r1, portR23_OFFSET
+	lwi r22, r1, portR22_OFFSET
+	lwi r21, r1, portR21_OFFSET
+	lwi r20, r1, portR20_OFFSET
+	lwi r19, r1, portR19_OFFSET
+	lwi r17, r1, portR17_OFFSET
+	lwi r16, r1, portR16_OFFSET
+	lwi r15, r1, portR15_OFFSET
+	lwi r14, r1, portR14_OFFSET
+	lwi r13, r1, portR13_OFFSET
+	lwi r12, r1, portR12_OFFSET
+	lwi r11, r1, portR11_OFFSET
+	lwi r10, r1, portR10_OFFSET
+	lwi r9, r1, portR9_OFFSET
+	lwi r8, r1, portR8_OFFSET
+	lwi r7, r1, portR7_OFFSET
+	lwi r6, r1, portR6_OFFSET
+	lwi r5, r1, portR5_OFFSET
+	lwi r4, r1, portR4_OFFSET
+	lwi r3, r1, portR3_OFFSET
+	lwi r2, r1, portR2_OFFSET
+
+	/* Reload the rmsr from the stack. */
+	lwi r18, r1, portMSR_OFFSET
+	mts rmsr, r18
+
+	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
+		/* Reload the FSR from the stack. */
+		lwi r18, r1, portFSR_OFFSET
+		mts rfsr, r18
+	#endif
+
+	/* Load the critical nesting value. */
+	lwi r18, r1, portCRITICAL_NESTING_OFFSET
+	swi r18, r0, uxCriticalNesting
+
+	/* Test the critical nesting value.  If it is non zero then the task last
+	exited the running state using a yield.  If it is zero, then the task
+	last exited the running state through an interrupt. */
+	xori r18, r18, 0
+	bnei r18, exit_from_yield
+
+	/* r18 was being used as a temporary.  Now restore its true value from the
+	stack. */
+	lwi r18, r1, portR18_OFFSET
+
+	/* Remove the stack frame. */
+	addik r1, r1, portCONTEXT_SIZE
+
+	/* Return using rtid so interrupts are re-enabled as this function is
+	exited. */
+	rtid r14, 0
+	or r0, r0, r0
+
+	.endm
+
+/* This function is used to exit portRESTORE_CONTEXT() if the task being
+returned to last left the Running state by calling taskYIELD() (rather than
+being preempted by an interrupt). */
+	.text
+	.align  4
+exit_from_yield:
+
+	/* r18 was being used as a temporary.  Now restore its true value from the
+	stack. */
+	lwi r18, r1, portR18_OFFSET
+
+	/* Remove the stack frame. */
+	addik r1, r1, portCONTEXT_SIZE
+
+	/* Return to the task. */
+	rtsd r14, 0
+	or r0, r0, r0
+
+
+	.text
+	.align  4
+_interrupt_handler:
+
+	portSAVE_CONTEXT
+
+	/* Stack the return address. */
+	swi r14, r1, portR14_OFFSET
+
+	/* Switch to the ISR stack. */
+	lwi r1, r0, pulISRStack
+
+	/* The parameter to the interrupt handler. */
+	ori r5, r0, configINTERRUPT_CONTROLLER_TO_USE
+
+	/* Execute any pending interrupts. */
+	bralid r15, XIntc_DeviceInterruptHandler
+	or r0, r0, r0
+
+	/* See if a new task should be selected to execute. */
+	lwi r18, r0, ulTaskSwitchRequested
+	or r18, r18, r0
+
+	/* If ulTaskSwitchRequested is already zero, then jump straight to
+	restoring the task that is already in the Running state. */
+	beqi r18, task_switch_not_requested
+
+	/* Set ulTaskSwitchRequested back to zero as a task switch is about to be
+	performed. */
+	swi r0, r0, ulTaskSwitchRequested
+
+	/* ulTaskSwitchRequested was not 0 when tested.  Select the next task to
+	execute. */
+	bralid r15, vTaskSwitchContext
+	or r0, r0, r0
+
+task_switch_not_requested:
+
+	/* Restore the context of the next task scheduled to execute. */
+	portRESTORE_CONTEXT
+
+
+	.text
+	.align  4
+VPortYieldASM:
+
+	portSAVE_CONTEXT
+
+	/* Modify the return address so a return is done to the instruction after
+	the call to VPortYieldASM. */
+	addi r14, r14, 8
+	swi r14, r1, portR14_OFFSET
+
+	/* Switch to use the ISR stack. */
+	lwi r1, r0, pulISRStack
+
+	/* Select the next task to execute. */
+	bralid r15, vTaskSwitchContext
+	or r0, r0, r0
+
+	/* Restore the context of the next task scheduled to execute. */
+	portRESTORE_CONTEXT
+
+	.text
+	.align  4
+vPortStartFirstTask:
+
+	portRESTORE_CONTEXT
+
+
+
+#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
+
+	.text
+	.align 4
+vPortExceptionHandlerEntry:
+
+	/* Take a copy of the stack pointer before vPortExecptionHandler is called,
+	storing its value prior to the function stack frame being created. */
+	swi r1, r0, pulStackPointerOnFunctionEntry
+	bralid r15, vPortExceptionHandler
+	or r0, r0, r0
+
+#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portmacro.h
new file mode 100644
index 0000000..2985761
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portmacro.h
@@ -0,0 +1,369 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* BSP includes. */
+#include <mb_interface.h>
+#include <xparameters.h>
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros and functions. */
+void microblaze_disable_interrupts( void );
+void microblaze_enable_interrupts( void );
+#define portDISABLE_INTERRUPTS()	microblaze_disable_interrupts()
+#define portENABLE_INTERRUPTS()		microblaze_enable_interrupts()
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+#define portENTER_CRITICAL()		{																\
+										extern volatile UBaseType_t uxCriticalNesting;				\
+										microblaze_disable_interrupts();							\
+										uxCriticalNesting++;										\
+									}
+
+#define portEXIT_CRITICAL()			{																\
+										extern volatile UBaseType_t uxCriticalNesting;				\
+										/* Interrupts are disabled, so we can */					\
+										/* access the variable directly. */							\
+										uxCriticalNesting--;										\
+										if( uxCriticalNesting == 0 )								\
+										{															\
+											/* The nesting has unwound and we 						\
+											can enable interrupts again. */							\
+											portENABLE_INTERRUPTS();								\
+										}															\
+									}
+
+/*-----------------------------------------------------------*/
+
+/* The yield macro maps directly to the vPortYield() function. */
+void vPortYield( void );
+#define portYIELD() vPortYield()
+
+/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead
+sets a flag to say that a yield has been requested.  The interrupt exit code
+then checks this flag, and calls vTaskSwitchContext() before restoring a task
+context, if the flag is not false.  This is done to prevent multiple calls to
+vTaskSwitchContext() being made from a single interrupt, as a single interrupt
+can result in multiple peripherals being serviced. */
+extern volatile uint32_t ulTaskSwitchRequested;
+#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
+
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+	/* Generic helper function. */
+	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+	{
+	uint8_t ucReturn;
+
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+		return ucReturn;
+	}
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			4
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* The following structure is used by the FreeRTOS exception handler.  It is
+filled with the MicroBlaze context as it was at the time the exception occurred.
+This is done as an aid to debugging exception occurrences. */
+typedef struct PORT_REGISTER_DUMP
+{
+	/* The following structure members hold the values of the MicroBlaze
+	registers at the time the exception was raised. */
+	uint32_t ulR1_SP;
+	uint32_t ulR2_small_data_area;
+	uint32_t ulR3;
+	uint32_t ulR4;
+	uint32_t ulR5;
+	uint32_t ulR6;
+	uint32_t ulR7;
+	uint32_t ulR8;
+	uint32_t ulR9;
+	uint32_t ulR10;
+	uint32_t ulR11;
+	uint32_t ulR12;
+	uint32_t ulR13_read_write_small_data_area;
+	uint32_t ulR14_return_address_from_interrupt;
+	uint32_t ulR15_return_address_from_subroutine;
+	uint32_t ulR16_return_address_from_trap;
+	uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
+	uint32_t ulR18;
+	uint32_t ulR19;
+	uint32_t ulR20;
+	uint32_t ulR21;
+	uint32_t ulR22;
+	uint32_t ulR23;
+	uint32_t ulR24;
+	uint32_t ulR25;
+	uint32_t ulR26;
+	uint32_t ulR27;
+	uint32_t ulR28;
+	uint32_t ulR29;
+	uint32_t ulR30;
+	uint32_t ulR31;
+	uint32_t ulPC;
+	uint32_t ulESR;
+	uint32_t ulMSR;
+	uint32_t ulEAR;
+	uint32_t ulFSR;
+	uint32_t ulEDR;
+
+	/* A human readable description of the exception cause.  The strings used
+	are the same as the #define constant names found in the
+	microblaze_exceptions_i.h header file */
+	int8_t *pcExceptionCause;
+
+	/* The human readable name of the task that was running at the time the
+	exception occurred.  This is the name that was given to the task when the
+	task was created using the FreeRTOS xTaskCreate() API function. */
+	char *pcCurrentTaskName;
+
+	/* The handle of the task that was running a the time the exception
+	occurred. */
+	void * xCurrentTaskHandle;
+
+} xPortRegisterDump;
+
+
+/*
+ * Installs pxHandler as the interrupt handler for the peripheral specified by
+ * the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have pxHandler assigned as its interrupt
+ * handler.  Peripheral IDs are defined in the xparameters.h header file, which
+ * is itself part of the BSP project.  For example, in the official demo
+ * application for this port, xparameters.h defines the following IDs for the
+ * four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
+ *
+ *
+ * pxHandler:
+ *
+ * A pointer to the interrupt handler function itself.  This must be a void
+ * function that takes a (void *) parameter.
+ *
+ *
+ * pvCallBackRef:
+ *
+ * The parameter passed into the handler function.  In many cases this will not
+ * be used and can be NULL.  Some times it is used to pass in a reference to
+ * the peripheral instance variable, so it can be accessed from inside the
+ * handler function.
+ *
+ *
+ * pdPASS is returned if the function executes successfully.  Any other value
+ * being returned indicates that the function did not execute correctly.
+ */
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
+
+
+/*
+ * Enables the interrupt, within the interrupt controller, for the peripheral
+ * specified by the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have its interrupt enabled in the
+ * interrupt controller.  Peripheral IDs are defined in the xparameters.h header
+ * file, which is itself part of the BSP project.  For example, in the official
+ * demo application for this port, xparameters.h defines the following IDs for
+ * the four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
+ *
+ */
+void vPortEnableInterrupt( uint8_t ucInterruptID );
+
+/*
+ * Disables the interrupt, within the interrupt controller, for the peripheral
+ * specified by the ucInterruptID parameter.
+ *
+ * ucInterruptID:
+ *
+ * The ID of the peripheral that will have its interrupt disabled in the
+ * interrupt controller.  Peripheral IDs are defined in the xparameters.h header
+ * file, which is itself part of the BSP project.  For example, in the official
+ * demo application for this port, xparameters.h defines the following IDs for
+ * the four possible interrupt sources:
+ *
+ * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
+ * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
+ * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
+ * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
+ *
+ */
+void vPortDisableInterrupt( uint8_t ucInterruptID );
+
+/*
+ * This is an application defined callback function used to install the tick
+ * interrupt handler.  It is provided as an application callback because the
+ * kernel will run on lots of different MicroBlaze and FPGA configurations - not
+ * all of which will have the same timer peripherals defined or available.  This
+ * example uses the AXI Timer 0.  If that is available on your hardware platform
+ * then this example callback implementation should not require modification.
+ * The name of the interrupt handler that should be installed is vPortTickISR(),
+ * which the function below declares as an extern.
+ */
+void vApplicationSetupTimerInterrupt( void );
+
+/*
+ * This is an application defined callback function used to clear whichever
+ * interrupt was installed by the the vApplicationSetupTimerInterrupt() callback
+ * function - in this case the interrupt generated by the AXI timer.  It is
+ * provided as an application callback because the kernel will run on lots of
+ * different MicroBlaze and FPGA configurations - not all of which will have the
+ * same timer peripherals defined or available.  This example uses the AXI Timer 0.
+ * If that is available on your hardware platform then this example callback
+ * implementation should not require modification provided the example definition
+ * of vApplicationSetupTimerInterrupt() is also not modified.
+ */
+void vApplicationClearTimerInterrupt( void );
+
+/*
+ * vPortExceptionsInstallHandlers() is only available when the MicroBlaze
+ * is configured to include exception functionality, and
+ * configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h.
+ *
+ * vPortExceptionsInstallHandlers() installs the FreeRTOS exception handler
+ * for every possible exception cause.
+ *
+ * vPortExceptionsInstallHandlers() can be called explicitly from application
+ * code.  After that is done, the default FreeRTOS exception handler that will
+ * have been installed can be replaced for any specific exception cause by using
+ * the standard Xilinx library function microblaze_register_exception_handler().
+ *
+ * If vPortExceptionsInstallHandlers() is not called explicitly by the
+ * application, it will be called automatically by the kernel the first time
+ * xPortInstallInterruptHandler() is called.  At that time, any exception
+ * handlers that may have already been installed will be replaced.
+ *
+ * See the description of vApplicationExceptionRegisterDump() for information
+ * on the processing performed by the FreeRTOS exception handler.
+ */
+void vPortExceptionsInstallHandlers( void );
+
+/*
+ * The FreeRTOS exception handler fills an xPortRegisterDump structure (defined
+ * in portmacro.h) with the MicroBlaze context, as it was at the time the
+ * exception occurred.  The exception handler then calls
+ * vApplicationExceptionRegisterDump(), passing in the completed
+ * xPortRegisterDump structure as its parameter.
+ *
+ * The FreeRTOS kernel provides its own implementation of
+ * vApplicationExceptionRegisterDump(), but the kernel provided implementation
+ * is declared as being 'weak'.  The weak definition allows the application
+ * writer to provide their own implementation, should they wish to use the
+ * register dump information.  For example, an implementation could be provided
+ * that wrote the register dump data to a display, or a UART port.
+ */
+void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump );
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/NiosII/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/NiosII/port.c
new file mode 100644
index 0000000..1d2da1e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/NiosII/port.c
@@ -0,0 +1,203 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the NIOS2 port.
+ *----------------------------------------------------------*/
+
+/* Standard Includes. */
+#include <string.h>
+#include <errno.h>
+
+/* Altera includes. */
+#include "sys/alt_irq.h"
+#include "altera_avalon_timer_regs.h"
+#include "priv/alt_irq_table.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Interrupts are enabled. */
+#define portINITIAL_ESTATUS     ( StackType_t ) 0x01 
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * Call back for the alarm function.
+ */
+void vPortSysTickHandler( void * context, alt_u32 id );
+
+/*-----------------------------------------------------------*/
+
+static void prvReadGp( uint32_t *ulValue )
+{
+	asm( "stw gp, (%0)" :: "r"(ulValue) );
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{    
+StackType_t *pxFramePointer = pxTopOfStack - 1;
+StackType_t xGlobalPointer;
+
+    prvReadGp( &xGlobalPointer ); 
+
+    /* End of stack marker. */
+    *pxTopOfStack = 0xdeadbeef;
+    pxTopOfStack--;
+    
+    *pxTopOfStack = ( StackType_t ) pxFramePointer; 
+    pxTopOfStack--;
+    
+    *pxTopOfStack = xGlobalPointer; 
+    
+    /* Space for R23 to R16. */
+    pxTopOfStack -= 9;
+
+    *pxTopOfStack = ( StackType_t ) pxCode; 
+    pxTopOfStack--;
+
+    *pxTopOfStack = portINITIAL_ESTATUS; 
+
+    /* Space for R15 to R5. */    
+    pxTopOfStack -= 12;
+    
+    *pxTopOfStack = ( StackType_t ) pvParameters; 
+
+    /* Space for R3 to R1, muldiv and RA. */
+    pxTopOfStack -= 5;
+    
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+	
+	/* Start the first task. */
+    asm volatile (  " movia r2, restore_sp_from_pxCurrentTCB        \n"
+                    " jmp r2                                          " );
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the NIOS2 port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+void prvSetupTimerInterrupt( void )
+{
+	/* Try to register the interrupt handler. */
+	if ( -EINVAL == alt_irq_register( SYS_CLK_IRQ, 0x0, vPortSysTickHandler ) )
+	{ 
+		/* Failed to install the Interrupt Handler. */
+		asm( "break" );
+	}
+	else
+	{
+		/* Configure SysTick to interrupt at the requested rate. */
+		IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_STOP_MSK );
+		IOWR_ALTERA_AVALON_TIMER_PERIODL( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) & 0xFFFF );
+		IOWR_ALTERA_AVALON_TIMER_PERIODH( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) >> 16 );
+		IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | ALTERA_AVALON_TIMER_CONTROL_START_MSK | ALTERA_AVALON_TIMER_CONTROL_ITO_MSK );	
+	} 
+
+	/* Clear any already pending interrupts generated by the Timer. */
+	IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSysTickHandler( void * context, alt_u32 id )
+{
+	/* Increment the kernel tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+        vTaskSwitchContext();
+	}
+		
+	/* Clear the interrupt. */
+	IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK );
+}
+/*-----------------------------------------------------------*/
+
+/** This function is a re-implementation of the Altera provided function.
+ * The function is re-implemented to prevent it from enabling an interrupt
+ * when it is registered. Interrupts should only be enabled after the FreeRTOS.org
+ * kernel has its scheduler started so that contexts are saved and switched 
+ * correctly.
+ */
+int alt_irq_register( alt_u32 id, void* context, void (*handler)(void*, alt_u32) )
+{
+	int rc = -EINVAL;  
+	alt_irq_context status;
+
+	if (id < ALT_NIRQ)
+	{
+		/* 
+		 * interrupts are disabled while the handler tables are updated to ensure
+		 * that an interrupt doesn't occur while the tables are in an inconsistent
+		 * state.
+		 */
+	
+		status = alt_irq_disable_all ();
+	
+		alt_irq[id].handler = handler;
+		alt_irq[id].context = context;
+	
+		rc = (handler) ? alt_irq_enable (id): alt_irq_disable (id);
+	
+		/* alt_irq_enable_all(status); This line is removed to prevent the interrupt from being immediately enabled. */
+	}
+    
+	return rc; 
+}
+/*-----------------------------------------------------------*/
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/NiosII/port_asm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/NiosII/port_asm.S
new file mode 100644
index 0000000..e04aac1
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/NiosII/port_asm.S
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+.extern		vTaskSwitchContext
+	
+.set noat
+
+# Exported to start the first task.
+.globl restore_sp_from_pxCurrentTCB		
+	
+# Entry point for exceptions.
+.section .exceptions.entry, "xa"		
+
+# Save the entire context of a task.
+save_context:
+	addi	ea, ea, -4			# Point to the next instruction.
+	addi	sp,	sp, -116		# Create space on the stack.
+	stw		ra, 0(sp)
+								# Leave a gap for muldiv 0
+	stw		at, 8(sp)		 
+	stw		r2, 12(sp)
+	stw		r3, 16(sp)
+	stw		r4, 20(sp)
+	stw		r5, 24(sp) 
+	stw		r6, 28(sp) 
+	stw		r7, 32(sp) 
+	stw		r8, 36(sp) 
+	stw		r9, 40(sp) 
+	stw		r10, 44(sp)
+	stw		r11, 48(sp)
+	stw		r12, 52(sp)
+	stw		r13, 56(sp)
+	stw		r14, 60(sp)
+	stw		r15, 64(sp)
+	rdctl	r5, estatus 		# Save the eStatus
+	stw		r5, 68(sp)
+	stw		ea, 72(sp)			# Save the PC
+	stw		r16, 76(sp)			# Save the remaining registers
+	stw		r17, 80(sp)
+	stw		r18, 84(sp)
+	stw		r19, 88(sp)
+	stw		r20, 92(sp)
+	stw		r21, 96(sp)
+	stw		r22, 100(sp)
+	stw		r23, 104(sp)
+	stw		gp, 108(sp)
+	stw		fp, 112(sp)
+
+save_sp_to_pxCurrentTCB:
+	movia	et, pxCurrentTCB	# Load the address of the pxCurrentTCB pointer
+	ldw		et, (et)			# Load the value of the pxCurrentTCB pointer
+	stw		sp, (et)			# Store the stack pointer into the top of the TCB
+	
+	.section .exceptions.irqtest, "xa"	
+hw_irq_test:
+	/*
+     * Test to see if the exception was a software exception or caused 
+     * by an external interrupt, and vector accordingly.
+     */
+    rdctl	r4, ipending		# Load the Pending Interrupts indication
+	rdctl	r5, estatus 		# Load the eStatus (enabled interrupts).
+    andi	r2, r5, 1			# Are interrupts enabled globally.
+    beq		r2, zero, soft_exceptions		# Interrupts are not enabled.
+    beq		r4, zero, soft_exceptions		# There are no interrupts triggered.
+
+	.section .exceptions.irqhandler, "xa"
+hw_irq_handler:
+	call	alt_irq_handler					# Call the alt_irq_handler to deliver to the registered interrupt handler.
+
+    .section .exceptions.irqreturn, "xa"
+restore_sp_from_pxCurrentTCB:
+	movia	et, pxCurrentTCB		# Load the address of the pxCurrentTCB pointer
+	ldw		et, (et)				# Load the value of the pxCurrentTCB pointer
+	ldw		sp, (et)				# Load the stack pointer with the top value of the TCB
+
+restore_context:
+	ldw		ra, 0(sp)		# Restore the registers.
+							# Leave a gap for muldiv 0.
+	ldw		at, 8(sp)
+	ldw		r2, 12(sp)
+	ldw		r3, 16(sp)
+	ldw		r4, 20(sp)
+	ldw		r5, 24(sp) 
+	ldw		r6, 28(sp) 
+	ldw		r7, 32(sp) 
+	ldw		r8, 36(sp) 
+	ldw		r9, 40(sp) 
+	ldw		r10, 44(sp)
+	ldw		r11, 48(sp)
+	ldw		r12, 52(sp)
+	ldw		r13, 56(sp)
+	ldw		r14, 60(sp)
+	ldw		r15, 64(sp)
+	ldw		et, 68(sp)		# Load the eStatus
+	wrctl	estatus, et 	# Write the eStatus
+	ldw		ea, 72(sp)		# Load the Program Counter
+	ldw		r16, 76(sp)
+	ldw		r17, 80(sp)
+	ldw		r18, 84(sp)
+	ldw		r19, 88(sp)
+	ldw		r20, 92(sp)
+	ldw		r21, 96(sp)
+	ldw		r22, 100(sp)
+	ldw		r23, 104(sp)
+	ldw		gp, 108(sp)
+	ldw		fp, 112(sp)
+	addi	sp,	sp, 116		# Release stack space
+
+    eret					# Return to address ea, loading eStatus into Status.
+   
+	.section .exceptions.soft, "xa"
+soft_exceptions:
+	ldw		et, 0(ea)				# Load the instruction where the interrupt occured.
+	movhi	at, %hi(0x003B683A)		# Load the registers with the trap instruction code
+	ori		at, at, %lo(0x003B683A)
+   	cmpne	et, et, at				# Compare the trap instruction code to the last excuted instruction
+  	beq		et, r0, call_scheduler	# its a trap so switchcontext
+  	break							# This is an un-implemented instruction or muldiv problem.
+  	br		restore_context			# its something else
+
+call_scheduler:
+	addi	ea, ea, 4						# A trap was called, increment the program counter so it is not called again.
+	stw		ea, 72(sp)						# Save the new program counter to the context.
+	call	vTaskSwitchContext				# Pick the next context.
+	br		restore_sp_from_pxCurrentTCB	# Switch in the task context and restore. 
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/NiosII/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/NiosII/portmacro.h
new file mode 100644
index 0000000..5d47cf8
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/NiosII/portmacro.h
@@ -0,0 +1,109 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "sys/alt_irq.h"
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH				( -1 )
+#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT				4
+#define portNOP()                   	asm volatile ( "NOP" )
+#define portCRITICAL_NESTING_IN_TCB		1
+/*-----------------------------------------------------------*/
+
+extern void vTaskSwitchContext( void );
+#define portYIELD()									asm volatile ( "trap" );
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	if( xSwitchRequired ) 	vTaskSwitchContext()
+
+
+/* Include the port_asm.S file where the Context saving/restoring is defined. */
+__asm__( "\n\t.globl	save_context" );
+
+/*-----------------------------------------------------------*/
+
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()	alt_irq_disable_all()
+#define portENABLE_INTERRUPTS()		alt_irq_enable_all( 0x01 );
+#define portENTER_CRITICAL()        vTaskEnterCritical()
+#define portEXIT_CRITICAL()         vTaskExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/FPU_Macros.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/FPU_Macros.h
new file mode 100644
index 0000000..dfd1e49
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/FPU_Macros.h
@@ -0,0 +1,45 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* When switching out a task, if the task tag contains a buffer address then
+save the flop context into the buffer. */
+#define traceTASK_SWITCHED_OUT()											\
+	if( pxCurrentTCB->pxTaskTag != NULL )									\
+	{																		\
+		extern void vPortSaveFPURegisters( void * );						\
+		vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) );	\
+	}
+
+/* When switching in a task, if the task tag contains a buffer address then
+load the flop context from the buffer. */
+#define traceTASK_SWITCHED_IN()												\
+	if( pxCurrentTCB->pxTaskTag != NULL )									\
+	{																		\
+		extern void vPortRestoreFPURegisters( void * );						\
+		vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) );	\
+	}
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/port.c
new file mode 100644
index 0000000..f0f9b2a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/port.c
@@ -0,0 +1,260 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the PPC405 port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "xtime_l.h"
+#include "xintc.h"
+#include "xintc_i.h"
+
+/*-----------------------------------------------------------*/
+
+/* Definitions to set the initial MSR of each task. */
+#define portCRITICAL_INTERRUPT_ENABLE	( 1UL << 17UL )
+#define portEXTERNAL_INTERRUPT_ENABLE	( 1UL << 15UL )
+#define portMACHINE_CHECK_ENABLE		( 1UL << 12UL )
+
+#if configUSE_FPU == 1
+	#define portAPU_PRESENT				( 1UL << 25UL )
+	#define portFCM_FPU_PRESENT			( 1UL << 13UL )
+#else
+	#define portAPU_PRESENT				( 0UL )
+	#define portFCM_FPU_PRESENT			( 0UL )
+#endif
+
+#define portINITIAL_MSR		( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
+
+
+extern const unsigned _SDA_BASE_;
+extern const unsigned _SDA2_BASE_;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the system timer to generate the tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The handler for the tick interrupt - defined in portasm.s.
+ */
+extern void vPortTickISR( void );
+
+/*
+ * The handler for the yield function - defined in portasm.s.
+ */
+extern void vPortYield( void );
+
+/*
+ * Function to start the scheduler running by starting the highest
+ * priority task that has thus far been created.
+ */
+extern void vPortStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* Structure used to hold the state of the interrupt controller. */
+static XIntc xInterruptController;
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if the task had been
+ * interrupted.
+ * 
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Place a known value at the bottom of the stack for debugging. */
+	*pxTopOfStack = 0xDEADBEEF;
+	pxTopOfStack--;
+
+	/* EABI stack frame. */
+	pxTopOfStack -= 20;	/* Previous backchain and LR, R31 to R4 inclusive. */
+
+	/* Parameters in R13. */
+	*pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
+	pxTopOfStack -= 10;
+
+	/* Parameters in R3. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+
+	/* Parameters in R2. */
+	*pxTopOfStack = ( StackType_t ) &_SDA2_BASE_;	/* address of the second small data area */
+	pxTopOfStack--;
+
+	/* R1 is the stack pointer so is omitted. */
+
+	*pxTopOfStack = 0x10000001UL;;	/* R0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;	/* USPRG0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;	/* CR. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;	/* XER. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;	/* CTR. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) vPortEndScheduler;	/* LR. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_MSR;/* SRR1. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;/* Backchain. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	prvSetupTimerInterrupt();
+	XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
+	vPortStartFirstTask();
+
+	/* Should not get here as the tasks are now running! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.   
+ */
+static void prvSetupTimerInterrupt( void )
+{
+const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
+
+	XTime_PITClearInterrupt();
+	XTime_FITClearInterrupt();
+	XTime_WDTClearInterrupt();
+	XTime_WDTDisableInterrupt();
+	XTime_FITDisableInterrupt();
+
+	XExc_RegisterHandler( XEXC_ID_PIT_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
+
+	XTime_PITEnableAutoReload();
+	XTime_PITSetInterval( ulInterval );
+	XTime_PITEnableInterrupt();
+}
+/*-----------------------------------------------------------*/
+
+void vPortISRHandler( void *pvNullDoNotUse )
+{
+uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
+BaseType_t xInterruptNumber;
+XIntc_Config *pxInterruptController;
+XIntc_VectorTableEntry *pxTable;
+
+	/* Just to remove compiler warning. */
+	( void ) pvNullDoNotUse;	
+
+	/* Get the configuration by using the device ID - in this case it is
+	assumed that only one interrupt controller is being used. */
+	pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
+  
+	/* Which interrupts are pending? */
+	ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
+  
+	for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
+	{
+		if( ulInterruptStatus & 0x01UL )
+		{
+			/* Clear the pending interrupt. */
+			XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
+
+			/* Call the registered handler. */
+			pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
+			pxTable->Handler( pxTable->CallBackRef );
+		}
+        
+		/* Check the next interrupt. */
+		ulInterruptMask <<= 0x01UL;
+		ulInterruptStatus >>= 0x01UL;
+
+		/* Have we serviced all interrupts? */
+		if( ulInterruptStatus == 0UL )
+		{
+			break;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetupInterruptController( void )
+{
+extern void vPortISRWrapper( void );
+
+	/* Perform all library calls necessary to initialise the exception table
+	and interrupt controller.  This assumes only one interrupt controller is in
+	use. */
+	XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+	XExc_Init();
+
+	/* The library functions save the context - we then jump to a wrapper to
+	save the stack into the TCB.  The wrapper then calls the handler defined
+	above. */
+	XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
+	XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
+	XIntc_Start( &xInterruptController, XIN_REAL_MODE );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
+{
+BaseType_t xReturn = pdFAIL;
+
+	/* This function is defined here so the scope of xInterruptController can
+	remain within this file. */
+
+	if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
+	{
+		XIntc_Enable( &xInterruptController, ucInterruptID );
+		xReturn = pdPASS;
+	}
+
+	return xReturn;		
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portasm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portasm.S
new file mode 100644
index 0000000..409964f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portasm.S
@@ -0,0 +1,382 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOSConfig.h"
+
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern xTaskIncrementTick
+	.extern vPortISRHandler
+
+	.global vPortStartFirstTask
+	.global vPortYield
+	.global vPortTickISR
+	.global vPortISRWrapper
+	.global vPortSaveFPURegisters
+	.global vPortRestoreFPURegisters
+
+.set	BChainField, 0
+.set	NextLRField, BChainField + 4
+.set	MSRField,    NextLRField + 4
+.set	PCField,     MSRField    + 4
+.set	LRField,     PCField     + 4
+.set	CTRField,    LRField     + 4
+.set	XERField,    CTRField    + 4
+.set	CRField,     XERField    + 4
+.set	USPRG0Field, CRField     + 4
+.set	r0Field,     USPRG0Field + 4
+.set	r2Field,     r0Field     + 4
+.set	r3r31Field,  r2Field     + 4
+.set	IFrameSize,  r3r31Field  + ( ( 31 - 3 ) + 1 ) * 4
+
+
+.macro portSAVE_STACK_POINTER_AND_LR
+
+	/* Get the address of the TCB. */
+	xor		R0, R0, R0
+	addis	R2, R0, pxCurrentTCB@ha
+	lwz		R2,	pxCurrentTCB@l( R2 )
+
+	/* Store the stack pointer into the TCB */
+	stw		SP,	0( R2 )
+
+	/* Save the link register */
+	stwu	R1, -24( R1 )
+	mflr	R0
+	stw		R31, 20( R1 )
+	stw		R0, 28( R1 )
+	mr		R31, r1
+
+.endm
+
+.macro portRESTORE_STACK_POINTER_AND_LR
+
+	/* Restore the link register */
+	lwz		R11, 0( R1 )
+	lwz		R0, 4( R11 )
+	mtlr	R0
+	lwz		R31, -4( R11 )
+	mr		R1, R11
+
+	/* Get the address of the TCB. */
+	xor		R0, R0, R0
+	addis   SP, R0, pxCurrentTCB@ha
+	lwz		SP,	pxCurrentTCB@l( R1 )
+
+	/* Get the task stack pointer from the TCB. */
+	lwz		SP, 0( SP )
+
+.endm
+
+
+vPortStartFirstTask:
+
+	/* Get the address of the TCB. */
+	xor		R0, R0, R0
+    addis   SP, R0, pxCurrentTCB@ha
+    lwz		SP,	pxCurrentTCB@l( SP )
+
+	/* Get the task stack pointer from the TCB. */
+	lwz		SP, 0( SP )
+	
+	/* Restore MSR register to SRR1. */
+	lwz		R0, MSRField(R1)
+	mtsrr1	R0
+	
+	/* Restore current PC location to SRR0. */
+	lwz		R0, PCField(R1)
+	mtsrr0	R0
+
+	/* Save  USPRG0 register */
+	lwz		R0, USPRG0Field(R1)
+	mtspr	0x100,R0
+	
+	/* Restore Condition register */
+	lwz		R0, CRField(R1)
+	mtcr	R0
+	
+	/* Restore Fixed Point Exception register */
+	lwz		R0, XERField(R1)
+	mtxer	R0
+	
+	/* Restore Counter register */
+	lwz		R0, CTRField(R1)
+	mtctr	R0
+	
+	/* Restore Link register */
+	lwz		R0, LRField(R1)
+	mtlr	R0
+	
+	/* Restore remaining GPR registers. */
+	lmw	R3,r3r31Field(R1)
+	
+	/* Restore r0 and r2. */
+	lwz		R0, r0Field(R1)
+	lwz		R2, r2Field(R1)
+	
+	/* Remove frame from stack */
+	addi	R1,R1,IFrameSize
+
+	/* Return into the first task */
+	rfi
+
+
+
+vPortYield:
+
+	portSAVE_STACK_POINTER_AND_LR
+	bl vTaskSwitchContext
+	portRESTORE_STACK_POINTER_AND_LR
+	blr
+
+vPortTickISR:
+
+	portSAVE_STACK_POINTER_AND_LR
+	bl xTaskIncrementTick
+	
+	#if configUSE_PREEMPTION == 1
+		bl vTaskSwitchContext
+	#endif
+
+	/* Clear the interrupt */
+	lis		R0, 2048
+	mttsr	R0
+
+	portRESTORE_STACK_POINTER_AND_LR
+	blr
+
+vPortISRWrapper:
+
+	portSAVE_STACK_POINTER_AND_LR
+	bl vPortISRHandler
+	portRESTORE_STACK_POINTER_AND_LR
+	blr
+
+#if configUSE_FPU == 1
+
+vPortSaveFPURegisters:
+
+	/* Enable APU and mark FPU as present. */
+	mfmsr	r0
+	xor		r30, r30, r30
+	oris	r30, r30, 512
+	ori		r30, r30, 8192
+	or		r0, r0, r30
+	mtmsr	r0
+
+#ifdef USE_DP_FPU
+
+	/* Buffer address is in r3.  Save each flop register into an offset from
+	this buffer address. */
+	stfd	f0, 0(r3)
+	stfd	f1, 8(r3)
+	stfd	f2, 16(r3)
+	stfd	f3, 24(r3)
+	stfd	f4, 32(r3)
+	stfd	f5, 40(r3)
+	stfd	f6, 48(r3)
+	stfd	f7, 56(r3)
+	stfd	f8, 64(r3)
+	stfd	f9, 72(r3)
+	stfd	f10, 80(r3)
+	stfd	f11, 88(r3)
+	stfd	f12, 96(r3)
+	stfd	f13, 104(r3)
+	stfd	f14, 112(r3)
+	stfd	f15, 120(r3)
+	stfd	f16, 128(r3)
+	stfd	f17, 136(r3)
+	stfd	f18, 144(r3)
+	stfd	f19, 152(r3)
+	stfd	f20, 160(r3)
+	stfd	f21, 168(r3)
+	stfd	f22, 176(r3)
+	stfd	f23, 184(r3)
+	stfd	f24, 192(r3)
+	stfd	f25, 200(r3)
+	stfd	f26, 208(r3)
+	stfd	f27, 216(r3)
+	stfd	f28, 224(r3)
+	stfd	f29, 232(r3)
+	stfd	f30, 240(r3)
+	stfd	f31, 248(r3)	
+	
+	/* Also save the FPSCR. */
+	mffs	f31
+	stfs	f31, 256(r3)
+
+#else
+
+	/* Buffer address is in r3.  Save each flop register into an offset from
+	this buffer address. */
+	stfs	f0, 0(r3)
+	stfs	f1, 4(r3)
+	stfs	f2, 8(r3)
+	stfs	f3, 12(r3)
+	stfs	f4, 16(r3)
+	stfs	f5, 20(r3)
+	stfs	f6, 24(r3)
+	stfs	f7, 28(r3)
+	stfs	f8, 32(r3)
+	stfs	f9, 36(r3)
+	stfs	f10, 40(r3)
+	stfs	f11, 44(r3)
+	stfs	f12, 48(r3)
+	stfs	f13, 52(r3)
+	stfs	f14, 56(r3)
+	stfs	f15, 60(r3)
+	stfs	f16, 64(r3)
+	stfs	f17, 68(r3)
+	stfs	f18, 72(r3)
+	stfs	f19, 76(r3)
+	stfs	f20, 80(r3)
+	stfs	f21, 84(r3)
+	stfs	f22, 88(r3)
+	stfs	f23, 92(r3)
+	stfs	f24, 96(r3)
+	stfs	f25, 100(r3)
+	stfs	f26, 104(r3)
+	stfs	f27, 108(r3)
+	stfs	f28, 112(r3)
+	stfs	f29, 116(r3)
+	stfs	f30, 120(r3)
+	stfs	f31, 124(r3)
+	
+	/* Also save the FPSCR. */
+	mffs	f31
+	stfs	f31, 128(r3)
+	
+#endif
+
+	blr
+
+#endif /* configUSE_FPU. */
+
+
+#if configUSE_FPU == 1
+
+vPortRestoreFPURegisters:
+
+	/* Enable APU and mark FPU as present. */
+	mfmsr	r0
+	xor		r30, r30, r30
+	oris	r30, r30, 512
+	ori		r30, r30, 8192
+	or		r0, r0, r30
+	mtmsr	r0
+
+#ifdef USE_DP_FPU
+
+	/* Buffer address is in r3.  Restore each flop register from an offset
+	into this buffer. 
+	
+	First the FPSCR. */
+	lfs		f31, 256(r3)
+	mtfsf	f31, 7
+
+	lfd		f0, 0(r3)
+	lfd	    f1, 8(r3)
+	lfd		f2, 16(r3)
+	lfd		f3, 24(r3)
+	lfd		f4, 32(r3)
+	lfd		f5, 40(r3)
+	lfd		f6, 48(r3)
+	lfd		f7, 56(r3)
+	lfd		f8, 64(r3)
+	lfd		f9, 72(r3)
+	lfd		f10, 80(r3)
+	lfd		f11, 88(r3)
+	lfd		f12, 96(r3)
+	lfd		f13, 104(r3)
+	lfd		f14, 112(r3)
+	lfd		f15, 120(r3)
+	lfd		f16, 128(r3)
+	lfd		f17, 136(r3)
+	lfd		f18, 144(r3)
+	lfd		f19, 152(r3)
+	lfd		f20, 160(r3)
+	lfd		f21, 168(r3)
+	lfd		f22, 176(r3)
+	lfd		f23, 184(r3)
+	lfd		f24, 192(r3)
+	lfd		f25, 200(r3)
+	lfd		f26, 208(r3)
+	lfd		f27, 216(r3)
+	lfd		f28, 224(r3)
+	lfd		f29, 232(r3)
+	lfd		f30, 240(r3)
+	lfd		f31, 248(r3)
+
+#else
+
+	/* Buffer address is in r3.  Restore each flop register from an offset
+	into this buffer. 
+	
+	First the FPSCR. */
+	lfs		f31, 128(r3)
+	mtfsf	f31, 7
+
+	lfs		f0, 0(r3)
+	lfs		f1, 4(r3)
+	lfs		f2, 8(r3)
+	lfs		f3, 12(r3)
+	lfs		f4, 16(r3)
+	lfs		f5, 20(r3)
+	lfs		f6, 24(r3)
+	lfs		f7, 28(r3)
+	lfs		f8, 32(r3)
+	lfs		f9, 36(r3)
+	lfs		f10, 40(r3)
+	lfs		f11, 44(r3)
+	lfs		f12, 48(r3)
+	lfs		f13, 52(r3)
+	lfs		f14, 56(r3)
+	lfs		f15, 60(r3)
+	lfs		f16, 64(r3)
+	lfs		f17, 68(r3)
+	lfs		f18, 72(r3)
+	lfs		f19, 76(r3)
+	lfs		f20, 80(r3)
+	lfs		f21, 84(r3)
+	lfs		f22, 88(r3)
+	lfs		f23, 92(r3)
+	lfs		f24, 96(r3)
+	lfs		f25, 100(r3)
+	lfs		f26, 104(r3)
+	lfs		f27, 108(r3)
+	lfs		f28, 112(r3)
+	lfs		f29, 116(r3)
+	lfs		f30, 120(r3)
+	lfs		f31, 124(r3)
+
+#endif
+
+	blr
+
+#endif /* configUSE_FPU. */
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portmacro.h
new file mode 100644
index 0000000..6d1eb6e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portmacro.h
@@ -0,0 +1,118 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include "xexception_l.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* This port uses the critical nesting count from the TCB rather than
+maintaining a separate value and then saving this value in the task stack. */
+#define portCRITICAL_NESTING_IN_TCB		1
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS()		XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+#define portENABLE_INTERRUPTS()			XExc_mEnableExceptions( XEXC_NON_CRITICAL );
+
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void vTaskEnterCritical( void );
+void vTaskExitCritical( void );
+#define portENTER_CRITICAL()			vTaskEnterCritical()
+#define portEXIT_CRITICAL()				vTaskExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+void vPortYield( void );
+#define portYIELD() asm volatile ( "SC \n\t NOP" )
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					asm volatile ( "NOP" )
+
+/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */
+#define portNO_FLOP_REGISTERS_TO_SAVE  ( 32 + 1 )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/* Port specific interrupt handling functions. */
+void vPortSetupInterruptController( void );
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/FPU_Macros.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/FPU_Macros.h
new file mode 100644
index 0000000..dfd1e49
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/FPU_Macros.h
@@ -0,0 +1,45 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* When switching out a task, if the task tag contains a buffer address then
+save the flop context into the buffer. */
+#define traceTASK_SWITCHED_OUT()											\
+	if( pxCurrentTCB->pxTaskTag != NULL )									\
+	{																		\
+		extern void vPortSaveFPURegisters( void * );						\
+		vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) );	\
+	}
+
+/* When switching in a task, if the task tag contains a buffer address then
+load the flop context from the buffer. */
+#define traceTASK_SWITCHED_IN()												\
+	if( pxCurrentTCB->pxTaskTag != NULL )									\
+	{																		\
+		extern void vPortRestoreFPURegisters( void * );						\
+		vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) );	\
+	}
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/port.c
new file mode 100644
index 0000000..ebaa68e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/port.c
@@ -0,0 +1,260 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the PPC440 port.
+ *----------------------------------------------------------*/
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "xtime_l.h"
+#include "xintc.h"
+#include "xintc_i.h"
+
+/*-----------------------------------------------------------*/
+
+/* Definitions to set the initial MSR of each task. */
+#define portCRITICAL_INTERRUPT_ENABLE	( 1UL << 17UL )
+#define portEXTERNAL_INTERRUPT_ENABLE	( 1UL << 15UL )
+#define portMACHINE_CHECK_ENABLE		( 1UL << 12UL )
+
+#if configUSE_FPU == 1
+	#define portAPU_PRESENT				( 1UL << 25UL )
+	#define portFCM_FPU_PRESENT			( 1UL << 13UL )
+#else
+	#define portAPU_PRESENT				( 0UL )
+	#define portFCM_FPU_PRESENT			( 0UL )
+#endif
+
+#define portINITIAL_MSR		( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
+
+
+extern const unsigned _SDA_BASE_;
+extern const unsigned _SDA2_BASE_;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the system timer to generate the tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The handler for the tick interrupt - defined in portasm.s.
+ */
+extern void vPortTickISR( void );
+
+/*
+ * The handler for the yield function - defined in portasm.s.
+ */
+extern void vPortYield( void );
+
+/*
+ * Function to start the scheduler running by starting the highest
+ * priority task that has thus far been created.
+ */
+extern void vPortStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* Structure used to hold the state of the interrupt controller. */
+static XIntc xInterruptController;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if the task had been
+ * interrupted.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Place a known value at the bottom of the stack for debugging. */
+	*pxTopOfStack = 0xDEADBEEF;
+	pxTopOfStack--;
+
+	/* EABI stack frame. */
+	pxTopOfStack -= 20;	/* Previous backchain and LR, R31 to R4 inclusive. */
+
+	/* Parameters in R13. */
+	*pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
+	pxTopOfStack -= 10;
+
+	/* Parameters in R3. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+
+	/* Parameters in R2. */
+	*pxTopOfStack = ( StackType_t ) &_SDA2_BASE_;	/* address of the second small data area */
+	pxTopOfStack--;
+
+	/* R1 is the stack pointer so is omitted. */
+
+	*pxTopOfStack = 0x10000001UL;;	/* R0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;	/* USPRG0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;	/* CR. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;	/* XER. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;	/* CTR. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) vPortEndScheduler;	/* LR. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_MSR;/* SRR1. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00000000UL;/* Backchain. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	prvSetupTimerInterrupt();
+	XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
+	vPortStartFirstTask();
+
+	/* Should not get here as the tasks are now running! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented. */
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
+
+	XTime_DECClearInterrupt();
+	XTime_FITClearInterrupt();
+	XTime_WDTClearInterrupt();
+	XTime_WDTDisableInterrupt();
+	XTime_FITDisableInterrupt();
+
+	XExc_RegisterHandler( XEXC_ID_DEC_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
+
+	XTime_DECEnableAutoReload();
+	XTime_DECSetInterval( ulInterval );
+	XTime_DECEnableInterrupt();
+}
+/*-----------------------------------------------------------*/
+
+void vPortISRHandler( void *pvNullDoNotUse )
+{
+uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
+BaseType_t xInterruptNumber;
+XIntc_Config *pxInterruptController;
+XIntc_VectorTableEntry *pxTable;
+
+	/* Just to remove compiler warning. */
+	( void ) pvNullDoNotUse;
+
+	/* Get the configuration by using the device ID - in this case it is
+	assumed that only one interrupt controller is being used. */
+	pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
+
+	/* Which interrupts are pending? */
+	ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
+
+	for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
+	{
+		if( ulInterruptStatus & 0x01UL )
+		{
+			/* Clear the pending interrupt. */
+			XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
+
+			/* Call the registered handler. */
+			pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
+			pxTable->Handler( pxTable->CallBackRef );
+		}
+
+		/* Check the next interrupt. */
+		ulInterruptMask <<= 0x01UL;
+		ulInterruptStatus >>= 0x01UL;
+
+		/* Have we serviced all interrupts? */
+		if( ulInterruptStatus == 0UL )
+		{
+			break;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetupInterruptController( void )
+{
+extern void vPortISRWrapper( void );
+
+	/* Perform all library calls necessary to initialise the exception table
+	and interrupt controller.  This assumes only one interrupt controller is in
+	use. */
+	XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+	XExc_Init();
+
+	/* The library functions save the context - we then jump to a wrapper to
+	save the stack into the TCB.  The wrapper then calls the handler defined
+	above. */
+	XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
+	XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
+	XIntc_Start( &xInterruptController, XIN_REAL_MODE );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
+{
+BaseType_t xReturn = pdFAIL;
+
+	/* This function is defined here so the scope of xInterruptController can
+	remain within this file. */
+
+	if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
+	{
+		XIntc_Enable( &xInterruptController, ucInterruptID );
+		xReturn = pdPASS;
+	}
+
+	return xReturn;
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portasm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portasm.S
new file mode 100644
index 0000000..409964f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portasm.S
@@ -0,0 +1,382 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOSConfig.h"
+
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern xTaskIncrementTick
+	.extern vPortISRHandler
+
+	.global vPortStartFirstTask
+	.global vPortYield
+	.global vPortTickISR
+	.global vPortISRWrapper
+	.global vPortSaveFPURegisters
+	.global vPortRestoreFPURegisters
+
+.set	BChainField, 0
+.set	NextLRField, BChainField + 4
+.set	MSRField,    NextLRField + 4
+.set	PCField,     MSRField    + 4
+.set	LRField,     PCField     + 4
+.set	CTRField,    LRField     + 4
+.set	XERField,    CTRField    + 4
+.set	CRField,     XERField    + 4
+.set	USPRG0Field, CRField     + 4
+.set	r0Field,     USPRG0Field + 4
+.set	r2Field,     r0Field     + 4
+.set	r3r31Field,  r2Field     + 4
+.set	IFrameSize,  r3r31Field  + ( ( 31 - 3 ) + 1 ) * 4
+
+
+.macro portSAVE_STACK_POINTER_AND_LR
+
+	/* Get the address of the TCB. */
+	xor		R0, R0, R0
+	addis	R2, R0, pxCurrentTCB@ha
+	lwz		R2,	pxCurrentTCB@l( R2 )
+
+	/* Store the stack pointer into the TCB */
+	stw		SP,	0( R2 )
+
+	/* Save the link register */
+	stwu	R1, -24( R1 )
+	mflr	R0
+	stw		R31, 20( R1 )
+	stw		R0, 28( R1 )
+	mr		R31, r1
+
+.endm
+
+.macro portRESTORE_STACK_POINTER_AND_LR
+
+	/* Restore the link register */
+	lwz		R11, 0( R1 )
+	lwz		R0, 4( R11 )
+	mtlr	R0
+	lwz		R31, -4( R11 )
+	mr		R1, R11
+
+	/* Get the address of the TCB. */
+	xor		R0, R0, R0
+	addis   SP, R0, pxCurrentTCB@ha
+	lwz		SP,	pxCurrentTCB@l( R1 )
+
+	/* Get the task stack pointer from the TCB. */
+	lwz		SP, 0( SP )
+
+.endm
+
+
+vPortStartFirstTask:
+
+	/* Get the address of the TCB. */
+	xor		R0, R0, R0
+    addis   SP, R0, pxCurrentTCB@ha
+    lwz		SP,	pxCurrentTCB@l( SP )
+
+	/* Get the task stack pointer from the TCB. */
+	lwz		SP, 0( SP )
+	
+	/* Restore MSR register to SRR1. */
+	lwz		R0, MSRField(R1)
+	mtsrr1	R0
+	
+	/* Restore current PC location to SRR0. */
+	lwz		R0, PCField(R1)
+	mtsrr0	R0
+
+	/* Save  USPRG0 register */
+	lwz		R0, USPRG0Field(R1)
+	mtspr	0x100,R0
+	
+	/* Restore Condition register */
+	lwz		R0, CRField(R1)
+	mtcr	R0
+	
+	/* Restore Fixed Point Exception register */
+	lwz		R0, XERField(R1)
+	mtxer	R0
+	
+	/* Restore Counter register */
+	lwz		R0, CTRField(R1)
+	mtctr	R0
+	
+	/* Restore Link register */
+	lwz		R0, LRField(R1)
+	mtlr	R0
+	
+	/* Restore remaining GPR registers. */
+	lmw	R3,r3r31Field(R1)
+	
+	/* Restore r0 and r2. */
+	lwz		R0, r0Field(R1)
+	lwz		R2, r2Field(R1)
+	
+	/* Remove frame from stack */
+	addi	R1,R1,IFrameSize
+
+	/* Return into the first task */
+	rfi
+
+
+
+vPortYield:
+
+	portSAVE_STACK_POINTER_AND_LR
+	bl vTaskSwitchContext
+	portRESTORE_STACK_POINTER_AND_LR
+	blr
+
+vPortTickISR:
+
+	portSAVE_STACK_POINTER_AND_LR
+	bl xTaskIncrementTick
+	
+	#if configUSE_PREEMPTION == 1
+		bl vTaskSwitchContext
+	#endif
+
+	/* Clear the interrupt */
+	lis		R0, 2048
+	mttsr	R0
+
+	portRESTORE_STACK_POINTER_AND_LR
+	blr
+
+vPortISRWrapper:
+
+	portSAVE_STACK_POINTER_AND_LR
+	bl vPortISRHandler
+	portRESTORE_STACK_POINTER_AND_LR
+	blr
+
+#if configUSE_FPU == 1
+
+vPortSaveFPURegisters:
+
+	/* Enable APU and mark FPU as present. */
+	mfmsr	r0
+	xor		r30, r30, r30
+	oris	r30, r30, 512
+	ori		r30, r30, 8192
+	or		r0, r0, r30
+	mtmsr	r0
+
+#ifdef USE_DP_FPU
+
+	/* Buffer address is in r3.  Save each flop register into an offset from
+	this buffer address. */
+	stfd	f0, 0(r3)
+	stfd	f1, 8(r3)
+	stfd	f2, 16(r3)
+	stfd	f3, 24(r3)
+	stfd	f4, 32(r3)
+	stfd	f5, 40(r3)
+	stfd	f6, 48(r3)
+	stfd	f7, 56(r3)
+	stfd	f8, 64(r3)
+	stfd	f9, 72(r3)
+	stfd	f10, 80(r3)
+	stfd	f11, 88(r3)
+	stfd	f12, 96(r3)
+	stfd	f13, 104(r3)
+	stfd	f14, 112(r3)
+	stfd	f15, 120(r3)
+	stfd	f16, 128(r3)
+	stfd	f17, 136(r3)
+	stfd	f18, 144(r3)
+	stfd	f19, 152(r3)
+	stfd	f20, 160(r3)
+	stfd	f21, 168(r3)
+	stfd	f22, 176(r3)
+	stfd	f23, 184(r3)
+	stfd	f24, 192(r3)
+	stfd	f25, 200(r3)
+	stfd	f26, 208(r3)
+	stfd	f27, 216(r3)
+	stfd	f28, 224(r3)
+	stfd	f29, 232(r3)
+	stfd	f30, 240(r3)
+	stfd	f31, 248(r3)	
+	
+	/* Also save the FPSCR. */
+	mffs	f31
+	stfs	f31, 256(r3)
+
+#else
+
+	/* Buffer address is in r3.  Save each flop register into an offset from
+	this buffer address. */
+	stfs	f0, 0(r3)
+	stfs	f1, 4(r3)
+	stfs	f2, 8(r3)
+	stfs	f3, 12(r3)
+	stfs	f4, 16(r3)
+	stfs	f5, 20(r3)
+	stfs	f6, 24(r3)
+	stfs	f7, 28(r3)
+	stfs	f8, 32(r3)
+	stfs	f9, 36(r3)
+	stfs	f10, 40(r3)
+	stfs	f11, 44(r3)
+	stfs	f12, 48(r3)
+	stfs	f13, 52(r3)
+	stfs	f14, 56(r3)
+	stfs	f15, 60(r3)
+	stfs	f16, 64(r3)
+	stfs	f17, 68(r3)
+	stfs	f18, 72(r3)
+	stfs	f19, 76(r3)
+	stfs	f20, 80(r3)
+	stfs	f21, 84(r3)
+	stfs	f22, 88(r3)
+	stfs	f23, 92(r3)
+	stfs	f24, 96(r3)
+	stfs	f25, 100(r3)
+	stfs	f26, 104(r3)
+	stfs	f27, 108(r3)
+	stfs	f28, 112(r3)
+	stfs	f29, 116(r3)
+	stfs	f30, 120(r3)
+	stfs	f31, 124(r3)
+	
+	/* Also save the FPSCR. */
+	mffs	f31
+	stfs	f31, 128(r3)
+	
+#endif
+
+	blr
+
+#endif /* configUSE_FPU. */
+
+
+#if configUSE_FPU == 1
+
+vPortRestoreFPURegisters:
+
+	/* Enable APU and mark FPU as present. */
+	mfmsr	r0
+	xor		r30, r30, r30
+	oris	r30, r30, 512
+	ori		r30, r30, 8192
+	or		r0, r0, r30
+	mtmsr	r0
+
+#ifdef USE_DP_FPU
+
+	/* Buffer address is in r3.  Restore each flop register from an offset
+	into this buffer. 
+	
+	First the FPSCR. */
+	lfs		f31, 256(r3)
+	mtfsf	f31, 7
+
+	lfd		f0, 0(r3)
+	lfd	    f1, 8(r3)
+	lfd		f2, 16(r3)
+	lfd		f3, 24(r3)
+	lfd		f4, 32(r3)
+	lfd		f5, 40(r3)
+	lfd		f6, 48(r3)
+	lfd		f7, 56(r3)
+	lfd		f8, 64(r3)
+	lfd		f9, 72(r3)
+	lfd		f10, 80(r3)
+	lfd		f11, 88(r3)
+	lfd		f12, 96(r3)
+	lfd		f13, 104(r3)
+	lfd		f14, 112(r3)
+	lfd		f15, 120(r3)
+	lfd		f16, 128(r3)
+	lfd		f17, 136(r3)
+	lfd		f18, 144(r3)
+	lfd		f19, 152(r3)
+	lfd		f20, 160(r3)
+	lfd		f21, 168(r3)
+	lfd		f22, 176(r3)
+	lfd		f23, 184(r3)
+	lfd		f24, 192(r3)
+	lfd		f25, 200(r3)
+	lfd		f26, 208(r3)
+	lfd		f27, 216(r3)
+	lfd		f28, 224(r3)
+	lfd		f29, 232(r3)
+	lfd		f30, 240(r3)
+	lfd		f31, 248(r3)
+
+#else
+
+	/* Buffer address is in r3.  Restore each flop register from an offset
+	into this buffer. 
+	
+	First the FPSCR. */
+	lfs		f31, 128(r3)
+	mtfsf	f31, 7
+
+	lfs		f0, 0(r3)
+	lfs		f1, 4(r3)
+	lfs		f2, 8(r3)
+	lfs		f3, 12(r3)
+	lfs		f4, 16(r3)
+	lfs		f5, 20(r3)
+	lfs		f6, 24(r3)
+	lfs		f7, 28(r3)
+	lfs		f8, 32(r3)
+	lfs		f9, 36(r3)
+	lfs		f10, 40(r3)
+	lfs		f11, 44(r3)
+	lfs		f12, 48(r3)
+	lfs		f13, 52(r3)
+	lfs		f14, 56(r3)
+	lfs		f15, 60(r3)
+	lfs		f16, 64(r3)
+	lfs		f17, 68(r3)
+	lfs		f18, 72(r3)
+	lfs		f19, 76(r3)
+	lfs		f20, 80(r3)
+	lfs		f21, 84(r3)
+	lfs		f22, 88(r3)
+	lfs		f23, 92(r3)
+	lfs		f24, 96(r3)
+	lfs		f25, 100(r3)
+	lfs		f26, 104(r3)
+	lfs		f27, 108(r3)
+	lfs		f28, 112(r3)
+	lfs		f29, 116(r3)
+	lfs		f30, 120(r3)
+	lfs		f31, 124(r3)
+
+#endif
+
+	blr
+
+#endif /* configUSE_FPU. */
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portmacro.h
new file mode 100644
index 0000000..6d1eb6e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portmacro.h
@@ -0,0 +1,118 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include "xexception_l.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* This port uses the critical nesting count from the TCB rather than
+maintaining a separate value and then saving this value in the task stack. */
+#define portCRITICAL_NESTING_IN_TCB		1
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS()		XExc_mDisableExceptions( XEXC_NON_CRITICAL );
+#define portENABLE_INTERRUPTS()			XExc_mEnableExceptions( XEXC_NON_CRITICAL );
+
+/*-----------------------------------------------------------*/
+
+/* Critical section macros. */
+void vTaskEnterCritical( void );
+void vTaskExitCritical( void );
+#define portENTER_CRITICAL()			vTaskEnterCritical()
+#define portEXIT_CRITICAL()				vTaskExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+void vPortYield( void );
+#define portYIELD() asm volatile ( "SC \n\t NOP" )
+#define portYIELD_FROM_ISR() vTaskSwitchContext()
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					asm volatile ( "NOP" )
+
+/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */
+#define portNO_FLOP_REGISTERS_TO_SAVE  ( 32 + 1 )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/* Port specific interrupt handling functions. */
+void vPortSetupInterruptController( void );
+BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/Documentation.url b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/Documentation.url
new file mode 100644
index 0000000..c7819d5
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/Documentation.url
@@ -0,0 +1,5 @@
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,11
+[InternetShortcut]
+IDList=
+URL=https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
new file mode 100644
index 0000000..bbf4bf1
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
@@ -0,0 +1,109 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and t
+
+ o permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
+ * compiler's!) include path.  For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
+
+/*
+ * This freertos_risc_v_chip_specific_extensions.h is for use with Pulpino Ri5cy
+ * devices, developed and tested using the Vega board RV32M1RM.
+ */
+
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
+#define __FREERTOS_RISC_V_EXTENSIONS_H__
+
+#define portasmHAS_MTIME 0
+
+/* Constants to define the additional registers found on the Pulpino RI5KY. */
+#define lpstart0 	0x7b0
+#define lpend0 		0x7b1
+#define lpcount0 	0x7b2
+#define lpstart1 	0x7b4
+#define lpend1 		0x7b5
+#define lpcount1 	0x7b6
+
+/* Six additional registers to save and restore, as per the #defines above. */
+#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */
+
+/* Save additional registers found on the Pulpino. */
+.macro portasmSAVE_ADDITIONAL_REGISTERS
+	addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */
+	csrr t0, lpstart0							 /* Load additional registers into accessible temporary registers. */
+	csrr t1, lpend0
+	csrr t2, lpcount0
+	csrr t3, lpstart1
+	csrr t4, lpend1
+	csrr t5, lpcount1
+	sw t0, 1 * portWORD_SIZE( sp )
+	sw t1, 2 * portWORD_SIZE( sp )
+	sw t2, 3 * portWORD_SIZE( sp )
+	sw t3, 4 * portWORD_SIZE( sp )
+	sw t4, 5 * portWORD_SIZE( sp )
+	sw t5, 6 * portWORD_SIZE( sp )
+	.endm
+
+/* Restore the additional registers found on the Pulpino. */
+.macro portasmRESTORE_ADDITIONAL_REGISTERS
+	lw t0, 1 * portWORD_SIZE( sp )			/* Load additional registers into accessible temporary registers. */
+	lw t1, 2 * portWORD_SIZE( sp )
+	lw t2, 3 * portWORD_SIZE( sp )
+	lw t3, 4 * portWORD_SIZE( sp )
+	lw t4, 5 * portWORD_SIZE( sp )
+	lw t5, 6 * portWORD_SIZE( sp )
+	csrw lpstart0, t0
+	csrw lpend0, t1
+	csrw lpcount0, t2
+	csrw lpstart1, t3
+	csrw lpend1, t4
+	csrw lpcount1, t5
+	addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */
+	.endm
+
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
new file mode 100644
index 0000000..bd1ba21
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -0,0 +1,68 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
+ * compiler's!) include path.  For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
+
+
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
+#define __FREERTOS_RISC_V_EXTENSIONS_H__
+
+#define portasmHAS_SIFIVE_CLINT 1
+#define portasmHAS_MTIME 1
+#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
+
+.macro portasmSAVE_ADDITIONAL_REGISTERS
+	/* No additional registers to save, so this macro does nothing. */
+	.endm
+
+.macro portasmRESTORE_ADDITIONAL_REGISTERS
+	/* No additional registers to restore, so this macro does nothing. */
+	.endm
+
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/readme.txt
new file mode 100644
index 0000000..69d98d9
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/readme.txt
@@ -0,0 +1,23 @@
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
+ * compiler's!) include path.  For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/port.c
new file mode 100644
index 0000000..8a8970c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/port.c
@@ -0,0 +1,212 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the RISC-V RV32 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portmacro.h"
+
+/* Standard includes. */
+#include "string.h"
+
+#ifdef configCLINT_BASE_ADDRESS
+	#warning The configCLINT_BASE_ADDRESS constant has been deprecated.  configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting.  Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+#ifndef configMTIME_BASE_ADDRESS
+	#warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address.  Otherwise set configMTIME_BASE_ADDRESS to 0.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+#ifndef configMTIMECMP_BASE_ADDRESS
+	#warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address.  Otherwise set configMTIMECMP_BASE_ADDRESS to 0.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/* The stack used by interrupt service routines.  Set configISR_STACK_SIZE_WORDS
+to use a statically allocated array as the interrupt stack.  Alternative leave
+configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
+linker variable names __freertos_irq_stack_top has the same value as the top
+of the stack used by main.  Using the linker script method will repurpose the
+stack that was used by main before the scheduler was started for use as the
+interrupt stack after the scheduler has started. */
+#ifdef configISR_STACK_SIZE_WORDS
+	static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
+	const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
+
+	/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
+	the task stacks, and so will legitimately appear in many positions within
+	the ISR stack. */
+	#define portISR_STACK_FILL_BYTE	0xee
+#else
+	extern const uint32_t __freertos_irq_stack_top[];
+	const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) __attribute__(( weak ));
+
+/*-----------------------------------------------------------*/
+
+/* Used to program the machine timer compare register. */
+uint64_t ullNextTime = 0ULL;
+const uint64_t *pullNextTime = &ullNextTime;
+const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */
+uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
+volatile uint64_t * pullMachineTimerCompareRegister = NULL;
+
+/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
+stack checking.  A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
+#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+	#warning This path not tested, or even compiled yet.
+
+	static const uint8_t ucExpectedStackBytes[] = {
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };	\
+
+	#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
+	/* Define the function away. */
+	#define portCHECK_ISR_STACK()
+#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+/*-----------------------------------------------------------*/
+
+#if( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
+
+	void vPortSetupTimerInterrupt( void )
+	{
+	uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
+	volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte typer so high 32-bit word is 4 bytes up. */
+	volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configMTIME_BASE_ADDRESS );
+	volatile uint32_t ulHartId;
+
+		__asm volatile( "csrr %0, mhartid" : "=r"( ulHartId ) );
+		pullMachineTimerCompareRegister  = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
+
+		do
+		{
+			ulCurrentTimeHigh = *pulTimeHigh;
+			ulCurrentTimeLow = *pulTimeLow;
+		} while( ulCurrentTimeHigh != *pulTimeHigh );
+
+		ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
+		ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */
+		ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
+		ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
+		*pullMachineTimerCompareRegister = ullNextTime;
+
+		/* Prepare the time to use after the next tick interrupt. */
+		ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
+	}
+
+#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void xPortStartFirstTask( void );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t mtvec = 0;
+
+		/* Check the least significant two bits of mtvec are 00 - indicating
+		single vector mode. */
+		__asm volatile( "csrr %0, mtvec" : "=r"( mtvec ) );
+		configASSERT( ( mtvec & 0x03UL ) == 0 );
+
+		/* Check alignment of the interrupt stack - which is the same as the
+		stack that was being used by main() prior to the scheduler being
+		started. */
+		configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+		#ifdef configISR_STACK_SIZE_WORDS
+		{
+			memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
+		}
+		#endif	 /* configISR_STACK_SIZE_WORDS */
+	}
+	#endif /* configASSERT_DEFINED */
+
+	/* If there is a CLINT then it is ok to use the default implementation
+	in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
+	configure whichever clock is to be used to generate the tick interrupt. */
+	vPortSetupTimerInterrupt();
+
+	#if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
+	{
+		/* Enable mtime and external interrupts.  1<<7 for timer interrupt, 1<<11
+		for external interrupt.  _RB_ What happens here when mtime is not present as
+		with pulpino? */
+		__asm volatile( "csrs mie, %0" :: "r"(0x880) );
+	}
+	#else
+	{
+		/* Enable external interrupts. */
+		__asm volatile( "csrs mie, %0" :: "r"(0x800) );
+	}
+	#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
+
+	xPortStartFirstTask();
+
+	/* Should not get here as after calling xPortStartFirstTask() only tasks
+	should be executing. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented. */
+	for( ;; );
+}
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
new file mode 100644
index 0000000..8b68684
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
@@ -0,0 +1,443 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
+ *
+ * + The code that is common to all RISC-V chips is implemented in
+ *   FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S.  There is only one
+ *   portASM.S file because the same file is used no matter which RISC-V chip is
+ *   in use.
+ *
+ * + The code that tailors the kernel's RISC-V port to a specific RISC-V
+ *   chip is implemented in freertos_risc_v_chip_specific_extensions.h.  There
+ *   is one freertos_risc_v_chip_specific_extensions.h that can be used with any
+ *   RISC-V chip that both includes a standard CLINT and does not add to the
+ *   base set of RISC-V registers.  There are additional
+ *   freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
+ *   that do not include a standard CLINT or do add to the base set of RISC-V
+ *   registers.
+ *
+ * CARE MUST BE TAKEN TO INCLDUE THE CORRECT
+ * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
+ * IN USE.  To include the correct freertos_risc_v_chip_specific_extensions.h
+ * header file ensure the path to the correct header file is in the assembler's
+ * include path.
+ *
+ * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
+ * that include a standard CLINT and do not add to the base set of RISC-V
+ * registers.
+ *
+ */
+#if __riscv_xlen == 64
+	#define portWORD_SIZE 8
+	#define store_x sd
+	#define load_x ld
+#elif __riscv_xlen == 32
+	#define store_x sw
+	#define load_x lw
+	#define portWORD_SIZE 4
+#else
+	#error Assembler did not define __riscv_xlen
+#endif
+
+#include "freertos_risc_v_chip_specific_extensions.h"
+
+/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
+definitions. */
+#if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME )
+	#error The portasmHAS_CLINT constant has been deprecated.  Please replace it with portasmHAS_MTIME.  portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+#ifdef portasmHAS_CLINT
+	#warning The portasmHAS_CLINT constant has been deprecated.  Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT.  For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+	#define portasmHAS_MTIME portasmHAS_CLINT
+	#define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT
+#endif
+
+#ifndef portasmHAS_MTIME
+	#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present).  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+#ifndef portasmHANDLE_INTERRUPT
+	#error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts.  portasmHANDLE_INTERRUPT can be defined on the assembler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file.  https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+#ifndef portasmHAS_SIFIVE_CLINT
+	#define portasmHAS_SIFIVE_CLINT 0
+#endif
+
+/* Only the standard core registers are stored by default.  Any additional
+registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
+portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
+specific version of freertos_risc_v_chip_specific_extensions.h.  See the notes
+at the top of this file. */
+#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
+
+.global xPortStartFirstTask
+.global freertos_risc_v_trap_handler
+.global pxPortInitialiseStack
+.extern pxCurrentTCB
+.extern ulPortTrapHandler
+.extern vTaskSwitchContext
+.extern xTaskIncrementTick
+.extern Timer_IRQHandler
+.extern pullMachineTimerCompareRegister
+.extern pullNextTime
+.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
+.extern xISRStackTop
+.extern portasmHANDLE_INTERRUPT
+
+/*-----------------------------------------------------------*/
+
+.align 8
+.func
+freertos_risc_v_trap_handler:
+	addi sp, sp, -portCONTEXT_SIZE
+	store_x x1, 1 * portWORD_SIZE( sp )
+	store_x x5, 2 * portWORD_SIZE( sp )
+	store_x x6, 3 * portWORD_SIZE( sp )
+	store_x x7, 4 * portWORD_SIZE( sp )
+	store_x x8, 5 * portWORD_SIZE( sp )
+	store_x x9, 6 * portWORD_SIZE( sp )
+	store_x x10, 7 * portWORD_SIZE( sp )
+	store_x x11, 8 * portWORD_SIZE( sp )
+	store_x x12, 9 * portWORD_SIZE( sp )
+	store_x x13, 10 * portWORD_SIZE( sp )
+	store_x x14, 11 * portWORD_SIZE( sp )
+	store_x x15, 12 * portWORD_SIZE( sp )
+	store_x x16, 13 * portWORD_SIZE( sp )
+	store_x x17, 14 * portWORD_SIZE( sp )
+	store_x x18, 15 * portWORD_SIZE( sp )
+	store_x x19, 16 * portWORD_SIZE( sp )
+	store_x x20, 17 * portWORD_SIZE( sp )
+	store_x x21, 18 * portWORD_SIZE( sp )
+	store_x x22, 19 * portWORD_SIZE( sp )
+	store_x x23, 20 * portWORD_SIZE( sp )
+	store_x x24, 21 * portWORD_SIZE( sp )
+	store_x x25, 22 * portWORD_SIZE( sp )
+	store_x x26, 23 * portWORD_SIZE( sp )
+	store_x x27, 24 * portWORD_SIZE( sp )
+	store_x x28, 25 * portWORD_SIZE( sp )
+	store_x x29, 26 * portWORD_SIZE( sp )
+	store_x x30, 27 * portWORD_SIZE( sp )
+	store_x x31, 28 * portWORD_SIZE( sp )
+
+	csrr t0, mstatus					/* Required for MPIE bit. */
+	store_x t0, 29 * portWORD_SIZE( sp )
+
+	portasmSAVE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
+
+	load_x  t0, pxCurrentTCB			/* Load pxCurrentTCB. */
+	store_x  sp, 0( t0 )				/* Write sp to first TCB member. */
+
+	csrr a0, mcause
+	csrr a1, mepc
+
+test_if_asynchronous:
+	srli a2, a0, __riscv_xlen - 1		/* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
+	beq a2, x0, handle_synchronous		/* Branch past interrupt handing if not asynchronous. */
+	store_x a1, 0( sp )					/* Asynch so save unmodified exception return address. */
+
+handle_asynchronous:
+
+#if( portasmHAS_MTIME != 0 )
+
+	test_if_mtimer:						/* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
+
+		addi t0, x0, 1
+
+		slli t0, t0, __riscv_xlen - 1   /* LSB is already set, shift into MSB.  Shift 31 on 32-bit or 63 on 64-bit cores. */
+		addi t1, t0, 7					/* 0x8000[]0007 == machine timer interrupt. */
+		bne a0, t1, test_if_external_interrupt
+
+		load_x t0, pullMachineTimerCompareRegister  /* Load address of compare register into t0. */
+		load_x t1, pullNextTime  		/* Load the address of ullNextTime into t1. */
+
+		#if( __riscv_xlen == 32 )
+
+			/* Update the 64-bit mtimer compare match value in two 32-bit writes. */
+			li t4, -1
+			lw t2, 0(t1)				/* Load the low word of ullNextTime into t2. */
+			lw t3, 4(t1)				/* Load the high word of ullNextTime into t3. */
+			sw t4, 0(t0)				/* Low word no smaller than old value to start with - will be overwritten below. */
+			sw t3, 4(t0)				/* Store high word of ullNextTime into compare register.  No smaller than new value. */
+			sw t2, 0(t0)				/* Store low word of ullNextTime into compare register. */
+			lw t0, uxTimerIncrementsForOneTick	/* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
+			add t4, t0, t2				/* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
+			sltu t5, t4, t2				/* See if the sum of low words overflowed (what about the zero case?). */
+			add t6, t3, t5				/* Add overflow to high word of ullNextTime. */
+			sw t4, 0(t1)				/* Store new low word of ullNextTime. */
+			sw t6, 4(t1)				/* Store new high word of ullNextTime. */
+
+		#endif /* __riscv_xlen == 32 */
+
+		#if( __riscv_xlen == 64 )
+
+			/* Update the 64-bit mtimer compare match value. */
+			ld t2, 0(t1)			 	/* Load ullNextTime into t2. */
+			sd t2, 0(t0)				/* Store ullNextTime into compare register. */
+			ld t0, uxTimerIncrementsForOneTick  /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
+			add t4, t0, t2				/* Add ullNextTime to the timer increments for one tick. */
+			sd t4, 0(t1)				/* Store ullNextTime. */
+
+		#endif /* __riscv_xlen == 64 */
+
+		load_x sp, xISRStackTop			/* Switch to ISR stack before function call. */
+		jal xTaskIncrementTick
+		beqz a0, processed_source		/* Don't switch context if incrementing tick didn't unblock a task. */
+		jal vTaskSwitchContext
+		j processed_source
+
+	test_if_external_interrupt:			/* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
+		addi t1, t1, 4					/* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
+		bne a0, t1, as_yet_unhandled	/* Something as yet unhandled. */
+
+#endif /* portasmHAS_MTIME */
+
+	load_x sp, xISRStackTop				/* Switch to ISR stack before function call. */
+	jal portasmHANDLE_INTERRUPT			/* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */
+	j processed_source
+
+handle_synchronous:
+	addi a1, a1, 4						/* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */
+	store_x a1, 0( sp )					/* Save updated exception return address. */
+
+test_if_environment_call:
+	li t0, 11 							/* 11 == environment call. */
+	bne a0, t0, is_exception			/* Not an M environment call, so some other exception. */
+	load_x sp, xISRStackTop				/* Switch to ISR stack before function call. */
+	jal vTaskSwitchContext
+	j processed_source
+
+is_exception:
+	csrr t0, mcause						/* For viewing in the debugger only. */
+	csrr t1, mepc						/* For viewing in the debugger only */
+	csrr t2, mstatus
+	j is_exception						/* No other exceptions handled yet. */
+
+as_yet_unhandled:
+	csrr t0, mcause						/* For viewing in the debugger only. */
+	j as_yet_unhandled
+
+processed_source:
+	load_x  t1, pxCurrentTCB			/* Load pxCurrentTCB. */
+	load_x  sp, 0( t1 )				 	/* Read sp from first TCB member. */
+
+	/* Load mret with the address of the next instruction in the task to run next. */
+	load_x t0, 0( sp )
+	csrw mepc, t0
+
+	portasmRESTORE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
+
+	/* Load mstatus with the interrupt enable bits used by the task. */
+	load_x  t0, 29 * portWORD_SIZE( sp )
+	csrw mstatus, t0						/* Required for MPIE bit. */
+
+	load_x  x1, 1 * portWORD_SIZE( sp )
+	load_x  x5, 2 * portWORD_SIZE( sp )		/* t0 */
+	load_x  x6, 3 * portWORD_SIZE( sp )		/* t1 */
+	load_x  x7, 4 * portWORD_SIZE( sp )		/* t2 */
+	load_x  x8, 5 * portWORD_SIZE( sp )		/* s0/fp */
+	load_x  x9, 6 * portWORD_SIZE( sp )		/* s1 */
+	load_x  x10, 7 * portWORD_SIZE( sp )	/* a0 */
+	load_x  x11, 8 * portWORD_SIZE( sp )	/* a1 */
+	load_x  x12, 9 * portWORD_SIZE( sp )	/* a2 */
+	load_x  x13, 10 * portWORD_SIZE( sp )	/* a3 */
+	load_x  x14, 11 * portWORD_SIZE( sp )	/* a4 */
+	load_x  x15, 12 * portWORD_SIZE( sp )	/* a5 */
+	load_x  x16, 13 * portWORD_SIZE( sp )	/* a6 */
+	load_x  x17, 14 * portWORD_SIZE( sp )	/* a7 */
+	load_x  x18, 15 * portWORD_SIZE( sp )	/* s2 */
+	load_x  x19, 16 * portWORD_SIZE( sp )	/* s3 */
+	load_x  x20, 17 * portWORD_SIZE( sp )	/* s4 */
+	load_x  x21, 18 * portWORD_SIZE( sp )	/* s5 */
+	load_x  x22, 19 * portWORD_SIZE( sp )	/* s6 */
+	load_x  x23, 20 * portWORD_SIZE( sp )	/* s7 */
+	load_x  x24, 21 * portWORD_SIZE( sp )	/* s8 */
+	load_x  x25, 22 * portWORD_SIZE( sp )	/* s9 */
+	load_x  x26, 23 * portWORD_SIZE( sp )	/* s10 */
+	load_x  x27, 24 * portWORD_SIZE( sp )	/* s11 */
+	load_x  x28, 25 * portWORD_SIZE( sp )	/* t3 */
+	load_x  x29, 26 * portWORD_SIZE( sp )	/* t4 */
+	load_x  x30, 27 * portWORD_SIZE( sp )	/* t5 */
+	load_x  x31, 28 * portWORD_SIZE( sp )	/* t6 */
+	addi sp, sp, portCONTEXT_SIZE
+
+	mret
+	.endfunc
+/*-----------------------------------------------------------*/
+
+.align 8
+.func
+xPortStartFirstTask:
+
+#if( portasmHAS_SIFIVE_CLINT != 0 )
+	/* If there is a clint then interrupts can branch directly to the FreeRTOS
+	trap handler.  Otherwise the interrupt controller will need to be configured
+	outside of this file. */
+	la t0, freertos_risc_v_trap_handler
+	csrw mtvec, t0
+#endif /* portasmHAS_CLILNT */
+
+	load_x  sp, pxCurrentTCB			/* Load pxCurrentTCB. */
+	load_x  sp, 0( sp )				 	/* Read sp from first TCB member. */
+
+	load_x  x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
+
+	portasmRESTORE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
+
+	load_x  x6, 3 * portWORD_SIZE( sp )		/* t1 */
+	load_x  x7, 4 * portWORD_SIZE( sp )		/* t2 */
+	load_x  x8, 5 * portWORD_SIZE( sp )		/* s0/fp */
+	load_x  x9, 6 * portWORD_SIZE( sp )		/* s1 */
+	load_x  x10, 7 * portWORD_SIZE( sp )	/* a0 */
+	load_x  x11, 8 * portWORD_SIZE( sp )	/* a1 */
+	load_x  x12, 9 * portWORD_SIZE( sp )	/* a2 */
+	load_x  x13, 10 * portWORD_SIZE( sp )	/* a3 */
+	load_x  x14, 11 * portWORD_SIZE( sp )	/* a4 */
+	load_x  x15, 12 * portWORD_SIZE( sp )	/* a5 */
+	load_x  x16, 13 * portWORD_SIZE( sp )	/* a6 */
+	load_x  x17, 14 * portWORD_SIZE( sp )	/* a7 */
+	load_x  x18, 15 * portWORD_SIZE( sp )	/* s2 */
+	load_x  x19, 16 * portWORD_SIZE( sp )	/* s3 */
+	load_x  x20, 17 * portWORD_SIZE( sp )	/* s4 */
+	load_x  x21, 18 * portWORD_SIZE( sp )	/* s5 */
+	load_x  x22, 19 * portWORD_SIZE( sp )	/* s6 */
+	load_x  x23, 20 * portWORD_SIZE( sp )	/* s7 */
+	load_x  x24, 21 * portWORD_SIZE( sp )	/* s8 */
+	load_x  x25, 22 * portWORD_SIZE( sp )	/* s9 */
+	load_x  x26, 23 * portWORD_SIZE( sp )	/* s10 */
+	load_x  x27, 24 * portWORD_SIZE( sp )	/* s11 */
+	load_x  x28, 25 * portWORD_SIZE( sp )	/* t3 */
+	load_x  x29, 26 * portWORD_SIZE( sp )	/* t4 */
+	load_x  x30, 27 * portWORD_SIZE( sp )	/* t5 */
+	load_x  x31, 28 * portWORD_SIZE( sp )	/* t6 */
+
+	load_x  x5, 29 * portWORD_SIZE( sp )	/* Initial mstatus into x5 (t0) */
+	addi x5, x5, 0x08						/* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
+	csrrw  x0, mstatus, x5					/* Interrupts enabled from here! */
+	load_x  x5, 2 * portWORD_SIZE( sp )		/* Initial x5 (t0) value. */
+
+	addi	sp, sp, portCONTEXT_SIZE
+	ret
+	.endfunc
+/*-----------------------------------------------------------*/
+
+/*
+ * Unlike other ports pxPortInitialiseStack() is written in assembly code as it
+ * needs access to the portasmADDITIONAL_CONTEXT_SIZE constant.  The prototype
+ * for the function is as per the other ports:
+ * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
+ *
+ * As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
+ * a1, and pvParameters in a2.  The new top of stack is passed out in a0.
+ *
+ * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
+ * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
+ *
+ * Register		ABI Name	Description						Saver
+ * x0			zero		Hard-wired zero					-
+ * x1			ra			Return address					Caller
+ * x2			sp			Stack pointer					Callee
+ * x3			gp			Global pointer					-
+ * x4			tp			Thread pointer					-
+ * x5-7			t0-2		Temporaries						Caller
+ * x8			s0/fp		Saved register/Frame pointer	Callee
+ * x9			s1			Saved register					Callee
+ * x10-11		a0-1		Function Arguments/return values Caller
+ * x12-17		a2-7		Function arguments				Caller
+ * x18-27		s2-11		Saved registers					Callee
+ * x28-31		t3-6		Temporaries						Caller
+ *
+ * The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
+ * where the global and thread pointers are currently assumed to be constant so
+ * are not saved:
+ *
+ * mstatus
+ * x31
+ * x30
+ * x29
+ * x28
+ * x27
+ * x26
+ * x25
+ * x24
+ * x23
+ * x22
+ * x21
+ * x20
+ * x19
+ * x18
+ * x17
+ * x16
+ * x15
+ * x14
+ * x13
+ * x12
+ * x11
+ * pvParameters
+ * x9
+ * x8
+ * x7
+ * x6
+ * x5
+ * portTASK_RETURN_ADDRESS
+ * [chip specific registers go here]
+ * pxCode
+ */
+.align 8
+.func
+pxPortInitialiseStack:
+
+	csrr t0, mstatus					/* Obtain current mstatus value. */
+	andi t0, t0, ~0x8					/* Ensure interrupts are disabled when the stack is restored within an ISR.  Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
+	addi t1, x0, 0x188					/* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
+	slli t1, t1, 4
+	or t0, t0, t1						/* Set MPIE and MPP bits in mstatus value. */
+
+	addi a0, a0, -portWORD_SIZE
+	store_x t0, 0(a0)					/* mstatus onto the stack. */
+	addi a0, a0, -(22 * portWORD_SIZE)	/* Space for registers x11-x31. */
+	store_x a2, 0(a0)					/* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
+	addi a0, a0, -(6 * portWORD_SIZE)	/* Space for registers x5-x9. */
+	store_x x0, 0(a0)					/* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
+	addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
+chip_specific_stack_frame:				/* First add any chip specific registers to the stack frame being created. */
+	beq t0, x0, 1f						/* No more chip specific registers to save. */
+	addi a0, a0, -portWORD_SIZE			/* Make space for chip specific register. */
+	store_x x0, 0(a0)					/* Give the chip specific register an initial value of zero. */
+	addi t0, t0, -1						/* Decrement the count of chip specific registers remaining. */
+	j chip_specific_stack_frame			/* Until no more chip specific registers. */
+1:
+	addi a0, a0, -portWORD_SIZE
+	store_x a1, 0(a0)					/* mret value (pxCode parameter) onto the stack. */
+	ret
+	.endfunc
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/portmacro.h
new file mode 100644
index 0000000..803c16c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/portmacro.h
@@ -0,0 +1,186 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#if __riscv_xlen == 64
+	#define portSTACK_TYPE			uint64_t
+	#define portBASE_TYPE			int64_t
+	#define portUBASE_TYPE			uint64_t
+	#define portMAX_DELAY 			( TickType_t ) 0xffffffffffffffffUL
+	#define portPOINTER_SIZE_TYPE 	uint64_t
+#elif __riscv_xlen == 32
+	#define portSTACK_TYPE	uint32_t
+	#define portBASE_TYPE	int32_t
+	#define portUBASE_TYPE	uint32_t
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#else
+	#error Assembler did not define __riscv_xlen
+#endif
+
+
+typedef portSTACK_TYPE StackType_t;
+typedef portBASE_TYPE BaseType_t;
+typedef portUBASE_TYPE UBaseType_t;
+typedef portUBASE_TYPE TickType_t;
+
+/* Legacy type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#ifdef __riscv64
+	#error This is the RV32 port that has not yet been adapted for 64.
+	#define portBYTE_ALIGNMENT			16
+#else
+	#define portBYTE_ALIGNMENT			16
+#endif
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+extern void vTaskSwitchContext( void );
+#define portYIELD() __asm volatile( "ecall" );
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vTaskSwitchContext()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+#define portCRITICAL_NESTING_IN_TCB					1
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+
+#define portSET_INTERRUPT_MASK_FROM_ISR() 0
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
+#define portDISABLE_INTERRUPTS()	__asm volatile( "csrc mstatus, 8" )
+#define portENABLE_INTERRUPTS()		__asm volatile( "csrs mstatus, 8" )
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/*-----------------------------------------------------------*/
+
+#define portNOP() __asm volatile 	( " nop " )
+
+#define portINLINE	__inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+
+/* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the
+configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions.  For
+backward compatibility derive the newer definitions from the old if the old
+definition is found. */
+#if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 )
+	/* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
+	there was no CLINT.  Equivalent now is to set the MTIME and MTIMECMP
+	addresses to 0. */
+	#define configMTIME_BASE_ADDRESS 	( 0 )
+	#define configMTIMECMP_BASE_ADDRESS ( 0 )
+#elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS )
+	/* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
+	the CLINT.  Equivalent now is to derive the MTIME and MTIMECMP addresses
+	from the CLINT address. */
+	#define configMTIME_BASE_ADDRESS 	( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
+	#define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
+#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS )
+	#error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  Set them to zero if there is no MTIME (machine time) clock.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/readme.txt
new file mode 100644
index 0000000..69d98d9
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RISC-V/readme.txt
@@ -0,0 +1,23 @@
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
+ * compiler's!) include path.  For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RL78/isr_support.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RL78/isr_support.h
new file mode 100644
index 0000000..37a8f3e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RL78/isr_support.h
@@ -0,0 +1,126 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Variables used by scheduler */
+	.extern    _pxCurrentTCB
+	.extern    _usCriticalNesting
+
+/*
+ * portSAVE_CONTEXT MACRO
+ * Saves the context of the general purpose registers, CS and ES (only in far
+ * memory mode) registers the usCriticalNesting Value and the Stack Pointer
+ * of the active Task onto the task stack
+ */
+	.macro portSAVE_CONTEXT
+
+	SEL 	RB0
+
+	/* Save AX Register to stack. */
+	PUSH	AX
+	PUSH	HL
+	/* Save CS register. */
+	MOV 	A, CS
+	XCH		A, X
+	/* Save ES register. */
+	MOV		A, ES
+	PUSH	AX
+	/* Save the remaining general purpose registers from bank 0. */
+	PUSH	DE
+	PUSH	BC
+	/* Save the other register banks - only necessary in the GCC port. */
+	SEL		RB1
+	PUSH	AX
+	PUSH	BC
+	PUSH	DE
+	PUSH	HL
+	SEL		RB2
+	PUSH	AX
+	PUSH	BC
+	PUSH	DE
+	PUSH	HL
+	/* Registers in bank 3 are for ISR use only so don't need saving. */
+	SEL		RB0
+	/* Save the usCriticalNesting value. */
+	MOVW	AX, !_usCriticalNesting
+	PUSH	AX
+	/* Save the Stack pointer. */
+	MOVW	AX, !_pxCurrentTCB
+	MOVW	HL, AX
+	MOVW	AX, SP
+	MOVW	[HL], AX
+	/* Switch stack pointers. */
+	movw sp,#_stack /* Set stack pointer */
+
+	.endm
+
+
+/*
+ * portRESTORE_CONTEXT MACRO
+ * Restores the task Stack Pointer then use this to restore usCriticalNesting,
+ * general purpose registers and the CS and ES (only in far memory mode)
+ * of the selected task from the task stack
+ */
+.macro portRESTORE_CONTEXT MACRO
+	SEL		RB0
+	/* Restore the Stack pointer. */
+	MOVW	AX, !_pxCurrentTCB
+	MOVW	HL, AX
+	MOVW	AX, [HL]
+	MOVW	SP, AX
+	/* Restore usCriticalNesting value. */
+	POP		AX
+	MOVW	!_usCriticalNesting, AX
+	/* Restore the alternative register banks - only necessary in the GCC
+	port.  Register bank 3 is dedicated for interrupts use so is not saved or
+	restored. */
+	SEL		RB2
+	POP		HL
+	POP		DE
+	POP		BC
+	POP		AX
+	SEL		RB1
+	POP		HL
+	POP		DE
+	POP		BC
+	POP		AX
+	SEL		RB0
+	/* Restore the necessary general purpose registers. */
+	POP		BC
+	POP		DE
+	/* Restore the ES register. */
+	POP		AX
+	MOV		ES, A
+	/* Restore the CS register. */
+	XCH		A, X
+	MOV		CS, A
+	/* Restore general purpose register HL. */
+	POP		HL
+	/* Restore AX. */
+	POP		AX
+
+	.endm
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RL78/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RL78/port.c
new file mode 100644
index 0000000..6fc711c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RL78/port.c
@@ -0,0 +1,211 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* The critical nesting value is initialised to a non zero value to ensure
+interrupts don't accidentally become enabled before the scheduler is started. */
+#define portINITIAL_CRITICAL_NESTING  ( ( uint16_t ) 10 )
+
+/* Initial PSW value allocated to a newly created task.
+ *   11000110
+ *   ||||||||-------------- Fill byte
+ *   |||||||--------------- Carry Flag cleared
+ *   |||||----------------- In-service priority Flags set to low level
+ *   ||||------------------ Register bank Select 0 Flag cleared
+ *   |||------------------- Auxiliary Carry Flag cleared
+ *   ||-------------------- Register bank Select 1 Flag cleared
+ *   |--------------------- Zero Flag set
+ *   ---------------------- Global Interrupt Flag set (enabled)
+ */
+#define portPSW		  ( 0xc6UL )
+
+/* Each task maintains a count of the critical section nesting depth.  Each time
+a critical section is entered the count is incremented.  Each time a critical
+section is exited the count is decremented - with interrupts only being
+re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as that could cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.
+ */
+__attribute__((weak)) void vApplicationSetupTimerInterrupt( void );
+
+/*
+ * Starts the scheduler by loading the context of the first task to run.
+ * (defined in portasm.S).
+ */
+extern void vPortStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t *pulLocal;
+
+	/* Stack type and pointers to the stack type are both 2 bytes. */
+
+	/* Parameters are passed in on the stack, and written using a 32bit value
+	hence a space is left for the second two bytes. */
+	pxTopOfStack--;
+
+	/* Write in the parameter value. */
+	pulLocal =  ( uint32_t * ) pxTopOfStack;
+	*pulLocal = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+
+	/* The return address, leaving space for the first two bytes of	the
+	32-bit value. */
+	pxTopOfStack--;
+	pulLocal = ( uint32_t * ) pxTopOfStack;
+	*pulLocal = ( uint32_t ) 0;
+	pxTopOfStack--;
+
+	/* The start address / PSW value is also written in as a 32bit value,
+	so leave a space for the second two bytes. */
+	pxTopOfStack--;
+
+	/* Task function start address combined with the PSW. */
+	pulLocal = ( uint32_t * ) pxTopOfStack;
+	*pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
+	pxTopOfStack--;
+
+	/* An initial value for the AX register. */
+	*pxTopOfStack = ( StackType_t ) 0x1111;
+	pxTopOfStack--;
+
+	/* An initial value for the HL register. */
+	*pxTopOfStack = ( StackType_t ) 0x2222;
+	pxTopOfStack--;
+
+	/* CS and ES registers. */
+	*pxTopOfStack = ( StackType_t ) 0x0F00;
+	pxTopOfStack--;
+
+	/* The remaining general purpose registers bank 0 (DE and BC) and the other
+	two register banks...register bank 3 is dedicated for use by interrupts so
+	is not saved as part of the task context. */
+	pxTopOfStack -= 10;
+
+	/* Finally the critical section nesting count is set to zero when the task
+	first starts. */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+
+	/* Return a pointer to the top of the stack that has beene generated so it
+	can	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called. */
+	vApplicationSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run. */
+	vPortStartFirstTask();
+
+	/* Execution should not reach here as the tasks are now running! */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the RL78 port will get stopped. */
+}
+/*-----------------------------------------------------------*/
+
+__attribute__((weak)) void vApplicationSetupTimerInterrupt( void )
+{
+const uint16_t usClockHz = 15000UL; /* Internal clock. */
+const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL;
+
+	/* Use the internal 15K clock. */
+	OSMC = ( unsigned char ) 0x16;
+
+	#ifdef RTCEN
+	{
+		/* Supply the interval timer clock. */
+		RTCEN = ( unsigned char ) 1U;
+
+		/* Disable INTIT interrupt. */
+		ITMK = ( unsigned char ) 1;
+
+		/* Disable ITMC operation. */
+		ITMC = ( unsigned char ) 0x0000;
+
+		/* Clear INIT interrupt. */
+		ITIF = ( unsigned char ) 0;
+
+		/* Set interval and enable interrupt operation. */
+		ITMC = usCompareMatch | 0x8000U;
+
+		/* Enable INTIT interrupt. */
+		ITMK = ( unsigned char ) 0;
+	}
+	#endif
+
+	#ifdef TMKAEN
+	{
+		/* Supply the interval timer clock. */
+		TMKAEN = ( unsigned char ) 1U;
+
+		/* Disable INTIT interrupt. */
+		TMKAMK = ( unsigned char ) 1;
+
+		/* Disable ITMC operation. */
+		ITMC = ( unsigned char ) 0x0000;
+
+		/* Clear INIT interrupt. */
+		TMKAIF = ( unsigned char ) 0;
+
+		/* Set interval and enable interrupt operation. */
+		ITMC = usCompareMatch | 0x8000U;
+
+		/* Enable INTIT interrupt. */
+		TMKAMK = ( unsigned char ) 0;
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RL78/portasm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RL78/portasm.S
new file mode 100644
index 0000000..3242f6f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RL78/portasm.S
@@ -0,0 +1,80 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOSConfig.h"
+#include "ISR_Support.h"
+
+	.global    _vPortYield
+	.global    _vPortStartFirstTask
+	.global    _vPortTickISR
+
+	.extern    _vTaskSwitchContext
+	.extern    _xTaskIncrementTick
+
+	.text
+	.align 2
+
+/* FreeRTOS yield handler.  This is installed as the BRK software interrupt
+handler. */
+_vPortYield:
+	/* Save the context of the current task. */
+	portSAVE_CONTEXT
+	/* Call the scheduler to select the next task. */
+	call      !!_vTaskSwitchContext
+	/* Restore the context of the next task to run. */
+	portRESTORE_CONTEXT
+	retb
+
+
+/* Starts the scheduler by restoring the context of the task that will execute
+first. */
+	.align 2
+_vPortStartFirstTask:
+	/* Restore the context of whichever task will execute first. */
+	portRESTORE_CONTEXT
+	/* An interrupt stack frame is used so the task is started using RETI. */
+	reti
+
+/* FreeRTOS tick handler.  This is installed as the interval timer interrupt
+handler. */
+	.align 2
+_vPortTickISR:
+
+	/* Save the context of the currently executing task. */
+	portSAVE_CONTEXT
+	/* Call the RTOS tick function. */
+	call      !!_xTaskIncrementTick
+#if configUSE_PREEMPTION == 1
+	/* Select the next task to run. */
+	call      !!_vTaskSwitchContext
+#endif
+	/* Retore the context of whichever task will run next. */
+	portRESTORE_CONTEXT
+	reti
+
+	.end
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RL78/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RL78/portmacro.h
new file mode 100644
index 0000000..6d16f35
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RL78/portmacro.h
@@ -0,0 +1,121 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE   short
+#define portPOINTER_SIZE_TYPE uint16_t
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS() __asm volatile ( "DI" )
+#define portENABLE_INTERRUPTS()	 __asm volatile ( "EI" )
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( unsigned short ) 0 )
+
+#define portENTER_CRITICAL()													\
+{																				\
+extern volatile uint16_t usCriticalNesting;										\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	/* Now interrupts are disabled ulCriticalNesting can be accessed */			\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
+	/* times portENTER_CRITICAL() has been called. */							\
+	usCriticalNesting++;														\
+}
+
+#define portEXIT_CRITICAL()														\
+{																				\
+extern volatile uint16_t usCriticalNesting;										\
+																				\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
+	{																			\
+		/* Decrement the nesting count as we are leaving a critical section. */	\
+		usCriticalNesting--;													\
+																				\
+		/* If the nesting level has reached zero then interrupts should be */	\
+		/* re-enabled. */														\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
+		{																		\
+			portENABLE_INTERRUPTS();											\
+		}																		\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portYIELD() 	__asm volatile ( "BRK" )
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
+#define portNOP()	__asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Hardwware specifics. */
+#define portBYTE_ALIGNMENT	2
+#define portSTACK_GROWTH	( -1 )
+#define portTICK_PERIOD_MS	( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX100/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX100/port.c
new file mode 100644
index 0000000..d5199d9
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX100/port.c
@@ -0,0 +1,700 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Standard C includes. */
+#include "limits.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+    #include "platform.h"
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+    #include "iodefine.h"
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW	 ( ( StackType_t ) 0x00030000 )
+
+/* The peripheral clock is divided by this value before being supplying the
+CMT. */
+#if ( configUSE_TICKLESS_IDLE == 0 )
+	/* If tickless idle is not used then the divisor can be fixed. */
+	#define portCLOCK_DIVISOR	8UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
+	#define portCLOCK_DIVISOR	512UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
+	#define portCLOCK_DIVISOR	128UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
+	#define portCLOCK_DIVISOR	32UL
+#else
+	#define portCLOCK_DIVISOR	8UL
+#endif
+
+/* These macros allow a critical section to be added around the call to
+xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+priority - ie a known priority.  Therefore these local macros are a slight
+optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+which would require the old IPL to be read first and stored in a local variable. */
+#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
+
+/* Keys required to lock and unlock access to certain system registers
+respectively. */
+#define portUNLOCK_KEY		0xA50B
+#define portLOCK_KEY		0xA500
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void ) __attribute__((naked));
+
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+    R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
+    R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+    void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H  */
+
+/*
+ * The tick ISR handler.  The peripheral used is configured by the application
+ * via a hook/callback function.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+    R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
+    R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+    void vTickISR( void ) __attribute__( ( interrupt ) );
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick using the CMT.
+ * The application writer can define configSETUP_TICK_INTERRUPT() (in
+ * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
+ * in place of prvSetupTimerInterrupt().
+ */
+static void prvSetupTimerInterrupt( void );
+#ifndef configSETUP_TICK_INTERRUPT
+	/* The user has not provided their own tick interrupt configuration so use
+	the definition in this file (which uses the interval timer). */
+	#define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
+#endif /* configSETUP_TICK_INTERRUPT */
+
+/*
+ * Called after the sleep mode registers have been configured, prvSleep()
+ * executes the pre and post sleep macros, and actually calls the wait
+ * instruction.
+ */
+#if configUSE_TICKLESS_IDLE == 1
+	static void prvSleep( TickType_t xExpectedIdleTime );
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+/* Used in the context save and restore code. */
+extern void *pxCurrentTCB;
+
+/* Calculate how many clock increments make up a single tick period. */
+static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	/* Holds the maximum number of ticks that can be suppressed - which is
+	basically how far into the future an interrupt can be generated. Set
+	during initialisation.  This is the maximum possible value that the
+	compare match register can hold divided by ulMatchValueForOneTick. */
+	static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
+
+	/* Flag set from the tick interrupt to allow the sleep processing to know if
+	sleep mode was exited because of a tick interrupt, or an interrupt
+	generated by something else. */
+	static volatile uint32_t ulTickFlag = pdFALSE;
+
+	/* The CMT counter is stopped temporarily each time it is re-programmed.
+	The following constant offsets the CMT counter match value by the number of
+	CMT	counts that would typically be missed while the counter was stopped to
+	compensate for the lost time.  The large difference between the divided CMT
+	clock and the CPU clock means it is likely ulStoppedTimerCompensation will
+	equal zero - and be optimised away. */
+	static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Offset to end up on 8 byte boundary. */
+	pxTopOfStack--;
+
+	/* R0 is not included as it is the stack pointer. */
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0x12345678;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaabbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		/* Leave space for the registers that will get popped from the stack
+		when the task first starts executing. */
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x12345678; /* Accumulator. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x87654321; /* Accumulator. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate
+		the tick interrupt.  This way the application can decide which
+		peripheral to use.  If tickless mode is used then the default
+		implementation defined in this file (which uses CMT0) should not be
+		overridden. */
+		configSETUP_TICK_INTERRUPT();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Execution should not reach here as the tasks are now running!
+	prvSetupTimerInterrupt() is called here to prevent the compiler outputting
+	a warning about a statically declared function not being referenced in the
+	case that the application writer has provided their own tick interrupt
+	configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
+	their own routine will be called in place of prvSetupTimerInterrupt()). */
+	prvSetupTimerInterrupt();
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvStartFirstTask( void )
+{
+	__asm volatile
+	(
+		/* When starting the scheduler there is nothing that needs moving to the
+		interrupt stack because the function is not called from an interrupt.
+		Just ensure the current stack is the user stack. */
+		"SETPSW		U						\n" \
+
+		/* Obtain the location of the stack associated with which ever task
+		pxCurrentTCB is currently pointing to. */
+		"MOV.L		#_pxCurrentTCB, R15		\n" \
+		"MOV.L		[R15], R15				\n" \
+		"MOV.L		[R15], R0				\n" \
+
+		/* Restore the registers from the stack of the task pointed to by
+		pxCurrentTCB. */
+		"POP		R15						\n" \
+
+		/* Accumulator low 32 bits. */
+		"MVTACLO	R15 					\n" \
+		"POP		R15						\n" \
+
+		/* Accumulator high 32 bits. */
+		"MVTACHI	R15 					\n" \
+
+		/* R1 to R15 - R0 is not included as it is the SP. */
+		"POPM		R1-R15 					\n" \
+
+		/* This pops the remaining registers. */
+		"RTE								\n" \
+		"NOP								\n" \
+		"NOP								\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortSoftwareInterruptISR( void )
+{
+	__asm volatile
+	(
+		/* Re-enable interrupts. */
+		"SETPSW		I							\n" \
+
+		/* Move the data that was automatically pushed onto the interrupt stack when
+		the interrupt occurred from the interrupt stack to the user stack.
+
+		R15 is saved before it is clobbered. */
+		"PUSH.L		R15							\n" \
+
+		/* Read the user stack pointer. */
+		"MVFC		USP, R15					\n" \
+
+		/* Move the address down to the data being moved. */
+		"SUB		#12, R15					\n" \
+		"MVTC		R15, USP					\n" \
+
+		/* Copy the data across, R15, then PC, then PSW. */
+		"MOV.L		[ R0 ], [ R15 ]				\n" \
+		"MOV.L 		4[ R0 ], 4[ R15 ]			\n" \
+		"MOV.L		8[ R0 ], 8[ R15 ]			\n" \
+
+		/* Move the interrupt stack pointer to its new correct position. */
+		"ADD		#12, R0						\n" \
+
+		/* All the rest of the registers are saved directly to the user stack. */
+		"SETPSW		U							\n" \
+
+		/* Save the rest of the general registers (R15 has been saved already). */
+		"PUSHM		R1-R14						\n" \
+
+		/* Save the accumulator. */
+		"MVFACHI 	R15							\n" \
+		"PUSH.L		R15							\n" \
+
+		/* Middle word. */
+		"MVFACMI	R15							\n" \
+
+		/* Shifted left as it is restored to the low order word. */
+		"SHLL		#16, R15					\n" \
+		"PUSH.L		R15							\n" \
+
+		/* Save the stack pointer to the TCB. */
+		"MOV.L		#_pxCurrentTCB, R15			\n" \
+		"MOV.L		[ R15 ], R15				\n" \
+		"MOV.L		R0, [ R15 ]					\n" \
+
+		/* Ensure the interrupt mask is set to the syscall priority while the kernel
+		structures are being accessed. */
+		"MVTIPL		%0 							\n" \
+
+		/* Select the next task to run. */
+		"BSR.A		_vTaskSwitchContext			\n" \
+
+		/* Reset the interrupt mask as no more data structure access is required. */
+		"MVTIPL		%1							\n" \
+
+		/* Load the stack pointer of the task that is now selected as the Running
+		state task from its TCB. */
+		"MOV.L		#_pxCurrentTCB,R15			\n" \
+		"MOV.L		[ R15 ], R15				\n" \
+		"MOV.L		[ R15 ], R0					\n" \
+
+		/* Restore the context of the new task.  The PSW (Program Status Word) and
+		PC will be popped by the RTE instruction. */
+		"POP		R15							\n" \
+		"MVTACLO 	R15							\n" \
+		"POP		R15							\n" \
+		"MVTACHI 	R15							\n" \
+		"POPM		R1-R15						\n" \
+		"RTE									\n" \
+		"NOP									\n" \
+		"NOP									  "
+		:: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vPortTickISR( void )
+{
+	/* Re-enabled interrupts. */
+	__asm volatile( "SETPSW	I" );
+
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates.  Ensure IPL is at the max syscall value first. */
+	portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
+
+	#if configUSE_TICKLESS_IDLE == 1
+	{
+		/* The CPU woke because of a tick. */
+		ulTickFlag = pdTRUE;
+
+		/* If this is the first tick since exiting tickless mode then the CMT
+		compare match value needs resetting. */
+		CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortGetIPL( void )
+{
+	__asm volatile
+	(
+		"MVFC	PSW, R1			\n"	\
+		"SHLR	#24, R1			\n"	\
+		"RTS					  "
+	);
+
+	/* This will never get executed, but keeps the compiler from complaining. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetIPL( uint32_t ulNewIPL )
+{
+	__asm volatile
+	(
+		"PUSH	R5				\n" \
+		"MVFC	PSW, R5			\n"	\
+		"SHLL	#24, R1			\n" \
+		"AND	#-0F000001H, R5 \n" \
+		"OR		R1, R5			\n" \
+		"MVTC	R5, PSW			\n" \
+		"POP	R5				\n" \
+		"RTS					  "
+	 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	/* Unlock. */
+	SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+	/* Enable CMT0. */
+	MSTP( CMT0 ) = 0;
+
+	/* Lock again. */
+	SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+	/* Interrupt on compare match. */
+	CMT0.CMCR.BIT.CMIE = 1;
+
+	/* Set the compare match value. */
+	CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+
+	/* Divide the PCLK. */
+	#if portCLOCK_DIVISOR == 512
+	{
+		CMT0.CMCR.BIT.CKS = 3;
+	}
+	#elif portCLOCK_DIVISOR == 128
+	{
+		CMT0.CMCR.BIT.CKS = 2;
+	}
+	#elif portCLOCK_DIVISOR == 32
+	{
+		CMT0.CMCR.BIT.CKS = 1;
+	}
+	#elif portCLOCK_DIVISOR == 8
+	{
+		CMT0.CMCR.BIT.CKS = 0;
+	}
+	#else
+	{
+		#error Invalid portCLOCK_DIVISOR setting
+	}
+	#endif
+
+	/* Enable the interrupt... */
+	_IEN( _CMT0_CMI0 ) = 1;
+
+	/* ...and set its priority to the application defined kernel priority. */
+	_IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
+
+	/* Start the timer. */
+	CMT.CMSTR0.BIT.STR0 = 1;
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	static void prvSleep( TickType_t xExpectedIdleTime )
+	{
+		/* Allow the application to define some pre-sleep processing. */
+		configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
+
+		/* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
+		means the application defined code has already executed the WAIT
+		instruction. */
+		if( xExpectedIdleTime > 0 )
+		{
+			__asm volatile( "WAIT" );
+		}
+
+		/* Allow the application to define some post sleep processing. */
+		configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
+	eSleepModeStatus eSleepAction;
+
+		/* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
+
+		/* Make sure the CMT reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Calculate the reload value required to wait xExpectedIdleTime tick
+		periods. */
+		ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
+		if( ulMatchValue > ulStoppedTimerCompensation )
+		{
+			/* Compensate for the fact that the CMT is going to be stopped
+			momentarily. */
+			ulMatchValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Stop the CMT momentarily.  The time the CMT is stopped for is
+		accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		CMT.CMSTR0.BIT.STR0 = 0;
+		while( CMT.CMSTR0.BIT.STR0 == 1 )
+		{
+			/* Nothing to do here. */
+		}
+
+		/* Critical section using the global interrupt bit as the i bit is
+		automatically reset by the WAIT instruction. */
+		__asm volatile( "CLRPSW i" );
+
+		/* The tick flag is set to false before sleeping.  If it is true when
+		sleep mode is exited then sleep mode was probably exited because the
+		tick was suppressed for the entire xExpectedIdleTime period. */
+		ulTickFlag = pdFALSE;
+
+		/* If a context switch is pending then abandon the low power entry as
+		the context switch might have been pended by an external interrupt that
+		requires processing. */
+		eSleepAction = eTaskConfirmSleepModeStatus();
+		if( eSleepAction == eAbortSleep )
+		{
+			/* Restart tick. */
+			CMT.CMSTR0.BIT.STR0 = 1;
+			__asm volatile( "SETPSW i" );
+		}
+		else if( eSleepAction == eNoTasksWaitingTimeout )
+		{
+			/* Protection off. */
+			SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+			/* Ready for software standby with all clocks stopped. */
+			SYSTEM.SBYCR.BIT.SSBY = 1;
+
+			/* Protection on. */
+			SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+			/* Sleep until something happens.  Calling prvSleep() will
+			automatically reset the i bit in the PSW. */
+			prvSleep( xExpectedIdleTime );
+
+			/* Restart the CMT. */
+			CMT.CMSTR0.BIT.STR0 = 1;
+		}
+		else
+		{
+			/* Protection off. */
+			SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+			/* Ready for deep sleep mode. */
+			SYSTEM.MSTPCRC.BIT.DSLPE = 1;
+			SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
+			SYSTEM.SBYCR.BIT.SSBY = 0;
+
+			/* Protection on. */
+			SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+			/* Adjust the match value to take into account that the current
+			time slice is already partially complete. */
+			ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
+			CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+
+			/* Restart the CMT to count up to the new match value. */
+			CMT0.CMCNT = 0;
+			CMT.CMSTR0.BIT.STR0 = 1;
+
+			/* Sleep until something happens.  Calling prvSleep() will
+			automatically reset the i bit in the PSW. */
+			prvSleep( xExpectedIdleTime );
+
+			/* Stop CMT.  Again, the time the SysTick is stopped for is
+			accounted for as best it can be, but using the tickless mode will
+			inevitably result in some tiny drift of the time maintained by the
+			kernel with	respect to calendar time. */
+			CMT.CMSTR0.BIT.STR0 = 0;
+			while( CMT.CMSTR0.BIT.STR0 == 1 )
+			{
+				/* Nothing to do here. */
+			}
+
+			ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
+
+			if( ulTickFlag != pdFALSE )
+			{
+				/* The tick interrupt has already executed, although because
+				this function is called with the scheduler suspended the actual
+				tick processing will not occur until after this function has
+				exited.  Reset the match value with whatever remains of this
+				tick period. */
+				ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
+				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+
+				/* The tick interrupt handler will already have pended the tick
+				processing in the kernel.  As the pending tick will be
+				processed as soon as this function exits, the tick value
+				maintained by the tick is stepped forward by one less than the
+				time spent sleeping.  The actual stepping of the tick appears
+				later in this function. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				How	many complete tick periods passed while the processor was
+				sleeping? */
+				ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
+
+				/* The match value is set to whatever fraction of a single tick
+				period remains. */
+				ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
+				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+			}
+
+			/* Restart the CMT so it runs up to the match value.  The match value
+			will get set to the value required to generate exactly one tick period
+			the next time the CMT interrupt executes. */
+			CMT0.CMCNT = 0;
+			CMT.CMSTR0.BIT.STR0 = 1;
+
+			/* Wind the tick forward by the number of tick periods that the CPU
+			remained in a low power state. */
+			vTaskStepTick( ulCompleteTickPeriods );
+		}
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX100/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX100/portmacro.h
new file mode 100644
index 0000000..bd85457
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX100/portmacro.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+/* When the FIT configurator or the Smart Configurator is used, platform.h has to be
+ * used. */
+#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
+    #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
+#endif
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					__asm volatile( "NOP" )
+
+/* Save clobbered register, set ITU SWINR (at address 0x872E0), read the value
+back to ensure it is set before continuing, then restore the clobbered
+register. */
+#define portYIELD()							\
+	__asm volatile							\
+	(										\
+		"MOV.L #0x872E0, r5			\n\t"	\
+		"MOV.B #1, [r5]				\n\t"	\
+		"MOV.L [r5], r5				\n\t"	\
+		::: "r5"							\
+	)
+
+#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) { portYIELD(); }
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	#0" )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#else
+	#define portDISABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+uint32_t ulPortGetIPL( void ) __attribute__((naked));
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+
+/* Tickless idle/low power functionality. */
+#if configUSE_TICKLESS_IDLE == 1
+	#ifndef portSUPPRESS_TICKS_AND_SLEEP
+		extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+		#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+	#endif
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX100/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX100/readme.txt
new file mode 100644
index 0000000..9e89a09
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX100/readme.txt
@@ -0,0 +1,72 @@
+The following table shows which port is recommended to be used.
+
+
+RX MCU Group    CPU     FPU         FPU         Port Layer
+                Core    (Single     (Double     CC-RX                   GNURX               ICCRX (*6)
+                Type    Precision)  Precision)
+
+RX110           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX111           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX113           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX130           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX13T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+
+RX210           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX21A           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX220           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX230,RX231     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23E-A         RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23W           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24U           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+
+RX610           RXv1    Yes         ---         N/A (*4)                N/A (*4)            N/A (*4)
+RX62N,RX621     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX630           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX634           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63N,RX631     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX64M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX65N,RX651     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX66N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX62T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX62G           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX66T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+RX71M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX72M           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+Notes:
+
+*1: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide
+the configuration function.  Please be aware that port.c is hard coded to use CMT0 though it seems to be
+configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*2: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is used, please modify port.c for the configuration.  Please be aware that port.c is
+hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of
+configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*3: RX100 ports are also available.
+
+*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction.
+
+*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
+
+#define configUSE_TASK_DPFPU_SUPPORT            0
+
+*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port.
+It contains two definitions of interrupt priority like the following.
+
+#define configKERNEL_INTERRUPT_PRIORITY         1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY    4
+
+
+For more information about Renesas RX MCUs, please visit the following URL:
+
+https://www.renesas.com/products/microcontrollers-microprocessors/rx.html
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX200/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX200/port.c
new file mode 100644
index 0000000..905a82b
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX200/port.c
@@ -0,0 +1,435 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+    #include "platform.h"
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+    #include "iodefine.h"
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
+
+/* These macros allow a critical section to be added around the call to
+xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+priority - ie a known priority.  Therefore these local macros are a slight
+optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+which would require the old IPL to be read first and stored in a local variable. */
+#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void ) __attribute__((naked));
+
+
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+    R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
+    R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+    void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H  */
+
+/*
+ * The tick ISR handler.  The peripheral used is configured by the application
+ * via a hook/callback function.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+    R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
+    R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+    void vTickISR( void ) __attribute__( ( interrupt ) );
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*-----------------------------------------------------------*/
+
+extern void *pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* R0 is not included as it is the stack pointer. */
+
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0xffffffff;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xeeeeeeee;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_FPSW;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11111111; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22222222; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33333333; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44444444; /* Accumulator 1. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55555555; /* Accumulator 1. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66666666; /* Accumulator 1. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate the
+		tick interrupt.  This way the application can decide which peripheral to
+		use.  A demo application is provided to show a suitable example. */
+		vApplicationSetupTimerInterrupt();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvStartFirstTask( void )
+{
+	__asm volatile
+	(
+		/* When starting the scheduler there is nothing that needs moving to the
+		interrupt stack because the function is not called from an interrupt.
+		Just ensure the current stack is the user stack. */
+		"SETPSW		U						\n" \
+
+		/* Obtain the location of the stack associated with which ever task
+		pxCurrentTCB is currently pointing to. */
+		"MOV.L		#_pxCurrentTCB, R15		\n" \
+		"MOV.L		[R15], R15				\n" \
+		"MOV.L		[R15], R0				\n" \
+
+		/* Restore the registers from the stack of the task pointed to by
+		pxCurrentTCB. */
+	    "POP		R15						\n" \
+
+		/* Accumulator low 32 bits. */
+	    "MVTACLO	R15, A0					\n" \
+	    "POP		R15						\n" \
+
+	    /* Accumulator high 32 bits. */
+	    "MVTACHI	R15, A0					\n" \
+	    "POP		R15						\n" \
+
+	    /* Accumulator guard. */
+	    "MVTACGU	R15, A0					\n" \
+	    "POP		R15						\n" \
+
+	    /* Accumulator low 32 bits. */
+	    "MVTACLO	R15, A1					\n" \
+	    "POP		R15						\n" \
+
+	    /* Accumulator high 32 bits. */
+	    "MVTACHI	R15, A1					\n" \
+	    "POP		R15						\n" \
+
+	    /* Accumulator guard. */
+	    "MVTACGU	R15, A1					\n" \
+	    "POP		R15						\n" \
+
+		/* Floating point status word. */
+	    "MVTC		R15, FPSW 				\n" \
+
+		/* R1 to R15 - R0 is not included as it is the SP. */
+	    "POPM		R1-R15 					\n" \
+
+		/* This pops the remaining registers. */
+	    "RTE								\n" \
+	    "NOP								\n" \
+	    "NOP								\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+	__asm volatile
+	(
+		/* Re-enable interrupts. */
+		"SETPSW		I							\n" \
+
+		/* Move the data that was automatically pushed onto the interrupt stack when
+		the interrupt occurred from the interrupt stack to the user stack.
+
+		R15 is saved before it is clobbered. */
+		"PUSH.L		R15							\n" \
+
+		/* Read the user stack pointer. */
+		"MVFC		USP, R15					\n" \
+
+		/* Move the address down to the data being moved. */
+		"SUB		#12, R15					\n" \
+		"MVTC		R15, USP					\n" \
+
+		/* Copy the data across, R15, then PC, then PSW. */
+		"MOV.L		[ R0 ], [ R15 ]				\n" \
+		"MOV.L 		4[ R0 ], 4[ R15 ]			\n" \
+		"MOV.L		8[ R0 ], 8[ R15 ]			\n" \
+
+		/* Move the interrupt stack pointer to its new correct position. */
+		"ADD		#12, R0						\n" \
+
+		/* All the rest of the registers are saved directly to the user stack. */
+		"SETPSW		U							\n" \
+
+		/* Save the rest of the general registers (R15 has been saved already). */
+		"PUSHM		R1-R14						\n" \
+
+		/* Save the FPSW and accumulator. */
+		"MVFC		FPSW, R15					\n" \
+		"PUSH.L		R15							\n" \
+		"MVFACGU	#0, A1, R15					\n" \
+		"PUSH.L		R15							\n" \
+		"MVFACHI	#0, A1, R15					\n" \
+		"PUSH.L		R15							\n" \
+		/* Low order word. */
+		"MVFACLO	#0, A1, R15					\n" \
+		"PUSH.L		R15							\n" \
+		"MVFACGU	#0, A0, R15					\n" \
+		"PUSH.L		R15							\n" \
+		"MVFACHI	#0, A0, R15					\n" \
+		"PUSH.L		R15							\n" \
+		/* Low order word. */
+		"MVFACLO	#0, A0, R15					\n" \
+		"PUSH.L		R15							\n" \
+
+		/* Save the stack pointer to the TCB. */
+		"MOV.L		#_pxCurrentTCB, R15			\n" \
+		"MOV.L		[ R15 ], R15				\n" \
+		"MOV.L		R0, [ R15 ]					\n" \
+
+		/* Ensure the interrupt mask is set to the syscall priority while the kernel
+		structures are being accessed. */
+		"MVTIPL		%0 							\n" \
+
+		/* Select the next task to run. */
+		"BSR.A		_vTaskSwitchContext			\n" \
+
+		/* Reset the interrupt mask as no more data structure access is required. */
+		"MVTIPL		%1							\n" \
+
+		/* Load the stack pointer of the task that is now selected as the Running
+		state task from its TCB. */
+		"MOV.L		#_pxCurrentTCB,R15			\n" \
+		"MOV.L		[ R15 ], R15				\n" \
+		"MOV.L		[ R15 ], R0					\n" \
+
+		/* Restore the context of the new task.  The PSW (Program Status Word) and
+		PC will be popped by the RTE instruction. */
+	    "POP		R15							\n" \
+
+	    /* Accumulator low 32 bits. */
+	    "MVTACLO	R15, A0						\n" \
+	    "POP		R15							\n" \
+
+	    /* Accumulator high 32 bits. */
+	    "MVTACHI	R15, A0						\n" \
+	    "POP		R15							\n" \
+
+	    /* Accumulator guard. */
+	    "MVTACGU	R15, A0						\n" \
+	    "POP		R15							\n" \
+
+	    /* Accumulator low 32 bits. */
+	    "MVTACLO	R15, A1						\n" \
+	    "POP		R15							\n" \
+
+	    /* Accumulator high 32 bits. */
+	    "MVTACHI	R15, A1						\n" \
+	    "POP		R15							\n" \
+
+	    /* Accumulator guard. */
+	    "MVTACGU	R15, A1						\n" \
+		"POP		R15							\n" \
+		"MVTC		R15, FPSW					\n" \
+		"POPM		R1-R15						\n" \
+		"RTE									\n" \
+		"NOP									\n" \
+		"NOP									  "
+		:: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vTickISR( void )
+{
+	/* Re-enabled interrupts. */
+	__asm volatile( "SETPSW	I" );
+
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates.  Ensure IPL is at the max syscall value first. */
+	portMASK_INTERRUPTS_FROM_KERNEL_ISR();
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortGetIPL( void )
+{
+	__asm volatile
+	(
+		"MVFC	PSW, R1			\n"	\
+		"SHLR	#24, R1			\n"	\
+		"RTS					  "
+	);
+
+	/* This will never get executed, but keeps the compiler from complaining. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetIPL( uint32_t ulNewIPL )
+{
+	__asm volatile
+	(
+		"PUSH	R5				\n" \
+		"MVFC	PSW, R5			\n"	\
+		"SHLL	#24, R1			\n" \
+		"AND	#-0F000001H, R5 \n" \
+		"OR		R1, R5			\n" \
+		"MVTC	R5, PSW			\n" \
+		"POP	R5				\n" \
+		"RTS					  "
+	 );
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX200/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX200/portmacro.h
new file mode 100644
index 0000000..03cf6cb
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX200/portmacro.h
@@ -0,0 +1,144 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* When the FIT configurator or the Smart Configurator is used, platform.h has to be
+ * used. */
+#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
+    #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
+#endif
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					__asm volatile( "NOP" )
+
+/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
+where portITU_SWINTR is the location of the software interrupt register
+(0x000872E0).  Don't rely on the assembler to select a register, so instead
+save and restore clobbered registers manually. */
+#define portYIELD()							\
+	__asm volatile 							\
+	(										\
+		"PUSH.L	R10					\n"		\
+		"MOV.L	#0x872E0, R10		\n"		\
+		"MOV.B	#0x1, [R10]			\n"		\
+		"MOV.L	[R10], R10			\n"		\
+		"POP	R10					\n"		\
+	)
+
+#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) portYIELD()
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	#0" )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#else
+	#define portDISABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+uint32_t ulPortGetIPL( void ) __attribute__((naked));
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600/port.c
new file mode 100644
index 0000000..fe01a5a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600/port.c
@@ -0,0 +1,388 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+    #include "platform.h"
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+    #include "iodefine.h"
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
+
+/* These macros allow a critical section to be added around the call to
+xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+priority - ie a known priority.  Therefore these local macros are a slight
+optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+which would require the old IPL to be read first and stored in a local variable. */
+#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void ) __attribute__((naked));
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+    R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
+    R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+    void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H  */
+
+/*
+ * The tick ISR handler.  The peripheral used is configured by the application
+ * via a hook/callback function.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+    R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
+    R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+    void vTickISR( void ) __attribute__( ( interrupt ) );
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*-----------------------------------------------------------*/
+
+extern void *pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* R0 is not included as it is the stack pointer. */
+
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0xffffffff;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xeeeeeeee;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_FPSW;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x12345678; /* Accumulator. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x87654321; /* Accumulator. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate the
+		tick interrupt.  This way the application can decide which peripheral to
+		use.  A demo application is provided to show a suitable example. */
+		vApplicationSetupTimerInterrupt();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvStartFirstTask( void )
+{
+	__asm volatile
+	(
+		/* When starting the scheduler there is nothing that needs moving to the
+		interrupt stack because the function is not called from an interrupt.
+		Just ensure the current stack is the user stack. */
+		"SETPSW		U						\n" \
+
+		/* Obtain the location of the stack associated with which ever task
+		pxCurrentTCB is currently pointing to. */
+		"MOV.L		#_pxCurrentTCB, R15		\n" \
+		"MOV.L		[R15], R15				\n" \
+		"MOV.L		[R15], R0				\n" \
+
+		/* Restore the registers from the stack of the task pointed to by
+		pxCurrentTCB. */
+	    "POP		R15						\n" \
+
+		/* Accumulator low 32 bits. */
+	    "MVTACLO	R15 					\n" \
+	    "POP		R15						\n" \
+
+		/* Accumulator high 32 bits. */
+	    "MVTACHI	R15 					\n" \
+	    "POP		R15						\n" \
+
+		/* Floating point status word. */
+	    "MVTC		R15, FPSW 				\n" \
+
+		/* R1 to R15 - R0 is not included as it is the SP. */
+	    "POPM		R1-R15 					\n" \
+
+		/* This pops the remaining registers. */
+	    "RTE								\n" \
+	    "NOP								\n" \
+	    "NOP								\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+	__asm volatile
+	(
+		/* Re-enable interrupts. */
+		"SETPSW		I							\n" \
+
+		/* Move the data that was automatically pushed onto the interrupt stack when
+		the interrupt occurred from the interrupt stack to the user stack.
+
+		R15 is saved before it is clobbered. */
+		"PUSH.L		R15							\n" \
+
+		/* Read the user stack pointer. */
+		"MVFC		USP, R15					\n" \
+
+		/* Move the address down to the data being moved. */
+		"SUB		#12, R15					\n" \
+		"MVTC		R15, USP					\n" \
+
+		/* Copy the data across, R15, then PC, then PSW. */
+		"MOV.L		[ R0 ], [ R15 ]				\n" \
+		"MOV.L 		4[ R0 ], 4[ R15 ]			\n" \
+		"MOV.L		8[ R0 ], 8[ R15 ]			\n" \
+
+		/* Move the interrupt stack pointer to its new correct position. */
+		"ADD		#12, R0						\n" \
+
+		/* All the rest of the registers are saved directly to the user stack. */
+		"SETPSW		U							\n" \
+
+		/* Save the rest of the general registers (R15 has been saved already). */
+		"PUSHM		R1-R14						\n" \
+
+		/* Save the FPSW and accumulator. */
+		"MVFC		FPSW, R15					\n" \
+		"PUSH.L		R15							\n" \
+		"MVFACHI 	R15							\n" \
+		"PUSH.L		R15							\n" \
+
+		/* Middle word. */
+		"MVFACMI	R15							\n" \
+
+		/* Shifted left as it is restored to the low order word. */
+		"SHLL		#16, R15					\n" \
+		"PUSH.L		R15							\n" \
+
+		/* Save the stack pointer to the TCB. */
+		"MOV.L		#_pxCurrentTCB, R15			\n" \
+		"MOV.L		[ R15 ], R15				\n" \
+		"MOV.L		R0, [ R15 ]					\n" \
+
+		/* Ensure the interrupt mask is set to the syscall priority while the kernel
+		structures are being accessed. */
+		"MVTIPL		%0 							\n" \
+
+		/* Select the next task to run. */
+		"BSR.A		_vTaskSwitchContext			\n" \
+
+		/* Reset the interrupt mask as no more data structure access is required. */
+		"MVTIPL		%1							\n" \
+
+		/* Load the stack pointer of the task that is now selected as the Running
+		state task from its TCB. */
+		"MOV.L		#_pxCurrentTCB,R15			\n" \
+		"MOV.L		[ R15 ], R15				\n" \
+		"MOV.L		[ R15 ], R0					\n" \
+
+		/* Restore the context of the new task.  The PSW (Program Status Word) and
+		PC will be popped by the RTE instruction. */
+		"POP		R15							\n" \
+		"MVTACLO 	R15							\n" \
+		"POP		R15							\n" \
+		"MVTACHI 	R15							\n" \
+		"POP		R15							\n" \
+		"MVTC		R15, FPSW					\n" \
+		"POPM		R1-R15						\n" \
+		"RTE									\n" \
+		"NOP									\n" \
+		"NOP									  "
+		:: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vTickISR( void )
+{
+	/* Re-enabled interrupts. */
+	__asm volatile( "SETPSW	I" );
+
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates.  Ensure IPL is at the max syscall value first. */
+	portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortGetIPL( void )
+{
+	__asm volatile
+	(
+		"MVFC	PSW, R1			\n"	\
+		"SHLR	#24, R1			\n"	\
+		"RTS					  "
+	);
+
+	/* This will never get executed, but keeps the compiler from complaining. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetIPL( uint32_t ulNewIPL )
+{
+	/* Avoid compiler warning about unreferenced parameter. */
+	( void ) ulNewIPL;
+
+	__asm volatile
+	(
+		"PUSH	R5				\n" \
+		"MVFC	PSW, R5			\n"	\
+		"SHLL	#24, R1			\n" \
+		"AND	#-0F000001H, R5 \n" \
+		"OR		R1, R5			\n" \
+		"MVTC	R5, PSW			\n" \
+		"POP	R5				\n" \
+		"RTS					  "
+	 );
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600/portmacro.h
new file mode 100644
index 0000000..c21caed
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600/portmacro.h
@@ -0,0 +1,144 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* When the FIT configurator or the Smart Configurator is used, platform.h has to be
+ * used. */
+#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
+    #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
+#endif
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					__asm volatile( "NOP" )
+
+/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
+where portITU_SWINTR is the location of the software interrupt register
+(0x000872E0).  Don't rely on the assembler to select a register, so instead
+save and restore clobbered registers manually. */
+#define portYIELD()							\
+	__asm volatile 							\
+	(										\
+		"PUSH.L	R10					\n"		\
+		"MOV.L	#0x872E0, R10		\n"		\
+		"MOV.B	#0x1, [R10]			\n"		\
+		"MOV.L	[R10], R10			\n"		\
+		"POP	R10					\n"		\
+	)
+
+#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) portYIELD()
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	#0" )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#else
+	#define portDISABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+uint32_t ulPortGetIPL( void ) __attribute__((naked));
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600/readme.txt
new file mode 100644
index 0000000..9e89a09
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600/readme.txt
@@ -0,0 +1,72 @@
+The following table shows which port is recommended to be used.
+
+
+RX MCU Group    CPU     FPU         FPU         Port Layer
+                Core    (Single     (Double     CC-RX                   GNURX               ICCRX (*6)
+                Type    Precision)  Precision)
+
+RX110           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX111           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX113           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX130           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX13T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+
+RX210           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX21A           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX220           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX230,RX231     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23E-A         RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23W           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24U           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+
+RX610           RXv1    Yes         ---         N/A (*4)                N/A (*4)            N/A (*4)
+RX62N,RX621     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX630           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX634           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63N,RX631     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX64M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX65N,RX651     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX66N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX62T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX62G           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX66T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+RX71M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX72M           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+Notes:
+
+*1: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide
+the configuration function.  Please be aware that port.c is hard coded to use CMT0 though it seems to be
+configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*2: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is used, please modify port.c for the configuration.  Please be aware that port.c is
+hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of
+configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*3: RX100 ports are also available.
+
+*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction.
+
+*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
+
+#define configUSE_TASK_DPFPU_SUPPORT            0
+
+*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port.
+It contains two definitions of interrupt priority like the following.
+
+#define configKERNEL_INTERRUPT_PRIORITY         1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY    4
+
+
+For more information about Renesas RX MCUs, please visit the following URL:
+
+https://www.renesas.com/products/microcontrollers-microprocessors/rx.html
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600v2/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600v2/port.c
new file mode 100644
index 0000000..d7bb4ed
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600v2/port.c
@@ -0,0 +1,432 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+    #include "platform.h"
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+    #include "iodefine.h"
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
+
+/* These macros allow a critical section to be added around the call to
+xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+priority - ie a known priority.  Therefore these local macros are a slight
+optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+which would require the old IPL to be read first and stored in a local variable. */
+#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void ) __attribute__((naked));
+
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
+R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+void vSoftwareInterruptISR( void ) __attribute__((naked));
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H  */
+
+/*
+ * The tick ISR handler.  The peripheral used is configured by the application
+ * via a hook/callback function.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+    R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
+    R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+    void vTickISR( void ) __attribute__( ( interrupt ) );
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+/*-----------------------------------------------------------*/
+
+extern void *pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* R0 is not included as it is the stack pointer. */
+
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0xffffffff;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xeeeeeeee;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_FPSW;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11111111; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22222222; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33333333; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44444444; /* Accumulator 1. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55555555; /* Accumulator 1. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66666666; /* Accumulator 1. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate the
+		tick interrupt.  This way the application can decide which peripheral to
+		use.  A demo application is provided to show a suitable example. */
+		vApplicationSetupTimerInterrupt();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvStartFirstTask( void )
+{
+	__asm volatile
+	(
+		/* When starting the scheduler there is nothing that needs moving to the
+		interrupt stack because the function is not called from an interrupt.
+		Just ensure the current stack is the user stack. */
+		"SETPSW		U						\n" \
+
+		/* Obtain the location of the stack associated with which ever task
+		pxCurrentTCB is currently pointing to. */
+		"MOV.L		#_pxCurrentTCB, R15		\n" \
+		"MOV.L		[R15], R15				\n" \
+		"MOV.L		[R15], R0				\n" \
+
+		/* Restore the registers from the stack of the task pointed to by
+		pxCurrentTCB. */
+	    "POP		R15						\n" \
+
+		/* Accumulator low 32 bits. */
+	    "MVTACLO	R15, A0					\n" \
+	    "POP		R15						\n" \
+
+	    /* Accumulator high 32 bits. */
+	    "MVTACHI	R15, A0					\n" \
+	    "POP		R15						\n" \
+
+	    /* Accumulator guard. */
+	    "MVTACGU	R15, A0					\n" \
+	    "POP		R15						\n" \
+
+	    /* Accumulator low 32 bits. */
+	    "MVTACLO	R15, A1					\n" \
+	    "POP		R15						\n" \
+
+	    /* Accumulator high 32 bits. */
+	    "MVTACHI	R15, A1					\n" \
+	    "POP		R15						\n" \
+
+	    /* Accumulator guard. */
+	    "MVTACGU	R15, A1					\n" \
+	    "POP		R15						\n" \
+
+		/* Floating point status word. */
+	    "MVTC		R15, FPSW 				\n" \
+
+		/* R1 to R15 - R0 is not included as it is the SP. */
+	    "POPM		R1-R15 					\n" \
+
+		/* This pops the remaining registers. */
+	    "RTE								\n" \
+	    "NOP								\n" \
+	    "NOP								\n"
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+	__asm volatile
+	(
+		/* Re-enable interrupts. */
+		"SETPSW		I							\n" \
+
+		/* Move the data that was automatically pushed onto the interrupt stack when
+		the interrupt occurred from the interrupt stack to the user stack.
+
+		R15 is saved before it is clobbered. */
+		"PUSH.L		R15							\n" \
+
+		/* Read the user stack pointer. */
+		"MVFC		USP, R15					\n" \
+
+		/* Move the address down to the data being moved. */
+		"SUB		#12, R15					\n" \
+		"MVTC		R15, USP					\n" \
+
+		/* Copy the data across, R15, then PC, then PSW. */
+		"MOV.L		[ R0 ], [ R15 ]				\n" \
+		"MOV.L 		4[ R0 ], 4[ R15 ]			\n" \
+		"MOV.L		8[ R0 ], 8[ R15 ]			\n" \
+
+		/* Move the interrupt stack pointer to its new correct position. */
+		"ADD		#12, R0						\n" \
+
+		/* All the rest of the registers are saved directly to the user stack. */
+		"SETPSW		U							\n" \
+
+		/* Save the rest of the general registers (R15 has been saved already). */
+		"PUSHM		R1-R14						\n" \
+
+		/* Save the FPSW and accumulator. */
+		"MVFC		FPSW, R15					\n" \
+		"PUSH.L		R15							\n" \
+		"MVFACGU	#0, A1, R15					\n" \
+		"PUSH.L		R15							\n" \
+		"MVFACHI	#0, A1, R15					\n" \
+		"PUSH.L		R15							\n" \
+		/* Low order word. */
+		"MVFACLO	#0, A1, R15					\n" \
+		"PUSH.L		R15							\n" \
+		"MVFACGU	#0, A0, R15					\n" \
+		"PUSH.L		R15							\n" \
+		"MVFACHI	#0, A0, R15					\n" \
+		"PUSH.L		R15							\n" \
+		/* Low order word. */
+		"MVFACLO	#0, A0, R15					\n" \
+		"PUSH.L		R15							\n" \
+
+		/* Save the stack pointer to the TCB. */
+		"MOV.L		#_pxCurrentTCB, R15			\n" \
+		"MOV.L		[ R15 ], R15				\n" \
+		"MOV.L		R0, [ R15 ]					\n" \
+
+		/* Ensure the interrupt mask is set to the syscall priority while the kernel
+		structures are being accessed. */
+		"MVTIPL		%0 							\n" \
+
+		/* Select the next task to run. */
+		"BSR.A		_vTaskSwitchContext			\n" \
+
+		/* Reset the interrupt mask as no more data structure access is required. */
+		"MVTIPL		%1							\n" \
+
+		/* Load the stack pointer of the task that is now selected as the Running
+		state task from its TCB. */
+		"MOV.L		#_pxCurrentTCB,R15			\n" \
+		"MOV.L		[ R15 ], R15				\n" \
+		"MOV.L		[ R15 ], R0					\n" \
+
+		/* Restore the context of the new task.  The PSW (Program Status Word) and
+		PC will be popped by the RTE instruction. */
+	    "POP		R15							\n" \
+
+	    /* Accumulator low 32 bits. */
+	    "MVTACLO	R15, A0						\n" \
+	    "POP		R15							\n" \
+
+	    /* Accumulator high 32 bits. */
+	    "MVTACHI	R15, A0						\n" \
+	    "POP		R15							\n" \
+
+	    /* Accumulator guard. */
+	    "MVTACGU	R15, A0						\n" \
+	    "POP		R15							\n" \
+
+	    /* Accumulator low 32 bits. */
+	    "MVTACLO	R15, A1						\n" \
+	    "POP		R15							\n" \
+
+	    /* Accumulator high 32 bits. */
+	    "MVTACHI	R15, A1						\n" \
+	    "POP		R15							\n" \
+
+	    /* Accumulator guard. */
+	    "MVTACGU	R15, A1						\n" \
+		"POP		R15							\n" \
+		"MVTC		R15, FPSW					\n" \
+		"POPM		R1-R15						\n" \
+		"RTE									\n" \
+		"NOP									\n" \
+		"NOP									  "
+		:: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void vTickISR( void )
+{
+	/* Re-enabled interrupts. */
+	__asm volatile( "SETPSW	I" );
+
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates.  Ensure IPL is at the max syscall value first. */
+	portMASK_INTERRUPTS_FROM_KERNEL_ISR();
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortGetIPL( void )
+{
+	__asm volatile
+	(
+		"MVFC	PSW, R1			\n"	\
+		"SHLR	#24, R1			\n"	\
+		"RTS					  "
+	);
+
+	/* This will never get executed, but keeps the compiler from complaining. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetIPL( uint32_t ulNewIPL )
+{
+	/* Avoid compiler warning about unreferenced parameter. */
+	( void ) ulNewIPL;
+
+	__asm volatile
+	(
+		"PUSH	R5				\n" \
+		"MVFC	PSW, R5			\n"	\
+		"SHLL	#24, R1			\n" \
+		"AND	#-0F000001H, R5 \n" \
+		"OR		R1, R5			\n" \
+		"MVTC	R5, PSW			\n" \
+		"POP	R5				\n" \
+		"RTS					  "
+	 );
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600v2/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600v2/portmacro.h
new file mode 100644
index 0000000..c21caed
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600v2/portmacro.h
@@ -0,0 +1,144 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* When the FIT configurator or the Smart Configurator is used, platform.h has to be
+ * used. */
+#ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
+    #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
+#endif
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					__asm volatile( "NOP" )
+
+/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
+where portITU_SWINTR is the location of the software interrupt register
+(0x000872E0).  Don't rely on the assembler to select a register, so instead
+save and restore clobbered registers manually. */
+#define portYIELD()							\
+	__asm volatile 							\
+	(										\
+		"PUSH.L	R10					\n"		\
+		"MOV.L	#0x872E0, R10		\n"		\
+		"MOV.B	#0x1, [R10]			\n"		\
+		"MOV.L	[R10], R10			\n"		\
+		"POP	R10					\n"		\
+	)
+
+#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) portYIELD()
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	#0" )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#else
+	#define portDISABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+uint32_t ulPortGetIPL( void ) __attribute__((naked));
+void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
+#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600v2/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600v2/readme.txt
new file mode 100644
index 0000000..9e89a09
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX600v2/readme.txt
@@ -0,0 +1,72 @@
+The following table shows which port is recommended to be used.
+
+
+RX MCU Group    CPU     FPU         FPU         Port Layer
+                Core    (Single     (Double     CC-RX                   GNURX               ICCRX (*6)
+                Type    Precision)  Precision)
+
+RX110           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX111           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX113           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX130           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX13T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+
+RX210           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX21A           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX220           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX230,RX231     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23E-A         RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23W           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24U           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+
+RX610           RXv1    Yes         ---         N/A (*4)                N/A (*4)            N/A (*4)
+RX62N,RX621     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX630           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX634           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63N,RX631     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX64M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX65N,RX651     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX66N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX62T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX62G           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX66T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+RX71M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX72M           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+Notes:
+
+*1: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide
+the configuration function.  Please be aware that port.c is hard coded to use CMT0 though it seems to be
+configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*2: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is used, please modify port.c for the configuration.  Please be aware that port.c is
+hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of
+configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*3: RX100 ports are also available.
+
+*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction.
+
+*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
+
+#define configUSE_TASK_DPFPU_SUPPORT            0
+
+*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port.
+It contains two definitions of interrupt priority like the following.
+
+#define configKERNEL_INTERRUPT_PRIORITY         1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY    4
+
+
+For more information about Renesas RX MCUs, please visit the following URL:
+
+https://www.renesas.com/products/microcontrollers-microprocessors/rx.html
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX700v3_DPFPU/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX700v3_DPFPU/port.c
new file mode 100644
index 0000000..1a77b58
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX700v3_DPFPU/port.c
@@ -0,0 +1,621 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the RXv3 DPFPU port.
+*----------------------------------------------------------*/
+
+#warning Testing for DFPU support in this port is not yet complete
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+    #include "platform.h"
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+    #include "iodefine.h"
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+ * PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
+#define portINITIAL_DPSW    ( ( StackType_t ) 0x00000100 )
+#define portINITIAL_DCMR    ( ( StackType_t ) 0x00000000 )
+#define portINITIAL_DECNT   ( ( StackType_t ) 0x00000001 )
+
+/* Tasks are not created with a DPFPU context, but can be given a DPFPU context
+ * after they have been created.  A variable is stored as part of the tasks context
+ * that holds portNO_DPFPU_CONTEXT if the task does not have a DPFPU context, or
+ * any other value if the task does have a DPFPU context. */
+#define portNO_DPFPU_CONTEXT    ( ( StackType_t ) 0 )
+#define portHAS_DPFPU_CONTEXT   ( ( StackType_t ) 1 )
+
+/* The space on the stack required to hold the DPFPU data registers.  This is 16
+ * 64-bit registers. */
+#define portDPFPU_DATA_REGISTER_WORDS   ( 16 * 2 )
+
+/* These macros allow a critical section to be added around the call to
+ * xTaskIncrementTick(), which is only ever called from interrupts at the kernel
+ * priority - ie a known priority.  Therefore these local macros are a slight
+ * optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
+ * which would require the old IPL to be read first and stored in a local variable. */
+#define portMASK_INTERRUPTS_FROM_KERNEL_ISR()      __asm volatile ( "MVTIPL	%0" ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR()    __asm volatile ( "MVTIPL	%0" ::"i" ( configKERNEL_INTERRUPT_PRIORITY ) )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void ) __attribute__( ( naked ) );
+
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+    R_BSP_PRAGMA_INTERRUPT( vSoftwareInterruptISR, VECT( ICU, SWINT ) )
+    R_BSP_ATTRIB_INTERRUPT void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+    void vSoftwareInterruptISR( void ) __attribute__( ( naked ) );
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H  */
+
+/*
+ * The tick ISR handler.  The peripheral used is configured by the application
+ * via a hook/callback function.
+ */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+    R_BSP_PRAGMA_INTERRUPT( vTickISR, _VECT( configTICK_VECTOR ) )
+    R_BSP_ATTRIB_INTERRUPT void vTickISR( void ); /* Do not add __attribute__( ( interrupt ) ). */
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+    void vTickISR( void ) __attribute__( ( interrupt ) );
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*-----------------------------------------------------------*/
+
+/* Saved as part of the task context.  If ulPortTaskHasDPFPUContext is non-zero
+ * then a DPFPU context must be saved and restored for the task. */
+#if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+    StackType_t ulPortTaskHasDPFPUContext = portNO_DPFPU_CONTEXT;
+
+#endif /* configUSE_TASK_DPFPU_SUPPORT */
+
+/* This is accessed by the inline assembler functions so is file scope for
+ * convenience. */
+extern void * pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* R0 is not included as it is the stack pointer. */
+
+    *pxTopOfStack = 0x00;
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_PSW;
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) pxCode;
+
+    /* When debugging it can be useful if every register is set to a known
+     * value.  Otherwise code space can be saved by just setting the registers
+     * that need to be set. */
+    #ifdef USE_FULL_REGISTER_INITIALISATION
+        {
+            pxTopOfStack--;
+            *pxTopOfStack = 0xffffffff; /* r15. */
+            pxTopOfStack--;
+            *pxTopOfStack = 0xeeeeeeee;
+            pxTopOfStack--;
+            *pxTopOfStack = 0xdddddddd;
+            pxTopOfStack--;
+            *pxTopOfStack = 0xcccccccc;
+            pxTopOfStack--;
+            *pxTopOfStack = 0xbbbbbbbb;
+            pxTopOfStack--;
+            *pxTopOfStack = 0xaaaaaaaa;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x99999999;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x88888888;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x77777777;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x66666666;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x55555555;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x44444444;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x33333333;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x22222222;
+            pxTopOfStack--;
+        }
+    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
+        {
+            pxTopOfStack -= 15;
+        }
+    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_FPSW;
+    pxTopOfStack--;
+    *pxTopOfStack = 0x11111111; /* Accumulator 1. */
+    pxTopOfStack--;
+    *pxTopOfStack = 0x22222222; /* Accumulator 1. */
+    pxTopOfStack--;
+    *pxTopOfStack = 0x33333333; /* Accumulator 1. */
+    pxTopOfStack--;
+    *pxTopOfStack = 0x44444444; /* Accumulator 0. */
+    pxTopOfStack--;
+    *pxTopOfStack = 0x55555555; /* Accumulator 0. */
+    pxTopOfStack--;
+    *pxTopOfStack = 0x66666666; /* Accumulator 0. */
+
+    #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+        {
+            /* The task will start without a DPFPU context.  A task that
+             * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before
+             * executing any floating point instructions. */
+            pxTopOfStack--;
+            *pxTopOfStack = portNO_DPFPU_CONTEXT;
+        }
+    #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+        {
+            /* The task will start with a DPFPU context.  Leave enough
+             * space for the registers - and ensure they are initialised if desired. */
+            #ifdef USE_FULL_REGISTER_INITIALISATION
+                {
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1515.1515; /* DR15. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1414.1414; /* DR14. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1313.1313; /* DR13. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1212.1212; /* DR12. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1111.1111; /* DR11. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1010.1010; /* DR10. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  909.0909; /* DR9. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  808.0808; /* DR8. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  707.0707; /* DR7. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  606.0606; /* DR6. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  505.0505; /* DR5. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  404.0404; /* DR4. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  303.0303; /* DR3. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  202.0202; /* DR2. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  101.0101; /* DR1. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 9876.54321;/* DR0. */
+                }
+            #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
+                {
+                    pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS;
+                    memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) );
+                }
+            #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_DCMR;  /* DCMR. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_DPSW;  /* DPSW. */
+        }
+    #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 )
+        {
+            /* Omit DPFPU support. */
+        }
+    #else /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+        {
+            #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined.
+        }
+    #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+    void vPortTaskUsesDPFPU( void )
+    {
+        /* A task is registering the fact that it needs a DPFPU context.  Set the
+         * DPFPU flag (which is saved as part of the task context). */
+        ulPortTaskHasDPFPUContext = portHAS_DPFPU_CONTEXT;
+    }
+
+#endif /* configUSE_TASK_DPFPU_SUPPORT */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+    extern void vApplicationSetupTimerInterrupt( void );
+
+    /* Use pxCurrentTCB just so it does not get optimised away. */
+    if( pxCurrentTCB != NULL )
+    {
+        /* Call an application function to set up the timer that will generate the
+         * tick interrupt.  This way the application can decide which peripheral to
+         * use.  A demo application is provided to show a suitable example. */
+        vApplicationSetupTimerInterrupt();
+
+        /* Enable the software interrupt. */
+        _IEN( _ICU_SWINT ) = 1;
+
+        /* Ensure the software interrupt is clear. */
+        _IR( _ICU_SWINT ) = 0;
+
+        /* Ensure the software interrupt is set to the kernel priority. */
+        _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+        /* Start the first task. */
+        prvStartFirstTask();
+    }
+
+    /* Should not get here. */
+    return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvStartFirstTask( void )
+{
+    __asm volatile
+    (
+
+        /* When starting the scheduler there is nothing that needs moving to the
+         * interrupt stack because the function is not called from an interrupt.
+         * Just ensure the current stack is the user stack. */
+        "SETPSW		U						\n"\
+
+
+        /* Obtain the location of the stack associated with which ever task
+         * pxCurrentTCB is currently pointing to. */
+        "MOV.L		#_pxCurrentTCB, R15		\n"\
+        "MOV.L		[R15], R15				\n"\
+        "MOV.L		[R15], R0				\n"\
+
+
+        /* Restore the registers from the stack of the task pointed to by
+         * pxCurrentTCB. */
+
+        #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+            /* The restored ulPortTaskHasDPFPUContext is to be zero here.
+             * So, it is never necessary to restore the DPFPU context here. */
+            "POP		R15									\n"\
+            "MOV.L		#_ulPortTaskHasDPFPUContext, R14	\n"\
+            "MOV.L		R15, [R14]							\n"\
+
+        #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+
+            /* Restore the DPFPU context. */
+            "DPOPM.L	DPSW-DECNT				\n"\
+            "DPOPM.D	DR0-DR15				\n"\
+
+        #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+
+        "POP		R15						\n"\
+
+        /* Accumulator low 32 bits. */
+        "MVTACLO	R15, A0					\n"\
+        "POP		R15						\n"\
+
+        /* Accumulator high 32 bits. */
+        "MVTACHI	R15, A0					\n"\
+        "POP		R15						\n"\
+
+        /* Accumulator guard. */
+        "MVTACGU	R15, A0					\n"\
+        "POP		R15						\n"\
+
+        /* Accumulator low 32 bits. */
+        "MVTACLO	R15, A1					\n"\
+        "POP		R15						\n"\
+
+        /* Accumulator high 32 bits. */
+        "MVTACHI	R15, A1					\n"\
+        "POP		R15						\n"\
+
+        /* Accumulator guard. */
+        "MVTACGU	R15, A1					\n"\
+        "POP		R15						\n"\
+
+        /* Floating point status word. */
+        "MVTC		R15, FPSW 				\n"\
+
+        /* R1 to R15 - R0 is not included as it is the SP. */
+        "POPM		R1-R15 					\n"\
+
+        /* This pops the remaining registers. */
+        "RTE								\n"\
+        "NOP								\n"\
+        "NOP								\n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+    __asm volatile
+    (
+        /* Re-enable interrupts. */
+        "SETPSW		I							\n"\
+
+
+        /* Move the data that was automatically pushed onto the interrupt stack when
+         * the interrupt occurred from the interrupt stack to the user stack.
+         *
+         * R15 is saved before it is clobbered. */
+        "PUSH.L		R15							\n"\
+
+        /* Read the user stack pointer. */
+        "MVFC		USP, R15					\n"\
+
+        /* Move the address down to the data being moved. */
+        "SUB		#12, R15					\n"\
+        "MVTC		R15, USP					\n"\
+
+        /* Copy the data across, R15, then PC, then PSW. */
+        "MOV.L		[ R0 ], [ R15 ]				\n"\
+        "MOV.L 		4[ R0 ], 4[ R15 ]			\n"\
+        "MOV.L		8[ R0 ], 8[ R15 ]			\n"\
+
+        /* Move the interrupt stack pointer to its new correct position. */
+        "ADD		#12, R0						\n"\
+
+        /* All the rest of the registers are saved directly to the user stack. */
+        "SETPSW		U							\n"\
+
+        /* Save the rest of the general registers (R15 has been saved already). */
+        "PUSHM		R1-R14						\n"\
+
+        /* Save the FPSW and accumulators. */
+        "MVFC		FPSW, R15					\n"\
+        "PUSH.L		R15							\n"\
+        "MVFACGU	#0, A1, R15					\n"\
+        "PUSH.L		R15							\n"\
+        "MVFACHI	#0, A1, R15					\n"\
+        "PUSH.L		R15							\n"\
+        "MVFACLO	#0, A1, R15					\n" /* Low order word. */ \
+        "PUSH.L		R15							\n"\
+        "MVFACGU	#0, A0, R15					\n"\
+        "PUSH.L		R15							\n"\
+        "MVFACHI	#0, A0, R15					\n"\
+        "PUSH.L		R15							\n"\
+        "MVFACLO	#0, A0, R15					\n" /* Low order word. */ \
+        "PUSH.L		R15							\n"\
+
+        #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+            /* Does the task have a DPFPU context that needs saving?  If
+             * ulPortTaskHasDPFPUContext is 0 then no. */
+            "MOV.L		#_ulPortTaskHasDPFPUContext, R15	\n"\
+            "MOV.L		[R15], R15							\n"\
+            "CMP		#0, R15								\n"\
+
+            /* Save the DPFPU context, if any. */
+            "BEQ.B		?+							\n"\
+            "DPUSHM.D	DR0-DR15					\n"\
+            "DPUSHM.L	DPSW-DECNT					\n"\
+            "?:										\n"\
+
+            /* Save ulPortTaskHasDPFPUContext itself. */
+            "PUSH.L		R15							\n"\
+
+        #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+
+            /* Save the DPFPU context, always. */
+            "DPUSHM.D	DR0-DR15					\n"\
+            "DPUSHM.L	DPSW-DECNT					\n"\
+
+        #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+
+
+        /* Save the stack pointer to the TCB. */
+        "MOV.L		#_pxCurrentTCB, R15			\n"\
+        "MOV.L		[ R15 ], R15				\n"\
+        "MOV.L		R0, [ R15 ]					\n"\
+
+
+        /* Ensure the interrupt mask is set to the syscall priority while the kernel
+         * structures are being accessed. */
+        "MVTIPL		%0 							\n"\
+
+        /* Select the next task to run. */
+        "BSR.A		_vTaskSwitchContext			\n"\
+
+        /* Reset the interrupt mask as no more data structure access is required. */
+        "MVTIPL		%1							\n"\
+
+
+        /* Load the stack pointer of the task that is now selected as the Running
+         * state task from its TCB. */
+        "MOV.L		#_pxCurrentTCB,R15			\n"\
+        "MOV.L		[ R15 ], R15				\n"\
+        "MOV.L		[ R15 ], R0					\n"\
+
+
+        /* Restore the context of the new task.  The PSW (Program Status Word) and
+         * PC will be popped by the RTE instruction. */
+
+        #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+            /* Is there a DPFPU context to restore?  If the restored
+             * ulPortTaskHasDPFPUContext is zero then no. */
+            "POP		R15									\n"\
+            "MOV.L		#_ulPortTaskHasDPFPUContext, R14	\n"\
+            "MOV.L		R15, [R14]							\n"\
+            "CMP		#0, R15								\n"\
+
+            /* Restore the DPFPU context, if any. */
+            "BEQ.B		?+							\n"\
+            "DPOPM.L	DPSW-DECNT					\n"\
+            "DPOPM.D	DR0-DR15					\n"\
+            "?:										\n"\
+
+        #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+
+            /* Restore the DPFPU context, always. */
+            "DPOPM.L	DPSW-DECNT					\n"\
+            "DPOPM.D	DR0-DR15					\n"\
+
+        #endif /* if( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+
+        "POP		R15							\n"\
+
+        /* Accumulator low 32 bits. */
+        "MVTACLO	R15, A0						\n"\
+        "POP		R15							\n"\
+
+        /* Accumulator high 32 bits. */
+        "MVTACHI	R15, A0						\n"\
+        "POP		R15							\n"\
+
+        /* Accumulator guard. */
+        "MVTACGU	R15, A0						\n"\
+        "POP		R15							\n"\
+
+        /* Accumulator low 32 bits. */
+        "MVTACLO	R15, A1						\n"\
+        "POP		R15							\n"\
+
+        /* Accumulator high 32 bits. */
+        "MVTACHI	R15, A1						\n"\
+        "POP		R15							\n"\
+
+        /* Accumulator guard. */
+        "MVTACGU	R15, A1						\n"\
+        "POP		R15							\n"\
+        "MVTC		R15, FPSW					\n"\
+        "POPM		R1-R15						\n"\
+        "RTE									\n"\
+        "NOP									\n"\
+        "NOP									  "
+        ::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
+    );
+}
+/*-----------------------------------------------------------*/
+
+void vTickISR( void )
+{
+    /* Re-enabled interrupts. */
+    __asm volatile ( "SETPSW	I");
+
+    /* Increment the tick, and perform any processing the new tick value
+     * necessitates.  Ensure IPL is at the max syscall value first. */
+    portMASK_INTERRUPTS_FROM_KERNEL_ISR();
+    {
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            taskYIELD();
+        }
+    }
+    portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortGetIPL( void )
+{
+    __asm volatile
+    (
+        "MVFC	PSW, R1			\n"\
+        "SHLR	#24, R1			\n"\
+        "RTS					  "
+    );
+
+    /* This will never get executed, but keeps the compiler from complaining. */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetIPL( uint32_t ulNewIPL )
+{
+    /* Avoid compiler warning about unreferenced parameter. */
+    ( void ) ulNewIPL;
+
+    __asm volatile
+    (
+        "PUSH	R5				\n"\
+        "MVFC	PSW, R5			\n"\
+        "SHLL	#24, R1			\n"\
+        "AND	#-0F000001H, R5 \n"\
+        "OR		R1, R5			\n"\
+        "MVTC	R5, PSW			\n"\
+        "POP	R5				\n"\
+        "RTS					  "
+    );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX700v3_DPFPU/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX700v3_DPFPU/portmacro.h
new file mode 100644
index 0000000..c8191ea
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX700v3_DPFPU/portmacro.h
@@ -0,0 +1,186 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* When the FIT configurator or the Smart Configurator is used, platform.h has to be 
+ * used. */
+    #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
+        #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
+    #endif
+
+/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will
+ * be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before
+ * making use of any DPFPU registers.  If configUSE_TASK_DPFPU_SUPPORT is set to 2 then
+ * tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has
+ * no effect.  If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care
+ * of any DPFPU context (even if DPFPU registers are used). */
+    #ifndef configUSE_TASK_DPFPU_SUPPORT
+        #define configUSE_TASK_DPFPU_SUPPORT 1
+    #endif
+
+/*-----------------------------------------------------------*/
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+ * portSTACK_TYPE and portBASE_TYPE. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+    #define portBYTE_ALIGNMENT    8     /* Could make four, according to manual. */
+    #define portSTACK_GROWTH      -1
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portNOP()    __asm volatile ( "NOP" )
+
+/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
+ * where portITU_SWINTR is the location of the software interrupt register
+ * (0x000872E0).  Don't rely on the assembler to select a register, so instead
+ * save and restore clobbered registers manually. */
+    #define portYIELD()           \
+    __asm volatile                \
+    (                             \
+        "PUSH.L	R10					\n"\
+        "MOV.L	#0x872E0, R10		\n"\
+        "MOV.B	#0x1, [R10]			\n"\
+        "CMP	[R10].UB, R10		\n"\
+        "POP    R10					\n"\
+        :::"cc"						\
+    )
+
+    #define portYIELD_FROM_ISR( x )                           if( ( x ) != pdFALSE ) portYIELD()
+
+/* Workaround to reduce errors/warnings caused by e2 studio CDT's INDEXER and CODAN. */
+    #ifdef __CDT_PARSER__
+    #ifndef __asm
+    #define __asm asm
+    #endif
+    #ifndef __attribute__
+    #define __attribute__( ... )
+    #endif
+    #endif
+
+/* These macros should not be called directly, but through the
+ * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+ * performed if configASSERT() is defined to ensure an assertion handler does not
+ * inadvertently attempt to lower the IPL when the call to assert was triggered
+ * because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+ * functions are those that end in FromISR.  FreeRTOS maintains a separate
+ * interrupt API to ensure API function and interrupt entry is as fast and as
+ * simple as possible. */
+    #define portENABLE_INTERRUPTS()                           __asm volatile ( "MVTIPL	#0")
+    #ifdef configASSERT
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+        #define portDISABLE_INTERRUPTS()                      if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL	%0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #else
+        #define portDISABLE_INTERRUPTS()                      __asm volatile ( "MVTIPL	%0"::"i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+    #endif
+
+/* Critical nesting counts are stored in the TCB. */
+    #define portCRITICAL_NESTING_IN_TCB    ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+    extern void vTaskEnterCritical( void );
+    extern void vTaskExitCritical( void );
+    #define portENTER_CRITICAL()    vTaskEnterCritical()
+    #define portEXIT_CRITICAL()     vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+    uint32_t ulPortGetIPL( void ) __attribute__( ( naked ) );
+    void vPortSetIPL( uint32_t ulNewIPL ) __attribute__( ( naked ) );
+    #define portSET_INTERRUPT_MASK_FROM_ISR()                              ulPortGetIPL(); portDISABLE_INTERRUPTS()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    vPortSetIPL( uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+/*-----------------------------------------------------------*/
+
+/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or left undefined) then tasks are
+ * created without a DPFPU context and must call vPortTaskUsesDPFPU() to give
+ * themselves a DPFPU context before using any DPFPU instructions.  If
+ * configUSE_TASK_DPFPU_SUPPORT is set to 2 then all tasks will have a DPFPU context
+ * by default. */
+    #if( configUSE_TASK_DPFPU_SUPPORT == 1 )
+        void vPortTaskUsesDPFPU( void );
+    #else
+/* Each task has a DPFPU context already, so define this function away to
+ * nothing to prevent it being called accidentally. */
+        #define vPortTaskUsesDPFPU()
+    #endif
+    #define portTASK_USES_DPFPU() vPortTaskUsesDPFPU()
+
+/* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */
+    #define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU()
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX700v3_DPFPU/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX700v3_DPFPU/readme.txt
new file mode 100644
index 0000000..9e89a09
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/RX700v3_DPFPU/readme.txt
@@ -0,0 +1,72 @@
+The following table shows which port is recommended to be used.
+
+
+RX MCU Group    CPU     FPU         FPU         Port Layer
+                Core    (Single     (Double     CC-RX                   GNURX               ICCRX (*6)
+                Type    Precision)  Precision)
+
+RX110           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX111           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX113           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX130           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX13T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+
+RX210           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX21A           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX220           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX230,RX231     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23E-A         RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23W           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24U           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+
+RX610           RXv1    Yes         ---         N/A (*4)                N/A (*4)            N/A (*4)
+RX62N,RX621     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX630           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX634           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63N,RX631     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX64M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX65N,RX651     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX66N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX62T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX62G           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX66T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+RX71M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX72M           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+Notes:
+
+*1: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide
+the configuration function.  Please be aware that port.c is hard coded to use CMT0 though it seems to be
+configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*2: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is used, please modify port.c for the configuration.  Please be aware that port.c is
+hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of
+configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*3: RX100 ports are also available.
+
+*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction.
+
+*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
+
+#define configUSE_TASK_DPFPU_SUPPORT            0
+
+*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port.
+It contains two definitions of interrupt priority like the following.
+
+#define configKERNEL_INTERRUPT_PRIORITY         1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY    4
+
+
+For more information about Renesas RX MCUs, please visit the following URL:
+
+https://www.renesas.com/products/microcontrollers-microprocessors/rx.html
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/STR75x/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/STR75x/port.c
new file mode 100644
index 0000000..0594172
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/STR75x/port.c
@@ -0,0 +1,197 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ST STR75x ARM7
+ * port.
+ *----------------------------------------------------------*/
+
+/* Library includes. */
+#include "75x_tb.h"
+#include "75x_eic.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the initial stack. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
+
+/* Prescale used on the timer clock when calculating the tick period. */
+#define portPRESCALE 20
+
+
+/*-----------------------------------------------------------*/
+
+/* Setup the TB to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The status register is set for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	#ifdef THUMB_INTERWORK
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+	#endif
+
+	pxTopOfStack--;
+
+	/* Interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+
+	return pxTopOfStack;	
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortISRStartFirstTask( void );
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortISRStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+EIC_IRQInitTypeDef  EIC_IRQInitStructure;	
+TB_InitTypeDef      TB_InitStructure;
+
+	/* Setup the EIC for the TB. */
+	EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
+	EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
+	EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
+	EIC_IRQInit(&EIC_IRQInitStructure);
+	
+	/* Setup the TB for the generation of the tick interrupt. */
+	TB_InitStructure.TB_Mode = TB_Mode_Timing;
+	TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
+	TB_InitStructure.TB_Prescaler = portPRESCALE - 1;
+	TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ );
+	TB_Init(&TB_InitStructure);
+	
+	/* Enable TB Update interrupt */
+	TB_ITConfig(TB_IT_Update, ENABLE);
+
+	/* Clear TB Update interrupt pending bit */
+	TB_ClearITPendingBit(TB_IT_Update);
+
+	/* Enable TB */
+	TB_Cmd(ENABLE);
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/STR75x/portISR.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/STR75x/portISR.c
new file mode 100644
index 0000000..f2a6f02
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/STR75x/portISR.c
@@ -0,0 +1,182 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Components that can be compiled to either ARM or THUMB mode are
+ * contained in port.c  The ISR routines, which can only be compiled
+ * to ARM mode, are contained in this file.
+ *----------------------------------------------------------*/
+
+/*
+*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
+
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * The scheduler can only be started from ARM mode, hence the inclusion of this
+ * function here.
+ */
+void vPortISRStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+void vPortISRStartFirstTask( void )
+{
+	/* Simply start the scheduler.  This is included here as it can only be
+	called from ARM mode. */
+	asm volatile (														\
+	"LDR		R0, =pxCurrentTCB								\n\t"	\
+	"LDR		R0, [R0]										\n\t"	\
+	"LDR		LR, [R0]										\n\t"	\
+																		\
+	/* The critical nesting depth is the first item on the stack. */	\
+	/* Load it into the ulCriticalNesting variable. */					\
+	"LDR		R0, =ulCriticalNesting							\n\t"	\
+	"LDMFD	LR!, {R1}											\n\t"	\
+	"STR		R1, [R0]										\n\t"	\
+																		\
+	/* Get the SPSR from the stack. */									\
+	"LDMFD	LR!, {R0}											\n\t"	\
+	"MSR		SPSR, R0										\n\t"	\
+																		\
+	/* Restore all system mode registers for the task. */				\
+	"LDMFD	LR, {R0-R14}^										\n\t"	\
+	"NOP														\n\t"	\
+																		\
+	/* Restore the return address. */									\
+	"LDR		LR, [LR, #+60]									\n\t"	\
+																		\
+	/* And return - correcting the offset in the LR to obtain the */	\
+	/* correct address. */												\
+	"SUBS PC, LR, #4											\n\t"	\
+	);																	
+}
+/*-----------------------------------------------------------*/
+
+void vPortTickISR( void )
+{
+	/* Increment the RTOS tick count, then look for the highest priority 
+	task that is ready to run. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{	
+		vTaskSwitchContext();
+	}
+			
+	/* Ready for the next interrupt. */
+	TB_ClearITPendingBit( TB_IT_Update );	
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions here to
+ * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
+ * the utilities are defined as macros in portmacro.h - as per other ports.
+ */
+#ifdef THUMB_INTERWORK
+
+	void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	void vPortDisableInterruptsFromThumb( void )
+	{
+		asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+			
+	void vPortEnableInterruptsFromThumb( void )
+	{
+		asm volatile ( 
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/	
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/	
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/	
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/	
+			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
+			"BX		R14" );					/* Return back to thumb.					*/
+	}
+
+#endif /* THUMB_INTERWORK */
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
+	asm volatile ( 
+		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
+		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
+		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
+		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
+		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed 
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable interrupts as per portEXIT_CRITICAL().					*/
+			asm volatile ( 
+				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	
+				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	
+				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	
+				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	
+				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
+		}
+	}
+}
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/STR75x/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/STR75x/portmacro.h
new file mode 100644
index 0000000..825620f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/STR75x/portmacro.h
@@ -0,0 +1,141 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portYIELD()					asm volatile ( "SWI 0" )
+#define portNOP()					asm volatile ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+/*
+ * The interrupt management utilities can only be called from ARM mode.  When
+ * THUMB_INTERWORK is defined the utilities are defined as functions in
+ * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
+ * defined then the utilities are defined as macros here - as per other ports.
+ */
+
+#ifdef THUMB_INTERWORK
+
+	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
+	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
+
+	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
+	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
+
+#else
+
+	#define portDISABLE_INTERRUPTS()											\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+	#define portENABLE_INTERRUPTS()												\
+		asm volatile (															\
+			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
+			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
+			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
+			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
+			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
+
+#endif /* THUMB_INTERWORK */
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
+{													\
+extern void vTaskSwitchContext( void );				\
+													\
+	if( xSwitchRequired ) 							\
+	{												\
+		vTaskSwitchContext();						\
+	}												\
+}
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/TriCore_1782/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/TriCore_1782/port.c
new file mode 100644
index 0000000..3d8c32d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/TriCore_1782/port.c
@@ -0,0 +1,541 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <string.h>
+
+/* TriCore specific includes. */
+#include <tc1782.h>
+#include <machine/intrinsics.h>
+#include <machine/cint.h>
+#include <machine/wdtcon.h>
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "list.h"
+
+#if configCHECK_FOR_STACK_OVERFLOW > 0
+	#error "Stack checking cannot be used with this port, as, unlike most ports, the pxTopOfStack member of the TCB is consumed CSA.  CSA starvation, loosely equivalent to stack overflow, will result in a trap exception."
+	/* The stack pointer is accessible using portCSA_TO_ADDRESS( portCSA_TO_ADDRESS( pxCurrentTCB->pxTopOfStack )[ 0 ] )[ 2 ]; */
+#endif /* configCHECK_FOR_STACK_OVERFLOW */
+
+
+/*-----------------------------------------------------------*/
+
+/* System register Definitions. */
+#define portSYSTEM_PROGRAM_STATUS_WORD					( 0x000008FFUL ) /* Supervisor Mode, MPU Register Set 0 and Call Depth Counting disabled. */
+#define portINITIAL_PRIVILEGED_PROGRAM_STATUS_WORD		( 0x000014FFUL ) /* IO Level 1, MPU Register Set 1 and Call Depth Counting disabled. */
+#define portINITIAL_UNPRIVILEGED_PROGRAM_STATUS_WORD	( 0x000010FFUL ) /* IO Level 0, MPU Register Set 1 and Call Depth Counting disabled. */
+#define portINITIAL_PCXI_UPPER_CONTEXT_WORD				( 0x00C00000UL ) /* The lower 20 bits identify the CSA address. */
+#define portINITIAL_SYSCON								( 0x00000000UL ) /* MPU Disable. */
+
+/* CSA manipulation macros. */
+#define portCSA_FCX_MASK					( 0x000FFFFFUL )
+
+/* OS Interrupt and Trap mechanisms. */
+#define portRESTORE_PSW_MASK				( ~( 0x000000FFUL ) )
+#define portSYSCALL_TRAP					( 6 )
+
+/* Each CSA contains 16 words of data. */
+#define portNUM_WORDS_IN_CSA				( 16 )
+
+/* The interrupt enable bit in the PCP_SRC register. */
+#define portENABLE_CPU_INTERRUPT 			( 1U << 12U )
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform any hardware configuration necessary to generate the tick interrupt.
+ */
+static void prvSystemTickHandler( int ) __attribute__((longcall));
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * Trap handler for yields.
+ */
+static void prvTrapYield( int iTrapIdentification );
+
+/*
+ * Priority 1 interrupt handler for yields pended from an interrupt.
+ */
+static void prvInterruptYield( int iTrapIdentification );
+
+/*-----------------------------------------------------------*/
+
+/* This reference is required by the save/restore context macros. */
+extern volatile uint32_t *pxCurrentTCB;
+
+/* Precalculate the compare match value at compile time. */
+static const uint32_t ulCompareMatchValue = ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ );
+
+/*-----------------------------------------------------------*/
+
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t *pulUpperCSA = NULL;
+uint32_t *pulLowerCSA = NULL;
+
+	/* 16 Address Registers (4 Address registers are global), 16 Data
+	Registers, and 3 System Registers.
+
+	There are 3 registers that track the CSAs.
+		FCX points to the head of globally free set of CSAs.
+		PCX for the task needs to point to Lower->Upper->NULL arrangement.
+		LCX points to the last free CSA so that corrective action can be taken.
+
+	Need two CSAs to store the context of a task.
+		The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
+		The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
+		The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
+		The Lower Context points to the Upper Context ready for the return from the interrupt handler.
+
+	 The Real stack pointer for the task is stored in the A10 which is restored
+	 with the upper context. */
+
+	/* Have to disable interrupts here because the CSAs are going to be
+	manipulated. */
+	portENTER_CRITICAL();
+	{
+		/* DSync to ensure that buffering is not a problem. */
+		_dsync();
+
+		/* Consume two free CSAs. */
+		pulLowerCSA = portCSA_TO_ADDRESS( __MFCR( $FCX ) );
+		if( NULL != pulLowerCSA )
+		{
+			/* The Lower Links to the Upper. */
+			pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] );
+		}
+
+		/* Check that we have successfully reserved two CSAs. */
+		if( ( NULL != pulLowerCSA ) && ( NULL != pulUpperCSA ) )
+		{
+			/* Remove the two consumed CSAs from the free CSA list. */
+			_disable();
+			_dsync();
+			_mtcr( $FCX, pulUpperCSA[ 0 ] );
+			_isync();
+			_enable();
+		}
+		else
+		{
+			/* Simply trigger a context list depletion trap. */
+			_svlcx();
+		}
+	}
+	portEXIT_CRITICAL();
+
+	/* Clear the upper CSA. */
+	memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
+
+	/* Upper Context. */
+	pulUpperCSA[ 2 ] = ( uint32_t )pxTopOfStack;		/* A10;	Stack Return aka Stack Pointer */
+	pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD;		/* PSW	*/
+
+	/* Clear the lower CSA. */
+	memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
+
+	/* Lower Context. */
+	pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters;		/* A4;	Address Type Parameter Register	*/
+	pulLowerCSA[ 1 ] = ( uint32_t ) pxCode;			/* A11;	Return Address aka RA */
+
+	/* PCXI pointing to the Upper context. */
+	pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( uint32_t ) portADDRESS_TO_CSA( pulUpperCSA ) );
+
+	/* Save the link to the CSA in the top of stack. */
+	pxTopOfStack = (uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA );
+
+	/* DSync to ensure that buffering is not a problem. */
+	_dsync();
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+int32_t xPortStartScheduler( void )
+{
+extern void vTrapInstallHandlers( void );
+uint32_t ulMFCR = 0UL;
+uint32_t *pulUpperCSA = NULL;
+uint32_t *pulLowerCSA = NULL;
+
+	/* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable
+	when this function is called. */
+
+	/* Set-up the timer interrupt. */
+	prvSetupTimerInterrupt();
+
+	/* Install the Trap Handlers. */
+	vTrapInstallHandlers();
+
+	/* Install the Syscall Handler for yield calls. */
+	if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvTrapYield ) )
+	{
+		/* Failed to install the yield handler, force an assert. */
+		configASSERT( ( ( volatile void * ) NULL ) );
+	}
+
+	/* Enable then install the priority 1 interrupt for pending context
+	switches from an ISR.  See mod_SRC in the TriCore manual. */
+	CPU_SRC0.reg = 	( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
+	if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) )
+	{
+		/* Failed to install the yield handler, force an assert. */
+		configASSERT( ( ( volatile void * ) NULL ) );
+	}
+
+	_disable();
+
+	/* Load the initial SYSCON. */
+	_mtcr( $SYSCON, portINITIAL_SYSCON );
+	_isync();
+
+	/* ENDINIT has already been applied in the 'cstart.c' code. */
+
+	/* Clear the PSW.CDC to enable the use of an RFE without it generating an
+	exception because this code is not genuinely in an exception. */
+	ulMFCR = __MFCR( $PSW );
+	ulMFCR &= portRESTORE_PSW_MASK;
+	_dsync();
+	_mtcr( $PSW, ulMFCR );
+	_isync();
+
+	/* Finally, perform the equivalent of a portRESTORE_CONTEXT() */
+	pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) );
+	pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] );
+	_dsync();
+	_mtcr( $PCXI, *pxCurrentTCB );
+	_isync();
+	_nop();
+	_rslcx();
+	_nop();
+
+	/* Return to the first task selected to execute. */
+	__asm volatile( "rfe" );
+
+	/* Will not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	/* Set-up the clock divider. */
+	unlock_wdtcon();
+	{
+		/* Wait until access to Endint protected register is enabled. */
+		while( 0 != ( WDT_CON0.reg & 0x1UL ) );
+
+		/* RMC == 1 so STM Clock == FPI */
+		STM_CLC.reg = ( 1UL << 8 );
+	}
+	lock_wdtcon();
+
+    /* Determine how many bits are used without changing other bits in the CMCON register. */
+	STM_CMCON.reg &= ~( 0x1fUL );
+	STM_CMCON.reg |= ( 0x1fUL - __CLZ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) );
+
+	/* Take into account the current time so a tick doesn't happen immediately. */
+	STM_CMP0.reg = ulCompareMatchValue + STM_TIM0.reg;
+
+	if( 0 != _install_int_handler( configKERNEL_INTERRUPT_PRIORITY, prvSystemTickHandler, 0 ) )
+	{
+		/* Set-up the interrupt. */
+		STM_SRC0.reg = ( configKERNEL_INTERRUPT_PRIORITY | 0x00005000UL );
+
+		/* Enable the Interrupt. */
+		STM_ISRR.reg &= ~( 0x03UL );
+		STM_ISRR.reg |= 0x1UL;
+		STM_ISRR.reg &= ~( 0x07UL );
+		STM_ICR.reg |= 0x1UL;
+	}
+	else
+	{
+		/* Failed to install the Tick Interrupt. */
+		configASSERT( ( ( volatile void * ) NULL ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSystemTickHandler( int iArg )
+{
+uint32_t ulSavedInterruptMask;
+uint32_t *pxUpperCSA = NULL;
+uint32_t xUpperCSA = 0UL;
+extern volatile uint32_t *pxCurrentTCB;
+int32_t lYieldRequired;
+
+	/* Just to avoid compiler warnings about unused parameters. */
+	( void ) iArg;
+
+	/* Clear the interrupt source. */
+	STM_ISRR.reg = 1UL;
+
+	/* Reload the Compare Match register for X ticks into the future.
+
+	If critical section or interrupt nesting budgets are exceeded, then
+	it is possible that the calculated next compare match value is in the
+	past.  If this occurs (unlikely), it is possible that the resulting
+	time slippage will exceed a single tick period.  Any adverse effect of
+	this is time bounded by the fact that only the first n bits of the 56 bit
+	STM timer are being used for a compare match, so another compare match
+	will occur after an overflow in just those n bits (not the entire 56 bits).
+	As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
+	a missed tick could result in the next tick interrupt occurring within a
+	time that is 1.7 times the desired period.  The fact that this is greater
+	than a single tick period is an effect of using a timer that cannot be
+	automatically reset, in hardware, by the occurrence of a tick interrupt.
+	Changing the tick source to a timer that has an automatic reset on compare
+	match (such as a GPTA timer) will reduce the maximum possible additional
+	period to exactly 1 times the desired period. */
+	STM_CMP0.reg += ulCompareMatchValue;
+
+	/* Kernel API calls require Critical Sections. */
+	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Increment the Tick. */
+		lYieldRequired = xTaskIncrementTick();
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+
+	if( lYieldRequired != pdFALSE )
+	{
+		/* Save the context of a task.
+		The upper context is automatically saved when entering a trap or interrupt.
+		Need to save the lower context as well and copy the PCXI CSA ID into
+		pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+		TCB of a task.
+
+		Call vTaskSwitchContext to select the next task, note that this changes the
+		value of pxCurrentTCB so that it needs to be reloaded.
+
+		Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+		that has just been switched in.
+
+		Load the context of the task.
+		Need to restore the lower context by loading the CSA from
+		pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+		In the Interrupt handler post-amble, RSLCX will restore the lower context
+		of the task. RFE will restore the upper context of the task, jump to the
+		return address and restore the previous state of interrupts being
+		enabled/disabled. */
+		_disable();
+		_dsync();
+		xUpperCSA = __MFCR( $PCXI );
+		pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
+		*pxCurrentTCB = pxUpperCSA[ 0 ];
+		vTaskSwitchContext();
+		pxUpperCSA[ 0 ] = *pxCurrentTCB;
+		CPU_SRC0.bits.SETR = 0;
+		_isync();
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * When a task is deleted, it is yielded permanently until the IDLE task
+ * has an opportunity to reclaim the memory that that task was using.
+ * Typically, the memory used by a task is the TCB and Stack but in the
+ * TriCore this includes the CSAs that were consumed as part of the Call
+ * Stack. These CSAs can only be returned to the Globally Free Pool when
+ * they are not part of the current Call Stack, hence, delaying the
+ * reclamation until the IDLE task is freeing the task's other resources.
+ * This function uses the head of the linked list of CSAs (from when the
+ * task yielded for the last time) and finds the tail (the very bottom of
+ * the call stack) and inserts this list at the head of the Free list,
+ * attaching the existing Free List to the tail of the reclaimed call stack.
+ *
+ * NOTE: the IDLE task needs processing time to complete this function
+ * and in heavily loaded systems, the Free CSAs may be consumed faster
+ * than they can be freed assuming that tasks are being spawned and
+ * deleted frequently.
+ */
+void vPortReclaimCSA( uint32_t *pxTCB )
+{
+uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA;
+uint32_t *pulNextCSA;
+
+	/* A pointer to the first CSA in the list of CSAs consumed by the task is
+	stored in the first element of the tasks TCB structure (where the stack
+	pointer would be on a traditional stack based architecture). */
+	pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK;
+
+	/* Mask off everything in the CSA link field other than the address.  If
+	the	address is NULL, then the CSA is not linking anywhere and there is
+	nothing	to do. */
+	pxTailCSA = pxHeadCSA;
+
+	/* Convert the link value to contain just a raw address and store this
+	in a local variable. */
+	pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
+
+	/* Iterate over the CSAs that were consumed as part of the task.  The
+	first field in the CSA is the pointer to then next CSA.  Mask off
+	everything in the pointer to the next CSA, other than the link address.
+	If this is NULL, then the CSA currently being pointed to is the last in
+	the chain. */
+	while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) )
+	{
+		/* Clear all bits of the pointer to the next in the chain, other
+		than the address bits themselves. */
+		pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK;
+
+		/* Move the pointer to point to the next CSA in the list. */
+		pxTailCSA = pulNextCSA[ 0 ];
+
+		/* Update the local pointer to the CSA. */
+		pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
+	}
+
+	_disable();
+	{
+		/* Look up the current free CSA head. */
+		_dsync();
+		pxFreeCSA = __MFCR( $FCX );
+
+		/* Join the current Free onto the Tail of what is being reclaimed. */
+		portCSA_TO_ADDRESS( pxTailCSA )[ 0 ] = pxFreeCSA;
+
+		/* Move the head of the reclaimed into the Free. */
+		_dsync();
+		_mtcr( $FCX, pxHeadCSA );
+		_isync();
+	}
+	_enable();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Nothing to do. Unlikely to want to end. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvTrapYield( int iTrapIdentification )
+{
+uint32_t *pxUpperCSA = NULL;
+uint32_t xUpperCSA = 0UL;
+extern volatile uint32_t *pxCurrentTCB;
+
+	switch( iTrapIdentification )
+	{
+		case portSYSCALL_TASK_YIELD:
+			/* Save the context of a task.
+			The upper context is automatically saved when entering a trap or interrupt.
+			Need to save the lower context as well and copy the PCXI CSA ID into
+			pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+			TCB of a task.
+
+			Call vTaskSwitchContext to select the next task, note that this changes the
+			value of pxCurrentTCB so that it needs to be reloaded.
+
+			Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+			that has just been switched in.
+
+			Load the context of the task.
+			Need to restore the lower context by loading the CSA from
+			pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+			In the Interrupt handler post-amble, RSLCX will restore the lower context
+			of the task. RFE will restore the upper context of the task, jump to the
+			return address and restore the previous state of interrupts being
+			enabled/disabled. */
+			_disable();
+			_dsync();
+			xUpperCSA = __MFCR( $PCXI );
+			pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
+			*pxCurrentTCB = pxUpperCSA[ 0 ];
+			vTaskSwitchContext();
+			pxUpperCSA[ 0 ] = *pxCurrentTCB;
+			CPU_SRC0.bits.SETR = 0;
+			_isync();
+			break;
+
+		default:
+			/* Unimplemented trap called. */
+			configASSERT( ( ( volatile void * ) NULL ) );
+			break;
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvInterruptYield( int iId )
+{
+uint32_t *pxUpperCSA = NULL;
+uint32_t xUpperCSA = 0UL;
+extern volatile uint32_t *pxCurrentTCB;
+
+	/* Just to remove compiler warnings. */
+	( void ) iId;
+
+	/* Save the context of a task.
+	The upper context is automatically saved when entering a trap or interrupt.
+	Need to save the lower context as well and copy the PCXI CSA ID into
+	pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
+	TCB of a task.
+
+	Call vTaskSwitchContext to select the next task, note that this changes the
+	value of pxCurrentTCB so that it needs to be reloaded.
+
+	Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
+	that has just been switched in.
+
+	Load the context of the task.
+	Need to restore the lower context by loading the CSA from
+	pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
+	In the Interrupt handler post-amble, RSLCX will restore the lower context
+	of the task. RFE will restore the upper context of the task, jump to the
+	return address and restore the previous state of interrupts being
+	enabled/disabled. */
+	_disable();
+	_dsync();
+	xUpperCSA = __MFCR( $PCXI );
+	pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
+	*pxCurrentTCB = pxUpperCSA[ 0 ];
+	vTaskSwitchContext();
+	pxUpperCSA[ 0 ] = *pxCurrentTCB;
+	CPU_SRC0.bits.SETR = 0;
+	_isync();
+}
+/*-----------------------------------------------------------*/
+
+uint32_t uxPortSetInterruptMaskFromISR( void )
+{
+uint32_t uxReturn = 0UL;
+
+	_disable();
+	uxReturn = __MFCR( $ICR );
+	_mtcr( $ICR, ( ( uxReturn & ~portCCPN_MASK ) | configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
+	_isync();
+	_enable();
+
+	/* Return just the interrupt mask bits. */
+	return ( uxReturn & portCCPN_MASK );
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/TriCore_1782/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/TriCore_1782/portmacro.h
new file mode 100644
index 0000000..521d788
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/TriCore_1782/portmacro.h
@@ -0,0 +1,173 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* System Includes. */
+#include <tc1782.h>
+#include <machine/intrinsics.h>
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*---------------------------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH							( -1 )
+#define portTICK_PERIOD_MS							( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT							4
+#define portNOP()									__asm volatile( " nop " )
+#define portCRITICAL_NESTING_IN_TCB					1
+#define portRESTORE_FIRST_TASK_PRIORITY_LEVEL		1
+
+
+/*---------------------------------------------------------------------------*/
+
+typedef struct MPU_SETTINGS { uint32_t ulNotUsed; } xMPU_SETTINGS;
+
+/* Define away the instruction from the Restore Context Macro. */
+#define portPRIVILEGE_BIT							0x0UL
+
+#define portCCPN_MASK						( 0x000000FFUL )
+
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()			vTaskEnterCritical()
+#define portEXIT_CRITICAL()				vTaskExitCritical()
+/*---------------------------------------------------------------------------*/
+
+/* CSA Manipulation. */
+#define portCSA_TO_ADDRESS( pCSA )			( ( uint32_t * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )
+#define portADDRESS_TO_CSA( pAddress )		( ( uint32_t )( ( ( ( (uint32_t)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t )( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )
+/*---------------------------------------------------------------------------*/
+
+#define portYIELD()								_syscall( 0 )
+/* Port Restore is implicit in the platform when the function is returned from the original PSW is automatically replaced. */
+#define portSYSCALL_TASK_YIELD					0
+#define portSYSCALL_RAISE_PRIORITY				1
+/*---------------------------------------------------------------------------*/
+
+/* Critical section management. */
+
+/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+#define portDISABLE_INTERRUPTS()	{																									\
+										uint32_t ulICR;																			\
+										_disable();																						\
+										ulICR = __MFCR( $ICR ); 		/* Get current ICR value. */										\
+										ulICR &= ~portCCPN_MASK;	/* Clear down mask bits. */											\
+										ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */	\
+										_mtcr( $ICR, ulICR );		/* Write back updated ICR. */										\
+										_isync();																						\
+										_enable();																						\
+									}
+
+/* Clear ICR.CCPN to allow all interrupt priorities. */
+#define portENABLE_INTERRUPTS()		{																	\
+										uint32_t ulICR;											\
+										_disable();														\
+										ulICR = __MFCR( $ICR );		/* Get current ICR value. */		\
+										ulICR &= ~portCCPN_MASK;	/* Clear down mask bits. */			\
+										_mtcr( $ICR, ulICR );		/* Write back updated ICR. */		\
+										_isync();														\
+										_enable();														\
+									}
+
+/* Set ICR.CCPN to uxSavedMaskValue. */
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) 	{																						\
+																	uint32_t ulICR;																\
+																	_disable();																			\
+																	ulICR = __MFCR( $ICR );		/* Get current ICR value. */							\
+																	ulICR &= ~portCCPN_MASK;	/* Clear down mask bits. */								\
+																	ulICR |= uxSavedMaskValue;	/* Set mask bits to previously saved mask value. */		\
+																	_mtcr( $ICR, ulICR );		/* Write back updated ICR. */							\
+																	_isync();																			\
+																	_enable();																			\
+																}
+
+
+/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY */
+extern uint32_t uxPortSetInterruptMaskFromISR( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR() 	uxPortSetInterruptMaskFromISR()
+
+/* Pend a priority 1 interrupt, which will take care of the context switch. */
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) 		if( xHigherPriorityTaskWoken != pdFALSE ) {	CPU_SRC0.bits.SETR = 1; _isync(); }
+
+/*---------------------------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*---------------------------------------------------------------------------*/
+
+/*
+ * Port specific clean up macro required to free the CSAs that were consumed by
+ * a task that has since been deleted.
+ */
+void vPortReclaimCSA( uint32_t *pxTCB );
+#define portCLEAN_UP_TCB( pxTCB )		vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/TriCore_1782/porttrap.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/TriCore_1782/porttrap.c
new file mode 100644
index 0000000..a53e95f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/GCC/TriCore_1782/porttrap.c
@@ -0,0 +1,281 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+
+/* Machine includes */
+#include <tc1782.h>
+#include <machine/intrinsics.h>
+#include <machine/cint.h>
+/*---------------------------------------------------------------------------*/
+
+/*
+ * This reference is required by the Save/Restore Context Macros.
+ */
+extern volatile uint32_t *pxCurrentTCB;
+/*-----------------------------------------------------------*/
+
+/*
+ * This file contains base definitions for all of the possible traps in the system.
+ * It is suggested to provide implementations for all of the traps but for
+ * the time being they simply trigger a DEBUG instruction so that it is easy
+ * to see what caused a particular trap.
+ *
+ * Trap Class 6, the SYSCALL, is used exclusively by the operating system.
+ */
+
+/* The Trap Classes. */
+#define portMMU_TRAP										0
+#define portIPT_TRAP										1
+#define portIE_TRAP											2
+#define portCM_TRAP											3
+#define portSBP_TRAP										4
+#define portASSERT_TRAP										5
+#define portNMI_TRAP										7
+
+/* MMU Trap Identifications. */
+#define portTIN_MMU_VIRTUAL_ADDRESS_FILL					0
+#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION				1
+
+/* Internal Protection Trap Identifications. */
+#define portTIN_IPT_PRIVILIGED_INSTRUCTION					1
+#define portTIN_IPT_MEMORY_PROTECTION_READ					2
+#define portTIN_IPT_MEMORY_PROTECTION_WRITE					3
+#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION				4
+#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS		5
+#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS			6
+#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION	7
+
+/* Instruction Error Trap Identifications. */
+#define portTIN_IE_ILLEGAL_OPCODE							1
+#define portTIN_IE_UNIMPLEMENTED_OPCODE						2
+#define portTIN_IE_INVALID_OPERAND							3
+#define portTIN_IE_DATA_ADDRESS_ALIGNMENT					4
+#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS				5
+
+/* Context Management Trap Identifications. */
+#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION				1
+#define portTIN_CM_CALL_DEPTH_OVERFLOW						2
+#define portTIN_CM_CALL_DEPTH_UNDEFLOW						3
+#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW				4
+#define portTIN_CM_CALL_STACK_UNDERFLOW						5
+#define portTIN_CM_CONTEXT_TYPE								6
+#define portTIN_CM_NESTING_ERROR							7
+
+/* System Bus and Peripherals Trap Identifications. */
+#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR			1
+#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR			2
+#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR			3
+#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR		4
+#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR			5
+#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR				6
+
+/* Assertion Trap Identifications. */
+#define portTIN_ASSERT_ARITHMETIC_OVERFLOW					1
+#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW			2
+
+/* Non-maskable Interrupt Trap Identifications. */
+#define portTIN_NMI_NON_MASKABLE_INTERRUPT					0
+/*---------------------------------------------------------------------------*/
+
+void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
+/*---------------------------------------------------------------------------*/
+
+void vTrapInstallHandlers( void )
+{
+	if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )
+	{
+		_debug();
+	}
+
+	if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )
+	{
+		_debug();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vMMUTrap( int iTrapIdentification )
+{
+	switch( iTrapIdentification )
+	{
+	case portTIN_MMU_VIRTUAL_ADDRESS_FILL:
+	case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:
+	default:
+		_debug();
+		break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vInternalProtectionTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_IPT_PRIVILIGED_INSTRUCTION:
+			/* Instruction is not allowed at current execution level, eg DISABLE at User-0. */
+
+		case portTIN_IPT_MEMORY_PROTECTION_READ:
+			/* Load word using invalid address. */
+			
+		case portTIN_IPT_MEMORY_PROTECTION_WRITE:
+			/* Store Word using invalid address. */
+			
+		case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:
+			/* PC jumped to an address outside of the valid range. */
+			
+		case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:
+			/* Access to a peripheral denied at current execution level. */
+			
+		case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:
+			/* NULL Pointer. */
+			
+		case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:
+			/* Tried to modify a global address pointer register. */
+			
+		default:
+		
+			pxCurrentTCB[ 0 ] = __MFCR( $PCXI );
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vInstructionErrorTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_IE_ILLEGAL_OPCODE:
+		case portTIN_IE_UNIMPLEMENTED_OPCODE:
+		case portTIN_IE_INVALID_OPERAND:
+		case portTIN_IE_DATA_ADDRESS_ALIGNMENT:
+		case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:
+		default:
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vContextManagementTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:
+		case portTIN_CM_CALL_DEPTH_OVERFLOW:
+		case portTIN_CM_CALL_DEPTH_UNDEFLOW:
+		case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:
+		case portTIN_CM_CALL_STACK_UNDERFLOW:
+		case portTIN_CM_CONTEXT_TYPE:
+		case portTIN_CM_NESTING_ERROR:
+		default:
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vSystemBusAndPeripheralsTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:
+		case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:
+		case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:
+		case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:
+		case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:
+		case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:
+		default:
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vAssertionTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_ASSERT_ARITHMETIC_OVERFLOW:
+		case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:
+		default:
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/
+
+void vNonMaskableInterruptTrap( int iTrapIdentification )
+{
+	/* Deliberate fall through to default. */
+	switch( iTrapIdentification )
+	{
+		case portTIN_NMI_NON_MASKABLE_INTERRUPT:
+		default:
+			_debug();
+			break;
+	}
+}
+/*---------------------------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/78K0R/ISR_Support.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/78K0R/ISR_Support.h
new file mode 100644
index 0000000..9e39621
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/78K0R/ISR_Support.h
@@ -0,0 +1,82 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+#include "FreeRTOSConfig.h"
+
+; Variables used by scheduler
+;------------------------------------------------------------------------------
+	EXTERN    pxCurrentTCB
+	EXTERN    usCriticalNesting
+
+;------------------------------------------------------------------------------
+;   portSAVE_CONTEXT MACRO
+;   Saves the context of the general purpose registers, CS and ES (only in far
+;	memory mode) registers the usCriticalNesting Value and the Stack Pointer
+;   of the active Task onto the task stack
+;------------------------------------------------------------------------------
+portSAVE_CONTEXT MACRO
+
+	PUSH      AX                    ; Save AX Register to stack.
+	PUSH      HL
+	MOV       A, CS                 ; Save CS register.
+	XCH       A, X
+	MOV       A, ES                 ; Save ES register.
+	PUSH      AX
+	PUSH      DE                    ; Save the remaining general purpose registers.
+	PUSH      BC
+	MOVW      AX, usCriticalNesting ; Save the usCriticalNesting value.
+	PUSH      AX
+	MOVW      AX, pxCurrentTCB 	    ; Save the Stack pointer.
+	MOVW      HL, AX
+	MOVW      AX, SP
+	MOVW      [HL], AX
+	ENDM
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   portRESTORE_CONTEXT MACRO
+;   Restores the task Stack Pointer then use this to restore usCriticalNesting,
+;   general purpose registers and the CS and ES (only in far memory mode)
+;   of the selected task from the task stack
+;------------------------------------------------------------------------------
+portRESTORE_CONTEXT MACRO
+	MOVW      AX, pxCurrentTCB	    ; Restore the Stack pointer.
+	MOVW      HL, AX
+	MOVW      AX, [HL]
+	MOVW      SP, AX
+	POP	      AX	                ; Restore usCriticalNesting value.
+	MOVW      usCriticalNesting, AX
+	POP	      BC                    ; Restore the necessary general purpose registers.
+	POP	      DE
+	POP       AX                    ; Restore the ES register.
+	MOV       ES, A
+	XCH       A, X                  ; Restore the CS register.
+	MOV       CS, A
+	POP       HL                    ; Restore general purpose register HL.
+	POP       AX                    ; Restore AX.
+	ENDM
+;------------------------------------------------------------------------------
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/78K0R/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/78K0R/port.c
new file mode 100644
index 0000000..fea8b79
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/78K0R/port.c
@@ -0,0 +1,225 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* The critical nesting value is initialised to a non zero value to ensure
+interrupts don't accidentally become enabled before the scheduler is started. */
+#define portINITIAL_CRITICAL_NESTING  (( uint16_t ) 10)
+
+/* Initial PSW value allocated to a newly created task.
+ *   1100011000000000
+ *   ||||||||-------------- Fill byte
+ *   |||||||--------------- Carry Flag cleared
+ *   |||||----------------- In-service priority Flags set to low level
+ *   ||||------------------ Register bank Select 0 Flag cleared
+ *   |||------------------- Auxiliary Carry Flag cleared
+ *   ||-------------------- Register bank Select 1 Flag cleared
+ *   |--------------------- Zero Flag set
+ *   ---------------------- Global Interrupt Flag set (enabled)
+ */
+#define portPSW		  (0xc6UL)
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Most ports implement critical sections by placing the interrupt flags on
+the stack before disabling interrupts.  Exiting the critical section is then
+simply a case of popping the flags from the stack.  As 78K0 IAR does not use
+a frame pointer this cannot be done as modifying the stack will clobber all
+the stack variables.  Instead each task maintains a count of the critical
+section nesting depth.  Each time a critical section is entered the count is
+incremented.  Each time a critical section is left the count is decremented -
+with interrupts only being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t *pulLocal;
+
+	#if configMEMORY_MODE == 1
+	{
+		/* Parameters are passed in on the stack, and written using a 32bit value
+		hence a space is left for the second two bytes. */
+		pxTopOfStack--;
+
+		/* Write in the parameter value. */
+		pulLocal =  ( uint32_t * ) pxTopOfStack;
+		*pulLocal = ( uint32_t ) pvParameters;
+		pxTopOfStack--;
+
+		/* These values are just spacers.  The return address of the function
+		would normally be written here. */
+		*pxTopOfStack = ( StackType_t ) 0xcdcd;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xcdcd;
+		pxTopOfStack--;
+
+		/* The start address / PSW value is also written in as a 32bit value,
+		so leave a space for the second two bytes. */
+		pxTopOfStack--;
+	
+		/* Task function start address combined with the PSW. */
+		pulLocal = ( uint32_t * ) pxTopOfStack;
+		*pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
+		pxTopOfStack--;
+
+		/* An initial value for the AX register. */
+		*pxTopOfStack = ( StackType_t ) 0x1111;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		/* Task function address is written to the stack first.  As it is
+		written as a 32bit value a space is left on the stack for the second
+		two bytes. */
+		pxTopOfStack--;
+
+		/* Task function start address combined with the PSW. */
+		pulLocal = ( uint32_t * ) pxTopOfStack;
+		*pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
+		pxTopOfStack--;
+
+		/* The parameter is passed in AX. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;
+		pxTopOfStack--;
+	}
+	#endif
+
+	/* An initial value for the HL register. */
+	*pxTopOfStack = ( StackType_t ) 0x2222;
+	pxTopOfStack--;
+
+	/* CS and ES registers. */
+	*pxTopOfStack = ( StackType_t ) 0x0F00;
+	pxTopOfStack--;
+
+	/* Finally the remaining general purpose registers DE and BC */
+	*pxTopOfStack = ( StackType_t ) 0xDEDE;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBCBC;
+	pxTopOfStack--;
+
+	/* Finally the critical section nesting count is set to zero when the task
+	first starts. */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run. */
+	vPortStart();
+
+	/* Should not get here as the tasks are now running! */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the 78K0R port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	/* Setup channel 5 of the TAU to generate the tick interrupt. */
+
+	/* First the Timer Array Unit has to be enabled. */
+	TAU0EN = 1;
+
+	/* To configure the Timer Array Unit all Channels have to first be stopped. */
+	TT0 = 0xff;
+
+	/* Interrupt of Timer Array Unit Channel 5 is disabled to set the interrupt
+	priority. */
+	TMMK05 = 1;
+
+	/* Clear Timer Array Unit Channel 5 interrupt flag. */	
+	TMIF05 = 0;
+
+	/* Set Timer Array Unit Channel 5 interrupt priority */
+	TMPR005 = 0;
+	TMPR105 = 0;
+
+	/* Set Timer Array Unit Channel 5 Mode as interval timer. */
+	TMR05 = 0x0000;
+
+	/* Set the compare match value according to the tick rate we want. */
+	TDR05 = ( TickType_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
+
+	/* Set Timer Array Unit Channel 5 output mode */
+	TOM0 &= ~0x0020;
+
+	/* Set Timer Array Unit Channel 5 output level */	
+	TOL0 &= ~0x0020;
+
+	/* Set Timer Array Unit Channel 5 output enable */	
+	TOE0 &= ~0x0020;
+
+	/* Interrupt of Timer Array Unit Channel 5 enabled */
+	TMMK05 = 0;
+
+	/* Start Timer Array Unit Channel 5.*/
+	TS0 |= 0x0020;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/78K0R/portasm.s26 b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/78K0R/portasm.s26
new file mode 100644
index 0000000..408f18b
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/78K0R/portasm.s26
@@ -0,0 +1,138 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+#include "ISR_Support.h"
+;------------------------------------------------------------------------------
+
+#if __CORE__ != __78K0R__
+	#error "This file is only for 78K0R Devices"
+#endif
+
+#define CS                    0xFFFFC
+#define ES                    0xFFFFD
+
+; Functions implemented in this file
+;------------------------------------------------------------------------------
+	PUBLIC    vPortYield
+	PUBLIC    vPortStart
+
+; Functions used by scheduler
+;------------------------------------------------------------------------------
+	EXTERN    vTaskSwitchContext
+	EXTERN    xTaskIncrementTick
+
+; Tick ISR Prototype
+;------------------------------------------------------------------------------
+;	EXTERN    ?CL78K0R_V2_L00
+
+	PUBWEAK   `??MD_INTTM05??INTVEC 68`
+	PUBLIC    MD_INTTM05
+
+MD_INTTM05    SYMBOL "MD_INTTM05"
+`??MD_INTTM05??INTVEC 68` SYMBOL "??INTVEC 68", MD_INTTM05
+
+
+
+;------------------------------------------------------------------------------
+;   Yield to another task.  Implemented as a software interrupt.  The return
+;   address and PSW will have been saved to the stack automatically before
+;   this code runs.
+;
+;   Input:  NONE
+;
+;   Call:   CALL    vPortYield
+;
+;   Output: NONE
+;
+;------------------------------------------------------------------------------
+    RSEG CODE:CODE
+vPortYield:
+	portSAVE_CONTEXT		        ; Save the context of the current task.
+	call      vTaskSwitchContext    ; Call the scheduler to select the next task.
+	portRESTORE_CONTEXT		        ; Restore the context of the next task to run.
+	retb
+
+
+;------------------------------------------------------------------------------
+;   Restore the context of the first task that is going to run.
+;
+;   Input:  NONE
+;
+;   Call:   CALL    vPortStart
+;
+;   Output: NONE
+;
+;------------------------------------------------------------------------------
+    RSEG CODE:CODE
+vPortStart:
+	portRESTORE_CONTEXT	            ; Restore the context of whichever task the ...
+	reti					        ; An interrupt stack frame is used so the task
+                                    ; is started using a RETI instruction.
+
+;------------------------------------------------------------------------------
+;   Perform the necessary steps of the Tick Count Increment and Task Switch
+;   depending on the chosen kernel configuration
+;
+;   Input:  NONE
+;
+;   Call:   ISR
+;
+;   Output: NONE
+;
+;------------------------------------------------------------------------------
+
+MD_INTTM05:
+
+	portSAVE_CONTEXT		        ; Save the context of the current task.
+	call      xTaskIncrementTick    ; Call the timer tick function.
+#if configUSE_PREEMPTION == 1
+	call      vTaskSwitchContext    ; Call the scheduler to select the next task.
+#endif
+	portRESTORE_CONTEXT		        ; Restore the context of the next task to run.
+	reti
+
+
+
+;	REQUIRE ?CL78K0R_V2_L00
+	COMMON INTVEC:CODE:ROOT(1)      ; Set ISR location to the Interrupt vector table.
+	ORG 68
+`??MD_INTTM05??INTVEC 68`:
+	DW MD_INTTM05
+
+	COMMON INTVEC:CODE:ROOT(1)      ; Set ISR location to the Interrupt vector table.
+	ORG 126
+`??vPortYield??INTVEC 126`:
+	DW vPortYield
+
+									; Set value for the usCriticalNesting.
+	RSEG NEAR_ID:CONST:SORT:NOROOT(1)
+`?<Initializer for usCriticalNesting>`:
+	DW 10
+
+;#endif
+
+      END
\ No newline at end of file
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/78K0R/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/78K0R/portmacro.h
new file mode 100644
index 0000000..1162611
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/78K0R/portmacro.h
@@ -0,0 +1,145 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint16_t
+#define portBASE_TYPE   short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if (configUSE_16_BIT_TICKS==1)
+	typedef unsigned int TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS() __asm ( "DI" )
+#define portENABLE_INTERRUPTS()	 __asm ( "EI" )
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
+
+#define portENTER_CRITICAL()													\
+{																				\
+extern volatile uint16_t usCriticalNesting;							\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	/* Now interrupts are disabled ulCriticalNesting can be accessed */			\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
+	/* times portENTER_CRITICAL() has been called. */							\
+	usCriticalNesting++;														\
+}
+
+#define portEXIT_CRITICAL()														\
+{																				\
+extern volatile uint16_t usCriticalNesting;							\
+																				\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
+	{																			\
+		/* Decrement the nesting count as we are leaving a critical section. */	\
+		usCriticalNesting--;													\
+																				\
+		/* If the nesting level has reached zero then interrupts should be */	\
+		/* re-enabled. */														\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
+		{																		\
+			portENABLE_INTERRUPTS();											\
+		}																		\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+extern void vPortStart( void );
+#define portYIELD()	__asm( "BRK" )
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
+#define portNOP()	__asm( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Hardwware specifics. */
+#define portBYTE_ALIGNMENT	2
+#define portSTACK_GROWTH	( -1 )
+#define portTICK_PERIOD_MS	( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+
+static __interrupt void P0_isr   (void);
+
+/* --------------------------------------------------------------------------*/
+/* Option-bytes and security ID                                              */
+/* --------------------------------------------------------------------------*/
+#define OPT_BYTES_SIZE     4
+#define SECU_ID_SIZE       10
+#define WATCHDOG_DISABLED  0x00
+#define LVI_ENABLED        0xFE
+#define LVI_DISABLED       0xFF
+#define RESERVED_FF        0xFF
+#define OCD_DISABLED       0x04
+#define OCD_ENABLED        0x81
+#define OCD_ENABLED_ERASE  0x80
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
new file mode 100644
index 0000000..47f88af
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
@@ -0,0 +1,300 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* IAR includes. */
+#include <intrinsics.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifndef configSETUP_TICK_INTERRUPT
+	#error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.  A default that uses the PIT is provided in the official demo application.
+#endif
+
+#ifndef configCLEAR_TICK_INTERRUPT
+	#error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.  A default that uses the PIT is provided in the official demo application.
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created.  A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS			( 0x01UL )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK			( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+mode. */
+#define portAPSR_USER_MODE				( 0x10 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.  This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts.  As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero
+then a floating point context must be saved and restored for the task. */
+uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth.  A context switch is only performed if
+if the nesting depth is 0. */
+uint32_t ulPortInterruptNesting = 0UL;
+
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro.
+
+	The fist real value on the stack is the status register, which is set for
+	system mode, with interrupts enabled.  A few NULLs are added first to ensure
+	GDB does not try decoding a non-existent return address. */
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+	{
+		/* The task will start in THUMB mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* Next the return address, which in this case is the start of the task. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	/* Next all the registers other than the stack pointer. */
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The task will start with a critical nesting count of 0 as interrupts are
+	enabled. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+	pxTopOfStack--;
+
+	/* The task will start without a floating point context.  A task that uses
+	the floating point hardware must call vPortTaskUsesFPU() before executing
+	any floating point instructions. */
+	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( ulPortInterruptNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+	/* Only continue if the CPU is not in User mode.  The CPU must be in a
+	Privileged mode for the scheduler to start. */
+	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+	ulAPSR &= portAPSR_MODE_BITS_MASK;
+	configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+	if( ulAPSR != portAPSR_USER_MODE )
+	{
+		/* Start the timer that generates the tick ISR. */
+		configSETUP_TICK_INTERRUPT();
+		vPortRestoreTaskContext();
+	}
+
+	/* Will only get here if vTaskStartScheduler() was called with the CPU in
+	a non-privileged mode or the binary point register was not set to its lowest
+	possible value. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( ulCriticalNesting == 1 )
+	{
+		configASSERT( ulPortInterruptNesting == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as the critical section is being
+		exited. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then all interrupt
+		priorities must be re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Critical nesting has reached zero so all interrupt priorities
+			should be unmasked. */
+			portENABLE_INTERRUPTS();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+	portDISABLE_INTERRUPTS();
+
+	/* Increment the RTOS tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		ulPortYieldRequired = pdTRUE;
+	}
+
+	portENABLE_INTERRUPTS();
+	configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+uint32_t ulInitialFPSCR = 0;
+
+	/* A task is registering the fact that it needs an FPU context.  Set the
+	FPU flag (which is saved as part of the task context). */
+	ulPortTaskHasFPUContext = pdTRUE;
+
+	/* Initialise the floating point status register. */
+	__asm( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) );
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
new file mode 100644
index 0000000..6a7709c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
@@ -0,0 +1,113 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	EXTERN	vTaskSwitchContext
+	EXTERN  ulCriticalNesting
+	EXTERN	pxCurrentTCB
+	EXTERN	ulPortTaskHasFPUContext
+	EXTERN  ulAsmAPIPriorityMask
+
+portSAVE_CONTEXT macro
+
+	; Save the LR and SPSR onto the system mode stack before switching to
+	; system mode to save the remaining system mode registers
+	SRSDB	sp!, #SYS_MODE
+	CPS		#SYS_MODE
+	PUSH	{R0-R12, R14}
+
+	; Push the critical nesting count
+	LDR		R2, =ulCriticalNesting
+	LDR		R1, [R2]
+	PUSH	{R1}
+
+	; Does the task have a floating point context that needs saving?  If
+	; ulPortTaskHasFPUContext is 0 then no.
+	LDR		R2, =ulPortTaskHasFPUContext
+	LDR		R3, [R2]
+	CMP		R3, #0
+
+	; Save the floating point context, if any
+	FMRXNE  R1,  FPSCR
+	VPUSHNE {D0-D15}
+#if configFPU_D32 == 1
+	VPUSHNE	{D16-D31}
+#endif ; configFPU_D32
+	PUSHNE	{R1}
+
+	; Save ulPortTaskHasFPUContext itself
+	PUSH	{R3}
+
+	; Save the stack pointer in the TCB
+	LDR		R0, =pxCurrentTCB
+	LDR		R1, [R0]
+	STR		SP, [R1]
+
+	endm
+
+; /**********************************************************************/
+
+portRESTORE_CONTEXT macro
+
+	; Set the SP to point to the stack of the task being restored.
+	LDR		R0, =pxCurrentTCB
+	LDR		R1, [R0]
+	LDR		SP, [R1]
+
+	; Is there a floating point context to restore?  If the restored
+	; ulPortTaskHasFPUContext is zero then no.
+	LDR		R0, =ulPortTaskHasFPUContext
+	POP		{R1}
+	STR		R1, [R0]
+	CMP		R1, #0
+
+	; Restore the floating point context, if any
+	POPNE 	{R0}
+#if configFPU_D32 == 1
+	VPOPNE	{D16-D31}
+#endif ; configFPU_D32
+	VPOPNE	{D0-D15}
+	VMSRNE  FPSCR, R0
+
+	; Restore the critical section nesting depth
+	LDR		R0, =ulCriticalNesting
+	POP		{R1}
+	STR		R1, [R0]
+
+	; Restore all system mode registers other than the SP (which is already
+	; being used)
+	POP		{R0-R12, R14}
+
+	; Return to the task code, loading CPSR on the way.  CPSR has the interrupt
+	; enable bit set appropriately for the task about to execute.
+	RFEIA	sp!
+
+	endm
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
new file mode 100644
index 0000000..115b705
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
@@ -0,0 +1,176 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	INCLUDE FreeRTOSConfig.h
+	INCLUDE portmacro.h
+
+	EXTERN	vTaskSwitchContext
+	EXTERN	ulPortYieldRequired
+	EXTERN	ulPortInterruptNesting
+	EXTERN	vApplicationIRQHandler
+
+	PUBLIC	FreeRTOS_SWI_Handler
+	PUBLIC  FreeRTOS_IRQ_Handler
+	PUBLIC 	vPortRestoreTaskContext
+
+SYS_MODE			EQU		0x1f
+SVC_MODE			EQU		0x13
+IRQ_MODE			EQU		0x12
+
+	SECTION .text:CODE:ROOT(2)
+	ARM
+
+	INCLUDE portASM.h
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; SVC handler is used to yield a task.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+FreeRTOS_SWI_Handler
+
+	PRESERVE8
+
+	; Save the context of the current task and select a new task to run.
+	portSAVE_CONTEXT
+	LDR R0, =vTaskSwitchContext
+	BLX	R0
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; vPortRestoreTaskContext is used to start the scheduler.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortRestoreTaskContext
+
+	PRESERVE8
+
+	; Switch to system mode
+	CPS		#SYS_MODE
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; IRQ interrupt handler used when individual priorities cannot be masked
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+FreeRTOS_IRQ_Handler
+
+	PRESERVE8
+
+	; Return to the interrupted instruction.
+	SUB		lr, lr, #4
+
+	; Push the return address and SPSR
+	PUSH	{lr}
+	MRS		lr, SPSR
+	PUSH	{lr}
+
+	; Change to supervisor mode to allow reentry.
+	CPS		#SVC_MODE
+
+	; Push used registers.
+	PUSH	{r0-r4, r12}
+
+	; Increment nesting count.  r3 holds the address of ulPortInterruptNesting
+	; for future use.  r1 holds the original ulPortInterruptNesting value for
+	; future use.
+	LDR		r3, =ulPortInterruptNesting
+	LDR		r1, [r3]
+	ADD		r4, r1, #1
+	STR		r4, [r3]
+
+	; Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
+	; future use.
+	MOV		r2, sp
+	AND		r2, r2, #4
+	SUB		sp, sp, r2
+
+	PUSH	{r0-r4, lr}
+
+	; Call the port part specific handler.
+	LDR		r0, =vApplicationIRQHandler
+	BLX		r0
+	POP		{r0-r4, lr}
+	ADD		sp, sp, r2
+
+	CPSID	i
+
+	; Write to the EOI register.
+	LDR 	r4, =configEOI_ADDRESS
+	STR		r0, [r4]
+
+	; Restore the old nesting count
+	STR		r1, [r3]
+
+	; A context switch is never performed if the nesting count is not 0.
+	CMP		r1, #0
+	BNE		exit_without_switch
+
+	; Did the interrupt request a context switch?  r1 holds the address of
+	; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+	; use.
+	LDR		r1, =ulPortYieldRequired
+	LDR		r0, [r1]
+	CMP		r0, #0
+	BNE		switch_before_exit
+
+exit_without_switch
+	; No context switch.  Restore used registers, LR_irq and SPSR before
+	; returning.
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	MOVS	PC, LR
+
+switch_before_exit
+	; A context switch is to be performed.  Clear the context switch pending
+	; flag.
+	MOV		r0, #0
+	STR		r0, [r1]
+
+	; Restore used registers, LR-irq and SPSR before saving the context
+	; to the task stack.
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	portSAVE_CONTEXT
+
+	; Call the function that selects the new task to execute.
+	; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+	; instructions, or 8 byte aligned stack allocated data.  LR does not need
+	; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
+	LDR		r0, =vTaskSwitchContext
+	BLX		r0
+
+	; Restore the context of, and branch to, the task selected to execute next.
+	portRESTORE_CONTEXT
+
+	END
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h
new file mode 100644
index 0000000..66fb730
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h
@@ -0,0 +1,162 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* IAR includes. */
+#ifdef __ICCARM__
+
+	#include <intrinsics.h>
+
+	#ifdef __cplusplus
+		extern "C" {
+	#endif
+
+	/*-----------------------------------------------------------
+	 * Port specific definitions.
+	 *
+	 * The settings in this file configure FreeRTOS correctly for the given hardware
+	 * and compiler.
+	 *
+	 * These settings should not be altered.
+	 *-----------------------------------------------------------
+	 */
+
+	/* Type definitions. */
+	#define portCHAR		char
+	#define portFLOAT		float
+	#define portDOUBLE		double
+	#define portLONG		long
+	#define portSHORT		short
+	#define portSTACK_TYPE	uint32_t
+	#define portBASE_TYPE	long
+
+	typedef portSTACK_TYPE StackType_t;
+	typedef long BaseType_t;
+	typedef unsigned long UBaseType_t;
+
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+
+	/*-----------------------------------------------------------*/
+
+	/* Hardware specifics. */
+	#define portSTACK_GROWTH			( -1 )
+	#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+	#define portBYTE_ALIGNMENT			8
+
+	/*-----------------------------------------------------------*/
+
+	/* Task utilities. */
+
+	/* Called at the end of an ISR that can cause a context switch. */
+	#define portEND_SWITCHING_ISR( xSwitchRequired )\
+	{												\
+	extern uint32_t ulPortYieldRequired;			\
+													\
+		if( xSwitchRequired != pdFALSE )			\
+		{											\
+			ulPortYieldRequired = pdTRUE;			\
+		}											\
+	}
+
+	#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+	#define portYIELD() __asm volatile ( "SWI 0" ); __ISB()
+
+
+	/*-----------------------------------------------------------
+	 * Critical section control
+	 *----------------------------------------------------------*/
+
+	extern void vPortEnterCritical( void );
+	extern void vPortExitCritical( void );
+	extern uint32_t ulPortSetInterruptMask( void );
+	extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+
+	#define portENTER_CRITICAL()		vPortEnterCritical();
+	#define portEXIT_CRITICAL()			vPortExitCritical();
+	#define portDISABLE_INTERRUPTS()	__disable_irq(); __DSB(); __ISB() /* No priority mask register so global disable is used. */
+	#define portENABLE_INTERRUPTS()		__enable_irq()
+	#define portSET_INTERRUPT_MASK_FROM_ISR()		__get_interrupt_state(); __disable_irq() /* No priority mask register so global disable is used. */
+	#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	__set_interrupt_state(x)
+
+	/*-----------------------------------------------------------*/
+
+	/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+	not required for this port but included in case common demo code that uses these
+	macros is used. */
+	#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+	#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+	/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+	handler for whichever peripheral is used to generate the RTOS tick. */
+	void FreeRTOS_Tick_Handler( void );
+
+	/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+	before any floating point instructions are executed. */
+	void vPortTaskUsesFPU( void );
+	#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+	/* Architecture specific optimisations. */
+	#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+		#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+	#endif
+
+	#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+		/* Store/clear the ready priorities in a bit map. */
+		#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+		#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+		/*-----------------------------------------------------------*/
+
+		#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )
+
+	#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+	#define portNOP() __asm volatile( "NOP" )
+
+
+	#ifdef __cplusplus
+		} /* extern C */
+	#endif
+
+	/* Suppress warnings that are generated by the IAR tools, but cannot be
+	fixed in the source code because to do so would cause other compilers to
+	generate warnings. */
+	#pragma diag_suppress=Pe191
+	#pragma diag_suppress=Pa082
+
+#endif /* __ICCARM__ */
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA9/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA9/port.c
new file mode 100644
index 0000000..eb396a2
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA9/port.c
@@ -0,0 +1,439 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* IAR includes. */
+#include <intrinsics.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
+	#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
+	#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configUNIQUE_INTERRUPT_PRIORITIES
+	#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configSETUP_TICK_INTERRUPT
+	#error configSETUP_TICK_INTERRUPT() must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif /* configSETUP_TICK_INTERRUPT */
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/* In case security extensions are implemented. */
+#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+#endif
+
+#ifndef configCLEAR_TICK_INTERRUPT
+	#define configCLEAR_TICK_INTERRUPT()
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
+
+/* In all GICs 255 can be written to the priority mask register to unmask all
+(but the lowest) interrupt priority. */
+#define portUNMASK_VALUE				( 0xFFUL )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created.  A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS			( 0x01UL )
+
+/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
+point is zero. */
+#define portBINARY_POINT_BITS			( ( uint8_t ) 0x03 )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK			( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+mode. */
+#define portAPSR_USER_MODE				( 0x10 )
+
+/* Macro to unmask all interrupt priorities. */
+#define portCLEAR_INTERRUPT_MASK()											\
+{																			\
+	__disable_irq();														\
+	portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;					\
+	__asm(	"DSB		\n"													\
+			"ISB		\n" );												\
+	__enable_irq();															\
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.  This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts.  As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero
+then a floating point context must be saved and restored for the task. */
+uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth.  A context switch is only performed if
+if the nesting depth is 0. */
+uint32_t ulPortInterruptNesting = 0UL;
+
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro.
+
+	The fist real value on the stack is the status register, which is set for
+	system mode, with interrupts enabled.  A few NULLs are added first to ensure
+	GDB does not try decoding a non-existent return address. */
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+	{
+		/* The task will start in THUMB mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* Next the return address, which in this case is the start of the task. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	/* Next all the registers other than the stack pointer. */
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The task will start with a critical nesting count of 0 as interrupts are
+	enabled. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+	pxTopOfStack--;
+
+	/* The task will start without a floating point context.  A task that uses
+	the floating point hardware must call vPortTaskUsesFPU() before executing
+	any floating point instructions. */
+	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( ulPortInterruptNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+	/* Only continue if the CPU is not in User mode.  The CPU must be in a
+	Privileged mode for the scheduler to start. */
+	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+	ulAPSR &= portAPSR_MODE_BITS_MASK;
+	configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+	if( ulAPSR != portAPSR_USER_MODE )
+	{
+		/* Only continue if the binary point value is set to its lowest possible
+		setting.  See the comments in vPortValidateInterruptPriority() below for
+		more information. */
+		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+
+		if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+		{
+			/* Start the timer that generates the tick ISR. */
+			configSETUP_TICK_INTERRUPT();
+
+			__enable_irq();
+			vPortRestoreTaskContext();
+		}
+	}
+
+	/* Will only get here if vTaskStartScheduler() was called with the CPU in
+	a non-privileged mode or the binary point register was not set to its lowest
+	possible value. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 	*/
+	ulPortSetInterruptMask();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+	
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API 
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( ulCriticalNesting == 1 )
+	{
+		configASSERT( ulPortInterruptNesting == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as the critical section is being
+		exited. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then all interrupt
+		priorities must be re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Critical nesting has reached zero so all interrupt priorities
+			should be unmasked. */
+			portCLEAR_INTERRUPT_MASK();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+	/* Set interrupt mask before altering scheduler structures.   The tick
+	handler runs at the lowest priority, so interrupts cannot already be masked,
+	so there is no need to save and restore the current mask value. */
+	__disable_irq();
+	portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+	__asm(	"DSB		\n"
+			"ISB		\n" );
+	__enable_irq();
+
+	/* Increment the RTOS tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		ulPortYieldRequired = pdTRUE;
+	}
+
+	/* Ensure all interrupt priorities are active again. */
+	portCLEAR_INTERRUPT_MASK();
+	configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+uint32_t ulInitialFPSCR = 0;
+
+	/* A task is registering the fact that it needs an FPU context.  Set the
+	FPU flag (which is saved as part of the task context). */
+	ulPortTaskHasFPUContext = pdTRUE;
+
+	/* Initialise the floating point status register. */
+	__asm( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) );
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( uint32_t ulNewMaskValue )
+{
+	if( ulNewMaskValue == pdFALSE )
+	{
+		portCLEAR_INTERRUPT_MASK();
+	}
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortSetInterruptMask( void )
+{
+uint32_t ulReturn;
+
+	__disable_irq();
+	if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+	{
+		/* Interrupts were already masked. */
+		ulReturn = pdTRUE;
+	}
+	else
+	{
+		ulReturn = pdFALSE;
+		portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+		__asm(	"DSB		\n"
+				"ISB		\n" );
+	}
+	__enable_irq();
+
+	return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+		/* The following assertion will fail if a service routine (ISR) for
+		an interrupt that has been assigned a priority above
+		configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+		function.  ISR safe FreeRTOS API functions must *only* be called
+		from interrupts that have been assigned a priority at or below
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		Numerically low interrupt priority numbers represent logically high
+		interrupt priorities, therefore the priority of the interrupt must
+		be set to a value equal to or numerically *higher* than
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		FreeRTOS maintains separate thread and ISR API functions to ensure
+		interrupt entry is as fast and simple as possible.
+
+		The following links provide detailed information:
+		https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+		https://www.FreeRTOS.org/FAQHelp.html */
+		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+		/* Priority grouping:  The interrupt controller (GIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		The priority grouping is configured by the GIC's binary point register
+		(ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
+		possible value (which may be above 0). */
+		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.h
new file mode 100644
index 0000000..4170c2e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.h
@@ -0,0 +1,115 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	EXTERN	vTaskSwitchContext
+	EXTERN  ulCriticalNesting
+	EXTERN	pxCurrentTCB
+	EXTERN	ulPortTaskHasFPUContext
+	EXTERN  ulAsmAPIPriorityMask
+
+portSAVE_CONTEXT macro
+
+	; Save the LR and SPSR onto the system mode stack before switching to
+	; system mode to save the remaining system mode registers
+	SRSDB	sp!, #SYS_MODE
+	CPS		#SYS_MODE
+	PUSH	{R0-R12, R14}
+
+	; Push the critical nesting count
+	LDR		R2, =ulCriticalNesting
+	LDR		R1, [R2]
+	PUSH	{R1}
+
+	; Does the task have a floating point context that needs saving?  If
+	; ulPortTaskHasFPUContext is 0 then no.
+	LDR		R2, =ulPortTaskHasFPUContext
+	LDR		R3, [R2]
+	CMP		R3, #0
+
+	; Save the floating point context, if any
+	FMRXNE  R1,  FPSCR
+	VPUSHNE {D0-D15}
+	VPUSHNE	{D16-D31}
+	PUSHNE	{R1}
+
+	; Save ulPortTaskHasFPUContext itself
+	PUSH	{R3}
+
+	; Save the stack pointer in the TCB
+	LDR		R0, =pxCurrentTCB
+	LDR		R1, [R0]
+	STR		SP, [R1]
+
+	endm
+
+; /**********************************************************************/
+
+portRESTORE_CONTEXT macro
+
+	; Set the SP to point to the stack of the task being restored.
+	LDR		R0, =pxCurrentTCB
+	LDR		R1, [R0]
+	LDR		SP, [R1]
+
+	; Is there a floating point context to restore?  If the restored
+	; ulPortTaskHasFPUContext is zero then no.
+	LDR		R0, =ulPortTaskHasFPUContext
+	POP		{R1}
+	STR		R1, [R0]
+	CMP		R1, #0
+
+	; Restore the floating point context, if any
+	POPNE 	{R0}
+	VPOPNE	{D16-D31}
+	VPOPNE	{D0-D15}
+	VMSRNE  FPSCR, R0
+
+	; Restore the critical section nesting depth
+	LDR		R0, =ulCriticalNesting
+	POP		{R1}
+	STR		R1, [R0]
+
+	; Ensure the priority mask is correct for the critical nesting depth
+	LDR		R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS
+	CMP		R1, #0
+	MOVEQ	R4, #255
+	LDRNE	R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )
+	STR		R4, [r2]
+
+	; Restore all system mode registers other than the SP (which is already
+	; being used)
+	POP		{R0-R12, R14}
+
+	; Return to the task code, loading CPSR on the way.
+	RFEIA	sp!
+
+	endm
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s
new file mode 100644
index 0000000..0186eb4
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s
@@ -0,0 +1,177 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	INCLUDE FreeRTOSConfig.h
+	INCLUDE portmacro.h
+
+	EXTERN	vApplicationIRQHandler
+	EXTERN	vTaskSwitchContext
+	EXTERN	ulPortYieldRequired
+	EXTERN	ulPortInterruptNesting
+
+	PUBLIC	FreeRTOS_SWI_Handler
+	PUBLIC  FreeRTOS_IRQ_Handler
+	PUBLIC 	vPortRestoreTaskContext
+
+SYS_MODE			EQU		0x1f
+SVC_MODE			EQU		0x13
+IRQ_MODE			EQU		0x12
+
+
+	SECTION .text:CODE:ROOT(2)
+	ARM
+
+	INCLUDE portASM.h
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; SVC handler is used to yield a task.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+FreeRTOS_SWI_Handler
+
+	PRESERVE8
+
+	; Save the context of the current task and select a new task to run.
+	portSAVE_CONTEXT
+	LDR R0, =vTaskSwitchContext
+	BLX	R0
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; vPortRestoreTaskContext is used to start the scheduler.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortRestoreTaskContext
+	; Switch to system mode
+	CPS		#SYS_MODE
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; PL390 GIC interrupt handler
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+FreeRTOS_IRQ_Handler
+
+	; Return to the interrupted instruction.
+	SUB		lr, lr, #4
+
+	; Push the return address and SPSR
+	PUSH	{lr}
+	MRS		lr, SPSR
+	PUSH	{lr}
+
+	; Change to supervisor mode to allow reentry.
+	CPS		#SVC_MODE
+
+	; Push used registers.
+	PUSH	{r0-r4, r12}
+
+	; Increment nesting count.  r3 holds the address of ulPortInterruptNesting
+	; for future use.  r1 holds the original ulPortInterruptNesting value for
+	; future use.
+	LDR		r3, =ulPortInterruptNesting
+	LDR		r1, [r3]
+	ADD		r4, r1, #1
+	STR		r4, [r3]
+
+	; Read value from the interrupt acknowledge register, which is stored in r0
+	; for future parameter and interrupt clearing use.
+	LDR 	r2, =portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS
+	LDR		r0, [r2]
+
+	; Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
+	; future use.  _RB_ Is this ever necessary if start of stack is 8-byte aligned?
+	MOV		r2, sp
+	AND		r2, r2, #4
+	SUB		sp, sp, r2
+
+	; Call the interrupt handler.  r4 is pushed to maintain alignment.
+	PUSH	{r0-r4, lr}
+	LDR		r1, =vApplicationIRQHandler
+	BLX		r1
+	POP		{r0-r4, lr}
+	ADD		sp, sp, r2
+
+	CPSID	i
+
+	; Write the value read from ICCIAR to ICCEOIR
+	LDR 	r4, =portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS
+	STR		r0, [r4]
+
+	; Restore the old nesting count
+	STR		r1, [r3]
+
+	; A context switch is never performed if the nesting count is not 0
+	CMP		r1, #0
+	BNE		exit_without_switch
+
+	; Did the interrupt request a context switch?  r1 holds the address of
+	; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+	; use.
+	LDR		r1, =ulPortYieldRequired
+	LDR		r0, [r1]
+	CMP		r0, #0
+	BNE		switch_before_exit
+
+exit_without_switch
+	; No context switch.  Restore used registers, LR_irq and SPSR before
+	; returning.
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	MOVS	PC, LR
+
+switch_before_exit
+	; A context switch is to be performed.  Clear the context switch pending
+	; flag.
+	MOV		r0, #0
+	STR		r0, [r1]
+
+	; Restore used registers, LR-irq and SPSR before saving the context
+	; to the task stack.
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	portSAVE_CONTEXT
+
+	; Call the function that selects the new task to execute.
+	; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+	; instructions, or 8 byte aligned stack allocated data.  LR does not need
+	; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
+	LDR		r0, =vTaskSwitchContext
+	BLX		r0
+
+	; Restore the context of, and branch to, the task selected to execute next.
+	portRESTORE_CONTEXT
+
+
+	END
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA9/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA9/portmacro.h
new file mode 100644
index 0000000..dd78c1a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CA9/portmacro.h
@@ -0,0 +1,209 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* IAR includes. */
+#ifdef __ICCARM__
+
+	#include <intrinsics.h>
+
+	#ifdef __cplusplus
+		extern "C" {
+	#endif
+
+	/*-----------------------------------------------------------
+	 * Port specific definitions.
+	 *
+	 * The settings in this file configure FreeRTOS correctly for the given hardware
+	 * and compiler.
+	 *
+	 * These settings should not be altered.
+	 *-----------------------------------------------------------
+	 */
+
+	/* Type definitions. */
+	#define portCHAR		char
+	#define portFLOAT		float
+	#define portDOUBLE		double
+	#define portLONG		long
+	#define portSHORT		short
+	#define portSTACK_TYPE	uint32_t
+	#define portBASE_TYPE	long
+
+	typedef portSTACK_TYPE StackType_t;
+	typedef long BaseType_t;
+	typedef unsigned long UBaseType_t;
+
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+
+	/*-----------------------------------------------------------*/
+
+	/* Hardware specifics. */
+	#define portSTACK_GROWTH			( -1 )
+	#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+	#define portBYTE_ALIGNMENT			8
+
+	/*-----------------------------------------------------------*/
+
+	/* Task utilities. */
+
+	/* Called at the end of an ISR that can cause a context switch. */
+	#define portEND_SWITCHING_ISR( xSwitchRequired )\
+	{												\
+	extern uint32_t ulPortYieldRequired;			\
+													\
+		if( xSwitchRequired != pdFALSE )			\
+		{											\
+			ulPortYieldRequired = pdTRUE;			\
+		}											\
+	}
+
+	#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+	#define portYIELD() __asm( "SWI 0" );
+
+
+	/*-----------------------------------------------------------
+	 * Critical section control
+	 *----------------------------------------------------------*/
+
+	extern void vPortEnterCritical( void );
+	extern void vPortExitCritical( void );
+	extern uint32_t ulPortSetInterruptMask( void );
+	extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+
+	/* These macros do not globally disable/enable interrupts.  They do mask off
+	interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+	#define portENTER_CRITICAL()		vPortEnterCritical();
+	#define portEXIT_CRITICAL()			vPortExitCritical();
+	#define portDISABLE_INTERRUPTS()	ulPortSetInterruptMask()
+	#define portENABLE_INTERRUPTS()		vPortClearInterruptMask( 0 )
+	#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortSetInterruptMask()
+	#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask(x)
+
+	/*-----------------------------------------------------------*/
+
+	/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+	not required for this port but included in case common demo code that uses these
+	macros is used. */
+	#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+	#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+	/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+	handler for whichever peripheral is used to generate the RTOS tick. */
+	void FreeRTOS_Tick_Handler( void );
+
+	/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+	before any floating point instructions are executed. */
+	void vPortTaskUsesFPU( void );
+	#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+	#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+	#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+	/* Architecture specific optimisations. */
+	#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+		#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+	#endif
+
+	#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+		/* Store/clear the ready priorities in a bit map. */
+		#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+		#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+		/*-----------------------------------------------------------*/
+
+		#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )
+
+	#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+	#ifdef configASSERT
+		void vPortValidateInterruptPriority( void );
+		#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+	#endif /* configASSERT */
+
+	#define portNOP() __asm volatile( "NOP" )
+
+
+	#ifdef __cplusplus
+		} /* extern C */
+	#endif
+
+	/* Suppress warnings that are generated by the IAR tools, but cannot be
+	fixed in the source code because to do so would cause other compilers to
+	generate warnings. */
+	#pragma diag_suppress=Pe191
+	#pragma diag_suppress=Pa082
+
+#endif /* __ICCARM__ */
+
+
+/* The number of bits to shift for an interrupt priority is dependent on the
+number of bits implemented by the interrupt controller. */
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16
+	#define portPRIORITY_SHIFT 4
+	#define portMAX_BINARY_POINT_VALUE	3
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
+	#define portPRIORITY_SHIFT 3
+	#define portMAX_BINARY_POINT_VALUE	2
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
+	#define portPRIORITY_SHIFT 2
+	#define portMAX_BINARY_POINT_VALUE	1
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
+	#define portPRIORITY_SHIFT 1
+	#define portMAX_BINARY_POINT_VALUE	0
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
+	#define portPRIORITY_SHIFT 0
+	#define portMAX_BINARY_POINT_VALUE	0
+#else
+	#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+#endif
+
+/* Interrupt controller access addresses. */
+#define portICCPMR_PRIORITY_MASK_OFFSET  						( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET 				( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET 					( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET							( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET						( 0x14 )
+
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS 		( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER 					( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS 	( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS 		( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS 			( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER 					( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER 				( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM0/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM0/port.c
new file mode 100644
index 0000000..39d7451
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM0/port.c
@@ -0,0 +1,431 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM0 port.
+*----------------------------------------------------------*/
+
+/* IAR includes. */
+#include "intrinsics.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_INT_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
+#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                      ( 0x01000000 )
+
+/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
+ * defined.  The value 255 should also ensure backward compatibility.
+ * FreeRTOS.org versions prior to V4.3.0 did not include this definition. */
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+    #define configKERNEL_INTERRUPT_PRIORITY    0
+#endif
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER    ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#ifndef portMISSED_COUNTS_FACTOR
+    #define portMISSED_COUNTS_FACTOR    ( 45UL )
+#endif
+
+/* The number of SysTick increments that make up one tick period. */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/* The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer. */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/* Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only. */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortSysTickHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    pxTopOfStack--;                                   /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+    *pxTopOfStack = portINITIAL_XPSR;                 /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) pxCode;           /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
+    pxTopOfStack -= 5;                                /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters;     /* R0 */
+    pxTopOfStack -= 8;                                /* R11..R4. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( uxCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    for( ; ; )
+    {
+    }
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    /* Make PendSV and SysTick the lowest priority interrupts. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Start the first task. */
+    vPortStartFirstTask();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortYield( void )
+{
+    /* Set a PendSV to request a context switch. */
+    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET;
+
+    /* Barriers are normally not required but do ensure the code is completely
+     * within the specified behaviour for the architecture. */
+    __DSB();
+    __ISB();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+    __DSB();
+    __ISB();
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__weak void vPortSetupTimerInterrupt( void )
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR;
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and reset the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+    __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+         * is accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods.  -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __disable_interrupt();
+        __DSB();
+        __ISB();
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above __disable_interrupt()
+             * call above. */
+            __enable_interrupt();
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again.  However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __DSB();
+                __WFI();
+                __ISB();
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately.  see comments above
+             * __disable_interrupt() call above. */
+            __enable_interrupt();
+            __DSB();
+            __ISB();
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __disable_interrupt();
+            __DSB();
+            __ISB();
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is yet
+             * to count to zero (in which case an interrupt other than the SysTick
+             * must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrpts enabled. */
+            __enable_interrupt();
+        }
+    }
+
+#endif /* configUSE_TICKLESS_IDLE */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s
new file mode 100644
index 0000000..f1fdc17
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s
@@ -0,0 +1,131 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include <FreeRTOSConfig.h>
+
+	RSEG    CODE:CODE(2)
+	thumb
+
+	EXTERN vPortYieldFromISR
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+
+	PUBLIC vSetMSP
+	PUBLIC xPortPendSVHandler
+	PUBLIC vPortSVCHandler
+	PUBLIC vPortStartFirstTask
+	PUBLIC ulSetInterruptMaskFromISR
+	PUBLIC vClearInterruptMaskFromISR
+
+/*-----------------------------------------------------------*/
+
+vSetMSP
+	msr msp, r0
+	bx lr
+
+/*-----------------------------------------------------------*/
+
+xPortPendSVHandler:
+	mrs r0, psp
+
+	ldr	r3, =pxCurrentTCB	/* Get the location of the current TCB. */
+	ldr	r2, [r3]
+
+	subs r0, r0, #32		/* Make space for the remaining low registers. */
+	str r0, [r2]			/* Save the new top of stack. */
+	stmia r0!, {r4-r7}		/* Store the low registers that are not saved automatically. */
+	mov r4, r8				/* Store the high registers. */
+	mov r5, r9
+	mov r6, r10
+	mov r7, r11
+	stmia r0!, {r4-r7}
+
+	push {r3, r14}
+	cpsid i
+	bl vTaskSwitchContext
+	cpsie i
+	pop {r2, r3}			/* lr goes in r3. r2 now holds tcb pointer. */
+
+	ldr r1, [r2]
+	ldr r0, [r1]			/* The first item in pxCurrentTCB is the task top of stack. */
+	adds r0, r0, #16		/* Move to the high registers. */
+	ldmia r0!, {r4-r7}		/* Pop the high registers. */
+	mov r8, r4
+	mov r9, r5
+	mov r10, r6
+	mov r11, r7
+
+	msr psp, r0				/* Remember the new top of stack for the task. */
+
+	subs r0, r0, #32		/* Go back for the low registers that are not automatically restored. */
+	ldmia r0!, {r4-r7}		/* Pop low registers.  */
+
+	bx r3
+
+/*-----------------------------------------------------------*/
+
+vPortSVCHandler;
+	/* This function is no longer used, but retained for backward
+	compatibility. */
+	bx lr
+
+/*-----------------------------------------------------------*/
+
+vPortStartFirstTask
+	/* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
+	table offset register that can be used to locate the initial stack value.
+	Not all M0 parts have the application vector table at address 0. */
+
+	ldr	r3, =pxCurrentTCB	/* Obtain location of pxCurrentTCB. */
+	ldr r1, [r3]
+	ldr r0, [r1]			/* The first item in pxCurrentTCB is the task top of stack. */
+	adds r0, #32			/* Discard everything up to r0. */
+	msr psp, r0				/* This is now the new top of stack to use in the task. */
+	movs r0, #2				/* Switch to the psp stack. */
+	msr CONTROL, r0
+	isb
+	pop {r0-r5}				/* Pop the registers that are saved automatically. */
+	mov lr, r5				/* lr is now in r5. */
+	pop {r3}				/* The return address is now in r3. */
+	pop {r2}				/* Pop and discard the XPSR. */
+	cpsie i					/* The first task has its context and interrupts can be enabled. */
+	bx r3					/* Jump to the user defined task code. */
+
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMaskFromISR
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+
+/*-----------------------------------------------------------*/
+
+vClearInterruptMaskFromISR
+	msr PRIMASK, r0
+	bx lr
+
+	END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM0/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM0/portmacro.h
new file mode 100644
index 0000000..5c5cab7
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM0/portmacro.h
@@ -0,0 +1,128 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+    extern void vPortYield( void );
+    #define portNVIC_INT_CTRL     ( ( volatile uint32_t * ) 0xe000ed04 )
+    #define portNVIC_PENDSVSET    0x10000000
+    #define portYIELD()                                 vPortYield()
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+    extern uint32_t ulSetInterruptMaskFromISR( void );
+    extern void vClearInterruptMaskFromISR( uint32_t ulMask );
+
+    #define portDISABLE_INTERRUPTS()                  __asm volatile ( "cpsid i" )
+    #define portENABLE_INTERRUPTS()                   __asm volatile ( "cpsie i" )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMaskFromISR()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMaskFromISR( x )
+
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+    #define portNOP()
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+    #pragma diag_suppress=Pa082
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/port.c
new file mode 100644
index 0000000..852a11c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/port.c
@@ -0,0 +1,1192 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if ( configENABLE_TRUSTZONE == 1 )
+    /* Secure components includes. */
+    #include "secure_context.h"
+    #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
+#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ            configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT          ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the
+ * same a the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE    ( 3UL )
+#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS      ( 20UL )
+#define portCPACR_CP11_POS      ( 22UL )
+
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS     ( 31UL )
+#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS     ( 30UL )
+#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS                ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS                ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS                ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS                ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS                ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS                ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS                ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS                ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE           ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The maximum 24-bit number.
+ *
+ * It is needed because the systick is a 24-bit counter.
+ */
+#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )
+
+/**
+ * @brief A fiddle factor to estimate the number of SysTick counts that would
+ * have occurred while the SysTick counter is stopped during tickless idle
+ * calculations.
+ */
+#define portMISSED_COUNTS_FACTOR    ( 45UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR    ( 0x01000000 )
+
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         FD
+ * 1111 1111  1111 1111  1111 1111  1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
+#else
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         BC
+ * 1111 1111  1111 1111  1111 1111  1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS    1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT    0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+
+/**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ *
+ * The implementation in this file is weak to allow application writers to
+ * change the timer used to generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether the current execution context is interrupt.
+ *
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE
+ * otherwise.
+ */
+BaseType_t xPortIsInsideInterrupt( void );
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+/**
+ * @brief The number of SysTick increments that make up one tick period.
+ */
+    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
+
+/**
+ * @brief The maximum number of tick periods that can be suppressed is
+ * limited by the 24 bit resolution of the SysTick timer.
+ */
+    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
+
+/**
+ * @brief Compensate for the CPU cycles that pass while the SysTick is
+ * stopped (low power functionality only).
+ */
+    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily. The time the SysTick is stopped for is
+         * accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods. -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm volatile ( "cpsid i" ::: "memory" );
+        __asm volatile ( "dsb" );
+        __asm volatile ( "isb" );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be un-suspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above the cpsid instruction()
+             * above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation
+             * contains its own wait for interrupt or wait for event
+             * instruction, and so wfi should not be executed again. However,
+             * the original expected idle time variable must remain unmodified,
+             * so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm volatile ( "dsb" ::: "memory" );
+                __asm volatile ( "wfi" );
+                __asm volatile ( "isb" );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately. See comments above
+             * the cpsid instruction above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will
+             * increase any slippage between the time maintained by the RTOS and
+             * calendar time. */
+            __asm volatile ( "cpsid i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
+             * Again, the time the SysTick is stopped for is accounted for as
+             * best it can be, but using the tickless mode will inevitably
+             * result in some tiny drift of the time maintained by the kernel
+             * with respect to calendar time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is
+             * yet to count to zero (in which case an interrupt other than the
+             * SysTick must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is
+                 * stepped forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+    }
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and reset the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    volatile uint32_t ulDummy = 0UL;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to. If a task wants to exit it
+     * should instead call vTaskDelete( NULL ). Artificially force an assert()
+     * to be triggered if configASSERT() is defined, then stop here so
+     * application writers can catch the error. */
+    configASSERT( ulCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being
+         * defined but never called.  ulDummy is used purely to quieten other
+         * warnings about code appearing after this function is called - making
+         * ulDummy volatile makes the compiler think the function could return
+         * and therefore not output an 'unreachable code' warning for code that
+         * appears after it. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __unprivileged_flash_start__;
+            extern uint32_t * __unprivileged_flash_end__;
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else /* if defined( __ARMCC_VERSION ) */
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __unprivileged_flash_start__[];
+            extern uint32_t __unprivileged_flash_end__[];
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Check that the MPU is present. */
+        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+        {
+            /* MAIR0 - Index 0. */
+            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+            /* MAIR0 - Index 1. */
+            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+            /* Setup privileged flash as Read Only so that privileged tasks can
+             * read it but not modify. */
+            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged flash as Read Only by both privileged and
+             * unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged syscalls flash as Read Only by both privileged
+             * and unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup RAM containing kernel data for privileged access only. */
+            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                               ( portMPU_REGION_EXECUTE_NEVER );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Enable mem fault. */
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
+
+            /* Enable MPU with privileged background access i.e. unmapped
+             * regions have privileged access. */
+            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_FPU == 1 )
+    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                /* Enable non-secure access to the FPU. */
+                SecureInit_EnableNSFPUAccess();
+            }
+        #endif /* configENABLE_TRUSTZONE */
+
+        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+         * unprivileged code should be able to access FPU. CP11 should be
+         * programmed to the same value as CP10. */
+        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+                            );
+
+        /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+         * context on exception entry and restore on exception return.
+         * LSPEN = 1 ==> Enable lazy context save of FP state. */
+        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+    }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Set a PendSV to request a context switch. */
+    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    portDISABLE_INTERRUPTS();
+    ulCriticalNesting++;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    configASSERT( ulCriticalNesting );
+    ulCriticalNesting--;
+
+    if( ulCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+    uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+    #if ( configENABLE_MPU == 1 )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+    #endif /* configENABLE_MPU */
+
+    uint32_t ulPC;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        uint32_t ulR0;
+        #if ( configENABLE_MPU == 1 )
+            uint32_t ulControl, ulIsTaskPrivileged;
+        #endif /* configENABLE_MPU */
+    #endif /* configENABLE_TRUSTZONE */
+    uint8_t ucSVCNumber;
+
+    /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+     * R12, LR, PC, xPSR. */
+    ulPC = pulCallerStackAddress[ 6 ];
+    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            case portSVC_ALLOCATE_SECURE_CONTEXT:
+
+                /* R0 contains the stack size passed as parameter to the
+                 * vPortAllocateSecureContext function. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                #if ( configENABLE_MPU == 1 )
+                    {
+                        /* Read the CONTROL register value. */
+                        __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+                        /* The task that raised the SVC is privileged if Bit[0]
+                         * in the CONTROL register is 0. */
+                        ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+                    }
+                #else /* if ( configENABLE_MPU == 1 ) */
+                    {
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0 );
+                    }
+                #endif /* configENABLE_MPU */
+
+                configASSERT( xSecureContext != NULL );
+                SecureContext_LoadContext( xSecureContext );
+                break;
+
+            case portSVC_FREE_SECURE_CONTEXT:
+                /* R0 contains the secure context handle to be freed. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                /* Free the secure context. */
+                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+                break;
+        #endif /* configENABLE_TRUSTZONE */
+
+        case portSVC_START_SCHEDULER:
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    /* De-prioritize the non-secure exceptions so that the
+                     * non-secure pendSV runs at the lowest priority. */
+                    SecureInit_DePrioritizeNSExceptions();
+
+                    /* Initialize the secure context management system. */
+                    SecureContext_Init();
+                }
+            #endif /* configENABLE_TRUSTZONE */
+
+            #if ( configENABLE_FPU == 1 )
+                {
+                    /* Setup the Floating Point Unit (FPU). */
+                    prvSetupFPU();
+                }
+            #endif /* configENABLE_FPU */
+
+            /* Setup the context of the first task so that the first task starts
+             * executing. */
+            vRestoreContextOfFirstTask();
+            break;
+
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_RAISE_PRIVILEGE:
+
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* configENABLE_MPU */
+
+        default:
+            /* Incorrect SVC call. */
+            configASSERT( pdFALSE );
+    }
+}
+/*-----------------------------------------------------------*/
+/* *INDENT-OFF* */
+#if ( configENABLE_MPU == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+/* *INDENT-ON* */
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    #if ( portPRELOAD_REGISTERS == 0 )
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #else /* portPRELOAD_REGISTERS */
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #endif /* portPRELOAD_REGISTERS */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    #if ( configENABLE_MPU == 1 )
+        {
+            /* Setup the Memory Protection Unit (MPU). */
+            prvSetupMPU();
+        }
+    #endif /* configENABLE_MPU */
+
+    /* Start the timer that generates the tick ISR. Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialize the critical nesting count ready for the first task. */
+    ulCriticalNesting = 0;
+
+    /* Start the first task. */
+    vStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing. Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. Call
+     * vTaskSwitchContext() so link time optimization does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here. */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    uint32_t ulStackDepth )
+    {
+        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+        int32_t lIndex = 0;
+
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Setup MAIR0. */
+        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid.  At all other
+         * times the stack parameters will not be valid and it is assumed that
+         * the stack region has already been configured. */
+        if( ulStackDepth > 0 )
+        {
+            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+
+            /* If the stack is within the privileged SRAM, do not protect it
+             * using a separate MPU region. This is needed because privileged
+             * SRAM is already protected using an MPU region and ARMv8-M does
+             * not allow overlapping MPU regions. */
+            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
+            {
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
+            }
+            else
+            {
+                /* Define the region that allows access to the stack. */
+                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+                                                             ( portMPU_REGION_NON_SHAREABLE ) |
+                                                             ( portMPU_REGION_READ_WRITE ) |
+                                                             ( portMPU_REGION_EXECUTE_NEVER );
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                                             ( portMPU_RLAR_REGION_ENABLE );
+            }
+        }
+
+        /* User supplied configurable regions. */
+        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+        {
+            /* If xRegions is NULL i.e. the task has not specified any MPU
+             * region, the else part ensures that all the configurable MPU
+             * regions are invalidated. */
+            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+            {
+                /* Translate the generic region definition contained in xRegions
+                 * into the ARMv8 specific MPU settings that are then stored in
+                 * xMPUSettings. */
+                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                /* Start address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+                                                                          ( portMPU_REGION_NON_SHAREABLE );
+
+                /* RO/RW. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+                }
+                else
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+                }
+
+                /* XN. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+                }
+
+                /* End Address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+                                                                          ( portMPU_RLAR_REGION_ENABLE );
+
+                /* Normal memory/ Device memory. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+                {
+                    /* Attr1 in MAIR0 is configured as device memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+                }
+                else
+                {
+                    /* Attr1 in MAIR0 is configured as normal memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+                }
+            }
+            else
+            {
+                /* Invalidate the region. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+            }
+
+            lIndex++;
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. Interrupt Program
+     * Status Register (IPSR) holds the exception number of the currently-executing
+     * exception or zero for Thread mode.*/
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
new file mode 100644
index 0000000..b01f171
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
new file mode 100644
index 0000000..8003b45
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
@@ -0,0 +1,377 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN xSecureContext
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+	EXTERN SecureContext_SaveContext
+	EXTERN SecureContext_LoadContext
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vPortAllocateSecureContext
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMask
+	PUBLIC vClearInterruptMask
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+	PUBLIC vPortFreeSecureContext
+
+#if ( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	tst r0, r1								/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+	beq running_privileged					/* If the result of previous AND operation was 0, branch. */
+	movs r0, #0								/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+	running_privileged:
+		movs r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+		bx lr								/* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	orrs r0, r1								/* r0 = r0 | r1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vPortAllocateSecureContext:
+	svc 0									/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r3, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r3]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	movs r5, #1								/* r5 = 1. */
+	bics r4, r5								/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	ldr  r4, [r3]							/* r4 = *r3 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	movs r5, #4								/* r5 = 4. */
+	str  r5, [r2]							/* Program RNR = 4. */
+	ldmia r3!, {r6,r7}						/* Read first set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write first set of RBAR/RLAR registers. */
+	movs r5, #5								/* r5 = 5. */
+	str  r5, [r2]							/* Program RNR = 5. */
+	ldmia r3!, {r6,r7}						/* Read second set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write second set of RBAR/RLAR registers. */
+	movs r5, #6								/* r5 = 6. */
+	str  r5, [r2]							/* Program RNR = 6. */
+	ldmia r3!, {r6,r7}						/* Read third set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write third set of RBAR/RLAR registers. */
+	movs r5, #7								/* r5 = 7. */
+	str  r5, [r2]							/* Program RNR = 7. */
+	ldmia r3!, {r6,r7}						/* Read fourth set of RBAR/RLAR from TCB. */
+	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
+	stmia r4!, {r6,r7}						/* Write fourth set of RBAR/RLAR registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	movs r5, #1								/* r5 = 1. */
+	orrs r4, r5								/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r4}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+	ldr  r5, =xSecureContext
+	str  r1, [r5]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	msr  control, r3						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r4									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+	ldr  r4, =xSecureContext
+	str  r1, [r4]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs r0, control							/* Read the CONTROL register. */
+	movs r1, #1								/* r1 = 1. */
+	bics r0, r1								/* Clear the bit 0. */
+	msr control, r0							/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMask:
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMask:
+	msr PRIMASK, r0
+	bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r1, psp								/* Read PSP in r1. */
+	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+
+	cbz r0, save_ns_context					/* No secure context to save. */
+	push {r0-r2, r14}
+	bl SecureContext_SaveContext
+	pop {r0-r3}								/* LR is now in r3. */
+	mov lr, r3								/* LR = r3. */
+	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r2, [r3]							/* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mrs r3, control							/* r3 = CONTROL. */
+	mov r4, lr								/* r4 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+#else /* configENABLE_MPU */
+	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
+#endif /* configENABLE_MPU */
+	b select_next_task
+
+	save_ns_context:
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r2, [r3]						/* Read pxCurrentTCB. */
+	#if ( configENABLE_MPU == 1 )
+		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		adds r1, r1, #16					/* r1 = r1 + 16. */
+		stmia r1!, {r4-r7}					/* Store the low registers that are not saved automatically. */
+		mov r4, r8							/* r4 = r8. */
+		mov r5, r9							/* r5 = r9. */
+		mov r6, r10							/* r6 = r10. */
+		mov r7, r11							/* r7 = r11. */
+		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mrs r3, control						/* r3 = CONTROL. */
+		mov r4, lr							/* r4 = LR/EXC_RETURN. */
+		subs r1, r1, #48					/* r1 = r1 - 48. */
+		stmia r1!, {r0, r2-r4}				/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mov r3, lr							/* r3 = LR/EXC_RETURN. */
+		stmia r1!, {r0, r2-r7}				/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
+		mov r4, r8							/* r4 = r8. */
+		mov r5, r9							/* r5 = r9. */
+		mov r6, r10							/* r6 = r10. */
+		mov r7, r11							/* r7 = r11. */
+		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
+	#endif /* configENABLE_MPU */
+
+	select_next_task:
+		cpsid i
+		bl vTaskSwitchContext
+		cpsie i
+
+		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r3, [r2]						/* Read pxCurrentTCB. */
+		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+
+	#if ( configENABLE_MPU == 1 )
+		dmb									/* Complete outstanding transfers before disabling MPU. */
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		movs r5, #1							/* r5 = 1. */
+		bics r4, r5							/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
+		str r4, [r2]						/* Disable MPU. */
+
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
+		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+		str r4, [r2]						/* Program MAIR0. */
+		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+		movs r5, #4							/* r5 = 4. */
+		str  r5, [r2]						/* Program RNR = 4. */
+		ldmia r3!, {r6,r7}					/* Read first set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write first set of RBAR/RLAR registers. */
+		movs r5, #5							/* r5 = 5. */
+		str  r5, [r2]						/* Program RNR = 5. */
+		ldmia r3!, {r6,r7}					/* Read second set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write second set of RBAR/RLAR registers. */
+		movs r5, #6							/* r5 = 6. */
+		str  r5, [r2]						/* Program RNR = 6. */
+		ldmia r3!, {r6,r7}					/* Read third set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write third set of RBAR/RLAR registers. */
+		movs r5, #7							/* r5 = 7. */
+		str  r5, [r2]						/* Program RNR = 7. */
+		ldmia r3!, {r6,r7}					/* Read fourth set of RBAR/RLAR from TCB. */
+		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
+		stmia r4!, {r6,r7}					/* Write fourth set of RBAR/RLAR registers. */
+
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		movs r5, #1							/* r5 = 1. */
+		orrs r4, r5							/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
+		str r4, [r2]						/* Enable MPU. */
+		dsb									/* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+
+	#if ( configENABLE_MPU == 1 )
+		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		msr control, r3						/* Restore the CONTROL register value for the task. */
+		mov lr, r4							/* LR = r4. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r4}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r4}
+		mov lr, r4							/* LR = r4. */
+		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#else /* configENABLE_MPU */
+		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		mov lr, r3							/* LR = r3. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r3}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r3}
+		mov lr, r3							/* LR = r3. */
+		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#endif /* configENABLE_MPU */
+
+	restore_ns_context:
+		adds r1, r1, #16					/* Move to the high registers. */
+		ldmia r1!, {r4-r7}					/* Restore the high registers that are not automatically restored. */
+		mov r8, r4							/* r8 = r4. */
+		mov r9, r5							/* r9 = r5. */
+		mov r10, r6							/* r10 = r6. */
+		mov r11, r7							/* r11 = r7. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		subs r1, r1, #32					/* Go back to the low registers. */
+		ldmia r1!, {r4-r7}					/* Restore the low registers that are not automatically restored. */
+		bx lr
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	movs r0, #4
+	mov r1, lr
+	tst r0, r1
+	beq stacking_used_msp
+	mrs r0, psp
+	b vPortSVCHandler_C
+	stacking_used_msp:
+		mrs r0, msp
+		b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+vPortFreeSecureContext:
+	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
+	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
+	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
+	beq free_secure_context
+	bx lr									/* There is no secure context (xSecureContext is NULL). */
+	free_secure_context:
+		svc 1								/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+		bx lr								/* Return. */
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
new file mode 100644
index 0000000..b36dc1f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
@@ -0,0 +1,319 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+    #ifndef configENABLE_FPU
+        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+    #endif /* configENABLE_FPU */
+
+    #ifndef configENABLE_MPU
+        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+    #endif /* configENABLE_MPU */
+
+    #ifndef configENABLE_TRUSTZONE
+        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+    #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+    #define portARCH_NAME                      "Cortex-M23"
+    #define portSTACK_GROWTH                   ( -1 )
+    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT                 8
+    #define portNOP()
+    #define portINLINE                         __inline
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+    #endif
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
+    #define portDONT_DISCARD                   __root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+    extern BaseType_t xPortIsInsideInterrupt( void );
+
+    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+    #endif /* configENABLE_TRUSTZONE */
+
+    #if ( configENABLE_MPU == 1 )
+        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+    #if ( configENABLE_MPU == 1 )
+        #define portUSING_MPU_WRAPPERS    1
+        #define portPRIVILEGE_BIT         ( 0x80000000UL )
+    #else
+        #define portPRIVILEGE_BIT         ( 0x0UL )
+    #endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
+    #define portSTACK_REGION                              ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
+    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
+    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
+    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
+    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
+    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+    } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
+    #define portSVC_FREE_SECURE_CONTEXT        1
+    #define portSVC_START_SCHEDULER            2
+    #define portSVC_RAISE_PRIVILEGE            3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+    #define portYIELD()                                 vPortYield()
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+    #define portDISABLE_INTERRUPTS()                  __asm volatile ( " cpsid i " ::: "memory" )
+    #define portENABLE_INTERRUPTS()                   __asm volatile ( " cpsie i " ::: "memory" )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+    #else
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+        #define portCLEAN_UP_TCB( pxTCB )
+    #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+        #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+        #define portRESET_PRIVILEGE()    vResetPrivilege()
+    #else
+        #define portIS_PRIVILEGED()
+        #define portRAISE_PRIVILEGE()
+        #define portRESET_PRIVILEGE()
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+    #pragma diag_suppress=Be006
+    #pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.c
new file mode 100644
index 0000000..046bf4e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.c
@@ -0,0 +1,206 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED      0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED    0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
+    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */
+    uint8_t * pucStackStart;          /**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* No stack for thread mode until a task's context is loaded. */
+        secureportSET_PSPLIM( securecontextNO_STACK );
+        secureportSET_PSP( securecontextNO_STACK );
+
+        #if ( configENABLE_MPU == 1 )
+            {
+                /* Configure thread mode to use PSP and to be unprivileged. */
+                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+            }
+        #else /* configENABLE_MPU */
+            {
+                /* Configure thread mode to use PSP and to be privileged.. */
+                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+            }
+        #endif /* configENABLE_MPU */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+                                                                                       uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+    uint8_t * pucStackMemory = NULL;
+    uint32_t ulIPSR;
+    SecureContextHandle_t xSecureContextHandle = NULL;
+
+    #if ( configENABLE_MPU == 1 )
+        uint32_t * pulCurrentStackPointer = NULL;
+    #endif /* configENABLE_MPU */
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* Allocate the context structure. */
+        xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+        if( xSecureContextHandle != NULL )
+        {
+            /* Allocate the stack space. */
+            pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+            if( pucStackMemory != NULL )
+            {
+                /* Since stack grows down, the starting point will be the last
+                 * location. Note that this location is next to the last
+                 * allocated byte because the hardware decrements the stack
+                 * pointer before writing i.e. if stack pointer is 0x2, a push
+                 * operation will decrement the stack pointer to 0x1 and then
+                 * write at 0x1. */
+                xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+                /* The stack cannot go beyond this location. This value is
+                 * programmed in the PSPLIM register on context switch.*/
+                xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+                #if ( configENABLE_MPU == 1 )
+                    {
+                        /* Store the correct CONTROL value for the task on the stack.
+                         * This value is programmed in the CONTROL register on
+                         * context switch. */
+                        pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+                        pulCurrentStackPointer--;
+
+                        if( ulIsTaskPrivileged )
+                        {
+                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+                        }
+                        else
+                        {
+                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                        }
+
+                        /* Store the current stack pointer. This value is programmed in
+                         * the PSP register on context switch. */
+                        xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                    }
+                #else /* configENABLE_MPU */
+                    {
+                        /* Current SP is set to the starting of the stack. This
+                         * value programmed in the PSP register on context switch. */
+                        xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+                    }
+                #endif /* configENABLE_MPU */
+            }
+            else
+            {
+                /* Free the context to avoid memory leak and make sure to return
+                 * NULL to indicate failure. */
+                vPortFree( xSecureContextHandle );
+                xSecureContextHandle = NULL;
+            }
+        }
+    }
+
+    return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* Ensure that valid parameters are passed. */
+        secureportASSERT( xSecureContextHandle != NULL );
+
+        /* Free the stack space. */
+        vPortFree( xSecureContextHandle->pucStackLimit );
+
+        /* Free the context itself. */
+        vPortFree( xSecureContextHandle );
+    }
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.h
new file mode 100644
index 0000000..532a407
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.h
@@ -0,0 +1,112 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK    0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext * SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if ( configENABLE_MPU == 1 )
+    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+                                                         uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c
new file mode 100644
index 0000000..455b90c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c
@@ -0,0 +1,48 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/* Functions implemented in assembler file. */
+extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
+extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+    SecureContext_LoadContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+    SecureContext_SaveContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
new file mode 100644
index 0000000..1f793f2
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
@@ -0,0 +1,76 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+
+	PUBLIC SecureContext_LoadContextAsm
+	PUBLIC SecureContext_SaveContextAsm
+
+#if ( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+SecureContext_LoadContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+#if ( configENABLE_MPU == 1 )
+	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
+	msr control, r3							/* CONTROL = r3. */
+#endif /* configENABLE_MPU */
+	msr psplim, r2							/* PSPLIM = r2. */
+	msr psp, r1								/* PSP = r1. */
+
+	load_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+SecureContext_SaveContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	mrs r1, psp								/* r1 = PSP. */
+#if ( configENABLE_MPU == 1 )
+	mrs r2, control							/* r2 = CONTROL. */
+	subs r1, r1, #4							/* Make space for the CONTROL value on the stack. */
+	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	stmia r1!, {r2}							/* Store CONTROL value on the stack. */
+#else /* configENABLE_MPU */
+	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+#endif /* configENABLE_MPU */
+	movs r1, #0								/* r1 = securecontextNO_STACK. */
+	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
+	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+
+	save_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
new file mode 100644
index 0000000..82dbd9e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
@@ -0,0 +1,454 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+    #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+    #define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+    #define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
+
+/* The application writer has already defined the array used for the RTOS
+* heap - probably so it can be placed in a special segment or address. */
+    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
+    size_t xBlockSize;                     /**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, * pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+    BlockLink_t * pxFirstFreeBlock;
+    uint8_t * pucAlignedHeap;
+    size_t uxAddress;
+    size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+    /* Ensure the heap starts on a correctly aligned boundary. */
+    uxAddress = ( size_t ) ucHeap;
+
+    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+    {
+        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+    }
+
+    pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+    /* xStart is used to hold a pointer to the first item in the list of free
+     * blocks.  The void cast is used to prevent compiler warnings. */
+    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+    xStart.xBlockSize = ( size_t ) 0;
+
+    /* pxEnd is used to mark the end of the list of free blocks and is inserted
+     * at the end of the heap space. */
+    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+    uxAddress -= xHeapStructSize;
+    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+    pxEnd = ( void * ) uxAddress;
+    pxEnd->xBlockSize = 0;
+    pxEnd->pxNextFreeBlock = NULL;
+
+    /* To start with there is a single free block that is sized to take up the
+     * entire heap space, minus the space taken by pxEnd. */
+    pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+    /* Only one block exists - and it covers the entire usable heap space. */
+    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+    /* Work out the position of the top bit in a size_t variable. */
+    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
+{
+    BlockLink_t * pxIterator;
+    uint8_t * puc;
+
+    /* Iterate through the list until a block is found that has a higher address
+     * than the block being inserted. */
+    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+    {
+        /* Nothing to do here, just iterate to the right position. */
+    }
+
+    /* Do the block being inserted, and the block it is being inserted after
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxIterator;
+
+    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+    {
+        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+        pxBlockToInsert = pxIterator;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Do the block being inserted, and the block it is being inserted before
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxBlockToInsert;
+
+    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+    {
+        if( pxIterator->pxNextFreeBlock != pxEnd )
+        {
+            /* Form one big block from the two blocks. */
+            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+        }
+        else
+        {
+            pxBlockToInsert->pxNextFreeBlock = pxEnd;
+        }
+    }
+    else
+    {
+        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+    }
+
+    /* If the block being inserted plugged a gab, so was merged with the block
+     * before and the block after, then it's pxNextFreeBlock pointer will have
+     * already been set, and should not be set here as that would make it point
+     * to itself. */
+    if( pxIterator != pxBlockToInsert )
+    {
+        pxIterator->pxNextFreeBlock = pxBlockToInsert;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void * pvPortMalloc( size_t xWantedSize )
+{
+    BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
+    void * pvReturn = NULL;
+
+    /* If this is the first call to malloc then the heap will require
+     * initialisation to setup the list of free blocks. */
+    if( pxEnd == NULL )
+    {
+        prvHeapInit();
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    {
+        /* The wanted size is increased so it can contain a BlockLink_t
+         * structure in addition to the requested amount of bytes. */
+        if( xWantedSize > 0 )
+        {
+            xWantedSize += xHeapStructSize;
+
+            /* Ensure that blocks are always aligned to the required number of
+             * bytes. */
+            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+            {
+                /* Byte alignment required. */
+                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+        {
+            /* Traverse the list from the start (lowest address) block until
+             * one of adequate size is found. */
+            pxPreviousBlock = &xStart;
+            pxBlock = xStart.pxNextFreeBlock;
+
+            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+            {
+                pxPreviousBlock = pxBlock;
+                pxBlock = pxBlock->pxNextFreeBlock;
+            }
+
+            /* If the end marker was reached then a block of adequate size was
+             * not found. */
+            if( pxBlock != pxEnd )
+            {
+                /* Return the memory space pointed to - jumping over the
+                 * BlockLink_t structure at its start. */
+                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+                /* This block is being returned for use so must be taken out
+                 * of the list of free blocks. */
+                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+                /* If the block is larger than required it can be split into
+                 * two. */
+                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+                {
+                    /* This block is to be split into two.  Create a new
+                     * block following the number of bytes requested. The void
+                     * cast is used to prevent byte alignment warnings from the
+                     * compiler. */
+                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+                    /* Calculate the sizes of two blocks split from the single
+                     * block. */
+                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+                    pxBlock->xBlockSize = xWantedSize;
+
+                    /* Insert the new block into the list of free blocks. */
+                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+                {
+                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                /* The block is being returned - it is allocated and owned by
+                 * the application and has no "next" block. */
+                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                pxBlock->pxNextFreeBlock = NULL;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    traceMALLOC( pvReturn, xWantedSize );
+
+    #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+        {
+            if( pvReturn == NULL )
+            {
+                extern void vApplicationMallocFailedHook( void );
+                vApplicationMallocFailedHook();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
+
+    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+    return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void * pv )
+{
+    uint8_t * puc = ( uint8_t * ) pv;
+    BlockLink_t * pxLink;
+
+    if( pv != NULL )
+    {
+        /* The memory being freed will have an BlockLink_t structure immediately
+         * before it. */
+        puc -= xHeapStructSize;
+
+        /* This casting is to keep the compiler from issuing warnings. */
+        pxLink = ( void * ) puc;
+
+        /* Check the block is actually allocated. */
+        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        {
+            if( pxLink->pxNextFreeBlock == NULL )
+            {
+                /* The block is being returned to the heap - it is no longer
+                 * allocated. */
+                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+                secureportDISABLE_NON_SECURE_INTERRUPTS();
+                {
+                    /* Add this block to the list of free blocks. */
+                    xFreeBytesRemaining += pxLink->xBlockSize;
+                    traceFREE( pv, pxLink->xBlockSize );
+                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+                }
+                secureportENABLE_NON_SECURE_INTERRUPTS();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+    return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+    return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+    /* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
new file mode 100644
index 0000000..fa78046
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void * pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void * pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.c
new file mode 100644
index 0000000..4e6018d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS          ( 29UL )
+#define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS              ( 26UL )
+#define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS            ( 10UL )
+#define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS            ( 11UL )
+#define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+                                   ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+                                   ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
+    }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+         * permitted. CP11 should be programmed to the same value as CP10. */
+        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+         * that we can enable/disable lazy stacking in port.c file. */
+        *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
+
+        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+         * registers (S16-S31) are also pushed to stack on exception entry and
+         * restored on exception return. */
+        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+    }
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.h
new file mode 100644
index 0000000..39deb36
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
new file mode 100644
index 0000000..7b8dbed
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT         8
+#define secureportBYTE_ALIGNMENT_MASK    ( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+    #define secureportNON_SECURE_CALLABLE    __cmse_nonsecure_entry __root
+#else
+    #define secureportNON_SECURE_CALLABLE    __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+    __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+    __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+    __asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+    __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+    __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+    __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+    __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+    __asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL     0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS()     secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x )                      \
+    if( ( x ) == 0 )                               \
+    {                                              \
+        secureportDISABLE_SECURE_INTERRUPTS();     \
+        secureportDISABLE_NON_SECURE_INTERRUPTS(); \
+        for( ; ; ) {; }                            \
+    }
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
new file mode 100644
index 0000000..852a11c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
@@ -0,0 +1,1192 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if ( configENABLE_TRUSTZONE == 1 )
+    /* Secure components includes. */
+    #include "secure_context.h"
+    #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
+#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ            configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT          ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the
+ * same a the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE    ( 3UL )
+#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS      ( 20UL )
+#define portCPACR_CP11_POS      ( 22UL )
+
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS     ( 31UL )
+#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS     ( 30UL )
+#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS                ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS                ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS                ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS                ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS                ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS                ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS                ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS                ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE           ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The maximum 24-bit number.
+ *
+ * It is needed because the systick is a 24-bit counter.
+ */
+#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )
+
+/**
+ * @brief A fiddle factor to estimate the number of SysTick counts that would
+ * have occurred while the SysTick counter is stopped during tickless idle
+ * calculations.
+ */
+#define portMISSED_COUNTS_FACTOR    ( 45UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR    ( 0x01000000 )
+
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         FD
+ * 1111 1111  1111 1111  1111 1111  1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
+#else
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         BC
+ * 1111 1111  1111 1111  1111 1111  1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS    1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT    0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+
+/**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ *
+ * The implementation in this file is weak to allow application writers to
+ * change the timer used to generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether the current execution context is interrupt.
+ *
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE
+ * otherwise.
+ */
+BaseType_t xPortIsInsideInterrupt( void );
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+/**
+ * @brief The number of SysTick increments that make up one tick period.
+ */
+    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
+
+/**
+ * @brief The maximum number of tick periods that can be suppressed is
+ * limited by the 24 bit resolution of the SysTick timer.
+ */
+    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
+
+/**
+ * @brief Compensate for the CPU cycles that pass while the SysTick is
+ * stopped (low power functionality only).
+ */
+    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily. The time the SysTick is stopped for is
+         * accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods. -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm volatile ( "cpsid i" ::: "memory" );
+        __asm volatile ( "dsb" );
+        __asm volatile ( "isb" );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be un-suspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above the cpsid instruction()
+             * above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation
+             * contains its own wait for interrupt or wait for event
+             * instruction, and so wfi should not be executed again. However,
+             * the original expected idle time variable must remain unmodified,
+             * so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm volatile ( "dsb" ::: "memory" );
+                __asm volatile ( "wfi" );
+                __asm volatile ( "isb" );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately. See comments above
+             * the cpsid instruction above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will
+             * increase any slippage between the time maintained by the RTOS and
+             * calendar time. */
+            __asm volatile ( "cpsid i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
+             * Again, the time the SysTick is stopped for is accounted for as
+             * best it can be, but using the tickless mode will inevitably
+             * result in some tiny drift of the time maintained by the kernel
+             * with respect to calendar time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is
+             * yet to count to zero (in which case an interrupt other than the
+             * SysTick must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is
+                 * stepped forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+    }
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and reset the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    volatile uint32_t ulDummy = 0UL;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to. If a task wants to exit it
+     * should instead call vTaskDelete( NULL ). Artificially force an assert()
+     * to be triggered if configASSERT() is defined, then stop here so
+     * application writers can catch the error. */
+    configASSERT( ulCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being
+         * defined but never called.  ulDummy is used purely to quieten other
+         * warnings about code appearing after this function is called - making
+         * ulDummy volatile makes the compiler think the function could return
+         * and therefore not output an 'unreachable code' warning for code that
+         * appears after it. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __unprivileged_flash_start__;
+            extern uint32_t * __unprivileged_flash_end__;
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else /* if defined( __ARMCC_VERSION ) */
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __unprivileged_flash_start__[];
+            extern uint32_t __unprivileged_flash_end__[];
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Check that the MPU is present. */
+        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+        {
+            /* MAIR0 - Index 0. */
+            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+            /* MAIR0 - Index 1. */
+            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+            /* Setup privileged flash as Read Only so that privileged tasks can
+             * read it but not modify. */
+            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged flash as Read Only by both privileged and
+             * unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged syscalls flash as Read Only by both privileged
+             * and unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup RAM containing kernel data for privileged access only. */
+            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                               ( portMPU_REGION_EXECUTE_NEVER );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Enable mem fault. */
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
+
+            /* Enable MPU with privileged background access i.e. unmapped
+             * regions have privileged access. */
+            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_FPU == 1 )
+    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                /* Enable non-secure access to the FPU. */
+                SecureInit_EnableNSFPUAccess();
+            }
+        #endif /* configENABLE_TRUSTZONE */
+
+        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+         * unprivileged code should be able to access FPU. CP11 should be
+         * programmed to the same value as CP10. */
+        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+                            );
+
+        /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+         * context on exception entry and restore on exception return.
+         * LSPEN = 1 ==> Enable lazy context save of FP state. */
+        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+    }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Set a PendSV to request a context switch. */
+    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    portDISABLE_INTERRUPTS();
+    ulCriticalNesting++;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    configASSERT( ulCriticalNesting );
+    ulCriticalNesting--;
+
+    if( ulCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+    uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+    #if ( configENABLE_MPU == 1 )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+    #endif /* configENABLE_MPU */
+
+    uint32_t ulPC;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        uint32_t ulR0;
+        #if ( configENABLE_MPU == 1 )
+            uint32_t ulControl, ulIsTaskPrivileged;
+        #endif /* configENABLE_MPU */
+    #endif /* configENABLE_TRUSTZONE */
+    uint8_t ucSVCNumber;
+
+    /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+     * R12, LR, PC, xPSR. */
+    ulPC = pulCallerStackAddress[ 6 ];
+    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            case portSVC_ALLOCATE_SECURE_CONTEXT:
+
+                /* R0 contains the stack size passed as parameter to the
+                 * vPortAllocateSecureContext function. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                #if ( configENABLE_MPU == 1 )
+                    {
+                        /* Read the CONTROL register value. */
+                        __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+                        /* The task that raised the SVC is privileged if Bit[0]
+                         * in the CONTROL register is 0. */
+                        ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+                    }
+                #else /* if ( configENABLE_MPU == 1 ) */
+                    {
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0 );
+                    }
+                #endif /* configENABLE_MPU */
+
+                configASSERT( xSecureContext != NULL );
+                SecureContext_LoadContext( xSecureContext );
+                break;
+
+            case portSVC_FREE_SECURE_CONTEXT:
+                /* R0 contains the secure context handle to be freed. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                /* Free the secure context. */
+                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+                break;
+        #endif /* configENABLE_TRUSTZONE */
+
+        case portSVC_START_SCHEDULER:
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    /* De-prioritize the non-secure exceptions so that the
+                     * non-secure pendSV runs at the lowest priority. */
+                    SecureInit_DePrioritizeNSExceptions();
+
+                    /* Initialize the secure context management system. */
+                    SecureContext_Init();
+                }
+            #endif /* configENABLE_TRUSTZONE */
+
+            #if ( configENABLE_FPU == 1 )
+                {
+                    /* Setup the Floating Point Unit (FPU). */
+                    prvSetupFPU();
+                }
+            #endif /* configENABLE_FPU */
+
+            /* Setup the context of the first task so that the first task starts
+             * executing. */
+            vRestoreContextOfFirstTask();
+            break;
+
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_RAISE_PRIVILEGE:
+
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* configENABLE_MPU */
+
+        default:
+            /* Incorrect SVC call. */
+            configASSERT( pdFALSE );
+    }
+}
+/*-----------------------------------------------------------*/
+/* *INDENT-OFF* */
+#if ( configENABLE_MPU == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+/* *INDENT-ON* */
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    #if ( portPRELOAD_REGISTERS == 0 )
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #else /* portPRELOAD_REGISTERS */
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #endif /* portPRELOAD_REGISTERS */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    #if ( configENABLE_MPU == 1 )
+        {
+            /* Setup the Memory Protection Unit (MPU). */
+            prvSetupMPU();
+        }
+    #endif /* configENABLE_MPU */
+
+    /* Start the timer that generates the tick ISR. Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialize the critical nesting count ready for the first task. */
+    ulCriticalNesting = 0;
+
+    /* Start the first task. */
+    vStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing. Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. Call
+     * vTaskSwitchContext() so link time optimization does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here. */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    uint32_t ulStackDepth )
+    {
+        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+        int32_t lIndex = 0;
+
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Setup MAIR0. */
+        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid.  At all other
+         * times the stack parameters will not be valid and it is assumed that
+         * the stack region has already been configured. */
+        if( ulStackDepth > 0 )
+        {
+            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+
+            /* If the stack is within the privileged SRAM, do not protect it
+             * using a separate MPU region. This is needed because privileged
+             * SRAM is already protected using an MPU region and ARMv8-M does
+             * not allow overlapping MPU regions. */
+            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
+            {
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
+            }
+            else
+            {
+                /* Define the region that allows access to the stack. */
+                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+                                                             ( portMPU_REGION_NON_SHAREABLE ) |
+                                                             ( portMPU_REGION_READ_WRITE ) |
+                                                             ( portMPU_REGION_EXECUTE_NEVER );
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                                             ( portMPU_RLAR_REGION_ENABLE );
+            }
+        }
+
+        /* User supplied configurable regions. */
+        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+        {
+            /* If xRegions is NULL i.e. the task has not specified any MPU
+             * region, the else part ensures that all the configurable MPU
+             * regions are invalidated. */
+            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+            {
+                /* Translate the generic region definition contained in xRegions
+                 * into the ARMv8 specific MPU settings that are then stored in
+                 * xMPUSettings. */
+                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                /* Start address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+                                                                          ( portMPU_REGION_NON_SHAREABLE );
+
+                /* RO/RW. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+                }
+                else
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+                }
+
+                /* XN. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+                }
+
+                /* End Address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+                                                                          ( portMPU_RLAR_REGION_ENABLE );
+
+                /* Normal memory/ Device memory. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+                {
+                    /* Attr1 in MAIR0 is configured as device memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+                }
+                else
+                {
+                    /* Attr1 in MAIR0 is configured as normal memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+                }
+            }
+            else
+            {
+                /* Invalidate the region. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+            }
+
+            lIndex++;
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. Interrupt Program
+     * Status Register (IPSR) holds the exception number of the currently-executing
+     * exception or zero for Thread mode.*/
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
new file mode 100644
index 0000000..b01f171
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
new file mode 100644
index 0000000..6e911bd
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
@@ -0,0 +1,303 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMask
+	PUBLIC vClearInterruptMask
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+
+#if ( configENABLE_FPU == 1 )
+	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
+#endif
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	tst r0, r1								/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
+	beq running_privileged					/* If the result of previous AND operation was 0, branch. */
+	movs r0, #0								/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+	running_privileged:
+		movs r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+		bx lr								/* Return. */
+
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	movs r1, #1								/* r1 = 1. */
+	orrs r0, r1								/* r0 = r0 | r1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r1, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r1]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	bics r3, r4								/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+	str r3, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr  r4, [r1]							/* r4 = *r1 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	movs r4, #4								/* r4 = 4. */
+	str  r4, [r2]							/* Program RNR = 4. */
+	ldmia r1!, {r5,r6}						/* Read first set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write first set of RBAR/RLAR registers. */
+	movs r4, #5								/* r4 = 5. */
+	str  r4, [r2]							/* Program RNR = 5. */
+	ldmia r1!, {r5,r6}						/* Read second set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write second set of RBAR/RLAR registers. */
+	movs r4, #6								/* r4 = 6. */
+	str  r4, [r2]							/* Program RNR = 6. */
+	ldmia r1!, {r5,r6}						/* Read third set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write third set of RBAR/RLAR registers. */
+	movs r4, #7								/* r4 = 7. */
+	str  r4, [r2]							/* Program RNR = 7. */
+	ldmia r1!, {r5,r6}						/* Read fourth set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write fourth set of RBAR/RLAR registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	orrs r3, r4								/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+	str r3, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	msr  control, r2						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	bx   r2									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs  r0, control						/* Read the CONTROL register. */
+	movs r1, #1								/* r1 = 1. */
+	bics r0, r1								/* Clear the bit 0. */
+	msr  control, r0						/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+	nop
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMask:
+	mrs r0, PRIMASK
+	cpsid i
+	bx lr
+/*-----------------------------------------------------------*/
+
+vClearInterruptMask:
+	msr PRIMASK, r0
+	bx lr
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r0, psp								/* Read PSP in r0. */
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+	subs r0, r0, #44						/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+	str r0, [r1]							/* Save the new top of stack in TCB. */
+	mrs r1, psplim							/* r1 = PSPLIM. */
+	mrs r2, control							/* r2 = CONTROL. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r0!, {r1-r7}						/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
+	mov r4, r8								/* r4 = r8. */
+	mov r5, r9								/* r5 = r9. */
+	mov r6, r10								/* r6 = r10. */
+	mov r7, r11								/* r7 = r11. */
+	stmia r0!, {r4-r7}						/* Store the high registers that are not saved automatically. */
+#else /* configENABLE_MPU */
+	subs r0, r0, #40						/* Make space for PSPLIM, LR and the remaining registers on the stack. */
+	str r0, [r1]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r0!, {r2-r7}						/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
+	mov r4, r8								/* r4 = r8. */
+	mov r5, r9								/* r5 = r9. */
+	mov r6, r10								/* r6 = r10. */
+	mov r7, r11								/* r7 = r11. */
+	stmia r0!, {r4-r7}						/* Store the high registers that are not saved automatically. */
+#endif /* configENABLE_MPU */
+
+	cpsid i
+	bl vTaskSwitchContext
+	cpsie i
+
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+	ldr r0, [r1]							/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	bics r3, r4								/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
+	str r3, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr  r4, [r1]							/* r4 = *r1 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	movs r4, #4								/* r4 = 4. */
+	str  r4, [r2]							/* Program RNR = 4. */
+	ldmia r1!, {r5,r6}						/* Read first set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write first set of RBAR/RLAR registers. */
+	movs r4, #5								/* r4 = 5. */
+	str  r4, [r2]							/* Program RNR = 5. */
+	ldmia r1!, {r5,r6}						/* Read second set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write second set of RBAR/RLAR registers. */
+	movs r4, #6								/* r4 = 6. */
+	str  r4, [r2]							/* Program RNR = 6. */
+	ldmia r1!, {r5,r6}						/* Read third set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write third set of RBAR/RLAR registers. */
+	movs r4, #7								/* r4 = 7. */
+	str  r4, [r2]							/* Program RNR = 7. */
+	ldmia r1!, {r5,r6}						/* Read fourth set of RBAR/RLAR from TCB. */
+	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
+	stmia r3!, {r5,r6}						/* Write fourth set of RBAR/RLAR registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
+	movs r4, #1								/* r4 = 1. */
+	orrs r3, r4								/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
+	str r3, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	adds r0, r0, #28						/* Move to the high registers. */
+	ldmia r0!, {r4-r7}						/* Restore the high registers that are not automatically restored. */
+	mov r8, r4								/* r8 = r4. */
+	mov r9, r5								/* r9 = r5. */
+	mov r10, r6								/* r10 = r6. */
+	mov r11, r7								/* r11 = r7. */
+	msr psp, r0								/* Remember the new top of stack for the task. */
+	subs r0, r0, #44						/* Move to the starting of the saved context. */
+	ldmia r0!, {r1-r7}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
+	msr psplim, r1							/* Restore the PSPLIM register value for the task. */
+	msr control, r2							/* Restore the CONTROL register value for the task. */
+	bx r3
+#else /* configENABLE_MPU */
+	adds r0, r0, #24						/* Move to the high registers. */
+	ldmia r0!, {r4-r7}						/* Restore the high registers that are not automatically restored. */
+	mov r8, r4								/* r8 = r4. */
+	mov r9, r5								/* r9 = r5. */
+	mov r10, r6								/* r10 = r6. */
+	mov r11, r7								/* r11 = r7. */
+	msr psp, r0								/* Remember the new top of stack for the task. */
+	subs r0, r0, #40						/* Move to the starting of the saved context. */
+	ldmia r0!, {r2-r7}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
+	msr psplim, r2							/* Restore the PSPLIM register value for the task. */
+	bx r3
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	movs r0, #4
+	mov r1, lr
+	tst r0, r1
+	beq stacking_used_msp
+	mrs r0, psp
+	b vPortSVCHandler_C
+	stacking_used_msp:
+		mrs r0, msp
+		b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
new file mode 100644
index 0000000..315e712
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
@@ -0,0 +1,319 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+    #ifndef configENABLE_FPU
+        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+    #endif /* configENABLE_FPU */
+
+    #ifndef configENABLE_MPU
+        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+    #endif /* configENABLE_MPU */
+
+    #ifndef configENABLE_TRUSTZONE
+        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+    #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+    #define portARCH_NAME                      "Cortex-M23"
+    #define portSTACK_GROWTH                   ( -1 )
+    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT                 8
+    #define portNOP()
+    #define portINLINE                         __inline
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+    #endif
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
+    #define portDONT_DISCARD                   __root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+    extern BaseType_t xPortIsInsideInterrupt( void );
+
+    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+    #endif /* configENABLE_TRUSTZONE */
+
+    #if ( configENABLE_MPU == 1 )
+        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+    #if ( configENABLE_MPU == 1 )
+        #define portUSING_MPU_WRAPPERS    1
+        #define portPRIVILEGE_BIT         ( 0x80000000UL )
+    #else
+        #define portPRIVILEGE_BIT         ( 0x0UL )
+    #endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
+    #define portSTACK_REGION                              ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
+    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
+    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
+    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
+    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
+    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+    } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
+    #define portSVC_FREE_SECURE_CONTEXT        1
+    #define portSVC_START_SCHEDULER            2
+    #define portSVC_RAISE_PRIVILEGE            3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+    #define portYIELD()                                 vPortYield()
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+    #define portDISABLE_INTERRUPTS()                  __asm volatile ( " cpsid i " ::: "memory" )
+    #define portENABLE_INTERRUPTS()                   __asm volatile ( " cpsie i " ::: "memory" )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+    #else
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+        #define portCLEAN_UP_TCB( pxTCB )
+    #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+        #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+        #define portRESET_PRIVILEGE()    vResetPrivilege()
+    #else
+        #define portIS_PRIVILEGED()
+        #define portRAISE_PRIVILEGE()
+        #define portRESET_PRIVILEGE()
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+    #pragma diag_suppress=Be006
+    #pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM3/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM3/port.c
new file mode 100644
index 0000000..3066af4
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM3/port.c
@@ -0,0 +1,608 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM3 port.
+*----------------------------------------------------------*/
+
+/* IAR includes. */
+#include <intrinsics.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
+    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
+#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                    ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK                   ( 0xFFUL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                      ( 0x01000000 )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#define portMISSED_COUNTS_FACTOR              ( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )
+
+/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
+ * defined.  The value 255 should also ensure backward compatibility.
+ * FreeRTOS.org versions prior to V4.3.0 did not include this definition. */
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+    #define configKERNEL_INTERRUPT_PRIORITY    255
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortSysTickHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    pxTopOfStack--;                                                      /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) prvTaskExitError;                    /* LR */
+    pxTopOfStack -= 5;                                                   /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters;                        /* R0 */
+    pxTopOfStack -= 8;                                                   /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( uxCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    for( ; ; )
+    {
+    }
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+            volatile uint8_t ucMaxPriorityValue;
+
+            /* Determine the maximum priority from which ISR safe FreeRTOS API
+             * functions can be called.  ISR safe functions are those that end in
+             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+             * ensure interrupt entry is as fast and simple as possible.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+            /* Determine the number of priority bits available.  First write to all
+             * possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+            /* Use the same mask on the maximum system call priority. */
+            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+            /* Calculate the maximum acceptable priority group value for the number
+             * of bits read back. */
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+            {
+                ulMaxPRIGROUPValue--;
+                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+            }
+
+            #ifdef __NVIC_PRIO_BITS
+                {
+                    /* Check the CMSIS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+                }
+            #endif
+
+            #ifdef configPRIO_BITS
+                {
+                    /* Check the FreeRTOS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+                }
+            #endif
+
+            /* Shift the priority group value back to its position within the AIRCR
+             * register. */
+            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* conifgASSERT_DEFINED */
+
+    /* Make PendSV and SysTick the lowest priority interrupts. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Start the first task. */
+    vPortStartFirstTask();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
+    if( uxCriticalNesting == 1 )
+    {
+        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+     * executes all interrupts must be unmasked.  There is therefore no need to
+     * save and then restore the interrupt mask value as its value is already
+     * known. */
+    portDISABLE_INTERRUPTS();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* A context switch is required.  Context switching is performed in
+             * the PendSV interrupt.  Pend the PendSV interrupt. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+    __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+         * is accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods.  -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __disable_interrupt();
+        __DSB();
+        __ISB();
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above __disable_interrupt()
+             * call above. */
+            __enable_interrupt();
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again.  However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __DSB();
+                __WFI();
+                __ISB();
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately.  see comments above
+             * __disable_interrupt() call above. */
+            __enable_interrupt();
+            __DSB();
+            __ISB();
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __disable_interrupt();
+            __DSB();
+            __ISB();
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is yet
+             * to count to zero (in which case an interrupt other than the SysTick
+             * must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __enable_interrupt();
+        }
+    }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__weak void vPortSetupTimerInterrupt( void )
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and clear the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+    void vPortValidateInterruptPriority( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        uint8_t ucCurrentPriority;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that	use the FreeRTOS API must not be left at their
+             * default priority of	zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and	therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
+
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredictable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
+
+#endif /* configASSERT_DEFINED */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s
new file mode 100644
index 0000000..7c8676c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s
@@ -0,0 +1,103 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include <FreeRTOSConfig.h>
+
+	RSEG    CODE:CODE(2)
+	thumb
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+
+	PUBLIC xPortPendSVHandler
+	PUBLIC vPortSVCHandler
+	PUBLIC vPortStartFirstTask
+
+
+
+/*-----------------------------------------------------------*/
+
+xPortPendSVHandler:
+	mrs r0, psp
+	isb
+	ldr	r3, =pxCurrentTCB			/* Get the location of the current TCB. */
+	ldr	r2, [r3]
+
+	stmdb r0!, {r4-r11}				/* Save the remaining registers. */
+	str r0, [r2]					/* Save the new top of stack into the first member of the TCB. */
+
+	stmdb sp!, {r3, r14}
+	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr basepri, r0
+	dsb
+	isb
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r3, r14}
+
+	ldr r1, [r3]
+	ldr r0, [r1]					/* The first item in pxCurrentTCB is the task top of stack. */
+	ldmia r0!, {r4-r11}				/* Pop the registers. */
+	msr psp, r0
+	isb
+	bx r14
+
+
+/*-----------------------------------------------------------*/
+
+vPortSVCHandler:
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr r1, [r3]
+	ldr r0, [r1]
+	/* Pop the core registers. */
+	ldmia r0!, {r4-r11}
+	msr psp, r0
+	isb
+	mov r0, #0
+	msr	basepri, r0
+	orr r14, r14, #13
+	bx r14
+
+/*-----------------------------------------------------------*/
+
+vPortStartFirstTask
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Call SVC to start the first task, ensuring interrupts are enabled. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	svc 0
+
+	END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h
new file mode 100644
index 0000000..1d390c0
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h
@@ -0,0 +1,207 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* IAR includes. */
+    #include <intrinsics.h>
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
+/*-----------------------------------------------------------*/
+
+/* Compiler directives. */
+    #define portWEAK_SYMBOL    __attribute__( ( weak ) )
+
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+    #define portYIELD()                                 \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        __DSB();                                        \
+        __ISB();                                        \
+    }
+
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired != pdFALSE ) portYIELD()
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #endif
+
+    #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
+
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
+
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+
+    #define portDISABLE_INTERRUPTS()                           \
+    {                                                          \
+        __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
+        __DSB();                                               \
+        __ISB();                                               \
+    }
+
+    #define portENABLE_INTERRUPTS()                   __set_BASEPRI( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         __get_BASEPRI(); portDISABLE_INTERRUPTS()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    __set_BASEPRI( x )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
+
+/* portNOP() is not required by this port. */
+    #define portNOP()
+
+    #define portINLINE              __inline
+
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
+    #endif
+
+/*-----------------------------------------------------------*/
+
+    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        BaseType_t xReturn;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+        if( ulCurrentInterrupt == 0 )
+        {
+            xReturn = pdFALSE;
+        }
+        else
+        {
+            xReturn = pdTRUE;
+        }
+
+        return xReturn;
+    }
+
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+    #pragma diag_suppress=Pe191
+    #pragma diag_suppress=Pa082
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/port.c
new file mode 100644
index 0000000..852a11c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/port.c
@@ -0,0 +1,1192 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if ( configENABLE_TRUSTZONE == 1 )
+    /* Secure components includes. */
+    #include "secure_context.h"
+    #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
+#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ            configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT          ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the
+ * same a the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE    ( 3UL )
+#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS      ( 20UL )
+#define portCPACR_CP11_POS      ( 22UL )
+
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS     ( 31UL )
+#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS     ( 30UL )
+#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS                ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS                ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS                ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS                ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS                ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS                ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS                ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS                ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE           ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The maximum 24-bit number.
+ *
+ * It is needed because the systick is a 24-bit counter.
+ */
+#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )
+
+/**
+ * @brief A fiddle factor to estimate the number of SysTick counts that would
+ * have occurred while the SysTick counter is stopped during tickless idle
+ * calculations.
+ */
+#define portMISSED_COUNTS_FACTOR    ( 45UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR    ( 0x01000000 )
+
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         FD
+ * 1111 1111  1111 1111  1111 1111  1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
+#else
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         BC
+ * 1111 1111  1111 1111  1111 1111  1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS    1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT    0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+
+/**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ *
+ * The implementation in this file is weak to allow application writers to
+ * change the timer used to generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether the current execution context is interrupt.
+ *
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE
+ * otherwise.
+ */
+BaseType_t xPortIsInsideInterrupt( void );
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+/**
+ * @brief The number of SysTick increments that make up one tick period.
+ */
+    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
+
+/**
+ * @brief The maximum number of tick periods that can be suppressed is
+ * limited by the 24 bit resolution of the SysTick timer.
+ */
+    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
+
+/**
+ * @brief Compensate for the CPU cycles that pass while the SysTick is
+ * stopped (low power functionality only).
+ */
+    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily. The time the SysTick is stopped for is
+         * accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods. -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm volatile ( "cpsid i" ::: "memory" );
+        __asm volatile ( "dsb" );
+        __asm volatile ( "isb" );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be un-suspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above the cpsid instruction()
+             * above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation
+             * contains its own wait for interrupt or wait for event
+             * instruction, and so wfi should not be executed again. However,
+             * the original expected idle time variable must remain unmodified,
+             * so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm volatile ( "dsb" ::: "memory" );
+                __asm volatile ( "wfi" );
+                __asm volatile ( "isb" );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately. See comments above
+             * the cpsid instruction above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will
+             * increase any slippage between the time maintained by the RTOS and
+             * calendar time. */
+            __asm volatile ( "cpsid i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
+             * Again, the time the SysTick is stopped for is accounted for as
+             * best it can be, but using the tickless mode will inevitably
+             * result in some tiny drift of the time maintained by the kernel
+             * with respect to calendar time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is
+             * yet to count to zero (in which case an interrupt other than the
+             * SysTick must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is
+                 * stepped forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+    }
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and reset the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    volatile uint32_t ulDummy = 0UL;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to. If a task wants to exit it
+     * should instead call vTaskDelete( NULL ). Artificially force an assert()
+     * to be triggered if configASSERT() is defined, then stop here so
+     * application writers can catch the error. */
+    configASSERT( ulCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being
+         * defined but never called.  ulDummy is used purely to quieten other
+         * warnings about code appearing after this function is called - making
+         * ulDummy volatile makes the compiler think the function could return
+         * and therefore not output an 'unreachable code' warning for code that
+         * appears after it. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __unprivileged_flash_start__;
+            extern uint32_t * __unprivileged_flash_end__;
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else /* if defined( __ARMCC_VERSION ) */
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __unprivileged_flash_start__[];
+            extern uint32_t __unprivileged_flash_end__[];
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Check that the MPU is present. */
+        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+        {
+            /* MAIR0 - Index 0. */
+            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+            /* MAIR0 - Index 1. */
+            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+            /* Setup privileged flash as Read Only so that privileged tasks can
+             * read it but not modify. */
+            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged flash as Read Only by both privileged and
+             * unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged syscalls flash as Read Only by both privileged
+             * and unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup RAM containing kernel data for privileged access only. */
+            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                               ( portMPU_REGION_EXECUTE_NEVER );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Enable mem fault. */
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
+
+            /* Enable MPU with privileged background access i.e. unmapped
+             * regions have privileged access. */
+            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_FPU == 1 )
+    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                /* Enable non-secure access to the FPU. */
+                SecureInit_EnableNSFPUAccess();
+            }
+        #endif /* configENABLE_TRUSTZONE */
+
+        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+         * unprivileged code should be able to access FPU. CP11 should be
+         * programmed to the same value as CP10. */
+        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+                            );
+
+        /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+         * context on exception entry and restore on exception return.
+         * LSPEN = 1 ==> Enable lazy context save of FP state. */
+        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+    }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Set a PendSV to request a context switch. */
+    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    portDISABLE_INTERRUPTS();
+    ulCriticalNesting++;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    configASSERT( ulCriticalNesting );
+    ulCriticalNesting--;
+
+    if( ulCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+    uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+    #if ( configENABLE_MPU == 1 )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+    #endif /* configENABLE_MPU */
+
+    uint32_t ulPC;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        uint32_t ulR0;
+        #if ( configENABLE_MPU == 1 )
+            uint32_t ulControl, ulIsTaskPrivileged;
+        #endif /* configENABLE_MPU */
+    #endif /* configENABLE_TRUSTZONE */
+    uint8_t ucSVCNumber;
+
+    /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+     * R12, LR, PC, xPSR. */
+    ulPC = pulCallerStackAddress[ 6 ];
+    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            case portSVC_ALLOCATE_SECURE_CONTEXT:
+
+                /* R0 contains the stack size passed as parameter to the
+                 * vPortAllocateSecureContext function. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                #if ( configENABLE_MPU == 1 )
+                    {
+                        /* Read the CONTROL register value. */
+                        __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+                        /* The task that raised the SVC is privileged if Bit[0]
+                         * in the CONTROL register is 0. */
+                        ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+                    }
+                #else /* if ( configENABLE_MPU == 1 ) */
+                    {
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0 );
+                    }
+                #endif /* configENABLE_MPU */
+
+                configASSERT( xSecureContext != NULL );
+                SecureContext_LoadContext( xSecureContext );
+                break;
+
+            case portSVC_FREE_SECURE_CONTEXT:
+                /* R0 contains the secure context handle to be freed. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                /* Free the secure context. */
+                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+                break;
+        #endif /* configENABLE_TRUSTZONE */
+
+        case portSVC_START_SCHEDULER:
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    /* De-prioritize the non-secure exceptions so that the
+                     * non-secure pendSV runs at the lowest priority. */
+                    SecureInit_DePrioritizeNSExceptions();
+
+                    /* Initialize the secure context management system. */
+                    SecureContext_Init();
+                }
+            #endif /* configENABLE_TRUSTZONE */
+
+            #if ( configENABLE_FPU == 1 )
+                {
+                    /* Setup the Floating Point Unit (FPU). */
+                    prvSetupFPU();
+                }
+            #endif /* configENABLE_FPU */
+
+            /* Setup the context of the first task so that the first task starts
+             * executing. */
+            vRestoreContextOfFirstTask();
+            break;
+
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_RAISE_PRIVILEGE:
+
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* configENABLE_MPU */
+
+        default:
+            /* Incorrect SVC call. */
+            configASSERT( pdFALSE );
+    }
+}
+/*-----------------------------------------------------------*/
+/* *INDENT-OFF* */
+#if ( configENABLE_MPU == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+/* *INDENT-ON* */
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    #if ( portPRELOAD_REGISTERS == 0 )
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #else /* portPRELOAD_REGISTERS */
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #endif /* portPRELOAD_REGISTERS */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    #if ( configENABLE_MPU == 1 )
+        {
+            /* Setup the Memory Protection Unit (MPU). */
+            prvSetupMPU();
+        }
+    #endif /* configENABLE_MPU */
+
+    /* Start the timer that generates the tick ISR. Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialize the critical nesting count ready for the first task. */
+    ulCriticalNesting = 0;
+
+    /* Start the first task. */
+    vStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing. Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. Call
+     * vTaskSwitchContext() so link time optimization does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here. */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    uint32_t ulStackDepth )
+    {
+        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+        int32_t lIndex = 0;
+
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Setup MAIR0. */
+        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid.  At all other
+         * times the stack parameters will not be valid and it is assumed that
+         * the stack region has already been configured. */
+        if( ulStackDepth > 0 )
+        {
+            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+
+            /* If the stack is within the privileged SRAM, do not protect it
+             * using a separate MPU region. This is needed because privileged
+             * SRAM is already protected using an MPU region and ARMv8-M does
+             * not allow overlapping MPU regions. */
+            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
+            {
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
+            }
+            else
+            {
+                /* Define the region that allows access to the stack. */
+                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+                                                             ( portMPU_REGION_NON_SHAREABLE ) |
+                                                             ( portMPU_REGION_READ_WRITE ) |
+                                                             ( portMPU_REGION_EXECUTE_NEVER );
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                                             ( portMPU_RLAR_REGION_ENABLE );
+            }
+        }
+
+        /* User supplied configurable regions. */
+        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+        {
+            /* If xRegions is NULL i.e. the task has not specified any MPU
+             * region, the else part ensures that all the configurable MPU
+             * regions are invalidated. */
+            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+            {
+                /* Translate the generic region definition contained in xRegions
+                 * into the ARMv8 specific MPU settings that are then stored in
+                 * xMPUSettings. */
+                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                /* Start address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+                                                                          ( portMPU_REGION_NON_SHAREABLE );
+
+                /* RO/RW. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+                }
+                else
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+                }
+
+                /* XN. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+                }
+
+                /* End Address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+                                                                          ( portMPU_RLAR_REGION_ENABLE );
+
+                /* Normal memory/ Device memory. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+                {
+                    /* Attr1 in MAIR0 is configured as device memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+                }
+                else
+                {
+                    /* Attr1 in MAIR0 is configured as normal memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+                }
+            }
+            else
+            {
+                /* Invalidate the region. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+            }
+
+            lIndex++;
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. Interrupt Program
+     * Status Register (IPSR) holds the exception number of the currently-executing
+     * exception or zero for Thread mode.*/
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
new file mode 100644
index 0000000..b01f171
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
new file mode 100644
index 0000000..6b125b2
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
@@ -0,0 +1,345 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+/* Including FreeRTOSConfig.h here will cause build errors if the header file
+contains code not understood by the assembler - for example the 'extern' keyword.
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
+the code is included in C files but excluded by the preprocessor in assembly
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
+#include "FreeRTOSConfig.h"
+
+	EXTERN pxCurrentTCB
+	EXTERN xSecureContext
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+	EXTERN SecureContext_SaveContext
+	EXTERN SecureContext_LoadContext
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vPortAllocateSecureContext
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMask
+	PUBLIC vClearInterruptMask
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+	PUBLIC vPortFreeSecureContext
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	ite ne
+	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	orr r0, r0, #1							/* r0 = r0 | 1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vPortAllocateSecureContext:
+	svc 0									/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r3, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r3]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+	ldr  r4, [r3]							/* r4 = *r3 i.e. r4 = MAIR0. */
+	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str  r4, [r2]							/* Program MAIR0. */
+	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+	movs r4, #4								/* r4 = 4. */
+	str  r4, [r2]							/* Program RNR = 4. */
+	adds r3, #4								/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+	ldr  r2, =0xe000ed9c					/* r2 = 0xe000ed9c [Location of RBAR]. */
+	ldmia r3!, {r4-r11}						/* Read 4 set of RBAR/RLAR registers from TCB. */
+	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r4}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
+	ldr  r5, =xSecureContext
+	str  r1, [r5]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	msr  control, r3						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	mov  r0, #0
+	msr  basepri, r0						/* Ensure that interrupts are enabled when the first task starts. */
+	bx   r4									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
+	ldr  r4, =xSecureContext
+	str  r1, [r4]							/* Set xSecureContext to this task's value for the same. */
+	msr  psplim, r2							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	mov  r0, #0
+	msr  basepri, r0						/* Ensure that interrupts are enabled when the first task starts. */
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs  r0, control						/* Read the CONTROL register. */
+	bic r0, r0, #1							/* Clear the bit 0. */
+	msr  control, r0						/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	cpsie f
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMask:
+	mrs r0, basepri							/* r0 = basepri. Return original basepri value. */
+	mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr basepri, r1							/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+	dsb
+	isb
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+vClearInterruptMask:
+	msr basepri, r0							/* basepri = ulMask. */
+	dsb
+	isb
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r1, psp								/* Read PSP in r1. */
+	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
+
+	cbz r0, save_ns_context					/* No secure context to save. */
+	push {r0-r2, r14}
+	bl SecureContext_SaveContext
+	pop {r0-r3}								/* LR is now in r3. */
+	mov lr, r3								/* LR = r3. */
+	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r2, [r3]							/* Read pxCurrentTCB. */
+#if ( configENABLE_MPU == 1 )
+	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mrs r3, control							/* r3 = CONTROL. */
+	mov r4, lr								/* r4 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+#else /* configENABLE_MPU */
+	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
+	str r1, [r2]							/* Save the new top of stack in TCB. */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
+#endif /* configENABLE_MPU */
+	b select_next_task
+
+	save_ns_context:
+		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r2, [r3]						/* Read pxCurrentTCB. */
+	#if ( configENABLE_FPU == 1 )
+		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+		it eq
+		vstmdbeq r1!, {s16-s31}				/* Store the FPU registers which are not saved automatically. */
+	#endif /* configENABLE_FPU */
+	#if ( configENABLE_MPU == 1 )
+		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		adds r1, r1, #16					/* r1 = r1 + 16. */
+		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mrs r3, control						/* r3 = CONTROL. */
+		mov r4, lr							/* r4 = LR/EXC_RETURN. */
+		subs r1, r1, #16					/* r1 = r1 - 16. */
+		stm r1, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
+	#else /* configENABLE_MPU */
+		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
+		str r1, [r2]						/* Save the new top of stack in TCB. */
+		adds r1, r1, #12					/* r1 = r1 + 12. */
+		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
+		mrs r2, psplim						/* r2 = PSPLIM. */
+		mov r3, lr							/* r3 = LR/EXC_RETURN. */
+		subs r1, r1, #12					/* r1 = r1 - 12. */
+		stmia r1!, {r0, r2-r3}				/* Store xSecureContext, PSPLIM and LR on the stack. */
+	#endif /* configENABLE_MPU */
+
+	select_next_task:
+		mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+		msr basepri, r0						/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+		dsb
+		isb
+		bl vTaskSwitchContext
+		mov r0, #0							/* r0 = 0. */
+		msr basepri, r0						/* Enable interrupts. */
+
+		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+		ldr r3, [r2]						/* Read pxCurrentTCB. */
+		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
+
+	#if ( configENABLE_MPU == 1 )
+		dmb									/* Complete outstanding transfers before disabling MPU. */
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		bic r4, r4, #1						/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+		str r4, [r2]						/* Disable MPU. */
+
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
+		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
+		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
+		str r4, [r2]						/* Program MAIR0. */
+		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
+		movs r4, #4							/* r4 = 4. */
+		str r4, [r2]						/* Program RNR = 4. */
+		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
+		ldr  r2, =0xe000ed9c				/* r2 = 0xe000ed9c [Location of RBAR]. */
+		ldmia r3!, {r4-r11}					/* Read 4 sets of RBAR/RLAR registers from TCB. */
+		stmia r2!, {r4-r11}					/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
+		orr r4, r4, #1						/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+		str r4, [r2]						/* Enable MPU. */
+		dsb									/* Force memory writes before continuing. */
+	#endif /* configENABLE_MPU */
+
+	#if ( configENABLE_MPU == 1 )
+		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		msr control, r3						/* Restore the CONTROL register value for the task. */
+		mov lr, r4							/* LR = r4. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r4}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r4}
+		mov lr, r4							/* LR = r4. */
+		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#else /* configENABLE_MPU */
+		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
+		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
+		mov lr, r3							/* LR = r3. */
+		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
+		str r0, [r2]						/* Restore the task's xSecureContext. */
+		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
+		push {r1,r3}
+		bl SecureContext_LoadContext		/* Restore the secure context. */
+		pop {r1,r3}
+		mov lr, r3							/* LR = r3. */
+		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
+		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+	#endif /* configENABLE_MPU */
+
+	restore_ns_context:
+		ldmia r1!, {r4-r11}					/* Restore the registers that are not automatically restored. */
+	#if ( configENABLE_FPU == 1 )
+		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+		it eq
+		vldmiaeq r1!, {s16-s31}				/* Restore the FPU registers which are not restored automatically. */
+	#endif /* configENABLE_FPU */
+		msr psp, r1							/* Remember the new top of stack for the task. */
+		bx lr
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	tst lr, #4
+	ite eq
+	mrseq r0, msp
+	mrsne r0, psp
+	b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+vPortFreeSecureContext:
+	/* r0 = uint32_t *pulTCB. */
+	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
+	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
+	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
+	it ne
+	svcne 1									/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
new file mode 100644
index 0000000..e3fa10a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
@@ -0,0 +1,319 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+    #ifndef configENABLE_FPU
+        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+    #endif /* configENABLE_FPU */
+
+    #ifndef configENABLE_MPU
+        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+    #endif /* configENABLE_MPU */
+
+    #ifndef configENABLE_TRUSTZONE
+        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+    #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+    #define portARCH_NAME                      "Cortex-M33"
+    #define portSTACK_GROWTH                   ( -1 )
+    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT                 8
+    #define portNOP()
+    #define portINLINE                         __inline
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+    #endif
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
+    #define portDONT_DISCARD                   __root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+    extern BaseType_t xPortIsInsideInterrupt( void );
+
+    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+    #endif /* configENABLE_TRUSTZONE */
+
+    #if ( configENABLE_MPU == 1 )
+        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+    #if ( configENABLE_MPU == 1 )
+        #define portUSING_MPU_WRAPPERS    1
+        #define portPRIVILEGE_BIT         ( 0x80000000UL )
+    #else
+        #define portPRIVILEGE_BIT         ( 0x0UL )
+    #endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
+    #define portSTACK_REGION                              ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
+    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
+    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
+    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
+    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
+    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+    } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
+    #define portSVC_FREE_SECURE_CONTEXT        1
+    #define portSVC_START_SCHEDULER            2
+    #define portSVC_RAISE_PRIVILEGE            3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+    #define portYIELD()                                 vPortYield()
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+    #define portDISABLE_INTERRUPTS()                  ulSetInterruptMask()
+    #define portENABLE_INTERRUPTS()                   vClearInterruptMask( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+    #else
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+        #define portCLEAN_UP_TCB( pxTCB )
+    #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+        #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+        #define portRESET_PRIVILEGE()    vResetPrivilege()
+    #else
+        #define portIS_PRIVILEGED()
+        #define portRAISE_PRIVILEGE()
+        #define portRESET_PRIVILEGE()
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+    #pragma diag_suppress=Be006
+    #pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.c
new file mode 100644
index 0000000..046bf4e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.c
@@ -0,0 +1,206 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief CONTROL value for privileged tasks.
+ *
+ * Bit[0] - 0 --> Thread mode is privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_PRIVILEGED      0x02
+
+/**
+ * @brief CONTROL value for un-privileged tasks.
+ *
+ * Bit[0] - 1 --> Thread mode is un-privileged.
+ * Bit[1] - 1 --> Thread mode uses PSP.
+ */
+#define securecontextCONTROL_VALUE_UNPRIVILEGED    0x03
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Structure to represent secure context.
+ *
+ * @note Since stack grows down, pucStackStart is the highest address while
+ * pucStackLimit is the first addess of the allocated memory.
+ */
+typedef struct SecureContext
+{
+    uint8_t * pucCurrentStackPointer; /**< Current value of stack pointer (PSP). */
+    uint8_t * pucStackLimit;          /**< Last location of the stack memory (PSPLIM). */
+    uint8_t * pucStackStart;          /**< First location of the stack memory. */
+} SecureContext_t;
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* No stack for thread mode until a task's context is loaded. */
+        secureportSET_PSPLIM( securecontextNO_STACK );
+        secureportSET_PSP( securecontextNO_STACK );
+
+        #if ( configENABLE_MPU == 1 )
+            {
+                /* Configure thread mode to use PSP and to be unprivileged. */
+                secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
+            }
+        #else /* configENABLE_MPU */
+            {
+                /* Configure thread mode to use PSP and to be privileged.. */
+                secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
+            }
+        #endif /* configENABLE_MPU */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+                                                                                       uint32_t ulIsTaskPrivileged )
+#else /* configENABLE_MPU */
+    secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
+#endif /* configENABLE_MPU */
+{
+    uint8_t * pucStackMemory = NULL;
+    uint32_t ulIPSR;
+    SecureContextHandle_t xSecureContextHandle = NULL;
+
+    #if ( configENABLE_MPU == 1 )
+        uint32_t * pulCurrentStackPointer = NULL;
+    #endif /* configENABLE_MPU */
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* Allocate the context structure. */
+        xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
+
+        if( xSecureContextHandle != NULL )
+        {
+            /* Allocate the stack space. */
+            pucStackMemory = pvPortMalloc( ulSecureStackSize );
+
+            if( pucStackMemory != NULL )
+            {
+                /* Since stack grows down, the starting point will be the last
+                 * location. Note that this location is next to the last
+                 * allocated byte because the hardware decrements the stack
+                 * pointer before writing i.e. if stack pointer is 0x2, a push
+                 * operation will decrement the stack pointer to 0x1 and then
+                 * write at 0x1. */
+                xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
+
+                /* The stack cannot go beyond this location. This value is
+                 * programmed in the PSPLIM register on context switch.*/
+                xSecureContextHandle->pucStackLimit = pucStackMemory;
+
+                #if ( configENABLE_MPU == 1 )
+                    {
+                        /* Store the correct CONTROL value for the task on the stack.
+                         * This value is programmed in the CONTROL register on
+                         * context switch. */
+                        pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
+                        pulCurrentStackPointer--;
+
+                        if( ulIsTaskPrivileged )
+                        {
+                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
+                        }
+                        else
+                        {
+                            *( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
+                        }
+
+                        /* Store the current stack pointer. This value is programmed in
+                         * the PSP register on context switch. */
+                        xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
+                    }
+                #else /* configENABLE_MPU */
+                    {
+                        /* Current SP is set to the starting of the stack. This
+                         * value programmed in the PSP register on context switch. */
+                        xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
+                    }
+                #endif /* configENABLE_MPU */
+            }
+            else
+            {
+                /* Free the context to avoid memory leak and make sure to return
+                 * NULL to indicate failure. */
+                vPortFree( xSecureContextHandle );
+                xSecureContextHandle = NULL;
+            }
+        }
+    }
+
+    return xSecureContextHandle;
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* Ensure that valid parameters are passed. */
+        secureportASSERT( xSecureContextHandle != NULL );
+
+        /* Free the stack space. */
+        vPortFree( xSecureContextHandle->pucStackLimit );
+
+        /* Free the context itself. */
+        vPortFree( xSecureContextHandle );
+    }
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.h
new file mode 100644
index 0000000..532a407
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.h
@@ -0,0 +1,112 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_CONTEXT_H__
+#define __SECURE_CONTEXT_H__
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+
+/**
+ * @brief PSP value when no task's context is loaded.
+ */
+#define securecontextNO_STACK    0x0
+
+/**
+ * @brief Opaque handle.
+ */
+struct SecureContext;
+typedef struct SecureContext * SecureContextHandle_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Initializes the secure context management system.
+ *
+ * PSP is set to NULL and therefore a task must allocate and load a context
+ * before calling any secure side function in the thread mode.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureContext_Init( void );
+
+/**
+ * @brief Allocates a context on the secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
+ * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
+ *
+ * @return Opaque context handle if context is successfully allocated, NULL
+ * otherwise.
+ */
+#if ( configENABLE_MPU == 1 )
+    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize,
+                                                         uint32_t ulIsTaskPrivileged );
+#else /* configENABLE_MPU */
+    SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
+#endif /* configENABLE_MPU */
+
+/**
+ * @brief Frees the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the
+ * context to be freed.
+ */
+void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Loads the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be loaded.
+ */
+void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
+
+/**
+ * @brief Saves the given context.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ *
+ * @param[in] xSecureContextHandle Context handle corresponding to the context
+ * to be saved.
+ */
+void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
+
+#endif /* __SECURE_CONTEXT_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c
new file mode 100644
index 0000000..455b90c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c
@@ -0,0 +1,48 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Secure context includes. */
+#include "secure_context.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/* Functions implemented in assembler file. */
+extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
+extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
+
+secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
+{
+    SecureContext_LoadContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
+{
+    SecureContext_SaveContextAsm( xSecureContextHandle );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
new file mode 100644
index 0000000..d2c599d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
@@ -0,0 +1,73 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+
+	PUBLIC SecureContext_LoadContextAsm
+	PUBLIC SecureContext_SaveContextAsm
+/*-----------------------------------------------------------*/
+
+SecureContext_LoadContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
+#if ( configENABLE_MPU == 1 )
+	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
+	msr control, r3							/* CONTROL = r3. */
+#endif /* configENABLE_MPU */
+	msr psplim, r2							/* PSPLIM = r2. */
+	msr psp, r1								/* PSP = r1. */
+
+	load_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+SecureContext_SaveContextAsm:
+	/* xSecureContextHandle value is in r0. */
+	mrs r1, ipsr							/* r1 = IPSR. */
+	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
+	mrs r1, psp								/* r1 = PSP. */
+#if ( configENABLE_FPU == 1 )
+	vstmdb r1!, {s0}						/* Trigger the defferred stacking of FPU registers. */
+	vldmia r1!, {s0}						/* Nullify the effect of the pervious statement. */
+#endif /* configENABLE_FPU */
+#if ( configENABLE_MPU == 1 )
+	mrs r2, control							/* r2 = CONTROL. */
+	stmdb r1!, {r2}							/* Store CONTROL value on the stack. */
+#endif /* configENABLE_MPU */
+	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
+	movs r1, #0								/* r1 = securecontextNO_STACK. */
+	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
+	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
+
+	save_ctx_therad_mode:
+		bx lr
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
new file mode 100644
index 0000000..82dbd9e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
@@ -0,0 +1,454 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure context heap includes. */
+#include "secure_heap.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Total heap size.
+ */
+#define secureconfigTOTAL_HEAP_SIZE    ( ( ( size_t ) ( 10 * 1024 ) ) )
+
+/* No test marker by default. */
+#ifndef mtCOVERAGE_TEST_MARKER
+    #define mtCOVERAGE_TEST_MARKER()
+#endif
+
+/* No tracing by default. */
+#ifndef traceMALLOC
+    #define traceMALLOC( pvReturn, xWantedSize )
+#endif
+
+/* No tracing by default. */
+#ifndef traceFREE
+    #define traceFREE( pv, xBlockSize )
+#endif
+
+/* Block sizes must not get too small. */
+#define secureheapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define secureheapBITS_PER_BYTE         ( ( size_t ) 8 )
+/*-----------------------------------------------------------*/
+
+/* Allocate the memory for the heap. */
+#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
+
+/* The application writer has already defined the array used for the RTOS
+* heap - probably so it can be placed in a special segment or address. */
+    extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#else /* configAPPLICATION_ALLOCATED_HEAP */
+    static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/**
+ * @brief The linked list structure.
+ *
+ * This is used to link free blocks in order of their memory address.
+ */
+typedef struct A_BLOCK_LINK
+{
+    struct A_BLOCK_LINK * pxNextFreeBlock; /**< The next free block in the list. */
+    size_t xBlockSize;                     /**< The size of the free block. */
+} BlockLink_t;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Called automatically to setup the required heap structures the first
+ * time pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/**
+ * @brief Inserts a block of memory that is being freed into the correct
+ * position in the list of free memory blocks.
+ *
+ * The block being freed will be merged with the block in front it and/or the
+ * block behind it if the memory blocks are adjacent to each other.
+ *
+ * @param[in] pxBlockToInsert The block being freed.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The size of the structure placed at the beginning of each allocated
+ * memory block must by correctly byte aligned.
+ */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+
+/**
+ * @brief Create a couple of list links to mark the start and end of the list.
+ */
+static BlockLink_t xStart, * pxEnd = NULL;
+
+/**
+ * @brief Keeps track of the number of free bytes remaining, but says nothing
+ * about fragmentation.
+ */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/**
+ * @brief Gets set to the top bit of an size_t type.
+ *
+ * When this bit in the xBlockSize member of an BlockLink_t structure is set
+ * then the block belongs to the application. When the bit is free the block is
+ * still part of the free heap space.
+ */
+static size_t xBlockAllocatedBit = 0;
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+    BlockLink_t * pxFirstFreeBlock;
+    uint8_t * pucAlignedHeap;
+    size_t uxAddress;
+    size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
+
+    /* Ensure the heap starts on a correctly aligned boundary. */
+    uxAddress = ( size_t ) ucHeap;
+
+    if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
+    {
+        uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
+        uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+    }
+
+    pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+    /* xStart is used to hold a pointer to the first item in the list of free
+     * blocks.  The void cast is used to prevent compiler warnings. */
+    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+    xStart.xBlockSize = ( size_t ) 0;
+
+    /* pxEnd is used to mark the end of the list of free blocks and is inserted
+     * at the end of the heap space. */
+    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+    uxAddress -= xHeapStructSize;
+    uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
+    pxEnd = ( void * ) uxAddress;
+    pxEnd->xBlockSize = 0;
+    pxEnd->pxNextFreeBlock = NULL;
+
+    /* To start with there is a single free block that is sized to take up the
+     * entire heap space, minus the space taken by pxEnd. */
+    pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+    /* Only one block exists - and it covers the entire usable heap space. */
+    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+    /* Work out the position of the top bit in a size_t variable. */
+    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
+{
+    BlockLink_t * pxIterator;
+    uint8_t * puc;
+
+    /* Iterate through the list until a block is found that has a higher address
+     * than the block being inserted. */
+    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+    {
+        /* Nothing to do here, just iterate to the right position. */
+    }
+
+    /* Do the block being inserted, and the block it is being inserted after
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxIterator;
+
+    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+    {
+        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+        pxBlockToInsert = pxIterator;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Do the block being inserted, and the block it is being inserted before
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxBlockToInsert;
+
+    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+    {
+        if( pxIterator->pxNextFreeBlock != pxEnd )
+        {
+            /* Form one big block from the two blocks. */
+            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+        }
+        else
+        {
+            pxBlockToInsert->pxNextFreeBlock = pxEnd;
+        }
+    }
+    else
+    {
+        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+    }
+
+    /* If the block being inserted plugged a gab, so was merged with the block
+     * before and the block after, then it's pxNextFreeBlock pointer will have
+     * already been set, and should not be set here as that would make it point
+     * to itself. */
+    if( pxIterator != pxBlockToInsert )
+    {
+        pxIterator->pxNextFreeBlock = pxBlockToInsert;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void * pvPortMalloc( size_t xWantedSize )
+{
+    BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
+    void * pvReturn = NULL;
+
+    /* If this is the first call to malloc then the heap will require
+     * initialisation to setup the list of free blocks. */
+    if( pxEnd == NULL )
+    {
+        prvHeapInit();
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Check the requested block size is not so large that the top bit is set.
+     * The top bit of the block size member of the BlockLink_t structure is used
+     * to determine who owns the block - the application or the kernel, so it
+     * must be free. */
+    if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+    {
+        /* The wanted size is increased so it can contain a BlockLink_t
+         * structure in addition to the requested amount of bytes. */
+        if( xWantedSize > 0 )
+        {
+            xWantedSize += xHeapStructSize;
+
+            /* Ensure that blocks are always aligned to the required number of
+             * bytes. */
+            if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
+            {
+                /* Byte alignment required. */
+                xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
+                secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+        {
+            /* Traverse the list from the start (lowest address) block until
+             * one of adequate size is found. */
+            pxPreviousBlock = &xStart;
+            pxBlock = xStart.pxNextFreeBlock;
+
+            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+            {
+                pxPreviousBlock = pxBlock;
+                pxBlock = pxBlock->pxNextFreeBlock;
+            }
+
+            /* If the end marker was reached then a block of adequate size was
+             * not found. */
+            if( pxBlock != pxEnd )
+            {
+                /* Return the memory space pointed to - jumping over the
+                 * BlockLink_t structure at its start. */
+                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+                /* This block is being returned for use so must be taken out
+                 * of the list of free blocks. */
+                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+                /* If the block is larger than required it can be split into
+                 * two. */
+                if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
+                {
+                    /* This block is to be split into two.  Create a new
+                     * block following the number of bytes requested. The void
+                     * cast is used to prevent byte alignment warnings from the
+                     * compiler. */
+                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+                    secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
+
+                    /* Calculate the sizes of two blocks split from the single
+                     * block. */
+                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+                    pxBlock->xBlockSize = xWantedSize;
+
+                    /* Insert the new block into the list of free blocks. */
+                    prvInsertBlockIntoFreeList( pxNewBlockLink );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+                if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+                {
+                    xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                /* The block is being returned - it is allocated and owned by
+                 * the application and has no "next" block. */
+                pxBlock->xBlockSize |= xBlockAllocatedBit;
+                pxBlock->pxNextFreeBlock = NULL;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    traceMALLOC( pvReturn, xWantedSize );
+
+    #if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
+        {
+            if( pvReturn == NULL )
+            {
+                extern void vApplicationMallocFailedHook( void );
+                vApplicationMallocFailedHook();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    #endif /* if ( secureconfigUSE_MALLOC_FAILED_HOOK == 1 ) */
+
+    secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
+    return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void * pv )
+{
+    uint8_t * puc = ( uint8_t * ) pv;
+    BlockLink_t * pxLink;
+
+    if( pv != NULL )
+    {
+        /* The memory being freed will have an BlockLink_t structure immediately
+         * before it. */
+        puc -= xHeapStructSize;
+
+        /* This casting is to keep the compiler from issuing warnings. */
+        pxLink = ( void * ) puc;
+
+        /* Check the block is actually allocated. */
+        secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        secureportASSERT( pxLink->pxNextFreeBlock == NULL );
+
+        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        {
+            if( pxLink->pxNextFreeBlock == NULL )
+            {
+                /* The block is being returned to the heap - it is no longer
+                 * allocated. */
+                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+                secureportDISABLE_NON_SECURE_INTERRUPTS();
+                {
+                    /* Add this block to the list of free blocks. */
+                    xFreeBytesRemaining += pxLink->xBlockSize;
+                    traceFREE( pv, pxLink->xBlockSize );
+                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+                }
+                secureportENABLE_NON_SECURE_INTERRUPTS();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+    return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+    return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+    /* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
new file mode 100644
index 0000000..fa78046
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_HEAP_H__
+#define __SECURE_HEAP_H__
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/**
+ * @brief Allocates memory from heap.
+ *
+ * @param[in] xWantedSize The size of the memory to be allocated.
+ *
+ * @return Pointer to the memory region if the allocation is successful, NULL
+ * otherwise.
+ */
+void * pvPortMalloc( size_t xWantedSize );
+
+/**
+ * @brief Frees the previously allocated memory.
+ *
+ * @param[in] pv Pointer to the memory to be freed.
+ */
+void vPortFree( void * pv );
+
+#endif /* __SECURE_HEAP_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.c
new file mode 100644
index 0000000..4e6018d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.c
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+
+/* Secure init includes. */
+#include "secure_init.h"
+
+/* Secure port macros. */
+#include "secure_port_macros.h"
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define secureinitSCB_AIRCR                 ( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
+#define secureinitSCB_AIRCR_VECTKEY_POS     ( 16UL )
+#define secureinitSCB_AIRCR_VECTKEY_MASK    ( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
+#define secureinitSCB_AIRCR_PRIS_POS        ( 14UL )
+#define secureinitSCB_AIRCR_PRIS_MASK       ( 1UL << secureinitSCB_AIRCR_PRIS_POS )
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define secureinitFPCCR                     ( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
+#define secureinitFPCCR_LSPENS_POS          ( 29UL )
+#define secureinitFPCCR_LSPENS_MASK         ( 1UL << secureinitFPCCR_LSPENS_POS )
+#define secureinitFPCCR_TS_POS              ( 26UL )
+#define secureinitFPCCR_TS_MASK             ( 1UL << secureinitFPCCR_TS_POS )
+
+#define secureinitNSACR                     ( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
+#define secureinitNSACR_CP10_POS            ( 10UL )
+#define secureinitNSACR_CP10_MASK           ( 1UL << secureinitNSACR_CP10_POS )
+#define secureinitNSACR_CP11_POS            ( 11UL )
+#define secureinitNSACR_CP11_MASK           ( 1UL << secureinitNSACR_CP11_POS )
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        *( secureinitSCB_AIRCR ) = ( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
+                                   ( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
+                                   ( ( 0x1UL << secureinitSCB_AIRCR_PRIS_POS ) & secureinitSCB_AIRCR_PRIS_MASK );
+    }
+}
+/*-----------------------------------------------------------*/
+
+secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
+{
+    uint32_t ulIPSR;
+
+    /* Read the Interrupt Program Status Register (IPSR) value. */
+    secureportREAD_IPSR( ulIPSR );
+
+    /* Do nothing if the processor is running in the Thread Mode. IPSR is zero
+     * when the processor is running in the Thread Mode. */
+    if( ulIPSR != 0 )
+    {
+        /* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
+         * permitted. CP11 should be programmed to the same value as CP10. */
+        *( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
+
+        /* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
+         * that we can enable/disable lazy stacking in port.c file. */
+        *( secureinitFPCCR ) &= ~( secureinitFPCCR_LSPENS_MASK );
+
+        /* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
+         * registers (S16-S31) are also pushed to stack on exception entry and
+         * restored on exception return. */
+        *( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
+    }
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.h
new file mode 100644
index 0000000..39deb36
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_INIT_H__
+#define __SECURE_INIT_H__
+
+/**
+ * @brief De-prioritizes the non-secure exceptions.
+ *
+ * This is needed to ensure that the non-secure PendSV runs at the lowest
+ * priority. Context switch is done in the non-secure PendSV handler.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_DePrioritizeNSExceptions( void );
+
+/**
+ * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
+ *
+ * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
+ * Registers are not leaked to the non-secure side.
+ *
+ * @note This function must be called in the handler mode. It is no-op if called
+ * in the thread mode.
+ */
+void SecureInit_EnableNSFPUAccess( void );
+
+#endif /* __SECURE_INIT_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
new file mode 100644
index 0000000..7b8dbed
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __SECURE_PORT_MACROS_H__
+#define __SECURE_PORT_MACROS_H__
+
+/**
+ * @brief Byte alignment requirements.
+ */
+#define secureportBYTE_ALIGNMENT         8
+#define secureportBYTE_ALIGNMENT_MASK    ( 0x0007 )
+
+/**
+ * @brief Macro to declare a function as non-secure callable.
+ */
+#if defined( __IAR_SYSTEMS_ICC__ )
+    #define secureportNON_SECURE_CALLABLE    __cmse_nonsecure_entry __root
+#else
+    #define secureportNON_SECURE_CALLABLE    __attribute__( ( cmse_nonsecure_entry ) ) __attribute__( ( used ) )
+#endif
+
+/**
+ * @brief Set the secure PRIMASK value.
+ */
+#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
+    __asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Set the non-secure PRIMASK value.
+ */
+#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
+    __asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
+
+/**
+ * @brief Read the PSP value in the given variable.
+ */
+#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
+    __asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSP to the given value.
+ */
+#define secureportSET_PSP( pucCurrentStackPointer ) \
+    __asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
+
+/**
+ * @brief Set the PSPLIM to the given value.
+ */
+#define secureportSET_PSPLIM( pucStackLimit ) \
+    __asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
+
+/**
+ * @brief Set the NonSecure MSP to the given value.
+ */
+#define secureportSET_MSP_NS( pucMainStackPointer ) \
+    __asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
+
+/**
+ * @brief Set the CONTROL register to the given value.
+ */
+#define secureportSET_CONTROL( ulControl ) \
+    __asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
+
+/**
+ * @brief Read the Interrupt Program Status Register (IPSR) value in the given
+ * variable.
+ */
+#define secureportREAD_IPSR( ulIPSR ) \
+    __asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
+
+/**
+ * @brief PRIMASK value to enable interrupts.
+ */
+#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL     0
+
+/**
+ * @brief PRIMASK value to disable interrupts.
+ */
+#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL    1
+
+/**
+ * @brief Disable secure interrupts.
+ */
+#define secureportDISABLE_SECURE_INTERRUPTS()        secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Disable non-secure interrupts.
+ *
+ * This effectively disables context switches.
+ */
+#define secureportDISABLE_NON_SECURE_INTERRUPTS()    secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Enable non-secure interrupts.
+ */
+#define secureportENABLE_NON_SECURE_INTERRUPTS()     secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
+
+/**
+ * @brief Assert definition.
+ */
+#define secureportASSERT( x )                      \
+    if( ( x ) == 0 )                               \
+    {                                              \
+        secureportDISABLE_SECURE_INTERRUPTS();     \
+        secureportDISABLE_NON_SECURE_INTERRUPTS(); \
+        for( ; ; ) {; }                            \
+    }
+
+#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
new file mode 100644
index 0000000..852a11c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
@@ -0,0 +1,1192 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers. That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/* Portasm includes. */
+#include "portasm.h"
+
+#if ( configENABLE_TRUSTZONE == 1 )
+    /* Secure components includes. */
+    #include "secure_context.h"
+    #include "secure_init.h"
+#endif /* configENABLE_TRUSTZONE */
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/**
+ * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
+ * i.e. the processor boots as secure and never jumps to the non-secure side.
+ * The Trust Zone support in the port must be disabled in order to run FreeRTOS
+ * on the secure side. The following are the valid configuration seetings:
+ *
+ * 1. Run FreeRTOS on the Secure Side:
+ *    configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
+ *
+ * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
+ *
+ * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
+ *    configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
+ */
+#if ( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
+    #error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the NVIC.
+ */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
+#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ            configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT          ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the
+ * same a the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the SCB.
+ */
+#define portSCB_SYS_HANDLER_CTRL_STATE_REG    ( *( volatile uint32_t * ) 0xe000ed24 )
+#define portSCB_MEM_FAULT_ENABLE_BIT          ( 1UL << 16UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the FPU.
+ */
+#define portCPACR               ( ( volatile uint32_t * ) 0xe000ed88 )              /* Coprocessor Access Control Register. */
+#define portCPACR_CP10_VALUE    ( 3UL )
+#define portCPACR_CP11_VALUE    portCPACR_CP10_VALUE
+#define portCPACR_CP10_POS      ( 20UL )
+#define portCPACR_CP11_POS      ( 22UL )
+
+#define portFPCCR               ( ( volatile uint32_t * ) 0xe000ef34 )              /* Floating Point Context Control Register. */
+#define portFPCCR_ASPEN_POS     ( 31UL )
+#define portFPCCR_ASPEN_MASK    ( 1UL << portFPCCR_ASPEN_POS )
+#define portFPCCR_LSPEN_POS     ( 30UL )
+#define portFPCCR_LSPEN_MASK    ( 1UL << portFPCCR_LSPEN_POS )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to manipulate the MPU.
+ */
+#define portMPU_TYPE_REG                      ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_CTRL_REG                      ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portMPU_RNR_REG                       ( *( ( volatile uint32_t * ) 0xe000ed98 ) )
+
+#define portMPU_RBAR_REG                      ( *( ( volatile uint32_t * ) 0xe000ed9c ) )
+#define portMPU_RLAR_REG                      ( *( ( volatile uint32_t * ) 0xe000eda0 ) )
+
+#define portMPU_RBAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda4 ) )
+#define portMPU_RLAR_A1_REG                   ( *( ( volatile uint32_t * ) 0xe000eda8 ) )
+
+#define portMPU_RBAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edac ) )
+#define portMPU_RLAR_A2_REG                   ( *( ( volatile uint32_t * ) 0xe000edb0 ) )
+
+#define portMPU_RBAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb4 ) )
+#define portMPU_RLAR_A3_REG                   ( *( ( volatile uint32_t * ) 0xe000edb8 ) )
+
+#define portMPU_MAIR0_REG                     ( *( ( volatile uint32_t * ) 0xe000edc0 ) )
+#define portMPU_MAIR1_REG                     ( *( ( volatile uint32_t * ) 0xe000edc4 ) )
+
+#define portMPU_RBAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+#define portMPU_RLAR_ADDRESS_MASK             ( 0xffffffe0 ) /* Must be 32-byte aligned. */
+
+#define portMPU_MAIR_ATTR0_POS                ( 0UL )
+#define portMPU_MAIR_ATTR0_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR1_POS                ( 8UL )
+#define portMPU_MAIR_ATTR1_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR2_POS                ( 16UL )
+#define portMPU_MAIR_ATTR2_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR3_POS                ( 24UL )
+#define portMPU_MAIR_ATTR3_MASK               ( 0xff000000 )
+
+#define portMPU_MAIR_ATTR4_POS                ( 0UL )
+#define portMPU_MAIR_ATTR4_MASK               ( 0x000000ff )
+
+#define portMPU_MAIR_ATTR5_POS                ( 8UL )
+#define portMPU_MAIR_ATTR5_MASK               ( 0x0000ff00 )
+
+#define portMPU_MAIR_ATTR6_POS                ( 16UL )
+#define portMPU_MAIR_ATTR6_MASK               ( 0x00ff0000 )
+
+#define portMPU_MAIR_ATTR7_POS                ( 24UL )
+#define portMPU_MAIR_ATTR7_MASK               ( 0xff000000 )
+
+#define portMPU_RLAR_ATTR_INDEX0              ( 0UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX1              ( 1UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX2              ( 2UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX3              ( 3UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX4              ( 4UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX5              ( 5UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX6              ( 6UL << 1UL )
+#define portMPU_RLAR_ATTR_INDEX7              ( 7UL << 1UL )
+
+#define portMPU_RLAR_REGION_ENABLE            ( 1UL )
+
+/* Enable privileged access to unmapped region. */
+#define portMPU_PRIV_BACKGROUND_ENABLE_BIT    ( 1UL << 2UL )
+
+/* Enable MPU. */
+#define portMPU_ENABLE_BIT                    ( 1UL << 0UL )
+
+/* Expected value of the portMPU_TYPE register. */
+#define portEXPECTED_MPU_TYPE_VALUE           ( 8UL << 8UL ) /* 8 regions, unified. */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief The maximum 24-bit number.
+ *
+ * It is needed because the systick is a 24-bit counter.
+ */
+#define portMAX_24_BIT_NUMBER       ( 0xffffffUL )
+
+/**
+ * @brief A fiddle factor to estimate the number of SysTick counts that would
+ * have occurred while the SysTick counter is stopped during tickless idle
+ * calculations.
+ */
+#define portMISSED_COUNTS_FACTOR    ( 45UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Constants required to set up the initial stack.
+ */
+#define portINITIAL_XPSR    ( 0x01000000 )
+
+#if ( configRUN_FREERTOS_SECURE_ONLY == 1 )
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         FD
+ * 1111 1111  1111 1111  1111 1111  1111 1101
+ *
+ * Bit[6] - 1 --> The exception was taken from the Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 1 --> The exception was taken to the Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xfffffffd )
+#else
+
+/**
+ * @brief Initial EXC_RETURN value.
+ *
+ *     FF         FF         FF         BC
+ * 1111 1111  1111 1111  1111 1111  1011 1100
+ *
+ * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
+ * Bit[5] - 1 --> Do not skip stacking of additional state context.
+ * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
+ * Bit[3] - 1 --> Return to the Thread mode.
+ * Bit[2] - 1 --> Restore registers from the process stack.
+ * Bit[1] - 0 --> Reserved, 0.
+ * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
+ */
+    #define portINITIAL_EXC_RETURN    ( 0xffffffbc )
+#endif /* configRUN_FREERTOS_SECURE_ONLY */
+
+/**
+ * @brief CONTROL register privileged bit mask.
+ *
+ * Bit[0] in CONTROL register tells the privilege:
+ *  Bit[0] = 0 ==> The task is privileged.
+ *  Bit[0] = 1 ==> The task is not privileged.
+ */
+#define portCONTROL_PRIVILEGED_MASK         ( 1UL << 0UL )
+
+/**
+ * @brief Initial CONTROL register values.
+ */
+#define portINITIAL_CONTROL_UNPRIVILEGED    ( 0x3 )
+#define portINITIAL_CONTROL_PRIVILEGED      ( 0x2 )
+
+/**
+ * @brief Let the user override the pre-loading of the initial LR with the
+ * address of prvTaskExitError() in case it messes up unwinding of the stack
+ * in the debugger.
+ */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/**
+ * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
+ * when a task is created. This helps in debugging at the cost of code size.
+ */
+#define portPRELOAD_REGISTERS    1
+
+/**
+ * @brief A task is created without a secure context, and must call
+ * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
+ * any secure calls.
+ */
+#define portNO_SECURE_CONTEXT    0
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Used to catch tasks that attempt to return from their implementing
+ * function.
+ */
+static void prvTaskExitError( void );
+
+#if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Setup the Memory Protection Unit (MPU).
+ */
+    static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+
+/**
+ * @brief Setup the Floating Point Unit (FPU).
+ */
+    static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
+#endif /* configENABLE_FPU */
+
+/**
+ * @brief Setup the timer to generate the tick interrupts.
+ *
+ * The implementation in this file is weak to allow application writers to
+ * change the timer used to generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether the current execution context is interrupt.
+ *
+ * @return pdTRUE if the current execution context is interrupt, pdFALSE
+ * otherwise.
+ */
+BaseType_t xPortIsInsideInterrupt( void );
+
+/**
+ * @brief Yield the processor.
+ */
+void vPortYield( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enter critical section.
+ */
+void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Exit from critical section.
+ */
+void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SysTick handler.
+ */
+void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief C part of SVC handler.
+ */
+portDONT_DISCARD void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Each task maintains its own interrupt status in the critical nesting
+ * variable.
+ */
+PRIVILEGED_DATA static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+#if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Saved as part of the task context to indicate which context the
+ * task is using on the secure side.
+ */
+    PRIVILEGED_DATA portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
+#endif /* configENABLE_TRUSTZONE */
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+/**
+ * @brief The number of SysTick increments that make up one tick period.
+ */
+    PRIVILEGED_DATA static uint32_t ulTimerCountsForOneTick = 0;
+
+/**
+ * @brief The maximum number of tick periods that can be suppressed is
+ * limited by the 24 bit resolution of the SysTick timer.
+ */
+    PRIVILEGED_DATA static uint32_t xMaximumPossibleSuppressedTicks = 0;
+
+/**
+ * @brief Compensate for the CPU cycles that pass while the SysTick is
+ * stopped (low power functionality only).
+ */
+    PRIVILEGED_DATA static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    __attribute__( ( weak ) ) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily. The time the SysTick is stopped for is
+         * accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods. -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm volatile ( "cpsid i" ::: "memory" );
+        __asm volatile ( "dsb" );
+        __asm volatile ( "isb" );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be un-suspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above the cpsid instruction()
+             * above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation
+             * contains its own wait for interrupt or wait for event
+             * instruction, and so wfi should not be executed again. However,
+             * the original expected idle time variable must remain unmodified,
+             * so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm volatile ( "dsb" ::: "memory" );
+                __asm volatile ( "wfi" );
+                __asm volatile ( "isb" );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately. See comments above
+             * the cpsid instruction above. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will
+             * increase any slippage between the time maintained by the RTOS and
+             * calendar time. */
+            __asm volatile ( "cpsid i" ::: "memory" );
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.
+             * Again, the time the SysTick is stopped for is accounted for as
+             * best it can be, but using the tickless mode will inevitably
+             * result in some tiny drift of the time maintained by the kernel
+             * with respect to calendar time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is
+             * yet to count to zero (in which case an interrupt other than the
+             * SysTick must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is
+                 * stepped forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __asm volatile ( "cpsie i" ::: "memory" );
+        }
+    }
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+__attribute__( ( weak ) ) void vPortSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and reset the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    volatile uint32_t ulDummy = 0UL;
+
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to. If a task wants to exit it
+     * should instead call vTaskDelete( NULL ). Artificially force an assert()
+     * to be triggered if configASSERT() is defined, then stop here so
+     * application writers can catch the error. */
+    configASSERT( ulCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    while( ulDummy == 0 )
+    {
+        /* This file calls prvTaskExitError() after the scheduler has been
+         * started to remove a compiler warning about the function being
+         * defined but never called.  ulDummy is used purely to quieten other
+         * warnings about code appearing after this function is called - making
+         * ulDummy volatile makes the compiler think the function could return
+         * and therefore not output an 'unreachable code' warning for code that
+         * appears after it. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_functions_start__;
+            extern uint32_t * __privileged_functions_end__;
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+            extern uint32_t * __unprivileged_flash_start__;
+            extern uint32_t * __unprivileged_flash_end__;
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else /* if defined( __ARMCC_VERSION ) */
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_functions_start__[];
+            extern uint32_t __privileged_functions_end__[];
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+            extern uint32_t __unprivileged_flash_start__[];
+            extern uint32_t __unprivileged_flash_end__[];
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Check that the MPU is present. */
+        if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+        {
+            /* MAIR0 - Index 0. */
+            portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+            /* MAIR0 - Index 1. */
+            portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+            /* Setup privileged flash as Read Only so that privileged tasks can
+             * read it but not modify. */
+            portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged flash as Read Only by both privileged and
+             * unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup unprivileged syscalls flash as Read Only by both privileged
+             * and unprivileged tasks. All tasks can read it but no-one can modify. */
+            portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_READ_ONLY );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Setup RAM containing kernel data for privileged access only. */
+            portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
+            portMPU_RBAR_REG = ( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
+                               ( portMPU_REGION_NON_SHAREABLE ) |
+                               ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                               ( portMPU_REGION_EXECUTE_NEVER );
+            portMPU_RLAR_REG = ( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
+                               ( portMPU_RLAR_ATTR_INDEX0 ) |
+                               ( portMPU_RLAR_REGION_ENABLE );
+
+            /* Enable mem fault. */
+            portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE_BIT;
+
+            /* Enable MPU with privileged background access i.e. unmapped
+             * regions have privileged access. */
+            portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE_BIT | portMPU_ENABLE_BIT );
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_FPU == 1 )
+    static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            {
+                /* Enable non-secure access to the FPU. */
+                SecureInit_EnableNSFPUAccess();
+            }
+        #endif /* configENABLE_TRUSTZONE */
+
+        /* CP10 = 11 ==> Full access to FPU i.e. both privileged and
+         * unprivileged code should be able to access FPU. CP11 should be
+         * programmed to the same value as CP10. */
+        *( portCPACR ) |= ( ( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
+                            ( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
+                            );
+
+        /* ASPEN = 1 ==> Hardware should automatically preserve floating point
+         * context on exception entry and restore on exception return.
+         * LSPEN = 1 ==> Enable lazy context save of FP state. */
+        *( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
+    }
+#endif /* configENABLE_FPU */
+/*-----------------------------------------------------------*/
+
+void vPortYield( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Set a PendSV to request a context switch. */
+    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    portDISABLE_INTERRUPTS();
+    ulCriticalNesting++;
+
+    /* Barriers are normally not required but do ensure the code is
+     * completely within the specified behaviour for the architecture. */
+    __asm volatile ( "dsb" ::: "memory" );
+    __asm volatile ( "isb" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
+{
+    configASSERT( ulCriticalNesting );
+    ulCriticalNesting--;
+
+    if( ulCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
+{
+    uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
+{
+    #if ( configENABLE_MPU == 1 )
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __syscalls_flash_start__;
+            extern uint32_t * __syscalls_flash_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __syscalls_flash_start__[];
+            extern uint32_t __syscalls_flash_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+    #endif /* configENABLE_MPU */
+
+    uint32_t ulPC;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        uint32_t ulR0;
+        #if ( configENABLE_MPU == 1 )
+            uint32_t ulControl, ulIsTaskPrivileged;
+        #endif /* configENABLE_MPU */
+    #endif /* configENABLE_TRUSTZONE */
+    uint8_t ucSVCNumber;
+
+    /* Register are stored on the stack in the following order - R0, R1, R2, R3,
+     * R12, LR, PC, xPSR. */
+    ulPC = pulCallerStackAddress[ 6 ];
+    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        #if ( configENABLE_TRUSTZONE == 1 )
+            case portSVC_ALLOCATE_SECURE_CONTEXT:
+
+                /* R0 contains the stack size passed as parameter to the
+                 * vPortAllocateSecureContext function. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                #if ( configENABLE_MPU == 1 )
+                    {
+                        /* Read the CONTROL register value. */
+                        __asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
+
+                        /* The task that raised the SVC is privileged if Bit[0]
+                         * in the CONTROL register is 0. */
+                        ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
+
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
+                    }
+                #else /* if ( configENABLE_MPU == 1 ) */
+                    {
+                        /* Allocate and load a context for the secure task. */
+                        xSecureContext = SecureContext_AllocateContext( ulR0 );
+                    }
+                #endif /* configENABLE_MPU */
+
+                configASSERT( xSecureContext != NULL );
+                SecureContext_LoadContext( xSecureContext );
+                break;
+
+            case portSVC_FREE_SECURE_CONTEXT:
+                /* R0 contains the secure context handle to be freed. */
+                ulR0 = pulCallerStackAddress[ 0 ];
+
+                /* Free the secure context. */
+                SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
+                break;
+        #endif /* configENABLE_TRUSTZONE */
+
+        case portSVC_START_SCHEDULER:
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    /* De-prioritize the non-secure exceptions so that the
+                     * non-secure pendSV runs at the lowest priority. */
+                    SecureInit_DePrioritizeNSExceptions();
+
+                    /* Initialize the secure context management system. */
+                    SecureContext_Init();
+                }
+            #endif /* configENABLE_TRUSTZONE */
+
+            #if ( configENABLE_FPU == 1 )
+                {
+                    /* Setup the Floating Point Unit (FPU). */
+                    prvSetupFPU();
+                }
+            #endif /* configENABLE_FPU */
+
+            /* Setup the context of the first task so that the first task starts
+             * executing. */
+            vRestoreContextOfFirstTask();
+            break;
+
+            #if ( configENABLE_MPU == 1 )
+                case portSVC_RAISE_PRIVILEGE:
+
+                    /* Only raise the privilege, if the svc was raised from any of
+                     * the system calls. */
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        vRaisePrivilege();
+                    }
+                    break;
+            #endif /* configENABLE_MPU */
+
+        default:
+            /* Incorrect SVC call. */
+            configASSERT( pdFALSE );
+    }
+}
+/*-----------------------------------------------------------*/
+/* *INDENT-OFF* */
+#if ( configENABLE_MPU == 1 )
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
+#else
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         StackType_t * pxEndOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters ) /* PRIVILEGED_FUNCTION */
+#endif /* configENABLE_MPU */
+/* *INDENT-ON* */
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    #if ( portPRELOAD_REGISTERS == 0 )
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack -= 5;                                       /* R12, R3, R2 and R1. */
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack -= 9;                                       /* R11..R4, EXC_RETURN. */
+            *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #else /* portPRELOAD_REGISTERS */
+        {
+            pxTopOfStack--;                                          /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+            *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x12121212UL;            /* R12 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x03030303UL;            /* R3 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x02020202UL;            /* R2 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x01010101UL;            /* R1 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pvParameters;            /* R0 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x11111111UL;            /* R11 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x10101010UL;            /* R10 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x09090909UL;            /* R09 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x08080808UL;            /* R08 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x07070707UL;            /* R07 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x06060606UL;            /* R06 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x05050505UL;            /* R05 */
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) 0x04040404UL;            /* R04 */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_EXC_RETURN;                  /* EXC_RETURN */
+
+            #if ( configENABLE_MPU == 1 )
+                {
+                    pxTopOfStack--;
+
+                    if( xRunPrivileged == pdTRUE )
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                    else
+                    {
+                        *pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED; /* Slot used to hold this task's CONTROL value. */
+                    }
+                }
+            #endif /* configENABLE_MPU */
+
+            pxTopOfStack--;
+            *pxTopOfStack = ( StackType_t ) pxEndOfStack; /* Slot used to hold this task's PSPLIM value. */
+
+            #if ( configENABLE_TRUSTZONE == 1 )
+                {
+                    pxTopOfStack--;
+                    *pxTopOfStack = portNO_SECURE_CONTEXT; /* Slot used to hold this task's xSecureContext value. */
+                }
+            #endif /* configENABLE_TRUSTZONE */
+        }
+    #endif /* portPRELOAD_REGISTERS */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    #if ( configENABLE_MPU == 1 )
+        {
+            /* Setup the Memory Protection Unit (MPU). */
+            prvSetupMPU();
+        }
+    #endif /* configENABLE_MPU */
+
+    /* Start the timer that generates the tick ISR. Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialize the critical nesting count ready for the first task. */
+    ulCriticalNesting = 0;
+
+    /* Start the first task. */
+    vStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing. Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. Call
+     * vTaskSwitchContext() so link time optimization does not remove the
+     * symbol. */
+    vTaskSwitchContext();
+    prvTaskExitError();
+
+    /* Should not get here. */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configENABLE_MPU == 1 )
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    uint32_t ulStackDepth )
+    {
+        uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
+        int32_t lIndex = 0;
+
+        #if defined( __ARMCC_VERSION )
+
+            /* Declaration when these variable are defined in code instead of being
+             * exported from linker scripts. */
+            extern uint32_t * __privileged_sram_start__;
+            extern uint32_t * __privileged_sram_end__;
+        #else
+            /* Declaration when these variable are exported from linker scripts. */
+            extern uint32_t __privileged_sram_start__[];
+            extern uint32_t __privileged_sram_end__[];
+        #endif /* defined( __ARMCC_VERSION ) */
+
+        /* Setup MAIR0. */
+        xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
+        xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
+
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid.  At all other
+         * times the stack parameters will not be valid and it is assumed that
+         * the stack region has already been configured. */
+        if( ulStackDepth > 0 )
+        {
+            ulRegionStartAddress = ( uint32_t ) pxBottomOfStack;
+            ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
+
+            /* If the stack is within the privileged SRAM, do not protect it
+             * using a separate MPU region. This is needed because privileged
+             * SRAM is already protected using an MPU region and ARMv8-M does
+             * not allow overlapping MPU regions. */
+            if( ( ulRegionStartAddress >= ( uint32_t ) __privileged_sram_start__ ) &&
+                ( ulRegionEndAddress <= ( uint32_t ) __privileged_sram_end__ ) )
+            {
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = 0;
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = 0;
+            }
+            else
+            {
+                /* Define the region that allows access to the stack. */
+                ulRegionStartAddress &= portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRBAR = ( ulRegionStartAddress ) |
+                                                             ( portMPU_REGION_NON_SHAREABLE ) |
+                                                             ( portMPU_REGION_READ_WRITE ) |
+                                                             ( portMPU_REGION_EXECUTE_NEVER );
+
+                xMPUSettings->xRegionsSettings[ 0 ].ulRLAR = ( ulRegionEndAddress ) |
+                                                             ( portMPU_RLAR_ATTR_INDEX0 ) |
+                                                             ( portMPU_RLAR_REGION_ENABLE );
+            }
+        }
+
+        /* User supplied configurable regions. */
+        for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
+        {
+            /* If xRegions is NULL i.e. the task has not specified any MPU
+             * region, the else part ensures that all the configurable MPU
+             * regions are invalidated. */
+            if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
+            {
+                /* Translate the generic region definition contained in xRegions
+                 * into the ARMv8 specific MPU settings that are then stored in
+                 * xMPUSettings. */
+                ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
+                ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
+                ulRegionEndAddress &= portMPU_RLAR_ADDRESS_MASK;
+
+                /* Start address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = ( ulRegionStartAddress ) |
+                                                                          ( portMPU_REGION_NON_SHAREABLE );
+
+                /* RO/RW. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
+                }
+                else
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
+                }
+
+                /* XN. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
+                {
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
+                }
+
+                /* End Address. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = ( ulRegionEndAddress ) |
+                                                                          ( portMPU_RLAR_REGION_ENABLE );
+
+                /* Normal memory/ Device memory. */
+                if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
+                {
+                    /* Attr1 in MAIR0 is configured as device memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
+                }
+                else
+                {
+                    /* Attr1 in MAIR0 is configured as normal memory. */
+                    xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
+                }
+            }
+            else
+            {
+                /* Invalidate the region. */
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
+                xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
+            }
+
+            lIndex++;
+        }
+    }
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. Interrupt Program
+     * Status Register (IPSR) holds the exception number of the currently-executing
+     * exception or zero for Thread mode.*/
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
new file mode 100644
index 0000000..b01f171
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef __PORT_ASM_H__
+#define __PORT_ASM_H__
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+
+/* MPU wrappers includes. */
+#include "mpu_wrappers.h"
+
+/**
+ * @brief Restore the context of the first task so that the first task starts
+ * executing.
+ */
+void vRestoreContextOfFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
+ * register.
+ *
+ * @note This is a privileged function and should only be called from the kenrel
+ * code.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vRaisePrivilege( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void ) __attribute__( ( naked ) );
+
+/**
+ * @brief Starts the first task.
+ */
+void vStartFirstTask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Disables interrupts.
+ */
+uint32_t ulSetInterruptMask( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Enables interrupts.
+ */
+void vClearInterruptMask( uint32_t ulMask ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief PendSV Exception handler.
+ */
+void PendSV_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief SVC Handler.
+ */
+void SVC_Handler( void ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Allocate a Secure context for the calling task.
+ *
+ * @param[in] ulSecureStackSize The size of the stack to be allocated on the
+ * secure side for the calling task.
+ */
+void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__( ( naked ) );
+
+/**
+ * @brief Free the task's secure context.
+ *
+ * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
+ */
+void vPortFreeSecureContext( uint32_t * pulTCB ) __attribute__( ( naked ) ) PRIVILEGED_FUNCTION;
+
+#endif /* __PORT_ASM_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
new file mode 100644
index 0000000..b65f0f4
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
@@ -0,0 +1,261 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+/* Including FreeRTOSConfig.h here will cause build errors if the header file
+contains code not understood by the assembler - for example the 'extern' keyword.
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
+the code is included in C files but excluded by the preprocessor in assembly
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
+#include "FreeRTOSConfig.h"
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+	PUBLIC vRestoreContextOfFirstTask
+	PUBLIC vRaisePrivilege
+	PUBLIC vStartFirstTask
+	PUBLIC ulSetInterruptMask
+	PUBLIC vClearInterruptMask
+	PUBLIC PendSV_Handler
+	PUBLIC SVC_Handler
+/*-----------------------------------------------------------*/
+
+/*---------------- Unprivileged Functions -------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION .text:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control							/* r0 = CONTROL. */
+	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	ite ne
+	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control							/* r0 = CONTROL. */
+	orr r0, r0, #1							/* r0 = r0 | 1. */
+	msr control, r0							/* CONTROL = r0. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+/*----------------- Privileged Functions --------------------*/
+
+/*-----------------------------------------------------------*/
+
+	SECTION privileged_functions:CODE:NOROOT(2)
+	THUMB
+/*-----------------------------------------------------------*/
+
+vRestoreContextOfFirstTask:
+	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr  r1, [r2]							/* Read pxCurrentTCB. */
+	ldr  r0, [r1]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
+	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str r3, [r2]							/* Program MAIR0. */
+	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
+	movs r3, #4								/* r3 = 4. */
+	str r3, [r2]							/* Program RNR = 4. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
+	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
+	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldm  r0!, {r1-r3}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	msr  control, r2						/* Set this task's CONTROL value. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	mov  r0, #0
+	msr  basepri, r0						/* Ensure that interrupts are enabled when the first task starts. */
+	bx   r3									/* Finally, branch to EXC_RETURN. */
+#else /* configENABLE_MPU */
+	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
+	msr  psplim, r1							/* Set this task's PSPLIM value. */
+	movs r1, #2								/* r1 = 2. */
+	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
+	adds r0, #32							/* Discard everything up to r0. */
+	msr  psp, r0							/* This is now the new top of stack to use in the task. */
+	isb
+	mov  r0, #0
+	msr  basepri, r0						/* Ensure that interrupts are enabled when the first task starts. */
+	bx   r2									/* Finally, branch to EXC_RETURN. */
+#endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+vRaisePrivilege:
+	mrs  r0, control						/* Read the CONTROL register. */
+	bic r0, r0, #1							/* Clear the bit 0. */
+	msr  control, r0						/* Write back the new CONTROL value. */
+	bx lr									/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+vStartFirstTask:
+	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
+	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
+	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
+	msr msp, r0								/* Set the MSP back to the start of the stack. */
+	cpsie i									/* Globally enable interrupts. */
+	cpsie f
+	dsb
+	isb
+	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
+/*-----------------------------------------------------------*/
+
+ulSetInterruptMask:
+	mrs r0, basepri							/* r0 = basepri. Return original basepri value. */
+	mov r1, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr basepri, r1							/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+	dsb
+	isb
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+vClearInterruptMask:
+	msr basepri, r0							/* basepri = ulMask. */
+	dsb
+	isb
+	bx lr									/* Return. */
+/*-----------------------------------------------------------*/
+
+PendSV_Handler:
+	mrs r0, psp								/* Read PSP in r0. */
+#if ( configENABLE_FPU == 1 )
+	tst lr, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	it eq
+	vstmdbeq r0!, {s16-s31}					/* Store the FPU registers which are not saved automatically. */
+#endif /* configENABLE_FPU */
+#if ( configENABLE_MPU == 1 )
+	mrs r1, psplim							/* r1 = PSPLIM. */
+	mrs r2, control							/* r2 = CONTROL. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmdb r0!, {r1-r11}						/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
+#else /* configENABLE_MPU */
+	mrs r2, psplim							/* r2 = PSPLIM. */
+	mov r3, lr								/* r3 = LR/EXC_RETURN. */
+	stmdb r0!, {r2-r11}						/* Store on the stack - PSPLIM, LR and registers that are not automatically. */
+#endif /* configENABLE_MPU */
+
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+	str r0, [r1]							/* Save the new top of stack in TCB. */
+
+	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr basepri, r0							/* Disable interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+	dsb
+	isb
+	bl vTaskSwitchContext
+	mov r0, #0								/* r0 = 0. */
+	msr basepri, r0							/* Enable interrupts. */
+
+	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
+	ldr r1, [r2]							/* Read pxCurrentTCB. */
+	ldr r0, [r1]							/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
+
+#if ( configENABLE_MPU == 1 )
+	dmb										/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
+	str r4, [r2]							/* Disable MPU. */
+
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
+	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
+	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
+	str r3, [r2]							/* Program MAIR0. */
+	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
+	movs r3, #4								/* r3 = 4. */
+	str r3, [r2]							/* Program RNR = 4. */
+	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
+	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
+	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
+	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
+
+	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
+	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
+	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
+	str r4, [r2]							/* Enable MPU. */
+	dsb										/* Force memory writes before continuing. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_MPU == 1 )
+	ldmia r0!, {r1-r11}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
+#else /* configENABLE_MPU */
+	ldmia r0!, {r2-r11}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
+#endif /* configENABLE_MPU */
+
+#if ( configENABLE_FPU == 1 )
+	tst r3, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
+	it eq
+	vldmiaeq r0!, {s16-s31}					/* Restore the FPU registers which are not restored automatically. */
+#endif /* configENABLE_FPU */
+
+ #if ( configENABLE_MPU == 1 )
+	msr psplim, r1							/* Restore the PSPLIM register value for the task. */
+	msr control, r2							/* Restore the CONTROL register value for the task. */
+#else /* configENABLE_MPU */
+	msr psplim, r2							/* Restore the PSPLIM register value for the task. */
+#endif /* configENABLE_MPU */
+	msr psp, r0								/* Remember the new top of stack for the task. */
+	bx r3
+/*-----------------------------------------------------------*/
+
+SVC_Handler:
+	tst lr, #4
+	ite eq
+	mrseq r0, msp
+	mrsne r0, psp
+	b vPortSVCHandler_C
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
new file mode 100644
index 0000000..e3fa10a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
@@ -0,0 +1,319 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*------------------------------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *------------------------------------------------------------------------------
+ */
+
+    #ifndef configENABLE_FPU
+        #error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
+    #endif /* configENABLE_FPU */
+
+    #ifndef configENABLE_MPU
+        #error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
+    #endif /* configENABLE_MPU */
+
+    #ifndef configENABLE_TRUSTZONE
+        #error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
+    #endif /* configENABLE_TRUSTZONE */
+
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Type definitions.
+ */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * Architecture specifics.
+ */
+    #define portARCH_NAME                      "Cortex-M33"
+    #define portSTACK_GROWTH                   ( -1 )
+    #define portTICK_PERIOD_MS                 ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT                 8
+    #define portNOP()
+    #define portINLINE                         __inline
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE               inline __attribute__( ( always_inline ) )
+    #endif
+    #define portHAS_STACK_OVERFLOW_CHECKING    1
+    #define portDONT_DISCARD                   __root
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Extern declarations.
+ */
+    extern BaseType_t xPortIsInsideInterrupt( void );
+
+    extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
+    extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
+
+    extern uint32_t ulSetInterruptMask( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+    extern void vClearInterruptMask( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+        extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
+        extern void vPortFreeSecureContext( uint32_t * pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
+    #endif /* configENABLE_TRUSTZONE */
+
+    #if ( configENABLE_MPU == 1 )
+        extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
+        extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief MPU specific constants.
+ */
+    #if ( configENABLE_MPU == 1 )
+        #define portUSING_MPU_WRAPPERS    1
+        #define portPRIVILEGE_BIT         ( 0x80000000UL )
+    #else
+        #define portPRIVILEGE_BIT         ( 0x0UL )
+    #endif /* configENABLE_MPU */
+
+
+/* MPU regions. */
+    #define portPRIVILEGED_FLASH_REGION                   ( 0UL )
+    #define portUNPRIVILEGED_FLASH_REGION                 ( 1UL )
+    #define portUNPRIVILEGED_SYSCALLS_REGION              ( 2UL )
+    #define portPRIVILEGED_RAM_REGION                     ( 3UL )
+    #define portSTACK_REGION                              ( 4UL )
+    #define portFIRST_CONFIGURABLE_REGION                 ( 5UL )
+    #define portLAST_CONFIGURABLE_REGION                  ( 7UL )
+    #define portNUM_CONFIGURABLE_REGIONS                  ( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
+    #define portTOTAL_NUM_REGIONS                         ( portNUM_CONFIGURABLE_REGIONS + 1 )   /* Plus one to make space for the stack region. */
+
+/* Device memory attributes used in MPU_MAIR registers.
+ *
+ * 8-bit values encoded as follows:
+ *  Bit[7:4] - 0000 - Device Memory
+ *  Bit[3:2] - 00 --> Device-nGnRnE
+ *				01 --> Device-nGnRE
+ *				10 --> Device-nGRE
+ *				11 --> Device-GRE
+ *  Bit[1:0] - 00, Reserved.
+ */
+    #define portMPU_DEVICE_MEMORY_nGnRnE                  ( 0x00 )   /* 0000 0000 */
+    #define portMPU_DEVICE_MEMORY_nGnRE                   ( 0x04 )   /* 0000 0100 */
+    #define portMPU_DEVICE_MEMORY_nGRE                    ( 0x08 )   /* 0000 1000 */
+    #define portMPU_DEVICE_MEMORY_GRE                     ( 0x0C )   /* 0000 1100 */
+
+/* Normal memory attributes used in MPU_MAIR registers. */
+    #define portMPU_NORMAL_MEMORY_NON_CACHEABLE           ( 0x44 )   /* Non-cacheable. */
+    #define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE    ( 0xFF )   /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
+
+/* Attributes used in MPU_RBAR registers. */
+    #define portMPU_REGION_NON_SHAREABLE                  ( 0UL << 3UL )
+    #define portMPU_REGION_INNER_SHAREABLE                ( 1UL << 3UL )
+    #define portMPU_REGION_OUTER_SHAREABLE                ( 2UL << 3UL )
+
+    #define portMPU_REGION_PRIVILEGED_READ_WRITE          ( 0UL << 1UL )
+    #define portMPU_REGION_READ_WRITE                     ( 1UL << 1UL )
+    #define portMPU_REGION_PRIVILEGED_READ_ONLY           ( 2UL << 1UL )
+    #define portMPU_REGION_READ_ONLY                      ( 3UL << 1UL )
+
+    #define portMPU_REGION_EXECUTE_NEVER                  ( 1UL )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Settings to define an MPU region.
+ */
+    typedef struct MPURegionSettings
+    {
+        uint32_t ulRBAR; /**< RBAR for the region. */
+        uint32_t ulRLAR; /**< RLAR for the region. */
+    } MPURegionSettings_t;
+
+/**
+ * @brief MPU settings as stored in the TCB.
+ */
+    typedef struct MPU_SETTINGS
+    {
+        uint32_t ulMAIR0;                                              /**< MAIR0 for the task containing attributes for all the 4 per task regions. */
+        MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
+    } xMPU_SETTINGS;
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief SVC numbers.
+ */
+    #define portSVC_ALLOCATE_SECURE_CONTEXT    0
+    #define portSVC_FREE_SECURE_CONTEXT        1
+    #define portSVC_START_SCHEDULER            2
+    #define portSVC_RAISE_PRIVILEGE            3
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Scheduler utilities.
+ */
+    #define portYIELD()                                 vPortYield()
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Critical section management.
+ */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMask( x )
+    #define portDISABLE_INTERRUPTS()                  ulSetInterruptMask()
+    #define portENABLE_INTERRUPTS()                   vClearInterruptMask( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Tickless idle/low power functionality.
+ */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Task function macros as described on the FreeRTOS.org WEB site.
+ */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_TRUSTZONE == 1 )
+
+/**
+ * @brief Allocate a secure context for the task.
+ *
+ * Tasks are not created with a secure context. Any task that is going to call
+ * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
+ * secure context before it calls any secure function.
+ *
+ * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
+ */
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )    vPortAllocateSecureContext( ulSecureStackSize )
+
+/**
+ * @brief Called when a task is deleted to delete the task's secure context,
+ * if it has one.
+ *
+ * @param[in] pxTCB The TCB of the task being deleted.
+ */
+        #define portCLEAN_UP_TCB( pxTCB )                           vPortFreeSecureContext( ( uint32_t * ) pxTCB )
+    #else
+        #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
+        #define portCLEAN_UP_TCB( pxTCB )
+    #endif /* configENABLE_TRUSTZONE */
+/*-----------------------------------------------------------*/
+
+    #if ( configENABLE_MPU == 1 )
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+        #define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ *
+ * The SVC handler checks that the SVC was raised from a system call and only
+ * then it raises the privilege. If this is called from any other place,
+ * the privilege is not raised.
+ */
+        #define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+        #define portRESET_PRIVILEGE()    vResetPrivilege()
+    #else
+        #define portIS_PRIVILEGED()
+        #define portRAISE_PRIVILEGE()
+        #define portRESET_PRIVILEGE()
+    #endif /* configENABLE_MPU */
+/*-----------------------------------------------------------*/
+
+/**
+ * @brief Barriers.
+ */
+    #define portMEMORY_BARRIER()    __asm volatile ( "" ::: "memory" )
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+    #pragma diag_suppress=Be006
+    #pragma diag_suppress=Pa082
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c
new file mode 100644
index 0000000..3da7fe2
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c
@@ -0,0 +1,645 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM4F port.
+*----------------------------------------------------------*/
+
+/* IAR includes. */
+#include <intrinsics.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __ARMVFP__
+    #error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
+    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )
+
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
+ * r0p1 port. */
+#define portCPUID                             ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID                 ( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID                 ( 0x410FC270UL )
+
+#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
+#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                    ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK                   ( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR                             ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS              ( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                      ( 0x01000000 )
+#define portINITIAL_EXC_RETURN                ( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#define portMISSED_COUNTS_FACTOR              ( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortSysTickHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Turn the VFP on.
+ */
+extern void vPortEnableVFP( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+
+    /* Offset added to account for the way the MCU uses the stack on entry/exit
+     * of interrupts, and to ensure alignment. */
+    pxTopOfStack--;
+
+    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) prvTaskExitError;                    /* LR */
+
+    /* Save code space by skipping register initialisation. */
+    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+    /* A save method is being used that requires each task to maintain its
+     * own exec return value. */
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+    pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( uxCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    for( ; ; )
+    {
+    }
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+    /* This port can be used on all revisions of the Cortex-M7 core other than
+     * the r0p1 parts.  r0p1 parts should use the port from the
+     * /source/portable/GCC/ARM_CM7/r0p1 directory. */
+    configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+    configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+            volatile uint8_t ucMaxPriorityValue;
+
+            /* Determine the maximum priority from which ISR safe FreeRTOS API
+             * functions can be called.  ISR safe functions are those that end in
+             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+             * ensure interrupt entry is as fast and simple as possible.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+            /* Determine the number of priority bits available.  First write to all
+             * possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+            /* Use the same mask on the maximum system call priority. */
+            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+            /* Calculate the maximum acceptable priority group value for the number
+             * of bits read back. */
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+            {
+                ulMaxPRIGROUPValue--;
+                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+            }
+
+            #ifdef __NVIC_PRIO_BITS
+                {
+                    /* Check the CMSIS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+                }
+            #endif
+
+            #ifdef configPRIO_BITS
+                {
+                    /* Check the FreeRTOS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+                }
+            #endif
+
+            /* Shift the priority group value back to its position within the AIRCR
+             * register. */
+            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* conifgASSERT_DEFINED */
+
+    /* Make PendSV and SysTick the lowest priority interrupts. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Ensure the VFP is enabled - it should be anyway. */
+    vPortEnableVFP();
+
+    /* Lazy save always. */
+    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+    /* Start the first task. */
+    vPortStartFirstTask();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
+    if( uxCriticalNesting == 1 )
+    {
+        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+     * executes all interrupts must be unmasked.  There is therefore no need to
+     * save and then restore the interrupt mask value as its value is already
+     * known. */
+    portDISABLE_INTERRUPTS();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* A context switch is required.  Context switching is performed in
+             * the PendSV interrupt.  Pend the PendSV interrupt. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+    __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+         * is accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods.  -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __disable_interrupt();
+        __DSB();
+        __ISB();
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above __disable_interrupt()
+             * call above. */
+            __enable_interrupt();
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again.  However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __DSB();
+                __WFI();
+                __ISB();
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately.  see comments above
+             * __disable_interrupt() call above. */
+            __enable_interrupt();
+            __DSB();
+            __ISB();
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __disable_interrupt();
+            __DSB();
+            __ISB();
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is yet
+             * to count to zero (in which case an interrupt other than the SysTick
+             * must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __enable_interrupt();
+        }
+    }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__weak void vPortSetupTimerInterrupt( void )
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and clear the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+    void vPortValidateInterruptPriority( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        uint8_t ucCurrentPriority;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that	use the FreeRTOS API must not be left at their
+             * default priority of	zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and	therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
+
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredictable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
+
+#endif /* configASSERT_DEFINED */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s
new file mode 100644
index 0000000..768b62f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include <FreeRTOSConfig.h>
+
+	RSEG    CODE:CODE(2)
+	thumb
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+
+	PUBLIC xPortPendSVHandler
+	PUBLIC vPortSVCHandler
+	PUBLIC vPortStartFirstTask
+	PUBLIC vPortEnableVFP
+
+
+/*-----------------------------------------------------------*/
+
+xPortPendSVHandler:
+	mrs r0, psp
+	isb
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr	r2, [r3]
+
+	/* Is the task using the FPU context?  If so, push high vfp registers. */
+	tst r14, #0x10
+	it eq
+	vstmdbeq r0!, {s16-s31}
+
+	/* Save the core registers. */
+	stmdb r0!, {r4-r11, r14}
+
+	/* Save the new top of stack into the first member of the TCB. */
+	str r0, [r2]
+
+	stmdb sp!, {r0, r3}
+	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr basepri, r0
+	dsb
+	isb
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r0, r3}
+
+	/* The first item in pxCurrentTCB is the task top of stack. */
+	ldr r1, [r3]
+	ldr r0, [r1]
+
+	/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+
+	/* Is the task using the FPU context?  If so, pop the high vfp registers
+	too. */
+	tst r14, #0x10
+	it eq
+	vldmiaeq r0!, {s16-s31}
+
+	msr psp, r0
+	isb
+	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
+		#if WORKAROUND_PMU_CM001 == 1
+			push { r14 }
+			pop { pc }
+		#endif
+	#endif
+
+	bx r14
+
+
+/*-----------------------------------------------------------*/
+
+vPortSVCHandler:
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr r1, [r3]
+	ldr r0, [r1]
+	/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+	msr psp, r0
+	isb
+	mov r0, #0
+	msr	basepri, r0
+	bx r14
+
+/*-----------------------------------------------------------*/
+
+vPortStartFirstTask
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Clear the bit that indicates the FPU is in use in case the FPU was used
+	before the scheduler was started - which would otherwise result in the
+	unnecessary leaving of space in the SVC stack for lazy saving of FPU
+	registers. */
+	mov r0, #0
+	msr control, r0
+	/* Call SVC to start the first task. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	svc 0
+
+/*-----------------------------------------------------------*/
+
+vPortEnableVFP:
+	/* The FPU enable bits are in the CPACR. */
+	ldr.w r0, =0xE000ED88
+	ldr	r1, [r0]
+
+	/* Enable CP10 and CP11 coprocessors, then save back. */
+	orr	r1, r1, #( 0xf << 20 )
+	str r1, [r0]
+	bx	r14
+
+
+
+	END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..3b44bc8
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h
@@ -0,0 +1,206 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* IAR includes. */
+    #include <intrinsics.h>
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
+/*-----------------------------------------------------------*/
+
+/* Compiler directives. */
+    #define portWEAK_SYMBOL    __attribute__( ( weak ) )
+
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+    #define portYIELD()                                 \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        __DSB();                                        \
+        __ISB();                                        \
+    }
+
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired != pdFALSE ) portYIELD()
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #endif
+
+    #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
+
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
+
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+
+    #define portDISABLE_INTERRUPTS()                           \
+    {                                                          \
+        __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
+        __DSB();                                               \
+        __ISB();                                               \
+    }
+
+    #define portENABLE_INTERRUPTS()                   __set_BASEPRI( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         __get_BASEPRI(); portDISABLE_INTERRUPTS()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    __set_BASEPRI( x )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
+
+/* portNOP() is not required by this port. */
+    #define portNOP()
+
+    #define portINLINE              __inline
+
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
+    #endif
+
+/*-----------------------------------------------------------*/
+
+    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        BaseType_t xReturn;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+        if( ulCurrentInterrupt == 0 )
+        {
+            xReturn = pdFALSE;
+        }
+        else
+        {
+            xReturn = pdTRUE;
+        }
+
+        return xReturn;
+    }
+
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+    #pragma diag_suppress=Pe191
+    #pragma diag_suppress=Pa082
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/port.c
new file mode 100644
index 0000000..56ff07c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/port.c
@@ -0,0 +1,771 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM4F MPU port.
+*----------------------------------------------------------*/
+
+/* IAR includes. */
+#include <intrinsics.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#ifndef __ARMVFP__
+    #error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
+    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG                 ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG        ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                        ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SHPR2_REG                        ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
+#define portNVIC_SYS_CTRL_STATE_REG               ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
+#define portNVIC_MEM_FAULT_ENABLE                 ( 1UL << 16UL )
+
+/* Constants required to access and manipulate the MPU. */
+#define portMPU_TYPE_REG                          ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_REGION_BASE_ADDRESS_REG           ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
+#define portMPU_REGION_ATTRIBUTE_REG              ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
+#define portMPU_CTRL_REG                          ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portEXPECTED_MPU_TYPE_VALUE               ( portTOTAL_NUM_REGIONS << 8UL )
+#define portMPU_ENABLE                            ( 0x01UL )
+#define portMPU_BACKGROUND_ENABLE                 ( 1UL << 2UL )
+#define portPRIVILEGED_EXECUTION_START_ADDRESS    ( 0UL )
+#define portMPU_REGION_VALID                      ( 0x10UL )
+#define portMPU_REGION_ENABLE                     ( 0x01UL )
+#define portPERIPHERALS_START_ADDRESS             0x40000000UL
+#define portPERIPHERALS_END_ADDRESS               0x5FFFFFFFUL
+
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT                  ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT               ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT           ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT                  ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT           ( 1UL << 25UL )
+
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
+ * r0p1 port. */
+#define portCPUID                                 ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID                     ( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID                     ( 0x410FC270UL )
+
+#define portNVIC_PENDSV_PRI                       ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI                      ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portNVIC_SVC_PRI                          ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER           ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16           ( 0xE000E3F0 )
+#define portAIRCR_REG                             ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE                       ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE                       ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS                     ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK                   ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                        ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK                       ( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR                                 ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS                  ( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                          ( 0x01000000 )
+#define portINITIAL_EXC_RETURN                    ( 0xfffffffd )
+#define portINITIAL_CONTROL_IF_UNPRIVILEGED       ( 0x03 )
+#define portINITIAL_CONTROL_IF_PRIVILEGED         ( 0x02 )
+
+/* Offsets in the stack to the parameters when inside the SVC handler. */
+#define portOFFSET_TO_PC                          ( 6 )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER                     ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#define portMISSED_COUNTS_FACTOR                  ( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK                    ( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Configure a number of standard MPU regions that are used by all tasks.
+ */
+static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the smallest MPU region size that a given number of bytes will fit
+ * into.  The region size is returned as the value that should be programmed
+ * into the region attribute register for that region.
+ */
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+extern void vPortStartFirstTask( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Turn the VFP on.
+ */
+extern void vPortEnableVFP( void );
+
+/*
+ * The C portion of the SVC handler.
+ */
+void vPortSVCHandler_C( uint32_t * pulParam );
+
+/*
+ * Called from the SVC handler used to start the scheduler.
+ */
+extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters,
+                                     BaseType_t xRunPrivileged )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+
+    /* Offset added to account for the way the MCU uses the stack on entry/exit
+     * of interrupts, and to ensure alignment. */
+    pxTopOfStack--;
+
+    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0;                                   /* LR */
+
+    /* Save code space by skipping register initialisation. */
+    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+    /* A save method is being used that requires each task to maintain its
+     * own exec return value. */
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+    pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    if( xRunPrivileged == pdTRUE )
+    {
+        *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
+    }
+    else
+    {
+        *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
+    }
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler_C( uint32_t * pulParam )
+{
+    uint8_t ucSVCNumber;
+    uint32_t ulPC;
+
+    #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+        extern uint32_t __syscalls_flash_start__[];
+        extern uint32_t __syscalls_flash_end__[];
+    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+
+    /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
+     * argument (r0) is pulParam[ 0 ]. */
+    ulPC = pulParam[ portOFFSET_TO_PC ];
+    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        case portSVC_START_SCHEDULER:
+            portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
+            vPortRestoreContextOfFirstTask();
+            break;
+
+        case portSVC_YIELD:
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+            /* Barriers are normally not required
+             * but do ensure the code is completely
+             * within the specified behaviour for the
+             * architecture. */
+            __asm volatile ( "dsb" ::: "memory" );
+            __asm volatile ( "isb" );
+
+            break;
+
+            #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+                case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
+                                               * svc was raised from any of the
+                                               * system calls. */
+
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        __asm volatile
+                        (
+                            "	mrs r1, control		\n"/* Obtain current control value. */
+                            "	bic r1, r1, #1		\n"/* Set privilege bit. */
+                            "	msr control, r1		\n"/* Write back new control value. */
+                            ::: "r1", "memory"
+                        );
+                    }
+
+                    break;
+            #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+                case portSVC_RAISE_PRIVILEGE:
+                    __asm volatile
+                    (
+                        "	mrs r1, control		\n"/* Obtain current control value. */
+                        "	bic r1, r1, #1		\n"/* Set privilege bit. */
+                        "	msr control, r1		\n"/* Write back new control value. */
+                        ::: "r1", "memory"
+                    );
+                    break;
+                    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+
+                default: /* Unknown SVC call. */
+                    break;
+    }
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+    /* This port can be used on all revisions of the Cortex-M7 core other than
+     * the r0p1 parts.  r0p1 parts should use the port from the
+     * /source/portable/GCC/ARM_CM7/r0p1 directory. */
+    configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+    configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+            volatile uint8_t ucMaxPriorityValue;
+
+            /* Determine the maximum priority from which ISR safe FreeRTOS API
+             * functions can be called.  ISR safe functions are those that end in
+             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+             * ensure interrupt entry is as fast and simple as possible.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+            /* Determine the number of priority bits available.  First write to all
+             * possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+            /* Use the same mask on the maximum system call priority. */
+            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+            /* Calculate the maximum acceptable priority group value for the number
+             * of bits read back. */
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+            {
+                ulMaxPRIGROUPValue--;
+                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+            }
+
+            #ifdef __NVIC_PRIO_BITS
+                {
+                    /* Check the CMSIS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+                }
+            #endif
+
+            #ifdef configPRIO_BITS
+                {
+                    /* Check the FreeRTOS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+                }
+            #endif
+
+            /* Shift the priority group value back to its position within the AIRCR
+             * register. */
+            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* conifgASSERT_DEFINED */
+
+    /* Make PendSV and SysTick the lowest priority interrupts. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Configure the regions in the MPU that are common to all tasks. */
+    prvSetupMPU();
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Ensure the VFP is enabled - it should be anyway. */
+    vPortEnableVFP();
+
+    /* Lazy save always. */
+    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+    /* Start the first task. */
+    vPortStartFirstTask();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+
+    vPortResetPrivilege( xRunningPrivileged );
+
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
+    if( uxCriticalNesting == 1 )
+    {
+        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    configASSERT( uxCriticalNesting );
+
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+
+    vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+     * executes all interrupts must be unmasked.  There is therefore no need to
+     * save and then restore the interrupt mask value as its value is already
+     * known. */
+    portDISABLE_INTERRUPTS();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* A context switch is required.  Context switching is performed in
+             * the PendSV interrupt.  Pend the PendSV interrupt. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__weak void vPortSetupTimerInterrupt( void )
+{
+    /* Stop and clear the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupMPU( void )
+{
+    extern uint32_t __privileged_functions_start__[];
+    extern uint32_t __privileged_functions_end__[];
+    extern uint32_t __FLASH_segment_start__[];
+    extern uint32_t __FLASH_segment_end__[];
+    extern uint32_t __privileged_data_start__[];
+    extern uint32_t __privileged_data_end__[];
+
+    /* The only permitted number of regions are 8 or 16. */
+    configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
+
+    /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
+    configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+
+    /* Check the expected MPU is present. */
+    if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+    {
+        /* First setup the unprivileged flash for unprivileged read only access. */
+        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
+                                          ( portMPU_REGION_VALID ) |
+                                          ( portUNPRIVILEGED_FLASH_REGION );
+
+        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
+                                       ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+                                       ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
+                                       ( portMPU_REGION_ENABLE );
+
+        /* Setup the privileged flash for privileged only access.  This is where
+         * the kernel code is placed. */
+        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
+                                          ( portMPU_REGION_VALID ) |
+                                          ( portPRIVILEGED_FLASH_REGION );
+
+        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
+                                       ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+                                       ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
+                                       ( portMPU_REGION_ENABLE );
+
+        /* Setup the privileged data RAM region.  This is where the kernel data
+         * is placed. */
+        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+                                          ( portMPU_REGION_VALID ) |
+                                          ( portPRIVILEGED_RAM_REGION );
+
+        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                                       ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+                                       prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+                                       ( portMPU_REGION_ENABLE );
+
+        /* By default allow everything to access the general peripherals.  The
+         * system peripherals and registers are protected. */
+        portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
+                                          ( portMPU_REGION_VALID ) |
+                                          ( portGENERAL_PERIPHERALS_REGION );
+
+        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
+                                       ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
+                                       ( portMPU_REGION_ENABLE );
+
+        /* Enable the memory fault exception. */
+        portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
+
+        /* Enable the MPU with the background region configured. */
+        portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+    }
+}
+/*-----------------------------------------------------------*/
+
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
+{
+    uint32_t ulRegionSize, ulReturnValue = 4;
+
+    /* 32 is the smallest region size, 31 is the largest valid value for
+     * ulReturnValue. */
+    for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
+    {
+        if( ulActualSizeInBytes <= ulRegionSize )
+        {
+            break;
+        }
+        else
+        {
+            ulReturnValue++;
+        }
+    }
+
+    /* Shift the code by one before returning so it can be written directly
+     * into the the correct bit position of the attribute register. */
+    return( ulReturnValue << 1UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                const struct xMEMORY_REGION * const xRegions,
+                                StackType_t * pxBottomOfStack,
+                                uint32_t ulStackDepth )
+{
+    extern uint32_t __SRAM_segment_start__[];
+    extern uint32_t __SRAM_segment_end__[];
+    extern uint32_t __privileged_data_start__[];
+    extern uint32_t __privileged_data_end__[];
+    int32_t lIndex;
+    uint32_t ul;
+
+    if( xRegions == NULL )
+    {
+        /* No MPU regions are specified so allow access to all RAM. */
+        xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+            ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
+            ( portMPU_REGION_VALID ) |
+            ( portSTACK_REGION );
+
+        xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+            ( portMPU_REGION_READ_WRITE ) |
+            ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+            ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
+            ( portMPU_REGION_ENABLE );
+
+        /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
+         * just removed the privileged only parameters. */
+        xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
+            ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+            ( portMPU_REGION_VALID ) |
+            ( portSTACK_REGION + 1 );
+
+        xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
+            ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+            ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+            prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+            ( portMPU_REGION_ENABLE );
+
+        /* Invalidate all other regions. */
+        for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+        {
+            xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+            xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+        }
+    }
+    else
+    {
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid.  At all other
+         * times the stack parameters will not be valid and it is assumed that the
+         * stack region has already been configured. */
+        if( ulStackDepth > 0 )
+        {
+            /* Define the region that allows access to the stack. */
+            xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+                ( ( uint32_t ) pxBottomOfStack ) |
+                ( portMPU_REGION_VALID ) |
+                ( portSTACK_REGION ); /* Region number. */
+
+            xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+                ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
+                ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+                ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+                ( portMPU_REGION_ENABLE );
+        }
+
+        lIndex = 0;
+
+        for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+        {
+            if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
+            {
+                /* Translate the generic region definition contained in
+                 * xRegions into the CM4 specific MPU settings that are then
+                 * stored in xMPUSettings. */
+                xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
+                    ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
+                    ( portMPU_REGION_VALID ) |
+                    ( portSTACK_REGION + ul ); /* Region number. */
+
+                xMPUSettings->xRegion[ ul ].ulRegionAttribute =
+                    ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
+                    ( xRegions[ lIndex ].ulParameters ) |
+                    ( portMPU_REGION_ENABLE );
+            }
+            else
+            {
+                /* Invalidate the region. */
+                xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+                xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+            }
+
+            lIndex++;
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+    void vPortValidateInterruptPriority( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        uint8_t ucCurrentPriority;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that	use the FreeRTOS API must not be left at their
+             * default priority of	zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and	therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
+
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredictable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portasm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portasm.s
new file mode 100644
index 0000000..e86f5dc
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portasm.s
@@ -0,0 +1,257 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+/* Including FreeRTOSConfig.h here will cause build errors if the header file
+contains code not understood by the assembler - for example the 'extern' keyword.
+To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
+the code is included in C files but excluded by the preprocessor in assembly
+files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
+#include <FreeRTOSConfig.h>
+
+	RSEG    CODE:CODE(2)
+	thumb
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+	EXTERN vPortSVCHandler_C
+
+	PUBLIC xPortPendSVHandler
+	PUBLIC vPortSVCHandler
+	PUBLIC vPortStartFirstTask
+	PUBLIC vPortEnableVFP
+	PUBLIC vPortRestoreContextOfFirstTask
+	PUBLIC xIsPrivileged
+	PUBLIC vResetPrivilege
+
+/*-----------------------------------------------------------*/
+
+xPortPendSVHandler:
+	mrs r0, psp
+	isb
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr	r2, [r3]
+
+	/* Is the task using the FPU context?  If so, push high vfp registers. */
+	tst r14, #0x10
+	it eq
+	vstmdbeq r0!, {s16-s31}
+
+	/* Save the core registers. */
+	mrs r1, control
+	stmdb r0!, {r1, r4-r11, r14}
+
+	/* Save the new top of stack into the first member of the TCB. */
+	str r0, [r2]
+
+	stmdb sp!, {r0, r3}
+	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	msr basepri, r0
+	dsb
+	isb
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r0, r3}
+
+	/* The first item in pxCurrentTCB is the task top of stack. */
+	ldr r1, [r3]
+	ldr r0, [r1]
+	/* Move onto the second item in the TCB... */
+	add r1, r1, #4
+
+	dmb					/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94	/* MPU_CTRL register. */
+	ldr r3, [r2]		/* Read the value of MPU_CTRL. */
+	bic r3, r3, #1		/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
+	str r3, [r2]		/* Disable MPU. */
+
+	/* Region Base Address register. */
+	ldr r2, =0xe000ed9c
+	/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+	ldmia r1!, {r4-r11}
+	/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+	stmia r2, {r4-r11}
+
+	#ifdef configTOTAL_MPU_REGIONS
+		#if ( configTOTAL_MPU_REGIONS == 16 )
+			/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
+			ldmia r1!, {r4-r11}
+			/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
+			stmia r2, {r4-r11}
+			/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
+			ldmia r1!, {r4-r11}
+			/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
+			stmia r2, {r4-r11}
+		#endif /* configTOTAL_MPU_REGIONS == 16. */
+	#endif /* configTOTAL_MPU_REGIONS */
+
+	ldr r2, =0xe000ed94	/* MPU_CTRL register. */
+	ldr r3, [r2]		/* Read the value of MPU_CTRL. */
+	orr r3, r3, #1		/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
+	str r3, [r2]		/* Enable MPU. */
+	dsb					/* Force memory writes before continuing. */
+
+	/* Pop the registers that are not automatically saved on exception entry. */
+	ldmia r0!, {r3-r11, r14}
+	msr control, r3
+
+	/* Is the task using the FPU context?  If so, pop the high vfp registers
+	too. */
+	tst r14, #0x10
+	it eq
+	vldmiaeq r0!, {s16-s31}
+
+	msr psp, r0
+	isb
+
+	bx r14
+
+
+/*-----------------------------------------------------------*/
+
+vPortSVCHandler:
+	#ifndef USE_PROCESS_STACK	/* Code should not be required if a main() is using the process stack. */
+		tst lr, #4
+		ite eq
+		mrseq r0, msp
+		mrsne r0, psp
+	#else
+		mrs r0, psp
+	#endif
+		b vPortSVCHandler_C
+
+/*-----------------------------------------------------------*/
+
+vPortStartFirstTask:
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Clear the bit that indicates the FPU is in use in case the FPU was used
+	before the scheduler was started - which would otherwise result in the
+	unnecessary leaving of space in the SVC stack for lazy saving of FPU
+	registers. */
+	mov r0, #0
+	msr control, r0
+	/* Call SVC to start the first task. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	svc 0
+
+/*-----------------------------------------------------------*/
+
+vPortRestoreContextOfFirstTask:
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Restore the context. */
+	ldr	r3, =pxCurrentTCB
+	ldr r1, [r3]
+	/* The first item in the TCB is the task top of stack. */
+	ldr r0, [r1]
+	/* Move onto the second item in the TCB... */
+	add r1, r1, #4
+
+	dmb					/* Complete outstanding transfers before disabling MPU. */
+	ldr r2, =0xe000ed94	/* MPU_CTRL register. */
+	ldr r3, [r2]		/* Read the value of MPU_CTRL. */
+	bic r3, r3, #1		/* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
+	str r3, [r2]		/* Disable MPU. */
+
+	/* Region Base Address register. */
+	ldr r2, =0xe000ed9c
+	/* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+	ldmia r1!, {r4-r11}
+	/* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+	stmia r2, {r4-r11}
+
+	#ifdef configTOTAL_MPU_REGIONS
+		#if ( configTOTAL_MPU_REGIONS == 16 )
+			/* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
+			ldmia r1!, {r4-r11}
+			/* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
+			stmia r2, {r4-r11}
+			/* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
+			ldmia r1!, {r4-r11}
+			/* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
+			stmia r2, {r4-r11}
+		#endif /* configTOTAL_MPU_REGIONS == 16. */
+	#endif /* configTOTAL_MPU_REGIONS */
+
+	ldr r2, =0xe000ed94	/* MPU_CTRL register. */
+	ldr r3, [r2]		/* Read the value of MPU_CTRL. */
+	orr r3, r3, #1		/* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
+	str r3, [r2]		/* Enable MPU. */
+	dsb					/* Force memory writes before continuing. */
+
+	/* Pop the registers that are not automatically saved on exception entry. */
+	ldmia r0!, {r3-r11, r14}
+	msr control, r3
+	/* Restore the task stack pointer. */
+	msr psp, r0
+	mov r0, #0
+	msr	basepri, r0
+	bx r14
+
+/*-----------------------------------------------------------*/
+
+vPortEnableVFP:
+	/* The FPU enable bits are in the CPACR. */
+	ldr.w r0, =0xE000ED88
+	ldr	r1, [r0]
+
+	/* Enable CP10 and CP11 coprocessors, then save back. */
+	orr	r1, r1, #( 0xf << 20 )
+	str r1, [r0]
+	bx	r14
+
+/*-----------------------------------------------------------*/
+
+xIsPrivileged:
+	mrs r0, control		/* r0 = CONTROL. */
+	tst r0, #1			/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+	ite ne
+	movne r0, #0		/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+	moveq r0, #1		/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+	bx lr				/* Return. */
+/*-----------------------------------------------------------*/
+
+vResetPrivilege:
+	mrs r0, control		/* r0 = CONTROL. */
+	orr r0, r0, #1		/* r0 = r0 | 1. */
+	msr control, r0		/* CONTROL = r0. */
+	bx lr				/* Return to the caller. */
+/*-----------------------------------------------------------*/
+
+	END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portmacro.h
new file mode 100644
index 0000000..d7cadbe
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portmacro.h
@@ -0,0 +1,356 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* IAR includes. */
+#include <intrinsics.h>
+
+/* Type definitions. */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
+
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
+
+#if ( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#else
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
+#endif
+/*-----------------------------------------------------------*/
+
+/* MPU specific constants. */
+#define portUSING_MPU_WRAPPERS                                   1
+#define portPRIVILEGE_BIT                                        ( 0x80000000UL )
+
+#define portMPU_REGION_READ_WRITE                                ( 0x03UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY                      ( 0x05UL << 24UL )
+#define portMPU_REGION_READ_ONLY                                 ( 0x06UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE                     ( 0x01UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY    ( 0x02UL << 24UL )
+#define portMPU_REGION_CACHEABLE_BUFFERABLE                      ( 0x07UL << 16UL )
+#define portMPU_REGION_EXECUTE_NEVER                             ( 0x01UL << 28UL )
+
+/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
+ * Register (RASR). */
+#define portMPU_RASR_TEX_S_C_B_LOCATION                          ( 16UL )
+#define portMPU_RASR_TEX_S_C_B_MASK                              ( 0x3FUL )
+
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+    /* Define to 8 for backward compatibility. */
+    #define configTOTAL_MPU_REGIONS    ( 8UL )
+#endif
+
+/*
+ * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
+ * memory type, and where necessary the cacheable and shareable properties
+ * of the memory region.
+ *
+ * The TEX, C, and B bits together indicate the memory type of the region,
+ * and:
+ * - For Normal memory, the cacheable properties of the region.
+ * - For Device memory, whether the region is shareable.
+ *
+ * For Normal memory regions, the S bit indicates whether the region is
+ * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
+ *
+ * See the following two tables for setting TEX, S, C and B bits for
+ * unprivileged flash, privileged flash and privileged RAM regions.
+ *
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | TEX | C | B | Memory type            |  Description or Normal region cacheability             |  Shareable?             |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 0 | 0 | Strongly-ordered       |  Strongly ordered                                      |  Shareable              |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 0 | 1 | Device                 |  Shared device                                         |  Shareable              |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 1 | 0 | Normal                 |  Outer and inner   write-through; no write allocate    |  S bit                  |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 1 | 1 | Normal                 |  Outer and inner   write-back; no write allocate       |  S bit                  |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 0 | 0 | Normal                 |  Outer and inner   Non-cacheable                       |  S bit                  |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 0 | 1 | Reserved               |  Reserved                                              |  Reserved               |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 1 | 0 | IMPLEMENTATION DEFINED |  IMPLEMENTATION DEFINED                                |  IMPLEMENTATION DEFINED |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 1 | 1 | Normal                 |  Outer and inner   write-back; write and read allocate |  S bit                  |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 0 | 0 | Device                 |  Non-shared device                                     |  Not shareable          |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 0 | 1 | Reserved               |  Reserved                                              |  Reserved               |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 1 | X | Reserved               |  Reserved                                              |  Reserved               |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 011 | X | X | Reserved               |  Reserved                                              |  Reserved               |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 1BB | A | A | Normal                 | Cached memory, with AA and BB indicating the inner and |  Reserved               |
+ |     |   |   |                        | outer cacheability rules that must be exported on the  |                         |
+ |     |   |   |                        | bus. See the table below for the cacheability policy   |                         |
+ |     |   |   |                        | encoding. memory, BB=Outer policy, AA=Inner policy.    |                         |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ |
+ +-----------------------------------------+----------------------------------------+
+ | AA or BB subfield of {TEX,C,B} encoding |  Cacheability policy                   |
+ +-----------------------------------------+----------------------------------------+
+ | 00                                      |  Non-cacheable                         |
+ +-----------------------------------------+----------------------------------------+
+ | 01                                      |  Write-back, write and   read allocate |
+ +-----------------------------------------+----------------------------------------+
+ | 10                                      |  Write-through, no write   allocate    |
+ +-----------------------------------------+----------------------------------------+
+ | 11                                      |  Write-back, no write   allocate       |
+ +-----------------------------------------+----------------------------------------+
+ */
+
+/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for flash
+ * region. */
+#ifndef configTEX_S_C_B_FLASH
+    /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
+    #define configTEX_S_C_B_FLASH    ( 0x07UL )
+#endif
+
+/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for RAM
+ * region. */
+#ifndef configTEX_S_C_B_SRAM
+    /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
+    #define configTEX_S_C_B_SRAM          ( 0x07UL )
+#endif
+
+#define portUNPRIVILEGED_FLASH_REGION     ( 0UL )
+#define portPRIVILEGED_FLASH_REGION       ( 1UL )
+#define portPRIVILEGED_RAM_REGION         ( 2UL )
+#define portGENERAL_PERIPHERALS_REGION    ( 3UL )
+#define portSTACK_REGION                  ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION     ( 5UL )
+#define portTOTAL_NUM_REGIONS             ( configTOTAL_MPU_REGIONS )
+#define portNUM_CONFIGURABLE_REGIONS      ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
+#define portLAST_CONFIGURABLE_REGION      ( portTOTAL_NUM_REGIONS - 1UL )
+
+#define portSWITCH_TO_USER_MODE()    __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" )
+
+typedef struct MPU_REGION_REGISTERS
+{
+    uint32_t ulRegionBaseAddress;
+    uint32_t ulRegionAttribute;
+} xMPU_REGION_REGISTERS;
+
+/* Plus 1 to create space for the stack region. */
+typedef struct MPU_SETTINGS
+{
+    xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
+} xMPU_SETTINGS;
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    8
+/*-----------------------------------------------------------*/
+
+/* SVC numbers for various services. */
+#define portSVC_START_SCHEDULER    0
+#define portSVC_YIELD              1
+#define portSVC_RAISE_PRIVILEGE    2
+
+/* Scheduler utilities. */
+
+#define portYIELD()    __asm volatile ( "	SVC	%0	\n"::"i" ( portSVC_YIELD ) : "memory" )
+#define portYIELD_WITHIN_API()                          \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        __DSB();                                        \
+        __ISB();                                        \
+    }
+
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API()
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+#endif
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
+
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()                               \
+    {                                                          \
+        __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
+        __DSB();                                               \
+        __ISB();                                               \
+    }
+
+#define portENABLE_INTERRUPTS()                   __set_BASEPRI( 0 )
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()         __get_BASEPRI(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    __set_BASEPRI( x )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+    void vPortValidateInterruptPriority( void );
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE              __inline
+
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
+#endif
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. */
+    __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+    if( ulCurrentInterrupt == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+
+
+/*-----------------------------------------------------------*/
+
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ */
+#define portRAISE_PRIVILEGE()    __asm volatile ( "svc %0 \n" ::"i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE()    vResetPrivilege()
+/*-----------------------------------------------------------*/
+
+#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
+    #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
+    #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY    0
+#endif
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+#pragma diag_suppress=Pe191
+#pragma diag_suppress=Pa082
+#pragma diag_suppress=Be006
+/*-----------------------------------------------------------*/
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM7/ReadMe.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM7/ReadMe.txt
new file mode 100644
index 0000000..2116456
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM7/ReadMe.txt
@@ -0,0 +1,18 @@
+There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.
+The best option depends on the revision of the ARM Cortex-M7 core in use.  The
+revision is specified by an 'r' number, and a 'p' number, so will look something
+like 'r0p1'.  Check the documentation for the microcontroller in use to find the 
+revision of the Cortex-M7 core used in that microcontroller.  If in doubt, use 
+the FreeRTOS port provided specifically for r0p1 revisions, as that can be used
+with all core revisions.
+
+The first option is to use the ARM Cortex-M4F port, and the second option is to
+use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.
+
+If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be
+used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in 
+the /FreeRTOS/Source/portable/IAR/ARM_CM4F directory.
+
+If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM
+Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1
+directory.
\ No newline at end of file
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/port.c
new file mode 100644
index 0000000..9dbec79
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/port.c
@@ -0,0 +1,633 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM7 port.
+*----------------------------------------------------------*/
+
+/* IAR includes. */
+#include <intrinsics.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __ARMVFP__
+    #error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#if ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
+    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
+#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                    ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK                   ( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR                             ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS              ( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                      ( 0x01000000 )
+#define portINITIAL_EXC_RETURN                ( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#define portMISSED_COUNTS_FACTOR              ( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortSysTickHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Turn the VFP on.
+ */
+extern void vPortEnableVFP( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+
+    /* Offset added to account for the way the MCU uses the stack on entry/exit
+     * of interrupts, and to ensure alignment. */
+    pxTopOfStack--;
+
+    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) prvTaskExitError;                    /* LR */
+
+    /* Save code space by skipping register initialisation. */
+    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+    /* A save method is being used that requires each task to maintain its
+     * own exec return value. */
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+    pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( uxCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    for( ; ; )
+    {
+    }
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+            volatile uint8_t ucMaxPriorityValue;
+
+            /* Determine the maximum priority from which ISR safe FreeRTOS API
+             * functions can be called.  ISR safe functions are those that end in
+             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+             * ensure interrupt entry is as fast and simple as possible.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+            /* Determine the number of priority bits available.  First write to all
+             * possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+            /* Use the same mask on the maximum system call priority. */
+            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+            /* Calculate the maximum acceptable priority group value for the number
+             * of bits read back. */
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+            {
+                ulMaxPRIGROUPValue--;
+                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+            }
+
+            #ifdef __NVIC_PRIO_BITS
+                {
+                    /* Check the CMSIS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+                }
+            #endif
+
+            #ifdef configPRIO_BITS
+                {
+                    /* Check the FreeRTOS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+                }
+            #endif
+
+            /* Shift the priority group value back to its position within the AIRCR
+             * register. */
+            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* conifgASSERT_DEFINED */
+
+    /* Make PendSV and SysTick the lowest priority interrupts. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Ensure the VFP is enabled - it should be anyway. */
+    vPortEnableVFP();
+
+    /* Lazy save always. */
+    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+    /* Start the first task. */
+    vPortStartFirstTask();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
+    if( uxCriticalNesting == 1 )
+    {
+        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+     * executes all interrupts must be unmasked.  There is therefore no need to
+     * save and then restore the interrupt mask value as its value is already
+     * known. */
+    portDISABLE_INTERRUPTS();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* A context switch is required.  Context switching is performed in
+             * the PendSV interrupt.  Pend the PendSV interrupt. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+    __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+         * is accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods.  -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __disable_interrupt();
+        __DSB();
+        __ISB();
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above __disable_interrupt()
+             * call above. */
+            __enable_interrupt();
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again.  However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __DSB();
+                __WFI();
+                __ISB();
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately.  see comments above
+             * __disable_interrupt() call above. */
+            __enable_interrupt();
+            __DSB();
+            __ISB();
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __disable_interrupt();
+            __DSB();
+            __ISB();
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is yet
+             * to count to zero (in which case an interrupt other than the SysTick
+             * must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __enable_interrupt();
+        }
+    }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__weak void vPortSetupTimerInterrupt( void )
+{
+    /* Calculate the constants required to configure the tick interrupt. */
+    #if ( configUSE_TICKLESS_IDLE == 1 )
+        {
+            ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+        }
+    #endif /* configUSE_TICKLESS_IDLE */
+
+    /* Stop and clear the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+    void vPortValidateInterruptPriority( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        uint8_t ucCurrentPriority;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that	use the FreeRTOS API must not be left at their
+             * default priority of	zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and	therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
+
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredictable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
+
+#endif /* configASSERT_DEFINED */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portasm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
new file mode 100644
index 0000000..786e0c9
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
@@ -0,0 +1,151 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include <FreeRTOSConfig.h>
+
+	RSEG    CODE:CODE(2)
+	thumb
+
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+
+	PUBLIC xPortPendSVHandler
+	PUBLIC vPortSVCHandler
+	PUBLIC vPortStartFirstTask
+	PUBLIC vPortEnableVFP
+
+
+/*-----------------------------------------------------------*/
+
+xPortPendSVHandler:
+	mrs r0, psp
+	isb
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr	r2, [r3]
+
+	/* Is the task using the FPU context?  If so, push high vfp registers. */
+	tst r14, #0x10
+	it eq
+	vstmdbeq r0!, {s16-s31}
+
+	/* Save the core registers. */
+	stmdb r0!, {r4-r11, r14}
+
+	/* Save the new top of stack into the first member of the TCB. */
+	str r0, [r2]
+
+	stmdb sp!, {r0, r3}
+	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+	cpsid i
+	msr basepri, r0
+	dsb
+	isb
+	cpsie i
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r0, r3}
+
+	/* The first item in pxCurrentTCB is the task top of stack. */
+	ldr r1, [r3]
+	ldr r0, [r1]
+
+	/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+
+	/* Is the task using the FPU context?  If so, pop the high vfp registers
+	too. */
+	tst r14, #0x10
+	it eq
+	vldmiaeq r0!, {s16-s31}
+
+	msr psp, r0
+	isb
+	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
+		#if WORKAROUND_PMU_CM001 == 1
+			push { r14 }
+			pop { pc }
+		#endif
+	#endif
+
+	bx r14
+
+
+/*-----------------------------------------------------------*/
+
+vPortSVCHandler:
+	/* Get the location of the current TCB. */
+	ldr	r3, =pxCurrentTCB
+	ldr r1, [r3]
+	ldr r0, [r1]
+	/* Pop the core registers. */
+	ldmia r0!, {r4-r11, r14}
+	msr psp, r0
+	isb
+	mov r0, #0
+	msr	basepri, r0
+	bx r14
+
+/*-----------------------------------------------------------*/
+
+vPortStartFirstTask
+	/* Use the NVIC offset register to locate the stack. */
+	ldr r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+	/* Set the msp back to the start of the stack. */
+	msr msp, r0
+	/* Clear the bit that indicates the FPU is in use in case the FPU was used
+	before the scheduler was started - which would otherwise result in the
+	unnecessary leaving of space in the SVC stack for lazy saving of FPU
+	registers. */
+	mov r0, #0
+	msr control, r0
+	/* Call SVC to start the first task. */
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	svc 0
+
+/*-----------------------------------------------------------*/
+
+vPortEnableVFP:
+	/* The FPU enable bits are in the CPACR. */
+	ldr.w r0, =0xE000ED88
+	ldr	r1, [r0]
+
+	/* Enable CP10 and CP11 coprocessors, then save back. */
+	orr	r1, r1, #( 0xf << 20 )
+	str r1, [r0]
+	bx	r14
+
+
+
+	END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
new file mode 100644
index 0000000..ed86473
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
@@ -0,0 +1,209 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* IAR includes. */
+    #include <intrinsics.h>
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
+/*-----------------------------------------------------------*/
+
+/* Compiler directives. */
+    #define portWEAK_SYMBOL    __attribute__( ( weak ) )
+
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+    #define portYIELD()                                 \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+        __DSB();                                        \
+        __ISB();                                        \
+    }
+
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired != pdFALSE ) portYIELD()
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #endif
+
+    #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
+
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
+
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+
+    #define portDISABLE_INTERRUPTS()                           \
+    {                                                          \
+        /* Errata work around. */                              \
+        __disable_interrupt();                                 \
+        __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY ); \
+        __DSB();                                               \
+        __ISB();                                               \
+        __enable_interrupt();                                  \
+    }
+
+    #define portENABLE_INTERRUPTS()                   __set_BASEPRI( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         __get_BASEPRI(); portDISABLE_INTERRUPTS()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    __set_BASEPRI( x )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
+
+/* portNOP() is not required by this port. */
+    #define portNOP()
+
+    #define portINLINE              __inline
+
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE    inline __attribute__( ( always_inline ) )
+    #endif
+
+/*-----------------------------------------------------------*/
+
+    portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        BaseType_t xReturn;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm volatile ( "mrs %0, ipsr" : "=r" ( ulCurrentInterrupt )::"memory" );
+
+        if( ulCurrentInterrupt == 0 )
+        {
+            xReturn = pdFALSE;
+        }
+        else
+        {
+            xReturn = pdTRUE;
+        }
+
+        return xReturn;
+    }
+
+/*-----------------------------------------------------------*/
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+ * the source code because to do so would cause other compilers to generate
+ * warnings. */
+    #pragma diag_suppress=Pe191
+    #pragma diag_suppress=Pa082
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/port.c
new file mode 100644
index 0000000..abcc155
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/port.c
@@ -0,0 +1,316 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifndef configSETUP_TICK_INTERRUPT
+	#error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.
+#endif
+
+#ifndef configCLEAR_TICK_INTERRUPT
+	#error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created.  A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS			( 0x01UL )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK			( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+mode. */
+#define portAPSR_USER_MODE				( 0x10 )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.  This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts.  As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
+a floating point context must be saved and restored for the task. */
+volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+volatile uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth.  A context switch is only performed if
+if the nesting depth is 0. */
+volatile uint32_t ulPortInterruptNesting = 0UL;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro.
+
+	The fist real value on the stack is the status register, which is set for
+	system mode, with interrupts enabled.  A few NULLs are added first to ensure
+	GDB does not try decoding a non-existent return address. */
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+	{
+		/* The task will start in THUMB mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* Next the return address, which in this case is the start of the task. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	/* Next all the registers other than the stack pointer. */
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The task will start with a critical nesting count of 0 as interrupts are
+	enabled. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+	pxTopOfStack--;
+
+	/* The task will start without a floating point context.  A task that uses
+	the floating point hardware must call vPortTaskUsesFPU() before executing
+	any floating point instructions. */
+	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( ulPortInterruptNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+	/* Only continue if the CPU is not in User mode.  The CPU must be in a
+	Privileged mode for the scheduler to start. */
+	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
+	ulAPSR &= portAPSR_MODE_BITS_MASK;
+	configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+	if( ulAPSR != portAPSR_USER_MODE )
+	{
+		/* Start the timer that generates the tick ISR. */
+		portDISABLE_INTERRUPTS();
+		configSETUP_TICK_INTERRUPT();
+
+		/* Start the first task executing. */
+		vPortRestoreTaskContext();
+	}
+
+	/* Will only get here if vTaskStartScheduler() was called with the CPU in
+	a non-privileged mode or the binary point register was not set to its lowest
+	possible value.  prvTaskExitError() is referenced to prevent a compiler
+	warning about it being defined but not referenced in the case that the user
+	defines their own exit address. */
+	( void ) prvTaskExitError;
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( ulCriticalNesting == 1 )
+	{
+		configASSERT( ulPortInterruptNesting == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as the critical section is being
+		exited. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then all interrupt
+		priorities must be re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Critical nesting has reached zero so all interrupt priorities
+			should be unmasked. */
+			portENABLE_INTERRUPTS();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+uint32_t ulInterruptStatus;
+
+	ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+
+	/* Increment the RTOS tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		ulPortYieldRequired = pdTRUE;
+	}
+
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus );
+
+	configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+uint32_t ulInitialFPSCR = 0;
+
+	/* A task is registering the fact that it needs an FPU context.  Set the
+	FPU flag (which is saved as part of the task context). */
+	ulPortTaskHasFPUContext = pdTRUE;
+
+	/* Initialise the floating point status register. */
+	__asm volatile ( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) );
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s
new file mode 100644
index 0000000..3c9f0f8
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s
@@ -0,0 +1,247 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+#include "FreeRTOSConfig.h"
+
+	SECTION .text:CODE:ROOT(2)
+	arm
+
+	/* Variables and functions. */
+	EXTERN pxCurrentTCB
+	EXTERN vTaskSwitchContext
+	EXTERN vApplicationIRQHandler
+	EXTERN ulPortInterruptNesting
+	EXTERN ulPortTaskHasFPUContext
+	EXTERN ulPortYieldRequired
+	EXTERN ulCriticalNesting
+
+	PUBLIC FreeRTOS_IRQ_Handler
+	PUBLIC FreeRTOS_SVC_Handler
+	PUBLIC vPortRestoreTaskContext
+
+SYS_MODE			EQU		0x1f
+SVC_MODE			EQU		0x13
+IRQ_MODE			EQU		0x12
+
+portSAVE_CONTEXT MACRO
+
+	/* Save the LR and SPSR onto the system mode stack before switching to
+	system mode to save the remaining system mode registers. */
+	SRSDB	sp!, #SYS_MODE
+	CPS		#SYS_MODE
+	PUSH	{R0-R12, R14}
+
+	/* Push the critical nesting count. */
+	LDR		R2, =ulCriticalNesting
+	LDR		R1, [R2]
+	PUSH	{R1}
+
+	/* Does the task have a floating point context that needs saving?  If
+	ulPortTaskHasFPUContext is 0 then no. */
+	LDR		R2, =ulPortTaskHasFPUContext
+	LDR		R3, [R2]
+	CMP		R3, #0
+
+	/* Save the floating point context, if any. */
+	FMRXNE  R1,  FPSCR
+	VPUSHNE {D0-D15}
+#if configFPU_D32 == 1
+	VPUSHNE	{D16-D31}
+#endif /* configFPU_D32 */
+	PUSHNE	{R1}
+
+	/* Save ulPortTaskHasFPUContext itself. */
+	PUSH	{R3}
+
+	/* Save the stack pointer in the TCB. */
+	LDR		R0, =pxCurrentTCB
+	LDR		R1, [R0]
+	STR		SP, [R1]
+
+	ENDM
+
+; /**********************************************************************/
+
+portRESTORE_CONTEXT MACRO
+
+	/* Set the SP to point to the stack of the task being restored. */
+	LDR		R0, =pxCurrentTCB
+	LDR		R1, [R0]
+	LDR		SP, [R1]
+
+	/* Is there a floating point context to restore?  If the restored
+	ulPortTaskHasFPUContext is zero then no. */
+	LDR		R0, =ulPortTaskHasFPUContext
+	POP		{R1}
+	STR		R1, [R0]
+	CMP		R1, #0
+
+	/* Restore the floating point context, if any. */
+	POPNE 	{R0}
+#if configFPU_D32 == 1
+	VPOPNE	{D16-D31}
+#endif /* configFPU_D32 */
+	VPOPNE	{D0-D15}
+	VMSRNE  FPSCR, R0
+
+	/* Restore the critical section nesting depth. */
+	LDR		R0, =ulCriticalNesting
+	POP		{R1}
+	STR		R1, [R0]
+
+	/* Restore all system mode registers other than the SP (which is already
+	being used). */
+	POP		{R0-R12, R14}
+
+	/* Return to the task code, loading CPSR on the way. */
+	RFEIA	sp!
+
+	ENDM
+
+
+
+
+/******************************************************************************
+ * SVC handler is used to yield.
+ *****************************************************************************/
+FreeRTOS_SVC_Handler:
+	/* Save the context of the current task and select a new task to run. */
+	portSAVE_CONTEXT
+	LDR R0, =vTaskSwitchContext
+	BLX	R0
+	portRESTORE_CONTEXT
+
+
+/******************************************************************************
+ * vPortRestoreTaskContext is used to start the scheduler.
+ *****************************************************************************/
+vPortRestoreTaskContext:
+	/* Switch to system mode. */
+	CPS		#SYS_MODE
+	portRESTORE_CONTEXT
+
+FreeRTOS_IRQ_Handler:
+	/* Return to the interrupted instruction. */
+	SUB		lr, lr, #4
+
+	/* Push the return address and SPSR. */
+	PUSH	{lr}
+	MRS		lr, SPSR
+	PUSH	{lr}
+
+	/* Change to supervisor mode to allow reentry. */
+	CPS		#SVC_MODE
+
+	/* Push used registers. */
+	PUSH	{r0-r3, r12}
+
+	/* Increment nesting count.  r3 holds the address of ulPortInterruptNesting
+	for future use.  r1 holds the original ulPortInterruptNesting value for
+	future use. */
+	LDR		r3, =ulPortInterruptNesting
+	LDR		r1, [r3]
+	ADD		r0, r1, #1
+	STR		r0, [r3]
+
+	/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
+	future use. */
+	MOV		r0, sp
+	AND		r2, r0, #4
+	SUB		sp, sp, r2
+
+	/* Call the interrupt handler. */
+	PUSH	{r0-r3, lr}
+	LDR		r1, =vApplicationIRQHandler
+	BLX		r1
+	POP		{r0-r3, lr}
+	ADD		sp, sp, r2
+
+	CPSID	i
+	DSB
+	ISB
+
+	/* Write to the EOI register. */
+	LDR 	r2, =configEOI_ADDRESS
+	STR		r0, [r2]
+
+	/* Restore the old nesting count. */
+	STR		r1, [r3]
+
+	/* A context switch is never performed if the nesting count is not 0. */
+	CMP		r1, #0
+	BNE		exit_without_switch
+
+	/* Did the interrupt request a context switch?  r1 holds the address of
+	ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+	use. */
+	LDR		r1, =ulPortYieldRequired
+	LDR		r0, [r1]
+	CMP		r0, #0
+	BNE		switch_before_exit
+
+exit_without_switch:
+	/* No context switch.  Restore used registers, LR_irq and SPSR before
+	returning. */
+	POP		{r0-r3, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	MOVS	PC, LR
+
+switch_before_exit:
+	/* A context swtich is to be performed.  Clear the context switch pending
+	flag. */
+	MOV		r0, #0
+	STR		r0, [r1]
+
+	/* Restore used registers, LR-irq and SPSR before saving the context
+	to the task stack. */
+	POP		{r0-r3, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	portSAVE_CONTEXT
+
+	/* Call the function that selects the new task to execute.
+	vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+	instructions, or 8 byte aligned stack allocated data.  LR does not need
+	saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
+	LDR		R0, =vTaskSwitchContext
+	BLX		R0
+
+	/* Restore the context of, and branch to, the task selected to execute
+	next. */
+	portRESTORE_CONTEXT
+
+	END
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h
new file mode 100644
index 0000000..32f9397
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h
@@ -0,0 +1,181 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include <intrinsics.h>
+
+#ifdef __cplusplus
+	extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+typedef uint32_t TickType_t;
+#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{												\
+extern volatile uint32_t ulPortYieldRequired;	\
+												\
+	if( xSwitchRequired != pdFALSE )			\
+	{											\
+		ulPortYieldRequired = pdTRUE;			\
+	}											\
+}
+
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm volatile ( "SWI 0		\n"				\
+									 "ISB		  " );
+
+
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+extern void vPortInstallFreeRTOSVectorTable( void );
+
+/* The I bit within the CPSR. */
+#define portINTERRUPT_ENABLE_BIT	( 1 << 7 )
+
+/* In the absence of a priority mask register, these functions and macros
+globally enable and disable interrupts. */
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+#define portENABLE_INTERRUPTS()		__asm volatile ( "CPSIE i 	\n"	);
+#define portDISABLE_INTERRUPTS()	__asm volatile ( "CPSID i 	\n"		\
+													 "DSB		\n"		\
+													 "ISB		  " );
+#pragma inline
+static inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
+{
+volatile uint32_t ulCPSR;
+
+	__asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) );
+	ulCPSR &= portINTERRUPT_ENABLE_BIT;
+	portDISABLE_INTERRUPTS();
+	return ulCPSR;
+}
+
+#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	if( x == 0 ) portENABLE_INTERRUPTS()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __CLZ( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#define portNOP() __asm volatile( "NOP" )
+#define portINLINE inline
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+the source code because to do so would cause other compilers to generate
+warnings. */
+#pragma diag_suppress=Pe191
+#pragma diag_suppress=Pa082
+
+#ifdef __cplusplus
+	} /* extern C */
+#endif
+
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ATMega323/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ATMega323/port.c
new file mode 100644
index 0000000..d04a293
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ATMega323/port.c
@@ -0,0 +1,339 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include <stdlib.h>
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the AVR/IAR port.
+ *----------------------------------------------------------*/
+
+/* Start tasks with interrupts enables. */
+#define portFLAGS_INT_ENABLED					( ( StackType_t ) 0x80 )
+
+/* Hardware constants for timer 1. */
+#define portCLEAR_COUNTER_ON_MATCH				( ( uint8_t ) 0x08 )
+#define portPRESCALE_64							( ( uint8_t ) 0x03 )
+#define portCLOCK_PRESCALER						( ( uint32_t ) 64 )
+#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE	( ( uint8_t ) 0x10 )
+
+/* The number of bytes used on the hardware stack by the task start address. */
+#define portBYTES_USED_BY_RETURN_ADDRESS		( 2 )
+/*-----------------------------------------------------------*/
+
+/* Stores the critical section nesting.  This must not be initialised to 0.
+It will be initialised when a task starts. */
+#define portNO_CRITICAL_NESTING					( ( UBaseType_t ) 0 )
+UBaseType_t uxCriticalNesting = 0x50;
+
+
+/*
+ * Perform hardware setup to enable ticks from timer 1, compare match A.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The IAR compiler does not have full support for inline assembler, so
+ * these are defined in the portmacro assembler file.
+ */
+extern void vPortYieldFromTick( void );
+extern void vPortStart( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint16_t usAddress;
+StackType_t *pxTopOfHardwareStack;
+
+	/* Place a few bytes of known values on the bottom of the stack.
+	This is just useful for debugging. */
+
+	*pxTopOfStack = 0x11;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack--;
+
+	/* Remember where the top of the hardware stack is - this is required
+	below. */
+	pxTopOfHardwareStack = pxTopOfStack;
+
+
+	/* Simulate how the stack would look after a call to vPortYield(). */
+
+	/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+
+
+
+	/* The IAR compiler requires two stacks per task.  First there is the
+	hardware call stack which uses the AVR stack pointer.  Second there is the
+	software stack (local variables, parameter passing, etc.) which uses the
+	AVR Y register.
+
+	This function places both stacks within the memory block passed in as the
+	first parameter.  The hardware stack is placed at the bottom of the memory
+	block.  A gap is then left for the hardware stack to grow.  Next the software
+	stack is placed.  The amount of space between the software and hardware
+	stacks is defined by configCALL_STACK_SIZE.
+
+
+
+	The first part of the stack is the hardware stack.  Place the start
+	address of the task on the hardware stack. */
+	usAddress = ( uint16_t ) pxCode;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+	usAddress >>= 8;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+
+	/* Leave enough space for the hardware stack before starting the software
+	stack.  The '- 2' is because we have already used two spaces for the
+	address of the start of the task. */
+	pxTopOfStack -= ( configCALL_STACK_SIZE - 2 );
+
+
+
+	/* Next simulate the stack as if after a call to portSAVE_CONTEXT().
+	portSAVE_CONTEXT places the flags on the stack immediately after r0
+	to ensure the interrupts get disabled as soon as possible, and so ensuring
+	the stack use is minimal should a context switch interrupt occur. */
+	*pxTopOfStack = ( StackType_t ) 0x00;	/* R0 */
+	pxTopOfStack--;
+	*pxTopOfStack = portFLAGS_INT_ENABLED;
+	pxTopOfStack--;
+
+	/* Next place the address of the hardware stack.  This is required so
+	the AVR stack pointer can be restored to point to the hardware stack. */
+	pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS;
+	usAddress = ( uint16_t ) pxTopOfHardwareStack;
+
+	/* SPL */
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+	/* SPH */
+	usAddress >>= 8;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+
+
+
+	/* Now the remaining registers. */
+	*pxTopOfStack = ( StackType_t ) 0x01;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x02;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x05;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x13;	/* R13 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x14;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x15;	/* R15 */
+	pxTopOfStack--;
+
+	/* Place the parameter on the stack in the expected location. */
+	usAddress = ( uint16_t ) pvParameters;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+	usAddress >>= 8;
+	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0x18;	/* R18 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x19;	/* R19 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x20;	/* R20 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x21;	/* R21 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x22;	/* R22 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x23;	/* R23 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x24;	/* R24 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x25;	/* R25 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x26;	/* R26 X */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x27;	/* R27 */
+	pxTopOfStack--;
+
+	/* The Y register is not stored as it is used as the software stack and
+	gets saved into the task control block. */
+
+	*pxTopOfStack = ( StackType_t ) 0x30;	/* R30 Z */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x031;	/* R31 */
+
+	pxTopOfStack--;
+	*pxTopOfStack = portNO_CRITICAL_NESTING;	/* Critical nesting is zero when the task starts. */
+
+	/*lint +e950 +e611 +e923 */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run.
+	Normally we would just call portRESTORE_CONTEXT() here, but as the IAR
+	compiler does not fully support inline assembler we have to make a call.*/
+	vPortStart();
+
+	/* Should not get here! */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the AVR port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup timer 1 compare match A to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+uint8_t ucHighByte, ucLowByte;
+
+	/* Using 16bit timer 1 to generate the tick.  Correct fuses must be
+	selected for the configCPU_CLOCK_HZ clock. */
+
+	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+	/* We only have 16 bits so have to scale to get our required tick rate. */
+	ulCompareMatch /= portCLOCK_PRESCALER;
+
+	/* Adjust for correct value. */
+	ulCompareMatch -= ( uint32_t ) 1;
+
+	/* Setup compare match value for compare match A.  Interrupts are disabled
+	before this is called so we need not worry here. */
+	ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+	ulCompareMatch >>= 8;
+	ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+	OCR1AH = ucHighByte;
+	OCR1AL = ucLowByte;
+
+	/* Setup clock source and compare match behaviour. */
+	ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64;
+	TCCR1B = ucLowByte;
+
+	/* Enable the interrupt - this is okay as interrupt are currently globally
+	disabled. */
+	TIMSK |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 1
+
+	/*
+	 * Tick ISR for preemptive scheduler.  We can use a __task attribute as
+	 * the context is saved at the start of vPortYieldFromTick().  The tick
+	 * count is incremented after the context is saved.
+	 */
+	__task void SIG_OUTPUT_COMPARE1A( void )
+	{
+		vPortYieldFromTick();
+		asm( "reti" );
+	}
+
+#else
+
+	/*
+	 * Tick ISR for the cooperative scheduler.  All this does is increment the
+	 * tick count.  We don't need to switch context, this can only be done by
+	 * manual calls to taskYIELD();
+	 *
+	 * THE INTERRUPT VECTOR IS POPULATED IN portmacro.s90.  DO NOT INSTALL
+	 * IT HERE USING THE USUAL PRAGMA.
+	 */
+	__interrupt void SIG_OUTPUT_COMPARE1A( void )
+	{
+		xTaskIncrementTick();
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	uxCriticalNesting--;
+	if( uxCriticalNesting == portNO_CRITICAL_NESTING )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.h
new file mode 100644
index 0000000..97695e2
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.h
@@ -0,0 +1,112 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V1.2.3
+
+	+ portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it
+	  base 16.
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint8_t
+#define portBASE_TYPE	char
+#define portPOINTER_SIZE_TYPE uint16_t
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portENTER_CRITICAL()	vPortEnterCritical()
+#define portEXIT_CRITICAL()		vPortExitCritical()
+
+#define portDISABLE_INTERRUPTS()	asm( "cli" )
+#define portENABLE_INTERRUPTS()		asm( "sei" )
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			1
+#define portNOP()					asm( "nop" )
+/*-----------------------------------------------------------*/
+
+/* Kernel utilities. */
+void vPortYield( void );
+#define portYIELD()	vPortYield()
+
+#ifdef IAR_MEGA_AVR
+	#define outb( PORT, VALUE ) PORT = VALUE
+#endif
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.s90 b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.s90
new file mode 100644
index 0000000..35f5828
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.s90
@@ -0,0 +1,245 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+#include <iom323.h>
+
+; Declare all extern symbols here - including any ISRs that are referenced in
+; the vector table.
+
+; ISR functions
+; -------------
+EXTERN SIG_OUTPUT_COMPARE1A
+EXTERN SIG_UART_RECV
+EXTERN SIG_UART_DATA
+
+
+; Functions used by scheduler
+; ---------------------------
+EXTERN vTaskSwitchContext
+EXTERN pxCurrentTCB
+EXTERN xTaskIncrementTick
+EXTERN uxCriticalNesting
+
+; Functions implemented in this file
+; ----------------------------------
+PUBLIC vPortYield
+PUBLIC vPortYieldFromTick
+PUBLIC vPortStart
+
+
+; Interrupt vector table.
+; -----------------------
+;
+; For simplicity the RTOS tick interrupt routine uses the __task keyword.
+; As the IAR compiler does not permit a function to be declared using both
+; __task and __interrupt, the use of __task necessitates that the interrupt
+; vector table be setup manually.
+;
+; To write an ISR, implement the ISR function using the __interrupt keyword
+; but do not install the interrupt using the "#pragma vector=ABC" method.
+; Instead manually place the name of the ISR in the vector table using an
+; ORG and jmp instruction as demonstrated below.
+; You will also have to add an EXTERN statement at the top of the file.
+
+	ASEG
+
+
+	ORG TIMER1_COMPA_vect				; Vector address
+		jmp SIG_OUTPUT_COMPARE1A		; ISR
+
+	ORG USART_RXC_vect					; Vector address
+		jmp SIG_UART_RECV				; ISR
+
+	ORG USART_UDRE_vect					; Vector address
+		jmp SIG_UART_DATA				; ISR
+
+
+	RSEG CODE
+
+
+
+; Saving and Restoring a Task Context and Task Switching
+; ------------------------------------------------------
+;
+; The IAR compiler does not fully support inline assembler, so saving and
+; restoring a task context has to be written in an asm file.
+;
+; vPortYield() and vPortYieldFromTick() are usually written in C.  Doing
+; so in this case would required calls to be made to portSAVE_CONTEXT() and
+; portRESTORE_CONTEXT().  This is dis-advantageous as the context switch
+; function would require two extra jump and return instructions over the
+; WinAVR equivalent.
+;
+; To avoid this I have opted to implement both vPortYield() and
+; vPortYieldFromTick() in this assembly file.  For convenience
+; portSAVE_CONTEXT and portRESTORE_CONTEXT are implemented as macros.
+
+portSAVE_CONTEXT MACRO
+	st	-y, r0			; First save the r0 register - we need to use this.
+	in	r0, SREG		; Obtain the SREG value so we can disable interrupts...
+	cli					; ... as soon as possible.
+	st	-y, r0			; Store the SREG as it was before we disabled interrupts.
+
+	in	r0, SPL			; Next store the hardware stack pointer.  The IAR...
+	st	-y, r0			; ... compiler uses the hardware stack as a call stack ...
+	in	r0, SPH			; ...  only.
+	st	-y, r0
+
+	st	-y, r1			; Now store the rest of the registers.  Dont store the ...
+	st	-y, r2			; ... the Y register here as it is used as the software
+	st	-y, r3			; stack pointer and will get saved into the TCB.
+	st	-y, r4
+	st	-y, r5
+	st	-y, r6
+	st	-y, r7
+	st	-y, r8
+	st	-y, r9
+	st	-y, r10
+	st	-y, r11
+	st	-y, r12
+	st	-y, r13
+	st	-y, r14
+	st	-y, r15
+	st	-y, r16
+	st	-y, r17
+	st	-y, r18
+	st	-y, r19
+	st	-y, r20
+	st	-y, r21
+	st	-y, r22
+	st	-y, r23
+	st	-y, r24
+	st	-y, r25
+	st	-y, r26
+	st	-y, r27
+	st	-y, r30
+	st	-y, r31
+	lds r0, uxCriticalNesting
+	st	-y, r0					; Store the critical nesting counter.
+
+	lds	r26, pxCurrentTCB		; Finally save the software stack pointer (Y ...
+	lds	r27, pxCurrentTCB + 1	; ... register) into the TCB.
+	st	x+, r28
+	st	x+, r29
+
+	ENDM
+
+
+portRESTORE_CONTEXT MACRO
+	lds	r26, pxCurrentTCB
+	lds	r27, pxCurrentTCB + 1	; Restore the software stack pointer from ...
+	ld	r28, x+					; the TCB into the software stack pointer (...
+	ld	r29, x+					; ... the Y register).
+
+	ld	r0, y+
+	sts	uxCriticalNesting, r0
+	ld	r31, y+					; Restore the registers down to R0.  The Y
+	ld	r30, y+					; register is missing from this list as it
+	ld	r27, y+					; has already been restored.
+	ld	r26, y+
+	ld	r25, y+
+	ld	r24, y+
+	ld	r23, y+
+	ld	r22, y+
+	ld	r21, y+
+	ld	r20, y+
+	ld	r19, y+
+	ld	r18, y+
+	ld	r17, y+
+	ld	r16, y+
+	ld	r15, y+
+	ld	r14, y+
+	ld	r13, y+
+	ld	r12, y+
+	ld	r11, y+
+	ld	r10, y+
+	ld	r9, y+
+	ld	r8, y+
+	ld	r7, y+
+	ld	r6, y+
+	ld	r5, y+
+	ld	r4, y+
+	ld	r3, y+
+	ld	r2, y+
+	ld	r1, y+
+
+	ld	r0, y+					; The next thing on the stack is the ...
+	out	SPH, r0					; ... hardware stack pointer.
+	ld	r0, y+
+	out	SPL, r0
+
+	ld	r0, y+					; Next there is the SREG register.
+	out SREG, r0
+
+	ld	r0, y+					; Finally we have finished with r0, so restore r0.
+
+	ENDM
+
+
+
+; vPortYield() and vPortYieldFromTick()
+; -------------------------------------
+;
+; Manual and preemptive context switch functions respectively.
+; The IAR compiler does not fully support inline assembler,
+; so these are implemented here rather than the more usually
+; place of within port.c.
+
+vPortYield:
+	portSAVE_CONTEXT			; Save the context of the current task.
+	call vTaskSwitchContext		; Call the scheduler.
+	portRESTORE_CONTEXT			; Restore the context of whichever task the ...
+	ret							; ... scheduler decided should run.
+
+vPortYieldFromTick:
+	portSAVE_CONTEXT			; Save the context of the current task.
+	call xTaskIncrementTick		; Call the timer tick function.
+	tst r16
+	breq SkipTaskSwitch
+	call vTaskSwitchContext		; Call the scheduler.
+SkipTaskSwitch:
+	portRESTORE_CONTEXT			; Restore the context of whichever task the ...
+	ret							; ... scheduler decided should run.
+
+; vPortStart()
+; ------------
+;
+; Again due to the lack of inline assembler, this is required
+; to get access to the portRESTORE_CONTEXT macro.
+
+vPortStart:
+	portRESTORE_CONTEXT
+	ret
+
+
+; Just a filler for unused interrupt vectors.
+vNoISR:
+	reti
+
+
+	END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR32_UC3/exception.s82 b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR32_UC3/exception.s82
new file mode 100644
index 0000000..30e0967
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR32_UC3/exception.s82
@@ -0,0 +1,311 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief Exception and interrupt vectors.
+ *
+ * This file maps all events supported by an AVR32UC.
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  All AVR32UC devices with an INTC module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation (Now Microchip):
+                                          https://www.microchip.com \n
+ *                       Support and FAQ: https://www.microchip.com/support
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include <avr32/io.h>
+#include "intc.h"
+
+
+//! @{
+//! \verbatim
+
+
+// Start of Exception Vector Table.
+
+  // EVBA must be aligned with a power of two strictly greater than the EVBA-
+  // relative offset of the last vector.
+  COMMON  EVTAB:CODE:ROOT(9)
+
+
+  // Force EVBA initialization.
+  EXTERN  ??init_EVBA
+  REQUIRE ??init_EVBA
+
+  // Export symbol.
+  PUBLIC  ??EVBA
+  PUBLIC  _evba
+??EVBA:
+_evba:
+
+        ORG 0x000
+        // Unrecoverable Exception.
+_handle_Unrecoverable_Exception:
+        rjmp $
+
+        ORG 0x004
+        // TLB Multiple Hit: UNUSED IN AVR32UC.
+_handle_TLB_Multiple_Hit:
+        rjmp $
+
+        ORG 0x008
+        // Bus Error Data Fetch.
+_handle_Bus_Error_Data_Fetch:
+        rjmp $
+
+        ORG 0x00C
+         // Bus Error Instruction Fetch.
+_handle_Bus_Error_Instruction_Fetch:
+        rjmp $
+
+        ORG 0x010
+        // NMI.
+_handle_NMI:
+        rjmp $
+
+        ORG 0x014
+        // Instruction Address.
+_handle_Instruction_Address:
+        rjmp $
+
+        ORG 0x018
+        // ITLB Protection.
+_handle_ITLB_Protection:
+        rjmp $
+
+        ORG 0x01C
+        // Breakpoint.
+_handle_Breakpoint:
+        rjmp $
+
+        ORG 0x020
+        // Illegal Opcode.
+_handle_Illegal_Opcode:
+        rjmp $
+
+        ORG 0x024
+        // Unimplemented Instruction.
+_handle_Unimplemented_Instruction:
+        rjmp $
+
+        ORG 0x028
+        // Privilege Violation.
+_handle_Privilege_Violation:
+        rjmp $
+
+        ORG 0x02C
+        // Floating-Point: UNUSED IN AVR32UC.
+_handle_Floating_Point:
+        rjmp $
+
+        ORG 0x030
+        // Coprocessor Absent: UNUSED IN AVR32UC.
+_handle_Coprocessor_Absent:
+        rjmp $
+
+        ORG 0x034
+        // Data Address (Read).
+_handle_Data_Address_Read:
+        rjmp $
+
+        ORG 0x038
+        // Data Address (Write).
+_handle_Data_Address_Write:
+        rjmp $
+
+        ORG 0x03C
+        // DTLB Protection (Read).
+_handle_DTLB_Protection_Read:
+        rjmp $
+
+        ORG 0x040
+        // DTLB Protection (Write).
+_handle_DTLB_Protection_Write:
+        rjmp $
+
+        ORG 0x044
+        // DTLB Modified: UNUSED IN AVR32UC.
+_handle_DTLB_Modified:
+        rjmp $
+
+        ORG 0x050
+        // ITLB Miss: UNUSED IN AVR32UC.
+_handle_ITLB_Miss:
+        rjmp $
+
+        ORG 0x060
+        // DTLB Miss (Read): UNUSED IN AVR32UC.
+_handle_DTLB_Miss_Read:
+        rjmp $
+
+        ORG 0x070
+        // DTLB Miss (Write): UNUSED IN AVR32UC.
+_handle_DTLB_Miss_Write:
+        rjmp $
+
+        ORG 0x100
+        // Supervisor Call.
+_handle_Supervisor_Call:
+        lddpc   pc, __SCALLYield
+
+
+// Interrupt support.
+// The interrupt controller must provide the offset address relative to EVBA.
+// Important note:
+//   All interrupts call a C function named _get_interrupt_handler.
+//   This function will read group and interrupt line number to then return in
+//   R12 a pointer to a user-provided interrupt handler.
+
+  ALIGN 2
+
+_int0:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 110b
+  brlo    _int0_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int0_normal:
+#endif
+  mov     r12, 0  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  mcall   __get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int1:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 110b
+  brlo    _int1_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int1_normal:
+#endif
+  mov     r12, 1  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  mcall   __get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int2:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 110b
+  brlo    _int2_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int2_normal:
+#endif
+  mov     r12, 2  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  mcall   __get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+_int3:
+  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
+  // CPU upon interrupt entry.
+#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
+  mfsr    r12, AVR32_SR
+  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
+  cp.w    r12, 110b
+  brlo    _int3_normal
+  lddsp   r12, sp[0 * 4]
+  stdsp   sp[6 * 4], r12
+  lddsp   r12, sp[1 * 4]
+  stdsp   sp[7 * 4], r12
+  lddsp   r12, sp[3 * 4]
+  sub     sp, -6 * 4
+  rete
+_int3_normal:
+#endif
+  mov     r12, 3  // Pass the int_lev parameter to the _get_interrupt_handler function.
+  mcall   __get_interrupt_handler
+  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
+  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
+  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
+
+
+// Constant data area.
+
+  ALIGN 2
+
+  // Import symbols.
+  EXTERN  SCALLYield
+  EXTERN  _get_interrupt_handler
+__SCALLYield:
+  DC32  SCALLYield
+__get_interrupt_handler:
+  DC32  _get_interrupt_handler
+
+  // Values to store in the interrupt priority registers for the various interrupt priority levels.
+  // The interrupt priority registers contain the interrupt priority level and
+  // the EVBA-relative interrupt vector offset.
+  PUBLIC  ipr_val
+ipr_val:
+  DC32  (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\
+        (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\
+        (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\
+        (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba)
+
+
+  END
+
+
+//! \endverbatim
+//! @}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR32_UC3/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR32_UC3/port.c
new file mode 100644
index 0000000..c5dab49
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR32_UC3/port.c
@@ -0,0 +1,407 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS port source for AVR32 UC3.
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation (Now Microchip):
+ *                                        https://www.microchip.com \n
+ *                       Support and FAQ: https://www.microchip.com/support/
+ *
+ *****************************************************************************/
+
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* AVR32 UC3 includes. */
+#include <avr32/io.h>
+#include <intrinsics.h>
+#include "gpio.h"
+
+#if configDBG
+	#include "usart.h"
+#endif
+
+#if( configTICK_USE_TC==1 )
+	#include "tc.h"
+#endif
+
+
+/* Constants required to setup the task context. */
+#define portINITIAL_SR            ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
+#define portINSTRUCTION_SIZE      ( ( StackType_t ) 0 )
+
+/* Each task maintains its own critical nesting variable. */
+#define portNO_CRITICAL_NESTING   ( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+#if( configTICK_USE_TC==0 )
+	static void prvScheduleNextTick( void );
+#else
+	static void prvClearTcInt( void );
+#endif
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Low-level initialization routine called during startup, before the main
+ * function.
+ */
+int __low_level_init(void)
+{
+	#if configHEAP_INIT
+		#pragma segment = "HEAP"
+		BaseType_t *pxMem;
+	#endif
+
+	/* Enable exceptions. */
+	ENABLE_ALL_EXCEPTIONS();
+
+	/* Initialize interrupt handling. */
+	INTC_init_interrupts();
+
+	#if configHEAP_INIT
+	{
+		/* Initialize the heap used by malloc. */
+		for( pxMem = __segment_begin( "HEAP" ); pxMem < ( BaseType_t * ) __segment_end( "HEAP" ); )
+		{
+			*pxMem++ = 0xA5A5A5A5;
+		}
+	}
+	#endif
+
+	/* Code section present if and only if the debug trace is activated. */
+	#if configDBG
+	{
+		static const gpio_map_t DBG_USART_GPIO_MAP =
+		{
+			{ configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
+			{ configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
+		};
+
+		static const usart_options_t DBG_USART_OPTIONS =
+		{
+			.baudrate = configDBG_USART_BAUDRATE,
+			.charlength = 8,
+			.paritytype = USART_NO_PARITY,
+			.stopbits = USART_1_STOPBIT,
+			.channelmode = USART_NORMAL_CHMODE
+		};
+
+		/* Initialize the USART used for the debug trace with the configured parameters. */
+		extern volatile avr32_usart_t *volatile stdio_usart_base;
+		stdio_usart_base = configDBG_USART;
+		gpio_enable_module( DBG_USART_GPIO_MAP,
+		                    sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
+		usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ);
+	}
+	#endif
+
+	/* Request initialization of data segments. */
+	return 1;
+}
+/*-----------------------------------------------------------*/
+
+/* Added as there is no such function in FreeRTOS. */
+void *pvPortRealloc( void *pv, size_t xWantedSize )
+{
+void *pvReturn;
+
+	vTaskSuspendAll();
+	{
+		pvReturn = realloc( pv, xWantedSize );
+	}
+	xTaskResumeAll();
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+/* The cooperative scheduler requires a normal IRQ service routine to
+simply increment the system tick. */
+/* The preemptive scheduler is defined as "naked" as the full context is saved
+on entry as part of the context switch. */
+#pragma shadow_registers = full   // Naked.
+static void vTick( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT_OS_INT();
+
+	#if( configTICK_USE_TC==1 )
+		/* Clear the interrupt flag. */
+		prvClearTcInt();
+	#else
+		/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
+		clock cycles from now. */
+		prvScheduleNextTick();
+	#endif
+
+	/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
+	calls in a critical section . */
+	portENTER_CRITICAL();
+		xTaskIncrementTick();
+	portEXIT_CRITICAL();
+
+	/* Restore the context of the "elected task". */
+	portRESTORE_CONTEXT_OS_INT();
+}
+/*-----------------------------------------------------------*/
+
+#pragma shadow_registers = full   // Naked.
+void SCALLYield( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT_SCALL();
+	vTaskSwitchContext();
+	portRESTORE_CONTEXT_SCALL();
+}
+/*-----------------------------------------------------------*/
+
+/* The code generated by the GCC compiler uses the stack in different ways at
+different optimisation levels.  The interrupt flags can therefore not always
+be saved to the stack.  Instead the critical section nesting level is stored
+in a variable, which is then saved as part of the stack context. */
+#pragma optimize = no_inline
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts */
+	portDISABLE_INTERRUPTS();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	 directly.  Increment ulCriticalNesting to keep a count of how many times
+	 portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+#pragma optimize = no_inline
+void vPortExitCritical( void )
+{
+	if(ulCriticalNesting > portNO_CRITICAL_NESTING)
+	{
+		ulCriticalNesting--;
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable all interrupt/exception. */
+			portENABLE_INTERRUPTS();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* When the task starts, it will expect to find the function parameter in R12. */
+	pxTopOfStack--;
+	*pxTopOfStack-- = ( StackType_t ) 0x08080808;					/* R8 */
+	*pxTopOfStack-- = ( StackType_t ) 0x09090909;					/* R9 */
+	*pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A;					/* R10 */
+	*pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B;					/* R11 */
+	*pxTopOfStack-- = ( StackType_t ) pvParameters;					/* R12 */
+	*pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF;					/* R14/LR */
+	*pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
+	*pxTopOfStack-- = ( StackType_t ) portINITIAL_SR;				/* SR */
+	*pxTopOfStack-- = ( StackType_t ) 0xFF0000FF;					/* R0 */
+	*pxTopOfStack-- = ( StackType_t ) 0x01010101;					/* R1 */
+	*pxTopOfStack-- = ( StackType_t ) 0x02020202;					/* R2 */
+	*pxTopOfStack-- = ( StackType_t ) 0x03030303;					/* R3 */
+	*pxTopOfStack-- = ( StackType_t ) 0x04040404;					/* R4 */
+	*pxTopOfStack-- = ( StackType_t ) 0x05050505;					/* R5 */
+	*pxTopOfStack-- = ( StackType_t ) 0x06060606;					/* R6 */
+	*pxTopOfStack-- = ( StackType_t ) 0x07070707;					/* R7 */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING;			/* ulCriticalNesting */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	portRESTORE_CONTEXT();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the AVR32 port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
+clock cycles from now. */
+#if( configTICK_USE_TC==0 )
+	static void prvScheduleFirstTick(void)
+	{
+		uint32_t lCycles;
+
+		lCycles = Get_system_register(AVR32_COUNT);
+		lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+		// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
+		// generation feature does not get disabled.
+		if(0 == lCycles)
+		{
+			lCycles++;
+		}
+		Set_system_register(AVR32_COMPARE, lCycles);
+	}
+	
+	#pragma optimize = no_inline
+	static void prvScheduleNextTick(void)
+	{
+		uint32_t lCycles, lCount;
+
+		lCycles = Get_system_register(AVR32_COMPARE);
+		lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+		// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
+		// generation feature does not get disabled.
+		if(0 == lCycles)
+		{
+			lCycles++;
+		}
+		lCount = Get_system_register(AVR32_COUNT);
+		if( lCycles < lCount )
+		{		// We missed a tick, recover for the next.
+			lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
+		}
+		Set_system_register(AVR32_COMPARE, lCycles);
+	}
+#else
+	#pragma optimize = no_inline
+	static void prvClearTcInt(void)
+	{
+		AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt(void)
+{
+	#if( configTICK_USE_TC==1 )
+
+		volatile avr32_tc_t *tc = &AVR32_TC;
+
+		// Options for waveform genration.
+		tc_waveform_opt_t waveform_opt =
+		{
+		.channel  = configTICK_TC_CHANNEL,             /* Channel selection. */
+
+		.bswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOB. */
+		.beevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOB. */
+		.bcpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOB. */
+		.bcpb     = TC_EVT_EFFECT_NOOP,                /* RB compare effect on TIOB. */
+
+		.aswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOA. */
+		.aeevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOA. */
+		.acpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOA: toggle. */
+		.acpa     = TC_EVT_EFFECT_NOOP,                /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
+
+		.wavsel   = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
+		.enetrg   = FALSE,                             /* External event trigger enable. */
+		.eevt     = 0,                                 /* External event selection. */
+		.eevtedg  = TC_SEL_NO_EDGE,                    /* External event edge selection. */
+		.cpcdis   = FALSE,                             /* Counter disable when RC compare. */
+		.cpcstop  = FALSE,                             /* Counter clock stopped with RC compare. */
+
+		.burst    = FALSE,                             /* Burst signal selection. */
+		.clki     = FALSE,                             /* Clock inversion. */
+		.tcclks   = TC_CLOCK_SOURCE_TC2                /* Internal source clock 2. */
+		};
+
+		tc_interrupt_t tc_interrupt =
+		{
+			.etrgs=0,
+			.ldrbs=0,
+			.ldras=0,
+			.cpcs =1,
+			.cpbs =0,
+			.cpas =0,
+			.lovrs=0,
+			.covfs=0,
+		};
+
+	#endif
+
+	/* Disable all interrupt/exception. */
+	portDISABLE_INTERRUPTS();
+
+	/* Register the compare interrupt handler to the interrupt controller and
+	enable the compare interrupt. */
+
+	#if( configTICK_USE_TC==1 )
+	{
+		INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, INT0);
+
+		/* Initialize the timer/counter. */
+		tc_init_waveform(tc, &waveform_opt);
+
+		/* Set the compare triggers.
+		Remember TC counter is 16-bits, so counting second is not possible!
+		That's why we configure it to count ms. */
+		tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
+
+		tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
+
+		/* Start the timer/counter. */
+		tc_start(tc, configTICK_TC_CHANNEL);
+	}
+	#else
+	{
+		INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
+		prvScheduleFirstTick();
+	}
+	#endif
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR32_UC3/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR32_UC3/portmacro.h
new file mode 100644
index 0000000..8961f46
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR32_UC3/portmacro.h
@@ -0,0 +1,655 @@
+/*This file has been prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief FreeRTOS port header for AVR32 UC3.
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  All AVR32 devices can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation (Now Microchip):
+ *                                        https://www.microchip.com
+ *                       Support and FAQ: https://www.microchip.com/support
+ *
+ *****************************************************************************/
+
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+#include <avr32/io.h>
+#include "intc.h"
+#include "compiler.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#define TASK_DELAY_MS(x)   ( (x)        /portTICK_PERIOD_MS )
+#define TASK_DELAY_S(x)    ( (x)*1000   /portTICK_PERIOD_MS )
+#define TASK_DELAY_MIN(x)  ( (x)*60*1000/portTICK_PERIOD_MS )
+
+#define configTICK_TC_IRQ             ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
+
+#if( configUSE_16_BIT_TICKS == 1 )
+  typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+  typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS      ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT       4
+#define portNOP()             {__asm__ __volatile__ ("nop");}
+/*-----------------------------------------------------------*/
+
+
+/*-----------------------------------------------------------*/
+
+/* INTC-specific. */
+#define DISABLE_ALL_EXCEPTIONS()    Disable_global_exception()
+#define ENABLE_ALL_EXCEPTIONS()     Enable_global_exception()
+
+#define DISABLE_ALL_INTERRUPTS()    Disable_global_interrupt()
+#define ENABLE_ALL_INTERRUPTS()     Enable_global_interrupt()
+
+#define DISABLE_INT_LEVEL(int_lev)  Disable_interrupt_level(int_lev)
+#define ENABLE_INT_LEVEL(int_lev)   Enable_interrupt_level(int_lev)
+
+
+/*
+ * Debug trace.
+ * Activated if and only if configDBG is nonzero.
+ * Prints a formatted string to stdout.
+ * The current source file name and line number are output with a colon before
+ * the formatted string.
+ * A carriage return and a linefeed are appended to the output.
+ * stdout is redirected to the USART configured by configDBG_USART.
+ * The parameters are the same as for the standard printf function.
+ * There is no return value.
+ * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
+ * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
+ */
+#if configDBG
+	#define portDBG_TRACE(...)												\
+	{																		\
+	  fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);					\
+	  printf(__VA_ARGS__);													\
+	  fputs("\r\n", stdout);												\
+	}
+#else
+	#define portDBG_TRACE(...)
+#endif
+
+
+/* Critical section management. */
+#define portDISABLE_INTERRUPTS()  DISABLE_ALL_INTERRUPTS()
+#define portENABLE_INTERRUPTS()   ENABLE_ALL_INTERRUPTS()
+
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()      vPortEnterCritical();
+#define portEXIT_CRITICAL()       vPortExitCritical();
+
+
+/* Added as there is no such function in FreeRTOS. */
+extern void *pvPortRealloc( void *pv, size_t xSize );
+/*-----------------------------------------------------------*/
+
+
+/*=============================================================================================*/
+
+/*
+ * Restore Context for cases other than INTi.
+ */
+#define portRESTORE_CONTEXT()																\
+{																							\
+  extern volatile uint32_t ulCriticalNesting;										\
+  extern volatile void *volatile pxCurrentTCB;												\
+																							\
+  __asm__ __volatile__ (																	\
+    /* Set SP to point to new stack */														\
+    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")												\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")												\n\t"\
+    "ld.w    r0, r8[0]																		\n\t"\
+    "ld.w    sp, r0[0]																		\n\t"\
+																							\
+    /* Restore ulCriticalNesting variable */												\
+    "ld.w    r0, sp++																		\n\t"\
+    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")										\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")										\n\t"\
+    "st.w    r8[0], r0																		\n\t"\
+																							\
+    /* Restore R0..R7 */																	\
+    "ldm     sp++, r0-r7																	\n\t"\
+    /* R0-R7 should not be used below this line */											\
+    /* Skip PC and SR (will do it at the end) */											\
+    "sub     sp, -2*4																		\n\t"\
+    /* Restore R8..R12 and LR */															\
+    "ldm     sp++, r8-r12, lr																\n\t"\
+    /* Restore SR */																		\
+    "ld.w    r0, sp[-8*4]																	\n\t" /* R0 is modified, is restored later. */\
+    "mtsr    "ASTRINGZ(AVR32_SR)", r0														\n\t"\
+    /* Restore r0 */																		\
+    "ld.w    r0, sp[-9*4]																	\n\t"\
+    /* Restore PC */																		\
+    "ld.w    pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */			\
+  );																						\
+																							\
+  /* Force import of global symbols from assembly */										\
+  ulCriticalNesting;																		\
+  pxCurrentTCB;																				\
+}
+
+
+/*
+ * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
+ * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
+ *
+ * Had to make different versions because registers saved on the system stack
+ * are not the same between INT0..3 exceptions and the scall exception.
+ */
+
+// Task context stack layout:
+  // R8  (*)
+  // R9  (*)
+  // R10 (*)
+  // R11 (*)
+  // R12 (*)
+  // R14/LR (*)
+  // R15/PC (*)
+  // SR (*)
+  // R0
+  // R1
+  // R2
+  // R3
+  // R4
+  // R5
+  // R6
+  // R7
+  // ulCriticalNesting
+// (*) automatically done for INT0..INT3, but not for SCALL
+
+/*
+ * The ISR used for the scheduler tick depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+#if configUSE_PREEMPTION == 0
+
+/*
+ * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
+ */
+#define portSAVE_CONTEXT_OS_INT()															\
+{																							\
+  /* Save R0..R7 */																			\
+  __asm__ __volatile__ ("stm     --sp, r0-r7");												\
+																							\
+  /* With the cooperative scheduler, as there is no context switch by interrupt, */			\
+  /* there is also no context save. */														\
+}
+
+/*
+ * portRESTORE_CONTEXT_OS_INT() for Tick exception.
+ */
+#define portRESTORE_CONTEXT_OS_INT()														\
+{																							\
+  __asm__ __volatile__ (																	\
+    /* Restore R0..R7 */																	\
+    "ldm     sp++, r0-r7																	\n\t"\
+																							\
+    /* With the cooperative scheduler, as there is no context switch by interrupt, */		\
+    /* there is also no context restore. */													\
+    "rete"																					\
+  );																						\
+}
+
+#else
+
+/*
+ * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
+ */
+#define portSAVE_CONTEXT_OS_INT()																	\
+{																									\
+  extern volatile uint32_t ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  /* When we come here */																			\
+  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */					\
+																									\
+  __asm__ __volatile__ (																			\
+    /* Save R0..R7 */																				\
+    "stm     --sp, r0-r7																			\n\t"\
+																									\
+    /* Save ulCriticalNesting variable  - R0 is overwritten */										\
+    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "st.w    --sp, r0																				\n\t"\
+																									\
+    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */	\
+    /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
+    /* level and allow other lower interrupt level to occur). */									\
+    /* In this case we don't want to do a task switch because we don't know what the stack */		\
+    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */	\
+    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */		\
+    /* will just be restoring the interrupt handler, no way!!! */									\
+    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */					\
+    "ld.w    r0, sp[9*4]																			\n\t" /* Read SR in stack */\
+    "bfextu  r0, r0, 22, 3																			\n\t" /* Extract the mode bits to R0. */\
+    "cp.w    r0, 1																					\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+    "brhi    LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)"										\n\t"\
+																									\
+    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */					\
+    /* NOTE: we don't enter a critical section here because all interrupt handlers */				\
+    /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */							\
+    /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */			\
+    /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */		\
+    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "st.w    r0[0], sp																				\n"\
+																									\
+    "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":"												\
+  );																								\
+}
+
+/*
+ * portRESTORE_CONTEXT_OS_INT() for Tick exception.
+ */
+#define portRESTORE_CONTEXT_OS_INT()																\
+{																									\
+  extern volatile uint32_t ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */		\
+  /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
+  /* level and allow other lower interrupt level to occur). */										\
+  /* In this case we don't want to do a task switch because we don't know what the stack */			\
+  /* currently looks like (we don't know what the interrupted interrupt handler was doing). */		\
+  /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */			\
+  /* will just be restoring the interrupt handler, no way!!! */										\
+  __asm__ __volatile__ (																			\
+    "ld.w    r0, sp[9*4]																			\n\t" /* Read SR in stack */\
+    "bfextu  r0, r0, 22, 3																			\n\t" /* Extract the mode bits to R0. */\
+    "cp.w    r0, 1																					\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+    "brhi    LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)										\
+  );																								\
+																									\
+  /* Else */																						\
+  /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */		\
+  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
+  portENTER_CRITICAL();																				\
+  vTaskSwitchContext();																				\
+  portEXIT_CRITICAL();																				\
+																									\
+  /* Restore all registers */																		\
+																									\
+  __asm__ __volatile__ (																			\
+    /* Set SP to point to new stack */																\
+    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "ld.w    sp, r0[0]																				\n"\
+																									\
+    "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":											\n\t"\
+																									\
+    /* Restore ulCriticalNesting variable */														\
+    "ld.w    r0, sp++																				\n\t"\
+    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "st.w    r8[0], r0																				\n\t"\
+																									\
+    /* Restore R0..R7 */																			\
+    "ldm     sp++, r0-r7																			\n\t"\
+																									\
+    /* Now, the stack should be R8..R12, LR, PC and SR */											\
+    "rete"																							\
+  );																								\
+																									\
+  /* Force import of global symbols from assembly */												\
+  ulCriticalNesting;																				\
+  pxCurrentTCB;																						\
+}
+
+#endif
+
+
+/*
+ * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
+ *
+ * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
+ *
+ */
+#define portSAVE_CONTEXT_SCALL()																	\
+{																									\
+  extern volatile uint32_t ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */				\
+  /* If SR[M2:M0] == 001 */																			\
+  /*    PC and SR are on the stack.  */																\
+  /* Else (other modes) */																			\
+  /*    Nothing on the stack. */																	\
+																									\
+  /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */				\
+  /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */				\
+  /* in an interrupt|exception handler. */															\
+																									\
+  __asm__ __volatile__ (																			\
+    /* in order to save R0-R7 */																	\
+    "sub     sp, 6*4																				\n\t"\
+    /* Save R0..R7 */																				\
+    "stm     --sp, r0-r7																			\n\t"\
+																									\
+    /* in order to save R8-R12 and LR */															\
+    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */					\
+    "sub     r7, sp,-16*4																			\n\t"\
+    /* Copy PC and SR in other places in the stack. */												\
+    "ld.w    r0, r7[-2*4]																			\n\t" /* Read SR */\
+    "st.w    r7[-8*4], r0																			\n\t" /* Copy SR */\
+    "ld.w    r0, r7[-1*4]																			\n\t" /* Read PC */\
+    "st.w    r7[-7*4], r0																			\n\t" /* Copy PC */\
+																									\
+    /* Save R8..R12 and LR on the stack. */															\
+    "stm     --r7, r8-r12, lr																		\n\t"\
+																									\
+    /* Arriving here we have the following stack organizations: */									\
+    /* R8..R12, LR, PC, SR, R0..R7. */																\
+																									\
+    /* Now we can finalize the save. */																\
+																									\
+    /* Save ulCriticalNesting variable  - R0 is overwritten */										\
+    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "st.w    --sp, r0"																				\
+  );																								\
+																									\
+  /* Disable the its which may cause a context switch (i.e. cause a change of */					\
+  /* pxCurrentTCB). */																				\
+  /* Basically, all accesses to the pxCurrentTCB structure should be put in a */					\
+  /* critical section because it is a global structure. */											\
+  portENTER_CRITICAL();																				\
+																									\
+  /* Store SP in the first member of the structure pointed to by pxCurrentTCB */					\
+  __asm__ __volatile__ (																			\
+    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "st.w    r0[0], sp"																				\
+  );																								\
+}
+
+/*
+ * portRESTORE_CONTEXT() for SupervisorCALL exception.
+ */
+#define portRESTORE_CONTEXT_SCALL()																	\
+{																									\
+  extern volatile uint32_t ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  /* Restore all registers */																		\
+																									\
+  /* Set SP to point to new stack */																\
+  __asm__ __volatile__ (																			\
+    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "ld.w    sp, r0[0]"																				\
+  );																								\
+																									\
+  /* Leave pxCurrentTCB variable access critical section */											\
+  portEXIT_CRITICAL();																				\
+																									\
+  __asm__ __volatile__ (																			\
+    /* Restore ulCriticalNesting variable */														\
+    "ld.w    r0, sp++																				\n\t"\
+    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "st.w    r8[0], r0																				\n\t"\
+																									\
+    /* skip PC and SR */																			\
+    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */					\
+    "sub     r7, sp, -10*4																			\n\t"\
+    /* Restore r8-r12 and LR */																		\
+    "ldm     r7++, r8-r12, lr																		\n\t"\
+																									\
+    /* RETS will take care of the extra PC and SR restore. */										\
+    /* So, we have to prepare the stack for this. */												\
+    "ld.w    r0, r7[-8*4]																			\n\t" /* Read SR */\
+    "st.w    r7[-2*4], r0																			\n\t" /* Copy SR */\
+    "ld.w    r0, r7[-7*4]																			\n\t" /* Read PC */\
+    "st.w    r7[-1*4], r0																			\n\t" /* Copy PC */\
+																									\
+    /* Restore R0..R7 */																			\
+    "ldm     sp++, r0-r7																			\n\t"\
+																									\
+    "sub     sp, -6*4																				\n\t"\
+																									\
+    "rets"																							\
+  );																								\
+																									\
+  /* Force import of global symbols from assembly */												\
+  ulCriticalNesting;																				\
+  pxCurrentTCB;																						\
+}
+
+
+/*
+ * The ISR used depends on whether the cooperative or
+ * the preemptive scheduler is being used.
+ */
+#if configUSE_PREEMPTION == 0
+
+/*
+ * ISR entry and exit macros.  These are only required if a task switch
+ * is required from the ISR.
+ */
+#define portENTER_SWITCHING_ISR()																	\
+{																									\
+  /* Save R0..R7 */																					\
+  __asm__ __volatile__ ("stm     --sp, r0-r7");														\
+																									\
+  /* With the cooperative scheduler, as there is no context switch by interrupt, */					\
+  /* there is also no context save. */																\
+}
+
+/*
+ * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
+ */
+#define portEXIT_SWITCHING_ISR()																	\
+{																									\
+  __asm__ __volatile__ (																			\
+    /* Restore R0..R7 */																			\
+    "ldm     sp++, r0-r7																			\n\t"\
+																									\
+    /* With the cooperative scheduler, as there is no context switch by interrupt, */				\
+    /* there is also no context restore. */															\
+    "rete"																							\
+  );																								\
+}
+
+#else
+
+/*
+ * ISR entry and exit macros.  These are only required if a task switch
+ * is required from the ISR.
+ */
+#define portENTER_SWITCHING_ISR()																	\
+{																									\
+  extern volatile uint32_t ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  /* When we come here */																			\
+  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */					\
+																									\
+  __asm__ __volatile__ (																			\
+    /* Save R0..R7 */																				\
+    "stm     --sp, r0-r7																			\n\t"\
+																									\
+    /* Save ulCriticalNesting variable  - R0 is overwritten */										\
+    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "st.w    --sp, r0																				\n\t"\
+																									\
+    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */	\
+    /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
+    /* level and allow other lower interrupt level to occur). */									\
+    /* In this case we don't want to do a task switch because we don't know what the stack */		\
+    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */	\
+    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */		\
+    /* will just be restoring the interrupt handler, no way!!! */									\
+    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */					\
+    "ld.w    r0, sp[9*4]																			\n\t" /* Read SR in stack */\
+    "bfextu  r0, r0, 22, 3																			\n\t" /* Extract the mode bits to R0. */\
+    "cp.w    r0, 1																					\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+    "brhi    LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)"										\n\t"\
+																									\
+    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */					\
+    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "st.w    r0[0], sp																				\n"\
+																									\
+    "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":"												\
+  );																								\
+}
+
+
+/*
+ * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
+ */
+#define portEXIT_SWITCHING_ISR()																	\
+{																									\
+  extern volatile uint32_t ulCriticalNesting;												\
+  extern volatile void *volatile pxCurrentTCB;														\
+																									\
+  __asm__ __volatile__ (																			\
+    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */	\
+    /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
+    /* level and allow other lower interrupt level to occur). */									\
+    /* In this case it's of no use to switch context and restore a new SP because we purposedly */	\
+    /* did not previously save SP in its TCB. */													\
+    "ld.w    r0, sp[9*4]																			\n\t" /* Read SR in stack */\
+    "bfextu  r0, r0, 22, 3																			\n\t" /* Extract the mode bits to R0. */\
+    "cp.w    r0, 1																					\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
+    "brhi    LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)"									\n\t"\
+																									\
+    /* If a switch is required then we just need to call */											\
+    /* vTaskSwitchContext() as the context has already been */										\
+    /* saved. */																					\
+    "cp.w    r12, 1																					\n\t" /* Check if Switch context is required. */\
+    "brne    LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":C"										\
+  );																								\
+																									\
+  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
+  portENTER_CRITICAL();																				\
+  vTaskSwitchContext();																				\
+  portEXIT_CRITICAL();																				\
+																									\
+  __asm__ __volatile__ (																			\
+    "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":												\n\t"\
+    /* Restore the context of which ever task is now the highest */									\
+    /* priority that is ready to run. */															\
+																									\
+    /* Restore all registers */																		\
+																									\
+    /* Set SP to point to new stack */																\
+    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
+    "ld.w    r0, r8[0]																				\n\t"\
+    "ld.w    sp, r0[0]																				\n"\
+																									\
+    "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":											\n\t"\
+																									\
+    /* Restore ulCriticalNesting variable */														\
+    "ld.w    r0, sp++																				\n\t"\
+    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
+    "st.w    r8[0], r0																				\n\t"\
+																									\
+    /* Restore R0..R7 */																			\
+    "ldm     sp++, r0-r7																			\n\t"\
+																									\
+    /* Now, the stack should be R8..R12, LR, PC and SR  */											\
+    "rete"																							\
+  );																								\
+																									\
+  /* Force import of global symbols from assembly */												\
+  ulCriticalNesting;																				\
+  pxCurrentTCB;																						\
+}
+
+#endif
+
+
+#define portYIELD()                 {__asm__ __volatile__ ("scall");}
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR32_UC3/read.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR32_UC3/read.c
new file mode 100644
index 0000000..61b17a4
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR32_UC3/read.c
@@ -0,0 +1,94 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief System-specific implementation of the \ref __read function used by
+          the standard library.
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  All AVR32 devices with a USART module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation (Now Microchip):
+ *                                        https://www.microchip.com \n
+ *                       Support and FAQ: https://www.microchip.com/support/
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include <yfuns.h>
+#include <avr32/io.h>
+#include "usart.h"
+
+
+_STD_BEGIN
+
+
+#pragma module_name = "?__read"
+
+
+extern volatile avr32_usart_t *volatile stdio_usart_base;
+
+
+/*! \brief Reads a number of bytes, at most \a size, into the memory area
+ *         pointed to by \a buffer.
+ *
+ * \param handle File handle to read from.
+ * \param buffer Pointer to buffer to write read bytes to.
+ * \param size Number of bytes to read.
+ *
+ * \return The number of bytes read, \c 0 at the end of the file, or
+ *         \c _LLIO_ERROR on failure.
+ */
+size_t __read(int handle, uint8_t *buffer, size_t size)
+{
+  int nChars = 0;
+
+  // This implementation only reads from stdin.
+  // For all other file handles, it returns failure.
+  if (handle != _LLIO_STDIN)
+  {
+    return _LLIO_ERROR;
+  }
+
+  for (; size > 0; --size)
+  {
+    int c = usart_getchar(stdio_usart_base);
+    if (c < 0)
+      break;
+
+    *buffer++ = c;
+    ++nChars;
+  }
+
+  return nChars;
+}
+
+
+_STD_END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR32_UC3/write.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR32_UC3/write.c
new file mode 100644
index 0000000..a78e0c1
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR32_UC3/write.c
@@ -0,0 +1,104 @@
+/*This file is prepared for Doxygen automatic documentation generation.*/
+/*! \file *********************************************************************
+ *
+ * \brief System-specific implementation of the \ref __write function used by
+          the standard library.
+ *
+ * - Compiler:           IAR EWAVR32
+ * - Supported devices:  All AVR32 devices with a USART module can be used.
+ * - AppNote:
+ *
+ * \author               Atmel Corporation (Now Microchip):
+ *                                        https://www.microchip.com \n
+ *                       Support and FAQ: https://www.microchip.com/support
+ *
+ ******************************************************************************/
+
+/* Copyright (c) 2007, Atmel Corporation All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of ATMEL may not be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
+ * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#include <yfuns.h>
+#include <avr32/io.h>
+#include "usart.h"
+
+
+_STD_BEGIN
+
+
+#pragma module_name = "?__write"
+
+
+//! Pointer to the base of the USART module instance to use for stdio.
+__no_init volatile avr32_usart_t *volatile stdio_usart_base;
+
+
+/*! \brief Writes a number of bytes, at most \a size, from the memory area
+ *         pointed to by \a buffer.
+ *
+ * If \a buffer is zero then \ref __write performs flushing of internal buffers,
+ * if any. In this case, \a handle can be \c -1 to indicate that all handles
+ * should be flushed.
+ *
+ * \param handle File handle to write to.
+ * \param buffer Pointer to buffer to read bytes to write from.
+ * \param size Number of bytes to write.
+ *
+ * \return The number of bytes written, or \c _LLIO_ERROR on failure.
+ */
+size_t __write(int handle, const uint8_t *buffer, size_t size)
+{
+  size_t nChars = 0;
+
+  if (buffer == 0)
+  {
+    // This means that we should flush internal buffers.
+    return 0;
+  }
+
+  // This implementation only writes to stdout and stderr.
+  // For all other file handles, it returns failure.
+  if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR)
+  {
+    return _LLIO_ERROR;
+  }
+
+  for (; size != 0; --size)
+  {
+    if (usart_putchar(stdio_usart_base, *buffer++) < 0)
+    {
+      return _LLIO_ERROR;
+    }
+
+    ++nChars;
+  }
+
+  return nChars;
+}
+
+
+_STD_END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_AVRDx/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_AVRDx/port.c
new file mode 100644
index 0000000..e72f0ae
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_AVRDx/port.c
@@ -0,0 +1,300 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include <stdlib.h>
+#include "porthardware.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the AVR port.
+*----------------------------------------------------------*/
+
+/* Start tasks with interrupts enables. */
+#define portFLAGS_INT_ENABLED    ( ( StackType_t ) 0x80 )
+
+/*-----------------------------------------------------------*/
+
+
+#define portBYTES_USED_BY_RETURN_ADDRESS    2
+#define portNO_CRITICAL_NESTING             ( ( UBaseType_t ) 0 )
+
+/* Stores the critical section nesting.  This must not be initialised to 0.
+ * It will be initialised when a task starts. */
+UBaseType_t uxCriticalNesting = 0x50;
+
+/*
+ * Setup timer to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The IAR compiler does not have full support for inline assembler, so
+ * these are defined in the portmacro assembler file.
+ */
+extern void vPortYieldFromTick( void );
+extern void vPortStart( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    uint16_t usAddress;
+    StackType_t * pxTopOfHardwareStack;
+
+    /* Simulate how the stack would look after a call to vPortYield(). */
+
+    /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+
+    /* The IAR compiler requires two stacks per task.  First there is the
+     * hardware call stack which uses the AVR stack pointer.  Second there is the
+     * software stack (local variables, parameter passing, etc.) which uses the
+     * AVR Y register.
+     * This function places both stacks within the memory block passed in as the
+     * first parameter.  The hardware stack is placed at the bottom of the memory
+     * block.  A gap is then left for the hardware stack to grow.  Next the software
+     * stack is placed.  The amount of space between the software and hardware
+     * stacks is defined by configCALL_STACK_SIZE.
+     * The first part of the stack is the hardware stack.  Place the start
+     * address of the task on the hardware stack. */
+
+    /* Place a few bytes of known values on the bottom of the stack.
+     * This is just useful for debugging. */
+    /**pxTopOfStack = 0x11; */
+    /*pxTopOfStack--; */
+    /**pxTopOfStack = 0x22; */
+    /*pxTopOfStack--; */
+    /**pxTopOfStack = 0x33; */
+    /*pxTopOfStack--; */
+
+    /* Remember where the top of the hardware stack is - this is required
+     * below. */
+    pxTopOfHardwareStack = pxTopOfStack;
+
+    usAddress = ( uint16_t ) pxCode;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    /* Leave enough space for the hardware stack before starting the software
+     * stack.  The '- 2' is because we have already used two spaces for the
+     * address of the start of the task. */
+    pxTopOfStack -= ( configCALL_STACK_SIZE - 2 );
+
+    /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
+     *  portSAVE_CONTEXT places the flags on the stack immediately after r0
+     *  to ensure the interrupts get disabled as soon as possible, and so ensuring
+     *  the stack use is minimal should a context switch interrupt occur. */
+
+    *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
+    pxTopOfStack--;
+    *pxTopOfStack = portFLAGS_INT_ENABLED;
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x00; /* RAMPZ */
+    pxTopOfStack--;
+
+    /* Next place the address of the hardware stack.  This is required so
+     * the AVR stack pointer can be restored to point to the hardware stack. */
+    pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS;
+    usAddress = ( uint16_t ) pxTopOfHardwareStack;
+
+    /* SPL */
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    /* SPH */
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    /* Now the remaining registers. */
+    *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */
+    pxTopOfStack--;
+
+    /* Place the parameter on the stack in the expected location. */
+    usAddress = ( uint16_t ) pvParameters;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */
+    pxTopOfStack--;
+
+    /* The Y register is not stored as it is used as the software stack and
+     * gets saved into the task control block. */
+
+    *pxTopOfStack = ( StackType_t ) 0x30;  /* R30 Z */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */
+
+    pxTopOfStack--;
+    *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */
+
+    /*lint +e950 +e611 +e923 */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+    /* Setup the hardware to generate the tick. */
+    prvSetupTimerInterrupt();
+
+    /* Restore the context of the first task that is going to run.
+     * Normally we would just call portRESTORE_CONTEXT() here, but as the IAR
+     * compiler does not fully support inline assembler we have to make a call.*/
+    vPortStart();
+
+    /* Should not get here. */
+    return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* vPortEndScheduler is not implemented in this port. */
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup timer to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+    TICK_init();
+}
+
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 1
+
+/*
+ * Tick ISR for preemptive scheduler.  We can use a naked attribute as
+ * the context is saved at the start of vPortYieldFromTick().  The tick
+ * count is incremented after the context is saved.
+ */
+
+    __task void TICK_INT( void )
+    {
+        vPortYieldFromTick();
+        asm ( "reti" );
+    }
+#else
+
+/*
+ * Tick ISR for the cooperative scheduler.  All this does is increment the
+ * tick count.  We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ */
+
+    __interrupt void TICK_INT( void )
+    {
+        /* Clear tick interrupt flag. */
+        INT_FLAGS = INT_MASK;
+
+        xTaskIncrementTick();
+    }
+#endif /* if configUSE_PREEMPTION == 1 */
+
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == portNO_CRITICAL_NESTING )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_AVRDx/porthardware.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_AVRDx/porthardware.h
new file mode 100644
index 0000000..dbbcd05
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_AVRDx/porthardware.h
@@ -0,0 +1,102 @@
+#ifndef PORTHARDWARE_H
+#define PORTHARDWARE_H
+
+#ifndef __IAR_SYSTEMS_ASM__
+    #include <ioavr.h>
+#endif
+#include "FreeRTOSConfig.h"
+
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMER_INSTANCE == 0 )
+
+    #define TICK_INT_vect    TCB0_INT_vect
+    #define INT_FLAGS        TCB0_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB0.INTCTRL = TCB_CAPT_bm;                          \
+        TCB0.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 1 )
+
+    #define TICK_INT_vect    TCB1_INT_vect
+    #define INT_FLAGS        TCB1_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB1.INTCTRL = TCB_CAPT_bm;                          \
+        TCB1.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 2 )
+
+    #define TICK_INT_vect    TCB2_INT_vect
+    #define INT_FLAGS        TCB2_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB2.INTCTRL = TCB_CAPT_bm;                          \
+        TCB2.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 3 )
+
+    #define TICK_INT_vect    TCB3_INT_vect
+    #define INT_FLAGS        TCB3_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB3.INTCTRL = TCB_CAPT_bm;                          \
+        TCB3.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 4 )
+
+    #define TICK_INT_vect    TCB4_INT_vect
+    #define INT_FLAGS        TCB4_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB4.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB4.INTCTRL = TCB_CAPT_bm;                          \
+        TCB4.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 5 )
+
+    #define TICK_INT_vect    RTC_CNT_vect
+    #define INT_FLAGS        RTC_INTFLAGS
+    #define INT_MASK         RTC_OVF_bm
+
+/* Hertz to period for RTC setup */
+    #define RTC_PERIOD_HZ( x )    ( 32768 * ( ( 1.0 / x ) ) )
+    #define TICK_init()                                        \
+    {                                                          \
+        while( RTC.STATUS > 0 ) {; }                           \
+        RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \
+        RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ );         \
+        RTC.INTCTRL |= 1 << RTC_OVF_bp;                        \
+    }
+
+#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */
+    #undef TICK_INT_vect
+    #undef INT_FLAGS
+    #undef INT_MASK
+    #undef TICK_init()
+    #error Invalid timer setting.
+#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */
+
+/*-----------------------------------------------------------*/
+
+#endif /* PORTHARDWARE_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_AVRDx/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_AVRDx/portmacro.h
new file mode 100644
index 0000000..c0bc803
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_AVRDx/portmacro.h
@@ -0,0 +1,108 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR                 char
+#define portFLOAT                float
+#define portDOUBLE               double
+#define portLONG                 long
+#define portSHORT                int
+#define portSTACK_TYPE           uint8_t
+#define portBASE_TYPE            char
+
+#define portPOINTER_SIZE_TYPE    uint16_t
+
+typedef portSTACK_TYPE   StackType_t;
+typedef signed char      BaseType_t;
+typedef unsigned char    UBaseType_t;
+
+#if ( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#else
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()        vPortEnterCritical()
+#define portEXIT_CRITICAL()         vPortExitCritical()
+
+#define portDISABLE_INTERRUPTS()    asm ( "cli" )
+#define portENABLE_INTERRUPTS()     asm ( "sei" )
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    1
+#define portNOP()    asm ( "nop" )
+/*-----------------------------------------------------------*/
+
+/* Kernel utilities. */
+extern void vPortYield( void );
+#define portYIELD()             vPortYield()
+
+extern void vPortYieldFromISR( void );
+#define portYIELD_FROM_ISR()    vPortYieldFromISR()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_AVRDx/portmacro.s90 b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_AVRDx/portmacro.s90
new file mode 100644
index 0000000..27400d5
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_AVRDx/portmacro.s90
@@ -0,0 +1,253 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; */
+
+#include "porthardware.h"
+
+; Declare all extern symbols here - including any ISRs that are referenced in
+; the vector table.
+
+; ISR functions
+; -------------
+EXTERN TICK_INT
+
+; Functions used by scheduler
+; ---------------------------
+EXTERN vTaskSwitchContext
+EXTERN pxCurrentTCB
+EXTERN xTaskIncrementTick
+EXTERN uxCriticalNesting
+
+; Functions implemented in this file
+; ----------------------------------
+PUBLIC vPortYield
+PUBLIC vPortYieldFromTick
+PUBLIC vPortYieldFromISR
+PUBLIC vPortStart
+
+; Interrupt vector table.
+; -----------------------
+;
+; For simplicity the RTOS tick interrupt routine uses the __task keyword.
+; As the IAR compiler does not permit a function to be declared using both
+; __task and __interrupt, the use of __task necessitates that the interrupt
+; vector table be setup manually.
+;
+; To write an ISR, implement the ISR function using the __interrupt keyword
+; but do not install the interrupt using the "#pragma vector=ABC" method.
+; Instead manually place the name of the ISR in the vector table using an
+; ORG and jmp instruction as demonstrated below.
+; You will also have to add an EXTERN statement at the top of the file.
+
+    ASEG
+
+        ORG TICK_INT_vect                   ; Vector address
+            jmp TICK_INT                    ; ISR
+
+    RSEG CODE
+
+CLR_INT MACRO  FLAG_REG, FLAG_MASK
+        st -y, r16
+        ldi r16, FLAG_MASK
+        sts FLAG_REG, r16
+        ld r16, y+
+        
+        ENDM
+
+; Saving and Restoring a Task Context and Task Switching
+; ------------------------------------------------------
+;
+; The IAR compiler does not fully support inline assembler, so saving and
+; restoring a task context has to be written in an asm file.
+;
+; vPortYield() and vPortYieldFromTick() are usually written in C.  Doing
+; so in this case would required calls to be made to portSAVE_CONTEXT() and
+; portRESTORE_CONTEXT().  This is dis-advantageous as the context switch
+; function would require two extra jump and return instructions over the
+; WinAVR equivalent.
+;
+; To avoid this I have opted to implement both vPortYield() and
+; vPortYieldFromTick() in this assembly file.  For convenience
+; portSAVE_CONTEXT and portRESTORE_CONTEXT are implemented as macros.
+
+portSAVE_CONTEXT MACRO
+    st  -y, r0          ; First save the r0 register - we need to use this.
+    in  r0, SREG        ; Obtain the SREG value so we can disable interrupts...
+    cli                 ; ... as soon as possible.
+    st  -y, r0          ; Store the SREG as it was before we disabled interrupts.
+
+    in  r0, RAMPZ
+    st  -y, r0
+
+    in  r0, SPL         ; Next store the hardware stack pointer.  The IAR...
+    st  -y, r0          ; ... compiler uses the hardware stack as a call stack ...
+    in  r0, SPH         ; ...  only.
+    st  -y, r0
+
+    st  -y, r1          ; Now store the rest of the registers.  Dont store the ...
+    st  -y, r2          ; ... the Y register here as it is used as the software
+    st  -y, r3          ; stack pointer and will get saved into the TCB.
+    st  -y, r4
+    st  -y, r5
+    st  -y, r6
+    st  -y, r7
+    st  -y, r8
+    st  -y, r9
+    st  -y, r10
+    st  -y, r11
+    st  -y, r12
+    st  -y, r13
+    st  -y, r14
+    st  -y, r15
+    st  -y, r16
+    st  -y, r17
+    st  -y, r18
+    st  -y, r19
+    st  -y, r20
+    st  -y, r21
+    st  -y, r22
+    st  -y, r23
+    st  -y, r24
+    st  -y, r25
+    st  -y, r26
+    st  -y, r27
+    st  -y, r30
+    st  -y, r31
+
+    lds r0, uxCriticalNesting
+    st  -y, r0                  ; Store the critical nesting counter.
+
+    lds r26, pxCurrentTCB       ; Finally save the software stack pointer (Y ...
+    lds r27, pxCurrentTCB + 1   ; ... register) into the TCB.
+    st  x+, r28
+    st  x+, r29
+
+    ENDM
+
+
+portRESTORE_CONTEXT MACRO
+    lds r26, pxCurrentTCB
+    lds r27, pxCurrentTCB + 1       ; Restore the software stack pointer from ...
+    ld  r28, x+                     ; the TCB into the software stack pointer (...
+    ld  r29, x+                     ; ... the Y register).
+
+    ld  r0, y+
+    sts uxCriticalNesting, r0
+
+    ld  r31, y+                     ; Restore the registers down to R0.  The Y
+    ld  r30, y+                     ; register is missing from this list as it
+    ld  r27, y+                     ; has already been restored.
+    ld  r26, y+
+    ld  r25, y+
+    ld  r24, y+
+    ld  r23, y+
+    ld  r22, y+
+    ld  r21, y+
+    ld  r20, y+
+    ld  r19, y+
+    ld  r18, y+
+    ld  r17, y+
+    ld  r16, y+
+    ld  r15, y+
+    ld  r14, y+
+    ld  r13, y+
+    ld  r12, y+
+    ld  r11, y+
+    ld  r10, y+
+    ld  r9, y+
+    ld  r8, y+
+    ld  r7, y+
+    ld  r6, y+
+    ld  r5, y+
+    ld  r4, y+
+    ld  r3, y+
+    ld  r2, y+
+    ld  r1, y+
+
+    ld  r0, y+                      ; The next thing on the stack is the ...
+    out SPH, r0                     ; ... hardware stack pointer.
+    ld  r0, y+
+    out SPL, r0
+
+    ld  r0, y+
+    out RAMPZ, r0
+
+    ld  r0, y+                      ; Next there is the SREG register.
+    out SREG, r0
+
+    ld  r0, y+                      ; Finally we have finished with r0, so restore r0.
+
+    ENDM
+
+
+
+; vPortYield(), vPortYieldFromTick() and vPortYieldFromISR()
+; -------------------------------------
+;
+; Manual and preemptive context switch functions respectively.
+; The IAR compiler does not fully support inline assembler,
+; so these are implemented here rather than the more usually
+; place of within port.c.
+
+vPortYield:
+    portSAVE_CONTEXT                ; Save the context of the current task.
+    call vTaskSwitchContext         ; Call the scheduler.
+    portRESTORE_CONTEXT             ; Restore the context of whichever task the ...
+    ret                             ; ... scheduler decided should run.
+
+vPortYieldFromTick:
+    CLR_INT INT_FLAGS, INT_MASK     ; Clear tick interrupt flag
+
+    portSAVE_CONTEXT                ; Save the context of the current task.    
+    call xTaskIncrementTick         ; Call the timer tick function.
+    tst r16
+    breq SkipTaskSwitch
+    call vTaskSwitchContext         ; Call the scheduler.
+
+SkipTaskSwitch:
+    portRESTORE_CONTEXT             ; Restore the context of whichever task the ...
+    reti                            ; ... scheduler decided should run.
+
+vPortYieldFromISR:
+    portSAVE_CONTEXT                ; Save the context of the current task.
+    call vTaskSwitchContext         ; Call the scheduler.
+    portRESTORE_CONTEXT             ; Restore the context of whichever task the ...
+    reti                            ; ... scheduler decided should run.
+
+; vPortStart()
+; ------------
+;
+; Again due to the lack of inline assembler, this is required
+; to get access to the portRESTORE_CONTEXT macro.
+
+vPortStart:
+    portRESTORE_CONTEXT
+    ret
+
+; Just a filler for unused interrupt vectors.
+vNoISR:
+    reti
+
+    END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_Mega0/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_Mega0/port.c
new file mode 100644
index 0000000..8520d41
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_Mega0/port.c
@@ -0,0 +1,298 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include <stdlib.h>
+#include "porthardware.h"
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the AVR port.
+*----------------------------------------------------------*/
+
+/* Start tasks with interrupts enables. */
+#define portFLAGS_INT_ENABLED    ( ( StackType_t ) 0x80 )
+
+/*-----------------------------------------------------------*/
+
+
+#define portBYTES_USED_BY_RETURN_ADDRESS    2
+#define portNO_CRITICAL_NESTING             ( ( UBaseType_t ) 0 )
+
+/* Stores the critical section nesting.  This must not be initialised to 0.
+ * It will be initialised when a task starts. */
+UBaseType_t uxCriticalNesting = 0x50;
+
+/*
+ * Setup timer to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * The IAR compiler does not have full support for inline assembler, so
+ * these are defined in the portmacro assembler file.
+ */
+extern void vPortYieldFromTick( void );
+extern void vPortStart( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    uint16_t usAddress;
+    StackType_t * pxTopOfHardwareStack;
+
+    /* Simulate how the stack would look after a call to vPortYield(). */
+
+    /*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+
+    /* The IAR compiler requires two stacks per task.  First there is the
+     * hardware call stack which uses the AVR stack pointer.  Second there is the
+     * software stack (local variables, parameter passing, etc.) which uses the
+     * AVR Y register.
+     * This function places both stacks within the memory block passed in as the
+     * first parameter.  The hardware stack is placed at the bottom of the memory
+     * block.  A gap is then left for the hardware stack to grow.  Next the software
+     * stack is placed.  The amount of space between the software and hardware
+     * stacks is defined by configCALL_STACK_SIZE.
+     * The first part of the stack is the hardware stack.  Place the start
+     * address of the task on the hardware stack. */
+
+    /* Place a few bytes of known values on the bottom of the stack.
+     * This is just useful for debugging. */
+    /**pxTopOfStack = 0x11; */
+    /*pxTopOfStack--; */
+    /**pxTopOfStack = 0x22; */
+    /*pxTopOfStack--; */
+    /**pxTopOfStack = 0x33; */
+    /*pxTopOfStack--; */
+
+    /* Remember where the top of the hardware stack is - this is required
+     * below. */
+    pxTopOfHardwareStack = pxTopOfStack;
+
+    usAddress = ( uint16_t ) pxCode;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    /* Leave enough space for the hardware stack before starting the software
+     * stack.  The '- 2' is because we have already used two spaces for the
+     * address of the start of the task. */
+    pxTopOfStack -= ( configCALL_STACK_SIZE - 2 );
+
+    /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
+     *  portSAVE_CONTEXT places the flags on the stack immediately after r0
+     *  to ensure the interrupts get disabled as soon as possible, and so ensuring
+     *  the stack use is minimal should a context switch interrupt occur. */
+
+    *pxTopOfStack = ( StackType_t ) 0x00; /* R0 */
+    pxTopOfStack--;
+    *pxTopOfStack = portFLAGS_INT_ENABLED;
+    pxTopOfStack--;
+
+    /* Next place the address of the hardware stack.  This is required so
+     * the AVR stack pointer can be restored to point to the hardware stack. */
+    pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS;
+    usAddress = ( uint16_t ) pxTopOfHardwareStack;
+
+    /* SPL */
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    /* SPH */
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    /* Now the remaining registers. */
+    *pxTopOfStack = ( StackType_t ) 0x01; /* R1 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x02; /* R2 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x03; /* R3 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x04; /* R4 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x05; /* R5 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x06; /* R6 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x07; /* R7 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x08; /* R8 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x09; /* R9 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x10; /* R10 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x11; /* R11 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x12; /* R12 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x13; /* R13 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x14; /* R14 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x15; /* R15 */
+    pxTopOfStack--;
+
+    /* Place the parameter on the stack in the expected location. */
+    usAddress = ( uint16_t ) pvParameters;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    *pxTopOfStack = ( StackType_t ) 0x18; /* R18 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x19; /* R19 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x20; /* R20 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x21; /* R21 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x22; /* R22 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x23; /* R23 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x24; /* R24 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x25; /* R25 */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x26; /* R26 X */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x27; /* R27 */
+    pxTopOfStack--;
+
+    /* The Y register is not stored as it is used as the software stack and
+     * gets saved into the task control block. */
+
+    *pxTopOfStack = ( StackType_t ) 0x30;  /* R30 Z */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) 0x031; /* R31 */
+
+    pxTopOfStack--;
+    *pxTopOfStack = portNO_CRITICAL_NESTING; /* Critical nesting is zero when the task starts. */
+
+    /*lint +e950 +e611 +e923 */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+    /* Setup the hardware to generate the tick. */
+    prvSetupTimerInterrupt();
+
+    /* Restore the context of the first task that is going to run.
+     * Normally we would just call portRESTORE_CONTEXT() here, but as the IAR
+     * compiler does not fully support inline assembler we have to make a call.*/
+    vPortStart();
+
+    /* Should not get here. */
+    return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* vPortEndScheduler is not implemented in this port. */
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup timer to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+    TICK_init();
+}
+
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 1
+
+/*
+ * Tick ISR for preemptive scheduler.  We can use a naked attribute as
+ * the context is saved at the start of vPortYieldFromTick().  The tick
+ * count is incremented after the context is saved.
+ */
+
+    __task void TICK_INT( void )
+    {
+        vPortYieldFromTick();
+        asm ( "reti" );
+    }
+#else
+
+/*
+ * Tick ISR for the cooperative scheduler.  All this does is increment the
+ * tick count.  We don't need to switch context, this can only be done by
+ * manual calls to taskYIELD();
+ */
+
+    __interrupt void TICK_INT( void )
+    {
+        /* Clear tick interrupt flag. */
+        INT_FLAGS = INT_MASK;
+
+        xTaskIncrementTick();
+    }
+#endif /* if configUSE_PREEMPTION == 1 */
+
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == portNO_CRITICAL_NESTING )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_Mega0/porthardware.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_Mega0/porthardware.h
new file mode 100644
index 0000000..793d589
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_Mega0/porthardware.h
@@ -0,0 +1,89 @@
+#ifndef PORTHARDWARE_H
+#define PORTHARDWARE_H
+
+#ifndef __IAR_SYSTEMS_ASM__
+    #include <ioavr.h>
+#endif
+#include "FreeRTOSConfig.h"
+
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMER_INSTANCE == 0 )
+
+    #define TICK_INT_vect    TCB0_INT_vect
+    #define INT_FLAGS        TCB0_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB0.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB0.INTCTRL = TCB_CAPT_bm;                          \
+        TCB0.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 1 )
+
+    #define TICK_INT_vect    TCB1_INT_vect
+    #define INT_FLAGS        TCB1_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB1.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB1.INTCTRL = TCB_CAPT_bm;                          \
+        TCB1.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 2 )
+
+    #define TICK_INT_vect    TCB2_INT_vect
+    #define INT_FLAGS        TCB2_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB2.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB2.INTCTRL = TCB_CAPT_bm;                          \
+        TCB2.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 3 )
+
+    #define TICK_INT_vect    TCB3_INT_vect
+    #define INT_FLAGS        TCB3_INTFLAGS
+    #define INT_MASK         TCB_CAPT_bm
+
+    #define TICK_init()                                      \
+    {                                                        \
+        TCB3.CCMP = configCPU_CLOCK_HZ / configTICK_RATE_HZ; \
+        TCB3.INTCTRL = TCB_CAPT_bm;                          \
+        TCB3.CTRLA = TCB_ENABLE_bm;                          \
+    }
+
+#elif ( configUSE_TIMER_INSTANCE == 4 )
+
+    #define TICK_INT_vect    RTC_CNT_vect
+    #define INT_FLAGS        RTC_INTFLAGS
+    #define INT_MASK         RTC_OVF_bm
+
+/* Hertz to period for RTC setup */
+    #define RTC_PERIOD_HZ( x )    ( 32768 * ( ( 1.0 / x ) ) )
+    #define TICK_init()                                        \
+    {                                                          \
+        while( RTC.STATUS > 0 ) {; }                           \
+        RTC.CTRLA = RTC_PRESCALER_DIV1_gc | 1 << RTC_RTCEN_bp; \
+        RTC.PER = RTC_PERIOD_HZ( configTICK_RATE_HZ );         \
+        RTC.INTCTRL |= 1 << RTC_OVF_bp;                        \
+    }
+
+#else /* if ( configUSE_TIMER_INSTANCE == 0 ) */
+    #undef TICK_INT_vect
+    #undef INT_FLAGS
+    #undef INT_MASK
+    #undef TICK_init()
+    #error Invalid timer setting.
+#endif /* if ( configUSE_TIMER_INSTANCE == 0 ) */
+
+/*-----------------------------------------------------------*/
+
+#endif /* PORTHARDWARE_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_Mega0/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_Mega0/portmacro.h
new file mode 100644
index 0000000..c0bc803
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_Mega0/portmacro.h
@@ -0,0 +1,108 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR                 char
+#define portFLOAT                float
+#define portDOUBLE               double
+#define portLONG                 long
+#define portSHORT                int
+#define portSTACK_TYPE           uint8_t
+#define portBASE_TYPE            char
+
+#define portPOINTER_SIZE_TYPE    uint16_t
+
+typedef portSTACK_TYPE   StackType_t;
+typedef signed char      BaseType_t;
+typedef unsigned char    UBaseType_t;
+
+#if ( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffff
+#else
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()        vPortEnterCritical()
+#define portEXIT_CRITICAL()         vPortExitCritical()
+
+#define portDISABLE_INTERRUPTS()    asm ( "cli" )
+#define portENABLE_INTERRUPTS()     asm ( "sei" )
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH      ( -1 )
+#define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT    1
+#define portNOP()    asm ( "nop" )
+/*-----------------------------------------------------------*/
+
+/* Kernel utilities. */
+extern void vPortYield( void );
+#define portYIELD()             vPortYield()
+
+extern void vPortYieldFromISR( void );
+#define portYIELD_FROM_ISR()    vPortYieldFromISR()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_Mega0/portmacro.s90 b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_Mega0/portmacro.s90
new file mode 100644
index 0000000..6ffbef0
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AVR_Mega0/portmacro.s90
@@ -0,0 +1,248 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+#include "porthardware.h"
+
+; Declare all extern symbols here - including any ISRs that are referenced in
+; the vector table.
+
+; ISR functions
+; -------------
+EXTERN TICK_INT
+
+; Functions used by scheduler
+; ---------------------------
+EXTERN vTaskSwitchContext
+EXTERN pxCurrentTCB
+EXTERN xTaskIncrementTick
+EXTERN uxCriticalNesting
+
+; Functions implemented in this file
+; ----------------------------------
+PUBLIC vPortYield
+PUBLIC vPortYieldFromTick
+PUBLIC vPortYieldFromISR
+PUBLIC vPortStart
+
+; Interrupt vector table.
+; -----------------------
+;
+; For simplicity the RTOS tick interrupt routine uses the __task keyword.
+; As the IAR compiler does not permit a function to be declared using both
+; __task and __interrupt, the use of __task necessitates that the interrupt
+; vector table be setup manually.
+;
+; To write an ISR, implement the ISR function using the __interrupt keyword
+; but do not install the interrupt using the "#pragma vector=ABC" method.
+; Instead manually place the name of the ISR in the vector table using an
+; ORG and jmp instruction as demonstrated below.
+; You will also have to add an EXTERN statement at the top of the file.
+
+    ASEG
+
+    ORG TICK_INT_vect                   ; Vector address
+        jmp TICK_INT                    ; ISR
+
+    RSEG CODE
+
+CLR_INT MACRO  FLAG_REG, FLAG_MASK
+    st -y, r16
+    ldi r16, FLAG_MASK
+    sts FLAG_REG, r16
+    ld r16, y+
+        
+    ENDM
+
+; Saving and Restoring a Task Context and Task Switching
+; ------------------------------------------------------
+;
+; The IAR compiler does not fully support inline assembler, so saving and
+; restoring a task context has to be written in an asm file.
+;
+; vPortYield() and vPortYieldFromTick() are usually written in C.  Doing
+; so in this case would required calls to be made to portSAVE_CONTEXT() and
+; portRESTORE_CONTEXT().  This is dis-advantageous as the context switch
+; function would require two extra jump and return instructions over the
+; WinAVR equivalent.
+;
+; To avoid this I have opted to implement both vPortYield() and
+; vPortYieldFromTick() in this assembly file.  For convenience
+; portSAVE_CONTEXT and portRESTORE_CONTEXT are implemented as macros.
+
+portSAVE_CONTEXT MACRO
+    st  -y, r0          ; First save the r0 register - we need to use this.
+    in  r0, SREG        ; Obtain the SREG value so we can disable interrupts...
+    cli                 ; ... as soon as possible.
+    st  -y, r0          ; Store the SREG as it was before we disabled interrupts.
+
+    in  r0, SPL         ; Next store the hardware stack pointer.  The IAR...
+    st  -y, r0          ; ... compiler uses the hardware stack as a call stack ...
+    in  r0, SPH         ; ...  only.
+    st  -y, r0
+
+    st  -y, r1          ; Now store the rest of the registers.  Dont store the ...
+    st  -y, r2          ; ... the Y register here as it is used as the software
+    st  -y, r3          ; stack pointer and will get saved into the TCB.
+    st  -y, r4
+    st  -y, r5
+    st  -y, r6
+    st  -y, r7
+    st  -y, r8
+    st  -y, r9
+    st  -y, r10
+    st  -y, r11
+    st  -y, r12
+    st  -y, r13
+    st  -y, r14
+    st  -y, r15
+    st  -y, r16
+    st  -y, r17
+    st  -y, r18
+    st  -y, r19
+    st  -y, r20
+    st  -y, r21
+    st  -y, r22
+    st  -y, r23
+    st  -y, r24
+    st  -y, r25
+    st  -y, r26
+    st  -y, r27
+    st  -y, r30
+    st  -y, r31
+        
+    lds r0, uxCriticalNesting
+    st  -y, r0                  ; Store the critical nesting counter.
+
+    lds r26, pxCurrentTCB       ; Finally save the software stack pointer (Y ...
+    lds r27, pxCurrentTCB + 1   ; ... register) into the TCB.
+    st  x+, r28
+    st  x+, r29
+
+    ENDM
+
+
+portRESTORE_CONTEXT MACRO
+    lds r26, pxCurrentTCB
+    lds r27, pxCurrentTCB + 1       ; Restore the software stack pointer from ...
+    ld  r28, x+                     ; the TCB into the software stack pointer (...
+    ld  r29, x+                     ; ... the Y register).
+
+    ld  r0, y+
+    sts uxCriticalNesting, r0
+
+    ld  r31, y+                     ; Restore the registers down to R0.  The Y
+    ld  r30, y+                     ; register is missing from this list as it
+    ld  r27, y+                     ; has already been restored.
+    ld  r26, y+
+    ld  r25, y+
+    ld  r24, y+
+    ld  r23, y+
+    ld  r22, y+
+    ld  r21, y+
+    ld  r20, y+
+    ld  r19, y+
+    ld  r18, y+
+    ld  r17, y+
+    ld  r16, y+
+    ld  r15, y+
+    ld  r14, y+
+    ld  r13, y+
+    ld  r12, y+
+    ld  r11, y+
+    ld  r10, y+
+    ld  r9, y+
+    ld  r8, y+
+    ld  r7, y+
+    ld  r6, y+
+    ld  r5, y+
+    ld  r4, y+
+    ld  r3, y+
+    ld  r2, y+
+    ld  r1, y+
+
+    ld  r0, y+                      ; The next thing on the stack is the ...
+    out SPH, r0                     ; ... hardware stack pointer.
+    ld  r0, y+
+    out SPL, r0
+
+    ld  r0, y+                      ; Next there is the SREG register.
+    out SREG, r0
+
+    ld  r0, y+                      ; Finally we have finished with r0, so restore r0.
+
+    ENDM
+
+
+
+; vPortYield(), vPortYieldFromTick() and vPortYieldFromISR()
+; -------------------------------------
+;
+; Manual and preemptive context switch functions respectively.
+; The IAR compiler does not fully support inline assembler,
+; so these are implemented here rather than the more usually
+; place of within port.c.
+
+vPortYield:
+    portSAVE_CONTEXT                ; Save the context of the current task.
+    call vTaskSwitchContext         ; Call the scheduler.
+    portRESTORE_CONTEXT             ; Restore the context of whichever task the ...
+    ret                             ; ... scheduler decided should run.
+
+vPortYieldFromTick:
+    CLR_INT INT_FLAGS, INT_MASK     ; Clear tick interrupt flag
+ 
+    portSAVE_CONTEXT                ; Save the context of the current task.
+    call xTaskIncrementTick         ; Call the timer tick function.
+    tst r16
+    breq SkipTaskSwitch
+    call vTaskSwitchContext         ; Call the scheduler.
+
+SkipTaskSwitch:
+    portRESTORE_CONTEXT             ; Restore the context of whichever task the ...
+    reti                            ; ... scheduler decided should run.
+
+vPortYieldFromISR:
+    portSAVE_CONTEXT                ; Save the context of the current task.
+    call vTaskSwitchContext         ; Call the scheduler.
+    portRESTORE_CONTEXT             ; Restore the context of whichever task the ...
+    reti                            ; ... scheduler decided should run.
+
+; vPortStart()
+; ------------
+;
+; Again due to the lack of inline assembler, this is required
+; to get access to the portRESTORE_CONTEXT macro.
+
+vPortStart:
+        portRESTORE_CONTEXT
+        ret
+
+; Just a filler for unused interrupt vectors.
+vNoISR:
+    reti
+
+END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
new file mode 100644
index 0000000..8f9ddb4
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
@@ -0,0 +1,1914 @@
+// ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ----------------------------------------------------------------------------
+//  The software is delivered "AS IS" without warranty or condition of any
+//  kind, either express, implied or statutory. This includes without
+//  limitation any warranty or condition with respect to merchantability or
+//  fitness for any particular purpose, or against the infringements of
+//  intellectual property rights of others.
+// ----------------------------------------------------------------------------
+// File Name           : AT91SAM7S64.h
+// Object              : AT91SAM7S64 definitions
+// Generated           : AT91 SW Application Group  07/16/2004 (07:43:08)
+// 
+// CVS Reference       : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004//
+// CVS Reference       : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004//
+// CVS Reference       : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004//
+// CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug  2 14:45:38 2002//
+// CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
+// CVS Reference       : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
+// CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
+// CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
+// CVS Reference       : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004//
+// CVS Reference       : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//
+// CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov  8 13:26:40 2002//
+// CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+// CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb  7 10:30:08 2003//
+// CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//
+// CVS Reference       : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//
+// CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+// ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7S64_H
+#define AT91SAM7S64_H
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYSC {
+	AT91_REG	 SYSC_AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 SYSC_AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 SYSC_AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 SYSC_AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 SYSC_AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 SYSC_AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 SYSC_AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 SYSC_AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SYSC_AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 SYSC_AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 SYSC_AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 SYSC_AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 SYSC_AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 SYSC_AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 SYSC_AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 SYSC_AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 SYSC_AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 SYSC_AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved2[45]; 	// 
+	AT91_REG	 SYSC_DBGU_CR; 	// Control Register
+	AT91_REG	 SYSC_DBGU_MR; 	// Mode Register
+	AT91_REG	 SYSC_DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 SYSC_DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SYSC_DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 SYSC_DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 SYSC_DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 SYSC_DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 SYSC_DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved3[7]; 	// 
+	AT91_REG	 SYSC_DBGU_C1R; 	// Chip ID1 Register
+	AT91_REG	 SYSC_DBGU_C2R; 	// Chip ID2 Register
+	AT91_REG	 SYSC_DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved4[45]; 	// 
+	AT91_REG	 SYSC_DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 SYSC_DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 SYSC_DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SYSC_DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 SYSC_DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SYSC_DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SYSC_DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SYSC_DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SYSC_DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SYSC_DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved5[54]; 	// 
+	AT91_REG	 SYSC_PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 SYSC_PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 SYSC_PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved6[1]; 	// 
+	AT91_REG	 SYSC_PIOA_OER; 	// Output Enable Register
+	AT91_REG	 SYSC_PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 SYSC_PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved7[1]; 	// 
+	AT91_REG	 SYSC_PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 SYSC_PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 SYSC_PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved8[1]; 	// 
+	AT91_REG	 SYSC_PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 SYSC_PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 SYSC_PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 SYSC_PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 SYSC_PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 SYSC_PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SYSC_PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 SYSC_PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 SYSC_PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 SYSC_PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 SYSC_PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved9[1]; 	// 
+	AT91_REG	 SYSC_PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 SYSC_PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 SYSC_PIOA_PPUSR; 	// Pad Pull-up Status Register
+	AT91_REG	 Reserved10[1]; 	// 
+	AT91_REG	 SYSC_PIOA_ASR; 	// Select A Register
+	AT91_REG	 SYSC_PIOA_BSR; 	// Select B Register
+	AT91_REG	 SYSC_PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved11[9]; 	// 
+	AT91_REG	 SYSC_PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 SYSC_PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 SYSC_PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved12[469]; 	// 
+	AT91_REG	 SYSC_PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 SYSC_PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 SYSC_PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved13[1]; 	// 
+	AT91_REG	 SYSC_PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 SYSC_PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 SYSC_PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved14[1]; 	// 
+	AT91_REG	 SYSC_PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 SYSC_PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved15[1]; 	// 
+	AT91_REG	 SYSC_PMC_PLLR; 	// PLL Register
+	AT91_REG	 SYSC_PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved16[3]; 	// 
+	AT91_REG	 SYSC_PMC_PCKR[8]; 	// Programmable Clock Register
+	AT91_REG	 SYSC_PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SYSC_PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SYSC_PMC_SR; 	// Status Register
+	AT91_REG	 SYSC_PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved17[36]; 	// 
+	AT91_REG	 SYSC_RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 SYSC_RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 SYSC_RSTC_RMR; 	// Reset Mode Register
+	AT91_REG	 Reserved18[5]; 	// 
+	AT91_REG	 SYSC_RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 SYSC_RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 SYSC_RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 SYSC_RTTC_RTSR; 	// Real-time Status Register
+	AT91_REG	 SYSC_PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 SYSC_PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 SYSC_PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 SYSC_PITC_PIIR; 	// Period Interval Image Register
+	AT91_REG	 SYSC_WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 SYSC_WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 SYSC_WDTC_WDSR; 	// Watchdog Status Register
+	AT91_REG	 Reserved19[5]; 	// 
+	AT91_REG	 SYSC_SYSC_VRPM; 	// Voltage Regulator Power Mode Register
+} AT91S_SYSC, *AT91PS_SYSC;
+
+// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- 
+#define AT91C_SYSC_PSTDBY     ((unsigned int) 0x1 <<  0) // (SYSC) Voltage Regulator Power Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       ((unsigned int) 0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    ((unsigned int) 0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved0[7]; 	// 
+	AT91_REG	 DBGU_C1R; 	// Chip ID1 Register
+	AT91_REG	 DBGU_C2R; 	// Chip ID2 Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved1[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral Data Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved3[1]; 	// 
+	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIO_PPUSR; 	// Pad Pull-up Status Register
+	AT91_REG	 Reserved4[1]; 	// 
+	AT91_REG	 PIO_ASR; 	// Select A Register
+	AT91_REG	 PIO_BSR; 	// Select B Register
+	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved5[9]; 	// 
+	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 CKGR_PLLR; 	// PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved3[3]; 	// 
+	AT91_REG	 PMC_PCKR[8]; 	// Programmable Clock Register
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_SYSC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_SYSC_ICERST     ((unsigned int) 0x1 <<  1) // (RSTC) ICE Interface Reset
+#define AT91C_SYSC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_SYSC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
+#define AT91C_SYSC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_SYSC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_SYSC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brown-out Detection Status
+#define AT91C_SYSC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_SYSC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_SYSC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_SYSC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_SYSC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_SYSC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brown-out Reset.
+#define AT91C_SYSC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_SYSC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_SYSC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_SYSC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_SYSC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_SYSC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_SYSC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_SYSC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_SYSC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_SYSC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_SYSC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
+// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_SYSC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_SYSC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_SYSC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_SYSC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_SYSC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_SYSC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_SYSC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_SYSC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_SYSC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_SYSC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
+// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_SYSC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_SYSC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_SYSC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_SYSC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_SYSC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_SYSC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_SYSC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_SYSC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_SYSC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_SYSC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+	AT91_REG	 MC_RCR; 	// MC Remap Control Register
+	AT91_REG	 MC_ASR; 	// MC Abort Status Register
+	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
+	AT91_REG	 Reserved0[21]; 	// 
+	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
+	AT91_REG	 MC_FCR; 	// MC Flash Command Register
+	AT91_REG	 MC_FSR; 	// MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91_REG	 Reserved1[48]; 	// 
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+	AT91_REG	 ADC_CR; 	// ADC Control Register
+	AT91_REG	 ADC_MR; 	// ADC Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
+	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
+	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
+	AT91_REG	 ADC_SR; 	// ADC Status Register
+	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
+	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
+	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
+	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
+	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
+	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
+	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
+	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
+	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
+	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
+	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
+	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
+	AT91_REG	 ADC_RCR; 	// Receive Counter Register
+	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
+	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 SSC_RC0R; 	// Receive Compare 0 Register
+	AT91_REG	 SSC_RC1R; 	// Receive Compare 1 Register
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_CKG         ((unsigned int) 0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection
+#define 	AT91C_SSC_CKG_NONE                 ((unsigned int) 0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
+#define 	AT91C_SSC_CKG_LOW                  ((unsigned int) 0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low
+#define 	AT91C_SSC_CKG_HIGH                 ((unsigned int) 0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High
+#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STOP        ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection
+#define AT91C_SSC_STTOUT      ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
+#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_CP0         ((unsigned int) 0x1 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_CP1         ((unsigned int) 0x1 <<  9) // (SSC) Compare 1
+#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	// 
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 US_XXR; 	// XON_XOFF Register
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (USART) Reset Status Bits
+#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 TWI_SMR; 	// Slave Mode Register
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved0[3]; 	// 
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SVEN        ((unsigned int) 0x1 <<  4) // (TWI) TWI Slave Transfer Enabled
+#define AT91C_TWI_SVDIS       ((unsigned int) 0x1 <<  5) // (TWI) TWI Slave Transfer Disabled
+#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- 
+#define AT91C_TWI_SADR        ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_SVREAD      ((unsigned int) 0x1 <<  3) // (TWI) Slave Read
+#define AT91C_TWI_SVACC       ((unsigned int) 0x1 <<  4) // (TWI) Slave Access
+#define AT91C_TWI_GCACC       ((unsigned int) 0x1 <<  5) // (TWI) General Call Access
+#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
+#define AT91C_TWI_ARBLST      ((unsigned int) 0x1 <<  9) // (TWI) Arbitration Lost
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_NONE                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_RISING               ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_FALLING              ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_BOTH                 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
+#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRCS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_ETRGS        ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x1 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x1 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x1 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA2                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
+	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
+	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
+	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
+	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
+	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
+	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
+	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
+	AT91_REG	 PWMC_SR; 	// PWMC Status Register
+	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
+	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
+	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
+	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
+	AT91_REG	 Reserved0[55]; 	// 
+	AT91_REG	 PWMC_VR; 	// PWMC Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_PWMC_CH	 PWMC_CH[32]; 	// PWMC Channel 0
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
+#define AT91C_PWMC_CHID4      ((unsigned int) 0x1 <<  4) // (PWMC) Channel ID 4
+#define AT91C_PWMC_CHID5      ((unsigned int) 0x1 <<  5) // (PWMC) Channel ID 5
+#define AT91C_PWMC_CHID6      ((unsigned int) 0x1 <<  6) // (PWMC) Channel ID 6
+#define AT91C_PWMC_CHID7      ((unsigned int) 0x1 <<  7) // (PWMC) Channel ID 7
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 UDP_CSR[8]; 	// Endpoint Control and Status Register
+	AT91_REG	 UDP_FDR[8]; 	// Endpoint FIFO Data Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  2) // (UDP) Remote Wake Up Enable
+#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_EPINT6      ((unsigned int) 0x1 <<  6) // (UDP) Endpoint 6 Interrupt
+#define AT91C_UDP_EPINT7      ((unsigned int) 0x1 <<  7) // (UDP) Endpoint 7 Interrupt
+#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
+#define AT91C_UDP_EP6         ((unsigned int) 0x1 <<  6) // (UDP) Reset Endpoint 6
+#define AT91C_UDP_EP7         ((unsigned int) 0x1 <<  7) // (UDP) Reset Endpoint 7
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
+// *****************************************************************************
+// ========== Register definition for SYSC peripheral ========== 
+#define AT91C_SYSC_SYSC_VRPM ((AT91_REG *) 	0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_C2R  ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID2 Register
+#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_C1R  ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID1 Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
+#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
+#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pad Pull-up Status Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
+#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
+#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
+// ========== Register definition for PDC_SPI peripheral ========== 
+#define AT91C_SPI_PTCR  ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
+#define AT91C_SPI_TNPR  ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
+#define AT91C_SPI_RNPR  ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
+#define AT91C_SPI_TPR   ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
+#define AT91C_SPI_RPR   ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI) Receive Pointer Register
+#define AT91C_SPI_PTSR  ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
+#define AT91C_SPI_TNCR  ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
+#define AT91C_SPI_RNCR  ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
+#define AT91C_SPI_TCR   ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI) Transmit Counter Register
+#define AT91C_SPI_RCR   ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI) Receive Counter Register
+// ========== Register definition for SPI peripheral ========== 
+#define AT91C_SPI_CSR   ((AT91_REG *) 	0xFFFE0030) // (SPI) Chip Select Register
+#define AT91C_SPI_IDR   ((AT91_REG *) 	0xFFFE0018) // (SPI) Interrupt Disable Register
+#define AT91C_SPI_SR    ((AT91_REG *) 	0xFFFE0010) // (SPI) Status Register
+#define AT91C_SPI_RDR   ((AT91_REG *) 	0xFFFE0008) // (SPI) Receive Data Register
+#define AT91C_SPI_CR    ((AT91_REG *) 	0xFFFE0000) // (SPI) Control Register
+#define AT91C_SPI_IMR   ((AT91_REG *) 	0xFFFE001C) // (SPI) Interrupt Mask Register
+#define AT91C_SPI_IER   ((AT91_REG *) 	0xFFFE0014) // (SPI) Interrupt Enable Register
+#define AT91C_SPI_TDR   ((AT91_REG *) 	0xFFFE000C) // (SPI) Transmit Data Register
+#define AT91C_SPI_MR    ((AT91_REG *) 	0xFFFE0004) // (SPI) Mode Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
+#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_RC0R  ((AT91_REG *) 	0xFFFD4038) // (SSC) Receive Compare 0 Register
+#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_RC1R  ((AT91_REG *) 	0xFFFD403C) // (SSC) Receive Compare 1 Register
+#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_XXR   ((AT91_REG *) 	0xFFFC4048) // (US1) XON_XOFF Register
+#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_XXR   ((AT91_REG *) 	0xFFFC0048) // (US0) XON_XOFF Register
+#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
+#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
+#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_SMR   ((AT91_REG *) 	0xFFFB8008) // (TWI) Slave Mode Register
+#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
+#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
+#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_CH3_CMR   ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+#define AT91C_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_CH2_CMR   ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_CH1_CMR   ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+#define AT91C_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_CH0_CMR   ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+#define AT91C_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
+#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_PWM0     ((unsigned int) AT91C_PIO_PA0) //  PWM Channel 0
+#define AT91C_PA0_TIOA0    ((unsigned int) AT91C_PIO_PA0) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_PWM1     ((unsigned int) AT91C_PIO_PA1) //  PWM Channel 1
+#define AT91C_PA1_TIOB0    ((unsigned int) AT91C_PIO_PA1) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_DTXD     ((unsigned int) AT91C_PIO_PA10) //  DBGU Debug Transmit Data
+#define AT91C_PA10_NPCS2    ((unsigned int) AT91C_PIO_PA10) //  SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_NPCS0    ((unsigned int) AT91C_PIO_PA11) //  SPI Peripheral Chip Select 0
+#define AT91C_PA11_PWM0     ((unsigned int) AT91C_PIO_PA11) //  PWM Channel 0
+#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_MISO     ((unsigned int) AT91C_PIO_PA12) //  SPI Master In Slave
+#define AT91C_PA12_PWM1     ((unsigned int) AT91C_PIO_PA12) //  PWM Channel 1
+#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_MOSI     ((unsigned int) AT91C_PIO_PA13) //  SPI Master Out Slave
+#define AT91C_PA13_PWM2     ((unsigned int) AT91C_PIO_PA13) //  PWM Channel 2
+#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_SPCK     ((unsigned int) AT91C_PIO_PA14) //  SPI Serial Clock
+#define AT91C_PA14_PWM3     ((unsigned int) AT91C_PIO_PA14) //  PWM Channel 3
+#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_TF       ((unsigned int) AT91C_PIO_PA15) //  SSC Transmit Frame Sync
+#define AT91C_PA15_TIOA1    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_TK       ((unsigned int) AT91C_PIO_PA16) //  SSC Transmit Clock
+#define AT91C_PA16_TIOB1    ((unsigned int) AT91C_PIO_PA16) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_TD       ((unsigned int) AT91C_PIO_PA17) //  SSC Transmit data
+#define AT91C_PA17_PCK1     ((unsigned int) AT91C_PIO_PA17) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_RD       ((unsigned int) AT91C_PIO_PA18) //  SSC Receive Data
+#define AT91C_PA18_PCK2     ((unsigned int) AT91C_PIO_PA18) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_RK       ((unsigned int) AT91C_PIO_PA19) //  SSC Receive Clock
+#define AT91C_PA19_FIQ      ((unsigned int) AT91C_PIO_PA19) //  AIC Fast Interrupt Input
+#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_PWM2     ((unsigned int) AT91C_PIO_PA2) //  PWM Channel 2
+#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_RF       ((unsigned int) AT91C_PIO_PA20) //  SSC Receive Frame Sync
+#define AT91C_PA20_IRQ0     ((unsigned int) AT91C_PIO_PA20) //  External Interrupt 0
+#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_RXD1     ((unsigned int) AT91C_PIO_PA21) //  USART 1 Receive Data
+#define AT91C_PA21_PCK1     ((unsigned int) AT91C_PIO_PA21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TXD1     ((unsigned int) AT91C_PIO_PA22) //  USART 1 Transmit Data
+#define AT91C_PA22_NPCS3    ((unsigned int) AT91C_PIO_PA22) //  SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_SCK1     ((unsigned int) AT91C_PIO_PA23) //  USART 1 Serial Clock
+#define AT91C_PA23_PWM0     ((unsigned int) AT91C_PIO_PA23) //  PWM Channel 0
+#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RTS1     ((unsigned int) AT91C_PIO_PA24) //  USART 1 Ready To Send
+#define AT91C_PA24_PWM1     ((unsigned int) AT91C_PIO_PA24) //  PWM Channel 1
+#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_CTS1     ((unsigned int) AT91C_PIO_PA25) //  USART 1 Clear To Send
+#define AT91C_PA25_PWM2     ((unsigned int) AT91C_PIO_PA25) //  PWM Channel 2
+#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_DCD1     ((unsigned int) AT91C_PIO_PA26) //  USART 1 Data Carrier Detect
+#define AT91C_PA26_TIOA2    ((unsigned int) AT91C_PIO_PA26) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DTR1     ((unsigned int) AT91C_PIO_PA27) //  USART 1 Data Terminal ready
+#define AT91C_PA27_TIOB2    ((unsigned int) AT91C_PIO_PA27) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DSR1     ((unsigned int) AT91C_PIO_PA28) //  USART 1 Data Set ready
+#define AT91C_PA28_TCLK1    ((unsigned int) AT91C_PIO_PA28) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_RI1      ((unsigned int) AT91C_PIO_PA29) //  USART 1 Ring Indicator
+#define AT91C_PA29_TCLK2    ((unsigned int) AT91C_PIO_PA29) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_TWD      ((unsigned int) AT91C_PIO_PA3) //  TWI Two-wire Serial Data
+#define AT91C_PA3_NPCS3    ((unsigned int) AT91C_PIO_PA3) //  SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ1     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 1
+#define AT91C_PA30_NPCS2    ((unsigned int) AT91C_PIO_PA30) //  SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA31       ((unsigned int) 1 << 31) // Pin Controlled by PA31
+#define AT91C_PA31_NPCS1    ((unsigned int) AT91C_PIO_PA31) //  SPI Peripheral Chip Select 1
+#define AT91C_PA31_PCK2     ((unsigned int) AT91C_PIO_PA31) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_TWCK     ((unsigned int) AT91C_PIO_PA4) //  TWI Two-wire Serial Clock
+#define AT91C_PA4_TCLK0    ((unsigned int) AT91C_PIO_PA4) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD0     ((unsigned int) AT91C_PIO_PA5) //  USART 0 Receive Data
+#define AT91C_PA5_NPCS3    ((unsigned int) AT91C_PIO_PA5) //  SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD0     ((unsigned int) AT91C_PIO_PA6) //  USART 0 Transmit Data
+#define AT91C_PA6_PCK0     ((unsigned int) AT91C_PIO_PA6) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_RTS0     ((unsigned int) AT91C_PIO_PA7) //  USART 0 Ready To Send
+#define AT91C_PA7_PWM3     ((unsigned int) AT91C_PIO_PA7) //  PWM Channel 3
+#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_CTS0     ((unsigned int) AT91C_PIO_PA8) //  USART 0 Clear To Send
+#define AT91C_PA8_ADTRG    ((unsigned int) AT91C_PIO_PA8) //  ADC External Trigger
+#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_DRXD     ((unsigned int) AT91C_PIO_PA9) //  DBGU Debug Receive Data
+#define AT91C_PA9_NPCS1    ((unsigned int) AT91C_PIO_PA9) //  SPI Peripheral Chip Select 1
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
+#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller
+#define AT91C_ID_3_Reserved ((unsigned int)  3) // Reserved
+#define AT91C_ID_ADC    ((unsigned int)  4) // Analog-to-Digital Converter
+#define AT91C_ID_SPI    ((unsigned int)  5) // Serial Peripheral Interface
+#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
+#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
+#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
+#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
+#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved
+#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved
+#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved
+#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved
+#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_BASE_SYSC      ((AT91PS_SYSC) 	0xFFFFF000) // (SYSC) Base Address
+#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI   ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI) Base Address
+#define AT91C_BASE_SPI       ((AT91PS_SPI) 	0xFFFE0000) // (SPI) Base Address
+#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte)
+#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00010000) // Internal ROM size in byte (64 Kbyte)
+
+#endif
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
new file mode 100644
index 0000000..7d2657a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
@@ -0,0 +1,1812 @@
+// ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+// ----------------------------------------------------------------------------
+//  The software is delivered "AS IS" without warranty or condition of any
+//  kind, either express, implied or statutory. This includes without
+//  limitation any warranty or condition with respect to merchantability or
+//  fitness for any particular purpose, or against the infringements of
+//  intellectual property rights of others.
+// ----------------------------------------------------------------------------
+// File Name           : AT91SAM7S64.h
+// Object              : AT91SAM7S64 definitions
+// Generated           : AT91 SW Application Group  07/16/2004 (07:43:09)
+// 
+// CVS Reference       : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004//
+// CVS Reference       : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004//
+// CVS Reference       : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004//
+// CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug  2 14:45:38 2002//
+// CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
+// CVS Reference       : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
+// CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
+// CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
+// CVS Reference       : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004//
+// CVS Reference       : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//
+// CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov  8 13:26:40 2002//
+// CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+// CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb  7 10:30:08 2003//
+// CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//
+// CVS Reference       : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//
+// CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+// ----------------------------------------------------------------------------
+
+// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+// *** Register offset in AT91S_SYSC structure ***
+#define SYSC_AIC_SMR    ( 0) // Source Mode Register
+#define SYSC_AIC_SVR    (128) // Source Vector Register
+#define SYSC_AIC_IVR    (256) // IRQ Vector Register
+#define SYSC_AIC_FVR    (260) // FIQ Vector Register
+#define SYSC_AIC_ISR    (264) // Interrupt Status Register
+#define SYSC_AIC_IPR    (268) // Interrupt Pending Register
+#define SYSC_AIC_IMR    (272) // Interrupt Mask Register
+#define SYSC_AIC_CISR   (276) // Core Interrupt Status Register
+#define SYSC_AIC_IECR   (288) // Interrupt Enable Command Register
+#define SYSC_AIC_IDCR   (292) // Interrupt Disable Command Register
+#define SYSC_AIC_ICCR   (296) // Interrupt Clear Command Register
+#define SYSC_AIC_ISCR   (300) // Interrupt Set Command Register
+#define SYSC_AIC_EOICR  (304) // End of Interrupt Command Register
+#define SYSC_AIC_SPU    (308) // Spurious Vector Register
+#define SYSC_AIC_DCR    (312) // Debug Control Register (Protect)
+#define SYSC_AIC_FFER   (320) // Fast Forcing Enable Register
+#define SYSC_AIC_FFDR   (324) // Fast Forcing Disable Register
+#define SYSC_AIC_FFSR   (328) // Fast Forcing Status Register
+#define SYSC_DBGU_CR    (512) // Control Register
+#define SYSC_DBGU_MR    (516) // Mode Register
+#define SYSC_DBGU_IER   (520) // Interrupt Enable Register
+#define SYSC_DBGU_IDR   (524) // Interrupt Disable Register
+#define SYSC_DBGU_IMR   (528) // Interrupt Mask Register
+#define SYSC_DBGU_CSR   (532) // Channel Status Register
+#define SYSC_DBGU_RHR   (536) // Receiver Holding Register
+#define SYSC_DBGU_THR   (540) // Transmitter Holding Register
+#define SYSC_DBGU_BRGR  (544) // Baud Rate Generator Register
+#define SYSC_DBGU_C1R   (576) // Chip ID1 Register
+#define SYSC_DBGU_C2R   (580) // Chip ID2 Register
+#define SYSC_DBGU_FNTR  (584) // Force NTRST Register
+#define SYSC_DBGU_RPR   (768) // Receive Pointer Register
+#define SYSC_DBGU_RCR   (772) // Receive Counter Register
+#define SYSC_DBGU_TPR   (776) // Transmit Pointer Register
+#define SYSC_DBGU_TCR   (780) // Transmit Counter Register
+#define SYSC_DBGU_RNPR  (784) // Receive Next Pointer Register
+#define SYSC_DBGU_RNCR  (788) // Receive Next Counter Register
+#define SYSC_DBGU_TNPR  (792) // Transmit Next Pointer Register
+#define SYSC_DBGU_TNCR  (796) // Transmit Next Counter Register
+#define SYSC_DBGU_PTCR  (800) // PDC Transfer Control Register
+#define SYSC_DBGU_PTSR  (804) // PDC Transfer Status Register
+#define SYSC_PIOA_PER   (1024) // PIO Enable Register
+#define SYSC_PIOA_PDR   (1028) // PIO Disable Register
+#define SYSC_PIOA_PSR   (1032) // PIO Status Register
+#define SYSC_PIOA_OER   (1040) // Output Enable Register
+#define SYSC_PIOA_ODR   (1044) // Output Disable Registerr
+#define SYSC_PIOA_OSR   (1048) // Output Status Register
+#define SYSC_PIOA_IFER  (1056) // Input Filter Enable Register
+#define SYSC_PIOA_IFDR  (1060) // Input Filter Disable Register
+#define SYSC_PIOA_IFSR  (1064) // Input Filter Status Register
+#define SYSC_PIOA_SODR  (1072) // Set Output Data Register
+#define SYSC_PIOA_CODR  (1076) // Clear Output Data Register
+#define SYSC_PIOA_ODSR  (1080) // Output Data Status Register
+#define SYSC_PIOA_PDSR  (1084) // Pin Data Status Register
+#define SYSC_PIOA_IER   (1088) // Interrupt Enable Register
+#define SYSC_PIOA_IDR   (1092) // Interrupt Disable Register
+#define SYSC_PIOA_IMR   (1096) // Interrupt Mask Register
+#define SYSC_PIOA_ISR   (1100) // Interrupt Status Register
+#define SYSC_PIOA_MDER  (1104) // Multi-driver Enable Register
+#define SYSC_PIOA_MDDR  (1108) // Multi-driver Disable Register
+#define SYSC_PIOA_MDSR  (1112) // Multi-driver Status Register
+#define SYSC_PIOA_PPUDR (1120) // Pull-up Disable Register
+#define SYSC_PIOA_PPUER (1124) // Pull-up Enable Register
+#define SYSC_PIOA_PPUSR (1128) // Pad Pull-up Status Register
+#define SYSC_PIOA_ASR   (1136) // Select A Register
+#define SYSC_PIOA_BSR   (1140) // Select B Register
+#define SYSC_PIOA_ABSR  (1144) // AB Select Status Register
+#define SYSC_PIOA_OWER  (1184) // Output Write Enable Register
+#define SYSC_PIOA_OWDR  (1188) // Output Write Disable Register
+#define SYSC_PIOA_OWSR  (1192) // Output Write Status Register
+#define SYSC_PMC_SCER   (3072) // System Clock Enable Register
+#define SYSC_PMC_SCDR   (3076) // System Clock Disable Register
+#define SYSC_PMC_SCSR   (3080) // System Clock Status Register
+#define SYSC_PMC_PCER   (3088) // Peripheral Clock Enable Register
+#define SYSC_PMC_PCDR   (3092) // Peripheral Clock Disable Register
+#define SYSC_PMC_PCSR   (3096) // Peripheral Clock Status Register
+#define SYSC_PMC_MOR    (3104) // Main Oscillator Register
+#define SYSC_PMC_MCFR   (3108) // Main Clock  Frequency Register
+#define SYSC_PMC_PLLR   (3116) // PLL Register
+#define SYSC_PMC_MCKR   (3120) // Master Clock Register
+#define SYSC_PMC_PCKR   (3136) // Programmable Clock Register
+#define SYSC_PMC_IER    (3168) // Interrupt Enable Register
+#define SYSC_PMC_IDR    (3172) // Interrupt Disable Register
+#define SYSC_PMC_SR     (3176) // Status Register
+#define SYSC_PMC_IMR    (3180) // Interrupt Mask Register
+#define SYSC_RSTC_RCR   (3328) // Reset Control Register
+#define SYSC_RSTC_RSR   (3332) // Reset Status Register
+#define SYSC_RSTC_RMR   (3336) // Reset Mode Register
+#define SYSC_RTTC_RTMR  (3360) // Real-time Mode Register
+#define SYSC_RTTC_RTAR  (3364) // Real-time Alarm Register
+#define SYSC_RTTC_RTVR  (3368) // Real-time Value Register
+#define SYSC_RTTC_RTSR  (3372) // Real-time Status Register
+#define SYSC_PITC_PIMR  (3376) // Period Interval Mode Register
+#define SYSC_PITC_PISR  (3380) // Period Interval Status Register
+#define SYSC_PITC_PIVR  (3384) // Period Interval Value Register
+#define SYSC_PITC_PIIR  (3388) // Period Interval Image Register
+#define SYSC_WDTC_WDCR  (3392) // Watchdog Control Register
+#define SYSC_WDTC_WDMR  (3396) // Watchdog Mode Register
+#define SYSC_WDTC_WDSR  (3400) // Watchdog Status Register
+#define SYSC_SYSC_VRPM  (3424) // Voltage Regulator Power Mode Register
+// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- 
+#define AT91C_SYSC_PSTDBY         (0x1 <<  0) // (SYSC) Voltage Regulator Power Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+// *** Register offset in AT91S_AIC structure ***
+#define AIC_SMR         ( 0) // Source Mode Register
+#define AIC_SVR         (128) // Source Vector Register
+#define AIC_IVR         (256) // IRQ Vector Register
+#define AIC_FVR         (260) // FIQ Vector Register
+#define AIC_ISR         (264) // Interrupt Status Register
+#define AIC_IPR         (268) // Interrupt Pending Register
+#define AIC_IMR         (272) // Interrupt Mask Register
+#define AIC_CISR        (276) // Core Interrupt Status Register
+#define AIC_IECR        (288) // Interrupt Enable Command Register
+#define AIC_IDCR        (292) // Interrupt Disable Command Register
+#define AIC_ICCR        (296) // Interrupt Clear Command Register
+#define AIC_ISCR        (300) // Interrupt Set Command Register
+#define AIC_EOICR       (304) // End of Interrupt Command Register
+#define AIC_SPU         (308) // Spurious Vector Register
+#define AIC_DCR         (312) // Debug Control Register (Protect)
+#define AIC_FFER        (320) // Fast Forcing Enable Register
+#define AIC_FFDR        (324) // Fast Forcing Disable Register
+#define AIC_FFSR        (328) // Fast Forcing Status Register
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT        (0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+// *** Register offset in AT91S_DBGU structure ***
+#define DBGU_CR         ( 0) // Control Register
+#define DBGU_MR         ( 4) // Mode Register
+#define DBGU_IER        ( 8) // Interrupt Enable Register
+#define DBGU_IDR        (12) // Interrupt Disable Register
+#define DBGU_IMR        (16) // Interrupt Mask Register
+#define DBGU_CSR        (20) // Channel Status Register
+#define DBGU_RHR        (24) // Receiver Holding Register
+#define DBGU_THR        (28) // Transmitter Holding Register
+#define DBGU_BRGR       (32) // Baud Rate Generator Register
+#define DBGU_C1R        (64) // Chip ID1 Register
+#define DBGU_C2R        (68) // Chip ID2 Register
+#define DBGU_FNTR       (72) // Force NTRST Register
+#define DBGU_RPR        (256) // Receive Pointer Register
+#define DBGU_RCR        (260) // Receive Counter Register
+#define DBGU_TPR        (264) // Transmit Pointer Register
+#define DBGU_TCR        (268) // Transmit Counter Register
+#define DBGU_RNPR       (272) // Receive Next Pointer Register
+#define DBGU_RNCR       (276) // Receive Next Counter Register
+#define DBGU_TNPR       (280) // Transmit Next Pointer Register
+#define DBGU_TNCR       (284) // Transmit Next Counter Register
+#define DBGU_PTCR       (288) // PDC Transfer Control Register
+#define DBGU_PTSR       (292) // PDC Transfer Status Register
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX            (0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX            (0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN             (0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS            (0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN             (0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS            (0x1 <<  7) // (DBGU) Transmitter Disable
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR              (0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE           (0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY            (0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY            (0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX            (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX            (0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE             (0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME            (0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE             (0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY          (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE           (0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF           (0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX          (0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX          (0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST      (0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral Data Controller
+// *****************************************************************************
+// *** Register offset in AT91S_PDC structure ***
+#define PDC_RPR         ( 0) // Receive Pointer Register
+#define PDC_RCR         ( 4) // Receive Counter Register
+#define PDC_TPR         ( 8) // Transmit Pointer Register
+#define PDC_TCR         (12) // Transmit Counter Register
+#define PDC_RNPR        (16) // Receive Next Pointer Register
+#define PDC_RNCR        (20) // Receive Next Counter Register
+#define PDC_TNPR        (24) // Transmit Next Pointer Register
+#define PDC_TNCR        (28) // Transmit Next Counter Register
+#define PDC_PTCR        (32) // PDC Transfer Control Register
+#define PDC_PTSR        (36) // PDC Transfer Status Register
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN           (0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS          (0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN           (0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS          (0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PIO structure ***
+#define PIO_PER         ( 0) // PIO Enable Register
+#define PIO_PDR         ( 4) // PIO Disable Register
+#define PIO_PSR         ( 8) // PIO Status Register
+#define PIO_OER         (16) // Output Enable Register
+#define PIO_ODR         (20) // Output Disable Registerr
+#define PIO_OSR         (24) // Output Status Register
+#define PIO_IFER        (32) // Input Filter Enable Register
+#define PIO_IFDR        (36) // Input Filter Disable Register
+#define PIO_IFSR        (40) // Input Filter Status Register
+#define PIO_SODR        (48) // Set Output Data Register
+#define PIO_CODR        (52) // Clear Output Data Register
+#define PIO_ODSR        (56) // Output Data Status Register
+#define PIO_PDSR        (60) // Pin Data Status Register
+#define PIO_IER         (64) // Interrupt Enable Register
+#define PIO_IDR         (68) // Interrupt Disable Register
+#define PIO_IMR         (72) // Interrupt Mask Register
+#define PIO_ISR         (76) // Interrupt Status Register
+#define PIO_MDER        (80) // Multi-driver Enable Register
+#define PIO_MDDR        (84) // Multi-driver Disable Register
+#define PIO_MDSR        (88) // Multi-driver Status Register
+#define PIO_PPUDR       (96) // Pull-up Disable Register
+#define PIO_PPUER       (100) // Pull-up Enable Register
+#define PIO_PPUSR       (104) // Pad Pull-up Status Register
+#define PIO_ASR         (112) // Select A Register
+#define PIO_BSR         (116) // Select B Register
+#define PIO_ABSR        (120) // AB Select Status Register
+#define PIO_OWER        (160) // Output Write Enable Register
+#define PIO_OWDR        (164) // Output Write Disable Register
+#define PIO_OWSR        (168) // Output Write Status Register
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+// *** Register offset in AT91S_CKGR structure ***
+#define CKGR_MOR        ( 0) // Main Oscillator Register
+#define CKGR_MCFR       ( 4) // Main Clock  Frequency Register
+#define CKGR_PLLR       (12) // PLL Register
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN         (0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS      (0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT        (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF          (0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY        (0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV            (0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT       (0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT            (0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL            (0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV         (0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PMC structure ***
+#define PMC_SCER        ( 0) // System Clock Enable Register
+#define PMC_SCDR        ( 4) // System Clock Disable Register
+#define PMC_SCSR        ( 8) // System Clock Status Register
+#define PMC_PCER        (16) // Peripheral Clock Enable Register
+#define PMC_PCDR        (20) // Peripheral Clock Disable Register
+#define PMC_PCSR        (24) // Peripheral Clock Status Register
+#define PMC_MOR         (32) // Main Oscillator Register
+#define PMC_MCFR        (36) // Main Clock  Frequency Register
+#define PMC_PLLR        (44) // PLL Register
+#define PMC_MCKR        (48) // Master Clock Register
+#define PMC_PCKR        (64) // Programmable Clock Register
+#define PMC_IER         (96) // Interrupt Enable Register
+#define PMC_IDR         (100) // Interrupt Disable Register
+#define PMC_SR          (104) // Status Register
+#define PMC_IMR         (108) // Interrupt Mask Register
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK             (0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP             (0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0            (0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1            (0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2            (0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3            (0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS             (0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES            (0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS           (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK            (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY          (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY         (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY         (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY         (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY         (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RSTC structure ***
+#define RSTC_RCR        ( 0) // Reset Control Register
+#define RSTC_RSR        ( 4) // Reset Status Register
+#define RSTC_RMR        ( 8) // Reset Mode Register
+// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_SYSC_PROCRST        (0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_SYSC_ICERST         (0x1 <<  1) // (RSTC) ICE Interface Reset
+#define AT91C_SYSC_PERRST         (0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_SYSC_EXTRST         (0x1 <<  3) // (RSTC) External Reset
+#define AT91C_SYSC_KEY            (0xFF << 24) // (RSTC) Password
+// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_SYSC_URSTS          (0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_SYSC_BODSTS         (0x1 <<  1) // (RSTC) Brown-out Detection Status
+#define AT91C_SYSC_RSTTYP         (0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_SYSC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_SYSC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_SYSC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_SYSC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_SYSC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brown-out Reset.
+#define AT91C_SYSC_NRSTL          (0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_SYSC_SRCMP          (0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_SYSC_URSTEN         (0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_SYSC_URSTIEN        (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_SYSC_ERSTL          (0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_SYSC_BODIEN         (0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RTTC structure ***
+#define RTTC_RTMR       ( 0) // Real-time Mode Register
+#define RTTC_RTAR       ( 4) // Real-time Alarm Register
+#define RTTC_RTVR       ( 8) // Real-time Value Register
+#define RTTC_RTSR       (12) // Real-time Status Register
+// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_SYSC_RTPRES         (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_SYSC_ALMIEN         (0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_SYSC_RTTINCIEN      (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_SYSC_RTTRST         (0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_SYSC_ALMV           (0x0 <<  0) // (RTTC) Alarm Value
+// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_SYSC_CRTV           (0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_SYSC_ALMS           (0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_SYSC_RTTINC         (0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PITC structure ***
+#define PITC_PIMR       ( 0) // Period Interval Mode Register
+#define PITC_PISR       ( 4) // Period Interval Status Register
+#define PITC_PIVR       ( 8) // Period Interval Value Register
+#define PITC_PIIR       (12) // Period Interval Image Register
+// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_SYSC_PIV            (0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_SYSC_PITEN          (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_SYSC_PITIEN         (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_SYSC_PITS           (0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_SYSC_CPIV           (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_SYSC_PICNT          (0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_WDTC structure ***
+#define WDTC_WDCR       ( 0) // Watchdog Control Register
+#define WDTC_WDMR       ( 4) // Watchdog Mode Register
+#define WDTC_WDSR       ( 8) // Watchdog Status Register
+// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_SYSC_WDRSTT         (0x1 <<  0) // (WDTC) Watchdog Restart
+// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_SYSC_WDV            (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_SYSC_WDFIEN         (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_SYSC_WDRSTEN        (0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_SYSC_WDRPROC        (0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_SYSC_WDDIS          (0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_SYSC_WDD            (0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_SYSC_WDDBGHLT       (0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_SYSC_WDIDLEHLT      (0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_SYSC_WDUNF          (0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_SYSC_WDERR          (0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_MC structure ***
+#define MC_RCR          ( 0) // MC Remap Control Register
+#define MC_ASR          ( 4) // MC Abort Status Register
+#define MC_AASR         ( 8) // MC Abort Address Status Register
+#define MC_FMR          (96) // MC Flash Mode Register
+#define MC_FCR          (100) // MC Flash Command Register
+#define MC_FSR          (104) // MC Flash Status Register
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB              (0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD           (0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD           (0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ            (0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP           (0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0             (0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1             (0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0           (0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1           (0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY             (0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE            (0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE            (0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP             (0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS              (0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN             (0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD             (0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN            (0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY              (0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY         (0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0           (0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1           (0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2           (0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3           (0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4           (0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5           (0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6           (0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7           (0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0           (0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1           (0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2           (0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3           (0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4           (0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5           (0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6           (0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7           (0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8           (0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9           (0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10          (0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11          (0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12          (0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13          (0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14          (0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15          (0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SPI structure ***
+#define SPI_CR          ( 0) // Control Register
+#define SPI_MR          ( 4) // Mode Register
+#define SPI_RDR         ( 8) // Receive Data Register
+#define SPI_TDR         (12) // Transmit Data Register
+#define SPI_SR          (16) // Status Register
+#define SPI_IER         (20) // Interrupt Enable Register
+#define SPI_IDR         (24) // Interrupt Disable Register
+#define SPI_IMR         (28) // Interrupt Mask Register
+#define SPI_CSR         (48) // Chip Select Register
+#define SPI_RPR         (256) // Receive Pointer Register
+#define SPI_RCR         (260) // Receive Counter Register
+#define SPI_TPR         (264) // Transmit Pointer Register
+#define SPI_TCR         (268) // Transmit Counter Register
+#define SPI_RNPR        (272) // Receive Next Pointer Register
+#define SPI_RNCR        (276) // Receive Next Counter Register
+#define SPI_TNPR        (280) // Transmit Next Pointer Register
+#define SPI_TNCR        (284) // Transmit Next Counter Register
+#define SPI_PTCR        (288) // PDC Transfer Control Register
+#define SPI_PTSR        (292) // PDC Transfer Status Register
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN           (0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS          (0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST           (0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER        (0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR            (0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS              (0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC          (0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV            (0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS         (0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB             (0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS             (0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS          (0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD              (0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD              (0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF            (0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE            (0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF            (0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES           (0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX           (0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX           (0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF          (0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE          (0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR            (0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY         (0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS          (0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL            (0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA           (0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT           (0x1 <<  2) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS            (0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR            (0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS           (0xFF << 16) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBCT          (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+// *** Register offset in AT91S_ADC structure ***
+#define ADC_CR          ( 0) // ADC Control Register
+#define ADC_MR          ( 4) // ADC Mode Register
+#define ADC_CHER        (16) // ADC Channel Enable Register
+#define ADC_CHDR        (20) // ADC Channel Disable Register
+#define ADC_CHSR        (24) // ADC Channel Status Register
+#define ADC_SR          (28) // ADC Status Register
+#define ADC_LCDR        (32) // ADC Last Converted Data Register
+#define ADC_IER         (36) // ADC Interrupt Enable Register
+#define ADC_IDR         (40) // ADC Interrupt Disable Register
+#define ADC_IMR         (44) // ADC Interrupt Mask Register
+#define ADC_CDR0        (48) // ADC Channel Data Register 0
+#define ADC_CDR1        (52) // ADC Channel Data Register 1
+#define ADC_CDR2        (56) // ADC Channel Data Register 2
+#define ADC_CDR3        (60) // ADC Channel Data Register 3
+#define ADC_CDR4        (64) // ADC Channel Data Register 4
+#define ADC_CDR5        (68) // ADC Channel Data Register 5
+#define ADC_CDR6        (72) // ADC Channel Data Register 6
+#define ADC_CDR7        (76) // ADC Channel Data Register 7
+#define ADC_RPR         (256) // Receive Pointer Register
+#define ADC_RCR         (260) // Receive Counter Register
+#define ADC_TPR         (264) // Transmit Pointer Register
+#define ADC_TCR         (268) // Transmit Counter Register
+#define ADC_RNPR        (272) // Receive Next Pointer Register
+#define ADC_RNCR        (276) // Receive Next Counter Register
+#define ADC_TNPR        (280) // Transmit Next Pointer Register
+#define ADC_TNCR        (284) // Transmit Next Counter Register
+#define ADC_PTCR        (288) // PDC Transfer Control Register
+#define ADC_PTSR        (292) // PDC Transfer Status Register
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST           (0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START           (0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN           (0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL          (0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES          (0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP           (0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL         (0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP         (0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM           (0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0             (0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1             (0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2             (0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3             (0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4             (0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5             (0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6             (0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7             (0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0            (0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1            (0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2            (0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3            (0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4            (0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5            (0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6            (0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7            (0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0           (0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1           (0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2           (0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3           (0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4           (0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5           (0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6           (0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7           (0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY            (0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE           (0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX           (0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF          (0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA           (0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA            (0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SSC structure ***
+#define SSC_CR          ( 0) // Control Register
+#define SSC_CMR         ( 4) // Clock Mode Register
+#define SSC_RCMR        (16) // Receive Clock ModeRegister
+#define SSC_RFMR        (20) // Receive Frame Mode Register
+#define SSC_TCMR        (24) // Transmit Clock Mode Register
+#define SSC_TFMR        (28) // Transmit Frame Mode Register
+#define SSC_RHR         (32) // Receive Holding Register
+#define SSC_THR         (36) // Transmit Holding Register
+#define SSC_RSHR        (48) // Receive Sync Holding Register
+#define SSC_TSHR        (52) // Transmit Sync Holding Register
+#define SSC_RC0R        (56) // Receive Compare 0 Register
+#define SSC_RC1R        (60) // Receive Compare 1 Register
+#define SSC_SR          (64) // Status Register
+#define SSC_IER         (68) // Interrupt Enable Register
+#define SSC_IDR         (72) // Interrupt Disable Register
+#define SSC_IMR         (76) // Interrupt Mask Register
+#define SSC_RPR         (256) // Receive Pointer Register
+#define SSC_RCR         (260) // Receive Counter Register
+#define SSC_TPR         (264) // Transmit Pointer Register
+#define SSC_TCR         (268) // Transmit Counter Register
+#define SSC_RNPR        (272) // Receive Next Pointer Register
+#define SSC_RNCR        (276) // Receive Next Counter Register
+#define SSC_TNPR        (280) // Transmit Next Pointer Register
+#define SSC_TNCR        (284) // Transmit Next Counter Register
+#define SSC_PTCR        (288) // PDC Transfer Control Register
+#define SSC_PTSR        (292) // PDC Transfer Status Register
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN            (0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS           (0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN            (0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS           (0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST           (0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS             (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO             (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI             (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_CKG             (0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection
+#define 	AT91C_SSC_CKG_NONE                 (0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
+#define 	AT91C_SSC_CKG_LOW                  (0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low
+#define 	AT91C_SSC_CKG_HIGH                 (0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High
+#define AT91C_SSC_START           (0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STOP            (0x1 << 12) // (SSC) Receive Stop Selection
+#define AT91C_SSC_STTOUT          (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
+#define AT91C_SSC_STTDLY          (0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD          (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN          (0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP            (0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF            (0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB           (0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN           (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS            (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE          (0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF          (0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN           (0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY           (0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY         (0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX           (0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE          (0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY           (0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN           (0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX           (0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF          (0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_CP0             (0x1 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_CP1             (0x1 <<  9) // (SSC) Compare 1
+#define AT91C_SSC_TXSYN           (0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN           (0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA           (0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA           (0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+// *** Register offset in AT91S_USART structure ***
+#define US_CR           ( 0) // Control Register
+#define US_MR           ( 4) // Mode Register
+#define US_IER          ( 8) // Interrupt Enable Register
+#define US_IDR          (12) // Interrupt Disable Register
+#define US_IMR          (16) // Interrupt Mask Register
+#define US_CSR          (20) // Channel Status Register
+#define US_RHR          (24) // Receiver Holding Register
+#define US_THR          (28) // Transmitter Holding Register
+#define US_BRGR         (32) // Baud Rate Generator Register
+#define US_RTOR         (36) // Receiver Time-out Register
+#define US_TTGR         (40) // Transmitter Time-guard Register
+#define US_FIDI         (64) // FI_DI_Ratio Register
+#define US_NER          (68) // Nb Errors Register
+#define US_XXR          (72) // XON_XOFF Register
+#define US_IF           (76) // IRDA_FILTER Register
+#define US_RPR          (256) // Receive Pointer Register
+#define US_RCR          (260) // Receive Counter Register
+#define US_TPR          (264) // Transmit Pointer Register
+#define US_TCR          (268) // Transmit Counter Register
+#define US_RNPR         (272) // Receive Next Pointer Register
+#define US_RNCR         (276) // Receive Next Counter Register
+#define US_TNPR         (280) // Transmit Next Pointer Register
+#define US_TNCR         (284) // Transmit Next Counter Register
+#define US_PTCR         (288) // PDC Transfer Control Register
+#define US_PTSR         (292) // PDC Transfer Status Register
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTSTA           (0x1 <<  8) // (USART) Reset Status Bits
+#define AT91C_US_STTBRK           (0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK           (0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO            (0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA            (0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT            (0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK          (0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO            (0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN            (0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS           (0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN            (0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS           (0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE           (0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS             (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL             (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC             (0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP           (0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF             (0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9            (0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO             (0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER             (0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK            (0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK           (0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER         (0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER           (0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK            (0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT          (0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION        (0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK             (0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC             (0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC            (0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC            (0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC            (0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI               (0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR              (0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD              (0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS              (0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TWI structure ***
+#define TWI_CR          ( 0) // Control Register
+#define TWI_MMR         ( 4) // Master Mode Register
+#define TWI_SMR         ( 8) // Slave Mode Register
+#define TWI_IADR        (12) // Internal Address Register
+#define TWI_CWGR        (16) // Clock Waveform Generator Register
+#define TWI_SR          (32) // Status Register
+#define TWI_IER         (36) // Interrupt Enable Register
+#define TWI_IDR         (40) // Interrupt Disable Register
+#define TWI_IMR         (44) // Interrupt Mask Register
+#define TWI_RHR         (48) // Receive Holding Register
+#define TWI_THR         (52) // Transmit Holding Register
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START           (0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP            (0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN            (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS           (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SVEN            (0x1 <<  4) // (TWI) TWI Slave Transfer Enabled
+#define AT91C_TWI_SVDIS           (0x1 <<  5) // (TWI) TWI Slave Transfer Disabled
+#define AT91C_TWI_SWRST           (0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ          (0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD           (0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR            (0x7F << 16) // (TWI) Device Address
+// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- 
+#define AT91C_TWI_SADR            (0x7F << 16) // (TWI) Slave Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV           (0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV           (0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV           (0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP          (0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY           (0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY           (0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_SVREAD          (0x1 <<  3) // (TWI) Slave Read
+#define AT91C_TWI_SVACC           (0x1 <<  4) // (TWI) Slave Access
+#define AT91C_TWI_GCACC           (0x1 <<  5) // (TWI) General Call Access
+#define AT91C_TWI_OVRE            (0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE            (0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK            (0x1 <<  8) // (TWI) Not Acknowledged
+#define AT91C_TWI_ARBLST          (0x1 <<  9) // (TWI) Arbitration Lost
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TC structure ***
+#define TC_CCR          ( 0) // Channel Control Register
+#define TC_CMR          ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
+#define TC_CV           (16) // Counter Value
+#define TC_RA           (20) // Register A
+#define TC_RB           (24) // Register B
+#define TC_RC           (28) // Register C
+#define TC_SR           (32) // Status Register
+#define TC_IER          (36) // Interrupt Enable Register
+#define TC_IDR          (40) // Interrupt Disable Register
+#define TC_IMR          (44) // Interrupt Mask Register
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN            (0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS           (0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG            (0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS             (0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI             (0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST            (0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_LDBDIS           (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_CPCDIS           (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_ETRGEDG          (0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG          (0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_ABETRG           (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_EEVT             (0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_NONE                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_RISING               (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_FALLING              (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_BOTH                 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ENETRG           (0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL          (0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG           (0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE             (0x1 << 15) // (TC) 
+#define AT91C_TC_LDRA             (0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPA             (0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRB             (0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC             (0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_AEEVT            (0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG           (0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB             (0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC             (0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT            (0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG           (0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS            (0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS            (0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS             (0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS             (0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS             (0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS            (0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS            (0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRCS            (0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_ETRGS            (0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA            (0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB            (0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TCB structure ***
+#define TCB_TC0         ( 0) // TC Channel 0
+#define TCB_TC1         (64) // TC Channel 1
+#define TCB_TC2         (128) // TC Channel 2
+#define TCB_BCR         (192) // TC Block Control Register
+#define TCB_BMR         (196) // TC Block Mode Register
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC            (0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S         (0x1 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S         (0x1 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S         (0x1 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA2                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC_CH structure ***
+#define PWMC_CMR        ( 0) // Channel Mode Register
+#define PWMC_CDTYR      ( 4) // Channel Duty Cycle Register
+#define PWMC_CPRDR      ( 8) // Channel Period Register
+#define PWMC_CCNTR      (12) // Channel Counter Register
+#define PWMC_CUPDR      (16) // Channel Update Register
+#define PWMC_Reserved   (20) // Reserved
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE           (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG           (0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL           (0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD            (0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY           (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD           (0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT           (0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD           (0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC structure ***
+#define PWMC_MR         ( 0) // PWMC Mode Register
+#define PWMC_ENA        ( 4) // PWMC Enable Register
+#define PWMC_DIS        ( 8) // PWMC Disable Register
+#define PWMC_SR         (12) // PWMC Status Register
+#define PWMC_IER        (16) // PWMC Interrupt Enable Register
+#define PWMC_IDR        (20) // PWMC Interrupt Disable Register
+#define PWMC_IMR        (24) // PWMC Interrupt Mask Register
+#define PWMC_ISR        (28) // PWMC Interrupt Status Register
+#define PWMC_VR         (252) // PWMC Version Register
+#define PWMC_CH         (512) // PWMC Channel 0
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA           (0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA           (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB           (0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB           (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0          (0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1          (0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2          (0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3          (0x1 <<  3) // (PWMC) Channel ID 3
+#define AT91C_PWMC_CHID4          (0x1 <<  4) // (PWMC) Channel ID 4
+#define AT91C_PWMC_CHID5          (0x1 <<  5) // (PWMC) Channel ID 5
+#define AT91C_PWMC_CHID6          (0x1 <<  6) // (PWMC) Channel ID 6
+#define AT91C_PWMC_CHID7          (0x1 <<  7) // (PWMC) Channel ID 7
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+// *** Register offset in AT91S_UDP structure ***
+#define UDP_NUM         ( 0) // Frame Number Register
+#define UDP_GLBSTATE    ( 4) // Global State Register
+#define UDP_FADDR       ( 8) // Function Address Register
+#define UDP_IER         (16) // Interrupt Enable Register
+#define UDP_IDR         (20) // Interrupt Disable Register
+#define UDP_IMR         (24) // Interrupt Mask Register
+#define UDP_ISR         (28) // Interrupt Status Register
+#define UDP_ICR         (32) // Interrupt Clear Register
+#define UDP_RSTEP       (40) // Reset Endpoint Register
+#define UDP_CSR         (48) // Endpoint Control and Status Register
+#define UDP_FDR         (80) // Endpoint FIFO Data Register
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM         (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR         (0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK          (0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN          (0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG           (0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_RMWUPE          (0x1 <<  2) // (UDP) Remote Wake Up Enable
+#define AT91C_UDP_RSMINPR         (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD            (0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN             (0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0          (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1          (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2          (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3          (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4          (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5          (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_EPINT6          (0x1 <<  6) // (UDP) Endpoint 6 Interrupt
+#define AT91C_UDP_EPINT7          (0x1 <<  7) // (UDP) Endpoint 7 Interrupt
+#define AT91C_UDP_RXSUSP          (0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM           (0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM          (0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT          (0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP          (0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES       (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0             (0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1             (0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2             (0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3             (0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4             (0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5             (0x1 <<  5) // (UDP) Reset Endpoint 5
+#define AT91C_UDP_EP6             (0x1 <<  6) // (UDP) Reset Endpoint 6
+#define AT91C_UDP_EP7             (0x1 <<  7) // (UDP) Reset Endpoint 7
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP          (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0     (0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP         (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR        (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY        (0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL      (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1     (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR             (0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE          (0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE           (0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS           (0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT       (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
+// *****************************************************************************
+// ========== Register definition for SYSC peripheral ========== 
+#define AT91C_SYSC_SYSC_VRPM      (0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_ICCR            (0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_IECR            (0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_SMR             (0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_ISCR            (0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_EOICR           (0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_DCR             (0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_FFER            (0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_SVR             (0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_SPU             (0xFFFFF134) // (AIC) Spurious Vector Register
+#define AT91C_AIC_FFDR            (0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_FVR             (0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_FFSR            (0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_IMR             (0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_ISR             (0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IVR             (0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_IDCR            (0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_CISR            (0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IPR             (0xFFFFF10C) // (AIC) Interrupt Pending Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_C2R            (0xFFFFF244) // (DBGU) Chip ID2 Register
+#define AT91C_DBGU_THR            (0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_CSR            (0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_IDR            (0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_MR             (0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_FNTR           (0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_C1R            (0xFFFFF240) // (DBGU) Chip ID1 Register
+#define AT91C_DBGU_BRGR           (0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_RHR            (0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IMR            (0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_IER            (0xFFFFF208) // (DBGU) Interrupt Enable Register
+#define AT91C_DBGU_CR             (0xFFFFF200) // (DBGU) Control Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TNCR           (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+#define AT91C_DBGU_RNCR           (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR           (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR           (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_RCR            (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_TCR            (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RPR            (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_TPR            (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RNPR           (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR           (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_IMR            (0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_IER            (0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_OWDR           (0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_ISR            (0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_PPUDR          (0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_MDSR           (0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_MDER           (0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PER            (0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_PSR            (0xFFFFF408) // (PIOA) PIO Status Register
+#define AT91C_PIOA_OER            (0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_BSR            (0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_PPUER          (0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_MDDR           (0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_PDR            (0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_ODR            (0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_IFDR           (0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_ABSR           (0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_ASR            (0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_PPUSR          (0xFFFFF468) // (PIOA) Pad Pull-up Status Register
+#define AT91C_PIOA_ODSR           (0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_SODR           (0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_IFSR           (0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_IFER           (0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_OSR            (0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_IDR            (0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_PDSR           (0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_CODR           (0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_OWSR           (0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_OWER           (0xFFFFF4A0) // (PIOA) Output Write Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_PLLR           (0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR           (0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+#define AT91C_CKGR_MOR            (0xFFFFFC20) // (CKGR) Main Oscillator Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_SCSR            (0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_SCER            (0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR             (0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IDR             (0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_PCDR            (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCDR            (0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_SR              (0xFFFFFC68) // (PMC) Status Register
+#define AT91C_PMC_IER             (0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_MCKR            (0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_MOR             (0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PCER            (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCSR            (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_PLLR            (0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_MCFR            (0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_PCKR            (0xFFFFFC40) // (PMC) Programmable Clock Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RSR            (0xFFFFFD04) // (RSTC) Reset Status Register
+#define AT91C_RSTC_RMR            (0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RCR            (0xFFFFFD00) // (RSTC) Reset Control Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR           (0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTAR           (0xFFFFFD24) // (RTTC) Real-time Alarm Register
+#define AT91C_RTTC_RTVR           (0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTMR           (0xFFFFFD20) // (RTTC) Real-time Mode Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIIR           (0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PISR           (0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIVR           (0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PIMR           (0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDMR           (0xFFFFFD44) // (WDTC) Watchdog Mode Register
+#define AT91C_WDTC_WDSR           (0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDCR           (0xFFFFFD40) // (WDTC) Watchdog Control Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_FCR              (0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_ASR              (0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_FSR              (0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR              (0xFFFFFF60) // (MC) MC Flash Mode Register
+#define AT91C_MC_AASR             (0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_RCR              (0xFFFFFF00) // (MC) MC Remap Control Register
+// ========== Register definition for PDC_SPI peripheral ========== 
+#define AT91C_SPI_PTCR            (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
+#define AT91C_SPI_TNPR            (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
+#define AT91C_SPI_RNPR            (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
+#define AT91C_SPI_TPR             (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
+#define AT91C_SPI_RPR             (0xFFFE0100) // (PDC_SPI) Receive Pointer Register
+#define AT91C_SPI_PTSR            (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
+#define AT91C_SPI_TNCR            (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
+#define AT91C_SPI_RNCR            (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
+#define AT91C_SPI_TCR             (0xFFFE010C) // (PDC_SPI) Transmit Counter Register
+#define AT91C_SPI_RCR             (0xFFFE0104) // (PDC_SPI) Receive Counter Register
+// ========== Register definition for SPI peripheral ========== 
+#define AT91C_SPI_CSR             (0xFFFE0030) // (SPI) Chip Select Register
+#define AT91C_SPI_IDR             (0xFFFE0018) // (SPI) Interrupt Disable Register
+#define AT91C_SPI_SR              (0xFFFE0010) // (SPI) Status Register
+#define AT91C_SPI_RDR             (0xFFFE0008) // (SPI) Receive Data Register
+#define AT91C_SPI_CR              (0xFFFE0000) // (SPI) Control Register
+#define AT91C_SPI_IMR             (0xFFFE001C) // (SPI) Interrupt Mask Register
+#define AT91C_SPI_IER             (0xFFFE0014) // (SPI) Interrupt Enable Register
+#define AT91C_SPI_TDR             (0xFFFE000C) // (SPI) Transmit Data Register
+#define AT91C_SPI_MR              (0xFFFE0004) // (SPI) Mode Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTCR            (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR            (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_RNPR            (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_TPR             (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RPR             (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_PTSR            (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_TNCR            (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNCR            (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_TCR             (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_RCR             (0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_IMR             (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+#define AT91C_ADC_CDR4            (0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR2            (0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR0            (0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR7            (0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR1            (0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_CDR3            (0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR5            (0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_MR              (0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_CDR6            (0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_CR              (0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CHER            (0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR            (0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_IER             (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_SR              (0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CHDR            (0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_IDR             (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_LCDR            (0xFFFD8020) // (ADC) ADC Last Converted Data Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_PTCR            (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TNPR            (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_RNPR            (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TPR             (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_RPR             (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_PTSR            (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+#define AT91C_SSC_TNCR            (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RNCR            (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TCR             (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR             (0xFFFD4104) // (PDC_SSC) Receive Counter Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RFMR            (0xFFFD4014) // (SSC) Receive Frame Mode Register
+#define AT91C_SSC_CMR             (0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_IDR             (0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_SR              (0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_RC0R            (0xFFFD4038) // (SSC) Receive Compare 0 Register
+#define AT91C_SSC_RSHR            (0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_RHR             (0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_TCMR            (0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_RCMR            (0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_CR              (0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR             (0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_IER             (0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_RC1R            (0xFFFD403C) // (SSC) Receive Compare 1 Register
+#define AT91C_SSC_TSHR            (0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_THR             (0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_TFMR            (0xFFFD401C) // (SSC) Transmit Frame Mode Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_PTSR            (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNCR            (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_RNCR            (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_TCR             (0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_RCR             (0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_PTCR            (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TNPR            (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RNPR            (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_TPR             (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+#define AT91C_US1_RPR             (0xFFFC4100) // (PDC_US1) Receive Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_XXR             (0xFFFC4048) // (US1) XON_XOFF Register
+#define AT91C_US1_RHR             (0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_IMR             (0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_IER             (0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_CR              (0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_RTOR            (0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_THR             (0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_CSR             (0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR             (0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_FIDI            (0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_BRGR            (0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_TTGR            (0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_IF              (0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER             (0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_MR              (0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_PTCR            (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_TNPR            (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR            (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TPR             (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RPR             (0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_PTSR            (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR            (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_RNCR            (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+#define AT91C_US0_TCR             (0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_RCR             (0xFFFC0104) // (PDC_US0) Receive Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_TTGR            (0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_BRGR            (0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_RHR             (0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IMR             (0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_NER             (0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_RTOR            (0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_XXR             (0xFFFC0048) // (US0) XON_XOFF Register
+#define AT91C_US0_FIDI            (0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_CR              (0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IER             (0xFFFC0008) // (US0) Interrupt Enable Register
+#define AT91C_US0_IF              (0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_MR              (0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_IDR             (0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_CSR             (0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_THR             (0xFFFC001C) // (US0) Transmitter Holding Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_RHR             (0xFFFB8030) // (TWI) Receive Holding Register
+#define AT91C_TWI_IDR             (0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_SR              (0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_CWGR            (0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_SMR             (0xFFFB8008) // (TWI) Slave Mode Register
+#define AT91C_TWI_CR              (0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_THR             (0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IMR             (0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_IER             (0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_IADR            (0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR             (0xFFFB8004) // (TWI) Master Mode Register
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_IMR             (0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_IER             (0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_RC              (0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_RA              (0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_CMR             (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_IDR             (0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_SR              (0xFFFA00A0) // (TC2) Status Register
+#define AT91C_TC2_RB              (0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_CV              (0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_CCR             (0xFFFA0080) // (TC2) Channel Control Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_IMR             (0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_IER             (0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_RC              (0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_RA              (0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_CMR             (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_IDR             (0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR              (0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_RB              (0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CV              (0xFFFA0050) // (TC1) Counter Value
+#define AT91C_TC1_CCR             (0xFFFA0040) // (TC1) Channel Control Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_IMR             (0xFFFA002C) // (TC0) Interrupt Mask Register
+#define AT91C_TC0_IER             (0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RC              (0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RA              (0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_CMR             (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IDR             (0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_SR              (0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RB              (0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CV              (0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_CCR             (0xFFFA0000) // (TC0) Channel Control Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR             (0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR             (0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_CH3_CUPDR           (0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_CH3_CPRDR           (0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_CH3_CMR             (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+#define AT91C_CH3_Reserved        (0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_CH3_CCNTR           (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_CH3_CDTYR           (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_CH2_CUPDR           (0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_CH2_CPRDR           (0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_CH2_CMR             (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_CH2_Reserved        (0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_CH2_CCNTR           (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_CH2_CDTYR           (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_CH1_CUPDR           (0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_CH1_CPRDR           (0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_CH1_CMR             (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+#define AT91C_CH1_Reserved        (0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_CH1_CCNTR           (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_CH1_CDTYR           (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_CH0_CUPDR           (0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_CH0_CPRDR           (0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_CH0_CMR             (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_CH0_Reserved        (0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_CH0_CCNTR           (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+#define AT91C_CH0_CDTYR           (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_VR             (0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR            (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_IDR            (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_SR             (0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_ENA            (0xFFFCC004) // (PWMC) PWMC Enable Register
+#define AT91C_PWMC_IMR            (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR             (0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_DIS            (0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER            (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_ISR             (0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_IDR             (0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_GLBSTATE        (0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_FDR             (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_CSR             (0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_RSTEP           (0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_ICR             (0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_IMR             (0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_IER             (0xFFFB0010) // (UDP) Interrupt Enable Register
+#define AT91C_UDP_FADDR           (0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM             (0xFFFB0000) // (UDP) Frame Number Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_PIO_PA0             (1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_PWM0            (AT91C_PIO_PA0) //  PWM Channel 0
+#define AT91C_PA0_TIOA0           (AT91C_PIO_PA0) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA1             (1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_PWM1            (AT91C_PIO_PA1) //  PWM Channel 1
+#define AT91C_PA1_TIOB0           (AT91C_PIO_PA1) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA10            (1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_DTXD           (AT91C_PIO_PA10) //  DBGU Debug Transmit Data
+#define AT91C_PA10_NPCS2          (AT91C_PIO_PA10) //  SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA11            (1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_NPCS0          (AT91C_PIO_PA11) //  SPI Peripheral Chip Select 0
+#define AT91C_PA11_PWM0           (AT91C_PIO_PA11) //  PWM Channel 0
+#define AT91C_PIO_PA12            (1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_MISO           (AT91C_PIO_PA12) //  SPI Master In Slave
+#define AT91C_PA12_PWM1           (AT91C_PIO_PA12) //  PWM Channel 1
+#define AT91C_PIO_PA13            (1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_MOSI           (AT91C_PIO_PA13) //  SPI Master Out Slave
+#define AT91C_PA13_PWM2           (AT91C_PIO_PA13) //  PWM Channel 2
+#define AT91C_PIO_PA14            (1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_SPCK           (AT91C_PIO_PA14) //  SPI Serial Clock
+#define AT91C_PA14_PWM3           (AT91C_PIO_PA14) //  PWM Channel 3
+#define AT91C_PIO_PA15            (1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_TF             (AT91C_PIO_PA15) //  SSC Transmit Frame Sync
+#define AT91C_PA15_TIOA1          (AT91C_PIO_PA15) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA16            (1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_TK             (AT91C_PIO_PA16) //  SSC Transmit Clock
+#define AT91C_PA16_TIOB1          (AT91C_PIO_PA16) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA17            (1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_TD             (AT91C_PIO_PA17) //  SSC Transmit data
+#define AT91C_PA17_PCK1           (AT91C_PIO_PA17) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA18            (1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_RD             (AT91C_PIO_PA18) //  SSC Receive Data
+#define AT91C_PA18_PCK2           (AT91C_PIO_PA18) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA19            (1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_RK             (AT91C_PIO_PA19) //  SSC Receive Clock
+#define AT91C_PA19_FIQ            (AT91C_PIO_PA19) //  AIC Fast Interrupt Input
+#define AT91C_PIO_PA2             (1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_PWM2            (AT91C_PIO_PA2) //  PWM Channel 2
+#define AT91C_PA2_SCK0            (AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PIO_PA20            (1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_RF             (AT91C_PIO_PA20) //  SSC Receive Frame Sync
+#define AT91C_PA20_IRQ0           (AT91C_PIO_PA20) //  External Interrupt 0
+#define AT91C_PIO_PA21            (1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_RXD1           (AT91C_PIO_PA21) //  USART 1 Receive Data
+#define AT91C_PA21_PCK1           (AT91C_PIO_PA21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA22            (1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TXD1           (AT91C_PIO_PA22) //  USART 1 Transmit Data
+#define AT91C_PA22_NPCS3          (AT91C_PIO_PA22) //  SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA23            (1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_SCK1           (AT91C_PIO_PA23) //  USART 1 Serial Clock
+#define AT91C_PA23_PWM0           (AT91C_PIO_PA23) //  PWM Channel 0
+#define AT91C_PIO_PA24            (1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RTS1           (AT91C_PIO_PA24) //  USART 1 Ready To Send
+#define AT91C_PA24_PWM1           (AT91C_PIO_PA24) //  PWM Channel 1
+#define AT91C_PIO_PA25            (1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_CTS1           (AT91C_PIO_PA25) //  USART 1 Clear To Send
+#define AT91C_PA25_PWM2           (AT91C_PIO_PA25) //  PWM Channel 2
+#define AT91C_PIO_PA26            (1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_DCD1           (AT91C_PIO_PA26) //  USART 1 Data Carrier Detect
+#define AT91C_PA26_TIOA2          (AT91C_PIO_PA26) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PIO_PA27            (1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DTR1           (AT91C_PIO_PA27) //  USART 1 Data Terminal ready
+#define AT91C_PA27_TIOB2          (AT91C_PIO_PA27) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PIO_PA28            (1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DSR1           (AT91C_PIO_PA28) //  USART 1 Data Set ready
+#define AT91C_PA28_TCLK1          (AT91C_PIO_PA28) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PA29            (1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_RI1            (AT91C_PIO_PA29) //  USART 1 Ring Indicator
+#define AT91C_PA29_TCLK2          (AT91C_PIO_PA29) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA3             (1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_TWD             (AT91C_PIO_PA3) //  TWI Two-wire Serial Data
+#define AT91C_PA3_NPCS3           (AT91C_PIO_PA3) //  SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA30            (1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ1           (AT91C_PIO_PA30) //  External Interrupt 1
+#define AT91C_PA30_NPCS2          (AT91C_PIO_PA30) //  SPI Peripheral Chip Select 2
+#define AT91C_PIO_PA31            (1 << 31) // Pin Controlled by PA31
+#define AT91C_PA31_NPCS1          (AT91C_PIO_PA31) //  SPI Peripheral Chip Select 1
+#define AT91C_PA31_PCK2           (AT91C_PIO_PA31) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4             (1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_TWCK            (AT91C_PIO_PA4) //  TWI Two-wire Serial Clock
+#define AT91C_PA4_TCLK0           (AT91C_PIO_PA4) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PA5             (1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD0            (AT91C_PIO_PA5) //  USART 0 Receive Data
+#define AT91C_PA5_NPCS3           (AT91C_PIO_PA5) //  SPI Peripheral Chip Select 3
+#define AT91C_PIO_PA6             (1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD0            (AT91C_PIO_PA6) //  USART 0 Transmit Data
+#define AT91C_PA6_PCK0            (AT91C_PIO_PA6) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PA7             (1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_RTS0            (AT91C_PIO_PA7) //  USART 0 Ready To Send
+#define AT91C_PA7_PWM3            (AT91C_PIO_PA7) //  PWM Channel 3
+#define AT91C_PIO_PA8             (1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_CTS0            (AT91C_PIO_PA8) //  USART 0 Clear To Send
+#define AT91C_PA8_ADTRG           (AT91C_PIO_PA8) //  ADC External Trigger
+#define AT91C_PIO_PA9             (1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_DRXD            (AT91C_PIO_PA9) //  DBGU Debug Receive Data
+#define AT91C_PA9_NPCS1           (AT91C_PIO_PA9) //  SPI Peripheral Chip Select 1
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ID_FIQ              ( 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS              ( 1) // System Peripheral
+#define AT91C_ID_PIOA             ( 2) // Parallel IO Controller
+#define AT91C_ID_3_Reserved       ( 3) // Reserved
+#define AT91C_ID_ADC              ( 4) // Analog-to-Digital Converter
+#define AT91C_ID_SPI              ( 5) // Serial Peripheral Interface
+#define AT91C_ID_US0              ( 6) // USART 0
+#define AT91C_ID_US1              ( 7) // USART 1
+#define AT91C_ID_SSC              ( 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI              ( 9) // Two-Wire Interface
+#define AT91C_ID_PWMC             (10) // PWM Controller
+#define AT91C_ID_UDP              (11) // USB Device Port
+#define AT91C_ID_TC0              (12) // Timer Counter 0
+#define AT91C_ID_TC1              (13) // Timer Counter 1
+#define AT91C_ID_TC2              (14) // Timer Counter 2
+#define AT91C_ID_15_Reserved      (15) // Reserved
+#define AT91C_ID_16_Reserved      (16) // Reserved
+#define AT91C_ID_17_Reserved      (17) // Reserved
+#define AT91C_ID_18_Reserved      (18) // Reserved
+#define AT91C_ID_19_Reserved      (19) // Reserved
+#define AT91C_ID_20_Reserved      (20) // Reserved
+#define AT91C_ID_21_Reserved      (21) // Reserved
+#define AT91C_ID_22_Reserved      (22) // Reserved
+#define AT91C_ID_23_Reserved      (23) // Reserved
+#define AT91C_ID_24_Reserved      (24) // Reserved
+#define AT91C_ID_25_Reserved      (25) // Reserved
+#define AT91C_ID_26_Reserved      (26) // Reserved
+#define AT91C_ID_27_Reserved      (27) // Reserved
+#define AT91C_ID_28_Reserved      (28) // Reserved
+#define AT91C_ID_29_Reserved      (29) // Reserved
+#define AT91C_ID_IRQ0             (30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1             (31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_BASE_SYSC           (0xFFFFF000) // (SYSC) Base Address
+#define AT91C_BASE_AIC            (0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_DBGU           (0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PDC_DBGU       (0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_PIOA           (0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_CKGR           (0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC            (0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC           (0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC           (0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC           (0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC           (0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_MC             (0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI        (0xFFFE0100) // (PDC_SPI) Base Address
+#define AT91C_BASE_SPI            (0xFFFE0000) // (SPI) Base Address
+#define AT91C_BASE_PDC_ADC        (0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC            (0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_SSC        (0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC            (0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_PDC_US1        (0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0        (0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0            (0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_TWI            (0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_TC2            (0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TC1            (0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC0            (0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TCB            (0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_PWMC_CH3       (0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2       (0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1       (0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0       (0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC           (0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP            (0xFFFB0000) // (UDP) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
+// *****************************************************************************
+#define AT91C_ISRAM	              (0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	         (0x00004000) // Internal SRAM size in byte (16 Kbyte)
+#define AT91C_IFLASH	             (0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	        (0x00010000) // Internal ROM size in byte (64 Kbyte)
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
new file mode 100644
index 0000000..ae4f35f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
@@ -0,0 +1,2715 @@
+//  ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+//  ----------------------------------------------------------------------------
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  ----------------------------------------------------------------------------
+// File Name           : AT91SAM7X128.h
+// Object              : AT91SAM7X128 definitions
+// Generated           : AT91 SW Application Group  05/20/2005 (16:22:23)
+// 
+// CVS Reference       : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//
+// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
+// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
+// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
+// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
+// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
+// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
+// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
+// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
+// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
+// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
+// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
+// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
+// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+//  ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7X128_H
+#define AT91SAM7X128_H
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved2[45]; 	// 
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved3[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved4[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved5[54]; 	// 
+	AT91_REG	 PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved6[1]; 	// 
+	AT91_REG	 PIOA_OER; 	// Output Enable Register
+	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved7[1]; 	// 
+	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved8[1]; 	// 
+	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved9[1]; 	// 
+	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved10[1]; 	// 
+	AT91_REG	 PIOA_ASR; 	// Select A Register
+	AT91_REG	 PIOA_BSR; 	// Select B Register
+	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved11[9]; 	// 
+	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved12[85]; 	// 
+	AT91_REG	 PIOB_PER; 	// PIO Enable Register
+	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOB_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved13[1]; 	// 
+	AT91_REG	 PIOB_OER; 	// Output Enable Register
+	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOB_OSR; 	// Output Status Register
+	AT91_REG	 Reserved14[1]; 	// 
+	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved15[1]; 	// 
+	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved16[1]; 	// 
+	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved17[1]; 	// 
+	AT91_REG	 PIOB_ASR; 	// Select A Register
+	AT91_REG	 PIOB_BSR; 	// Select B Register
+	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved18[9]; 	// 
+	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved19[341]; 	// 
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved20[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved21[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved22[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved23[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved24[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved25[36]; 	// 
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+	AT91_REG	 Reserved26[5]; 	// 
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+	AT91_REG	 Reserved27[5]; 	// 
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
+#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved0[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved1[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved3[1]; 	// 
+	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved4[1]; 	// 
+	AT91_REG	 PIO_ASR; 	// Select A Register
+	AT91_REG	 PIO_BSR; 	// Select B Register
+	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved5[9]; 	// 
+	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 CKGR_PLLR; 	// PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved3[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved4[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
+
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+	AT91_REG	 MC_RCR; 	// MC Remap Control Register
+	AT91_REG	 MC_ASR; 	// MC Abort Status Register
+	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
+	AT91_REG	 Reserved0[21]; 	// 
+	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
+	AT91_REG	 MC_FCR; 	// MC Flash Command Register
+	AT91_REG	 MC_FSR; 	// MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91_REG	 Reserved1[48]; 	// 
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	// 
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved3[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved1[3]; 	// 
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
+	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
+	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
+	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
+	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
+	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
+	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
+	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
+	AT91_REG	 PWMC_SR; 	// PWMC Status Register
+	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
+	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
+	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
+	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
+	AT91_REG	 Reserved0[55]; 	// 
+	AT91_REG	 PWMC_VR; 	// PWMC Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
+	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
+	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
+	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
+	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
+	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
+	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
+	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
+
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+	AT91_REG	 CAN_MR; 	// Mode Register
+	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
+	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
+	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
+	AT91_REG	 CAN_SR; 	// Status Register
+	AT91_REG	 CAN_BR; 	// Baudrate Register
+	AT91_REG	 CAN_TIM; 	// Timer Register
+	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
+	AT91_REG	 CAN_ECR; 	// Error Counter Register
+	AT91_REG	 CAN_TCR; 	// Transfer Command Register
+	AT91_REG	 CAN_ACR; 	// Abort Command Register
+	AT91_REG	 Reserved0[52]; 	// 
+	AT91_REG	 CAN_VR; 	// Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
+	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
+	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
+	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
+	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
+	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
+	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
+	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
+	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
+	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
+	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
+	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
+	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
+	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
+	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
+	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
+
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+	AT91_REG	 EMAC_NCR; 	// Network Control Register
+	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
+	AT91_REG	 EMAC_NSR; 	// Network Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
+	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
+	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
+	AT91_REG	 EMAC_RSR; 	// Receive Status Register
+	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
+	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
+	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
+	AT91_REG	 EMAC_PTR; 	// Pause Time Register
+	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
+	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
+	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
+	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
+	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
+	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
+	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
+	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
+	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
+	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
+	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
+	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
+	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
+	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
+	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
+	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
+	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
+	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
+	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
+	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
+	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
+	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
+	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
+	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
+	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
+	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
+	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
+	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
+	AT91_REG	 Reserved1[13]; 	// 
+	AT91_REG	 EMAC_REV; 	// Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+	AT91_REG	 ADC_CR; 	// ADC Control Register
+	AT91_REG	 ADC_MR; 	// ADC Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
+	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
+	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
+	AT91_REG	 ADC_SR; 	// ADC Status Register
+	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
+	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
+	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
+	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
+	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
+	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
+	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
+	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
+	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
+	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
+	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
+	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
+	AT91_REG	 ADC_RCR; 	// Receive Counter Register
+	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
+	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+	AT91_REG	 AES_CR; 	// Control Register
+	AT91_REG	 AES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AES_IER; 	// Interrupt Enable Register
+	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AES_ISR; 	// Interrupt Status Register
+	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
+	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
+	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved2[35]; 	// 
+	AT91_REG	 AES_VR; 	// AES Version Register
+	AT91_REG	 AES_RPR; 	// Receive Pointer Register
+	AT91_REG	 AES_RCR; 	// Receive Counter Register
+	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 AES_TCR; 	// Transmit Counter Register
+	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
+
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
+#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
+#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
+#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
+#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+	AT91_REG	 TDES_CR; 	// Control Register
+	AT91_REG	 TDES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
+	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
+	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
+	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
+	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved4[37]; 	// 
+	AT91_REG	 TDES_VR; 	// TDES Version Register
+	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
+	AT91_REG	 TDES_RCR; 	// Receive Counter Register
+	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
+	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
+
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
+#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ========== 
+#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ========== 
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ========== 
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ========== 
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ========== 
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ========== 
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ========== 
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ========== 
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ========== 
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ========== 
+#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ========== 
+#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ========== 
+#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ========== 
+#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ========== 
+#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ========== 
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
+#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
+#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
+#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
+#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
+#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
+#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
+#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
+#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
+#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
+#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
+#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
+#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
+#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
+#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
+#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
+#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
+#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
+#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
+#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
+#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
+#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
+#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
+#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
+#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
+#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
+#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
+#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
+#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
+#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
+#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
+#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
+#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
+#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
+#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
+#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
+#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
+#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
+#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
+#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
+#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
+#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
+#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
+#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte)
+#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte)
+
+#endif
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
new file mode 100644
index 0000000..96b680a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
@@ -0,0 +1,2446 @@
+//  ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+//  ----------------------------------------------------------------------------
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  ----------------------------------------------------------------------------
+// File Name           : AT91SAM7X128.h
+// Object              : AT91SAM7X128 definitions
+// Generated           : AT91 SW Application Group  05/20/2005 (16:22:23)
+// 
+// CVS Reference       : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//
+// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
+// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
+// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
+// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
+// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
+// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
+// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
+// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
+// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
+// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
+// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
+// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
+// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+//  ----------------------------------------------------------------------------
+
+// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+// *** Register offset in AT91S_AIC structure ***
+#define AIC_SMR         ( 0) // Source Mode Register
+#define AIC_SVR         (128) // Source Vector Register
+#define AIC_IVR         (256) // IRQ Vector Register
+#define AIC_FVR         (260) // FIQ Vector Register
+#define AIC_ISR         (264) // Interrupt Status Register
+#define AIC_IPR         (268) // Interrupt Pending Register
+#define AIC_IMR         (272) // Interrupt Mask Register
+#define AIC_CISR        (276) // Core Interrupt Status Register
+#define AIC_IECR        (288) // Interrupt Enable Command Register
+#define AIC_IDCR        (292) // Interrupt Disable Command Register
+#define AIC_ICCR        (296) // Interrupt Clear Command Register
+#define AIC_ISCR        (300) // Interrupt Set Command Register
+#define AIC_EOICR       (304) // End of Interrupt Command Register
+#define AIC_SPU         (308) // Spurious Vector Register
+#define AIC_DCR         (312) // Debug Control Register (Protect)
+#define AIC_FFER        (320) // Fast Forcing Enable Register
+#define AIC_FFDR        (324) // Fast Forcing Disable Register
+#define AIC_FFSR        (328) // Fast Forcing Status Register
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
+#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT        (0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+// *** Register offset in AT91S_PDC structure ***
+#define PDC_RPR         ( 0) // Receive Pointer Register
+#define PDC_RCR         ( 4) // Receive Counter Register
+#define PDC_TPR         ( 8) // Transmit Pointer Register
+#define PDC_TCR         (12) // Transmit Counter Register
+#define PDC_RNPR        (16) // Receive Next Pointer Register
+#define PDC_RNCR        (20) // Receive Next Counter Register
+#define PDC_TNPR        (24) // Transmit Next Pointer Register
+#define PDC_TNCR        (28) // Transmit Next Counter Register
+#define PDC_PTCR        (32) // PDC Transfer Control Register
+#define PDC_PTSR        (36) // PDC Transfer Status Register
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN           (0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS          (0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN           (0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS          (0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+// *** Register offset in AT91S_DBGU structure ***
+#define DBGU_CR         ( 0) // Control Register
+#define DBGU_MR         ( 4) // Mode Register
+#define DBGU_IER        ( 8) // Interrupt Enable Register
+#define DBGU_IDR        (12) // Interrupt Disable Register
+#define DBGU_IMR        (16) // Interrupt Mask Register
+#define DBGU_CSR        (20) // Channel Status Register
+#define DBGU_RHR        (24) // Receiver Holding Register
+#define DBGU_THR        (28) // Transmitter Holding Register
+#define DBGU_BRGR       (32) // Baud Rate Generator Register
+#define DBGU_CIDR       (64) // Chip ID Register
+#define DBGU_EXID       (68) // Chip ID Extension Register
+#define DBGU_FNTR       (72) // Force NTRST Register
+#define DBGU_RPR        (256) // Receive Pointer Register
+#define DBGU_RCR        (260) // Receive Counter Register
+#define DBGU_TPR        (264) // Transmit Pointer Register
+#define DBGU_TCR        (268) // Transmit Counter Register
+#define DBGU_RNPR       (272) // Receive Next Pointer Register
+#define DBGU_RNCR       (276) // Receive Next Counter Register
+#define DBGU_TNPR       (280) // Transmit Next Pointer Register
+#define DBGU_TNCR       (284) // Transmit Next Counter Register
+#define DBGU_PTCR       (288) // PDC Transfer Control Register
+#define DBGU_PTSR       (292) // PDC Transfer Status Register
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX            (0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX            (0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN             (0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS            (0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN             (0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS            (0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA           (0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR              (0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE           (0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY            (0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY            (0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX            (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX            (0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE             (0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME            (0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE             (0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY          (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE           (0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF           (0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX          (0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX          (0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST      (0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PIO structure ***
+#define PIO_PER         ( 0) // PIO Enable Register
+#define PIO_PDR         ( 4) // PIO Disable Register
+#define PIO_PSR         ( 8) // PIO Status Register
+#define PIO_OER         (16) // Output Enable Register
+#define PIO_ODR         (20) // Output Disable Registerr
+#define PIO_OSR         (24) // Output Status Register
+#define PIO_IFER        (32) // Input Filter Enable Register
+#define PIO_IFDR        (36) // Input Filter Disable Register
+#define PIO_IFSR        (40) // Input Filter Status Register
+#define PIO_SODR        (48) // Set Output Data Register
+#define PIO_CODR        (52) // Clear Output Data Register
+#define PIO_ODSR        (56) // Output Data Status Register
+#define PIO_PDSR        (60) // Pin Data Status Register
+#define PIO_IER         (64) // Interrupt Enable Register
+#define PIO_IDR         (68) // Interrupt Disable Register
+#define PIO_IMR         (72) // Interrupt Mask Register
+#define PIO_ISR         (76) // Interrupt Status Register
+#define PIO_MDER        (80) // Multi-driver Enable Register
+#define PIO_MDDR        (84) // Multi-driver Disable Register
+#define PIO_MDSR        (88) // Multi-driver Status Register
+#define PIO_PPUDR       (96) // Pull-up Disable Register
+#define PIO_PPUER       (100) // Pull-up Enable Register
+#define PIO_PPUSR       (104) // Pull-up Status Register
+#define PIO_ASR         (112) // Select A Register
+#define PIO_BSR         (116) // Select B Register
+#define PIO_ABSR        (120) // AB Select Status Register
+#define PIO_OWER        (160) // Output Write Enable Register
+#define PIO_OWDR        (164) // Output Write Disable Register
+#define PIO_OWSR        (168) // Output Write Status Register
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+// *** Register offset in AT91S_CKGR structure ***
+#define CKGR_MOR        ( 0) // Main Oscillator Register
+#define CKGR_MCFR       ( 4) // Main Clock  Frequency Register
+#define CKGR_PLLR       (12) // PLL Register
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN         (0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS      (0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT        (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF          (0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY        (0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV            (0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT       (0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT            (0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL            (0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV         (0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PMC structure ***
+#define PMC_SCER        ( 0) // System Clock Enable Register
+#define PMC_SCDR        ( 4) // System Clock Disable Register
+#define PMC_SCSR        ( 8) // System Clock Status Register
+#define PMC_PCER        (16) // Peripheral Clock Enable Register
+#define PMC_PCDR        (20) // Peripheral Clock Disable Register
+#define PMC_PCSR        (24) // Peripheral Clock Status Register
+#define PMC_MOR         (32) // Main Oscillator Register
+#define PMC_MCFR        (36) // Main Clock  Frequency Register
+#define PMC_PLLR        (44) // PLL Register
+#define PMC_MCKR        (48) // Master Clock Register
+#define PMC_PCKR        (64) // Programmable Clock Register
+#define PMC_IER         (96) // Interrupt Enable Register
+#define PMC_IDR         (100) // Interrupt Disable Register
+#define PMC_SR          (104) // Status Register
+#define PMC_IMR         (108) // Interrupt Mask Register
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK             (0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP             (0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0            (0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1            (0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2            (0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3            (0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS             (0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES            (0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS           (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK            (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY          (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY         (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY         (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY         (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY         (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RSTC structure ***
+#define RSTC_RCR        ( 0) // Reset Control Register
+#define RSTC_RSR        ( 4) // Reset Status Register
+#define RSTC_RMR        ( 8) // Reset Mode Register
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST        (0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST         (0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST         (0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY            (0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS          (0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS         (0x1 <<  1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP         (0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_RSTC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL          (0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP          (0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN         (0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN        (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL          (0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN         (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RTTC structure ***
+#define RTTC_RTMR       ( 0) // Real-time Mode Register
+#define RTTC_RTAR       ( 4) // Real-time Alarm Register
+#define RTTC_RTVR       ( 8) // Real-time Value Register
+#define RTTC_RTSR       (12) // Real-time Status Register
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES         (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN         (0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN      (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST         (0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV           (0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV           (0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS           (0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC         (0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PITC structure ***
+#define PITC_PIMR       ( 0) // Period Interval Mode Register
+#define PITC_PISR       ( 4) // Period Interval Status Register
+#define PITC_PIVR       ( 8) // Period Interval Value Register
+#define PITC_PIIR       (12) // Period Interval Image Register
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV            (0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN          (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN         (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS           (0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV           (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT          (0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_WDTC structure ***
+#define WDTC_WDCR       ( 0) // Watchdog Control Register
+#define WDTC_WDMR       ( 4) // Watchdog Mode Register
+#define WDTC_WDSR       ( 8) // Watchdog Status Register
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT         (0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY            (0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV            (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN         (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN        (0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC        (0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS          (0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD            (0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT       (0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT      (0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF          (0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR          (0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_VREG structure ***
+#define VREG_MR         ( 0) // Voltage Regulator Mode Register
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+#define AT91C_VREG_PSTDBY         (0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_MC structure ***
+#define MC_RCR          ( 0) // MC Remap Control Register
+#define MC_ASR          ( 4) // MC Abort Status Register
+#define MC_AASR         ( 8) // MC Abort Address Status Register
+#define MC_FMR          (96) // MC Flash Mode Register
+#define MC_FCR          (100) // MC Flash Command Register
+#define MC_FSR          (104) // MC Flash Status Register
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB              (0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD           (0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD           (0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ            (0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP           (0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0             (0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1             (0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0           (0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1           (0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY             (0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE            (0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE            (0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP             (0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS              (0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN             (0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD             (0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN            (0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY              (0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY         (0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0           (0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1           (0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2           (0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3           (0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4           (0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5           (0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6           (0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7           (0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0           (0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1           (0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2           (0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3           (0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4           (0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5           (0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6           (0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7           (0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8           (0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9           (0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10          (0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11          (0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12          (0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13          (0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14          (0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15          (0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SPI structure ***
+#define SPI_CR          ( 0) // Control Register
+#define SPI_MR          ( 4) // Mode Register
+#define SPI_RDR         ( 8) // Receive Data Register
+#define SPI_TDR         (12) // Transmit Data Register
+#define SPI_SR          (16) // Status Register
+#define SPI_IER         (20) // Interrupt Enable Register
+#define SPI_IDR         (24) // Interrupt Disable Register
+#define SPI_IMR         (28) // Interrupt Mask Register
+#define SPI_CSR         (48) // Chip Select Register
+#define SPI_RPR         (256) // Receive Pointer Register
+#define SPI_RCR         (260) // Receive Counter Register
+#define SPI_TPR         (264) // Transmit Pointer Register
+#define SPI_TCR         (268) // Transmit Counter Register
+#define SPI_RNPR        (272) // Receive Next Pointer Register
+#define SPI_RNCR        (276) // Receive Next Counter Register
+#define SPI_TNPR        (280) // Transmit Next Pointer Register
+#define SPI_TNCR        (284) // Transmit Next Counter Register
+#define SPI_PTCR        (288) // PDC Transfer Control Register
+#define SPI_PTSR        (292) // PDC Transfer Status Register
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN           (0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS          (0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST           (0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER        (0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR            (0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS              (0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC          (0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV            (0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS         (0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB             (0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS             (0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS          (0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD              (0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD              (0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF            (0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE            (0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF            (0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES           (0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX           (0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX           (0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF          (0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE          (0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR            (0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY         (0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS          (0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL            (0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA           (0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT           (0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS            (0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR            (0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS           (0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT          (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+// *** Register offset in AT91S_USART structure ***
+#define US_CR           ( 0) // Control Register
+#define US_MR           ( 4) // Mode Register
+#define US_IER          ( 8) // Interrupt Enable Register
+#define US_IDR          (12) // Interrupt Disable Register
+#define US_IMR          (16) // Interrupt Mask Register
+#define US_CSR          (20) // Channel Status Register
+#define US_RHR          (24) // Receiver Holding Register
+#define US_THR          (28) // Transmitter Holding Register
+#define US_BRGR         (32) // Baud Rate Generator Register
+#define US_RTOR         (36) // Receiver Time-out Register
+#define US_TTGR         (40) // Transmitter Time-guard Register
+#define US_FIDI         (64) // FI_DI_Ratio Register
+#define US_NER          (68) // Nb Errors Register
+#define US_IF           (76) // IRDA_FILTER Register
+#define US_RPR          (256) // Receive Pointer Register
+#define US_RCR          (260) // Receive Counter Register
+#define US_TPR          (264) // Transmit Pointer Register
+#define US_TCR          (268) // Transmit Counter Register
+#define US_RNPR         (272) // Receive Next Pointer Register
+#define US_RNCR         (276) // Receive Next Counter Register
+#define US_TNPR         (280) // Transmit Next Pointer Register
+#define US_TNCR         (284) // Transmit Next Counter Register
+#define US_PTCR         (288) // PDC Transfer Control Register
+#define US_PTSR         (292) // PDC Transfer Status Register
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK           (0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK           (0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO            (0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA            (0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT            (0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK          (0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO            (0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN            (0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS           (0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN            (0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS           (0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE           (0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS             (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL             (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC             (0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP           (0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF             (0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9            (0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO             (0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER             (0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK            (0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK           (0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER         (0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER           (0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK            (0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT          (0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION        (0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK             (0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC             (0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC            (0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC            (0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC            (0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI               (0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR              (0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD              (0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS              (0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SSC structure ***
+#define SSC_CR          ( 0) // Control Register
+#define SSC_CMR         ( 4) // Clock Mode Register
+#define SSC_RCMR        (16) // Receive Clock ModeRegister
+#define SSC_RFMR        (20) // Receive Frame Mode Register
+#define SSC_TCMR        (24) // Transmit Clock Mode Register
+#define SSC_TFMR        (28) // Transmit Frame Mode Register
+#define SSC_RHR         (32) // Receive Holding Register
+#define SSC_THR         (36) // Transmit Holding Register
+#define SSC_RSHR        (48) // Receive Sync Holding Register
+#define SSC_TSHR        (52) // Transmit Sync Holding Register
+#define SSC_SR          (64) // Status Register
+#define SSC_IER         (68) // Interrupt Enable Register
+#define SSC_IDR         (72) // Interrupt Disable Register
+#define SSC_IMR         (76) // Interrupt Mask Register
+#define SSC_RPR         (256) // Receive Pointer Register
+#define SSC_RCR         (260) // Receive Counter Register
+#define SSC_TPR         (264) // Transmit Pointer Register
+#define SSC_TCR         (268) // Transmit Counter Register
+#define SSC_RNPR        (272) // Receive Next Pointer Register
+#define SSC_RNCR        (276) // Receive Next Counter Register
+#define SSC_TNPR        (280) // Transmit Next Pointer Register
+#define SSC_TNCR        (284) // Transmit Next Counter Register
+#define SSC_PTCR        (288) // PDC Transfer Control Register
+#define SSC_PTSR        (292) // PDC Transfer Status Register
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN            (0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS           (0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN            (0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS           (0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST           (0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS             (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO             (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI             (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START           (0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY          (0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD          (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN          (0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP            (0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF            (0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB           (0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN           (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS            (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE          (0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF          (0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN           (0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY           (0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY         (0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX           (0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE          (0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY           (0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN           (0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX           (0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF          (0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN           (0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN           (0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA           (0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA           (0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TWI structure ***
+#define TWI_CR          ( 0) // Control Register
+#define TWI_MMR         ( 4) // Master Mode Register
+#define TWI_IADR        (12) // Internal Address Register
+#define TWI_CWGR        (16) // Clock Waveform Generator Register
+#define TWI_SR          (32) // Status Register
+#define TWI_IER         (36) // Interrupt Enable Register
+#define TWI_IDR         (40) // Interrupt Disable Register
+#define TWI_IMR         (44) // Interrupt Mask Register
+#define TWI_RHR         (48) // Receive Holding Register
+#define TWI_THR         (52) // Transmit Holding Register
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START           (0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP            (0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN            (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS           (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST           (0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ          (0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD           (0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR            (0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV           (0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV           (0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV           (0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP          (0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY           (0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY           (0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE            (0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE            (0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK            (0x1 <<  8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC_CH structure ***
+#define PWMC_CMR        ( 0) // Channel Mode Register
+#define PWMC_CDTYR      ( 4) // Channel Duty Cycle Register
+#define PWMC_CPRDR      ( 8) // Channel Period Register
+#define PWMC_CCNTR      (12) // Channel Counter Register
+#define PWMC_CUPDR      (16) // Channel Update Register
+#define PWMC_Reserved   (20) // Reserved
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE           (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG           (0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL           (0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD            (0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY           (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD           (0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT           (0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD           (0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC structure ***
+#define PWMC_MR         ( 0) // PWMC Mode Register
+#define PWMC_ENA        ( 4) // PWMC Enable Register
+#define PWMC_DIS        ( 8) // PWMC Disable Register
+#define PWMC_SR         (12) // PWMC Status Register
+#define PWMC_IER        (16) // PWMC Interrupt Enable Register
+#define PWMC_IDR        (20) // PWMC Interrupt Disable Register
+#define PWMC_IMR        (24) // PWMC Interrupt Mask Register
+#define PWMC_ISR        (28) // PWMC Interrupt Status Register
+#define PWMC_VR         (252) // PWMC Version Register
+#define PWMC_CH         (512) // PWMC Channel
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA           (0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA           (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB           (0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB           (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0          (0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1          (0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2          (0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3          (0x1 <<  3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+// *** Register offset in AT91S_UDP structure ***
+#define UDP_NUM         ( 0) // Frame Number Register
+#define UDP_GLBSTATE    ( 4) // Global State Register
+#define UDP_FADDR       ( 8) // Function Address Register
+#define UDP_IER         (16) // Interrupt Enable Register
+#define UDP_IDR         (20) // Interrupt Disable Register
+#define UDP_IMR         (24) // Interrupt Mask Register
+#define UDP_ISR         (28) // Interrupt Status Register
+#define UDP_ICR         (32) // Interrupt Clear Register
+#define UDP_RSTEP       (40) // Reset Endpoint Register
+#define UDP_CSR         (48) // Endpoint Control and Status Register
+#define UDP_FDR         (80) // Endpoint FIFO Data Register
+#define UDP_TXVC        (116) // Transceiver Control Register
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM         (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR         (0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK          (0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN          (0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG           (0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR             (0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR         (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE          (0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD            (0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN             (0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0          (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1          (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2          (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3          (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4          (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5          (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP          (0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM           (0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM          (0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT          (0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP          (0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES       (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0             (0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1             (0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2             (0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3             (0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4             (0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5             (0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP          (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0     (0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP         (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR        (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY        (0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL      (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1     (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR             (0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE          (0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE           (0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS           (0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT       (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS          (0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON            (0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TC structure ***
+#define TC_CCR          ( 0) // Channel Control Register
+#define TC_CMR          ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
+#define TC_CV           (16) // Counter Value
+#define TC_RA           (20) // Register A
+#define TC_RB           (24) // Register B
+#define TC_RC           (28) // Register C
+#define TC_SR           (32) // Status Register
+#define TC_IER          (36) // Interrupt Enable Register
+#define TC_IDR          (40) // Interrupt Disable Register
+#define TC_IMR          (44) // Interrupt Mask Register
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN            (0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS           (0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG            (0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS             (0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI             (0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST            (0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS           (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS           (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG          (0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG          (0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT             (0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG           (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG           (0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL          (0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG           (0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE             (0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA             (0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA             (0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC             (0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB             (0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT            (0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG           (0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB             (0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC             (0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT            (0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG           (0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS            (0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS            (0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS             (0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS             (0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS             (0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS            (0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS            (0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS            (0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA           (0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA            (0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB            (0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TCB structure ***
+#define TCB_TC0         ( 0) // TC Channel 0
+#define TCB_TC1         (64) // TC Channel 1
+#define TCB_TC2         (128) // TC Channel 2
+#define TCB_BCR         (192) // TC Block Control Register
+#define TCB_BMR         (196) // TC Block Mode Register
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC            (0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S         (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S         (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S         (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// *****************************************************************************
+// *** Register offset in AT91S_CAN_MB structure ***
+#define CAN_MB_MMR      ( 0) // MailBox Mode Register
+#define CAN_MB_MAM      ( 4) // MailBox Acceptance Mask Register
+#define CAN_MB_MID      ( 8) // MailBox ID Register
+#define CAN_MB_MFID     (12) // MailBox Family ID Register
+#define CAN_MB_MSR      (16) // MailBox Status Register
+#define CAN_MB_MDL      (20) // MailBox Data Low Register
+#define CAN_MB_MDH      (24) // MailBox Data High Register
+#define CAN_MB_MCR      (28) // MailBox Control Register
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+#define AT91C_CAN_MTIMEMARK       (0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR           (0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT             (0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define 	AT91C_CAN_MOT_DIS                  (0x0 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RX                   (0x1 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RXOVERWRITE          (0x2 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_TX                   (0x3 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_CONSUMER             (0x4 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_PRODUCER             (0x5 << 24) // (CAN_MB) 
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+#define AT91C_CAN_MIDvB           (0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA           (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE            (0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+#define AT91C_CAN_MTIMESTAMP      (0xFFFF <<  0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC            (0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR            (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT            (0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY            (0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI             (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+#define AT91C_CAN_MACR            (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR            (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// *****************************************************************************
+// *** Register offset in AT91S_CAN structure ***
+#define CAN_MR          ( 0) // Mode Register
+#define CAN_IER         ( 4) // Interrupt Enable Register
+#define CAN_IDR         ( 8) // Interrupt Disable Register
+#define CAN_IMR         (12) // Interrupt Mask Register
+#define CAN_SR          (16) // Status Register
+#define CAN_BR          (20) // Baudrate Register
+#define CAN_TIM         (24) // Timer Register
+#define CAN_TIMESTP     (28) // Time Stamp Register
+#define CAN_ECR         (32) // Error Counter Register
+#define CAN_TCR         (36) // Transfer Command Register
+#define CAN_ACR         (40) // Abort Command Register
+#define CAN_VR          (252) // Version Register
+#define CAN_MB0         (512) // CAN Mailbox 0
+#define CAN_MB1         (544) // CAN Mailbox 1
+#define CAN_MB2         (576) // CAN Mailbox 2
+#define CAN_MB3         (608) // CAN Mailbox 3
+#define CAN_MB4         (640) // CAN Mailbox 4
+#define CAN_MB5         (672) // CAN Mailbox 5
+#define CAN_MB6         (704) // CAN Mailbox 6
+#define CAN_MB7         (736) // CAN Mailbox 7
+#define CAN_MB8         (768) // CAN Mailbox 8
+#define CAN_MB9         (800) // CAN Mailbox 9
+#define CAN_MB10        (832) // CAN Mailbox 10
+#define CAN_MB11        (864) // CAN Mailbox 11
+#define CAN_MB12        (896) // CAN Mailbox 12
+#define CAN_MB13        (928) // CAN Mailbox 13
+#define CAN_MB14        (960) // CAN Mailbox 14
+#define CAN_MB15        (992) // CAN Mailbox 15
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+#define AT91C_CAN_CANEN           (0x1 <<  0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM             (0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM             (0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL             (0x1 <<  3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF            (0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM             (0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ          (0x1 <<  6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT            (0x1 <<  7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+#define AT91C_CAN_MB0             (0x1 <<  0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1             (0x1 <<  1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2             (0x1 <<  2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3             (0x1 <<  3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4             (0x1 <<  4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5             (0x1 <<  5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6             (0x1 <<  6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7             (0x1 <<  7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8             (0x1 <<  8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9             (0x1 <<  9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10            (0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11            (0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12            (0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13            (0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14            (0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15            (0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA            (0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN            (0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP            (0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF            (0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP           (0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP          (0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF            (0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP            (0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR            (0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR            (0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR            (0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR            (0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR            (0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+#define AT91C_CAN_RBSY            (0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY            (0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY            (0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+#define AT91C_CAN_PHASE2          (0x7 <<  0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1          (0x7 <<  4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG          (0x7 <<  8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC            (0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP             (0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP             (0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+#define AT91C_CAN_TIMER           (0xFFFF <<  0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+#define AT91C_CAN_REC             (0xFF <<  0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC             (0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+#define AT91C_CAN_TIMRST          (0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+// *** Register offset in AT91S_EMAC structure ***
+#define EMAC_NCR        ( 0) // Network Control Register
+#define EMAC_NCFGR      ( 4) // Network Configuration Register
+#define EMAC_NSR        ( 8) // Network Status Register
+#define EMAC_TSR        (20) // Transmit Status Register
+#define EMAC_RBQP       (24) // Receive Buffer Queue Pointer
+#define EMAC_TBQP       (28) // Transmit Buffer Queue Pointer
+#define EMAC_RSR        (32) // Receive Status Register
+#define EMAC_ISR        (36) // Interrupt Status Register
+#define EMAC_IER        (40) // Interrupt Enable Register
+#define EMAC_IDR        (44) // Interrupt Disable Register
+#define EMAC_IMR        (48) // Interrupt Mask Register
+#define EMAC_MAN        (52) // PHY Maintenance Register
+#define EMAC_PTR        (56) // Pause Time Register
+#define EMAC_PFR        (60) // Pause Frames received Register
+#define EMAC_FTO        (64) // Frames Transmitted OK Register
+#define EMAC_SCF        (68) // Single Collision Frame Register
+#define EMAC_MCF        (72) // Multiple Collision Frame Register
+#define EMAC_FRO        (76) // Frames Received OK Register
+#define EMAC_FCSE       (80) // Frame Check Sequence Error Register
+#define EMAC_ALE        (84) // Alignment Error Register
+#define EMAC_DTF        (88) // Deferred Transmission Frame Register
+#define EMAC_LCOL       (92) // Late Collision Register
+#define EMAC_ECOL       (96) // Excessive Collision Register
+#define EMAC_TUND       (100) // Transmit Underrun Error Register
+#define EMAC_CSE        (104) // Carrier Sense Error Register
+#define EMAC_RRE        (108) // Receive Ressource Error Register
+#define EMAC_ROV        (112) // Receive Overrun Errors Register
+#define EMAC_RSE        (116) // Receive Symbol Errors Register
+#define EMAC_ELE        (120) // Excessive Length Errors Register
+#define EMAC_RJA        (124) // Receive Jabbers Register
+#define EMAC_USF        (128) // Undersize Frames Register
+#define EMAC_STE        (132) // SQE Test Error Register
+#define EMAC_RLE        (136) // Receive Length Field Mismatch Register
+#define EMAC_TPF        (140) // Transmitted Pause Frames Register
+#define EMAC_HRB        (144) // Hash Address Bottom[31:0]
+#define EMAC_HRT        (148) // Hash Address Top[63:32]
+#define EMAC_SA1L       (152) // Specific Address 1 Bottom, First 4 bytes
+#define EMAC_SA1H       (156) // Specific Address 1 Top, Last 2 bytes
+#define EMAC_SA2L       (160) // Specific Address 2 Bottom, First 4 bytes
+#define EMAC_SA2H       (164) // Specific Address 2 Top, Last 2 bytes
+#define EMAC_SA3L       (168) // Specific Address 3 Bottom, First 4 bytes
+#define EMAC_SA3H       (172) // Specific Address 3 Top, Last 2 bytes
+#define EMAC_SA4L       (176) // Specific Address 4 Bottom, First 4 bytes
+#define EMAC_SA4H       (180) // Specific Address 4 Top, Last 2 bytes
+#define EMAC_TID        (184) // Type ID Checking Register
+#define EMAC_TPQ        (188) // Transmit Pause Quantum Register
+#define EMAC_USRIO      (192) // USER Input/Output Register
+#define EMAC_WOL        (196) // Wake On LAN Register
+#define EMAC_REV        (252) // Revision Register
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB             (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB            (0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE             (0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE             (0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE            (0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT        (0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT        (0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT         (0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP             (0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART         (0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT          (0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR           (0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ            (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD            (0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD             (0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME         (0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF            (0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC            (0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI            (0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI            (0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG            (0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE            (0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK            (0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY            (0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE            (0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF           (0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE           (0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS          (0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD          (0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS         (0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR          (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO           (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE           (0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR            (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL            (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES           (0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO            (0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX            (0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP           (0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND            (0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA            (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC            (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR            (0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD            (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP          (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR          (0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR          (0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR          (0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX           (0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR          (0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP          (0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK           (0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR           (0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP          (0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE           (0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ            (0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA           (0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE           (0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA           (0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA           (0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW             (0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF            (0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII           (0x1 <<  0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP             (0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG            (0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP            (0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1            (0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF         (0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF        (0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+// *** Register offset in AT91S_ADC structure ***
+#define ADC_CR          ( 0) // ADC Control Register
+#define ADC_MR          ( 4) // ADC Mode Register
+#define ADC_CHER        (16) // ADC Channel Enable Register
+#define ADC_CHDR        (20) // ADC Channel Disable Register
+#define ADC_CHSR        (24) // ADC Channel Status Register
+#define ADC_SR          (28) // ADC Status Register
+#define ADC_LCDR        (32) // ADC Last Converted Data Register
+#define ADC_IER         (36) // ADC Interrupt Enable Register
+#define ADC_IDR         (40) // ADC Interrupt Disable Register
+#define ADC_IMR         (44) // ADC Interrupt Mask Register
+#define ADC_CDR0        (48) // ADC Channel Data Register 0
+#define ADC_CDR1        (52) // ADC Channel Data Register 1
+#define ADC_CDR2        (56) // ADC Channel Data Register 2
+#define ADC_CDR3        (60) // ADC Channel Data Register 3
+#define ADC_CDR4        (64) // ADC Channel Data Register 4
+#define ADC_CDR5        (68) // ADC Channel Data Register 5
+#define ADC_CDR6        (72) // ADC Channel Data Register 6
+#define ADC_CDR7        (76) // ADC Channel Data Register 7
+#define ADC_RPR         (256) // Receive Pointer Register
+#define ADC_RCR         (260) // Receive Counter Register
+#define ADC_TPR         (264) // Transmit Pointer Register
+#define ADC_TCR         (268) // Transmit Counter Register
+#define ADC_RNPR        (272) // Receive Next Pointer Register
+#define ADC_RNCR        (276) // Receive Next Counter Register
+#define ADC_TNPR        (280) // Transmit Next Pointer Register
+#define ADC_TNCR        (284) // Transmit Next Counter Register
+#define ADC_PTCR        (288) // PDC Transfer Control Register
+#define ADC_PTSR        (292) // PDC Transfer Status Register
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST           (0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START           (0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN           (0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL          (0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES          (0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP           (0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL         (0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP         (0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM           (0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0             (0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1             (0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2             (0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3             (0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4             (0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5             (0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6             (0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7             (0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0            (0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1            (0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2            (0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3            (0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4            (0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5            (0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6            (0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7            (0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0           (0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1           (0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2           (0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3           (0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4           (0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5           (0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6           (0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7           (0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY            (0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE           (0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX           (0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF          (0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA           (0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA            (0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// *****************************************************************************
+// *** Register offset in AT91S_AES structure ***
+#define AES_CR          ( 0) // Control Register
+#define AES_MR          ( 4) // Mode Register
+#define AES_IER         (16) // Interrupt Enable Register
+#define AES_IDR         (20) // Interrupt Disable Register
+#define AES_IMR         (24) // Interrupt Mask Register
+#define AES_ISR         (28) // Interrupt Status Register
+#define AES_KEYWxR      (32) // Key Word x Register
+#define AES_IDATAxR     (64) // Input Data x Register
+#define AES_ODATAxR     (80) // Output Data x Register
+#define AES_IVxR        (96) // Initialization Vector x Register
+#define AES_VR          (252) // AES Version Register
+#define AES_RPR         (256) // Receive Pointer Register
+#define AES_RCR         (260) // Receive Counter Register
+#define AES_TPR         (264) // Transmit Pointer Register
+#define AES_TCR         (268) // Transmit Counter Register
+#define AES_RNPR        (272) // Receive Next Pointer Register
+#define AES_RNCR        (276) // Receive Next Counter Register
+#define AES_TNPR        (280) // Transmit Next Pointer Register
+#define AES_TNCR        (284) // Transmit Next Counter Register
+#define AES_PTCR        (288) // PDC Transfer Control Register
+#define AES_PTSR        (292) // PDC Transfer Status Register
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+#define AT91C_AES_START           (0x1 <<  0) // (AES) Starts Processing
+#define AT91C_AES_SWRST           (0x1 <<  8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED        (0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+#define AT91C_AES_CIPHER          (0x1 <<  0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY         (0xF <<  4) // (AES) Processing Delay
+#define AT91C_AES_SMOD            (0x3 <<  8) // (AES) Start Mode
+#define 	AT91C_AES_SMOD_MANUAL               (0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define 	AT91C_AES_SMOD_AUTO                 (0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define 	AT91C_AES_SMOD_PDC                  (0x2 <<  8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD           (0x7 << 12) // (AES) Operation Mode
+#define 	AT91C_AES_OPMOD_ECB                  (0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define 	AT91C_AES_OPMOD_CBC                  (0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define 	AT91C_AES_OPMOD_OFB                  (0x2 << 12) // (AES) OFB Output Feedback mode.
+#define 	AT91C_AES_OPMOD_CFB                  (0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define 	AT91C_AES_OPMOD_CTR                  (0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD             (0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS            (0x7 << 16) // (AES) Cipher Feedback Data Size
+#define 	AT91C_AES_CFBS_128_BIT              (0x0 << 16) // (AES) 128-bit.
+#define 	AT91C_AES_CFBS_64_BIT               (0x1 << 16) // (AES) 64-bit.
+#define 	AT91C_AES_CFBS_32_BIT               (0x2 << 16) // (AES) 32-bit.
+#define 	AT91C_AES_CFBS_16_BIT               (0x3 << 16) // (AES) 16-bit.
+#define 	AT91C_AES_CFBS_8_BIT                (0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY            (0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE           (0x1F << 24) // (AES) Countermeasure Type
+#define 	AT91C_AES_CTYPE_TYPE1_EN             (0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE2_EN             (0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE3_EN             (0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE4_EN             (0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE5_EN             (0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_AES_DATRDY          (0x1 <<  0) // (AES) DATRDY
+#define AT91C_AES_ENDRX           (0x1 <<  1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX           (0x1 <<  2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF          (0x1 <<  3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE          (0x1 <<  4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD            (0x1 <<  8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_AES_URAT            (0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  (0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define 	AT91C_AES_URAT_WO_REG_READ          (0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// *****************************************************************************
+// *** Register offset in AT91S_TDES structure ***
+#define TDES_CR         ( 0) // Control Register
+#define TDES_MR         ( 4) // Mode Register
+#define TDES_IER        (16) // Interrupt Enable Register
+#define TDES_IDR        (20) // Interrupt Disable Register
+#define TDES_IMR        (24) // Interrupt Mask Register
+#define TDES_ISR        (28) // Interrupt Status Register
+#define TDES_KEY1WxR    (32) // Key 1 Word x Register
+#define TDES_KEY2WxR    (40) // Key 2 Word x Register
+#define TDES_KEY3WxR    (48) // Key 3 Word x Register
+#define TDES_IDATAxR    (64) // Input Data x Register
+#define TDES_ODATAxR    (80) // Output Data x Register
+#define TDES_IVxR       (96) // Initialization Vector x Register
+#define TDES_VR         (252) // TDES Version Register
+#define TDES_RPR        (256) // Receive Pointer Register
+#define TDES_RCR        (260) // Receive Counter Register
+#define TDES_TPR        (264) // Transmit Pointer Register
+#define TDES_TCR        (268) // Transmit Counter Register
+#define TDES_RNPR       (272) // Receive Next Pointer Register
+#define TDES_RNCR       (276) // Receive Next Counter Register
+#define TDES_TNPR       (280) // Transmit Next Pointer Register
+#define TDES_TNCR       (284) // Transmit Next Counter Register
+#define TDES_PTCR       (288) // PDC Transfer Control Register
+#define TDES_PTSR       (292) // PDC Transfer Status Register
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+#define AT91C_TDES_START          (0x1 <<  0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST          (0x1 <<  8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+#define AT91C_TDES_CIPHER         (0x1 <<  0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD        (0x1 <<  1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD         (0x1 <<  4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD           (0x3 <<  8) // (TDES) Start Mode
+#define 	AT91C_TDES_SMOD_MANUAL               (0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define 	AT91C_TDES_SMOD_AUTO                 (0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define 	AT91C_TDES_SMOD_PDC                  (0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD          (0x3 << 12) // (TDES) Operation Mode
+#define 	AT91C_TDES_OPMOD_ECB                  (0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define 	AT91C_TDES_OPMOD_CBC                  (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define 	AT91C_TDES_OPMOD_OFB                  (0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define 	AT91C_TDES_OPMOD_CFB                  (0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD            (0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS           (0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define 	AT91C_TDES_CFBS_64_BIT               (0x0 << 16) // (TDES) 64-bit.
+#define 	AT91C_TDES_CFBS_32_BIT               (0x1 << 16) // (TDES) 32-bit.
+#define 	AT91C_TDES_CFBS_16_BIT               (0x2 << 16) // (TDES) 16-bit.
+#define 	AT91C_TDES_CFBS_8_BIT                (0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_TDES_DATRDY         (0x1 <<  0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX          (0x1 <<  1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX          (0x1 <<  2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF         (0x1 <<  3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE         (0x1 <<  4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD           (0x1 <<  8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_TDES_URAT           (0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing.
+#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing.
+#define 	AT91C_TDES_URAT_WO_REG_READ          (0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR             (0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR             (0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR             (0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR             (0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR           (0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR             (0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR            (0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR            (0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR             (0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR             (0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR             (0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER            (0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR            (0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR            (0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR            (0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR            (0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR            (0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU             (0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR            (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR           (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR           (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR            (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR            (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR            (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR           (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR           (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR           (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR           (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID           (0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR           (0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR            (0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR            (0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR           (0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR             (0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR            (0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR             (0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR           (0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR            (0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR            (0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER            (0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR            (0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR           (0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR            (0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR           (0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER            (0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR          (0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR            (0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER            (0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR           (0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR           (0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR           (0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR            (0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR           (0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR          (0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR           (0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR            (0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER           (0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER           (0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR           (0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER          (0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR            (0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR            (0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR           (0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR           (0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER           (0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR            (0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR           (0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER            (0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR            (0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR           (0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER           (0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR          (0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR            (0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR            (0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR          (0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR            (0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER            (0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR           (0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER           (0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR           (0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR           (0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR           (0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR            (0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR           (0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR            (0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR            (0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR           (0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER          (0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR           (0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR            (0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR           (0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR            (0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR           (0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER           (0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR            (0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR           (0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER            (0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER            (0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR            (0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR           (0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR           (0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_IDR             (0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR             (0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR            (0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER            (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR            (0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR            (0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR            (0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR            (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR            (0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR            (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR            (0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_SCER            (0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR             (0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER             (0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR              (0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR            (0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR            (0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR            (0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR           (0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR           (0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR           (0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR           (0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR           (0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR           (0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR           (0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR           (0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR           (0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR           (0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR           (0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ========== 
+#define AT91C_VREG_MR             (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_ASR              (0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR              (0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR              (0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR             (0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR              (0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR              (0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR           (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR            (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR           (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR            (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR           (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR            (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR            (0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR           (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR           (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR           (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IMR            (0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER            (0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR             (0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR            (0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR            (0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR             (0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR            (0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR             (0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR            (0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR           (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR            (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR            (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR            (0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR           (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR           (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR            (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR           (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR           (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR           (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IER            (0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR             (0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR            (0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR             (0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR             (0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR            (0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR            (0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR            (0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR            (0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_RNCR            (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR            (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR             (0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR            (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR            (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR             (0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR            (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR             (0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR            (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR             (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_IF              (0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER             (0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR            (0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR             (0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR             (0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER             (0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR             (0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR            (0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR             (0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR            (0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR             (0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI            (0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR              (0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR              (0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TNPR            (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR            (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR             (0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR            (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR            (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR            (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR             (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR             (0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR             (0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR            (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_BRGR            (0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER             (0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR              (0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR             (0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI            (0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR            (0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR              (0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR            (0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR             (0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR             (0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR             (0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR             (0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF              (0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER             (0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_TNCR            (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR             (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR            (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR             (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR            (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR             (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR             (0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR            (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR            (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR            (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RHR             (0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR            (0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR            (0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR             (0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR             (0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR            (0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER             (0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR            (0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR              (0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR             (0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR            (0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR              (0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR             (0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR            (0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_IER             (0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR              (0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR              (0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR             (0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR             (0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR             (0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR            (0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR             (0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR            (0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR             (0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_PWMC_CH3_CUPDR      (0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved   (0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR      (0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR      (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR      (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR        (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_PWMC_CH2_Reserved   (0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR        (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR      (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR      (0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR      (0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR      (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_PWMC_CH1_Reserved   (0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR      (0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR      (0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR      (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR      (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR        (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_PWMC_CH0_Reserved   (0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR      (0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR      (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR        (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR      (0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR      (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_IDR            (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS            (0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER            (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR             (0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR            (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR             (0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR            (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR             (0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA            (0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_IMR             (0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR           (0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM             (0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR             (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR             (0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR             (0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR             (0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR             (0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP           (0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC            (0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE        (0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER             (0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR              (0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC              (0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB              (0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR             (0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR             (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER             (0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA              (0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR             (0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV              (0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR             (0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB              (0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR             (0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER             (0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR             (0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR              (0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR             (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA              (0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC              (0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR             (0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV              (0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR             (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR             (0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV              (0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA              (0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB              (0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR             (0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR             (0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC              (0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER             (0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR              (0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR             (0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR             (0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ========== 
+#define AT91C_CAN_MB0_MDL         (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM         (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR         (0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID         (0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR         (0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID        (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH         (0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR         (0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ========== 
+#define AT91C_CAN_MB1_MDL         (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID         (0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR         (0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR         (0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM         (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH         (0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR         (0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID        (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ========== 
+#define AT91C_CAN_MB2_MCR         (0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH         (0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID         (0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL         (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR         (0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM         (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID        (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR         (0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ========== 
+#define AT91C_CAN_MB3_MFID        (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM         (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID         (0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR         (0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR         (0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR         (0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL         (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH         (0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ========== 
+#define AT91C_CAN_MB4_MID         (0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR         (0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH         (0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID        (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR         (0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR         (0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL         (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM         (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ========== 
+#define AT91C_CAN_MB5_MSR         (0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR         (0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID        (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH         (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID         (0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR         (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL         (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM         (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ========== 
+#define AT91C_CAN_MB6_MFID        (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID         (0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM         (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR         (0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL         (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR         (0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH         (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR         (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ========== 
+#define AT91C_CAN_MB7_MCR         (0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH         (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID        (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL         (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID         (0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR         (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM         (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR         (0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ========== 
+#define AT91C_CAN_TCR             (0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR             (0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER             (0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR             (0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP         (0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR              (0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR             (0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR             (0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM             (0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR              (0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR              (0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR              (0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ========== 
+#define AT91C_EMAC_ISR            (0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H           (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L           (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE            (0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL           (0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE            (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL            (0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF            (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND           (0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR            (0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L           (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR            (0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L           (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR            (0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR            (0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE            (0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL           (0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID            (0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB            (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP           (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO          (0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR            (0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H           (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV            (0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE            (0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA            (0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP           (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF            (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR          (0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT            (0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF            (0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE           (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ            (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN            (0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO            (0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV            (0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR            (0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF            (0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR            (0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF            (0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR            (0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L           (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO            (0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER            (0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H           (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE            (0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H           (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE            (0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE            (0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTSR            (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR            (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR            (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR            (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR            (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR            (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR             (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR             (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR             (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR             (0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CDR2            (0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3            (0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0            (0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5            (0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR            (0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR              (0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4            (0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1            (0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR            (0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR             (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR              (0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7            (0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6            (0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER             (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER            (0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR            (0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR              (0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR             (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ========== 
+#define AT91C_AES_TPR             (0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR            (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR            (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR            (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR             (0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR             (0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR            (0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR            (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR             (0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR            (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ========== 
+#define AT91C_AES_IVxR            (0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR              (0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR              (0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR         (0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR         (0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR              (0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR             (0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR             (0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER             (0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR          (0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR             (0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ========== 
+#define AT91C_TDES_RNCR           (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR            (0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR            (0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR           (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR           (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR            (0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR           (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR            (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR           (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR           (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ========== 
+#define AT91C_TDES_KEY2WxR        (0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR        (0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR            (0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR             (0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR           (0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR        (0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR            (0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR             (0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR             (0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER            (0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR            (0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR        (0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR        (0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_PIO_PA0             (1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0            (AT91C_PIO_PA0) //  USART 0 Receive Data
+#define AT91C_PIO_PA1             (1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0            (AT91C_PIO_PA1) //  USART 0 Transmit Data
+#define AT91C_PIO_PA10            (1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD            (AT91C_PIO_PA10) //  TWI Two-wire Serial Data
+#define AT91C_PIO_PA11            (1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK           (AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12            (1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00         (AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13            (1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01         (AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1           (AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14            (1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02         (AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1           (AT91C_PIO_PA14) //  External Interrupt 1
+#define AT91C_PIO_PA15            (1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03         (AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2          (AT91C_PIO_PA15) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA16            (1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0          (AT91C_PIO_PA16) //  SPI 0 Master In Slave
+#define AT91C_PIO_PA17            (1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0          (AT91C_PIO_PA17) //  SPI 0 Master Out Slave
+#define AT91C_PIO_PA18            (1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0          (AT91C_PIO_PA18) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA19            (1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX          (AT91C_PIO_PA19) //  CAN Receive
+#define AT91C_PIO_PA2             (1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0            (AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PA2_NPCS11          (AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20            (1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX          (AT91C_PIO_PA20) //  CAN Transmit
+#define AT91C_PIO_PA21            (1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF             (AT91C_PIO_PA21) //  SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10         (AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22            (1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK             (AT91C_PIO_PA22) //  SSC Transmit Clock
+#define AT91C_PA22_SPCK1          (AT91C_PIO_PA22) //  SPI 1 Serial Clock
+#define AT91C_PIO_PA23            (1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD             (AT91C_PIO_PA23) //  SSC Transmit data
+#define AT91C_PA23_MOSI1          (AT91C_PIO_PA23) //  SPI 1 Master Out Slave
+#define AT91C_PIO_PA24            (1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD             (AT91C_PIO_PA24) //  SSC Receive Data
+#define AT91C_PA24_MISO1          (AT91C_PIO_PA24) //  SPI 1 Master In Slave
+#define AT91C_PIO_PA25            (1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK             (AT91C_PIO_PA25) //  SSC Receive Clock
+#define AT91C_PA25_NPCS11         (AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26            (1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF             (AT91C_PIO_PA26) //  SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12         (AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27            (1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD           (AT91C_PIO_PA27) //  DBGU Debug Receive Data
+#define AT91C_PA27_PCK3           (AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28            (1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD           (AT91C_PIO_PA28) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PA29            (1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ            (AT91C_PIO_PA29) //  AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13         (AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3             (1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0            (AT91C_PIO_PA3) //  USART 0 Ready To Send
+#define AT91C_PA3_NPCS12          (AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30            (1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0           (AT91C_PIO_PA30) //  External Interrupt 0
+#define AT91C_PA30_PCK2           (AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4             (1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0            (AT91C_PIO_PA4) //  USART 0 Clear To Send
+#define AT91C_PA4_NPCS13          (AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5             (1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1            (AT91C_PIO_PA5) //  USART 1 Receive Data
+#define AT91C_PIO_PA6             (1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1            (AT91C_PIO_PA6) //  USART 1 Transmit Data
+#define AT91C_PIO_PA7             (1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1            (AT91C_PIO_PA7) //  USART 1 Serial Clock
+#define AT91C_PA7_NPCS01          (AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8             (1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1            (AT91C_PIO_PA8) //  USART 1 Ready To Send
+#define AT91C_PA8_NPCS02          (AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9             (1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1            (AT91C_PIO_PA9) //  USART 1 Clear To Send
+#define AT91C_PA9_NPCS03          (AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0             (1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK    (AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0            (AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1             (1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN           (AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10            (1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2           (AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11         (AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11            (1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3           (AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12         (AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12            (1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER          (AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0          (AT91C_PIO_PB12) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PB13            (1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2           (AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01         (AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14            (1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3           (AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02         (AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15            (1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV          (AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16            (1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL           (AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13         (AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17            (1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK          (AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03         (AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18            (1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100          (AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG          (AT91C_PIO_PB18) //  ADC External Trigger
+#define AT91C_PIO_PB19            (1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0           (AT91C_PIO_PB19) //  PWM Channel 0
+#define AT91C_PB19_TCLK1          (AT91C_PIO_PB19) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB2             (1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0            (AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20            (1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1           (AT91C_PIO_PB20) //  PWM Channel 1
+#define AT91C_PB20_PCK0           (AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21            (1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2           (AT91C_PIO_PB21) //  PWM Channel 2
+#define AT91C_PB21_PCK1           (AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22            (1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3           (AT91C_PIO_PB22) //  PWM Channel 3
+#define AT91C_PB22_PCK2           (AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23            (1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0          (AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1           (AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24            (1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0          (AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1           (AT91C_PIO_PB24) //  USART 1 Data Set ready
+#define AT91C_PIO_PB25            (1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1          (AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1           (AT91C_PIO_PB25) //  USART 1 Data Terminal ready
+#define AT91C_PIO_PB26            (1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1          (AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1            (AT91C_PIO_PB26) //  USART 1 Ring Indicator
+#define AT91C_PIO_PB27            (1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2          (AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0           (AT91C_PIO_PB27) //  PWM Channel 0
+#define AT91C_PIO_PB28            (1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2          (AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1           (AT91C_PIO_PB28) //  PWM Channel 1
+#define AT91C_PIO_PB29            (1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1           (AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2           (AT91C_PIO_PB29) //  PWM Channel 2
+#define AT91C_PIO_PB3             (1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1            (AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30            (1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2           (AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3           (AT91C_PIO_PB30) //  PWM Channel 3
+#define AT91C_PIO_PB4             (1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV     (AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5             (1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0            (AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6             (1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1            (AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7             (1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER           (AT91C_PIO_PB7) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PB8             (1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC            (AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9             (1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO           (AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_ID_FIQ              ( 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS              ( 1) // System Peripheral
+#define AT91C_ID_PIOA             ( 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB             ( 3) // Parallel IO Controller B
+#define AT91C_ID_SPI0             ( 4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1             ( 5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0              ( 6) // USART 0
+#define AT91C_ID_US1              ( 7) // USART 1
+#define AT91C_ID_SSC              ( 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI              ( 9) // Two-Wire Interface
+#define AT91C_ID_PWMC             (10) // PWM Controller
+#define AT91C_ID_UDP              (11) // USB Device Port
+#define AT91C_ID_TC0              (12) // Timer Counter 0
+#define AT91C_ID_TC1              (13) // Timer Counter 1
+#define AT91C_ID_TC2              (14) // Timer Counter 2
+#define AT91C_ID_CAN              (15) // Control Area Network Controller
+#define AT91C_ID_EMAC             (16) // Ethernet MAC
+#define AT91C_ID_ADC              (17) // Analog-to-Digital Converter
+#define AT91C_ID_AES              (18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES             (19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved      (20) // Reserved
+#define AT91C_ID_21_Reserved      (21) // Reserved
+#define AT91C_ID_22_Reserved      (22) // Reserved
+#define AT91C_ID_23_Reserved      (23) // Reserved
+#define AT91C_ID_24_Reserved      (24) // Reserved
+#define AT91C_ID_25_Reserved      (25) // Reserved
+#define AT91C_ID_26_Reserved      (26) // Reserved
+#define AT91C_ID_27_Reserved      (27) // Reserved
+#define AT91C_ID_28_Reserved      (28) // Reserved
+#define AT91C_ID_29_Reserved      (29) // Reserved
+#define AT91C_ID_IRQ0             (30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1             (31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_BASE_SYS            (0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC            (0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU       (0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU           (0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA           (0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB           (0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR           (0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC            (0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC           (0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC           (0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC           (0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC           (0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG           (0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC             (0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1       (0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1           (0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0       (0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0           (0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1        (0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0        (0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0            (0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC        (0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC            (0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI            (0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3       (0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2       (0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1       (0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0       (0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC           (0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP            (0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0            (0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1            (0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2            (0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB            (0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0        (0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1        (0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2        (0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3        (0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4        (0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5        (0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6        (0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7        (0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN            (0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC           (0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC        (0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC            (0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES        (0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES            (0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES       (0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES           (0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
+// *****************************************************************************
+#define AT91C_ISRAM	              (0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	         (0x00008000) // Internal SRAM size in byte (32 Kbyte)
+#define AT91C_IFLASH	             (0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	        (0x00020000) // Internal ROM size in byte (128 Kbyte)
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
new file mode 100644
index 0000000..6b73f8a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
@@ -0,0 +1,2715 @@
+//  ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+//  ----------------------------------------------------------------------------
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  ----------------------------------------------------------------------------
+// File Name           : AT91SAM7X256.h
+// Object              : AT91SAM7X256 definitions
+// Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
+// 
+// CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
+// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
+// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
+// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
+// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
+// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
+// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
+// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
+// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
+// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
+// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
+// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
+// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
+// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+//  ----------------------------------------------------------------------------
+
+#ifndef AT91SAM7X256_H
+#define AT91SAM7X256_H
+
+typedef volatile unsigned int AT91_REG;// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+typedef struct _AT91S_SYS {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+	AT91_REG	 Reserved2[45]; 	// 
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved3[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved4[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+	AT91_REG	 Reserved5[54]; 	// 
+	AT91_REG	 PIOA_PER; 	// PIO Enable Register
+	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOA_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved6[1]; 	// 
+	AT91_REG	 PIOA_OER; 	// Output Enable Register
+	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOA_OSR; 	// Output Status Register
+	AT91_REG	 Reserved7[1]; 	// 
+	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved8[1]; 	// 
+	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved9[1]; 	// 
+	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved10[1]; 	// 
+	AT91_REG	 PIOA_ASR; 	// Select A Register
+	AT91_REG	 PIOA_BSR; 	// Select B Register
+	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved11[9]; 	// 
+	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved12[85]; 	// 
+	AT91_REG	 PIOB_PER; 	// PIO Enable Register
+	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
+	AT91_REG	 PIOB_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved13[1]; 	// 
+	AT91_REG	 PIOB_OER; 	// Output Enable Register
+	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIOB_OSR; 	// Output Status Register
+	AT91_REG	 Reserved14[1]; 	// 
+	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved15[1]; 	// 
+	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
+	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved16[1]; 	// 
+	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved17[1]; 	// 
+	AT91_REG	 PIOB_ASR; 	// Select A Register
+	AT91_REG	 PIOB_BSR; 	// Select B Register
+	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved18[9]; 	// 
+	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
+	AT91_REG	 Reserved19[341]; 	// 
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved20[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved21[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved22[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved23[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved24[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved25[36]; 	// 
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+	AT91_REG	 Reserved26[5]; 	// 
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+	AT91_REG	 Reserved27[5]; 	// 
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_SYS, *AT91PS_SYS;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+typedef struct _AT91S_AIC {
+	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
+	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
+	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
+	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
+	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
+	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
+	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
+	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
+	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
+	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
+	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
+	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
+	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
+	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
+	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
+} AT91S_AIC, *AT91PS_AIC;
+
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
+#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+typedef struct _AT91S_PDC {
+	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
+	AT91_REG	 PDC_RCR; 	// Receive Counter Register
+	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
+	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
+} AT91S_PDC, *AT91PS_PDC;
+
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+typedef struct _AT91S_DBGU {
+	AT91_REG	 DBGU_CR; 	// Control Register
+	AT91_REG	 DBGU_MR; 	// Mode Register
+	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
+	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
+	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
+	AT91_REG	 DBGU_CSR; 	// Channel Status Register
+	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
+	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
+	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 Reserved0[7]; 	// 
+	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
+	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
+	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
+	AT91_REG	 Reserved1[45]; 	// 
+	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
+	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
+	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
+	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
+	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
+} AT91S_DBGU, *AT91PS_DBGU;
+
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+typedef struct _AT91S_PIO {
+	AT91_REG	 PIO_PER; 	// PIO Enable Register
+	AT91_REG	 PIO_PDR; 	// PIO Disable Register
+	AT91_REG	 PIO_PSR; 	// PIO Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PIO_OER; 	// Output Enable Register
+	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
+	AT91_REG	 PIO_OSR; 	// Output Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
+	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
+	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PIO_SODR; 	// Set Output Data Register
+	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
+	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
+	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
+	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
+	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
+	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
+	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
+	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
+	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
+	AT91_REG	 Reserved3[1]; 	// 
+	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
+	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
+	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
+	AT91_REG	 Reserved4[1]; 	// 
+	AT91_REG	 PIO_ASR; 	// Select A Register
+	AT91_REG	 PIO_BSR; 	// Select B Register
+	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
+	AT91_REG	 Reserved5[9]; 	// 
+	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
+	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
+	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
+} AT91S_PIO, *AT91PS_PIO;
+
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+typedef struct _AT91S_CKGR {
+	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
+	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 CKGR_PLLR; 	// PLL Register
+} AT91S_CKGR, *AT91PS_CKGR;
+
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+typedef struct _AT91S_PMC {
+	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
+	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
+	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
+	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
+	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
+	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 PMC_PLLR; 	// PLL Register
+	AT91_REG	 PMC_MCKR; 	// Master Clock Register
+	AT91_REG	 Reserved3[3]; 	// 
+	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
+	AT91_REG	 Reserved4[4]; 	// 
+	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
+	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 PMC_SR; 	// Status Register
+	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
+} AT91S_PMC, *AT91PS_PMC;
+
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RSTC {
+	AT91_REG	 RSTC_RCR; 	// Reset Control Register
+	AT91_REG	 RSTC_RSR; 	// Reset Status Register
+	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
+} AT91S_RSTC, *AT91PS_RSTC;
+
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_RTTC {
+	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
+	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
+	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
+	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
+} AT91S_RTTC, *AT91PS_RTTC;
+
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PITC {
+	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
+	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
+	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
+	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
+} AT91S_PITC, *AT91PS_PITC;
+
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_WDTC {
+	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
+	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
+	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
+} AT91S_WDTC, *AT91PS_WDTC;
+
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_VREG {
+	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
+} AT91S_VREG, *AT91PS_VREG;
+
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_MC {
+	AT91_REG	 MC_RCR; 	// MC Remap Control Register
+	AT91_REG	 MC_ASR; 	// MC Abort Status Register
+	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
+	AT91_REG	 Reserved0[21]; 	// 
+	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
+	AT91_REG	 MC_FCR; 	// MC Flash Command Register
+	AT91_REG	 MC_FSR; 	// MC Flash Status Register
+} AT91S_MC, *AT91PS_MC;
+
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+typedef struct _AT91S_SPI {
+	AT91_REG	 SPI_CR; 	// Control Register
+	AT91_REG	 SPI_MR; 	// Mode Register
+	AT91_REG	 SPI_RDR; 	// Receive Data Register
+	AT91_REG	 SPI_TDR; 	// Transmit Data Register
+	AT91_REG	 SPI_SR; 	// Status Register
+	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
+	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
+	AT91_REG	 Reserved1[48]; 	// 
+	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
+	AT91_REG	 SPI_RCR; 	// Receive Counter Register
+	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
+	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
+} AT91S_SPI, *AT91PS_SPI;
+
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+typedef struct _AT91S_USART {
+	AT91_REG	 US_CR; 	// Control Register
+	AT91_REG	 US_MR; 	// Mode Register
+	AT91_REG	 US_IER; 	// Interrupt Enable Register
+	AT91_REG	 US_IDR; 	// Interrupt Disable Register
+	AT91_REG	 US_IMR; 	// Interrupt Mask Register
+	AT91_REG	 US_CSR; 	// Channel Status Register
+	AT91_REG	 US_RHR; 	// Receiver Holding Register
+	AT91_REG	 US_THR; 	// Transmitter Holding Register
+	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
+	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
+	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
+	AT91_REG	 Reserved0[5]; 	// 
+	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
+	AT91_REG	 US_NER; 	// Nb Errors Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 US_IF; 	// IRDA_FILTER Register
+	AT91_REG	 Reserved2[44]; 	// 
+	AT91_REG	 US_RPR; 	// Receive Pointer Register
+	AT91_REG	 US_RCR; 	// Receive Counter Register
+	AT91_REG	 US_TPR; 	// Transmit Pointer Register
+	AT91_REG	 US_TCR; 	// Transmit Counter Register
+	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
+} AT91S_USART, *AT91PS_USART;
+
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_SSC {
+	AT91_REG	 SSC_CR; 	// Control Register
+	AT91_REG	 SSC_CMR; 	// Clock Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
+	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
+	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
+	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
+	AT91_REG	 SSC_RHR; 	// Receive Holding Register
+	AT91_REG	 SSC_THR; 	// Transmit Holding Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
+	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 SSC_SR; 	// Status Register
+	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
+	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 Reserved3[44]; 	// 
+	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
+	AT91_REG	 SSC_RCR; 	// Receive Counter Register
+	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
+	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
+} AT91S_SSC, *AT91PS_SSC;
+
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+typedef struct _AT91S_TWI {
+	AT91_REG	 TWI_CR; 	// Control Register
+	AT91_REG	 TWI_MMR; 	// Master Mode Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 TWI_IADR; 	// Internal Address Register
+	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
+	AT91_REG	 Reserved1[3]; 	// 
+	AT91_REG	 TWI_SR; 	// Status Register
+	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
+	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TWI_RHR; 	// Receive Holding Register
+	AT91_REG	 TWI_THR; 	// Transmit Holding Register
+} AT91S_TWI, *AT91PS_TWI;
+
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC_CH {
+	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
+	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
+	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
+	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
+	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
+	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
+} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
+
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+typedef struct _AT91S_PWMC {
+	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
+	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
+	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
+	AT91_REG	 PWMC_SR; 	// PWMC Status Register
+	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
+	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
+	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
+	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
+	AT91_REG	 Reserved0[55]; 	// 
+	AT91_REG	 PWMC_VR; 	// PWMC Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
+} AT91S_PWMC, *AT91PS_PWMC;
+
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+typedef struct _AT91S_UDP {
+	AT91_REG	 UDP_NUM; 	// Frame Number Register
+	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
+	AT91_REG	 UDP_FADDR; 	// Function Address Register
+	AT91_REG	 Reserved0[1]; 	// 
+	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
+	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
+	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
+	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
+	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
+	AT91_REG	 Reserved1[1]; 	// 
+	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
+	AT91_REG	 Reserved2[1]; 	// 
+	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
+	AT91_REG	 Reserved4[3]; 	// 
+	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
+} AT91S_UDP, *AT91PS_UDP;
+
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+typedef struct _AT91S_TC {
+	AT91_REG	 TC_CCR; 	// Channel Control Register
+	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TC_CV; 	// Counter Value
+	AT91_REG	 TC_RA; 	// Register A
+	AT91_REG	 TC_RB; 	// Register B
+	AT91_REG	 TC_RC; 	// Register C
+	AT91_REG	 TC_SR; 	// Status Register
+	AT91_REG	 TC_IER; 	// Interrupt Enable Register
+	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
+} AT91S_TC, *AT91PS_TC;
+
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+typedef struct _AT91S_TCB {
+	AT91S_TC	 TCB_TC0; 	// TC Channel 0
+	AT91_REG	 Reserved0[4]; 	// 
+	AT91S_TC	 TCB_TC1; 	// TC Channel 1
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91S_TC	 TCB_TC2; 	// TC Channel 2
+	AT91_REG	 Reserved2[4]; 	// 
+	AT91_REG	 TCB_BCR; 	// TC Block Control Register
+	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
+} AT91S_TCB, *AT91PS_TCB;
+
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN_MB {
+	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
+	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
+	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
+	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
+	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
+	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
+	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
+	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
+} AT91S_CAN_MB, *AT91PS_CAN_MB;
+
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// *****************************************************************************
+typedef struct _AT91S_CAN {
+	AT91_REG	 CAN_MR; 	// Mode Register
+	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
+	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
+	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
+	AT91_REG	 CAN_SR; 	// Status Register
+	AT91_REG	 CAN_BR; 	// Baudrate Register
+	AT91_REG	 CAN_TIM; 	// Timer Register
+	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
+	AT91_REG	 CAN_ECR; 	// Error Counter Register
+	AT91_REG	 CAN_TCR; 	// Transfer Command Register
+	AT91_REG	 CAN_ACR; 	// Abort Command Register
+	AT91_REG	 Reserved0[52]; 	// 
+	AT91_REG	 CAN_VR; 	// Version Register
+	AT91_REG	 Reserved1[64]; 	// 
+	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
+	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
+	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
+	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
+	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
+	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
+	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
+	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
+	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
+	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
+	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
+	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
+	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
+	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
+	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
+	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
+} AT91S_CAN, *AT91PS_CAN;
+
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+typedef struct _AT91S_EMAC {
+	AT91_REG	 EMAC_NCR; 	// Network Control Register
+	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
+	AT91_REG	 EMAC_NSR; 	// Network Status Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
+	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
+	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
+	AT91_REG	 EMAC_RSR; 	// Receive Status Register
+	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
+	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
+	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
+	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
+	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
+	AT91_REG	 EMAC_PTR; 	// Pause Time Register
+	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
+	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
+	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
+	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
+	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
+	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
+	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
+	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
+	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
+	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
+	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
+	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
+	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
+	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
+	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
+	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
+	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
+	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
+	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
+	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
+	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
+	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
+	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
+	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
+	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
+	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
+	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
+	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
+	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
+	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
+	AT91_REG	 Reserved1[13]; 	// 
+	AT91_REG	 EMAC_REV; 	// Revision Register
+} AT91S_EMAC, *AT91PS_EMAC;
+
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+typedef struct _AT91S_ADC {
+	AT91_REG	 ADC_CR; 	// ADC Control Register
+	AT91_REG	 ADC_MR; 	// ADC Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
+	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
+	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
+	AT91_REG	 ADC_SR; 	// ADC Status Register
+	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
+	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
+	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
+	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
+	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
+	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
+	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
+	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
+	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
+	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
+	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
+	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
+	AT91_REG	 Reserved1[44]; 	// 
+	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
+	AT91_REG	 ADC_RCR; 	// Receive Counter Register
+	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
+	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
+	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
+} AT91S_ADC, *AT91PS_ADC;
+
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_AES {
+	AT91_REG	 AES_CR; 	// Control Register
+	AT91_REG	 AES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 AES_IER; 	// Interrupt Enable Register
+	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 AES_ISR; 	// Interrupt Status Register
+	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
+	AT91_REG	 Reserved1[4]; 	// 
+	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
+	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
+	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved2[35]; 	// 
+	AT91_REG	 AES_VR; 	// AES Version Register
+	AT91_REG	 AES_RPR; 	// Receive Pointer Register
+	AT91_REG	 AES_RCR; 	// Receive Counter Register
+	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 AES_TCR; 	// Transmit Counter Register
+	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
+} AT91S_AES, *AT91PS_AES;
+
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
+#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
+#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
+#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
+#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
+#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
+#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
+#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
+#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
+#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
+#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
+#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
+#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// *****************************************************************************
+typedef struct _AT91S_TDES {
+	AT91_REG	 TDES_CR; 	// Control Register
+	AT91_REG	 TDES_MR; 	// Mode Register
+	AT91_REG	 Reserved0[2]; 	// 
+	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
+	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
+	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
+	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
+	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
+	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
+	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
+	AT91_REG	 Reserved1[2]; 	// 
+	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
+	AT91_REG	 Reserved2[2]; 	// 
+	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
+	AT91_REG	 Reserved3[2]; 	// 
+	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
+	AT91_REG	 Reserved4[37]; 	// 
+	AT91_REG	 TDES_VR; 	// TDES Version Register
+	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
+	AT91_REG	 TDES_RCR; 	// Receive Counter Register
+	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
+	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
+	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
+	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
+	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
+	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
+	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
+	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
+} AT91S_TDES, *AT91PS_TDES;
+
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
+#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
+#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
+#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
+#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
+#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
+#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
+#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ========== 
+#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ========== 
+#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ========== 
+#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ========== 
+#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ========== 
+#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ========== 
+#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ========== 
+#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ========== 
+#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ========== 
+#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ========== 
+#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ========== 
+#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ========== 
+#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ========== 
+#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ========== 
+#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ========== 
+#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
+#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
+#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
+#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
+#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
+#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
+#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
+#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
+#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
+#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
+#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
+#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
+#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
+#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
+#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
+#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
+#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
+#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
+#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
+#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
+#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
+#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
+#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
+#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
+#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
+#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
+#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
+#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
+#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
+#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
+#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
+#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
+#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
+#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
+#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
+#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
+#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
+#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
+#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
+#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
+#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
+#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
+#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
+#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
+#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
+#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
+#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
+#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
+#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
+#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
+#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
+#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
+#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
+#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
+#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
+#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
+#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
+#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
+#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
+#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
+#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
+#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
+#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
+
+#endif
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
new file mode 100644
index 0000000..5b8dfe8
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
@@ -0,0 +1,2446 @@
+//  ----------------------------------------------------------------------------
+//          ATMEL Microcontroller Software Support  -  ROUSSET  -
+//  ----------------------------------------------------------------------------
+//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//  ----------------------------------------------------------------------------
+// File Name           : AT91SAM7X256.h
+// Object              : AT91SAM7X256 definitions
+// Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
+// 
+// CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
+// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
+// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
+// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
+// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
+// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
+// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
+// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
+// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
+// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
+// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
+// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
+// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
+// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
+// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
+// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
+// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
+// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
+// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
+// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
+// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
+// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
+// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
+// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
+// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
+//  ----------------------------------------------------------------------------
+
+// Hardware register definition
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR System Peripherals
+// *****************************************************************************
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
+// *****************************************************************************
+// *** Register offset in AT91S_AIC structure ***
+#define AIC_SMR         ( 0) // Source Mode Register
+#define AIC_SVR         (128) // Source Vector Register
+#define AIC_IVR         (256) // IRQ Vector Register
+#define AIC_FVR         (260) // FIQ Vector Register
+#define AIC_ISR         (264) // Interrupt Status Register
+#define AIC_IPR         (268) // Interrupt Pending Register
+#define AIC_IMR         (272) // Interrupt Mask Register
+#define AIC_CISR        (276) // Core Interrupt Status Register
+#define AIC_IECR        (288) // Interrupt Enable Command Register
+#define AIC_IDCR        (292) // Interrupt Disable Command Register
+#define AIC_ICCR        (296) // Interrupt Clear Command Register
+#define AIC_ISCR        (300) // Interrupt Set Command Register
+#define AIC_EOICR       (304) // End of Interrupt Command Register
+#define AIC_SPU         (308) // Spurious Vector Register
+#define AIC_DCR         (312) // Debug Control Register (Protect)
+#define AIC_FFER        (320) // Fast Forcing Enable Register
+#define AIC_FFDR        (324) // Fast Forcing Disable Register
+#define AIC_FFSR        (328) // Fast Forcing Status Register
+// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
+#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level
+#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
+#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
+#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type
+#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
+#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
+#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
+#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
+// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
+#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status
+#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status
+// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
+#define AT91C_AIC_DCR_PROT        (0x1 <<  0) // (AIC) Protection Mode
+#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) // (AIC) General Mask
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
+// *****************************************************************************
+// *** Register offset in AT91S_PDC structure ***
+#define PDC_RPR         ( 0) // Receive Pointer Register
+#define PDC_RCR         ( 4) // Receive Counter Register
+#define PDC_TPR         ( 8) // Transmit Pointer Register
+#define PDC_TCR         (12) // Transmit Counter Register
+#define PDC_RNPR        (16) // Receive Next Pointer Register
+#define PDC_RNCR        (20) // Receive Next Counter Register
+#define PDC_TNPR        (24) // Transmit Next Pointer Register
+#define PDC_TNCR        (28) // Transmit Next Counter Register
+#define PDC_PTCR        (32) // PDC Transfer Control Register
+#define PDC_PTSR        (36) // PDC Transfer Status Register
+// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
+#define AT91C_PDC_RXTEN           (0x1 <<  0) // (PDC) Receiver Transfer Enable
+#define AT91C_PDC_RXTDIS          (0x1 <<  1) // (PDC) Receiver Transfer Disable
+#define AT91C_PDC_TXTEN           (0x1 <<  8) // (PDC) Transmitter Transfer Enable
+#define AT91C_PDC_TXTDIS          (0x1 <<  9) // (PDC) Transmitter Transfer Disable
+// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Debug Unit
+// *****************************************************************************
+// *** Register offset in AT91S_DBGU structure ***
+#define DBGU_CR         ( 0) // Control Register
+#define DBGU_MR         ( 4) // Mode Register
+#define DBGU_IER        ( 8) // Interrupt Enable Register
+#define DBGU_IDR        (12) // Interrupt Disable Register
+#define DBGU_IMR        (16) // Interrupt Mask Register
+#define DBGU_CSR        (20) // Channel Status Register
+#define DBGU_RHR        (24) // Receiver Holding Register
+#define DBGU_THR        (28) // Transmitter Holding Register
+#define DBGU_BRGR       (32) // Baud Rate Generator Register
+#define DBGU_CIDR       (64) // Chip ID Register
+#define DBGU_EXID       (68) // Chip ID Extension Register
+#define DBGU_FNTR       (72) // Force NTRST Register
+#define DBGU_RPR        (256) // Receive Pointer Register
+#define DBGU_RCR        (260) // Receive Counter Register
+#define DBGU_TPR        (264) // Transmit Pointer Register
+#define DBGU_TCR        (268) // Transmit Counter Register
+#define DBGU_RNPR       (272) // Receive Next Pointer Register
+#define DBGU_RNCR       (276) // Receive Next Counter Register
+#define DBGU_TNPR       (280) // Transmit Next Pointer Register
+#define DBGU_TNCR       (284) // Transmit Next Counter Register
+#define DBGU_PTCR       (288) // PDC Transfer Control Register
+#define DBGU_PTSR       (292) // PDC Transfer Status Register
+// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_RSTRX            (0x1 <<  2) // (DBGU) Reset Receiver
+#define AT91C_US_RSTTX            (0x1 <<  3) // (DBGU) Reset Transmitter
+#define AT91C_US_RXEN             (0x1 <<  4) // (DBGU) Receiver Enable
+#define AT91C_US_RXDIS            (0x1 <<  5) // (DBGU) Receiver Disable
+#define AT91C_US_TXEN             (0x1 <<  6) // (DBGU) Transmitter Enable
+#define AT91C_US_TXDIS            (0x1 <<  7) // (DBGU) Transmitter Disable
+#define AT91C_US_RSTSTA           (0x1 <<  8) // (DBGU) Reset Status Bits
+// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_PAR              (0x7 <<  9) // (DBGU) Parity type
+#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
+#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
+#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
+#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
+#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
+#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
+#define AT91C_US_CHMODE           (0x3 << 14) // (DBGU) Channel Mode
+#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
+#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
+#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
+#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
+// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXRDY            (0x1 <<  0) // (DBGU) RXRDY Interrupt
+#define AT91C_US_TXRDY            (0x1 <<  1) // (DBGU) TXRDY Interrupt
+#define AT91C_US_ENDRX            (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
+#define AT91C_US_ENDTX            (0x1 <<  4) // (DBGU) End of Transmit Interrupt
+#define AT91C_US_OVRE             (0x1 <<  5) // (DBGU) Overrun Interrupt
+#define AT91C_US_FRAME            (0x1 <<  6) // (DBGU) Framing Error Interrupt
+#define AT91C_US_PARE             (0x1 <<  7) // (DBGU) Parity Error Interrupt
+#define AT91C_US_TXEMPTY          (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
+#define AT91C_US_TXBUFE           (0x1 << 11) // (DBGU) TXBUFE Interrupt
+#define AT91C_US_RXBUFF           (0x1 << 12) // (DBGU) RXBUFF Interrupt
+#define AT91C_US_COMM_TX          (0x1 << 30) // (DBGU) COMM_TX Interrupt
+#define AT91C_US_COMM_RX          (0x1 << 31) // (DBGU) COMM_RX Interrupt
+// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
+// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
+#define AT91C_US_FORCE_NTRST      (0x1 <<  0) // (DBGU) Force NTRST in JTAG
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PIO structure ***
+#define PIO_PER         ( 0) // PIO Enable Register
+#define PIO_PDR         ( 4) // PIO Disable Register
+#define PIO_PSR         ( 8) // PIO Status Register
+#define PIO_OER         (16) // Output Enable Register
+#define PIO_ODR         (20) // Output Disable Registerr
+#define PIO_OSR         (24) // Output Status Register
+#define PIO_IFER        (32) // Input Filter Enable Register
+#define PIO_IFDR        (36) // Input Filter Disable Register
+#define PIO_IFSR        (40) // Input Filter Status Register
+#define PIO_SODR        (48) // Set Output Data Register
+#define PIO_CODR        (52) // Clear Output Data Register
+#define PIO_ODSR        (56) // Output Data Status Register
+#define PIO_PDSR        (60) // Pin Data Status Register
+#define PIO_IER         (64) // Interrupt Enable Register
+#define PIO_IDR         (68) // Interrupt Disable Register
+#define PIO_IMR         (72) // Interrupt Mask Register
+#define PIO_ISR         (76) // Interrupt Status Register
+#define PIO_MDER        (80) // Multi-driver Enable Register
+#define PIO_MDDR        (84) // Multi-driver Disable Register
+#define PIO_MDSR        (88) // Multi-driver Status Register
+#define PIO_PPUDR       (96) // Pull-up Disable Register
+#define PIO_PPUER       (100) // Pull-up Enable Register
+#define PIO_PPUSR       (104) // Pull-up Status Register
+#define PIO_ASR         (112) // Select A Register
+#define PIO_BSR         (116) // Select B Register
+#define PIO_ABSR        (120) // AB Select Status Register
+#define PIO_OWER        (160) // Output Write Enable Register
+#define PIO_OWDR        (164) // Output Write Disable Register
+#define PIO_OWSR        (168) // Output Write Status Register
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
+// *****************************************************************************
+// *** Register offset in AT91S_CKGR structure ***
+#define CKGR_MOR        ( 0) // Main Oscillator Register
+#define CKGR_MCFR       ( 4) // Main Clock  Frequency Register
+#define CKGR_PLLR       (12) // PLL Register
+// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
+#define AT91C_CKGR_MOSCEN         (0x1 <<  0) // (CKGR) Main Oscillator Enable
+#define AT91C_CKGR_OSCBYPASS      (0x1 <<  1) // (CKGR) Main Oscillator Bypass
+#define AT91C_CKGR_OSCOUNT        (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
+// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
+#define AT91C_CKGR_MAINF          (0xFFFF <<  0) // (CKGR) Main Clock Frequency
+#define AT91C_CKGR_MAINRDY        (0x1 << 16) // (CKGR) Main Clock Ready
+// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
+#define AT91C_CKGR_DIV            (0xFF <<  0) // (CKGR) Divider Selected
+#define 	AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
+#define 	AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
+#define AT91C_CKGR_PLLCOUNT       (0x3F <<  8) // (CKGR) PLL Counter
+#define AT91C_CKGR_OUT            (0x3 << 14) // (CKGR) PLL Output Frequency Range
+#define 	AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
+#define 	AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
+#define AT91C_CKGR_MUL            (0x7FF << 16) // (CKGR) PLL Multiplier
+#define AT91C_CKGR_USBDIV         (0x3 << 28) // (CKGR) Divider for USB Clocks
+#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
+#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
+#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Power Management Controler
+// *****************************************************************************
+// *** Register offset in AT91S_PMC structure ***
+#define PMC_SCER        ( 0) // System Clock Enable Register
+#define PMC_SCDR        ( 4) // System Clock Disable Register
+#define PMC_SCSR        ( 8) // System Clock Status Register
+#define PMC_PCER        (16) // Peripheral Clock Enable Register
+#define PMC_PCDR        (20) // Peripheral Clock Disable Register
+#define PMC_PCSR        (24) // Peripheral Clock Status Register
+#define PMC_MOR         (32) // Main Oscillator Register
+#define PMC_MCFR        (36) // Main Clock  Frequency Register
+#define PMC_PLLR        (44) // PLL Register
+#define PMC_MCKR        (48) // Master Clock Register
+#define PMC_PCKR        (64) // Programmable Clock Register
+#define PMC_IER         (96) // Interrupt Enable Register
+#define PMC_IDR         (100) // Interrupt Disable Register
+#define PMC_SR          (104) // Status Register
+#define PMC_IMR         (108) // Interrupt Mask Register
+// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
+#define AT91C_PMC_PCK             (0x1 <<  0) // (PMC) Processor Clock
+#define AT91C_PMC_UDP             (0x1 <<  7) // (PMC) USB Device Port Clock
+#define AT91C_PMC_PCK0            (0x1 <<  8) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK1            (0x1 <<  9) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK2            (0x1 << 10) // (PMC) Programmable Clock Output
+#define AT91C_PMC_PCK3            (0x1 << 11) // (PMC) Programmable Clock Output
+// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
+// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
+// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
+// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
+// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
+// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
+#define AT91C_PMC_CSS             (0x3 <<  0) // (PMC) Programmable Clock Selection
+#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
+#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
+#define 	AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
+#define AT91C_PMC_PRES            (0x7 <<  2) // (PMC) Programmable Clock Prescaler
+#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
+#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
+#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
+#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
+#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
+#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
+#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
+// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
+// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
+#define AT91C_PMC_MOSCS           (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
+#define AT91C_PMC_LOCK            (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
+#define AT91C_PMC_MCKRDY          (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK0RDY         (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK1RDY         (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK2RDY         (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
+#define AT91C_PMC_PCK3RDY         (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
+// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
+// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
+// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RSTC structure ***
+#define RSTC_RCR        ( 0) // Reset Control Register
+#define RSTC_RSR        ( 4) // Reset Status Register
+#define RSTC_RMR        ( 8) // Reset Mode Register
+// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
+#define AT91C_RSTC_PROCRST        (0x1 <<  0) // (RSTC) Processor Reset
+#define AT91C_RSTC_PERRST         (0x1 <<  2) // (RSTC) Peripheral Reset
+#define AT91C_RSTC_EXTRST         (0x1 <<  3) // (RSTC) External Reset
+#define AT91C_RSTC_KEY            (0xFF << 24) // (RSTC) Password
+// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
+#define AT91C_RSTC_URSTS          (0x1 <<  0) // (RSTC) User Reset Status
+#define AT91C_RSTC_BODSTS         (0x1 <<  1) // (RSTC) Brownout Detection Status
+#define AT91C_RSTC_RSTTYP         (0x7 <<  8) // (RSTC) Reset Type
+#define 	AT91C_RSTC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
+#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
+#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
+#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
+#define 	AT91C_RSTC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brownout Reset occured.
+#define AT91C_RSTC_NRSTL          (0x1 << 16) // (RSTC) NRST pin level
+#define AT91C_RSTC_SRCMP          (0x1 << 17) // (RSTC) Software Reset Command in Progress.
+// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
+#define AT91C_RSTC_URSTEN         (0x1 <<  0) // (RSTC) User Reset Enable
+#define AT91C_RSTC_URSTIEN        (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
+#define AT91C_RSTC_ERSTL          (0xF <<  8) // (RSTC) User Reset Enable
+#define AT91C_RSTC_BODIEN         (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_RTTC structure ***
+#define RTTC_RTMR       ( 0) // Real-time Mode Register
+#define RTTC_RTAR       ( 4) // Real-time Alarm Register
+#define RTTC_RTVR       ( 8) // Real-time Value Register
+#define RTTC_RTSR       (12) // Real-time Status Register
+// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
+#define AT91C_RTTC_RTPRES         (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
+#define AT91C_RTTC_ALMIEN         (0x1 << 16) // (RTTC) Alarm Interrupt Enable
+#define AT91C_RTTC_RTTINCIEN      (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
+#define AT91C_RTTC_RTTRST         (0x1 << 18) // (RTTC) Real Time Timer Restart
+// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
+#define AT91C_RTTC_ALMV           (0x0 <<  0) // (RTTC) Alarm Value
+// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
+#define AT91C_RTTC_CRTV           (0x0 <<  0) // (RTTC) Current Real-time Value
+// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
+#define AT91C_RTTC_ALMS           (0x1 <<  0) // (RTTC) Real-time Alarm Status
+#define AT91C_RTTC_RTTINC         (0x1 <<  1) // (RTTC) Real-time Timer Increment
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PITC structure ***
+#define PITC_PIMR       ( 0) // Period Interval Mode Register
+#define PITC_PISR       ( 4) // Period Interval Status Register
+#define PITC_PIVR       ( 8) // Period Interval Value Register
+#define PITC_PIIR       (12) // Period Interval Image Register
+// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
+#define AT91C_PITC_PIV            (0xFFFFF <<  0) // (PITC) Periodic Interval Value
+#define AT91C_PITC_PITEN          (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
+#define AT91C_PITC_PITIEN         (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
+// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
+#define AT91C_PITC_PITS           (0x1 <<  0) // (PITC) Periodic Interval Timer Status
+// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
+#define AT91C_PITC_CPIV           (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
+#define AT91C_PITC_PICNT          (0xFFF << 20) // (PITC) Periodic Interval Counter
+// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_WDTC structure ***
+#define WDTC_WDCR       ( 0) // Watchdog Control Register
+#define WDTC_WDMR       ( 4) // Watchdog Mode Register
+#define WDTC_WDSR       ( 8) // Watchdog Status Register
+// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
+#define AT91C_WDTC_WDRSTT         (0x1 <<  0) // (WDTC) Watchdog Restart
+#define AT91C_WDTC_KEY            (0xFF << 24) // (WDTC) Watchdog KEY Password
+// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
+#define AT91C_WDTC_WDV            (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDFIEN         (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
+#define AT91C_WDTC_WDRSTEN        (0x1 << 13) // (WDTC) Watchdog Reset Enable
+#define AT91C_WDTC_WDRPROC        (0x1 << 14) // (WDTC) Watchdog Timer Restart
+#define AT91C_WDTC_WDDIS          (0x1 << 15) // (WDTC) Watchdog Disable
+#define AT91C_WDTC_WDD            (0xFFF << 16) // (WDTC) Watchdog Delta Value
+#define AT91C_WDTC_WDDBGHLT       (0x1 << 28) // (WDTC) Watchdog Debug Halt
+#define AT91C_WDTC_WDIDLEHLT      (0x1 << 29) // (WDTC) Watchdog Idle Halt
+// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
+#define AT91C_WDTC_WDUNF          (0x1 <<  0) // (WDTC) Watchdog Underflow
+#define AT91C_WDTC_WDERR          (0x1 <<  1) // (WDTC) Watchdog Error
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_VREG structure ***
+#define VREG_MR         ( 0) // Voltage Regulator Mode Register
+// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
+#define AT91C_VREG_PSTDBY         (0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_MC structure ***
+#define MC_RCR          ( 0) // MC Remap Control Register
+#define MC_ASR          ( 4) // MC Abort Status Register
+#define MC_AASR         ( 8) // MC Abort Address Status Register
+#define MC_FMR          (96) // MC Flash Mode Register
+#define MC_FCR          (100) // MC Flash Command Register
+#define MC_FSR          (104) // MC Flash Status Register
+// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
+#define AT91C_MC_RCB              (0x1 <<  0) // (MC) Remap Command Bit
+// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
+#define AT91C_MC_UNDADD           (0x1 <<  0) // (MC) Undefined Addess Abort Status
+#define AT91C_MC_MISADD           (0x1 <<  1) // (MC) Misaligned Addess Abort Status
+#define AT91C_MC_ABTSZ            (0x3 <<  8) // (MC) Abort Size Status
+#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
+#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
+#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
+#define AT91C_MC_ABTTYP           (0x3 << 10) // (MC) Abort Type Status
+#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
+#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
+#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
+#define AT91C_MC_MST0             (0x1 << 16) // (MC) Master 0 Abort Source
+#define AT91C_MC_MST1             (0x1 << 17) // (MC) Master 1 Abort Source
+#define AT91C_MC_SVMST0           (0x1 << 24) // (MC) Saved Master 0 Abort Source
+#define AT91C_MC_SVMST1           (0x1 << 25) // (MC) Saved Master 1 Abort Source
+// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
+#define AT91C_MC_FRDY             (0x1 <<  0) // (MC) Flash Ready
+#define AT91C_MC_LOCKE            (0x1 <<  2) // (MC) Lock Error
+#define AT91C_MC_PROGE            (0x1 <<  3) // (MC) Programming Error
+#define AT91C_MC_NEBP             (0x1 <<  7) // (MC) No Erase Before Programming
+#define AT91C_MC_FWS              (0x3 <<  8) // (MC) Flash Wait State
+#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
+#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
+#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
+#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
+#define AT91C_MC_FMCN             (0xFF << 16) // (MC) Flash Microsecond Cycle Number
+// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
+#define AT91C_MC_FCMD             (0xF <<  0) // (MC) Flash Command
+#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
+#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
+#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
+#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
+#define 	AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
+#define 	AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
+#define AT91C_MC_PAGEN            (0x3FF <<  8) // (MC) Page Number
+#define AT91C_MC_KEY              (0xFF << 24) // (MC) Writing Protect Key
+// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
+#define AT91C_MC_SECURITY         (0x1 <<  4) // (MC) Security Bit Status
+#define AT91C_MC_GPNVM0           (0x1 <<  8) // (MC) Sector 0 Lock Status
+#define AT91C_MC_GPNVM1           (0x1 <<  9) // (MC) Sector 1 Lock Status
+#define AT91C_MC_GPNVM2           (0x1 << 10) // (MC) Sector 2 Lock Status
+#define AT91C_MC_GPNVM3           (0x1 << 11) // (MC) Sector 3 Lock Status
+#define AT91C_MC_GPNVM4           (0x1 << 12) // (MC) Sector 4 Lock Status
+#define AT91C_MC_GPNVM5           (0x1 << 13) // (MC) Sector 5 Lock Status
+#define AT91C_MC_GPNVM6           (0x1 << 14) // (MC) Sector 6 Lock Status
+#define AT91C_MC_GPNVM7           (0x1 << 15) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS0           (0x1 << 16) // (MC) Sector 0 Lock Status
+#define AT91C_MC_LOCKS1           (0x1 << 17) // (MC) Sector 1 Lock Status
+#define AT91C_MC_LOCKS2           (0x1 << 18) // (MC) Sector 2 Lock Status
+#define AT91C_MC_LOCKS3           (0x1 << 19) // (MC) Sector 3 Lock Status
+#define AT91C_MC_LOCKS4           (0x1 << 20) // (MC) Sector 4 Lock Status
+#define AT91C_MC_LOCKS5           (0x1 << 21) // (MC) Sector 5 Lock Status
+#define AT91C_MC_LOCKS6           (0x1 << 22) // (MC) Sector 6 Lock Status
+#define AT91C_MC_LOCKS7           (0x1 << 23) // (MC) Sector 7 Lock Status
+#define AT91C_MC_LOCKS8           (0x1 << 24) // (MC) Sector 8 Lock Status
+#define AT91C_MC_LOCKS9           (0x1 << 25) // (MC) Sector 9 Lock Status
+#define AT91C_MC_LOCKS10          (0x1 << 26) // (MC) Sector 10 Lock Status
+#define AT91C_MC_LOCKS11          (0x1 << 27) // (MC) Sector 11 Lock Status
+#define AT91C_MC_LOCKS12          (0x1 << 28) // (MC) Sector 12 Lock Status
+#define AT91C_MC_LOCKS13          (0x1 << 29) // (MC) Sector 13 Lock Status
+#define AT91C_MC_LOCKS14          (0x1 << 30) // (MC) Sector 14 Lock Status
+#define AT91C_MC_LOCKS15          (0x1 << 31) // (MC) Sector 15 Lock Status
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SPI structure ***
+#define SPI_CR          ( 0) // Control Register
+#define SPI_MR          ( 4) // Mode Register
+#define SPI_RDR         ( 8) // Receive Data Register
+#define SPI_TDR         (12) // Transmit Data Register
+#define SPI_SR          (16) // Status Register
+#define SPI_IER         (20) // Interrupt Enable Register
+#define SPI_IDR         (24) // Interrupt Disable Register
+#define SPI_IMR         (28) // Interrupt Mask Register
+#define SPI_CSR         (48) // Chip Select Register
+#define SPI_RPR         (256) // Receive Pointer Register
+#define SPI_RCR         (260) // Receive Counter Register
+#define SPI_TPR         (264) // Transmit Pointer Register
+#define SPI_TCR         (268) // Transmit Counter Register
+#define SPI_RNPR        (272) // Receive Next Pointer Register
+#define SPI_RNCR        (276) // Receive Next Counter Register
+#define SPI_TNPR        (280) // Transmit Next Pointer Register
+#define SPI_TNCR        (284) // Transmit Next Counter Register
+#define SPI_PTCR        (288) // PDC Transfer Control Register
+#define SPI_PTSR        (292) // PDC Transfer Status Register
+// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
+#define AT91C_SPI_SPIEN           (0x1 <<  0) // (SPI) SPI Enable
+#define AT91C_SPI_SPIDIS          (0x1 <<  1) // (SPI) SPI Disable
+#define AT91C_SPI_SWRST           (0x1 <<  7) // (SPI) SPI Software reset
+#define AT91C_SPI_LASTXFER        (0x1 << 24) // (SPI) SPI Last Transfer
+// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
+#define AT91C_SPI_MSTR            (0x1 <<  0) // (SPI) Master/Slave Mode
+#define AT91C_SPI_PS              (0x1 <<  1) // (SPI) Peripheral Select
+#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
+#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
+#define AT91C_SPI_PCSDEC          (0x1 <<  2) // (SPI) Chip Select Decode
+#define AT91C_SPI_FDIV            (0x1 <<  3) // (SPI) Clock Selection
+#define AT91C_SPI_MODFDIS         (0x1 <<  4) // (SPI) Mode Fault Detection
+#define AT91C_SPI_LLB             (0x1 <<  7) // (SPI) Clock Selection
+#define AT91C_SPI_PCS             (0xF << 16) // (SPI) Peripheral Chip Select
+#define AT91C_SPI_DLYBCS          (0xFF << 24) // (SPI) Delay Between Chip Selects
+// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
+#define AT91C_SPI_RD              (0xFFFF <<  0) // (SPI) Receive Data
+#define AT91C_SPI_RPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
+#define AT91C_SPI_TD              (0xFFFF <<  0) // (SPI) Transmit Data
+#define AT91C_SPI_TPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
+// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
+#define AT91C_SPI_RDRF            (0x1 <<  0) // (SPI) Receive Data Register Full
+#define AT91C_SPI_TDRE            (0x1 <<  1) // (SPI) Transmit Data Register Empty
+#define AT91C_SPI_MODF            (0x1 <<  2) // (SPI) Mode Fault Error
+#define AT91C_SPI_OVRES           (0x1 <<  3) // (SPI) Overrun Error Status
+#define AT91C_SPI_ENDRX           (0x1 <<  4) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_ENDTX           (0x1 <<  5) // (SPI) End of Receiver Transfer
+#define AT91C_SPI_RXBUFF          (0x1 <<  6) // (SPI) RXBUFF Interrupt
+#define AT91C_SPI_TXBUFE          (0x1 <<  7) // (SPI) TXBUFE Interrupt
+#define AT91C_SPI_NSSR            (0x1 <<  8) // (SPI) NSSR Interrupt
+#define AT91C_SPI_TXEMPTY         (0x1 <<  9) // (SPI) TXEMPTY Interrupt
+#define AT91C_SPI_SPIENS          (0x1 << 16) // (SPI) Enable Status
+// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
+// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
+// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
+// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
+#define AT91C_SPI_CPOL            (0x1 <<  0) // (SPI) Clock Polarity
+#define AT91C_SPI_NCPHA           (0x1 <<  1) // (SPI) Clock Phase
+#define AT91C_SPI_CSAAT           (0x1 <<  3) // (SPI) Chip Select Active After Transfer
+#define AT91C_SPI_BITS            (0xF <<  4) // (SPI) Bits Per Transfer
+#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
+#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
+#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
+#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
+#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
+#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
+#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
+#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
+#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
+#define AT91C_SPI_SCBR            (0xFF <<  8) // (SPI) Serial Clock Baud Rate
+#define AT91C_SPI_DLYBS           (0xFF << 16) // (SPI) Delay Before SPCK
+#define AT91C_SPI_DLYBCT          (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Usart
+// *****************************************************************************
+// *** Register offset in AT91S_USART structure ***
+#define US_CR           ( 0) // Control Register
+#define US_MR           ( 4) // Mode Register
+#define US_IER          ( 8) // Interrupt Enable Register
+#define US_IDR          (12) // Interrupt Disable Register
+#define US_IMR          (16) // Interrupt Mask Register
+#define US_CSR          (20) // Channel Status Register
+#define US_RHR          (24) // Receiver Holding Register
+#define US_THR          (28) // Transmitter Holding Register
+#define US_BRGR         (32) // Baud Rate Generator Register
+#define US_RTOR         (36) // Receiver Time-out Register
+#define US_TTGR         (40) // Transmitter Time-guard Register
+#define US_FIDI         (64) // FI_DI_Ratio Register
+#define US_NER          (68) // Nb Errors Register
+#define US_IF           (76) // IRDA_FILTER Register
+#define US_RPR          (256) // Receive Pointer Register
+#define US_RCR          (260) // Receive Counter Register
+#define US_TPR          (264) // Transmit Pointer Register
+#define US_TCR          (268) // Transmit Counter Register
+#define US_RNPR         (272) // Receive Next Pointer Register
+#define US_RNCR         (276) // Receive Next Counter Register
+#define US_TNPR         (280) // Transmit Next Pointer Register
+#define US_TNCR         (284) // Transmit Next Counter Register
+#define US_PTCR         (288) // PDC Transfer Control Register
+#define US_PTSR         (292) // PDC Transfer Status Register
+// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
+#define AT91C_US_STTBRK           (0x1 <<  9) // (USART) Start Break
+#define AT91C_US_STPBRK           (0x1 << 10) // (USART) Stop Break
+#define AT91C_US_STTTO            (0x1 << 11) // (USART) Start Time-out
+#define AT91C_US_SENDA            (0x1 << 12) // (USART) Send Address
+#define AT91C_US_RSTIT            (0x1 << 13) // (USART) Reset Iterations
+#define AT91C_US_RSTNACK          (0x1 << 14) // (USART) Reset Non Acknowledge
+#define AT91C_US_RETTO            (0x1 << 15) // (USART) Rearm Time-out
+#define AT91C_US_DTREN            (0x1 << 16) // (USART) Data Terminal ready Enable
+#define AT91C_US_DTRDIS           (0x1 << 17) // (USART) Data Terminal ready Disable
+#define AT91C_US_RTSEN            (0x1 << 18) // (USART) Request to Send enable
+#define AT91C_US_RTSDIS           (0x1 << 19) // (USART) Request to Send Disable
+// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
+#define AT91C_US_USMODE           (0xF <<  0) // (USART) Usart mode
+#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
+#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
+#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
+#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
+#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
+#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
+#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
+#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
+#define AT91C_US_CLKS             (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
+#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
+#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
+#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
+#define AT91C_US_CHRL             (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
+#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
+#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
+#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
+#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
+#define AT91C_US_SYNC             (0x1 <<  8) // (USART) Synchronous Mode Select
+#define AT91C_US_NBSTOP           (0x3 << 12) // (USART) Number of Stop bits
+#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
+#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
+#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
+#define AT91C_US_MSBF             (0x1 << 16) // (USART) Bit Order
+#define AT91C_US_MODE9            (0x1 << 17) // (USART) 9-bit Character length
+#define AT91C_US_CKLO             (0x1 << 18) // (USART) Clock Output Select
+#define AT91C_US_OVER             (0x1 << 19) // (USART) Over Sampling Mode
+#define AT91C_US_INACK            (0x1 << 20) // (USART) Inhibit Non Acknowledge
+#define AT91C_US_DSNACK           (0x1 << 21) // (USART) Disable Successive NACK
+#define AT91C_US_MAX_ITER         (0x1 << 24) // (USART) Number of Repetitions
+#define AT91C_US_FILTER           (0x1 << 28) // (USART) Receive Line Filter
+// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
+#define AT91C_US_RXBRK            (0x1 <<  2) // (USART) Break Received/End of Break
+#define AT91C_US_TIMEOUT          (0x1 <<  8) // (USART) Receiver Time-out
+#define AT91C_US_ITERATION        (0x1 << 10) // (USART) Max number of Repetitions Reached
+#define AT91C_US_NACK             (0x1 << 13) // (USART) Non Acknowledge
+#define AT91C_US_RIIC             (0x1 << 16) // (USART) Ring INdicator Input Change Flag
+#define AT91C_US_DSRIC            (0x1 << 17) // (USART) Data Set Ready Input Change Flag
+#define AT91C_US_DCDIC            (0x1 << 18) // (USART) Data Carrier Flag
+#define AT91C_US_CTSIC            (0x1 << 19) // (USART) Clear To Send Input Change Flag
+// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
+// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
+// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
+#define AT91C_US_RI               (0x1 << 20) // (USART) Image of RI Input
+#define AT91C_US_DSR              (0x1 << 21) // (USART) Image of DSR Input
+#define AT91C_US_DCD              (0x1 << 22) // (USART) Image of DCD Input
+#define AT91C_US_CTS              (0x1 << 23) // (USART) Image of CTS Input
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_SSC structure ***
+#define SSC_CR          ( 0) // Control Register
+#define SSC_CMR         ( 4) // Clock Mode Register
+#define SSC_RCMR        (16) // Receive Clock ModeRegister
+#define SSC_RFMR        (20) // Receive Frame Mode Register
+#define SSC_TCMR        (24) // Transmit Clock Mode Register
+#define SSC_TFMR        (28) // Transmit Frame Mode Register
+#define SSC_RHR         (32) // Receive Holding Register
+#define SSC_THR         (36) // Transmit Holding Register
+#define SSC_RSHR        (48) // Receive Sync Holding Register
+#define SSC_TSHR        (52) // Transmit Sync Holding Register
+#define SSC_SR          (64) // Status Register
+#define SSC_IER         (68) // Interrupt Enable Register
+#define SSC_IDR         (72) // Interrupt Disable Register
+#define SSC_IMR         (76) // Interrupt Mask Register
+#define SSC_RPR         (256) // Receive Pointer Register
+#define SSC_RCR         (260) // Receive Counter Register
+#define SSC_TPR         (264) // Transmit Pointer Register
+#define SSC_TCR         (268) // Transmit Counter Register
+#define SSC_RNPR        (272) // Receive Next Pointer Register
+#define SSC_RNCR        (276) // Receive Next Counter Register
+#define SSC_TNPR        (280) // Transmit Next Pointer Register
+#define SSC_TNCR        (284) // Transmit Next Counter Register
+#define SSC_PTCR        (288) // PDC Transfer Control Register
+#define SSC_PTSR        (292) // PDC Transfer Status Register
+// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
+#define AT91C_SSC_RXEN            (0x1 <<  0) // (SSC) Receive Enable
+#define AT91C_SSC_RXDIS           (0x1 <<  1) // (SSC) Receive Disable
+#define AT91C_SSC_TXEN            (0x1 <<  8) // (SSC) Transmit Enable
+#define AT91C_SSC_TXDIS           (0x1 <<  9) // (SSC) Transmit Disable
+#define AT91C_SSC_SWRST           (0x1 << 15) // (SSC) Software Reset
+// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
+#define AT91C_SSC_CKS             (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
+#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
+#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
+#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
+#define AT91C_SSC_CKO             (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
+#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
+#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
+#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
+#define AT91C_SSC_CKI             (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
+#define AT91C_SSC_START           (0xF <<  8) // (SSC) Receive/Transmit Start Selection
+#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
+#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
+#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
+#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
+#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
+#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
+#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
+#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
+#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
+#define AT91C_SSC_STTDLY          (0xFF << 16) // (SSC) Receive/Transmit Start Delay
+#define AT91C_SSC_PERIOD          (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
+// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
+#define AT91C_SSC_DATLEN          (0x1F <<  0) // (SSC) Data Length
+#define AT91C_SSC_LOOP            (0x1 <<  5) // (SSC) Loop Mode
+#define AT91C_SSC_MSBF            (0x1 <<  7) // (SSC) Most Significant Bit First
+#define AT91C_SSC_DATNB           (0xF <<  8) // (SSC) Data Number per Frame
+#define AT91C_SSC_FSLEN           (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
+#define AT91C_SSC_FSOS            (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
+#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
+#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
+#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
+#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
+#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
+#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
+#define AT91C_SSC_FSEDGE          (0x1 << 24) // (SSC) Frame Sync Edge Detection
+// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
+// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
+#define AT91C_SSC_DATDEF          (0x1 <<  5) // (SSC) Data Default Value
+#define AT91C_SSC_FSDEN           (0x1 << 23) // (SSC) Frame Sync Data Enable
+// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
+#define AT91C_SSC_TXRDY           (0x1 <<  0) // (SSC) Transmit Ready
+#define AT91C_SSC_TXEMPTY         (0x1 <<  1) // (SSC) Transmit Empty
+#define AT91C_SSC_ENDTX           (0x1 <<  2) // (SSC) End Of Transmission
+#define AT91C_SSC_TXBUFE          (0x1 <<  3) // (SSC) Transmit Buffer Empty
+#define AT91C_SSC_RXRDY           (0x1 <<  4) // (SSC) Receive Ready
+#define AT91C_SSC_OVRUN           (0x1 <<  5) // (SSC) Receive Overrun
+#define AT91C_SSC_ENDRX           (0x1 <<  6) // (SSC) End of Reception
+#define AT91C_SSC_RXBUFF          (0x1 <<  7) // (SSC) Receive Buffer Full
+#define AT91C_SSC_TXSYN           (0x1 << 10) // (SSC) Transmit Sync
+#define AT91C_SSC_RXSYN           (0x1 << 11) // (SSC) Receive Sync
+#define AT91C_SSC_TXENA           (0x1 << 16) // (SSC) Transmit Enable
+#define AT91C_SSC_RXENA           (0x1 << 17) // (SSC) Receive Enable
+// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
+// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
+// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Two-wire Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TWI structure ***
+#define TWI_CR          ( 0) // Control Register
+#define TWI_MMR         ( 4) // Master Mode Register
+#define TWI_IADR        (12) // Internal Address Register
+#define TWI_CWGR        (16) // Clock Waveform Generator Register
+#define TWI_SR          (32) // Status Register
+#define TWI_IER         (36) // Interrupt Enable Register
+#define TWI_IDR         (40) // Interrupt Disable Register
+#define TWI_IMR         (44) // Interrupt Mask Register
+#define TWI_RHR         (48) // Receive Holding Register
+#define TWI_THR         (52) // Transmit Holding Register
+// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
+#define AT91C_TWI_START           (0x1 <<  0) // (TWI) Send a START Condition
+#define AT91C_TWI_STOP            (0x1 <<  1) // (TWI) Send a STOP Condition
+#define AT91C_TWI_MSEN            (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
+#define AT91C_TWI_MSDIS           (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
+#define AT91C_TWI_SWRST           (0x1 <<  7) // (TWI) Software Reset
+// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
+#define AT91C_TWI_IADRSZ          (0x3 <<  8) // (TWI) Internal Device Address Size
+#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
+#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
+#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
+#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
+#define AT91C_TWI_MREAD           (0x1 << 12) // (TWI) Master Read Direction
+#define AT91C_TWI_DADR            (0x7F << 16) // (TWI) Device Address
+// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
+#define AT91C_TWI_CLDIV           (0xFF <<  0) // (TWI) Clock Low Divider
+#define AT91C_TWI_CHDIV           (0xFF <<  8) // (TWI) Clock High Divider
+#define AT91C_TWI_CKDIV           (0x7 << 16) // (TWI) Clock Divider
+// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
+#define AT91C_TWI_TXCOMP          (0x1 <<  0) // (TWI) Transmission Completed
+#define AT91C_TWI_RXRDY           (0x1 <<  1) // (TWI) Receive holding register ReaDY
+#define AT91C_TWI_TXRDY           (0x1 <<  2) // (TWI) Transmit holding register ReaDY
+#define AT91C_TWI_OVRE            (0x1 <<  6) // (TWI) Overrun Error
+#define AT91C_TWI_UNRE            (0x1 <<  7) // (TWI) Underrun Error
+#define AT91C_TWI_NACK            (0x1 <<  8) // (TWI) Not Acknowledged
+// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
+// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
+// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC_CH structure ***
+#define PWMC_CMR        ( 0) // Channel Mode Register
+#define PWMC_CDTYR      ( 4) // Channel Duty Cycle Register
+#define PWMC_CPRDR      ( 8) // Channel Period Register
+#define PWMC_CCNTR      (12) // Channel Counter Register
+#define PWMC_CUPDR      (16) // Channel Update Register
+#define PWMC_Reserved   (20) // Reserved
+// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
+#define AT91C_PWMC_CPRE           (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
+#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH) 
+#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH) 
+#define AT91C_PWMC_CALG           (0x1 <<  8) // (PWMC_CH) Channel Alignment
+#define AT91C_PWMC_CPOL           (0x1 <<  9) // (PWMC_CH) Channel Polarity
+#define AT91C_PWMC_CPD            (0x1 << 10) // (PWMC_CH) Channel Update Period
+// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
+#define AT91C_PWMC_CDTY           (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
+// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
+#define AT91C_PWMC_CPRD           (0x0 <<  0) // (PWMC_CH) Channel Period
+// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
+#define AT91C_PWMC_CCNT           (0x0 <<  0) // (PWMC_CH) Channel Counter
+// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
+#define AT91C_PWMC_CUPD           (0x0 <<  0) // (PWMC_CH) Channel Update
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
+// *****************************************************************************
+// *** Register offset in AT91S_PWMC structure ***
+#define PWMC_MR         ( 0) // PWMC Mode Register
+#define PWMC_ENA        ( 4) // PWMC Enable Register
+#define PWMC_DIS        ( 8) // PWMC Disable Register
+#define PWMC_SR         (12) // PWMC Status Register
+#define PWMC_IER        (16) // PWMC Interrupt Enable Register
+#define PWMC_IDR        (20) // PWMC Interrupt Disable Register
+#define PWMC_IMR        (24) // PWMC Interrupt Mask Register
+#define PWMC_ISR        (28) // PWMC Interrupt Status Register
+#define PWMC_VR         (252) // PWMC Version Register
+#define PWMC_CH         (512) // PWMC Channel
+// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
+#define AT91C_PWMC_DIVA           (0xFF <<  0) // (PWMC) CLKA divide factor.
+#define AT91C_PWMC_PREA           (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
+#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC) 
+#define AT91C_PWMC_DIVB           (0xFF << 16) // (PWMC) CLKB divide factor.
+#define AT91C_PWMC_PREB           (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
+#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC) 
+// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
+#define AT91C_PWMC_CHID0          (0x1 <<  0) // (PWMC) Channel ID 0
+#define AT91C_PWMC_CHID1          (0x1 <<  1) // (PWMC) Channel ID 1
+#define AT91C_PWMC_CHID2          (0x1 <<  2) // (PWMC) Channel ID 2
+#define AT91C_PWMC_CHID3          (0x1 <<  3) // (PWMC) Channel ID 3
+// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
+// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
+// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
+// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
+// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
+// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR USB Device Interface
+// *****************************************************************************
+// *** Register offset in AT91S_UDP structure ***
+#define UDP_NUM         ( 0) // Frame Number Register
+#define UDP_GLBSTATE    ( 4) // Global State Register
+#define UDP_FADDR       ( 8) // Function Address Register
+#define UDP_IER         (16) // Interrupt Enable Register
+#define UDP_IDR         (20) // Interrupt Disable Register
+#define UDP_IMR         (24) // Interrupt Mask Register
+#define UDP_ISR         (28) // Interrupt Status Register
+#define UDP_ICR         (32) // Interrupt Clear Register
+#define UDP_RSTEP       (40) // Reset Endpoint Register
+#define UDP_CSR         (48) // Endpoint Control and Status Register
+#define UDP_FDR         (80) // Endpoint FIFO Data Register
+#define UDP_TXVC        (116) // Transceiver Control Register
+// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
+#define AT91C_UDP_FRM_NUM         (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
+#define AT91C_UDP_FRM_ERR         (0x1 << 16) // (UDP) Frame Error
+#define AT91C_UDP_FRM_OK          (0x1 << 17) // (UDP) Frame OK
+// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
+#define AT91C_UDP_FADDEN          (0x1 <<  0) // (UDP) Function Address Enable
+#define AT91C_UDP_CONFG           (0x1 <<  1) // (UDP) Configured
+#define AT91C_UDP_ESR             (0x1 <<  2) // (UDP) Enable Send Resume
+#define AT91C_UDP_RSMINPR         (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
+#define AT91C_UDP_RMWUPE          (0x1 <<  4) // (UDP) Remote Wake Up Enable
+// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
+#define AT91C_UDP_FADD            (0xFF <<  0) // (UDP) Function Address Value
+#define AT91C_UDP_FEN             (0x1 <<  8) // (UDP) Function Enable
+// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
+#define AT91C_UDP_EPINT0          (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT1          (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
+#define AT91C_UDP_EPINT2          (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
+#define AT91C_UDP_EPINT3          (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
+#define AT91C_UDP_EPINT4          (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
+#define AT91C_UDP_EPINT5          (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
+#define AT91C_UDP_RXSUSP          (0x1 <<  8) // (UDP) USB Suspend Interrupt
+#define AT91C_UDP_RXRSM           (0x1 <<  9) // (UDP) USB Resume Interrupt
+#define AT91C_UDP_EXTRSM          (0x1 << 10) // (UDP) USB External Resume Interrupt
+#define AT91C_UDP_SOFINT          (0x1 << 11) // (UDP) USB Start Of frame Interrupt
+#define AT91C_UDP_WAKEUP          (0x1 << 13) // (UDP) USB Resume Interrupt
+// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
+// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
+// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
+#define AT91C_UDP_ENDBUSRES       (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
+// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
+// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
+#define AT91C_UDP_EP0             (0x1 <<  0) // (UDP) Reset Endpoint 0
+#define AT91C_UDP_EP1             (0x1 <<  1) // (UDP) Reset Endpoint 1
+#define AT91C_UDP_EP2             (0x1 <<  2) // (UDP) Reset Endpoint 2
+#define AT91C_UDP_EP3             (0x1 <<  3) // (UDP) Reset Endpoint 3
+#define AT91C_UDP_EP4             (0x1 <<  4) // (UDP) Reset Endpoint 4
+#define AT91C_UDP_EP5             (0x1 <<  5) // (UDP) Reset Endpoint 5
+// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
+#define AT91C_UDP_TXCOMP          (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
+#define AT91C_UDP_RX_DATA_BK0     (0x1 <<  1) // (UDP) Receive Data Bank 0
+#define AT91C_UDP_RXSETUP         (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
+#define AT91C_UDP_ISOERROR        (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
+#define AT91C_UDP_TXPKTRDY        (0x1 <<  4) // (UDP) Transmit Packet Ready
+#define AT91C_UDP_FORCESTALL      (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
+#define AT91C_UDP_RX_DATA_BK1     (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
+#define AT91C_UDP_DIR             (0x1 <<  7) // (UDP) Transfer Direction
+#define AT91C_UDP_EPTYPE          (0x7 <<  8) // (UDP) Endpoint type
+#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
+#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
+#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
+#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
+#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
+#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
+#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
+#define AT91C_UDP_DTGLE           (0x1 << 11) // (UDP) Data Toggle
+#define AT91C_UDP_EPEDS           (0x1 << 15) // (UDP) Endpoint Enable Disable
+#define AT91C_UDP_RXBYTECNT       (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
+// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
+#define AT91C_UDP_TXVDIS          (0x1 <<  8) // (UDP) 
+#define AT91C_UDP_PUON            (0x1 <<  9) // (UDP) Pull-up ON
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TC structure ***
+#define TC_CCR          ( 0) // Channel Control Register
+#define TC_CMR          ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
+#define TC_CV           (16) // Counter Value
+#define TC_RA           (20) // Register A
+#define TC_RB           (24) // Register B
+#define TC_RC           (28) // Register C
+#define TC_SR           (32) // Status Register
+#define TC_IER          (36) // Interrupt Enable Register
+#define TC_IDR          (40) // Interrupt Disable Register
+#define TC_IMR          (44) // Interrupt Mask Register
+// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
+#define AT91C_TC_CLKEN            (0x1 <<  0) // (TC) Counter Clock Enable Command
+#define AT91C_TC_CLKDIS           (0x1 <<  1) // (TC) Counter Clock Disable Command
+#define AT91C_TC_SWTRG            (0x1 <<  2) // (TC) Software Trigger Command
+// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
+#define AT91C_TC_CLKS             (0x7 <<  0) // (TC) Clock Selection
+#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
+#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
+#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
+#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
+#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
+#define AT91C_TC_CLKI             (0x1 <<  3) // (TC) Clock Invert
+#define AT91C_TC_BURST            (0x3 <<  4) // (TC) Burst Signal Selection
+#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
+#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
+#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
+#define AT91C_TC_CPCSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
+#define AT91C_TC_LDBSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
+#define AT91C_TC_CPCDIS           (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
+#define AT91C_TC_LDBDIS           (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
+#define AT91C_TC_ETRGEDG          (0x3 <<  8) // (TC) External Trigger Edge Selection
+#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVTEDG          (0x3 <<  8) // (TC) External Event Edge Selection
+#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
+#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
+#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
+#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
+#define AT91C_TC_EEVT             (0x3 << 10) // (TC) External Event  Selection
+#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
+#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
+#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
+#define AT91C_TC_ABETRG           (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
+#define AT91C_TC_ENETRG           (0x1 << 12) // (TC) External Event Trigger enable
+#define AT91C_TC_WAVESEL          (0x3 << 13) // (TC) Waveform  Selection
+#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
+#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
+#define AT91C_TC_CPCTRG           (0x1 << 14) // (TC) RC Compare Trigger Enable
+#define AT91C_TC_WAVE             (0x1 << 15) // (TC) 
+#define AT91C_TC_ACPA             (0x3 << 16) // (TC) RA Compare Effect on TIOA
+#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
+#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
+#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
+#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
+#define AT91C_TC_LDRA             (0x3 << 16) // (TC) RA Loading Selection
+#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
+#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_ACPC             (0x3 << 18) // (TC) RC Compare Effect on TIOA
+#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
+#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
+#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
+#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
+#define AT91C_TC_LDRB             (0x3 << 18) // (TC) RB Loading Selection
+#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
+#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
+#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
+#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
+#define AT91C_TC_AEEVT            (0x3 << 20) // (TC) External Event Effect on TIOA
+#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
+#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
+#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
+#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
+#define AT91C_TC_ASWTRG           (0x3 << 22) // (TC) Software Trigger Effect on TIOA
+#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
+#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
+#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
+#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
+#define AT91C_TC_BCPB             (0x3 << 24) // (TC) RB Compare Effect on TIOB
+#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
+#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
+#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
+#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
+#define AT91C_TC_BCPC             (0x3 << 26) // (TC) RC Compare Effect on TIOB
+#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
+#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
+#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
+#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
+#define AT91C_TC_BEEVT            (0x3 << 28) // (TC) External Event Effect on TIOB
+#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
+#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
+#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
+#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
+#define AT91C_TC_BSWTRG           (0x3 << 30) // (TC) Software Trigger Effect on TIOB
+#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
+#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
+#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
+#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
+// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
+#define AT91C_TC_COVFS            (0x1 <<  0) // (TC) Counter Overflow
+#define AT91C_TC_LOVRS            (0x1 <<  1) // (TC) Load Overrun
+#define AT91C_TC_CPAS             (0x1 <<  2) // (TC) RA Compare
+#define AT91C_TC_CPBS             (0x1 <<  3) // (TC) RB Compare
+#define AT91C_TC_CPCS             (0x1 <<  4) // (TC) RC Compare
+#define AT91C_TC_LDRAS            (0x1 <<  5) // (TC) RA Loading
+#define AT91C_TC_LDRBS            (0x1 <<  6) // (TC) RB Loading
+#define AT91C_TC_ETRGS            (0x1 <<  7) // (TC) External Trigger
+#define AT91C_TC_CLKSTA           (0x1 << 16) // (TC) Clock Enabling
+#define AT91C_TC_MTIOA            (0x1 << 17) // (TC) TIOA Mirror
+#define AT91C_TC_MTIOB            (0x1 << 18) // (TC) TIOA Mirror
+// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
+// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
+// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
+// *****************************************************************************
+// *** Register offset in AT91S_TCB structure ***
+#define TCB_TC0         ( 0) // TC Channel 0
+#define TCB_TC1         (64) // TC Channel 1
+#define TCB_TC2         (128) // TC Channel 2
+#define TCB_BCR         (192) // TC Block Control Register
+#define TCB_BMR         (196) // TC Block Mode Register
+// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
+#define AT91C_TCB_SYNC            (0x1 <<  0) // (TCB) Synchro Command
+// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
+#define AT91C_TCB_TC0XC0S         (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
+#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
+#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
+#define AT91C_TCB_TC1XC1S         (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
+#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
+#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
+#define AT91C_TCB_TC2XC2S         (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
+#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
+#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
+// *****************************************************************************
+// *** Register offset in AT91S_CAN_MB structure ***
+#define CAN_MB_MMR      ( 0) // MailBox Mode Register
+#define CAN_MB_MAM      ( 4) // MailBox Acceptance Mask Register
+#define CAN_MB_MID      ( 8) // MailBox ID Register
+#define CAN_MB_MFID     (12) // MailBox Family ID Register
+#define CAN_MB_MSR      (16) // MailBox Status Register
+#define CAN_MB_MDL      (20) // MailBox Data Low Register
+#define CAN_MB_MDH      (24) // MailBox Data High Register
+#define CAN_MB_MCR      (28) // MailBox Control Register
+// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
+#define AT91C_CAN_MTIMEMARK       (0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
+#define AT91C_CAN_PRIOR           (0xF << 16) // (CAN_MB) Mailbox Priority
+#define AT91C_CAN_MOT             (0x7 << 24) // (CAN_MB) Mailbox Object Type
+#define 	AT91C_CAN_MOT_DIS                  (0x0 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RX                   (0x1 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_RXOVERWRITE          (0x2 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_TX                   (0x3 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_CONSUMER             (0x4 << 24) // (CAN_MB) 
+#define 	AT91C_CAN_MOT_PRODUCER             (0x5 << 24) // (CAN_MB) 
+// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
+#define AT91C_CAN_MIDvB           (0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
+#define AT91C_CAN_MIDvA           (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
+#define AT91C_CAN_MIDE            (0x1 << 29) // (CAN_MB) Identifier Version
+// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
+// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
+// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
+#define AT91C_CAN_MTIMESTAMP      (0xFFFF <<  0) // (CAN_MB) Timer Value
+#define AT91C_CAN_MDLC            (0xF << 16) // (CAN_MB) Mailbox Data Length Code
+#define AT91C_CAN_MRTR            (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
+#define AT91C_CAN_MABT            (0x1 << 22) // (CAN_MB) Mailbox Message Abort
+#define AT91C_CAN_MRDY            (0x1 << 23) // (CAN_MB) Mailbox Ready
+#define AT91C_CAN_MMI             (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
+// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
+// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
+// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
+#define AT91C_CAN_MACR            (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
+#define AT91C_CAN_MTCR            (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
+// *****************************************************************************
+// *** Register offset in AT91S_CAN structure ***
+#define CAN_MR          ( 0) // Mode Register
+#define CAN_IER         ( 4) // Interrupt Enable Register
+#define CAN_IDR         ( 8) // Interrupt Disable Register
+#define CAN_IMR         (12) // Interrupt Mask Register
+#define CAN_SR          (16) // Status Register
+#define CAN_BR          (20) // Baudrate Register
+#define CAN_TIM         (24) // Timer Register
+#define CAN_TIMESTP     (28) // Time Stamp Register
+#define CAN_ECR         (32) // Error Counter Register
+#define CAN_TCR         (36) // Transfer Command Register
+#define CAN_ACR         (40) // Abort Command Register
+#define CAN_VR          (252) // Version Register
+#define CAN_MB0         (512) // CAN Mailbox 0
+#define CAN_MB1         (544) // CAN Mailbox 1
+#define CAN_MB2         (576) // CAN Mailbox 2
+#define CAN_MB3         (608) // CAN Mailbox 3
+#define CAN_MB4         (640) // CAN Mailbox 4
+#define CAN_MB5         (672) // CAN Mailbox 5
+#define CAN_MB6         (704) // CAN Mailbox 6
+#define CAN_MB7         (736) // CAN Mailbox 7
+#define CAN_MB8         (768) // CAN Mailbox 8
+#define CAN_MB9         (800) // CAN Mailbox 9
+#define CAN_MB10        (832) // CAN Mailbox 10
+#define CAN_MB11        (864) // CAN Mailbox 11
+#define CAN_MB12        (896) // CAN Mailbox 12
+#define CAN_MB13        (928) // CAN Mailbox 13
+#define CAN_MB14        (960) // CAN Mailbox 14
+#define CAN_MB15        (992) // CAN Mailbox 15
+// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
+#define AT91C_CAN_CANEN           (0x1 <<  0) // (CAN) CAN Controller Enable
+#define AT91C_CAN_LPM             (0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
+#define AT91C_CAN_ABM             (0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
+#define AT91C_CAN_OVL             (0x1 <<  3) // (CAN) Disable/Enable Overload Frame
+#define AT91C_CAN_TEOF            (0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
+#define AT91C_CAN_TTM             (0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
+#define AT91C_CAN_TIMFRZ          (0x1 <<  6) // (CAN) Enable Timer Freeze
+#define AT91C_CAN_DRPT            (0x1 <<  7) // (CAN) Disable Repeat
+// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
+#define AT91C_CAN_MB0             (0x1 <<  0) // (CAN) Mailbox 0 Flag
+#define AT91C_CAN_MB1             (0x1 <<  1) // (CAN) Mailbox 1 Flag
+#define AT91C_CAN_MB2             (0x1 <<  2) // (CAN) Mailbox 2 Flag
+#define AT91C_CAN_MB3             (0x1 <<  3) // (CAN) Mailbox 3 Flag
+#define AT91C_CAN_MB4             (0x1 <<  4) // (CAN) Mailbox 4 Flag
+#define AT91C_CAN_MB5             (0x1 <<  5) // (CAN) Mailbox 5 Flag
+#define AT91C_CAN_MB6             (0x1 <<  6) // (CAN) Mailbox 6 Flag
+#define AT91C_CAN_MB7             (0x1 <<  7) // (CAN) Mailbox 7 Flag
+#define AT91C_CAN_MB8             (0x1 <<  8) // (CAN) Mailbox 8 Flag
+#define AT91C_CAN_MB9             (0x1 <<  9) // (CAN) Mailbox 9 Flag
+#define AT91C_CAN_MB10            (0x1 << 10) // (CAN) Mailbox 10 Flag
+#define AT91C_CAN_MB11            (0x1 << 11) // (CAN) Mailbox 11 Flag
+#define AT91C_CAN_MB12            (0x1 << 12) // (CAN) Mailbox 12 Flag
+#define AT91C_CAN_MB13            (0x1 << 13) // (CAN) Mailbox 13 Flag
+#define AT91C_CAN_MB14            (0x1 << 14) // (CAN) Mailbox 14 Flag
+#define AT91C_CAN_MB15            (0x1 << 15) // (CAN) Mailbox 15 Flag
+#define AT91C_CAN_ERRA            (0x1 << 16) // (CAN) Error Active Mode Flag
+#define AT91C_CAN_WARN            (0x1 << 17) // (CAN) Warning Limit Flag
+#define AT91C_CAN_ERRP            (0x1 << 18) // (CAN) Error Passive Mode Flag
+#define AT91C_CAN_BOFF            (0x1 << 19) // (CAN) Bus Off Mode Flag
+#define AT91C_CAN_SLEEP           (0x1 << 20) // (CAN) Sleep Flag
+#define AT91C_CAN_WAKEUP          (0x1 << 21) // (CAN) Wakeup Flag
+#define AT91C_CAN_TOVF            (0x1 << 22) // (CAN) Timer Overflow Flag
+#define AT91C_CAN_TSTP            (0x1 << 23) // (CAN) Timestamp Flag
+#define AT91C_CAN_CERR            (0x1 << 24) // (CAN) CRC Error
+#define AT91C_CAN_SERR            (0x1 << 25) // (CAN) Stuffing Error
+#define AT91C_CAN_AERR            (0x1 << 26) // (CAN) Acknowledgment Error
+#define AT91C_CAN_FERR            (0x1 << 27) // (CAN) Form Error
+#define AT91C_CAN_BERR            (0x1 << 28) // (CAN) Bit Error
+// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
+// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
+// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
+#define AT91C_CAN_RBSY            (0x1 << 29) // (CAN) Receiver Busy
+#define AT91C_CAN_TBSY            (0x1 << 30) // (CAN) Transmitter Busy
+#define AT91C_CAN_OVLY            (0x1 << 31) // (CAN) Overload Busy
+// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
+#define AT91C_CAN_PHASE2          (0x7 <<  0) // (CAN) Phase 2 segment
+#define AT91C_CAN_PHASE1          (0x7 <<  4) // (CAN) Phase 1 segment
+#define AT91C_CAN_PROPAG          (0x7 <<  8) // (CAN) Programmation time segment
+#define AT91C_CAN_SYNC            (0x3 << 12) // (CAN) Re-synchronization jump width segment
+#define AT91C_CAN_BRP             (0x7F << 16) // (CAN) Baudrate Prescaler
+#define AT91C_CAN_SMP             (0x1 << 24) // (CAN) Sampling mode
+// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
+#define AT91C_CAN_TIMER           (0xFFFF <<  0) // (CAN) Timer field
+// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
+// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
+#define AT91C_CAN_REC             (0xFF <<  0) // (CAN) Receive Error Counter
+#define AT91C_CAN_TEC             (0xFF << 16) // (CAN) Transmit Error Counter
+// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
+#define AT91C_CAN_TIMRST          (0x1 << 31) // (CAN) Timer Reset Field
+// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
+// *****************************************************************************
+// *** Register offset in AT91S_EMAC structure ***
+#define EMAC_NCR        ( 0) // Network Control Register
+#define EMAC_NCFGR      ( 4) // Network Configuration Register
+#define EMAC_NSR        ( 8) // Network Status Register
+#define EMAC_TSR        (20) // Transmit Status Register
+#define EMAC_RBQP       (24) // Receive Buffer Queue Pointer
+#define EMAC_TBQP       (28) // Transmit Buffer Queue Pointer
+#define EMAC_RSR        (32) // Receive Status Register
+#define EMAC_ISR        (36) // Interrupt Status Register
+#define EMAC_IER        (40) // Interrupt Enable Register
+#define EMAC_IDR        (44) // Interrupt Disable Register
+#define EMAC_IMR        (48) // Interrupt Mask Register
+#define EMAC_MAN        (52) // PHY Maintenance Register
+#define EMAC_PTR        (56) // Pause Time Register
+#define EMAC_PFR        (60) // Pause Frames received Register
+#define EMAC_FTO        (64) // Frames Transmitted OK Register
+#define EMAC_SCF        (68) // Single Collision Frame Register
+#define EMAC_MCF        (72) // Multiple Collision Frame Register
+#define EMAC_FRO        (76) // Frames Received OK Register
+#define EMAC_FCSE       (80) // Frame Check Sequence Error Register
+#define EMAC_ALE        (84) // Alignment Error Register
+#define EMAC_DTF        (88) // Deferred Transmission Frame Register
+#define EMAC_LCOL       (92) // Late Collision Register
+#define EMAC_ECOL       (96) // Excessive Collision Register
+#define EMAC_TUND       (100) // Transmit Underrun Error Register
+#define EMAC_CSE        (104) // Carrier Sense Error Register
+#define EMAC_RRE        (108) // Receive Ressource Error Register
+#define EMAC_ROV        (112) // Receive Overrun Errors Register
+#define EMAC_RSE        (116) // Receive Symbol Errors Register
+#define EMAC_ELE        (120) // Excessive Length Errors Register
+#define EMAC_RJA        (124) // Receive Jabbers Register
+#define EMAC_USF        (128) // Undersize Frames Register
+#define EMAC_STE        (132) // SQE Test Error Register
+#define EMAC_RLE        (136) // Receive Length Field Mismatch Register
+#define EMAC_TPF        (140) // Transmitted Pause Frames Register
+#define EMAC_HRB        (144) // Hash Address Bottom[31:0]
+#define EMAC_HRT        (148) // Hash Address Top[63:32]
+#define EMAC_SA1L       (152) // Specific Address 1 Bottom, First 4 bytes
+#define EMAC_SA1H       (156) // Specific Address 1 Top, Last 2 bytes
+#define EMAC_SA2L       (160) // Specific Address 2 Bottom, First 4 bytes
+#define EMAC_SA2H       (164) // Specific Address 2 Top, Last 2 bytes
+#define EMAC_SA3L       (168) // Specific Address 3 Bottom, First 4 bytes
+#define EMAC_SA3H       (172) // Specific Address 3 Top, Last 2 bytes
+#define EMAC_SA4L       (176) // Specific Address 4 Bottom, First 4 bytes
+#define EMAC_SA4H       (180) // Specific Address 4 Top, Last 2 bytes
+#define EMAC_TID        (184) // Type ID Checking Register
+#define EMAC_TPQ        (188) // Transmit Pause Quantum Register
+#define EMAC_USRIO      (192) // USER Input/Output Register
+#define EMAC_WOL        (196) // Wake On LAN Register
+#define EMAC_REV        (252) // Revision Register
+// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
+#define AT91C_EMAC_LB             (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
+#define AT91C_EMAC_LLB            (0x1 <<  1) // (EMAC) Loopback local. 
+#define AT91C_EMAC_RE             (0x1 <<  2) // (EMAC) Receive enable. 
+#define AT91C_EMAC_TE             (0x1 <<  3) // (EMAC) Transmit enable. 
+#define AT91C_EMAC_MPE            (0x1 <<  4) // (EMAC) Management port enable. 
+#define AT91C_EMAC_CLRSTAT        (0x1 <<  5) // (EMAC) Clear statistics registers. 
+#define AT91C_EMAC_INCSTAT        (0x1 <<  6) // (EMAC) Increment statistics registers. 
+#define AT91C_EMAC_WESTAT         (0x1 <<  7) // (EMAC) Write enable for statistics registers. 
+#define AT91C_EMAC_BP             (0x1 <<  8) // (EMAC) Back pressure. 
+#define AT91C_EMAC_TSTART         (0x1 <<  9) // (EMAC) Start Transmission. 
+#define AT91C_EMAC_THALT          (0x1 << 10) // (EMAC) Transmission Halt. 
+#define AT91C_EMAC_TPFR           (0x1 << 11) // (EMAC) Transmit pause frame 
+#define AT91C_EMAC_TZQ            (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
+// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
+#define AT91C_EMAC_SPD            (0x1 <<  0) // (EMAC) Speed. 
+#define AT91C_EMAC_FD             (0x1 <<  1) // (EMAC) Full duplex. 
+#define AT91C_EMAC_JFRAME         (0x1 <<  3) // (EMAC) Jumbo Frames. 
+#define AT91C_EMAC_CAF            (0x1 <<  4) // (EMAC) Copy all frames. 
+#define AT91C_EMAC_NBC            (0x1 <<  5) // (EMAC) No broadcast. 
+#define AT91C_EMAC_MTI            (0x1 <<  6) // (EMAC) Multicast hash event enable
+#define AT91C_EMAC_UNI            (0x1 <<  7) // (EMAC) Unicast hash enable. 
+#define AT91C_EMAC_BIG            (0x1 <<  8) // (EMAC) Receive 1522 bytes. 
+#define AT91C_EMAC_EAE            (0x1 <<  9) // (EMAC) External address match enable. 
+#define AT91C_EMAC_CLK            (0x3 << 10) // (EMAC) 
+#define 	AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
+#define 	AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
+#define 	AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
+#define 	AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
+#define AT91C_EMAC_RTY            (0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PAE            (0x1 << 13) // (EMAC) 
+#define AT91C_EMAC_RBOF           (0x3 << 14) // (EMAC) 
+#define 	AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) // (EMAC) no offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
+#define 	AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
+#define AT91C_EMAC_RLCE           (0x1 << 16) // (EMAC) Receive Length field Checking Enable
+#define AT91C_EMAC_DRFCS          (0x1 << 17) // (EMAC) Discard Receive FCS
+#define AT91C_EMAC_EFRHD          (0x1 << 18) // (EMAC) 
+#define AT91C_EMAC_IRXFCS         (0x1 << 19) // (EMAC) Ignore RX FCS
+// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
+#define AT91C_EMAC_LINKR          (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_MDIO           (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_IDLE           (0x1 <<  2) // (EMAC) 
+// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
+#define AT91C_EMAC_UBR            (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_COL            (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RLES           (0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TGO            (0x1 <<  3) // (EMAC) Transmit Go
+#define AT91C_EMAC_BEX            (0x1 <<  4) // (EMAC) Buffers exhausted mid frame
+#define AT91C_EMAC_COMP           (0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_UND            (0x1 <<  6) // (EMAC) 
+// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
+#define AT91C_EMAC_BNA            (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_REC            (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_OVR            (0x1 <<  2) // (EMAC) 
+// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
+#define AT91C_EMAC_MFD            (0x1 <<  0) // (EMAC) 
+#define AT91C_EMAC_RCOMP          (0x1 <<  1) // (EMAC) 
+#define AT91C_EMAC_RXUBR          (0x1 <<  2) // (EMAC) 
+#define AT91C_EMAC_TXUBR          (0x1 <<  3) // (EMAC) 
+#define AT91C_EMAC_TUNDR          (0x1 <<  4) // (EMAC) 
+#define AT91C_EMAC_RLEX           (0x1 <<  5) // (EMAC) 
+#define AT91C_EMAC_TXERR          (0x1 <<  6) // (EMAC) 
+#define AT91C_EMAC_TCOMP          (0x1 <<  7) // (EMAC) 
+#define AT91C_EMAC_LINK           (0x1 <<  9) // (EMAC) 
+#define AT91C_EMAC_ROVR           (0x1 << 10) // (EMAC) 
+#define AT91C_EMAC_HRESP          (0x1 << 11) // (EMAC) 
+#define AT91C_EMAC_PFRE           (0x1 << 12) // (EMAC) 
+#define AT91C_EMAC_PTZ            (0x1 << 13) // (EMAC) 
+// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
+// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
+// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
+// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
+#define AT91C_EMAC_DATA           (0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_CODE           (0x3 << 16) // (EMAC) 
+#define AT91C_EMAC_REGA           (0x1F << 18) // (EMAC) 
+#define AT91C_EMAC_PHYA           (0x1F << 23) // (EMAC) 
+#define AT91C_EMAC_RW             (0x3 << 28) // (EMAC) 
+#define AT91C_EMAC_SOF            (0x3 << 30) // (EMAC) 
+// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
+#define AT91C_EMAC_RMII           (0x1 <<  0) // (EMAC) Reduce MII
+// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
+#define AT91C_EMAC_IP             (0xFFFF <<  0) // (EMAC) ARP request IP address
+#define AT91C_EMAC_MAG            (0x1 << 16) // (EMAC) Magic packet event enable
+#define AT91C_EMAC_ARP            (0x1 << 17) // (EMAC) ARP request event enable
+#define AT91C_EMAC_SA1            (0x1 << 18) // (EMAC) Specific address register 1 event enable
+// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
+#define AT91C_EMAC_REVREF         (0xFFFF <<  0) // (EMAC) 
+#define AT91C_EMAC_PARTREF        (0xFFFF << 16) // (EMAC) 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
+// *****************************************************************************
+// *** Register offset in AT91S_ADC structure ***
+#define ADC_CR          ( 0) // ADC Control Register
+#define ADC_MR          ( 4) // ADC Mode Register
+#define ADC_CHER        (16) // ADC Channel Enable Register
+#define ADC_CHDR        (20) // ADC Channel Disable Register
+#define ADC_CHSR        (24) // ADC Channel Status Register
+#define ADC_SR          (28) // ADC Status Register
+#define ADC_LCDR        (32) // ADC Last Converted Data Register
+#define ADC_IER         (36) // ADC Interrupt Enable Register
+#define ADC_IDR         (40) // ADC Interrupt Disable Register
+#define ADC_IMR         (44) // ADC Interrupt Mask Register
+#define ADC_CDR0        (48) // ADC Channel Data Register 0
+#define ADC_CDR1        (52) // ADC Channel Data Register 1
+#define ADC_CDR2        (56) // ADC Channel Data Register 2
+#define ADC_CDR3        (60) // ADC Channel Data Register 3
+#define ADC_CDR4        (64) // ADC Channel Data Register 4
+#define ADC_CDR5        (68) // ADC Channel Data Register 5
+#define ADC_CDR6        (72) // ADC Channel Data Register 6
+#define ADC_CDR7        (76) // ADC Channel Data Register 7
+#define ADC_RPR         (256) // Receive Pointer Register
+#define ADC_RCR         (260) // Receive Counter Register
+#define ADC_TPR         (264) // Transmit Pointer Register
+#define ADC_TCR         (268) // Transmit Counter Register
+#define ADC_RNPR        (272) // Receive Next Pointer Register
+#define ADC_RNCR        (276) // Receive Next Counter Register
+#define ADC_TNPR        (280) // Transmit Next Pointer Register
+#define ADC_TNCR        (284) // Transmit Next Counter Register
+#define ADC_PTCR        (288) // PDC Transfer Control Register
+#define ADC_PTSR        (292) // PDC Transfer Status Register
+// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
+#define AT91C_ADC_SWRST           (0x1 <<  0) // (ADC) Software Reset
+#define AT91C_ADC_START           (0x1 <<  1) // (ADC) Start Conversion
+// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
+#define AT91C_ADC_TRGEN           (0x1 <<  0) // (ADC) Trigger Enable
+#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
+#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
+#define AT91C_ADC_TRGSEL          (0x7 <<  1) // (ADC) Trigger Selection
+#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
+#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
+#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
+#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
+#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
+#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
+#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
+#define AT91C_ADC_LOWRES          (0x1 <<  4) // (ADC) Resolution.
+#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
+#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
+#define AT91C_ADC_SLEEP           (0x1 <<  5) // (ADC) Sleep Mode
+#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
+#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
+#define AT91C_ADC_PRESCAL         (0x3F <<  8) // (ADC) Prescaler rate selection
+#define AT91C_ADC_STARTUP         (0x1F << 16) // (ADC) Startup Time
+#define AT91C_ADC_SHTIM           (0xF << 24) // (ADC) Sample & Hold Time
+// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
+#define AT91C_ADC_CH0             (0x1 <<  0) // (ADC) Channel 0
+#define AT91C_ADC_CH1             (0x1 <<  1) // (ADC) Channel 1
+#define AT91C_ADC_CH2             (0x1 <<  2) // (ADC) Channel 2
+#define AT91C_ADC_CH3             (0x1 <<  3) // (ADC) Channel 3
+#define AT91C_ADC_CH4             (0x1 <<  4) // (ADC) Channel 4
+#define AT91C_ADC_CH5             (0x1 <<  5) // (ADC) Channel 5
+#define AT91C_ADC_CH6             (0x1 <<  6) // (ADC) Channel 6
+#define AT91C_ADC_CH7             (0x1 <<  7) // (ADC) Channel 7
+// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
+// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
+// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
+#define AT91C_ADC_EOC0            (0x1 <<  0) // (ADC) End of Conversion
+#define AT91C_ADC_EOC1            (0x1 <<  1) // (ADC) End of Conversion
+#define AT91C_ADC_EOC2            (0x1 <<  2) // (ADC) End of Conversion
+#define AT91C_ADC_EOC3            (0x1 <<  3) // (ADC) End of Conversion
+#define AT91C_ADC_EOC4            (0x1 <<  4) // (ADC) End of Conversion
+#define AT91C_ADC_EOC5            (0x1 <<  5) // (ADC) End of Conversion
+#define AT91C_ADC_EOC6            (0x1 <<  6) // (ADC) End of Conversion
+#define AT91C_ADC_EOC7            (0x1 <<  7) // (ADC) End of Conversion
+#define AT91C_ADC_OVRE0           (0x1 <<  8) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE1           (0x1 <<  9) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE2           (0x1 << 10) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE3           (0x1 << 11) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE4           (0x1 << 12) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE5           (0x1 << 13) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE6           (0x1 << 14) // (ADC) Overrun Error
+#define AT91C_ADC_OVRE7           (0x1 << 15) // (ADC) Overrun Error
+#define AT91C_ADC_DRDY            (0x1 << 16) // (ADC) Data Ready
+#define AT91C_ADC_GOVRE           (0x1 << 17) // (ADC) General Overrun
+#define AT91C_ADC_ENDRX           (0x1 << 18) // (ADC) End of Receiver Transfer
+#define AT91C_ADC_RXBUFF          (0x1 << 19) // (ADC) RXBUFF Interrupt
+// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
+#define AT91C_ADC_LDATA           (0x3FF <<  0) // (ADC) Last Data Converted
+// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
+// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
+// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
+// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
+#define AT91C_ADC_DATA            (0x3FF <<  0) // (ADC) Converted Data
+// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
+// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
+// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
+// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
+// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
+// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
+// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
+// *****************************************************************************
+// *** Register offset in AT91S_AES structure ***
+#define AES_CR          ( 0) // Control Register
+#define AES_MR          ( 4) // Mode Register
+#define AES_IER         (16) // Interrupt Enable Register
+#define AES_IDR         (20) // Interrupt Disable Register
+#define AES_IMR         (24) // Interrupt Mask Register
+#define AES_ISR         (28) // Interrupt Status Register
+#define AES_KEYWxR      (32) // Key Word x Register
+#define AES_IDATAxR     (64) // Input Data x Register
+#define AES_ODATAxR     (80) // Output Data x Register
+#define AES_IVxR        (96) // Initialization Vector x Register
+#define AES_VR          (252) // AES Version Register
+#define AES_RPR         (256) // Receive Pointer Register
+#define AES_RCR         (260) // Receive Counter Register
+#define AES_TPR         (264) // Transmit Pointer Register
+#define AES_TCR         (268) // Transmit Counter Register
+#define AES_RNPR        (272) // Receive Next Pointer Register
+#define AES_RNCR        (276) // Receive Next Counter Register
+#define AES_TNPR        (280) // Transmit Next Pointer Register
+#define AES_TNCR        (284) // Transmit Next Counter Register
+#define AES_PTCR        (288) // PDC Transfer Control Register
+#define AES_PTSR        (292) // PDC Transfer Status Register
+// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
+#define AT91C_AES_START           (0x1 <<  0) // (AES) Starts Processing
+#define AT91C_AES_SWRST           (0x1 <<  8) // (AES) Software Reset
+#define AT91C_AES_LOADSEED        (0x1 << 16) // (AES) Random Number Generator Seed Loading
+// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
+#define AT91C_AES_CIPHER          (0x1 <<  0) // (AES) Processing Mode
+#define AT91C_AES_PROCDLY         (0xF <<  4) // (AES) Processing Delay
+#define AT91C_AES_SMOD            (0x3 <<  8) // (AES) Start Mode
+#define 	AT91C_AES_SMOD_MANUAL               (0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
+#define 	AT91C_AES_SMOD_AUTO                 (0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
+#define 	AT91C_AES_SMOD_PDC                  (0x2 <<  8) // (AES) PDC Mode (cf datasheet).
+#define AT91C_AES_OPMOD           (0x7 << 12) // (AES) Operation Mode
+#define 	AT91C_AES_OPMOD_ECB                  (0x0 << 12) // (AES) ECB Electronic CodeBook mode.
+#define 	AT91C_AES_OPMOD_CBC                  (0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
+#define 	AT91C_AES_OPMOD_OFB                  (0x2 << 12) // (AES) OFB Output Feedback mode.
+#define 	AT91C_AES_OPMOD_CFB                  (0x3 << 12) // (AES) CFB Cipher Feedback mode.
+#define 	AT91C_AES_OPMOD_CTR                  (0x4 << 12) // (AES) CTR Counter mode.
+#define AT91C_AES_LOD             (0x1 << 15) // (AES) Last Output Data Mode
+#define AT91C_AES_CFBS            (0x7 << 16) // (AES) Cipher Feedback Data Size
+#define 	AT91C_AES_CFBS_128_BIT              (0x0 << 16) // (AES) 128-bit.
+#define 	AT91C_AES_CFBS_64_BIT               (0x1 << 16) // (AES) 64-bit.
+#define 	AT91C_AES_CFBS_32_BIT               (0x2 << 16) // (AES) 32-bit.
+#define 	AT91C_AES_CFBS_16_BIT               (0x3 << 16) // (AES) 16-bit.
+#define 	AT91C_AES_CFBS_8_BIT                (0x4 << 16) // (AES) 8-bit.
+#define AT91C_AES_CKEY            (0xF << 20) // (AES) Countermeasure Key
+#define AT91C_AES_CTYPE           (0x1F << 24) // (AES) Countermeasure Type
+#define 	AT91C_AES_CTYPE_TYPE1_EN             (0x1 << 24) // (AES) Countermeasure type 1 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE2_EN             (0x2 << 24) // (AES) Countermeasure type 2 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE3_EN             (0x4 << 24) // (AES) Countermeasure type 3 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE4_EN             (0x8 << 24) // (AES) Countermeasure type 4 is enabled.
+#define 	AT91C_AES_CTYPE_TYPE5_EN             (0x10 << 24) // (AES) Countermeasure type 5 is enabled.
+// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_AES_DATRDY          (0x1 <<  0) // (AES) DATRDY
+#define AT91C_AES_ENDRX           (0x1 <<  1) // (AES) PDC Read Buffer End
+#define AT91C_AES_ENDTX           (0x1 <<  2) // (AES) PDC Write Buffer End
+#define AT91C_AES_RXBUFF          (0x1 <<  3) // (AES) PDC Read Buffer Full
+#define AT91C_AES_TXBUFE          (0x1 <<  4) // (AES) PDC Write Buffer Empty
+#define AT91C_AES_URAD            (0x1 <<  8) // (AES) Unspecified Register Access Detection
+// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_AES_URAT            (0x7 << 12) // (AES) Unspecified Register Access Type Status
+#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing.
+#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  (0x3 << 12) // (AES) Output data register read during the sub-keys generation.
+#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation.
+#define 	AT91C_AES_URAT_WO_REG_READ          (0x5 << 12) // (AES) Write-only register read access.
+
+// *****************************************************************************
+//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
+// *****************************************************************************
+// *** Register offset in AT91S_TDES structure ***
+#define TDES_CR         ( 0) // Control Register
+#define TDES_MR         ( 4) // Mode Register
+#define TDES_IER        (16) // Interrupt Enable Register
+#define TDES_IDR        (20) // Interrupt Disable Register
+#define TDES_IMR        (24) // Interrupt Mask Register
+#define TDES_ISR        (28) // Interrupt Status Register
+#define TDES_KEY1WxR    (32) // Key 1 Word x Register
+#define TDES_KEY2WxR    (40) // Key 2 Word x Register
+#define TDES_KEY3WxR    (48) // Key 3 Word x Register
+#define TDES_IDATAxR    (64) // Input Data x Register
+#define TDES_ODATAxR    (80) // Output Data x Register
+#define TDES_IVxR       (96) // Initialization Vector x Register
+#define TDES_VR         (252) // TDES Version Register
+#define TDES_RPR        (256) // Receive Pointer Register
+#define TDES_RCR        (260) // Receive Counter Register
+#define TDES_TPR        (264) // Transmit Pointer Register
+#define TDES_TCR        (268) // Transmit Counter Register
+#define TDES_RNPR       (272) // Receive Next Pointer Register
+#define TDES_RNCR       (276) // Receive Next Counter Register
+#define TDES_TNPR       (280) // Transmit Next Pointer Register
+#define TDES_TNCR       (284) // Transmit Next Counter Register
+#define TDES_PTCR       (288) // PDC Transfer Control Register
+#define TDES_PTSR       (292) // PDC Transfer Status Register
+// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
+#define AT91C_TDES_START          (0x1 <<  0) // (TDES) Starts Processing
+#define AT91C_TDES_SWRST          (0x1 <<  8) // (TDES) Software Reset
+// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
+#define AT91C_TDES_CIPHER         (0x1 <<  0) // (TDES) Processing Mode
+#define AT91C_TDES_TDESMOD        (0x1 <<  1) // (TDES) Single or Triple DES Mode
+#define AT91C_TDES_KEYMOD         (0x1 <<  4) // (TDES) Key Mode
+#define AT91C_TDES_SMOD           (0x3 <<  8) // (TDES) Start Mode
+#define 	AT91C_TDES_SMOD_MANUAL               (0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
+#define 	AT91C_TDES_SMOD_AUTO                 (0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
+#define 	AT91C_TDES_SMOD_PDC                  (0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
+#define AT91C_TDES_OPMOD          (0x3 << 12) // (TDES) Operation Mode
+#define 	AT91C_TDES_OPMOD_ECB                  (0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
+#define 	AT91C_TDES_OPMOD_CBC                  (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
+#define 	AT91C_TDES_OPMOD_OFB                  (0x2 << 12) // (TDES) OFB Output Feedback mode.
+#define 	AT91C_TDES_OPMOD_CFB                  (0x3 << 12) // (TDES) CFB Cipher Feedback mode.
+#define AT91C_TDES_LOD            (0x1 << 15) // (TDES) Last Output Data Mode
+#define AT91C_TDES_CFBS           (0x3 << 16) // (TDES) Cipher Feedback Data Size
+#define 	AT91C_TDES_CFBS_64_BIT               (0x0 << 16) // (TDES) 64-bit.
+#define 	AT91C_TDES_CFBS_32_BIT               (0x1 << 16) // (TDES) 32-bit.
+#define 	AT91C_TDES_CFBS_16_BIT               (0x2 << 16) // (TDES) 16-bit.
+#define 	AT91C_TDES_CFBS_8_BIT                (0x3 << 16) // (TDES) 8-bit.
+// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
+#define AT91C_TDES_DATRDY         (0x1 <<  0) // (TDES) DATRDY
+#define AT91C_TDES_ENDRX          (0x1 <<  1) // (TDES) PDC Read Buffer End
+#define AT91C_TDES_ENDTX          (0x1 <<  2) // (TDES) PDC Write Buffer End
+#define AT91C_TDES_RXBUFF         (0x1 <<  3) // (TDES) PDC Read Buffer Full
+#define AT91C_TDES_TXBUFE         (0x1 <<  4) // (TDES) PDC Write Buffer Empty
+#define AT91C_TDES_URAD           (0x1 <<  8) // (TDES) Unspecified Register Access Detection
+// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
+// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
+// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
+#define AT91C_TDES_URAT           (0x3 << 12) // (TDES) Unspecified Register Access Type Status
+#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
+#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing.
+#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing.
+#define 	AT91C_TDES_URAT_WO_REG_READ          (0x3 << 12) // (TDES) Write-only register read access.
+
+// *****************************************************************************
+//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
+// *****************************************************************************
+// ========== Register definition for SYS peripheral ========== 
+// ========== Register definition for AIC peripheral ========== 
+#define AT91C_AIC_IVR             (0xFFFFF100) // (AIC) IRQ Vector Register
+#define AT91C_AIC_SMR             (0xFFFFF000) // (AIC) Source Mode Register
+#define AT91C_AIC_FVR             (0xFFFFF104) // (AIC) FIQ Vector Register
+#define AT91C_AIC_DCR             (0xFFFFF138) // (AIC) Debug Control Register (Protect)
+#define AT91C_AIC_EOICR           (0xFFFFF130) // (AIC) End of Interrupt Command Register
+#define AT91C_AIC_SVR             (0xFFFFF080) // (AIC) Source Vector Register
+#define AT91C_AIC_FFSR            (0xFFFFF148) // (AIC) Fast Forcing Status Register
+#define AT91C_AIC_ICCR            (0xFFFFF128) // (AIC) Interrupt Clear Command Register
+#define AT91C_AIC_ISR             (0xFFFFF108) // (AIC) Interrupt Status Register
+#define AT91C_AIC_IMR             (0xFFFFF110) // (AIC) Interrupt Mask Register
+#define AT91C_AIC_IPR             (0xFFFFF10C) // (AIC) Interrupt Pending Register
+#define AT91C_AIC_FFER            (0xFFFFF140) // (AIC) Fast Forcing Enable Register
+#define AT91C_AIC_IECR            (0xFFFFF120) // (AIC) Interrupt Enable Command Register
+#define AT91C_AIC_ISCR            (0xFFFFF12C) // (AIC) Interrupt Set Command Register
+#define AT91C_AIC_FFDR            (0xFFFFF144) // (AIC) Fast Forcing Disable Register
+#define AT91C_AIC_CISR            (0xFFFFF114) // (AIC) Core Interrupt Status Register
+#define AT91C_AIC_IDCR            (0xFFFFF124) // (AIC) Interrupt Disable Command Register
+#define AT91C_AIC_SPU             (0xFFFFF134) // (AIC) Spurious Vector Register
+// ========== Register definition for PDC_DBGU peripheral ========== 
+#define AT91C_DBGU_TCR            (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
+#define AT91C_DBGU_RNPR           (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
+#define AT91C_DBGU_TNPR           (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
+#define AT91C_DBGU_TPR            (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
+#define AT91C_DBGU_RPR            (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
+#define AT91C_DBGU_RCR            (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
+#define AT91C_DBGU_RNCR           (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
+#define AT91C_DBGU_PTCR           (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
+#define AT91C_DBGU_PTSR           (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
+#define AT91C_DBGU_TNCR           (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
+// ========== Register definition for DBGU peripheral ========== 
+#define AT91C_DBGU_EXID           (0xFFFFF244) // (DBGU) Chip ID Extension Register
+#define AT91C_DBGU_BRGR           (0xFFFFF220) // (DBGU) Baud Rate Generator Register
+#define AT91C_DBGU_IDR            (0xFFFFF20C) // (DBGU) Interrupt Disable Register
+#define AT91C_DBGU_CSR            (0xFFFFF214) // (DBGU) Channel Status Register
+#define AT91C_DBGU_CIDR           (0xFFFFF240) // (DBGU) Chip ID Register
+#define AT91C_DBGU_MR             (0xFFFFF204) // (DBGU) Mode Register
+#define AT91C_DBGU_IMR            (0xFFFFF210) // (DBGU) Interrupt Mask Register
+#define AT91C_DBGU_CR             (0xFFFFF200) // (DBGU) Control Register
+#define AT91C_DBGU_FNTR           (0xFFFFF248) // (DBGU) Force NTRST Register
+#define AT91C_DBGU_THR            (0xFFFFF21C) // (DBGU) Transmitter Holding Register
+#define AT91C_DBGU_RHR            (0xFFFFF218) // (DBGU) Receiver Holding Register
+#define AT91C_DBGU_IER            (0xFFFFF208) // (DBGU) Interrupt Enable Register
+// ========== Register definition for PIOA peripheral ========== 
+#define AT91C_PIOA_ODR            (0xFFFFF414) // (PIOA) Output Disable Registerr
+#define AT91C_PIOA_SODR           (0xFFFFF430) // (PIOA) Set Output Data Register
+#define AT91C_PIOA_ISR            (0xFFFFF44C) // (PIOA) Interrupt Status Register
+#define AT91C_PIOA_ABSR           (0xFFFFF478) // (PIOA) AB Select Status Register
+#define AT91C_PIOA_IER            (0xFFFFF440) // (PIOA) Interrupt Enable Register
+#define AT91C_PIOA_PPUDR          (0xFFFFF460) // (PIOA) Pull-up Disable Register
+#define AT91C_PIOA_IMR            (0xFFFFF448) // (PIOA) Interrupt Mask Register
+#define AT91C_PIOA_PER            (0xFFFFF400) // (PIOA) PIO Enable Register
+#define AT91C_PIOA_IFDR           (0xFFFFF424) // (PIOA) Input Filter Disable Register
+#define AT91C_PIOA_OWDR           (0xFFFFF4A4) // (PIOA) Output Write Disable Register
+#define AT91C_PIOA_MDSR           (0xFFFFF458) // (PIOA) Multi-driver Status Register
+#define AT91C_PIOA_IDR            (0xFFFFF444) // (PIOA) Interrupt Disable Register
+#define AT91C_PIOA_ODSR           (0xFFFFF438) // (PIOA) Output Data Status Register
+#define AT91C_PIOA_PPUSR          (0xFFFFF468) // (PIOA) Pull-up Status Register
+#define AT91C_PIOA_OWSR           (0xFFFFF4A8) // (PIOA) Output Write Status Register
+#define AT91C_PIOA_BSR            (0xFFFFF474) // (PIOA) Select B Register
+#define AT91C_PIOA_OWER           (0xFFFFF4A0) // (PIOA) Output Write Enable Register
+#define AT91C_PIOA_IFER           (0xFFFFF420) // (PIOA) Input Filter Enable Register
+#define AT91C_PIOA_PDSR           (0xFFFFF43C) // (PIOA) Pin Data Status Register
+#define AT91C_PIOA_PPUER          (0xFFFFF464) // (PIOA) Pull-up Enable Register
+#define AT91C_PIOA_OSR            (0xFFFFF418) // (PIOA) Output Status Register
+#define AT91C_PIOA_ASR            (0xFFFFF470) // (PIOA) Select A Register
+#define AT91C_PIOA_MDDR           (0xFFFFF454) // (PIOA) Multi-driver Disable Register
+#define AT91C_PIOA_CODR           (0xFFFFF434) // (PIOA) Clear Output Data Register
+#define AT91C_PIOA_MDER           (0xFFFFF450) // (PIOA) Multi-driver Enable Register
+#define AT91C_PIOA_PDR            (0xFFFFF404) // (PIOA) PIO Disable Register
+#define AT91C_PIOA_IFSR           (0xFFFFF428) // (PIOA) Input Filter Status Register
+#define AT91C_PIOA_OER            (0xFFFFF410) // (PIOA) Output Enable Register
+#define AT91C_PIOA_PSR            (0xFFFFF408) // (PIOA) PIO Status Register
+// ========== Register definition for PIOB peripheral ========== 
+#define AT91C_PIOB_OWDR           (0xFFFFF6A4) // (PIOB) Output Write Disable Register
+#define AT91C_PIOB_MDER           (0xFFFFF650) // (PIOB) Multi-driver Enable Register
+#define AT91C_PIOB_PPUSR          (0xFFFFF668) // (PIOB) Pull-up Status Register
+#define AT91C_PIOB_IMR            (0xFFFFF648) // (PIOB) Interrupt Mask Register
+#define AT91C_PIOB_ASR            (0xFFFFF670) // (PIOB) Select A Register
+#define AT91C_PIOB_PPUDR          (0xFFFFF660) // (PIOB) Pull-up Disable Register
+#define AT91C_PIOB_PSR            (0xFFFFF608) // (PIOB) PIO Status Register
+#define AT91C_PIOB_IER            (0xFFFFF640) // (PIOB) Interrupt Enable Register
+#define AT91C_PIOB_CODR           (0xFFFFF634) // (PIOB) Clear Output Data Register
+#define AT91C_PIOB_OWER           (0xFFFFF6A0) // (PIOB) Output Write Enable Register
+#define AT91C_PIOB_ABSR           (0xFFFFF678) // (PIOB) AB Select Status Register
+#define AT91C_PIOB_IFDR           (0xFFFFF624) // (PIOB) Input Filter Disable Register
+#define AT91C_PIOB_PDSR           (0xFFFFF63C) // (PIOB) Pin Data Status Register
+#define AT91C_PIOB_IDR            (0xFFFFF644) // (PIOB) Interrupt Disable Register
+#define AT91C_PIOB_OWSR           (0xFFFFF6A8) // (PIOB) Output Write Status Register
+#define AT91C_PIOB_PDR            (0xFFFFF604) // (PIOB) PIO Disable Register
+#define AT91C_PIOB_ODR            (0xFFFFF614) // (PIOB) Output Disable Registerr
+#define AT91C_PIOB_IFSR           (0xFFFFF628) // (PIOB) Input Filter Status Register
+#define AT91C_PIOB_PPUER          (0xFFFFF664) // (PIOB) Pull-up Enable Register
+#define AT91C_PIOB_SODR           (0xFFFFF630) // (PIOB) Set Output Data Register
+#define AT91C_PIOB_ISR            (0xFFFFF64C) // (PIOB) Interrupt Status Register
+#define AT91C_PIOB_ODSR           (0xFFFFF638) // (PIOB) Output Data Status Register
+#define AT91C_PIOB_OSR            (0xFFFFF618) // (PIOB) Output Status Register
+#define AT91C_PIOB_MDSR           (0xFFFFF658) // (PIOB) Multi-driver Status Register
+#define AT91C_PIOB_IFER           (0xFFFFF620) // (PIOB) Input Filter Enable Register
+#define AT91C_PIOB_BSR            (0xFFFFF674) // (PIOB) Select B Register
+#define AT91C_PIOB_MDDR           (0xFFFFF654) // (PIOB) Multi-driver Disable Register
+#define AT91C_PIOB_OER            (0xFFFFF610) // (PIOB) Output Enable Register
+#define AT91C_PIOB_PER            (0xFFFFF600) // (PIOB) PIO Enable Register
+// ========== Register definition for CKGR peripheral ========== 
+#define AT91C_CKGR_MOR            (0xFFFFFC20) // (CKGR) Main Oscillator Register
+#define AT91C_CKGR_PLLR           (0xFFFFFC2C) // (CKGR) PLL Register
+#define AT91C_CKGR_MCFR           (0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
+// ========== Register definition for PMC peripheral ========== 
+#define AT91C_PMC_IDR             (0xFFFFFC64) // (PMC) Interrupt Disable Register
+#define AT91C_PMC_MOR             (0xFFFFFC20) // (PMC) Main Oscillator Register
+#define AT91C_PMC_PLLR            (0xFFFFFC2C) // (PMC) PLL Register
+#define AT91C_PMC_PCER            (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
+#define AT91C_PMC_PCKR            (0xFFFFFC40) // (PMC) Programmable Clock Register
+#define AT91C_PMC_MCKR            (0xFFFFFC30) // (PMC) Master Clock Register
+#define AT91C_PMC_SCDR            (0xFFFFFC04) // (PMC) System Clock Disable Register
+#define AT91C_PMC_PCDR            (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
+#define AT91C_PMC_SCSR            (0xFFFFFC08) // (PMC) System Clock Status Register
+#define AT91C_PMC_PCSR            (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
+#define AT91C_PMC_MCFR            (0xFFFFFC24) // (PMC) Main Clock  Frequency Register
+#define AT91C_PMC_SCER            (0xFFFFFC00) // (PMC) System Clock Enable Register
+#define AT91C_PMC_IMR             (0xFFFFFC6C) // (PMC) Interrupt Mask Register
+#define AT91C_PMC_IER             (0xFFFFFC60) // (PMC) Interrupt Enable Register
+#define AT91C_PMC_SR              (0xFFFFFC68) // (PMC) Status Register
+// ========== Register definition for RSTC peripheral ========== 
+#define AT91C_RSTC_RCR            (0xFFFFFD00) // (RSTC) Reset Control Register
+#define AT91C_RSTC_RMR            (0xFFFFFD08) // (RSTC) Reset Mode Register
+#define AT91C_RSTC_RSR            (0xFFFFFD04) // (RSTC) Reset Status Register
+// ========== Register definition for RTTC peripheral ========== 
+#define AT91C_RTTC_RTSR           (0xFFFFFD2C) // (RTTC) Real-time Status Register
+#define AT91C_RTTC_RTMR           (0xFFFFFD20) // (RTTC) Real-time Mode Register
+#define AT91C_RTTC_RTVR           (0xFFFFFD28) // (RTTC) Real-time Value Register
+#define AT91C_RTTC_RTAR           (0xFFFFFD24) // (RTTC) Real-time Alarm Register
+// ========== Register definition for PITC peripheral ========== 
+#define AT91C_PITC_PIVR           (0xFFFFFD38) // (PITC) Period Interval Value Register
+#define AT91C_PITC_PISR           (0xFFFFFD34) // (PITC) Period Interval Status Register
+#define AT91C_PITC_PIIR           (0xFFFFFD3C) // (PITC) Period Interval Image Register
+#define AT91C_PITC_PIMR           (0xFFFFFD30) // (PITC) Period Interval Mode Register
+// ========== Register definition for WDTC peripheral ========== 
+#define AT91C_WDTC_WDCR           (0xFFFFFD40) // (WDTC) Watchdog Control Register
+#define AT91C_WDTC_WDSR           (0xFFFFFD48) // (WDTC) Watchdog Status Register
+#define AT91C_WDTC_WDMR           (0xFFFFFD44) // (WDTC) Watchdog Mode Register
+// ========== Register definition for VREG peripheral ========== 
+#define AT91C_VREG_MR             (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
+// ========== Register definition for MC peripheral ========== 
+#define AT91C_MC_ASR              (0xFFFFFF04) // (MC) MC Abort Status Register
+#define AT91C_MC_RCR              (0xFFFFFF00) // (MC) MC Remap Control Register
+#define AT91C_MC_FCR              (0xFFFFFF64) // (MC) MC Flash Command Register
+#define AT91C_MC_AASR             (0xFFFFFF08) // (MC) MC Abort Address Status Register
+#define AT91C_MC_FSR              (0xFFFFFF68) // (MC) MC Flash Status Register
+#define AT91C_MC_FMR              (0xFFFFFF60) // (MC) MC Flash Mode Register
+// ========== Register definition for PDC_SPI1 peripheral ========== 
+#define AT91C_SPI1_PTCR           (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
+#define AT91C_SPI1_RPR            (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
+#define AT91C_SPI1_TNCR           (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
+#define AT91C_SPI1_TPR            (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
+#define AT91C_SPI1_TNPR           (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
+#define AT91C_SPI1_TCR            (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
+#define AT91C_SPI1_RCR            (0xFFFE4104) // (PDC_SPI1) Receive Counter Register
+#define AT91C_SPI1_RNPR           (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
+#define AT91C_SPI1_RNCR           (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
+#define AT91C_SPI1_PTSR           (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
+// ========== Register definition for SPI1 peripheral ========== 
+#define AT91C_SPI1_IMR            (0xFFFE401C) // (SPI1) Interrupt Mask Register
+#define AT91C_SPI1_IER            (0xFFFE4014) // (SPI1) Interrupt Enable Register
+#define AT91C_SPI1_MR             (0xFFFE4004) // (SPI1) Mode Register
+#define AT91C_SPI1_RDR            (0xFFFE4008) // (SPI1) Receive Data Register
+#define AT91C_SPI1_IDR            (0xFFFE4018) // (SPI1) Interrupt Disable Register
+#define AT91C_SPI1_SR             (0xFFFE4010) // (SPI1) Status Register
+#define AT91C_SPI1_TDR            (0xFFFE400C) // (SPI1) Transmit Data Register
+#define AT91C_SPI1_CR             (0xFFFE4000) // (SPI1) Control Register
+#define AT91C_SPI1_CSR            (0xFFFE4030) // (SPI1) Chip Select Register
+// ========== Register definition for PDC_SPI0 peripheral ========== 
+#define AT91C_SPI0_PTCR           (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
+#define AT91C_SPI0_TPR            (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
+#define AT91C_SPI0_TCR            (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
+#define AT91C_SPI0_RCR            (0xFFFE0104) // (PDC_SPI0) Receive Counter Register
+#define AT91C_SPI0_PTSR           (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
+#define AT91C_SPI0_RNPR           (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
+#define AT91C_SPI0_RPR            (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
+#define AT91C_SPI0_TNCR           (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
+#define AT91C_SPI0_RNCR           (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
+#define AT91C_SPI0_TNPR           (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
+// ========== Register definition for SPI0 peripheral ========== 
+#define AT91C_SPI0_IER            (0xFFFE0014) // (SPI0) Interrupt Enable Register
+#define AT91C_SPI0_SR             (0xFFFE0010) // (SPI0) Status Register
+#define AT91C_SPI0_IDR            (0xFFFE0018) // (SPI0) Interrupt Disable Register
+#define AT91C_SPI0_CR             (0xFFFE0000) // (SPI0) Control Register
+#define AT91C_SPI0_MR             (0xFFFE0004) // (SPI0) Mode Register
+#define AT91C_SPI0_IMR            (0xFFFE001C) // (SPI0) Interrupt Mask Register
+#define AT91C_SPI0_TDR            (0xFFFE000C) // (SPI0) Transmit Data Register
+#define AT91C_SPI0_RDR            (0xFFFE0008) // (SPI0) Receive Data Register
+#define AT91C_SPI0_CSR            (0xFFFE0030) // (SPI0) Chip Select Register
+// ========== Register definition for PDC_US1 peripheral ========== 
+#define AT91C_US1_RNCR            (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
+#define AT91C_US1_PTCR            (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
+#define AT91C_US1_TCR             (0xFFFC410C) // (PDC_US1) Transmit Counter Register
+#define AT91C_US1_PTSR            (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
+#define AT91C_US1_TNPR            (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
+#define AT91C_US1_RCR             (0xFFFC4104) // (PDC_US1) Receive Counter Register
+#define AT91C_US1_RNPR            (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
+#define AT91C_US1_RPR             (0xFFFC4100) // (PDC_US1) Receive Pointer Register
+#define AT91C_US1_TNCR            (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
+#define AT91C_US1_TPR             (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
+// ========== Register definition for US1 peripheral ========== 
+#define AT91C_US1_IF              (0xFFFC404C) // (US1) IRDA_FILTER Register
+#define AT91C_US1_NER             (0xFFFC4044) // (US1) Nb Errors Register
+#define AT91C_US1_RTOR            (0xFFFC4024) // (US1) Receiver Time-out Register
+#define AT91C_US1_CSR             (0xFFFC4014) // (US1) Channel Status Register
+#define AT91C_US1_IDR             (0xFFFC400C) // (US1) Interrupt Disable Register
+#define AT91C_US1_IER             (0xFFFC4008) // (US1) Interrupt Enable Register
+#define AT91C_US1_THR             (0xFFFC401C) // (US1) Transmitter Holding Register
+#define AT91C_US1_TTGR            (0xFFFC4028) // (US1) Transmitter Time-guard Register
+#define AT91C_US1_RHR             (0xFFFC4018) // (US1) Receiver Holding Register
+#define AT91C_US1_BRGR            (0xFFFC4020) // (US1) Baud Rate Generator Register
+#define AT91C_US1_IMR             (0xFFFC4010) // (US1) Interrupt Mask Register
+#define AT91C_US1_FIDI            (0xFFFC4040) // (US1) FI_DI_Ratio Register
+#define AT91C_US1_CR              (0xFFFC4000) // (US1) Control Register
+#define AT91C_US1_MR              (0xFFFC4004) // (US1) Mode Register
+// ========== Register definition for PDC_US0 peripheral ========== 
+#define AT91C_US0_TNPR            (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
+#define AT91C_US0_RNPR            (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
+#define AT91C_US0_TCR             (0xFFFC010C) // (PDC_US0) Transmit Counter Register
+#define AT91C_US0_PTCR            (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
+#define AT91C_US0_PTSR            (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
+#define AT91C_US0_TNCR            (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
+#define AT91C_US0_TPR             (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
+#define AT91C_US0_RCR             (0xFFFC0104) // (PDC_US0) Receive Counter Register
+#define AT91C_US0_RPR             (0xFFFC0100) // (PDC_US0) Receive Pointer Register
+#define AT91C_US0_RNCR            (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
+// ========== Register definition for US0 peripheral ========== 
+#define AT91C_US0_BRGR            (0xFFFC0020) // (US0) Baud Rate Generator Register
+#define AT91C_US0_NER             (0xFFFC0044) // (US0) Nb Errors Register
+#define AT91C_US0_CR              (0xFFFC0000) // (US0) Control Register
+#define AT91C_US0_IMR             (0xFFFC0010) // (US0) Interrupt Mask Register
+#define AT91C_US0_FIDI            (0xFFFC0040) // (US0) FI_DI_Ratio Register
+#define AT91C_US0_TTGR            (0xFFFC0028) // (US0) Transmitter Time-guard Register
+#define AT91C_US0_MR              (0xFFFC0004) // (US0) Mode Register
+#define AT91C_US0_RTOR            (0xFFFC0024) // (US0) Receiver Time-out Register
+#define AT91C_US0_CSR             (0xFFFC0014) // (US0) Channel Status Register
+#define AT91C_US0_RHR             (0xFFFC0018) // (US0) Receiver Holding Register
+#define AT91C_US0_IDR             (0xFFFC000C) // (US0) Interrupt Disable Register
+#define AT91C_US0_THR             (0xFFFC001C) // (US0) Transmitter Holding Register
+#define AT91C_US0_IF              (0xFFFC004C) // (US0) IRDA_FILTER Register
+#define AT91C_US0_IER             (0xFFFC0008) // (US0) Interrupt Enable Register
+// ========== Register definition for PDC_SSC peripheral ========== 
+#define AT91C_SSC_TNCR            (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
+#define AT91C_SSC_RPR             (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
+#define AT91C_SSC_RNCR            (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
+#define AT91C_SSC_TPR             (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
+#define AT91C_SSC_PTCR            (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
+#define AT91C_SSC_TCR             (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
+#define AT91C_SSC_RCR             (0xFFFD4104) // (PDC_SSC) Receive Counter Register
+#define AT91C_SSC_RNPR            (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
+#define AT91C_SSC_TNPR            (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
+#define AT91C_SSC_PTSR            (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
+// ========== Register definition for SSC peripheral ========== 
+#define AT91C_SSC_RHR             (0xFFFD4020) // (SSC) Receive Holding Register
+#define AT91C_SSC_RSHR            (0xFFFD4030) // (SSC) Receive Sync Holding Register
+#define AT91C_SSC_TFMR            (0xFFFD401C) // (SSC) Transmit Frame Mode Register
+#define AT91C_SSC_IDR             (0xFFFD4048) // (SSC) Interrupt Disable Register
+#define AT91C_SSC_THR             (0xFFFD4024) // (SSC) Transmit Holding Register
+#define AT91C_SSC_RCMR            (0xFFFD4010) // (SSC) Receive Clock ModeRegister
+#define AT91C_SSC_IER             (0xFFFD4044) // (SSC) Interrupt Enable Register
+#define AT91C_SSC_TSHR            (0xFFFD4034) // (SSC) Transmit Sync Holding Register
+#define AT91C_SSC_SR              (0xFFFD4040) // (SSC) Status Register
+#define AT91C_SSC_CMR             (0xFFFD4004) // (SSC) Clock Mode Register
+#define AT91C_SSC_TCMR            (0xFFFD4018) // (SSC) Transmit Clock Mode Register
+#define AT91C_SSC_CR              (0xFFFD4000) // (SSC) Control Register
+#define AT91C_SSC_IMR             (0xFFFD404C) // (SSC) Interrupt Mask Register
+#define AT91C_SSC_RFMR            (0xFFFD4014) // (SSC) Receive Frame Mode Register
+// ========== Register definition for TWI peripheral ========== 
+#define AT91C_TWI_IER             (0xFFFB8024) // (TWI) Interrupt Enable Register
+#define AT91C_TWI_CR              (0xFFFB8000) // (TWI) Control Register
+#define AT91C_TWI_SR              (0xFFFB8020) // (TWI) Status Register
+#define AT91C_TWI_IMR             (0xFFFB802C) // (TWI) Interrupt Mask Register
+#define AT91C_TWI_THR             (0xFFFB8034) // (TWI) Transmit Holding Register
+#define AT91C_TWI_IDR             (0xFFFB8028) // (TWI) Interrupt Disable Register
+#define AT91C_TWI_IADR            (0xFFFB800C) // (TWI) Internal Address Register
+#define AT91C_TWI_MMR             (0xFFFB8004) // (TWI) Master Mode Register
+#define AT91C_TWI_CWGR            (0xFFFB8010) // (TWI) Clock Waveform Generator Register
+#define AT91C_TWI_RHR             (0xFFFB8030) // (TWI) Receive Holding Register
+// ========== Register definition for PWMC_CH3 peripheral ========== 
+#define AT91C_PWMC_CH3_CUPDR      (0xFFFCC270) // (PWMC_CH3) Channel Update Register
+#define AT91C_PWMC_CH3_Reserved   (0xFFFCC274) // (PWMC_CH3) Reserved
+#define AT91C_PWMC_CH3_CPRDR      (0xFFFCC268) // (PWMC_CH3) Channel Period Register
+#define AT91C_PWMC_CH3_CDTYR      (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
+#define AT91C_PWMC_CH3_CCNTR      (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
+#define AT91C_PWMC_CH3_CMR        (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
+// ========== Register definition for PWMC_CH2 peripheral ========== 
+#define AT91C_PWMC_CH2_Reserved   (0xFFFCC254) // (PWMC_CH2) Reserved
+#define AT91C_PWMC_CH2_CMR        (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
+#define AT91C_PWMC_CH2_CCNTR      (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
+#define AT91C_PWMC_CH2_CPRDR      (0xFFFCC248) // (PWMC_CH2) Channel Period Register
+#define AT91C_PWMC_CH2_CUPDR      (0xFFFCC250) // (PWMC_CH2) Channel Update Register
+#define AT91C_PWMC_CH2_CDTYR      (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
+// ========== Register definition for PWMC_CH1 peripheral ========== 
+#define AT91C_PWMC_CH1_Reserved   (0xFFFCC234) // (PWMC_CH1) Reserved
+#define AT91C_PWMC_CH1_CUPDR      (0xFFFCC230) // (PWMC_CH1) Channel Update Register
+#define AT91C_PWMC_CH1_CPRDR      (0xFFFCC228) // (PWMC_CH1) Channel Period Register
+#define AT91C_PWMC_CH1_CCNTR      (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
+#define AT91C_PWMC_CH1_CDTYR      (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
+#define AT91C_PWMC_CH1_CMR        (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
+// ========== Register definition for PWMC_CH0 peripheral ========== 
+#define AT91C_PWMC_CH0_Reserved   (0xFFFCC214) // (PWMC_CH0) Reserved
+#define AT91C_PWMC_CH0_CPRDR      (0xFFFCC208) // (PWMC_CH0) Channel Period Register
+#define AT91C_PWMC_CH0_CDTYR      (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
+#define AT91C_PWMC_CH0_CMR        (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
+#define AT91C_PWMC_CH0_CUPDR      (0xFFFCC210) // (PWMC_CH0) Channel Update Register
+#define AT91C_PWMC_CH0_CCNTR      (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
+// ========== Register definition for PWMC peripheral ========== 
+#define AT91C_PWMC_IDR            (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
+#define AT91C_PWMC_DIS            (0xFFFCC008) // (PWMC) PWMC Disable Register
+#define AT91C_PWMC_IER            (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
+#define AT91C_PWMC_VR             (0xFFFCC0FC) // (PWMC) PWMC Version Register
+#define AT91C_PWMC_ISR            (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
+#define AT91C_PWMC_SR             (0xFFFCC00C) // (PWMC) PWMC Status Register
+#define AT91C_PWMC_IMR            (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
+#define AT91C_PWMC_MR             (0xFFFCC000) // (PWMC) PWMC Mode Register
+#define AT91C_PWMC_ENA            (0xFFFCC004) // (PWMC) PWMC Enable Register
+// ========== Register definition for UDP peripheral ========== 
+#define AT91C_UDP_IMR             (0xFFFB0018) // (UDP) Interrupt Mask Register
+#define AT91C_UDP_FADDR           (0xFFFB0008) // (UDP) Function Address Register
+#define AT91C_UDP_NUM             (0xFFFB0000) // (UDP) Frame Number Register
+#define AT91C_UDP_FDR             (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
+#define AT91C_UDP_ISR             (0xFFFB001C) // (UDP) Interrupt Status Register
+#define AT91C_UDP_CSR             (0xFFFB0030) // (UDP) Endpoint Control and Status Register
+#define AT91C_UDP_IDR             (0xFFFB0014) // (UDP) Interrupt Disable Register
+#define AT91C_UDP_ICR             (0xFFFB0020) // (UDP) Interrupt Clear Register
+#define AT91C_UDP_RSTEP           (0xFFFB0028) // (UDP) Reset Endpoint Register
+#define AT91C_UDP_TXVC            (0xFFFB0074) // (UDP) Transceiver Control Register
+#define AT91C_UDP_GLBSTATE        (0xFFFB0004) // (UDP) Global State Register
+#define AT91C_UDP_IER             (0xFFFB0010) // (UDP) Interrupt Enable Register
+// ========== Register definition for TC0 peripheral ========== 
+#define AT91C_TC0_SR              (0xFFFA0020) // (TC0) Status Register
+#define AT91C_TC0_RC              (0xFFFA001C) // (TC0) Register C
+#define AT91C_TC0_RB              (0xFFFA0018) // (TC0) Register B
+#define AT91C_TC0_CCR             (0xFFFA0000) // (TC0) Channel Control Register
+#define AT91C_TC0_CMR             (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC0_IER             (0xFFFA0024) // (TC0) Interrupt Enable Register
+#define AT91C_TC0_RA              (0xFFFA0014) // (TC0) Register A
+#define AT91C_TC0_IDR             (0xFFFA0028) // (TC0) Interrupt Disable Register
+#define AT91C_TC0_CV              (0xFFFA0010) // (TC0) Counter Value
+#define AT91C_TC0_IMR             (0xFFFA002C) // (TC0) Interrupt Mask Register
+// ========== Register definition for TC1 peripheral ========== 
+#define AT91C_TC1_RB              (0xFFFA0058) // (TC1) Register B
+#define AT91C_TC1_CCR             (0xFFFA0040) // (TC1) Channel Control Register
+#define AT91C_TC1_IER             (0xFFFA0064) // (TC1) Interrupt Enable Register
+#define AT91C_TC1_IDR             (0xFFFA0068) // (TC1) Interrupt Disable Register
+#define AT91C_TC1_SR              (0xFFFA0060) // (TC1) Status Register
+#define AT91C_TC1_CMR             (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC1_RA              (0xFFFA0054) // (TC1) Register A
+#define AT91C_TC1_RC              (0xFFFA005C) // (TC1) Register C
+#define AT91C_TC1_IMR             (0xFFFA006C) // (TC1) Interrupt Mask Register
+#define AT91C_TC1_CV              (0xFFFA0050) // (TC1) Counter Value
+// ========== Register definition for TC2 peripheral ========== 
+#define AT91C_TC2_CMR             (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
+#define AT91C_TC2_CCR             (0xFFFA0080) // (TC2) Channel Control Register
+#define AT91C_TC2_CV              (0xFFFA0090) // (TC2) Counter Value
+#define AT91C_TC2_RA              (0xFFFA0094) // (TC2) Register A
+#define AT91C_TC2_RB              (0xFFFA0098) // (TC2) Register B
+#define AT91C_TC2_IDR             (0xFFFA00A8) // (TC2) Interrupt Disable Register
+#define AT91C_TC2_IMR             (0xFFFA00AC) // (TC2) Interrupt Mask Register
+#define AT91C_TC2_RC              (0xFFFA009C) // (TC2) Register C
+#define AT91C_TC2_IER             (0xFFFA00A4) // (TC2) Interrupt Enable Register
+#define AT91C_TC2_SR              (0xFFFA00A0) // (TC2) Status Register
+// ========== Register definition for TCB peripheral ========== 
+#define AT91C_TCB_BMR             (0xFFFA00C4) // (TCB) TC Block Mode Register
+#define AT91C_TCB_BCR             (0xFFFA00C0) // (TCB) TC Block Control Register
+// ========== Register definition for CAN_MB0 peripheral ========== 
+#define AT91C_CAN_MB0_MDL         (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
+#define AT91C_CAN_MB0_MAM         (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB0_MCR         (0xFFFD021C) // (CAN_MB0) MailBox Control Register
+#define AT91C_CAN_MB0_MID         (0xFFFD0208) // (CAN_MB0) MailBox ID Register
+#define AT91C_CAN_MB0_MSR         (0xFFFD0210) // (CAN_MB0) MailBox Status Register
+#define AT91C_CAN_MB0_MFID        (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
+#define AT91C_CAN_MB0_MDH         (0xFFFD0218) // (CAN_MB0) MailBox Data High Register
+#define AT91C_CAN_MB0_MMR         (0xFFFD0200) // (CAN_MB0) MailBox Mode Register
+// ========== Register definition for CAN_MB1 peripheral ========== 
+#define AT91C_CAN_MB1_MDL         (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
+#define AT91C_CAN_MB1_MID         (0xFFFD0228) // (CAN_MB1) MailBox ID Register
+#define AT91C_CAN_MB1_MMR         (0xFFFD0220) // (CAN_MB1) MailBox Mode Register
+#define AT91C_CAN_MB1_MSR         (0xFFFD0230) // (CAN_MB1) MailBox Status Register
+#define AT91C_CAN_MB1_MAM         (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB1_MDH         (0xFFFD0238) // (CAN_MB1) MailBox Data High Register
+#define AT91C_CAN_MB1_MCR         (0xFFFD023C) // (CAN_MB1) MailBox Control Register
+#define AT91C_CAN_MB1_MFID        (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
+// ========== Register definition for CAN_MB2 peripheral ========== 
+#define AT91C_CAN_MB2_MCR         (0xFFFD025C) // (CAN_MB2) MailBox Control Register
+#define AT91C_CAN_MB2_MDH         (0xFFFD0258) // (CAN_MB2) MailBox Data High Register
+#define AT91C_CAN_MB2_MID         (0xFFFD0248) // (CAN_MB2) MailBox ID Register
+#define AT91C_CAN_MB2_MDL         (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
+#define AT91C_CAN_MB2_MMR         (0xFFFD0240) // (CAN_MB2) MailBox Mode Register
+#define AT91C_CAN_MB2_MAM         (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB2_MFID        (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
+#define AT91C_CAN_MB2_MSR         (0xFFFD0250) // (CAN_MB2) MailBox Status Register
+// ========== Register definition for CAN_MB3 peripheral ========== 
+#define AT91C_CAN_MB3_MFID        (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
+#define AT91C_CAN_MB3_MAM         (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB3_MID         (0xFFFD0268) // (CAN_MB3) MailBox ID Register
+#define AT91C_CAN_MB3_MCR         (0xFFFD027C) // (CAN_MB3) MailBox Control Register
+#define AT91C_CAN_MB3_MMR         (0xFFFD0260) // (CAN_MB3) MailBox Mode Register
+#define AT91C_CAN_MB3_MSR         (0xFFFD0270) // (CAN_MB3) MailBox Status Register
+#define AT91C_CAN_MB3_MDL         (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
+#define AT91C_CAN_MB3_MDH         (0xFFFD0278) // (CAN_MB3) MailBox Data High Register
+// ========== Register definition for CAN_MB4 peripheral ========== 
+#define AT91C_CAN_MB4_MID         (0xFFFD0288) // (CAN_MB4) MailBox ID Register
+#define AT91C_CAN_MB4_MMR         (0xFFFD0280) // (CAN_MB4) MailBox Mode Register
+#define AT91C_CAN_MB4_MDH         (0xFFFD0298) // (CAN_MB4) MailBox Data High Register
+#define AT91C_CAN_MB4_MFID        (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
+#define AT91C_CAN_MB4_MSR         (0xFFFD0290) // (CAN_MB4) MailBox Status Register
+#define AT91C_CAN_MB4_MCR         (0xFFFD029C) // (CAN_MB4) MailBox Control Register
+#define AT91C_CAN_MB4_MDL         (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
+#define AT91C_CAN_MB4_MAM         (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB5 peripheral ========== 
+#define AT91C_CAN_MB5_MSR         (0xFFFD02B0) // (CAN_MB5) MailBox Status Register
+#define AT91C_CAN_MB5_MCR         (0xFFFD02BC) // (CAN_MB5) MailBox Control Register
+#define AT91C_CAN_MB5_MFID        (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
+#define AT91C_CAN_MB5_MDH         (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
+#define AT91C_CAN_MB5_MID         (0xFFFD02A8) // (CAN_MB5) MailBox ID Register
+#define AT91C_CAN_MB5_MMR         (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
+#define AT91C_CAN_MB5_MDL         (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
+#define AT91C_CAN_MB5_MAM         (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
+// ========== Register definition for CAN_MB6 peripheral ========== 
+#define AT91C_CAN_MB6_MFID        (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
+#define AT91C_CAN_MB6_MID         (0xFFFD02C8) // (CAN_MB6) MailBox ID Register
+#define AT91C_CAN_MB6_MAM         (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB6_MSR         (0xFFFD02D0) // (CAN_MB6) MailBox Status Register
+#define AT91C_CAN_MB6_MDL         (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
+#define AT91C_CAN_MB6_MCR         (0xFFFD02DC) // (CAN_MB6) MailBox Control Register
+#define AT91C_CAN_MB6_MDH         (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
+#define AT91C_CAN_MB6_MMR         (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
+// ========== Register definition for CAN_MB7 peripheral ========== 
+#define AT91C_CAN_MB7_MCR         (0xFFFD02FC) // (CAN_MB7) MailBox Control Register
+#define AT91C_CAN_MB7_MDH         (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
+#define AT91C_CAN_MB7_MFID        (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
+#define AT91C_CAN_MB7_MDL         (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
+#define AT91C_CAN_MB7_MID         (0xFFFD02E8) // (CAN_MB7) MailBox ID Register
+#define AT91C_CAN_MB7_MMR         (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
+#define AT91C_CAN_MB7_MAM         (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
+#define AT91C_CAN_MB7_MSR         (0xFFFD02F0) // (CAN_MB7) MailBox Status Register
+// ========== Register definition for CAN peripheral ========== 
+#define AT91C_CAN_TCR             (0xFFFD0024) // (CAN) Transfer Command Register
+#define AT91C_CAN_IMR             (0xFFFD000C) // (CAN) Interrupt Mask Register
+#define AT91C_CAN_IER             (0xFFFD0004) // (CAN) Interrupt Enable Register
+#define AT91C_CAN_ECR             (0xFFFD0020) // (CAN) Error Counter Register
+#define AT91C_CAN_TIMESTP         (0xFFFD001C) // (CAN) Time Stamp Register
+#define AT91C_CAN_MR              (0xFFFD0000) // (CAN) Mode Register
+#define AT91C_CAN_IDR             (0xFFFD0008) // (CAN) Interrupt Disable Register
+#define AT91C_CAN_ACR             (0xFFFD0028) // (CAN) Abort Command Register
+#define AT91C_CAN_TIM             (0xFFFD0018) // (CAN) Timer Register
+#define AT91C_CAN_SR              (0xFFFD0010) // (CAN) Status Register
+#define AT91C_CAN_BR              (0xFFFD0014) // (CAN) Baudrate Register
+#define AT91C_CAN_VR              (0xFFFD00FC) // (CAN) Version Register
+// ========== Register definition for EMAC peripheral ========== 
+#define AT91C_EMAC_ISR            (0xFFFDC024) // (EMAC) Interrupt Status Register
+#define AT91C_EMAC_SA4H           (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
+#define AT91C_EMAC_SA1L           (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
+#define AT91C_EMAC_ELE            (0xFFFDC078) // (EMAC) Excessive Length Errors Register
+#define AT91C_EMAC_LCOL           (0xFFFDC05C) // (EMAC) Late Collision Register
+#define AT91C_EMAC_RLE            (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
+#define AT91C_EMAC_WOL            (0xFFFDC0C4) // (EMAC) Wake On LAN Register
+#define AT91C_EMAC_DTF            (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
+#define AT91C_EMAC_TUND           (0xFFFDC064) // (EMAC) Transmit Underrun Error Register
+#define AT91C_EMAC_NCR            (0xFFFDC000) // (EMAC) Network Control Register
+#define AT91C_EMAC_SA4L           (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
+#define AT91C_EMAC_RSR            (0xFFFDC020) // (EMAC) Receive Status Register
+#define AT91C_EMAC_SA3L           (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
+#define AT91C_EMAC_TSR            (0xFFFDC014) // (EMAC) Transmit Status Register
+#define AT91C_EMAC_IDR            (0xFFFDC02C) // (EMAC) Interrupt Disable Register
+#define AT91C_EMAC_RSE            (0xFFFDC074) // (EMAC) Receive Symbol Errors Register
+#define AT91C_EMAC_ECOL           (0xFFFDC060) // (EMAC) Excessive Collision Register
+#define AT91C_EMAC_TID            (0xFFFDC0B8) // (EMAC) Type ID Checking Register
+#define AT91C_EMAC_HRB            (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
+#define AT91C_EMAC_TBQP           (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
+#define AT91C_EMAC_USRIO          (0xFFFDC0C0) // (EMAC) USER Input/Output Register
+#define AT91C_EMAC_PTR            (0xFFFDC038) // (EMAC) Pause Time Register
+#define AT91C_EMAC_SA2H           (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
+#define AT91C_EMAC_ROV            (0xFFFDC070) // (EMAC) Receive Overrun Errors Register
+#define AT91C_EMAC_ALE            (0xFFFDC054) // (EMAC) Alignment Error Register
+#define AT91C_EMAC_RJA            (0xFFFDC07C) // (EMAC) Receive Jabbers Register
+#define AT91C_EMAC_RBQP           (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
+#define AT91C_EMAC_TPF            (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
+#define AT91C_EMAC_NCFGR          (0xFFFDC004) // (EMAC) Network Configuration Register
+#define AT91C_EMAC_HRT            (0xFFFDC094) // (EMAC) Hash Address Top[63:32]
+#define AT91C_EMAC_USF            (0xFFFDC080) // (EMAC) Undersize Frames Register
+#define AT91C_EMAC_FCSE           (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
+#define AT91C_EMAC_TPQ            (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
+#define AT91C_EMAC_MAN            (0xFFFDC034) // (EMAC) PHY Maintenance Register
+#define AT91C_EMAC_FTO            (0xFFFDC040) // (EMAC) Frames Transmitted OK Register
+#define AT91C_EMAC_REV            (0xFFFDC0FC) // (EMAC) Revision Register
+#define AT91C_EMAC_IMR            (0xFFFDC030) // (EMAC) Interrupt Mask Register
+#define AT91C_EMAC_SCF            (0xFFFDC044) // (EMAC) Single Collision Frame Register
+#define AT91C_EMAC_PFR            (0xFFFDC03C) // (EMAC) Pause Frames received Register
+#define AT91C_EMAC_MCF            (0xFFFDC048) // (EMAC) Multiple Collision Frame Register
+#define AT91C_EMAC_NSR            (0xFFFDC008) // (EMAC) Network Status Register
+#define AT91C_EMAC_SA2L           (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
+#define AT91C_EMAC_FRO            (0xFFFDC04C) // (EMAC) Frames Received OK Register
+#define AT91C_EMAC_IER            (0xFFFDC028) // (EMAC) Interrupt Enable Register
+#define AT91C_EMAC_SA1H           (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
+#define AT91C_EMAC_CSE            (0xFFFDC068) // (EMAC) Carrier Sense Error Register
+#define AT91C_EMAC_SA3H           (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
+#define AT91C_EMAC_RRE            (0xFFFDC06C) // (EMAC) Receive Ressource Error Register
+#define AT91C_EMAC_STE            (0xFFFDC084) // (EMAC) SQE Test Error Register
+// ========== Register definition for PDC_ADC peripheral ========== 
+#define AT91C_ADC_PTSR            (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
+#define AT91C_ADC_PTCR            (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
+#define AT91C_ADC_TNPR            (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
+#define AT91C_ADC_TNCR            (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
+#define AT91C_ADC_RNPR            (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
+#define AT91C_ADC_RNCR            (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
+#define AT91C_ADC_RPR             (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
+#define AT91C_ADC_TCR             (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
+#define AT91C_ADC_TPR             (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
+#define AT91C_ADC_RCR             (0xFFFD8104) // (PDC_ADC) Receive Counter Register
+// ========== Register definition for ADC peripheral ========== 
+#define AT91C_ADC_CDR2            (0xFFFD8038) // (ADC) ADC Channel Data Register 2
+#define AT91C_ADC_CDR3            (0xFFFD803C) // (ADC) ADC Channel Data Register 3
+#define AT91C_ADC_CDR0            (0xFFFD8030) // (ADC) ADC Channel Data Register 0
+#define AT91C_ADC_CDR5            (0xFFFD8044) // (ADC) ADC Channel Data Register 5
+#define AT91C_ADC_CHDR            (0xFFFD8014) // (ADC) ADC Channel Disable Register
+#define AT91C_ADC_SR              (0xFFFD801C) // (ADC) ADC Status Register
+#define AT91C_ADC_CDR4            (0xFFFD8040) // (ADC) ADC Channel Data Register 4
+#define AT91C_ADC_CDR1            (0xFFFD8034) // (ADC) ADC Channel Data Register 1
+#define AT91C_ADC_LCDR            (0xFFFD8020) // (ADC) ADC Last Converted Data Register
+#define AT91C_ADC_IDR             (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
+#define AT91C_ADC_CR              (0xFFFD8000) // (ADC) ADC Control Register
+#define AT91C_ADC_CDR7            (0xFFFD804C) // (ADC) ADC Channel Data Register 7
+#define AT91C_ADC_CDR6            (0xFFFD8048) // (ADC) ADC Channel Data Register 6
+#define AT91C_ADC_IER             (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
+#define AT91C_ADC_CHER            (0xFFFD8010) // (ADC) ADC Channel Enable Register
+#define AT91C_ADC_CHSR            (0xFFFD8018) // (ADC) ADC Channel Status Register
+#define AT91C_ADC_MR              (0xFFFD8004) // (ADC) ADC Mode Register
+#define AT91C_ADC_IMR             (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
+// ========== Register definition for PDC_AES peripheral ========== 
+#define AT91C_AES_TPR             (0xFFFA4108) // (PDC_AES) Transmit Pointer Register
+#define AT91C_AES_PTCR            (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
+#define AT91C_AES_RNPR            (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
+#define AT91C_AES_TNCR            (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
+#define AT91C_AES_TCR             (0xFFFA410C) // (PDC_AES) Transmit Counter Register
+#define AT91C_AES_RCR             (0xFFFA4104) // (PDC_AES) Receive Counter Register
+#define AT91C_AES_RNCR            (0xFFFA4114) // (PDC_AES) Receive Next Counter Register
+#define AT91C_AES_TNPR            (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
+#define AT91C_AES_RPR             (0xFFFA4100) // (PDC_AES) Receive Pointer Register
+#define AT91C_AES_PTSR            (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
+// ========== Register definition for AES peripheral ========== 
+#define AT91C_AES_IVxR            (0xFFFA4060) // (AES) Initialization Vector x Register
+#define AT91C_AES_MR              (0xFFFA4004) // (AES) Mode Register
+#define AT91C_AES_VR              (0xFFFA40FC) // (AES) AES Version Register
+#define AT91C_AES_ODATAxR         (0xFFFA4050) // (AES) Output Data x Register
+#define AT91C_AES_IDATAxR         (0xFFFA4040) // (AES) Input Data x Register
+#define AT91C_AES_CR              (0xFFFA4000) // (AES) Control Register
+#define AT91C_AES_IDR             (0xFFFA4014) // (AES) Interrupt Disable Register
+#define AT91C_AES_IMR             (0xFFFA4018) // (AES) Interrupt Mask Register
+#define AT91C_AES_IER             (0xFFFA4010) // (AES) Interrupt Enable Register
+#define AT91C_AES_KEYWxR          (0xFFFA4020) // (AES) Key Word x Register
+#define AT91C_AES_ISR             (0xFFFA401C) // (AES) Interrupt Status Register
+// ========== Register definition for PDC_TDES peripheral ========== 
+#define AT91C_TDES_RNCR           (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
+#define AT91C_TDES_TCR            (0xFFFA810C) // (PDC_TDES) Transmit Counter Register
+#define AT91C_TDES_RCR            (0xFFFA8104) // (PDC_TDES) Receive Counter Register
+#define AT91C_TDES_TNPR           (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
+#define AT91C_TDES_RNPR           (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
+#define AT91C_TDES_RPR            (0xFFFA8100) // (PDC_TDES) Receive Pointer Register
+#define AT91C_TDES_TNCR           (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
+#define AT91C_TDES_TPR            (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
+#define AT91C_TDES_PTSR           (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
+#define AT91C_TDES_PTCR           (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
+// ========== Register definition for TDES peripheral ========== 
+#define AT91C_TDES_KEY2WxR        (0xFFFA8028) // (TDES) Key 2 Word x Register
+#define AT91C_TDES_KEY3WxR        (0xFFFA8030) // (TDES) Key 3 Word x Register
+#define AT91C_TDES_IDR            (0xFFFA8014) // (TDES) Interrupt Disable Register
+#define AT91C_TDES_VR             (0xFFFA80FC) // (TDES) TDES Version Register
+#define AT91C_TDES_IVxR           (0xFFFA8060) // (TDES) Initialization Vector x Register
+#define AT91C_TDES_ODATAxR        (0xFFFA8050) // (TDES) Output Data x Register
+#define AT91C_TDES_IMR            (0xFFFA8018) // (TDES) Interrupt Mask Register
+#define AT91C_TDES_MR             (0xFFFA8004) // (TDES) Mode Register
+#define AT91C_TDES_CR             (0xFFFA8000) // (TDES) Control Register
+#define AT91C_TDES_IER            (0xFFFA8010) // (TDES) Interrupt Enable Register
+#define AT91C_TDES_ISR            (0xFFFA801C) // (TDES) Interrupt Status Register
+#define AT91C_TDES_IDATAxR        (0xFFFA8040) // (TDES) Input Data x Register
+#define AT91C_TDES_KEY1WxR        (0xFFFA8020) // (TDES) Key 1 Word x Register
+
+// *****************************************************************************
+//               PIO DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_PIO_PA0             (1 <<  0) // Pin Controlled by PA0
+#define AT91C_PA0_RXD0            (AT91C_PIO_PA0) //  USART 0 Receive Data
+#define AT91C_PIO_PA1             (1 <<  1) // Pin Controlled by PA1
+#define AT91C_PA1_TXD0            (AT91C_PIO_PA1) //  USART 0 Transmit Data
+#define AT91C_PIO_PA10            (1 << 10) // Pin Controlled by PA10
+#define AT91C_PA10_TWD            (AT91C_PIO_PA10) //  TWI Two-wire Serial Data
+#define AT91C_PIO_PA11            (1 << 11) // Pin Controlled by PA11
+#define AT91C_PA11_TWCK           (AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
+#define AT91C_PIO_PA12            (1 << 12) // Pin Controlled by PA12
+#define AT91C_PA12_NPCS00         (AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
+#define AT91C_PIO_PA13            (1 << 13) // Pin Controlled by PA13
+#define AT91C_PA13_NPCS01         (AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PA13_PCK1           (AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PA14            (1 << 14) // Pin Controlled by PA14
+#define AT91C_PA14_NPCS02         (AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PA14_IRQ1           (AT91C_PIO_PA14) //  External Interrupt 1
+#define AT91C_PIO_PA15            (1 << 15) // Pin Controlled by PA15
+#define AT91C_PA15_NPCS03         (AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PA15_TCLK2          (AT91C_PIO_PA15) //  Timer Counter 2 external clock input
+#define AT91C_PIO_PA16            (1 << 16) // Pin Controlled by PA16
+#define AT91C_PA16_MISO0          (AT91C_PIO_PA16) //  SPI 0 Master In Slave
+#define AT91C_PIO_PA17            (1 << 17) // Pin Controlled by PA17
+#define AT91C_PA17_MOSI0          (AT91C_PIO_PA17) //  SPI 0 Master Out Slave
+#define AT91C_PIO_PA18            (1 << 18) // Pin Controlled by PA18
+#define AT91C_PA18_SPCK0          (AT91C_PIO_PA18) //  SPI 0 Serial Clock
+#define AT91C_PIO_PA19            (1 << 19) // Pin Controlled by PA19
+#define AT91C_PA19_CANRX          (AT91C_PIO_PA19) //  CAN Receive
+#define AT91C_PIO_PA2             (1 <<  2) // Pin Controlled by PA2
+#define AT91C_PA2_SCK0            (AT91C_PIO_PA2) //  USART 0 Serial Clock
+#define AT91C_PA2_NPCS11          (AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA20            (1 << 20) // Pin Controlled by PA20
+#define AT91C_PA20_CANTX          (AT91C_PIO_PA20) //  CAN Transmit
+#define AT91C_PIO_PA21            (1 << 21) // Pin Controlled by PA21
+#define AT91C_PA21_TF             (AT91C_PIO_PA21) //  SSC Transmit Frame Sync
+#define AT91C_PA21_NPCS10         (AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
+#define AT91C_PIO_PA22            (1 << 22) // Pin Controlled by PA22
+#define AT91C_PA22_TK             (AT91C_PIO_PA22) //  SSC Transmit Clock
+#define AT91C_PA22_SPCK1          (AT91C_PIO_PA22) //  SPI 1 Serial Clock
+#define AT91C_PIO_PA23            (1 << 23) // Pin Controlled by PA23
+#define AT91C_PA23_TD             (AT91C_PIO_PA23) //  SSC Transmit data
+#define AT91C_PA23_MOSI1          (AT91C_PIO_PA23) //  SPI 1 Master Out Slave
+#define AT91C_PIO_PA24            (1 << 24) // Pin Controlled by PA24
+#define AT91C_PA24_RD             (AT91C_PIO_PA24) //  SSC Receive Data
+#define AT91C_PA24_MISO1          (AT91C_PIO_PA24) //  SPI 1 Master In Slave
+#define AT91C_PIO_PA25            (1 << 25) // Pin Controlled by PA25
+#define AT91C_PA25_RK             (AT91C_PIO_PA25) //  SSC Receive Clock
+#define AT91C_PA25_NPCS11         (AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PA26            (1 << 26) // Pin Controlled by PA26
+#define AT91C_PA26_RF             (AT91C_PIO_PA26) //  SSC Receive Frame Sync
+#define AT91C_PA26_NPCS12         (AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA27            (1 << 27) // Pin Controlled by PA27
+#define AT91C_PA27_DRXD           (AT91C_PIO_PA27) //  DBGU Debug Receive Data
+#define AT91C_PA27_PCK3           (AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
+#define AT91C_PIO_PA28            (1 << 28) // Pin Controlled by PA28
+#define AT91C_PA28_DTXD           (AT91C_PIO_PA28) //  DBGU Debug Transmit Data
+#define AT91C_PIO_PA29            (1 << 29) // Pin Controlled by PA29
+#define AT91C_PA29_FIQ            (AT91C_PIO_PA29) //  AIC Fast Interrupt Input
+#define AT91C_PA29_NPCS13         (AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA3             (1 <<  3) // Pin Controlled by PA3
+#define AT91C_PA3_RTS0            (AT91C_PIO_PA3) //  USART 0 Ready To Send
+#define AT91C_PA3_NPCS12          (AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PA30            (1 << 30) // Pin Controlled by PA30
+#define AT91C_PA30_IRQ0           (AT91C_PIO_PA30) //  External Interrupt 0
+#define AT91C_PA30_PCK2           (AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PA4             (1 <<  4) // Pin Controlled by PA4
+#define AT91C_PA4_CTS0            (AT91C_PIO_PA4) //  USART 0 Clear To Send
+#define AT91C_PA4_NPCS13          (AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PA5             (1 <<  5) // Pin Controlled by PA5
+#define AT91C_PA5_RXD1            (AT91C_PIO_PA5) //  USART 1 Receive Data
+#define AT91C_PIO_PA6             (1 <<  6) // Pin Controlled by PA6
+#define AT91C_PA6_TXD1            (AT91C_PIO_PA6) //  USART 1 Transmit Data
+#define AT91C_PIO_PA7             (1 <<  7) // Pin Controlled by PA7
+#define AT91C_PA7_SCK1            (AT91C_PIO_PA7) //  USART 1 Serial Clock
+#define AT91C_PA7_NPCS01          (AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PA8             (1 <<  8) // Pin Controlled by PA8
+#define AT91C_PA8_RTS1            (AT91C_PIO_PA8) //  USART 1 Ready To Send
+#define AT91C_PA8_NPCS02          (AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PA9             (1 <<  9) // Pin Controlled by PA9
+#define AT91C_PA9_CTS1            (AT91C_PIO_PA9) //  USART 1 Clear To Send
+#define AT91C_PA9_NPCS03          (AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB0             (1 <<  0) // Pin Controlled by PB0
+#define AT91C_PB0_ETXCK_EREFCK    (AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
+#define AT91C_PB0_PCK0            (AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB1             (1 <<  1) // Pin Controlled by PB1
+#define AT91C_PB1_ETXEN           (AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
+#define AT91C_PIO_PB10            (1 << 10) // Pin Controlled by PB10
+#define AT91C_PB10_ETX2           (AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
+#define AT91C_PB10_NPCS11         (AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
+#define AT91C_PIO_PB11            (1 << 11) // Pin Controlled by PB11
+#define AT91C_PB11_ETX3           (AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
+#define AT91C_PB11_NPCS12         (AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
+#define AT91C_PIO_PB12            (1 << 12) // Pin Controlled by PB12
+#define AT91C_PB12_ETXER          (AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
+#define AT91C_PB12_TCLK0          (AT91C_PIO_PB12) //  Timer Counter 0 external clock input
+#define AT91C_PIO_PB13            (1 << 13) // Pin Controlled by PB13
+#define AT91C_PB13_ERX2           (AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
+#define AT91C_PB13_NPCS01         (AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
+#define AT91C_PIO_PB14            (1 << 14) // Pin Controlled by PB14
+#define AT91C_PB14_ERX3           (AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
+#define AT91C_PB14_NPCS02         (AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
+#define AT91C_PIO_PB15            (1 << 15) // Pin Controlled by PB15
+#define AT91C_PB15_ERXDV          (AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
+#define AT91C_PIO_PB16            (1 << 16) // Pin Controlled by PB16
+#define AT91C_PB16_ECOL           (AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
+#define AT91C_PB16_NPCS13         (AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
+#define AT91C_PIO_PB17            (1 << 17) // Pin Controlled by PB17
+#define AT91C_PB17_ERXCK          (AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
+#define AT91C_PB17_NPCS03         (AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
+#define AT91C_PIO_PB18            (1 << 18) // Pin Controlled by PB18
+#define AT91C_PB18_EF100          (AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
+#define AT91C_PB18_ADTRG          (AT91C_PIO_PB18) //  ADC External Trigger
+#define AT91C_PIO_PB19            (1 << 19) // Pin Controlled by PB19
+#define AT91C_PB19_PWM0           (AT91C_PIO_PB19) //  PWM Channel 0
+#define AT91C_PB19_TCLK1          (AT91C_PIO_PB19) //  Timer Counter 1 external clock input
+#define AT91C_PIO_PB2             (1 <<  2) // Pin Controlled by PB2
+#define AT91C_PB2_ETX0            (AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
+#define AT91C_PIO_PB20            (1 << 20) // Pin Controlled by PB20
+#define AT91C_PB20_PWM1           (AT91C_PIO_PB20) //  PWM Channel 1
+#define AT91C_PB20_PCK0           (AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
+#define AT91C_PIO_PB21            (1 << 21) // Pin Controlled by PB21
+#define AT91C_PB21_PWM2           (AT91C_PIO_PB21) //  PWM Channel 2
+#define AT91C_PB21_PCK1           (AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
+#define AT91C_PIO_PB22            (1 << 22) // Pin Controlled by PB22
+#define AT91C_PB22_PWM3           (AT91C_PIO_PB22) //  PWM Channel 3
+#define AT91C_PB22_PCK2           (AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
+#define AT91C_PIO_PB23            (1 << 23) // Pin Controlled by PB23
+#define AT91C_PB23_TIOA0          (AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
+#define AT91C_PB23_DCD1           (AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
+#define AT91C_PIO_PB24            (1 << 24) // Pin Controlled by PB24
+#define AT91C_PB24_TIOB0          (AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
+#define AT91C_PB24_DSR1           (AT91C_PIO_PB24) //  USART 1 Data Set ready
+#define AT91C_PIO_PB25            (1 << 25) // Pin Controlled by PB25
+#define AT91C_PB25_TIOA1          (AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
+#define AT91C_PB25_DTR1           (AT91C_PIO_PB25) //  USART 1 Data Terminal ready
+#define AT91C_PIO_PB26            (1 << 26) // Pin Controlled by PB26
+#define AT91C_PB26_TIOB1          (AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
+#define AT91C_PB26_RI1            (AT91C_PIO_PB26) //  USART 1 Ring Indicator
+#define AT91C_PIO_PB27            (1 << 27) // Pin Controlled by PB27
+#define AT91C_PB27_TIOA2          (AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
+#define AT91C_PB27_PWM0           (AT91C_PIO_PB27) //  PWM Channel 0
+#define AT91C_PIO_PB28            (1 << 28) // Pin Controlled by PB28
+#define AT91C_PB28_TIOB2          (AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
+#define AT91C_PB28_PWM1           (AT91C_PIO_PB28) //  PWM Channel 1
+#define AT91C_PIO_PB29            (1 << 29) // Pin Controlled by PB29
+#define AT91C_PB29_PCK1           (AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
+#define AT91C_PB29_PWM2           (AT91C_PIO_PB29) //  PWM Channel 2
+#define AT91C_PIO_PB3             (1 <<  3) // Pin Controlled by PB3
+#define AT91C_PB3_ETX1            (AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
+#define AT91C_PIO_PB30            (1 << 30) // Pin Controlled by PB30
+#define AT91C_PB30_PCK2           (AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
+#define AT91C_PB30_PWM3           (AT91C_PIO_PB30) //  PWM Channel 3
+#define AT91C_PIO_PB4             (1 <<  4) // Pin Controlled by PB4
+#define AT91C_PB4_ECRS_ECRSDV     (AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
+#define AT91C_PIO_PB5             (1 <<  5) // Pin Controlled by PB5
+#define AT91C_PB5_ERX0            (AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
+#define AT91C_PIO_PB6             (1 <<  6) // Pin Controlled by PB6
+#define AT91C_PB6_ERX1            (AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
+#define AT91C_PIO_PB7             (1 <<  7) // Pin Controlled by PB7
+#define AT91C_PB7_ERXER           (AT91C_PIO_PB7) //  Ethernet MAC Receive Error
+#define AT91C_PIO_PB8             (1 <<  8) // Pin Controlled by PB8
+#define AT91C_PB8_EMDC            (AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
+#define AT91C_PIO_PB9             (1 <<  9) // Pin Controlled by PB9
+#define AT91C_PB9_EMDIO           (AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
+
+// *****************************************************************************
+//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ID_FIQ              ( 0) // Advanced Interrupt Controller (FIQ)
+#define AT91C_ID_SYS              ( 1) // System Peripheral
+#define AT91C_ID_PIOA             ( 2) // Parallel IO Controller A
+#define AT91C_ID_PIOB             ( 3) // Parallel IO Controller B
+#define AT91C_ID_SPI0             ( 4) // Serial Peripheral Interface 0
+#define AT91C_ID_SPI1             ( 5) // Serial Peripheral Interface 1
+#define AT91C_ID_US0              ( 6) // USART 0
+#define AT91C_ID_US1              ( 7) // USART 1
+#define AT91C_ID_SSC              ( 8) // Serial Synchronous Controller
+#define AT91C_ID_TWI              ( 9) // Two-Wire Interface
+#define AT91C_ID_PWMC             (10) // PWM Controller
+#define AT91C_ID_UDP              (11) // USB Device Port
+#define AT91C_ID_TC0              (12) // Timer Counter 0
+#define AT91C_ID_TC1              (13) // Timer Counter 1
+#define AT91C_ID_TC2              (14) // Timer Counter 2
+#define AT91C_ID_CAN              (15) // Control Area Network Controller
+#define AT91C_ID_EMAC             (16) // Ethernet MAC
+#define AT91C_ID_ADC              (17) // Analog-to-Digital Converter
+#define AT91C_ID_AES              (18) // Advanced Encryption Standard 128-bit
+#define AT91C_ID_TDES             (19) // Triple Data Encryption Standard
+#define AT91C_ID_20_Reserved      (20) // Reserved
+#define AT91C_ID_21_Reserved      (21) // Reserved
+#define AT91C_ID_22_Reserved      (22) // Reserved
+#define AT91C_ID_23_Reserved      (23) // Reserved
+#define AT91C_ID_24_Reserved      (24) // Reserved
+#define AT91C_ID_25_Reserved      (25) // Reserved
+#define AT91C_ID_26_Reserved      (26) // Reserved
+#define AT91C_ID_27_Reserved      (27) // Reserved
+#define AT91C_ID_28_Reserved      (28) // Reserved
+#define AT91C_ID_29_Reserved      (29) // Reserved
+#define AT91C_ID_IRQ0             (30) // Advanced Interrupt Controller (IRQ0)
+#define AT91C_ID_IRQ1             (31) // Advanced Interrupt Controller (IRQ1)
+
+// *****************************************************************************
+//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_BASE_SYS            (0xFFFFF000) // (SYS) Base Address
+#define AT91C_BASE_AIC            (0xFFFFF000) // (AIC) Base Address
+#define AT91C_BASE_PDC_DBGU       (0xFFFFF300) // (PDC_DBGU) Base Address
+#define AT91C_BASE_DBGU           (0xFFFFF200) // (DBGU) Base Address
+#define AT91C_BASE_PIOA           (0xFFFFF400) // (PIOA) Base Address
+#define AT91C_BASE_PIOB           (0xFFFFF600) // (PIOB) Base Address
+#define AT91C_BASE_CKGR           (0xFFFFFC20) // (CKGR) Base Address
+#define AT91C_BASE_PMC            (0xFFFFFC00) // (PMC) Base Address
+#define AT91C_BASE_RSTC           (0xFFFFFD00) // (RSTC) Base Address
+#define AT91C_BASE_RTTC           (0xFFFFFD20) // (RTTC) Base Address
+#define AT91C_BASE_PITC           (0xFFFFFD30) // (PITC) Base Address
+#define AT91C_BASE_WDTC           (0xFFFFFD40) // (WDTC) Base Address
+#define AT91C_BASE_VREG           (0xFFFFFD60) // (VREG) Base Address
+#define AT91C_BASE_MC             (0xFFFFFF00) // (MC) Base Address
+#define AT91C_BASE_PDC_SPI1       (0xFFFE4100) // (PDC_SPI1) Base Address
+#define AT91C_BASE_SPI1           (0xFFFE4000) // (SPI1) Base Address
+#define AT91C_BASE_PDC_SPI0       (0xFFFE0100) // (PDC_SPI0) Base Address
+#define AT91C_BASE_SPI0           (0xFFFE0000) // (SPI0) Base Address
+#define AT91C_BASE_PDC_US1        (0xFFFC4100) // (PDC_US1) Base Address
+#define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address
+#define AT91C_BASE_PDC_US0        (0xFFFC0100) // (PDC_US0) Base Address
+#define AT91C_BASE_US0            (0xFFFC0000) // (US0) Base Address
+#define AT91C_BASE_PDC_SSC        (0xFFFD4100) // (PDC_SSC) Base Address
+#define AT91C_BASE_SSC            (0xFFFD4000) // (SSC) Base Address
+#define AT91C_BASE_TWI            (0xFFFB8000) // (TWI) Base Address
+#define AT91C_BASE_PWMC_CH3       (0xFFFCC260) // (PWMC_CH3) Base Address
+#define AT91C_BASE_PWMC_CH2       (0xFFFCC240) // (PWMC_CH2) Base Address
+#define AT91C_BASE_PWMC_CH1       (0xFFFCC220) // (PWMC_CH1) Base Address
+#define AT91C_BASE_PWMC_CH0       (0xFFFCC200) // (PWMC_CH0) Base Address
+#define AT91C_BASE_PWMC           (0xFFFCC000) // (PWMC) Base Address
+#define AT91C_BASE_UDP            (0xFFFB0000) // (UDP) Base Address
+#define AT91C_BASE_TC0            (0xFFFA0000) // (TC0) Base Address
+#define AT91C_BASE_TC1            (0xFFFA0040) // (TC1) Base Address
+#define AT91C_BASE_TC2            (0xFFFA0080) // (TC2) Base Address
+#define AT91C_BASE_TCB            (0xFFFA0000) // (TCB) Base Address
+#define AT91C_BASE_CAN_MB0        (0xFFFD0200) // (CAN_MB0) Base Address
+#define AT91C_BASE_CAN_MB1        (0xFFFD0220) // (CAN_MB1) Base Address
+#define AT91C_BASE_CAN_MB2        (0xFFFD0240) // (CAN_MB2) Base Address
+#define AT91C_BASE_CAN_MB3        (0xFFFD0260) // (CAN_MB3) Base Address
+#define AT91C_BASE_CAN_MB4        (0xFFFD0280) // (CAN_MB4) Base Address
+#define AT91C_BASE_CAN_MB5        (0xFFFD02A0) // (CAN_MB5) Base Address
+#define AT91C_BASE_CAN_MB6        (0xFFFD02C0) // (CAN_MB6) Base Address
+#define AT91C_BASE_CAN_MB7        (0xFFFD02E0) // (CAN_MB7) Base Address
+#define AT91C_BASE_CAN            (0xFFFD0000) // (CAN) Base Address
+#define AT91C_BASE_EMAC           (0xFFFDC000) // (EMAC) Base Address
+#define AT91C_BASE_PDC_ADC        (0xFFFD8100) // (PDC_ADC) Base Address
+#define AT91C_BASE_ADC            (0xFFFD8000) // (ADC) Base Address
+#define AT91C_BASE_PDC_AES        (0xFFFA4100) // (PDC_AES) Base Address
+#define AT91C_BASE_AES            (0xFFFA4000) // (AES) Base Address
+#define AT91C_BASE_PDC_TDES       (0xFFFA8100) // (PDC_TDES) Base Address
+#define AT91C_BASE_TDES           (0xFFFA8000) // (TDES) Base Address
+
+// *****************************************************************************
+//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
+// *****************************************************************************
+#define AT91C_ISRAM	              (0x00200000) // Internal SRAM base address
+#define AT91C_ISRAM_SIZE	         (0x00010000) // Internal SRAM size in byte (64 Kbyte)
+#define AT91C_IFLASH	             (0x00100000) // Internal ROM base address
+#define AT91C_IFLASH_SIZE	        (0x00040000) // Internal ROM size in byte (256 Kbyte)
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h
new file mode 100644
index 0000000..f16c592
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h
@@ -0,0 +1,105 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	EXTERN pxCurrentTCB
+	EXTERN ulCriticalNesting
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+portSAVE_CONTEXT MACRO
+
+	; Push R0 as we are going to use the register.
+	STMDB	SP!, {R0}
+
+	; Set R0 to point to the task stack pointer.
+	STMDB	SP, {SP}^
+	NOP
+	SUB		SP, SP, #4
+	LDMIA	SP!, {R0}
+
+	; Push the return address onto the stack.
+	STMDB	R0!, {LR}
+
+	; Now we have saved LR we can use it instead of R0.
+	MOV		LR, R0
+
+	; Pop R0 so we can save it onto the system mode stack.
+	LDMIA	SP!, {R0}
+
+	; Push all the system mode registers onto the task stack.
+	STMDB	LR, {R0-LR}^
+	NOP
+	SUB		LR, LR, #60
+
+	; Push the SPSR onto the task stack.
+	MRS		R0, SPSR
+	STMDB	LR!, {R0}
+
+	LDR		R0, =ulCriticalNesting
+	LDR		R0, [R0]
+	STMDB	LR!, {R0}
+
+	; Store the new top of stack for the task.
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	STR		LR, [R0]
+
+	ENDM
+
+
+portRESTORE_CONTEXT MACRO
+
+	; Set the LR to the task stack.
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	LDR		LR, [R0]
+
+	; The critical nesting depth is the first item on the stack.
+	; Load it into the ulCriticalNesting variable.
+	LDR		R0, =ulCriticalNesting
+	LDMFD	LR!, {R1}
+	STR		R1, [R0]
+
+	; Get the SPSR from the stack.
+	LDMFD	LR!, {R0}
+	MSR		SPSR_cxsf, R0
+
+	; Restore all system mode registers for the task.
+	LDMFD	LR, {R0-R14}^
+	NOP
+
+	; Restore the return address.
+	LDR		LR, [LR, #+60]
+
+	; And return - correcting the offset in the LR to obtain the
+	; correct address.
+	SUBS	PC, LR, #4
+
+	ENDM
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
new file mode 100644
index 0000000..9d012c4
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
@@ -0,0 +1,3265 @@
+//*----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//*----------------------------------------------------------------------------
+//* The software is delivered "AS IS" without warranty or condition of any
+//* kind, either express, implied or statutory. This includes without
+//* limitation any warranty or condition with respect to merchantability or
+//* fitness for any particular purpose, or against the infringements of
+//* intellectual property rights of others.
+//*----------------------------------------------------------------------------
+//* File Name           : lib_AT91SAM7S64.h
+//* Object              : AT91SAM7S64 inlined functions
+//* Generated           : AT91 SW Application Group  07/16/2004 (07:43:09)
+//*
+//* CVS Reference       : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004//
+//* CVS Reference       : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003//
+//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003//
+//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference       : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
+//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003//
+//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference       : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003//
+//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference       : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003//
+//* CVS Reference       : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002//
+//*----------------------------------------------------------------------------
+
+#ifndef lib_AT91SAM7S64_H
+#define lib_AT91SAM7S64_H
+
+/* *****************************************************************************
+                SOFTWARE API FOR MC
+   ***************************************************************************** */
+
+#define AT91C_MC_CORRECT_KEY  ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_Remap
+//* \brief Make Remap
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_Remap (void)     //  
+{
+    AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
+    
+    pMC->MC_RCR = AT91C_MC_RCB;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_CfgModeReg
+//* \brief Configure the EFC Mode Register of the MC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_CfgModeReg (
+	AT91PS_MC pMC, // pointer to a MC controller
+	unsigned int mode)        // mode register 
+{
+	// Write to the FMR register
+	pMC->MC_FMR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_GetModeReg
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetModeReg(
+	AT91PS_MC pMC) // pointer to a MC controller
+{
+	return pMC->MC_FMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_ComputeFMCN
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
+	int master_clock) // master clock in Hz
+{
+	return (master_clock/1000000 +2);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_PerformCmd
+//* \brief Perform EFC Command
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_PerformCmd (
+	AT91PS_MC pMC, // pointer to a MC controller
+    unsigned int transfer_cmd)
+{
+	pMC->MC_FCR = transfer_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_GetStatus
+//* \brief Return MC EFC Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetStatus(
+	AT91PS_MC pMC) // pointer to a MC controller
+{
+	return pMC->MC_FSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_IsInterruptMasked
+//* \brief Test if EFC MC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
+        AT91PS_MC pMC,   // \arg  pointer to a MC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_IsInterruptSet
+//* \brief Test if EFC MC Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
+        AT91PS_MC pMC,   // \arg  pointer to a MC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_MC_EFC_GetStatus(pMC) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PDC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetNextRx
+//* \brief Set the next receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextRx (
+	AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
+	char *address,       // \arg address to the next bloc to be received
+	unsigned int bytes)  // \arg number of bytes to be received
+{
+	pPDC->PDC_RNPR = (unsigned int) address;
+	pPDC->PDC_RNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetNextTx
+//* \brief Set the next transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextTx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be transmitted
+	unsigned int bytes)    // \arg number of bytes to be transmitted
+{
+	pPDC->PDC_TNPR = (unsigned int) address;
+	pPDC->PDC_TNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetRx
+//* \brief Set the receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetRx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be received
+	unsigned int bytes)    // \arg number of bytes to be received
+{
+	pPDC->PDC_RPR = (unsigned int) address;
+	pPDC->PDC_RCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetTx
+//* \brief Set the transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetTx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be transmitted
+	unsigned int bytes)    // \arg number of bytes to be transmitted
+{
+	pPDC->PDC_TPR = (unsigned int) address;
+	pPDC->PDC_TCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_EnableTx
+//* \brief Enable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableTx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_EnableRx
+//* \brief Enable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableRx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_DisableTx
+//* \brief Disable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableTx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_DisableRx
+//* \brief Disable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableRx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsTxEmpty
+//* \brief Test if the current transfer descriptor has been sent
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_TCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsNextTxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_TNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsRxEmpty
+//* \brief Test if the current transfer descriptor has been filled
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_RCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsNextRxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_RNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_Open
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Open (
+	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+{
+    //* Disable the RX and TX PDC transfer requests
+	AT91F_PDC_DisableRx(pPDC);
+	AT91F_PDC_DisableTx(pPDC);
+
+	//* Reset all Counter register Next buffer first
+	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+    //* Enable the RX and TX PDC transfer requests
+	AT91F_PDC_EnableRx(pPDC);
+	AT91F_PDC_EnableTx(pPDC);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_Close
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Close (
+	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+{
+    //* Disable the RX and TX PDC transfer requests
+	AT91F_PDC_DisableRx(pPDC);
+	AT91F_PDC_DisableTx(pPDC);
+
+	//* Reset all Counter register Next buffer first
+	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SendFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_SendFrame(
+	AT91PS_PDC pPDC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	if (AT91F_PDC_IsTxEmpty(pPDC)) {
+		//* Buffer and next buffer can be initialized
+		AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
+		AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
+		return 2;
+	}
+	else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
+		//* Only one buffer can be initialized
+		AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
+		return 1;
+	}
+	else {
+		//* All buffer are in use...
+		return 0;
+	}
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_ReceiveFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_ReceiveFrame (
+	AT91PS_PDC pPDC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	if (AT91F_PDC_IsRxEmpty(pPDC)) {
+		//* Buffer and next buffer can be initialized
+		AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
+		AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
+		return 2;
+	}
+	else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
+		//* Only one buffer can be initialized
+		AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
+		return 1;
+	}
+	else {
+		//* All buffer are in use...
+		return 0;
+	}
+}
+/* *****************************************************************************
+                SOFTWARE API FOR DBGU
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_InterruptEnable
+//* \brief Enable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptEnable(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  dbgu interrupt to be enabled
+{
+        pDbgu->DBGU_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_InterruptDisable
+//* \brief Disable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptDisable(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  dbgu interrupt to be disabled
+{
+        pDbgu->DBGU_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_GetInterruptMaskStatus
+//* \brief Return DBGU Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
+        AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
+{
+        return pDbgu->DBGU_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_IsInterruptMasked
+//* \brief Test if DBGU Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_DBGU_IsInterruptMasked(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR SSC
+   ***************************************************************************** */
+//* Define the standard I2S mode configuration
+
+//* Configuration to set in the SSC Transmit Clock Mode Register
+//* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
+//* 			  nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+									   AT91C_SSC_CKS_DIV   +\
+                            		   AT91C_SSC_CKO_CONTINOUS      +\
+                            		   AT91C_SSC_CKG_NONE    +\
+                                       AT91C_SSC_START_FALL_RF +\
+                           			   AT91C_SSC_STTOUT  +\
+                            		   ((1<<16) & AT91C_SSC_STTDLY) +\
+                            		   ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
+
+
+//* Configuration to set in the SSC Transmit Frame Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* 			 nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+									(nb_bit_by_slot-1)  +\
+                            		AT91C_SSC_MSBF   +\
+                            		(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
+                            		(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
+                            		AT91C_SSC_FSOS_NEGATIVE)
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_SetBaudrate (
+        AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
+        unsigned int mainClock, // \arg peripheral clock
+        unsigned int speed)     // \arg SSC baudrate
+{
+        unsigned int baud_value;
+        //* Define the baud rate divisor register
+        if (speed == 0)
+           baud_value = 0;
+        else
+        {
+           baud_value = (unsigned int) (mainClock * 10)/(2*speed);
+           if ((baud_value % 10) >= 5)
+                  baud_value = (baud_value / 10) + 1;
+           else
+                  baud_value /= 10;
+        }
+
+        pSSC->SSC_CMR = baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_Configure
+//* \brief Configure SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_Configure (
+             AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
+             unsigned int syst_clock,  // \arg System Clock Frequency
+             unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
+             unsigned int clock_rx,    // \arg Receiver Clock Parameters
+             unsigned int mode_rx,     // \arg mode Register to be programmed
+             unsigned int clock_tx,    // \arg Transmitter Clock Parameters
+             unsigned int mode_tx)     // \arg mode Register to be programmed
+{
+    //* Disable interrupts
+	pSSC->SSC_IDR = (unsigned int) -1;
+
+    //* Reset receiver and transmitter
+	pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
+
+    //* Define the Clock Mode Register
+	AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
+
+     //* Write the Receive Clock Mode Register
+	pSSC->SSC_RCMR =  clock_rx;
+
+     //* Write the Transmit Clock Mode Register
+	pSSC->SSC_TCMR =  clock_tx;
+
+     //* Write the Receive Frame Mode Register
+	pSSC->SSC_RFMR =  mode_rx;
+
+     //* Write the Transmit Frame Mode Register
+	pSSC->SSC_TFMR =  mode_tx;
+
+    //* Clear Transmit and Receive Counters
+	AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
+
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableRx
+//* \brief Enable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableRx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Enable receiver
+    pSSC->SSC_CR = AT91C_SSC_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableRx
+//* \brief Disable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableRx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Disable receiver
+    pSSC->SSC_CR = AT91C_SSC_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableTx
+//* \brief Enable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableTx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Enable  transmitter
+    pSSC->SSC_CR = AT91C_SSC_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableTx
+//* \brief Disable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableTx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Disable  transmitter
+    pSSC->SSC_CR = AT91C_SSC_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableIt
+//* \brief Enable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableIt (
+	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pSSC->SSC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableIt
+//* \brief Disable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableIt (
+	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pSSC->SSC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_ReceiveFrame (
+	AT91PS_SSC pSSC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pSSC->SSC_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_SendFrame(
+	AT91PS_SSC pSSC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pSSC->SSC_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_GetInterruptMaskStatus
+//* \brief Return SSC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
+        AT91PS_SSC pSsc) // \arg  pointer to a SSC controller
+{
+        return pSsc->SSC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_IsInterruptMasked
+//* \brief Test if SSC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_SSC_IsInterruptMasked(
+        AT91PS_SSC pSsc,   // \arg  pointer to a SSC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR SPI
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Open
+//* \brief Open a SPI Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_Open (
+        const unsigned int null)  // \arg
+{
+        /* NOT DEFINED AT THIS MOMENT */
+        return ( 0 );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgCs
+//* \brief Configure SPI chip select register
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgCs (
+	AT91PS_SPI pSPI,     // pointer to a SPI controller
+	int cs,     // SPI cs number (0 to 3)
+ 	int val)   //  chip select register
+{
+	//* Write to the CSR register
+	*(pSPI->SPI_CSR + cs) = val;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_EnableIt
+//* \brief Enable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_EnableIt (
+	AT91PS_SPI pSPI,     // pointer to a SPI controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pSPI->SPI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_DisableIt
+//* \brief Disable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_DisableIt (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pSPI->SPI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Reset
+//* \brief Reset the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Reset (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SWRST;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Enable
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Enable (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SPIEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Disable
+//* \brief Disable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Disable (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgMode
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgMode (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	int mode)        // mode register 
+{
+	//* Write to the MR register
+	pSPI->SPI_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgPCS
+//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPCS (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	char PCS_Device) // PCS of the Device
+{	
+ 	//* Write to the MR register
+	pSPI->SPI_MR &= 0xFFF0FFFF;
+	pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_ReceiveFrame (
+	AT91PS_SPI pSPI,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pSPI->SPI_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_SendFrame(
+	AT91PS_SPI pSPI,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pSPI->SPI_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Close
+//* \brief Close SPI: disable IT disable transfert, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Close (
+	AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
+{
+    //* Reset all the Chip Select register
+    pSPI->SPI_CSR[0] = 0 ;
+    pSPI->SPI_CSR[1] = 0 ;
+    pSPI->SPI_CSR[2] = 0 ;
+    pSPI->SPI_CSR[3] = 0 ;
+
+    //* Reset the SPI mode
+    pSPI->SPI_MR = 0  ;
+
+    //* Disable all interrupts
+    pSPI->SPI_IDR = 0xFFFFFFFF ;
+
+    //* Abort the Peripheral Data Transfers
+    AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
+
+    //* Disable receiver and transmitter and stop any activity immediately
+    pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_PutChar (
+	AT91PS_SPI pSPI,
+	unsigned int character,
+             unsigned int cs_number )
+{
+    unsigned int value_for_cs;
+    value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number
+    pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_GetChar (
+	const AT91PS_SPI pSPI)
+{
+    return((pSPI->SPI_RDR) & 0xFFFF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_GetInterruptMaskStatus
+//* \brief Return SPI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
+        AT91PS_SPI pSpi) // \arg  pointer to a SPI controller
+{
+        return pSpi->SPI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_IsInterruptMasked
+//* \brief Test if SPI Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_IsInterruptMasked(
+        AT91PS_SPI pSpi,   // \arg  pointer to a SPI controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PWMC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_GetStatus
+//* \brief Return PWM Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
+	AT91PS_PWMC pPWM) // pointer to a PWM controller
+{
+	return pPWM->PWMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_InterruptEnable
+//* \brief Enable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptEnable(
+        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  PWM interrupt to be enabled
+{
+        pPwm->PWMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_InterruptDisable
+//* \brief Disable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptDisable(
+        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  PWM interrupt to be disabled
+{
+        pPwm->PWMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_GetInterruptMaskStatus
+//* \brief Return PWM Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
+        AT91PS_PWMC pPwm) // \arg  pointer to a PWM controller
+{
+        return pPwm->PWMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_IsInterruptMasked
+//* \brief Test if PWM Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsInterruptMasked(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_IsStatusSet
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsStatusSet(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PWMC_GetStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_CfgChannel
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int channelId, // \arg PWM channel ID
+        unsigned int mode, // \arg  PWM mode
+        unsigned int period, // \arg PWM period
+        unsigned int duty) // \arg PWM duty cycle
+{
+	pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
+	pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
+	pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_StartChannel
+//* \brief Enable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StartChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_ENA = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_StopChannel
+//* \brief Disable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StopChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_DIS = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_UpdateChannel
+//* \brief Update Period or Duty Cycle
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_UpdateChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int channelId, // \arg PWM channel ID
+        unsigned int update) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_InterruptEnable
+//* \brief Enable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptEnable(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  TC interrupt to be enabled
+{
+        pTc->TC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_InterruptDisable
+//* \brief Disable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptDisable(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  TC interrupt to be disabled
+{
+        pTc->TC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_GetInterruptMaskStatus
+//* \brief Return TC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
+        AT91PS_TC pTc) // \arg  pointer to a TC controller
+{
+        return pTc->TC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_IsInterruptMasked
+//* \brief Test if TC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_TC_IsInterruptMasked(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PMC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgSysClkEnableReg
+//* \brief Configure the System Clock Enable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkEnableReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	//* Write to the SCER register
+	pPMC->PMC_SCER = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgSysClkDisableReg
+//* \brief Configure the System Clock Disable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkDisableReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	//* Write to the SCDR register
+	pPMC->PMC_SCDR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetSysClkStatusReg
+//* \brief Return the System Clock Status Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
+	AT91PS_PMC pPMC // pointer to a CAN controller
+	)
+{
+	return pPMC->PMC_SCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnablePeriphClock
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePeriphClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int periphIds)  // \arg IDs of peripherals to enable
+{
+	pPMC->PMC_PCER = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisablePeriphClock
+//* \brief Disable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePeriphClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int periphIds)  // \arg IDs of peripherals to enable
+{
+	pPMC->PMC_PCDR = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetPeriphClock
+//* \brief Get peripheral clock status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetPeriphClock (
+	AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+	return pPMC->PMC_PCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_CfgMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscillatorReg (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int mode)
+{
+	pCKGR->CKGR_MOR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	return pCKGR->CKGR_MOR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_EnableMainOscillator
+//* \brief Enable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_EnableMainOscillator(
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_DisableMainOscillator
+//* \brief Disable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_DisableMainOscillator (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
+//* \brief Cfg MOR Register according to the main osc startup time
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
+	pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainClockFreqReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	return pCKGR->CKGR_MCFR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainClock
+//* \brief Return Main clock in Hz
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClock (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgMCKReg
+//* \brief Cfg Master Clock Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgMCKReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	pPMC->PMC_MCKR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetMCKReg
+//* \brief Return Master Clock Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMCKReg(
+	AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+	return pPMC->PMC_MCKR;
+}
+
+//*------------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetMasterClock
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7
+//*------------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMasterClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	unsigned int reg = pPMC->PMC_MCKR;
+	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
+	unsigned int pllDivider, pllMultiplier;
+
+	switch (reg & AT91C_PMC_CSS) {
+		case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
+			return slowClock / prescaler;
+		case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
+			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
+		case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
+			reg = pCKGR->CKGR_PLLR;
+			pllDivider    = (reg  & AT91C_CKGR_DIV);
+			pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
+			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
+	}
+	return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePCK (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
+	unsigned int mode)
+{
+	pPMC->PMC_PCKR[pck] = mode;
+	pPMC->PMC_SCER = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePCK (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
+{
+	pPMC->PMC_SCDR = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnableIt
+//* \brief Enable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnableIt (
+	AT91PS_PMC pPMC,     // pointer to a PMC controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pPMC->PMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisableIt
+//* \brief Disable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisableIt (
+	AT91PS_PMC pPMC, // pointer to a PMC controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pPMC->PMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetStatus
+//* \brief Return PMC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
+	AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+	return pPMC->PMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetInterruptMaskStatus
+//* \brief Return PMC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
+	AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+	return pPMC->PMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_IsInterruptMasked
+//* \brief Test if PMC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsInterruptMasked(
+        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_IsStatusSet
+//* \brief Test if PMC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsStatusSet(
+        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PMC_GetStatus(pPMC) & flag);
+}/* *****************************************************************************
+                SOFTWARE API FOR ADC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_EnableIt
+//* \brief Enable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableIt (
+	AT91PS_ADC pADC,     // pointer to a ADC controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pADC->ADC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_DisableIt
+//* \brief Disable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableIt (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pADC->ADC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetStatus
+//* \brief Return ADC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
+	AT91PS_ADC pADC) // pointer to a ADC controller
+{
+	return pADC->ADC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetInterruptMaskStatus
+//* \brief Return ADC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
+	AT91PS_ADC pADC) // pointer to a ADC controller
+{
+	return pADC->ADC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_IsInterruptMasked
+//* \brief Test if ADC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsInterruptMasked(
+        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_IsStatusSet
+//* \brief Test if ADC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsStatusSet(
+        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_ADC_GetStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgModeReg
+//* \brief Configure the Mode Register of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgModeReg (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pADC->ADC_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetModeReg
+//* \brief Return the Mode Register of the ADC controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetModeReg (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgTimings
+//* \brief Configure the different necessary timings of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgTimings (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int mck_clock, // in MHz 
+	unsigned int adc_clock, // in MHz 
+	unsigned int startup_time, // in us 
+	unsigned int sample_and_hold_time)	// in ns  
+{
+	unsigned int prescal,startup,shtim;
+	
+	prescal = mck_clock/(2*adc_clock) - 1;
+	startup = adc_clock*startup_time/8 - 1;
+	shtim = adc_clock*sample_and_hold_time/1000 - 1;
+	
+	//* Write to the MR register
+	pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_EnableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableChannel (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int channel)        // mode register 
+{
+	//* Write to the CHER register
+	pADC->ADC_CHER = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_DisableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableChannel (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int channel)        // mode register 
+{
+	//* Write to the CHDR register
+	pADC->ADC_CHDR = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetChannelStatus
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetChannelStatus (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CHSR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_StartConversion
+//* \brief Software request for a analog to digital conversion 
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_StartConversion (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	pADC->ADC_CR = AT91C_ADC_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_SoftReset
+//* \brief Software reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_SoftReset (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	pADC->ADC_CR = AT91C_ADC_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetLastConvertedData
+//* \brief Return the Last Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetLastConvertedData (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_LCDR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH0
+//* \brief Return the Channel 0 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR0;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH1
+//* \brief Return the Channel 1 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR1;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH2
+//* \brief Return the Channel 2 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR2;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH3
+//* \brief Return the Channel 3 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR3;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH4
+//* \brief Return the Channel 4 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR4;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH5
+//* \brief Return the Channel 5 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR5;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH6
+//* \brief Return the Channel 6 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR6;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH7
+//* \brief Return the Channel 7 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR7;	
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PIO
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgPeriph
+//* \brief Enable pins to be drived by peripheral
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPeriph(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int periphAEnable,  // \arg PERIPH A to enable
+	unsigned int periphBEnable)  // \arg PERIPH B to enable
+
+{
+	pPio->PIO_ASR = periphAEnable;
+	pPio->PIO_BSR = periphBEnable;
+	pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgOutput
+//* \brief Enable PIO in output mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOutput(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int pioEnable)      // \arg PIO to be enabled
+{
+	pPio->PIO_PER = pioEnable; // Set in PIO mode
+	pPio->PIO_OER = pioEnable; // Configure in Output
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgInput
+//* \brief Enable PIO in input mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInput(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int inputEnable)      // \arg PIO to be enabled
+{
+	// Disable output
+	pPio->PIO_ODR  = inputEnable;
+	pPio->PIO_PER  = inputEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgOpendrain
+//* \brief Configure PIO in open drain
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOpendrain(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int multiDrvEnable) // \arg pio to be configured in open drain
+{
+	// Configure the multi-drive option
+	pPio->PIO_MDDR = ~multiDrvEnable;
+	pPio->PIO_MDER = multiDrvEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgPullup
+//* \brief Enable pullup on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPullup(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int pullupEnable)   // \arg enable pullup on PIO
+{
+		// Connect or not Pullup
+	pPio->PIO_PPUDR = ~pullupEnable;
+	pPio->PIO_PPUER = pullupEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgDirectDrive
+//* \brief Enable direct drive on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgDirectDrive(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int directDrive)    // \arg PIO to be configured with direct drive
+
+{
+	// Configure the Direct Drive
+	pPio->PIO_OWDR  = ~directDrive;
+	pPio->PIO_OWER  = directDrive;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgInputFilter
+//* \brief Enable input filter on input PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInputFilter(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int inputFilter)    // \arg PIO to be configured with input filter
+
+{
+	// Configure the Direct Drive
+	pPio->PIO_IFDR  = ~inputFilter;
+	pPio->PIO_IFER  = inputFilter;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInput
+//* \brief Return PIO input value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
+	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+	return pPio->PIO_PDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInputSet
+//* \brief Test if PIO is input flag is active
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputSet(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PIO_GetInput(pPio) & flag);
+}
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_SetOutput
+//* \brief Set to 1 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_SetOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be set
+{
+	pPio->PIO_SODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_ClearOutput
+//* \brief Set to 0 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ClearOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be cleared
+{
+	pPio->PIO_CODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_ForceOutput
+//* \brief Force output when Direct drive option is enabled
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ForceOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be forced
+{
+	pPio->PIO_ODSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Enable
+//* \brief Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Enable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be enabled 
+{
+        pPio->PIO_PER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Disable
+//* \brief Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Disable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be disabled 
+{
+        pPio->PIO_PDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetStatus
+//* \brief Return PIO Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_PSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsSet
+//* \brief Test if PIO is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputEnable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output to be enabled
+{
+        pPio->PIO_OER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputDisable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output to be disabled
+{
+        pPio->PIO_ODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputStatus
+//* \brief Return PIO Output Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_OSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOuputSet
+//* \brief Test if PIO Output is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InputFilterEnable
+//* \brief Input Filter Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio input filter to be enabled
+{
+        pPio->PIO_IFER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InputFilterDisable
+//* \brief Input Filter Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio input filter to be disabled
+{
+        pPio->PIO_IFDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInputFilterStatus
+//* \brief Return PIO Input Filter Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_IFSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInputFilterSet
+//* \brief Test if PIO Input filter is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputFilterSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputDataStatus
+//* \brief Return PIO Output Data Status 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status 
+	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ODSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InterruptEnable
+//* \brief Enable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio interrupt to be enabled
+{
+        pPio->PIO_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InterruptDisable
+//* \brief Disable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio interrupt to be disabled
+{
+        pPio->PIO_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInterruptMaskStatus
+//* \brief Return PIO Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInterruptStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInterruptMasked
+//* \brief Test if PIO Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptMasked(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInterruptSet
+//* \brief Test if PIO Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_MultiDriverEnable
+//* \brief Multi Driver Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be enabled
+{
+        pPio->PIO_MDER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_MultiDriverDisable
+//* \brief Multi Driver Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be disabled
+{
+        pPio->PIO_MDDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetMultiDriverStatus
+//* \brief Return PIO Multi Driver Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_MDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsMultiDriverSet
+//* \brief Test if PIO MultiDriver is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsMultiDriverSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_A_RegisterSelection
+//* \brief PIO A Register Selection 
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_A_RegisterSelection(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio A register selection
+{
+        pPio->PIO_ASR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_B_RegisterSelection
+//* \brief PIO B Register Selection 
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_B_RegisterSelection(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio B register selection 
+{
+        pPio->PIO_BSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Get_AB_RegisterStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ABSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsAB_RegisterSet
+//* \brief Test if PIO AB Register is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsAB_RegisterSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputWriteEnable
+//* \brief Output Write Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output write to be enabled
+{
+        pPio->PIO_OWER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputWriteDisable
+//* \brief Output Write Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output write to be disabled
+{
+        pPio->PIO_OWDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputWriteStatus
+//* \brief Return PIO Output Write Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_OWSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOutputWriteSet
+//* \brief Test if PIO OutputWrite is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputWriteSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetCfgPullup
+//* \brief Return PIO Configuration Pullup
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup 
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_PPUSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOutputDataStatusSet
+//* \brief Test if PIO Output Data Status is Set 
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputDataStatusSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsCfgPullupStatusSet
+//* \brief Test if PIO Configuration Pullup Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsCfgPullupStatusSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TWI
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_EnableIt
+//* \brief Enable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_EnableIt (
+	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pTWI->TWI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_DisableIt
+//* \brief Disable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_DisableIt (
+	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pTWI->TWI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_Configure
+//* \brief Configure TWI in master mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \arg pointer to a TWI controller
+{
+    //* Disable interrupts
+	pTWI->TWI_IDR = (unsigned int) -1;
+
+    //* Reset peripheral
+	pTWI->TWI_CR = AT91C_TWI_SWRST;
+
+	//* Set Master mode
+	pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_GetInterruptMaskStatus
+//* \brief Return TWI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
+        AT91PS_TWI pTwi) // \arg  pointer to a TWI controller
+{
+        return pTwi->TWI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_IsInterruptMasked
+//* \brief Test if TWI Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_TWI_IsInterruptMasked(
+        AT91PS_TWI pTwi,   // \arg  pointer to a TWI controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR USART
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Baudrate
+//* \brief Calculate the baudrate
+//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
+                        AT91C_US_NBSTOP_1_BIT + \
+                        AT91C_US_PAR_NONE + \
+                        AT91C_US_CHRL_8_BITS + \
+                        AT91C_US_CLKS_CLOCK )
+
+//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
+                            AT91C_US_NBSTOP_1_BIT + \
+                            AT91C_US_PAR_NONE + \
+                            AT91C_US_CHRL_8_BITS + \
+                            AT91C_US_CLKS_EXT )
+
+//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
+                       AT91C_US_USMODE_NORMAL + \
+                       AT91C_US_NBSTOP_1_BIT + \
+                       AT91C_US_PAR_NONE + \
+                       AT91C_US_CHRL_8_BITS + \
+                       AT91C_US_CLKS_CLOCK )
+
+//* SCK used Label
+#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
+
+//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
+#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
+					   		 AT91C_US_CLKS_CLOCK +\
+                       		 AT91C_US_NBSTOP_1_BIT + \
+                       		 AT91C_US_PAR_EVEN + \
+                       		 AT91C_US_CHRL_8_BITS + \
+                       		 AT91C_US_CKLO +\
+                       		 AT91C_US_OVER)
+
+//* Standard IRDA mode
+#define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \
+                            AT91C_US_NBSTOP_1_BIT + \
+                            AT91C_US_PAR_NONE + \
+                            AT91C_US_CHRL_8_BITS + \
+                            AT91C_US_CLKS_CLOCK )
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Baudrate
+//* \brief Caluculate baud_value according to the main clock and the baud rate
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Baudrate (
+	const unsigned int main_clock, // \arg peripheral clock
+	const unsigned int baud_rate)  // \arg UART baudrate
+{
+	unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
+	if ((baud_value % 10) >= 5)
+		baud_value = (baud_value / 10) + 1;
+	else
+		baud_value /= 10;
+	return baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetBaudrate (
+	AT91PS_USART pUSART,    // \arg pointer to a USART controller
+	unsigned int mainClock, // \arg peripheral clock
+	unsigned int speed)     // \arg UART baudrate
+{
+	//* Define the baud rate divisor register
+	pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetTimeguard
+//* \brief Set USART timeguard
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetTimeguard (
+	AT91PS_USART pUSART,    // \arg pointer to a USART controller
+	unsigned int timeguard) // \arg timeguard value
+{
+	//* Write the Timeguard Register
+	pUSART->US_TTGR = timeguard ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableIt
+//* \brief Enable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableIt (
+	AT91PS_USART pUSART, // \arg pointer to a USART controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pUSART->US_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableIt
+//* \brief Disable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableIt (
+	AT91PS_USART pUSART, // \arg pointer to a USART controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IER register
+	pUSART->US_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Configure
+//* \brief Configure USART
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Configure (
+	AT91PS_USART pUSART,     // \arg pointer to a USART controller
+	unsigned int mainClock,  // \arg peripheral clock
+	unsigned int mode ,      // \arg mode Register to be programmed
+	unsigned int baudRate ,  // \arg baudrate to be programmed
+	unsigned int timeguard ) // \arg timeguard to be programmed
+{
+    //* Disable interrupts
+    pUSART->US_IDR = (unsigned int) -1;
+
+    //* Reset receiver and transmitter
+    pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
+
+	//* Define the baud rate divisor register
+	AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
+
+	//* Write the Timeguard Register
+	AT91F_US_SetTimeguard(pUSART, timeguard);
+
+    //* Clear Transmit and Receive Counters
+    AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
+
+    //* Define the USART mode
+    pUSART->US_MR = mode  ;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableRx
+//* \brief Enable receiving characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Enable receiver
+    pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableTx
+//* \brief Enable sending characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Enable  transmitter
+    pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ResetRx
+//* \brief Reset Receiver and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+	//* Reset receiver
+	pUSART->US_CR = AT91C_US_RSTRX;
+    //* Re-Enable receiver
+    pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ResetTx
+//* \brief Reset Transmitter and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+	//* Reset transmitter
+	pUSART->US_CR = AT91C_US_RSTTX;
+    //* Enable transmitter
+    pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableRx
+//* \brief Disable Receiver
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Disable receiver
+    pUSART->US_CR = AT91C_US_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableTx
+//* \brief Disable Transmitter
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Disable transmitter
+    pUSART->US_CR = AT91C_US_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Close
+//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Close (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Reset the baud rate divisor register
+    pUSART->US_BRGR = 0 ;
+
+    //* Reset the USART mode
+    pUSART->US_MR = 0  ;
+
+    //* Reset the Timeguard Register
+    pUSART->US_TTGR = 0;
+
+    //* Disable all interrupts
+    pUSART->US_IDR = 0xFFFFFFFF ;
+
+    //* Abort the Peripheral Data Transfers
+    AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
+
+    //* Disable receiver and transmitter and stop any activity immediately
+    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_TxReady
+//* \brief Return 1 if a character can be written in US_THR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_TxReady (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR & AT91C_US_TXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_RxReady
+//* \brief Return 1 if a character can be read in US_RHR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_RxReady (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR & AT91C_US_RXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Error
+//* \brief Return the error flag
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Error (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR &
+    	(AT91C_US_OVRE |  // Overrun error
+    	 AT91C_US_FRAME | // Framing error
+    	 AT91C_US_PARE));  // Parity error
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_PutChar (
+	AT91PS_USART pUSART,
+	int character )
+{
+    pUSART->US_THR = (character & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_US_GetChar (
+	const AT91PS_USART pUSART)
+{
+    return((pUSART->US_RHR) & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_SendFrame(
+	AT91PS_USART pUSART,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pUSART->US_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_ReceiveFrame (
+	AT91PS_USART pUSART,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pUSART->US_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetIrdaFilter
+//* \brief Set the value of IrDa filter tregister
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetIrdaFilter (
+	AT91PS_USART pUSART,
+	unsigned char value
+)
+{
+	pUSART->US_IF = value;
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR UDP
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EnableIt
+//* \brief Enable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableIt (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pUDP->UDP_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_DisableIt
+//* \brief Disable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableIt (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pUDP->UDP_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_SetAddress
+//* \brief Set UDP functional address
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetAddress (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char address)   // \arg new UDP address
+{
+	pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EnableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableEp (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg endpoints to be enabled
+{
+	pUDP->UDP_GLBSTATE  |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_DisableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableEp (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg endpoints to be enabled
+{
+	pUDP->UDP_GLBSTATE  &= ~(flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_SetState
+//* \brief Set UDP Device state
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetState (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg new UDP address
+{
+	pUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
+	pUDP->UDP_GLBSTATE  |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_GetState
+//* \brief return UDP Device state
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
+	AT91PS_UDP pUDP)     // \arg pointer to a UDP controller
+{
+	return (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_ResetEp
+//* \brief Reset UDP endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg Endpoints to be reset
+{
+	pUDP->UDP_RSTEP = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpStall
+//* \brief Endpoint will STALL requests
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpStall(
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpWrite
+//* \brief Write value in the DPR
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpWrite(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned char value)     // \arg value to be written in the DPR
+{
+	pUDP->UDP_FDR[endpoint] = value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpRead
+//* \brief Return value from the DPR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpRead(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	return pUDP->UDP_FDR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpEndOfWr
+//* \brief Notify the UDP that values in DPR are ready to be sent
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpEndOfWr(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpClear
+//* \brief Clear flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpClear(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned int flag)       // \arg flag to be cleared
+{
+	pUDP->UDP_CSR[endpoint] &= ~(flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpSet
+//* \brief Set flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpSet(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned int flag)       // \arg flag to be cleared
+{
+	pUDP->UDP_CSR[endpoint] |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpStatus
+//* \brief Return the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpStatus(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	return pUDP->UDP_CSR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_GetInterruptMaskStatus
+//* \brief Return UDP Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
+        AT91PS_UDP pUdp) // \arg  pointer to a UDP controller
+{
+        return pUdp->UDP_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_IsInterruptMasked
+//* \brief Test if UDP Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_UDP_IsInterruptMasked(
+        AT91PS_UDP pUdp,   // \arg  pointer to a UDP controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR AIC
+   ***************************************************************************** */
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_ConfigureIt (
+	AT91PS_AIC pAic,  // \arg pointer to the AIC registers
+	unsigned int irq_id,     // \arg interrupt number to initialize
+	unsigned int priority,   // \arg priority to give to the interrupt
+	unsigned int src_type,   // \arg activation and sense of activation
+	void (*newHandler) (void) ) // \arg address of the interrupt handler
+{
+	unsigned int oldHandler;
+    unsigned int mask ;
+
+    oldHandler = pAic->AIC_SVR[irq_id];
+
+    mask = 0x1 << irq_id ;
+    //* Disable the interrupt on the interrupt controller
+    pAic->AIC_IDCR = mask ;
+    //* Save the interrupt handler routine pointer and the interrupt priority
+    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
+    //* Store the Source Mode Register
+    pAic->AIC_SMR[irq_id] = src_type | priority  ;
+    //* Clear the interrupt on the interrupt controller
+    pAic->AIC_ICCR = mask ;
+
+	return oldHandler;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_EnableIt
+//* \brief Enable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_EnableIt (
+	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
+	unsigned int irq_id ) // \arg interrupt number to initialize
+{
+    //* Enable the interrupt on the interrupt controller
+    pAic->AIC_IECR = 0x1 << irq_id ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_DisableIt
+//* \brief Disable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_DisableIt (
+	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
+	unsigned int irq_id ) // \arg interrupt number to initialize
+{
+    unsigned int mask = 0x1 << irq_id;
+    //* Disable the interrupt on the interrupt controller
+    pAic->AIC_IDCR = mask ;
+    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+    pAic->AIC_ICCR = mask ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ClearIt
+//* \brief Clear corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_ClearIt (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg interrupt number to initialize
+{
+    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+    pAic->AIC_ICCR = (0x1 << irq_id);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_AcknowledgeIt
+//* \brief Acknowledge corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_AcknowledgeIt (
+	AT91PS_AIC pAic)     // \arg pointer to the AIC registers
+{
+    pAic->AIC_EOICR = pAic->AIC_EOICR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_SetExceptionVector
+//* \brief Configure vector handler
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_SetExceptionVector (
+	unsigned int *pVector, // \arg pointer to the AIC registers
+	void (*Handler) () )   // \arg Interrupt Handler
+{
+	unsigned int oldVector = *pVector;
+
+	if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
+		*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
+	else
+		*pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
+
+	return oldVector;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_Trig
+//* \brief Trig an IT
+//*----------------------------------------------------------------------------
+__inline void  AT91F_AIC_Trig (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg interrupt number
+{
+	pAic->AIC_ISCR = (0x1 << irq_id) ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_IsActive
+//* \brief Test if an IT is active
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_IsActive (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg Interrupt Number
+{
+	return (pAic->AIC_ISR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_IsPending
+//* \brief Test if an IT is pending
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_IsPending (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg Interrupt Number
+{
+	return (pAic->AIC_IPR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_Open
+//* \brief Set exception vectors and AIC registers to default values
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Open(
+	AT91PS_AIC pAic,        // \arg pointer to the AIC registers
+	void (*IrqHandler) (),  // \arg Default IRQ vector exception
+	void (*FiqHandler) (),  // \arg Default FIQ vector exception
+	void (*DefaultHandler)  (), // \arg Default Handler set in ISR
+	void (*SpuriousHandler) (), // \arg Default Spurious Handler
+	unsigned int protectMode)   // \arg Debug Control Register
+{
+	int i;
+
+	// Disable all interrupts and set IVR to the default handler
+	for (i = 0; i < 32; ++i) {
+		AT91F_AIC_DisableIt(pAic, i);
+		AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler);
+	}
+
+	// Set the IRQ exception vector
+	AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
+	// Set the Fast Interrupt exception vector
+	AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
+
+	pAic->AIC_SPU = (unsigned int) SpuriousHandler;
+	pAic->AIC_DCR = protectMode;
+}
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  MC
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  DBGU
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_CfgPIO
+//* \brief Configure PIO controllers to drive DBGU signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA10_DTXD    ) |
+		((unsigned int) AT91C_PA9_DRXD    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH3_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH3 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH3_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA14_PWM3    ) |
+		((unsigned int) AT91C_PA7_PWM3    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH2_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH2_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA2_PWM2    ), // Peripheral A
+		((unsigned int) AT91C_PA25_PWM2    ) |
+		((unsigned int) AT91C_PA13_PWM2    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH1_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA1_PWM1    ), // Peripheral A
+		((unsigned int) AT91C_PA24_PWM1    ) |
+		((unsigned int) AT91C_PA12_PWM1    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH0_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA0_PWM0    ), // Peripheral A
+		((unsigned int) AT91C_PA23_PWM0    ) |
+		((unsigned int) AT91C_PA11_PWM0    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SSC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_CfgPIO
+//* \brief Configure PIO controllers to drive SSC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA17_TD      ) |
+		((unsigned int) AT91C_PA15_TF      ) |
+		((unsigned int) AT91C_PA19_RK      ) |
+		((unsigned int) AT91C_PA18_RD      ) |
+		((unsigned int) AT91C_PA20_RF      ) |
+		((unsigned int) AT91C_PA16_TK      ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SPI
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SPI));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgPIO
+//* \brief Configure PIO controllers to drive SPI signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA11_NPCS0   ) |
+		((unsigned int) AT91C_PA13_MOSI    ) |
+		((unsigned int) AT91C_PA31_NPCS1   ) |
+		((unsigned int) AT91C_PA12_MISO    ) |
+		((unsigned int) AT91C_PA14_SPCK    ), // Peripheral A
+		((unsigned int) AT91C_PA9_NPCS1   ) |
+		((unsigned int) AT91C_PA30_NPCS2   ) |
+		((unsigned int) AT91C_PA10_NPCS2   ) |
+		((unsigned int) AT91C_PA22_NPCS3   ) |
+		((unsigned int) AT91C_PA3_NPCS3   ) |
+		((unsigned int) AT91C_PA5_NPCS3   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PWMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PWMC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC2_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC2
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC2));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC2_CfgPIO
+//* \brief Configure PIO controllers to drive TC2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA26_TIOA2   ) |
+		((unsigned int) AT91C_PA27_TIOB2   ) |
+		((unsigned int) AT91C_PA29_TCLK2   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC1
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC1_CfgPIO
+//* \brief Configure PIO controllers to drive TC1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA15_TIOA1   ) |
+		((unsigned int) AT91C_PA16_TIOB1   ) |
+		((unsigned int) AT91C_PA28_TCLK1   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC0
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC0_CfgPIO
+//* \brief Configure PIO controllers to drive TC0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA0_TIOA0   ) |
+		((unsigned int) AT91C_PA1_TIOB0   ) |
+		((unsigned int) AT91C_PA4_TCLK0   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgPIO
+//* \brief Configure PIO controllers to drive PMC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA17_PCK1    ) |
+		((unsigned int) AT91C_PA21_PCK1    ) |
+		((unsigned int) AT91C_PA31_PCK2    ) |
+		((unsigned int) AT91C_PA18_PCK2    ) |
+		((unsigned int) AT91C_PA6_PCK0    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  ADC
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_ADC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgPIO
+//* \brief Configure PIO controllers to drive ADC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA8_ADTRG   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIOA_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PIOA
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOA_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PIOA));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TWI
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TWI));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_CfgPIO
+//* \brief Configure PIO controllers to drive TWI signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA3_TWD     ) |
+		((unsigned int) AT91C_PA4_TWCK    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  US1
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_US1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US1_CfgPIO
+//* \brief Configure PIO controllers to drive US1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA21_RXD1    ) |
+		((unsigned int) AT91C_PA27_DTR1    ) |
+		((unsigned int) AT91C_PA26_DCD1    ) |
+		((unsigned int) AT91C_PA22_TXD1    ) |
+		((unsigned int) AT91C_PA24_RTS1    ) |
+		((unsigned int) AT91C_PA23_SCK1    ) |
+		((unsigned int) AT91C_PA28_DSR1    ) |
+		((unsigned int) AT91C_PA29_RI1     ) |
+		((unsigned int) AT91C_PA25_CTS1    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  US0
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_US0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US0_CfgPIO
+//* \brief Configure PIO controllers to drive US0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA5_RXD0    ) |
+		((unsigned int) AT91C_PA6_TXD0    ) |
+		((unsigned int) AT91C_PA7_RTS0    ) |
+		((unsigned int) AT91C_PA8_CTS0    ), // Peripheral A
+		((unsigned int) AT91C_PA2_SCK0    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  UDP
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_UDP));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  AIC
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_IRQ0) |
+		((unsigned int) 1 << AT91C_ID_FIQ) |
+		((unsigned int) 1 << AT91C_ID_IRQ1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_CfgPIO
+//* \brief Configure PIO controllers to drive AIC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA30_IRQ1    ), // Peripheral A
+		((unsigned int) AT91C_PA20_IRQ0    ) |
+		((unsigned int) AT91C_PA19_FIQ     )); // Peripheral B
+}
+
+#endif // lib_AT91SAM7S64_H
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
new file mode 100644
index 0000000..805a2bc
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
@@ -0,0 +1,4558 @@
+//* ----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//* ----------------------------------------------------------------------------
+//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//* ----------------------------------------------------------------------------
+//* File Name           : lib_AT91SAM7X128.h
+//* Object              : AT91SAM7X128 inlined functions
+//* Generated           : AT91 SW Application Group  05/20/2005 (16:22:23)
+//*
+//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005//
+//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
+//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
+//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
+//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
+//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
+//* CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
+//* CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
+//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
+//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
+//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
+//* CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
+//* CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
+//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
+//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
+//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
+//* ----------------------------------------------------------------------------
+
+#ifndef lib_AT91SAM7X128_H
+#define lib_AT91SAM7X128_H
+
+/* *****************************************************************************
+                SOFTWARE API FOR AIC
+   ***************************************************************************** */
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_ConfigureIt (
+	AT91PS_AIC pAic,  // \arg pointer to the AIC registers
+	unsigned int irq_id,     // \arg interrupt number to initialize
+	unsigned int priority,   // \arg priority to give to the interrupt
+	unsigned int src_type,   // \arg activation and sense of activation
+	void (*newHandler) (void) ) // \arg address of the interrupt handler
+{
+	unsigned int oldHandler;
+    unsigned int mask ;
+
+    oldHandler = pAic->AIC_SVR[irq_id];
+
+    mask = 0x1 << irq_id ;
+    //* Disable the interrupt on the interrupt controller
+    pAic->AIC_IDCR = mask ;
+    //* Save the interrupt handler routine pointer and the interrupt priority
+    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
+    //* Store the Source Mode Register
+    pAic->AIC_SMR[irq_id] = src_type | priority  ;
+    //* Clear the interrupt on the interrupt controller
+    pAic->AIC_ICCR = mask ;
+
+	return oldHandler;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_EnableIt
+//* \brief Enable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_EnableIt (
+	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
+	unsigned int irq_id ) // \arg interrupt number to initialize
+{
+    //* Enable the interrupt on the interrupt controller
+    pAic->AIC_IECR = 0x1 << irq_id ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_DisableIt
+//* \brief Disable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_DisableIt (
+	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
+	unsigned int irq_id ) // \arg interrupt number to initialize
+{
+    unsigned int mask = 0x1 << irq_id;
+    //* Disable the interrupt on the interrupt controller
+    pAic->AIC_IDCR = mask ;
+    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+    pAic->AIC_ICCR = mask ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ClearIt
+//* \brief Clear corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_ClearIt (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg interrupt number to initialize
+{
+    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+    pAic->AIC_ICCR = (0x1 << irq_id);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_AcknowledgeIt
+//* \brief Acknowledge corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_AcknowledgeIt (
+	AT91PS_AIC pAic)     // \arg pointer to the AIC registers
+{
+    pAic->AIC_EOICR = pAic->AIC_EOICR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_SetExceptionVector
+//* \brief Configure vector handler
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_SetExceptionVector (
+	unsigned int *pVector, // \arg pointer to the AIC registers
+	void (*Handler) () )   // \arg Interrupt Handler
+{
+	unsigned int oldVector = *pVector;
+
+	if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
+		*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
+	else
+		*pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
+
+	return oldVector;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_Trig
+//* \brief Trig an IT
+//*----------------------------------------------------------------------------
+__inline void  AT91F_AIC_Trig (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg interrupt number
+{
+	pAic->AIC_ISCR = (0x1 << irq_id) ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_IsActive
+//* \brief Test if an IT is active
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_IsActive (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg Interrupt Number
+{
+	return (pAic->AIC_ISR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_IsPending
+//* \brief Test if an IT is pending
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_IsPending (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg Interrupt Number
+{
+	return (pAic->AIC_IPR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_Open
+//* \brief Set exception vectors and AIC registers to default values
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Open(
+	AT91PS_AIC pAic,        // \arg pointer to the AIC registers
+	void (*IrqHandler) (),  // \arg Default IRQ vector exception
+	void (*FiqHandler) (),  // \arg Default FIQ vector exception
+	void (*DefaultHandler)  (), // \arg Default Handler set in ISR
+	void (*SpuriousHandler) (), // \arg Default Spurious Handler
+	unsigned int protectMode)   // \arg Debug Control Register
+{
+	int i;
+
+	// Disable all interrupts and set IVR to the default handler
+	for (i = 0; i < 32; ++i) {
+		AT91F_AIC_DisableIt(pAic, i);
+		AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
+	}
+
+	// Set the IRQ exception vector
+	AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
+	// Set the Fast Interrupt exception vector
+	AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
+
+	pAic->AIC_SPU = (unsigned int) SpuriousHandler;
+	pAic->AIC_DCR = protectMode;
+}
+/* *****************************************************************************
+                SOFTWARE API FOR PDC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetNextRx
+//* \brief Set the next receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextRx (
+	AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
+	char *address,       // \arg address to the next bloc to be received
+	unsigned int bytes)  // \arg number of bytes to be received
+{
+	pPDC->PDC_RNPR = (unsigned int) address;
+	pPDC->PDC_RNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetNextTx
+//* \brief Set the next transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextTx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be transmitted
+	unsigned int bytes)    // \arg number of bytes to be transmitted
+{
+	pPDC->PDC_TNPR = (unsigned int) address;
+	pPDC->PDC_TNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetRx
+//* \brief Set the receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetRx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be received
+	unsigned int bytes)    // \arg number of bytes to be received
+{
+	pPDC->PDC_RPR = (unsigned int) address;
+	pPDC->PDC_RCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetTx
+//* \brief Set the transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetTx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be transmitted
+	unsigned int bytes)    // \arg number of bytes to be transmitted
+{
+	pPDC->PDC_TPR = (unsigned int) address;
+	pPDC->PDC_TCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_EnableTx
+//* \brief Enable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableTx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_EnableRx
+//* \brief Enable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableRx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_DisableTx
+//* \brief Disable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableTx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_DisableRx
+//* \brief Disable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableRx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsTxEmpty
+//* \brief Test if the current transfer descriptor has been sent
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_TCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsNextTxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_TNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsRxEmpty
+//* \brief Test if the current transfer descriptor has been filled
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_RCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsNextRxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_RNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_Open
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Open (
+	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+{
+    //* Disable the RX and TX PDC transfer requests
+	AT91F_PDC_DisableRx(pPDC);
+	AT91F_PDC_DisableTx(pPDC);
+
+	//* Reset all Counter register Next buffer first
+	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+    //* Enable the RX and TX PDC transfer requests
+	AT91F_PDC_EnableRx(pPDC);
+	AT91F_PDC_EnableTx(pPDC);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_Close
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Close (
+	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+{
+    //* Disable the RX and TX PDC transfer requests
+	AT91F_PDC_DisableRx(pPDC);
+	AT91F_PDC_DisableTx(pPDC);
+
+	//* Reset all Counter register Next buffer first
+	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SendFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_SendFrame(
+	AT91PS_PDC pPDC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	if (AT91F_PDC_IsTxEmpty(pPDC)) {
+		//* Buffer and next buffer can be initialized
+		AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
+		AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
+		return 2;
+	}
+	else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
+		//* Only one buffer can be initialized
+		AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
+		return 1;
+	}
+	else {
+		//* All buffer are in use...
+		return 0;
+	}
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_ReceiveFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_ReceiveFrame (
+	AT91PS_PDC pPDC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	if (AT91F_PDC_IsRxEmpty(pPDC)) {
+		//* Buffer and next buffer can be initialized
+		AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
+		AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
+		return 2;
+	}
+	else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
+		//* Only one buffer can be initialized
+		AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
+		return 1;
+	}
+	else {
+		//* All buffer are in use...
+		return 0;
+	}
+}
+/* *****************************************************************************
+                SOFTWARE API FOR DBGU
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_InterruptEnable
+//* \brief Enable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptEnable(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  dbgu interrupt to be enabled
+{
+        pDbgu->DBGU_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_InterruptDisable
+//* \brief Disable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptDisable(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  dbgu interrupt to be disabled
+{
+        pDbgu->DBGU_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_GetInterruptMaskStatus
+//* \brief Return DBGU Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
+        AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
+{
+        return pDbgu->DBGU_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_IsInterruptMasked
+//* \brief Test if DBGU Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_DBGU_IsInterruptMasked(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PIO
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgPeriph
+//* \brief Enable pins to be drived by peripheral
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPeriph(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int periphAEnable,  // \arg PERIPH A to enable
+	unsigned int periphBEnable)  // \arg PERIPH B to enable
+
+{
+	pPio->PIO_ASR = periphAEnable;
+	pPio->PIO_BSR = periphBEnable;
+	pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgOutput
+//* \brief Enable PIO in output mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOutput(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int pioEnable)      // \arg PIO to be enabled
+{
+	pPio->PIO_PER = pioEnable; // Set in PIO mode
+	pPio->PIO_OER = pioEnable; // Configure in Output
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgInput
+//* \brief Enable PIO in input mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInput(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int inputEnable)      // \arg PIO to be enabled
+{
+	// Disable output
+	pPio->PIO_ODR  = inputEnable;
+	pPio->PIO_PER  = inputEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgOpendrain
+//* \brief Configure PIO in open drain
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOpendrain(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int multiDrvEnable) // \arg pio to be configured in open drain
+{
+	// Configure the multi-drive option
+	pPio->PIO_MDDR = ~multiDrvEnable;
+	pPio->PIO_MDER = multiDrvEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgPullup
+//* \brief Enable pullup on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPullup(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int pullupEnable)   // \arg enable pullup on PIO
+{
+		// Connect or not Pullup
+	pPio->PIO_PPUDR = ~pullupEnable;
+	pPio->PIO_PPUER = pullupEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgDirectDrive
+//* \brief Enable direct drive on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgDirectDrive(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int directDrive)    // \arg PIO to be configured with direct drive
+
+{
+	// Configure the Direct Drive
+	pPio->PIO_OWDR  = ~directDrive;
+	pPio->PIO_OWER  = directDrive;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgInputFilter
+//* \brief Enable input filter on input PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInputFilter(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int inputFilter)    // \arg PIO to be configured with input filter
+
+{
+	// Configure the Direct Drive
+	pPio->PIO_IFDR  = ~inputFilter;
+	pPio->PIO_IFER  = inputFilter;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInput
+//* \brief Return PIO input value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
+	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+	return pPio->PIO_PDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInputSet
+//* \brief Test if PIO is input flag is active
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputSet(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PIO_GetInput(pPio) & flag);
+}
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_SetOutput
+//* \brief Set to 1 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_SetOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be set
+{
+	pPio->PIO_SODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_ClearOutput
+//* \brief Set to 0 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ClearOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be cleared
+{
+	pPio->PIO_CODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_ForceOutput
+//* \brief Force output when Direct drive option is enabled
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ForceOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be forced
+{
+	pPio->PIO_ODSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Enable
+//* \brief Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Enable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be enabled 
+{
+        pPio->PIO_PER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Disable
+//* \brief Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Disable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be disabled 
+{
+        pPio->PIO_PDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetStatus
+//* \brief Return PIO Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_PSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsSet
+//* \brief Test if PIO is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputEnable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output to be enabled
+{
+        pPio->PIO_OER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputDisable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output to be disabled
+{
+        pPio->PIO_ODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputStatus
+//* \brief Return PIO Output Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_OSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOuputSet
+//* \brief Test if PIO Output is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InputFilterEnable
+//* \brief Input Filter Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio input filter to be enabled
+{
+        pPio->PIO_IFER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InputFilterDisable
+//* \brief Input Filter Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio input filter to be disabled
+{
+        pPio->PIO_IFDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInputFilterStatus
+//* \brief Return PIO Input Filter Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_IFSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInputFilterSet
+//* \brief Test if PIO Input filter is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputFilterSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputDataStatus
+//* \brief Return PIO Output Data Status 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status 
+	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ODSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InterruptEnable
+//* \brief Enable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio interrupt to be enabled
+{
+        pPio->PIO_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InterruptDisable
+//* \brief Disable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio interrupt to be disabled
+{
+        pPio->PIO_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInterruptMaskStatus
+//* \brief Return PIO Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInterruptStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInterruptMasked
+//* \brief Test if PIO Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptMasked(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInterruptSet
+//* \brief Test if PIO Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_MultiDriverEnable
+//* \brief Multi Driver Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be enabled
+{
+        pPio->PIO_MDER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_MultiDriverDisable
+//* \brief Multi Driver Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be disabled
+{
+        pPio->PIO_MDDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetMultiDriverStatus
+//* \brief Return PIO Multi Driver Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_MDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsMultiDriverSet
+//* \brief Test if PIO MultiDriver is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsMultiDriverSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_A_RegisterSelection
+//* \brief PIO A Register Selection 
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_A_RegisterSelection(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio A register selection
+{
+        pPio->PIO_ASR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_B_RegisterSelection
+//* \brief PIO B Register Selection 
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_B_RegisterSelection(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio B register selection 
+{
+        pPio->PIO_BSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Get_AB_RegisterStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ABSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsAB_RegisterSet
+//* \brief Test if PIO AB Register is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsAB_RegisterSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputWriteEnable
+//* \brief Output Write Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output write to be enabled
+{
+        pPio->PIO_OWER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputWriteDisable
+//* \brief Output Write Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output write to be disabled
+{
+        pPio->PIO_OWDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputWriteStatus
+//* \brief Return PIO Output Write Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_OWSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOutputWriteSet
+//* \brief Test if PIO OutputWrite is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputWriteSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetCfgPullup
+//* \brief Return PIO Configuration Pullup
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup 
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_PPUSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOutputDataStatusSet
+//* \brief Test if PIO Output Data Status is Set 
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputDataStatusSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsCfgPullupStatusSet
+//* \brief Test if PIO Configuration Pullup Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsCfgPullupStatusSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PMC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgSysClkEnableReg
+//* \brief Configure the System Clock Enable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkEnableReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	//* Write to the SCER register
+	pPMC->PMC_SCER = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgSysClkDisableReg
+//* \brief Configure the System Clock Disable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkDisableReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	//* Write to the SCDR register
+	pPMC->PMC_SCDR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetSysClkStatusReg
+//* \brief Return the System Clock Status Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
+	AT91PS_PMC pPMC // pointer to a CAN controller
+	)
+{
+	return pPMC->PMC_SCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnablePeriphClock
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePeriphClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int periphIds)  // \arg IDs of peripherals to enable
+{
+	pPMC->PMC_PCER = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisablePeriphClock
+//* \brief Disable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePeriphClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int periphIds)  // \arg IDs of peripherals to enable
+{
+	pPMC->PMC_PCDR = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetPeriphClock
+//* \brief Get peripheral clock status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetPeriphClock (
+	AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+	return pPMC->PMC_PCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_CfgMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscillatorReg (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int mode)
+{
+	pCKGR->CKGR_MOR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	return pCKGR->CKGR_MOR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_EnableMainOscillator
+//* \brief Enable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_EnableMainOscillator(
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_DisableMainOscillator
+//* \brief Disable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_DisableMainOscillator (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
+//* \brief Cfg MOR Register according to the main osc startup time
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
+	pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainClockFreqReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	return pCKGR->CKGR_MCFR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainClock
+//* \brief Return Main clock in Hz
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClock (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgMCKReg
+//* \brief Cfg Master Clock Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgMCKReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	pPMC->PMC_MCKR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetMCKReg
+//* \brief Return Master Clock Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMCKReg(
+	AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+	return pPMC->PMC_MCKR;
+}
+
+//*------------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetMasterClock
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7
+//*------------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMasterClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	unsigned int reg = pPMC->PMC_MCKR;
+	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
+	unsigned int pllDivider, pllMultiplier;
+
+	switch (reg & AT91C_PMC_CSS) {
+		case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
+			return slowClock / prescaler;
+		case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
+			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
+		case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
+			reg = pCKGR->CKGR_PLLR;
+			pllDivider    = (reg  & AT91C_CKGR_DIV);
+			pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
+			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
+	}
+	return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePCK (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
+	unsigned int mode)
+{
+	pPMC->PMC_PCKR[pck] = mode;
+	pPMC->PMC_SCER = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePCK (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
+{
+	pPMC->PMC_SCDR = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnableIt
+//* \brief Enable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnableIt (
+	AT91PS_PMC pPMC,     // pointer to a PMC controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pPMC->PMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisableIt
+//* \brief Disable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisableIt (
+	AT91PS_PMC pPMC, // pointer to a PMC controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pPMC->PMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetStatus
+//* \brief Return PMC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
+	AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+	return pPMC->PMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetInterruptMaskStatus
+//* \brief Return PMC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
+	AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+	return pPMC->PMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_IsInterruptMasked
+//* \brief Test if PMC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsInterruptMasked(
+        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_IsStatusSet
+//* \brief Test if PMC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsStatusSet(
+        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PMC_GetStatus(pPMC) & flag);
+}/* *****************************************************************************
+                SOFTWARE API FOR RSTC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTSoftReset
+//* \brief Start Software Reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSoftReset(
+        AT91PS_RSTC pRSTC,
+        unsigned int reset)
+{
+	pRSTC->RSTC_RCR = (0xA5000000 | reset);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTSetMode
+//* \brief Set Reset Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSetMode(
+        AT91PS_RSTC pRSTC,
+        unsigned int mode)
+{
+	pRSTC->RSTC_RMR = (0xA5000000 | mode);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTGetMode
+//* \brief Get Reset Mode
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetMode(
+        AT91PS_RSTC pRSTC)
+{
+	return (pRSTC->RSTC_RMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTGetStatus
+//* \brief Get Reset Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetStatus(
+        AT91PS_RSTC pRSTC)
+{
+	return (pRSTC->RSTC_RSR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTIsSoftRstActive
+//* \brief Return !=0 if software reset is still not completed
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTIsSoftRstActive(
+        AT91PS_RSTC pRSTC)
+{
+	return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR RTTC
+   ***************************************************************************** */
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_SetRTT_TimeBase()
+//* \brief  Set the RTT prescaler according to the TimeBase in ms
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetTimeBase(
+        AT91PS_RTTC pRTTC, 
+        unsigned int ms)
+{
+	if (ms > 2000)
+		return 1;   // AT91C_TIME_OUT_OF_RANGE
+	pRTTC->RTTC_RTMR &= ~0xFFFF;	
+	pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);	
+	return 0;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTSetPrescaler()
+//* \brief  Set the new prescaler value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetPrescaler(
+        AT91PS_RTTC pRTTC, 
+        unsigned int rtpres)
+{
+	pRTTC->RTTC_RTMR &= ~0xFFFF;	
+	pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);	
+	return (pRTTC->RTTC_RTMR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTRestart()
+//* \brief  Restart the RTT prescaler
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTRestart(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;	
+}
+
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetAlarmINT()
+//* \brief  Enable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ClearAlarmINT()
+//* \brief  Disable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearAlarmINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetRttIncINT()
+//* \brief  Enable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetRttIncINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ClearRttIncINT()
+//* \brief  Disable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearRttIncINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetAlarmValue()
+//* \brief  Set RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmValue(
+        AT91PS_RTTC pRTTC, unsigned int alarm)
+{
+	pRTTC->RTTC_RTAR = alarm;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_GetAlarmValue()
+//* \brief  Get RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetAlarmValue(
+        AT91PS_RTTC pRTTC)
+{
+	return(pRTTC->RTTC_RTAR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTGetStatus()
+//* \brief  Read the RTT status
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetStatus(
+        AT91PS_RTTC pRTTC)
+{
+	return(pRTTC->RTTC_RTSR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ReadValue()
+//* \brief  Read the RTT value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTReadValue(
+        AT91PS_RTTC pRTTC)
+{
+        register volatile unsigned int val1,val2;
+	do
+	{
+		val1 = pRTTC->RTTC_RTVR;
+		val2 = pRTTC->RTTC_RTVR;
+	}	
+	while(val1 != val2);
+	return(val1);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR PITC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITInit
+//* \brief System timer init : period in µsecond, system clock freq in MHz
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITInit(
+        AT91PS_PITC pPITC,
+        unsigned int period,
+        unsigned int pit_frequency)
+{
+	pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
+	pPITC->PITC_PIMR |= AT91C_PITC_PITEN;	 
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITSetPIV
+//* \brief Set the PIT Periodic Interval Value 
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITSetPIV(
+        AT91PS_PITC pPITC,
+        unsigned int piv)
+{
+	pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITEnableInt
+//* \brief Enable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITEnableInt(
+        AT91PS_PITC pPITC)
+{
+	pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;	 
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITDisableInt
+//* \brief Disable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITDisableInt(
+        AT91PS_PITC pPITC)
+{
+	pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;	 
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetMode
+//* \brief Read PIT mode register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetMode(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetStatus
+//* \brief Read PIT status register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetStatus(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PISR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetPIIR
+//* \brief Read PIT CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIIR(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIIR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetPIVR
+//* \brief Read System timer CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIVR(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIVR);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR WDTC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTSetMode
+//* \brief Set Watchdog Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTSetMode(
+        AT91PS_WDTC pWDTC,
+        unsigned int Mode)
+{
+	pWDTC->WDTC_WDMR = Mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTRestart
+//* \brief Restart Watchdog
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTRestart(
+        AT91PS_WDTC pWDTC)
+{
+	pWDTC->WDTC_WDCR = 0xA5000001;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTSGettatus
+//* \brief Get Watchdog Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTSGettatus(
+        AT91PS_WDTC pWDTC)
+{
+	return(pWDTC->WDTC_WDSR & 0x3);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTGetPeriod
+//* \brief Translate ms into Watchdog Compatible value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)
+{
+	if ((ms < 4) || (ms > 16000))
+		return 0;
+	return((ms << 8) / 1000);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR VREG
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_Enable_LowPowerMode
+//* \brief Enable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Enable_LowPowerMode(
+        AT91PS_VREG pVREG)
+{
+	pVREG->VREG_MR |= AT91C_VREG_PSTDBY;	 
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_Disable_LowPowerMode
+//* \brief Disable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Disable_LowPowerMode(
+        AT91PS_VREG pVREG)
+{
+	pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;	 
+}/* *****************************************************************************
+                SOFTWARE API FOR MC
+   ***************************************************************************** */
+
+#define AT91C_MC_CORRECT_KEY  ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_Remap
+//* \brief Make Remap
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_Remap (void)     //  
+{
+    AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
+    
+    pMC->MC_RCR = AT91C_MC_RCB;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_CfgModeReg
+//* \brief Configure the EFC Mode Register of the MC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_CfgModeReg (
+	AT91PS_MC pMC, // pointer to a MC controller
+	unsigned int mode)        // mode register 
+{
+	// Write to the FMR register
+	pMC->MC_FMR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_GetModeReg
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetModeReg(
+	AT91PS_MC pMC) // pointer to a MC controller
+{
+	return pMC->MC_FMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_ComputeFMCN
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
+	int master_clock) // master clock in Hz
+{
+	return (master_clock/1000000 +2);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_PerformCmd
+//* \brief Perform EFC Command
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_PerformCmd (
+	AT91PS_MC pMC, // pointer to a MC controller
+    unsigned int transfer_cmd)
+{
+	pMC->MC_FCR = transfer_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_GetStatus
+//* \brief Return MC EFC Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetStatus(
+	AT91PS_MC pMC) // pointer to a MC controller
+{
+	return pMC->MC_FSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_IsInterruptMasked
+//* \brief Test if EFC MC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
+        AT91PS_MC pMC,   // \arg  pointer to a MC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_IsInterruptSet
+//* \brief Test if EFC MC Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
+        AT91PS_MC pMC,   // \arg  pointer to a MC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_MC_EFC_GetStatus(pMC) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR SPI
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Open
+//* \brief Open a SPI Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_Open (
+        const unsigned int null)  // \arg
+{
+        /* NOT DEFINED AT THIS MOMENT */
+        return ( 0 );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgCs
+//* \brief Configure SPI chip select register
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgCs (
+	AT91PS_SPI pSPI,     // pointer to a SPI controller
+	int cs,     // SPI cs number (0 to 3)
+ 	int val)   //  chip select register
+{
+	//* Write to the CSR register
+	*(pSPI->SPI_CSR + cs) = val;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_EnableIt
+//* \brief Enable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_EnableIt (
+	AT91PS_SPI pSPI,     // pointer to a SPI controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pSPI->SPI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_DisableIt
+//* \brief Disable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_DisableIt (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pSPI->SPI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Reset
+//* \brief Reset the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Reset (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SWRST;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Enable
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Enable (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SPIEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Disable
+//* \brief Disable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Disable (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgMode
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgMode (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	int mode)        // mode register 
+{
+	//* Write to the MR register
+	pSPI->SPI_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgPCS
+//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPCS (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	char PCS_Device) // PCS of the Device
+{	
+ 	//* Write to the MR register
+	pSPI->SPI_MR &= 0xFFF0FFFF;
+	pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_ReceiveFrame (
+	AT91PS_SPI pSPI,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pSPI->SPI_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_SendFrame(
+	AT91PS_SPI pSPI,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pSPI->SPI_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Close
+//* \brief Close SPI: disable IT disable transfert, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Close (
+	AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
+{
+    //* Reset all the Chip Select register
+    pSPI->SPI_CSR[0] = 0 ;
+    pSPI->SPI_CSR[1] = 0 ;
+    pSPI->SPI_CSR[2] = 0 ;
+    pSPI->SPI_CSR[3] = 0 ;
+
+    //* Reset the SPI mode
+    pSPI->SPI_MR = 0  ;
+
+    //* Disable all interrupts
+    pSPI->SPI_IDR = 0xFFFFFFFF ;
+
+    //* Abort the Peripheral Data Transfers
+    AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
+
+    //* Disable receiver and transmitter and stop any activity immediately
+    pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_PutChar (
+	AT91PS_SPI pSPI,
+	unsigned int character,
+             unsigned int cs_number )
+{
+    unsigned int value_for_cs;
+    value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number
+    pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_GetChar (
+	const AT91PS_SPI pSPI)
+{
+    return((pSPI->SPI_RDR) & 0xFFFF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_GetInterruptMaskStatus
+//* \brief Return SPI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
+        AT91PS_SPI pSpi) // \arg  pointer to a SPI controller
+{
+        return pSpi->SPI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_IsInterruptMasked
+//* \brief Test if SPI Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_IsInterruptMasked(
+        AT91PS_SPI pSpi,   // \arg  pointer to a SPI controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR USART
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Baudrate
+//* \brief Calculate the baudrate
+//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
+                        AT91C_US_NBSTOP_1_BIT + \
+                        AT91C_US_PAR_NONE + \
+                        AT91C_US_CHRL_8_BITS + \
+                        AT91C_US_CLKS_CLOCK )
+
+//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
+                            AT91C_US_NBSTOP_1_BIT + \
+                            AT91C_US_PAR_NONE + \
+                            AT91C_US_CHRL_8_BITS + \
+                            AT91C_US_CLKS_EXT )
+
+//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
+                       AT91C_US_USMODE_NORMAL + \
+                       AT91C_US_NBSTOP_1_BIT + \
+                       AT91C_US_PAR_NONE + \
+                       AT91C_US_CHRL_8_BITS + \
+                       AT91C_US_CLKS_CLOCK )
+
+//* SCK used Label
+#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
+
+//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
+#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
+					   		 AT91C_US_CLKS_CLOCK +\
+                       		 AT91C_US_NBSTOP_1_BIT + \
+                       		 AT91C_US_PAR_EVEN + \
+                       		 AT91C_US_CHRL_8_BITS + \
+                       		 AT91C_US_CKLO +\
+                       		 AT91C_US_OVER)
+
+//* Standard IRDA mode
+#define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \
+                            AT91C_US_NBSTOP_1_BIT + \
+                            AT91C_US_PAR_NONE + \
+                            AT91C_US_CHRL_8_BITS + \
+                            AT91C_US_CLKS_CLOCK )
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Baudrate
+//* \brief Caluculate baud_value according to the main clock and the baud rate
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Baudrate (
+	const unsigned int main_clock, // \arg peripheral clock
+	const unsigned int baud_rate)  // \arg UART baudrate
+{
+	unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
+	if ((baud_value % 10) >= 5)
+		baud_value = (baud_value / 10) + 1;
+	else
+		baud_value /= 10;
+	return baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetBaudrate (
+	AT91PS_USART pUSART,    // \arg pointer to a USART controller
+	unsigned int mainClock, // \arg peripheral clock
+	unsigned int speed)     // \arg UART baudrate
+{
+	//* Define the baud rate divisor register
+	pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetTimeguard
+//* \brief Set USART timeguard
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetTimeguard (
+	AT91PS_USART pUSART,    // \arg pointer to a USART controller
+	unsigned int timeguard) // \arg timeguard value
+{
+	//* Write the Timeguard Register
+	pUSART->US_TTGR = timeguard ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableIt
+//* \brief Enable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableIt (
+	AT91PS_USART pUSART, // \arg pointer to a USART controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pUSART->US_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableIt
+//* \brief Disable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableIt (
+	AT91PS_USART pUSART, // \arg pointer to a USART controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IER register
+	pUSART->US_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Configure
+//* \brief Configure USART
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Configure (
+	AT91PS_USART pUSART,     // \arg pointer to a USART controller
+	unsigned int mainClock,  // \arg peripheral clock
+	unsigned int mode ,      // \arg mode Register to be programmed
+	unsigned int baudRate ,  // \arg baudrate to be programmed
+	unsigned int timeguard ) // \arg timeguard to be programmed
+{
+    //* Disable interrupts
+    pUSART->US_IDR = (unsigned int) -1;
+
+    //* Reset receiver and transmitter
+    pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
+
+	//* Define the baud rate divisor register
+	AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
+
+	//* Write the Timeguard Register
+	AT91F_US_SetTimeguard(pUSART, timeguard);
+
+    //* Clear Transmit and Receive Counters
+    AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
+
+    //* Define the USART mode
+    pUSART->US_MR = mode  ;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableRx
+//* \brief Enable receiving characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Enable receiver
+    pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableTx
+//* \brief Enable sending characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Enable  transmitter
+    pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ResetRx
+//* \brief Reset Receiver and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+	//* Reset receiver
+	pUSART->US_CR = AT91C_US_RSTRX;
+    //* Re-Enable receiver
+    pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ResetTx
+//* \brief Reset Transmitter and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+	//* Reset transmitter
+	pUSART->US_CR = AT91C_US_RSTTX;
+    //* Enable transmitter
+    pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableRx
+//* \brief Disable Receiver
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Disable receiver
+    pUSART->US_CR = AT91C_US_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableTx
+//* \brief Disable Transmitter
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Disable transmitter
+    pUSART->US_CR = AT91C_US_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Close
+//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Close (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Reset the baud rate divisor register
+    pUSART->US_BRGR = 0 ;
+
+    //* Reset the USART mode
+    pUSART->US_MR = 0  ;
+
+    //* Reset the Timeguard Register
+    pUSART->US_TTGR = 0;
+
+    //* Disable all interrupts
+    pUSART->US_IDR = 0xFFFFFFFF ;
+
+    //* Abort the Peripheral Data Transfers
+    AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
+
+    //* Disable receiver and transmitter and stop any activity immediately
+    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_TxReady
+//* \brief Return 1 if a character can be written in US_THR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_TxReady (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR & AT91C_US_TXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_RxReady
+//* \brief Return 1 if a character can be read in US_RHR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_RxReady (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR & AT91C_US_RXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Error
+//* \brief Return the error flag
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Error (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR &
+    	(AT91C_US_OVRE |  // Overrun error
+    	 AT91C_US_FRAME | // Framing error
+    	 AT91C_US_PARE));  // Parity error
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_PutChar (
+	AT91PS_USART pUSART,
+	int character )
+{
+    pUSART->US_THR = (character & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_US_GetChar (
+	const AT91PS_USART pUSART)
+{
+    return((pUSART->US_RHR) & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_SendFrame(
+	AT91PS_USART pUSART,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pUSART->US_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_ReceiveFrame (
+	AT91PS_USART pUSART,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pUSART->US_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetIrdaFilter
+//* \brief Set the value of IrDa filter tregister
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetIrdaFilter (
+	AT91PS_USART pUSART,
+	unsigned char value
+)
+{
+	pUSART->US_IF = value;
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR SSC
+   ***************************************************************************** */
+//* Define the standard I2S mode configuration
+
+//* Configuration to set in the SSC Transmit Clock Mode Register
+//* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
+//* 			  nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+									   AT91C_SSC_CKS_DIV   +\
+                            		   AT91C_SSC_CKO_CONTINOUS      +\
+                            		   AT91C_SSC_CKG_NONE    +\
+                                       AT91C_SSC_START_FALL_RF +\
+                           			   AT91C_SSC_STTOUT  +\
+                            		   ((1<<16) & AT91C_SSC_STTDLY) +\
+                            		   ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
+
+
+//* Configuration to set in the SSC Transmit Frame Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* 			 nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+									(nb_bit_by_slot-1)  +\
+                            		AT91C_SSC_MSBF   +\
+                            		(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
+                            		(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
+                            		AT91C_SSC_FSOS_NEGATIVE)
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_SetBaudrate (
+        AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
+        unsigned int mainClock, // \arg peripheral clock
+        unsigned int speed)     // \arg SSC baudrate
+{
+        unsigned int baud_value;
+        //* Define the baud rate divisor register
+        if (speed == 0)
+           baud_value = 0;
+        else
+        {
+           baud_value = (unsigned int) (mainClock * 10)/(2*speed);
+           if ((baud_value % 10) >= 5)
+                  baud_value = (baud_value / 10) + 1;
+           else
+                  baud_value /= 10;
+        }
+
+        pSSC->SSC_CMR = baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_Configure
+//* \brief Configure SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_Configure (
+             AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
+             unsigned int syst_clock,  // \arg System Clock Frequency
+             unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
+             unsigned int clock_rx,    // \arg Receiver Clock Parameters
+             unsigned int mode_rx,     // \arg mode Register to be programmed
+             unsigned int clock_tx,    // \arg Transmitter Clock Parameters
+             unsigned int mode_tx)     // \arg mode Register to be programmed
+{
+    //* Disable interrupts
+	pSSC->SSC_IDR = (unsigned int) -1;
+
+    //* Reset receiver and transmitter
+	pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
+
+    //* Define the Clock Mode Register
+	AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
+
+     //* Write the Receive Clock Mode Register
+	pSSC->SSC_RCMR =  clock_rx;
+
+     //* Write the Transmit Clock Mode Register
+	pSSC->SSC_TCMR =  clock_tx;
+
+     //* Write the Receive Frame Mode Register
+	pSSC->SSC_RFMR =  mode_rx;
+
+     //* Write the Transmit Frame Mode Register
+	pSSC->SSC_TFMR =  mode_tx;
+
+    //* Clear Transmit and Receive Counters
+	AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
+
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableRx
+//* \brief Enable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableRx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Enable receiver
+    pSSC->SSC_CR = AT91C_SSC_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableRx
+//* \brief Disable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableRx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Disable receiver
+    pSSC->SSC_CR = AT91C_SSC_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableTx
+//* \brief Enable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableTx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Enable  transmitter
+    pSSC->SSC_CR = AT91C_SSC_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableTx
+//* \brief Disable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableTx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Disable  transmitter
+    pSSC->SSC_CR = AT91C_SSC_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableIt
+//* \brief Enable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableIt (
+	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pSSC->SSC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableIt
+//* \brief Disable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableIt (
+	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pSSC->SSC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_ReceiveFrame (
+	AT91PS_SSC pSSC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pSSC->SSC_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_SendFrame(
+	AT91PS_SSC pSSC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pSSC->SSC_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_GetInterruptMaskStatus
+//* \brief Return SSC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
+        AT91PS_SSC pSsc) // \arg  pointer to a SSC controller
+{
+        return pSsc->SSC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_IsInterruptMasked
+//* \brief Test if SSC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_SSC_IsInterruptMasked(
+        AT91PS_SSC pSsc,   // \arg  pointer to a SSC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TWI
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_EnableIt
+//* \brief Enable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_EnableIt (
+	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pTWI->TWI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_DisableIt
+//* \brief Disable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_DisableIt (
+	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pTWI->TWI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_Configure
+//* \brief Configure TWI in master mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \arg pointer to a TWI controller
+{
+    //* Disable interrupts
+	pTWI->TWI_IDR = (unsigned int) -1;
+
+    //* Reset peripheral
+	pTWI->TWI_CR = AT91C_TWI_SWRST;
+
+	//* Set Master mode
+	pTWI->TWI_CR = AT91C_TWI_MSEN;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_GetInterruptMaskStatus
+//* \brief Return TWI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
+        AT91PS_TWI pTwi) // \arg  pointer to a TWI controller
+{
+        return pTwi->TWI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_IsInterruptMasked
+//* \brief Test if TWI Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_TWI_IsInterruptMasked(
+        AT91PS_TWI pTwi,   // \arg  pointer to a TWI controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PWMC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_GetStatus
+//* \brief Return PWM Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
+	AT91PS_PWMC pPWM) // pointer to a PWM controller
+{
+	return pPWM->PWMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_InterruptEnable
+//* \brief Enable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptEnable(
+        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  PWM interrupt to be enabled
+{
+        pPwm->PWMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_InterruptDisable
+//* \brief Disable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptDisable(
+        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  PWM interrupt to be disabled
+{
+        pPwm->PWMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_GetInterruptMaskStatus
+//* \brief Return PWM Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
+        AT91PS_PWMC pPwm) // \arg  pointer to a PWM controller
+{
+        return pPwm->PWMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_IsInterruptMasked
+//* \brief Test if PWM Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsInterruptMasked(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_IsStatusSet
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsStatusSet(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PWMC_GetStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_CfgChannel
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int channelId, // \arg PWM channel ID
+        unsigned int mode, // \arg  PWM mode
+        unsigned int period, // \arg PWM period
+        unsigned int duty) // \arg PWM duty cycle
+{
+	pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
+	pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
+	pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_StartChannel
+//* \brief Enable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StartChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_ENA = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_StopChannel
+//* \brief Disable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StopChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_DIS = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_UpdateChannel
+//* \brief Update Period or Duty Cycle
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_UpdateChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int channelId, // \arg PWM channel ID
+        unsigned int update) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR UDP
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EnableIt
+//* \brief Enable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableIt (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pUDP->UDP_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_DisableIt
+//* \brief Disable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableIt (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pUDP->UDP_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_SetAddress
+//* \brief Set UDP functional address
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetAddress (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char address)   // \arg new UDP address
+{
+	pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EnableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableEp (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_DisableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableEp (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_SetState
+//* \brief Set UDP Device state
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetState (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg new UDP address
+{
+	pUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
+	pUDP->UDP_GLBSTATE  |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_GetState
+//* \brief return UDP Device state
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
+	AT91PS_UDP pUDP)     // \arg pointer to a UDP controller
+{
+	return (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_ResetEp
+//* \brief Reset UDP endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg Endpoints to be reset
+{
+	pUDP->UDP_RSTEP = flag;
+	pUDP->UDP_RSTEP = 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpStall
+//* \brief Endpoint will STALL requests
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpStall(
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpWrite
+//* \brief Write value in the DPR
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpWrite(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned char value)     // \arg value to be written in the DPR
+{
+	pUDP->UDP_FDR[endpoint] = value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpRead
+//* \brief Return value from the DPR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpRead(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	return pUDP->UDP_FDR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpEndOfWr
+//* \brief Notify the UDP that values in DPR are ready to be sent
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpEndOfWr(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpClear
+//* \brief Clear flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpClear(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned int flag)       // \arg flag to be cleared
+{
+	pUDP->UDP_CSR[endpoint] &= ~(flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpSet
+//* \brief Set flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpSet(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned int flag)       // \arg flag to be cleared
+{
+	pUDP->UDP_CSR[endpoint] |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpStatus
+//* \brief Return the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpStatus(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	return pUDP->UDP_CSR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_GetInterruptMaskStatus
+//* \brief Return UDP Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
+        AT91PS_UDP pUdp) // \arg  pointer to a UDP controller
+{
+        return pUdp->UDP_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_IsInterruptMasked
+//* \brief Test if UDP Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_UDP_IsInterruptMasked(
+        AT91PS_UDP pUdp,   // \arg  pointer to a UDP controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_InterruptEnable
+//* \brief Enable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptEnable(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  TC interrupt to be enabled
+{
+        pTc->TC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_InterruptDisable
+//* \brief Disable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptDisable(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  TC interrupt to be disabled
+{
+        pTc->TC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_GetInterruptMaskStatus
+//* \brief Return TC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
+        AT91PS_TC pTc) // \arg  pointer to a TC controller
+{
+        return pTc->TC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_IsInterruptMasked
+//* \brief Test if TC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline int AT91F_TC_IsInterruptMasked(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR CAN
+   ***************************************************************************** */
+#define	STANDARD_FORMAT 0
+#define	EXTENDED_FORMAT 1
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_InitMailboxRegisters()
+//* \brief Configure the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB	CAN_Mailbox,
+								int  			mode_reg,
+								int 			acceptance_mask_reg,
+								int  			id_reg,
+								int  			data_low_reg,
+								int  			data_high_reg,
+								int  			control_reg)
+{
+	CAN_Mailbox->CAN_MB_MCR 	= 0x0;
+	CAN_Mailbox->CAN_MB_MMR 	= mode_reg;
+	CAN_Mailbox->CAN_MB_MAM 	= acceptance_mask_reg;
+	CAN_Mailbox->CAN_MB_MID 	= id_reg;
+	CAN_Mailbox->CAN_MB_MDL 	= data_low_reg; 		
+	CAN_Mailbox->CAN_MB_MDH 	= data_high_reg;
+	CAN_Mailbox->CAN_MB_MCR 	= control_reg;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EnableCAN()
+//* \brief 
+//*----------------------------------------------------------------------------
+__inline void AT91F_EnableCAN(
+	AT91PS_CAN pCAN)     // pointer to a CAN controller
+{
+	pCAN->CAN_MR |= AT91C_CAN_CANEN;
+
+	// Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver
+	while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DisableCAN()
+//* \brief 
+//*----------------------------------------------------------------------------
+__inline void AT91F_DisableCAN(
+	AT91PS_CAN pCAN)     // pointer to a CAN controller
+{
+	pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_EnableIt
+//* \brief Enable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_EnableIt (
+	AT91PS_CAN pCAN,     // pointer to a CAN controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pCAN->CAN_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_DisableIt
+//* \brief Disable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_DisableIt (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pCAN->CAN_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetStatus
+//* \brief Return CAN Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status
+	AT91PS_CAN pCAN) // pointer to a CAN controller
+{
+	return pCAN->CAN_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetInterruptMaskStatus
+//* \brief Return CAN Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status
+	AT91PS_CAN pCAN) // pointer to a CAN controller
+{
+	return pCAN->CAN_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_IsInterruptMasked
+//* \brief Test if CAN Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsInterruptMasked(
+        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_IsStatusSet
+//* \brief Test if CAN Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsStatusSet(
+        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_CAN_GetStatus(pCAN) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgModeReg
+//* \brief Configure the Mode Register of the CAN controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgModeReg (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pCAN->CAN_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetModeReg
+//* \brief Return the Mode Register of the CAN controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetModeReg (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgBaudrateReg
+//* \brief Configure the Baudrate of the CAN controller for the network
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgBaudrateReg (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int baudrate_cfg)
+{
+	//* Write to the BR register
+	pCAN->CAN_BR = baudrate_cfg;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetBaudrate
+//* \brief Return the Baudrate of the CAN controller for the network value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetBaudrate (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_BR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetInternalCounter
+//* \brief Return CAN Timer Regsiter Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInternalCounter (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_TIM;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetTimestamp
+//* \brief Return CAN Timestamp Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetTimestamp (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_TIMESTP;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetErrorCounter
+//* \brief Return CAN Error Counter Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetErrorCounter (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_ECR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_InitTransferRequest
+//* \brief Request for a transfer on the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitTransferRequest (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+    unsigned int transfer_cmd)
+{
+	pCAN->CAN_TCR = transfer_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_InitAbortRequest
+//* \brief Abort the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitAbortRequest (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+    unsigned int abort_cmd)
+{
+	pCAN->CAN_ACR = abort_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageModeReg
+//* \brief Program the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageModeReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int mode)
+{
+	CAN_Mailbox->CAN_MB_MMR = mode;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageModeReg
+//* \brief Return the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageModeReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MMR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageIDReg
+//* \brief Program the Message ID Register
+//* \brief Version == 0 for Standard messsage, Version == 1 for Extended  
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageIDReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int id,
+    unsigned char version)
+{
+	if(version==0)	// IDvA Standard Format
+		CAN_Mailbox->CAN_MB_MID = id<<18;
+	else	// IDvB Extended Format
+		CAN_Mailbox->CAN_MB_MID = id | (1<<29);	// set MIDE bit
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageIDReg
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageIDReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MID;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageAcceptanceMaskReg
+//* \brief Program the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int mask)
+{
+	CAN_Mailbox->CAN_MB_MAM = mask;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageAcceptanceMaskReg
+//* \brief Return the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MAM;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetFamilyID
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetFamilyID (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MFID;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageCtrl
+//* \brief Request and config for a transfer on the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageCtrlReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int message_ctrl_cmd)
+{
+	CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageStatus
+//* \brief Return CAN Mailbox Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageStatus (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MSR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageDataLow
+//* \brief Program data low value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataLow (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int data)
+{
+	CAN_Mailbox->CAN_MB_MDL = data;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageDataLow
+//* \brief Return data low value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataLow (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MDL;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageDataHigh
+//* \brief Program data high value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataHigh (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int data)
+{
+	CAN_Mailbox->CAN_MB_MDH = data;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageDataHigh
+//* \brief Return data high value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataHigh (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MDH;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_Open
+//* \brief Open a CAN Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_Open (
+        const unsigned int null)  // \arg
+{
+        /* NOT DEFINED AT THIS MOMENT */
+        return ( 0 );
+}
+/* *****************************************************************************
+                SOFTWARE API FOR ADC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_EnableIt
+//* \brief Enable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableIt (
+	AT91PS_ADC pADC,     // pointer to a ADC controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pADC->ADC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_DisableIt
+//* \brief Disable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableIt (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pADC->ADC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetStatus
+//* \brief Return ADC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
+	AT91PS_ADC pADC) // pointer to a ADC controller
+{
+	return pADC->ADC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetInterruptMaskStatus
+//* \brief Return ADC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
+	AT91PS_ADC pADC) // pointer to a ADC controller
+{
+	return pADC->ADC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_IsInterruptMasked
+//* \brief Test if ADC Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsInterruptMasked(
+        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_IsStatusSet
+//* \brief Test if ADC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsStatusSet(
+        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_ADC_GetStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgModeReg
+//* \brief Configure the Mode Register of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgModeReg (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pADC->ADC_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetModeReg
+//* \brief Return the Mode Register of the ADC controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetModeReg (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgTimings
+//* \brief Configure the different necessary timings of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgTimings (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int mck_clock, // in MHz 
+	unsigned int adc_clock, // in MHz 
+	unsigned int startup_time, // in us 
+	unsigned int sample_and_hold_time)	// in ns  
+{
+	unsigned int prescal,startup,shtim;
+	
+	prescal = mck_clock/(2*adc_clock) - 1;
+	startup = adc_clock*startup_time/8 - 1;
+	shtim = adc_clock*sample_and_hold_time/1000 - 1;
+	
+	//* Write to the MR register
+	pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_EnableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableChannel (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int channel)        // mode register 
+{
+	//* Write to the CHER register
+	pADC->ADC_CHER = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_DisableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableChannel (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int channel)        // mode register 
+{
+	//* Write to the CHDR register
+	pADC->ADC_CHDR = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetChannelStatus
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetChannelStatus (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CHSR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_StartConversion
+//* \brief Software request for a analog to digital conversion 
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_StartConversion (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	pADC->ADC_CR = AT91C_ADC_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_SoftReset
+//* \brief Software reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_SoftReset (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	pADC->ADC_CR = AT91C_ADC_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetLastConvertedData
+//* \brief Return the Last Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetLastConvertedData (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_LCDR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH0
+//* \brief Return the Channel 0 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR0;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH1
+//* \brief Return the Channel 1 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR1;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH2
+//* \brief Return the Channel 2 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR2;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH3
+//* \brief Return the Channel 3 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR3;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH4
+//* \brief Return the Channel 4 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR4;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH5
+//* \brief Return the Channel 5 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR5;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH6
+//* \brief Return the Channel 6 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR6;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH7
+//* \brief Return the Channel 7 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR7;	
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR AES
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_EnableIt
+//* \brief Enable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_EnableIt (
+	AT91PS_AES pAES,     // pointer to a AES controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pAES->AES_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_DisableIt
+//* \brief Disable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_DisableIt (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pAES->AES_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetStatus
+//* \brief Return AES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status
+	AT91PS_AES pAES) // pointer to a AES controller
+{
+	return pAES->AES_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetInterruptMaskStatus
+//* \brief Return AES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status
+	AT91PS_AES pAES) // pointer to a AES controller
+{
+	return pAES->AES_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_IsInterruptMasked
+//* \brief Test if AES Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsInterruptMasked(
+        AT91PS_AES pAES,   // \arg  pointer to a AES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_IsStatusSet
+//* \brief Test if AES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsStatusSet(
+        AT91PS_AES pAES,   // \arg  pointer to a AES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_AES_GetStatus(pAES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_CfgModeReg
+//* \brief Configure the Mode Register of the AES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgModeReg (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pAES->AES_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetModeReg
+//* \brief Return the Mode Register of the AES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetModeReg (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	return pAES->AES_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_StartProcessing (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SoftReset
+//* \brief Reset AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SoftReset (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_LoadNewSeed
+//* \brief Load New Seed in the random number generator
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_LoadNewSeed (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_LOADSEED;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SetCryptoKey
+//* \brief Set Cryptographic Key x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetCryptoKey (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pAES->AES_KEYWxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_InputData (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int indata
+	)
+{
+	pAES->AES_IDATAxR[index] = indata;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetOutputData (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index
+	)
+{
+	return pAES->AES_ODATAxR[index];	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SetInitializationVector
+//* \brief Set Initialization Vector (or Counter) x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetInitializationVector (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int initvector
+	)
+{
+	pAES->AES_IVxR[index] = initvector;	
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TDES
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_EnableIt
+//* \brief Enable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_EnableIt (
+	AT91PS_TDES pTDES,     // pointer to a TDES controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pTDES->TDES_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_DisableIt
+//* \brief Disable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_DisableIt (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pTDES->TDES_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetStatus
+//* \brief Return TDES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status
+	AT91PS_TDES pTDES) // pointer to a TDES controller
+{
+	return pTDES->TDES_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetInterruptMaskStatus
+//* \brief Return TDES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status
+	AT91PS_TDES pTDES) // pointer to a TDES controller
+{
+	return pTDES->TDES_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_IsInterruptMasked
+//* \brief Test if TDES Interrupt is Masked 
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsInterruptMasked(
+        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_IsStatusSet
+//* \brief Test if TDES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsStatusSet(
+        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_TDES_GetStatus(pTDES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_CfgModeReg
+//* \brief Configure the Mode Register of the TDES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgModeReg (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned int mode)        // mode register 
+{
+	//* Write to the MR register
+	pTDES->TDES_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetModeReg
+//* \brief Return the Mode Register of the TDES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetModeReg (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	return pTDES->TDES_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_StartProcessing (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	pTDES->TDES_CR = AT91C_TDES_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SoftReset
+//* \brief Reset TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SoftReset (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	pTDES->TDES_CR = AT91C_TDES_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey1
+//* \brief Set Cryptographic Key 1 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey1 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY1WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey2
+//* \brief Set Cryptographic Key 2 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey2 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY2WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey3
+//* \brief Set Cryptographic Key 3 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey3 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY3WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_InputData (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int indata
+	)
+{
+	pTDES->TDES_IDATAxR[index] = indata;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetOutputData (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index
+	)
+{
+	return pTDES->TDES_ODATAxR[index];	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetInitializationVector
+//* \brief Set Initialization Vector x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetInitializationVector (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int initvector
+	)
+{
+	pTDES->TDES_IVxR[index] = initvector;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  DBGU
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_CfgPIO
+//* \brief Configure PIO controllers to drive DBGU signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA27_DRXD    ) |
+		((unsigned int) AT91C_PA28_DTXD    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgPIO
+//* \brief Configure PIO controllers to drive PMC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB30_PCK2    ) |
+		((unsigned int) AT91C_PB29_PCK1    ), // Peripheral A
+		((unsigned int) AT91C_PB20_PCK0    ) |
+		((unsigned int) AT91C_PB0_PCK0    ) |
+		((unsigned int) AT91C_PB22_PCK2    ) |
+		((unsigned int) AT91C_PB21_PCK1    )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA30_PCK2    ) |
+		((unsigned int) AT91C_PA13_PCK1    ) |
+		((unsigned int) AT91C_PA27_PCK3    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  VREG
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  RSTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SSC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_CfgPIO
+//* \brief Configure PIO controllers to drive SSC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA25_RK      ) |
+		((unsigned int) AT91C_PA22_TK      ) |
+		((unsigned int) AT91C_PA21_TF      ) |
+		((unsigned int) AT91C_PA24_RD      ) |
+		((unsigned int) AT91C_PA26_RF      ) |
+		((unsigned int) AT91C_PA23_TD      ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  WDTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  US1
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_US1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US1_CfgPIO
+//* \brief Configure PIO controllers to drive US1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB26_RI1     ) |
+		((unsigned int) AT91C_PB24_DSR1    ) |
+		((unsigned int) AT91C_PB23_DCD1    ) |
+		((unsigned int) AT91C_PB25_DTR1    )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA7_SCK1    ) |
+		((unsigned int) AT91C_PA8_RTS1    ) |
+		((unsigned int) AT91C_PA6_TXD1    ) |
+		((unsigned int) AT91C_PA5_RXD1    ) |
+		((unsigned int) AT91C_PA9_CTS1    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  US0
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_US0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US0_CfgPIO
+//* \brief Configure PIO controllers to drive US0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA0_RXD0    ) |
+		((unsigned int) AT91C_PA4_CTS0    ) |
+		((unsigned int) AT91C_PA3_RTS0    ) |
+		((unsigned int) AT91C_PA2_SCK0    ) |
+		((unsigned int) AT91C_PA1_TXD0    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SPI1
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SPI1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI1_CfgPIO
+//* \brief Configure PIO controllers to drive SPI1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB16_NPCS13  ) |
+		((unsigned int) AT91C_PB10_NPCS11  ) |
+		((unsigned int) AT91C_PB11_NPCS12  )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA4_NPCS13  ) |
+		((unsigned int) AT91C_PA29_NPCS13  ) |
+		((unsigned int) AT91C_PA21_NPCS10  ) |
+		((unsigned int) AT91C_PA22_SPCK1   ) |
+		((unsigned int) AT91C_PA25_NPCS11  ) |
+		((unsigned int) AT91C_PA2_NPCS11  ) |
+		((unsigned int) AT91C_PA24_MISO1   ) |
+		((unsigned int) AT91C_PA3_NPCS12  ) |
+		((unsigned int) AT91C_PA26_NPCS12  ) |
+		((unsigned int) AT91C_PA23_MOSI1   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SPI0
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SPI0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI0_CfgPIO
+//* \brief Configure PIO controllers to drive SPI0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB13_NPCS01  ) |
+		((unsigned int) AT91C_PB17_NPCS03  ) |
+		((unsigned int) AT91C_PB14_NPCS02  )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA16_MISO0   ) |
+		((unsigned int) AT91C_PA13_NPCS01  ) |
+		((unsigned int) AT91C_PA15_NPCS03  ) |
+		((unsigned int) AT91C_PA17_MOSI0   ) |
+		((unsigned int) AT91C_PA18_SPCK0   ) |
+		((unsigned int) AT91C_PA14_NPCS02  ) |
+		((unsigned int) AT91C_PA12_NPCS00  ), // Peripheral A
+		((unsigned int) AT91C_PA7_NPCS01  ) |
+		((unsigned int) AT91C_PA9_NPCS03  ) |
+		((unsigned int) AT91C_PA8_NPCS02  )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PITC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  AIC
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_FIQ) |
+		((unsigned int) 1 << AT91C_ID_IRQ0) |
+		((unsigned int) 1 << AT91C_ID_IRQ1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_CfgPIO
+//* \brief Configure PIO controllers to drive AIC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA30_IRQ0    ) |
+		((unsigned int) AT91C_PA29_FIQ     ), // Peripheral A
+		((unsigned int) AT91C_PA14_IRQ1    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_AES));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TWI
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TWI));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_CfgPIO
+//* \brief Configure PIO controllers to drive TWI signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA11_TWCK    ) |
+		((unsigned int) AT91C_PA10_TWD     ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  ADC
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_ADC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgPIO
+//* \brief Configure PIO controllers to drive ADC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB18_ADTRG   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH3_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH3 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH3_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB22_PWM3    ), // Peripheral A
+		((unsigned int) AT91C_PB30_PWM3    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH2_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH2_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB21_PWM2    ), // Peripheral A
+		((unsigned int) AT91C_PB29_PWM2    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH1_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB20_PWM1    ), // Peripheral A
+		((unsigned int) AT91C_PB28_PWM1    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH0_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB19_PWM0    ), // Peripheral A
+		((unsigned int) AT91C_PB27_PWM0    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RTTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  RTTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RTTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  UDP
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_UDP));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TDES));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EMAC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  EMAC
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_EMAC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EMAC_CfgPIO
+//* \brief Configure PIO controllers to drive EMAC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB2_ETX0    ) |
+		((unsigned int) AT91C_PB12_ETXER   ) |
+		((unsigned int) AT91C_PB16_ECOL    ) |
+		((unsigned int) AT91C_PB11_ETX3    ) |
+		((unsigned int) AT91C_PB6_ERX1    ) |
+		((unsigned int) AT91C_PB15_ERXDV   ) |
+		((unsigned int) AT91C_PB13_ERX2    ) |
+		((unsigned int) AT91C_PB3_ETX1    ) |
+		((unsigned int) AT91C_PB8_EMDC    ) |
+		((unsigned int) AT91C_PB5_ERX0    ) |
+		//((unsigned int) AT91C_PB18_EF100   ) |
+		((unsigned int) AT91C_PB14_ERX3    ) |
+		((unsigned int) AT91C_PB4_ECRS_ECRSDV) |
+		((unsigned int) AT91C_PB1_ETXEN   ) |
+		((unsigned int) AT91C_PB10_ETX2    ) |
+		((unsigned int) AT91C_PB0_ETXCK_EREFCK) |
+		((unsigned int) AT91C_PB9_EMDIO   ) |
+		((unsigned int) AT91C_PB7_ERXER   ) |
+		((unsigned int) AT91C_PB17_ERXCK   ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC0
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC0_CfgPIO
+//* \brief Configure PIO controllers to drive TC0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB23_TIOA0   ) |
+		((unsigned int) AT91C_PB24_TIOB0   ), // Peripheral A
+		((unsigned int) AT91C_PB12_TCLK0   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC1
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC1_CfgPIO
+//* \brief Configure PIO controllers to drive TC1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB25_TIOA1   ) |
+		((unsigned int) AT91C_PB26_TIOB1   ), // Peripheral A
+		((unsigned int) AT91C_PB19_TCLK1   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC2_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC2
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC2));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC2_CfgPIO
+//* \brief Configure PIO controllers to drive TC2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB28_TIOB2   ) |
+		((unsigned int) AT91C_PB27_TIOA2   ), // Peripheral A
+		0); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA15_TCLK2   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  MC
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIOA_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PIOA
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOA_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PIOA));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIOB_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PIOB
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOB_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PIOB));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  CAN
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_CAN));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgPIO
+//* \brief Configure PIO controllers to drive CAN signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA20_CANTX   ) |
+		((unsigned int) AT91C_PA19_CANRX   ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PWMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PWMC));
+}
+
+#endif // lib_AT91SAM7X128_H
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h
new file mode 100644
index 0000000..02ee900
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h
@@ -0,0 +1,4558 @@
+//* ----------------------------------------------------------------------------
+//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
+//* ----------------------------------------------------------------------------
+//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
+//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
+//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
+//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
+//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
+//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//* ----------------------------------------------------------------------------
+//* File Name           : lib_AT91SAM7X256.h
+//* Object              : AT91SAM7X256 inlined functions
+//* Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
+//*
+//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
+//* CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005//
+//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
+//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
+//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
+//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
+//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
+//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
+//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
+//* CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
+//* CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
+//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
+//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
+//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
+//* CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
+//* CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
+//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
+//* CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
+//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
+//* CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
+//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
+//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
+//* ----------------------------------------------------------------------------
+
+#ifndef lib_AT91SAM7X256_H
+#define lib_AT91SAM7X256_H
+
+/* *****************************************************************************
+                SOFTWARE API FOR AIC
+   ***************************************************************************** */
+#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ConfigureIt
+//* \brief Interrupt Handler Initialization
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AIC_ConfigureIt (
+	AT91PS_AIC pAic,  // \arg pointer to the AIC registers
+	unsigned int irq_id,     // \arg interrupt number to initialize
+	unsigned int priority,   // \arg priority to give to the interrupt
+	unsigned int src_type,   // \arg activation and sense of activation
+	void (*newHandler) (void) ) // \arg address of the interrupt handler
+{
+	unsigned int oldHandler;
+    unsigned int mask ;
+
+    oldHandler = pAic->AIC_SVR[irq_id];
+
+    mask = 0x1 << irq_id ;
+    //* Disable the interrupt on the interrupt controller
+    pAic->AIC_IDCR = mask ;
+    //* Save the interrupt handler routine pointer and the interrupt priority
+    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
+    //* Store the Source Mode Register
+    pAic->AIC_SMR[irq_id] = src_type | priority  ;
+    //* Clear the interrupt on the interrupt controller
+    pAic->AIC_ICCR = mask ;
+
+	return oldHandler;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_EnableIt
+//* \brief Enable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_EnableIt (
+	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
+	unsigned int irq_id ) // \arg interrupt number to initialize
+{
+    //* Enable the interrupt on the interrupt controller
+    pAic->AIC_IECR = 0x1 << irq_id ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_DisableIt
+//* \brief Disable corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_DisableIt (
+	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
+	unsigned int irq_id ) // \arg interrupt number to initialize
+{
+    unsigned int mask = 0x1 << irq_id;
+    //* Disable the interrupt on the interrupt controller
+    pAic->AIC_IDCR = mask ;
+    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+    pAic->AIC_ICCR = mask ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_ClearIt
+//* \brief Clear corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_ClearIt (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg interrupt number to initialize
+{
+    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
+    pAic->AIC_ICCR = (0x1 << irq_id);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_AcknowledgeIt
+//* \brief Acknowledge corresponding IT number
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_AcknowledgeIt (
+	AT91PS_AIC pAic)     // \arg pointer to the AIC registers
+{
+    pAic->AIC_EOICR = pAic->AIC_EOICR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_SetExceptionVector
+//* \brief Configure vector handler
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_SetExceptionVector (
+	unsigned int *pVector, // \arg pointer to the AIC registers
+	void (*Handler) () )   // \arg Interrupt Handler
+{
+	unsigned int oldVector = *pVector;
+
+	if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
+		*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
+	else
+		*pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
+
+	return oldVector;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_Trig
+//* \brief Trig an IT
+//*----------------------------------------------------------------------------
+__inline void  AT91F_AIC_Trig (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg interrupt number
+{
+	pAic->AIC_ISCR = (0x1 << irq_id) ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_IsActive
+//* \brief Test if an IT is active
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_IsActive (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg Interrupt Number
+{
+	return (pAic->AIC_ISR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_IsPending
+//* \brief Test if an IT is pending
+//*----------------------------------------------------------------------------
+__inline unsigned int  AT91F_AIC_IsPending (
+	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
+	unsigned int irq_id) // \arg Interrupt Number
+{
+	return (pAic->AIC_IPR & (0x1 << irq_id));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_Open
+//* \brief Set exception vectors and AIC registers to default values
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_Open(
+	AT91PS_AIC pAic,        // \arg pointer to the AIC registers
+	void (*IrqHandler) (),  // \arg Default IRQ vector exception
+	void (*FiqHandler) (),  // \arg Default FIQ vector exception
+	void (*DefaultHandler)  (), // \arg Default Handler set in ISR
+	void (*SpuriousHandler) (), // \arg Default Spurious Handler
+	unsigned int protectMode)   // \arg Debug Control Register
+{
+	int i;
+
+	// Disable all interrupts and set IVR to the default handler
+	for (i = 0; i < 32; ++i) {
+		AT91F_AIC_DisableIt(pAic, i);
+		AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
+	}
+
+	// Set the IRQ exception vector
+	AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
+	// Set the Fast Interrupt exception vector
+	AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
+
+	pAic->AIC_SPU = (unsigned int) SpuriousHandler;
+	pAic->AIC_DCR = protectMode;
+}
+/* *****************************************************************************
+                SOFTWARE API FOR PDC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetNextRx
+//* \brief Set the next receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextRx (
+	AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
+	char *address,       // \arg address to the next bloc to be received
+	unsigned int bytes)  // \arg number of bytes to be received
+{
+	pPDC->PDC_RNPR = (unsigned int) address;
+	pPDC->PDC_RNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetNextTx
+//* \brief Set the next transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetNextTx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be transmitted
+	unsigned int bytes)    // \arg number of bytes to be transmitted
+{
+	pPDC->PDC_TNPR = (unsigned int) address;
+	pPDC->PDC_TNCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetRx
+//* \brief Set the receive transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetRx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be received
+	unsigned int bytes)    // \arg number of bytes to be received
+{
+	pPDC->PDC_RPR = (unsigned int) address;
+	pPDC->PDC_RCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SetTx
+//* \brief Set the transmit transfer descriptor
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_SetTx (
+	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
+	char *address,         // \arg address to the next bloc to be transmitted
+	unsigned int bytes)    // \arg number of bytes to be transmitted
+{
+	pPDC->PDC_TPR = (unsigned int) address;
+	pPDC->PDC_TCR = bytes;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_EnableTx
+//* \brief Enable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableTx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_EnableRx
+//* \brief Enable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_EnableRx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_DisableTx
+//* \brief Disable transmit
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableTx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_DisableRx
+//* \brief Disable receive
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_DisableRx (
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsTxEmpty
+//* \brief Test if the current transfer descriptor has been sent
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_TCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsNextTxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_TNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsRxEmpty
+//* \brief Test if the current transfer descriptor has been filled
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_RCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_IsNextRxEmpty
+//* \brief Test if the next transfer descriptor has been moved to the current td
+//*----------------------------------------------------------------------------
+__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
+	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
+{
+	return !(pPDC->PDC_RNCR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_Open
+//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Open (
+	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+{
+    //* Disable the RX and TX PDC transfer requests
+	AT91F_PDC_DisableRx(pPDC);
+	AT91F_PDC_DisableTx(pPDC);
+
+	//* Reset all Counter register Next buffer first
+	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+    //* Enable the RX and TX PDC transfer requests
+	AT91F_PDC_EnableRx(pPDC);
+	AT91F_PDC_EnableTx(pPDC);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_Close
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline void AT91F_PDC_Close (
+	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
+{
+    //* Disable the RX and TX PDC transfer requests
+	AT91F_PDC_DisableRx(pPDC);
+	AT91F_PDC_DisableTx(pPDC);
+
+	//* Reset all Counter register Next buffer first
+	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
+	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_SendFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_SendFrame(
+	AT91PS_PDC pPDC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	if (AT91F_PDC_IsTxEmpty(pPDC)) {
+		//* Buffer and next buffer can be initialized
+		AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
+		AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
+		return 2;
+	}
+	else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
+		//* Only one buffer can be initialized
+		AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
+		return 1;
+	}
+	else {
+		//* All buffer are in use...
+		return 0;
+	}
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PDC_ReceiveFrame
+//* \brief Close PDC: disable TX and RX reset transfer descriptors
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PDC_ReceiveFrame (
+	AT91PS_PDC pPDC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	if (AT91F_PDC_IsRxEmpty(pPDC)) {
+		//* Buffer and next buffer can be initialized
+		AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
+		AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
+		return 2;
+	}
+	else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
+		//* Only one buffer can be initialized
+		AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
+		return 1;
+	}
+	else {
+		//* All buffer are in use...
+		return 0;
+	}
+}
+/* *****************************************************************************
+                SOFTWARE API FOR DBGU
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_InterruptEnable
+//* \brief Enable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptEnable(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  dbgu interrupt to be enabled
+{
+        pDbgu->DBGU_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_InterruptDisable
+//* \brief Disable DBGU Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_InterruptDisable(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  dbgu interrupt to be disabled
+{
+        pDbgu->DBGU_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_GetInterruptMaskStatus
+//* \brief Return DBGU Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
+        AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
+{
+        return pDbgu->DBGU_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_IsInterruptMasked
+//* \brief Test if DBGU Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_DBGU_IsInterruptMasked(
+        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PIO
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgPeriph
+//* \brief Enable pins to be drived by peripheral
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPeriph(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int periphAEnable,  // \arg PERIPH A to enable
+	unsigned int periphBEnable)  // \arg PERIPH B to enable
+
+{
+	pPio->PIO_ASR = periphAEnable;
+	pPio->PIO_BSR = periphBEnable;
+	pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgOutput
+//* \brief Enable PIO in output mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOutput(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int pioEnable)      // \arg PIO to be enabled
+{
+	pPio->PIO_PER = pioEnable; // Set in PIO mode
+	pPio->PIO_OER = pioEnable; // Configure in Output
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgInput
+//* \brief Enable PIO in input mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInput(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int inputEnable)      // \arg PIO to be enabled
+{
+	// Disable output
+	pPio->PIO_ODR  = inputEnable;
+	pPio->PIO_PER  = inputEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgOpendrain
+//* \brief Configure PIO in open drain
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgOpendrain(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int multiDrvEnable) // \arg pio to be configured in open drain
+{
+	// Configure the multi-drive option
+	pPio->PIO_MDDR = ~multiDrvEnable;
+	pPio->PIO_MDER = multiDrvEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgPullup
+//* \brief Enable pullup on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgPullup(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int pullupEnable)   // \arg enable pullup on PIO
+{
+		// Connect or not Pullup
+	pPio->PIO_PPUDR = ~pullupEnable;
+	pPio->PIO_PPUER = pullupEnable;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgDirectDrive
+//* \brief Enable direct drive on PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgDirectDrive(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int directDrive)    // \arg PIO to be configured with direct drive
+
+{
+	// Configure the Direct Drive
+	pPio->PIO_OWDR  = ~directDrive;
+	pPio->PIO_OWER  = directDrive;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_CfgInputFilter
+//* \brief Enable input filter on input PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_CfgInputFilter(
+	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
+	unsigned int inputFilter)    // \arg PIO to be configured with input filter
+
+{
+	// Configure the Direct Drive
+	pPio->PIO_IFDR  = ~inputFilter;
+	pPio->PIO_IFER  = inputFilter;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInput
+//* \brief Return PIO input value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
+	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+	return pPio->PIO_PDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInputSet
+//* \brief Test if PIO is input flag is active
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputSet(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PIO_GetInput(pPio) & flag);
+}
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_SetOutput
+//* \brief Set to 1 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_SetOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be set
+{
+	pPio->PIO_SODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_ClearOutput
+//* \brief Set to 0 output PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ClearOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be cleared
+{
+	pPio->PIO_CODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_ForceOutput
+//* \brief Force output when Direct drive option is enabled
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_ForceOutput(
+	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+	unsigned int flag) // \arg  output to be forced
+{
+	pPio->PIO_ODSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Enable
+//* \brief Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Enable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be enabled
+{
+        pPio->PIO_PER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Disable
+//* \brief Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_Disable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be disabled
+{
+        pPio->PIO_PDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetStatus
+//* \brief Return PIO Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_PSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsSet
+//* \brief Test if PIO is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputEnable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output to be enabled
+{
+        pPio->PIO_OER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputDisable
+//* \brief Output Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output to be disabled
+{
+        pPio->PIO_ODR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputStatus
+//* \brief Return PIO Output Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_OSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOuputSet
+//* \brief Test if PIO Output is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InputFilterEnable
+//* \brief Input Filter Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio input filter to be enabled
+{
+        pPio->PIO_IFER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InputFilterDisable
+//* \brief Input Filter Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InputFilterDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio input filter to be disabled
+{
+        pPio->PIO_IFDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInputFilterStatus
+//* \brief Return PIO Input Filter Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_IFSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInputFilterSet
+//* \brief Test if PIO Input filter is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInputFilterSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputDataStatus
+//* \brief Return PIO Output Data Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
+	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ODSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InterruptEnable
+//* \brief Enable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio interrupt to be enabled
+{
+        pPio->PIO_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_InterruptDisable
+//* \brief Disable PIO Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_InterruptDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio interrupt to be disabled
+{
+        pPio->PIO_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInterruptMaskStatus
+//* \brief Return PIO Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetInterruptStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInterruptMasked
+//* \brief Test if PIO Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptMasked(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsInterruptSet
+//* \brief Test if PIO Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsInterruptSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_MultiDriverEnable
+//* \brief Multi Driver Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be enabled
+{
+        pPio->PIO_MDER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_MultiDriverDisable
+//* \brief Multi Driver Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_MultiDriverDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio to be disabled
+{
+        pPio->PIO_MDDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetMultiDriverStatus
+//* \brief Return PIO Multi Driver Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_MDSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsMultiDriverSet
+//* \brief Test if PIO MultiDriver is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsMultiDriverSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_A_RegisterSelection
+//* \brief PIO A Register Selection
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_A_RegisterSelection(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio A register selection
+{
+        pPio->PIO_ASR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_B_RegisterSelection
+//* \brief PIO B Register Selection
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_B_RegisterSelection(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio B register selection
+{
+        pPio->PIO_BSR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_Get_AB_RegisterStatus
+//* \brief Return PIO Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_ABSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsAB_RegisterSet
+//* \brief Test if PIO AB Register is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsAB_RegisterSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputWriteEnable
+//* \brief Output Write Enable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteEnable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output write to be enabled
+{
+        pPio->PIO_OWER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_OutputWriteDisable
+//* \brief Output Write Disable PIO
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIO_OutputWriteDisable(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  pio output write to be disabled
+{
+        pPio->PIO_OWDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetOutputWriteStatus
+//* \brief Return PIO Output Write Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_OWSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOutputWriteSet
+//* \brief Test if PIO OutputWrite is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputWriteSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_GetCfgPullup
+//* \brief Return PIO Configuration Pullup
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
+        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
+{
+        return pPio->PIO_PPUSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsOutputDataStatusSet
+//* \brief Test if PIO Output Data Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsOutputDataStatusSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIO_IsCfgPullupStatusSet
+//* \brief Test if PIO Configuration Pullup Status is Set
+//*----------------------------------------------------------------------------
+__inline int AT91F_PIO_IsCfgPullupStatusSet(
+        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PMC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgSysClkEnableReg
+//* \brief Configure the System Clock Enable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkEnableReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	//* Write to the SCER register
+	pPMC->PMC_SCER = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgSysClkDisableReg
+//* \brief Configure the System Clock Disable Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgSysClkDisableReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	//* Write to the SCDR register
+	pPMC->PMC_SCDR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetSysClkStatusReg
+//* \brief Return the System Clock Status Register of the PMC controller
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
+	AT91PS_PMC pPMC // pointer to a CAN controller
+	)
+{
+	return pPMC->PMC_SCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnablePeriphClock
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePeriphClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int periphIds)  // \arg IDs of peripherals to enable
+{
+	pPMC->PMC_PCER = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisablePeriphClock
+//* \brief Disable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePeriphClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int periphIds)  // \arg IDs of peripherals to enable
+{
+	pPMC->PMC_PCDR = periphIds;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetPeriphClock
+//* \brief Get peripheral clock status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetPeriphClock (
+	AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+	return pPMC->PMC_PCSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_CfgMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscillatorReg (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int mode)
+{
+	pCKGR->CKGR_MOR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainOscillatorReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	return pCKGR->CKGR_MOR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_EnableMainOscillator
+//* \brief Enable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_EnableMainOscillator(
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_DisableMainOscillator
+//* \brief Disable the main oscillator
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_DisableMainOscillator (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
+//* \brief Cfg MOR Register according to the main osc startup time
+//*----------------------------------------------------------------------------
+__inline void AT91F_CKGR_CfgMainOscStartUpTime (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
+	pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainClockFreqReg
+//* \brief Cfg the main oscillator
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
+	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
+{
+	return pCKGR->CKGR_MCFR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CKGR_GetMainClock
+//* \brief Return Main clock in Hz
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CKGR_GetMainClock (
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgMCKReg
+//* \brief Cfg Master Clock Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgMCKReg (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int mode)
+{
+	pPMC->PMC_MCKR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetMCKReg
+//* \brief Return Master Clock Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMCKReg(
+	AT91PS_PMC pPMC) // \arg pointer to PMC controller
+{
+	return pPMC->PMC_MCKR;
+}
+
+//*------------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetMasterClock
+//* \brief Return master clock in Hz which correponds to processor clock for ARM7
+//*------------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetMasterClock (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
+	unsigned int slowClock)  // \arg slowClock in Hz
+{
+	unsigned int reg = pPMC->PMC_MCKR;
+	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
+	unsigned int pllDivider, pllMultiplier;
+
+	switch (reg & AT91C_PMC_CSS) {
+		case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
+			return slowClock / prescaler;
+		case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
+			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
+		case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
+			reg = pCKGR->CKGR_PLLR;
+			pllDivider    = (reg  & AT91C_CKGR_DIV);
+			pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
+			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
+	}
+	return 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnablePCK (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
+	unsigned int mode)
+{
+	pPMC->PMC_PCKR[pck] = mode;
+	pPMC->PMC_SCER = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisablePCK
+//* \brief Enable peripheral clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisablePCK (
+	AT91PS_PMC pPMC, // \arg pointer to PMC controller
+	unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
+{
+	pPMC->PMC_SCDR = (1 << pck) << 8;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_EnableIt
+//* \brief Enable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_EnableIt (
+	AT91PS_PMC pPMC,     // pointer to a PMC controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pPMC->PMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_DisableIt
+//* \brief Disable PMC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_DisableIt (
+	AT91PS_PMC pPMC, // pointer to a PMC controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pPMC->PMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetStatus
+//* \brief Return PMC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
+	AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+	return pPMC->PMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_GetInterruptMaskStatus
+//* \brief Return PMC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
+	AT91PS_PMC pPMC) // pointer to a PMC controller
+{
+	return pPMC->PMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_IsInterruptMasked
+//* \brief Test if PMC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsInterruptMasked(
+        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_IsStatusSet
+//* \brief Test if PMC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PMC_IsStatusSet(
+        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PMC_GetStatus(pPMC) & flag);
+}/* *****************************************************************************
+                SOFTWARE API FOR RSTC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTSoftReset
+//* \brief Start Software Reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSoftReset(
+        AT91PS_RSTC pRSTC,
+        unsigned int reset)
+{
+	pRSTC->RSTC_RCR = (0xA5000000 | reset);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTSetMode
+//* \brief Set Reset Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTSetMode(
+        AT91PS_RSTC pRSTC,
+        unsigned int mode)
+{
+	pRSTC->RSTC_RMR = (0xA5000000 | mode);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTGetMode
+//* \brief Get Reset Mode
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetMode(
+        AT91PS_RSTC pRSTC)
+{
+	return (pRSTC->RSTC_RMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTGetStatus
+//* \brief Get Reset Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTGetStatus(
+        AT91PS_RSTC pRSTC)
+{
+	return (pRSTC->RSTC_RSR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTIsSoftRstActive
+//* \brief Return !=0 if software reset is still not completed
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_RSTIsSoftRstActive(
+        AT91PS_RSTC pRSTC)
+{
+	return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR RTTC
+   ***************************************************************************** */
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_SetRTT_TimeBase()
+//* \brief  Set the RTT prescaler according to the TimeBase in ms
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetTimeBase(
+        AT91PS_RTTC pRTTC,
+        unsigned int ms)
+{
+	if (ms > 2000)
+		return 1;   // AT91C_TIME_OUT_OF_RANGE
+	pRTTC->RTTC_RTMR &= ~0xFFFF;	
+	pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);	
+	return 0;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTSetPrescaler()
+//* \brief  Set the new prescaler value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTSetPrescaler(
+        AT91PS_RTTC pRTTC,
+        unsigned int rtpres)
+{
+	pRTTC->RTTC_RTMR &= ~0xFFFF;	
+	pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);	
+	return (pRTTC->RTTC_RTMR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTRestart()
+//* \brief  Restart the RTT prescaler
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTRestart(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;	
+}
+
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetAlarmINT()
+//* \brief  Enable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ClearAlarmINT()
+//* \brief  Disable RTT Alarm Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearAlarmINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetRttIncINT()
+//* \brief  Enable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetRttIncINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ClearRttIncINT()
+//* \brief  Disable RTT INC Interrupt
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTClearRttIncINT(
+        AT91PS_RTTC pRTTC)
+{
+	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_SetAlarmValue()
+//* \brief  Set RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline void AT91F_RTTSetAlarmValue(
+        AT91PS_RTTC pRTTC, unsigned int alarm)
+{
+	pRTTC->RTTC_RTAR = alarm;
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_GetAlarmValue()
+//* \brief  Get RTT Alarm Value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetAlarmValue(
+        AT91PS_RTTC pRTTC)
+{
+	return(pRTTC->RTTC_RTAR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTTGetStatus()
+//* \brief  Read the RTT status
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTGetStatus(
+        AT91PS_RTTC pRTTC)
+{
+	return(pRTTC->RTTC_RTSR);
+}
+
+//*--------------------------------------------------------------------------------------
+//* \fn     AT91F_RTT_ReadValue()
+//* \brief  Read the RTT value
+//*--------------------------------------------------------------------------------------
+__inline unsigned int AT91F_RTTReadValue(
+        AT91PS_RTTC pRTTC)
+{
+        register volatile unsigned int val1,val2;
+	do
+	{
+		val1 = pRTTC->RTTC_RTVR;
+		val2 = pRTTC->RTTC_RTVR;
+	}	
+	while(val1 != val2);
+	return(val1);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR PITC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITInit
+//* \brief System timer init : period in µsecond, system clock freq in MHz
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITInit(
+        AT91PS_PITC pPITC,
+        unsigned int period,
+        unsigned int pit_frequency)
+{
+	pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
+	pPITC->PITC_PIMR |= AT91C_PITC_PITEN;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITSetPIV
+//* \brief Set the PIT Periodic Interval Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITSetPIV(
+        AT91PS_PITC pPITC,
+        unsigned int piv)
+{
+	pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITEnableInt
+//* \brief Enable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITEnableInt(
+        AT91PS_PITC pPITC)
+{
+	pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITDisableInt
+//* \brief Disable PIT periodic interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITDisableInt(
+        AT91PS_PITC pPITC)
+{
+	pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetMode
+//* \brief Read PIT mode register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetMode(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIMR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetStatus
+//* \brief Read PIT status register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetStatus(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PISR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetPIIR
+//* \brief Read PIT CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIIR(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIIR);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITGetPIVR
+//* \brief Read System timer CPIV and PICNT without ressetting the counters
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PITGetPIVR(
+        AT91PS_PITC pPITC)
+{
+	return(pPITC->PITC_PIVR);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR WDTC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTSetMode
+//* \brief Set Watchdog Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTSetMode(
+        AT91PS_WDTC pWDTC,
+        unsigned int Mode)
+{
+	pWDTC->WDTC_WDMR = Mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTRestart
+//* \brief Restart Watchdog
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTRestart(
+        AT91PS_WDTC pWDTC)
+{
+	pWDTC->WDTC_WDCR = 0xA5000001;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTSGettatus
+//* \brief Get Watchdog Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTSGettatus(
+        AT91PS_WDTC pWDTC)
+{
+	return(pWDTC->WDTC_WDSR & 0x3);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTGetPeriod
+//* \brief Translate ms into Watchdog Compatible value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)
+{
+	if ((ms < 4) || (ms > 16000))
+		return 0;
+	return((ms << 8) / 1000);
+}
+/* *****************************************************************************
+                SOFTWARE API FOR VREG
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_Enable_LowPowerMode
+//* \brief Enable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Enable_LowPowerMode(
+        AT91PS_VREG pVREG)
+{
+	pVREG->VREG_MR |= AT91C_VREG_PSTDBY;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_Disable_LowPowerMode
+//* \brief Disable VREG Low Power Mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_Disable_LowPowerMode(
+        AT91PS_VREG pVREG)
+{
+	pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;	
+}/* *****************************************************************************
+                SOFTWARE API FOR MC
+   ***************************************************************************** */
+
+#define AT91C_MC_CORRECT_KEY  ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_Remap
+//* \brief Make Remap
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_Remap (void)     //
+{
+    AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
+
+    pMC->MC_RCR = AT91C_MC_RCB;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_CfgModeReg
+//* \brief Configure the EFC Mode Register of the MC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_CfgModeReg (
+	AT91PS_MC pMC, // pointer to a MC controller
+	unsigned int mode)        // mode register
+{
+	// Write to the FMR register
+	pMC->MC_FMR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_GetModeReg
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetModeReg(
+	AT91PS_MC pMC) // pointer to a MC controller
+{
+	return pMC->MC_FMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_ComputeFMCN
+//* \brief Return MC EFC Mode Regsiter
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
+	int master_clock) // master clock in Hz
+{
+	return (master_clock/1000000 +2);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_PerformCmd
+//* \brief Perform EFC Command
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_EFC_PerformCmd (
+	AT91PS_MC pMC, // pointer to a MC controller
+    unsigned int transfer_cmd)
+{
+	pMC->MC_FCR = transfer_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_GetStatus
+//* \brief Return MC EFC Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_GetStatus(
+	AT91PS_MC pMC) // pointer to a MC controller
+{
+	return pMC->MC_FSR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_IsInterruptMasked
+//* \brief Test if EFC MC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
+        AT91PS_MC pMC,   // \arg  pointer to a MC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_EFC_IsInterruptSet
+//* \brief Test if EFC MC Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
+        AT91PS_MC pMC,   // \arg  pointer to a MC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_MC_EFC_GetStatus(pMC) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR SPI
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Open
+//* \brief Open a SPI Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_Open (
+        const unsigned int null)  // \arg
+{
+        /* NOT DEFINED AT THIS MOMENT */
+        return ( 0 );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgCs
+//* \brief Configure SPI chip select register
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgCs (
+	AT91PS_SPI pSPI,     // pointer to a SPI controller
+	int cs,     // SPI cs number (0 to 3)
+ 	int val)   //  chip select register
+{
+	//* Write to the CSR register
+	*(pSPI->SPI_CSR + cs) = val;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_EnableIt
+//* \brief Enable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_EnableIt (
+	AT91PS_SPI pSPI,     // pointer to a SPI controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pSPI->SPI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_DisableIt
+//* \brief Disable SPI interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_DisableIt (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pSPI->SPI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Reset
+//* \brief Reset the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Reset (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SWRST;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Enable
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Enable (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SPIEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Disable
+//* \brief Disable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Disable (
+	AT91PS_SPI pSPI // pointer to a SPI controller
+	)
+{
+	//* Write to the CR register
+	pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgMode
+//* \brief Enable the SPI controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgMode (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	int mode)        // mode register
+{
+	//* Write to the MR register
+	pSPI->SPI_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_CfgPCS
+//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_CfgPCS (
+	AT91PS_SPI pSPI, // pointer to a SPI controller
+	char PCS_Device) // PCS of the Device
+{	
+ 	//* Write to the MR register
+	pSPI->SPI_MR &= 0xFFF0FFFF;
+	pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_ReceiveFrame (
+	AT91PS_SPI pSPI,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pSPI->SPI_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_SendFrame(
+	AT91PS_SPI pSPI,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pSPI->SPI_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_Close
+//* \brief Close SPI: disable IT disable transfert, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_Close (
+	AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
+{
+    //* Reset all the Chip Select register
+    pSPI->SPI_CSR[0] = 0 ;
+    pSPI->SPI_CSR[1] = 0 ;
+    pSPI->SPI_CSR[2] = 0 ;
+    pSPI->SPI_CSR[3] = 0 ;
+
+    //* Reset the SPI mode
+    pSPI->SPI_MR = 0  ;
+
+    //* Disable all interrupts
+    pSPI->SPI_IDR = 0xFFFFFFFF ;
+
+    //* Abort the Peripheral Data Transfers
+    AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
+
+    //* Disable receiver and transmitter and stop any activity immediately
+    pSPI->SPI_CR = AT91C_SPI_SPIDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI_PutChar (
+	AT91PS_SPI pSPI,
+	unsigned int character,
+             unsigned int cs_number )
+{
+    unsigned int value_for_cs;
+    value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number
+    pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_GetChar (
+	const AT91PS_SPI pSPI)
+{
+    return((pSPI->SPI_RDR) & 0xFFFF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_GetInterruptMaskStatus
+//* \brief Return SPI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
+        AT91PS_SPI pSpi) // \arg  pointer to a SPI controller
+{
+        return pSpi->SPI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI_IsInterruptMasked
+//* \brief Test if SPI Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_SPI_IsInterruptMasked(
+        AT91PS_SPI pSpi,   // \arg  pointer to a SPI controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR USART
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Baudrate
+//* \brief Calculate the baudrate
+//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
+                        AT91C_US_NBSTOP_1_BIT + \
+                        AT91C_US_PAR_NONE + \
+                        AT91C_US_CHRL_8_BITS + \
+                        AT91C_US_CLKS_CLOCK )
+
+//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
+                            AT91C_US_NBSTOP_1_BIT + \
+                            AT91C_US_PAR_NONE + \
+                            AT91C_US_CHRL_8_BITS + \
+                            AT91C_US_CLKS_EXT )
+
+//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
+#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
+                       AT91C_US_USMODE_NORMAL + \
+                       AT91C_US_NBSTOP_1_BIT + \
+                       AT91C_US_PAR_NONE + \
+                       AT91C_US_CHRL_8_BITS + \
+                       AT91C_US_CLKS_CLOCK )
+
+//* SCK used Label
+#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
+
+//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
+#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
+					   		 AT91C_US_CLKS_CLOCK +\
+                       		 AT91C_US_NBSTOP_1_BIT + \
+                       		 AT91C_US_PAR_EVEN + \
+                       		 AT91C_US_CHRL_8_BITS + \
+                       		 AT91C_US_CKLO +\
+                       		 AT91C_US_OVER)
+
+//* Standard IRDA mode
+#define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \
+                            AT91C_US_NBSTOP_1_BIT + \
+                            AT91C_US_PAR_NONE + \
+                            AT91C_US_CHRL_8_BITS + \
+                            AT91C_US_CLKS_CLOCK )
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Baudrate
+//* \brief Caluculate baud_value according to the main clock and the baud rate
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Baudrate (
+	const unsigned int main_clock, // \arg peripheral clock
+	const unsigned int baud_rate)  // \arg UART baudrate
+{
+	unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
+	if ((baud_value % 10) >= 5)
+		baud_value = (baud_value / 10) + 1;
+	else
+		baud_value /= 10;
+	return baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetBaudrate (
+	AT91PS_USART pUSART,    // \arg pointer to a USART controller
+	unsigned int mainClock, // \arg peripheral clock
+	unsigned int speed)     // \arg UART baudrate
+{
+	//* Define the baud rate divisor register
+	pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetTimeguard
+//* \brief Set USART timeguard
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetTimeguard (
+	AT91PS_USART pUSART,    // \arg pointer to a USART controller
+	unsigned int timeguard) // \arg timeguard value
+{
+	//* Write the Timeguard Register
+	pUSART->US_TTGR = timeguard ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableIt
+//* \brief Enable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableIt (
+	AT91PS_USART pUSART, // \arg pointer to a USART controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pUSART->US_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableIt
+//* \brief Disable USART IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableIt (
+	AT91PS_USART pUSART, // \arg pointer to a USART controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IER register
+	pUSART->US_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Configure
+//* \brief Configure USART
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Configure (
+	AT91PS_USART pUSART,     // \arg pointer to a USART controller
+	unsigned int mainClock,  // \arg peripheral clock
+	unsigned int mode ,      // \arg mode Register to be programmed
+	unsigned int baudRate ,  // \arg baudrate to be programmed
+	unsigned int timeguard ) // \arg timeguard to be programmed
+{
+    //* Disable interrupts
+    pUSART->US_IDR = (unsigned int) -1;
+
+    //* Reset receiver and transmitter
+    pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
+
+	//* Define the baud rate divisor register
+	AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
+
+	//* Write the Timeguard Register
+	AT91F_US_SetTimeguard(pUSART, timeguard);
+
+    //* Clear Transmit and Receive Counters
+    AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
+
+    //* Define the USART mode
+    pUSART->US_MR = mode  ;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableRx
+//* \brief Enable receiving characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Enable receiver
+    pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_EnableTx
+//* \brief Enable sending characters
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_EnableTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Enable  transmitter
+    pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ResetRx
+//* \brief Reset Receiver and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+	//* Reset receiver
+	pUSART->US_CR = AT91C_US_RSTRX;
+    //* Re-Enable receiver
+    pUSART->US_CR = AT91C_US_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ResetTx
+//* \brief Reset Transmitter and re-enable it
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_ResetTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+	//* Reset transmitter
+	pUSART->US_CR = AT91C_US_RSTTX;
+    //* Enable transmitter
+    pUSART->US_CR = AT91C_US_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableRx
+//* \brief Disable Receiver
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableRx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Disable receiver
+    pUSART->US_CR = AT91C_US_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_DisableTx
+//* \brief Disable Transmitter
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_DisableTx (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Disable transmitter
+    pUSART->US_CR = AT91C_US_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Close
+//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_Close (
+	AT91PS_USART pUSART)     // \arg pointer to a USART controller
+{
+    //* Reset the baud rate divisor register
+    pUSART->US_BRGR = 0 ;
+
+    //* Reset the USART mode
+    pUSART->US_MR = 0  ;
+
+    //* Reset the Timeguard Register
+    pUSART->US_TTGR = 0;
+
+    //* Disable all interrupts
+    pUSART->US_IDR = 0xFFFFFFFF ;
+
+    //* Abort the Peripheral Data Transfers
+    AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
+
+    //* Disable receiver and transmitter and stop any activity immediately
+    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_TxReady
+//* \brief Return 1 if a character can be written in US_THR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_TxReady (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR & AT91C_US_TXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_RxReady
+//* \brief Return 1 if a character can be read in US_RHR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_RxReady (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR & AT91C_US_RXRDY);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_Error
+//* \brief Return the error flag
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_Error (
+	AT91PS_USART pUSART )     // \arg pointer to a USART controller
+{
+    return (pUSART->US_CSR &
+    	(AT91C_US_OVRE |  // Overrun error
+    	 AT91C_US_FRAME | // Framing error
+    	 AT91C_US_PARE));  // Parity error
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_PutChar
+//* \brief Send a character,does not check if ready to send
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_PutChar (
+	AT91PS_USART pUSART,
+	int character )
+{
+    pUSART->US_THR = (character & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_GetChar
+//* \brief Receive a character,does not check if a character is available
+//*----------------------------------------------------------------------------
+__inline int AT91F_US_GetChar (
+	const AT91PS_USART pUSART)
+{
+    return((pUSART->US_RHR) & 0x1FF);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_SendFrame(
+	AT91PS_USART pUSART,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pUSART->US_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_US_ReceiveFrame (
+	AT91PS_USART pUSART,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pUSART->US_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US_SetIrdaFilter
+//* \brief Set the value of IrDa filter tregister
+//*----------------------------------------------------------------------------
+__inline void AT91F_US_SetIrdaFilter (
+	AT91PS_USART pUSART,
+	unsigned char value
+)
+{
+	pUSART->US_IF = value;
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR SSC
+   ***************************************************************************** */
+//* Define the standard I2S mode configuration
+
+//* Configuration to set in the SSC Transmit Clock Mode Register
+//* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
+//* 			  nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+									   AT91C_SSC_CKS_DIV   +\
+                            		   AT91C_SSC_CKO_CONTINOUS      +\
+                            		   AT91C_SSC_CKG_NONE    +\
+                                       AT91C_SSC_START_FALL_RF +\
+                           			   AT91C_SSC_STTOUT  +\
+                            		   ((1<<16) & AT91C_SSC_STTDLY) +\
+                            		   ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
+
+
+//* Configuration to set in the SSC Transmit Frame Mode Register
+//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
+//* 			 nb_slot_by_frame : number of channels
+#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
+									(nb_bit_by_slot-1)  +\
+                            		AT91C_SSC_MSBF   +\
+                            		(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
+                            		(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
+                            		AT91C_SSC_FSOS_NEGATIVE)
+
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_SetBaudrate
+//* \brief Set the baudrate according to the CPU clock
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_SetBaudrate (
+        AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
+        unsigned int mainClock, // \arg peripheral clock
+        unsigned int speed)     // \arg SSC baudrate
+{
+        unsigned int baud_value;
+        //* Define the baud rate divisor register
+        if (speed == 0)
+           baud_value = 0;
+        else
+        {
+           baud_value = (unsigned int) (mainClock * 10)/(2*speed);
+           if ((baud_value % 10) >= 5)
+                  baud_value = (baud_value / 10) + 1;
+           else
+                  baud_value /= 10;
+        }
+
+        pSSC->SSC_CMR = baud_value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_Configure
+//* \brief Configure SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_Configure (
+             AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
+             unsigned int syst_clock,  // \arg System Clock Frequency
+             unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
+             unsigned int clock_rx,    // \arg Receiver Clock Parameters
+             unsigned int mode_rx,     // \arg mode Register to be programmed
+             unsigned int clock_tx,    // \arg Transmitter Clock Parameters
+             unsigned int mode_tx)     // \arg mode Register to be programmed
+{
+    //* Disable interrupts
+	pSSC->SSC_IDR = (unsigned int) -1;
+
+    //* Reset receiver and transmitter
+	pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
+
+    //* Define the Clock Mode Register
+	AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
+
+     //* Write the Receive Clock Mode Register
+	pSSC->SSC_RCMR =  clock_rx;
+
+     //* Write the Transmit Clock Mode Register
+	pSSC->SSC_TCMR =  clock_tx;
+
+     //* Write the Receive Frame Mode Register
+	pSSC->SSC_RFMR =  mode_rx;
+
+     //* Write the Transmit Frame Mode Register
+	pSSC->SSC_TFMR =  mode_tx;
+
+    //* Clear Transmit and Receive Counters
+	AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
+
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableRx
+//* \brief Enable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableRx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Enable receiver
+    pSSC->SSC_CR = AT91C_SSC_RXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableRx
+//* \brief Disable receiving datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableRx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Disable receiver
+    pSSC->SSC_CR = AT91C_SSC_RXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableTx
+//* \brief Enable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableTx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Enable  transmitter
+    pSSC->SSC_CR = AT91C_SSC_TXEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableTx
+//* \brief Disable sending datas
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableTx (
+	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
+{
+    //* Disable  transmitter
+    pSSC->SSC_CR = AT91C_SSC_TXDIS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_EnableIt
+//* \brief Enable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_EnableIt (
+	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pSSC->SSC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_DisableIt
+//* \brief Disable SSC IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_DisableIt (
+	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pSSC->SSC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_ReceiveFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_ReceiveFrame (
+	AT91PS_SSC pSSC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_ReceiveFrame(
+		(AT91PS_PDC) &(pSSC->SSC_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_SendFrame
+//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_SendFrame(
+	AT91PS_SSC pSSC,
+	char *pBuffer,
+	unsigned int szBuffer,
+	char *pNextBuffer,
+	unsigned int szNextBuffer )
+{
+	return AT91F_PDC_SendFrame(
+		(AT91PS_PDC) &(pSSC->SSC_RPR),
+		pBuffer,
+		szBuffer,
+		pNextBuffer,
+		szNextBuffer);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_GetInterruptMaskStatus
+//* \brief Return SSC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
+        AT91PS_SSC pSsc) // \arg  pointer to a SSC controller
+{
+        return pSsc->SSC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_IsInterruptMasked
+//* \brief Test if SSC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_SSC_IsInterruptMasked(
+        AT91PS_SSC pSsc,   // \arg  pointer to a SSC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TWI
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_EnableIt
+//* \brief Enable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_EnableIt (
+	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pTWI->TWI_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_DisableIt
+//* \brief Disable TWI IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_DisableIt (
+	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pTWI->TWI_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_Configure
+//* \brief Configure TWI in master mode
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \arg pointer to a TWI controller
+{
+    //* Disable interrupts
+	pTWI->TWI_IDR = (unsigned int) -1;
+
+    //* Reset peripheral
+	pTWI->TWI_CR = AT91C_TWI_SWRST;
+
+	//* Set Master mode
+	pTWI->TWI_CR = AT91C_TWI_MSEN;
+
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_GetInterruptMaskStatus
+//* \brief Return TWI Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
+        AT91PS_TWI pTwi) // \arg  pointer to a TWI controller
+{
+        return pTwi->TWI_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_IsInterruptMasked
+//* \brief Test if TWI Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_TWI_IsInterruptMasked(
+        AT91PS_TWI pTwi,   // \arg  pointer to a TWI controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR PWMC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_GetStatus
+//* \brief Return PWM Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
+	AT91PS_PWMC pPWM) // pointer to a PWM controller
+{
+	return pPWM->PWMC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_InterruptEnable
+//* \brief Enable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptEnable(
+        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  PWM interrupt to be enabled
+{
+        pPwm->PWMC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_InterruptDisable
+//* \brief Disable PWM Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_InterruptDisable(
+        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  PWM interrupt to be disabled
+{
+        pPwm->PWMC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_GetInterruptMaskStatus
+//* \brief Return PWM Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
+        AT91PS_PWMC pPwm) // \arg  pointer to a PWM controller
+{
+        return pPwm->PWMC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_IsInterruptMasked
+//* \brief Test if PWM Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsInterruptMasked(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_IsStatusSet
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_PWMC_IsStatusSet(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_PWMC_GetStatus(pPWM) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_CfgChannel
+//* \brief Test if PWM Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int channelId, // \arg PWM channel ID
+        unsigned int mode, // \arg  PWM mode
+        unsigned int period, // \arg PWM period
+        unsigned int duty) // \arg PWM duty cycle
+{
+	pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
+	pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
+	pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_StartChannel
+//* \brief Enable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StartChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_ENA = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_StopChannel
+//* \brief Disable channel
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_StopChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int flag) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_DIS = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWM_UpdateChannel
+//* \brief Update Period or Duty Cycle
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_UpdateChannel(
+        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
+        unsigned int channelId, // \arg PWM channel ID
+        unsigned int update) // \arg  Channels IDs to be enabled
+{
+	pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR UDP
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EnableIt
+//* \brief Enable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableIt (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg IT to be enabled
+{
+	//* Write to the IER register
+	pUDP->UDP_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_DisableIt
+//* \brief Disable UDP IT
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableIt (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg IT to be disabled
+{
+	//* Write to the IDR register
+	pUDP->UDP_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_SetAddress
+//* \brief Set UDP functional address
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetAddress (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char address)   // \arg new UDP address
+{
+	pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EnableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EnableEp (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_DisableEp
+//* \brief Enable Endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_DisableEp (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_SetState
+//* \brief Set UDP Device state
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_SetState (
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg new UDP address
+{
+	pUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
+	pUDP->UDP_GLBSTATE  |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_GetState
+//* \brief return UDP Device state
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
+	AT91PS_UDP pUDP)     // \arg pointer to a UDP controller
+{
+	return (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_ResetEp
+//* \brief Reset UDP endpoint
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned int flag)   // \arg Endpoints to be reset
+{
+	pUDP->UDP_RSTEP = flag;
+	pUDP->UDP_RSTEP = 0;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpStall
+//* \brief Endpoint will STALL requests
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpStall(
+	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
+	unsigned char endpoint)   // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpWrite
+//* \brief Write value in the DPR
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpWrite(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned char value)     // \arg value to be written in the DPR
+{
+	pUDP->UDP_FDR[endpoint] = value;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpRead
+//* \brief Return value from the DPR
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpRead(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	return pUDP->UDP_FDR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpEndOfWr
+//* \brief Notify the UDP that values in DPR are ready to be sent
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpEndOfWr(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpClear
+//* \brief Clear flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpClear(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned int flag)       // \arg flag to be cleared
+{
+	pUDP->UDP_CSR[endpoint] &= ~(flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpSet
+//* \brief Set flag in the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_EpSet(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint,  // \arg endpoint number
+	unsigned int flag)       // \arg flag to be cleared
+{
+	pUDP->UDP_CSR[endpoint] |= flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_EpStatus
+//* \brief Return the endpoint CSR register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_EpStatus(
+	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
+	unsigned char endpoint)  // \arg endpoint number
+{
+	return pUDP->UDP_CSR[endpoint];
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_GetInterruptMaskStatus
+//* \brief Return UDP Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
+        AT91PS_UDP pUdp) // \arg  pointer to a UDP controller
+{
+        return pUdp->UDP_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_IsInterruptMasked
+//* \brief Test if UDP Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_UDP_IsInterruptMasked(
+        AT91PS_UDP pUdp,   // \arg  pointer to a UDP controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_InterruptEnable
+//* \brief Enable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptEnable(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  TC interrupt to be enabled
+{
+        pTc->TC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_InterruptDisable
+//* \brief Disable TC Interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC_InterruptDisable(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  TC interrupt to be disabled
+{
+        pTc->TC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_GetInterruptMaskStatus
+//* \brief Return TC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
+        AT91PS_TC pTc) // \arg  pointer to a TC controller
+{
+        return pTc->TC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC_IsInterruptMasked
+//* \brief Test if TC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline int AT91F_TC_IsInterruptMasked(
+        AT91PS_TC pTc,   // \arg  pointer to a TC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+        return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR CAN
+   ***************************************************************************** */
+#define	STANDARD_FORMAT 0
+#define	EXTENDED_FORMAT 1
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_InitMailboxRegisters()
+//* \brief Configure the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB	CAN_Mailbox,
+								int  			mode_reg,
+								int 			acceptance_mask_reg,
+								int  			id_reg,
+								int  			data_low_reg,
+								int  			data_high_reg,
+								int  			control_reg)
+{
+	CAN_Mailbox->CAN_MB_MCR 	= 0x0;
+	CAN_Mailbox->CAN_MB_MMR 	= mode_reg;
+	CAN_Mailbox->CAN_MB_MAM 	= acceptance_mask_reg;
+	CAN_Mailbox->CAN_MB_MID 	= id_reg;
+	CAN_Mailbox->CAN_MB_MDL 	= data_low_reg; 		
+	CAN_Mailbox->CAN_MB_MDH 	= data_high_reg;
+	CAN_Mailbox->CAN_MB_MCR 	= control_reg;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EnableCAN()
+//* \brief
+//*----------------------------------------------------------------------------
+__inline void AT91F_EnableCAN(
+	AT91PS_CAN pCAN)     // pointer to a CAN controller
+{
+	pCAN->CAN_MR |= AT91C_CAN_CANEN;
+
+	// Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver
+	while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP );
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DisableCAN()
+//* \brief
+//*----------------------------------------------------------------------------
+__inline void AT91F_DisableCAN(
+	AT91PS_CAN pCAN)     // pointer to a CAN controller
+{
+	pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_EnableIt
+//* \brief Enable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_EnableIt (
+	AT91PS_CAN pCAN,     // pointer to a CAN controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pCAN->CAN_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_DisableIt
+//* \brief Disable CAN interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_DisableIt (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pCAN->CAN_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetStatus
+//* \brief Return CAN Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status
+	AT91PS_CAN pCAN) // pointer to a CAN controller
+{
+	return pCAN->CAN_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetInterruptMaskStatus
+//* \brief Return CAN Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status
+	AT91PS_CAN pCAN) // pointer to a CAN controller
+{
+	return pCAN->CAN_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_IsInterruptMasked
+//* \brief Test if CAN Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsInterruptMasked(
+        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_IsStatusSet
+//* \brief Test if CAN Interrupt is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_IsStatusSet(
+        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_CAN_GetStatus(pCAN) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgModeReg
+//* \brief Configure the Mode Register of the CAN controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgModeReg (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int mode)        // mode register
+{
+	//* Write to the MR register
+	pCAN->CAN_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetModeReg
+//* \brief Return the Mode Register of the CAN controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetModeReg (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgBaudrateReg
+//* \brief Configure the Baudrate of the CAN controller for the network
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgBaudrateReg (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+	unsigned int baudrate_cfg)
+{
+	//* Write to the BR register
+	pCAN->CAN_BR = baudrate_cfg;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetBaudrate
+//* \brief Return the Baudrate of the CAN controller for the network value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetBaudrate (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_BR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetInternalCounter
+//* \brief Return CAN Timer Regsiter Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetInternalCounter (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_TIM;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetTimestamp
+//* \brief Return CAN Timestamp Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetTimestamp (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_TIMESTP;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetErrorCounter
+//* \brief Return CAN Error Counter Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetErrorCounter (
+	AT91PS_CAN pCAN // pointer to a CAN controller
+	)
+{
+	return pCAN->CAN_ECR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_InitTransferRequest
+//* \brief Request for a transfer on the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitTransferRequest (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+    unsigned int transfer_cmd)
+{
+	pCAN->CAN_TCR = transfer_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_InitAbortRequest
+//* \brief Abort the corresponding mailboxes
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_InitAbortRequest (
+	AT91PS_CAN pCAN, // pointer to a CAN controller
+    unsigned int abort_cmd)
+{
+	pCAN->CAN_ACR = abort_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageModeReg
+//* \brief Program the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageModeReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int mode)
+{
+	CAN_Mailbox->CAN_MB_MMR = mode;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageModeReg
+//* \brief Return the Message Mode Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageModeReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MMR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageIDReg
+//* \brief Program the Message ID Register
+//* \brief Version == 0 for Standard messsage, Version == 1 for Extended
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageIDReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int id,
+    unsigned char version)
+{
+	if(version==0)	// IDvA Standard Format
+		CAN_Mailbox->CAN_MB_MID = id<<18;
+	else	// IDvB Extended Format
+		CAN_Mailbox->CAN_MB_MID = id | (1<<29);	// set MIDE bit
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageIDReg
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageIDReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MID;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageAcceptanceMaskReg
+//* \brief Program the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int mask)
+{
+	CAN_Mailbox->CAN_MB_MAM = mask;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageAcceptanceMaskReg
+//* \brief Return the Message Acceptance Mask Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MAM;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetFamilyID
+//* \brief Return the Message ID Register
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetFamilyID (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MFID;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageCtrl
+//* \brief Request and config for a transfer on the corresponding mailbox
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageCtrlReg (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int message_ctrl_cmd)
+{
+	CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageStatus
+//* \brief Return CAN Mailbox Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageStatus (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MSR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageDataLow
+//* \brief Program data low value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataLow (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int data)
+{
+	CAN_Mailbox->CAN_MB_MDL = data;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageDataLow
+//* \brief Return data low value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataLow (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MDL;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgMessageDataHigh
+//* \brief Program data high value
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgMessageDataHigh (
+	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
+    unsigned int data)
+{
+	CAN_Mailbox->CAN_MB_MDH = data;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_GetMessageDataHigh
+//* \brief Return data high value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_GetMessageDataHigh (
+	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
+{
+	return CAN_Mailbox->CAN_MB_MDH;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_Open
+//* \brief Open a CAN Port
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_CAN_Open (
+        const unsigned int null)  // \arg
+{
+        /* NOT DEFINED AT THIS MOMENT */
+        return ( 0 );
+}
+/* *****************************************************************************
+                SOFTWARE API FOR ADC
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_EnableIt
+//* \brief Enable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableIt (
+	AT91PS_ADC pADC,     // pointer to a ADC controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pADC->ADC_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_DisableIt
+//* \brief Disable ADC interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableIt (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pADC->ADC_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetStatus
+//* \brief Return ADC Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
+	AT91PS_ADC pADC) // pointer to a ADC controller
+{
+	return pADC->ADC_SR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetInterruptMaskStatus
+//* \brief Return ADC Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
+	AT91PS_ADC pADC) // pointer to a ADC controller
+{
+	return pADC->ADC_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_IsInterruptMasked
+//* \brief Test if ADC Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsInterruptMasked(
+        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_IsStatusSet
+//* \brief Test if ADC Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_IsStatusSet(
+        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_ADC_GetStatus(pADC) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgModeReg
+//* \brief Configure the Mode Register of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgModeReg (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int mode)        // mode register
+{
+	//* Write to the MR register
+	pADC->ADC_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetModeReg
+//* \brief Return the Mode Register of the ADC controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetModeReg (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgTimings
+//* \brief Configure the different necessary timings of the ADC controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgTimings (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int mck_clock, // in MHz
+	unsigned int adc_clock, // in MHz
+	unsigned int startup_time, // in us
+	unsigned int sample_and_hold_time)	// in ns
+{
+	unsigned int prescal,startup,shtim;
+	
+	prescal = mck_clock/(2*adc_clock) - 1;
+	startup = adc_clock*startup_time/8 - 1;
+	shtim = adc_clock*sample_and_hold_time/1000 - 1;
+	
+	//* Write to the MR register
+	pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_EnableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_EnableChannel (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int channel)        // mode register
+{
+	//* Write to the CHER register
+	pADC->ADC_CHER = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_DisableChannel
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_DisableChannel (
+	AT91PS_ADC pADC, // pointer to a ADC controller
+	unsigned int channel)        // mode register
+{
+	//* Write to the CHDR register
+	pADC->ADC_CHDR = channel;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetChannelStatus
+//* \brief Return ADC Timer Register Value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetChannelStatus (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CHSR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_StartConversion
+//* \brief Software request for a analog to digital conversion
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_StartConversion (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	pADC->ADC_CR = AT91C_ADC_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_SoftReset
+//* \brief Software reset
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_SoftReset (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	pADC->ADC_CR = AT91C_ADC_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetLastConvertedData
+//* \brief Return the Last Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetLastConvertedData (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_LCDR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH0
+//* \brief Return the Channel 0 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR0;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH1
+//* \brief Return the Channel 1 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR1;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH2
+//* \brief Return the Channel 2 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR2;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH3
+//* \brief Return the Channel 3 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR3;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH4
+//* \brief Return the Channel 4 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR4;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH5
+//* \brief Return the Channel 5 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR5;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH6
+//* \brief Return the Channel 6 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR6;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_GetConvertedDataCH7
+//* \brief Return the Channel 7 Converted Data
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
+	AT91PS_ADC pADC // pointer to a ADC controller
+	)
+{
+	return pADC->ADC_CDR7;	
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR AES
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_EnableIt
+//* \brief Enable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_EnableIt (
+	AT91PS_AES pAES,     // pointer to a AES controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pAES->AES_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_DisableIt
+//* \brief Disable AES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_DisableIt (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pAES->AES_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetStatus
+//* \brief Return AES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status
+	AT91PS_AES pAES) // pointer to a AES controller
+{
+	return pAES->AES_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetInterruptMaskStatus
+//* \brief Return AES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status
+	AT91PS_AES pAES) // pointer to a AES controller
+{
+	return pAES->AES_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_IsInterruptMasked
+//* \brief Test if AES Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsInterruptMasked(
+        AT91PS_AES pAES,   // \arg  pointer to a AES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_IsStatusSet
+//* \brief Test if AES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_IsStatusSet(
+        AT91PS_AES pAES,   // \arg  pointer to a AES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_AES_GetStatus(pAES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_CfgModeReg
+//* \brief Configure the Mode Register of the AES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgModeReg (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned int mode)        // mode register
+{
+	//* Write to the MR register
+	pAES->AES_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetModeReg
+//* \brief Return the Mode Register of the AES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetModeReg (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	return pAES->AES_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_StartProcessing (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SoftReset
+//* \brief Reset AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SoftReset (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_LoadNewSeed
+//* \brief Load New Seed in the random number generator
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_LoadNewSeed (
+	AT91PS_AES pAES // pointer to a AES controller
+	)
+{
+	pAES->AES_CR = AT91C_AES_LOADSEED;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SetCryptoKey
+//* \brief Set Cryptographic Key x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetCryptoKey (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pAES->AES_KEYWxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_InputData (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int indata
+	)
+{
+	pAES->AES_IDATAxR[index] = indata;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_AES_GetOutputData (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index
+	)
+{
+	return pAES->AES_ODATAxR[index];	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_SetInitializationVector
+//* \brief Set Initialization Vector (or Counter) x
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_SetInitializationVector (
+	AT91PS_AES pAES, // pointer to a AES controller
+	unsigned char index,
+	unsigned int initvector
+	)
+{
+	pAES->AES_IVxR[index] = initvector;	
+}
+
+/* *****************************************************************************
+                SOFTWARE API FOR TDES
+   ***************************************************************************** */
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_EnableIt
+//* \brief Enable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_EnableIt (
+	AT91PS_TDES pTDES,     // pointer to a TDES controller
+	unsigned int flag)   // IT to be enabled
+{
+	//* Write to the IER register
+	pTDES->TDES_IER = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_DisableIt
+//* \brief Disable TDES interrupt
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_DisableIt (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned int flag) // IT to be disabled
+{
+	//* Write to the IDR register
+	pTDES->TDES_IDR = flag;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetStatus
+//* \brief Return TDES Interrupt Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status
+	AT91PS_TDES pTDES) // pointer to a TDES controller
+{
+	return pTDES->TDES_ISR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetInterruptMaskStatus
+//* \brief Return TDES Interrupt Mask Status
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status
+	AT91PS_TDES pTDES) // pointer to a TDES controller
+{
+	return pTDES->TDES_IMR;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_IsInterruptMasked
+//* \brief Test if TDES Interrupt is Masked
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsInterruptMasked(
+        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_IsStatusSet
+//* \brief Test if TDES Status is Set
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_IsStatusSet(
+        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
+        unsigned int flag) // \arg  flag to be tested
+{
+	return (AT91F_TDES_GetStatus(pTDES) & flag);
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_CfgModeReg
+//* \brief Configure the Mode Register of the TDES controller
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgModeReg (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned int mode)        // mode register
+{
+	//* Write to the MR register
+	pTDES->TDES_MR = mode;
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetModeReg
+//* \brief Return the Mode Register of the TDES controller value
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetModeReg (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	return pTDES->TDES_MR;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_StartProcessing
+//* \brief Start Encryption or Decryption
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_StartProcessing (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	pTDES->TDES_CR = AT91C_TDES_START;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SoftReset
+//* \brief Reset TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SoftReset (
+	AT91PS_TDES pTDES // pointer to a TDES controller
+	)
+{
+	pTDES->TDES_CR = AT91C_TDES_SWRST;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey1
+//* \brief Set Cryptographic Key 1 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey1 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY1WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey2
+//* \brief Set Cryptographic Key 2 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey2 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY2WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetCryptoKey3
+//* \brief Set Cryptographic Key 3 Word x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetCryptoKey3 (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int keyword
+	)
+{
+	pTDES->TDES_KEY3WxR[index] = keyword;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_InputData
+//* \brief Set Input Data x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_InputData (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int indata
+	)
+{
+	pTDES->TDES_IDATAxR[index] = indata;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_GetOutputData
+//* \brief Get Output Data x
+//*----------------------------------------------------------------------------
+__inline unsigned int AT91F_TDES_GetOutputData (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index
+	)
+{
+	return pTDES->TDES_ODATAxR[index];	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_SetInitializationVector
+//* \brief Set Initialization Vector x
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_SetInitializationVector (
+	AT91PS_TDES pTDES, // pointer to a TDES controller
+	unsigned char index,
+	unsigned int initvector
+	)
+{
+	pTDES->TDES_IVxR[index] = initvector;	
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  DBGU
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_DBGU_CfgPIO
+//* \brief Configure PIO controllers to drive DBGU signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_DBGU_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA27_DRXD    ) |
+		((unsigned int) AT91C_PA28_DTXD    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PMC_CfgPIO
+//* \brief Configure PIO controllers to drive PMC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PMC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB30_PCK2    ) |
+		((unsigned int) AT91C_PB29_PCK1    ), // Peripheral A
+		((unsigned int) AT91C_PB20_PCK0    ) |
+		((unsigned int) AT91C_PB0_PCK0    ) |
+		((unsigned int) AT91C_PB22_PCK2    ) |
+		((unsigned int) AT91C_PB21_PCK1    )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA30_PCK2    ) |
+		((unsigned int) AT91C_PA13_PCK1    ) |
+		((unsigned int) AT91C_PA27_PCK3    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_VREG_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  VREG
+//*----------------------------------------------------------------------------
+__inline void AT91F_VREG_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RSTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  RSTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RSTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SSC
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SSC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SSC_CfgPIO
+//* \brief Configure PIO controllers to drive SSC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SSC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA25_RK      ) |
+		((unsigned int) AT91C_PA22_TK      ) |
+		((unsigned int) AT91C_PA21_TF      ) |
+		((unsigned int) AT91C_PA24_RD      ) |
+		((unsigned int) AT91C_PA26_RF      ) |
+		((unsigned int) AT91C_PA23_TD      ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_WDTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  WDTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_WDTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  US1
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_US1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US1_CfgPIO
+//* \brief Configure PIO controllers to drive US1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB26_RI1     ) |
+		((unsigned int) AT91C_PB24_DSR1    ) |
+		((unsigned int) AT91C_PB23_DCD1    ) |
+		((unsigned int) AT91C_PB25_DTR1    )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA7_SCK1    ) |
+		((unsigned int) AT91C_PA8_RTS1    ) |
+		((unsigned int) AT91C_PA6_TXD1    ) |
+		((unsigned int) AT91C_PA5_RXD1    ) |
+		((unsigned int) AT91C_PA9_CTS1    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  US0
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_US0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_US0_CfgPIO
+//* \brief Configure PIO controllers to drive US0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_US0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA0_RXD0    ) |
+		((unsigned int) AT91C_PA4_CTS0    ) |
+		((unsigned int) AT91C_PA3_RTS0    ) |
+		((unsigned int) AT91C_PA2_SCK0    ) |
+		((unsigned int) AT91C_PA1_TXD0    ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SPI1
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SPI1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI1_CfgPIO
+//* \brief Configure PIO controllers to drive SPI1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB16_NPCS13  ) |
+		((unsigned int) AT91C_PB10_NPCS11  ) |
+		((unsigned int) AT91C_PB11_NPCS12  )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA4_NPCS13  ) |
+		((unsigned int) AT91C_PA29_NPCS13  ) |
+		((unsigned int) AT91C_PA21_NPCS10  ) |
+		((unsigned int) AT91C_PA22_SPCK1   ) |
+		((unsigned int) AT91C_PA25_NPCS11  ) |
+		((unsigned int) AT91C_PA2_NPCS11  ) |
+		((unsigned int) AT91C_PA24_MISO1   ) |
+		((unsigned int) AT91C_PA3_NPCS12  ) |
+		((unsigned int) AT91C_PA26_NPCS12  ) |
+		((unsigned int) AT91C_PA23_MOSI1   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  SPI0
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SPI0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_SPI0_CfgPIO
+//* \brief Configure PIO controllers to drive SPI0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_SPI0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB13_NPCS01  ) |
+		((unsigned int) AT91C_PB17_NPCS03  ) |
+		((unsigned int) AT91C_PB14_NPCS02  )); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA16_MISO0   ) |
+		((unsigned int) AT91C_PA13_NPCS01  ) |
+		((unsigned int) AT91C_PA15_NPCS03  ) |
+		((unsigned int) AT91C_PA17_MOSI0   ) |
+		((unsigned int) AT91C_PA18_SPCK0   ) |
+		((unsigned int) AT91C_PA14_NPCS02  ) |
+		((unsigned int) AT91C_PA12_NPCS00  ), // Peripheral A
+		((unsigned int) AT91C_PA7_NPCS01  ) |
+		((unsigned int) AT91C_PA9_NPCS03  ) |
+		((unsigned int) AT91C_PA8_NPCS02  )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PITC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PITC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PITC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  AIC
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_FIQ) |
+		((unsigned int) 1 << AT91C_ID_IRQ0) |
+		((unsigned int) 1 << AT91C_ID_IRQ1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AIC_CfgPIO
+//* \brief Configure PIO controllers to drive AIC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_AIC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA30_IRQ0    ) |
+		((unsigned int) AT91C_PA29_FIQ     ), // Peripheral A
+		((unsigned int) AT91C_PA14_IRQ1    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_AES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  AES
+//*----------------------------------------------------------------------------
+__inline void AT91F_AES_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_AES));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TWI
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TWI));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TWI_CfgPIO
+//* \brief Configure PIO controllers to drive TWI signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TWI_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA11_TWCK    ) |
+		((unsigned int) AT91C_PA10_TWD     ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  ADC
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_ADC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_ADC_CfgPIO
+//* \brief Configure PIO controllers to drive ADC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_ADC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PB18_ADTRG   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH3_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH3 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH3_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB22_PWM3    ), // Peripheral A
+		((unsigned int) AT91C_PB30_PWM3    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH2_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH2_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB21_PWM2    ), // Peripheral A
+		((unsigned int) AT91C_PB29_PWM2    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH1_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB20_PWM1    ), // Peripheral A
+		((unsigned int) AT91C_PB28_PWM1    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CH0_CfgPIO
+//* \brief Configure PIO controllers to drive PWMC_CH0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CH0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB19_PWM0    ), // Peripheral A
+		((unsigned int) AT91C_PB27_PWM0    )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_RTTC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  RTTC
+//*----------------------------------------------------------------------------
+__inline void AT91F_RTTC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_UDP_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  UDP
+//*----------------------------------------------------------------------------
+__inline void AT91F_UDP_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_UDP));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TDES_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TDES
+//*----------------------------------------------------------------------------
+__inline void AT91F_TDES_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TDES));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EMAC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  EMAC
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_EMAC));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_EMAC_CfgPIO
+//* \brief Configure PIO controllers to drive EMAC signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_EMAC_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB2_ETX0    ) |
+		((unsigned int) AT91C_PB12_ETXER   ) |
+		((unsigned int) AT91C_PB16_ECOL    ) |
+		((unsigned int) AT91C_PB11_ETX3    ) |
+		((unsigned int) AT91C_PB6_ERX1    ) |
+		((unsigned int) AT91C_PB15_ERXDV   ) |
+		((unsigned int) AT91C_PB13_ERX2    ) |
+		((unsigned int) AT91C_PB3_ETX1    ) |
+		((unsigned int) AT91C_PB8_EMDC    ) |
+		((unsigned int) AT91C_PB5_ERX0    ) |
+		//((unsigned int) AT91C_PB18_EF100   ) |
+		((unsigned int) AT91C_PB14_ERX3    ) |
+		((unsigned int) AT91C_PB4_ECRS_ECRSDV) |
+		((unsigned int) AT91C_PB1_ETXEN   ) |
+		((unsigned int) AT91C_PB10_ETX2    ) |
+		((unsigned int) AT91C_PB0_ETXCK_EREFCK) |
+		((unsigned int) AT91C_PB9_EMDIO   ) |
+		((unsigned int) AT91C_PB7_ERXER   ) |
+		((unsigned int) AT91C_PB17_ERXCK   ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC0_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC0
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC0));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC0_CfgPIO
+//* \brief Configure PIO controllers to drive TC0 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC0_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB23_TIOA0   ) |
+		((unsigned int) AT91C_PB24_TIOB0   ), // Peripheral A
+		((unsigned int) AT91C_PB12_TCLK0   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC1_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC1
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC1));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC1_CfgPIO
+//* \brief Configure PIO controllers to drive TC1 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC1_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB25_TIOA1   ) |
+		((unsigned int) AT91C_PB26_TIOB1   ), // Peripheral A
+		((unsigned int) AT91C_PB19_TCLK1   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC2_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  TC2
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_TC2));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_TC2_CfgPIO
+//* \brief Configure PIO controllers to drive TC2 signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_TC2_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOB, // PIO controller base address
+		((unsigned int) AT91C_PB28_TIOB2   ) |
+		((unsigned int) AT91C_PB27_TIOA2   ), // Peripheral A
+		0); // Peripheral B
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		0, // Peripheral A
+		((unsigned int) AT91C_PA15_TCLK2   )); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_MC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  MC
+//*----------------------------------------------------------------------------
+__inline void AT91F_MC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_SYS));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIOA_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PIOA
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOA_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PIOA));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PIOB_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PIOB
+//*----------------------------------------------------------------------------
+__inline void AT91F_PIOB_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PIOB));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  CAN
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_CAN));
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_CAN_CfgPIO
+//* \brief Configure PIO controllers to drive CAN signals
+//*----------------------------------------------------------------------------
+__inline void AT91F_CAN_CfgPIO (void)
+{
+	// Configure PIO controllers to periph mode
+	AT91F_PIO_CfgPeriph(
+		AT91C_BASE_PIOA, // PIO controller base address
+		((unsigned int) AT91C_PA20_CANTX   ) |
+		((unsigned int) AT91C_PA19_CANRX   ), // Peripheral A
+		0); // Peripheral B
+}
+
+//*----------------------------------------------------------------------------
+//* \fn    AT91F_PWMC_CfgPMC
+//* \brief Enable Peripheral clock in PMC for  PWMC
+//*----------------------------------------------------------------------------
+__inline void AT91F_PWMC_CfgPMC (void)
+{
+	AT91F_PMC_EnablePeriphClock(
+		AT91C_BASE_PMC, // PIO controller base address
+		((unsigned int) 1 << AT91C_ID_PWMC));
+}
+
+#endif // lib_AT91SAM7X256_H
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/port.c
new file mode 100644
index 0000000..b3dc0c9
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/port.c
@@ -0,0 +1,259 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Atmel ARM7 port.
+ *----------------------------------------------------------*/
+
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the initial stack. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+
+/* Constants required to setup the PIT. */
+#define portPIT_CLOCK_DIVISOR			( ( uint32_t ) 16 )
+#define portPIT_COUNTER_VALUE			( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
+
+
+#define portINT_LEVEL_SENSITIVE  0
+#define portPIT_ENABLE      	( ( uint16_t ) 0x1 << 24 )
+#define portPIT_INT_ENABLE     	( ( uint16_t ) 0x1 << 25 )
+/*-----------------------------------------------------------*/
+
+/* Setup the PIT to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* ulCriticalNesting will get set to zero when the first task starts.  It
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
+uint32_t ulCriticalNesting = ( uint32_t ) 9999;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The status register is set for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+	
+	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}	
+	
+	pxTopOfStack--;
+
+	/* Interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+
+	return pxTopOfStack;	
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 0
+
+	/* The cooperative scheduler requires a normal IRQ service routine to
+	simply increment the system tick. */
+	static __arm __irq void vPortNonPreemptiveTick( void );
+	static __arm __irq void vPortNonPreemptiveTick( void )
+	{
+		uint32_t ulDummy;
+		
+		/* Increment the tick count - which may wake some tasks but as the
+		preemptive scheduler is not being used any woken task is not given
+		processor time no matter what its priority. */
+		xTaskIncrementTick();
+		
+		/* Clear the PIT interrupt. */
+		ulDummy = AT91C_BASE_PITC->PITC_PIVR;
+		
+		/* End the interrupt in the AIC. */
+		AT91C_BASE_AIC->AIC_EOICR = ulDummy;
+	}
+
+#else
+
+	/* Currently the IAR port requires the preemptive tick function to be
+	defined in an asm file. */
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+AT91PS_PITC pxPIT = AT91C_BASE_PITC;
+
+	/* Setup the AIC for PIT interrupts.  The interrupt routine chosen depends
+	on whether the preemptive or cooperative scheduler is being used. */
+	#if configUSE_PREEMPTION == 0
+
+		AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortNonPreemptiveTick );
+
+	#else
+		
+		extern void ( vPortPreemptiveTick )( void );
+		AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortPreemptiveTick );
+
+	#endif
+
+	/* Configure the PIT period. */
+	pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
+
+	/* Enable the interrupt.  Global interrupts are disables at this point so
+	this is safe. */
+	AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts first! */
+	__disable_interrupt();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			__enable_interrupt();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portasm.s79 b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portasm.s79
new file mode 100644
index 0000000..b2f5a3f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portasm.s79
@@ -0,0 +1,88 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+		RSEG ICODE:CODE
+		CODE32
+
+	EXTERN vTaskSwitchContext
+	EXTERN xTaskIncrementTick
+
+	PUBLIC vPortYieldProcessor
+	PUBLIC vPortPreemptiveTick
+	PUBLIC vPortStartFirstTask
+
+#include "AT91SAM7S64_inc.h"
+#include "ISR_Support.h"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Starting the first task is just a matter of restoring the context that
+; was created by pxPortInitialiseStack().
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Manual context switch function.  This is the SWI hander.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortYieldProcessor:
+	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
+								; as if the context was saved during and IRQ
+								; handler.
+
+	portSAVE_CONTEXT			; Save the context of the current task...
+	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
+	mov     lr, pc
+	BX R0
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Preemptive context switch function.  This will only ever get installed if
+; portUSE_PREEMPTION is set to 1 in portmacro.h.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortPreemptiveTick:
+	portSAVE_CONTEXT			; Save the context of the current task.
+
+	LDR R0, =xTaskIncrementTick ; Increment the tick count - this may wake a task.
+	mov lr, pc
+	BX R0
+
+	CMP R0, #0
+	BEQ SkipContextSwitch
+	LDR R0, =vTaskSwitchContext ; Select the next task to execute.
+	mov lr, pc
+	BX R0
+SkipContextSwitch
+	LDR	R14, =AT91C_BASE_PITC	; Clear the PIT interrupt
+	LDR	R0, [R14, #PITC_PIVR ]
+
+	LDR R14, =AT91C_BASE_AIC	; Mark the End of Interrupt on the AIC
+    STR	R14, [R14, #AIC_EOICR]
+
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+
+
+	END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portmacro.h
new file mode 100644
index 0000000..16bb707
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portmacro.h
@@ -0,0 +1,111 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portYIELD()					asm ( "SWI 0" )
+#define portNOP()					asm ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+__arm __interwork void vPortDisableInterruptsFromThumb( void );
+__arm __interwork void vPortEnableInterruptsFromThumb( void );
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()	__disable_interrupt()
+#define portENABLE_INTERRUPTS()		__enable_interrupt()
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
+{													\
+extern void vTaskSwitchContext( void );				\
+													\
+	if( xSwitchRequired ) 							\
+	{												\
+		vTaskSwitchContext();						\
+	}												\
+}
+/*-----------------------------------------------------------*/
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/ISR_Support.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/ISR_Support.h
new file mode 100644
index 0000000..4a32f39
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/ISR_Support.h
@@ -0,0 +1,78 @@
+	EXTERN pxCurrentTCB
+	EXTERN ulCriticalNesting
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+portSAVE_CONTEXT MACRO
+
+	; Push R0 as we are going to use the register. 					
+	STMDB	SP!, {R0}
+
+	; Set R0 to point to the task stack pointer. 					
+	STMDB	SP, {SP}^
+	NOP
+	SUB		SP, SP, #4
+	LDMIA	SP!, {R0}
+
+	; Push the return address onto the stack. 						
+	STMDB	R0!, {LR}
+
+	; Now we have saved LR we can use it instead of R0. 				
+	MOV		LR, R0
+
+	; Pop R0 so we can save it onto the system mode stack. 			
+	LDMIA	SP!, {R0}
+
+	; Push all the system mode registers onto the task stack. 		
+	STMDB	LR, {R0-LR}^
+	NOP
+	SUB		LR, LR, #60
+
+	; Push the SPSR onto the task stack. 							
+	MRS		R0, SPSR
+	STMDB	LR!, {R0}
+
+	LDR		R0, =ulCriticalNesting 
+	LDR		R0, [R0]
+	STMDB	LR!, {R0}
+
+	; Store the new top of stack for the task. 						
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	STR		LR, [R0]
+
+	ENDM
+
+
+portRESTORE_CONTEXT MACRO
+
+	; Set the LR to the task stack. 									
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	LDR		LR, [R0]
+
+	; The critical nesting depth is the first item on the stack. 	
+	; Load it into the ulCriticalNesting variable. 					
+	LDR		R0, =ulCriticalNesting
+	LDMFD	LR!, {R1}
+	STR		R1, [R0]
+
+	; Get the SPSR from the stack. 									
+	LDMFD	LR!, {R0}
+	MSR		SPSR_cxsf, R0
+
+	; Restore all system mode registers for the task. 				
+	LDMFD	LR, {R0-R14}^
+	NOP
+
+	; Restore the return address. 									
+	LDR		LR, [LR, #+60]
+
+	; And return - correcting the offset in the LR to obtain the 	
+	; correct address. 												
+	SUBS	PC, LR, #4
+
+	ENDM
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/port.c
new file mode 100644
index 0000000..8e65038
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/port.c
@@ -0,0 +1,256 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Atmel ARM7 port.
+ *----------------------------------------------------------*/
+
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Hardware includes. */
+#include <board.h>
+#include <pio/pio.h>
+#include <pio/pio_it.h>
+#include <pit/pit.h>
+#include <aic/aic.h>
+#include <tc/tc.h>
+#include <utility/led.h>
+#include <utility/trace.h>
+
+/*-----------------------------------------------------------*/
+
+/* Constants required to setup the initial stack. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+
+/* Constants required to setup the PIT. */
+#define port1MHz_IN_Hz 					( 1000000ul )
+#define port1SECOND_IN_uS				( 1000000.0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
+
+
+#define portINT_LEVEL_SENSITIVE  0
+#define portPIT_ENABLE      	( ( uint16_t ) 0x1 << 24 )
+#define portPIT_INT_ENABLE     	( ( uint16_t ) 0x1 << 25 )
+/*-----------------------------------------------------------*/
+
+/* Setup the PIT to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* The PIT interrupt handler - the RTOS tick. */
+static void vPortTickISR( void );
+
+/* ulCriticalNesting will get set to zero when the first task starts.  It
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
+uint32_t ulCriticalNesting = ( uint32_t ) 9999;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The status register is set for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+	
+	#ifdef THUMB_INTERWORK
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+	#endif
+	
+	pxTopOfStack--;
+
+	/* Interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+
+	return pxTopOfStack;	
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+static __arm void vPortTickISR( void )
+{
+volatile uint32_t ulDummy;
+	
+	/* Increment the tick count - which may wake some tasks but as the
+	preemptive scheduler is not being used any woken task is not given
+	processor time no matter what its priority. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		vTaskSwitchContext();
+	}
+		
+	/* Clear the PIT interrupt. */
+	ulDummy = AT91C_BASE_PITC->PITC_PIVR;
+	
+	/* To remove compiler warning. */
+	( void ) ulDummy;
+	
+	/* The AIC is cleared in the asm wrapper, outside of this function. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+const uint32_t ulPeriodIn_uS = ( 1.0 / ( double ) configTICK_RATE_HZ ) * port1SECOND_IN_uS;
+
+	/* Setup the PIT for the required frequency. */
+	PIT_Init( ulPeriodIn_uS, BOARD_MCK / port1MHz_IN_Hz );
+	
+	/* Setup the PIT interrupt. */
+	AIC_DisableIT( AT91C_ID_SYS );
+	AIC_ConfigureIT( AT91C_ID_SYS, AT91C_AIC_PRIOR_LOWEST, vPortTickISR );
+	AIC_EnableIT( AT91C_ID_SYS );
+	PIT_EnableIT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts first! */
+	__disable_irq();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			__enable_irq();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portasm.s79 b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portasm.s79
new file mode 100644
index 0000000..d5ac7eb
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portasm.s79
@@ -0,0 +1,34 @@
+		RSEG ICODE:CODE
+		CODE32
+
+	EXTERN vTaskSwitchContext
+
+	PUBLIC vPortYieldProcessor
+	PUBLIC vPortStartFirstTask
+
+#include "ISR_Support.h"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Starting the first task is just a matter of restoring the context that
+; was created by pxPortInitialiseStack().
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Manual context switch function.  This is the SWI hander.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortYieldProcessor:
+	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
+								; as if the context was saved during and IRQ
+								; handler.
+								
+	portSAVE_CONTEXT			; Save the context of the current task...
+	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
+	mov     lr, pc
+	BX R0
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+
+
+	END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portmacro.h
new file mode 100644
index 0000000..e9d62cd
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portmacro.h
@@ -0,0 +1,114 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include <intrinsics.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portYIELD()					asm ( "SWI 0" )
+#define portNOP()					asm ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+__arm __interwork void vPortDisableInterruptsFromThumb( void );
+__arm __interwork void vPortEnableInterruptsFromThumb( void );
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()	__disable_irq()
+#define portENABLE_INTERRUPTS()		__enable_irq()
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
+{													\
+extern void vTaskSwitchContext( void );				\
+													\
+	if( xSwitchRequired ) 							\
+	{												\
+		vTaskSwitchContext();						\
+	}												\
+}
+/*-----------------------------------------------------------*/
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/LPC2000/ISR_Support.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/LPC2000/ISR_Support.h
new file mode 100644
index 0000000..f16c592
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/LPC2000/ISR_Support.h
@@ -0,0 +1,105 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	EXTERN pxCurrentTCB
+	EXTERN ulCriticalNesting
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+portSAVE_CONTEXT MACRO
+
+	; Push R0 as we are going to use the register.
+	STMDB	SP!, {R0}
+
+	; Set R0 to point to the task stack pointer.
+	STMDB	SP, {SP}^
+	NOP
+	SUB		SP, SP, #4
+	LDMIA	SP!, {R0}
+
+	; Push the return address onto the stack.
+	STMDB	R0!, {LR}
+
+	; Now we have saved LR we can use it instead of R0.
+	MOV		LR, R0
+
+	; Pop R0 so we can save it onto the system mode stack.
+	LDMIA	SP!, {R0}
+
+	; Push all the system mode registers onto the task stack.
+	STMDB	LR, {R0-LR}^
+	NOP
+	SUB		LR, LR, #60
+
+	; Push the SPSR onto the task stack.
+	MRS		R0, SPSR
+	STMDB	LR!, {R0}
+
+	LDR		R0, =ulCriticalNesting
+	LDR		R0, [R0]
+	STMDB	LR!, {R0}
+
+	; Store the new top of stack for the task.
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	STR		LR, [R0]
+
+	ENDM
+
+
+portRESTORE_CONTEXT MACRO
+
+	; Set the LR to the task stack.
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	LDR		LR, [R0]
+
+	; The critical nesting depth is the first item on the stack.
+	; Load it into the ulCriticalNesting variable.
+	LDR		R0, =ulCriticalNesting
+	LDMFD	LR!, {R1}
+	STR		R1, [R0]
+
+	; Get the SPSR from the stack.
+	LDMFD	LR!, {R0}
+	MSR		SPSR_cxsf, R0
+
+	; Restore all system mode registers for the task.
+	LDMFD	LR, {R0-R14}^
+	NOP
+
+	; Restore the return address.
+	LDR		LR, [LR, #+60]
+
+	; And return - correcting the offset in the LR to obtain the
+	; correct address.
+	SUBS	PC, LR, #4
+
+	ENDM
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/LPC2000/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/LPC2000/port.c
new file mode 100644
index 0000000..0be2c0b
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/LPC2000/port.c
@@ -0,0 +1,317 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Philips ARM7 port.
+ *----------------------------------------------------------*/
+
+/*
+	Changes from V3.2.2
+
+	+ Bug fix - The prescale value for the timer setup is now written to T0PR
+	  instead of T0PC.  This bug would have had no effect unless a prescale
+	  value was actually used.
+*/
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <intrinsics.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the tick ISR. */
+#define portENABLE_TIMER			( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE			0x00
+#define portINTERRUPT_ON_MATCH		( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH	( ( uint32_t ) 0x02 )
+
+/* Constants required to setup the initial stack. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+
+/* Constants required to setup the PIT. */
+#define portPIT_CLOCK_DIVISOR			( ( uint32_t ) 16 )
+#define portPIT_COUNTER_VALUE			( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
+
+/* Constants required to handle interrupts. */
+#define portTIMER_MATCH_ISR_BIT		( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT		( ( uint32_t ) 0 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
+
+
+#define portINT_LEVEL_SENSITIVE  0
+#define portPIT_ENABLE      	( ( uint16_t ) 0x1 << 24 )
+#define portPIT_INT_ENABLE     	( ( uint16_t ) 0x1 << 25 )
+
+/* Constants required to setup the VIC for the tick ISR. */
+#define portTIMER_VIC_CHANNEL		( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT	( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE		( ( uint32_t ) 0x0020 )
+
+/*-----------------------------------------------------------*/
+
+/* Setup the PIT to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* ulCriticalNesting will get set to zero when the first task starts.  It
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
+uint32_t ulCriticalNesting = ( uint32_t ) 9999;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The status register is set for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+	
+	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+	
+	pxTopOfStack--;
+
+	/* Interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+
+	return pxTopOfStack;	
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 0
+
+	/* The cooperative scheduler requires a normal IRQ service routine to
+	simply increment the system tick. */
+	static __arm __irq void vPortNonPreemptiveTick( void );
+	static __arm __irq void vPortNonPreemptiveTick( void )
+	{
+		/* Increment the tick count - which may wake some tasks but as the
+		preemptive scheduler is not being used any woken task is not given
+		processor time no matter what its priority. */
+		xTaskIncrementTick();
+		
+		/* Ready for the next interrupt. */
+		T0IR = portTIMER_MATCH_ISR_BIT;
+		VICVectAddr = portCLEAR_VIC_INTERRUPT;
+	}
+
+#else
+
+	/* This function is called from an asm wrapper, so does not require the __irq
+	keyword. */
+	void vPortPreemptiveTick( void );
+	void vPortPreemptiveTick( void )
+	{
+		/* Increment the tick counter. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{	
+			/* The new tick value might unblock a task.  Ensure the highest task that
+			is ready to execute is the task that will execute when the tick ISR
+			exits. */
+			vTaskSwitchContext();
+		}
+	
+		/* Ready for the next interrupt. */
+		T0IR = portTIMER_MATCH_ISR_BIT;
+		VICVectAddr = portCLEAR_VIC_INTERRUPT;
+	}
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+
+	/* A 1ms tick does not require the use of the timer prescale.  This is
+	defaulted to zero but can be used if necessary. */
+	T0PR = portPRESCALE_VALUE;
+
+	/* Calculate the match value required for our wanted tick rate. */
+	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+	/* Protect against divide by zero.  Using an if() statement still results
+	in a warning - hence the #if. */
+	#if portPRESCALE_VALUE != 0
+	{
+		ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
+	}
+	#endif
+
+	T0MR0 = ulCompareMatch;
+
+	/* Generate tick with timer 0 compare match. */
+	T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
+
+	/* Setup the VIC for the timer. */
+	VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
+	VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
+	
+	/* The ISR installed depends on whether the preemptive or cooperative
+	scheduler is being used. */
+	#if configUSE_PREEMPTION == 1
+	{	
+		extern void ( vPortPreemptiveTickEntry )( void );
+
+		VICVectAddr0 = ( uint32_t ) vPortPreemptiveTickEntry;
+	}
+	#else
+	{
+		extern void ( vNonPreemptiveTick )( void );
+
+		VICVectAddr0 = ( int32_t ) vPortNonPreemptiveTick;
+	}
+	#endif
+
+	VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
+
+	/* Start the timer - interrupts are disabled when this function is called
+	so it is okay to do this here. */
+	T0TCR = portENABLE_TIMER;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts first! */
+	__disable_interrupt();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			__enable_interrupt();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/LPC2000/portasm.s79 b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/LPC2000/portasm.s79
new file mode 100644
index 0000000..f25a57c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/LPC2000/portasm.s79
@@ -0,0 +1,76 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+		RSEG ICODE:CODE
+		CODE32
+
+	EXTERN vTaskSwitchContext
+	EXTERN vPortPreemptiveTick
+
+	PUBLIC vPortPreemptiveTickEntry
+	PUBLIC vPortYieldProcessor
+	PUBLIC vPortStartFirstTask
+
+#include "FreeRTOSConfig.h"
+#include "ISR_Support.h"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Starting the first task is just a matter of restoring the context that
+; was created by pxPortInitialiseStack().
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Manual context switch function.  This is the SWI hander.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortYieldProcessor:
+	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
+								; as if the context was saved during and IRQ
+								; handler.
+
+	portSAVE_CONTEXT			; Save the context of the current task...
+	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
+	mov     lr, pc
+	BX R0
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Preemptive context switch function.  This will only ever get installed if
+; portUSE_PREEMPTION is set to 1 in portmacro.h.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortPreemptiveTickEntry:
+#if configUSE_PREEMPTION == 1
+	portSAVE_CONTEXT			; Save the context of the current task...
+	LDR R0, =vPortPreemptiveTick; before selecting the next task to execute.
+	mov     lr, pc
+	BX R0
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+#endif
+
+	END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/LPC2000/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/LPC2000/portmacro.h
new file mode 100644
index 0000000..d386903
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/LPC2000/portmacro.h
@@ -0,0 +1,113 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include <intrinsics.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portYIELD()					asm ( "SWI 0" )
+#define portNOP()					asm ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+__arm __interwork void vPortDisableInterruptsFromThumb( void );
+__arm __interwork void vPortEnableInterruptsFromThumb( void );
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()	__disable_interrupt()
+#define portENABLE_INTERRUPTS()		__enable_interrupt()
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
+{													\
+extern void vTaskSwitchContext( void );				\
+													\
+	if( xSwitchRequired ) 							\
+	{												\
+		vTaskSwitchContext();						\
+	}												\
+}
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430/port.c
new file mode 100644
index 0000000..3c8cfc3
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430/port.c
@@ -0,0 +1,173 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MSP430 port.
+ *----------------------------------------------------------*/
+
+/* Constants required for hardware setup.  The tick ISR runs off the ACLK,
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ			( ( TickType_t ) 32768 )
+#define portINITIAL_CRITICAL_NESTING	( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED			( ( StackType_t ) 0x08 )
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Each task maintains a count of the critical section nesting depth.  Each
+time a critical section is entered the count is incremented.  Each time a
+critical section is exited the count is decremented - with interrupts only
+being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+void vPortSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/*
+		Place a few bytes of known values on the bottom of the stack.
+		This is just useful for debugging and can be included if required.
+
+		*pxTopOfStack = ( StackType_t ) 0x1111;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x2222;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x3333;
+		pxTopOfStack--;
+	*/
+
+	/* The msp430 automatically pushes the PC then SR onto the stack before
+	executing an ISR.  We want the stack to look just as if this has happened
+	so place a pointer to the start of the task on the stack first - followed
+	by the flags we want the task to use when it starts up. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+	*pxTopOfStack = portFLAGS_INT_ENABLED;
+	pxTopOfStack--;
+
+	/* Next the general purpose registers. */
+	*pxTopOfStack = ( StackType_t ) 0x4444;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x5555;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x6666;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x7777;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x8888;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x9999;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xaaaa;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xbbbb;
+	pxTopOfStack--;	
+	
+	/* When the task starts is will expect to find the function parameter in
+	R15. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+	
+	*pxTopOfStack = ( StackType_t ) 0xdddd;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xeeee;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xffff;
+	pxTopOfStack--;
+
+	/* A variable is used to keep track of the critical section nesting.
+	This variable has to be stored as part of the task context and is
+	initially set to zero. */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the MSP430 port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.  This uses timer 0
+ * but could alternatively use the watchdog timer or timer 1.
+ */
+void vPortSetupTimerInterrupt( void )
+{
+	/* Ensure the timer is stopped. */
+	TACTL = 0;
+
+	/* Run the timer of the ACLK. */
+	TACTL = TASSEL_1;
+
+	/* Clear everything to start with. */
+	TACTL |= TACLR;
+
+	/* Set the compare match value according to the tick rate we want. */
+	TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
+
+	/* Enable the interrupts. */
+	TACCTL0 = CCIE;
+
+	/* Start up clean. */
+	TACTL |= TACLR;
+
+	/* Up mode. */
+	TACTL |= MC_1;
+}
+/*-----------------------------------------------------------*/
+
+
+	
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430/portasm.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430/portasm.h
new file mode 100644
index 0000000..4e726d3
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430/portasm.h
@@ -0,0 +1,84 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTASM_H
+#define PORTASM_H
+
+portSAVE_CONTEXT macro
+
+		IMPORT pxCurrentTCB
+		IMPORT usCriticalNesting
+
+		/* Save the remaining registers. */
+		push	r4
+		push	r5
+		push	r6
+		push	r7
+		push	r8
+		push	r9
+		push	r10
+		push	r11
+		push	r12
+		push	r13
+		push	r14
+		push	r15
+		mov.w	&usCriticalNesting, r14
+		push	r14
+		mov.w	&pxCurrentTCB, r12
+		mov.w	r1, 0(r12)
+		endm
+/*-----------------------------------------------------------*/
+		
+portRESTORE_CONTEXT macro
+		mov.w	&pxCurrentTCB, r12
+		mov.w	@r12, r1
+		pop		r15
+		mov.w	r15, &usCriticalNesting
+		pop		r15
+		pop		r14
+		pop		r13
+		pop		r12
+		pop		r11
+		pop		r10
+		pop		r9
+		pop		r8
+		pop		r7
+		pop		r6
+		pop		r5
+		pop		r4
+
+		/* The last thing on the stack will be the status register.
+        Ensure the power down bits are clear ready for the next
+        time this power down register is popped from the stack. */
+		bic.w   #0xf0,0(SP)
+
+		reti
+		endm
+/*-----------------------------------------------------------*/
+
+#endif
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430/portext.s43 b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430/portext.s43
new file mode 100644
index 0000000..ee747f3
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430/portext.s43
@@ -0,0 +1,106 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+#include "FreeRTOSConfig.h"
+#include "portasm.h"
+
+	IMPORT xTaskIncrementTick
+	IMPORT vTaskSwitchContext
+	IMPORT vPortSetupTimerInterrupt
+
+	EXPORT vTickISR
+	EXPORT vPortYield
+	EXPORT xPortStartScheduler
+
+	RSEG CODE
+
+/*
+ * The RTOS tick ISR.
+ *
+ * If the cooperative scheduler is in use this simply increments the tick
+ * count.
+ *
+ * If the preemptive scheduler is in use a context switch can also occur.
+ */
+vTickISR:
+	portSAVE_CONTEXT
+
+	call	#xTaskIncrementTick
+	cmp.w	#0x0, R12
+    jeq		SkipContextSwitch
+	call	#vTaskSwitchContext
+SkipContextSwitch:
+
+	portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Manual context switch called by the portYIELD() macro.
+ */
+vPortYield:
+
+	/* Mimic an interrupt by pushing the SR. */
+	push	SR
+
+	/* Now the SR is stacked we can disable interrupts. */
+	dint
+
+	/* Save the context of the current task. */
+	portSAVE_CONTEXT
+
+	/* Switch to the highest priority task that is ready to run. */
+	call	#vTaskSwitchContext
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Start off the scheduler by initialising the RTOS tick timer, then restoring
+ * the context of the first task.
+ */
+xPortStartScheduler:
+
+	/* Setup the hardware to generate the tick.  Interrupts are disabled
+	when this function is called. */
+	call	#vPortSetupTimerInterrupt
+
+	/* Restore the context of the first task that is going to run. */
+	portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+
+	/* Install vTickISR as the timer A0 interrupt. */
+	ASEG
+	ORG 0xFFE0 + TIMERA0_VECTOR
+
+	_vTickISR_: DC16 vTickISR
+
+
+	END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430/portmacro.h
new file mode 100644
index 0000000..f68d271
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430/portmacro.h
@@ -0,0 +1,133 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS()	_DINT(); _NOP()
+#define portENABLE_INTERRUPTS()		_EINT(); _NOP()
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
+
+#define portENTER_CRITICAL()													\
+{																				\
+extern volatile uint16_t usCriticalNesting;							\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	/* Now interrupts are disabled usCriticalNesting can be accessed */			\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
+	/* times portENTER_CRITICAL() has been called. */							\
+	usCriticalNesting++;														\
+}
+
+#define portEXIT_CRITICAL()														\
+{																				\
+extern volatile uint16_t usCriticalNesting;							\
+																				\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
+	{																			\
+		/* Decrement the nesting count as we are leaving a critical section. */	\
+		usCriticalNesting--;													\
+																				\
+		/* If the nesting level has reached zero then interrupts should be */	\
+		/* re-enabled. */														\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
+		{																		\
+			portENABLE_INTERRUPTS();											\
+		}																		\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+extern void vPortYield( void );
+#define portYIELD() vPortYield()
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			2
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()
+#define portPOINTER_SIZE_TYPE		uint16_t
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#if configINTERRUPT_EXAMPLE_METHOD == 2
+
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR( x ) if( x ) vTaskSwitchContext()
+
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430X/data_model.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430X/data_model.h
new file mode 100644
index 0000000..89d871d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430X/data_model.h
@@ -0,0 +1,63 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef DATA_MODEL_H
+#define DATA_MODEL_H
+
+#if __DATA_MODEL__ == __DATA_MODEL_SMALL__
+	#define pushm_x pushm.w
+	#define popm_x popm.w
+	#define push_x push.w
+	#define pop_x pop.w
+	#define mov_x mov.w
+	#define cmp_x cmp.w
+#endif
+
+#if __DATA_MODEL__ == __DATA_MODEL_MEDIUM__
+	#define pushm_x pushm.a
+	#define popm_x popm.a
+	#define push_x pushx.a
+	#define pop_x popx.a
+	#define mov_x mov.w
+	#define cmp_x cmp.w
+#endif
+
+#if __DATA_MODEL__ == __DATA_MODEL_LARGE__
+	#define pushm_x pushm.a
+	#define popm_x popm.a
+	#define push_x pushx.a
+	#define pop_x popx.a
+	#define mov_x movx.a
+	#define cmp_x cmpx.a
+#endif
+
+#ifndef pushm_x
+	#error The assembler options must define one of the following symbols: __DATA_MODEL_SMALL__, __DATA_MODEL_MEDIUM__, or __DATA_MODEL_LARGE__
+#endif
+
+#endif /* DATA_MODEL_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430X/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430X/port.c
new file mode 100644
index 0000000..a6feab8
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430X/port.c
@@ -0,0 +1,182 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MSP430X port.
+ *----------------------------------------------------------*/
+
+/* Constants required for hardware setup.  The tick ISR runs off the ACLK,
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ			( ( TickType_t ) 32768 )
+#define portINITIAL_CRITICAL_NESTING	( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED			( ( StackType_t ) 0x08 )
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Each task maintains a count of the critical section nesting depth.  Each
+time a critical section is entered the count is incremented.  Each time a
+critical section is exited the count is decremented - with interrupts only
+being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+void vPortSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint16_t *pusTopOfStack;
+uint32_t *pulTopOfStack;
+
+	/*
+		Place a few bytes of known values on the bottom of the stack.
+		This is just useful for debugging and can be included if required.
+	
+		*pxTopOfStack = ( StackType_t ) 0x1111;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x2222;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x3333;
+	*/
+
+	/* StackType_t is either 16 bits or 32 bits depending on the data model.
+	Some stacked items do not change size depending on the data model so have
+	to be explicitly cast to the correct size so this function will work
+	whichever data model is being used. */
+	if( sizeof( StackType_t ) == sizeof( uint16_t ) )
+	{
+		/* Make room for a 20 bit value stored as a 32 bit value. */
+		pusTopOfStack = ( uint16_t * ) pxTopOfStack;
+		pusTopOfStack--;
+		pulTopOfStack = ( uint32_t * ) pusTopOfStack;
+	}
+	else
+	{
+		pulTopOfStack = ( uint32_t * ) pxTopOfStack;
+	}
+	*pulTopOfStack = ( uint32_t ) pxCode;
+	
+	pusTopOfStack = ( uint16_t * ) pulTopOfStack;
+	pusTopOfStack--;
+	*pusTopOfStack = portFLAGS_INT_ENABLED;
+	pusTopOfStack -= ( sizeof( StackType_t ) / 2 );
+	
+	/* From here on the size of stacked items depends on the memory model. */
+	pxTopOfStack = ( StackType_t * ) pusTopOfStack;
+
+	/* Next the general purpose registers. */
+	#ifdef PRELOAD_REGISTER_VALUES
+		*pxTopOfStack = ( StackType_t ) 0xffff;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xeeee;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xdddd;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) pvParameters;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0xaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x9999;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x8888;
+		pxTopOfStack--;	
+		*pxTopOfStack = ( StackType_t ) 0x5555;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x6666;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x5555;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x4444;
+		pxTopOfStack--;
+	#else
+		pxTopOfStack -= 3;
+		*pxTopOfStack = ( StackType_t ) pvParameters;
+		pxTopOfStack -= 9;
+	#endif
+
+
+	/* A variable is used to keep track of the critical section nesting.
+	This variable has to be stored as part of the task context and is
+	initially set to zero. */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the MSP430 port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.
+ */
+void vPortSetupTimerInterrupt( void )
+{
+	vApplicationSetupTimerInterrupt();
+}
+/*-----------------------------------------------------------*/
+
+#pragma vector=configTICK_VECTOR
+__interrupt __raw void vTickISREntry( void )
+{
+extern void vPortTickISR( void );
+
+	__bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );
+	vPortTickISR();
+}
+
+	
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430X/portext.s43 b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430X/portext.s43
new file mode 100644
index 0000000..a1eede9
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430X/portext.s43
@@ -0,0 +1,138 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+#include "msp430.h"
+#include "FreeRTOSConfig.h"
+#include "data_model.h"
+
+	IMPORT xTaskIncrementTick
+	IMPORT vTaskSwitchContext
+	IMPORT vPortSetupTimerInterrupt
+	IMPORT pxCurrentTCB
+	IMPORT usCriticalNesting
+
+	EXPORT vPortTickISR
+	EXPORT vPortYield
+	EXPORT xPortStartScheduler
+
+portSAVE_CONTEXT macro
+
+	/* Save the remaining registers. */
+	pushm_x	#12, r15
+	mov.w	&usCriticalNesting, r14
+	push_x r14
+	mov_x	&pxCurrentTCB, r12
+	mov_x	sp, 0( r12 )
+	endm
+/*-----------------------------------------------------------*/
+
+portRESTORE_CONTEXT macro
+
+	mov_x	&pxCurrentTCB, r12
+	mov_x	@r12, sp
+	pop_x	r15
+	mov.w	r15, &usCriticalNesting
+	popm_x	#12, r15
+	nop
+	pop.w	sr
+	nop
+	reta
+	endm
+/*-----------------------------------------------------------*/
+
+
+/*
+ * The RTOS tick ISR.
+ *
+ * If the cooperative scheduler is in use this simply increments the tick
+ * count.
+ *
+ * If the preemptive scheduler is in use a context switch can also occur.
+ */
+
+	RSEG CODE
+	EVEN
+
+vPortTickISR:
+
+	/* The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs
+	to save it manually before it gets modified (interrupts get disabled).
+	Entering through this interrupt means the SR is already on the stack, but
+	this keeps the stack frames identical. */
+	push.w sr
+	portSAVE_CONTEXT
+
+	calla	#xTaskIncrementTick
+	cmp.w   #0x0, R12
+    jeq     SkipContextSwitch
+    calla   #vTaskSwitchContext
+SkipContextSwitch:
+	portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch called by the portYIELD() macro.
+ */
+ 	EVEN
+
+vPortYield:
+
+	/* The sr needs saving before it is modified. */
+	push.w	sr
+
+	/* Now the SR is stacked interrupts can be disabled. */
+	dint
+	nop
+
+	/* Save the context of the current task. */
+	portSAVE_CONTEXT
+
+	/* Select the next task to run. */
+	calla	#vTaskSwitchContext
+
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Start off the scheduler by initialising the RTOS tick timer, then restoring
+ * the context of the first task.
+ */
+ 	EVEN
+
+xPortStartScheduler:
+
+	/* Setup the hardware to generate the tick.  Interrupts are disabled
+	when this function is called. */
+	calla	#vPortSetupTimerInterrupt
+
+	/* Restore the context of the first task that is going to run. */
+	portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+	END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430X/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430X/portmacro.h
new file mode 100644
index 0000000..30bfeef
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/MSP430X/portmacro.h
@@ -0,0 +1,142 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Hardware includes. */
+#include "msp430.h"
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portBASE_TYPE	short
+
+/* The stack type changes depending on the data model. */
+#if( __DATA_MODEL__ == __DATA_MODEL_SMALL__ )
+	#define portSTACK_TYPE uint16_t
+	#define portPOINTER_SIZE_TYPE uint16_t
+#else
+	#define portSTACK_TYPE uint32_t
+#endif
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS()	_DINT(); _NOP()
+#define portENABLE_INTERRUPTS()		_EINT(); _NOP()
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
+
+#define portENTER_CRITICAL()													\
+{																				\
+extern volatile uint16_t usCriticalNesting;										\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	/* Now interrupts are disabled usCriticalNesting can be accessed */			\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
+	/* times portENTER_CRITICAL() has been called. */							\
+	usCriticalNesting++;														\
+}
+
+#define portEXIT_CRITICAL()														\
+{																				\
+extern volatile uint16_t usCriticalNesting;										\
+																				\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
+	{																			\
+		/* Decrement the nesting count as we are leaving a critical section. */	\
+		usCriticalNesting--;													\
+																				\
+		/* If the nesting level has reached zero then interrupts should be */	\
+		/* re-enabled. */														\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
+		{																		\
+			portENABLE_INTERRUPTS();											\
+		}																		\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+extern void vPortYield( void );
+#define portYIELD() vPortYield()
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			2
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					__no_operation()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#define portYIELD_FROM_ISR( x ) if( x ) vPortYield()
+
+void vApplicationSetupTimerInterrupt( void );
+
+/* sizeof( int ) != sizeof( long ) so a full printf() library is required if
+run time stats information is to be displayed. */
+#define portLU_PRINTF_SPECIFIER_REQUIRED
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/Documentation.url b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/Documentation.url
new file mode 100644
index 0000000..c7819d5
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/Documentation.url
@@ -0,0 +1,5 @@
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,11
+[InternetShortcut]
+IDList=
+URL=https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
new file mode 100644
index 0000000..37edd6a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -0,0 +1,68 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
+ * compiler's!) include path.  For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
+
+
+#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
+#define __FREERTOS_RISC_V_EXTENSIONS_H__
+
+#define portasmHAS_SIFIVE_CLINT 1
+#define portasmHAS_MTIME 1
+#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
+
+portasmSAVE_ADDITIONAL_REGISTERS MACRO
+	/* No additional registers to save, so this macro does nothing. */
+	ENDM
+
+portasmRESTORE_ADDITIONAL_REGISTERS MACRO
+	/* No additional registers to restore, so this macro does nothing. */
+	ENDM
+
+#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/chip_specific_extensions/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/chip_specific_extensions/readme.txt
new file mode 100644
index 0000000..69d98d9
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/chip_specific_extensions/readme.txt
@@ -0,0 +1,23 @@
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
+ * compiler's!) include path.  For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/port.c
new file mode 100644
index 0000000..e4123df
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/port.c
@@ -0,0 +1,212 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the RISC-V RV32 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portmacro.h"
+
+/* Standard includes. */
+#include "string.h"
+
+#ifdef configCLINT_BASE_ADDRESS
+	#warning The configCLINT_BASE_ADDRESS constant has been deprecated.  configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS are currently being derived from the (possibly 0) configCLINT_BASE_ADDRESS setting.  Please update to define configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS dirctly in place of configCLINT_BASE_ADDRESS.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+#ifndef configMTIME_BASE_ADDRESS
+	#warning configMTIME_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  If the target chip includes a memory-mapped mtime register then set configMTIME_BASE_ADDRESS to the mapped address.  Otherwise set configMTIME_BASE_ADDRESS to 0.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+#ifndef configMTIMECMP_BASE_ADDRESS
+	#warning configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  If the target chip includes a memory-mapped mtimecmp register then set configMTIMECMP_BASE_ADDRESS to the mapped address.  Otherwise set configMTIMECMP_BASE_ADDRESS to 0.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/* The stack used by interrupt service routines.  Set configISR_STACK_SIZE_WORDS
+to use a statically allocated array as the interrupt stack.  Alternative leave
+configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
+linker variable names __freertos_irq_stack_top has the same value as the top
+of the stack used by main.  Using the linker script method will repurpose the
+stack that was used by main before the scheduler was started for use as the
+interrupt stack after the scheduler has started. */
+#ifdef configISR_STACK_SIZE_WORDS
+	static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
+	const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ] );
+
+	/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
+	the task stacks, and so will legitimately appear in many positions within
+	the ISR stack. */
+	#define portISR_STACK_FILL_BYTE	0xee
+#else
+	extern const uint32_t __freertos_irq_stack_top[];
+	const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
+#endif
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void ) __attribute__(( weak ));
+
+/*-----------------------------------------------------------*/
+
+/* Used to program the machine timer compare register. */
+uint64_t ullNextTime = 0ULL;
+const uint64_t *pullNextTime = &ullNextTime;
+const size_t uxTimerIncrementsForOneTick = ( size_t ) ( ( configCPU_CLOCK_HZ ) / ( configTICK_RATE_HZ ) ); /* Assumes increment won't go over 32-bits. */
+uint32_t const ullMachineTimerCompareRegisterBase = configMTIMECMP_BASE_ADDRESS;
+volatile uint64_t * pullMachineTimerCompareRegister = NULL;
+
+/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
+stack checking.  A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
+#if defined( configISR_STACK_SIZE_WORDS ) && ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+	#warning This path not tested, or even compiled yet.
+
+	static const uint8_t ucExpectedStackBytes[] = {
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };	\
+
+	#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
+	/* Define the function away. */
+	#define portCHECK_ISR_STACK()
+#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+/*-----------------------------------------------------------*/
+
+#if( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 )
+
+	void vPortSetupTimerInterrupt( void )
+	{
+	uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
+	volatile uint32_t * const pulTimeHigh = ( uint32_t * ) ( ( configMTIME_BASE_ADDRESS ) + 4UL ); /* 8-byte typer so high 32-bit word is 4 bytes up. */
+	volatile uint32_t * const pulTimeLow = ( uint32_t * ) ( configMTIME_BASE_ADDRESS );
+	volatile uint32_t ulHartId;
+
+		__asm volatile( "csrr %0, 0xf14" : "=r"( ulHartId ) ); /* 0xf14 is hartid. */
+		pullMachineTimerCompareRegister  = ( volatile uint64_t * ) ( ullMachineTimerCompareRegisterBase + ( ulHartId * sizeof( uint64_t ) ) );
+
+		do
+		{
+			ulCurrentTimeHigh = *pulTimeHigh;
+			ulCurrentTimeLow = *pulTimeLow;
+		} while( ulCurrentTimeHigh != *pulTimeHigh );
+
+		ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
+		ullNextTime <<= 32ULL; /* High 4-byte word is 32-bits up. */
+		ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
+		ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
+		*pullMachineTimerCompareRegister = ullNextTime;
+
+		/* Prepare the time to use after the next tick interrupt. */
+		ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
+	}
+
+#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIME_BASE_ADDRESS != 0 ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void xPortStartFirstTask( void );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t mtvec = 0;
+
+		/* Check the least significant two bits of mtvec are 00 - indicating
+		single vector mode. */
+		__asm volatile( "csrr %0, 0x305" : "=r"( mtvec ) ); /* 0x305 is mtvec. */
+		configASSERT( ( mtvec & 0x03UL ) == 0 );
+
+		/* Check alignment of the interrupt stack - which is the same as the
+		stack that was being used by main() prior to the scheduler being
+		started. */
+		configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+		#ifdef configISR_STACK_SIZE_WORDS
+		{
+			memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
+		}
+		#endif	 /* configISR_STACK_SIZE_WORDS */
+	}
+	#endif /* configASSERT_DEFINED */
+
+	/* If there is a CLINT then it is ok to use the default implementation
+	in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
+	configure whichever clock is to be used to generate the tick interrupt. */
+	vPortSetupTimerInterrupt();
+
+	#if( ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) )
+	{
+		/* Enable mtime and external interrupts.  1<<7 for timer interrupt, 1<<11
+		for external interrupt.  _RB_ What happens here when mtime is not present as
+		with pulpino? */
+		__asm volatile( "csrs 0x304, %0" :: "r"(0x880) ); /* 0x304 is mie. */
+	}
+	#else
+	{
+		/* Enable external interrupts. */
+		__asm volatile( "csrs 0x304, %0" :: "r"(0x800) ); /* 304 is mie. */
+	}
+	#endif /* ( configMTIME_BASE_ADDRESS != 0 ) && ( configMTIMECMP_BASE_ADDRESS != 0 ) */
+
+	xPortStartFirstTask();
+
+	/* Should not get here as after calling xPortStartFirstTask() only tasks
+	should be executing. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented. */
+	for( ;; );
+}
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/portASM.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/portASM.s
new file mode 100644
index 0000000..b2beaae
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/portASM.s
@@ -0,0 +1,447 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
+ *
+ * + The code that is common to all RISC-V chips is implemented in
+ *   FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S.  There is only one
+ *   portASM.S file because the same file is used no matter which RISC-V chip is
+ *   in use.
+ *
+ * + The code that tailors the kernel's RISC-V port to a specific RISC-V
+ *   chip is implemented in freertos_risc_v_chip_specific_extensions.h.  There
+ *   is one freertos_risc_v_chip_specific_extensions.h that can be used with any
+ *   RISC-V chip that both includes a standard CLINT and does not add to the
+ *   base set of RISC-V registers.  There are additional
+ *   freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
+ *   that do not include a standard CLINT or do add to the base set of RISC-V
+ *   registers.
+ *
+ * CARE MUST BE TAKEN TO INCLDUE THE CORRECT
+ * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
+ * IN USE.  To include the correct freertos_risc_v_chip_specific_extensions.h
+ * header file ensure the path to the correct header file is in the assembler's
+ * include path.
+ *
+ * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
+ * that include a standard CLINT and do not add to the base set of RISC-V
+ * registers.
+ *
+ */
+#if __riscv_xlen == 64
+	#define portWORD_SIZE 8
+	#define store_x sd
+	#define load_x ld
+#elif __riscv_xlen == 32
+	#define store_x sw
+	#define load_x lw
+	#define portWORD_SIZE 4
+#else
+	#error Assembler did not define __riscv_xlen
+#endif
+
+#include "freertos_risc_v_chip_specific_extensions.h"
+
+/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
+definitions. */
+#if defined( portasmHAS_CLINT ) && defined( portasmHAS_MTIME )
+	#error The portasmHAS_CLINT constant has been deprecated.  Please replace it with portasmHAS_MTIME.  portasmHAS_CLINT and portasmHAS_MTIME cannot both be defined at once.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+#ifdef portasmHAS_CLINT
+	#warning The portasmHAS_CLINT constant has been deprecated.  Please replace it with portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT.  For now portasmHAS_MTIME and portasmHAS_SIFIVE_CLINT are derived from portasmHAS_CLINT.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+	#define portasmHAS_MTIME portasmHAS_CLINT
+	#define portasmHAS_SIFIVE_CLINT portasmHAS_CLINT
+#endif
+
+#ifndef portasmHAS_MTIME
+	#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_MTIME to either 1 (MTIME clock present) or 0 (MTIME clock not present).  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+#ifndef portasmHANDLE_INTERRUPT
+	#error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts.  portasmHANDLE_INTERRUPT can be defined on the assembler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file.  https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+
+#ifndef portasmHAS_SIFIVE_CLINT
+	#define portasmHAS_SIFIVE_CLINT 0
+#endif
+
+/* CSR definitions. */
+#define CSR_MSTATUS 		0x300
+#define CSR_MTVEC			0x305
+#define CSR_MEPC            0x341
+#define CSR_MCAUSE          0x342
+
+
+/* Only the standard core registers are stored by default.  Any additional
+registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
+portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
+specific version of freertos_risc_v_chip_specific_extensions.h.  See the notes
+at the top of this file. */
+#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
+
+	PUBLIC xPortStartFirstTask
+	PUBLIC freertos_risc_v_trap_handler
+	PUBLIC pxPortInitialiseStack
+	EXTERN pxCurrentTCB
+	EXTERN ulPortTrapHandler
+	EXTERN vTaskSwitchContext
+	EXTERN xTaskIncrementTick
+	EXTERN Timer_IRQHandler
+	EXTERN pullMachineTimerCompareRegister
+	EXTERN pullNextTime
+	EXTERN uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
+	EXTERN xISRStackTop
+	EXTERN portasmHANDLE_INTERRUPT
+
+/*-----------------------------------------------------------*/
+
+	SECTION `.text`:CODE:NOROOT(2)
+	CODE
+
+freertos_risc_v_trap_handler:
+	addi sp, sp, -portCONTEXT_SIZE
+	store_x x1, 1 * portWORD_SIZE( sp )
+	store_x x5, 2 * portWORD_SIZE( sp )
+	store_x x6, 3 * portWORD_SIZE( sp )
+	store_x x7, 4 * portWORD_SIZE( sp )
+	store_x x8, 5 * portWORD_SIZE( sp )
+	store_x x9, 6 * portWORD_SIZE( sp )
+	store_x x10, 7 * portWORD_SIZE( sp )
+	store_x x11, 8 * portWORD_SIZE( sp )
+	store_x x12, 9 * portWORD_SIZE( sp )
+	store_x x13, 10 * portWORD_SIZE( sp )
+	store_x x14, 11 * portWORD_SIZE( sp )
+	store_x x15, 12 * portWORD_SIZE( sp )
+	store_x x16, 13 * portWORD_SIZE( sp )
+	store_x x17, 14 * portWORD_SIZE( sp )
+	store_x x18, 15 * portWORD_SIZE( sp )
+	store_x x19, 16 * portWORD_SIZE( sp )
+	store_x x20, 17 * portWORD_SIZE( sp )
+	store_x x21, 18 * portWORD_SIZE( sp )
+	store_x x22, 19 * portWORD_SIZE( sp )
+	store_x x23, 20 * portWORD_SIZE( sp )
+	store_x x24, 21 * portWORD_SIZE( sp )
+	store_x x25, 22 * portWORD_SIZE( sp )
+	store_x x26, 23 * portWORD_SIZE( sp )
+	store_x x27, 24 * portWORD_SIZE( sp )
+	store_x x28, 25 * portWORD_SIZE( sp )
+	store_x x29, 26 * portWORD_SIZE( sp )
+	store_x x30, 27 * portWORD_SIZE( sp )
+	store_x x31, 28 * portWORD_SIZE( sp )
+
+	csrr t0, CSR_MSTATUS					/* Required for MPIE bit. */
+	store_x t0, 29 * portWORD_SIZE( sp )
+
+	portasmSAVE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
+
+	load_x  t0, pxCurrentTCB			/* Load pxCurrentTCB. */
+	store_x  sp, 0( t0 )				/* Write sp to first TCB member. */
+
+	csrr a0, CSR_MCAUSE
+	csrr a1, CSR_MEPC
+
+test_if_asynchronous:
+	srli a2, a0, __riscv_xlen - 1		/* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
+	beq a2, x0, handle_synchronous		/* Branch past interrupt handing if not asynchronous. */
+	store_x a1, 0( sp )					/* Asynch so save unmodified exception return address. */
+
+handle_asynchronous:
+
+#if( portasmHAS_MTIME != 0 )
+
+	test_if_mtimer:						/* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
+
+		addi t0, x0, 1
+
+		slli t0, t0, __riscv_xlen - 1   /* LSB is already set, shift into MSB.  Shift 31 on 32-bit or 63 on 64-bit cores. */
+		addi t1, t0, 7					/* 0x8000[]0007 == machine timer interrupt. */
+		bne a0, t1, test_if_external_interrupt
+
+		load_x t0, pullMachineTimerCompareRegister  /* Load address of compare register into t0. */
+		load_x t1, pullNextTime  		/* Load the address of ullNextTime into t1. */
+
+		#if( __riscv_xlen == 32 )
+
+			/* Update the 64-bit mtimer compare match value in two 32-bit writes. */
+			li t4, -1
+			lw t2, 0(t1)				/* Load the low word of ullNextTime into t2. */
+			lw t3, 4(t1)				/* Load the high word of ullNextTime into t3. */
+			sw t4, 0(t0)				/* Low word no smaller than old value to start with - will be overwritten below. */
+			sw t3, 4(t0)				/* Store high word of ullNextTime into compare register.  No smaller than new value. */
+			sw t2, 0(t0)				/* Store low word of ullNextTime into compare register. */
+			lw t0, uxTimerIncrementsForOneTick	/* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
+			add t4, t0, t2				/* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
+			sltu t5, t4, t2				/* See if the sum of low words overflowed (what about the zero case?). */
+			add t6, t3, t5				/* Add overflow to high word of ullNextTime. */
+			sw t4, 0(t1)				/* Store new low word of ullNextTime. */
+			sw t6, 4(t1)				/* Store new high word of ullNextTime. */
+
+		#endif /* __riscv_xlen == 32 */
+
+		#if( __riscv_xlen == 64 )
+
+			/* Update the 64-bit mtimer compare match value. */
+			ld t2, 0(t1)			 	/* Load ullNextTime into t2. */
+			sd t2, 0(t0)				/* Store ullNextTime into compare register. */
+			ld t0, uxTimerIncrementsForOneTick  /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
+			add t4, t0, t2				/* Add ullNextTime to the timer increments for one tick. */
+			sd t4, 0(t1)				/* Store ullNextTime. */
+
+		#endif /* __riscv_xlen == 64 */
+
+		load_x sp, xISRStackTop			/* Switch to ISR stack before function call. */
+		jal xTaskIncrementTick
+		beqz a0, processed_source		/* Don't switch context if incrementing tick didn't unblock a task. */
+		jal vTaskSwitchContext
+		j processed_source
+
+	test_if_external_interrupt:			/* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
+		addi t1, t1, 4					/* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
+		bne a0, t1, as_yet_unhandled	/* Something as yet unhandled. */
+
+#endif /* portasmHAS_MTIME */
+
+	load_x sp, xISRStackTop				/* Switch to ISR stack before function call. */
+	jal portasmHANDLE_INTERRUPT			/* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */
+	j processed_source
+
+handle_synchronous:
+	addi a1, a1, 4						/* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */
+	store_x a1, 0( sp )					/* Save updated exception return address. */
+
+test_if_environment_call:
+	li t0, 11 							/* 11 == environment call. */
+	bne a0, t0, is_exception			/* Not an M environment call, so some other exception. */
+	load_x sp, xISRStackTop				/* Switch to ISR stack before function call. */
+	jal vTaskSwitchContext
+	j processed_source
+
+is_exception:
+	csrr t0, CSR_MCAUSE					/* For viewing in the debugger only. */
+	csrr t1, CSR_MEPC					/* For viewing in the debugger only */
+	csrr t2, CSR_MSTATUS
+	j is_exception						/* No other exceptions handled yet. */
+
+as_yet_unhandled:
+	csrr t0, mcause						/* For viewing in the debugger only. */
+	j as_yet_unhandled
+
+processed_source:
+	load_x  t1, pxCurrentTCB			/* Load pxCurrentTCB. */
+	load_x  sp, 0( t1 )				 	/* Read sp from first TCB member. */
+
+	/* Load mret with the address of the next instruction in the task to run next. */
+	load_x t0, 0( sp )
+	csrw CSR_MEPC, t0
+
+	portasmRESTORE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
+
+	/* Load mstatus with the interrupt enable bits used by the task. */
+	load_x  t0, 29 * portWORD_SIZE( sp )
+	csrw CSR_MSTATUS, t0						/* Required for MPIE bit. */
+
+	load_x  x1, 1 * portWORD_SIZE( sp )
+	load_x  x5, 2 * portWORD_SIZE( sp )		/* t0 */
+	load_x  x6, 3 * portWORD_SIZE( sp )		/* t1 */
+	load_x  x7, 4 * portWORD_SIZE( sp )		/* t2 */
+	load_x  x8, 5 * portWORD_SIZE( sp )		/* s0/fp */
+	load_x  x9, 6 * portWORD_SIZE( sp )		/* s1 */
+	load_x  x10, 7 * portWORD_SIZE( sp )	/* a0 */
+	load_x  x11, 8 * portWORD_SIZE( sp )	/* a1 */
+	load_x  x12, 9 * portWORD_SIZE( sp )	/* a2 */
+	load_x  x13, 10 * portWORD_SIZE( sp )	/* a3 */
+	load_x  x14, 11 * portWORD_SIZE( sp )	/* a4 */
+	load_x  x15, 12 * portWORD_SIZE( sp )	/* a5 */
+	load_x  x16, 13 * portWORD_SIZE( sp )	/* a6 */
+	load_x  x17, 14 * portWORD_SIZE( sp )	/* a7 */
+	load_x  x18, 15 * portWORD_SIZE( sp )	/* s2 */
+	load_x  x19, 16 * portWORD_SIZE( sp )	/* s3 */
+	load_x  x20, 17 * portWORD_SIZE( sp )	/* s4 */
+	load_x  x21, 18 * portWORD_SIZE( sp )	/* s5 */
+	load_x  x22, 19 * portWORD_SIZE( sp )	/* s6 */
+	load_x  x23, 20 * portWORD_SIZE( sp )	/* s7 */
+	load_x  x24, 21 * portWORD_SIZE( sp )	/* s8 */
+	load_x  x25, 22 * portWORD_SIZE( sp )	/* s9 */
+	load_x  x26, 23 * portWORD_SIZE( sp )	/* s10 */
+	load_x  x27, 24 * portWORD_SIZE( sp )	/* s11 */
+	load_x  x28, 25 * portWORD_SIZE( sp )	/* t3 */
+	load_x  x29, 26 * portWORD_SIZE( sp )	/* t4 */
+	load_x  x30, 27 * portWORD_SIZE( sp )	/* t5 */
+	load_x  x31, 28 * portWORD_SIZE( sp )	/* t6 */
+	addi sp, sp, portCONTEXT_SIZE
+
+	mret
+
+/*-----------------------------------------------------------*/
+
+xPortStartFirstTask:
+
+#if( portasmHAS_SIFIVE_CLINT != 0 )
+	/* If there is a clint then interrupts can branch directly to the FreeRTOS
+	trap handler.  Otherwise the interrupt controller will need to be configured
+	outside of this file. */
+	la t0, freertos_risc_v_trap_handler
+	csrw CSR_MTVEC, t0
+#endif /* portasmHAS_CLILNT */
+
+	load_x  sp, pxCurrentTCB			/* Load pxCurrentTCB. */
+	load_x  sp, 0( sp )				 	/* Read sp from first TCB member. */
+
+	load_x  x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
+
+	portasmRESTORE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
+
+	load_x  x6, 3 * portWORD_SIZE( sp )		/* t1 */
+	load_x  x7, 4 * portWORD_SIZE( sp )		/* t2 */
+	load_x  x8, 5 * portWORD_SIZE( sp )		/* s0/fp */
+	load_x  x9, 6 * portWORD_SIZE( sp )		/* s1 */
+	load_x  x10, 7 * portWORD_SIZE( sp )	/* a0 */
+	load_x  x11, 8 * portWORD_SIZE( sp )	/* a1 */
+	load_x  x12, 9 * portWORD_SIZE( sp )	/* a2 */
+	load_x  x13, 10 * portWORD_SIZE( sp )	/* a3 */
+	load_x  x14, 11 * portWORD_SIZE( sp )	/* a4 */
+	load_x  x15, 12 * portWORD_SIZE( sp )	/* a5 */
+	load_x  x16, 13 * portWORD_SIZE( sp )	/* a6 */
+	load_x  x17, 14 * portWORD_SIZE( sp )	/* a7 */
+	load_x  x18, 15 * portWORD_SIZE( sp )	/* s2 */
+	load_x  x19, 16 * portWORD_SIZE( sp )	/* s3 */
+	load_x  x20, 17 * portWORD_SIZE( sp )	/* s4 */
+	load_x  x21, 18 * portWORD_SIZE( sp )	/* s5 */
+	load_x  x22, 19 * portWORD_SIZE( sp )	/* s6 */
+	load_x  x23, 20 * portWORD_SIZE( sp )	/* s7 */
+	load_x  x24, 21 * portWORD_SIZE( sp )	/* s8 */
+	load_x  x25, 22 * portWORD_SIZE( sp )	/* s9 */
+	load_x  x26, 23 * portWORD_SIZE( sp )	/* s10 */
+	load_x  x27, 24 * portWORD_SIZE( sp )	/* s11 */
+	load_x  x28, 25 * portWORD_SIZE( sp )	/* t3 */
+	load_x  x29, 26 * portWORD_SIZE( sp )	/* t4 */
+	load_x  x30, 27 * portWORD_SIZE( sp )	/* t5 */
+	load_x  x31, 28 * portWORD_SIZE( sp )	/* t6 */
+
+	load_x  x5, 29 * portWORD_SIZE( sp )	/* Initial mstatus into x5 (t0) */
+	addi x5, x5, 0x08						/* Set MIE bit so the first task starts with interrupts enabled - required as returns with ret not eret. */
+	csrrw  x0, CSR_MSTATUS, x5					/* Interrupts enabled from here! */
+	load_x  x5, 2 * portWORD_SIZE( sp )		/* Initial x5 (t0) value. */
+	addi	sp, sp, portCONTEXT_SIZE
+	ret
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Unlike other ports pxPortInitialiseStack() is written in assembly code as it
+ * needs access to the portasmADDITIONAL_CONTEXT_SIZE constant.  The prototype
+ * for the function is as per the other ports:
+ * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
+ *
+ * As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
+ * a1, and pvParameters in a2.  The new top of stack is passed out in a0.
+ *
+ * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
+ * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
+ *
+ * Register		ABI Name	Description						Saver
+ * x0			zero		Hard-wired zero					-
+ * x1			ra			Return address					Caller
+ * x2			sp			Stack pointer					Callee
+ * x3			gp			Global pointer					-
+ * x4			tp			Thread pointer					-
+ * x5-7			t0-2		Temporaries						Caller
+ * x8			s0/fp		Saved register/Frame pointer	Callee
+ * x9			s1			Saved register					Callee
+ * x10-11		a0-1		Function Arguments/return values Caller
+ * x12-17		a2-7		Function arguments				Caller
+ * x18-27		s2-11		Saved registers					Callee
+ * x28-31		t3-6		Temporaries						Caller
+ *
+ * The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
+ * where the global and thread pointers are currently assumed to be constant so
+ * are not saved:
+ *
+ * mstatus
+ * x31
+ * x30
+ * x29
+ * x28
+ * x27
+ * x26
+ * x25
+ * x24
+ * x23
+ * x22
+ * x21
+ * x20
+ * x19
+ * x18
+ * x17
+ * x16
+ * x15
+ * x14
+ * x13
+ * x12
+ * x11
+ * pvParameters
+ * x9
+ * x8
+ * x7
+ * x6
+ * x5
+ * portTASK_RETURN_ADDRESS
+ * [chip specific registers go here]
+ * pxCode
+ */
+pxPortInitialiseStack:
+
+	csrr t0, CSR_MSTATUS					/* Obtain current mstatus value. */
+	andi t0, t0, ~0x8					/* Ensure interrupts are disabled when the stack is restored within an ISR.  Required when a task is created after the schedulre has been started, otherwise interrupts would be disabled anyway. */
+	addi t1, x0, 0x188					/* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
+	slli t1, t1, 4
+	or t0, t0, t1						/* Set MPIE and MPP bits in mstatus value. */
+
+	addi a0, a0, -portWORD_SIZE
+	store_x t0, 0(a0)					/* mstatus onto the stack. */
+	addi a0, a0, -(22 * portWORD_SIZE)	/* Space for registers x11-x31. */
+	store_x a2, 0(a0)					/* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
+	addi a0, a0, -(6 * portWORD_SIZE)	/* Space for registers x5-x9. */
+	store_x x0, 0(a0)					/* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
+	addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
+chip_specific_stack_frame:				/* First add any chip specific registers to the stack frame being created. */
+	beq t0, x0, no_more_regs			/* No more chip specific registers to save. */
+	addi a0, a0, -portWORD_SIZE			/* Make space for chip specific register. */
+	store_x x0, 0(a0)					/* Give the chip specific register an initial value of zero. */
+	addi t0, t0, -1						/* Decrement the count of chip specific registers remaining. */
+	j chip_specific_stack_frame			/* Until no more chip specific registers. */
+no_more_regs:
+	addi a0, a0, -portWORD_SIZE
+	store_x a1, 0(a0)					/* mret value (pxCode parameter) onto the stack. */
+	ret
+
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/portmacro.h
new file mode 100644
index 0000000..6899fec
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/portmacro.h
@@ -0,0 +1,177 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include "intrinsics.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#if __riscv_xlen == 64
+	#define portSTACK_TYPE			uint64_t
+	#define portBASE_TYPE			int64_t
+	#define portUBASE_TYPE			uint64_t
+	#define portMAX_DELAY 			( TickType_t ) 0xffffffffffffffffUL
+	#define portPOINTER_SIZE_TYPE 	uint64_t
+#elif __riscv_xlen == 32
+	#define portSTACK_TYPE	uint32_t
+	#define portBASE_TYPE	int32_t
+	#define portUBASE_TYPE	uint32_t
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#else
+	#error Assembler did not define __riscv_xlen
+#endif
+
+
+typedef portSTACK_TYPE StackType_t;
+typedef portBASE_TYPE BaseType_t;
+typedef portUBASE_TYPE UBaseType_t;
+typedef portUBASE_TYPE TickType_t;
+
+/* Legacy type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+not need to be guarded with a critical section. */
+#define portTICK_TYPE_IS_ATOMIC 1
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#ifdef __riscv64
+	#error This is the RV32 port that has not yet been adapted for 64.
+	#define portBYTE_ALIGNMENT			16
+#else
+	#define portBYTE_ALIGNMENT 			16
+#endif
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+extern void vTaskSwitchContext( void );
+#define portYIELD() __asm volatile( "ecall" );
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vTaskSwitchContext()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+#define portCRITICAL_NESTING_IN_TCB					1
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+
+#define portSET_INTERRUPT_MASK_FROM_ISR() 0
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
+#define portDISABLE_INTERRUPTS()	__disable_interrupt()
+#define portENABLE_INTERRUPTS()		__enable_interrupt()
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
+
+	#error configUSE_PORT_OPTIMISED_TASK_SELECTION cannot yet be used in the IAR RISC-V port, the CLZ instruction needs to be emulated.
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/*-----------------------------------------------------------*/
+
+#define portNOP() __asm volatile 	( " nop " )
+
+#define portINLINE	__inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+
+/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
+the source code because to do so would cause other compilers to generate
+warnings. */
+#pragma diag_suppress=Pa082
+
+/* configCLINT_BASE_ADDRESS is a legacy definition that was replaced by the
+configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions.  For
+backward compatibility derive the newer definitions from the old if the old
+definition is found. */
+#if defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS ) && ( configCLINT_BASE_ADDRESS == 0 )
+	/* Legacy case where configCLINT_BASE_ADDRESS was defined as 0 to indicate
+	there was no CLINT.  Equivalent now is to set the MTIME and MTIMECMP
+	addresses to 0. */
+	#define configMTIME_BASE_ADDRESS 	( 0 )
+	#define configMTIMECMP_BASE_ADDRESS ( 0 )
+#elif defined( configCLINT_BASE_ADDRESS ) && !defined( configMTIME_BASE_ADDRESS )
+	/* Legacy case where configCLINT_BASE_ADDRESS was set to the base address of
+	the CLINT.  Equivalent now is to derive the MTIME and MTIMECMP addresses
+	from the CLINT address. */
+	#define configMTIME_BASE_ADDRESS 	( ( configCLINT_BASE_ADDRESS ) + 0xBFF8UL )
+	#define configMTIMECMP_BASE_ADDRESS ( ( configCLINT_BASE_ADDRESS ) + 0x4000UL )
+#elif !defined( configMTIME_BASE_ADDRESS ) || !defined( configMTIMECMP_BASE_ADDRESS )
+	#error configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  Set them to zero if there is no MTIME (machine time) clock.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+#endif
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/readme.txt
new file mode 100644
index 0000000..69d98d9
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RISC-V/readme.txt
@@ -0,0 +1,23 @@
+/*
+ * The FreeRTOS kernel's RISC-V port is split between the the code that is
+ * common across all currently supported RISC-V chips (implementations of the
+ * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
+ *
+ * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ *   is common to all currently supported RISC-V chips.  There is only one
+ *   portASM.S file because the same file is built for all RISC-V target chips.
+ *
+ * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
+ *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
+ *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
+ *   as there are multiple RISC-V chip implementations.
+ *
+ * !!!NOTE!!!
+ * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
+ * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
+ * compiler's!) include path.  For example, if the chip in use includes a core
+ * local interrupter (CLINT) and does not include any chip specific register
+ * extensions then add the path below to the assembler's include path:
+ * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ *
+ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RL78/ISR_Support.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RL78/ISR_Support.h
new file mode 100644
index 0000000..3ca3b85
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RL78/ISR_Support.h
@@ -0,0 +1,83 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+
+#include "FreeRTOSConfig.h"
+
+; Variables used by scheduler
+;------------------------------------------------------------------------------
+	EXTERN    pxCurrentTCB
+	EXTERN    usCriticalNesting
+
+;------------------------------------------------------------------------------
+;   portSAVE_CONTEXT MACRO
+;   Saves the context of the general purpose registers, CS and ES (only in far
+;	memory mode) registers the usCriticalNesting Value and the Stack Pointer
+;   of the active Task onto the task stack
+;------------------------------------------------------------------------------
+portSAVE_CONTEXT MACRO
+
+	PUSH      AX                    ; Save AX Register to stack.
+	PUSH      HL
+	MOV       A, CS                 ; Save CS register.
+	XCH       A, X
+	MOV       A, ES                 ; Save ES register.
+	PUSH      AX
+	PUSH      DE                    ; Save the remaining general purpose registers.
+	PUSH      BC
+	MOVW      AX, usCriticalNesting ; Save the usCriticalNesting value.
+	PUSH      AX
+	MOVW      AX, pxCurrentTCB 	    ; Save the Stack pointer.
+	MOVW      HL, AX
+	MOVW      AX, SP
+	MOVW      [HL], AX
+	ENDM
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   portRESTORE_CONTEXT MACRO
+;   Restores the task Stack Pointer then use this to restore usCriticalNesting,
+;   general purpose registers and the CS and ES (only in far memory mode)
+;   of the selected task from the task stack
+;------------------------------------------------------------------------------
+portRESTORE_CONTEXT MACRO
+	MOVW      AX, pxCurrentTCB	    ; Restore the Stack pointer.
+	MOVW      HL, AX
+	MOVW      AX, [HL]
+	MOVW      SP, AX
+	POP	      AX	                ; Restore usCriticalNesting value.
+	MOVW      usCriticalNesting, AX
+	POP	      BC                    ; Restore the necessary general purpose registers.
+	POP	      DE
+	POP       AX                    ; Restore the ES register.
+	MOV       ES, A
+	XCH       A, X                  ; Restore the CS register.
+	MOV       CS, A
+	POP       HL                    ; Restore general purpose register HL.
+	POP       AX                    ; Restore AX.
+	ENDM
+;------------------------------------------------------------------------------
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RL78/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RL78/port.c
new file mode 100644
index 0000000..0247213
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RL78/port.c
@@ -0,0 +1,280 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* The critical nesting value is initialised to a non zero value to ensure
+interrupts don't accidentally become enabled before the scheduler is started. */
+#define portINITIAL_CRITICAL_NESTING  ( ( uint16_t ) 10 )
+
+/* Initial PSW value allocated to a newly created task.
+ *   1100011000000000
+ *   ||||||||-------------- Fill byte
+ *   |||||||--------------- Carry Flag cleared
+ *   |||||----------------- In-service priority Flags set to low level
+ *   ||||------------------ Register bank Select 0 Flag cleared
+ *   |||------------------- Auxiliary Carry Flag cleared
+ *   ||-------------------- Register bank Select 1 Flag cleared
+ *   |--------------------- Zero Flag set
+ *   ---------------------- Global Interrupt Flag set (enabled)
+ */
+#define portPSW		  ( 0xc6UL )
+
+/* The address of the pxCurrentTCB variable, but don't know or need to know its
+type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Each task maintains a count of the critical section nesting depth.  Each time
+a critical section is entered the count is incremented.  Each time a critical
+section is exited the count is decremented - with interrupts only being
+re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as that could cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick using the interval timer.
+ * The application writer can define configSETUP_TICK_INTERRUPT() (in
+ * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
+ * in place of prvSetupTimerInterrupt().
+ */
+static void prvSetupTimerInterrupt( void );
+#ifndef configSETUP_TICK_INTERRUPT
+	/* The user has not provided their own tick interrupt configuration so use
+    the definition in this file (which uses the interval timer). */
+	#define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
+#endif /* configSETUP_TICK_INTERRUPT */
+
+/*
+ * Defined in portasm.s87, this function starts the scheduler by loading the
+ * context of the first task to run.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t *pulLocal;
+
+	/* With large code and large data sizeof( StackType_t ) == 2, and
+	sizeof( StackType_t * ) == 4.  With small code and small data
+	sizeof( StackType_t ) == 2 and sizeof( StackType_t * ) == 2. */
+
+	#if __DATA_MODEL__ == __DATA_MODEL_FAR__
+	{
+		/* Parameters are passed in on the stack, and written using a 32-bit value
+		hence a space is left for the second two bytes. */
+		pxTopOfStack--;
+
+		/* Write in the parameter value. */
+		pulLocal =  ( uint32_t * ) pxTopOfStack;
+		*pulLocal = ( uint32_t ) pvParameters;
+		pxTopOfStack--;
+
+		/* The return address, leaving space for the first two bytes of	the
+		32-bit value.  See the comments above the prvTaskExitError() prototype
+		at the top of this file. */
+		pxTopOfStack--;
+		pulLocal = ( uint32_t * ) pxTopOfStack;
+		*pulLocal = ( uint32_t ) prvTaskExitError;
+		pxTopOfStack--;
+
+		/* The start address / PSW value is also written in as a 32-bit value,
+		so leave a space for the second two bytes. */
+		pxTopOfStack--;
+
+		/* Task function start address combined with the PSW. */
+		pulLocal = ( uint32_t * ) pxTopOfStack;
+		*pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
+		pxTopOfStack--;
+
+		/* An initial value for the AX register. */
+		*pxTopOfStack = ( StackType_t ) 0x1111;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		/* The return address, leaving space for the first two bytes of	the
+		32-bit value.  See the comments above the prvTaskExitError() prototype
+		at the top of this file. */
+		pxTopOfStack--;
+		pulLocal = ( uint32_t * ) pxTopOfStack;
+		*pulLocal = ( uint32_t ) prvTaskExitError;
+		pxTopOfStack--;
+
+		/* Task function.  Again as it is written as a 32-bit value a space is
+		left on the stack for the second two bytes. */
+		pxTopOfStack--;
+
+		/* Task function start address combined with the PSW. */
+		pulLocal = ( uint32_t * ) pxTopOfStack;
+		*pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
+		pxTopOfStack--;
+
+		/* The parameter is passed in AX. */
+		*pxTopOfStack = ( StackType_t ) pvParameters;
+		pxTopOfStack--;
+	}
+	#endif
+
+	/* An initial value for the HL register. */
+	*pxTopOfStack = ( StackType_t ) 0x2222;
+	pxTopOfStack--;
+
+	/* CS and ES registers. */
+	*pxTopOfStack = ( StackType_t ) 0x0F00;
+	pxTopOfStack--;
+
+	/* The remaining general purpose registers DE and BC */
+	*pxTopOfStack = ( StackType_t ) 0xDEDE;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBCBC;
+	pxTopOfStack--;
+
+	/* Finally the critical section nesting count is set to zero when the task
+	first starts. */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+
+	/* Return a pointer to the top of the stack that has been generated so it
+	can	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( usCriticalNesting == ~0U );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called. */
+	configSETUP_TICK_INTERRUPT();
+
+	/* Restore the context of the first task that is going to run. */
+	vPortStartFirstTask();
+
+	/* Execution should not reach here as the tasks are now running!
+	prvSetupTimerInterrupt() is called here to prevent the compiler outputting
+	a warning about a statically declared function not being referenced in the
+	case that the application writer has provided their own tick interrupt
+	configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
+	their own routine will be called in place of prvSetupTimerInterrupt()). */
+	prvSetupTimerInterrupt();
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the RL78 port will get stopped. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+const uint16_t usClockHz = 15000UL; /* Internal clock. */
+const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL;
+
+	/* Use the internal 15K clock. */
+	OSMC = ( uint8_t ) 0x16;
+
+	#ifdef RTCEN
+	{
+		/* Supply the interval timer clock. */
+		RTCEN = ( uint8_t ) 1U;
+
+		/* Disable INTIT interrupt. */
+		ITMK = ( uint8_t ) 1;
+
+		/* Disable ITMC operation. */
+		ITMC = ( uint8_t ) 0x0000;
+
+		/* Clear INIT interrupt. */
+		ITIF = ( uint8_t ) 0;
+
+		/* Set interval and enable interrupt operation. */
+		ITMC = usCompareMatch | 0x8000U;
+
+		/* Enable INTIT interrupt. */
+		ITMK = ( uint8_t ) 0;
+	}
+	#endif
+
+	#ifdef TMKAEN
+	{
+		/* Supply the interval timer clock. */
+		TMKAEN = ( uint8_t ) 1U;
+
+		/* Disable INTIT interrupt. */
+		TMKAMK = ( uint8_t ) 1;
+
+		/* Disable ITMC operation. */
+		ITMC = ( uint8_t ) 0x0000;
+
+		/* Clear INIT interrupt. */
+		TMKAIF = ( uint8_t ) 0;
+
+		/* Set interval and enable interrupt operation. */
+		ITMC = usCompareMatch | 0x8000U;
+
+		/* Enable INTIT interrupt. */
+		TMKAMK = ( uint8_t ) 0;
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RL78/portasm.s87 b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RL78/portasm.s87
new file mode 100644
index 0000000..4f23f45
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RL78/portasm.s87
@@ -0,0 +1,83 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+#include "ISR_Support.h"
+
+#define CS                    0xFFFFC
+#define ES                    0xFFFFD
+
+	PUBLIC    vPortYield
+	PUBLIC    vPortStartFirstTask
+	PUBLIC    vPortTickISR
+
+	EXTERN    vTaskSwitchContext
+	EXTERN    xTaskIncrementTick
+
+; FreeRTOS yield handler.  This is installed as the BRK software interrupt
+; handler.
+    RSEG CODE:CODE
+vPortYield:
+	portSAVE_CONTEXT		        ; Save the context of the current task.
+	call      vTaskSwitchContext    ; Call the scheduler to select the next task.
+	portRESTORE_CONTEXT		        ; Restore the context of the next task to run.
+	retb
+
+
+; Starts the scheduler by restoring the context of the task that will execute
+; first.
+    RSEG CODE:CODE
+vPortStartFirstTask:
+	portRESTORE_CONTEXT	            ; Restore the context of whichever task the ...
+	reti					        ; An interrupt stack frame is used so the task
+                                    ; is started using a RETI instruction.
+
+; FreeRTOS tick handler.  This is installed as the interval timer interrupt
+; handler.
+	 RSEG CODE:CODE
+vPortTickISR:
+
+	portSAVE_CONTEXT		       ; Save the context of the current task.
+	call	xTaskIncrementTick     ; Call the timer tick function.
+	cmpw	ax, #0x00
+	skz
+	call	vTaskSwitchContext     ; Call the scheduler to select the next task.
+	portRESTORE_CONTEXT		       ; Restore the context of the next task to run.
+	reti
+
+
+; Install the interrupt handlers
+
+	COMMON INTVEC:CODE:ROOT(1)
+	ORG configTICK_VECTOR
+	DW vPortTickISR
+
+	COMMON INTVEC:CODE:ROOT(1)
+	ORG 126
+	DW vPortYield
+
+
+      END
\ No newline at end of file
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RL78/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RL78/portmacro.h
new file mode 100644
index 0000000..e2d1889
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RL78/portmacro.h
@@ -0,0 +1,144 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+#if __DATA_MODEL__ == __DATA_MODEL_FAR__ && __CODE_MODEL__ == __CODE_MODEL_NEAR__
+	#warning This port has not been tested with your selected memory model combination. If a far data model is required it is recommended to also use a far code model.
+#endif
+
+#if __DATA_MODEL__ == __DATA_MODEL_NEAR__ && __CODE_MODEL__ == __CODE_MODEL_FAR__
+	#warning This port has not been tested with your selected memory model combination. If a far code model is required it is recommended to also use a far data model.
+#endif
+
+/* Type definitions. */
+
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint16_t
+#define portBASE_TYPE   short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+
+#if __DATA_MODEL__ == __DATA_MODEL_FAR__
+	#define portPOINTER_SIZE_TYPE uint32_t
+#else
+	#define portPOINTER_SIZE_TYPE uint16_t
+#endif
+
+
+#if ( configUSE_16_BIT_TICKS == 1 )
+	typedef unsigned int TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS() __asm ( "DI" )
+#define portENABLE_INTERRUPTS()	 __asm ( "EI" )
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
+
+#define portENTER_CRITICAL()													\
+{																				\
+extern volatile uint16_t usCriticalNesting;										\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	/* Now interrupts are disabled ulCriticalNesting can be accessed */			\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
+	/* times portENTER_CRITICAL() has been called. */							\
+	usCriticalNesting++;														\
+}
+
+#define portEXIT_CRITICAL()														\
+{																				\
+extern volatile uint16_t usCriticalNesting;										\
+																				\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
+	{																			\
+		/* Decrement the nesting count as we are leaving a critical section. */	\
+		usCriticalNesting--;													\
+																				\
+		/* If the nesting level has reached zero then interrupts should be */	\
+		/* re-enabled. */														\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
+		{																		\
+			portENABLE_INTERRUPTS();											\
+		}																		\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portYIELD()	__asm( "BRK" )
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
+#define portNOP()	__asm( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Hardwware specifics. */
+#define portBYTE_ALIGNMENT	2
+#define portSTACK_GROWTH	( -1 )
+#define portTICK_PERIOD_MS	( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX100/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX100/port.c
new file mode 100644
index 0000000..6677dd6
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX100/port.c
@@ -0,0 +1,516 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Standard C includes. */
+#include "limits.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#include "machine.h"
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+
+/* The peripheral clock is divided by this value before being supplying the
+CMT. */
+#if ( configUSE_TICKLESS_IDLE == 0 )
+	/* If tickless idle is not used then the divisor can be fixed. */
+	#define portCLOCK_DIVISOR	8UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
+	#define portCLOCK_DIVISOR	512UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
+	#define portCLOCK_DIVISOR	128UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
+	#define portCLOCK_DIVISOR	32UL
+#else
+	#define portCLOCK_DIVISOR	8UL
+#endif
+
+
+/* Keys required to lock and unlock access to certain system registers
+respectively. */
+#define portUNLOCK_KEY		0xA50B
+#define portLOCK_KEY		0xA500
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+extern void prvStartFirstTask( void );
+
+/*
+ * The tick ISR handler.  The peripheral used is configured by the application
+ * via a hook/callback function.
+ */
+__interrupt static void prvTickISR( void );
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick using the CMT.
+ * The application writer can define configSETUP_TICK_INTERRUPT() (in
+ * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
+ * in place of prvSetupTimerInterrupt().
+ */
+static void prvSetupTimerInterrupt( void );
+#ifndef configSETUP_TICK_INTERRUPT
+	/* The user has not provided their own tick interrupt configuration so use
+    the definition in this file (which uses the interval timer). */
+	#define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
+#endif /* configSETUP_TICK_INTERRUPT */
+
+/*
+ * Called after the sleep mode registers have been configured, prvSleep()
+ * executes the pre and post sleep macros, and actually calls the wait
+ * instruction.
+ */
+#if configUSE_TICKLESS_IDLE == 1
+	static void prvSleep( TickType_t xExpectedIdleTime );
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+extern void *pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/* Calculate how many clock increments make up a single tick period. */
+static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	/* Holds the maximum number of ticks that can be suppressed - which is
+	basically how far into the future an interrupt can be generated. Set
+	during initialisation.  This is the maximum possible value that the
+	compare match register can hold divided by ulMatchValueForOneTick. */
+	static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
+
+	/* Flag set from the tick interrupt to allow the sleep processing to know if
+	sleep mode was exited because of a tick interrupt, or an interrupt
+	generated by something else. */
+	static volatile uint32_t ulTickFlag = pdFALSE;
+
+	/* The CMT counter is stopped temporarily each time it is re-programmed.
+	The following constant offsets the CMT counter match value by the number of
+	CMT	counts that would typically be missed while the counter was stopped to
+	compensate for the lost time.  The large difference between the divided CMT
+	clock and the CPU clock means it is likely ulStoppedTimerCompensation will
+	equal zero - and be optimised away. */
+	static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Offset to end up on 8 byte boundary. */
+	pxTopOfStack--;
+
+	/* R0 is not included as it is the stack pointer. */
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+    *pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0x12345678;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaabbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		/* Leave space for the registers that will get popped from the stack
+		when the task first starts executing. */
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x12345678; /* Accumulator. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x87654321; /* Accumulator. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate
+		the tick interrupt.  This way the application can decide which
+		peripheral to use.  If tickless mode is used then the default
+		implementation defined in this file (which uses CMT0) should not be
+		overridden. */
+		configSETUP_TICK_INTERRUPT();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Execution should not reach here as the tasks are now running!
+	prvSetupTimerInterrupt() is called here to prevent the compiler outputting
+	a warning about a statically declared function not being referenced in the
+	case that the application writer has provided their own tick interrupt
+	configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
+	their own routine will be called in place of prvSetupTimerInterrupt()). */
+	prvSetupTimerInterrupt();
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+#pragma vector = configTICK_VECTOR
+__interrupt static void prvTickISR( void )
+{
+	/* Re-enable interrupts. */
+	__enable_interrupt();
+
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates. */
+	__set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	__set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
+
+	#if configUSE_TICKLESS_IDLE == 1
+	{
+		/* The CPU woke because of a tick. */
+		ulTickFlag = pdTRUE;
+
+		/* If this is the first tick since exiting tickless mode then the CMT
+		compare match value needs resetting. */
+		CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	/* Unlock. */
+	SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+	/* Enable CMT0. */
+	MSTP( CMT0 ) = 0;
+
+	/* Lock again. */
+	SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+	/* Interrupt on compare match. */
+	CMT0.CMCR.BIT.CMIE = 1;
+
+	/* Set the compare match value. */
+	CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+
+	/* Divide the PCLK. */
+	#if portCLOCK_DIVISOR == 512
+	{
+		CMT0.CMCR.BIT.CKS = 3;
+	}
+	#elif portCLOCK_DIVISOR == 128
+	{
+		CMT0.CMCR.BIT.CKS = 2;
+	}
+	#elif portCLOCK_DIVISOR == 32
+	{
+		CMT0.CMCR.BIT.CKS = 1;
+	}
+	#elif portCLOCK_DIVISOR == 8
+	{
+		CMT0.CMCR.BIT.CKS = 0;
+	}
+	#else
+	{
+		#error Invalid portCLOCK_DIVISOR setting
+	}
+	#endif
+
+
+	/* Enable the interrupt... */
+	_IEN( _CMT0_CMI0 ) = 1;
+
+	/* ...and set its priority to the application defined kernel priority. */
+	_IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
+
+	/* Start the timer. */
+	CMT.CMSTR0.BIT.STR0 = 1;
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	static void prvSleep( TickType_t xExpectedIdleTime )
+	{
+		/* Allow the application to define some pre-sleep processing. */
+		configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
+
+		/* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
+		means the application defined code has already executed the WAIT
+		instruction. */
+		if( xExpectedIdleTime > 0 )
+		{
+			__wait_for_interrupt();
+		}
+
+		/* Allow the application to define some post sleep processing. */
+		configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
+	eSleepModeStatus eSleepAction;
+
+		/* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
+
+		/* Make sure the CMT reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Calculate the reload value required to wait xExpectedIdleTime tick
+		periods. */
+		ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
+		if( ulMatchValue > ulStoppedTimerCompensation )
+		{
+			/* Compensate for the fact that the CMT is going to be stopped
+			momentarily. */
+			ulMatchValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Stop the CMT momentarily.  The time the CMT is stopped for is
+		accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		CMT.CMSTR0.BIT.STR0 = 0;
+		while( CMT.CMSTR0.BIT.STR0 == 1 )
+		{
+			/* Nothing to do here. */
+		}
+
+		/* Critical section using the global interrupt bit as the i bit is
+		automatically reset by the WAIT instruction. */
+		__disable_interrupt();
+
+		/* The tick flag is set to false before sleeping.  If it is true when
+		sleep mode is exited then sleep mode was probably exited because the
+		tick was suppressed for the entire xExpectedIdleTime period. */
+		ulTickFlag = pdFALSE;
+
+		/* If a context switch is pending then abandon the low power entry as
+		the context switch might have been pended by an external interrupt that
+		requires processing. */
+		eSleepAction = eTaskConfirmSleepModeStatus();
+		if( eSleepAction == eAbortSleep )
+		{
+			/* Restart tick. */
+			CMT.CMSTR0.BIT.STR0 = 1;
+			__enable_interrupt();
+		}
+		else if( eSleepAction == eNoTasksWaitingTimeout )
+		{
+		    /* Protection off. */
+		    SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+		    /* Ready for software standby with all clocks stopped. */
+			SYSTEM.SBYCR.BIT.SSBY = 1;
+
+		    /* Protection on. */
+		    SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+			/* Sleep until something happens.  Calling prvSleep() will
+			automatically reset the i bit in the PSW. */
+			prvSleep( xExpectedIdleTime );
+
+			/* Restart the CMT. */
+			CMT.CMSTR0.BIT.STR0 = 1;
+		}
+		else
+		{
+		    /* Protection off. */
+		    SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+		    /* Ready for deep sleep mode. */
+			SYSTEM.MSTPCRC.BIT.DSLPE = 1;
+			SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
+			SYSTEM.SBYCR.BIT.SSBY = 0;
+
+		    /* Protection on. */
+		    SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+		    /* Adjust the match value to take into account that the current
+			time slice is already partially complete. */
+			ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
+			CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+
+			/* Restart the CMT to count up to the new match value. */
+			CMT0.CMCNT = 0;
+			CMT.CMSTR0.BIT.STR0 = 1;
+
+			/* Sleep until something happens.  Calling prvSleep() will
+			automatically reset the i bit in the PSW. */
+			prvSleep( xExpectedIdleTime );
+
+			/* Stop CMT.  Again, the time the SysTick is stopped for is
+			accounted for as best it can be, but using the tickless mode will
+			inevitably result in some tiny drift of the time maintained by the
+			kernel with	respect to calendar time. */
+			CMT.CMSTR0.BIT.STR0 = 0;
+			while( CMT.CMSTR0.BIT.STR0 == 1 )
+			{
+				/* Nothing to do here. */
+			}
+
+			ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
+
+			if( ulTickFlag != pdFALSE )
+			{
+				/* The tick interrupt has already executed, although because
+				this function is called with the scheduler suspended the actual
+				tick processing will not occur until after this function has
+				exited.  Reset the match value with whatever remains of this
+				tick period. */
+				ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
+				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+
+				/* The tick interrupt handler will already have pended the tick
+				processing in the kernel.  As the pending tick will be
+				processed as soon as this function exits, the tick value
+				maintained by the tick is stepped forward by one less than the
+				time spent sleeping.  The actual stepping of the tick appears
+				later in this function. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				How	many complete tick periods passed while the processor was
+				sleeping? */
+				ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
+
+				/* The match value is set to whatever fraction of a single tick
+				period remains. */
+				ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
+				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+			}
+
+			/* Restart the CMT so it runs up to the match value.  The match value
+			will get set to the value required to generate exactly one tick period
+			the next time the CMT interrupt executes. */
+			CMT0.CMCNT = 0;
+			CMT.CMSTR0.BIT.STR0 = 1;
+
+			/* Wind the tick forward by the number of tick periods that the CPU
+			remained in a low power state. */
+			vTaskStepTick( ulCompleteTickPeriods );
+		}
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX100/port_asm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX100/port_asm.s
new file mode 100644
index 0000000..dcf184d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX100/port_asm.s
@@ -0,0 +1,151 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "PriorityDefinitions.h"
+
+	PUBLIC _prvStartFirstTask
+	PUBLIC ___interrupt_27
+
+	EXTERN _pxCurrentTCB
+	EXTERN _vTaskSwitchContext
+
+	RSEG CODE:CODE(4)
+
+_prvStartFirstTask:
+
+		/* When starting the scheduler there is nothing that needs moving to the
+		interrupt stack because the function is not called from an interrupt.
+		Just ensure the current stack is the user stack. */
+		SETPSW		U
+
+		/* Obtain the location of the stack associated with which ever task
+		pxCurrentTCB is currently pointing to. */
+		MOV.L		#_pxCurrentTCB, R15
+		MOV.L		[R15], R15
+		MOV.L		[R15], R0
+
+		/* Restore the registers from the stack of the task pointed to by
+		pxCurrentTCB. */
+		POP			R15
+
+		/* Accumulator low 32 bits. */
+		MVTACLO		R15
+		POP			R15
+
+		/* Accumulator high 32 bits. */
+		MVTACHI		R15
+
+		/* R1 to R15 - R0 is not included as it is the SP. */
+		POPM		R1-R15
+
+		/* This pops the remaining registers. */
+		RTE
+		NOP
+		NOP
+
+/*-----------------------------------------------------------*/
+
+/* The software interrupt - overwrite the default 'weak' definition. */
+___interrupt_27:
+
+		/* Re-enable interrupts. */
+		SETPSW		I
+
+		/* Move the data that was automatically pushed onto the interrupt stack when
+		the interrupt occurred from the interrupt stack to the user stack.
+
+		R15 is saved before it is clobbered. */
+		PUSH.L		R15
+
+		/* Read the user stack pointer. */
+		MVFC		USP, R15
+
+		/* Move the address down to the data being moved. */
+		SUB			#12, R15
+		MVTC		R15, USP
+
+		/* Copy the data across, R15, then PC, then PSW. */
+		MOV.L		[ R0 ], [ R15 ]
+		MOV.L 		4[ R0 ], 4[ R15 ]
+		MOV.L		8[ R0 ], 8[ R15 ]
+
+		/* Move the interrupt stack pointer to its new correct position. */
+		ADD		#12, R0
+
+		/* All the rest of the registers are saved directly to the user stack. */
+		SETPSW		U
+
+		/* Save the rest of the general registers (R15 has been saved already). */
+		PUSHM		R1-R14
+
+		/* Save the accumulator. */
+		MVFACHI 	R15
+		PUSH.L		R15
+
+		/* Middle word. */
+		MVFACMI	R15
+
+		/* Shifted left as it is restored to the low order word. */
+		SHLL		#16, R15
+		PUSH.L		R15
+
+		/* Save the stack pointer to the TCB. */
+		MOV.L		#_pxCurrentTCB, R15
+		MOV.L		[ R15 ], R15
+		MOV.L		R0, [ R15 ]
+
+		/* Ensure the interrupt mask is set to the syscall priority while the kernel
+		structures are being accessed. */
+		MVTIPL		#configMAX_SYSCALL_INTERRUPT_PRIORITY
+
+		/* Select the next task to run. */
+		BSR.A		_vTaskSwitchContext
+
+		/* Reset the interrupt mask as no more data structure access is required. */
+		MVTIPL		#configKERNEL_INTERRUPT_PRIORITY
+
+		/* Load the stack pointer of the task that is now selected as the Running
+		state task from its TCB. */
+		MOV.L		#_pxCurrentTCB,R15
+		MOV.L		[ R15 ], R15
+		MOV.L		[ R15 ], R0
+
+		/* Restore the context of the new task.  The PSW (Program Status Word) and
+		PC will be popped by the RTE instruction. */
+		POP			R15
+		MVTACLO 	R15
+		POP			R15
+		MVTACHI 	R15
+		POPM		R1-R15
+		RTE
+		NOP
+		NOP
+
+/*-----------------------------------------------------------*/
+
+		END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX100/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX100/portmacro.h
new file mode 100644
index 0000000..b3f9571
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX100/portmacro.h
@@ -0,0 +1,150 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include <intrinsics.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Hardware specifics. */
+#include "machine.h"
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					__no_operation()
+
+#define portYIELD()						\
+	__asm volatile						\
+	(									\
+		"MOV.L #0x872E0, R15		\n"	\
+		"MOV.B #1, [R15]			\n"	\
+		"MOV.L [R15], R15			\n"	\
+		::: "R15"						\
+	)
+
+#define portYIELD_FROM_ISR( x )	if( ( x ) != pdFALSE ) { portYIELD(); }
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) 0 )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+	#define portDISABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
+
+/* Tickless idle/low power functionality. */
+#if configUSE_TICKLESS_IDLE == 1
+	#ifndef portSUPPRESS_TICKS_AND_SLEEP
+		extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+		#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+	#endif
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/* Prevent warnings of undefined behaviour: the order of volatile accesses is
+undefined - all warnings have been manually checked and are not an issue, and
+the warnings cannot be prevent by code changes without undesirable effects. */
+#pragma diag_suppress=Pa082
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX100/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX100/readme.txt
new file mode 100644
index 0000000..9e89a09
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX100/readme.txt
@@ -0,0 +1,72 @@
+The following table shows which port is recommended to be used.
+
+
+RX MCU Group    CPU     FPU         FPU         Port Layer
+                Core    (Single     (Double     CC-RX                   GNURX               ICCRX (*6)
+                Type    Precision)  Precision)
+
+RX110           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX111           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX113           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX130           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX13T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+
+RX210           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX21A           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX220           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX230,RX231     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23E-A         RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23W           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24U           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+
+RX610           RXv1    Yes         ---         N/A (*4)                N/A (*4)            N/A (*4)
+RX62N,RX621     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX630           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX634           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63N,RX631     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX64M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX65N,RX651     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX66N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX62T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX62G           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX66T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+RX71M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX72M           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+Notes:
+
+*1: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide
+the configuration function.  Please be aware that port.c is hard coded to use CMT0 though it seems to be
+configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*2: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is used, please modify port.c for the configuration.  Please be aware that port.c is
+hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of
+configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*3: RX100 ports are also available.
+
+*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction.
+
+*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
+
+#define configUSE_TASK_DPFPU_SUPPORT            0
+
+*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port.
+It contains two definitions of interrupt priority like the following.
+
+#define configKERNEL_INTERRUPT_PRIORITY         1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY    4
+
+
+For more information about Renesas RX MCUs, please visit the following URL:
+
+https://www.renesas.com/products/microcontrollers-microprocessors/rx.html
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX600/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX600/port.c
new file mode 100644
index 0000000..29af0f4
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX600/port.c
@@ -0,0 +1,193 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#include <iorx62n.h>
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW	 ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW	( ( StackType_t ) 0x00000100 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+extern void prvStartFirstTask( void );
+
+/*
+ * The tick ISR handler.  The peripheral used is configured by the application
+ * via a hook/callback function.
+ */
+__interrupt void vTickISR( void );
+
+/*-----------------------------------------------------------*/
+
+extern void *pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* R0 is not included as it is the stack pointer. */
+
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0xffffffff;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xeeeeeeee;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_FPSW;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x12345678; /* Accumulator. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x87654321; /* Accumulator. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate the
+		tick interrupt.  This way the application can decide which peripheral to
+		use.  A demo application is provided to show a suitable example. */
+		vApplicationSetupTimerInterrupt();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+#pragma vector = configTICK_VECTOR
+__interrupt void vTickISR( void )
+{
+	/* Re-enable interrupts. */
+	__enable_interrupt();
+
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates. */
+	__set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	__set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX600/port_asm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX600/port_asm.s
new file mode 100644
index 0000000..f0b7690
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX600/port_asm.s
@@ -0,0 +1,159 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "PriorityDefinitions.h"
+
+	PUBLIC _prvStartFirstTask
+	PUBLIC ___interrupt_27
+
+	EXTERN _pxCurrentTCB
+	EXTERN _vTaskSwitchContext
+
+	RSEG CODE:CODE(4)
+
+_prvStartFirstTask:
+
+		/* When starting the scheduler there is nothing that needs moving to the
+		interrupt stack because the function is not called from an interrupt.
+		Just ensure the current stack is the user stack. */
+		SETPSW		U
+
+		/* Obtain the location of the stack associated with which ever task
+		pxCurrentTCB is currently pointing to. */
+		MOV.L		#_pxCurrentTCB, R15
+		MOV.L		[R15], R15
+		MOV.L		[R15], R0
+
+		/* Restore the registers from the stack of the task pointed to by
+		pxCurrentTCB. */
+		POP			R15
+
+		/* Accumulator low 32 bits. */
+		MVTACLO		R15
+		POP			R15
+
+		/* Accumulator high 32 bits. */
+		MVTACHI		R15
+		POP			R15
+
+		/* Floating point status word. */
+		MVTC		R15, FPSW
+
+		/* R1 to R15 - R0 is not included as it is the SP. */
+		POPM		R1-R15
+
+		/* This pops the remaining registers. */
+		RTE
+		NOP
+		NOP
+
+/*-----------------------------------------------------------*/
+
+/* The software interrupt - overwrite the default 'weak' definition. */
+___interrupt_27:
+
+		/* Re-enable interrupts. */
+		SETPSW		I
+
+		/* Move the data that was automatically pushed onto the interrupt stack when
+		the interrupt occurred from the interrupt stack to the user stack.
+
+		R15 is saved before it is clobbered. */
+		PUSH.L		R15
+
+		/* Read the user stack pointer. */
+		MVFC		USP, R15
+
+		/* Move the address down to the data being moved. */
+		SUB			#12, R15
+		MVTC		R15, USP
+
+		/* Copy the data across, R15, then PC, then PSW. */
+		MOV.L		[ R0 ], [ R15 ]
+		MOV.L 		4[ R0 ], 4[ R15 ]
+		MOV.L		8[ R0 ], 8[ R15 ]
+
+		/* Move the interrupt stack pointer to its new correct position. */
+		ADD		#12, R0
+
+		/* All the rest of the registers are saved directly to the user stack. */
+		SETPSW		U
+
+		/* Save the rest of the general registers (R15 has been saved already). */
+		PUSHM		R1-R14
+
+		/* Save the FPSW and accumulator. */
+		MVFC		FPSW, R15
+		PUSH.L		R15
+		MVFACHI 	R15
+		PUSH.L		R15
+
+		/* Middle word. */
+		MVFACMI	R15
+
+		/* Shifted left as it is restored to the low order word. */
+		SHLL		#16, R15
+		PUSH.L		R15
+
+		/* Save the stack pointer to the TCB. */
+		MOV.L		#_pxCurrentTCB, R15
+		MOV.L		[ R15 ], R15
+		MOV.L		R0, [ R15 ]
+
+		/* Ensure the interrupt mask is set to the syscall priority while the kernel
+		structures are being accessed. */
+		MVTIPL		#configMAX_SYSCALL_INTERRUPT_PRIORITY
+
+		/* Select the next task to run. */
+		BSR.A		_vTaskSwitchContext
+
+		/* Reset the interrupt mask as no more data structure access is required. */
+		MVTIPL		#configKERNEL_INTERRUPT_PRIORITY
+
+		/* Load the stack pointer of the task that is now selected as the Running
+		state task from its TCB. */
+		MOV.L		#_pxCurrentTCB,R15
+		MOV.L		[ R15 ], R15
+		MOV.L		[ R15 ], R0
+
+		/* Restore the context of the new task.  The PSW (Program Status Word) and
+		PC will be popped by the RTE instruction. */
+		POP			R15
+		MVTACLO 	R15
+		POP			R15
+		MVTACHI 	R15
+		POP			R15
+		MVTC		R15, FPSW
+		POPM		R1-R15
+		RTE
+		NOP
+		NOP
+
+/*-----------------------------------------------------------*/
+
+		END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX600/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX600/portmacro.h
new file mode 100644
index 0000000..e6a762e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX600/portmacro.h
@@ -0,0 +1,139 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include <intrinsics.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					__no_operation()
+
+/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
+where portITU_SWINTR is the location of the software interrupt register
+(0x000872E0).  Don't rely on the assembler to select a register, so instead
+save and restore clobbered registers manually. */
+#define portYIELD()							\
+	__asm volatile 							\
+	(										\
+		"PUSH.L	R10					\n"		\
+		"MOV.L	#0x872E0, R10		\n"		\
+		"MOV.B	#0x1, [R10]			\n"		\
+		"MOV.L	[R10], R10			\n"		\
+		"POP	R10					\n"		\
+	)
+
+#define portYIELD_FROM_ISR( x )	if( ( x ) != pdFALSE ) portYIELD()
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) 0 )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+	#define portDISABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX600/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX600/readme.txt
new file mode 100644
index 0000000..9e89a09
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX600/readme.txt
@@ -0,0 +1,72 @@
+The following table shows which port is recommended to be used.
+
+
+RX MCU Group    CPU     FPU         FPU         Port Layer
+                Core    (Single     (Double     CC-RX                   GNURX               ICCRX (*6)
+                Type    Precision)  Precision)
+
+RX110           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX111           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX113           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX130           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX13T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+
+RX210           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX21A           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX220           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX230,RX231     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23E-A         RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23W           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24U           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+
+RX610           RXv1    Yes         ---         N/A (*4)                N/A (*4)            N/A (*4)
+RX62N,RX621     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX630           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX634           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63N,RX631     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX64M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX65N,RX651     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX66N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX62T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX62G           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX66T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+RX71M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX72M           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+Notes:
+
+*1: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide
+the configuration function.  Please be aware that port.c is hard coded to use CMT0 though it seems to be
+configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*2: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is used, please modify port.c for the configuration.  Please be aware that port.c is
+hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of
+configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*3: RX100 ports are also available.
+
+*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction.
+
+*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
+
+#define configUSE_TASK_DPFPU_SUPPORT            0
+
+*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port.
+It contains two definitions of interrupt priority like the following.
+
+#define configKERNEL_INTERRUPT_PRIORITY         1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY    4
+
+
+For more information about Renesas RX MCUs, please visit the following URL:
+
+https://www.renesas.com/products/microcontrollers-microprocessors/rx.html
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX700v3_DPFPU/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX700v3_DPFPU/port.c
new file mode 100644
index 0000000..83a5f40
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX700v3_DPFPU/port.c
@@ -0,0 +1,567 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the RXv3 DPFPU port.
+*----------------------------------------------------------*/
+
+#warning Testing for DFPU support in this port is not yet complete
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+    #include "platform.h"
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+    #include "iodefine.h"
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+ * PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
+#define portINITIAL_DPSW    ( ( StackType_t ) 0x00000100 )
+#define portINITIAL_DCMR    ( ( StackType_t ) 0x00000000 )
+#define portINITIAL_DECNT   ( ( StackType_t ) 0x00000001 )
+
+/* Tasks are not created with a DPFPU context, but can be given a DPFPU context
+ * after they have been created.  A variable is stored as part of the tasks context
+ * that holds portNO_DPFPU_CONTEXT if the task does not have a DPFPU context, or
+ * any other value if the task does have a DPFPU context. */
+#define portNO_DPFPU_CONTEXT    ( ( StackType_t ) 0 )
+#define portHAS_DPFPU_CONTEXT   ( ( StackType_t ) 1 )
+
+/* The space on the stack required to hold the DPFPU data registers.  This is 16
+ * 64-bit registers. */
+#define portDPFPU_DATA_REGISTER_WORDS   ( 16 * 2 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+__interrupt void vSoftwareInterruptISR( void );
+
+/*
+ * The tick ISR handler.  The peripheral used is configured by the application
+ * via a hook/callback function.
+ */
+__interrupt void vTickISR( void );
+
+/*-----------------------------------------------------------*/
+
+/* Saved as part of the task context.  If ulPortTaskHasDPFPUContext is non-zero
+ * then a DPFPU context must be saved and restored for the task. */
+#if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+    StackType_t ulPortTaskHasDPFPUContext = portNO_DPFPU_CONTEXT;
+
+#endif /* configUSE_TASK_DPFPU_SUPPORT */
+
+/* This is accessed by the inline assembler functions so is file scope for
+ * convenience. */
+extern void * pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* R0 is not included as it is the stack pointer. */
+
+    *pxTopOfStack = 0x00;
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_PSW;
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) pxCode;
+
+    /* When debugging it can be useful if every register is set to a known
+     * value.  Otherwise code space can be saved by just setting the registers
+     * that need to be set. */
+    #ifdef USE_FULL_REGISTER_INITIALISATION
+        {
+            pxTopOfStack--;
+            *pxTopOfStack = 0xffffffff; /* r15. */
+            pxTopOfStack--;
+            *pxTopOfStack = 0xeeeeeeee;
+            pxTopOfStack--;
+            *pxTopOfStack = 0xdddddddd;
+            pxTopOfStack--;
+            *pxTopOfStack = 0xcccccccc;
+            pxTopOfStack--;
+            *pxTopOfStack = 0xbbbbbbbb;
+            pxTopOfStack--;
+            *pxTopOfStack = 0xaaaaaaaa;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x99999999;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x88888888;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x77777777;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x66666666;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x55555555;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x44444444;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x33333333;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x22222222;
+            pxTopOfStack--;
+        }
+    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
+        {
+            pxTopOfStack -= 15;
+        }
+    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_FPSW;
+    pxTopOfStack--;
+    *pxTopOfStack = 0x11111111; /* Accumulator 1. */
+    pxTopOfStack--;
+    *pxTopOfStack = 0x22222222; /* Accumulator 1. */
+    pxTopOfStack--;
+    *pxTopOfStack = 0x33333333; /* Accumulator 1. */
+    pxTopOfStack--;
+    *pxTopOfStack = 0x44444444; /* Accumulator 0. */
+    pxTopOfStack--;
+    *pxTopOfStack = 0x55555555; /* Accumulator 0. */
+    pxTopOfStack--;
+    *pxTopOfStack = 0x66666666; /* Accumulator 0. */
+
+    #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+        {
+            /* The task will start without a DPFPU context.  A task that
+             * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before
+             * executing any floating point instructions. */
+            pxTopOfStack--;
+            *pxTopOfStack = portNO_DPFPU_CONTEXT;
+        }
+    #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+        {
+            /* The task will start with a DPFPU context.  Leave enough
+             * space for the registers - and ensure they are initialised if desired. */
+            #ifdef USE_FULL_REGISTER_INITIALISATION
+                {
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1515.1515; /* DR15. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1414.1414; /* DR14. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1313.1313; /* DR13. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1212.1212; /* DR12. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1111.1111; /* DR11. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1010.1010; /* DR10. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  909.0909; /* DR9. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  808.0808; /* DR8. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  707.0707; /* DR7. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  606.0606; /* DR6. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  505.0505; /* DR5. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  404.0404; /* DR4. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  303.0303; /* DR3. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  202.0202; /* DR2. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  101.0101; /* DR1. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 9876.54321;/* DR0. */
+                }
+            #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
+                {
+                    pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS;
+                    memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) );
+                }
+            #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_DCMR;  /* DCMR. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_DPSW;  /* DPSW. */
+        }
+    #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 )
+        {
+            /* Omit DPFPU support. */
+        }
+    #else /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+        {
+            #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined.
+        }
+    #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+    void vPortTaskUsesDPFPU( void )
+    {
+        /* A task is registering the fact that it needs a DPFPU context.  Set the
+         * DPFPU flag (which is saved as part of the task context). */
+        ulPortTaskHasDPFPUContext = portHAS_DPFPU_CONTEXT;
+    }
+
+#endif /* configUSE_TASK_DPFPU_SUPPORT */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+    extern void vApplicationSetupTimerInterrupt( void );
+
+    /* Use pxCurrentTCB just so it does not get optimised away. */
+    if( pxCurrentTCB != NULL )
+    {
+        /* Call an application function to set up the timer that will generate the
+         * tick interrupt.  This way the application can decide which peripheral to
+         * use.  A demo application is provided to show a suitable example. */
+        vApplicationSetupTimerInterrupt();
+
+        /* Enable the software interrupt. */
+        _IEN( _ICU_SWINT ) = 1;
+
+        /* Ensure the software interrupt is clear. */
+        _IR( _ICU_SWINT ) = 0;
+
+        /* Ensure the software interrupt is set to the kernel priority. */
+        _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+        /* Start the first task. */
+        prvStartFirstTask();
+    }
+
+    /* Should not get here. */
+    return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( pxCurrentTCB == NULL );
+
+    /* The following line is just to prevent the symbol getting optimised away. */
+    ( void ) vTaskSwitchContext();
+}
+/*-----------------------------------------------------------*/
+
+static void prvStartFirstTask( void )
+{
+    __asm volatile
+    (
+
+        /* When starting the scheduler there is nothing that needs moving to the
+         * interrupt stack because the function is not called from an interrupt.
+         * Just ensure the current stack is the user stack. */
+        "SETPSW		U						\n"\
+
+
+        /* Obtain the location of the stack associated with which ever task
+         * pxCurrentTCB is currently pointing to. */
+        "MOV.L		#_pxCurrentTCB, R15		\n"\
+        "MOV.L		[R15], R15				\n"\
+        "MOV.L		[R15], R0				\n"\
+
+
+        /* Restore the registers from the stack of the task pointed to by
+         * pxCurrentTCB. */
+
+        #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+            /* The restored ulPortTaskHasDPFPUContext is to be zero here.
+             * So, it is never necessary to restore the DPFPU context here. */
+            "POP		R15									\n"\
+            "MOV.L		#_ulPortTaskHasDPFPUContext, R14	\n"\
+            "MOV.L		R15, [R14]							\n"\
+
+        #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+
+            /* Restore the DPFPU context. */
+            "DPOPM.L	DPSW-DECNT				\n"\
+            "DPOPM.D	DR0-DR15				\n"\
+
+        #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+
+        "POP		R15						\n"\
+
+        /* Accumulator low 32 bits. */
+        "MVTACLO	R15, A0					\n"\
+        "POP		R15						\n"\
+
+        /* Accumulator high 32 bits. */
+        "MVTACHI	R15, A0					\n"\
+        "POP		R15						\n"\
+
+        /* Accumulator guard. */
+        "MVTACGU	R15, A0					\n"\
+        "POP		R15						\n"\
+
+        /* Accumulator low 32 bits. */
+        "MVTACLO	R15, A1					\n"\
+        "POP		R15						\n"\
+
+        /* Accumulator high 32 bits. */
+        "MVTACHI	R15, A1					\n"\
+        "POP		R15						\n"\
+
+        /* Accumulator guard. */
+        "MVTACGU	R15, A1					\n"\
+        "POP		R15						\n"\
+
+        /* Floating point status word. */
+        "MVTC		R15, FPSW 				\n"\
+
+        /* R1 to R15 - R0 is not included as it is the SP. */
+        "POPM		R1-R15 					\n"\
+
+        /* This pops the remaining registers. */
+        "RTE								\n"\
+        "NOP								\n"\
+        "NOP								\n"
+    );
+}
+/*-----------------------------------------------------------*/
+
+#pragma vector = VECT( ICU, SWINT )
+__interrupt void vSoftwareInterruptISR( void )
+{
+    __asm volatile
+    (
+        /* Re-enable interrupts. */
+        "SETPSW		I							\n"\
+
+
+        /* Move the data that was automatically pushed onto the interrupt stack when
+         * the interrupt occurred from the interrupt stack to the user stack.
+         *
+         * R15 is saved before it is clobbered. */
+        "PUSH.L		R15							\n"\
+
+        /* Read the user stack pointer. */
+        "MVFC		USP, R15					\n"\
+
+        /* Move the address down to the data being moved. */
+        "SUB		#12, R15					\n"\
+        "MVTC		R15, USP					\n"\
+
+        /* Copy the data across, R15, then PC, then PSW. */
+        "MOV.L		[ R0 ], [ R15 ]				\n"\
+        "MOV.L 		4[ R0 ], 4[ R15 ]			\n"\
+        "MOV.L		8[ R0 ], 8[ R15 ]			\n"\
+
+        /* Move the interrupt stack pointer to its new correct position. */
+        "ADD		#12, R0						\n"\
+
+        /* All the rest of the registers are saved directly to the user stack. */
+        "SETPSW		U							\n"\
+
+        /* Save the rest of the general registers (R15 has been saved already). */
+        "PUSHM		R1-R14						\n"\
+
+        /* Save the FPSW and accumulators. */
+        "MVFC		FPSW, R15					\n"\
+        "PUSH.L		R15							\n"\
+        "MVFACGU	#0, A1, R15					\n"\
+        "PUSH.L		R15							\n"\
+        "MVFACHI	#0, A1, R15					\n"\
+        "PUSH.L		R15							\n"\
+        "MVFACLO	#0, A1, R15					\n" /* Low order word. */ \
+        "PUSH.L		R15							\n"\
+        "MVFACGU	#0, A0, R15					\n"\
+        "PUSH.L		R15							\n"\
+        "MVFACHI	#0, A0, R15					\n"\
+        "PUSH.L		R15							\n"\
+        "MVFACLO	#0, A0, R15					\n" /* Low order word. */ \
+        "PUSH.L		R15							\n"\
+
+        #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+            /* Does the task have a DPFPU context that needs saving?  If
+             * ulPortTaskHasDPFPUContext is 0 then no. */
+            "MOV.L		#_ulPortTaskHasDPFPUContext, R15	\n"\
+            "MOV.L		[R15], R15							\n"\
+            "CMP		#0, R15								\n"\
+
+            /* Save the DPFPU context, if any. */
+            "BEQ.B		__lab1						\n"\
+            "DPUSHM.D	DR0-DR15					\n"\
+            "DPUSHM.L	DPSW-DECNT					\n"\
+            "__lab1:								\n"\
+
+            /* Save ulPortTaskHasDPFPUContext itself. */
+            "PUSH.L		R15							\n"\
+
+        #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+
+            /* Save the DPFPU context, always. */
+            "DPUSHM.D	DR0-DR15					\n"\
+            "DPUSHM.L	DPSW-DECNT					\n"\
+
+        #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+
+
+        /* Save the stack pointer to the TCB. */
+        "MOV.L		#_pxCurrentTCB, R15			\n"\
+        "MOV.L		[ R15 ], R15				\n"\
+        "MOV.L		R0, [ R15 ]					\n"\
+
+
+        /* Ensure the interrupt mask is set to the syscall priority while the kernel
+         * structures are being accessed. */
+        "MVTIPL		%0 							\n"\
+
+        /* Select the next task to run. */
+        "BSR.A		_vTaskSwitchContext			\n"\
+
+        /* Reset the interrupt mask as no more data structure access is required. */
+        "MVTIPL		%1							\n"\
+
+
+        /* Load the stack pointer of the task that is now selected as the Running
+         * state task from its TCB. */
+        "MOV.L		#_pxCurrentTCB,R15			\n"\
+        "MOV.L		[ R15 ], R15				\n"\
+        "MOV.L		[ R15 ], R0					\n"\
+
+
+        /* Restore the context of the new task.  The PSW (Program Status Word) and
+         * PC will be popped by the RTE instruction. */
+
+        #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+            /* Is there a DPFPU context to restore?  If the restored
+             * ulPortTaskHasDPFPUContext is zero then no. */
+            "POP		R15									\n"\
+            "MOV.L		#_ulPortTaskHasDPFPUContext, R14	\n"\
+            "MOV.L		R15, [R14]							\n"\
+            "CMP		#0, R15								\n"\
+
+            /* Restore the DPFPU context, if any. */
+            "BEQ.B		__lab2						\n"\
+            "DPOPM.L	DPSW-DECNT					\n"\
+            "DPOPM.D	DR0-DR15					\n"\
+            "__lab2:								\n"\
+
+        #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+
+            /* Restore the DPFPU context, always. */
+            "DPOPM.L	DPSW-DECNT					\n"\
+            "DPOPM.D	DR0-DR15					\n"\
+
+        #endif /* if( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+
+        "POP		R15							\n"\
+
+        /* Accumulator low 32 bits. */
+        "MVTACLO	R15, A0						\n"\
+        "POP		R15							\n"\
+
+        /* Accumulator high 32 bits. */
+        "MVTACHI	R15, A0						\n"\
+        "POP		R15							\n"\
+
+        /* Accumulator guard. */
+        "MVTACGU	R15, A0						\n"\
+        "POP		R15							\n"\
+
+        /* Accumulator low 32 bits. */
+        "MVTACLO	R15, A1						\n"\
+        "POP		R15							\n"\
+
+        /* Accumulator high 32 bits. */
+        "MVTACHI	R15, A1						\n"\
+        "POP		R15							\n"\
+
+        /* Accumulator guard. */
+        "MVTACGU	R15, A1						\n"\
+        "POP		R15							\n"\
+        "MVTC		R15, FPSW					\n"\
+        "POPM		R1-R15						\n"\
+        "RTE									\n"\
+        "NOP									\n"\
+        "NOP									  "
+        portCDT_NO_PARSE( :: ) "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ), "i" ( configKERNEL_INTERRUPT_PRIORITY )
+    );
+}
+/*-----------------------------------------------------------*/
+
+#pragma vector = _VECT( configTICK_VECTOR )
+__interrupt void vTickISR( void )
+{
+    /* Re-enable interrupts. */
+    __enable_interrupt();
+
+    /* Increment the tick, and perform any processing the new tick value
+     * necessitates.  Ensure IPL is at the max syscall value first. */
+    __set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+    {
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            taskYIELD();
+        }
+    }
+    __set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX700v3_DPFPU/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX700v3_DPFPU/portmacro.h
new file mode 100644
index 0000000..df45877
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX700v3_DPFPU/portmacro.h
@@ -0,0 +1,195 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+/* Hardware specifics. */
+    #include <intrinsics.h>
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* When the FIT configurator or the Smart Configurator is used, platform.h has to be 
+ * used. */
+    #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
+        #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
+    #endif
+
+/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will
+ * be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before
+ * making use of any DPFPU registers.  If configUSE_TASK_DPFPU_SUPPORT is set to 2 then
+ * tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has
+ * no effect.  If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care
+ * of any DPFPU context (even if DPFPU registers are used). */
+    #ifndef configUSE_TASK_DPFPU_SUPPORT
+        #define configUSE_TASK_DPFPU_SUPPORT 1
+    #endif
+
+/*-----------------------------------------------------------*/
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+ * portSTACK_TYPE and portBASE_TYPE. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+    #define portBYTE_ALIGNMENT    8     /* Could make four, according to manual. */
+    #define portSTACK_GROWTH      -1
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portNOP()    __no_operation()
+
+/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
+ * where portITU_SWINTR is the location of the software interrupt register
+ * (0x000872E0).  Don't rely on the assembler to select a register, so instead
+ * save and restore clobbered registers manually. */
+    #define portYIELD()           \
+    __asm volatile                \
+    (                             \
+        "PUSH.L	R10					\n"\
+        "MOV.L	#0x872E0, R10		\n"\
+        "MOV.B	#0x1, [R10]			\n"\
+        "CMP	[R10].UB, R10		\n"\
+        "POP    R10					\n"\
+        portCDT_NO_PARSE( ::: ) "cc"\
+    )
+
+    #define portYIELD_FROM_ISR( x )                           if( ( x ) != pdFALSE ) portYIELD()
+
+/* Workaround to reduce errors/warnings caused by e2 studio CDT's INDEXER and CODAN. */
+    #ifdef __CDT_PARSER__
+    #ifndef __asm
+    #define __asm asm
+    #endif
+    #ifndef __attribute__
+    #define __attribute__( ... )
+    #endif
+    #define portCDT_NO_PARSE( token )
+    #else
+    #define portCDT_NO_PARSE( token ) token
+    #endif
+
+/* These macros should not be called directly, but through the
+ * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+ * performed if configASSERT() is defined to ensure an assertion handler does not
+ * inadvertently attempt to lower the IPL when the call to assert was triggered
+ * because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+ * functions are those that end in FromISR.  FreeRTOS maintains a separate
+ * interrupt API to ensure API function and interrupt entry is as fast and as
+ * simple as possible. */
+    #define portENABLE_INTERRUPTS()                           __set_interrupt_level( ( uint8_t ) 0 )
+    #ifdef configASSERT
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+        #define portDISABLE_INTERRUPTS()                      if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #else
+        #define portDISABLE_INTERRUPTS()                      __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #endif
+
+/* Critical nesting counts are stored in the TCB. */
+    #define portCRITICAL_NESTING_IN_TCB    ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+    extern void vTaskEnterCritical( void );
+    extern void vTaskExitCritical( void );
+    #define portENTER_CRITICAL()    vTaskEnterCritical()
+    #define portEXIT_CRITICAL()     vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()                              __get_interrupt_level(); portDISABLE_INTERRUPTS()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+/*-----------------------------------------------------------*/
+
+/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or left undefined) then tasks are
+ * created without a DPFPU context and must call vPortTaskUsesDPFPU() to give
+ * themselves a DPFPU context before using any DPFPU instructions.  If
+ * configUSE_TASK_DPFPU_SUPPORT is set to 2 then all tasks will have a DPFPU context
+ * by default. */
+    #if( configUSE_TASK_DPFPU_SUPPORT == 1 )
+        void vPortTaskUsesDPFPU( void );
+    #else
+/* Each task has a DPFPU context already, so define this function away to
+ * nothing to prevent it being called accidentally. */
+        #define vPortTaskUsesDPFPU()
+    #endif
+    #define portTASK_USES_DPFPU() vPortTaskUsesDPFPU()
+
+/* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */
+    #define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU()
+
+/* Prevent warnings of undefined behaviour: the order of volatile accesses is
+ * undefined - all warnings have been manually checked and are not an issue, and
+ * the warnings cannot be prevent by code changes without undesirable effects. */
+    #pragma diag_suppress=Pa082
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX700v3_DPFPU/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX700v3_DPFPU/readme.txt
new file mode 100644
index 0000000..9e89a09
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RX700v3_DPFPU/readme.txt
@@ -0,0 +1,72 @@
+The following table shows which port is recommended to be used.
+
+
+RX MCU Group    CPU     FPU         FPU         Port Layer
+                Core    (Single     (Double     CC-RX                   GNURX               ICCRX (*6)
+                Type    Precision)  Precision)
+
+RX110           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX111           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX113           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX130           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX13T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+
+RX210           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX21A           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX220           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX230,RX231     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23E-A         RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23W           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24U           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+
+RX610           RXv1    Yes         ---         N/A (*4)                N/A (*4)            N/A (*4)
+RX62N,RX621     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX630           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX634           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63N,RX631     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX64M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX65N,RX651     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX66N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX62T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX62G           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX66T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+RX71M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX72M           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+Notes:
+
+*1: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide
+the configuration function.  Please be aware that port.c is hard coded to use CMT0 though it seems to be
+configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*2: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is used, please modify port.c for the configuration.  Please be aware that port.c is
+hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of
+configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*3: RX100 ports are also available.
+
+*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction.
+
+*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
+
+#define configUSE_TASK_DPFPU_SUPPORT            0
+
+*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port.
+It contains two definitions of interrupt priority like the following.
+
+#define configKERNEL_INTERRUPT_PRIORITY         1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY    4
+
+
+For more information about Renesas RX MCUs, please visit the following URL:
+
+https://www.renesas.com/products/microcontrollers-microprocessors/rx.html
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RXv2/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RXv2/port.c
new file mode 100644
index 0000000..fd81f5d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RXv2/port.c
@@ -0,0 +1,201 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#include <machine.h>
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW	 ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW	( ( StackType_t ) 0x00000100 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+extern void prvStartFirstTask( void );
+
+/*
+ * The tick ISR handler.  The peripheral used is configured by the application
+ * via a hook/callback function.
+ */
+__interrupt void vTickISR( void );
+
+/*-----------------------------------------------------------*/
+
+extern void *pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* R0 is not included as it is the stack pointer. */
+
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0xffffffff;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xeeeeeeee;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_FPSW;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11111111; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22222222; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33333333; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44444444; /* Accumulator 1. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55555555; /* Accumulator 1. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66666666; /* Accumulator 1. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate the
+		tick interrupt.  This way the application can decide which peripheral to
+		use.  A demo application is provided to show a suitable example. */
+		vApplicationSetupTimerInterrupt();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+#pragma vector = configTICK_VECTOR
+__interrupt void vTickISR( void )
+{
+	/* Re-enable interrupts. */
+	__enable_interrupt();
+
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates. */
+	__set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	__set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s
new file mode 100644
index 0000000..5313755
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s
@@ -0,0 +1,200 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "PriorityDefinitions.h"
+
+	PUBLIC _prvStartFirstTask
+	PUBLIC ___interrupt_27
+
+	EXTERN _pxCurrentTCB
+	EXTERN _vTaskSwitchContext
+
+	RSEG CODE:CODE(4)
+
+_prvStartFirstTask:
+
+		/* When starting the scheduler there is nothing that needs moving to the
+		interrupt stack because the function is not called from an interrupt.
+		Just ensure the current stack is the user stack. */
+		SETPSW		U
+
+		/* Obtain the location of the stack associated with which ever task
+		pxCurrentTCB is currently pointing to. */
+		MOV.L		#_pxCurrentTCB, R15
+		MOV.L		[R15], R15
+		MOV.L		[R15], R0
+
+		/* Restore the registers from the stack of the task pointed to by
+		pxCurrentTCB. */
+		POP			R15
+
+		/* Accumulator low 32 bits. */
+		MVTACLO		R15, A0
+		POP			R15
+
+		/* Accumulator high 32 bits. */
+		MVTACHI		R15, A0
+		POP			R15
+
+		/* Accumulator guard. */
+		MVTACGU		R15, A0
+		POP			R15
+
+		/* Accumulator low 32 bits. */
+		MVTACLO		R15, A1
+		POP			R15
+
+		/* Accumulator high 32 bits. */
+		MVTACHI		R15, A1
+		POP			R15
+
+		/* Accumulator guard. */
+		MVTACGU		R15, A1
+		POP			R15
+
+		/* Floating point status word. */
+		MVTC		R15, FPSW
+
+		/* R1 to R15 - R0 is not included as it is the SP. */
+		POPM		R1-R15
+
+		/* This pops the remaining registers. */
+		RTE
+		NOP
+		NOP
+
+/*-----------------------------------------------------------*/
+
+/* The software interrupt - overwrite the default 'weak' definition. */
+___interrupt_27:
+
+		/* Re-enable interrupts. */
+		SETPSW		I
+
+		/* Move the data that was automatically pushed onto the interrupt stack when
+		the interrupt occurred from the interrupt stack to the user stack.
+
+		R15 is saved before it is clobbered. */
+		PUSH.L		R15
+
+		/* Read the user stack pointer. */
+		MVFC		USP, R15
+
+		/* Move the address down to the data being moved. */
+		SUB		#12, R15
+		MVTC		R15, USP
+
+		/* Copy the data across, R15, then PC, then PSW. */
+		MOV.L		[ R0 ], [ R15 ]
+		MOV.L 		4[ R0 ], 4[ R15 ]
+		MOV.L		8[ R0 ], 8[ R15 ]
+
+		/* Move the interrupt stack pointer to its new correct position. */
+		ADD		#12, R0
+
+		/* All the rest of the registers are saved directly to the user stack. */
+		SETPSW		U
+
+		/* Save the rest of the general registers (R15 has been saved already). */
+		PUSHM		R1-R14
+
+		/* Save the FPSW and accumulator. */
+		MVFC		FPSW, R15
+		PUSH.L		R15
+		MVFACGU		#0, A1, R15
+		PUSH.L		R15
+		MVFACHI		#0, A1, R15
+		PUSH.L		R15
+		/* Low order word. */
+		MVFACLO		#0, A1, R15
+		PUSH.L		R15
+		MVFACGU		#0, A0, R15
+		PUSH.L		R15
+		MVFACHI		#0, A0, R15
+		PUSH.L		R15
+		/* Low order word. */
+		MVFACLO		#0, A0, R15
+		PUSH.L		R15
+
+		/* Save the stack pointer to the TCB. */
+		MOV.L		#_pxCurrentTCB, R15
+		MOV.L		[ R15 ], R15
+		MOV.L		R0, [ R15 ]
+
+		/* Ensure the interrupt mask is set to the syscall priority while the kernel
+		structures are being accessed. */
+		MVTIPL		#configMAX_SYSCALL_INTERRUPT_PRIORITY
+
+		/* Select the next task to run. */
+		BSR.A		_vTaskSwitchContext
+
+		/* Reset the interrupt mask as no more data structure access is required. */
+		MVTIPL		#configKERNEL_INTERRUPT_PRIORITY
+
+		/* Load the stack pointer of the task that is now selected as the Running
+		state task from its TCB. */
+		MOV.L		#_pxCurrentTCB,R15
+		MOV.L		[ R15 ], R15
+		MOV.L		[ R15 ], R0
+
+		/* Restore the context of the new task.  The PSW (Program Status Word) and
+		PC will be popped by the RTE instruction. */
+		POP		R15
+
+		/* Accumulator low 32 bits. */
+		MVTACLO	R15, A0
+		POP		R15
+
+		/* Accumulator high 32 bits. */
+		MVTACHI	R15, A0
+		POP		R15
+
+		/* Accumulator guard. */
+		MVTACGU	R15, A0
+		POP		R15
+
+		/* Accumulator low 32 bits. */
+		MVTACLO	R15, A1
+		POP		R15
+
+		/* Accumulator high 32 bits. */
+		MVTACHI	R15, A1
+		POP		R15
+
+		/* Accumulator guard. */
+		MVTACGU	R15, A1
+		POP		R15
+		MVTC		R15, FPSW
+		POPM		R1-R15
+		RTE
+		NOP
+		NOP
+
+/*-----------------------------------------------------------*/
+
+		END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h
new file mode 100644
index 0000000..6a0602a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h
@@ -0,0 +1,144 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include <intrinsics.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()					__no_operation()
+
+/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
+where portITU_SWINTR is the location of the software interrupt register
+(0x000872E0).  Don't rely on the assembler to select a register, so instead
+save and restore clobbered registers manually. */
+#define portYIELD()							\
+	__asm volatile 							\
+	(										\
+		"PUSH.L	R10					\n"		\
+		"MOV.L	#0x872E0, R10		\n"		\
+		"MOV.B	#0x1, [R10]			\n"		\
+		"MOV.L	[R10], R10			\n"		\
+		"POP	R10					\n"		\
+	)
+
+#define portYIELD_FROM_ISR( x )	if( ( x ) != pdFALSE ) portYIELD()
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) 0 )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+	#define portDISABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+/* Prevent warnings of undefined behaviour: the order of volatile accesses is
+undefined - all warnings have been manually checked and are not an issue, and
+the warnings cannot be prevent by code changes without undesirable effects. */
+#pragma diag_suppress=Pa082
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RXv2/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RXv2/readme.txt
new file mode 100644
index 0000000..9e89a09
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/RXv2/readme.txt
@@ -0,0 +1,72 @@
+The following table shows which port is recommended to be used.
+
+
+RX MCU Group    CPU     FPU         FPU         Port Layer
+                Core    (Single     (Double     CC-RX                   GNURX               ICCRX (*6)
+                Type    Precision)  Precision)
+
+RX110           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX111           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX113           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX130           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX13T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+
+RX210           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX21A           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX220           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX230,RX231     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23E-A         RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23W           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24U           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+
+RX610           RXv1    Yes         ---         N/A (*4)                N/A (*4)            N/A (*4)
+RX62N,RX621     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX630           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX634           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63N,RX631     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX64M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX65N,RX651     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX66N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX62T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX62G           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX66T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+RX71M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX72M           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+Notes:
+
+*1: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide
+the configuration function.  Please be aware that port.c is hard coded to use CMT0 though it seems to be
+configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*2: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is used, please modify port.c for the configuration.  Please be aware that port.c is
+hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of
+configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*3: RX100 ports are also available.
+
+*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction.
+
+*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
+
+#define configUSE_TASK_DPFPU_SUPPORT            0
+
+*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port.
+It contains two definitions of interrupt priority like the following.
+
+#define configKERNEL_INTERRUPT_PRIORITY         1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY    4
+
+
+For more information about Renesas RX MCUs, please visit the following URL:
+
+https://www.renesas.com/products/microcontrollers-microprocessors/rx.html
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR71x/ISR_Support.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR71x/ISR_Support.h
new file mode 100644
index 0000000..f16c592
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR71x/ISR_Support.h
@@ -0,0 +1,105 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	EXTERN pxCurrentTCB
+	EXTERN ulCriticalNesting
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+portSAVE_CONTEXT MACRO
+
+	; Push R0 as we are going to use the register.
+	STMDB	SP!, {R0}
+
+	; Set R0 to point to the task stack pointer.
+	STMDB	SP, {SP}^
+	NOP
+	SUB		SP, SP, #4
+	LDMIA	SP!, {R0}
+
+	; Push the return address onto the stack.
+	STMDB	R0!, {LR}
+
+	; Now we have saved LR we can use it instead of R0.
+	MOV		LR, R0
+
+	; Pop R0 so we can save it onto the system mode stack.
+	LDMIA	SP!, {R0}
+
+	; Push all the system mode registers onto the task stack.
+	STMDB	LR, {R0-LR}^
+	NOP
+	SUB		LR, LR, #60
+
+	; Push the SPSR onto the task stack.
+	MRS		R0, SPSR
+	STMDB	LR!, {R0}
+
+	LDR		R0, =ulCriticalNesting
+	LDR		R0, [R0]
+	STMDB	LR!, {R0}
+
+	; Store the new top of stack for the task.
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	STR		LR, [R0]
+
+	ENDM
+
+
+portRESTORE_CONTEXT MACRO
+
+	; Set the LR to the task stack.
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	LDR		LR, [R0]
+
+	; The critical nesting depth is the first item on the stack.
+	; Load it into the ulCriticalNesting variable.
+	LDR		R0, =ulCriticalNesting
+	LDMFD	LR!, {R1}
+	STR		R1, [R0]
+
+	; Get the SPSR from the stack.
+	LDMFD	LR!, {R0}
+	MSR		SPSR_cxsf, R0
+
+	; Restore all system mode registers for the task.
+	LDMFD	LR, {R0-R14}^
+	NOP
+
+	; Restore the return address.
+	LDR		LR, [LR, #+60]
+
+	; And return - correcting the offset in the LR to obtain the
+	; correct address.
+	SUBS	PC, LR, #4
+
+	ENDM
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR71x/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR71x/port.c
new file mode 100644
index 0000000..88a1a21
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR71x/port.c
@@ -0,0 +1,258 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ST STR71x ARM7
+ * port.
+ *----------------------------------------------------------*/
+
+/* Library includes. */
+#include "wdg.h"
+#include "eic.h"
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the initial stack. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
+
+#define portMICROS_PER_SECOND 1000000
+
+/*-----------------------------------------------------------*/
+
+/* Setup the watchdog to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* ulCriticalNesting will get set to zero when the first task starts.  It
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
+uint32_t ulCriticalNesting = ( uint32_t ) 9999;
+
+/* Tick interrupt routines for cooperative and preemptive operation
+respectively.  The preemptive version is not defined as __irq as it is called
+from an asm wrapper function. */
+__arm __irq void vPortNonPreemptiveTick( void );
+void vPortPreemptiveTick( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The status register is set for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+	
+	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}		
+	
+	pxTopOfStack--;
+
+	/* Interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+
+	return pxTopOfStack;	
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/* The cooperative scheduler requires a normal IRQ service routine to
+simply increment the system tick. */
+__arm __irq void vPortNonPreemptiveTick( void )
+{
+	/* Increment the tick count - which may wake some tasks but as the
+	preemptive scheduler is not being used any woken task is not given
+	processor time no matter what its priority. */
+	xTaskIncrementTick();
+
+	/* Clear the interrupt in the watchdog and EIC. */
+	WDG->SR = 0x0000;
+	portCLEAR_EIC();		
+}
+/*-----------------------------------------------------------*/
+
+/* This function is called from an asm wrapper, so does not require the __irq
+keyword. */
+void vPortPreemptiveTick( void )
+{
+	/* Increment the tick counter. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		/* Select a new task to execute. */
+		vTaskSwitchContext();
+	}
+
+	/* Clear the interrupt in the watchdog and EIC. */
+	WDG->SR = 0x0000;
+	portCLEAR_EIC();			
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	/* Set the watchdog up to generate a periodic tick. */
+	WDG_ECITConfig( DISABLE );
+	WDG_CntOnOffConfig( DISABLE );
+	WDG_PeriodValueConfig( portMICROS_PER_SECOND / configTICK_RATE_HZ );
+
+	/* Setup the tick interrupt in the EIC. */
+	EIC_IRQChannelPriorityConfig( WDG_IRQChannel, 1 );
+	EIC_IRQChannelConfig( WDG_IRQChannel, ENABLE );
+	EIC_IRQConfig( ENABLE );
+	WDG_ECITConfig( ENABLE );
+
+	/* Start the timer - interrupts are actually disabled at this point so
+	it is safe to do this here. */
+	WDG_CntOnOffConfig( ENABLE );
+}
+/*-----------------------------------------------------------*/
+
+__arm __interwork void vPortEnterCritical( void )
+{
+	/* Disable interrupts first! */
+	__disable_interrupt();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+__arm __interwork void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			__enable_interrupt();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR71x/portasm.s79 b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR71x/portasm.s79
new file mode 100644
index 0000000..943b814
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR71x/portasm.s79
@@ -0,0 +1,76 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+		RSEG ICODE:CODE
+		CODE32
+
+	EXTERN vPortPreemptiveTick
+	EXTERN vTaskSwitchContext
+
+	PUBLIC vPortYieldProcessor
+	PUBLIC vPortStartFirstTask
+	PUBLIC vPortPreemptiveTickISR
+
+#include "ISR_Support.h"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Starting the first task is just a matter of restoring the context that
+; was created by pxPortInitialiseStack().
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Manual context switch function.  This is the SWI hander.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortYieldProcessor:
+	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
+								; as if the context was saved during and IRQ
+								; handler.
+
+	portSAVE_CONTEXT			; Save the context of the current task...
+	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
+	mov     lr, pc
+	BX R0
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Preemptive context switch function.  This will only ever get used if
+; portUSE_PREEMPTION is set to 1 in portmacro.h.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortPreemptiveTickISR:
+	portSAVE_CONTEXT			; Save the context of the current task.
+
+	LDR R0, =vPortPreemptiveTick ; Increment the tick count - this may wake a task.
+	MOV lr, pc
+	BX R0
+
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+
+
+	END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR71x/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR71x/portmacro.h
new file mode 100644
index 0000000..5e75a1d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR71x/portmacro.h
@@ -0,0 +1,121 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+#include <intrinsics.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portYIELD()					asm ( "SWI 0" )
+#define portNOP()					asm ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+__arm __interwork void vPortDisableInterruptsFromThumb( void );
+__arm __interwork void vPortEnableInterruptsFromThumb( void );
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()	__disable_interrupt()
+#define portENABLE_INTERRUPTS()		__enable_interrupt()
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
+{													\
+extern void vTaskSwitchContext( void );				\
+													\
+	if( xSwitchRequired ) 							\
+	{												\
+		vTaskSwitchContext();						\
+	}												\
+}
+/*-----------------------------------------------------------*/
+
+/* EIC utilities. */
+#define portEIC_CICR_ADDR		*( ( uint32_t * ) 0xFFFFF804 )
+#define portEIC_IPR_ADDR		*( ( uint32_t * ) 0xFFFFF840 )
+#define portCLEAR_EIC()			portEIC_IPR_ADDR = 0x01 << portEIC_CICR_ADDR
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR75x/ISR_Support.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR75x/ISR_Support.h
new file mode 100644
index 0000000..f16c592
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR75x/ISR_Support.h
@@ -0,0 +1,105 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	EXTERN pxCurrentTCB
+	EXTERN ulCriticalNesting
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+portSAVE_CONTEXT MACRO
+
+	; Push R0 as we are going to use the register.
+	STMDB	SP!, {R0}
+
+	; Set R0 to point to the task stack pointer.
+	STMDB	SP, {SP}^
+	NOP
+	SUB		SP, SP, #4
+	LDMIA	SP!, {R0}
+
+	; Push the return address onto the stack.
+	STMDB	R0!, {LR}
+
+	; Now we have saved LR we can use it instead of R0.
+	MOV		LR, R0
+
+	; Pop R0 so we can save it onto the system mode stack.
+	LDMIA	SP!, {R0}
+
+	; Push all the system mode registers onto the task stack.
+	STMDB	LR, {R0-LR}^
+	NOP
+	SUB		LR, LR, #60
+
+	; Push the SPSR onto the task stack.
+	MRS		R0, SPSR
+	STMDB	LR!, {R0}
+
+	LDR		R0, =ulCriticalNesting
+	LDR		R0, [R0]
+	STMDB	LR!, {R0}
+
+	; Store the new top of stack for the task.
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	STR		LR, [R0]
+
+	ENDM
+
+
+portRESTORE_CONTEXT MACRO
+
+	; Set the LR to the task stack.
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	LDR		LR, [R0]
+
+	; The critical nesting depth is the first item on the stack.
+	; Load it into the ulCriticalNesting variable.
+	LDR		R0, =ulCriticalNesting
+	LDMFD	LR!, {R1}
+	STR		R1, [R0]
+
+	; Get the SPSR from the stack.
+	LDMFD	LR!, {R0}
+	MSR		SPSR_cxsf, R0
+
+	; Restore all system mode registers for the task.
+	LDMFD	LR, {R0-R14}^
+	NOP
+
+	; Restore the return address.
+	LDR		LR, [LR, #+60]
+
+	; And return - correcting the offset in the LR to obtain the
+	; correct address.
+	SUBS	PC, LR, #4
+
+	ENDM
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR75x/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR75x/port.c
new file mode 100644
index 0000000..49871fe
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR75x/port.c
@@ -0,0 +1,237 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ST STR75x ARM7
+ * port.
+ *----------------------------------------------------------*/
+
+/* Library includes. */
+#include "75x_tb.h"
+#include "75x_eic.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the initial stack. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
+
+/* Prescale used on the timer clock when calculating the tick period. */
+#define portPRESCALE 20
+
+
+/*-----------------------------------------------------------*/
+
+/* Setup the TB to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* ulCriticalNesting will get set to zero when the first task starts.  It
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
+uint32_t ulCriticalNesting = ( uint32_t ) 9999;
+
+/* Tick interrupt routines for preemptive operation. */
+__arm void vPortPreemptiveTick( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The status register is set for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+	pxTopOfStack--;
+
+	/* Interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+
+	return pxTopOfStack;	
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+__arm void vPortPreemptiveTick( void )
+{
+	/* Increment the tick counter. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		/* Select a new task to execute. */
+		vTaskSwitchContext();
+	}
+		
+	TB_ClearITPendingBit( TB_IT_Update );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+EIC_IRQInitTypeDef  EIC_IRQInitStructure;	
+TB_InitTypeDef      TB_InitStructure;
+
+	/* Setup the EIC for the TB. */
+	EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
+	EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
+	EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
+	EIC_IRQInit(&EIC_IRQInitStructure);
+	
+	/* Setup the TB for the generation of the tick interrupt. */
+	TB_InitStructure.TB_Mode = TB_Mode_Timing;
+	TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
+	TB_InitStructure.TB_Prescaler = portPRESCALE - 1;
+	TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ );
+	TB_Init(&TB_InitStructure);
+	
+	/* Enable TB Update interrupt */
+	TB_ITConfig(TB_IT_Update, ENABLE);
+
+	/* Clear TB Update interrupt pending bit */
+	TB_ClearITPendingBit(TB_IT_Update);
+
+	/* Enable TB */
+	TB_Cmd(ENABLE);
+}
+/*-----------------------------------------------------------*/
+
+__arm __interwork void vPortEnterCritical( void )
+{
+	/* Disable interrupts first! */
+	__disable_interrupt();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+__arm __interwork void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			__enable_interrupt();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR75x/portasm.s79 b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR75x/portasm.s79
new file mode 100644
index 0000000..df40a70
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR75x/portasm.s79
@@ -0,0 +1,63 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	RSEG ICODE:CODE
+	CODE32
+
+	EXTERN vPortPreemptiveTick
+	EXTERN vTaskSwitchContext
+
+	PUBLIC vPortYieldProcessor
+	PUBLIC vPortStartFirstTask
+
+#include "ISR_Support.h"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Starting the first task is just a matter of restoring the context that
+; was created by pxPortInitialiseStack().
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Manual context switch function.  This is the SWI hander.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortYieldProcessor:
+	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
+								; as if the context was saved during and IRQ
+								; handler.
+
+	portSAVE_CONTEXT			; Save the context of the current task...
+	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
+	mov     lr, pc
+	BX R0
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+
+
+
+	END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR75x/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR75x/portmacro.h
new file mode 100644
index 0000000..89652b1
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR75x/portmacro.h
@@ -0,0 +1,112 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+#include <intrinsics.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portYIELD()					asm ( "SWI 0" )
+#define portNOP()					asm ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()	__disable_interrupt()
+#define portENABLE_INTERRUPTS()		__enable_interrupt()
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
+{													\
+extern void vTaskSwitchContext( void );				\
+													\
+	if( xSwitchRequired ) 							\
+	{												\
+		vTaskSwitchContext();						\
+	}												\
+}
+/*-----------------------------------------------------------*/
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR91x/ISR_Support.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR91x/ISR_Support.h
new file mode 100644
index 0000000..a4f3544
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR91x/ISR_Support.h
@@ -0,0 +1,105 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN ulCriticalNesting
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+portSAVE_CONTEXT MACRO
+
+	; Push R0 as we are going to use the register. 					
+	STMDB	SP!, {R0}
+
+	; Set R0 to point to the task stack pointer. 					
+	STMDB	SP, {SP}^
+	NOP
+	SUB		SP, SP, #4
+	LDMIA	SP!, {R0}
+
+	; Push the return address onto the stack. 						
+	STMDB	R0!, {LR}
+
+	; Now we have saved LR we can use it instead of R0. 				
+	MOV		LR, R0
+
+	; Pop R0 so we can save it onto the system mode stack. 			
+	LDMIA	SP!, {R0}
+
+	; Push all the system mode registers onto the task stack. 		
+	STMDB	LR, {R0-LR}^
+	NOP
+	SUB		LR, LR, #60
+
+	; Push the SPSR onto the task stack. 							
+	MRS		R0, SPSR
+	STMDB	LR!, {R0}
+
+	LDR		R0, =ulCriticalNesting 
+	LDR		R0, [R0]
+	STMDB	LR!, {R0}
+
+	; Store the new top of stack for the task. 						
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	STR		LR, [R0]
+
+	ENDM
+
+
+portRESTORE_CONTEXT MACRO
+
+	; Set the LR to the task stack. 									
+	LDR		R1, =pxCurrentTCB
+	LDR		R0, [R1]
+	LDR		LR, [R0]
+
+	; The critical nesting depth is the first item on the stack. 	
+	; Load it into the ulCriticalNesting variable. 					
+	LDR		R0, =ulCriticalNesting
+	LDMFD	LR!, {R1}
+	STR		R1, [R0]
+
+	; Get the SPSR from the stack. 									
+	LDMFD	LR!, {R0}
+	MSR		SPSR_cxsf, R0
+
+	; Restore all system mode registers for the task. 				
+	LDMFD	LR, {R0-R14}^
+	NOP
+
+	; Restore the return address. 									
+	LDR		LR, [LR, #+60]
+
+	; And return - correcting the offset in the LR to obtain the 	
+	; correct address. 												
+	SUBS	PC, LR, #4
+
+	ENDM
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR91x/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR91x/port.c
new file mode 100644
index 0000000..59cd0a7
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR91x/port.c
@@ -0,0 +1,421 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ST STR91x ARM9
+ * port.
+ *----------------------------------------------------------*/
+
+/* Library includes. */
+#include "91x_lib.h"
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <assert.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configUSE_WATCHDOG_TICK
+	#error configUSE_WATCHDOG_TICK must be set to either 1 or 0 in FreeRTOSConfig.h to use either the Watchdog or timer 2 to generate the tick interrupt respectively.
+#endif
+
+/* Constants required to setup the initial stack. */
+#ifndef _RUN_TASK_IN_ARM_MODE_
+	#define portINITIAL_SPSR			( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
+#else
+	#define portINITIAL_SPSR 			( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#endif
+
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+
+/* Constants required to handle critical sections. */
+#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
+
+#ifndef abs
+	#define abs(x) ((x)>0 ? (x) : -(x))
+#endif
+
+/**
+ * Toggle a led using the following algorithm:
+ * if ( GPIO_ReadBit(GPIO9, GPIO_Pin_2) )
+ * {
+ *   GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET );
+ * }
+ * else
+ * {
+ *   GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET );
+ * }
+ *
+ */
+#define TOGGLE_LED(port,pin) 									\
+	if ( ((((port)->DR[(pin)<<2])) & (pin)) != Bit_RESET ) 		\
+	{															\
+    	(port)->DR[(pin) <<2] = 0x00;							\
+  	}															\
+  	else														\
+	{															\
+    	(port)->DR[(pin) <<2] = (pin);							\
+  	}
+
+
+/*-----------------------------------------------------------*/
+
+/* Setup the watchdog to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* ulCriticalNesting will get set to zero when the first task starts.  It
+cannot be initialised to 0 as this will cause interrupts to be enabled
+during the kernel initialisation process. */
+uint32_t ulCriticalNesting = ( uint32_t ) 9999;
+
+/* Tick interrupt routines for cooperative and preemptive operation
+respectively.  The preemptive version is not defined as __irq as it is called
+from an asm wrapper function. */
+void WDG_IRQHandler( void );
+
+/* VIC interrupt default handler. */
+static void prvDefaultHandler( void );
+
+#if configUSE_WATCHDOG_TICK == 0
+	/* Used to update the OCR timer register */
+	static u16 s_nPulseLength;
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a task to look exactly as if a call to
+ * portSAVE_CONTEXT had been called.
+ *
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	StackType_t *pxOriginalTOS;
+
+	pxOriginalTOS = pxTopOfStack;
+
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro. */
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+
+	/* When the task starts is will expect to find the function parameter in
+	R0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The status register is set for system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+	pxTopOfStack--;
+
+	/* Interrupt flags cannot always be stored on the stack and will
+	instead be stored in a variable, which is then saved as part of the
+	tasks context. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+
+	return pxTopOfStack;	
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task. */
+	vPortStartFirstTask();	
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  */
+}
+/*-----------------------------------------------------------*/
+
+/* This function is called from an asm wrapper, so does not require the __irq
+keyword. */
+#if configUSE_WATCHDOG_TICK == 1
+
+	static void prvFindFactors(u32 n, u16 *a, u32 *b)
+	{
+		/* This function is copied from the ST STR7 library and is
+		copyright STMicroelectronics.  Reproduced with permission. */
+	
+		u32 b0;
+		u16 a0;
+		int32_t err, err_min=n;
+	
+		*a = a0 = ((n-1)/65536ul) + 1;
+		*b = b0 = n / *a;
+	
+		for (; *a <= 256; (*a)++)
+		{
+			*b = n / *a;
+			err = (int32_t)*a * (int32_t)*b - (int32_t)n;
+			if (abs(err) > (*a / 2))
+			{
+				(*b)++;
+				err = (int32_t)*a * (int32_t)*b - (int32_t)n;
+			}
+			if (abs(err) < abs(err_min))
+			{
+				err_min = err;
+				a0 = *a;
+				b0 = *b;
+				if (err == 0) break;
+			}
+		}
+	
+		*a = a0;
+		*b = b0;
+	}
+	/*-----------------------------------------------------------*/
+
+	static void prvSetupTimerInterrupt( void )
+	{
+	WDG_InitTypeDef xWdg;
+	uint16_t a;
+	uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b;
+	
+		/* Configure the watchdog as a free running timer that generates a
+		periodic interrupt. */
+	
+		SCU_APBPeriphClockConfig( __WDG, ENABLE );
+		WDG_DeInit();
+		WDG_StructInit(&xWdg);
+		prvFindFactors( n, &a, &b );
+		xWdg.WDG_Prescaler = a - 1;
+		xWdg.WDG_Preload = b - 1;
+		WDG_Init( &xWdg );
+		WDG_ITConfig(ENABLE);
+		
+		/* Configure the VIC for the WDG interrupt. */
+		VIC_Config( WDG_ITLine, VIC_IRQ, 10 );
+		VIC_ITCmd( WDG_ITLine, ENABLE );
+		
+		/* Install the default handlers for both VIC's. */
+		VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
+		VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
+		
+		WDG_Cmd(ENABLE);
+	}
+	/*-----------------------------------------------------------*/
+
+	void WDG_IRQHandler( void )
+	{
+		{
+			/* Increment the tick counter. */
+			if( xTaskIncrementTick() != pdFALSE )
+			{		
+				/* Select a new task to execute. */
+				vTaskSwitchContext();
+			}
+		
+			/* Clear the interrupt in the watchdog. */
+			WDG->SR &= ~0x0001;
+		}
+	}
+
+#else
+
+	static void prvFindFactors(u32 n, u8 *a, u16 *b)
+	{
+		/* This function is copied from the ST STR7 library and is
+		copyright STMicroelectronics.  Reproduced with permission. */
+	
+		u16 b0;
+		u8 a0;
+		int32_t err, err_min=n;
+	
+	
+		*a = a0 = ((n-1)/256) + 1;
+		*b = b0 = n / *a;
+	
+		for (; *a <= 256; (*a)++)
+		{
+			*b = n / *a;
+			err = (int32_t)*a * (int32_t)*b - (int32_t)n;
+			if (abs(err) > (*a / 2))
+			{
+				(*b)++;
+				err = (int32_t)*a * (int32_t)*b - (int32_t)n;
+			}
+			if (abs(err) < abs(err_min))
+			{
+				err_min = err;
+				a0 = *a;
+				b0 = *b;
+				if (err == 0) break;
+			}
+		}
+	
+		*a = a0;
+		*b = b0;
+	}
+	/*-----------------------------------------------------------*/
+
+	static void prvSetupTimerInterrupt( void )
+	{
+		uint8_t a;
+		uint16_t b;
+		uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ;
+		
+		TIM_InitTypeDef timer;
+		
+		SCU_APBPeriphClockConfig( __TIM23, ENABLE );
+		TIM_DeInit(TIM2);
+		TIM_StructInit(&timer);
+		prvFindFactors( n, &a, &b );
+		
+		timer.TIM_Mode           = TIM_OCM_CHANNEL_1;
+		timer.TIM_OC1_Modes      = TIM_TIMING;
+		timer.TIM_Clock_Source   = TIM_CLK_APB;
+		timer.TIM_Clock_Edge     = TIM_CLK_EDGE_RISING;
+		timer.TIM_Prescaler      = a-1;
+		timer.TIM_Pulse_Level_1  = TIM_HIGH;
+		timer.TIM_Pulse_Length_1 = s_nPulseLength  = b-1;
+		
+		TIM_Init (TIM2, &timer);
+		TIM_ITConfig(TIM2, TIM_IT_OC1, ENABLE);
+		/* Configure the VIC for the WDG interrupt. */
+		VIC_Config( TIM2_ITLine, VIC_IRQ, 10 );
+		VIC_ITCmd( TIM2_ITLine, ENABLE );
+		
+		/* Install the default handlers for both VIC's. */
+		VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
+		VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
+		
+		TIM_CounterCmd(TIM2, TIM_CLEAR);
+		TIM_CounterCmd(TIM2, TIM_START);
+	}
+	/*-----------------------------------------------------------*/
+
+	void TIM2_IRQHandler( void )
+	{
+		/* Reset the timer counter to avioid overflow. */
+		TIM2->OC1R += s_nPulseLength;
+		
+		/* Increment the tick counter. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Select a new task to run. */
+			vTaskSwitchContext();
+		}
+		
+		/* Clear the interrupt in the watchdog. */
+		TIM2->SR &= ~TIM_FLAG_OC1;
+	}
+
+#endif /* USE_WATCHDOG_TICK */
+
+/*-----------------------------------------------------------*/
+
+__arm __interwork void vPortEnterCritical( void )
+{
+	/* Disable interrupts first! */
+	portDISABLE_INTERRUPTS();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+__arm __interwork void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			portENABLE_INTERRUPTS();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvDefaultHandler( void )
+{
+}
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR91x/portasm.s79 b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR91x/portasm.s79
new file mode 100644
index 0000000..146d8d7
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR91x/portasm.s79
@@ -0,0 +1,60 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+		RSEG ICODE:CODE
+		CODE32
+
+	EXTERN vTaskSwitchContext
+
+	PUBLIC vPortYieldProcessor
+	PUBLIC vPortStartFirstTask
+
+#include "ISR_Support.h"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Starting the first task is just a matter of restoring the context that
+; was created by pxPortInitialiseStack().
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortStartFirstTask:
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Manual context switch function.  This is the SWI hander.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortYieldProcessor:
+	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
+								; as if the context was saved during and IRQ
+								; handler.
+								
+	portSAVE_CONTEXT			; Save the context of the current task...
+	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
+	MOV     lr, pc
+	BX R0
+	portRESTORE_CONTEXT			; Restore the context of the selected task.
+
+	END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR91x/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR91x/portmacro.h
new file mode 100644
index 0000000..4940934
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/STR91x/portmacro.h
@@ -0,0 +1,114 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+#include <intrinsics.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Type definitions. */
+#define portCHAR			char
+#define portFLOAT			float
+#define portDOUBLE			double
+#define portLONG			long
+#define portSHORT			short
+#define portSTACK_TYPE		uint32_t
+#define portBASE_TYPE		long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+#define portYIELD()					asm ( "SWI 0" )
+#define portNOP()					asm ( "NOP" )
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+__arm __interwork void vPortEnterCritical( void );
+__arm __interwork void vPortExitCritical( void );
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+
+#define portDISABLE_INTERRUPTS()	__disable_interrupt()
+#define portENABLE_INTERRUPTS()		__enable_interrupt()
+
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
+{													\
+extern void vTaskSwitchContext( void );				\
+													\
+	if( xSwitchRequired ) 							\
+	{												\
+		vTaskSwitchContext();						\
+	}												\
+}
+/*-----------------------------------------------------------*/
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/ISR_Support.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/ISR_Support.h
new file mode 100644
index 0000000..f1f97ee
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/ISR_Support.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+	EXTERN pxCurrentTCB
+	EXTERN usCriticalNesting
+
+#include "FreeRTOSConfig.h"
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Context save and restore macro definitions
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+portSAVE_CONTEXT MACRO
+
+    add     -0x0C,sp			; prepare stack to save necessary values
+    st.w    lp,8[sp]			; store LP to stack
+    stsr    0,r31
+    st.w    lp,4[sp]			; store EIPC to stack
+    stsr    1,lp
+    st.w    lp,0[sp]			; store EIPSW to stack
+#if configDATA_MODE == 1                                        ; Using the Tiny data model
+    prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers
+    sst.w   r19,72[ep]
+    sst.w   r18,68[ep]
+    sst.w   r17,64[ep]
+    sst.w   r16,60[ep]
+    sst.w   r15,56[ep]
+    sst.w   r14,52[ep]
+    sst.w   r13,48[ep]
+    sst.w   r12,44[ep]
+    sst.w   r11,40[ep]
+    sst.w   r10,36[ep]
+    sst.w   r9,32[ep]
+    sst.w   r8,28[ep]
+    sst.w   r7,24[ep]
+    sst.w   r6,20[ep]
+    sst.w   r5,16[ep]
+    sst.w   r4,12[ep]
+#else                                                           ; Using the Small/Large data model
+    prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp     ; save general purpose registers
+    sst.w   r19,68[ep]
+    sst.w   r18,64[ep]
+    sst.w   r17,60[ep]
+    sst.w   r16,56[ep]
+    sst.w   r15,52[ep]
+    sst.w   r14,48[ep]
+    sst.w   r13,44[ep]
+    sst.w   r12,40[ep]
+    sst.w   r11,36[ep]
+    sst.w   r10,32[ep]
+    sst.w   r9,28[ep]
+    sst.w   r8,24[ep]
+    sst.w   r7,20[ep]
+    sst.w   r6,16[ep]
+    sst.w   r5,12[ep]
+#endif /* configDATA_MODE */
+    sst.w   r2,8[ep]
+    sst.w   r1,4[ep]
+    MOVHI   hi1(usCriticalNesting),r0,r1	; save usCriticalNesting value to stack
+    ld.w    lw1(usCriticalNesting)[r1],r2
+    sst.w   r2,0[ep]
+    MOVHI   hi1(pxCurrentTCB),r0,r1			; save SP to top of current TCB
+    ld.w    lw1(pxCurrentTCB)[r1],r2
+    st.w    sp,0[r2]
+    ENDM
+
+
+portRESTORE_CONTEXT MACRO
+
+    MOVHI   hi1(pxCurrentTCB),r0,r1			; get Stackpointer address
+    ld.w    lw1(pxCurrentTCB)[r1],sp
+    MOV     sp,r1
+    ld.w    0[r1],sp						; load stackpointer
+    MOV     sp,ep							; set stack pointer to element pointer
+    sld.w   0[ep],r1						; load usCriticalNesting value from stack
+    MOVHI   hi1(usCriticalNesting),r0,r2
+    st.w    r1,lw1(usCriticalNesting)[r2]
+    sld.w   4[ep],r1						; restore general purpose registers
+    sld.w   8[ep],r2
+#if configDATA_MODE == 1					; Using Tiny data model
+    sld.w   12[ep],r4
+    sld.w   16[ep],r5
+    sld.w   20[ep],r6
+    sld.w   24[ep],r7
+    sld.w   28[ep],r8
+    sld.w   32[ep],r9
+    sld.w   36[ep],r10
+    sld.w   40[ep],r11
+    sld.w   44[ep],r12
+    sld.w   48[ep],r13
+    sld.w   52[ep],r14
+    sld.w   56[ep],r15
+    sld.w   60[ep],r16
+    sld.w   64[ep],r17
+    sld.w   68[ep],r18
+    sld.w   72[ep],r19
+    dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30}
+#else										; Using Small/Large data model
+    sld.w   12[ep],r5
+    sld.w   16[ep],r6
+    sld.w   20[ep],r7
+    sld.w   24[ep],r8
+    sld.w   28[ep],r9
+    sld.w   32[ep],r10
+    sld.w   36[ep],r11
+    sld.w   40[ep],r12
+    sld.w   44[ep],r13
+    sld.w   48[ep],r14
+    sld.w   52[ep],r15
+    sld.w   56[ep],r16
+    sld.w   60[ep],r17
+    sld.w   64[ep],r18
+    sld.w   68[ep],r19
+    dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30}
+#endif /* configDATA_MODE */
+    ld.w    0[sp],lp						; restore EIPSW from stack
+    ldsr    lp,1
+    ld.w    4[sp],lp						; restore EIPC from stack
+    ldsr    lp,0
+    ld.w    8[sp],lp						; restore LP from stack
+    add     0x0C,sp							; set SP to right position
+
+    RETI
+
+    ENDM
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/port.c
new file mode 100644
index 0000000..2172f54
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/port.c
@@ -0,0 +1,183 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Critical nesting should be initialised to a non zero value so interrupts don't
+accidentally get enabled before the scheduler is started. */
+#define portINITIAL_CRITICAL_NESTING  (( StackType_t ) 10)
+
+/* The PSW value assigned to tasks when they start to run for the first time. */
+#define portPSW		  (( StackType_t ) 0x00000000)
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Keeps track of the nesting level of critical sections. */
+volatile StackType_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+/*-----------------------------------------------------------*/
+
+/* Sets up the timer to generate the tick interrupt. */
+static void prvSetupTimerInterrupt( void );
+
+/*-----------------------------------------------------------*/
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	*pxTopOfStack = ( StackType_t ) pxCode;          /* Task function start address */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;          /* Task function start address */
+	pxTopOfStack--;
+	*pxTopOfStack = portPSW;                            /* Initial PSW value */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x20202020;      /* Initial Value of R20 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x21212121;      /* Initial Value of R21 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x22222222;      /* Initial Value of R22 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x23232323;      /* Initial Value of R23 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x24242424;      /* Initial Value of R24 */
+	pxTopOfStack--;
+#if (__DATA_MODEL__ == 0) || (__DATA_MODEL__ == 1)
+	*pxTopOfStack = ( StackType_t ) 0x25252525;      /* Initial Value of R25 */
+	pxTopOfStack--;
+#endif /* configDATA_MODE */
+	*pxTopOfStack = ( StackType_t ) 0x26262626;      /* Initial Value of R26 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x27272727;      /* Initial Value of R27 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x28282828;      /* Initial Value of R28 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x29292929;      /* Initial Value of R29 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x30303030;      /* Initial Value of R30 */
+	pxTopOfStack--; 	
+	*pxTopOfStack = ( StackType_t ) 0x19191919;      /* Initial Value of R19 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x18181818;      /* Initial Value of R18 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x17171717;      /* Initial Value of R17 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x16161616;      /* Initial Value of R16 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x15151515;      /* Initial Value of R15 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x14141414;      /* Initial Value of R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x13131313;      /* Initial Value of R13 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;      /* Initial Value of R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11111111;      /* Initial Value of R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10101010;      /* Initial Value of R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x99999999;      /* Initial Value of R09 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x88888888;      /* Initial Value of R08 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x77777777;      /* Initial Value of R07 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x66666666;      /* Initial Value of R06 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x55555555;      /* Initial Value of R05 */
+	pxTopOfStack--;
+#if __DATA_MODEL__ == 0 || __DATA_MODEL__ == 1
+	*pxTopOfStack = ( StackType_t ) 0x44444444;      /* Initial Value of R04 */
+	pxTopOfStack--;
+#endif /* configDATA_MODE */
+	*pxTopOfStack = ( StackType_t ) 0x22222222;      /* Initial Value of R02 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters;    /* R1 is expected to hold the function parameter*/
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
+
+	/*
+	 * Return a pointer to the top of the stack we have generated so this can
+	 * be stored in the task control block for the task.
+	 */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick.  Interrupts are disabled when
+	this function is called. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run. */
+	vPortStart();
+
+	/* Should not get here as the tasks are now running! */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the V850ES/Fx3 port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.  This uses
+ */
+static void prvSetupTimerInterrupt( void )
+{
+	TM0CE     = 0;	/* TMM0 operation disable */
+	TM0EQMK0  = 1;	/* INTTM0EQ0 interrupt disable */
+	TM0EQIF0  = 0;	/* clear INTTM0EQ0 interrupt flag */
+
+	#ifdef __IAR_V850ES_Fx3__
+	{
+		TM0CMP0   = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1);    /* divided by 2 because peripherals only run at CPU_CLOCK/2 */
+	}
+	#else
+	{
+		TM0CMP0   = (configCPU_CLOCK_HZ / configTICK_RATE_HZ);	
+	}
+	#endif
+
+	TM0EQIC0 &= 0xF8;
+	TM0CTL0   = 0x00;
+	TM0EQIF0 =  0;	/* clear INTTM0EQ0 interrupt flag */
+	TM0EQMK0 =  0;	/* INTTM0EQ0 interrupt enable */
+	TM0CE =     1;	/* TMM0 operation enable */
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/portasm.s85 b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/portasm.s85
new file mode 100644
index 0000000..aca09de
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/portasm.s85
@@ -0,0 +1,315 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+; Note: Select the correct include files for the device used by the application.
+#include "FreeRTOSConfig.h"
+;------------------------------------------------------------------------------
+
+; Functions used by scheduler
+;------------------------------------------------------------------------------
+    EXTERN    vTaskSwitchContext
+    EXTERN    xTaskIncrementTick
+
+; Variables used by scheduler
+;------------------------------------------------------------------------------
+    EXTERN    pxCurrentTCB
+    EXTERN    usCriticalNesting
+
+; Functions implemented in this file
+;------------------------------------------------------------------------------
+    PUBLIC    vPortYield
+    PUBLIC    vPortStart
+
+; Security ID definition
+;------------------------------------------------------------------------------
+#define	CG_SECURITY0	0FFH
+#define	CG_SECURITY1	0FFH
+#define	CG_SECURITY2	0FFH
+#define	CG_SECURITY3	0FFH
+#define	CG_SECURITY4	0FFH
+#define	CG_SECURITY5	0FFH
+#define	CG_SECURITY6	0FFH
+#define	CG_SECURITY7	0FFH
+#define	CG_SECURITY8	0FFH
+#define	CG_SECURITY9	0FFH
+
+; Tick ISR Prototype
+;------------------------------------------------------------------------------
+        PUBWEAK `??MD_INTTM0EQ0??INTVEC 640`
+        PUBLIC MD_INTTM0EQ0
+
+MD_INTTM0EQ0        SYMBOL "MD_INTTM0EQ0"
+`??MD_INTTM0EQ0??INTVEC 640` SYMBOL "??INTVEC 640", MD_INTTM0EQ0
+
+;------------------------------------------------------------------------------
+;   portSAVE_CONTEXT MACRO
+;   Saves the context of the remaining general purpose registers
+;   and the usCriticalNesting Value of the active Task onto the task stack
+;   saves stack pointer to the TCB
+;------------------------------------------------------------------------------
+portSAVE_CONTEXT MACRO
+#if configDATA_MODE == 1                                        ; Using the Tiny data model
+    prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers
+    sst.w   r19,72[ep]
+    sst.w   r18,68[ep]
+    sst.w   r17,64[ep]
+    sst.w   r16,60[ep]
+    sst.w   r15,56[ep]
+    sst.w   r14,52[ep]
+    sst.w   r13,48[ep]
+    sst.w   r12,44[ep]
+    sst.w   r11,40[ep]
+    sst.w   r10,36[ep]
+    sst.w   r9,32[ep]
+    sst.w   r8,28[ep]
+    sst.w   r7,24[ep]
+    sst.w   r6,20[ep]
+    sst.w   r5,16[ep]
+    sst.w   r4,12[ep]
+#else                                                           ; Using the Small/Large data model
+    prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp     ; save general purpose registers
+    sst.w   r19,68[ep]
+    sst.w   r18,64[ep]
+    sst.w   r17,60[ep]
+    sst.w   r16,56[ep]
+    sst.w   r15,52[ep]
+    sst.w   r14,48[ep]
+    sst.w   r13,44[ep]
+    sst.w   r12,40[ep]
+    sst.w   r11,36[ep]
+    sst.w   r10,32[ep]
+    sst.w   r9,28[ep]
+    sst.w   r8,24[ep]
+    sst.w   r7,20[ep]
+    sst.w   r6,16[ep]
+    sst.w   r5,12[ep]
+#endif /* configDATA_MODE */
+    sst.w   r2,8[ep]
+    sst.w   r1,4[ep]
+    MOVHI   hi1(usCriticalNesting),r0,r1                        ; save usCriticalNesting value to stack
+    ld.w    lw1(usCriticalNesting)[r1],r2
+    sst.w   r2,0[ep]
+    MOVHI   hi1(pxCurrentTCB),r0,r1                             ; save SP to top of current TCB
+    ld.w    lw1(pxCurrentTCB)[r1],r2
+    st.w    sp,0[r2]
+    ENDM
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   portRESTORE_CONTEXT MACRO
+;   Gets stack pointer from the current TCB
+;   Restores the context of the usCriticalNesting value and general purpose
+;   registers of the selected task from the task stack
+;------------------------------------------------------------------------------
+portRESTORE_CONTEXT MACRO
+    MOVHI   hi1(pxCurrentTCB),r0,r1         ; get Stackpointer address
+    ld.w    lw1(pxCurrentTCB)[r1],sp
+    MOV     sp,r1
+    ld.w    0[r1],sp                        ; load stackpointer
+    MOV     sp,ep                           ; set stack pointer to element pointer
+    sld.w   0[ep],r1                        ; load usCriticalNesting value from stack
+    MOVHI   hi1(usCriticalNesting),r0,r2
+    st.w    r1,lw1(usCriticalNesting)[r2]
+    sld.w   4[ep],r1                        ; restore general purpose registers
+    sld.w   8[ep],r2
+#if configDATA_MODE == 1                    ; Using Tiny data model
+    sld.w   12[ep],r4
+    sld.w   16[ep],r5
+    sld.w   20[ep],r6
+    sld.w   24[ep],r7
+    sld.w   28[ep],r8
+    sld.w   32[ep],r9
+    sld.w   36[ep],r10
+    sld.w   40[ep],r11
+    sld.w   44[ep],r12
+    sld.w   48[ep],r13
+    sld.w   52[ep],r14
+    sld.w   56[ep],r15
+    sld.w   60[ep],r16
+    sld.w   64[ep],r17
+    sld.w   68[ep],r18
+    sld.w   72[ep],r19
+    dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30}
+#else                                       ; Using Small/Large data model
+    sld.w   12[ep],r5
+    sld.w   16[ep],r6
+    sld.w   20[ep],r7
+    sld.w   24[ep],r8
+    sld.w   28[ep],r9
+    sld.w   32[ep],r10
+    sld.w   36[ep],r11
+    sld.w   40[ep],r12
+    sld.w   44[ep],r13
+    sld.w   48[ep],r14
+    sld.w   52[ep],r15
+    sld.w   56[ep],r16
+    sld.w   60[ep],r17
+    sld.w   64[ep],r18
+    sld.w   68[ep],r19
+    dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30}
+#endif /* configDATA_MODE */
+    ENDM
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Restore the context of the first task that is going to run.
+;
+;   Input:  NONE
+;
+;   Call:   CALL    vPortStart
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+    RSEG CODE:CODE
+vPortStart:
+    portRESTORE_CONTEXT	                    ; Restore the context of whichever task the ...
+    ld.w    0[sp],lp
+    ldsr    lp,5                            ; restore PSW
+    DI
+    ld.w    4[sp],lp                        ; restore LP
+    ld.w    8[sp],lp                        ; restore LP
+    ADD     0x0C,sp                         ; set SP to right position
+    EI
+    jmp     [lp]
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Port Yield function to check for a Task switch in the cooperative and
+;   preemptive mode
+;
+;   Input:  NONE
+;
+;   Call:   CALL    vPortYield
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+
+	RSEG CODE:CODE
+vPortYield:
+
+    add     -0x0C,sp                          ; prepare stack to save necessary values
+    st.w    lp,8[sp]                        ; store LP to stack
+    stsr    0,r31
+    st.w    lp,4[sp]                        ; store EIPC to stack
+    stsr    1,lp
+    st.w    lp,0[sp]                        ; store EIPSW to stack
+    portSAVE_CONTEXT		            ; Save the context of the current task.
+    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
+    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
+                		            ; ... scheduler decided should run.
+	ld.w    0[sp],lp                        ; restore EIPSW from stack
+    ldsr    lp,1
+    ld.w    4[sp],lp                        ; restore EIPC from stack
+    ldsr    lp,0
+    ld.w    8[sp],lp                        ; restore LP from stack
+    add     0x0C,sp                         ; set SP to right position
+
+    RETI
+
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Perform the necessary steps of the Tick Count Increment and Task Switch
+;   depending on the chosen kernel configuration
+;
+;   Input:  NONE
+;
+;   Call:   ISR
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+#if configUSE_PREEMPTION == 1               ; use preemptive kernel mode
+
+MD_INTTM0EQ0:
+
+    add     -0x0C,sp                          ; prepare stack to save necessary values
+    st.w    lp,8[sp]                        ; store LP to stack
+    stsr    0,r31
+    st.w    lp,4[sp]                        ; store EIPC to stack
+    stsr    1,lp
+    st.w    lp,0[sp]                        ; store EIPSW to stack
+    portSAVE_CONTEXT		            ; Save the context of the current task.
+    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
+    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
+    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
+                		            ; ... scheduler decided should run.
+    ld.w    0[sp],lp                        ; restore EIPSW from stack
+    ldsr    lp,1
+    ld.w    4[sp],lp                        ; restore EIPC from stack
+    ldsr    lp,0
+    ld.w    8[sp],lp                        ; restore LP from stack
+    add     0x0C,sp                         ; set SP to right position
+
+    RETI
+;------------------------------------------------------------------------------
+#else                                       ; use cooperative kernel mode
+
+MD_INTTM0EQ0:
+    prepare {lp,ep},8,sp
+    sst.w   r1,4[ep]
+    sst.w   r5,0[ep]
+    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
+    sld.w   0[ep],r5
+    sld.w   4[ep],r1
+    dispose 8,{lp,ep}
+    RETI
+#endif /* configUSE_PREEMPTION */
+
+;------------------------------------------------------------------------------
+        COMMON INTVEC:CODE:ROOT(2)
+        ORG 640
+`??MD_INTTM0EQ0??INTVEC 640`:
+        JR MD_INTTM0EQ0
+
+        RSEG NEAR_ID:CONST:SORT:NOROOT(2)
+`?<Initializer for usCriticalNesting>`:
+        DW 10
+
+      COMMON INTVEC:CODE:ROOT(2)
+      ORG 40H
+`??vPortYield??INTVEC 40`:
+        JR vPortYield
+
+;------------------------------------------------------------------------------
+; set microcontroller security ID
+
+      COMMON INTVEC:CODE:ROOT(2)
+      ORG 70H
+`SECUID`:
+      DB CG_SECURITY0
+      DB CG_SECURITY1
+      DB CG_SECURITY2
+      DB CG_SECURITY3
+      DB CG_SECURITY4
+      DB CG_SECURITY5
+      DB CG_SECURITY6
+      DB CG_SECURITY7
+      DB CG_SECURITY8
+      DB CG_SECURITY9
+
+
+      END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/portasm_Fx3.s85 b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/portasm_Fx3.s85
new file mode 100644
index 0000000..f8cd6f2
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/portasm_Fx3.s85
@@ -0,0 +1,335 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+; Note: Select the correct include files for the device used by the application.
+#include "FreeRTOSConfig.h"
+;------------------------------------------------------------------------------
+
+; Functions used by scheduler
+;------------------------------------------------------------------------------
+    EXTERN    vTaskSwitchContext
+    EXTERN    xTaskIncrementTick
+
+; Variables used by scheduler
+;------------------------------------------------------------------------------
+    EXTERN    pxCurrentTCB
+    EXTERN    usCriticalNesting
+
+; Functions implemented in this file
+;------------------------------------------------------------------------------
+    PUBLIC    vPortYield
+    PUBLIC    vPortStart
+
+; Security ID definition
+;------------------------------------------------------------------------------
+#define	CG_SECURITY0	0FFH
+#define	CG_SECURITY1	0FFH
+#define	CG_SECURITY2	0FFH
+#define	CG_SECURITY3	0FFH
+#define	CG_SECURITY4	0FFH
+#define	CG_SECURITY5	0FFH
+#define	CG_SECURITY6	0FFH
+#define	CG_SECURITY7	0FFH
+#define	CG_SECURITY8	0FFH
+#define	CG_SECURITY9	0FFH
+
+; Option Byte definitions
+;------------------------------------------------------------------------------
+#define	CG_OPTION7A	0x00
+#define	CG_OPTION7B	0x04
+#define	OPT7C		0x00
+#define	OPT7D		0x00
+#define	OPT7E		0x00
+#define	OPT7F		0x00
+
+; Tick ISR Prototype
+;------------------------------------------------------------------------------
+        PUBWEAK `??MD_INTTM0EQ0??INTVEC 608`
+        PUBLIC MD_INTTM0EQ0
+
+MD_INTTM0EQ0        SYMBOL "MD_INTTM0EQ0"
+`??MD_INTTM0EQ0??INTVEC 608` SYMBOL "??INTVEC 608", MD_INTTM0EQ0
+
+;------------------------------------------------------------------------------
+;   portSAVE_CONTEXT MACRO
+;   Saves the context of the remaining general purpose registers
+;   and the usCriticalNesting Value of the active Task onto the task stack
+;   saves stack pointer to the TCB
+;------------------------------------------------------------------------------
+portSAVE_CONTEXT MACRO
+#if configDATA_MODE == 1                                        ; Using the Tiny data model
+    prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers
+    sst.w   r19,72[ep]
+    sst.w   r18,68[ep]
+    sst.w   r17,64[ep]
+    sst.w   r16,60[ep]
+    sst.w   r15,56[ep]
+    sst.w   r14,52[ep]
+    sst.w   r13,48[ep]
+    sst.w   r12,44[ep]
+    sst.w   r11,40[ep]
+    sst.w   r10,36[ep]
+    sst.w   r9,32[ep]
+    sst.w   r8,28[ep]
+    sst.w   r7,24[ep]
+    sst.w   r6,20[ep]
+    sst.w   r5,16[ep]
+    sst.w   r4,12[ep]
+#else                                                           ; Using the Small/Large data model
+    prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp     ; save general purpose registers
+    sst.w   r19,68[ep]
+    sst.w   r18,64[ep]
+    sst.w   r17,60[ep]
+    sst.w   r16,56[ep]
+    sst.w   r15,52[ep]
+    sst.w   r14,48[ep]
+    sst.w   r13,44[ep]
+    sst.w   r12,40[ep]
+    sst.w   r11,36[ep]
+    sst.w   r10,32[ep]
+    sst.w   r9,28[ep]
+    sst.w   r8,24[ep]
+    sst.w   r7,20[ep]
+    sst.w   r6,16[ep]
+    sst.w   r5,12[ep]
+#endif /* configDATA_MODE */
+    sst.w   r2,8[ep]
+    sst.w   r1,4[ep]
+    MOVHI   hi1(usCriticalNesting),r0,r1                        ; save usCriticalNesting value to stack
+    ld.w    lw1(usCriticalNesting)[r1],r2
+    sst.w   r2,0[ep]
+    MOVHI   hi1(pxCurrentTCB),r0,r1                             ; save SP to top of current TCB
+    ld.w    lw1(pxCurrentTCB)[r1],r2
+    st.w    sp,0[r2]
+    ENDM
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   portRESTORE_CONTEXT MACRO
+;   Gets stack pointer from the current TCB
+;   Restores the context of the usCriticalNesting value and general purpose
+;   registers of the selected task from the task stack
+;------------------------------------------------------------------------------
+portRESTORE_CONTEXT MACRO
+    MOVHI   hi1(pxCurrentTCB),r0,r1         ; get Stackpointer address
+    ld.w    lw1(pxCurrentTCB)[r1],sp
+    MOV     sp,r1
+    ld.w    0[r1],sp                        ; load stackpointer
+    MOV     sp,ep                           ; set stack pointer to element pointer
+    sld.w   0[ep],r1                        ; load usCriticalNesting value from stack
+    MOVHI   hi1(usCriticalNesting),r0,r2
+    st.w    r1,lw1(usCriticalNesting)[r2]
+    sld.w   4[ep],r1                        ; restore general purpose registers
+    sld.w   8[ep],r2
+#if configDATA_MODE == 1                    ; Using Tiny data model
+    sld.w   12[ep],r4
+    sld.w   16[ep],r5
+    sld.w   20[ep],r6
+    sld.w   24[ep],r7
+    sld.w   28[ep],r8
+    sld.w   32[ep],r9
+    sld.w   36[ep],r10
+    sld.w   40[ep],r11
+    sld.w   44[ep],r12
+    sld.w   48[ep],r13
+    sld.w   52[ep],r14
+    sld.w   56[ep],r15
+    sld.w   60[ep],r16
+    sld.w   64[ep],r17
+    sld.w   68[ep],r18
+    sld.w   72[ep],r19
+    dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30}
+#else                                       ; Using Small/Large data model
+    sld.w   12[ep],r5
+    sld.w   16[ep],r6
+    sld.w   20[ep],r7
+    sld.w   24[ep],r8
+    sld.w   28[ep],r9
+    sld.w   32[ep],r10
+    sld.w   36[ep],r11
+    sld.w   40[ep],r12
+    sld.w   44[ep],r13
+    sld.w   48[ep],r14
+    sld.w   52[ep],r15
+    sld.w   56[ep],r16
+    sld.w   60[ep],r17
+    sld.w   64[ep],r18
+    sld.w   68[ep],r19
+    dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30}
+#endif /* configDATA_MODE */
+    ENDM
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Restore the context of the first task that is going to run.
+;
+;   Input:  NONE
+;
+;   Call:   CALL    vPortStart
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+    RSEG CODE:CODE
+vPortStart:
+    portRESTORE_CONTEXT	                    ; Restore the context of whichever task the ...
+    ld.w    0[sp],lp
+    ldsr    lp,5                            ; restore PSW
+    DI
+    ld.w    4[sp],lp                        ; restore LP
+    ld.w    8[sp],lp                        ; restore LP
+    ADD     0x0C,sp                         ; set SP to right position
+    EI
+    jmp     [lp]
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Port Yield function to check for a Task switch in the cooperative and
+;   preemptive mode
+;
+;   Input:  NONE
+;
+;   Call:   CALL    vPortYield
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+
+	RSEG CODE:CODE
+vPortYield:
+
+    add     -0x0C,sp                          ; prepare stack to save necessary values
+    st.w    lp,8[sp]                        ; store LP to stack
+    stsr    0,r31
+    st.w    lp,4[sp]                        ; store EIPC to stack
+    stsr    1,lp
+    st.w    lp,0[sp]                        ; store EIPSW to stack
+    portSAVE_CONTEXT		            ; Save the context of the current task.
+    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
+    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
+                		            ; ... scheduler decided should run.
+	ld.w    0[sp],lp                        ; restore EIPSW from stack
+    ldsr    lp,1
+    ld.w    4[sp],lp                        ; restore EIPC from stack
+    ldsr    lp,0
+    ld.w    8[sp],lp                        ; restore LP from stack
+    add     0x0C,sp                         ; set SP to right position
+
+    RETI
+
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Perform the necessary steps of the Tick Count Increment and Task Switch
+;   depending on the chosen kernel configuration
+;
+;   Input:  NONE
+;
+;   Call:   ISR
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+#if configUSE_PREEMPTION == 1               ; use preemptive kernel mode
+
+MD_INTTM0EQ0:
+
+    add     -0x0C,sp                          ; prepare stack to save necessary values
+    st.w    lp,8[sp]                        ; store LP to stack
+    stsr    0,r31
+    st.w    lp,4[sp]                        ; store EIPC to stack
+    stsr    1,lp
+    st.w    lp,0[sp]                        ; store EIPSW to stack
+    portSAVE_CONTEXT		            ; Save the context of the current task.
+    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
+    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
+    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
+                		            ; ... scheduler decided should run.
+    ld.w    0[sp],lp                        ; restore EIPSW from stack
+    ldsr    lp,1
+    ld.w    4[sp],lp                        ; restore EIPC from stack
+    ldsr    lp,0
+    ld.w    8[sp],lp                        ; restore LP from stack
+    add     0x0C,sp                         ; set SP to right position
+
+    RETI
+;------------------------------------------------------------------------------
+#else                                       ; use cooperative kernel mode
+
+MD_INTTM0EQ0:
+    prepare {lp,ep},8,sp
+    sst.w   r1,4[ep]
+    sst.w   r5,0[ep]
+    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
+    sld.w   0[ep],r5
+    sld.w   4[ep],r1
+    dispose 8,{lp,ep}
+    RETI
+#endif /* configUSE_PREEMPTION */
+
+;------------------------------------------------------------------------------
+        COMMON INTVEC:CODE:ROOT(2)
+        ORG 608
+`??MD_INTTM0EQ0??INTVEC 608`:
+        JR MD_INTTM0EQ0
+
+        RSEG NEAR_ID:CONST:SORT:NOROOT(2)
+`?<Initializer for usCriticalNesting>`:
+        DW 10
+
+      COMMON INTVEC:CODE:ROOT(2)
+      ORG 40H
+`??vPortYield??INTVEC 40`:
+        JR vPortYield
+
+;------------------------------------------------------------------------------
+; set microcontroller security ID
+
+      COMMON INTVEC:CODE:ROOT(2)
+      ORG 70H
+`SECUID`:
+      DB CG_SECURITY0
+      DB CG_SECURITY1
+      DB CG_SECURITY2
+      DB CG_SECURITY3
+      DB CG_SECURITY4
+      DB CG_SECURITY5
+      DB CG_SECURITY6
+      DB CG_SECURITY7
+      DB CG_SECURITY8
+      DB CG_SECURITY9
+
+;------------------------------------------------------------------------------
+; set microcontroller option bytes
+
+      COMMON INTVEC:CODE:ROOT(2)
+      ORG 7AH
+`OPTBYTES`:
+      DB CG_OPTION7A
+      DB CG_OPTION7B
+      DB OPT7C
+      DB OPT7D
+      DB OPT7E
+      DB OPT7F
+
+      END
\ No newline at end of file
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/portasm_Hx2.s85 b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/portasm_Hx2.s85
new file mode 100644
index 0000000..cc831bb
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/portasm_Hx2.s85
@@ -0,0 +1,350 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+; Note: Select the correct include files for the device used by the application.
+#include "FreeRTOSConfig.h"
+;------------------------------------------------------------------------------
+
+; Functions used by scheduler
+;------------------------------------------------------------------------------
+    EXTERN    vTaskSwitchContext
+    EXTERN    xTaskIncrementTick
+
+; Variables used by scheduler
+;------------------------------------------------------------------------------
+    EXTERN    pxCurrentTCB
+    EXTERN    usCriticalNesting
+
+; Functions implemented in this file
+;------------------------------------------------------------------------------
+    PUBLIC    vPortYield
+    PUBLIC    vPortStart
+
+; Security ID definition
+;------------------------------------------------------------------------------
+#define	CG_SECURITY0	0FFH
+#define	CG_SECURITY1	0FFH
+#define	CG_SECURITY2	0FFH
+#define	CG_SECURITY3	0FFH
+#define	CG_SECURITY4	0FFH
+#define	CG_SECURITY5	0FFH
+#define	CG_SECURITY6	0FFH
+#define	CG_SECURITY7	0FFH
+#define	CG_SECURITY8	0FFH
+#define	CG_SECURITY9	0FFH
+
+; Tick ISR Prototype
+;------------------------------------------------------------------------------
+        PUBWEAK `??MD_INTTM0EQ0??INTVEC 544`
+        PUBLIC MD_INTTM0EQ0
+
+MD_INTTM0EQ0        SYMBOL "MD_INTTM0EQ0"
+`??MD_INTTM0EQ0??INTVEC 544` SYMBOL "??INTVEC 544", MD_INTTM0EQ0
+
+;------------------------------------------------------------------------------
+;   portSAVE_CONTEXT MACRO
+;   Saves the context of the remaining general purpose registers
+;   and the usCriticalNesting Value of the active Task onto the task stack
+;   saves stack pointer to the TCB
+;------------------------------------------------------------------------------
+portSAVE_CONTEXT MACRO
+#if configDATA_MODE == 1                                        ; Using the Tiny data model
+    prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers
+    sst.w   r19,72[ep]
+    sst.w   r18,68[ep]
+    sst.w   r17,64[ep]
+    sst.w   r16,60[ep]
+    sst.w   r15,56[ep]
+    sst.w   r14,52[ep]
+    sst.w   r13,48[ep]
+    sst.w   r12,44[ep]
+    sst.w   r11,40[ep]
+    sst.w   r10,36[ep]
+    sst.w   r9,32[ep]
+    sst.w   r8,28[ep]
+    sst.w   r7,24[ep]
+    sst.w   r6,20[ep]
+    sst.w   r5,16[ep]
+    sst.w   r4,12[ep]
+#else                                                           ; Using the Small/Large data model
+    prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp     ; save general purpose registers
+    sst.w   r19,68[ep]
+    sst.w   r18,64[ep]
+    sst.w   r17,60[ep]
+    sst.w   r16,56[ep]
+    sst.w   r15,52[ep]
+    sst.w   r14,48[ep]
+    sst.w   r13,44[ep]
+    sst.w   r12,40[ep]
+    sst.w   r11,36[ep]
+    sst.w   r10,32[ep]
+    sst.w   r9,28[ep]
+    sst.w   r8,24[ep]
+    sst.w   r7,20[ep]
+    sst.w   r6,16[ep]
+    sst.w   r5,12[ep]
+#endif /* configDATA_MODE */
+    sst.w   r2,8[ep]
+    sst.w   r1,4[ep]
+    MOVHI   hi1(usCriticalNesting),r0,r1                        ; save usCriticalNesting value to stack
+    ld.w    lw1(usCriticalNesting)[r1],r2
+    sst.w   r2,0[ep]
+    MOVHI   hi1(pxCurrentTCB),r0,r1                             ; save SP to top of current TCB
+    ld.w    lw1(pxCurrentTCB)[r1],r2
+    st.w    sp,0[r2]
+    ENDM
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   portRESTORE_CONTEXT MACRO
+;   Gets stack pointer from the current TCB
+;   Restores the context of the usCriticalNesting value and general purpose
+;   registers of the selected task from the task stack
+;------------------------------------------------------------------------------
+portRESTORE_CONTEXT MACRO
+    MOVHI   hi1(pxCurrentTCB),r0,r1         ; get Stackpointer address
+    ld.w    lw1(pxCurrentTCB)[r1],sp
+    MOV     sp,r1
+    ld.w    0[r1],sp                        ; load stackpointer
+    MOV     sp,ep                           ; set stack pointer to element pointer
+    sld.w   0[ep],r1                        ; load usCriticalNesting value from stack
+    MOVHI   hi1(usCriticalNesting),r0,r2
+    st.w    r1,lw1(usCriticalNesting)[r2]
+    sld.w   4[ep],r1                        ; restore general purpose registers
+    sld.w   8[ep],r2
+#if configDATA_MODE == 1                    ; Using Tiny data model
+    sld.w   12[ep],r4
+    sld.w   16[ep],r5
+    sld.w   20[ep],r6
+    sld.w   24[ep],r7
+    sld.w   28[ep],r8
+    sld.w   32[ep],r9
+    sld.w   36[ep],r10
+    sld.w   40[ep],r11
+    sld.w   44[ep],r12
+    sld.w   48[ep],r13
+    sld.w   52[ep],r14
+    sld.w   56[ep],r15
+    sld.w   60[ep],r16
+    sld.w   64[ep],r17
+    sld.w   68[ep],r18
+    sld.w   72[ep],r19
+    dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30}
+#else                                       ; Using Small/Large data model
+    sld.w   12[ep],r5
+    sld.w   16[ep],r6
+    sld.w   20[ep],r7
+    sld.w   24[ep],r8
+    sld.w   28[ep],r9
+    sld.w   32[ep],r10
+    sld.w   36[ep],r11
+    sld.w   40[ep],r12
+    sld.w   44[ep],r13
+    sld.w   48[ep],r14
+    sld.w   52[ep],r15
+    sld.w   56[ep],r16
+    sld.w   60[ep],r17
+    sld.w   64[ep],r18
+    sld.w   68[ep],r19
+    dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30}
+#endif /* configDATA_MODE */
+    ENDM
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Restore the context of the first task that is going to run.
+;
+;   Input:  NONE
+;
+;   Call:   CALL    vPortStart
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+    RSEG CODE:CODE
+vPortStart:
+    portRESTORE_CONTEXT	                    ; Restore the context of whichever task the ...
+    ld.w    0[sp],lp
+    ldsr    lp,5                            ; restore PSW
+    DI
+    ld.w    4[sp],lp                        ; restore LP
+    ld.w    8[sp],lp                        ; restore LP
+    ADD     0x0C,sp                         ; set SP to right position
+    EI
+    jmp     [lp]
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Port Yield function to check for a Task switch in the cooperative and
+;   preemptive mode
+;
+;   Input:  NONE
+;
+;   Call:   CALL    vPortYield
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+
+	RSEG CODE:CODE
+vPortYield:
+
+    add     -0x0C,sp                          ; prepare stack to save necessary values
+    st.w    lp,8[sp]                        ; store LP to stack
+    stsr    0,r31
+    st.w    lp,4[sp]                        ; store EIPC to stack
+    stsr    1,lp
+    st.w    lp,0[sp]                        ; store EIPSW to stack
+    portSAVE_CONTEXT		            ; Save the context of the current task.
+    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
+    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
+                		            ; ... scheduler decided should run.
+	ld.w    0[sp],lp                        ; restore EIPSW from stack
+    ldsr    lp,1
+    ld.w    4[sp],lp                        ; restore EIPC from stack
+    ldsr    lp,0
+    ld.w    8[sp],lp                        ; restore LP from stack
+    add     0x0C,sp                         ; set SP to right position
+
+    RETI
+
+;------------------------------------------------------------------------------
+
+;------------------------------------------------------------------------------
+;   Perform the necessary steps of the Tick Count Increment and Task Switch
+;   depending on the chosen kernel configuration
+;
+;   Input:  NONE
+;
+;   Call:   ISR
+;
+;   Output: NONE
+;------------------------------------------------------------------------------
+#if configUSE_PREEMPTION == 1               ; use preemptive kernel mode
+
+MD_INTTM0EQ0:
+
+    add     -0x0C,sp                          ; prepare stack to save necessary values
+    st.w    lp,8[sp]                        ; store LP to stack
+    stsr    0,r31
+    st.w    lp,4[sp]                        ; store EIPC to stack
+    stsr    1,lp
+    st.w    lp,0[sp]                        ; store EIPSW to stack
+    portSAVE_CONTEXT		            ; Save the context of the current task.
+    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
+    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
+    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
+                		            ; ... scheduler decided should run.
+    ld.w    0[sp],lp                        ; restore EIPSW from stack
+    ldsr    lp,1
+    ld.w    4[sp],lp                        ; restore EIPC from stack
+    ldsr    lp,0
+    ld.w    8[sp],lp                        ; restore LP from stack
+    add     0x0C,sp                         ; set SP to right position
+
+    RETI
+;------------------------------------------------------------------------------
+#else                                       ; use cooperative kernel mode
+
+MD_INTTM0EQ0:
+    prepare {lp,ep},8,sp
+    sst.w   r1,4[ep]
+    sst.w   r5,0[ep]
+    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
+    sld.w   0[ep],r5
+    sld.w   4[ep],r1
+    dispose 8,{lp,ep}
+    RETI
+#endif /* configUSE_PREEMPTION */
+
+;------------------------------------------------------------------------------
+        COMMON INTVEC:CODE:ROOT(2)
+        ORG 544
+`??MD_INTTM0EQ0??INTVEC 544`:
+        JR MD_INTTM0EQ0
+
+        RSEG NEAR_ID:CONST:SORT:NOROOT(2)
+`?<Initializer for usCriticalNesting>`:
+        DW 10
+
+      COMMON INTVEC:CODE:ROOT(2)
+      ORG 40H
+`??vPortYield??INTVEC 40`:
+        JR vPortYield
+
+;------------------------------------------------------------------------------
+; set microcontroller security ID
+
+      COMMON INTVEC:CODE:ROOT(2)
+      ORG 70H
+`SECUID`:
+      DB CG_SECURITY0
+      DB CG_SECURITY1
+      DB CG_SECURITY2
+      DB CG_SECURITY3
+      DB CG_SECURITY4
+      DB CG_SECURITY5
+      DB CG_SECURITY6
+      DB CG_SECURITY7
+      DB CG_SECURITY8
+      DB CG_SECURITY9
+
+
+; set microcontroller Option bytes
+
+      COMMON INTVEC:CODE:ROOT(2)
+      ORG 122
+`OPTBYTES`:
+      DB 0xFD
+      DB 0xFF
+      DB 0xFF
+      DB 0xFF
+      DB 0xFF
+      DB 0xFF
+
+#if configOCD_USAGE == 1
+
+      COMMON   INTVEC:CODE:ROOT(4)
+      ORG      0x230
+      PUBLIC ROM_INT2
+ROM_INT2:
+      DB 0xff, 0xff, 0xff, 0xff
+      DB 0xff, 0xff, 0xff, 0xff
+      DB 0xff, 0xff, 0xff, 0xff
+      DB 0xff, 0xff, 0xff, 0xff
+
+
+      COMMON   INTVEC:CODE:ROOT(4)
+      ORG      0x60
+      PUBLIC   ROM_INT
+ROM_INT:
+      DB 0xff, 0xff, 0xff, 0xff
+      DB 0xff, 0xff, 0xff, 0xff
+      DB 0xff, 0xff, 0xff, 0xff
+      DB 0xff, 0xff, 0xff, 0xff
+
+#endif /* configOCD_USAGE */
+
+      END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/portmacro.h
new file mode 100644
index 0000000..8f808c6
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/IAR/V850ES/portmacro.h
@@ -0,0 +1,135 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  unsigned int
+#define portBASE_TYPE   int
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if (configUSE_16_BIT_TICKS==1)
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS() __asm ( "DI" )
+#define portENABLE_INTERRUPTS()	 __asm ( "EI" )
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( UBaseType_t ) 0 )
+
+#define portENTER_CRITICAL()														\
+{																					\
+extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting;						\
+																					\
+	portDISABLE_INTERRUPTS();														\
+																					\
+	/* Now interrupts are disabled ulCriticalNesting can be accessed */				\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */		\
+	/* times portENTER_CRITICAL() has been called. */								\
+	usCriticalNesting++;															\
+}
+
+#define portEXIT_CRITICAL()															\
+{																					\
+extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting;						\
+																					\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )						\
+	{																				\
+		/* Decrement the nesting count as we are leaving a critical section. */		\
+		usCriticalNesting--;														\
+																					\
+		/* If the nesting level has reached zero then interrupts should be */		\
+		/* re-enabled. */															\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )					\
+		{																			\
+			portENABLE_INTERRUPTS();												\
+		}																			\
+	}																				\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+extern void vPortYield( void );
+extern void vPortStart( void );
+extern void portSAVE_CONTEXT( void );
+extern void portRESTORE_CONTEXT( void );
+#define portYIELD()	__asm ( "trap 0" )
+#define portNOP()	__asm ( "NOP" )
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
+
+/*-----------------------------------------------------------*/
+
+/* Hardwware specifics. */
+#define portBYTE_ALIGNMENT	4
+#define portSTACK_GROWTH	( -1 )
+#define portTICK_PERIOD_MS	( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Keil/See-also-the-RVDS-directory.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Keil/See-also-the-RVDS-directory.txt
new file mode 100644
index 0000000..bd7fab7
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Keil/See-also-the-RVDS-directory.txt
@@ -0,0 +1 @@
+Nothing to see here.
\ No newline at end of file
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC18F/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC18F/port.c
new file mode 100644
index 0000000..b255007
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC18F/port.c
@@ -0,0 +1,615 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* 
+Changes between V1.2.4 and V1.2.5
+
+	+ Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global 
+	  interrupt flag setting.  Using the two bits defined within
+	  portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
+	  before the test was performed.
+
+Changes from V1.2.5
+
+	+ Set the interrupt vector address to 0x08.  Previously it was at the
+	  incorrect address for compatibility mode of 0x18.
+
+Changes from V2.1.1
+
+	+ PCLATU and PCLATH are now saved as part of the context.  This allows
+	  function pointers to be used within tasks.  Thanks to Javier Espeche
+	  for the enhancement. 
+
+Changes from V2.3.1
+
+	+ TABLAT is now saved as part of the task context.
+	
+Changes from V3.2.0
+
+	+ TBLPTRU is now initialised to zero as the MPLAB compiler expects this
+	  value and does not write to the register.
+*/
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* MPLAB library include file. */
+#include "timers.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the PIC port.
+ *----------------------------------------------------------*/
+
+/* Hardware setup for tick. */
+#define portTIMER_FOSC_SCALE			( ( uint32_t ) 4 )
+
+/* Initial interrupt enable state for newly created tasks.  This value is
+copied into INTCON when a task switches in for the first time. */
+#define portINITAL_INTERRUPT_STATE			0xc0
+
+/* Just the bit within INTCON for the global interrupt flag. */
+#define portGLOBAL_INTERRUPT_FLAG			0x80
+
+/* Constant used for context switch macro when we require the interrupt 
+enable state to be unchanged when the interrupted task is switched back in. */
+#define portINTERRUPTS_UNCHANGED			0x00
+
+/* Some memory areas get saved as part of the task context.  These memory
+area's get used by the compiler for temporary storage, especially when 
+performing mathematical operations, or when using 32bit data types.  This
+constant defines the size of memory area which must be saved. */
+#define portCOMPILER_MANAGED_MEMORY_SIZE	( ( uint8_t ) 0x13 )
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* IO port constants. */
+#define portBIT_SET		( ( uint8_t ) 1 )
+#define portBIT_CLEAR	( ( uint8_t ) 0 )
+
+/*
+ * The serial port ISR's are defined in serial.c, but are called from portable
+ * as they use the same vector as the tick ISR.
+ */
+void vSerialTxISR( void );
+void vSerialRxISR( void );
+
+/*
+ * Perform hardware setup to enable ticks.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/* 
+ * ISR to maintain the tick, and perform tick context switches if the
+ * preemptive scheduler is being used.
+ */
+static void prvTickISR( void );
+
+/*
+ * ISR placed on the low priority vector.  This calls the appropriate ISR for
+ * the actual interrupt.
+ */
+static void prvLowInterrupt( void );
+
+/* 
+ * Macro that pushes all the registers that make up the context of a task onto
+ * the stack, then saves the new top of stack into the TCB.
+ * 
+ * If this is called from an ISR then the interrupt enable bits must have been 
+ * set for the ISR to ever get called.  Therefore we want to save the INTCON
+ * register with the enable bits forced to be set - and ucForcedInterruptFlags 
+ * must contain these bit settings.  This means the interrupts will again be
+ * enabled when the interrupted task is switched back in.
+ *
+ * If this is called from a manual context switch (i.e. from a call to yield),
+ * then we want to save the INTCON so it is restored with its current state,
+ * and ucForcedInterruptFlags must be 0.  This allows a yield from within
+ * a critical section.
+ *
+ * The compiler uses some locations at the bottom of the memory for temporary
+ * storage during math and other computations.  This is especially true if
+ * 32bit data types are utilised (as they are by the scheduler).  The .tmpdata
+ * and MATH_DATA sections have to be stored in there entirety as part of a task
+ * context.  This macro stores from data address 0x00 to 
+ * portCOMPILER_MANAGED_MEMORY_SIZE.  This is sufficient for the demo 
+ * applications but you should check the map file for your project to ensure 
+ * this is sufficient for your needs.  It is not clear whether this size is 
+ * fixed for all compilations or has the potential to be program specific.
+ */
+#define	portSAVE_CONTEXT( ucForcedInterruptFlags )								\
+{																				\
+	_asm																		\
+		/* Save the status and WREG registers first, as these will get modified	\
+		by the operations below. */												\
+		MOVFF	WREG, PREINC1													\
+		MOVFF   STATUS, PREINC1													\
+		/* Save the INTCON register with the appropriate bits forced if			\
+		necessary - as described above. */										\
+		MOVFF	INTCON, WREG													\
+		IORLW	ucForcedInterruptFlags											\
+		MOVFF	WREG, PREINC1													\
+	_endasm																		\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	_asm																		\
+		/* Store the necessary registers to the stack. */						\
+		MOVFF	BSR, PREINC1													\
+		MOVFF	FSR2L, PREINC1													\
+		MOVFF	FSR2H, PREINC1													\
+		MOVFF	FSR0L, PREINC1													\
+		MOVFF	FSR0H, PREINC1													\
+		MOVFF	TABLAT, PREINC1													\
+		MOVFF	TBLPTRU, PREINC1												\
+		MOVFF	TBLPTRH, PREINC1												\
+		MOVFF	TBLPTRL, PREINC1												\
+		MOVFF	PRODH, PREINC1													\
+		MOVFF	PRODL, PREINC1													\
+		MOVFF	PCLATU, PREINC1													\
+		MOVFF	PCLATH, PREINC1													\
+		/* Store the .tempdata and MATH_DATA areas as described above. */		\
+		CLRF	FSR0L, 0														\
+		CLRF	FSR0H, 0														\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	POSTINC0, PREINC1												\
+		MOVFF	INDF0, PREINC1													\
+		MOVFF	FSR0L, PREINC1													\
+		MOVFF	FSR0H, PREINC1													\
+		/* Store the hardware stack pointer in a temp register before we		\
+		modify it. */															\
+		MOVFF	STKPTR, FSR0L													\
+	_endasm																		\
+																				\
+		/* Store each address from the hardware stack. */						\
+		while( STKPTR > ( uint8_t ) 0 )								\
+		{																		\
+			_asm																\
+				MOVFF	TOSL, PREINC1											\
+				MOVFF	TOSH, PREINC1											\
+				MOVFF	TOSU, PREINC1											\
+				POP																\
+			_endasm																\
+		}																		\
+																				\
+	_asm																		\
+		/* Store the number of addresses on the hardware stack (from the		\
+		temporary register). */													\
+		MOVFF	FSR0L, PREINC1													\
+		MOVF	PREINC1, 1, 0													\
+	_endasm																		\
+																				\
+	/* Save the new top of the software stack in the TCB. */					\
+	_asm																		\
+		MOVFF	pxCurrentTCB, FSR0L												\
+		MOVFF	pxCurrentTCB + 1, FSR0H											\
+		MOVFF	FSR1L, POSTINC0													\
+		MOVFF	FSR1H, POSTINC0													\
+	_endasm																		\
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * This is the reverse of portSAVE_CONTEXT.  See portSAVE_CONTEXT for more
+ * details.
+ */
+#define portRESTORE_CONTEXT()													\
+{																				\
+	_asm																		\
+		/* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */					\
+		MOVFF	pxCurrentTCB, FSR0L												\
+		MOVFF	pxCurrentTCB + 1, FSR0H											\
+																				\
+		/* De-reference FSR0 to set the address it holds into FSR1.				\
+		(i.e. *( pxCurrentTCB->pxTopOfStack ) ). */								\
+		MOVFF	POSTINC0, FSR1L													\
+		MOVFF	POSTINC0, FSR1H													\
+																				\
+		/* How many return addresses are there on the hardware stack?  Discard	\
+		the first byte as we are pointing to the next free space. */			\
+		MOVFF	POSTDEC1, FSR0L													\
+		MOVFF	POSTDEC1, FSR0L													\
+	_endasm																		\
+																				\
+	/* Fill the hardware stack from our software stack. */						\
+	STKPTR = 0;																	\
+																				\
+	while( STKPTR < FSR0L )														\
+	{																			\
+		_asm																	\
+			PUSH																\
+			MOVF	POSTDEC1, 0, 0												\
+			MOVWF	TOSU, 0														\
+			MOVF	POSTDEC1, 0, 0												\
+			MOVWF	TOSH, 0														\
+			MOVF	POSTDEC1, 0, 0												\
+			MOVWF	TOSL, 0														\
+		_endasm																	\
+	}																			\
+																				\
+	_asm																		\
+		/* Restore the .tmpdata and MATH_DATA memory. */						\
+		MOVFF	POSTDEC1, FSR0H													\
+		MOVFF	POSTDEC1, FSR0L													\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, POSTDEC0												\
+		MOVFF	POSTDEC1, INDF0													\
+		/* Restore the other registers forming the tasks context. */			\
+		MOVFF	POSTDEC1, PCLATH												\
+		MOVFF	POSTDEC1, PCLATU												\
+		MOVFF	POSTDEC1, PRODL													\
+		MOVFF	POSTDEC1, PRODH													\
+		MOVFF	POSTDEC1, TBLPTRL												\
+		MOVFF	POSTDEC1, TBLPTRH												\
+		MOVFF	POSTDEC1, TBLPTRU												\
+		MOVFF	POSTDEC1, TABLAT												\
+		MOVFF	POSTDEC1, FSR0H													\
+		MOVFF	POSTDEC1, FSR0L													\
+		MOVFF	POSTDEC1, FSR2H													\
+		MOVFF	POSTDEC1, FSR2L													\
+		MOVFF	POSTDEC1, BSR													\
+		/* The next byte is the INTCON register.  Read this into WREG as some	\
+		manipulation is required. */											\
+		MOVFF	POSTDEC1, WREG													\
+	_endasm																		\
+																				\
+	/* From the INTCON register, only the interrupt enable bits form part		\
+	of the tasks context.  It is perfectly legitimate for another task to		\
+	have modified any other bits.  We therefore only restore the top two bits.	\
+	*/																			\
+	if( WREG & portGLOBAL_INTERRUPT_FLAG )										\
+	{																			\
+		_asm 																	\
+			MOVFF	POSTDEC1, STATUS											\
+			MOVFF	POSTDEC1, WREG												\
+			/* Return enabling interrupts. */									\
+			RETFIE	0															\
+		_endasm																	\
+	}																			\
+	else																		\
+	{																			\
+		_asm 																	\
+			MOVFF	POSTDEC1, STATUS											\
+			MOVFF	POSTDEC1, WREG												\
+			/* Return without effecting interrupts.  The context may have		\
+			been saved from a critical region. */								\
+			RETURN	0															\
+		_endasm																	\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t ulAddress;
+uint8_t ucBlock;
+
+	/* Place a few bytes of known values on the bottom of the stack. 
+	This is just useful for debugging. */
+
+	*pxTopOfStack = 0x11;
+	pxTopOfStack++;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack++;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack++;
+
+
+	/* Simulate how the stack would look after a call to vPortYield() generated
+	by the compiler. 
+
+	First store the function parameters.  This is where the task will expect to
+	find them when it starts running. */
+	ulAddress = ( uint32_t ) pvParameters;
+	*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
+	pxTopOfStack++;
+
+	ulAddress >>= 8;
+	*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
+	pxTopOfStack++;
+
+	/* Next we just leave a space.  When a context is saved the stack pointer
+	is incremented before it is used so as not to corrupt whatever the stack
+	pointer is actually pointing to.  This is especially necessary during 
+	function epilogue code generated by the compiler. */
+	*pxTopOfStack = 0x44;
+	pxTopOfStack++;
+
+	/* Next are all the registers that form part of the task context. */
+	
+	*pxTopOfStack = ( StackType_t ) 0x66; /* WREG. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0xcc; /* Status. */
+	pxTopOfStack++;
+
+	/* INTCON is saved with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITAL_INTERRUPT_STATE; /* INTCON */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x11; /* BSR. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x22; /* FSR2L. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x33; /* FSR2H. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x44; /* FSR0L. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x55; /* FSR0H. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x66; /* TABLAT. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x00; /* TBLPTRU. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x88; /* TBLPTRUH. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x99; /* TBLPTRUL. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0xaa; /* PRODH. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0xbb; /* PRODL. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x00; /* PCLATU. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x00; /* PCLATH. */
+	pxTopOfStack++;
+
+	/* Next the .tmpdata and MATH_DATA sections. */
+	for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
+	{
+		*pxTopOfStack = ( StackType_t ) ucBlock;
+		*pxTopOfStack++;
+	}
+
+	/* Store the top of the global data section. */
+	*pxTopOfStack = ( StackType_t ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
+	pxTopOfStack++;
+
+	*pxTopOfStack = ( StackType_t ) 0x00; /* High. */
+	pxTopOfStack++;
+
+	/* The only function return address so far is the address of the 
+	task. */
+	ulAddress = ( uint32_t ) pxCode;
+
+	/* TOS low. */
+	*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
+	pxTopOfStack++;
+	ulAddress >>= 8;
+
+	/* TOS high. */
+	*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
+	pxTopOfStack++;
+	ulAddress >>= 8;
+
+	/* TOS even higher. */
+	*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
+	pxTopOfStack++;
+
+	/* Store the number of return addresses on the hardware stack - so far only
+	the address of the task entry point. */
+	*pxTopOfStack = ( StackType_t ) 1;
+	pxTopOfStack++;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup a timer for the tick ISR is using the preemptive scheduler. */
+	prvSetupTimerInterrupt(); 
+
+	/* Restore the context of the first task to run. */
+	portRESTORE_CONTEXT();
+
+	/* Should not get here.  Use the function name to stop compiler warnings. */
+	( void ) prvLowInterrupt;
+	( void ) prvTickISR;
+
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the scheduler for the PIC port will get stopped
+	once running.  If required disable the tick interrupt here, then return 
+	to xPortStartScheduler(). */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch.  This is similar to the tick context switch,
+ * but does not increment the tick count.  It must be identical to the
+ * tick context switch in how it stores the stack of a task.
+ */
+void vPortYield( void )
+{
+	/* This can get called with interrupts either enabled or disabled.  We
+	will save the INTCON register with the interrupt enable bits unmodified. */
+	portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
+
+	/* Switch to the highest priority task that is ready to run. */
+	vTaskSwitchContext();
+
+	/* Start executing the task we have just switched to. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Vector for ISR.  Nothing here must alter any registers!
+ */
+#pragma code high_vector=0x08
+static void prvLowInterrupt( void )
+{
+	/* Was the interrupt the tick? */
+	if( PIR1bits.CCP1IF )
+	{		
+		_asm
+			goto prvTickISR
+		_endasm
+	}
+
+	/* Was the interrupt a byte being received? */
+	if( PIR1bits.RCIF )
+	{
+		_asm
+			goto vSerialRxISR
+		_endasm
+	}
+
+	/* Was the interrupt the Tx register becoming empty? */
+	if( PIR1bits.TXIF )
+	{
+		if( PIE1bits.TXIE )
+		{
+			_asm
+				goto vSerialTxISR
+			_endasm
+		}
+	}
+}
+#pragma code
+
+/*-----------------------------------------------------------*/
+
+/*
+ * ISR for the tick.
+ * This increments the tick count and, if using the preemptive scheduler, 
+ * performs a context switch.  This must be identical to the manual 
+ * context switch in how it stores the context of a task. 
+ */
+static void prvTickISR( void )
+{
+	/* Interrupts must have been enabled for the ISR to fire, so we have to 
+	save the context with interrupts enabled. */
+	portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
+	PIR1bits.CCP1IF = 0;
+
+	/* Maintain the tick count. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		/* Switch to the highest priority task that is ready to run. */
+		vTaskSwitchContext();
+	}
+
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup a timer for a regular tick.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
+uint32_t ulCompareValue;
+uint8_t ucByte;
+
+	/* Interrupts are disabled when this function is called.
+
+	Setup CCP1 to provide the tick interrupt using a compare match on timer
+	1.
+
+	Clear the time count then setup timer. */
+	TMR1H = ( uint8_t ) 0x00;
+	TMR1L = ( uint8_t ) 0x00;
+
+	/* Set the compare match value. */
+	ulCompareValue = ulConstCompareValue;
+	CCPR1L = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
+	ulCompareValue >>= ( uint32_t ) 8;
+	CCPR1H = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );	
+
+	CCP1CONbits.CCP1M0 = portBIT_SET;	/*< Compare match mode. */
+	CCP1CONbits.CCP1M1 = portBIT_SET;	/*< Compare match mode. */
+	CCP1CONbits.CCP1M2 = portBIT_CLEAR;	/*< Compare match mode. */
+	CCP1CONbits.CCP1M3 = portBIT_SET;	/*< Compare match mode. */
+	PIE1bits.CCP1IE = portBIT_SET;		/*< Interrupt enable. */
+
+	/* We are only going to use the global interrupt bit, so set the peripheral
+	bit to true. */
+	INTCONbits.GIEL = portBIT_SET;
+
+	/* Provided library function for setting up the timer that will produce the
+	tick. */
+	OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
+}
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC18F/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC18F/portmacro.h
new file mode 100644
index 0000000..e194736
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC18F/portmacro.h
@@ -0,0 +1,112 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint8_t
+#define portBASE_TYPE	char
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			1
+#define portGLOBAL_INT_ENABLE_BIT	0x80
+#define portSTACK_GROWTH			1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portDISABLE_INTERRUPTS()	INTCONbits.GIEH = 0;
+#define portENABLE_INTERRUPTS()		INTCONbits.GIEH = 1;
+
+/* Push the INTCON register onto the stack, then disable interrupts. */
+#define portENTER_CRITICAL()		POSTINC1 = INTCON;				\
+									INTCONbits.GIEH = 0;
+
+/* Retrieve the INTCON register from the stack, and enable interrupts
+if they were saved as being enabled.  Don't modify any other bits
+within the INTCON register as these may have lagitimately have been
+modified within the critical region. */
+#define portEXIT_CRITICAL()			_asm									\
+										MOVF	POSTDEC1, 1, 0				\
+									_endasm									\
+									if( INDF1 & portGLOBAL_INT_ENABLE_BIT )	\
+									{										\
+										portENABLE_INTERRUPTS();			\
+									}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+extern void vPortYield( void );
+#define portYIELD()				vPortYield()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Required by the kernel aware debugger. */
+#ifdef __DEBUG
+	#define portREMOVE_STATIC_QUALIFIER
+#endif
+
+
+#define portNOP()				_asm	\
+									NOP \
+								_endasm
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC18F/stdio.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC18F/stdio.h
new file mode 100644
index 0000000..e69de29
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/port.c
new file mode 100644
index 0000000..fc43c62
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/port.c
@@ -0,0 +1,333 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+	Changes from V4.2.1
+
+	+ Introduced the configKERNEL_INTERRUPT_PRIORITY definition.
+*/
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the PIC24 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Hardware specifics. */
+#define portBIT_SET 1
+#define portTIMER_PRESCALE 8
+#define portINITIAL_SR	0
+
+/* Defined for backward compatability with project created prior to
+FreeRTOS.org V4.3.0. */
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+	#define configKERNEL_INTERRUPT_PRIORITY 1
+#endif
+
+/* Use _T1Interrupt as the interrupt handler name if the application writer has
+not provided their own. */
+#ifndef configTICK_INTERRUPT_HANDLER
+	#define configTICK_INTERRUPT_HANDLER _T1Interrupt
+#endif /* configTICK_INTERRUPT_HANDLER */
+
+/* The program counter is only 23 bits. */
+#define portUNUSED_PR_BITS	0x7f
+
+/* Records the nesting depth of calls to portENTER_CRITICAL(). */
+UBaseType_t uxCriticalNesting = 0xef;
+
+#if configKERNEL_INTERRUPT_PRIORITY != 1
+	#error If configKERNEL_INTERRUPT_PRIORITY is not 1 then the #32 in the following macros needs changing to equal the portINTERRUPT_BITS value, which is ( configKERNEL_INTERRUPT_PRIORITY << 5 )
+#endif
+
+#if defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ )
+
+    #ifdef __HAS_EDS__
+		#define portRESTORE_CONTEXT()																						\
+					asm volatile(	"MOV	_pxCurrentTCB, W0		\n"	/* Restore the stack pointer for the task. */		\
+							"MOV	[W0], W15				\n"																\
+							"POP	W0						\n"	/* Restore the critical nesting counter for the task. */	\
+							"MOV	W0, _uxCriticalNesting	\n"																\
+							"POP	DSWPAG					\n"																\
+							"POP    DSRPAG					\n"																\
+							"POP	CORCON					\n"																\
+							"POP	TBLPAG					\n"																\
+							"POP	RCOUNT					\n"	/* Restore the registers from the stack. */					\
+							"POP	W14						\n"																\
+							"POP.D	W12						\n"																\
+							"POP.D	W10						\n"																\
+							"POP.D	W8						\n"																\
+							"POP.D	W6						\n"																\
+							"POP.D	W4						\n"																\
+							"POP.D	W2						\n"																\
+							"POP.D	W0						\n"																\
+							"POP	SR						  " );
+	#else /* __HAS_EDS__ */
+		#define portRESTORE_CONTEXT()																						\
+			asm volatile(	"MOV	_pxCurrentTCB, W0		\n"	/* Restore the stack pointer for the task. */				\
+							"MOV	[W0], W15				\n"																\
+							"POP	W0						\n"	/* Restore the critical nesting counter for the task. */	\
+							"MOV	W0, _uxCriticalNesting	\n"																\
+							"POP	PSVPAG					\n"																\
+							"POP	CORCON					\n"																\
+							"POP	TBLPAG					\n"																\
+							"POP	RCOUNT					\n"	/* Restore the registers from the stack. */					\
+							"POP	W14						\n"																\
+							"POP.D	W12						\n"																\
+							"POP.D	W10						\n"																\
+							"POP.D	W8						\n"																\
+							"POP.D	W6						\n"																\
+							"POP.D	W4						\n"																\
+							"POP.D	W2						\n"																\
+							"POP.D	W0						\n"																\
+							"POP	SR						  " );
+		#endif /* __HAS_EDS__ */
+#endif /* MPLAB_PIC24_PORT */
+
+#if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ )
+
+	#define portRESTORE_CONTEXT()																						\
+		asm volatile(	"MOV	_pxCurrentTCB, W0		\n"	/* Restore the stack pointer for the task. */				\
+						"MOV	[W0], W15				\n"																\
+						"POP	W0						\n"	/* Restore the critical nesting counter for the task. */	\
+						"MOV	W0, _uxCriticalNesting	\n"																\
+						"POP	PSVPAG					\n"																\
+						"POP	CORCON					\n"																\
+						"POP	DOENDH					\n"																\
+						"POP	DOENDL					\n"																\
+						"POP	DOSTARTH				\n"																\
+						"POP	DOSTARTL				\n"																\
+						"POP	DCOUNT					\n"																\
+						"POP	ACCBU					\n"																\
+						"POP	ACCBH					\n"																\
+						"POP	ACCBL					\n"																\
+						"POP	ACCAU					\n"																\
+						"POP	ACCAH					\n"																\
+						"POP	ACCAL					\n"																\
+						"POP	TBLPAG					\n"																\
+						"POP	RCOUNT					\n"	/* Restore the registers from the stack. */					\
+						"POP	W14						\n"																\
+						"POP.D	W12						\n"																\
+						"POP.D	W10						\n"																\
+						"POP.D	W8						\n"																\
+						"POP.D	W6						\n"																\
+						"POP.D	W4						\n"																\
+						"POP.D	W2						\n"																\
+						"POP.D	W0						\n"																\
+						"POP	SR						  " );
+
+#endif /* MPLAB_DSPIC_PORT */
+
+#ifndef portRESTORE_CONTEXT
+	#error Unrecognised device selected
+
+	/* Note:  dsPIC parts with EDS are not supported as there is no easy way to
+	recover the hardware stacked copies for DOCOUNT, DOHIGH, DOLOW. */
+#endif
+
+/*
+ * Setup the timer used to generate the tick interrupt.
+ */
+void vApplicationSetupTickTimerInterrupt( void );
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint16_t usCode;
+UBaseType_t i;
+
+const StackType_t xInitialStack[] =
+{
+	0x1111,	/* W1 */
+	0x2222, /* W2 */
+	0x3333, /* W3 */
+	0x4444, /* W4 */
+	0x5555, /* W5 */
+	0x6666, /* W6 */
+	0x7777, /* W7 */
+	0x8888, /* W8 */
+	0x9999, /* W9 */
+	0xaaaa, /* W10 */
+	0xbbbb, /* W11 */
+	0xcccc, /* W12 */
+	0xdddd, /* W13 */
+	0xeeee, /* W14 */
+	0xcdce, /* RCOUNT */
+	0xabac, /* TBLPAG */
+
+	/* dsPIC specific registers. */
+	#ifdef MPLAB_DSPIC_PORT
+		0x0202, /* ACCAL */
+		0x0303, /* ACCAH */
+		0x0404, /* ACCAU */
+		0x0505, /* ACCBL */
+		0x0606, /* ACCBH */
+		0x0707, /* ACCBU */
+		0x0808, /* DCOUNT */
+		0x090a, /* DOSTARTL */
+		0x1010, /* DOSTARTH */
+		0x1110, /* DOENDL */
+		0x1212, /* DOENDH */
+	#endif
+};
+
+	/* Setup the stack as if a yield had occurred.
+
+	Save the low bytes of the program counter. */
+	usCode = ( uint16_t ) pxCode;
+	*pxTopOfStack = ( StackType_t ) usCode;
+	pxTopOfStack++;
+
+	/* Save the high byte of the program counter.  This will always be zero
+	here as it is passed in a 16bit pointer.  If the address is greater than
+	16 bits then the pointer will point to a jump table. */
+	*pxTopOfStack = ( StackType_t ) 0;
+	pxTopOfStack++;
+
+	/* Status register with interrupts enabled. */
+	*pxTopOfStack = portINITIAL_SR;
+	pxTopOfStack++;
+
+	/* Parameters are passed in W0. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack++;
+
+	for( i = 0; i < ( sizeof( xInitialStack ) / sizeof( StackType_t ) ); i++ )
+	{
+		*pxTopOfStack = xInitialStack[ i ];
+		pxTopOfStack++;
+	}
+
+	*pxTopOfStack = CORCON;
+	pxTopOfStack++;
+
+	#if defined(__HAS_EDS__)
+		*pxTopOfStack = DSRPAG;
+		pxTopOfStack++;
+		*pxTopOfStack = DSWPAG;
+		pxTopOfStack++;
+	#else /* __HAS_EDS__ */
+		*pxTopOfStack = PSVPAG;
+		pxTopOfStack++;
+	#endif /* __HAS_EDS__ */
+
+	/* Finally the critical nesting depth. */
+	*pxTopOfStack = 0x00;
+	pxTopOfStack++;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup a timer for the tick ISR. */
+	vApplicationSetupTickTimerInterrupt();
+
+	/* Restore the context of the first task to run. */
+	portRESTORE_CONTEXT();
+
+	/* Simulate the end of the yield function. */
+	asm volatile ( "return" );
+
+	/* Should not reach here. */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup a timer for a regular tick.
+ */
+__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
+{
+const uint32_t ulCompareMatch = ( ( configCPU_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
+
+	/* Prescale of 8. */
+	T1CON = 0;
+	TMR1 = 0;
+
+	PR1 = ( uint16_t ) ulCompareMatch;
+
+	/* Setup timer 1 interrupt priority. */
+	IPC0bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
+
+	/* Clear the interrupt as a starting condition. */
+	IFS0bits.T1IF = 0;
+
+	/* Enable the interrupt. */
+	IEC0bits.T1IE = 1;
+
+	/* Setup the prescale value. */
+	T1CONbits.TCKPS0 = 1;
+	T1CONbits.TCKPS1 = 0;
+
+	/* Start the timer. */
+	T1CONbits.TON = 1;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void __attribute__((__interrupt__, auto_psv)) configTICK_INTERRUPT_HANDLER( void )
+{
+	/* Clear the timer interrupt. */
+	IFS0bits.T1IF = 0;
+
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		portYIELD();
+	}
+}
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S
new file mode 100644
index 0000000..87e8a2c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S
@@ -0,0 +1,92 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#if defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ )
+
+        .global _vPortYield
+		.extern _vTaskSwitchContext
+		.extern uxCriticalNesting
+
+_vPortYield:
+
+		PUSH	SR						/* Save the SR used by the task.... */
+		PUSH	W0						/* ....then disable interrupts. */
+		MOV		#32, W0
+		MOV		W0, SR
+		PUSH	W1						/* Save registers to the stack. */
+		PUSH.D	W2
+		PUSH.D	W4
+		PUSH.D	W6
+		PUSH.D 	W8
+		PUSH.D 	W10
+		PUSH.D	W12
+		PUSH	W14
+		PUSH	RCOUNT
+		PUSH	TBLPAG
+
+		PUSH	CORCON
+		#ifdef __HAS_EDS__
+			PUSH	DSRPAG
+			PUSH	DSWPAG
+		#else
+			PUSH	PSVPAG
+		#endif /* __HAS_EDS__ */
+		MOV		_uxCriticalNesting, W0		/* Save the critical nesting counter for the task. */
+		PUSH	W0
+		MOV		_pxCurrentTCB, W0			/* Save the new top of stack into the TCB. */
+		MOV		W15, [W0]
+
+		call 	_vTaskSwitchContext
+
+		MOV		_pxCurrentTCB, W0			/* Restore the stack pointer for the task. */
+		MOV		[W0], W15
+		POP		W0							/* Restore the critical nesting counter for the task. */
+		MOV		W0, _uxCriticalNesting
+		#ifdef __HAS_EDS__
+			POP		DSWPAG
+			POP		DSRPAG
+		#else
+			POP		PSVPAG
+		#endif /* __HAS_EDS__ */
+		POP		CORCON
+		POP		TBLPAG
+		POP		RCOUNT						/* Restore the registers from the stack. */
+		POP		W14
+		POP.D	W12
+		POP.D	W10
+		POP.D	W8
+		POP.D	W6
+		POP.D	W4
+		POP.D	W2
+		POP.D	W0
+		POP		SR
+
+        return
+
+        .end
+		
+#endif /* defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ ) */
\ No newline at end of file
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S
new file mode 100644
index 0000000..f9273b4
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S
@@ -0,0 +1,106 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ )
+
+        .global _vPortYield
+		.extern _vTaskSwitchContext
+		.extern uxCriticalNesting
+
+_vPortYield:
+
+		PUSH	SR						/* Save the SR used by the task.... */
+		PUSH	W0						/* ....then disable interrupts. */
+		MOV		#32, W0
+		MOV		W0, SR
+		PUSH	W1						/* Save registers to the stack. */
+		PUSH.D	W2
+		PUSH.D	W4
+		PUSH.D	W6
+		PUSH.D 	W8
+		PUSH.D 	W10
+		PUSH.D	W12
+		PUSH	W14
+		PUSH	RCOUNT
+		PUSH	TBLPAG
+		PUSH	ACCAL
+		PUSH	ACCAH
+		PUSH	ACCAU
+		PUSH	ACCBL
+		PUSH	ACCBH
+		PUSH	ACCBU
+		PUSH	DCOUNT
+		PUSH	DOSTARTL
+		PUSH	DOSTARTH
+		PUSH	DOENDL
+		PUSH	DOENDH
+
+
+		PUSH	CORCON
+		PUSH	PSVPAG
+		MOV		_uxCriticalNesting, W0		/* Save the critical nesting counter for the task. */
+		PUSH	W0
+		MOV		_pxCurrentTCB, W0			/* Save the new top of stack into the TCB. */
+		MOV		W15, [W0]
+
+		call 	_vTaskSwitchContext
+
+		MOV		_pxCurrentTCB, W0			/* Restore the stack pointer for the task. */
+		MOV		[W0], W15
+		POP		W0							/* Restore the critical nesting counter for the task. */
+		MOV		W0, _uxCriticalNesting
+		POP		PSVPAG
+		POP		CORCON
+		POP		DOENDH
+		POP		DOENDL
+		POP		DOSTARTH
+		POP		DOSTARTL
+		POP		DCOUNT
+		POP		ACCBU
+		POP		ACCBH
+		POP		ACCBL
+		POP		ACCAU
+		POP		ACCAH
+		POP		ACCAL
+		POP		TBLPAG
+		POP		RCOUNT						/* Restore the registers from the stack. */
+		POP		W14
+		POP.D	W12
+		POP.D	W10
+		POP.D	W8
+		POP.D	W6
+		POP.D	W4
+		POP.D	W2
+		POP.D	W0
+		POP		SR
+
+        return
+
+        .end
+
+#endif /* defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h
new file mode 100644
index 0000000..b237d2d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h
@@ -0,0 +1,108 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			2
+#define portSTACK_GROWTH			1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portDISABLE_INTERRUPTS()	SET_CPU_IPL( configKERNEL_INTERRUPT_PRIORITY ); __asm volatile ( "NOP" )
+#define portENABLE_INTERRUPTS()		SET_CPU_IPL( 0 )
+
+/* Note that exiting a critical sectino will set the IPL bits to 0, nomatter
+what their value was prior to entering the critical section. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+extern void vPortYield( void );
+#define portYIELD()				asm volatile ( "CALL _vPortYield			\n"		\
+												"NOP					  " );
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Required by the kernel aware debugger. */
+#ifdef __DEBUG
+	#define portREMOVE_STATIC_QUALIFIER
+#endif
+
+#define portNOP()				asm volatile ( "NOP" )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/ISR_Support.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
new file mode 100644
index 0000000..c5047d7
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
@@ -0,0 +1,214 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOSConfig.h"
+
+#define portCONTEXT_SIZE 132
+#define portEPC_STACK_LOCATION 124
+#define portSTATUS_STACK_LOCATION 128
+
+#ifdef __LANGUAGE_ASSEMBLY__
+
+/******************************************************************/
+.macro	portSAVE_CONTEXT
+
+	/* Make room for the context. First save the current status so it can be
+	manipulated, and the cause and EPC registers so their original values are
+	captured. */
+	mfc0	k0, _CP0_CAUSE
+	addiu	sp, sp, -portCONTEXT_SIZE
+	mfc0	k1, _CP0_STATUS
+
+	/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
+	maintain the values of these registers across the ISR. */
+	sw		s6, 44(sp)
+	sw		s5, 40(sp)
+	sw		k1, portSTATUS_STACK_LOCATION(sp)
+
+	/* Prepare to enable interrupts above the current priority.
+	k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
+	srl		k0, k0, 0xa
+
+	/* Insert bit field. 7 bits k0[6:0] to k1[16:10] */
+	ins		k1, k0, 10, 7
+
+	/* Sets CP0.Status.IPL = CP0.Cause.RIPL
+	Copy the MSB of the IPL, but it would be an error if it was set anyway. */
+	srl		k0, k0, 0x7
+
+	/* MSB of IPL is bit[18] of CP0.Status */
+	ins		k1, k0, 18, 1
+
+	/* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM,
+	   b[3]=Rsvd, b[2]=ERL, b[1]=EXL
+	   Setting EXL=0 allows higher priority interrupts
+	   to preempt this handler */
+	ins		k1, zero, 1, 4
+
+
+	/* s5 is used as the frame pointer. */
+	add		s5, zero, sp
+
+	/* Check the nesting count value. */
+	la		k0, uxInterruptNesting
+	lw		s6, (k0)
+
+	/* If the nesting count is 0 then swap to the the system stack, otherwise
+	the system stack is already being used. */
+	bne		s6, zero, 1f
+	nop
+
+	/* Swap to the system stack. */
+	la		sp, xISRStackTop
+	lw		sp, (sp)
+
+	/* Increment and save the nesting count. */
+1:  addiu   s6, s6, 1
+	sw		s6, 0(k0)
+
+	/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
+	mfc0	s6, _CP0_EPC
+
+	/* Re-enable interrupts. */
+	mtc0	k1, _CP0_STATUS
+
+	/* Save the context into the space just created.  s6 is saved again
+	here as it now contains the EPC value.  No other s registers need be
+	saved. */
+	sw		ra, 120(s5) /* Return address (RA=R31) */
+	sw		s8, 116(s5) /* Frame Pointer (FP=R30) */
+	sw		t9, 112(s5)
+	sw		t8, 108(s5)
+	sw		t7, 104(s5)
+	sw		t6, 100(s5)
+	sw		t5, 96(s5)
+	sw		t4, 92(s5)
+	sw		t3, 88(s5)
+	sw		t2, 84(s5)
+	sw		t1, 80(s5)
+	sw		t0, 76(s5)
+	sw		a3, 72(s5)
+	sw		a2, 68(s5)
+	sw		a1, 64(s5)
+	sw		a0, 60(s5)
+	sw		v1, 56(s5)
+	sw		v0, 52(s5)
+	sw		s6, portEPC_STACK_LOCATION(s5)
+	sw		$1, 16(s5)
+
+	/* MEC14xx does not have DSP, removed 7 words */
+	mfhi	s6
+	sw		s6, 12(s5)
+	mflo	s6
+	sw		s6, 8(s5)
+
+	/* Update the task stack pointer value if nesting is zero. */
+	la		s6, uxInterruptNesting
+	lw		s6, (s6)
+	addiu	s6, s6, -1
+	bne		s6, zero, 1f
+	nop
+
+	/* Save the stack pointer. */
+	la		s6, uxSavedTaskStackPointer
+	sw		s5, (s6)
+1:
+	.endm
+
+/******************************************************************/
+.macro	portRESTORE_CONTEXT
+
+	/* Restore the stack pointer from the TCB.  This is only done if the
+	nesting count is 1. */
+	la		s6, uxInterruptNesting
+	lw		s6, (s6)
+	addiu   s6, s6, -1
+	bne		s6, zero, 1f
+	nop
+	la		s6, uxSavedTaskStackPointer
+	lw		s5, (s6)
+
+	/* Restore the context.
+	MCHP MEC14xx does not include DSP */
+1:
+	lw		s6, 8(s5)
+	mtlo	s6
+	lw		s6, 12(s5)
+	mthi	s6
+	lw		$1, 16(s5)
+
+	/* s6 is loaded as it was used as a scratch register and therefore saved
+	as part of the interrupt context. */
+	lw		s6, 44(s5)
+	lw		v0, 52(s5)
+	lw		v1, 56(s5)
+	lw		a0, 60(s5)
+	lw		a1, 64(s5)
+	lw		a2, 68(s5)
+	lw		a3, 72(s5)
+	lw		t0, 76(s5)
+	lw		t1, 80(s5)
+	lw		t2, 84(s5)
+	lw		t3, 88(s5)
+	lw		t4, 92(s5)
+	lw		t5, 96(s5)
+	lw		t6, 100(s5)
+	lw		t7, 104(s5)
+	lw		t8, 108(s5)
+	lw		t9, 112(s5)
+	lw		s8, 116(s5)
+	lw		ra, 120(s5)
+
+	/* Protect access to the k registers, and others. */
+	di
+	ehb
+
+	/* Decrement the nesting count. */
+	la		k0, uxInterruptNesting
+	lw		k1, (k0)
+	addiu	k1, k1, -1
+	sw		k1, 0(k0)
+
+	lw		k0, portSTATUS_STACK_LOCATION(s5)
+	lw		k1, portEPC_STACK_LOCATION(s5)
+
+	/* Leave the stack in its original state.  First load sp from s5, then
+	restore s5 from the stack. */
+	add		sp, zero, s5
+	lw		s5, 40(sp)
+	addiu   sp, sp, portCONTEXT_SIZE
+
+	mtc0	k0, _CP0_STATUS
+	mtc0	k1, _CP0_EPC
+	ehb
+	eret
+	nop
+
+	.endm
+
+#endif /* #ifdef __LANGUAGE_ASSEMBLY__ */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port.c
new file mode 100644
index 0000000..108f263
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port.c
@@ -0,0 +1,345 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the PIC32MEC14xx  port.
+ *----------------------------------------------------------*/
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Microchip includes. */
+#include <xc.h>
+#include <cp0defs.h>
+
+#if !defined(__MEC__)
+	#error This port is designed to work with XC32 on MEC14xx.  Please update your C compiler version or settings.
+#endif
+
+#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
+	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
+#endif
+
+/* Bits within various registers. */
+#define portIE_BIT					( 0x00000001 )
+#define portEXL_BIT					( 0x00000002 )
+
+/* The EXL bit is set to ensure interrupts do not occur while the context of
+the first task is being restored.  MEC14xx does not have DSP HW. */
+#define portINITIAL_SR				( portIE_BIT | portEXL_BIT )
+
+/* MEC14xx RTOS Timer MMCR's. */
+#define portMMCR_RTMR_PRELOAD	*((volatile uint32_t *)(0xA0007404ul))
+#define portMMCR_RTMR_CONTROL	*((volatile uint32_t *)(0xA0007408ul))
+
+/* MEC14xx JTVIC external interrupt controller is mapped to M14K closely-coupled
+peripheral space. */
+#define portGIRQ23_RTOS_TIMER_BITPOS	( 4 )
+#define portGIRQ23_RTOS_TIMER_MASK		( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) )
+#define portMMCR_JTVIC_GIRQ23_SRC		*((volatile uint32_t *)(0xBFFFC0F0ul))
+#define portMMCR_JTVIC_GIRQ23_SETEN		*((volatile uint32_t *)(0xBFFFC0F4ul))
+#define portMMCR_JTVIC_GIRQ23_PRIA		*((volatile uint32_t *)(0xBFFFC3F0ul))
+
+/* MIPS Software Interrupts are routed through JTVIC GIRQ24 */
+#define portGIRQ24_M14K_SOFTIRQ0_BITPOS	( 1 )
+#define portGIRQ24_M14K_SOFTIRQ0_MASK	( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) )
+#define portMMCR_JTVIC_GIRQ24_SRC		*((volatile uint32_t *)(0xBFFFC100ul))
+#define portMMCR_JTVIC_GIRQ24_SETEN		*((volatile uint32_t *)(0xBFFFC104ul))
+#define portMMCR_JTVIC_GIRQ24_PRIA		*((volatile uint32_t *)(0xBFFFC400ul))
+
+/*
+By default port.c generates its tick interrupt from the RTOS timer.  The user
+can override this behaviour by:
+	1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
+	   which is the function that configures the timer.  The function is defined
+	   as a weak symbol in this file so if the same function name is used in the
+	   application code then the version in the application code will be linked
+	   into the application in preference to the version defined in this file.
+	2: Provide a vector implementation in port_asm.S that overrides the default
+	   behaviour for the specified interrupt vector.
+	3: Specify the correct bit to clear the interrupt during the timer interrupt
+	   handler.
+*/
+#ifndef configTICK_INTERRUPT_VECTOR
+	#define configTICK_INTERRUPT_VECTOR girq23_b4
+	#define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK
+#else
+	#ifndef configCLEAR_TICK_TIMER_INTERRUPT
+		#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
+	#endif
+#endif
+
+/* Let the user override the pre-loading of the initial RA with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
+in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
+stack checking.  A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
+#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
+
+	/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
+	the task stacks, and so will legitimately appear in many positions within
+	the ISR stack. */
+    #define portISR_STACK_FILL_BYTE	0xee
+
+	static const uint8_t ucExpectedStackBytes[] = {
+							portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+							portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+							portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+							portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+							portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };	\
+
+	#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
+	/* Define the function away. */
+	#define portCHECK_ISR_STACK()
+#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Records the interrupt nesting depth.  This is initialised to one as it is
+decremented to 0 when the first task starts. */
+volatile UBaseType_t uxInterruptNesting = 0x01;
+
+/* Stores the task stack pointer when a switch is made to use the system stack. */
+UBaseType_t uxSavedTaskStackPointer = 0;
+
+/* The stack used by interrupt service routines that cause a context switch. */
+StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
+
+/* The top of stack value ensures there is enough space to store 6 registers on
+the callers stack, as some functions seem to want to do this. */
+const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Ensure byte alignment is maintained when leaving this function. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0x12345678;	/* Word to which the stack pointer will be left pointing after context restore. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) ulPortGetCP0Cause();
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) portINITIAL_SR;	/* CP0_STATUS */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) pxCode; 		/* CP0_EPC */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS;	/* ra */
+	pxTopOfStack -= 15;
+
+	*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
+	pxTopOfStack -= 15;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static __inline uint32_t prvDisableInterrupt( void )
+{
+uint32_t prev_state;
+
+	__asm volatile( "di %0; ehb" : "=r" ( prev_state ) :: "memory" );
+	return prev_state;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxSavedTaskStackPointer == 0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup a timer for a regular tick.  This function uses the RTOS timer.
+ * The function is declared weak so an application writer can use a different
+ * timer by redefining this implementation.  If a different timer is used then
+ * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to
+ * ensure the RTOS provided tick interrupt handler is installed on the correct
+ * vector number.
+ */
+__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
+{
+/* MEC14xx RTOS Timer whose input clock is 32KHz. */
+const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
+
+	configASSERT( ulPreload != 0UL );
+
+	/* Configure the RTOS timer. */
+	portMMCR_RTMR_CONTROL = 0ul;
+	portMMCR_RTMR_PRELOAD = ulPreload;
+
+	/* Configure interrupts from the RTOS timer. */
+	portMMCR_JTVIC_GIRQ23_SRC = ( portGIRQ23_RTOS_TIMER_MASK );
+	portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 16 );
+	portMMCR_JTVIC_GIRQ23_PRIA |= ( ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) ) << 16 );
+	portMMCR_JTVIC_GIRQ23_SETEN = ( portGIRQ23_RTOS_TIMER_MASK );
+
+	/* Enable the RTOS timer. */
+	portMMCR_RTMR_CONTROL = 0x0Fu;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler(void)
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxInterruptNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+extern void *pxCurrentTCB;
+
+	#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+	{
+		/* Fill the ISR stack to make it easy to asses how much is being used. */
+		memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
+	}
+	#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+	/* Clear the software interrupt flag. */
+	portMMCR_JTVIC_GIRQ24_SRC = (portGIRQ24_M14K_SOFTIRQ0_MASK);
+
+	/* Set software timer priority.  Each GIRQn has one nibble containing its
+	priority */
+	portMMCR_JTVIC_GIRQ24_PRIA &= ~(0xF0ul);
+	portMMCR_JTVIC_GIRQ24_PRIA |= ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) << 4 );
+
+	/* Enable software interrupt. */
+	portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
+
+	/* Setup the timer to generate the tick.  Interrupts will have been disabled
+	by the time we get here. */
+	vApplicationSetupTickTimerInterrupt();
+
+	/* Start the highest priority task that has been created so far.  Its stack
+	location is loaded into uxSavedTaskStackPointer. */
+	uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
+	vPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS. */
+	prvTaskExitError();
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortIncrementTick( void )
+{
+UBaseType_t uxSavedStatus;
+uint32_t ulCause;
+
+	uxSavedStatus = uxPortSetInterruptMaskFromISR();
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			ulCause = ulPortGetCP0Cause();
+			ulCause |= ( 1ul << 8UL );
+			vPortSetCP0Cause( ulCause );
+		}
+	}
+	vPortClearInterruptMaskFromISR( uxSavedStatus );
+
+	/* Look for the ISR stack getting near or past its limit. */
+	portCHECK_ISR_STACK();
+
+	/* Clear timer interrupt. */
+	configCLEAR_TICK_TIMER_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxPortSetInterruptMaskFromISR( void )
+{
+UBaseType_t uxSavedStatusRegister;
+
+	prvDisableInterrupt();
+	uxSavedStatusRegister = ulPortGetCP0Status() | 0x01;
+
+	/* This clears the IPL bits, then sets them to
+	configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
+	from an interrupt that has a priority above
+	configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
+	can only result in the IPL being unchanged or raised, and therefore never
+	lowered. */
+	vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
+
+	return uxSavedStatusRegister;
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
+{
+	vPortSetCP0Status( uxSavedStatusRegister );
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port_asm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port_asm.S
new file mode 100644
index 0000000..fea9443
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port_asm.S
@@ -0,0 +1,348 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* FreeRTOS includes. */
+#include "FreeRTOSConfig.h"
+#include "ISR_Support.h"
+
+/* Microchip includes. */
+#include <xc.h>
+#include <sys/asm.h>
+
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern vPortIncrementTick
+	.extern xISRStackTop
+
+	PORT_CPP_JTVIC_BASE = 0xBFFFC000
+	PORT_CCP_JTVIC_GIRQ24_SRC = 0xBFFFC100
+
+	.global vPortStartFirstTask .text
+	.global vPortYieldISR .text
+	.global vPortTickInterruptHandler .text
+
+
+/******************************************************************/
+
+
+/***************************************************************
+*  The following is needed to locate the
+*  vPortTickInterruptHandler function into the correct vector
+*  MEC14xx - This ISR will only be used if HW timers' interrupts
+*  in GIRQ23 are disaggregated.
+*
+***************************************************************/
+
+	.set  noreorder
+	.set  noat
+	.set  micromips
+
+	.section .text, code
+	.ent    vPortTickInterruptHandler
+
+#if configTIMERS_DISAGGREGATED_ISRS == 0
+
+	.globl girq23_isr
+
+girq23_isr:
+vPortTickInterruptHandler:
+
+	portSAVE_CONTEXT
+
+	jal		girq23_handler
+	nop
+
+	portRESTORE_CONTEXT
+
+.end vPortTickInterruptHandler
+
+#else
+
+	.globl girq23_b4
+
+girq23_b4:
+vPortTickInterruptHandler:
+
+	portSAVE_CONTEXT
+
+	jal		vPortIncrementTick
+	nop
+
+	portRESTORE_CONTEXT
+
+.end vPortTickInterruptHandler
+
+#endif /* #if configTIMERS_DISAGGREGATED_ISRS == 0 */
+
+/******************************************************************/
+
+	.set	micromips
+	.set	noreorder
+	.set	noat
+
+	.section .text, code
+	.ent	vPortStartFirstTask
+
+vPortStartFirstTask:
+
+	/* Simply restore the context of the highest priority task that has
+	been created so far. */
+	portRESTORE_CONTEXT
+
+.end vPortStartFirstTask
+
+
+
+/*******************************************************************/
+
+/***************************************************************
+*  The following is needed to locate the vPortYieldISR function into the correct
+* vector.
+***************************************************************/
+
+	.set micromips
+	.set noreorder
+	.set noat
+
+	.section .text, code
+
+	.global vPortYieldISR
+
+
+#if configCPU_DISAGGREGATED_ISRS == 0
+	.global girq24_isr
+	.ent girq24_isr
+girq24_isr:
+	la		k0, PORT_CPP_JTVIC_BASE
+	lw		k0, 0x10C(k0)
+	andi	k1, k0, 0x2
+	bgtz	k1, vPortYieldISR
+	nop
+
+	portSAVE_CONTEXT
+
+	jal		girq24_b_0_2
+
+	portRESTORE_CONTEXT
+
+	.end girq24_isr
+
+#else
+	.global girq24_b1
+girq24_b1:
+#endif
+		.ent  vPortYieldISR
+vPortYieldISR:
+
+	/* Make room for the context. First save the current status so it can be
+	manipulated, and the cause and EPC registers so thier original values
+	are captured. */
+	addiu	sp, sp, -portCONTEXT_SIZE
+	mfc0	k1, _CP0_STATUS
+
+	/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
+	maintain the values of these registers across the ISR. */
+	sw		s6, 44(sp)
+	sw		s5, 40(sp)
+	sw		k1, portSTATUS_STACK_LOCATION(sp)
+
+	/* Prepare to re-enable interrupts above the kernel priority. */
+	ins		k1, zero, 10, 7		 /* Clear IPL bits 0:6. */
+	ins		k1, zero, 18, 1		 /* Clear IPL bit 7  */
+	ori		k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
+	ins		k1, zero, 1, 4		  /* Clear EXL, ERL and UM. */
+
+	/* s5 is used as the frame pointer. */
+	add		s5, zero, sp
+
+	/* Swap to the system stack.  This is not conditional on the nesting
+	count as this interrupt is always the lowest priority and therefore
+	the nesting is always 0. */
+	la		sp, xISRStackTop
+	lw		sp, (sp)
+
+	/* Set the nesting count. */
+	la		k0, uxInterruptNesting
+	addiu   s6, zero, 1
+	sw		s6, 0(k0)
+
+	/* s6 holds the EPC value, this is saved with the rest of the context
+	after interrupts are enabled. */
+	mfc0	s6, _CP0_EPC
+
+	/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+	mtc0	k1, _CP0_STATUS
+
+	/* Save the context into the space just created.  s6 is saved again
+	here as it now contains the EPC value. */
+	sw		ra, 120(s5)
+	sw		s8, 116(s5)
+	sw		t9, 112(s5)
+	sw		t8, 108(s5)
+	sw		t7, 104(s5)
+	sw		t6, 100(s5)
+	sw		t5, 96(s5)
+	sw		t4, 92(s5)
+	sw		t3, 88(s5)
+	sw		t2, 84(s5)
+	sw		t1, 80(s5)
+	sw		t0, 76(s5)
+	sw		a3, 72(s5)
+	sw		a2, 68(s5)
+	sw		a1, 64(s5)
+	sw		a0, 60(s5)
+	sw		v1, 56(s5)
+	sw		v0, 52(s5)
+	sw		s7, 48(s5)
+	sw		s6, portEPC_STACK_LOCATION(s5)
+	/* s5 and s6 has already been saved. */
+	sw		s4, 36(s5)
+	sw		s3, 32(s5)
+	sw		s2, 28(s5)
+	sw		s1, 24(s5)
+	sw		s0, 20(s5)
+	sw		$1, 16(s5)
+
+	/* s7 is used as a scratch register as this should always be saved acro ss
+	nesting interrupts. */
+	mfhi	s7
+	sw		s7, 12(s5)
+	mflo	s7
+	sw		s7, 8(s5)
+
+	/* Save the stack pointer to the task. */
+	la		s7, pxCurrentTCB
+	lw		s7, (s7)
+	sw		s5, (s7)
+
+	/* Set the interrupt mask to the max priority that can use the API.
+	The yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY
+	which is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only
+	ever raise the IPL value and never lower it. */
+	di
+	ehb
+	mfc0	s7, _CP0_STATUS
+	ins		s7, zero, 10, 7
+	ins		s7, zero, 18, 1
+	ori		s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
+
+	/* This mtc0 re-enables interrupts, but only above
+	configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+	mtc0	s6, _CP0_STATUS
+	ehb
+
+	/* Clear the software interrupt in the core. */
+	mfc0	s6, _CP0_CAUSE
+	ins		s6, zero, 8, 1
+	mtc0	s6, _CP0_CAUSE
+	ehb
+
+	/* Clear the interrupt in the interrupt controller.
+	MEC14xx GIRQ24 Source bit[1] = 1 to clear */
+	la		s6, PORT_CCP_JTVIC_GIRQ24_SRC
+	addiu	s4, zero, 2
+	sw		s4, (s6)
+	jal		vTaskSwitchContext
+	nop
+
+	/* Clear the interrupt mask again. The saved status value is still in s7 */
+	mtc0	s7, _CP0_STATUS
+	ehb
+
+	/* Restore the stack pointer from the TCB. */
+	la		s0, pxCurrentTCB
+	lw		s0, (s0)
+	lw		s5, (s0)
+
+	/* Restore the rest of the context. */
+	lw		s0, 8(s5)
+	mtlo	s0
+	lw		s0, 12(s5)
+	mthi	s0
+
+	lw		$1, 16(s5)
+	lw		s0, 20(s5)
+	lw		s1, 24(s5)
+	lw		s2, 28(s5)
+	lw		s3, 32(s5)
+	lw		s4, 36(s5)
+
+	/* s5 is loaded later. */
+	lw		s6, 44(s5)
+	lw		s7, 48(s5)
+	lw		v0, 52(s5)
+	lw		v1, 56(s5)
+	lw		a0, 60(s5)
+	lw		a1, 64(s5)
+	lw		a2, 68(s5)
+	lw		a3, 72(s5)
+	lw		t0, 76(s5)
+	lw		t1, 80(s5)
+	lw		t2, 84(s5)
+	lw		t3, 88(s5)
+	lw		t4, 92(s5)
+	lw		t5, 96(s5)
+	lw		t6, 100(s5)
+	lw		t7, 104(s5)
+	lw		t8, 108(s5)
+	lw		t9, 112(s5)
+	lw		s8, 116(s5)
+	lw		ra, 120(s5)
+
+	/* Protect access to the k registers, and others. */
+	di
+	ehb
+
+	/* Set nesting back to zero.  As the lowest priority interrupt this
+	interrupt cannot have nested. */
+	la		k0, uxInterruptNesting
+	sw		zero, 0(k0)
+
+	/* Switch back to use the real stack pointer. */
+	add		sp, zero, s5
+
+	/* Restore the real s5 value. */
+	lw		s5, 40(sp)
+
+	/* Pop the status and epc values. */
+	lw		k1, portSTATUS_STACK_LOCATION(sp)
+	lw		k0, portEPC_STACK_LOCATION(sp)
+
+	/* Remove stack frame. */
+	addiu	sp, sp, portCONTEXT_SIZE
+
+	mtc0	k1, _CP0_STATUS
+	mtc0	k0, _CP0_EPC
+	ehb
+	eret
+	nop
+
+.end	vPortYieldISR
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/portmacro.h
new file mode 100644
index 0000000..2b95626
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/portmacro.h
@@ -0,0 +1,252 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT  8
+#define portSTACK_GROWTH    -1
+#define portTICK_PERIOD_MS  ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portIPL_SHIFT       ( 10UL )
+/* Don't straddle the CEE bit.  Interrupts calling FreeRTOS functions should
+never have higher IPL bits set anyway. */
+#define portALL_IPL_BITS    ( 0x7FUL << portIPL_SHIFT )
+#define portSW0_BIT         ( 0x01 << 8 )
+
+/* Interrupt priority conversion */
+#define portIPL_TO_CODE( iplNumber )    ( ( iplNumber >> 1 ) & 0x03ul )
+#define portCODE_TO_IPL( iplCode )      ( ( iplCode << 1 ) | 0x01ul )
+
+/*-----------------------------------------------------------*/
+
+static inline uint32_t ulPortGetCP0Status( void )
+{
+uint32_t rv;
+
+	__asm volatile(
+			"\n\t"
+			"mfc0 %0,$12,0      \n\t"
+			: "=r" ( rv ) :: );
+
+	return rv;
+}
+/*-----------------------------------------------------------*/
+
+static inline void vPortSetCP0Status( uint32_t new_status)
+{
+	( void ) new_status;
+
+	__asm__ __volatile__(
+			"\n\t"
+			"mtc0 %0,$12,0      \n\t"
+			"ehb                \n\t"
+			:
+			:"r" ( new_status ) : );
+}
+/*-----------------------------------------------------------*/
+
+static inline uint32_t ulPortGetCP0Cause( void )
+{
+uint32_t rv;
+
+	__asm volatile(
+			"\n\t"
+			"mfc0 %0,$13,0      \n\t"
+			: "=r" ( rv ) :: );
+
+    return rv;
+}
+/*-----------------------------------------------------------*/
+
+static inline void vPortSetCP0Cause( uint32_t new_cause )
+{
+	( void ) new_cause;
+
+	__asm__ __volatile__(
+			"\n\t"
+			"mtc0 %0,$13,0      \n\t"
+			"ehb                \n\t"
+			:
+			:"r" ( new_cause ) : );
+}
+/*-----------------------------------------------------------*/
+
+/* This clears the IPL bits, then sets them to
+configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
+configASSERT() is defined to ensure an assertion handler does not inadvertently
+attempt to lower the IPL when the call to assert was triggered because the IPL
+value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
+safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
+those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
+ensure API function and interrupt entry is as fast and as simple as possible. */
+#ifdef configASSERT
+    #define portDISABLE_INTERRUPTS() 																			\
+	{ 																											\
+	uint32_t ulStatus; 																							\
+		/* Mask interrupts at and below the kernel interrupt priority. */  										\
+		ulStatus = ulPortGetCP0Status(); 																		\
+		/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ 									\
+		if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) 		\
+		{ 																										\
+			ulStatus &= ~portALL_IPL_BITS;  																	\
+			vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); 		\
+		} 																										\
+    }
+#else /* configASSERT */
+	#define portDISABLE_INTERRUPTS() 																			\
+	{ 																											\
+	uint32_t ulStatus;  																						\
+		/* Mask interrupts at and below the kernel interrupt priority. */ 										\
+		ulStatus = ulPortGetCP0Status(); 																		\
+		ulStatus &= ~portALL_IPL_BITS; 																			\
+		vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); 			\
+	}
+#endif /* configASSERT */
+
+#define portENABLE_INTERRUPTS() 			\
+{ 											\
+uint32_t ulStatus; 							\
+	/* Unmask all interrupts. */ 			\
+	ulStatus = ulPortGetCP0Status(); 		\
+	ulStatus &= ~portALL_IPL_BITS; 			\
+	vPortSetCP0Status( ulStatus ); 			\
+}
+
+
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portCRITICAL_NESTING_IN_TCB	1
+#define portENTER_CRITICAL()		vTaskEnterCritical()
+#define portEXIT_CRITICAL()			vTaskExitCritical()
+
+extern UBaseType_t uxPortSetInterruptMaskFromISR();
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
+
+#endif /* taskRECORD_READY_PRIORITY */
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+#define portYIELD() 						\
+{ 											\
+uint32_t ulCause; 							\
+	/* Trigger software interrupt. */ 		\
+	ulCause = ulPortGetCP0Cause(); 			\
+	ulCause |= portSW0_BIT; 				\
+	vPortSetCP0Cause( ulCause ); 			\
+}
+
+extern volatile UBaseType_t uxInterruptNesting;
+#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
+
+#define portNOP() __asm volatile ( "nop" )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#define portEND_SWITCHING_ISR( xSwitchRequired ) 	if( xSwitchRequired )	\
+													{ 						\
+														portYIELD();		\
+													}
+
+/* Required by the kernel aware debugger. */
+#ifdef __DEBUG
+    #define portREMOVE_STATIC_QUALIFIER
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MX/ISR_Support.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MX/ISR_Support.h
new file mode 100644
index 0000000..4409fde
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MX/ISR_Support.h
@@ -0,0 +1,191 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOSConfig.h"
+
+#define portCONTEXT_SIZE 132
+#define portEPC_STACK_LOCATION	124
+#define portSTATUS_STACK_LOCATION 128
+
+/******************************************************************/
+.macro	portSAVE_CONTEXT
+
+	/* Make room for the context. First save the current status so it can be
+	manipulated, and the cause and EPC registers so their original values are
+	captured. */
+	mfc0		k0, _CP0_CAUSE
+	addiu		sp,	sp, -portCONTEXT_SIZE
+	mfc0		k1, _CP0_STATUS
+
+	/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
+	maintain the values of these registers across the ISR. */
+	sw			s6, 44(sp)
+	sw			s5, 40(sp)
+	sw			k1, portSTATUS_STACK_LOCATION(sp)
+
+	/* Prepare to enable interrupts above the current priority. */
+	srl			k0, k0, 0xa
+	ins 		k1, k0, 10, 6
+	ins			k1, zero, 1, 4
+
+	/* s5 is used as the frame pointer. */
+	add			s5, zero, sp
+
+	/* Check the nesting count value. */
+	la			k0, uxInterruptNesting
+	lw			s6, (k0)
+
+	/* If the nesting count is 0 then swap to the the system stack, otherwise
+	the system stack is already being used. */
+	bne			s6, zero, 1f
+	nop
+
+	/* Swap to the system stack. */
+	la			sp, xISRStackTop
+	lw			sp, (sp)
+
+	/* Increment and save the nesting count. */
+1:	addiu		s6, s6, 1
+	sw			s6, 0(k0)
+
+	/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
+	mfc0 		s6, _CP0_EPC
+
+	/* Re-enable interrupts. */
+	mtc0		k1, _CP0_STATUS
+
+	/* Save the context into the space just created.  s6 is saved again
+	here as it now contains the EPC value.  No other s registers need be
+	saved. */
+	sw			ra, 120(s5)
+	sw			s8, 116(s5)
+	sw			t9, 112(s5)
+	sw			t8, 108(s5)
+	sw			t7, 104(s5)
+	sw			t6, 100(s5)
+	sw			t5, 96(s5)
+	sw			t4, 92(s5)
+	sw			t3, 88(s5)
+	sw			t2, 84(s5)
+	sw			t1, 80(s5)
+	sw			t0, 76(s5)
+	sw			a3, 72(s5)
+	sw			a2, 68(s5)
+	sw			a1, 64(s5)
+	sw			a0, 60(s5)
+	sw			v1, 56(s5)
+	sw			v0, 52(s5)
+	sw			s6, portEPC_STACK_LOCATION(s5)
+	sw			$1, 16(s5)
+
+	/* s6 is used as a scratch register. */
+	mfhi		s6
+	sw			s6, 12(s5)
+	mflo		s6
+	sw			s6, 8(s5)
+
+	/* Update the task stack pointer value if nesting is zero. */
+	la			s6, uxInterruptNesting
+	lw			s6, (s6)
+	addiu		s6, s6, -1
+	bne			s6, zero, 1f
+	nop
+
+	/* Save the stack pointer. */
+	la			s6, uxSavedTaskStackPointer
+	sw			s5, (s6)
+1:
+	.endm
+
+/******************************************************************/
+.macro	portRESTORE_CONTEXT
+
+	/* Restore the stack pointer from the TCB.  This is only done if the
+	nesting count is 1. */
+	la			s6, uxInterruptNesting
+	lw			s6, (s6)
+	addiu		s6, s6, -1
+	bne			s6, zero, 1f
+	nop
+	la			s6, uxSavedTaskStackPointer
+	lw			s5, (s6)
+
+	/* Restore the context. */
+1:	lw			s6, 8(s5)
+	mtlo		s6
+	lw			s6, 12(s5)
+	mthi		s6
+	lw			$1, 16(s5)
+	/* s6 is loaded as it was used as a scratch register and therefore saved
+	as part of the interrupt context. */
+	lw			s6, 44(s5)
+	lw			v0, 52(s5)
+	lw			v1, 56(s5)
+	lw			a0, 60(s5)
+	lw			a1, 64(s5)
+	lw			a2, 68(s5)
+	lw			a3, 72(s5)
+	lw			t0, 76(s5)
+	lw			t1, 80(s5)
+	lw			t2, 84(s5)
+	lw			t3, 88(s5)
+	lw			t4, 92(s5)
+	lw			t5, 96(s5)
+	lw			t6, 100(s5)
+	lw			t7, 104(s5)
+	lw			t8, 108(s5)
+	lw			t9, 112(s5)
+	lw			s8, 116(s5)
+	lw			ra, 120(s5)
+
+	/* Protect access to the k registers, and others. */
+	di
+	ehb
+
+	/* Decrement the nesting count. */
+	la			k0, uxInterruptNesting
+	lw			k1, (k0)
+	addiu		k1, k1, -1
+	sw			k1, 0(k0)
+
+	lw			k0, portSTATUS_STACK_LOCATION(s5)
+	lw			k1, portEPC_STACK_LOCATION(s5)
+
+	/* Leave the stack in its original state.  First load sp from s5, then
+	restore s5 from the stack. */
+	add			sp, zero, s5
+	lw			s5, 40(sp)
+	addiu		sp, sp,	portCONTEXT_SIZE
+
+	mtc0		k0, _CP0_STATUS
+	mtc0 		k1, _CP0_EPC
+	ehb
+	eret
+	nop
+
+	.endm
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MX/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MX/port.c
new file mode 100644
index 0000000..dc98f4a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MX/port.c
@@ -0,0 +1,334 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the PIC32MX port.
+  *----------------------------------------------------------*/
+
+#ifndef __XC
+    #error This port is designed to work with XC32.  Please update your C compiler version.
+#endif
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Hardware specifics. */
+#define portTIMER_PRESCALE	8
+#define portPRESCALE_BITS	1
+
+/* Bits within various registers. */
+#define portIE_BIT						( 0x00000001 )
+#define portEXL_BIT						( 0x00000002 )
+
+/* Bits within the CAUSE register. */
+#define portCORE_SW_0					( 0x00000100 )
+#define portCORE_SW_1					( 0x00000200 )
+
+/* The EXL bit is set to ensure interrupts do not occur while the context of
+the first task is being restored. */
+#define portINITIAL_SR					( portIE_BIT | portEXL_BIT )
+
+/*
+By default port.c generates its tick interrupt from TIMER1.  The user can
+override this behaviour by:
+	1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
+	   which is the function that configures the timer.  The function is defined
+	   as a weak symbol in this file so if the same function name is used in the
+	   application code then the version in the application code will be linked
+	   into the application in preference to the version defined in this file.
+	2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
+	   to generate the tick interrupt.  For example, when timer 1 is used then
+	   configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
+	   configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
+	3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
+	   timer used to generate the tick interrupt.  For example, when timer 1 is
+	   used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
+	   IFS0CLR = _IFS0_T1IF_MASK.
+*/
+#ifndef configTICK_INTERRUPT_VECTOR
+	#define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
+	#define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
+#else
+	#ifndef configCLEAR_TICK_TIMER_INTERRUPT
+		#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
+	#endif
+#endif
+
+/* Let the user override the pre-loading of the initial RA with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
+stack checking.  A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
+#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
+
+	/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
+	the task stacks, and so will legitimately appear in many positions within
+	the ISR stack. */
+	#define portISR_STACK_FILL_BYTE	0xee
+
+	static const uint8_t ucExpectedStackBytes[] = {
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };	\
+
+	#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
+	/* Define the function away. */
+	#define portCHECK_ISR_STACK()
+#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Place the prototype here to ensure the interrupt vector is correctly installed.
+ * Note that because the interrupt is written in assembly, the IPL setting in the
+ * following line of code has no effect.  The interrupt priority is set by the
+ * call to ConfigIntTimer1() in vApplicationSetupTickTimerInterrupt().
+ */
+extern void __attribute__( (interrupt(IPL1AUTO), vector( configTICK_INTERRUPT_VECTOR ))) vPortTickInterruptHandler( void );
+
+/*
+ * The software interrupt handler that performs the yield.  Note that, because
+ * the interrupt is written in assembly, the IPL setting in the following line of
+ * code has no effect.  The interrupt priority is set by the call to
+ * mConfigIntCoreSW0() in xPortStartScheduler().
+ */
+void __attribute__( (interrupt(IPL1AUTO), vector(_CORE_SOFTWARE_0_VECTOR))) vPortYieldISR( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Records the interrupt nesting depth.  This is initialised to one as it is
+decremented to 0 when the first task starts. */
+volatile UBaseType_t uxInterruptNesting = 0x01;
+
+/* Stores the task stack pointer when a switch is made to use the system stack. */
+UBaseType_t uxSavedTaskStackPointer = 0;
+
+/* The stack used by interrupt service routines that cause a context switch. */
+__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
+
+/* The top of stack value ensures there is enough space to store 6 registers on
+the callers stack, as some functions seem to want to do this. */
+const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Ensure 8 byte alignment is maintained when the context is popped from
+	 * stack. The size of the context is 33 words (132 bytes). */
+	pxTopOfStack--;
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0x12345678;	/* Word to which the stack pointer will be left pointing after context restore. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) _CP0_GET_CAUSE();
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) pxCode; 		/* CP0_EPC */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS;	/* ra */
+	pxTopOfStack -= 15;
+
+	*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
+	pxTopOfStack -= 15;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxSavedTaskStackPointer == 0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup a timer for a regular tick.  This function uses peripheral timer 1.
+ * The function is declared weak so an application writer can use a different
+ * timer by redefining this implementation.  If a different timer is used then
+ * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to
+ * ensure the RTOS provided tick interrupt handler is installed on the correct
+ * vector number.  When Timer 1 is used the vector number is defined as
+ * _TIMER_1_VECTOR.
+ */
+__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
+{
+const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1;
+
+	T1CON = 0x0000;
+	T1CONbits.TCKPS = portPRESCALE_BITS;
+	PR1 = ulCompareMatch;
+	IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
+
+	/* Clear the interrupt as a starting condition. */
+	IFS0bits.T1IF = 0;
+
+	/* Enable the interrupt. */
+	IEC0bits.T1IE = 1;
+
+	/* Start the timer. */
+	T1CONbits.TON = 1;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler(void)
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxInterruptNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+extern void *pxCurrentTCB;
+
+	#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+	{
+		/* Fill the ISR stack to make it easy to asses how much is being used. */
+		memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
+	}
+	#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+	/* Clear the software interrupt flag. */
+	IFS0CLR = _IFS0_CS0IF_MASK;
+
+	/* Set software timer priority. */
+	IPC0CLR = _IPC0_CS0IP_MASK;
+	IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION );
+
+	/* Enable software interrupt. */
+	IEC0CLR = _IEC0_CS0IE_MASK;
+	IEC0SET = 1 << _IEC0_CS0IE_POSITION;
+
+	/* Setup the timer to generate the tick.  Interrupts will have been
+	disabled by the time we get here. */
+	vApplicationSetupTickTimerInterrupt();
+
+	/* Kick off the highest priority task that has been created so far.
+	Its stack location is loaded into uxSavedTaskStackPointer. */
+	uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
+	vPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS. */
+	prvTaskExitError();
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortIncrementTick( void )
+{
+UBaseType_t uxSavedStatus;
+
+	uxSavedStatus = uxPortSetInterruptMaskFromISR();
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			_CP0_BIS_CAUSE( portCORE_SW_0 );
+		}
+	}
+	vPortClearInterruptMaskFromISR( uxSavedStatus );
+
+	/* Look for the ISR stack getting near or past its limit. */
+	portCHECK_ISR_STACK();
+
+	/* Clear timer interrupt. */
+	configCLEAR_TICK_TIMER_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxPortSetInterruptMaskFromISR( void )
+{
+UBaseType_t uxSavedStatusRegister;
+
+	__builtin_disable_interrupts();
+	uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
+	/* This clears the IPL bits, then sets them to
+	configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
+	from an interrupt that has a priority above
+	configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
+	can only result in the IPL being unchanged or raised, and therefore never
+	lowered. */
+	_CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
+
+	return uxSavedStatusRegister;
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
+{
+	_CP0_SET_STATUS( uxSavedStatusRegister );
+}
+/*-----------------------------------------------------------*/
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MX/port_asm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MX/port_asm.S
new file mode 100644
index 0000000..6271543
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MX/port_asm.S
@@ -0,0 +1,268 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include <xc.h>
+#include <sys/asm.h>
+#include "ISR_Support.h"
+
+
+	.set	nomips16
+ 	.set 	noreorder
+
+ 	.extern pxCurrentTCB
+ 	.extern vTaskSwitchContext
+ 	.extern vPortIncrementTick
+	.extern xISRStackTop
+
+ 	.global vPortStartFirstTask
+	.global vPortYieldISR
+	.global vPortTickInterruptHandler
+
+
+/******************************************************************/
+
+ 	.set		noreorder
+	.set 		noat
+ 	.ent		vPortTickInterruptHandler
+
+vPortTickInterruptHandler:
+
+	portSAVE_CONTEXT
+
+	jal 		vPortIncrementTick
+	nop
+
+	portRESTORE_CONTEXT
+
+	.end vPortTickInterruptHandler
+
+/******************************************************************/
+
+ 	.set		noreorder
+	.set 		noat
+ 	.ent		vPortStartFirstTask
+
+vPortStartFirstTask:
+
+	/* Simply restore the context of the highest priority task that has been
+	created so far. */
+	portRESTORE_CONTEXT
+
+	.end vPortStartFirstTask
+
+
+
+/*******************************************************************/
+
+	.set		noreorder
+	.set 		noat
+	.ent		vPortYieldISR
+
+vPortYieldISR:
+
+	/* Make room for the context. First save the current status so it can be
+	manipulated. */
+	addiu		sp, sp, -portCONTEXT_SIZE
+	mfc0		k1, _CP0_STATUS
+
+	/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
+	maintain the values of these registers across the ISR. */
+	sw			s6, 44(sp)
+	sw			s5, 40(sp)
+	sw			k1, portSTATUS_STACK_LOCATION(sp)
+
+	/* Prepare to re-enabled interrupt above the kernel priority. */
+	ins 		k1, zero, 10, 6
+	ori			k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
+	ins			k1, zero, 1, 4
+
+	/* s5 is used as the frame pointer. */
+	add			s5, zero, sp
+
+	/* Swap to the system stack.  This is not conditional on the nesting
+	count as this interrupt is always the lowest priority and therefore
+	the nesting is always 0. */
+	la			sp, xISRStackTop
+	lw			sp, (sp)
+
+	/* Set the nesting count. */
+	la			k0, uxInterruptNesting
+	addiu		s6, zero, 1
+	sw			s6, 0(k0)
+
+	/* s6 holds the EPC value, this is saved with the rest of the context
+	after interrupts are enabled. */
+	mfc0 		s6, _CP0_EPC
+
+	/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+	mtc0		k1, _CP0_STATUS
+
+	/* Save the context into the space just created.  s6 is saved again
+	here as it now contains the EPC value. */
+	sw			ra, 120(s5)
+	sw			s8, 116(s5)
+	sw			t9, 112(s5)
+	sw			t8, 108(s5)
+	sw			t7, 104(s5)
+	sw			t6, 100(s5)
+	sw			t5, 96(s5)
+	sw			t4, 92(s5)
+	sw			t3, 88(s5)
+	sw			t2, 84(s5)
+	sw			t1, 80(s5)
+	sw			t0, 76(s5)
+	sw			a3, 72(s5)
+	sw			a2, 68(s5)
+	sw			a1, 64(s5)
+	sw			a0, 60(s5)
+	sw			v1, 56(s5)
+	sw			v0, 52(s5)
+	sw			s7, 48(s5)
+	sw			s6, portEPC_STACK_LOCATION(s5)
+	/* s5 and s6 has already been saved. */
+	sw			s4, 36(s5)
+	sw			s3, 32(s5)
+	sw			s2, 28(s5)
+	sw			s1, 24(s5)
+	sw			s0, 20(s5)
+	sw			$1, 16(s5)
+
+	/* s7 is used as a scratch register as this should always be saved across
+	nesting interrupts. */
+	mfhi		s7
+	sw			s7, 12(s5)
+	mflo		s7
+	sw			s7, 8(s5)
+
+	/* Save the stack pointer to the task. */
+	la			s7, pxCurrentTCB
+	lw			s7, (s7)
+	sw			s5, (s7)
+
+	/* Set the interrupt mask to the max priority that can use the API.  The
+	yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
+	is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
+	raise the IPL value and never lower it. */
+	di
+	ehb
+	mfc0		s7, _CP0_STATUS
+	ins 		s7, zero, 10, 6
+	ori			s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
+
+	/* This mtc0 re-enables interrupts, but only above
+	configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+	mtc0		s6, _CP0_STATUS
+	ehb
+
+	/* Clear the software interrupt in the core. */
+	mfc0		s6, _CP0_CAUSE
+	ins			s6, zero, 8, 1
+	mtc0		s6, _CP0_CAUSE
+	ehb
+
+	/* Clear the interrupt in the interrupt controller. */
+	la			s6, IFS0CLR
+	addiu		s4, zero, 2
+	sw			s4, (s6)
+
+	jal			vTaskSwitchContext
+	nop
+
+	/* Clear the interrupt mask again.  The saved status value is still in s7. */
+	mtc0		s7, _CP0_STATUS
+	ehb
+
+	/* Restore the stack pointer from the TCB. */
+	la			s0, pxCurrentTCB
+	lw			s0, (s0)
+	lw			s5, (s0)
+
+	/* Restore the rest of the context. */
+	lw			s0, 8(s5)
+	mtlo		s0
+	lw			s0, 12(s5)
+	mthi		s0
+	lw			$1, 16(s5)
+	lw			s0, 20(s5)
+	lw			s1, 24(s5)
+	lw			s2, 28(s5)
+	lw			s3, 32(s5)
+	lw			s4, 36(s5)
+	/* s5 is loaded later. */
+	lw			s6, 44(s5)
+	lw			s7, 48(s5)
+	lw			v0, 52(s5)
+	lw			v1, 56(s5)
+	lw			a0, 60(s5)
+	lw			a1, 64(s5)
+	lw			a2, 68(s5)
+	lw			a3, 72(s5)
+	lw			t0, 76(s5)
+	lw			t1, 80(s5)
+	lw			t2, 84(s5)
+	lw			t3, 88(s5)
+	lw			t4, 92(s5)
+	lw			t5, 96(s5)
+	lw			t6, 100(s5)
+	lw			t7, 104(s5)
+	lw			t8, 108(s5)
+	lw			t9, 112(s5)
+	lw			s8, 116(s5)
+	lw			ra, 120(s5)
+
+	/* Protect access to the k registers, and others. */
+	di
+	ehb
+
+	/* Set nesting back to zero.  As the lowest priority interrupt this
+	interrupt cannot have nested. */
+	la			k0, uxInterruptNesting
+	sw			zero, 0(k0)
+
+	/* Switch back to use the real stack pointer. */
+	add			sp, zero, s5
+
+	/* Restore the real s5 value. */
+	lw			s5, 40(sp)
+
+	/* Pop the status and epc values. */
+	lw			k1, portSTATUS_STACK_LOCATION(sp)
+	lw			k0, portEPC_STACK_LOCATION(sp)
+
+	/* Remove stack frame. */
+	addiu		sp, sp, portCONTEXT_SIZE
+
+	mtc0		k1, _CP0_STATUS
+	mtc0 		k0, _CP0_EPC
+	ehb
+	eret
+	nop
+
+	.end		vPortYieldISR
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MX/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MX/portmacro.h
new file mode 100644
index 0000000..0495e18
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MX/portmacro.h
@@ -0,0 +1,204 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* System include files */
+#include <xc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portIPL_SHIFT				( 10UL )
+#define portALL_IPL_BITS			( 0x3fUL << portIPL_SHIFT )
+#define portSW0_BIT					( 0x01 << 8 )
+
+/* This clears the IPL bits, then sets them to
+configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
+configASSERT() is defined to ensure an assertion handler does not inadvertently
+attempt to lower the IPL when the call to assert was triggered because the IPL
+value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
+safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
+those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
+ensure API function and interrupt entry is as fast and as simple as possible. */
+#ifdef configASSERT
+	#define portDISABLE_INTERRUPTS()											\
+	{																			\
+	uint32_t ulStatus;														\
+																				\
+		/* Mask interrupts at and below the kernel interrupt priority. */		\
+		ulStatus = _CP0_GET_STATUS();											\
+																				\
+		/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */	\
+		if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
+		{																		\
+			ulStatus &= ~portALL_IPL_BITS;										\
+			_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+		}																		\
+	}
+#else /* configASSERT */
+	#define portDISABLE_INTERRUPTS()										\
+	{																		\
+	uint32_t ulStatus;													\
+																			\
+		/* Mask interrupts at and below the kernel interrupt priority. */	\
+		ulStatus = _CP0_GET_STATUS();										\
+		ulStatus &= ~portALL_IPL_BITS;										\
+		_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+	}
+#endif /* configASSERT */
+
+#define portENABLE_INTERRUPTS()											\
+{																		\
+uint32_t ulStatus;													\
+																		\
+	/* Unmask all interrupts. */										\
+	ulStatus = _CP0_GET_STATUS();										\
+	ulStatus &= ~portALL_IPL_BITS;										\
+	_CP0_SET_STATUS( ulStatus );										\
+}
+
+
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portCRITICAL_NESTING_IN_TCB	1
+#define portENTER_CRITICAL()		vTaskEnterCritical()
+#define portEXIT_CRITICAL()			vTaskExitCritical()
+
+extern UBaseType_t uxPortSetInterruptMaskFromISR();
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
+
+#endif /* taskRECORD_READY_PRIORITY */
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+#define portYIELD()								\
+{												\
+uint32_t ulCause;							\
+												\
+	/* Trigger software interrupt. */			\
+	ulCause = _CP0_GET_CAUSE();					\
+	ulCause |= portSW0_BIT;						\
+	_CP0_SET_CAUSE( ulCause );					\
+}
+
+extern volatile UBaseType_t uxInterruptNesting;
+#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
+
+#define portNOP()	__asm volatile ( "nop" )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#define portEND_SWITCHING_ISR( xSwitchRequired )	if( xSwitchRequired )	\
+													{						\
+														portYIELD();		\
+													}
+
+/* Required by the kernel aware debugger. */
+#ifdef __DEBUG
+	#define portREMOVE_STATIC_QUALIFIER
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MZ/ISR_Support.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MZ/ISR_Support.h
new file mode 100644
index 0000000..73e7b58
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MZ/ISR_Support.h
@@ -0,0 +1,432 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOSConfig.h"
+
+#define portCONTEXT_SIZE                160
+#define portEPC_STACK_LOCATION          152
+#define portSTATUS_STACK_LOCATION       156
+#define portFPCSR_STACK_LOCATION        0
+#define portTASK_HAS_FPU_STACK_LOCATION     0
+#define portFPU_CONTEXT_SIZE            264
+
+/******************************************************************/
+.macro  portSAVE_FPU_REGS    offset, base
+    /* Macro to assist with saving just the FPU registers to the
+     * specified address and base offset,
+     * offset is a constant, base is the base pointer register  */
+
+	sdc1		$f31, \offset + 248(\base)
+	sdc1		$f30, \offset + 240(\base)
+	sdc1		$f29, \offset + 232(\base)
+	sdc1		$f28, \offset + 224(\base)
+	sdc1		$f27, \offset + 216(\base)
+	sdc1		$f26, \offset + 208(\base)
+	sdc1		$f25, \offset + 200(\base)
+	sdc1		$f24, \offset + 192(\base)
+	sdc1		$f23, \offset + 184(\base)
+	sdc1		$f22, \offset + 176(\base)
+	sdc1		$f21, \offset + 168(\base)
+	sdc1		$f20, \offset + 160(\base)
+	sdc1		$f19, \offset + 152(\base)
+	sdc1		$f18, \offset + 144(\base)
+	sdc1		$f17, \offset + 136(\base)
+	sdc1		$f16, \offset + 128(\base)
+	sdc1		$f15, \offset + 120(\base)
+	sdc1		$f14, \offset + 112(\base)
+	sdc1		$f13, \offset + 104(\base)
+	sdc1		$f12, \offset + 96(\base)
+	sdc1		$f11, \offset + 88(\base)
+	sdc1		$f10, \offset + 80(\base)
+	sdc1		$f9, \offset + 72(\base)
+	sdc1		$f8, \offset + 64(\base)
+	sdc1		$f7, \offset + 56(\base)
+	sdc1		$f6, \offset + 48(\base)
+	sdc1		$f5, \offset + 40(\base)
+	sdc1		$f4, \offset + 32(\base)
+	sdc1		$f3, \offset + 24(\base)
+	sdc1		$f2, \offset + 16(\base)
+	sdc1		$f1, \offset + 8(\base)
+	sdc1		$f0, \offset + 0(\base)
+
+    .endm
+
+/******************************************************************/
+.macro  portLOAD_FPU_REGS    offset, base
+    /* Macro to assist with loading just the FPU registers from the
+     * specified address and base offset, offset is a constant,
+     * base is the base pointer register  */
+
+	ldc1		$f0, \offset + 0(\base)
+	ldc1		$f1, \offset + 8(\base)
+	ldc1		$f2, \offset + 16(\base)
+	ldc1		$f3, \offset + 24(\base)
+	ldc1		$f4, \offset + 32(\base)
+	ldc1		$f5, \offset + 40(\base)
+	ldc1		$f6, \offset + 48(\base)
+	ldc1		$f7, \offset + 56(\base)
+	ldc1		$f8, \offset + 64(\base)
+	ldc1		$f9, \offset + 72(\base)
+	ldc1		$f10, \offset + 80(\base)
+	ldc1		$f11, \offset + 88(\base)
+	ldc1		$f12, \offset + 96(\base)
+	ldc1		$f13, \offset + 104(\base)
+	ldc1		$f14, \offset + 112(\base)
+	ldc1		$f15, \offset + 120(\base)
+	ldc1		$f16, \offset + 128(\base)
+	ldc1		$f17, \offset + 136(\base)
+	ldc1		$f18, \offset + 144(\base)
+	ldc1		$f19, \offset + 152(\base)
+	ldc1		$f20, \offset + 160(\base)
+	ldc1		$f21, \offset + 168(\base)
+	ldc1		$f22, \offset + 176(\base)
+	ldc1		$f23, \offset + 184(\base)
+	ldc1		$f24, \offset + 192(\base)
+	ldc1		$f25, \offset + 200(\base)
+	ldc1		$f26, \offset + 208(\base)
+	ldc1		$f27, \offset + 216(\base)
+	ldc1		$f28, \offset + 224(\base)
+	ldc1		$f29, \offset + 232(\base)
+	ldc1		$f30, \offset + 240(\base)
+	ldc1		$f31, \offset + 248(\base)
+
+    .endm
+
+/******************************************************************/
+.macro	portSAVE_CONTEXT
+
+	/* Make room for the context. First save the current status so it can be
+	manipulated, and the cause and EPC registers so their original values are
+	captured. */
+	mfc0		k0, _CP0_CAUSE
+	addiu		sp, sp, -portCONTEXT_SIZE
+
+	#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+		/* Test if we are already using the system stack. Only tasks may use the
+		FPU so if we are already in a nested interrupt then the FPU context does
+		not require saving. */
+		la			k1, uxInterruptNesting
+		lw			k1, 0(k1)
+		bne			k1, zero, 2f
+		nop
+
+		/* Test if the current task needs the FPU context saving. */
+		la			k1, ulTaskHasFPUContext
+		lw			k1, 0(k1)
+		beq			k1, zero, 1f
+		nop
+
+		/* Adjust the stack to account for the additional FPU context.*/
+		addiu		sp, sp, -portFPU_CONTEXT_SIZE
+
+	1:
+		/* Save the ulTaskHasFPUContext flag. */
+		sw			k1, portTASK_HAS_FPU_STACK_LOCATION(sp)
+
+	2:
+	#endif
+
+	mfc0		k1, _CP0_STATUS
+
+	/* Also save s7, s6 and s5 so they can be used.  Any nesting interrupts
+	should maintain the values of these registers across the ISR. */
+	sw			s7, 48(sp)
+	sw			s6, 44(sp)
+	sw			s5, 40(sp)
+	sw			k1, portSTATUS_STACK_LOCATION(sp)
+
+	/* Prepare to enable interrupts above the current priority. */
+	srl			k0, k0, 0xa
+	ins 		k1, k0, 10, 7
+	srl			k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */
+	ins 		k1, k0, 18, 1
+	ins			k1, zero, 1, 4
+
+	/* s5 is used as the frame pointer. */
+	add			s5, zero, sp
+
+	/* Check the nesting count value. */
+	la			k0, uxInterruptNesting
+	lw			s6, (k0)
+
+	/* If the nesting count is 0 then swap to the the system stack, otherwise
+	the system stack is already being used. */
+	bne			s6, zero, 1f
+	nop
+
+	/* Swap to the system stack. */
+	la			sp, xISRStackTop
+	lw			sp, (sp)
+
+	/* Increment and save the nesting count. */
+1:	addiu		s6, s6, 1
+	sw			s6, 0(k0)
+
+	/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
+	mfc0 		s6, _CP0_EPC
+
+	/* Re-enable interrupts. */
+	mtc0		k1, _CP0_STATUS
+
+	/* Save the context into the space just created.  s6 is saved again
+	here as it now contains the EPC value.  No other s registers need be
+	saved. */
+	sw			ra, 120(s5)
+	sw			s8, 116(s5)
+	sw			t9, 112(s5)
+	sw			t8, 108(s5)
+	sw			t7, 104(s5)
+	sw			t6, 100(s5)
+	sw			t5, 96(s5)
+	sw			t4, 92(s5)
+	sw			t3, 88(s5)
+	sw			t2, 84(s5)
+	sw			t1, 80(s5)
+	sw			t0, 76(s5)
+	sw			a3, 72(s5)
+	sw			a2, 68(s5)
+	sw			a1, 64(s5)
+	sw			a0, 60(s5)
+	sw			v1, 56(s5)
+	sw			v0, 52(s5)
+	sw			s6, portEPC_STACK_LOCATION(s5)
+	sw			$1, 16(s5)
+
+	/* Save the AC0, AC1, AC2, AC3 registers from the DSP.  s6 is used as a
+	scratch register. */
+	mfhi		s6, $ac1
+	sw			s6, 128(s5)
+	mflo		s6, $ac1
+	sw			s6, 124(s5)
+
+	mfhi		s6, $ac2
+	sw			s6, 136(s5)
+	mflo		s6, $ac2
+	sw			s6, 132(s5)
+
+	mfhi		s6, $ac3
+	sw			s6, 144(s5)
+	mflo		s6, $ac3
+	sw			s6, 140(s5)
+
+	/* Save the DSP Control register */
+	rddsp		s6
+	sw			s6, 148(s5)
+
+	/* ac0 is done separately to match the MX port. */
+	mfhi		s6, $ac0
+	sw			s6, 12(s5)
+	mflo		s6, $ac0
+	sw			s6, 8(s5)
+
+	/* Save the FPU context if the nesting count was zero. */
+	#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+		la			s6, uxInterruptNesting
+		lw			s6, 0(s6)
+		addiu		s6, s6, -1
+		bne			s6, zero, 1f
+		nop
+
+		/* Test if the current task needs the FPU context saving. */
+		lw			s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
+		beq			s6, zero, 1f
+		nop
+
+		/* Save the FPU registers. */
+		portSAVE_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
+
+		/* Save the FPU status register */
+		cfc1		s6, $f31
+		sw			s6, (portCONTEXT_SIZE + portFPCSR_STACK_LOCATION)(s5)
+
+		1:
+	#endif
+
+	/* Update the task stack pointer value if nesting is zero. */
+	la			s6, uxInterruptNesting
+	lw			s6, (s6)
+	addiu		s6, s6, -1
+	bne			s6, zero, 1f
+	nop
+
+	/* Save the stack pointer. */
+	la			s6, uxSavedTaskStackPointer
+	sw			s5, (s6)
+1:
+	.endm
+
+/******************************************************************/
+.macro	portRESTORE_CONTEXT
+
+	/* Restore the stack pointer from the TCB.  This is only done if the
+	nesting count is 1. */
+	la			s6, uxInterruptNesting
+	lw			s6, (s6)
+	addiu		s6, s6, -1
+	bne			s6, zero, 1f
+	nop
+	la			s6, uxSavedTaskStackPointer
+	lw			s5, (s6)
+
+    #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+		/* Restore the FPU context if required. */
+		lw			s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
+		beq			s6, zero, 1f
+		nop
+
+		/* Restore the FPU registers. */
+		portLOAD_FPU_REGS   ( portCONTEXT_SIZE + 8 ), s5
+
+		/* Restore the FPU status register. */
+		lw			s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
+		ctc1		s6, $f31
+   	#endif
+
+1:
+
+	/* Restore the context. */
+	lw			s6, 128(s5)
+	mthi		s6, $ac1
+	lw			s6, 124(s5)
+	mtlo		s6, $ac1
+
+	lw			s6, 136(s5)
+	mthi		s6, $ac2
+	lw			s6, 132(s5)
+	mtlo		s6, $ac2
+
+	lw			s6, 144(s5)
+	mthi		s6, $ac3
+	lw			s6, 140(s5)
+	mtlo		s6, $ac3
+
+	/* Restore DSPControl. */
+	lw			s6, 148(s5)
+	wrdsp		s6
+
+	lw			s6, 8(s5)
+	mtlo		s6, $ac0
+	lw			s6, 12(s5)
+	mthi		s6, $ac0
+	lw			$1, 16(s5)
+
+	/* s6 is loaded as it was used as a scratch register and therefore saved
+	as part of the interrupt context. */
+	lw			s7, 48(s5)
+	lw			s6, 44(s5)
+	lw			v0, 52(s5)
+	lw			v1, 56(s5)
+	lw			a0, 60(s5)
+	lw			a1, 64(s5)
+	lw			a2, 68(s5)
+	lw			a3, 72(s5)
+	lw			t0, 76(s5)
+	lw			t1, 80(s5)
+	lw			t2, 84(s5)
+	lw			t3, 88(s5)
+	lw			t4, 92(s5)
+	lw			t5, 96(s5)
+	lw			t6, 100(s5)
+	lw			t7, 104(s5)
+	lw			t8, 108(s5)
+	lw			t9, 112(s5)
+	lw			s8, 116(s5)
+	lw			ra, 120(s5)
+
+	/* Protect access to the k registers, and others. */
+	di
+	ehb
+
+	/* Decrement the nesting count. */
+	la			k0, uxInterruptNesting
+	lw			k1, (k0)
+	addiu		k1, k1, -1
+	sw			k1, 0(k0)
+
+	#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+		/* If the nesting count is now zero then the FPU context may be restored. */
+		bne			k1, zero, 1f
+		nop
+
+		/* Restore the value of ulTaskHasFPUContext */
+		la			k0, ulTaskHasFPUContext
+		lw			k1, 0(s5)
+		sw			k1, 0(k0)
+
+		/* If the task does not have an FPU context then adjust the stack normally. */
+		beq			k1, zero, 1f
+		nop
+
+		/* Restore the STATUS and EPC registers */
+		lw			k0, portSTATUS_STACK_LOCATION(s5)
+		lw			k1, portEPC_STACK_LOCATION(s5)
+
+		/* Leave the stack in its original state.  First load sp from s5, then
+		restore s5 from the stack. */
+		add			sp, zero, s5
+		lw			s5, 40(sp)
+
+		/* Adjust the stack pointer to remove the FPU context */
+		addiu		sp, sp,	portFPU_CONTEXT_SIZE
+		beq			zero, zero, 2f
+		nop
+
+		1:  /* Restore the STATUS and EPC registers */
+		lw			k0, portSTATUS_STACK_LOCATION(s5)
+		lw			k1, portEPC_STACK_LOCATION(s5)
+
+		/* Leave the stack in its original state.  First load sp from s5, then
+		restore s5 from the stack. */
+		add			sp, zero, s5
+		lw			s5, 40(sp)
+
+		2:  /* Adjust the stack pointer */
+		addiu		sp, sp, portCONTEXT_SIZE
+
+	#else
+
+		/* Restore the frame when there is no hardware FP support. */
+		lw			k0, portSTATUS_STACK_LOCATION(s5)
+		lw			k1, portEPC_STACK_LOCATION(s5)
+
+		/* Leave the stack in its original state.  First load sp from s5, then
+		restore s5 from the stack. */
+		add			sp, zero, s5
+		lw			s5, 40(sp)
+
+		addiu		sp, sp,	portCONTEXT_SIZE
+
+	#endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+
+	mtc0		k0, _CP0_STATUS
+	mtc0 		k1, _CP0_EPC
+	ehb
+	eret
+	nop
+
+	.endm
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port.c
new file mode 100644
index 0000000..3225dde
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port.c
@@ -0,0 +1,372 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the PIC32MZ port.
+  *----------------------------------------------------------*/
+
+/* Microchip specific headers. */
+#include <xc.h>
+
+/* Standard headers. */
+#include <string.h>
+
+/* Scheduler include files. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#if !defined(__PIC32MZ__)
+    #error This port is designed to work with XC32 on PIC32MZ MCUs.  Please update your C compiler version or settings.
+#endif
+
+#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
+	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
+#endif
+
+/* Hardware specifics. */
+#define portTIMER_PRESCALE	8
+#define portPRESCALE_BITS	1
+
+/* Bits within various registers. */
+#define portIE_BIT					( 0x00000001 )
+#define portEXL_BIT					( 0x00000002 )
+#define portMX_BIT					( 0x01000000 ) /* Allow access to DSP instructions. */
+#define portCU1_BIT					( 0x20000000 ) /* enable CP1 for parts with hardware. */
+#define portFR_BIT					( 0x04000000 ) /* Enable 64 bit floating point registers. */
+
+/* Bits within the CAUSE register. */
+#define portCORE_SW_0				( 0x00000100 )
+#define portCORE_SW_1				( 0x00000200 )
+
+/* The EXL bit is set to ensure interrupts do not occur while the context of
+the first task is being restored. */
+#if ( __mips_hard_float == 1 )
+    #define portINITIAL_SR			( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT )
+#else
+    #define portINITIAL_SR			( portIE_BIT | portEXL_BIT | portMX_BIT )
+#endif
+
+/* The initial value to store into the FPU status and control register. This is
+ only used on parts that support a hardware FPU. */
+#define portINITIAL_FPSCR			(0x1000000) /* High perf on denormal ops */
+
+
+/*
+By default port.c generates its tick interrupt from TIMER1.  The user can
+override this behaviour by:
+	1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
+	   which is the function that configures the timer.  The function is defined
+	   as a weak symbol in this file so if the same function name is used in the
+	   application code then the version in the application code will be linked
+	   into the application in preference to the version defined in this file.
+	2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
+	   to generate the tick interrupt.  For example, when timer 1 is used then
+	   configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
+	   configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
+	3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
+	   timer used to generate the tick interrupt.  For example, when timer 1 is
+	   used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
+	   IFS0CLR = _IFS0_T1IF_MASK.
+*/
+#ifndef configTICK_INTERRUPT_VECTOR
+	#define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
+	#define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
+#else
+	#ifndef configCLEAR_TICK_TIMER_INTERRUPT
+		#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
+	#endif
+#endif
+
+/* Let the user override the pre-loading of the initial RA with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
+stack checking.  A problem in the ISR stack will trigger an assert, not call the
+stack overflow hook function (because the stack overflow hook is specific to a
+task stack, not the ISR stack). */
+#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
+
+	/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
+	the task stacks, and so will legitimately appear in many positions within
+	the ISR stack. */
+	#define portISR_STACK_FILL_BYTE	0xee
+
+	static const uint8_t ucExpectedStackBytes[] = {
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
+									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };	\
+
+	#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
+#else
+	/* Define the function away. */
+	#define portCHECK_ISR_STACK()
+#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Records the interrupt nesting depth.  This is initialised to one as it is
+decremented to 0 when the first task starts. */
+volatile UBaseType_t uxInterruptNesting = 0x01;
+
+/* Stores the task stack pointer when a switch is made to use the system stack. */
+UBaseType_t uxSavedTaskStackPointer = 0;
+
+/* The stack used by interrupt service routines that cause a context switch. */
+__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
+
+/* The top of stack value ensures there is enough space to store 6 registers on
+the callers stack, as some functions seem to want to do this.  8 byte alignment
+is required to allow double word floating point stack pushes generated by the
+compiler. */
+const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
+
+/* Saved as part of the task context. Set to pdFALSE if the task does not
+ require an FPU context. */
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+	uint32_t ulTaskHasFPUContext = 0;
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Ensure 8 byte alignment is maintained when leaving this function. */
+	pxTopOfStack--;
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0x12345678;	/* Word to which the stack pointer will be left pointing after context restore. */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) _CP0_GET_CAUSE();
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) pxCode; 		/* CP0_EPC */
+	pxTopOfStack--;
+
+	*pxTopOfStack = (StackType_t) 0x00000000;	/* DSPControl */
+	pxTopOfStack -= 7;  						/* Includes space for AC1 - AC3. */
+
+	*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS;	/* ra */
+	pxTopOfStack -= 15;
+
+	*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
+	pxTopOfStack -= 15;
+
+	*pxTopOfStack = (StackType_t) pdFALSE; /*by default disable FPU context save on parts with FPU */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxSavedTaskStackPointer == 0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup a timer for a regular tick.  This function uses peripheral timer 1.
+ * The function is declared weak so an application writer can use a different
+ * timer by redefining this implementation.  If a different timer is used then
+ * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to
+ * ensure the RTOS provided tick interrupt handler is installed on the correct
+ * vector number.  When Timer 1 is used the vector number is defined as
+ * _TIMER_1_VECTOR.
+ */
+__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
+{
+const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1UL;
+
+	T1CON = 0x0000;
+	T1CONbits.TCKPS = portPRESCALE_BITS;
+	PR1 = ulCompareMatch;
+	IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
+
+	/* Clear the interrupt as a starting condition. */
+	IFS0bits.T1IF = 0;
+
+	/* Enable the interrupt. */
+	IEC0bits.T1IE = 1;
+
+	/* Start the timer. */
+	T1CONbits.TON = 1;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler(void)
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxInterruptNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vPortStartFirstTask( void );
+extern void *pxCurrentTCB;
+
+	#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
+	{
+		/* Fill the ISR stack to make it easy to asses how much is being used. */
+		memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
+	}
+	#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
+
+	/* Clear the software interrupt flag. */
+	IFS0CLR = _IFS0_CS0IF_MASK;
+
+	/* Set software timer priority. */
+	IPC0CLR = _IPC0_CS0IP_MASK;
+	IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION );
+
+	/* Enable software interrupt. */
+	IEC0CLR = _IEC0_CS0IE_MASK;
+	IEC0SET = 1 << _IEC0_CS0IE_POSITION;
+
+	/* Setup the timer to generate the tick.  Interrupts will have been
+	disabled by the time we get here. */
+	vApplicationSetupTickTimerInterrupt();
+
+	/* Kick off the highest priority task that has been created so far.
+	Its stack location is loaded into uxSavedTaskStackPointer. */
+	uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
+	vPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS. */
+	prvTaskExitError();
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortIncrementTick( void )
+{
+UBaseType_t uxSavedStatus;
+
+	uxSavedStatus = uxPortSetInterruptMaskFromISR();
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Pend a context switch. */
+			_CP0_BIS_CAUSE( portCORE_SW_0 );
+		}
+	}
+	vPortClearInterruptMaskFromISR( uxSavedStatus );
+
+	/* Look for the ISR stack getting near or past its limit. */
+	portCHECK_ISR_STACK();
+
+	/* Clear timer interrupt. */
+	configCLEAR_TICK_TIMER_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxPortSetInterruptMaskFromISR( void )
+{
+UBaseType_t uxSavedStatusRegister;
+
+	__builtin_disable_interrupts();
+	uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
+	/* This clears the IPL bits, then sets them to
+	configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
+	from an interrupt that has a priority above
+	configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
+	can only result in the IPL being unchanged or raised, and therefore never
+	lowered. */
+	_CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
+
+	return uxSavedStatusRegister;
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
+{
+	_CP0_SET_STATUS( uxSavedStatusRegister );
+}
+/*-----------------------------------------------------------*/
+
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+
+	void vPortTaskUsesFPU(void)
+	{
+	extern void vPortInitialiseFPSCR( uint32_t uxFPSCRInit );
+
+		portENTER_CRITICAL();
+
+		/* Initialise the floating point status register. */
+		vPortInitialiseFPSCR(portINITIAL_FPSCR);
+
+		/* A task is registering the fact that it needs a FPU context. Set the
+		FPU flag (saved as part of the task context). */
+		ulTaskHasFPUContext = pdTRUE;
+
+		portEXIT_CRITICAL();
+	}
+
+#endif /* __mips_hard_float == 1 */
+
+/*-----------------------------------------------------------*/
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port_asm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port_asm.S
new file mode 100644
index 0000000..020b2c4
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port_asm.S
@@ -0,0 +1,768 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include <xc.h>
+#include <sys/asm.h>
+#include "FreeRTOSConfig.h"
+#include "ISR_Support.h"
+
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern vPortIncrementTick
+	.extern xISRStackTop
+	.extern ulTaskHasFPUContext
+
+	.global vPortStartFirstTask
+	.global vPortYieldISR
+	.global vPortTickInterruptHandler
+	.global vPortInitialiseFPSCR
+
+
+/******************************************************************/
+
+	.set  nomips16
+	.set  nomicromips
+	.set  noreorder
+	.set  noat
+
+	/***************************************************************
+	*  The following is needed to locate the
+	*  vPortTickInterruptHandler function into the correct vector
+	***************************************************************/
+	#ifdef configTICK_INTERRUPT_VECTOR
+		#if (configTICK_INTERRUPT_VECTOR == _CORE_TIMER_VECTOR)
+			.equ     __vector_dispatch_0, vPortTickInterruptHandler
+			.global  __vector_dispatch_0
+			.section .vector_0, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_1_VECTOR)
+			.equ     __vector_dispatch_4, vPortTickInterruptHandler
+			.global  __vector_dispatch_4
+			.section .vector_4, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_2_VECTOR)
+			.equ     __vector_dispatch_9, vPortTickInterruptHandler
+			.global  __vector_dispatch_9
+			.section .vector_9, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_3_VECTOR)
+			.equ     __vector_dispatch_14, vPortTickInterruptHandler
+			.global  __vector_dispatch_14
+			.section .vector_14, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_4_VECTOR)
+			.equ     __vector_dispatch_19, vPortTickInterruptHandler
+			.global  __vector_dispatch_19
+			.section .vector_19, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_5_VECTOR)
+			.equ     __vector_dispatch_24, vPortTickInterruptHandler
+			.global  __vector_dispatch_24
+			.section .vector_24, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_6_VECTOR)
+			.equ     __vector_dispatch_28, vPortTickInterruptHandler
+			.global  __vector_dispatch_28
+			.section .vector_28, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_7_VECTOR)
+			.equ     __vector_dispatch_32, vPortTickInterruptHandler
+			.global  __vector_dispatch_32
+			.section .vector_32, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_8_VECTOR)
+			.equ     __vector_dispatch_36, vPortTickInterruptHandler
+			.global  __vector_dispatch_36
+			.section .vector_36, code, keep
+		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_9_VECTOR)
+			.equ     __vector_dispatch_40, vPortTickInterruptHandler
+			.global  __vector_dispatch_40
+			.section .vector_40, code, keep
+		#endif
+	#else
+		.equ     __vector_dispatch_4, vPortTickInterruptHandler
+		.global  __vector_dispatch_4
+		.section .vector_4, code, keep
+	#endif
+
+	.ent		vPortTickInterruptHandler
+
+vPortTickInterruptHandler:
+
+	portSAVE_CONTEXT
+
+	jal 		vPortIncrementTick
+	nop
+
+	portRESTORE_CONTEXT
+
+	.end vPortTickInterruptHandler
+
+/******************************************************************/
+
+	.set		noreorder
+	.set 		noat
+	.section .text, code
+	.ent		vPortStartFirstTask
+
+vPortStartFirstTask:
+
+	/* Simply restore the context of the highest priority task that has been
+	created so far. */
+	portRESTORE_CONTEXT
+
+	.end vPortStartFirstTask
+
+
+
+/*******************************************************************/
+
+	.set  nomips16
+	.set  nomicromips
+	.set  noreorder
+	.set  noat
+	/***************************************************************
+	*  The following is needed to locate the vPortYieldISR function
+	*  into the correct vector
+	***************************************************************/
+	.equ     __vector_dispatch_1, vPortYieldISR
+	.global  __vector_dispatch_1
+	.section .vector_1, code
+
+	.ent  vPortYieldISR
+vPortYieldISR:
+
+	#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+		/* Code sequence for FPU support, the context save requires advance
+		knowledge of the stack frame size and if the current task actually uses the 
+		FPU. */
+
+		/* Make room for the context. First save the current status so it can be
+		manipulated, and the cause and EPC registers so their original values are
+		captured. */
+		la		k0, ulTaskHasFPUContext
+		lw		k0, 0(k0)
+		beq		k0, zero, 1f
+		addiu	sp, sp, -portCONTEXT_SIZE	/* always reserve space for the context. */
+		addiu	sp, sp, -portFPU_CONTEXT_SIZE	/* reserve additional space for the FPU context. */
+	1:
+		mfc0	k1, _CP0_STATUS
+
+		/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
+		maintain the values of these registers across the ISR. */
+		sw		s6, 44(sp)
+		sw		s5, 40(sp)
+		sw		k1, portSTATUS_STACK_LOCATION(sp)
+		sw		k0, portTASK_HAS_FPU_STACK_LOCATION(sp)
+
+		/* Prepare to re-enabled interrupts above the kernel priority. */
+		ins 	k1, zero, 10, 7         /* Clear IPL bits 0:6. */
+		ins 	k1, zero, 18, 1         /* Clear IPL bit 7.  It would be an error here if this bit were set anyway. */
+		ori		k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
+		ins		k1, zero, 1, 4          /* Clear EXL, ERL and UM. */
+
+		/* s5 is used as the frame pointer. */
+		add		s5, zero, sp
+
+		/* Swap to the system stack.  This is not conditional on the nesting
+		count as this interrupt is always the lowest priority and therefore
+		the nesting is always 0. */
+		la		sp, xISRStackTop
+		lw		sp, (sp)
+
+		/* Set the nesting count. */
+		la		k0, uxInterruptNesting
+		addiu	s6, zero, 1
+		sw		s6, 0(k0)
+
+		/* s6 holds the EPC value, this is saved with the rest of the context
+		after interrupts are enabled. */
+		mfc0 	s6, _CP0_EPC
+
+		/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+		mtc0	k1, _CP0_STATUS
+
+		/* Save the context into the space just created.  s6 is saved again
+		here as it now contains the EPC value. */
+		sw		ra, 120(s5)
+		sw		s8, 116(s5)
+		sw		t9, 112(s5)
+		sw		t8, 108(s5)
+		sw		t7, 104(s5)
+		sw		t6, 100(s5)
+		sw		t5, 96(s5)
+		sw		t4, 92(s5)
+		sw		t3, 88(s5)
+		sw		t2, 84(s5)
+		sw		t1, 80(s5)
+		sw		t0, 76(s5)
+		sw		a3, 72(s5)
+		sw		a2, 68(s5)
+		sw		a1, 64(s5)
+		sw		a0, 60(s5)
+		sw		v1, 56(s5)
+		sw		v0, 52(s5)
+		sw		s7, 48(s5)
+		sw		s6, portEPC_STACK_LOCATION(s5)
+		/* s5 and s6 has already been saved. */
+		sw		s4, 36(s5)
+		sw		s3, 32(s5)
+		sw		s2, 28(s5)
+		sw		s1, 24(s5)
+		sw		s0, 20(s5)
+		sw		$1, 16(s5)
+
+		/* s7 is used as a scratch register as this should always be saved across
+		nesting interrupts. */
+
+		/* Save the AC0, AC1, AC2 and AC3. */
+		mfhi	s7, $ac1
+		sw		s7, 128(s5)
+		mflo	s7, $ac1
+		sw		s7, 124(s5)
+
+		mfhi	s7, $ac2
+		sw		s7, 136(s5)
+		mflo	s7, $ac2
+		sw		s7, 132(s5)
+
+		mfhi	s7, $ac3
+		sw		s7, 144(s5)
+		mflo	s7, $ac3
+		sw		s7, 140(s5)
+
+		rddsp	s7
+		sw		s7, 148(s5)
+
+		mfhi	s7, $ac0
+		sw		s7, 12(s5)
+		mflo	s7, $ac0
+		sw		s7, 8(s5)
+
+		/* Test if FPU context save is required. */
+		lw		s7, portTASK_HAS_FPU_STACK_LOCATION(s5)
+		beq		s7, zero, 1f
+		nop
+
+		/* Save the FPU registers above the normal context. */
+		portSAVE_FPU_REGS   (portCONTEXT_SIZE + 8), s5
+
+		/* Save the FPU status register */
+		cfc1	s7, $f31
+		sw		s7, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
+
+	1:
+		/* Save the stack pointer to the task. */
+		la		s7, pxCurrentTCB
+		lw		s7, (s7)
+		sw		s5, (s7)
+
+		/* Set the interrupt mask to the max priority that can use the API.  The
+		yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
+		is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
+		raise the IPL value and never lower it. */
+		di
+		ehb
+		mfc0	s7, _CP0_STATUS
+		ins 	s7, zero, 10, 7
+		ins 	s7, zero, 18, 1
+		ori		s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
+
+		/* This mtc0 re-enables interrupts, but only above
+		configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+		mtc0	s6, _CP0_STATUS
+		ehb
+
+		/* Clear the software interrupt in the core. */
+		mfc0	s6, _CP0_CAUSE
+		ins		s6, zero, 8, 1
+		mtc0	s6, _CP0_CAUSE
+		ehb
+
+		/* Clear the interrupt in the interrupt controller. */
+		la		s6, IFS0CLR
+		addiu	s4, zero, 2
+		sw		s4, (s6)
+
+		jal		vTaskSwitchContext
+		nop
+
+		/* Clear the interrupt mask again.  The saved status value is still in s7. */
+		mtc0	s7, _CP0_STATUS
+		ehb
+
+		/* Restore the stack pointer from the TCB. */
+		la		s0, pxCurrentTCB
+		lw		s0, (s0)
+		lw		s5, (s0)
+
+		/* Test if the FPU context needs restoring. */
+		lw		s0, portTASK_HAS_FPU_STACK_LOCATION(s5)
+		beq		s0, zero, 1f
+		nop
+
+		/* Restore the FPU status register. */
+		lw		s0, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
+		ctc1	s0, $f31
+
+		/* Restore the FPU registers. */
+		portLOAD_FPU_REGS   ( portCONTEXT_SIZE + 8 ), s5
+
+	1:
+		/* Restore the rest of the context. */
+		lw		s0, 128(s5)
+		mthi	s0, $ac1
+		lw		s0, 124(s5)
+		mtlo		s0, $ac1
+
+		lw		s0, 136(s5)
+		mthi	s0, $ac2
+		lw		s0, 132(s5)
+		mtlo	s0, $ac2
+
+		lw		s0, 144(s5)
+		mthi	s0, $ac3
+		lw		s0, 140(s5)
+		mtlo	s0, $ac3
+
+		lw		s0, 148(s5)
+		wrdsp	s0
+
+		lw		s0, 8(s5)
+		mtlo	s0, $ac0
+		lw		s0, 12(s5)
+		mthi	s0, $ac0
+
+		lw		$1, 16(s5)
+		lw		s0, 20(s5)
+		lw		s1, 24(s5)
+		lw		s2, 28(s5)
+		lw		s3, 32(s5)
+		lw		s4, 36(s5)
+
+		/* s5 is loaded later. */
+		lw		s6, 44(s5)
+		lw		s7, 48(s5)
+		lw		v0, 52(s5)
+		lw		v1, 56(s5)
+		lw		a0, 60(s5)
+		lw		a1, 64(s5)
+		lw		a2, 68(s5)
+		lw		a3, 72(s5)
+		lw		t0, 76(s5)
+		lw		t1, 80(s5)
+		lw		t2, 84(s5)
+		lw		t3, 88(s5)
+		lw		t4, 92(s5)
+		lw		t5, 96(s5)
+		lw		t6, 100(s5)
+		lw		t7, 104(s5)
+		lw		t8, 108(s5)
+		lw		t9, 112(s5)
+		lw		s8, 116(s5)
+		lw		ra, 120(s5)
+
+		/* Protect access to the k registers, and others. */
+		di
+		ehb
+
+		/* Set nesting back to zero.  As the lowest priority interrupt this
+		interrupt cannot have nested. */
+		la		k0, uxInterruptNesting
+		sw		zero, 0(k0)
+
+		/* Switch back to use the real stack pointer. */
+		add		sp, zero, s5
+
+		/* Restore the real s5 value. */
+		lw		s5, 40(sp)
+
+		/* Pop the FPU context value from the stack */
+		lw		k0, portTASK_HAS_FPU_STACK_LOCATION(sp)
+		la		k1, ulTaskHasFPUContext
+		sw		k0, 0(k1)
+		beq		k0, zero, 1f
+		nop
+
+		/* task has FPU context so adjust the stack frame after popping the
+		status and epc values. */
+		lw		k1, portSTATUS_STACK_LOCATION(sp)
+		lw		k0, portEPC_STACK_LOCATION(sp)
+		addiu	sp, sp, portFPU_CONTEXT_SIZE
+		beq		zero, zero, 2f
+		nop
+
+	1:
+		/* Pop the status and epc values. */
+		lw		k1, portSTATUS_STACK_LOCATION(sp)
+		lw		k0, portEPC_STACK_LOCATION(sp)
+
+	2:
+		/* Remove stack frame. */
+		addiu	sp, sp, portCONTEXT_SIZE
+
+	#else
+		/* Code sequence for no FPU support, the context save requires advance
+		knowledge of the stack frame size when no FPU is being used */
+
+		/* Make room for the context. First save the current status so it can be
+		manipulated, and the cause and EPC registers so thier original values are
+		captured. */
+		addiu	sp, sp, -portCONTEXT_SIZE
+		mfc0	k1, _CP0_STATUS
+
+		/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
+		maintain the values of these registers across the ISR. */
+		sw		s6, 44(sp)
+		sw		s5, 40(sp)
+		sw		k1, portSTATUS_STACK_LOCATION(sp)
+
+		/* Prepare to re-enabled interrupts above the kernel priority. */
+		ins 	k1, zero, 10, 7         /* Clear IPL bits 0:6. */
+		ins 	k1, zero, 18, 1         /* Clear IPL bit 7.  It would be an error here if this bit were set anyway. */
+		ori		k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
+		ins		k1, zero, 1, 4          /* Clear EXL, ERL and UM. */
+
+		/* s5 is used as the frame pointer. */
+		add		s5, zero, sp
+
+		/* Swap to the system stack.  This is not conditional on the nesting
+		count as this interrupt is always the lowest priority and therefore
+		the nesting is always 0. */
+		la		sp, xISRStackTop
+		lw		sp, (sp)
+
+		/* Set the nesting count. */
+		la		k0, uxInterruptNesting
+		addiu	s6, zero, 1
+		sw		s6, 0(k0)
+
+		/* s6 holds the EPC value, this is saved with the rest of the context
+		after interrupts are enabled. */
+		mfc0 	s6, _CP0_EPC
+
+		/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+		mtc0	k1, _CP0_STATUS
+
+		/* Save the context into the space just created.  s6 is saved again
+		here as it now contains the EPC value. */
+		sw		ra, 120(s5)
+		sw		s8, 116(s5)
+		sw		t9, 112(s5)
+		sw		t8, 108(s5)
+		sw		t7, 104(s5)
+		sw		t6, 100(s5)
+		sw		t5, 96(s5)
+		sw		t4, 92(s5)
+		sw		t3, 88(s5)
+		sw		t2, 84(s5)
+		sw		t1, 80(s5)
+		sw		t0, 76(s5)
+		sw		a3, 72(s5)
+		sw		a2, 68(s5)
+		sw		a1, 64(s5)
+		sw		a0, 60(s5)
+		sw		v1, 56(s5)
+		sw		v0, 52(s5)
+		sw		s7, 48(s5)
+		sw		s6, portEPC_STACK_LOCATION(s5)
+		/* s5 and s6 has already been saved. */
+		sw		s4, 36(s5)
+		sw		s3, 32(s5)
+		sw		s2, 28(s5)
+		sw		s1, 24(s5)
+		sw		s0, 20(s5)
+		sw		$1, 16(s5)
+
+		/* s7 is used as a scratch register as this should always be saved across
+		nesting interrupts. */
+
+		/* Save the AC0, AC1, AC2 and AC3. */
+		mfhi	s7, $ac1
+		sw		s7, 128(s5)
+		mflo	s7, $ac1
+		sw		s7, 124(s5)
+
+		mfhi	s7, $ac2
+		sw		s7, 136(s5)
+		mflo	s7, $ac2
+		sw		s7, 132(s5)
+
+		mfhi	s7, $ac3
+		sw		s7, 144(s5)
+		mflo	s7, $ac3
+		sw		s7, 140(s5)
+
+		rddsp	s7
+		sw		s7, 148(s5)
+
+		mfhi	s7, $ac0
+		sw		s7, 12(s5)
+		mflo	s7, $ac0
+		sw		s7, 8(s5)
+
+		/* Save the stack pointer to the task. */
+		la		s7, pxCurrentTCB
+		lw		s7, (s7)
+		sw		s5, (s7)
+
+		/* Set the interrupt mask to the max priority that can use the API.  The
+		yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
+		is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
+		raise the IPL value and never lower it. */
+		di
+		ehb
+		mfc0	s7, _CP0_STATUS
+		ins 	s7, zero, 10, 7
+		ins 	s7, zero, 18, 1
+		ori		s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
+
+		/* This mtc0 re-enables interrupts, but only above
+		configMAX_SYSCALL_INTERRUPT_PRIORITY. */
+		mtc0	s6, _CP0_STATUS
+		ehb
+
+		/* Clear the software interrupt in the core. */
+		mfc0	s6, _CP0_CAUSE
+		ins		s6, zero, 8, 1
+		mtc0	s6, _CP0_CAUSE
+		ehb
+
+		/* Clear the interrupt in the interrupt controller. */
+		la		s6, IFS0CLR
+		addiu	s4, zero, 2
+		sw		s4, (s6)
+
+		jal		vTaskSwitchContext
+		nop
+
+		/* Clear the interrupt mask again.  The saved status value is still in s7. */
+		mtc0	s7, _CP0_STATUS
+		ehb
+
+		/* Restore the stack pointer from the TCB. */
+		la		s0, pxCurrentTCB
+		lw		s0, (s0)
+		lw		s5, (s0)
+
+		/* Restore the rest of the context. */
+		lw		s0, 128(s5)
+		mthi	s0, $ac1
+		lw		s0, 124(s5)
+		mtlo	s0, $ac1
+
+		lw		s0, 136(s5)
+		mthi	s0, $ac2
+		lw		s0, 132(s5)
+		mtlo	s0, $ac2
+
+		lw		s0, 144(s5)
+		mthi	s0, $ac3
+		lw		s0, 140(s5)
+		mtlo	s0, $ac3
+
+		lw		s0, 148(s5)
+		wrdsp	s0
+
+		lw		s0, 8(s5)
+		mtlo	s0, $ac0
+		lw		s0, 12(s5)
+		mthi	s0, $ac0
+
+		lw		$1, 16(s5)
+		lw		s0, 20(s5)
+		lw		s1, 24(s5)
+		lw		s2, 28(s5)
+		lw		s3, 32(s5)
+		lw		s4, 36(s5)
+
+		/* s5 is loaded later. */
+		lw		s6, 44(s5)
+		lw		s7, 48(s5)
+		lw		v0, 52(s5)
+		lw		v1, 56(s5)
+		lw		a0, 60(s5)
+		lw		a1, 64(s5)
+		lw		a2, 68(s5)
+		lw		a3, 72(s5)
+		lw		t0, 76(s5)
+		lw		t1, 80(s5)
+		lw		t2, 84(s5)
+		lw		t3, 88(s5)
+		lw		t4, 92(s5)
+		lw		t5, 96(s5)
+		lw		t6, 100(s5)
+		lw		t7, 104(s5)
+		lw		t8, 108(s5)
+		lw		t9, 112(s5)
+		lw		s8, 116(s5)
+		lw		ra, 120(s5)
+
+		/* Protect access to the k registers, and others. */
+		di
+		ehb
+
+		/* Set nesting back to zero.  As the lowest priority interrupt this
+		interrupt cannot have nested. */
+		la		k0, uxInterruptNesting
+		sw		zero, 0(k0)
+
+		/* Switch back to use the real stack pointer. */
+		add		sp, zero, s5
+
+		/* Restore the real s5 value. */
+		lw		s5, 40(sp)
+
+		/* Pop the status and epc values. */
+		lw		k1, portSTATUS_STACK_LOCATION(sp)
+		lw		k0, portEPC_STACK_LOCATION(sp)
+
+		/* Remove stack frame. */
+		addiu	sp, sp, portCONTEXT_SIZE
+
+	#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+
+	/* Restore the status and EPC registers and return */
+	mtc0	k1, _CP0_STATUS
+	mtc0 	k0, _CP0_EPC
+	ehb
+	eret
+	nop
+
+	.end	vPortYieldISR
+
+/******************************************************************/
+
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+
+	.macro portFPUSetAndInc reg, dest
+	mtc1	\reg, \dest
+	cvt.d.w	\dest, \dest
+	addiu	\reg, \reg, 1
+	.endm
+
+	.set	noreorder
+	.set 	noat
+	.section .text, code
+	.ent	vPortInitialiseFPSCR
+
+vPortInitialiseFPSCR:
+
+	/* Initialize the floating point status register in CP1. The initial
+	value is passed in a0. */
+	ctc1		a0, $f31
+
+	/* Clear the FPU registers */
+	addiu			a0, zero, 0x0000
+	portFPUSetAndInc	a0, $f0
+	portFPUSetAndInc	a0, $f1
+	portFPUSetAndInc	a0, $f2
+	portFPUSetAndInc	a0, $f3
+	portFPUSetAndInc	a0, $f4
+	portFPUSetAndInc	a0, $f5
+	portFPUSetAndInc	a0, $f6
+	portFPUSetAndInc	a0, $f7
+	portFPUSetAndInc	a0, $f8
+	portFPUSetAndInc	a0, $f9
+	portFPUSetAndInc	a0, $f10
+	portFPUSetAndInc	a0, $f11
+	portFPUSetAndInc	a0, $f12
+	portFPUSetAndInc	a0, $f13
+	portFPUSetAndInc	a0, $f14
+	portFPUSetAndInc	a0, $f15
+	portFPUSetAndInc	a0, $f16
+	portFPUSetAndInc	a0, $f17
+	portFPUSetAndInc	a0, $f18
+	portFPUSetAndInc	a0, $f19
+	portFPUSetAndInc	a0, $f20
+	portFPUSetAndInc	a0, $f21
+	portFPUSetAndInc	a0, $f22
+	portFPUSetAndInc	a0, $f23
+	portFPUSetAndInc	a0, $f24
+	portFPUSetAndInc	a0, $f25
+	portFPUSetAndInc	a0, $f26
+	portFPUSetAndInc	a0, $f27
+	portFPUSetAndInc	a0, $f28
+	portFPUSetAndInc	a0, $f29
+	portFPUSetAndInc	a0, $f30
+	portFPUSetAndInc	a0, $f31
+
+	jr		ra
+	nop
+
+	.end vPortInitialiseFPSCR
+
+#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+	
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+
+	/**********************************************************************/
+	/* Test read back								*/
+	/* a0 = address to store registers				*/
+
+	.set		noreorder
+	.set 		noat
+	.section	.text, code
+	.ent		vPortFPUReadback
+	.global		vPortFPUReadback
+
+vPortFPUReadback:
+	sdc1		$f0, 0(a0)
+	sdc1		$f1, 8(a0)
+	sdc1		$f2, 16(a0)
+	sdc1		$f3, 24(a0)
+	sdc1		$f4, 32(a0)
+	sdc1		$f5, 40(a0)
+	sdc1		$f6, 48(a0)
+	sdc1		$f7, 56(a0)
+	sdc1		$f8, 64(a0)
+	sdc1		$f9, 72(a0)
+	sdc1		$f10, 80(a0)
+	sdc1		$f11, 88(a0)
+	sdc1		$f12, 96(a0)
+	sdc1		$f13, 104(a0)
+	sdc1		$f14, 112(a0)
+	sdc1		$f15, 120(a0)
+	sdc1		$f16, 128(a0)
+	sdc1		$f17, 136(a0)
+	sdc1		$f18, 144(a0)
+	sdc1		$f19, 152(a0)
+	sdc1		$f20, 160(a0)
+	sdc1		$f21, 168(a0)
+	sdc1		$f22, 176(a0)
+	sdc1		$f23, 184(a0)
+	sdc1		$f24, 192(a0)
+	sdc1		$f25, 200(a0)
+	sdc1		$f26, 208(a0)
+	sdc1		$f27, 216(a0)
+	sdc1		$f28, 224(a0)
+	sdc1		$f29, 232(a0)
+	sdc1		$f30, 240(a0)
+	sdc1		$f31, 248(a0)
+
+	jr		ra
+	nop
+
+	.end vPortFPUReadback
+
+#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MZ/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MZ/portmacro.h
new file mode 100644
index 0000000..58c4236
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MPLAB/PIC32MZ/portmacro.h
@@ -0,0 +1,215 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* System include files */
+#include <xc.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			8
+#define portSTACK_GROWTH			-1
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portIPL_SHIFT				( 10UL )
+/* Don't straddle the CEE bit.  Interrupts calling FreeRTOS functions should
+never have higher IPL bits set anyway. */
+#define portALL_IPL_BITS			( 0x7FUL << portIPL_SHIFT )
+#define portSW0_BIT					( 0x01 << 8 )
+
+/* This clears the IPL bits, then sets them to
+configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
+configASSERT() is defined to ensure an assertion handler does not inadvertently
+attempt to lower the IPL when the call to assert was triggered because the IPL
+value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
+safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
+those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
+ensure API function and interrupt entry is as fast and as simple as possible. */
+#ifdef configASSERT
+	#define portDISABLE_INTERRUPTS()											\
+	{																			\
+	uint32_t ulStatus;															\
+																				\
+		/* Mask interrupts at and below the kernel interrupt priority. */		\
+		ulStatus = _CP0_GET_STATUS();											\
+																				\
+		/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */	\
+		if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
+		{																		\
+			ulStatus &= ~portALL_IPL_BITS;										\
+			_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+		}																		\
+	}
+#else /* configASSERT */
+	#define portDISABLE_INTERRUPTS()										\
+	{																		\
+	uint32_t ulStatus;														\
+																			\
+		/* Mask interrupts at and below the kernel interrupt priority. */	\
+		ulStatus = _CP0_GET_STATUS();										\
+		ulStatus &= ~portALL_IPL_BITS;										\
+		_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
+	}
+#endif /* configASSERT */
+
+#define portENABLE_INTERRUPTS()											\
+{																		\
+uint32_t ulStatus;														\
+																		\
+	/* Unmask all interrupts. */										\
+	ulStatus = _CP0_GET_STATUS();										\
+	ulStatus &= ~portALL_IPL_BITS;										\
+	_CP0_SET_STATUS( ulStatus );										\
+}
+
+
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portCRITICAL_NESTING_IN_TCB	1
+#define portENTER_CRITICAL()		vTaskEnterCritical()
+#define portEXIT_CRITICAL()			vTaskExitCritical()
+
+extern UBaseType_t uxPortSetInterruptMaskFromISR();
+extern void vPortClearInterruptMaskFromISR( UBaseType_t );
+#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
+
+#if ( __mips_hard_float == 0 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+    #error configUSE_TASK_FPU_SUPPORT can only be set to 1 when the part supports a hardware FPU module.
+#endif
+
+#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
+    void vPortTaskUsesFPU( void );
+	#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+#endif
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
+
+#endif /* taskRECORD_READY_PRIORITY */
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+#define portYIELD()								\
+{												\
+uint32_t ulCause;								\
+												\
+	/* Trigger software interrupt. */			\
+	ulCause = _CP0_GET_CAUSE();					\
+	ulCause |= portSW0_BIT;						\
+	_CP0_SET_CAUSE( ulCause );					\
+}
+
+extern volatile UBaseType_t uxInterruptNesting;
+#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
+
+#define portNOP()	__asm volatile ( "nop" )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#define portEND_SWITCHING_ISR( xSwitchRequired )	if( xSwitchRequired )	\
+													{						\
+														portYIELD();		\
+													}
+
+/* Required by the kernel aware debugger. */
+#ifdef __DEBUG
+	#define portREMOVE_STATIC_QUALIFIER
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MSVC-MingW/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MSVC-MingW/port.c
new file mode 100644
index 0000000..48f15e7
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MSVC-MingW/port.c
@@ -0,0 +1,699 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdio.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifdef __GNUC__
+	#include "mmsystem.h"
+#else
+	#pragma comment(lib, "winmm.lib")
+#endif
+
+#define portMAX_INTERRUPTS				( ( uint32_t ) sizeof( uint32_t ) * 8UL ) /* The number of bits in an uint32_t. */
+#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
+
+/* The priorities at which the various components of the simulation execute. */
+#define portDELETE_SELF_THREAD_PRIORITY			 THREAD_PRIORITY_TIME_CRITICAL /* Must be highest. */
+#define portSIMULATED_INTERRUPTS_THREAD_PRIORITY THREAD_PRIORITY_TIME_CRITICAL
+#define portSIMULATED_TIMER_THREAD_PRIORITY		 THREAD_PRIORITY_HIGHEST
+#define portTASK_THREAD_PRIORITY				 THREAD_PRIORITY_ABOVE_NORMAL
+
+/*
+ * Created as a high priority thread, this function uses a timer to simulate
+ * a tick interrupt being generated on an embedded target.  In this Windows
+ * environment the timer does not achieve anything approaching real time
+ * performance though.
+ */
+static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter );
+
+/*
+ * Process all the simulated interrupts - each represented by a bit in
+ * ulPendingInterrupts variable.
+ */
+static void prvProcessSimulatedInterrupts( void );
+
+/*
+ * Interrupt handlers used by the kernel itself.  These are executed from the
+ * simulated interrupt handler thread.
+ */
+static uint32_t prvProcessYieldInterrupt( void );
+static uint32_t prvProcessTickInterrupt( void );
+
+/*
+ * Exiting a critical section will cause the calling task to block on yield
+ * event to wait for an interrupt to process if an interrupt was pended while
+ * inside the critical section.  This variable protects against a recursive
+ * attempt to obtain pvInterruptEventMutex if a critical section is used inside
+ * an interrupt handler itself.
+ */
+volatile BaseType_t xInsideInterrupt = pdFALSE;
+
+/*
+ * Called when the process exits to let Windows know the high timer resolution
+ * is no longer required.
+ */
+static BOOL WINAPI prvEndProcess( DWORD dwCtrlType );
+
+/*-----------------------------------------------------------*/
+
+/* The WIN32 simulator runs each task in a thread.  The context switching is
+managed by the threads, so the task stack does not have to be managed directly,
+although the task stack is still used to hold an xThreadState structure this is
+the only thing it will ever hold.  The structure indirectly maps the task handle
+to a thread handle. */
+typedef struct
+{
+	/* Handle of the thread that executes the task. */
+	void *pvThread;
+
+	/* Event used to make sure the thread does not execute past a yield point
+	between the call to SuspendThread() to suspend the thread and the
+	asynchronous SuspendThread() operation actually being performed. */
+	void *pvYieldEvent;
+} ThreadState_t;
+
+/* Simulated interrupts waiting to be processed.  This is a bit mask where each
+bit represents one interrupt, so a maximum of 32 interrupts can be simulated. */
+static volatile uint32_t ulPendingInterrupts = 0UL;
+
+/* An event used to inform the simulated interrupt processing thread (a high
+priority thread that simulated interrupt processing) that an interrupt is
+pending. */
+static void *pvInterruptEvent = NULL;
+
+/* Mutex used to protect all the simulated interrupt variables that are accessed
+by multiple threads. */
+static void *pvInterruptEventMutex = NULL;
+
+/* The critical nesting count for the currently executing task.  This is
+initialised to a non-zero value so interrupts do not become enabled during
+the initialisation phase.  As each task has its own critical nesting value
+ulCriticalNesting will get set to zero when the first task runs.  This
+initialisation is probably not critical in this simulated environment as the
+simulated interrupt handlers do not get created until the FreeRTOS scheduler is
+started anyway. */
+static volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Handlers for all the simulated software interrupts.  The first two positions
+are used for the Yield and Tick interrupts so are handled slightly differently,
+all the other interrupts can be user defined. */
+static uint32_t (*ulIsrHandler[ portMAX_INTERRUPTS ])( void ) = { 0 };
+
+/* Pointer to the TCB of the currently executing task. */
+extern void * volatile pxCurrentTCB;
+
+/* Used to ensure nothing is processed during the startup sequence. */
+static BaseType_t xPortRunning = pdFALSE;
+
+/*-----------------------------------------------------------*/
+
+static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter )
+{
+TickType_t xMinimumWindowsBlockTime;
+TIMECAPS xTimeCaps;
+
+	/* Set the timer resolution to the maximum possible. */
+	if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR )
+	{
+		xMinimumWindowsBlockTime = ( TickType_t ) xTimeCaps.wPeriodMin;
+		timeBeginPeriod( xTimeCaps.wPeriodMin );
+
+		/* Register an exit handler so the timeBeginPeriod() function can be
+		matched with a timeEndPeriod() when the application exits. */
+		SetConsoleCtrlHandler( prvEndProcess, TRUE );
+	}
+	else
+	{
+		xMinimumWindowsBlockTime = ( TickType_t ) 20;
+	}
+
+	/* Just to prevent compiler warnings. */
+	( void ) lpParameter;
+
+	for( ;; )
+	{
+		/* Wait until the timer expires and we can access the simulated interrupt
+		variables.  *NOTE* this is not a 'real time' way of generating tick
+		events as the next wake time should be relative to the previous wake
+		time, not the time that Sleep() is called.  It is done this way to
+		prevent overruns in this very non real time simulated/emulated
+		environment. */
+		if( portTICK_PERIOD_MS < xMinimumWindowsBlockTime )
+		{
+			Sleep( xMinimumWindowsBlockTime );
+		}
+		else
+		{
+			Sleep( portTICK_PERIOD_MS );
+		}
+
+		configASSERT( xPortRunning );
+
+		/* Can't proceed if in a critical section as pvInterruptEventMutex won't
+		be available. */
+		WaitForSingleObject( pvInterruptEventMutex, INFINITE );
+
+		/* The timer has expired, generate the simulated tick event. */
+		ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK );
+
+		/* The interrupt is now pending - notify the simulated interrupt
+		handler thread.  Must be outside of a critical section to get here so
+		the handler thread can execute immediately pvInterruptEventMutex is
+		released. */
+		configASSERT( ulCriticalNesting == 0UL );
+		SetEvent( pvInterruptEvent );
+
+		/* Give back the mutex so the simulated interrupt handler unblocks
+		and can access the interrupt handler variables. */
+		ReleaseMutex( pvInterruptEventMutex );
+	}
+
+	#ifdef __GNUC__
+		/* Should never reach here - MingW complains if you leave this line out,
+		MSVC complains if you put it in. */
+		return 0;
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+static BOOL WINAPI prvEndProcess( DWORD dwCtrlType )
+{
+TIMECAPS xTimeCaps;
+
+	( void ) dwCtrlType;
+
+	if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR )
+	{
+		/* Match the call to timeBeginPeriod( xTimeCaps.wPeriodMin ) made when
+		the process started with a timeEndPeriod() as the process exits. */
+		timeEndPeriod( xTimeCaps.wPeriodMin );
+	}
+
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+ThreadState_t *pxThreadState = NULL;
+int8_t *pcTopOfStack = ( int8_t * ) pxTopOfStack;
+const SIZE_T xStackSize = 1024; /* Set the size to a small number which will get rounded up to the minimum possible. */
+
+	/* In this simulated case a stack is not initialised, but instead a thread
+	is created that will execute the task being created.  The thread handles
+	the context switching itself.  The ThreadState_t object is placed onto
+	the stack that was created for the task - so the stack buffer is still
+	used, just not in the conventional way.  It will not be used for anything
+	other than holding this structure. */
+	pxThreadState = ( ThreadState_t * ) ( pcTopOfStack - sizeof( ThreadState_t ) );
+
+	/* Create the event used to prevent the thread from executing past its yield
+	point if the SuspendThread() call that suspends the thread does not take
+	effect immediately (it is an asynchronous call). */
+	pxThreadState->pvYieldEvent = CreateEvent(  NULL,  /* Default security attributes. */
+												FALSE, /* Auto reset. */
+												FALSE, /* Start not signalled. */
+												NULL );/* No name. */
+
+	/* Create the thread itself. */
+	pxThreadState->pvThread = CreateThread( NULL, xStackSize, ( LPTHREAD_START_ROUTINE ) pxCode, pvParameters, CREATE_SUSPENDED | STACK_SIZE_PARAM_IS_A_RESERVATION, NULL );
+	configASSERT( pxThreadState->pvThread ); /* See comment where TerminateThread() is called. */
+	SetThreadAffinityMask( pxThreadState->pvThread, 0x01 );
+	SetThreadPriorityBoost( pxThreadState->pvThread, TRUE );
+	SetThreadPriority( pxThreadState->pvThread, portTASK_THREAD_PRIORITY );
+
+	return ( StackType_t * ) pxThreadState;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+void *pvHandle = NULL;
+int32_t lSuccess;
+ThreadState_t *pxThreadState = NULL;
+SYSTEM_INFO xSystemInfo;
+
+	/* This port runs windows threads with extremely high priority.  All the
+	threads execute on the same core - to prevent locking up the host only start
+	if the host has multiple cores. */
+	GetSystemInfo( &xSystemInfo );
+	if( xSystemInfo.dwNumberOfProcessors <= 1 )
+	{
+		printf( "This version of the FreeRTOS Windows port can only be used on multi-core hosts.\r\n" );
+		lSuccess = pdFAIL;
+	}
+	else
+	{
+		lSuccess = pdPASS;
+
+		/* The highest priority class is used to [try to] prevent other Windows
+		activity interfering with FreeRTOS timing too much. */
+		if( SetPriorityClass( GetCurrentProcess(), REALTIME_PRIORITY_CLASS ) == 0 )
+		{
+			printf( "SetPriorityClass() failed\r\n" );
+		}
+
+		/* Install the interrupt handlers used by the scheduler itself. */
+		vPortSetInterruptHandler( portINTERRUPT_YIELD, prvProcessYieldInterrupt );
+		vPortSetInterruptHandler( portINTERRUPT_TICK, prvProcessTickInterrupt );
+
+		/* Create the events and mutexes that are used to synchronise all the
+		threads. */
+		pvInterruptEventMutex = CreateMutex( NULL, FALSE, NULL );
+		pvInterruptEvent = CreateEvent( NULL, FALSE, FALSE, NULL );
+
+		if( ( pvInterruptEventMutex == NULL ) || ( pvInterruptEvent == NULL ) )
+		{
+			lSuccess = pdFAIL;
+		}
+
+		/* Set the priority of this thread such that it is above the priority of
+		the threads that run tasks.  This higher priority is required to ensure
+		simulated interrupts take priority over tasks. */
+		pvHandle = GetCurrentThread();
+		if( pvHandle == NULL )
+		{
+			lSuccess = pdFAIL;
+		}
+	}
+
+	if( lSuccess == pdPASS )
+	{
+		if( SetThreadPriority( pvHandle, portSIMULATED_INTERRUPTS_THREAD_PRIORITY ) == 0 )
+		{
+			lSuccess = pdFAIL;
+		}
+		SetThreadPriorityBoost( pvHandle, TRUE );
+		SetThreadAffinityMask( pvHandle, 0x01 );
+	}
+
+	if( lSuccess == pdPASS )
+	{
+		/* Start the thread that simulates the timer peripheral to generate
+		tick interrupts.  The priority is set below that of the simulated
+		interrupt handler so the interrupt event mutex is used for the
+		handshake / overrun protection. */
+		pvHandle = CreateThread( NULL, 0, prvSimulatedPeripheralTimer, NULL, CREATE_SUSPENDED, NULL );
+		if( pvHandle != NULL )
+		{
+			SetThreadPriority( pvHandle, portSIMULATED_TIMER_THREAD_PRIORITY );
+			SetThreadPriorityBoost( pvHandle, TRUE );
+			SetThreadAffinityMask( pvHandle, 0x01 );
+			ResumeThread( pvHandle );
+		}
+
+		/* Start the highest priority task by obtaining its associated thread
+		state structure, in which is stored the thread handle. */
+		pxThreadState = ( ThreadState_t * ) *( ( size_t * ) pxCurrentTCB );
+		ulCriticalNesting = portNO_CRITICAL_NESTING;
+
+		/* Start the first task. */
+		ResumeThread( pxThreadState->pvThread );
+
+		/* Handle all simulated interrupts - including yield requests and
+		simulated ticks. */
+		prvProcessSimulatedInterrupts();
+	}
+
+	/* Would not expect to return from prvProcessSimulatedInterrupts(), so should
+	not get here. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+static uint32_t prvProcessYieldInterrupt( void )
+{
+	/* Always return true as this is a yield. */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+static uint32_t prvProcessTickInterrupt( void )
+{
+uint32_t ulSwitchRequired;
+
+	/* Process the tick itself. */
+	configASSERT( xPortRunning );
+	ulSwitchRequired = ( uint32_t ) xTaskIncrementTick();
+
+	return ulSwitchRequired;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessSimulatedInterrupts( void )
+{
+uint32_t ulSwitchRequired, i;
+ThreadState_t *pxThreadState;
+void *pvObjectList[ 2 ];
+CONTEXT xContext;
+
+	/* Going to block on the mutex that ensured exclusive access to the simulated
+	interrupt objects, and the event that signals that a simulated interrupt
+	should be processed. */
+	pvObjectList[ 0 ] = pvInterruptEventMutex;
+	pvObjectList[ 1 ] = pvInterruptEvent;
+
+	/* Create a pending tick to ensure the first task is started as soon as
+	this thread pends. */
+	ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK );
+	SetEvent( pvInterruptEvent );
+
+	xPortRunning = pdTRUE;
+
+	for(;;)
+	{
+		xInsideInterrupt = pdFALSE;
+		WaitForMultipleObjects( sizeof( pvObjectList ) / sizeof( void * ), pvObjectList, TRUE, INFINITE );
+
+		/* Cannot be in a critical section to get here.  Tasks that exit a
+		critical section will block on a yield mutex to wait for an interrupt to
+		process if an interrupt was set pending while the task was inside the
+		critical section.  xInsideInterrupt prevents interrupts that contain
+		critical sections from doing the same. */
+		xInsideInterrupt = pdTRUE;
+
+		/* Used to indicate whether the simulated interrupt processing has
+		necessitated a context switch to another task/thread. */
+		ulSwitchRequired = pdFALSE;
+
+		/* For each interrupt we are interested in processing, each of which is
+		represented by a bit in the 32bit ulPendingInterrupts variable. */
+		for( i = 0; i < portMAX_INTERRUPTS; i++ )
+		{
+			/* Is the simulated interrupt pending? */
+			if( ( ulPendingInterrupts & ( 1UL << i ) ) != 0 )
+			{
+				/* Is a handler installed? */
+				if( ulIsrHandler[ i ] != NULL )
+				{
+					/* Run the actual handler.  Handlers return pdTRUE if they
+					necessitate a context switch. */
+					if( ulIsrHandler[ i ]() != pdFALSE )
+					{
+						/* A bit mask is used purely to help debugging. */
+						ulSwitchRequired |= ( 1 << i );
+					}
+				}
+
+				/* Clear the interrupt pending bit. */
+				ulPendingInterrupts &= ~( 1UL << i );
+			}
+		}
+
+		if( ulSwitchRequired != pdFALSE )
+		{
+			void *pvOldCurrentTCB;
+
+			pvOldCurrentTCB = pxCurrentTCB;
+
+			/* Select the next task to run. */
+			vTaskSwitchContext();
+
+			/* If the task selected to enter the running state is not the task
+			that is already in the running state. */
+			if( pvOldCurrentTCB != pxCurrentTCB )
+			{
+				/* Suspend the old thread.  In the cases where the (simulated)
+				interrupt is asynchronous (tick event swapping a task out rather
+				than a task blocking or yielding) it doesn't matter if the
+				'suspend' operation doesn't take effect immediately - if it
+				doesn't it would just be like the interrupt occurring slightly
+				later.  In cases where the yield was caused by a task blocking
+				or yielding then the task will block on a yield event after the
+				yield operation in case the 'suspend' operation doesn't take
+				effect immediately.  */
+				pxThreadState = ( ThreadState_t *) *( ( size_t * ) pvOldCurrentTCB );
+				SuspendThread( pxThreadState->pvThread );
+
+				/* Ensure the thread is actually suspended by performing a
+				synchronous operation that can only complete when the thread is
+				actually suspended.  The below code asks for dummy register
+				data.  Experimentation shows that these two lines don't appear
+				to do anything now, but according to
+				https://devblogs.microsoft.com/oldnewthing/20150205-00/?p=44743
+				they do - so as they do not harm (slight run-time hit). */
+				xContext.ContextFlags = CONTEXT_INTEGER;
+				( void ) GetThreadContext( pxThreadState->pvThread, &xContext );
+
+				/* Obtain the state of the task now selected to enter the
+				Running state. */
+				pxThreadState = ( ThreadState_t * ) ( *( size_t *) pxCurrentTCB );
+
+				/* pxThreadState->pvThread can be NULL if the task deleted
+				itself - but a deleted task should never be resumed here. */
+				configASSERT( pxThreadState->pvThread != NULL );
+				ResumeThread( pxThreadState->pvThread );
+			}
+		}
+
+		/* If the thread that is about to be resumed stopped running
+		because it yielded then it will wait on an event when it resumed
+		(to ensure it does not continue running after the call to
+		SuspendThread() above as SuspendThread() is asynchronous).
+		Signal the event to ensure the thread can proceed now it is
+		valid for it to do so.  Signaling the event is benign in the case that
+		the task was switched out asynchronously by an interrupt as the event
+		is reset before the task blocks on it. */
+		pxThreadState = ( ThreadState_t * ) ( *( size_t *) pxCurrentTCB );
+		SetEvent( pxThreadState->pvYieldEvent );
+		ReleaseMutex( pvInterruptEventMutex );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortDeleteThread( void *pvTaskToDelete )
+{
+ThreadState_t *pxThreadState;
+uint32_t ulErrorCode;
+
+	/* Remove compiler warnings if configASSERT() is not defined. */
+	( void ) ulErrorCode;
+
+	/* Find the handle of the thread being deleted. */
+	pxThreadState = ( ThreadState_t * ) ( *( size_t *) pvTaskToDelete );
+
+	/* Check that the thread is still valid, it might have been closed by
+	vPortCloseRunningThread() - which will be the case if the task associated
+	with the thread originally deleted itself rather than being deleted by a
+	different task. */
+	if( pxThreadState->pvThread != NULL )
+	{
+		WaitForSingleObject( pvInterruptEventMutex, INFINITE );
+
+		/* !!! This is not a nice way to terminate a thread, and will eventually
+		result in resources being depleted if tasks frequently delete other
+		tasks (rather than deleting themselves) as the task stacks will not be
+		freed. */
+		ulErrorCode = TerminateThread( pxThreadState->pvThread, 0 );
+		configASSERT( ulErrorCode );
+
+		ulErrorCode = CloseHandle( pxThreadState->pvThread );
+		configASSERT( ulErrorCode );
+
+		ReleaseMutex( pvInterruptEventMutex );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortCloseRunningThread( void *pvTaskToDelete, volatile BaseType_t *pxPendYield )
+{
+ThreadState_t *pxThreadState;
+void *pvThread;
+uint32_t ulErrorCode;
+
+	/* Remove compiler warnings if configASSERT() is not defined. */
+	( void ) ulErrorCode;
+
+	/* Find the handle of the thread being deleted. */
+	pxThreadState = ( ThreadState_t * ) ( *( size_t *) pvTaskToDelete );
+	pvThread = pxThreadState->pvThread;
+
+	/* Raise the Windows priority of the thread to ensure the FreeRTOS scheduler
+	does not run and swap it out before it is closed.  If that were to happen
+	the thread would never run again and effectively be a thread handle and
+	memory leak. */
+	SetThreadPriority( pvThread, portDELETE_SELF_THREAD_PRIORITY );
+
+	/* This function will not return, therefore a yield is set as pending to
+	ensure a context switch occurs away from this thread on the next tick. */
+	*pxPendYield = pdTRUE;
+
+	/* Mark the thread associated with this task as invalid so
+	vPortDeleteThread() does not try to terminate it. */
+	pxThreadState->pvThread = NULL;
+
+	/* Close the thread. */
+	ulErrorCode = CloseHandle( pvThread );
+	configASSERT( ulErrorCode );
+
+	/* This is called from a critical section, which must be exited before the
+	thread stops. */
+	taskEXIT_CRITICAL();
+	CloseHandle( pxThreadState->pvYieldEvent );
+	ExitThread( 0 );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	exit( 0 );
+}
+/*-----------------------------------------------------------*/
+
+void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber )
+{
+ThreadState_t *pxThreadState = ( ThreadState_t *) *( ( size_t * ) pxCurrentTCB );
+
+	configASSERT( xPortRunning );
+
+	if( ( ulInterruptNumber < portMAX_INTERRUPTS ) && ( pvInterruptEventMutex != NULL ) )
+	{
+		WaitForSingleObject( pvInterruptEventMutex, INFINITE );
+		ulPendingInterrupts |= ( 1 << ulInterruptNumber );
+
+		/* The simulated interrupt is now held pending, but don't actually
+		process it yet if this call is within a critical section.  It is
+		possible for this to be in a critical section as calls to wait for
+		mutexes are accumulative.  If in a critical section then the event
+		will get set when the critical section nesting count is wound back
+		down to zero. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			SetEvent( pvInterruptEvent );
+
+			/* Going to wait for an event - make sure the event is not already
+			signaled. */
+			ResetEvent( pxThreadState->pvYieldEvent );
+		}
+
+		ReleaseMutex( pvInterruptEventMutex );
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* An interrupt was pended so ensure to block to allow it to
+			execute.  In most cases the (simulated) interrupt will have
+			executed before the next line is reached - so this is just to make
+			sure. */
+			WaitForSingleObject( pxThreadState->pvYieldEvent, INFINITE );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortSetInterruptHandler( uint32_t ulInterruptNumber, uint32_t (*pvHandler)( void ) )
+{
+	if( ulInterruptNumber < portMAX_INTERRUPTS )
+	{
+		if( pvInterruptEventMutex != NULL )
+		{
+			WaitForSingleObject( pvInterruptEventMutex, INFINITE );
+			ulIsrHandler[ ulInterruptNumber ] = pvHandler;
+			ReleaseMutex( pvInterruptEventMutex );
+		}
+		else
+		{
+			ulIsrHandler[ ulInterruptNumber ] = pvHandler;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	if( xPortRunning == pdTRUE )
+	{
+		/* The interrupt event mutex is held for the entire critical section,
+		effectively disabling (simulated) interrupts. */
+		WaitForSingleObject( pvInterruptEventMutex, INFINITE );
+	}
+
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+int32_t lMutexNeedsReleasing;
+
+	/* The interrupt event mutex should already be held by this thread as it was
+	obtained on entry to the critical section. */
+	lMutexNeedsReleasing = pdTRUE;
+
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		ulCriticalNesting--;
+
+		/* Don't need to wait for any pending interrupts to execute if the
+		critical section was exited from inside an interrupt. */
+		if( ( ulCriticalNesting == portNO_CRITICAL_NESTING ) && ( xInsideInterrupt == pdFALSE ) )
+		{
+			/* Were any interrupts set to pending while interrupts were
+			(simulated) disabled? */
+			if( ulPendingInterrupts != 0UL )
+			{
+				ThreadState_t *pxThreadState = ( ThreadState_t *) *( ( size_t * ) pxCurrentTCB );
+
+				configASSERT( xPortRunning );
+
+				/* The interrupt won't actually executed until
+				pvInterruptEventMutex is released as it waits on both
+				pvInterruptEventMutex and pvInterruptEvent.
+				pvInterruptEvent is only set when the simulated
+				interrupt is pended if the interrupt is pended
+				from outside a critical section - hence it is set
+				here. */
+				SetEvent( pvInterruptEvent );
+				/* The calling task is going to wait for an event to ensure the
+				interrupt that is pending executes immediately after the
+				critical section is exited - so make sure the event is not
+				already signaled. */
+				ResetEvent( pxThreadState->pvYieldEvent );
+
+				/* Mutex will be released now so the (simulated) interrupt can
+				execute, so does not require releasing on function exit. */
+				lMutexNeedsReleasing = pdFALSE;
+				ReleaseMutex( pvInterruptEventMutex );
+				WaitForSingleObject( pxThreadState->pvYieldEvent, INFINITE );
+			}
+		}
+	}
+
+	if( pvInterruptEventMutex != NULL )
+	{
+		if( lMutexNeedsReleasing == pdTRUE )
+		{
+			configASSERT( xPortRunning );
+			ReleaseMutex( pvInterruptEventMutex );
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MSVC-MingW/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MSVC-MingW/portmacro.h
new file mode 100644
index 0000000..55ece9f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MSVC-MingW/portmacro.h
@@ -0,0 +1,162 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include <windows.h>
+#include <winbase.h>
+
+/******************************************************************************
+	Defines
+******************************************************************************/
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	size_t
+#define portBASE_TYPE	long
+#define portPOINTER_SIZE_TYPE size_t
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+    typedef uint32_t TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32/64-bit tick type on a 32/64-bit architecture, so reads of the tick
+	count do not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portINLINE __inline
+
+#if defined( __x86_64__) || defined( _M_X64 )
+	#define portBYTE_ALIGNMENT		8
+#else
+	#define portBYTE_ALIGNMENT		4
+#endif
+
+#define portYIELD()					vPortGenerateSimulatedInterrupt( portINTERRUPT_YIELD )
+
+
+extern volatile BaseType_t xInsideInterrupt;
+#define portSOFTWARE_BARRIER() while( xInsideInterrupt != pdFALSE )
+
+
+/* Simulated interrupts return pdFALSE if no context switch should be performed,
+or a non-zero number if a context switch should be performed. */
+#define portYIELD_FROM_ISR( x ) ( void ) x
+#define portEND_SWITCHING_ISR( x ) portYIELD_FROM_ISR( ( x ) )
+
+void vPortCloseRunningThread( void *pvTaskToDelete, volatile BaseType_t *pxPendYield );
+void vPortDeleteThread( void *pvThreadToDelete );
+#define portCLEAN_UP_TCB( pxTCB )	vPortDeleteThread( pxTCB )
+#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortCloseRunningThread( ( pvTaskToDelete ), ( pxPendYield ) )
+#define portDISABLE_INTERRUPTS() vPortEnterCritical()
+#define portENABLE_INTERRUPTS() vPortExitCritical()
+
+/* Critical section handling. */
+void vPortEnterCritical( void );
+void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical()
+#define portEXIT_CRITICAL()			vPortExitCritical()
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+
+	/*-----------------------------------------------------------*/
+
+	#ifdef __GNUC__
+		#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )	\
+			__asm volatile(	"bsr %1, %0\n\t" 									\
+							:"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" )
+	#else
+		/* BitScanReverse returns the bit position of the most significant '1'
+		in the word. */
+		#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) _BitScanReverse( ( DWORD * ) &( uxTopPriority ), ( uxReadyPriorities ) )
+	#endif /* __GNUC__ */
+
+#endif /* taskRECORD_READY_PRIORITY */
+
+#ifndef __GNUC__
+	__pragma( warning( disable:4211 ) ) /* Nonstandard extension used, as extern is only nonstandard to MSVC. */
+#endif
+
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
+
+#define portINTERRUPT_YIELD				( 0UL )
+#define portINTERRUPT_TICK				( 1UL )
+
+/*
+ * Raise a simulated interrupt represented by the bit mask in ulInterruptMask.
+ * Each bit can be used to represent an individual interrupt - with the first
+ * two bits being used for the Yield and Tick interrupts respectively.
+*/
+void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber );
+
+/*
+ * Install an interrupt handler to be called by the simulated interrupt handler
+ * thread.  The interrupt number must be above any used by the kernel itself
+ * (at the time of writing the kernel was using interrupt numbers 0, 1, and 2
+ * as defined above).  The number must also be lower than 32.
+ *
+ * Interrupt handler functions must return a non-zero value if executing the
+ * handler resulted in a task switch being required.
+ */
+void vPortSetInterruptHandler( uint32_t ulInterruptNumber, uint32_t (*pvHandler)( void ) );
+
+#endif
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/ReadMe.url b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/ReadMe.url
new file mode 100644
index 0000000..4d2d044
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/ReadMe.url
@@ -0,0 +1,5 @@
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,2
+[InternetShortcut]
+URL=https://www.FreeRTOS.org/a00111.html
+IDList=
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/heap_1.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/heap_1.c
new file mode 100644
index 0000000..a1e96bd
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/heap_1.c
@@ -0,0 +1,151 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+/*
+ * The simplest possible implementation of pvPortMalloc().  Note that this
+ * implementation does NOT allow allocated memory to be freed again.
+ *
+ * See heap_2.c, heap_3.c and heap_4.c for alternative implementations, and the
+ * memory management pages of https://www.FreeRTOS.org for more information.
+ */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+    #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* A few bytes might be lost to byte aligning the heap start address. */
+#define configADJUSTED_HEAP_SIZE    ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
+
+/* Allocate the memory for the heap. */
+#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
+
+/* The application writer has already defined the array used for the RTOS
+* heap - probably so it can be placed in a special segment or address. */
+    extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+    static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/* Index into the ucHeap array. */
+static size_t xNextFreeByte = ( size_t ) 0;
+
+/*-----------------------------------------------------------*/
+
+void * pvPortMalloc( size_t xWantedSize )
+{
+    void * pvReturn = NULL;
+    static uint8_t * pucAlignedHeap = NULL;
+
+    /* Ensure that blocks are always aligned. */
+    #if ( portBYTE_ALIGNMENT != 1 )
+        {
+            if( xWantedSize & portBYTE_ALIGNMENT_MASK )
+            {
+                /* Byte alignment required. Check for overflow. */
+                if ( (xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) )) > xWantedSize )
+                {
+                    xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+                } 
+                else 
+                {
+                    xWantedSize = 0;
+                }
+            }
+        }
+    #endif
+
+    vTaskSuspendAll();
+    {
+        if( pucAlignedHeap == NULL )
+        {
+            /* Ensure the heap starts on a correctly aligned boundary. */
+            pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) & ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+        }
+
+        /* Check there is enough room left for the allocation and. */
+        if( ( xWantedSize > 0 ) && /* valid size */
+            ( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) &&
+            ( ( xNextFreeByte + xWantedSize ) > xNextFreeByte ) ) /* Check for overflow. */
+        {
+            /* Return the next free byte then increment the index past this
+             * block. */
+            pvReturn = pucAlignedHeap + xNextFreeByte;
+            xNextFreeByte += xWantedSize;
+        }
+
+        traceMALLOC( pvReturn, xWantedSize );
+    }
+    ( void ) xTaskResumeAll();
+
+    #if ( configUSE_MALLOC_FAILED_HOOK == 1 )
+        {
+            if( pvReturn == NULL )
+            {
+                extern void vApplicationMallocFailedHook( void );
+                vApplicationMallocFailedHook();
+            }
+        }
+    #endif
+
+    return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void * pv )
+{
+    /* Memory cannot be freed using this scheme.  See heap_2.c, heap_3.c and
+     * heap_4.c for alternative implementations, and the memory management pages of
+     * https://www.FreeRTOS.org for more information. */
+    ( void ) pv;
+
+    /* Force an assert as it is invalid to call this function. */
+    configASSERT( pv == NULL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+    /* Only required when static memory is not cleared. */
+    xNextFreeByte = ( size_t ) 0;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+    return( configADJUSTED_HEAP_SIZE - xNextFreeByte );
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/heap_2.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/heap_2.c
new file mode 100644
index 0000000..42fdaa9
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/heap_2.c
@@ -0,0 +1,284 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that permits
+ * allocated blocks to be freed, but does not combine adjacent free blocks
+ * into a single larger block (and so will fragment memory).  See heap_4.c for
+ * an equivalent that does combine adjacent blocks into single larger blocks.
+ *
+ * See heap_1.c, heap_3.c and heap_4.c for alternative implementations, and the
+ * memory management pages of https://www.FreeRTOS.org for more information.
+ */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+    #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* A few bytes might be lost to byte aligning the heap start address. */
+#define configADJUSTED_HEAP_SIZE    ( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
+
+/*
+ * Initialises the heap structures before their first use.
+ */
+static void prvHeapInit( void );
+
+/* Allocate the memory for the heap. */
+#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
+
+/* The application writer has already defined the array used for the RTOS
+* heap - probably so it can be placed in a special segment or address. */
+    extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+    static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+
+/* Define the linked list structure.  This is used to link free blocks in order
+ * of their size. */
+typedef struct A_BLOCK_LINK
+{
+    struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */
+    size_t xBlockSize;                     /*<< The size of the free block. */
+} BlockLink_t;
+
+
+static const uint16_t heapSTRUCT_SIZE = ( ( sizeof( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );
+#define heapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, xEnd;
+
+/* Keeps track of the number of free bytes remaining, but says nothing about
+ * fragmentation. */
+static size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;
+
+/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */
+
+/*
+ * Insert a block into the list of free blocks - which is ordered by size of
+ * the block.  Small blocks at the start of the list and large blocks at the end
+ * of the list.
+ */
+#define prvInsertBlockIntoFreeList( pxBlockToInsert )                                                                               \
+    {                                                                                                                               \
+        BlockLink_t * pxIterator;                                                                                                   \
+        size_t xBlockSize;                                                                                                          \
+                                                                                                                                    \
+        xBlockSize = pxBlockToInsert->xBlockSize;                                                                                   \
+                                                                                                                                    \
+        /* Iterate through the list until a block is found that has a larger size */                                                \
+        /* than the block we are inserting. */                                                                                      \
+        for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock ) \
+        {                                                                                                                           \
+            /* There is nothing to do here - just iterate to the correct position. */                                               \
+        }                                                                                                                           \
+                                                                                                                                    \
+        /* Update the list to include the block being inserted in the correct */                                                    \
+        /* position. */                                                                                                             \
+        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;                                                             \
+        pxIterator->pxNextFreeBlock = pxBlockToInsert;                                                                              \
+    }
+/*-----------------------------------------------------------*/
+
+void * pvPortMalloc( size_t xWantedSize )
+{
+    BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
+    static BaseType_t xHeapHasBeenInitialised = pdFALSE;
+    void * pvReturn = NULL;
+
+    vTaskSuspendAll();
+    {
+        /* If this is the first call to malloc then the heap will require
+         * initialisation to setup the list of free blocks. */
+        if( xHeapHasBeenInitialised == pdFALSE )
+        {
+            prvHeapInit();
+            xHeapHasBeenInitialised = pdTRUE;
+        }
+
+        /* The wanted size must be increased so it can contain a BlockLink_t
+         * structure in addition to the requested amount of bytes. */
+        if( ( xWantedSize > 0 ) && 
+            ( ( xWantedSize + heapSTRUCT_SIZE ) >  xWantedSize ) ) /* Overflow check */
+        {
+            xWantedSize += heapSTRUCT_SIZE;
+
+            /* Byte alignment required. Check for overflow. */
+            if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) ) 
+                    > xWantedSize )
+            {
+                xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+                configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+            }
+            else
+            {
+                xWantedSize = 0;
+            }       
+        }
+        else 
+        {
+            xWantedSize = 0; 
+        }
+
+
+        if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+        {
+            /* Blocks are stored in byte order - traverse the list from the start
+             * (smallest) block until one of adequate size is found. */
+            pxPreviousBlock = &xStart;
+            pxBlock = xStart.pxNextFreeBlock;
+
+            while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+            {
+                pxPreviousBlock = pxBlock;
+                pxBlock = pxBlock->pxNextFreeBlock;
+            }
+
+            /* If we found the end marker then a block of adequate size was not found. */
+            if( pxBlock != &xEnd )
+            {
+                /* Return the memory space - jumping over the BlockLink_t structure
+                 * at its start. */
+                pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );
+
+                /* This block is being returned for use so must be taken out of the
+                 * list of free blocks. */
+                pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+                /* If the block is larger than required it can be split into two. */
+                if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+                {
+                    /* This block is to be split into two.  Create a new block
+                     * following the number of bytes requested. The void cast is
+                     * used to prevent byte alignment warnings from the compiler. */
+                    pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+
+                    /* Calculate the sizes of two blocks split from the single
+                     * block. */
+                    pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+                    pxBlock->xBlockSize = xWantedSize;
+
+                    /* Insert the new block into the list of free blocks. */
+                    prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
+                }
+
+                xFreeBytesRemaining -= pxBlock->xBlockSize;
+            }
+        }
+
+        traceMALLOC( pvReturn, xWantedSize );
+    }
+    ( void ) xTaskResumeAll();
+
+    #if ( configUSE_MALLOC_FAILED_HOOK == 1 )
+        {
+            if( pvReturn == NULL )
+            {
+                extern void vApplicationMallocFailedHook( void );
+                vApplicationMallocFailedHook();
+            }
+        }
+    #endif
+
+    return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void * pv )
+{
+    uint8_t * puc = ( uint8_t * ) pv;
+    BlockLink_t * pxLink;
+
+    if( pv != NULL )
+    {
+        /* The memory being freed will have an BlockLink_t structure immediately
+         * before it. */
+        puc -= heapSTRUCT_SIZE;
+
+        /* This unexpected casting is to keep some compilers from issuing
+         * byte alignment warnings. */
+        pxLink = ( void * ) puc;
+
+        vTaskSuspendAll();
+        {
+            /* Add this block to the list of free blocks. */
+            prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+            xFreeBytesRemaining += pxLink->xBlockSize;
+            traceFREE( pv, pxLink->xBlockSize );
+        }
+        ( void ) xTaskResumeAll();
+    }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+    return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+    /* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+    BlockLink_t * pxFirstFreeBlock;
+    uint8_t * pucAlignedHeap;
+
+    /* Ensure the heap starts on a correctly aligned boundary. */
+    pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) & ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+
+    /* xStart is used to hold a pointer to the first item in the list of free
+     * blocks.  The void cast is used to prevent compiler warnings. */
+    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+    xStart.xBlockSize = ( size_t ) 0;
+
+    /* xEnd is used to mark the end of the list of free blocks. */
+    xEnd.xBlockSize = configADJUSTED_HEAP_SIZE;
+    xEnd.pxNextFreeBlock = NULL;
+
+    /* To start with there is a single free block that is sized to take up the
+     * entire heap space. */
+    pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+    pxFirstFreeBlock->xBlockSize = configADJUSTED_HEAP_SIZE;
+    pxFirstFreeBlock->pxNextFreeBlock = &xEnd;
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/heap_3.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/heap_3.c
new file mode 100644
index 0000000..677fefb
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/heap_3.c
@@ -0,0 +1,94 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*
+ * Implementation of pvPortMalloc() and vPortFree() that relies on the
+ * compilers own malloc() and free() implementations.
+ *
+ * This file can only be used if the linker is configured to to generate
+ * a heap memory area.
+ *
+ * See heap_1.c, heap_2.c and heap_4.c for alternative implementations, and the
+ * memory management pages of https://www.FreeRTOS.org for more information.
+ */
+
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+    #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/*-----------------------------------------------------------*/
+
+void * pvPortMalloc( size_t xWantedSize )
+{
+    void * pvReturn;
+
+    vTaskSuspendAll();
+    {
+        pvReturn = malloc( xWantedSize );
+        traceMALLOC( pvReturn, xWantedSize );
+    }
+    ( void ) xTaskResumeAll();
+
+    #if ( configUSE_MALLOC_FAILED_HOOK == 1 )
+        {
+            if( pvReturn == NULL )
+            {
+                extern void vApplicationMallocFailedHook( void );
+                vApplicationMallocFailedHook();
+            }
+        }
+    #endif
+
+    return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void * pv )
+{
+    if( pv )
+    {
+        vTaskSuspendAll();
+        {
+            free( pv );
+            traceFREE( pv, 0 );
+        }
+        ( void ) xTaskResumeAll();
+    }
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/heap_4.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/heap_4.c
new file mode 100644
index 0000000..e4e52a8
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/heap_4.c
@@ -0,0 +1,502 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that combines
+ * (coalescences) adjacent memory blocks as they are freed, and in so doing
+ * limits memory fragmentation.
+ *
+ * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
+ * memory management pages of https://www.FreeRTOS.org for more information.
+ */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+    #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE         ( ( size_t ) 8 )
+
+/* Allocate the memory for the heap. */
+#if ( configAPPLICATION_ALLOCATED_HEAP == 1 )
+
+/* The application writer has already defined the array used for the RTOS
+* heap - probably so it can be placed in a special segment or address. */
+    extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+    PRIVILEGED_DATA static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/* Define the linked list structure.  This is used to link free blocks in order
+ * of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+    struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */
+    size_t xBlockSize;                     /*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks.  The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called automatically to setup the required heap structures the first time
+ * pvPortMalloc() is called.
+ */
+static void prvHeapInit( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+ * block must by correctly byte aligned. */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+PRIVILEGED_DATA static BlockLink_t xStart, * pxEnd = NULL;
+
+/* Keeps track of the number of calls to allocate and free memory as well as the
+ * number of free bytes remaining, but says nothing about fragmentation. */
+PRIVILEGED_DATA static size_t xFreeBytesRemaining = 0U;
+PRIVILEGED_DATA static size_t xMinimumEverFreeBytesRemaining = 0U;
+PRIVILEGED_DATA static size_t xNumberOfSuccessfulAllocations = 0;
+PRIVILEGED_DATA static size_t xNumberOfSuccessfulFrees = 0;
+
+/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
+ * member of an BlockLink_t structure is set then the block belongs to the
+ * application.  When the bit is free the block is still part of the free heap
+ * space. */
+PRIVILEGED_DATA static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void * pvPortMalloc( size_t xWantedSize )
+{
+    BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
+    void * pvReturn = NULL;
+
+    vTaskSuspendAll();
+    {
+        /* If this is the first call to malloc then the heap will require
+         * initialisation to setup the list of free blocks. */
+        if( pxEnd == NULL )
+        {
+            prvHeapInit();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        /* Check the requested block size is not so large that the top bit is
+         * set.  The top bit of the block size member of the BlockLink_t structure
+         * is used to determine who owns the block - the application or the
+         * kernel, so it must be free. */
+        if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+        {
+            /* The wanted size must be increased so it can contain a BlockLink_t
+             * structure in addition to the requested amount of bytes. */
+            if( ( xWantedSize > 0 ) && 
+                ( ( xWantedSize + xHeapStructSize ) >  xWantedSize ) ) /* Overflow check */
+            {
+                xWantedSize += xHeapStructSize;
+
+                /* Ensure that blocks are always aligned. */
+                if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+                {
+                    /* Byte alignment required. Check for overflow. */
+                    if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) ) 
+                            > xWantedSize )
+                    {
+                        xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+                        configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+                    }
+                    else
+                    {
+                        xWantedSize = 0;
+                    }  
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            } 
+            else 
+            {
+                xWantedSize = 0;
+            }
+
+            if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+            {
+                /* Traverse the list from the start	(lowest address) block until
+                 * one of adequate size is found. */
+                pxPreviousBlock = &xStart;
+                pxBlock = xStart.pxNextFreeBlock;
+
+                while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+                {
+                    pxPreviousBlock = pxBlock;
+                    pxBlock = pxBlock->pxNextFreeBlock;
+                }
+
+                /* If the end marker was reached then a block of adequate size
+                 * was not found. */
+                if( pxBlock != pxEnd )
+                {
+                    /* Return the memory space pointed to - jumping over the
+                     * BlockLink_t structure at its start. */
+                    pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+                    /* This block is being returned for use so must be taken out
+                     * of the list of free blocks. */
+                    pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+                    /* If the block is larger than required it can be split into
+                     * two. */
+                    if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+                    {
+                        /* This block is to be split into two.  Create a new
+                         * block following the number of bytes requested. The void
+                         * cast is used to prevent byte alignment warnings from the
+                         * compiler. */
+                        pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+                        configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+                        /* Calculate the sizes of two blocks split from the
+                         * single block. */
+                        pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+                        pxBlock->xBlockSize = xWantedSize;
+
+                        /* Insert the new block into the list of free blocks. */
+                        prvInsertBlockIntoFreeList( pxNewBlockLink );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+                    if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+                    {
+                        xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    /* The block is being returned - it is allocated and owned
+                     * by the application and has no "next" block. */
+                    pxBlock->xBlockSize |= xBlockAllocatedBit;
+                    pxBlock->pxNextFreeBlock = NULL;
+                    xNumberOfSuccessfulAllocations++;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceMALLOC( pvReturn, xWantedSize );
+    }
+    ( void ) xTaskResumeAll();
+
+    #if ( configUSE_MALLOC_FAILED_HOOK == 1 )
+        {
+            if( pvReturn == NULL )
+            {
+                extern void vApplicationMallocFailedHook( void );
+                vApplicationMallocFailedHook();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */
+
+    configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
+    return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void * pv )
+{
+    uint8_t * puc = ( uint8_t * ) pv;
+    BlockLink_t * pxLink;
+
+    if( pv != NULL )
+    {
+        /* The memory being freed will have an BlockLink_t structure immediately
+         * before it. */
+        puc -= xHeapStructSize;
+
+        /* This casting is to keep the compiler from issuing warnings. */
+        pxLink = ( void * ) puc;
+
+        /* Check the block is actually allocated. */
+        configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        {
+            if( pxLink->pxNextFreeBlock == NULL )
+            {
+                /* The block is being returned to the heap - it is no longer
+                 * allocated. */
+                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+                vTaskSuspendAll();
+                {
+                    /* Add this block to the list of free blocks. */
+                    xFreeBytesRemaining += pxLink->xBlockSize;
+                    traceFREE( pv, pxLink->xBlockSize );
+                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+                    xNumberOfSuccessfulFrees++;
+                }
+                ( void ) xTaskResumeAll();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+    return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+    return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+    /* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void ) /* PRIVILEGED_FUNCTION */
+{
+    BlockLink_t * pxFirstFreeBlock;
+    uint8_t * pucAlignedHeap;
+    size_t uxAddress;
+    size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+
+    /* Ensure the heap starts on a correctly aligned boundary. */
+    uxAddress = ( size_t ) ucHeap;
+
+    if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+    {
+        uxAddress += ( portBYTE_ALIGNMENT - 1 );
+        uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+        xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
+    }
+
+    pucAlignedHeap = ( uint8_t * ) uxAddress;
+
+    /* xStart is used to hold a pointer to the first item in the list of free
+     * blocks.  The void cast is used to prevent compiler warnings. */
+    xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+    xStart.xBlockSize = ( size_t ) 0;
+
+    /* pxEnd is used to mark the end of the list of free blocks and is inserted
+     * at the end of the heap space. */
+    uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
+    uxAddress -= xHeapStructSize;
+    uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+    pxEnd = ( void * ) uxAddress;
+    pxEnd->xBlockSize = 0;
+    pxEnd->pxNextFreeBlock = NULL;
+
+    /* To start with there is a single free block that is sized to take up the
+     * entire heap space, minus the space taken by pxEnd. */
+    pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+    pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
+    pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+    /* Only one block exists - and it covers the entire usable heap space. */
+    xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+    xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+    /* Work out the position of the top bit in a size_t variable. */
+    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert ) /* PRIVILEGED_FUNCTION */
+{
+    BlockLink_t * pxIterator;
+    uint8_t * puc;
+
+    /* Iterate through the list until a block is found that has a higher address
+     * than the block being inserted. */
+    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+    {
+        /* Nothing to do here, just iterate to the right position. */
+    }
+
+    /* Do the block being inserted, and the block it is being inserted after
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxIterator;
+
+    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+    {
+        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+        pxBlockToInsert = pxIterator;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Do the block being inserted, and the block it is being inserted before
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxBlockToInsert;
+
+    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+    {
+        if( pxIterator->pxNextFreeBlock != pxEnd )
+        {
+            /* Form one big block from the two blocks. */
+            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+        }
+        else
+        {
+            pxBlockToInsert->pxNextFreeBlock = pxEnd;
+        }
+    }
+    else
+    {
+        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+    }
+
+    /* If the block being inserted plugged a gab, so was merged with the block
+     * before and the block after, then it's pxNextFreeBlock pointer will have
+     * already been set, and should not be set here as that would make it point
+     * to itself. */
+    if( pxIterator != pxBlockToInsert )
+    {
+        pxIterator->pxNextFreeBlock = pxBlockToInsert;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortGetHeapStats( HeapStats_t * pxHeapStats )
+{
+    BlockLink_t * pxBlock;
+    size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */
+
+    vTaskSuspendAll();
+    {
+        pxBlock = xStart.pxNextFreeBlock;
+
+        /* pxBlock will be NULL if the heap has not been initialised.  The heap
+         * is initialised automatically when the first allocation is made. */
+        if( pxBlock != NULL )
+        {
+            do
+            {
+                /* Increment the number of blocks and record the largest block seen
+                 * so far. */
+                xBlocks++;
+
+                if( pxBlock->xBlockSize > xMaxSize )
+                {
+                    xMaxSize = pxBlock->xBlockSize;
+                }
+
+                if( pxBlock->xBlockSize < xMinSize )
+                {
+                    xMinSize = pxBlock->xBlockSize;
+                }
+
+                /* Move to the next block in the chain until the last block is
+                 * reached. */
+                pxBlock = pxBlock->pxNextFreeBlock;
+            } while( pxBlock != pxEnd );
+        }
+    }
+    ( void ) xTaskResumeAll();
+
+    pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize;
+    pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize;
+    pxHeapStats->xNumberOfFreeBlocks = xBlocks;
+
+    taskENTER_CRITICAL();
+    {
+        pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining;
+        pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations;
+        pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees;
+        pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining;
+    }
+    taskEXIT_CRITICAL();
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/heap_5.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/heap_5.c
new file mode 100644
index 0000000..52390f5
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MemMang/heap_5.c
@@ -0,0 +1,557 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * A sample implementation of pvPortMalloc() that allows the heap to be defined
+ * across multiple non-contigous blocks and combines (coalescences) adjacent
+ * memory blocks as they are freed.
+ *
+ * See heap_1.c, heap_2.c, heap_3.c and heap_4.c for alternative
+ * implementations, and the memory management pages of https://www.FreeRTOS.org
+ * for more information.
+ *
+ * Usage notes:
+ *
+ * vPortDefineHeapRegions() ***must*** be called before pvPortMalloc().
+ * pvPortMalloc() will be called if any task objects (tasks, queues, event
+ * groups, etc.) are created, therefore vPortDefineHeapRegions() ***must*** be
+ * called before any other objects are defined.
+ *
+ * vPortDefineHeapRegions() takes a single parameter.  The parameter is an array
+ * of HeapRegion_t structures.  HeapRegion_t is defined in portable.h as
+ *
+ * typedef struct HeapRegion
+ * {
+ *	uint8_t *pucStartAddress; << Start address of a block of memory that will be part of the heap.
+ *	size_t xSizeInBytes;	  << Size of the block of memory.
+ * } HeapRegion_t;
+ *
+ * The array is terminated using a NULL zero sized region definition, and the
+ * memory regions defined in the array ***must*** appear in address order from
+ * low address to high address.  So the following is a valid example of how
+ * to use the function.
+ *
+ * HeapRegion_t xHeapRegions[] =
+ * {
+ *  { ( uint8_t * ) 0x80000000UL, 0x10000 }, << Defines a block of 0x10000 bytes starting at address 0x80000000
+ *  { ( uint8_t * ) 0x90000000UL, 0xa0000 }, << Defines a block of 0xa0000 bytes starting at address of 0x90000000
+ *  { NULL, 0 }                << Terminates the array.
+ * };
+ *
+ * vPortDefineHeapRegions( xHeapRegions ); << Pass the array into vPortDefineHeapRegions().
+ *
+ * Note 0x80000000 is the lower address so appears in the array first.
+ *
+ */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+    #error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
+#endif
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE    ( ( size_t ) ( xHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE         ( ( size_t ) 8 )
+
+/* Define the linked list structure.  This is used to link free blocks in order
+ * of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+    struct A_BLOCK_LINK * pxNextFreeBlock; /*<< The next free block in the list. */
+    size_t xBlockSize;                     /*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks.  The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert );
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+ * block must by correctly byte aligned. */
+static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, * pxEnd = NULL;
+
+/* Keeps track of the number of calls to allocate and free memory as well as the
+ * number of free bytes remaining, but says nothing about fragmentation. */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+static size_t xNumberOfSuccessfulAllocations = 0;
+static size_t xNumberOfSuccessfulFrees = 0;
+
+/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
+ * member of an BlockLink_t structure is set then the block belongs to the
+ * application.  When the bit is free the block is still part of the free heap
+ * space. */
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void * pvPortMalloc( size_t xWantedSize )
+{
+    BlockLink_t * pxBlock, * pxPreviousBlock, * pxNewBlockLink;
+    void * pvReturn = NULL;
+
+    /* The heap must be initialised before the first call to
+     * prvPortMalloc(). */
+    configASSERT( pxEnd );
+
+    vTaskSuspendAll();
+    {
+        /* Check the requested block size is not so large that the top bit is
+         * set.  The top bit of the block size member of the BlockLink_t structure
+         * is used to determine who owns the block - the application or the
+         * kernel, so it must be free. */
+        if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+        {
+            /* The wanted size is increased so it can contain a BlockLink_t
+             * structure in addition to the requested amount of bytes. */
+            if( ( xWantedSize > 0 ) && 
+                ( ( xWantedSize + xHeapStructSize ) >  xWantedSize ) ) /* Overflow check */
+            {
+                xWantedSize += xHeapStructSize;
+
+                /* Ensure that blocks are always aligned */
+                if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+                {
+                    /* Byte alignment required. Check for overflow */
+                    if( ( xWantedSize + ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) ) ) >
+                         xWantedSize )
+                    {
+                        xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+                    } 
+                    else 
+                    {
+                        xWantedSize = 0;
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                xWantedSize = 0;
+            }
+
+            if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+            {
+                /* Traverse the list from the start	(lowest address) block until
+                 * one of adequate size is found. */
+                pxPreviousBlock = &xStart;
+                pxBlock = xStart.pxNextFreeBlock;
+
+                while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+                {
+                    pxPreviousBlock = pxBlock;
+                    pxBlock = pxBlock->pxNextFreeBlock;
+                }
+
+                /* If the end marker was reached then a block of adequate size
+                 * was not found. */
+                if( pxBlock != pxEnd )
+                {
+                    /* Return the memory space pointed to - jumping over the
+                     * BlockLink_t structure at its start. */
+                    pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+                    /* This block is being returned for use so must be taken out
+                     * of the list of free blocks. */
+                    pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+                    /* If the block is larger than required it can be split into
+                     * two. */
+                    if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+                    {
+                        /* This block is to be split into two.  Create a new
+                         * block following the number of bytes requested. The void
+                         * cast is used to prevent byte alignment warnings from the
+                         * compiler. */
+                        pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+
+                        /* Calculate the sizes of two blocks split from the
+                         * single block. */
+                        pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+                        pxBlock->xBlockSize = xWantedSize;
+
+                        /* Insert the new block into the list of free blocks. */
+                        prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+                    if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+                    {
+                        xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    /* The block is being returned - it is allocated and owned
+                     * by the application and has no "next" block. */
+                    pxBlock->xBlockSize |= xBlockAllocatedBit;
+                    pxBlock->pxNextFreeBlock = NULL;
+                    xNumberOfSuccessfulAllocations++;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        traceMALLOC( pvReturn, xWantedSize );
+    }
+    ( void ) xTaskResumeAll();
+
+    #if ( configUSE_MALLOC_FAILED_HOOK == 1 )
+        {
+            if( pvReturn == NULL )
+            {
+                extern void vApplicationMallocFailedHook( void );
+                vApplicationMallocFailedHook();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    #endif /* if ( configUSE_MALLOC_FAILED_HOOK == 1 ) */
+
+    return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void * pv )
+{
+    uint8_t * puc = ( uint8_t * ) pv;
+    BlockLink_t * pxLink;
+
+    if( pv != NULL )
+    {
+        /* The memory being freed will have an BlockLink_t structure immediately
+         * before it. */
+        puc -= xHeapStructSize;
+
+        /* This casting is to keep the compiler from issuing warnings. */
+        pxLink = ( void * ) puc;
+
+        /* Check the block is actually allocated. */
+        configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+        configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+        if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+        {
+            if( pxLink->pxNextFreeBlock == NULL )
+            {
+                /* The block is being returned to the heap - it is no longer
+                 * allocated. */
+                pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+                vTaskSuspendAll();
+                {
+                    /* Add this block to the list of free blocks. */
+                    xFreeBytesRemaining += pxLink->xBlockSize;
+                    traceFREE( pv, pxLink->xBlockSize );
+                    prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+                    xNumberOfSuccessfulFrees++;
+                }
+                ( void ) xTaskResumeAll();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+    return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+    return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t * pxBlockToInsert )
+{
+    BlockLink_t * pxIterator;
+    uint8_t * puc;
+
+    /* Iterate through the list until a block is found that has a higher address
+     * than the block being inserted. */
+    for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+    {
+        /* Nothing to do here, just iterate to the right position. */
+    }
+
+    /* Do the block being inserted, and the block it is being inserted after
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxIterator;
+
+    if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+    {
+        pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+        pxBlockToInsert = pxIterator;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    /* Do the block being inserted, and the block it is being inserted before
+     * make a contiguous block of memory? */
+    puc = ( uint8_t * ) pxBlockToInsert;
+
+    if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+    {
+        if( pxIterator->pxNextFreeBlock != pxEnd )
+        {
+            /* Form one big block from the two blocks. */
+            pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+            pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+        }
+        else
+        {
+            pxBlockToInsert->pxNextFreeBlock = pxEnd;
+        }
+    }
+    else
+    {
+        pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+    }
+
+    /* If the block being inserted plugged a gab, so was merged with the block
+     * before and the block after, then it's pxNextFreeBlock pointer will have
+     * already been set, and should not be set here as that would make it point
+     * to itself. */
+    if( pxIterator != pxBlockToInsert )
+    {
+        pxIterator->pxNextFreeBlock = pxBlockToInsert;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )
+{
+    BlockLink_t * pxFirstFreeBlockInRegion = NULL, * pxPreviousFreeBlock;
+    size_t xAlignedHeap;
+    size_t xTotalRegionSize, xTotalHeapSize = 0;
+    BaseType_t xDefinedRegions = 0;
+    size_t xAddress;
+    const HeapRegion_t * pxHeapRegion;
+
+    /* Can only call once! */
+    configASSERT( pxEnd == NULL );
+
+    pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
+
+    while( pxHeapRegion->xSizeInBytes > 0 )
+    {
+        xTotalRegionSize = pxHeapRegion->xSizeInBytes;
+
+        /* Ensure the heap region starts on a correctly aligned boundary. */
+        xAddress = ( size_t ) pxHeapRegion->pucStartAddress;
+
+        if( ( xAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+        {
+            xAddress += ( portBYTE_ALIGNMENT - 1 );
+            xAddress &= ~portBYTE_ALIGNMENT_MASK;
+
+            /* Adjust the size for the bytes lost to alignment. */
+            xTotalRegionSize -= xAddress - ( size_t ) pxHeapRegion->pucStartAddress;
+        }
+
+        xAlignedHeap = xAddress;
+
+        /* Set xStart if it has not already been set. */
+        if( xDefinedRegions == 0 )
+        {
+            /* xStart is used to hold a pointer to the first item in the list of
+             *  free blocks.  The void cast is used to prevent compiler warnings. */
+            xStart.pxNextFreeBlock = ( BlockLink_t * ) xAlignedHeap;
+            xStart.xBlockSize = ( size_t ) 0;
+        }
+        else
+        {
+            /* Should only get here if one region has already been added to the
+             * heap. */
+            configASSERT( pxEnd != NULL );
+
+            /* Check blocks are passed in with increasing start addresses. */
+            configASSERT( xAddress > ( size_t ) pxEnd );
+        }
+
+        /* Remember the location of the end marker in the previous region, if
+         * any. */
+        pxPreviousFreeBlock = pxEnd;
+
+        /* pxEnd is used to mark the end of the list of free blocks and is
+         * inserted at the end of the region space. */
+        xAddress = xAlignedHeap + xTotalRegionSize;
+        xAddress -= xHeapStructSize;
+        xAddress &= ~portBYTE_ALIGNMENT_MASK;
+        pxEnd = ( BlockLink_t * ) xAddress;
+        pxEnd->xBlockSize = 0;
+        pxEnd->pxNextFreeBlock = NULL;
+
+        /* To start with there is a single free block in this region that is
+         * sized to take up the entire heap region minus the space taken by the
+         * free block structure. */
+        pxFirstFreeBlockInRegion = ( BlockLink_t * ) xAlignedHeap;
+        pxFirstFreeBlockInRegion->xBlockSize = xAddress - ( size_t ) pxFirstFreeBlockInRegion;
+        pxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd;
+
+        /* If this is not the first region that makes up the entire heap space
+         * then link the previous region to this region. */
+        if( pxPreviousFreeBlock != NULL )
+        {
+            pxPreviousFreeBlock->pxNextFreeBlock = pxFirstFreeBlockInRegion;
+        }
+
+        xTotalHeapSize += pxFirstFreeBlockInRegion->xBlockSize;
+
+        /* Move onto the next HeapRegion_t structure. */
+        xDefinedRegions++;
+        pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
+    }
+
+    xMinimumEverFreeBytesRemaining = xTotalHeapSize;
+    xFreeBytesRemaining = xTotalHeapSize;
+
+    /* Check something was actually defined before it is accessed. */
+    configASSERT( xTotalHeapSize );
+
+    /* Work out the position of the top bit in a size_t variable. */
+    xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+void vPortGetHeapStats( HeapStats_t * pxHeapStats )
+{
+    BlockLink_t * pxBlock;
+    size_t xBlocks = 0, xMaxSize = 0, xMinSize = portMAX_DELAY; /* portMAX_DELAY used as a portable way of getting the maximum value. */
+
+    vTaskSuspendAll();
+    {
+        pxBlock = xStart.pxNextFreeBlock;
+
+        /* pxBlock will be NULL if the heap has not been initialised.  The heap
+         * is initialised automatically when the first allocation is made. */
+        if( pxBlock != NULL )
+        {
+            do
+            {
+                /* Increment the number of blocks and record the largest block seen
+                 * so far. */
+                xBlocks++;
+
+                if( pxBlock->xBlockSize > xMaxSize )
+                {
+                    xMaxSize = pxBlock->xBlockSize;
+                }
+
+                /* Heap five will have a zero sized block at the end of each
+                 * each region - the block is only used to link to the next
+                 * heap region so it not a real block. */
+                if( pxBlock->xBlockSize != 0 )
+                {
+                    if( pxBlock->xBlockSize < xMinSize )
+                    {
+                        xMinSize = pxBlock->xBlockSize;
+                    }
+                }
+
+                /* Move to the next block in the chain until the last block is
+                 * reached. */
+                pxBlock = pxBlock->pxNextFreeBlock;
+            } while( pxBlock != pxEnd );
+        }
+    }
+    ( void ) xTaskResumeAll();
+
+    pxHeapStats->xSizeOfLargestFreeBlockInBytes = xMaxSize;
+    pxHeapStats->xSizeOfSmallestFreeBlockInBytes = xMinSize;
+    pxHeapStats->xNumberOfFreeBlocks = xBlocks;
+
+    taskENTER_CRITICAL();
+    {
+        pxHeapStats->xAvailableHeapSpaceInBytes = xFreeBytesRemaining;
+        pxHeapStats->xNumberOfSuccessfulAllocations = xNumberOfSuccessfulAllocations;
+        pxHeapStats->xNumberOfSuccessfulFrees = xNumberOfSuccessfulFrees;
+        pxHeapStats->xMinimumEverFreeBytesRemaining = xMinimumEverFreeBytesRemaining;
+    }
+    taskEXIT_CRITICAL();
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MikroC/ARM_CM4F/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MikroC/ARM_CM4F/port.c
new file mode 100644
index 0000000..e079395
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MikroC/ARM_CM4F/port.c
@@ -0,0 +1,839 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM4F port.
+*----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
+#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                    ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK                   ( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR                             ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS              ( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                      ( 0x01000000 )
+#define portINITIAL_EXC_RETURN                ( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#define portMISSED_COUNTS_FACTOR              ( 45UL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/* Cannot find a weak linkage attribute, so the
+ * configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if the
+ * application writer wants to provide their own implementation of
+ * vPortSetupTimerInterrupt().  Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+ * is defined. */
+#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+    #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION    0
+#endif
+
+/* Manual definition of missing asm names. */
+#define psp        9
+#define basepri    17
+#define msp        8
+#define ipsr       5
+#define control    20
+
+/* From port.c. */
+extern void * pxCurrentTCB;
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void );
+
+/*
+ * Function to enable the VFP.
+ */
+static void vPortEnableVFP( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+
+    /* Offset added to account for the way the MCU uses the stack on entry/exit
+     * of interrupts, and to ensure alignment. */
+    pxTopOfStack--;
+
+    /* Sometimes the parameters are loaded from the stack. */
+    *pxTopOfStack = ( StackType_t ) pvParameters;
+    pxTopOfStack--;
+
+    *pxTopOfStack = portINITIAL_XPSR;                        /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) pxCode;                  /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS; /* LR */
+
+    /* Save code space by skipping register initialisation. */
+    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+    /* A save method is being used that requires each task to maintain its
+     * own exec return value. */
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+    pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( uxCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    for( ; ; )
+    {
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void ) iv IVT_INT_SVCall ics ICS_OFF
+{
+    __asm {
+/* *INDENT-OFF* */
+        ldr r3, =_pxCurrentTCB     /* Restore the context. */
+        ldr r1, [ r3 ]    /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+        ldr r0, [ r1 ]              /* The first item in pxCurrentTCB is the task top of stack. */
+        ldm r0 !, ( r4 - r11, r14 ) /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+        msr psp, r0                 /* Restore the task stack pointer. */
+        isb
+        mov r0, #0
+        msr basepri, r0
+        bx r14
+/* *INDENT-ON* */
+    };
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+    __asm {
+/* *INDENT-OFF* */
+        ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
+        ldr r0, [ r0 ]
+        ldr r0, [ r0 ]
+        msr msp, r0 /* Set the msp back to the start of the stack. */
+
+        /* Clear the bit that indicates the FPU is in use in case the FPU was used
+         * before the scheduler was started - which would otherwise result in the
+         * unnecessary leaving of space in the SVC stack for lazy saving of FPU
+         * registers. */
+        mov r0, #0
+        msr control, r0
+        cpsie i /* Globally enable interrupts. */
+        cpsie f
+        dsb
+        isb
+        svc #0 /* System call to start first task. */
+        nop
+/* *INDENT-ON* */
+    };
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+            volatile uint8_t ucMaxPriorityValue;
+
+            /* Determine the maximum priority from which ISR safe FreeRTOS API
+             * functions can be called.  ISR safe functions are those that end in
+             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+             * ensure interrupt entry is as fast and simple as possible.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+            /* Determine the number of priority bits available.  First write to all
+             * possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+            /* The kernel interrupt priority should be set to the lowest
+             * priority. */
+            configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
+
+            /* Use the same mask on the maximum system call priority. */
+            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+            /* Calculate the maximum acceptable priority group value for the number
+             * of bits read back. */
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+            {
+                ulMaxPRIGROUPValue--;
+                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+            }
+
+            #ifdef __NVIC_PRIO_BITS
+                {
+                    /* Check the CMSIS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+                }
+            #endif
+
+            #ifdef configPRIO_BITS
+                {
+                    /* Check the FreeRTOS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+                }
+            #endif
+
+            /* Shift the priority group value back to its position within the AIRCR
+             * register. */
+            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* conifgASSERT_DEFINED */
+
+    /* Make PendSV and SysTick the lowest priority interrupts. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Ensure the VFP is enabled - it should be anyway. */
+    vPortEnableVFP();
+
+    /* Lazy save always. */
+    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+    /* Start the first task. */
+    prvPortStartFirstTask();
+
+    /* Should never get here as the tasks will now be executing!  Call the task
+     * exit error function to prevent compiler warnings about a static function
+     * not being called in the case that the application writer overrides this
+     * functionality by defining configTASK_RETURN_ADDRESS. */
+    prvTaskExitError();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
+    if( uxCriticalNesting == 1 )
+    {
+        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+const uint8_t ucMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+void xPortPendSVHandler( void ) iv IVT_INT_PendSV ics ICS_OFF
+{
+    __asm {
+        #ifdef HW_DEBUG
+/* *INDENT-OFF* */
+
+            /* The function is not truly naked, so add back the 4 bytes subtracted
+            * from the stack pointer by the function prologue. */
+            add sp, sp, # 4
+        #endif
+        mrs r0, psp
+        isb
+
+        ldr r3, =_pxCurrentTCB /* Get the location of the current TCB. */
+        ldr r2, [ r3 ]
+
+        tst r14, #0x10 /* Is the task using the FPU context?  If so, push high vfp registers. */
+        it eq
+        vstmdbeq r0 !, ( s16 - s31 )
+
+        stmdb r0 !, ( r4 - r11, r14 ) /* Save the core registers. */
+
+        str r0, [ r2 ]                /* Save the new top of stack into the first member of the TCB. */
+
+        stmdb sp !, ( r0, r3 )
+        ldr r0, = _ucMaxSyscallInterruptPriority
+        ldr r1, [ r0 ]
+        msr basepri, r1
+        dsb
+        isb
+        bl _vTaskSwitchContext
+        mov r0, #0
+        msr basepri, r0
+        ldm sp !, ( r0, r3 )
+
+        ldr r1, [ r3 ] /* The first item in pxCurrentTCB is the task top of stack. */
+        ldr r0, [ r1 ]
+
+        ldm r0 !, ( r4 - r11, r14 ) /* Pop the core registers. */
+
+        tst r14, #0x10             /* Is the task using the FPU context?  If so, pop the high vfp registers too. */
+        it eq
+        vldmiaeq r0 !, ( s16 - s31 )
+
+        msr psp, r0
+        isb
+        bx r14
+/* *INDENT-ON* */
+    }
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void ) iv IVT_INT_SysTick ics ICS_AUTO
+{
+    /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+     * executes all interrupts must be unmasked.  There is therefore no need to
+     * save and then restore the interrupt mask value as its value is already
+     * known - therefore the slightly faster portDISABLE_INTERRUPTS() function is
+     * used in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
+    portDISABLE_INTERRUPTS();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* A context switch is required.  Context switching is performed in
+             * the PendSV interrupt.  Pend the PendSV interrupt. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+    #if ( ( configUSE_TICKLESS_IDLE == 1 ) && ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) )
+
+    void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+         * is accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods.  -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __asm {
+            "cpsid i"
+        };
+        __asm {
+            "dsb"
+        };
+        __asm {
+            "isb"
+        };
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above the cpsid instruction()
+             * above. */
+            __asm {
+                "cpsie i"
+            };
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again.  However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __asm {
+                    "dsb"
+                };
+                __asm {
+                    "wfi"
+                };
+                __asm {
+                    "isb"
+                };
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately.  see comments above
+             * __disable_interrupt() call above. */
+            __asm {
+                "cpsie i"
+            };
+            __asm {
+                "dsb"
+            };
+            __asm {
+                "isb"
+            };
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __asm {
+                "cpsid i"
+            };
+            __asm {
+                "dsb"
+            };
+            __asm {
+                "isb"
+            };
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is yet
+             * to count to zero (in which case an interrupt other than the SysTick
+             * must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __asm {
+                "cpsie i"
+            };
+        }
+    }
+
+    #endif /* #if configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+    #if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
+
+    void vPortSetupTimerInterrupt( void )
+    {
+        /* Calculate the constants required to configure the tick interrupt. */
+        #if ( configUSE_TICKLESS_IDLE == 1 )
+            {
+                ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+                xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+                ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+            }
+        #endif /* configUSE_TICKLESS_IDLE */
+
+        /* Reset SysTick. */
+        portNVIC_SYSTICK_CTRL_REG = 0UL;
+        portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+        /* Configure SysTick to interrupt at the requested rate. */
+        portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+        portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+    }
+
+    #endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
+/*-----------------------------------------------------------*/
+
+/* This is a naked function. */
+static void vPortEnableVFP( void )
+{
+    __asm {
+/* *INDENT-OFF* */
+        ldr r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */
+        ldr r1, [ r0 ]
+
+        orr r1, r1, #0xF00000 /* Enable CP10 and CP11 coprocessors, then save back. */
+        str r1, [ r0 ]
+        bx r14
+/* *INDENT-ON* */
+    };
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortIsInsideInterrupt( void )
+{
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. */
+    if( CPU_REG_GET( CPU_IPSR ) == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+    #if ( configASSERT_DEFINED == 1 )
+
+/* Limitations in the MikroC inline asm means ulCurrentInterrupt has to be
+ * global - which makes vPortValidateInterruptPriority() non re-entrant.
+ * However that should not matter as an interrupt can only itself be
+ * interrupted by a higher priority interrupt.  That means if
+ * ulCurrentInterrupt, so ulCurrentInterrupt getting corrupted cannot lead to
+ * an invalid interrupt priority being missed. */
+    uint32_t ulCurrentInterrupt;
+    uint8_t ucCurrentPriority;
+    void vPortValidateInterruptPriority( void )
+    {
+        /* Obtain the number of the currently executing interrupt. */
+        __asm {
+/* *INDENT-OFF* */
+            push( r0, r1 )
+            mrs r0, ipsr
+            ldr r1, =_ulCurrentInterrupt
+            str r0, [ r1 ]
+            pop( r0, r1 )
+/* *INDENT-ON* */
+        };
+
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = *( ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + ulCurrentInterrupt ) );
+
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that	use the FreeRTOS API must not be left at their
+             * default priority of	zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and	therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
+
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredictable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
+
+    #endif /* configASSERT_DEFINED */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MikroC/ARM_CM4F/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MikroC/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..6a9a9ce
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/MikroC/ARM_CM4F/portmacro.h
@@ -0,0 +1,189 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* The compiler needs to be told functions that are only referenced by pointer
+ * are to be included in the build.  NOTE:  Omitting these lines will result in a
+ * run-time crash, not a linker error! */
+    #pragma funcall vTaskStartScheduler prvIdleTask
+    #pragma funcall xTimerCreateTimerTask prvTimerTask
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+    #define portYIELD()                                 \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+                                                        \
+        /* Barriers are normally not required but do ensure the code is completely \
+         * within the specified behaviour for the architecture. */ \
+        __asm{ dsb };                                              \
+        __asm{ isb };                                              \
+    }
+
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired != pdFALSE ) portYIELD()
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+    #define portDISABLE_INTERRUPTS()                  CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm{ dsb }; __asm{ isb }
+    #define portENABLE_INTERRUPTS()                   CPU_REG_SET( CPU_BASEPRI, 0 );
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    CPU_REG_SET( CPU_BASEPRI, x ); /* Barrier instructions not used as this is only used to lower the basepri. */
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #endif
+
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Generic helper function. */
+        __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+        {
+            uint8_t ucReturn;
+
+            __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+
+            return ucReturn;
+        }
+
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
+
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+    #endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
+
+/* portNOP() is not required by this port. */
+    #define portNOP()
+
+    BaseType_t xPortIsInsideInterrupt( void );
+
+/*-----------------------------------------------------------*/
+
+    static inline uint32_t ulPortRaiseBASEPRI( void )
+    {
+        uint32_t ulOriginalBASEPRI;
+
+        ulOriginalBASEPRI = CPU_REG_GET( CPU_BASEPRI );
+        CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY );
+        __asm{ dsb };
+        __asm{ isb };
+        return ulOriginalBASEPRI;
+    }
+/*-----------------------------------------------------------*/
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/port.c
new file mode 100644
index 0000000..e4017b9
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/port.c
@@ -0,0 +1,239 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Tern EE 186
+ * port.
+ *----------------------------------------------------------*/
+
+/* Library includes. */
+#include <embedded.h>
+#include <ae.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portasm.h"
+
+/* The timer increments every four clocks, hence the divide by 4. */
+#define portTIMER_COMPARE ( uint16_t ) ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / ( uint32_t ) 4 )
+
+/* From the RDC data sheet. */
+#define portENABLE_TIMER_AND_INTERRUPT ( uint16_t ) 0xe001
+
+/* Interrupt control. */
+#define portEIO_REGISTER 0xff22
+#define portCLEAR_INTERRUPT 0x0008
+
+/* Setup the hardware to generate the required tick frequency. */
+static void prvSetupTimerInterrupt( void );
+
+/* The ISR used depends on whether the preemptive or cooperative scheduler
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+	/* Tick service routine used by the scheduler when preemptive scheduling is
+	being used. */
+	static void __interrupt __far prvPreemptiveTick( void );
+#else
+	/* Tick service routine used by the scheduler when cooperative scheduling is
+	being used. */
+	static void __interrupt __far prvNonPreemptiveTick( void );
+#endif
+
+/* Trap routine used by taskYIELD() to manually cause a context switch. */
+static void __interrupt __far prvYieldProcessor( void );
+
+/* The timer initialisation functions leave interrupts enabled,
+which is not what we want.  This ISR is installed temporarily in case
+the timer fires before we get a change to disable interrupts again. */
+static void __interrupt __far prvDummyISR( void );
+
+/*-----------------------------------------------------------*/
+/* See header file for description. */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t DS_Reg = 0;
+
+	/* Place a few bytes of known values on the bottom of the stack.
+	This is just useful for debugging. */
+
+	*pxTopOfStack = 0x1111;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2222;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x3333;
+	pxTopOfStack--;
+
+	/* We are going to start the scheduler using a return from interrupt
+	instruction to load the program counter, so first there would be the
+	function call with parameters preamble. */
+	
+	*pxTopOfStack = FP_SEG( pvParameters );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pvParameters );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_SEG( pxCode );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pxCode );
+	pxTopOfStack--;
+
+	/* Next the status register and interrupt return address. */
+	*pxTopOfStack = portINITIAL_SW;
+	pxTopOfStack--;
+	*pxTopOfStack = FP_SEG( pxCode );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pxCode );
+	pxTopOfStack--;
+
+	/* The remaining registers would be pushed on the stack by our context
+	switch function.  These are loaded with values simply to make debugging
+	easier. */
+	*pxTopOfStack = ( StackType_t ) 0xAAAA;	/* AX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xCCCC;	/* CX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xEEEE;	/* ES */
+	pxTopOfStack--;
+
+	/* We need the true data segment. */
+	__asm{	MOV DS_Reg, DS };
+
+	*pxTopOfStack = DS_Reg;						/* DS */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0123;	/* SI */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DI */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BP */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* This is called with interrupts already disabled. */
+
+	/* Put our manual switch (yield) function on a known
+	vector. */
+	setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+
+	/* Setup the tick interrupt. */
+	prvSetupTimerInterrupt();
+
+	/* Kick off the scheduler by setting up the context of the first task. */
+	portFIRST_CONTEXT();
+
+	/* Should not get here! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+static void __interrupt __far prvDummyISR( void )
+{
+	/* The timer initialisation functions leave interrupts enabled,
+	which is not what we want.  This ISR is installed temporarily in case
+	the timer fires before we get a change to disable interrupts again. */
+	outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
+}
+/*-----------------------------------------------------------*/
+
+/* The ISR used depends on whether the preemptive or cooperative scheduler
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+	static void __interrupt __far prvPreemptiveTick( void )
+	{
+		/* Get the scheduler to update the task states following the tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Switch in the context of the next task to be run. */
+			portSWITCH_CONTEXT();
+		}
+
+		/* Reset interrupt. */
+		outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
+	}
+#else
+	static void __interrupt __far prvNonPreemptiveTick( void )
+	{
+		/* Same as preemptive tick, but the cooperative scheduler is being used
+		so we don't have to switch in the context of the next task. */
+		xTaskIncrementTick();
+		
+		/* Reset interrupt. */
+		outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+static void __interrupt __far prvYieldProcessor( void )
+{
+	/* Switch in the context of the next task to be run. */
+	portSWITCH_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+const uint16_t usTimerACompare = portTIMER_COMPARE, usTimerAMode = portENABLE_TIMER_AND_INTERRUPT;
+const uint16_t usT2_IRQ = 0x13;
+
+	/* Configure the timer, the dummy handler is used here as the init
+	function leaves interrupts enabled. */
+	t2_init( usTimerAMode, usTimerACompare, prvDummyISR );
+
+	/* Disable interrupts again before installing the real handlers. */
+	portDISABLE_INTERRUPTS();
+
+	#if( configUSE_PREEMPTION == 1 )
+		/* Tick service routine used by the scheduler when preemptive scheduling is
+		being used. */
+		setvect( usT2_IRQ, prvPreemptiveTick );
+	#else
+		/* Tick service routine used by the scheduler when cooperative scheduling is
+		being used. */
+		setvect( usT2_IRQ, prvNonPreemptiveTick );
+	#endif
+}
+
+
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h
new file mode 100644
index 0000000..ed37545
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h
@@ -0,0 +1,76 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/*
+ * Saves the stack pointer for one task into its TCB, calls
+ * vTaskSwitchContext() to update the TCB being used, then restores the stack
+ * from the new TCB read to run the task.
+ */
+void portSWITCH_CONTEXT( void );
+
+/*
+ * Load the stack pointer from the TCB of the task which is going to be first
+ * to execute.  Then force an IRET so the registers and IP are popped off the
+ * stack.
+ */
+void portFIRST_CONTEXT( void );
+
+#define portSWITCH_CONTEXT()										 \
+						asm { mov	ax, seg pxCurrentTCB		} \
+							asm { mov	ds, ax						}  \
+							asm { les	bx, pxCurrentTCB			}	/* Save the stack pointer into the TCB. */    \
+							asm { mov	es:0x2[ bx ], ss			}   \
+							asm { mov	es:[ bx ], sp				}   \
+							asm { call  far ptr vTaskSwitchContext	}	/* Perform the switch. */   \
+							asm { mov	ax, seg pxCurrentTCB		}	/* Restore the stack pointer from the TCB. */  \
+							asm { mov	ds, ax						}   \
+							asm { les	bx, dword ptr pxCurrentTCB	}   \
+							asm { mov	ss, es:[ bx + 2 ]			}      \
+							asm { mov	sp, es:[ bx ]				}
+
+#define portFIRST_CONTEXT()												\
+							asm { mov	ax, seg pxCurrentTCB		}	\
+							asm { mov	ds, ax						}	\
+							asm { les	bx, dword ptr pxCurrentTCB	}	\
+							asm { mov	ss, es:[ bx + 2 ]			}	\
+							asm { mov	sp, es:[ bx ]				}	\
+							asm { pop	bp							}	\
+							asm { pop	di							}	\
+							asm { pop	si							}	\
+							asm { pop	ds							}	\
+							asm { pop	es							}	\
+							asm { pop	dx							}	\
+							asm { pop	cx							}	\
+							asm { pop	bx							}	\
+							asm { pop	ax							}	\
+							asm { iret								}
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h
new file mode 100644
index 0000000..ffe264e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h
@@ -0,0 +1,106 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		long
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#define portENTER_CRITICAL()			__asm{ pushf }  \
+										__asm{ cli 	 }	\
+
+#define portEXIT_CRITICAL()				__asm{ popf }
+
+#define portDISABLE_INTERRUPTS()		__asm{ cli }
+
+#define portENABLE_INTERRUPTS()			__asm{ sti }
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portNOP()						__asm{ nop }
+#define portSTACK_GROWTH				( -1 )
+#define portSWITCH_INT_NUMBER 			0x80
+#define portYIELD()						__asm{ int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT				2
+#define portINITIAL_SW					( ( portSTACK_TYPE ) 0x0202 )	/* Start the tasks with interrupts enabled. */
+/*-----------------------------------------------------------*/
+
+/* Compiler specifics. */
+#define portINPUT_BYTE( xAddr )				inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )	outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr )				inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue )	outpw( xAddr, usValue )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/port.c
new file mode 100644
index 0000000..c949b8e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/port.c
@@ -0,0 +1,219 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Tern EE 186
+ * port.
+ *----------------------------------------------------------*/
+
+/* Library includes. */
+#include <embedded.h>
+#include <ae.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portasm.h"
+
+/* The timer increments every four clocks, hence the divide by 4. */
+#define portPRESCALE_VALUE ( 16 )
+#define portTIMER_COMPARE ( configCPU_CLOCK_HZ  / ( configTICK_RATE_HZ * 4UL ) )
+
+/* From the RDC data sheet. */
+#define portENABLE_TIMER_AND_INTERRUPT 	( uint16_t ) 0xe00b
+#define portENABLE_TIMER				( uint16_t ) 0xC001
+
+/* Interrupt control. */
+#define portEIO_REGISTER 0xff22
+#define portCLEAR_INTERRUPT 0x0008
+
+/* Setup the hardware to generate the required tick frequency. */
+static void prvSetupTimerInterrupt( void );
+
+/* The ISR used depends on whether the preemptive or cooperative scheduler
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+	/* Tick service routine used by the scheduler when preemptive scheduling is
+	being used. */
+	static void __interrupt __far prvPreemptiveTick( void );
+#else
+	/* Tick service routine used by the scheduler when cooperative scheduling is
+	being used. */
+	static void __interrupt __far prvNonPreemptiveTick( void );
+#endif
+
+/* Trap routine used by taskYIELD() to manually cause a context switch. */
+static void __interrupt __far prvYieldProcessor( void );
+
+/*-----------------------------------------------------------*/
+/* See header file for description. */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t DS_Reg = 0;
+
+	/* We need the true data segment. */
+	__asm{	MOV DS_Reg, DS };
+
+	/* Place a few bytes of known values on the bottom of the stack.
+	This is just useful for debugging. */
+
+	*pxTopOfStack = 0x1111;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2222;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x3333;
+	pxTopOfStack--;
+
+	/* We are going to start the scheduler using a return from interrupt
+	instruction to load the program counter, so first there would be the
+	function call with parameters preamble. */
+	
+	*pxTopOfStack = FP_OFF( pvParameters );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pxCode );
+	pxTopOfStack--;
+
+	/* Next the status register and interrupt return address. */
+	*pxTopOfStack = portINITIAL_SW;
+	pxTopOfStack--;
+	*pxTopOfStack = FP_SEG( pxCode );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pxCode );
+	pxTopOfStack--;
+
+	/* The remaining registers would be pushed on the stack by our context
+	switch function.  These are loaded with values simply to make debugging
+	easier. */
+	*pxTopOfStack = ( StackType_t ) 0xAAAA;	/* AX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xCCCC;	/* CX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xEEEE;	/* ES */
+	pxTopOfStack--;
+
+	*pxTopOfStack = DS_Reg;						/* DS */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0123;	/* SI */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DI */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BP */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* This is called with interrupts already disabled. */
+
+	/* Put our manual switch (yield) function on a known
+	vector. */
+	setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+
+	/* Setup the tick interrupt. */
+	prvSetupTimerInterrupt();
+
+	/* Kick off the scheduler by setting up the context of the first task. */
+	portFIRST_CONTEXT();
+
+	/* Should not get here! */
+	return pdFALSE;
+}
+/*-----------------------------------------------------------*/
+
+/* The ISR used depends on whether the preemptive or cooperative scheduler
+is being used. */
+#if( configUSE_PREEMPTION == 1 )
+	static void __interrupt __far prvPreemptiveTick( void )
+	{
+		/* Get the scheduler to update the task states following the tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Switch in the context of the next task to be run. */
+			portEND_SWITCHING_ISR();
+		}
+
+		/* Reset interrupt. */
+		outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
+	}
+#else
+	static void __interrupt __far prvNonPreemptiveTick( void )
+	{
+		/* Same as preemptive tick, but the cooperative scheduler is being used
+		so we don't have to switch in the context of the next task. */
+		xTaskIncrementTick();
+		
+		/* Reset interrupt. */
+		outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+static void __interrupt __far prvYieldProcessor( void )
+{
+	/* Switch in the context of the next task to be run. */
+	portEND_SWITCHING_ISR();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+const uint32_t ulCompareValue = portTIMER_COMPARE;
+uint16_t usTimerCompare;
+
+	usTimerCompare = ( uint16_t ) ( ulCompareValue >> 4 );
+    t2_init( portENABLE_TIMER, portPRESCALE_VALUE, NULL );
+
+	#if( configUSE_PREEMPTION == 1 )
+		/* Tick service routine used by the scheduler when preemptive scheduling is
+		being used. */
+		t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvPreemptiveTick );
+	#else
+		/* Tick service routine used by the scheduler when cooperative scheduling is
+		being used. */
+		t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvNonPreemptiveTick );
+	#endif
+}
+
+
+
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portasm.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portasm.h
new file mode 100644
index 0000000..521e404
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portasm.h
@@ -0,0 +1,72 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORT_ASM_H
+#define PORT_ASM_H
+
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/*
+ * Saves the stack pointer for one task into its TCB, calls
+ * vTaskSwitchContext() to update the TCB being used, then restores the stack
+ * from the new TCB read to run the task.
+ */
+void portEND_SWITCHING_ISR( void );
+
+/*
+ * Load the stack pointer from the TCB of the task which is going to be first
+ * to execute.  Then force an IRET so the registers and IP are popped off the
+ * stack.
+ */
+void portFIRST_CONTEXT( void );
+
+#define portEND_SWITCHING_ISR()											\
+							asm { mov	bx, [pxCurrentTCB]			}   \
+                            asm { mov	word ptr [bx], sp			}	\
+							asm { call  far ptr vTaskSwitchContext	}	\
+							asm { mov	bx, [pxCurrentTCB]			}	\
+							asm { mov	sp, [bx]					}
+
+#define portFIRST_CONTEXT()											\
+							asm { mov	bx, [pxCurrentTCB]			}	\
+							asm { mov	sp, [bx]					}	\
+							asm { pop	bp							}	\
+							asm { pop	di							}	\
+							asm { pop	si							}	\
+   							asm { pop	ds							}	\
+   							asm { pop	es							}	\
+							asm { pop	dx							}	\
+							asm { pop	cx							}	\
+							asm { pop	bx							}	\
+							asm { pop	ax							}	\
+							asm { iret								}
+
+
+#endif
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portmacro.h
new file mode 100644
index 0000000..dd7265a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portmacro.h
@@ -0,0 +1,107 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		long
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+
+typedef void ( __interrupt __far *pxISR )();
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#define portENTER_CRITICAL()			__asm{ pushf }  \
+										__asm{ cli 	 }	\
+
+#define portEXIT_CRITICAL()				__asm{ popf }
+
+#define portDISABLE_INTERRUPTS()		__asm{ cli }
+
+#define portENABLE_INTERRUPTS()			__asm{ sti }
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portNOP()						__asm{ nop }
+#define portSTACK_GROWTH				( -1 )
+#define portSWITCH_INT_NUMBER 			0x80
+#define portYIELD()						__asm{ int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT				2
+#define portINITIAL_SW					( ( portSTACK_TYPE ) 0x0202 )	/* Start the tasks with interrupts enabled. */
+/*-----------------------------------------------------------*/
+
+/* Compiler specifics. */
+#define portINPUT_BYTE( xAddr )				inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )	outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr )				inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue )	outpw( xAddr, usValue )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/port.c
new file mode 100644
index 0000000..4089326
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/port.c
@@ -0,0 +1,291 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
+#define portNO_CRITICAL_SECTION_NESTING	( ( StackType_t ) 0 )
+
+/* Constants required to setup the tick ISR. */
+#define portENABLE_TIMER			( ( uint8_t ) 0x01 )
+#define portPRESCALE_VALUE			0x00
+#define portINTERRUPT_ON_MATCH		( ( uint32_t ) 0x01 )
+#define portRESET_COUNT_ON_MATCH	( ( uint32_t ) 0x02 )
+
+/* Constants required to setup the VIC for the tick ISR. */
+#define portTIMER_VIC_CHANNEL		( ( uint32_t ) 0x0004 )
+#define portTIMER_VIC_CHANNEL_BIT	( ( uint32_t ) 0x0010 )
+#define portTIMER_VIC_ENABLE		( ( uint32_t ) 0x0020 )
+
+/* Constants required to handle interrupts. */
+#define portTIMER_MATCH_ISR_BIT		( ( uint8_t ) 0x01 )
+#define portCLEAR_VIC_INTERRUPT		( ( uint32_t ) 0 )
+
+/*-----------------------------------------------------------*/
+
+/* The code generated by the Keil compiler does not maintain separate
+stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+use the stack as per other ports.  Instead a variable is used to keep
+track of the critical section nesting.  This variable has to be stored
+as part of the task context and must be initialised to a non zero value. */
+
+#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/*-----------------------------------------------------------*/
+
+/* Setup the timer to generate the tick interrupts. */
+static void prvSetupTimerInterrupt( void );
+
+/* 
+ * The scheduler can only be started from ARM mode, so 
+ * vPortStartFirstSTask() is defined in portISR.c. 
+ */
+extern __asm void vPortStartFirstTask( void );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t *pxOriginalTOS;
+
+	/* Setup the initial stack of the task.  The stack is set exactly as 
+	expected by the portRESTORE_CONTEXT() macro.
+
+	Remember where the top of the (simulated) stack is before we place 
+	anything on it. */
+	pxOriginalTOS = pxTopOfStack;
+	
+	/* To ensure asserts in tasks.c don't fail, although in this case the assert
+	is not really required. */
+	pxTopOfStack--;
+
+	/* First on the stack is the return address - which in this case is the
+	start of the task.  The offset is added to make the return address appear
+	as it would within an IRQ ISR. */
+	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
+	pxTopOfStack--;
+
+	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The last thing onto the stack is the status register, which is set for
+	system mode, with interrupts enabled. */
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
+	{
+		/* We want the task to start in thumb mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* The code generated by the Keil compiler does not maintain separate
+	stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+	use the stack as per other ports.  Instead a variable is used to keep
+	track of the critical section nesting.  This variable has to be stored
+	as part of the task context and is initially set to zero. */
+	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Start the timer that generates the tick ISR. */
+	prvSetupTimerInterrupt();
+
+	/* Start the first task.  This is done from portISR.c as ARM mode must be
+	used. */
+	vPortStartFirstTask();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ARM port will require this function as there
+	is nothing to return to.  If this is required - stop the tick ISR then
+	return back to main. */
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 0
+
+	/* 
+	 * The cooperative scheduler requires a normal IRQ service routine to 
+	 * simply increment the system tick. 
+	 */
+	void vNonPreemptiveTick( void ) __irq;
+	void vNonPreemptiveTick( void ) __irq
+	{
+		/* Increment the tick count - this may make a delaying task ready
+		to run - but a context switch is not performed. */		
+		xTaskIncrementTick();
+
+		T0IR = portTIMER_MATCH_ISR_BIT;				/* Clear the timer event */
+		VICVectAddr = portCLEAR_VIC_INTERRUPT;		/* Acknowledge the Interrupt */
+	}
+
+ #else
+
+	/*
+	 **************************************************************************
+	 * The preemptive scheduler ISR is written in assembler and can be found   
+	 * in the portASM.s file. This will only get used if portUSE_PREEMPTION
+	 * is set to 1 in portmacro.h
+	 ************************************************************************** 
+	 */
+
+	  void vPreemptiveTick( void );
+
+#endif
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+
+	/* A 1ms tick does not require the use of the timer prescale.  This is
+	defaulted to zero but can be used if necessary. */
+	T0PR = portPRESCALE_VALUE;
+
+	/* Calculate the match value required for our wanted tick rate. */
+	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+	/* Protect against divide by zero.  Using an if() statement still results
+	in a warning - hence the #if. */
+	#if portPRESCALE_VALUE != 0
+	{
+		ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
+	}
+	#endif
+
+	T0MR0 = ulCompareMatch;
+
+	/* Generate tick with timer 0 compare match. */
+	T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
+
+	/* Setup the VIC for the timer. */
+	VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
+	VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
+	
+	/* The ISR installed depends on whether the preemptive or cooperative
+	scheduler is being used. */
+	#if configUSE_PREEMPTION == 1
+	{	
+		VICVectAddr0 = ( uint32_t ) vPreemptiveTick;
+	}
+	#else
+	{
+		VICVectAddr0 = ( uint32_t ) vNonPreemptiveTick;
+	}
+	#endif
+
+	VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
+
+	/* Start the timer - interrupts are disabled when this function is called
+	so it is okay to do this here. */
+	T0TCR = portENABLE_TIMER;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
+	__disable_irq();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed 
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as we are leaving a critical section. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then interrupts should be
+		re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Enable interrupts as per portEXIT_CRITICAL(). */
+			__enable_irq();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portASM.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portASM.s
new file mode 100644
index 0000000..92967e0
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portASM.s
@@ -0,0 +1,124 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	INCLUDE portmacro.inc
+
+	IMPORT	vTaskSwitchContext
+	IMPORT	xTaskIncrementTick
+
+	EXPORT	vPortYieldProcessor
+	EXPORT	vPortStartFirstTask
+	EXPORT	vPreemptiveTick
+	EXPORT	vPortYield
+
+
+VICVECTADDR	EQU	0xFFFFF030
+T0IR		EQU	0xE0004000
+T0MATCHBIT	EQU	0x00000001
+
+	ARM
+	AREA	PORT_ASM, CODE, READONLY
+
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Starting the first task is done by just restoring the context
+; setup by pxPortInitialiseStack
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortStartFirstTask
+
+	PRESERVE8
+
+	portRESTORE_CONTEXT
+
+vPortYield
+
+	PRESERVE8
+
+	SVC 0
+	bx lr
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Interrupt service routine for the SWI interrupt.  The vector table is
+; configured in the startup.s file.
+;
+; vPortYieldProcessor() is used to manually force a context switch.  The
+; SWI interrupt is generated by a call to taskYIELD() or portYIELD().
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+vPortYieldProcessor
+
+	PRESERVE8
+
+	; Within an IRQ ISR the link register has an offset from the true return
+	; address, but an SWI ISR does not.  Add the offset manually so the same
+	; ISR return code can be used in both cases.
+	ADD	LR, LR, #4
+
+	; Perform the context switch.
+	portSAVE_CONTEXT					; Save current task context
+	LDR R0, =vTaskSwitchContext			; Get the address of the context switch function
+	MOV LR, PC							; Store the return address
+	BX	R0								; Call the contedxt switch function
+	portRESTORE_CONTEXT					; restore the context of the selected task
+
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; Interrupt service routine for preemptive scheduler tick timer
+; Only used if portUSE_PREEMPTION is set to 1 in portmacro.h
+;
+; Uses timer 0 of LPC21XX Family
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+
+vPreemptiveTick
+
+	PRESERVE8
+
+	portSAVE_CONTEXT					; Save the context of the current task.
+
+	LDR R0, =xTaskIncrementTick			; Increment the tick count.
+	MOV LR, PC							; This may make a delayed task ready
+	BX R0								; to run.
+
+	CMP R0, #0
+	BEQ SkipContextSwitch
+	LDR R0, =vTaskSwitchContext			; Find the highest priority task that
+	MOV LR, PC							; is ready to run.
+	BX R0
+SkipContextSwitch
+	MOV R0, #T0MATCHBIT					; Clear the timer event
+	LDR R1, =T0IR
+	STR R0, [R1]
+
+	LDR	R0, =VICVECTADDR				; Acknowledge the interrupt
+	STR	R0,[R0]
+
+	portRESTORE_CONTEXT					; Restore the context of the highest
+										; priority task that is ready to run.
+	END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.h
new file mode 100644
index 0000000..6c67230
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*-----------------------------------------------------------
+ * ISR entry and exit macros.  These are only required if a task switch
+ * is required from an ISR.
+ *----------------------------------------------------------*/
+
+/* If a switch is required then we just need to call */
+/* vTaskSwitchContext() as the context has already been */
+/* saved. */
+
+#define portEXIT_SWITCHING_ISR(SwitchRequired)				 \
+{															 \
+extern void vTaskSwitchContext(void);						 \
+															 \
+		if(SwitchRequired)									 \
+		{													 \
+			vTaskSwitchContext();							 \
+		}													 \
+}															 \
+
+extern void vPortYield( void );
+#define portYIELD() vPortYield()
+
+
+/* Critical section management. */
+
+/*
+ ******************************************************************
+ * We don't need to worry about whether we're in ARM or
+ * THUMB mode with the Keil Real View compiler when enabling
+ * or disabling interrupts as the compiler's intrinsic functions
+ * take care of that for us.
+ *******************************************************************
+ */
+#define portDISABLE_INTERRUPTS()	__disable_irq()
+#define portENABLE_INTERRUPTS()		__enable_irq()
+
+
+/*-----------------------------------------------------------
+ * Critical section control
+ *
+ * The code generated by the Keil compiler does not maintain separate
+ * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
+ * use the stack as per other ports.  Instead a variable is used to keep
+ * track of the critical section nesting.  This necessitates the use of a
+ * function in place of the macro.
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+/*-----------------------------------------------------------*/
+
+/* Compiler specifics. */
+#define inline
+#define register
+#define portNOP()	__asm{ NOP }
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.inc b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.inc
new file mode 100644
index 0000000..ffdfab0
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.inc
@@ -0,0 +1,91 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	IMPORT  ulCriticalNesting		;
+	IMPORT	pxCurrentTCB			;
+
+
+	MACRO
+	portRESTORE_CONTEXT
+
+
+	LDR		R0, =pxCurrentTCB		; Set the LR to the task stack.  The location was...
+	LDR		R0, [R0]				; ... stored in pxCurrentTCB
+	LDR		LR, [R0]
+
+	LDR		R0, =ulCriticalNesting	; The critical nesting depth is the first item on...
+	LDMFD	LR!, {R1}				; ...the stack.  Load it into the ulCriticalNesting var.
+	STR		R1, [R0]				;
+
+	LDMFD	LR!, {R0}				; Get the SPSR from the stack.
+	MSR		SPSR_cxsf, R0			;
+
+	LDMFD	LR, {R0-R14}^			; Restore all system mode registers for the task.
+	NOP								;
+
+	LDR		LR, [LR, #+60]			; Restore the return address
+
+									; And return - correcting the offset in the LR to obtain ...
+	SUBS	PC, LR, #4				; ...the correct address.
+
+	MEND
+
+; /**********************************************************************/
+
+	MACRO
+	portSAVE_CONTEXT
+
+
+	STMDB 	SP!, {R0}				; Store R0 first as we need to use it.
+
+	STMDB	SP,{SP}^				; Set R0 to point to the task stack pointer.
+	NOP								;
+	SUB		SP, SP, #4				;
+	LDMIA	SP!,{R0}				;
+
+	STMDB	R0!, {LR}				; Push the return address onto the stack.
+	MOV		LR, R0					; Now we have saved LR we can use it instead of R0.
+	LDMIA	SP!, {R0}				; Pop R0 so we can save it onto the system mode stack.
+
+	STMDB	LR,{R0-LR}^				; Push all the system mode registers onto the task stack.
+	NOP								;
+	SUB		LR, LR, #60				;
+
+	MRS		R0, SPSR				; Push the SPSR onto the task stack.
+	STMDB	LR!, {R0}				;
+
+	LDR		R0, =ulCriticalNesting	;
+	LDR		R0, [R0]				;
+	STMDB	LR!, {R0}				;
+
+	LDR		R0, =pxCurrentTCB		; Store the new top of stack for the task.
+	LDR		R1, [R0]				;
+	STR		LR, [R1]				;
+
+	MEND
+
+	END
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CA9/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CA9/port.c
new file mode 100644
index 0000000..9219e81
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CA9/port.c
@@ -0,0 +1,480 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
+	#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
+	#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configUNIQUE_INTERRUPT_PRIORITIES
+	#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#ifndef configSETUP_TICK_INTERRUPT
+	#error configSETUP_TICK_INTERRUPT() must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif /* configSETUP_TICK_INTERRUPT */
+
+#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See https://www.FreeRTOS.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
+#endif
+
+#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/* In case security extensions are implemented. */
+#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
+#endif
+
+#ifndef configCLEAR_TICK_INTERRUPT
+	#define configCLEAR_TICK_INTERRUPT()
+#endif
+
+/* The number of bits to shift for an interrupt priority is dependent on the
+number of bits implemented by the interrupt controller. */
+#if configUNIQUE_INTERRUPT_PRIORITIES == 16
+	#define portPRIORITY_SHIFT 4
+	#define portMAX_BINARY_POINT_VALUE	3
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
+	#define portPRIORITY_SHIFT 3
+	#define portMAX_BINARY_POINT_VALUE	2
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
+	#define portPRIORITY_SHIFT 2
+	#define portMAX_BINARY_POINT_VALUE	1
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
+	#define portPRIORITY_SHIFT 1
+	#define portMAX_BINARY_POINT_VALUE	0
+#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
+	#define portPRIORITY_SHIFT 0
+	#define portMAX_BINARY_POINT_VALUE	0
+#else
+	#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
+#endif
+
+/* A critical section is exited when the critical section nesting count reaches
+this value. */
+#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
+
+/* In all GICs 255 can be written to the priority mask register to unmask all
+(but the lowest) interrupt priority. */
+#define portUNMASK_VALUE				( 0xFFUL )
+
+/* Tasks are not created with a floating point context, but can be given a
+floating point context after they have been created.  A variable is stored as
+part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
+does not have an FPU context, or any other value if the task does have an FPU
+context. */
+#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
+
+/* Interrupt controller access addresses. */
+#define portICCPMR_PRIORITY_MASK_OFFSET  		( 0x04 )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
+#define portICCEOIR_END_OF_INTERRUPT_OFFSET 	( 0x10 )
+#define portICCBPR_BINARY_POINT_OFFSET			( 0x08 )
+#define portICCRPR_RUNNING_PRIORITY_OFFSET		( 0x14 )
+#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS 		( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER 					( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
+#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS 	( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
+#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS 		( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
+#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS 			( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
+#define portICCBPR_BINARY_POINT_REGISTER 					( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
+#define portICCRPR_RUNNING_PRIORITY_REGISTER 				( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
+
+/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
+point is zero. */
+#define portBINARY_POINT_BITS			( ( uint8_t ) 0x03 )
+
+/* Constants required to setup the initial task context. */
+#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
+#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
+#define portTHUMB_MODE_ADDRESS			( 0x01UL )
+
+/* Masks all bits in the APSR other than the mode bits. */
+#define portAPSR_MODE_BITS_MASK			( 0x1F )
+
+/* The value of the mode bits in the APSR when the CPU is executing in user
+mode. */
+#define portAPSR_USER_MODE				( 0x10 )
+
+/* Macro to unmask all interrupt priorities. */
+#define portCLEAR_INTERRUPT_MASK()											\
+{																			\
+	__disable_irq();														\
+	portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;					\
+	__asm(	"DSB		\n"													\
+			"ISB		\n" );												\
+	__enable_irq();															\
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Starts the first task executing.  This function is necessarily written in
+ * assembly code so is implemented in portASM.s.
+ */
+extern void vPortRestoreTaskContext( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* A variable is used to keep track of the critical section nesting.  This
+variable has to be stored as part of the task context and must be initialised to
+a non zero value to ensure interrupts don't inadvertently become unmasked before
+the scheduler starts.  As it is stored as part of the task context it will
+automatically be set to 0 when the first task is started. */
+volatile uint32_t ulCriticalNesting = 9999UL;
+
+/* Used to pass constants into the ASM code.  The address at which variables are
+placed is the constant value so indirect loads in the asm code are not
+required. */
+uint32_t ulICCIAR __attribute__( ( at( portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ) ) );
+uint32_t ulICCEOIR __attribute__( ( at( portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ) ) );
+uint32_t ulICCPMR __attribute__( ( at( portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ) ) );
+uint32_t ulAsmAPIPriorityMask __attribute__( ( at( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) );
+
+/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
+a floating point context must be saved and restored for the task. */
+uint32_t ulPortTaskHasFPUContext = pdFALSE;
+
+/* Set to 1 to pend a context switch from an ISR. */
+uint32_t ulPortYieldRequired = pdFALSE;
+
+/* Counts the interrupt nesting depth.  A context switch is only performed if
+if the nesting depth is 0. */
+uint32_t ulPortInterruptNesting = 0UL;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Setup the initial stack of the task.  The stack is set exactly as
+	expected by the portRESTORE_CONTEXT() macro.
+
+	The fist real value on the stack is the status register, which is set for
+	system mode, with interrupts enabled.  A few NULLs are added first to ensure
+	GDB does not try decoding a non-existent return address. */
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = NULL;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
+
+	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
+	{
+		/* The task will start in THUMB mode. */
+		*pxTopOfStack |= portTHUMB_MODE_BIT;
+	}
+
+	pxTopOfStack--;
+
+	/* Next the return address, which in this case is the start of the task. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+
+	/* Next all the registers other than the stack pointer. */
+	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+	pxTopOfStack--;
+
+	/* The task will start with a critical nesting count of 0 as interrupts are
+	enabled. */
+	*pxTopOfStack = portNO_CRITICAL_NESTING;
+	pxTopOfStack--;
+
+	/* The task will start without a floating point context.  A task that uses
+	the floating point hardware must call vPortTaskUsesFPU() before executing
+	any floating point instructions. */
+	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( ulPortInterruptNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+uint32_t ulAPSR;
+
+	/* Only continue if the CPU is not in User mode.  The CPU must be in a
+	Privileged mode for the scheduler to start. */
+	__asm( "MRS ulAPSR, APSR" );
+	ulAPSR &= portAPSR_MODE_BITS_MASK;
+	configASSERT( ulAPSR != portAPSR_USER_MODE );
+
+	if( ulAPSR != portAPSR_USER_MODE )
+	{
+		/* Only continue if the binary point value is set to its lowest possible
+		setting.  See the comments in vPortValidateInterruptPriority() below for
+		more information. */
+		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
+
+		if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
+		{
+			/* Start the timer that generates the tick ISR. */
+			configSETUP_TICK_INTERRUPT();
+
+			__enable_irq();
+			vPortRestoreTaskContext();
+		}
+	}
+
+	/* Will only get here if vTaskStartScheduler() was called with the CPU in
+	a non-privileged mode or the binary point register was not set to its lowest
+	possible value. */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 	*/
+	ulPortSetInterruptMask();
+
+	/* Now interrupts are disabled ulCriticalNesting can be accessed
+	directly.  Increment ulCriticalNesting to keep a count of how many times
+	portENTER_CRITICAL() has been called. */
+	ulCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( ulCriticalNesting == 1 )
+	{
+		configASSERT( ulPortInterruptNesting == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
+	{
+		/* Decrement the nesting count as the critical section is being
+		exited. */
+		ulCriticalNesting--;
+
+		/* If the nesting level has reached zero then all interrupt
+		priorities must be re-enabled. */
+		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
+		{
+			/* Critical nesting has reached zero so all interrupt priorities
+			should be unmasked. */
+			portCLEAR_INTERRUPT_MASK();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+void FreeRTOS_Tick_Handler( void )
+{
+	/* Set interrupt mask before altering scheduler structures.   The tick
+	handler runs at the lowest priority, so interrupts cannot already be masked,
+	so there is no need to save and restore the current mask value. */
+	__disable_irq();
+	portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+	__asm(	"DSB		\n"
+			"ISB		\n" );
+	__enable_irq();
+
+	/* Increment the RTOS tick. */
+	if( xTaskIncrementTick() != pdFALSE )
+	{
+		ulPortYieldRequired = pdTRUE;
+	}
+
+	/* Ensure all interrupt priorities are active again. */
+	portCLEAR_INTERRUPT_MASK();
+	configCLEAR_TICK_INTERRUPT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortTaskUsesFPU( void )
+{
+uint32_t ulInitialFPSCR = 0;
+
+	/* A task is registering the fact that it needs an FPU context.  Set the
+	FPU flag (which is saved as part of the task context). */
+	ulPortTaskHasFPUContext = pdTRUE;
+
+	/* Initialise the floating point status register. */
+	__asm( "FMXR 	FPSCR, ulInitialFPSCR" );
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( uint32_t ulNewMaskValue )
+{
+	if( ulNewMaskValue == pdFALSE )
+	{
+		portCLEAR_INTERRUPT_MASK();
+	}
+}
+/*-----------------------------------------------------------*/
+
+uint32_t ulPortSetInterruptMask( void )
+{
+uint32_t ulReturn;
+
+	__disable_irq();
+	if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
+	{
+		/* Interrupts were already masked. */
+		ulReturn = pdTRUE;
+	}
+	else
+	{
+		ulReturn = pdFALSE;
+		portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
+		__asm(	"DSB		\n"
+				"ISB		\n" );
+	}
+	__enable_irq();
+
+	return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+		/* The following assertion will fail if a service routine (ISR) for
+		an interrupt that has been assigned a priority above
+		configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+		function.  ISR safe FreeRTOS API functions must *only* be called
+		from interrupts that have been assigned a priority at or below
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		Numerically low interrupt priority numbers represent logically high
+		interrupt priorities, therefore the priority of the interrupt must
+		be set to a value equal to or numerically *higher* than
+		configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+		FreeRTOS maintains separate thread and ISR API functions to ensure
+		interrupt entry is as fast and simple as possible.
+
+		The following links provide detailed information:
+		https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+		https://www.FreeRTOS.org/FAQHelp.html */
+		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
+
+		/* Priority grouping:  The interrupt controller (GIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		The priority grouping is configured by the GIC's binary point register
+		(ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
+		possible value (which may be above 0). */
+		configASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CA9/portASM.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CA9/portASM.s
new file mode 100644
index 0000000..dfde98a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CA9/portASM.s
@@ -0,0 +1,174 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	INCLUDE portmacro.inc
+
+	IMPORT	vApplicationIRQHandler
+	IMPORT	vTaskSwitchContext
+	IMPORT	ulPortYieldRequired
+	IMPORT	ulPortInterruptNesting
+	IMPORT	vTaskSwitchContext
+	IMPORT	ulICCIAR
+	IMPORT	ulICCEOIR
+
+	EXPORT	FreeRTOS_SWI_Handler
+	EXPORT  FreeRTOS_IRQ_Handler
+	EXPORT 	vPortRestoreTaskContext
+
+	ARM
+	AREA	PORT_ASM, CODE, READONLY
+
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; SVC handler is used to yield a task.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+FreeRTOS_SWI_Handler
+
+	PRESERVE8
+
+	; Save the context of the current task and select a new task to run.
+	portSAVE_CONTEXT
+	LDR R0, =vTaskSwitchContext
+	BLX	R0
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; vPortRestoreTaskContext is used to start the scheduler.
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+vPortRestoreTaskContext
+	; Switch to system mode
+	CPS		#SYS_MODE
+	portRESTORE_CONTEXT
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+; PL390 GIC interrupt handler
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+FreeRTOS_IRQ_Handler
+
+	; Return to the interrupted instruction.
+	SUB		lr, lr, #4
+
+	; Push the return address and SPSR
+	PUSH	{lr}
+	MRS		lr, SPSR
+	PUSH	{lr}
+
+	; Change to supervisor mode to allow reentry.
+	CPS		#SVC_MODE
+
+	; Push used registers.
+	PUSH	{r0-r4, r12}
+
+	; Increment nesting count.  r3 holds the address of ulPortInterruptNesting
+	; for future use.  r1 holds the original ulPortInterruptNesting value for
+	; future use.
+	LDR		r3, =ulPortInterruptNesting
+	LDR		r1, [r3]
+	ADD		r4, r1, #1
+	STR		r4, [r3]
+
+	; Read value from the interrupt acknowledge register, which is stored in r0
+	; for future parameter and interrupt clearing use.
+	LDR 	r2, =ulICCIAR
+	LDR		r0, [r2]
+
+	; Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
+	; future use.  _RB_ Does this ever actually need to be done provided the
+	; start of the stack is 8-byte aligned?
+	MOV		r2, sp
+	AND		r2, r2, #4
+	SUB		sp, sp, r2
+
+	; Call the interrupt handler.  r4 is pushed to maintain alignment.
+	PUSH	{r0-r4, lr}
+	LDR		r1, =vApplicationIRQHandler
+	BLX		r1
+	POP		{r0-r4, lr}
+	ADD		sp, sp, r2
+
+	CPSID 	i
+
+	; Write the value read from ICCIAR to ICCEOIR
+	LDR 	r4, =ulICCEOIR
+	STR		r0, [r4]
+
+	; Restore the old nesting count
+	STR		r1, [r3]
+
+	; A context switch is never performed if the nesting count is not 0
+	CMP		r1, #0
+	BNE		exit_without_switch
+
+	; Did the interrupt request a context switch?  r1 holds the address of
+	; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
+	; use.
+	LDR		r1, =ulPortYieldRequired
+	LDR		r0, [r1]
+	CMP		r0, #0
+	BNE		switch_before_exit
+
+exit_without_switch
+	; No context switch.  Restore used registers, LR_irq and SPSR before
+	; returning.
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	MOVS	PC, LR
+
+switch_before_exit
+	; A context swtich is to be performed.  Clear the context switch pending
+	; flag.
+	MOV		r0, #0
+	STR		r0, [r1]
+
+	; Restore used registers, LR-irq and SPSR before saving the context
+	; to the task stack.
+	POP		{r0-r4, r12}
+	CPS		#IRQ_MODE
+	POP		{LR}
+	MSR		SPSR_cxsf, LR
+	POP		{LR}
+	portSAVE_CONTEXT
+
+	; Call the function that selects the new task to execute.
+	; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
+	; instructions, or 8 byte aligned stack allocated data.  LR does not need
+	; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
+	LDR		r0, =vTaskSwitchContext
+	BLX		r0
+
+	; Restore the context of, and branch to, the task selected to execute next.
+	portRESTORE_CONTEXT
+
+
+	END
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.h
new file mode 100644
index 0000000..38a9778
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.h
@@ -0,0 +1,162 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the given hardware
+ * and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/* Called at the end of an ISR that can cause a context switch. */
+#define portEND_SWITCHING_ISR( xSwitchRequired )\
+{												\
+extern uint32_t ulPortYieldRequired;			\
+												\
+	if( xSwitchRequired != pdFALSE )			\
+	{											\
+		ulPortYieldRequired = pdTRUE;			\
+	}											\
+}
+
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+#define portYIELD() __asm( "SWI 0" );
+
+
+/*-----------------------------------------------------------
+ * Critical section control
+ *----------------------------------------------------------*/
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern uint32_t ulPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
+
+/* These macros do not globally disable/enable interrupts.  They do mask off
+interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
+#define portENTER_CRITICAL()		vPortEnterCritical();
+#define portEXIT_CRITICAL()			vPortExitCritical();
+#define portDISABLE_INTERRUPTS()	ulPortSetInterruptMask()
+#define portENABLE_INTERRUPTS()		vPortClearInterruptMask( 0 )
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask(x)
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not required for this port but included in case common demo code that uses these
+macros is used. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
+
+/* Prototype of the FreeRTOS tick handler.  This must be installed as the
+handler for whichever peripheral is used to generate the RTOS tick. */
+void FreeRTOS_Tick_Handler( void );
+
+/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
+before any floating point instructions are executed. */
+void vPortTaskUsesFPU( void );
+#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
+
+#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
+#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( uxReadyPriorities ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+#define portNOP() __nop()
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.inc b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.inc
new file mode 100644
index 0000000..cf2557f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.inc
@@ -0,0 +1,120 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+SYS_MODE			EQU		0x1f
+SVC_MODE			EQU		0x13
+IRQ_MODE			EQU		0x12
+
+	IMPORT  ulCriticalNesting
+	IMPORT	pxCurrentTCB
+	IMPORT	ulPortTaskHasFPUContext
+	IMPORT  ulAsmAPIPriorityMask
+	IMPORT	ulICCPMR
+
+
+	MACRO
+	portSAVE_CONTEXT
+
+	; Save the LR and SPSR onto the system mode stack before switching to
+	; system mode to save the remaining system mode registers
+	SRSDB	sp!, #SYS_MODE
+	CPS		#SYS_MODE
+	PUSH	{R0-R12, R14}
+
+	; Push the critical nesting count
+	LDR		R2, =ulCriticalNesting
+	LDR		R1, [R2]
+	PUSH	{R1}
+
+	; Does the task have a floating point context that needs saving?  If
+	; ulPortTaskHasFPUContext is 0 then no.
+	LDR		R2, =ulPortTaskHasFPUContext
+	LDR		R3, [R2]
+	CMP		R3, #0
+
+	; Save the floating point context, if any
+	FMRXNE  R1,  FPSCR
+	VPUSHNE {D0-D15}
+	VPUSHNE	{D16-D31}
+	PUSHNE	{R1}
+
+	; Save ulPortTaskHasFPUContext itself
+	PUSH	{R3}
+
+	; Save the stack pointer in the TCB
+	LDR		R0, =pxCurrentTCB
+	LDR		R1, [R0]
+	STR		SP, [R1]
+
+	MEND
+
+; /**********************************************************************/
+
+	MACRO
+	portRESTORE_CONTEXT
+
+	; Set the SP to point to the stack of the task being restored.
+	LDR		R0, =pxCurrentTCB
+	LDR		R1, [R0]
+	LDR		SP, [R1]
+
+	; Is there a floating point context to restore?  If the restored
+	; ulPortTaskHasFPUContext is zero then no.
+	LDR		R0, =ulPortTaskHasFPUContext
+	POP		{R1}
+	STR		R1, [R0]
+	CMP		R1, #0
+
+	; Restore the floating point context, if any
+	POPNE	{R0}
+	VPOPNE	{D16-D31}
+	VPOPNE	{D0-D15}
+	VMSRNE  FPSCR, R0
+
+	; Restore the critical section nesting depth
+	LDR		R0, =ulCriticalNesting
+	POP		{R1}
+	STR		R1, [R0]
+
+	; Ensure the priority mask is correct for the critical nesting depth
+	LDR		R2, =ulICCPMR
+	CMP		R1, #0
+	MOVEQ	R4, #255
+	LDRNE	R4, =ulAsmAPIPriorityMask
+	STR		R4, [r2]
+
+	; Restore all system mode registers other than the SP (which is already
+	; being used)
+	POP		{R0-R12, R14}
+
+	; Return to the task code, loading CPSR on the way.
+	RFEIA	sp!
+
+	MEND
+
+	END
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM0/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM0/port.c
new file mode 100644
index 0000000..c4a4d36
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM0/port.c
@@ -0,0 +1,547 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM0 port.
+*----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_INT_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SYSTICK_CLK_BIT              ( 1UL << 2UL )
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portNVIC_PENDSVSET_BIT                ( 1UL << 28UL )
+#define portMIN_INTERRUPT_PRIORITY            ( 255UL )
+#define portNVIC_PENDSV_PRI                   ( portMIN_INTERRUPT_PRIORITY << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( portMIN_INTERRUPT_PRIORITY << 24UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                      ( 0x01000000 )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#ifndef portMISSED_COUNTS_FACTOR
+    #define portMISSED_COUNTS_FACTOR    ( 45UL )
+#endif
+
+/* Constants used with memory barrier intrinsics. */
+#define portSY_FULL_READ_WRITE    ( 15 )
+
+/* Legacy macro for backward compatibility only.  This macro used to be used to
+ * replace the function that configures the clock used to generate the tick
+ * interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so
+ * the application writer can override it by simply defining a function of the
+ * same name (vApplicationSetupTickInterrupt()). */
+#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+    #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION    0
+#endif
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/* The number of SysTick increments that make up one tick period. */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/* The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer. */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/* Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    pxTopOfStack--;                                   /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+    *pxTopOfStack = portINITIAL_XPSR;                 /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) pxCode;           /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) prvTaskExitError; /* LR */
+    pxTopOfStack -= 5;                                /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters;     /* R0 */
+    pxTopOfStack -= 8;                                /* R11..R4. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( uxCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    for( ; ; )
+    {
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortSVCHandler( void )
+{
+    /* This function is no longer used, but retained for backward
+     * compatibility. */
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvPortStartFirstTask( void )
+{
+    extern pxCurrentTCB;
+
+    PRESERVE8
+
+    /* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
+     * table offset register that can be used to locate the initial stack value.
+     * Not all M0 parts have the application vector table at address 0. */
+/* *INDENT-OFF* */
+
+    ldr r3, = pxCurrentTCB /* Obtain location of pxCurrentTCB. */
+    ldr r1, [ r3 ]
+    ldr r0, [ r1 ]         /* The first item in pxCurrentTCB is the task top of stack. */
+    adds r0, # 32          /* Discard everything up to r0. */
+    msr psp, r0            /* This is now the new top of stack to use in the task. */
+    movs r0, # 2           /* Switch to the psp stack. */
+    msr CONTROL, r0
+    isb
+    pop { r0 - r5 } /* Pop the registers that are saved automatically. */
+    mov lr, r5 /* lr is now in r5. */
+    pop { r3 } /* The return address is now in r3. */
+    pop { r2 } /* Pop and discard the XPSR. */
+    cpsie i /* The first task has its context and interrupts can be enabled. */
+    bx r3 /* Finally, jump to the user defined task code. */
+
+    ALIGN
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    /* Make PendSV, CallSV and SysTick the same priority as the kernel. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Start the first task. */
+    prvPortStartFirstTask();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortYield( void )
+{
+    /* Set a PendSV to request a context switch. */
+    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+    /* Barriers are normally not required but do ensure the code is completely
+     * within the specified behaviour for the architecture. */
+    __dsb( portSY_FULL_READ_WRITE );
+    __isb( portSY_FULL_READ_WRITE );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+    __dsb( portSY_FULL_READ_WRITE );
+    __isb( portSY_FULL_READ_WRITE );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+__asm uint32_t ulSetInterruptMaskFromISR( void )
+{
+/* *INDENT-OFF* */
+    mrs r0, PRIMASK
+    cpsid i
+    bx lr
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+__asm void vClearInterruptMaskFromISR( uint32_t ulMask )
+{
+/* *INDENT-OFF* */
+    msr PRIMASK, r0
+    bx lr
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+__asm void xPortPendSVHandler( void )
+{
+    extern vTaskSwitchContext
+    extern pxCurrentTCB
+
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    mrs r0, psp
+
+    ldr r3, = pxCurrentTCB /* Get the location of the current TCB. */
+    ldr r2, [ r3 ]
+
+    subs r0, # 32  /* Make space for the remaining low registers. */
+    str r0, [ r2 ] /* Save the new top of stack. */
+    stmia r0 !, { r4 - r7 } /* Store the low registers that are not saved automatically. */
+    mov r4, r8 /* Store the high registers. */
+    mov r5, r9
+    mov r6, r10
+    mov r7, r11
+    stmia r0 !, { r4 - r7 }
+
+    push { r3, r14 }
+    cpsid i
+    bl vTaskSwitchContext
+    cpsie i
+    pop { r2, r3 } /* lr goes in r3. r2 now holds tcb pointer. */
+
+    ldr r1, [ r2 ]
+    ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */
+    adds r0, # 16  /* Move to the high registers. */
+    ldmia r0 !, { r4 - r7 } /* Pop the high registers. */
+    mov r8, r4
+    mov r9, r5
+    mov r10, r6
+    mov r11, r7
+
+    msr psp, r0   /* Remember the new top of stack for the task. */
+
+    subs r0, # 32 /* Go back for the low registers that are not automatically restored. */
+    ldmia r0 !, { r4 - r7 } /* Pop low registers.  */
+
+    bx r3
+    ALIGN
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    uint32_t ulPreviousMask;
+
+    ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
+
+    __weak void vPortSetupTimerInterrupt( void )
+    {
+        /* Calculate the constants required to configure the tick interrupt. */
+        #if ( configUSE_TICKLESS_IDLE == 1 )
+            ulTimerCountsForOneTick = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
+            xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+            ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR;
+        #endif /* configUSE_TICKLESS_IDLE */
+
+        /* Stop and reset the SysTick. */
+        portNVIC_SYSTICK_CTRL_REG = 0UL;
+        portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+        /* Configure SysTick to interrupt at the requested rate. */
+        portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+        portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT;
+    }
+
+#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+    __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily. The time the SysTick is stopped for
+         * is accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods.  -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __disable_irq();
+        __dsb( portSY_FULL_READ_WRITE );
+        __isb( portSY_FULL_READ_WRITE );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above __disable_irq() call
+             * above. */
+            __enable_irq();
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens. configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again. However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __dsb( portSY_FULL_READ_WRITE );
+                __wfi();
+                __isb( portSY_FULL_READ_WRITE );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately. see comments above
+             * __disable_interrupt() call above. */
+            __enable_irq();
+            __dsb( portSY_FULL_READ_WRITE );
+            __isb( portSY_FULL_READ_WRITE );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __disable_irq();
+            __dsb( portSY_FULL_READ_WRITE );
+            __isb( portSY_FULL_READ_WRITE );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is yet
+             * to count to zero (in which case an interrupt other than the SysTick
+             * must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD
+             * again, then set portNVIC_SYSTICK_LOAD back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrpts enabled. */
+            __enable_irq();
+        }
+    }
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM0/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM0/portmacro.h
new file mode 100644
index 0000000..a6c88c8
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM0/portmacro.h
@@ -0,0 +1,123 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+    extern void vPortYield( void );
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portYIELD()                                 vPortYield()
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+    extern uint32_t ulSetInterruptMaskFromISR( void );
+    extern void vClearInterruptMaskFromISR( uint32_t ulMask );
+
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulSetInterruptMaskFromISR()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vClearInterruptMaskFromISR( x )
+    #define portDISABLE_INTERRUPTS()                  __disable_irq()
+    #define portENABLE_INTERRUPTS()                   __enable_irq()
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+    #define portNOP()
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
new file mode 100644
index 0000000..014c4b5
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
@@ -0,0 +1,716 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM3 port.
+*----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+    #define configKERNEL_INTERRUPT_PRIORITY    255
+#endif
+
+#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
+    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+
+/* Legacy macro for backward compatibility only.  This macro used to be used to
+ * replace the function that configures the clock used to generate the tick
+ * interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so
+ * the application writer can override it by simply defining a function of the
+ * same name (vApplicationSetupTickInterrupt()). */
+#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+    #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION    0
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
+#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                    ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK                   ( 0xFFUL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                      ( 0x01000000 )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#define portMISSED_COUNTS_FACTOR              ( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    pxTopOfStack--;                                                      /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) prvTaskExitError;                    /* LR */
+
+    pxTopOfStack -= 5;                                                   /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters;                        /* R0 */
+    pxTopOfStack -= 8;                                                   /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( uxCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    for( ; ; )
+    {
+    }
+}
+/*-----------------------------------------------------------*/
+
+__asm void vPortSVCHandler( void )
+{
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    ldr r3, = pxCurrentTCB   /* Restore the context. */
+    ldr r1, [ r3 ] /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+    ldr r0, [ r1 ]           /* The first item in pxCurrentTCB is the task top of stack. */
+    ldmia r0 !, { r4 - r11 } /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+    msr psp, r0 /* Restore the task stack pointer. */
+    isb
+    mov r0, # 0
+    msr basepri, r0
+    orr r14, # 0xd
+    bx r14
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvStartFirstTask( void )
+{
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    /* Use the NVIC offset register to locate the stack. */
+    ldr r0, =0xE000ED08
+    ldr r0, [ r0 ]
+    ldr r0, [ r0 ]
+
+    /* Set the msp back to the start of the stack. */
+    msr msp, r0
+    /* Globally enable interrupts. */
+    cpsie i
+    cpsie f
+    dsb
+    isb
+    /* Call SVC to start the first task. */
+    svc 0
+    nop
+    nop
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+            volatile uint8_t ucMaxPriorityValue;
+
+            /* Determine the maximum priority from which ISR safe FreeRTOS API
+             * functions can be called.  ISR safe functions are those that end in
+             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+             * ensure interrupt entry is as fast and simple as possible.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+            /* Determine the number of priority bits available.  First write to all
+             * possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+            /* The kernel interrupt priority should be set to the lowest
+             * priority. */
+            configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
+
+            /* Use the same mask on the maximum system call priority. */
+            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+            /* Calculate the maximum acceptable priority group value for the number
+             * of bits read back. */
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+            {
+                ulMaxPRIGROUPValue--;
+                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+            }
+
+            #ifdef __NVIC_PRIO_BITS
+                {
+                    /* Check the CMSIS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+                }
+            #endif
+
+            #ifdef configPRIO_BITS
+                {
+                    /* Check the FreeRTOS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+                }
+            #endif
+
+            /* Shift the priority group value back to its position within the AIRCR
+             * register. */
+            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* conifgASSERT_DEFINED */
+
+    /* Make PendSV and SysTick the lowest priority interrupts. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Start the first task. */
+    prvStartFirstTask();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
+    if( uxCriticalNesting == 1 )
+    {
+        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+__asm void xPortPendSVHandler( void )
+{
+    extern uxCriticalNesting;
+    extern pxCurrentTCB;
+    extern vTaskSwitchContext;
+
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    mrs r0, psp
+    isb
+
+    ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
+    ldr r2, [ r3 ]
+
+    stmdb r0 !, { r4 - r11 } /* Save the remaining registers. */
+    str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */
+
+    stmdb sp !, { r3, r14 }
+    mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+    msr basepri, r0
+    dsb
+    isb
+    bl vTaskSwitchContext
+    mov r0, #0
+    msr basepri, r0
+    ldmia sp !, { r3, r14 }
+
+    ldr r1, [ r3 ]
+    ldr r0, [ r1 ] /* The first item in pxCurrentTCB is the task top of stack. */
+    ldmia r0 !, { r4 - r11 } /* Pop the registers and the critical nesting count. */
+    msr psp, r0
+    isb
+    bx r14
+    nop
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+     * executes all interrupts must be unmasked.  There is therefore no need to
+     * save and then restore the interrupt mask value as its value is already
+     * known - therefore the slightly faster vPortRaiseBASEPRI() function is used
+     * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
+    vPortRaiseBASEPRI();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* A context switch is required.  Context switching is performed in
+             * the PendSV interrupt.  Pend the PendSV interrupt. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+
+    vPortClearBASEPRIFromISR();
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+    __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+         * is accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods.  -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __disable_irq();
+        __dsb( portSY_FULL_READ_WRITE );
+        __isb( portSY_FULL_READ_WRITE );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above __disable_irq() call
+             * above. */
+            __enable_irq();
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again.  However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __dsb( portSY_FULL_READ_WRITE );
+                __wfi();
+                __isb( portSY_FULL_READ_WRITE );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately.  see comments above
+             * __disable_interrupt() call above. */
+            __enable_irq();
+            __dsb( portSY_FULL_READ_WRITE );
+            __isb( portSY_FULL_READ_WRITE );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __disable_irq();
+            __dsb( portSY_FULL_READ_WRITE );
+            __isb( portSY_FULL_READ_WRITE );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is yet
+             * to count to zero (in which case an interrupt other than the SysTick
+             * must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __enable_irq();
+        }
+    }
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the SysTick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
+
+    __weak void vPortSetupTimerInterrupt( void )
+    {
+        /* Calculate the constants required to configure the tick interrupt. */
+        #if ( configUSE_TICKLESS_IDLE == 1 )
+            {
+                ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+                xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+                ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+            }
+        #endif /* configUSE_TICKLESS_IDLE */
+
+        /* Stop and clear the SysTick. */
+        portNVIC_SYSTICK_CTRL_REG = 0UL;
+        portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+        /* Configure SysTick to interrupt at the requested rate. */
+        portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+        portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+    }
+
+#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
+/*-----------------------------------------------------------*/
+
+__asm uint32_t vPortGetIPSR( void )
+{
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    mrs r0, ipsr
+    bx r14
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+    void vPortValidateInterruptPriority( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        uint8_t ucCurrentPriority;
+
+        /* Obtain the number of the currently executing interrupt. */
+        ulCurrentInterrupt = vPortGetIPSR();
+
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that	use the FreeRTOS API must not be left at their
+             * default priority of	zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and	therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
+
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredictable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
+
+#endif /* configASSERT_DEFINED */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
new file mode 100644
index 0000000..5b6ba43
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
@@ -0,0 +1,264 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH          ( -1 )
+    #define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT        8
+
+/* Constants used with memory barrier intrinsics. */
+    #define portSY_FULL_READ_WRITE    ( 15 )
+
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+    #define portYIELD()                                 \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+                                                        \
+        /* Barriers are normally not required but do ensure the code is completely \
+         * within the specified behaviour for the architecture. */ \
+        __dsb( portSY_FULL_READ_WRITE );                           \
+        __isb( portSY_FULL_READ_WRITE );                           \
+    }
+/*-----------------------------------------------------------*/
+
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired != pdFALSE ) portYIELD()
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+
+    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
+    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
+
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Port specific optimisations. */
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #endif
+
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
+
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
+
+    #endif /* taskRECORD_READY_PRIORITY */
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
+
+/* portNOP() is not required by this port. */
+    #define portNOP()
+
+    #define portINLINE              __inline
+
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE    __forceinline
+    #endif
+
+/*-----------------------------------------------------------*/
+
+    static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+    {
+        __asm
+        {
+            /* Barrier instructions are not used as this function is only used to
+             * lower the BASEPRI value. */
+/* *INDENT-OFF* */
+            msr basepri, ulBASEPRI
+/* *INDENT-ON* */
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+    {
+        uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+        __asm
+        {
+            /* Set BASEPRI to the max syscall priority to effect a critical
+             * section. */
+/* *INDENT-OFF* */
+            msr basepri, ulNewBASEPRI
+            dsb
+            isb
+/* *INDENT-ON* */
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+    {
+        __asm
+        {
+            /* Set BASEPRI to 0 so no interrupts are masked.  This function is only
+             * used to lower the mask in an interrupt, so memory barriers are not
+             * used. */
+/* *INDENT-OFF* */
+            msr basepri, # 0
+/* *INDENT-ON* */
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+    {
+        uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+        __asm
+        {
+            /* Set BASEPRI to the max syscall priority to effect a critical
+             * section. */
+/* *INDENT-OFF* */
+            mrs ulReturn, basepri
+            msr basepri, ulNewBASEPRI
+            dsb
+            isb
+/* *INDENT-ON* */
+        }
+
+        return ulReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        BaseType_t xReturn;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm
+        {
+/* *INDENT-OFF* */
+            mrs ulCurrentInterrupt, ipsr
+/* *INDENT-ON* */
+        }
+
+        if( ulCurrentInterrupt == 0 )
+        {
+            xReturn = pdFALSE;
+        }
+        else
+        {
+            xReturn = pdTRUE;
+        }
+
+        return xReturn;
+    }
+
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
new file mode 100644
index 0000000..c01589c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
@@ -0,0 +1,808 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM4F port.
+*----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __TARGET_FPU_VFP
+    #error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
+    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+
+/* Legacy macro for backward compatibility only.  This macro used to be used to
+ * replace the function that configures the clock used to generate the tick
+ * interrupt (prvSetupTimerInterrupt()), but now the function is declared weak so
+ * the application writer can override it by simply defining a function of the
+ * same name (vApplicationSetupTickInterrupt()). */
+#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+    #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION    0
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )
+
+/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
+ * r0p1 port. */
+#define portCPUID                             ( *( ( volatile uint32_t * ) 0xE000ed00 ) )
+#define portCORTEX_M7_r0p1_ID                 ( 0x410FC271UL )
+#define portCORTEX_M7_r0p0_ID                 ( 0x410FC270UL )
+
+#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
+#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                    ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK                   ( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR                             ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS              ( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                      ( 0x01000000 )
+#define portINITIAL_EXC_RETURN                ( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#define portMISSED_COUNTS_FACTOR              ( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Functions defined in portasm.s to enable the VFP.
+ */
+static void prvEnableVFP( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+
+    /* Offset added to account for the way the MCU uses the stack on entry/exit
+     * of interrupts, and to ensure alignment. */
+    pxTopOfStack--;
+
+    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) prvTaskExitError;                    /* LR */
+
+    /* Save code space by skipping register initialisation. */
+    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+    /* A save method is being used that requires each task to maintain its
+     * own exec return value. */
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+    pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( uxCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    for( ; ; )
+    {
+    }
+}
+/*-----------------------------------------------------------*/
+
+__asm void vPortSVCHandler( void )
+{
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    /* Get the location of the current TCB. */
+    ldr r3, = pxCurrentTCB
+    ldr r1, [ r3 ]
+    ldr r0, [ r1 ]
+    /* Pop the core registers. */
+    ldmia r0 !, {r4-r11,r14}
+    msr psp, r0
+    isb
+    mov r0, # 0
+    msr basepri, r0
+    bx r14
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvStartFirstTask( void )
+{
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    /* Use the NVIC offset register to locate the stack. */
+    ldr r0, =0xE000ED08
+    ldr r0, [ r0 ]
+    ldr r0, [ r0 ]
+    /* Set the msp back to the start of the stack. */
+    msr msp, r0
+
+    /* Clear the bit that indicates the FPU is in use in case the FPU was used
+     * before the scheduler was started - which would otherwise result in the
+     * unnecessary leaving of space in the SVC stack for lazy saving of FPU
+     * registers. */
+    mov r0, #0
+    msr control, r0
+    /* Globally enable interrupts. */
+    cpsie i
+    cpsie f
+    dsb
+    isb
+    /* Call SVC to start the first task. */
+    svc 0
+    nop
+    nop
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvEnableVFP( void )
+{
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    /* The FPU enable bits are in the CPACR. */
+    ldr.w r0, =0xE000ED88
+    ldr r1, [ r0 ]
+
+    /* Enable CP10 and CP11 coprocessors, then save back. */
+    orr r1, r1, #( 0xf << 20 )
+    str r1, [ r0 ]
+    bx r14
+    nop
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+    /* This port can be used on all revisions of the Cortex-M7 core other than
+     * the r0p1 parts.  r0p1 parts should use the port from the
+     * /source/portable/GCC/ARM_CM7/r0p1 directory. */
+    configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
+    configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
+
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+            volatile uint8_t ucMaxPriorityValue;
+
+            /* Determine the maximum priority from which ISR safe FreeRTOS API
+             * functions can be called.  ISR safe functions are those that end in
+             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+             * ensure interrupt entry is as fast and simple as possible.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+            /* Determine the number of priority bits available.  First write to all
+             * possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+            /* The kernel interrupt priority should be set to the lowest
+             * priority. */
+            configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
+
+            /* Use the same mask on the maximum system call priority. */
+            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+            /* Calculate the maximum acceptable priority group value for the number
+             * of bits read back. */
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+            {
+                ulMaxPRIGROUPValue--;
+                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+            }
+
+            #ifdef __NVIC_PRIO_BITS
+                {
+                    /* Check the CMSIS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+                }
+            #endif
+
+            #ifdef configPRIO_BITS
+                {
+                    /* Check the FreeRTOS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+                }
+            #endif
+
+            /* Shift the priority group value back to its position within the AIRCR
+             * register. */
+            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* conifgASSERT_DEFINED */
+
+    /* Make PendSV and SysTick the lowest priority interrupts. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Ensure the VFP is enabled - it should be anyway. */
+    prvEnableVFP();
+
+    /* Lazy save always. */
+    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+    /* Start the first task. */
+    prvStartFirstTask();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
+    if( uxCriticalNesting == 1 )
+    {
+        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+__asm void xPortPendSVHandler( void )
+{
+    extern uxCriticalNesting;
+    extern pxCurrentTCB;
+    extern vTaskSwitchContext;
+
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    mrs r0, psp
+    isb
+    /* Get the location of the current TCB. */
+    ldr r3, =pxCurrentTCB
+    ldr r2, [ r3 ]
+
+    /* Is the task using the FPU context?  If so, push high vfp registers. */
+    tst r14, #0x10
+    it eq
+    vstmdbeq r0!, {s16-s31}
+
+    /* Save the core registers. */
+    stmdb r0!, {r4-r11, r14}
+
+    /* Save the new top of stack into the first member of the TCB. */
+    str r0, [ r2 ]
+
+    stmdb sp!, {r0, r3}
+    mov r0, # configMAX_SYSCALL_INTERRUPT_PRIORITY
+    msr basepri, r0
+    dsb
+    isb
+    bl vTaskSwitchContext
+    mov r0, # 0
+    msr basepri, r0
+    ldmia sp!, {r0, r3}
+
+    /* The first item in pxCurrentTCB is the task top of stack. */
+    ldr r1, [ r3 ]
+    ldr r0, [ r1 ]
+
+    /* Pop the core registers. */
+    ldmia r0!, {r4-r11, r14}
+
+    /* Is the task using the FPU context?  If so, pop the high vfp registers
+     * too. */
+    tst r14, # 0x10
+    it eq
+    vldmiaeq r0!, {s16-s31}
+
+    msr psp, r0
+    isb
+    #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
+        #if WORKAROUND_PMU_CM001 == 1
+            push { r14 }
+            pop { pc }
+            nop
+        #endif
+    #endif
+
+    bx r14
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+     * executes all interrupts must be unmasked.  There is therefore no need to
+     * save and then restore the interrupt mask value as its value is already
+     * known - therefore the slightly faster vPortRaiseBASEPRI() function is used
+     * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
+    vPortRaiseBASEPRI();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* A context switch is required.  Context switching is performed in
+             * the PendSV interrupt.  Pend the PendSV interrupt. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+
+    vPortClearBASEPRIFromISR();
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+    __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+         * is accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods.  -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __disable_irq();
+        __dsb( portSY_FULL_READ_WRITE );
+        __isb( portSY_FULL_READ_WRITE );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above __disable_irq() call
+             * above. */
+            __enable_irq();
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again.  However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __dsb( portSY_FULL_READ_WRITE );
+                __wfi();
+                __isb( portSY_FULL_READ_WRITE );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately.  see comments above
+             * __disable_interrupt() call above. */
+            __enable_irq();
+            __dsb( portSY_FULL_READ_WRITE );
+            __isb( portSY_FULL_READ_WRITE );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __disable_irq();
+            __dsb( portSY_FULL_READ_WRITE );
+            __isb( portSY_FULL_READ_WRITE );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is yet
+             * to count to zero (in which case an interrupt other than the SysTick
+             * must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __enable_irq();
+        }
+    }
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the SysTick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
+
+    __weak void vPortSetupTimerInterrupt( void )
+    {
+        /* Calculate the constants required to configure the tick interrupt. */
+        #if ( configUSE_TICKLESS_IDLE == 1 )
+            {
+                ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+                xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+                ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+            }
+        #endif /* configUSE_TICKLESS_IDLE */
+
+        /* Stop and clear the SysTick. */
+        portNVIC_SYSTICK_CTRL_REG = 0UL;
+        portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+        /* Configure SysTick to interrupt at the requested rate. */
+        portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+        portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+    }
+
+#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
+/*-----------------------------------------------------------*/
+
+__asm uint32_t vPortGetIPSR( void )
+{
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    mrs r0, ipsr
+    bx r14
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+    void vPortValidateInterruptPriority( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        uint8_t ucCurrentPriority;
+
+        /* Obtain the number of the currently executing interrupt. */
+        ulCurrentInterrupt = vPortGetIPSR();
+
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that	use the FreeRTOS API must not be left at their
+             * default priority of	zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and	therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
+
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredictable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
+
+#endif /* configASSERT_DEFINED */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..0fddf40
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
@@ -0,0 +1,264 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+/* *INDENT-OFF* */
+
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH          ( -1 )
+    #define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT        8
+
+/* Constants used with memory barrier intrinsics. */
+    #define portSY_FULL_READ_WRITE    ( 15 )
+
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+    #define portYIELD()                                 \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+                                                        \
+        /* Barriers are normally not required but do ensure the code is completely \
+         * within the specified behaviour for the architecture. */ \
+        __dsb( portSY_FULL_READ_WRITE );                           \
+        __isb( portSY_FULL_READ_WRITE );                           \
+    }
+/*-----------------------------------------------------------*/
+
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired != pdFALSE ) portYIELD()
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+
+    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
+    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
+
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Port specific optimisations. */
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #endif
+
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
+
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
+
+    #endif /* taskRECORD_READY_PRIORITY */
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
+
+/* portNOP() is not required by this port. */
+    #define portNOP()
+
+    #define portINLINE              __inline
+
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE    __forceinline
+    #endif
+
+/*-----------------------------------------------------------*/
+
+    static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+    {
+        __asm
+        {
+            /* Barrier instructions are not used as this function is only used to
+             * lower the BASEPRI value. */
+/* *INDENT-OFF* */
+        msr basepri, ulBASEPRI
+/* *INDENT-ON* */
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+    {
+        uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+        __asm
+        {
+            /* Set BASEPRI to the max syscall priority to effect a critical
+             * section. */
+/* *INDENT-OFF* */
+            msr basepri, ulNewBASEPRI
+            dsb
+            isb
+/* *INDENT-ON* */
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+    {
+        __asm
+        {
+            /* Set BASEPRI to 0 so no interrupts are masked.  This function is only
+             * used to lower the mask in an interrupt, so memory barriers are not
+             * used. */
+/* *INDENT-OFF* */
+            msr basepri, # 0
+/* *INDENT-ON* */
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+    {
+        uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+        __asm
+        {
+            /* Set BASEPRI to the max syscall priority to effect a critical
+             * section. */
+/* *INDENT-OFF* */
+            mrs ulReturn, basepri
+            msr basepri, ulNewBASEPRI
+            dsb
+            isb
+/* *INDENT-ON* */
+        }
+
+        return ulReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        BaseType_t xReturn;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm
+        {
+/* *INDENT-OFF* */
+            mrs ulCurrentInterrupt, ipsr
+/* *INDENT-ON* */
+        }
+
+        if( ulCurrentInterrupt == 0 )
+        {
+            xReturn = pdFALSE;
+        }
+        else
+        {
+            xReturn = pdTRUE;
+        }
+
+        return xReturn;
+    }
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c
new file mode 100644
index 0000000..c09b1c6
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c
@@ -0,0 +1,976 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM4 MPU port.
+*----------------------------------------------------------*/
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __TARGET_FPU_VFP
+    #error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Constants required to access and manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL_REG                 ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG                 ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG        ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                        ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+#define portNVIC_SHPR2_REG                        ( *( ( volatile uint32_t * ) 0xe000ed1c ) )
+#define portNVIC_SYS_CTRL_STATE_REG               ( *( ( volatile uint32_t * ) 0xe000ed24 ) )
+#define portNVIC_MEM_FAULT_ENABLE                 ( 1UL << 16UL )
+
+/* Constants required to access and manipulate the MPU. */
+#define portMPU_TYPE_REG                          ( *( ( volatile uint32_t * ) 0xe000ed90 ) )
+#define portMPU_REGION_BASE_ADDRESS_REG           ( *( ( volatile uint32_t * ) 0xe000ed9C ) )
+#define portMPU_REGION_ATTRIBUTE_REG              ( *( ( volatile uint32_t * ) 0xe000edA0 ) )
+#define portMPU_CTRL_REG                          ( *( ( volatile uint32_t * ) 0xe000ed94 ) )
+#define portEXPECTED_MPU_TYPE_VALUE               ( portTOTAL_NUM_REGIONS << 8UL )
+#define portMPU_ENABLE                            ( 0x01UL )
+#define portMPU_BACKGROUND_ENABLE                 ( 1UL << 2UL )
+#define portPRIVILEGED_EXECUTION_START_ADDRESS    ( 0UL )
+#define portMPU_REGION_VALID                      ( 0x10UL )
+#define portMPU_REGION_ENABLE                     ( 0x01UL )
+#define portPERIPHERALS_START_ADDRESS             0x40000000UL
+#define portPERIPHERALS_END_ADDRESS               0x5FFFFFFFUL
+
+/* Constants required to access and manipulate the SysTick. */
+#define portNVIC_SYSTICK_CLK                      ( 0x00000004UL )
+#define portNVIC_SYSTICK_INT                      ( 0x00000002UL )
+#define portNVIC_SYSTICK_ENABLE                   ( 0x00000001UL )
+#define portNVIC_PENDSV_PRI                       ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI                      ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+#define portNVIC_SVC_PRI                          ( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR                                 ( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS                  ( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                          ( 0x01000000UL )
+#define portINITIAL_EXC_RETURN                    ( 0xfffffffdUL )
+#define portINITIAL_CONTROL_IF_UNPRIVILEGED       ( 0x03 )
+#define portINITIAL_CONTROL_IF_PRIVILEGED         ( 0x02 )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER           ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16           ( 0xE000E3F0 )
+#define portAIRCR_REG                             ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE                       ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE                       ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS                     ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK                   ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                        ( 8UL )
+
+/* Offsets in the stack to the parameters when inside the SVC handler. */
+#define portOFFSET_TO_PC                          ( 6 )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK                    ( ( StackType_t ) 0xfffffffeUL )
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable.  Note this is not saved as part of the task context as context
+ * switches can only occur when uxCriticalNesting is zero. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Setup the timer to generate the tick interrupts.
+ */
+void vSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Configure a number of standard MPU regions that are used by all tasks.
+ */
+static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvStartFirstTask( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the smallest MPU region size that a given number of bytes will fit
+ * into.  The region size is returned as the value that should be programmed
+ * into the region attribute register for that region.
+ */
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
+
+/*
+ * Standard FreeRTOS exception handlers.
+ */
+void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION;
+void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
+void vPortSVCHandler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Starts the scheduler by restoring the context of the first task to run.
+ */
+static void prvRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * C portion of the SVC handler.  The SVC handler is split between an asm entry
+ * and a C wrapper for simplicity of coding and maintenance.
+ */
+void prvSVCHandler( uint32_t * pulRegisters ) __attribute__( ( used ) ) PRIVILEGED_FUNCTION;
+
+/*
+ * Function to enable the VFP.
+ */
+static void vPortEnableVFP( void );
+
+/*
+ * Utility function.
+ */
+static uint32_t prvPortGetIPSR( void );
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+BaseType_t xIsPrivileged( void );
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ *
+ * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
+ *  Bit[0] = 0 --> The processor is running privileged
+ *  Bit[0] = 1 --> The processor is running unprivileged.
+ */
+void vResetPrivilege( void );
+
+/**
+ * @brief Calls the port specific code to raise the privilege.
+ *
+ * @return pdFALSE if privilege was raised, pdTRUE otherwise.
+ */
+extern BaseType_t xPortRaisePrivilege( void );
+
+/**
+ * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
+ * code to reset the privilege, otherwise does nothing.
+ */
+extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters,
+                                     BaseType_t xRunPrivileged )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+    pxTopOfStack--;                                                      /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = 0;                                                   /* LR */
+    pxTopOfStack -= 5;                                                   /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters;                        /* R0 */
+
+    /* A save method is being used that requires each task to maintain its
+     * own exec return value. */
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+    pxTopOfStack -= 9; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    if( xRunPrivileged == pdTRUE )
+    {
+        *pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
+    }
+    else
+    {
+        *pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
+    }
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void prvSVCHandler( uint32_t * pulParam )
+{
+    uint8_t ucSVCNumber;
+    uint32_t ulReg, ulPC;
+
+    #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+        extern uint32_t __syscalls_flash_start__;
+        extern uint32_t __syscalls_flash_end__;
+    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+
+    /* The stack contains: r0, r1, r2, r3, r12, LR, PC and xPSR. The first
+     * argument (r0) is pulParam[ 0 ]. */
+    ulPC = pulParam[ portOFFSET_TO_PC ];
+    ucSVCNumber = ( ( uint8_t * ) ulPC )[ -2 ];
+
+    switch( ucSVCNumber )
+    {
+        case portSVC_START_SCHEDULER:
+            portNVIC_SHPR2_REG |= portNVIC_SVC_PRI;
+            prvRestoreContextOfFirstTask();
+            break;
+
+        case portSVC_YIELD:
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+
+            /* Barriers are normally not required
+             * but do ensure the code is completely
+             * within the specified behaviour for the
+             * architecture. */
+            __asm volatile ( "dsb" );
+            __asm volatile ( "isb" );
+
+            break;
+
+            #if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 )
+                case portSVC_RAISE_PRIVILEGE: /* Only raise the privilege, if the
+                                               * svc was raised from any of the
+                                               * system calls. */
+
+                    if( ( ulPC >= ( uint32_t ) __syscalls_flash_start__ ) &&
+                        ( ulPC <= ( uint32_t ) __syscalls_flash_end__ ) )
+                    {
+                        __asm
+                        {
+/* *INDENT-OFF* */
+                            mrs ulReg, control /* Obtain current control value. */
+                            bic ulReg, # 1     /* Set privilege bit. */
+                            msr control, ulReg /* Write back new control value. */
+/* *INDENT-ON* */
+                        }
+                    }
+
+                    break;
+            #else /* if ( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+                case portSVC_RAISE_PRIVILEGE:
+                    __asm
+                    {
+/* *INDENT-OFF* */
+                        mrs ulReg, control /* Obtain current control value. */
+                        bic ulReg, # 1     /* Set privilege bit. */
+                        msr control, ulReg /* Write back new control value. */
+/* *INDENT-ON* */
+                    }
+                    break;
+                    #endif /* #if( configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY == 1 ) */
+
+                default: /* Unknown SVC call. */
+                    break;
+    }
+}
+/*-----------------------------------------------------------*/
+
+__asm void vPortSVCHandler( void )
+{
+    extern prvSVCHandler
+
+/* *INDENT-OFF* */
+        PRESERVE8
+
+    /* Assumes psp was in use. */
+    #ifndef USE_PROCESS_STACK   /* Code should not be required if a main() is using the process stack. */
+        tst lr, # 4
+        ite eq
+        mrseq r0, msp
+        mrsne r0, psp
+    #else
+        mrs r0, psp
+    #endif
+
+    b prvSVCHandler
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvRestoreContextOfFirstTask( void )
+{
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    ldr r0, =0xE000ED08 /* Use the NVIC offset register to locate the stack. */
+    ldr r0, [ r0 ]
+    ldr r0, [ r0 ]
+    msr msp, r0              /* Set the msp back to the start of the stack. */
+    ldr r3, =pxCurrentTCB   /* Restore the context. */
+    ldr r1, [ r3 ]
+    ldr r0, [ r1 ]    /* The first item in the TCB is the task top of stack. */
+    add r1, r1, #4          /* Move onto the second item in the TCB... */
+
+    dmb               /* Complete outstanding transfers before disabling MPU. */
+    ldr r2, =0xe000ed94     /* MPU_CTRL register. */
+    ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
+    bic r3, r3, # 1          /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
+    str r3, [ r2 ]           /* Disable MPU. */
+
+    ldr r2, =0xe000ed9c     /* Region Base Address register. */
+    ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+    stmia r2, { r4 - r11 }  /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+
+    #if ( portTOTAL_NUM_REGIONS == 16 )
+        ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
+        stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
+        ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
+        stmia r2, { r4 - r11 }  /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
+    #endif /* portTOTAL_NUM_REGIONS == 16. */
+
+    ldr r2, =0xe000ed94     /* MPU_CTRL register. */
+    ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
+    orr r3, r3, #1          /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
+    str r3, [ r2 ]           /* Enable MPU. */
+    dsb                      /* Force memory writes before continuing. */
+
+    ldmia r0 !, { r3 - r11, r14 } /* Pop the registers that are not automatically saved on exception entry. */
+    msr control, r3
+    msr psp, r0 /* Restore the task stack pointer. */
+    mov r0, #0
+    msr basepri, r0
+    bx r14
+    nop
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See
+     * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
+
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+            volatile uint8_t ucMaxPriorityValue;
+
+            /* Determine the maximum priority from which ISR safe FreeRTOS API
+             * functions can be called.  ISR safe functions are those that end in
+             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+             * ensure interrupt entry is as fast and simple as possible.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+            /* Determine the number of priority bits available.  First write to all
+             * possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+            /* Use the same mask on the maximum system call priority. */
+            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+            /* Calculate the maximum acceptable priority group value for the number
+             * of bits read back. */
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+            {
+                ulMaxPRIGROUPValue--;
+                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+            }
+
+            #ifdef __NVIC_PRIO_BITS
+                {
+                    /* Check the CMSIS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+                }
+            #endif
+
+            #ifdef configPRIO_BITS
+                {
+                    /* Check the FreeRTOS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+                }
+            #endif
+
+            /* Shift the priority group value back to its position within the AIRCR
+             * register. */
+            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* conifgASSERT_DEFINED */
+
+    /* Make PendSV and SysTick the same priority as the kernel, and the SVC
+     * handler higher priority so it can be used to exit a critical section (where
+     * lower priorities are masked). */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Configure the regions in the MPU that are common to all tasks. */
+    prvSetupMPU();
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Ensure the VFP is enabled - it should be anyway. */
+    vPortEnableVFP();
+
+    /* Lazy save always. */
+    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+    /* Start the first task. */
+    prvStartFirstTask();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvStartFirstTask( void )
+{
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    /* Use the NVIC offset register to locate the stack. */
+    ldr r0, =0xE000ED08
+    ldr r0, [ r0 ]
+    ldr r0, [ r0 ]
+    /* Set the msp back to the start of the stack. */
+    msr msp, r0
+
+    /* Clear the bit that indicates the FPU is in use in case the FPU was used
+     * before the scheduler was started - which would otherwise result in the
+     * unnecessary leaving of space in the SVC stack for lazy saving of FPU
+     * registers. */
+    mov r0, #0
+    msr control, r0
+    /* Globally enable interrupts. */
+    cpsie i
+    cpsie f
+    dsb
+    isb
+    svc portSVC_START_SCHEDULER /* System call to start first task. */
+    nop
+    nop
+/* *INDENT-ON* */
+}
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+
+    vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    BaseType_t xRunningPrivileged = xPortRaisePrivilege();
+
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+
+    vPortResetPrivilege( xRunningPrivileged );
+}
+/*-----------------------------------------------------------*/
+
+__asm void xPortPendSVHandler( void )
+{
+    extern uxCriticalNesting;
+    extern pxCurrentTCB;
+    extern vTaskSwitchContext;
+
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    mrs r0, psp
+
+    ldr r3, =pxCurrentTCB /* Get the location of the current TCB. */
+    ldr r2, [ r3 ]
+
+    tst r14, #0x10 /* Is the task using the FPU context?  If so, push high vfp registers. */
+    it eq
+    vstmdbeq r0 !, { s16 - s31 }
+
+    mrs r1, control
+    stmdb r0 !, { r1, r4 - r11, r14 }   /* Save the remaining registers. */
+    str r0, [ r2 ] /* Save the new top of stack into the first member of the TCB. */
+
+    stmdb sp !, { r0, r3 }
+    mov r0, # configMAX_SYSCALL_INTERRUPT_PRIORITY
+    msr basepri, r0
+    dsb
+    isb
+    bl vTaskSwitchContext
+    mov r0, #0
+    msr basepri, r0
+    ldmia sp !, { r0, r3 }
+    /* Restore the context. */
+    ldr r1, [ r3 ]
+    ldr r0, [ r1 ]           /* The first item in the TCB is the task top of stack. */
+    add r1, r1, #4          /* Move onto the second item in the TCB... */
+
+    dmb                      /* Complete outstanding transfers before disabling MPU. */
+    ldr r2, =0xe000ed94     /* MPU_CTRL register. */
+    ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
+    bic r3, r3, #1          /* r3 = r3 & ~1 i.e. Clear the bit 0 in r3. */
+    str r3, [ r2 ]           /* Disable MPU. */
+
+    ldr r2, =0xe000ed9c     /* Region Base Address register. */
+    ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 4 - 7]. */
+    stmia r2, { r4 - r11 }   /* Write 4 sets of MPU registers [MPU Region # 4 - 7]. */
+
+    #if ( portTOTAL_NUM_REGIONS == 16 )
+        ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 8 - 11]. */
+        stmia r2, { r4 - r11 }  /* Write 4 sets of MPU registers. [MPU Region # 8 - 11]. */
+        ldmia r1 !, { r4 - r11 } /* Read 4 sets of MPU registers [MPU Region # 12 - 15]. */
+        stmia r2, { r4 - r11 } /* Write 4 sets of MPU registers. [MPU Region # 12 - 15]. */
+    #endif /* portTOTAL_NUM_REGIONS == 16. */
+
+    ldr r2, =0xe000ed94     /* MPU_CTRL register. */
+    ldr r3, [ r2 ] /* Read the value of MPU_CTRL. */
+    orr r3, r3, #1          /* r3 = r3 | 1 i.e. Set the bit 0 in r3. */
+    str r3, [ r2 ]           /* Enable MPU. */
+    dsb                      /* Force memory writes before continuing. */
+
+    ldmia r0 !, { r3 - r11, r14 }                               /* Pop the registers that are not automatically saved on exception entry. */
+    msr control, r3
+
+    tst r14, #0x10 /* Is the task using the FPU context?  If so, pop the high vfp registers too. */
+    it eq
+    vldmiaeq r0 !, { s16 - s31 }
+
+    msr psp, r0
+    bx r14
+    nop
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    uint32_t ulDummy;
+
+    ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__weak void vSetupTimerInterrupt( void )
+{
+    /* Reset the SysTick. */
+    portNVIC_SYSTICK_CTRL_REG = 0UL;
+    portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+    /* Configure SysTick to interrupt at the requested rate. */
+    portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
+
+__asm void vPortSwitchToUserMode( void )
+{
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    mrs r0, control
+    orr r0, #1
+    msr control, r0
+    bx r14
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+__asm void vPortEnableVFP( void )
+{
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    ldr.w r0, =0xE000ED88 /* The FPU enable bits are in the CPACR. */
+    ldr r1, [ r0 ]
+
+    orr r1, r1, #( 0xf << 20 ) /* Enable CP10 and CP11 coprocessors, then save back. */
+    str r1, [ r0 ]
+    bx r14
+    nop
+    nop
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupMPU( void )
+{
+    extern uint32_t __privileged_functions_start__;
+    extern uint32_t __privileged_functions_end__;
+    extern uint32_t __FLASH_segment_start__;
+    extern uint32_t __FLASH_segment_end__;
+    extern uint32_t __privileged_data_start__;
+    extern uint32_t __privileged_data_end__;
+
+    /* The only permitted number of regions are 8 or 16. */
+    configASSERT( ( portTOTAL_NUM_REGIONS == 8 ) || ( portTOTAL_NUM_REGIONS == 16 ) );
+
+    /* Ensure that the configTOTAL_MPU_REGIONS is configured correctly. */
+    configASSERT( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE );
+
+    /* Check the expected MPU is present. */
+    if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
+    {
+        /* First setup the unprivileged flash for unprivileged read only access. */
+        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
+                                          ( portMPU_REGION_VALID ) |
+                                          ( portUNPRIVILEGED_FLASH_REGION );
+
+        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_ONLY ) |
+                                       ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+                                       ( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
+                                       ( portMPU_REGION_ENABLE );
+
+        /* Setup the privileged flash for privileged only access.  This is where
+         * the kernel code is placed. */
+        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_functions_start__ ) | /* Base address. */
+                                          ( portMPU_REGION_VALID ) |
+                                          ( portPRIVILEGED_FLASH_REGION );
+
+        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
+                                       ( ( configTEX_S_C_B_FLASH & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+                                       ( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __privileged_functions_start__ ) ) |
+                                       ( portMPU_REGION_ENABLE );
+
+        /* Setup the privileged data RAM region.  This is where the kernel data
+         * is placed. */
+        portMPU_REGION_BASE_ADDRESS_REG = ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+                                          ( portMPU_REGION_VALID ) |
+                                          ( portPRIVILEGED_RAM_REGION );
+
+        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+                                       ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+                                       prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+                                       ( portMPU_REGION_ENABLE );
+
+        /* By default allow everything to access the general peripherals.  The
+         * system peripherals and registers are protected. */
+        portMPU_REGION_BASE_ADDRESS_REG = ( portPERIPHERALS_START_ADDRESS ) |
+                                          ( portMPU_REGION_VALID ) |
+                                          ( portGENERAL_PERIPHERALS_REGION );
+
+        portMPU_REGION_ATTRIBUTE_REG = ( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
+                                       ( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
+                                       ( portMPU_REGION_ENABLE );
+
+        /* Enable the memory fault exception. */
+        portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
+
+        /* Enable the MPU with the background region configured. */
+        portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
+    }
+}
+/*-----------------------------------------------------------*/
+
+static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
+{
+    uint32_t ulRegionSize, ulReturnValue = 4;
+
+    /* 32 is the smallest region size, 31 is the largest valid value for
+     * ulReturnValue. */
+    for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
+    {
+        if( ulActualSizeInBytes <= ulRegionSize )
+        {
+            break;
+        }
+        else
+        {
+            ulReturnValue++;
+        }
+    }
+
+    /* Shift the code by one before returning so it can be written directly
+     * into the the correct bit position of the attribute register. */
+    return( ulReturnValue << 1UL );
+}
+/*-----------------------------------------------------------*/
+
+__asm BaseType_t xIsPrivileged( void )
+{
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    mrs r0, control /* r0 = CONTROL. */
+    tst r0, #1     /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
+    ite ne
+    movne r0, #0   /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
+    moveq r0, #1   /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
+    bx lr           /* Return. */
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+__asm void vResetPrivilege( void )
+{
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    mrs r0, control /* r0 = CONTROL. */
+    orrs r0, #1    /* r0 = r0 | 1. */
+    msr control, r0 /* CONTROL = r0. */
+    bx lr           /* Return. */
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                const struct xMEMORY_REGION * const xRegions,
+                                StackType_t * pxBottomOfStack,
+                                uint32_t ulStackDepth )
+{
+    extern uint32_t __SRAM_segment_start__;
+    extern uint32_t __SRAM_segment_end__;
+    extern uint32_t __privileged_data_start__;
+    extern uint32_t __privileged_data_end__;
+
+
+    int32_t lIndex;
+    uint32_t ul;
+
+    if( xRegions == NULL )
+    {
+        /* No MPU regions are specified so allow access to all RAM. */
+        xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+            ( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
+            ( portMPU_REGION_VALID ) |
+            ( portSTACK_REGION );
+
+        xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+            ( portMPU_REGION_READ_WRITE ) |
+            ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+            ( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
+            ( portMPU_REGION_ENABLE );
+
+        /* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
+         * just removed the privileged only parameters. */
+        xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
+            ( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
+            ( portMPU_REGION_VALID ) |
+            ( portSTACK_REGION + 1 );
+
+        xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
+            ( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
+            ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+            prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
+            ( portMPU_REGION_ENABLE );
+
+        /* Invalidate all other regions. */
+        for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+        {
+            xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+            xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+        }
+    }
+    else
+    {
+        /* This function is called automatically when the task is created - in
+         * which case the stack region parameters will be valid.  At all other
+         * times the stack parameters will not be valid and it is assumed that the
+         * stack region has already been configured. */
+        if( ulStackDepth > 0 )
+        {
+            /* Define the region that allows access to the stack. */
+            xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
+                ( ( uint32_t ) pxBottomOfStack ) |
+                ( portMPU_REGION_VALID ) |
+                ( portSTACK_REGION ); /* Region number. */
+
+            xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
+                ( portMPU_REGION_READ_WRITE ) | /* Read and write. */
+                ( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
+                ( ( configTEX_S_C_B_SRAM & portMPU_RASR_TEX_S_C_B_MASK ) << portMPU_RASR_TEX_S_C_B_LOCATION ) |
+                ( portMPU_REGION_ENABLE );
+        }
+
+        lIndex = 0;
+
+        for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
+        {
+            if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
+            {
+                /* Translate the generic region definition contained in
+                 * xRegions into the CM4 specific MPU settings that are then
+                 * stored in xMPUSettings. */
+                xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
+                    ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
+                    ( portMPU_REGION_VALID ) |
+                    ( portSTACK_REGION + ul ); /* Region number. */
+
+                xMPUSettings->xRegion[ ul ].ulRegionAttribute =
+                    ( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
+                    ( xRegions[ lIndex ].ulParameters ) |
+                    ( portMPU_REGION_ENABLE );
+            }
+            else
+            {
+                /* Invalidate the region. */
+                xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
+                xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
+            }
+
+            lIndex++;
+        }
+    }
+}
+/*-----------------------------------------------------------*/
+
+__asm uint32_t prvPortGetIPSR( void )
+{
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    mrs r0, ipsr
+    bx r14
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+    void vPortValidateInterruptPriority( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        uint8_t ucCurrentPriority;
+
+        /* Obtain the number of the currently executing interrupt. */
+        ulCurrentInterrupt = prvPortGetIPSR();
+
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that	use the FreeRTOS API must not be left at their
+             * default priority of	zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and	therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
+
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredicable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
+
+#endif /* configASSERT_DEFINED */
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
new file mode 100644
index 0000000..7cc5bbf
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
@@ -0,0 +1,413 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    uint32_t
+#define portBASE_TYPE     long
+
+typedef portSTACK_TYPE   StackType_t;
+typedef long             BaseType_t;
+typedef unsigned long    UBaseType_t;
+
+#if ( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffff
+#else
+    typedef uint32_t     TickType_t;
+    #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+    #define portTICK_TYPE_IS_ATOMIC    1
+#endif
+/*-----------------------------------------------------------*/
+
+/* MPU specific constants. */
+#define portUSING_MPU_WRAPPERS                                   1
+#define portPRIVILEGE_BIT                                        ( 0x80000000UL )
+
+#define portMPU_REGION_READ_WRITE                                ( 0x03UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_ONLY                      ( 0x05UL << 24UL )
+#define portMPU_REGION_READ_ONLY                                 ( 0x06UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE                     ( 0x01UL << 24UL )
+#define portMPU_REGION_PRIVILEGED_READ_WRITE_UNPRIV_READ_ONLY    ( 0x02UL << 24UL )
+#define portMPU_REGION_CACHEABLE_BUFFERABLE                      ( 0x07UL << 16UL )
+#define portMPU_REGION_EXECUTE_NEVER                             ( 0x01UL << 28UL )
+
+/* Location of the TEX,S,C,B bits in the MPU Region Attribute and Size
+ * Register (RASR). */
+#define portMPU_RASR_TEX_S_C_B_LOCATION                          ( 16UL )
+#define portMPU_RASR_TEX_S_C_B_MASK                              ( 0x3FUL )
+
+/* MPU settings that can be overriden in FreeRTOSConfig.h. */
+#ifndef configTOTAL_MPU_REGIONS
+    /* Define to 8 for backward compatibility. */
+    #define configTOTAL_MPU_REGIONS    ( 8UL )
+#endif
+
+/*
+ * The TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits define the
+ * memory type, and where necessary the cacheable and shareable properties
+ * of the memory region.
+ *
+ * The TEX, C, and B bits together indicate the memory type of the region,
+ * and:
+ * - For Normal memory, the cacheable properties of the region.
+ * - For Device memory, whether the region is shareable.
+ *
+ * For Normal memory regions, the S bit indicates whether the region is
+ * shareable. For Strongly-ordered and Device memory, the S bit is ignored.
+ *
+ * See the following two tables for setting TEX, S, C and B bits for
+ * unprivileged flash, privileged flash and privileged RAM regions.
+ *
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | TEX | C | B | Memory type            |  Description or Normal region cacheability             |  Shareable?             |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 0 | 0 | Strongly-ordered       |  Strongly ordered                                      |  Shareable              |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 0 | 1 | Device                 |  Shared device                                         |  Shareable              |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 1 | 0 | Normal                 |  Outer and inner   write-through; no write allocate    |  S bit                  |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 000 | 1 | 1 | Normal                 |  Outer and inner   write-back; no write allocate       |  S bit                  |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 0 | 0 | Normal                 |  Outer and inner   Non-cacheable                       |  S bit                  |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 0 | 1 | Reserved               |  Reserved                                              |  Reserved               |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 1 | 0 | IMPLEMENTATION DEFINED |  IMPLEMENTATION DEFINED                                |  IMPLEMENTATION DEFINED |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 001 | 1 | 1 | Normal                 |  Outer and inner   write-back; write and read allocate |  S bit                  |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 0 | 0 | Device                 |  Non-shared device                                     |  Not shareable          |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 0 | 1 | Reserved               |  Reserved                                              |  Reserved               |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 010 | 1 | X | Reserved               |  Reserved                                              |  Reserved               |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 011 | X | X | Reserved               |  Reserved                                              |  Reserved               |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ | 1BB | A | A | Normal                 | Cached memory, with AA and BB indicating the inner and |  Reserved               |
+ |     |   |   |                        | outer cacheability rules that must be exported on the  |                         |
+ |     |   |   |                        | bus. See the table below for the cacheability policy   |                         |
+ |     |   |   |                        | encoding. memory, BB=Outer policy, AA=Inner policy.    |                         |
+ +-----+---+---+------------------------+--------------------------------------------------------+-------------------------+
+ |
+ +-----------------------------------------+----------------------------------------+
+ | AA or BB subfield of {TEX,C,B} encoding |  Cacheability policy                   |
+ +-----------------------------------------+----------------------------------------+
+ | 00                                      |  Non-cacheable                         |
+ +-----------------------------------------+----------------------------------------+
+ | 01                                      |  Write-back, write and   read allocate |
+ +-----------------------------------------+----------------------------------------+
+ | 10                                      |  Write-through, no write   allocate    |
+ +-----------------------------------------+----------------------------------------+
+ | 11                                      |  Write-back, no write   allocate       |
+ +-----------------------------------------+----------------------------------------+
+ */
+
+/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for Flash
+ * region. */
+#ifndef configTEX_S_C_B_FLASH
+    /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
+    #define configTEX_S_C_B_FLASH    ( 0x07UL )
+#endif
+
+/* TEX, Shareable (S), Cacheable (C) and Bufferable (B) bits for SRAM
+ * region. */
+#ifndef configTEX_S_C_B_SRAM
+    /* Default to TEX=000, S=1, C=1, B=1 for backward compatibility. */
+    #define configTEX_S_C_B_SRAM          ( 0x07UL )
+#endif
+
+#define portUNPRIVILEGED_FLASH_REGION     ( 0UL )
+#define portPRIVILEGED_FLASH_REGION       ( 1UL )
+#define portPRIVILEGED_RAM_REGION         ( 2UL )
+#define portGENERAL_PERIPHERALS_REGION    ( 3UL )
+#define portSTACK_REGION                  ( 4UL )
+#define portFIRST_CONFIGURABLE_REGION     ( 5UL )
+#define portTOTAL_NUM_REGIONS             ( configTOTAL_MPU_REGIONS )
+#define portNUM_CONFIGURABLE_REGIONS      ( portTOTAL_NUM_REGIONS - portFIRST_CONFIGURABLE_REGION )
+#define portLAST_CONFIGURABLE_REGION      ( portTOTAL_NUM_REGIONS - 1 )
+
+void vPortSwitchToUserMode( void );
+#define portSWITCH_TO_USER_MODE()    vPortSwitchToUserMode()
+
+typedef struct MPU_REGION_REGISTERS
+{
+    uint32_t ulRegionBaseAddress;
+    uint32_t ulRegionAttribute;
+} xMPU_REGION_REGISTERS;
+
+/* Plus 1 to create space for the stack region. */
+typedef struct MPU_SETTINGS
+{
+    xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
+} xMPU_SETTINGS;
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH          ( -1 )
+#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT        8
+
+/* Constants used with memory barrier intrinsics. */
+#define portSY_FULL_READ_WRITE    ( 15 )
+
+/*-----------------------------------------------------------*/
+
+/* SVC numbers for various services. */
+#define portSVC_START_SCHEDULER    0
+#define portSVC_YIELD              1
+#define portSVC_RAISE_PRIVILEGE    2
+
+/* Scheduler utilities. */
+
+#define portYIELD()    __asm{ SVC portSVC_YIELD }
+#define portYIELD_WITHIN_API()                          \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+                                                        \
+        /* Barriers are normally not required but do ensure the code is completely \
+         * within the specified behaviour for the architecture. */ \
+        __dsb( portSY_FULL_READ_WRITE );                           \
+        __isb( portSY_FULL_READ_WRITE );                           \
+    }
+/*-----------------------------------------------------------*/
+
+#define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
+#define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+
+#define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
+#define portENTER_CRITICAL()                      vPortEnterCritical()
+#define portEXIT_CRITICAL()                       vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+    #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Check the configuration. */
+    #if ( configMAX_PRIORITIES > 32 )
+        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+    #endif
+
+/* Store/clear the ready priorities in a bit map. */
+    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+    void vPortValidateInterruptPriority( void );
+    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE              __inline
+
+#ifndef portFORCE_INLINE
+    #define portFORCE_INLINE    __forceinline
+#endif
+/*-----------------------------------------------------------*/
+
+extern BaseType_t xIsPrivileged( void );
+extern void vResetPrivilege( void );
+
+/**
+ * @brief Checks whether or not the processor is privileged.
+ *
+ * @return 1 if the processor is already privileged, 0 otherwise.
+ */
+#define portIS_PRIVILEGED()      xIsPrivileged()
+
+/**
+ * @brief Raise an SVC request to raise privilege.
+ */
+#define portRAISE_PRIVILEGE()    __asm { svc portSVC_RAISE_PRIVILEGE }
+
+/**
+ * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
+ * register.
+ */
+#define portRESET_PRIVILEGE()    vResetPrivilege()
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+{
+    __asm
+    {
+        /* Barrier instructions are not used as this function is only used to
+         * lower the BASEPRI value. */
+/* *INDENT-OFF* */
+        msr basepri, ulBASEPRI
+/* *INDENT-ON* */
+    }
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+{
+    uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+    __asm
+    {
+        /* Set BASEPRI to the max syscall priority to effect a critical
+         * section. */
+/* *INDENT-OFF* */
+        msr basepri, ulNewBASEPRI
+        dsb
+        isb
+/* *INDENT-ON* */
+    }
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+{
+    __asm
+    {
+        /* Set BASEPRI to 0 so no interrupts are masked.  This function is only
+         * used to lower the mask in an interrupt, so memory barriers are not
+         * used. */
+/* *INDENT-OFF* */
+        msr basepri, # 0
+/* *INDENT-ON* */
+    }
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+{
+    uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+    __asm
+    {
+        /* Set BASEPRI to the max syscall priority to effect a critical
+         * section. */
+/* *INDENT-OFF* */
+        mrs ulReturn, basepri
+        msr basepri, ulNewBASEPRI
+        dsb
+        isb
+/* *INDENT-ON* */
+    }
+
+    return ulReturn;
+}
+/*-----------------------------------------------------------*/
+
+static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+{
+    uint32_t ulCurrentInterrupt;
+    BaseType_t xReturn;
+
+    /* Obtain the number of the currently executing interrupt. */
+    __asm
+    {
+        mrs ulCurrentInterrupt, ipsr
+    }
+
+    if( ulCurrentInterrupt == 0 )
+    {
+        xReturn = pdFALSE;
+    }
+    else
+    {
+        xReturn = pdTRUE;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#ifndef configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY
+    #warning "configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY is not defined. We recommend defining it to 1 in FreeRTOSConfig.h for better security. https://www.FreeRTOS.org/FreeRTOS-V10.3.x.html"
+    #define configENFORCE_SYSTEM_CALLS_FROM_KERNEL_ONLY    0
+#endif
+/*-----------------------------------------------------------*/
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM7/ReadMe.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM7/ReadMe.txt
new file mode 100644
index 0000000..b3950da
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM7/ReadMe.txt
@@ -0,0 +1,18 @@
+There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.
+The best option depends on the revision of the ARM Cortex-M7 core in use.  The
+revision is specified by an 'r' number, and a 'p' number, so will look something
+like 'r0p1'.  Check the documentation for the microcontroller in use to find the 
+revision of the Cortex-M7 core used in that microcontroller.  If in doubt, use 
+the FreeRTOS port provided specifically for r0p1 revisions, as that can be used
+with all core revisions.
+
+The first option is to use the ARM Cortex-M4F port, and the second option is to
+use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.
+
+If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be
+used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in 
+the /FreeRTOS/Source/portable/RVDS/ARM_CM4F directory.
+
+If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM
+Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1
+directory.
\ No newline at end of file
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/port.c
new file mode 100644
index 0000000..25e5f5a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/port.c
@@ -0,0 +1,795 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM7 port.
+*----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+#ifndef __TARGET_FPU_VFP
+    #error This port can only be used when the project options are configured to enable hardware floating point support.
+#endif
+
+#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
+    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http: /*www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+    #define configSYSTICK_CLOCK_HZ      configCPU_CLOCK_HZ
+    /* Ensure the SysTick is clocked at the same frequency as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 1UL << 2UL )
+#else
+
+/* The way the SysTick is clocked is not modified in case it is not the same
+ * as the core. */
+    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
+#endif
+
+/* The __weak attribute does not work as you might expect with the Keil tools
+ * so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
+ * the application writer wants to provide their own implementation of
+ * vPortSetupTimerInterrupt().  Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+ * is defined. */
+#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
+    #define configOVERRIDE_DEFAULT_TICK_CONFIGURATION    0
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG             ( *( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG             ( *( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG    ( *( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SHPR3_REG                    ( *( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT              ( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT           ( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT       ( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT              ( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT       ( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI                   ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI                  ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER       ( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16       ( 0xE000E3F0 )
+#define portAIRCR_REG                         ( *( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE                   ( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE                   ( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS                 ( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK               ( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT                    ( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK                   ( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR                             ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS              ( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR                      ( 0x01000000 )
+#define portINITIAL_EXC_RETURN                ( 0xfffffffd )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER                 ( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+ * occurred while the SysTick counter is stopped during tickless idle
+ * calculations. */
+#define portMISSED_COUNTS_FACTOR              ( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK                ( ( StackType_t ) 0xfffffffeUL )
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void );
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void );
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Functions defined in portasm.s to enable the VFP.
+ */
+static void prvEnableVFP( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if ( configUSE_TICKLESS_IDLE == 1 )
+    static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+    static uint8_t ucMaxSysCallPriority = 0;
+    static uint32_t ulMaxPRIGROUPValue = 0;
+    static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+
+    /* Offset added to account for the way the MCU uses the stack on entry/exit
+     * of interrupts, and to ensure alignment. */
+    pxTopOfStack--;
+
+    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) prvTaskExitError;                    /* LR */
+
+    /* Save code space by skipping register initialisation. */
+    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+    /* A save method is being used that requires each task to maintain its
+     * own exec return value. */
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+    pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( uxCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    for( ; ; )
+    {
+    }
+}
+/*-----------------------------------------------------------*/
+
+__asm void vPortSVCHandler( void )
+{
+    PRESERVE8
+
+/* *INDENT-OFF* */
+    /* Get the location of the current TCB. */
+    ldr r3, =pxCurrentTCB
+    ldr r1, [ r3 ]
+    ldr r0, [ r1 ]
+    /* Pop the core registers. */
+    ldmia r0 !, { r4 - r11, r14 }
+    msr psp, r0
+    isb
+    mov r0, #0
+    msr basepri, r0
+    bx r14
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvStartFirstTask( void )
+{
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    /* Use the NVIC offset register to locate the stack. */
+    ldr r0, =0xE000ED08
+    ldr r0, [ r0 ]
+    ldr r0, [ r0 ]
+    /* Set the msp back to the start of the stack. */
+    msr msp, r0
+
+    /* Clear the bit that indicates the FPU is in use in case the FPU was used
+     * before the scheduler was started - which would otherwise result in the
+     * unnecessary leaving of space in the SVC stack for lazy saving of FPU
+     * registers. */
+    mov r0, #0
+    msr control, r0
+    /* Globally enable interrupts. */
+    cpsie i
+    cpsie f
+    dsb
+    isb
+    /* Call SVC to start the first task. */
+    svc 0
+    nop
+    nop
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+__asm void prvEnableVFP( void )
+{
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    /* The FPU enable bits are in the CPACR. */
+    ldr.w r0, =0xE000ED88
+    ldr r1, [ r0 ]
+
+    /* Enable CP10 and CP11 coprocessors, then save back. */
+    orr r1, r1, #( 0xf << 20 )
+    str r1, [ r0 ]
+    bx r14
+    nop
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            volatile uint32_t ulOriginalPriority;
+            volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+            volatile uint8_t ucMaxPriorityValue;
+
+            /* Determine the maximum priority from which ISR safe FreeRTOS API
+             * functions can be called.  ISR safe functions are those that end in
+             * "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+             * ensure interrupt entry is as fast and simple as possible.
+             *
+             * Save the interrupt priority value that is about to be clobbered. */
+            ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+            /* Determine the number of priority bits available.  First write to all
+             * possible bits. */
+            *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+            /* Read the value back to see how many bits stuck. */
+            ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+            /* The kernel interrupt priority should be set to the lowest
+             * priority. */
+            configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
+
+            /* Use the same mask on the maximum system call priority. */
+            ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+            /* Calculate the maximum acceptable priority group value for the number
+             * of bits read back. */
+            ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+
+            while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+            {
+                ulMaxPRIGROUPValue--;
+                ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+            }
+
+            #ifdef __NVIC_PRIO_BITS
+                {
+                    /* Check the CMSIS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
+                }
+            #endif
+
+            #ifdef configPRIO_BITS
+                {
+                    /* Check the FreeRTOS configuration that defines the number of
+                     * priority bits matches the number of priority bits actually queried
+                     * from the hardware. */
+                    configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
+                }
+            #endif
+
+            /* Shift the priority group value back to its position within the AIRCR
+             * register. */
+            ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+            ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+            /* Restore the clobbered interrupt priority register to its original
+             * value. */
+            *pucFirstUserPriorityRegister = ulOriginalPriority;
+        }
+    #endif /* conifgASSERT_DEFINED */
+
+    /* Make PendSV and SysTick the lowest priority interrupts. */
+    portNVIC_SHPR3_REG |= portNVIC_PENDSV_PRI;
+
+    portNVIC_SHPR3_REG |= portNVIC_SYSTICK_PRI;
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    vPortSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    uxCriticalNesting = 0;
+
+    /* Ensure the VFP is enabled - it should be anyway. */
+    prvEnableVFP();
+
+    /* Lazy save always. */
+    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+    /* Start the first task. */
+    prvStartFirstTask();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    uxCriticalNesting++;
+
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
+    if( uxCriticalNesting == 1 )
+    {
+        configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    configASSERT( uxCriticalNesting );
+    uxCriticalNesting--;
+
+    if( uxCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+__asm void xPortPendSVHandler( void )
+{
+    extern uxCriticalNesting;
+    extern pxCurrentTCB;
+    extern vTaskSwitchContext;
+
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    mrs r0, psp
+    isb
+    /* Get the location of the current TCB. */
+    ldr r3, =pxCurrentTCB
+    ldr r2, [ r3 ]
+
+    /* Is the task using the FPU context?  If so, push high vfp registers. */
+    tst r14, #0x10
+    it eq
+    vstmdbeq r0 !, { s16 - s31 }
+
+    /* Save the core registers. */
+    stmdb r0 !, { r4 - r11, r14 }
+
+    /* Save the new top of stack into the first member of the TCB. */
+    str r0, [ r2 ]
+
+    stmdb sp !, { r0, r3 }
+    mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
+    cpsid i
+    msr basepri, r0
+    dsb
+    isb
+    cpsie i
+    bl vTaskSwitchContext
+    mov r0, #0
+    msr basepri, r0
+    ldmia sp !, { r0, r3 }
+
+    /* The first item in pxCurrentTCB is the task top of stack. */
+    ldr r1, [ r3 ]
+    ldr r0, [ r1 ]
+
+    /* Pop the core registers. */
+    ldmia r0 !, { r4 - r11, r14 }
+
+    /* Is the task using the FPU context?  If so, pop the high vfp registers
+     * too. */
+    tst r14, #0x10
+    it eq
+    vldmiaeq r0 !, { s16 - s31 }
+
+    msr psp, r0
+    isb
+    #ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
+        #if WORKAROUND_PMU_CM001 == 1
+            push { r14 }
+            pop { pc }
+            nop
+        #endif
+    #endif
+
+    bx r14
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+    /* The SysTick runs at the lowest interrupt priority, so when this interrupt
+     * executes all interrupts must be unmasked.  There is therefore no need to
+     * save and then restore the interrupt mask value as its value is already
+     * known - therefore the slightly faster vPortRaiseBASEPRI() function is used
+     * in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
+    vPortRaiseBASEPRI();
+    {
+        /* Increment the RTOS tick. */
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* A context switch is required.  Context switching is performed in
+             * the PendSV interrupt.  Pend the PendSV interrupt. */
+            portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+        }
+    }
+
+    vPortClearBASEPRIFromISR();
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE == 1 )
+
+    __weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+    {
+        uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
+        TickType_t xModifiableIdleTime;
+
+        /* Make sure the SysTick reload value does not overflow the counter. */
+        if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+        {
+            xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+        }
+
+        /* Stop the SysTick momentarily.  The time the SysTick is stopped for
+         * is accounted for as best it can be, but using the tickless mode will
+         * inevitably result in some tiny drift of the time maintained by the
+         * kernel with respect to calendar time. */
+        portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+        /* Calculate the reload value required to wait xExpectedIdleTime
+         * tick periods.  -1 is used because this code will execute part way
+         * through one of the tick periods. */
+        ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+
+        if( ulReloadValue > ulStoppedTimerCompensation )
+        {
+            ulReloadValue -= ulStoppedTimerCompensation;
+        }
+
+        /* Enter a critical section but don't use the taskENTER_CRITICAL()
+         * method as that will mask interrupts that should exit sleep mode. */
+        __disable_irq();
+        __dsb( portSY_FULL_READ_WRITE );
+        __isb( portSY_FULL_READ_WRITE );
+
+        /* If a context switch is pending or a task is waiting for the scheduler
+         * to be unsuspended then abandon the low power entry. */
+        if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+        {
+            /* Restart from whatever is left in the count register to complete
+             * this tick period. */
+            portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Reset the reload register to the value required for normal tick
+             * periods. */
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Re-enable interrupts - see comments above __disable_irq() call
+             * above. */
+            __enable_irq();
+        }
+        else
+        {
+            /* Set the new reload value. */
+            portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+            /* Clear the SysTick count flag and set the count value back to
+             * zero. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+            /* Restart SysTick. */
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+            /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+             * set its parameter to 0 to indicate that its implementation contains
+             * its own wait for interrupt or wait for event instruction, and so wfi
+             * should not be executed again.  However, the original expected idle
+             * time variable must remain unmodified, so a copy is taken. */
+            xModifiableIdleTime = xExpectedIdleTime;
+            configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+
+            if( xModifiableIdleTime > 0 )
+            {
+                __dsb( portSY_FULL_READ_WRITE );
+                __wfi();
+                __isb( portSY_FULL_READ_WRITE );
+            }
+
+            configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+            /* Re-enable interrupts to allow the interrupt that brought the MCU
+             * out of sleep mode to execute immediately.  see comments above
+             * __disable_interrupt() call above. */
+            __enable_irq();
+            __dsb( portSY_FULL_READ_WRITE );
+            __isb( portSY_FULL_READ_WRITE );
+
+            /* Disable interrupts again because the clock is about to be stopped
+             * and interrupts that execute while the clock is stopped will increase
+             * any slippage between the time maintained by the RTOS and calendar
+             * time. */
+            __disable_irq();
+            __dsb( portSY_FULL_READ_WRITE );
+            __isb( portSY_FULL_READ_WRITE );
+
+            /* Disable the SysTick clock without reading the
+             * portNVIC_SYSTICK_CTRL_REG register to ensure the
+             * portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
+             * the time the SysTick is stopped for is accounted for as best it can
+             * be, but using the tickless mode will inevitably result in some tiny
+             * drift of the time maintained by the kernel with respect to calendar
+             * time*/
+            portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
+
+            /* Determine if the SysTick clock has already counted to zero and
+             * been set back to the current reload value (the reload back being
+             * correct for the entire expected idle time) or if the SysTick is yet
+             * to count to zero (in which case an interrupt other than the SysTick
+             * must have brought the system out of sleep mode). */
+            if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+            {
+                uint32_t ulCalculatedLoadValue;
+
+                /* The tick interrupt is already pending, and the SysTick count
+                 * reloaded with ulReloadValue.  Reset the
+                 * portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+                 * period. */
+                ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+                /* Don't allow a tiny value, or values that have somehow
+                 * underflowed because the post sleep hook did something
+                 * that took too long. */
+                if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+                {
+                    ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+                }
+
+                portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+                /* As the pending tick will be processed as soon as this
+                 * function exits, the tick value maintained by the tick is stepped
+                 * forward by one less than the time spent waiting. */
+                ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+            }
+            else
+            {
+                /* Something other than the tick interrupt ended the sleep.
+                 * Work out how long the sleep lasted rounded to complete tick
+                 * periods (not the ulReload value which accounted for part
+                 * ticks). */
+                ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+                /* How many complete tick periods passed while the processor
+                 * was waiting? */
+                ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+                /* The reload value is set to whatever fraction of a single tick
+                 * period remains. */
+                portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+            }
+
+            /* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+             * again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+             * value. */
+            portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+            portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+            vTaskStepTick( ulCompleteTickPeriods );
+            portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+            /* Exit with interrupts enabled. */
+            __enable_irq();
+        }
+    }
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the SysTick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+#if ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
+
+    __weak void vPortSetupTimerInterrupt( void )
+    {
+        /* Calculate the constants required to configure the tick interrupt. */
+        #if ( configUSE_TICKLESS_IDLE == 1 )
+            {
+                ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+                xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+                ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+            }
+        #endif /* configUSE_TICKLESS_IDLE */
+
+        /* Stop and clear the SysTick. */
+        portNVIC_SYSTICK_CTRL_REG = 0UL;
+        portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+        /* Configure SysTick to interrupt at the requested rate. */
+        portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+        portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+    }
+
+#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
+/*-----------------------------------------------------------*/
+
+__asm uint32_t vPortGetIPSR( void )
+{
+/* *INDENT-OFF* */
+    PRESERVE8
+
+    mrs r0, ipsr
+    bx r14
+/* *INDENT-ON* */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configASSERT_DEFINED == 1 )
+
+    void vPortValidateInterruptPriority( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        uint8_t ucCurrentPriority;
+
+        /* Obtain the number of the currently executing interrupt. */
+        ulCurrentInterrupt = vPortGetIPSR();
+
+        /* Is the interrupt number a user defined interrupt? */
+        if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+        {
+            /* Look up the interrupt's priority. */
+            ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+            /* The following assertion will fail if a service routine (ISR) for
+             * an interrupt that has been assigned a priority above
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+             * function.  ISR safe FreeRTOS API functions must *only* be called
+             * from interrupts that have been assigned a priority at or below
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Numerically low interrupt priority numbers represent logically high
+             * interrupt priorities, therefore the priority of the interrupt must
+             * be set to a value equal to or numerically *higher* than
+             * configMAX_SYSCALL_INTERRUPT_PRIORITY.
+             *
+             * Interrupts that	use the FreeRTOS API must not be left at their
+             * default priority of	zero as that is the highest possible priority,
+             * which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+             * and	therefore also guaranteed to be invalid.
+             *
+             * FreeRTOS maintains separate thread and ISR API functions to ensure
+             * interrupt entry is as fast and simple as possible.
+             *
+             * The following links provide detailed information:
+             * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
+             * https://www.FreeRTOS.org/FAQHelp.html */
+            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+        }
+
+        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
+         * that define each interrupt's priority to be split between bits that
+         * define the interrupt's pre-emption priority bits and bits that define
+         * the interrupt's sub-priority.  For simplicity all bits must be defined
+         * to be pre-emption priority bits.  The following assertion will fail if
+         * this is not the case (if some bits represent a sub-priority).
+         *
+         * If the application only uses CMSIS libraries for interrupt
+         * configuration then the correct setting can be achieved on all Cortex-M
+         * devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+         * scheduler.  Note however that some vendor specific peripheral libraries
+         * assume a non-zero priority group setting, in which cases using a value
+         * of zero will result in unpredictable behaviour. */
+        configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+    }
+
+#endif /* configASSERT_DEFINED */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
new file mode 100644
index 0000000..82671b1
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
@@ -0,0 +1,265 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH          ( -1 )
+    #define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT        8
+
+/* Constants used with memory barrier intrinsics. */
+    #define portSY_FULL_READ_WRITE    ( 15 )
+
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+    #define portYIELD()                                 \
+    {                                                   \
+        /* Set a PendSV to request a context switch. */ \
+        portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT; \
+                                                        \
+        /* Barriers are normally not required but do ensure the code is completely \
+         * within the specified behaviour for the architecture. */ \
+        __dsb( portSY_FULL_READ_WRITE );                           \
+        __isb( portSY_FULL_READ_WRITE );                           \
+    }
+/*-----------------------------------------------------------*/
+
+    #define portNVIC_INT_CTRL_REG     ( *( ( volatile uint32_t * ) 0xe000ed04 ) )
+    #define portNVIC_PENDSVSET_BIT    ( 1UL << 28UL )
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired != pdFALSE ) portYIELD()
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+
+    #define portDISABLE_INTERRUPTS()                  vPortRaiseBASEPRI()
+    #define portENABLE_INTERRUPTS()                   vPortSetBASEPRI( 0 )
+    #define portENTER_CRITICAL()                      vPortEnterCritical()
+    #define portEXIT_CRITICAL()                       vPortExitCritical()
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortRaiseBASEPRI()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortSetBASEPRI( x )
+
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+    #ifndef portSUPPRESS_TICKS_AND_SLEEP
+        extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+        #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )    vPortSuppressTicksAndSleep( xExpectedIdleTime )
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Port specific optimisations. */
+    #ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+        #define configUSE_PORT_OPTIMISED_TASK_SELECTION    1
+    #endif
+
+    #if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+/* Check the configuration. */
+        #if ( configMAX_PRIORITIES > 32 )
+            #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+        #endif
+
+/* Store/clear the ready priorities in a bit map. */
+        #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities )    ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+        #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities )     ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+/*-----------------------------------------------------------*/
+
+        #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )    uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
+
+    #endif /* taskRECORD_READY_PRIORITY */
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+ * not necessary for to use this port.  They are defined so the common demo files
+ * (which build with all the ports) will build. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+/*-----------------------------------------------------------*/
+
+    #ifdef configASSERT
+        void vPortValidateInterruptPriority( void );
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    vPortValidateInterruptPriority()
+    #endif
+
+/* portNOP() is not required by this port. */
+    #define portNOP()
+
+    #define portINLINE              __inline
+
+    #ifndef portFORCE_INLINE
+        #define portFORCE_INLINE    __forceinline
+    #endif
+
+/*-----------------------------------------------------------*/
+
+    static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
+    {
+        __asm
+        {
+            /* Barrier instructions are not used as this function is only used to
+             * lower the BASEPRI value. */
+/* *INDENT-OFF* */
+            msr basepri, ulBASEPRI
+/* *INDENT-ON* */
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static portFORCE_INLINE void vPortRaiseBASEPRI( void )
+    {
+        uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+        __asm
+        {
+            /* Set BASEPRI to the max syscall priority to effect a critical
+             * section. */
+/* *INDENT-OFF* */
+            cpsid i
+            msr basepri, ulNewBASEPRI
+            dsb
+            isb
+            cpsie i
+/* *INDENT-ON* */
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
+    {
+        __asm
+        {
+            /* Set BASEPRI to 0 so no interrupts are masked.  This function is only
+             * used to lower the mask in an interrupt, so memory barriers are not
+             * used. */
+/* *INDENT-OFF* */
+            msr basepri, # 0
+/* *INDENT-ON* */
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
+    {
+        uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+        __asm
+        {
+            /* Set BASEPRI to the max syscall priority to effect a critical
+             * section. */
+/* *INDENT-OFF* */
+            mrs ulReturn, basepri
+            cpsid i
+            msr basepri, ulNewBASEPRI
+            dsb
+            isb
+            cpsie i
+/* *INDENT-ON* */
+        }
+
+        return ulReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
+    {
+        uint32_t ulCurrentInterrupt;
+        BaseType_t xReturn;
+
+        /* Obtain the number of the currently executing interrupt. */
+        __asm
+        {
+/* *INDENT-OFF* */
+            mrs ulCurrentInterrupt, ipsr
+/* *INDENT-ON* */
+        }
+
+        if( ulCurrentInterrupt == 0 )
+        {
+            xReturn = pdFALSE;
+        }
+        else
+        {
+            xReturn = pdTRUE;
+        }
+
+        return xReturn;
+    }
+
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX100/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX100/port.c
new file mode 100644
index 0000000..0b8bf8e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX100/port.c
@@ -0,0 +1,646 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the RX100 port.
+ *----------------------------------------------------------*/
+
+/* Standard C includes. */
+#include "limits.h"
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#include "iodefine.h"
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+
+/* The peripheral clock is divided by this value before being supplying the
+CMT. */
+#if ( configUSE_TICKLESS_IDLE == 0 )
+	/* If tickless idle is not used then the divisor can be fixed. */
+	#define portCLOCK_DIVISOR	8UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
+	#define portCLOCK_DIVISOR	512UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
+	#define portCLOCK_DIVISOR	128UL
+#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
+	#define portCLOCK_DIVISOR	32UL
+#else
+	#define portCLOCK_DIVISOR	8UL
+#endif
+
+
+/* Keys required to lock and unlock access to certain system registers
+respectively. */
+#define portUNLOCK_KEY		0xA50B
+#define portLOCK_KEY		0xA500
+
+/*-----------------------------------------------------------*/
+
+/* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
+ and therefore installed in the vector table, when the FreeRTOS code is built
+as a library. */
+extern BaseType_t vSoftwareInterruptEntry;
+const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+static void prvYieldHandler( void );
+
+/*
+ * The entry point for the software interrupt handler.  This is the function
+ * that calls the inline asm function prvYieldHandler().  It is installed in
+ * the vector table, but the code that installs it is in prvYieldHandler rather
+ * than using a #pragma.
+ */
+void vSoftwareInterruptISR( void );
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick using the CMT.
+ * The application writer can define configSETUP_TICK_INTERRUPT() (in
+ * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
+ * in place of prvSetupTimerInterrupt().
+ */
+static void prvSetupTimerInterrupt( void );
+#ifndef configSETUP_TICK_INTERRUPT
+	/* The user has not provided their own tick interrupt configuration so use
+    the definition in this file (which uses the interval timer). */
+	#define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
+#endif /* configSETUP_TICK_INTERRUPT */
+
+/*
+ * Called after the sleep mode registers have been configured, prvSleep()
+ * executes the pre and post sleep macros, and actually calls the wait
+ * instruction.
+ */
+#if configUSE_TICKLESS_IDLE == 1
+	static void prvSleep( TickType_t xExpectedIdleTime );
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*-----------------------------------------------------------*/
+
+/* These is accessed by the inline assembler functions. */
+extern void *pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/*-----------------------------------------------------------*/
+
+/* Calculate how many clock increments make up a single tick period. */
+static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	/* Holds the maximum number of ticks that can be suppressed - which is
+	basically how far into the future an interrupt can be generated. Set
+	during initialisation.  This is the maximum possible value that the
+	compare match register can hold divided by ulMatchValueForOneTick. */
+	static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
+
+	/* Flag set from the tick interrupt to allow the sleep processing to know if
+	sleep mode was exited because of a tick interrupt, or an interrupt
+	generated by something else. */
+	static volatile uint32_t ulTickFlag = pdFALSE;
+
+	/* The CMT counter is stopped temporarily each time it is re-programmed.
+	The following constant offsets the CMT counter match value by the number of
+	CMT	counts that would typically be missed while the counter was stopped to
+	compensate for the lost time.  The large difference between the divided CMT
+	clock and the CPU clock means it is likely ulStoppedTimerCompensation will
+	equal zero - and be optimised away. */
+	static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Offset to end up on 8 byte boundary. */
+	pxTopOfStack--;
+
+	/* R0 is not included as it is the stack pointer. */
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+    *pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0x12345678;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaabbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		/* Leave space for the registers that will get popped from the stack
+		when the task first starts executing. */
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x12345678; /* Accumulator. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x87654321; /* Accumulator. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate
+		the tick interrupt.  This way the application can decide which
+		peripheral to use.  If tickless mode is used then the default
+		implementation defined in this file (which uses CMT0) should not be
+		overridden. */
+		configSETUP_TICK_INTERRUPT();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Execution should not reach here as the tasks are now running!
+	prvSetupTimerInterrupt() is called here to prevent the compiler outputting
+	a warning about a statically declared function not being referenced in the
+	case that the application writer has provided their own tick interrupt
+	configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
+	their own routine will be called in place of prvSetupTimerInterrupt()). */
+	prvSetupTimerInterrupt();
+
+	/* Just to make sure the function is not optimised away. */
+	( void ) vSoftwareInterruptISR();
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvStartFirstTask
+static void prvStartFirstTask( void )
+{
+	/* When starting the scheduler there is nothing that needs moving to the
+	interrupt stack because the function is not called from an interrupt.
+	Just ensure the current stack is the user stack. */
+	SETPSW	U
+
+	/* Obtain the location of the stack associated with which ever task
+	pxCurrentTCB is currently pointing to. */
+	MOV.L	#_pxCurrentTCB, R15
+	MOV.L	[R15], R15
+	MOV.L	[R15], R0
+
+	/* Restore the registers from the stack of the task pointed to by
+	pxCurrentTCB. */
+    POP		R15
+    MVTACLO	R15 		/* Accumulator low 32 bits. */
+    POP		R15
+    MVTACHI	R15 		/* Accumulator high 32 bits. */
+    POPM	R1-R15 		/* R1 to R15 - R0 is not included as it is the SP. */
+    RTE					/* This pops the remaining registers. */
+    NOP
+    NOP
+}
+/*-----------------------------------------------------------*/
+
+#pragma interrupt ( prvTickISR( vect = _VECT( configTICK_VECTOR ), enable ) )
+void prvTickISR( void )
+{
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates. */
+	set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	set_ipl( configKERNEL_INTERRUPT_PRIORITY );
+
+	#if configUSE_TICKLESS_IDLE == 1
+	{
+		/* The CPU woke because of a tick. */
+		ulTickFlag = pdTRUE;
+
+		/* If this is the first tick since exiting tickless mode then the CMT
+		compare match value needs resetting. */
+		CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+	}
+	#endif
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+	prvYieldHandler();
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvYieldHandler
+static void prvYieldHandler( void )
+{
+	/* Re-enable interrupts. */
+	SETPSW	I
+
+	/* Move the data that was automatically pushed onto the interrupt stack
+	when the interrupt occurred from the interrupt stack to the user stack.
+
+	R15 is saved before it is clobbered. */
+	PUSH.L	R15
+
+	/* Read the user stack pointer. */
+	MVFC	USP, R15
+
+	/* Move the address down to the data being moved. */
+	SUB		#12, R15
+	MVTC	R15, USP
+
+	/* Copy the data across. */
+	MOV.L	[ R0 ], [ R15 ] ; R15
+	MOV.L 	4[ R0 ], 4[ R15 ]  ; PC
+	MOV.L	8[ R0 ], 8[ R15 ]  ; PSW
+
+	/* Move the interrupt stack pointer to its new correct position. */
+	ADD	#12, R0
+
+	/* All the rest of the registers are saved directly to the user stack. */
+	SETPSW	U
+
+	/* Save the rest of the general registers (R15 has been saved already). */
+	PUSHM	R1-R14
+
+	/* Save the accumulator. */
+	MVFACHI	R15
+	PUSH.L	R15
+	MVFACMI	R15	; Middle order word.
+	SHLL	#16, R15 ; Shifted left as it is restored to the low order word.
+	PUSH.L	R15
+
+	/* Save the stack pointer to the TCB. */
+	MOV.L	#_pxCurrentTCB, R15
+	MOV.L	[ R15 ], R15
+	MOV.L	R0, [ R15 ]
+
+	/* Ensure the interrupt mask is set to the syscall priority while the
+	kernel structures are being accessed. */
+	MVTIPL	#configMAX_SYSCALL_INTERRUPT_PRIORITY
+
+	/* Select the next task to run. */
+	BSR.A	_vTaskSwitchContext
+
+	/* Reset the interrupt mask as no more data structure access is
+	required. */
+	MVTIPL	#configKERNEL_INTERRUPT_PRIORITY
+
+	/* Load the stack pointer of the task that is now selected as the Running
+	state task from its TCB. */
+	MOV.L	#_pxCurrentTCB,R15
+	MOV.L	[ R15 ], R15
+	MOV.L	[ R15 ], R0
+
+	/* Restore the context of the new task.  The PSW (Program Status Word) and
+	PC will be popped by the RTE instruction. */
+	POP		R15
+	MVTACLO	R15
+	POP		R15
+	MVTACHI	R15
+	POPM	R1-R15
+	RTE
+	NOP
+	NOP
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+
+	/* The following line is just to prevent the symbol getting optimised away. */
+	( void ) vTaskSwitchContext();
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+	/* Unlock. */
+	SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+	/* Enable CMT0. */
+	MSTP( CMT0 ) = 0;
+
+	/* Lock again. */
+	SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+	/* Interrupt on compare match. */
+	CMT0.CMCR.BIT.CMIE = 1;
+
+	/* Set the compare match value. */
+	CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
+
+	/* Divide the PCLK. */
+	#if portCLOCK_DIVISOR == 512
+	{
+		CMT0.CMCR.BIT.CKS = 3;
+	}
+	#elif portCLOCK_DIVISOR == 128
+	{
+		CMT0.CMCR.BIT.CKS = 2;
+	}
+	#elif portCLOCK_DIVISOR == 32
+	{
+		CMT0.CMCR.BIT.CKS = 1;
+	}
+	#elif portCLOCK_DIVISOR == 8
+	{
+		CMT0.CMCR.BIT.CKS = 0;
+	}
+	#else
+	{
+		#error Invalid portCLOCK_DIVISOR setting
+	}
+	#endif
+
+
+	/* Enable the interrupt... */
+	_IEN( _CMT0_CMI0 ) = 1;
+
+	/* ...and set its priority to the application defined kernel priority. */
+	_IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
+
+	/* Start the timer. */
+	CMT.CMSTR0.BIT.STR0 = 1;
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	static void prvSleep( TickType_t xExpectedIdleTime )
+	{
+		/* Allow the application to define some pre-sleep processing. */
+		configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
+
+		/* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
+		means the application defined code has already executed the WAIT
+		instruction. */
+		if( xExpectedIdleTime > 0 )
+		{
+			wait();
+		}
+
+		/* Allow the application to define some post sleep processing. */
+		configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
+	eSleepModeStatus eSleepAction;
+
+		/* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
+
+		/* Make sure the CMT reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Calculate the reload value required to wait xExpectedIdleTime tick
+		periods. */
+		ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
+		if( ulMatchValue > ulStoppedTimerCompensation )
+		{
+			/* Compensate for the fact that the CMT is going to be stopped
+			momentarily. */
+			ulMatchValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Stop the CMT momentarily.  The time the CMT is stopped for is
+		accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		CMT.CMSTR0.BIT.STR0 = 0;
+		while( CMT.CMSTR0.BIT.STR0 == 1 )
+		{
+			/* Nothing to do here. */
+		}
+
+		/* Critical section using the global interrupt bit as the i bit is
+		automatically reset by the WAIT instruction. */
+		clrpsw_i();
+
+		/* The tick flag is set to false before sleeping.  If it is true when
+		sleep mode is exited then sleep mode was probably exited because the
+		tick was suppressed for the entire xExpectedIdleTime period. */
+		ulTickFlag = pdFALSE;
+
+		/* If a context switch is pending then abandon the low power entry as
+		the context switch might have been pended by an external interrupt that
+		requires processing. */
+		eSleepAction = eTaskConfirmSleepModeStatus();
+		if( eSleepAction == eAbortSleep )
+		{
+			/* Restart tick. */
+			CMT.CMSTR0.BIT.STR0 = 1;
+			setpsw_i();
+		}
+		else if( eSleepAction == eNoTasksWaitingTimeout )
+		{
+		    /* Protection off. */
+		    SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+		    /* Ready for software standby with all clocks stopped. */
+			SYSTEM.SBYCR.BIT.SSBY = 1;
+
+		    /* Protection on. */
+		    SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+			/* Sleep until something happens.  Calling prvSleep() will
+			automatically reset the i bit in the PSW. */
+			prvSleep( xExpectedIdleTime );
+
+			/* Restart the CMT. */
+			CMT.CMSTR0.BIT.STR0 = 1;
+		}
+		else
+		{
+		    /* Protection off. */
+		    SYSTEM.PRCR.WORD = portUNLOCK_KEY;
+
+		    /* Ready for deep sleep mode. */
+			SYSTEM.MSTPCRC.BIT.DSLPE = 1;
+			SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
+			SYSTEM.SBYCR.BIT.SSBY = 0;
+
+		    /* Protection on. */
+		    SYSTEM.PRCR.WORD = portLOCK_KEY;
+
+		    /* Adjust the match value to take into account that the current
+			time slice is already partially complete. */
+			ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
+			CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+
+			/* Restart the CMT to count up to the new match value. */
+			CMT0.CMCNT = 0;
+			CMT.CMSTR0.BIT.STR0 = 1;
+
+			/* Sleep until something happens.  Calling prvSleep() will
+			automatically reset the i bit in the PSW. */
+			prvSleep( xExpectedIdleTime );
+
+			/* Stop CMT.  Again, the time the SysTick is stopped for is
+			accounted for as best it can be, but using the tickless mode will
+			inevitably result in some tiny drift of the time maintained by the
+			kernel with	respect to calendar time. */
+			CMT.CMSTR0.BIT.STR0 = 0;
+			while( CMT.CMSTR0.BIT.STR0 == 1 )
+			{
+				/* Nothing to do here. */
+			}
+
+			ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
+
+			if( ulTickFlag != pdFALSE )
+			{
+				/* The tick interrupt has already executed, although because
+				this function is called with the scheduler suspended the actual
+				tick processing will not occur until after this function has
+				exited.  Reset the match value with whatever remains of this
+				tick period. */
+				ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
+				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+
+				/* The tick interrupt handler will already have pended the tick
+				processing in the kernel.  As the pending tick will be
+				processed as soon as this function exits, the tick value
+				maintained by the tick is stepped forward by one less than the
+				time spent sleeping.  The actual stepping of the tick appears
+				later in this function. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				How	many complete tick periods passed while the processor was
+				sleeping? */
+				ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
+
+				/* The match value is set to whatever fraction of a single tick
+				period remains. */
+				ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
+				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
+			}
+
+			/* Restart the CMT so it runs up to the match value.  The match value
+			will get set to the value required to generate exactly one tick period
+			the next time the CMT interrupt executes. */
+			CMT0.CMCNT = 0;
+			CMT.CMSTR0.BIT.STR0 = 1;
+
+			/* Wind the tick forward by the number of tick periods that the CPU
+			remained in a low power state. */
+			vTaskStepTick( ulCompleteTickPeriods );
+		}
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX100/port_asm.src b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX100/port_asm.src
new file mode 100644
index 0000000..05631c9
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX100/port_asm.src
@@ -0,0 +1,41 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+		.GLB	_vSoftwareInterruptISR
+                .GLB    _vSoftwareInterruptEntry
+
+		.SECTION   P,CODE
+
+_vSoftwareInterruptEntry:
+
+	BRA	_vSoftwareInterruptISR
+
+		.RVECTOR	27, _vSoftwareInterruptEntry
+
+		.END
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX100/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX100/portmacro.h
new file mode 100644
index 0000000..b0fdcf9
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX100/portmacro.h
@@ -0,0 +1,151 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Hardware specifics. */
+#include "machine.h"
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other
+than portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT				8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH				-1
+#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()						nop()
+
+#pragma inline_asm vPortYield
+static void vPortYield( void )
+{
+	/* Save clobbered register - may not actually be necessary if inline asm
+	functions are considered to use the same rules as function calls by the
+	compiler. */
+	PUSH.L R5
+	/* Set ITU SWINTR. */
+	MOV.L #872E0H, R5
+	MOV.B #1, [R5]
+	/* Read back to ensure the value is taken before proceeding. */
+	MOV.L [R5], R5
+	/* Restore clobbered register to its previous value. */
+	POP R5
+}
+#define portYIELD()	vPortYield()
+#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) { portYIELD(); }
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	set_ipl( ( long ) 0 )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+	#define portDISABLE_INTERRUPTS() 	set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( signed long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( signed long ) uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#if configUSE_TICKLESS_IDLE == 1
+	#ifndef portSUPPRESS_TICKS_AND_SLEEP
+		extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+		#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+	#endif
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX100/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX100/readme.txt
new file mode 100644
index 0000000..9e89a09
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX100/readme.txt
@@ -0,0 +1,72 @@
+The following table shows which port is recommended to be used.
+
+
+RX MCU Group    CPU     FPU         FPU         Port Layer
+                Core    (Single     (Double     CC-RX                   GNURX               ICCRX (*6)
+                Type    Precision)  Precision)
+
+RX110           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX111           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX113           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX130           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX13T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+
+RX210           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX21A           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX220           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX230,RX231     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23E-A         RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23W           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24U           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+
+RX610           RXv1    Yes         ---         N/A (*4)                N/A (*4)            N/A (*4)
+RX62N,RX621     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX630           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX634           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63N,RX631     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX64M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX65N,RX651     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX66N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX62T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX62G           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX66T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+RX71M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX72M           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+Notes:
+
+*1: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide
+the configuration function.  Please be aware that port.c is hard coded to use CMT0 though it seems to be
+configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*2: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is used, please modify port.c for the configuration.  Please be aware that port.c is
+hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of
+configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*3: RX100 ports are also available.
+
+*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction.
+
+*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
+
+#define configUSE_TASK_DPFPU_SUPPORT            0
+
+*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port.
+It contains two definitions of interrupt priority like the following.
+
+#define configKERNEL_INTERRUPT_PRIORITY         1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY    4
+
+
+For more information about Renesas RX MCUs, please visit the following URL:
+
+https://www.renesas.com/products/microcontrollers-microprocessors/rx.html
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX200/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX200/port.c
new file mode 100644
index 0000000..7762372
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX200/port.c
@@ -0,0 +1,324 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the RX200 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#include "iodefine.h"
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+
+/*-----------------------------------------------------------*/
+
+/* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
+ and therefore installed in the vector table, when the FreeRTOS code is built
+as a library. */
+extern BaseType_t vSoftwareInterruptEntry;
+const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+static void prvYieldHandler( void );
+
+/*
+ * The entry point for the software interrupt handler.  This is the function
+ * that calls the inline asm function prvYieldHandler().  It is installed in
+ * the vector table, but the code that installs it is in prvYieldHandler rather
+ * than using a #pragma.
+ */
+void vSoftwareInterruptISR( void );
+
+/*-----------------------------------------------------------*/
+
+/* This is accessed by the inline assembler functions so is file scope for
+convenience. */
+extern void *pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Offset to end up on 8 byte boundary. */
+	pxTopOfStack--;
+
+	/* R0 is not included as it is the stack pointer. */
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+    *pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0x12345678;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaabbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x12345678; /* Accumulator. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x87654321; /* Accumulator. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate the
+		tick interrupt.  This way the application can decide which peripheral to
+		use.  A demo application is provided to show a suitable example. */
+		vApplicationSetupTimerInterrupt();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Just to make sure the function is not optimised away. */
+	( void ) vSoftwareInterruptISR();
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvStartFirstTask
+static void prvStartFirstTask( void )
+{
+	/* When starting the scheduler there is nothing that needs moving to the
+	interrupt stack because the function is not called from an interrupt.
+	Just ensure the current stack is the user stack. */
+	SETPSW	U
+
+	/* Obtain the location of the stack associated with which ever task
+	pxCurrentTCB is currently pointing to. */
+	MOV.L	#_pxCurrentTCB, R15
+	MOV.L	[R15], R15
+	MOV.L	[R15], R0
+
+	/* Restore the registers from the stack of the task pointed to by
+	pxCurrentTCB. */
+    POP		R15
+    MVTACLO	R15 		/* Accumulator low 32 bits. */
+    POP		R15
+    MVTACHI	R15 		/* Accumulator high 32 bits. */
+    POPM	R1-R15 		/* R1 to R15 - R0 is not included as it is the SP. */
+    RTE					/* This pops the remaining registers. */
+    NOP
+    NOP
+}
+/*-----------------------------------------------------------*/
+
+#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) )
+void vTickISR( void )
+{
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates. */
+	set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	set_ipl( configKERNEL_INTERRUPT_PRIORITY );
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+	prvYieldHandler();
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvYieldHandler
+static void prvYieldHandler( void )
+{
+	/* Re-enable interrupts. */
+	SETPSW	I
+
+	/* Move the data that was automatically pushed onto the interrupt stack when
+	the interrupt occurred from the interrupt stack to the user stack.
+
+	R15 is saved before it is clobbered. */
+	PUSH.L	R15
+
+	/* Read the user stack pointer. */
+	MVFC	USP, R15
+
+	/* Move the address down to the data being moved. */
+	SUB		#12, R15
+	MVTC	R15, USP
+
+	/* Copy the data across. */
+	MOV.L	[ R0 ], [ R15 ] ; R15
+	MOV.L 	4[ R0 ], 4[ R15 ]  ; PC
+	MOV.L	8[ R0 ], 8[ R15 ]  ; PSW
+
+	/* Move the interrupt stack pointer to its new correct position. */
+	ADD	#12, R0
+
+	/* All the rest of the registers are saved directly to the user stack. */
+	SETPSW	U
+
+	/* Save the rest of the general registers (R15 has been saved already). */
+	PUSHM	R1-R14
+
+	/* Save the accumulator. */
+	MVFACHI	R15
+	PUSH.L	R15
+	MVFACMI	R15	; Middle order word.
+	SHLL	#16, R15 ; Shifted left as it is restored to the low order word.
+	PUSH.L	R15
+
+	/* Save the stack pointer to the TCB. */
+	MOV.L	#_pxCurrentTCB, R15
+	MOV.L	[ R15 ], R15
+	MOV.L	R0, [ R15 ]
+
+	/* Ensure the interrupt mask is set to the syscall priority while the kernel
+	structures are being accessed. */
+	MVTIPL	#configMAX_SYSCALL_INTERRUPT_PRIORITY
+
+	/* Select the next task to run. */
+	BSR.A	_vTaskSwitchContext
+
+	/* Reset the interrupt mask as no more data structure access is required. */
+	MVTIPL	#configKERNEL_INTERRUPT_PRIORITY
+
+	/* Load the stack pointer of the task that is now selected as the Running
+	state task from its TCB. */
+	MOV.L	#_pxCurrentTCB,R15
+	MOV.L	[ R15 ], R15
+	MOV.L	[ R15 ], R0
+
+	/* Restore the context of the new task.  The PSW (Program Status Word) and
+	PC will be popped by the RTE instruction. */
+	POP		R15
+	MVTACLO	R15
+	POP		R15
+	MVTACHI	R15
+	POPM	R1-R15
+	RTE
+	NOP
+	NOP
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+
+	/* The following line is just to prevent the symbol getting optimised away. */
+	( void ) vTaskSwitchContext();
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX200/port_asm.src b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX200/port_asm.src
new file mode 100644
index 0000000..05631c9
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX200/port_asm.src
@@ -0,0 +1,41 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+		.GLB	_vSoftwareInterruptISR
+                .GLB    _vSoftwareInterruptEntry
+
+		.SECTION   P,CODE
+
+_vSoftwareInterruptEntry:
+
+	BRA	_vSoftwareInterruptISR
+
+		.RVECTOR	27, _vSoftwareInterruptEntry
+
+		.END
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX200/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX200/portmacro.h
new file mode 100644
index 0000000..17bcf60
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX200/portmacro.h
@@ -0,0 +1,141 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Hardware specifics. */
+#include "machine.h"
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT				8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH				-1
+#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()						nop()
+
+#pragma inline_asm vPortYield
+static void vPortYield( void )
+{
+	/* Save clobbered register - may not actually be necessary if inline asm
+	functions are considered to use the same rules as function calls by the
+	compiler. */
+	PUSH.L R5
+	/* Set ITU SWINTR. */
+	MOV.L #553696, R5
+	MOV.B #1, [R5]
+	/* Read back to ensure the value is taken before proceeding. */
+	MOV.L [R5], R5
+	/* Restore clobbered register to its previous value. */
+	POP R5
+}
+#define portYIELD()	vPortYield()
+#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) portYIELD()
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	set_ipl( ( long ) 0 )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+	#define portDISABLE_INTERRUPTS() 	set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+#define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX200/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX200/readme.txt
new file mode 100644
index 0000000..9e89a09
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX200/readme.txt
@@ -0,0 +1,72 @@
+The following table shows which port is recommended to be used.
+
+
+RX MCU Group    CPU     FPU         FPU         Port Layer
+                Core    (Single     (Double     CC-RX                   GNURX               ICCRX (*6)
+                Type    Precision)  Precision)
+
+RX110           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX111           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX113           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX130           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX13T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+
+RX210           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX21A           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX220           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX230,RX231     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23E-A         RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23W           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24U           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+
+RX610           RXv1    Yes         ---         N/A (*4)                N/A (*4)            N/A (*4)
+RX62N,RX621     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX630           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX634           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63N,RX631     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX64M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX65N,RX651     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX66N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX62T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX62G           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX66T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+RX71M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX72M           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+Notes:
+
+*1: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide
+the configuration function.  Please be aware that port.c is hard coded to use CMT0 though it seems to be
+configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*2: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is used, please modify port.c for the configuration.  Please be aware that port.c is
+hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of
+configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*3: RX100 ports are also available.
+
+*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction.
+
+*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
+
+#define configUSE_TASK_DPFPU_SUPPORT            0
+
+*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port.
+It contains two definitions of interrupt priority like the following.
+
+#define configKERNEL_INTERRUPT_PRIORITY         1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY    4
+
+
+For more information about Renesas RX MCUs, please visit the following URL:
+
+https://www.renesas.com/products/microcontrollers-microprocessors/rx.html
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600/port.c
new file mode 100644
index 0000000..de7a557
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600/port.c
@@ -0,0 +1,329 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the RX600 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#include "iodefine.h"
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
+
+/*-----------------------------------------------------------*/
+
+/* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
+ and therefore installed in the vector table, when the FreeRTOS code is built
+as a library. */
+extern BaseType_t vSoftwareInterruptEntry;
+const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+static void prvYieldHandler( void );
+
+/*
+ * The entry point for the software interrupt handler.  This is the function
+ * that calls the inline asm function prvYieldHandler().  It is installed in
+ * the vector table, but the code that installs it is in prvYieldHandler rather
+ * than using a #pragma.
+ */
+void vSoftwareInterruptISR( void );
+
+/*-----------------------------------------------------------*/
+
+/* This is accessed by the inline assembler functions so is file scope for
+convenience. */
+extern void *pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* R0 is not included as it is the stack pointer. */
+
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0xffffffff;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xeeeeeeee;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_FPSW;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x12345678; /* Accumulator. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x87654321; /* Accumulator. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate the
+		tick interrupt.  This way the application can decide which peripheral to
+		use.  A demo application is provided to show a suitable example. */
+		vApplicationSetupTimerInterrupt();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Just to make sure the function is not optimised away. */
+	( void ) vSoftwareInterruptISR();
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvStartFirstTask
+static void prvStartFirstTask( void )
+{
+	/* When starting the scheduler there is nothing that needs moving to the
+	interrupt stack because the function is not called from an interrupt.
+	Just ensure the current stack is the user stack. */
+	SETPSW	U
+
+	/* Obtain the location of the stack associated with which ever task
+	pxCurrentTCB is currently pointing to. */
+	MOV.L	#_pxCurrentTCB, R15
+	MOV.L	[R15], R15
+	MOV.L	[R15], R0
+
+	/* Restore the registers from the stack of the task pointed to by
+	pxCurrentTCB. */
+    POP		R15
+    MVTACLO	R15 		/* Accumulator low 32 bits. */
+    POP		R15
+    MVTACHI	R15 		/* Accumulator high 32 bits. */
+    POP		R15
+    MVTC	R15,FPSW 	/* Floating point status word. */
+    POPM	R1-R15 		/* R1 to R15 - R0 is not included as it is the SP. */
+    RTE					/* This pops the remaining registers. */
+    NOP
+    NOP
+}
+/*-----------------------------------------------------------*/
+
+#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) )
+void vTickISR( void )
+{
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates. */
+	set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	set_ipl( configKERNEL_INTERRUPT_PRIORITY );
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+	prvYieldHandler();
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvYieldHandler
+static void prvYieldHandler( void )
+{
+	/* Re-enable interrupts. */
+	SETPSW	I
+
+	/* Move the data that was automatically pushed onto the interrupt stack when
+	the interrupt occurred from the interrupt stack to the user stack.
+
+	R15 is saved before it is clobbered. */
+	PUSH.L	R15
+
+	/* Read the user stack pointer. */
+	MVFC	USP, R15
+
+	/* Move the address down to the data being moved. */
+	SUB		#12, R15
+	MVTC	R15, USP
+
+	/* Copy the data across. */
+	MOV.L	[ R0 ], [ R15 ] ; R15
+	MOV.L 	4[ R0 ], 4[ R15 ]  ; PC
+	MOV.L	8[ R0 ], 8[ R15 ]  ; PSW
+
+	/* Move the interrupt stack pointer to its new correct position. */
+	ADD	#12, R0
+
+	/* All the rest of the registers are saved directly to the user stack. */
+	SETPSW	U
+
+	/* Save the rest of the general registers (R15 has been saved already). */
+	PUSHM	R1-R14
+
+	/* Save the FPSW and accumulator. */
+	MVFC	FPSW, R15
+	PUSH.L	R15
+	MVFACHI	R15
+	PUSH.L	R15
+	MVFACMI	R15	; Middle order word.
+	SHLL	#16, R15 ; Shifted left as it is restored to the low order word.
+	PUSH.L	R15
+
+	/* Save the stack pointer to the TCB. */
+	MOV.L	#_pxCurrentTCB, R15
+	MOV.L	[ R15 ], R15
+	MOV.L	R0, [ R15 ]
+
+	/* Ensure the interrupt mask is set to the syscall priority while the kernel
+	structures are being accessed. */
+	MVTIPL	#configMAX_SYSCALL_INTERRUPT_PRIORITY
+
+	/* Select the next task to run. */
+	BSR.A	_vTaskSwitchContext
+
+	/* Reset the interrupt mask as no more data structure access is required. */
+	MVTIPL	#configKERNEL_INTERRUPT_PRIORITY
+
+	/* Load the stack pointer of the task that is now selected as the Running
+	state task from its TCB. */
+	MOV.L	#_pxCurrentTCB,R15
+	MOV.L	[ R15 ], R15
+	MOV.L	[ R15 ], R0
+
+	/* Restore the context of the new task.  The PSW (Program Status Word) and
+	PC will be popped by the RTE instruction. */
+	POP		R15
+	MVTACLO	R15
+	POP		R15
+	MVTACHI	R15
+	POP		R15
+	MVTC	R15,FPSW
+	POPM	R1-R15
+	RTE
+	NOP
+	NOP
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+
+	/* The following line is just to prevent the symbol getting optimised away. */
+	( void ) vTaskSwitchContext();
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600/port_asm.src b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600/port_asm.src
new file mode 100644
index 0000000..05631c9
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600/port_asm.src
@@ -0,0 +1,41 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+		.GLB	_vSoftwareInterruptISR
+                .GLB    _vSoftwareInterruptEntry
+
+		.SECTION   P,CODE
+
+_vSoftwareInterruptEntry:
+
+	BRA	_vSoftwareInterruptISR
+
+		.RVECTOR	27, _vSoftwareInterruptEntry
+
+		.END
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600/portmacro.h
new file mode 100644
index 0000000..2e49aa5
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600/portmacro.h
@@ -0,0 +1,142 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Hardware specifics. */
+#include "machine.h"
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT				8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH				-1
+#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()						nop()
+
+
+#pragma inline_asm vPortYield
+static void vPortYield( void )
+{
+	/* Save clobbered register - may not actually be necessary if inline asm
+	functions are considered to use the same rules as function calls by the
+	compiler. */
+	PUSH.L R5
+	/* Set ITU SWINTR. */
+	MOV.L #553696, R5
+	MOV.B #1, [R5]
+	/* Read back to ensure the value is taken before proceeding. */
+	MOV.L [R5], R5
+	/* Restore clobbered register to its previous value. */
+	POP R5
+}
+#define portYIELD()	vPortYield()
+#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) portYIELD()
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	set_ipl( ( long ) 0 )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+	#define portDISABLE_INTERRUPTS() 	set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+#define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600/readme.txt
new file mode 100644
index 0000000..9e89a09
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600/readme.txt
@@ -0,0 +1,72 @@
+The following table shows which port is recommended to be used.
+
+
+RX MCU Group    CPU     FPU         FPU         Port Layer
+                Core    (Single     (Double     CC-RX                   GNURX               ICCRX (*6)
+                Type    Precision)  Precision)
+
+RX110           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX111           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX113           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX130           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX13T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+
+RX210           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX21A           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX220           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX230,RX231     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23E-A         RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23W           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24U           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+
+RX610           RXv1    Yes         ---         N/A (*4)                N/A (*4)            N/A (*4)
+RX62N,RX621     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX630           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX634           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63N,RX631     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX64M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX65N,RX651     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX66N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX62T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX62G           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX66T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+RX71M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX72M           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+Notes:
+
+*1: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide
+the configuration function.  Please be aware that port.c is hard coded to use CMT0 though it seems to be
+configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*2: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is used, please modify port.c for the configuration.  Please be aware that port.c is
+hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of
+configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*3: RX100 ports are also available.
+
+*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction.
+
+*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
+
+#define configUSE_TASK_DPFPU_SUPPORT            0
+
+*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port.
+It contains two definitions of interrupt priority like the following.
+
+#define configKERNEL_INTERRUPT_PRIORITY         1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY    4
+
+
+For more information about Renesas RX MCUs, please visit the following URL:
+
+https://www.renesas.com/products/microcontrollers-microprocessors/rx.html
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600v2/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600v2/port.c
new file mode 100644
index 0000000..16a7d8a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600v2/port.c
@@ -0,0 +1,364 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the RX600 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#if defined( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H ) && ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+	#include "platform.h"
+#else
+	#include "iodefine.h"
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
+
+/*-----------------------------------------------------------*/
+
+/* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
+ and therefore installed in the vector table, when the FreeRTOS code is built
+as a library. */
+extern BaseType_t vSoftwareInterruptEntry;
+const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+static void prvYieldHandler( void );
+
+/*
+ * The entry point for the software interrupt handler.  This is the function
+ * that calls the inline asm function prvYieldHandler().  It is installed in
+ * the vector table, but the code that installs it is in prvYieldHandler rather
+ * than using a #pragma.
+ */
+void vSoftwareInterruptISR( void );
+
+/*-----------------------------------------------------------*/
+
+/* This is accessed by the inline assembler functions so is file scope for
+convenience. */
+extern void *pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* R0 is not included as it is the stack pointer. */
+
+	*pxTopOfStack = 0x00;
+	pxTopOfStack--;
+ 	*pxTopOfStack = portINITIAL_PSW;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) pxCode;
+
+	/* When debugging it can be useful if every register is set to a known
+	value.  Otherwise code space can be saved by just setting the registers
+	that need to be set. */
+	#ifdef USE_FULL_REGISTER_INITIALISATION
+	{
+		pxTopOfStack--;
+		*pxTopOfStack = 0xffffffff;	/* r15. */
+		pxTopOfStack--;
+		*pxTopOfStack = 0xeeeeeeee;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xdddddddd;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xcccccccc;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xbbbbbbbb;
+		pxTopOfStack--;
+		*pxTopOfStack = 0xaaaaaaaa;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x99999999;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x88888888;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x77777777;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x66666666;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x55555555;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x44444444;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x33333333;
+		pxTopOfStack--;
+		*pxTopOfStack = 0x22222222;
+		pxTopOfStack--;
+	}
+	#else
+	{
+		pxTopOfStack -= 15;
+	}
+	#endif
+
+	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = portINITIAL_FPSW;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x11111111; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22222222; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33333333; /* Accumulator 0. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x44444444; /* Accumulator 1. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x55555555; /* Accumulator 1. */
+	pxTopOfStack--;
+	*pxTopOfStack = 0x66666666; /* Accumulator 1. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+	/* Use pxCurrentTCB just so it does not get optimised away. */
+	if( pxCurrentTCB != NULL )
+	{
+		/* Call an application function to set up the timer that will generate the
+		tick interrupt.  This way the application can decide which peripheral to
+		use.  A demo application is provided to show a suitable example. */
+		vApplicationSetupTimerInterrupt();
+
+		/* Enable the software interrupt. */
+		_IEN( _ICU_SWINT ) = 1;
+
+		/* Ensure the software interrupt is clear. */
+		_IR( _ICU_SWINT ) = 0;
+
+		/* Ensure the software interrupt is set to the kernel priority. */
+		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+		/* Start the first task. */
+		prvStartFirstTask();
+	}
+
+	/* Just to make sure the function is not optimised away. */
+	( void ) vSoftwareInterruptISR();
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvStartFirstTask
+static void prvStartFirstTask( void )
+{
+	/* When starting the scheduler there is nothing that needs moving to the
+	interrupt stack because the function is not called from an interrupt.
+	Just ensure the current stack is the user stack. */
+	SETPSW	U
+
+	/* Obtain the location of the stack associated with which ever task
+	pxCurrentTCB is currently pointing to. */
+	MOV.L	#_pxCurrentTCB, R15
+	MOV.L	[R15], R15
+	MOV.L	[R15], R0
+
+	/* Restore the registers from the stack of the task pointed to by
+	pxCurrentTCB. */
+    POP		R15
+    MVTACLO	R15, A0		/* Accumulator low 32 bits. */
+    POP		R15
+    MVTACHI	R15, A0		/* Accumulator high 32 bits. */
+    POP		R15
+    MVTACGU	R15, A0		/* Accumulator guard. */
+    POP		R15
+    MVTACLO	R15, A1		/* Accumulator low 32 bits. */
+    POP		R15
+    MVTACHI	R15, A1		/* Accumulator high 32 bits. */
+    POP		R15
+    MVTACGU	R15, A1		/* Accumulator guard. */
+    POP		R15
+    MVTC	R15,FPSW 	/* Floating point status word. */
+    POPM	R1-R15 		/* R1 to R15 - R0 is not included as it is the SP. */
+    RTE					/* This pops the remaining registers. */
+    NOP
+    NOP
+}
+/*-----------------------------------------------------------*/
+
+#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) )
+void vTickISR( void )
+{
+	/* Increment the tick, and perform any processing the new tick value
+	necessitates. */
+	set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+	{
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			taskYIELD();
+		}
+	}
+	set_ipl( configKERNEL_INTERRUPT_PRIORITY );
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+	prvYieldHandler();
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvYieldHandler
+static void prvYieldHandler( void )
+{
+	/* Re-enable interrupts. */
+	SETPSW	I
+
+	/* Move the data that was automatically pushed onto the interrupt stack when
+	the interrupt occurred from the interrupt stack to the user stack.
+
+	R15 is saved before it is clobbered. */
+	PUSH.L	R15
+
+	/* Read the user stack pointer. */
+	MVFC	USP, R15
+
+	/* Move the address down to the data being moved. */
+	SUB		#12, R15
+	MVTC	R15, USP
+
+	/* Copy the data across. */
+	MOV.L	[ R0 ], [ R15 ] ; R15
+	MOV.L 	4[ R0 ], 4[ R15 ]  ; PC
+	MOV.L	8[ R0 ], 8[ R15 ]  ; PSW
+
+	/* Move the interrupt stack pointer to its new correct position. */
+	ADD	#12, R0
+
+	/* All the rest of the registers are saved directly to the user stack. */
+	SETPSW	U
+
+	/* Save the rest of the general registers (R15 has been saved already). */
+	PUSHM	R1-R14
+
+	/* Save the FPSW and accumulators. */
+	MVFC	FPSW, R15
+	PUSH.L	R15
+	MVFACGU	#0, A1, R15
+	PUSH.L	R15
+	MVFACHI	#0, A1, R15
+	PUSH.L	R15
+	MVFACLO	#0, A1, R15	; Low order word.
+	PUSH.L	R15
+	MVFACGU	#0, A0, R15
+	PUSH.L	R15
+	MVFACHI	#0, A0, R15
+	PUSH.L	R15
+	MVFACLO	#0, A0, R15	; Low order word.
+	PUSH.L	R15
+
+	/* Save the stack pointer to the TCB. */
+	MOV.L	#_pxCurrentTCB, R15
+	MOV.L	[ R15 ], R15
+	MOV.L	R0, [ R15 ]
+
+	/* Ensure the interrupt mask is set to the syscall priority while the kernel
+	structures are being accessed. */
+	MVTIPL	#configMAX_SYSCALL_INTERRUPT_PRIORITY
+
+	/* Select the next task to run. */
+	BSR.A	_vTaskSwitchContext
+
+	/* Reset the interrupt mask as no more data structure access is required. */
+	MVTIPL	#configKERNEL_INTERRUPT_PRIORITY
+
+	/* Load the stack pointer of the task that is now selected as the Running
+	state task from its TCB. */
+	MOV.L	#_pxCurrentTCB,R15
+	MOV.L	[ R15 ], R15
+	MOV.L	[ R15 ], R0
+
+	/* Restore the context of the new task.  The PSW (Program Status Word) and
+	PC will be popped by the RTE instruction. */
+    POP		R15
+    MVTACLO	R15, A0		/* Accumulator low 32 bits. */
+    POP		R15
+    MVTACHI	R15, A0		/* Accumulator high 32 bits. */
+    POP		R15
+    MVTACGU	R15, A0		/* Accumulator guard. */
+    POP		R15
+    MVTACLO	R15, A1		/* Accumulator low 32 bits. */
+    POP		R15
+    MVTACHI	R15, A1		/* Accumulator high 32 bits. */
+    POP		R15
+    MVTACGU	R15, A1		/* Accumulator guard. */
+	POP		R15
+	MVTC	R15,FPSW
+	POPM	R1-R15
+	RTE
+	NOP
+	NOP
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( pxCurrentTCB == NULL );
+
+	/* The following line is just to prevent the symbol getting optimised away. */
+	( void ) vTaskSwitchContext();
+}
+/*-----------------------------------------------------------*/
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600v2/port_asm.src b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600v2/port_asm.src
new file mode 100644
index 0000000..459432e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600v2/port_asm.src
@@ -0,0 +1,41 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+		.GLB	_vSoftwareInterruptISR
+		.GLB    _vSoftwareInterruptEntry
+
+		.SECTION   P,CODE
+
+_vSoftwareInterruptEntry:
+
+	BRA	_vSoftwareInterruptISR
+
+		.RVECTOR	27, _vSoftwareInterruptEntry
+
+		.END
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600v2/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600v2/portmacro.h
new file mode 100644
index 0000000..2ad5465
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600v2/portmacro.h
@@ -0,0 +1,142 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Hardware specifics. */
+#include "machine.h"
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT				8	/* Could make four, according to manual. */
+#define portSTACK_GROWTH				-1
+#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()						nop()
+
+
+#pragma inline_asm vPortYield
+static void vPortYield( void )
+{
+	/* Save clobbered register - may not actually be necessary if inline asm
+	functions are considered to use the same rules as function calls by the
+	compiler. */
+	PUSH.L R5
+	/* Set ITU SWINTR. */
+	MOV.L #553696, R5
+	MOV.B #1, [R5]
+	/* Read back to ensure the value is taken before proceeding. */
+	MOV.L [R5], R5
+	/* Restore clobbered register to its previous value. */
+	POP R5
+}
+#define portYIELD()	vPortYield()
+#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) portYIELD()
+
+/* These macros should not be called directly, but through the
+taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+performed if configASSERT() is defined to ensure an assertion handler does not
+inadvertently attempt to lower the IPL when the call to assert was triggered
+because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+functions are those that end in FromISR.  FreeRTOS maintains a separate
+interrupt API to ensure API function and interrupt entry is as fast and as
+simple as possible. */
+#define portENABLE_INTERRUPTS() 	set_ipl( ( long ) 0 )
+#ifdef configASSERT
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+	#define portDISABLE_INTERRUPTS() 	if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#else
+	#define portDISABLE_INTERRUPTS() 	set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#endif
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical()
+#define portEXIT_CRITICAL()		vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+#define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600v2/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600v2/readme.txt
new file mode 100644
index 0000000..9e89a09
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX600v2/readme.txt
@@ -0,0 +1,72 @@
+The following table shows which port is recommended to be used.
+
+
+RX MCU Group    CPU     FPU         FPU         Port Layer
+                Core    (Single     (Double     CC-RX                   GNURX               ICCRX (*6)
+                Type    Precision)  Precision)
+
+RX110           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX111           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX113           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX130           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX13T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+
+RX210           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX21A           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX220           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX230,RX231     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23E-A         RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23W           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24U           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+
+RX610           RXv1    Yes         ---         N/A (*4)                N/A (*4)            N/A (*4)
+RX62N,RX621     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX630           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX634           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63N,RX631     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX64M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX65N,RX651     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX66N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX62T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX62G           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX66T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+RX71M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX72M           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+Notes:
+
+*1: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide
+the configuration function.  Please be aware that port.c is hard coded to use CMT0 though it seems to be
+configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*2: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is used, please modify port.c for the configuration.  Please be aware that port.c is
+hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of
+configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*3: RX100 ports are also available.
+
+*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction.
+
+*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
+
+#define configUSE_TASK_DPFPU_SUPPORT            0
+
+*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port.
+It contains two definitions of interrupt priority like the following.
+
+#define configKERNEL_INTERRUPT_PRIORITY         1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY    4
+
+
+For more information about Renesas RX MCUs, please visit the following URL:
+
+https://www.renesas.com/products/microcontrollers-microprocessors/rx.html
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX700v3_DPFPU/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX700v3_DPFPU/port.c
new file mode 100644
index 0000000..1d708a3
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX700v3_DPFPU/port.c
@@ -0,0 +1,590 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the RXv3 DPFPU port.
+*----------------------------------------------------------*/
+
+#warning Testing for DFPU support in this port is not yet complete
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/* Hardware specifics. */
+#if ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
+
+    #include "platform.h"
+
+#else /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+    #include "iodefine.h"
+
+#endif /* configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H */
+
+/*-----------------------------------------------------------*/
+
+/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
+ * PSW is set with U and I set, and PM and IPL clear. */
+#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
+#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
+#define portINITIAL_DPSW    ( ( StackType_t ) 0x00000100 )
+#define portINITIAL_DCMR    ( ( StackType_t ) 0x00000000 )
+#define portINITIAL_DECNT   ( ( StackType_t ) 0x00000001 )
+
+/* Tasks are not created with a DPFPU context, but can be given a DPFPU context
+ * after they have been created.  A variable is stored as part of the tasks context
+ * that holds portNO_DPFPU_CONTEXT if the task does not have a DPFPU context, or
+ * any other value if the task does have a DPFPU context. */
+#define portNO_DPFPU_CONTEXT    ( ( StackType_t ) 0 )
+#define portHAS_DPFPU_CONTEXT   ( ( StackType_t ) 1 )
+
+/* The space on the stack required to hold the DPFPU data registers.  This is 16
+ * 64-bit registers. */
+#define portDPFPU_DATA_REGISTER_WORDS   ( 16 * 2 )
+
+/*-----------------------------------------------------------*/
+
+/* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
+ * and therefore installed in the vector table, when the FreeRTOS code is built
+ * as a library. */
+extern BaseType_t vSoftwareInterruptEntry;
+const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Function to start the first task executing - written in asm code as direct
+ * access to registers is required.
+ */
+static void prvStartFirstTask( void );
+
+/*
+ * Software interrupt handler.  Performs the actual context switch (saving and
+ * restoring of registers).  Written in asm code as direct register access is
+ * required.
+ */
+static void prvYieldHandler( void );
+
+/*
+ * The entry point for the software interrupt handler.  This is the function
+ * that calls the inline asm function prvYieldHandler().  It is installed in
+ * the vector table, but the code that installs it is in prvYieldHandler rather
+ * than using a #pragma.
+ */
+void vSoftwareInterruptISR( void );
+
+/*
+ * The tick ISR handler.  The peripheral used is configured by the application
+ * via a hook/callback function.
+ */
+void vTickISR( void );
+
+/*-----------------------------------------------------------*/
+
+/* Saved as part of the task context.  If ulPortTaskHasDPFPUContext is non-zero
+ * then a DPFPU context must be saved and restored for the task. */
+#if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+    StackType_t ulPortTaskHasDPFPUContext = portNO_DPFPU_CONTEXT;
+
+#endif /* configUSE_TASK_DPFPU_SUPPORT */
+
+/* This is accessed by the inline assembler functions so is file scope for
+ * convenience. */
+extern void * pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* R0 is not included as it is the stack pointer. */
+
+    *pxTopOfStack = 0x00;
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_PSW;
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) pxCode;
+
+    /* When debugging it can be useful if every register is set to a known
+     * value.  Otherwise code space can be saved by just setting the registers
+     * that need to be set. */
+    #ifdef USE_FULL_REGISTER_INITIALISATION
+        {
+            pxTopOfStack--;
+            *pxTopOfStack = 0xffffffff; /* r15. */
+            pxTopOfStack--;
+            *pxTopOfStack = 0xeeeeeeee;
+            pxTopOfStack--;
+            *pxTopOfStack = 0xdddddddd;
+            pxTopOfStack--;
+            *pxTopOfStack = 0xcccccccc;
+            pxTopOfStack--;
+            *pxTopOfStack = 0xbbbbbbbb;
+            pxTopOfStack--;
+            *pxTopOfStack = 0xaaaaaaaa;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x99999999;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x88888888;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x77777777;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x66666666;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x55555555;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x44444444;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x33333333;
+            pxTopOfStack--;
+            *pxTopOfStack = 0x22222222;
+            pxTopOfStack--;
+        }
+    #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
+        {
+            pxTopOfStack -= 15;
+        }
+    #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_FPSW;
+    pxTopOfStack--;
+    *pxTopOfStack = 0x11111111; /* Accumulator 1. */
+    pxTopOfStack--;
+    *pxTopOfStack = 0x22222222; /* Accumulator 1. */
+    pxTopOfStack--;
+    *pxTopOfStack = 0x33333333; /* Accumulator 1. */
+    pxTopOfStack--;
+    *pxTopOfStack = 0x44444444; /* Accumulator 0. */
+    pxTopOfStack--;
+    *pxTopOfStack = 0x55555555; /* Accumulator 0. */
+    pxTopOfStack--;
+    *pxTopOfStack = 0x66666666; /* Accumulator 0. */
+
+    #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+        {
+            /* The task will start without a DPFPU context.  A task that
+             * uses the DPFPU hardware must call vPortTaskUsesDPFPU() before
+             * executing any floating point instructions. */
+            pxTopOfStack--;
+            *pxTopOfStack = portNO_DPFPU_CONTEXT;
+        }
+    #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+        {
+            /* The task will start with a DPFPU context.  Leave enough
+             * space for the registers - and ensure they are initialised if desired. */
+            #ifdef USE_FULL_REGISTER_INITIALISATION
+                {
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1515.1515; /* DR15. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1414.1414; /* DR14. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1313.1313; /* DR13. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1212.1212; /* DR12. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1111.1111; /* DR11. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 1010.1010; /* DR10. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  909.0909; /* DR9. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  808.0808; /* DR8. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  707.0707; /* DR7. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  606.0606; /* DR6. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  505.0505; /* DR5. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  404.0404; /* DR4. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  303.0303; /* DR3. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  202.0202; /* DR2. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack =  101.0101; /* DR1. */
+                    pxTopOfStack -= 2;
+                    *(double *)pxTopOfStack = 9876.54321;/* DR0. */
+                }
+            #else /* ifdef USE_FULL_REGISTER_INITIALISATION */
+                {
+                    pxTopOfStack -= portDPFPU_DATA_REGISTER_WORDS;
+                    memset( pxTopOfStack, 0x00, portDPFPU_DATA_REGISTER_WORDS * sizeof( StackType_t ) );
+                }
+            #endif /* ifdef USE_FULL_REGISTER_INITIALISATION */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_DECNT; /* DECNT. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_DCMR;  /* DCMR. */
+            pxTopOfStack--;
+            *pxTopOfStack = portINITIAL_DPSW;  /* DPSW. */
+        }
+    #elif ( configUSE_TASK_DPFPU_SUPPORT == 0 )
+        {
+            /* Omit DPFPU support. */
+        }
+    #else /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+        {
+            #error Invalid configUSE_TASK_DPFPU_SUPPORT setting - configUSE_TASK_DPFPU_SUPPORT must be set to 0, 1, 2, or left undefined.
+        }
+    #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+    void vPortTaskUsesDPFPU( void )
+    {
+        /* A task is registering the fact that it needs a DPFPU context.  Set the
+         * DPFPU flag (which is saved as part of the task context). */
+        ulPortTaskHasDPFPUContext = portHAS_DPFPU_CONTEXT;
+    }
+
+#endif /* configUSE_TASK_DPFPU_SUPPORT */
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+    extern void vApplicationSetupTimerInterrupt( void );
+
+    /* Use pxCurrentTCB just so it does not get optimised away. */
+    if( pxCurrentTCB != NULL )
+    {
+        /* Call an application function to set up the timer that will generate the
+         * tick interrupt.  This way the application can decide which peripheral to
+         * use.  A demo application is provided to show a suitable example. */
+        vApplicationSetupTimerInterrupt();
+
+        /* Enable the software interrupt. */
+        _IEN( _ICU_SWINT ) = 1;
+
+        /* Ensure the software interrupt is clear. */
+        _IR( _ICU_SWINT ) = 0;
+
+        /* Ensure the software interrupt is set to the kernel priority. */
+        _IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
+
+        /* Start the first task. */
+        prvStartFirstTask();
+    }
+
+    /* Just to make sure the function is not optimised away. */
+    ( void ) vSoftwareInterruptISR();
+
+    /* Should not get here. */
+    return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( pxCurrentTCB == NULL );
+
+    /* The following line is just to prevent the symbol getting optimised away. */
+    ( void ) vTaskSwitchContext();
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvStartFirstTask
+static void prvStartFirstTask( void )
+{
+#ifndef __CDT_PARSER__
+
+    /* When starting the scheduler there is nothing that needs moving to the
+     * interrupt stack because the function is not called from an interrupt.
+     * Just ensure the current stack is the user stack. */
+    SETPSW U
+
+
+    /* Obtain the location of the stack associated with which ever task
+     * pxCurrentTCB is currently pointing to. */
+    MOV.L # _pxCurrentTCB, R15
+    MOV.L [ R15 ], R15
+    MOV.L [ R15 ], R0
+
+
+    /* Restore the registers from the stack of the task pointed to by
+     * pxCurrentTCB. */
+
+    #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+        /* The restored ulPortTaskHasDPFPUContext is to be zero here.
+         * So, it is never necessary to restore the DPFPU context here. */
+        POP R15
+        MOV.L # _ulPortTaskHasDPFPUContext, R14
+        MOV.L R15, [ R14 ]
+
+    #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+
+        /* Restore the DPFPU context. */
+        DPOPM.L DPSW-DECNT
+        DPOPM.D DR0-DR15
+
+    #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+
+    POP R15
+
+    /* Accumulator low 32 bits. */
+    MVTACLO R15, A0
+    POP R15
+
+    /* Accumulator high 32 bits. */
+    MVTACHI R15, A0
+    POP R15
+
+    /* Accumulator guard. */
+    MVTACGU R15, A0
+    POP R15
+
+    /* Accumulator low 32 bits. */
+    MVTACLO R15, A1
+    POP R15
+
+    /* Accumulator high 32 bits. */
+    MVTACHI R15, A1
+    POP R15
+
+    /* Accumulator guard. */
+    MVTACGU R15, A1
+    POP R15
+
+    /* Floating point status word. */
+    MVTC R15, FPSW
+
+    /* R1 to R15 - R0 is not included as it is the SP. */
+    POPM R1-R15
+
+    /* This pops the remaining registers. */
+    RTE
+    NOP
+    NOP
+
+#endif /* ifndef __CDT_PARSER__ */
+}
+/*-----------------------------------------------------------*/
+
+void vSoftwareInterruptISR( void )
+{
+    prvYieldHandler();
+}
+/*-----------------------------------------------------------*/
+
+#pragma inline_asm prvYieldHandler
+static void prvYieldHandler( void )
+{
+#ifndef __CDT_PARSER__
+
+    /* Re-enable interrupts. */
+    SETPSW I
+
+
+    /* Move the data that was automatically pushed onto the interrupt stack when
+     * the interrupt occurred from the interrupt stack to the user stack.
+     *
+     * R15 is saved before it is clobbered. */
+    PUSH.L R15
+
+    /* Read the user stack pointer. */
+    MVFC USP, R15
+
+    /* Move the address down to the data being moved. */
+    SUB # 12, R15
+    MVTC R15, USP
+
+    /* Copy the data across, R15, then PC, then PSW. */
+    MOV.L [ R0 ], [ R15 ]
+    MOV.L 4[ R0 ], 4[ R15 ]
+    MOV.L 8[ R0 ], 8[ R15 ]
+
+    /* Move the interrupt stack pointer to its new correct position. */
+    ADD # 12, R0
+
+    /* All the rest of the registers are saved directly to the user stack. */
+    SETPSW U
+
+    /* Save the rest of the general registers (R15 has been saved already). */
+    PUSHM R1-R14
+
+    /* Save the FPSW and accumulators. */
+    MVFC FPSW, R15
+    PUSH.L R15
+    MVFACGU # 0, A1, R15
+    PUSH.L R15
+    MVFACHI # 0, A1, R15
+    PUSH.L R15
+    MVFACLO # 0, A1, R15 /* Low order word. */
+    PUSH.L R15
+    MVFACGU # 0, A0, R15
+    PUSH.L R15
+    MVFACHI # 0, A0, R15
+    PUSH.L R15
+    MVFACLO # 0, A0, R15 /* Low order word. */
+    PUSH.L R15
+
+    #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+        /* Does the task have a DPFPU context that needs saving?  If
+         * ulPortTaskHasDPFPUContext is 0 then no. */
+        MOV.L # _ulPortTaskHasDPFPUContext, R15
+        MOV.L [ R15 ], R15
+        CMP # 0, R15
+
+        /* Save the DPFPU context, if any. */
+        BEQ.B ?+
+        DPUSHM.D DR0-DR15
+        DPUSHM.L DPSW-DECNT
+        ?:
+
+        /* Save ulPortTaskHasDPFPUContext itself. */
+        PUSH.L R15
+
+    #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+
+        /* Save the DPFPU context, always. */
+        DPUSHM.D DR0-DR15
+        DPUSHM.L DPSW-DECNT
+
+    #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+
+
+    /* Save the stack pointer to the TCB. */
+    MOV.L # _pxCurrentTCB, R15
+    MOV.L [ R15 ], R15
+    MOV.L R0, [ R15 ]
+
+
+    /* Ensure the interrupt mask is set to the syscall priority while the kernel
+     * structures are being accessed. */
+    MVTIPL # configMAX_SYSCALL_INTERRUPT_PRIORITY
+
+    /* Select the next task to run. */
+    BSR.A _vTaskSwitchContext
+
+    /* Reset the interrupt mask as no more data structure access is required. */
+    MVTIPL # configKERNEL_INTERRUPT_PRIORITY
+
+
+    /* Load the stack pointer of the task that is now selected as the Running
+     * state task from its TCB. */
+    MOV.L # _pxCurrentTCB, R15
+    MOV.L [ R15 ], R15
+    MOV.L [ R15 ], R0
+
+
+    /* Restore the context of the new task.  The PSW (Program Status Word) and
+     * PC will be popped by the RTE instruction. */
+
+    #if ( configUSE_TASK_DPFPU_SUPPORT == 1 )
+
+        /* Is there a DPFPU context to restore?  If the restored
+         * ulPortTaskHasDPFPUContext is zero then no. */
+        POP R15
+        MOV.L # _ulPortTaskHasDPFPUContext, R14
+        MOV.L R15, [ R14 ]
+        CMP # 0, R15
+
+        /* Restore the DPFPU context, if any. */
+        BEQ.B ?+
+        DPOPM.L DPSW-DECNT
+        DPOPM.D DR0-DR15
+        ?:
+
+    #elif ( configUSE_TASK_DPFPU_SUPPORT == 2 )
+
+        /* Restore the DPFPU context, always. */
+        DPOPM.L DPSW-DECNT
+        DPOPM.D DR0-DR15
+
+    #endif /* if ( configUSE_TASK_DPFPU_SUPPORT == 1 ) */
+
+    POP R15
+
+    /* Accumulator low 32 bits. */
+    MVTACLO R15, A0
+    POP R15
+
+    /* Accumulator high 32 bits. */
+    MVTACHI R15, A0
+    POP R15
+
+    /* Accumulator guard. */
+    MVTACGU R15, A0
+    POP R15
+
+    /* Accumulator low 32 bits. */
+    MVTACLO R15, A1
+    POP R15
+
+    /* Accumulator high 32 bits. */
+    MVTACHI R15, A1
+    POP R15
+
+    /* Accumulator guard. */
+    MVTACGU R15, A1
+    POP R15
+    MVTC R15, FPSW
+    POPM R1-R15
+    RTE
+    NOP
+    NOP
+
+#endif /* ifndef __CDT_PARSER__ */
+}
+/*-----------------------------------------------------------*/
+
+#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) )
+void vTickISR( void )
+{
+    /* Increment the tick, and perform any processing the new tick value
+     * necessitates.  Ensure IPL is at the max syscall value first. */
+    set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+    {
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            taskYIELD();
+        }
+    }
+    set_ipl( configKERNEL_INTERRUPT_PRIORITY );
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX700v3_DPFPU/port_asm.src b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX700v3_DPFPU/port_asm.src
new file mode 100644
index 0000000..ba6e3b7
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX700v3_DPFPU/port_asm.src
@@ -0,0 +1,41 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+		.GLB	_vSoftwareInterruptISR
+		.GLB    _vSoftwareInterruptEntry
+
+		.SECTION   P,CODE
+
+_vSoftwareInterruptEntry:
+
+	BRA	_vSoftwareInterruptISR
+
+		.RVECTOR	27, _vSoftwareInterruptEntry
+
+		.END
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX700v3_DPFPU/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX700v3_DPFPU/portmacro.h
new file mode 100644
index 0000000..f576e81
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX700v3_DPFPU/portmacro.h
@@ -0,0 +1,185 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/* Hardware specifics. */
+    #include <machine.h>
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* When the FIT configurator or the Smart Configurator is used, platform.h has to be 
+ * used. */
+    #ifndef configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H
+        #define configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H 0
+    #endif
+
+/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or undefined) then each task will
+ * be created without a DPFPU context, and a task must call vTaskUsesDPFPU() before
+ * making use of any DPFPU registers.  If configUSE_TASK_DPFPU_SUPPORT is set to 2 then
+ * tasks are created with a DPFPU context by default, and calling vTaskUsesDPFPU() has
+ * no effect.  If configUSE_TASK_DPFPU_SUPPORT is set to 0 then tasks never take care
+ * of any DPFPU context (even if DPFPU registers are used). */
+    #ifndef configUSE_TASK_DPFPU_SUPPORT
+        #define configUSE_TASK_DPFPU_SUPPORT 1
+    #endif
+
+/*-----------------------------------------------------------*/
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+ * portSTACK_TYPE and portBASE_TYPE. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+    #define portBYTE_ALIGNMENT    8     /* Could make four, according to manual. */
+    #define portSTACK_GROWTH      -1
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portNOP()    nop()
+
+/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
+ * where portITU_SWINTR is the location of the software interrupt register
+ * (0x000872E0).  Don't rely on the assembler to select a register, so instead
+ * save and restore clobbered registers manually. */
+    #pragma inline_asm vPortYield
+    static void vPortYield( void )
+    {
+    #ifndef __CDT_PARSER__
+        /* Save clobbered register - may not actually be necessary if inline asm
+         * functions are considered to use the same rules as function calls by the
+         * compiler. */
+        PUSH.L R5
+        /* Set ITU SWINTR. */
+        MOV.L # 000872E0H, R5
+        MOV.B # 1, [ R5 ]
+        /* Read back to ensure the value is taken before proceeding. */
+        CMP [ R5 ].UB, R5
+        /* Restore clobbered register to its previous value. */
+        POP R5
+    #endif
+    }
+
+    #define portYIELD()                                       vPortYield()
+    #define portYIELD_FROM_ISR( x )                           if( ( x ) != pdFALSE ) portYIELD()
+
+/* These macros should not be called directly, but through the
+ * taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
+ * performed if configASSERT() is defined to ensure an assertion handler does not
+ * inadvertently attempt to lower the IPL when the call to assert was triggered
+ * because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
+ * when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
+ * functions are those that end in FromISR.  FreeRTOS maintains a separate
+ * interrupt API to ensure API function and interrupt entry is as fast and as
+ * simple as possible. */
+    #define portENABLE_INTERRUPTS()                           set_ipl( ( long ) 0 )
+    #ifdef configASSERT
+        #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()    configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
+        #define portDISABLE_INTERRUPTS()                      if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #else
+        #define portDISABLE_INTERRUPTS()                      set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #endif
+
+/* Critical nesting counts are stored in the TCB. */
+    #define portCRITICAL_NESTING_IN_TCB    ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+    extern void vTaskEnterCritical( void );
+    extern void vTaskExitCritical( void );
+    #define portENTER_CRITICAL()    vTaskEnterCritical()
+    #define portEXIT_CRITICAL()     vTaskExitCritical()
+
+/* As this port allows interrupt nesting... */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()                              ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus )    set_ipl( ( long ) uxSavedInterruptStatus )
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+/*-----------------------------------------------------------*/
+
+/* If configUSE_TASK_DPFPU_SUPPORT is set to 1 (or left undefined) then tasks are
+ * created without a DPFPU context and must call vPortTaskUsesDPFPU() to give
+ * themselves a DPFPU context before using any DPFPU instructions.  If
+ * configUSE_TASK_DPFPU_SUPPORT is set to 2 then all tasks will have a DPFPU context
+ * by default. */
+    #if( configUSE_TASK_DPFPU_SUPPORT == 1 )
+        void vPortTaskUsesDPFPU( void );
+    #else
+/* Each task has a DPFPU context already, so define this function away to
+ * nothing to prevent it being called accidentally. */
+        #define vPortTaskUsesDPFPU()
+    #endif
+    #define portTASK_USES_DPFPU() vPortTaskUsesDPFPU()
+
+/* Definition to allow compatibility with existing FreeRTOS Demo using flop.c. */
+    #define portTASK_USES_FLOATING_POINT() vPortTaskUsesDPFPU()
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX700v3_DPFPU/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX700v3_DPFPU/readme.txt
new file mode 100644
index 0000000..9e89a09
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/RX700v3_DPFPU/readme.txt
@@ -0,0 +1,72 @@
+The following table shows which port is recommended to be used.
+
+
+RX MCU Group    CPU     FPU         FPU         Port Layer
+                Core    (Single     (Double     CC-RX                   GNURX               ICCRX (*6)
+                Type    Precision)  Precision)
+
+RX110           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX111           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX113           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX130           RXv1    No          ---         Renesas/RX100 (*1,*2)   GCC/RX100 (*1,*2)   IAR/RX100 (*1,*2)
+RX13T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+
+RX210           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX21A           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX220           RXv1    No          ---         Renesas/RX200 (*3)      N/A (*3)            N/A (*3)
+RX230,RX231     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23E-A         RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23W           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX23T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24T           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX24U           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+
+RX610           RXv1    Yes         ---         N/A (*4)                N/A (*4)            N/A (*4)
+RX62N,RX621     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX630           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX634           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63N,RX631     RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX64M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX65N,RX651     RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX66N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX62T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX62G           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX63T           RXv1    Yes         ---         Renesas/RX600           GCC/RX600           IAR/RX600
+RX66T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+RX71M           RXv2    Yes         ---         Renesas/RX600v2         GCC/RX600v2         IAR/RXv2
+RX72M           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72N           RXv3    Yes         Yes         Renesas/RX700v3_DPFPU   GCC/RX700v3_DPFPU   IAR/RX700v3_DPFPU
+RX72T           RXv3    Yes         No          Renesas/RX600v2 (*5)    GCC/RX600v2 (*5)    IAR/RXv2 (*5)
+
+Notes:
+
+*1: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is not used, please define configSETUP_TICK_INTERRUPT() (in FreeRTOSConfig.h) and provide
+the configuration function.  Please be aware that port.c is hard coded to use CMT0 though it seems to be
+configured to use any CMTn according to the definition of configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*2: If the application writer wants to use their own tick interrupt configuration when tickless idle
+functionality is used, please modify port.c for the configuration.  Please be aware that port.c is
+hard coded to use CMT0 though it seems to be configured to use any CMTn according to the definition of
+configTICK_VECTOR (in FreeRTOSConfig.h).
+
+*3: RX100 ports are also available.
+
+*4: RX600 ports use MVTIPL instruction but RX610 MCUs don't support this instruction.
+
+*5: RX700v3_DPFPU ports are also available with the following definition in FreeRTOSConfig.h.
+
+#define configUSE_TASK_DPFPU_SUPPORT            0
+
+*6: PriorityDefinitions.h has to be provided for port_asm.s in case of other than RX700v3_DPFPU port.
+It contains two definitions of interrupt priority like the following.
+
+#define configKERNEL_INTERRUPT_PRIORITY         1
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY    4
+
+
+For more information about Renesas RX MCUs, please visit the following URL:
+
+https://www.renesas.com/products/microcontrollers-microprocessors/rx.html
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/SH2A_FPU/ISR_Support.inc b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/SH2A_FPU/ISR_Support.inc
new file mode 100644
index 0000000..30edf90
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/SH2A_FPU/ISR_Support.inc
@@ -0,0 +1,74 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+	.macro portSAVE_CONTEXT
+
+	; Save r0 to r14 and pr.
+	movml.l r15, @-r15
+
+	; Save mac1, mach and gbr
+	sts.l	macl, @-r15
+	sts.l	mach, @-r15
+	stc.l	gbr, @-r15
+
+	; Get the address of pxCurrentTCB
+	mov.l	#_pxCurrentTCB, r0
+
+	; Get the address of pxTopOfStack from the TCB.
+	mov.l	@r0, r0
+
+	; Save the stack pointer in pxTopOfStack.
+	mov.l	r15, @r0
+
+	.endm
+
+;-----------------------------------------------------------
+
+	.macro portRESTORE_CONTEXT
+
+	; Get the address of the pxCurrentTCB variable.
+	mov.l	#_pxCurrentTCB, r0
+
+	; Get the address of the task stack from pxCurrentTCB.
+	mov.l	@r0, r0
+
+	; Get the task stack itself into the stack pointer.
+	mov.l	@r0, r15
+
+	; Restore system registers.
+	ldc.l	@r15+, gbr
+	lds.l	@r15+, mach
+	lds.l	@r15+, macl
+
+	; Restore r0 to r14 and PR
+	movml.l	@r15+, r15
+
+	; Pop the SR and PC to jump to the start of the task.
+	rte
+	nop
+
+	.endm
+;-----------------------------------------------------------
\ No newline at end of file
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/SH2A_FPU/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/SH2A_FPU/port.c
new file mode 100644
index 0000000..6b54d15
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/SH2A_FPU/port.c
@@ -0,0 +1,271 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the SH2A port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Library includes. */
+#include "string.h"
+
+/*-----------------------------------------------------------*/
+
+/* The SR assigned to a newly created task.  The only important thing in this
+value is for all interrupts to be enabled. */
+#define portINITIAL_SR				( 0UL )
+
+/* Dimensions the array into which the floating point context is saved.
+Allocate enough space for FPR0 to FPR15, FPUL and FPSCR, each of which is 4
+bytes big.  If this number is changed then the 72 in portasm.src also needs
+changing. */
+#define portFLOP_REGISTERS_TO_STORE	( 18 )
+#define portFLOP_STORAGE_SIZE 		( portFLOP_REGISTERS_TO_STORE * 4 )
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
+	#error configSUPPORT_DYNAMIC_ALLOCATION must be 1 to use this port.
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The TRAPA handler used to force a context switch.
+ */
+void vPortYield( void );
+
+/*
+ * Function to start the first task executing - defined in portasm.src.
+ */
+extern void vPortStartFirstTask( void );
+
+/*
+ * Obtains the current GBR value - defined in portasm.src.
+ */
+extern uint32_t ulPortGetGBR( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Mark the end of the stack - used for debugging only and can be removed. */
+	*pxTopOfStack = 0x11111111UL;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22222222UL;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33333333UL;
+	pxTopOfStack--;
+
+	/* SR. */
+	*pxTopOfStack = portINITIAL_SR;
+	pxTopOfStack--;
+
+	/* PC. */
+	*pxTopOfStack = ( uint32_t ) pxCode;
+	pxTopOfStack--;
+
+	/* PR. */
+	*pxTopOfStack = 15;
+	pxTopOfStack--;
+
+	/* 14. */
+	*pxTopOfStack = 14;
+	pxTopOfStack--;
+
+	/* R13. */
+	*pxTopOfStack = 13;
+	pxTopOfStack--;
+
+	/* R12. */
+	*pxTopOfStack = 12;
+	pxTopOfStack--;
+
+	/* R11. */
+	*pxTopOfStack = 11;
+	pxTopOfStack--;
+
+	/* R10. */
+	*pxTopOfStack = 10;
+	pxTopOfStack--;
+
+	/* R9. */
+	*pxTopOfStack = 9;
+	pxTopOfStack--;
+
+	/* R8. */
+	*pxTopOfStack = 8;
+	pxTopOfStack--;
+
+	/* R7. */
+	*pxTopOfStack = 7;
+	pxTopOfStack--;
+
+	/* R6. */
+	*pxTopOfStack = 6;
+	pxTopOfStack--;
+
+	/* R5. */
+	*pxTopOfStack = 5;
+	pxTopOfStack--;
+
+	/* R4. */
+	*pxTopOfStack = ( uint32_t ) pvParameters;
+	pxTopOfStack--;
+
+	/* R3. */
+	*pxTopOfStack = 3;
+	pxTopOfStack--;
+
+	/* R2. */
+	*pxTopOfStack = 2;
+	pxTopOfStack--;
+
+	/* R1. */
+	*pxTopOfStack = 1;
+	pxTopOfStack--;
+
+	/* R0 */
+	*pxTopOfStack = 0;
+	pxTopOfStack--;
+
+	/* MACL. */
+	*pxTopOfStack = 16;
+	pxTopOfStack--;
+
+	/* MACH. */
+	*pxTopOfStack = 17;
+	pxTopOfStack--;
+
+	/* GBR. */
+	*pxTopOfStack = ulPortGetGBR();
+
+	/* GBR = global base register.
+	   VBR = vector base register.
+	   TBR = jump table base register.
+	   R15 is the stack pointer. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+extern void vApplicationSetupTimerInterrupt( void );
+
+	/* Call an application function to set up the timer that will generate the
+	tick interrupt.  This way the application can decide which peripheral to
+	use.  A demo application is provided to show a suitable example. */
+	vApplicationSetupTimerInterrupt();
+
+	/* Start the first task.  This will only restore the standard registers and
+	not the flop registers.  This does not really matter though because the only
+	flop register that is initialised to a particular value is fpscr, and it is
+	only initialised to the current value, which will still be the current value
+	when the first task starts executing. */
+	trapa( portSTART_SCHEDULER_TRAP_NO );
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented as there is nothing to return to. */
+}
+/*-----------------------------------------------------------*/
+
+void vPortYield( void )
+{
+int32_t lInterruptMask;
+
+	/* Ensure the yield trap runs at the same priority as the other interrupts
+	that can cause a context switch. */
+	lInterruptMask = get_imask();
+
+	/* taskYIELD() can only be called from a task, not an interrupt, so the
+	current interrupt mask can only be 0 or portKERNEL_INTERRUPT_PRIORITY and
+	the mask can be set without risk of accidentally lowering the mask value. */
+	set_imask( portKERNEL_INTERRUPT_PRIORITY );
+
+	trapa( portYIELD_TRAP_NO );
+
+	/* Restore the interrupt mask to whatever it was previously (when the
+	function was entered). */
+	set_imask( ( int ) lInterruptMask );
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortUsesFloatingPoint( TaskHandle_t xTask )
+{
+uint32_t *pulFlopBuffer;
+BaseType_t xReturn;
+extern void * volatile pxCurrentTCB;
+
+	/* This function tells the kernel that the task referenced by xTask is
+	going to use the floating point registers and therefore requires the
+	floating point registers saved as part of its context. */
+
+	/* Passing NULL as xTask is used to indicate that the calling task is the
+	subject task - so pxCurrentTCB is the task handle. */
+	if( xTask == NULL )
+	{
+		xTask = ( TaskHandle_t ) pxCurrentTCB;
+	}
+
+	/* Allocate a buffer large enough to hold all the flop registers. */
+	pulFlopBuffer = ( uint32_t * ) pvPortMalloc( portFLOP_STORAGE_SIZE );
+
+	if( pulFlopBuffer != NULL )
+	{
+		/* Start with the registers in a benign state. */
+		memset( ( void * ) pulFlopBuffer, 0x00, portFLOP_STORAGE_SIZE );
+
+		/* The first thing to get saved in the buffer is the FPSCR value -
+		initialise this to the current FPSCR value. */
+		*pulFlopBuffer = get_fpscr();
+
+		/* Use the task tag to point to the flop buffer.  Pass pointer to just
+		above the buffer because the flop save routine uses a pre-decrement. */
+		vTaskSetApplicationTaskTag( xTask, ( void * ) ( pulFlopBuffer + portFLOP_REGISTERS_TO_STORE ) );
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = pdFAIL;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portasm.src b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portasm.src
new file mode 100644
index 0000000..e2c1758
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portasm.src
@@ -0,0 +1,150 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+	.import _pxCurrentTCB
+	.import _vTaskSwitchContext
+	.import _xTaskIncrementTick
+
+	.export _vPortStartFirstTask
+	.export _ulPortGetGBR
+	.export _vPortYieldHandler
+	.export _vPortPreemptiveTick
+	.export _vPortCooperativeTick
+	.export _vPortSaveFlopRegisters
+	.export _vPortRestoreFlopRegisters
+
+    .section    P
+
+	.INCLUDE "ISR_Support.inc"
+
+_vPortStartFirstTask:
+
+	portRESTORE_CONTEXT
+
+;-----------------------------------------------------------
+
+_vPortYieldHandler:
+
+	portSAVE_CONTEXT
+
+	mov.l	#_vTaskSwitchContext, r0
+	jsr		@r0
+	nop
+
+	portRESTORE_CONTEXT
+
+;-----------------------------------------------------------
+
+_vPortPreemptiveTick
+
+	portSAVE_CONTEXT
+
+	mov.l	#_xTaskIncrementTick, r0
+	jsr		@r0
+	nop
+
+	mov.l	#_vTaskSwitchContext, r0
+	jsr		@r0
+	nop
+
+	portRESTORE_CONTEXT
+
+;-----------------------------------------------------------
+
+_vPortCooperativeTick
+
+	portSAVE_CONTEXT
+
+	mov.l	#_xTaskIncrementTick, r0
+	jsr		@r0
+	nop
+
+	portRESTORE_CONTEXT
+
+;-----------------------------------------------------------
+
+_ulPortGetGBR:
+
+	stc.l	gbr, r0
+	rts
+	nop
+
+;-----------------------------------------------------------
+
+_vPortSaveFlopRegisters:
+
+	fmov.s	fr0, @-r4
+	fmov.s	fr1, @-r4
+	fmov.s	fr2, @-r4
+	fmov.s	fr3, @-r4
+	fmov.s	fr4, @-r4
+	fmov.s	fr5, @-r4
+	fmov.s	fr6, @-r4
+	fmov.s	fr7, @-r4
+	fmov.s	fr8, @-r4
+	fmov.s	fr9, @-r4
+	fmov.s	fr10, @-r4
+	fmov.s	fr11, @-r4
+	fmov.s	fr12, @-r4
+	fmov.s	fr13, @-r4
+	fmov.s	fr14, @-r4
+	fmov.s	fr15, @-r4
+	sts.l   fpul, @-r4
+	sts.l   fpscr, @-r4
+
+	rts
+	nop
+
+;-----------------------------------------------------------
+
+_vPortRestoreFlopRegisters:
+
+	add.l  #-72, r4
+	lds.l  @r4+, fpscr
+	lds.l  @r4+, fpul
+	fmov.s @r4+, fr15
+	fmov.s @r4+, fr14
+	fmov.s @r4+, fr13
+	fmov.s @r4+, fr12
+	fmov.s @r4+, fr11
+	fmov.s @r4+, fr10
+	fmov.s @r4+, fr9
+	fmov.s @r4+, fr8
+	fmov.s @r4+, fr7
+	fmov.s @r4+, fr6
+	fmov.s @r4+, fr5
+	fmov.s @r4+, fr4
+	fmov.s @r4+, fr3
+	fmov.s @r4+, fr2
+	fmov.s @r4+, fr1
+	fmov.s @r4+, fr0
+
+	rts
+	nop
+
+	.end
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portmacro.h
new file mode 100644
index 0000000..d7ccc1f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portmacro.h
@@ -0,0 +1,139 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include <machine.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions - these are a bit legacy and not really used now, other than
+portSTACK_TYPE and portBASE_TYPE. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT				8
+#define portSTACK_GROWTH				-1
+#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()						nop()
+#define portSTART_SCHEDULER_TRAP_NO		( 32 )
+#define portYIELD_TRAP_NO				( 33 )
+#define portKERNEL_INTERRUPT_PRIORITY	( 1 )
+
+void vPortYield( void );
+#define portYIELD()						vPortYield()
+
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR( x )			if( x != pdFALSE ) vTaskSwitchContext()
+
+/*
+ * This function tells the kernel that the task referenced by xTask is going to
+ * use the floating point registers and therefore requires the floating point
+ * registers saved as part of its context.
+ */
+BaseType_t xPortUsesFloatingPoint( void* xTask );
+
+/*
+ * The flop save and restore functions are defined in portasm.src and called by
+ * the trace "task switched in" and "trace task switched out" macros.
+ */
+void vPortSaveFlopRegisters( void *pulBuffer );
+void vPortRestoreFlopRegisters( void *pulBuffer );
+
+/*
+ * pxTaskTag is used to point to the buffer into which the floating point
+ * context should be saved.  If pxTaskTag is NULL then the task does not use
+ * a floating point context.
+ */
+#define traceTASK_SWITCHED_OUT() if( pxCurrentTCB->pxTaskTag != NULL ) vPortSaveFlopRegisters( pxCurrentTCB->pxTaskTag )
+#define traceTASK_SWITCHED_IN() if( pxCurrentTCB->pxTaskTag != NULL ) vPortRestoreFlopRegisters( pxCurrentTCB->pxTaskTag )
+
+/*
+ * These macros should be called directly, but through the taskENTER_CRITICAL()
+ * and taskEXIT_CRITICAL() macros.
+ */
+#define portENABLE_INTERRUPTS() 	set_imask( 0x00 )
+#define portDISABLE_INTERRUPTS() 	set_imask( portKERNEL_INTERRUPT_PRIORITY )
+
+/* Critical nesting counts are stored in the TCB. */
+#define portCRITICAL_NESTING_IN_TCB ( 1 )
+
+/* The critical nesting functions defined within tasks.c. */
+extern void vTaskEnterCritical( void );
+extern void vTaskExitCritical( void );
+#define portENTER_CRITICAL()	vTaskEnterCritical();
+#define portEXIT_CRITICAL()		vTaskExitCritical();
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Rowley/ARM7/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Rowley/ARM7/readme.txt
new file mode 100644
index 0000000..8d3e87f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Rowley/ARM7/readme.txt
@@ -0,0 +1 @@
+The Rowley ARM7 demo uses the GCC ARM7 port files.
\ No newline at end of file
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Rowley/MSP430F449/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Rowley/MSP430F449/port.c
new file mode 100644
index 0000000..0c60283
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Rowley/MSP430F449/port.c
@@ -0,0 +1,172 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the MSP430 port.
+ *----------------------------------------------------------*/
+
+/* Constants required for hardware setup.  The tick ISR runs off the ACLK, 
+not the MCLK. */
+#define portACLK_FREQUENCY_HZ			( ( TickType_t ) 32768 )
+#define portINITIAL_CRITICAL_NESTING	( ( uint16_t ) 10 )
+#define portFLAGS_INT_ENABLED			( ( StackType_t ) 0x08 )
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/* Each task maintains a count of the critical section nesting depth.  Each 
+time a critical section is entered the count is incremented.  Each time a 
+critical section is exited the count is decremented - with interrupts only 
+being re-enabled if the count is zero.
+
+usCriticalNesting will get set to zero when the scheduler starts, but must
+not be initialised to zero as this will cause problems during the startup
+sequence. */
+volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
+ * could have alternatively used the watchdog timer or timer 1.
+ */
+void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ * 
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* 
+		Place a few bytes of known values on the bottom of the stack. 
+		This is just useful for debugging and can be included if required.
+
+		*pxTopOfStack = ( StackType_t ) 0x1111;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x2222;
+		pxTopOfStack--;
+		*pxTopOfStack = ( StackType_t ) 0x3333;
+		pxTopOfStack--; 
+	*/
+
+	/* The msp430 automatically pushes the PC then SR onto the stack before 
+	executing an ISR.  We want the stack to look just as if this has happened
+	so place a pointer to the start of the task on the stack first - followed
+	by the flags we want the task to use when it starts up. */
+	*pxTopOfStack = ( StackType_t ) pxCode;
+	pxTopOfStack--;
+	*pxTopOfStack = portFLAGS_INT_ENABLED;
+	pxTopOfStack--;
+
+	/* Next the general purpose registers. */
+	*pxTopOfStack = ( StackType_t ) 0x4444;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x5555;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x6666;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x7777;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x8888;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x9999;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xaaaa;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xbbbb;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xcccc;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xdddd;
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xeeee;
+	pxTopOfStack--;
+
+	/* When the task starts is will expect to find the function parameter in
+	R15. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;
+	pxTopOfStack--;
+
+	/* A variable is used to keep track of the critical section nesting.  
+	This variable has to be stored as part of the task context and is 
+	initially set to zero. */
+	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
+
+	/* Return a pointer to the top of the stack we have generated so this can
+	be stored in the task control block for the task. */
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the MSP430 port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Hardware initialisation to generate the RTOS tick.  This uses timer 0
+ * but could alternatively use the watchdog timer or timer 1. 
+ */
+void prvSetupTimerInterrupt( void )
+{
+	/* Ensure the timer is stopped. */
+	TACTL = 0;
+
+	/* Run the timer of the ACLK. */
+	TACTL = TASSEL_1;
+
+	/* Clear everything to start with. */
+	TACTL |= TACLR;
+
+	/* Set the compare match value according to the tick rate we want. */
+	TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
+
+	/* Enable the interrupts. */
+	TACCTL0 = CCIE;
+
+	/* Start up clean. */
+	TACTL |= TACLR;
+
+	/* Up mode. */
+	TACTL |= MC_1;
+}
+/*-----------------------------------------------------------*/
+
+
+	
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Rowley/MSP430F449/portasm.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Rowley/MSP430F449/portasm.h
new file mode 100644
index 0000000..63fd246
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Rowley/MSP430F449/portasm.h
@@ -0,0 +1,80 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORT_ASM_H
+#define PORT_ASM_H
+
+portSAVE_CONTEXT macro
+                /* Save the remaining registers. */
+		push	r4
+		push	r5
+		push	r6
+		push	r7
+		push	r8
+		push	r9
+		push	r10
+		push	r11
+		push	r12
+		push	r13
+		push	r14
+		push	r15
+		mov.w	&_usCriticalNesting, r14
+		push	r14
+		mov.w	&_pxCurrentTCB, r12
+		mov.w	r1, @r12
+		endm
+/*-----------------------------------------------------------*/
+		
+portRESTORE_CONTEXT macro
+		mov.w	&_pxCurrentTCB, r12
+		mov.w	@r12, r1
+		pop		r15
+		mov.w	r15, &_usCriticalNesting
+		pop		r15
+		pop		r14
+		pop		r13
+		pop		r12
+		pop		r11
+		pop		r10
+		pop		r9
+		pop		r8
+		pop		r7
+		pop		r6
+		pop		r5
+		pop		r4
+
+		/* The last thing on the stack will be the status register.
+                Ensure the power down bits are clear ready for the next
+                time this power down register is popped from the stack. */
+		bic.w   #0xf0,0(SP)
+
+		reti
+		endm
+/*-----------------------------------------------------------*/
+
+#endif
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Rowley/MSP430F449/portext.asm b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Rowley/MSP430F449/portext.asm
new file mode 100644
index 0000000..a0567c2
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Rowley/MSP430F449/portext.asm
@@ -0,0 +1,102 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOSConfig.h"
+#include "portasm.h"
+
+
+.CODE
+
+/*
+ * The RTOS tick ISR.
+ *
+ * If the cooperative scheduler is in use this simply increments the tick 
+ * count.
+ *
+ * If the preemptive scheduler is in use a context switch can also occur.
+ */
+_vTickISR:
+		portSAVE_CONTEXT
+				
+		call	#_xTaskIncrementTick
+		cmp.w   #0x00, r15
+                jeq     _SkipContextSwitch
+		call	#_vTaskSwitchContext
+_SkipContextSwitch:		
+		portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Manual context switch called by the portYIELD() macro.
+ */                
+_vPortYield::
+
+		/* Mimic an interrupt by pushing the SR. */
+		push	SR			
+
+		/* Now the SR is stacked we can disable interrupts. */
+		dint			
+				
+		/* Save the context of the current task. */
+		portSAVE_CONTEXT			
+
+		/* Switch to the highest priority task that is ready to run. */
+		call	#_vTaskSwitchContext		
+
+		/* Restore the context of the new task. */
+		portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/
+
+
+/*
+ * Start off the scheduler by initialising the RTOS tick timer, then restoring
+ * the context of the first task.
+ */
+_xPortStartScheduler::
+
+		/* Setup the hardware to generate the tick.  Interrupts are disabled 
+		when this function is called. */
+		call	#_prvSetupTimerInterrupt
+
+		/* Restore the context of the first task that is going to run. */
+		portRESTORE_CONTEXT
+/*-----------------------------------------------------------*/          
+      		
+
+		/* Place the tick ISR in the correct vector. */
+		.VECTORS
+		
+		.KEEP
+		
+		ORG		TIMERA0_VECTOR
+		DW		_vTickISR
+		
+
+
+		END
+		
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Rowley/MSP430F449/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Rowley/MSP430F449/portmacro.h
new file mode 100644
index 0000000..bd8780f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Rowley/MSP430F449/portmacro.h
@@ -0,0 +1,132 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* Interrupt control macros. */
+#define portDISABLE_INTERRUPTS()	_DINT(); _NOP()
+#define portENABLE_INTERRUPTS()		_EINT();
+/*-----------------------------------------------------------*/
+
+/* Critical section control macros. */
+#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
+
+#define portENTER_CRITICAL()													\
+{																				\
+extern volatile uint16_t usCriticalNesting;							\
+																				\
+	portDISABLE_INTERRUPTS();													\
+																				\
+	/* Now interrupts are disabled usCriticalNesting can be accessed */			\
+	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
+	/* times portENTER_CRITICAL() has been called. */							\
+	usCriticalNesting++;														\
+}
+
+#define portEXIT_CRITICAL()														\
+{																				\
+extern volatile uint16_t usCriticalNesting;							\
+																				\
+	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
+	{																			\
+		/* Decrement the nesting count as we are leaving a critical section. */	\
+		usCriticalNesting--;													\
+																				\
+		/* If the nesting level has reached zero then interrupts should be */	\
+		/* re-enabled. */														\
+		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
+		{																		\
+			portENABLE_INTERRUPTS();											\
+		}																		\
+	}																			\
+}
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+
+/*
+ * Manual context switch called by portYIELD or taskYIELD.
+ */
+extern void vPortYield( void );
+#define portYIELD() vPortYield()
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			2
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portNOP()
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel
+
+#if configINTERRUPT_EXAMPLE_METHOD == 2
+
+extern void vTaskSwitchContext( void );
+#define portYIELD_FROM_ISR( x ) if( x ) vTaskSwitchContext()
+
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/SDCC/Cygnal/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/SDCC/Cygnal/port.c
new file mode 100644
index 0000000..c7ca00f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/SDCC/Cygnal/port.c
@@ -0,0 +1,424 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Cygnal port.
+ *----------------------------------------------------------*/
+
+/* Standard includes. */
+#include <string.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to setup timer 2 to produce the RTOS tick. */
+#define portCLOCK_DIVISOR				( ( uint32_t ) 12 )
+#define portMAX_TIMER_VALUE				( ( uint32_t ) 0xffff )
+#define portENABLE_TIMER				( ( uint8_t ) 0x04 )
+#define portTIMER_2_INTERRUPT_ENABLE	( ( uint8_t ) 0x20 )
+
+/* The value used in the IE register when a task first starts. */
+#define portGLOBAL_INTERRUPT_BIT	( ( StackType_t ) 0x80 )
+
+/* The value used in the PSW register when a task first starts. */
+#define portINITIAL_PSW				( ( StackType_t ) 0x00 )
+
+/* Macro to clear the timer 2 interrupt flag. */
+#define portCLEAR_INTERRUPT_FLAG()	TMR2CN &= ~0x80;
+
+/* Used during a context switch to store the size of the stack being copied
+to or from XRAM. */
+data static uint8_t ucStackBytes;
+
+/* Used during a context switch to point to the next byte in XRAM from/to which
+a RAM byte is to be copied. */
+xdata static StackType_t * data pxXRAMStack;
+
+/* Used during a context switch to point to the next byte in RAM from/to which
+an XRAM byte is to be copied. */
+data static StackType_t * data pxRAMStack;
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/*
+ * Setup the hardware to generate an interrupt off timer 2 at the required 
+ * frequency.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*-----------------------------------------------------------*/
+/*
+ * Macro that copies the current stack from internal RAM to XRAM.  This is 
+ * required as the 8051 only contains enough internal RAM for a single stack, 
+ * but we have a stack for every task.
+ */
+#define portCOPY_STACK_TO_XRAM()																\
+{																								\
+	/* pxCurrentTCB points to a TCB which itself points to the location into					\
+	which the first	stack byte should be copied.  Set pxXRAMStack to point						\
+	to the location into which the first stack byte is to be copied. */							\
+	pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB );		\
+																								\
+	/* Set pxRAMStack to point to the first byte to be coped from the stack. */					\
+	pxRAMStack = ( data StackType_t * data ) configSTACK_START;								\
+																								\
+	/* Calculate the size of the stack we are about to copy from the current					\
+	stack pointer value. */																		\
+	ucStackBytes = SP - ( configSTACK_START - 1 );												\
+																								\
+	/* Before starting to copy the stack, store the calculated stack size so					\
+	the stack can be restored when the task is resumed. */										\
+	*pxXRAMStack = ucStackBytes;																\
+																								\
+	/* Copy each stack byte in turn.  pxXRAMStack is incremented first as we					\
+	have already stored the stack size into XRAM. */											\
+	while( ucStackBytes )																		\
+	{																							\
+		pxXRAMStack++;																			\
+		*pxXRAMStack = *pxRAMStack;																\
+		pxRAMStack++;																			\
+		ucStackBytes--;																			\
+	}																							\
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro that copies the stack of the task being resumed from XRAM into 
+ * internal RAM.
+ */
+#define portCOPY_XRAM_TO_STACK()																\
+{																								\
+	/* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to						\
+	copy the data back out of XRAM and into the stack. */										\
+	pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB );		\
+	pxRAMStack = ( data StackType_t * data ) ( configSTACK_START - 1 );						\
+																								\
+	/* The first value stored in XRAM was the size of the stack - i.e. the						\
+	number of bytes we need to copy back. */													\
+	ucStackBytes = pxXRAMStack[ 0 ];															\
+																								\
+	/* Copy the required number of bytes back into the stack. */								\
+	do																							\
+	{																							\
+		pxXRAMStack++;																			\
+		pxRAMStack++;																			\
+		*pxRAMStack = *pxXRAMStack;																\
+		ucStackBytes--;																			\
+	} while( ucStackBytes );																	\
+																								\
+	/* Restore the stack pointer ready to use the restored stack. */							\
+	SP = ( uint8_t ) pxRAMStack;														\
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to push the current execution context onto the stack, before the stack 
+ * is moved to XRAM. 
+ */
+#define portSAVE_CONTEXT()																		\
+{																								\
+	_asm																						\
+		/* Push ACC first, as when restoring the context it must be restored					\
+		last (it is used to set the IE register). */											\
+		push	ACC																				\
+		/* Store the IE register then disable interrupts. */									\
+		push	IE																				\
+		clr		_EA																				\
+		push	DPL																				\
+		push	DPH																				\
+		push	b																				\
+		push	ar2																				\
+		push	ar3																				\
+		push	ar4																				\
+		push	ar5																				\
+		push	ar6																				\
+		push	ar7																				\
+		push	ar0																				\
+		push	ar1																				\
+		push	PSW																				\
+	_endasm;																					\
+		PSW = 0;																				\
+	_asm																						\
+		push	_bp																				\
+	_endasm;																					\
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro that restores the execution context from the stack.  The execution 
+ * context was saved into the stack before the stack was copied into XRAM.
+ */
+#define portRESTORE_CONTEXT()																	\
+{																								\
+	_asm																						\
+		pop		_bp																				\
+		pop		PSW																				\
+		pop		ar1																				\
+		pop		ar0																				\
+		pop		ar7																				\
+		pop		ar6																				\
+		pop		ar5																				\
+		pop		ar4																				\
+		pop		ar3																				\
+		pop		ar2																				\
+		pop		b																				\
+		pop		DPH																				\
+		pop		DPL																				\
+		/* The next byte of the stack is the IE register.  Only the global						\
+		enable bit forms part of the task context.  Pop off the IE then set						\
+		the global enable bit to match that of the stored IE register. */						\
+		pop		ACC																				\
+		JB		ACC.7,0098$																		\
+		CLR		IE.7																			\
+		LJMP	0099$																			\
+	0098$:																						\
+		SETB	IE.7																			\
+	0099$:																						\
+		/* Finally pop off the ACC, which was the first register saved. */						\
+		pop		ACC																				\
+		reti																					\
+	_endasm;																					\
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint32_t ulAddress;
+StackType_t *pxStartOfStack;
+
+	/* Leave space to write the size of the stack as the first byte. */
+	pxStartOfStack = pxTopOfStack;
+	pxTopOfStack++;
+
+	/* Place a few bytes of known values on the bottom of the stack. 
+	This is just useful for debugging and can be uncommented if required.
+	*pxTopOfStack = 0x11;
+	pxTopOfStack++;
+	*pxTopOfStack = 0x22;
+	pxTopOfStack++;
+	*pxTopOfStack = 0x33;
+	pxTopOfStack++;
+	*/
+
+	/* Simulate how the stack would look after a call to the scheduler tick 
+	ISR. 
+
+	The return address that would have been pushed by the MCU. */
+	ulAddress = ( uint32_t ) pxCode;
+	*pxTopOfStack = ( StackType_t ) ulAddress;
+	ulAddress >>= 8;
+	pxTopOfStack++;
+	*pxTopOfStack = ( StackType_t ) ( ulAddress );
+	pxTopOfStack++;
+
+	/* Next all the registers will have been pushed by portSAVE_CONTEXT(). */
+	*pxTopOfStack = 0xaa;	/* acc */
+	pxTopOfStack++;	
+
+	/* We want tasks to start with interrupts enabled. */
+	*pxTopOfStack = portGLOBAL_INTERRUPT_BIT;
+	pxTopOfStack++;
+
+	/* The function parameters will be passed in the DPTR and B register as
+	a three byte generic pointer is used. */
+	ulAddress = ( uint32_t ) pvParameters;
+	*pxTopOfStack = ( StackType_t ) ulAddress;	/* DPL */
+	ulAddress >>= 8;
+	*pxTopOfStack++;
+	*pxTopOfStack = ( StackType_t ) ulAddress;	/* DPH */
+	ulAddress >>= 8;
+	pxTopOfStack++;
+	*pxTopOfStack = ( StackType_t ) ulAddress;	/* b */
+	pxTopOfStack++;
+
+	/* The remaining registers are straight forward. */
+	*pxTopOfStack = 0x02;	/* R2 */
+	pxTopOfStack++;
+	*pxTopOfStack = 0x03;	/* R3 */
+	pxTopOfStack++;
+	*pxTopOfStack = 0x04;	/* R4 */
+	pxTopOfStack++;
+	*pxTopOfStack = 0x05;	/* R5 */
+	pxTopOfStack++;
+	*pxTopOfStack = 0x06;	/* R6 */
+	pxTopOfStack++;
+	*pxTopOfStack = 0x07;	/* R7 */
+	pxTopOfStack++;
+	*pxTopOfStack = 0x00;	/* R0 */
+	pxTopOfStack++;
+	*pxTopOfStack = 0x01;	/* R1 */
+	pxTopOfStack++;
+	*pxTopOfStack = 0x00;	/* PSW */
+	pxTopOfStack++;
+	*pxTopOfStack = 0xbb;	/* BP */
+
+	/* Dont increment the stack size here as we don't want to include
+	the stack size byte as part of the stack size count.
+
+	Finally we place the stack size at the beginning. */
+	*pxStartOfStack = ( StackType_t ) ( pxTopOfStack - pxStartOfStack );
+
+	/* Unlike most ports, we return the start of the stack as this is where the
+	size of the stack is stored. */
+	return pxStartOfStack;
+}
+/*-----------------------------------------------------------*/
+
+/* 
+ * See header file for description. 
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup timer 2 to generate the RTOS tick. */
+	prvSetupTimerInterrupt();	
+
+	/* Make sure we start with the expected SFR page.  This line should not
+	really be required. */
+	SFRPAGE = 0;
+
+	/* Copy the stack for the first task to execute from XRAM into the stack,
+	restore the task context from the new stack, then start running the task. */
+	portCOPY_XRAM_TO_STACK();
+	portRESTORE_CONTEXT();
+
+	/* Should never get here! */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented for this port. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch.  The first thing we do is save the registers so we
+ * can use a naked attribute.
+ */
+void vPortYield( void ) _naked
+{
+	/* Save the execution context onto the stack, then copy the entire stack
+	to XRAM.  This is necessary as the internal RAM is only large enough to
+	hold one stack, and we want one per task. 
+	
+	PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH
+	IS REQUIRED. */
+	portSAVE_CONTEXT();
+	portCOPY_STACK_TO_XRAM();
+
+	/* Call the standard scheduler context switch function. */
+	vTaskSwitchContext();
+
+	/* Copy the stack of the task about to execute from XRAM into RAM and
+	restore it's context ready to run on exiting. */
+	portCOPY_XRAM_TO_STACK();
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 1
+	void vTimer2ISR( void ) interrupt 5 _naked
+	{
+		/* Preemptive context switch function triggered by the timer 2 ISR.
+		This does the same as vPortYield() (see above) with the addition
+		of incrementing the RTOS tick count. */
+
+		portSAVE_CONTEXT();
+		portCOPY_STACK_TO_XRAM();
+
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			vTaskSwitchContext();
+		}
+		
+		portCLEAR_INTERRUPT_FLAG();
+		portCOPY_XRAM_TO_STACK();
+		portRESTORE_CONTEXT();
+	}
+#else
+	void vTimer2ISR( void ) interrupt 5
+	{
+		/* When using the cooperative scheduler the timer 2 ISR is only 
+		required to increment the RTOS tick count. */
+
+		xTaskIncrementTick();
+		portCLEAR_INTERRUPT_FLAG();
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+uint8_t ucOriginalSFRPage;
+
+/* Constants calculated to give the required timer capture values. */
+const uint32_t ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR;
+const uint32_t ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ;
+const uint32_t ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime;
+const uint8_t ucLowCaptureByte = ( uint8_t ) ( ulCaptureValue & ( uint32_t ) 0xff );
+const uint8_t ucHighCaptureByte = ( uint8_t ) ( ulCaptureValue >> ( uint32_t ) 8 );
+
+	/* NOTE:  This uses a timer only present on 8052 architecture. */
+
+	/* Remember the current SFR page so we can restore it at the end of the
+	function. */
+	ucOriginalSFRPage = SFRPAGE;
+	SFRPAGE = 0;
+
+	/* TMR2CF can be left in its default state. */	
+	TMR2CF = ( uint8_t ) 0;
+
+	/* Setup the overflow reload value. */
+	RCAP2L = ucLowCaptureByte;
+	RCAP2H = ucHighCaptureByte;
+
+	/* The initial load is performed manually. */
+	TMR2L = ucLowCaptureByte;
+	TMR2H = ucHighCaptureByte;
+
+	/* Enable the timer 2 interrupts. */
+	IE |= portTIMER_2_INTERRUPT_ENABLE;
+
+	/* Interrupts are disabled when this is called so the timer can be started
+	here. */
+	TMR2CN = portENABLE_TIMER;
+
+	/* Restore the original SFR page. */
+	SFRPAGE = ucOriginalSFRPage;
+}
+
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/SDCC/Cygnal/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/SDCC/Cygnal/portmacro.h
new file mode 100644
index 0000000..0c51e56
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/SDCC/Cygnal/portmacro.h
@@ -0,0 +1,115 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#if configUSE_PREEMPTION == 0
+	void vTimer2ISR( void ) interrupt 5;
+#else
+	void vTimer2ISR( void ) interrupt 5 _naked;
+#endif
+
+void vSerialISR( void ) interrupt 4;
+
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		float
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint8_t
+#define portBASE_TYPE	char
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#define portENTER_CRITICAL()		_asm		\
+									push	ACC	\
+									push	IE	\
+									_endasm;	\
+									EA = 0;
+
+#define portEXIT_CRITICAL()			_asm			\
+									pop		ACC		\
+									_endasm;		\
+									ACC &= 0x80;	\
+									IE |= ACC;		\
+									_asm			\
+									pop		ACC		\
+									_endasm;
+
+#define portDISABLE_INTERRUPTS()	EA = 0;
+#define portENABLE_INTERRUPTS()		EA = 1;
+/*-----------------------------------------------------------*/
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT			1
+#define portSTACK_GROWTH			( 1 )
+#define portTICK_PERIOD_MS			( ( uint32_t ) 1000 / configTICK_RATE_HZ )
+/*-----------------------------------------------------------*/
+
+/* Task utilities. */
+void vPortYield( void ) _naked;
+#define portYIELD()	vPortYield();
+/*-----------------------------------------------------------*/
+
+#define portNOP()				_asm	\
+									nop \
+								_endasm;
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#endif /* PORTMACRO_H */
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c
new file mode 100644
index 0000000..fe70d48
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c
@@ -0,0 +1,23 @@
+#include "FreeRTOSConfig.h"
+#include <stdlib.h>
+
+	static  long         brk_siz  =  0;
+//	#if  configTOTAL_HEAP_SIZE != 0
+	typedef int          _heep_t;
+	#define ROUNDUP(s)   (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1))
+	static  _heep_t      _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)];
+	#define              _heep_size      ROUNDUP(configTOTAL_HEAP_SIZE)
+/*	#else
+	extern  char        *_heep;
+	extern  long        _heep_size;
+	#endif
+*/	
+	extern  char  *sbrk(int  size)
+	{
+	   if  (brk_siz  +  size  >  _heep_size  ||  brk_siz  +  size  <  0)
+
+          return((char*)-1);
+	   brk_siz  +=  size;
+	   return(  (char*)_heep  +  brk_siz  -  size);
+	}
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB91460/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB91460/port.c
new file mode 100644
index 0000000..b8faac0
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB91460/port.c
@@ -0,0 +1,321 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "mb91467d.h"
+
+/*-----------------------------------------------------------*/
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+ 
+#pragma asm
+#macro  SaveContext
+	 ORCCR #0x20								;Switch to user stack
+	 ST RP,@-R15								;Store RP
+	 STM0 (R7,R6,R5,R4,R3,R2,R1,R0)				;Store R7-R0
+	 STM1 (R14,R13,R12,R11,R10,R9,R8)			;Store R14-R8
+	 ST MDH, @-R15								;Store MDH
+	 ST MDL, @-R15								;Store MDL
+	 
+	 ANDCCR #0xDF								;Switch back to system stack
+	 LD @R15+,R0								;Store PC to R0 
+	 ORCCR #0x20								;Switch to user stack
+	 ST R0,@-R15								;Store PC to User stack
+	 
+	 ANDCCR #0xDF								;Switch back to system stack
+	 LD @R15+,R0								;Store PS to R0
+	 ORCCR #0x20								;Switch to user stack
+	 ST R0,@-R15								;Store PS to User stack
+	 
+	 LDI #_pxCurrentTCB, R0						;Get pxCurrentTCB address
+	 LD @R0, R0									;Get the pxCurrentTCB->pxTopOfStack address
+	 ST R15,@R0									;Store USP to pxCurrentTCB->pxTopOfStack
+	 
+	 ANDCCR #0xDF								;Switch back to system stack for the rest of tick ISR
+#endm
+
+#macro RestoreContext
+	 LDI #_pxCurrentTCB, R0						;Get pxCurrentTCB address
+	 LD @R0, R0									;Get the pxCurrentTCB->pxTopOfStack address
+	 ORCCR #0x20								;Switch to user stack
+	 LD @R0, R15								;Restore USP from pxCurrentTCB->pxTopOfStack
+
+	 LD @R15+,R0								;Store PS to R0
+	 ANDCCR #0xDF								;Switch to system stack
+	 ST R0,@-R15								;Store PS to system stack
+
+	 ORCCR #0x20								;Switch to user stack
+	 LD @R15+,R0								;Store PC to R0
+	 ANDCCR #0xDF								;Switch to system stack
+	 ST R0,@-R15								;Store PC to system stack
+
+	 ORCCR #0x20								;Switch back to retrieve the remaining context
+
+	 LD @R15+, MDL								;Restore MDL
+	 LD @R15+, MDH								;Restore MDH
+	 LDM1 (R14,R13,R12,R11,R10,R9,R8)			;Restore R14-R8
+	 LDM0 (R7,R6,R5,R4,R3,R2,R1,R0)				;Restore R7-R0
+	 LD @R15+, RP								;Restore RP
+	 
+	 ANDCCR #0xDF								;Switch back to system stack for the rest of tick ISR
+#endm
+#pragma endasm
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform hardware setup to enable ticks from timer 1,
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ * 
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Place a few bytes of known values on the bottom of the stack. 
+	This is just useful for debugging. */
+
+	*pxTopOfStack = 0x11111111;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x22222222;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x33333333;
+	pxTopOfStack--;
+
+	/* This is a redundant push to the stack, it may be required if 
+	in some implementations of the compiler the parameter to the task 
+	is passed on to the stack rather than in R4 register. */
+	*pxTopOfStack = (StackType_t)(pvParameters);
+	pxTopOfStack--;                  
+    
+	*pxTopOfStack = ( StackType_t ) 0x00000000;	/* RP */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00007777;	/* R7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00006666;	/* R6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00005555;	/* R5 */
+	pxTopOfStack--;
+	
+	/* In the current implementation of the compiler the first 
+	parameter to the task (or function) is passed via R4 parameter 
+	to the task, hence the pvParameters pointer is copied into the R4 
+	register. See compiler manual section 4.6.2 for more information. */
+	*pxTopOfStack = ( StackType_t ) (pvParameters);	/* R4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00003333;	/* R3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00002222;	/* R2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00001111;	/* R1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00000001;	/* R0 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x0000EEEE;	/* R14 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0000DDDD;	/* R13 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0000CCCC;	/* R12 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0000BBBB;	/* R11 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0000AAAA;	/* R10 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00009999;	/* R9 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x00008888;	/* R8 */
+	pxTopOfStack--;	
+	*pxTopOfStack = ( StackType_t ) 0x11110000;	/* MDH */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x22220000;	/* MDL */
+	pxTopOfStack--;
+
+	/* The start of the task code. */
+	*pxTopOfStack = ( StackType_t ) pxCode;	/* PC */
+	pxTopOfStack--;
+	 
+    /* PS - User Mode, USP, ILM=31, Interrupts enabled */
+	*pxTopOfStack = ( StackType_t ) 0x001F0030;	/* PS */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick. */
+	prvSetupTimerInterrupt();
+
+	/* Restore the context of the first task that is going to run. */
+	#pragma asm
+		RestoreContext
+	#pragma endasm
+
+	/* Simulate a function call end as generated by the compiler.  We will now
+	jump to the start of the task the context of which we have just restored. */	
+	__asm(" reti ");
+
+	/* Should not get here. */
+	return pdFAIL;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented - unlikely to ever be required as there is nothing to
+	return to. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupTimerInterrupt( void )
+{
+/* The peripheral clock divided by 32 is used by the timer. */
+const uint16_t usReloadValue = ( uint16_t ) ( ( ( configPER_CLOCK_HZ / configTICK_RATE_HZ ) / 32UL ) - 1UL );
+
+	/* Setup RLT0 to generate a tick interrupt. */
+
+	TMCSR0_CNTE = 0;		/* Count Disable */
+    TMCSR0_CSL = 0x2;		/* CLKP/32 */
+    TMCSR0_MOD = 0;			/* Software trigger */
+    TMCSR0_RELD = 1;		/* Reload */
+    
+    TMCSR0_UF = 0;			/* Clear underflow flag */
+	TMRLR0 = usReloadValue;
+	TMCSR0_INTE = 1;		/* Interrupt Enable */
+	TMCSR0_CNTE = 1;		/* Count Enable */
+	TMCSR0_TRG = 1;			/* Trigger */
+	
+    PORTEN = 0x3;			/* Port Enable */
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 1
+
+	/* 
+	 * Tick ISR for preemptive scheduler. The tick count is incremented 
+	 * after the context is saved. Then the context is switched if required,
+	 * and last the context of the task which is to be resumed is restored.
+	 */
+
+	#pragma asm
+
+	.global _ReloadTimer0_IRQHandler
+	_ReloadTimer0_IRQHandler:
+
+	ANDCCR #0xEF							;Disable Interrupts
+	SaveContext								;Save context
+	ORCCR #0x10								;Re-enable Interrupts
+
+	LDI #0xFFFB,R1
+	LDI #_tmcsr0, R0
+	AND R1,@R0								;Clear RLT0 interrupt flag
+
+	CALL32	 _xTaskIncrementTick,R12		;Increment Tick
+	CALL32	 _vTaskSwitchContext,R12		;Switch context if required
+
+	ANDCCR #0xEF							;Disable Interrupts
+	RestoreContext							;Restore context
+	ORCCR #0x10								;Re-enable Interrupts
+
+	RETI
+
+	#pragma endasm
+	
+#else
+	
+	/* 
+	 * Tick ISR for the cooperative scheduler.  All this does is increment the
+	 * tick count.  We don't need to switch context, this can only be done by
+	 * manual calls to taskYIELD();
+	 */
+	__interrupt void ReloadTimer0_IRQHandler( void )
+	{
+		/* Clear RLT0 interrupt flag */
+		TMCSR0_UF = 0; 
+		xTaskIncrementTick();
+	}
+
+#endif
+
+/*
+ * Manual context switch. We can use a __nosavereg attribute  as the context 
+ * would be saved by PortSAVE_CONTEXT().  The context is switched and then 
+ * the context of the new task is restored saved. 
+ */
+#pragma asm
+
+	.global _vPortYieldDelayed
+	_vPortYieldDelayed:
+
+	ANDCCR #0xEF							;Disable Interrupts
+	SaveContext								;Save context
+	ORCCR #0x10								;Re-enable Interrupts
+
+	LDI #_dicr, R0
+	BANDL #0x0E, @R0						;Clear Delayed interrupt flag
+
+	CALL32	 _vTaskSwitchContext,R12		;Switch context if required
+
+	ANDCCR #0xEF							;Disable Interrupts
+	RestoreContext							;Restore context
+	ORCCR #0x10								;Re-enable Interrupts
+
+	RETI
+
+#pragma endasm
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch. We can use a __nosavereg attribute  as the context 
+ * would be saved by PortSAVE_CONTEXT().  The context is switched and then 
+ * the context of the new task is restored saved. 
+ */ 	 
+#pragma asm
+
+	.global _vPortYield
+	_vPortYield:
+
+	SaveContext								;Save context
+	CALL32	 _vTaskSwitchContext,R12		;Switch context if required
+	RestoreContext							;Restore context
+	
+	RETI
+
+#pragma endasm
+/*-----------------------------------------------------------*/
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB91460/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB91460/portmacro.h
new file mode 100644
index 0000000..6f4bcf2
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB91460/portmacro.h
@@ -0,0 +1,109 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* Hardware specific includes. */
+#include "mb91467d.h"
+
+/* Standard includes. */
+#include <stddef.h>
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+#if configKERNEL_INTERRUPT_PRIORITY != 30
+	#error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - 30 (1Eh) being the default.
+#endif
+#define portDISABLE_INTERRUPTS() __asm(" STILM #1Eh ")
+#define portENABLE_INTERRUPTS() __asm(" STILM #1Fh ")
+
+#define portENTER_CRITICAL()	\
+	__asm(" ST PS,@-R15 ");		\
+	__asm(" ANDCCR #0xef ");	\
+
+
+#define portEXIT_CRITICAL()		\
+	__asm(" LD @R15+,PS ");		\
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			4
+#define portNOP()					__asm( " nop " );
+/*-----------------------------------------------------------*/
+
+/* portYIELD() uses a SW interrupt */
+#define portYIELD()					__asm( " INT #40H " );
+
+/* portYIELD_FROM_ISR() uses delayed interrupt */
+#define portYIELD_FROM_ISR()			DICR_DLYI = 1
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE
+
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB96340/__STD_LIB_sbrk.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB96340/__STD_LIB_sbrk.c
new file mode 100644
index 0000000..a520aff
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB96340/__STD_LIB_sbrk.c
@@ -0,0 +1,28 @@
+/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
+/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
+/* ELIGIBILITY FOR ANY PURPOSES.                                             */
+/*                 (C) Fujitsu Microelectronics Europe GmbH                  */
+/*---------------------------------------------------------------------------
+  __STD_LIB_sbrk.C
+  - Used by heap_3.c for memory accocation and deletion.
+
+/*---------------------------------------------------------------------------*/
+
+#include "FreeRTOSConfig.h"
+#include <stdlib.h>
+
+	static  long         brk_siz  =  0;
+	typedef int          _heep_t;
+	#define ROUNDUP(s)   (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1))
+	static  _heep_t      _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)];
+	#define              _heep_size      ROUNDUP(configTOTAL_HEAP_SIZE)
+
+	extern  char  *sbrk(int  size)
+	{
+	   if  (brk_siz  +  size  >  _heep_size  ||  brk_siz  +  size  <  0)
+
+          return((char*)-1);
+	   brk_siz  +=  size;
+	   return(  (char*)_heep  +  brk_siz  -  size);
+	}
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB96340/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB96340/port.c
new file mode 100644
index 0000000..813db10
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB96340/port.c
@@ -0,0 +1,509 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the 16FX port.
+ *----------------------------------------------------------*/
+
+/* 
+ * Get current value of DPR and ADB registers 
+ */
+StackType_t xGet_DPR_ADB_bank( void ); 
+
+/* 
+ * Get current value of DTB and PCB registers 
+ */
+StackType_t xGet_DTB_PCB_bank( void );
+
+/*
+ * Sets up the periodic ISR used for the RTOS tick.  This uses RLT0, but
+ * can be done using any given RLT.
+ */
+static void prvSetupRLT0Interrupt( void );
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * We require the address of the pxCurrentTCB variable, but don't want to know
+ * any details of its type. 
+ */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * Macro to save a task context to the task stack. This macro  copies the 
+ * saved context (AH:AL, DPR:ADB, DTB:PCB , PC and PS) from  the   system 
+ * stack to task stack pointed by user stack pointer ( USP  for SMALL and 
+ * MEDIUM memory model amd USB:USP for COMPACT  and LARGE memory model ),
+ * then  it pushes the general purpose registers RW0-RW7  on  to the task 
+ * stack. Finally the  resultant  stack  pointer  value is saved into the 
+ * task  control  block  so  it  can  be retrieved the next time the task 
+ * executes.
+ */ 
+#if( ( configMEMMODEL == portSMALL ) || ( configMEMMODEL == portMEDIUM ) )
+
+	#define portSAVE_CONTEXT()											\
+			{	__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+	    		__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");		\
+				__asm(" MOVW A, _pxCurrentTCB ");						\
+				__asm(" MOVW A, SP ");									\
+  				__asm(" SWAPW ");										\
+				__asm(" MOVW @AL, AH ");								\
+				__asm(" OR   CCR,#H'20 ");								\
+			}
+
+/* 
+ * Macro to restore a task context from the task stack.  This is effecti-
+ * vely the reverse of SAVE_CONTEXT(). First the stack pointer  value
+ * (USP for SMALL and MEDIUM memory model amd  USB:USP  for  COMPACT  and 
+ * LARGE memory model ) is loaded from the task  control block.  Next the 
+ * value of all the general purpose registers RW0-RW7 is retrieved. Fina-
+ * lly it copies of the context ( AH:AL,  DPR:ADB, DTB:PCB, PC and PS) of 
+ * the task to be executed upon RETI from user stack to system stack.  
+ */
+ 
+	#define portRESTORE_CONTEXT()										\
+			{	__asm(" MOVW A, _pxCurrentTCB ");						\
+				__asm(" MOVW A, @A ");									\
+  				__asm(" AND  CCR,#H'DF ");  							\
+  				__asm(" MOVW SP, A ");									\
+				__asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");		\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+			}
+		
+#elif( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
+
+	#define portSAVE_CONTEXT()											\
+			{	__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+	    		__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" POPW  A ");										\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" PUSHW  A ");									\
+				__asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");		\
+				__asm(" MOVL A, _pxCurrentTCB ");						\
+				__asm(" MOVL RL2, A ");									\
+				__asm(" MOVW A, SP ");									\
+				__asm(" MOVW @RL2+0, A ");								\
+				__asm(" MOV A, USB ");									\
+				__asm(" MOV @RL2+2, A ");								\
+			}	
+            
+	#define portRESTORE_CONTEXT()										\
+			{	__asm(" MOVL A, _pxCurrentTCB ");						\
+				__asm(" MOVL RL2, A ");									\
+				__asm(" MOVW A, @RL2+0 ");								\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" MOVW SP, A ");									\
+				__asm(" MOV A, @RL2+2 ");								\
+				__asm(" MOV USB, A ");									\
+				__asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");		\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+				__asm(" AND  CCR,#H'DF ");  							\
+				__asm(" POPW  A ");										\
+				__asm(" OR   CCR,#H'20 ");								\
+				__asm(" PUSHW  A ");									\
+			}
+#endif
+
+/*-----------------------------------------------------------*/	
+
+/* 
+ * Functions for obtaining the current value  of  DPR:ADB, DTB:PCB bank registers
+ */
+ 
+#pragma asm
+
+        .GLOBAL    _xGet_DPR_ADB_bank
+        .GLOBAL    _xGet_DTB_PCB_bank
+        .SECTION   CODE, CODE, ALIGN=1
+
+_xGet_DPR_ADB_bank:
+
+    MOV A, DPR
+    SWAP
+    MOV A, ADB
+    ORW A
+	#if configMEMMODEL == portMEDIUM || configMEMMODEL == portLARGE
+		RETP
+	#elif configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT   
+		RET
+	#endif 
+
+
+_xGet_DTB_PCB_bank:
+
+    MOV A, DTB
+    SWAP
+    MOV A, PCB
+    ORW A
+	#if configMEMMODEL == portMEDIUM || configMEMMODEL == portLARGE
+		RETP
+	#elif configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT   
+		RET
+	#endif 
+
+#pragma endasm
+/*-----------------------------------------------------------*/
+
+/* 
+ * Initialise the stack of a task to look exactly as if a call to 
+ * portSAVE_CONTEXT had been called.
+ * 
+ * See the header file portable.h.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Place a few bytes of known values on the bottom of the stack. 
+	This is just useful for debugging. */
+	*pxTopOfStack = 0x1111;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2222;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x3333;
+	pxTopOfStack--;
+
+	/* Once the task is called the task  would  push  the  pointer to the
+	parameter onto the stack. Hence here the pointer would be copied to the stack
+	first.  When using the COMPACT or LARGE memory model the pointer would be 24 
+	bits, and when using the SMALL or MEDIUM memory model the pointer would be 16 
+	bits. */ 
+	#if( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
+	{
+		*pxTopOfStack = ( StackType_t ) ( ( uint32_t ) ( pvParameters ) >> 16 );
+		pxTopOfStack--;         
+	}
+	#endif
+
+    *pxTopOfStack = ( StackType_t ) ( pvParameters );
+    pxTopOfStack--;                  
+    
+    /* This is redundant push to the stack. This is required in order to introduce 
+    an offset so that the task accesses a parameter correctly that is passed on to 
+    the task stack. */
+	#if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
+	{
+		*pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff );      
+		pxTopOfStack--;       
+	}
+	#endif
+
+    /* This is redundant push to the stack. This is required in order to introduce 
+    an offset so the task correctly accesses the parameter passed on the task stack. */
+    *pxTopOfStack = ( StackType_t ) ( pxCode );
+    pxTopOfStack--;       
+
+    /* PS - User Mode, ILM=7, RB=0, Interrupts enabled,USP */
+    *pxTopOfStack = 0xE0C0;							
+	pxTopOfStack--; 
+
+	/* PC */
+	*pxTopOfStack = ( StackType_t ) ( pxCode );     
+    pxTopOfStack--;      
+    
+    /* DTB | PCB */
+	#if configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT
+	{
+		*pxTopOfStack = xGet_DTB_PCB_bank();         	
+		pxTopOfStack--;
+	}
+	#endif
+
+	/* DTB | PCB, in case of MEDIUM and LARGE memory models, PCB would be used
+	along with PC to indicate the start address of the function. */
+	#if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
+	{
+		*pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff );
+		pxTopOfStack--;       
+	}
+	#endif
+
+	/* DPR | ADB  */
+	*pxTopOfStack = xGet_DPR_ADB_bank();				
+	pxTopOfStack--;
+    
+	/* AL */
+	*pxTopOfStack = ( StackType_t ) 0x9999;		
+	pxTopOfStack--;
+
+	/* AH */
+	*pxTopOfStack = ( StackType_t ) 0xAAAA;		
+	pxTopOfStack--;
+	
+	/* Next the general purpose registers. */
+	*pxTopOfStack = ( StackType_t ) 0x7777;	/* RW7 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x6666;	/* RW6 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x5555;	/* RW5 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x4444;	/* RW4 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x3333;	/* RW3 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x2222;	/* RW2 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x1111;	/* RW1 */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x8888;	/* RW0 */
+		
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupRLT0Interrupt( void )
+{
+/* The peripheral clock divided by 16 is used by the timer. */
+const uint16_t usReloadValue = ( uint16_t ) ( ( ( configCLKP1_CLOCK_HZ / configTICK_RATE_HZ ) / 16UL ) - 1UL );
+
+	/* set reload value = 34999+1, TICK Interrupt after 10 ms @ 56MHz of CLKP1 */
+	TMRLR0 = usReloadValue;    
+    
+    /* prescaler 1:16, reload, interrupt enable, count enable, trigger */
+    TMCSR0 = 0x041B;    
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	/* Setup the hardware to generate the tick. */
+	prvSetupRLT0Interrupt();
+	
+	/* Restore the context of the first task that is going to run. */
+	portRESTORE_CONTEXT();
+
+	/* Simulate a function call end as generated by the compiler.  We will now
+	jump to the start of the task the context of which we have just restored. */	
+	__asm(" reti ");
+
+
+	/* Should not get here. */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented - unlikely to ever be required as there is nothing to
+	return to. */
+}
+
+/*-----------------------------------------------------------*/
+
+/* 
+ * The interrupt service routine used depends on whether the pre-emptive
+ * scheduler is being used or not.
+ */
+
+#if configUSE_PREEMPTION == 1
+
+	/* 
+	 * Tick ISR for preemptive scheduler.  We can use a __nosavereg attribute
+	 * as the context is to be saved by the portSAVE_CONTEXT() macro, not the
+	 * compiler generated code.  The tick count is incremented after the context 
+	 * is saved. 
+	 */
+	__nosavereg __interrupt void prvRLT0_TICKISR( void )
+	{
+		/* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */
+		__DI();
+		
+		/* Save the context of the interrupted task. */
+		portSAVE_CONTEXT();
+		
+		/* Enable interrupts */
+		__EI();
+		
+		/* Clear RLT0 interrupt flag */
+		TMCSR0_UF = 0;      
+		
+		/* Increment the tick count then switch to the highest priority task
+		that is ready to run. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			vTaskSwitchContext();
+		}
+
+		/* Disable interrupts so that portRESTORE_CONTEXT() is not interrupted */
+		__DI();
+		
+		/* Restore the context of the new task. */
+		portRESTORE_CONTEXT();
+		
+		/* Enable interrupts */
+		__EI();
+	}
+
+#else
+
+	/*
+	 * Tick ISR for the cooperative scheduler.  All this does is increment the
+	 * tick count.  We don't need to switch context, this can only be done by
+	 * manual calls to taskYIELD();
+	 */
+	__interrupt void prvRLT0_TICKISR( void )
+	{
+		/* Clear RLT0 interrupt flag */
+		TMCSR0_UF = 0;  
+		
+		xTaskIncrementTick();
+	}
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch. We can use a __nosavereg attribute  as the context 
+ * is to be saved by the portSAVE_CONTEXT() macro, not the compiler generated 
+ * code.
+ */
+__nosavereg __interrupt void vPortYield( void )
+{
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT();
+	
+	/* Switch to the highest priority task that is ready to run. */
+	vTaskSwitchContext();
+	
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+__nosavereg __interrupt void vPortYieldDelayed( void )
+{    
+    /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */      
+	__DI();
+	
+	/* Save the context of the interrupted task. */
+	portSAVE_CONTEXT();
+	
+	/* Enable interrupts */
+	__EI();
+				
+	/* Clear delayed interrupt flag */
+    __asm (" CLRB  03A4H:0 ");
+	
+	/* Switch to the highest priority task that is ready to run. */
+	vTaskSwitchContext();
+	
+	/* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */   
+	__DI();
+	
+	/* Restore the context of the new task. */
+	portRESTORE_CONTEXT();
+
+	/* Enable interrupts */
+	__EI();
+}	
+/*-----------------------------------------------------------*/
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB96340/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB96340/portmacro.h
new file mode 100644
index 0000000..941cd2a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Softune/MB96340/portmacro.h
@@ -0,0 +1,116 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* Standard includes. */
+#include <stddef.h>
+
+/* Constants denoting the available memory models.  These are used within
+FreeRTOSConfig.h to set the configMEMMODEL value. */
+#define portSMALL     0
+#define portMEDIUM    1
+#define portCOMPACT   2
+#define portLARGE     3
+
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section handling. */
+#if configKERNEL_INTERRUPT_PRIORITY != 6
+	#error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - #06H being the default.
+#endif
+#define portDISABLE_INTERRUPTS()	__asm(" MOV ILM, #06h ")
+#define portENABLE_INTERRUPTS()		__asm(" MOV ILM, #07h ")
+
+#define portENTER_CRITICAL()								\
+		{	__asm(" PUSHW PS ");							\
+			portDISABLE_INTERRUPTS();						\
+		}
+
+#define portEXIT_CRITICAL()									\
+		{	__asm(" POPW PS ");								\
+		}
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			2
+#define portNOP()					__asm( " NOP " );
+/*-----------------------------------------------------------*/
+
+/* portYIELD() uses SW interrupt */
+#define portYIELD()					__asm( " INT #122 " );
+
+/* portYIELD_FROM_ISR() uses delayed interrupt */
+#define portYIELD_FROM_ISR()		 __asm( " SETB  03A4H:0 " );
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE
+
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c
new file mode 100644
index 0000000..76b570f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c
@@ -0,0 +1,267 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+* Implementation of functions defined in portable.h for the ARM CM4F port.
+*----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* Constants required to manipulate the NVIC. */
+#define portNVIC_SYSTICK_CTRL       ( ( volatile uint32_t * ) 0xe000e010 )
+#define portNVIC_SYSTICK_LOAD       ( ( volatile uint32_t * ) 0xe000e014 )
+#define portNVIC_SHPR3_REG          ( ( volatile uint32_t * ) 0xe000ed20 )
+#define portNVIC_SYSTICK_CLK        0x00000004
+#define portNVIC_SYSTICK_INT        0x00000002
+#define portNVIC_SYSTICK_ENABLE     0x00000001
+#define portNVIC_PENDSV_PRI         ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )
+#define portNVIC_SYSTICK_PRI        ( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK         ( 0xFFUL )
+
+/* Constants required to manipulate the VFP. */
+#define portFPCCR                   ( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
+#define portASPEN_AND_LSPEN_BITS    ( 0x3UL << 30UL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR            ( 0x01000000 )
+#define portINITIAL_EXC_RETURN      ( 0xfffffffd )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+ * prvTaskExitError() in case it messes up unwinding of the stack in the
+ * debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+    #define portTASK_RETURN_ADDRESS    configTASK_RETURN_ADDRESS
+#else
+    #define portTASK_RETURN_ADDRESS    prvTaskExitError
+#endif
+
+/* For strict compliance with the Cortex-M spec the task start address should
+ * have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK    ( ( StackType_t ) 0xfffffffeUL )
+
+/* The priority used by the kernel is assigned to a variable to make access
+ * from inline assembler easier. */
+const uint32_t ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;
+
+/* Each task maintains its own interrupt status in the critical nesting
+ * variable. */
+static uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
+
+/*
+ * Setup the timer to generate the tick interrupts.
+ */
+static void prvSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void SysTick_Handler( void );
+
+/*
+ * Functions defined in port_asm.asm.
+ */
+extern void vPortEnableVFP( void );
+extern void vPortStartFirstTask( void );
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/* This exists purely to allow the const to be used from within the
+ * port_asm.asm assembly file. */
+const uint32_t ulMaxSyscallInterruptPriorityConst = configMAX_SYSCALL_INTERRUPT_PRIORITY;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* Simulate the stack frame as it would be created by a context switch
+     * interrupt. */
+
+    /* Offset added to account for the way the MCU uses the stack on entry/exit
+     * of interrupts, and to ensure alignment. */
+    pxTopOfStack--;
+
+    *pxTopOfStack = portINITIAL_XPSR;                                    /* xPSR */
+    pxTopOfStack--;
+    *pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK; /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;             /* LR */
+
+    /* Save code space by skipping register initialisation. */
+    pxTopOfStack -= 5;                            /* R12, R3, R2 and R1. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+    /* A save method is being used that requires each task to maintain its
+     * own exec return value. */
+    pxTopOfStack--;
+    *pxTopOfStack = portINITIAL_EXC_RETURN;
+
+    pxTopOfStack -= 8; /* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+    /* A function that implements a task must not exit or attempt to return to
+     * its caller as there is nothing to return to.  If a task wants to exit it
+     * should instead call vTaskDelete( NULL ).
+     *
+     * Artificially force an assert() to be triggered if configASSERT() is
+     * defined, then stop here so application writers can catch the error. */
+    configASSERT( ulCriticalNesting == ~0UL );
+    portDISABLE_INTERRUPTS();
+
+    for( ; ; )
+    {
+    }
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+     * See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
+
+    /* Make PendSV and SysTick the lowest priority interrupts. */
+    *( portNVIC_SHPR3_REG ) |= portNVIC_PENDSV_PRI;
+    *( portNVIC_SHPR3_REG ) |= portNVIC_SYSTICK_PRI;
+
+    /* Start the timer that generates the tick ISR.  Interrupts are disabled
+     * here already. */
+    prvSetupTimerInterrupt();
+
+    /* Initialise the critical nesting count ready for the first task. */
+    ulCriticalNesting = 0;
+
+    /* Ensure the VFP is enabled - it should be anyway. */
+    vPortEnableVFP();
+
+    /* Lazy save always. */
+    *( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
+
+    /* Start the first task. */
+    vPortStartFirstTask();
+
+    /* Should not get here! */
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented in ports where there is nothing to return to.
+     * Artificially force an assert. */
+    configASSERT( ulCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortYield( void )
+{
+    /* Set a PendSV to request a context switch. */
+    *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+
+    /* Barriers are normally not required but do ensure the code is completely
+     * within the specified behaviour for the architecture. */
+    __DSB();
+    __ISB();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    ulCriticalNesting++;
+    __DSB();
+    __ISB();
+
+    /* This is not the interrupt safe version of the enter critical function so
+     * assert() if it is being called from an interrupt context.  Only API
+     * functions that end in "FromISR" can be used in an interrupt.  Only assert if
+     * the critical nesting count is 1 to protect against recursive calls if the
+     * assert function also uses a critical section. */
+    if( ulCriticalNesting == 1 )
+    {
+        configASSERT( ( ( *( portNVIC_INT_CTRL ) ) & portVECTACTIVE_MASK ) == 0 );
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    configASSERT( ulCriticalNesting );
+    ulCriticalNesting--;
+
+    if( ulCriticalNesting == 0 )
+    {
+        portENABLE_INTERRUPTS();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void SysTick_Handler( void )
+{
+    uint32_t ulDummy;
+
+    ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        if( xTaskIncrementTick() != pdFALSE )
+        {
+            /* Pend a context switch. */
+            *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+void prvSetupTimerInterrupt( void )
+{
+    /* Configure SysTick to interrupt at the requested rate. */
+    *( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+    *( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port_asm.asm b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port_asm.asm
new file mode 100644
index 0000000..2069ad4
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port_asm.asm
@@ -0,0 +1,236 @@
+;/*
+; * FreeRTOS Kernel V10.4.3
+; * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+; *
+; * Permission is hereby granted, free of charge, to any person obtaining a copy of
+; * this software and associated documentation files (the "Software"), to deal in
+; * the Software without restriction, including without limitation the rights to
+; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+; * the Software, and to permit persons to whom the Software is furnished to do so,
+; * subject to the following conditions:
+; *
+; * The above copyright notice and this permission notice shall be included in all
+; * copies or substantial portions of the Software.
+; *
+; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+; *
+; * https://www.FreeRTOS.org
+; * https://github.com/FreeRTOS
+; *
+; * 1 tab == 4 spaces!
+; */
+
+
+	.extern pxCurrentTCB
+	.extern vTaskSwitchContext
+	.extern ulMaxSyscallInterruptPriorityConst
+
+	.global _vector_14
+	.global _lc_ref__vector_pp_14
+	.global SVC_Handler
+	.global vPortStartFirstTask
+	.global vPortEnableVFP
+	.global ulPortSetInterruptMask
+	.global vPortClearInterruptMask
+
+;-----------------------------------------------------------
+
+	.section .text
+	.thumb
+	.align 4
+_vector_14: .type func
+
+	mrs r0, psp
+	isb
+
+	;Get the location of the current TCB.
+	ldr.w	r3, =pxCurrentTCB
+	ldr	r2, [r3]
+
+	;Is the task using the FPU context?  If so, push high vfp registers.
+	tst r14, #0x10
+	it eq
+	vstmdbeq r0!, {s16-s31}
+
+	;Save the core registers.
+	stmdb r0!, {r4-r11, r14}
+
+	;Save the new top of stack into the first member of the TCB.
+	str r0, [r2]
+
+	stmdb sp!, {r0, r3}
+	ldr.w r0, =ulMaxSyscallInterruptPriorityConst
+	ldr r0, [r0]
+	msr basepri, r0
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r0, r3}
+
+	;The first item in pxCurrentTCB is the task top of stack.
+	ldr r1, [r3]
+	ldr r0, [r1]
+
+	;Pop the core registers.
+	ldmia r0!, {r4-r11, r14}
+
+	;Is the task using the FPU context?  If so, pop the high vfp registers too.
+	tst r14, #0x10
+	it eq
+	vldmiaeq r0!, {s16-s31}
+
+	msr psp, r0
+	isb
+	bx r14
+
+	.size	_vector_14, $-_vector_14
+	.endsec
+
+;-----------------------------------------------------------
+
+; This function is an XMC4000 silicon errata workaround.  It will get used when
+; the SILICON_BUG_PMC_CM_001 linker macro is defined.
+	.section .text
+	.thumb
+	.align 4
+_lc_ref__vector_pp_14: .type func
+
+	mrs r0, psp
+	isb
+
+	;Get the location of the current TCB.
+	ldr.w	r3, =pxCurrentTCB
+	ldr	r2, [r3]
+
+	;Is the task using the FPU context?  If so, push high vfp registers.
+	tst r14, #0x10
+	it eq
+	vstmdbeq r0!, {s16-s31}
+
+	;Save the core registers.
+	stmdb r0!, {r4-r11, r14}
+
+	;Save the new top of stack into the first member of the TCB.
+	str r0, [r2]
+
+	stmdb sp!, {r3}
+	ldr.w r0, =ulMaxSyscallInterruptPriorityConst
+	ldr r0, [r0]
+	msr basepri, r0
+	bl vTaskSwitchContext
+	mov r0, #0
+	msr basepri, r0
+	ldmia sp!, {r3}
+
+	;The first item in pxCurrentTCB is the task top of stack.
+	ldr r1, [r3]
+	ldr r0, [r1]
+
+	;Pop the core registers.
+	ldmia r0!, {r4-r11, r14}
+
+	;Is the task using the FPU context?  If so, pop the high vfp registers too.
+	tst r14, #0x10
+	it eq
+	vldmiaeq r0!, {s16-s31}
+
+	msr psp, r0
+	isb
+	push { lr }
+	pop { pc } ; XMC4000 specific errata workaround.  Do not used "bx lr" here.
+
+	.size	_lc_ref__vector_pp_14, $-_lc_ref__vector_pp_14
+	.endsec
+
+;-----------------------------------------------------------
+
+	.section .text
+	.thumb
+	.align 4
+SVC_Handler: .type func
+	;Get the location of the current TCB.
+	ldr.w	r3, =pxCurrentTCB
+	ldr r1, [r3]
+	ldr r0, [r1]
+	;Pop the core registers.
+	ldmia r0!, {r4-r11, r14}
+	msr psp, r0
+	isb
+	mov r0, #0
+	msr	basepri, r0
+	bx r14
+	.size	SVC_Handler, $-SVC_Handler
+	.endsec
+
+;-----------------------------------------------------------
+
+	.section .text
+	.thumb
+	.align 4
+vPortStartFirstTask .type func
+	;Use the NVIC offset register to locate the stack.
+	ldr.w r0, =0xE000ED08
+	ldr r0, [r0]
+	ldr r0, [r0]
+	;Set the msp back to the start of the stack.
+	msr msp, r0
+	;Call SVC to start the first task.
+	cpsie i
+	cpsie f
+	dsb
+	isb
+	svc 0
+	.size	vPortStartFirstTask, $-vPortStartFirstTask
+	.endsec
+
+;-----------------------------------------------------------
+
+	.section .text
+	.thumb
+	.align 4
+vPortEnableVFP .type func
+	;The FPU enable bits are in the CPACR.
+	ldr.w r0, =0xE000ED88
+	ldr	r1, [r0]
+
+	;Enable CP10 and CP11 coprocessors, then save back.
+	orr	r1, r1, #( 0xf << 20 )
+	str r1, [r0]
+	bx	r14
+	.size	vPortEnableVFP, $-vPortEnableVFP
+	.endsec
+
+;-----------------------------------------------------------
+
+	.section .text
+	.thumb
+	.align 4
+ulPortSetInterruptMask:
+	mrs r0, basepri
+	ldr.w r1, =ulMaxSyscallInterruptPriorityConst
+	ldr r1, [r1]
+	msr basepri, r1
+	bx r14
+	.size	ulPortSetInterruptMask, $-ulPortSetInterruptMask
+	.endsec
+
+;-----------------------------------------------------------
+
+	.section .text
+	.thumb
+	.align 4
+vPortClearInterruptMask:
+	msr basepri, r0
+	bx r14
+	.size	vPortClearInterruptMask, $-vPortClearInterruptMask
+	.endsec
+
+;-----------------------------------------------------------
+
+	.end
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h
new file mode 100644
index 0000000..b2a48e8
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h
@@ -0,0 +1,132 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    uint32_t
+    #define portBASE_TYPE     long
+
+    typedef portSTACK_TYPE   StackType_t;
+    typedef long             BaseType_t;
+    typedef unsigned long    UBaseType_t;
+
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t     TickType_t;
+        #define portMAX_DELAY              ( TickType_t ) 0xffffffffUL
+
+/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+ * not need to be guarded with a critical section. */
+        #define portTICK_TYPE_IS_ATOMIC    1
+    #endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    8
+/*-----------------------------------------------------------*/
+
+
+/* Scheduler utilities. */
+    extern void vPortYield( void );
+    #define portNVIC_INT_CTRL     ( ( volatile uint32_t * ) 0xe000ed04 )
+    #define portNVIC_PENDSVSET    0x10000000
+    #define portYIELD()                                 vPortYield()
+
+    #define portEND_SWITCHING_ISR( xSwitchRequired )    if( xSwitchRequired ) *( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET
+    #define portYIELD_FROM_ISR( x )                     portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+
+/* Critical section management. */
+
+/*
+ * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other
+ * registers.  r0 is clobbered.
+ */
+    #define portSET_INTERRUPT_MASK()      __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+
+/*
+ * Set basepri back to 0 without effective other registers.
+ * r0 is clobbered.  FAQ:  Setting BASEPRI to 0 is not a bug.  Please see
+ * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.
+ */
+    #define portCLEAR_INTERRUPT_MASK()    __set_BASEPRI( 0 )
+
+    extern uint32_t ulPortSetInterruptMask( void );
+    extern void vPortClearInterruptMask( uint32_t ulNewMask );
+    #define portSET_INTERRUPT_MASK_FROM_ISR()         ulPortSetInterruptMask()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )    vPortClearInterruptMask( x )
+
+
+    extern void vPortEnterCritical( void );
+    extern void vPortExitCritical( void );
+
+    #define portDISABLE_INTERRUPTS()    portSET_INTERRUPT_MASK()
+    #define portENABLE_INTERRUPTS()     portCLEAR_INTERRUPT_MASK()
+    #define portENTER_CRITICAL()        vPortEnterCritical()
+    #define portEXIT_CRITICAL()         vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+    #define portNOP()
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/CDK/T-HEAD_CK802/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/CDK/T-HEAD_CK802/port.c
new file mode 100644
index 0000000..db8d50f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/CDK/T-HEAD_CK802/port.c
@@ -0,0 +1,150 @@
+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* Kernel includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+extern void vPortStartTask(void);
+
+/* Used to keep track of the number of nested calls to taskENTER_CRITICAL().  This
+will be set to 0 prior to the first task being started. */
+portLONG ulCriticalNesting = 0x9999UL;
+
+/* Used to record one tack want to swtich task after enter critical area, we need know it
+ * and implement task switch after exit critical area */
+portLONG pendsvflag = 0;
+
+StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+    StackType_t *stk  = NULL;
+
+    stk = pxTopOfStack;
+
+    *(--stk)  = (uint32_t)pxCode;            /* Entry Point                                         */
+    *(--stk)  = (uint32_t)0xE0000140L;       /* PSR                                                 */
+    *(--stk)  = (uint32_t)0xFFFFFFFEL;       /* R15 (LR) (init value will cause fault if ever used) */
+    *(--stk)  = (uint32_t)0x13131313L;       /* R13                                                 */
+    *(--stk)  = (uint32_t)0x12121212L;       /* R12                                                 */
+    *(--stk)  = (uint32_t)0x11111111L;       /* R11                                                 */
+    *(--stk)  = (uint32_t)0x10101010L;       /* R10                                                 */
+    *(--stk)  = (uint32_t)0x09090909L;       /* R9                                                  */
+    *(--stk)  = (uint32_t)0x08080808L;       /* R8                                                  */
+    *(--stk)  = (uint32_t)0x07070707L;       /* R7                                                  */
+    *(--stk)  = (uint32_t)0x06060606L;       /* R6                                                  */
+    *(--stk)  = (uint32_t)0x05050505L;       /* R5                                                  */
+    *(--stk)  = (uint32_t)0x04040404L;       /* R4                                                  */
+    *(--stk)  = (uint32_t)0x03030303L;       /* R3                                                  */
+    *(--stk)  = (uint32_t)0x02020202L;       /* R2                                                  */
+    *(--stk)  = (uint32_t)0x01010101L;       /* R1                                                  */
+    *(--stk)  = (uint32_t)pvParameters;      /* R0 : argument                                       */
+
+    return stk;
+}
+
+BaseType_t xPortStartScheduler( void )
+{
+    ulCriticalNesting = 0UL;
+
+    vPortStartTask();
+
+    return pdFALSE;
+}
+
+
+void vPortEndScheduler( void )
+{
+    /* Not implemented as there is nothing to return to. */
+}
+
+void vPortEnterCritical( void )
+{
+    portDISABLE_INTERRUPTS();
+    ulCriticalNesting ++;
+}
+
+void vPortExitCritical( void )
+{
+    if (ulCriticalNesting == 0) {
+        while(1);
+    }
+
+    ulCriticalNesting --;
+    if (ulCriticalNesting == 0)
+    {
+        portENABLE_INTERRUPTS();
+
+        if (pendsvflag)
+        {
+            pendsvflag = 0;
+            portYIELD();
+        }
+    }
+}
+
+#if configUSE_PREEMPTION == 0
+void xPortSysTickHandler( void )
+{
+    portLONG ulDummy;
+
+    ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+    xTaskIncrementTick();
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
+
+#else
+void xPortSysTickHandler( void )
+{
+    portLONG ulDummy;
+
+    ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        if (xTaskIncrementTick() != pdFALSE)
+        {
+            portYIELD_FROM_ISR(pdTRUE);
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
+}
+#endif
+
+void vPortYieldHandler( void )
+{
+    uint32_t ulSavedInterruptMask;
+
+    ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+
+    vTaskSwitchContext();
+
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
+}
+
+__attribute__((weak)) void vApplicationStackOverflowHook( xTaskHandle *pxTask, signed portCHAR *pcTaskName )
+{
+    for(;;);
+}
+
+__attribute__((weak)) void vApplicationMallocFailedHook( void )
+{
+    for(;;);
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/CDK/T-HEAD_CK802/portasm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/CDK/T-HEAD_CK802/portasm.S
new file mode 100644
index 0000000..693ec64
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/CDK/T-HEAD_CK802/portasm.S
@@ -0,0 +1,126 @@
+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * 1 tab == 4 spaces!
+ */
+
+//#include <csi_config.h>
+
+/********************************************************************
+ * Functions: vPortStartTask
+ *
+ ********************************************************************/
+.global vPortStartTask
+.type   vPortStartTask, %function
+vPortStartTask:
+    psrclr   ie
+    lrw      r4, pxCurrentTCB
+    ld.w     r4, (r4)                // the current task stack pointer is the first member
+    ld.w     sp, (r4)
+
+    ldw      r0, (sp, 64)
+    mtcr     r0, epc
+    ldw      r0, (sp, 60)
+    mtcr     r0, epsr
+    ldw      r15, (sp, 56)
+    ldm      r0-r13, (sp)
+    addi     sp, 68
+    rte
+
+/********************************************************************
+ * Functions: vPortYield
+ *
+ ********************************************************************/
+.global vPortYield
+.type   vPortYield, %function
+vPortYield:
+    psrclr  ee
+    subi    sp, 68
+    stm     r0-r13, (sp)
+    stw     r15, (sp, 56)
+    mfcr    r0, psr
+    bseti   r0, 8
+    stw     r0, (sp, 60)
+    stw     r15, (sp, 64)
+
+    lrw     r2, pxCurrentTCB
+    ld.w    r3, (r2)
+    st.w    sp, (r3)
+
+    jbsr    vTaskSwitchContext
+    lrw     r4, pxCurrentTCB
+    ld.w    r4, (r4)
+    ld.w    sp, (r4)
+
+    ldw     r0, (sp, 64)
+    mtcr    r0, epc
+    ldw     r0, (sp, 60)
+    mtcr    r0, epsr
+    ldw     r15, (sp, 56)
+    ldm     r0-r13, (sp)
+    addi    sp, 68
+
+    rte
+
+/********************************************************************
+ * Functions: NOVIC_IRQ_Default_Handler
+ *
+ ********************************************************************/
+.global NOVIC_IRQ_Default_Handler
+.type   NOVIC_IRQ_Default_Handler, %function
+NOVIC_IRQ_Default_Handler:
+    psrset  ee
+    subi    sp, 68
+    stm     r0-r13, (sp)
+    stw     r15, (sp, 56)
+    mfcr    r0, epsr
+    stw     r0, (sp, 60)
+    mfcr    r0, epc
+    stw     r0, (sp, 64)
+	
+    lrw     r7, pxCurrentTCB
+    ldw     r7, (r7)
+    stw     sp, (r7)
+
+    lrw     sp, g_top_irqstack
+
+    lrw     r1, g_irqvector
+    mfcr    r0, psr
+    lsri    r0, 16
+    sextb   r0
+    subi    r0, 32
+    lsli    r0, 2
+    add     r1, r0
+    ldw     r1, (r1)
+    lsri    r0, 2
+    jsr     r1
+
+    lrw     r7, pxCurrentTCB
+    ldw     r7, (r7)
+    ldw     sp, (r7)
+
+    ldw     r0, (sp, 64)
+    mtcr    r0, epc
+    ldw     r0, (sp, 60)
+    mtcr    r0, epsr
+    ldm     r0-r13, (sp)
+    ldw     r15, (sp, 56)
+    addi    sp, 68
+    rte
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h
new file mode 100644
index 0000000..6db37cc
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/CDK/T-HEAD_CK802/portmacro.h
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <csi_core.h>
+
+extern void vPortYield(void);
+#ifdef __cplusplus
+class vPortYield;
+extern "C" {
+#endif
+
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      double
+#define portLONG        long
+#define portSHORT       short
+#define portSTACK_TYPE  uint32_t
+#define portBASE_TYPE   long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+typedef void (*portvectorfunc)(void);
+
+#if( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t  TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+    typedef uint32_t  TickType_t;
+    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+
+
+/* Hardware specifics. */
+#define portBYTE_ALIGNMENT          8
+#define portSTACK_GROWTH            -1
+#define portMS_PERIOD_TICK          10
+#define portTICK_PERIOD_MS	        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+
+
+static inline void vPortEnableInterrupt( void )
+{
+    __enable_irq();
+}
+
+static inline void vPortDisableInterrupt( void )
+{
+    __disable_irq();
+}
+
+static inline portLONG GetCurrentPSR (void)
+{
+    return __get_PSR();
+}
+
+static inline portLONG SaveLocalPSR (void)
+{
+    portLONG flags = __get_PSR();
+    __disable_irq();
+    return flags;
+}
+
+static inline void RestoreLocalPSR (portLONG newMask)
+{
+    __asm__ __volatile__(
+    "mtcr   %0, psr \n"
+    :
+    :"r" (newMask)
+    :"memory"
+    );
+}
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+extern __attribute__((naked)) void cpu_yeild(void);
+
+#define portDISABLE_INTERRUPTS()                vPortDisableInterrupt()
+#define portENABLE_INTERRUPTS()                 vPortEnableInterrupt()
+#define portENTER_CRITICAL()                    vPortEnterCritical()
+#define portEXIT_CRITICAL()                     vPortExitCritical()
+#define portSET_INTERRUPT_MASK_FROM_ISR()       SaveLocalPSR()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(a)    RestoreLocalPSR(a)
+
+#define portNOP()                   asm("nop")
+
+extern portLONG ulCriticalNesting;
+extern portLONG pendsvflag;
+
+#define portYIELD()                 if (ulCriticalNesting == 0) \
+                                    {   \
+                                        vPortYield();   \
+                                    }   \
+                                    else \
+                                    {   \
+                                        pendsvflag = 1; \
+                                    }   \
+                                    portNOP();portNOP()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+#define portEND_SWITCHING_ISR( xSwitchRequired )    do {    \
+                                                            if( xSwitchRequired != pdFALSE )    \
+                                                            {   \
+                                                                portYIELD();    \
+                                                            }   \
+                                                    }while(0)
+
+#define portYIELD_FROM_ISR( a )     vTaskSwitchContext()
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c
new file mode 100644
index 0000000..9e6b565
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.c
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * \file
+ * \brief   exception processing for freertos
+ */
+
+/* #include "embARC.h" */
+
+#include "arc_freertos_exceptions.h"
+
+#ifdef __GNU__
+    extern void gnu_printf_setup( void );
+#endif
+
+/**
+ * \brief  freertos related cpu exception initialization, all the interrupts handled by freertos must be not
+ * fast irqs. If fiq is needed, please install the default firq_exc_entry or your own fast irq entry into
+ * the specific interrupt exception.
+ */
+void freertos_exc_init( void )
+{
+    #ifdef __GNU__
+        gnu_printf_setup();
+    #endif
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h
new file mode 100644
index 0000000..29a7038
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_freertos_exceptions.h
@@ -0,0 +1,45 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef ARC_FREERTOS_EXCEPTIONS_H
+#define ARC_FREERTOS_EXCEPTIONS_H
+
+/*
+ * here, all arc cpu exceptions share the same entry, also for all interrupt
+ * exceptions
+ */
+extern void exc_entry_cpu( void ); /* cpu exception entry for freertos */
+extern void exc_entry_int( void ); /* int exception entry for freertos */
+
+/* task dispatch functions in .s */
+extern void start_r( void );
+extern void start_dispatch();
+extern void dispatch();
+
+extern void freertos_exc_init( void );
+
+#endif /* ARC_FREERTOS_EXCEPTIONS_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s
new file mode 100644
index 0000000..ba1e911
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/arc_support.s
@@ -0,0 +1,521 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * \file
+ * \ingroup OS_FREERTOS
+ * \brief  freertos support for arc processor
+ *	like task dispatcher, interrupt handler
+ */
+/** @cond OS_FREERTOS_ASM_ARC_SUPPORT */
+
+/*
+ * core-dependent part in assemble language (for arc)
+ */
+#define __ASSEMBLY__
+#include "arc/arc.h"
+#include "arc/arc_asm_common.h"
+
+/*
+ *  task dispatcher
+ *
+ */
+	.text
+	.align 4
+	.global dispatch
+dispatch:
+/*
+ *  the pre-conditions of this routine are task context, CPU is
+ *  locked, dispatch is enabled.
+ */
+	SAVE_NONSCRATCH_REGS		/* save callee save registers */
+	mov	r1, dispatch_r
+	PUSH	r1			/* save return address */
+	ld	r0, [pxCurrentTCB]
+	bl	dispatcher
+
+/* return routine when task dispatch happened in task context */
+dispatch_r:
+	RESTORE_NONSCRATCH_REGS		/* recover registers */
+	j	[blink]
+
+/*
+ *  start dispatch
+ */
+	.global start_dispatch
+	.align 4
+start_dispatch:
+/*
+ *  this routine is called in the non-task context during the startup of the kernel
+ *  , and all the interrupts are locked.
+ *
+ *  when the dispatcher is called, the cpu is locked, no nest exception (CPU exception/interrupt).
+ *  In target_initialize, all interrupt priority mask should be cleared, cpu should be
+ *  locked, the interrupts outside the kernel such as fiq can be
+ *  enabled.
+ */
+	clri
+	mov	r0, 0
+	st	r0, [exc_nest_count]
+	b	dispatcher_0
+/*
+ *  dispatcher
+ */
+dispatcher:
+	ld	r1, [ulCriticalNesting]
+	PUSH	r1			/* save critical nesting */
+	st	sp, [r0]		/* save stack pointer of current task, r0->pxCurrentTCB */
+	jl	vTaskSwitchContext	/* change the value of pxCurrentTCB */
+/*
+ *  before dispatcher is called, task context | cpu locked | dispatch enabled
+ *  should be satisfied. In this routine, the processor will jump
+ *  into the entry of next to run task
+ *
+ *  i.e. kernel mode, IRQ disabled, dispatch enabled
+ */
+dispatcher_0:
+	ld	r1, [pxCurrentTCB]
+	ld	sp, [r1]	/* recover task stack */
+#if ARC_FEATURE_STACK_CHECK
+#if ARC_FEATURE_SEC_PRESENT
+	lr r0, [AUX_SEC_STAT]
+	bclr r0, r0, AUX_SEC_STAT_BIT_SSC
+	sflag r0
+#else
+	lr r0, [AUX_STATUS32]
+	bclr r0, r0, AUX_STATUS_BIT_SC
+	kflag r0
+#endif
+	jl	vPortSetStackCheck
+#if ARC_FEATURE_SEC_PRESENT
+	lr r0, [AUX_SEC_STAT]
+	bset r0, r0, AUX_SEC_STAT_BIT_SSC
+	sflag r0
+#else
+	lr r0, [AUX_STATUS32]
+	bset r0, r0, AUX_STATUS_BIT_SC
+	kflag r0
+#endif
+#endif
+	POP	r0		/* get critical nesting */
+	st	r0, [ulCriticalNesting]
+	POP	r0		/* get return address  */
+	j	[r0]
+
+/*
+ *  task startup routine
+ *
+ */
+	.text
+	.global start_r
+	.align 4
+start_r:
+	seti	/* unlock cpu */
+	mov	blink, vPortEndTask	/* set return address */
+	POP	r1			/* get task function body */
+	POP	r0			/* get task parameters */
+	j	[r1]
+
+/****** exceptions and interrupts handing ******/
+/****** entry for exception handling ******/
+	.global exc_entry_cpu
+	.align 4
+exc_entry_cpu:
+
+	EXCEPTION_PROLOGUE
+
+	mov	blink,	sp
+	mov	r3, sp		/* as exception handler's para(p_excinfo) */
+
+	ld	r0, [exc_nest_count]
+	add	r1, r0, 1
+	st	r1, [exc_nest_count]
+	brne	r0, 0, exc_handler_1
+/* change to exception stack if interrupt happened in task context */
+	mov	sp, _e_stack
+exc_handler_1:
+	PUSH	blink
+
+	lr	r0, [AUX_ECR]
+	lsr	r0, r0, 16
+	mov	r1, exc_int_handler_table
+	ld.as	r2, [r1, r0]
+
+	mov	r0, r3
+	jl	[r2]		/* !!!!jump to exception handler where interrupts are not allowed! */
+
+/* interrupts are not allowed */
+ret_exc:
+	POP	sp
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	st 	r0, [r1]
+	brne	r0, 0, ret_exc_1 /* nest exception case */
+	lr	r1, [AUX_IRQ_ACT] /* nest interrupt case */
+	brne	r1, 0, ret_exc_1
+
+	ld	r0, [context_switch_reqflg]
+	brne	r0, 0, ret_exc_2
+ret_exc_1:	/* return from non-task context, interrupts or exceptions are nested */
+
+	EXCEPTION_EPILOGUE
+	rtie
+
+/* there is a dispatch request */
+ret_exc_2:
+	/* clear dispatch request */
+	mov	r0, 0
+	st	r0, [context_switch_reqflg]
+
+	ld	r0, [pxCurrentTCB]
+	breq	r0, 0, ret_exc_1
+
+	SAVE_CALLEE_REGS	/* save callee save registers */
+
+	lr	r0, [AUX_STATUS32]
+	bclr	r0, r0, AUX_STATUS_BIT_AE	/* clear exception bit */
+	kflag	r0
+
+	mov	r1, ret_exc_r	/* save return address */
+	PUSH	r1
+
+	bl	dispatcher	/* r0->pxCurrentTCB */
+
+ret_exc_r:
+	/* recover exception status */
+	lr	r0, [AUX_STATUS32]
+	bset	r0, r0, AUX_STATUS_BIT_AE
+	kflag	r0
+
+	RESTORE_CALLEE_REGS	/* recover registers */
+	EXCEPTION_EPILOGUE
+	rtie
+
+/****** entry for normal interrupt exception handling ******/
+	.global exc_entry_int	/* entry for interrupt handling */
+	.align 4
+exc_entry_int:
+#if ARC_FEATURE_FIRQ == 1
+#if ARC_FEATURE_RGF_NUM_BANKS > 1
+	lr	r0, [AUX_IRQ_ACT]			/*  check whether it is P0 interrupt */
+	btst	r0, 0
+	jnz	exc_entry_firq
+#else
+	PUSH	r10
+	lr	r10, [AUX_IRQ_ACT]
+	btst	r10, 0
+	POP	r10
+	jnz	exc_entry_firq
+#endif
+#endif
+	INTERRUPT_PROLOGUE
+
+	mov	blink, sp
+
+	clri	/* disable interrupt */
+	ld	r3, [exc_nest_count]
+	add	r2, r3, 1
+	st	r2, [exc_nest_count]
+	seti	/* enable higher priority interrupt */
+
+	brne	r3, 0, irq_handler_1
+/* change to exception stack if interrupt happened in task context */
+	mov	sp, _e_stack
+#if ARC_FEATURE_STACK_CHECK
+#if ARC_FEATURE_SEC_PRESENT
+	lr r0, [AUX_SEC_STAT]
+	bclr r0, r0, AUX_SEC_STAT_BIT_SSC
+	sflag r0
+#else
+	lr r0, [AUX_STATUS32]
+	bclr r0, r0, AUX_STATUS_BIT_SC
+	kflag r0
+#endif
+#endif
+irq_handler_1:
+	PUSH	blink
+
+	lr	r0, [AUX_IRQ_CAUSE]
+	mov	r1, exc_int_handler_table
+	ld.as	r2, [r1, r0]	/* r2 = exc_int_handler_table + irqno *4 */
+/* handle software triggered interrupt */
+	lr	r3, [AUX_IRQ_HINT]
+	cmp	r3, r0
+	bne.d irq_hint_handled
+	xor	r3, r3, r3
+	sr	r3, [AUX_IRQ_HINT]
+irq_hint_handled:
+
+	jl	[r2]		/* jump to interrupt handler */
+/* no interrupts are allowed from here */
+ret_int:
+	clri	/* disable interrupt */
+
+	POP	sp
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	st	r0, [r1]
+/* if there are multi-bits set in IRQ_ACT, it's still in nest interrupt */
+	lr	r0, [AUX_IRQ_CAUSE]
+	sr	r0, [AUX_IRQ_SELECT]
+	lr 	r3, [AUX_IRQ_PRIORITY]
+	lr	r1, [AUX_IRQ_ACT]
+	bclr	r2, r1, r3
+	brne	r2, 0, ret_int_1
+
+	ld	r0, [context_switch_reqflg]
+	brne	r0, 0, ret_int_2
+ret_int_1:	/* return from non-task context */
+	INTERRUPT_EPILOGUE
+	rtie
+/* there is a dispatch request */
+ret_int_2:
+	/* clear dispatch request */
+	mov	r0, 0
+	st	r0, [context_switch_reqflg]
+
+	ld	r0, [pxCurrentTCB]
+	breq 	r0, 0, ret_int_1
+
+/* r1 has old AUX_IRQ_ACT */
+	PUSH	r1
+/* clear related bits in IRQ_ACT manually to simulate a irq return  */
+	sr	r2, [AUX_IRQ_ACT]
+
+	SAVE_CALLEE_REGS	/* save callee save registers */
+	mov	r1, ret_int_r	/* save return address */
+	PUSH	r1
+
+	bl	dispatcher	/* r0->pxCurrentTCB */
+
+ret_int_r:
+	RESTORE_CALLEE_REGS	/* recover registers */
+	POPAX	AUX_IRQ_ACT
+	INTERRUPT_EPILOGUE
+	rtie
+
+#if ARC_FEATURE_FIRQ == 1
+	.global exc_entry_firq
+	.align 4
+exc_entry_firq:
+#if ARC_FEATURE_STACK_CHECK && ARC_FEATURE_RGF_NUM_BANKS > 1
+#if ARC_FEATURE_SEC_PRESENT
+	lr r0, [AUX_SEC_STAT]
+	bclr r0, r0, AUX_SEC_STAT_BIT_SSC
+	sflag r0
+#else
+	lr r0, [AUX_STATUS32]
+	bclr r0, r0, AUX_STATUS_BIT_SC
+	kflag r0
+#endif
+#endif
+	SAVE_FIQ_EXC_REGS
+
+	mov	blink, sp
+
+	ld	r3, [exc_nest_count]
+	add	r2, r3, 1
+	st	r2, [exc_nest_count]
+
+	brne	r3, 0, firq_handler_1
+#if ARC_FEATURE_STACK_CHECK && ARC_FEATURE_RGF_NUM_BANKS == 1
+#if ARC_FEATURE_SEC_PRESENT
+	lr r0, [AUX_SEC_STAT]
+	bclr r0, r0, AUX_SEC_STAT_BIT_SSC
+	sflag r0
+#else
+	lr r0, [AUX_STATUS32]
+	bclr r0, r0, AUX_STATUS_BIT_SC
+	kflag r0
+#endif
+#endif
+/* change to exception stack if interrupt happened in task context */
+	mov	sp, _e_stack
+firq_handler_1:
+	PUSH	blink
+
+	lr	r0, [AUX_IRQ_CAUSE]
+	mov	r1, exc_int_handler_table
+	ld.as	r2, [r1, r0]	/* r2 = exc_int_handler_table + irqno *4 */
+/* handle software triggered interrupt */
+	lr	r3, [AUX_IRQ_HINT]
+	brne	r3, r0, firq_hint_handled
+	xor	r3, r3, r3
+	sr	r3, [AUX_IRQ_HINT]
+firq_hint_handled:
+
+	jl	[r2]		/* jump to interrupt handler */
+/* no interrupts are allowed from here */
+ret_firq:
+	clri
+	POP	sp
+
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	st	r0, [r1]
+/* if there are multi-bits set in IRQ_ACT, it's still in nest interrupt */
+	lr	r1, [AUX_IRQ_ACT]
+	bclr	r1, r1, 0
+	brne	r1, 0, ret_firq_1
+
+	ld	r0, [context_switch_reqflg]
+	brne	r0, 0, ret_firq_2
+ret_firq_1:	/* return from non-task context */
+	RESTORE_FIQ_EXC_REGS
+	rtie
+/* there is a dispatch request */
+ret_firq_2:
+	/* clear dispatch request */
+	mov	r0, 0
+	st	r0, [context_switch_reqflg]
+
+	ld	r0, [pxCurrentTCB]
+	breq 	r0, 0, ret_firq_1
+
+/* reconstruct the interruptted context
+ * When ARC_FEATURE_RGF_BANKED_REGS >= 16 (16, 32), sp is banked
+ * so need to restore the fast irq stack.
+ */
+#if ARC_FEATURE_RGF_BANKED_REGS >= 16
+	RESTORE_LP_REGS
+#if ARC_FEATURE_CODE_DENSITY
+	RESTORE_CODE_DENSITY
+#endif
+	RESTORE_R58_R59
+#endif
+
+/* when BANKED_REGS == 16, r4-r9 wiil be also saved in fast irq stack
+ * so pop them out
+ */
+#if  ARC_FEATURE_RGF_BANKED_REGS == 16 && !defined(ARC_FEATURE_RF16)
+	POP		r9
+	POP		r8
+	POP		r7
+	POP		r6
+	POP		r5
+	POP		r4
+#endif
+
+/* for other cases, unbanked regs are already in interrupted context's stack,
+ * so just need to save and pop the banked regs
+ */
+
+/* save the interruptted context */
+#if ARC_FEATURE_RGF_BANKED_REGS > 0
+/* switch back to bank0  */
+	lr r0, [AUX_STATUS32]
+	bic     r0, r0, 0x70000
+	kflag   r0
+#endif
+
+#if ARC_FEATURE_RGF_BANKED_REGS == 4
+/* r4 - r12, gp, fp, r30, blink already saved */
+	PUSH	r0
+	PUSH	r1
+	PUSH	r2
+	PUSH	r3
+#elif ARC_FEATURE_RGF_BANKED_REGS == 8
+/* r4 - r9, r0, r11 gp, fp, r30, blink already saved */
+	PUSH	r0
+	PUSH	r1
+	PUSH	r2
+	PUSH	r3
+	PUSH	r12
+#elif ARC_FEATURE_RGF_BANKED_REGS >= 16
+/* nothing is saved, */
+	SAVE_R0_TO_R12
+
+	SAVE_R58_R59
+	PUSH	gp
+	PUSH	fp
+	PUSH	r30		/* general purpose */
+	PUSH	blink
+
+#if ARC_FEATURE_CODE_DENSITY
+	SAVE_CODE_DENSITY
+#endif
+	SAVE_LP_REGS
+#endif
+	PUSH	ilink
+	lr	r0, [AUX_STATUS32_P0]
+	PUSH	r0
+	lr	r0, [AUX_IRQ_ACT]
+	PUSH	r0
+	bclr	r0, r0, 0
+	sr	r0, [AUX_IRQ_ACT]
+
+	SAVE_CALLEE_REGS	/* save callee save registers */
+
+	mov	r1, ret_firq_r	/* save return address */
+	PUSH	r1
+	ld	r0, [pxCurrentTCB]
+	bl	dispatcher	/* r0->pxCurrentTCB */
+
+ret_firq_r:
+	RESTORE_CALLEE_REGS	/* recover registers */
+	POPAX	AUX_IRQ_ACT
+	POPAX	AUX_STATUS32_P0
+	POP	ilink
+
+#if ARC_FEATURE_RGF_NUM_BANKS > 1
+#if ARC_FEATURE_RGF_BANKED_REGS == 4
+/* r4 - r12, gp, fp, r30, blink already saved */
+	POP	r3
+	POP	r2
+	POP	r1
+	POP	r0
+	RESTORE_FIQ_EXC_REGS
+#elif ARC_FEATURE_RGF_BANKED_REGS == 8
+/* r4 - r9, gp, fp, r30, blink already saved */
+	POP	r12
+	POP	r3
+	POP	r2
+	POP	r1
+	POP	r0
+	RESTORE_FIQ_EXC_REGS
+#elif ARC_FEATURE_RGF_BANKED_REGS >= 16
+	RESTORE_LP_REGS
+#if ARC_FEATURE_CODE_DENSITY
+	RESTORE_CODE_DENSITY
+#endif
+	POP	blink
+	POP	r30
+	POP	fp
+	POP	gp
+
+	RESTORE_R58_R59
+	RESTORE_R0_TO_R12
+#endif /* ARC_FEATURE_RGF_BANKED_REGS  */
+#else
+	RESTORE_FIQ_EXC_REGS
+#endif /* ARC_FEATURE_RGF_NUM_BANKS */
+	rtie
+#endif
+/** @endcond */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c
new file mode 100644
index 0000000..1762d4a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/freertos_tls.c
@@ -0,0 +1,238 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#if defined( __MW__ )
+
+    #include <stdint.h>
+    #include <stdlib.h>
+    #include <string.h>
+
+    #include "FreeRTOS.h"
+
+    #include "queue.h"
+    #include "semphr.h"
+    #include "task.h"
+
+    #include "arc/arc_exception.h"
+    #include "embARC_toolchain.h"
+    #include "embARC_debug.h"
+
+    #ifdef ENABLE_FREERTOS_TLS_DEBUG
+        #define TLS_DEBUG( fmt, ... )    EMBARC_PRINTF( fmt, ## __VA_ARGS__ )
+    #else
+        #define TLS_DEBUG( fmt, ... )
+    #endif
+
+/*
+ * Runtime routines to execute constructors and
+ * destructors for task local storage.
+ */
+    extern void __mw_run_tls_dtor();
+    extern void __mw_run_tls_ctor();
+
+    extern uint32_t exc_nest_count;
+
+/*
+ * Linker generated symbols to mark .tls section addresses
+ * first byte .. last byte
+ */
+    extern char _ftls[], _etls[];
+    #pragma weak _ftls
+    #pragma weak _etls
+
+    void executable_requires_tls_section( void )
+    {
+        #if _ARC
+            for( ; ; )
+            {
+                _flag( 1 );
+                _nop();
+                _nop();
+                _nop();
+                _nop();
+                _nop();
+            }
+        #endif
+    }
+    #pragma off_inline(executable_requires_tls_section);
+    #pragma alias(executable_requires_tls_section, "executable_requires_.tls_section");
+
+    static void * init_task_tls( void )
+    {
+        uint32_t len = ( uint32_t ) ( _etls - _ftls );
+        void * tls = NULL;
+
+        #if FREERTOS_HEAP_SEL == 3
+        #warning "FreeRTOS TLS support is not compatible with heap 3 solution(FREERTOS_HEAP_SEL=3)!"
+        #warning "You can change FREERTOS_HEAP_SEL in freertos.mk to select other heap solution."
+        #else
+            tls = pvPortMalloc( len );
+        #endif
+
+        if( tls )
+        {
+            TLS_DEBUG( "Malloc task tls:%dbytes\r\n", len );
+            memcpy( tls, _ftls, len );
+            __mw_run_tls_ctor(); /* Run constructors */
+        }
+
+        return tls;
+    }
+
+    static void free_task_tls( void * pxTCB )
+    {
+        TaskHandle_t task2free = ( TaskHandle_t ) pxTCB;
+
+        if( task2free != NULL )
+        {
+            void * tls = pvTaskGetThreadLocalStoragePointer( task2free, 0 );
+
+            if( tls )
+            {
+                TLS_DEBUG( "Free task tls\r\n" );
+                __mw_run_tls_dtor();
+                vPortFree( tls );
+                vTaskSetThreadLocalStoragePointer( task2free, 0, NULL );
+            }
+        }
+    }
+
+    void task_end_hook( void * pxTCB )
+    {
+        free_task_tls( pxTCB );
+    }
+
+    static void * get_isr_tls( void )
+    {
+        /* In an ISR */
+        static int first = 1;
+
+        if( _Rarely( first ) )
+        {
+            first = 0;
+            __mw_run_tls_ctor(); /* Run constructors */
+        }
+
+        return ( void * ) _ftls;
+    }
+    #pragma off_inline(get_isr_tls)
+
+    static void * get_task_tls( void )
+    {
+        TaskHandle_t cur_task;
+
+        cur_task = xTaskGetCurrentTaskHandle();
+
+        if( cur_task == NULL )
+        {
+            return get_isr_tls();
+        }
+
+        void * tls = pvTaskGetThreadLocalStoragePointer( cur_task, 0 );
+
+        if( tls == NULL )
+        {
+            tls = init_task_tls();
+
+            if( tls )
+            {
+                vTaskSetThreadLocalStoragePointer( cur_task, 0, tls );
+            }
+            else
+            {
+                tls = get_isr_tls();
+            }
+        }
+
+        return tls;
+    }
+    #pragma off_inline(get_task_tls)
+
+    #if _ARC /* for ARC XCALLs need to preserve flags */
+        extern void * _Preserve_flags _mwget_tls( void );
+    #endif
+
+/*
+ * Back end gens calls to find local data for this task
+ */
+    void * _mwget_tls( void )
+    {
+        if( _ftls == ( char * ) 0 )
+        {
+            executable_requires_tls_section();
+        }
+
+        if( exc_nest_count > 0 ) /* In ISR */
+        {
+            return get_isr_tls();
+        }
+        else /* In Task */
+        {
+            return get_task_tls();
+        }
+    }
+
+
+/* simple interface of thread safe */
+    typedef xSemaphoreHandle _lock_t;
+    #if configUSE_RECURSIVE_MUTEXES != 1
+        #error "configUSE_RECURSIVE_MUTEXES in FreeRTOSConfig.h need to 1"
+    #endif
+
+    void _mwmutex_create( _lock_t * mutex_ptr )
+    {
+        *mutex_ptr = xSemaphoreCreateRecursiveMutex();
+    }
+
+    void _mwmutex_delete( _lock_t * mutex_ptr )
+    {
+        if( ( *mutex_ptr ) != NULL )
+        {
+            vSemaphoreDelete( *mutex_ptr );
+        }
+    }
+
+    void _mwmutex_lock( _lock_t mutex )
+    {
+        if( ( mutex ) != NULL )
+        {
+            while( xSemaphoreTakeRecursive( mutex, portMAX_DELAY ) != pdTRUE )
+            {
+            }
+        }
+    }
+
+    void _mwmutex_unlock( _lock_t mutex )
+    {
+        if( ( mutex ) != NULL )
+        {
+            xSemaphoreGiveRecursive( mutex );
+        }
+    }
+
+#else /* if defined( __MW__ ) */
+
+#endif /* __MW__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/port.c
new file mode 100644
index 0000000..86f63f1
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/port.c
@@ -0,0 +1,299 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*
+ * Implementation of functions defined in portable.h
+ */
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "FreeRTOSConfig.h"
+
+#include "arc/arc_exception.h"
+#include "arc/arc_timer.h"
+#include "board.h"
+
+#include "arc_freertos_exceptions.h"
+
+volatile unsigned int ulCriticalNesting = 999UL;
+volatile unsigned int context_switch_reqflg; /* task context switch request flag in exceptions and interrupts handling */
+
+/**
+ * \var exc_nest_count
+ * \brief the counter for exc/int processing, =0 no int/exc
+ * >1 in int/exc processing
+ * @}
+ */
+uint32_t exc_nest_count;
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief kernel tick interrupt handler of freertos
+ */
+/* ----------------------------------------------------------------------------*/
+static void vKernelTick( void * ptr )
+{
+    /* clear timer interrupt */
+    arc_timer_int_clear( BOARD_OS_TIMER_ID );
+    board_timer_update( configTICK_RATE_HZ );
+
+    if( xTaskIncrementTick() )
+    {
+        portYIELD_FROM_ISR(); /* need to make task switch */
+    }
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief  setup freertos kernel tick
+ */
+/* ----------------------------------------------------------------------------*/
+static void prvSetupTimerInterrupt( void )
+{
+    unsigned int cyc = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+    int_disable( BOARD_OS_TIMER_INTNO ); /* disable os timer interrupt */
+    arc_timer_stop( BOARD_OS_TIMER_ID );
+    arc_timer_start( BOARD_OS_TIMER_ID, TIMER_CTRL_IE | TIMER_CTRL_NH, cyc );
+
+    int_handler_install( BOARD_OS_TIMER_INTNO, ( INT_HANDLER_T ) vKernelTick );
+    int_pri_set( BOARD_OS_TIMER_INTNO, INT_PRI_MIN );
+    int_enable( BOARD_OS_TIMER_INTNO );
+}
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ * For ARC, task context switch is implemented with the help of SWI exception
+ * It's not efficient but simple.
+ *
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* To ensure asserts in tasks.c don't fail, although in this case the assert
+     * is not really required. */
+    pxTopOfStack--;
+
+    /* Setup the initial stack of the task.  The stack is set exactly as
+     * expected by the portRESTORE_CONTEXT() macro. */
+
+    /* When the task starts is will expect to find the function parameter in
+     * R0. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) pxCode; /* function body */
+
+    /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) start_r; /* dispatch return address */
+
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING;
+    return pxTopOfStack;
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief  start the freertos scheduler, go to the first task
+ *
+ * @returns
+ */
+/* ----------------------------------------------------------------------------*/
+BaseType_t xPortStartScheduler( void )
+{
+    /* Start the timer that generates the tick ISR. */
+    prvSetupTimerInterrupt();
+    start_dispatch();
+
+    /* Should not get here! */
+    return 0;
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief
+ */
+/* ----------------------------------------------------------------------------*/
+void vPortEndScheduler( void )
+{
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief  generate a task switch request in ISR
+ */
+/* ----------------------------------------------------------------------------*/
+void vPortYieldFromIsr( void )
+{
+    unsigned int status32;
+
+    status32 = cpu_lock_save();
+    context_switch_reqflg = true;
+    cpu_unlock_restore( status32 );
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief
+ */
+/* ----------------------------------------------------------------------------*/
+void vPortYield( void )
+{
+    unsigned int status32;
+
+    status32 = cpu_lock_save();
+    dispatch();
+    cpu_unlock_restore( status32 );
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief
+ */
+/* ----------------------------------------------------------------------------*/
+void vPortEndTask( void )
+{
+    #if ( INCLUDE_vTaskDelete == 1 )
+        vTaskDelete( NULL ); /* Delete task itself */
+    #endif
+
+    while( 1 ) /* Yield to other task */
+    {
+        vPortYield();
+    }
+}
+
+#if ARC_FEATURE_STACK_CHECK
+
+/*
+ * !!! Note !!!
+ * This a trick!!!
+ * It's a copy from task.c. We need to konw the definition of TCB for the purpose of hardware
+ * stack check. Pls don't forget to update it when FreeRTOS is updated.
+ */
+    typedef struct tskTaskControlBlock       /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+    {
+        volatile StackType_t * pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+        #if ( portUSING_MPU_WRAPPERS == 1 )
+            xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+        #endif
+
+        ListItem_t xStateListItem;                  /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+        ListItem_t xEventListItem;                  /*< Used to reference a task from an event list. */
+        UBaseType_t uxPriority;                     /*< The priority of the task.  0 is the lowest priority. */
+        StackType_t * pxStack;                      /*< Points to the start of the stack. */
+        char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+        #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+            StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */
+        #endif
+
+        #if ( portCRITICAL_NESTING_IN_TCB == 1 )
+            UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+        #endif
+
+        #if ( configUSE_TRACE_FACILITY == 1 )
+            UBaseType_t uxTCBNumber;  /*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+            UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */
+        #endif
+
+        #if ( configUSE_MUTEXES == 1 )
+            UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+            UBaseType_t uxMutexesHeld;
+        #endif
+
+        #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+            TaskHookFunction_t pxTaskTag;
+        #endif
+
+        #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+            void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+        #endif
+
+        #if ( configGENERATE_RUN_TIME_STATS == 1 )
+            uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */
+        #endif
+
+        #if ( configUSE_NEWLIB_REENTRANT == 1 )
+
+            /* Allocate a Newlib reent structure that is specific to this task.
+             * Note Newlib support has been included by popular demand, but is not
+             * used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+             * responsible for resulting newlib operation.  User must be familiar with
+             * newlib and must provide system-wide implementations of the necessary
+             * stubs. Be warned that (at the time of writing) the current newlib design
+             * implements a system-wide malloc() that must be provided with locks. */
+            struct  _reent xNewLib_reent;
+        #endif
+
+        #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+            volatile uint32_t ulNotifiedValue;
+            volatile uint8_t ucNotifyState;
+        #endif
+
+        /* See the comments above the definition of
+         * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+        #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+            uint8_t ucStaticallyAllocated;                     /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+        #endif
+
+        #if ( INCLUDE_xTaskAbortDelay == 1 )
+            uint8_t ucDelayAborted;
+        #endif
+
+        #if ( configUSE_POSIX_ERRNO == 1 )
+            int iTaskErrno;
+        #endif
+    } tskTCB;
+
+
+    void vPortSetStackCheck( TaskHandle_t old,
+                             TaskHandle_t new )
+    {
+        if( new != NULL )
+        {
+            #if ARC_FEATURE_SEC_PRESENT
+                arc_aux_write( AUX_S_KSTACK_BASE, ( uint32_t ) ( new->pxEndOfStack ) );
+                arc_aux_write( AUX_S_KSTACK_TOP, ( uint32_t ) ( new->pxStack ) );
+            #else
+                arc_aux_write( AUX_KSTACK_BASE, ( uint32_t ) ( new->pxEndOfStack ) );
+                arc_aux_write( AUX_KSTACK_TOP, ( uint32_t ) ( new->pxStack ) );
+            #endif
+        }
+    }
+#endif /* if ARC_FEATURE_STACK_CHECK */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h
new file mode 100644
index 0000000..728b21b
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_EM_HS/portmacro.h
@@ -0,0 +1,158 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+/* record stack high address for stack check */
+#ifndef configRECORD_STACK_HIGH_ADDRESS
+    #define configRECORD_STACK_HIGH_ADDRESS    1
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR          char
+#define portFLOAT         float
+#define portDOUBLE        double
+#define portLONG          long
+#define portSHORT         short
+#define portSTACK_TYPE    unsigned int
+#define portBASE_TYPE     portLONG
+
+#ifndef Asm
+    #define Asm           __asm__ volatile
+#endif
+
+/*
+ *  normal constants
+ */
+#ifndef NULL
+    #define NULL    0           /* invalid pointer */
+#endif /* NULL */
+
+#ifndef true
+    #define true    1           /* true */
+#endif /* true */
+
+#ifndef false
+    #define false    0          /* false */
+#endif /* false */
+
+typedef portSTACK_TYPE     StackType_t;
+typedef long               BaseType_t;
+typedef unsigned long      UBaseType_t;
+
+#if ( configUSE_16_BIT_TICKS == 1 )
+    typedef uint16_t       TickType_t;
+    #define portMAX_DELAY          ( TickType_t ) 0xffff
+#else
+    typedef unsigned int   TickType_t;
+    #define portMAX_DELAY          ( TickType_t ) 0xffffffffUL
+#endif
+
+#define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
+#define portSTACK_GROWTH           ( -1 )
+#define portTICK_PERIOD_MS         ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT         8
+#define portNOP()               Asm( "nop_s" );
+#define IPM_ENABLE_ALL             1
+
+#define portYIELD_FROM_ISR()    vPortYieldFromIsr()
+#define portYIELD()             vPortYield()
+
+/* Critical section management. */
+#define portDISABLE_INTERRUPTS() \
+    {                            \
+        Asm( "clri" );           \
+        Asm( "" ::: "memory" );  \
+    }                            \
+
+#define portENABLE_INTERRUPTS() \
+    {                           \
+        Asm( "" ::: "memory" ); \
+        Asm( "seti" );          \
+    }                           \
+
+extern volatile unsigned int ulCriticalNesting;
+
+#define portENTER_CRITICAL()     \
+    {                            \
+        portDISABLE_INTERRUPTS() \
+        ulCriticalNesting++;     \
+    }
+
+
+#define portEXIT_CRITICAL()                                    \
+    {                                                          \
+        if( ulCriticalNesting > portNO_CRITICAL_NESTING )      \
+        {                                                      \
+            ulCriticalNesting--;                               \
+            if( ulCriticalNesting == portNO_CRITICAL_NESTING ) \
+            {                                                  \
+                portENABLE_INTERRUPTS()                        \
+            }                                                  \
+        }                                                      \
+    }
+
+
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()              do {} while( 0 )     /* we use the timer */
+#define portALT_GET_RUN_TIME_COUNTER_VALUE( dest )            ( dest = xTickCount )
+
+#if defined( __MW__ )
+    extern void task_end_hook( void * pxTCB );
+    #define portCLEAN_UP_TCB( pxTCB )    task_end_hook( ( void * ) pxTCB )
+#else
+    #define portCLEAN_UP_TCB( pxTCB )    ( void ) pxTCB
+#endif
+
+void vPortYield( void );
+void vPortYieldFromIsr( void );
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c
new file mode 100644
index 0000000..9e6b565
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.c
@@ -0,0 +1,51 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * \file
+ * \brief   exception processing for freertos
+ */
+
+/* #include "embARC.h" */
+
+#include "arc_freertos_exceptions.h"
+
+#ifdef __GNU__
+    extern void gnu_printf_setup( void );
+#endif
+
+/**
+ * \brief  freertos related cpu exception initialization, all the interrupts handled by freertos must be not
+ * fast irqs. If fiq is needed, please install the default firq_exc_entry or your own fast irq entry into
+ * the specific interrupt exception.
+ */
+void freertos_exc_init( void )
+{
+    #ifdef __GNU__
+        gnu_printf_setup();
+    #endif
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h
new file mode 100644
index 0000000..29a7038
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/arc_freertos_exceptions.h
@@ -0,0 +1,45 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef ARC_FREERTOS_EXCEPTIONS_H
+#define ARC_FREERTOS_EXCEPTIONS_H
+
+/*
+ * here, all arc cpu exceptions share the same entry, also for all interrupt
+ * exceptions
+ */
+extern void exc_entry_cpu( void ); /* cpu exception entry for freertos */
+extern void exc_entry_int( void ); /* int exception entry for freertos */
+
+/* task dispatch functions in .s */
+extern void start_r( void );
+extern void start_dispatch();
+extern void dispatch();
+
+extern void freertos_exc_init( void );
+
+#endif /* ARC_FREERTOS_EXCEPTIONS_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/arc_support.s b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/arc_support.s
new file mode 100644
index 0000000..06d6125
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/arc_support.s
@@ -0,0 +1,321 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/**
+ * \file
+ * \ingroup OS_FREERTOS
+ * \brief  freertos support for arc processor
+ *	like task dispatcher, interrupt handler
+ */
+/** @cond OS_FREERTOS_ASM_ARC_SUPPORT */
+
+/*
+ * core-dependent part in assemble language (for arc)
+ */
+#define __ASSEMBLY__
+#include "arc/arc.h"
+#include "arc/arc_asm_common.h"
+
+/*
+ *  task dispatcher
+ *
+ */
+	.text
+	.align 4
+	.global dispatch
+dispatch:
+/*
+ *  the pre-conditions of this routine are task context, CPU is
+ *  locked, dispatch is enabled.
+ */
+	SAVE_NONSCRATCH_REGS		/* save callee save registers */
+	mov	r1, dispatch_r
+	PUSH	r1			/* save return address */
+	ld	r0, [pxCurrentTCB]
+	bl	dispatcher
+
+/* return routine when task dispatch happened in task context */
+dispatch_r:
+	RESTORE_NONSCRATCH_REGS		/* recover registers */
+	j	[blink]
+
+/*
+ *  start dispatch
+ */
+	.global start_dispatch
+	.align 4
+start_dispatch:
+/*
+ *  this routine is called in the non-task context during the startup of the kernel
+ *  , and all the interrupts are locked.
+ *
+ *  when the dispatcher is called, the cpu is locked, no nest exception (CPU exception/interrupt).
+ *  In target_initialize, all interrupt priority mask should be cleared, cpu should be
+ *  locked, the interrupts outside the kernel such as fiq can be
+ *  enabled.
+ */
+	clri
+	mov	r0, 0
+	st	r0, [exc_nest_count]
+	b	dispatcher_0
+/*
+ *  dispatcher
+ */
+dispatcher:
+	ld	r1, [ulCriticalNesting]
+	PUSH	r1			/* save critical nesting */
+	st	sp, [r0]		/* save stack pointer of current task, r0->pxCurrentTCB */
+	jl	vTaskSwitchContext	/* change the value of pxCurrentTCB */
+/*
+ *  before dispatcher is called, task context | cpu locked | dispatch enabled
+ *  should be satisfied. In this routine, the processor will jump
+ *  into the entry of next to run task
+ *
+ *  i.e. kernel mode, IRQ disabled, dispatch enabled
+ */
+dispatcher_0:
+	ld	r1, [pxCurrentTCB]
+	ld	sp, [r1]	/* recover task stack */
+#if ARC_FEATURE_STACK_CHECK
+	lr r0, [AUX_STATUS32]
+	bclr r0, r0, AUX_STATUS_BIT_SC
+	flag r0
+	jl	vPortSetStackCheck
+	lr r0, [AUX_STATUS32]
+	bset r0, r0, AUX_STATUS_BIT_SC
+	flag r0
+#endif
+	POP	r0		/* get critical nesting */
+	st	r0, [ulCriticalNesting]
+	POP	r0		/* get return address  */
+	j	[r0]
+
+/*
+ *  task startup routine
+ *
+ */
+	.text
+	.global start_r
+	.align 4
+start_r:
+	seti	/* unlock cpu */
+	mov	blink, vPortEndTask	/* set return address */
+	POP	r1			/* get task function body */
+	POP	r0			/* get task parameters */
+	j	[r1]
+
+/****** exceptions and interrupts handing ******/
+/****** entry for exception handling ******/
+	.global exc_entry_cpu
+	.align 4
+exc_entry_cpu:
+
+	EXCEPTION_PROLOGUE
+
+
+	mov	blink,	sp
+	mov	r3, sp		/* as exception handler's para(p_excinfo) */
+
+	ld	r1, [exc_nest_count]
+	add	r1, r1, 1
+	st	r1, [exc_nest_count]
+	brne	r1, 0, exc_handler_1
+/* change to exception stack if interrupt happened in task context */
+	mov	sp, _e_stack
+exc_handler_1:
+	PUSH	blink
+
+/* find the exception cause */
+#if ARC_FEATURE_CORE_700
+	lr	r0, [AUX_ECR]
+	lsr	r0, r0, 16
+	bmsk	r0, r0, 7
+#endif
+	mov	r1, exc_int_handler_table
+	ld.as	r2, [r1, r0]
+
+	mov	r0, r3
+	jl	[r2]		/* !!!!jump to exception handler where interrupts are not allowed! */
+
+/* interrupts are not allowed */
+ret_exc:
+	POP	sp
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	st 	r0, [r1]
+	brne	r0, 0, ret_exc_1  /* nested exception case */
+	lr	r1, [AUX_IRQ_LV12]
+	brne	r1, 0, ret_exc_1  /* nested or pending interrupt case */
+
+	ld	r0, [context_switch_reqflg]
+	brne	r0, 0, ret_exc_2
+ret_exc_1:	/* return from non-task context, interrupts or exceptions are nested */
+
+	EXCEPTION_EPILOGUE
+#if ARC_FEATURE_CORE_600
+	rtie ilink2
+#else
+	rtie
+#endif
+
+/* there is a dispatch request */
+ret_exc_2:
+	/* clear dispatch request */
+	mov	r0, 0
+	st	r0, [context_switch_reqflg]
+
+	ld	r0, [pxCurrentTCB]
+	breq	r0, 0, ret_exc_1
+
+	SAVE_CALLEE_REGS	/* save callee save registers */
+
+	lr	r0, [AUX_STATUS32]
+	bclr	r0, r0, AUX_STATUS_BIT_AE	/* clear exception bit */
+	flag	r0
+
+	mov	r1, ret_exc_r	/* save return address */
+	PUSH	r1
+
+	bl	dispatcher	/* r0->pxCurrentTCB */
+
+ret_exc_r:
+	/* recover exception status */
+	lr	r0, [AUX_STATUS32]
+	bset	r0, r0, AUX_STATUS_BIT_AE
+	flag	r0
+
+	RESTORE_CALLEE_REGS	/* recover registers */
+	EXCEPTION_EPILOGUE
+#if ARC_FEATURE_CORE_600
+	rtie ilink2
+#else
+	rtie
+#endif
+
+/****** entry for normal interrupt exception handling ******/
+	.global exc_entry_int	/* entry for interrupt handling */
+	.align 4
+exc_entry_int:
+
+	INTERRUPT_PROLOGUE
+
+	mov	blink, sp
+
+	/* disable interrupt */
+	push r0
+	lr  r0, [AUX_STATUS32]
+	push r0
+    bclr r0, r0, AUX_STATUS_BIT_E1
+    bclr r0, r0, AUX_STATUS_BIT_E2
+    flag r0
+	ld	r3, [exc_nest_count]
+	add	r2, r3, 1
+	st	r2, [exc_nest_count]
+	/* enable interrupt */
+	pop r0
+	flag r0
+	pop r0
+
+	brne	r3, 0, irq_handler_1
+/* change to exception stack if interrupt happened in task context */
+	mov	sp, _e_stack
+#if ARC_FEATURE_STACK_CHECK
+	lr r0, [AUX_STATUS32]
+	bclr r0, r0, AUX_STATUS_BIT_SC
+	flag r0
+#endif
+irq_handler_1:
+	PUSH	blink
+
+/* critical area */
+#if ARC_FEATURE_CORE_700
+	lr	r0, [AUX_IRQ_CAUSE1]
+#endif
+	mov	r1, exc_int_handler_table
+	ld.as	r2, [r1, r0]	/* r2 = exc_int_handler_table + irqno *4 */
+/* handle software triggered interrupt */
+	lr	r3, [AUX_IRQ_HINT]
+	cmp	r3, r0
+	bne.d irq_hint_handled
+	xor	r3, r3, r3
+	sr	r3, [AUX_IRQ_HINT]
+irq_hint_handled:
+
+	jl	[r2]		/* jump to interrupt handler */
+/* no interrupts are allowed from here */
+ret_int:
+	clri	/* disable interrupt */
+
+	POP	sp
+	mov	r1, exc_nest_count
+	ld	r0, [r1]
+	sub	r0, r0, 1
+	st	r0, [r1]
+/* if there are multi-bits set in IRQ_LV12, it's still in nest interrupt */
+	lr	r1, [AUX_IRQ_LV12]
+
+	ld	r0, [context_switch_reqflg]
+	brne	r0, 0, ret_int_2
+ret_int_1:	/* return from non-task context */
+	INTERRUPT_EPILOGUE
+#if ARC_FEATURE_CORE_600
+/* TODO: series 600 IRQ6 and IRQ7 uses ilink2 */
+	rtie ilink1
+#else
+	rtie
+#endif
+/* there is a dispatch request */
+ret_int_2:
+	/* clear dispatch request */
+	mov	r0, 0
+	st	r0, [context_switch_reqflg]
+
+	ld	r0, [pxCurrentTCB]
+	breq 	r0, 0, ret_int_1
+
+/* r1 has old AUX_IRQ_LV12 */
+	PUSH	r1
+/* clear related bits in IRQ_ACT manually to simulate a irq return  */
+
+	SAVE_CALLEE_REGS	/* save callee save registers */
+	mov	r1, ret_int_r	/* save return address */
+	PUSH	r1
+
+	bl	dispatcher	/* r0->pxCurrentTCB */
+
+ret_int_r:
+	RESTORE_CALLEE_REGS	/* recover registers */
+	POPAX	AUX_IRQ_LV12
+	INTERRUPT_EPILOGUE
+#if ARC_FEATURE_CORE_600
+	rtie ilink1
+#else
+	rtie
+#endif
+
+/** @endcond */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/port.c
new file mode 100644
index 0000000..a99313a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/port.c
@@ -0,0 +1,295 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Implementation of functions defined in portable.h
+ */
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "FreeRTOSConfig.h"
+
+#include "arc/arc_exception.h"
+#include "arc/arc_timer.h"
+#include "board.h"
+
+#include "arc_freertos_exceptions.h"
+
+volatile unsigned int ulCriticalNesting = 999UL;
+volatile unsigned int context_switch_reqflg; /* task context switch request flag in exceptions and interrupts handling */
+
+/**
+ * \var exc_nest_count
+ * \brief the counter for exc/int processing, =0 no int/exc
+ * >1 in int/exc processing
+ * @}
+ */
+uint32_t exc_nest_count;
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief kernel tick interrupt handler of freertos
+ */
+/* ----------------------------------------------------------------------------*/
+static void vKernelTick( void * ptr )
+{
+    /* clear timer interrupt */
+    arc_timer_int_clear( BOARD_OS_TIMER_ID );
+    board_timer_update( configTICK_RATE_HZ );
+
+    if( xTaskIncrementTick() )
+    {
+        portYIELD_FROM_ISR(); /* need to make task switch */
+    }
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief  setup freertos kernel tick
+ */
+/* ----------------------------------------------------------------------------*/
+static void prvSetupTimerInterrupt( void )
+{
+    unsigned int cyc = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+    int_disable( BOARD_OS_TIMER_INTNO ); /* disable os timer interrupt */
+    arc_timer_stop( BOARD_OS_TIMER_ID );
+    arc_timer_start( BOARD_OS_TIMER_ID, TIMER_CTRL_IE | TIMER_CTRL_NH, cyc );
+
+    int_handler_install( BOARD_OS_TIMER_INTNO, ( INT_HANDLER_T ) vKernelTick );
+    int_pri_set( BOARD_OS_TIMER_INTNO, INT_PRI_MIN );
+    int_enable( BOARD_OS_TIMER_INTNO );
+}
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ * For ARC, task context switch is implemented with the help of SWI exception
+ * It's not efficient but simple.
+ *
+ */
+StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                     TaskFunction_t pxCode,
+                                     void * pvParameters )
+{
+    /* To ensure asserts in tasks.c don't fail, although in this case the assert
+     * is not really required. */
+    pxTopOfStack--;
+
+    /* Setup the initial stack of the task.  The stack is set exactly as
+     * expected by the portRESTORE_CONTEXT() macro. */
+
+    /* When the task starts is will expect to find the function parameter in
+     * R0. */
+    *pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
+
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) pxCode; /* function body */
+
+    /* PC */
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) start_r; /* dispatch return address */
+
+    pxTopOfStack--;
+    *pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING;
+    return pxTopOfStack;
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief  start the freertos scheduler, go to the first task
+ *
+ * @returns
+ */
+/* ----------------------------------------------------------------------------*/
+BaseType_t xPortStartScheduler( void )
+{
+    /* Start the timer that generates the tick ISR. */
+    prvSetupTimerInterrupt();
+    start_dispatch();
+
+    /* Should not get here! */
+    return 0;
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief
+ */
+/* ----------------------------------------------------------------------------*/
+void vPortEndScheduler( void )
+{
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief  generate a task switch request in ISR
+ */
+/* ----------------------------------------------------------------------------*/
+void vPortYieldFromIsr( void )
+{
+    unsigned int status32;
+
+    status32 = cpu_lock_save();
+    context_switch_reqflg = true;
+    cpu_unlock_restore( status32 );
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief
+ */
+/* ----------------------------------------------------------------------------*/
+void vPortYield( void )
+{
+    unsigned int status32;
+
+    status32 = cpu_lock_save();
+    dispatch();
+    cpu_unlock_restore( status32 );
+}
+
+/* --------------------------------------------------------------------------*/
+
+/**
+ * @brief
+ */
+/* ----------------------------------------------------------------------------*/
+void vPortEndTask( void )
+{
+    #if ( INCLUDE_vTaskDelete == 1 )
+        vTaskDelete( NULL ); /* Delete task itself */
+    #endif
+
+    while( 1 ) /* Yield to other task */
+    {
+        vPortYield();
+    }
+}
+
+#if ARC_FEATURE_STACK_CHECK
+
+/*
+ * !!! Note !!!
+ * This a trick!!!
+ * It's a copy from task.c. We need to konw the definition of TCB for the purpose of hardware
+ * stack check. Pls don't forget to update it when FreeRTOS is updated.
+ */
+    typedef struct tskTaskControlBlock       /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+    {
+        volatile StackType_t * pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+        #if ( portUSING_MPU_WRAPPERS == 1 )
+            xMPU_SETTINGS xMPUSettings;     /*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+        #endif
+
+        ListItem_t xStateListItem;                  /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+        ListItem_t xEventListItem;                  /*< Used to reference a task from an event list. */
+        UBaseType_t uxPriority;                     /*< The priority of the task.  0 is the lowest priority. */
+        StackType_t * pxStack;                      /*< Points to the start of the stack. */
+        char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+        #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+            StackType_t * pxEndOfStack;     /*< Points to the highest valid address for the stack. */
+        #endif
+
+        #if ( portCRITICAL_NESTING_IN_TCB == 1 )
+            UBaseType_t uxCriticalNesting;  /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+        #endif
+
+        #if ( configUSE_TRACE_FACILITY == 1 )
+            UBaseType_t uxTCBNumber;        /*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+            UBaseType_t uxTaskNumber;       /*< Stores a number specifically for use by third party trace code. */
+        #endif
+
+        #if ( configUSE_MUTEXES == 1 )
+            UBaseType_t uxBasePriority;     /*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+            UBaseType_t uxMutexesHeld;
+        #endif
+
+        #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+            TaskHookFunction_t pxTaskTag;
+        #endif
+
+        #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+            void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+        #endif
+
+        #if ( configGENERATE_RUN_TIME_STATS == 1 )
+            uint32_t ulRunTimeCounter;      /*< Stores the amount of time the task has spent in the Running state. */
+        #endif
+
+        #if ( configUSE_NEWLIB_REENTRANT == 1 )
+
+            /* Allocate a Newlib reent structure that is specific to this task.
+             * Note Newlib support has been included by popular demand, but is not
+             * used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+             * responsible for resulting newlib operation.  User must be familiar with
+             * newlib and must provide system-wide implementations of the necessary
+             * stubs. Be warned that (at the time of writing) the current newlib design
+             * implements a system-wide malloc() that must be provided with locks. */
+            struct  _reent xNewLib_reent;
+        #endif
+
+        #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+            volatile uint32_t ulNotifiedValue;
+            volatile uint8_t ucNotifyState;
+        #endif
+
+        /* See the comments above the definition of
+         * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+        #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+            uint8_t ucStaticallyAllocated;                     /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+        #endif
+
+        #if ( INCLUDE_xTaskAbortDelay == 1 )
+            uint8_t ucDelayAborted;
+        #endif
+
+        #if ( configUSE_POSIX_ERRNO == 1 )
+            int iTaskErrno;
+        #endif
+    } tskTCB;
+
+
+    void vPortSetStackCheck( TaskHandle_t old,
+                             TaskHandle_t new )
+    {
+        if( new != NULL )
+        {
+            arc_aux_write( AUX_USTACK_BASE, ( uint32_t ) ( new->pxEndOfStack ) );
+            arc_aux_write( AUX_USTACK_TOP, ( uint32_t ) ( new->pxStack ) );
+        }
+    }
+#endif /* if ARC_FEATURE_STACK_CHECK */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/portmacro.h
new file mode 100644
index 0000000..73f8c29
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARC_v1/portmacro.h
@@ -0,0 +1,149 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Synopsys, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+    #define PORTMACRO_H
+    #include "embARC.h"
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+/* record stack high address for stack check */
+    #ifndef configRECORD_STACK_HIGH_ADDRESS
+        #define configRECORD_STACK_HIGH_ADDRESS    1
+    #endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+    #define portCHAR          char
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          long
+    #define portSHORT         short
+    #define portSTACK_TYPE    unsigned int
+    #define portBASE_TYPE     portLONG
+
+    #ifndef Asm
+        #define Asm           __asm__ volatile
+    #endif
+
+/*
+ *  normal constants
+ */
+    #ifndef NULL
+        #define NULL    0       /* invalid pointer */
+    #endif /* NULL */
+
+    #ifndef true
+        #define true    1       /* true */
+    #endif /* true */
+
+    #ifndef false
+        #define false    0      /* false */
+    #endif /* false */
+
+    typedef portSTACK_TYPE     StackType_t;
+    typedef long               BaseType_t;
+    typedef unsigned long      UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t       TickType_t;
+        #define portMAX_DELAY          ( TickType_t ) 0xffff
+    #else
+        typedef unsigned int   TickType_t;
+        #define portMAX_DELAY          ( TickType_t ) 0xffffffffUL
+    #endif
+
+    #define portNO_CRITICAL_NESTING    ( ( uint32_t ) 0 )
+    #define portSTACK_GROWTH           ( -1 )
+    #define portTICK_PERIOD_MS         ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT         8
+    #define portNOP()               Asm( "nop_s" );
+    #define IPM_ENABLE_ALL             1
+
+    #define portYIELD_FROM_ISR()    vPortYieldFromIsr()
+    #define portYIELD()             vPortYield()
+
+/* Critical section management. */
+    #define portDISABLE_INTERRUPTS() \
+    {                                \
+        arc_lock();                  \
+    }                                \
+
+    #define portENABLE_INTERRUPTS() \
+    {                               \
+        arc_unlock();               \
+    }                               \
+
+    extern volatile unsigned int ulCriticalNesting;
+
+    #define portENTER_CRITICAL() \
+    {                            \
+        portDISABLE_INTERRUPTS() \
+        ulCriticalNesting++;     \
+    }
+
+
+    #define portEXIT_CRITICAL()                                \
+    {                                                          \
+        if( ulCriticalNesting > portNO_CRITICAL_NESTING )      \
+        {                                                      \
+            ulCriticalNesting--;                               \
+            if( ulCriticalNesting == portNO_CRITICAL_NESTING ) \
+            {                                                  \
+                portENABLE_INTERRUPTS()                        \
+            }                                                  \
+        }                                                      \
+    }
+
+
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+    #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()              do {} while( 0 ) /* we use the timer */
+    #define portALT_GET_RUN_TIME_COUNTER_VALUE( dest )            ( dest = xTickCount )
+
+    #define portCLEAN_UP_TCB( pxTCB )                             ( void ) pxTCB
+
+    void vPortYield( void );
+    void vPortYieldFromIsr( void );
+
+    #ifdef __cplusplus
+}
+    #endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARM_CM33_TFM/README.md b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARM_CM33_TFM/README.md
new file mode 100644
index 0000000..6b03f56
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARM_CM33_TFM/README.md
@@ -0,0 +1,71 @@
+# Target of this port
+
+This port adds the support that FreeRTOS applications can call the secure
+services in Trusted Firmware M(TF-M) through Platform Security Architecture
+(PSA) API based on the ARM Cortex-M33 platform.
+
+The Platform Security Architecture (PSA) makes it quicker, easier and cheaper
+to design security into a device from the ground up. PSA is made up of four key
+stages: analyze, architect, implement, and certify. See [PSA Resource Page](https://developer.arm.com/architectures/security-architectures/platform-security-architecture).
+
+TF-M is an open source project. It provides a reference implementation of PSA
+for Arm M-profile architecture. Please get the details from this [link](https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/about/).
+
+# Derivation of the source code
+
+* ```os_wrapper_freertos.c```
+  The implementation of APIs which are defined in ```os_wrapper\mutex.h``` by TF-M
+  (tag: TF-Mv1.1). The implementation is based on FreeRTOS mutex type semaphore.
+
+# Usage notes
+
+To build a project based on this port:
+* Step 1: build the secure image. Please follow the **Build the Secure Side** section for details.
+* Step 2: build the nonsecure image. Please follow the **Build the Non-Secure Side** for details.
+
+## Build the Secure Side
+
+### Get the TF-M source code
+
+See the [link](https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/) to get the source code. This port is based on TF-M version **tag: TF-Mv1.1**.
+
+### Build TF-M
+
+Please refer to this [link](https://git.trustedfirmware.org/TF-M/trusted-firmware-m.git/tree/docs/getting_started/tfm_build_instruction.rst) to build the secure side.
+_**Note:** ```CONFIG_TFM_ENABLE_CTX_MGMT``` must be configured as "OFF" when building TF-M_.
+
+## Build the Non-Secure Side
+
+Please copy all the files in ```freertos_kernel\portable\GCC\ARM_CM33_NTZ``` into the ```freertos_kernel\portable\GCC\ARM_CM33_TFM``` folder before using this port. Note that TrustZone is enabled in this port. The TF-M runs in the Secure Side.
+
+Please call the API ```tfm_ns_interface_init()``` which is defined in ```os_wrapper_freertos.c``` at the very beginning of your application. Otherwise, it will always fail when calling a TF-M service in the Nonsecure Side.
+
+### Configuration in FreeRTOS kernel
+
+* ```configRUN_FREERTOS_SECURE_ONLY```
+This macro should be configured as 0. In this port, TF-M runs in the Secure Side while FreeRTOS
+Kernel runs in the Non-Secure Side.
+
+* ```configENABLE_FPU```
+The setting of this macro is decided by the setting in Secure Side which is platform-specific.
+If the Secure Side enables Non-Secure access to FPU, then this macro can be configured as 0 or 1. Otherwise, this macro can only be configured as 0.
+
+* ```configENABLE_TRUSTZONE```
+This macro should be configured as 0 because TF-M doesn't use the secure context management function of FreeRTOS. New secure context management might be introduced when TF-M supports multiple secure context.
+
+
+### Integrate TF-M Non-Secure interface with FreeRTOS project
+
+To enable calling TF-M services by the Non-Secure Side, the files below should be included in the FreeRTOS project and built together.
+* files in ```trusted-firmware-m\build\install\export\tfm\src```
+  These files contain the implementation of PSA Functional Developer APIs which can be called by Non-Secure Side directly and PSA Firmware Framework APIs in the IPC model. These files should be taken
+  as part of the Non-Secure source code.
+* files in ```trusted-firmware-m\build\install\export\tfm\include```
+  These files are the necessary header files to call TF-M services.
+* ```trusted-firmware-m\build\install\export\tfm\veneers\s_veneers.o```
+  This object file contains all the Non-Secure callable functions exported by
+  TF-M and it should be linked when generating the Non-Secure image.
+
+
+
+*Copyright (c) 2020, Arm Limited. All rights reserved.*
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARM_CM33_TFM/os_wrapper_freertos.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARM_CM33_TFM/os_wrapper_freertos.c
new file mode 100644
index 0000000..5e9145b
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ARM_CM33_TFM/os_wrapper_freertos.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+/*
+ * This file contains the implementation of APIs which are defined in
+ * os_wrapper/mutex.h by TF-M(tag: TF-Mv1.1). The implementation is based
+ * on FreeRTOS mutex type semaphore.
+ */
+
+#include "os_wrapper/mutex.h"
+
+#include "FreeRTOS.h"
+#include "semphr.h"
+#include "mpu_wrappers.h"
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	/*
+	 * In the static allocation, the RAM is required to hold the semaphore's
+	 * state.
+	 */
+	StaticSemaphore_t xSecureMutexBuffer;
+#endif
+
+void * os_wrapper_mutex_create( void )
+{
+SemaphoreHandle_t xMutexHandle = NULL;
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	xMutexHandle = xSemaphoreCreateMutex();
+#elif( configSUPPORT_STATIC_ALLOCATION == 1 )
+	xMutexHandle = xSemaphoreCreateMutexStatic( &xSecureMutexBuffer );
+#endif
+	return ( void * ) xMutexHandle;
+}
+/*-----------------------------------------------------------*/
+
+uint32_t os_wrapper_mutex_acquire( void * handle, uint32_t timeout )
+{
+BaseType_t xRet;
+
+	if( ! handle )
+		return OS_WRAPPER_ERROR;
+
+	xRet = xSemaphoreTake( ( SemaphoreHandle_t ) handle,
+						   ( timeout == OS_WRAPPER_WAIT_FOREVER ) ?
+                           portMAX_DELAY : ( TickType_t ) timeout );
+
+	if( xRet != pdPASS )
+		return OS_WRAPPER_ERROR;
+	else
+		return OS_WRAPPER_SUCCESS;
+}
+/*-----------------------------------------------------------*/
+
+uint32_t os_wrapper_mutex_release( void * handle )
+{
+BaseType_t xRet;
+
+	if( !handle )
+		return OS_WRAPPER_ERROR;
+
+	xRet = xSemaphoreGive( ( SemaphoreHandle_t ) handle );
+
+	if( xRet != pdPASS )
+		return OS_WRAPPER_ERROR;
+	else
+		return OS_WRAPPER_SUCCESS;
+}
+/*-----------------------------------------------------------*/
+
+uint32_t os_wrapper_mutex_delete( void * handle )
+{
+	vSemaphoreDelete( ( SemaphoreHandle_t ) handle );
+
+	return OS_WRAPPER_SUCCESS;
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ATmega/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ATmega/port.c
new file mode 100644
index 0000000..8ad81b1
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ATmega/port.c
@@ -0,0 +1,765 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#include <stdlib.h>
+
+#include <avr/io.h>
+#include <avr/interrupt.h>
+#include <avr/wdt.h>
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the AVR port.
+ *----------------------------------------------------------*/
+
+/* Start tasks with interrupts enabled. */
+#define portFLAGS_INT_ENABLED           ( (StackType_t) 0x80 )
+
+#if defined( portUSE_WDTO)
+    #warning "Watchdog Timer used for scheduler."
+    #define portSCHEDULER_ISR           WDT_vect
+
+#elif defined( portUSE_TIMER0 )
+/* Hardware constants for Timer0. */
+    #warning "Timer0 used for scheduler."
+    #define portSCHEDULER_ISR           TIMER0_COMPA_vect
+    #define portCLEAR_COUNTER_ON_MATCH  ( (uint8_t) _BV(WGM01) )
+    #define portPRESCALE_1024           ( (uint8_t) (_BV(CS02)|_BV(CS00)) )
+    #define portCLOCK_PRESCALER         ( (uint32_t) 1024 )
+    #define portCOMPARE_MATCH_A_INTERRUPT_ENABLE    ( (uint8_t) _BV(OCIE0A) )
+    #define portOCRL                    OCR0A
+    #define portTCCRa                   TCCR0A
+    #define portTCCRb                   TCCR0B
+    #define portTIMSK                   TIMSK0
+    #define portTIFR                    TIFR0
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/*-----------------------------------------------------------*/
+
+/**
+    Enable the watchdog timer, configuring it for expire after
+    (value) timeout (which is a combination of the WDP0
+    through WDP3 bits).
+
+    This function is derived from <avr/wdt.h> but enables only
+    the interrupt bit (WDIE), rather than the reset bit (WDE).
+
+    Can't find it documented but the WDT, once enabled,
+    rolls over and fires a new interrupt each time.
+
+    See also the symbolic constants WDTO_15MS et al.
+
+    Updated to match avr-libc 2.0.0
+*/
+
+#if defined( portUSE_WDTO)
+
+static __inline__
+__attribute__ ((__always_inline__))
+void wdt_interrupt_enable (const uint8_t value)
+{
+    if (_SFR_IO_REG_P (_WD_CONTROL_REG))
+    {
+        __asm__ __volatile__ (
+                "in __tmp_reg__,__SREG__"   "\n\t"
+                "cli"                       "\n\t"
+                "wdr"                       "\n\t"
+                "out %0, %1"                "\n\t"
+                "out __SREG__,__tmp_reg__"  "\n\t"
+                "out %0, %2"                "\n\t"
+                : /* no outputs */
+                : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
+                "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
+                "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
+                        _BV(WDIF) | _BV(WDIE) | (value & 0x07)) )
+                : "r0"
+        );
+    }
+    else
+    {
+        __asm__ __volatile__ (
+                "in __tmp_reg__,__SREG__"   "\n\t"
+                "cli"                       "\n\t"
+                "wdr"                       "\n\t"
+                "sts %0, %1"                "\n\t"
+                "out __SREG__,__tmp_reg__"  "\n\t"
+                "sts %0, %2"                "\n\t"
+                : /* no outputs */
+                : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
+                "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
+                "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
+                        _BV(WDIF) | _BV(WDIE) | (value & 0x07)) )
+                : "r0"
+        );
+    }
+}
+#endif
+
+/*-----------------------------------------------------------*/
+/**
+    Enable the watchdog timer, configuring it for expire after
+    (value) timeout (which is a combination of the WDP0
+    through WDP3 bits).
+
+    This function is derived from <avr/wdt.h> but enables both
+    the reset bit (WDE), and the interrupt bit (WDIE).
+
+    This will ensure that if the interrupt is not serviced
+    before the second timeout, the AVR will reset.
+
+    Servicing the interrupt automatically clears it,
+    and ensures the AVR does not reset.
+
+    Can't find it documented but the WDT, once enabled,
+    rolls over and fires a new interrupt each time.
+
+    See also the symbolic constants WDTO_15MS et al.
+
+    Updated to match avr-libc 2.0.0
+*/
+
+#if defined( portUSE_WDTO)
+
+static __inline__
+__attribute__ ((__always_inline__))
+void wdt_interrupt_reset_enable (const uint8_t value)
+{
+    if (_SFR_IO_REG_P (_WD_CONTROL_REG))
+    {
+        __asm__ __volatile__ (
+                "in __tmp_reg__,__SREG__"   "\n\t"
+                "cli"                       "\n\t"
+                "wdr"                       "\n\t"
+                "out %0, %1"                "\n\t"
+                "out __SREG__,__tmp_reg__"  "\n\t"
+                "out %0, %2"                "\n\t"
+                : /* no outputs */
+                : "I" (_SFR_IO_ADDR(_WD_CONTROL_REG)),
+                "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
+                "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
+                        _BV(WDIF) | _BV(WDIE) | _BV(WDE) | (value & 0x07)) )
+                : "r0"
+        );
+    }
+    else
+    {
+        __asm__ __volatile__ (
+                "in __tmp_reg__,__SREG__"   "\n\t"
+                "cli"                       "\n\t"
+                "wdr"                       "\n\t"
+                "sts %0, %1"                "\n\t"
+                "out __SREG__,__tmp_reg__"  "\n\t"
+                "sts %0, %2"                "\n\t"
+                : /* no outputs */
+                : "n" (_SFR_MEM_ADDR(_WD_CONTROL_REG)),
+                "r" ((uint8_t)(_BV(_WD_CHANGE_BIT) | _BV(WDE))),
+                "r" ((uint8_t) ((value & 0x08 ? _WD_PS3_MASK : 0x00) |
+                        _BV(WDIF) | _BV(WDIE) | _BV(WDE) | (value & 0x07)) )
+                : "r0"
+        );
+    }
+}
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to save all the general purpose registers, the save the stack pointer
+ * into the TCB.
+ *
+ * The first thing we do is save the flags then disable interrupts. This is to
+ * guard our stack against having a context switch interrupt after we have already
+ * pushed the registers onto the stack - causing the 32 registers to be on the
+ * stack twice.
+ *
+ * r1 is set to zero (__zero_reg__) as the compiler expects it to be thus, however
+ * some of the math routines make use of R1.
+ *
+ * r0 is set to __tmp_reg__ as the compiler expects it to be thus.
+ *
+ * #if defined(__AVR_HAVE_RAMPZ__)
+ * #define __RAMPZ__ 0x3B
+ * #endif
+ *
+ * #if defined(__AVR_3_BYTE_PC__)
+ * #define __EIND__ 0x3C
+ * #endif
+ *
+ * The interrupts will have been disabled during the call to portSAVE_CONTEXT()
+ * so we need not worry about reading/writing to the stack pointer.
+ */
+#if defined(__AVR_3_BYTE_PC__) && defined(__AVR_HAVE_RAMPZ__)
+/* 3-Byte PC Save  with RAMPZ */
+#define portSAVE_CONTEXT()                                                              \
+        __asm__ __volatile__ (  "push   __tmp_reg__                             \n\t"   \
+                                "in     __tmp_reg__, __SREG__                   \n\t"   \
+                                "cli                                            \n\t"   \
+                                "push   __tmp_reg__                             \n\t"   \
+                                "in     __tmp_reg__, 0x3B                       \n\t"   \
+                                "push   __tmp_reg__                             \n\t"   \
+                                "in     __tmp_reg__, 0x3C                       \n\t"   \
+                                "push   __tmp_reg__                             \n\t"   \
+                                "push   __zero_reg__                            \n\t"   \
+                                "clr    __zero_reg__                            \n\t"   \
+                                "push   r2                                      \n\t"   \
+                                "push   r3                                      \n\t"   \
+                                "push   r4                                      \n\t"   \
+                                "push   r5                                      \n\t"   \
+                                "push   r6                                      \n\t"   \
+                                "push   r7                                      \n\t"   \
+                                "push   r8                                      \n\t"   \
+                                "push   r9                                      \n\t"   \
+                                "push   r10                                     \n\t"   \
+                                "push   r11                                     \n\t"   \
+                                "push   r12                                     \n\t"   \
+                                "push   r13                                     \n\t"   \
+                                "push   r14                                     \n\t"   \
+                                "push   r15                                     \n\t"   \
+                                "push   r16                                     \n\t"   \
+                                "push   r17                                     \n\t"   \
+                                "push   r18                                     \n\t"   \
+                                "push   r19                                     \n\t"   \
+                                "push   r20                                     \n\t"   \
+                                "push   r21                                     \n\t"   \
+                                "push   r22                                     \n\t"   \
+                                "push   r23                                     \n\t"   \
+                                "push   r24                                     \n\t"   \
+                                "push   r25                                     \n\t"   \
+                                "push   r26                                     \n\t"   \
+                                "push   r27                                     \n\t"   \
+                                "push   r28                                     \n\t"   \
+                                "push   r29                                     \n\t"   \
+                                "push   r30                                     \n\t"   \
+                                "push   r31                                     \n\t"   \
+                                "lds    r26, pxCurrentTCB                       \n\t"   \
+                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
+                                "in     __tmp_reg__, __SP_L__                   \n\t"   \
+                                "st     x+, __tmp_reg__                         \n\t"   \
+                                "in     __tmp_reg__, __SP_H__                   \n\t"   \
+                                "st     x+, __tmp_reg__                         \n\t"   \
+                             );
+#elif defined(__AVR_HAVE_RAMPZ__)
+/* 2-Byte PC Save  with RAMPZ */
+#define portSAVE_CONTEXT()                                                              \
+        __asm__ __volatile__ (  "push   __tmp_reg__                             \n\t"   \
+                                "in     __tmp_reg__, __SREG__                   \n\t"   \
+                                "cli                                            \n\t"   \
+                                "push   __tmp_reg__                             \n\t"   \
+                                "in     __tmp_reg__, 0x3B                       \n\t"   \
+                                "push   __tmp_reg__                             \n\t"   \
+                                "push   __zero_reg__                            \n\t"   \
+                                "clr    __zero_reg__                            \n\t"   \
+                                "push   r2                                      \n\t"   \
+                                "push   r3                                      \n\t"   \
+                                "push   r4                                      \n\t"   \
+                                "push   r5                                      \n\t"   \
+                                "push   r6                                      \n\t"   \
+                                "push   r7                                      \n\t"   \
+                                "push   r8                                      \n\t"   \
+                                "push   r9                                      \n\t"   \
+                                "push   r10                                     \n\t"   \
+                                "push   r11                                     \n\t"   \
+                                "push   r12                                     \n\t"   \
+                                "push   r13                                     \n\t"   \
+                                "push   r14                                     \n\t"   \
+                                "push   r15                                     \n\t"   \
+                                "push   r16                                     \n\t"   \
+                                "push   r17                                     \n\t"   \
+                                "push   r18                                     \n\t"   \
+                                "push   r19                                     \n\t"   \
+                                "push   r20                                     \n\t"   \
+                                "push   r21                                     \n\t"   \
+                                "push   r22                                     \n\t"   \
+                                "push   r23                                     \n\t"   \
+                                "push   r24                                     \n\t"   \
+                                "push   r25                                     \n\t"   \
+                                "push   r26                                     \n\t"   \
+                                "push   r27                                     \n\t"   \
+                                "push   r28                                     \n\t"   \
+                                "push   r29                                     \n\t"   \
+                                "push   r30                                     \n\t"   \
+                                "push   r31                                     \n\t"   \
+                                "lds    r26, pxCurrentTCB                       \n\t"   \
+                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
+                                "in     __tmp_reg__, __SP_L__                   \n\t"   \
+                                "st     x+, __tmp_reg__                         \n\t"   \
+                                "in     __tmp_reg__, __SP_H__                   \n\t"   \
+                                "st     x+, __tmp_reg__                         \n\t"   \
+                             );
+#else
+/* 2-Byte PC Save */
+#define portSAVE_CONTEXT()                                                              \
+        __asm__ __volatile__ (  "push   __tmp_reg__                             \n\t"   \
+                                "in     __tmp_reg__, __SREG__                   \n\t"   \
+                                "cli                                            \n\t"   \
+                                "push   __tmp_reg__                             \n\t"   \
+                                "push   __zero_reg__                            \n\t"   \
+                                "clr    __zero_reg__                            \n\t"   \
+                                "push   r2                                      \n\t"   \
+                                "push   r3                                      \n\t"   \
+                                "push   r4                                      \n\t"   \
+                                "push   r5                                      \n\t"   \
+                                "push   r6                                      \n\t"   \
+                                "push   r7                                      \n\t"   \
+                                "push   r8                                      \n\t"   \
+                                "push   r9                                      \n\t"   \
+                                "push   r10                                     \n\t"   \
+                                "push   r11                                     \n\t"   \
+                                "push   r12                                     \n\t"   \
+                                "push   r13                                     \n\t"   \
+                                "push   r14                                     \n\t"   \
+                                "push   r15                                     \n\t"   \
+                                "push   r16                                     \n\t"   \
+                                "push   r17                                     \n\t"   \
+                                "push   r18                                     \n\t"   \
+                                "push   r19                                     \n\t"   \
+                                "push   r20                                     \n\t"   \
+                                "push   r21                                     \n\t"   \
+                                "push   r22                                     \n\t"   \
+                                "push   r23                                     \n\t"   \
+                                "push   r24                                     \n\t"   \
+                                "push   r25                                     \n\t"   \
+                                "push   r26                                     \n\t"   \
+                                "push   r27                                     \n\t"   \
+                                "push   r28                                     \n\t"   \
+                                "push   r29                                     \n\t"   \
+                                "push   r30                                     \n\t"   \
+                                "push   r31                                     \n\t"   \
+                                "lds    r26, pxCurrentTCB                       \n\t"   \
+                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
+                                "in     __tmp_reg__, __SP_L__                   \n\t"   \
+                                "st     x+, __tmp_reg__                         \n\t"   \
+                                "in     __tmp_reg__, __SP_H__                   \n\t"   \
+                                "st     x+, __tmp_reg__                         \n\t"   \
+                             );
+#endif
+
+/*
+ * Opposite to portSAVE_CONTEXT().  Interrupts will have been disabled during
+ * the context save so we can write to the stack pointer.
+ */
+#if defined(__AVR_3_BYTE_PC__) && defined(__AVR_HAVE_RAMPZ__)
+/* 3-Byte PC Restore with RAMPZ */
+#define portRESTORE_CONTEXT()                                                           \
+        __asm__ __volatile__ (  "lds    r26, pxCurrentTCB                       \n\t"   \
+                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
+                                "ld     r28, x+                                 \n\t"   \
+                                "out    __SP_L__, r28                           \n\t"   \
+                                "ld     r29, x+                                 \n\t"   \
+                                "out    __SP_H__, r29                           \n\t"   \
+                                "pop    r31                                     \n\t"   \
+                                "pop    r30                                     \n\t"   \
+                                "pop    r29                                     \n\t"   \
+                                "pop    r28                                     \n\t"   \
+                                "pop    r27                                     \n\t"   \
+                                "pop    r26                                     \n\t"   \
+                                "pop    r25                                     \n\t"   \
+                                "pop    r24                                     \n\t"   \
+                                "pop    r23                                     \n\t"   \
+                                "pop    r22                                     \n\t"   \
+                                "pop    r21                                     \n\t"   \
+                                "pop    r20                                     \n\t"   \
+                                "pop    r19                                     \n\t"   \
+                                "pop    r18                                     \n\t"   \
+                                "pop    r17                                     \n\t"   \
+                                "pop    r16                                     \n\t"   \
+                                "pop    r15                                     \n\t"   \
+                                "pop    r14                                     \n\t"   \
+                                "pop    r13                                     \n\t"   \
+                                "pop    r12                                     \n\t"   \
+                                "pop    r11                                     \n\t"   \
+                                "pop    r10                                     \n\t"   \
+                                "pop    r9                                      \n\t"   \
+                                "pop    r8                                      \n\t"   \
+                                "pop    r7                                      \n\t"   \
+                                "pop    r6                                      \n\t"   \
+                                "pop    r5                                      \n\t"   \
+                                "pop    r4                                      \n\t"   \
+                                "pop    r3                                      \n\t"   \
+                                "pop    r2                                      \n\t"   \
+                                "pop    __zero_reg__                            \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                                "out    0x3C, __tmp_reg__                       \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                                "out    0x3B, __tmp_reg__                       \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                                "out    __SREG__, __tmp_reg__                   \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                             );
+#elif defined(__AVR_HAVE_RAMPZ__)
+/* 2-Byte PC Restore with RAMPZ */
+#define portRESTORE_CONTEXT()                                                           \
+        __asm__ __volatile__ (  "lds    r26, pxCurrentTCB                       \n\t"   \
+                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
+                                "ld     r28, x+                                 \n\t"   \
+                                "out    __SP_L__, r28                           \n\t"   \
+                                "ld     r29, x+                                 \n\t"   \
+                                "out    __SP_H__, r29                           \n\t"   \
+                                "pop    r31                                     \n\t"   \
+                                "pop    r30                                     \n\t"   \
+                                "pop    r29                                     \n\t"   \
+                                "pop    r28                                     \n\t"   \
+                                "pop    r27                                     \n\t"   \
+                                "pop    r26                                     \n\t"   \
+                                "pop    r25                                     \n\t"   \
+                                "pop    r24                                     \n\t"   \
+                                "pop    r23                                     \n\t"   \
+                                "pop    r22                                     \n\t"   \
+                                "pop    r21                                     \n\t"   \
+                                "pop    r20                                     \n\t"   \
+                                "pop    r19                                     \n\t"   \
+                                "pop    r18                                     \n\t"   \
+                                "pop    r17                                     \n\t"   \
+                                "pop    r16                                     \n\t"   \
+                                "pop    r15                                     \n\t"   \
+                                "pop    r14                                     \n\t"   \
+                                "pop    r13                                     \n\t"   \
+                                "pop    r12                                     \n\t"   \
+                                "pop    r11                                     \n\t"   \
+                                "pop    r10                                     \n\t"   \
+                                "pop    r9                                      \n\t"   \
+                                "pop    r8                                      \n\t"   \
+                                "pop    r7                                      \n\t"   \
+                                "pop    r6                                      \n\t"   \
+                                "pop    r5                                      \n\t"   \
+                                "pop    r4                                      \n\t"   \
+                                "pop    r3                                      \n\t"   \
+                                "pop    r2                                      \n\t"   \
+                                "pop    __zero_reg__                            \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                                "out    0x3B, __tmp_reg__                       \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                                "out    __SREG__, __tmp_reg__                   \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                             );
+#else
+/* 2-Byte PC Restore */
+#define portRESTORE_CONTEXT()                                                           \
+        __asm__ __volatile__ (  "lds    r26, pxCurrentTCB                       \n\t"   \
+                                "lds    r27, pxCurrentTCB + 1                   \n\t"   \
+                                "ld     r28, x+                                 \n\t"   \
+                                "out    __SP_L__, r28                           \n\t"   \
+                                "ld     r29, x+                                 \n\t"   \
+                                "out    __SP_H__, r29                           \n\t"   \
+                                "pop    r31                                     \n\t"   \
+                                "pop    r30                                     \n\t"   \
+                                "pop    r29                                     \n\t"   \
+                                "pop    r28                                     \n\t"   \
+                                "pop    r27                                     \n\t"   \
+                                "pop    r26                                     \n\t"   \
+                                "pop    r25                                     \n\t"   \
+                                "pop    r24                                     \n\t"   \
+                                "pop    r23                                     \n\t"   \
+                                "pop    r22                                     \n\t"   \
+                                "pop    r21                                     \n\t"   \
+                                "pop    r20                                     \n\t"   \
+                                "pop    r19                                     \n\t"   \
+                                "pop    r18                                     \n\t"   \
+                                "pop    r17                                     \n\t"   \
+                                "pop    r16                                     \n\t"   \
+                                "pop    r15                                     \n\t"   \
+                                "pop    r14                                     \n\t"   \
+                                "pop    r13                                     \n\t"   \
+                                "pop    r12                                     \n\t"   \
+                                "pop    r11                                     \n\t"   \
+                                "pop    r10                                     \n\t"   \
+                                "pop    r9                                      \n\t"   \
+                                "pop    r8                                      \n\t"   \
+                                "pop    r7                                      \n\t"   \
+                                "pop    r6                                      \n\t"   \
+                                "pop    r5                                      \n\t"   \
+                                "pop    r4                                      \n\t"   \
+                                "pop    r3                                      \n\t"   \
+                                "pop    r2                                      \n\t"   \
+                                "pop    __zero_reg__                            \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                                "out    __SREG__, __tmp_reg__                   \n\t"   \
+                                "pop    __tmp_reg__                             \n\t"   \
+                             );
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Perform hardware setup to enable ticks from relevant Timer.
+ */
+static void prvSetupTimerInterrupt( void );
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint16_t usAddress;
+    /* Simulate how the stack would look after a call to vPortYield() generated by
+    the compiler. */
+
+    /* The start of the task code will be popped off the stack last, so place
+    it on first. */
+    usAddress = ( uint16_t ) pxCode;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+#if defined(__AVR_3_BYTE_PC__)
+    /* The AVR ATmega2560/ATmega2561 have 256KBytes of program memory and a 17-bit
+     * program counter. When a code address is stored on the stack, it takes 3 bytes
+     * instead of 2 for the other ATmega* chips.
+     *
+     * Store 0 as the top byte since we force all task routines to the bottom 128K
+     * of flash. We do this by using the .lowtext label in the linker script.
+     *
+     * In order to do this properly, we would need to get a full 3-byte pointer to
+     * pxCode. That requires a change to GCC. Not likely to happen any time soon.
+     */
+    *pxTopOfStack = 0;
+    pxTopOfStack--;
+#endif
+
+    /* Next simulate the stack as if after a call to portSAVE_CONTEXT().
+    portSAVE_CONTEXT places the flags on the stack immediately after r0
+    to ensure the interrupts get disabled as soon as possible, and so ensuring
+    the stack use is minimal should a context switch interrupt occur. */
+    *pxTopOfStack = ( StackType_t ) 0x00;    /* R0 */
+    pxTopOfStack--;
+    *pxTopOfStack = portFLAGS_INT_ENABLED;
+    pxTopOfStack--;
+
+#if defined(__AVR_3_BYTE_PC__)
+    /* If we have an ATmega256x, we are also saving the EIND register.
+     * We should default to 0.
+     */
+    *pxTopOfStack = ( StackType_t ) 0x00;    /* EIND */
+    pxTopOfStack--;
+#endif
+
+#if defined(__AVR_HAVE_RAMPZ__)
+    /* We are saving the RAMPZ register.
+     * We should default to 0.
+     */
+    *pxTopOfStack = ( StackType_t ) 0x00;    /* RAMPZ */
+    pxTopOfStack--;
+#endif
+
+    /* Now the remaining registers. The compiler expects R1 to be 0. */
+    *pxTopOfStack = ( StackType_t ) 0x00;    /* R1 */
+
+    /* Leave R2 - R23 untouched */
+    pxTopOfStack -= 23;
+
+    /* Place the parameter on the stack in the expected location. */
+    usAddress = ( uint16_t ) pvParameters;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+    pxTopOfStack--;
+
+    usAddress >>= 8;
+    *pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
+
+    /* Leave register R26 - R31 untouched */
+    pxTopOfStack -= 7;
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+    /* Setup the relevant timer hardware to generate the tick. */
+    prvSetupTimerInterrupt();
+
+    /* Restore the context of the first task that is going to run. */
+    portRESTORE_CONTEXT();
+
+    /* Simulate a function call end as generated by the compiler. We will now
+    jump to the start of the task the context of which we have just restored. */
+    __asm__ __volatile__ ( "ret" );
+
+    /* Should not get here. */
+    return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the ATmega port will get stopped. */
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch. The first thing we do is save the registers so we
+ * can use a naked attribute.
+ */
+void vPortYield( void ) __attribute__ ( ( hot, flatten, naked ) );
+void vPortYield( void )
+{
+    portSAVE_CONTEXT();
+    vTaskSwitchContext();
+    portRESTORE_CONTEXT();
+
+    __asm__ __volatile__ ( "ret" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch callable from ISRs. The first thing we do is save
+ * the registers so we can use a naked attribute.
+ */
+void vPortYieldFromISR(void) __attribute__ ( ( hot, flatten, naked ) );
+void vPortYieldFromISR(void)
+{
+    portSAVE_CONTEXT();
+    vTaskSwitchContext();
+    portRESTORE_CONTEXT();
+
+    __asm__ __volatile__ ( "reti" );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Context switch function used by the tick. This must be identical to
+ * vPortYield() from the call to vTaskSwitchContext() onwards. The only
+ * difference from vPortYield() is the tick count is incremented as the
+ * call comes from the tick ISR.
+ */
+void vPortYieldFromTick( void ) __attribute__ ( ( hot, flatten, naked ) );
+void vPortYieldFromTick( void )
+{
+    portSAVE_CONTEXT();
+    if( xTaskIncrementTick() != pdFALSE )
+    {
+        vTaskSwitchContext();
+    }
+    portRESTORE_CONTEXT();
+
+    __asm__ __volatile__ ( "ret" );
+}
+/*-----------------------------------------------------------*/
+
+#if defined(portUSE_WDTO)
+/*
+ * Setup WDT to generate a tick interrupt.
+ */
+void prvSetupTimerInterrupt( void )
+{
+    /* reset watchdog */
+    wdt_reset();
+
+    /* set up WDT Interrupt (rather than the WDT Reset). */
+    wdt_interrupt_enable( portUSE_WDTO );
+}
+
+#elif defined (portUSE_TIMER0)
+/*
+ * Setup Timer0 compare match A to generate a tick interrupt.
+ */
+static void prvSetupTimerInterrupt( void )
+{
+uint32_t ulCompareMatch;
+uint8_t ucLowByte;
+
+    /* Using 8bit Timer0 to generate the tick. Correct fuses must be
+    selected for the configCPU_CLOCK_HZ clock.*/
+
+    ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
+
+    /* We only have 8 bits so have to scale 1024 to get our required tick rate. */
+    ulCompareMatch /= portCLOCK_PRESCALER;
+
+    /* Adjust for correct value. */
+    ulCompareMatch -= ( uint32_t ) 1;
+
+    /* Setup compare match value for compare match A. Interrupts are disabled
+    before this is called so we need not worry here. */
+    ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
+    portOCRL = ucLowByte;
+
+    /* Setup clock source and compare match behaviour. */
+    portTCCRa = portCLEAR_COUNTER_ON_MATCH;
+    portTCCRb = portPRESCALE_1024;
+
+
+    /* Enable the interrupt - this is okay as interrupt are currently globally disabled. */
+    ucLowByte = portTIMSK;
+    ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
+    portTIMSK = ucLowByte;
+}
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+#if configUSE_PREEMPTION == 1
+
+    /*
+     * Tick ISR for preemptive scheduler. We can use a naked attribute as
+     * the context is saved at the start of vPortYieldFromTick(). The tick
+     * count is incremented after the context is saved.
+     *
+     * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
+     *
+     */
+    ISR(portSCHEDULER_ISR, ISR_NAKED) __attribute__ ((hot, flatten));
+/*  ISR(portSCHEDULER_ISR, ISR_NAKED ISR_NOBLOCK) __attribute__ ((hot, flatten));
+ */
+    ISR(portSCHEDULER_ISR)
+    {
+        vPortYieldFromTick();
+        __asm__ __volatile__ ( "reti" );
+    }
+#else
+
+    /*
+     * Tick ISR for the cooperative scheduler. All this does is increment the
+     * tick count. We don't need to switch context, this can only be done by
+     * manual calls to taskYIELD();
+     *
+     * use ISR_NOBLOCK where there is an important timer running, that should preempt the scheduler.
+     */
+    ISR(portSCHEDULER_ISR) __attribute__ ((hot, flatten));
+/*  ISR(portSCHEDULER_ISR, ISR_NOBLOCK) __attribute__ ((hot, flatten));
+ */
+    ISR(portSCHEDULER_ISR)
+    {
+        xTaskIncrementTick();
+    }
+#endif
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ATmega/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ATmega/portmacro.h
new file mode 100644
index 0000000..46b7431
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ATmega/portmacro.h
@@ -0,0 +1,156 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+*/
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+#include <avr/wdt.h>
+
+/* Type definitions. */
+#define portCHAR                    char
+#define portFLOAT                   float
+#define portDOUBLE                  double
+#define portLONG                    long
+#define portSHORT                   int
+
+typedef uint8_t                     StackType_t;
+typedef int8_t                      BaseType_t;
+typedef uint8_t                     UBaseType_t;
+
+#if configUSE_16_BIT_TICKS == 1
+    typedef uint16_t                TickType_t;
+    #define portMAX_DELAY           ( TickType_t ) 0xffff
+#else
+    typedef uint32_t                TickType_t;
+    #define portMAX_DELAY           ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+
+#define portENTER_CRITICAL()        __asm__ __volatile__ (                          \
+                                        "in __tmp_reg__, __SREG__"        "\n\t"    \
+                                        "cli"                             "\n\t"    \
+                                        "push __tmp_reg__"                "\n\t"    \
+                                        ::: "memory"                                \
+                                        )
+
+
+#define portEXIT_CRITICAL()         __asm__ __volatile__ (                          \
+                                        "pop __tmp_reg__"                 "\n\t"    \
+                                        "out __SREG__, __tmp_reg__"       "\n\t"    \
+                                        ::: "memory"                                \
+                                        )
+
+
+#define portDISABLE_INTERRUPTS()    __asm__ __volatile__ ( "cli" ::: "memory")
+#define portENABLE_INTERRUPTS()     __asm__ __volatile__ ( "sei" ::: "memory")
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+
+/* System Tick  - Scheduler timer
+ * Prefer to use the enhanced Watchdog Timer, but also Timer0 is ok.
+ */
+
+#if defined(WDIE) && defined(WDIF)              /* If Enhanced WDT with interrupt capability is available */
+
+#define portUSE_WDTO                WDTO_15MS   /* use the Watchdog Timer for xTaskIncrementTick */
+
+/* Watchdog period options:         WDTO_15MS
+                                    WDTO_30MS
+                                    WDTO_60MS
+                                    WDTO_120MS
+                                    WDTO_250MS
+                                    WDTO_500MS
+                                    WDTO_1S
+                                    WDTO_2S
+*/
+
+#else
+
+#define portUSE_TIMER0                          /* use the 8-bit Timer0 for xTaskIncrementTick */
+
+#endif
+
+#define portSTACK_GROWTH            ( -1 )
+
+/* Timing for the scheduler.
+ * Watchdog Timer is 128kHz nominal,
+ * but 120 kHz at 5V DC and 25 degrees is actually more accurate,
+ * from data sheet.
+ */
+#if defined( portUSE_WDTO )
+#define portTICK_PERIOD_MS          ( (TickType_t) _BV( portUSE_WDTO + 4 ) )
+#else
+#define portTICK_PERIOD_MS          ( (TickType_t) 1000 / configTICK_RATE_HZ )
+#endif
+
+#define portBYTE_ALIGNMENT          1
+#define portNOP()                   __asm__ __volatile__ ( "nop" );
+/*-----------------------------------------------------------*/
+
+/* Kernel utilities. */
+extern void vPortYield( void )      __attribute__ ( ( naked ) );
+#define portYIELD()                 vPortYield()
+
+extern void vPortYieldFromISR( void )   __attribute__ ( ( naked ) );
+#define portYIELD_FROM_ISR()            vPortYieldFromISR()
+/*-----------------------------------------------------------*/
+
+#if defined(__AVR_3_BYTE_PC__)
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+
+/* Add .lowtext tag from the avr linker script avr6.x for ATmega2560 and ATmega2561
+ * to make sure functions are loaded in low memory.
+ */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__ ((section (".lowtext")))
+#else
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#endif
+
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ATmega/readme.md b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ATmega/readme.md
new file mode 100644
index 0000000..4afb4fe
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/ATmega/readme.md
@@ -0,0 +1,86 @@
+<h2>ATmegaxxxx</h2>
+
+__Port for generalised Microchip ATmega architecture__
+
+<h3>Description</h3>
+
+This port provides a basis for supporting all modern ATmega devices using either the Enhanced Watchdog Timer, or Timer0 (an 8-bit Timer generally available across the whole range).
+
+This initial commit contains the information required to build with System Tick being generated by either the:
+- Watchdog Timer, or
+- Timer0 - an 8-bit Timer, or
+- TimerN - a 16-bit Timer which will be configured by the user.
+
+Further commits can add support for 16-bit Timers available on many relevant devices. The availability of these 16-bit Timers is somewhat device specific, and these complex and highly configurable Timers are often used to generate phase correct PWM timing (for example) and they would be wasted as a simple System Tick.
+
+The port also provides support for the 3 byte program counter devices __ATmega2560__ and __ATmega2561__. Specific to these two devices the `EIND` register need to be preserved during a context switch. Also, due to a limitation in GCC, the scheduler needs to reside in the lower 128kB of flash for both of these devices. This is achieved by adding the `.lowtext` section attribute to the function prototype.
+
+To build generic Microchip (AVR) ATmega support the similarities across the family must be considered, and differences respected. Some comments on the strategy follow.
+
+<h3>System Tick</h3>
+
+The Microchip (AVR) ATmega family has limited Timer and Pin capabilities, and is designed to be used in physical applications, controlling hardware with PWM and recognising level and edge voltage changes. It does this mainly through the use of 16-bit Timers (for generating phase correct PWM by up/down counting), and Pins attached to Interrupts. The 8-bit Timers are also attached to Pins, and they can be used for more simple timing tasks, requiring only a single counting direction.
+
+The Timers not attached to Pins (and therefore not impacting the application of the device) are some 16-bit Timers (very device dependent, eg Timer3 on 1284p), The RTC Timer, and the Watch Dog Timer.
+
+The Watch Dog Timer is configured identically across most of the ATmega devices. It comes in two variants. 1. Old style (eg ATmega32) which does not have an Interrupt capability, and hence on these old devices cannot be used as the System Tick. and 2. New style enhanced WDT, which can generate an Interrupt, and is available on every relevant device.
+
+Using the Watch Dog Timer (WDT) to generate the System Tick does not impact its use as a watch dog. It can be configured to generate a System Tick interrupt, and then one period later to Reset the device if the interrupt is not serviced.
+
+Configuration and usage of the WDT is covered in `<avr/wdt.h>` which was revised in avr-libc 2.0.0.
+
+Two additional WDT functions are provided in `port.c`, which extend avr-libc functions to enable the WDT Interrupt without enabling Reset `wdt_interrupt_enable()`, and to enable both the Interrupt and the Reset `wdt_interrupt_reset_enable()`.
+
+<h3>3 Byte PC Devices</h3>
+
+The ATtiny, ATmega, ATxmega families can optionally support both 3 byte PC and 3 byte RAM addresses. However, focusing on just the ATmega family only two devices have a large Flash requiring them to use 3 byte PC. These are the __ATmega2560__ and __ATmega2561__. This PR provides support for these two devices in two ways.
+
+ - providing `portSAVE_CONTEXT()` and `portRESTORE_CONTEXT` saving both the __RAMPZ__ and __EIND__ registers.
+ - providing a `portTASK_FUNCTION_PROTO()` with the linker attribute `.lowtext` which is used to ensure that the scheduler and relevant functions remain in the lower 128kB of Flash.
+
+For devices which can support __XRAM__ and have the __RAMPZ__ register, this register is also preserved during the context switch.
+
+<h3>Interrupt Nesting</h3>
+
+The ATmega family does not support interrupt nesting, having only one interrupt priority. This means that when the Scheduler is running, interrupts are normally disabled.
+
+When a very time critical process is running, based on microsecond timing generated by one of the Timers, it is important to re-enable interrupts as early as possible in processing a Yield. Fortunately, this is supported through the use of the `NO_BLOCK` decorator when defining the Interrupt Service Routine.
+
+The `NO_BLOCK` decorator will enable the global interrupt early in the handling of an ISR (in this case for the Scheduler), and enable interrupts to be nested. Using this method, I've been able to successfully implement an [Audio Synthesiser](https://feilipu.me/2015/06/02/goldilocks-analogue-synthesizer/) with less than 83 microseconds for each cycle, whilst still running the Scheduler to handle display and input.
+
+Using `NO_BLOCK` is optional, and should only be done if a critical Timer should interrupt the Scheduler.
+
+<h3>Heap Management</h3>
+
+Most users of FreeRTOS will choose to manage their own heap using one of the pre-allocated heap management algorithms, but for those that choose to use `heap_3.c`, the wrappered `malloc()` method, there is an issue that needs to be addressed.
+
+The avr-libc library assumes that the stack will always be above the heap, and does a check for this when responding to a `malloc()` request. This is not the case when Tasks are running, as their stack is located in the early allocated heap address ranges which will be below free heap memory, and so the `malloc()` request will fail even though heap space is available.
+
+To avoid this issue causing `pvPort_Malloc()` to failing, the user needs to issue this tuning statement BEFORE they use the heap, or use the `xTaskCreate()` API.
+
+```c
+if( __malloc_heap_end == 0 )
+    __malloc_heap_end = (char *)(RAMEND - __malloc_margin);
+```
+Unfortunately in the repository there is nowhere sensible to include this statement as it should be included early in the `main()` function.
+
+For devices which can support __XRAM__ the user will need to tune the location of stack and heap according to their own requirements.
+
+<h3>Supported Devices</h3>
+
+ATmega devices with __ENHANCED WDT__ Interrupt capability - will use WDT.
+
+ - ATmega8U2/16U2/32U2 -> 2kB RAM
+ - ATmega16U4/32U4 - Arduino Leonardo -> 2.5kB RAM
+ - ATmega48PB/88PB/168PB/328PB - Arduino Uno -> 2kB RAM
+ - ATmega164PA/324PA/644PA/1284P - Goldilocks -> __16kB RAM__
+ - ATmega324PB -> 2kB RAM
+ - ATmega640/1280/2560/1281/2561 - Arduino Mega -> __8kB RAM + XRAM__
+
+ATmega devices without enhanced __WDT__ Interrupt capability - will use a 8-bit or 16-bit Timer.
+
+ - ATmega8A/16A/32A/64A/128A -> 4kB RAM
+ - ATmega165A/165PA/325A/325PA/3250A/3250PA/645A/645P/6450A/6450P -> 4kB RAM
+ - ATmega169A/169PA/329A/329PA/3290A/3290PA/649A/649P/6490A/6490P -> 4kB RAM
+ - ATmega808/809/1608/1609/3208/3209/4808/4809 - megaAVR 0-Series -> 6kB RAM
+ 
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/FreeRTOS-simulator-for-Linux.url b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/FreeRTOS-simulator-for-Linux.url
new file mode 100644
index 0000000..60f7ee8
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/FreeRTOS-simulator-for-Linux.url
@@ -0,0 +1,5 @@
+[{000214A0-0000-0000-C000-000000000046}]
+Prop3=19,11
+[InternetShortcut]
+IDList=
+URL=https://www.freertos.org/FreeRTOS-simulator-for-Linux.html
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/port.c
new file mode 100644
index 0000000..05d89ff
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/port.c
@@ -0,0 +1,562 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Posix port.
+ *
+ * Each task has a pthread which eases use of standard debuggers
+ * (allowing backtraces of tasks etc). Threads for tasks that are not
+ * running are blocked in sigwait().
+ *
+ * Task switch is done by resuming the thread for the next task by
+ * signaling the condition variable and then waiting on a condition variable
+ * with the current thread.
+ *
+ * The timer interrupt uses SIGALRM and care is taken to ensure that
+ * the signal handler runs only on the thread for the current task.
+ *
+ * Use of part of the standard C library requires care as some
+ * functions can take pthread mutexes internally which can result in
+ * deadlocks as the FreeRTOS kernel can switch tasks while they're
+ * holding a pthread mutex.
+ *
+ * stdio (printf() and friends) should be called from a single task
+ * only or serialized with a FreeRTOS primitive such as a binary
+ * semaphore or mutex.
+ *----------------------------------------------------------*/
+
+#include <errno.h>
+#include <pthread.h>
+#include <signal.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/time.h>
+#include <sys/times.h>
+#include <time.h>
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "utils/wait_for_event.h"
+/*-----------------------------------------------------------*/
+
+#define SIG_RESUME SIGUSR1
+
+typedef struct THREAD
+{
+    pthread_t pthread;
+    pdTASK_CODE pxCode;
+    void *pvParams;
+    BaseType_t xDying;
+    struct event *ev;
+} Thread_t;
+
+/*
+ * The additional per-thread data is stored at the beginning of the
+ * task's stack.
+ */
+static inline Thread_t *prvGetThreadFromTask(TaskHandle_t xTask)
+{
+StackType_t *pxTopOfStack = *(StackType_t **)xTask;
+
+    return (Thread_t *)(pxTopOfStack + 1);
+}
+
+/*-----------------------------------------------------------*/
+
+static pthread_once_t hSigSetupThread = PTHREAD_ONCE_INIT;
+static sigset_t xResumeSignals;
+static sigset_t xAllSignals;
+static sigset_t xSchedulerOriginalSignalMask;
+static pthread_t hMainThread = ( pthread_t )NULL;
+static volatile portBASE_TYPE uxCriticalNesting;
+/*-----------------------------------------------------------*/
+
+static portBASE_TYPE xSchedulerEnd = pdFALSE;
+/*-----------------------------------------------------------*/
+
+static void prvSetupSignalsAndSchedulerPolicy( void );
+static void prvSetupTimerInterrupt( void );
+static void *prvWaitForStart( void * pvParams );
+static void prvSwitchThread( Thread_t * xThreadToResume,
+                             Thread_t *xThreadToSuspend );
+static void prvSuspendSelf( Thread_t * thread);
+static void prvResumeThread( Thread_t * xThreadId );
+static void vPortSystemTickHandler( int sig );
+static void vPortStartFirstTask( void );
+/*-----------------------------------------------------------*/
+
+static void prvFatalError( const char *pcCall, int iErrno )
+{
+    fprintf( stderr, "%s: %s\n", pcCall, strerror( iErrno ) );
+    abort();
+}
+
+/*
+ * See header file for description.
+ */
+portSTACK_TYPE *pxPortInitialiseStack( portSTACK_TYPE *pxTopOfStack,
+                                       portSTACK_TYPE *pxEndOfStack,
+                                       pdTASK_CODE pxCode, void *pvParameters )
+{
+Thread_t *thread;
+pthread_attr_t xThreadAttributes;
+size_t ulStackSize;
+int iRet;
+
+    (void)pthread_once( &hSigSetupThread, prvSetupSignalsAndSchedulerPolicy );
+
+    /*
+     * Store the additional thread data at the start of the stack.
+     */
+    thread = (Thread_t *)(pxTopOfStack + 1) - 1;
+    pxTopOfStack = (portSTACK_TYPE *)thread - 1;
+    ulStackSize = (pxTopOfStack + 1 - pxEndOfStack) * sizeof(*pxTopOfStack);
+
+    thread->pxCode = pxCode;
+    thread->pvParams = pvParameters;
+    thread->xDying = pdFALSE;
+
+    pthread_attr_init( &xThreadAttributes );
+    pthread_attr_setstack( &xThreadAttributes, pxEndOfStack, ulStackSize );
+
+    thread->ev = event_create();
+
+    vPortEnterCritical();
+
+    iRet = pthread_create( &thread->pthread, &xThreadAttributes,
+                           prvWaitForStart, thread );
+    if ( iRet )
+    {
+        prvFatalError( "pthread_create", iRet );
+    }
+
+    vPortExitCritical();
+
+    return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+void vPortStartFirstTask( void )
+{
+Thread_t *pxFirstThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+
+    /* Start the first task. */
+    prvResumeThread( pxFirstThread );
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+portBASE_TYPE xPortStartScheduler( void )
+{
+int iSignal;
+sigset_t xSignals;
+
+    hMainThread = pthread_self();
+
+    /* Start the timer that generates the tick ISR(SIGALRM).
+       Interrupts are disabled here already. */
+    prvSetupTimerInterrupt();
+
+    /* Start the first task. */
+    vPortStartFirstTask();
+
+    /* Wait until signaled by vPortEndScheduler(). */
+    sigemptyset( &xSignals );
+    sigaddset( &xSignals, SIG_RESUME );
+
+    while ( !xSchedulerEnd )
+    {
+        sigwait( &xSignals, &iSignal );
+    }
+
+    /* Cancel the Idle task and free its resources */
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+    vPortCancelThread( xTaskGetIdleTaskHandle() );
+#endif
+
+#if ( configUSE_TIMERS == 1 )
+    /* Cancel the Timer task and free its resources */
+    vPortCancelThread( xTimerGetTimerDaemonTaskHandle() );
+#endif /* configUSE_TIMERS */
+
+    /* Restore original signal mask. */
+    (void)pthread_sigmask( SIG_SETMASK, &xSchedulerOriginalSignalMask,  NULL );
+
+    return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+struct itimerval itimer;
+struct sigaction sigtick;
+Thread_t *xCurrentThread;
+
+    /* Stop the timer and ignore any pending SIGALRMs that would end
+     * up running on the main thread when it is resumed. */
+    itimer.it_value.tv_sec = 0;
+    itimer.it_value.tv_usec = 0;
+
+    itimer.it_interval.tv_sec = 0;
+    itimer.it_interval.tv_usec = 0;
+    (void)setitimer( ITIMER_REAL, &itimer, NULL );
+
+    sigtick.sa_flags = 0;
+    sigtick.sa_handler = SIG_IGN;
+    sigemptyset( &sigtick.sa_mask );
+    sigaction( SIGALRM, &sigtick, NULL );
+
+    /* Signal the scheduler to exit its loop. */
+    xSchedulerEnd = pdTRUE;
+    (void)pthread_kill( hMainThread, SIG_RESUME );
+
+    xCurrentThread = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+    prvSuspendSelf(xCurrentThread);
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+    if ( uxCriticalNesting == 0 )
+    {
+        vPortDisableInterrupts();
+    }
+    uxCriticalNesting++;
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+    uxCriticalNesting--;
+
+    /* If we have reached 0 then re-enable the interrupts. */
+    if( uxCriticalNesting == 0 )
+    {
+        vPortEnableInterrupts();
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vPortYieldFromISR( void )
+{
+Thread_t *xThreadToSuspend;
+Thread_t *xThreadToResume;
+
+    xThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+
+    vTaskSwitchContext();
+
+    xThreadToResume = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+
+    prvSwitchThread( xThreadToResume, xThreadToSuspend );
+}
+/*-----------------------------------------------------------*/
+
+void vPortYield( void )
+{
+    vPortEnterCritical();
+
+    vPortYieldFromISR();
+
+    vPortExitCritical();
+}
+/*-----------------------------------------------------------*/
+
+void vPortDisableInterrupts( void )
+{
+    pthread_sigmask( SIG_BLOCK, &xAllSignals, NULL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnableInterrupts( void )
+{
+    pthread_sigmask( SIG_UNBLOCK, &xAllSignals, NULL );
+}
+/*-----------------------------------------------------------*/
+
+portBASE_TYPE xPortSetInterruptMask( void )
+{
+    /* Interrupts are always disabled inside ISRs (signals
+       handlers). */
+    return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+void vPortClearInterruptMask( portBASE_TYPE xMask )
+{
+}
+/*-----------------------------------------------------------*/
+
+static uint64_t prvGetTimeNs(void)
+{
+struct timespec t;
+
+    clock_gettime(CLOCK_MONOTONIC, &t);
+
+    return t.tv_sec * 1000000000ull + t.tv_nsec;
+}
+
+static uint64_t prvStartTimeNs;
+/* commented as part of the code below in vPortSystemTickHandler,
+ * to adjust timing according to full demo requirements */
+/* static uint64_t prvTickCount; */
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+void prvSetupTimerInterrupt( void )
+{
+struct itimerval itimer;
+int iRet;
+
+    /* Initialise the structure with the current timer information. */
+    iRet = getitimer( ITIMER_REAL, &itimer );
+    if ( iRet )
+    {
+        prvFatalError( "getitimer", errno );
+    }
+
+    /* Set the interval between timer events. */
+    itimer.it_interval.tv_sec = 0;
+    itimer.it_interval.tv_usec = portTICK_RATE_MICROSECONDS;
+
+    /* Set the current count-down. */
+    itimer.it_value.tv_sec = 0;
+    itimer.it_value.tv_usec = portTICK_RATE_MICROSECONDS;
+
+    /* Set-up the timer interrupt. */
+    iRet = setitimer( ITIMER_REAL, &itimer, NULL );
+    if ( iRet )
+    {
+        prvFatalError( "setitimer", errno );
+    }
+
+    prvStartTimeNs = prvGetTimeNs();
+}
+/*-----------------------------------------------------------*/
+
+static void vPortSystemTickHandler( int sig )
+{
+Thread_t *pxThreadToSuspend;
+Thread_t *pxThreadToResume;
+/* uint64_t xExpectedTicks; */
+
+    uxCriticalNesting++; /* Signals are blocked in this signal handler. */
+
+#if ( configUSE_PREEMPTION == 1 )
+    pxThreadToSuspend = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+#endif
+
+    /* Tick Increment, accounting for any lost signals or drift in
+     * the timer. */
+/*
+ *      Comment code to adjust timing according to full demo requirements
+ *      xExpectedTicks = (prvGetTimeNs() - prvStartTimeNs)
+ *        / (portTICK_RATE_MICROSECONDS * 1000);
+ * do { */
+        xTaskIncrementTick();
+/*        prvTickCount++;
+ *    } while (prvTickCount < xExpectedTicks);
+*/
+
+#if ( configUSE_PREEMPTION == 1 )
+    /* Select Next Task. */
+    vTaskSwitchContext();
+
+    pxThreadToResume = prvGetThreadFromTask( xTaskGetCurrentTaskHandle() );
+
+    prvSwitchThread(pxThreadToResume, pxThreadToSuspend);
+#endif
+
+    uxCriticalNesting--;
+}
+/*-----------------------------------------------------------*/
+
+void vPortThreadDying( void *pxTaskToDelete, volatile BaseType_t *pxPendYield )
+{
+Thread_t *pxThread = prvGetThreadFromTask( pxTaskToDelete );
+
+    pxThread->xDying = pdTRUE;
+}
+
+void vPortCancelThread( void *pxTaskToDelete )
+{
+Thread_t *pxThreadToCancel = prvGetThreadFromTask( pxTaskToDelete );
+
+    /*
+     * The thread has already been suspended so it can be safely cancelled.
+     */
+    pthread_cancel( pxThreadToCancel->pthread );
+    pthread_join( pxThreadToCancel->pthread, NULL );
+    event_delete( pxThreadToCancel->ev );
+}
+/*-----------------------------------------------------------*/
+
+static void *prvWaitForStart( void * pvParams )
+{
+Thread_t *pxThread = pvParams;
+
+    prvSuspendSelf(pxThread);
+
+    /* Resumed for the first time, unblocks all signals. */
+    uxCriticalNesting = 0;
+    vPortEnableInterrupts();
+
+    /* Call the task's entry point. */
+    pxThread->pxCode( pxThread->pvParams );
+
+    /* A function that implements a task must not exit or attempt to return to
+    * its caller as there is nothing to return to. If a task wants to exit it
+    * should instead call vTaskDelete( NULL ). Artificially force an assert()
+    * to be triggered if configASSERT() is defined, so application writers can
+        * catch the error. */
+    configASSERT( pdFALSE );
+
+    return NULL;
+}
+/*-----------------------------------------------------------*/
+
+static void prvSwitchThread( Thread_t *pxThreadToResume,
+                             Thread_t *pxThreadToSuspend )
+{
+BaseType_t uxSavedCriticalNesting;
+
+    if ( pxThreadToSuspend != pxThreadToResume )
+    {
+        /*
+         * Switch tasks.
+         *
+         * The critical section nesting is per-task, so save it on the
+         * stack of the current (suspending thread), restoring it when
+         * we switch back to this task.
+         */
+        uxSavedCriticalNesting = uxCriticalNesting;
+
+        prvResumeThread( pxThreadToResume );
+        if ( pxThreadToSuspend->xDying )
+        {
+            pthread_exit( NULL );
+        }
+        prvSuspendSelf( pxThreadToSuspend );
+
+        uxCriticalNesting = uxSavedCriticalNesting;
+    }
+}
+/*-----------------------------------------------------------*/
+
+static void prvSuspendSelf( Thread_t *thread )
+{
+    /*
+     * Suspend this thread by waiting for a pthread_cond_signal event.
+     *
+     * A suspended thread must not handle signals (interrupts) so
+     * all signals must be blocked by calling this from:
+     *
+     * - Inside a critical section (vPortEnterCritical() /
+     *   vPortExitCritical()).
+     *
+     * - From a signal handler that has all signals masked.
+     *
+     * - A thread with all signals blocked with pthread_sigmask().
+        */
+    event_wait(thread->ev);
+}
+
+/*-----------------------------------------------------------*/
+
+static void prvResumeThread( Thread_t *xThreadId )
+{
+    if ( pthread_self() != xThreadId->pthread )
+    {
+        event_signal(xThreadId->ev);
+    }
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetupSignalsAndSchedulerPolicy( void )
+{
+struct sigaction sigresume, sigtick;
+int iRet;
+
+    hMainThread = pthread_self();
+
+    /* Initialise common signal masks. */
+    sigemptyset( &xResumeSignals );
+    sigaddset( &xResumeSignals, SIG_RESUME );
+    sigfillset( &xAllSignals );
+    /* Don't block SIGINT so this can be used to break into GDB while
+     * in a critical section. */
+    sigdelset( &xAllSignals, SIGINT );
+
+    /*
+     * Block all signals in this thread so all new threads
+     * inherits this mask.
+     *
+     * When a thread is resumed for the first time, all signals
+     * will be unblocked.
+     */
+    (void)pthread_sigmask( SIG_SETMASK, &xAllSignals,
+                           *&xSchedulerOriginalSignalMask );
+
+    /* SIG_RESUME is only used with sigwait() so doesn't need a
+       handler. */
+    sigresume.sa_flags = 0;
+    sigresume.sa_handler = SIG_IGN;
+    sigfillset( &sigresume.sa_mask );
+
+    sigtick.sa_flags = 0;
+    sigtick.sa_handler = vPortSystemTickHandler;
+    sigfillset( &sigtick.sa_mask );
+
+    iRet = sigaction( SIG_RESUME, &sigresume, NULL );
+    if ( iRet )
+    {
+        prvFatalError( "sigaction", errno );
+    }
+
+    iRet = sigaction( SIGALRM, &sigtick, NULL );
+    if ( iRet )
+    {
+        prvFatalError( "sigaction", errno );
+    }
+}
+/*-----------------------------------------------------------*/
+
+unsigned long ulPortGetRunTime( void )
+{
+struct tms xTimes;
+
+    times( &xTimes );
+
+    return ( unsigned long ) xTimes.tms_utime;
+}
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/portmacro.h
new file mode 100644
index 0000000..3f96b40
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/portmacro.h
@@ -0,0 +1,134 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright 2020 Cambridge Consultants Ltd.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <limits.h>
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	unsigned long
+#define portBASE_TYPE	long
+#define portPOINTER_SIZE_TYPE intptr_t
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+typedef unsigned long TickType_t;
+#define portMAX_DELAY ( TickType_t ) ULONG_MAX
+
+#define portTICK_TYPE_IS_ATOMIC 1
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portHAS_STACK_OVERFLOW_CHECKING	( 1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portTICK_RATE_MICROSECONDS	( ( portTickType ) 1000000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+extern void vPortYield( void );
+
+#define portYIELD() vPortYield()
+
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) vPortYield()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortDisableInterrupts( void );
+extern void vPortEnableInterrupts( void );
+#define portSET_INTERRUPT_MASK()        ( vPortDisableInterrupts() )
+#define portCLEAR_INTERRUPT_MASK()      ( vPortEnableInterrupts() )
+
+extern portBASE_TYPE xPortSetInterruptMask( void );
+extern void vPortClearInterruptMask( portBASE_TYPE xMask );
+
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()		xPortSetInterruptMask()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask(x)
+#define portDISABLE_INTERRUPTS()				portSET_INTERRUPT_MASK()
+#define portENABLE_INTERRUPTS()					portCLEAR_INTERRUPT_MASK()
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+extern void vPortThreadDying( void *pxTaskToDelete, volatile BaseType_t *pxPendYield );
+extern void vPortCancelThread( void *pxTaskToDelete );
+#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortThreadDying( ( pvTaskToDelete ), ( pxPendYield ) )
+#define portCLEAN_UP_TCB( pxTCB )	vPortCancelThread( pxTCB )
+/*-----------------------------------------------------------*/
+
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/*
+ * Tasks run in their own pthreads and context switches between them
+ * are always a full memory barrier. ISRs are emulated as signals
+ * which also imply a full memory barrier.
+ *
+ * Thus, only a compilier barrier is needed to prevent the compiler
+ * reordering.
+ */
+#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
+
+extern unsigned long ulPortGetRunTime( void );
+#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() /* no-op */
+#define portGET_RUN_TIME_COUNTER_VALUE()         ulPortGetRunTime()
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c
new file mode 100644
index 0000000..896604a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/utils/wait_for_event.c
@@ -0,0 +1,76 @@
+#include <pthread.h>
+#include <stdlib.h>
+#include <errno.h>
+
+#include "wait_for_event.h"
+
+struct event
+{
+    pthread_mutex_t mutex;
+    pthread_cond_t cond;
+    bool event_triggered;
+};
+
+struct event * event_create()
+{
+    struct event * ev = malloc( sizeof( struct event ) );
+
+    ev->event_triggered = false;
+    pthread_mutex_init( &ev->mutex, NULL );
+    pthread_cond_init( &ev->cond, NULL );
+    return ev;
+}
+
+void event_delete( struct event * ev )
+{
+    pthread_mutex_destroy( &ev->mutex );
+    pthread_cond_destroy( &ev->cond );
+    free( ev );
+}
+
+bool event_wait( struct event * ev )
+{
+    pthread_mutex_lock( &ev->mutex );
+
+    while( ev->event_triggered == false )
+    {
+        pthread_cond_wait( &ev->cond, &ev->mutex );
+    }
+
+    ev->event_triggered = false;
+    pthread_mutex_unlock( &ev->mutex );
+    return true;
+}
+bool event_wait_timed( struct event * ev,
+                       time_t ms )
+{
+    struct timespec ts;
+    int ret = 0;
+
+    clock_gettime( CLOCK_REALTIME, &ts );
+    //ts.tv_sec += ms;
+    ts.tv_nsec += (ms * 1000000);
+    pthread_mutex_lock( &ev->mutex );
+
+    while( (ev->event_triggered == false) && (ret == 0) )
+    {
+        ret = pthread_cond_timedwait( &ev->cond, &ev->mutex, &ts );
+
+        if( ( ret == -1 ) && ( errno == ETIMEDOUT ) )
+        {
+            return false;
+        }
+    }
+
+    ev->event_triggered = false;
+    pthread_mutex_unlock( &ev->mutex );
+    return true;
+}
+
+void event_signal( struct event * ev )
+{
+    pthread_mutex_lock( &ev->mutex );
+    ev->event_triggered = true;
+    pthread_cond_signal( &ev->cond );
+    pthread_mutex_unlock( &ev->mutex );
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h
new file mode 100644
index 0000000..2693a0d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Posix/utils/wait_for_event.h
@@ -0,0 +1,18 @@
+#ifndef _WAIT_FOR_EVENT_H_
+#define _WAIT_FOR_EVENT_H_
+
+#include <stdbool.h>
+#include <time.h>
+
+struct event;
+
+struct event * event_create();
+void event_delete( struct event * );
+bool event_wait( struct event * ev );
+bool event_wait_timed( struct event * ev,
+                       time_t ms );
+void event_signal( struct event * ev );
+
+
+
+#endif /* ifndef _WAIT_FOR_EVENT_H_ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/README-for-info-on-official-MIT-license-port.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/README-for-info-on-official-MIT-license-port.txt
new file mode 100644
index 0000000..bc15d12
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/README-for-info-on-official-MIT-license-port.txt
@@ -0,0 +1,6 @@
+The official and MIT licensed FreeRTOS ports for RISC-V are located in the following directories:
+\FreeRTOS\Source\portable\GCC\RISC-V
+\FreeRTOS\Source\portable\IAR\RISC-V
+
+Also so https://www.FreeRTOS.org/Using-FreeRTOS-on-RISC-V.html
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/FreeRTOS-openocd.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/FreeRTOS-openocd.c
new file mode 100644
index 0000000..671c2de
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/FreeRTOS-openocd.c
@@ -0,0 +1,27 @@
+/*
+ * Since at least FreeRTOS V7.5.3 uxTopUsedPriority is no longer
+ * present in the kernel, so it has to be supplied by other means for
+ * OpenOCD's threads awareness.
+ *
+ * Add this file to your project, and, if you're using --gc-sections,
+ * ``--undefined=uxTopUsedPriority'' (or
+ * ``-Wl,--undefined=uxTopUsedPriority'' when using gcc for final
+ * linking) to your LDFLAGS; same with all the other symbols you need.
+ */
+
+#include "FreeRTOS.h"
+#include "esp_attr.h"
+#include "sdkconfig.h"
+
+#ifdef __GNUC__
+    #define USED    __attribute__( ( used ) )
+#else
+    #define USED
+#endif
+
+/* 
+ * This file is no longer needed as AFTER FreeRTOS V10.14.1 OpenOCD is fixed in the kernel.
+ * #ifdef CONFIG_ESP32_DEBUG_OCDAWARE
+ *   const int USED DRAM_ATTR uxTopUsedPriority = configMAX_PRIORITIES - 1;
+ * #endif 
+ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h
new file mode 100644
index 0000000..ce34b97
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h
@@ -0,0 +1,46 @@
+/*******************************************************************************
+ * // Copyright (c) 2003-2015 Cadence Design Systems, Inc.
+ * //
+ * // Permission is hereby granted, free of charge, to any person obtaining
+ * // a copy of this software and associated documentation files (the
+ * // "Software"), to deal in the Software without restriction, including
+ * // without limitation the rights to use, copy, modify, merge, publish,
+ * // distribute, sublicense, and/or sell copies of the Software, and to
+ * // permit persons to whom the Software is furnished to do so, subject to
+ * // the following conditions:
+ * //
+ * // The above copyright notice and this permission notice shall be included
+ * // in all copies or substantial portions of the Software.
+ * //
+ * // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ * --------------------------------------------------------------------------------
+ */
+
+/*
+ * This utility helps benchmarking interrupt latency and context switches.
+ * In order to enable it, set configBENCHMARK to 1 in FreeRTOSConfig.h.
+ * You will also need to download the FreeRTOS_trace patch that contains
+ * portbenchmark.c and the complete version of portbenchmark.h
+ */
+
+#ifndef PORTBENCHMARK_H
+#define PORTBENCHMARK_H
+
+#if configBENCHMARK
+    #error "You need to download the FreeRTOS_trace patch that overwrites this file"
+#endif
+
+#define portbenchmarkINTERRUPT_DISABLE()
+#define portbenchmarkINTERRUPT_RESTORE( newstate )
+#define portbenchmarkIntLatency()
+#define portbenchmarkIntWait()
+#define portbenchmarkReset()
+#define portbenchmarkPrint()
+
+#endif /* PORTBENCHMARK */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
new file mode 100644
index 0000000..03ab18e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
@@ -0,0 +1,502 @@
+/*
+ *  FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
+ *  All rights reserved
+ *
+ *  VISIT https://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+ *
+ ***************************************************************************
+ *                                                                       *
+ *    FreeRTOS provides completely free yet professionally developed,    *
+ *    robust, strictly quality controlled, supported, and cross          *
+ *    platform software that has become a de facto standard.             *
+ *                                                                       *
+ *    Help yourself get started quickly and support the FreeRTOS         *
+ *    project by purchasing a FreeRTOS tutorial book, reference          *
+ *    manual, or both from: https://www.FreeRTOS.org/Documentation       *
+ *                                                                       *
+ *    Thank you!                                                         *
+ *                                                                       *
+ ***************************************************************************
+ *
+ *  This file is part of the FreeRTOS distribution.
+ *
+ *  FreeRTOS is free software; you can redistribute it and/or modify it under
+ *  the terms of the GNU General Public License (version 2) as published by the
+ *  Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+ *
+ *  >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+ *  >>!   distribute a combined work that includes FreeRTOS without being   !<<
+ *  >>!   obliged to provide the source code for proprietary components     !<<
+ *  >>!   outside of the FreeRTOS kernel.                                   !<<
+ *
+ *  FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ *  WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ *  FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+ *  link: https://www.FreeRTOS.org/a00114.html
+ *
+ *
+ ***************************************************************************
+ *                                                                       *
+ *    Having a problem?  Start by reading the FAQ "My application does   *
+ *    not run, what could be wrong?"                                     *
+ *                                                                       *
+ *    https://www.FreeRTOS.org/FAQHelp.html                              *
+ *                                                                       *
+ ***************************************************************************
+ *
+ *  https://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ *  license and Real Time Engineers Ltd. contact details.
+ *
+ *  https://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ *  including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ *  compatible FAT file system, and our tiny thread aware UDP/IP stack.
+ *
+ *  https://www.highintegritysystems.com/openrtos/ - Real Time Engineers ltd
+ *  license FreeRTOS to High Integrity Systems to sell under the OpenRTOS brand.
+ *  Low cost OpenRTOS licenses offer ticketed support, indemnification
+ *  and middleware.
+ *
+ *  https://www.highintegritysystems.com/safertos/ - High Integrity Systems
+ *  also provide a safety engineered and independently SIL3 certified version
+ *  for use in safety and mission critical applications that require
+ *  provable dependability.
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+#ifndef __ASSEMBLER__
+
+    #include <stdint.h>
+
+    #include <xtensa/hal.h>
+    #include <xtensa/config/core.h>
+    #include <xtensa/config/system.h> /* required for XSHAL_CLIB */
+    #include <xtensa/xtruntime.h>
+    #include "esp_timer.h"            /* required for FreeRTOS run time stats */
+    #include "esp_system.h"
+
+
+    #include <esp_heap_caps.h>
+    #include "soc/soc_memory_layout.h"
+
+/*#include "xtensa_context.h" */
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+
+    #define portCHAR          int8_t
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          int32_t
+    #define portSHORT         int16_t
+    #define portSTACK_TYPE    uint8_t
+    #define portBASE_TYPE     int
+
+    typedef portSTACK_TYPE           StackType_t;
+    typedef portBASE_TYPE            BaseType_t;
+    typedef unsigned portBASE_TYPE   UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t             TickType_t;
+        #define portMAX_DELAY    ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t             TickType_t;
+        #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+    #endif
+/*-----------------------------------------------------------*/
+
+/* portbenchmark */
+    #include "portbenchmark.h"
+
+    #include "sdkconfig.h"
+    #include "esp_attr.h"
+
+/* "mux" data structure (spinlock) */
+    typedef struct
+    {
+        /* owner field values:
+         * 0                - Uninitialized (invalid)
+         * portMUX_FREE_VAL - Mux is free, can be locked by either CPU
+         * CORE_ID_PRO / CORE_ID_APP - Mux is locked to the particular core
+         *
+         * Any value other than portMUX_FREE_VAL, CORE_ID_PRO, CORE_ID_APP indicates corruption
+         */
+        uint32_t owner;
+
+        /* count field:
+         * If mux is unlocked, count should be zero.
+         * If mux is locked, count is non-zero & represents the number of recursive locks on the mux.
+         */
+        uint32_t count;
+        #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+            const char * lastLockedFn;
+            int lastLockedLine;
+        #endif
+    } portMUX_TYPE;
+
+    #define portMUX_FREE_VAL      0xB33FFFFF
+
+/* Special constants for vPortCPUAcquireMutexTimeout() */
+    #define portMUX_NO_TIMEOUT    ( -1 ) /* When passed for 'timeout_cycles', spin forever if necessary */
+    #define portMUX_TRY_LOCK      0      /* Try to acquire the spinlock a single time only */
+
+/* Keep this in sync with the portMUX_TYPE struct definition please. */
+    #ifndef CONFIG_FREERTOS_PORTMUX_DEBUG
+        #define portMUX_INITIALIZER_UNLOCKED \
+    {                                        \
+        .owner = portMUX_FREE_VAL,           \
+        .count = 0,                          \
+    }
+    #else
+        #define portMUX_INITIALIZER_UNLOCKED \
+    {                                        \
+        .owner = portMUX_FREE_VAL,           \
+        .count = 0,                          \
+        .lastLockedFn = "(never locked)",    \
+        .lastLockedLine = -1                 \
+    }
+    #endif /* ifndef CONFIG_FREERTOS_PORTMUX_DEBUG */
+
+
+    #define portASSERT_IF_IN_ISR()    vPortAssertIfInISR()
+    void vPortAssertIfInISR();
+
+    #define portCRITICAL_NESTING_IN_TCB    1
+
+/*
+ * Modifications to portENTER_CRITICAL.
+ *
+ * For an introduction, see "Critical Sections & Disabling Interrupts" in docs/api-guides/freertos-smp.rst
+ *
+ * The original portENTER_CRITICAL only disabled the ISRs. This is enough for single-CPU operation: by
+ * disabling the interrupts, there is no task switch so no other tasks can meddle in the data, and because
+ * interrupts are disabled, ISRs can't corrupt data structures either.
+ *
+ * For multiprocessing, things get a bit more hairy. First of all, disabling the interrupts doesn't stop
+ * the tasks or ISRs on the other processors meddling with our CPU. For tasks, this is solved by adding
+ * a spinlock to the portENTER_CRITICAL macro. A task running on the other CPU accessing the same data will
+ * spinlock in the portENTER_CRITICAL code until the first CPU is done.
+ *
+ * For ISRs, we now also need muxes: while portENTER_CRITICAL disabling interrupts will stop ISRs on the same
+ * CPU from meddling with the data, it does not stop interrupts on the other cores from interfering with the
+ * data. For this, we also use a spinlock in the routines called by the ISR, but these spinlocks
+ * do not disable the interrupts (because they already are).
+ *
+ * This all assumes that interrupts are either entirely disabled or enabled. Interrupt priority levels
+ * will break this scheme.
+ *
+ * Remark: For the ESP32, portENTER_CRITICAL and portENTER_CRITICAL_ISR both alias vTaskEnterCritical, meaning
+ * that either function can be called both from ISR as well as task context. This is not standard FreeRTOS
+ * behaviour; please keep this in mind if you need any compatibility with other FreeRTOS implementations.
+ */
+    void vPortCPUInitializeMutex( portMUX_TYPE * mux );
+    #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+        #error CONFIG_FREERTOS_PORTMUX_DEBUG not supported in Amazon FreeRTOS
+    #endif
+
+    void vTaskExitCritical();
+    void vTaskEnterCritical();
+    static inline void vPortConsumeSpinlockArg( int unused,
+                                                ... )
+    {
+    }
+
+/** @brief Acquire a portmux spinlock with a timeout
+ *
+ * @param mux Pointer to portmux to acquire.
+ * @param timeout_cycles Timeout to spin, in CPU cycles. Pass portMUX_NO_TIMEOUT to wait forever,
+ * portMUX_TRY_LOCK to try a single time to acquire the lock.
+ *
+ * @return true if mutex is successfully acquired, false on timeout.
+ */
+    bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux,
+                                      int timeout_cycles );
+    void vPortCPUReleaseMutex( portMUX_TYPE * mux );
+
+    #define portENTER_CRITICAL( ... )        do { vTaskEnterCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 )
+    #define portEXIT_CRITICAL( ... )         do { vTaskExitCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 )
+
+
+    #define portENTER_CRITICAL_ISR( mux )    vPortCPUAcquireMutexTimeout( mux, portMUX_NO_TIMEOUT )
+    #define portEXIT_CRITICAL_ISR( mux )     vPortCPUReleaseMutex( mux )
+
+    #define portENTER_CRITICAL_SAFE( mux ) \
+    do {                                   \
+        if( xPortInIsrContext() ) {        \
+            portENTER_CRITICAL_ISR( mux ); \
+        }                                  \
+        else {                             \
+            portENTER_CRITICAL( mux );     \
+        }                                  \
+    } while( 0 )
+
+    #define portEXIT_CRITICAL_SAFE( mux ) \
+    do {                                  \
+        if( xPortInIsrContext() ) {       \
+            portEXIT_CRITICAL_ISR( mux ); \
+        }                                 \
+        else {                            \
+            portEXIT_CRITICAL( mux );     \
+        }                                 \
+    } while( 0 )
+
+
+/* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */
+/* These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. */
+/* */
+/* Only applies to one CPU. See notes above & below for reasons not to use these. */
+    #define portDISABLE_INTERRUPTS()    do { XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); portbenchmarkINTERRUPT_DISABLE(); } while( 0 )
+    #define portENABLE_INTERRUPTS()     do { portbenchmarkINTERRUPT_RESTORE( 0 ); XTOS_SET_INTLEVEL( 0 ); } while( 0 )
+
+/* Cleaner solution allows nested interrupts disabling and restoring via local registers or stack. */
+/* They can be called from interrupts too. */
+/* WARNING: Only applies to current CPU. See notes above. */
+    static inline unsigned portENTER_CRITICAL_NESTED()
+    {
+        unsigned state = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL );
+
+        portbenchmarkINTERRUPT_DISABLE();
+        return state;
+    }
+    #define portEXIT_CRITICAL_NESTED( state )             do { portbenchmarkINTERRUPT_RESTORE( state ); XTOS_RESTORE_JUST_INTLEVEL( state ); } while( 0 )
+
+/* These FreeRTOS versions are similar to the nested versions above */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()             portENTER_CRITICAL_NESTED()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( state )    portEXIT_CRITICAL_NESTED( state )
+
+/*Because the ROM routines don't necessarily handle a stack in external RAM correctly, we force */
+/*the stack memory to always be internal. */
+    #define pvPortMallocTcbMem( size )        heap_caps_malloc( size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT )
+    #define pvPortMallocStackMem( size )      heap_caps_malloc( size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT )
+
+/*xTaskCreateStatic uses these functions to check incoming memory. */
+    #define portVALID_TCB_MEM( ptr )          ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) )
+    #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+        #define portVALID_STACK_MEM( ptr )    esp_ptr_byte_accessible( ptr )
+    #else
+        #define portVALID_STACK_MEM( ptr )    ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) )
+    #endif
+
+/*
+ * Wrapper for the Xtensa compare-and-set instruction. This subroutine will atomically compare
+ * *addr to 'compare'. If *addr == compare, *addr is set to *set. *set is updated with the previous
+ * value of *addr (either 'compare' or some other value.)
+ *
+ * Warning: From the ISA docs: in some (unspecified) cases, the s32c1i instruction may return the
+ * *bitwise inverse* of the old mem if the mem wasn't written. This doesn't seem to happen on the
+ * ESP32 (portMUX assertions would fail).
+ */
+        static inline void uxPortCompareSet( volatile uint32_t * addr,
+                                             uint32_t compare,
+                                             uint32_t * set )
+        {
+            #if ( XCHAL_HAVE_S32C1I > 0 )
+                __asm__ __volatile__ (
+                    "WSR 	    %2,SCOMPARE1 \n"
+                    "S32C1I     %0, %1, 0	 \n"
+                    : "=r" ( *set )
+                    : "r" ( addr ), "r" ( compare ), "0" ( *set )
+                    );
+            #else
+                /* No S32C1I, so do this by disabling and re-enabling interrupts (slower) */
+                uint32_t intlevel, old_value;
+                __asm__ __volatile__ ( "rsil %0, " XTSTR( XCHAL_EXCM_LEVEL ) "\n"
+                                       : "=r" ( intlevel ) );
+
+                old_value = *addr;
+
+                if( old_value == compare )
+                {
+                    *addr = *set;
+                }
+
+                __asm__ __volatile__ ( "memw \n"
+                                       "wsr %0, ps\n"
+                                       : : "r" ( intlevel ) );
+
+                *set = old_value;
+            #endif /* if ( XCHAL_HAVE_S32C1I > 0 ) */
+        }
+
+        void uxPortCompareSetExtram( volatile uint32_t * addr,
+                                     uint32_t compare,
+                                     uint32_t * set );
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    4
+    #define portNOP()    XT_NOP()
+/*-----------------------------------------------------------*/
+
+/* Fine resolution time */
+    #define portGET_RUN_TIME_COUNTER_VALUE()    xthal_get_ccount()
+/*ccount or esp_timer are initialized elsewhere */
+    #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
+
+    #ifdef CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER
+/* Coarse resolution time (us) */
+        #define portALT_GET_RUN_TIME_COUNTER_VALUE( x )    x = ( uint32_t ) esp_timer_get_time()
+    #endif
+
+
+
+/* Kernel utilities. */
+    void vPortYield( void );
+    void _frxt_setup_switch( void );
+    #define portYIELD()             vPortYield()
+    #define portYIELD_FROM_ISR()    { traceISR_EXIT_TO_SCHEDULER(); _frxt_setup_switch(); }
+
+    static inline uint32_t xPortGetCoreID();
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+/* When coprocessors are defined, we to maintain a pointer to coprocessors area. */
+/* We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold: */
+/* MPU wrappers, coprocessor area pointer, trace code structure, and more if needed. */
+/* The field is normally used for memory protection. FreeRTOS should create another general purpose field. */
+    typedef struct
+    {
+        #if XCHAL_CP_NUM > 0
+            volatile StackType_t * coproc_area; /* Pointer to coprocessor save area; MUST BE FIRST */
+        #endif
+
+        #if portUSING_MPU_WRAPPERS
+            /* Define here mpu_settings, which is port dependent */
+            int mpu_setting; /* Just a dummy example here; MPU not ported to Xtensa yet */
+        #endif
+
+        #if configUSE_TRACE_FACILITY_2
+            struct
+            {
+                /* Cf. porttraceStamp() */
+                int taskstamp;      /* Stamp from inside task to see where we are */
+                int taskstampcount; /* A counter usually incremented when we restart the task's loop */
+            } porttrace;
+        #endif
+    } xMPU_SETTINGS;
+
+/* Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS) */
+    #if ( XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2 ) && !portUSING_MPU_WRAPPERS /* If MPU wrappers not used, we still need to allocate coproc area */
+        #undef portUSING_MPU_WRAPPERS
+        #define portUSING_MPU_WRAPPERS    1                                           /* Enable it to allocate coproc area */
+        #define MPU_WRAPPERS_H                                                        /* Override mpu_wrapper.h to disable unwanted code */
+        #define PRIVILEGED_FUNCTION
+        #define PRIVILEGED_DATA
+    #endif
+
+    bool vApplicationSleep( TickType_t xExpectedIdleTime );
+
+    #define portSUPPRESS_TICKS_AND_SLEEP( idleTime )    vApplicationSleep( idleTime )
+
+
+
+    void _xt_coproc_release( volatile void * coproc_sa_base );
+
+
+/*
+ * Map to the memory management routines required for the port.
+ *
+ * Note that libc standard malloc/free are also available for
+ * non-FreeRTOS-specific code, and behave the same as
+ * pvPortMalloc()/vPortFree().
+ */
+    #define pvPortMalloc                       heap_caps_malloc_default
+    #define vPortFree                          heap_caps_free
+    #define xPortGetFreeHeapSize               esp_get_free_heap_size
+    #define xPortGetMinimumEverFreeHeapSize    esp_get_minimum_free_heap_size
+
+
+/*
+ * Callback to set a watchpoint on the end of the stack. Called every context switch to change the stack
+ * watchpoint around.
+ */
+    void vPortSetStackWatchpoint( void * pxStackStart );
+
+/*
+ * Returns true if the current core is in ISR context; low prio ISR, med prio ISR or timer tick ISR. High prio ISRs
+ * aren't detected here, but they normally cannot call C code, so that should not be an issue anyway.
+ */
+    BaseType_t xPortInIsrContext();
+
+/*
+ * This function will be called in High prio ISRs. Returns true if the current core was in ISR context
+ * before calling into high prio ISR context.
+ */
+    BaseType_t xPortInterruptedFromISRContext();
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+    #if ( portUSING_MPU_WRAPPERS == 1 )
+        struct xMEMORY_REGION;
+        void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                        const struct xMEMORY_REGION * const xRegions,
+                                        StackType_t * pxBottomOfStack,
+                                        uint32_t usStackDepth ) PRIVILEGED_FUNCTION;
+        void vPortReleaseTaskMPUSettings( xMPU_SETTINGS * xMPUSettings );
+    #endif
+
+/* Multi-core: get current core ID */
+    static inline uint32_t IRAM_ATTR xPortGetCoreID()
+    {
+        int id;
+
+        asm (
+            "rsr.prid %0\n"
+            " extui %0,%0,13,1"
+            : "=r" ( id ) );
+        return id;
+    }
+
+/* Get tick rate per second */
+    uint32_t xPortGetTickRateHz( void );
+
+/* porttrace */
+    #if configUSE_TRACE_FACILITY_2
+        #include "porttrace.h"
+    #endif
+
+/* configASSERT_2 if requested */
+    #if configASSERT_2
+        #include <stdio.h>
+        void exit( int );
+        #define configASSERT( x )    if( !( x ) ) { porttracePrint( -1 ); printf( "\nAssertion failed in %s:%d\n", __FILE__, __LINE__ ); exit( -1 ); }
+    #endif
+
+#endif // __ASSEMBLER__
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h
new file mode 100644
index 0000000..f91dab1
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h
@@ -0,0 +1,132 @@
+/*******************************************************************************
+ * Copyright (c) 2006-2015 Cadence Design Systems Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+*  Xtensa-specific API for RTOS ports.
+******************************************************************************/
+
+#ifndef __XTENSA_API_H__
+#define __XTENSA_API_H__
+
+#include <xtensa/hal.h>
+
+#include "xtensa_context.h"
+
+
+/* Typedef for C-callable interrupt handler function */
+typedef void (* xt_handler)( void * );
+
+/* Typedef for C-callable exception handler function */
+typedef void (* xt_exc_handler)( XtExcFrame * );
+
+
+/*
+ * -------------------------------------------------------------------------------
+ * Call this function to set a handler for the specified exception. The handler
+ * will be installed on the core that calls this function.
+ *
+ *  n        - Exception number (type)
+ *  f        - Handler function address, NULL to uninstall handler.
+ *
+ * The handler will be passed a pointer to the exception frame, which is created
+ * on the stack of the thread that caused the exception.
+ *
+ * If the handler returns, the thread context will be restored and the faulting
+ * instruction will be retried. Any values in the exception frame that are
+ * modified by the handler will be restored as part of the context. For details
+ * of the exception frame structure see xtensa_context.h.
+ * -------------------------------------------------------------------------------
+ */
+extern xt_exc_handler xt_set_exception_handler( int n,
+                                                xt_exc_handler f );
+
+
+/*
+ * -------------------------------------------------------------------------------
+ * Call this function to set a handler for the specified interrupt. The handler
+ * will be installed on the core that calls this function.
+ *
+ *  n        - Interrupt number.
+ *  f        - Handler function address, NULL to uninstall handler.
+ *  arg      - Argument to be passed to handler.
+ * -------------------------------------------------------------------------------
+ */
+extern xt_handler xt_set_interrupt_handler( int n,
+                                            xt_handler f,
+                                            void * arg );
+
+
+/*
+ * -------------------------------------------------------------------------------
+ * Call this function to enable the specified interrupts on the core that runs
+ * this code.
+ *
+ *  mask     - Bit mask of interrupts to be enabled.
+ * -------------------------------------------------------------------------------
+ */
+extern void xt_ints_on( unsigned int mask );
+
+
+/*
+ * -------------------------------------------------------------------------------
+ * Call this function to disable the specified interrupts on the core that runs
+ * this code.
+ *
+ *  mask     - Bit mask of interrupts to be disabled.
+ * -------------------------------------------------------------------------------
+ */
+extern void xt_ints_off( unsigned int mask );
+
+
+/*
+ * -------------------------------------------------------------------------------
+ * Call this function to set the specified (s/w) interrupt.
+ * -------------------------------------------------------------------------------
+ */
+static inline void xt_set_intset( unsigned int arg )
+{
+    xthal_set_intset( arg );
+}
+
+
+/*
+ * -------------------------------------------------------------------------------
+ * Call this function to clear the specified (s/w or edge-triggered)
+ * interrupt.
+ * -------------------------------------------------------------------------------
+ */
+static inline void xt_set_intclear( unsigned int arg )
+{
+    xthal_set_intclear( arg );
+}
+
+/*
+ * -------------------------------------------------------------------------------
+ * Call this function to get handler's argument for the specified interrupt.
+ *
+ *  n        - Interrupt number.
+ * -------------------------------------------------------------------------------
+ */
+extern void * xt_get_interrupt_handler_arg( int n );
+
+#endif /* __XTENSA_API_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h
new file mode 100644
index 0000000..4ac32d7
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h
@@ -0,0 +1,145 @@
+/*******************************************************************************
+*  // Copyright (c) 2003-2015 Cadence Design Systems, Inc.
+*  //
+*  // Permission is hereby granted, free of charge, to any person obtaining
+*  // a copy of this software and associated documentation files (the
+*  // "Software"), to deal in the Software without restriction, including
+*  // without limitation the rights to use, copy, modify, merge, publish,
+*  // distribute, sublicense, and/or sell copies of the Software, and to
+*  // permit persons to whom the Software is furnished to do so, subject to
+*  // the following conditions:
+*  //
+*  // The above copyright notice and this permission notice shall be included
+*  // in all copies or substantial portions of the Software.
+*  //
+*  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+*  // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+*  // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+*  // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+*  // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+*  // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+*  // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*  --------------------------------------------------------------------------------
+*
+*  Configuration-specific information for Xtensa build. This file must be
+*  included in FreeRTOSConfig.h to properly set up the config-dependent
+*  parameters correctly.
+*
+*  NOTE: To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must
+*  be defined to be > 0 somewhere above or on the command line.
+*
+*******************************************************************************/
+
+#ifndef XTENSA_CONFIG_H
+    #define XTENSA_CONFIG_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+    #include <xtensa/hal.h>
+    #include <xtensa/config/core.h>
+    #include <xtensa/config/system.h> /* required for XSHAL_CLIB */
+
+    #include "xtensa_context.h"
+
+
+/*-----------------------------------------------------------------------------
+ *                                 STACK REQUIREMENTS
+ *
+ * This section defines the minimum stack size, and the extra space required to
+ * be allocated for saving coprocessor state and/or C library state information
+ * (if thread safety is enabled for the C library). The sizes are in bytes.
+ *
+ * Stack sizes for individual tasks should be derived from these minima based on
+ * the maximum call depth of the task and the maximum level of interrupt nesting.
+ * A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
+ * on the requirement for a task that calls nothing else but can be interrupted.
+ * This assumes that interrupt handlers do not call more than a few levels deep.
+ * If this is not true, i.e. one or more interrupt handlers make deep calls then
+ * the minimum must be increased.
+ *
+ * If the Xtensa processor configuration includes coprocessors, then space is
+ * allocated to save the coprocessor state on the stack.
+ *
+ * If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
+ * is defined) then space is allocated to save the C library context in the TCB.
+ *
+ * Allocating insufficient stack space is a common source of hard-to-find errors.
+ * During development, it is best to enable the FreeRTOS stack checking features.
+ *
+ * Usage:
+ *
+ * XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
+ *                            use of the C library. This will require extra stack
+ *                            space to be allocated for tasks that use the C library
+ *                            reentrant functions. See below for more information.
+ *
+ * NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
+ * support thread safety. Check your core configuration to see which C library
+ * was chosen for your system.
+ *
+ * XT_STACK_MIN_SIZE       -- The minimum stack size for any task. It is recommended
+ *                            that you do not use a stack smaller than this for any
+ *                            task. In case you want to use stacks smaller than this
+ *                            size, you must verify that the smaller size(s) will work
+ *                            under all operating conditions.
+ *
+ * XT_STACK_EXTRA          -- The amount of extra stack space to allocate for a task
+ *                            that does not make C library reentrant calls. Add this
+ *                            to the amount of stack space required by the task itself.
+ *
+ * XT_STACK_EXTRA_CLIB     -- The amount of space to allocate for C library state.
+ *
+ *  -----------------------------------------------------------------------------*/
+
+/* Extra space required for interrupt/exception hooks. */
+    #ifdef XT_INTEXC_HOOKS
+        #ifdef __XTENSA_CALL0_ABI__
+            #define STK_INTEXC_EXTRA     0x200
+        #else
+            #define STK_INTEXC_EXTRA     0x180
+        #endif
+    #else
+        #define STK_INTEXC_EXTRA         0
+    #endif
+
+    #define XT_CLIB_CONTEXT_AREA_SIZE    0
+
+/*------------------------------------------------------------------------------
+ *  Extra size -- interrupt frame plus coprocessor save area plus hook space.
+ *  NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
+ *  ------------------------------------------------------------------------------*/
+    #ifdef __XTENSA_CALL0_ABI__
+        #define XT_XTRA_SIZE    ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE )
+    #else
+        #define XT_XTRA_SIZE    ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE )
+    #endif
+
+/*------------------------------------------------------------------------------
+ *  Space allocated for user code -- function calls and local variables.
+ *  NOTE: This number can be adjusted to suit your needs. You must verify that the
+ *  amount of space you reserve is adequate for the worst-case conditions in your
+ *  application.
+ *  NOTE: The windowed ABI requires more stack, since space has to be reserved
+ *  for spilling register windows.
+ *  ------------------------------------------------------------------------------*/
+    #ifdef __XTENSA_CALL0_ABI__
+        #define XT_USER_SIZE    0x200
+    #else
+        #define XT_USER_SIZE    0x400
+    #endif
+
+/* Minimum recommended stack size. */
+    #define XT_STACK_MIN_SIZE      ( ( XT_XTRA_SIZE + XT_USER_SIZE ) / sizeof( unsigned char ) )
+
+/* OS overhead with and without C library thread context. */
+    #define XT_STACK_EXTRA         ( XT_XTRA_SIZE )
+    #define XT_STACK_EXTRA_CLIB    ( XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE )
+
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* XTENSA_CONFIG_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h
new file mode 100644
index 0000000..5a76201
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h
@@ -0,0 +1,378 @@
+/*******************************************************************************
+Copyright (c) 2006-2015 Cadence Design Systems Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be included
+in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+--------------------------------------------------------------------------------
+
+        XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
+
+This header contains definitions and macros for use primarily by Xtensa
+RTOS assembly coded source files. It includes and uses the Xtensa hardware
+abstraction layer (HAL) to deal with config specifics. It may also be
+included in C source files.
+
+!! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !!
+
+NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
+
+*******************************************************************************/
+
+#ifndef XTENSA_CONTEXT_H
+#define XTENSA_CONTEXT_H
+
+#ifdef __ASSEMBLER__
+#include    <xtensa/coreasm.h>
+#endif
+
+#include    <xtensa/config/tie.h>
+#include    <xtensa/corebits.h>
+#include    <xtensa/config/system.h>
+#include <xtensa/xtruntime-frames.h>
+
+
+/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
+#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
+
+
+/*
+-------------------------------------------------------------------------------
+  Macros that help define structures for both C and assembler.
+-------------------------------------------------------------------------------
+*/
+
+#ifdef STRUCT_BEGIN
+#undef STRUCT_BEGIN
+#undef STRUCT_FIELD
+#undef STRUCT_AFIELD
+#undef STRUCT_END
+#endif
+
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
+
+#define STRUCT_BEGIN            .pushsection .text; .struct 0
+#define STRUCT_FIELD(ctype,size,asname,name)    asname: .space  size
+#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space  (size)*(n)
+#define STRUCT_END(sname)       sname##Size:; .popsection
+
+#else
+
+#define STRUCT_BEGIN            typedef struct {
+#define STRUCT_FIELD(ctype,size,asname,name)    ctype   name;
+#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype   name[n];
+#define STRUCT_END(sname)       } sname;
+
+#endif //_ASMLANGUAGE || __ASSEMBLER__
+
+
+/*
+-------------------------------------------------------------------------------
+  INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
+
+  A stack frame of this structure is allocated for any interrupt or exception.
+  It goes on the current stack. If the RTOS has a system stack for handling 
+  interrupts, every thread stack must allow space for just one interrupt stack 
+  frame, then nested interrupt stack frames go on the system stack.
+
+  The frame includes basic registers (explicit) and "extra" registers introduced 
+  by user TIE or the use of the MAC16 option in the user's Xtensa config.
+  The frame size is minimized by omitting regs not applicable to user's config.
+
+  For Windowed ABI, this stack frame includes the interruptee's base save area,
+  another base save area to manage gcc nested functions, and a little temporary 
+  space to help manage the spilling of the register windows.
+-------------------------------------------------------------------------------
+*/
+
+STRUCT_BEGIN
+STRUCT_FIELD (long, 4, XT_STK_EXIT,     exit) /* exit point for dispatch */
+STRUCT_FIELD (long, 4, XT_STK_PC,       pc)   /* return PC */
+STRUCT_FIELD (long, 4, XT_STK_PS,       ps)   /* return PS */
+STRUCT_FIELD (long, 4, XT_STK_A0,       a0)
+STRUCT_FIELD (long, 4, XT_STK_A1,       a1)   /* stack pointer before interrupt */
+STRUCT_FIELD (long, 4, XT_STK_A2,       a2)
+STRUCT_FIELD (long, 4, XT_STK_A3,       a3)
+STRUCT_FIELD (long, 4, XT_STK_A4,       a4)
+STRUCT_FIELD (long, 4, XT_STK_A5,       a5)
+STRUCT_FIELD (long, 4, XT_STK_A6,       a6)
+STRUCT_FIELD (long, 4, XT_STK_A7,       a7)
+STRUCT_FIELD (long, 4, XT_STK_A8,       a8)
+STRUCT_FIELD (long, 4, XT_STK_A9,       a9)
+STRUCT_FIELD (long, 4, XT_STK_A10,      a10)
+STRUCT_FIELD (long, 4, XT_STK_A11,      a11)
+STRUCT_FIELD (long, 4, XT_STK_A12,      a12)
+STRUCT_FIELD (long, 4, XT_STK_A13,      a13)
+STRUCT_FIELD (long, 4, XT_STK_A14,      a14)
+STRUCT_FIELD (long, 4, XT_STK_A15,      a15)
+STRUCT_FIELD (long, 4, XT_STK_SAR,      sar)
+STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
+STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
+#if XCHAL_HAVE_LOOPS
+STRUCT_FIELD (long, 4, XT_STK_LBEG,   lbeg)
+STRUCT_FIELD (long, 4, XT_STK_LEND,   lend)
+STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
+#endif
+#ifndef __XTENSA_CALL0_ABI__
+/* Temporary space for saving stuff during window spill */
+STRUCT_FIELD (long, 4, XT_STK_TMP0,   tmp0)
+STRUCT_FIELD (long, 4, XT_STK_TMP1,   tmp1)
+STRUCT_FIELD (long, 4, XT_STK_TMP2,   tmp2)
+#endif
+#ifdef XT_USE_SWPRI
+/* Storage for virtual priority mask */
+STRUCT_FIELD (long, 4, XT_STK_VPRI,   vpri)
+#endif
+#ifdef XT_USE_OVLY
+/* Storage for overlay state */
+STRUCT_FIELD (long, 4, XT_STK_OVLY,   ovly)
+#endif
+STRUCT_END(XtExcFrame)
+
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
+#define XT_STK_NEXT1      XtExcFrameSize
+#else
+#define XT_STK_NEXT1      sizeof(XtExcFrame)
+#endif
+
+/* Allocate extra storage if needed */
+#if XCHAL_EXTRA_SA_SIZE != 0
+
+#if XCHAL_EXTRA_SA_ALIGN <= 16
+#define XT_STK_EXTRA            ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
+#else
+/* If need more alignment than stack, add space for dynamic alignment */
+#define XT_STK_EXTRA            (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
+#endif
+#define XT_STK_NEXT2            (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
+
+#else
+
+#define XT_STK_NEXT2            XT_STK_NEXT1   
+
+#endif
+
+/*
+-------------------------------------------------------------------------------
+  This is the frame size. Add space for 4 registers (interruptee's base save
+  area) and some space for gcc nested functions if any.
+-------------------------------------------------------------------------------
+*/
+#define XT_STK_FRMSZ            (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
+
+
+/*
+-------------------------------------------------------------------------------
+  SOLICITED STACK FRAME FOR A THREAD
+
+  A stack frame of this structure is allocated whenever a thread enters the 
+  RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
+  It goes on the current thread's stack.
+
+  The solicited frame only includes registers that are required to be preserved
+  by the callee according to the compiler's ABI conventions, some space to save 
+  the return address for returning to the caller, and the caller's PS register.
+
+  For Windowed ABI, this stack frame includes the caller's base save area.
+
+  Note on XT_SOL_EXIT field:
+      It is necessary to distinguish a solicited from an interrupt stack frame.
+      This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
+      always at the same offset (0). It can be written with a code (usually 0) 
+      to distinguish a solicted frame from an interrupt frame. An RTOS port may
+      opt to ignore this field if it has another way of distinguishing frames.
+-------------------------------------------------------------------------------
+*/
+
+STRUCT_BEGIN
+#ifdef __XTENSA_CALL0_ABI__
+STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
+STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
+STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
+STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
+STRUCT_FIELD (long, 4, XT_SOL_A12,  a12)    /* should be on 16-byte alignment */
+STRUCT_FIELD (long, 4, XT_SOL_A13,  a13)
+STRUCT_FIELD (long, 4, XT_SOL_A14,  a14)
+STRUCT_FIELD (long, 4, XT_SOL_A15,  a15)
+#else
+STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
+STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
+STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
+STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
+STRUCT_FIELD (long, 4, XT_SOL_A0,   a0)    /* should be on 16-byte alignment */
+STRUCT_FIELD (long, 4, XT_SOL_A1,   a1)
+STRUCT_FIELD (long, 4, XT_SOL_A2,   a2)
+STRUCT_FIELD (long, 4, XT_SOL_A3,   a3)
+#endif
+STRUCT_END(XtSolFrame)
+
+/* Size of solicited stack frame */
+#define XT_SOL_FRMSZ            ALIGNUP(0x10, XtSolFrameSize)
+
+
+/*
+-------------------------------------------------------------------------------
+  CO-PROCESSOR STATE SAVE AREA FOR A THREAD
+
+  The RTOS must provide an area per thread to save the state of co-processors
+  when that thread does not have control. Co-processors are context-switched
+  lazily (on demand) only when a new thread uses a co-processor instruction,
+  otherwise a thread retains ownership of the co-processor even when it loses
+  control of the processor. An Xtensa co-processor exception is triggered when
+  any co-processor instruction is executed by a thread that is not the owner,
+  and the context switch of that co-processor is then peformed by the handler.
+  Ownership represents which thread's state is currently in the co-processor.
+
+  Co-processors may not be used by interrupt or exception handlers. If an 
+  co-processor instruction is executed by an interrupt or exception handler,
+  the co-processor exception handler will trigger a kernel panic and freeze.
+  This restriction is introduced to reduce the overhead of saving and restoring
+  co-processor state (which can be quite large) and in particular remove that
+  overhead from interrupt handlers.
+
+  The co-processor state save area may be in any convenient per-thread location
+  such as in the thread control block or above the thread stack area. It need
+  not be in the interrupt stack frame since interrupts don't use co-processors.
+
+  Along with the save area for each co-processor, two bitmasks with flags per 
+  co-processor (laid out as in the CPENABLE reg) help manage context-switching
+  co-processors as efficiently as possible:
+
+  XT_CPENABLE
+    The contents of a non-running thread's CPENABLE register.
+    It represents the co-processors owned (and whose state is still needed)
+    by the thread. When a thread is preempted, its CPENABLE is saved here.
+    When a thread solicits a context-swtich, its CPENABLE is cleared - the
+    compiler has saved the (caller-saved) co-proc state if it needs to.
+    When a non-running thread loses ownership of a CP, its bit is cleared.
+    When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
+    Avoids co-processor exceptions when no change of ownership is needed.
+
+  XT_CPSTORED
+    A bitmask with the same layout as CPENABLE, a bit per co-processor.
+    Indicates whether the state of each co-processor is saved in the state 
+    save area. When a thread enters the kernel, only the state of co-procs
+    still enabled in CPENABLE is saved. When the co-processor exception 
+    handler assigns ownership of a co-processor to a thread, it restores 
+    the saved state only if this bit is set, and clears this bit.
+
+  XT_CP_CS_ST
+    A bitmask with the same layout as CPENABLE, a bit per co-processor.
+    Indicates whether callee-saved state is saved in the state save area.
+    Callee-saved state is saved by itself on a solicited context switch,
+    and restored when needed by the coprocessor exception handler.
+    Unsolicited switches will cause the entire coprocessor to be saved
+    when necessary.
+
+  XT_CP_ASA
+    Pointer to the aligned save area.  Allows it to be aligned more than
+    the overall save area (which might only be stack-aligned or TCB-aligned).
+    Especially relevant for Xtensa cores configured with a very large data
+    path that requires alignment greater than 16 bytes (ABI stack alignment).
+-------------------------------------------------------------------------------
+*/
+
+#if XCHAL_CP_NUM > 0
+
+/*  Offsets of each coprocessor save area within the 'aligned save area':  */
+#define XT_CP0_SA   0
+#define XT_CP1_SA   ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
+#define XT_CP2_SA   ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
+#define XT_CP3_SA   ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
+#define XT_CP4_SA   ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
+#define XT_CP5_SA   ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
+#define XT_CP6_SA   ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
+#define XT_CP7_SA   ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
+#define XT_CP_SA_SIZE   ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
+
+/*  Offsets within the overall save area:  */
+#define XT_CPENABLE 0   /* (2 bytes) coprocessors active for this thread */
+#define XT_CPSTORED 2   /* (2 bytes) coprocessors saved for this thread */
+#define XT_CP_CS_ST 4   /* (2 bytes) coprocessor callee-saved regs stored for this thread */
+#define XT_CP_ASA   8   /* (4 bytes) ptr to aligned save area */
+/*  Overall size allows for dynamic alignment:  */
+#define XT_CP_SIZE  (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
+#else
+#define XT_CP_SIZE  0
+#endif
+
+
+/*
+ Macro to get the current core ID. Only uses the reg given as an argument.
+ Reading PRID on the ESP32 gives us 0xCDCD on the PRO processor (0)
+ and 0xABAB on the APP CPU (1). We can distinguish between the two by checking
+ bit 13: it's 1 on the APP and 0 on the PRO processor.
+*/
+#ifdef __ASSEMBLER__
+	.macro getcoreid reg
+	rsr.prid \reg
+	extui \reg,\reg,13,1
+	.endm
+#endif
+
+#define CORE_ID_PRO 0xCDCD
+#define CORE_ID_APP 0xABAB
+
+/*
+-------------------------------------------------------------------------------
+  MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
+
+  Convenient where the frame size requirements are the same for both ABIs.
+    ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
+    ENTRY0,    RET0    are for frameless functions (no locals, no calls).
+
+  where size = size of stack frame in bytes (must be >0 and aligned to 16).
+  For framed functions the frame is created and the return address saved at
+  base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
+  For frameless functions, there is no frame and return address remains in a0.
+  Note: Because CPP macros expand to a single line, macros requiring multi-line 
+  expansions are implemented as assembler macros.
+-------------------------------------------------------------------------------
+*/
+
+#ifdef __ASSEMBLER__
+#ifdef __XTENSA_CALL0_ABI__
+  /* Call0 */
+  #define ENTRY(sz)     entry1  sz
+    .macro  entry1 size=0x10
+    addi    sp, sp, -\size
+    s32i    a0, sp, 0
+    .endm
+  #define ENTRY0      
+  #define RET(sz)       ret1    sz
+    .macro  ret1 size=0x10
+    l32i    a0, sp, 0
+    addi    sp, sp, \size
+    ret
+    .endm
+  #define RET0          ret
+#else
+  /* Windowed */
+  #define ENTRY(sz)     entry   sp, sz
+  #define ENTRY0        entry   sp, 0x10
+  #define RET(sz)       retw
+  #define RET0          retw
+#endif
+#endif
+
+
+
+
+
+#endif /* XTENSA_CONTEXT_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h
new file mode 100644
index 0000000..dbd82b6
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h
@@ -0,0 +1,231 @@
+/*******************************************************************************
+*  // Copyright (c) 2003-2015 Cadence Design Systems, Inc.
+*  //
+*  // Permission is hereby granted, free of charge, to any person obtaining
+*  // a copy of this software and associated documentation files (the
+*  // "Software"), to deal in the Software without restriction, including
+*  // without limitation the rights to use, copy, modify, merge, publish,
+*  // distribute, sublicense, and/or sell copies of the Software, and to
+*  // permit persons to whom the Software is furnished to do so, subject to
+*  // the following conditions:
+*  //
+*  // The above copyright notice and this permission notice shall be included
+*  // in all copies or substantial portions of the Software.
+*  //
+*  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+*  // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+*  // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+*  // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+*  // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+*  // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+*  // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*  --------------------------------------------------------------------------------
+*
+*       RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES
+*                           (FreeRTOS Port)
+*
+*  This header is the primary glue between generic Xtensa RTOS support
+*  sources and a specific RTOS port for Xtensa.  It contains definitions
+*  and macros for use primarily by Xtensa assembly coded source files.
+*
+*  Macros in this header map callouts from generic Xtensa files to specific
+*  RTOS functions. It may also be included in C source files.
+*
+*  Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa
+*  architecture, using the Xtensa hardware abstraction layer (HAL) to deal
+*  with configuration specifics.
+*
+*  Should be included by all Xtensa generic and RTOS port-specific sources.
+*
+*******************************************************************************/
+
+#ifndef XTENSA_RTOS_H
+#define XTENSA_RTOS_H
+
+#ifdef __ASSEMBLER__
+    #include    <xtensa/coreasm.h>
+#else
+    #include    <xtensa/config/core.h>
+#endif
+
+#include    <xtensa/corebits.h>
+#include    <xtensa/config/system.h>
+
+/*
+ * Include any RTOS specific definitions that are needed by this header.
+ */
+#include    "FreeRTOSConfig.h"
+
+/*
+ * Convert FreeRTOSConfig definitions to XTENSA definitions.
+ * However these can still be overridden from the command line.
+ */
+
+#ifndef XT_SIMULATOR
+    #if configXT_SIMULATOR
+        #define XT_SIMULATOR    1       /* Simulator mode */
+    #endif
+#endif
+
+#ifndef XT_BOARD
+    #if configXT_BOARD
+        #define XT_BOARD    1           /* Board mode */
+    #endif
+#endif
+
+#ifndef XT_TIMER_INDEX
+    #if defined configXT_TIMER_INDEX
+        #define XT_TIMER_INDEX    configXT_TIMER_INDEX     /* Index of hardware timer to be used */
+    #endif
+#endif
+
+#ifndef XT_INTEXC_HOOKS
+    #if configXT_INTEXC_HOOKS
+        #define XT_INTEXC_HOOKS    1    /* Enables exception hooks */
+    #endif
+#endif
+
+#if !defined( XT_SIMULATOR ) && !defined( XT_BOARD )
+    #error Either XT_SIMULATOR or XT_BOARD must be defined.
+#endif
+
+
+/*
+ * Name of RTOS (for messages).
+ */
+#define XT_RTOS_NAME    FreeRTOS
+
+/*
+ * Check some Xtensa configuration requirements and report error if not met.
+ * Error messages can be customize to the RTOS port.
+ */
+
+#if !XCHAL_HAVE_XEA2
+    #error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."
+#endif
+
+
+/*******************************************************************************
+*
+*  RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
+*
+*  Define callout macros used in generic Xtensa code to interact with the RTOS.
+*  The macros are simply the function names for use in calls from assembler code.
+*  Some of these functions may call back to generic functions in xtensa_context.h .
+*
+*******************************************************************************/
+
+/*
+ * Inform RTOS of entry into an interrupt handler that will affect it.
+ * Allows RTOS to manage switch to any system stack and count nesting level.
+ * Called after minimal context has been saved, with interrupts disabled.
+ * RTOS port can call0 _xt_context_save to save the rest of the context.
+ * May only be called from assembly code by the 'call0' instruction.
+ */
+/* void XT_RTOS_INT_ENTER(void) */
+#define XT_RTOS_INT_ENTER    _frxt_int_enter
+
+/*
+ * Inform RTOS of completion of an interrupt handler, and give control to
+ * RTOS to perform thread/task scheduling, switch back from any system stack
+ * and restore the context, and return to the exit dispatcher saved in the
+ * stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
+ * to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
+ * leaving only a minimal part of the context to be restored by the exit
+ * dispatcher. This function does not return to the place it was called from.
+ * May only be called from assembly code by the 'call0' instruction.
+ */
+/* void XT_RTOS_INT_EXIT(void) */
+#define XT_RTOS_INT_EXIT    _frxt_int_exit
+
+/*
+ * Inform RTOS of the occurrence of a tick timer interrupt.
+ * If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
+ * May be coded in or called from C or assembly, per ABI conventions.
+ * RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
+ */
+/* void XT_RTOS_TIMER_INT(void) */
+#define XT_RTOS_TIMER_INT    _frxt_timer_int
+#define XT_TICK_PER_SEC      configTICK_RATE_HZ
+
+/*
+ * Return in a15 the base address of the co-processor state save area for the
+ * thread that triggered a co-processor exception, or 0 if no thread was running.
+ * The state save area is structured as defined in xtensa_context.h and has size
+ * XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
+ * in interrupt handlers or the RTOS kernel. May only be called from assembly code
+ * and by the 'call0' instruction. A result of 0 indicates an unrecoverable error.
+ * The implementation may use only a2-4, a15 (all other regs must be preserved).
+ */
+/* void* XT_RTOS_CP_STATE(void) */
+#define XT_RTOS_CP_STATE    _frxt_task_coproc_state
+
+
+/*******************************************************************************
+*
+*  HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
+*
+*  This Xtensa RTOS port provides hooks for dynamically installing exception
+*  and interrupt handlers to facilitate automated testing where each test
+*  case can install its own handler for user exceptions and each interrupt
+*  priority (level). This consists of an array of function pointers indexed
+*  by interrupt priority, with index 0 being the user exception handler hook.
+*  Each entry in the array is initially 0, and may be replaced by a function
+*  pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
+*
+*  The handler for low and medium priority obeys ABI conventions so may be coded
+*  in C. For the exception handler, the cause is the contents of the EXCCAUSE
+*  reg, and the result is -1 if handled, else the cause (still needs handling).
+*  For interrupt handlers, the cause is a mask of pending enabled interrupts at
+*  that level, and the result is the same mask with the bits for the handled
+*  interrupts cleared (those not cleared still need handling). This allows a test
+*  case to either pre-handle or override the default handling for the exception
+*  or interrupt level (see xtensa_vectors.S).
+*
+*  High priority handlers (including NMI) must be coded in assembly, are always
+*  called by 'call0' regardless of ABI, must preserve all registers except a0,
+*  and must not use or modify the interrupted stack. The hook argument 'cause'
+*  is not passed and the result is ignored, so as not to burden the caller with
+*  saving and restoring a2 (it assumes only one interrupt per level - see the
+*  discussion in high priority interrupts in xtensa_vectors.S). The handler
+*  therefore should be coded to prototype 'void h(void)' even though it plugs
+*  into an array of handlers of prototype 'unsigned h(unsigned)'.
+*
+*  To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
+*
+*******************************************************************************/
+
+#define XT_INTEXC_HOOK_NUM    ( 1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI )
+
+#ifndef __ASSEMBLER__
+    typedef unsigned (* XT_INTEXC_HOOK)( unsigned cause );
+    extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[ XT_INTEXC_HOOK_NUM ];
+#endif
+
+
+/*******************************************************************************
+*
+*  CONVENIENCE INCLUSIONS.
+*
+*  Ensures RTOS specific files need only include this one Xtensa-generic header.
+*  These headers are included last so they can use the RTOS definitions above.
+*
+*******************************************************************************/
+
+#include    "xtensa_context.h"
+
+#ifdef XT_RTOS_TIMER_INT
+    #include    "xtensa_timer.h"
+#endif
+
+
+/*******************************************************************************
+*
+*  Xtensa Port Version.
+*
+*******************************************************************************/
+
+#define XTENSA_PORT_VERSION           1.4 .2
+#define XTENSA_PORT_VERSION_STRING    "1.4.2"
+
+#endif /* XTENSA_RTOS_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h
new file mode 100644
index 0000000..431205d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h
@@ -0,0 +1,158 @@
+/*******************************************************************************
+*  // Copyright (c) 2003-2015 Cadence Design Systems, Inc.
+*  //
+*  // Permission is hereby granted, free of charge, to any person obtaining
+*  // a copy of this software and associated documentation files (the
+*  // "Software"), to deal in the Software without restriction, including
+*  // without limitation the rights to use, copy, modify, merge, publish,
+*  // distribute, sublicense, and/or sell copies of the Software, and to
+*  // permit persons to whom the Software is furnished to do so, subject to
+*  // the following conditions:
+*  //
+*  // The above copyright notice and this permission notice shall be included
+*  // in all copies or substantial portions of the Software.
+*  //
+*  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+*  // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+*  // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+*  // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+*  // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+*  // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+*  // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*  --------------------------------------------------------------------------------
+*
+*       XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
+*
+*  This header contains definitions and macros for use primarily by Xtensa
+*  RTOS assembly coded source files. It includes and uses the Xtensa hardware
+*  abstraction layer (HAL) to deal with config specifics. It may also be
+*  included in C source files.
+*
+*  User may edit to modify timer selection and to specify clock frequency and
+*  tick duration to match timer interrupt to the real-time tick duration.
+*
+*  If the RTOS has no timer interrupt, then there is no tick timer and the
+*  clock frequency is irrelevant, so all of these macros are left undefined
+*  and the Xtensa core configuration need not have a timer.
+*
+*******************************************************************************/
+
+#ifndef XTENSA_TIMER_H
+#define XTENSA_TIMER_H
+
+#ifdef __ASSEMBLER__
+    #include    <xtensa/coreasm.h>
+#endif
+
+#include    <xtensa/corebits.h>
+#include    <xtensa/config/system.h>
+
+#include    "xtensa_rtos.h" /* in case this wasn't included directly */
+
+#include    "FreeRTOSConfig.h"
+
+/*
+ * Select timer to use for periodic tick, and determine its interrupt number
+ * and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
+ * in which case its validity is checked (it must exist in this core and must
+ * not be on a high priority interrupt - an error will be reported in invalid).
+ * Otherwise select the first low or medium priority interrupt timer available.
+ */
+#if XCHAL_NUM_TIMERS == 0
+
+    #error "This Xtensa configuration is unsupported, it has no timers."
+
+#else
+
+    #ifndef XT_TIMER_INDEX
+        #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+            #if XCHAL_INT_LEVEL( XCHAL_TIMER3_INTERRUPT ) <= XCHAL_EXCM_LEVEL
+                #undef  XT_TIMER_INDEX
+                #define XT_TIMER_INDEX    3
+            #endif
+        #endif
+        #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+            #if XCHAL_INT_LEVEL( XCHAL_TIMER2_INTERRUPT ) <= XCHAL_EXCM_LEVEL
+                #undef  XT_TIMER_INDEX
+                #define XT_TIMER_INDEX    2
+            #endif
+        #endif
+        #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+            #if XCHAL_INT_LEVEL( XCHAL_TIMER1_INTERRUPT ) <= XCHAL_EXCM_LEVEL
+                #undef  XT_TIMER_INDEX
+                #define XT_TIMER_INDEX    1
+            #endif
+        #endif
+        #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+            #if XCHAL_INT_LEVEL( XCHAL_TIMER0_INTERRUPT ) <= XCHAL_EXCM_LEVEL
+                #undef  XT_TIMER_INDEX
+                #define XT_TIMER_INDEX    0
+            #endif
+        #endif
+    #endif /* ifndef XT_TIMER_INDEX */
+    #ifndef XT_TIMER_INDEX
+        #error "There is no suitable timer in this Xtensa configuration."
+    #endif
+
+    #define XT_CCOMPARE        ( CCOMPARE + XT_TIMER_INDEX )
+    #define XT_TIMER_INTNUM    XCHAL_TIMER_INTERRUPT( XT_TIMER_INDEX )
+    #define XT_TIMER_INTPRI    XCHAL_INT_LEVEL( XT_TIMER_INTNUM )
+    #define XT_TIMER_INTEN     ( 1 << XT_TIMER_INTNUM )
+
+    #if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
+        #error "The timer selected by XT_TIMER_INDEX does not exist in this core."
+    #elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
+        #error "The timer interrupt cannot be high priority (use medium or low)."
+    #endif
+
+#endif /* XCHAL_NUM_TIMERS */
+
+/*
+ * Set processor clock frequency, used to determine clock divisor for timer tick.
+ * User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
+ * If using a supported board via the board-independent API defined in xtbsp.h,
+ * this may be left undefined and frequency and tick divisor will be computed
+ * and cached during run-time initialization.
+ *
+ * NOTE ON SIMULATOR:
+ * Under the Xtensa instruction set simulator, the frequency can only be estimated
+ * because it depends on the speed of the host and the version of the simulator.
+ * Also because it runs much slower than hardware, it is not possible to achieve
+ * real-time performance for most applications under the simulator. A frequency
+ * too low does not allow enough time between timer interrupts, starving threads.
+ * To obtain a more convenient but non-real-time tick duration on the simulator,
+ * compile with xt-xcc option "-DXT_SIMULATOR".
+ * Adjust this frequency to taste (it's not real-time anyway!).
+ */
+#if defined( XT_SIMULATOR ) && !defined( XT_CLOCK_FREQ )
+    #define XT_CLOCK_FREQ    configCPU_CLOCK_HZ
+#endif
+
+#if !defined( XT_CLOCK_FREQ ) && !defined( XT_BOARD )
+    #error "XT_CLOCK_FREQ must be defined for the target platform."
+#endif
+
+/*
+ * Default number of timer "ticks" per second (default 100 for 10ms tick).
+ * RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
+ * User may redefine this to an optimal value for the application, either by
+ * editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
+ * "-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.
+ */
+#ifndef XT_TICK_PER_SEC
+    #define XT_TICK_PER_SEC    configTICK_RATE_HZ    /* 10 ms tick = 100 ticks per second */
+#endif
+
+/*
+ * Derivation of clock divisor for timer tick and interrupt (one per tick).
+ */
+#ifdef XT_CLOCK_FREQ
+    #define XT_TICK_DIVISOR    ( XT_CLOCK_FREQ / XT_TICK_PER_SEC )
+#endif
+
+#ifndef __ASSEMBLER__
+    extern unsigned _xt_tick_divisor;
+    extern void _xt_tick_divisor_init( void );
+#endif
+
+#endif /* XTENSA_TIMER_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
new file mode 100644
index 0000000..d3666a5
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
@@ -0,0 +1,517 @@
+/*
+ *  FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
+ *  All rights reserved
+ *
+ *  VISIT https://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+ *
+ *  This file is part of the FreeRTOS distribution.
+ *
+ *  FreeRTOS is free software; you can redistribute it and/or modify it under
+ *  the terms of the GNU General Public License (version 2) as published by the
+ *  Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+ *
+ ***************************************************************************
+ *  >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+ *  >>!   distribute a combined work that includes FreeRTOS without being   !<<
+ *  >>!   obliged to provide the source code for proprietary components     !<<
+ *  >>!   outside of the FreeRTOS kernel.                                   !<<
+ ***************************************************************************
+ *
+ *  FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ *  WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ *  FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+ *  link: https://www.FreeRTOS.org/a00114.html
+ *
+ ***************************************************************************
+ *                                                                       *
+ *    FreeRTOS provides completely free yet professionally developed,    *
+ *    robust, strictly quality controlled, supported, and cross          *
+ *    platform software that is more than just the market leader, it     *
+ *    is the industry's de facto standard.                               *
+ *                                                                       *
+ *    Help yourself get started quickly while simultaneously helping     *
+ *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+ *    tutorial book, reference manual, or both:                          *
+ *    https://www.FreeRTOS.org/Documentation                             *
+ *                                                                       *
+ ***************************************************************************
+ *
+ *  https://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+ *  the FAQ page "My application does not run, what could be wrong?".  Have you
+ *  defined configASSERT()?
+ *
+ *  https://www.FreeRTOS.org/support - In return for receiving this top quality
+ *  embedded software for free we request you assist our global community by
+ *  participating in the support forum.
+ *
+ *  https://www.FreeRTOS.org/training - Investing in training allows your team
+ *  to be as productive as possible as early as possible.  Now you can receive
+ *  FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+ *  Ltd, and the world's leading authority on the world's leading RTOS.
+ *
+ *  https://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ *  including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ *  compatible FAT file system, and our tiny thread aware UDP/IP stack.
+ *
+ *  https://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+ *  Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+ *
+ *  https://www.highintegritysystems.com/openrtos/ - Real Time Engineers ltd.
+ *  license FreeRTOS to High Integrity Systems ltd. to sell under the OpenRTOS
+ *  brand.  Low cost OpenRTOS licenses offer ticketed support, indemnification
+ *  and commercial middleware.
+ *
+ *  https://www.highintegritysystems.com/safertos/ - High Integrity Systems
+ *  also provide a safety engineered and independently SIL3 certified version
+ *  for use in safety and mission critical applications that require provable
+ *  dependability.
+ *
+ */
+
+/*******************************************************************************
+ * // Copyright (c) 2003-2015 Cadence Design Systems, Inc.
+ * //
+ * // Permission is hereby granted, free of charge, to any person obtaining
+ * // a copy of this software and associated documentation files (the
+ * // "Software"), to deal in the Software without restriction, including
+ * // without limitation the rights to use, copy, modify, merge, publish,
+ * // distribute, sublicense, and/or sell copies of the Software, and to
+ * // permit persons to whom the Software is furnished to do so, subject to
+ * // the following conditions:
+ * //
+ * // The above copyright notice and this permission notice shall be included
+ * // in all copies or substantial portions of the Software.
+ * //
+ * // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ * -----------------------------------------------------------------------------
+ */
+
+#include <stdlib.h>
+#include <xtensa/config/core.h>
+
+#include "xtensa_rtos.h"
+
+#if CONFIG_IDF_TARGET_ESP32S2
+    #include "esp32s2/rom/ets_sys.h"
+#elif CONFIG_IDF_TARGET_ESP32
+    #include "esp32/rom/ets_sys.h"
+#endif
+#include "soc/cpu.h"
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#include "esp_private/panic_reason.h"
+#include "esp_debug_helpers.h"
+#include "esp_heap_caps.h"
+#include "esp_private/crosscore_int.h"
+
+#include "esp_intr_alloc.h"
+#include "esp_log.h"
+
+/* Defined in portasm.h */
+extern void _frxt_tick_timer_init( void );
+
+/* Defined in xtensa_context.S */
+extern void _xt_coproc_init( void );
+
+
+#if CONFIG_FREERTOS_CORETIMER_0
+    #define SYSTICK_INTR_ID    ( ETS_INTERNAL_TIMER0_INTR_SOURCE + ETS_INTERNAL_INTR_SOURCE_OFF )
+#endif
+#if CONFIG_FREERTOS_CORETIMER_1
+    #define SYSTICK_INTR_ID    ( ETS_INTERNAL_TIMER1_INTR_SOURCE + ETS_INTERNAL_INTR_SOURCE_OFF )
+#endif
+
+/*-----------------------------------------------------------*/
+
+unsigned port_xSchedulerRunning[ portNUM_PROCESSORS ] = { 0 }; /* Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting */
+unsigned port_interruptNesting[ portNUM_PROCESSORS ] = { 0 };  /* Interrupt nesting level. Increased/decreased in portasm.c, _frxt_int_enter/_frxt_int_exit */
+
+/*-----------------------------------------------------------*/
+
+/* User exception dispatcher when exiting */
+void _xt_user_exit( void );
+
+#if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
+/* Wrapper to allow task functions to return (increases stack overhead by 16 bytes) */
+    static void vPortTaskWrapper( TaskFunction_t pxCode,
+                                  void * pvParameters )
+    {
+        pxCode( pvParameters );
+        /*FreeRTOS tasks should not return. Log the task name and abort. */
+        char * pcTaskName = pcTaskGetTaskName( NULL );
+        ESP_LOGE( "FreeRTOS", "FreeRTOS Task \"%s\" should not return, Aborting now!", pcTaskName );
+        abort();
+    }
+#endif /* if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER */
+
+/*
+ * Stack initialization
+ */
+/* *INDENT-OFF* */
+#if portUSING_MPU_WRAPPERS
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged )
+#else
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters )
+#endif
+/* *INDENT-ON* */
+{
+    StackType_t * sp, * tp;
+    XtExcFrame * frame;
+
+    #if XCHAL_CP_NUM > 0
+        uint32_t * p;
+    #endif
+
+    /* Create interrupt stack frame aligned to 16 byte boundary */
+    sp = ( StackType_t * ) ( ( ( UBaseType_t ) pxTopOfStack - XT_CP_SIZE - XT_STK_FRMSZ ) & ~0xf );
+
+    /* Clear the entire frame (do not use memset() because we don't depend on C library) */
+    for( tp = sp; tp <= pxTopOfStack; ++tp )
+    {
+        *tp = 0;
+    }
+
+    frame = ( XtExcFrame * ) sp;
+
+    /* Explicitly initialize certain saved registers */
+    #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
+        frame->pc = ( UBaseType_t ) vPortTaskWrapper; /* task wrapper						*/
+    #else
+        frame->pc = ( UBaseType_t ) pxCode;           /* task entrypoint					*/
+    #endif
+    frame->a0 = 0;                                    /* to terminate GDB backtrace		*/
+    frame->a1 = ( UBaseType_t ) sp + XT_STK_FRMSZ;    /* physical top of stack frame		*/
+    frame->exit = ( UBaseType_t ) _xt_user_exit;      /* user exception exit dispatcher	*/
+
+    /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */
+    /* Also set entry point argument parameter. */
+    #ifdef __XTENSA_CALL0_ABI__
+        #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
+            frame->a2 = ( UBaseType_t ) pxCode;
+            frame->a3 = ( UBaseType_t ) pvParameters;
+        #else
+            frame->a2 = ( UBaseType_t ) pvParameters;
+        #endif
+        frame->ps = PS_UM | PS_EXCM;
+    #else
+        /* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */
+        #if CONFIG_FREERTOS_TASK_FUNCTION_WRAPPER
+            frame->a6 = ( UBaseType_t ) pxCode;
+            frame->a7 = ( UBaseType_t ) pvParameters;
+        #else
+            frame->a6 = ( UBaseType_t ) pvParameters;
+        #endif
+        frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC( 1 );
+    #endif /* ifdef __XTENSA_CALL0_ABI__ */
+
+    #ifdef XT_USE_SWPRI
+        /* Set the initial virtual priority mask value to all 1's. */
+        frame->vpri = 0xFFFFFFFF;
+    #endif
+
+    #if XCHAL_CP_NUM > 0
+        /* Init the coprocessor save area (see xtensa_context.h) */
+
+        /* No access to TCB here, so derive indirectly. Stack growth is top to bottom.
+         * //p = (uint32_t *) xMPUSettings->coproc_area;
+         */
+        p = ( uint32_t * ) ( ( ( uint32_t ) pxTopOfStack - XT_CP_SIZE ) & ~0xf );
+        configASSERT( ( uint32_t ) p >= frame->a1 );
+        p[ 0 ] = 0;
+        p[ 1 ] = 0;
+        p[ 2 ] = ( ( ( uint32_t ) p ) + 12 + XCHAL_TOTAL_SA_ALIGN - 1 ) & -XCHAL_TOTAL_SA_ALIGN;
+    #endif
+
+    return sp;
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* It is unlikely that the Xtensa port will get stopped.  If required simply
+     * disable the tick interrupt here. */
+}
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+    /* Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored */
+
+    #if XCHAL_CP_NUM > 0
+        /* Initialize co-processor management for tasks. Leave CPENABLE alone. */
+        _xt_coproc_init();
+    #endif
+
+    /* Init the tick divisor value */
+    _xt_tick_divisor_init();
+
+    /* Setup the hardware to generate the tick. */
+    _frxt_tick_timer_init();
+
+    port_xSchedulerRunning[ xPortGetCoreID() ] = 1;
+
+    /* Cannot be directly called from C; never returns */
+    __asm__ volatile ( "call0    _frxt_dispatch\n" );
+
+    /* Should not get here. */
+    return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortSysTickHandler( void )
+{
+    BaseType_t ret;
+    unsigned interruptMask;
+
+    portbenchmarkIntLatency();
+    traceISR_ENTER( SYSTICK_INTR_ID );
+
+    /* Interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY must be
+     * disabled before calling xTaskIncrementTick as it access the
+     * kernel lists. */
+    interruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        ret = xTaskIncrementTick();
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( interruptMask );
+
+    if( ret != pdFALSE )
+    {
+        portYIELD_FROM_ISR();
+    }
+    else
+    {
+        traceISR_EXIT();
+    }
+
+    return ret;
+}
+
+
+void vPortYieldOtherCore( BaseType_t coreid )
+{
+    esp_crosscore_int_send_yield( coreid );
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area.
+ */
+#if portUSING_MPU_WRAPPERS
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    uint32_t usStackDepth )
+    {
+        #if XCHAL_CP_NUM > 0
+            xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + usStackDepth - 1 ));
+            xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+            xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
+
+
+            /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
+             * clear the stack area after we return. This is done in pxPortInitialiseStack().
+             */
+        #endif
+    }
+
+    void vPortReleaseTaskMPUSettings( xMPU_SETTINGS * xMPUSettings )
+    {
+        /* If task has live floating point registers somewhere, release them */
+        _xt_coproc_release( xMPUSettings->coproc_area );
+    }
+
+#endif /* if portUSING_MPU_WRAPPERS */
+
+/*
+ * Returns true if the current core is in ISR context; low prio ISR, med prio ISR or timer tick ISR. High prio ISRs
+ * aren't detected here, but they normally cannot call C code, so that should not be an issue anyway.
+ */
+BaseType_t xPortInIsrContext()
+{
+    unsigned int irqStatus;
+    BaseType_t ret;
+
+    irqStatus = portENTER_CRITICAL_NESTED();
+    ret = ( port_interruptNesting[ xPortGetCoreID() ] != 0 );
+    portEXIT_CRITICAL_NESTED( irqStatus );
+    return ret;
+}
+
+/*
+ * This function will be called in High prio ISRs. Returns true if the current core was in ISR context
+ * before calling into high prio ISR context.
+ */
+BaseType_t IRAM_ATTR xPortInterruptedFromISRContext()
+{
+    return( port_interruptNesting[ xPortGetCoreID() ] != 0 );
+}
+
+void vPortAssertIfInISR()
+{
+    if( xPortInIsrContext() )
+    {
+        ets_printf( "core=%d port_interruptNesting=%d\n\n", xPortGetCoreID(), port_interruptNesting[ xPortGetCoreID() ] );
+    }
+
+    configASSERT( !xPortInIsrContext() );
+}
+
+/*
+ * For kernel use: Initialize a per-CPU mux. Mux will be initialized unlocked.
+ */
+void vPortCPUInitializeMutex( portMUX_TYPE * mux )
+{
+    #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+        ets_printf( "Initializing mux %p\n", mux );
+        mux->lastLockedFn = "(never locked)";
+        mux->lastLockedLine = -1;
+    #endif
+    mux->owner = portMUX_FREE_VAL;
+    mux->count = 0;
+}
+
+#include "portmux_impl.h"
+
+/*
+ * For kernel use: Acquire a per-CPU mux. Spinlocks, so don't hold on to these muxes for too long.
+ */
+#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+    void vPortCPUAcquireMutex( portMUX_TYPE * mux,
+                               const char * fnName,
+                               int line )
+    {
+        unsigned int irqStatus = portENTER_CRITICAL_NESTED();
+
+        vPortCPUAcquireMutexIntsDisabled( mux, portMUX_NO_TIMEOUT, fnName, line );
+        portEXIT_CRITICAL_NESTED( irqStatus );
+    }
+
+    bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux,
+                                      int timeout_cycles,
+                                      const char * fnName,
+                                      int line )
+    {
+        unsigned int irqStatus = portENTER_CRITICAL_NESTED();
+        bool result = vPortCPUAcquireMutexIntsDisabled( mux, timeout_cycles, fnName, line );
+
+        portEXIT_CRITICAL_NESTED( irqStatus );
+        return result;
+    }
+
+#else /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
+    void vPortCPUAcquireMutex( portMUX_TYPE * mux )
+    {
+        unsigned int irqStatus = portENTER_CRITICAL_NESTED();
+
+        vPortCPUAcquireMutexIntsDisabled( mux, portMUX_NO_TIMEOUT );
+        portEXIT_CRITICAL_NESTED( irqStatus );
+    }
+
+    bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux,
+                                      int timeout_cycles )
+    {
+        unsigned int irqStatus = portENTER_CRITICAL_NESTED();
+        bool result = vPortCPUAcquireMutexIntsDisabled( mux, timeout_cycles );
+
+        portEXIT_CRITICAL_NESTED( irqStatus );
+        return result;
+    }
+#endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
+
+
+/*
+ * For kernel use: Release a per-CPU mux
+ *
+ * Mux must be already locked by this core
+ */
+#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+    void vPortCPUReleaseMutex( portMUX_TYPE * mux,
+                               const char * fnName,
+                               int line )
+    {
+        unsigned int irqStatus = portENTER_CRITICAL_NESTED();
+
+        vPortCPUReleaseMutexIntsDisabled( mux, fnName, line );
+        portEXIT_CRITICAL_NESTED( irqStatus );
+    }
+#else
+    void vPortCPUReleaseMutex( portMUX_TYPE * mux )
+    {
+        unsigned int irqStatus = portENTER_CRITICAL_NESTED();
+
+        vPortCPUReleaseMutexIntsDisabled( mux );
+        portEXIT_CRITICAL_NESTED( irqStatus );
+    }
+#endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
+
+void vPortSetStackWatchpoint( void * pxStackStart )
+{
+    /*Set watchpoint 1 to watch the last 32 bytes of the stack. */
+    /*Unfortunately, the Xtensa watchpoints can't set a watchpoint on a random [base - base+n] region because */
+    /*the size works by masking off the lowest address bits. For that reason, we futz a bit and watch the lowest 32 */
+    /*bytes of the stack we can actually watch. In general, this can cause the watchpoint to be triggered at most */
+    /*28 bytes early. The value 32 is chosen because it's larger than the stack canary, which in FreeRTOS is 20 bytes. */
+    /*This way, we make sure we trigger before/when the stack canary is corrupted, not after. */
+    int addr = ( int ) pxStackStart;
+
+    addr = ( addr + 31 ) & ( ~31 );
+    esp_set_watchpoint( 1, ( char * ) addr, 32, ESP_WATCHPOINT_STORE );
+}
+
+#if defined( CONFIG_SPIRAM_SUPPORT )
+
+/*
+ * Compare & set (S32C1) does not work in external RAM. Instead, this routine uses a mux (in internal memory) to fake it.
+ */
+    static portMUX_TYPE extram_mux = portMUX_INITIALIZER_UNLOCKED;
+
+    void uxPortCompareSetExtram( volatile uint32_t * addr,
+                                 uint32_t compare,
+                                 uint32_t * set )
+    {
+        uint32_t prev;
+
+        #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+            vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT, __FUNCTION__, __LINE__ );
+        #else
+            vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT );
+        #endif
+        prev = *addr;
+
+        if( prev == compare )
+        {
+            *addr = *set;
+        }
+
+        *set = prev;
+        #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+            vPortCPUReleaseMutexIntsDisabled( &extram_mux, __FUNCTION__, __LINE__ );
+        #else
+            vPortCPUReleaseMutexIntsDisabled( &extram_mux );
+        #endif
+    }
+#endif //defined(CONFIG_SPIRAM_SUPPORT)
+
+
+
+uint32_t xPortGetTickRateHz( void )
+{
+    return ( uint32_t ) configTICK_RATE_HZ;
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portasm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portasm.S
new file mode 100644
index 0000000..7884cf4
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portasm.S
@@ -0,0 +1,677 @@
+/*
+//-----------------------------------------------------------------------------
+// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
+//
+// Permission is hereby granted, free of charge, to any person obtaining
+// a copy of this software and associated documentation files (the
+// "Software"), to deal in the Software without restriction, including
+// without limitation the rights to use, copy, modify, merge, publish,
+// distribute, sublicense, and/or sell copies of the Software, and to
+// permit persons to whom the Software is furnished to do so, subject to
+// the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+//-----------------------------------------------------------------------------
+*/
+
+#include "xtensa_rtos.h"
+#include "sdkconfig.h"
+
+#define TOPOFSTACK_OFFS                 0x00    /* StackType_t *pxTopOfStack */
+#define CP_TOPOFSTACK_OFFS              0x04    /* xMPU_SETTINGS.coproc_area */
+
+.extern pxCurrentTCB
+
+/*
+*******************************************************************************
+* Interrupt stack. The size of the interrupt stack is determined by the config
+* parameter "configISR_STACK_SIZE" in FreeRTOSConfig.h
+*******************************************************************************
+*/
+
+    .data
+    .align      16
+    .global     port_IntStack
+    .global     port_IntStackTop
+    .global     port_switch_flag
+port_IntStack:
+    .space      configISR_STACK_SIZE*portNUM_PROCESSORS		/* This allocates stacks for each individual CPU. */
+port_IntStackTop:
+    .word		0
+port_switch_flag:
+    .space      portNUM_PROCESSORS*4 /* One flag for each individual CPU. */
+
+    .text
+
+/*
+*******************************************************************************
+* _frxt_setup_switch
+* void _frxt_setup_switch(void);
+* 
+* Sets an internal flag indicating that a task switch is required on return
+* from interrupt handling.
+* 
+*******************************************************************************
+*/
+    .global     _frxt_setup_switch
+    .type       _frxt_setup_switch,@function
+    .align      4
+_frxt_setup_switch:
+
+    ENTRY(16)
+
+	getcoreid a3
+    movi    a2, port_switch_flag
+	addx4	a2,  a3, a2
+
+    movi    a3, 1
+    s32i    a3, a2, 0
+
+    RET(16)
+
+
+
+
+
+
+/*
+*******************************************************************************
+* _frxt_int_enter
+* void _frxt_int_enter(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for
+* freeRTOS. Saves the rest of the interrupt context (not already saved).
+* May only be called from assembly code by the 'call0' instruction, with
+* interrupts disabled.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+*******************************************************************************
+*/
+    .globl  _frxt_int_enter
+    .type   _frxt_int_enter,@function
+    .align  4
+_frxt_int_enter:
+
+    /* Save a12-13 in the stack frame as required by _xt_context_save. */
+    s32i    a12, a1, XT_STK_A12
+    s32i    a13, a1, XT_STK_A13
+
+    /* Save return address in a safe place (free a0). */
+    mov     a12, a0
+
+    /* Save the rest of the interrupted context (preserves A12-13). */
+    call0   _xt_context_save
+
+    /*
+    Save interrupted task's SP in TCB only if not nesting.
+    Manage nesting directly rather than call the generic IntEnter()
+    (in windowed ABI we can't call a C function here anyway because PS.EXCM is still set).
+    */
+	getcoreid a4
+    movi    a2,  port_xSchedulerRunning
+	addx4	a2,  a4, a2
+    movi    a3,  port_interruptNesting
+	addx4	a3,  a4, a3
+    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
+    beqz    a2,  1f                     /* scheduler not running, no tasks */
+    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
+    addi    a2,  a2, 1                  /* increment nesting count         */
+    s32i    a2,  a3, 0                  /* save nesting count              */
+    bnei    a2,  1, .Lnested            /* !=0 before incr, so nested      */
+
+    movi    a2,  pxCurrentTCB
+	addx4	a2,  a4, a2
+    l32i    a2,  a2, 0                  /* a2 = current TCB                */
+    beqz    a2,  1f
+    s32i    a1,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP */
+    movi    a1,  port_IntStack+configISR_STACK_SIZE   /* a1 = top of intr stack for CPU 0  */
+    movi    a2,  configISR_STACK_SIZE   /* add configISR_STACK_SIZE * cpu_num to arrive at top of stack for cpu_num */
+	mull	a2,  a4, a2
+	add     a1,  a1, a2					/* for current proc */
+
+    #ifdef CONFIG_FREERTOS_FPU_IN_ISR
+    #if XCHAL_CP_NUM > 0
+    rsr     a3, CPENABLE                /* Restore thread scope CPENABLE */
+    addi    sp, sp,-4                   /* ISR will manage FPU coprocessor by forcing */
+    s32i    a3, a1, 0                   /* its trigger */
+    #endif
+    #endif
+
+.Lnested:
+1:
+    #ifdef CONFIG_FREERTOS_FPU_IN_ISR
+    #if XCHAL_CP_NUM > 0
+    movi    a3,  0              /* whilst ISRs pending keep CPENABLE exception active */
+    wsr     a3,  CPENABLE
+    rsync
+    #endif
+    #endif
+
+    mov     a0,  a12                    /* restore return addr and return  */
+    ret
+
+/*
+*******************************************************************************
+* _frxt_int_exit
+* void _frxt_int_exit(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for
+* FreeRTOS. If required, calls vPortYieldFromInt() to perform task context
+* switching, restore the (possibly) new task's context, and return to the
+* exit dispatcher saved in the task's stack frame at XT_STK_EXIT.
+* May only be called from assembly code by the 'call0' instruction. Does not
+* return to caller.
+* See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+*******************************************************************************
+*/
+    .globl  _frxt_int_exit
+    .type   _frxt_int_exit,@function
+    .align  4
+_frxt_int_exit:
+
+	getcoreid a4
+    movi    a2,  port_xSchedulerRunning
+	addx4	a2,  a4, a2
+    movi    a3,  port_interruptNesting
+	addx4	a3,  a4, a3
+    rsil    a0,  XCHAL_EXCM_LEVEL       /* lock out interrupts             */
+    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
+    beqz    a2,  .Lnoswitch             /* scheduler not running, no tasks */
+    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
+    addi    a2,  a2, -1                 /* decrement nesting count         */
+    s32i    a2,  a3, 0                  /* save nesting count              */
+    bnez    a2,  .Lnesting              /* !=0 after decr so still nested  */
+
+    #ifdef CONFIG_FREERTOS_FPU_IN_ISR 
+    #if XCHAL_CP_NUM > 0
+    l32i    a3,  sp, 0                  /* Grab last CPENABLE before leave ISR */
+    addi    sp,  sp, 4
+    wsr     a3, CPENABLE
+    rsync                               /* ensure CPENABLE was modified */
+    #endif
+    #endif
+
+    movi    a2,  pxCurrentTCB
+	addx4	a2,  a4, a2
+    l32i    a2,  a2, 0                  /* a2 = current TCB                */
+    beqz    a2,  1f                     /* no task ? go to dispatcher      */
+    l32i    a1,  a2, TOPOFSTACK_OFFS    /* SP = pxCurrentTCB->pxTopOfStack */
+
+    movi    a2,  port_switch_flag       /* address of switch flag          */
+	addx4	a2,  a4, a2					/* point to flag for this cpu      */
+    l32i    a3,  a2, 0                  /* a3 = port_switch_flag           */
+    beqz    a3,  .Lnoswitch             /* flag = 0 means no switch reqd   */
+    movi    a3,  0
+    s32i    a3,  a2, 0                  /* zero out the flag for next time */
+
+1:
+    /*
+    Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption.
+    However a12-13 were already saved by _frxt_int_enter().
+    */
+    #ifdef __XTENSA_CALL0_ABI__
+    s32i    a14, a1, XT_STK_A14
+    s32i    a15, a1, XT_STK_A15
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   vPortYieldFromInt       /* call dispatch inside the function; never returns */
+    #else
+    call4   vPortYieldFromInt       /* this one returns */
+    call0   _frxt_dispatch          /* tail-call dispatcher */
+    /* Never returns here. */
+    #endif
+
+.Lnoswitch:
+    /*
+    If we came here then about to resume the interrupted task.
+    */
+
+.Lnesting:
+    /*
+    We come here only if there was no context switch, that is if this
+    is a nested interrupt, or the interrupted task was not preempted.
+    In either case there's no need to load the SP.
+    */
+
+    /* Restore full context from interrupt stack frame */
+    call0   _xt_context_restore
+
+    /*
+    Must return via the exit dispatcher corresponding to the entrypoint from which
+    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
+    stack frame is deallocated in the exit dispatcher.
+    */
+    l32i    a0,  a1, XT_STK_EXIT
+    ret
+
+
+/*
+**********************************************************************************************************
+*                                           _frxt_timer_int
+*                                      void _frxt_timer_int(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS.
+* Called every timer interrupt.
+* Manages the tick timer and calls xPortSysTickHandler() every tick.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+* Callable from C (obeys ABI conventions). Implemented in assmebly code for performance.
+*
+**********************************************************************************************************
+*/
+    .globl  _frxt_timer_int
+    .type   _frxt_timer_int,@function
+    .align  4
+_frxt_timer_int:
+
+    /*
+    Xtensa timers work by comparing a cycle counter with a preset value.  Once the match occurs
+    an interrupt is generated, and the handler has to set a new cycle count into the comparator.
+    To avoid clock drift due to interrupt latency, the new cycle count is computed from the old,
+    not the time the interrupt was serviced. However if a timer interrupt is ever serviced more
+    than one tick late, it is necessary to process multiple ticks until the new cycle count is
+    in the future, otherwise the next timer interrupt would not occur until after the cycle
+    counter had wrapped (2^32 cycles later).
+
+    do {
+        ticks++;
+        old_ccompare = read_ccompare_i();
+        write_ccompare_i( old_ccompare + divisor );
+        service one tick;
+        diff = read_ccount() - old_ccompare;
+    } while ( diff > divisor );
+    */
+
+    ENTRY(16)
+
+    #ifdef CONFIG_PM_TRACE
+    movi a6, 1 /* = ESP_PM_TRACE_TICK */
+    getcoreid a7
+    call4 esp_pm_trace_enter
+    #endif // CONFIG_PM_TRACE
+
+.L_xt_timer_int_catchup:
+
+    /* Update the timer comparator for the next tick. */
+    #ifdef XT_CLOCK_FREQ
+    movi    a2, XT_TICK_DIVISOR         /* a2 = comparator increment          */
+    #else
+    movi    a3, _xt_tick_divisor
+    l32i    a2, a3, 0                   /* a2 = comparator increment          */
+    #endif
+    rsr     a3, XT_CCOMPARE             /* a3 = old comparator value          */
+    add     a4, a3, a2                  /* a4 = new comparator value          */
+    wsr     a4, XT_CCOMPARE             /* update comp. and clear interrupt   */
+    esync
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Preserve a2 and a3 across C calls. */
+    s32i    a2, sp, 4
+    s32i    a3, sp, 8
+    #endif
+
+    /* Call the FreeRTOS tick handler (see port.c). */
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   xPortSysTickHandler
+    #else
+    call4   xPortSysTickHandler
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Restore a2 and a3. */
+    l32i    a2, sp, 4
+    l32i    a3, sp, 8
+    #endif
+
+    /* Check if we need to process more ticks to catch up. */
+    esync                               /* ensure comparator update complete  */
+    rsr     a4, CCOUNT                  /* a4 = cycle count                   */
+    sub     a4, a4, a3                  /* diff = ccount - old comparator     */
+    blt     a2, a4, .L_xt_timer_int_catchup  /* repeat while diff > divisor */
+
+#ifdef CONFIG_PM_TRACE
+    movi a6, 1 /* = ESP_PM_TRACE_TICK */
+    getcoreid a7
+    call4 esp_pm_trace_exit
+#endif // CONFIG_PM_TRACE
+
+    RET(16)
+
+    /*
+**********************************************************************************************************
+*                                           _frxt_tick_timer_init
+*                                      void _frxt_tick_timer_init(void)
+*
+* Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called).
+* Callable from C (obeys ABI conventions on entry).
+*
+**********************************************************************************************************
+*/
+    .globl  _frxt_tick_timer_init
+    .type   _frxt_tick_timer_init,@function
+    .align  4
+_frxt_tick_timer_init:
+
+    ENTRY(16)
+
+
+    /* Set up the periodic tick timer (assume enough time to complete init). */
+    #ifdef XT_CLOCK_FREQ
+    movi    a3, XT_TICK_DIVISOR
+    #else
+    movi    a2, _xt_tick_divisor
+    l32i    a3, a2, 0
+    #endif
+    rsr     a2, CCOUNT              /* current cycle count */
+    add     a2, a2, a3              /* time of first timer interrupt */
+    wsr     a2, XT_CCOMPARE         /* set the comparator */
+
+    /*
+    Enable the timer interrupt at the device level. Don't write directly
+    to the INTENABLE register because it may be virtualized.
+    */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a2, XT_TIMER_INTEN
+    call0   xt_ints_on
+    #else
+    movi    a6, XT_TIMER_INTEN
+    call4   xt_ints_on
+    #endif
+
+    RET(16)
+
+/*
+**********************************************************************************************************
+*                                    DISPATCH THE HIGH READY TASK
+*                                     void _frxt_dispatch(void)
+*
+* Switch context to the highest priority ready task, restore its state and dispatch control to it.
+*
+* This is a common dispatcher that acts as a shared exit path for all the context switch functions
+* including vPortYield() and vPortYieldFromInt(), all of which tail-call this dispatcher
+* (for windowed ABI vPortYieldFromInt() calls it indirectly via _frxt_int_exit() ).
+*
+* The Xtensa port uses different stack frames for solicited and unsolicited task suspension (see
+* comments on stack frames in xtensa_context.h). This function restores the state accordingly.
+* If restoring a task that solicited entry, restores the minimal state and leaves CPENABLE clear.
+* If restoring a task that was preempted, restores all state including the task's CPENABLE.
+*
+* Entry:
+*   pxCurrentTCB  points to the TCB of the task to suspend,
+*   Because it is tail-called without a true function entrypoint, it needs no 'entry' instruction.
+*
+* Exit:
+*   If incoming task called vPortYield() (solicited), this function returns as if from vPortYield().
+*   If incoming task was preempted by an interrupt, this function jumps to exit dispatcher.
+*
+**********************************************************************************************************
+*/
+    .globl  _frxt_dispatch
+    .type   _frxt_dispatch,@function
+    .align  4
+_frxt_dispatch:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   vTaskSwitchContext  // Get next TCB to resume
+    movi    a2, pxCurrentTCB
+	getcoreid a3
+	addx4	a2,  a3, a2
+    #else
+    call4   vTaskSwitchContext  // Get next TCB to resume
+    movi    a2, pxCurrentTCB
+	getcoreid a3
+	addx4	a2,  a3, a2
+    #endif
+    l32i    a3,  a2, 0
+    l32i    sp,  a3, TOPOFSTACK_OFFS     /* SP = next_TCB->pxTopOfStack;  */
+    s32i    a3,  a2, 0
+
+    /* Determine the type of stack frame. */
+    l32i    a2,  sp, XT_STK_EXIT        /* exit dispatcher or solicited flag */
+    bnez    a2,  .L_frxt_dispatch_stk
+
+.L_frxt_dispatch_sol:
+
+    /* Solicited stack frame. Restore minimal context and return from vPortYield(). */
+    l32i    a3,  sp, XT_SOL_PS
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a12, sp, XT_SOL_A12
+    l32i    a13, sp, XT_SOL_A13
+    l32i    a14, sp, XT_SOL_A14
+    l32i    a15, sp, XT_SOL_A15
+    #endif
+    l32i    a0,  sp, XT_SOL_PC
+    #if XCHAL_CP_NUM > 0
+    /* Ensure wsr.CPENABLE is complete (should be, it was cleared on entry). */
+    rsync
+    #endif
+    /* As soons as PS is restored, interrupts can happen. No need to sync PS. */
+    wsr     a3,  PS
+    #ifdef __XTENSA_CALL0_ABI__
+    addi    sp,  sp, XT_SOL_FRMSZ
+    ret
+    #else
+    retw
+    #endif
+
+.L_frxt_dispatch_stk:
+
+    #if XCHAL_CP_NUM > 0
+    /* Restore CPENABLE from task's co-processor save area. */
+    movi    a3, pxCurrentTCB            /* cp_state =                       */
+	getcoreid a2
+	addx4	a3,  a2, a3
+    l32i    a3, a3, 0
+    l32i    a2, a3, CP_TOPOFSTACK_OFFS     /* StackType_t                       *pxStack; */
+    l16ui   a3, a2, XT_CPENABLE         /* CPENABLE = cp_state->cpenable;   */
+    wsr     a3, CPENABLE
+    #endif
+
+    /* Interrupt stack frame. Restore full context and return to exit dispatcher. */
+    call0   _xt_context_restore
+
+    /* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a14, sp, XT_STK_A14
+    l32i    a15, sp, XT_STK_A15
+    #endif
+
+    #if XCHAL_CP_NUM > 0
+    /* Ensure wsr.CPENABLE has completed. */
+    rsync
+    #endif
+
+    /*
+    Must return via the exit dispatcher corresponding to the entrypoint from which
+    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
+    stack frame is deallocated in the exit dispatcher.
+    */
+    l32i    a0, sp, XT_STK_EXIT
+    ret
+
+
+/*
+**********************************************************************************************************
+*                            PERFORM A SOLICTED CONTEXT SWITCH (from a task)
+*                                        void vPortYield(void)
+*
+* This function saves the minimal state needed for a solicited task suspension, clears CPENABLE,
+* then tail-calls the dispatcher _frxt_dispatch() to perform the actual context switch
+*
+* At Entry:
+*   pxCurrentTCB  points to the TCB of the task to suspend
+*   Callable from C (obeys ABI conventions on entry).
+*
+* Does not return to caller.
+*
+**********************************************************************************************************
+*/
+    .globl  vPortYield
+    .type   vPortYield,@function
+    .align  4
+vPortYield:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    addi    sp,  sp, -XT_SOL_FRMSZ
+    #else
+    entry   sp,  XT_SOL_FRMSZ
+    #endif
+
+    rsr     a2,  PS
+    s32i    a0,  sp, XT_SOL_PC
+    s32i    a2,  sp, XT_SOL_PS
+    #ifdef __XTENSA_CALL0_ABI__
+    s32i    a12, sp, XT_SOL_A12         /* save callee-saved registers      */
+    s32i    a13, sp, XT_SOL_A13
+    s32i    a14, sp, XT_SOL_A14
+    s32i    a15, sp, XT_SOL_A15
+    #else
+    /* Spill register windows. Calling xthal_window_spill() causes extra    */
+    /* spills and reloads, so we will set things up to call the _nw version */
+    /* instead to save cycles.                                              */
+    movi    a6,  ~(PS_WOE_MASK|PS_INTLEVEL_MASK)  /* spills a4-a7 if needed */
+    and     a2,  a2, a6                           /* clear WOE, INTLEVEL    */
+    addi    a2,  a2, XCHAL_EXCM_LEVEL             /* set INTLEVEL           */
+    wsr     a2,  PS
+    rsync
+    call0   xthal_window_spill_nw
+    l32i    a2,  sp, XT_SOL_PS                    /* restore PS             */
+    wsr     a2,  PS
+    #endif
+
+    rsil    a2,  XCHAL_EXCM_LEVEL       /* disable low/med interrupts       */
+
+    #if XCHAL_CP_NUM > 0
+    /* Save coprocessor callee-saved state (if any). At this point CPENABLE */
+    /* should still reflect which CPs were in use (enabled).                */
+    call0   _xt_coproc_savecs
+    #endif
+
+    movi    a2,  pxCurrentTCB
+	getcoreid a3
+	addx4	a2,  a3, a2
+    l32i    a2,  a2, 0                  /* a2 = pxCurrentTCB                */
+    movi    a3,  0
+    s32i    a3,  sp, XT_SOL_EXIT        /* 0 to flag as solicited frame     */
+    s32i    sp,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP  */
+
+    #if XCHAL_CP_NUM > 0
+    /* Clear CPENABLE, also in task's co-processor state save area. */
+    l32i    a2,  a2, CP_TOPOFSTACK_OFFS /* a2 = pxCurrentTCB->cp_state      */
+    movi    a3,  0
+    wsr     a3,  CPENABLE
+    beqz    a2,  1f
+    s16i    a3,  a2, XT_CPENABLE        /* clear saved cpenable             */
+1:
+    #endif
+
+    /* Tail-call dispatcher. */
+    call0   _frxt_dispatch
+    /* Never reaches here. */
+
+
+/*
+**********************************************************************************************************
+*                         PERFORM AN UNSOLICITED CONTEXT SWITCH (from an interrupt)
+*                                        void vPortYieldFromInt(void)
+*
+* This calls the context switch hook (removed), saves and clears CPENABLE, then tail-calls the dispatcher
+* _frxt_dispatch() to perform the actual context switch.
+*
+* At Entry:
+*   Interrupted task context has been saved in an interrupt stack frame at pxCurrentTCB->pxTopOfStack.
+*   pxCurrentTCB  points to the TCB of the task to suspend,
+*   Callable from C (obeys ABI conventions on entry).
+*
+* At Exit:
+*   Windowed ABI defers the actual context switch until the stack is unwound to interrupt entry.
+*   Call0 ABI tail-calls the dispatcher directly (no need to unwind) so does not return to caller.
+*
+**********************************************************************************************************
+*/
+    .globl  vPortYieldFromInt
+    .type   vPortYieldFromInt,@function
+    .align  4
+vPortYieldFromInt:
+
+    ENTRY(16)
+
+    #if XCHAL_CP_NUM > 0
+    /* Save CPENABLE in task's co-processor save area, and clear CPENABLE.  */
+    movi    a3, pxCurrentTCB            /* cp_state =                       */
+	getcoreid a2
+	addx4	a3,  a2, a3
+    l32i    a3, a3, 0
+
+    l32i    a2, a3, CP_TOPOFSTACK_OFFS
+
+    rsr     a3, CPENABLE
+    s16i    a3, a2, XT_CPENABLE         /* cp_state->cpenable = CPENABLE;   */
+    movi    a3, 0
+    wsr     a3, CPENABLE                /* disable all co-processors        */
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Tail-call dispatcher. */
+    call0   _frxt_dispatch
+    /* Never reaches here. */
+    #else
+    RET(16)
+    #endif
+
+/*
+**********************************************************************************************************
+*                                        _frxt_task_coproc_state
+*                                   void _frxt_task_coproc_state(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function for FreeRTOS.
+*
+* May only be called when a task is running, not within an interrupt handler (returns 0 in that case).
+* May only be called from assembly code by the 'call0' instruction. Does NOT obey ABI conventions.
+* Returns in A15 a pointer to the base of the co-processor state save area for the current task.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+**********************************************************************************************************
+*/
+#if XCHAL_CP_NUM > 0
+
+    .globl  _frxt_task_coproc_state
+    .type   _frxt_task_coproc_state,@function
+    .align  4
+_frxt_task_coproc_state:
+
+
+	/* We can use a3 as a scratchpad, the instances of code calling XT_RTOS_CP_STATE don't seem to need it saved. */
+	getcoreid a3
+    movi    a15, port_xSchedulerRunning /* if (port_xSchedulerRunning              */
+	addx4	a15, a3,a15
+    l32i    a15, a15, 0
+    beqz    a15, 1f
+    movi    a15, port_interruptNesting  /* && port_interruptNesting == 0           */
+	addx4	a15, a3, a15
+    l32i    a15, a15, 0
+    bnez    a15, 1f
+
+    movi    a15, pxCurrentTCB
+	addx4	a15, a3, a15
+    l32i    a15, a15, 0                 /* && pxCurrentTCB != 0) {                 */
+
+    beqz    a15, 2f
+    l32i    a15, a15, CP_TOPOFSTACK_OFFS
+    ret
+
+1:  movi    a15, 0
+2:  ret
+
+#endif /* XCHAL_CP_NUM > 0 */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h
new file mode 100644
index 0000000..4c2f9dc
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h
@@ -0,0 +1,113 @@
+/*
+ *  Copyright (C) 2016-2017 Espressif Shanghai PTE LTD
+ *  Copyright (C) 2015 Real Time Engineers Ltd.
+ *
+ *  All rights reserved
+ *
+ *  FreeRTOS is free software; you can redistribute it and/or modify it under
+ *  the terms of the GNU General Public License (version 2) as published by the
+ *  Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+ *
+ ***************************************************************************
+ *  >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+ *  >>!   distribute a combined work that includes FreeRTOS without being   !<<
+ *  >>!   obliged to provide the source code for proprietary components     !<<
+ *  >>!   outside of the FreeRTOS kernel.                                   !<<
+ ***************************************************************************
+ *
+ *  FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ *  WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ *  FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+ *  link: https://www.FreeRTOS.org/a00114.html
+ */
+
+/* This header exists for performance reasons, in order to inline the
+ * implementation of vPortCPUAcquireMutexIntsDisabled and
+ * vPortCPUReleaseMutexIntsDisabled into the
+ * vTaskEnterCritical/vTaskExitCritical functions in task.c as well as the
+ * vPortCPUAcquireMutex/vPortCPUReleaseMutex implementations.
+ *
+ * Normally this kind of performance hack is over the top, but
+ * vTaskEnterCritical/vTaskExitCritical is called a great
+ * deal by FreeRTOS internals.
+ *
+ * It should be #included by freertos port.c or tasks.c, in esp-idf.
+ *
+ * The way it works is that it essentially uses portmux_impl.inc.h as a
+ * generator template of sorts. When no external memory is used, this
+ * template is only used to generate the vPortCPUAcquireMutexIntsDisabledInternal
+ * and vPortCPUReleaseMutexIntsDisabledInternal functions, which use S32C1 to
+ * do an atomic compare & swap. When external memory is used the functions
+ * vPortCPUAcquireMutexIntsDisabledExtram and vPortCPUReleaseMutexIntsDisabledExtram
+ * are also generated, which use uxPortCompareSetExtram to fake the S32C1 instruction.
+ * The wrapper functions vPortCPUAcquireMutexIntsDisabled and
+ * vPortCPUReleaseMutexIntsDisabled will then use the appropriate function to do the
+ * actual lock/unlock.
+ */
+#include "soc/cpu.h"
+#include "portable.h"
+
+/* XOR one core ID with this value to get the other core ID */
+#define CORE_ID_XOR_SWAP    ( CORE_ID_PRO ^ CORE_ID_APP )
+
+
+
+/*Define the mux routines for use with muxes in internal RAM */
+#define PORTMUX_AQUIRE_MUX_FN_NAME     vPortCPUAcquireMutexIntsDisabledInternal
+#define PORTMUX_RELEASE_MUX_FN_NAME    vPortCPUReleaseMutexIntsDisabledInternal
+#define PORTMUX_COMPARE_SET_FN_NAME    uxPortCompareSet
+#include "portmux_impl.inc.h"
+#undef PORTMUX_AQUIRE_MUX_FN_NAME
+#undef PORTMUX_RELEASE_MUX_FN_NAME
+#undef PORTMUX_COMPARE_SET_FN_NAME
+
+
+#if defined( CONFIG_SPIRAM_SUPPORT )
+
+    #define PORTMUX_AQUIRE_MUX_FN_NAME     vPortCPUAcquireMutexIntsDisabledExtram
+    #define PORTMUX_RELEASE_MUX_FN_NAME    vPortCPUReleaseMutexIntsDisabledExtram
+    #define PORTMUX_COMPARE_SET_FN_NAME    uxPortCompareSetExtram
+    #include "portmux_impl.inc.h"
+    #undef PORTMUX_AQUIRE_MUX_FN_NAME
+    #undef PORTMUX_RELEASE_MUX_FN_NAME
+    #undef PORTMUX_COMPARE_SET_FN_NAME
+
+#endif
+
+
+#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+    #define PORTMUX_AQUIRE_MUX_FN_ARGS     portMUX_TYPE * mux, int timeout_cycles, const char * fnName, int line
+    #define PORTMUX_RELEASE_MUX_FN_ARGS    portMUX_TYPE * mux, const char * fnName, int line
+    #define PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( x )     x, timeout_cycles, fnName, line
+    #define PORTMUX_RELEASE_MUX_FN_CALL_ARGS( x )    x, fnName, line
+#else
+    #define PORTMUX_AQUIRE_MUX_FN_ARGS     portMUX_TYPE * mux, int timeout_cycles
+    #define PORTMUX_RELEASE_MUX_FN_ARGS    portMUX_TYPE * mux
+    #define PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( x )     x, timeout_cycles
+    #define PORTMUX_RELEASE_MUX_FN_CALL_ARGS( x )    x
+#endif
+
+
+static inline bool __attribute__( ( always_inline ) ) vPortCPUAcquireMutexIntsDisabled( PORTMUX_AQUIRE_MUX_FN_ARGS )
+{
+    #if defined( CONFIG_SPIRAM_SUPPORT )
+        if( esp_ptr_external_ram( mux ) )
+        {
+            return vPortCPUAcquireMutexIntsDisabledExtram( PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( mux ) );
+        }
+    #endif
+    return vPortCPUAcquireMutexIntsDisabledInternal( PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( mux ) );
+}
+
+
+static inline void vPortCPUReleaseMutexIntsDisabled( PORTMUX_RELEASE_MUX_FN_ARGS )
+{
+    #if defined( CONFIG_SPIRAM_SUPPORT )
+        if( esp_ptr_external_ram( mux ) )
+        {
+            vPortCPUReleaseMutexIntsDisabledExtram( PORTMUX_RELEASE_MUX_FN_CALL_ARGS( mux ) );
+            return;
+        }
+    #endif
+    vPortCPUReleaseMutexIntsDisabledInternal( PORTMUX_RELEASE_MUX_FN_CALL_ARGS( mux ) );
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h
new file mode 100644
index 0000000..e98d488
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h
@@ -0,0 +1,200 @@
+/*
+ *  Copyright (C) 2016-2017 Espressif Shanghai PTE LTD
+ *  Copyright (C) 2015 Real Time Engineers Ltd.
+ *
+ *  All rights reserved
+ *
+ *  FreeRTOS is free software; you can redistribute it and/or modify it under
+ *  the terms of the GNU General Public License (version 2) as published by the
+ *  Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+ *
+ ***************************************************************************
+ *  >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+ *  >>!   distribute a combined work that includes FreeRTOS without being   !<<
+ *  >>!   obliged to provide the source code for proprietary components     !<<
+ *  >>!   outside of the FreeRTOS kernel.                                   !<<
+ ***************************************************************************
+ *
+ *  FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ *  WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ *  FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+ *  link: https://www.FreeRTOS.org/a00114.html
+ */
+
+
+/*
+ * Warning: funky preprocessor hackery ahead. Including these headers will generate two
+ * functions, which names are defined by the preprocessor macros
+ * PORTMUX_AQUIRE_MUX_FN_NAME and PORTMUX_RELEASE_MUX_FN_NAME. In order to do the compare
+ * and exchange function, they will use whatever PORTMUX_COMPARE_SET_FN_NAME resolves to.
+ *
+ * In some scenarios, this header is included *twice* in portmux_impl.h: one time
+ * for the 'normal' mux code which uses a compare&exchange routine, another time
+ * to generate code for a second set of these routines that use a second mux
+ * (in internal ram) to fake a compare&exchange on a variable in external memory.
+ */
+
+
+
+static inline bool __attribute__( ( always_inline ) )
+#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+    PORTMUX_AQUIRE_MUX_FN_NAME( portMUX_TYPE * mux,
+                                int timeout_cycles,
+                                const char * fnName,
+                                int line )
+    {
+#else
+    PORTMUX_AQUIRE_MUX_FN_NAME( portMUX_TYPE * mux, int timeout_cycles )
+    {
+        #endif
+
+
+        #if !CONFIG_FREERTOS_UNICORE
+            uint32_t res;
+            portBASE_TYPE coreID, otherCoreID;
+            uint32_t ccount_start;
+            bool set_timeout = timeout_cycles > portMUX_NO_TIMEOUT;
+            #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                if( !set_timeout )
+                {
+                    timeout_cycles = 10000; /* Always set a timeout in debug mode */
+                    set_timeout = true;
+                }
+            #endif
+
+            if( set_timeout ) /* Timeout */
+            {
+                RSR( CCOUNT, ccount_start );
+            }
+
+            #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                uint32_t owner = mux->owner;
+
+                if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) )
+                {
+                    ets_printf( "ERROR: vPortCPUAcquireMutex: mux %p is uninitialized (0x%X)! Called from %s line %d.\n", mux, owner, fnName, line );
+                    mux->owner = portMUX_FREE_VAL;
+                }
+            #endif
+
+            /* Spin until we own the core */
+
+            RSR( PRID, coreID );
+
+            /* Note: coreID is the full 32 bit core ID (CORE_ID_PRO/CORE_ID_APP),
+             * not the 0/1 value returned by xPortGetCoreID()
+             */
+            otherCoreID = CORE_ID_XOR_SWAP ^ coreID;
+
+            do
+            {
+                /* mux->owner should be one of portMUX_FREE_VAL, CORE_ID_PRO,
+                 * CORE_ID_APP:
+                 *
+                 * - If portMUX_FREE_VAL, we want to atomically set to 'coreID'.
+                 * - If "our" coreID, we can drop through immediately.
+                 * - If "otherCoreID", we spin here.
+                 */
+                res = coreID;
+                PORTMUX_COMPARE_SET_FN_NAME( &mux->owner, portMUX_FREE_VAL, &res );
+
+                if( res != otherCoreID )
+                {
+                    break; /* mux->owner is "our" coreID */
+                }
+
+                if( set_timeout )
+                {
+                    uint32_t ccount_now;
+                    RSR( CCOUNT, ccount_now );
+
+                    if( ccount_now - ccount_start > ( unsigned ) timeout_cycles )
+                    {
+                        #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                            ets_printf( "Timeout on mux! last non-recursive lock %s line %d, curr %s line %d\n", mux->lastLockedFn, mux->lastLockedLine, fnName, line );
+                            ets_printf( "Owner 0x%x count %d\n", mux->owner, mux->count );
+                        #endif
+                        return false;
+                    }
+                }
+            } while( 1 );
+
+            assert( res == coreID || res == portMUX_FREE_VAL );           /* any other value implies memory corruption or uninitialized mux */
+            assert( ( res == portMUX_FREE_VAL ) == ( mux->count == 0 ) ); /* we're first to lock iff count is zero */
+            assert( mux->count < 0xFF );                                  /* Bad count value implies memory corruption */
+
+            /* now we own it, we can increment the refcount */
+            mux->count++;
+
+
+            #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                if( res == portMUX_FREE_VAL ) /*initial lock */
+                {
+                    mux->lastLockedFn = fnName;
+                    mux->lastLockedLine = line;
+                }
+                else
+                {
+                    ets_printf( "Recursive lock: count=%d last non-recursive lock %s line %d, curr %s line %d\n", mux->count - 1,
+                                mux->lastLockedFn, mux->lastLockedLine, fnName, line );
+                }
+            #endif /* CONFIG_FREERTOS_PORTMUX_DEBUG */
+        #endif /* CONFIG_FREERTOS_UNICORE */
+        return true;
+    }
+
+#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+        static inline void PORTMUX_RELEASE_MUX_FN_NAME( portMUX_TYPE * mux,
+                                                        const char * fnName,
+                                                        int line )
+        {
+#else
+        static inline void PORTMUX_RELEASE_MUX_FN_NAME( portMUX_TYPE * mux )
+        {
+            #endif
+
+
+            #if !CONFIG_FREERTOS_UNICORE
+                portBASE_TYPE coreID;
+                #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                    const char * lastLockedFn = mux->lastLockedFn;
+                    int lastLockedLine = mux->lastLockedLine;
+                    mux->lastLockedFn = fnName;
+                    mux->lastLockedLine = line;
+                    uint32_t owner = mux->owner;
+
+                    if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) )
+                    {
+                        ets_printf( "ERROR: vPortCPUReleaseMutex: mux %p is invalid (0x%x)!\n", mux, mux->owner );
+                    }
+                #endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
+
+                #if CONFIG_FREERTOS_PORTMUX_DEBUG || !defined( NDEBUG )
+                    RSR( PRID, coreID );
+                #endif
+
+                #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                    if( coreID != mux->owner )
+                    {
+                        ets_printf( "ERROR: vPortCPUReleaseMutex: mux %p was already unlocked!\n", mux );
+                        ets_printf( "Last non-recursive unlock %s line %d, curr unlock %s line %d\n", lastLockedFn, lastLockedLine, fnName, line );
+                    }
+                #endif
+
+                assert( coreID == mux->owner ); /* This is a mutex we didn't lock, or it's corrupt */
+
+                mux->count--;
+
+                if( mux->count == 0 )
+                {
+                    mux->owner = portMUX_FREE_VAL;
+                }
+                else
+                {
+                    assert( mux->count < 0x100 ); /* Indicates memory corruption */
+                    #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG_RECURSIVE
+                        ets_printf( "Recursive unlock: count=%d last locked %s line %d, curr %s line %d\n", mux->count, lastLockedFn, lastLockedLine, fnName, line );
+                    #endif
+                }
+            #endif //!CONFIG_FREERTOS_UNICORE
+        }
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S
new file mode 100644
index 0000000..fedf428
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S
@@ -0,0 +1,648 @@
+/*******************************************************************************
+Copyright (c) 2006-2015 Cadence Design Systems Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be included
+in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+--------------------------------------------------------------------------------
+
+        XTENSA CONTEXT SAVE AND RESTORE ROUTINES
+
+Low-level Call0 functions for handling generic context save and restore of
+registers not specifically addressed by the interrupt vectors and handlers.
+Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).
+Except for the calls to RTOS functions, this code is generic to Xtensa.
+
+Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-
+save regs (A12-A15), which is always the case if the handlers are coded in C.
+However A12, A13 are made available as scratch registers for interrupt dispatch
+code, so are presumed saved anyway, and are always restored even in Call0 ABI.
+Only A14, A15 are truly handled as callee-save regs.
+
+Because Xtensa is a configurable architecture, this port supports all user
+generated configurations (except restrictions stated in the release notes).
+This is accomplished by conditional compilation using macros and functions
+defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
+Only the processor state included in your configuration is saved and restored,
+including any processor state added by user configuration options or TIE.
+
+*******************************************************************************/
+
+/*  Warn nicely if this file gets named with a lowercase .s instead of .S:  */
+#define NOERROR #
+NOERROR: .error "C preprocessor needed for this file: make sure its filename\
+ ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option."
+
+
+#include "xtensa_rtos.h"
+#include "xtensa_context.h"
+
+#ifdef XT_USE_OVLY
+#include <xtensa/overlay_os_asm.h>
+#endif
+
+    .text
+
+
+
+/*******************************************************************************
+
+_xt_context_save
+
+    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
+
+Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the
+interrupt stack frame defined in xtensa_rtos.h.
+Its counterpart is _xt_context_restore (which also restores A12, A13).
+
+Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.
+This function preserves A12 & A13 in order to provide the caller with 2 scratch 
+regs that need not be saved over the call to this function. The choice of which
+2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw,
+to avoid moving data more than necessary. Caller can assign regs accordingly.
+
+Entry Conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    Original A12, A13 have already been saved in the interrupt stack frame.
+    Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the 
+    point of interruption.
+    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
+
+Exit conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    A12, A13 as at entry (preserved).
+    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
+
+*******************************************************************************/
+
+    .global _xt_context_save
+    .type   _xt_context_save,@function
+    .align  4
+	.literal_position
+    .align  4
+_xt_context_save:
+
+    s32i    a2,  sp, XT_STK_A2
+    s32i    a3,  sp, XT_STK_A3
+    s32i    a4,  sp, XT_STK_A4
+    s32i    a5,  sp, XT_STK_A5
+    s32i    a6,  sp, XT_STK_A6
+    s32i    a7,  sp, XT_STK_A7
+    s32i    a8,  sp, XT_STK_A8
+    s32i    a9,  sp, XT_STK_A9
+    s32i    a10, sp, XT_STK_A10
+    s32i    a11, sp, XT_STK_A11
+
+    /*
+    Call0 ABI callee-saved regs a12-15 do not need to be saved here.
+    a12-13 are the caller's responsibility so it can use them as scratch.
+    So only need to save a14-a15 here for Windowed ABI (not Call0).
+    */
+    #ifndef __XTENSA_CALL0_ABI__
+    s32i    a14, sp, XT_STK_A14
+    s32i    a15, sp, XT_STK_A15
+    #endif
+
+    rsr     a3,  SAR
+    s32i    a3,  sp, XT_STK_SAR
+
+    #if XCHAL_HAVE_LOOPS
+    rsr     a3,  LBEG
+    s32i    a3,  sp, XT_STK_LBEG
+    rsr     a3,  LEND
+    s32i    a3,  sp, XT_STK_LEND
+    rsr     a3,  LCOUNT
+    s32i    a3,  sp, XT_STK_LCOUNT
+    #endif
+
+    #ifdef XT_USE_SWPRI
+    /* Save virtual priority mask */
+    movi    a3,  _xt_vpri_mask
+    l32i    a3,  a3, 0
+    s32i    a3,  sp, XT_STK_VPRI
+    #endif
+
+    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
+    mov     a9,  a0                     /* preserve ret addr */
+    #endif
+
+    #ifndef __XTENSA_CALL0_ABI__
+    /*
+    To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15.
+    Need to save a9,12,13 temporarily (in frame temps) and recover originals.
+    Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow
+    and underflow exceptions disabled (assured by PS.EXCM == 1).
+    */
+    s32i    a12, sp, XT_STK_TMP0        /* temp. save stuff in stack frame */
+    s32i    a13, sp, XT_STK_TMP1    
+    s32i    a9,  sp, XT_STK_TMP2    
+
+    /*
+    Save the overlay state if we are supporting overlays. Since we just saved
+    three registers, we can conveniently use them here. Note that as of now,
+    overlays only work for windowed calling ABI.
+    */
+    #ifdef XT_USE_OVLY
+    l32i    a9,  sp, XT_STK_PC          /* recover saved PC */
+    _xt_overlay_get_state    a9, a12, a13
+    s32i    a9,  sp, XT_STK_OVLY        /* save overlay state */
+    #endif
+
+    l32i    a12, sp, XT_STK_A12         /* recover original a9,12,13 */
+    l32i    a13, sp, XT_STK_A13
+    l32i    a9,  sp, XT_STK_A9
+    addi    sp,  sp, XT_STK_FRMSZ       /* restore the interruptee's SP */
+    call0   xthal_window_spill_nw       /* preserves only a4,5,8,9,12,13 */
+    addi    sp,  sp, -XT_STK_FRMSZ
+    l32i    a12, sp, XT_STK_TMP0        /* recover stuff from stack frame */
+    l32i    a13, sp, XT_STK_TMP1    
+    l32i    a9,  sp, XT_STK_TMP2    
+    #endif
+
+    #if XCHAL_EXTRA_SA_SIZE > 0
+    /*  
+    NOTE: Normally the xthal_save_extra_nw macro only affects address
+    registers a2-a5. It is theoretically possible for Xtensa processor
+    designers to write TIE that causes more address registers to be
+    affected, but it is generally unlikely. If that ever happens,
+    more registers need to be saved/restored around this macro invocation.
+    Here we assume a9,12,13 are preserved.
+    Future Xtensa tools releases might limit the regs that can be affected.
+    */
+    addi    a2,  sp, XT_STK_EXTRA       /* where to save it */
+    # if XCHAL_EXTRA_SA_ALIGN > 16
+    movi    a3, -XCHAL_EXTRA_SA_ALIGN
+    and     a2, a2, a3                  /* align dynamically >16 bytes */
+    # endif
+    call0   xthal_save_extra_nw         /* destroys a0,2,3,4,5 */
+    #endif
+
+    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
+    mov     a0, a9                      /* retrieve ret addr */
+    #endif
+
+    ret
+
+/*******************************************************************************
+
+_xt_context_restore
+
+    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
+
+Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0
+ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt 
+stack frame defined in xtensa_rtos.h .
+Its counterpart is _xt_context_save (whose caller saved A12, A13).
+
+Caller is responsible to restore PC, PS, A0, A1 (SP).
+
+Entry Conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+
+Exit conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    Other processor state except PC, PS, A0, A1 (SP), is as at the point 
+    of interruption.
+
+*******************************************************************************/
+
+    .global _xt_context_restore
+    .type   _xt_context_restore,@function
+    .align  4
+	.literal_position
+    .align  4
+_xt_context_restore:
+
+    #if XCHAL_EXTRA_SA_SIZE > 0
+    /*  
+    NOTE: Normally the xthal_restore_extra_nw macro only affects address
+    registers a2-a5. It is theoretically possible for Xtensa processor
+    designers to write TIE that causes more address registers to be
+    affected, but it is generally unlikely. If that ever happens,
+    more registers need to be saved/restored around this macro invocation.
+    Here we only assume a13 is preserved.
+    Future Xtensa tools releases might limit the regs that can be affected.
+    */
+    mov     a13, a0                     /* preserve ret addr */
+    addi    a2,  sp, XT_STK_EXTRA       /* where to find it */
+    # if XCHAL_EXTRA_SA_ALIGN > 16
+    movi    a3, -XCHAL_EXTRA_SA_ALIGN
+    and     a2, a2, a3                  /* align dynamically >16 bytes */
+    # endif
+    call0   xthal_restore_extra_nw      /* destroys a0,2,3,4,5 */
+    mov     a0,  a13                    /* retrieve ret addr */
+    #endif
+
+    #if XCHAL_HAVE_LOOPS
+    l32i    a2,  sp, XT_STK_LBEG
+    l32i    a3,  sp, XT_STK_LEND
+    wsr     a2,  LBEG
+    l32i    a2,  sp, XT_STK_LCOUNT
+    wsr     a3,  LEND
+    wsr     a2,  LCOUNT
+    #endif
+
+    #ifdef XT_USE_OVLY
+    /*
+    If we are using overlays, this is a good spot to check if we need
+    to restore an overlay for the incoming task. Here we have a bunch
+    of registers to spare. Note that this step is going to use a few
+    bytes of storage below SP (SP-20 to SP-32) if an overlay is going
+    to be restored.
+    */
+    l32i    a2,  sp, XT_STK_PC          /* retrieve PC */
+    l32i    a3,  sp, XT_STK_PS          /* retrieve PS */
+    l32i    a4,  sp, XT_STK_OVLY        /* retrieve overlay state */
+    l32i    a5,  sp, XT_STK_A1          /* retrieve stack ptr */
+    _xt_overlay_check_map    a2, a3, a4, a5, a6
+    s32i    a2,  sp, XT_STK_PC          /* save updated PC */
+    s32i    a3,  sp, XT_STK_PS          /* save updated PS */
+    #endif
+
+    #ifdef XT_USE_SWPRI
+    /* Restore virtual interrupt priority and interrupt enable */
+    movi    a3,  _xt_intdata
+    l32i    a4,  a3, 0                  /* a4 = _xt_intenable */
+    l32i    a5,  sp, XT_STK_VPRI        /* a5 = saved _xt_vpri_mask */
+    and     a4,  a4, a5
+    wsr     a4,  INTENABLE              /* update INTENABLE */
+    s32i    a5,  a3, 4                  /* restore _xt_vpri_mask */
+    #endif
+
+    l32i    a3,  sp, XT_STK_SAR
+    l32i    a2,  sp, XT_STK_A2
+    wsr     a3,  SAR
+    l32i    a3,  sp, XT_STK_A3
+    l32i    a4,  sp, XT_STK_A4
+    l32i    a5,  sp, XT_STK_A5
+    l32i    a6,  sp, XT_STK_A6
+    l32i    a7,  sp, XT_STK_A7
+    l32i    a8,  sp, XT_STK_A8
+    l32i    a9,  sp, XT_STK_A9
+    l32i    a10, sp, XT_STK_A10
+    l32i    a11, sp, XT_STK_A11
+
+    /*
+    Call0 ABI callee-saved regs a12-15 do not need to be restored here.
+    However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(), 
+    so need to be restored anyway, despite being callee-saved in Call0.
+    */
+    l32i    a12, sp, XT_STK_A12
+    l32i    a13, sp, XT_STK_A13
+    #ifndef __XTENSA_CALL0_ABI__
+    l32i    a14, sp, XT_STK_A14
+    l32i    a15, sp, XT_STK_A15
+    #endif
+
+    ret
+
+
+/*******************************************************************************
+
+_xt_coproc_init
+
+Initializes global co-processor management data, setting all co-processors
+to "unowned". Leaves CPENABLE as it found it (does NOT clear it).
+
+Called during initialization of the RTOS, before any threads run.
+
+This may be called from normal Xtensa single-threaded application code which
+might use co-processors. The Xtensa run-time initialization enables all 
+co-processors. They must remain enabled here, else a co-processor exception
+might occur outside of a thread, which the exception handler doesn't expect.
+
+Entry Conditions:
+    Xtensa single-threaded run-time environment is in effect.
+    No thread is yet running.
+
+Exit conditions:
+    None.
+
+Obeys ABI conventions per prototype:
+    void _xt_coproc_init(void)
+
+*******************************************************************************/
+
+#if XCHAL_CP_NUM > 0
+
+    .global _xt_coproc_init
+    .type   _xt_coproc_init,@function
+    .align  4
+	.literal_position
+    .align  4
+_xt_coproc_init:
+    ENTRY0
+
+    /* Initialize thread co-processor ownerships to 0 (unowned). */
+    movi    a2, _xt_coproc_owner_sa         /* a2 = base of owner array */
+    addi    a3, a2, (XCHAL_CP_MAX*portNUM_PROCESSORS) << 2       /* a3 = top+1 of owner array */
+    movi    a4, 0                           /* a4 = 0 (unowned) */
+1:  s32i    a4, a2, 0
+    addi    a2, a2, 4
+    bltu    a2, a3, 1b
+
+    RET0
+
+#endif
+
+
+/*******************************************************************************
+
+_xt_coproc_release
+
+Releases any and all co-processors owned by a given thread. The thread is 
+identified by it's co-processor state save area defined in xtensa_context.h .
+
+Must be called before a thread's co-proc save area is deleted to avoid
+memory corruption when the exception handler tries to save the state.
+May be called when a thread terminates or completes but does not delete
+the co-proc save area, to avoid the exception handler having to save the 
+thread's co-proc state before another thread can use it (optimization).
+
+Needs to be called on the processor the thread was running on. Unpinned threads
+won't have an entry here because they get pinned as soon they use a coprocessor.
+
+Entry Conditions:
+    A2  = Pointer to base of co-processor state save area.
+
+Exit conditions:
+    None.
+
+Obeys ABI conventions per prototype:
+    void _xt_coproc_release(void * coproc_sa_base)
+
+*******************************************************************************/
+
+#if XCHAL_CP_NUM > 0
+
+    .global _xt_coproc_release
+    .type   _xt_coproc_release,@function
+    .align  4
+	.literal_position
+    .align  4
+_xt_coproc_release:
+    ENTRY0                                  /* a2 = base of save area */
+
+	getcoreid a5
+	movi    a3, XCHAL_CP_MAX << 2
+	mull    a5, a5, a3
+    movi    a3, _xt_coproc_owner_sa         /* a3 = base of owner array */
+	add     a3, a3, a5
+
+    addi    a4, a3, XCHAL_CP_MAX << 2       /* a4 = top+1 of owner array */
+    movi    a5, 0                           /* a5 = 0 (unowned) */
+
+    rsil    a6, XCHAL_EXCM_LEVEL            /* lock interrupts */
+
+1:  l32i    a7, a3, 0                       /* a7 = owner at a3 */
+    bne     a2, a7, 2f                      /* if (coproc_sa_base == owner) */
+    s32i    a5, a3, 0                       /*   owner = unowned */
+2:  addi    a3, a3, 1<<2                    /* a3 = next entry in owner array */
+    bltu    a3, a4, 1b                      /* repeat until end of array */
+
+3:  wsr     a6, PS                          /* restore interrupts */
+
+    RET0
+
+#endif
+
+
+/*******************************************************************************
+_xt_coproc_savecs
+
+If there is a current thread and it has a coprocessor state save area, then
+save all callee-saved state into this area. This function is called from the
+solicited context switch handler. It calls a system-specific function to get
+the coprocessor save area base address.
+
+Entry conditions:
+    - The thread being switched out is still the current thread.
+    - CPENABLE state reflects which coprocessors are active.
+    - Registers have been saved/spilled already.
+
+Exit conditions:
+    - All necessary CP callee-saved state has been saved.
+    - Registers a2-a7, a13-a15 have been trashed.
+
+Must be called from assembly code only, using CALL0.
+*******************************************************************************/
+#if XCHAL_CP_NUM > 0
+
+    .extern     _xt_coproc_sa_offset   /* external reference */
+
+    .global     _xt_coproc_savecs
+    .type       _xt_coproc_savecs,@function
+    .align  4
+	.literal_position
+    .align      4
+_xt_coproc_savecs:
+
+    /* At entry, CPENABLE should be showing which CPs are enabled. */
+
+    rsr     a2, CPENABLE                /* a2 = which CPs are enabled      */
+    beqz    a2, .Ldone                  /* quick exit if none              */
+    mov     a14, a0                     /* save return address             */
+    call0   XT_RTOS_CP_STATE            /* get address of CP save area     */
+    mov     a0, a14                     /* restore return address          */
+    beqz    a15, .Ldone                 /* if none then nothing to do      */
+    s16i    a2, a15, XT_CP_CS_ST        /* save mask of CPs being stored   */
+    movi    a13, _xt_coproc_sa_offset   /* array of CP save offsets        */
+    l32i    a15, a15, XT_CP_ASA         /* a15 = base of aligned save area */
+
+#if XCHAL_CP0_SA_SIZE
+    bbci.l  a2, 0, 2f                   /* CP 0 not enabled                */
+    l32i    a14, a13, 0                 /* a14 = _xt_coproc_sa_offset[0]   */
+    add     a3, a14, a15                /* a3 = save area for CP 0         */
+    xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP1_SA_SIZE
+    bbci.l  a2, 1, 2f                   /* CP 1 not enabled                */
+    l32i    a14, a13, 4                 /* a14 = _xt_coproc_sa_offset[1]   */
+    add     a3, a14, a15                /* a3 = save area for CP 1         */
+    xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP2_SA_SIZE
+    bbci.l  a2, 2, 2f
+    l32i    a14, a13, 8
+    add     a3, a14, a15
+    xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP3_SA_SIZE
+    bbci.l  a2, 3, 2f
+    l32i    a14, a13, 12
+    add     a3, a14, a15
+    xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP4_SA_SIZE
+    bbci.l  a2, 4, 2f
+    l32i    a14, a13, 16
+    add     a3, a14, a15
+    xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP5_SA_SIZE
+    bbci.l  a2, 5, 2f
+    l32i    a14, a13, 20
+    add     a3, a14, a15
+    xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP6_SA_SIZE
+    bbci.l  a2, 6, 2f
+    l32i    a14, a13, 24
+    add     a3, a14, a15
+    xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP7_SA_SIZE
+    bbci.l  a2, 7, 2f
+    l32i    a14, a13, 28
+    add     a3, a14, a15
+    xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+.Ldone:
+    ret
+#endif
+
+
+/*******************************************************************************
+_xt_coproc_restorecs
+
+Restore any callee-saved coprocessor state for the incoming thread.
+This function is called from coprocessor exception handling, when giving
+ownership to a thread that solicited a context switch earlier. It calls a
+system-specific function to get the coprocessor save area base address.
+
+Entry conditions:
+    - The incoming thread is set as the current thread.
+    - CPENABLE is set up correctly for all required coprocessors.
+    - a2 = mask of coprocessors to be restored.
+
+Exit conditions:
+    - All necessary CP callee-saved state has been restored.
+    - CPENABLE - unchanged.
+    - Registers a2-a7, a13-a15 have been trashed.
+
+Must be called from assembly code only, using CALL0.
+*******************************************************************************/
+#if XCHAL_CP_NUM > 0
+
+    .global     _xt_coproc_restorecs
+    .type       _xt_coproc_restorecs,@function
+    .align  4
+	.literal_position
+    .align      4
+_xt_coproc_restorecs:
+
+    mov     a14, a0                     /* save return address             */
+    call0   XT_RTOS_CP_STATE            /* get address of CP save area     */
+    mov     a0, a14                     /* restore return address          */
+    beqz    a15, .Ldone2                /* if none then nothing to do      */
+    l16ui   a3, a15, XT_CP_CS_ST        /* a3 = which CPs have been saved  */
+    xor     a3, a3, a2                  /* clear the ones being restored   */
+    s32i    a3, a15, XT_CP_CS_ST        /* update saved CP mask            */
+    movi    a13, _xt_coproc_sa_offset   /* array of CP save offsets        */
+    l32i    a15, a15, XT_CP_ASA         /* a15 = base of aligned save area */
+    
+#if XCHAL_CP0_SA_SIZE
+    bbci.l  a2, 0, 2f                   /* CP 0 not enabled                */
+    l32i    a14, a13, 0                 /* a14 = _xt_coproc_sa_offset[0]   */
+    add     a3, a14, a15                /* a3 = save area for CP 0         */
+    xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:  
+#endif
+
+#if XCHAL_CP1_SA_SIZE
+    bbci.l  a2, 1, 2f                   /* CP 1 not enabled                */
+    l32i    a14, a13, 4                 /* a14 = _xt_coproc_sa_offset[1]   */
+    add     a3, a14, a15                /* a3 = save area for CP 1         */
+    xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP2_SA_SIZE
+    bbci.l  a2, 2, 2f
+    l32i    a14, a13, 8
+    add     a3, a14, a15
+    xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP3_SA_SIZE
+    bbci.l  a2, 3, 2f
+    l32i    a14, a13, 12
+    add     a3, a14, a15
+    xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP4_SA_SIZE
+    bbci.l  a2, 4, 2f
+    l32i    a14, a13, 16
+    add     a3, a14, a15
+    xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP5_SA_SIZE
+    bbci.l  a2, 5, 2f
+    l32i    a14, a13, 20
+    add     a3, a14, a15
+    xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP6_SA_SIZE
+    bbci.l  a2, 6, 2f
+    l32i    a14, a13, 24
+    add     a3, a14, a15
+    xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP7_SA_SIZE
+    bbci.l  a2, 7, 2f
+    l32i    a14, a13, 28
+    add     a3, a14, a15
+    xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+.Ldone2:
+    ret
+
+#endif
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c
new file mode 100644
index 0000000..2bf1da7
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c
@@ -0,0 +1,58 @@
+/*******************************************************************************
+*  // Copyright (c) 2003-2015 Cadence Design Systems, Inc.
+*  //
+*  // Permission is hereby granted, free of charge, to any person obtaining
+*  // a copy of this software and associated documentation files (the
+*  // "Software"), to deal in the Software without restriction, including
+*  // without limitation the rights to use, copy, modify, merge, publish,
+*  // distribute, sublicense, and/or sell copies of the Software, and to
+*  // permit persons to whom the Software is furnished to do so, subject to
+*  // the following conditions:
+*  //
+*  // The above copyright notice and this permission notice shall be included
+*  // in all copies or substantial portions of the Software.
+*  //
+*  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+*  // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+*  // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+*  // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+*  // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+*  // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+*  // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*  --------------------------------------------------------------------------------
+*
+*       XTENSA INITIALIZATION ROUTINES CODED IN C
+*
+*  This file contains miscellaneous Xtensa RTOS-generic initialization functions
+*  that are implemented in C.
+*
+*******************************************************************************/
+
+
+#ifdef XT_BOARD
+    #include    <xtensa/xtbsp.h>
+#endif
+
+#include    "xtensa_rtos.h"
+#if CONFIG_IDF_TARGET_ESP32S2
+#include    "esp32s2/clk.h"
+#elif CONFIG_IDF_TARGET_ESP32
+#include    "esp32/clk.h"
+#endif
+
+#ifdef XT_RTOS_TIMER_INT
+
+    unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */
+
+    void _xt_tick_divisor_init( void )
+    {
+        _xt_tick_divisor = esp_clk_cpu_freq() / XT_TICK_PER_SEC;
+    }
+
+/* Deprecated, to be removed */
+    int xt_clock_freq( void )
+    {
+        return esp_clk_cpu_freq();
+    }
+
+#endif /* XT_RTOS_TIMER_INT */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c
new file mode 100644
index 0000000..93e4160
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c
@@ -0,0 +1,178 @@
+/*******************************************************************************
+ * Copyright (c) 2006-2015 Cadence Design Systems Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+*  Xtensa-specific interrupt and exception functions for RTOS ports.
+*  Also see xtensa_intr_asm.S.
+******************************************************************************/
+
+#include <stdlib.h>
+
+#include <xtensa/config/core.h>
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/xtensa_api.h"
+#include "freertos/portable.h"
+
+#if CONFIG_IDF_TARGET_ESP32S2
+#include "esp32s2/rom/ets_sys.h"
+#elif CONFIG_IDF_TARGET_ESP32
+#include "esp32/rom/ets_sys.h"
+#endif
+
+#if XCHAL_HAVE_EXCEPTIONS
+
+/* Handler table is in xtensa_intr_asm.S */
+
+    extern xt_exc_handler _xt_exception_table[ XCHAL_EXCCAUSE_NUM * portNUM_PROCESSORS ];
+
+
+/*
+ * Default handler for unhandled exceptions.
+ * CHANGED: We do this in panic.c now
+ */
+
+/*void xt_unhandled_exception(XtExcFrame *frame) */
+/*{ */
+    /*exit(-1); */
+/*} */
+    extern void xt_unhandled_exception( XtExcFrame * frame );
+
+
+/*
+ * This function registers a handler for the specified exception.
+ * The function returns the address of the previous handler.
+ * On error, it returns 0.
+ */
+    xt_exc_handler xt_set_exception_handler( int n,
+                                             xt_exc_handler f )
+    {
+        xt_exc_handler old;
+
+        if( ( n < 0 ) || ( n >= XCHAL_EXCCAUSE_NUM ) )
+        {
+            return 0; /* invalid exception number */
+        }
+
+        /* Convert exception number to _xt_exception_table name */
+        n = n * portNUM_PROCESSORS + xPortGetCoreID();
+        old = _xt_exception_table[ n ];
+
+        if( f )
+        {
+            _xt_exception_table[ n ] = f;
+        }
+        else
+        {
+            _xt_exception_table[ n ] = &xt_unhandled_exception;
+        }
+
+        return( ( old == &xt_unhandled_exception ) ? 0 : old );
+    }
+
+#endif /* if XCHAL_HAVE_EXCEPTIONS */
+
+#if XCHAL_HAVE_INTERRUPTS
+
+/* Handler table is in xtensa_intr_asm.S */
+
+    typedef struct xt_handler_table_entry
+    {
+        void * handler;
+        void * arg;
+    } xt_handler_table_entry;
+
+    extern xt_handler_table_entry _xt_interrupt_table[ XCHAL_NUM_INTERRUPTS * portNUM_PROCESSORS ];
+
+
+/*
+ * Default handler for unhandled interrupts.
+ */
+    void xt_unhandled_interrupt( void * arg )
+    {
+        ets_printf( "Unhandled interrupt %d on cpu %d!\n", ( int ) arg, xPortGetCoreID() );
+    }
+
+
+/*
+ * This function registers a handler for the specified interrupt. The "arg"
+ * parameter specifies the argument to be passed to the handler when it is
+ * invoked. The function returns the address of the previous handler.
+ * On error, it returns 0.
+ */
+    xt_handler xt_set_interrupt_handler( int n,
+                                         xt_handler f,
+                                         void * arg )
+    {
+        xt_handler_table_entry * entry;
+        xt_handler old;
+
+        if( ( n < 0 ) || ( n >= XCHAL_NUM_INTERRUPTS ) )
+        {
+            return 0; /* invalid interrupt number */
+        }
+
+        if( Xthal_intlevel[ n ] > XCHAL_EXCM_LEVEL )
+        {
+            return 0; /* priority level too high to safely handle in C */
+        }
+
+        /* Convert exception number to _xt_exception_table name */
+        n = n * portNUM_PROCESSORS + xPortGetCoreID();
+
+        entry = _xt_interrupt_table + n;
+        old = entry->handler;
+
+        if( f )
+        {
+            entry->handler = f;
+            entry->arg = arg;
+        }
+        else
+        {
+            entry->handler = &xt_unhandled_interrupt;
+            entry->arg = ( void * ) n;
+        }
+
+        return( ( old == &xt_unhandled_interrupt ) ? 0 : old );
+    }
+
+    #if CONFIG_SYSVIEW_ENABLE
+        void * xt_get_interrupt_handler_arg( int n )
+        {
+            xt_handler_table_entry * entry;
+
+            if( ( n < 0 ) || ( n >= XCHAL_NUM_INTERRUPTS ) )
+            {
+                return 0; /* invalid interrupt number */
+            }
+
+            /* Convert exception number to _xt_exception_table name */
+            n = n * portNUM_PROCESSORS + xPortGetCoreID();
+
+            entry = _xt_interrupt_table + n;
+            return entry->arg;
+        }
+    #endif /* if CONFIG_SYSVIEW_ENABLE */
+
+#endif /* XCHAL_HAVE_INTERRUPTS */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr_asm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr_asm.S
new file mode 100644
index 0000000..ddfe4ba
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr_asm.S
@@ -0,0 +1,225 @@
+/*******************************************************************************
+Copyright (c) 2006-2015 Cadence Design Systems Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be included
+in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+******************************************************************************/
+
+/******************************************************************************
+  Xtensa interrupt handling data and assembly routines.
+  Also see xtensa_intr.c and xtensa_vectors.S.
+******************************************************************************/
+
+#include <xtensa/hal.h>
+#include <xtensa/config/core.h>
+
+#include "xtensa_context.h"
+#include "FreeRTOSConfig.h"
+
+#if XCHAL_HAVE_INTERRUPTS
+
+/*
+-------------------------------------------------------------------------------
+  INTENABLE virtualization information.
+-------------------------------------------------------------------------------
+*/
+
+
+#if XT_USE_SWPRI
+/* Warning - this is not multicore-compatible. */
+    .data
+    .global _xt_intdata
+    .align  8
+_xt_intdata:
+    .global _xt_intenable
+    .type   _xt_intenable,@object
+    .size   _xt_intenable,4
+    .global _xt_vpri_mask
+    .type   _xt_vpri_mask,@object
+    .size   _xt_vpri_mask,4
+
+_xt_intenable:     .word   0             /* Virtual INTENABLE     */
+_xt_vpri_mask:     .word   0xFFFFFFFF    /* Virtual priority mask */
+#endif
+
+/*
+-------------------------------------------------------------------------------
+  Table of C-callable interrupt handlers for each interrupt. Note that not all
+  slots can be filled, because interrupts at level > EXCM_LEVEL will not be
+  dispatched to a C handler by default.
+
+  Stored as:
+  int 0 cpu 0
+  int 0 cpu 1
+  ...
+  int 0 cpu n
+  int 1 cpu 0
+  int 1 cpu 1
+  etc
+-------------------------------------------------------------------------------
+*/
+
+    .data
+    .global _xt_interrupt_table
+    .align  8
+
+_xt_interrupt_table:
+
+    .set    i, 0
+    .rept   XCHAL_NUM_INTERRUPTS*portNUM_PROCESSORS
+    .word   xt_unhandled_interrupt      /* handler address               */
+    .word   i                           /* handler arg (default: intnum) */
+    .set    i, i+1
+    .endr
+
+#endif /* XCHAL_HAVE_INTERRUPTS */
+
+
+#if XCHAL_HAVE_EXCEPTIONS
+
+/*
+-------------------------------------------------------------------------------
+  Table of C-callable exception handlers for each exception. Note that not all
+  slots will be active, because some exceptions (e.g. coprocessor exceptions)
+  are always handled by the OS and cannot be hooked by user handlers.
+
+  Stored as:
+  exc 0 cpu 0
+  exc 0 cpu 1
+  ...
+  exc 0 cpu n
+  exc 1 cpu 0
+  exc 1 cpu 1
+  etc
+-------------------------------------------------------------------------------
+*/
+
+    .data
+    .global _xt_exception_table
+    .align  4
+
+_xt_exception_table:
+    .rept   XCHAL_EXCCAUSE_NUM * portNUM_PROCESSORS
+    .word   xt_unhandled_exception    /* handler address */
+    .endr
+
+#endif
+
+
+/*
+-------------------------------------------------------------------------------
+  unsigned int xt_ints_on ( unsigned int mask )
+
+  Enables a set of interrupts. Does not simply set INTENABLE directly, but
+  computes it as a function of the current virtual priority if XT_USE_SWPRI is
+  enabled.
+  Can be called from interrupt handlers.
+-------------------------------------------------------------------------------
+*/
+
+    .text
+    .align  4
+    .global xt_ints_on
+    .type   xt_ints_on,@function
+
+xt_ints_on:
+
+    ENTRY0
+
+#if XCHAL_HAVE_INTERRUPTS
+#if XT_USE_SWPRI
+    movi    a3, 0
+    movi    a4, _xt_intdata
+    xsr     a3, INTENABLE        /* Disables all interrupts   */
+    rsync
+    l32i    a3, a4, 0            /* a3 = _xt_intenable        */
+    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask        */
+    or      a5, a3, a2           /* a5 = _xt_intenable | mask */
+    s32i    a5, a4, 0            /* _xt_intenable |= mask     */
+    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
+    wsr     a5, INTENABLE        /* Reenable interrupts       */
+    mov     a2, a3               /* Previous mask             */
+#else
+    movi    a3, 0
+    xsr     a3, INTENABLE        /* Disables all interrupts   */
+    rsync
+    or      a2, a3, a2           /* set bits in mask */
+    wsr     a2, INTENABLE        /* Re-enable ints */
+    rsync
+    mov     a2, a3               /* return prev mask */
+#endif
+#else
+    movi    a2, 0                /* Return zero */
+#endif
+    RET0
+
+    .size   xt_ints_on, . - xt_ints_on
+
+
+/*
+-------------------------------------------------------------------------------
+  unsigned int xt_ints_off ( unsigned int mask )
+
+  Disables a set of interrupts. Does not simply set INTENABLE directly,
+  but computes it as a function of the current virtual priority if XT_USE_SWPRI is
+  enabled.
+  Can be called from interrupt handlers.
+-------------------------------------------------------------------------------
+*/
+
+    .text
+    .align  4
+    .global xt_ints_off
+    .type   xt_ints_off,@function
+
+xt_ints_off:
+
+    ENTRY0
+#if XCHAL_HAVE_INTERRUPTS
+#if XT_USE_SWPRI
+    movi    a3, 0
+    movi    a4, _xt_intdata
+    xsr     a3, INTENABLE        /* Disables all interrupts    */
+    rsync
+    l32i    a3, a4, 0            /* a3 = _xt_intenable         */
+    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask         */
+    or      a5, a3, a2           /* a5 = _xt_intenable | mask  */
+    xor     a5, a5, a2           /* a5 = _xt_intenable & ~mask */
+    s32i    a5, a4, 0            /* _xt_intenable &= ~mask     */
+    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
+    wsr     a5, INTENABLE        /* Reenable interrupts        */
+    mov     a2, a3               /* Previous mask              */
+#else
+    movi    a4, 0
+    xsr     a4, INTENABLE        /* Disables all interrupts   */
+    rsync
+    or      a3, a4, a2           /* set bits in mask */
+    xor     a3, a3, a2           /* invert bits in mask set in mask, essentially clearing them */
+    wsr     a3, INTENABLE        /* Re-enable ints */
+    rsync
+    mov     a2, a4               /* return prev mask */
+#endif
+#else
+    movi    a2, 0                /* return zero */
+#endif
+    RET0
+
+    .size   xt_ints_off, . - xt_ints_off
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_loadstore_handler.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_loadstore_handler.S
new file mode 100644
index 0000000..32d7a8a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_loadstore_handler.S
@@ -0,0 +1,559 @@
+/*
+ Copyright 2019 Espressif Systems (Shanghai) PTE LTD
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+     http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ *  LoadStoreErrorCause:     Occurs when trying to access 32 bit addressable memory region as 8 bit or 16 bit
+ *  LoadStoreAlignmentCause: Occurs when trying to access in an unaligned manner
+ *
+ *          xxxx xxxx = imm8 field
+ *               yyyy = imm4 field
+ *               ssss = s field
+ *               tttt = t field
+ *
+ *                            16                0
+ *                            -------------------
+ *          L32I.N            yyyy ssss tttt 1000
+ *          S32I.N            yyyy ssss tttt 1001
+ *
+ *                  23                          0
+ *                  -----------------------------
+ *          L8UI    xxxx xxxx 0000 ssss tttt 0010               <- LoadStoreError
+ *          L16UI   xxxx xxxx 0001 ssss tttt 0010               <- LoadStoreError, LoadStoreAlignment
+ *          L16SI   xxxx xxxx 1001 ssss tttt 0010               <- LoadStoreError, LoadStoreAlignment
+ *          L32I    xxxx xxxx 0010 ssss tttt 0010               <- LoadStoreAlignment
+ *
+ *          S8I     xxxx xxxx 0100 ssss tttt 0010               <- LoadStoreError
+ *          S16I    xxxx xxxx 0101 ssss tttt 0010               <- LoadStoreError, LoadStoreAlignment
+ *          S32I    xxxx xxxx 0110 ssss tttt 0010               <- LoadStoreAlignment
+ *
+ *                   ******* UNSUPPORTED *******
+ *
+ *          L32E    0000 1001 rrrr ssss tttt 0000
+ *          S32E    0100 1001 rrrr ssss tttt 0000
+ *                  -----------------------------
+ */
+
+#include "xtensa_rtos.h"
+#include "sdkconfig.h"
+#include "soc/soc.h"
+
+#define LOADSTORE_HANDLER_STACK_SZ      8
+    .section .bss, "aw"
+    .balign 16
+LoadStoreHandlerStack:
+    .rept LOADSTORE_HANDLER_STACK_SZ
+    .word 0
+    .endr
+
+
+/* LoadStoreErrorCause handler:
+ *
+ * Completes 8-bit or 16-bit load/store instructions from 32-bit aligned memory region
+ * Called from UserExceptionVector if EXCCAUSE is LoadStoreErrorCause
+ */
+
+    .global   LoadStoreErrorHandler
+    .section .iram1, "ax"
+
+    .literal_position
+
+    .balign 4
+LoadStoreErrorHandler:
+    .type   LoadStoreErrorHandler, @function
+
+    wsr     a0, depc                            // Save return address in depc
+    mov     a0, sp
+    movi    sp, LoadStoreHandlerStack
+    s32i    a0, sp, 0x04                        // Since a0 contains value of a1
+    s32i    a2, sp, 0x08
+    s32i    a3, sp, 0x0c
+    s32i    a4, sp, 0x10
+
+    rsr     a0, sar                             // Save SAR in a0 to restore later
+
+    /* Check whether the address lies in the valid range */
+    rsr     a3, excvaddr
+    movi    a4, _iram_text_end                  // End of code section of IRAM
+    bge     a3, a4, 1f
+    movi    a4, SOC_CACHE_APP_LOW               // Check if in APP cache region
+    blt     a3, a4, .LS_wrong_opcode
+    movi    a4, SOC_CACHE_APP_HIGH
+    bge     a3, a4, .LS_wrong_opcode
+    j       2f
+
+1:
+    movi    a4, SOC_IRAM_HIGH                   // End of IRAM address range
+    bge     a3, a4, .LS_wrong_opcode
+
+2:
+    /* Examine the opcode which generated the exception */
+    /* Note: Instructions are in this order to avoid pipeline stalls. */
+    rsr     a2, epc1
+    movi    a4, ~3
+    ssa8l   a2                                  // sar is now correct shift for aligned read
+    and     a2, a2, a4                          // a2 now 4-byte aligned address of instruction
+    l32i    a4, a2, 0
+    l32i    a2, a2, 4
+
+    src     a2, a2, a4                          // a2 now instruction that failed
+    bbci    a2, 1, .LS_wrong_opcode
+    bbsi    a2, 14, .LSE_store_op               // Store instruction
+
+    /* l8/l16ui/l16si */
+    movi    a4, ~3
+    and     a4, a3, a4                          // a4 now word aligned read address
+
+    ssa8l   a3                                  // sar is now shift to extract a3's byte
+    l32i    a4, a4, 0                           // perform the actual read
+    srl     a4, a4                              // shift right correct distance
+    extui   a3, a2, 12, 4
+    bnez    a3, 1f                              // l16ui/l16si
+    extui   a4, a4, 0, 8                        // mask off bits needed for an l8
+    j       2f
+
+1:
+    extui   a4, a4, 0, 16
+    bbci    a2, 15, 2f                          // l16ui
+
+    /* Sign adjustment */
+    slli    a4, a4, 16
+    srai    a4, a4, 16                          // a4 contains the value
+
+2:
+    /* a4 contains the value */
+    rsr     a3, epc1
+    addi    a3, a3, 3
+    wsr     a3, epc1
+    wsr     a0, sar
+    rsr     a0, excsave1
+
+    extui   a2, a2, 3, 5
+    blti    a2, 10, .LSE_stack_reg
+
+    movi    a3, .LS_jumptable_base
+    addx8   a2, a2, a3                          // a2 is now the address to jump to
+    l32i    a3, sp, 0x0c
+    jx      a2
+
+.LSE_stack_reg:
+    addx2   a2, a2, sp
+    s32i    a4, a2, 0
+
+    /* Restore all values */
+    l32i    a4, sp, 0x10
+    l32i    a3, sp, 0x0c
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+.LSE_store_op:
+    s32i    a5, a1, 0x14
+    s32i    a6, a1, 0x18
+
+    /* a2 -> instruction that caused the error */
+    /* a3 -> unaligned address */
+    extui   a4, a2, 4, 4
+    blti    a4, 7, 1f
+    movi    a5, .LSE_store_reg
+    addx8   a5, a4, a5
+    jx      a5
+
+1:
+    addx4   a4, a4, sp
+    l32i    a4, a4, 0
+
+.LSE_store_data:
+    /* a4 contains the value */
+    rsr     a6, epc1
+    addi    a6, a6, 3
+    wsr     a6, epc1
+
+    ssa8b   a3
+    movi    a5, -1
+    bbsi    a2, 12, 1f                          // s16
+    extui   a4, a4, 0, 8
+    movi    a6, 0xff
+    j       2f
+1:
+    extui   a4, a4, 0, 16
+    movi    a6, 0xffff
+2:
+    sll     a4, a4                              // shift the value to proper offset
+    sll     a6, a6
+    xor     a5, a5, a6                          // a5 contains the mask
+
+    movi    a6, ~3
+    and     a3, a3, a6                          // a3 has the aligned address
+    l32i    a6, a3, 0                           // a6 contains the data at the aligned address
+    and     a6, a6, a5
+    or      a4, a6, a4
+    s32i    a4, a3, 0
+
+    /* Restore registers */
+    wsr     a0, sar
+
+    l32i    a6, sp, 0x18
+    l32i    a5, sp, 0x14
+    l32i    a4, sp, 0x10
+    l32i    a3, sp, 0x0c
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rsr     a0, excsave1
+
+    rfe
+
+.LSE_store_reg:
+    .org .LSE_store_reg + (7 * 8)
+    mov     a4, a7
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (8 * 8)
+    mov     a4, a8
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (9 * 8)
+    mov     a4, a9
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (10 * 8)
+    mov     a4, a10
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (11 * 8)
+    mov     a4, a11
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (12 * 8)
+    mov     a4, a12
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (13 * 8)
+    mov     a4, a13
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (14 * 8)
+    mov     a4, a14
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (15 * 8)
+    mov     a4, a15
+    j .LSE_store_data
+
+
+/* LoadStoreAlignmentCause handler:
+ *
+ * Completes unaligned 16-bit and 32-bit load/store instructions from 32-bit aligned memory region
+ * Called from UserExceptionVector if EXCCAUSE is LoadStoreAlignmentCause
+ */
+
+    .global   AlignmentErrorHandler
+    .section .iram1, "ax"
+
+    .literal_position
+
+    .balign 4
+AlignmentErrorHandler:
+    .type   AlignmentErrorHandler, @function
+
+    wsr     a0, depc                            // Save return address in depc
+    mov     a0, sp
+    movi    sp, LoadStoreHandlerStack
+    s32i    a0, sp, 0x04                        // Since a0 contains value of a1
+    s32i    a2, sp, 0x08
+    s32i    a3, sp, 0x0c
+    s32i    a4, sp, 0x10
+
+    rsr     a0, sar                             // Save SAR in a0 to restore later
+
+    /* Check whether the address lies in the valid range */
+    rsr     a3, excvaddr
+    movi    a4, _iram_text_end                  // End of code section of IRAM
+    bge     a3, a4, 1f
+    movi    a4, SOC_CACHE_APP_LOW               // Check if in APP cache region
+    blt     a3, a4, .LS_wrong_opcode
+    movi    a4, SOC_CACHE_APP_HIGH
+    bge     a3, a4, .LS_wrong_opcode
+    j       2f
+
+1:
+    movi    a4, SOC_IRAM_HIGH                   // End of IRAM address range
+    bge     a3, a4, .LS_wrong_opcode
+
+2:
+    /* Examine the opcode which generated the exception */
+    /* Note: Instructions are in this order to avoid pipeline stalls. */
+    rsr     a2, epc1
+    movi    a4, ~3
+    ssa8l   a2                                  // sar is now correct shift for aligned read
+    and     a2, a2, a4                          // a2 now 4-byte aligned address of instruction
+    l32i    a4, a2, 0
+    l32i    a2, a2, 4
+
+    /* a2 has the instruction that caused the error */
+    src     a2, a2, a4
+    extui   a4, a2, 0, 4
+    addi    a4, a4, -9
+    beqz    a4, .LSA_store_op
+    bbsi    a2, 14, .LSA_store_op
+
+    ssa8l   a3                                  // a3 contains the unaligned address
+    movi    a4, ~3
+    and     a4, a3, a4                          // a4 has the aligned address
+    l32i    a3, a4, 0
+    l32i    a4, a4, 4
+    src     a4, a4, a3
+
+    rsr     a3, epc1
+    addi    a3, a3, 2
+    bbsi    a2, 3, 1f                           // l32i.n
+    bbci    a2, 1, .LS_wrong_opcode
+    addi    a3, a3, 1
+
+    bbsi    a2, 13, 1f                          // l32
+    extui   a4, a4, 0, 16
+    bbci    a2, 15, 1f                          // l16ui
+
+    /* Sign adjustment */
+    slli    a4, a4, 16
+    srai    a4, a4, 16                          // a4 contains the value
+
+1:
+    wsr     a3, epc1
+    wsr     a0, sar
+    rsr     a0, excsave1
+
+    extui   a2, a2, 4, 4
+    blti    a2, 5, .LSA_stack_reg               // a3 contains the target register
+
+    movi    a3, .LS_jumptable_base
+    slli    a2, a2, 4
+    add     a2, a2, a3                          // a2 is now the address to jump to
+    l32i    a3, sp, 0x0c
+    jx      a2
+
+.LSA_stack_reg:
+    addx4   a2, a2, sp
+    s32i    a4, a2, 0
+
+    /* Restore all values */
+    l32i    a4, sp, 0x10
+    l32i    a3, sp, 0x0c
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+/* Store instruction */
+.LSA_store_op:
+    s32i    a5, sp, 0x14
+    s32i    a6, sp, 0x18
+    s32i    a7, sp, 0x1c
+
+    /* a2 -> instruction that caused the error */
+    /* a3 -> unaligned address */
+    extui   a4, a2, 4, 4
+    blti    a4, 8, 1f
+    movi    a5, .LSA_store_reg
+    addx8   a5, a4, a5
+    jx      a5
+
+1:
+    addx4   a4, a4, sp
+    l32i    a4, a4, 0                           // a4 contains the value
+
+.LSA_store_data:
+    movi    a6, 0
+
+    rsr     a7, epc1
+    addi    a7, a7 ,2
+    bbsi    a2, 3, 1f                           // s32i.n
+    bbci    a2, 1, .LS_wrong_opcode
+
+    addi    a7, a7, 1
+    bbsi    a2, 13, 1f                          // s32i
+
+    movi    a5, -1
+    extui   a4, a4, 0, 16
+    slli    a6, a5, 16                          // 0xffff0000
+
+1:
+    wsr     a7, epc1
+    movi    a5, ~3
+    and     a5, a3, a5                          // a5 has the aligned address
+
+    ssa8b   a3
+    movi    a3, -1
+    src     a7, a6, a3
+    src     a3, a3, a6
+
+    /* Store data on lower address */
+    l32i    a6, a5, 0
+    and     a6, a6, a7
+    sll     a7, a4
+    or      a6, a6, a7
+    s32i    a6, a5, 0
+
+    /* Store data on higher address */
+    l32i    a7, a5, 4
+    srl     a6, a4
+    and     a3, a7, a3
+    or      a3, a3, a6
+    s32i    a3, a5, 4
+
+    /* Restore registers */
+    wsr     a0, sar
+    rsr     a0, excsave1
+
+    l32i    a7, sp, 0x1c
+    l32i    a6, sp, 0x18
+    l32i    a5, sp, 0x14
+    l32i    a4, sp, 0x10
+    l32i    a3, sp, 0x0c
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+.LSA_store_reg:
+    .org .LSA_store_reg + (8 * 8)
+    mov     a4, a8
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (9 * 8)
+    mov     a4, a9
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (10 * 8)
+    mov     a4, a10
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (11 * 8)
+    mov     a4, a11
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (12 * 8)
+    mov     a4, a12
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (13 * 8)
+    mov     a4, a13
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (14 * 8)
+    mov     a4, a14
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (15 * 8)
+    mov     a4, a15
+    j       .LSA_store_data
+
+/*
+ * Common routines for both the exception handlers
+ */
+    .balign 4
+.LS_jumptable:
+    /*  The first 5 entries (80 bytes) of this table are unused (registers
+        a0..a4 are handled separately above).  Rather than have a whole bunch
+        of wasted space, just pretend that the table starts 80 bytes
+        earlier in memory. */
+    .set    .LS_jumptable_base, .LS_jumptable - (16 * 5)
+
+    .org    .LS_jumptable_base + (16 * 5)
+    mov     a5, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 6)
+    mov     a6, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 7)
+    mov     a7, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 8)
+    mov     a8, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 9)
+    mov     a9, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 10)
+    mov     a10, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 11)
+    mov     a11, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 12)
+    mov     a12, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 13)
+    mov     a13, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 14)
+    mov     a14, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 15)
+    mov     a15, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+.LS_wrong_opcode:
+    /* Reaches here if the address is in invalid range or the opcode isn't supported.
+     * Restore registers and jump back to _xt_user_exc
+     */
+    wsr     a0, sar
+    l32i    a4, sp, 0x10
+    l32i    a3, sp, 0x0c
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rsr     a0, depc
+    ret                                         // Equivalent to jx a0
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c
new file mode 100644
index 0000000..ef893a7
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c
@@ -0,0 +1,67 @@
+/* xtensa_overlay_os_hook.c -- Overlay manager OS hooks for FreeRTOS. */
+
+/* Copyright (c) 2015-2015 Cadence Design Systems Inc. */
+/* */
+/* Permission is hereby granted, free of charge, to any person obtaining */
+/* a copy of this software and associated documentation files (the */
+/* "Software"), to deal in the Software without restriction, including */
+/* without limitation the rights to use, copy, modify, merge, publish, */
+/* distribute, sublicense, and/or sell copies of the Software, and to */
+/* permit persons to whom the Software is furnished to do so, subject to */
+/* the following conditions: */
+/* */
+/* The above copyright notice and this permission notice shall be included */
+/* in all copies or substantial portions of the Software. */
+/* */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+
+#include "FreeRTOS.h"
+#include "semphr.h"
+
+#if configUSE_MUTEX
+
+/* Mutex object that controls access to the overlay. Currently only one
+ * overlay region is supported so one mutex suffices.
+ */
+    static SemaphoreHandle_t xt_overlay_mutex;
+
+
+/* This function should be overridden to provide OS specific init such
+ * as the creation of a mutex lock that can be used for overlay locking.
+ * Typically this mutex would be set up with priority inheritance. See
+ * overlay manager documentation for more details.
+ */
+    void xt_overlay_init_os( void )
+    {
+        /* Create the mutex for overlay access. Priority inheritance is
+         * required.
+         */
+        xt_overlay_mutex = xSemaphoreCreateMutex();
+    }
+
+
+/* This function locks access to shared overlay resources, typically
+ * by acquiring a mutex.
+ */
+    void xt_overlay_lock( void )
+    {
+        xSemaphoreTake( xt_overlay_mutex, 0 );
+    }
+
+
+/* This function releases access to shared overlay resources, typically
+ * by unlocking a mutex.
+ */
+    void xt_overlay_unlock( void )
+    {
+        xSemaphoreGive( xt_overlay_mutex );
+    }
+
+#endif /* if configUSE_MUTEX */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S
new file mode 100644
index 0000000..6ce34dd
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S
@@ -0,0 +1,164 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "xtensa_rtos.h"
+#include "esp_private/panic_reason.h"
+#include "sdkconfig.h"
+#include "soc/soc.h"
+
+/*
+This file contains the default handlers for the high interrupt levels as well as some specialized exceptions. 
+The default behaviour is to just exit the interrupt or call the panic handler on the exceptions
+*/
+
+
+#if XCHAL_HAVE_DEBUG
+    .global    xt_debugexception
+    .weak xt_debugexception
+    .set xt_debugexception, _xt_debugexception
+    .section .iram1,"ax"
+    .type       _xt_debugexception,@function
+    .align      4
+
+_xt_debugexception:
+    movi    a0,PANIC_RSN_DEBUGEXCEPTION
+    wsr     a0,EXCCAUSE
+    /* _xt_panic assumes a level 1 exception. As we're
+       crashing anyhow, copy EPC & EXCSAVE from DEBUGLEVEL
+       to level 1. */
+    rsr     a0,(EPC + XCHAL_DEBUGLEVEL)
+    wsr     a0,EPC_1
+    rsr     a0,(EXCSAVE + XCHAL_DEBUGLEVEL)
+    wsr     a0,EXCSAVE_1
+    call0   _xt_panic                       /* does not return */
+    rfi     XCHAL_DEBUGLEVEL
+
+#endif /* Debug exception */
+
+
+#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
+    .global    xt_highint2
+    .weak xt_highint2
+    .set xt_highint2, _xt_highint2
+    .section .iram1,"ax"
+    .type       _xt_highint2,@function
+    .align      4
+_xt_highint2:
+
+    /* Default handler does nothing; just returns */
+    .align  4
+.L_xt_highint2_exit:
+    rsr     a0, EXCSAVE_2                   /* restore a0 */
+    rfi     2
+
+#endif  /* Level 2 */
+
+#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
+
+    .global    xt_highint3
+    .weak xt_highint3
+    .set xt_highint3, _xt_highint3
+    .section .iram1,"ax"
+    .type       _xt_highint3,@function
+    .align      4
+_xt_highint3:
+
+    /* Default handler does nothing; just returns */
+
+    .align  4
+.L_xt_highint3_exit:
+    rsr     a0, EXCSAVE_3                   /* restore a0 */
+    rfi     3
+
+#endif  /* Level 3 */
+
+#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
+
+    .global    xt_highint4
+    .weak xt_highint4
+    .set xt_highint4, _xt_highint4
+    .section .iram1,"ax"
+    .type       _xt_highint4,@function
+    .align      4
+_xt_highint4:
+
+    /* Default handler does nothing; just returns */
+
+    .align  4
+.L_xt_highint4_exit:
+    rsr     a0, EXCSAVE_4                   /* restore a0 */
+    rfi     4
+
+#endif  /* Level 4 */
+
+#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
+
+    .global    xt_highint5
+    .weak xt_highint5
+    .set xt_highint5, _xt_highint5
+    .section .iram1,"ax"
+    .type       _xt_highint5,@function
+    .align      4
+_xt_highint5:
+
+    /* Default handler does nothing; just returns */
+
+    .align  4
+.L_xt_highint5_exit:
+    rsr     a0, EXCSAVE_5                   /* restore a0 */
+    rfi     5
+
+
+#endif  /* Level 5 */
+
+#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
+
+    .global    _xt_highint6
+    .global    xt_highint6
+    .weak xt_highint6
+    .set xt_highint6, _xt_highint6
+    .section .iram1,"ax"
+    .type       _xt_highint6,@function
+    .align      4
+_xt_highint6:
+
+    /* Default handler does nothing; just returns */
+
+    .align  4
+.L_xt_highint6_exit:
+    rsr     a0, EXCSAVE_6                   /* restore a0 */
+    rfi     6
+
+#endif  /* Level 6 */
+
+#if XCHAL_HAVE_NMI
+
+    .global    _xt_nmi
+    .global    xt_nmi
+    .weak xt_nmi
+    .set xt_nmi, _xt_nmi
+    .section .iram1,"ax"
+    .type       _xt_nmi,@function
+    .align      4
+_xt_nmi:
+
+    /* Default handler does nothing; just returns */
+
+    .align  4
+.L_xt_nmi_exit:
+    rsr     a0, EXCSAVE + XCHAL_NMILEVEL    /* restore a0 */
+    rfi     XCHAL_NMILEVEL
+
+#endif  /* NMI */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vectors.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vectors.S
new file mode 100644
index 0000000..eb0729f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vectors.S
@@ -0,0 +1,2027 @@
+/*******************************************************************************
+Copyright (c) 2006-2015 Cadence Design Systems Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be included
+in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+--------------------------------------------------------------------------------
+
+        XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS
+
+  Xtensa low level exception and interrupt vectors and handlers for an RTOS.
+
+  Interrupt handlers and user exception handlers support interaction with
+  the RTOS by calling XT_RTOS_INT_ENTER and XT_RTOS_INT_EXIT before and
+  after user's specific interrupt handlers. These macros are defined in
+  xtensa_<rtos>.h to call suitable functions in a specific RTOS.
+
+  Users can install application-specific interrupt handlers for low and
+  medium level interrupts, by calling xt_set_interrupt_handler(). These
+  handlers can be written in C, and must obey C calling convention. The
+  handler table is indexed by the interrupt number. Each handler may be
+  provided with an argument. 
+
+  Note that the system timer interrupt is handled specially, and is
+  dispatched to the RTOS-specific handler. This timer cannot be hooked
+  by application code.
+
+  Optional hooks are also provided to install a handler per level at 
+  run-time, made available by compiling this source file with 
+  '-DXT_INTEXC_HOOKS' (useful for automated testing).
+
+!!  This file is a template that usually needs to be modified to handle       !!
+!!  application specific interrupts. Search USER_EDIT for helpful comments    !!
+!!  on where to insert handlers and how to write them.                        !!
+
+  Users can also install application-specific exception handlers in the
+  same way, by calling xt_set_exception_handler(). One handler slot is
+  provided for each exception type. Note that some exceptions are handled
+  by the porting layer itself, and cannot be taken over by application
+  code in this manner. These are the alloca, syscall, and coprocessor
+  exceptions.
+
+  The exception handlers can be written in C, and must follow C calling
+  convention. Each handler is passed a pointer to an exception frame as
+  its single argument. The exception frame is created on the stack, and
+  holds the saved context of the thread that took the exception. If the
+  handler returns, the context will be restored and the instruction that
+  caused the exception will be retried. If the handler makes any changes
+  to the saved state in the exception frame, the changes will be applied
+  when restoring the context.
+
+  Because Xtensa is a configurable architecture, this port supports all user
+  generated configurations (except restrictions stated in the release notes).
+  This is accomplished by conditional compilation using macros and functions
+  defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
+  Only the relevant parts of this file will be included in your RTOS build.
+  For example, this file provides interrupt vector templates for all types and
+  all priority levels, but only the ones in your configuration are built.
+
+  NOTES on the use of 'call0' for long jumps instead of 'j':
+   1. This file should be assembled with the -mlongcalls option to xt-xcc.
+   2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to
+      a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the
+      distance from the call to the destination. The linker then relaxes
+      it back to 'call0 dest' if it determines that dest is within range.
+      This allows more flexibility in locating code without the performance
+      overhead of the 'l32r' literal data load in cases where the destination
+      is in range of 'call0'. There is an additional benefit in that 'call0'
+      has a longer range than 'j' due to the target being word-aligned, so 
+      the 'l32r' sequence is less likely needed.
+   3. The use of 'call0' with -mlongcalls requires that register a0 not be 
+      live at the time of the call, which is always the case for a function 
+      call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'.
+   4. This use of 'call0' is independent of the C function call ABI.
+
+*******************************************************************************/
+
+#include "xtensa_rtos.h"
+#include "esp_private/panic_reason.h"
+#include "sdkconfig.h"
+#include "soc/soc.h"
+
+/*
+  Define for workaround: pin no-cpu-affinity tasks to a cpu when fpu is used.
+  Please change this when the tcb structure is changed
+*/
+#define TASKTCB_XCOREID_OFFSET (0x38+configMAX_TASK_NAME_LEN+3)&~3
+.extern pxCurrentTCB
+
+/*
+--------------------------------------------------------------------------------
+    In order for backtracing to be able to trace from the pre-exception stack
+    across to the exception stack (including nested interrupts), we need to create
+    a pseudo base-save area to make it appear like the exception dispatcher was
+    triggered by a CALL4 from the pre-exception code. In reality, the exception
+    dispatcher uses the same window as pre-exception code, and only CALL0s are
+    used within the exception dispatcher.
+
+    To create the pseudo base-save area, we need to store a copy of the pre-exception's
+    base save area (a0 to a4) below the exception dispatcher's SP. EXCSAVE_x will
+    be used to store a copy of the SP that points to the interrupted code's exception
+    frame just in case the exception dispatcher's SP does not point to the exception
+    frame (which is the case when switching from task to interrupt stack).
+
+    Clearing the pseudo base-save area is uncessary as the interrupt dispatcher
+    will restore the current SP to that of the pre-exception SP.
+--------------------------------------------------------------------------------
+*/
+#ifdef CONFIG_FREERTOS_INTERRUPT_BACKTRACE
+#define XT_DEBUG_BACKTRACE    1
+#endif
+
+
+/*
+--------------------------------------------------------------------------------
+  Defines used to access _xtos_interrupt_table.
+--------------------------------------------------------------------------------
+*/
+#define XIE_HANDLER     0
+#define XIE_ARG         4
+#define XIE_SIZE        8
+
+
+/*
+  Macro get_percpu_entry_for - convert a per-core ID into a multicore entry.
+  Basically does reg=reg*portNUM_PROCESSORS+current_core_id
+  Multiple versions here to optimize for specific portNUM_PROCESSORS values.
+*/
+    .macro get_percpu_entry_for reg scratch
+#if (portNUM_PROCESSORS == 1)
+    /* No need to do anything */
+#elif  (portNUM_PROCESSORS == 2)
+    /* Optimized 2-core code. */
+    getcoreid \scratch
+    addx2 \reg,\reg,\scratch
+#else
+    /* Generalized n-core code. Untested! */
+    movi \scratch,portNUM_PROCESSORS
+    mull \scratch,\reg,\scratch
+    getcoreid \reg
+    add \reg,\scratch,\reg
+#endif
+   .endm
+/*
+--------------------------------------------------------------------------------
+  Macro extract_msb - return the input with only the highest bit set.
+
+  Input  : "ain"  - Input value, clobbered.
+  Output : "aout" - Output value, has only one bit set, MSB of "ain".
+  The two arguments must be different AR registers.
+--------------------------------------------------------------------------------
+*/
+
+    .macro  extract_msb     aout ain
+1:
+    addi    \aout, \ain, -1         /* aout = ain - 1        */
+    and     \ain, \ain, \aout       /* ain  = ain & aout     */
+    bnez    \ain, 1b                /* repeat until ain == 0 */
+    addi    \aout, \aout, 1         /* return aout + 1       */
+    .endm
+
+/*
+--------------------------------------------------------------------------------
+  Macro dispatch_c_isr - dispatch interrupts to user ISRs.
+  This will dispatch to user handlers (if any) that are registered in the
+  XTOS dispatch table (_xtos_interrupt_table). These handlers would have
+  been registered by calling _xtos_set_interrupt_handler(). There is one
+  exception - the timer interrupt used by the OS will not be dispatched
+  to a user handler - this must be handled by the caller of this macro.
+
+  Level triggered and software interrupts are automatically deasserted by
+  this code.
+
+  ASSUMPTIONS:
+    -- PS.INTLEVEL is set to "level" at entry
+    -- PS.EXCM = 0, C calling enabled
+
+  NOTE: For CALL0 ABI, a12-a15 have not yet been saved.
+
+  NOTE: This macro will use registers a0 and a2-a7. The arguments are:
+    level -- interrupt level
+    mask  -- interrupt bitmask for this level
+--------------------------------------------------------------------------------
+*/
+
+    .macro  dispatch_c_isr    level  mask
+
+    #ifdef CONFIG_PM_TRACE
+    movi a6, 0 /* = ESP_PM_TRACE_IDLE */
+    getcoreid a7
+    call4 esp_pm_trace_exit
+    #endif // CONFIG_PM_TRACE
+
+    /* Get mask of pending, enabled interrupts at this level into a2. */
+
+.L_xt_user_int_&level&:
+    rsr     a2, INTENABLE
+    rsr     a3, INTERRUPT
+    movi    a4, \mask
+    and     a2, a2, a3
+    and     a2, a2, a4
+    beqz    a2, 9f                          /* nothing to do */
+
+    /* This bit of code provides a nice debug backtrace in the debugger.
+       It does take a few more instructions, so undef XT_DEBUG_BACKTRACE
+       if you want to save the cycles.
+       At this point, the exception frame should have been allocated and filled,
+       and current sp points to the interrupt stack (for non-nested interrupt)
+       or below the allocated exception frame (for nested interrupts). Copy the
+       pre-exception's base save area below the current SP.
+    */
+    #ifdef XT_DEBUG_BACKTRACE
+    #ifndef __XTENSA_CALL0_ABI__
+    rsr     a0, EXCSAVE_1 + \level - 1      /* Get exception frame pointer stored in EXCSAVE_x */
+    l32i    a3, a0, XT_STK_A0               /* Copy pre-exception a0 (return address) */
+    s32e    a3, a1, -16
+    l32i    a3, a0, XT_STK_A1               /* Copy pre-exception a1 (stack pointer) */
+    s32e    a3, a1, -12
+    /* Backtracing only needs a0 and a1, no need to create full base save area.
+       Also need to change current frame's return address to point to pre-exception's
+       last run instruction.
+     */
+    rsr     a0, EPC_1 + \level - 1          /* return address */
+    movi    a4, 0xC0000000                  /* constant with top 2 bits set (call size) */
+    or      a0, a0, a4                      /* set top 2 bits */
+    addx2   a0, a4, a0                      /* clear top bit -- simulating call4 size   */
+    #endif
+    #endif
+
+    #ifdef CONFIG_PM_ENABLE
+    call4 esp_pm_impl_isr_hook
+    #endif
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a4, _xt_intexc_hooks
+    l32i    a4, a4, \level << 2
+    beqz    a4, 2f
+    #ifdef __XTENSA_CALL0_ABI__
+    callx0  a4
+    beqz    a2, 9f
+    #else
+    mov     a6, a2
+    callx4  a4
+    beqz    a6, 9f
+    mov     a2, a6
+    #endif
+2:
+    #endif
+
+    /* Now look up in the dispatch table and call user ISR if any. */
+    /* If multiple bits are set then MSB has highest priority.     */
+
+    extract_msb  a4, a2                     /* a4 = MSB of a2, a2 trashed */
+
+    #ifdef XT_USE_SWPRI
+    /* Enable all interrupts at this level that are numerically higher
+       than the one we just selected, since they are treated as higher
+       priority.
+    */
+    movi    a3, \mask                       /* a3 = all interrupts at this level */
+    add     a2, a4, a4                      /* a2 = a4 << 1 */
+    addi    a2, a2, -1                      /* a2 = mask of 1's <= a4 bit */
+    and     a2, a2, a3                      /* a2 = mask of all bits <= a4 at this level */
+    movi    a3, _xt_intdata
+    l32i    a6, a3, 4                       /* a6 = _xt_vpri_mask */
+    neg     a2, a2
+    addi    a2, a2, -1                      /* a2 = mask to apply */
+    and     a5, a6, a2                      /* mask off all bits <= a4 bit */
+    s32i    a5, a3, 4                       /* update _xt_vpri_mask */
+    rsr     a3, INTENABLE
+    and     a3, a3, a2                      /* mask off all bits <= a4 bit */
+    wsr     a3, INTENABLE
+    rsil    a3, \level - 1                  /* lower interrupt level by 1 */
+    #endif
+
+    movi    a3, XT_TIMER_INTEN              /* a3 = timer interrupt bit */
+    wsr     a4, INTCLEAR                    /* clear sw or edge-triggered interrupt */
+    beq     a3, a4, 7f                      /* if timer interrupt then skip table */
+
+    find_ms_setbit a3, a4, a3, 0            /* a3 = interrupt number */
+
+    get_percpu_entry_for a3, a12
+    movi    a4, _xt_interrupt_table
+    addx8   a3, a3, a4                      /* a3 = address of interrupt table entry */
+    l32i    a4, a3, XIE_HANDLER             /* a4 = handler address */
+    #ifdef __XTENSA_CALL0_ABI__
+    mov     a12, a6                         /* save in callee-saved reg */
+    l32i    a2, a3, XIE_ARG                 /* a2 = handler arg */
+    callx0  a4                              /* call handler */
+    mov     a2, a12
+    #else
+    mov     a2, a6                          /* save in windowed reg */
+    l32i    a6, a3, XIE_ARG                 /* a6 = handler arg */
+    callx4  a4                              /* call handler */
+    #endif
+
+    #ifdef XT_USE_SWPRI
+    j       8f
+    #else
+    j       .L_xt_user_int_&level&          /* check for more interrupts */
+    #endif
+
+7:
+
+    .ifeq XT_TIMER_INTPRI - \level
+.L_xt_user_int_timer_&level&:
+    /*
+    Interrupt handler for the RTOS tick timer if at this level.
+    We'll be reading the interrupt state again after this call
+    so no need to preserve any registers except a6 (vpri_mask).
+    */
+
+    #ifdef __XTENSA_CALL0_ABI__
+    mov     a12, a6
+    call0   XT_RTOS_TIMER_INT
+    mov     a2, a12
+    #else
+    mov     a2, a6
+    call4   XT_RTOS_TIMER_INT
+    #endif
+    .endif
+
+    #ifdef XT_USE_SWPRI
+    j       8f
+    #else
+    j       .L_xt_user_int_&level&          /* check for more interrupts */
+    #endif
+
+    #ifdef XT_USE_SWPRI
+8:
+    /* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from
+       virtual _xt_intenable which _could_ have changed during interrupt
+       processing. */
+
+    movi    a3, _xt_intdata
+    l32i    a4, a3, 0                       /* a4 = _xt_intenable    */
+    s32i    a2, a3, 4                       /* update _xt_vpri_mask  */
+    and     a4, a4, a2                      /* a4 = masked intenable */
+    wsr     a4, INTENABLE                   /* update INTENABLE      */
+    #endif
+
+9:
+    /* done */
+
+    .endm
+
+
+/*
+--------------------------------------------------------------------------------
+  Panic handler.
+  Should be reached by call0 (preferable) or jump only. If call0, a0 says where 
+  from. If on simulator, display panic message and abort, else loop indefinitely.
+--------------------------------------------------------------------------------
+*/
+
+    .section .iram1,"ax"
+    .global panicHandler
+
+    .global     _xt_panic
+    .type       _xt_panic,@function
+    .align      4
+    .literal_position
+    .align      4
+
+_xt_panic:
+    /* Allocate exception frame and save minimal context. */
+    mov     a0, sp
+    addi    sp, sp, -XT_STK_FRMSZ
+    s32i    a0, sp, XT_STK_A1
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -12                     /* for debug backtrace */
+    #endif
+    rsr     a0, PS                          /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_1                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -16                     /* for debug backtrace */
+    #endif
+    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
+    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
+    call0   _xt_context_save
+
+    /* Save exc cause and vaddr into exception frame */
+    rsr     a0, EXCCAUSE
+    s32i    a0, sp, XT_STK_EXCCAUSE
+    rsr     a0, EXCVADDR
+    s32i    a0, sp, XT_STK_EXCVADDR
+
+    /* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
+    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
+
+    s32i    a0, sp, XT_STK_A0
+
+    /* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
+    movi    a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
+    wsr     a0, PS
+
+    //Call panic handler
+    mov     a6,sp
+    call4 panicHandler
+
+
+    .align 4
+//Call using call0. Prints the hex char in a2. Kills a3, a4, a5
+panic_print_hex:
+    movi a3,0x60000000
+    movi a4,8
+panic_print_hex_loop:
+    l32i a5, a3, 0x1c
+    extui a5, a5, 16, 8
+    bgei a5,64,panic_print_hex_loop
+
+    srli a5,a2,28
+    bgei a5,10,panic_print_hex_a
+    addi a5,a5,'0'
+    j panic_print_hex_ok
+panic_print_hex_a:
+    addi a5,a5,'A'-10
+panic_print_hex_ok:
+    s32i a5,a3,0
+    slli a2,a2,4
+    
+    addi a4,a4,-1
+    bnei a4,0,panic_print_hex_loop
+    movi a5,' '
+    s32i a5,a3,0
+
+    ret
+
+
+
+    .section    .rodata, "a"
+    .align      4
+
+
+
+/*
+--------------------------------------------------------------------------------
+    Hooks to dynamically install handlers for exceptions and interrupts.
+    Allows automated regression frameworks to install handlers per test.
+    Consists of an array of function pointers indexed by interrupt level, 
+    with index 0 containing the entry for user exceptions.
+    Initialized with all 0s, meaning no handler is installed at each level.
+    See comment in xtensa_rtos.h for more details.
+
+    *WARNING*  This array is for all CPUs, that is, installing a hook for 
+    one CPU will install it for all others as well!
+--------------------------------------------------------------------------------
+*/
+
+    #ifdef XT_INTEXC_HOOKS
+    .data
+    .global     _xt_intexc_hooks
+    .type       _xt_intexc_hooks,@object
+    .align      4
+
+_xt_intexc_hooks:
+    .fill       XT_INTEXC_HOOK_NUM, 4, 0
+    #endif
+
+
+/*
+--------------------------------------------------------------------------------
+  EXCEPTION AND LEVEL 1 INTERRUPT VECTORS AND LOW LEVEL HANDLERS
+  (except window exception vectors).
+
+  Each vector goes at a predetermined location according to the Xtensa
+  hardware configuration, which is ensured by its placement in a special
+  section known to the Xtensa linker support package (LSP). It performs
+  the minimum necessary before jumping to the handler in the .text section.
+
+  The corresponding handler goes in the normal .text section. It sets up
+  the appropriate stack frame, saves a few vector-specific registers and
+  calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
+  and enter the RTOS, then sets up a C environment. It then calls the
+  user's interrupt handler code (which may be coded in C) and finally 
+  calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
+
+  While XT_RTOS_INT_EXIT does not return directly to the interruptee,
+  eventually the RTOS scheduler will want to dispatch the interrupted
+  task or handler. The scheduler will return to the exit point that was
+  saved in the interrupt stack frame at XT_STK_EXIT.
+--------------------------------------------------------------------------------
+*/
+
+
+/*
+--------------------------------------------------------------------------------
+Debug Exception.
+--------------------------------------------------------------------------------
+*/
+
+#if XCHAL_HAVE_DEBUG
+
+    .begin      literal_prefix .DebugExceptionVector
+    .section    .DebugExceptionVector.text, "ax"
+    .global     _DebugExceptionVector
+    .align      4
+    .global     xt_debugexception
+_DebugExceptionVector:
+    wsr     a0, EXCSAVE+XCHAL_DEBUGLEVEL    /* preserve a0 */
+    call0   xt_debugexception            /* load exception handler */
+
+    .end        literal_prefix
+
+#endif
+
+/*
+--------------------------------------------------------------------------------
+Double Exception.
+Double exceptions are not a normal occurrence. They indicate a bug of some kind.
+--------------------------------------------------------------------------------
+*/
+
+#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
+
+    .begin      literal_prefix .DoubleExceptionVector
+    .section    .DoubleExceptionVector.text, "ax"
+    .global     _DoubleExceptionVector
+    .align      4
+
+_DoubleExceptionVector:
+
+    #if XCHAL_HAVE_DEBUG
+    break   1, 4                            /* unhandled double exception */
+    #endif
+    movi    a0,PANIC_RSN_DOUBLEEXCEPTION
+    wsr     a0,EXCCAUSE
+    call0   _xt_panic                       /* does not return */
+    rfde                                    /* make a0 point here not later */
+
+    .end        literal_prefix
+
+#endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */
+
+/*
+--------------------------------------------------------------------------------
+Kernel Exception (including Level 1 Interrupt from kernel mode).
+--------------------------------------------------------------------------------
+*/
+
+    .begin      literal_prefix .KernelExceptionVector
+    .section    .KernelExceptionVector.text, "ax"
+    .global     _KernelExceptionVector
+    .align      4
+
+_KernelExceptionVector:
+
+    wsr     a0, EXCSAVE_1                   /* preserve a0 */
+    call0   _xt_kernel_exc                  /* kernel exception handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .section .iram1,"ax"
+    .align      4
+
+_xt_kernel_exc:
+    #if XCHAL_HAVE_DEBUG
+    break   1, 0                            /* unhandled kernel exception */
+    #endif
+    movi    a0,PANIC_RSN_KERNELEXCEPTION
+    wsr     a0,EXCCAUSE
+    call0   _xt_panic                       /* does not return */
+    rfe                                     /* make a0 point here not there */
+
+
+/*
+--------------------------------------------------------------------------------
+User Exception (including Level 1 Interrupt from user mode).
+--------------------------------------------------------------------------------
+*/
+
+    .begin      literal_prefix .UserExceptionVector
+    .section    .UserExceptionVector.text, "ax"
+    .global     _UserExceptionVector
+    .type       _UserExceptionVector,@function
+    .align      4
+
+_UserExceptionVector:
+
+    wsr     a0, EXCSAVE_1                   /* preserve a0 */
+    call0   _xt_user_exc                    /* user exception handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+/*
+--------------------------------------------------------------------------------
+  Insert some waypoints for jumping beyond the signed 8-bit range of
+  conditional branch instructions, so the conditional branchces to specific
+  exception handlers are not taken in the mainline. Saves some cycles in the
+  mainline.
+--------------------------------------------------------------------------------
+*/
+
+#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
+    .global   LoadStoreErrorHandler
+    .global   AlignmentErrorHandler
+#endif
+
+    .section .iram1,"ax"
+
+    #if XCHAL_HAVE_WINDOWED
+    .align      4
+_xt_to_alloca_exc:
+    call0   _xt_alloca_exc                  /* in window vectors section */
+    /* never returns here - call0 is used as a jump (see note at top) */
+    #endif
+
+    .align      4
+_xt_to_syscall_exc:
+    call0   _xt_syscall_exc
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    #if XCHAL_CP_NUM > 0
+    .align      4
+_xt_to_coproc_exc:
+    call0   _xt_coproc_exc
+    /* never returns here - call0 is used as a jump (see note at top) */
+    #endif
+
+#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
+    .align      4
+_call_loadstore_handler:
+    call0   LoadStoreErrorHandler
+    /* This will return only if wrong opcode or address out of range*/
+    j       .LS_exit
+
+    .align      4
+_call_alignment_handler:
+    call0   AlignmentErrorHandler
+    /* This will return only if wrong opcode or address out of range*/
+    addi    a0, a0, 1
+    j       .LS_exit
+#endif
+
+/*
+--------------------------------------------------------------------------------
+  User exception handler.
+--------------------------------------------------------------------------------
+*/
+
+    .type       _xt_user_exc,@function
+    .align      4
+
+_xt_user_exc:
+
+    /* If level 1 interrupt then jump to the dispatcher */
+    rsr     a0, EXCCAUSE
+    beqi    a0, EXCCAUSE_LEVEL1INTERRUPT, _xt_lowint1
+
+    /* Handle any coprocessor exceptions. Rely on the fact that exception
+       numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors.
+    */
+    #if XCHAL_CP_NUM > 0
+    bgeui   a0, EXCCAUSE_CP0_DISABLED, _xt_to_coproc_exc
+    #endif
+
+    /* Handle alloca and syscall exceptions */
+    #if XCHAL_HAVE_WINDOWED
+    beqi    a0, EXCCAUSE_ALLOCA,  _xt_to_alloca_exc
+    #endif
+    beqi    a0, EXCCAUSE_SYSCALL, _xt_to_syscall_exc
+
+#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
+    beqi    a0, EXCCAUSE_LOAD_STORE_ERROR, _call_loadstore_handler
+
+    addi    a0, a0, -1
+    beqi    a0, 8, _call_alignment_handler
+    addi    a0, a0, 1
+.LS_exit:
+#endif
+
+    /* Handle all other exceptions. All can have user-defined handlers. */
+    /* NOTE: we'll stay on the user stack for exception handling.       */
+
+    /* Allocate exception frame and save minimal context. */
+    mov     a0, sp
+    addi    sp, sp, -XT_STK_FRMSZ
+    s32i    a0, sp, XT_STK_A1
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -12                     /* for debug backtrace */
+    #endif
+    rsr     a0, PS                          /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_1                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -16                     /* for debug backtrace */
+    #endif
+    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
+    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
+    call0   _xt_context_save
+
+    /* Save exc cause and vaddr into exception frame */
+    rsr     a0, EXCCAUSE
+    s32i    a0, sp, XT_STK_EXCCAUSE
+    rsr     a0, EXCVADDR
+    s32i    a0, sp, XT_STK_EXCVADDR
+
+    /* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
+    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+
+    /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+
+    /*
+        Create pseudo base save area. At this point, sp is still pointing to the
+        allocated and filled exception stack frame.
+    */
+    #ifdef XT_DEBUG_BACKTRACE
+    #ifndef __XTENSA_CALL0_ABI__
+    l32i    a3, sp, XT_STK_A0               /* Copy pre-exception a0 (return address) */
+    s32e    a3, sp, -16
+    l32i    a3, sp, XT_STK_A1               /* Copy pre-exception a1 (stack pointer) */
+    s32e    a3, sp, -12
+    rsr     a0, EPC_1                       /* return address for debug backtrace */
+    movi    a5, 0xC0000000                  /* constant with top 2 bits set (call size) */
+    rsync                                   /* wait for WSR.PS to complete */
+    or      a0, a0, a5                      /* set top 2 bits */
+    addx2   a0, a5, a0                      /* clear top bit -- thus simulating call4 size */
+    #else
+    rsync                                   /* wait for WSR.PS to complete */
+    #endif
+    #endif
+
+    rsr     a2, EXCCAUSE                    /* recover exc cause */
+
+    #ifdef XT_INTEXC_HOOKS
+    /*
+    Call exception hook to pre-handle exceptions (if installed).
+    Pass EXCCAUSE in a2, and check result in a2 (if -1, skip default handling).
+    */
+    movi    a4, _xt_intexc_hooks
+    l32i    a4, a4, 0                       /* user exception hook index 0 */
+    beqz    a4, 1f
+.Ln_xt_user_exc_call_hook:
+    #ifdef __XTENSA_CALL0_ABI__
+    callx0  a4
+    beqi    a2, -1, .L_xt_user_done
+    #else
+    mov     a6, a2
+    callx4  a4
+    beqi    a6, -1, .L_xt_user_done
+    mov     a2, a6
+    #endif
+1:
+    #endif
+
+    rsr     a2, EXCCAUSE                    /* recover exc cause */
+    movi    a3, _xt_exception_table
+    get_percpu_entry_for a2, a4
+    addx4   a4, a2, a3                      /* a4 = address of exception table entry */
+    l32i    a4, a4, 0                       /* a4 = handler address */
+    #ifdef __XTENSA_CALL0_ABI__
+    mov     a2, sp                          /* a2 = pointer to exc frame */
+    callx0  a4                              /* call handler */
+    #else
+    mov     a6, sp                          /* a6 = pointer to exc frame */
+    callx4  a4                              /* call handler */
+    #endif
+
+.L_xt_user_done:
+
+    /* Restore context and return */
+    call0   _xt_context_restore
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, PS
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_1
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove exception frame */
+    rsync                                   /* ensure PS and EPC written */
+    rfe                                     /* PS.EXCM is cleared */
+
+
+/*
+--------------------------------------------------------------------------------
+  Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+  on entry and used to return to a thread or interrupted interrupt handler.
+--------------------------------------------------------------------------------
+*/
+
+    .global     _xt_user_exit
+    .type       _xt_user_exit,@function
+    .align      4
+_xt_user_exit:
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, PS
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_1
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure PS and EPC written */
+    rfe                                     /* PS.EXCM is cleared */
+
+
+/*
+
+--------------------------------------------------------------------------------
+Syscall Exception Handler (jumped to from User Exception Handler).
+Syscall 0 is required to spill the register windows (no-op in Call 0 ABI).
+Only syscall 0 is handled here. Other syscalls return -1 to caller in a2.
+--------------------------------------------------------------------------------
+*/
+
+    .section .iram1,"ax"
+    .type       _xt_syscall_exc,@function
+    .align      4
+_xt_syscall_exc:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /*
+    Save minimal regs for scratch. Syscall 0 does nothing in Call0 ABI.
+    Use a minimal stack frame (16B) to save A2 & A3 for scratch.
+    PS.EXCM could be cleared here, but unlikely to improve worst-case latency.
+    rsr     a0, PS
+    addi    a0, a0, -PS_EXCM_MASK
+    wsr     a0, PS
+    */
+    addi    sp, sp, -16
+    s32i    a2, sp, 8
+    s32i    a3, sp, 12
+    #else   /* Windowed ABI */
+    /*
+    Save necessary context and spill the register windows.
+    PS.EXCM is still set and must remain set until after the spill.
+    Reuse context save function though it saves more than necessary.
+    For this reason, a full interrupt stack frame is allocated.
+    */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
+    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
+    call0   _xt_context_save
+    #endif
+
+    /*
+    Grab the interruptee's PC and skip over the 'syscall' instruction.
+    If it's at the end of a zero-overhead loop and it's not on the last
+    iteration, decrement loop counter and skip to beginning of loop.
+    */
+    rsr     a2, EPC_1                       /* a2 = PC of 'syscall' */
+    addi    a3, a2, 3                       /* ++PC                 */
+    #if XCHAL_HAVE_LOOPS
+    rsr     a0, LEND                        /* if (PC == LEND       */
+    bne     a3, a0, 1f
+    rsr     a0, LCOUNT                      /*     && LCOUNT != 0)  */
+    beqz    a0, 1f                          /* {                    */
+    addi    a0, a0, -1                      /*   --LCOUNT           */
+    rsr     a3, LBEG                        /*   PC = LBEG          */
+    wsr     a0, LCOUNT                      /* }                    */
+    #endif
+1:  wsr     a3, EPC_1                       /* update PC            */
+
+    /* Restore interruptee's context and return from exception. */
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a2, sp, 8
+    l32i    a3, sp, 12
+    addi    sp, sp, 16
+    #else
+    call0   _xt_context_restore
+    addi    sp, sp, XT_STK_FRMSZ
+    #endif
+    movi    a0, -1
+    movnez  a2, a0, a2                      /* return -1 if not syscall 0 */
+    rsr     a0, EXCSAVE_1
+    rfe
+
+/*
+--------------------------------------------------------------------------------
+Co-Processor Exception Handler (jumped to from User Exception Handler).
+These exceptions are generated by co-processor instructions, which are only
+allowed in thread code (not in interrupts or kernel code). This restriction is 
+deliberately imposed to reduce the burden of state-save/restore in interrupts.
+--------------------------------------------------------------------------------
+*/
+#if XCHAL_CP_NUM > 0
+
+    .section .rodata, "a"
+
+/* Offset to CP n save area in thread's CP save area. */
+    .global _xt_coproc_sa_offset
+    .type   _xt_coproc_sa_offset,@object
+    .align  16                      /* minimize crossing cache boundaries */
+_xt_coproc_sa_offset:
+    .word   XT_CP0_SA, XT_CP1_SA, XT_CP2_SA, XT_CP3_SA
+    .word   XT_CP4_SA, XT_CP5_SA, XT_CP6_SA, XT_CP7_SA
+
+/* Bitmask for CP n's CPENABLE bit. */
+    .type   _xt_coproc_mask,@object
+    .align  16,,8                   /* try to keep it all in one cache line */
+    .set    i, 0
+_xt_coproc_mask:
+    .rept   XCHAL_CP_MAX
+    .long   (i<<16) | (1<<i)    // upper 16-bits = i, lower = bitmask
+    .set    i, i+1
+    .endr
+
+    .data
+
+/* Owner thread of CP n, identified by thread's CP save area (0 = unowned). */
+    .global _xt_coproc_owner_sa
+    .type   _xt_coproc_owner_sa,@object
+    .align  16,,XCHAL_CP_MAX<<2     /* minimize crossing cache boundaries */
+_xt_coproc_owner_sa:
+    .space  (XCHAL_CP_MAX * portNUM_PROCESSORS) << 2
+
+    .section .iram1,"ax"
+
+
+    .align  4
+.L_goto_invalid:
+    j   .L_xt_coproc_invalid    /* not in a thread (invalid) */
+    .align  4
+.L_goto_done:
+    j   .L_xt_coproc_done
+
+
+/*
+--------------------------------------------------------------------------------
+  Coprocessor exception handler.
+  At entry, only a0 has been saved (in EXCSAVE_1).
+--------------------------------------------------------------------------------
+*/
+
+    .type   _xt_coproc_exc,@function
+    .align  4
+
+_xt_coproc_exc:
+
+    /* Allocate interrupt stack frame and save minimal context. */
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -12                     /* for debug backtrace */
+    #endif
+    rsr     a0, PS                          /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_1                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -16                     /* for debug backtrace */
+    #endif
+    movi    a0, _xt_user_exit               /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    rsr     a0, EXCCAUSE
+    s32i    a5, sp, XT_STK_A5               /* save a5 */
+    addi    a5, a0, -EXCCAUSE_CP0_DISABLED  /* a5 = CP index */
+
+    /* Save a few more of interruptee's registers (a5 was already saved). */
+    s32i    a2,  sp, XT_STK_A2
+    s32i    a3,  sp, XT_STK_A3
+    s32i    a4,  sp, XT_STK_A4
+    s32i    a15, sp, XT_STK_A15
+
+    /* Get co-processor state save area of new owner thread. */
+    call0   XT_RTOS_CP_STATE                /* a15 = new owner's save area */
+
+    #ifndef CONFIG_FREERTOS_FPU_IN_ISR     
+    beqz    a15, .L_goto_invalid
+    #endif
+
+    /*When FPU in ISR is enabled we could deal with zeroed a15 */
+
+    /* Enable the co-processor's bit in CPENABLE. */
+    movi    a0, _xt_coproc_mask
+    rsr     a4, CPENABLE                    /* a4 = CPENABLE */
+    addx4   a0, a5, a0                      /* a0 = &_xt_coproc_mask[n] */
+    l32i    a0, a0, 0                       /* a0 = (n << 16) | (1 << n) */
+
+    /* FPU operations are incompatible with non-pinned tasks. If we have a FPU operation
+       here, to keep the entire thing from crashing, it's better to pin the task to whatever
+       core we're running on now. */
+    movi    a2, pxCurrentTCB
+    getcoreid a3
+    addx4     a2,  a3, a2
+    l32i    a2, a2, 0                       /* a2 = start of pxCurrentTCB[cpuid] */
+    addi    a2, a2, TASKTCB_XCOREID_OFFSET  /* offset to xCoreID in tcb struct */
+    s32i    a3, a2, 0                       /* store current cpuid */
+
+    /* Grab correct xt_coproc_owner_sa for this core */
+    movi    a2, XCHAL_CP_MAX << 2
+    mull    a2, a2, a3                      /* multiply by current processor id */
+    movi    a3, _xt_coproc_owner_sa         /* a3 = base of owner array */
+    add     a3, a3, a2                      /* a3 = owner area needed for this processor */
+
+    extui   a2, a0, 0, 16                   /* coprocessor bitmask portion */
+    or      a4, a4, a2                      /* a4 = CPENABLE | (1 << n) */
+    wsr     a4, CPENABLE
+
+/* 
+Keep loading _xt_coproc_owner_sa[n] atomic (=load once, then use that value
+everywhere): _xt_coproc_release assumes it works like this in order not to need
+locking.
+*/
+
+
+    /* Get old coprocessor owner thread (save area ptr) and assign new one.  */
+    addx4   a3,  a5, a3                      /* a3 = &_xt_coproc_owner_sa[n] */
+    l32i    a2,  a3, 0                       /* a2 = old owner's save area */
+    s32i    a15, a3, 0                       /* _xt_coproc_owner_sa[n] = new */
+    rsync                                    /* ensure wsr.CPENABLE is complete */
+
+    /* Only need to context switch if new owner != old owner. */
+    /* If float is necessary on ISR, we need to remove this check */
+    /* below, because on restoring from ISR we may have new == old condition used
+     * to force cp restore to next thread
+     */
+    #ifndef CONFIG_FREERTOS_FPU_IN_ISR     
+    beq     a15, a2, .L_goto_done           /* new owner == old, we're done */
+    #endif
+
+    /* If no old owner then nothing to save. */
+    beqz    a2, .L_check_new
+
+    /* If old owner not actively using CP then nothing to save. */
+    l16ui   a4,  a2,  XT_CPENABLE           /* a4 = old owner's CPENABLE */
+    bnone   a4,  a0,  .L_check_new          /* old owner not using CP    */
+
+.L_save_old:
+    /* Save old owner's coprocessor state. */
+
+    movi    a5, _xt_coproc_sa_offset
+
+    /* Mark old owner state as no longer active (CPENABLE bit n clear). */
+    xor     a4,  a4,  a0                    /* clear CP bit in CPENABLE    */
+    s16i    a4,  a2,  XT_CPENABLE           /* update old owner's CPENABLE */
+
+    extui   a4,  a0,  16,  5                /* a4 = CP index = n */
+    addx4   a5,  a4,  a5                    /* a5 = &_xt_coproc_sa_offset[n] */
+
+    /* Mark old owner state as saved (CPSTORED bit n set). */
+    l16ui   a4,  a2,  XT_CPSTORED           /* a4 = old owner's CPSTORED */
+    l32i    a5,  a5,  0                     /* a5 = XT_CP[n]_SA offset */
+    or      a4,  a4,  a0                    /* set CP in old owner's CPSTORED */
+    s16i    a4,  a2,  XT_CPSTORED           /* update old owner's CPSTORED */
+    l32i    a2, a2, XT_CP_ASA               /* ptr to actual (aligned) save area */
+    extui   a3, a0, 16, 5                   /* a3 = CP index = n */
+    add     a2, a2, a5                      /* a2 = old owner's area for CP n */
+
+    /*
+    The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
+    It is theoretically possible for Xtensa processor designers to write TIE 
+    that causes more address registers to be affected, but it is generally 
+    unlikely. If that ever happens, more registers needs to be saved/restored
+    around this macro invocation, and the value in a15 needs to be recomputed.
+    */
+    xchal_cpi_store_funcbody
+
+.L_check_new:
+    /* Check if any state has to be restored for new owner. */
+    /* NOTE: a15 = new owner's save area, cannot be zero when we get here. */
+    beqz    a15, .L_xt_coproc_done
+
+    l16ui   a3,  a15, XT_CPSTORED           /* a3 = new owner's CPSTORED */
+    movi    a4, _xt_coproc_sa_offset
+    bnone   a3,  a0,  .L_check_cs           /* full CP not saved, check callee-saved */
+    xor     a3,  a3,  a0                    /* CPSTORED bit is set, clear it */
+    s16i    a3,  a15, XT_CPSTORED           /* update new owner's CPSTORED */
+
+    /* Adjust new owner's save area pointers to area for CP n. */
+    extui   a3,  a0, 16, 5                  /* a3 = CP index = n */
+    addx4   a4,  a3, a4                     /* a4 = &_xt_coproc_sa_offset[n] */
+    l32i    a4,  a4, 0                      /* a4 = XT_CP[n]_SA */
+    l32i    a5, a15, XT_CP_ASA              /* ptr to actual (aligned) save area */
+    add     a2,  a4, a5                     /* a2 = new owner's area for CP */
+
+    /*
+    The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
+    It is theoretically possible for Xtensa processor designers to write TIE 
+    that causes more address registers to be affected, but it is generally 
+    unlikely. If that ever happens, more registers needs to be saved/restored
+    around this macro invocation.
+    */
+    xchal_cpi_load_funcbody
+
+    /* Restore interruptee's saved registers. */
+    /* Can omit rsync for wsr.CPENABLE here because _xt_user_exit does it. */
+.L_xt_coproc_done:
+    l32i    a15, sp, XT_STK_A15
+    l32i    a5,  sp, XT_STK_A5
+    l32i    a4,  sp, XT_STK_A4
+    l32i    a3,  sp, XT_STK_A3
+    l32i    a2,  sp, XT_STK_A2
+    call0   _xt_user_exit                   /* return via exit dispatcher */
+    /* Never returns here - call0 is used as a jump (see note at top) */
+
+.L_check_cs:
+    /* a0 = CP mask in low bits, a15 = new owner's save area */
+    l16ui   a2, a15, XT_CP_CS_ST            /* a2 = mask of CPs saved    */
+    bnone   a2,  a0, .L_xt_coproc_done      /* if no match then done     */
+    and     a2,  a2, a0                     /* a2 = which CPs to restore */
+    extui   a2,  a2, 0, 8                   /* extract low 8 bits        */
+    s32i    a6,  sp, XT_STK_A6              /* save extra needed regs    */
+    s32i    a7,  sp, XT_STK_A7
+    s32i    a13, sp, XT_STK_A13
+    s32i    a14, sp, XT_STK_A14
+    call0   _xt_coproc_restorecs            /* restore CP registers      */
+    l32i    a6,  sp, XT_STK_A6              /* restore saved registers   */
+    l32i    a7,  sp, XT_STK_A7
+    l32i    a13, sp, XT_STK_A13
+    l32i    a14, sp, XT_STK_A14
+    j       .L_xt_coproc_done
+
+    /* Co-processor exception occurred outside a thread (not supported). */
+.L_xt_coproc_invalid:
+    movi    a0,PANIC_RSN_COPROCEXCEPTION
+    wsr     a0,EXCCAUSE
+    call0   _xt_panic                       /* not in a thread (invalid) */
+    /* never returns */
+
+
+#endif /* XCHAL_CP_NUM */
+
+
+/*
+-------------------------------------------------------------------------------
+  Level 1 interrupt dispatch. Assumes stack frame has not been allocated yet.
+-------------------------------------------------------------------------------
+*/
+
+    .section .iram1,"ax"
+    .type       _xt_lowint1,@function
+    .align      4
+
+_xt_lowint1:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, PS                          /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_1                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_user_exit               /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* EXCSAVE_1 should now be free to use. Use it to keep a copy of the
+    current stack pointer that points to the exception frame (XT_STK_FRAME).*/
+    #ifdef XT_DEBUG_BACKTRACE
+    #ifndef __XTENSA_CALL0_ABI__
+    mov     a0, sp
+    wsr     a0, EXCSAVE_1
+    #endif
+    #endif
+
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */ 
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(1) | PS_UM
+    #else 
+    movi    a0, PS_INTLEVEL(1) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+
+/*
+-------------------------------------------------------------------------------
+  MEDIUM PRIORITY (LEVEL 2+) INTERRUPT VECTORS AND LOW LEVEL HANDLERS.
+
+  Medium priority interrupts are by definition those with priority greater
+  than 1 and not greater than XCHAL_EXCM_LEVEL. These are disabled by
+  setting PS.EXCM and therefore can easily support a C environment for
+  handlers in C, and interact safely with an RTOS.
+
+  Each vector goes at a predetermined location according to the Xtensa
+  hardware configuration, which is ensured by its placement in a special
+  section known to the Xtensa linker support package (LSP). It performs
+  the minimum necessary before jumping to the handler in the .text section.
+
+  The corresponding handler goes in the normal .text section. It sets up
+  the appropriate stack frame, saves a few vector-specific registers and
+  calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
+  and enter the RTOS, then sets up a C environment. It then calls the
+  user's interrupt handler code (which may be coded in C) and finally 
+  calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
+
+  While XT_RTOS_INT_EXIT does not return directly to the interruptee,
+  eventually the RTOS scheduler will want to dispatch the interrupted
+  task or handler. The scheduler will return to the exit point that was
+  saved in the interrupt stack frame at XT_STK_EXIT.
+-------------------------------------------------------------------------------
+*/
+
+#if XCHAL_EXCM_LEVEL >= 2
+
+    .begin      literal_prefix .Level2InterruptVector
+    .section    .Level2InterruptVector.text, "ax"
+    .global     _Level2Vector
+    .type       _Level2Vector,@function
+    .align      4
+_Level2Vector:
+    wsr     a0, EXCSAVE_2                   /* preserve a0 */
+    call0   _xt_medint2                     /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .section .iram1,"ax"
+    .type       _xt_medint2,@function
+    .align      4
+_xt_medint2:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_2                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_2                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_2                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint2_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* EXCSAVE_2 should now be free to use. Use it to keep a copy of the
+    current stack pointer that points to the exception frame (XT_STK_FRAME).*/
+    #ifdef XT_DEBUG_BACKTRACE
+    #ifndef __XTENSA_CALL0_ABI__
+    mov     a0, sp
+    wsr     a0, EXCSAVE_2
+    #endif
+    #endif
+
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(2) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(2) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint2_exit
+    .type       _xt_medint2_exit,@function
+    .align      4
+_xt_medint2_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_2
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_2
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     2
+
+#endif  /* Level 2 */
+
+#if XCHAL_EXCM_LEVEL >= 3
+
+    .begin      literal_prefix .Level3InterruptVector
+    .section    .Level3InterruptVector.text, "ax"
+    .global     _Level3Vector
+    .type       _Level3Vector,@function
+    .align      4
+_Level3Vector:
+    wsr     a0, EXCSAVE_3                   /* preserve a0 */
+    call0   _xt_medint3                     /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .section .iram1,"ax"
+    .type       _xt_medint3,@function
+    .align      4
+_xt_medint3:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_3                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_3                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_3                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint3_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* EXCSAVE_3 should now be free to use. Use it to keep a copy of the
+    current stack pointer that points to the exception frame (XT_STK_FRAME).*/
+    #ifdef XT_DEBUG_BACKTRACE
+    #ifndef __XTENSA_CALL0_ABI__
+    mov     a0, sp
+    wsr     a0, EXCSAVE_3
+    #endif
+    #endif
+
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(3) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(3) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint3_exit
+    .type       _xt_medint3_exit,@function
+    .align      4
+_xt_medint3_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_3
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_3
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     3
+
+#endif  /* Level 3 */
+
+#if XCHAL_EXCM_LEVEL >= 4
+
+    .begin      literal_prefix .Level4InterruptVector
+    .section    .Level4InterruptVector.text, "ax"
+    .global     _Level4Vector
+    .type       _Level4Vector,@function
+    .align      4
+_Level4Vector:
+    wsr     a0, EXCSAVE_4                   /* preserve a0 */
+    call0   _xt_medint4                     /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .section .iram1,"ax"
+    .type       _xt_medint4,@function
+    .align      4
+_xt_medint4:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_4                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_4                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_4                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint4_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* EXCSAVE_4 should now be free to use. Use it to keep a copy of the
+    current stack pointer that points to the exception frame (XT_STK_FRAME).*/
+    #ifdef XT_DEBUG_BACKTRACE
+    #ifndef __XTENSA_CALL0_ABI__
+    mov     a0, sp
+    wsr     a0, EXCSAVE_4
+    #endif
+    #endif
+
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(4) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(4) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint4_exit
+    .type       _xt_medint4_exit,@function
+    .align      4
+_xt_medint4_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_4
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_4
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     4
+
+#endif  /* Level 4 */
+
+#if XCHAL_EXCM_LEVEL >= 5
+
+    .begin      literal_prefix .Level5InterruptVector
+    .section    .Level5InterruptVector.text, "ax"
+    .global     _Level5Vector
+    .type       _Level5Vector,@function
+    .align      4
+_Level5Vector:
+    wsr     a0, EXCSAVE_5                   /* preserve a0 */
+    call0   _xt_medint5                     /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .section .iram1,"ax"
+    .type       _xt_medint5,@function
+    .align      4
+_xt_medint5:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_5                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_5                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_5                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint5_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* EXCSAVE_5 should now be free to use. Use it to keep a copy of the
+    current stack pointer that points to the exception frame (XT_STK_FRAME).*/
+    #ifdef XT_DEBUG_BACKTRACE
+    #ifndef __XTENSA_CALL0_ABI__
+    mov     a0, sp
+    wsr     a0, EXCSAVE_5
+    #endif
+    #endif
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(5) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint5_exit
+    .type       _xt_medint5_exit,@function
+    .align      4
+_xt_medint5_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_5
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_5
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     5
+
+#endif  /* Level 5 */
+
+#if XCHAL_EXCM_LEVEL >= 6
+
+    .begin      literal_prefix .Level6InterruptVector
+    .section    .Level6InterruptVector.text, "ax"
+    .global     _Level6Vector
+    .type       _Level6Vector,@function
+    .align      4
+_Level6Vector:
+    wsr     a0, EXCSAVE_6                   /* preserve a0 */
+    call0   _xt_medint6                     /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .section .iram1,"ax"
+    .type       _xt_medint6,@function
+    .align      4
+_xt_medint6:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_6                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_6                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_6                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint6_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* EXCSAVE_6 should now be free to use. Use it to keep a copy of the
+    current stack pointer that points to the exception frame (XT_STK_FRAME).*/
+    #ifdef XT_DEBUG_BACKTRACE
+    #ifndef __XTENSA_CALL0_ABI__
+    mov     a0, sp
+    wsr     a0, EXCSAVE_6
+    #endif
+    #endif
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(6) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(6) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint6_exit
+    .type       _xt_medint6_exit,@function
+    .align      4
+_xt_medint6_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_6
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_6
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     6
+
+#endif  /* Level 6 */
+
+
+/*******************************************************************************
+
+HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS
+
+High priority interrupts are by definition those with priorities greater
+than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority
+interrupts cannot interact with the RTOS, that is they must save all regs
+they use and not call any RTOS function.
+
+A further restriction imposed by the Xtensa windowed architecture is that
+high priority interrupts must not modify the stack area even logically
+"above" the top of the interrupted stack (they need to provide their
+own stack or static save area).
+
+Cadence Design Systems recommends high priority interrupt handlers be coded in assembly
+and used for purposes requiring very short service times.
+
+Here are templates for high priority (level 2+) interrupt vectors.
+They assume only one interrupt per level to avoid the burden of identifying
+which interrupts at this level are pending and enabled. This allows for 
+minimum latency and avoids having to save/restore a2 in addition to a0.
+If more than one interrupt per high priority level is configured, this burden
+is on the handler which in any case must provide a way to save and restore
+registers it uses without touching the interrupted stack.
+
+Each vector goes at a predetermined location according to the Xtensa
+hardware configuration, which is ensured by its placement in a special
+section known to the Xtensa linker support package (LSP). It performs
+the minimum necessary before jumping to the handler in the .text section.
+
+*******************************************************************************/
+
+/*
+These stubs just call xt_highintX/xt_nmi to handle the real interrupt. Please define
+these in an external assembly source file. If these symbols are not defined anywhere
+else, the defaults in xtensa_vector_defaults.S are used.
+*/
+
+#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
+
+    .begin      literal_prefix .Level2InterruptVector
+    .section    .Level2InterruptVector.text, "ax"
+    .global     _Level2Vector
+    .type       _Level2Vector,@function
+    .global     xt_highint2
+    .align      4
+_Level2Vector:
+    wsr     a0, EXCSAVE_2                   /* preserve a0 */
+    call0   xt_highint2                    /* load interrupt handler */
+
+    .end        literal_prefix
+
+#endif  /* Level 2 */
+
+#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
+
+    .begin      literal_prefix .Level3InterruptVector
+    .section    .Level3InterruptVector.text, "ax"
+    .global     _Level3Vector
+    .type       _Level3Vector,@function
+    .global     xt_highint3
+    .align      4
+_Level3Vector:
+    wsr     a0, EXCSAVE_3                   /* preserve a0 */
+    call0   xt_highint3                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+#endif  /* Level 3 */
+
+#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
+
+    .begin      literal_prefix .Level4InterruptVector
+    .section    .Level4InterruptVector.text, "ax"
+    .global     _Level4Vector
+    .type       _Level4Vector,@function
+    .global     xt_highint4
+    .align      4
+_Level4Vector:
+    wsr     a0, EXCSAVE_4                   /* preserve a0 */
+    call0   xt_highint4                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+#endif  /* Level 4 */
+
+#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
+
+    .begin      literal_prefix .Level5InterruptVector
+    .section    .Level5InterruptVector.text, "ax"
+    .global     _Level5Vector
+    .type       _Level5Vector,@function
+    .global     xt_highint5
+    .align      4
+_Level5Vector:
+    wsr     a0, EXCSAVE_5                   /* preserve a0 */
+    call0   xt_highint5                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+#endif  /* Level 5 */
+
+#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
+
+    .begin      literal_prefix .Level6InterruptVector
+    .section    .Level6InterruptVector.text, "ax"
+    .global     _Level6Vector
+    .type       _Level6Vector,@function
+    .global     xt_highint6
+    .align      4
+_Level6Vector:
+    wsr     a0, EXCSAVE_6                   /* preserve a0 */
+    call0   xt_highint6                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+#endif  /* Level 6 */
+
+#if XCHAL_HAVE_NMI
+
+    .begin      literal_prefix .NMIExceptionVector
+    .section    .NMIExceptionVector.text, "ax"
+    .global     _NMIExceptionVector
+    .type       _NMIExceptionVector,@function
+    .global     xt_nmi
+    .align      4
+_NMIExceptionVector:
+    wsr     a0, EXCSAVE + XCHAL_NMILEVEL  _ /* preserve a0 */
+    call0   xt_nmi                         /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+#endif  /* NMI */
+
+
+/*******************************************************************************
+
+WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER
+
+Here is the code for each window overflow/underflow exception vector and 
+(interspersed) efficient code for handling the alloca exception cause.
+Window exceptions are handled entirely in the vector area and are very
+tight for performance. The alloca exception is also handled entirely in 
+the window vector area so comes at essentially no cost in code size.
+Users should never need to modify them and Cadence Design Systems recommends 
+they do not.
+
+Window handlers go at predetermined vector locations according to the
+Xtensa hardware configuration, which is ensured by their placement in a
+special section known to the Xtensa linker support package (LSP). Since
+their offsets in that section are always the same, the LSPs do not define
+a section per vector.
+
+These things are coded for XEA2 only (XEA1 is not supported).
+
+Note on Underflow Handlers:
+The underflow handler for returning from call[i+1] to call[i]
+must preserve all the registers from call[i+1]'s window.
+In particular, a0 and a1 must be preserved because the RETW instruction
+will be reexecuted (and may even underflow if an intervening exception
+has flushed call[i]'s registers).
+Registers a2 and up may contain return values.
+
+*******************************************************************************/
+
+#if XCHAL_HAVE_WINDOWED
+
+    .section .WindowVectors.text, "ax"
+
+/*
+--------------------------------------------------------------------------------
+Window Overflow Exception for Call4.
+
+Invoked if a call[i] referenced a register (a4-a15)
+that contains data from ancestor call[j];
+call[j] had done a call4 to call[j+1].
+On entry here:
+    window rotated to call[j] start point;
+        a0-a3 are registers to be saved;
+        a4-a15 must be preserved;
+        a5 is call[j+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x0
+    .global _WindowOverflow4
+_WindowOverflow4:
+
+    s32e    a0, a5, -16     /* save a0 to call[j+1]'s stack frame */
+    s32e    a1, a5, -12     /* save a1 to call[j+1]'s stack frame */
+    s32e    a2, a5,  -8     /* save a2 to call[j+1]'s stack frame */
+    s32e    a3, a5,  -4     /* save a3 to call[j+1]'s stack frame */
+    rfwo                    /* rotates back to call[i] position */
+
+/*
+--------------------------------------------------------------------------------
+Window Underflow Exception for Call4
+
+Invoked by RETW returning from call[i+1] to call[i]
+where call[i]'s registers must be reloaded (not live in ARs);
+where call[i] had done a call4 to call[i+1].
+On entry here:
+        window rotated to call[i] start point;
+        a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
+        a4-a15 must be preserved (they are call[i+1].reg[0..11]);
+        a5 is call[i+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x40
+    .global _WindowUnderflow4
+_WindowUnderflow4:
+
+    l32e    a0, a5, -16     /* restore a0 from call[i+1]'s stack frame */
+    l32e    a1, a5, -12     /* restore a1 from call[i+1]'s stack frame */
+    l32e    a2, a5,  -8     /* restore a2 from call[i+1]'s stack frame */
+    l32e    a3, a5,  -4     /* restore a3 from call[i+1]'s stack frame */
+    rfwu
+
+/*
+--------------------------------------------------------------------------------
+Handle alloca exception generated by interruptee executing 'movsp'.
+This uses space between the window vectors, so is essentially "free".
+All interruptee's regs are intact except a0 which is saved in EXCSAVE_1,
+and PS.EXCM has been set by the exception hardware (can't be interrupted).
+The fact the alloca exception was taken means the registers associated with
+the base-save area have been spilled and will be restored by the underflow
+handler, so those 4 registers are available for scratch.
+The code is optimized to avoid unaligned branches and minimize cache misses.
+--------------------------------------------------------------------------------
+*/
+
+    .align  4
+    .global _xt_alloca_exc
+_xt_alloca_exc:
+
+    rsr     a0, WINDOWBASE  /* grab WINDOWBASE before rotw changes it */
+    rotw    -1              /* WINDOWBASE goes to a4, new a0-a3 are scratch */
+    rsr     a2, PS
+    extui   a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
+    xor     a3, a3, a4      /* bits changed from old to current windowbase */
+    rsr     a4, EXCSAVE_1   /* restore original a0 (now in a4) */
+    slli    a3, a3, XCHAL_PS_OWB_SHIFT
+    xor     a2, a2, a3      /* flip changed bits in old window base */
+    wsr     a2, PS          /* update PS.OWB to new window base */
+    rsync
+
+    _bbci.l a4, 31, _WindowUnderflow4
+    rotw    -1              /* original a0 goes to a8 */
+    _bbci.l a8, 30, _WindowUnderflow8
+    rotw    -1
+    j               _WindowUnderflow12
+
+/*
+--------------------------------------------------------------------------------
+Window Overflow Exception for Call8
+
+Invoked if a call[i] referenced a register (a4-a15)
+that contains data from ancestor call[j];
+call[j] had done a call8 to call[j+1].
+On entry here:
+    window rotated to call[j] start point;
+        a0-a7 are registers to be saved;
+        a8-a15 must be preserved;
+        a9 is call[j+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x80
+    .global _WindowOverflow8
+_WindowOverflow8:
+
+    s32e    a0, a9, -16     /* save a0 to call[j+1]'s stack frame */
+    l32e    a0, a1, -12     /* a0 <- call[j-1]'s sp
+                               (used to find end of call[j]'s frame) */
+    s32e    a1, a9, -12     /* save a1 to call[j+1]'s stack frame */
+    s32e    a2, a9,  -8     /* save a2 to call[j+1]'s stack frame */
+    s32e    a3, a9,  -4     /* save a3 to call[j+1]'s stack frame */
+    s32e    a4, a0, -32     /* save a4 to call[j]'s stack frame */
+    s32e    a5, a0, -28     /* save a5 to call[j]'s stack frame */
+    s32e    a6, a0, -24     /* save a6 to call[j]'s stack frame */
+    s32e    a7, a0, -20     /* save a7 to call[j]'s stack frame */
+    rfwo                    /* rotates back to call[i] position */
+
+/*
+--------------------------------------------------------------------------------
+Window Underflow Exception for Call8
+
+Invoked by RETW returning from call[i+1] to call[i]
+where call[i]'s registers must be reloaded (not live in ARs);
+where call[i] had done a call8 to call[i+1].
+On entry here:
+        window rotated to call[i] start point;
+        a0-a7 are undefined, must be reloaded with call[i].reg[0..7];
+        a8-a15 must be preserved (they are call[i+1].reg[0..7]);
+        a9 is call[i+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0xC0
+    .global _WindowUnderflow8
+_WindowUnderflow8:
+
+    l32e    a0, a9, -16     /* restore a0 from call[i+1]'s stack frame */
+    l32e    a1, a9, -12     /* restore a1 from call[i+1]'s stack frame */
+    l32e    a2, a9,  -8     /* restore a2 from call[i+1]'s stack frame */
+    l32e    a7, a1, -12     /* a7 <- call[i-1]'s sp
+                               (used to find end of call[i]'s frame) */
+    l32e    a3, a9,  -4     /* restore a3 from call[i+1]'s stack frame */
+    l32e    a4, a7, -32     /* restore a4 from call[i]'s stack frame */
+    l32e    a5, a7, -28     /* restore a5 from call[i]'s stack frame */
+    l32e    a6, a7, -24     /* restore a6 from call[i]'s stack frame */
+    l32e    a7, a7, -20     /* restore a7 from call[i]'s stack frame */
+    rfwu
+
+/*
+--------------------------------------------------------------------------------
+Window Overflow Exception for Call12
+
+Invoked if a call[i] referenced a register (a4-a15)
+that contains data from ancestor call[j];
+call[j] had done a call12 to call[j+1].
+On entry here:
+    window rotated to call[j] start point;
+        a0-a11 are registers to be saved;
+        a12-a15 must be preserved;
+        a13 is call[j+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x100
+    .global _WindowOverflow12
+_WindowOverflow12:
+
+    s32e    a0,  a13, -16   /* save a0 to call[j+1]'s stack frame */
+    l32e    a0,  a1,  -12   /* a0 <- call[j-1]'s sp
+                               (used to find end of call[j]'s frame) */
+    s32e    a1,  a13, -12   /* save a1 to call[j+1]'s stack frame */
+    s32e    a2,  a13,  -8   /* save a2 to call[j+1]'s stack frame */
+    s32e    a3,  a13,  -4   /* save a3 to call[j+1]'s stack frame */
+    s32e    a4,  a0,  -48   /* save a4 to end of call[j]'s stack frame */
+    s32e    a5,  a0,  -44   /* save a5 to end of call[j]'s stack frame */
+    s32e    a6,  a0,  -40   /* save a6 to end of call[j]'s stack frame */
+    s32e    a7,  a0,  -36   /* save a7 to end of call[j]'s stack frame */
+    s32e    a8,  a0,  -32   /* save a8 to end of call[j]'s stack frame */
+    s32e    a9,  a0,  -28   /* save a9 to end of call[j]'s stack frame */
+    s32e    a10, a0,  -24   /* save a10 to end of call[j]'s stack frame */
+    s32e    a11, a0,  -20   /* save a11 to end of call[j]'s stack frame */
+    rfwo                    /* rotates back to call[i] position */
+
+/*
+--------------------------------------------------------------------------------
+Window Underflow Exception for Call12
+
+Invoked by RETW returning from call[i+1] to call[i]
+where call[i]'s registers must be reloaded (not live in ARs);
+where call[i] had done a call12 to call[i+1].
+On entry here:
+        window rotated to call[i] start point;
+        a0-a11 are undefined, must be reloaded with call[i].reg[0..11];
+        a12-a15 must be preserved (they are call[i+1].reg[0..3]);
+        a13 is call[i+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org 0x140
+    .global _WindowUnderflow12
+_WindowUnderflow12:
+
+    l32e    a0,  a13, -16   /* restore a0 from call[i+1]'s stack frame */
+    l32e    a1,  a13, -12   /* restore a1 from call[i+1]'s stack frame */
+    l32e    a2,  a13,  -8   /* restore a2 from call[i+1]'s stack frame */
+    l32e    a11, a1,  -12   /* a11 <- call[i-1]'s sp
+                               (used to find end of call[i]'s frame) */
+    l32e    a3,  a13,  -4   /* restore a3 from call[i+1]'s stack frame */
+    l32e    a4,  a11, -48   /* restore a4 from end of call[i]'s stack frame */
+    l32e    a5,  a11, -44   /* restore a5 from end of call[i]'s stack frame */
+    l32e    a6,  a11, -40   /* restore a6 from end of call[i]'s stack frame */
+    l32e    a7,  a11, -36   /* restore a7 from end of call[i]'s stack frame */
+    l32e    a8,  a11, -32   /* restore a8 from end of call[i]'s stack frame */
+    l32e    a9,  a11, -28   /* restore a9 from end of call[i]'s stack frame */
+    l32e    a10, a11, -24   /* restore a10 from end of call[i]'s stack frame */
+    l32e    a11, a11, -20   /* restore a11 from end of call[i]'s stack frame */
+    rfwu
+
+#endif /* XCHAL_HAVE_WINDOWED */
+
+    .section    .UserEnter.text, "ax"
+    .global     call_user_start
+    .type       call_user_start,@function
+    .align      4
+    .literal_position
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/FreeRTOS-openocd.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/FreeRTOS-openocd.c
new file mode 100644
index 0000000..671c2de
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/FreeRTOS-openocd.c
@@ -0,0 +1,27 @@
+/*
+ * Since at least FreeRTOS V7.5.3 uxTopUsedPriority is no longer
+ * present in the kernel, so it has to be supplied by other means for
+ * OpenOCD's threads awareness.
+ *
+ * Add this file to your project, and, if you're using --gc-sections,
+ * ``--undefined=uxTopUsedPriority'' (or
+ * ``-Wl,--undefined=uxTopUsedPriority'' when using gcc for final
+ * linking) to your LDFLAGS; same with all the other symbols you need.
+ */
+
+#include "FreeRTOS.h"
+#include "esp_attr.h"
+#include "sdkconfig.h"
+
+#ifdef __GNUC__
+    #define USED    __attribute__( ( used ) )
+#else
+    #define USED
+#endif
+
+/* 
+ * This file is no longer needed as AFTER FreeRTOS V10.14.1 OpenOCD is fixed in the kernel.
+ * #ifdef CONFIG_ESP32_DEBUG_OCDAWARE
+ *   const int USED DRAM_ATTR uxTopUsedPriority = configMAX_PRIORITIES - 1;
+ * #endif 
+ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/portbenchmark.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/portbenchmark.h
new file mode 100644
index 0000000..ce34b97
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/portbenchmark.h
@@ -0,0 +1,46 @@
+/*******************************************************************************
+ * // Copyright (c) 2003-2015 Cadence Design Systems, Inc.
+ * //
+ * // Permission is hereby granted, free of charge, to any person obtaining
+ * // a copy of this software and associated documentation files (the
+ * // "Software"), to deal in the Software without restriction, including
+ * // without limitation the rights to use, copy, modify, merge, publish,
+ * // distribute, sublicense, and/or sell copies of the Software, and to
+ * // permit persons to whom the Software is furnished to do so, subject to
+ * // the following conditions:
+ * //
+ * // The above copyright notice and this permission notice shall be included
+ * // in all copies or substantial portions of the Software.
+ * //
+ * // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ * --------------------------------------------------------------------------------
+ */
+
+/*
+ * This utility helps benchmarking interrupt latency and context switches.
+ * In order to enable it, set configBENCHMARK to 1 in FreeRTOSConfig.h.
+ * You will also need to download the FreeRTOS_trace patch that contains
+ * portbenchmark.c and the complete version of portbenchmark.h
+ */
+
+#ifndef PORTBENCHMARK_H
+#define PORTBENCHMARK_H
+
+#if configBENCHMARK
+    #error "You need to download the FreeRTOS_trace patch that overwrites this file"
+#endif
+
+#define portbenchmarkINTERRUPT_DISABLE()
+#define portbenchmarkINTERRUPT_RESTORE( newstate )
+#define portbenchmarkIntLatency()
+#define portbenchmarkIntWait()
+#define portbenchmarkReset()
+#define portbenchmarkPrint()
+
+#endif /* PORTBENCHMARK */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/portmacro.h
new file mode 100644
index 0000000..7835eab
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/portmacro.h
@@ -0,0 +1,489 @@
+/*
+ *  FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
+ *  All rights reserved
+ *
+ *  VISIT https://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+ *
+ ***************************************************************************
+ *                                                                       *
+ *    FreeRTOS provides completely free yet professionally developed,    *
+ *    robust, strictly quality controlled, supported, and cross          *
+ *    platform software that has become a de facto standard.             *
+ *                                                                       *
+ *    Help yourself get started quickly and support the FreeRTOS         *
+ *    project by purchasing a FreeRTOS tutorial book, reference          *
+ *    manual, or both from: https://www.FreeRTOS.org/Documentation       *
+ *                                                                       *
+ *    Thank you!                                                         *
+ *                                                                       *
+ ***************************************************************************
+ *
+ *  This file is part of the FreeRTOS distribution.
+ *
+ *  FreeRTOS is free software; you can redistribute it and/or modify it under
+ *  the terms of the GNU General Public License (version 2) as published by the
+ *  Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+ *
+ *  >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+ *  >>!   distribute a combined work that includes FreeRTOS without being   !<<
+ *  >>!   obliged to provide the source code for proprietary components     !<<
+ *  >>!   outside of the FreeRTOS kernel.                                   !<<
+ *
+ *  FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ *  WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ *  FOR A PARTICULAR PURPOSE.  Full license text is available from the following
+ *  link: https://www.FreeRTOS.org/a00114.html
+ *
+ *
+ ***************************************************************************
+ *                                                                       *
+ *    Having a problem?  Start by reading the FAQ "My application does   *
+ *    not run, what could be wrong?"                                     *
+ *                                                                       *
+ *    https://www.FreeRTOS.org/FAQHelp.html                              *
+ *                                                                       *
+ ***************************************************************************
+ *
+ *  https://www.FreeRTOS.org - Documentation, books, training, latest versions,
+ *  license and Real Time Engineers Ltd. contact details.
+ *
+ *  https://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ *  including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ *  compatible FAT file system, and our tiny thread aware UDP/IP stack.
+ *
+ *  https://www.highintegritysystems.com/openrtos/ - Real Time Engineers ltd
+ *  license FreeRTOS to High Integrity Systems to sell under the OpenRTOS brand.
+ *  Low cost OpenRTOS licenses offer ticketed support, indemnification
+ *  and middleware.
+ *
+ *  https://www.highintegritysystems.com/safertos/ - High Integrity Systems
+ *  also provide a safety engineered and independently SIL3 certified version
+ *  for use in safety and mission critical applications that require
+ *  provable dependability.
+ *
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    extern "C" {
+#endif
+/* *INDENT-ON* */
+
+#ifndef __ASSEMBLER__
+
+    #include <stdint.h>
+
+    #include <xtensa/hal.h>
+    #include <xtensa/config/core.h>
+    #include <xtensa/config/system.h> /* required for XSHAL_CLIB */
+    #include <xtensa/xtruntime.h>
+    #include "esp_timer.h"            /* required for FreeRTOS run time stats */
+    #include "esp_system.h"
+
+
+    #include <esp_heap_caps.h>
+    #include "soc/soc_memory_layout.h"
+
+/*#include "xtensa_context.h" */
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+
+    #define portCHAR          int8_t
+    #define portFLOAT         float
+    #define portDOUBLE        double
+    #define portLONG          int32_t
+    #define portSHORT         int16_t
+    #define portSTACK_TYPE    uint8_t
+    #define portBASE_TYPE     int
+
+    typedef portSTACK_TYPE           StackType_t;
+    typedef portBASE_TYPE            BaseType_t;
+    typedef unsigned portBASE_TYPE   UBaseType_t;
+
+    #if ( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t             TickType_t;
+        #define portMAX_DELAY    ( TickType_t ) 0xffff
+    #else
+        typedef uint32_t             TickType_t;
+        #define portMAX_DELAY    ( TickType_t ) 0xffffffffUL
+    #endif
+/*-----------------------------------------------------------*/
+
+/* portbenchmark */
+    #include "portbenchmark.h"
+
+    #include "sdkconfig.h"
+    #include "esp_attr.h"
+
+/* "mux" data structure (spinlock) */
+    typedef struct
+    {
+        /* owner field values:
+         * 0                - Uninitialized (invalid)
+         * portMUX_FREE_VAL - Mux is free, can be locked by either CPU
+         * CORE_ID_PRO / CORE_ID_APP - Mux is locked to the particular core
+         *
+         * Any value other than portMUX_FREE_VAL, CORE_ID_PRO, CORE_ID_APP indicates corruption
+         */
+        uint32_t owner;
+
+        /* count field:
+         * If mux is unlocked, count should be zero.
+         * If mux is locked, count is non-zero & represents the number of recursive locks on the mux.
+         */
+        uint32_t count;
+        #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+            const char * lastLockedFn;
+            int lastLockedLine;
+        #endif
+    } portMUX_TYPE;
+
+    #define portMUX_FREE_VAL      0xB33FFFFF
+
+/* Special constants for vPortCPUAcquireMutexTimeout() */
+    #define portMUX_NO_TIMEOUT    ( -1 ) /* When passed for 'timeout_cycles', spin forever if necessary */
+    #define portMUX_TRY_LOCK      0      /* Try to acquire the spinlock a single time only */
+
+/* Keep this in sync with the portMUX_TYPE struct definition please. */
+    #ifndef CONFIG_FREERTOS_PORTMUX_DEBUG
+        #define portMUX_INITIALIZER_UNLOCKED \
+    {                                        \
+        .owner = portMUX_FREE_VAL,           \
+        .count = 0,                          \
+    }
+    #else
+        #define portMUX_INITIALIZER_UNLOCKED \
+    {                                        \
+        .owner = portMUX_FREE_VAL,           \
+        .count = 0,                          \
+        .lastLockedFn = "(never locked)",    \
+        .lastLockedLine = -1                 \
+    }
+    #endif /* ifndef CONFIG_FREERTOS_PORTMUX_DEBUG */
+
+
+    #define portASSERT_IF_IN_ISR()    vPortAssertIfInISR()
+    void vPortAssertIfInISR();
+
+    #define portCRITICAL_NESTING_IN_TCB    1
+
+/*
+ * Modifications to portENTER_CRITICAL.
+ *
+ * For an introduction, see "Critical Sections & Disabling Interrupts" in docs/api-guides/freertos-smp.rst
+ *
+ * The original portENTER_CRITICAL only disabled the ISRs. This is enough for single-CPU operation: by
+ * disabling the interrupts, there is no task switch so no other tasks can meddle in the data, and because
+ * interrupts are disabled, ISRs can't corrupt data structures either.
+ *
+ * For multiprocessing, things get a bit more hairy. First of all, disabling the interrupts doesn't stop
+ * the tasks or ISRs on the other processors meddling with our CPU. For tasks, this is solved by adding
+ * a spinlock to the portENTER_CRITICAL macro. A task running on the other CPU accessing the same data will
+ * spinlock in the portENTER_CRITICAL code until the first CPU is done.
+ *
+ * For ISRs, we now also need muxes: while portENTER_CRITICAL disabling interrupts will stop ISRs on the same
+ * CPU from meddling with the data, it does not stop interrupts on the other cores from interfering with the
+ * data. For this, we also use a spinlock in the routines called by the ISR, but these spinlocks
+ * do not disable the interrupts (because they already are).
+ *
+ * This all assumes that interrupts are either entirely disabled or enabled. Interrupt priority levels
+ * will break this scheme.
+ *
+ * Remark: For the ESP32, portENTER_CRITICAL and portENTER_CRITICAL_ISR both alias vTaskEnterCritical, meaning
+ * that either function can be called both from ISR as well as task context. This is not standard FreeRTOS
+ * behaviour; please keep this in mind if you need any compatibility with other FreeRTOS implementations.
+ */
+    void vPortCPUInitializeMutex( portMUX_TYPE * mux );
+    #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+        #error CONFIG_FREERTOS_PORTMUX_DEBUG not supported in Amazon FreeRTOS
+    #endif
+
+    void vTaskExitCritical();
+    void vTaskEnterCritical();
+    static inline void vPortConsumeSpinlockArg( int unused,
+                                                ... )
+    {
+    }
+
+/** @brief Acquire a portmux spinlock with a timeout
+ *
+ * @param mux Pointer to portmux to acquire.
+ * @param timeout_cycles Timeout to spin, in CPU cycles. Pass portMUX_NO_TIMEOUT to wait forever,
+ * portMUX_TRY_LOCK to try a single time to acquire the lock.
+ *
+ * @return true if mutex is successfully acquired, false on timeout.
+ */
+    bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux,
+                                      int timeout_cycles );
+    void vPortCPUReleaseMutex( portMUX_TYPE * mux );
+
+    #define portENTER_CRITICAL( ... )        do { vTaskEnterCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 )
+    #define portEXIT_CRITICAL( ... )         do { vTaskExitCritical(); vPortConsumeSpinlockArg( 0, ## __VA_ARGS__ ); } while( 0 )
+
+
+    #define portENTER_CRITICAL_ISR( mux )    vPortCPUAcquireMutexTimeout( mux, portMUX_NO_TIMEOUT )
+    #define portEXIT_CRITICAL_ISR( mux )     vPortCPUReleaseMutex( mux )
+
+    #define portENTER_CRITICAL_SAFE( mux ) \
+    do {                                   \
+        if( xPortInIsrContext() ) {        \
+            portENTER_CRITICAL_ISR( mux ); \
+        }                                  \
+        else {                             \
+            portENTER_CRITICAL( mux );     \
+        }                                  \
+    } while( 0 )
+
+    #define portEXIT_CRITICAL_SAFE( mux ) \
+    do {                                  \
+        if( xPortInIsrContext() ) {       \
+            portEXIT_CRITICAL_ISR( mux ); \
+        }                                 \
+        else {                            \
+            portEXIT_CRITICAL( mux );     \
+        }                                 \
+    } while( 0 )
+
+
+/* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */
+/* These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level. */
+/* */
+/* Only applies to one CPU. See notes above & below for reasons not to use these. */
+    #define portDISABLE_INTERRUPTS()    do { XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL ); portbenchmarkINTERRUPT_DISABLE(); } while( 0 )
+    #define portENABLE_INTERRUPTS()     do { portbenchmarkINTERRUPT_RESTORE( 0 ); XTOS_SET_INTLEVEL( 0 ); } while( 0 )
+
+/* Cleaner solution allows nested interrupts disabling and restoring via local registers or stack. */
+/* They can be called from interrupts too. */
+/* WARNING: Only applies to current CPU. See notes above. */
+    static inline unsigned portENTER_CRITICAL_NESTED()
+    {
+        unsigned state = XTOS_SET_INTLEVEL( XCHAL_EXCM_LEVEL );
+
+        portbenchmarkINTERRUPT_DISABLE();
+        return state;
+    }
+    #define portEXIT_CRITICAL_NESTED( state )             do { portbenchmarkINTERRUPT_RESTORE( state ); XTOS_RESTORE_JUST_INTLEVEL( state ); } while( 0 )
+
+/* These FreeRTOS versions are similar to the nested versions above */
+    #define portSET_INTERRUPT_MASK_FROM_ISR()             portENTER_CRITICAL_NESTED()
+    #define portCLEAR_INTERRUPT_MASK_FROM_ISR( state )    portEXIT_CRITICAL_NESTED( state )
+
+/*Because the ROM routines don't necessarily handle a stack in external RAM correctly, we force */
+/*the stack memory to always be internal. */
+    #define pvPortMallocTcbMem( size )        heap_caps_malloc( size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT )
+    #define pvPortMallocStackMem( size )      heap_caps_malloc( size, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT )
+
+/*xTaskCreateStatic uses these functions to check incoming memory. */
+    #define portVALID_TCB_MEM( ptr )          ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) )
+    #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+        #define portVALID_STACK_MEM( ptr )    esp_ptr_byte_accessible( ptr )
+    #else
+        #define portVALID_STACK_MEM( ptr )    ( esp_ptr_internal( ptr ) && esp_ptr_byte_accessible( ptr ) )
+    #endif
+
+/*
+ * Wrapper for the Xtensa compare-and-set instruction. This subroutine will atomically compare
+ * *addr to 'compare'. If *addr == compare, *addr is set to *set. *set is updated with the previous
+ * value of *addr (either 'compare' or some other value.)
+ *
+ * Warning: From the ISA docs: in some (unspecified) cases, the s32c1i instruction may return the
+ * *bitwise inverse* of the old mem if the mem wasn't written. This doesn't seem to happen on the
+ * ESP32 (portMUX assertions would fail).
+ */
+        static inline void uxPortCompareSet( volatile uint32_t * addr,
+                                             uint32_t compare,
+                                             uint32_t * set )
+        {
+            __asm__ __volatile__ (
+                "WSR 	    %2,SCOMPARE1 \n"
+                "S32C1I     %0, %1, 0	 \n"
+                : "=r" ( *set )
+                : "r" ( addr ), "r" ( compare ), "0" ( *set )
+                );
+        }
+
+        void uxPortCompareSetExtram( volatile uint32_t * addr,
+                                     uint32_t compare,
+                                     uint32_t * set );
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+    #define portSTACK_GROWTH      ( -1 )
+    #define portTICK_PERIOD_MS    ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+    #define portBYTE_ALIGNMENT    4
+    #define portNOP()    XT_NOP()
+/*-----------------------------------------------------------*/
+
+/* Fine resolution time */
+    #define portGET_RUN_TIME_COUNTER_VALUE()    xthal_get_ccount()
+/*ccount or esp_timer are initialized elsewhere */
+    #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
+
+    #ifdef CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER
+/* Coarse resolution time (us) */
+        #define portALT_GET_RUN_TIME_COUNTER_VALUE( x )    x = ( uint32_t ) esp_timer_get_time()
+    #endif
+
+
+
+/* Kernel utilities. */
+    void vPortYield( void );
+    void _frxt_setup_switch( void );
+    #define portYIELD()             vPortYield()
+    #define portYIELD_FROM_ISR()    { traceISR_EXIT_TO_SCHEDULER(); _frxt_setup_switch(); }
+
+    static inline uint32_t xPortGetCoreID();
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+    #define portTASK_FUNCTION_PROTO( vFunction, pvParameters )    void vFunction( void * pvParameters )
+    #define portTASK_FUNCTION( vFunction, pvParameters )          void vFunction( void * pvParameters )
+
+/* When coprocessors are defined, we to maintain a pointer to coprocessors area. */
+/* We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold: */
+/* MPU wrappers, coprocessor area pointer, trace code structure, and more if needed. */
+/* The field is normally used for memory protection. FreeRTOS should create another general purpose field. */
+    typedef struct
+    {
+        #if XCHAL_CP_NUM > 0
+            volatile StackType_t * coproc_area; /* Pointer to coprocessor save area; MUST BE FIRST */
+        #endif
+
+        #if portUSING_MPU_WRAPPERS
+            /* Define here mpu_settings, which is port dependent */
+            int mpu_setting; /* Just a dummy example here; MPU not ported to Xtensa yet */
+        #endif
+
+        #if configUSE_TRACE_FACILITY_2
+            struct
+            {
+                /* Cf. porttraceStamp() */
+                int taskstamp;      /* Stamp from inside task to see where we are */
+                int taskstampcount; /* A counter usually incremented when we restart the task's loop */
+            } porttrace;
+        #endif
+    } xMPU_SETTINGS;
+
+/* Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS) */
+    #if ( XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2 ) && !portUSING_MPU_WRAPPERS /* If MPU wrappers not used, we still need to allocate coproc area */
+        #undef portUSING_MPU_WRAPPERS
+        #define portUSING_MPU_WRAPPERS    1                                           /* Enable it to allocate coproc area */
+        #define MPU_WRAPPERS_H                                                        /* Override mpu_wrapper.h to disable unwanted code */
+        #define PRIVILEGED_FUNCTION
+        #define PRIVILEGED_DATA
+    #endif
+
+    bool vApplicationSleep( TickType_t xExpectedIdleTime );
+
+    #define portSUPPRESS_TICKS_AND_SLEEP( idleTime )    vApplicationSleep( idleTime )
+
+
+
+    void _xt_coproc_release( volatile void * coproc_sa_base );
+
+
+/*
+ * Map to the memory management routines required for the port.
+ *
+ * Note that libc standard malloc/free are also available for
+ * non-FreeRTOS-specific code, and behave the same as
+ * pvPortMalloc()/vPortFree().
+ */
+    #define pvPortMalloc                       heap_caps_malloc_default
+    #define vPortFree                          heap_caps_free
+    #define xPortGetFreeHeapSize               esp_get_free_heap_size
+    #define xPortGetMinimumEverFreeHeapSize    esp_get_minimum_free_heap_size
+
+/*
+ * Send an interrupt to another core in order to make the task running
+ * on it yield for a higher-priority task.
+ */
+
+        void vPortYieldOtherCore( BaseType_t coreid ) PRIVILEGED_FUNCTION;
+
+
+/*
+ * Callback to set a watchpoint on the end of the stack. Called every context switch to change the stack
+ * watchpoint around.
+ */
+    void vPortSetStackWatchpoint( void * pxStackStart );
+
+/*
+ * Returns true if the current core is in ISR context; low prio ISR, med prio ISR or timer tick ISR. High prio ISRs
+ * aren't detected here, but they normally cannot call C code, so that should not be an issue anyway.
+ */
+    BaseType_t xPortInIsrContext();
+
+/*
+ * This function will be called in High prio ISRs. Returns true if the current core was in ISR context
+ * before calling into high prio ISR context.
+ */
+    BaseType_t xPortInterruptedFromISRContext();
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+    #if ( portUSING_MPU_WRAPPERS == 1 )
+        struct xMEMORY_REGION;
+        void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                        const struct xMEMORY_REGION * const xRegions,
+                                        StackType_t * pxBottomOfStack,
+                                        uint32_t usStackDepth ) PRIVILEGED_FUNCTION;
+        void vPortReleaseTaskMPUSettings( xMPU_SETTINGS * xMPUSettings );
+    #endif
+
+/* Multi-core: get current core ID */
+    static inline uint32_t IRAM_ATTR xPortGetCoreID()
+    {
+        int id;
+
+        asm (
+            "rsr.prid %0\n"
+            " extui %0,%0,13,1"
+            : "=r" ( id ) );
+        return id;
+    }
+
+/* Get tick rate per second */
+    uint32_t xPortGetTickRateHz( void );
+
+/* porttrace */
+    #if configUSE_TRACE_FACILITY_2
+        #include "porttrace.h"
+    #endif
+
+/* configASSERT_2 if requested */
+    #if configASSERT_2
+        #include <stdio.h>
+        void exit( int );
+        #define configASSERT( x )    if( !( x ) ) { porttracePrint( -1 ); printf( "\nAssertion failed in %s:%d\n", __FILE__, __LINE__ ); exit( -1 ); }
+    #endif
+
+#endif // __ASSEMBLER__
+
+/* *INDENT-OFF* */
+#ifdef __cplusplus
+    }
+#endif
+/* *INDENT-ON* */
+
+#endif /* PORTMACRO_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/xtensa_api.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/xtensa_api.h
new file mode 100644
index 0000000..f91dab1
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/xtensa_api.h
@@ -0,0 +1,132 @@
+/*******************************************************************************
+ * Copyright (c) 2006-2015 Cadence Design Systems Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+*  Xtensa-specific API for RTOS ports.
+******************************************************************************/
+
+#ifndef __XTENSA_API_H__
+#define __XTENSA_API_H__
+
+#include <xtensa/hal.h>
+
+#include "xtensa_context.h"
+
+
+/* Typedef for C-callable interrupt handler function */
+typedef void (* xt_handler)( void * );
+
+/* Typedef for C-callable exception handler function */
+typedef void (* xt_exc_handler)( XtExcFrame * );
+
+
+/*
+ * -------------------------------------------------------------------------------
+ * Call this function to set a handler for the specified exception. The handler
+ * will be installed on the core that calls this function.
+ *
+ *  n        - Exception number (type)
+ *  f        - Handler function address, NULL to uninstall handler.
+ *
+ * The handler will be passed a pointer to the exception frame, which is created
+ * on the stack of the thread that caused the exception.
+ *
+ * If the handler returns, the thread context will be restored and the faulting
+ * instruction will be retried. Any values in the exception frame that are
+ * modified by the handler will be restored as part of the context. For details
+ * of the exception frame structure see xtensa_context.h.
+ * -------------------------------------------------------------------------------
+ */
+extern xt_exc_handler xt_set_exception_handler( int n,
+                                                xt_exc_handler f );
+
+
+/*
+ * -------------------------------------------------------------------------------
+ * Call this function to set a handler for the specified interrupt. The handler
+ * will be installed on the core that calls this function.
+ *
+ *  n        - Interrupt number.
+ *  f        - Handler function address, NULL to uninstall handler.
+ *  arg      - Argument to be passed to handler.
+ * -------------------------------------------------------------------------------
+ */
+extern xt_handler xt_set_interrupt_handler( int n,
+                                            xt_handler f,
+                                            void * arg );
+
+
+/*
+ * -------------------------------------------------------------------------------
+ * Call this function to enable the specified interrupts on the core that runs
+ * this code.
+ *
+ *  mask     - Bit mask of interrupts to be enabled.
+ * -------------------------------------------------------------------------------
+ */
+extern void xt_ints_on( unsigned int mask );
+
+
+/*
+ * -------------------------------------------------------------------------------
+ * Call this function to disable the specified interrupts on the core that runs
+ * this code.
+ *
+ *  mask     - Bit mask of interrupts to be disabled.
+ * -------------------------------------------------------------------------------
+ */
+extern void xt_ints_off( unsigned int mask );
+
+
+/*
+ * -------------------------------------------------------------------------------
+ * Call this function to set the specified (s/w) interrupt.
+ * -------------------------------------------------------------------------------
+ */
+static inline void xt_set_intset( unsigned int arg )
+{
+    xthal_set_intset( arg );
+}
+
+
+/*
+ * -------------------------------------------------------------------------------
+ * Call this function to clear the specified (s/w or edge-triggered)
+ * interrupt.
+ * -------------------------------------------------------------------------------
+ */
+static inline void xt_set_intclear( unsigned int arg )
+{
+    xthal_set_intclear( arg );
+}
+
+/*
+ * -------------------------------------------------------------------------------
+ * Call this function to get handler's argument for the specified interrupt.
+ *
+ *  n        - Interrupt number.
+ * -------------------------------------------------------------------------------
+ */
+extern void * xt_get_interrupt_handler_arg( int n );
+
+#endif /* __XTENSA_API_H__ */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/xtensa_config.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/xtensa_config.h
new file mode 100644
index 0000000..4ac32d7
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/xtensa_config.h
@@ -0,0 +1,145 @@
+/*******************************************************************************
+*  // Copyright (c) 2003-2015 Cadence Design Systems, Inc.
+*  //
+*  // Permission is hereby granted, free of charge, to any person obtaining
+*  // a copy of this software and associated documentation files (the
+*  // "Software"), to deal in the Software without restriction, including
+*  // without limitation the rights to use, copy, modify, merge, publish,
+*  // distribute, sublicense, and/or sell copies of the Software, and to
+*  // permit persons to whom the Software is furnished to do so, subject to
+*  // the following conditions:
+*  //
+*  // The above copyright notice and this permission notice shall be included
+*  // in all copies or substantial portions of the Software.
+*  //
+*  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+*  // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+*  // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+*  // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+*  // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+*  // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+*  // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*  --------------------------------------------------------------------------------
+*
+*  Configuration-specific information for Xtensa build. This file must be
+*  included in FreeRTOSConfig.h to properly set up the config-dependent
+*  parameters correctly.
+*
+*  NOTE: To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must
+*  be defined to be > 0 somewhere above or on the command line.
+*
+*******************************************************************************/
+
+#ifndef XTENSA_CONFIG_H
+    #define XTENSA_CONFIG_H
+
+    #ifdef __cplusplus
+        extern "C" {
+    #endif
+
+    #include <xtensa/hal.h>
+    #include <xtensa/config/core.h>
+    #include <xtensa/config/system.h> /* required for XSHAL_CLIB */
+
+    #include "xtensa_context.h"
+
+
+/*-----------------------------------------------------------------------------
+ *                                 STACK REQUIREMENTS
+ *
+ * This section defines the minimum stack size, and the extra space required to
+ * be allocated for saving coprocessor state and/or C library state information
+ * (if thread safety is enabled for the C library). The sizes are in bytes.
+ *
+ * Stack sizes for individual tasks should be derived from these minima based on
+ * the maximum call depth of the task and the maximum level of interrupt nesting.
+ * A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
+ * on the requirement for a task that calls nothing else but can be interrupted.
+ * This assumes that interrupt handlers do not call more than a few levels deep.
+ * If this is not true, i.e. one or more interrupt handlers make deep calls then
+ * the minimum must be increased.
+ *
+ * If the Xtensa processor configuration includes coprocessors, then space is
+ * allocated to save the coprocessor state on the stack.
+ *
+ * If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
+ * is defined) then space is allocated to save the C library context in the TCB.
+ *
+ * Allocating insufficient stack space is a common source of hard-to-find errors.
+ * During development, it is best to enable the FreeRTOS stack checking features.
+ *
+ * Usage:
+ *
+ * XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
+ *                            use of the C library. This will require extra stack
+ *                            space to be allocated for tasks that use the C library
+ *                            reentrant functions. See below for more information.
+ *
+ * NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
+ * support thread safety. Check your core configuration to see which C library
+ * was chosen for your system.
+ *
+ * XT_STACK_MIN_SIZE       -- The minimum stack size for any task. It is recommended
+ *                            that you do not use a stack smaller than this for any
+ *                            task. In case you want to use stacks smaller than this
+ *                            size, you must verify that the smaller size(s) will work
+ *                            under all operating conditions.
+ *
+ * XT_STACK_EXTRA          -- The amount of extra stack space to allocate for a task
+ *                            that does not make C library reentrant calls. Add this
+ *                            to the amount of stack space required by the task itself.
+ *
+ * XT_STACK_EXTRA_CLIB     -- The amount of space to allocate for C library state.
+ *
+ *  -----------------------------------------------------------------------------*/
+
+/* Extra space required for interrupt/exception hooks. */
+    #ifdef XT_INTEXC_HOOKS
+        #ifdef __XTENSA_CALL0_ABI__
+            #define STK_INTEXC_EXTRA     0x200
+        #else
+            #define STK_INTEXC_EXTRA     0x180
+        #endif
+    #else
+        #define STK_INTEXC_EXTRA         0
+    #endif
+
+    #define XT_CLIB_CONTEXT_AREA_SIZE    0
+
+/*------------------------------------------------------------------------------
+ *  Extra size -- interrupt frame plus coprocessor save area plus hook space.
+ *  NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
+ *  ------------------------------------------------------------------------------*/
+    #ifdef __XTENSA_CALL0_ABI__
+        #define XT_XTRA_SIZE    ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE )
+    #else
+        #define XT_XTRA_SIZE    ( XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE )
+    #endif
+
+/*------------------------------------------------------------------------------
+ *  Space allocated for user code -- function calls and local variables.
+ *  NOTE: This number can be adjusted to suit your needs. You must verify that the
+ *  amount of space you reserve is adequate for the worst-case conditions in your
+ *  application.
+ *  NOTE: The windowed ABI requires more stack, since space has to be reserved
+ *  for spilling register windows.
+ *  ------------------------------------------------------------------------------*/
+    #ifdef __XTENSA_CALL0_ABI__
+        #define XT_USER_SIZE    0x200
+    #else
+        #define XT_USER_SIZE    0x400
+    #endif
+
+/* Minimum recommended stack size. */
+    #define XT_STACK_MIN_SIZE      ( ( XT_XTRA_SIZE + XT_USER_SIZE ) / sizeof( unsigned char ) )
+
+/* OS overhead with and without C library thread context. */
+    #define XT_STACK_EXTRA         ( XT_XTRA_SIZE )
+    #define XT_STACK_EXTRA_CLIB    ( XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE )
+
+
+    #ifdef __cplusplus
+        }
+    #endif
+
+#endif /* XTENSA_CONFIG_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/xtensa_context.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/xtensa_context.h
new file mode 100644
index 0000000..5a76201
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/xtensa_context.h
@@ -0,0 +1,378 @@
+/*******************************************************************************
+Copyright (c) 2006-2015 Cadence Design Systems Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be included
+in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+--------------------------------------------------------------------------------
+
+        XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
+
+This header contains definitions and macros for use primarily by Xtensa
+RTOS assembly coded source files. It includes and uses the Xtensa hardware
+abstraction layer (HAL) to deal with config specifics. It may also be
+included in C source files.
+
+!! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !!
+
+NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
+
+*******************************************************************************/
+
+#ifndef XTENSA_CONTEXT_H
+#define XTENSA_CONTEXT_H
+
+#ifdef __ASSEMBLER__
+#include    <xtensa/coreasm.h>
+#endif
+
+#include    <xtensa/config/tie.h>
+#include    <xtensa/corebits.h>
+#include    <xtensa/config/system.h>
+#include <xtensa/xtruntime-frames.h>
+
+
+/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
+#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
+
+
+/*
+-------------------------------------------------------------------------------
+  Macros that help define structures for both C and assembler.
+-------------------------------------------------------------------------------
+*/
+
+#ifdef STRUCT_BEGIN
+#undef STRUCT_BEGIN
+#undef STRUCT_FIELD
+#undef STRUCT_AFIELD
+#undef STRUCT_END
+#endif
+
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
+
+#define STRUCT_BEGIN            .pushsection .text; .struct 0
+#define STRUCT_FIELD(ctype,size,asname,name)    asname: .space  size
+#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space  (size)*(n)
+#define STRUCT_END(sname)       sname##Size:; .popsection
+
+#else
+
+#define STRUCT_BEGIN            typedef struct {
+#define STRUCT_FIELD(ctype,size,asname,name)    ctype   name;
+#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype   name[n];
+#define STRUCT_END(sname)       } sname;
+
+#endif //_ASMLANGUAGE || __ASSEMBLER__
+
+
+/*
+-------------------------------------------------------------------------------
+  INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
+
+  A stack frame of this structure is allocated for any interrupt or exception.
+  It goes on the current stack. If the RTOS has a system stack for handling 
+  interrupts, every thread stack must allow space for just one interrupt stack 
+  frame, then nested interrupt stack frames go on the system stack.
+
+  The frame includes basic registers (explicit) and "extra" registers introduced 
+  by user TIE or the use of the MAC16 option in the user's Xtensa config.
+  The frame size is minimized by omitting regs not applicable to user's config.
+
+  For Windowed ABI, this stack frame includes the interruptee's base save area,
+  another base save area to manage gcc nested functions, and a little temporary 
+  space to help manage the spilling of the register windows.
+-------------------------------------------------------------------------------
+*/
+
+STRUCT_BEGIN
+STRUCT_FIELD (long, 4, XT_STK_EXIT,     exit) /* exit point for dispatch */
+STRUCT_FIELD (long, 4, XT_STK_PC,       pc)   /* return PC */
+STRUCT_FIELD (long, 4, XT_STK_PS,       ps)   /* return PS */
+STRUCT_FIELD (long, 4, XT_STK_A0,       a0)
+STRUCT_FIELD (long, 4, XT_STK_A1,       a1)   /* stack pointer before interrupt */
+STRUCT_FIELD (long, 4, XT_STK_A2,       a2)
+STRUCT_FIELD (long, 4, XT_STK_A3,       a3)
+STRUCT_FIELD (long, 4, XT_STK_A4,       a4)
+STRUCT_FIELD (long, 4, XT_STK_A5,       a5)
+STRUCT_FIELD (long, 4, XT_STK_A6,       a6)
+STRUCT_FIELD (long, 4, XT_STK_A7,       a7)
+STRUCT_FIELD (long, 4, XT_STK_A8,       a8)
+STRUCT_FIELD (long, 4, XT_STK_A9,       a9)
+STRUCT_FIELD (long, 4, XT_STK_A10,      a10)
+STRUCT_FIELD (long, 4, XT_STK_A11,      a11)
+STRUCT_FIELD (long, 4, XT_STK_A12,      a12)
+STRUCT_FIELD (long, 4, XT_STK_A13,      a13)
+STRUCT_FIELD (long, 4, XT_STK_A14,      a14)
+STRUCT_FIELD (long, 4, XT_STK_A15,      a15)
+STRUCT_FIELD (long, 4, XT_STK_SAR,      sar)
+STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
+STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
+#if XCHAL_HAVE_LOOPS
+STRUCT_FIELD (long, 4, XT_STK_LBEG,   lbeg)
+STRUCT_FIELD (long, 4, XT_STK_LEND,   lend)
+STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
+#endif
+#ifndef __XTENSA_CALL0_ABI__
+/* Temporary space for saving stuff during window spill */
+STRUCT_FIELD (long, 4, XT_STK_TMP0,   tmp0)
+STRUCT_FIELD (long, 4, XT_STK_TMP1,   tmp1)
+STRUCT_FIELD (long, 4, XT_STK_TMP2,   tmp2)
+#endif
+#ifdef XT_USE_SWPRI
+/* Storage for virtual priority mask */
+STRUCT_FIELD (long, 4, XT_STK_VPRI,   vpri)
+#endif
+#ifdef XT_USE_OVLY
+/* Storage for overlay state */
+STRUCT_FIELD (long, 4, XT_STK_OVLY,   ovly)
+#endif
+STRUCT_END(XtExcFrame)
+
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
+#define XT_STK_NEXT1      XtExcFrameSize
+#else
+#define XT_STK_NEXT1      sizeof(XtExcFrame)
+#endif
+
+/* Allocate extra storage if needed */
+#if XCHAL_EXTRA_SA_SIZE != 0
+
+#if XCHAL_EXTRA_SA_ALIGN <= 16
+#define XT_STK_EXTRA            ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
+#else
+/* If need more alignment than stack, add space for dynamic alignment */
+#define XT_STK_EXTRA            (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
+#endif
+#define XT_STK_NEXT2            (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
+
+#else
+
+#define XT_STK_NEXT2            XT_STK_NEXT1   
+
+#endif
+
+/*
+-------------------------------------------------------------------------------
+  This is the frame size. Add space for 4 registers (interruptee's base save
+  area) and some space for gcc nested functions if any.
+-------------------------------------------------------------------------------
+*/
+#define XT_STK_FRMSZ            (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
+
+
+/*
+-------------------------------------------------------------------------------
+  SOLICITED STACK FRAME FOR A THREAD
+
+  A stack frame of this structure is allocated whenever a thread enters the 
+  RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
+  It goes on the current thread's stack.
+
+  The solicited frame only includes registers that are required to be preserved
+  by the callee according to the compiler's ABI conventions, some space to save 
+  the return address for returning to the caller, and the caller's PS register.
+
+  For Windowed ABI, this stack frame includes the caller's base save area.
+
+  Note on XT_SOL_EXIT field:
+      It is necessary to distinguish a solicited from an interrupt stack frame.
+      This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
+      always at the same offset (0). It can be written with a code (usually 0) 
+      to distinguish a solicted frame from an interrupt frame. An RTOS port may
+      opt to ignore this field if it has another way of distinguishing frames.
+-------------------------------------------------------------------------------
+*/
+
+STRUCT_BEGIN
+#ifdef __XTENSA_CALL0_ABI__
+STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
+STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
+STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
+STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
+STRUCT_FIELD (long, 4, XT_SOL_A12,  a12)    /* should be on 16-byte alignment */
+STRUCT_FIELD (long, 4, XT_SOL_A13,  a13)
+STRUCT_FIELD (long, 4, XT_SOL_A14,  a14)
+STRUCT_FIELD (long, 4, XT_SOL_A15,  a15)
+#else
+STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
+STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
+STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
+STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
+STRUCT_FIELD (long, 4, XT_SOL_A0,   a0)    /* should be on 16-byte alignment */
+STRUCT_FIELD (long, 4, XT_SOL_A1,   a1)
+STRUCT_FIELD (long, 4, XT_SOL_A2,   a2)
+STRUCT_FIELD (long, 4, XT_SOL_A3,   a3)
+#endif
+STRUCT_END(XtSolFrame)
+
+/* Size of solicited stack frame */
+#define XT_SOL_FRMSZ            ALIGNUP(0x10, XtSolFrameSize)
+
+
+/*
+-------------------------------------------------------------------------------
+  CO-PROCESSOR STATE SAVE AREA FOR A THREAD
+
+  The RTOS must provide an area per thread to save the state of co-processors
+  when that thread does not have control. Co-processors are context-switched
+  lazily (on demand) only when a new thread uses a co-processor instruction,
+  otherwise a thread retains ownership of the co-processor even when it loses
+  control of the processor. An Xtensa co-processor exception is triggered when
+  any co-processor instruction is executed by a thread that is not the owner,
+  and the context switch of that co-processor is then peformed by the handler.
+  Ownership represents which thread's state is currently in the co-processor.
+
+  Co-processors may not be used by interrupt or exception handlers. If an 
+  co-processor instruction is executed by an interrupt or exception handler,
+  the co-processor exception handler will trigger a kernel panic and freeze.
+  This restriction is introduced to reduce the overhead of saving and restoring
+  co-processor state (which can be quite large) and in particular remove that
+  overhead from interrupt handlers.
+
+  The co-processor state save area may be in any convenient per-thread location
+  such as in the thread control block or above the thread stack area. It need
+  not be in the interrupt stack frame since interrupts don't use co-processors.
+
+  Along with the save area for each co-processor, two bitmasks with flags per 
+  co-processor (laid out as in the CPENABLE reg) help manage context-switching
+  co-processors as efficiently as possible:
+
+  XT_CPENABLE
+    The contents of a non-running thread's CPENABLE register.
+    It represents the co-processors owned (and whose state is still needed)
+    by the thread. When a thread is preempted, its CPENABLE is saved here.
+    When a thread solicits a context-swtich, its CPENABLE is cleared - the
+    compiler has saved the (caller-saved) co-proc state if it needs to.
+    When a non-running thread loses ownership of a CP, its bit is cleared.
+    When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
+    Avoids co-processor exceptions when no change of ownership is needed.
+
+  XT_CPSTORED
+    A bitmask with the same layout as CPENABLE, a bit per co-processor.
+    Indicates whether the state of each co-processor is saved in the state 
+    save area. When a thread enters the kernel, only the state of co-procs
+    still enabled in CPENABLE is saved. When the co-processor exception 
+    handler assigns ownership of a co-processor to a thread, it restores 
+    the saved state only if this bit is set, and clears this bit.
+
+  XT_CP_CS_ST
+    A bitmask with the same layout as CPENABLE, a bit per co-processor.
+    Indicates whether callee-saved state is saved in the state save area.
+    Callee-saved state is saved by itself on a solicited context switch,
+    and restored when needed by the coprocessor exception handler.
+    Unsolicited switches will cause the entire coprocessor to be saved
+    when necessary.
+
+  XT_CP_ASA
+    Pointer to the aligned save area.  Allows it to be aligned more than
+    the overall save area (which might only be stack-aligned or TCB-aligned).
+    Especially relevant for Xtensa cores configured with a very large data
+    path that requires alignment greater than 16 bytes (ABI stack alignment).
+-------------------------------------------------------------------------------
+*/
+
+#if XCHAL_CP_NUM > 0
+
+/*  Offsets of each coprocessor save area within the 'aligned save area':  */
+#define XT_CP0_SA   0
+#define XT_CP1_SA   ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
+#define XT_CP2_SA   ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
+#define XT_CP3_SA   ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
+#define XT_CP4_SA   ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
+#define XT_CP5_SA   ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
+#define XT_CP6_SA   ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
+#define XT_CP7_SA   ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
+#define XT_CP_SA_SIZE   ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
+
+/*  Offsets within the overall save area:  */
+#define XT_CPENABLE 0   /* (2 bytes) coprocessors active for this thread */
+#define XT_CPSTORED 2   /* (2 bytes) coprocessors saved for this thread */
+#define XT_CP_CS_ST 4   /* (2 bytes) coprocessor callee-saved regs stored for this thread */
+#define XT_CP_ASA   8   /* (4 bytes) ptr to aligned save area */
+/*  Overall size allows for dynamic alignment:  */
+#define XT_CP_SIZE  (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
+#else
+#define XT_CP_SIZE  0
+#endif
+
+
+/*
+ Macro to get the current core ID. Only uses the reg given as an argument.
+ Reading PRID on the ESP32 gives us 0xCDCD on the PRO processor (0)
+ and 0xABAB on the APP CPU (1). We can distinguish between the two by checking
+ bit 13: it's 1 on the APP and 0 on the PRO processor.
+*/
+#ifdef __ASSEMBLER__
+	.macro getcoreid reg
+	rsr.prid \reg
+	extui \reg,\reg,13,1
+	.endm
+#endif
+
+#define CORE_ID_PRO 0xCDCD
+#define CORE_ID_APP 0xABAB
+
+/*
+-------------------------------------------------------------------------------
+  MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
+
+  Convenient where the frame size requirements are the same for both ABIs.
+    ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
+    ENTRY0,    RET0    are for frameless functions (no locals, no calls).
+
+  where size = size of stack frame in bytes (must be >0 and aligned to 16).
+  For framed functions the frame is created and the return address saved at
+  base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
+  For frameless functions, there is no frame and return address remains in a0.
+  Note: Because CPP macros expand to a single line, macros requiring multi-line 
+  expansions are implemented as assembler macros.
+-------------------------------------------------------------------------------
+*/
+
+#ifdef __ASSEMBLER__
+#ifdef __XTENSA_CALL0_ABI__
+  /* Call0 */
+  #define ENTRY(sz)     entry1  sz
+    .macro  entry1 size=0x10
+    addi    sp, sp, -\size
+    s32i    a0, sp, 0
+    .endm
+  #define ENTRY0      
+  #define RET(sz)       ret1    sz
+    .macro  ret1 size=0x10
+    l32i    a0, sp, 0
+    addi    sp, sp, \size
+    ret
+    .endm
+  #define RET0          ret
+#else
+  /* Windowed */
+  #define ENTRY(sz)     entry   sp, sz
+  #define ENTRY0        entry   sp, 0x10
+  #define RET(sz)       retw
+  #define RET0          retw
+#endif
+#endif
+
+
+
+
+
+#endif /* XTENSA_CONTEXT_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/xtensa_rtos.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/xtensa_rtos.h
new file mode 100644
index 0000000..dbd82b6
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/xtensa_rtos.h
@@ -0,0 +1,231 @@
+/*******************************************************************************
+*  // Copyright (c) 2003-2015 Cadence Design Systems, Inc.
+*  //
+*  // Permission is hereby granted, free of charge, to any person obtaining
+*  // a copy of this software and associated documentation files (the
+*  // "Software"), to deal in the Software without restriction, including
+*  // without limitation the rights to use, copy, modify, merge, publish,
+*  // distribute, sublicense, and/or sell copies of the Software, and to
+*  // permit persons to whom the Software is furnished to do so, subject to
+*  // the following conditions:
+*  //
+*  // The above copyright notice and this permission notice shall be included
+*  // in all copies or substantial portions of the Software.
+*  //
+*  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+*  // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+*  // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+*  // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+*  // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+*  // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+*  // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*  --------------------------------------------------------------------------------
+*
+*       RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES
+*                           (FreeRTOS Port)
+*
+*  This header is the primary glue between generic Xtensa RTOS support
+*  sources and a specific RTOS port for Xtensa.  It contains definitions
+*  and macros for use primarily by Xtensa assembly coded source files.
+*
+*  Macros in this header map callouts from generic Xtensa files to specific
+*  RTOS functions. It may also be included in C source files.
+*
+*  Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa
+*  architecture, using the Xtensa hardware abstraction layer (HAL) to deal
+*  with configuration specifics.
+*
+*  Should be included by all Xtensa generic and RTOS port-specific sources.
+*
+*******************************************************************************/
+
+#ifndef XTENSA_RTOS_H
+#define XTENSA_RTOS_H
+
+#ifdef __ASSEMBLER__
+    #include    <xtensa/coreasm.h>
+#else
+    #include    <xtensa/config/core.h>
+#endif
+
+#include    <xtensa/corebits.h>
+#include    <xtensa/config/system.h>
+
+/*
+ * Include any RTOS specific definitions that are needed by this header.
+ */
+#include    "FreeRTOSConfig.h"
+
+/*
+ * Convert FreeRTOSConfig definitions to XTENSA definitions.
+ * However these can still be overridden from the command line.
+ */
+
+#ifndef XT_SIMULATOR
+    #if configXT_SIMULATOR
+        #define XT_SIMULATOR    1       /* Simulator mode */
+    #endif
+#endif
+
+#ifndef XT_BOARD
+    #if configXT_BOARD
+        #define XT_BOARD    1           /* Board mode */
+    #endif
+#endif
+
+#ifndef XT_TIMER_INDEX
+    #if defined configXT_TIMER_INDEX
+        #define XT_TIMER_INDEX    configXT_TIMER_INDEX     /* Index of hardware timer to be used */
+    #endif
+#endif
+
+#ifndef XT_INTEXC_HOOKS
+    #if configXT_INTEXC_HOOKS
+        #define XT_INTEXC_HOOKS    1    /* Enables exception hooks */
+    #endif
+#endif
+
+#if !defined( XT_SIMULATOR ) && !defined( XT_BOARD )
+    #error Either XT_SIMULATOR or XT_BOARD must be defined.
+#endif
+
+
+/*
+ * Name of RTOS (for messages).
+ */
+#define XT_RTOS_NAME    FreeRTOS
+
+/*
+ * Check some Xtensa configuration requirements and report error if not met.
+ * Error messages can be customize to the RTOS port.
+ */
+
+#if !XCHAL_HAVE_XEA2
+    #error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."
+#endif
+
+
+/*******************************************************************************
+*
+*  RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
+*
+*  Define callout macros used in generic Xtensa code to interact with the RTOS.
+*  The macros are simply the function names for use in calls from assembler code.
+*  Some of these functions may call back to generic functions in xtensa_context.h .
+*
+*******************************************************************************/
+
+/*
+ * Inform RTOS of entry into an interrupt handler that will affect it.
+ * Allows RTOS to manage switch to any system stack and count nesting level.
+ * Called after minimal context has been saved, with interrupts disabled.
+ * RTOS port can call0 _xt_context_save to save the rest of the context.
+ * May only be called from assembly code by the 'call0' instruction.
+ */
+/* void XT_RTOS_INT_ENTER(void) */
+#define XT_RTOS_INT_ENTER    _frxt_int_enter
+
+/*
+ * Inform RTOS of completion of an interrupt handler, and give control to
+ * RTOS to perform thread/task scheduling, switch back from any system stack
+ * and restore the context, and return to the exit dispatcher saved in the
+ * stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
+ * to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
+ * leaving only a minimal part of the context to be restored by the exit
+ * dispatcher. This function does not return to the place it was called from.
+ * May only be called from assembly code by the 'call0' instruction.
+ */
+/* void XT_RTOS_INT_EXIT(void) */
+#define XT_RTOS_INT_EXIT    _frxt_int_exit
+
+/*
+ * Inform RTOS of the occurrence of a tick timer interrupt.
+ * If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
+ * May be coded in or called from C or assembly, per ABI conventions.
+ * RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
+ */
+/* void XT_RTOS_TIMER_INT(void) */
+#define XT_RTOS_TIMER_INT    _frxt_timer_int
+#define XT_TICK_PER_SEC      configTICK_RATE_HZ
+
+/*
+ * Return in a15 the base address of the co-processor state save area for the
+ * thread that triggered a co-processor exception, or 0 if no thread was running.
+ * The state save area is structured as defined in xtensa_context.h and has size
+ * XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
+ * in interrupt handlers or the RTOS kernel. May only be called from assembly code
+ * and by the 'call0' instruction. A result of 0 indicates an unrecoverable error.
+ * The implementation may use only a2-4, a15 (all other regs must be preserved).
+ */
+/* void* XT_RTOS_CP_STATE(void) */
+#define XT_RTOS_CP_STATE    _frxt_task_coproc_state
+
+
+/*******************************************************************************
+*
+*  HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
+*
+*  This Xtensa RTOS port provides hooks for dynamically installing exception
+*  and interrupt handlers to facilitate automated testing where each test
+*  case can install its own handler for user exceptions and each interrupt
+*  priority (level). This consists of an array of function pointers indexed
+*  by interrupt priority, with index 0 being the user exception handler hook.
+*  Each entry in the array is initially 0, and may be replaced by a function
+*  pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
+*
+*  The handler for low and medium priority obeys ABI conventions so may be coded
+*  in C. For the exception handler, the cause is the contents of the EXCCAUSE
+*  reg, and the result is -1 if handled, else the cause (still needs handling).
+*  For interrupt handlers, the cause is a mask of pending enabled interrupts at
+*  that level, and the result is the same mask with the bits for the handled
+*  interrupts cleared (those not cleared still need handling). This allows a test
+*  case to either pre-handle or override the default handling for the exception
+*  or interrupt level (see xtensa_vectors.S).
+*
+*  High priority handlers (including NMI) must be coded in assembly, are always
+*  called by 'call0' regardless of ABI, must preserve all registers except a0,
+*  and must not use or modify the interrupted stack. The hook argument 'cause'
+*  is not passed and the result is ignored, so as not to burden the caller with
+*  saving and restoring a2 (it assumes only one interrupt per level - see the
+*  discussion in high priority interrupts in xtensa_vectors.S). The handler
+*  therefore should be coded to prototype 'void h(void)' even though it plugs
+*  into an array of handlers of prototype 'unsigned h(unsigned)'.
+*
+*  To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
+*
+*******************************************************************************/
+
+#define XT_INTEXC_HOOK_NUM    ( 1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI )
+
+#ifndef __ASSEMBLER__
+    typedef unsigned (* XT_INTEXC_HOOK)( unsigned cause );
+    extern volatile XT_INTEXC_HOOK _xt_intexc_hooks[ XT_INTEXC_HOOK_NUM ];
+#endif
+
+
+/*******************************************************************************
+*
+*  CONVENIENCE INCLUSIONS.
+*
+*  Ensures RTOS specific files need only include this one Xtensa-generic header.
+*  These headers are included last so they can use the RTOS definitions above.
+*
+*******************************************************************************/
+
+#include    "xtensa_context.h"
+
+#ifdef XT_RTOS_TIMER_INT
+    #include    "xtensa_timer.h"
+#endif
+
+
+/*******************************************************************************
+*
+*  Xtensa Port Version.
+*
+*******************************************************************************/
+
+#define XTENSA_PORT_VERSION           1.4 .2
+#define XTENSA_PORT_VERSION_STRING    "1.4.2"
+
+#endif /* XTENSA_RTOS_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/xtensa_timer.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/xtensa_timer.h
new file mode 100644
index 0000000..431205d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/include/xtensa_timer.h
@@ -0,0 +1,158 @@
+/*******************************************************************************
+*  // Copyright (c) 2003-2015 Cadence Design Systems, Inc.
+*  //
+*  // Permission is hereby granted, free of charge, to any person obtaining
+*  // a copy of this software and associated documentation files (the
+*  // "Software"), to deal in the Software without restriction, including
+*  // without limitation the rights to use, copy, modify, merge, publish,
+*  // distribute, sublicense, and/or sell copies of the Software, and to
+*  // permit persons to whom the Software is furnished to do so, subject to
+*  // the following conditions:
+*  //
+*  // The above copyright notice and this permission notice shall be included
+*  // in all copies or substantial portions of the Software.
+*  //
+*  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+*  // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+*  // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+*  // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+*  // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+*  // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+*  // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*  --------------------------------------------------------------------------------
+*
+*       XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
+*
+*  This header contains definitions and macros for use primarily by Xtensa
+*  RTOS assembly coded source files. It includes and uses the Xtensa hardware
+*  abstraction layer (HAL) to deal with config specifics. It may also be
+*  included in C source files.
+*
+*  User may edit to modify timer selection and to specify clock frequency and
+*  tick duration to match timer interrupt to the real-time tick duration.
+*
+*  If the RTOS has no timer interrupt, then there is no tick timer and the
+*  clock frequency is irrelevant, so all of these macros are left undefined
+*  and the Xtensa core configuration need not have a timer.
+*
+*******************************************************************************/
+
+#ifndef XTENSA_TIMER_H
+#define XTENSA_TIMER_H
+
+#ifdef __ASSEMBLER__
+    #include    <xtensa/coreasm.h>
+#endif
+
+#include    <xtensa/corebits.h>
+#include    <xtensa/config/system.h>
+
+#include    "xtensa_rtos.h" /* in case this wasn't included directly */
+
+#include    "FreeRTOSConfig.h"
+
+/*
+ * Select timer to use for periodic tick, and determine its interrupt number
+ * and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
+ * in which case its validity is checked (it must exist in this core and must
+ * not be on a high priority interrupt - an error will be reported in invalid).
+ * Otherwise select the first low or medium priority interrupt timer available.
+ */
+#if XCHAL_NUM_TIMERS == 0
+
+    #error "This Xtensa configuration is unsupported, it has no timers."
+
+#else
+
+    #ifndef XT_TIMER_INDEX
+        #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+            #if XCHAL_INT_LEVEL( XCHAL_TIMER3_INTERRUPT ) <= XCHAL_EXCM_LEVEL
+                #undef  XT_TIMER_INDEX
+                #define XT_TIMER_INDEX    3
+            #endif
+        #endif
+        #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+            #if XCHAL_INT_LEVEL( XCHAL_TIMER2_INTERRUPT ) <= XCHAL_EXCM_LEVEL
+                #undef  XT_TIMER_INDEX
+                #define XT_TIMER_INDEX    2
+            #endif
+        #endif
+        #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+            #if XCHAL_INT_LEVEL( XCHAL_TIMER1_INTERRUPT ) <= XCHAL_EXCM_LEVEL
+                #undef  XT_TIMER_INDEX
+                #define XT_TIMER_INDEX    1
+            #endif
+        #endif
+        #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+            #if XCHAL_INT_LEVEL( XCHAL_TIMER0_INTERRUPT ) <= XCHAL_EXCM_LEVEL
+                #undef  XT_TIMER_INDEX
+                #define XT_TIMER_INDEX    0
+            #endif
+        #endif
+    #endif /* ifndef XT_TIMER_INDEX */
+    #ifndef XT_TIMER_INDEX
+        #error "There is no suitable timer in this Xtensa configuration."
+    #endif
+
+    #define XT_CCOMPARE        ( CCOMPARE + XT_TIMER_INDEX )
+    #define XT_TIMER_INTNUM    XCHAL_TIMER_INTERRUPT( XT_TIMER_INDEX )
+    #define XT_TIMER_INTPRI    XCHAL_INT_LEVEL( XT_TIMER_INTNUM )
+    #define XT_TIMER_INTEN     ( 1 << XT_TIMER_INTNUM )
+
+    #if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
+        #error "The timer selected by XT_TIMER_INDEX does not exist in this core."
+    #elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
+        #error "The timer interrupt cannot be high priority (use medium or low)."
+    #endif
+
+#endif /* XCHAL_NUM_TIMERS */
+
+/*
+ * Set processor clock frequency, used to determine clock divisor for timer tick.
+ * User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
+ * If using a supported board via the board-independent API defined in xtbsp.h,
+ * this may be left undefined and frequency and tick divisor will be computed
+ * and cached during run-time initialization.
+ *
+ * NOTE ON SIMULATOR:
+ * Under the Xtensa instruction set simulator, the frequency can only be estimated
+ * because it depends on the speed of the host and the version of the simulator.
+ * Also because it runs much slower than hardware, it is not possible to achieve
+ * real-time performance for most applications under the simulator. A frequency
+ * too low does not allow enough time between timer interrupts, starving threads.
+ * To obtain a more convenient but non-real-time tick duration on the simulator,
+ * compile with xt-xcc option "-DXT_SIMULATOR".
+ * Adjust this frequency to taste (it's not real-time anyway!).
+ */
+#if defined( XT_SIMULATOR ) && !defined( XT_CLOCK_FREQ )
+    #define XT_CLOCK_FREQ    configCPU_CLOCK_HZ
+#endif
+
+#if !defined( XT_CLOCK_FREQ ) && !defined( XT_BOARD )
+    #error "XT_CLOCK_FREQ must be defined for the target platform."
+#endif
+
+/*
+ * Default number of timer "ticks" per second (default 100 for 10ms tick).
+ * RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
+ * User may redefine this to an optimal value for the application, either by
+ * editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
+ * "-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.
+ */
+#ifndef XT_TICK_PER_SEC
+    #define XT_TICK_PER_SEC    configTICK_RATE_HZ    /* 10 ms tick = 100 ticks per second */
+#endif
+
+/*
+ * Derivation of clock divisor for timer tick and interrupt (one per tick).
+ */
+#ifdef XT_CLOCK_FREQ
+    #define XT_TICK_DIVISOR    ( XT_CLOCK_FREQ / XT_TICK_PER_SEC )
+#endif
+
+#ifndef __ASSEMBLER__
+    extern unsigned _xt_tick_divisor;
+    extern void _xt_tick_divisor_init( void );
+#endif
+
+#endif /* XTENSA_TIMER_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/port.c
new file mode 100644
index 0000000..992789a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/port.c
@@ -0,0 +1,484 @@
+/*
+ *  FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
+ *  All rights reserved
+ *
+ *  VISIT https://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+ *
+ *  This file is part of the FreeRTOS distribution.
+ *
+ *  FreeRTOS is free software; you can redistribute it and/or modify it under
+ *  the terms of the GNU General Public License (version 2) as published by the
+ *  Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+ *
+ ***************************************************************************
+ *  >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+ *  >>!   distribute a combined work that includes FreeRTOS without being   !<<
+ *  >>!   obliged to provide the source code for proprietary components     !<<
+ *  >>!   outside of the FreeRTOS kernel.                                   !<<
+ ***************************************************************************
+ *
+ *  FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ *  WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ *  FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+ *  link: https://www.FreeRTOS.org/a00114.html
+ *
+ ***************************************************************************
+ *                                                                       *
+ *    FreeRTOS provides completely free yet professionally developed,    *
+ *    robust, strictly quality controlled, supported, and cross          *
+ *    platform software that is more than just the market leader, it     *
+ *    is the industry's de facto standard.                               *
+ *                                                                       *
+ *    Help yourself get started quickly while simultaneously helping     *
+ *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+ *    tutorial book, reference manual, or both:                          *
+ *    https://www.FreeRTOS.org/Documentation                             *
+ *                                                                       *
+ ***************************************************************************
+ *
+ *  https://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+ *  the FAQ page "My application does not run, what could be wrong?".  Have you
+ *  defined configASSERT()?
+ *
+ *  https://www.FreeRTOS.org/support - In return for receiving this top quality
+ *  embedded software for free we request you assist our global community by
+ *  participating in the support forum.
+ *
+ *  https://www.FreeRTOS.org/training - Investing in training allows your team
+ *  to be as productive as possible as early as possible.  Now you can receive
+ *  FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+ *  Ltd, and the world's leading authority on the world's leading RTOS.
+ *
+ *  https://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+ *  including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+ *  compatible FAT file system, and our tiny thread aware UDP/IP stack.
+ *
+ *  https://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+ *  Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+ *
+ *  https://www.highintegritysystems.com/openrtos/ - Real Time Engineers ltd.
+ *  license FreeRTOS to High Integrity Systems ltd. to sell under the OpenRTOS
+ *  brand.  Low cost OpenRTOS licenses offer ticketed support, indemnification
+ *  and commercial middleware.
+ *
+ *  https://www.highintegritysystems.com/safertos/ - High Integrity Systems
+ *  also provide a safety engineered and independently SIL3 certified version
+ *  for use in safety and mission critical applications that require provable
+ *  dependability.
+ *
+ */
+
+/*******************************************************************************
+ * // Copyright (c) 2003-2015 Cadence Design Systems, Inc.
+ * //
+ * // Permission is hereby granted, free of charge, to any person obtaining
+ * // a copy of this software and associated documentation files (the
+ * // "Software"), to deal in the Software without restriction, including
+ * // without limitation the rights to use, copy, modify, merge, publish,
+ * // distribute, sublicense, and/or sell copies of the Software, and to
+ * // permit persons to whom the Software is furnished to do so, subject to
+ * // the following conditions:
+ * //
+ * // The above copyright notice and this permission notice shall be included
+ * // in all copies or substantial portions of the Software.
+ * //
+ * // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ * -----------------------------------------------------------------------------
+ */
+
+#include <stdlib.h>
+#include <xtensa/config/core.h>
+
+#include "xtensa_rtos.h"
+
+#include "rom/ets_sys.h"
+#include "soc/cpu.h"
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#include "esp_panic.h"
+#include "esp_heap_caps.h"
+#include "esp_crosscore_int.h"
+
+#include "esp_intr_alloc.h"
+
+/* Defined in portasm.h */
+extern void _frxt_tick_timer_init( void );
+
+/* Defined in xtensa_context.S */
+extern void _xt_coproc_init( void );
+
+
+#if CONFIG_FREERTOS_CORETIMER_0
+    #define SYSTICK_INTR_ID    ( ETS_INTERNAL_TIMER0_INTR_SOURCE + ETS_INTERNAL_INTR_SOURCE_OFF )
+#endif
+#if CONFIG_FREERTOS_CORETIMER_1
+    #define SYSTICK_INTR_ID    ( ETS_INTERNAL_TIMER1_INTR_SOURCE + ETS_INTERNAL_INTR_SOURCE_OFF )
+#endif
+
+/*-----------------------------------------------------------*/
+
+unsigned port_xSchedulerRunning[ portNUM_PROCESSORS ] = { 0 }; /* Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting */
+unsigned port_interruptNesting[ portNUM_PROCESSORS ] = { 0 };  /* Interrupt nesting level. Increased/decreased in portasm.c, _frxt_int_enter/_frxt_int_exit */
+
+/*-----------------------------------------------------------*/
+
+/* User exception dispatcher when exiting */
+void _xt_user_exit( void );
+
+/*
+ * Stack initialization
+ */
+/* *INDENT-OFF* */
+#if portUSING_MPU_WRAPPERS
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters,
+                                         BaseType_t xRunPrivileged )
+#else
+    StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
+                                         TaskFunction_t pxCode,
+                                         void * pvParameters )
+#endif
+/* *INDENT-ON* */
+{
+    StackType_t * sp, * tp;
+    XtExcFrame * frame;
+
+    #if XCHAL_CP_NUM > 0
+        uint32_t * p;
+    #endif
+
+    /* Create interrupt stack frame aligned to 16 byte boundary */
+    sp = ( StackType_t * ) ( ( ( UBaseType_t ) pxTopOfStack - XT_CP_SIZE - XT_STK_FRMSZ ) & ~0xf );
+
+    /* Clear the entire frame (do not use memset() because we don't depend on C library) */
+    for( tp = sp; tp <= pxTopOfStack; ++tp )
+    {
+        *tp = 0;
+    }
+
+    frame = ( XtExcFrame * ) sp;
+
+    /* Explicitly initialize certain saved registers */
+    frame->pc = ( UBaseType_t ) pxCode;             /* task entrypoint                */
+    frame->a0 = 0;                                  /* to terminate GDB backtrace     */
+    frame->a1 = ( UBaseType_t ) sp + XT_STK_FRMSZ;  /* physical top of stack frame    */
+    frame->exit = ( UBaseType_t ) _xt_user_exit;    /* user exception exit dispatcher */
+
+    /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */
+    /* Also set entry point argument parameter. */
+    #ifdef __XTENSA_CALL0_ABI__
+        frame->a2 = ( UBaseType_t ) pvParameters;
+        frame->ps = PS_UM | PS_EXCM;
+    #else
+        /* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */
+        frame->a6 = ( UBaseType_t ) pvParameters;
+        frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC( 1 );
+    #endif
+
+    #ifdef XT_USE_SWPRI
+        /* Set the initial virtual priority mask value to all 1's. */
+        frame->vpri = 0xFFFFFFFF;
+    #endif
+
+    #if XCHAL_CP_NUM > 0
+        /* Init the coprocessor save area (see xtensa_context.h) */
+
+        /* No access to TCB here, so derive indirectly. Stack growth is top to bottom.
+         * //p = (uint32_t *) xMPUSettings->coproc_area;
+         */
+        p = ( uint32_t * ) ( ( ( uint32_t ) pxTopOfStack - XT_CP_SIZE ) & ~0xf );
+        configASSERT( ( uint32_t ) p >= frame->a1 );
+        p[ 0 ] = 0;
+        p[ 1 ] = 0;
+        p[ 2 ] = ( ( ( uint32_t ) p ) + 12 + XCHAL_TOTAL_SA_ALIGN - 1 ) & -XCHAL_TOTAL_SA_ALIGN;
+    #endif
+
+    return sp;
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+    /* It is unlikely that the Xtensa port will get stopped.  If required simply
+     * disable the tick interrupt here. */
+}
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+    /* Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored */
+
+    #if XCHAL_CP_NUM > 0
+        /* Initialize co-processor management for tasks. Leave CPENABLE alone. */
+        _xt_coproc_init();
+    #endif
+
+    /* Init the tick divisor value */
+    _xt_tick_divisor_init();
+
+    /* Setup the hardware to generate the tick. */
+    _frxt_tick_timer_init();
+
+    port_xSchedulerRunning[ xPortGetCoreID() ] = 1;
+
+    /* Cannot be directly called from C; never returns */
+    __asm__ volatile ( "call0    _frxt_dispatch\n" );
+
+    /* Should not get here. */
+    return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortSysTickHandler( void )
+{
+    BaseType_t ret;
+    unsigned interruptMask;
+
+    portbenchmarkIntLatency();
+    traceISR_ENTER( SYSTICK_INTR_ID );
+
+    /* Interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY must be
+     * disabled before calling xTaskIncrementTick as it access the
+     * kernel lists. */
+    interruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        ret = xTaskIncrementTick();
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( interruptMask );
+
+    if( ret != pdFALSE )
+    {
+        portYIELD_FROM_ISR();
+    }
+    else
+    {
+        traceISR_EXIT();
+    }
+
+    return ret;
+}
+
+
+void vPortYieldOtherCore( BaseType_t coreid )
+{
+    esp_crosscore_int_send_yield( coreid );
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area.
+ */
+#if portUSING_MPU_WRAPPERS
+    void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                    const struct xMEMORY_REGION * const xRegions,
+                                    StackType_t * pxBottomOfStack,
+                                    uint32_t usStackDepth )
+    {
+        #if XCHAL_CP_NUM > 0
+            xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + usStackDepth - 1 ));
+            xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+            xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
+
+                
+            /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
+             * clear the stack area after we return. This is done in pxPortInitialiseStack().
+             */
+        #endif
+    }
+
+    void vPortReleaseTaskMPUSettings( xMPU_SETTINGS * xMPUSettings )
+    {
+        /* If task has live floating point registers somewhere, release them */
+        _xt_coproc_release( xMPUSettings->coproc_area );
+    }
+
+#endif /* if portUSING_MPU_WRAPPERS */
+
+/*
+ * Returns true if the current core is in ISR context; low prio ISR, med prio ISR or timer tick ISR. High prio ISRs
+ * aren't detected here, but they normally cannot call C code, so that should not be an issue anyway.
+ */
+BaseType_t xPortInIsrContext()
+{
+    unsigned int irqStatus;
+    BaseType_t ret;
+
+    irqStatus = portENTER_CRITICAL_NESTED();
+    ret = ( port_interruptNesting[ xPortGetCoreID() ] != 0 );
+    portEXIT_CRITICAL_NESTED( irqStatus );
+    return ret;
+}
+
+/*
+ * This function will be called in High prio ISRs. Returns true if the current core was in ISR context
+ * before calling into high prio ISR context.
+ */
+BaseType_t IRAM_ATTR xPortInterruptedFromISRContext()
+{
+    return( port_interruptNesting[ xPortGetCoreID() ] != 0 );
+}
+
+void vPortAssertIfInISR()
+{
+    if( xPortInIsrContext() )
+    {
+        ets_printf( "core=%d port_interruptNesting=%d\n\n", xPortGetCoreID(), port_interruptNesting[ xPortGetCoreID() ] );
+    }
+
+    configASSERT( !xPortInIsrContext() );
+}
+
+/*
+ * For kernel use: Initialize a per-CPU mux. Mux will be initialized unlocked.
+ */
+void vPortCPUInitializeMutex( portMUX_TYPE * mux )
+{
+    #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+        ets_printf( "Initializing mux %p\n", mux );
+        mux->lastLockedFn = "(never locked)";
+        mux->lastLockedLine = -1;
+    #endif
+    mux->owner = portMUX_FREE_VAL;
+    mux->count = 0;
+}
+
+#include "portmux_impl.h"
+
+/*
+ * For kernel use: Acquire a per-CPU mux. Spinlocks, so don't hold on to these muxes for too long.
+ */
+#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+    void vPortCPUAcquireMutex( portMUX_TYPE * mux,
+                               const char * fnName,
+                               int line )
+    {
+        unsigned int irqStatus = portENTER_CRITICAL_NESTED();
+
+        vPortCPUAcquireMutexIntsDisabled( mux, portMUX_NO_TIMEOUT, fnName, line );
+        portEXIT_CRITICAL_NESTED( irqStatus );
+    }
+
+    bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux,
+                                      int timeout_cycles,
+                                      const char * fnName,
+                                      int line )
+    {
+        unsigned int irqStatus = portENTER_CRITICAL_NESTED();
+        bool result = vPortCPUAcquireMutexIntsDisabled( mux, timeout_cycles, fnName, line );
+
+        portEXIT_CRITICAL_NESTED( irqStatus );
+        return result;
+    }
+
+#else /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
+    void vPortCPUAcquireMutex( portMUX_TYPE * mux )
+    {
+        unsigned int irqStatus = portENTER_CRITICAL_NESTED();
+
+        vPortCPUAcquireMutexIntsDisabled( mux, portMUX_NO_TIMEOUT );
+        portEXIT_CRITICAL_NESTED( irqStatus );
+    }
+
+    bool vPortCPUAcquireMutexTimeout( portMUX_TYPE * mux,
+                                      int timeout_cycles )
+    {
+        unsigned int irqStatus = portENTER_CRITICAL_NESTED();
+        bool result = vPortCPUAcquireMutexIntsDisabled( mux, timeout_cycles );
+
+        portEXIT_CRITICAL_NESTED( irqStatus );
+        return result;
+    }
+#endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
+
+
+/*
+ * For kernel use: Release a per-CPU mux
+ *
+ * Mux must be already locked by this core
+ */
+#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+    void vPortCPUReleaseMutex( portMUX_TYPE * mux,
+                               const char * fnName,
+                               int line )
+    {
+        unsigned int irqStatus = portENTER_CRITICAL_NESTED();
+
+        vPortCPUReleaseMutexIntsDisabled( mux, fnName, line );
+        portEXIT_CRITICAL_NESTED( irqStatus );
+    }
+#else
+    void vPortCPUReleaseMutex( portMUX_TYPE * mux )
+    {
+        unsigned int irqStatus = portENTER_CRITICAL_NESTED();
+
+        vPortCPUReleaseMutexIntsDisabled( mux );
+        portEXIT_CRITICAL_NESTED( irqStatus );
+    }
+#endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
+
+void vPortSetStackWatchpoint( void * pxStackStart )
+{
+    /*Set watchpoint 1 to watch the last 32 bytes of the stack. */
+    /*Unfortunately, the Xtensa watchpoints can't set a watchpoint on a random [base - base+n] region because */
+    /*the size works by masking off the lowest address bits. For that reason, we futz a bit and watch the lowest 32 */
+    /*bytes of the stack we can actually watch. In general, this can cause the watchpoint to be triggered at most */
+    /*28 bytes early. The value 32 is chosen because it's larger than the stack canary, which in FreeRTOS is 20 bytes. */
+    /*This way, we make sure we trigger before/when the stack canary is corrupted, not after. */
+    int addr = ( int ) pxStackStart;
+
+    addr = ( addr + 31 ) & ( ~31 );
+    esp_set_watchpoint( 1, ( char * ) addr, 32, ESP_WATCHPOINT_STORE );
+}
+
+#if defined( CONFIG_SPIRAM_SUPPORT )
+
+/*
+ * Compare & set (S32C1) does not work in external RAM. Instead, this routine uses a mux (in internal memory) to fake it.
+ */
+    static portMUX_TYPE extram_mux = portMUX_INITIALIZER_UNLOCKED;
+
+    void uxPortCompareSetExtram( volatile uint32_t * addr,
+                                 uint32_t compare,
+                                 uint32_t * set )
+    {
+        uint32_t prev;
+
+        #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+            vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT, __FUNCTION__, __LINE__ );
+        #else
+            vPortCPUAcquireMutexIntsDisabled( &extram_mux, portMUX_NO_TIMEOUT );
+        #endif
+        prev = *addr;
+
+        if( prev == compare )
+        {
+            *addr = *set;
+        }
+
+        *set = prev;
+        #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+            vPortCPUReleaseMutexIntsDisabled( &extram_mux, __FUNCTION__, __LINE__ );
+        #else
+            vPortCPUReleaseMutexIntsDisabled( &extram_mux );
+        #endif
+    }
+#endif //defined(CONFIG_SPIRAM_SUPPORT)
+
+
+
+uint32_t xPortGetTickRateHz( void )
+{
+    return ( uint32_t ) configTICK_RATE_HZ;
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/portasm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/portasm.S
new file mode 100644
index 0000000..b43e9be
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/portasm.S
@@ -0,0 +1,653 @@
+/*
+//-----------------------------------------------------------------------------
+// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
+//
+// Permission is hereby granted, free of charge, to any person obtaining
+// a copy of this software and associated documentation files (the
+// "Software"), to deal in the Software without restriction, including
+// without limitation the rights to use, copy, modify, merge, publish,
+// distribute, sublicense, and/or sell copies of the Software, and to
+// permit persons to whom the Software is furnished to do so, subject to
+// the following conditions:
+//
+// The above copyright notice and this permission notice shall be included
+// in all copies or substantial portions of the Software.
+//
+// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+//-----------------------------------------------------------------------------
+*/
+
+#include "xtensa_rtos.h"
+#include "sdkconfig.h"
+
+#define TOPOFSTACK_OFFS                 0x00    /* StackType_t *pxTopOfStack */
+#define CP_TOPOFSTACK_OFFS              0x04    /* xMPU_SETTINGS.coproc_area */
+
+.extern pxCurrentTCB
+
+/*
+*******************************************************************************
+* Interrupt stack. The size of the interrupt stack is determined by the config
+* parameter "configISR_STACK_SIZE" in FreeRTOSConfig.h
+*******************************************************************************
+*/
+
+    .data
+    .align      16
+    .global     port_IntStack
+    .global     port_IntStackTop
+    .global     port_switch_flag
+port_IntStack:
+    .space      configISR_STACK_SIZE*portNUM_PROCESSORS		/* This allocates stacks for each individual CPU. */
+port_IntStackTop:
+    .word		0
+port_switch_flag:
+    .space      portNUM_PROCESSORS*4 /* One flag for each individual CPU. */
+
+    .text
+
+/*
+*******************************************************************************
+* _frxt_setup_switch
+* void _frxt_setup_switch(void);
+* 
+* Sets an internal flag indicating that a task switch is required on return
+* from interrupt handling.
+* 
+*******************************************************************************
+*/
+    .global     _frxt_setup_switch
+    .type       _frxt_setup_switch,@function
+    .align      4
+_frxt_setup_switch:
+
+    ENTRY(16)
+
+	getcoreid a3
+    movi    a2, port_switch_flag
+	addx4	a2,  a3, a2
+
+    movi    a3, 1
+    s32i    a3, a2, 0
+
+    RET(16)
+
+
+
+
+
+
+/*
+*******************************************************************************
+* _frxt_int_enter
+* void _frxt_int_enter(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for
+* freeRTOS. Saves the rest of the interrupt context (not already saved).
+* May only be called from assembly code by the 'call0' instruction, with
+* interrupts disabled.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+*******************************************************************************
+*/
+    .globl  _frxt_int_enter
+    .type   _frxt_int_enter,@function
+    .align  4
+_frxt_int_enter:
+
+    /* Save a12-13 in the stack frame as required by _xt_context_save. */
+    s32i    a12, a1, XT_STK_A12
+    s32i    a13, a1, XT_STK_A13
+
+    /* Save return address in a safe place (free a0). */
+    mov     a12, a0
+
+    /* Save the rest of the interrupted context (preserves A12-13). */
+    call0   _xt_context_save
+
+    /*
+    Save interrupted task's SP in TCB only if not nesting.
+    Manage nesting directly rather than call the generic IntEnter()
+    (in windowed ABI we can't call a C function here anyway because PS.EXCM is still set).
+    */
+	getcoreid a4
+    movi    a2,  port_xSchedulerRunning
+	addx4	a2,  a4, a2
+    movi    a3,  port_interruptNesting
+	addx4	a3,  a4, a3
+    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
+    beqz    a2,  1f                     /* scheduler not running, no tasks */
+    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
+    addi    a2,  a2, 1                  /* increment nesting count         */
+    s32i    a2,  a3, 0                  /* save nesting count              */
+    bnei    a2,  1, .Lnested            /* !=0 before incr, so nested      */
+
+    movi    a2,  pxCurrentTCB
+	addx4	a2,  a4, a2
+    l32i    a2,  a2, 0                  /* a2 = current TCB                */
+    beqz    a2,  1f
+    s32i    a1,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP */
+    movi    a1,  port_IntStack+configISR_STACK_SIZE   /* a1 = top of intr stack for CPU 0  */
+    movi    a2,  configISR_STACK_SIZE   /* add configISR_STACK_SIZE * cpu_num to arrive at top of stack for cpu_num */
+	mull	a2,  a4, a2
+	add     a1,  a1, a2					/* for current proc */
+
+.Lnested:
+1:
+    mov     a0,  a12                    /* restore return addr and return  */
+    ret
+
+/*
+*******************************************************************************
+* _frxt_int_exit
+* void _frxt_int_exit(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for
+* FreeRTOS. If required, calls vPortYieldFromInt() to perform task context
+* switching, restore the (possibly) new task's context, and return to the
+* exit dispatcher saved in the task's stack frame at XT_STK_EXIT.
+* May only be called from assembly code by the 'call0' instruction. Does not
+* return to caller.
+* See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+*******************************************************************************
+*/
+    .globl  _frxt_int_exit
+    .type   _frxt_int_exit,@function
+    .align  4
+_frxt_int_exit:
+
+	getcoreid a4
+    movi    a2,  port_xSchedulerRunning
+	addx4	a2,  a4, a2
+    movi    a3,  port_interruptNesting
+	addx4	a3,  a4, a3
+    rsil    a0,  XCHAL_EXCM_LEVEL       /* lock out interrupts             */
+    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
+    beqz    a2,  .Lnoswitch             /* scheduler not running, no tasks */
+    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
+    addi    a2,  a2, -1                 /* decrement nesting count         */
+    s32i    a2,  a3, 0                  /* save nesting count              */
+    bnez    a2,  .Lnesting              /* !=0 after decr so still nested  */
+
+    movi    a2,  pxCurrentTCB
+	addx4	a2,  a4, a2
+    l32i    a2,  a2, 0                  /* a2 = current TCB                */
+    beqz    a2,  1f                     /* no task ? go to dispatcher      */
+    l32i    a1,  a2, TOPOFSTACK_OFFS    /* SP = pxCurrentTCB->pxTopOfStack */
+
+    movi    a2,  port_switch_flag       /* address of switch flag          */
+	addx4	a2,  a4, a2					/* point to flag for this cpu      */
+    l32i    a3,  a2, 0                  /* a3 = port_switch_flag           */
+    beqz    a3,  .Lnoswitch             /* flag = 0 means no switch reqd   */
+    movi    a3,  0
+    s32i    a3,  a2, 0                  /* zero out the flag for next time */
+
+1:
+    /*
+    Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption.
+    However a12-13 were already saved by _frxt_int_enter().
+    */
+    #ifdef __XTENSA_CALL0_ABI__
+    s32i    a14, a1, XT_STK_A14
+    s32i    a15, a1, XT_STK_A15
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   vPortYieldFromInt       /* call dispatch inside the function; never returns */
+    #else
+    call4   vPortYieldFromInt       /* this one returns */
+    call0   _frxt_dispatch          /* tail-call dispatcher */
+    /* Never returns here. */
+    #endif
+
+.Lnoswitch:
+    /*
+    If we came here then about to resume the interrupted task.
+    */
+
+.Lnesting:
+    /*
+    We come here only if there was no context switch, that is if this
+    is a nested interrupt, or the interrupted task was not preempted.
+    In either case there's no need to load the SP.
+    */
+
+    /* Restore full context from interrupt stack frame */
+    call0   _xt_context_restore
+
+    /*
+    Must return via the exit dispatcher corresponding to the entrypoint from which
+    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
+    stack frame is deallocated in the exit dispatcher.
+    */
+    l32i    a0,  a1, XT_STK_EXIT
+    ret
+
+
+/*
+**********************************************************************************************************
+*                                           _frxt_timer_int
+*                                      void _frxt_timer_int(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS.
+* Called every timer interrupt.
+* Manages the tick timer and calls xPortSysTickHandler() every tick.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+* Callable from C (obeys ABI conventions). Implemented in assmebly code for performance.
+*
+**********************************************************************************************************
+*/
+    .globl  _frxt_timer_int
+    .type   _frxt_timer_int,@function
+    .align  4
+_frxt_timer_int:
+
+    /*
+    Xtensa timers work by comparing a cycle counter with a preset value.  Once the match occurs
+    an interrupt is generated, and the handler has to set a new cycle count into the comparator.
+    To avoid clock drift due to interrupt latency, the new cycle count is computed from the old,
+    not the time the interrupt was serviced. However if a timer interrupt is ever serviced more
+    than one tick late, it is necessary to process multiple ticks until the new cycle count is
+    in the future, otherwise the next timer interrupt would not occur until after the cycle
+    counter had wrapped (2^32 cycles later).
+
+    do {
+        ticks++;
+        old_ccompare = read_ccompare_i();
+        write_ccompare_i( old_ccompare + divisor );
+        service one tick;
+        diff = read_ccount() - old_ccompare;
+    } while ( diff > divisor );
+    */
+
+    ENTRY(16)
+
+    #ifdef CONFIG_PM_TRACE
+    movi a6, 1 /* = ESP_PM_TRACE_TICK */
+    getcoreid a7
+    call4 esp_pm_trace_enter
+    #endif // CONFIG_PM_TRACE
+
+.L_xt_timer_int_catchup:
+
+    /* Update the timer comparator for the next tick. */
+    #ifdef XT_CLOCK_FREQ
+    movi    a2, XT_TICK_DIVISOR         /* a2 = comparator increment          */
+    #else
+    movi    a3, _xt_tick_divisor
+    l32i    a2, a3, 0                   /* a2 = comparator increment          */
+    #endif
+    rsr     a3, XT_CCOMPARE             /* a3 = old comparator value          */
+    add     a4, a3, a2                  /* a4 = new comparator value          */
+    wsr     a4, XT_CCOMPARE             /* update comp. and clear interrupt   */
+    esync
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Preserve a2 and a3 across C calls. */
+    s32i    a2, sp, 4
+    s32i    a3, sp, 8
+    #endif
+
+    /* Call the FreeRTOS tick handler (see port.c). */
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   xPortSysTickHandler
+    #else
+    call4   xPortSysTickHandler
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Restore a2 and a3. */
+    l32i    a2, sp, 4
+    l32i    a3, sp, 8
+    #endif
+
+    /* Check if we need to process more ticks to catch up. */
+    esync                               /* ensure comparator update complete  */
+    rsr     a4, CCOUNT                  /* a4 = cycle count                   */
+    sub     a4, a4, a3                  /* diff = ccount - old comparator     */
+    blt     a2, a4, .L_xt_timer_int_catchup  /* repeat while diff > divisor */
+
+#ifdef CONFIG_PM_TRACE
+    movi a6, 1 /* = ESP_PM_TRACE_TICK */
+    getcoreid a7
+    call4 esp_pm_trace_exit
+#endif // CONFIG_PM_TRACE
+
+    RET(16)
+
+    /*
+**********************************************************************************************************
+*                                           _frxt_tick_timer_init
+*                                      void _frxt_tick_timer_init(void)
+*
+* Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called).
+* Callable from C (obeys ABI conventions on entry).
+*
+**********************************************************************************************************
+*/
+    .globl  _frxt_tick_timer_init
+    .type   _frxt_tick_timer_init,@function
+    .align  4
+_frxt_tick_timer_init:
+
+    ENTRY(16)
+
+
+    /* Set up the periodic tick timer (assume enough time to complete init). */
+    #ifdef XT_CLOCK_FREQ
+    movi    a3, XT_TICK_DIVISOR
+    #else
+    movi    a2, _xt_tick_divisor
+    l32i    a3, a2, 0
+    #endif
+    rsr     a2, CCOUNT              /* current cycle count */
+    add     a2, a2, a3              /* time of first timer interrupt */
+    wsr     a2, XT_CCOMPARE         /* set the comparator */
+
+    /*
+    Enable the timer interrupt at the device level. Don't write directly
+    to the INTENABLE register because it may be virtualized.
+    */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a2, XT_TIMER_INTEN
+    call0   xt_ints_on
+    #else
+    movi    a6, XT_TIMER_INTEN
+    call4   xt_ints_on
+    #endif
+
+    RET(16)
+
+/*
+**********************************************************************************************************
+*                                    DISPATCH THE HIGH READY TASK
+*                                     void _frxt_dispatch(void)
+*
+* Switch context to the highest priority ready task, restore its state and dispatch control to it.
+*
+* This is a common dispatcher that acts as a shared exit path for all the context switch functions
+* including vPortYield() and vPortYieldFromInt(), all of which tail-call this dispatcher
+* (for windowed ABI vPortYieldFromInt() calls it indirectly via _frxt_int_exit() ).
+*
+* The Xtensa port uses different stack frames for solicited and unsolicited task suspension (see
+* comments on stack frames in xtensa_context.h). This function restores the state accordingly.
+* If restoring a task that solicited entry, restores the minimal state and leaves CPENABLE clear.
+* If restoring a task that was preempted, restores all state including the task's CPENABLE.
+*
+* Entry:
+*   pxCurrentTCB  points to the TCB of the task to suspend,
+*   Because it is tail-called without a true function entrypoint, it needs no 'entry' instruction.
+*
+* Exit:
+*   If incoming task called vPortYield() (solicited), this function returns as if from vPortYield().
+*   If incoming task was preempted by an interrupt, this function jumps to exit dispatcher.
+*
+**********************************************************************************************************
+*/
+    .globl  _frxt_dispatch
+    .type   _frxt_dispatch,@function
+    .align  4
+_frxt_dispatch:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   vTaskSwitchContext  // Get next TCB to resume
+    movi    a2, pxCurrentTCB
+	getcoreid a3
+	addx4	a2,  a3, a2
+    #else
+    call4   vTaskSwitchContext  // Get next TCB to resume
+    movi    a2, pxCurrentTCB
+	getcoreid a3
+	addx4	a2,  a3, a2
+    #endif
+    l32i    a3,  a2, 0
+    l32i    sp,  a3, TOPOFSTACK_OFFS     /* SP = next_TCB->pxTopOfStack;  */
+    s32i    a3,  a2, 0
+
+    /* Determine the type of stack frame. */
+    l32i    a2,  sp, XT_STK_EXIT        /* exit dispatcher or solicited flag */
+    bnez    a2,  .L_frxt_dispatch_stk
+
+.L_frxt_dispatch_sol:
+
+    /* Solicited stack frame. Restore minimal context and return from vPortYield(). */
+    l32i    a3,  sp, XT_SOL_PS
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a12, sp, XT_SOL_A12
+    l32i    a13, sp, XT_SOL_A13
+    l32i    a14, sp, XT_SOL_A14
+    l32i    a15, sp, XT_SOL_A15
+    #endif
+    l32i    a0,  sp, XT_SOL_PC
+    #if XCHAL_CP_NUM > 0
+    /* Ensure wsr.CPENABLE is complete (should be, it was cleared on entry). */
+    rsync
+    #endif
+    /* As soons as PS is restored, interrupts can happen. No need to sync PS. */
+    wsr     a3,  PS
+    #ifdef __XTENSA_CALL0_ABI__
+    addi    sp,  sp, XT_SOL_FRMSZ
+    ret
+    #else
+    retw
+    #endif
+
+.L_frxt_dispatch_stk:
+
+    #if XCHAL_CP_NUM > 0
+    /* Restore CPENABLE from task's co-processor save area. */
+    movi    a3, pxCurrentTCB            /* cp_state =                       */
+	getcoreid a2
+	addx4	a3,  a2, a3
+    l32i    a3, a3, 0
+    l32i    a2, a3, CP_TOPOFSTACK_OFFS     /* StackType_t                       *pxStack; */
+    l16ui   a3, a2, XT_CPENABLE         /* CPENABLE = cp_state->cpenable;   */
+    wsr     a3, CPENABLE
+    #endif
+
+    /* Interrupt stack frame. Restore full context and return to exit dispatcher. */
+    call0   _xt_context_restore
+
+    /* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a14, sp, XT_STK_A14
+    l32i    a15, sp, XT_STK_A15
+    #endif
+
+    #if XCHAL_CP_NUM > 0
+    /* Ensure wsr.CPENABLE has completed. */
+    rsync
+    #endif
+
+    /*
+    Must return via the exit dispatcher corresponding to the entrypoint from which
+    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
+    stack frame is deallocated in the exit dispatcher.
+    */
+    l32i    a0, sp, XT_STK_EXIT
+    ret
+
+
+/*
+**********************************************************************************************************
+*                            PERFORM A SOLICTED CONTEXT SWITCH (from a task)
+*                                        void vPortYield(void)
+*
+* This function saves the minimal state needed for a solicited task suspension, clears CPENABLE,
+* then tail-calls the dispatcher _frxt_dispatch() to perform the actual context switch
+*
+* At Entry:
+*   pxCurrentTCB  points to the TCB of the task to suspend
+*   Callable from C (obeys ABI conventions on entry).
+*
+* Does not return to caller.
+*
+**********************************************************************************************************
+*/
+    .globl  vPortYield
+    .type   vPortYield,@function
+    .align  4
+vPortYield:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    addi    sp,  sp, -XT_SOL_FRMSZ
+    #else
+    entry   sp,  XT_SOL_FRMSZ
+    #endif
+
+    rsr     a2,  PS
+    s32i    a0,  sp, XT_SOL_PC
+    s32i    a2,  sp, XT_SOL_PS
+    #ifdef __XTENSA_CALL0_ABI__
+    s32i    a12, sp, XT_SOL_A12         /* save callee-saved registers      */
+    s32i    a13, sp, XT_SOL_A13
+    s32i    a14, sp, XT_SOL_A14
+    s32i    a15, sp, XT_SOL_A15
+    #else
+    /* Spill register windows. Calling xthal_window_spill() causes extra    */
+    /* spills and reloads, so we will set things up to call the _nw version */
+    /* instead to save cycles.                                              */
+    movi    a6,  ~(PS_WOE_MASK|PS_INTLEVEL_MASK)  /* spills a4-a7 if needed */
+    and     a2,  a2, a6                           /* clear WOE, INTLEVEL    */
+    addi    a2,  a2, XCHAL_EXCM_LEVEL             /* set INTLEVEL           */
+    wsr     a2,  PS
+    rsync
+    call0   xthal_window_spill_nw
+    l32i    a2,  sp, XT_SOL_PS                    /* restore PS             */
+    wsr     a2,  PS
+    #endif
+
+    rsil    a2,  XCHAL_EXCM_LEVEL       /* disable low/med interrupts       */
+
+    #if XCHAL_CP_NUM > 0
+    /* Save coprocessor callee-saved state (if any). At this point CPENABLE */
+    /* should still reflect which CPs were in use (enabled).                */
+    call0   _xt_coproc_savecs
+    #endif
+
+    movi    a2,  pxCurrentTCB
+	getcoreid a3
+	addx4	a2,  a3, a2
+    l32i    a2,  a2, 0                  /* a2 = pxCurrentTCB                */
+    movi    a3,  0
+    s32i    a3,  sp, XT_SOL_EXIT        /* 0 to flag as solicited frame     */
+    s32i    sp,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP  */
+
+    #if XCHAL_CP_NUM > 0
+    /* Clear CPENABLE, also in task's co-processor state save area. */
+    l32i    a2,  a2, CP_TOPOFSTACK_OFFS /* a2 = pxCurrentTCB->cp_state      */
+    movi    a3,  0
+    wsr     a3,  CPENABLE
+    beqz    a2,  1f
+    s16i    a3,  a2, XT_CPENABLE        /* clear saved cpenable             */
+1:
+    #endif
+
+    /* Tail-call dispatcher. */
+    call0   _frxt_dispatch
+    /* Never reaches here. */
+
+
+/*
+**********************************************************************************************************
+*                         PERFORM AN UNSOLICITED CONTEXT SWITCH (from an interrupt)
+*                                        void vPortYieldFromInt(void)
+*
+* This calls the context switch hook (removed), saves and clears CPENABLE, then tail-calls the dispatcher
+* _frxt_dispatch() to perform the actual context switch.
+*
+* At Entry:
+*   Interrupted task context has been saved in an interrupt stack frame at pxCurrentTCB->pxTopOfStack.
+*   pxCurrentTCB  points to the TCB of the task to suspend,
+*   Callable from C (obeys ABI conventions on entry).
+*
+* At Exit:
+*   Windowed ABI defers the actual context switch until the stack is unwound to interrupt entry.
+*   Call0 ABI tail-calls the dispatcher directly (no need to unwind) so does not return to caller.
+*
+**********************************************************************************************************
+*/
+    .globl  vPortYieldFromInt
+    .type   vPortYieldFromInt,@function
+    .align  4
+vPortYieldFromInt:
+
+    ENTRY(16)
+
+    #if XCHAL_CP_NUM > 0
+    /* Save CPENABLE in task's co-processor save area, and clear CPENABLE.  */
+    movi    a3, pxCurrentTCB            /* cp_state =                       */
+	getcoreid a2
+	addx4	a3,  a2, a3
+    l32i    a3, a3, 0
+
+    l32i    a2, a3, CP_TOPOFSTACK_OFFS
+
+    rsr     a3, CPENABLE
+    s16i    a3, a2, XT_CPENABLE         /* cp_state->cpenable = CPENABLE;   */
+    movi    a3, 0
+    wsr     a3, CPENABLE                /* disable all co-processors        */
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Tail-call dispatcher. */
+    call0   _frxt_dispatch
+    /* Never reaches here. */
+    #else
+    RET(16)
+    #endif
+
+/*
+**********************************************************************************************************
+*                                        _frxt_task_coproc_state
+*                                   void _frxt_task_coproc_state(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function for FreeRTOS.
+*
+* May only be called when a task is running, not within an interrupt handler (returns 0 in that case).
+* May only be called from assembly code by the 'call0' instruction. Does NOT obey ABI conventions.
+* Returns in A15 a pointer to the base of the co-processor state save area for the current task.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+**********************************************************************************************************
+*/
+#if XCHAL_CP_NUM > 0
+
+    .globl  _frxt_task_coproc_state
+    .type   _frxt_task_coproc_state,@function
+    .align  4
+_frxt_task_coproc_state:
+
+
+	/* We can use a3 as a scratchpad, the instances of code calling XT_RTOS_CP_STATE don't seem to need it saved. */
+	getcoreid a3
+    movi    a15, port_xSchedulerRunning /* if (port_xSchedulerRunning              */
+	addx4	a15, a3,a15
+    l32i    a15, a15, 0
+    beqz    a15, 1f
+    movi    a15, port_interruptNesting  /* && port_interruptNesting == 0           */
+	addx4	a15, a3, a15
+    l32i    a15, a15, 0
+    bnez    a15, 1f
+
+    movi    a15, pxCurrentTCB
+	addx4	a15, a3, a15
+    l32i    a15, a15, 0                 /* && pxCurrentTCB != 0) {                 */
+
+
+    beqz    a15, 2f
+    l32i    a15, a15, CP_TOPOFSTACK_OFFS
+    ret
+
+1:  movi    a15, 0
+2:  ret
+
+#endif /* XCHAL_CP_NUM > 0 */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/portmux_impl.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/portmux_impl.h
new file mode 100644
index 0000000..4c2f9dc
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/portmux_impl.h
@@ -0,0 +1,113 @@
+/*
+ *  Copyright (C) 2016-2017 Espressif Shanghai PTE LTD
+ *  Copyright (C) 2015 Real Time Engineers Ltd.
+ *
+ *  All rights reserved
+ *
+ *  FreeRTOS is free software; you can redistribute it and/or modify it under
+ *  the terms of the GNU General Public License (version 2) as published by the
+ *  Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+ *
+ ***************************************************************************
+ *  >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+ *  >>!   distribute a combined work that includes FreeRTOS without being   !<<
+ *  >>!   obliged to provide the source code for proprietary components     !<<
+ *  >>!   outside of the FreeRTOS kernel.                                   !<<
+ ***************************************************************************
+ *
+ *  FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ *  WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ *  FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+ *  link: https://www.FreeRTOS.org/a00114.html
+ */
+
+/* This header exists for performance reasons, in order to inline the
+ * implementation of vPortCPUAcquireMutexIntsDisabled and
+ * vPortCPUReleaseMutexIntsDisabled into the
+ * vTaskEnterCritical/vTaskExitCritical functions in task.c as well as the
+ * vPortCPUAcquireMutex/vPortCPUReleaseMutex implementations.
+ *
+ * Normally this kind of performance hack is over the top, but
+ * vTaskEnterCritical/vTaskExitCritical is called a great
+ * deal by FreeRTOS internals.
+ *
+ * It should be #included by freertos port.c or tasks.c, in esp-idf.
+ *
+ * The way it works is that it essentially uses portmux_impl.inc.h as a
+ * generator template of sorts. When no external memory is used, this
+ * template is only used to generate the vPortCPUAcquireMutexIntsDisabledInternal
+ * and vPortCPUReleaseMutexIntsDisabledInternal functions, which use S32C1 to
+ * do an atomic compare & swap. When external memory is used the functions
+ * vPortCPUAcquireMutexIntsDisabledExtram and vPortCPUReleaseMutexIntsDisabledExtram
+ * are also generated, which use uxPortCompareSetExtram to fake the S32C1 instruction.
+ * The wrapper functions vPortCPUAcquireMutexIntsDisabled and
+ * vPortCPUReleaseMutexIntsDisabled will then use the appropriate function to do the
+ * actual lock/unlock.
+ */
+#include "soc/cpu.h"
+#include "portable.h"
+
+/* XOR one core ID with this value to get the other core ID */
+#define CORE_ID_XOR_SWAP    ( CORE_ID_PRO ^ CORE_ID_APP )
+
+
+
+/*Define the mux routines for use with muxes in internal RAM */
+#define PORTMUX_AQUIRE_MUX_FN_NAME     vPortCPUAcquireMutexIntsDisabledInternal
+#define PORTMUX_RELEASE_MUX_FN_NAME    vPortCPUReleaseMutexIntsDisabledInternal
+#define PORTMUX_COMPARE_SET_FN_NAME    uxPortCompareSet
+#include "portmux_impl.inc.h"
+#undef PORTMUX_AQUIRE_MUX_FN_NAME
+#undef PORTMUX_RELEASE_MUX_FN_NAME
+#undef PORTMUX_COMPARE_SET_FN_NAME
+
+
+#if defined( CONFIG_SPIRAM_SUPPORT )
+
+    #define PORTMUX_AQUIRE_MUX_FN_NAME     vPortCPUAcquireMutexIntsDisabledExtram
+    #define PORTMUX_RELEASE_MUX_FN_NAME    vPortCPUReleaseMutexIntsDisabledExtram
+    #define PORTMUX_COMPARE_SET_FN_NAME    uxPortCompareSetExtram
+    #include "portmux_impl.inc.h"
+    #undef PORTMUX_AQUIRE_MUX_FN_NAME
+    #undef PORTMUX_RELEASE_MUX_FN_NAME
+    #undef PORTMUX_COMPARE_SET_FN_NAME
+
+#endif
+
+
+#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+    #define PORTMUX_AQUIRE_MUX_FN_ARGS     portMUX_TYPE * mux, int timeout_cycles, const char * fnName, int line
+    #define PORTMUX_RELEASE_MUX_FN_ARGS    portMUX_TYPE * mux, const char * fnName, int line
+    #define PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( x )     x, timeout_cycles, fnName, line
+    #define PORTMUX_RELEASE_MUX_FN_CALL_ARGS( x )    x, fnName, line
+#else
+    #define PORTMUX_AQUIRE_MUX_FN_ARGS     portMUX_TYPE * mux, int timeout_cycles
+    #define PORTMUX_RELEASE_MUX_FN_ARGS    portMUX_TYPE * mux
+    #define PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( x )     x, timeout_cycles
+    #define PORTMUX_RELEASE_MUX_FN_CALL_ARGS( x )    x
+#endif
+
+
+static inline bool __attribute__( ( always_inline ) ) vPortCPUAcquireMutexIntsDisabled( PORTMUX_AQUIRE_MUX_FN_ARGS )
+{
+    #if defined( CONFIG_SPIRAM_SUPPORT )
+        if( esp_ptr_external_ram( mux ) )
+        {
+            return vPortCPUAcquireMutexIntsDisabledExtram( PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( mux ) );
+        }
+    #endif
+    return vPortCPUAcquireMutexIntsDisabledInternal( PORTMUX_AQUIRE_MUX_FN_CALL_ARGS( mux ) );
+}
+
+
+static inline void vPortCPUReleaseMutexIntsDisabled( PORTMUX_RELEASE_MUX_FN_ARGS )
+{
+    #if defined( CONFIG_SPIRAM_SUPPORT )
+        if( esp_ptr_external_ram( mux ) )
+        {
+            vPortCPUReleaseMutexIntsDisabledExtram( PORTMUX_RELEASE_MUX_FN_CALL_ARGS( mux ) );
+            return;
+        }
+    #endif
+    vPortCPUReleaseMutexIntsDisabledInternal( PORTMUX_RELEASE_MUX_FN_CALL_ARGS( mux ) );
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/portmux_impl.inc.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/portmux_impl.inc.h
new file mode 100644
index 0000000..e98d488
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/portmux_impl.inc.h
@@ -0,0 +1,200 @@
+/*
+ *  Copyright (C) 2016-2017 Espressif Shanghai PTE LTD
+ *  Copyright (C) 2015 Real Time Engineers Ltd.
+ *
+ *  All rights reserved
+ *
+ *  FreeRTOS is free software; you can redistribute it and/or modify it under
+ *  the terms of the GNU General Public License (version 2) as published by the
+ *  Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+ *
+ ***************************************************************************
+ *  >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+ *  >>!   distribute a combined work that includes FreeRTOS without being   !<<
+ *  >>!   obliged to provide the source code for proprietary components     !<<
+ *  >>!   outside of the FreeRTOS kernel.                                   !<<
+ ***************************************************************************
+ *
+ *  FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+ *  WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ *  FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+ *  link: https://www.FreeRTOS.org/a00114.html
+ */
+
+
+/*
+ * Warning: funky preprocessor hackery ahead. Including these headers will generate two
+ * functions, which names are defined by the preprocessor macros
+ * PORTMUX_AQUIRE_MUX_FN_NAME and PORTMUX_RELEASE_MUX_FN_NAME. In order to do the compare
+ * and exchange function, they will use whatever PORTMUX_COMPARE_SET_FN_NAME resolves to.
+ *
+ * In some scenarios, this header is included *twice* in portmux_impl.h: one time
+ * for the 'normal' mux code which uses a compare&exchange routine, another time
+ * to generate code for a second set of these routines that use a second mux
+ * (in internal ram) to fake a compare&exchange on a variable in external memory.
+ */
+
+
+
+static inline bool __attribute__( ( always_inline ) )
+#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+    PORTMUX_AQUIRE_MUX_FN_NAME( portMUX_TYPE * mux,
+                                int timeout_cycles,
+                                const char * fnName,
+                                int line )
+    {
+#else
+    PORTMUX_AQUIRE_MUX_FN_NAME( portMUX_TYPE * mux, int timeout_cycles )
+    {
+        #endif
+
+
+        #if !CONFIG_FREERTOS_UNICORE
+            uint32_t res;
+            portBASE_TYPE coreID, otherCoreID;
+            uint32_t ccount_start;
+            bool set_timeout = timeout_cycles > portMUX_NO_TIMEOUT;
+            #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                if( !set_timeout )
+                {
+                    timeout_cycles = 10000; /* Always set a timeout in debug mode */
+                    set_timeout = true;
+                }
+            #endif
+
+            if( set_timeout ) /* Timeout */
+            {
+                RSR( CCOUNT, ccount_start );
+            }
+
+            #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                uint32_t owner = mux->owner;
+
+                if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) )
+                {
+                    ets_printf( "ERROR: vPortCPUAcquireMutex: mux %p is uninitialized (0x%X)! Called from %s line %d.\n", mux, owner, fnName, line );
+                    mux->owner = portMUX_FREE_VAL;
+                }
+            #endif
+
+            /* Spin until we own the core */
+
+            RSR( PRID, coreID );
+
+            /* Note: coreID is the full 32 bit core ID (CORE_ID_PRO/CORE_ID_APP),
+             * not the 0/1 value returned by xPortGetCoreID()
+             */
+            otherCoreID = CORE_ID_XOR_SWAP ^ coreID;
+
+            do
+            {
+                /* mux->owner should be one of portMUX_FREE_VAL, CORE_ID_PRO,
+                 * CORE_ID_APP:
+                 *
+                 * - If portMUX_FREE_VAL, we want to atomically set to 'coreID'.
+                 * - If "our" coreID, we can drop through immediately.
+                 * - If "otherCoreID", we spin here.
+                 */
+                res = coreID;
+                PORTMUX_COMPARE_SET_FN_NAME( &mux->owner, portMUX_FREE_VAL, &res );
+
+                if( res != otherCoreID )
+                {
+                    break; /* mux->owner is "our" coreID */
+                }
+
+                if( set_timeout )
+                {
+                    uint32_t ccount_now;
+                    RSR( CCOUNT, ccount_now );
+
+                    if( ccount_now - ccount_start > ( unsigned ) timeout_cycles )
+                    {
+                        #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                            ets_printf( "Timeout on mux! last non-recursive lock %s line %d, curr %s line %d\n", mux->lastLockedFn, mux->lastLockedLine, fnName, line );
+                            ets_printf( "Owner 0x%x count %d\n", mux->owner, mux->count );
+                        #endif
+                        return false;
+                    }
+                }
+            } while( 1 );
+
+            assert( res == coreID || res == portMUX_FREE_VAL );           /* any other value implies memory corruption or uninitialized mux */
+            assert( ( res == portMUX_FREE_VAL ) == ( mux->count == 0 ) ); /* we're first to lock iff count is zero */
+            assert( mux->count < 0xFF );                                  /* Bad count value implies memory corruption */
+
+            /* now we own it, we can increment the refcount */
+            mux->count++;
+
+
+            #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                if( res == portMUX_FREE_VAL ) /*initial lock */
+                {
+                    mux->lastLockedFn = fnName;
+                    mux->lastLockedLine = line;
+                }
+                else
+                {
+                    ets_printf( "Recursive lock: count=%d last non-recursive lock %s line %d, curr %s line %d\n", mux->count - 1,
+                                mux->lastLockedFn, mux->lastLockedLine, fnName, line );
+                }
+            #endif /* CONFIG_FREERTOS_PORTMUX_DEBUG */
+        #endif /* CONFIG_FREERTOS_UNICORE */
+        return true;
+    }
+
+#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+        static inline void PORTMUX_RELEASE_MUX_FN_NAME( portMUX_TYPE * mux,
+                                                        const char * fnName,
+                                                        int line )
+        {
+#else
+        static inline void PORTMUX_RELEASE_MUX_FN_NAME( portMUX_TYPE * mux )
+        {
+            #endif
+
+
+            #if !CONFIG_FREERTOS_UNICORE
+                portBASE_TYPE coreID;
+                #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                    const char * lastLockedFn = mux->lastLockedFn;
+                    int lastLockedLine = mux->lastLockedLine;
+                    mux->lastLockedFn = fnName;
+                    mux->lastLockedLine = line;
+                    uint32_t owner = mux->owner;
+
+                    if( ( owner != portMUX_FREE_VAL ) && ( owner != CORE_ID_PRO ) && ( owner != CORE_ID_APP ) )
+                    {
+                        ets_printf( "ERROR: vPortCPUReleaseMutex: mux %p is invalid (0x%x)!\n", mux, mux->owner );
+                    }
+                #endif /* ifdef CONFIG_FREERTOS_PORTMUX_DEBUG */
+
+                #if CONFIG_FREERTOS_PORTMUX_DEBUG || !defined( NDEBUG )
+                    RSR( PRID, coreID );
+                #endif
+
+                #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
+                    if( coreID != mux->owner )
+                    {
+                        ets_printf( "ERROR: vPortCPUReleaseMutex: mux %p was already unlocked!\n", mux );
+                        ets_printf( "Last non-recursive unlock %s line %d, curr unlock %s line %d\n", lastLockedFn, lastLockedLine, fnName, line );
+                    }
+                #endif
+
+                assert( coreID == mux->owner ); /* This is a mutex we didn't lock, or it's corrupt */
+
+                mux->count--;
+
+                if( mux->count == 0 )
+                {
+                    mux->owner = portMUX_FREE_VAL;
+                }
+                else
+                {
+                    assert( mux->count < 0x100 ); /* Indicates memory corruption */
+                    #ifdef CONFIG_FREERTOS_PORTMUX_DEBUG_RECURSIVE
+                        ets_printf( "Recursive unlock: count=%d last locked %s line %d, curr %s line %d\n", mux->count, lastLockedFn, lastLockedLine, fnName, line );
+                    #endif
+                }
+            #endif //!CONFIG_FREERTOS_UNICORE
+        }
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_context.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_context.S
new file mode 100644
index 0000000..fedf428
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_context.S
@@ -0,0 +1,648 @@
+/*******************************************************************************
+Copyright (c) 2006-2015 Cadence Design Systems Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be included
+in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+--------------------------------------------------------------------------------
+
+        XTENSA CONTEXT SAVE AND RESTORE ROUTINES
+
+Low-level Call0 functions for handling generic context save and restore of
+registers not specifically addressed by the interrupt vectors and handlers.
+Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).
+Except for the calls to RTOS functions, this code is generic to Xtensa.
+
+Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-
+save regs (A12-A15), which is always the case if the handlers are coded in C.
+However A12, A13 are made available as scratch registers for interrupt dispatch
+code, so are presumed saved anyway, and are always restored even in Call0 ABI.
+Only A14, A15 are truly handled as callee-save regs.
+
+Because Xtensa is a configurable architecture, this port supports all user
+generated configurations (except restrictions stated in the release notes).
+This is accomplished by conditional compilation using macros and functions
+defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
+Only the processor state included in your configuration is saved and restored,
+including any processor state added by user configuration options or TIE.
+
+*******************************************************************************/
+
+/*  Warn nicely if this file gets named with a lowercase .s instead of .S:  */
+#define NOERROR #
+NOERROR: .error "C preprocessor needed for this file: make sure its filename\
+ ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option."
+
+
+#include "xtensa_rtos.h"
+#include "xtensa_context.h"
+
+#ifdef XT_USE_OVLY
+#include <xtensa/overlay_os_asm.h>
+#endif
+
+    .text
+
+
+
+/*******************************************************************************
+
+_xt_context_save
+
+    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
+
+Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the
+interrupt stack frame defined in xtensa_rtos.h.
+Its counterpart is _xt_context_restore (which also restores A12, A13).
+
+Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.
+This function preserves A12 & A13 in order to provide the caller with 2 scratch 
+regs that need not be saved over the call to this function. The choice of which
+2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw,
+to avoid moving data more than necessary. Caller can assign regs accordingly.
+
+Entry Conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    Original A12, A13 have already been saved in the interrupt stack frame.
+    Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the 
+    point of interruption.
+    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
+
+Exit conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    A12, A13 as at entry (preserved).
+    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
+
+*******************************************************************************/
+
+    .global _xt_context_save
+    .type   _xt_context_save,@function
+    .align  4
+	.literal_position
+    .align  4
+_xt_context_save:
+
+    s32i    a2,  sp, XT_STK_A2
+    s32i    a3,  sp, XT_STK_A3
+    s32i    a4,  sp, XT_STK_A4
+    s32i    a5,  sp, XT_STK_A5
+    s32i    a6,  sp, XT_STK_A6
+    s32i    a7,  sp, XT_STK_A7
+    s32i    a8,  sp, XT_STK_A8
+    s32i    a9,  sp, XT_STK_A9
+    s32i    a10, sp, XT_STK_A10
+    s32i    a11, sp, XT_STK_A11
+
+    /*
+    Call0 ABI callee-saved regs a12-15 do not need to be saved here.
+    a12-13 are the caller's responsibility so it can use them as scratch.
+    So only need to save a14-a15 here for Windowed ABI (not Call0).
+    */
+    #ifndef __XTENSA_CALL0_ABI__
+    s32i    a14, sp, XT_STK_A14
+    s32i    a15, sp, XT_STK_A15
+    #endif
+
+    rsr     a3,  SAR
+    s32i    a3,  sp, XT_STK_SAR
+
+    #if XCHAL_HAVE_LOOPS
+    rsr     a3,  LBEG
+    s32i    a3,  sp, XT_STK_LBEG
+    rsr     a3,  LEND
+    s32i    a3,  sp, XT_STK_LEND
+    rsr     a3,  LCOUNT
+    s32i    a3,  sp, XT_STK_LCOUNT
+    #endif
+
+    #ifdef XT_USE_SWPRI
+    /* Save virtual priority mask */
+    movi    a3,  _xt_vpri_mask
+    l32i    a3,  a3, 0
+    s32i    a3,  sp, XT_STK_VPRI
+    #endif
+
+    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
+    mov     a9,  a0                     /* preserve ret addr */
+    #endif
+
+    #ifndef __XTENSA_CALL0_ABI__
+    /*
+    To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15.
+    Need to save a9,12,13 temporarily (in frame temps) and recover originals.
+    Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow
+    and underflow exceptions disabled (assured by PS.EXCM == 1).
+    */
+    s32i    a12, sp, XT_STK_TMP0        /* temp. save stuff in stack frame */
+    s32i    a13, sp, XT_STK_TMP1    
+    s32i    a9,  sp, XT_STK_TMP2    
+
+    /*
+    Save the overlay state if we are supporting overlays. Since we just saved
+    three registers, we can conveniently use them here. Note that as of now,
+    overlays only work for windowed calling ABI.
+    */
+    #ifdef XT_USE_OVLY
+    l32i    a9,  sp, XT_STK_PC          /* recover saved PC */
+    _xt_overlay_get_state    a9, a12, a13
+    s32i    a9,  sp, XT_STK_OVLY        /* save overlay state */
+    #endif
+
+    l32i    a12, sp, XT_STK_A12         /* recover original a9,12,13 */
+    l32i    a13, sp, XT_STK_A13
+    l32i    a9,  sp, XT_STK_A9
+    addi    sp,  sp, XT_STK_FRMSZ       /* restore the interruptee's SP */
+    call0   xthal_window_spill_nw       /* preserves only a4,5,8,9,12,13 */
+    addi    sp,  sp, -XT_STK_FRMSZ
+    l32i    a12, sp, XT_STK_TMP0        /* recover stuff from stack frame */
+    l32i    a13, sp, XT_STK_TMP1    
+    l32i    a9,  sp, XT_STK_TMP2    
+    #endif
+
+    #if XCHAL_EXTRA_SA_SIZE > 0
+    /*  
+    NOTE: Normally the xthal_save_extra_nw macro only affects address
+    registers a2-a5. It is theoretically possible for Xtensa processor
+    designers to write TIE that causes more address registers to be
+    affected, but it is generally unlikely. If that ever happens,
+    more registers need to be saved/restored around this macro invocation.
+    Here we assume a9,12,13 are preserved.
+    Future Xtensa tools releases might limit the regs that can be affected.
+    */
+    addi    a2,  sp, XT_STK_EXTRA       /* where to save it */
+    # if XCHAL_EXTRA_SA_ALIGN > 16
+    movi    a3, -XCHAL_EXTRA_SA_ALIGN
+    and     a2, a2, a3                  /* align dynamically >16 bytes */
+    # endif
+    call0   xthal_save_extra_nw         /* destroys a0,2,3,4,5 */
+    #endif
+
+    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
+    mov     a0, a9                      /* retrieve ret addr */
+    #endif
+
+    ret
+
+/*******************************************************************************
+
+_xt_context_restore
+
+    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
+
+Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0
+ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt 
+stack frame defined in xtensa_rtos.h .
+Its counterpart is _xt_context_save (whose caller saved A12, A13).
+
+Caller is responsible to restore PC, PS, A0, A1 (SP).
+
+Entry Conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+
+Exit conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    Other processor state except PC, PS, A0, A1 (SP), is as at the point 
+    of interruption.
+
+*******************************************************************************/
+
+    .global _xt_context_restore
+    .type   _xt_context_restore,@function
+    .align  4
+	.literal_position
+    .align  4
+_xt_context_restore:
+
+    #if XCHAL_EXTRA_SA_SIZE > 0
+    /*  
+    NOTE: Normally the xthal_restore_extra_nw macro only affects address
+    registers a2-a5. It is theoretically possible for Xtensa processor
+    designers to write TIE that causes more address registers to be
+    affected, but it is generally unlikely. If that ever happens,
+    more registers need to be saved/restored around this macro invocation.
+    Here we only assume a13 is preserved.
+    Future Xtensa tools releases might limit the regs that can be affected.
+    */
+    mov     a13, a0                     /* preserve ret addr */
+    addi    a2,  sp, XT_STK_EXTRA       /* where to find it */
+    # if XCHAL_EXTRA_SA_ALIGN > 16
+    movi    a3, -XCHAL_EXTRA_SA_ALIGN
+    and     a2, a2, a3                  /* align dynamically >16 bytes */
+    # endif
+    call0   xthal_restore_extra_nw      /* destroys a0,2,3,4,5 */
+    mov     a0,  a13                    /* retrieve ret addr */
+    #endif
+
+    #if XCHAL_HAVE_LOOPS
+    l32i    a2,  sp, XT_STK_LBEG
+    l32i    a3,  sp, XT_STK_LEND
+    wsr     a2,  LBEG
+    l32i    a2,  sp, XT_STK_LCOUNT
+    wsr     a3,  LEND
+    wsr     a2,  LCOUNT
+    #endif
+
+    #ifdef XT_USE_OVLY
+    /*
+    If we are using overlays, this is a good spot to check if we need
+    to restore an overlay for the incoming task. Here we have a bunch
+    of registers to spare. Note that this step is going to use a few
+    bytes of storage below SP (SP-20 to SP-32) if an overlay is going
+    to be restored.
+    */
+    l32i    a2,  sp, XT_STK_PC          /* retrieve PC */
+    l32i    a3,  sp, XT_STK_PS          /* retrieve PS */
+    l32i    a4,  sp, XT_STK_OVLY        /* retrieve overlay state */
+    l32i    a5,  sp, XT_STK_A1          /* retrieve stack ptr */
+    _xt_overlay_check_map    a2, a3, a4, a5, a6
+    s32i    a2,  sp, XT_STK_PC          /* save updated PC */
+    s32i    a3,  sp, XT_STK_PS          /* save updated PS */
+    #endif
+
+    #ifdef XT_USE_SWPRI
+    /* Restore virtual interrupt priority and interrupt enable */
+    movi    a3,  _xt_intdata
+    l32i    a4,  a3, 0                  /* a4 = _xt_intenable */
+    l32i    a5,  sp, XT_STK_VPRI        /* a5 = saved _xt_vpri_mask */
+    and     a4,  a4, a5
+    wsr     a4,  INTENABLE              /* update INTENABLE */
+    s32i    a5,  a3, 4                  /* restore _xt_vpri_mask */
+    #endif
+
+    l32i    a3,  sp, XT_STK_SAR
+    l32i    a2,  sp, XT_STK_A2
+    wsr     a3,  SAR
+    l32i    a3,  sp, XT_STK_A3
+    l32i    a4,  sp, XT_STK_A4
+    l32i    a5,  sp, XT_STK_A5
+    l32i    a6,  sp, XT_STK_A6
+    l32i    a7,  sp, XT_STK_A7
+    l32i    a8,  sp, XT_STK_A8
+    l32i    a9,  sp, XT_STK_A9
+    l32i    a10, sp, XT_STK_A10
+    l32i    a11, sp, XT_STK_A11
+
+    /*
+    Call0 ABI callee-saved regs a12-15 do not need to be restored here.
+    However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(), 
+    so need to be restored anyway, despite being callee-saved in Call0.
+    */
+    l32i    a12, sp, XT_STK_A12
+    l32i    a13, sp, XT_STK_A13
+    #ifndef __XTENSA_CALL0_ABI__
+    l32i    a14, sp, XT_STK_A14
+    l32i    a15, sp, XT_STK_A15
+    #endif
+
+    ret
+
+
+/*******************************************************************************
+
+_xt_coproc_init
+
+Initializes global co-processor management data, setting all co-processors
+to "unowned". Leaves CPENABLE as it found it (does NOT clear it).
+
+Called during initialization of the RTOS, before any threads run.
+
+This may be called from normal Xtensa single-threaded application code which
+might use co-processors. The Xtensa run-time initialization enables all 
+co-processors. They must remain enabled here, else a co-processor exception
+might occur outside of a thread, which the exception handler doesn't expect.
+
+Entry Conditions:
+    Xtensa single-threaded run-time environment is in effect.
+    No thread is yet running.
+
+Exit conditions:
+    None.
+
+Obeys ABI conventions per prototype:
+    void _xt_coproc_init(void)
+
+*******************************************************************************/
+
+#if XCHAL_CP_NUM > 0
+
+    .global _xt_coproc_init
+    .type   _xt_coproc_init,@function
+    .align  4
+	.literal_position
+    .align  4
+_xt_coproc_init:
+    ENTRY0
+
+    /* Initialize thread co-processor ownerships to 0 (unowned). */
+    movi    a2, _xt_coproc_owner_sa         /* a2 = base of owner array */
+    addi    a3, a2, (XCHAL_CP_MAX*portNUM_PROCESSORS) << 2       /* a3 = top+1 of owner array */
+    movi    a4, 0                           /* a4 = 0 (unowned) */
+1:  s32i    a4, a2, 0
+    addi    a2, a2, 4
+    bltu    a2, a3, 1b
+
+    RET0
+
+#endif
+
+
+/*******************************************************************************
+
+_xt_coproc_release
+
+Releases any and all co-processors owned by a given thread. The thread is 
+identified by it's co-processor state save area defined in xtensa_context.h .
+
+Must be called before a thread's co-proc save area is deleted to avoid
+memory corruption when the exception handler tries to save the state.
+May be called when a thread terminates or completes but does not delete
+the co-proc save area, to avoid the exception handler having to save the 
+thread's co-proc state before another thread can use it (optimization).
+
+Needs to be called on the processor the thread was running on. Unpinned threads
+won't have an entry here because they get pinned as soon they use a coprocessor.
+
+Entry Conditions:
+    A2  = Pointer to base of co-processor state save area.
+
+Exit conditions:
+    None.
+
+Obeys ABI conventions per prototype:
+    void _xt_coproc_release(void * coproc_sa_base)
+
+*******************************************************************************/
+
+#if XCHAL_CP_NUM > 0
+
+    .global _xt_coproc_release
+    .type   _xt_coproc_release,@function
+    .align  4
+	.literal_position
+    .align  4
+_xt_coproc_release:
+    ENTRY0                                  /* a2 = base of save area */
+
+	getcoreid a5
+	movi    a3, XCHAL_CP_MAX << 2
+	mull    a5, a5, a3
+    movi    a3, _xt_coproc_owner_sa         /* a3 = base of owner array */
+	add     a3, a3, a5
+
+    addi    a4, a3, XCHAL_CP_MAX << 2       /* a4 = top+1 of owner array */
+    movi    a5, 0                           /* a5 = 0 (unowned) */
+
+    rsil    a6, XCHAL_EXCM_LEVEL            /* lock interrupts */
+
+1:  l32i    a7, a3, 0                       /* a7 = owner at a3 */
+    bne     a2, a7, 2f                      /* if (coproc_sa_base == owner) */
+    s32i    a5, a3, 0                       /*   owner = unowned */
+2:  addi    a3, a3, 1<<2                    /* a3 = next entry in owner array */
+    bltu    a3, a4, 1b                      /* repeat until end of array */
+
+3:  wsr     a6, PS                          /* restore interrupts */
+
+    RET0
+
+#endif
+
+
+/*******************************************************************************
+_xt_coproc_savecs
+
+If there is a current thread and it has a coprocessor state save area, then
+save all callee-saved state into this area. This function is called from the
+solicited context switch handler. It calls a system-specific function to get
+the coprocessor save area base address.
+
+Entry conditions:
+    - The thread being switched out is still the current thread.
+    - CPENABLE state reflects which coprocessors are active.
+    - Registers have been saved/spilled already.
+
+Exit conditions:
+    - All necessary CP callee-saved state has been saved.
+    - Registers a2-a7, a13-a15 have been trashed.
+
+Must be called from assembly code only, using CALL0.
+*******************************************************************************/
+#if XCHAL_CP_NUM > 0
+
+    .extern     _xt_coproc_sa_offset   /* external reference */
+
+    .global     _xt_coproc_savecs
+    .type       _xt_coproc_savecs,@function
+    .align  4
+	.literal_position
+    .align      4
+_xt_coproc_savecs:
+
+    /* At entry, CPENABLE should be showing which CPs are enabled. */
+
+    rsr     a2, CPENABLE                /* a2 = which CPs are enabled      */
+    beqz    a2, .Ldone                  /* quick exit if none              */
+    mov     a14, a0                     /* save return address             */
+    call0   XT_RTOS_CP_STATE            /* get address of CP save area     */
+    mov     a0, a14                     /* restore return address          */
+    beqz    a15, .Ldone                 /* if none then nothing to do      */
+    s16i    a2, a15, XT_CP_CS_ST        /* save mask of CPs being stored   */
+    movi    a13, _xt_coproc_sa_offset   /* array of CP save offsets        */
+    l32i    a15, a15, XT_CP_ASA         /* a15 = base of aligned save area */
+
+#if XCHAL_CP0_SA_SIZE
+    bbci.l  a2, 0, 2f                   /* CP 0 not enabled                */
+    l32i    a14, a13, 0                 /* a14 = _xt_coproc_sa_offset[0]   */
+    add     a3, a14, a15                /* a3 = save area for CP 0         */
+    xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP1_SA_SIZE
+    bbci.l  a2, 1, 2f                   /* CP 1 not enabled                */
+    l32i    a14, a13, 4                 /* a14 = _xt_coproc_sa_offset[1]   */
+    add     a3, a14, a15                /* a3 = save area for CP 1         */
+    xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP2_SA_SIZE
+    bbci.l  a2, 2, 2f
+    l32i    a14, a13, 8
+    add     a3, a14, a15
+    xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP3_SA_SIZE
+    bbci.l  a2, 3, 2f
+    l32i    a14, a13, 12
+    add     a3, a14, a15
+    xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP4_SA_SIZE
+    bbci.l  a2, 4, 2f
+    l32i    a14, a13, 16
+    add     a3, a14, a15
+    xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP5_SA_SIZE
+    bbci.l  a2, 5, 2f
+    l32i    a14, a13, 20
+    add     a3, a14, a15
+    xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP6_SA_SIZE
+    bbci.l  a2, 6, 2f
+    l32i    a14, a13, 24
+    add     a3, a14, a15
+    xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP7_SA_SIZE
+    bbci.l  a2, 7, 2f
+    l32i    a14, a13, 28
+    add     a3, a14, a15
+    xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+.Ldone:
+    ret
+#endif
+
+
+/*******************************************************************************
+_xt_coproc_restorecs
+
+Restore any callee-saved coprocessor state for the incoming thread.
+This function is called from coprocessor exception handling, when giving
+ownership to a thread that solicited a context switch earlier. It calls a
+system-specific function to get the coprocessor save area base address.
+
+Entry conditions:
+    - The incoming thread is set as the current thread.
+    - CPENABLE is set up correctly for all required coprocessors.
+    - a2 = mask of coprocessors to be restored.
+
+Exit conditions:
+    - All necessary CP callee-saved state has been restored.
+    - CPENABLE - unchanged.
+    - Registers a2-a7, a13-a15 have been trashed.
+
+Must be called from assembly code only, using CALL0.
+*******************************************************************************/
+#if XCHAL_CP_NUM > 0
+
+    .global     _xt_coproc_restorecs
+    .type       _xt_coproc_restorecs,@function
+    .align  4
+	.literal_position
+    .align      4
+_xt_coproc_restorecs:
+
+    mov     a14, a0                     /* save return address             */
+    call0   XT_RTOS_CP_STATE            /* get address of CP save area     */
+    mov     a0, a14                     /* restore return address          */
+    beqz    a15, .Ldone2                /* if none then nothing to do      */
+    l16ui   a3, a15, XT_CP_CS_ST        /* a3 = which CPs have been saved  */
+    xor     a3, a3, a2                  /* clear the ones being restored   */
+    s32i    a3, a15, XT_CP_CS_ST        /* update saved CP mask            */
+    movi    a13, _xt_coproc_sa_offset   /* array of CP save offsets        */
+    l32i    a15, a15, XT_CP_ASA         /* a15 = base of aligned save area */
+    
+#if XCHAL_CP0_SA_SIZE
+    bbci.l  a2, 0, 2f                   /* CP 0 not enabled                */
+    l32i    a14, a13, 0                 /* a14 = _xt_coproc_sa_offset[0]   */
+    add     a3, a14, a15                /* a3 = save area for CP 0         */
+    xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:  
+#endif
+
+#if XCHAL_CP1_SA_SIZE
+    bbci.l  a2, 1, 2f                   /* CP 1 not enabled                */
+    l32i    a14, a13, 4                 /* a14 = _xt_coproc_sa_offset[1]   */
+    add     a3, a14, a15                /* a3 = save area for CP 1         */
+    xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP2_SA_SIZE
+    bbci.l  a2, 2, 2f
+    l32i    a14, a13, 8
+    add     a3, a14, a15
+    xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP3_SA_SIZE
+    bbci.l  a2, 3, 2f
+    l32i    a14, a13, 12
+    add     a3, a14, a15
+    xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP4_SA_SIZE
+    bbci.l  a2, 4, 2f
+    l32i    a14, a13, 16
+    add     a3, a14, a15
+    xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP5_SA_SIZE
+    bbci.l  a2, 5, 2f
+    l32i    a14, a13, 20
+    add     a3, a14, a15
+    xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP6_SA_SIZE
+    bbci.l  a2, 6, 2f
+    l32i    a14, a13, 24
+    add     a3, a14, a15
+    xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP7_SA_SIZE
+    bbci.l  a2, 7, 2f
+    l32i    a14, a13, 28
+    add     a3, a14, a15
+    xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+.Ldone2:
+    ret
+
+#endif
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_init.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_init.c
new file mode 100644
index 0000000..6aaea0b
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_init.c
@@ -0,0 +1,54 @@
+/*******************************************************************************
+*  // Copyright (c) 2003-2015 Cadence Design Systems, Inc.
+*  //
+*  // Permission is hereby granted, free of charge, to any person obtaining
+*  // a copy of this software and associated documentation files (the
+*  // "Software"), to deal in the Software without restriction, including
+*  // without limitation the rights to use, copy, modify, merge, publish,
+*  // distribute, sublicense, and/or sell copies of the Software, and to
+*  // permit persons to whom the Software is furnished to do so, subject to
+*  // the following conditions:
+*  //
+*  // The above copyright notice and this permission notice shall be included
+*  // in all copies or substantial portions of the Software.
+*  //
+*  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+*  // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+*  // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+*  // IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+*  // CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+*  // TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+*  // SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+*  --------------------------------------------------------------------------------
+*
+*       XTENSA INITIALIZATION ROUTINES CODED IN C
+*
+*  This file contains miscellaneous Xtensa RTOS-generic initialization functions
+*  that are implemented in C.
+*
+*******************************************************************************/
+
+
+#ifdef XT_BOARD
+    #include    <xtensa/xtbsp.h>
+#endif
+
+#include    "xtensa_rtos.h"
+#include    "esp_clk.h"
+
+#ifdef XT_RTOS_TIMER_INT
+
+    unsigned _xt_tick_divisor = 0; /* cached number of cycles per tick */
+
+    void _xt_tick_divisor_init( void )
+    {
+        _xt_tick_divisor = esp_clk_cpu_freq() / XT_TICK_PER_SEC;
+    }
+
+/* Deprecated, to be removed */
+    int xt_clock_freq( void )
+    {
+        return esp_clk_cpu_freq();
+    }
+
+#endif /* XT_RTOS_TIMER_INT */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_intr.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_intr.c
new file mode 100644
index 0000000..6d05ae5
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_intr.c
@@ -0,0 +1,174 @@
+/*******************************************************************************
+ * Copyright (c) 2006-2015 Cadence Design Systems Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ ******************************************************************************/
+
+/******************************************************************************
+*  Xtensa-specific interrupt and exception functions for RTOS ports.
+*  Also see xtensa_intr_asm.S.
+******************************************************************************/
+
+#include <stdlib.h>
+
+#include <xtensa/config/core.h>
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/xtensa_api.h"
+#include "freertos/portable.h"
+
+#include "rom/ets_sys.h"
+
+#if XCHAL_HAVE_EXCEPTIONS
+
+/* Handler table is in xtensa_intr_asm.S */
+
+    extern xt_exc_handler _xt_exception_table[ XCHAL_EXCCAUSE_NUM * portNUM_PROCESSORS ];
+
+
+/*
+ * Default handler for unhandled exceptions.
+ * CHANGED: We do this in panic.c now
+ */
+
+/*void xt_unhandled_exception(XtExcFrame *frame) */
+/*{ */
+    /*exit(-1); */
+/*} */
+    extern void xt_unhandled_exception( XtExcFrame * frame );
+
+
+/*
+ * This function registers a handler for the specified exception.
+ * The function returns the address of the previous handler.
+ * On error, it returns 0.
+ */
+    xt_exc_handler xt_set_exception_handler( int n,
+                                             xt_exc_handler f )
+    {
+        xt_exc_handler old;
+
+        if( ( n < 0 ) || ( n >= XCHAL_EXCCAUSE_NUM ) )
+        {
+            return 0; /* invalid exception number */
+        }
+
+        /* Convert exception number to _xt_exception_table name */
+        n = n * portNUM_PROCESSORS + xPortGetCoreID();
+        old = _xt_exception_table[ n ];
+
+        if( f )
+        {
+            _xt_exception_table[ n ] = f;
+        }
+        else
+        {
+            _xt_exception_table[ n ] = &xt_unhandled_exception;
+        }
+
+        return( ( old == &xt_unhandled_exception ) ? 0 : old );
+    }
+
+#endif /* if XCHAL_HAVE_EXCEPTIONS */
+
+#if XCHAL_HAVE_INTERRUPTS
+
+/* Handler table is in xtensa_intr_asm.S */
+
+    typedef struct xt_handler_table_entry
+    {
+        void * handler;
+        void * arg;
+    } xt_handler_table_entry;
+
+    extern xt_handler_table_entry _xt_interrupt_table[ XCHAL_NUM_INTERRUPTS * portNUM_PROCESSORS ];
+
+
+/*
+ * Default handler for unhandled interrupts.
+ */
+    void xt_unhandled_interrupt( void * arg )
+    {
+        ets_printf( "Unhandled interrupt %d on cpu %d!\n", ( int ) arg, xPortGetCoreID() );
+    }
+
+
+/*
+ * This function registers a handler for the specified interrupt. The "arg"
+ * parameter specifies the argument to be passed to the handler when it is
+ * invoked. The function returns the address of the previous handler.
+ * On error, it returns 0.
+ */
+    xt_handler xt_set_interrupt_handler( int n,
+                                         xt_handler f,
+                                         void * arg )
+    {
+        xt_handler_table_entry * entry;
+        xt_handler old;
+
+        if( ( n < 0 ) || ( n >= XCHAL_NUM_INTERRUPTS ) )
+        {
+            return 0; /* invalid interrupt number */
+        }
+
+        if( Xthal_intlevel[ n ] > XCHAL_EXCM_LEVEL )
+        {
+            return 0; /* priority level too high to safely handle in C */
+        }
+
+        /* Convert exception number to _xt_exception_table name */
+        n = n * portNUM_PROCESSORS + xPortGetCoreID();
+
+        entry = _xt_interrupt_table + n;
+        old = entry->handler;
+
+        if( f )
+        {
+            entry->handler = f;
+            entry->arg = arg;
+        }
+        else
+        {
+            entry->handler = &xt_unhandled_interrupt;
+            entry->arg = ( void * ) n;
+        }
+
+        return( ( old == &xt_unhandled_interrupt ) ? 0 : old );
+    }
+
+    #if CONFIG_SYSVIEW_ENABLE
+        void * xt_get_interrupt_handler_arg( int n )
+        {
+            xt_handler_table_entry * entry;
+
+            if( ( n < 0 ) || ( n >= XCHAL_NUM_INTERRUPTS ) )
+            {
+                return 0; /* invalid interrupt number */
+            }
+
+            /* Convert exception number to _xt_exception_table name */
+            n = n * portNUM_PROCESSORS + xPortGetCoreID();
+
+            entry = _xt_interrupt_table + n;
+            return entry->arg;
+        }
+    #endif /* if CONFIG_SYSVIEW_ENABLE */
+
+#endif /* XCHAL_HAVE_INTERRUPTS */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_intr_asm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_intr_asm.S
new file mode 100644
index 0000000..ddfe4ba
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_intr_asm.S
@@ -0,0 +1,225 @@
+/*******************************************************************************
+Copyright (c) 2006-2015 Cadence Design Systems Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be included
+in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+******************************************************************************/
+
+/******************************************************************************
+  Xtensa interrupt handling data and assembly routines.
+  Also see xtensa_intr.c and xtensa_vectors.S.
+******************************************************************************/
+
+#include <xtensa/hal.h>
+#include <xtensa/config/core.h>
+
+#include "xtensa_context.h"
+#include "FreeRTOSConfig.h"
+
+#if XCHAL_HAVE_INTERRUPTS
+
+/*
+-------------------------------------------------------------------------------
+  INTENABLE virtualization information.
+-------------------------------------------------------------------------------
+*/
+
+
+#if XT_USE_SWPRI
+/* Warning - this is not multicore-compatible. */
+    .data
+    .global _xt_intdata
+    .align  8
+_xt_intdata:
+    .global _xt_intenable
+    .type   _xt_intenable,@object
+    .size   _xt_intenable,4
+    .global _xt_vpri_mask
+    .type   _xt_vpri_mask,@object
+    .size   _xt_vpri_mask,4
+
+_xt_intenable:     .word   0             /* Virtual INTENABLE     */
+_xt_vpri_mask:     .word   0xFFFFFFFF    /* Virtual priority mask */
+#endif
+
+/*
+-------------------------------------------------------------------------------
+  Table of C-callable interrupt handlers for each interrupt. Note that not all
+  slots can be filled, because interrupts at level > EXCM_LEVEL will not be
+  dispatched to a C handler by default.
+
+  Stored as:
+  int 0 cpu 0
+  int 0 cpu 1
+  ...
+  int 0 cpu n
+  int 1 cpu 0
+  int 1 cpu 1
+  etc
+-------------------------------------------------------------------------------
+*/
+
+    .data
+    .global _xt_interrupt_table
+    .align  8
+
+_xt_interrupt_table:
+
+    .set    i, 0
+    .rept   XCHAL_NUM_INTERRUPTS*portNUM_PROCESSORS
+    .word   xt_unhandled_interrupt      /* handler address               */
+    .word   i                           /* handler arg (default: intnum) */
+    .set    i, i+1
+    .endr
+
+#endif /* XCHAL_HAVE_INTERRUPTS */
+
+
+#if XCHAL_HAVE_EXCEPTIONS
+
+/*
+-------------------------------------------------------------------------------
+  Table of C-callable exception handlers for each exception. Note that not all
+  slots will be active, because some exceptions (e.g. coprocessor exceptions)
+  are always handled by the OS and cannot be hooked by user handlers.
+
+  Stored as:
+  exc 0 cpu 0
+  exc 0 cpu 1
+  ...
+  exc 0 cpu n
+  exc 1 cpu 0
+  exc 1 cpu 1
+  etc
+-------------------------------------------------------------------------------
+*/
+
+    .data
+    .global _xt_exception_table
+    .align  4
+
+_xt_exception_table:
+    .rept   XCHAL_EXCCAUSE_NUM * portNUM_PROCESSORS
+    .word   xt_unhandled_exception    /* handler address */
+    .endr
+
+#endif
+
+
+/*
+-------------------------------------------------------------------------------
+  unsigned int xt_ints_on ( unsigned int mask )
+
+  Enables a set of interrupts. Does not simply set INTENABLE directly, but
+  computes it as a function of the current virtual priority if XT_USE_SWPRI is
+  enabled.
+  Can be called from interrupt handlers.
+-------------------------------------------------------------------------------
+*/
+
+    .text
+    .align  4
+    .global xt_ints_on
+    .type   xt_ints_on,@function
+
+xt_ints_on:
+
+    ENTRY0
+
+#if XCHAL_HAVE_INTERRUPTS
+#if XT_USE_SWPRI
+    movi    a3, 0
+    movi    a4, _xt_intdata
+    xsr     a3, INTENABLE        /* Disables all interrupts   */
+    rsync
+    l32i    a3, a4, 0            /* a3 = _xt_intenable        */
+    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask        */
+    or      a5, a3, a2           /* a5 = _xt_intenable | mask */
+    s32i    a5, a4, 0            /* _xt_intenable |= mask     */
+    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
+    wsr     a5, INTENABLE        /* Reenable interrupts       */
+    mov     a2, a3               /* Previous mask             */
+#else
+    movi    a3, 0
+    xsr     a3, INTENABLE        /* Disables all interrupts   */
+    rsync
+    or      a2, a3, a2           /* set bits in mask */
+    wsr     a2, INTENABLE        /* Re-enable ints */
+    rsync
+    mov     a2, a3               /* return prev mask */
+#endif
+#else
+    movi    a2, 0                /* Return zero */
+#endif
+    RET0
+
+    .size   xt_ints_on, . - xt_ints_on
+
+
+/*
+-------------------------------------------------------------------------------
+  unsigned int xt_ints_off ( unsigned int mask )
+
+  Disables a set of interrupts. Does not simply set INTENABLE directly,
+  but computes it as a function of the current virtual priority if XT_USE_SWPRI is
+  enabled.
+  Can be called from interrupt handlers.
+-------------------------------------------------------------------------------
+*/
+
+    .text
+    .align  4
+    .global xt_ints_off
+    .type   xt_ints_off,@function
+
+xt_ints_off:
+
+    ENTRY0
+#if XCHAL_HAVE_INTERRUPTS
+#if XT_USE_SWPRI
+    movi    a3, 0
+    movi    a4, _xt_intdata
+    xsr     a3, INTENABLE        /* Disables all interrupts    */
+    rsync
+    l32i    a3, a4, 0            /* a3 = _xt_intenable         */
+    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask         */
+    or      a5, a3, a2           /* a5 = _xt_intenable | mask  */
+    xor     a5, a5, a2           /* a5 = _xt_intenable & ~mask */
+    s32i    a5, a4, 0            /* _xt_intenable &= ~mask     */
+    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
+    wsr     a5, INTENABLE        /* Reenable interrupts        */
+    mov     a2, a3               /* Previous mask              */
+#else
+    movi    a4, 0
+    xsr     a4, INTENABLE        /* Disables all interrupts   */
+    rsync
+    or      a3, a4, a2           /* set bits in mask */
+    xor     a3, a3, a2           /* invert bits in mask set in mask, essentially clearing them */
+    wsr     a3, INTENABLE        /* Re-enable ints */
+    rsync
+    mov     a2, a4               /* return prev mask */
+#endif
+#else
+    movi    a2, 0                /* return zero */
+#endif
+    RET0
+
+    .size   xt_ints_off, . - xt_ints_off
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_loadstore_handler.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_loadstore_handler.S
new file mode 100644
index 0000000..32d7a8a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_loadstore_handler.S
@@ -0,0 +1,559 @@
+/*
+ Copyright 2019 Espressif Systems (Shanghai) PTE LTD
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+     http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/*
+ *  LoadStoreErrorCause:     Occurs when trying to access 32 bit addressable memory region as 8 bit or 16 bit
+ *  LoadStoreAlignmentCause: Occurs when trying to access in an unaligned manner
+ *
+ *          xxxx xxxx = imm8 field
+ *               yyyy = imm4 field
+ *               ssss = s field
+ *               tttt = t field
+ *
+ *                            16                0
+ *                            -------------------
+ *          L32I.N            yyyy ssss tttt 1000
+ *          S32I.N            yyyy ssss tttt 1001
+ *
+ *                  23                          0
+ *                  -----------------------------
+ *          L8UI    xxxx xxxx 0000 ssss tttt 0010               <- LoadStoreError
+ *          L16UI   xxxx xxxx 0001 ssss tttt 0010               <- LoadStoreError, LoadStoreAlignment
+ *          L16SI   xxxx xxxx 1001 ssss tttt 0010               <- LoadStoreError, LoadStoreAlignment
+ *          L32I    xxxx xxxx 0010 ssss tttt 0010               <- LoadStoreAlignment
+ *
+ *          S8I     xxxx xxxx 0100 ssss tttt 0010               <- LoadStoreError
+ *          S16I    xxxx xxxx 0101 ssss tttt 0010               <- LoadStoreError, LoadStoreAlignment
+ *          S32I    xxxx xxxx 0110 ssss tttt 0010               <- LoadStoreAlignment
+ *
+ *                   ******* UNSUPPORTED *******
+ *
+ *          L32E    0000 1001 rrrr ssss tttt 0000
+ *          S32E    0100 1001 rrrr ssss tttt 0000
+ *                  -----------------------------
+ */
+
+#include "xtensa_rtos.h"
+#include "sdkconfig.h"
+#include "soc/soc.h"
+
+#define LOADSTORE_HANDLER_STACK_SZ      8
+    .section .bss, "aw"
+    .balign 16
+LoadStoreHandlerStack:
+    .rept LOADSTORE_HANDLER_STACK_SZ
+    .word 0
+    .endr
+
+
+/* LoadStoreErrorCause handler:
+ *
+ * Completes 8-bit or 16-bit load/store instructions from 32-bit aligned memory region
+ * Called from UserExceptionVector if EXCCAUSE is LoadStoreErrorCause
+ */
+
+    .global   LoadStoreErrorHandler
+    .section .iram1, "ax"
+
+    .literal_position
+
+    .balign 4
+LoadStoreErrorHandler:
+    .type   LoadStoreErrorHandler, @function
+
+    wsr     a0, depc                            // Save return address in depc
+    mov     a0, sp
+    movi    sp, LoadStoreHandlerStack
+    s32i    a0, sp, 0x04                        // Since a0 contains value of a1
+    s32i    a2, sp, 0x08
+    s32i    a3, sp, 0x0c
+    s32i    a4, sp, 0x10
+
+    rsr     a0, sar                             // Save SAR in a0 to restore later
+
+    /* Check whether the address lies in the valid range */
+    rsr     a3, excvaddr
+    movi    a4, _iram_text_end                  // End of code section of IRAM
+    bge     a3, a4, 1f
+    movi    a4, SOC_CACHE_APP_LOW               // Check if in APP cache region
+    blt     a3, a4, .LS_wrong_opcode
+    movi    a4, SOC_CACHE_APP_HIGH
+    bge     a3, a4, .LS_wrong_opcode
+    j       2f
+
+1:
+    movi    a4, SOC_IRAM_HIGH                   // End of IRAM address range
+    bge     a3, a4, .LS_wrong_opcode
+
+2:
+    /* Examine the opcode which generated the exception */
+    /* Note: Instructions are in this order to avoid pipeline stalls. */
+    rsr     a2, epc1
+    movi    a4, ~3
+    ssa8l   a2                                  // sar is now correct shift for aligned read
+    and     a2, a2, a4                          // a2 now 4-byte aligned address of instruction
+    l32i    a4, a2, 0
+    l32i    a2, a2, 4
+
+    src     a2, a2, a4                          // a2 now instruction that failed
+    bbci    a2, 1, .LS_wrong_opcode
+    bbsi    a2, 14, .LSE_store_op               // Store instruction
+
+    /* l8/l16ui/l16si */
+    movi    a4, ~3
+    and     a4, a3, a4                          // a4 now word aligned read address
+
+    ssa8l   a3                                  // sar is now shift to extract a3's byte
+    l32i    a4, a4, 0                           // perform the actual read
+    srl     a4, a4                              // shift right correct distance
+    extui   a3, a2, 12, 4
+    bnez    a3, 1f                              // l16ui/l16si
+    extui   a4, a4, 0, 8                        // mask off bits needed for an l8
+    j       2f
+
+1:
+    extui   a4, a4, 0, 16
+    bbci    a2, 15, 2f                          // l16ui
+
+    /* Sign adjustment */
+    slli    a4, a4, 16
+    srai    a4, a4, 16                          // a4 contains the value
+
+2:
+    /* a4 contains the value */
+    rsr     a3, epc1
+    addi    a3, a3, 3
+    wsr     a3, epc1
+    wsr     a0, sar
+    rsr     a0, excsave1
+
+    extui   a2, a2, 3, 5
+    blti    a2, 10, .LSE_stack_reg
+
+    movi    a3, .LS_jumptable_base
+    addx8   a2, a2, a3                          // a2 is now the address to jump to
+    l32i    a3, sp, 0x0c
+    jx      a2
+
+.LSE_stack_reg:
+    addx2   a2, a2, sp
+    s32i    a4, a2, 0
+
+    /* Restore all values */
+    l32i    a4, sp, 0x10
+    l32i    a3, sp, 0x0c
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+.LSE_store_op:
+    s32i    a5, a1, 0x14
+    s32i    a6, a1, 0x18
+
+    /* a2 -> instruction that caused the error */
+    /* a3 -> unaligned address */
+    extui   a4, a2, 4, 4
+    blti    a4, 7, 1f
+    movi    a5, .LSE_store_reg
+    addx8   a5, a4, a5
+    jx      a5
+
+1:
+    addx4   a4, a4, sp
+    l32i    a4, a4, 0
+
+.LSE_store_data:
+    /* a4 contains the value */
+    rsr     a6, epc1
+    addi    a6, a6, 3
+    wsr     a6, epc1
+
+    ssa8b   a3
+    movi    a5, -1
+    bbsi    a2, 12, 1f                          // s16
+    extui   a4, a4, 0, 8
+    movi    a6, 0xff
+    j       2f
+1:
+    extui   a4, a4, 0, 16
+    movi    a6, 0xffff
+2:
+    sll     a4, a4                              // shift the value to proper offset
+    sll     a6, a6
+    xor     a5, a5, a6                          // a5 contains the mask
+
+    movi    a6, ~3
+    and     a3, a3, a6                          // a3 has the aligned address
+    l32i    a6, a3, 0                           // a6 contains the data at the aligned address
+    and     a6, a6, a5
+    or      a4, a6, a4
+    s32i    a4, a3, 0
+
+    /* Restore registers */
+    wsr     a0, sar
+
+    l32i    a6, sp, 0x18
+    l32i    a5, sp, 0x14
+    l32i    a4, sp, 0x10
+    l32i    a3, sp, 0x0c
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rsr     a0, excsave1
+
+    rfe
+
+.LSE_store_reg:
+    .org .LSE_store_reg + (7 * 8)
+    mov     a4, a7
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (8 * 8)
+    mov     a4, a8
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (9 * 8)
+    mov     a4, a9
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (10 * 8)
+    mov     a4, a10
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (11 * 8)
+    mov     a4, a11
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (12 * 8)
+    mov     a4, a12
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (13 * 8)
+    mov     a4, a13
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (14 * 8)
+    mov     a4, a14
+    j .LSE_store_data
+
+    .org .LSE_store_reg + (15 * 8)
+    mov     a4, a15
+    j .LSE_store_data
+
+
+/* LoadStoreAlignmentCause handler:
+ *
+ * Completes unaligned 16-bit and 32-bit load/store instructions from 32-bit aligned memory region
+ * Called from UserExceptionVector if EXCCAUSE is LoadStoreAlignmentCause
+ */
+
+    .global   AlignmentErrorHandler
+    .section .iram1, "ax"
+
+    .literal_position
+
+    .balign 4
+AlignmentErrorHandler:
+    .type   AlignmentErrorHandler, @function
+
+    wsr     a0, depc                            // Save return address in depc
+    mov     a0, sp
+    movi    sp, LoadStoreHandlerStack
+    s32i    a0, sp, 0x04                        // Since a0 contains value of a1
+    s32i    a2, sp, 0x08
+    s32i    a3, sp, 0x0c
+    s32i    a4, sp, 0x10
+
+    rsr     a0, sar                             // Save SAR in a0 to restore later
+
+    /* Check whether the address lies in the valid range */
+    rsr     a3, excvaddr
+    movi    a4, _iram_text_end                  // End of code section of IRAM
+    bge     a3, a4, 1f
+    movi    a4, SOC_CACHE_APP_LOW               // Check if in APP cache region
+    blt     a3, a4, .LS_wrong_opcode
+    movi    a4, SOC_CACHE_APP_HIGH
+    bge     a3, a4, .LS_wrong_opcode
+    j       2f
+
+1:
+    movi    a4, SOC_IRAM_HIGH                   // End of IRAM address range
+    bge     a3, a4, .LS_wrong_opcode
+
+2:
+    /* Examine the opcode which generated the exception */
+    /* Note: Instructions are in this order to avoid pipeline stalls. */
+    rsr     a2, epc1
+    movi    a4, ~3
+    ssa8l   a2                                  // sar is now correct shift for aligned read
+    and     a2, a2, a4                          // a2 now 4-byte aligned address of instruction
+    l32i    a4, a2, 0
+    l32i    a2, a2, 4
+
+    /* a2 has the instruction that caused the error */
+    src     a2, a2, a4
+    extui   a4, a2, 0, 4
+    addi    a4, a4, -9
+    beqz    a4, .LSA_store_op
+    bbsi    a2, 14, .LSA_store_op
+
+    ssa8l   a3                                  // a3 contains the unaligned address
+    movi    a4, ~3
+    and     a4, a3, a4                          // a4 has the aligned address
+    l32i    a3, a4, 0
+    l32i    a4, a4, 4
+    src     a4, a4, a3
+
+    rsr     a3, epc1
+    addi    a3, a3, 2
+    bbsi    a2, 3, 1f                           // l32i.n
+    bbci    a2, 1, .LS_wrong_opcode
+    addi    a3, a3, 1
+
+    bbsi    a2, 13, 1f                          // l32
+    extui   a4, a4, 0, 16
+    bbci    a2, 15, 1f                          // l16ui
+
+    /* Sign adjustment */
+    slli    a4, a4, 16
+    srai    a4, a4, 16                          // a4 contains the value
+
+1:
+    wsr     a3, epc1
+    wsr     a0, sar
+    rsr     a0, excsave1
+
+    extui   a2, a2, 4, 4
+    blti    a2, 5, .LSA_stack_reg               // a3 contains the target register
+
+    movi    a3, .LS_jumptable_base
+    slli    a2, a2, 4
+    add     a2, a2, a3                          // a2 is now the address to jump to
+    l32i    a3, sp, 0x0c
+    jx      a2
+
+.LSA_stack_reg:
+    addx4   a2, a2, sp
+    s32i    a4, a2, 0
+
+    /* Restore all values */
+    l32i    a4, sp, 0x10
+    l32i    a3, sp, 0x0c
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+/* Store instruction */
+.LSA_store_op:
+    s32i    a5, sp, 0x14
+    s32i    a6, sp, 0x18
+    s32i    a7, sp, 0x1c
+
+    /* a2 -> instruction that caused the error */
+    /* a3 -> unaligned address */
+    extui   a4, a2, 4, 4
+    blti    a4, 8, 1f
+    movi    a5, .LSA_store_reg
+    addx8   a5, a4, a5
+    jx      a5
+
+1:
+    addx4   a4, a4, sp
+    l32i    a4, a4, 0                           // a4 contains the value
+
+.LSA_store_data:
+    movi    a6, 0
+
+    rsr     a7, epc1
+    addi    a7, a7 ,2
+    bbsi    a2, 3, 1f                           // s32i.n
+    bbci    a2, 1, .LS_wrong_opcode
+
+    addi    a7, a7, 1
+    bbsi    a2, 13, 1f                          // s32i
+
+    movi    a5, -1
+    extui   a4, a4, 0, 16
+    slli    a6, a5, 16                          // 0xffff0000
+
+1:
+    wsr     a7, epc1
+    movi    a5, ~3
+    and     a5, a3, a5                          // a5 has the aligned address
+
+    ssa8b   a3
+    movi    a3, -1
+    src     a7, a6, a3
+    src     a3, a3, a6
+
+    /* Store data on lower address */
+    l32i    a6, a5, 0
+    and     a6, a6, a7
+    sll     a7, a4
+    or      a6, a6, a7
+    s32i    a6, a5, 0
+
+    /* Store data on higher address */
+    l32i    a7, a5, 4
+    srl     a6, a4
+    and     a3, a7, a3
+    or      a3, a3, a6
+    s32i    a3, a5, 4
+
+    /* Restore registers */
+    wsr     a0, sar
+    rsr     a0, excsave1
+
+    l32i    a7, sp, 0x1c
+    l32i    a6, sp, 0x18
+    l32i    a5, sp, 0x14
+    l32i    a4, sp, 0x10
+    l32i    a3, sp, 0x0c
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+.LSA_store_reg:
+    .org .LSA_store_reg + (8 * 8)
+    mov     a4, a8
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (9 * 8)
+    mov     a4, a9
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (10 * 8)
+    mov     a4, a10
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (11 * 8)
+    mov     a4, a11
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (12 * 8)
+    mov     a4, a12
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (13 * 8)
+    mov     a4, a13
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (14 * 8)
+    mov     a4, a14
+    j       .LSA_store_data
+
+    .org .LSA_store_reg + (15 * 8)
+    mov     a4, a15
+    j       .LSA_store_data
+
+/*
+ * Common routines for both the exception handlers
+ */
+    .balign 4
+.LS_jumptable:
+    /*  The first 5 entries (80 bytes) of this table are unused (registers
+        a0..a4 are handled separately above).  Rather than have a whole bunch
+        of wasted space, just pretend that the table starts 80 bytes
+        earlier in memory. */
+    .set    .LS_jumptable_base, .LS_jumptable - (16 * 5)
+
+    .org    .LS_jumptable_base + (16 * 5)
+    mov     a5, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 6)
+    mov     a6, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 7)
+    mov     a7, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 8)
+    mov     a8, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 9)
+    mov     a9, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 10)
+    mov     a10, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 11)
+    mov     a11, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 12)
+    mov     a12, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 13)
+    mov     a13, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 14)
+    mov     a14, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+    .org    .LS_jumptable_base + (16 * 15)
+    mov     a15, a4
+    l32i    a4, sp, 0x10
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rfe
+
+.LS_wrong_opcode:
+    /* Reaches here if the address is in invalid range or the opcode isn't supported.
+     * Restore registers and jump back to _xt_user_exc
+     */
+    wsr     a0, sar
+    l32i    a4, sp, 0x10
+    l32i    a3, sp, 0x0c
+    l32i    a2, sp, 0x08
+    l32i    a1, sp, 0x04
+    rsr     a0, depc
+    ret                                         // Equivalent to jx a0
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_overlay_os_hook.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_overlay_os_hook.c
new file mode 100644
index 0000000..ef893a7
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_overlay_os_hook.c
@@ -0,0 +1,67 @@
+/* xtensa_overlay_os_hook.c -- Overlay manager OS hooks for FreeRTOS. */
+
+/* Copyright (c) 2015-2015 Cadence Design Systems Inc. */
+/* */
+/* Permission is hereby granted, free of charge, to any person obtaining */
+/* a copy of this software and associated documentation files (the */
+/* "Software"), to deal in the Software without restriction, including */
+/* without limitation the rights to use, copy, modify, merge, publish, */
+/* distribute, sublicense, and/or sell copies of the Software, and to */
+/* permit persons to whom the Software is furnished to do so, subject to */
+/* the following conditions: */
+/* */
+/* The above copyright notice and this permission notice shall be included */
+/* in all copies or substantial portions of the Software. */
+/* */
+/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, */
+/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
+/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY */
+/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, */
+/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE */
+/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
+
+
+#include "FreeRTOS.h"
+#include "semphr.h"
+
+#if configUSE_MUTEX
+
+/* Mutex object that controls access to the overlay. Currently only one
+ * overlay region is supported so one mutex suffices.
+ */
+    static SemaphoreHandle_t xt_overlay_mutex;
+
+
+/* This function should be overridden to provide OS specific init such
+ * as the creation of a mutex lock that can be used for overlay locking.
+ * Typically this mutex would be set up with priority inheritance. See
+ * overlay manager documentation for more details.
+ */
+    void xt_overlay_init_os( void )
+    {
+        /* Create the mutex for overlay access. Priority inheritance is
+         * required.
+         */
+        xt_overlay_mutex = xSemaphoreCreateMutex();
+    }
+
+
+/* This function locks access to shared overlay resources, typically
+ * by acquiring a mutex.
+ */
+    void xt_overlay_lock( void )
+    {
+        xSemaphoreTake( xt_overlay_mutex, 0 );
+    }
+
+
+/* This function releases access to shared overlay resources, typically
+ * by unlocking a mutex.
+ */
+    void xt_overlay_unlock( void )
+    {
+        xSemaphoreGive( xt_overlay_mutex );
+    }
+
+#endif /* if configUSE_MUTEX */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_vector_defaults.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_vector_defaults.S
new file mode 100644
index 0000000..f6c34a3
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_vector_defaults.S
@@ -0,0 +1,164 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "xtensa_rtos.h"
+#include "esp_panic.h"
+#include "sdkconfig.h"
+#include "soc/soc.h"
+
+/*
+This file contains the default handlers for the high interrupt levels as well as some specialized exceptions. 
+The default behaviour is to just exit the interrupt or call the panic handler on the exceptions
+*/
+
+
+#if XCHAL_HAVE_DEBUG
+    .global    xt_debugexception
+    .weak xt_debugexception
+    .set xt_debugexception, _xt_debugexception
+    .section .iram1,"ax"
+    .type       _xt_debugexception,@function
+    .align      4
+
+_xt_debugexception:
+    movi    a0,PANIC_RSN_DEBUGEXCEPTION
+    wsr     a0,EXCCAUSE
+    /* _xt_panic assumes a level 1 exception. As we're
+       crashing anyhow, copy EPC & EXCSAVE from DEBUGLEVEL
+       to level 1. */
+    rsr     a0,(EPC + XCHAL_DEBUGLEVEL)
+    wsr     a0,EPC_1
+    rsr     a0,(EXCSAVE + XCHAL_DEBUGLEVEL)
+    wsr     a0,EXCSAVE_1
+    call0   _xt_panic                       /* does not return */
+    rfi     XCHAL_DEBUGLEVEL
+
+#endif /* Debug exception */
+
+
+#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
+    .global    xt_highint2
+    .weak xt_highint2
+    .set xt_highint2, _xt_highint2
+    .section .iram1,"ax"
+    .type       _xt_highint2,@function
+    .align      4
+_xt_highint2:
+
+    /* Default handler does nothing; just returns */
+    .align  4
+.L_xt_highint2_exit:
+    rsr     a0, EXCSAVE_2                   /* restore a0 */
+    rfi     2
+
+#endif  /* Level 2 */
+
+#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
+
+    .global    xt_highint3
+    .weak xt_highint3
+    .set xt_highint3, _xt_highint3
+    .section .iram1,"ax"
+    .type       _xt_highint3,@function
+    .align      4
+_xt_highint3:
+
+    /* Default handler does nothing; just returns */
+
+    .align  4
+.L_xt_highint3_exit:
+    rsr     a0, EXCSAVE_3                   /* restore a0 */
+    rfi     3
+
+#endif  /* Level 3 */
+
+#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
+
+    .global    xt_highint4
+    .weak xt_highint4
+    .set xt_highint4, _xt_highint4
+    .section .iram1,"ax"
+    .type       _xt_highint4,@function
+    .align      4
+_xt_highint4:
+
+    /* Default handler does nothing; just returns */
+
+    .align  4
+.L_xt_highint4_exit:
+    rsr     a0, EXCSAVE_4                   /* restore a0 */
+    rfi     4
+
+#endif  /* Level 4 */
+
+#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
+
+    .global    xt_highint5
+    .weak xt_highint5
+    .set xt_highint5, _xt_highint5
+    .section .iram1,"ax"
+    .type       _xt_highint5,@function
+    .align      4
+_xt_highint5:
+
+    /* Default handler does nothing; just returns */
+
+    .align  4
+.L_xt_highint5_exit:
+    rsr     a0, EXCSAVE_5                   /* restore a0 */
+    rfi     5
+
+
+#endif  /* Level 5 */
+
+#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
+
+    .global    _xt_highint6
+    .global    xt_highint6
+    .weak xt_highint6
+    .set xt_highint6, _xt_highint6
+    .section .iram1,"ax"
+    .type       _xt_highint6,@function
+    .align      4
+_xt_highint6:
+
+    /* Default handler does nothing; just returns */
+
+    .align  4
+.L_xt_highint6_exit:
+    rsr     a0, EXCSAVE_6                   /* restore a0 */
+    rfi     6
+
+#endif  /* Level 6 */
+
+#if XCHAL_HAVE_NMI
+
+    .global    _xt_nmi
+    .global    xt_nmi
+    .weak xt_nmi
+    .set xt_nmi, _xt_nmi
+    .section .iram1,"ax"
+    .type       _xt_nmi,@function
+    .align      4
+_xt_nmi:
+
+    /* Default handler does nothing; just returns */
+
+    .align  4
+.L_xt_nmi_exit:
+    rsr     a0, EXCSAVE + XCHAL_NMILEVEL    /* restore a0 */
+    rfi     XCHAL_NMILEVEL
+
+#endif  /* NMI */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_vectors.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_vectors.S
new file mode 100644
index 0000000..5c8601d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32_IDF3/xtensa_vectors.S
@@ -0,0 +1,1919 @@
+/*******************************************************************************
+Copyright (c) 2006-2015 Cadence Design Systems Inc.
+
+Permission is hereby granted, free of charge, to any person obtaining
+a copy of this software and associated documentation files (the
+"Software"), to deal in the Software without restriction, including
+without limitation the rights to use, copy, modify, merge, publish,
+distribute, sublicense, and/or sell copies of the Software, and to
+permit persons to whom the Software is furnished to do so, subject to
+the following conditions:
+
+The above copyright notice and this permission notice shall be included
+in all copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+--------------------------------------------------------------------------------
+
+        XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS
+
+  Xtensa low level exception and interrupt vectors and handlers for an RTOS.
+
+  Interrupt handlers and user exception handlers support interaction with
+  the RTOS by calling XT_RTOS_INT_ENTER and XT_RTOS_INT_EXIT before and
+  after user's specific interrupt handlers. These macros are defined in
+  xtensa_<rtos>.h to call suitable functions in a specific RTOS.
+
+  Users can install application-specific interrupt handlers for low and
+  medium level interrupts, by calling xt_set_interrupt_handler(). These
+  handlers can be written in C, and must obey C calling convention. The
+  handler table is indexed by the interrupt number. Each handler may be
+  provided with an argument. 
+
+  Note that the system timer interrupt is handled specially, and is
+  dispatched to the RTOS-specific handler. This timer cannot be hooked
+  by application code.
+
+  Optional hooks are also provided to install a handler per level at 
+  run-time, made available by compiling this source file with 
+  '-DXT_INTEXC_HOOKS' (useful for automated testing).
+
+!!  This file is a template that usually needs to be modified to handle       !!
+!!  application specific interrupts. Search USER_EDIT for helpful comments    !!
+!!  on where to insert handlers and how to write them.                        !!
+
+  Users can also install application-specific exception handlers in the
+  same way, by calling xt_set_exception_handler(). One handler slot is
+  provided for each exception type. Note that some exceptions are handled
+  by the porting layer itself, and cannot be taken over by application
+  code in this manner. These are the alloca, syscall, and coprocessor
+  exceptions.
+
+  The exception handlers can be written in C, and must follow C calling
+  convention. Each handler is passed a pointer to an exception frame as
+  its single argument. The exception frame is created on the stack, and
+  holds the saved context of the thread that took the exception. If the
+  handler returns, the context will be restored and the instruction that
+  caused the exception will be retried. If the handler makes any changes
+  to the saved state in the exception frame, the changes will be applied
+  when restoring the context.
+
+  Because Xtensa is a configurable architecture, this port supports all user
+  generated configurations (except restrictions stated in the release notes).
+  This is accomplished by conditional compilation using macros and functions
+  defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
+  Only the relevant parts of this file will be included in your RTOS build.
+  For example, this file provides interrupt vector templates for all types and
+  all priority levels, but only the ones in your configuration are built.
+
+  NOTES on the use of 'call0' for long jumps instead of 'j':
+   1. This file should be assembled with the -mlongcalls option to xt-xcc.
+   2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to
+      a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the
+      distance from the call to the destination. The linker then relaxes
+      it back to 'call0 dest' if it determines that dest is within range.
+      This allows more flexibility in locating code without the performance
+      overhead of the 'l32r' literal data load in cases where the destination
+      is in range of 'call0'. There is an additional benefit in that 'call0'
+      has a longer range than 'j' due to the target being word-aligned, so 
+      the 'l32r' sequence is less likely needed.
+   3. The use of 'call0' with -mlongcalls requires that register a0 not be 
+      live at the time of the call, which is always the case for a function 
+      call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'.
+   4. This use of 'call0' is independent of the C function call ABI.
+
+*******************************************************************************/
+
+#include "xtensa_rtos.h"
+#include "esp_panic.h"
+#include "sdkconfig.h"
+#include "soc/soc.h"
+#include "soc/dport_reg.h"
+
+/*
+  Define for workaround: pin no-cpu-affinity tasks to a cpu when fpu is used.
+  Please change this when the tcb structure is changed
+*/
+#define TASKTCB_XCOREID_OFFSET (0x38+configMAX_TASK_NAME_LEN+3)&~3
+.extern pxCurrentTCB
+
+/* Enable stack backtrace across exception/interrupt - see below */
+#ifdef CONFIG_FREERTOS_INTERRUPT_BACKTRACE
+#define XT_DEBUG_BACKTRACE    1
+#endif
+
+
+/*
+--------------------------------------------------------------------------------
+  Defines used to access _xtos_interrupt_table.
+--------------------------------------------------------------------------------
+*/
+#define XIE_HANDLER     0
+#define XIE_ARG         4
+#define XIE_SIZE        8
+
+
+/*
+  Macro get_percpu_entry_for - convert a per-core ID into a multicore entry.
+  Basically does reg=reg*portNUM_PROCESSORS+current_core_id
+  Multiple versions here to optimize for specific portNUM_PROCESSORS values.
+*/
+    .macro get_percpu_entry_for reg scratch
+#if (portNUM_PROCESSORS == 1)
+    /* No need to do anything */
+#elif  (portNUM_PROCESSORS == 2)
+    /* Optimized 2-core code. */
+    getcoreid \scratch
+    addx2 \reg,\reg,\scratch
+#else
+    /* Generalized n-core code. Untested! */
+    movi \scratch,portNUM_PROCESSORS
+    mull \scratch,\reg,\scratch
+    getcoreid \reg
+    add \reg,\scratch,\reg
+#endif
+   .endm
+/*
+--------------------------------------------------------------------------------
+  Macro extract_msb - return the input with only the highest bit set.
+
+  Input  : "ain"  - Input value, clobbered.
+  Output : "aout" - Output value, has only one bit set, MSB of "ain".
+  The two arguments must be different AR registers.
+--------------------------------------------------------------------------------
+*/
+
+    .macro  extract_msb     aout ain
+1:
+    addi    \aout, \ain, -1         /* aout = ain - 1        */
+    and     \ain, \ain, \aout       /* ain  = ain & aout     */
+    bnez    \ain, 1b                /* repeat until ain == 0 */
+    addi    \aout, \aout, 1         /* return aout + 1       */
+    .endm
+
+/*
+--------------------------------------------------------------------------------
+  Macro dispatch_c_isr - dispatch interrupts to user ISRs.
+  This will dispatch to user handlers (if any) that are registered in the
+  XTOS dispatch table (_xtos_interrupt_table). These handlers would have
+  been registered by calling _xtos_set_interrupt_handler(). There is one
+  exception - the timer interrupt used by the OS will not be dispatched
+  to a user handler - this must be handled by the caller of this macro.
+
+  Level triggered and software interrupts are automatically deasserted by
+  this code.
+
+  ASSUMPTIONS:
+    -- PS.INTLEVEL is set to "level" at entry
+    -- PS.EXCM = 0, C calling enabled
+
+  NOTE: For CALL0 ABI, a12-a15 have not yet been saved.
+
+  NOTE: This macro will use registers a0 and a2-a7. The arguments are:
+    level -- interrupt level
+    mask  -- interrupt bitmask for this level
+--------------------------------------------------------------------------------
+*/
+
+    .macro  dispatch_c_isr    level  mask
+
+    #ifdef CONFIG_PM_TRACE
+    movi a6, 0 /* = ESP_PM_TRACE_IDLE */
+    getcoreid a7
+    call4 esp_pm_trace_exit
+    #endif // CONFIG_PM_TRACE
+
+    /* Get mask of pending, enabled interrupts at this level into a2. */
+
+.L_xt_user_int_&level&:
+    rsr     a2, INTENABLE
+    rsr     a3, INTERRUPT
+    movi    a4, \mask
+    and     a2, a2, a3
+    and     a2, a2, a4
+    beqz    a2, 9f                          /* nothing to do */
+
+    /* This bit of code provides a nice debug backtrace in the debugger.
+       It does take a few more instructions, so undef XT_DEBUG_BACKTRACE
+       if you want to save the cycles.
+    */
+    #ifdef XT_DEBUG_BACKTRACE
+    #ifndef __XTENSA_CALL0_ABI__
+    rsr     a0, EPC_1 + \level - 1          /* return address */
+    movi    a4, 0xC0000000                  /* constant with top 2 bits set (call size) */
+    or      a0, a0, a4                      /* set top 2 bits */
+    addx2   a0, a4, a0                      /* clear top bit -- simulating call4 size   */
+    #endif
+    #endif
+
+    #ifdef CONFIG_PM_ENABLE
+    call4 esp_pm_impl_isr_hook
+    #endif
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a4, _xt_intexc_hooks
+    l32i    a4, a4, \level << 2
+    beqz    a4, 2f
+    #ifdef __XTENSA_CALL0_ABI__
+    callx0  a4
+    beqz    a2, 9f
+    #else
+    mov     a6, a2
+    callx4  a4
+    beqz    a6, 9f
+    mov     a2, a6
+    #endif
+2:
+    #endif
+
+    /* Now look up in the dispatch table and call user ISR if any. */
+    /* If multiple bits are set then MSB has highest priority.     */
+
+    extract_msb  a4, a2                     /* a4 = MSB of a2, a2 trashed */
+
+    #ifdef XT_USE_SWPRI
+    /* Enable all interrupts at this level that are numerically higher
+       than the one we just selected, since they are treated as higher
+       priority.
+    */
+    movi    a3, \mask                       /* a3 = all interrupts at this level */
+    add     a2, a4, a4                      /* a2 = a4 << 1 */
+    addi    a2, a2, -1                      /* a2 = mask of 1's <= a4 bit */
+    and     a2, a2, a3                      /* a2 = mask of all bits <= a4 at this level */
+    movi    a3, _xt_intdata
+    l32i    a6, a3, 4                       /* a6 = _xt_vpri_mask */
+    neg     a2, a2
+    addi    a2, a2, -1                      /* a2 = mask to apply */
+    and     a5, a6, a2                      /* mask off all bits <= a4 bit */
+    s32i    a5, a3, 4                       /* update _xt_vpri_mask */
+    rsr     a3, INTENABLE
+    and     a3, a3, a2                      /* mask off all bits <= a4 bit */
+    wsr     a3, INTENABLE
+    rsil    a3, \level - 1                  /* lower interrupt level by 1 */
+    #endif
+
+    movi    a3, XT_TIMER_INTEN              /* a3 = timer interrupt bit */
+    wsr     a4, INTCLEAR                    /* clear sw or edge-triggered interrupt */
+    beq     a3, a4, 7f                      /* if timer interrupt then skip table */
+
+    find_ms_setbit a3, a4, a3, 0            /* a3 = interrupt number */
+
+    get_percpu_entry_for a3, a12
+    movi    a4, _xt_interrupt_table
+    addx8   a3, a3, a4                      /* a3 = address of interrupt table entry */
+    l32i    a4, a3, XIE_HANDLER             /* a4 = handler address */
+    #ifdef __XTENSA_CALL0_ABI__
+    mov     a12, a6                         /* save in callee-saved reg */
+    l32i    a2, a3, XIE_ARG                 /* a2 = handler arg */
+    callx0  a4                              /* call handler */
+    mov     a2, a12
+    #else
+    mov     a2, a6                          /* save in windowed reg */
+    l32i    a6, a3, XIE_ARG                 /* a6 = handler arg */
+    callx4  a4                              /* call handler */
+    #endif
+
+    #ifdef XT_USE_SWPRI
+    j       8f
+    #else
+    j       .L_xt_user_int_&level&          /* check for more interrupts */
+    #endif
+
+7:
+
+    .ifeq XT_TIMER_INTPRI - \level
+.L_xt_user_int_timer_&level&:
+    /*
+    Interrupt handler for the RTOS tick timer if at this level.
+    We'll be reading the interrupt state again after this call
+    so no need to preserve any registers except a6 (vpri_mask).
+    */
+
+    #ifdef __XTENSA_CALL0_ABI__
+    mov     a12, a6
+    call0   XT_RTOS_TIMER_INT
+    mov     a2, a12
+    #else
+    mov     a2, a6
+    call4   XT_RTOS_TIMER_INT
+    #endif
+    .endif
+
+    #ifdef XT_USE_SWPRI
+    j       8f
+    #else
+    j       .L_xt_user_int_&level&          /* check for more interrupts */
+    #endif
+
+    #ifdef XT_USE_SWPRI
+8:
+    /* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from
+       virtual _xt_intenable which _could_ have changed during interrupt
+       processing. */
+
+    movi    a3, _xt_intdata
+    l32i    a4, a3, 0                       /* a4 = _xt_intenable    */
+    s32i    a2, a3, 4                       /* update _xt_vpri_mask  */
+    and     a4, a4, a2                      /* a4 = masked intenable */
+    wsr     a4, INTENABLE                   /* update INTENABLE      */
+    #endif
+
+9:
+    /* done */
+
+    .endm
+
+
+/*
+--------------------------------------------------------------------------------
+  Panic handler.
+  Should be reached by call0 (preferable) or jump only. If call0, a0 says where 
+  from. If on simulator, display panic message and abort, else loop indefinitely.
+--------------------------------------------------------------------------------
+*/
+
+    .section .iram1,"ax"
+    .global panicHandler
+
+    .global     _xt_panic
+    .type       _xt_panic,@function
+    .align      4
+    .literal_position
+    .align      4
+
+_xt_panic:
+    /* Allocate exception frame and save minimal context. */
+    mov     a0, sp
+    addi    sp, sp, -XT_STK_FRMSZ
+    s32i    a0, sp, XT_STK_A1
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -12                     /* for debug backtrace */
+    #endif
+    rsr     a0, PS                          /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_1                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -16                     /* for debug backtrace */
+    #endif
+    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
+    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
+    call0   _xt_context_save
+
+    /* Save exc cause and vaddr into exception frame */
+    rsr     a0, EXCCAUSE
+    s32i    a0, sp, XT_STK_EXCCAUSE
+    rsr     a0, EXCVADDR
+    s32i    a0, sp, XT_STK_EXCVADDR
+
+    /* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
+    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
+
+    s32i    a0, sp, XT_STK_A0
+
+    /* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
+    movi    a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
+    wsr     a0, PS
+
+    //Call panic handler
+    mov     a6,sp
+    call4 panicHandler
+
+
+    .align 4
+//Call using call0. Prints the hex char in a2. Kills a3, a4, a5
+panic_print_hex:
+    movi a3,0x60000000
+    movi a4,8
+panic_print_hex_loop:
+    l32i a5, a3, 0x1c
+    extui a5, a5, 16, 8
+    bgei a5,64,panic_print_hex_loop
+
+    srli a5,a2,28
+    bgei a5,10,panic_print_hex_a
+    addi a5,a5,'0'
+    j panic_print_hex_ok
+panic_print_hex_a:
+    addi a5,a5,'A'-10
+panic_print_hex_ok:
+    s32i a5,a3,0
+    slli a2,a2,4
+    
+    addi a4,a4,-1
+    bnei a4,0,panic_print_hex_loop
+    movi a5,' '
+    s32i a5,a3,0
+
+    ret
+
+
+
+    .section    .rodata, "a"
+    .align      4
+
+
+
+/*
+--------------------------------------------------------------------------------
+    Hooks to dynamically install handlers for exceptions and interrupts.
+    Allows automated regression frameworks to install handlers per test.
+    Consists of an array of function pointers indexed by interrupt level, 
+    with index 0 containing the entry for user exceptions.
+    Initialized with all 0s, meaning no handler is installed at each level.
+    See comment in xtensa_rtos.h for more details.
+
+    *WARNING*  This array is for all CPUs, that is, installing a hook for 
+    one CPU will install it for all others as well!
+--------------------------------------------------------------------------------
+*/
+
+    #ifdef XT_INTEXC_HOOKS
+    .data
+    .global     _xt_intexc_hooks
+    .type       _xt_intexc_hooks,@object
+    .align      4
+
+_xt_intexc_hooks:
+    .fill       XT_INTEXC_HOOK_NUM, 4, 0
+    #endif
+
+
+/*
+--------------------------------------------------------------------------------
+  EXCEPTION AND LEVEL 1 INTERRUPT VECTORS AND LOW LEVEL HANDLERS
+  (except window exception vectors).
+
+  Each vector goes at a predetermined location according to the Xtensa
+  hardware configuration, which is ensured by its placement in a special
+  section known to the Xtensa linker support package (LSP). It performs
+  the minimum necessary before jumping to the handler in the .text section.
+
+  The corresponding handler goes in the normal .text section. It sets up
+  the appropriate stack frame, saves a few vector-specific registers and
+  calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
+  and enter the RTOS, then sets up a C environment. It then calls the
+  user's interrupt handler code (which may be coded in C) and finally 
+  calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
+
+  While XT_RTOS_INT_EXIT does not return directly to the interruptee,
+  eventually the RTOS scheduler will want to dispatch the interrupted
+  task or handler. The scheduler will return to the exit point that was
+  saved in the interrupt stack frame at XT_STK_EXIT.
+--------------------------------------------------------------------------------
+*/
+
+
+/*
+--------------------------------------------------------------------------------
+Debug Exception.
+--------------------------------------------------------------------------------
+*/
+
+#if XCHAL_HAVE_DEBUG
+
+    .begin      literal_prefix .DebugExceptionVector
+    .section    .DebugExceptionVector.text, "ax"
+    .global     _DebugExceptionVector
+    .align      4
+    .global     xt_debugexception
+_DebugExceptionVector:
+    wsr     a0, EXCSAVE+XCHAL_DEBUGLEVEL    /* preserve a0 */
+    call0   xt_debugexception            /* load exception handler */
+
+    .end        literal_prefix
+
+#endif
+
+/*
+--------------------------------------------------------------------------------
+Double Exception.
+Double exceptions are not a normal occurrence. They indicate a bug of some kind.
+--------------------------------------------------------------------------------
+*/
+
+#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
+
+    .begin      literal_prefix .DoubleExceptionVector
+    .section    .DoubleExceptionVector.text, "ax"
+    .global     _DoubleExceptionVector
+    .align      4
+
+_DoubleExceptionVector:
+
+    #if XCHAL_HAVE_DEBUG
+    break   1, 4                            /* unhandled double exception */
+    #endif
+    movi    a0,PANIC_RSN_DOUBLEEXCEPTION
+    wsr     a0,EXCCAUSE
+    call0   _xt_panic                       /* does not return */
+    rfde                                    /* make a0 point here not later */
+
+    .end        literal_prefix
+
+#endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */
+
+/*
+--------------------------------------------------------------------------------
+Kernel Exception (including Level 1 Interrupt from kernel mode).
+--------------------------------------------------------------------------------
+*/
+
+    .begin      literal_prefix .KernelExceptionVector
+    .section    .KernelExceptionVector.text, "ax"
+    .global     _KernelExceptionVector
+    .align      4
+
+_KernelExceptionVector:
+
+    wsr     a0, EXCSAVE_1                   /* preserve a0 */
+    call0   _xt_kernel_exc                  /* kernel exception handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .section .iram1,"ax"
+    .align      4
+
+_xt_kernel_exc:
+    #if XCHAL_HAVE_DEBUG
+    break   1, 0                            /* unhandled kernel exception */
+    #endif
+    movi    a0,PANIC_RSN_KERNELEXCEPTION
+    wsr     a0,EXCCAUSE
+    call0   _xt_panic                       /* does not return */
+    rfe                                     /* make a0 point here not there */
+
+
+/*
+--------------------------------------------------------------------------------
+User Exception (including Level 1 Interrupt from user mode).
+--------------------------------------------------------------------------------
+*/
+
+    .begin      literal_prefix .UserExceptionVector
+    .section    .UserExceptionVector.text, "ax"
+    .global     _UserExceptionVector
+    .type       _UserExceptionVector,@function
+    .align      4
+
+_UserExceptionVector:
+
+    wsr     a0, EXCSAVE_1                   /* preserve a0 */
+    call0   _xt_user_exc                    /* user exception handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+/*
+--------------------------------------------------------------------------------
+  Insert some waypoints for jumping beyond the signed 8-bit range of
+  conditional branch instructions, so the conditional branchces to specific
+  exception handlers are not taken in the mainline. Saves some cycles in the
+  mainline.
+--------------------------------------------------------------------------------
+*/
+
+#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
+    .global   LoadStoreErrorHandler
+    .global   AlignmentErrorHandler
+#endif
+
+    .section .iram1,"ax"
+
+    #if XCHAL_HAVE_WINDOWED
+    .align      4
+_xt_to_alloca_exc:
+    call0   _xt_alloca_exc                  /* in window vectors section */
+    /* never returns here - call0 is used as a jump (see note at top) */
+    #endif
+
+    .align      4
+_xt_to_syscall_exc:
+    call0   _xt_syscall_exc
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    #if XCHAL_CP_NUM > 0
+    .align      4
+_xt_to_coproc_exc:
+    call0   _xt_coproc_exc
+    /* never returns here - call0 is used as a jump (see note at top) */
+    #endif
+
+#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
+    .align      4
+_call_loadstore_handler:
+    call0   LoadStoreErrorHandler
+    /* This will return only if wrong opcode or address out of range*/
+    j       .LS_exit
+
+    .align      4
+_call_alignment_handler:
+    call0   AlignmentErrorHandler
+    /* This will return only if wrong opcode or address out of range*/
+    addi    a0, a0, 1
+    j       .LS_exit
+#endif
+
+/*
+--------------------------------------------------------------------------------
+  User exception handler.
+--------------------------------------------------------------------------------
+*/
+
+    .type       _xt_user_exc,@function
+    .align      4
+
+_xt_user_exc:
+
+    /* If level 1 interrupt then jump to the dispatcher */
+    rsr     a0, EXCCAUSE
+    beqi    a0, EXCCAUSE_LEVEL1INTERRUPT, _xt_lowint1
+
+    /* Handle any coprocessor exceptions. Rely on the fact that exception
+       numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors.
+    */
+    #if XCHAL_CP_NUM > 0
+    bgeui   a0, EXCCAUSE_CP0_DISABLED, _xt_to_coproc_exc
+    #endif
+
+    /* Handle alloca and syscall exceptions */
+    #if XCHAL_HAVE_WINDOWED
+    beqi    a0, EXCCAUSE_ALLOCA,  _xt_to_alloca_exc
+    #endif
+    beqi    a0, EXCCAUSE_SYSCALL, _xt_to_syscall_exc
+
+#ifdef CONFIG_ESP32_IRAM_AS_8BIT_ACCESSIBLE_MEMORY
+    beqi    a0, EXCCAUSE_LOAD_STORE_ERROR, _call_loadstore_handler
+
+    addi    a0, a0, -1
+    beqi    a0, 8, _call_alignment_handler
+    addi    a0, a0, 1
+.LS_exit:
+#endif
+
+    /* Handle all other exceptions. All can have user-defined handlers. */
+    /* NOTE: we'll stay on the user stack for exception handling.       */
+
+    /* Allocate exception frame and save minimal context. */
+    mov     a0, sp
+    addi    sp, sp, -XT_STK_FRMSZ
+    s32i    a0, sp, XT_STK_A1
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -12                     /* for debug backtrace */
+    #endif
+    rsr     a0, PS                          /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_1                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -16                     /* for debug backtrace */
+    #endif
+    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
+    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
+    call0   _xt_context_save
+
+    /* Save exc cause and vaddr into exception frame */
+    rsr     a0, EXCCAUSE
+    s32i    a0, sp, XT_STK_EXCCAUSE
+    rsr     a0, EXCVADDR
+    s32i    a0, sp, XT_STK_EXCVADDR
+
+    /* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
+    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+
+    /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+
+    #ifdef XT_DEBUG_BACKTRACE
+    #ifndef __XTENSA_CALL0_ABI__
+    rsr     a0, EPC_1                       /* return address for debug backtrace */
+    movi    a5, 0xC0000000                  /* constant with top 2 bits set (call size) */
+    rsync                                   /* wait for WSR.PS to complete */
+    or      a0, a0, a5                      /* set top 2 bits */
+    addx2   a0, a5, a0                      /* clear top bit -- thus simulating call4 size */
+    #else
+    rsync                                   /* wait for WSR.PS to complete */
+    #endif
+    #endif
+
+    rsr     a2, EXCCAUSE                    /* recover exc cause */
+
+    #ifdef XT_INTEXC_HOOKS
+    /*
+    Call exception hook to pre-handle exceptions (if installed).
+    Pass EXCCAUSE in a2, and check result in a2 (if -1, skip default handling).
+    */
+    movi    a4, _xt_intexc_hooks
+    l32i    a4, a4, 0                       /* user exception hook index 0 */
+    beqz    a4, 1f
+.Ln_xt_user_exc_call_hook:
+    #ifdef __XTENSA_CALL0_ABI__
+    callx0  a4
+    beqi    a2, -1, .L_xt_user_done
+    #else
+    mov     a6, a2
+    callx4  a4
+    beqi    a6, -1, .L_xt_user_done
+    mov     a2, a6
+    #endif
+1:
+    #endif
+
+    rsr     a2, EXCCAUSE                    /* recover exc cause */
+    movi    a3, _xt_exception_table
+    get_percpu_entry_for a2, a4
+    addx4   a4, a2, a3                      /* a4 = address of exception table entry */
+    l32i    a4, a4, 0                       /* a4 = handler address */
+    #ifdef __XTENSA_CALL0_ABI__
+    mov     a2, sp                          /* a2 = pointer to exc frame */
+    callx0  a4                              /* call handler */
+    #else
+    mov     a6, sp                          /* a6 = pointer to exc frame */
+    callx4  a4                              /* call handler */
+    #endif
+
+.L_xt_user_done:
+
+    /* Restore context and return */
+    call0   _xt_context_restore
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, PS
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_1
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove exception frame */
+    rsync                                   /* ensure PS and EPC written */
+    rfe                                     /* PS.EXCM is cleared */
+
+
+/*
+--------------------------------------------------------------------------------
+  Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+  on entry and used to return to a thread or interrupted interrupt handler.
+--------------------------------------------------------------------------------
+*/
+
+    .global     _xt_user_exit
+    .type       _xt_user_exit,@function
+    .align      4
+_xt_user_exit:
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, PS
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_1
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure PS and EPC written */
+    rfe                                     /* PS.EXCM is cleared */
+
+
+/*
+
+--------------------------------------------------------------------------------
+Syscall Exception Handler (jumped to from User Exception Handler).
+Syscall 0 is required to spill the register windows (no-op in Call 0 ABI).
+Only syscall 0 is handled here. Other syscalls return -1 to caller in a2.
+--------------------------------------------------------------------------------
+*/
+
+    .section .iram1,"ax"
+    .type       _xt_syscall_exc,@function
+    .align      4
+_xt_syscall_exc:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /*
+    Save minimal regs for scratch. Syscall 0 does nothing in Call0 ABI.
+    Use a minimal stack frame (16B) to save A2 & A3 for scratch.
+    PS.EXCM could be cleared here, but unlikely to improve worst-case latency.
+    rsr     a0, PS
+    addi    a0, a0, -PS_EXCM_MASK
+    wsr     a0, PS
+    */
+    addi    sp, sp, -16
+    s32i    a2, sp, 8
+    s32i    a3, sp, 12
+    #else   /* Windowed ABI */
+    /*
+    Save necessary context and spill the register windows.
+    PS.EXCM is still set and must remain set until after the spill.
+    Reuse context save function though it saves more than necessary.
+    For this reason, a full interrupt stack frame is allocated.
+    */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
+    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
+    call0   _xt_context_save
+    #endif
+
+    /*
+    Grab the interruptee's PC and skip over the 'syscall' instruction.
+    If it's at the end of a zero-overhead loop and it's not on the last
+    iteration, decrement loop counter and skip to beginning of loop.
+    */
+    rsr     a2, EPC_1                       /* a2 = PC of 'syscall' */
+    addi    a3, a2, 3                       /* ++PC                 */
+    #if XCHAL_HAVE_LOOPS
+    rsr     a0, LEND                        /* if (PC == LEND       */
+    bne     a3, a0, 1f
+    rsr     a0, LCOUNT                      /*     && LCOUNT != 0)  */
+    beqz    a0, 1f                          /* {                    */
+    addi    a0, a0, -1                      /*   --LCOUNT           */
+    rsr     a3, LBEG                        /*   PC = LBEG          */
+    wsr     a0, LCOUNT                      /* }                    */
+    #endif
+1:  wsr     a3, EPC_1                       /* update PC            */
+
+    /* Restore interruptee's context and return from exception. */
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a2, sp, 8
+    l32i    a3, sp, 12
+    addi    sp, sp, 16
+    #else
+    call0   _xt_context_restore
+    addi    sp, sp, XT_STK_FRMSZ
+    #endif
+    movi    a0, -1
+    movnez  a2, a0, a2                      /* return -1 if not syscall 0 */
+    rsr     a0, EXCSAVE_1
+    rfe
+
+/*
+--------------------------------------------------------------------------------
+Co-Processor Exception Handler (jumped to from User Exception Handler).
+These exceptions are generated by co-processor instructions, which are only
+allowed in thread code (not in interrupts or kernel code). This restriction is 
+deliberately imposed to reduce the burden of state-save/restore in interrupts.
+--------------------------------------------------------------------------------
+*/
+#if XCHAL_CP_NUM > 0
+
+    .section .rodata, "a"
+
+/* Offset to CP n save area in thread's CP save area. */
+    .global _xt_coproc_sa_offset
+    .type   _xt_coproc_sa_offset,@object
+    .align  16                      /* minimize crossing cache boundaries */
+_xt_coproc_sa_offset:
+    .word   XT_CP0_SA, XT_CP1_SA, XT_CP2_SA, XT_CP3_SA
+    .word   XT_CP4_SA, XT_CP5_SA, XT_CP6_SA, XT_CP7_SA
+
+/* Bitmask for CP n's CPENABLE bit. */
+    .type   _xt_coproc_mask,@object
+    .align  16,,8                   /* try to keep it all in one cache line */
+    .set    i, 0
+_xt_coproc_mask:
+    .rept   XCHAL_CP_MAX
+    .long   (i<<16) | (1<<i)    // upper 16-bits = i, lower = bitmask
+    .set    i, i+1
+    .endr
+
+    .data
+
+/* Owner thread of CP n, identified by thread's CP save area (0 = unowned). */
+    .global _xt_coproc_owner_sa
+    .type   _xt_coproc_owner_sa,@object
+    .align  16,,XCHAL_CP_MAX<<2     /* minimize crossing cache boundaries */
+_xt_coproc_owner_sa:
+    .space  (XCHAL_CP_MAX * portNUM_PROCESSORS) << 2
+
+    .section .iram1,"ax"
+
+
+    .align  4
+.L_goto_invalid:
+    j   .L_xt_coproc_invalid    /* not in a thread (invalid) */
+    .align  4
+.L_goto_done:
+    j   .L_xt_coproc_done
+
+
+/*
+--------------------------------------------------------------------------------
+  Coprocessor exception handler.
+  At entry, only a0 has been saved (in EXCSAVE_1).
+--------------------------------------------------------------------------------
+*/
+
+    .type   _xt_coproc_exc,@function
+    .align  4
+
+_xt_coproc_exc:
+
+    /* Allocate interrupt stack frame and save minimal context. */
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -12                     /* for debug backtrace */
+    #endif
+    rsr     a0, PS                          /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_1                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -16                     /* for debug backtrace */
+    #endif
+    movi    a0, _xt_user_exit               /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    rsr     a0, EXCCAUSE
+    s32i    a5, sp, XT_STK_A5               /* save a5 */
+    addi    a5, a0, -EXCCAUSE_CP0_DISABLED  /* a5 = CP index */
+
+    /* Save a few more of interruptee's registers (a5 was already saved). */
+    s32i    a2,  sp, XT_STK_A2
+    s32i    a3,  sp, XT_STK_A3
+    s32i    a4,  sp, XT_STK_A4
+    s32i    a15, sp, XT_STK_A15
+
+    /* Get co-processor state save area of new owner thread. */
+    call0   XT_RTOS_CP_STATE                /* a15 = new owner's save area */
+    beqz    a15, .L_goto_invalid            /* not in a thread (invalid) */
+
+    /* Enable the co-processor's bit in CPENABLE. */
+    movi    a0, _xt_coproc_mask
+    rsr     a4, CPENABLE                    /* a4 = CPENABLE */
+    addx4   a0, a5, a0                      /* a0 = &_xt_coproc_mask[n] */
+    l32i    a0, a0, 0                       /* a0 = (n << 16) | (1 << n) */
+
+    /* FPU operations are incompatible with non-pinned tasks. If we have a FPU operation
+       here, to keep the entire thing from crashing, it's better to pin the task to whatever
+       core we're running on now. */
+    movi    a2, pxCurrentTCB
+    getcoreid a3
+    addx4     a2,  a3, a2
+    l32i    a2, a2, 0                       /* a2 = start of pxCurrentTCB[cpuid] */
+    addi    a2, a2, TASKTCB_XCOREID_OFFSET  /* offset to xCoreID in tcb struct */
+    s32i    a3, a2, 0                       /* store current cpuid */
+
+    /* Grab correct xt_coproc_owner_sa for this core */
+    movi    a2, XCHAL_CP_MAX << 2
+    mull    a2, a2, a3                      /* multiply by current processor id */
+    movi    a3, _xt_coproc_owner_sa         /* a3 = base of owner array */
+    add     a3, a3, a2                      /* a3 = owner area needed for this processor */
+
+    extui   a2, a0, 0, 16                   /* coprocessor bitmask portion */
+    or      a4, a4, a2                      /* a4 = CPENABLE | (1 << n) */
+    wsr     a4, CPENABLE
+
+/* 
+Keep loading _xt_coproc_owner_sa[n] atomic (=load once, then use that value
+everywhere): _xt_coproc_release assumes it works like this in order not to need
+locking.
+*/
+
+
+    /* Get old coprocessor owner thread (save area ptr) and assign new one.  */
+    addx4   a3,  a5, a3                      /* a3 = &_xt_coproc_owner_sa[n] */
+    l32i    a2,  a3, 0                       /* a2 = old owner's save area */
+    s32i    a15, a3, 0                       /* _xt_coproc_owner_sa[n] = new */
+    rsync                                    /* ensure wsr.CPENABLE is complete */
+
+    /* Only need to context switch if new owner != old owner. */
+    beq     a15, a2, .L_goto_done           /* new owner == old, we're done */
+
+    /* If no old owner then nothing to save. */
+    beqz    a2, .L_check_new
+
+    /* If old owner not actively using CP then nothing to save. */
+    l16ui   a4,  a2,  XT_CPENABLE           /* a4 = old owner's CPENABLE */
+    bnone   a4,  a0,  .L_check_new          /* old owner not using CP    */
+
+.L_save_old:
+    /* Save old owner's coprocessor state. */
+
+    movi    a5, _xt_coproc_sa_offset
+
+    /* Mark old owner state as no longer active (CPENABLE bit n clear). */
+    xor     a4,  a4,  a0                    /* clear CP bit in CPENABLE    */
+    s16i    a4,  a2,  XT_CPENABLE           /* update old owner's CPENABLE */
+
+    extui   a4,  a0,  16,  5                /* a4 = CP index = n */
+    addx4   a5,  a4,  a5                    /* a5 = &_xt_coproc_sa_offset[n] */
+
+    /* Mark old owner state as saved (CPSTORED bit n set). */
+    l16ui   a4,  a2,  XT_CPSTORED           /* a4 = old owner's CPSTORED */
+    l32i    a5,  a5,  0                     /* a5 = XT_CP[n]_SA offset */
+    or      a4,  a4,  a0                    /* set CP in old owner's CPSTORED */
+    s16i    a4,  a2,  XT_CPSTORED           /* update old owner's CPSTORED */
+    l32i    a2, a2, XT_CP_ASA               /* ptr to actual (aligned) save area */
+    extui   a3, a0, 16, 5                   /* a3 = CP index = n */
+    add     a2, a2, a5                      /* a2 = old owner's area for CP n */
+
+    /*
+    The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
+    It is theoretically possible for Xtensa processor designers to write TIE 
+    that causes more address registers to be affected, but it is generally 
+    unlikely. If that ever happens, more registers needs to be saved/restored
+    around this macro invocation, and the value in a15 needs to be recomputed.
+    */
+    xchal_cpi_store_funcbody
+
+.L_check_new:
+    /* Check if any state has to be restored for new owner. */
+    /* NOTE: a15 = new owner's save area, cannot be zero when we get here. */
+
+    l16ui   a3,  a15, XT_CPSTORED           /* a3 = new owner's CPSTORED */
+    movi    a4, _xt_coproc_sa_offset
+    bnone   a3,  a0,  .L_check_cs           /* full CP not saved, check callee-saved */
+    xor     a3,  a3,  a0                    /* CPSTORED bit is set, clear it */
+    s16i    a3,  a15, XT_CPSTORED           /* update new owner's CPSTORED */
+
+    /* Adjust new owner's save area pointers to area for CP n. */
+    extui   a3,  a0, 16, 5                  /* a3 = CP index = n */
+    addx4   a4,  a3, a4                     /* a4 = &_xt_coproc_sa_offset[n] */
+    l32i    a4,  a4, 0                      /* a4 = XT_CP[n]_SA */
+    l32i    a5, a15, XT_CP_ASA              /* ptr to actual (aligned) save area */
+    add     a2,  a4, a5                     /* a2 = new owner's area for CP */
+
+    /*
+    The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
+    It is theoretically possible for Xtensa processor designers to write TIE 
+    that causes more address registers to be affected, but it is generally 
+    unlikely. If that ever happens, more registers needs to be saved/restored
+    around this macro invocation.
+    */
+    xchal_cpi_load_funcbody
+
+    /* Restore interruptee's saved registers. */
+    /* Can omit rsync for wsr.CPENABLE here because _xt_user_exit does it. */
+.L_xt_coproc_done:
+    l32i    a15, sp, XT_STK_A15
+    l32i    a5,  sp, XT_STK_A5
+    l32i    a4,  sp, XT_STK_A4
+    l32i    a3,  sp, XT_STK_A3
+    l32i    a2,  sp, XT_STK_A2
+    call0   _xt_user_exit                   /* return via exit dispatcher */
+    /* Never returns here - call0 is used as a jump (see note at top) */
+
+.L_check_cs:
+    /* a0 = CP mask in low bits, a15 = new owner's save area */
+    l16ui   a2, a15, XT_CP_CS_ST            /* a2 = mask of CPs saved    */
+    bnone   a2,  a0, .L_xt_coproc_done      /* if no match then done     */
+    and     a2,  a2, a0                     /* a2 = which CPs to restore */
+    extui   a2,  a2, 0, 8                   /* extract low 8 bits        */
+    s32i    a6,  sp, XT_STK_A6              /* save extra needed regs    */
+    s32i    a7,  sp, XT_STK_A7
+    s32i    a13, sp, XT_STK_A13
+    s32i    a14, sp, XT_STK_A14
+    call0   _xt_coproc_restorecs            /* restore CP registers      */
+    l32i    a6,  sp, XT_STK_A6              /* restore saved registers   */
+    l32i    a7,  sp, XT_STK_A7
+    l32i    a13, sp, XT_STK_A13
+    l32i    a14, sp, XT_STK_A14
+    j       .L_xt_coproc_done
+
+    /* Co-processor exception occurred outside a thread (not supported). */
+.L_xt_coproc_invalid:
+    movi    a0,PANIC_RSN_COPROCEXCEPTION
+    wsr     a0,EXCCAUSE
+    call0   _xt_panic                       /* not in a thread (invalid) */
+    /* never returns */
+
+
+#endif /* XCHAL_CP_NUM */
+
+
+/*
+-------------------------------------------------------------------------------
+  Level 1 interrupt dispatch. Assumes stack frame has not been allocated yet.
+-------------------------------------------------------------------------------
+*/
+
+    .section .iram1,"ax"
+    .type       _xt_lowint1,@function
+    .align      4
+
+_xt_lowint1:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, PS                          /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_1                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_user_exit               /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */ 
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(1) | PS_UM
+    #else 
+    movi    a0, PS_INTLEVEL(1) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+
+/*
+-------------------------------------------------------------------------------
+  MEDIUM PRIORITY (LEVEL 2+) INTERRUPT VECTORS AND LOW LEVEL HANDLERS.
+
+  Medium priority interrupts are by definition those with priority greater
+  than 1 and not greater than XCHAL_EXCM_LEVEL. These are disabled by
+  setting PS.EXCM and therefore can easily support a C environment for
+  handlers in C, and interact safely with an RTOS.
+
+  Each vector goes at a predetermined location according to the Xtensa
+  hardware configuration, which is ensured by its placement in a special
+  section known to the Xtensa linker support package (LSP). It performs
+  the minimum necessary before jumping to the handler in the .text section.
+
+  The corresponding handler goes in the normal .text section. It sets up
+  the appropriate stack frame, saves a few vector-specific registers and
+  calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
+  and enter the RTOS, then sets up a C environment. It then calls the
+  user's interrupt handler code (which may be coded in C) and finally 
+  calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
+
+  While XT_RTOS_INT_EXIT does not return directly to the interruptee,
+  eventually the RTOS scheduler will want to dispatch the interrupted
+  task or handler. The scheduler will return to the exit point that was
+  saved in the interrupt stack frame at XT_STK_EXIT.
+-------------------------------------------------------------------------------
+*/
+
+#if XCHAL_EXCM_LEVEL >= 2
+
+    .begin      literal_prefix .Level2InterruptVector
+    .section    .Level2InterruptVector.text, "ax"
+    .global     _Level2Vector
+    .type       _Level2Vector,@function
+    .align      4
+_Level2Vector:
+    wsr     a0, EXCSAVE_2                   /* preserve a0 */
+    call0   _xt_medint2                     /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .section .iram1,"ax"
+    .type       _xt_medint2,@function
+    .align      4
+_xt_medint2:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_2                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_2                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_2                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint2_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(2) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(2) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint2_exit
+    .type       _xt_medint2_exit,@function
+    .align      4
+_xt_medint2_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_2
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_2
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     2
+
+#endif  /* Level 2 */
+
+#if XCHAL_EXCM_LEVEL >= 3
+
+    .begin      literal_prefix .Level3InterruptVector
+    .section    .Level3InterruptVector.text, "ax"
+    .global     _Level3Vector
+    .type       _Level3Vector,@function
+    .align      4
+_Level3Vector:
+    wsr     a0, EXCSAVE_3                   /* preserve a0 */
+    call0   _xt_medint3                     /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .section .iram1,"ax"
+    .type       _xt_medint3,@function
+    .align      4
+_xt_medint3:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_3                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_3                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_3                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint3_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(3) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(3) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint3_exit
+    .type       _xt_medint3_exit,@function
+    .align      4
+_xt_medint3_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_3
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_3
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     3
+
+#endif  /* Level 3 */
+
+#if XCHAL_EXCM_LEVEL >= 4
+
+    .begin      literal_prefix .Level4InterruptVector
+    .section    .Level4InterruptVector.text, "ax"
+    .global     _Level4Vector
+    .type       _Level4Vector,@function
+    .align      4
+_Level4Vector:
+    wsr     a0, EXCSAVE_4                   /* preserve a0 */
+    call0   _xt_medint4                     /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .section .iram1,"ax"
+    .type       _xt_medint4,@function
+    .align      4
+_xt_medint4:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_4                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_4                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_4                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint4_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(4) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(4) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint4_exit
+    .type       _xt_medint4_exit,@function
+    .align      4
+_xt_medint4_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_4
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_4
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     4
+
+#endif  /* Level 4 */
+
+#if XCHAL_EXCM_LEVEL >= 5
+
+    .begin      literal_prefix .Level5InterruptVector
+    .section    .Level5InterruptVector.text, "ax"
+    .global     _Level5Vector
+    .type       _Level5Vector,@function
+    .align      4
+_Level5Vector:
+    wsr     a0, EXCSAVE_5                   /* preserve a0 */
+    call0   _xt_medint5                     /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .section .iram1,"ax"
+    .type       _xt_medint5,@function
+    .align      4
+_xt_medint5:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_5                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_5                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_5                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint5_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(5) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint5_exit
+    .type       _xt_medint5_exit,@function
+    .align      4
+_xt_medint5_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_5
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_5
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     5
+
+#endif  /* Level 5 */
+
+#if XCHAL_EXCM_LEVEL >= 6
+
+    .begin      literal_prefix .Level6InterruptVector
+    .section    .Level6InterruptVector.text, "ax"
+    .global     _Level6Vector
+    .type       _Level6Vector,@function
+    .align      4
+_Level6Vector:
+    wsr     a0, EXCSAVE_6                   /* preserve a0 */
+    call0   _xt_medint6                     /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .section .iram1,"ax"
+    .type       _xt_medint6,@function
+    .align      4
+_xt_medint6:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_6                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_6                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_6                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint6_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(6) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(6) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint6_exit
+    .type       _xt_medint6_exit,@function
+    .align      4
+_xt_medint6_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_6
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_6
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     6
+
+#endif  /* Level 6 */
+
+
+/*******************************************************************************
+
+HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS
+
+High priority interrupts are by definition those with priorities greater
+than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority
+interrupts cannot interact with the RTOS, that is they must save all regs
+they use and not call any RTOS function.
+
+A further restriction imposed by the Xtensa windowed architecture is that
+high priority interrupts must not modify the stack area even logically
+"above" the top of the interrupted stack (they need to provide their
+own stack or static save area).
+
+Cadence Design Systems recommends high priority interrupt handlers be coded in assembly
+and used for purposes requiring very short service times.
+
+Here are templates for high priority (level 2+) interrupt vectors.
+They assume only one interrupt per level to avoid the burden of identifying
+which interrupts at this level are pending and enabled. This allows for 
+minimum latency and avoids having to save/restore a2 in addition to a0.
+If more than one interrupt per high priority level is configured, this burden
+is on the handler which in any case must provide a way to save and restore
+registers it uses without touching the interrupted stack.
+
+Each vector goes at a predetermined location according to the Xtensa
+hardware configuration, which is ensured by its placement in a special
+section known to the Xtensa linker support package (LSP). It performs
+the minimum necessary before jumping to the handler in the .text section.
+
+*******************************************************************************/
+
+/*
+These stubs just call xt_highintX/xt_nmi to handle the real interrupt. Please define
+these in an external assembly source file. If these symbols are not defined anywhere
+else, the defaults in xtensa_vector_defaults.S are used.
+*/
+
+#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
+
+    .begin      literal_prefix .Level2InterruptVector
+    .section    .Level2InterruptVector.text, "ax"
+    .global     _Level2Vector
+    .type       _Level2Vector,@function
+    .global     xt_highint2
+    .align      4
+_Level2Vector:
+    wsr     a0, EXCSAVE_2                   /* preserve a0 */
+    call0   xt_highint2                    /* load interrupt handler */
+
+    .end        literal_prefix
+
+#endif  /* Level 2 */
+
+#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
+
+    .begin      literal_prefix .Level3InterruptVector
+    .section    .Level3InterruptVector.text, "ax"
+    .global     _Level3Vector
+    .type       _Level3Vector,@function
+    .global     xt_highint3
+    .align      4
+_Level3Vector:
+    wsr     a0, EXCSAVE_3                   /* preserve a0 */
+    call0   xt_highint3                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+#endif  /* Level 3 */
+
+#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
+
+    .begin      literal_prefix .Level4InterruptVector
+    .section    .Level4InterruptVector.text, "ax"
+    .global     _Level4Vector
+    .type       _Level4Vector,@function
+    .global     xt_highint4
+    .align      4
+_Level4Vector:
+    wsr     a0, EXCSAVE_4                   /* preserve a0 */
+    call0   xt_highint4                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+#endif  /* Level 4 */
+
+#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
+
+    .begin      literal_prefix .Level5InterruptVector
+    .section    .Level5InterruptVector.text, "ax"
+    .global     _Level5Vector
+    .type       _Level5Vector,@function
+    .global     xt_highint5
+    .align      4
+_Level5Vector:
+    wsr     a0, EXCSAVE_5                   /* preserve a0 */
+    call0   xt_highint5                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+#endif  /* Level 5 */
+
+#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
+
+    .begin      literal_prefix .Level6InterruptVector
+    .section    .Level6InterruptVector.text, "ax"
+    .global     _Level6Vector
+    .type       _Level6Vector,@function
+    .global     xt_highint6
+    .align      4
+_Level6Vector:
+    wsr     a0, EXCSAVE_6                   /* preserve a0 */
+    call0   xt_highint6                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+#endif  /* Level 6 */
+
+#if XCHAL_HAVE_NMI
+
+    .begin      literal_prefix .NMIExceptionVector
+    .section    .NMIExceptionVector.text, "ax"
+    .global     _NMIExceptionVector
+    .type       _NMIExceptionVector,@function
+    .global     xt_nmi
+    .align      4
+_NMIExceptionVector:
+    wsr     a0, EXCSAVE + XCHAL_NMILEVEL  _ /* preserve a0 */
+    call0   xt_nmi                         /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+#endif  /* NMI */
+
+
+/*******************************************************************************
+
+WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER
+
+Here is the code for each window overflow/underflow exception vector and 
+(interspersed) efficient code for handling the alloca exception cause.
+Window exceptions are handled entirely in the vector area and are very
+tight for performance. The alloca exception is also handled entirely in 
+the window vector area so comes at essentially no cost in code size.
+Users should never need to modify them and Cadence Design Systems recommends 
+they do not.
+
+Window handlers go at predetermined vector locations according to the
+Xtensa hardware configuration, which is ensured by their placement in a
+special section known to the Xtensa linker support package (LSP). Since
+their offsets in that section are always the same, the LSPs do not define
+a section per vector.
+
+These things are coded for XEA2 only (XEA1 is not supported).
+
+Note on Underflow Handlers:
+The underflow handler for returning from call[i+1] to call[i]
+must preserve all the registers from call[i+1]'s window.
+In particular, a0 and a1 must be preserved because the RETW instruction
+will be reexecuted (and may even underflow if an intervening exception
+has flushed call[i]'s registers).
+Registers a2 and up may contain return values.
+
+*******************************************************************************/
+
+#if XCHAL_HAVE_WINDOWED
+
+    .section .WindowVectors.text, "ax"
+
+/*
+--------------------------------------------------------------------------------
+Window Overflow Exception for Call4.
+
+Invoked if a call[i] referenced a register (a4-a15)
+that contains data from ancestor call[j];
+call[j] had done a call4 to call[j+1].
+On entry here:
+    window rotated to call[j] start point;
+        a0-a3 are registers to be saved;
+        a4-a15 must be preserved;
+        a5 is call[j+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x0
+    .global _WindowOverflow4
+_WindowOverflow4:
+
+    s32e    a0, a5, -16     /* save a0 to call[j+1]'s stack frame */
+    s32e    a1, a5, -12     /* save a1 to call[j+1]'s stack frame */
+    s32e    a2, a5,  -8     /* save a2 to call[j+1]'s stack frame */
+    s32e    a3, a5,  -4     /* save a3 to call[j+1]'s stack frame */
+    rfwo                    /* rotates back to call[i] position */
+
+/*
+--------------------------------------------------------------------------------
+Window Underflow Exception for Call4
+
+Invoked by RETW returning from call[i+1] to call[i]
+where call[i]'s registers must be reloaded (not live in ARs);
+where call[i] had done a call4 to call[i+1].
+On entry here:
+        window rotated to call[i] start point;
+        a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
+        a4-a15 must be preserved (they are call[i+1].reg[0..11]);
+        a5 is call[i+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x40
+    .global _WindowUnderflow4
+_WindowUnderflow4:
+
+    l32e    a0, a5, -16     /* restore a0 from call[i+1]'s stack frame */
+    l32e    a1, a5, -12     /* restore a1 from call[i+1]'s stack frame */
+    l32e    a2, a5,  -8     /* restore a2 from call[i+1]'s stack frame */
+    l32e    a3, a5,  -4     /* restore a3 from call[i+1]'s stack frame */
+    rfwu
+
+/*
+--------------------------------------------------------------------------------
+Handle alloca exception generated by interruptee executing 'movsp'.
+This uses space between the window vectors, so is essentially "free".
+All interruptee's regs are intact except a0 which is saved in EXCSAVE_1,
+and PS.EXCM has been set by the exception hardware (can't be interrupted).
+The fact the alloca exception was taken means the registers associated with
+the base-save area have been spilled and will be restored by the underflow
+handler, so those 4 registers are available for scratch.
+The code is optimized to avoid unaligned branches and minimize cache misses.
+--------------------------------------------------------------------------------
+*/
+
+    .align  4
+    .global _xt_alloca_exc
+_xt_alloca_exc:
+
+    rsr     a0, WINDOWBASE  /* grab WINDOWBASE before rotw changes it */
+    rotw    -1              /* WINDOWBASE goes to a4, new a0-a3 are scratch */
+    rsr     a2, PS
+    extui   a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
+    xor     a3, a3, a4      /* bits changed from old to current windowbase */
+    rsr     a4, EXCSAVE_1   /* restore original a0 (now in a4) */
+    slli    a3, a3, XCHAL_PS_OWB_SHIFT
+    xor     a2, a2, a3      /* flip changed bits in old window base */
+    wsr     a2, PS          /* update PS.OWB to new window base */
+    rsync
+
+    _bbci.l a4, 31, _WindowUnderflow4
+    rotw    -1              /* original a0 goes to a8 */
+    _bbci.l a8, 30, _WindowUnderflow8
+    rotw    -1
+    j               _WindowUnderflow12
+
+/*
+--------------------------------------------------------------------------------
+Window Overflow Exception for Call8
+
+Invoked if a call[i] referenced a register (a4-a15)
+that contains data from ancestor call[j];
+call[j] had done a call8 to call[j+1].
+On entry here:
+    window rotated to call[j] start point;
+        a0-a7 are registers to be saved;
+        a8-a15 must be preserved;
+        a9 is call[j+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x80
+    .global _WindowOverflow8
+_WindowOverflow8:
+
+    s32e    a0, a9, -16     /* save a0 to call[j+1]'s stack frame */
+    l32e    a0, a1, -12     /* a0 <- call[j-1]'s sp
+                               (used to find end of call[j]'s frame) */
+    s32e    a1, a9, -12     /* save a1 to call[j+1]'s stack frame */
+    s32e    a2, a9,  -8     /* save a2 to call[j+1]'s stack frame */
+    s32e    a3, a9,  -4     /* save a3 to call[j+1]'s stack frame */
+    s32e    a4, a0, -32     /* save a4 to call[j]'s stack frame */
+    s32e    a5, a0, -28     /* save a5 to call[j]'s stack frame */
+    s32e    a6, a0, -24     /* save a6 to call[j]'s stack frame */
+    s32e    a7, a0, -20     /* save a7 to call[j]'s stack frame */
+    rfwo                    /* rotates back to call[i] position */
+
+/*
+--------------------------------------------------------------------------------
+Window Underflow Exception for Call8
+
+Invoked by RETW returning from call[i+1] to call[i]
+where call[i]'s registers must be reloaded (not live in ARs);
+where call[i] had done a call8 to call[i+1].
+On entry here:
+        window rotated to call[i] start point;
+        a0-a7 are undefined, must be reloaded with call[i].reg[0..7];
+        a8-a15 must be preserved (they are call[i+1].reg[0..7]);
+        a9 is call[i+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0xC0
+    .global _WindowUnderflow8
+_WindowUnderflow8:
+
+    l32e    a0, a9, -16     /* restore a0 from call[i+1]'s stack frame */
+    l32e    a1, a9, -12     /* restore a1 from call[i+1]'s stack frame */
+    l32e    a2, a9,  -8     /* restore a2 from call[i+1]'s stack frame */
+    l32e    a7, a1, -12     /* a7 <- call[i-1]'s sp
+                               (used to find end of call[i]'s frame) */
+    l32e    a3, a9,  -4     /* restore a3 from call[i+1]'s stack frame */
+    l32e    a4, a7, -32     /* restore a4 from call[i]'s stack frame */
+    l32e    a5, a7, -28     /* restore a5 from call[i]'s stack frame */
+    l32e    a6, a7, -24     /* restore a6 from call[i]'s stack frame */
+    l32e    a7, a7, -20     /* restore a7 from call[i]'s stack frame */
+    rfwu
+
+/*
+--------------------------------------------------------------------------------
+Window Overflow Exception for Call12
+
+Invoked if a call[i] referenced a register (a4-a15)
+that contains data from ancestor call[j];
+call[j] had done a call12 to call[j+1].
+On entry here:
+    window rotated to call[j] start point;
+        a0-a11 are registers to be saved;
+        a12-a15 must be preserved;
+        a13 is call[j+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x100
+    .global _WindowOverflow12
+_WindowOverflow12:
+
+    s32e    a0,  a13, -16   /* save a0 to call[j+1]'s stack frame */
+    l32e    a0,  a1,  -12   /* a0 <- call[j-1]'s sp
+                               (used to find end of call[j]'s frame) */
+    s32e    a1,  a13, -12   /* save a1 to call[j+1]'s stack frame */
+    s32e    a2,  a13,  -8   /* save a2 to call[j+1]'s stack frame */
+    s32e    a3,  a13,  -4   /* save a3 to call[j+1]'s stack frame */
+    s32e    a4,  a0,  -48   /* save a4 to end of call[j]'s stack frame */
+    s32e    a5,  a0,  -44   /* save a5 to end of call[j]'s stack frame */
+    s32e    a6,  a0,  -40   /* save a6 to end of call[j]'s stack frame */
+    s32e    a7,  a0,  -36   /* save a7 to end of call[j]'s stack frame */
+    s32e    a8,  a0,  -32   /* save a8 to end of call[j]'s stack frame */
+    s32e    a9,  a0,  -28   /* save a9 to end of call[j]'s stack frame */
+    s32e    a10, a0,  -24   /* save a10 to end of call[j]'s stack frame */
+    s32e    a11, a0,  -20   /* save a11 to end of call[j]'s stack frame */
+    rfwo                    /* rotates back to call[i] position */
+
+/*
+--------------------------------------------------------------------------------
+Window Underflow Exception for Call12
+
+Invoked by RETW returning from call[i+1] to call[i]
+where call[i]'s registers must be reloaded (not live in ARs);
+where call[i] had done a call12 to call[i+1].
+On entry here:
+        window rotated to call[i] start point;
+        a0-a11 are undefined, must be reloaded with call[i].reg[0..11];
+        a12-a15 must be preserved (they are call[i+1].reg[0..3]);
+        a13 is call[i+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org 0x140
+    .global _WindowUnderflow12
+_WindowUnderflow12:
+
+    l32e    a0,  a13, -16   /* restore a0 from call[i+1]'s stack frame */
+    l32e    a1,  a13, -12   /* restore a1 from call[i+1]'s stack frame */
+    l32e    a2,  a13,  -8   /* restore a2 from call[i+1]'s stack frame */
+    l32e    a11, a1,  -12   /* a11 <- call[i-1]'s sp
+                               (used to find end of call[i]'s frame) */
+    l32e    a3,  a13,  -4   /* restore a3 from call[i+1]'s stack frame */
+    l32e    a4,  a11, -48   /* restore a4 from end of call[i]'s stack frame */
+    l32e    a5,  a11, -44   /* restore a5 from end of call[i]'s stack frame */
+    l32e    a6,  a11, -40   /* restore a6 from end of call[i]'s stack frame */
+    l32e    a7,  a11, -36   /* restore a7 from end of call[i]'s stack frame */
+    l32e    a8,  a11, -32   /* restore a8 from end of call[i]'s stack frame */
+    l32e    a9,  a11, -28   /* restore a9 from end of call[i]'s stack frame */
+    l32e    a10, a11, -24   /* restore a10 from end of call[i]'s stack frame */
+    l32e    a11, a11, -20   /* restore a11 from end of call[i]'s stack frame */
+    rfwu
+
+#endif /* XCHAL_HAVE_WINDOWED */
+
+    .section    .UserEnter.text, "ax"
+    .global     call_user_start
+    .type       call_user_start,@function
+    .align      4
+    .literal_position
+
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/Makefile b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/Makefile
new file mode 100644
index 0000000..6a0d3b0
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/Makefile
@@ -0,0 +1,98 @@
+### Makefile to build the FreeRTOS library ###
+
+# Build target (options: sim, board)
+
+TARGET      = sim
+SMALL       =
+
+# Tools
+
+CC          = xt-xcc
+AS          = xt-xcc
+AR          = xt-ar
+XT_CORE     = $(patsubst %-params,%,$(notdir $(shell xt-xcc --show-config=core)))
+CONFIGDIR   = $(shell xt-xcc --show-config=config)
+
+# For platform-specific commands
+
+include $(CONFIGDIR)/misc/hostenv.mk
+
+# Source code and build locations
+
+SRCROOT     = $(subst /,$(S),$(CURDIR))
+TSTROOT     = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..$(S)..$(S)..$(S)demos$(S)cadence$(S)sim$(SMALL))
+BLDROOT     = $(TSTROOT)$(S)build
+BLDDIR      = $(BLDROOT)$(S)$(XT_CORE)
+
+FR_SRCDIR   = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..)
+FR_SRCDIR2  = $(FR_SRCDIR)$(S)portable$(S)MemMang
+XT_SRCDIR   = $(SRCROOT)
+
+vpath %.c $(FR_SRCDIR) $(FR_SRCDIR2) $(XT_SRCDIR)
+vpath %.S $(XT_SRCDIR)
+
+# File lists
+
+FR_C_FILES  = $(notdir $(wildcard $(FR_SRCDIR)/*.c)) $(notdir $(wildcard $(FR_SRCDIR2)/*.c))
+XT_C_FILES  = $(notdir $(wildcard $(XT_SRCDIR)/*.c))
+XT_S_FILES  = $(notdir $(wildcard $(XT_SRCDIR)/*.S))
+
+# List of all .o files that will go into the library
+
+LIB_C_O     = $(patsubst %.c,%.o,$(XT_C_FILES) $(FR_C_FILES))
+LIB_S_O     = $(patsubst %.S,%.o,$(XT_S_FILES))
+LIB_O_LIST  = $(addprefix $(BLDDIR)/,$(LIB_C_O) $(LIB_S_O))
+
+# Output files
+
+OSLIB       = $(BLDDIR)$(S)libfreertos.a
+
+# Build options
+
+ifeq ($(TARGET),sim)
+DFLAGS      = -DXT_SIMULATOR
+endif
+ifeq ($(TARGET),board)
+DFLAGS      = -DXT_BOARD
+endif
+
+IFLAGS      = \
+  -I$(FR_SRCDIR)$(S)..$(S)include -I$(FR_SRCDIR)$(S)..$(S)include$(S)private \
+  -I$(XT_SRCDIR) -I$(TSTROOT)$(S)common$(S)config_files -I$(BLDDIR)
+
+CFLAGS      = -O2 -g
+CCFLAGS     = $(CFLAGS) -Wall -mno-coproc -mlongcalls -ffunction-sections -mno-l32r-flix $(DFLAGS)
+ASFLAGS     = $(CCFLAGS)
+
+# Include dependency rules (generated using -MD)
+
+-include $(wildcard $(BLDDIR)/*.d)
+
+# Targets
+
+all : mkdir $(OSLIB)
+
+mkdir : $(BLDDIR)/.mkdir
+
+$(BLDDIR)/.mkdir :
+	@$(MKPATH) $(BLDDIR)
+	@echo "" > $@
+	-$(CP) $(CONFIGDIR)/xtensa-elf/include/sys/reent.h $(BLDDIR)/reent.h
+
+$(OSLIB) : $(LIB_O_LIST)
+	$(AR) -rs $@ $^
+
+$(BLDDIR)/%.o : %.c
+	$(CC) $(CCFLAGS) $(IFLAGS) -MD -MF $(subst .o,.d,$@) -c -o $@ $<
+
+$(BLDDIR)/%.o : %.S
+	$(CC) $(ASFLAGS) $(IFLAGS) -MD -MF $(subst .o,.d,$@) -c -o $@ $<
+
+clean :
+	$(RM_R) $(BLDDIR)
+
+clean_all :
+	$(RM_R) $(BLDROOT)
+
+.PHONY : all mkdir clean clean_all
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/port.c
new file mode 100644
index 0000000..e1d9651
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/port.c
@@ -0,0 +1,230 @@
+
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <stdlib.h>
+#include <xtensa/config/core.h>
+
+#include "xtensa_rtos.h"
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+
+/* Defined in portasm.h */
+extern void _frxt_tick_timer_init(void);
+
+/* Defined in xtensa_context.S */
+extern void _xt_coproc_init(void);
+
+
+/*-----------------------------------------------------------*/
+
+/* We require the address of the pxCurrentTCB variable, but don't want to know
+any details of its type. */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+unsigned port_xSchedulerRunning = 0; // Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting
+unsigned port_interruptNesting = 0;  // Interrupt nesting level
+
+/*-----------------------------------------------------------*/
+
+// User exception dispatcher when exiting
+void _xt_user_exit(void);
+
+/* 
+ * Stack initialization
+ */
+#if portUSING_MPU_WRAPPERS
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
+#else
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+#endif
+{
+    StackType_t * sp, * tp;
+    XtExcFrame * frame;
+
+    #if XCHAL_CP_NUM > 0
+        uint32_t * p;
+    #endif
+
+    /* Create interrupt stack frame aligned to 16 byte boundary */
+    sp = ( StackType_t * ) ( ( ( UBaseType_t ) pxTopOfStack - XT_CP_SIZE - XT_STK_FRMSZ ) & ~0xf );
+
+    /* Clear the entire frame (do not use memset() because we don't depend on C library) */
+    for( tp = sp; tp <= pxTopOfStack; ++tp )
+    {
+        *tp = 0;
+    }
+
+    frame = ( XtExcFrame * ) sp;
+
+    /* Explicitly initialize certain saved registers */
+    frame->pc = ( UBaseType_t ) pxCode;             /* task entrypoint                */
+    frame->a0 = 0;                                  /* to terminate GDB backtrace     */
+    frame->a1 = ( UBaseType_t ) sp + XT_STK_FRMSZ;  /* physical top of stack frame    */
+    frame->exit = ( UBaseType_t ) _xt_user_exit;    /* user exception exit dispatcher */
+
+    /* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */
+    /* Also set entry point argument parameter. */
+    #ifdef __XTENSA_CALL0_ABI__
+        frame->a2 = ( UBaseType_t ) pvParameters;
+        frame->ps = PS_UM | PS_EXCM;
+    #else
+        /* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */
+        frame->a6 = ( UBaseType_t ) pvParameters;
+        frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC( 1 );
+    #endif
+
+    #ifdef XT_USE_SWPRI
+        /* Set the initial virtual priority mask value to all 1's. */
+        frame->vpri = 0xFFFFFFFF;
+    #endif
+
+    #if XCHAL_CP_NUM > 0
+        /* Init the coprocessor save area (see xtensa_context.h) */
+
+        /* No access to TCB here, so derive indirectly. Stack growth is top to bottom.
+         * //p = (uint32_t *) xMPUSettings->coproc_area;
+         */
+        p = ( uint32_t * ) ( ( ( uint32_t ) pxTopOfStack - XT_CP_SIZE ) & ~0xf );
+        configASSERT( ( uint32_t ) p >= frame->a1 );
+        p[ 0 ] = 0;
+        p[ 1 ] = 0;
+        p[ 2 ] = ( ( ( uint32_t ) p ) + 12 + XCHAL_TOTAL_SA_ALIGN - 1 ) & -XCHAL_TOTAL_SA_ALIGN;
+    #endif
+
+    return sp;
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* It is unlikely that the Xtensa port will get stopped.  If required simply
+	disable the tick interrupt here. */
+}
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	// Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored
+
+	#if XCHAL_CP_NUM > 0
+	/* Initialize co-processor management for tasks. Leave CPENABLE alone. */
+	_xt_coproc_init();
+	#endif
+
+	/* Init the tick divisor value */
+	_xt_tick_divisor_init();
+
+	/* Setup the hardware to generate the tick. */
+	_frxt_tick_timer_init();
+
+	#if XT_USE_THREAD_SAFE_CLIB
+	// Init C library
+	vPortClibInit();
+	#endif
+
+	port_xSchedulerRunning = 1;
+
+	// Cannot be directly called from C; never returns
+	__asm__ volatile ("call0    _frxt_dispatch\n");
+
+	/* Should not get here. */
+	return pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortSysTickHandler( void )
+{
+	BaseType_t ret;
+	uint32_t interruptMask;
+
+	portbenchmarkIntLatency();
+
+	/* Interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY must be
+	 * disabled before calling xTaskIncrementTick as it access the
+	 * kernel lists. */
+	interruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		ret = xTaskIncrementTick();
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( interruptMask );
+
+	portYIELD_FROM_ISR( ret );
+
+	return ret;
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area.
+ */
+#if portUSING_MPU_WRAPPERS
+void vPortStoreTaskMPUSettings( xMPU_SETTINGS * xMPUSettings,
+                                const struct xMEMORY_REGION * const xRegions,
+                                StackType_t * pxBottomOfStack,
+                                uint32_t ulStackDepth )
+{
+    #if XCHAL_CP_NUM > 0
+        xMPUSettings->coproc_area = ( StackType_t * ) ( ( uint32_t ) ( pxBottomOfStack + ulStackDepth - 1 ));
+        xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) xMPUSettings->coproc_area ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+        xMPUSettings->coproc_area = ( StackType_t * ) ( ( ( uint32_t ) xMPUSettings->coproc_area - XT_CP_SIZE ) & ~0xf );
+
+        /* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
+         * clear the stack area after we return. This is done in pxPortInitialiseStack().
+         */
+    #endif
+}
+#endif /* if portUSING_MPU_WRAPPERS */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portasm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portasm.S
new file mode 100644
index 0000000..11017f3
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portasm.S
@@ -0,0 +1,596 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "xtensa_rtos.h"
+
+#define TOPOFSTACK_OFFS                 0x00    /* StackType_t *pxTopOfStack */
+#define CP_TOPOFSTACK_OFFS              0x04    /* xMPU_SETTINGS.coproc_area */
+
+.extern pxCurrentTCB
+
+
+/*
+*******************************************************************************
+* Interrupt stack. The size of the interrupt stack is determined by the config
+* parameter "configISR_STACK_SIZE" in FreeRTOSConfig.h
+*******************************************************************************
+*/
+    .data
+    .align      16
+    .global     port_IntStack
+port_IntStack:
+    .space      configISR_STACK_SIZE
+port_IntStackTop:
+    .word       0
+port_switch_flag:
+    .word       0
+
+    .text
+/*
+*******************************************************************************
+* _frxt_setup_switch
+* void _frxt_setup_switch(void);
+* 
+* Sets an internal flag indicating that a task switch is required on return
+* from interrupt handling.
+* 
+*******************************************************************************
+*/
+    .global     _frxt_setup_switch
+    .type       _frxt_setup_switch,@function
+    .align      4
+_frxt_setup_switch:
+
+    ENTRY(16)
+
+    movi    a2, port_switch_flag
+    movi    a3, 1
+    s32i    a3, a2, 0
+
+    RET(16)
+
+/*
+*******************************************************************************
+*                                            _frxt_int_enter
+*                                       void _frxt_int_enter(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for
+* freeRTOS. Saves the rest of the interrupt context (not already saved).
+* May only be called from assembly code by the 'call0' instruction, with
+* interrupts disabled.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+*******************************************************************************
+*/
+    .globl  _frxt_int_enter
+    .type   _frxt_int_enter,@function
+    .align  4
+_frxt_int_enter:
+
+    /* Save a12-13 in the stack frame as required by _xt_context_save. */
+    s32i    a12, a1, XT_STK_A12
+    s32i    a13, a1, XT_STK_A13
+
+    /* Save return address in a safe place (free a0). */
+    mov     a12, a0
+
+    /* Save the rest of the interrupted context (preserves A12-13). */
+    call0   _xt_context_save
+
+    /*
+    Save interrupted task's SP in TCB only if not nesting.
+    Manage nesting directly rather than call the generic IntEnter()
+    (in windowed ABI we can't call a C function here anyway because PS.EXCM is still set).
+    */
+    movi    a2,  port_xSchedulerRunning
+    movi    a3,  port_interruptNesting
+    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
+    beqz    a2,  1f                     /* scheduler not running, no tasks */
+    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
+    addi    a2,  a2, 1                  /* increment nesting count         */
+    s32i    a2,  a3, 0                  /* save nesting count              */
+    bnei    a2,  1, .Lnested            /* !=0 before incr, so nested      */
+
+    movi    a2,  pxCurrentTCB
+    l32i    a2,  a2, 0                  /* a2 = current TCB                */
+    beqz    a2,  1f
+    s32i    a1,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP */
+    movi    a1,  port_IntStackTop       /* a1 = top of intr stack          */
+
+.Lnested:
+1:
+    mov     a0,  a12                    /* restore return addr and return  */
+    ret
+
+/*
+*******************************************************************************
+*                                            _frxt_int_exit
+*                                       void _frxt_int_exit(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for
+* FreeRTOS. If required, calls vPortYieldFromInt() to perform task context
+* switching, restore the (possibly) new task's context, and return to the
+* exit dispatcher saved in the task's stack frame at XT_STK_EXIT.
+* May only be called from assembly code by the 'call0' instruction. Does not
+* return to caller.
+* See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+*******************************************************************************
+*/
+    .globl  _frxt_int_exit
+    .type   _frxt_int_exit,@function
+    .align  4
+_frxt_int_exit:
+
+    movi    a2,  port_xSchedulerRunning
+    movi    a3,  port_interruptNesting
+    rsil    a0,  XCHAL_EXCM_LEVEL       /* lock out interrupts             */
+    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
+    beqz    a2,  .Lnoswitch             /* scheduler not running, no tasks */
+    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
+    addi    a2,  a2, -1                 /* decrement nesting count         */
+    s32i    a2,  a3, 0                  /* save nesting count              */
+    bnez    a2,  .Lnesting              /* !=0 after decr so still nested  */
+
+    movi    a2,  pxCurrentTCB
+    l32i    a2,  a2, 0                  /* a2 = current TCB                */
+    beqz    a2,  1f                     /* no task ? go to dispatcher      */
+    l32i    a1,  a2, TOPOFSTACK_OFFS    /* SP = pxCurrentTCB->pxTopOfStack */
+
+    movi    a2,  port_switch_flag       /* address of switch flag          */
+    l32i    a3,  a2, 0                  /* a3 = port_switch_flag           */
+    beqz    a3,  .Lnoswitch             /* flag = 0 means no switch reqd   */
+    movi    a3,  0
+    s32i    a3,  a2, 0                  /* zero out the flag for next time */
+
+1:
+    /*
+    Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption.
+    However a12-13 were already saved by _frxt_int_enter().
+    */
+    #ifdef __XTENSA_CALL0_ABI__
+    s32i    a14, a1, XT_STK_A14
+    s32i    a15, a1, XT_STK_A15
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   vPortYieldFromInt       /* call dispatch inside the function; never returns */
+    #else
+    call4   vPortYieldFromInt       /* this one returns */
+    call0   _frxt_dispatch          /* tail-call dispatcher */
+    /* Never returns here. */
+    #endif
+
+.Lnoswitch:
+    /*
+    If we came here then about to resume the interrupted task.
+    */
+
+.Lnesting:
+    /*
+    We come here only if there was no context switch, that is if this
+    is a nested interrupt, or the interrupted task was not preempted.
+    In either case there's no need to load the SP.
+    */
+
+    /* Restore full context from interrupt stack frame */
+    call0   _xt_context_restore
+
+    /*
+    Must return via the exit dispatcher corresponding to the entrypoint from which
+    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
+    stack frame is deallocated in the exit dispatcher.
+    */
+    l32i    a0,  a1, XT_STK_EXIT
+    ret
+
+
+/*
+**********************************************************************************************************
+*                                           _frxt_timer_int
+*                                      void _frxt_timer_int(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS.
+* Called every timer interrupt.
+* Manages the tick timer and calls xPortSysTickHandler() every tick.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+* Callable from C (obeys ABI conventions). Implemented in assmebly code for performance.
+*
+**********************************************************************************************************
+*/
+    .globl  _frxt_timer_int
+    .type   _frxt_timer_int,@function
+    .align  4
+_frxt_timer_int:
+
+    /*
+    Xtensa timers work by comparing a cycle counter with a preset value.  Once the match occurs
+    an interrupt is generated, and the handler has to set a new cycle count into the comparator.
+    To avoid clock drift due to interrupt latency, the new cycle count is computed from the old,
+    not the time the interrupt was serviced. However if a timer interrupt is ever serviced more
+    than one tick late, it is necessary to process multiple ticks until the new cycle count is
+    in the future, otherwise the next timer interrupt would not occur until after the cycle
+    counter had wrapped (2^32 cycles later).
+
+    do {
+        ticks++;
+        old_ccompare = read_ccompare_i();
+        write_ccompare_i( old_ccompare + divisor );
+        service one tick;
+        diff = read_ccount() - old_ccompare;
+    } while ( diff > divisor );
+    */
+
+    ENTRY(16)
+
+.L_xt_timer_int_catchup:
+
+    /* Update the timer comparator for the next tick. */
+    #ifdef XT_CLOCK_FREQ
+    movi    a2, XT_TICK_DIVISOR         /* a2 = comparator increment          */
+    #else
+    movi    a3, _xt_tick_divisor
+    l32i    a2, a3, 0                   /* a2 = comparator increment          */
+    #endif
+    rsr     a3, XT_CCOMPARE             /* a3 = old comparator value          */
+    add     a4, a3, a2                  /* a4 = new comparator value          */
+    wsr     a4, XT_CCOMPARE             /* update comp. and clear interrupt   */
+    esync
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Preserve a2 and a3 across C calls. */
+    s32i    a2, sp, 4
+    s32i    a3, sp, 8
+    #endif
+
+    /* Call the FreeRTOS tick handler (see port.c). */
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   xPortSysTickHandler
+    #else
+    call4   xPortSysTickHandler
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Restore a2 and a3. */
+    l32i    a2, sp, 4
+    l32i    a3, sp, 8
+    #endif
+
+    /* Check if we need to process more ticks to catch up. */
+    esync                               /* ensure comparator update complete  */
+    rsr     a4, CCOUNT                  /* a4 = cycle count                   */
+    sub     a4, a4, a3                  /* diff = ccount - old comparator     */
+    blt     a2, a4, .L_xt_timer_int_catchup  /* repeat while diff > divisor */
+
+    RET(16)
+
+    /*
+**********************************************************************************************************
+*                                           _frxt_tick_timer_init
+*                                      void _frxt_tick_timer_init(void)
+*
+* Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called).
+* Callable from C (obeys ABI conventions on entry).
+*
+**********************************************************************************************************
+*/
+    .globl  _frxt_tick_timer_init
+    .type   _frxt_tick_timer_init,@function
+    .align  4
+_frxt_tick_timer_init:
+
+    ENTRY(16)
+
+    /* Set up the periodic tick timer (assume enough time to complete init). */
+    #ifdef XT_CLOCK_FREQ
+    movi    a3, XT_TICK_DIVISOR
+    #else
+    movi    a2, _xt_tick_divisor
+    l32i    a3, a2, 0
+    #endif
+    rsr     a2, CCOUNT              /* current cycle count */
+    add     a2, a2, a3              /* time of first timer interrupt */
+    wsr     a2, XT_CCOMPARE         /* set the comparator */
+
+    /*
+    Enable the timer interrupt at the device level. Don't write directly
+    to the INTENABLE register because it may be virtualized.
+    */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a2, XT_TIMER_INTEN
+    call0   xt_ints_on
+    #else
+    movi    a6, XT_TIMER_INTEN
+    call4   xt_ints_on
+    #endif
+
+    RET(16)
+
+/*
+**********************************************************************************************************
+*                                    DISPATCH THE HIGH READY TASK
+*                                     void _frxt_dispatch(void)
+*
+* Switch context to the highest priority ready task, restore its state and dispatch control to it.
+*
+* This is a common dispatcher that acts as a shared exit path for all the context switch functions
+* including vPortYield() and vPortYieldFromInt(), all of which tail-call this dispatcher
+* (for windowed ABI vPortYieldFromInt() calls it indirectly via _frxt_int_exit() ).
+*
+* The Xtensa port uses different stack frames for solicited and unsolicited task suspension (see
+* comments on stack frames in xtensa_context.h). This function restores the state accordingly.
+* If restoring a task that solicited entry, restores the minimal state and leaves CPENABLE clear.
+* If restoring a task that was preempted, restores all state including the task's CPENABLE.
+*
+* Entry:
+*   pxCurrentTCB  points to the TCB of the task to suspend,
+*   Because it is tail-called without a true function entrypoint, it needs no 'entry' instruction.
+*
+* Exit:
+*   If incoming task called vPortYield() (solicited), this function returns as if from vPortYield().
+*   If incoming task was preempted by an interrupt, this function jumps to exit dispatcher.
+*
+**********************************************************************************************************
+*/
+    .globl  _frxt_dispatch
+    .type   _frxt_dispatch,@function
+    .align  4
+_frxt_dispatch:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    call0   vTaskSwitchContext  // Get next TCB to resume
+    movi    a2, pxCurrentTCB
+    #else
+    movi    a2, pxCurrentTCB
+    call4   vTaskSwitchContext  // Get next TCB to resume
+    #endif
+    l32i    a3,  a2, 0
+    l32i    sp,  a3, TOPOFSTACK_OFFS     /* SP = next_TCB->pxTopOfStack;  */
+    s32i    a3,  a2, 0
+
+    /* Determine the type of stack frame. */
+    l32i    a2,  sp, XT_STK_EXIT        /* exit dispatcher or solicited flag */
+    bnez    a2,  .L_frxt_dispatch_stk
+
+.L_frxt_dispatch_sol:
+
+    /* Solicited stack frame. Restore minimal context and return from vPortYield(). */
+    l32i    a3,  sp, XT_SOL_PS
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a12, sp, XT_SOL_A12
+    l32i    a13, sp, XT_SOL_A13
+    l32i    a14, sp, XT_SOL_A14
+    l32i    a15, sp, XT_SOL_A15
+    #endif
+    l32i    a0,  sp, XT_SOL_PC
+    #if XCHAL_CP_NUM > 0
+    /* Ensure wsr.CPENABLE is complete (should be, it was cleared on entry). */
+    rsync
+    #endif
+    /* As soons as PS is restored, interrupts can happen. No need to sync PS. */
+    wsr     a3,  PS
+    #ifdef __XTENSA_CALL0_ABI__
+    addi    sp,  sp, XT_SOL_FRMSZ
+    ret
+    #else
+    retw
+    #endif
+
+.L_frxt_dispatch_stk:
+
+    #if XCHAL_CP_NUM > 0
+    /* Restore CPENABLE from task's co-processor save area. */
+    movi    a3, pxCurrentTCB            /* cp_state =                       */
+    l32i    a3, a3, 0
+    l32i    a2, a3, CP_TOPOFSTACK_OFFS     /* StackType_t                       *pxStack; */
+    l16ui    a3, a2, XT_CPENABLE         /* CPENABLE = cp_state->cpenable;   */
+    wsr     a3, CPENABLE
+    #endif
+
+    /* Interrupt stack frame. Restore full context and return to exit dispatcher. */
+    call0   _xt_context_restore
+
+    /* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a14, sp, XT_STK_A14
+    l32i    a15, sp, XT_STK_A15
+    #endif
+
+    #if XCHAL_CP_NUM > 0
+    /* Ensure wsr.CPENABLE has completed. */
+    rsync
+    #endif
+
+    /*
+    Must return via the exit dispatcher corresponding to the entrypoint from which
+    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
+    stack frame is deallocated in the exit dispatcher.
+    */
+    l32i    a0, sp, XT_STK_EXIT
+    ret
+
+
+/*
+**********************************************************************************************************
+*                            PERFORM A SOLICTED CONTEXT SWITCH (from a task)
+*                                        void vPortYield(void)
+*
+* This function saves the minimal state needed for a solicited task suspension, clears CPENABLE,
+* then tail-calls the dispatcher _frxt_dispatch() to perform the actual context switch
+*
+* At Entry:
+*   pxCurrentTCB  points to the TCB of the task to suspend
+*   Callable from C (obeys ABI conventions on entry).
+*
+* Does not return to caller.
+*
+**********************************************************************************************************
+*/
+    .globl  vPortYield
+    .type   vPortYield,@function
+    .align  4
+vPortYield:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    addi    sp,  sp, -XT_SOL_FRMSZ
+    #else
+    entry   sp,  XT_SOL_FRMSZ
+    #endif
+
+    rsr     a2,  PS
+    s32i    a0,  sp, XT_SOL_PC
+    s32i    a2,  sp, XT_SOL_PS
+    #ifdef __XTENSA_CALL0_ABI__
+    s32i    a12, sp, XT_SOL_A12         /* save callee-saved registers      */
+    s32i    a13, sp, XT_SOL_A13
+    s32i    a14, sp, XT_SOL_A14
+    s32i    a15, sp, XT_SOL_A15
+    #else
+    /* Spill register windows. Calling xthal_window_spill() causes extra    */
+    /* spills and reloads, so we will set things up to call the _nw version */
+    /* instead to save cycles.                                              */
+    movi    a6,  ~(PS_WOE_MASK|PS_INTLEVEL_MASK)  /* spills a4-a7 if needed */
+    and     a2,  a2, a6                           /* clear WOE, INTLEVEL    */
+    addi    a2,  a2, XCHAL_EXCM_LEVEL             /* set INTLEVEL           */
+    wsr     a2,  PS
+    rsync
+    call0   xthal_window_spill_nw
+    l32i    a2,  sp, XT_SOL_PS                    /* restore PS             */
+    wsr     a2,  PS
+    #endif
+
+    rsil    a2,  XCHAL_EXCM_LEVEL       /* disable low/med interrupts       */
+
+    #if XCHAL_CP_NUM > 0
+    /* Save coprocessor callee-saved state (if any). At this point CPENABLE */
+    /* should still reflect which CPs were in use (enabled).                */
+    call0   _xt_coproc_savecs
+    #endif
+
+    movi    a2,  pxCurrentTCB
+    movi    a3,  0
+    l32i    a2,  a2, 0                  /* a2 = pxCurrentTCB                */
+    s32i    a3,  sp, XT_SOL_EXIT        /* 0 to flag as solicited frame     */
+    s32i    sp,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP  */
+
+    #if XCHAL_CP_NUM > 0
+    /* Clear CPENABLE, also in task's co-processor state save area. */
+    l32i    a2,  a2, CP_TOPOFSTACK_OFFS /* a2 = pxCurrentTCB->cp_state      */
+    movi    a3,  0
+    wsr     a3,  CPENABLE
+    beqz    a2,  1f
+    s16i     a3,  a2, XT_CPENABLE        /* clear saved cpenable             */
+1:
+    #endif
+
+    /* Tail-call dispatcher. */
+    call0   _frxt_dispatch
+    /* Never reaches here. */
+
+
+/*
+**********************************************************************************************************
+*                         PERFORM AN UNSOLICITED CONTEXT SWITCH (from an interrupt)
+*                                        void vPortYieldFromInt(void)
+*
+* This calls the context switch hook (removed), saves and clears CPENABLE, then tail-calls the dispatcher
+* _frxt_dispatch() to perform the actual context switch.
+*
+* At Entry:
+*   Interrupted task context has been saved in an interrupt stack frame at pxCurrentTCB->pxTopOfStack.
+*   pxCurrentTCB  points to the TCB of the task to suspend,
+*   Callable from C (obeys ABI conventions on entry).
+*
+* At Exit:
+*   Windowed ABI defers the actual context switch until the stack is unwound to interrupt entry.
+*   Call0 ABI tail-calls the dispatcher directly (no need to unwind) so does not return to caller.
+*
+**********************************************************************************************************
+*/
+    .globl  vPortYieldFromInt
+    .type   vPortYieldFromInt,@function
+    .align  4
+vPortYieldFromInt:
+
+    ENTRY(16)
+
+    #if XCHAL_CP_NUM > 0
+    /* Save CPENABLE in task's co-processor save area, and clear CPENABLE.  */
+    movi    a3, pxCurrentTCB            /* cp_state =                       */
+    l32i    a3, a3, 0
+    l32i    a2, a3, CP_TOPOFSTACK_OFFS
+
+    rsr     a3, CPENABLE
+    s16i     a3, a2, XT_CPENABLE         /* cp_state->cpenable = CPENABLE;   */
+    movi    a3, 0
+    wsr     a3, CPENABLE                /* disable all co-processors        */
+    #endif
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /* Tail-call dispatcher. */
+    call0   _frxt_dispatch
+    /* Never reaches here. */
+    #else
+    RET(16)
+    #endif
+
+/*
+**********************************************************************************************************
+*                                        _frxt_task_coproc_state
+*                                   void _frxt_task_coproc_state(void)
+*
+* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function for FreeRTOS.
+*
+* May only be called when a task is running, not within an interrupt handler (returns 0 in that case).
+* May only be called from assembly code by the 'call0' instruction. Does NOT obey ABI conventions.
+* Returns in A15 a pointer to the base of the co-processor state save area for the current task.
+* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
+*
+**********************************************************************************************************
+*/
+#if XCHAL_CP_NUM > 0
+
+    .globl  _frxt_task_coproc_state
+    .type   _frxt_task_coproc_state,@function
+    .align  4
+_frxt_task_coproc_state:
+
+    movi    a15, port_xSchedulerRunning /* if (port_xSchedulerRunning              */
+    l32i    a15, a15, 0
+    beqz    a15, 1f
+    movi    a15, port_interruptNesting  /* && port_interruptNesting == 0           */
+    l32i    a15, a15, 0
+    bnez    a15, 1f
+    movi    a15, pxCurrentTCB
+    l32i    a15, a15, 0                 /* && pxCurrentTCB != 0) {                 */
+    beqz    a15, 2f
+    l32i    a15, a15, CP_TOPOFSTACK_OFFS
+    ret
+
+1:  movi    a15, 0
+2:  ret
+
+#endif /* XCHAL_CP_NUM > 0 */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portbenchmark.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
new file mode 100644
index 0000000..3df6103
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
@@ -0,0 +1,46 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * This utility helps benchmarking interrupt latency and context switches.
+ * In order to enable it, set configBENCHMARK to 1 in FreeRTOSConfig.h.
+ * You will also need to download the FreeRTOS_trace patch that contains
+ * portbenchmark.c and the complete version of portbenchmark.h
+ */
+
+#ifndef PORTBENCHMARK_H
+#define PORTBENCHMARK_H
+
+#if configBENCHMARK
+    #error "You need to download the FreeRTOS_trace patch that overwrites this file"
+#endif
+
+#define portbenchmarkINTERRUPT_DISABLE()
+#define portbenchmarkINTERRUPT_RESTORE(newstate)
+#define portbenchmarkIntLatency()
+#define portbenchmarkIntWait()
+#define portbenchmarkReset()
+#define portbenchmarkPrint()
+
+#endif /* PORTBENCHMARK */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portclib.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portclib.c
new file mode 100644
index 0000000..7268923
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portclib.c
@@ -0,0 +1,225 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "FreeRTOS.h"
+
+#if XT_USE_THREAD_SAFE_CLIB
+
+#if XSHAL_CLIB == XTHAL_CLIB_XCLIB
+
+#include <errno.h>
+#include <sys/reent.h>
+
+#include "semphr.h"
+
+typedef SemaphoreHandle_t       _Rmtx;
+
+//-----------------------------------------------------------------------------
+//  Override this and set to nonzero to enable locking.
+//-----------------------------------------------------------------------------
+int32_t _xclib_use_mt = 1;
+
+
+//-----------------------------------------------------------------------------
+//  Init lock.
+//-----------------------------------------------------------------------------
+void
+_Mtxinit(_Rmtx * mtx)
+{
+    *mtx = xSemaphoreCreateRecursiveMutex();
+}
+
+//-----------------------------------------------------------------------------
+//  Destroy lock.
+//-----------------------------------------------------------------------------
+void
+_Mtxdst(_Rmtx * mtx)
+{
+    if ((mtx != NULL) && (*mtx != NULL)) {
+        vSemaphoreDelete(*mtx);
+    }
+}
+
+//-----------------------------------------------------------------------------
+//  Lock.
+//-----------------------------------------------------------------------------
+void
+_Mtxlock(_Rmtx * mtx)
+{
+    if ((mtx != NULL) && (*mtx != NULL)) {
+        xSemaphoreTakeRecursive(*mtx, portMAX_DELAY);
+    }
+}
+
+//-----------------------------------------------------------------------------
+//  Unlock.
+//-----------------------------------------------------------------------------
+void
+_Mtxunlock(_Rmtx * mtx)
+{
+    if ((mtx != NULL) && (*mtx != NULL)) {
+        xSemaphoreGiveRecursive(*mtx);
+    }
+}
+
+//-----------------------------------------------------------------------------
+//  Called by malloc() to allocate blocks of memory from the heap.
+//-----------------------------------------------------------------------------
+void *
+_sbrk_r (struct _reent * reent, int32_t incr)
+{
+    extern char _end;
+    extern char _heap_sentry;
+    static char * _heap_sentry_ptr = &_heap_sentry;
+    static char * heap_ptr;
+    char * base;
+
+    if (!heap_ptr)
+        heap_ptr = (char *) &_end;
+
+    base = heap_ptr;
+    if (heap_ptr + incr >= _heap_sentry_ptr) {
+        reent->_errno = ENOMEM;
+        return (char *) -1;
+    }
+
+    heap_ptr += incr;
+    return base;
+}
+
+//-----------------------------------------------------------------------------
+//  Global initialization for C library.
+//-----------------------------------------------------------------------------
+void
+vPortClibInit(void)
+{
+}
+
+//-----------------------------------------------------------------------------
+//  Per-thread cleanup stub provided for linking, does nothing.
+//-----------------------------------------------------------------------------
+void
+_reclaim_reent(void * ptr)
+{
+}
+
+#endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */
+
+#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+
+#include <errno.h>
+#include <malloc.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include "semphr.h"
+
+static SemaphoreHandle_t xClibMutex;
+static uint32_t  ulClibInitDone = 0;
+
+//-----------------------------------------------------------------------------
+//  Get C library lock.
+//-----------------------------------------------------------------------------
+void
+__malloc_lock(struct _reent * ptr)
+{
+    if (!ulClibInitDone)
+        return;
+
+    xSemaphoreTakeRecursive(xClibMutex, portMAX_DELAY);
+}
+
+//-----------------------------------------------------------------------------
+//  Release C library lock.
+//-----------------------------------------------------------------------------
+void
+__malloc_unlock(struct _reent * ptr)
+{
+    if (!ulClibInitDone)
+        return;
+
+    xSemaphoreGiveRecursive(xClibMutex);
+}
+
+//-----------------------------------------------------------------------------
+//  Lock for environment. Since we have only one global lock we can just call
+//  the malloc() lock function.
+//-----------------------------------------------------------------------------
+void
+__env_lock(struct _reent * ptr)
+{
+    __malloc_lock(ptr);
+}
+
+
+//-----------------------------------------------------------------------------
+//  Unlock environment.
+//-----------------------------------------------------------------------------
+void
+__env_unlock(struct _reent * ptr)
+{
+    __malloc_unlock(ptr);
+}
+
+//-----------------------------------------------------------------------------
+//  Called by malloc() to allocate blocks of memory from the heap.
+//-----------------------------------------------------------------------------
+void *
+_sbrk_r (struct _reent * reent, int32_t incr)
+{
+    extern char _end;
+    extern char _heap_sentry;
+    static char * _heap_sentry_ptr = &_heap_sentry;
+    static char * heap_ptr;
+    char * base;
+
+    if (!heap_ptr)
+        heap_ptr = (char *) &_end;
+
+    base = heap_ptr;
+    if (heap_ptr + incr >= _heap_sentry_ptr) {
+        reent->_errno = ENOMEM;
+        return (char *) -1;
+    }
+
+    heap_ptr += incr;
+    return base;
+}
+
+//-----------------------------------------------------------------------------
+//  Global initialization for C library.
+//-----------------------------------------------------------------------------
+void
+vPortClibInit(void)
+{
+    configASSERT(!ulClibInitDone);
+
+    xClibMutex = xSemaphoreCreateRecursiveMutex();
+    ulClibInitDone  = 1;
+}
+
+#endif /* XSHAL_CLIB == XTHAL_CLIB_NEWLIB */
+
+#endif /* XT_USE_THREAD_SAFE_CLIB */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portmacro.h
new file mode 100644
index 0000000..6e1ea16
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portmacro.h
@@ -0,0 +1,236 @@
+
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software. If you wish to use our Amazon
+ * FreeRTOS name, please do so in a fair use way that does not cause confusion.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifndef __ASSEMBLER__
+
+#include <stdint.h>
+
+#include <xtensa/tie/xt_core.h>
+#include <xtensa/hal.h>
+#include <xtensa/config/core.h>
+#include <xtensa/config/system.h>	/* required for XSHAL_CLIB */
+#include <xtensa/xtruntime.h>
+
+//#include "xtensa_context.h"
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+
+#define portCHAR		int8_t
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		int32_t
+#define portSHORT		int16_t
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	int
+
+typedef portSTACK_TYPE			StackType_t;
+typedef portBASE_TYPE			BaseType_t;
+typedef unsigned portBASE_TYPE	UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+// portbenchmark
+#include "portbenchmark.h"
+
+/* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */
+// These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level.
+#define portDISABLE_INTERRUPTS()      do { XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); } while (0)
+#define portENABLE_INTERRUPTS()       do { portbenchmarkINTERRUPT_RESTORE(0); XTOS_SET_INTLEVEL(0); } while (0)
+
+// These can be nested
+#define portCRITICAL_NESTING_IN_TCB 1  // For now, let FreeRTOS' (tasks.c) manage critical nesting
+void vTaskEnterCritical(void);
+void vTaskExitCritical(void);
+#define portENTER_CRITICAL()        vTaskEnterCritical()
+#define portEXIT_CRITICAL()         vTaskExitCritical()
+
+// Cleaner and preferred solution allows nested interrupts disabling and restoring via local registers or stack.
+// They can be called from interrupts too.
+static inline unsigned portENTER_CRITICAL_NESTED() { unsigned state = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); return state; }
+#define portEXIT_CRITICAL_NESTED(state)   do { portbenchmarkINTERRUPT_RESTORE(state); XTOS_RESTORE_JUST_INTLEVEL(state); } while (0)
+
+// These FreeRTOS versions are similar to the nested versions above
+#define portSET_INTERRUPT_MASK_FROM_ISR()            portENTER_CRITICAL_NESTED()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(state)     portEXIT_CRITICAL_NESTED(state)
+
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			4
+#define portNOP()					XT_NOP()
+/*-----------------------------------------------------------*/
+
+/* Fine resolution time */
+#define portGET_RUN_TIME_COUNTER_VALUE()  xthal_get_ccount()
+
+/* Kernel utilities. */
+void vPortYield( void );
+void _frxt_setup_switch( void );
+#define portYIELD()       vPortYield()
+#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )	\
+	if ( ( xHigherPriorityTaskWoken ) != 0 ) {	\
+		_frxt_setup_switch();			\
+	}
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+// When coprocessors are defined, we to maintain a pointer to coprocessors area.
+// We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold:
+// MPU wrappers, coprocessor area pointer, trace code structure, and more if needed.
+// The field is normally used for memory protection. FreeRTOS should create another general purpose field.
+typedef struct {
+	#if XCHAL_CP_NUM > 0
+	volatile StackType_t* coproc_area; // Pointer to coprocessor save area; MUST BE FIRST
+	#endif
+
+	#if portUSING_MPU_WRAPPERS
+	// Define here mpu_settings, which is port dependent
+	int mpu_setting; // Just a dummy example here; MPU not ported to Xtensa yet
+	#endif
+
+	#if configUSE_TRACE_FACILITY_2
+	struct {
+		// Cf. porttraceStamp()
+		int taskstamp;        /* Stamp from inside task to see where we are */
+		int taskstampcount;   /* A counter usually incremented when we restart the task's loop */
+	} porttrace;
+	#endif
+} xMPU_SETTINGS;
+
+// Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS)
+#if (XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2) && !portUSING_MPU_WRAPPERS   // If MPU wrappers not used, we still need to allocate coproc area
+	#undef portUSING_MPU_WRAPPERS
+	#define portUSING_MPU_WRAPPERS 1   // Enable it to allocate coproc area
+	#define MPU_WRAPPERS_H             // Override mpu_wrapper.h to disable unwanted code
+	#define PRIVILEGED_FUNCTION
+	#define PRIVILEGED_DATA
+#endif
+
+// porttrace
+#if configUSE_TRACE_FACILITY_2
+#include "porttrace.h"
+#endif
+
+// configASSERT_2 if requested
+#if configASSERT_2
+#include <stdio.h>
+void exit(int);
+#define configASSERT( x )   if (!(x)) { porttracePrint(-1); printf("\nAssertion failed in %s:%d\n", __FILE__, __LINE__); exit(-1); }
+#endif
+
+
+/* C library support -- only XCLIB and NEWLIB are supported. */
+
+/* To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must be
+   defined to be > 0 somewhere above or on the command line. */
+
+#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_XCLIB)
+extern void vPortClibInit(void);
+
+// No cleanup necessary at this time.
+#define portCLEAN_UP_TCB(pxTCB)
+#endif // XCLIB support
+
+#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_NEWLIB)
+extern void vPortClibInit(void);
+
+// This C library cleanup is not currently done by FreeRTOS when deleting a task
+#include <stdio.h>
+#define portCLEAN_UP_TCB(pxTCB)   vPortCleanUpTcbClib(&((pxTCB)->xNewLib_reent))
+static inline void vPortCleanUpTcbClib(struct _reent *ptr)
+{
+    FILE * fp = &(ptr->__sf[0]);
+    int i;
+    for (i = 0; i < 3; ++i, ++fp) {
+        fp->_close = NULL;
+    }
+}
+#endif // NEWLIB support
+
+#endif // __ASSEMBLER__
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/porttrace.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/porttrace.h
new file mode 100644
index 0000000..498444b
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/porttrace.h
@@ -0,0 +1,44 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * This utility helps tracing the entering and exiting from tasks.
+ * It maintains a circular buffer of tasks in the order they execute,
+ * and their execution time. To enable it, set configUSE_TRACE_FACILITY_2
+ * to 1 in FreeRTOSConfig.h. You will also need to download the 
+ * FreeRTOS_trace patch that contains porttrace.c and the complete version
+ * of porttrace.h.
+ */
+
+#ifndef PORTTRACE_H
+#define PORTTRACE_H
+
+#if configUSE_TRACE_FACILITY_2
+    #error "You need to download the FreeRTOS_trace patch that overwrites this file"
+#endif
+
+#define porttracePrint(nelements)
+#define porttraceStamp(stamp, count_incr)
+
+#endif /* PORTTRACE_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt
new file mode 100644
index 0000000..247d731
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt
@@ -0,0 +1,764 @@
+    FreeRTOS Port for Xtensa Configurable and Diamond Processors
+    ============================================================
+
+                FreeRTOS Kernel Version 10.0.0
+
+
+Introduction
+------------
+
+This document describes the Xtensa port for FreeRTOS multitasking RTOS.
+For an introduction to FreeRTOS itself, please refer to FreeRTOS
+documentation.
+
+This port currently works with FreeRTOS kernel version 10.0.0.
+
+
+Xtensa Configuration Requirements and Restrictions
+--------------------------------------------------
+
+The Xtensa configurable architecture supports a vast space of processor
+features. This port supports all of them, including custom processor
+extensions defined in the TIE language, with certain minimum
+requirements. You must use Xtensa Tools to compile and link FreeRTOS and
+your application for your Xtensa configuration. The port uses the Xtensa
+Hardware Abstraction Layer (HAL) to adapt to your Xtensa configuration.
+NOTE: It may be possible to build and run this with the open-source 
+xtensa-linux tools provided you have the correct overlay for your Xtensa
+configuration. However, this has not been tested and is currently not
+supported by Cadence.
+
+This port includes optional reentrancy support for the 'newlib' and
+'xclib' C runtime libraries distributed with Xtensa Tools, providing
+thread-safety on a per task basis (for use in tasks only, not interrupt
+handlers).
+
+NOTE: At this time only 'newlib' and 'xclib' C libraries are supported
+for thread safety. The 'uclibc' library is not reentrant and does not
+provide thread safety at this time. However, if you are not concerned
+with reentrancy then you can use any of these libraries.
+
+This port also includes a simple example application that may run on
+a supported board or the Xtensa instruction set simulator (ISS). There
+are also a couple of test programs used in maintaining the port, which
+serve as additional examples.
+
+FreeRTOS for Xtensa configurable processors requires the following minimum 
+processor configuration options:
+- Timer interrupt option with at least one interruptible timer.
+- Interrupt option (implied by the timer interrupt option).
+- Exception Architecture 2 (XEA2). Please note that XEA1 is NOT supported.
+  All 'Diamond', 'Xtensa 6', 'Xtensa LX' and 'Xtensa LX2' processors and
+  most 'Xtensa T1050' processors are configured with XEA2.
+All Diamond processor cores meet these requirements and are supported.
+
+Minimal support for certain evaluation boards is provided via a board
+independent XTBSP API implemented by a board specific library distributed
+with the Xtensa Tools. This provides the board clock frequency and basic
+polled drivers for the display and console device. Note that XTBSP
+is not a tradtional RTOS "board support package" with RTOS specific
+interrupt-driven drivers - it is not specific to any RTOS. Note that
+FreeRTOS can run on any Xtensa or Diamond board without this board support
+(a "raw" platform), but you will have to provide the clock frequency
+and drivers for any on-board devices you want to use.
+
+
+Installation
+------------
+
+The Xtensa port of FreeRTOS is available at this location:
+
+    https://github.com/foss-xtensa/amazon-freertos
+
+This download includes the core FreeRTOS source and include files needed
+to build the port. You can also download the official release of FreeRTOS
+version 1.0.0 or later from this location:
+
+    https://github.com/aws/amazon-freertos
+
+The Xtensa port files are currently not included in the official package.
+
+All source is provided along with a Makefile that works for any host
+platform supported by Xtensa Tools (Windows, Linux). These instructions
+are written for Windows users, but can easily be understood and adapted
+to other host platforms.
+
+First install the FreeRTOS common package in a directory of your choosing.
+The structure of that package will look like this:
+
+<install directory>
+|-- demos
+|   `-- cadence
+|       `-- sim
+|           |-- common
+|           |   |-- application_code
+|           |   |   `-- cadence_code
+|           |   `-- config_files
+|           `-- xplorer
+`-- lib
+    |-- FreeRTOS
+    |   `-- portable
+    |       |-- Common
+    |       |-- MemMang
+    |       `-- XCC
+    |           `-- Xtensa
+    `-- include
+        `-- private
+
+The Xtensa Tools are available from Cadence as part of a processor
+license. Be sure you have installed the Xtensa Tools and your processor
+configuration.
+
+
+Building FreeRTOS for Xtensa
+----------------------------
+
+To build the FreeRTOS library and the example programs, go into the
+directory 'demos/cadence/sim' and use the makefile in that directory.
+"make all" will build all the examples. There is another makefile in
+the 'lib/FreeRTOS/portable/XCC/Xtensa' directory that builds just the
+FreeRTOS library.
+
+By default, you will build for the Xtensa instruction set simulator. If
+you have a supported emulation board, you can build to run on that. You
+can also build to run on a raw Xtensa core with no board support, a
+good starting point for supporting your own target platform. Cadence
+recommends doing functional development on the simulator because it
+is easier to debug with, then move to a board if/when you need to test
+hardware drivers or real-time performance.
+
+The provided makefile simplifies building FreeRTOS and the example
+for your Xtensa configuration and platform (ISS, board, etc.). There
+are detailed instructions in the comments at the top of the makefile.
+
+The makefiles work on Windows and Linux and support incremental builds.
+The build for each Xtensa configuration and target platform is placed in
+a subdirectory so several core and platform builds can co-exist even with
+incremental rebuilds. You may specify the root of the build area (if tou
+want it to be elsewhere than under the source tree) by defining BLDROOT
+either in the make command or your shell environment.
+
+
+Building the FreeRTOS Library
+-----------------------------
+
+First, be sure you have installed Xtensa Tools and your processor
+configuration, and be sure that Xtensa Tools are in your search path.
+You can use xt-make, which comes with the Xtensa Tools, to run the
+makefiles.
+
+Change directories to the Xtensa port directory:
+
+> cd lib/FreeRTOS/portable/XCC/Xtensa
+
+Now build the FreeRTOS RTOS as a library (libfreertos.a) as follows:
+
+> xt-make
+
+which by default builds for the simulator (TARGET=sim), or:
+
+> xt-make TARGET=board
+
+which builds for a supported board. Note that the board type does not
+need to be specified when building the FreeRTOS library.
+
+If you are building for an Xtensa processor configuration that is not the
+default you selected when you installed Xtensa Tools, you need to define the 
+environment variable XTENSA_CORE. If your configuration is not in the 
+default registry you selected when you installed Xtensa Tools, you also
+need to define the environment variable XTENSA_SYSTEM. See tools manuals.
+You can avoid defining these in your environment if you pass the variables 
+you need to redefine into xt-make as follows:
+
+> xt-make XTENSA_CORE=<your_config_name> XTENSA_SYSTEM=<your_registry> ...
+
+There are more details about build options in the comment in the Makefile.
+
+After the library has been built, you must link your application with this
+library in order to use FreeRTOS.
+
+
+Building the FreeRTOS Examples
+------------------------------
+
+The provided examples are designed to run on the Xtensa instruction set
+simulator (ISS) or a supported evaluation board programmed with your
+Xtensa processor configuration.
+
+To build the examples for the default platform (simulator):
+
+> cd demos/cadence/sim
+
+> xt-make all
+
+which is the same as
+
+> xt-make all TARGET=sim
+
+The boards currently supported are the Xilinx ML605 and KC705 FPGA
+development boards. To target these boards, type
+
+> xt-make all TARGET=ml605
+
+or
+
+> xt-make all TARGET=kc705
+
+To build in a location other than the default, specify the new location
+using the BLDROOT variable. Note that this makefile will invoke the 
+FreeRTOS library build makefile automatically, passing on the relevant
+parameters based on what you specified.
+
+You can override the default compilation options by specifying the new
+options via CFLAGS. For example:
+
+> xt-make all TARGET=sim CFLAGS="-O2 -Os -g"
+
+This compiles the examples and links them with the FreeRTOS library
+libfreertos.a and the appropriate linker-support package (LSP) for your
+target platform (you can override the LSP by adding LSP=<lsp> to the
+xt-make command line). The resulting ELF files can be downloaded and
+executed on the target. The example binaries appear in the platform
+specific subdirectory described earlier.
+
+To build your application with thread-safe C library support, you
+need to make certain modifications to the application to plug in and
+invoke the reentrancy support. This allows each task to use the library
+without interference with other tasks (it is not safe for interrupt
+handlers to call the C library).
+
+First, you must define
+
+    XT_USE_THREAD_SAFE_CLIB
+
+to a nonzero value either in xtensa_config.h or on the compiler's command
+line. Note that the default xtensa_config.h provided with this port does
+define this to 1 if either newlib or xclib is detected.
+
+Then, you must also make sure to allocate extra space on the stack for
+each task that will use the C library reentrant functions. This extra
+space is to be allocated over and above the actual stack space required
+by the task itself. The define
+
+    XT_STACK_EXTRA_CLIB
+
+specifies the amount of extra space to be added on to the stack to allow
+saving the context for the C library as well as the coprocessors if any.
+E.g. if your task requires 2000 bytes of stack space, you must allocate
+(2000 + XT_STACK_EXTRA_CLIB) bytes for the stack.
+
+
+IMPORTANT NOTE
+--------------
+
+The header file FreeRTOS.h, which is a part of the core FreeRTOS sources,
+includes <reent.h> if thread safety for the C libraries is enabled. For
+xclib, this file exists in <sys/reent.h> and so is reported as missing.
+To work around this, the makefiles supplied with this port will copy the
+reent.h header into the build directory during the build process. If you
+use a different build process, then you must make sure to copy this file
+to a location that is included in the list of include paths. This can be
+the build directory or the directory that contains the Xtensa port source
+files.
+
+
+Running or Debugging an Application
+-----------------------------------
+
+To execute the example application on the simulator:
+
+> xt-run [--turbo] example.exe
+
+The option --turbo provides much faster, but non-cycle-accurate simulation
+(the --turbo option is only available with Xtensa Tools version 7 or later).
+
+
+To execute on the simulator using the Xplorer GUI based debugger:
+
+> xplorer --debug example.exe
+
+
+To execute on a supported evaluation board, download example.exe per
+instructions in the tools manuals. Be sure the board has been programmed
+with the correct configuration and is set up to boot from RAM and debug
+a downloaded program!  Optionally you may connect a terminal or terminal
+emulator to the serial port on the board with settings as described in
+the board user manual, and see the output of printf on the terminal.
+
+To obtain I/O on a "raw" platform such as an unsupported board, you need
+to provide low level I/O drivers (eg. inbyte() and outbyte() for character
+I/O if you want to use printf etc.).  You can run "raw" executables on
+any Xtensa platform, including simulator and any board, but you will not
+see any behavior specific to the platform (eg. display, printed output,
+stopping simulation at end of program). You can, while debugging, use a
+debugger mechanism called GDBIO to obtain basic I/O. To use GDBIO, link
+with the gdbio LSP. Refer to Xtensa tools documentation for details.
+
+
+Task Stack Sizes
+----------------
+
+The application must ensure that every task has enough space for its
+stack. Each task needs enough space for its own use, its own interrupt
+stack frame (defined in xtensa_context.h) and space to save coprocessor
+state, if any. Several factors influence the size of the stack required,
+including the compiler optimization level and the use of the C library.
+Calls to standard output functions such as printf() can use up a lot of
+stack space. The tool xt-stack-usage is helpful in determining safe stack
+sizes for your application.
+
+Some macros are provided in xtensa_config.h to help determine the stack
+size for tasks that do and do not use the C library. Use these as the
+basis for each task's stack size. They are minimum requirements taking
+into account your configuration and use of the C library. In particular,
+the define
+
+    XT_STACK_MIN_SIZE
+
+defines the minimum stack size for any task. Be very careful if you try
+to use a stack size smaller than this minimum. Stack overruns can cause
+all kinds of hard-to-debug errors. It is recommended that you enable the
+FreeRTOS stack checking features during development.
+
+WARNING: The newlib printf() function uses a lot of stack space. Be very
+careful in using it. Optionally you can use the 'libxtutil' library for
+output - it implements a subset of printf() that has smaller code size
+and uses far less stack space. More information about this library is in
+the Xtensa Tools documentation.
+
+
+Interrupt Stack
+---------------
+
+Beginning with port version 1.2, the port uses a separate interrupt stack
+for handling interrupts. Thus, it is no longer necessary for each task to
+reserve space on its stack to handle interrupts. The size of the interrupt
+stack is controlled by the parameter "configISR_STACK_SIZE" defined in
+FreeRTOSConfig.h. Define this carefully to match your system requirements.
+
+
+Assembler / Compiler Switches
+-----------------------------
+
+The following are compiler switches are used by the provided
+Makefile in building the FreeRTOS library and example application.
+These can be modified by editing the Makefile or by overriding the
+CFLAGS variable in the make command line, for example:
+
+> xt-make CFLAGS="-O2 -DXT_USE_THREAD_SAFE_CLIB"
+
+    -g                      Specifies debug information.
+    -c                      Specifies object code generation.
+    -On                     Sets compiler optimization level n (default -O0).
+    -mlongcalls             Allows assembler and linker to convert call 
+                            instructions to longer indirect call sequences 
+                            when target is out of range.
+    -x assembler-with-cpp   Passes .s and .S files through C preprocessor.
+    -Dmacro                 Define a preprocessor macro with no value.
+    -Dmacro=value           Define a preprocessor macro with a value.
+
+See the compiler / linker documentation for a full list of switches and
+their use.
+
+Many definitions can be provided at compile-time via the -D option 
+without editing the source code. Here are some of the more useful ones:
+
+    XT_USE_THREAD_SAFE_CLIB Enable support for the reentrancy to provide
+                            thread-safety for the newlib and xclib libraries
+                            supplied with Xtensa Tools. Default ON.
+
+    Note, the follwing defines are unique to the Xtensa port so have names
+    beginning with "XT_".
+
+    XT_SIMULATOR            Set this if building to run on the simulator.
+                            Takes advantage of certain simulator control
+                            and reporting facilities, and adjusts timing 
+                            of periodic tick to provide a more acceptable
+                            performance in simulation (see XT_CLOCK_FREQ).
+                            Set by default unless PLATFORM is overridden.
+
+    XT_BOARD                Set this if building for a supported board.
+                            Be sure to specify the correct LSP for the
+                            board. See the example makefile for usage.
+
+    XT_CLOCK_FREQ=freq      Specifies the target processor's clock 
+                            frequency in Hz. Used primarily to set the 
+                            timer that generates the periodic interrupt.
+                            Defaults are provided and may be edited in
+                            xtensa_timer.h (see comments there also).
+                            Default for simulator provides more acceptable
+                            performance, but cannot provide real-time
+                            performance due to variation in simulation
+                            speed per host platform and insufficient 
+                            cycles between interrupts to process them.
+                            Supported board platforms by default leave 
+                            this undefined and compute the clock frequency 
+                            at initialization unless this is explicitly 
+                            defined.
+
+    XT_TICK_PER_SEC=n       Specifies the frequency of the periodic tick.
+
+    XT_TIMER_INDEX=n        Specifies which timer to use for periodic tick.
+                            Set this if your Xtensa processor configuration 
+                            provides more than one suitable timer and you 
+                            want to override the default. See xtensa_timer.h .
+
+    XT_INTEXC_HOOKS         Enables hooks in interrupt vector handlers
+                            to support dynamic installation of exception
+                            and interrupt handlers. Disabled by default.
+
+    XT_USE_OVLY             Enable code overlay support. It uses a mutex,
+                            hence configUSE_MUTEX must be enabled. This
+                            option is currently unsupported.
+
+    XT_USE_SWPRI            Enable software prioritization of interrupts.
+                            Enabling this will prioritize interrupts with
+                            higher bit numbers over those with lower bit
+                            numbers at the same level. This works only for
+                            low and medium priority interrupts that can be
+                            dispatched to C handlers.
+
+
+Register Usage and Stack Frames
+-------------------------------
+
+The Xtensa architecture specifies two ABIs that determine how the general
+purpose registers a0-a15 are used: the standard windowed ABI use with
+the Xtensa windowed register file architecture, and the optional and
+more conventional Call0 ABI (required for Xtensa configurations without
+a windowed register file).
+
+Xtensa processors may have other special registers (including co-processor
+registers and other TIE "states") that are independent of this choice
+of ABI. See Xtensa documentation for more details.
+
+In the windowed ABI the registers of the current window are used as follows:
+    a0      = return address
+    a1      = stack pointer (alias sp)
+    a2      = first argument and result of call (in simple cases)
+    a3-7    = second through sixth arguments of call (in simple cases).
+              Note that complex or large arguments are passed on the
+              stack. Details are in the Xtensa Tools manuals.
+    a8-a15  = available for use as temporaries.
+There are no callee-save registers. The windowed hardware automatically
+saves registers a0-a3 on a call4, a0-a8 on a call8, a0-a12 on a call12,
+by rotating the register window. Hardware triggers window overflow and
+underflow exceptions as necessary when registers outside the current 
+window need to be spilled to preallocated space in the stack frame, or
+restored. Complete details are in the Xtensa manuals. The entire windowed
+register file is saved and restored on interrupt or task context switch.
+
+The Call0 ABI does not make use of register windows, relying instead
+on a fixed set of 16 registers without window rotation.
+The Call0 ABI is more conventional and uses registers as follows:
+    a0      = return address
+    a1      = stack pointer (alias sp)
+    a2      = first argument and result of call (in simple cases)
+    a3-7    = second through sixth arguments of call (in simple cases).
+              Note that complex or large arguments are passed on the
+              stack. Details are in the Xtensa Tools manuals.
+    a8-a11  = scratch.
+    a12-a15 = callee-save (a function must preserve these for its caller).
+On a FreeRTOS API call, callee-save registers are saved only when a task
+context switch occurs, and other registers are not saved at all (the caller
+does not expect them to be preserved). On an interrupt, callee-saved
+registers might only be saved and restored when a task context-switch
+occurs, but all other registers are always saved and restored.
+
+An Xtensa processor has other special registers independent of the ABI,
+depending on the configuration (including co-processor registers and other
+TIE state) that are part of the task context. FreeRTOS preserves all such
+registers over an unsolicited context-switch triggered by an interrupt.
+However it does NOT preserve these over a solicited context-switch during
+a FreeRTOS API call. This bears some explanation. These special registers
+are either ignored by the compiler or treated as caller-saved, meaning
+that if kept "live" over a function call (ie. need to be preserved)
+they must be saved and restored by the caller. Since solicited entry to
+FreeRTOS is always made by a function call, FreeRTOS assumes the caller
+has saved any of these registers that are "live". FreeRTOS avoids a lot
+of overhead by not having to save and restore every special register
+(there can be many) on every solicited context switch.
+
+As a consequence, the application developer should NOT assume that special
+registers are preserved over a FreeRTOS API call such as vTaskDelay().
+If multiple tasks use a register, the caller must save and restore it.
+
+The saved context stack frames for context switches that occur as
+a result of interrupt handling (interrupt frame) or from task-level
+API calls (solicited frame) are described in human readable form in
+xtensa_context.h .  All suspended tasks have one of these two types
+of stack frames. The top of the suspended task's stack is pointed to
+by pxCurrentTCB->pxTopOfStack. A special location common to both stack
+frames differentiates solicited and interrupt stack frames.
+
+
+Improving Performance, Footprint, or Ease of Debugging
+------------------------------------------------------
+
+By default FreeRTOS for Xtensa is built with debug (-g) and without
+compiler optimizations (-O0). This makes debugging easier. Of course,
+-O0 costs performance and usually also increases stack usage. To make
+FreeRTOS run faster you can change the Makefile to enable the desired
+optimizations or set a predefined optimization level (-O<level>) .
+
+Maximum performance is achieved with -O3 -ipa, but that might increase 
+the footprint substantially. A good compromise is -O2. See the compiler
+manual for details.
+
+Minimal footprint is achieved by optimizing for space with -Os, at the
+cost of some performance. See the compiler manual for details.
+
+The Xtensa architecture port-specific assembly files are coded with no
+file-scope labels inside functions (all labels inside functions begin with
+".L"). This allows a profiler to accurately associate an address with a
+function, and also allows the debugger's stack trace to show the correct
+function wherever the program counter is within that function. However
+there are some tradeoffs in debugging. Local (".L") labels are not
+visible to the debugger, so the following limitations may be observed
+during debugging:
+- You cannot set a breakpoint on a local label inside a function.
+- Disassembly will show the entire function, but will get out of sync and
+  show incorrect opcodes if it crosses any padding before an aligned local
+  branch target (".L" label, not ".Ln"). Restart disassembly specifying an
+  address range explicitly between points where there is padding.
+Since FreeRTOS is provided in source form, it is not difficult to remove
+the ".L" and ".Ln" prefixes from local labels if you want them visible.
+They can also be made visible by passing the '-L' option to the assembler
+and linker (see the assembler and linker manuals for details).
+
+
+Interrupt and Exception Handling
+--------------------------------
+
+FreeRTOS provides a complete set of efficient exception and first-level
+interrupt handlers installed at the appropriate exception and interrupt
+vector locations. The Xtensa architecture supports several different
+classes of exceptions and interrupts. Being a configurable architecture,
+many of these are optional, and the vector locations are determined by
+your processor configuration. (Note that Diamond cores are pre-configured
+with specific vector locations.) The handlers provided use conditional
+compilation to adapt to your processor configuration and include only 
+the code that is needed.
+
+Xtensa vector locations may reside almost anywhere, including in ROM.
+The amount of code space available at each of these locations is
+often very small (e.g. due to following vectors). A small stub of
+code installed at the vector jumps to the corresponding handler,
+usually in RAM. The exception and interrupt handlers are defined in
+xtensa_vectors.S. They are not specific to FreeRTOS, but call into
+FreeRTOS where appropriate via macros defined in xtensa_rtos.h .
+
+The handlers provided for low and medium priority interrupts are just
+dispatchers that save relevant state and call user-definable handlers.
+See the files xtensa_vectors.S and xtensa_api.h for more details of how
+to create and install application-specific user interrupt handlers.
+Similarly, user-defined handlers can be installed for exceptions (other
+than a few which are always handled by the OS).
+
+The high priority interrupt handlers provided may be considered templates
+into which the application adds code to service specific interrupts.
+The places where application handlers should be inserted are tagged with
+the comment "USER_EDIT" in xtensa_vectors.S.
+
+This FreeRTOS port supports strict priority-based nesting of interrupts.
+An interrupt may only nest on top of one of strictly lower priority.
+Equal priority interrupts concurrently pending are handled in an
+application-defined sequence before any lower priority interrupts
+are handled. During interrupt and exception handling, the processor's
+interrupt level (PS.INTLEVEL) is used to control the interrupt priority
+level that can be accepted; interrupt sources are not controlled
+individually by FreeRTOS (the application is free to access the INTENABLE
+register directly to enable/disable individual interrupts, eg. using
+Xtensa HAL services). This approach provides the most deterministic
+bounds on interrupt latency (for a given priority) and stack depth.
+
+Software prioritization of interrupts at the same priority is controlled
+by the definition of XT_USE_SWPRI. See above for a description of this
+parameter.
+
+The following subsections describe the handling of each class of exception
+and interrupt in more detail. Many have nothing to do with FreeRTOS but
+are mentioned because there is code to handle them in xtensa_vectors.S.
+
+User Exception and Interrupt Handler (Low/Medium Priority):
+
+    All Xtensa 'general exceptions' come to the user, kernel, or double
+    exception vector.  The exception type is identified by the EXCCAUSE
+    special register (level 1 interrupts are one particular cause of a
+    general exception). This port sets up PS to direct all such exceptions
+    to the user vector. Exceptions taken at the other two vectors usually
+    indicate a kernel or application bug.
+
+    Level 1 interrupts are identified at the beginning of the handler
+    and are dispatched to a dedicated handler. Then, syscall and alloca
+    exceptions are identified and dispatched to special handlers described
+    below. After this, coprocessor exceptions are identified and dispatched
+    to the coprocessor handler.
+
+    Any remaining exceptions are processed as follows:
+
+    Having allocated the exception stack frame, the user exception handler
+    saves the current task state and sets up a C environment and enables
+    the high-priority class of interrupts (which do not interact with
+    FreeRTOS), then reads EXCCAUSE and uses the cause (number) to index
+    into a table of user-specified handlers. The correct handler is then
+    called. If the handler returns, the context is restored and control is
+    returned to the code that caused the exception. The user-defined handler
+    may alter the saved context, or any other system state, that allows the
+    faulting instruction to be retried.
+
+    If the cause is a level 1 (low-priority) or medium-priority interrupt,
+    the handler enables all interrupts above that priority level after
+    saving the task context. It then sets up the environment for C code
+    and then calls the handler (found in the handler table) for the
+    interrupt number. If the user has not specified a handler, then the
+    default handler will be called, which will terminate the program.
+
+    If the interrupt is for the system timer, it calls a special interrupt
+    handler for the system timer tick, which calls _frxt_timer_int then
+    clears its bit from the mask. This interrupt cannot be hooked by the
+    user-defined handler.
+
+    Finally, the handler calls _frxt_int_exit to allow FreeRTOS to perform
+    any scheduling necessary and return either to the interrupted task
+    or another.
+
+    If software prioritization is enabled, the handler will re-enable all
+    interrupts at the same level that are numerically higher than the current
+    one, before calling the user handler. This allows a higher priority
+    interrupt to pre-empt the lower priority handler.
+
+Medium Priority Interrupt Handlers:
+
+    Medium priority interrupts are those at levels 2 up to XCHAL_EXCM_LEVEL,
+    a configuration-specific maximum interrupt level affected by the global
+    'exception mode' bit in the processor status word (PS.EXCM).
+    Interrupt levels above XCHAL_EXCM_LEVEL are of the high-priority class.
+    The Xtensa hardware documentation considers medium priority interrupts
+    to be a special case of high-priority interrupts, but from a software
+    perspective they are very different.
+
+    Dispatch of medium-priority interrupts is discussed in the section
+    above.
+
+High Priority Interrupt Handlers:
+
+    High priority interrupts are those strictly above XCHAL_EXCM_LEVEL, 
+    a configuration-specific maximum interrupt level affected by the 
+    global 'exception mode' bit in the processor status word (PS.EXCM).
+    High priority handlers may not directly interact with FreeRTOS at all,
+    and are described here only for the sake of completeness. They must
+    be coded in assembler (may not be coded in C) and are intended to be 
+    used for handling extremely high frequency hardware events that need
+    to be handled in only a few cycles. A high priority interrupt handler
+    may trigger a software interrupt at a medium or low priority level to
+    occasionally signal FreeRTOS. Please see Xtensa documentation.
+
+    There is a separate vector and a few special registers for each high
+    priority interrupt, providing for fast dispatch and efficient nesting
+    on top of lower priority interrupts. Handlers are templates included
+    only for the vectors that exist in your Xtensa processor configuration.
+    These templates are written for only one interrupt per high priority 
+    level to minimize latency servicing very fast time-critical interrupts.
+    The vector code jumps to the corresponding first-level interrupt handler,
+    which then executes application-provided assembler code before returning
+    quickly to the interrupted task or lower priority handler.
+
+Kernel Exception Handler:
+
+    Kernel mode is not used in this port of FreeRTOS, and therefore kernel
+    exceptions should not happen. A stub is provided for the vector that
+    triggers the debugger (if connected) or calls _xt_panic to freeze the 
+    processor should a kernel exception occur.
+
+Alloca Exception Handler:
+
+    Alloca exceptions are generated by the 'movsp' instruction, which
+    is used only in the windowed ABI. Its purpose is to allocate some
+    space on top of the stack. Because the window hardware may have
+    spilled some registers to the 16 byte "base save" area below the
+    stack pointer, it is necessary to protect those values. The alloca
+    handler accomplishes this quickly without setting up an interrupt
+    frame or entering FreeRTOS, by emulating a register underflow and
+    re-executing 'movsp'.
+
+Syscall Exception Handler:
+
+    Syscall exceptions are generated by a 'syscall' instruction.
+    The windowed ABI specifies that executing this instruction with
+    a value of zero in register a2 must spill any unsaved registers
+    in the windowed register file to their pre-determined locations
+    on the caller's stack. The handler does exactly that, and skips
+    over the 'syscall' instruction before returning to the caller.
+    If a2 is non-zero, the handler returns a2 == -1 to the caller.
+
+Co-Processor Exception Handler:
+
+    A co-processor exception is generated when a task accesses a
+    co-processor that it does not "own". Ownership represents which
+    task's state is currently in the co-processor. Co-processors are
+    context-switched "lazily" (on demand) only when a non-owning task
+    uses a co-processor instruction, otherwise a task retains ownership
+    even when it is preempted from the main processor. The co-processor
+    exception handler performs the context-switch and manages ownership.
+
+    Co-processors may not be used by any code outside the context of a
+    task. A co-processor exception triggered by code that is not part
+    of a running task is a fatal error and FreeRTOS for Xtensa will panic.
+    This restriction is intended to reduce the overhead of saving and 
+    restoring co-processor state (which can be quite large) and in 
+    particular remove that overhead from interrupt handlers.
+
+Debug Exception Handler:
+
+    A debug exception is caused as a result of running code, such as by
+    a 'break' instruction or hardware breakpoints and watchpoints, or
+    as a result of an external debug interrupt, such as from an OCD based
+    debugger or multiprocessor debug events ("breakin/breakout"). If the
+    processor is running in OCD mode under control of an OCD-based debugger,
+    the trigger event immediately halts the processor and gives control to
+    the OCD debugger. Otherwise control is transferred to the debug vector.
+    The debug vector handler calls the simulator if running on the ISS,
+    which then takes control and interacts with any attached debugger.
+    If running on hardware and not in OCD mode, debug exceptions are not
+    expected, so the debug handler calls _xt_panic to freeze the processor.
+
+Double Exception Handler:
+
+    A double exception is a general exception that happens while the
+    processor is in exception mode (PS.EXCM set), and thus indicates a
+    bug in kernel code. The double exception vector handler triggers
+    the debugger (if connected) or calls _xt_panic to freeze the 
+    processor.
+
+Window Overflow and Underflow Exception Handlers:
+
+    Window overflow and underflow handlers are required for use of the
+    windowed ABI. Each has its own dedicated vector and highly optimized
+    code that is independent of OS. See Xtensa documentation for details.
+
+Hooks for Dynamic Installation of Handlers:
+
+    Optional hooks are provided in the user exception and low level
+    interrupt handler and all medium and high priority interrupt handlers,
+    to dynamically install a handler function (which may be coded in C,
+    unless in a high-priority interrupt handler). These hooks are enabled
+    and used by automatic regression tests, they are not part of a normal
+    FreeRTOS build. However an application is free to take advantage of
+    them. The interrupt/exception hooks are described in xtensa_rtos.h .
+
+    It is recommended that the application not make use of these hooks, but
+    rather use xt_set_interrupt_handler() and xt_set_exception_handler()
+    to install application-specific handlers. This method is more convenient
+    and allows arguments to be passed to the handlers. Software prioritization
+    of interrupts works only with this method. See xtensa_api.h for details.
+
+Overlay Support
+
+    Code overlays are currently not supported for FreeRTOS. This will be
+    supported in a future release. Make sure that the option XT_USE_OVLY is
+    never defined when building.
+
+
+-End-
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_api.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
new file mode 100644
index 0000000..1be2905
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
@@ -0,0 +1,123 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Xtensa-specific API for RTOS ports.
+ */
+
+#ifndef __XTENSA_API_H__
+#define __XTENSA_API_H__
+
+#include <xtensa/hal.h>
+
+#include "xtensa_context.h"
+
+
+/* Typedef for C-callable interrupt handler function */
+typedef void (*xt_handler)(void *);
+
+/* Typedef for C-callable exception handler function */
+typedef void (*xt_exc_handler)(XtExcFrame *);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to set a handler for the specified exception.
+
+    n        - Exception number (type)
+    f        - Handler function address, NULL to uninstall handler.
+
+  The handler will be passed a pointer to the exception frame, which is created
+  on the stack of the thread that caused the exception.
+
+  If the handler returns, the thread context will be restored and the faulting
+  instruction will be retried. Any values in the exception frame that are
+  modified by the handler will be restored as part of the context. For details
+  of the exception frame structure see xtensa_context.h.
+-------------------------------------------------------------------------------
+*/
+extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to set a handler for the specified interrupt.
+ 
+    n        - Interrupt number.
+    f        - Handler function address, NULL to uninstall handler.
+    arg      - Argument to be passed to handler.
+-------------------------------------------------------------------------------
+*/
+extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to enable the specified interrupts.
+
+    mask     - Bit mask of interrupts to be enabled.
+
+  Returns the previous state of the interrupt enables.
+-------------------------------------------------------------------------------
+*/
+extern unsigned int xt_ints_on(unsigned int mask);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to disable the specified interrupts.
+
+    mask     - Bit mask of interrupts to be disabled.
+
+  Returns the previous state of the interrupt enables.
+-------------------------------------------------------------------------------
+*/
+extern unsigned int xt_ints_off(unsigned int mask);
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to set the specified (s/w) interrupt.
+-------------------------------------------------------------------------------
+*/
+static inline void xt_set_intset(unsigned int arg)
+{
+    xthal_set_intset(arg);
+}
+
+
+/*
+-------------------------------------------------------------------------------
+  Call this function to clear the specified (s/w or edge-triggered)
+  interrupt.
+-------------------------------------------------------------------------------
+*/
+static inline void xt_set_intclear(unsigned int arg)
+{
+    xthal_set_intclear(arg);
+}
+
+
+#endif /* __XTENSA_API_H__ */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_config.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
new file mode 100644
index 0000000..308361f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
@@ -0,0 +1,183 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Configuration-specific information for Xtensa build. This file must be
+ * included in FreeRTOSConfig.h to properly set up the config-dependent
+ * parameters correctly.
+ *
+ * NOTE: To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must
+ * be defined to be > 0 somewhere above or on the command line.
+ */
+
+#ifndef XTENSA_CONFIG_H
+#define XTENSA_CONFIG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <xtensa/hal.h>
+#include <xtensa/config/core.h>
+#include <xtensa/config/system.h>	/* required for XSHAL_CLIB */
+
+#include "xtensa_context.h"
+
+
+/*-----------------------------------------------------------------------------
+*                                 STACK REQUIREMENTS
+*
+* This section defines the minimum stack size, and the extra space required to
+* be allocated for saving coprocessor state and/or C library state information
+* (if thread safety is enabled for the C library). The sizes are in bytes.
+*
+* Stack sizes for individual tasks should be derived from these minima based on
+* the maximum call depth of the task and the maximum level of interrupt nesting.
+* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
+* on the requirement for a task that calls nothing else but can be interrupted.
+* This assumes that interrupt handlers do not call more than a few levels deep.
+* If this is not true, i.e. one or more interrupt handlers make deep calls then
+* the minimum must be increased.
+*
+* If the Xtensa processor configuration includes coprocessors, then space is 
+* allocated to save the coprocessor state on the stack.
+*
+* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
+* is defined) then space is allocated to save the C library context in the TCB.
+* 
+* Allocating insufficient stack space is a common source of hard-to-find errors.
+* During development, it is best to enable the FreeRTOS stack checking features.
+*
+* Usage:
+* 
+* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
+*                            use of the C library. This will require extra stack
+*                            space to be allocated for tasks that use the C library
+*                            reentrant functions. See below for more information.
+* 
+* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
+* support thread safety. Check your core configuration to see which C library
+* was chosen for your system.
+* 
+* XT_STACK_MIN_SIZE       -- The minimum stack size for any task. It is recommended
+*                            that you do not use a stack smaller than this for any
+*                            task. In case you want to use stacks smaller than this
+*                            size, you must verify that the smaller size(s) will work
+*                            under all operating conditions.
+*
+* XT_STACK_EXTRA          -- The amount of extra stack space to allocate for a task
+*                            that does not make C library reentrant calls. Add this
+*                            to the amount of stack space required by the task itself.
+*
+* XT_STACK_EXTRA_CLIB     -- The amount of space to allocate for C library state.
+*
+-----------------------------------------------------------------------------*/
+
+/* Extra space required for interrupt/exception hooks. */
+#ifdef XT_INTEXC_HOOKS
+  #ifdef __XTENSA_CALL0_ABI__
+    #define STK_INTEXC_EXTRA        0x200
+  #else
+    #define STK_INTEXC_EXTRA        0x180
+  #endif
+#else
+  #define STK_INTEXC_EXTRA          0
+#endif
+
+/* Check C library thread safety support and compute size of C library save area.
+   For the supported libraries, we enable thread safety by default, and this can
+   be overridden from the compiler/make command line. */
+#if (XSHAL_CLIB == XTHAL_CLIB_NEWLIB) || (XSHAL_CLIB == XTHAL_CLIB_XCLIB)
+  #ifndef XT_USE_THREAD_SAFE_CLIB
+    #define XT_USE_THREAD_SAFE_CLIB         1
+  #endif
+#else
+  #define XT_USE_THREAD_SAFE_CLIB           0
+#endif
+
+#if XT_USE_THREAD_SAFE_CLIB > 0u
+  #if XSHAL_CLIB == XTHAL_CLIB_XCLIB
+    #define XT_HAVE_THREAD_SAFE_CLIB        1
+    #if !defined __ASSEMBLER__
+      #include <sys/reent.h>
+      #define XT_CLIB_CONTEXT_AREA_SIZE     ((sizeof(struct _reent) + 15) + (-16))
+      #define XT_CLIB_GLOBAL_PTR            _reent_ptr
+      #define _REENT_INIT_PTR               _init_reent
+      #define _impure_ptr                   _reent_ptr
+
+      void _reclaim_reent(void * ptr);
+    #endif
+  #elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB
+    #define XT_HAVE_THREAD_SAFE_CLIB        1
+    #if !defined __ASSEMBLER__
+      #include <sys/reent.h>
+      #define XT_CLIB_CONTEXT_AREA_SIZE     ((sizeof(struct _reent) + 15) + (-16))
+      #define XT_CLIB_GLOBAL_PTR            _impure_ptr
+    #endif
+  #else
+    #define XT_HAVE_THREAD_SAFE_CLIB        0
+    #error The selected C runtime library is not thread safe.
+  #endif
+#else
+  #define XT_CLIB_CONTEXT_AREA_SIZE         0
+#endif
+
+/*------------------------------------------------------------------------------
+  Extra size -- interrupt frame plus coprocessor save area plus hook space.
+  NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
+------------------------------------------------------------------------------*/
+#ifdef __XTENSA_CALL0_ABI__
+  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE)
+#else
+  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE)
+#endif
+
+/*------------------------------------------------------------------------------
+  Space allocated for user code -- function calls and local variables.
+  NOTE: This number can be adjusted to suit your needs. You must verify that the
+  amount of space you reserve is adequate for the worst-case conditions in your
+  application.
+  NOTE: The windowed ABI requires more stack, since space has to be reserved
+  for spilling register windows.
+------------------------------------------------------------------------------*/
+#ifdef __XTENSA_CALL0_ABI__
+  #define XT_USER_SIZE            0x200
+#else
+  #define XT_USER_SIZE            0x400
+#endif
+
+/* Minimum recommended stack size. */
+#define XT_STACK_MIN_SIZE         ((XT_XTRA_SIZE + XT_USER_SIZE) / sizeof(unsigned char))
+
+/* OS overhead with and without C library thread context. */
+#define XT_STACK_EXTRA              (XT_XTRA_SIZE)
+#define XT_STACK_EXTRA_CLIB         (XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE)
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* XTENSA_CONFIG_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.S
new file mode 100644
index 0000000..7e10b13
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.S
@@ -0,0 +1,625 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * XTENSA CONTEXT SAVE AND RESTORE ROUTINES
+ *
+ * Low-level Call0 functions for handling generic context save and restore of
+ * registers not specifically addressed by the interrupt vectors and handlers.
+ * Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).
+ * Except for the calls to RTOS functions, this code is generic to Xtensa.
+ *
+ * Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-
+ * save regs (A12-A15), which is always the case if the handlers are coded in C.
+ * However A12, A13 are made available as scratch registers for interrupt dispatch
+ * code, so are presumed saved anyway, and are always restored even in Call0 ABI.
+ * Only A14, A15 are truly handled as callee-save regs.
+ *
+ * Because Xtensa is a configurable architecture, this port supports all user
+ * generated configurations (except restrictions stated in the release notes).
+ * This is accomplished by conditional compilation using macros and functions
+ * defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
+ * Only the processor state included in your configuration is saved and restored,
+ * including any processor state added by user configuration options or TIE.
+ */
+
+/*  Warn nicely if this file gets named with a lowercase .s instead of .S:  */
+#define NOERROR #
+NOERROR: .error "C preprocessor needed for this file: make sure its filename\
+ ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option."
+
+
+#include "xtensa_rtos.h"
+
+#ifdef XT_USE_OVLY
+#include <xtensa/overlay_os_asm.h>
+#endif
+
+    .text
+
+/*******************************************************************************
+
+_xt_context_save
+
+    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
+
+Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the
+interrupt stack frame defined in xtensa_rtos.h.
+Its counterpart is _xt_context_restore (which also restores A12, A13).
+
+Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.
+This function preserves A12 & A13 in order to provide the caller with 2 scratch 
+regs that need not be saved over the call to this function. The choice of which
+2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw,
+to avoid moving data more than necessary. Caller can assign regs accordingly.
+
+Entry Conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    Original A12, A13 have already been saved in the interrupt stack frame.
+    Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the 
+    point of interruption.
+    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
+
+Exit conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    A12, A13 as at entry (preserved).
+    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
+
+*******************************************************************************/
+
+    .global _xt_context_save
+    .type   _xt_context_save,@function
+    .align  4
+_xt_context_save:
+
+    s32i    a2,  sp, XT_STK_A2
+    s32i    a3,  sp, XT_STK_A3
+    s32i    a4,  sp, XT_STK_A4
+    s32i    a5,  sp, XT_STK_A5
+    s32i    a6,  sp, XT_STK_A6
+    s32i    a7,  sp, XT_STK_A7
+    s32i    a8,  sp, XT_STK_A8
+    s32i    a9,  sp, XT_STK_A9
+    s32i    a10, sp, XT_STK_A10
+    s32i    a11, sp, XT_STK_A11
+
+    /*
+    Call0 ABI callee-saved regs a12-15 do not need to be saved here.
+    a12-13 are the caller's responsibility so it can use them as scratch.
+    So only need to save a14-a15 here for Windowed ABI (not Call0).
+    */
+    #ifndef __XTENSA_CALL0_ABI__
+    s32i    a14, sp, XT_STK_A14
+    s32i    a15, sp, XT_STK_A15
+    #endif
+
+    rsr     a3,  SAR
+    s32i    a3,  sp, XT_STK_SAR
+
+    #if XCHAL_HAVE_LOOPS
+    rsr     a3,  LBEG
+    s32i    a3,  sp, XT_STK_LBEG
+    rsr     a3,  LEND
+    s32i    a3,  sp, XT_STK_LEND
+    rsr     a3,  LCOUNT
+    s32i    a3,  sp, XT_STK_LCOUNT
+    #endif
+
+    #if XT_USE_SWPRI
+    /* Save virtual priority mask */
+    movi    a3,  _xt_vpri_mask
+    l32i    a3,  a3, 0
+    s32i    a3,  sp, XT_STK_VPRI
+    #endif
+
+    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
+    mov     a9,  a0                     /* preserve ret addr */
+    #endif
+
+    #ifndef __XTENSA_CALL0_ABI__
+    /*
+    To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15.
+    Need to save a9,12,13 temporarily (in frame temps) and recover originals.
+    Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow
+    and underflow exceptions disabled (assured by PS.EXCM == 1).
+    */
+    s32i    a12, sp, XT_STK_TMP0        /* temp. save stuff in stack frame */
+    s32i    a13, sp, XT_STK_TMP1    
+    s32i    a9,  sp, XT_STK_TMP2    
+
+    /*
+    Save the overlay state if we are supporting overlays. Since we just saved
+    three registers, we can conveniently use them here. Note that as of now,
+    overlays only work for windowed calling ABI.
+    */
+    #ifdef XT_USE_OVLY
+    l32i    a9,  sp, XT_STK_PC          /* recover saved PC */
+    _xt_overlay_get_state    a9, a12, a13
+    s32i    a9,  sp, XT_STK_OVLY        /* save overlay state */
+    #endif
+
+    l32i    a12, sp, XT_STK_A12         /* recover original a9,12,13 */
+    l32i    a13, sp, XT_STK_A13
+    l32i    a9,  sp, XT_STK_A9
+    addi    sp,  sp, XT_STK_FRMSZ       /* restore the interruptee's SP */
+    call0   xthal_window_spill_nw       /* preserves only a4,5,8,9,12,13 */
+    addi    sp,  sp, -XT_STK_FRMSZ
+    l32i    a12, sp, XT_STK_TMP0        /* recover stuff from stack frame */
+    l32i    a13, sp, XT_STK_TMP1    
+    l32i    a9,  sp, XT_STK_TMP2    
+    #endif
+
+    #if XCHAL_EXTRA_SA_SIZE > 0
+    /*  
+    NOTE: Normally the xthal_save_extra_nw macro only affects address
+    registers a2-a5. It is theoretically possible for Xtensa processor
+    designers to write TIE that causes more address registers to be
+    affected, but it is generally unlikely. If that ever happens,
+    more registers need to be saved/restored around this macro invocation.
+    Here we assume a9,12,13 are preserved.
+    Future Xtensa tools releases might limit the regs that can be affected.
+    */
+    addi    a2,  sp, XT_STK_EXTRA       /* where to save it */
+    # if XCHAL_EXTRA_SA_ALIGN > 16
+    movi    a3, -XCHAL_EXTRA_SA_ALIGN
+    and     a2, a2, a3                  /* align dynamically >16 bytes */
+    # endif
+    call0   xthal_save_extra_nw         /* destroys a0,2,3,4,5 */
+    #endif
+
+    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
+    mov     a0, a9                      /* retrieve ret addr */
+    #endif
+
+    ret
+
+/*******************************************************************************
+
+_xt_context_restore
+
+    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
+
+Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0
+ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt 
+stack frame defined in xtensa_rtos.h .
+Its counterpart is _xt_context_save (whose caller saved A12, A13).
+
+Caller is responsible to restore PC, PS, A0, A1 (SP).
+
+Entry Conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+
+Exit conditions:
+    A0  = Return address in caller.
+    A1  = Stack pointer of interrupted thread or handler ("interruptee").
+    Other processor state except PC, PS, A0, A1 (SP), is as at the point 
+    of interruption.
+
+*******************************************************************************/
+
+    .global _xt_context_restore
+    .type   _xt_context_restore,@function
+    .align  4
+_xt_context_restore:
+
+    #if XCHAL_EXTRA_SA_SIZE > 0
+    /*  
+    NOTE: Normally the xthal_restore_extra_nw macro only affects address
+    registers a2-a5. It is theoretically possible for Xtensa processor
+    designers to write TIE that causes more address registers to be
+    affected, but it is generally unlikely. If that ever happens,
+    more registers need to be saved/restored around this macro invocation.
+    Here we only assume a13 is preserved.
+    Future Xtensa tools releases might limit the regs that can be affected.
+    */
+    mov     a13, a0                     /* preserve ret addr */
+    addi    a2,  sp, XT_STK_EXTRA       /* where to find it */
+    # if XCHAL_EXTRA_SA_ALIGN > 16
+    movi    a3, -XCHAL_EXTRA_SA_ALIGN
+    and     a2, a2, a3                  /* align dynamically >16 bytes */
+    # endif
+    call0   xthal_restore_extra_nw      /* destroys a0,2,3,4,5 */
+    mov     a0,  a13                    /* retrieve ret addr */
+    #endif
+
+    #if XCHAL_HAVE_LOOPS
+    l32i    a2,  sp, XT_STK_LBEG
+    l32i    a3,  sp, XT_STK_LEND
+    wsr     a2,  LBEG
+    l32i    a2,  sp, XT_STK_LCOUNT
+    wsr     a3,  LEND
+    wsr     a2,  LCOUNT
+    #endif
+
+    #ifdef XT_USE_OVLY
+    /*
+    If we are using overlays, this is a good spot to check if we need
+    to restore an overlay for the incoming task. Here we have a bunch
+    of registers to spare. Note that this step is going to use a few
+    bytes of storage below SP (SP-20 to SP-32) if an overlay is going
+    to be restored.
+    */
+    l32i    a2,  sp, XT_STK_PC          /* retrieve PC */
+    l32i    a3,  sp, XT_STK_PS          /* retrieve PS */
+    l32i    a4,  sp, XT_STK_OVLY        /* retrieve overlay state */
+    l32i    a5,  sp, XT_STK_A1          /* retrieve stack ptr */
+    _xt_overlay_check_map    a2, a3, a4, a5, a6
+    s32i    a2,  sp, XT_STK_PC          /* save updated PC */
+    s32i    a3,  sp, XT_STK_PS          /* save updated PS */
+    #endif
+
+    #ifdef XT_USE_SWPRI
+    /* Restore virtual interrupt priority and interrupt enable */
+    movi    a3,  _xt_intdata
+    l32i    a4,  a3, 0                  /* a4 = _xt_intenable */
+    l32i    a5,  sp, XT_STK_VPRI        /* a5 = saved _xt_vpri_mask */
+    and     a4,  a4, a5
+    wsr     a4,  INTENABLE              /* update INTENABLE */
+    s32i    a5,  a3, 4                  /* restore _xt_vpri_mask */
+    #endif
+
+    l32i    a3,  sp, XT_STK_SAR
+    l32i    a2,  sp, XT_STK_A2
+    wsr     a3,  SAR
+    l32i    a3,  sp, XT_STK_A3
+    l32i    a4,  sp, XT_STK_A4
+    l32i    a5,  sp, XT_STK_A5
+    l32i    a6,  sp, XT_STK_A6
+    l32i    a7,  sp, XT_STK_A7
+    l32i    a8,  sp, XT_STK_A8
+    l32i    a9,  sp, XT_STK_A9
+    l32i    a10, sp, XT_STK_A10
+    l32i    a11, sp, XT_STK_A11
+
+    /*
+    Call0 ABI callee-saved regs a12-15 do not need to be restored here.
+    However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(), 
+    so need to be restored anyway, despite being callee-saved in Call0.
+    */
+    l32i    a12, sp, XT_STK_A12
+    l32i    a13, sp, XT_STK_A13
+    #ifndef __XTENSA_CALL0_ABI__
+    l32i    a14, sp, XT_STK_A14
+    l32i    a15, sp, XT_STK_A15
+    #endif
+
+    ret
+
+
+/*******************************************************************************
+
+_xt_coproc_init
+
+Initializes global co-processor management data, setting all co-processors
+to "unowned". Leaves CPENABLE as it found it (does NOT clear it).
+
+Called during initialization of the RTOS, before any threads run.
+
+This may be called from normal Xtensa single-threaded application code which
+might use co-processors. The Xtensa run-time initialization enables all 
+co-processors. They must remain enabled here, else a co-processor exception
+might occur outside of a thread, which the exception handler doesn't expect.
+
+Entry Conditions:
+    Xtensa single-threaded run-time environment is in effect.
+    No thread is yet running.
+
+Exit conditions:
+    None.
+
+Obeys ABI conventions per prototype:
+    void _xt_coproc_init(void)
+
+*******************************************************************************/
+
+#if XCHAL_CP_NUM > 0
+
+    .global _xt_coproc_init
+    .type   _xt_coproc_init,@function
+    .align  4
+_xt_coproc_init:
+    ENTRY0
+
+    /* Initialize thread co-processor ownerships to 0 (unowned). */
+    movi    a2, _xt_coproc_owner_sa         /* a2 = base of owner array */
+    addi    a3, a2, XCHAL_CP_MAX << 2       /* a3 = top+1 of owner array */
+    movi    a4, 0                           /* a4 = 0 (unowned) */
+1:  s32i    a4, a2, 0
+    addi    a2, a2, 4
+    bltu    a2, a3, 1b
+
+    RET0
+
+#endif
+
+
+/*******************************************************************************
+
+_xt_coproc_release
+
+Releases any and all co-processors owned by a given thread. The thread is 
+identified by it's co-processor state save area defined in xtensa_context.h .
+
+Must be called before a thread's co-proc save area is deleted to avoid
+memory corruption when the exception handler tries to save the state.
+May be called when a thread terminates or completes but does not delete
+the co-proc save area, to avoid the exception handler having to save the 
+thread's co-proc state before another thread can use it (optimization).
+
+Entry Conditions:
+    A2  = Pointer to base of co-processor state save area.
+
+Exit conditions:
+    None.
+
+Obeys ABI conventions per prototype:
+    void _xt_coproc_release(void * coproc_sa_base)
+
+*******************************************************************************/
+
+#if XCHAL_CP_NUM > 0
+
+    .global _xt_coproc_release
+    .type   _xt_coproc_release,@function
+    .align  4
+_xt_coproc_release:
+    ENTRY0                                  /* a2 = base of save area */
+
+    movi    a3, _xt_coproc_owner_sa         /* a3 = base of owner array */
+    addi    a4, a3, XCHAL_CP_MAX << 2       /* a4 = top+1 of owner array */
+    movi    a5, 0                           /* a5 = 0 (unowned) */
+
+    rsil    a6, XCHAL_EXCM_LEVEL            /* lock interrupts */
+
+1:  l32i    a7, a3, 0                       /* a7 = owner at a3 */
+    bne     a2, a7, 2f                      /* if (coproc_sa_base == owner) */
+    s32i    a5, a3, 0                       /*   owner = unowned */
+2:  addi    a3, a3, 1<<2                    /* a3 = next entry in owner array */
+    bltu    a3, a4, 1b                      /* repeat until end of array */
+
+3:  wsr     a6, PS                          /* restore interrupts */
+
+    RET0
+
+#endif
+
+
+/*******************************************************************************
+_xt_coproc_savecs
+
+If there is a current thread and it has a coprocessor state save area, then
+save all callee-saved state into this area. This function is called from the
+solicited context switch handler. It calls a system-specific function to get
+the coprocessor save area base address.
+
+Entry conditions:
+    - The thread being switched out is still the current thread.
+    - CPENABLE state reflects which coprocessors are active.
+    - Registers have been saved/spilled already.
+
+Exit conditions:
+    - All necessary CP callee-saved state has been saved.
+    - Registers a2-a7, a13-a15 have been trashed.
+
+Must be called from assembly code only, using CALL0.
+*******************************************************************************/
+#if XCHAL_CP_NUM > 0
+
+    .extern     _xt_coproc_sa_offset   /* external reference */
+
+    .global     _xt_coproc_savecs
+    .type       _xt_coproc_savecs,@function
+    .align      4
+_xt_coproc_savecs:
+
+    /* At entry, CPENABLE should be showing which CPs are enabled. */
+
+    rsr     a2, CPENABLE                /* a2 = which CPs are enabled      */
+    beqz    a2, .Ldone                  /* quick exit if none              */
+    mov     a14, a0                     /* save return address             */
+    call0   XT_RTOS_CP_STATE            /* get address of CP save area     */
+    mov     a0, a14                     /* restore return address          */
+    beqz    a15, .Ldone                 /* if none then nothing to do      */
+    s16i    a2, a15, XT_CP_CS_ST        /* save mask of CPs being stored   */
+    movi    a13, _xt_coproc_sa_offset   /* array of CP save offsets        */
+    l32i    a15, a15, XT_CP_ASA         /* a15 = base of aligned save area */
+
+#if XCHAL_CP0_SA_SIZE
+    bbci.l  a2, 0, 2f                   /* CP 0 not enabled                */
+    l32i    a14, a13, 0                 /* a14 = _xt_coproc_sa_offset[0]   */
+    add     a3, a14, a15                /* a3 = save area for CP 0         */
+    xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP1_SA_SIZE
+    bbci.l  a2, 1, 2f                   /* CP 1 not enabled                */
+    l32i    a14, a13, 4                 /* a14 = _xt_coproc_sa_offset[1]   */
+    add     a3, a14, a15                /* a3 = save area for CP 1         */
+    xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP2_SA_SIZE
+    bbci.l  a2, 2, 2f
+    l32i    a14, a13, 8
+    add     a3, a14, a15
+    xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP3_SA_SIZE
+    bbci.l  a2, 3, 2f
+    l32i    a14, a13, 12
+    add     a3, a14, a15
+    xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP4_SA_SIZE
+    bbci.l  a2, 4, 2f
+    l32i    a14, a13, 16
+    add     a3, a14, a15
+    xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP5_SA_SIZE
+    bbci.l  a2, 5, 2f
+    l32i    a14, a13, 20
+    add     a3, a14, a15
+    xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP6_SA_SIZE
+    bbci.l  a2, 6, 2f
+    l32i    a14, a13, 24
+    add     a3, a14, a15
+    xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP7_SA_SIZE
+    bbci.l  a2, 7, 2f
+    l32i    a14, a13, 28
+    add     a3, a14, a15
+    xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+.Ldone:
+    ret
+#endif
+
+
+/*******************************************************************************
+_xt_coproc_restorecs
+
+Restore any callee-saved coprocessor state for the incoming thread.
+This function is called from coprocessor exception handling, when giving
+ownership to a thread that solicited a context switch earlier. It calls a
+system-specific function to get the coprocessor save area base address.
+
+Entry conditions:
+    - The incoming thread is set as the current thread.
+    - CPENABLE is set up correctly for all required coprocessors.
+    - a2 = mask of coprocessors to be restored.
+
+Exit conditions:
+    - All necessary CP callee-saved state has been restored.
+    - CPENABLE - unchanged.
+    - Registers a2-a7, a13-a15 have been trashed.
+
+Must be called from assembly code only, using CALL0.
+*******************************************************************************/
+#if XCHAL_CP_NUM > 0
+
+    .global     _xt_coproc_restorecs
+    .type       _xt_coproc_restorecs,@function
+    .align      4
+_xt_coproc_restorecs:
+
+    mov     a14, a0                     /* save return address             */
+    call0   XT_RTOS_CP_STATE            /* get address of CP save area     */
+    mov     a0, a14                     /* restore return address          */
+    beqz    a15, .Ldone2                /* if none then nothing to do      */
+    l16ui   a3, a15, XT_CP_CS_ST        /* a3 = which CPs have been saved  */
+    xor     a3, a3, a2                  /* clear the ones being restored   */
+    s32i    a3, a15, XT_CP_CS_ST        /* update saved CP mask            */
+    movi    a13, _xt_coproc_sa_offset   /* array of CP save offsets        */
+    l32i    a15, a15, XT_CP_ASA         /* a15 = base of aligned save area */
+    
+#if XCHAL_CP0_SA_SIZE
+    bbci.l  a2, 0, 2f                   /* CP 0 not enabled                */
+    l32i    a14, a13, 0                 /* a14 = _xt_coproc_sa_offset[0]   */
+    add     a3, a14, a15                /* a3 = save area for CP 0         */
+    xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:  
+#endif
+
+#if XCHAL_CP1_SA_SIZE
+    bbci.l  a2, 1, 2f                   /* CP 1 not enabled                */
+    l32i    a14, a13, 4                 /* a14 = _xt_coproc_sa_offset[1]   */
+    add     a3, a14, a15                /* a3 = save area for CP 1         */
+    xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP2_SA_SIZE
+    bbci.l  a2, 2, 2f
+    l32i    a14, a13, 8
+    add     a3, a14, a15
+    xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP3_SA_SIZE
+    bbci.l  a2, 3, 2f
+    l32i    a14, a13, 12
+    add     a3, a14, a15
+    xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP4_SA_SIZE
+    bbci.l  a2, 4, 2f
+    l32i    a14, a13, 16
+    add     a3, a14, a15
+    xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP5_SA_SIZE
+    bbci.l  a2, 5, 2f
+    l32i    a14, a13, 20
+    add     a3, a14, a15
+    xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP6_SA_SIZE
+    bbci.l  a2, 6, 2f
+    l32i    a14, a13, 24
+    add     a3, a14, a15
+    xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+#if XCHAL_CP7_SA_SIZE
+    bbci.l  a2, 7, 2f
+    l32i    a14, a13, 28
+    add     a3, a14, a15
+    xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
+2:
+#endif
+
+.Ldone2:
+    ret
+
+#endif
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
new file mode 100644
index 0000000..122d236
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
@@ -0,0 +1,351 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
+ *
+ * This header contains definitions and macros for use primarily by Xtensa
+ * RTOS assembly coded source files. It includes and uses the Xtensa hardware
+ * abstraction layer (HAL) to deal with config specifics. It may also be
+ * included in C source files.
+ *
+ * !! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !!
+ *
+ * NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
+ */
+
+#ifndef XTENSA_CONTEXT_H
+#define XTENSA_CONTEXT_H
+
+#ifdef __ASSEMBLER__
+#include    <xtensa/coreasm.h>
+#endif
+
+#include    <xtensa/config/tie.h>
+#include    <xtensa/corebits.h>
+#include    <xtensa/config/system.h>
+
+
+/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
+#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
+
+
+/*
+-------------------------------------------------------------------------------
+  Macros that help define structures for both C and assembler.
+-------------------------------------------------------------------------------
+*/
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
+
+#define STRUCT_BEGIN            .pushsection .text; .struct 0
+#define STRUCT_FIELD(ctype,size,asname,name)    asname: .space  size
+#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space  (size)*(n)
+#define STRUCT_END(sname)       sname##Size:; .popsection
+
+#else
+
+#define STRUCT_BEGIN            typedef struct {
+#define STRUCT_FIELD(ctype,size,asname,name)    ctype   name;
+#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype   name[n];
+#define STRUCT_END(sname)       } sname;
+
+#endif //_ASMLANGUAGE || __ASSEMBLER__
+
+
+/*
+-------------------------------------------------------------------------------
+  INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
+
+  A stack frame of this structure is allocated for any interrupt or exception.
+  It goes on the current stack. If the RTOS has a system stack for handling 
+  interrupts, every thread stack must allow space for just one interrupt stack 
+  frame, then nested interrupt stack frames go on the system stack.
+
+  The frame includes basic registers (explicit) and "extra" registers introduced 
+  by user TIE or the use of the MAC16 option in the user's Xtensa config.
+  The frame size is minimized by omitting regs not applicable to user's config.
+
+  For Windowed ABI, this stack frame includes the interruptee's base save area,
+  another base save area to manage gcc nested functions, and a little temporary 
+  space to help manage the spilling of the register windows.
+-------------------------------------------------------------------------------
+*/
+
+STRUCT_BEGIN
+STRUCT_FIELD (long, 4, XT_STK_EXIT,     exit) /* exit point for dispatch */
+STRUCT_FIELD (long, 4, XT_STK_PC,       pc)   /* return PC */
+STRUCT_FIELD (long, 4, XT_STK_PS,       ps)   /* return PS */
+STRUCT_FIELD (long, 4, XT_STK_A0,       a0)
+STRUCT_FIELD (long, 4, XT_STK_A1,       a1)   /* stack pointer before interrupt */
+STRUCT_FIELD (long, 4, XT_STK_A2,       a2)
+STRUCT_FIELD (long, 4, XT_STK_A3,       a3)
+STRUCT_FIELD (long, 4, XT_STK_A4,       a4)
+STRUCT_FIELD (long, 4, XT_STK_A5,       a5)
+STRUCT_FIELD (long, 4, XT_STK_A6,       a6)
+STRUCT_FIELD (long, 4, XT_STK_A7,       a7)
+STRUCT_FIELD (long, 4, XT_STK_A8,       a8)
+STRUCT_FIELD (long, 4, XT_STK_A9,       a9)
+STRUCT_FIELD (long, 4, XT_STK_A10,      a10)
+STRUCT_FIELD (long, 4, XT_STK_A11,      a11)
+STRUCT_FIELD (long, 4, XT_STK_A12,      a12)
+STRUCT_FIELD (long, 4, XT_STK_A13,      a13)
+STRUCT_FIELD (long, 4, XT_STK_A14,      a14)
+STRUCT_FIELD (long, 4, XT_STK_A15,      a15)
+STRUCT_FIELD (long, 4, XT_STK_SAR,      sar)
+STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
+STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
+#if XCHAL_HAVE_LOOPS
+STRUCT_FIELD (long, 4, XT_STK_LBEG,   lbeg)
+STRUCT_FIELD (long, 4, XT_STK_LEND,   lend)
+STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
+#endif
+#ifndef __XTENSA_CALL0_ABI__
+/* Temporary space for saving stuff during window spill */
+STRUCT_FIELD (long, 4, XT_STK_TMP0,   tmp0)
+STRUCT_FIELD (long, 4, XT_STK_TMP1,   tmp1)
+STRUCT_FIELD (long, 4, XT_STK_TMP2,   tmp2)
+#endif
+#ifdef XT_USE_SWPRI
+/* Storage for virtual priority mask */
+STRUCT_FIELD (long, 4, XT_STK_VPRI,   vpri)
+#endif
+#ifdef XT_USE_OVLY
+/* Storage for overlay state */
+STRUCT_FIELD (long, 4, XT_STK_OVLY,   ovly)
+#endif
+STRUCT_END(XtExcFrame)
+
+#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
+#define XT_STK_NEXT1      XtExcFrameSize
+#else
+#define XT_STK_NEXT1      sizeof(XtExcFrame)
+#endif
+
+/* Allocate extra storage if needed */
+#if XCHAL_EXTRA_SA_SIZE != 0
+
+#if XCHAL_EXTRA_SA_ALIGN <= 16
+#define XT_STK_EXTRA            ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
+#else
+/* If need more alignment than stack, add space for dynamic alignment */
+#define XT_STK_EXTRA            (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
+#endif
+#define XT_STK_NEXT2            (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
+
+#else
+
+#define XT_STK_NEXT2            XT_STK_NEXT1   
+
+#endif
+
+/*
+-------------------------------------------------------------------------------
+  This is the frame size. Add space for 4 registers (interruptee's base save
+  area) and some space for gcc nested functions if any.
+-------------------------------------------------------------------------------
+*/
+#define XT_STK_FRMSZ            (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
+
+
+/*
+-------------------------------------------------------------------------------
+  SOLICITED STACK FRAME FOR A THREAD
+
+  A stack frame of this structure is allocated whenever a thread enters the 
+  RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
+  It goes on the current thread's stack.
+
+  The solicited frame only includes registers that are required to be preserved
+  by the callee according to the compiler's ABI conventions, some space to save 
+  the return address for returning to the caller, and the caller's PS register.
+
+  For Windowed ABI, this stack frame includes the caller's base save area.
+
+  Note on XT_SOL_EXIT field:
+      It is necessary to distinguish a solicited from an interrupt stack frame.
+      This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
+      always at the same offset (0). It can be written with a code (usually 0) 
+      to distinguish a solicted frame from an interrupt frame. An RTOS port may
+      opt to ignore this field if it has another way of distinguishing frames.
+-------------------------------------------------------------------------------
+*/
+
+STRUCT_BEGIN
+#ifdef __XTENSA_CALL0_ABI__
+STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
+STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
+STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
+STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
+STRUCT_FIELD (long, 4, XT_SOL_A12,  a12)    /* should be on 16-byte alignment */
+STRUCT_FIELD (long, 4, XT_SOL_A13,  a13)
+STRUCT_FIELD (long, 4, XT_SOL_A14,  a14)
+STRUCT_FIELD (long, 4, XT_SOL_A15,  a15)
+#else
+STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
+STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
+STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
+STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
+STRUCT_FIELD (long, 4, XT_SOL_A0,   a0)    /* should be on 16-byte alignment */
+STRUCT_FIELD (long, 4, XT_SOL_A1,   a1)
+STRUCT_FIELD (long, 4, XT_SOL_A2,   a2)
+STRUCT_FIELD (long, 4, XT_SOL_A3,   a3)
+#endif
+STRUCT_END(XtSolFrame)
+
+/* Size of solicited stack frame */
+#define XT_SOL_FRMSZ            ALIGNUP(0x10, XtSolFrameSize)
+
+
+/*
+-------------------------------------------------------------------------------
+  CO-PROCESSOR STATE SAVE AREA FOR A THREAD
+
+  The RTOS must provide an area per thread to save the state of co-processors
+  when that thread does not have control. Co-processors are context-switched
+  lazily (on demand) only when a new thread uses a co-processor instruction,
+  otherwise a thread retains ownership of the co-processor even when it loses
+  control of the processor. An Xtensa co-processor exception is triggered when
+  any co-processor instruction is executed by a thread that is not the owner,
+  and the context switch of that co-processor is then peformed by the handler.
+  Ownership represents which thread's state is currently in the co-processor.
+
+  Co-processors may not be used by interrupt or exception handlers. If an 
+  co-processor instruction is executed by an interrupt or exception handler,
+  the co-processor exception handler will trigger a kernel panic and freeze.
+  This restriction is introduced to reduce the overhead of saving and restoring
+  co-processor state (which can be quite large) and in particular remove that
+  overhead from interrupt handlers.
+
+  The co-processor state save area may be in any convenient per-thread location
+  such as in the thread control block or above the thread stack area. It need
+  not be in the interrupt stack frame since interrupts don't use co-processors.
+
+  Along with the save area for each co-processor, two bitmasks with flags per 
+  co-processor (laid out as in the CPENABLE reg) help manage context-switching
+  co-processors as efficiently as possible:
+
+  XT_CPENABLE
+    The contents of a non-running thread's CPENABLE register.
+    It represents the co-processors owned (and whose state is still needed)
+    by the thread. When a thread is preempted, its CPENABLE is saved here.
+    When a thread solicits a context-swtich, its CPENABLE is cleared - the
+    compiler has saved the (caller-saved) co-proc state if it needs to.
+    When a non-running thread loses ownership of a CP, its bit is cleared.
+    When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
+    Avoids co-processor exceptions when no change of ownership is needed.
+
+  XT_CPSTORED
+    A bitmask with the same layout as CPENABLE, a bit per co-processor.
+    Indicates whether the state of each co-processor is saved in the state 
+    save area. When a thread enters the kernel, only the state of co-procs
+    still enabled in CPENABLE is saved. When the co-processor exception 
+    handler assigns ownership of a co-processor to a thread, it restores 
+    the saved state only if this bit is set, and clears this bit.
+
+  XT_CP_CS_ST
+    A bitmask with the same layout as CPENABLE, a bit per co-processor.
+    Indicates whether callee-saved state is saved in the state save area.
+    Callee-saved state is saved by itself on a solicited context switch,
+    and restored when needed by the coprocessor exception handler.
+    Unsolicited switches will cause the entire coprocessor to be saved
+    when necessary.
+
+  XT_CP_ASA
+    Pointer to the aligned save area.  Allows it to be aligned more than
+    the overall save area (which might only be stack-aligned or TCB-aligned).
+    Especially relevant for Xtensa cores configured with a very large data
+    path that requires alignment greater than 16 bytes (ABI stack alignment).
+-------------------------------------------------------------------------------
+*/
+
+#if XCHAL_CP_NUM > 0
+
+/*  Offsets of each coprocessor save area within the 'aligned save area':  */
+#define XT_CP0_SA   0
+#define XT_CP1_SA   ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
+#define XT_CP2_SA   ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
+#define XT_CP3_SA   ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
+#define XT_CP4_SA   ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
+#define XT_CP5_SA   ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
+#define XT_CP6_SA   ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
+#define XT_CP7_SA   ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
+#define XT_CP_SA_SIZE   ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
+
+/*  Offsets within the overall save area:  */
+#define XT_CPENABLE 0   /* (2 bytes) coprocessors active for this thread */
+#define XT_CPSTORED 2   /* (2 bytes) coprocessors saved for this thread */
+#define XT_CP_CS_ST 4   /* (2 bytes) coprocessor callee-saved regs stored for this thread */
+#define XT_CP_ASA   8   /* (4 bytes) ptr to aligned save area */
+/*  Overall size allows for dynamic alignment:  */
+#define XT_CP_SIZE  (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
+#else
+#define XT_CP_SIZE  0
+#endif
+
+
+/*
+-------------------------------------------------------------------------------
+  MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
+
+  Convenient where the frame size requirements are the same for both ABIs.
+    ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
+    ENTRY0,    RET0    are for frameless functions (no locals, no calls).
+
+  where size = size of stack frame in bytes (must be >0 and aligned to 16).
+  For framed functions the frame is created and the return address saved at
+  base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
+  For frameless functions, there is no frame and return address remains in a0.
+  Note: Because CPP macros expand to a single line, macros requiring multi-line 
+  expansions are implemented as assembler macros.
+-------------------------------------------------------------------------------
+*/
+
+#ifdef __ASSEMBLER__
+#ifdef __XTENSA_CALL0_ABI__
+  /* Call0 */
+  #define ENTRY(sz)     entry1  sz
+    .macro  entry1 size=0x10
+    addi    sp, sp, -\size
+    s32i    a0, sp, 0
+    .endm
+  #define ENTRY0      
+  #define RET(sz)       ret1    sz
+    .macro  ret1 size=0x10
+    l32i    a0, sp, 0
+    addi    sp, sp, \size
+    ret
+    .endm
+  #define RET0          ret
+#else
+  /* Windowed */
+  #define ENTRY(sz)     entry   sp, sz
+  #define ENTRY0        entry   sp, 0x10
+  #define RET(sz)       retw
+  #define RET0          retw
+#endif
+#endif
+
+
+#endif /* XTENSA_CONTEXT_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_init.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
new file mode 100644
index 0000000..da8bf2d
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
@@ -0,0 +1,66 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * XTENSA INITIALIZATION ROUTINES CODED IN C
+ *
+ * This file contains miscellaneous Xtensa RTOS-generic initialization functions
+ * that are implemented in C.
+ */
+
+
+#ifdef XT_BOARD
+#include    <xtensa/xtbsp.h>
+#endif
+
+#include    "xtensa_rtos.h"
+
+#ifdef XT_RTOS_TIMER_INT
+
+unsigned _xt_tick_divisor = 0;  /* cached number of cycles per tick */
+
+/*
+Compute and initialize at run-time the tick divisor (the number of 
+processor clock cycles in an RTOS tick, used to set the tick timer).
+Called when the processor clock frequency is not known at compile-time.
+*/
+void _xt_tick_divisor_init(void)
+{
+#ifdef XT_CLOCK_FREQ
+
+    _xt_tick_divisor = (XT_CLOCK_FREQ / XT_TICK_PER_SEC);
+
+#else
+
+    #ifdef XT_BOARD
+    _xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC;
+    #else
+    #error "No way to obtain processor clock frequency"
+    #endif  /* XT_BOARD */
+
+#endif /* XT_CLOCK_FREQ */
+}
+
+#endif /* XT_RTOS_TIMER_INT */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
new file mode 100644
index 0000000..846aafb
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
@@ -0,0 +1,133 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Xtensa-specific interrupt and exception functions for RTOS ports.
+ * Also see xtensa_intr_asm.S.
+ */
+
+#include <stdlib.h>
+
+#include <xtensa/config/core.h>
+
+#include "xtensa_api.h"
+
+
+#if XCHAL_HAVE_EXCEPTIONS
+
+/* Handler table is in xtensa_intr_asm.S */
+
+extern xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM];
+
+
+/*
+  Default handler for unhandled exceptions.
+*/
+void xt_unhandled_exception(XtExcFrame *frame)
+{
+    exit(-1);
+}
+
+
+/*
+  This function registers a handler for the specified exception.
+  The function returns the address of the previous handler.
+  On error, it returns 0.
+*/
+xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f)
+{
+    xt_exc_handler old;
+
+    if( n < 0 || n >= XCHAL_EXCCAUSE_NUM )
+        return 0;       /* invalid exception number */
+
+    old = _xt_exception_table[n];
+
+    if (f) {
+        _xt_exception_table[n] = f;
+    }
+    else {
+        _xt_exception_table[n] = &xt_unhandled_exception;
+    }
+
+    return ((old == &xt_unhandled_exception) ? 0 : old);
+}
+
+#endif
+
+#if XCHAL_HAVE_INTERRUPTS
+
+/* Handler table is in xtensa_intr_asm.S */
+
+typedef struct xt_handler_table_entry {
+    void * handler;
+    void * arg;
+} xt_handler_table_entry;
+
+extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS];
+
+
+/*
+  Default handler for unhandled interrupts.
+*/
+void xt_unhandled_interrupt(void * arg)
+{
+    exit(-1);
+}
+
+
+/*
+  This function registers a handler for the specified interrupt. The "arg"
+  parameter specifies the argument to be passed to the handler when it is
+  invoked. The function returns the address of the previous handler.
+  On error, it returns 0.
+*/
+xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg)
+{
+    xt_handler_table_entry * entry;
+    xt_handler               old;
+
+    if( n < 0 || n >= XCHAL_NUM_INTERRUPTS )
+        return 0;       /* invalid interrupt number */
+    if( Xthal_intlevel[n] > XCHAL_EXCM_LEVEL )
+        return 0;       /* priority level too high to safely handle in C */
+
+    entry = _xt_interrupt_table + n;
+    old   = entry->handler;
+
+    if (f) {
+        entry->handler = f;
+        entry->arg     = arg;
+    }
+    else {
+        entry->handler = &xt_unhandled_interrupt;
+        entry->arg     = (void*)n;
+    }
+
+    return ((old == &xt_unhandled_interrupt) ? 0 : old);
+}
+
+
+#endif /* XCHAL_HAVE_INTERRUPTS */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S
new file mode 100644
index 0000000..45060f1
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S
@@ -0,0 +1,180 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * Xtensa interrupt handling data and assembly routines.
+ * Also see xtensa_intr.c and xtensa_vectors.S.
+ */
+
+#include <xtensa/hal.h>
+#include <xtensa/config/core.h>
+
+#include "xtensa_context.h"
+
+#if XCHAL_HAVE_INTERRUPTS
+
+/*
+-------------------------------------------------------------------------------
+  INTENABLE virtualization information.
+-------------------------------------------------------------------------------
+*/
+
+    .data
+    .global _xt_intdata
+    .align  8
+_xt_intdata:
+    .global _xt_intenable
+    .type   _xt_intenable,@object
+    .size   _xt_intenable,4
+    .global _xt_vpri_mask
+    .type   _xt_vpri_mask,@object
+    .size   _xt_vpri_mask,4
+
+_xt_intenable:     .word   0             /* Virtual INTENABLE     */
+_xt_vpri_mask:     .word   0xFFFFFFFF    /* Virtual priority mask */
+
+
+/*
+-------------------------------------------------------------------------------
+  Table of C-callable interrupt handlers for each interrupt. Note that not all
+  slots can be filled, because interrupts at level > EXCM_LEVEL will not be
+  dispatched to a C handler by default.
+-------------------------------------------------------------------------------
+*/
+
+    .data
+    .global _xt_interrupt_table
+    .align  8
+
+_xt_interrupt_table:
+
+    .set    i, 0
+    .rept   XCHAL_NUM_INTERRUPTS
+    .word   xt_unhandled_interrupt      /* handler address               */
+    .word   i                           /* handler arg (default: intnum) */
+    .set    i, i+1
+    .endr
+
+#endif /* XCHAL_HAVE_INTERRUPTS */
+
+
+#if XCHAL_HAVE_EXCEPTIONS
+
+/*
+-------------------------------------------------------------------------------
+  Table of C-callable exception handlers for each exception. Note that not all
+  slots will be active, because some exceptions (e.g. coprocessor exceptions)
+  are always handled by the OS and cannot be hooked by user handlers.
+-------------------------------------------------------------------------------
+*/
+
+    .data
+    .global _xt_exception_table
+    .align  4
+
+_xt_exception_table:
+    .rept   XCHAL_EXCCAUSE_NUM
+    .word   xt_unhandled_exception    /* handler address */
+    .endr
+
+#endif
+
+
+/*
+-------------------------------------------------------------------------------
+  unsigned int xt_ints_on ( unsigned int mask )
+
+  Enables a set of interrupts. Does not simply set INTENABLE directly, but
+  computes it as a function of the current virtual priority.
+  Can be called from interrupt handlers.
+-------------------------------------------------------------------------------
+*/
+
+    .text
+    .align  4
+    .global xt_ints_on
+    .type   xt_ints_on,@function
+
+xt_ints_on:
+
+    ENTRY0
+#if XCHAL_HAVE_INTERRUPTS
+    movi    a3, 0
+    movi    a4, _xt_intdata
+    xsr     a3, INTENABLE        /* Disables all interrupts   */
+    rsync
+    l32i    a3, a4, 0            /* a3 = _xt_intenable        */
+    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask        */
+    or      a5, a3, a2           /* a5 = _xt_intenable | mask */
+    s32i    a5, a4, 0            /* _xt_intenable |= mask     */
+    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
+    wsr     a5, INTENABLE        /* Reenable interrupts       */
+    mov     a2, a3               /* Previous mask             */
+#else
+    movi    a2, 0                /* Return zero */
+#endif
+    RET0
+
+    .size   xt_ints_on, . - xt_ints_on
+
+
+/*
+-------------------------------------------------------------------------------
+  unsigned int xt_ints_off ( unsigned int mask )
+
+  Disables a set of interrupts. Does not simply set INTENABLE directly,
+  but computes it as a function of the current virtual priority.
+  Can be called from interrupt handlers.
+-------------------------------------------------------------------------------
+*/
+
+    .text
+    .align  4
+    .global xt_ints_off
+    .type   xt_ints_off,@function
+
+xt_ints_off:
+
+    ENTRY0
+#if XCHAL_HAVE_INTERRUPTS
+    movi    a3, 0
+    movi    a4, _xt_intdata
+    xsr     a3, INTENABLE        /* Disables all interrupts    */
+    rsync
+    l32i    a3, a4, 0            /* a3 = _xt_intenable         */
+    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask         */
+    or      a5, a3, a2           /* a5 = _xt_intenable | mask  */
+    xor     a5, a5, a2           /* a5 = _xt_intenable & ~mask */
+    s32i    a5, a4, 0            /* _xt_intenable &= ~mask     */
+    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
+    wsr     a5, INTENABLE        /* Reenable interrupts        */
+    mov     a2, a3               /* Previous mask              */
+#else
+    movi    a2, 0                /* return zero */
+#endif
+    RET0
+
+    .size   xt_ints_off, . - xt_ints_off
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
new file mode 100644
index 0000000..050b495
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
@@ -0,0 +1,71 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * xtensa_overlay_os_hook.c -- Overlay manager OS hooks for FreeRTOS.
+ */
+
+#include "FreeRTOS.h"
+#include "semphr.h"
+
+#if configUSE_MUTEX
+
+/* Mutex object that controls access to the overlay. Currently only one
+ * overlay region is supported so one mutex suffices.
+ */
+static SemaphoreHandle_t xt_overlay_mutex;
+
+
+/* This function should be overridden to provide OS specific init such
+ * as the creation of a mutex lock that can be used for overlay locking.
+ * Typically this mutex would be set up with priority inheritance. See
+ * overlay manager documentation for more details.
+ */
+void xt_overlay_init_os(void)
+{
+    /* Create the mutex for overlay access. Priority inheritance is
+     * required.
+     */
+    xt_overlay_mutex = xSemaphoreCreateMutex();
+}
+
+
+/* This function locks access to shared overlay resources, typically
+ * by acquiring a mutex.
+ */
+void xt_overlay_lock(void)
+{
+    xSemaphoreTake(xt_overlay_mutex, 0);
+}
+
+
+/* This function releases access to shared overlay resources, typically
+ * by unlocking a mutex.
+ */
+void xt_overlay_unlock(void)
+{
+    xSemaphoreGive(xt_overlay_mutex);
+}
+
+#endif
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
new file mode 100644
index 0000000..207a76c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
@@ -0,0 +1,234 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES
+ *                       (FreeRTOS Port)
+ *
+ * This header is the primary glue between generic Xtensa RTOS support
+ * sources and a specific RTOS port for Xtensa.  It contains definitions
+ * and macros for use primarily by Xtensa assembly coded source files.
+ *
+ * Macros in this header map callouts from generic Xtensa files to specific
+ * RTOS functions. It may also be included in C source files.
+ *
+ * Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa 
+ * architecture, using the Xtensa hardware abstraction layer (HAL) to deal 
+ * with configuration specifics.
+ * 
+ * Should be included by all Xtensa generic and RTOS port-specific sources.
+ */
+
+#ifndef XTENSA_RTOS_H
+#define XTENSA_RTOS_H
+
+#ifdef __ASSEMBLER__
+#include    <xtensa/coreasm.h>
+#else
+#include    <xtensa/config/core.h>
+#endif
+
+#include    <xtensa/corebits.h>
+#include    <xtensa/config/system.h>
+#include    <xtensa/simcall.h>
+
+/*
+Include any RTOS specific definitions that are needed by this header.
+*/
+#include    <FreeRTOSConfig.h>
+
+/*
+Convert FreeRTOSConfig definitions to XTENSA definitions.
+However these can still be overridden from the command line.
+*/
+
+#ifndef XT_SIMULATOR
+  #if configXT_SIMULATOR
+    #define XT_SIMULATOR             1  /* Simulator mode */
+  #endif
+#endif
+
+#ifndef XT_BOARD
+  #if configXT_BOARD
+    #define XT_BOARD                 1  /* Board mode */
+  #endif
+#endif
+
+#ifndef XT_TIMER_INDEX
+  #if defined configXT_TIMER_INDEX
+    #define XT_TIMER_INDEX           configXT_TIMER_INDEX  /* Index of hardware timer to be used */
+  #endif
+#endif
+
+#ifndef XT_INTEXC_HOOKS
+  #if configXT_INTEXC_HOOKS
+    #define XT_INTEXC_HOOKS          1  /* Enables exception hooks */
+  #endif
+#endif
+
+#if (!XT_SIMULATOR) && (!XT_BOARD)
+  #error Either XT_SIMULATOR or XT_BOARD must be defined.
+#endif
+
+
+/*
+Name of RTOS (for messages).
+*/
+#define XT_RTOS_NAME    FreeRTOS
+
+/*
+Check some Xtensa configuration requirements and report error if not met.
+Error messages can be customize to the RTOS port.
+*/
+
+#if !XCHAL_HAVE_XEA2
+#error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."
+#endif
+
+
+/*******************************************************************************
+
+RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
+
+Define callout macros used in generic Xtensa code to interact with the RTOS.
+The macros are simply the function names for use in calls from assembler code.
+Some of these functions may call back to generic functions in xtensa_context.h .
+
+*******************************************************************************/
+
+/*
+Inform RTOS of entry into an interrupt handler that will affect it. 
+Allows RTOS to manage switch to any system stack and count nesting level.
+Called after minimal context has been saved, with interrupts disabled.
+RTOS port can call0 _xt_context_save to save the rest of the context.
+May only be called from assembly code by the 'call0' instruction.
+*/
+// void XT_RTOS_INT_ENTER(void)
+#define XT_RTOS_INT_ENTER   _frxt_int_enter
+
+/*
+Inform RTOS of completion of an interrupt handler, and give control to
+RTOS to perform thread/task scheduling, switch back from any system stack
+and restore the context, and return to the exit dispatcher saved in the
+stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
+to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
+leaving only a minimal part of the context to be restored by the exit
+dispatcher. This function does not return to the place it was called from.
+May only be called from assembly code by the 'call0' instruction.
+*/
+// void XT_RTOS_INT_EXIT(void)
+#define XT_RTOS_INT_EXIT    _frxt_int_exit
+
+/*
+Inform RTOS of the occurrence of a tick timer interrupt.
+If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
+May be coded in or called from C or assembly, per ABI conventions.
+RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
+*/
+// void XT_RTOS_TIMER_INT(void)
+#define XT_RTOS_TIMER_INT   _frxt_timer_int
+#define XT_TICK_PER_SEC     configTICK_RATE_HZ
+
+/*
+Return in a15 the base address of the co-processor state save area for the 
+thread that triggered a co-processor exception, or 0 if no thread was running.
+The state save area is structured as defined in xtensa_context.h and has size 
+XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
+in interrupt handlers or the RTOS kernel. May only be called from assembly code
+and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. 
+The implementation may use only a2-4, a15 (all other regs must be preserved).
+*/
+// void* XT_RTOS_CP_STATE(void)
+#define XT_RTOS_CP_STATE    _frxt_task_coproc_state
+
+
+/*******************************************************************************
+
+HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
+
+This Xtensa RTOS port provides hooks for dynamically installing exception
+and interrupt handlers to facilitate automated testing where each test
+case can install its own handler for user exceptions and each interrupt
+priority (level). This consists of an array of function pointers indexed
+by interrupt priority, with index 0 being the user exception handler hook.
+Each entry in the array is initially 0, and may be replaced by a function 
+pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
+
+The handler for low and medium priority obeys ABI conventions so may be coded
+in C. For the exception handler, the cause is the contents of the EXCCAUSE
+reg, and the result is -1 if handled, else the cause (still needs handling).
+For interrupt handlers, the cause is a mask of pending enabled interrupts at
+that level, and the result is the same mask with the bits for the handled
+interrupts cleared (those not cleared still need handling). This allows a test
+case to either pre-handle or override the default handling for the exception
+or interrupt level (see xtensa_vectors.S).
+
+High priority handlers (including NMI) must be coded in assembly, are always
+called by 'call0' regardless of ABI, must preserve all registers except a0,
+and must not use or modify the interrupted stack. The hook argument 'cause'
+is not passed and the result is ignored, so as not to burden the caller with
+saving and restoring a2 (it assumes only one interrupt per level - see the
+discussion in high priority interrupts in xtensa_vectors.S). The handler
+therefore should be coded to prototype 'void h(void)' even though it plugs
+into an array of handlers of prototype 'unsigned h(unsigned)'.
+
+To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
+
+*******************************************************************************/
+
+#define XT_INTEXC_HOOK_NUM  (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)
+
+#ifndef __ASSEMBLER__
+typedef unsigned (*XT_INTEXC_HOOK)(unsigned cause);
+extern  volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
+#endif
+
+
+/*******************************************************************************
+
+CONVENIENCE INCLUSIONS.
+
+Ensures RTOS specific files need only include this one Xtensa-generic header.
+These headers are included last so they can use the RTOS definitions above.
+
+*******************************************************************************/
+
+#include    "xtensa_context.h"
+
+#ifdef XT_RTOS_TIMER_INT
+#include    "xtensa_timer.h"
+#endif
+
+
+/*******************************************************************************
+
+Xtensa Port Version.
+
+*******************************************************************************/
+
+#define XTENSA_PORT_VERSION             1.7
+#define XTENSA_PORT_VERSION_STRING      "1.7"
+
+#endif /* XTENSA_RTOS_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
new file mode 100644
index 0000000..7d7acaa
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
@@ -0,0 +1,160 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+ * XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
+ *
+ * This header contains definitions and macros for use primarily by Xtensa
+ * RTOS assembly coded source files. It includes and uses the Xtensa hardware
+ * abstraction layer (HAL) to deal with config specifics. It may also be
+ * included in C source files.
+ *
+ * Edit this file to modify timer selection and to specify clock frequency and
+ * tick duration to match timer interrupt to the real-time tick duration.
+ *
+ * If the RTOS has no timer interrupt, then there is no tick timer and the
+ * clock frequency is irrelevant, so all of these macros are left undefined
+ * and the Xtensa core configuration need not have a timer.
+ */
+
+#ifndef XTENSA_TIMER_H
+#define XTENSA_TIMER_H
+
+#ifdef __ASSEMBLER__
+#include    <xtensa/coreasm.h>
+#endif
+
+#include    <xtensa/corebits.h>
+#include    <xtensa/config/system.h>
+
+#include    "xtensa_rtos.h"     /* in case this wasn't included directly */
+
+#include    <FreeRTOSConfig.h>
+
+/*
+Select timer to use for periodic tick, and determine its interrupt number 
+and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
+in which case its validity is checked (it must exist in this core and must 
+not be on a high priority interrupt - an error will be reported in invalid).
+Otherwise select the first low or medium priority interrupt timer available.
+*/
+#if XCHAL_NUM_TIMERS == 0
+
+  #error "This Xtensa configuration is unsupported, it has no timers."
+
+#else
+
+#ifndef XT_TIMER_INDEX
+  #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    3
+    #endif
+  #endif
+  #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    2
+    #endif
+  #endif
+  #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    1
+    #endif
+  #endif
+  #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
+    #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
+      #undef  XT_TIMER_INDEX
+      #define XT_TIMER_INDEX    0
+    #endif
+  #endif
+#endif
+#ifndef XT_TIMER_INDEX
+  #error "There is no suitable timer in this Xtensa configuration."
+#endif
+
+#define XT_CCOMPARE             (CCOMPARE + XT_TIMER_INDEX)
+#define XT_TIMER_INTNUM         XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)
+#define XT_TIMER_INTPRI         XCHAL_INT_LEVEL(XT_TIMER_INTNUM)
+#define XT_TIMER_INTEN          (1 << XT_TIMER_INTNUM)
+
+#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
+  #error "The timer selected by XT_TIMER_INDEX does not exist in this core."
+#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
+  #error "The timer interrupt cannot be high priority (use medium or low)."
+#endif
+
+#endif /* XCHAL_NUM_TIMERS */
+
+/*
+Set processor clock frequency, used to determine clock divisor for timer tick.
+User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
+If using a supported board via the board-independent API defined in xtbsp.h,
+this may be left undefined and frequency and tick divisor will be computed 
+and cached during run-time initialization.
+
+NOTE ON SIMULATOR:
+Under the Xtensa instruction set simulator, the frequency can only be estimated 
+because it depends on the speed of the host and the version of the simulator.
+Also because it runs much slower than hardware, it is not possible to achieve
+real-time performance for most applications under the simulator. A frequency
+too low does not allow enough time between timer interrupts, starving threads.
+To obtain a more convenient but non-real-time tick duration on the simulator, 
+compile with xt-xcc option "-DXT_SIMULATOR".
+Adjust this frequency to taste (it's not real-time anyway!).
+*/
+#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
+#define XT_CLOCK_FREQ       configCPU_CLOCK_HZ
+#endif
+
+#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
+  #error "XT_CLOCK_FREQ must be defined for the target platform."
+#endif
+
+/*
+Default number of timer "ticks" per second (default 100 for 10ms tick).
+RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
+User may redefine this to an optimal value for the application, either by
+editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
+"-DXT_TICK_PER_SEC=<value>" where <value> is a suitable number.
+*/
+#ifndef XT_TICK_PER_SEC
+#define XT_TICK_PER_SEC    configTICK_RATE_HZ        /* 10 ms tick = 100 ticks per second */
+#endif
+
+/*
+Derivation of clock divisor for timer tick and interrupt (one per tick).
+*/
+#ifdef XT_CLOCK_FREQ
+#define XT_TICK_DIVISOR     (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
+#endif
+
+#ifndef __ASSEMBLER__
+extern unsigned _xt_tick_divisor;
+extern void     _xt_tick_divisor_init(void);
+#endif
+
+#endif  /* XTENSA_TIMER_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S
new file mode 100644
index 0000000..224ac87
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S
@@ -0,0 +1,1905 @@
+
+/*
+ * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sublicense, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/*
+        XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS
+
+  Xtensa low level exception and interrupt vectors and handlers for an RTOS.
+
+  Interrupt handlers and user exception handlers support interaction with
+  the RTOS by calling XT_RTOS_INT_ENTER and XT_RTOS_INT_EXIT before and
+  after user's specific interrupt handlers. These macros are defined in
+  xtensa_<rtos>.h to call suitable functions in a specific RTOS.
+
+  Users can install application-specific interrupt handlers for low and
+  medium level interrupts, by calling xt_set_interrupt_handler(). These
+  handlers can be written in C, and must obey C calling convention. The
+  handler table is indexed by the interrupt number. Each handler may be
+  provided with an argument. 
+
+  Note that the system timer interrupt is handled specially, and is
+  dispatched to the RTOS-specific handler. This timer cannot be hooked
+  by application code.
+
+  Optional hooks are also provided to install a handler per level at 
+  run-time, made available by compiling this source file with 
+  '-DXT_INTEXC_HOOKS' (useful for automated testing).
+
+!!  This file is a template that usually needs to be modified to handle       !!
+!!  application specific interrupts. Search USER_EDIT for helpful comments    !!
+!!  on where to insert handlers and how to write them.                        !!
+
+  Users can also install application-specific exception handlers in the
+  same way, by calling xt_set_exception_handler(). One handler slot is
+  provided for each exception type. Note that some exceptions are handled
+  by the porting layer itself, and cannot be taken over by application
+  code in this manner. These are the alloca, syscall, and coprocessor
+  exceptions.
+
+  The exception handlers can be written in C, and must follow C calling
+  convention. Each handler is passed a pointer to an exception frame as
+  its single argument. The exception frame is created on the stack, and
+  holds the saved context of the thread that took the exception. If the
+  handler returns, the context will be restored and the instruction that
+  caused the exception will be retried. If the handler makes any changes
+  to the saved state in the exception frame, the changes will be applied
+  when restoring the context.
+
+  Because Xtensa is a configurable architecture, this port supports all user
+  generated configurations (except restrictions stated in the release notes).
+  This is accomplished by conditional compilation using macros and functions
+  defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
+  Only the relevant parts of this file will be included in your RTOS build.
+  For example, this file provides interrupt vector templates for all types and
+  all priority levels, but only the ones in your configuration are built.
+
+  NOTES on the use of 'call0' for long jumps instead of 'j':
+   1. This file should be assembled with the -mlongcalls option to xt-xcc.
+   2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to
+      a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the
+      distance from the call to the destination. The linker then relaxes
+      it back to 'call0 dest' if it determines that dest is within range.
+      This allows more flexibility in locating code without the performance
+      overhead of the 'l32r' literal data load in cases where the destination
+      is in range of 'call0'. There is an additional benefit in that 'call0'
+      has a longer range than 'j' due to the target being word-aligned, so 
+      the 'l32r' sequence is less likely needed.
+   3. The use of 'call0' with -mlongcalls requires that register a0 not be 
+      live at the time of the call, which is always the case for a function 
+      call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'.
+   4. This use of 'call0' is independent of the C function call ABI.
+
+ */
+
+#include "xtensa_rtos.h"
+
+
+/* Enable stack backtrace across exception/interrupt - see below */
+#define XT_DEBUG_BACKTRACE    1
+
+
+/*
+--------------------------------------------------------------------------------
+  Defines used to access _xtos_interrupt_table.
+--------------------------------------------------------------------------------
+*/
+#define XIE_HANDLER     0
+#define XIE_ARG         4
+#define XIE_SIZE        8
+
+/*
+--------------------------------------------------------------------------------
+  Macro extract_msb - return the input with only the highest bit set.
+
+  Input  : "ain"  - Input value, clobbered.
+  Output : "aout" - Output value, has only one bit set, MSB of "ain".
+  The two arguments must be different AR registers.
+--------------------------------------------------------------------------------
+*/
+
+    .macro  extract_msb     aout ain
+1:
+    addi    \aout, \ain, -1         /* aout = ain - 1        */
+    and     \ain, \ain, \aout       /* ain  = ain & aout     */
+    bnez    \ain, 1b                /* repeat until ain == 0 */
+    addi    \aout, \aout, 1         /* return aout + 1       */
+    .endm
+
+/*
+--------------------------------------------------------------------------------
+  Macro dispatch_c_isr - dispatch interrupts to user ISRs.
+  This will dispatch to user handlers (if any) that are registered in the
+  XTOS dispatch table (_xtos_interrupt_table). These handlers would have
+  been registered by calling _xtos_set_interrupt_handler(). There is one
+  exception - the timer interrupt used by the OS will not be dispatched
+  to a user handler - this must be handled by the caller of this macro.
+
+  Level triggered and software interrupts are automatically deasserted by
+  this code.
+
+  ASSUMPTIONS:
+    -- PS.INTLEVEL is set to "level" at entry
+    -- PS.EXCM = 0, C calling enabled
+
+  NOTE: For CALL0 ABI, a12-a15 have not yet been saved.
+
+  NOTE: This macro will use registers a0 and a2-a6. The arguments are:
+    level -- interrupt level
+    mask  -- interrupt bitmask for this level
+--------------------------------------------------------------------------------
+*/
+
+    .macro  dispatch_c_isr    level  mask
+
+    /* Get mask of pending, enabled interrupts at this level into a2. */
+
+.L_xt_user_int_&level&:
+    rsr     a2, INTENABLE
+    rsr     a3, INTERRUPT
+    movi    a4, \mask
+    and     a2, a2, a3
+    and     a2, a2, a4
+    beqz    a2, 9f                          /* nothing to do */
+
+    /* This bit of code provides a nice debug backtrace in the debugger.
+       It does take a few more instructions, so undef XT_DEBUG_BACKTRACE
+       if you want to save the cycles.
+    */
+    #if XT_DEBUG_BACKTRACE
+    #ifndef __XTENSA_CALL0_ABI__
+    rsr     a0, EPC_1 + \level - 1          /* return address */
+    movi    a4, 0xC0000000                  /* constant with top 2 bits set (call size) */
+    or      a0, a0, a4                      /* set top 2 bits */
+    addx2   a0, a4, a0                      /* clear top bit -- simulating call4 size   */
+    #endif
+    #endif
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a4, _xt_intexc_hooks
+    l32i    a4, a4, \level << 2
+    beqz    a4, 2f
+    #ifdef __XTENSA_CALL0_ABI__
+    callx0  a4
+    beqz    a2, 9f
+    #else
+    mov     a6, a2
+    callx4  a4
+    beqz    a6, 9f
+    mov     a2, a6
+    #endif
+2:
+    #endif
+
+    /* Now look up in the dispatch table and call user ISR if any. */
+    /* If multiple bits are set then MSB has highest priority.     */
+
+    extract_msb  a4, a2                     /* a4 = MSB of a2, a2 trashed */
+
+    #ifdef XT_USE_SWPRI
+    /* Enable all interrupts at this level that are numerically higher
+       than the one we just selected, since they are treated as higher
+       priority.
+    */
+    movi    a3, \mask                       /* a3 = all interrupts at this level */
+    add     a2, a4, a4                      /* a2 = a4 << 1 */
+    addi    a2, a2, -1                      /* a2 = mask of 1's <= a4 bit */
+    and     a2, a2, a3                      /* a2 = mask of all bits <= a4 at this level */
+    movi    a3, _xt_intdata
+    l32i    a6, a3, 4                       /* a6 = _xt_vpri_mask */
+    neg     a2, a2
+    addi    a2, a2, -1                      /* a2 = mask to apply */
+    and     a5, a6, a2                      /* mask off all bits <= a4 bit */
+    s32i    a5, a3, 4                       /* update _xt_vpri_mask */
+    rsr     a3, INTENABLE
+    and     a3, a3, a2                      /* mask off all bits <= a4 bit */
+    wsr     a3, INTENABLE
+    rsil    a3, \level - 1                  /* lower interrupt level by 1 */
+    #endif
+
+    movi    a3, XT_TIMER_INTEN              /* a3 = timer interrupt bit */
+    wsr     a4, INTCLEAR                    /* clear sw or edge-triggered interrupt */
+    beq     a3, a4, 7f                      /* if timer interrupt then skip table */
+
+    find_ms_setbit a3, a4, a3, 0            /* a3 = interrupt number */
+
+    movi    a4, _xt_interrupt_table
+    addx8   a3, a3, a4                      /* a3 = address of interrupt table entry */
+    l32i    a4, a3, XIE_HANDLER             /* a4 = handler address */
+    #ifdef __XTENSA_CALL0_ABI__
+    mov     a12, a6                         /* save in callee-saved reg */
+    l32i    a2, a3, XIE_ARG                 /* a2 = handler arg */
+    callx0  a4                              /* call handler */
+    mov     a2, a12
+    #else
+    mov     a2, a6                          /* save in windowed reg */
+    l32i    a6, a3, XIE_ARG                 /* a6 = handler arg */
+    callx4  a4                              /* call handler */
+    #endif
+
+    #ifdef XT_USE_SWPRI
+    j       8f
+    #else
+    j       .L_xt_user_int_&level&          /* check for more interrupts */
+    #endif
+
+7:
+
+    .ifeq XT_TIMER_INTPRI - \level
+.L_xt_user_int_timer_&level&:
+    /*
+    Interrupt handler for the RTOS tick timer if at this level.
+    We'll be reading the interrupt state again after this call
+    so no need to preserve any registers except a6 (vpri_mask).
+    */
+
+    #ifdef __XTENSA_CALL0_ABI__
+    mov     a12, a6
+    call0   XT_RTOS_TIMER_INT
+    mov     a2, a12
+    #else
+    mov     a2, a6
+    call4   XT_RTOS_TIMER_INT
+    #endif
+    .endif
+
+    #ifdef XT_USE_SWPRI
+    j       8f
+    #else
+    j       .L_xt_user_int_&level&          /* check for more interrupts */
+    #endif
+
+    #ifdef XT_USE_SWPRI
+8:
+    /* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from
+       virtual _xt_intenable which _could_ have changed during interrupt
+       processing. */
+
+    movi    a3, _xt_intdata
+    l32i    a4, a3, 0                       /* a4 = _xt_intenable    */
+    s32i    a2, a3, 4                       /* update _xt_vpri_mask  */
+    and     a4, a4, a2                      /* a4 = masked intenable */
+    wsr     a4, INTENABLE                   /* update INTENABLE      */
+    #endif
+
+9:
+    /* done */
+
+    .endm
+
+
+/*
+--------------------------------------------------------------------------------
+  Panic handler.
+  Should be reached by call0 (preferable) or jump only. If call0, a0 says where 
+  from. If on simulator, display panic message and abort, else loop indefinitely.
+--------------------------------------------------------------------------------
+*/
+
+    .text
+    .global     _xt_panic
+    .type       _xt_panic,@function
+    .align      4
+
+_xt_panic:
+    #ifdef XT_SIMULATOR
+    addi    a4, a0, -3                      /* point to call0 */
+    movi    a3, _xt_panic_message
+    movi    a2, SYS_log_msg
+    simcall
+    movi    a2, SYS_gdb_abort
+    simcall
+    #else
+    rsil    a2, XCHAL_EXCM_LEVEL            /* disable all low & med ints */
+1:  j       1b                              /* loop infinitely */
+    #endif
+
+    .section    .rodata, "a"
+    .align      4
+
+_xt_panic_message:
+    .string "\n*** _xt_panic() was called from 0x%08x or jumped to. ***\n"
+
+
+/*
+--------------------------------------------------------------------------------
+    Hooks to dynamically install handlers for exceptions and interrupts.
+    Allows automated regression frameworks to install handlers per test.
+    Consists of an array of function pointers indexed by interrupt level, 
+    with index 0 containing the entry for user exceptions.
+    Initialized with all 0s, meaning no handler is installed at each level.
+    See comment in xtensa_rtos.h for more details.
+--------------------------------------------------------------------------------
+*/
+
+    #ifdef XT_INTEXC_HOOKS
+    .data
+    .global     _xt_intexc_hooks
+    .type       _xt_intexc_hooks,@object
+    .align      4
+
+_xt_intexc_hooks:
+    .fill       XT_INTEXC_HOOK_NUM, 4, 0
+    #endif
+
+
+/*
+--------------------------------------------------------------------------------
+  EXCEPTION AND LEVEL 1 INTERRUPT VECTORS AND LOW LEVEL HANDLERS
+  (except window exception vectors).
+
+  Each vector goes at a predetermined location according to the Xtensa
+  hardware configuration, which is ensured by its placement in a special
+  section known to the Xtensa linker support package (LSP). It performs
+  the minimum necessary before jumping to the handler in the .text section.
+
+  The corresponding handler goes in the normal .text section. It sets up
+  the appropriate stack frame, saves a few vector-specific registers and
+  calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
+  and enter the RTOS, then sets up a C environment. It then calls the
+  user's interrupt handler code (which may be coded in C) and finally 
+  calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
+
+  While XT_RTOS_INT_EXIT does not return directly to the interruptee,
+  eventually the RTOS scheduler will want to dispatch the interrupted
+  task or handler. The scheduler will return to the exit point that was
+  saved in the interrupt stack frame at XT_STK_EXIT.
+--------------------------------------------------------------------------------
+*/
+
+
+/*
+--------------------------------------------------------------------------------
+Debug Exception.
+--------------------------------------------------------------------------------
+*/
+
+#if XCHAL_HAVE_DEBUG
+
+    .begin      literal_prefix .DebugExceptionVector
+    .section    .DebugExceptionVector.text, "ax"
+    .global     _DebugExceptionVector
+    .align      4
+
+_DebugExceptionVector:
+
+    #ifdef XT_SIMULATOR
+    /*
+    In the simulator, let the debugger (if any) handle the debug exception,
+    or simply stop the simulation:
+    */
+    wsr     a2, EXCSAVE+XCHAL_DEBUGLEVEL    /* save a2 where sim expects it */
+    movi    a2, SYS_gdb_enter_sktloop
+    simcall                                 /* have ISS handle debug exc. */
+    #elif 0 /* change condition to 1 to use the HAL minimal debug handler */
+    wsr     a3, EXCSAVE+XCHAL_DEBUGLEVEL
+    movi    a3, xthal_debugexc_defhndlr_nw  /* use default debug handler */
+    jx      a3
+    #else
+    wsr     a0, EXCSAVE+XCHAL_DEBUGLEVEL    /* save original a0 somewhere */
+    call0   _xt_panic                       /* does not return */
+    rfi     XCHAL_DEBUGLEVEL                /* make a0 point here not later */
+    #endif
+
+    .end        literal_prefix
+
+#endif
+
+/*
+--------------------------------------------------------------------------------
+Double Exception.
+Double exceptions are not a normal occurrence. They indicate a bug of some kind.
+--------------------------------------------------------------------------------
+*/
+
+#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
+
+    .begin      literal_prefix .DoubleExceptionVector
+    .section    .DoubleExceptionVector.text, "ax"
+    .global     _DoubleExceptionVector
+    .align      4
+
+_DoubleExceptionVector:
+
+    #if XCHAL_HAVE_DEBUG
+    break   1, 4                            /* unhandled double exception */
+    #endif
+    call0   _xt_panic                       /* does not return */
+    rfde                                    /* make a0 point here not later */
+
+    .end        literal_prefix
+
+#endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */
+
+/*
+--------------------------------------------------------------------------------
+Kernel Exception (including Level 1 Interrupt from kernel mode).
+--------------------------------------------------------------------------------
+*/
+
+    .begin      literal_prefix .KernelExceptionVector
+    .section    .KernelExceptionVector.text, "ax"
+    .global     _KernelExceptionVector
+    .align      4
+
+_KernelExceptionVector:
+
+    wsr     a0, EXCSAVE_1                   /* preserve a0 */
+    call0   _xt_kernel_exc                  /* kernel exception handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .align      4
+
+_xt_kernel_exc:
+    #if XCHAL_HAVE_DEBUG
+    break   1, 0                            /* unhandled kernel exception */
+    #endif
+    call0   _xt_panic                       /* does not return */
+    rfe                                     /* make a0 point here not there */
+
+
+/*
+--------------------------------------------------------------------------------
+User Exception (including Level 1 Interrupt from user mode).
+--------------------------------------------------------------------------------
+*/
+
+    .begin      literal_prefix .UserExceptionVector
+    .section    .UserExceptionVector.text, "ax"
+    .global     _UserExceptionVector
+    .type       _UserExceptionVector,@function
+    .align      4
+
+_UserExceptionVector:
+
+    wsr     a0, EXCSAVE_1                   /* preserve a0 */
+    call0   _xt_user_exc                    /* user exception handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+/*
+--------------------------------------------------------------------------------
+  Insert some waypoints for jumping beyond the signed 8-bit range of
+  conditional branch instructions, so the conditional branchces to specific
+  exception handlers are not taken in the mainline. Saves some cycles in the
+  mainline.
+--------------------------------------------------------------------------------
+*/
+
+    .text
+
+    #if XCHAL_HAVE_WINDOWED
+    .align      4
+_xt_to_alloca_exc:
+    call0   _xt_alloca_exc                  /* in window vectors section */
+    /* never returns here - call0 is used as a jump (see note at top) */
+    #endif
+
+    .align      4
+_xt_to_syscall_exc:
+    call0   _xt_syscall_exc
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    #if XCHAL_CP_NUM > 0
+    .align      4
+_xt_to_coproc_exc:
+    call0   _xt_coproc_exc
+    /* never returns here - call0 is used as a jump (see note at top) */
+    #endif
+
+
+/*
+--------------------------------------------------------------------------------
+  User exception handler.
+--------------------------------------------------------------------------------
+*/
+
+    .type       _xt_user_exc,@function
+    .align      4
+
+_xt_user_exc:
+
+    /* If level 1 interrupt then jump to the dispatcher */
+    rsr     a0, EXCCAUSE
+    beqi    a0, EXCCAUSE_LEVEL1INTERRUPT, _xt_lowint1
+
+    /* Handle any coprocessor exceptions. Rely on the fact that exception
+       numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors.
+    */
+    #if XCHAL_CP_NUM > 0
+    bgeui   a0, EXCCAUSE_CP0_DISABLED, _xt_to_coproc_exc
+    #endif
+
+    /* Handle alloca and syscall exceptions */
+    #if XCHAL_HAVE_WINDOWED
+    beqi    a0, EXCCAUSE_ALLOCA,  _xt_to_alloca_exc
+    #endif
+    beqi    a0, EXCCAUSE_SYSCALL, _xt_to_syscall_exc
+
+    /* Handle all other exceptions. All can have user-defined handlers. */
+    /* NOTE: we'll stay on the user stack for exception handling.       */
+
+    /* Allocate exception frame and save minimal context. */
+    mov     a0, sp
+    addi    sp, sp, -XT_STK_FRMSZ
+    s32i    a0, sp, XT_STK_A1
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -12                     /* for debug backtrace */
+    #endif
+    rsr     a0, PS                          /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_1                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -16                     /* for debug backtrace */
+    #endif
+    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
+    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
+    call0   _xt_context_save
+
+    /* Save exc cause and vaddr into exception frame */
+    rsr     a0, EXCCAUSE
+    s32i    a0, sp, XT_STK_EXCCAUSE
+    rsr     a0, EXCVADDR
+    s32i    a0, sp, XT_STK_EXCVADDR
+
+    /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+
+    #ifdef XT_DEBUG_BACKTRACE
+    #ifndef __XTENSA_CALL0_ABI__
+    rsr     a0, EPC_1                       /* return address for debug backtrace */
+    movi    a5, 0xC0000000                  /* constant with top 2 bits set (call size) */
+    rsync                                   /* wait for WSR.PS to complete */
+    or      a0, a0, a5                      /* set top 2 bits */
+    addx2   a0, a5, a0                      /* clear top bit -- thus simulating call4 size */
+    #else
+    rsync                                   /* wait for WSR.PS to complete */
+    #endif
+    #endif
+
+    rsr     a2, EXCCAUSE                    /* recover exc cause */
+
+    #ifdef XT_INTEXC_HOOKS
+    /*
+    Call exception hook to pre-handle exceptions (if installed).
+    Pass EXCCAUSE in a2, and check result in a2 (if -1, skip default handling).
+    */
+    movi    a4, _xt_intexc_hooks
+    l32i    a4, a4, 0                       /* user exception hook index 0 */
+    beqz    a4, 1f
+.Ln_xt_user_exc_call_hook:
+    #ifdef __XTENSA_CALL0_ABI__
+    callx0  a4
+    beqi    a2, -1, .L_xt_user_done
+    #else
+    mov     a6, a2
+    callx4  a4
+    beqi    a6, -1, .L_xt_user_done
+    mov     a2, a6
+    #endif
+1:
+    #endif
+
+    rsr     a2, EXCCAUSE                    /* recover exc cause */
+    movi    a3, _xt_exception_table
+    addx4   a4, a2, a3                      /* a4 = address of exception table entry */
+    l32i    a4, a4, 0                       /* a4 = handler address */
+    #ifdef __XTENSA_CALL0_ABI__
+    mov     a2, sp                          /* a2 = pointer to exc frame */
+    callx0  a4                              /* call handler */
+    #else
+    mov     a6, sp                          /* a6 = pointer to exc frame */
+    callx4  a4                              /* call handler */
+    #endif
+
+.L_xt_user_done:
+
+    /* Restore context and return */
+    call0   _xt_context_restore
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, PS
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_1
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove exception frame */
+    rsync                                   /* ensure PS and EPC written */
+    rfe                                     /* PS.EXCM is cleared */
+
+
+/*
+--------------------------------------------------------------------------------
+  Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+  on entry and used to return to a thread or interrupted interrupt handler.
+--------------------------------------------------------------------------------
+*/
+
+    .global     _xt_user_exit
+    .type       _xt_user_exit,@function
+    .align      4
+_xt_user_exit:
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, PS
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_1
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure PS and EPC written */
+    rfe                                     /* PS.EXCM is cleared */
+
+
+/*
+--------------------------------------------------------------------------------
+Syscall Exception Handler (jumped to from User Exception Handler).
+Syscall 0 is required to spill the register windows (no-op in Call 0 ABI).
+Only syscall 0 is handled here. Other syscalls return -1 to caller in a2.
+--------------------------------------------------------------------------------
+*/
+
+    .text
+    .type       _xt_syscall_exc,@function
+    .align      4
+_xt_syscall_exc:
+
+    #ifdef __XTENSA_CALL0_ABI__
+    /*
+    Save minimal regs for scratch. Syscall 0 does nothing in Call0 ABI.
+    Use a minimal stack frame (16B) to save A2 & A3 for scratch.
+    PS.EXCM could be cleared here, but unlikely to improve worst-case latency.
+    rsr     a0, PS
+    addi    a0, a0, -PS_EXCM_MASK
+    wsr     a0, PS
+    */
+    addi    sp, sp, -16
+    s32i    a2, sp, 8
+    s32i    a3, sp, 12
+    #else   /* Windowed ABI */
+    /*
+    Save necessary context and spill the register windows.
+    PS.EXCM is still set and must remain set until after the spill.
+    Reuse context save function though it saves more than necessary.
+    For this reason, a full interrupt stack frame is allocated.
+    */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
+    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
+    call0   _xt_context_save
+    #endif
+
+    /*
+    Grab the interruptee's PC and skip over the 'syscall' instruction.
+    If it's at the end of a zero-overhead loop and it's not on the last
+    iteration, decrement loop counter and skip to beginning of loop.
+    */
+    rsr     a2, EPC_1                       /* a2 = PC of 'syscall' */
+    addi    a3, a2, 3                       /* ++PC                 */
+    #if XCHAL_HAVE_LOOPS
+    rsr     a0, LEND                        /* if (PC == LEND       */
+    bne     a3, a0, 1f
+    rsr     a0, LCOUNT                      /*     && LCOUNT != 0)  */
+    beqz    a0, 1f                          /* {                    */
+    addi    a0, a0, -1                      /*   --LCOUNT           */
+    rsr     a3, LBEG                        /*   PC = LBEG          */
+    wsr     a0, LCOUNT                      /* }                    */
+    #endif
+1:  wsr     a3, EPC_1                       /* update PC            */
+
+    /* Restore interruptee's context and return from exception. */
+    #ifdef __XTENSA_CALL0_ABI__
+    l32i    a2, sp, 8
+    l32i    a3, sp, 12
+    addi    sp, sp, 16
+    #else
+    call0   _xt_context_restore
+    addi    sp, sp, XT_STK_FRMSZ
+    #endif
+    movi    a0, -1
+    movnez  a2, a0, a2                      /* return -1 if not syscall 0 */
+    rsr     a0, EXCSAVE_1
+    rfe
+
+/*
+--------------------------------------------------------------------------------
+Co-Processor Exception Handler (jumped to from User Exception Handler).
+These exceptions are generated by co-processor instructions, which are only
+allowed in thread code (not in interrupts or kernel code). This restriction is 
+deliberately imposed to reduce the burden of state-save/restore in interrupts.
+--------------------------------------------------------------------------------
+*/
+#if XCHAL_CP_NUM > 0
+
+    .section .rodata, "a"
+
+/* Offset to CP n save area in thread's CP save area. */
+    .global _xt_coproc_sa_offset
+    .type   _xt_coproc_sa_offset,@object
+    .align  16                      /* minimize crossing cache boundaries */
+_xt_coproc_sa_offset:
+    .word   XT_CP0_SA, XT_CP1_SA, XT_CP2_SA, XT_CP3_SA
+    .word   XT_CP4_SA, XT_CP5_SA, XT_CP6_SA, XT_CP7_SA
+
+/* Bitmask for CP n's CPENABLE bit. */
+    .type   _xt_coproc_mask,@object
+    .align  16,,8                   /* try to keep it all in one cache line */
+    .set    i, 0
+_xt_coproc_mask:
+    .rept   XCHAL_CP_MAX
+    .long   (i<<16) | (1<<i)    // upper 16-bits = i, lower = bitmask
+    .set    i, i+1
+    .endr
+
+    .data
+
+/* Owner thread of CP n, identified by thread's CP save area (0 = unowned). */
+    .global _xt_coproc_owner_sa
+    .type   _xt_coproc_owner_sa,@object
+    .align  16,,XCHAL_CP_MAX<<2     /* minimize crossing cache boundaries */
+_xt_coproc_owner_sa:
+    .space  XCHAL_CP_MAX << 2
+
+    .text
+
+
+    .align  4
+.L_goto_invalid:
+    j   .L_xt_coproc_invalid    /* not in a thread (invalid) */
+    .align  4
+.L_goto_done:
+    j   .L_xt_coproc_done
+
+
+/*
+--------------------------------------------------------------------------------
+  Coprocessor exception handler.
+  At entry, only a0 has been saved (in EXCSAVE_1).
+--------------------------------------------------------------------------------
+*/
+
+    .type   _xt_coproc_exc,@function
+    .align  4
+
+_xt_coproc_exc:
+
+    /* Allocate interrupt stack frame and save minimal context. */
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -12                     /* for debug backtrace */
+    #endif
+    rsr     a0, PS                          /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_1                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    #if XCHAL_HAVE_WINDOWED
+    s32e    a0, sp, -16                     /* for debug backtrace */
+    #endif
+    movi    a0, _xt_user_exit               /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    rsr     a0, EXCCAUSE
+    s32i    a5, sp, XT_STK_A5               /* save a5 */
+    addi    a5, a0, -EXCCAUSE_CP0_DISABLED  /* a5 = CP index */
+
+    /* Save a few more of interruptee's registers (a5 was already saved). */
+    s32i    a2,  sp, XT_STK_A2
+    s32i    a3,  sp, XT_STK_A3
+    s32i    a4,  sp, XT_STK_A4
+    s32i    a15, sp, XT_STK_A15
+
+    /* Get co-processor state save area of new owner thread. */
+    call0   XT_RTOS_CP_STATE                /* a15 = new owner's save area */
+    beqz    a15, .L_goto_invalid            /* not in a thread (invalid) */
+
+    /* Enable the co-processor's bit in CPENABLE. */
+    movi    a0, _xt_coproc_mask
+    rsr     a4, CPENABLE                    /* a4 = CPENABLE */
+    addx4   a0, a5, a0                      /* a0 = &_xt_coproc_mask[n] */
+    l32i    a0, a0, 0                       /* a0 = (n << 16) | (1 << n) */
+    movi    a3, _xt_coproc_owner_sa     /* (placed here for load slot) */
+    extui   a2, a0, 0, 16                   /* coprocessor bitmask portion */
+    or      a4, a4, a2                      /* a4 = CPENABLE | (1 << n) */
+    wsr     a4, CPENABLE
+
+    /* Get old coprocessor owner thread (save area ptr) and assign new one.  */
+    addx4   a3,  a5, a3                      /* a3 = &_xt_coproc_owner_sa[n] */
+    l32i    a2,  a3, 0                       /* a2 = old owner's save area */
+    s32i    a15, a3, 0                       /* _xt_coproc_owner_sa[n] = new */
+    rsync                                    /* ensure wsr.CPENABLE is complete */
+
+    /* Only need to context switch if new owner != old owner. */
+    beq     a15, a2, .L_goto_done           /* new owner == old, we're done */
+
+    /* If no old owner then nothing to save. */
+    beqz    a2, .L_check_new
+
+    /* If old owner not actively using CP then nothing to save. */
+    l16ui   a4,  a2,  XT_CPENABLE           /* a4 = old owner's CPENABLE */
+    bnone   a4,  a0,  .L_check_new          /* old owner not using CP    */
+
+.L_save_old:
+    /* Save old owner's coprocessor state. */
+
+    movi    a5, _xt_coproc_sa_offset
+
+    /* Mark old owner state as no longer active (CPENABLE bit n clear). */
+    xor     a4,  a4,  a0                    /* clear CP bit in CPENABLE    */
+    s16i    a4,  a2,  XT_CPENABLE           /* update old owner's CPENABLE */
+
+    extui   a4,  a0,  16,  5                /* a4 = CP index = n */
+    addx4   a5,  a4,  a5                    /* a5 = &_xt_coproc_sa_offset[n] */
+
+    /* Mark old owner state as saved (CPSTORED bit n set). */
+    l16ui   a4,  a2,  XT_CPSTORED           /* a4 = old owner's CPSTORED */
+    l32i    a5,  a5,  0                     /* a5 = XT_CP[n]_SA offset */
+    or      a4,  a4,  a0                    /* set CP in old owner's CPSTORED */
+    s16i    a4,  a2,  XT_CPSTORED           /* update old owner's CPSTORED */
+    l32i    a2, a2, XT_CP_ASA               /* ptr to actual (aligned) save area */
+    extui   a3, a0, 16, 5                   /* a3 = CP index = n */
+    add     a2, a2, a5                      /* a2 = old owner's area for CP n */
+
+    /*
+    The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
+    It is theoretically possible for Xtensa processor designers to write TIE 
+    that causes more address registers to be affected, but it is generally 
+    unlikely. If that ever happens, more registers needs to be saved/restored
+    around this macro invocation, and the value in a15 needs to be recomputed.
+    */
+    xchal_cpi_store_funcbody
+
+.L_check_new:
+    /* Check if any state has to be restored for new owner. */
+    /* NOTE: a15 = new owner's save area, cannot be zero when we get here. */
+
+    l16ui   a3,  a15, XT_CPSTORED           /* a3 = new owner's CPSTORED */
+    movi    a4, _xt_coproc_sa_offset
+    bnone   a3,  a0,  .L_check_cs           /* full CP not saved, check callee-saved */
+    xor     a3,  a3,  a0                    /* CPSTORED bit is set, clear it */
+    s16i    a3,  a15, XT_CPSTORED           /* update new owner's CPSTORED */
+
+    /* Adjust new owner's save area pointers to area for CP n. */
+    extui   a3,  a0, 16, 5                  /* a3 = CP index = n */
+    addx4   a4,  a3, a4                     /* a4 = &_xt_coproc_sa_offset[n] */
+    l32i    a4,  a4, 0                      /* a4 = XT_CP[n]_SA */
+    l32i    a5, a15, XT_CP_ASA              /* ptr to actual (aligned) save area */
+    add     a2,  a4, a5                     /* a2 = new owner's area for CP */
+
+    /*
+    The config-specific HAL macro invoked below destroys a2-5, preserves a0-1.
+    It is theoretically possible for Xtensa processor designers to write TIE 
+    that causes more address registers to be affected, but it is generally 
+    unlikely. If that ever happens, more registers needs to be saved/restored
+    around this macro invocation.
+    */
+    xchal_cpi_load_funcbody
+
+    /* Restore interruptee's saved registers. */
+    /* Can omit rsync for wsr.CPENABLE here because _xt_user_exit does it. */
+.L_xt_coproc_done:
+    l32i    a15, sp, XT_STK_A15
+    l32i    a5,  sp, XT_STK_A5
+    l32i    a4,  sp, XT_STK_A4
+    l32i    a3,  sp, XT_STK_A3
+    l32i    a2,  sp, XT_STK_A2
+    call0   _xt_user_exit                   /* return via exit dispatcher */
+    /* Never returns here - call0 is used as a jump (see note at top) */
+
+.L_check_cs:
+    /* a0 = CP mask in low bits, a15 = new owner's save area */
+    l16ui   a2, a15, XT_CP_CS_ST            /* a2 = mask of CPs saved    */
+    bnone   a2,  a0, .L_xt_coproc_done      /* if no match then done     */
+    and     a2,  a2, a0                     /* a2 = which CPs to restore */
+    extui   a2,  a2, 0, 8                   /* extract low 8 bits        */
+    s32i    a6,  sp, XT_STK_A6              /* save extra needed regs    */
+    s32i    a7,  sp, XT_STK_A7
+    s32i    a13, sp, XT_STK_A13
+    s32i    a14, sp, XT_STK_A14
+    call0   _xt_coproc_restorecs            /* restore CP registers      */
+    l32i    a6,  sp, XT_STK_A6              /* restore saved registers   */
+    l32i    a7,  sp, XT_STK_A7
+    l32i    a13, sp, XT_STK_A13
+    l32i    a14, sp, XT_STK_A14
+    j       .L_xt_coproc_done
+
+    /* Co-processor exception occurred outside a thread (not supported). */
+.L_xt_coproc_invalid:
+    #if XCHAL_HAVE_DEBUG
+    break   1, 1                            /* unhandled user exception */
+    #endif
+    call0   _xt_panic                       /* not in a thread (invalid) */
+    /* never returns */
+
+
+#endif /* XCHAL_CP_NUM */
+
+
+/*
+-------------------------------------------------------------------------------
+  Level 1 interrupt dispatch. Assumes stack frame has not been allocated yet.
+-------------------------------------------------------------------------------
+*/
+
+    .text   
+    .type       _xt_lowint1,@function
+    .align      4
+
+_xt_lowint1:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, PS                          /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_1                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_user_exit               /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */ 
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(1) | PS_UM
+    #else 
+    movi    a0, PS_INTLEVEL(1) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 1 XCHAL_INTLEVEL1_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+
+/*
+-------------------------------------------------------------------------------
+  MEDIUM PRIORITY (LEVEL 2+) INTERRUPT VECTORS AND LOW LEVEL HANDLERS.
+
+  Medium priority interrupts are by definition those with priority greater
+  than 1 and not greater than XCHAL_EXCM_LEVEL. These are disabled by
+  setting PS.EXCM and therefore can easily support a C environment for
+  handlers in C, and interact safely with an RTOS.
+
+  Each vector goes at a predetermined location according to the Xtensa
+  hardware configuration, which is ensured by its placement in a special
+  section known to the Xtensa linker support package (LSP). It performs
+  the minimum necessary before jumping to the handler in the .text section.
+
+  The corresponding handler goes in the normal .text section. It sets up
+  the appropriate stack frame, saves a few vector-specific registers and
+  calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
+  and enter the RTOS, then sets up a C environment. It then calls the
+  user's interrupt handler code (which may be coded in C) and finally 
+  calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
+
+  While XT_RTOS_INT_EXIT does not return directly to the interruptee,
+  eventually the RTOS scheduler will want to dispatch the interrupted
+  task or handler. The scheduler will return to the exit point that was
+  saved in the interrupt stack frame at XT_STK_EXIT.
+-------------------------------------------------------------------------------
+*/
+
+#if XCHAL_EXCM_LEVEL >= 2
+
+    .begin      literal_prefix .Level2InterruptVector
+    .section    .Level2InterruptVector.text, "ax"
+    .global     _Level2Vector
+    .type       _Level2Vector,@function
+    .align      4
+_Level2Vector:
+    wsr     a0, EXCSAVE_2                   /* preserve a0 */
+    call0   _xt_medint2                     /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_medint2,@function
+    .align      4
+_xt_medint2:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_2                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_2                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_2                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint2_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(2) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(2) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint2_exit
+    .type       _xt_medint2_exit,@function
+    .align      4
+_xt_medint2_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_2
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_2
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     2
+
+#endif  /* Level 2 */
+
+#if XCHAL_EXCM_LEVEL >= 3
+
+    .begin      literal_prefix .Level3InterruptVector
+    .section    .Level3InterruptVector.text, "ax"
+    .global     _Level3Vector
+    .type       _Level3Vector,@function
+    .align      4
+_Level3Vector:
+    wsr     a0, EXCSAVE_3                   /* preserve a0 */
+    call0   _xt_medint3                     /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_medint3,@function
+    .align      4
+_xt_medint3:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_3                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_3                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_3                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint3_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(3) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(3) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint3_exit
+    .type       _xt_medint3_exit,@function
+    .align      4
+_xt_medint3_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_3
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_3
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     3
+
+#endif  /* Level 3 */
+
+#if XCHAL_EXCM_LEVEL >= 4
+
+    .begin      literal_prefix .Level4InterruptVector
+    .section    .Level4InterruptVector.text, "ax"
+    .global     _Level4Vector
+    .type       _Level4Vector,@function
+    .align      4
+_Level4Vector:
+    wsr     a0, EXCSAVE_4                   /* preserve a0 */
+    call0   _xt_medint4                     /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_medint4,@function
+    .align      4
+_xt_medint4:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_4                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_4                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_4                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint4_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(4) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(4) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint4_exit
+    .type       _xt_medint4_exit,@function
+    .align      4
+_xt_medint4_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_4
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_4
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     4
+
+#endif  /* Level 4 */
+
+#if XCHAL_EXCM_LEVEL >= 5
+
+    .begin      literal_prefix .Level5InterruptVector
+    .section    .Level5InterruptVector.text, "ax"
+    .global     _Level5Vector
+    .type       _Level5Vector,@function
+    .align      4
+_Level5Vector:
+    wsr     a0, EXCSAVE_5                   /* preserve a0 */
+    call0   _xt_medint5                     /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_medint5,@function
+    .align      4
+_xt_medint5:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_5                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_5                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_5                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint5_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(5) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint5_exit
+    .type       _xt_medint5_exit,@function
+    .align      4
+_xt_medint5_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_5
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_5
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     5
+
+#endif  /* Level 5 */
+
+#if XCHAL_EXCM_LEVEL >= 6
+
+    .begin      literal_prefix .Level6InterruptVector
+    .section    .Level6InterruptVector.text, "ax"
+    .global     _Level6Vector
+    .type       _Level6Vector,@function
+    .align      4
+_Level6Vector:
+    wsr     a0, EXCSAVE_6                   /* preserve a0 */
+    call0   _xt_medint6                     /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_medint6,@function
+    .align      4
+_xt_medint6:
+    mov     a0, sp                          /* sp == a1 */
+    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
+    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
+    rsr     a0, EPS_6                       /* save interruptee's PS */
+    s32i    a0, sp, XT_STK_PS
+    rsr     a0, EPC_6                       /* save interruptee's PC */
+    s32i    a0, sp, XT_STK_PC
+    rsr     a0, EXCSAVE_6                   /* save interruptee's a0 */
+    s32i    a0, sp, XT_STK_A0
+    movi    a0, _xt_medint6_exit            /* save exit point for dispatch */
+    s32i    a0, sp, XT_STK_EXIT
+
+    /* Save rest of interrupt context and enter RTOS. */
+    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
+
+    /* !! We are now on the RTOS system stack !! */
+
+    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
+    #ifdef __XTENSA_CALL0_ABI__
+    movi    a0, PS_INTLEVEL(6) | PS_UM
+    #else
+    movi    a0, PS_INTLEVEL(6) | PS_UM | PS_WOE
+    #endif
+    wsr     a0, PS
+    rsync
+
+    /* OK to call C code at this point, dispatch user ISRs */
+
+    dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK
+
+    /* Done handling interrupts, transfer control to OS */
+    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
+
+    /*
+    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
+    on entry and used to return to a thread or interrupted interrupt handler.
+    */
+    .global     _xt_medint6_exit
+    .type       _xt_medint6_exit,@function
+    .align      4
+_xt_medint6_exit:
+    /* Restore only level-specific regs (the rest were already restored) */
+    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
+    wsr     a0, EPS_6
+    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
+    wsr     a0, EPC_6
+    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
+    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
+    rsync                                   /* ensure EPS and EPC written */
+    rfi     6
+
+#endif  /* Level 6 */
+
+
+/*******************************************************************************
+
+HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS
+
+High priority interrupts are by definition those with priorities greater
+than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority
+interrupts cannot interact with the RTOS, that is they must save all regs
+they use and not call any RTOS function.
+
+A further restriction imposed by the Xtensa windowed architecture is that
+high priority interrupts must not modify the stack area even logically
+"above" the top of the interrupted stack (they need to provide their
+own stack or static save area).
+
+Cadence Design Systems recommends high priority interrupt handlers be coded in assembly
+and used for purposes requiring very short service times.
+
+Here are templates for high priority (level 2+) interrupt vectors.
+They assume only one interrupt per level to avoid the burden of identifying
+which interrupts at this level are pending and enabled. This allows for 
+minimum latency and avoids having to save/restore a2 in addition to a0.
+If more than one interrupt per high priority level is configured, this burden
+is on the handler which in any case must provide a way to save and restore
+registers it uses without touching the interrupted stack.
+
+Each vector goes at a predetermined location according to the Xtensa
+hardware configuration, which is ensured by its placement in a special
+section known to the Xtensa linker support package (LSP). It performs
+the minimum necessary before jumping to the handler in the .text section.
+
+*******************************************************************************/
+
+/*
+Currently only shells for high priority interrupt handlers are provided
+here. However a template and example can be found in the Cadence Design Systems tools
+documentation: "Microprocessor Programmer's Guide".
+*/
+
+#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
+
+    .begin      literal_prefix .Level2InterruptVector
+    .section    .Level2InterruptVector.text, "ax"
+    .global     _Level2Vector
+    .type       _Level2Vector,@function
+    .align      4
+_Level2Vector:
+    wsr     a0, EXCSAVE_2                   /* preserve a0 */
+    call0   _xt_highint2                    /* load interrupt handler */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_highint2,@function
+    .align      4
+_xt_highint2:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, 2<<2
+    beqz    a0, 1f
+.Ln_xt_highint2_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_highint2_exit:
+    rsr     a0, EXCSAVE_2                   /* restore a0 */
+    rfi     2
+
+#endif  /* Level 2 */
+
+#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
+
+    .begin      literal_prefix .Level3InterruptVector
+    .section    .Level3InterruptVector.text, "ax"
+    .global     _Level3Vector
+    .type       _Level3Vector,@function
+    .align      4
+_Level3Vector:
+    wsr     a0, EXCSAVE_3                   /* preserve a0 */
+    call0   _xt_highint3                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_highint3,@function
+    .align      4
+_xt_highint3:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, 3<<2
+    beqz    a0, 1f
+.Ln_xt_highint3_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_highint3_exit:
+    rsr     a0, EXCSAVE_3                   /* restore a0 */
+    rfi     3
+
+#endif  /* Level 3 */
+
+#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
+
+    .begin      literal_prefix .Level4InterruptVector
+    .section    .Level4InterruptVector.text, "ax"
+    .global     _Level4Vector
+    .type       _Level4Vector,@function
+    .align      4
+_Level4Vector:
+    wsr     a0, EXCSAVE_4                   /* preserve a0 */
+    call0   _xt_highint4                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_highint4,@function
+    .align      4
+_xt_highint4:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, 4<<2
+    beqz    a0, 1f
+.Ln_xt_highint4_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_highint4_exit:
+    rsr     a0, EXCSAVE_4                   /* restore a0 */
+    rfi     4
+
+#endif  /* Level 4 */
+
+#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
+
+    .begin      literal_prefix .Level5InterruptVector
+    .section    .Level5InterruptVector.text, "ax"
+    .global     _Level5Vector
+    .type       _Level5Vector,@function
+    .align      4
+_Level5Vector:
+    wsr     a0, EXCSAVE_5                   /* preserve a0 */
+    call0   _xt_highint5                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_highint5,@function
+    .align      4
+_xt_highint5:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, 5<<2
+    beqz    a0, 1f
+.Ln_xt_highint5_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_highint5_exit:
+    rsr     a0, EXCSAVE_5                   /* restore a0 */
+    rfi     5
+
+#endif  /* Level 5 */
+
+#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
+
+    .begin      literal_prefix .Level6InterruptVector
+    .section    .Level6InterruptVector.text, "ax"
+    .global     _Level6Vector
+    .type       _Level6Vector,@function
+    .align      4
+_Level6Vector:
+    wsr     a0, EXCSAVE_6                   /* preserve a0 */
+    call0   _xt_highint6                    /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_highint6,@function
+    .align      4
+_xt_highint6:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, 6<<2
+    beqz    a0, 1f
+.Ln_xt_highint6_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_highint6_exit:
+    rsr     a0, EXCSAVE_6                   /* restore a0 */
+    rfi     6
+
+#endif  /* Level 6 */
+
+#if XCHAL_HAVE_NMI
+
+    .begin      literal_prefix .NMIExceptionVector
+    .section    .NMIExceptionVector.text, "ax"
+    .global     _NMIExceptionVector
+    .type       _NMIExceptionVector,@function
+    .align      4
+_NMIExceptionVector:
+    wsr     a0, EXCSAVE + XCHAL_NMILEVEL  _ /* preserve a0 */
+    call0   _xt_nmi                         /* load interrupt handler */
+    /* never returns here - call0 is used as a jump (see note at top) */
+
+    .end        literal_prefix
+
+    .text
+    .type       _xt_nmi,@function
+    .align      4
+_xt_nmi:
+
+    #ifdef XT_INTEXC_HOOKS
+    /* Call interrupt hook if present to (pre)handle interrupts. */
+    movi    a0, _xt_intexc_hooks
+    l32i    a0, a0, XCHAL_NMILEVEL<<2
+    beqz    a0, 1f
+.Ln_xt_nmi_call_hook:
+    callx0  a0                              /* must NOT disturb stack! */
+1:
+    #endif
+
+    /* USER_EDIT:
+    ADD HIGH PRIORITY NON-MASKABLE INTERRUPT (NMI) HANDLER CODE HERE.
+    */
+
+    .align  4
+.L_xt_nmi_exit:
+    rsr     a0, EXCSAVE + XCHAL_NMILEVEL    /* restore a0 */
+    rfi     XCHAL_NMILEVEL
+
+#endif  /* NMI */
+
+
+/*******************************************************************************
+
+WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER
+
+Here is the code for each window overflow/underflow exception vector and 
+(interspersed) efficient code for handling the alloca exception cause.
+Window exceptions are handled entirely in the vector area and are very
+tight for performance. The alloca exception is also handled entirely in 
+the window vector area so comes at essentially no cost in code size.
+Users should never need to modify them and Cadence Design Systems recommends 
+they do not.
+
+Window handlers go at predetermined vector locations according to the
+Xtensa hardware configuration, which is ensured by their placement in a
+special section known to the Xtensa linker support package (LSP). Since
+their offsets in that section are always the same, the LSPs do not define
+a section per vector.
+
+These things are coded for XEA2 only (XEA1 is not supported).
+
+Note on Underflow Handlers:
+The underflow handler for returning from call[i+1] to call[i]
+must preserve all the registers from call[i+1]'s window.
+In particular, a0 and a1 must be preserved because the RETW instruction
+will be reexecuted (and may even underflow if an intervening exception
+has flushed call[i]'s registers).
+Registers a2 and up may contain return values.
+
+*******************************************************************************/
+
+#if XCHAL_HAVE_WINDOWED
+
+    .section .WindowVectors.text, "ax"
+
+/*
+--------------------------------------------------------------------------------
+Window Overflow Exception for Call4.
+
+Invoked if a call[i] referenced a register (a4-a15)
+that contains data from ancestor call[j];
+call[j] had done a call4 to call[j+1].
+On entry here:
+    window rotated to call[j] start point;
+        a0-a3 are registers to be saved;
+        a4-a15 must be preserved;
+        a5 is call[j+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x0
+    .global _WindowOverflow4
+_WindowOverflow4:
+
+    s32e    a0, a5, -16     /* save a0 to call[j+1]'s stack frame */
+    s32e    a1, a5, -12     /* save a1 to call[j+1]'s stack frame */
+    s32e    a2, a5,  -8     /* save a2 to call[j+1]'s stack frame */
+    s32e    a3, a5,  -4     /* save a3 to call[j+1]'s stack frame */
+    rfwo                    /* rotates back to call[i] position */
+
+/*
+--------------------------------------------------------------------------------
+Window Underflow Exception for Call4
+
+Invoked by RETW returning from call[i+1] to call[i]
+where call[i]'s registers must be reloaded (not live in ARs);
+where call[i] had done a call4 to call[i+1].
+On entry here:
+        window rotated to call[i] start point;
+        a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
+        a4-a15 must be preserved (they are call[i+1].reg[0..11]);
+        a5 is call[i+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x40
+    .global _WindowUnderflow4
+_WindowUnderflow4:
+
+    l32e    a0, a5, -16     /* restore a0 from call[i+1]'s stack frame */
+    l32e    a1, a5, -12     /* restore a1 from call[i+1]'s stack frame */
+    l32e    a2, a5,  -8     /* restore a2 from call[i+1]'s stack frame */
+    l32e    a3, a5,  -4     /* restore a3 from call[i+1]'s stack frame */
+    rfwu
+
+/*
+--------------------------------------------------------------------------------
+Handle alloca exception generated by interruptee executing 'movsp'.
+This uses space between the window vectors, so is essentially "free".
+All interruptee's regs are intact except a0 which is saved in EXCSAVE_1,
+and PS.EXCM has been set by the exception hardware (can't be interrupted).
+The fact the alloca exception was taken means the registers associated with
+the base-save area have been spilled and will be restored by the underflow
+handler, so those 4 registers are available for scratch.
+The code is optimized to avoid unaligned branches and minimize cache misses.
+--------------------------------------------------------------------------------
+*/
+
+    .align  4
+    .global _xt_alloca_exc
+_xt_alloca_exc:
+
+    rsr     a0, WINDOWBASE  /* grab WINDOWBASE before rotw changes it */
+    rotw    -1              /* WINDOWBASE goes to a4, new a0-a3 are scratch */
+    rsr     a2, PS
+    extui   a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
+    xor     a3, a3, a4      /* bits changed from old to current windowbase */
+    rsr     a4, EXCSAVE_1   /* restore original a0 (now in a4) */
+    slli    a3, a3, XCHAL_PS_OWB_SHIFT
+    xor     a2, a2, a3      /* flip changed bits in old window base */
+    wsr     a2, PS          /* update PS.OWB to new window base */
+    rsync
+
+    _bbci.l a4, 31, _WindowUnderflow4
+    rotw    -1              /* original a0 goes to a8 */
+    _bbci.l a8, 30, _WindowUnderflow8
+    rotw    -1
+    j               _WindowUnderflow12
+
+/*
+--------------------------------------------------------------------------------
+Window Overflow Exception for Call8
+
+Invoked if a call[i] referenced a register (a4-a15)
+that contains data from ancestor call[j];
+call[j] had done a call8 to call[j+1].
+On entry here:
+    window rotated to call[j] start point;
+        a0-a7 are registers to be saved;
+        a8-a15 must be preserved;
+        a9 is call[j+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x80
+    .global _WindowOverflow8
+_WindowOverflow8:
+
+    s32e    a0, a9, -16     /* save a0 to call[j+1]'s stack frame */
+    l32e    a0, a1, -12     /* a0 <- call[j-1]'s sp
+                               (used to find end of call[j]'s frame) */
+    s32e    a1, a9, -12     /* save a1 to call[j+1]'s stack frame */
+    s32e    a2, a9,  -8     /* save a2 to call[j+1]'s stack frame */
+    s32e    a3, a9,  -4     /* save a3 to call[j+1]'s stack frame */
+    s32e    a4, a0, -32     /* save a4 to call[j]'s stack frame */
+    s32e    a5, a0, -28     /* save a5 to call[j]'s stack frame */
+    s32e    a6, a0, -24     /* save a6 to call[j]'s stack frame */
+    s32e    a7, a0, -20     /* save a7 to call[j]'s stack frame */
+    rfwo                    /* rotates back to call[i] position */
+
+/*
+--------------------------------------------------------------------------------
+Window Underflow Exception for Call8
+
+Invoked by RETW returning from call[i+1] to call[i]
+where call[i]'s registers must be reloaded (not live in ARs);
+where call[i] had done a call8 to call[i+1].
+On entry here:
+        window rotated to call[i] start point;
+        a0-a7 are undefined, must be reloaded with call[i].reg[0..7];
+        a8-a15 must be preserved (they are call[i+1].reg[0..7]);
+        a9 is call[i+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0xC0
+    .global _WindowUnderflow8
+_WindowUnderflow8:
+
+    l32e    a0, a9, -16     /* restore a0 from call[i+1]'s stack frame */
+    l32e    a1, a9, -12     /* restore a1 from call[i+1]'s stack frame */
+    l32e    a2, a9,  -8     /* restore a2 from call[i+1]'s stack frame */
+    l32e    a7, a1, -12     /* a7 <- call[i-1]'s sp
+                               (used to find end of call[i]'s frame) */
+    l32e    a3, a9,  -4     /* restore a3 from call[i+1]'s stack frame */
+    l32e    a4, a7, -32     /* restore a4 from call[i]'s stack frame */
+    l32e    a5, a7, -28     /* restore a5 from call[i]'s stack frame */
+    l32e    a6, a7, -24     /* restore a6 from call[i]'s stack frame */
+    l32e    a7, a7, -20     /* restore a7 from call[i]'s stack frame */
+    rfwu
+
+/*
+--------------------------------------------------------------------------------
+Window Overflow Exception for Call12
+
+Invoked if a call[i] referenced a register (a4-a15)
+that contains data from ancestor call[j];
+call[j] had done a call12 to call[j+1].
+On entry here:
+    window rotated to call[j] start point;
+        a0-a11 are registers to be saved;
+        a12-a15 must be preserved;
+        a13 is call[j+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org    0x100
+    .global _WindowOverflow12
+_WindowOverflow12:
+
+    s32e    a0,  a13, -16   /* save a0 to call[j+1]'s stack frame */
+    l32e    a0,  a1,  -12   /* a0 <- call[j-1]'s sp
+                               (used to find end of call[j]'s frame) */
+    s32e    a1,  a13, -12   /* save a1 to call[j+1]'s stack frame */
+    s32e    a2,  a13,  -8   /* save a2 to call[j+1]'s stack frame */
+    s32e    a3,  a13,  -4   /* save a3 to call[j+1]'s stack frame */
+    s32e    a4,  a0,  -48   /* save a4 to end of call[j]'s stack frame */
+    s32e    a5,  a0,  -44   /* save a5 to end of call[j]'s stack frame */
+    s32e    a6,  a0,  -40   /* save a6 to end of call[j]'s stack frame */
+    s32e    a7,  a0,  -36   /* save a7 to end of call[j]'s stack frame */
+    s32e    a8,  a0,  -32   /* save a8 to end of call[j]'s stack frame */
+    s32e    a9,  a0,  -28   /* save a9 to end of call[j]'s stack frame */
+    s32e    a10, a0,  -24   /* save a10 to end of call[j]'s stack frame */
+    s32e    a11, a0,  -20   /* save a11 to end of call[j]'s stack frame */
+    rfwo                    /* rotates back to call[i] position */
+
+/*
+--------------------------------------------------------------------------------
+Window Underflow Exception for Call12
+
+Invoked by RETW returning from call[i+1] to call[i]
+where call[i]'s registers must be reloaded (not live in ARs);
+where call[i] had done a call12 to call[i+1].
+On entry here:
+        window rotated to call[i] start point;
+        a0-a11 are undefined, must be reloaded with call[i].reg[0..11];
+        a12-a15 must be preserved (they are call[i+1].reg[0..3]);
+        a13 is call[i+1]'s stack pointer.
+--------------------------------------------------------------------------------
+*/
+
+    .org 0x140
+    .global _WindowUnderflow12
+_WindowUnderflow12:
+
+    l32e    a0,  a13, -16   /* restore a0 from call[i+1]'s stack frame */
+    l32e    a1,  a13, -12   /* restore a1 from call[i+1]'s stack frame */
+    l32e    a2,  a13,  -8   /* restore a2 from call[i+1]'s stack frame */
+    l32e    a11, a1,  -12   /* a11 <- call[i-1]'s sp
+                               (used to find end of call[i]'s frame) */
+    l32e    a3,  a13,  -4   /* restore a3 from call[i+1]'s stack frame */
+    l32e    a4,  a11, -48   /* restore a4 from end of call[i]'s stack frame */
+    l32e    a5,  a11, -44   /* restore a5 from end of call[i]'s stack frame */
+    l32e    a6,  a11, -40   /* restore a6 from end of call[i]'s stack frame */
+    l32e    a7,  a11, -36   /* restore a7 from end of call[i]'s stack frame */
+    l32e    a8,  a11, -32   /* restore a8 from end of call[i]'s stack frame */
+    l32e    a9,  a11, -28   /* restore a9 from end of call[i]'s stack frame */
+    l32e    a10, a11, -24   /* restore a10 from end of call[i]'s stack frame */
+    l32e    a11, a11, -20   /* restore a11 from end of call[i]'s stack frame */
+    rfwu
+
+#endif /* XCHAL_HAVE_WINDOWED */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c
new file mode 100644
index 0000000..680f38e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c
@@ -0,0 +1,138 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* 
+Changes from V3.0.0
+	+ ISRcode is pulled inline and portTICKisr() is therefore
+	  deleted from this file.
+
+	+ Prescaler logic for Timer1 added to allow for a wider
+	  range of TickRates.
+
+Changes from V3.0.1
+*/
+
+#include <FreeRTOS.h>
+#include <task.h>
+
+/* IO port constants. */
+#define portBIT_SET		(1)
+#define portBIT_CLEAR	(0)
+
+/* 
+ * Hardware setup for the tick.
+ * We use a compare match on timer1. Depending on MPU-frequency
+ * and requested tickrate, a prescaled value with a matching
+ * prescaler are determined.
+ */
+#define	portTIMER_COMPARE_BASE			((APROCFREQ/4)/configTICK_RATE_HZ)
+
+#if portTIMER_COMPARE_BASE   < 0x10000
+	#define	portTIMER_COMPARE_VALUE		(portTIMER_COMPARE_BASE)
+	#define portTIMER_COMPARE_PS1		(portBIT_CLEAR)
+	#define portTIMER_COMPARE_PS0		(portBIT_CLEAR)
+#elif portTIMER_COMPARE_BASE < 0x20000
+	#define	portTIMER_COMPARE_VALUE		(portTIMER_COMPARE_BASE / 2)
+	#define portTIMER_COMPARE_PS1		(portBIT_CLEAR)
+	#define portTIMER_COMPARE_PS0		(portBIT_SET)
+#elif portTIMER_COMPARE_BASE < 0x40000
+	#define	portTIMER_COMPARE_VALUE		(portTIMER_COMPARE_BASE / 4)
+	#define portTIMER_COMPARE_PS1		(portBIT_SET)
+	#define portTIMER_COMPARE_PS0		(portBIT_CLEAR)
+#elif portTIMER_COMPARE_BASE < 0x80000
+	#define	portTIMER_COMPARE_VALUE		(portTIMER_COMPARE_BASE / 8)
+	#define portTIMER_COMPARE_PS1		(portBIT_SET)
+	#define portTIMER_COMPARE_PS0		(portBIT_SET)
+#else
+	#error "TickRate out of range"
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup a timer for a regular tick.
+ */
+void portSetupTick( void )
+{
+	/*
+	 * Interrupts are disabled when this function is called.
+	 */
+
+	/*
+	 * Setup CCP1
+	 * Provide the tick interrupt using a compare match on timer1.
+	 */
+
+	/*
+	 * Set the compare match value.
+	 */
+	CCPR1H = ( uint8_t ) ( ( portTIMER_COMPARE_VALUE >> 8 ) & 0xff );
+	CCPR1L = ( uint8_t )   ( portTIMER_COMPARE_VALUE & 0xff );
+
+	/*
+	 * Set Compare Special Event Trigger Mode
+	 */
+	bCCP1M3 	= portBIT_SET;
+	bCCP1M2 	= portBIT_CLEAR;
+	bCCP1M1 	= portBIT_SET;
+	bCCP1M0		= portBIT_SET;
+
+	/*
+	 * Enable CCP1 interrupt
+	 */
+	bCCP1IE 	= portBIT_SET;
+
+	/*
+	 * We are only going to use the global interrupt bit, so disable
+	 * interruptpriorities and enable peripheral interrupts.
+	 */
+	bIPEN		= portBIT_CLEAR;
+	bPEIE		= portBIT_SET;
+
+	/*
+	 * Set up timer1
+	 * It will produce the system tick.
+	 */
+
+	/*
+	 * Clear the time count
+	 */
+	TMR1H = ( uint8_t ) 0x00;
+	TMR1L = ( uint8_t ) 0x00;
+
+	/*
+	 * Setup the timer
+	 */
+	bRD16		= portBIT_SET;				// 16-bit
+	bT1CKPS1	= portTIMER_COMPARE_PS1;	// prescaler
+	bT1CKPS0	= portTIMER_COMPARE_PS0;	// prescaler
+	bT1OSCEN	= portBIT_SET;				// Oscillator enable
+	bT1SYNC		= portBIT_SET;				// No external clock sync
+	bTMR1CS		= portBIT_CLEAR;			// Internal clock
+	
+	bTMR1ON		= portBIT_SET;				// Start timer1
+}
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c
new file mode 100644
index 0000000..67b5b58
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c
@@ -0,0 +1,78 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/* 
+Changes from V3.0.0
+	+ ISRcode pulled inline to reduce stack-usage.
+
+	+ Added functionality to only call vTaskSwitchContext() once
+	  when handling multiple interruptsources in a single interruptcall.
+
+	+ Filename changed to a .c extension to allow stepping through code
+	  using F7.
+
+Changes from V3.0.1
+*/
+
+/*
+ * ISR for the tick.
+ * This increments the tick count and, if using the preemptive scheduler, 
+ * performs a context switch.  This must be identical to the manual 
+ * context switch in how it stores the context of a task. 
+ */
+
+#ifndef _FREERTOS_DRIVERS_TICK_ISRTICK_C
+#define _FREERTOS_DRIVERS_TICK_ISRTICK_C
+
+{
+	/*
+	 * Was the interrupt the SystemClock?
+	 */
+	if( bCCP1IF && bCCP1IE )
+	{
+		/*
+		 * Reset the interrupt flag
+		 */
+		bCCP1IF = 0;
+	
+		/*
+	 	 * Maintain the tick count.
+	 	 */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/*
+		 	 * Ask for a switch to the highest priority task
+		 	 * that is ready to run.
+		 	 */
+			uxSwitchRequested = pdTRUE;
+		}
+	}
+}
+
+#pragma wizcpp uselib     "$__PATHNAME__/Tick.c"
+
+#endif	/* _FREERTOS_DRIVERS_TICK_ISRTICK_C */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/Install.bat b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/Install.bat
new file mode 100644
index 0000000..780ec21
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/Install.bat
@@ -0,0 +1,172 @@
+
+@echo off
+cls
+
+SET PACKAGENAME=the FreeRTOS port for fedC and wizC
+
+echo.
+echo Hello, I'm the installationscript for %PACKAGENAME%.
+echo.
+
+:CHECKFEDC
+  set FED=C:\Program Files\FED\PIC_C
+  echo.
+  echo I'm checking your system for fedC
+  if not exist "%FED%" goto NOFEDC
+  echo YES, I found a fedC-installation!
+  goto FOUNDFED
+:NOFEDC
+  echo I could not find a fedC-installation.
+
+
+:CHECKWIZC
+  set FED=C:\Program Files\FED\PIXIE
+  echo.
+  echo I'm checking your system for wizC
+  if not exist "%FED%" goto NOWIZC
+  echo YES, I found a wizC-installation!
+  goto FOUNDFED
+:noWIZC
+  echo I could not find a wizC-installation.
+
+
+:ERROR
+  echo.
+  echo.
+  echo I could not find a FED C-compiler installation on your system.
+  echo.
+  echo Perhaps I got confused because you installed fedC or wizC in a non-default directory.
+  echo If this is the case, please change the path at the top of this install-script.
+  echo After that rerun the script and I will be happy to try again.
+  echo.
+  goto ENDIT
+
+
+:FOUNDFED
+  echo.
+  echo.
+
+  set FEDLIBS=%FED%\Libs
+  set FEDLIBSUSER=%FEDLIBS%\LibsUser
+
+  if exist "%FEDLIBS%" goto INSTALL
+  echo The FED installationdirectory "%FED%"
+  echo contains no Libs subdirectory. This is weird!
+  echo.
+  echo Installation is aborted, sorry...
+  goto ENDIT
+
+
+:INSTALL
+  echo I am about to install %PACKAGENAME%
+  echo into directory %FEDLIBSUSER%
+  echo.
+  echo   Press 'enter'  to let me do my thing
+  echo   Press 'ctrl-c' to stop me
+  pause >nul
+  echo.
+  echo Installing...
+
+
+:RESET_READONLY
+  echo.
+  echo   Removing ReadOnly attributes
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c"     >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c"         >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c"         >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c"        >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c"        >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c"    >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h"    >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h"     >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h"         >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h"     >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h"     >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h"        >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h"       >nul
+  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h"         >nul
+  attrib -R "%FEDLIBSUSER%\FreeRTOS.h"                         >nul
+  echo   Done
+
+:CREATE_DIRECTORIES
+  echo.
+  echo   Creating directories (if necessary)...
+  if not exist "%FEDLIBSUSER%"                          mkdir "%FEDLIBSUSER%"
+  if not exist "%FEDLIBSUSER%\libFreeRTOS"              mkdir "%FEDLIBSUSER%\libFreeRTOS"
+  if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers"      mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers"
+  if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick" mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick"
+  if not exist "%FEDLIBSUSER%\libFreeRTOS\Include"      mkdir "%FEDLIBSUSER%\libFreeRTOS\Include"
+  if not exist "%FEDLIBSUSER%\libFreeRTOS\Modules"      mkdir "%FEDLIBSUSER%\libFreeRTOS\Modules"
+  echo   Done
+
+
+  echo.
+  echo   Copying Files...
+:COPY_MODULES
+  echo     Modules...
+  copy /V /Y "Port.c"                      "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c"         >nul
+  copy /V /Y "..\..\..\Croutine.c"         "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c"     >nul
+  copy /V /Y "..\..\..\List.c"             "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c"         >nul
+  copy /V /Y "..\..\..\Queue.c"            "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c"        >nul
+  copy /V /Y "..\..\..\Tasks.c"            "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c"        >nul
+
+:COPY_DRIVERS
+  echo     Drivers...
+  copy /V /Y "Drivers\Tick\Tick.c"         "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c"    >nul
+  copy /V /Y "Drivers\Tick\isrTick.c"      "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul
+
+:COPY_HEADERS
+  echo     Headers...
+  copy /V /Y "portmacro.h"                 "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h"    >nul
+  copy /V /Y "..\..\..\include\Croutine.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h"     >nul
+  copy /V /Y "..\..\..\include\List.h"     "%FEDLIBSUSER%\libFreeRTOS\Include\List.h"         >nul
+  copy /V /Y "..\..\..\include\Portable.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h"     >nul
+  copy /V /Y "..\..\..\include\Projdefs.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h"     >nul
+  copy /V /Y "..\..\..\include\Queue.h"    "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h"        >nul
+  copy /V /Y "..\..\..\include\Semphr.h"   "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h"       >nul
+  copy /V /Y "..\..\..\include\Task.h"     "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h"         >nul
+  copy /V /Y "addFreeRTOS.h" + "..\..\..\include\FreeRTOS.h" "%FEDLIBSUSER%\FreeRTOS.h"       >nul
+
+
+  echo   Done
+
+
+:SET_READONLY
+  echo.
+  echo   Setting files to ReadOnly
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c"         >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c"     >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c"         >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c"        >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c"        >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c"    >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h"    >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h"     >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h"         >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h"     >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h"     >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h"        >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h"       >nul
+  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h"         >nul
+  attrib +R "%FEDLIBSUSER%\FreeRTOS.h"                         >nul
+  echo   Done
+
+
+:FINISHED
+  echo.
+  echo The installation of %PACKAGENAME% is completed.
+  echo.
+  echo Please review the installation instructions as additional libraries
+  echo  and fedC/wizC configuration settings may be needed for FreeRTOS
+  echo  to function correctly.
+
+  goto ENDIT
+
+
+:ENDIT
+  echo.
+  echo.
+  echo Press 'enter' to close this window
+  pause >nul
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/addFreeRTOS.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/addFreeRTOS.h
new file mode 100644
index 0000000..e1a441e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/addFreeRTOS.h
@@ -0,0 +1,53 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V3.0.0
+
+Changes from V3.0.1
+
+Changes from V4.0.1
+    Uselib pragma added for Croutine.c
+*/
+
+/*
+ * The installation script will automatically prepend this file to the default FreeRTOS.h.
+ */
+
+#ifndef WIZC_FREERTOS_H
+#define WIZC_FREERTOS_H
+
+#pragma	noheap
+#pragma wizcpp expandnl   on
+#pragma wizcpp searchpath "$__PATHNAME__/libFreeRTOS/Include/"
+#pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/Croutine.c"
+#pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/Tasks.c"
+#pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/Queue.c"
+#pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/List.c"
+#pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/Port.c"
+
+#endif	/* WIZC_FREERTOS_H */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/port.c
new file mode 100644
index 0000000..a44ee89
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/port.c
@@ -0,0 +1,317 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V3.2.1
+	+ CallReturn Depth increased from 8 to 10 levels to accomodate wizC/fedC V12.
+
+Changes from V3.2.0
+	+ TBLPTRU is now initialised to zero during the initial stack creation of a new task. This solves
+	an error on devices with more than 64kB ROM.
+
+Changes from V3.0.0
+	+ ucCriticalNesting is now initialised to 0x7F to prevent interrupts from being
+          handled before the scheduler is started.
+
+Changes from V3.0.1
+*/
+
+/* Scheduler include files. */
+#include <FreeRTOS.h>
+#include <task.h>
+
+#include <malloc.h>
+
+/*---------------------------------------------------------------------------
+ * Implementation of functions defined in portable.h for the WizC PIC18 port.
+ *---------------------------------------------------------------------------*/
+
+/*
+ * We require the address of the pxCurrentTCB variable, but don't want to
+ * know any details of its type.
+ */
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+
+/*
+ * Define minimal-stack constants
+ * -----
+ * FSR's:
+ *		STATUS, WREG, BSR, PRODH, PRODL, FSR0H, FSR0L,
+ *		FSR1H, FSR1L,TABLAT, (TBLPTRU), TBLPTRH, TBLPTRL,
+ *		(PCLATU), PCLATH
+ *		sfr's within parenthesis only on devices > 64kB
+ * -----
+ * Call/Return stack:
+ *		 2 bytes per entry on devices <= 64kB
+ *		 3 bytes per entry on devices >  64kB
+ * -----
+ * Other bytes:
+ *		 2 bytes: FunctionParameter for initial taskcode
+ *		 1 byte : Number of entries on call/return stack
+ *		 1 byte : ucCriticalNesting
+ *		16 bytes: Free space on stack
+ */
+#if _ROMSIZE > 0x8000
+	#define portSTACK_FSR_BYTES				( 15 )
+	#define portSTACK_CALLRETURN_ENTRY_SIZE	(  3 )
+#else
+	#define portSTACK_FSR_BYTES				( 13 )
+	#define portSTACK_CALLRETURN_ENTRY_SIZE	(  2 )
+#endif
+
+#define portSTACK_MINIMAL_CALLRETURN_DEPTH	( 10 )
+#define portSTACK_OTHER_BYTES				( 20 )
+
+uint16_t usCalcMinStackSize		= 0;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * We initialise ucCriticalNesting to the middle value an
+ * uint8_t can contain. This way portENTER_CRITICAL()
+ * and portEXIT_CRITICAL() can be called without interrupts
+ * being enabled before the scheduler starts.
+ */
+register uint8_t ucCriticalNesting = 0x7F;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the stack of a new task.
+ * See portSAVE_CONTEXT macro for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+uint8_t ucScratch;
+	/*
+	 * Get the size of the RAMarea in page 0 used by the compiler
+	 * We do this here already to avoid W-register conflicts.
+	 */
+	_Pragma("asm")
+		movlw	OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE
+		movwf	PRODL,ACCESS		; PRODL is used as temp register
+	_Pragma("asmend")
+	ucScratch = PRODL;
+
+	/*
+	 * Place a few bytes of known values on the bottom of the stack.
+	 * This is just useful for debugging.
+	 */
+//	*pxTopOfStack--	= 0x11;
+//	*pxTopOfStack-- = 0x22;
+//	*pxTopOfStack-- = 0x33;
+
+	/*
+	 * Simulate how the stack would look after a call to vPortYield()
+	 * generated by the compiler.
+	 */
+
+	/*
+	 * First store the function parameters.  This is where the task expects
+	 * to find them when it starts running.
+	 */
+	*pxTopOfStack-- = ( StackType_t ) ( (( uint16_t ) pvParameters >> 8) & 0x00ff );
+	*pxTopOfStack-- = ( StackType_t ) (  ( uint16_t ) pvParameters       & 0x00ff );
+
+	/*
+	 * Next are all the registers that form part of the task context.
+	 */
+	*pxTopOfStack-- = ( StackType_t ) 0x11; /* STATUS. */
+	*pxTopOfStack-- = ( StackType_t ) 0x22; /* WREG. */
+	*pxTopOfStack-- = ( StackType_t ) 0x33; /* BSR. */
+	*pxTopOfStack-- = ( StackType_t ) 0x44; /* PRODH. */
+	*pxTopOfStack-- = ( StackType_t ) 0x55; /* PRODL. */
+	*pxTopOfStack-- = ( StackType_t ) 0x66; /* FSR0H. */
+	*pxTopOfStack-- = ( StackType_t ) 0x77; /* FSR0L. */
+	*pxTopOfStack-- = ( StackType_t ) 0x88; /* FSR1H. */
+	*pxTopOfStack-- = ( StackType_t ) 0x99; /* FSR1L. */
+	*pxTopOfStack-- = ( StackType_t ) 0xAA; /* TABLAT. */
+#if _ROMSIZE > 0x8000
+	*pxTopOfStack-- = ( StackType_t ) 0x00; /* TBLPTRU. */
+#endif
+	*pxTopOfStack-- = ( StackType_t ) 0xCC; /* TBLPTRH. */
+	*pxTopOfStack-- = ( StackType_t ) 0xDD; /* TBLPTRL. */
+#if _ROMSIZE > 0x8000
+	*pxTopOfStack-- = ( StackType_t ) 0xEE; /* PCLATU. */
+#endif
+	*pxTopOfStack-- = ( StackType_t ) 0xFF; /* PCLATH. */
+
+	/*
+	 * Next the compiler's scratchspace.
+	 */
+	while(ucScratch-- > 0)
+	{
+		*pxTopOfStack-- = ( StackType_t ) 0;
+	}
+
+	/*
+	 * The only function return address so far is the address of the task entry.
+	 * The order is TOSU/TOSH/TOSL. For devices > 64kB, TOSU is put on the
+	 * stack, too. TOSU is always written as zero here because wizC does not allow
+	 * functionpointers to point above 64kB in ROM.
+	 */
+#if _ROMSIZE > 0x8000
+	*pxTopOfStack-- = ( StackType_t ) 0;
+#endif
+	*pxTopOfStack-- = ( StackType_t ) ( ( ( uint16_t ) pxCode >> 8 ) & 0x00ff );
+	*pxTopOfStack-- = ( StackType_t ) ( (   uint16_t ) pxCode        & 0x00ff );
+
+	/*
+	 * Store the number of return addresses on the hardware stack.
+	 * So far only the address of the task entry point.
+	 */
+	*pxTopOfStack-- = ( StackType_t ) 1;
+
+	/*
+	 * The code generated by wizC does not maintain separate
+	 * stack and frame pointers. Therefore the portENTER_CRITICAL macro cannot
+	 * use the stack as per other ports.  Instead a variable is used to keep
+	 * track of the critical section nesting.  This variable has to be stored
+	 * as part of the task context and is initially set to zero.
+	 */
+	*pxTopOfStack-- = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void )
+{
+	/*
+	 * Fetch the size of compiler's scratchspace.
+	 */
+	_Pragma("asm")
+		movlw	OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE
+		movlb	usCalcMinStackSize>>8
+		movwf	usCalcMinStackSize,BANKED
+	_Pragma("asmend")
+
+	/*
+	 * Add minimum needed stackspace
+	 */
+	usCalcMinStackSize	+=	( portSTACK_FSR_BYTES )
+		+	( portSTACK_MINIMAL_CALLRETURN_DEPTH * portSTACK_CALLRETURN_ENTRY_SIZE )
+		+	( portSTACK_OTHER_BYTES );
+
+	return(usCalcMinStackSize);
+}
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xPortStartScheduler( void )
+{
+	extern void portSetupTick( void );
+
+	/*
+	 * Setup a timer for the tick ISR for the preemptive scheduler.
+	 */
+	portSetupTick();
+
+	/*
+	 * Restore the context of the first task to run.
+	 */
+	portRESTORE_CONTEXT();
+
+	/*
+	 * This point should never be reached during execution.
+	 */
+	return pdTRUE;
+}
+
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/*
+	 * It is unlikely that the scheduler for the PIC port will get stopped
+	 * once running. When called a reset is done which is probably the
+	 * most valid action.
+	 */
+	_Pragma(asmline reset);
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Manual context switch.  This is similar to the tick context switch,
+ * but does not increment the tick count.  It must be identical to the
+ * tick context switch in how it stores the stack of a task.
+ */
+void vPortYield( void )
+{
+	/*
+	 * Save the context of the current task.
+	 */
+	portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
+
+	/*
+	 * Switch to the highest priority task that is ready to run.
+	 */
+	vTaskSwitchContext();
+
+	/*
+	 * Start executing the task we have just switched to.
+	 */
+	portRESTORE_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	void *pvPortMalloc( uint16_t usWantedSize )
+	{
+	void *pvReturn;
+
+		vTaskSuspendAll();
+		{
+			pvReturn = malloc( ( malloc_t ) usWantedSize );
+		}
+		xTaskResumeAll();
+
+		return pvReturn;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	void vPortFree( void *pv )
+	{
+		if( pv )
+		{
+			vTaskSuspendAll();
+			{
+				free( pv );
+			}
+			xTaskResumeAll();
+		}
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
\ No newline at end of file
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/portmacro.h
new file mode 100644
index 0000000..65f88a1
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/WizC/PIC18/portmacro.h
@@ -0,0 +1,423 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V3.0.0
+
+Changes from V3.0.1
+*/
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#if !defined(_SERIES) || _SERIES != 18
+	#error "WizC supports FreeRTOS on the Microchip PIC18-series only"
+#endif
+
+#if !defined(QUICKCALL) || QUICKCALL != 1
+	#error "QuickCall must be enabled (see ProjectOptions/Optimisations)"
+#endif
+
+#include <stddef.h>
+#include <pic.h>
+
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		portFLOAT
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint8_t
+#define portBASE_TYPE	char
+
+typedef portSTACK_TYPE StackType_t;
+typedef signed char BaseType_t;
+typedef unsigned char UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )	( 0xFFFF )
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t )	( 0xFFFFFFFF )
+#endif
+
+#define portBYTE_ALIGNMENT			1
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Constant used for context switch macro when we require the interrupt
+ * enable state to be forced when the interrupted task is switched back in.
+ */
+#define portINTERRUPTS_FORCED				(0x01)
+
+/*
+ * Constant used for context switch macro when we require the interrupt
+ * enable state to be unchanged when the interrupted task is switched back in.
+ */
+#define portINTERRUPTS_UNCHANGED			(0x00)
+
+/* Initial interrupt enable state for newly created tasks.  This value is
+ * used when a task switches in for the first time.
+ */
+#define portINTERRUPTS_INITIAL_STATE		(portINTERRUPTS_FORCED)
+
+/*
+ * Macros to modify the global interrupt enable bit in INTCON.
+ */
+#define portDISABLE_INTERRUPTS()	\
+	do								\
+	{								\
+		bGIE=0;						\
+	} while(bGIE)	// MicroChip recommends this check!
+
+#define portENABLE_INTERRUPTS()		\
+	do								\
+	{								\
+		bGIE=1;						\
+	} while(0)
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Critical section macros.
+ */
+extern uint8_t ucCriticalNesting;
+
+#define portNO_CRITICAL_SECTION_NESTING		( ( uint8_t ) 0 )
+
+#define portENTER_CRITICAL()										\
+	do																\
+	{																\
+		portDISABLE_INTERRUPTS();									\
+																	\
+		/*															\
+		 * Now interrupts are disabled ucCriticalNesting			\
+		 * can be accessed directly. Increment						\
+		 * ucCriticalNesting to keep a count of how					\
+		 * many times portENTER_CRITICAL() has been called. 		\
+		 */															\
+		ucCriticalNesting++;										\
+	} while(0)
+
+#define portEXIT_CRITICAL()											\
+	do																\
+	{																\
+		if(ucCriticalNesting > portNO_CRITICAL_SECTION_NESTING)		\
+		{															\
+			/*														\
+			 * Decrement the nesting count as we are leaving a		\
+			 * critical section.									\
+			 */														\
+			ucCriticalNesting--;									\
+		}															\
+																	\
+		/*															\
+		 * If the nesting level has reached zero then				\
+		 * interrupts should be re-enabled.							\
+		 */															\
+		if( ucCriticalNesting == portNO_CRITICAL_SECTION_NESTING )	\
+		{															\
+			portENABLE_INTERRUPTS();								\
+		}															\
+	} while(0)
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The minimal stacksize is calculated on the first reference of
+ * portMINIMAL_STACK_SIZE. Some input to this calculation is
+ * compiletime determined, other input is port-defined (see port.c)
+ */
+extern uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void );
+extern uint16_t usCalcMinStackSize;
+
+#define portMINIMAL_STACK_SIZE					\
+	((usCalcMinStackSize == 0)					\
+		? usPortCALCULATE_MINIMAL_STACK_SIZE()	\
+		: usCalcMinStackSize )
+
+/*
+ * WizC uses a downgrowing stack
+ */
+#define portSTACK_GROWTH			( -1 )
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro's that pushes all the registers that make up the context of a task onto
+ * the stack, then saves the new top of stack into the TCB. TOSU and TBLPTRU
+ * are only saved/restored on devices with more than 64kB (32k Words) ROM.
+ *
+ * The stackpointer is helt by WizC in FSR2 and points to the first free byte.
+ * WizC uses a "downgrowing" stack. There is no framepointer.
+ *
+ * We keep track of the interruptstatus using ucCriticalNesting. When this
+ * value equals zero, interrupts have to be enabled upon exit from the
+ * portRESTORE_CONTEXT macro.
+ *
+ * If this is called from an ISR then the interrupt enable bits must have been
+ * set for the ISR to ever get called.  Therefore we want to save
+ * ucCriticalNesting with value zero. This means the interrupts will again be
+ * re-enabled when the interrupted task is switched back in.
+ *
+ * If this is called from a manual context switch (i.e. from a call to yield),
+ * then we want to keep the current value of ucCritialNesting so it is restored
+ * with its current value. This allows a yield from within a critical section.
+ *
+ * The compiler uses some locations at the bottom of RAM for temporary
+ * storage. The compiler may also have been instructed to optimize
+ * function-parameters and local variables to global storage. The compiler
+ * uses an area called LocOpt for this wizC feature.
+ * The total overheadstorage has to be saved in it's entirety as part of
+ * a task context. These macro's store/restore from data address 0x0000 to
+ * (OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE - 1).
+ * OVERHEADPAGE0, LOCOPTSIZE and MAXLOCOPTSIZE are compiler-generated
+ * assembler definitions.
+ */
+
+#define	portSAVE_CONTEXT( ucInterruptForced )						\
+	do																\
+	{																\
+		portDISABLE_INTERRUPTS();									\
+																	\
+		_Pragma("asm")												\
+			;														\
+			; Push the relevant SFR's onto the task's stack			\
+			;														\
+			movff   STATUS,POSTDEC2									\
+			movff	WREG,POSTDEC2									\
+			movff	BSR,POSTDEC2									\
+			movff	PRODH,POSTDEC2									\
+			movff	PRODL,POSTDEC2									\
+			movff	FSR0H,POSTDEC2									\
+			movff	FSR0L,POSTDEC2									\
+			movff	FSR1H,POSTDEC2									\
+			movff	FSR1L,POSTDEC2									\
+			movff	TABLAT,POSTDEC2									\
+			if __ROMSIZE > 0x8000									\
+				movff	TBLPTRU,POSTDEC2							\
+			endif													\
+			movff	TBLPTRH,POSTDEC2								\
+			movff	TBLPTRL,POSTDEC2								\
+			if __ROMSIZE > 0x8000									\
+				movff	PCLATU,POSTDEC2								\
+			endif													\
+			movff	PCLATH,POSTDEC2									\
+			;														\
+			; Store the compiler-scratch-area as described above.	\
+			;														\
+			movlw	OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE			\
+			clrf	FSR0L,ACCESS									\
+			clrf	FSR0H,ACCESS									\
+		_rtos_S1:													\
+			movff	POSTINC0,POSTDEC2								\
+			decfsz	WREG,W,ACCESS									\
+			SMARTJUMP _rtos_S1										\
+			;														\
+			; Save the pic call/return-stack belonging to the		\
+			; current task by copying it to the task's software-	\
+			; stack. We save the hardware stack pointer (which		\
+			; is the number of addresses on the stack) in the		\
+			; W-register first because we need it later and it		\
+			; is modified in the save-loop by executing pop's.		\
+			; After the loop the W-register is stored on the		\
+			; stack, too.											\
+			;														\
+			movf	STKPTR,W,ACCESS									\
+			bz		_rtos_s3										\
+		_rtos_S2:													\
+			if __ROMSIZE > 0x8000									\
+				movff	TOSU,POSTDEC2								\
+			endif													\
+			movff	TOSH,POSTDEC2									\
+			movff	TOSL,POSTDEC2									\
+			pop														\
+			tstfsz	STKPTR,ACCESS									\
+			SMARTJUMP _rtos_S2										\
+		_rtos_s3:													\
+			movwf	POSTDEC2,ACCESS									\
+			;														\
+			; Next the value for ucCriticalNesting used by the		\
+			; task is stored on the stack. When						\
+			; (ucInterruptForced == portINTERRUPTS_FORCED), we save	\
+			; it as 0 (portNO_CRITICAL_SECTION_NESTING).			\
+			;														\
+			if ucInterruptForced == portINTERRUPTS_FORCED			\
+				clrf POSTDEC2,ACCESS								\
+			else													\
+				movff	ucCriticalNesting,POSTDEC2					\
+			endif													\
+			;														\
+			; Save the new top of the software stack in the TCB.	\
+			;														\
+			movff	pxCurrentTCB,FSR0L								\
+			movff	pxCurrentTCB+1,FSR0H							\
+			movff	FSR2L,POSTINC0									\
+			movff	FSR2H,POSTINC0									\
+		_Pragma("asmend")											\
+	} while(0)
+
+/************************************************************/
+
+/*
+ * This is the reverse of portSAVE_CONTEXT.
+ */
+#define portRESTORE_CONTEXT()										\
+	do																\
+	{																\
+		_Pragma("asm")												\
+			;														\
+			; Set FSR0 to point to pxCurrentTCB->pxTopOfStack.		\
+			;														\
+			movff	pxCurrentTCB,FSR0L								\
+			movff	pxCurrentTCB+1,FSR0H							\
+			;														\
+			; De-reference FSR0 to set the address it holds into	\
+			; FSR2 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). FSR2	\
+			; is used by wizC as stackpointer.						\
+			;														\
+			movff	POSTINC0,FSR2L									\
+			movff	POSTINC0,FSR2H									\
+			;														\
+			; Next, the value for ucCriticalNesting used by the		\
+			; task is retrieved from the stack.						\
+			;														\
+			movff	PREINC2,ucCriticalNesting						\
+			;														\
+			; Rebuild the pic call/return-stack. The number of		\
+			; return addresses is the next item on the task stack.	\
+			; Save this number in PRODL. Then fetch the addresses	\
+			; and store them on the hardwarestack.					\
+			; The datasheets say we can't use movff here...			\
+			;														\
+			movff	PREINC2,PRODL	// Use PRODL as tempregister	\
+			clrf	STKPTR,ACCESS									\
+		_rtos_R1:													\
+			push													\
+			movf	PREINC2,W,ACCESS								\
+			movwf	TOSL,ACCESS										\
+			movf	PREINC2,W,ACCESS								\
+			movwf	TOSH,ACCESS										\
+			if __ROMSIZE > 0x8000									\
+				movf	PREINC2,W,ACCESS							\
+				movwf	TOSU,ACCESS									\
+			else													\
+				clrf	TOSU,ACCESS									\
+			endif													\
+			decfsz	PRODL,F,ACCESS									\
+			SMARTJUMP _rtos_R1										\
+			;														\
+			; Restore the compiler's working storage area to page 0	\
+			;														\
+			movlw	OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE			\
+			movwf	FSR0L,ACCESS									\
+			clrf	FSR0H,ACCESS									\
+		_rtos_R2:													\
+			decf	FSR0L,F,ACCESS									\
+			movff	PREINC2,INDF0									\
+			tstfsz	FSR0L,ACCESS									\
+			SMARTJUMP _rtos_R2										\
+			;														\
+			; Restore the sfr's forming the tasks context.			\
+			; We cannot yet restore bsr, w and status because		\
+			; we need these	registers for a final test.				\
+			;														\
+			movff	PREINC2,PCLATH									\
+			if __ROMSIZE > 0x8000									\
+				movff	PREINC2,PCLATU								\
+			else													\
+				clrf	PCLATU,ACCESS								\
+			endif													\
+			movff	PREINC2,TBLPTRL									\
+			movff	PREINC2,TBLPTRH									\
+			if __ROMSIZE > 0x8000									\
+				movff	PREINC2,TBLPTRU								\
+			else													\
+				clrf	TBLPTRU,ACCESS								\
+			endif													\
+			movff	PREINC2,TABLAT									\
+			movff	PREINC2,FSR1L									\
+			movff	PREINC2,FSR1H									\
+			movff	PREINC2,FSR0L									\
+			movff	PREINC2,FSR0H									\
+			movff	PREINC2,PRODL									\
+			movff	PREINC2,PRODH									\
+			;														\
+			; The return from portRESTORE_CONTEXT() depends on		\
+			; the value of ucCriticalNesting. When it is zero,		\
+			; interrupts need to be enabled. This is done via a		\
+			; retfie instruction because we need the				\
+			; interrupt-enabling and the return to the restored		\
+			; task to be uninterruptable.							\
+	 		; Because bsr, status and W are affected by the test	\
+	 		; they are restored after the test.						\
+			;														\
+			movlb	ucCriticalNesting>>8							\
+			tstfsz	ucCriticalNesting,BANKED						\
+			SMARTJUMP _rtos_R4										\
+		_rtos_R3:													\
+			movff	PREINC2,BSR										\
+			movff	PREINC2,WREG									\
+			movff	PREINC2,STATUS									\
+			retfie	0		; Return enabling interrupts			\
+		_rtos_R4:													\
+			movff	PREINC2,BSR										\
+			movff	PREINC2,WREG									\
+			movff	PREINC2,STATUS									\
+			return	0		; Return without affecting interrupts	\
+		_Pragma("asmend")											\
+	} while(0)
+
+/*-----------------------------------------------------------*/
+
+#define portTICK_PERIOD_MS	( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+
+/*-----------------------------------------------------------*/
+
+extern void vPortYield( void );
+#define portYIELD()				vPortYield()
+
+#define portNOP()	_Pragma("asm")									\
+						nop											\
+					_Pragma("asmend")
+
+/*-----------------------------------------------------------*/
+
+#define portTASK_FUNCTION( xFunction, pvParameters )	 	\
+	void pointed xFunction( void *pvParameters )		\
+	_Pragma(asmfunc xFunction)
+
+#define portTASK_FUNCTION_PROTO		portTASK_FUNCTION
+/*-----------------------------------------------------------*/
+
+
+#define volatile
+#define register
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/port.c
new file mode 100644
index 0000000..460995e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/port.c
@@ -0,0 +1,246 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V1.00:
+	
+	+ Call to taskYIELD() from within tick ISR has been replaced by the more
+	  efficient portSWITCH_CONTEXT().
+	+ ISR function definitions renamed to include the prv prefix.
+
+Changes from V1.2.0:
+
+	+ portRESET_PIC() is now called last thing before the end of the preemptive
+	  tick routine.
+
+Changes from V2.6.1
+
+	+ Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+	  macro to be consistent with the later ports.
+*/
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the Flashlite 186
+ * port.
+ *----------------------------------------------------------*/
+
+#include <stdlib.h>
+#include <i86.h>
+#include <dos.h>
+#include <setjmp.h>
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portasm.h"
+
+/*lint -e950 Non ANSI reserved words okay in this file only. */
+
+#define portTIMER_EOI_TYPE		( 8 )
+#define portRESET_PIC()			portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
+#define portTIMER_INT_NUMBER	0x12
+
+#define portTIMER_1_CONTROL_REGISTER	( ( uint16_t ) 0xff5e )
+#define portTIMER_0_CONTROL_REGISTER	( ( uint16_t ) 0xff56 )
+#define portTIMER_INTERRUPT_ENABLE		( ( uint16_t ) 0x2000 )
+
+/* Setup the hardware to generate the required tick frequency. */
+static void prvSetTickFrequency( uint32_t ulTickRateHz );
+
+/* Set the hardware back to the state as per before the scheduler started. */
+static void prvExitFunction( void );
+
+#if configUSE_PREEMPTION == 1
+	/* Tick service routine used by the scheduler when preemptive scheduling is
+	being used. */
+	static void __interrupt __far prvPreemptiveTick( void );
+#else
+	/* Tick service routine used by the scheduler when cooperative scheduling is 
+	being used. */
+	static void __interrupt __far prvNonPreemptiveTick( void );
+#endif
+
+/* Trap routine used by taskYIELD() to manually cause a context switch. */
+static void __interrupt __far prvYieldProcessor( void );
+
+/*lint -e956 File scopes necessary here. */
+
+/* Set true when the vectors are set so the scheduler will service the tick. */
+static int16_t sSchedulerRunning = pdFALSE;
+
+/* Points to the original routine installed on the vector we use for manual context switches.  This is then used to restore the original routine during prvExitFunction(). */
+static void ( __interrupt __far *pxOldSwitchISR )();
+
+/* Used to restore the original DOS context when the scheduler is ended. */
+static jmp_buf xJumpBuf;
+
+/*lint +e956 */
+
+/*-----------------------------------------------------------*/
+BaseType_t xPortStartScheduler( void )
+{
+	/* This is called with interrupts already disabled. */
+
+	/* Remember what was on the interrupts we are going to use
+	so we can put them back later if required. */
+	pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
+
+	/* Put our manual switch (yield) function on a known
+	vector. */
+	_dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+
+	#if configUSE_PREEMPTION == 1
+	{		
+		/* Put our tick switch function on the timer interrupt. */
+		_dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
+	}
+	#else
+	{
+		/* We want the timer interrupt to just increment the tick count. */
+		_dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
+	}
+	#endif
+
+	prvSetTickFrequency( configTICK_RATE_HZ );
+
+	/* Clean up function if we want to return to DOS. */
+	if( setjmp( xJumpBuf ) != 0 )
+	{
+		prvExitFunction();
+		sSchedulerRunning = pdFALSE;
+	}
+	else
+	{
+		sSchedulerRunning = pdTRUE;
+
+		/* Kick off the scheduler by setting up the context of the first task. */
+		portFIRST_CONTEXT();
+	}
+
+	return sSchedulerRunning;
+}
+/*-----------------------------------------------------------*/
+
+/* The tick ISR used depend on whether or not the preemptive or cooperative
+kernel is being used. */
+#if configUSE_PREEMPTION == 1
+	static void __interrupt __far prvPreemptiveTick( void )
+	{
+		/* Get the scheduler to update the task states following the tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Switch in the context of the next task to be run. */
+			portSWITCH_CONTEXT();
+		}
+
+		/* Reset the PIC ready for the next time. */
+		portRESET_PIC();
+	}
+#else
+	static void __interrupt __far prvNonPreemptiveTick( void )
+	{
+		/* Same as preemptive tick, but the cooperative scheduler is being used
+		so we don't have to switch in the context of the next task. */
+		xTaskIncrementTick();
+		portRESET_PIC();
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+static void __interrupt __far prvYieldProcessor( void )
+{
+	/* Switch in the context of the next task to be run. */
+	portSWITCH_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Jump back to the processor state prior to starting the
+	scheduler.  This means we are not going to be using a
+	task stack frame so the task can be deleted. */
+	longjmp( xJumpBuf, 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvExitFunction( void )
+{
+const uint16_t usTimerDisable = 0x0000;
+uint16_t usTimer0Control;
+
+	/* Interrupts should be disabled here anyway - but no 
+	harm in making sure. */
+	portDISABLE_INTERRUPTS();
+	if( sSchedulerRunning == pdTRUE )
+	{
+		/* Put back the switch interrupt routines that was in place
+		before the scheduler started. */
+		_dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
+	}
+
+	/* Disable the timer used for the tick to ensure the scheduler is
+	not called before restoring interrupts.  There was previously nothing
+	on this timer so there is no old ISR to restore. */
+	portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );
+
+	/* Restart the DOS tick. */
+	usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
+	usTimer0Control |= portTIMER_INTERRUPT_ENABLE;
+	portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
+
+
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetTickFrequency( uint32_t ulTickRateHz )
+{
+const uint16_t usMaxCountRegister = 0xff5a;
+const uint16_t usTimerPriorityRegister = 0xff32;
+const uint16_t usTimerEnable = 0xC000;
+const uint16_t usRetrigger = 0x0001;
+const uint16_t usTimerHighPriority = 0x0000;
+uint16_t usTimer0Control;
+
+/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */
+
+const uint32_t ulClockFrequency = 0x7f31a0;
+
+uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
+
+	portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger );
+	portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount );
+	portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority );
+
+	/* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */
+	usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
+	usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE;
+	portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
+}
+
+
+/*lint +e950 */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
new file mode 100644
index 0000000..6b8f259
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
@@ -0,0 +1,110 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+
+/* Type definitions. */
+#define portCHAR        char
+#define portFLOAT       float
+#define portDOUBLE      long
+#define portLONG        long
+#define portSHORT       int
+#define portSTACK_TYPE  uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+        typedef uint16_t TickType_t;
+        #define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+        typedef uint32_t TickType_t;
+        #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+void portENTER_CRITICAL( void );
+#pragma aux portENTER_CRITICAL = "pushf" \
+                                 "cli";
+
+void portEXIT_CRITICAL( void );
+#pragma aux portEXIT_CRITICAL   = "popf";
+
+void portDISABLE_INTERRUPTS( void );
+#pragma aux portDISABLE_INTERRUPTS = "cli";
+
+void portENABLE_INTERRUPTS( void );
+#pragma aux portENABLE_INTERRUPTS = "sti";
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH        ( -1 )
+#define portSWITCH_INT_NUMBER   0x80
+#define portYIELD()             __asm{ int portSWITCH_INT_NUMBER }
+#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT      2
+#define portINITIAL_SW          ( ( portSTACK_TYPE ) 0x0202 )   /* Start the tasks with interrupts enabled. */
+#define portNOP()				__asm{ nop }
+/*-----------------------------------------------------------*/
+
+/* Compiler specifics. */
+#define portINPUT_BYTE( xAddr )                 inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )       outp( xAddr, ucValue )
+#define portINPUT_WORD( xAddr )                 inpw( xAddr )
+#define portOUTPUT_WORD( xAddr, usValue )       outpw( xAddr, usValue )
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/port.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/port.c
new file mode 100644
index 0000000..97aabd7
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/port.c
@@ -0,0 +1,302 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V1.00:
+	
+	+ Call to taskYIELD() from within tick ISR has been replaced by the more
+	  efficient portSWITCH_CONTEXT().
+	+ ISR function definitions renamed to include the prv prefix.
+
+Changes from V1.2.0:
+
+	+ prvPortResetPIC() is now called last thing before the end of the 
+	  preemptive tick routine.
+
+Changes from V2.6.1
+
+	+ Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
+	  macro to be consistent with the later ports.
+
+Changes from V4.0.1
+	
+	+ Add function prvSetTickFrequencyDefault() to set the DOS tick back to
+	  its proper value when the scheduler exits. 
+*/
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <i86.h>
+#include <dos.h>
+#include <setjmp.h>
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "portasm.h"
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the industrial
+ * PC port.
+ *----------------------------------------------------------*/
+
+/*lint -e950 Non ANSI reserved words okay in this file only. */
+
+#define portTIMER_INT_NUMBER	0x08
+
+/* Setup hardware for required tick interrupt rate. */
+static void prvSetTickFrequency( uint32_t ulTickRateHz );
+
+/* Restore hardware to as it was prior to starting the scheduler. */
+static void prvExitFunction( void );
+
+/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC
+directly.  We chain to the DOS tick as close as possible to the standard DOS
+tick rate. */
+static void prvPortResetPIC( void );
+
+/* The tick ISR used depends on whether the preemptive or cooperative scheduler
+is being used. */
+#if configUSE_PREEMPTION == 1
+	/* Tick service routine used by the scheduler when preemptive scheduling is
+	being used. */
+	static void __interrupt __far prvPreemptiveTick( void );
+#else
+	/* Tick service routine used by the scheduler when cooperative scheduling is 
+	being used. */
+	static void __interrupt __far prvNonPreemptiveTick( void );
+#endif
+/* Trap routine used by taskYIELD() to manually cause a context switch. */
+static void __interrupt __far prvYieldProcessor( void );
+
+/* Set the tick frequency back so the floppy drive works correctly when the
+scheduler exits. */
+static void prvSetTickFrequencyDefault( void );
+
+/*lint -e956 File scopes necessary here. */
+
+/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */
+static int16_t sDOSTickCounter;							
+
+/* Set true when the vectors are set so the scheduler will service the tick. */
+static int16_t sSchedulerRunning = pdFALSE;				
+
+/* Points to the original routine installed on the vector we use for manual context switches.  This is then used to restore the original routine during prvExitFunction(). */
+static void ( __interrupt __far *pxOldSwitchISR )();		
+
+/* Points to the original routine installed on the vector we use to chain to the DOS tick.  This is then used to restore the original routine during prvExitFunction(). */
+static void ( __interrupt __far *pxOldSwitchISRPlus1 )();	
+
+/* Used to restore the original DOS context when the scheduler is ended. */
+static jmp_buf xJumpBuf;
+
+/*lint +e956 */
+
+/*-----------------------------------------------------------*/
+BaseType_t xPortStartScheduler( void )
+{
+pxISR pxOriginalTickISR;
+	
+	/* This is called with interrupts already disabled. */
+
+	/* Remember what was on the interrupts we are going to use
+	so we can put them back later if required. */
+	pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
+	pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );
+	pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
+
+	prvSetTickFrequency( configTICK_RATE_HZ );
+
+	/* Put our manual switch (yield) function on a known
+	vector. */
+	_dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
+
+	/* Put the old tick on a different interrupt number so we can
+	call it when we want. */
+	_dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );
+
+	#if configUSE_PREEMPTION == 1
+	{		
+		/* Put our tick switch function on the timer interrupt. */
+		_dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
+	}
+	#else
+	{
+		/* We want the timer interrupt to just increment the tick count. */
+		_dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
+	}
+	#endif
+
+	/* Setup a counter that is used to call the DOS interrupt as close
+	to it's original frequency as can be achieved given our chosen tick
+	frequency. */
+	sDOSTickCounter = portTICKS_PER_DOS_TICK;
+
+	/* Clean up function if we want to return to DOS. */
+	if( setjmp( xJumpBuf ) != 0 )
+	{
+		prvExitFunction();
+		sSchedulerRunning = pdFALSE;
+	}
+	else
+	{
+		sSchedulerRunning = pdTRUE;
+
+		/* Kick off the scheduler by setting up the context of the first task. */
+		portFIRST_CONTEXT();
+	}
+
+	return sSchedulerRunning;
+}
+/*-----------------------------------------------------------*/
+
+/* The tick ISR used depends on whether the preemptive or cooperative scheduler
+is being used. */
+#if configUSE_PREEMPTION == 1
+	/* Tick service routine used by the scheduler when preemptive scheduling is
+	being used. */
+	static void __interrupt __far prvPreemptiveTick( void )
+	{
+		/* Get the scheduler to update the task states following the tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* Switch in the context of the next task to be run. */
+			portSWITCH_CONTEXT();
+		}
+
+		/* Reset the PIC ready for the next time. */
+		prvPortResetPIC();
+	}
+#else
+	static void __interrupt __far prvNonPreemptiveTick( void )
+	{
+		/* Same as preemptive tick, but the cooperative scheduler is being used
+		so we don't have to switch in the context of the next task. */
+		xTaskIncrementTick();
+		prvPortResetPIC();
+	}
+#endif
+/*-----------------------------------------------------------*/
+
+
+static void __interrupt __far prvYieldProcessor( void )
+{
+	/* Switch in the context of the next task to be run. */
+	portSWITCH_CONTEXT();
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortResetPIC( void )
+{
+	/* We are going to call the DOS tick interrupt at as close a
+	frequency to the normal DOS tick as possible. */
+
+	/* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */
+	--sDOSTickCounter;
+	if( sDOSTickCounter <= 0 )
+	{
+		sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK;
+		__asm{ int	portSWITCH_INT_NUMBER + 1 };		 
+	}
+	else
+	{
+		/* Reset the PIC as the DOS tick is not being called to
+		do it. */
+		__asm
+		{
+			mov	al, 20H
+			out 20H, al
+		};
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Jump back to the processor state prior to starting the
+	scheduler.  This means we are not going to be using a
+	task stack frame so the task can be deleted. */
+	longjmp( xJumpBuf, 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvExitFunction( void )
+{
+void ( __interrupt __far *pxOriginalTickISR )();
+
+	/* Interrupts should be disabled here anyway - but no 
+	harm in making sure. */
+	portDISABLE_INTERRUPTS();
+	if( sSchedulerRunning == pdTRUE )
+	{
+		/* Set the DOS tick back onto the timer ticker. */
+		pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
+		_dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR );
+		prvSetTickFrequencyDefault();
+
+		/* Put back the switch interrupt routines that was in place
+		before the scheduler started. */
+		_dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
+		_dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );
+	}
+	/* The tick timer is back how DOS wants it.  We can re-enable
+	interrupts without the scheduler being called. */
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetTickFrequency( uint32_t ulTickRateHz )
+{
+const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+const uint16_t usPIT0 = ( uint16_t ) 0x40;
+const uint32_t ulPIT_CONST = ( uint32_t ) 1193180;
+const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+uint32_t ulOutput;
+
+	/* Setup the 8245 to tick at the wanted frequency. */
+	portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
+	ulOutput = ulPIT_CONST / ulTickRateHz;
+   
+	portOUTPUT_BYTE( usPIT0, ( uint16_t )( ulOutput & ( uint32_t ) 0xff ) );
+	ulOutput >>= 8;
+	portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
+}
+/*-----------------------------------------------------------*/
+
+static void prvSetTickFrequencyDefault( void )
+{
+const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
+const uint16_t usPIT0 = ( uint16_t ) 0x40;
+const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
+
+	portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
+	portOUTPUT_BYTE( usPIT0,0 );
+	portOUTPUT_BYTE( usPIT0,0 );
+}
+
+
+/*lint +e950 */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/portmacro.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/portmacro.h
new file mode 100644
index 0000000..fd53224
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/portmacro.h
@@ -0,0 +1,112 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		int
+#define portSTACK_TYPE	uint16_t
+#define portBASE_TYPE	short
+
+typedef portSTACK_TYPE StackType_t;
+typedef short BaseType_t;
+typedef unsigned short UBaseType_t;
+
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+#endif
+/*-----------------------------------------------------------*/
+
+/* Critical section definitions.  portENTER_CRITICAL() must be defined as a
+macro for portable.h to work properly. */
+void portLOCAL_ENTER_CRITICAL( void );
+#pragma aux portLOCAL_ENTER_CRITICAL = 	"pushf" \
+										"cli";
+#define portENTER_CRITICAL() portLOCAL_ENTER_CRITICAL()
+
+void portEXIT_CRITICAL( void );
+#pragma aux portEXIT_CRITICAL	=		"popf";
+
+void portDISABLE_INTERRUPTS( void );
+#pragma aux portDISABLE_INTERRUPTS =	"cli";
+
+void portENABLE_INTERRUPTS( void );
+#pragma aux portENABLE_INTERRUPTS =		"sti";
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH		( -1 )
+#define portSWITCH_INT_NUMBER 	0x80
+#define portYIELD()				__asm{ int portSWITCH_INT_NUMBER }
+#define portDOS_TICK_RATE		( 18.20648 )
+#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portTICKS_PER_DOS_TICK	( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
+#define portINITIAL_SW			( ( portSTACK_TYPE ) 0x0202 )	/* Start the tasks with interrupts enabled. */
+#define portBYTE_ALIGNMENT		( 2 )
+/*-----------------------------------------------------------*/
+
+/* Compiler specifics. */
+#define portINPUT_BYTE( xAddr )				inp( xAddr )
+#define portOUTPUT_BYTE( xAddr, ucValue )	outp( xAddr, ucValue )
+#define portNOP() __asm{ nop }
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site. */
+#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
+#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* PORTMACRO_H */
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portasm.h b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portasm.h
new file mode 100644
index 0000000..50a724c
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portasm.h
@@ -0,0 +1,110 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+typedef void TCB_t;
+extern volatile TCB_t * volatile pxCurrentTCB;
+extern void vTaskSwitchContext( void );
+
+/* 
+ * Saves the stack pointer for one task into its TCB, calls 
+ * vTaskSwitchContext() to update the TCB being used, then restores the stack 
+ * from the new TCB read to run the task. 
+ */
+void portSWITCH_CONTEXT( void );
+
+/*
+ * Load the stack pointer from the TCB of the task which is going to be first
+ * to execute.  Then force an IRET so the registers and IP are popped off the
+ * stack.
+ */
+void portFIRST_CONTEXT( void );
+
+/* There are slightly different versions depending on whether you are building
+to include debugger information.  If debugger information is used then there
+are a couple of extra bytes left of the ISR stack (presumably for use by the
+debugger).  The true stack pointer is then stored in the bp register.  We add
+2 to the stack pointer to remove the extra bytes before we restore our context. */
+
+#ifdef DEBUG_BUILD
+
+	#pragma aux portSWITCH_CONTEXT =	"mov	ax, seg pxCurrentTCB"														\
+										"mov	ds, ax"																		\
+										"les	bx, pxCurrentTCB"			/* Save the stack pointer into the TCB. */		\
+										"mov	es:0x2[ bx ], ss"															\
+										"mov	es:[ bx ], sp"																\
+										"call	vTaskSwitchContext"			/* Perform the switch. */						\
+										"mov	ax, seg pxCurrentTCB"		/* Restore the stack pointer from the TCB. */	\
+										"mov	ds, ax"																		\
+										"les	bx, dword ptr pxCurrentTCB"													\
+										"mov	ss, es:[ bx + 2 ]"															\
+										"mov	sp, es:[ bx ]"																\
+										"mov	bp, sp"						/* Prepair the bp register for the restoration of the SP in the compiler generated portion of the ISR */	\
+										"add	bp, 0x0002"
+
+										
+
+	#pragma aux portFIRST_CONTEXT =		"mov	ax, seg pxCurrentTCB"			\
+										"mov	ds, ax"							\
+										"les	bx, dword ptr pxCurrentTCB"		\
+										"mov	ss, es:[ bx + 2 ]"				\
+										"mov	sp, es:[ bx ]"					\
+										"add	sp, 0x0002"						/* Remove the extra bytes that exist in debug builds before restoring the context. */ \
+										"pop	ax"								\
+										"pop	ax"								\
+										"pop	es"								\
+										"pop	ds"								\
+										"popa"									\
+										"iret"									
+#else
+
+	#pragma aux portSWITCH_CONTEXT =	"mov	ax, seg pxCurrentTCB"														\
+										"mov	ds, ax"																		\
+										"les	bx, pxCurrentTCB"			/* Save the stack pointer into the TCB. */		\
+										"mov	es:0x2[ bx ], ss"															\
+										"mov	es:[ bx ], sp"																\
+										"call	vTaskSwitchContext"			/* Perform the switch. */						\
+										"mov	ax, seg pxCurrentTCB"		/* Restore the stack pointer from the TCB. */	\
+										"mov	ds, ax"																		\
+										"les	bx, dword ptr pxCurrentTCB"													\
+										"mov	ss, es:[ bx + 2 ]"															\
+										"mov	sp, es:[ bx ]"
+										
+
+	#pragma aux portFIRST_CONTEXT =		"mov	ax, seg pxCurrentTCB"			\
+										"mov	ds, ax"							\
+										"les	bx, dword ptr pxCurrentTCB"		\
+										"mov	ss, es:[ bx + 2 ]"				\
+										"mov	sp, es:[ bx ]"					\
+										"pop	ax"								\
+										"pop	ax"								\
+										"pop	es"								\
+										"pop	ds"								\
+										"popa"									\
+										"iret"									
+#endif
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portcomn.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portcomn.c
new file mode 100644
index 0000000..2b00fe0
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portcomn.c
@@ -0,0 +1,141 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ * 1 tab == 4 spaces!
+ */
+
+/*
+Changes from V1.00:
+	
+	+ pxPortInitialiseStack() now initialises the stack of new tasks to the 
+	  same format used by the compiler.  This allows the compiler generated
+	  interrupt mechanism to be used for context switches.
+
+Changes from V2.4.2:
+
+	+ pvPortMalloc and vPortFree have been removed.  The projects now use
+	  the definitions from the source/portable/MemMang directory.
+
+Changes from V2.6.1:
+
+	+ usPortCheckFreeStackSpace() has been moved to tasks.c.
+*/
+
+	
+
+#include <stdlib.h>
+#include "FreeRTOS.h"
+
+/*-----------------------------------------------------------*/
+
+/* See header file for description. */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+StackType_t DS_Reg = 0, *pxOriginalSP;
+
+	/* Place a few bytes of known values on the bottom of the stack. 
+	This is just useful for debugging. */
+
+	*pxTopOfStack = 0x1111;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x2222;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x3333;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x4444;
+	pxTopOfStack--;
+	*pxTopOfStack = 0x5555;
+	pxTopOfStack--;
+
+
+	/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
+
+	/* We are going to start the scheduler using a return from interrupt
+	instruction to load the program counter, so first there would be the
+	status register and interrupt return address.  We make this the start 
+	of the task. */
+	*pxTopOfStack = portINITIAL_SW; 
+	pxTopOfStack--;
+	*pxTopOfStack = FP_SEG( pxCode );
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pxCode );
+	pxTopOfStack--;
+
+	/* We are going to setup the stack for the new task to look like
+	the stack frame was setup by a compiler generated ISR.  We need to know
+	the address of the existing stack top to place in the SP register within
+	the stack frame.  pxOriginalSP holds SP before (simulated) pusha was 
+	called. */
+	pxOriginalSP = pxTopOfStack;
+
+	/* The remaining registers would be pushed on the stack by our context 
+	switch function.  These are loaded with values simply to make debugging
+	easier. */
+	*pxTopOfStack = FP_OFF( pvParameters );		/* AX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xCCCC;	/* CX */
+	pxTopOfStack--;
+	*pxTopOfStack = FP_SEG( pvParameters );		/* DX */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BX */
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pxOriginalSP );		/* SP */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BP */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0x0123;	/* SI */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DI */
+
+	/* We need the true data segment. */
+	__asm{	MOV DS_Reg, DS };
+
+	pxTopOfStack--;
+	*pxTopOfStack = DS_Reg;	/* DS */
+
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) 0xEEEE;	/* ES */
+
+	/* The AX register is pushed again twice - don't know why. */
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pvParameters );		/* AX */
+	pxTopOfStack--;
+	*pxTopOfStack = FP_OFF( pvParameters );		/* AX */
+
+
+	#ifdef DEBUG_BUILD
+		/* The compiler adds space to each ISR stack if building to
+		include debug information.  Presumably this is used by the
+		debugger - we don't need to initialise it to anything just
+		make sure it is there. */
+		pxTopOfStack--;
+	#endif
+
+	/*lint +e950 +e611 +e923 */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/readme.txt b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/readme.txt
new file mode 100644
index 0000000..af93a4b
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/portable/readme.txt
@@ -0,0 +1,20 @@
+Each real time kernel port consists of three files that contain the core kernel
+components and are common to every port, and one or more files that are
+specific to a particular microcontroller and/or compiler.
+
+
++ The FreeRTOS/Source/Portable/MemMang directory contains the five sample
+memory allocators as described on the https://www.FreeRTOS.org WEB site.
+
++ The other directories each contain files specific to a particular
+microcontroller or compiler, where the directory name denotes the compiler
+specific files the directory contains.
+
+
+
+For example, if you are interested in the [compiler] port for the [architecture]
+microcontroller, then the port specific files are contained in
+FreeRTOS/Source/Portable/[compiler]/[architecture] directory.  If this is the
+only port you are interested in then all the other directories can be
+ignored.
+
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/queue.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/queue.c
new file mode 100644
index 0000000..7ed8e98
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/queue.c
@@ -0,0 +1,3016 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+#include <stdlib.h>
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+#if ( configUSE_CO_ROUTINES == 1 )
+    #include "croutine.h"
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+ * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+ * for the header files above, but not in this file, in order to generate the
+ * correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+
+/* Constants used with the cRxLock and cTxLock structure members. */
+#define queueUNLOCKED             ( ( int8_t ) -1 )
+#define queueLOCKED_UNMODIFIED    ( ( int8_t ) 0 )
+#define queueINT8_MAX             ( ( int8_t ) 127 )
+
+/* When the Queue_t structure is used to represent a base queue its pcHead and
+ * pcTail members are used as pointers into the queue storage area.  When the
+ * Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
+ * not necessary, and the pcHead pointer is set to NULL to indicate that the
+ * structure instead holds a pointer to the mutex holder (if any).  Map alternative
+ * names to the pcHead and structure member to ensure the readability of the code
+ * is maintained.  The QueuePointers_t and SemaphoreData_t types are used to form
+ * a union as their usage is mutually exclusive dependent on what the queue is
+ * being used for. */
+#define uxQueueType               pcHead
+#define queueQUEUE_IS_MUTEX       NULL
+
+typedef struct QueuePointers
+{
+    int8_t * pcTail;     /*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+    int8_t * pcReadFrom; /*< Points to the last place that a queued item was read from when the structure is used as a queue. */
+} QueuePointers_t;
+
+typedef struct SemaphoreData
+{
+    TaskHandle_t xMutexHolder;        /*< The handle of the task that holds the mutex. */
+    UBaseType_t uxRecursiveCallCount; /*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+} SemaphoreData_t;
+
+/* Semaphores do not actually store or copy data, so have an item size of
+ * zero. */
+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH    ( ( UBaseType_t ) 0 )
+#define queueMUTEX_GIVE_BLOCK_TIME          ( ( TickType_t ) 0U )
+
+#if ( configUSE_PREEMPTION == 0 )
+
+/* If the cooperative scheduler is being used then a yield should not be
+ * performed just because a higher priority task has been woken. */
+    #define queueYIELD_IF_USING_PREEMPTION()
+#else
+    #define queueYIELD_IF_USING_PREEMPTION()    portYIELD_WITHIN_API()
+#endif
+
+/*
+ * Definition of the queue used by the scheduler.
+ * Items are queued by copy, not reference.  See the following link for the
+ * rationale: https://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ */
+typedef struct QueueDefinition /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+    int8_t * pcHead;           /*< Points to the beginning of the queue storage area. */
+    int8_t * pcWriteTo;        /*< Points to the free next place in the storage area. */
+
+    union
+    {
+        QueuePointers_t xQueue;     /*< Data required exclusively when this structure is used as a queue. */
+        SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */
+    } u;
+
+    List_t xTasksWaitingToSend;             /*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
+    List_t xTasksWaitingToReceive;          /*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */
+
+    volatile UBaseType_t uxMessagesWaiting; /*< The number of items currently in the queue. */
+    UBaseType_t uxLength;                   /*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
+    UBaseType_t uxItemSize;                 /*< The size of each items that the queue will hold. */
+
+    volatile int8_t cRxLock;                /*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+    volatile int8_t cTxLock;                /*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+
+    #if ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+        uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
+    #endif
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+        struct QueueDefinition * pxQueueSetContainer;
+    #endif
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxQueueNumber;
+        uint8_t ucQueueType;
+    #endif
+} xQUEUE;
+
+/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
+ * name below to enable the use of older kernel aware debuggers. */
+typedef xQUEUE Queue_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The queue registry is just a means for kernel aware debuggers to locate
+ * queue structures.  It has no other purpose so is an optional component.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+/* The type stored within the queue registry array.  This allows a name
+ * to be assigned to each queue making kernel aware debugging a little
+ * more user friendly. */
+    typedef struct QUEUE_REGISTRY_ITEM
+    {
+        const char * pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+        QueueHandle_t xHandle;
+    } xQueueRegistryItem;
+
+/* The old xQueueRegistryItem name is maintained above then typedefed to the
+ * new xQueueRegistryItem name below to enable the use of older kernel aware
+ * debuggers. */
+    typedef xQueueRegistryItem QueueRegistryItem_t;
+
+/* The queue registry is simply an array of QueueRegistryItem_t structures.
+ * The pcQueueName member of a structure being NULL is indicative of the
+ * array position being vacant. */
+    PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+
+/*
+ * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not
+ * prevent an ISR from adding or removing items to the queue, but does prevent
+ * an ISR from removing tasks from the queue event lists.  If an ISR finds a
+ * queue is locked it will instead increment the appropriate queue lock count
+ * to indicate that a task may require unblocking.  When the queue in unlocked
+ * these lock counts are inspected, and the appropriate action taken.
+ */
+static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any data in a queue.
+ *
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
+ */
+static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any space in a queue.
+ *
+ * @return pdTRUE if there is no space, otherwise pdFALSE;
+ */
+static BaseType_t prvIsQueueFull( const Queue_t * pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item into the queue, either at the front of the queue or the
+ * back of the queue.
+ */
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue,
+                                      const void * pvItemToQueue,
+                                      const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item out of a queue.
+ */
+static void prvCopyDataFromQueue( Queue_t * const pxQueue,
+                                  void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+/*
+ * Checks to see if a queue is a member of a queue set, and if so, notifies
+ * the queue set that the queue contains data.
+ */
+    static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Called after a Queue_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
+                                   const UBaseType_t uxItemSize,
+                                   uint8_t * pucQueueStorage,
+                                   const uint8_t ucQueueType,
+                                   Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Mutexes are a special type of queue.  When a mutex is created, first the
+ * queue is created, then prvInitialiseMutex() is called to configure the queue
+ * as a mutex.
+ */
+#if ( configUSE_MUTEXES == 1 )
+    static void prvInitialiseMutex( Queue_t * pxNewQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+#if ( configUSE_MUTEXES == 1 )
+
+/*
+ * If a task waiting for a mutex causes the mutex holder to inherit a
+ * priority, but the waiting task times out, then the holder should
+ * disinherit the priority - but only down to the highest priority of any
+ * other tasks that are waiting for the same mutex.  This function returns
+ * that priority.
+ */
+    static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+#endif
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to mark a queue as locked.  Locking a queue prevents an ISR from
+ * accessing the queue event lists.
+ */
+#define prvLockQueue( pxQueue )                            \
+    taskENTER_CRITICAL();                                  \
+    {                                                      \
+        if( ( pxQueue )->cRxLock == queueUNLOCKED )        \
+        {                                                  \
+            ( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED; \
+        }                                                  \
+        if( ( pxQueue )->cTxLock == queueUNLOCKED )        \
+        {                                                  \
+            ( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED; \
+        }                                                  \
+    }                                                      \
+    taskEXIT_CRITICAL()
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue,
+                               BaseType_t xNewQueue )
+{
+    Queue_t * const pxQueue = xQueue;
+
+    configASSERT( pxQueue );
+
+    taskENTER_CRITICAL();
+    {
+        pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+        pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+        pxQueue->pcWriteTo = pxQueue->pcHead;
+        pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+        pxQueue->cRxLock = queueUNLOCKED;
+        pxQueue->cTxLock = queueUNLOCKED;
+
+        if( xNewQueue == pdFALSE )
+        {
+            /* If there are tasks blocked waiting to read from the queue, then
+             * the tasks will remain blocked as after this function exits the queue
+             * will still be empty.  If there are tasks blocked waiting to write to
+             * the queue, then one should be unblocked as after this function exits
+             * it will be possible to write to it. */
+            if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+            {
+                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+                {
+                    queueYIELD_IF_USING_PREEMPTION();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            /* Ensure the event queues start in the correct state. */
+            vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
+            vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
+        }
+    }
+    taskEXIT_CRITICAL();
+
+    /* A value is returned for calling semantic consistency with previous
+     * versions. */
+    return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+    QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength,
+                                             const UBaseType_t uxItemSize,
+                                             uint8_t * pucQueueStorage,
+                                             StaticQueue_t * pxStaticQueue,
+                                             const uint8_t ucQueueType )
+    {
+        Queue_t * pxNewQueue;
+
+        configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+        /* The StaticQueue_t structure and the queue storage area must be
+         * supplied. */
+        configASSERT( pxStaticQueue != NULL );
+
+        /* A queue storage area should be provided if the item size is not 0, and
+         * should not be provided if the item size is 0. */
+        configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
+        configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
+
+        #if ( configASSERT_DEFINED == 1 )
+            {
+                /* Sanity check that the size of the structure used to declare a
+                 * variable of type StaticQueue_t or StaticSemaphore_t equals the size of
+                 * the real queue and semaphore structures. */
+                volatile size_t xSize = sizeof( StaticQueue_t );
+                configASSERT( xSize == sizeof( Queue_t ) );
+                ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+            }
+        #endif /* configASSERT_DEFINED */
+
+        /* The address of a statically allocated queue was passed in, use it.
+         * The address of a statically allocated storage area was also passed in
+         * but is already set. */
+        pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+
+        if( pxNewQueue != NULL )
+        {
+            #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+                {
+                    /* Queues can be allocated wither statically or dynamically, so
+                     * note this queue was allocated statically in case the queue is
+                     * later deleted. */
+                    pxNewQueue->ucStaticallyAllocated = pdTRUE;
+                }
+            #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+            prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+        }
+        else
+        {
+            traceQUEUE_CREATE_FAILED( ucQueueType );
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        return pxNewQueue;
+    }
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+    QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength,
+                                       const UBaseType_t uxItemSize,
+                                       const uint8_t ucQueueType )
+    {
+        Queue_t * pxNewQueue;
+        size_t xQueueSizeInBytes;
+        uint8_t * pucQueueStorage;
+
+        configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+        /* Allocate enough space to hold the maximum number of items that
+         * can be in the queue at any time.  It is valid for uxItemSize to be
+         * zero in the case the queue is used as a semaphore. */
+        xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+        /* Check for multiplication overflow. */
+        configASSERT( ( uxItemSize == 0 ) || ( uxQueueLength == ( xQueueSizeInBytes / uxItemSize ) ) );
+
+        /* Check for addition overflow. */
+        configASSERT( ( sizeof( Queue_t ) + xQueueSizeInBytes ) >  xQueueSizeInBytes );
+
+        /* Allocate the queue and storage area.  Justification for MISRA
+         * deviation as follows:  pvPortMalloc() always ensures returned memory
+         * blocks are aligned per the requirements of the MCU stack.  In this case
+         * pvPortMalloc() must return a pointer that is guaranteed to meet the
+         * alignment requirements of the Queue_t structure - which in this case
+         * is an int8_t *.  Therefore, whenever the stack alignment requirements
+         * are greater than or equal to the pointer to char requirements the cast
+         * is safe.  In other cases alignment requirements are not strict (one or
+         * two bytes). */
+        pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
+
+        if( pxNewQueue != NULL )
+        {
+            /* Jump past the queue structure to find the location of the queue
+             * storage area. */
+            pucQueueStorage = ( uint8_t * ) pxNewQueue;
+            pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
+
+            #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+                {
+                    /* Queues can be created either statically or dynamically, so
+                     * note this task was created dynamically in case it is later
+                     * deleted. */
+                    pxNewQueue->ucStaticallyAllocated = pdFALSE;
+                }
+            #endif /* configSUPPORT_STATIC_ALLOCATION */
+
+            prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+        }
+        else
+        {
+            traceQUEUE_CREATE_FAILED( ucQueueType );
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        return pxNewQueue;
+    }
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength,
+                                   const UBaseType_t uxItemSize,
+                                   uint8_t * pucQueueStorage,
+                                   const uint8_t ucQueueType,
+                                   Queue_t * pxNewQueue )
+{
+    /* Remove compiler warnings about unused parameters should
+     * configUSE_TRACE_FACILITY not be set to 1. */
+    ( void ) ucQueueType;
+
+    if( uxItemSize == ( UBaseType_t ) 0 )
+    {
+        /* No RAM was allocated for the queue storage area, but PC head cannot
+         * be set to NULL because NULL is used as a key to say the queue is used as
+         * a mutex.  Therefore just set pcHead to point to the queue as a benign
+         * value that is known to be within the memory map. */
+        pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
+    }
+    else
+    {
+        /* Set the head to the start of the queue storage area. */
+        pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
+    }
+
+    /* Initialise the queue members as described where the queue type is
+     * defined. */
+    pxNewQueue->uxLength = uxQueueLength;
+    pxNewQueue->uxItemSize = uxItemSize;
+    ( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        {
+            pxNewQueue->ucQueueType = ucQueueType;
+        }
+    #endif /* configUSE_TRACE_FACILITY */
+
+    #if ( configUSE_QUEUE_SETS == 1 )
+        {
+            pxNewQueue->pxQueueSetContainer = NULL;
+        }
+    #endif /* configUSE_QUEUE_SETS */
+
+    traceQUEUE_CREATE( pxNewQueue );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+    static void prvInitialiseMutex( Queue_t * pxNewQueue )
+    {
+        if( pxNewQueue != NULL )
+        {
+            /* The queue create function will set all the queue structure members
+            * correctly for a generic queue, but this function is creating a
+            * mutex.  Overwrite those members that need to be set differently -
+            * in particular the information required for priority inheritance. */
+            pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
+            pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
+
+            /* In case this is a recursive mutex. */
+            pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
+
+            traceCREATE_MUTEX( pxNewQueue );
+
+            /* Start with the semaphore in the expected state. */
+            ( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
+        }
+        else
+        {
+            traceCREATE_MUTEX_FAILED();
+        }
+    }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+    QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
+    {
+        QueueHandle_t xNewQueue;
+        const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+        xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+        prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+        return xNewQueue;
+    }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+    QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType,
+                                           StaticQueue_t * pxStaticQueue )
+    {
+        QueueHandle_t xNewQueue;
+        const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+        /* Prevent compiler warnings about unused parameters if
+         * configUSE_TRACE_FACILITY does not equal 1. */
+        ( void ) ucQueueType;
+
+        xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+        prvInitialiseMutex( ( Queue_t * ) xNewQueue );
+
+        return xNewQueue;
+    }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+    TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+    {
+        TaskHandle_t pxReturn;
+        Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
+
+        /* This function is called by xSemaphoreGetMutexHolder(), and should not
+         * be called directly.  Note:  This is a good way of determining if the
+         * calling task is the mutex holder, but not a good way of determining the
+         * identity of the mutex holder, as the holder may change between the
+         * following critical section exiting and the function returning. */
+        taskENTER_CRITICAL();
+        {
+            if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
+            {
+                pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
+            }
+            else
+            {
+                pxReturn = NULL;
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        return pxReturn;
+    } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+    TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
+    {
+        TaskHandle_t pxReturn;
+
+        configASSERT( xSemaphore );
+
+        /* Mutexes cannot be used in interrupt service routines, so the mutex
+         * holder should not change in an ISR, and therefore a critical section is
+         * not required here. */
+        if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+        {
+            pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
+        }
+        else
+        {
+            pxReturn = NULL;
+        }
+
+        return pxReturn;
+    } /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif /* if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+    BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
+    {
+        BaseType_t xReturn;
+        Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+        configASSERT( pxMutex );
+
+        /* If this is the task that holds the mutex then xMutexHolder will not
+         * change outside of this task.  If this task does not hold the mutex then
+         * pxMutexHolder can never coincidentally equal the tasks handle, and as
+         * this is the only condition we are interested in it does not matter if
+         * pxMutexHolder is accessed simultaneously by another task.  Therefore no
+         * mutual exclusion is required to test the pxMutexHolder variable. */
+        if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+        {
+            traceGIVE_MUTEX_RECURSIVE( pxMutex );
+
+            /* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
+             * the task handle, therefore no underflow check is required.  Also,
+             * uxRecursiveCallCount is only modified by the mutex holder, and as
+             * there can only be one, no mutual exclusion is required to modify the
+             * uxRecursiveCallCount member. */
+            ( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
+
+            /* Has the recursive call count unwound to 0? */
+            if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+            {
+                /* Return the mutex.  This will automatically unblock any other
+                 * task that might be waiting to access the mutex. */
+                ( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            xReturn = pdPASS;
+        }
+        else
+        {
+            /* The mutex cannot be given because the calling task is not the
+             * holder. */
+            xReturn = pdFAIL;
+
+            traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
+        }
+
+        return xReturn;
+    }
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+    BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex,
+                                         TickType_t xTicksToWait )
+    {
+        BaseType_t xReturn;
+        Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+        configASSERT( pxMutex );
+
+        /* Comments regarding mutual exclusion as per those within
+         * xQueueGiveMutexRecursive(). */
+
+        traceTAKE_MUTEX_RECURSIVE( pxMutex );
+
+        if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
+        {
+            ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+            xReturn = pdPASS;
+        }
+        else
+        {
+            xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
+
+            /* pdPASS will only be returned if the mutex was successfully
+             * obtained.  The calling task may have entered the Blocked state
+             * before reaching here. */
+            if( xReturn != pdFAIL )
+            {
+                ( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
+            }
+            else
+            {
+                traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
+            }
+        }
+
+        return xReturn;
+    }
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+    QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount,
+                                                       const UBaseType_t uxInitialCount,
+                                                       StaticQueue_t * pxStaticQueue )
+    {
+        QueueHandle_t xHandle;
+
+        configASSERT( uxMaxCount != 0 );
+        configASSERT( uxInitialCount <= uxMaxCount );
+
+        xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+        if( xHandle != NULL )
+        {
+            ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+            traceCREATE_COUNTING_SEMAPHORE();
+        }
+        else
+        {
+            traceCREATE_COUNTING_SEMAPHORE_FAILED();
+        }
+
+        return xHandle;
+    }
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+    QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount,
+                                                 const UBaseType_t uxInitialCount )
+    {
+        QueueHandle_t xHandle;
+
+        configASSERT( uxMaxCount != 0 );
+        configASSERT( uxInitialCount <= uxMaxCount );
+
+        xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+        if( xHandle != NULL )
+        {
+            ( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+            traceCREATE_COUNTING_SEMAPHORE();
+        }
+        else
+        {
+            traceCREATE_COUNTING_SEMAPHORE_FAILED();
+        }
+
+        return xHandle;
+    }
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue,
+                              const void * const pvItemToQueue,
+                              TickType_t xTicksToWait,
+                              const BaseType_t xCopyPosition )
+{
+    BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
+    TimeOut_t xTimeOut;
+    Queue_t * const pxQueue = xQueue;
+
+    configASSERT( pxQueue );
+    configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+    configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+        {
+            configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+        }
+    #endif
+
+    /*lint -save -e904 This function relaxes the coding standard somewhat to
+     * allow return statements within the function itself.  This is done in the
+     * interest of execution time efficiency. */
+    for( ; ; )
+    {
+        taskENTER_CRITICAL();
+        {
+            /* Is there room on the queue now?  The running task must be the
+             * highest priority task wanting to access the queue.  If the head item
+             * in the queue is to be overwritten then it does not matter if the
+             * queue is full. */
+            if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+            {
+                traceQUEUE_SEND( pxQueue );
+
+                #if ( configUSE_QUEUE_SETS == 1 )
+                    {
+                        const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+                        xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+                        if( pxQueue->pxQueueSetContainer != NULL )
+                        {
+                            if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+                            {
+                                /* Do not notify the queue set as an existing item
+                                 * was overwritten in the queue so the number of items
+                                 * in the queue has not changed. */
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                            else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+                            {
+                                /* The queue is a member of a queue set, and posting
+                                 * to the queue set caused a higher priority task to
+                                 * unblock. A context switch is required. */
+                                queueYIELD_IF_USING_PREEMPTION();
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        else
+                        {
+                            /* If there was a task waiting for data to arrive on the
+                             * queue then unblock it now. */
+                            if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                            {
+                                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                                {
+                                    /* The unblocked task has a priority higher than
+                                     * our own so yield immediately.  Yes it is ok to
+                                     * do this from within the critical section - the
+                                     * kernel takes care of that. */
+                                    queueYIELD_IF_USING_PREEMPTION();
+                                }
+                                else
+                                {
+                                    mtCOVERAGE_TEST_MARKER();
+                                }
+                            }
+                            else if( xYieldRequired != pdFALSE )
+                            {
+                                /* This path is a special case that will only get
+                                 * executed if the task was holding multiple mutexes
+                                 * and the mutexes were given back in an order that is
+                                 * different to that in which they were taken. */
+                                queueYIELD_IF_USING_PREEMPTION();
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                    }
+                #else /* configUSE_QUEUE_SETS */
+                    {
+                        xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+                        /* If there was a task waiting for data to arrive on the
+                         * queue then unblock it now. */
+                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                        {
+                            if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                            {
+                                /* The unblocked task has a priority higher than
+                                 * our own so yield immediately.  Yes it is ok to do
+                                 * this from within the critical section - the kernel
+                                 * takes care of that. */
+                                queueYIELD_IF_USING_PREEMPTION();
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        else if( xYieldRequired != pdFALSE )
+                        {
+                            /* This path is a special case that will only get
+                             * executed if the task was holding multiple mutexes and
+                             * the mutexes were given back in an order that is
+                             * different to that in which they were taken. */
+                            queueYIELD_IF_USING_PREEMPTION();
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                #endif /* configUSE_QUEUE_SETS */
+
+                taskEXIT_CRITICAL();
+                return pdPASS;
+            }
+            else
+            {
+                if( xTicksToWait == ( TickType_t ) 0 )
+                {
+                    /* The queue was full and no block time is specified (or
+                     * the block time has expired) so leave now. */
+                    taskEXIT_CRITICAL();
+
+                    /* Return to the original privilege level before exiting
+                     * the function. */
+                    traceQUEUE_SEND_FAILED( pxQueue );
+                    return errQUEUE_FULL;
+                }
+                else if( xEntryTimeSet == pdFALSE )
+                {
+                    /* The queue was full and a block time was specified so
+                     * configure the timeout structure. */
+                    vTaskInternalSetTimeOutState( &xTimeOut );
+                    xEntryTimeSet = pdTRUE;
+                }
+                else
+                {
+                    /* Entry time was already set. */
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        /* Interrupts and other tasks can send to and receive from the queue
+         * now the critical section has been exited. */
+
+        vTaskSuspendAll();
+        prvLockQueue( pxQueue );
+
+        /* Update the timeout state to see if it has expired yet. */
+        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+        {
+            if( prvIsQueueFull( pxQueue ) != pdFALSE )
+            {
+                traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+
+                /* Unlocking the queue means queue events can effect the
+                 * event list.  It is possible that interrupts occurring now
+                 * remove this task from the event list again - but as the
+                 * scheduler is suspended the task will go onto the pending
+                 * ready last instead of the actual ready list. */
+                prvUnlockQueue( pxQueue );
+
+                /* Resuming the scheduler will move tasks from the pending
+                 * ready list into the ready list - so it is feasible that this
+                 * task is already in a ready list before it yields - in which
+                 * case the yield will not cause a context switch unless there
+                 * is also a higher priority task in the pending ready list. */
+                if( xTaskResumeAll() == pdFALSE )
+                {
+                    portYIELD_WITHIN_API();
+                }
+            }
+            else
+            {
+                /* Try again. */
+                prvUnlockQueue( pxQueue );
+                ( void ) xTaskResumeAll();
+            }
+        }
+        else
+        {
+            /* The timeout has expired. */
+            prvUnlockQueue( pxQueue );
+            ( void ) xTaskResumeAll();
+
+            traceQUEUE_SEND_FAILED( pxQueue );
+            return errQUEUE_FULL;
+        }
+    } /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue,
+                                     const void * const pvItemToQueue,
+                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                     const BaseType_t xCopyPosition )
+{
+    BaseType_t xReturn;
+    UBaseType_t uxSavedInterruptStatus;
+    Queue_t * const pxQueue = xQueue;
+
+    configASSERT( pxQueue );
+    configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+    configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+
+    /* RTOS ports that support interrupt nesting have the concept of a maximum
+     * system call (or maximum API call) interrupt priority.  Interrupts that are
+     * above the maximum system call priority are kept permanently enabled, even
+     * when the RTOS kernel is in a critical section, but cannot make any calls to
+     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+     * failure if a FreeRTOS API function is called from an interrupt that has been
+     * assigned a priority above the configured maximum system call priority.
+     * Only FreeRTOS functions that end in FromISR can be called from interrupts
+     * that have been assigned a priority at or (logically) below the maximum
+     * system call interrupt priority.  FreeRTOS maintains a separate interrupt
+     * safe API to ensure interrupt entry is as fast and as simple as possible.
+     * More information (albeit Cortex-M specific) is provided on the following
+     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+    /* Similar to xQueueGenericSend, except without blocking if there is no room
+     * in the queue.  Also don't directly wake a task that was blocked on a queue
+     * read, instead return a flag to say whether a context switch is required or
+     * not (i.e. has a task with a higher priority than us been woken by this
+     * post). */
+    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+        {
+            const int8_t cTxLock = pxQueue->cTxLock;
+            const UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+            traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+            /* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
+             *  semaphore or mutex.  That means prvCopyDataToQueue() cannot result
+             *  in a task disinheriting a priority and prvCopyDataToQueue() can be
+             *  called here even though the disinherit function does not check if
+             *  the scheduler is suspended before accessing the ready lists. */
+            ( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+            /* The event list is not altered if the queue is locked.  This will
+             * be done when the queue is unlocked later. */
+            if( cTxLock == queueUNLOCKED )
+            {
+                #if ( configUSE_QUEUE_SETS == 1 )
+                    {
+                        if( pxQueue->pxQueueSetContainer != NULL )
+                        {
+                            if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
+                            {
+                                /* Do not notify the queue set as an existing item
+                                 * was overwritten in the queue so the number of items
+                                 * in the queue has not changed. */
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                            else if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+                            {
+                                /* The queue is a member of a queue set, and posting
+                                 * to the queue set caused a higher priority task to
+                                 * unblock.  A context switch is required. */
+                                if( pxHigherPriorityTaskWoken != NULL )
+                                {
+                                    *pxHigherPriorityTaskWoken = pdTRUE;
+                                }
+                                else
+                                {
+                                    mtCOVERAGE_TEST_MARKER();
+                                }
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        else
+                        {
+                            if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                            {
+                                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                                {
+                                    /* The task waiting has a higher priority so
+                                     *  record that a context switch is required. */
+                                    if( pxHigherPriorityTaskWoken != NULL )
+                                    {
+                                        *pxHigherPriorityTaskWoken = pdTRUE;
+                                    }
+                                    else
+                                    {
+                                        mtCOVERAGE_TEST_MARKER();
+                                    }
+                                }
+                                else
+                                {
+                                    mtCOVERAGE_TEST_MARKER();
+                                }
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                    }
+                #else /* configUSE_QUEUE_SETS */
+                    {
+                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                        {
+                            if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                            {
+                                /* The task waiting has a higher priority so record that a
+                                 * context switch is required. */
+                                if( pxHigherPriorityTaskWoken != NULL )
+                                {
+                                    *pxHigherPriorityTaskWoken = pdTRUE;
+                                }
+                                else
+                                {
+                                    mtCOVERAGE_TEST_MARKER();
+                                }
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+
+                        /* Not used in this path. */
+                        ( void ) uxPreviousMessagesWaiting;
+                    }
+                #endif /* configUSE_QUEUE_SETS */
+            }
+            else
+            {
+                /* Increment the lock count so the task that unlocks the queue
+                 * knows that data was posted while it was locked. */
+                configASSERT( cTxLock != queueINT8_MAX );
+
+                pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+            }
+
+            xReturn = pdPASS;
+        }
+        else
+        {
+            traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+            xReturn = errQUEUE_FULL;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue,
+                              BaseType_t * const pxHigherPriorityTaskWoken )
+{
+    BaseType_t xReturn;
+    UBaseType_t uxSavedInterruptStatus;
+    Queue_t * const pxQueue = xQueue;
+
+    /* Similar to xQueueGenericSendFromISR() but used with semaphores where the
+     * item size is 0.  Don't directly wake a task that was blocked on a queue
+     * read, instead return a flag to say whether a context switch is required or
+     * not (i.e. has a task with a higher priority than us been woken by this
+     * post). */
+
+    configASSERT( pxQueue );
+
+    /* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
+     * if the item size is not 0. */
+    configASSERT( pxQueue->uxItemSize == 0 );
+
+    /* Normally a mutex would not be given from an interrupt, especially if
+     * there is a mutex holder, as priority inheritance makes no sense for an
+     * interrupts, only tasks. */
+    configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
+
+    /* RTOS ports that support interrupt nesting have the concept of a maximum
+     * system call (or maximum API call) interrupt priority.  Interrupts that are
+     * above the maximum system call priority are kept permanently enabled, even
+     * when the RTOS kernel is in a critical section, but cannot make any calls to
+     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+     * failure if a FreeRTOS API function is called from an interrupt that has been
+     * assigned a priority above the configured maximum system call priority.
+     * Only FreeRTOS functions that end in FromISR can be called from interrupts
+     * that have been assigned a priority at or (logically) below the maximum
+     * system call interrupt priority.  FreeRTOS maintains a separate interrupt
+     * safe API to ensure interrupt entry is as fast and as simple as possible.
+     * More information (albeit Cortex-M specific) is provided on the following
+     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+        /* When the queue is used to implement a semaphore no data is ever
+         * moved through the queue but it is still valid to see if the queue 'has
+         * space'. */
+        if( uxMessagesWaiting < pxQueue->uxLength )
+        {
+            const int8_t cTxLock = pxQueue->cTxLock;
+
+            traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+            /* A task can only have an inherited priority if it is a mutex
+             * holder - and if there is a mutex holder then the mutex cannot be
+             * given from an ISR.  As this is the ISR version of the function it
+             * can be assumed there is no mutex holder and no need to determine if
+             * priority disinheritance is needed.  Simply increase the count of
+             * messages (semaphores) available. */
+            pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+            /* The event list is not altered if the queue is locked.  This will
+             * be done when the queue is unlocked later. */
+            if( cTxLock == queueUNLOCKED )
+            {
+                #if ( configUSE_QUEUE_SETS == 1 )
+                    {
+                        if( pxQueue->pxQueueSetContainer != NULL )
+                        {
+                            if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+                            {
+                                /* The semaphore is a member of a queue set, and
+                                 * posting to the queue set caused a higher priority
+                                 * task to unblock.  A context switch is required. */
+                                if( pxHigherPriorityTaskWoken != NULL )
+                                {
+                                    *pxHigherPriorityTaskWoken = pdTRUE;
+                                }
+                                else
+                                {
+                                    mtCOVERAGE_TEST_MARKER();
+                                }
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        else
+                        {
+                            if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                            {
+                                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                                {
+                                    /* The task waiting has a higher priority so
+                                     *  record that a context switch is required. */
+                                    if( pxHigherPriorityTaskWoken != NULL )
+                                    {
+                                        *pxHigherPriorityTaskWoken = pdTRUE;
+                                    }
+                                    else
+                                    {
+                                        mtCOVERAGE_TEST_MARKER();
+                                    }
+                                }
+                                else
+                                {
+                                    mtCOVERAGE_TEST_MARKER();
+                                }
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                    }
+                #else /* configUSE_QUEUE_SETS */
+                    {
+                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                        {
+                            if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                            {
+                                /* The task waiting has a higher priority so record that a
+                                 * context switch is required. */
+                                if( pxHigherPriorityTaskWoken != NULL )
+                                {
+                                    *pxHigherPriorityTaskWoken = pdTRUE;
+                                }
+                                else
+                                {
+                                    mtCOVERAGE_TEST_MARKER();
+                                }
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                #endif /* configUSE_QUEUE_SETS */
+            }
+            else
+            {
+                /* Increment the lock count so the task that unlocks the queue
+                 * knows that data was posted while it was locked. */
+                configASSERT( cTxLock != queueINT8_MAX );
+
+                pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+            }
+
+            xReturn = pdPASS;
+        }
+        else
+        {
+            traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+            xReturn = errQUEUE_FULL;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceive( QueueHandle_t xQueue,
+                          void * const pvBuffer,
+                          TickType_t xTicksToWait )
+{
+    BaseType_t xEntryTimeSet = pdFALSE;
+    TimeOut_t xTimeOut;
+    Queue_t * const pxQueue = xQueue;
+
+    /* Check the pointer is not NULL. */
+    configASSERT( ( pxQueue ) );
+
+    /* The buffer into which data is received can only be NULL if the data size
+     * is zero (so no data is copied into the buffer). */
+    configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+    /* Cannot block if the scheduler is suspended. */
+    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+        {
+            configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+        }
+    #endif
+
+    /*lint -save -e904  This function relaxes the coding standard somewhat to
+     * allow return statements within the function itself.  This is done in the
+     * interest of execution time efficiency. */
+    for( ; ; )
+    {
+        taskENTER_CRITICAL();
+        {
+            const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+            /* Is there data in the queue now?  To be running the calling task
+             * must be the highest priority task wanting to access the queue. */
+            if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+            {
+                /* Data available, remove one item. */
+                prvCopyDataFromQueue( pxQueue, pvBuffer );
+                traceQUEUE_RECEIVE( pxQueue );
+                pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+                /* There is now space in the queue, were any tasks waiting to
+                 * post to the queue?  If so, unblock the highest priority waiting
+                 * task. */
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+                {
+                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+                    {
+                        queueYIELD_IF_USING_PREEMPTION();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                taskEXIT_CRITICAL();
+                return pdPASS;
+            }
+            else
+            {
+                if( xTicksToWait == ( TickType_t ) 0 )
+                {
+                    /* The queue was empty and no block time is specified (or
+                     * the block time has expired) so leave now. */
+                    taskEXIT_CRITICAL();
+                    traceQUEUE_RECEIVE_FAILED( pxQueue );
+                    return errQUEUE_EMPTY;
+                }
+                else if( xEntryTimeSet == pdFALSE )
+                {
+                    /* The queue was empty and a block time was specified so
+                     * configure the timeout structure. */
+                    vTaskInternalSetTimeOutState( &xTimeOut );
+                    xEntryTimeSet = pdTRUE;
+                }
+                else
+                {
+                    /* Entry time was already set. */
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        /* Interrupts and other tasks can send to and receive from the queue
+         * now the critical section has been exited. */
+
+        vTaskSuspendAll();
+        prvLockQueue( pxQueue );
+
+        /* Update the timeout state to see if it has expired yet. */
+        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+        {
+            /* The timeout has not expired.  If the queue is still empty place
+             * the task on the list of tasks waiting to receive from the queue. */
+            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+            {
+                traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+                prvUnlockQueue( pxQueue );
+
+                if( xTaskResumeAll() == pdFALSE )
+                {
+                    portYIELD_WITHIN_API();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                /* The queue contains data again.  Loop back to try and read the
+                 * data. */
+                prvUnlockQueue( pxQueue );
+                ( void ) xTaskResumeAll();
+            }
+        }
+        else
+        {
+            /* Timed out.  If there is no data in the queue exit, otherwise loop
+             * back and attempt to read the data. */
+            prvUnlockQueue( pxQueue );
+            ( void ) xTaskResumeAll();
+
+            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+            {
+                traceQUEUE_RECEIVE_FAILED( pxQueue );
+                return errQUEUE_EMPTY;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    } /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue,
+                                TickType_t xTicksToWait )
+{
+    BaseType_t xEntryTimeSet = pdFALSE;
+    TimeOut_t xTimeOut;
+    Queue_t * const pxQueue = xQueue;
+
+    #if ( configUSE_MUTEXES == 1 )
+        BaseType_t xInheritanceOccurred = pdFALSE;
+    #endif
+
+    /* Check the queue pointer is not NULL. */
+    configASSERT( ( pxQueue ) );
+
+    /* Check this really is a semaphore, in which case the item size will be
+     * 0. */
+    configASSERT( pxQueue->uxItemSize == 0 );
+
+    /* Cannot block if the scheduler is suspended. */
+    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+        {
+            configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+        }
+    #endif
+
+    /*lint -save -e904 This function relaxes the coding standard somewhat to allow return
+     * statements within the function itself.  This is done in the interest
+     * of execution time efficiency. */
+    for( ; ; )
+    {
+        taskENTER_CRITICAL();
+        {
+            /* Semaphores are queues with an item size of 0, and where the
+             * number of messages in the queue is the semaphore's count value. */
+            const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
+
+            /* Is there data in the queue now?  To be running the calling task
+             * must be the highest priority task wanting to access the queue. */
+            if( uxSemaphoreCount > ( UBaseType_t ) 0 )
+            {
+                traceQUEUE_RECEIVE( pxQueue );
+
+                /* Semaphores are queues with a data size of zero and where the
+                 * messages waiting is the semaphore's count.  Reduce the count. */
+                pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
+
+                #if ( configUSE_MUTEXES == 1 )
+                    {
+                        if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+                        {
+                            /* Record the information required to implement
+                             * priority inheritance should it become necessary. */
+                            pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                #endif /* configUSE_MUTEXES */
+
+                /* Check to see if other tasks are blocked waiting to give the
+                 * semaphore, and if so, unblock the highest priority such task. */
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+                {
+                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+                    {
+                        queueYIELD_IF_USING_PREEMPTION();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                taskEXIT_CRITICAL();
+                return pdPASS;
+            }
+            else
+            {
+                if( xTicksToWait == ( TickType_t ) 0 )
+                {
+                    /* For inheritance to have occurred there must have been an
+                     * initial timeout, and an adjusted timeout cannot become 0, as
+                     * if it were 0 the function would have exited. */
+                    #if ( configUSE_MUTEXES == 1 )
+                        {
+                            configASSERT( xInheritanceOccurred == pdFALSE );
+                        }
+                    #endif /* configUSE_MUTEXES */
+
+                    /* The semaphore count was 0 and no block time is specified
+                     * (or the block time has expired) so exit now. */
+                    taskEXIT_CRITICAL();
+                    traceQUEUE_RECEIVE_FAILED( pxQueue );
+                    return errQUEUE_EMPTY;
+                }
+                else if( xEntryTimeSet == pdFALSE )
+                {
+                    /* The semaphore count was 0 and a block time was specified
+                     * so configure the timeout structure ready to block. */
+                    vTaskInternalSetTimeOutState( &xTimeOut );
+                    xEntryTimeSet = pdTRUE;
+                }
+                else
+                {
+                    /* Entry time was already set. */
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        /* Interrupts and other tasks can give to and take from the semaphore
+         * now the critical section has been exited. */
+
+        vTaskSuspendAll();
+        prvLockQueue( pxQueue );
+
+        /* Update the timeout state to see if it has expired yet. */
+        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+        {
+            /* A block time is specified and not expired.  If the semaphore
+             * count is 0 then enter the Blocked state to wait for a semaphore to
+             * become available.  As semaphores are implemented with queues the
+             * queue being empty is equivalent to the semaphore count being 0. */
+            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+            {
+                traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+
+                #if ( configUSE_MUTEXES == 1 )
+                    {
+                        if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+                        {
+                            taskENTER_CRITICAL();
+                            {
+                                xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
+                            }
+                            taskEXIT_CRITICAL();
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                #endif /* if ( configUSE_MUTEXES == 1 ) */
+
+                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+                prvUnlockQueue( pxQueue );
+
+                if( xTaskResumeAll() == pdFALSE )
+                {
+                    portYIELD_WITHIN_API();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                /* There was no timeout and the semaphore count was not 0, so
+                 * attempt to take the semaphore again. */
+                prvUnlockQueue( pxQueue );
+                ( void ) xTaskResumeAll();
+            }
+        }
+        else
+        {
+            /* Timed out. */
+            prvUnlockQueue( pxQueue );
+            ( void ) xTaskResumeAll();
+
+            /* If the semaphore count is 0 exit now as the timeout has
+             * expired.  Otherwise return to attempt to take the semaphore that is
+             * known to be available.  As semaphores are implemented by queues the
+             * queue being empty is equivalent to the semaphore count being 0. */
+            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+            {
+                #if ( configUSE_MUTEXES == 1 )
+                    {
+                        /* xInheritanceOccurred could only have be set if
+                         * pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
+                         * test the mutex type again to check it is actually a mutex. */
+                        if( xInheritanceOccurred != pdFALSE )
+                        {
+                            taskENTER_CRITICAL();
+                            {
+                                UBaseType_t uxHighestWaitingPriority;
+
+                                /* This task blocking on the mutex caused another
+                                 * task to inherit this task's priority.  Now this task
+                                 * has timed out the priority should be disinherited
+                                 * again, but only as low as the next highest priority
+                                 * task that is waiting for the same mutex. */
+                                uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
+                                vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
+                            }
+                            taskEXIT_CRITICAL();
+                        }
+                    }
+                #endif /* configUSE_MUTEXES */
+
+                traceQUEUE_RECEIVE_FAILED( pxQueue );
+                return errQUEUE_EMPTY;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    } /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeek( QueueHandle_t xQueue,
+                       void * const pvBuffer,
+                       TickType_t xTicksToWait )
+{
+    BaseType_t xEntryTimeSet = pdFALSE;
+    TimeOut_t xTimeOut;
+    int8_t * pcOriginalReadPosition;
+    Queue_t * const pxQueue = xQueue;
+
+    /* Check the pointer is not NULL. */
+    configASSERT( ( pxQueue ) );
+
+    /* The buffer into which data is received can only be NULL if the data size
+     * is zero (so no data is copied into the buffer. */
+    configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+    /* Cannot block if the scheduler is suspended. */
+    #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+        {
+            configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+        }
+    #endif
+
+    /*lint -save -e904  This function relaxes the coding standard somewhat to
+     * allow return statements within the function itself.  This is done in the
+     * interest of execution time efficiency. */
+    for( ; ; )
+    {
+        taskENTER_CRITICAL();
+        {
+            const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+            /* Is there data in the queue now?  To be running the calling task
+             * must be the highest priority task wanting to access the queue. */
+            if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+            {
+                /* Remember the read position so it can be reset after the data
+                 * is read from the queue as this function is only peeking the
+                 * data, not removing it. */
+                pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+
+                prvCopyDataFromQueue( pxQueue, pvBuffer );
+                traceQUEUE_PEEK( pxQueue );
+
+                /* The data is not being removed, so reset the read pointer. */
+                pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+                /* The data is being left in the queue, so see if there are
+                 * any other tasks waiting for the data. */
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                {
+                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                    {
+                        /* The task waiting has a higher priority than this task. */
+                        queueYIELD_IF_USING_PREEMPTION();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                taskEXIT_CRITICAL();
+                return pdPASS;
+            }
+            else
+            {
+                if( xTicksToWait == ( TickType_t ) 0 )
+                {
+                    /* The queue was empty and no block time is specified (or
+                     * the block time has expired) so leave now. */
+                    taskEXIT_CRITICAL();
+                    traceQUEUE_PEEK_FAILED( pxQueue );
+                    return errQUEUE_EMPTY;
+                }
+                else if( xEntryTimeSet == pdFALSE )
+                {
+                    /* The queue was empty and a block time was specified so
+                     * configure the timeout structure ready to enter the blocked
+                     * state. */
+                    vTaskInternalSetTimeOutState( &xTimeOut );
+                    xEntryTimeSet = pdTRUE;
+                }
+                else
+                {
+                    /* Entry time was already set. */
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        /* Interrupts and other tasks can send to and receive from the queue
+         * now the critical section has been exited. */
+
+        vTaskSuspendAll();
+        prvLockQueue( pxQueue );
+
+        /* Update the timeout state to see if it has expired yet. */
+        if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+        {
+            /* Timeout has not expired yet, check to see if there is data in the
+            * queue now, and if not enter the Blocked state to wait for data. */
+            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+            {
+                traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
+                vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+                prvUnlockQueue( pxQueue );
+
+                if( xTaskResumeAll() == pdFALSE )
+                {
+                    portYIELD_WITHIN_API();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                /* There is data in the queue now, so don't enter the blocked
+                 * state, instead return to try and obtain the data. */
+                prvUnlockQueue( pxQueue );
+                ( void ) xTaskResumeAll();
+            }
+        }
+        else
+        {
+            /* The timeout has expired.  If there is still no data in the queue
+             * exit, otherwise go back and try to read the data again. */
+            prvUnlockQueue( pxQueue );
+            ( void ) xTaskResumeAll();
+
+            if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+            {
+                traceQUEUE_PEEK_FAILED( pxQueue );
+                return errQUEUE_EMPTY;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    } /*lint -restore */
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue,
+                                 void * const pvBuffer,
+                                 BaseType_t * const pxHigherPriorityTaskWoken )
+{
+    BaseType_t xReturn;
+    UBaseType_t uxSavedInterruptStatus;
+    Queue_t * const pxQueue = xQueue;
+
+    configASSERT( pxQueue );
+    configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+    /* RTOS ports that support interrupt nesting have the concept of a maximum
+     * system call (or maximum API call) interrupt priority.  Interrupts that are
+     * above the maximum system call priority are kept permanently enabled, even
+     * when the RTOS kernel is in a critical section, but cannot make any calls to
+     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+     * failure if a FreeRTOS API function is called from an interrupt that has been
+     * assigned a priority above the configured maximum system call priority.
+     * Only FreeRTOS functions that end in FromISR can be called from interrupts
+     * that have been assigned a priority at or (logically) below the maximum
+     * system call interrupt priority.  FreeRTOS maintains a separate interrupt
+     * safe API to ensure interrupt entry is as fast and as simple as possible.
+     * More information (albeit Cortex-M specific) is provided on the following
+     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+        /* Cannot block in an ISR, so check there is data available. */
+        if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+        {
+            const int8_t cRxLock = pxQueue->cRxLock;
+
+            traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
+
+            prvCopyDataFromQueue( pxQueue, pvBuffer );
+            pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
+
+            /* If the queue is locked the event list will not be modified.
+             * Instead update the lock count so the task that unlocks the queue
+             * will know that an ISR has removed data while the queue was
+             * locked. */
+            if( cRxLock == queueUNLOCKED )
+            {
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+                {
+                    if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+                    {
+                        /* The task waiting has a higher priority than us so
+                         * force a context switch. */
+                        if( pxHigherPriorityTaskWoken != NULL )
+                        {
+                            *pxHigherPriorityTaskWoken = pdTRUE;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                /* Increment the lock count so the task that unlocks the queue
+                 * knows that data was removed while it was locked. */
+                configASSERT( cRxLock != queueINT8_MAX );
+
+                pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
+            }
+
+            xReturn = pdPASS;
+        }
+        else
+        {
+            xReturn = pdFAIL;
+            traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,
+                              void * const pvBuffer )
+{
+    BaseType_t xReturn;
+    UBaseType_t uxSavedInterruptStatus;
+    int8_t * pcOriginalReadPosition;
+    Queue_t * const pxQueue = xQueue;
+
+    configASSERT( pxQueue );
+    configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+    configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
+
+    /* RTOS ports that support interrupt nesting have the concept of a maximum
+     * system call (or maximum API call) interrupt priority.  Interrupts that are
+     * above the maximum system call priority are kept permanently enabled, even
+     * when the RTOS kernel is in a critical section, but cannot make any calls to
+     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+     * failure if a FreeRTOS API function is called from an interrupt that has been
+     * assigned a priority above the configured maximum system call priority.
+     * Only FreeRTOS functions that end in FromISR can be called from interrupts
+     * that have been assigned a priority at or (logically) below the maximum
+     * system call interrupt priority.  FreeRTOS maintains a separate interrupt
+     * safe API to ensure interrupt entry is as fast and as simple as possible.
+     * More information (albeit Cortex-M specific) is provided on the following
+     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+    uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        /* Cannot block in an ISR, so check there is data available. */
+        if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+        {
+            traceQUEUE_PEEK_FROM_ISR( pxQueue );
+
+            /* Remember the read position so it can be reset as nothing is
+             * actually being removed from the queue. */
+            pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
+            prvCopyDataFromQueue( pxQueue, pvBuffer );
+            pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
+
+            xReturn = pdPASS;
+        }
+        else
+        {
+            xReturn = pdFAIL;
+            traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
+{
+    UBaseType_t uxReturn;
+
+    configASSERT( xQueue );
+
+    taskENTER_CRITICAL();
+    {
+        uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+    }
+    taskEXIT_CRITICAL();
+
+    return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
+{
+    UBaseType_t uxReturn;
+    Queue_t * const pxQueue = xQueue;
+
+    configASSERT( pxQueue );
+
+    taskENTER_CRITICAL();
+    {
+        uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
+    }
+    taskEXIT_CRITICAL();
+
+    return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
+{
+    UBaseType_t uxReturn;
+    Queue_t * const pxQueue = xQueue;
+
+    configASSERT( pxQueue );
+    uxReturn = pxQueue->uxMessagesWaiting;
+
+    return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+void vQueueDelete( QueueHandle_t xQueue )
+{
+    Queue_t * const pxQueue = xQueue;
+
+    configASSERT( pxQueue );
+    traceQUEUE_DELETE( pxQueue );
+
+    #if ( configQUEUE_REGISTRY_SIZE > 0 )
+        {
+            vQueueUnregisterQueue( pxQueue );
+        }
+    #endif
+
+    #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+        {
+            /* The queue can only have been allocated dynamically - free it
+             * again. */
+            vPortFree( pxQueue );
+        }
+    #elif ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+        {
+            /* The queue could have been allocated statically or dynamically, so
+             * check before attempting to free the memory. */
+            if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+            {
+                vPortFree( pxQueue );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    #else /* if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) */
+        {
+            /* The queue must have been statically allocated, so is not going to be
+             * deleted.  Avoid compiler warnings about the unused parameter. */
+            ( void ) pxQueue;
+        }
+    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
+    {
+        return ( ( Queue_t * ) xQueue )->uxQueueNumber;
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    void vQueueSetQueueNumber( QueueHandle_t xQueue,
+                               UBaseType_t uxQueueNumber )
+    {
+        ( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
+    {
+        return ( ( Queue_t * ) xQueue )->ucQueueType;
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+    static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
+    {
+        UBaseType_t uxHighestPriorityOfWaitingTasks;
+
+        /* If a task waiting for a mutex causes the mutex holder to inherit a
+         * priority, but the waiting task times out, then the holder should
+         * disinherit the priority - but only down to the highest priority of any
+         * other tasks that are waiting for the same mutex.  For this purpose,
+         * return the priority of the highest priority task that is waiting for the
+         * mutex. */
+        if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
+        {
+            uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
+        }
+        else
+        {
+            uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
+        }
+
+        return uxHighestPriorityOfWaitingTasks;
+    }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue,
+                                      const void * pvItemToQueue,
+                                      const BaseType_t xPosition )
+{
+    BaseType_t xReturn = pdFALSE;
+    UBaseType_t uxMessagesWaiting;
+
+    /* This function is called from a critical section. */
+
+    uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+    if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
+    {
+        #if ( configUSE_MUTEXES == 1 )
+            {
+                if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+                {
+                    /* The mutex is no longer being held. */
+                    xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
+                    pxQueue->u.xSemaphore.xMutexHolder = NULL;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        #endif /* configUSE_MUTEXES */
+    }
+    else if( xPosition == queueSEND_TO_BACK )
+    {
+        ( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+        pxQueue->pcWriteTo += pxQueue->uxItemSize;                                                       /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+
+        if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail )                                             /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+        {
+            pxQueue->pcWriteTo = pxQueue->pcHead;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        ( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
+        pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
+
+        if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+        {
+            pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        if( xPosition == queueOVERWRITE )
+        {
+            if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+            {
+                /* An item is not being added but overwritten, so subtract
+                 * one from the recorded number of items in the queue so when
+                 * one is added again below the number of recorded items remains
+                 * correct. */
+                --uxMessagesWaiting;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+    pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCopyDataFromQueue( Queue_t * const pxQueue,
+                                  void * const pvBuffer )
+{
+    if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
+    {
+        pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;           /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
+
+        if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+        {
+            pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
+    }
+}
+/*-----------------------------------------------------------*/
+
+static void prvUnlockQueue( Queue_t * const pxQueue )
+{
+    /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
+
+    /* The lock counts contains the number of extra data items placed or
+     * removed from the queue while the queue was locked.  When a queue is
+     * locked items can be added or removed, but the event lists cannot be
+     * updated. */
+    taskENTER_CRITICAL();
+    {
+        int8_t cTxLock = pxQueue->cTxLock;
+
+        /* See if data was added to the queue while it was locked. */
+        while( cTxLock > queueLOCKED_UNMODIFIED )
+        {
+            /* Data was posted while the queue was locked.  Are any tasks
+             * blocked waiting for data to become available? */
+            #if ( configUSE_QUEUE_SETS == 1 )
+                {
+                    if( pxQueue->pxQueueSetContainer != NULL )
+                    {
+                        if( prvNotifyQueueSetContainer( pxQueue ) != pdFALSE )
+                        {
+                            /* The queue is a member of a queue set, and posting to
+                             * the queue set caused a higher priority task to unblock.
+                             * A context switch is required. */
+                            vTaskMissedYield();
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    else
+                    {
+                        /* Tasks that are removed from the event list will get
+                         * added to the pending ready list as the scheduler is still
+                         * suspended. */
+                        if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                        {
+                            if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                            {
+                                /* The task waiting has a higher priority so record that a
+                                 * context switch is required. */
+                                vTaskMissedYield();
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        else
+                        {
+                            break;
+                        }
+                    }
+                }
+            #else /* configUSE_QUEUE_SETS */
+                {
+                    /* Tasks that are removed from the event list will get added to
+                     * the pending ready list as the scheduler is still suspended. */
+                    if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                    {
+                        if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                        {
+                            /* The task waiting has a higher priority so record that
+                             * a context switch is required. */
+                            vTaskMissedYield();
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    else
+                    {
+                        break;
+                    }
+                }
+            #endif /* configUSE_QUEUE_SETS */
+
+            --cTxLock;
+        }
+
+        pxQueue->cTxLock = queueUNLOCKED;
+    }
+    taskEXIT_CRITICAL();
+
+    /* Do the same for the Rx lock. */
+    taskENTER_CRITICAL();
+    {
+        int8_t cRxLock = pxQueue->cRxLock;
+
+        while( cRxLock > queueLOCKED_UNMODIFIED )
+        {
+            if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+            {
+                if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+                {
+                    vTaskMissedYield();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                --cRxLock;
+            }
+            else
+            {
+                break;
+            }
+        }
+
+        pxQueue->cRxLock = queueUNLOCKED;
+    }
+    taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueEmpty( const Queue_t * pxQueue )
+{
+    BaseType_t xReturn;
+
+    taskENTER_CRITICAL();
+    {
+        if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+        {
+            xReturn = pdTRUE;
+        }
+        else
+        {
+            xReturn = pdFALSE;
+        }
+    }
+    taskEXIT_CRITICAL();
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
+{
+    BaseType_t xReturn;
+    Queue_t * const pxQueue = xQueue;
+
+    configASSERT( pxQueue );
+
+    if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+    {
+        xReturn = pdTRUE;
+    }
+    else
+    {
+        xReturn = pdFALSE;
+    }
+
+    return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueFull( const Queue_t * pxQueue )
+{
+    BaseType_t xReturn;
+
+    taskENTER_CRITICAL();
+    {
+        if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+        {
+            xReturn = pdTRUE;
+        }
+        else
+        {
+            xReturn = pdFALSE;
+        }
+    }
+    taskEXIT_CRITICAL();
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
+{
+    BaseType_t xReturn;
+    Queue_t * const pxQueue = xQueue;
+
+    configASSERT( pxQueue );
+
+    if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+    {
+        xReturn = pdTRUE;
+    }
+    else
+    {
+        xReturn = pdFALSE;
+    }
+
+    return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+    BaseType_t xQueueCRSend( QueueHandle_t xQueue,
+                             const void * pvItemToQueue,
+                             TickType_t xTicksToWait )
+    {
+        BaseType_t xReturn;
+        Queue_t * const pxQueue = xQueue;
+
+        /* If the queue is already full we may have to block.  A critical section
+         * is required to prevent an interrupt removing something from the queue
+         * between the check to see if the queue is full and blocking on the queue. */
+        portDISABLE_INTERRUPTS();
+        {
+            if( prvIsQueueFull( pxQueue ) != pdFALSE )
+            {
+                /* The queue is full - do we want to block or just leave without
+                 * posting? */
+                if( xTicksToWait > ( TickType_t ) 0 )
+                {
+                    /* As this is called from a coroutine we cannot block directly, but
+                     * return indicating that we need to block. */
+                    vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
+                    portENABLE_INTERRUPTS();
+                    return errQUEUE_BLOCKED;
+                }
+                else
+                {
+                    portENABLE_INTERRUPTS();
+                    return errQUEUE_FULL;
+                }
+            }
+        }
+        portENABLE_INTERRUPTS();
+
+        portDISABLE_INTERRUPTS();
+        {
+            if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+            {
+                /* There is room in the queue, copy the data into the queue. */
+                prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+                xReturn = pdPASS;
+
+                /* Were any co-routines waiting for data to become available? */
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                {
+                    /* In this instance the co-routine could be placed directly
+                     * into the ready list as we are within a critical section.
+                     * Instead the same pending ready list mechanism is used as if
+                     * the event were caused from within an interrupt. */
+                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                    {
+                        /* The co-routine waiting has a higher priority so record
+                         * that a yield might be appropriate. */
+                        xReturn = errQUEUE_YIELD;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                xReturn = errQUEUE_FULL;
+            }
+        }
+        portENABLE_INTERRUPTS();
+
+        return xReturn;
+    }
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+    BaseType_t xQueueCRReceive( QueueHandle_t xQueue,
+                                void * pvBuffer,
+                                TickType_t xTicksToWait )
+    {
+        BaseType_t xReturn;
+        Queue_t * const pxQueue = xQueue;
+
+        /* If the queue is already empty we may have to block.  A critical section
+         * is required to prevent an interrupt adding something to the queue
+         * between the check to see if the queue is empty and blocking on the queue. */
+        portDISABLE_INTERRUPTS();
+        {
+            if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+            {
+                /* There are no messages in the queue, do we want to block or just
+                 * leave with nothing? */
+                if( xTicksToWait > ( TickType_t ) 0 )
+                {
+                    /* As this is a co-routine we cannot block directly, but return
+                     * indicating that we need to block. */
+                    vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
+                    portENABLE_INTERRUPTS();
+                    return errQUEUE_BLOCKED;
+                }
+                else
+                {
+                    portENABLE_INTERRUPTS();
+                    return errQUEUE_FULL;
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        portENABLE_INTERRUPTS();
+
+        portDISABLE_INTERRUPTS();
+        {
+            if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+            {
+                /* Data is available from the queue. */
+                pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+
+                if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+                {
+                    pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                --( pxQueue->uxMessagesWaiting );
+                ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+                xReturn = pdPASS;
+
+                /* Were any co-routines waiting for space to become available? */
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+                {
+                    /* In this instance the co-routine could be placed directly
+                     * into the ready list as we are within a critical section.
+                     * Instead the same pending ready list mechanism is used as if
+                     * the event were caused from within an interrupt. */
+                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+                    {
+                        xReturn = errQUEUE_YIELD;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                xReturn = pdFAIL;
+            }
+        }
+        portENABLE_INTERRUPTS();
+
+        return xReturn;
+    }
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+    BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue,
+                                    const void * pvItemToQueue,
+                                    BaseType_t xCoRoutinePreviouslyWoken )
+    {
+        Queue_t * const pxQueue = xQueue;
+
+        /* Cannot block within an ISR so if there is no space on the queue then
+         * exit without doing anything. */
+        if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+        {
+            prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+
+            /* We only want to wake one co-routine per ISR, so check that a
+             * co-routine has not already been woken. */
+            if( xCoRoutinePreviouslyWoken == pdFALSE )
+            {
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+                {
+                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+                    {
+                        return pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        return xCoRoutinePreviouslyWoken;
+    }
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+    BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue,
+                                       void * pvBuffer,
+                                       BaseType_t * pxCoRoutineWoken )
+    {
+        BaseType_t xReturn;
+        Queue_t * const pxQueue = xQueue;
+
+        /* We cannot block from an ISR, so check there is data available. If
+         * not then just leave without doing anything. */
+        if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+        {
+            /* Copy the data from the queue. */
+            pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
+
+            if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
+            {
+                pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            --( pxQueue->uxMessagesWaiting );
+            ( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+            if( ( *pxCoRoutineWoken ) == pdFALSE )
+            {
+                if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+                {
+                    if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+                    {
+                        *pxCoRoutineWoken = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            xReturn = pdPASS;
+        }
+        else
+        {
+            xReturn = pdFAIL;
+        }
+
+        return xReturn;
+    }
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+    void vQueueAddToRegistry( QueueHandle_t xQueue,
+                              const char * pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    {
+        UBaseType_t ux;
+
+        /* See if there is an empty space in the registry.  A NULL name denotes
+         * a free slot. */
+        for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+        {
+            if( xQueueRegistry[ ux ].pcQueueName == NULL )
+            {
+                /* Store the information on this queue. */
+                xQueueRegistry[ ux ].pcQueueName = pcQueueName;
+                xQueueRegistry[ ux ].xHandle = xQueue;
+
+                traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
+                break;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    }
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+    const char * pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    {
+        UBaseType_t ux;
+        const char * pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+        /* Note there is nothing here to protect against another task adding or
+         * removing entries from the registry while it is being searched. */
+
+        for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+        {
+            if( xQueueRegistry[ ux ].xHandle == xQueue )
+            {
+                pcReturn = xQueueRegistry[ ux ].pcQueueName;
+                break;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+
+        return pcReturn;
+    } /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+    void vQueueUnregisterQueue( QueueHandle_t xQueue )
+    {
+        UBaseType_t ux;
+
+        /* See if the handle of the queue being unregistered in actually in the
+         * registry. */
+        for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+        {
+            if( xQueueRegistry[ ux ].xHandle == xQueue )
+            {
+                /* Set the name to NULL to show that this slot if free again. */
+                xQueueRegistry[ ux ].pcQueueName = NULL;
+
+                /* Set the handle to NULL to ensure the same queue handle cannot
+                 * appear in the registry twice if it is added, removed, then
+                 * added again. */
+                xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
+                break;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    } /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+    void vQueueWaitForMessageRestricted( QueueHandle_t xQueue,
+                                         TickType_t xTicksToWait,
+                                         const BaseType_t xWaitIndefinitely )
+    {
+        Queue_t * const pxQueue = xQueue;
+
+        /* This function should not be called by application code hence the
+         * 'Restricted' in its name.  It is not part of the public API.  It is
+         * designed for use by kernel code, and has special calling requirements.
+         * It can result in vListInsert() being called on a list that can only
+         * possibly ever have one item in it, so the list will be fast, but even
+         * so it should be called with the scheduler locked and not from a critical
+         * section. */
+
+        /* Only do anything if there are no messages in the queue.  This function
+         *  will not actually cause the task to block, just place it on a blocked
+         *  list.  It will not block until the scheduler is unlocked - at which
+         *  time a yield will be performed.  If an item is added to the queue while
+         *  the queue is locked, and the calling task blocks on the queue, then the
+         *  calling task will be immediately unblocked when the queue is unlocked. */
+        prvLockQueue( pxQueue );
+
+        if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
+        {
+            /* There is nothing in the queue, block for the specified period. */
+            vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        prvUnlockQueue( pxQueue );
+    }
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+    QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
+    {
+        QueueSetHandle_t pxQueue;
+
+        pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
+
+        return pxQueue;
+    }
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+    BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                               QueueSetHandle_t xQueueSet )
+    {
+        BaseType_t xReturn;
+
+        taskENTER_CRITICAL();
+        {
+            if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
+            {
+                /* Cannot add a queue/semaphore to more than one queue set. */
+                xReturn = pdFAIL;
+            }
+            else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
+            {
+                /* Cannot add a queue/semaphore to a queue set if there are already
+                 * items in the queue/semaphore. */
+                xReturn = pdFAIL;
+            }
+            else
+            {
+                ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
+                xReturn = pdPASS;
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        return xReturn;
+    }
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+    BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore,
+                                    QueueSetHandle_t xQueueSet )
+    {
+        BaseType_t xReturn;
+        Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
+
+        if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
+        {
+            /* The queue was not a member of the set. */
+            xReturn = pdFAIL;
+        }
+        else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
+        {
+            /* It is dangerous to remove a queue from a set when the queue is
+             * not empty because the queue set will still hold pending events for
+             * the queue. */
+            xReturn = pdFAIL;
+        }
+        else
+        {
+            taskENTER_CRITICAL();
+            {
+                /* The queue is no longer contained in the set. */
+                pxQueueOrSemaphore->pxQueueSetContainer = NULL;
+            }
+            taskEXIT_CRITICAL();
+            xReturn = pdPASS;
+        }
+
+        return xReturn;
+    } /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+    QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet,
+                                                TickType_t const xTicksToWait )
+    {
+        QueueSetMemberHandle_t xReturn = NULL;
+
+        ( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
+        return xReturn;
+    }
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+    QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
+    {
+        QueueSetMemberHandle_t xReturn = NULL;
+
+        ( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
+        return xReturn;
+    }
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+    static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue )
+    {
+        Queue_t * pxQueueSetContainer = pxQueue->pxQueueSetContainer;
+        BaseType_t xReturn = pdFALSE;
+
+        /* This function must be called form a critical section. */
+
+        configASSERT( pxQueueSetContainer );
+        configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
+
+        if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
+        {
+            const int8_t cTxLock = pxQueueSetContainer->cTxLock;
+
+            traceQUEUE_SET_SEND( pxQueueSetContainer );
+
+            /* The data copied is the handle of the queue that contains data. */
+            xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, queueSEND_TO_BACK );
+
+            if( cTxLock == queueUNLOCKED )
+            {
+                if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
+                {
+                    if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
+                    {
+                        /* The task waiting has a higher priority. */
+                        xReturn = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                configASSERT( cTxLock != queueINT8_MAX );
+
+                pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        return xReturn;
+    }
+
+#endif /* configUSE_QUEUE_SETS */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/stream_buffer.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/stream_buffer.c
new file mode 100644
index 0000000..5c6a47e
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/stream_buffer.c
@@ -0,0 +1,1314 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdint.h>
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "stream_buffer.h"
+
+#if ( configUSE_TASK_NOTIFICATIONS != 1 )
+    #error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
+#endif
+
+/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
+ * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+ * for the header files above, but not in this file, in order to generate the
+ * correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* If the user has not provided application specific Rx notification macros,
+ * or #defined the notification macros away, them provide default implementations
+ * that uses task notifications. */
+/*lint -save -e9026 Function like macros allowed and needed here so they can be overridden. */
+#ifndef sbRECEIVE_COMPLETED
+    #define sbRECEIVE_COMPLETED( pxStreamBuffer )                         \
+    vTaskSuspendAll();                                                    \
+    {                                                                     \
+        if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )              \
+        {                                                                 \
+            ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend, \
+                                  ( uint32_t ) 0,                         \
+                                  eNoAction );                            \
+            ( pxStreamBuffer )->xTaskWaitingToSend = NULL;                \
+        }                                                                 \
+    }                                                                     \
+    ( void ) xTaskResumeAll();
+#endif /* sbRECEIVE_COMPLETED */
+
+#ifndef sbRECEIVE_COMPLETED_FROM_ISR
+    #define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,                            \
+                                          pxHigherPriorityTaskWoken )                \
+    {                                                                                \
+        UBaseType_t uxSavedInterruptStatus;                                          \
+                                                                                     \
+        uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();  \
+        {                                                                            \
+            if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )                     \
+            {                                                                        \
+                ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend, \
+                                             ( uint32_t ) 0,                         \
+                                             eNoAction,                              \
+                                             pxHigherPriorityTaskWoken );            \
+                ( pxStreamBuffer )->xTaskWaitingToSend = NULL;                       \
+            }                                                                        \
+        }                                                                            \
+        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );                 \
+    }
+#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
+
+/* If the user has not provided an application specific Tx notification macro,
+ * or #defined the notification macro away, them provide a default implementation
+ * that uses task notifications. */
+#ifndef sbSEND_COMPLETED
+    #define sbSEND_COMPLETED( pxStreamBuffer )                               \
+    vTaskSuspendAll();                                                       \
+    {                                                                        \
+        if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )              \
+        {                                                                    \
+            ( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive, \
+                                  ( uint32_t ) 0,                            \
+                                  eNoAction );                               \
+            ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;                \
+        }                                                                    \
+    }                                                                        \
+    ( void ) xTaskResumeAll();
+#endif /* sbSEND_COMPLETED */
+
+#ifndef sbSEND_COMPLETE_FROM_ISR
+    #define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )       \
+    {                                                                                   \
+        UBaseType_t uxSavedInterruptStatus;                                             \
+                                                                                        \
+        uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();     \
+        {                                                                               \
+            if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )                     \
+            {                                                                           \
+                ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive, \
+                                             ( uint32_t ) 0,                            \
+                                             eNoAction,                                 \
+                                             pxHigherPriorityTaskWoken );               \
+                ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;                       \
+            }                                                                           \
+        }                                                                               \
+        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );                    \
+    }
+#endif /* sbSEND_COMPLETE_FROM_ISR */
+/*lint -restore (9026) */
+
+/* The number of bytes used to hold the length of a message in the buffer. */
+#define sbBYTES_TO_STORE_MESSAGE_LENGTH    ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
+
+/* Bits stored in the ucFlags field of the stream buffer. */
+#define sbFLAGS_IS_MESSAGE_BUFFER          ( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
+#define sbFLAGS_IS_STATICALLY_ALLOCATED    ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
+
+/*-----------------------------------------------------------*/
+
+/* Structure that hold state information on the buffer. */
+typedef struct StreamBufferDef_t                 /*lint !e9058 Style convention uses tag. */
+{
+    volatile size_t xTail;                       /* Index to the next item to read within the buffer. */
+    volatile size_t xHead;                       /* Index to the next item to write within the buffer. */
+    size_t xLength;                              /* The length of the buffer pointed to by pucBuffer. */
+    size_t xTriggerLevelBytes;                   /* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
+    volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
+    volatile TaskHandle_t xTaskWaitingToSend;    /* Holds the handle of a task waiting to send data to a message buffer that is full. */
+    uint8_t * pucBuffer;                         /* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
+    uint8_t ucFlags;
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxStreamBufferNumber; /* Used for tracing purposes. */
+    #endif
+} StreamBuffer_t;
+
+/*
+ * The number of bytes available to be read from the buffer.
+ */
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Add xCount bytes from pucData into the pxStreamBuffer message buffer.
+ * Returns the number of bytes written, which will either equal xCount in the
+ * success case, or 0 if there was not enough space in the buffer (in which case
+ * no data is written into the buffer).
+ */
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer,
+                                     const uint8_t * pucData,
+                                     size_t xCount ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then reads an entire
+ * message out of the buffer.  If the stream buffer is being used as a stream
+ * buffer then read as many bytes as possible from the buffer.
+ * prvReadBytesFromBuffer() is called to actually extract the bytes from the
+ * buffer's data storage area.
+ */
+static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer,
+                                        void * pvRxData,
+                                        size_t xBufferLengthBytes,
+                                        size_t xBytesAvailable,
+                                        size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the stream buffer is being used as a message buffer, then writes an entire
+ * message to the buffer.  If the stream buffer is being used as a stream
+ * buffer then write as many bytes as possible to the buffer.
+ * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
+ * data storage area.
+ */
+static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
+                                       const void * pvTxData,
+                                       size_t xDataLengthBytes,
+                                       size_t xSpace,
+                                       size_t xRequiredSpace ) PRIVILEGED_FUNCTION;
+
+/*
+ * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them
+ * to pucData.
+ */
+static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer,
+                                      uint8_t * pucData,
+                                      size_t xMaxCount,
+                                      size_t xBytesAvailable ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
+ * initialise the members of the newly created stream buffer structure.
+ */
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+                                          uint8_t * const pucBuffer,
+                                          size_t xBufferSizeBytes,
+                                          size_t xTriggerLevelBytes,
+                                          uint8_t ucFlags ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+    StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
+                                                     size_t xTriggerLevelBytes,
+                                                     BaseType_t xIsMessageBuffer )
+    {
+        uint8_t * pucAllocatedMemory;
+        uint8_t ucFlags;
+
+        /* In case the stream buffer is going to be used as a message buffer
+         * (that is, it will hold discrete messages with a little meta data that
+         * says how big the next message is) check the buffer will be large enough
+         * to hold at least one message. */
+        if( xIsMessageBuffer == pdTRUE )
+        {
+            /* Is a message buffer but not statically allocated. */
+            ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
+            configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+        }
+        else
+        {
+            /* Not a message buffer and not statically allocated. */
+            ucFlags = 0;
+            configASSERT( xBufferSizeBytes > 0 );
+        }
+
+        configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+        /* A trigger level of 0 would cause a waiting task to unblock even when
+         * the buffer was empty. */
+        if( xTriggerLevelBytes == ( size_t ) 0 )
+        {
+            xTriggerLevelBytes = ( size_t ) 1;
+        }
+
+        /* A stream buffer requires a StreamBuffer_t structure and a buffer.
+         * Both are allocated in a single call to pvPortMalloc().  The
+         * StreamBuffer_t structure is placed at the start of the allocated memory
+         * and the buffer follows immediately after.  The requested size is
+         * incremented so the free space is returned as the user would expect -
+         * this is a quirk of the implementation that means otherwise the free
+         * space would be reported as one byte smaller than would be logically
+         * expected. */
+        if( xBufferSizeBytes < ( xBufferSizeBytes + 1 + sizeof( StreamBuffer_t ) ) )
+        {
+            xBufferSizeBytes++;
+            pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */
+        }
+        else
+        {
+            pucAllocatedMemory = NULL;
+        }
+        
+
+        if( pucAllocatedMemory != NULL )
+        {
+            prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory,       /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
+                                          pucAllocatedMemory + sizeof( StreamBuffer_t ), /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
+                                          xBufferSizeBytes,
+                                          xTriggerLevelBytes,
+                                          ucFlags );
+
+            traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
+        }
+        else
+        {
+            traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
+        }
+
+        return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
+    }
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+    StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
+                                                           size_t xTriggerLevelBytes,
+                                                           BaseType_t xIsMessageBuffer,
+                                                           uint8_t * const pucStreamBufferStorageArea,
+                                                           StaticStreamBuffer_t * const pxStaticStreamBuffer )
+    {
+        StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
+        StreamBufferHandle_t xReturn;
+        uint8_t ucFlags;
+
+        configASSERT( pucStreamBufferStorageArea );
+        configASSERT( pxStaticStreamBuffer );
+        configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
+
+        /* A trigger level of 0 would cause a waiting task to unblock even when
+         * the buffer was empty. */
+        if( xTriggerLevelBytes == ( size_t ) 0 )
+        {
+            xTriggerLevelBytes = ( size_t ) 1;
+        }
+
+        if( xIsMessageBuffer != pdFALSE )
+        {
+            /* Statically allocated message buffer. */
+            ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
+        }
+        else
+        {
+            /* Statically allocated stream buffer. */
+            ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
+        }
+
+        /* In case the stream buffer is going to be used as a message buffer
+         * (that is, it will hold discrete messages with a little meta data that
+         * says how big the next message is) check the buffer will be large enough
+         * to hold at least one message. */
+        configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
+
+        #if ( configASSERT_DEFINED == 1 )
+            {
+                /* Sanity check that the size of the structure used to declare a
+                 * variable of type StaticStreamBuffer_t equals the size of the real
+                 * message buffer structure. */
+                volatile size_t xSize = sizeof( StaticStreamBuffer_t );
+                configASSERT( xSize == sizeof( StreamBuffer_t ) );
+            } /*lint !e529 xSize is referenced is configASSERT() is defined. */
+        #endif /* configASSERT_DEFINED */
+
+        if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
+        {
+            prvInitialiseNewStreamBuffer( pxStreamBuffer,
+                                          pucStreamBufferStorageArea,
+                                          xBufferSizeBytes,
+                                          xTriggerLevelBytes,
+                                          ucFlags );
+
+            /* Remember this was statically allocated in case it is ever deleted
+             * again. */
+            pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
+
+            traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
+
+            xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
+        }
+        else
+        {
+            xReturn = NULL;
+            traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
+        }
+
+        return xReturn;
+    }
+
+#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
+{
+    StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
+
+    configASSERT( pxStreamBuffer );
+
+    traceSTREAM_BUFFER_DELETE( xStreamBuffer );
+
+    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
+    {
+        #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+            {
+                /* Both the structure and the buffer were allocated using a single call
+                * to pvPortMalloc(), hence only one call to vPortFree() is required. */
+                vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
+            }
+        #else
+            {
+                /* Should not be possible to get here, ucFlags must be corrupt.
+                 * Force an assert. */
+                configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
+            }
+        #endif
+    }
+    else
+    {
+        /* The structure and buffer were not allocated dynamically and cannot be
+         * freed - just scrub the structure so future use will assert. */
+        ( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
+    }
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    BaseType_t xReturn = pdFAIL;
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxStreamBufferNumber;
+    #endif
+
+    configASSERT( pxStreamBuffer );
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        {
+            /* Store the stream buffer number so it can be restored after the
+             * reset. */
+            uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
+        }
+    #endif
+
+    /* Can only reset a message buffer if there are no tasks blocked on it. */
+    taskENTER_CRITICAL();
+    {
+        if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
+        {
+            if( pxStreamBuffer->xTaskWaitingToSend == NULL )
+            {
+                prvInitialiseNewStreamBuffer( pxStreamBuffer,
+                                              pxStreamBuffer->pucBuffer,
+                                              pxStreamBuffer->xLength,
+                                              pxStreamBuffer->xTriggerLevelBytes,
+                                              pxStreamBuffer->ucFlags );
+                xReturn = pdPASS;
+
+                #if ( configUSE_TRACE_FACILITY == 1 )
+                    {
+                        pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+                    }
+                #endif
+
+                traceSTREAM_BUFFER_RESET( xStreamBuffer );
+            }
+        }
+    }
+    taskEXIT_CRITICAL();
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer,
+                                         size_t xTriggerLevel )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    BaseType_t xReturn;
+
+    configASSERT( pxStreamBuffer );
+
+    /* It is not valid for the trigger level to be 0. */
+    if( xTriggerLevel == ( size_t ) 0 )
+    {
+        xTriggerLevel = ( size_t ) 1;
+    }
+
+    /* The trigger level is the number of bytes that must be in the stream
+     * buffer before a task that is waiting for data is unblocked. */
+    if( xTriggerLevel <= pxStreamBuffer->xLength )
+    {
+        pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
+        xReturn = pdPASS;
+    }
+    else
+    {
+        xReturn = pdFALSE;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    size_t xSpace;
+
+    configASSERT( pxStreamBuffer );
+
+    xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
+    xSpace -= pxStreamBuffer->xHead;
+    xSpace -= ( size_t ) 1;
+
+    if( xSpace >= pxStreamBuffer->xLength )
+    {
+        xSpace -= pxStreamBuffer->xLength;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    return xSpace;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
+{
+    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    size_t xReturn;
+
+    configASSERT( pxStreamBuffer );
+
+    xReturn = prvBytesInBuffer( pxStreamBuffer );
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
+                          const void * pvTxData,
+                          size_t xDataLengthBytes,
+                          TickType_t xTicksToWait )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    size_t xReturn, xSpace = 0;
+    size_t xRequiredSpace = xDataLengthBytes;
+    TimeOut_t xTimeOut;
+
+    /* The maximum amount of space a stream buffer will ever report is its length
+     * minus 1. */
+    const size_t xMaxReportedSpace = pxStreamBuffer->xLength - ( size_t ) 1;
+
+    configASSERT( pvTxData );
+    configASSERT( pxStreamBuffer );
+
+    /* This send function is used to write to both message buffers and stream
+     * buffers.  If this is a message buffer then the space needed must be
+     * increased by the amount of bytes needed to store the length of the
+     * message. */
+    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+    {
+        xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+
+        /* Overflow? */
+        configASSERT( xRequiredSpace > xDataLengthBytes );
+
+        /* If this is a message buffer then it must be possible to write the
+         * whole message. */
+        if( xRequiredSpace > xMaxReportedSpace )
+        {
+            /* The message would not fit even if the entire buffer was empty,
+             * so don't wait for space. */
+            xTicksToWait = ( TickType_t ) 0;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        /* If this is a stream buffer then it is acceptable to write only part
+         * of the message to the buffer.  Cap the length to the total length of
+         * the buffer. */
+        if( xRequiredSpace > xMaxReportedSpace )
+        {
+            xRequiredSpace = xMaxReportedSpace;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+    if( xTicksToWait != ( TickType_t ) 0 )
+    {
+        vTaskSetTimeOutState( &xTimeOut );
+
+        do
+        {
+            /* Wait until the required number of bytes are free in the message
+             * buffer. */
+            taskENTER_CRITICAL();
+            {
+                xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+
+                if( xSpace < xRequiredSpace )
+                {
+                    /* Clear notification state as going to wait for space. */
+                    ( void ) xTaskNotifyStateClear( NULL );
+
+                    /* Should only be one writer. */
+                    configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
+                    pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
+                }
+                else
+                {
+                    taskEXIT_CRITICAL();
+                    break;
+                }
+            }
+            taskEXIT_CRITICAL();
+
+            traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
+            ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+            pxStreamBuffer->xTaskWaitingToSend = NULL;
+        } while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    if( xSpace == ( size_t ) 0 )
+    {
+        xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+    if( xReturn > ( size_t ) 0 )
+    {
+        traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );
+
+        /* Was a task waiting for the data? */
+        if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+        {
+            sbSEND_COMPLETED( pxStreamBuffer );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+        traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
+                                 const void * pvTxData,
+                                 size_t xDataLengthBytes,
+                                 BaseType_t * const pxHigherPriorityTaskWoken )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    size_t xReturn, xSpace;
+    size_t xRequiredSpace = xDataLengthBytes;
+
+    configASSERT( pvTxData );
+    configASSERT( pxStreamBuffer );
+
+    /* This send function is used to write to both message buffers and stream
+     * buffers.  If this is a message buffer then the space needed must be
+     * increased by the amount of bytes needed to store the length of the
+     * message. */
+    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+    {
+        xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
+    xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
+
+    if( xReturn > ( size_t ) 0 )
+    {
+        /* Was a task waiting for the data? */
+        if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
+        {
+            sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
+                                       const void * pvTxData,
+                                       size_t xDataLengthBytes,
+                                       size_t xSpace,
+                                       size_t xRequiredSpace )
+{
+    BaseType_t xShouldWrite;
+    size_t xReturn;
+
+    if( xSpace == ( size_t ) 0 )
+    {
+        /* Doesn't matter if this is a stream buffer or a message buffer, there
+         * is no space to write. */
+        xShouldWrite = pdFALSE;
+    }
+    else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
+    {
+        /* This is a stream buffer, as opposed to a message buffer, so writing a
+         * stream of bytes rather than discrete messages.  Write as many bytes as
+         * possible. */
+        xShouldWrite = pdTRUE;
+        xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
+    }
+    else if( xSpace >= xRequiredSpace )
+    {
+        /* This is a message buffer, as opposed to a stream buffer, and there
+         * is enough space to write both the message length and the message itself
+         * into the buffer.  Start by writing the length of the data, the data
+         * itself will be written later in this function. */
+        xShouldWrite = pdTRUE;
+        ( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
+    }
+    else
+    {
+        /* There is space available, but not enough space. */
+        xShouldWrite = pdFALSE;
+    }
+
+    if( xShouldWrite != pdFALSE )
+    {
+        /* Writes the data itself. */
+        xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alignment and access. */
+    }
+    else
+    {
+        xReturn = 0;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
+                             void * pvRxData,
+                             size_t xBufferLengthBytes,
+                             TickType_t xTicksToWait )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+    configASSERT( pvRxData );
+    configASSERT( pxStreamBuffer );
+
+    /* This receive function is used by both message buffers, which store
+     * discrete messages, and stream buffers, which store a continuous stream of
+     * bytes.  Discrete messages include an additional
+     * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+     * message. */
+    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+    {
+        xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+    }
+    else
+    {
+        xBytesToStoreMessageLength = 0;
+    }
+
+    if( xTicksToWait != ( TickType_t ) 0 )
+    {
+        /* Checking if there is data and clearing the notification state must be
+         * performed atomically. */
+        taskENTER_CRITICAL();
+        {
+            xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+            /* If this function was invoked by a message buffer read then
+             * xBytesToStoreMessageLength holds the number of bytes used to hold
+             * the length of the next discrete message.  If this function was
+             * invoked by a stream buffer read then xBytesToStoreMessageLength will
+             * be 0. */
+            if( xBytesAvailable <= xBytesToStoreMessageLength )
+            {
+                /* Clear notification state as going to wait for data. */
+                ( void ) xTaskNotifyStateClear( NULL );
+
+                /* Should only be one reader. */
+                configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
+                pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        if( xBytesAvailable <= xBytesToStoreMessageLength )
+        {
+            /* Wait for data to be available. */
+            traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
+            ( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
+            pxStreamBuffer->xTaskWaitingToReceive = NULL;
+
+            /* Recheck the data available after blocking. */
+            xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+    }
+
+    /* Whether receiving a discrete message (where xBytesToStoreMessageLength
+     * holds the number of bytes used to store the message length) or a stream of
+     * bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+     * available must be greater than xBytesToStoreMessageLength to be able to
+     * read bytes from the buffer. */
+    if( xBytesAvailable > xBytesToStoreMessageLength )
+    {
+        xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+        /* Was a task waiting for space in the buffer? */
+        if( xReceivedLength != ( size_t ) 0 )
+        {
+            traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
+            sbRECEIVE_COMPLETED( pxStreamBuffer );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    size_t xReturn, xBytesAvailable, xOriginalTail;
+    configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
+
+    configASSERT( pxStreamBuffer );
+
+    /* Ensure the stream buffer is being used as a message buffer. */
+    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+    {
+        xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+        if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
+        {
+            /* The number of bytes available is greater than the number of bytes
+             * required to hold the length of the next message, so another message
+             * is available.  Return its length without removing the length bytes
+             * from the buffer.  A copy of the tail is stored so the buffer can be
+             * returned to its prior state as the message is not actually being
+             * removed from the buffer. */
+            xOriginalTail = pxStreamBuffer->xTail;
+            ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );
+            xReturn = ( size_t ) xTempReturn;
+            pxStreamBuffer->xTail = xOriginalTail;
+        }
+        else
+        {
+            /* The minimum amount of bytes in a message buffer is
+             * ( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
+             * less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
+             * value is 0. */
+            configASSERT( xBytesAvailable == 0 );
+            xReturn = 0;
+        }
+    }
+    else
+    {
+        xReturn = 0;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
+                                    void * pvRxData,
+                                    size_t xBufferLengthBytes,
+                                    BaseType_t * const pxHigherPriorityTaskWoken )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
+
+    configASSERT( pvRxData );
+    configASSERT( pxStreamBuffer );
+
+    /* This receive function is used by both message buffers, which store
+     * discrete messages, and stream buffers, which store a continuous stream of
+     * bytes.  Discrete messages include an additional
+     * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
+     * message. */
+    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+    {
+        xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+    }
+    else
+    {
+        xBytesToStoreMessageLength = 0;
+    }
+
+    xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
+
+    /* Whether receiving a discrete message (where xBytesToStoreMessageLength
+     * holds the number of bytes used to store the message length) or a stream of
+     * bytes (where xBytesToStoreMessageLength is zero), the number of bytes
+     * available must be greater than xBytesToStoreMessageLength to be able to
+     * read bytes from the buffer. */
+    if( xBytesAvailable > xBytesToStoreMessageLength )
+    {
+        xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
+
+        /* Was a task waiting for space in the buffer? */
+        if( xReceivedLength != ( size_t ) 0 )
+        {
+            sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
+
+    return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadMessageFromBuffer( StreamBuffer_t * pxStreamBuffer,
+                                        void * pvRxData,
+                                        size_t xBufferLengthBytes,
+                                        size_t xBytesAvailable,
+                                        size_t xBytesToStoreMessageLength )
+{
+    size_t xOriginalTail, xReceivedLength, xNextMessageLength;
+    configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
+
+    if( xBytesToStoreMessageLength != ( size_t ) 0 )
+    {
+        /* A discrete message is being received.  First receive the length
+         * of the message.  A copy of the tail is stored so the buffer can be
+         * returned to its prior state if the length of the message is too
+         * large for the provided buffer. */
+        xOriginalTail = pxStreamBuffer->xTail;
+        ( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
+        xNextMessageLength = ( size_t ) xTempNextMessageLength;
+
+        /* Reduce the number of bytes available by the number of bytes just
+         * read out. */
+        xBytesAvailable -= xBytesToStoreMessageLength;
+
+        /* Check there is enough space in the buffer provided by the
+         * user. */
+        if( xNextMessageLength > xBufferLengthBytes )
+        {
+            /* The user has provided insufficient space to read the message
+             * so return the buffer to its previous state (so the length of
+             * the message is in the buffer again). */
+            pxStreamBuffer->xTail = xOriginalTail;
+            xNextMessageLength = 0;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        /* A stream of bytes is being received (as opposed to a discrete
+         * message), so read as many bytes as possible. */
+        xNextMessageLength = xBufferLengthBytes;
+    }
+
+    /* Read the actual data. */
+    xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
+
+    return xReceivedLength;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
+{
+    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    BaseType_t xReturn;
+    size_t xTail;
+
+    configASSERT( pxStreamBuffer );
+
+    /* True if no bytes are available. */
+    xTail = pxStreamBuffer->xTail;
+
+    if( pxStreamBuffer->xHead == xTail )
+    {
+        xReturn = pdTRUE;
+    }
+    else
+    {
+        xReturn = pdFALSE;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
+{
+    BaseType_t xReturn;
+    size_t xBytesToStoreMessageLength;
+    const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+
+    configASSERT( pxStreamBuffer );
+
+    /* This generic version of the receive function is used by both message
+     * buffers, which store discrete messages, and stream buffers, which store a
+     * continuous stream of bytes.  Discrete messages include an additional
+     * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
+    if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
+    {
+        xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
+    }
+    else
+    {
+        xBytesToStoreMessageLength = 0;
+    }
+
+    /* True if the available space equals zero. */
+    if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
+    {
+        xReturn = pdTRUE;
+    }
+    else
+    {
+        xReturn = pdFALSE;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
+                                              BaseType_t * pxHigherPriorityTaskWoken )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    BaseType_t xReturn;
+    UBaseType_t uxSavedInterruptStatus;
+
+    configASSERT( pxStreamBuffer );
+
+    uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
+        {
+            ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
+                                         ( uint32_t ) 0,
+                                         eNoAction,
+                                         pxHigherPriorityTaskWoken );
+            ( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
+            xReturn = pdTRUE;
+        }
+        else
+        {
+            xReturn = pdFALSE;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer,
+                                                 BaseType_t * pxHigherPriorityTaskWoken )
+{
+    StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
+    BaseType_t xReturn;
+    UBaseType_t uxSavedInterruptStatus;
+
+    configASSERT( pxStreamBuffer );
+
+    uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
+    {
+        if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
+        {
+            ( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
+                                         ( uint32_t ) 0,
+                                         eNoAction,
+                                         pxHigherPriorityTaskWoken );
+            ( pxStreamBuffer )->xTaskWaitingToSend = NULL;
+            xReturn = pdTRUE;
+        }
+        else
+        {
+            xReturn = pdFALSE;
+        }
+    }
+    portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer,
+                                     const uint8_t * pucData,
+                                     size_t xCount )
+{
+    size_t xNextHead, xFirstLength;
+
+    configASSERT( xCount > ( size_t ) 0 );
+
+    xNextHead = pxStreamBuffer->xHead;
+
+    /* Calculate the number of bytes that can be added in the first write -
+     * which may be less than the total number of bytes that need to be added if
+     * the buffer will wrap back to the beginning. */
+    xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
+
+    /* Write as many bytes as can be written in the first write. */
+    configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
+    ( void ) memcpy( ( void * ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+    /* If the number of bytes written was less than the number that could be
+     * written in the first write... */
+    if( xCount > xFirstLength )
+    {
+        /* ...then write the remaining bytes to the start of the buffer. */
+        configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
+        ( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    xNextHead += xCount;
+
+    if( xNextHead >= pxStreamBuffer->xLength )
+    {
+        xNextHead -= pxStreamBuffer->xLength;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    pxStreamBuffer->xHead = xNextHead;
+
+    return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvReadBytesFromBuffer( StreamBuffer_t * pxStreamBuffer,
+                                      uint8_t * pucData,
+                                      size_t xMaxCount,
+                                      size_t xBytesAvailable )
+{
+    size_t xCount, xFirstLength, xNextTail;
+
+    /* Use the minimum of the wanted bytes and the available bytes. */
+    xCount = configMIN( xBytesAvailable, xMaxCount );
+
+    if( xCount > ( size_t ) 0 )
+    {
+        xNextTail = pxStreamBuffer->xTail;
+
+        /* Calculate the number of bytes that can be read - which may be
+         * less than the number wanted if the data wraps around to the start of
+         * the buffer. */
+        xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );
+
+        /* Obtain the number of bytes it is possible to obtain in the first
+         * read.  Asserts check bounds of read and write. */
+        configASSERT( xFirstLength <= xMaxCount );
+        configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
+        ( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+
+        /* If the total number of wanted bytes is greater than the number
+         * that could be read in the first read... */
+        if( xCount > xFirstLength )
+        {
+            /*...then read the remaining bytes from the start of the buffer. */
+            configASSERT( xCount <= xMaxCount );
+            ( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        /* Move the tail pointer to effectively remove the data read from
+         * the buffer. */
+        xNextTail += xCount;
+
+        if( xNextTail >= pxStreamBuffer->xLength )
+        {
+            xNextTail -= pxStreamBuffer->xLength;
+        }
+
+        pxStreamBuffer->xTail = xNextTail;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
+{
+/* Returns the distance between xTail and xHead. */
+    size_t xCount;
+
+    xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
+    xCount -= pxStreamBuffer->xTail;
+
+    if( xCount >= pxStreamBuffer->xLength )
+    {
+        xCount -= pxStreamBuffer->xLength;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    return xCount;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
+                                          uint8_t * const pucBuffer,
+                                          size_t xBufferSizeBytes,
+                                          size_t xTriggerLevelBytes,
+                                          uint8_t ucFlags )
+{
+    /* Assert here is deliberately writing to the entire buffer to ensure it can
+     * be written to without generating exceptions, and is setting the buffer to a
+     * known value to assist in development/debugging. */
+    #if ( configASSERT_DEFINED == 1 )
+        {
+            /* The value written just has to be identifiable when looking at the
+             * memory.  Don't use 0xA5 as that is the stack fill value and could
+             * result in confusion as to what is actually being observed. */
+            const BaseType_t xWriteValue = 0x55;
+            configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
+        } /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
+    #endif
+
+    ( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
+    pxStreamBuffer->pucBuffer = pucBuffer;
+    pxStreamBuffer->xLength = xBufferSizeBytes;
+    pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
+    pxStreamBuffer->ucFlags = ucFlags;
+}
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
+    {
+        return xStreamBuffer->uxStreamBufferNumber;
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer,
+                                             UBaseType_t uxStreamBufferNumber )
+    {
+        xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
+    {
+        return( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/tasks.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/tasks.c
new file mode 100644
index 0000000..884005a
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/tasks.c
@@ -0,0 +1,5395 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "stack_macros.h"
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+ * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+ * for the header files above, but not in this file, in order to generate the
+ * correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
+
+/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
+ * functions but without including stdio.h here. */
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
+
+/* At the bottom of this file are two optional functions that can be used
+ * to generate human readable text from the raw data generated by the
+ * uxTaskGetSystemState() function.  Note the formatting functions are provided
+ * for convenience only, and are NOT considered part of the kernel. */
+    #include <stdio.h>
+#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
+
+#if ( configUSE_PREEMPTION == 0 )
+
+/* If the cooperative scheduler is being used then a yield should not be
+ * performed just because a higher priority task has been woken. */
+    #define taskYIELD_IF_USING_PREEMPTION()
+#else
+    #define taskYIELD_IF_USING_PREEMPTION()    portYIELD_WITHIN_API()
+#endif
+
+/* Values that can be assigned to the ucNotifyState member of the TCB. */
+#define taskNOT_WAITING_NOTIFICATION              ( ( uint8_t ) 0 ) /* Must be zero as it is the initialised value. */
+#define taskWAITING_NOTIFICATION                  ( ( uint8_t ) 1 )
+#define taskNOTIFICATION_RECEIVED                 ( ( uint8_t ) 2 )
+
+/*
+ * The value used to fill the stack of a task when the task is created.  This
+ * is used purely for checking the high water mark for tasks.
+ */
+#define tskSTACK_FILL_BYTE                        ( 0xa5U )
+
+/* Bits used to recored how a task's stack and TCB were allocated. */
+#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB    ( ( uint8_t ) 0 )
+#define tskSTATICALLY_ALLOCATED_STACK_ONLY        ( ( uint8_t ) 1 )
+#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB     ( ( uint8_t ) 2 )
+
+/* If any of the following are set then task stacks are filled with a known
+ * value so the high water mark can be determined.  If none of the following are
+ * set then don't fill the stack so there is no unnecessary dependency on memset. */
+#if ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+    #define tskSET_NEW_STACKS_TO_KNOWN_VALUE    1
+#else
+    #define tskSET_NEW_STACKS_TO_KNOWN_VALUE    0
+#endif
+
+/*
+ * Macros used by vListTask to indicate which state a task is in.
+ */
+#define tskRUNNING_CHAR      ( 'X' )
+#define tskBLOCKED_CHAR      ( 'B' )
+#define tskREADY_CHAR        ( 'R' )
+#define tskDELETED_CHAR      ( 'D' )
+#define tskSUSPENDED_CHAR    ( 'S' )
+
+/*
+ * Some kernel aware debuggers require the data the debugger needs access to be
+ * global, rather than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+    #define static
+#endif
+
+/* The name allocated to the Idle task.  This can be overridden by defining
+ * configIDLE_TASK_NAME in FreeRTOSConfig.h. */
+#ifndef configIDLE_TASK_NAME
+    #define configIDLE_TASK_NAME    "IDLE"
+#endif
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+
+/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
+ * performed in a generic way that is not optimised to any particular
+ * microcontroller architecture. */
+
+/* uxTopReadyPriority holds the priority of the highest priority ready
+ * state task. */
+    #define taskRECORD_READY_PRIORITY( uxPriority ) \
+    {                                               \
+        if( ( uxPriority ) > uxTopReadyPriority )   \
+        {                                           \
+            uxTopReadyPriority = ( uxPriority );    \
+        }                                           \
+    } /* taskRECORD_READY_PRIORITY */
+
+/*-----------------------------------------------------------*/
+
+    #define taskSELECT_HIGHEST_PRIORITY_TASK()                                \
+    {                                                                         \
+        UBaseType_t uxTopPriority = uxTopReadyPriority;                       \
+                                                                              \
+        /* Find the highest priority queue that contains ready tasks. */      \
+        while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) ) \
+        {                                                                     \
+            configASSERT( uxTopPriority );                                    \
+            --uxTopPriority;                                                  \
+        }                                                                     \
+                                                                              \
+        /* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of \
+         * the  same priority get an equal share of the processor time. */                    \
+        listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) ); \
+        uxTopReadyPriority = uxTopPriority;                                                   \
+    } /* taskSELECT_HIGHEST_PRIORITY_TASK */
+
+/*-----------------------------------------------------------*/
+
+/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
+ * they are only required when a port optimised method of task selection is
+ * being used. */
+    #define taskRESET_READY_PRIORITY( uxPriority )
+    #define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
+ * performed in a way that is tailored to the particular microcontroller
+ * architecture being used. */
+
+/* A port optimised version is provided.  Call the port defined macros. */
+    #define taskRECORD_READY_PRIORITY( uxPriority )    portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+/*-----------------------------------------------------------*/
+
+    #define taskSELECT_HIGHEST_PRIORITY_TASK()                                                  \
+    {                                                                                           \
+        UBaseType_t uxTopPriority;                                                              \
+                                                                                                \
+        /* Find the highest priority list that contains ready tasks. */                         \
+        portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );                          \
+        configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 ); \
+        listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );   \
+    } /* taskSELECT_HIGHEST_PRIORITY_TASK() */
+
+/*-----------------------------------------------------------*/
+
+/* A port optimised version is provided, call it only if the TCB being reset
+ * is being referenced from a ready list.  If it is referenced from a delayed
+ * or suspended list then it won't be in a ready list. */
+    #define taskRESET_READY_PRIORITY( uxPriority )                                                     \
+    {                                                                                                  \
+        if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 ) \
+        {                                                                                              \
+            portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );                        \
+        }                                                                                              \
+    }
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
+ * count overflows. */
+#define taskSWITCH_DELAYED_LISTS()                                                \
+    {                                                                             \
+        List_t * pxTemp;                                                          \
+                                                                                  \
+        /* The delayed tasks list should be empty when the lists are switched. */ \
+        configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );               \
+                                                                                  \
+        pxTemp = pxDelayedTaskList;                                               \
+        pxDelayedTaskList = pxOverflowDelayedTaskList;                            \
+        pxOverflowDelayedTaskList = pxTemp;                                       \
+        xNumOfOverflows++;                                                        \
+        prvResetNextTaskUnblockTime();                                            \
+    }
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Place the task represented by pxTCB into the appropriate ready list for
+ * the task.  It is inserted at the end of the list.
+ */
+#define prvAddTaskToReadyList( pxTCB )                                                                 \
+    traceMOVED_TASK_TO_READY_STATE( pxTCB );                                                           \
+    taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );                                                \
+    vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
+    tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+/*-----------------------------------------------------------*/
+
+/*
+ * Several functions take an TaskHandle_t parameter that can optionally be NULL,
+ * where NULL is used to indicate that the handle of the currently executing
+ * task should be used in place of the parameter.  This macro simply checks to
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.
+ */
+#define prvGetTCBFromHandle( pxHandle )    ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )
+
+/* The item value of the event list item is normally used to hold the priority
+ * of the task to which it belongs (coded to allow it to be held in reverse
+ * priority order).  However, it is occasionally borrowed for other purposes.  It
+ * is important its value is not updated due to a task priority change while it is
+ * being used for another purpose.  The following bit definition is used to inform
+ * the scheduler that the value should not be changed - in which case it is the
+ * responsibility of whichever module is using the value to ensure it gets set back
+ * to its original value when it is released. */
+#if ( configUSE_16_BIT_TICKS == 1 )
+    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    0x8000U
+#else
+    #define taskEVENT_LIST_ITEM_VALUE_IN_USE    0x80000000UL
+#endif
+
+/*
+ * Task control block.  A task control block (TCB) is allocated for each task,
+ * and stores task state information, including a pointer to the task's context
+ * (the task's run time environment, including register values)
+ */
+typedef struct tskTaskControlBlock       /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+{
+    volatile StackType_t * pxTopOfStack; /*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+    #if ( portUSING_MPU_WRAPPERS == 1 )
+        xMPU_SETTINGS xMPUSettings; /*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+    #endif
+
+    ListItem_t xStateListItem;                  /*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+    ListItem_t xEventListItem;                  /*< Used to reference a task from an event list. */
+    UBaseType_t uxPriority;                     /*< The priority of the task.  0 is the lowest priority. */
+    StackType_t * pxStack;                      /*< Points to the start of the stack. */
+    char pcTaskName[ configMAX_TASK_NAME_LEN ]; /*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+    #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
+        StackType_t * pxEndOfStack; /*< Points to the highest valid address for the stack. */
+    #endif
+
+    #if ( portCRITICAL_NESTING_IN_TCB == 1 )
+        UBaseType_t uxCriticalNesting; /*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+    #endif
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+        UBaseType_t uxTCBNumber;  /*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+        UBaseType_t uxTaskNumber; /*< Stores a number specifically for use by third party trace code. */
+    #endif
+
+    #if ( configUSE_MUTEXES == 1 )
+        UBaseType_t uxBasePriority; /*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+        UBaseType_t uxMutexesHeld;
+    #endif
+
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+        TaskHookFunction_t pxTaskTag;
+    #endif
+
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+        void * pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+    #endif
+
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
+        uint32_t ulRunTimeCounter; /*< Stores the amount of time the task has spent in the Running state. */
+    #endif
+
+    #if ( configUSE_NEWLIB_REENTRANT == 1 )
+
+        /* Allocate a Newlib reent structure that is specific to this task.
+         * Note Newlib support has been included by popular demand, but is not
+         * used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+         * responsible for resulting newlib operation.  User must be familiar with
+         * newlib and must provide system-wide implementations of the necessary
+         * stubs. Be warned that (at the time of writing) the current newlib design
+         * implements a system-wide malloc() that must be provided with locks.
+         *
+         * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+         * for additional information. */
+        struct  _reent xNewLib_reent;
+    #endif
+
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+        volatile uint32_t ulNotifiedValue[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];
+        volatile uint8_t ucNotifyState[ configTASK_NOTIFICATION_ARRAY_ENTRIES ];
+    #endif
+
+    /* See the comments in FreeRTOS.h with the definition of
+     * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+    #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+        uint8_t ucStaticallyAllocated;                     /*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+    #endif
+
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
+        uint8_t ucDelayAborted;
+    #endif
+
+    #if ( configUSE_POSIX_ERRNO == 1 )
+        int iTaskErrno;
+    #endif
+} tskTCB;
+
+/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
+ * below to enable the use of older kernel aware debuggers. */
+typedef tskTCB TCB_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+ * which static variables must be declared volatile. */
+PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+
+/* Lists for ready and blocked tasks. --------------------
+ * xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but
+ * doing so breaks some kernel aware debuggers and debuggers that rely on removing
+ * the static qualifier. */
+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ]; /*< Prioritised ready tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList1;                         /*< Delayed tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList2;                         /*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;              /*< Points to the delayed task list currently being used. */
+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;      /*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t xPendingReadyList;                         /*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+    PRIVILEGED_DATA static List_t xTasksWaitingTermination; /*< Tasks that have been deleted - but their memory not yet freed. */
+    PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
+
+#endif
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+    PRIVILEGED_DATA static List_t xSuspendedTaskList; /*< Tasks that are currently suspended. */
+
+#endif
+
+/* Global POSIX errno. Its value is changed upon context switching to match
+ * the errno of the currently running task. */
+#if ( configUSE_POSIX_ERRNO == 1 )
+    int FreeRTOS_errno = 0;
+#endif
+
+/* Other file private variables. --------------------------------*/
+PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks = ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority = tskIDLE_PRIORITY;
+PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning = pdFALSE;
+PRIVILEGED_DATA static volatile TickType_t xPendedTicks = ( TickType_t ) 0U;
+PRIVILEGED_DATA static volatile BaseType_t xYieldPending = pdFALSE;
+PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows = ( BaseType_t ) 0;
+PRIVILEGED_DATA static UBaseType_t uxTaskNumber = ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime = ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
+PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle = NULL;                          /*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */
+
+/* Improve support for OpenOCD. The kernel tracks Ready tasks via priority lists.
+ * For tracking the state of remote threads, OpenOCD uses uxTopUsedPriority
+ * to determine the number of priority lists to read back from the remote target. */
+const volatile UBaseType_t uxTopUsedPriority = configMAX_PRIORITIES - 1U;
+
+/* Context switches are held pending while the scheduler is suspended.  Also,
+ * interrupts must not manipulate the xStateListItem of a TCB, or any of the
+ * lists the xStateListItem can be referenced from, if the scheduler is suspended.
+ * If an interrupt needs to unblock a task while the scheduler is suspended then it
+ * moves the task's event list item into the xPendingReadyList, ready for the
+ * kernel to move the task from the pending ready list into the real ready list
+ * when the scheduler is unsuspended.  The pending ready list itself can only be
+ * accessed from a critical section. */
+PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended = ( UBaseType_t ) pdFALSE;
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+/* Do not move these variables to function scope as doing so prevents the
+ * code working with debuggers that need to remove the static qualifier. */
+    PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;    /*< Holds the value of a timer/counter the last time a task was switched in. */
+    PRIVILEGED_DATA static volatile uint32_t ulTotalRunTime = 0UL; /*< Holds the total amount of execution time as defined by the run time counter clock. */
+
+#endif
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+/* File private functions. --------------------------------*/
+
+/**
+ * Utility task that simply returns pdTRUE if the task referenced by xTask is
+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask
+ * is in any other state.
+ */
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+    static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first task.
+ */
+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The idle task, which as all tasks is implemented as a never ending loop.
+ * The idle task is automatically created and added to the ready lists upon
+ * creation of the first user task.
+ *
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters ) PRIVILEGED_FUNCTION;
+
+/*
+ * Utility to free all memory allocated by the scheduler to hold a TCB,
+ * including the stack pointed to by the TCB.
+ *
+ * This does not free memory allocated by the task itself (i.e. memory
+ * allocated by calls to pvPortMalloc from within the tasks application code).
+ */
+#if ( INCLUDE_vTaskDelete == 1 )
+
+    static void prvDeleteTCB( TCB_t * pxTCB ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Used only by the idle task.  This checks to see if anything has been placed
+ * in the list of tasks waiting to be deleted.  If so the task is cleaned up
+ * and its TCB deleted.
+ */
+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The currently executing task is entering the Blocked state.  Add the task to
+ * either the current or the overflow delayed task list.
+ */
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
+                                            const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * Fills an TaskStatus_t structure with information on each task that is
+ * referenced from the pxList list (which may be a ready list, a delayed list,
+ * a suspended list, etc.).
+ *
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
+ * NORMAL APPLICATION CODE.
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray,
+                                                     List_t * pxList,
+                                                     eTaskState eState ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Searches pxList for a task with name pcNameToQuery - returning a handle to
+ * the task if it is found, or NULL if the task is not found.
+ */
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+    static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,
+                                                     const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * When a task is created, the stack of the task is filled with a known value.
+ * This function determines the 'high water mark' of the task stack by
+ * determining how much of the stack remains at the original preset value.
+ */
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+    static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Return the amount of time, in ticks, that will pass before the kernel will
+ * next move a task from the Blocked state to the Running state.
+ *
+ * This conditional compilation should use inequality to 0, not equality to 1.
+ * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
+ * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
+ * set to a value other than 1.
+ */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+    static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Set xNextTaskUnblockTime to the time at which the next Blocked state task
+ * will exit the Blocked state.
+ */
+static void prvResetNextTaskUnblockTime( void ) PRIVILEGED_FUNCTION;
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+/*
+ * Helper function used to pad task names with spaces when printing out
+ * human readable tables of task information.
+ */
+    static char * prvWriteNameToBuffer( char * pcBuffer,
+                                        const char * pcTaskName ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Called after a Task_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
+                                  const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                  const uint32_t ulStackDepth,
+                                  void * const pvParameters,
+                                  UBaseType_t uxPriority,
+                                  TaskHandle_t * const pxCreatedTask,
+                                  TCB_t * pxNewTCB,
+                                  const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a new task has been created and initialised to place the task
+ * under the control of the scheduler.
+ */
+static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB ) PRIVILEGED_FUNCTION;
+
+/*
+ * freertos_tasks_c_additions_init() should only be called if the user definable
+ * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
+ * called by the function.
+ */
+#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+
+    static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+    TaskHandle_t xTaskCreateStatic( TaskFunction_t pxTaskCode,
+                                    const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                    const uint32_t ulStackDepth,
+                                    void * const pvParameters,
+                                    UBaseType_t uxPriority,
+                                    StackType_t * const puxStackBuffer,
+                                    StaticTask_t * const pxTaskBuffer )
+    {
+        TCB_t * pxNewTCB;
+        TaskHandle_t xReturn;
+
+        configASSERT( puxStackBuffer != NULL );
+        configASSERT( pxTaskBuffer != NULL );
+
+        #if ( configASSERT_DEFINED == 1 )
+            {
+                /* Sanity check that the size of the structure used to declare a
+                 * variable of type StaticTask_t equals the size of the real task
+                 * structure. */
+                volatile size_t xSize = sizeof( StaticTask_t );
+                configASSERT( xSize == sizeof( TCB_t ) );
+                ( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
+            }
+        #endif /* configASSERT_DEFINED */
+
+        if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
+        {
+            /* The memory used for the task's TCB and stack are passed into this
+             * function - use them. */
+            pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+            pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
+
+            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+                {
+                    /* Tasks can be created statically or dynamically, so note this
+                     * task was created statically in case the task is later deleted. */
+                    pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+                }
+            #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+            prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+            prvAddNewTaskToReadyList( pxNewTCB );
+        }
+        else
+        {
+            xReturn = NULL;
+        }
+
+        return xReturn;
+    }
+
+#endif /* SUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+    BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition,
+                                            TaskHandle_t * pxCreatedTask )
+    {
+        TCB_t * pxNewTCB;
+        BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+        configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
+        configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
+
+        if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
+        {
+            /* Allocate space for the TCB.  Where the memory comes from depends
+             * on the implementation of the port malloc function and whether or
+             * not static allocation is being used. */
+            pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
+
+            /* Store the stack location in the TCB. */
+            pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+                {
+                    /* Tasks can be created statically or dynamically, so note this
+                     * task was created statically in case the task is later deleted. */
+                    pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+                }
+            #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+            prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
+                                  pxTaskDefinition->pcName,
+                                  ( uint32_t ) pxTaskDefinition->usStackDepth,
+                                  pxTaskDefinition->pvParameters,
+                                  pxTaskDefinition->uxPriority,
+                                  pxCreatedTask, pxNewTCB,
+                                  pxTaskDefinition->xRegions );
+
+            prvAddNewTaskToReadyList( pxNewTCB );
+            xReturn = pdPASS;
+        }
+
+        return xReturn;
+    }
+
+#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+    BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition,
+                                      TaskHandle_t * pxCreatedTask )
+    {
+        TCB_t * pxNewTCB;
+        BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+        configASSERT( pxTaskDefinition->puxStackBuffer );
+
+        if( pxTaskDefinition->puxStackBuffer != NULL )
+        {
+            /* Allocate space for the TCB.  Where the memory comes from depends
+             * on the implementation of the port malloc function and whether or
+             * not static allocation is being used. */
+            pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+            if( pxNewTCB != NULL )
+            {
+                /* Store the stack location in the TCB. */
+                pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+                #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+                    {
+                        /* Tasks can be created statically or dynamically, so note
+                         * this task had a statically allocated stack in case it is
+                         * later deleted.  The TCB was allocated dynamically. */
+                        pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
+                    }
+                #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+                prvInitialiseNewTask( pxTaskDefinition->pvTaskCode,
+                                      pxTaskDefinition->pcName,
+                                      ( uint32_t ) pxTaskDefinition->usStackDepth,
+                                      pxTaskDefinition->pvParameters,
+                                      pxTaskDefinition->uxPriority,
+                                      pxCreatedTask, pxNewTCB,
+                                      pxTaskDefinition->xRegions );
+
+                prvAddNewTaskToReadyList( pxNewTCB );
+                xReturn = pdPASS;
+            }
+        }
+
+        return xReturn;
+    }
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+    BaseType_t xTaskCreate( TaskFunction_t pxTaskCode,
+                            const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                            const configSTACK_DEPTH_TYPE usStackDepth,
+                            void * const pvParameters,
+                            UBaseType_t uxPriority,
+                            TaskHandle_t * const pxCreatedTask )
+    {
+        TCB_t * pxNewTCB;
+        BaseType_t xReturn;
+
+        /* If the stack grows down then allocate the stack then the TCB so the stack
+         * does not grow into the TCB.  Likewise if the stack grows up then allocate
+         * the TCB then the stack. */
+        #if ( portSTACK_GROWTH > 0 )
+            {
+                /* Allocate space for the TCB.  Where the memory comes from depends on
+                 * the implementation of the port malloc function and whether or not static
+                 * allocation is being used. */
+                pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+                if( pxNewTCB != NULL )
+                {
+                    /* Allocate space for the stack used by the task being created.
+                     * The base of the stack memory stored in the TCB so the task can
+                     * be deleted later if required. */
+                    pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+                    if( pxNewTCB->pxStack == NULL )
+                    {
+                        /* Could not allocate the stack.  Delete the allocated TCB. */
+                        vPortFree( pxNewTCB );
+                        pxNewTCB = NULL;
+                    }
+                }
+            }
+        #else /* portSTACK_GROWTH */
+            {
+                StackType_t * pxStack;
+
+                /* Allocate space for the stack used by the task being created. */
+                pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
+
+                if( pxStack != NULL )
+                {
+                    /* Allocate space for the TCB. */
+                    pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
+
+                    if( pxNewTCB != NULL )
+                    {
+                        /* Store the stack location in the TCB. */
+                        pxNewTCB->pxStack = pxStack;
+                    }
+                    else
+                    {
+                        /* The stack cannot be used as the TCB was not created.  Free
+                         * it again. */
+                        vPortFree( pxStack );
+                    }
+                }
+                else
+                {
+                    pxNewTCB = NULL;
+                }
+            }
+        #endif /* portSTACK_GROWTH */
+
+        if( pxNewTCB != NULL )
+        {
+            #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
+                {
+                    /* Tasks can be created statically or dynamically, so note this
+                     * task was created dynamically in case it is later deleted. */
+                    pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
+                }
+            #endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
+
+            prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+            prvAddNewTaskToReadyList( pxNewTCB );
+            xReturn = pdPASS;
+        }
+        else
+        {
+            xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+        }
+
+        return xReturn;
+    }
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTask( TaskFunction_t pxTaskCode,
+                                  const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                  const uint32_t ulStackDepth,
+                                  void * const pvParameters,
+                                  UBaseType_t uxPriority,
+                                  TaskHandle_t * const pxCreatedTask,
+                                  TCB_t * pxNewTCB,
+                                  const MemoryRegion_t * const xRegions )
+{
+    StackType_t * pxTopOfStack;
+    UBaseType_t x;
+
+    #if ( portUSING_MPU_WRAPPERS == 1 )
+        /* Should the task be created in privileged mode? */
+        BaseType_t xRunPrivileged;
+
+        if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
+        {
+            xRunPrivileged = pdTRUE;
+        }
+        else
+        {
+            xRunPrivileged = pdFALSE;
+        }
+        uxPriority &= ~portPRIVILEGE_BIT;
+    #endif /* portUSING_MPU_WRAPPERS == 1 */
+
+    /* Avoid dependency on memset() if it is not required. */
+    #if ( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
+        {
+            /* Fill the stack with a known value to assist debugging. */
+            ( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+        }
+    #endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
+
+    /* Calculate the top of stack address.  This depends on whether the stack
+     * grows from high memory to low (as per the 80x86) or vice versa.
+     * portSTACK_GROWTH is used to make the result positive or negative as required
+     * by the port. */
+    #if ( portSTACK_GROWTH < 0 )
+        {
+            pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
+            pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
+
+            /* Check the alignment of the calculated top of stack is correct. */
+            configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+            #if ( configRECORD_STACK_HIGH_ADDRESS == 1 )
+                {
+                    /* Also record the stack's high address, which may assist
+                     * debugging. */
+                    pxNewTCB->pxEndOfStack = pxTopOfStack;
+                }
+            #endif /* configRECORD_STACK_HIGH_ADDRESS */
+        }
+    #else /* portSTACK_GROWTH */
+        {
+            pxTopOfStack = pxNewTCB->pxStack;
+
+            /* Check the alignment of the stack buffer is correct. */
+            configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+            /* The other extreme of the stack space is required if stack checking is
+             * performed. */
+            pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+        }
+    #endif /* portSTACK_GROWTH */
+
+    /* Store the task name in the TCB. */
+    if( pcName != NULL )
+    {
+        for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+        {
+            pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+
+            /* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+             * configMAX_TASK_NAME_LEN characters just in case the memory after the
+             * string is not accessible (extremely unlikely). */
+            if( pcName[ x ] == ( char ) 0x00 )
+            {
+                break;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+
+        /* Ensure the name string is terminated in the case that the string length
+         * was greater or equal to configMAX_TASK_NAME_LEN. */
+        pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+    }
+    else
+    {
+        /* The task has not been given a name, so just ensure there is a NULL
+         * terminator when it is read out. */
+        pxNewTCB->pcTaskName[ 0 ] = 0x00;
+    }
+
+    /* This is used as an array index so must ensure it's not too large.  First
+     * remove the privilege bit if one is present. */
+    if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+    {
+        uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    pxNewTCB->uxPriority = uxPriority;
+    #if ( configUSE_MUTEXES == 1 )
+        {
+            pxNewTCB->uxBasePriority = uxPriority;
+            pxNewTCB->uxMutexesHeld = 0;
+        }
+    #endif /* configUSE_MUTEXES */
+
+    vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
+    vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
+
+    /* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
+     * back to  the containing TCB from a generic item in a list. */
+    listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
+
+    /* Event lists are always in priority order. */
+    listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+    listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
+
+    #if ( portCRITICAL_NESTING_IN_TCB == 1 )
+        {
+            pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
+        }
+    #endif /* portCRITICAL_NESTING_IN_TCB */
+
+    #if ( configUSE_APPLICATION_TASK_TAG == 1 )
+        {
+            pxNewTCB->pxTaskTag = NULL;
+        }
+    #endif /* configUSE_APPLICATION_TASK_TAG */
+
+    #if ( configGENERATE_RUN_TIME_STATS == 1 )
+        {
+            pxNewTCB->ulRunTimeCounter = 0UL;
+        }
+    #endif /* configGENERATE_RUN_TIME_STATS */
+
+    #if ( portUSING_MPU_WRAPPERS == 1 )
+        {
+            vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
+        }
+    #else
+        {
+            /* Avoid compiler warning about unreferenced parameter. */
+            ( void ) xRegions;
+        }
+    #endif
+
+    #if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+        {
+            memset( ( void * ) &( pxNewTCB->pvThreadLocalStoragePointers[ 0 ] ), 0x00, sizeof( pxNewTCB->pvThreadLocalStoragePointers ) );
+        }
+    #endif
+
+    #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+        {
+            memset( ( void * ) &( pxNewTCB->ulNotifiedValue[ 0 ] ), 0x00, sizeof( pxNewTCB->ulNotifiedValue ) );
+            memset( ( void * ) &( pxNewTCB->ucNotifyState[ 0 ] ), 0x00, sizeof( pxNewTCB->ucNotifyState ) );
+        }
+    #endif
+
+    #if ( configUSE_NEWLIB_REENTRANT == 1 )
+        {
+            /* Initialise this task's Newlib reent structure.
+             * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+             * for additional information. */
+            _REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
+        }
+    #endif
+
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
+        {
+            pxNewTCB->ucDelayAborted = pdFALSE;
+        }
+    #endif
+
+    /* Initialize the TCB stack to look as if the task was already running,
+     * but had been interrupted by the scheduler.  The return address is set
+     * to the start of the task function. Once the stack has been initialised
+     * the top of stack variable is updated. */
+    #if ( portUSING_MPU_WRAPPERS == 1 )
+        {
+            /* If the port has capability to detect stack overflow,
+             * pass the stack end address to the stack initialization
+             * function as well. */
+            #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+                {
+                    #if ( portSTACK_GROWTH < 0 )
+                        {
+                            pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );
+                        }
+                    #else /* portSTACK_GROWTH */
+                        {
+                            pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+                        }
+                    #endif /* portSTACK_GROWTH */
+                }
+            #else /* portHAS_STACK_OVERFLOW_CHECKING */
+                {
+                    pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+                }
+            #endif /* portHAS_STACK_OVERFLOW_CHECKING */
+        }
+    #else /* portUSING_MPU_WRAPPERS */
+        {
+            /* If the port has capability to detect stack overflow,
+             * pass the stack end address to the stack initialization
+             * function as well. */
+            #if ( portHAS_STACK_OVERFLOW_CHECKING == 1 )
+                {
+                    #if ( portSTACK_GROWTH < 0 )
+                        {
+                            pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
+                        }
+                    #else /* portSTACK_GROWTH */
+                        {
+                            pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
+                        }
+                    #endif /* portSTACK_GROWTH */
+                }
+            #else /* portHAS_STACK_OVERFLOW_CHECKING */
+                {
+                    pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+                }
+            #endif /* portHAS_STACK_OVERFLOW_CHECKING */
+        }
+    #endif /* portUSING_MPU_WRAPPERS */
+
+    if( pxCreatedTask != NULL )
+    {
+        /* Pass the handle out in an anonymous way.  The handle can be used to
+         * change the created task's priority, delete the created task, etc.*/
+        *pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+}
+/*-----------------------------------------------------------*/
+
+static void prvAddNewTaskToReadyList( TCB_t * pxNewTCB )
+{
+    /* Ensure interrupts don't access the task lists while the lists are being
+     * updated. */
+    taskENTER_CRITICAL();
+    {
+        uxCurrentNumberOfTasks++;
+
+        if( pxCurrentTCB == NULL )
+        {
+            /* There are no other tasks, or all the other tasks are in
+             * the suspended state - make this the current task. */
+            pxCurrentTCB = pxNewTCB;
+
+            if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+            {
+                /* This is the first task to be created so do the preliminary
+                 * initialisation required.  We will not recover if this call
+                 * fails, but we will report the failure. */
+                prvInitialiseTaskLists();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            /* If the scheduler is not already running, make this task the
+             * current task if it is the highest priority task to be created
+             * so far. */
+            if( xSchedulerRunning == pdFALSE )
+            {
+                if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+                {
+                    pxCurrentTCB = pxNewTCB;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+
+        uxTaskNumber++;
+
+        #if ( configUSE_TRACE_FACILITY == 1 )
+            {
+                /* Add a counter into the TCB for tracing only. */
+                pxNewTCB->uxTCBNumber = uxTaskNumber;
+            }
+        #endif /* configUSE_TRACE_FACILITY */
+        traceTASK_CREATE( pxNewTCB );
+
+        prvAddTaskToReadyList( pxNewTCB );
+
+        portSETUP_TCB( pxNewTCB );
+    }
+    taskEXIT_CRITICAL();
+
+    if( xSchedulerRunning != pdFALSE )
+    {
+        /* If the created task is of a higher priority than the current task
+         * then it should run now. */
+        if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
+        {
+            taskYIELD_IF_USING_PREEMPTION();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+    void vTaskDelete( TaskHandle_t xTaskToDelete )
+    {
+        TCB_t * pxTCB;
+
+        taskENTER_CRITICAL();
+        {
+            /* If null is passed in here then it is the calling task that is
+             * being deleted. */
+            pxTCB = prvGetTCBFromHandle( xTaskToDelete );
+
+            /* Remove task from the ready/delayed list. */
+            if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+            {
+                taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            /* Is the task waiting on an event also? */
+            if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+            {
+                ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            /* Increment the uxTaskNumber also so kernel aware debuggers can
+             * detect that the task lists need re-generating.  This is done before
+             * portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
+             * not return. */
+            uxTaskNumber++;
+
+            if( pxTCB == pxCurrentTCB )
+            {
+                /* A task is deleting itself.  This cannot complete within the
+                 * task itself, as a context switch to another task is required.
+                 * Place the task in the termination list.  The idle task will
+                 * check the termination list and free up any memory allocated by
+                 * the scheduler for the TCB and stack of the deleted task. */
+                vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
+
+                /* Increment the ucTasksDeleted variable so the idle task knows
+                 * there is a task that has been deleted and that it should therefore
+                 * check the xTasksWaitingTermination list. */
+                ++uxDeletedTasksWaitingCleanUp;
+
+                /* Call the delete hook before portPRE_TASK_DELETE_HOOK() as
+                 * portPRE_TASK_DELETE_HOOK() does not return in the Win32 port. */
+                traceTASK_DELETE( pxTCB );
+
+                /* The pre-delete hook is primarily for the Windows simulator,
+                 * in which Windows specific clean up operations are performed,
+                 * after which it is not possible to yield away from this task -
+                 * hence xYieldPending is used to latch that a context switch is
+                 * required. */
+                portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
+            }
+            else
+            {
+                --uxCurrentNumberOfTasks;
+                traceTASK_DELETE( pxTCB );
+                prvDeleteTCB( pxTCB );
+
+                /* Reset the next expected unblock time in case it referred to
+                 * the task that has just been deleted. */
+                prvResetNextTaskUnblockTime();
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        /* Force a reschedule if it is the currently running task that has just
+         * been deleted. */
+        if( xSchedulerRunning != pdFALSE )
+        {
+            if( pxTCB == pxCurrentTCB )
+            {
+                configASSERT( uxSchedulerSuspended == 0 );
+                portYIELD_WITHIN_API();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    }
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskDelayUntil == 1 )
+
+    BaseType_t xTaskDelayUntil( TickType_t * const pxPreviousWakeTime,
+                                const TickType_t xTimeIncrement )
+    {
+        TickType_t xTimeToWake;
+        BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
+
+        configASSERT( pxPreviousWakeTime );
+        configASSERT( ( xTimeIncrement > 0U ) );
+        configASSERT( uxSchedulerSuspended == 0 );
+
+        vTaskSuspendAll();
+        {
+            /* Minor optimisation.  The tick count cannot change in this
+             * block. */
+            const TickType_t xConstTickCount = xTickCount;
+
+            /* Generate the tick time at which the task wants to wake. */
+            xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
+
+            if( xConstTickCount < *pxPreviousWakeTime )
+            {
+                /* The tick count has overflowed since this function was
+                 * lasted called.  In this case the only time we should ever
+                 * actually delay is if the wake time has also  overflowed,
+                 * and the wake time is greater than the tick time.  When this
+                 * is the case it is as if neither time had overflowed. */
+                if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
+                {
+                    xShouldDelay = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                /* The tick time has not overflowed.  In this case we will
+                 * delay if either the wake time has overflowed, and/or the
+                 * tick time is less than the wake time. */
+                if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
+                {
+                    xShouldDelay = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+
+            /* Update the wake time ready for the next call. */
+            *pxPreviousWakeTime = xTimeToWake;
+
+            if( xShouldDelay != pdFALSE )
+            {
+                traceTASK_DELAY_UNTIL( xTimeToWake );
+
+                /* prvAddCurrentTaskToDelayedList() needs the block time, not
+                 * the time to wake, so subtract the current tick count. */
+                prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        xAlreadyYielded = xTaskResumeAll();
+
+        /* Force a reschedule if xTaskResumeAll has not already done so, we may
+         * have put ourselves to sleep. */
+        if( xAlreadyYielded == pdFALSE )
+        {
+            portYIELD_WITHIN_API();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        return xShouldDelay;
+    }
+
+#endif /* INCLUDE_xTaskDelayUntil */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+    void vTaskDelay( const TickType_t xTicksToDelay )
+    {
+        BaseType_t xAlreadyYielded = pdFALSE;
+
+        /* A delay time of zero just forces a reschedule. */
+        if( xTicksToDelay > ( TickType_t ) 0U )
+        {
+            configASSERT( uxSchedulerSuspended == 0 );
+            vTaskSuspendAll();
+            {
+                traceTASK_DELAY();
+
+                /* A task that is removed from the event list while the
+                 * scheduler is suspended will not get placed in the ready
+                 * list or removed from the blocked list until the scheduler
+                 * is resumed.
+                 *
+                 * This task cannot be in an event list as it is the currently
+                 * executing task. */
+                prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
+            }
+            xAlreadyYielded = xTaskResumeAll();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        /* Force a reschedule if xTaskResumeAll has not already done so, we may
+         * have put ourselves to sleep. */
+        if( xAlreadyYielded == pdFALSE )
+        {
+            portYIELD_WITHIN_API();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+#endif /* INCLUDE_vTaskDelay */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
+
+    eTaskState eTaskGetState( TaskHandle_t xTask )
+    {
+        eTaskState eReturn;
+        List_t const * pxStateList, * pxDelayedList, * pxOverflowedDelayedList;
+        const TCB_t * const pxTCB = xTask;
+
+        configASSERT( pxTCB );
+
+        if( pxTCB == pxCurrentTCB )
+        {
+            /* The task calling this function is querying its own state. */
+            eReturn = eRunning;
+        }
+        else
+        {
+            taskENTER_CRITICAL();
+            {
+                pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+                pxDelayedList = pxDelayedTaskList;
+                pxOverflowedDelayedList = pxOverflowDelayedTaskList;
+            }
+            taskEXIT_CRITICAL();
+
+            if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
+            {
+                /* The task being queried is referenced from one of the Blocked
+                 * lists. */
+                eReturn = eBlocked;
+            }
+
+            #if ( INCLUDE_vTaskSuspend == 1 )
+                else if( pxStateList == &xSuspendedTaskList )
+                {
+                    /* The task being queried is referenced from the suspended
+                     * list.  Is it genuinely suspended or is it blocked
+                     * indefinitely? */
+                    if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
+                    {
+                        #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+                            {
+                                BaseType_t x;
+
+                                /* The task does not appear on the event list item of
+                                 * and of the RTOS objects, but could still be in the
+                                 * blocked state if it is waiting on its notification
+                                 * rather than waiting on an object.  If not, is
+                                 * suspended. */
+                                eReturn = eSuspended;
+
+                                for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+                                {
+                                    if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
+                                    {
+                                        eReturn = eBlocked;
+                                        break;
+                                    }
+                                }
+                            }
+                        #else /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+                            {
+                                eReturn = eSuspended;
+                            }
+                        #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+                    }
+                    else
+                    {
+                        eReturn = eBlocked;
+                    }
+                }
+            #endif /* if ( INCLUDE_vTaskSuspend == 1 ) */
+
+            #if ( INCLUDE_vTaskDelete == 1 )
+                else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
+                {
+                    /* The task being queried is referenced from the deleted
+                     * tasks list, or it is not referenced from any lists at
+                     * all. */
+                    eReturn = eDeleted;
+                }
+            #endif
+
+            else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
+            {
+                /* If the task is not in any other state, it must be in the
+                 * Ready (including pending ready) state. */
+                eReturn = eReady;
+            }
+        }
+
+        return eReturn;
+    } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_eTaskGetState */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+    UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
+    {
+        TCB_t const * pxTCB;
+        UBaseType_t uxReturn;
+
+        taskENTER_CRITICAL();
+        {
+            /* If null is passed in here then it is the priority of the task
+             * that called uxTaskPriorityGet() that is being queried. */
+            pxTCB = prvGetTCBFromHandle( xTask );
+            uxReturn = pxTCB->uxPriority;
+        }
+        taskEXIT_CRITICAL();
+
+        return uxReturn;
+    }
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+    UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
+    {
+        TCB_t const * pxTCB;
+        UBaseType_t uxReturn, uxSavedInterruptState;
+
+        /* RTOS ports that support interrupt nesting have the concept of a
+         * maximum  system call (or maximum API call) interrupt priority.
+         * Interrupts that are  above the maximum system call priority are keep
+         * permanently enabled, even when the RTOS kernel is in a critical section,
+         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+         * is defined in FreeRTOSConfig.h then
+         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+         * failure if a FreeRTOS API function is called from an interrupt that has
+         * been assigned a priority above the configured maximum system call
+         * priority.  Only FreeRTOS functions that end in FromISR can be called
+         * from interrupts  that have been assigned a priority at or (logically)
+         * below the maximum system call interrupt priority.  FreeRTOS maintains a
+         * separate interrupt safe API to ensure interrupt entry is as fast and as
+         * simple as possible.  More information (albeit Cortex-M specific) is
+         * provided on the following link:
+         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+        uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
+        {
+            /* If null is passed in here then it is the priority of the calling
+             * task that is being queried. */
+            pxTCB = prvGetTCBFromHandle( xTask );
+            uxReturn = pxTCB->uxPriority;
+        }
+        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
+
+        return uxReturn;
+    }
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+
+    void vTaskPrioritySet( TaskHandle_t xTask,
+                           UBaseType_t uxNewPriority )
+    {
+        TCB_t * pxTCB;
+        UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
+        BaseType_t xYieldRequired = pdFALSE;
+
+        configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
+
+        /* Ensure the new priority is valid. */
+        if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+        {
+            uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        taskENTER_CRITICAL();
+        {
+            /* If null is passed in here then it is the priority of the calling
+             * task that is being changed. */
+            pxTCB = prvGetTCBFromHandle( xTask );
+
+            traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
+
+            #if ( configUSE_MUTEXES == 1 )
+                {
+                    uxCurrentBasePriority = pxTCB->uxBasePriority;
+                }
+            #else
+                {
+                    uxCurrentBasePriority = pxTCB->uxPriority;
+                }
+            #endif
+
+            if( uxCurrentBasePriority != uxNewPriority )
+            {
+                /* The priority change may have readied a task of higher
+                 * priority than the calling task. */
+                if( uxNewPriority > uxCurrentBasePriority )
+                {
+                    if( pxTCB != pxCurrentTCB )
+                    {
+                        /* The priority of a task other than the currently
+                         * running task is being raised.  Is the priority being
+                         * raised above that of the running task? */
+                        if( uxNewPriority >= pxCurrentTCB->uxPriority )
+                        {
+                            xYieldRequired = pdTRUE;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    else
+                    {
+                        /* The priority of the running task is being raised,
+                         * but the running task must already be the highest
+                         * priority task able to run so no yield is required. */
+                    }
+                }
+                else if( pxTCB == pxCurrentTCB )
+                {
+                    /* Setting the priority of the running task down means
+                     * there may now be another task of higher priority that
+                     * is ready to execute. */
+                    xYieldRequired = pdTRUE;
+                }
+                else
+                {
+                    /* Setting the priority of any other task down does not
+                     * require a yield as the running task must be above the
+                     * new priority of the task being modified. */
+                }
+
+                /* Remember the ready list the task might be referenced from
+                 * before its uxPriority member is changed so the
+                 * taskRESET_READY_PRIORITY() macro can function correctly. */
+                uxPriorityUsedOnEntry = pxTCB->uxPriority;
+
+                #if ( configUSE_MUTEXES == 1 )
+                    {
+                        /* Only change the priority being used if the task is not
+                         * currently using an inherited priority. */
+                        if( pxTCB->uxBasePriority == pxTCB->uxPriority )
+                        {
+                            pxTCB->uxPriority = uxNewPriority;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+
+                        /* The base priority gets set whatever. */
+                        pxTCB->uxBasePriority = uxNewPriority;
+                    }
+                #else /* if ( configUSE_MUTEXES == 1 ) */
+                    {
+                        pxTCB->uxPriority = uxNewPriority;
+                    }
+                #endif /* if ( configUSE_MUTEXES == 1 ) */
+
+                /* Only reset the event list item value if the value is not
+                 * being used for anything else. */
+                if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+                {
+                    listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                /* If the task is in the blocked or suspended list we need do
+                 * nothing more than change its priority variable. However, if
+                 * the task is in a ready list it needs to be removed and placed
+                 * in the list appropriate to its new priority. */
+                if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+                {
+                    /* The task is currently in its ready list - remove before
+                     * adding it to it's new ready list.  As we are in a critical
+                     * section we can do this even if the scheduler is suspended. */
+                    if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+                    {
+                        /* It is known that the task is in its ready list so
+                         * there is no need to check again and the port level
+                         * reset macro can be called directly. */
+                        portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    prvAddTaskToReadyList( pxTCB );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                if( xYieldRequired != pdFALSE )
+                {
+                    taskYIELD_IF_USING_PREEMPTION();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                /* Remove compiler warning about unused variables when the port
+                 * optimised task selection is not being used. */
+                ( void ) uxPriorityUsedOnEntry;
+            }
+        }
+        taskEXIT_CRITICAL();
+    }
+
+#endif /* INCLUDE_vTaskPrioritySet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+    void vTaskSuspend( TaskHandle_t xTaskToSuspend )
+    {
+        TCB_t * pxTCB;
+
+        taskENTER_CRITICAL();
+        {
+            /* If null is passed in here then it is the running task that is
+             * being suspended. */
+            pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
+
+            traceTASK_SUSPEND( pxTCB );
+
+            /* Remove task from the ready/delayed list and place in the
+             * suspended list. */
+            if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+            {
+                taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            /* Is the task waiting on an event also? */
+            if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+            {
+                ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
+
+            #if ( configUSE_TASK_NOTIFICATIONS == 1 )
+                {
+                    BaseType_t x;
+
+                    for( x = 0; x < configTASK_NOTIFICATION_ARRAY_ENTRIES; x++ )
+                    {
+                        if( pxTCB->ucNotifyState[ x ] == taskWAITING_NOTIFICATION )
+                        {
+                            /* The task was blocked to wait for a notification, but is
+                             * now suspended, so no notification was received. */
+                            pxTCB->ucNotifyState[ x ] = taskNOT_WAITING_NOTIFICATION;
+                        }
+                    }
+                }
+            #endif /* if ( configUSE_TASK_NOTIFICATIONS == 1 ) */
+        }
+        taskEXIT_CRITICAL();
+
+        if( xSchedulerRunning != pdFALSE )
+        {
+            /* Reset the next expected unblock time in case it referred to the
+             * task that is now in the Suspended state. */
+            taskENTER_CRITICAL();
+            {
+                prvResetNextTaskUnblockTime();
+            }
+            taskEXIT_CRITICAL();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        if( pxTCB == pxCurrentTCB )
+        {
+            if( xSchedulerRunning != pdFALSE )
+            {
+                /* The current task has just been suspended. */
+                configASSERT( uxSchedulerSuspended == 0 );
+                portYIELD_WITHIN_API();
+            }
+            else
+            {
+                /* The scheduler is not running, but the task that was pointed
+                 * to by pxCurrentTCB has just been suspended and pxCurrentTCB
+                 * must be adjusted to point to a different task. */
+                if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
+                {
+                    /* No other tasks are ready, so set pxCurrentTCB back to
+                     * NULL so when the next task is created pxCurrentTCB will
+                     * be set to point to it no matter what its relative priority
+                     * is. */
+                    pxCurrentTCB = NULL;
+                }
+                else
+                {
+                    vTaskSwitchContext();
+                }
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+    static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
+    {
+        BaseType_t xReturn = pdFALSE;
+        const TCB_t * const pxTCB = xTask;
+
+        /* Accesses xPendingReadyList so must be called from a critical
+         * section. */
+
+        /* It does not make sense to check if the calling task is suspended. */
+        configASSERT( xTask );
+
+        /* Is the task being resumed actually in the suspended list? */
+        if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
+        {
+            /* Has the task already been resumed from within an ISR? */
+            if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
+            {
+                /* Is it in the suspended list because it is in the Suspended
+                 * state, or because is is blocked with no timeout? */
+                if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
+                {
+                    xReturn = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        return xReturn;
+    } /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+    void vTaskResume( TaskHandle_t xTaskToResume )
+    {
+        TCB_t * const pxTCB = xTaskToResume;
+
+        /* It does not make sense to resume the calling task. */
+        configASSERT( xTaskToResume );
+
+        /* The parameter cannot be NULL as it is impossible to resume the
+         * currently executing task. */
+        if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
+        {
+            taskENTER_CRITICAL();
+            {
+                if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+                {
+                    traceTASK_RESUME( pxTCB );
+
+                    /* The ready list can be accessed even if the scheduler is
+                     * suspended because this is inside a critical section. */
+                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+                    prvAddTaskToReadyList( pxTCB );
+
+                    /* A higher priority task may have just been resumed. */
+                    if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+                    {
+                        /* This yield may not cause the task just resumed to run,
+                         * but will leave the lists in the correct state for the
+                         * next yield. */
+                        taskYIELD_IF_USING_PREEMPTION();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            taskEXIT_CRITICAL();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
+
+    BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
+    {
+        BaseType_t xYieldRequired = pdFALSE;
+        TCB_t * const pxTCB = xTaskToResume;
+        UBaseType_t uxSavedInterruptStatus;
+
+        configASSERT( xTaskToResume );
+
+        /* RTOS ports that support interrupt nesting have the concept of a
+         * maximum  system call (or maximum API call) interrupt priority.
+         * Interrupts that are  above the maximum system call priority are keep
+         * permanently enabled, even when the RTOS kernel is in a critical section,
+         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+         * is defined in FreeRTOSConfig.h then
+         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+         * failure if a FreeRTOS API function is called from an interrupt that has
+         * been assigned a priority above the configured maximum system call
+         * priority.  Only FreeRTOS functions that end in FromISR can be called
+         * from interrupts  that have been assigned a priority at or (logically)
+         * below the maximum system call interrupt priority.  FreeRTOS maintains a
+         * separate interrupt safe API to ensure interrupt entry is as fast and as
+         * simple as possible.  More information (albeit Cortex-M specific) is
+         * provided on the following link:
+         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+        {
+            if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+            {
+                traceTASK_RESUME_FROM_ISR( pxTCB );
+
+                /* Check the ready lists can be accessed. */
+                if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+                {
+                    /* Ready lists can be accessed so move the task from the
+                     * suspended list to the ready list directly. */
+                    if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+                    {
+                        xYieldRequired = pdTRUE;
+
+                        /* Mark that a yield is pending in case the user is not
+                         * using the return value to initiate a context switch
+                         * from the ISR using portYIELD_FROM_ISR. */
+                        xYieldPending = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+                    prvAddTaskToReadyList( pxTCB );
+                }
+                else
+                {
+                    /* The delayed or ready lists cannot be accessed so the task
+                     * is held in the pending ready list until the scheduler is
+                     * unsuspended. */
+                    vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+        return xYieldRequired;
+    }
+
+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+void vTaskStartScheduler( void )
+{
+    BaseType_t xReturn;
+
+    /* Add the idle task at the lowest priority. */
+    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+        {
+            StaticTask_t * pxIdleTaskTCBBuffer = NULL;
+            StackType_t * pxIdleTaskStackBuffer = NULL;
+            uint32_t ulIdleTaskStackSize;
+
+            /* The Idle task is created using user provided RAM - obtain the
+             * address of the RAM then create the idle task. */
+            vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+            xIdleTaskHandle = xTaskCreateStatic( prvIdleTask,
+                                                 configIDLE_TASK_NAME,
+                                                 ulIdleTaskStackSize,
+                                                 ( void * ) NULL,       /*lint !e961.  The cast is not redundant for all compilers. */
+                                                 portPRIVILEGE_BIT,     /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+                                                 pxIdleTaskStackBuffer,
+                                                 pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+
+            if( xIdleTaskHandle != NULL )
+            {
+                xReturn = pdPASS;
+            }
+            else
+            {
+                xReturn = pdFAIL;
+            }
+        }
+    #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+        {
+            /* The Idle task is being created using dynamically allocated RAM. */
+            xReturn = xTaskCreate( prvIdleTask,
+                                   configIDLE_TASK_NAME,
+                                   configMINIMAL_STACK_SIZE,
+                                   ( void * ) NULL,
+                                   portPRIVILEGE_BIT,  /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
+                                   &xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+        }
+    #endif /* configSUPPORT_STATIC_ALLOCATION */
+
+    #if ( configUSE_TIMERS == 1 )
+        {
+            if( xReturn == pdPASS )
+            {
+                xReturn = xTimerCreateTimerTask();
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+    #endif /* configUSE_TIMERS */
+
+    if( xReturn == pdPASS )
+    {
+        /* freertos_tasks_c_additions_init() should only be called if the user
+         * definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
+         * the only macro called by the function. */
+        #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+            {
+                freertos_tasks_c_additions_init();
+            }
+        #endif
+
+        /* Interrupts are turned off here, to ensure a tick does not occur
+         * before or during the call to xPortStartScheduler().  The stacks of
+         * the created tasks contain a status word with interrupts switched on
+         * so interrupts will automatically get re-enabled when the first task
+         * starts to run. */
+        portDISABLE_INTERRUPTS();
+
+        #if ( configUSE_NEWLIB_REENTRANT == 1 )
+            {
+                /* Switch Newlib's _impure_ptr variable to point to the _reent
+                 * structure specific to the task that will run first.
+                 * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+                 * for additional information. */
+                _impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+            }
+        #endif /* configUSE_NEWLIB_REENTRANT */
+
+        xNextTaskUnblockTime = portMAX_DELAY;
+        xSchedulerRunning = pdTRUE;
+        xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
+
+        /* If configGENERATE_RUN_TIME_STATS is defined then the following
+         * macro must be defined to configure the timer/counter used to generate
+         * the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS
+         * is set to 0 and the following line fails to build then ensure you do not
+         * have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
+         * FreeRTOSConfig.h file. */
+        portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
+
+        traceTASK_SWITCHED_IN();
+
+        /* Setting up the timer tick is hardware specific and thus in the
+         * portable interface. */
+        if( xPortStartScheduler() != pdFALSE )
+        {
+            /* Should not reach here as if the scheduler is running the
+             * function will not return. */
+        }
+        else
+        {
+            /* Should only reach here if a task calls xTaskEndScheduler(). */
+        }
+    }
+    else
+    {
+        /* This line will only be reached if the kernel could not be started,
+         * because there was not enough FreeRTOS heap to create the idle task
+         * or the timer task. */
+        configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
+    }
+
+    /* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
+     * meaning xIdleTaskHandle is not used anywhere else. */
+    ( void ) xIdleTaskHandle;
+
+    /* OpenOCD makes use of uxTopUsedPriority for thread debugging. Prevent uxTopUsedPriority
+     * from getting optimized out as it is no longer used by the kernel. */
+    ( void ) uxTopUsedPriority;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskEndScheduler( void )
+{
+    /* Stop the scheduler interrupts and call the portable scheduler end
+     * routine so the original ISRs can be restored if necessary.  The port
+     * layer must ensure interrupts enable  bit is left in the correct state. */
+    portDISABLE_INTERRUPTS();
+    xSchedulerRunning = pdFALSE;
+    vPortEndScheduler();
+}
+/*----------------------------------------------------------*/
+
+void vTaskSuspendAll( void )
+{
+    /* A critical section is not required as the variable is of type
+     * BaseType_t.  Please read Richard Barry's reply in the following link to a
+     * post in the FreeRTOS support forum before reporting this as a bug! -
+     * https://goo.gl/wu4acr */
+
+    /* portSOFRWARE_BARRIER() is only implemented for emulated/simulated ports that
+     * do not otherwise exhibit real time behaviour. */
+    portSOFTWARE_BARRIER();
+
+    /* The scheduler is suspended if uxSchedulerSuspended is non-zero.  An increment
+     * is used to allow calls to vTaskSuspendAll() to nest. */
+    ++uxSchedulerSuspended;
+
+    /* Enforces ordering for ports and optimised compilers that may otherwise place
+     * the above increment elsewhere. */
+    portMEMORY_BARRIER();
+}
+/*----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+    static TickType_t prvGetExpectedIdleTime( void )
+    {
+        TickType_t xReturn;
+        UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
+
+        /* uxHigherPriorityReadyTasks takes care of the case where
+         * configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
+         * task that are in the Ready state, even though the idle task is
+         * running. */
+        #if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+            {
+                if( uxTopReadyPriority > tskIDLE_PRIORITY )
+                {
+                    uxHigherPriorityReadyTasks = pdTRUE;
+                }
+            }
+        #else
+            {
+                const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
+
+                /* When port optimised task selection is used the uxTopReadyPriority
+                 * variable is used as a bit map.  If bits other than the least
+                 * significant bit are set then there are tasks that have a priority
+                 * above the idle priority that are in the Ready state.  This takes
+                 * care of the case where the co-operative scheduler is in use. */
+                if( uxTopReadyPriority > uxLeastSignificantBit )
+                {
+                    uxHigherPriorityReadyTasks = pdTRUE;
+                }
+            }
+        #endif /* if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 ) */
+
+        if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
+        {
+            xReturn = 0;
+        }
+        else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
+        {
+            /* There are other idle priority tasks in the ready state.  If
+             * time slicing is used then the very next tick interrupt must be
+             * processed. */
+            xReturn = 0;
+        }
+        else if( uxHigherPriorityReadyTasks != pdFALSE )
+        {
+            /* There are tasks in the Ready state that have a priority above the
+             * idle priority.  This path can only be reached if
+             * configUSE_PREEMPTION is 0. */
+            xReturn = 0;
+        }
+        else
+        {
+            xReturn = xNextTaskUnblockTime - xTickCount;
+        }
+
+        return xReturn;
+    }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskResumeAll( void )
+{
+    TCB_t * pxTCB = NULL;
+    BaseType_t xAlreadyYielded = pdFALSE;
+
+    /* If uxSchedulerSuspended is zero then this function does not match a
+     * previous call to vTaskSuspendAll(). */
+    configASSERT( uxSchedulerSuspended );
+
+    /* It is possible that an ISR caused a task to be removed from an event
+     * list while the scheduler was suspended.  If this was the case then the
+     * removed task will have been added to the xPendingReadyList.  Once the
+     * scheduler has been resumed it is safe to move all the pending ready
+     * tasks from this list into their appropriate ready list. */
+    taskENTER_CRITICAL();
+    {
+        --uxSchedulerSuspended;
+
+        if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+        {
+            if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+            {
+                /* Move any readied tasks from the pending list into the
+                 * appropriate ready list. */
+                while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+                {
+                    pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+                    ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+                    prvAddTaskToReadyList( pxTCB );
+
+                    /* If the moved task has a priority higher than the current
+                     * task then a yield must be performed. */
+                    if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+                    {
+                        xYieldPending = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+
+                if( pxTCB != NULL )
+                {
+                    /* A task was unblocked while the scheduler was suspended,
+                     * which may have prevented the next unblock time from being
+                     * re-calculated, in which case re-calculate it now.  Mainly
+                     * important for low power tickless implementations, where
+                     * this can prevent an unnecessary exit from low power
+                     * state. */
+                    prvResetNextTaskUnblockTime();
+                }
+
+                /* If any ticks occurred while the scheduler was suspended then
+                 * they should be processed now.  This ensures the tick count does
+                 * not  slip, and that any delayed tasks are resumed at the correct
+                 * time. */
+                {
+                    TickType_t xPendedCounts = xPendedTicks; /* Non-volatile copy. */
+
+                    if( xPendedCounts > ( TickType_t ) 0U )
+                    {
+                        do
+                        {
+                            if( xTaskIncrementTick() != pdFALSE )
+                            {
+                                xYieldPending = pdTRUE;
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+
+                            --xPendedCounts;
+                        } while( xPendedCounts > ( TickType_t ) 0U );
+
+                        xPendedTicks = 0;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+
+                if( xYieldPending != pdFALSE )
+                {
+                    #if ( configUSE_PREEMPTION != 0 )
+                        {
+                            xAlreadyYielded = pdTRUE;
+                        }
+                    #endif
+                    taskYIELD_IF_USING_PREEMPTION();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+    taskEXIT_CRITICAL();
+
+    return xAlreadyYielded;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCount( void )
+{
+    TickType_t xTicks;
+
+    /* Critical section required if running on a 16 bit processor. */
+    portTICK_TYPE_ENTER_CRITICAL();
+    {
+        xTicks = xTickCount;
+    }
+    portTICK_TYPE_EXIT_CRITICAL();
+
+    return xTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCountFromISR( void )
+{
+    TickType_t xReturn;
+    UBaseType_t uxSavedInterruptStatus;
+
+    /* RTOS ports that support interrupt nesting have the concept of a maximum
+     * system call (or maximum API call) interrupt priority.  Interrupts that are
+     * above the maximum system call priority are kept permanently enabled, even
+     * when the RTOS kernel is in a critical section, but cannot make any calls to
+     * FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+     * then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+     * failure if a FreeRTOS API function is called from an interrupt that has been
+     * assigned a priority above the configured maximum system call priority.
+     * Only FreeRTOS functions that end in FromISR can be called from interrupts
+     * that have been assigned a priority at or (logically) below the maximum
+     * system call  interrupt priority.  FreeRTOS maintains a separate interrupt
+     * safe API to ensure interrupt entry is as fast and as simple as possible.
+     * More information (albeit Cortex-M specific) is provided on the following
+     * link: https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+    portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+    uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
+    {
+        xReturn = xTickCount;
+    }
+    portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTaskGetNumberOfTasks( void )
+{
+    /* A critical section is not required because the variables are of type
+     * BaseType_t. */
+    return uxCurrentNumberOfTasks;
+}
+/*-----------------------------------------------------------*/
+
+char * pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+    TCB_t * pxTCB;
+
+    /* If null is passed in here then the name of the calling task is being
+     * queried. */
+    pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+    configASSERT( pxTCB );
+    return &( pxTCB->pcTaskName[ 0 ] );
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+    static TCB_t * prvSearchForNameWithinSingleList( List_t * pxList,
+                                                     const char pcNameToQuery[] )
+    {
+        TCB_t * pxNextTCB, * pxFirstTCB, * pxReturn = NULL;
+        UBaseType_t x;
+        char cNextChar;
+        BaseType_t xBreakLoop;
+
+        /* This function is called with the scheduler suspended. */
+
+        if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+        {
+            listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+            do
+            {
+                listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+                /* Check each character in the name looking for a match or
+                 * mismatch. */
+                xBreakLoop = pdFALSE;
+
+                for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+                {
+                    cNextChar = pxNextTCB->pcTaskName[ x ];
+
+                    if( cNextChar != pcNameToQuery[ x ] )
+                    {
+                        /* Characters didn't match. */
+                        xBreakLoop = pdTRUE;
+                    }
+                    else if( cNextChar == ( char ) 0x00 )
+                    {
+                        /* Both strings terminated, a match must have been
+                         * found. */
+                        pxReturn = pxNextTCB;
+                        xBreakLoop = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    if( xBreakLoop != pdFALSE )
+                    {
+                        break;
+                    }
+                }
+
+                if( pxReturn != NULL )
+                {
+                    /* The handle has been found. */
+                    break;
+                }
+            } while( pxNextTCB != pxFirstTCB );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        return pxReturn;
+    }
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+    TaskHandle_t xTaskGetHandle( const char * pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    {
+        UBaseType_t uxQueue = configMAX_PRIORITIES;
+        TCB_t * pxTCB;
+
+        /* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
+        configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
+
+        vTaskSuspendAll();
+        {
+            /* Search the ready lists. */
+            do
+            {
+                uxQueue--;
+                pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );
+
+                if( pxTCB != NULL )
+                {
+                    /* Found the handle. */
+                    break;
+                }
+            } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+            /* Search the delayed lists. */
+            if( pxTCB == NULL )
+            {
+                pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
+            }
+
+            if( pxTCB == NULL )
+            {
+                pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
+            }
+
+            #if ( INCLUDE_vTaskSuspend == 1 )
+                {
+                    if( pxTCB == NULL )
+                    {
+                        /* Search the suspended list. */
+                        pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
+                    }
+                }
+            #endif
+
+            #if ( INCLUDE_vTaskDelete == 1 )
+                {
+                    if( pxTCB == NULL )
+                    {
+                        /* Search the deleted list. */
+                        pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
+                    }
+                }
+            #endif
+        }
+        ( void ) xTaskResumeAll();
+
+        return pxTCB;
+    }
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray,
+                                      const UBaseType_t uxArraySize,
+                                      uint32_t * const pulTotalRunTime )
+    {
+        UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
+
+        vTaskSuspendAll();
+        {
+            /* Is there a space in the array for each task in the system? */
+            if( uxArraySize >= uxCurrentNumberOfTasks )
+            {
+                /* Fill in an TaskStatus_t structure with information on each
+                 * task in the Ready state. */
+                do
+                {
+                    uxQueue--;
+                    uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
+                } while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+                /* Fill in an TaskStatus_t structure with information on each
+                 * task in the Blocked state. */
+                uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
+                uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
+
+                #if ( INCLUDE_vTaskDelete == 1 )
+                    {
+                        /* Fill in an TaskStatus_t structure with information on
+                         * each task that has been deleted but not yet cleaned up. */
+                        uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
+                    }
+                #endif
+
+                #if ( INCLUDE_vTaskSuspend == 1 )
+                    {
+                        /* Fill in an TaskStatus_t structure with information on
+                         * each task in the Suspended state. */
+                        uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
+                    }
+                #endif
+
+                #if ( configGENERATE_RUN_TIME_STATS == 1 )
+                    {
+                        if( pulTotalRunTime != NULL )
+                        {
+                            #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+                                portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
+                            #else
+                                *pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+                            #endif
+                        }
+                    }
+                #else /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
+                    {
+                        if( pulTotalRunTime != NULL )
+                        {
+                            *pulTotalRunTime = 0;
+                        }
+                    }
+                #endif /* if ( configGENERATE_RUN_TIME_STATS == 1 ) */
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        ( void ) xTaskResumeAll();
+
+        return uxTask;
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+    TaskHandle_t xTaskGetIdleTaskHandle( void )
+    {
+        /* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+         * started, then xIdleTaskHandle will be NULL. */
+        configASSERT( ( xIdleTaskHandle != NULL ) );
+        return xIdleTaskHandle;
+    }
+
+#endif /* INCLUDE_xTaskGetIdleTaskHandle */
+/*----------------------------------------------------------*/
+
+/* This conditional compilation should use inequality to 0, not equality to 1.
+ * This is to ensure vTaskStepTick() is available when user defined low power mode
+ * implementations require configUSE_TICKLESS_IDLE to be set to a value other than
+ * 1. */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+    void vTaskStepTick( const TickType_t xTicksToJump )
+    {
+        /* Correct the tick count value after a period during which the tick
+         * was suppressed.  Note this does *not* call the tick hook function for
+         * each stepped tick. */
+        configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+        xTickCount += xTicksToJump;
+        traceINCREASE_TICK_COUNT( xTicksToJump );
+    }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskCatchUpTicks( TickType_t xTicksToCatchUp )
+{
+    BaseType_t xYieldOccurred;
+
+    /* Must not be called with the scheduler suspended as the implementation
+     * relies on xPendedTicks being wound down to 0 in xTaskResumeAll(). */
+    configASSERT( uxSchedulerSuspended == 0 );
+
+    /* Use xPendedTicks to mimic xTicksToCatchUp number of ticks occurring when
+     * the scheduler is suspended so the ticks are executed in xTaskResumeAll(). */
+    vTaskSuspendAll();
+    xPendedTicks += xTicksToCatchUp;
+    xYieldOccurred = xTaskResumeAll();
+
+    return xYieldOccurred;
+}
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+
+    BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
+    {
+        TCB_t * pxTCB = xTask;
+        BaseType_t xReturn;
+
+        configASSERT( pxTCB );
+
+        vTaskSuspendAll();
+        {
+            /* A task can only be prematurely removed from the Blocked state if
+             * it is actually in the Blocked state. */
+            if( eTaskGetState( xTask ) == eBlocked )
+            {
+                xReturn = pdPASS;
+
+                /* Remove the reference to the task from the blocked list.  An
+                 * interrupt won't touch the xStateListItem because the
+                 * scheduler is suspended. */
+                ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+                /* Is the task waiting on an event also?  If so remove it from
+                 * the event list too.  Interrupts can touch the event list item,
+                 * even though the scheduler is suspended, so a critical section
+                 * is used. */
+                taskENTER_CRITICAL();
+                {
+                    if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+                    {
+                        ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+
+                        /* This lets the task know it was forcibly removed from the
+                         * blocked state so it should not re-evaluate its block time and
+                         * then block again. */
+                        pxTCB->ucDelayAborted = pdTRUE;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                taskEXIT_CRITICAL();
+
+                /* Place the unblocked task into the appropriate ready list. */
+                prvAddTaskToReadyList( pxTCB );
+
+                /* A task being unblocked cannot cause an immediate context
+                 * switch if preemption is turned off. */
+                #if ( configUSE_PREEMPTION == 1 )
+                    {
+                        /* Preemption is on, but a context switch should only be
+                         *  performed if the unblocked task has a priority that is
+                         *  equal to or higher than the currently executing task. */
+                        if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                        {
+                            /* Pend the yield to be performed when the scheduler
+                             * is unsuspended. */
+                            xYieldPending = pdTRUE;
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                #endif /* configUSE_PREEMPTION */
+            }
+            else
+            {
+                xReturn = pdFAIL;
+            }
+        }
+        ( void ) xTaskResumeAll();
+
+        return xReturn;
+    }
+
+#endif /* INCLUDE_xTaskAbortDelay */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskIncrementTick( void )
+{
+    TCB_t * pxTCB;
+    TickType_t xItemValue;
+    BaseType_t xSwitchRequired = pdFALSE;
+
+    /* Called by the portable layer each time a tick interrupt occurs.
+     * Increments the tick then checks to see if the new tick value will cause any
+     * tasks to be unblocked. */
+    traceTASK_INCREMENT_TICK( xTickCount );
+
+    if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+    {
+        /* Minor optimisation.  The tick count cannot change in this
+         * block. */
+        const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
+
+        /* Increment the RTOS tick, switching the delayed and overflowed
+         * delayed lists if it wraps to 0. */
+        xTickCount = xConstTickCount;
+
+        if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
+        {
+            taskSWITCH_DELAYED_LISTS();
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        /* See if this tick has made a timeout expire.  Tasks are stored in
+         * the  queue in the order of their wake time - meaning once one task
+         * has been found whose block time has not expired there is no need to
+         * look any further down the list. */
+        if( xConstTickCount >= xNextTaskUnblockTime )
+        {
+            for( ; ; )
+            {
+                if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+                {
+                    /* The delayed list is empty.  Set xNextTaskUnblockTime
+                     * to the maximum possible value so it is extremely
+                     * unlikely that the
+                     * if( xTickCount >= xNextTaskUnblockTime ) test will pass
+                     * next time through. */
+                    xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+                    break;
+                }
+                else
+                {
+                    /* The delayed list is not empty, get the value of the
+                     * item at the head of the delayed list.  This is the time
+                     * at which the task at the head of the delayed list must
+                     * be removed from the Blocked state. */
+                    pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+                    xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
+
+                    if( xConstTickCount < xItemValue )
+                    {
+                        /* It is not time to unblock this item yet, but the
+                         * item value is the time at which the task at the head
+                         * of the blocked list must be removed from the Blocked
+                         * state -  so record the item value in
+                         * xNextTaskUnblockTime. */
+                        xNextTaskUnblockTime = xItemValue;
+                        break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    /* It is time to remove the item from the Blocked state. */
+                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+                    /* Is the task waiting on an event also?  If so remove
+                     * it from the event list. */
+                    if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+                    {
+                        ( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    /* Place the unblocked task into the appropriate ready
+                     * list. */
+                    prvAddTaskToReadyList( pxTCB );
+
+                    /* A task being unblocked cannot cause an immediate
+                     * context switch if preemption is turned off. */
+                    #if ( configUSE_PREEMPTION == 1 )
+                        {
+                            /* Preemption is on, but a context switch should
+                             * only be performed if the unblocked task has a
+                             * priority that is equal to or higher than the
+                             * currently executing task. */
+                            if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+                            {
+                                xSwitchRequired = pdTRUE;
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                    #endif /* configUSE_PREEMPTION */
+                }
+            }
+        }
+
+        /* Tasks of equal priority to the currently running task will share
+         * processing time (time slice) if preemption is on, and the application
+         * writer has not explicitly turned time slicing off. */
+        #if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+            {
+                if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+                {
+                    xSwitchRequired = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
+
+        #if ( configUSE_TICK_HOOK == 1 )
+            {
+                /* Guard against the tick hook being called when the pended tick
+                 * count is being unwound (when the scheduler is being unlocked). */
+                if( xPendedTicks == ( TickType_t ) 0 )
+                {
+                    vApplicationTickHook();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        #endif /* configUSE_TICK_HOOK */
+
+        #if ( configUSE_PREEMPTION == 1 )
+            {
+                if( xYieldPending != pdFALSE )
+                {
+                    xSwitchRequired = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        #endif /* configUSE_PREEMPTION */
+    }
+    else
+    {
+        ++xPendedTicks;
+
+        /* The tick hook gets called at regular intervals, even if the
+         * scheduler is locked. */
+        #if ( configUSE_TICK_HOOK == 1 )
+            {
+                vApplicationTickHook();
+            }
+        #endif
+    }
+
+    return xSwitchRequired;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+    void vTaskSetApplicationTaskTag( TaskHandle_t xTask,
+                                     TaskHookFunction_t pxHookFunction )
+    {
+        TCB_t * xTCB;
+
+        /* If xTask is NULL then it is the task hook of the calling task that is
+         * getting set. */
+        if( xTask == NULL )
+        {
+            xTCB = ( TCB_t * ) pxCurrentTCB;
+        }
+        else
+        {
+            xTCB = xTask;
+        }
+
+        /* Save the hook function in the TCB.  A critical section is required as
+         * the value can be accessed from an interrupt. */
+        taskENTER_CRITICAL();
+        {
+            xTCB->pxTaskTag = pxHookFunction;
+        }
+        taskEXIT_CRITICAL();
+    }
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+    TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
+    {
+        TCB_t * pxTCB;
+        TaskHookFunction_t xReturn;
+
+        /* If xTask is NULL then set the calling task's hook. */
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        /* Save the hook function in the TCB.  A critical section is required as
+         * the value can be accessed from an interrupt. */
+        taskENTER_CRITICAL();
+        {
+            xReturn = pxTCB->pxTaskTag;
+        }
+        taskEXIT_CRITICAL();
+
+        return xReturn;
+    }
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+    TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )
+    {
+        TCB_t * pxTCB;
+        TaskHookFunction_t xReturn;
+        UBaseType_t uxSavedInterruptStatus;
+
+        /* If xTask is NULL then set the calling task's hook. */
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        /* Save the hook function in the TCB.  A critical section is required as
+         * the value can be accessed from an interrupt. */
+        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+        {
+            xReturn = pxTCB->pxTaskTag;
+        }
+        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+    BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask,
+                                             void * pvParameter )
+    {
+        TCB_t * xTCB;
+        BaseType_t xReturn;
+
+        /* If xTask is NULL then we are calling our own task hook. */
+        if( xTask == NULL )
+        {
+            xTCB = pxCurrentTCB;
+        }
+        else
+        {
+            xTCB = xTask;
+        }
+
+        if( xTCB->pxTaskTag != NULL )
+        {
+            xReturn = xTCB->pxTaskTag( pvParameter );
+        }
+        else
+        {
+            xReturn = pdFAIL;
+        }
+
+        return xReturn;
+    }
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+void vTaskSwitchContext( void )
+{
+    if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
+    {
+        /* The scheduler is currently suspended - do not allow a context
+         * switch. */
+        xYieldPending = pdTRUE;
+    }
+    else
+    {
+        xYieldPending = pdFALSE;
+        traceTASK_SWITCHED_OUT();
+
+        #if ( configGENERATE_RUN_TIME_STATS == 1 )
+            {
+                #ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+                    portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
+                #else
+                    ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+                #endif
+
+                /* Add the amount of time the task has been running to the
+                 * accumulated time so far.  The time the task started running was
+                 * stored in ulTaskSwitchedInTime.  Note that there is no overflow
+                 * protection here so count values are only valid until the timer
+                 * overflows.  The guard against negative values is to protect
+                 * against suspect run time stat counter implementations - which
+                 * are provided by the application, not the kernel. */
+                if( ulTotalRunTime > ulTaskSwitchedInTime )
+                {
+                    pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                ulTaskSwitchedInTime = ulTotalRunTime;
+            }
+        #endif /* configGENERATE_RUN_TIME_STATS */
+
+        /* Check for stack overflow, if configured. */
+        taskCHECK_FOR_STACK_OVERFLOW();
+
+        /* Before the currently running task is switched out, save its errno. */
+        #if ( configUSE_POSIX_ERRNO == 1 )
+            {
+                pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
+            }
+        #endif
+
+        /* Select a new task to run using either the generic C or port
+         * optimised asm code. */
+        taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+        traceTASK_SWITCHED_IN();
+
+        /* After the new task is switched in, update the global errno. */
+        #if ( configUSE_POSIX_ERRNO == 1 )
+            {
+                FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
+            }
+        #endif
+
+        #if ( configUSE_NEWLIB_REENTRANT == 1 )
+            {
+                /* Switch Newlib's _impure_ptr variable to point to the _reent
+                 * structure specific to this task.
+                 * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+                 * for additional information. */
+                _impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+            }
+        #endif /* configUSE_NEWLIB_REENTRANT */
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnEventList( List_t * const pxEventList,
+                            const TickType_t xTicksToWait )
+{
+    configASSERT( pxEventList );
+
+    /* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
+     * SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
+
+    /* Place the event list item of the TCB in the appropriate event list.
+     * This is placed in the list in priority order so the highest priority task
+     * is the first to be woken by the event.  The queue that contains the event
+     * list is locked, preventing simultaneous access from interrupts. */
+    vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList,
+                                     const TickType_t xItemValue,
+                                     const TickType_t xTicksToWait )
+{
+    configASSERT( pxEventList );
+
+    /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+     * the event groups implementation. */
+    configASSERT( uxSchedulerSuspended != 0 );
+
+    /* Store the item value in the event list item.  It is safe to access the
+     * event list item here as interrupts won't access the event list item of a
+     * task that is not in the Blocked state. */
+    listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+    /* Place the event list item of the TCB at the end of the appropriate event
+     * list.  It is safe to access the event list here because it is part of an
+     * event group implementation - and interrupts don't access event groups
+     * directly (instead they access them indirectly by pending function calls to
+     * the task level). */
+    vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+    void vTaskPlaceOnEventListRestricted( List_t * const pxEventList,
+                                          TickType_t xTicksToWait,
+                                          const BaseType_t xWaitIndefinitely )
+    {
+        configASSERT( pxEventList );
+
+        /* This function should not be called by application code hence the
+         * 'Restricted' in its name.  It is not part of the public API.  It is
+         * designed for use by kernel code, and has special calling requirements -
+         * it should be called with the scheduler suspended. */
+
+
+        /* Place the event list item of the TCB in the appropriate event list.
+         * In this case it is assume that this is the only task that is going to
+         * be waiting on this event list, so the faster vListInsertEnd() function
+         * can be used in place of vListInsert. */
+        vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+        /* If the task should block indefinitely then set the block time to a
+         * value that will be recognised as an indefinite delay inside the
+         * prvAddCurrentTaskToDelayedList() function. */
+        if( xWaitIndefinitely != pdFALSE )
+        {
+            xTicksToWait = portMAX_DELAY;
+        }
+
+        traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
+        prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+    }
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
+{
+    TCB_t * pxUnblockedTCB;
+    BaseType_t xReturn;
+
+    /* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
+     * called from a critical section within an ISR. */
+
+    /* The event list is sorted in priority order, so the first in the list can
+     * be removed as it is known to be the highest priority.  Remove the TCB from
+     * the delayed list, and add it to the ready list.
+     *
+     * If an event is for a queue that is locked then this function will never
+     * get called - the lock count on the queue will get modified instead.  This
+     * means exclusive access to the event list is guaranteed here.
+     *
+     * This function assumes that a check has already been made to ensure that
+     * pxEventList is not empty. */
+    pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+    configASSERT( pxUnblockedTCB );
+    ( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
+
+    if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+    {
+        ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+        prvAddTaskToReadyList( pxUnblockedTCB );
+
+        #if ( configUSE_TICKLESS_IDLE != 0 )
+            {
+                /* If a task is blocked on a kernel object then xNextTaskUnblockTime
+                 * might be set to the blocked task's time out time.  If the task is
+                 * unblocked for a reason other than a timeout xNextTaskUnblockTime is
+                 * normally left unchanged, because it is automatically reset to a new
+                 * value when the tick count equals xNextTaskUnblockTime.  However if
+                 * tickless idling is used it might be more important to enter sleep mode
+                 * at the earliest possible time - so reset xNextTaskUnblockTime here to
+                 * ensure it is updated at the earliest possible time. */
+                prvResetNextTaskUnblockTime();
+            }
+        #endif
+    }
+    else
+    {
+        /* The delayed and ready lists cannot be accessed, so hold this task
+         * pending until the scheduler is resumed. */
+        vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
+    }
+
+    if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+    {
+        /* Return true if the task removed from the event list has a higher
+         * priority than the calling task.  This allows the calling task to know if
+         * it should force a context switch now. */
+        xReturn = pdTRUE;
+
+        /* Mark that a yield is pending in case the user is not using the
+         * "xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+        xYieldPending = pdTRUE;
+    }
+    else
+    {
+        xReturn = pdFALSE;
+    }
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem,
+                                        const TickType_t xItemValue )
+{
+    TCB_t * pxUnblockedTCB;
+
+    /* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+     * the event flags implementation. */
+    configASSERT( uxSchedulerSuspended != pdFALSE );
+
+    /* Store the new item value in the event list. */
+    listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+    /* Remove the event list form the event flag.  Interrupts do not access
+     * event flags. */
+    pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+    configASSERT( pxUnblockedTCB );
+    ( void ) uxListRemove( pxEventListItem );
+
+    #if ( configUSE_TICKLESS_IDLE != 0 )
+        {
+            /* If a task is blocked on a kernel object then xNextTaskUnblockTime
+             * might be set to the blocked task's time out time.  If the task is
+             * unblocked for a reason other than a timeout xNextTaskUnblockTime is
+             * normally left unchanged, because it is automatically reset to a new
+             * value when the tick count equals xNextTaskUnblockTime.  However if
+             * tickless idling is used it might be more important to enter sleep mode
+             * at the earliest possible time - so reset xNextTaskUnblockTime here to
+             * ensure it is updated at the earliest possible time. */
+            prvResetNextTaskUnblockTime();
+        }
+    #endif
+
+    /* Remove the task from the delayed list and add it to the ready list.  The
+     * scheduler is suspended so interrupts will not be accessing the ready
+     * lists. */
+    ( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+    prvAddTaskToReadyList( pxUnblockedTCB );
+
+    if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+    {
+        /* The unblocked task has a priority above that of the calling task, so
+         * a context switch is required.  This function is called with the
+         * scheduler suspended so xYieldPending is set so the context switch
+         * occurs immediately that the scheduler is resumed (unsuspended). */
+        xYieldPending = pdTRUE;
+    }
+}
+/*-----------------------------------------------------------*/
+
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+    configASSERT( pxTimeOut );
+    taskENTER_CRITICAL();
+    {
+        pxTimeOut->xOverflowCount = xNumOfOverflows;
+        pxTimeOut->xTimeOnEntering = xTickCount;
+    }
+    taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+    /* For internal use only as it does not use a critical section. */
+    pxTimeOut->xOverflowCount = xNumOfOverflows;
+    pxTimeOut->xTimeOnEntering = xTickCount;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut,
+                                 TickType_t * const pxTicksToWait )
+{
+    BaseType_t xReturn;
+
+    configASSERT( pxTimeOut );
+    configASSERT( pxTicksToWait );
+
+    taskENTER_CRITICAL();
+    {
+        /* Minor optimisation.  The tick count cannot change in this block. */
+        const TickType_t xConstTickCount = xTickCount;
+        const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
+
+        #if ( INCLUDE_xTaskAbortDelay == 1 )
+            if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
+            {
+                /* The delay was aborted, which is not the same as a time out,
+                 * but has the same result. */
+                pxCurrentTCB->ucDelayAborted = pdFALSE;
+                xReturn = pdTRUE;
+            }
+            else
+        #endif
+
+        #if ( INCLUDE_vTaskSuspend == 1 )
+            if( *pxTicksToWait == portMAX_DELAY )
+            {
+                /* If INCLUDE_vTaskSuspend is set to 1 and the block time
+                 * specified is the maximum block time then the task should block
+                 * indefinitely, and therefore never time out. */
+                xReturn = pdFALSE;
+            }
+            else
+        #endif
+
+        if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+        {
+            /* The tick count is greater than the time at which
+             * vTaskSetTimeout() was called, but has also overflowed since
+             * vTaskSetTimeOut() was called.  It must have wrapped all the way
+             * around and gone past again. This passed since vTaskSetTimeout()
+             * was called. */
+            xReturn = pdTRUE;
+            *pxTicksToWait = ( TickType_t ) 0;
+        }
+        else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+        {
+            /* Not a genuine timeout. Adjust parameters for time remaining. */
+            *pxTicksToWait -= xElapsedTime;
+            vTaskInternalSetTimeOutState( pxTimeOut );
+            xReturn = pdFALSE;
+        }
+        else
+        {
+            *pxTicksToWait = ( TickType_t ) 0;
+            xReturn = pdTRUE;
+        }
+    }
+    taskEXIT_CRITICAL();
+
+    return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskMissedYield( void )
+{
+    xYieldPending = pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
+    {
+        UBaseType_t uxReturn;
+        TCB_t const * pxTCB;
+
+        if( xTask != NULL )
+        {
+            pxTCB = xTask;
+            uxReturn = pxTCB->uxTaskNumber;
+        }
+        else
+        {
+            uxReturn = 0U;
+        }
+
+        return uxReturn;
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    void vTaskSetTaskNumber( TaskHandle_t xTask,
+                             const UBaseType_t uxHandle )
+    {
+        TCB_t * pxTCB;
+
+        if( xTask != NULL )
+        {
+            pxTCB = xTask;
+            pxTCB->uxTaskNumber = uxHandle;
+        }
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+
+/*
+ * -----------------------------------------------------------
+ * The Idle task.
+ * ----------------------------------------------------------
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION( prvIdleTask, pvParameters )
+{
+    /* Stop warnings. */
+    ( void ) pvParameters;
+
+    /** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
+     * SCHEDULER IS STARTED. **/
+
+    /* In case a task that has a secure context deletes itself, in which case
+     * the idle task is responsible for deleting the task's secure context, if
+     * any. */
+    portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
+
+    for( ; ; )
+    {
+        /* See if any tasks have deleted themselves - if so then the idle task
+         * is responsible for freeing the deleted task's TCB and stack. */
+        prvCheckTasksWaitingTermination();
+
+        #if ( configUSE_PREEMPTION == 0 )
+            {
+                /* If we are not using preemption we keep forcing a task switch to
+                 * see if any other task has become available.  If we are using
+                 * preemption we don't need to do this as any task becoming available
+                 * will automatically get the processor anyway. */
+                taskYIELD();
+            }
+        #endif /* configUSE_PREEMPTION */
+
+        #if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+            {
+                /* When using preemption tasks of equal priority will be
+                 * timesliced.  If a task that is sharing the idle priority is ready
+                 * to run then the idle task should yield before the end of the
+                 * timeslice.
+                 *
+                 * A critical region is not required here as we are just reading from
+                 * the list, and an occasional incorrect value will not matter.  If
+                 * the ready list at the idle priority contains more than one task
+                 * then a task other than the idle task is ready to execute. */
+                if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+                {
+                    taskYIELD();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        #endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+        #if ( configUSE_IDLE_HOOK == 1 )
+            {
+                extern void vApplicationIdleHook( void );
+
+                /* Call the user defined function from within the idle task.  This
+                 * allows the application designer to add background functionality
+                 * without the overhead of a separate task.
+                 * NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+                 * CALL A FUNCTION THAT MIGHT BLOCK. */
+                vApplicationIdleHook();
+            }
+        #endif /* configUSE_IDLE_HOOK */
+
+        /* This conditional compilation should use inequality to 0, not equality
+         * to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
+         * user defined low power mode  implementations require
+         * configUSE_TICKLESS_IDLE to be set to a value other than 1. */
+        #if ( configUSE_TICKLESS_IDLE != 0 )
+            {
+                TickType_t xExpectedIdleTime;
+
+                /* It is not desirable to suspend then resume the scheduler on
+                 * each iteration of the idle task.  Therefore, a preliminary
+                 * test of the expected idle time is performed without the
+                 * scheduler suspended.  The result here is not necessarily
+                 * valid. */
+                xExpectedIdleTime = prvGetExpectedIdleTime();
+
+                if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+                {
+                    vTaskSuspendAll();
+                    {
+                        /* Now the scheduler is suspended, the expected idle
+                         * time can be sampled again, and this time its value can
+                         * be used. */
+                        configASSERT( xNextTaskUnblockTime >= xTickCount );
+                        xExpectedIdleTime = prvGetExpectedIdleTime();
+
+                        /* Define the following macro to set xExpectedIdleTime to 0
+                         * if the application does not want
+                         * portSUPPRESS_TICKS_AND_SLEEP() to be called. */
+                        configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
+
+                        if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+                        {
+                            traceLOW_POWER_IDLE_BEGIN();
+                            portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
+                            traceLOW_POWER_IDLE_END();
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                    ( void ) xTaskResumeAll();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        #endif /* configUSE_TICKLESS_IDLE */
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+    eSleepModeStatus eTaskConfirmSleepModeStatus( void )
+    {
+        /* The idle task exists in addition to the application tasks. */
+        const UBaseType_t uxNonApplicationTasks = 1;
+        eSleepModeStatus eReturn = eStandardSleep;
+
+        /* This function must be called from a critical section. */
+
+        if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
+        {
+            /* A task was made ready while the scheduler was suspended. */
+            eReturn = eAbortSleep;
+        }
+        else if( xYieldPending != pdFALSE )
+        {
+            /* A yield was pended while the scheduler was suspended. */
+            eReturn = eAbortSleep;
+        }
+        else if( xPendedTicks != 0 )
+        {
+            /* A tick interrupt has already occurred but was held pending
+             * because the scheduler is suspended. */
+            eReturn = eAbortSleep;
+        }
+        else
+        {
+            /* If all the tasks are in the suspended list (which might mean they
+             * have an infinite block time rather than actually being suspended)
+             * then it is safe to turn all clocks off and just wait for external
+             * interrupts. */
+            if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
+            {
+                eReturn = eNoTasksWaitingTimeout;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+
+        return eReturn;
+    }
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+    void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet,
+                                            BaseType_t xIndex,
+                                            void * pvValue )
+    {
+        TCB_t * pxTCB;
+
+        if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+        {
+            pxTCB = prvGetTCBFromHandle( xTaskToSet );
+            configASSERT( pxTCB != NULL );
+            pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
+        }
+    }
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+    void * pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery,
+                                               BaseType_t xIndex )
+    {
+        void * pvReturn = NULL;
+        TCB_t * pxTCB;
+
+        if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+        {
+            pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+            pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
+        }
+        else
+        {
+            pvReturn = NULL;
+        }
+
+        return pvReturn;
+    }
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+    void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify,
+                                  const MemoryRegion_t * const xRegions )
+    {
+        TCB_t * pxTCB;
+
+        /* If null is passed in here then we are modifying the MPU settings of
+         * the calling task. */
+        pxTCB = prvGetTCBFromHandle( xTaskToModify );
+
+        vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
+    }
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTaskLists( void )
+{
+    UBaseType_t uxPriority;
+
+    for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+    {
+        vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
+    }
+
+    vListInitialise( &xDelayedTaskList1 );
+    vListInitialise( &xDelayedTaskList2 );
+    vListInitialise( &xPendingReadyList );
+
+    #if ( INCLUDE_vTaskDelete == 1 )
+        {
+            vListInitialise( &xTasksWaitingTermination );
+        }
+    #endif /* INCLUDE_vTaskDelete */
+
+    #if ( INCLUDE_vTaskSuspend == 1 )
+        {
+            vListInitialise( &xSuspendedTaskList );
+        }
+    #endif /* INCLUDE_vTaskSuspend */
+
+    /* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
+     * using list2. */
+    pxDelayedTaskList = &xDelayedTaskList1;
+    pxOverflowDelayedTaskList = &xDelayedTaskList2;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTasksWaitingTermination( void )
+{
+    /** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
+
+    #if ( INCLUDE_vTaskDelete == 1 )
+        {
+            TCB_t * pxTCB;
+
+            /* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
+             * being called too often in the idle task. */
+            while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+            {
+                taskENTER_CRITICAL();
+                {
+                    pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+                    --uxCurrentNumberOfTasks;
+                    --uxDeletedTasksWaitingCleanUp;
+                }
+                taskEXIT_CRITICAL();
+
+                prvDeleteTCB( pxTCB );
+            }
+        }
+    #endif /* INCLUDE_vTaskDelete */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    void vTaskGetInfo( TaskHandle_t xTask,
+                       TaskStatus_t * pxTaskStatus,
+                       BaseType_t xGetFreeStackSpace,
+                       eTaskState eState )
+    {
+        TCB_t * pxTCB;
+
+        /* xTask is NULL then get the state of the calling task. */
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
+        pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName[ 0 ] );
+        pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
+        pxTaskStatus->pxStackBase = pxTCB->pxStack;
+        pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
+
+        #if ( configUSE_MUTEXES == 1 )
+            {
+                pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
+            }
+        #else
+            {
+                pxTaskStatus->uxBasePriority = 0;
+            }
+        #endif
+
+        #if ( configGENERATE_RUN_TIME_STATS == 1 )
+            {
+                pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
+            }
+        #else
+            {
+                pxTaskStatus->ulRunTimeCounter = 0;
+            }
+        #endif
+
+        /* Obtaining the task state is a little fiddly, so is only done if the
+         * value of eState passed into this function is eInvalid - otherwise the
+         * state is just set to whatever is passed in. */
+        if( eState != eInvalid )
+        {
+            if( pxTCB == pxCurrentTCB )
+            {
+                pxTaskStatus->eCurrentState = eRunning;
+            }
+            else
+            {
+                pxTaskStatus->eCurrentState = eState;
+
+                #if ( INCLUDE_vTaskSuspend == 1 )
+                    {
+                        /* If the task is in the suspended list then there is a
+                         *  chance it is actually just blocked indefinitely - so really
+                         *  it should be reported as being in the Blocked state. */
+                        if( eState == eSuspended )
+                        {
+                            vTaskSuspendAll();
+                            {
+                                if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+                                {
+                                    pxTaskStatus->eCurrentState = eBlocked;
+                                }
+                            }
+                            ( void ) xTaskResumeAll();
+                        }
+                    }
+                #endif /* INCLUDE_vTaskSuspend */
+            }
+        }
+        else
+        {
+            pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
+        }
+
+        /* Obtaining the stack space takes some time, so the xGetFreeStackSpace
+         * parameter is provided to allow it to be skipped. */
+        if( xGetFreeStackSpace != pdFALSE )
+        {
+            #if ( portSTACK_GROWTH > 0 )
+                {
+                    pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
+                }
+            #else
+                {
+                    pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
+                }
+            #endif
+        }
+        else
+        {
+            pxTaskStatus->usStackHighWaterMark = 0;
+        }
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+    static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t * pxTaskStatusArray,
+                                                     List_t * pxList,
+                                                     eTaskState eState )
+    {
+        configLIST_VOLATILE TCB_t * pxNextTCB, * pxFirstTCB;
+        UBaseType_t uxTask = 0;
+
+        if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+        {
+            listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+            /* Populate an TaskStatus_t structure within the
+             * pxTaskStatusArray array for each task that is referenced from
+             * pxList.  See the definition of TaskStatus_t in task.h for the
+             * meaning of each TaskStatus_t structure member. */
+            do
+            {
+                listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+                vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
+                uxTask++;
+            } while( pxNextTCB != pxFirstTCB );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        return uxTask;
+    }
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
+
+    static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+    {
+        uint32_t ulCount = 0U;
+
+        while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
+        {
+            pucStackByte -= portSTACK_GROWTH;
+            ulCount++;
+        }
+
+        ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
+
+        return ( configSTACK_DEPTH_TYPE ) ulCount;
+    }
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
+
+/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
+ * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
+ * user to determine the return type.  It gets around the problem of the value
+ * overflowing on 8-bit types without breaking backward compatibility for
+ * applications that expect an 8-bit return type. */
+    configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )
+    {
+        TCB_t * pxTCB;
+        uint8_t * pucEndOfStack;
+        configSTACK_DEPTH_TYPE uxReturn;
+
+        /* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
+         * the same except for their return type.  Using configSTACK_DEPTH_TYPE
+         * allows the user to determine the return type.  It gets around the
+         * problem of the value overflowing on 8-bit types without breaking
+         * backward compatibility for applications that expect an 8-bit return
+         * type. */
+
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        #if portSTACK_GROWTH < 0
+            {
+                pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+            }
+        #else
+            {
+                pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+            }
+        #endif
+
+        uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+        return uxReturn;
+    }
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+    UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+    {
+        TCB_t * pxTCB;
+        uint8_t * pucEndOfStack;
+        UBaseType_t uxReturn;
+
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        #if portSTACK_GROWTH < 0
+            {
+                pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+            }
+        #else
+            {
+                pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+            }
+        #endif
+
+        uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+        return uxReturn;
+    }
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+    static void prvDeleteTCB( TCB_t * pxTCB )
+    {
+        /* This call is required specifically for the TriCore port.  It must be
+         * above the vPortFree() calls.  The call is also used by ports/demos that
+         * want to allocate and clean RAM statically. */
+        portCLEAN_UP_TCB( pxTCB );
+
+        /* Free up the memory allocated by the scheduler for the task.  It is up
+         * to the task to free any memory allocated at the application level.
+         * See the third party link http://www.nadler.com/embedded/newlibAndFreeRTOS.html
+         * for additional information. */
+        #if ( configUSE_NEWLIB_REENTRANT == 1 )
+            {
+                _reclaim_reent( &( pxTCB->xNewLib_reent ) );
+            }
+        #endif /* configUSE_NEWLIB_REENTRANT */
+
+        #if ( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+            {
+                /* The task can only have been allocated dynamically - free both
+                 * the stack and TCB. */
+                vPortFree( pxTCB->pxStack );
+                vPortFree( pxTCB );
+            }
+        #elif ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
+            {
+                /* The task could have been allocated statically or dynamically, so
+                 * check what was statically allocated before trying to free the
+                 * memory. */
+                if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
+                {
+                    /* Both the stack and TCB were allocated dynamically, so both
+                     * must be freed. */
+                    vPortFree( pxTCB->pxStack );
+                    vPortFree( pxTCB );
+                }
+                else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
+                {
+                    /* Only the stack was statically allocated, so the TCB is the
+                     * only memory that must be freed. */
+                    vPortFree( pxTCB );
+                }
+                else
+                {
+                    /* Neither the stack nor the TCB were allocated dynamically, so
+                     * nothing needs to be freed. */
+                    configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB );
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+    }
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+static void prvResetNextTaskUnblockTime( void )
+{
+    if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+    {
+        /* The new current delayed list is empty.  Set xNextTaskUnblockTime to
+         * the maximum possible value so it is  extremely unlikely that the
+         * if( xTickCount >= xNextTaskUnblockTime ) test will pass until
+         * there is an item in the delayed list. */
+        xNextTaskUnblockTime = portMAX_DELAY;
+    }
+    else
+    {
+        /* The new current delayed list is not empty, get the value of
+         * the item at the head of the delayed list.  This is the time at
+         * which the task at the head of the delayed list should be removed
+         * from the Blocked state. */
+        xNextTaskUnblockTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxDelayedTaskList );
+    }
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+    TaskHandle_t xTaskGetCurrentTaskHandle( void )
+    {
+        TaskHandle_t xReturn;
+
+        /* A critical section is not required as this is not called from
+         * an interrupt and the current TCB will always be the same for any
+         * individual execution thread. */
+        xReturn = pxCurrentTCB;
+
+        return xReturn;
+    }
+
+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+
+    BaseType_t xTaskGetSchedulerState( void )
+    {
+        BaseType_t xReturn;
+
+        if( xSchedulerRunning == pdFALSE )
+        {
+            xReturn = taskSCHEDULER_NOT_STARTED;
+        }
+        else
+        {
+            if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+            {
+                xReturn = taskSCHEDULER_RUNNING;
+            }
+            else
+            {
+                xReturn = taskSCHEDULER_SUSPENDED;
+            }
+        }
+
+        return xReturn;
+    }
+
+#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+    BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
+    {
+        TCB_t * const pxMutexHolderTCB = pxMutexHolder;
+        BaseType_t xReturn = pdFALSE;
+
+        /* If the mutex was given back by an interrupt while the queue was
+         * locked then the mutex holder might now be NULL.  _RB_ Is this still
+         * needed as interrupts can no longer use mutexes? */
+        if( pxMutexHolder != NULL )
+        {
+            /* If the holder of the mutex has a priority below the priority of
+             * the task attempting to obtain the mutex then it will temporarily
+             * inherit the priority of the task attempting to obtain the mutex. */
+            if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
+            {
+                /* Adjust the mutex holder state to account for its new
+                 * priority.  Only reset the event list item value if the value is
+                 * not being used for anything else. */
+                if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+                {
+                    listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                /* If the task being modified is in the ready state it will need
+                 * to be moved into a new list. */
+                if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
+                {
+                    if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+                    {
+                        /* It is known that the task is in its ready list so
+                         * there is no need to check again and the port level
+                         * reset macro can be called directly. */
+                        portRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority, uxTopReadyPriority );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    /* Inherit the priority before being moved into the new list. */
+                    pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+                    prvAddTaskToReadyList( pxMutexHolderTCB );
+                }
+                else
+                {
+                    /* Just inherit the priority. */
+                    pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
+                }
+
+                traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
+
+                /* Inheritance occurred. */
+                xReturn = pdTRUE;
+            }
+            else
+            {
+                if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
+                {
+                    /* The base priority of the mutex holder is lower than the
+                     * priority of the task attempting to take the mutex, but the
+                     * current priority of the mutex holder is not lower than the
+                     * priority of the task attempting to take the mutex.
+                     * Therefore the mutex holder must have already inherited a
+                     * priority, but inheritance would have occurred if that had
+                     * not been the case. */
+                    xReturn = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        return xReturn;
+    }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+    BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
+    {
+        TCB_t * const pxTCB = pxMutexHolder;
+        BaseType_t xReturn = pdFALSE;
+
+        if( pxMutexHolder != NULL )
+        {
+            /* A task can only have an inherited priority if it holds the mutex.
+             * If the mutex is held by a task then it cannot be given from an
+             * interrupt, and if a mutex is given by the holding task then it must
+             * be the running state task. */
+            configASSERT( pxTCB == pxCurrentTCB );
+            configASSERT( pxTCB->uxMutexesHeld );
+            ( pxTCB->uxMutexesHeld )--;
+
+            /* Has the holder of the mutex inherited the priority of another
+             * task? */
+            if( pxTCB->uxPriority != pxTCB->uxBasePriority )
+            {
+                /* Only disinherit if no other mutexes are held. */
+                if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
+                {
+                    /* A task can only have an inherited priority if it holds
+                     * the mutex.  If the mutex is held by a task then it cannot be
+                     * given from an interrupt, and if a mutex is given by the
+                     * holding task then it must be the running state task.  Remove
+                     * the holding task from the ready list. */
+                    if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+                    {
+                        portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    /* Disinherit the priority before adding the task into the
+                     * new  ready list. */
+                    traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+                    pxTCB->uxPriority = pxTCB->uxBasePriority;
+
+                    /* Reset the event list item value.  It cannot be in use for
+                     * any other purpose if this task is running, and it must be
+                     * running to give back the mutex. */
+                    listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+                    prvAddTaskToReadyList( pxTCB );
+
+                    /* Return true to indicate that a context switch is required.
+                     * This is only actually required in the corner case whereby
+                     * multiple mutexes were held and the mutexes were given back
+                     * in an order different to that in which they were taken.
+                     * If a context switch did not occur when the first mutex was
+                     * returned, even if a task was waiting on it, then a context
+                     * switch should occur when the last mutex is returned whether
+                     * a task is waiting on it or not. */
+                    xReturn = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        return xReturn;
+    }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+    void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder,
+                                              UBaseType_t uxHighestPriorityWaitingTask )
+    {
+        TCB_t * const pxTCB = pxMutexHolder;
+        UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
+        const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
+
+        if( pxMutexHolder != NULL )
+        {
+            /* If pxMutexHolder is not NULL then the holder must hold at least
+             * one mutex. */
+            configASSERT( pxTCB->uxMutexesHeld );
+
+            /* Determine the priority to which the priority of the task that
+             * holds the mutex should be set.  This will be the greater of the
+             * holding task's base priority and the priority of the highest
+             * priority task that is waiting to obtain the mutex. */
+            if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
+            {
+                uxPriorityToUse = uxHighestPriorityWaitingTask;
+            }
+            else
+            {
+                uxPriorityToUse = pxTCB->uxBasePriority;
+            }
+
+            /* Does the priority need to change? */
+            if( pxTCB->uxPriority != uxPriorityToUse )
+            {
+                /* Only disinherit if no other mutexes are held.  This is a
+                 * simplification in the priority inheritance implementation.  If
+                 * the task that holds the mutex is also holding other mutexes then
+                 * the other mutexes may have caused the priority inheritance. */
+                if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
+                {
+                    /* If a task has timed out because it already holds the
+                     * mutex it was trying to obtain then it cannot of inherited
+                     * its own priority. */
+                    configASSERT( pxTCB != pxCurrentTCB );
+
+                    /* Disinherit the priority, remembering the previous
+                     * priority to facilitate determining the subject task's
+                     * state. */
+                    traceTASK_PRIORITY_DISINHERIT( pxTCB, uxPriorityToUse );
+                    uxPriorityUsedOnEntry = pxTCB->uxPriority;
+                    pxTCB->uxPriority = uxPriorityToUse;
+
+                    /* Only reset the event list item value if the value is not
+                     * being used for anything else. */
+                    if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+                    {
+                        listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+
+                    /* If the running task is not the task that holds the mutex
+                     * then the task that holds the mutex could be in either the
+                     * Ready, Blocked or Suspended states.  Only remove the task
+                     * from its current state list if it is in the Ready state as
+                     * the task's priority is going to change and there is one
+                     * Ready list per priority. */
+                    if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+                    {
+                        if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+                        {
+                            /* It is known that the task is in its ready list so
+                             * there is no need to check again and the port level
+                             * reset macro can be called directly. */
+                            portRESET_READY_PRIORITY( pxTCB->uxPriority, uxTopReadyPriority );
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+
+                        prvAddTaskToReadyList( pxTCB );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+    void vTaskEnterCritical( void )
+    {
+        portDISABLE_INTERRUPTS();
+
+        if( xSchedulerRunning != pdFALSE )
+        {
+            ( pxCurrentTCB->uxCriticalNesting )++;
+
+            /* This is not the interrupt safe version of the enter critical
+             * function so  assert() if it is being called from an interrupt
+             * context.  Only API functions that end in "FromISR" can be used in an
+             * interrupt.  Only assert if the critical nesting count is 1 to
+             * protect against recursive calls if the assert function also uses a
+             * critical section. */
+            if( pxCurrentTCB->uxCriticalNesting == 1 )
+            {
+                portASSERT_IF_IN_ISR();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+    void vTaskExitCritical( void )
+    {
+        if( xSchedulerRunning != pdFALSE )
+        {
+            if( pxCurrentTCB->uxCriticalNesting > 0U )
+            {
+                ( pxCurrentTCB->uxCriticalNesting )--;
+
+                if( pxCurrentTCB->uxCriticalNesting == 0U )
+                {
+                    portENABLE_INTERRUPTS();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+    static char * prvWriteNameToBuffer( char * pcBuffer,
+                                        const char * pcTaskName )
+    {
+        size_t x;
+
+        /* Start by copying the entire string. */
+        strcpy( pcBuffer, pcTaskName );
+
+        /* Pad the end of the string with spaces to ensure columns line up when
+         * printed out. */
+        for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
+        {
+            pcBuffer[ x ] = ' ';
+        }
+
+        /* Terminate. */
+        pcBuffer[ x ] = ( char ) 0x00;
+
+        /* Return the new end of string. */
+        return &( pcBuffer[ x ] );
+    }
+
+#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+    void vTaskList( char * pcWriteBuffer )
+    {
+        TaskStatus_t * pxTaskStatusArray;
+        UBaseType_t uxArraySize, x;
+        char cStatus;
+
+        /*
+         * PLEASE NOTE:
+         *
+         * This function is provided for convenience only, and is used by many
+         * of the demo applications.  Do not consider it to be part of the
+         * scheduler.
+         *
+         * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+         * uxTaskGetSystemState() output into a human readable table that
+         * displays task names, states and stack usage.
+         *
+         * vTaskList() has a dependency on the sprintf() C library function that
+         * might bloat the code size, use a lot of stack, and provide different
+         * results on different platforms.  An alternative, tiny, third party,
+         * and limited functionality implementation of sprintf() is provided in
+         * many of the FreeRTOS/Demo sub-directories in a file called
+         * printf-stdarg.c (note printf-stdarg.c does not provide a full
+         * snprintf() implementation!).
+         *
+         * It is recommended that production systems call uxTaskGetSystemState()
+         * directly to get access to raw stats data, rather than indirectly
+         * through a call to vTaskList().
+         */
+
+
+        /* Make sure the write buffer does not contain a string. */
+        *pcWriteBuffer = ( char ) 0x00;
+
+        /* Take a snapshot of the number of tasks in case it changes while this
+         * function is executing. */
+        uxArraySize = uxCurrentNumberOfTasks;
+
+        /* Allocate an array index for each task.  NOTE!  if
+         * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+         * equate to NULL. */
+        pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+        if( pxTaskStatusArray != NULL )
+        {
+            /* Generate the (binary) data. */
+            uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
+
+            /* Create a human readable table from the binary data. */
+            for( x = 0; x < uxArraySize; x++ )
+            {
+                switch( pxTaskStatusArray[ x ].eCurrentState )
+                {
+                    case eRunning:
+                        cStatus = tskRUNNING_CHAR;
+                        break;
+
+                    case eReady:
+                        cStatus = tskREADY_CHAR;
+                        break;
+
+                    case eBlocked:
+                        cStatus = tskBLOCKED_CHAR;
+                        break;
+
+                    case eSuspended:
+                        cStatus = tskSUSPENDED_CHAR;
+                        break;
+
+                    case eDeleted:
+                        cStatus = tskDELETED_CHAR;
+                        break;
+
+                    case eInvalid: /* Fall through. */
+                    default:       /* Should not get here, but it is included
+                                    * to prevent static checking errors. */
+                        cStatus = ( char ) 0x00;
+                        break;
+                }
+
+                /* Write the task name to the string, padding with spaces so it
+                 * can be printed in tabular form more easily. */
+                pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+                /* Write the rest of the string. */
+                sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+                pcWriteBuffer += strlen( pcWriteBuffer );                                                                                                                                                                                                /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+            }
+
+            /* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+             * is 0 then vPortFree() will be #defined to nothing. */
+            vPortFree( pxTaskStatusArray );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+    void vTaskGetRunTimeStats( char * pcWriteBuffer )
+    {
+        TaskStatus_t * pxTaskStatusArray;
+        UBaseType_t uxArraySize, x;
+        uint32_t ulTotalTime, ulStatsAsPercentage;
+
+        #if ( configUSE_TRACE_FACILITY != 1 )
+            {
+                #error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
+            }
+        #endif
+
+        /*
+         * PLEASE NOTE:
+         *
+         * This function is provided for convenience only, and is used by many
+         * of the demo applications.  Do not consider it to be part of the
+         * scheduler.
+         *
+         * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
+         * of the uxTaskGetSystemState() output into a human readable table that
+         * displays the amount of time each task has spent in the Running state
+         * in both absolute and percentage terms.
+         *
+         * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
+         * function that might bloat the code size, use a lot of stack, and
+         * provide different results on different platforms.  An alternative,
+         * tiny, third party, and limited functionality implementation of
+         * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
+         * a file called printf-stdarg.c (note printf-stdarg.c does not provide
+         * a full snprintf() implementation!).
+         *
+         * It is recommended that production systems call uxTaskGetSystemState()
+         * directly to get access to raw stats data, rather than indirectly
+         * through a call to vTaskGetRunTimeStats().
+         */
+
+        /* Make sure the write buffer does not contain a string. */
+        *pcWriteBuffer = ( char ) 0x00;
+
+        /* Take a snapshot of the number of tasks in case it changes while this
+         * function is executing. */
+        uxArraySize = uxCurrentNumberOfTasks;
+
+        /* Allocate an array index for each task.  NOTE!  If
+         * configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+         * equate to NULL. */
+        pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
+
+        if( pxTaskStatusArray != NULL )
+        {
+            /* Generate the (binary) data. */
+            uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
+
+            /* For percentage calculations. */
+            ulTotalTime /= 100UL;
+
+            /* Avoid divide by zero errors. */
+            if( ulTotalTime > 0UL )
+            {
+                /* Create a human readable table from the binary data. */
+                for( x = 0; x < uxArraySize; x++ )
+                {
+                    /* What percentage of the total run time has the task used?
+                     * This will always be rounded down to the nearest integer.
+                     * ulTotalRunTimeDiv100 has already been divided by 100. */
+                    ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
+
+                    /* Write the task name to the string, padding with
+                     * spaces so it can be printed in tabular form more
+                     * easily. */
+                    pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+                    if( ulStatsAsPercentage > 0UL )
+                    {
+                        #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+                            {
+                                sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+                            }
+                        #else
+                            {
+                                /* sizeof( int ) == sizeof( long ) so a smaller
+                                 * printf() library can be used. */
+                                sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+                            }
+                        #endif
+                    }
+                    else
+                    {
+                        /* If the percentage is zero here then the task has
+                         * consumed less than 1% of the total run time. */
+                        #ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+                            {
+                                sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
+                            }
+                        #else
+                            {
+                                /* sizeof( int ) == sizeof( long ) so a smaller
+                                 * printf() library can be used. */
+                                sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
+                            }
+                        #endif
+                    }
+
+                    pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            /* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+             * is 0 then vPortFree() will be #defined to nothing. */
+            vPortFree( pxTaskStatusArray );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+    }
+
+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+TickType_t uxTaskResetEventItemValue( void )
+{
+    TickType_t uxReturn;
+
+    uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
+
+    /* Reset the event list item to its normal value - so it can be used with
+     * queues and semaphores. */
+    listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+    return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+    TaskHandle_t pvTaskIncrementMutexHeldCount( void )
+    {
+        /* If xSemaphoreCreateMutex() is called before any tasks have been created
+         * then pxCurrentTCB will be NULL. */
+        if( pxCurrentTCB != NULL )
+        {
+            ( pxCurrentTCB->uxMutexesHeld )++;
+        }
+
+        return pxCurrentTCB;
+    }
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+    uint32_t ulTaskGenericNotifyTake( UBaseType_t uxIndexToWait,
+                                      BaseType_t xClearCountOnExit,
+                                      TickType_t xTicksToWait )
+    {
+        uint32_t ulReturn;
+
+        configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+
+        taskENTER_CRITICAL();
+        {
+            /* Only block if the notification count is not already non-zero. */
+            if( pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] == 0UL )
+            {
+                /* Mark this task as waiting for a notification. */
+                pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION;
+
+                if( xTicksToWait > ( TickType_t ) 0 )
+                {
+                    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+                    traceTASK_NOTIFY_TAKE_BLOCK( uxIndexToWait );
+
+                    /* All ports are written to allow a yield in a critical
+                     * section (some will yield immediately, others wait until the
+                     * critical section exits) - but it is not something that
+                     * application code should ever do. */
+                    portYIELD_WITHIN_API();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        taskENTER_CRITICAL();
+        {
+            traceTASK_NOTIFY_TAKE( uxIndexToWait );
+            ulReturn = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ];
+
+            if( ulReturn != 0UL )
+            {
+                if( xClearCountOnExit != pdFALSE )
+                {
+                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = 0UL;
+                }
+                else
+                {
+                    pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] = ulReturn - ( uint32_t ) 1;
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+
+            pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION;
+        }
+        taskEXIT_CRITICAL();
+
+        return ulReturn;
+    }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+    BaseType_t xTaskGenericNotifyWait( UBaseType_t uxIndexToWait,
+                                       uint32_t ulBitsToClearOnEntry,
+                                       uint32_t ulBitsToClearOnExit,
+                                       uint32_t * pulNotificationValue,
+                                       TickType_t xTicksToWait )
+    {
+        BaseType_t xReturn;
+
+        configASSERT( uxIndexToWait < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+
+        taskENTER_CRITICAL();
+        {
+            /* Only block if a notification is not already pending. */
+            if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED )
+            {
+                /* Clear bits in the task's notification value as bits may get
+                 * set  by the notifying task or interrupt.  This can be used to
+                 * clear the value to zero. */
+                pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnEntry;
+
+                /* Mark this task as waiting for a notification. */
+                pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskWAITING_NOTIFICATION;
+
+                if( xTicksToWait > ( TickType_t ) 0 )
+                {
+                    prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+                    traceTASK_NOTIFY_WAIT_BLOCK( uxIndexToWait );
+
+                    /* All ports are written to allow a yield in a critical
+                     * section (some will yield immediately, others wait until the
+                     * critical section exits) - but it is not something that
+                     * application code should ever do. */
+                    portYIELD_WITHIN_API();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        taskENTER_CRITICAL();
+        {
+            traceTASK_NOTIFY_WAIT( uxIndexToWait );
+
+            if( pulNotificationValue != NULL )
+            {
+                /* Output the current notification value, which may or may not
+                 * have changed. */
+                *pulNotificationValue = pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ];
+            }
+
+            /* If ucNotifyValue is set then either the task never entered the
+             * blocked state (because a notification was already pending) or the
+             * task unblocked because of a notification.  Otherwise the task
+             * unblocked because of a timeout. */
+            if( pxCurrentTCB->ucNotifyState[ uxIndexToWait ] != taskNOTIFICATION_RECEIVED )
+            {
+                /* A notification was not received. */
+                xReturn = pdFALSE;
+            }
+            else
+            {
+                /* A notification was already pending or a notification was
+                 * received while the task was waiting. */
+                pxCurrentTCB->ulNotifiedValue[ uxIndexToWait ] &= ~ulBitsToClearOnExit;
+                xReturn = pdTRUE;
+            }
+
+            pxCurrentTCB->ucNotifyState[ uxIndexToWait ] = taskNOT_WAITING_NOTIFICATION;
+        }
+        taskEXIT_CRITICAL();
+
+        return xReturn;
+    }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+    BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify,
+                                   UBaseType_t uxIndexToNotify,
+                                   uint32_t ulValue,
+                                   eNotifyAction eAction,
+                                   uint32_t * pulPreviousNotificationValue )
+    {
+        TCB_t * pxTCB;
+        BaseType_t xReturn = pdPASS;
+        uint8_t ucOriginalNotifyState;
+
+        configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+        configASSERT( xTaskToNotify );
+        pxTCB = xTaskToNotify;
+
+        taskENTER_CRITICAL();
+        {
+            if( pulPreviousNotificationValue != NULL )
+            {
+                *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ];
+            }
+
+            ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
+
+            pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
+
+            switch( eAction )
+            {
+                case eSetBits:
+                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue;
+                    break;
+
+                case eIncrement:
+                    ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;
+                    break;
+
+                case eSetValueWithOverwrite:
+                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
+                    break;
+
+                case eSetValueWithoutOverwrite:
+
+                    if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+                    {
+                        pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
+                    }
+                    else
+                    {
+                        /* The value could not be written to the task. */
+                        xReturn = pdFAIL;
+                    }
+
+                    break;
+
+                case eNoAction:
+
+                    /* The task is being notified without its notify value being
+                     * updated. */
+                    break;
+
+                default:
+
+                    /* Should not get here if all enums are handled.
+                     * Artificially force an assert by testing a value the
+                     * compiler can't assume is const. */
+                    configASSERT( xTickCount == ( TickType_t ) 0 );
+
+                    break;
+            }
+
+            traceTASK_NOTIFY( uxIndexToNotify );
+
+            /* If the task is in the blocked state specifically to wait for a
+             * notification then unblock it now. */
+            if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+            {
+                ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+                prvAddTaskToReadyList( pxTCB );
+
+                /* The task should not have been on an event list. */
+                configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+                #if ( configUSE_TICKLESS_IDLE != 0 )
+                    {
+                        /* If a task is blocked waiting for a notification then
+                         * xNextTaskUnblockTime might be set to the blocked task's time
+                         * out time.  If the task is unblocked for a reason other than
+                         * a timeout xNextTaskUnblockTime is normally left unchanged,
+                         * because it will automatically get reset to a new value when
+                         * the tick count equals xNextTaskUnblockTime.  However if
+                         * tickless idling is used it might be more important to enter
+                         * sleep mode at the earliest possible time - so reset
+                         * xNextTaskUnblockTime here to ensure it is updated at the
+                         * earliest possible time. */
+                        prvResetNextTaskUnblockTime();
+                    }
+                #endif
+
+                if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                {
+                    /* The notified task has a priority above the currently
+                     * executing task so a yield is required. */
+                    taskYIELD_IF_USING_PREEMPTION();
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        return xReturn;
+    }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+    BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify,
+                                          UBaseType_t uxIndexToNotify,
+                                          uint32_t ulValue,
+                                          eNotifyAction eAction,
+                                          uint32_t * pulPreviousNotificationValue,
+                                          BaseType_t * pxHigherPriorityTaskWoken )
+    {
+        TCB_t * pxTCB;
+        uint8_t ucOriginalNotifyState;
+        BaseType_t xReturn = pdPASS;
+        UBaseType_t uxSavedInterruptStatus;
+
+        configASSERT( xTaskToNotify );
+        configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+
+        /* RTOS ports that support interrupt nesting have the concept of a
+         * maximum  system call (or maximum API call) interrupt priority.
+         * Interrupts that are  above the maximum system call priority are keep
+         * permanently enabled, even when the RTOS kernel is in a critical section,
+         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+         * is defined in FreeRTOSConfig.h then
+         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+         * failure if a FreeRTOS API function is called from an interrupt that has
+         * been assigned a priority above the configured maximum system call
+         * priority.  Only FreeRTOS functions that end in FromISR can be called
+         * from interrupts  that have been assigned a priority at or (logically)
+         * below the maximum system call interrupt priority.  FreeRTOS maintains a
+         * separate interrupt safe API to ensure interrupt entry is as fast and as
+         * simple as possible.  More information (albeit Cortex-M specific) is
+         * provided on the following link:
+         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+        pxTCB = xTaskToNotify;
+
+        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+        {
+            if( pulPreviousNotificationValue != NULL )
+            {
+                *pulPreviousNotificationValue = pxTCB->ulNotifiedValue[ uxIndexToNotify ];
+            }
+
+            ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
+            pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
+
+            switch( eAction )
+            {
+                case eSetBits:
+                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] |= ulValue;
+                    break;
+
+                case eIncrement:
+                    ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;
+                    break;
+
+                case eSetValueWithOverwrite:
+                    pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
+                    break;
+
+                case eSetValueWithoutOverwrite:
+
+                    if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+                    {
+                        pxTCB->ulNotifiedValue[ uxIndexToNotify ] = ulValue;
+                    }
+                    else
+                    {
+                        /* The value could not be written to the task. */
+                        xReturn = pdFAIL;
+                    }
+
+                    break;
+
+                case eNoAction:
+
+                    /* The task is being notified without its notify value being
+                     * updated. */
+                    break;
+
+                default:
+
+                    /* Should not get here if all enums are handled.
+                     * Artificially force an assert by testing a value the
+                     * compiler can't assume is const. */
+                    configASSERT( xTickCount == ( TickType_t ) 0 );
+                    break;
+            }
+
+            traceTASK_NOTIFY_FROM_ISR( uxIndexToNotify );
+
+            /* If the task is in the blocked state specifically to wait for a
+             * notification then unblock it now. */
+            if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+            {
+                /* The task should not have been on an event list. */
+                configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+                if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+                {
+                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+                    prvAddTaskToReadyList( pxTCB );
+                }
+                else
+                {
+                    /* The delayed and ready lists cannot be accessed, so hold
+                     * this task pending until the scheduler is resumed. */
+                    vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+                }
+
+                if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                {
+                    /* The notified task has a priority above the currently
+                     * executing task so a yield is required. */
+                    if( pxHigherPriorityTaskWoken != NULL )
+                    {
+                        *pxHigherPriorityTaskWoken = pdTRUE;
+                    }
+
+                    /* Mark that a yield is pending in case the user is not
+                     * using the "xHigherPriorityTaskWoken" parameter to an ISR
+                     * safe FreeRTOS function. */
+                    xYieldPending = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        }
+        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+        return xReturn;
+    }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+    void vTaskGenericNotifyGiveFromISR( TaskHandle_t xTaskToNotify,
+                                        UBaseType_t uxIndexToNotify,
+                                        BaseType_t * pxHigherPriorityTaskWoken )
+    {
+        TCB_t * pxTCB;
+        uint8_t ucOriginalNotifyState;
+        UBaseType_t uxSavedInterruptStatus;
+
+        configASSERT( xTaskToNotify );
+        configASSERT( uxIndexToNotify < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+
+        /* RTOS ports that support interrupt nesting have the concept of a
+         * maximum  system call (or maximum API call) interrupt priority.
+         * Interrupts that are  above the maximum system call priority are keep
+         * permanently enabled, even when the RTOS kernel is in a critical section,
+         * but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+         * is defined in FreeRTOSConfig.h then
+         * portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+         * failure if a FreeRTOS API function is called from an interrupt that has
+         * been assigned a priority above the configured maximum system call
+         * priority.  Only FreeRTOS functions that end in FromISR can be called
+         * from interrupts  that have been assigned a priority at or (logically)
+         * below the maximum system call interrupt priority.  FreeRTOS maintains a
+         * separate interrupt safe API to ensure interrupt entry is as fast and as
+         * simple as possible.  More information (albeit Cortex-M specific) is
+         * provided on the following link:
+         * https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+        portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+        pxTCB = xTaskToNotify;
+
+        uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+        {
+            ucOriginalNotifyState = pxTCB->ucNotifyState[ uxIndexToNotify ];
+            pxTCB->ucNotifyState[ uxIndexToNotify ] = taskNOTIFICATION_RECEIVED;
+
+            /* 'Giving' is equivalent to incrementing a count in a counting
+             * semaphore. */
+            ( pxTCB->ulNotifiedValue[ uxIndexToNotify ] )++;
+
+            traceTASK_NOTIFY_GIVE_FROM_ISR( uxIndexToNotify );
+
+            /* If the task is in the blocked state specifically to wait for a
+             * notification then unblock it now. */
+            if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+            {
+                /* The task should not have been on an event list. */
+                configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+                if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+                {
+                    ( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+                    prvAddTaskToReadyList( pxTCB );
+                }
+                else
+                {
+                    /* The delayed and ready lists cannot be accessed, so hold
+                     * this task pending until the scheduler is resumed. */
+                    vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+                }
+
+                if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+                {
+                    /* The notified task has a priority above the currently
+                     * executing task so a yield is required. */
+                    if( pxHigherPriorityTaskWoken != NULL )
+                    {
+                        *pxHigherPriorityTaskWoken = pdTRUE;
+                    }
+
+                    /* Mark that a yield is pending in case the user is not
+                     * using the "xHigherPriorityTaskWoken" parameter in an ISR
+                     * safe FreeRTOS function. */
+                    xYieldPending = pdTRUE;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+        }
+        portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+    }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+    BaseType_t xTaskGenericNotifyStateClear( TaskHandle_t xTask,
+                                             UBaseType_t uxIndexToClear )
+    {
+        TCB_t * pxTCB;
+        BaseType_t xReturn;
+
+        configASSERT( uxIndexToClear < configTASK_NOTIFICATION_ARRAY_ENTRIES );
+
+        /* If null is passed in here then it is the calling task that is having
+         * its notification state cleared. */
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        taskENTER_CRITICAL();
+        {
+            if( pxTCB->ucNotifyState[ uxIndexToClear ] == taskNOTIFICATION_RECEIVED )
+            {
+                pxTCB->ucNotifyState[ uxIndexToClear ] = taskNOT_WAITING_NOTIFICATION;
+                xReturn = pdPASS;
+            }
+            else
+            {
+                xReturn = pdFAIL;
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        return xReturn;
+    }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+
+    uint32_t ulTaskGenericNotifyValueClear( TaskHandle_t xTask,
+                                            UBaseType_t uxIndexToClear,
+                                            uint32_t ulBitsToClear )
+    {
+        TCB_t * pxTCB;
+        uint32_t ulReturn;
+
+        /* If null is passed in here then it is the calling task that is having
+         * its notification state cleared. */
+        pxTCB = prvGetTCBFromHandle( xTask );
+
+        taskENTER_CRITICAL();
+        {
+            /* Return the notification as it was before the bits were cleared,
+             * then clear the bit mask. */
+            ulReturn = pxTCB->ulNotifiedValue[ uxIndexToClear ];
+            pxTCB->ulNotifiedValue[ uxIndexToClear ] &= ~ulBitsToClear;
+        }
+        taskEXIT_CRITICAL();
+
+        return ulReturn;
+    }
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
+
+    uint32_t ulTaskGetIdleRunTimeCounter( void )
+    {
+        return xIdleTaskHandle->ulRunTimeCounter;
+    }
+
+#endif
+/*-----------------------------------------------------------*/
+
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait,
+                                            const BaseType_t xCanBlockIndefinitely )
+{
+    TickType_t xTimeToWake;
+    const TickType_t xConstTickCount = xTickCount;
+
+    #if ( INCLUDE_xTaskAbortDelay == 1 )
+        {
+            /* About to enter a delayed list, so ensure the ucDelayAborted flag is
+             * reset to pdFALSE so it can be detected as having been set to pdTRUE
+             * when the task leaves the Blocked state. */
+            pxCurrentTCB->ucDelayAborted = pdFALSE;
+        }
+    #endif
+
+    /* Remove the task from the ready list before adding it to the blocked list
+     * as the same list item is used for both lists. */
+    if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+    {
+        /* The current task must be in a ready list, so there is no need to
+         * check, and the port reset macro can be called directly. */
+        portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
+    }
+    else
+    {
+        mtCOVERAGE_TEST_MARKER();
+    }
+
+    #if ( INCLUDE_vTaskSuspend == 1 )
+        {
+            if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
+            {
+                /* Add the task to the suspended task list instead of a delayed task
+                 * list to ensure it is not woken by a timing event.  It will block
+                 * indefinitely. */
+                vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
+            }
+            else
+            {
+                /* Calculate the time at which the task should be woken if the event
+                 * does not occur.  This may overflow but this doesn't matter, the
+                 * kernel will manage it correctly. */
+                xTimeToWake = xConstTickCount + xTicksToWait;
+
+                /* The list item will be inserted in wake time order. */
+                listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+                if( xTimeToWake < xConstTickCount )
+                {
+                    /* Wake time has overflowed.  Place this item in the overflow
+                     * list. */
+                    vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+                }
+                else
+                {
+                    /* The wake time has not overflowed, so the current block list
+                     * is used. */
+                    vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+                    /* If the task entering the blocked state was placed at the
+                     * head of the list of blocked tasks then xNextTaskUnblockTime
+                     * needs to be updated too. */
+                    if( xTimeToWake < xNextTaskUnblockTime )
+                    {
+                        xNextTaskUnblockTime = xTimeToWake;
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+            }
+        }
+    #else /* INCLUDE_vTaskSuspend */
+        {
+            /* Calculate the time at which the task should be woken if the event
+             * does not occur.  This may overflow but this doesn't matter, the kernel
+             * will manage it correctly. */
+            xTimeToWake = xConstTickCount + xTicksToWait;
+
+            /* The list item will be inserted in wake time order. */
+            listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+            if( xTimeToWake < xConstTickCount )
+            {
+                /* Wake time has overflowed.  Place this item in the overflow list. */
+                vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+            }
+            else
+            {
+                /* The wake time has not overflowed, so the current block list is used. */
+                vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+                /* If the task entering the blocked state was placed at the head of the
+                 * list of blocked tasks then xNextTaskUnblockTime needs to be updated
+                 * too. */
+                if( xTimeToWake < xNextTaskUnblockTime )
+                {
+                    xNextTaskUnblockTime = xTimeToWake;
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+            }
+
+            /* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
+            ( void ) xCanBlockIndefinitely;
+        }
+    #endif /* INCLUDE_vTaskSuspend */
+}
+
+/* Code below here allows additional code to be inserted into this source file,
+ * especially where access to file scope functions and data is needed (for example
+ * when performing module tests). */
+
+#ifdef FREERTOS_MODULE_TEST
+    #include "tasks_test_access_functions.h"
+#endif
+
+
+#if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )
+
+    #include "freertos_tasks_c_additions.h"
+
+    #ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
+        static void freertos_tasks_c_additions_init( void )
+        {
+            FREERTOS_TASKS_C_ADDITIONS_INIT();
+        }
+    #endif
+
+#endif /* if ( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 ) */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/timers.c b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/timers.c
new file mode 100644
index 0000000..eb42296
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/FreeRTOS/Source/timers.c
@@ -0,0 +1,1144 @@
+/*
+ * FreeRTOS Kernel V10.4.3
+ * Copyright (C) 2020 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy of
+ * this software and associated documentation files (the "Software"), to deal in
+ * the Software without restriction, including without limitation the rights to
+ * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
+ * the Software, and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in all
+ * copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
+ * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
+ * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
+ * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * https://www.FreeRTOS.org
+ * https://github.com/FreeRTOS
+ *
+ */
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+ * all the API functions to use the MPU wrappers.  That should only be done when
+ * task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
+    #error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
+#endif
+
+/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
+ * because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
+ * for the header files above, but not in this file, in order to generate the
+ * correct privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
+
+
+/* This entire source file will be skipped if the application is not configured
+ * to include software timer functionality.  This #if is closed at the very bottom
+ * of this file.  If you want to include software timer functionality then ensure
+ * configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_TIMERS == 1 )
+
+/* Misc definitions. */
+    #define tmrNO_DELAY    ( TickType_t ) 0U
+
+/* The name assigned to the timer service task.  This can be overridden by
+ * defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
+    #ifndef configTIMER_SERVICE_TASK_NAME
+        #define configTIMER_SERVICE_TASK_NAME    "Tmr Svc"
+    #endif
+
+/* Bit definitions used in the ucStatus member of a timer structure. */
+    #define tmrSTATUS_IS_ACTIVE                  ( ( uint8_t ) 0x01 )
+    #define tmrSTATUS_IS_STATICALLY_ALLOCATED    ( ( uint8_t ) 0x02 )
+    #define tmrSTATUS_IS_AUTORELOAD              ( ( uint8_t ) 0x04 )
+
+/* The definition of the timers themselves. */
+    typedef struct tmrTimerControl                  /* The old naming convention is used to prevent breaking kernel aware debuggers. */
+    {
+        const char * pcTimerName;                   /*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+        ListItem_t xTimerListItem;                  /*<< Standard linked list item as used by all kernel features for event management. */
+        TickType_t xTimerPeriodInTicks;             /*<< How quickly and often the timer expires. */
+        void * pvTimerID;                           /*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
+        TimerCallbackFunction_t pxCallbackFunction; /*<< The function that will be called when the timer expires. */
+        #if ( configUSE_TRACE_FACILITY == 1 )
+            UBaseType_t uxTimerNumber;              /*<< An ID assigned by trace tools such as FreeRTOS+Trace */
+        #endif
+        uint8_t ucStatus;                           /*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
+    } xTIMER;
+
+/* The old xTIMER name is maintained above then typedefed to the new Timer_t
+ * name below to enable the use of older kernel aware debuggers. */
+    typedef xTIMER Timer_t;
+
+/* The definition of messages that can be sent and received on the timer queue.
+ * Two types of message can be queued - messages that manipulate a software timer,
+ * and messages that request the execution of a non-timer related callback.  The
+ * two message types are defined in two separate structures, xTimerParametersType
+ * and xCallbackParametersType respectively. */
+    typedef struct tmrTimerParameters
+    {
+        TickType_t xMessageValue; /*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
+        Timer_t * pxTimer;        /*<< The timer to which the command will be applied. */
+    } TimerParameter_t;
+
+
+    typedef struct tmrCallbackParameters
+    {
+        PendedFunction_t pxCallbackFunction; /* << The callback function to execute. */
+        void * pvParameter1;                 /* << The value that will be used as the callback functions first parameter. */
+        uint32_t ulParameter2;               /* << The value that will be used as the callback functions second parameter. */
+    } CallbackParameters_t;
+
+/* The structure that contains the two message types, along with an identifier
+ * that is used to determine which message type is valid. */
+    typedef struct tmrTimerQueueMessage
+    {
+        BaseType_t xMessageID; /*<< The command being sent to the timer service task. */
+        union
+        {
+            TimerParameter_t xTimerParameters;
+
+            /* Don't include xCallbackParameters if it is not going to be used as
+             * it makes the structure (and therefore the timer queue) larger. */
+            #if ( INCLUDE_xTimerPendFunctionCall == 1 )
+                CallbackParameters_t xCallbackParameters;
+            #endif /* INCLUDE_xTimerPendFunctionCall */
+        } u;
+    } DaemonTaskMessage_t;
+
+/*lint -save -e956 A manual analysis and inspection has been used to determine
+ * which static variables must be declared volatile. */
+
+/* The list in which active timers are stored.  Timers are referenced in expire
+ * time order, with the nearest expiry time at the front of the list.  Only the
+ * timer service task is allowed to access these lists.
+ * xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
+ * breaks some kernel aware debuggers, and debuggers that reply on removing the
+ * static qualifier. */
+    PRIVILEGED_DATA static List_t xActiveTimerList1;
+    PRIVILEGED_DATA static List_t xActiveTimerList2;
+    PRIVILEGED_DATA static List_t * pxCurrentTimerList;
+    PRIVILEGED_DATA static List_t * pxOverflowTimerList;
+
+/* A queue that is used to send commands to the timer service task. */
+    PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
+    PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
+
+/*lint -restore */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Initialise the infrastructure used by the timer service task if it has not
+ * been initialised already.
+ */
+    static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The timer service task (daemon).  Timer functionality is controlled by this
+ * task.  Other tasks communicate with the timer service task using the
+ * xTimerQueue queue.
+ */
+    static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by the timer service task to interpret and process a command it
+ * received on the timer queue.
+ */
+    static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
+ * depending on if the expire time causes a timer counter overflow.
+ */
+    static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer,
+                                                  const TickType_t xNextExpiryTime,
+                                                  const TickType_t xTimeNow,
+                                                  const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
+
+/*
+ * An active timer has reached its expire time.  Reload the timer if it is an
+ * auto-reload timer, then call its callback.
+ */
+    static void prvProcessExpiredTimer( const TickType_t xNextExpireTime,
+                                        const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
+
+/*
+ * The tick count has overflowed.  Switch the timer lists after ensuring the
+ * current timer list does not still reference some timers.
+ */
+    static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.
+ */
+    static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the timer list contains any active timers then return the expire time of
+ * the timer that will expire first and set *pxListWasEmpty to false.  If the
+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty
+ * to pdTRUE.
+ */
+    static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a timer has expired, process it.  Otherwise, block the timer service task
+ * until either a timer does expire or a command is received.
+ */
+    static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime,
+                                            BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a Timer_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+    static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                       const TickType_t xTimerPeriodInTicks,
+                                       const UBaseType_t uxAutoReload,
+                                       void * const pvTimerID,
+                                       TimerCallbackFunction_t pxCallbackFunction,
+                                       Timer_t * pxNewTimer ) PRIVILEGED_FUNCTION;
+/*-----------------------------------------------------------*/
+
+    BaseType_t xTimerCreateTimerTask( void )
+    {
+        BaseType_t xReturn = pdFAIL;
+
+        /* This function is called when the scheduler is started if
+         * configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
+         * timer service task has been created/initialised.  If timers have already
+         * been created then the initialisation will already have been performed. */
+        prvCheckForValidListAndQueue();
+
+        if( xTimerQueue != NULL )
+        {
+            #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+                {
+                    StaticTask_t * pxTimerTaskTCBBuffer = NULL;
+                    StackType_t * pxTimerTaskStackBuffer = NULL;
+                    uint32_t ulTimerTaskStackSize;
+
+                    vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+                    xTimerTaskHandle = xTaskCreateStatic( prvTimerTask,
+                                                          configTIMER_SERVICE_TASK_NAME,
+                                                          ulTimerTaskStackSize,
+                                                          NULL,
+                                                          ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+                                                          pxTimerTaskStackBuffer,
+                                                          pxTimerTaskTCBBuffer );
+
+                    if( xTimerTaskHandle != NULL )
+                    {
+                        xReturn = pdPASS;
+                    }
+                }
+            #else /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+                {
+                    xReturn = xTaskCreate( prvTimerTask,
+                                           configTIMER_SERVICE_TASK_NAME,
+                                           configTIMER_TASK_STACK_DEPTH,
+                                           NULL,
+                                           ( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+                                           &xTimerTaskHandle );
+                }
+            #endif /* configSUPPORT_STATIC_ALLOCATION */
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        configASSERT( xReturn );
+        return xReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+        TimerHandle_t xTimerCreate( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                    const TickType_t xTimerPeriodInTicks,
+                                    const UBaseType_t uxAutoReload,
+                                    void * const pvTimerID,
+                                    TimerCallbackFunction_t pxCallbackFunction )
+        {
+            Timer_t * pxNewTimer;
+
+            pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
+
+            if( pxNewTimer != NULL )
+            {
+                /* Status is thus far zero as the timer is not created statically
+                 * and has not been started.  The auto-reload bit may get set in
+                 * prvInitialiseNewTimer. */
+                pxNewTimer->ucStatus = 0x00;
+                prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+            }
+
+            return pxNewTimer;
+        }
+
+    #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+    #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+        TimerHandle_t xTimerCreateStatic( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                          const TickType_t xTimerPeriodInTicks,
+                                          const UBaseType_t uxAutoReload,
+                                          void * const pvTimerID,
+                                          TimerCallbackFunction_t pxCallbackFunction,
+                                          StaticTimer_t * pxTimerBuffer )
+        {
+            Timer_t * pxNewTimer;
+
+            #if ( configASSERT_DEFINED == 1 )
+                {
+                    /* Sanity check that the size of the structure used to declare a
+                     * variable of type StaticTimer_t equals the size of the real timer
+                     * structure. */
+                    volatile size_t xSize = sizeof( StaticTimer_t );
+                    configASSERT( xSize == sizeof( Timer_t ) );
+                    ( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
+                }
+            #endif /* configASSERT_DEFINED */
+
+            /* A pointer to a StaticTimer_t structure MUST be provided, use it. */
+            configASSERT( pxTimerBuffer );
+            pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
+
+            if( pxNewTimer != NULL )
+            {
+                /* Timers can be created statically or dynamically so note this
+                 * timer was created statically in case it is later deleted.  The
+                 * auto-reload bit may get set in prvInitialiseNewTimer(). */
+                pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
+
+                prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+            }
+
+            return pxNewTimer;
+        }
+
+    #endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+    static void prvInitialiseNewTimer( const char * const pcTimerName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+                                       const TickType_t xTimerPeriodInTicks,
+                                       const UBaseType_t uxAutoReload,
+                                       void * const pvTimerID,
+                                       TimerCallbackFunction_t pxCallbackFunction,
+                                       Timer_t * pxNewTimer )
+    {
+        /* 0 is not a valid value for xTimerPeriodInTicks. */
+        configASSERT( ( xTimerPeriodInTicks > 0 ) );
+
+        if( pxNewTimer != NULL )
+        {
+            /* Ensure the infrastructure used by the timer service task has been
+             * created/initialised. */
+            prvCheckForValidListAndQueue();
+
+            /* Initialise the timer structure members using the function
+             * parameters. */
+            pxNewTimer->pcTimerName = pcTimerName;
+            pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
+            pxNewTimer->pvTimerID = pvTimerID;
+            pxNewTimer->pxCallbackFunction = pxCallbackFunction;
+            vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
+
+            if( uxAutoReload != pdFALSE )
+            {
+                pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+            }
+
+            traceTIMER_CREATE( pxNewTimer );
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t xTimerGenericCommand( TimerHandle_t xTimer,
+                                     const BaseType_t xCommandID,
+                                     const TickType_t xOptionalValue,
+                                     BaseType_t * const pxHigherPriorityTaskWoken,
+                                     const TickType_t xTicksToWait )
+    {
+        BaseType_t xReturn = pdFAIL;
+        DaemonTaskMessage_t xMessage;
+
+        configASSERT( xTimer );
+
+        /* Send a message to the timer service task to perform a particular action
+         * on a particular timer definition. */
+        if( xTimerQueue != NULL )
+        {
+            /* Send a command to the timer service task to start the xTimer timer. */
+            xMessage.xMessageID = xCommandID;
+            xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+            xMessage.u.xTimerParameters.pxTimer = xTimer;
+
+            if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+            {
+                if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
+                {
+                    xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+                }
+                else
+                {
+                    xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
+                }
+            }
+            else
+            {
+                xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+            }
+
+            traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+        }
+        else
+        {
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        return xReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
+    {
+        /* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
+         * started, then xTimerTaskHandle will be NULL. */
+        configASSERT( ( xTimerTaskHandle != NULL ) );
+        return xTimerTaskHandle;
+    }
+/*-----------------------------------------------------------*/
+
+    TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
+    {
+        Timer_t * pxTimer = xTimer;
+
+        configASSERT( xTimer );
+        return pxTimer->xTimerPeriodInTicks;
+    }
+/*-----------------------------------------------------------*/
+
+    void vTimerSetReloadMode( TimerHandle_t xTimer,
+                              const UBaseType_t uxAutoReload )
+    {
+        Timer_t * pxTimer = xTimer;
+
+        configASSERT( xTimer );
+        taskENTER_CRITICAL();
+        {
+            if( uxAutoReload != pdFALSE )
+            {
+                pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
+            }
+            else
+            {
+                pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD;
+            }
+        }
+        taskEXIT_CRITICAL();
+    }
+/*-----------------------------------------------------------*/
+
+    UBaseType_t uxTimerGetReloadMode( TimerHandle_t xTimer )
+    {
+        Timer_t * pxTimer = xTimer;
+        UBaseType_t uxReturn;
+
+        configASSERT( xTimer );
+        taskENTER_CRITICAL();
+        {
+            if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) == 0 )
+            {
+                /* Not an auto-reload timer. */
+                uxReturn = ( UBaseType_t ) pdFALSE;
+            }
+            else
+            {
+                /* Is an auto-reload timer. */
+                uxReturn = ( UBaseType_t ) pdTRUE;
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        return uxReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
+    {
+        Timer_t * pxTimer = xTimer;
+        TickType_t xReturn;
+
+        configASSERT( xTimer );
+        xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
+        return xReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+    {
+        Timer_t * pxTimer = xTimer;
+
+        configASSERT( xTimer );
+        return pxTimer->pcTimerName;
+    }
+/*-----------------------------------------------------------*/
+
+    static void prvProcessExpiredTimer( const TickType_t xNextExpireTime,
+                                        const TickType_t xTimeNow )
+    {
+        BaseType_t xResult;
+        Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+
+        /* Remove the timer from the list of active timers.  A check has already
+         * been performed to ensure the list is not empty. */
+
+        ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+        traceTIMER_EXPIRED( pxTimer );
+
+        /* If the timer is an auto-reload timer then calculate the next
+         * expiry time and re-insert the timer in the list of active timers. */
+        if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+        {
+            /* The timer is inserted into a list using a time relative to anything
+             * other than the current time.  It will therefore be inserted into the
+             * correct list relative to the time this task thinks it is now. */
+            if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
+            {
+                /* The timer expired before it was added to the active timer
+                 * list.  Reload it now.  */
+                xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+                configASSERT( xResult );
+                ( void ) xResult;
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        else
+        {
+            pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+            mtCOVERAGE_TEST_MARKER();
+        }
+
+        /* Call the timer callback. */
+        pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+    }
+/*-----------------------------------------------------------*/
+
+    static portTASK_FUNCTION( prvTimerTask, pvParameters )
+    {
+        TickType_t xNextExpireTime;
+        BaseType_t xListWasEmpty;
+
+        /* Just to avoid compiler warnings. */
+        ( void ) pvParameters;
+
+        #if ( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
+            {
+                extern void vApplicationDaemonTaskStartupHook( void );
+
+                /* Allow the application writer to execute some code in the context of
+                 * this task at the point the task starts executing.  This is useful if the
+                 * application includes initialisation code that would benefit from
+                 * executing after the scheduler has been started. */
+                vApplicationDaemonTaskStartupHook();
+            }
+        #endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
+
+        for( ; ; )
+        {
+            /* Query the timers list to see if it contains any timers, and if so,
+             * obtain the time at which the next timer will expire. */
+            xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+
+            /* If a timer has expired, process it.  Otherwise, block this task
+             * until either a timer does expire, or a command is received. */
+            prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
+
+            /* Empty the command queue. */
+            prvProcessReceivedCommands();
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime,
+                                            BaseType_t xListWasEmpty )
+    {
+        TickType_t xTimeNow;
+        BaseType_t xTimerListsWereSwitched;
+
+        vTaskSuspendAll();
+        {
+            /* Obtain the time now to make an assessment as to whether the timer
+             * has expired or not.  If obtaining the time causes the lists to switch
+             * then don't process this timer as any timers that remained in the list
+             * when the lists were switched will have been processed within the
+             * prvSampleTimeNow() function. */
+            xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+            if( xTimerListsWereSwitched == pdFALSE )
+            {
+                /* The tick count has not overflowed, has the timer expired? */
+                if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
+                {
+                    ( void ) xTaskResumeAll();
+                    prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
+                }
+                else
+                {
+                    /* The tick count has not overflowed, and the next expire
+                     * time has not been reached yet.  This task should therefore
+                     * block to wait for the next expire time or a command to be
+                     * received - whichever comes first.  The following line cannot
+                     * be reached unless xNextExpireTime > xTimeNow, except in the
+                     * case when the current timer list is empty. */
+                    if( xListWasEmpty != pdFALSE )
+                    {
+                        /* The current timer list is empty - is the overflow list
+                         * also empty? */
+                        xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
+                    }
+
+                    vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
+
+                    if( xTaskResumeAll() == pdFALSE )
+                    {
+                        /* Yield to wait for either a command to arrive, or the
+                         * block time to expire.  If a command arrived between the
+                         * critical section being exited and this yield then the yield
+                         * will not cause the task to block. */
+                        portYIELD_WITHIN_API();
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+            }
+            else
+            {
+                ( void ) xTaskResumeAll();
+            }
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
+    {
+        TickType_t xNextExpireTime;
+
+        /* Timers are listed in expiry time order, with the head of the list
+         * referencing the task that will expire first.  Obtain the time at which
+         * the timer with the nearest expiry time will expire.  If there are no
+         * active timers then just set the next expire time to 0.  That will cause
+         * this task to unblock when the tick count overflows, at which point the
+         * timer lists will be switched and the next expiry time can be
+         * re-assessed.  */
+        *pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
+
+        if( *pxListWasEmpty == pdFALSE )
+        {
+            xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+        }
+        else
+        {
+            /* Ensure the task unblocks when the tick count rolls over. */
+            xNextExpireTime = ( TickType_t ) 0U;
+        }
+
+        return xNextExpireTime;
+    }
+/*-----------------------------------------------------------*/
+
+    static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
+    {
+        TickType_t xTimeNow;
+        PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+
+        xTimeNow = xTaskGetTickCount();
+
+        if( xTimeNow < xLastTime )
+        {
+            prvSwitchTimerLists();
+            *pxTimerListsWereSwitched = pdTRUE;
+        }
+        else
+        {
+            *pxTimerListsWereSwitched = pdFALSE;
+        }
+
+        xLastTime = xTimeNow;
+
+        return xTimeNow;
+    }
+/*-----------------------------------------------------------*/
+
+    static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer,
+                                                  const TickType_t xNextExpiryTime,
+                                                  const TickType_t xTimeNow,
+                                                  const TickType_t xCommandTime )
+    {
+        BaseType_t xProcessTimerNow = pdFALSE;
+
+        listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
+        listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+
+        if( xNextExpiryTime <= xTimeNow )
+        {
+            /* Has the expiry time elapsed between the command to start/reset a
+             * timer was issued, and the time the command was processed? */
+            if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+            {
+                /* The time between a command being issued and the command being
+                 * processed actually exceeds the timers period.  */
+                xProcessTimerNow = pdTRUE;
+            }
+            else
+            {
+                vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
+            }
+        }
+        else
+        {
+            if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
+            {
+                /* If, since the command was issued, the tick count has overflowed
+                 * but the expiry time has not, then the timer must have already passed
+                 * its expiry time and should be processed immediately. */
+                xProcessTimerNow = pdTRUE;
+            }
+            else
+            {
+                vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+            }
+        }
+
+        return xProcessTimerNow;
+    }
+/*-----------------------------------------------------------*/
+
+    static void prvProcessReceivedCommands( void )
+    {
+        DaemonTaskMessage_t xMessage;
+        Timer_t * pxTimer;
+        BaseType_t xTimerListsWereSwitched, xResult;
+        TickType_t xTimeNow;
+
+        while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+        {
+            #if ( INCLUDE_xTimerPendFunctionCall == 1 )
+                {
+                    /* Negative commands are pended function calls rather than timer
+                     * commands. */
+                    if( xMessage.xMessageID < ( BaseType_t ) 0 )
+                    {
+                        const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
+
+                        /* The timer uses the xCallbackParameters member to request a
+                         * callback be executed.  Check the callback is not NULL. */
+                        configASSERT( pxCallback );
+
+                        /* Call the function. */
+                        pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
+                    }
+                    else
+                    {
+                        mtCOVERAGE_TEST_MARKER();
+                    }
+                }
+            #endif /* INCLUDE_xTimerPendFunctionCall */
+
+            /* Commands that are positive are timer commands rather than pended
+             * function calls. */
+            if( xMessage.xMessageID >= ( BaseType_t ) 0 )
+            {
+                /* The messages uses the xTimerParameters member to work on a
+                 * software timer. */
+                pxTimer = xMessage.u.xTimerParameters.pxTimer;
+
+                if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
+                {
+                    /* The timer is in a list, remove it. */
+                    ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+                }
+                else
+                {
+                    mtCOVERAGE_TEST_MARKER();
+                }
+
+                traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
+
+                /* In this case the xTimerListsWereSwitched parameter is not used, but
+                 *  it must be present in the function call.  prvSampleTimeNow() must be
+                 *  called after the message is received from xTimerQueue so there is no
+                 *  possibility of a higher priority task adding a message to the message
+                 *  queue with a time that is ahead of the timer daemon task (because it
+                 *  pre-empted the timer daemon task after the xTimeNow value was set). */
+                xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+                switch( xMessage.xMessageID )
+                {
+                    case tmrCOMMAND_START:
+                    case tmrCOMMAND_START_FROM_ISR:
+                    case tmrCOMMAND_RESET:
+                    case tmrCOMMAND_RESET_FROM_ISR:
+                    case tmrCOMMAND_START_DONT_TRACE:
+                        /* Start or restart a timer. */
+                        pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+
+                        if( prvInsertTimerInActiveList( pxTimer, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+                        {
+                            /* The timer expired before it was added to the active
+                             * timer list.  Process it now. */
+                            pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+                            traceTIMER_EXPIRED( pxTimer );
+
+                            if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+                            {
+                                xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
+                                configASSERT( xResult );
+                                ( void ) xResult;
+                            }
+                            else
+                            {
+                                mtCOVERAGE_TEST_MARKER();
+                            }
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+
+                        break;
+
+                    case tmrCOMMAND_STOP:
+                    case tmrCOMMAND_STOP_FROM_ISR:
+                        /* The timer has already been removed from the active list. */
+                        pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+                        break;
+
+                    case tmrCOMMAND_CHANGE_PERIOD:
+                    case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR:
+                        pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
+                        pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+                        configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+
+                        /* The new period does not really have a reference, and can
+                         * be longer or shorter than the old one.  The command time is
+                         * therefore set to the current time, and as the period cannot
+                         * be zero the next expiry time can only be in the future,
+                         * meaning (unlike for the xTimerStart() case above) there is
+                         * no fail case that needs to be handled here. */
+                        ( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+                        break;
+
+                    case tmrCOMMAND_DELETE:
+                        #if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+                            {
+                                /* The timer has already been removed from the active list,
+                                 * just free up the memory if the memory was dynamically
+                                 * allocated. */
+                                if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
+                                {
+                                    vPortFree( pxTimer );
+                                }
+                                else
+                                {
+                                    pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+                                }
+                            }
+                        #else /* if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) */
+                            {
+                                /* If dynamic allocation is not enabled, the memory
+                                 * could not have been dynamically allocated. So there is
+                                 * no need to free the memory - just mark the timer as
+                                 * "not active". */
+                                pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
+                            }
+                        #endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+                        break;
+
+                    default:
+                        /* Don't expect to get here. */
+                        break;
+                }
+            }
+        }
+    }
+/*-----------------------------------------------------------*/
+
+    static void prvSwitchTimerLists( void )
+    {
+        TickType_t xNextExpireTime, xReloadTime;
+        List_t * pxTemp;
+        Timer_t * pxTimer;
+        BaseType_t xResult;
+
+        /* The tick count has overflowed.  The timer lists must be switched.
+         * If there are any timers still referenced from the current timer list
+         * then they must have expired and should be processed before the lists
+         * are switched. */
+        while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+        {
+            xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+            /* Remove the timer from the list. */
+            pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
+            ( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+            traceTIMER_EXPIRED( pxTimer );
+
+            /* Execute its callback, then send a command to restart the timer if
+             * it is an auto-reload timer.  It cannot be restarted here as the lists
+             * have not yet been switched. */
+            pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+
+            if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
+            {
+                /* Calculate the reload value, and if the reload value results in
+                 * the timer going into the same timer list then it has already expired
+                 * and the timer should be re-inserted into the current list so it is
+                 * processed again within this loop.  Otherwise a command should be sent
+                 * to restart the timer to ensure it is only inserted into a list after
+                 * the lists have been swapped. */
+                xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
+
+                if( xReloadTime > xNextExpireTime )
+                {
+                    listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
+                    listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+                    vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+                }
+                else
+                {
+                    xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+                    configASSERT( xResult );
+                    ( void ) xResult;
+                }
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+
+        pxTemp = pxCurrentTimerList;
+        pxCurrentTimerList = pxOverflowTimerList;
+        pxOverflowTimerList = pxTemp;
+    }
+/*-----------------------------------------------------------*/
+
+    static void prvCheckForValidListAndQueue( void )
+    {
+        /* Check that the list from which active timers are referenced, and the
+         * queue used to communicate with the timer service, have been
+         * initialised. */
+        taskENTER_CRITICAL();
+        {
+            if( xTimerQueue == NULL )
+            {
+                vListInitialise( &xActiveTimerList1 );
+                vListInitialise( &xActiveTimerList2 );
+                pxCurrentTimerList = &xActiveTimerList1;
+                pxOverflowTimerList = &xActiveTimerList2;
+
+                #if ( configSUPPORT_STATIC_ALLOCATION == 1 )
+                    {
+                        /* The timer queue is allocated statically in case
+                         * configSUPPORT_DYNAMIC_ALLOCATION is 0. */
+                        PRIVILEGED_DATA static StaticQueue_t xStaticTimerQueue;                                                                          /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+                        PRIVILEGED_DATA static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
+
+                        xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+                    }
+                #else
+                    {
+                        xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
+                    }
+                #endif /* if ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
+
+                #if ( configQUEUE_REGISTRY_SIZE > 0 )
+                    {
+                        if( xTimerQueue != NULL )
+                        {
+                            vQueueAddToRegistry( xTimerQueue, "TmrQ" );
+                        }
+                        else
+                        {
+                            mtCOVERAGE_TEST_MARKER();
+                        }
+                    }
+                #endif /* configQUEUE_REGISTRY_SIZE */
+            }
+            else
+            {
+                mtCOVERAGE_TEST_MARKER();
+            }
+        }
+        taskEXIT_CRITICAL();
+    }
+/*-----------------------------------------------------------*/
+
+    BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
+    {
+        BaseType_t xReturn;
+        Timer_t * pxTimer = xTimer;
+
+        configASSERT( xTimer );
+
+        /* Is the timer in the list of active timers? */
+        taskENTER_CRITICAL();
+        {
+            if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
+            {
+                xReturn = pdFALSE;
+            }
+            else
+            {
+                xReturn = pdTRUE;
+            }
+        }
+        taskEXIT_CRITICAL();
+
+        return xReturn;
+    } /*lint !e818 Can't be pointer to const due to the typedef. */
+/*-----------------------------------------------------------*/
+
+    void * pvTimerGetTimerID( const TimerHandle_t xTimer )
+    {
+        Timer_t * const pxTimer = xTimer;
+        void * pvReturn;
+
+        configASSERT( xTimer );
+
+        taskENTER_CRITICAL();
+        {
+            pvReturn = pxTimer->pvTimerID;
+        }
+        taskEXIT_CRITICAL();
+
+        return pvReturn;
+    }
+/*-----------------------------------------------------------*/
+
+    void vTimerSetTimerID( TimerHandle_t xTimer,
+                           void * pvNewID )
+    {
+        Timer_t * const pxTimer = xTimer;
+
+        configASSERT( xTimer );
+
+        taskENTER_CRITICAL();
+        {
+            pxTimer->pvTimerID = pvNewID;
+        }
+        taskEXIT_CRITICAL();
+    }
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_xTimerPendFunctionCall == 1 )
+
+        BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+                                                  void * pvParameter1,
+                                                  uint32_t ulParameter2,
+                                                  BaseType_t * pxHigherPriorityTaskWoken )
+        {
+            DaemonTaskMessage_t xMessage;
+            BaseType_t xReturn;
+
+            /* Complete the message with the function parameters and post it to the
+             * daemon task. */
+            xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
+            xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+            xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+            xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+            xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+
+            tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+            return xReturn;
+        }
+
+    #endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+    #if ( INCLUDE_xTimerPendFunctionCall == 1 )
+
+        BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+                                           void * pvParameter1,
+                                           uint32_t ulParameter2,
+                                           TickType_t xTicksToWait )
+        {
+            DaemonTaskMessage_t xMessage;
+            BaseType_t xReturn;
+
+            /* This function can only be called after a timer has been created or
+             * after the scheduler has been started because, until then, the timer
+             * queue does not exist. */
+            configASSERT( xTimerQueue );
+
+            /* Complete the message with the function parameters and post it to the
+             * daemon task. */
+            xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
+            xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+            xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+            xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+            xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+
+            tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+            return xReturn;
+        }
+
+    #endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+
+        UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
+        {
+            return ( ( Timer_t * ) xTimer )->uxTimerNumber;
+        }
+
+    #endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+    #if ( configUSE_TRACE_FACILITY == 1 )
+
+        void vTimerSetTimerNumber( TimerHandle_t xTimer,
+                                   UBaseType_t uxTimerNumber )
+        {
+            ( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
+        }
+
+    #endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+ * to include software timer functionality.  If you want to include software timer
+ * functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_TIMERS == 1 */
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-core-no-safety-config.mk b/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-core-no-safety-config.mk
new file mode 100644
index 0000000..0eeeb18
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-core-no-safety-config.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-freertos-core-no-safety-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_FREERTOS_CORE_NO_SAFETY_CONFIG               := 1
+
+#
+# Location of source code files
+MODULE_FREERTOS_CORE_NO_SAFETY_SOURCE_DIR            = $(FREERTOS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_FREERTOS_CORE_NO_SAFETY_INCLUDES              =
+MODULE_FREERTOS_CORE_NO_SAFETY_INCLUDES              = -I $(FREERTOS_DIR)/include
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-core-no-safety.mk b/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-core-no-safety.mk
new file mode 100644
index 0000000..8d4d045
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-core-no-safety.mk
@@ -0,0 +1,69 @@
+#
+# Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-freertos-core-no-safety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_FREERTOS_CORE_NO_SAFETY_NAME                 := FREERTOS_CORE_NO_SAFETY
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_FREERTOS_CORE_NO_SAFETY_DEFINED              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_FREERTOS_CORE_NO_SAFETY_DEPENDS              := FREERTOS_CORE_NO_SAFETY
+$(foreach _,$(CONFIG_FREERTOS_CORE_NO_SAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+ifndef MODULE_FREERTOS_CORE_NO_SAFETY_C_SRC
+MODULE_FREERTOS_CORE_NO_SAFETY_C_SRC                 =
+MODULE_FREERTOS_CORE_NO_SAFETY_C_SRC                += $(FREERTOS_DIR)/croutine.c
+MODULE_FREERTOS_CORE_NO_SAFETY_C_SRC                += $(FREERTOS_DIR)/event_groups.c
+MODULE_FREERTOS_CORE_NO_SAFETY_C_SRC                += $(FREERTOS_DIR)/list.c
+MODULE_FREERTOS_CORE_NO_SAFETY_C_SRC                += $(FREERTOS_DIR)/queue.c
+MODULE_FREERTOS_CORE_NO_SAFETY_C_SRC                += $(FREERTOS_DIR)/tasks.c
+MODULE_FREERTOS_CORE_NO_SAFETY_C_SRC                += $(FREERTOS_DIR)/timers.c
+endif
+
+#
+# Assembly source
+MODULE_FREERTOS_CORE_NO_SAFETY_ASM_SRC               =
+
+#
+# Special C Flags
+MODULE_FREERTOS_CORE_NO_SAFETY_C_FLAGS               =
+
+#
+# Special ASM Flags
+MODULE_FREERTOS_CORE_NO_SAFETY_ASM_FLAGS             =
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-mmgr-no-safety-config.mk b/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-mmgr-no-safety-config.mk
new file mode 100644
index 0000000..e890a47
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-mmgr-no-safety-config.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-freertos-mmgr-no-safety-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_FREERTOS_MMGR_NO_SAFETY_CONFIG               := 1
+
+#
+# Location of source code files
+MODULE_FREERTOS_MMGR_NO_SAFETY_SOURCE_DIR            = $(FREERTOS_MMGR_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_FREERTOS_MMGR_NO_SAFETY_INCLUDES              =
+MODULE_FREERTOS_MMGR_NO_SAFETY_INCLUDES              = -I $(FREERTOS_DIR)/include
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-mmgr-no-safety.mk b/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-mmgr-no-safety.mk
new file mode 100644
index 0000000..c147cea
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-mmgr-no-safety.mk
@@ -0,0 +1,68 @@
+#
+# Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-freertos-mmgr-no-safety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_FREERTOS_MMGR_NO_SAFETY_NAME                 := FREERTOS_MMGR_NO_SAFETY
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_FREERTOS_MMGR_NO_SAFETY_DEFINED              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_FREERTOS_MMGR_NO_SAFETY_DEPENDS              := FREERTOS_CORE_NO_SAFETY
+$(foreach _,$(CONFIG_FREERTOS_MMGR_NO_SAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+ifndef MODULE_FREERTOS_MMGR_NO_SAFETY_C_SRC
+MODULE_FREERTOS_MMGR_NO_SAFETY_C_SRC                 =
+MODULE_FREERTOS_MMGR_NO_SAFETY_C_SRC                += $(FREERTOS_MMGR_DIR)/heap_1.c
+MODULE_FREERTOS_MMGR_NO_SAFETY_C_SRC                += $(FREERTOS_MMGR_DIR)/heap_2.c
+MODULE_FREERTOS_MMGR_NO_SAFETY_C_SRC                += $(FREERTOS_MMGR_DIR)/heap_3.c
+MODULE_FREERTOS_MMGR_NO_SAFETY_C_SRC                += $(FREERTOS_MMGR_DIR)/heap_4.c
+MODULE_FREERTOS_MMGR_NO_SAFETY_C_SRC                += $(FREERTOS_MMGR_DIR)/heap_5.c
+endif
+
+#
+# Assembly source
+MODULE_FREERTOS_MMGR_NO_SAFETY_ASM_SRC               =
+
+#
+# Special C Flags
+MODULE_FREERTOS_MMGR_NO_SAFETY_C_FLAGS               =
+
+#
+# Special ASM Flags
+MODULE_FREERTOS_MMGR_NO_SAFETY_ASM_FLAGS             =
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-port-cortex-r5-no-safety-config.mk b/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-port-cortex-r5-no-safety-config.mk
new file mode 100644
index 0000000..4177d18
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-port-cortex-r5-no-safety-config.mk
@@ -0,0 +1,34 @@
+#
+# Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-freertos-port-cortex-r5-no-safety-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_FREERTOS_PORT_CORTEX_R5_NO_SAFETY_CONFIG     := 1
+
+#
+# Location of source code files
+MODULE_FREERTOS_PORT_CORTEX_R5_NO_SAFETY_SOURCE_DIR  = $(FREERTOS_PORT_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_FREERTOS_PORT_CORTEX_R5_NO_SAFETY_INCLUDES   += -I $(FREERTOS_PORT_DIR)
diff --git a/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-port-cortex-r5-no-safety.mk b/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-port-cortex-r5-no-safety.mk
new file mode 100644
index 0000000..383692f
--- /dev/null
+++ b/spe-freertos-bsp/FreeRTOSV10.4.3/fsp_project/module-freertos-port-cortex-r5-no-safety.mk
@@ -0,0 +1,63 @@
+#
+# Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-freertos-port-cortex-r5-no-safety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_FREERTOS_PORT_CORTEX_R5_NO_SAFETY_NAME       := FREERTOS_PORT_CORTEX_R5_NO_SAFETY
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_FREERTOS_PORT_CORTEX_R5_NO_SAFETY_DEFINED    := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_FREERTOS_PORT_CORTEX_R5_NO_SAFETY_DEPENDS    := FREERTOS_CORE_NO_SAFETY FREERTOS_PORT_CORTEX_R5_NO_SAFETY
+$(foreach _,$(CONFIG_FREERTOS_PORT_CORTEX_R5_NO_SAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_FREERTOS_PORT_CORTEX_R5_NO_SAFETY_C_SRC       =
+MODULE_FREERTOS_PORT_CORTEX_R5_NO_SAFETY_C_SRC      += $(FREERTOS_PORT_DIR)/port.c
+
+#
+# Assembly source
+MODULE_FREERTOS_PORT_CORTEX_R5_NO_SAFETY_ASM_SRC     =
+MODULE_FREERTOS_PORT_CORTEX_R5_NO_SAFETY_ASM_SRC    += $(FREERTOS_PORT_DIR)/portASM.S
+
+#
+# Special C Flags
+MODULE_FREERTOS_PORT_CORTEX_R5_NO_SAFETY_C_FLAGS     =
+
+#
+# Special ASM Flags
+MODULE_FREERTOS_PORT_CORTEX_R5_NO_SAFETY_ASM_FLAGS   =
diff --git a/spe-freertos-bsp/README.txt b/spe-freertos-bsp/README.txt
new file mode 100644
index 0000000..194ae07
--- /dev/null
+++ b/spe-freertos-bsp/README.txt
@@ -0,0 +1,6 @@
+This package contains the rt-aux-cpu-demo-fsp sources which provide a FreeRTOS
+based software demo to run Real-Time applications on the Cortex-R5 Sensor
+Processing Engine (SPE) on the Jetson platforms.
+
+How to get started:
+Follow rt-aux-cpu-demo-fsp/doc/welcome.md and rt-aux-cpu-demo-fsp/doc/compile-flash.md for the details.
diff --git a/spe-freertos-bsp/fsp/source/diags/cr52-diag/cr52-diag.c b/spe-freertos-bsp/fsp/source/diags/cr52-diag/cr52-diag.c
new file mode 100644
index 0000000..906e33f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/diags/cr52-diag/cr52-diag.c
@@ -0,0 +1,129 @@
+/*
+ * cr52-diag - Diagnostics module for debugging FSP on NVRISCV.
+ *
+ */
+#include <stdbool.h>
+
+#include <stdint.h>
+#include <stddef.h>
+#include <misc/ct-assert.h>
+#include <cpu/mmio-access.h>
+#include <misc/macros.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__MMIO_ACCESS_H, "Header file missing or invalid.")
+
+#if 0
+#pragma message "content of INT_MAX: " STR(INT_MAX)
+#pragma message "content of INT32_MAX: " STR(INT32_MAX)
+#pragma message "content of UINT_MAX: " STR(UINT_MAX)
+#pragma message "content of UINT32_MAX: " STR(UINT32_MAX)
+#pragma message "content of LONG_MAX: " STR(LONG_MAX)
+#pragma message "content of size_t: " STR(__SIZE_TYPE__)
+#pragma message "content of sizeof(uintptr_t): " STR(sizeof(uintptr_t))
+#pragma message "content of sizeof(uint32_t): " STR(sizeof(uint32_t))
+#pragma message "content of sizeof(unsigned long): " STR(sizeof(unsigned long))
+#pragma message "content of __LONG_MAX__: " STR(__LONG_MAX__)
+#pragma message "content of UINTPTR_MAX: " STR(UINTPTR_MAX)
+#endif
+
+#define BASE_ADDR32	0x12345678U
+#define BASE_ADDR64	0x1234567890UL
+#define OFFSET_32	0x75050505U
+
+/* Prototypes */
+void cr52_diag(void);
+uint32_t r32(uintptr_t addr);
+void     w32(uintptr_t addr, uint32_t data);
+//uint32_t ra32(uint32_t addr);
+//void     wa32(uint32_t data, uint32_t addr);
+uint32_t r32o(uintptr_t addr, uint32_t offset);
+void     w32o(uintptr_t addr, uint32_t offset, uint32_t data);
+//uint32_t ra32o(uint32_t addr, uint32_t offset);
+//void     wa32o(uint32_t data, uint32_t addr, uint32_t offset);
+
+/* CR52-DIAG implementation */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+void cr52_diag(void)
+{
+    /* Verify that 32-bit MMIO functions are MISRA clean */
+    uintptr_t addr32 = BASE_ADDR32;
+    uint32_t  offs32 = OFFSET_32;
+    uint32_t  data32;
+    data32 = r32(addr32);
+    w32(addr32, data32);
+//    data32 = ra32(addr32);
+//    wa32(data32, addr32);
+    data32 = r32o(addr32, offs32);
+    w32o(addr32, offs32, data32);
+//    data32 = ra32o(addr32, offs32);
+//    wa32o(data32, addr32, offs32);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+uint32_t r32(uintptr_t addr)
+{
+    return ioread32(addr);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+void w32(uintptr_t addr, uint32_t data)
+{
+    iowrite32(addr, data);
+}
+
+#if 0
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+uint32_t ra32(uint32_t addr)
+{
+    return readl(addr);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+void wa32(uint32_t data, uint32_t addr)
+{
+    writel(addr, data);
+}
+#endif
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+uint32_t r32o(uintptr_t addr, uint32_t offset)
+{
+    return ioread32_offset(addr, offset);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+void w32o(uintptr_t addr, uint32_t offset, uint32_t data)
+{
+    iowrite32_offset(addr, offset, data);
+}
+
+#if 0
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+uint32_t ra32o(uint32_t addr, uint32_t offset)
+{
+    return readl_base_offset(addr, offset);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+void wa32o(uint32_t data, uint32_t addr, uint32_t offset)
+{
+    writel_base_offset(data, addr, offset);
+}
+#endif
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/diags/cr52-diag/module-cr52-diag-config.mk b/spe-freertos-bsp/fsp/source/diags/cr52-diag/module-cr52-diag-config.mk
new file mode 100644
index 0000000..8ae6b2e
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/diags/cr52-diag/module-cr52-diag-config.mk
@@ -0,0 +1,54 @@
+#
+# Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cr52-diag-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to
+#   VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_CR52_DIAG_CONFIG			:= 1
+
+#
+# Define a something similar to header guard protection...for makefiles
+# instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_CR52_DIAG_DEFINED		:= 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_CR52_DIAG_DEPENDS		:= CPL
+$(foreach _,$(MODULE_CR52_DIAG_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_CR52_DIAG_DRIVERS_DIR		 = $(FSP_COMMON_REPO)/diags/cr52-diag
+MODULE_CR52_DIAG_SOURCE_DIR		 = $(MODULE_CR52_DIAG_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_CR52_DIAG_INCLUDES          =
diff --git a/spe-freertos-bsp/fsp/source/diags/cr52-diag/module-cr52-diag.mk b/spe-freertos-bsp/fsp/source/diags/cr52-diag/module-cr52-diag.mk
new file mode 100644
index 0000000..b4af212
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/diags/cr52-diag/module-cr52-diag.mk
@@ -0,0 +1,62 @@
+#
+# Copyright (c) 2020 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cr52-diag.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to
+#   VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_CR52_DIAG_NAME		:= CR52_DIAG
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_CR52_DIAG_DEFINED	:= 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_CR52_DIAG_DEPENDS	:= CR52_DIAG CPL
+$(foreach _,$(CONFIG_CR52_DIAG_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_CR52_DIAG_C_SRC		 =
+MODULE_CR52_DIAG_C_SRC		+= $(MODULE_CR52_DIAG_DRIVERS_DIR)/cr52-diag.c
+
+#
+# Assembly source
+MODULE_CR52_DIAG_ASM_SRC	 =
+
+#
+# Special C Flags
+MODULE_CR52_DIAG_C_FLAGS	 =
+
+#
+# Special ASM Flags
+MODULE_CR52_DIAG_ASM_FLAGS	 =
diff --git a/spe-freertos-bsp/fsp/source/diags/nvgpu-diag/module-nvgpu-diag-config.mk b/spe-freertos-bsp/fsp/source/diags/nvgpu-diag/module-nvgpu-diag-config.mk
new file mode 100644
index 0000000..4bc9006
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/diags/nvgpu-diag/module-nvgpu-diag-config.mk
@@ -0,0 +1,54 @@
+#
+# Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-nvgpu-diag-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to
+#   VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_NVGPU_DIAG_CONFIG            := 1
+
+#
+# Define a something similar to header guard protection...for makefiles
+# instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_NVGPU_DIAG_DEFINED           := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_NVGPU_DIAG_DEPENDS           := CPL
+$(foreach _,$(MODULE_NVGPU_DIAG_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_NVGPU_DIAG_DRIVERS_DIR        = $(FSP_COMMON_REPO)/diags/nvgpu-diag
+MODULE_NVGPU_DIAG_SOURCE_DIR         = $(MODULE_NVGPU_DIAG_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_NVGPU_DIAG_INCLUDES           =
diff --git a/spe-freertos-bsp/fsp/source/diags/nvgpu-diag/module-nvgpu-diag.mk b/spe-freertos-bsp/fsp/source/diags/nvgpu-diag/module-nvgpu-diag.mk
new file mode 100644
index 0000000..ce28cbc
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/diags/nvgpu-diag/module-nvgpu-diag.mk
@@ -0,0 +1,62 @@
+#
+# Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-nvgpu-diag.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to
+#   VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_NVGPU_DIAG_NAME          := NVGPU_DIAG
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_NVGPU_DIAG_DEFINED       := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_NVGPU_DIAG_DEPENDS       := NVGPU_DIAG CPL
+$(foreach _,$(CONFIG_NVGPU_DIAG_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_NVGPU_DIAG_C_SRC          =
+MODULE_NVGPU_DIAG_C_SRC         += $(MODULE_NVGPU_DIAG_DRIVERS_DIR)/nvgpu-diag.c
+
+#
+# Assembly source
+MODULE_NVGPU_DIAG_ASM_SRC        =
+
+#
+# Special C Flags
+MODULE_NVGPU_DIAG_C_FLAGS        =
+
+#
+# Special ASM Flags
+MODULE_NVGPU_DIAG_ASM_FLAGS      =
diff --git a/spe-freertos-bsp/fsp/source/diags/nvgpu-diag/nvgpu-diag.c b/spe-freertos-bsp/fsp/source/diags/nvgpu-diag/nvgpu-diag.c
new file mode 100644
index 0000000..d437e0b
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/diags/nvgpu-diag/nvgpu-diag.c
@@ -0,0 +1,276 @@
+/* _NVRM_COPYRIGHT_BEGIN_
+ *
+ * Copyright 2018-2021 by NVIDIA Corporation.  All rights reserved.  All
+ * information contained herein is proprietary and confidential to NVIDIA
+ * Corporation.  Any use, reproduction, or disclosure without the written
+ * permission of NVIDIA Corporation is prohibited.
+ *
+ * _NVRM_COPYRIGHT_END_
+ */
+
+/*
+ * nvgpu-diag - Diagnostics module for debugging FSP on NVRISCV.
+ */
+
+/*
+ * @file nvgpu-diag.c
+ * @brief Diagnostics module for debugging FSP on NVRISCV.
+ */
+#include <stdbool.h>
+
+#include <stdint.h>
+#include <stddef.h>
+#include <misc/ct-assert.h>
+#include <misc/macros.h>
+
+#include <misc/nvmisc_drf.h>
+#include <cpu/cache.h>
+#include <cpu/csr.h>
+#include <cpu/io.h>
+#include <cpu/mmio-access.h>
+#include <cpu/riscv-mpu.h>
+#include <cpu/fence.h>
+#include <cpu/barriers.h>
+#include <cpu/sbi.h>
+#include <cpu/shutdown.h>
+#include <ssp/ssp.h>
+#include <libc-lite/libc.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The HEADER_CHECK macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+HEADER_CHECK(FSP__MISC__MACROS_H)
+HEADER_CHECK(FSP__CPU__MMIO_ACCESS_H)
+HEADER_CHECK(FSP__CPU__IO_H)
+#if NVRISCV_HAS_CSB_MMIO
+HEADER_CHECK(FSP__CPU__IO_CSB_H)
+#endif
+HEADER_CHECK(FSP__CPU__IO_LOCAL_H)
+#if NVRISCV_HAS_PRI
+HEADER_CHECK(FSP__CPU__IO_PRI_H)
+#endif
+#if NVRISCV_HAS_DIO_SE || NVRISCV_HAS_DIO_SNIC || NVRISCV_HAS_DIO_FBHUB
+HEADER_CHECK(FSP__CPU__IO_DIO_H)
+#endif
+HEADER_CHECK(FSP__MISC__NVMISC_DRF_H)
+HEADER_CHECK(FSP__CPU__RISCV_MPU_H)
+HEADER_CHECK(FSP__CPU__FENCE_H)
+HEADER_CHECK(FSP__CPU__CACHE_H)
+HEADER_CHECK(FSP__CPU__BARRIER_H)
+HEADER_CHECK(FSP__CPU__SHUTDOWN_H)
+HEADER_CHECK(FSP__CPU__SBI_H)
+HEADER_CHECK(FSP__LIBC__LIBC_H)
+
+#if 0
+#pragma message "content of INT_MAX: " STR(INT_MAX)
+#pragma message "content of INT32_MAX: " STR(INT32_MAX)
+#pragma message "content of UINT_MAX: " STR(UINT_MAX)
+#pragma message "content of UINT32_MAX: " STR(UINT32_MAX)
+#pragma message "content of LONG_MAX: " STR(LONG_MAX)
+#pragma message "content of size_t: " STR(__SIZE_TYPE__)
+#pragma message "content of sizeof(uintptr_t): " STR(sizeof(uintptr_t))
+#pragma message "content of sizeof(uint32_t): " STR(sizeof(uint32_t))
+#pragma message "content of sizeof(unsigned long): " STR(sizeof(unsigned long))
+#pragma message "content of __LONG_MAX__: " STR(__LONG_MAX__)
+#pragma message "content of UINTPTR_MAX: " STR(UINTPTR_MAX)
+#endif
+
+#define BASE_ADDR32	0x12345678U
+#define BASE_ADDR64	0x1234567890UL
+#define OFFSET_32	0x05050505U
+
+/* Prototypes */
+void     nvgpu_diag(void);
+uint32_t r32(uintptr_t addr);
+void     w32(uintptr_t addr, uint32_t data);
+uint32_t r32o(uintptr_t addr, uint32_t offset);
+void     w32o(uintptr_t addr, uint32_t offset, uint32_t data);
+uint64_t r64(uintptr_t addr);
+void     w64(uintptr_t addr, uint64_t data);
+uint64_t r64o(uintptr_t addr, uint32_t offset);
+void     w64o(uintptr_t addr, uint32_t offset, uint64_t data);
+
+/* NVGPU-DIAG implementation */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+void nvgpu_diag(void)
+{
+    /* Verify cache */
+    uintptr_t base = BASE_ADDR64;
+    size_t length = 64UL;
+    riscv_addr_type_t address_type = RISCV_ADDR_TYPE_PA;
+
+    icache_invalidate_all();
+    dcache_invalidate_all();
+    dcache_invalidate(&base, length);
+    dcache_invalidate_address_type(&base, length, address_type);
+    cache_invalidate(&base, length);
+
+    /* Verify that 32-bit MMIO functions are MISRA clean */
+    uintptr_t addr32 = BASE_ADDR32;
+    uint32_t  offs32 = OFFSET_32;
+    uint32_t  data32;
+    data32 = r32(addr32);
+    w32(addr32, data32);
+    data32 = r32o(addr32, offs32);
+    w32o(addr32, offs32, data32);
+
+    /* Verify that 64-bit MMIO functions are MISRA clean */
+    uintptr_t addr64 = BASE_ADDR64;
+    uint64_t data64;
+    data64 = r64(addr64);
+    w64(addr64, data64);
+    data64 = r64o(addr64, offs32);
+    w64o(addr64, offs32, data64);
+
+    /* Verify that io driver functions are MISRA clean */
+    uint32_t ioAddr32 = BASE_ADDR32;
+    uint32_t ioData32;
+
+    ioData32 = local_read(ioAddr32);
+    local_write(ioAddr32, ioData32);
+#if (defined(NVRISCV_HAS_CSB_MMIO) && (NVRISCV_HAS_CSB_MMIO==1))
+    ioData32 = csb_read(ioAddr32);
+    csb_write(ioAddr32, ioData32);
+#endif
+#if (defined(NVRISCV_HAS_PRI) && (NVRISCV_HAS_PRI==1))
+#if (defined(NVRISCV_HAS_CSB_OVER_PRI) && (NVRISCV_HAS_CSB_OVER_PRI==1))
+    ioData32 = csb_read(ioAddr32);
+    csb_write(ioAddr32, ioData32);
+#endif
+    ioData32 = pri_read(ioAddr32);
+    pri_write(ioAddr32, ioData32);
+    ioData32 = falcon_read(ioAddr32);
+    falcon_write(ioAddr32, ioData32);
+    ioData32 = riscv_read(ioAddr32);
+    riscv_write(ioAddr32, ioData32);
+#endif
+
+    /* Verify that io dio driver functions are MISRA clean */
+#if NVRISCV_HAS_DIO_SE
+    uint32_t io_dio_se_addr32 = BASE_ADDR32;
+    uint32_t io_dio_se_data32 = 0U;
+    DIO_PORT io_dio_se_port = { .dio_type=DIO_TYPE_SE, .port_idx=0U };
+    if (dio_read_write(io_dio_se_port, DIO_OPERATION_RD, io_dio_se_addr32, &io_dio_se_data32) != (E_SUCCESS)) {
+        io_dio_se_data32 = 0U;
+    }
+#endif
+
+#if NVRISCV_HAS_DIO_SNIC
+    uint32_t io_dio_snic_addr32 = BASE_ADDR32;
+    uint32_t io_dio_snic_data32 = 0U;
+    DIO_PORT io_dio_snic_port = { .dio_type=DIO_TYPE_SNIC, .port_idx=0U };
+    if (dio_read_write(io_dio_snic_port, DIO_OPERATION_RD, io_dio_snic_addr32, &io_dio_snic_data32) != (E_SUCCESS)) {
+        io_dio_snic_data32 = 0U;
+    }
+#endif
+
+#if NVRISCV_HAS_DIO_FBHUB
+    uint32_t io_dio_fbhub_addr32 = BASE_ADDR32;
+    uint32_t io_dio_fbhub_data32 = 0U;
+    DIO_PORT io_dio_fbhub_port = { .dio_type=DIO_TYPE_FBHUB, .port_idx=0U };
+    if (dio_read_write(io_dio_fbhub_port, DIO_OPERATION_RD, io_dio_fbhub_addr32, &io_dio_fbhub_data32) != (E_SUCCESS)) {
+        io_dio_fbhub_data32 = 0U;
+    }
+#endif
+
+    /* Verify that FENCE wrappers are MISRA clean */
+    riscv_lw_fence_io();
+    riscv_lw_fence_rw();
+    riscv_lw_fence_rwio();
+    riscv_fence_io();
+    riscv_fence_rw();
+    riscv_fence_rwio();
+    riscv_sfence_vma(0xFF,0xFF);
+
+    /* Verify that barrier functions are MISRA clean */
+    barrier_cache_op_complete();
+    barrier_memory_order();
+    barrier_memory_complete();
+    barrier_instruction_synchronization();
+
+    /* Verify that shutdown helper functions are MISRA clean */
+    riscv_panic();
+    riscv_shutdown();
+
+    /* Verify libc functions */
+    const uint8_t s1[3] = {1,1,1};
+    uint8_t s2[3] = {1,1,1};
+
+    if (memcmp(s1, s1, sizeof(*s1)/sizeof(char)) == 0)
+    {
+        s2[0] = 0;
+    }
+    (void) memcpy(s2, s1, sizeof(*s1)/sizeof(char));
+    (void) memset(s2, 0, sizeof(*s2)/sizeof(char));
+
+    /* Stack Smashing Protection */
+    error_t ssp_generate_result;
+    ssp_generate_result = ssp_generate_and_set_canary_with_init();
+    ssp_generate_result = ssp_generate_and_set_canary();
+    if (ssp_generate_result == E_SUCCESS)
+    {
+        (void) ssp_get_canary();
+        ssp_set_canary(0x1234);
+    }
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+uint32_t r32(uintptr_t addr)
+{
+    return ioread32(addr);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+uint32_t r32o(uintptr_t addr, uint32_t offset)
+{
+    return ioread32_offset(addr, offset);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+void w32(uintptr_t addr, uint32_t data)
+{
+    iowrite32(addr, data);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+void w32o(uintptr_t addr, uint32_t offset, uint32_t data)
+{
+    iowrite32_offset(addr, offset, data);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+uint64_t r64(uintptr_t addr)
+{
+    return ioread64(addr);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+uint64_t r64o(uintptr_t addr, uint32_t offset)
+{
+    return ioread64_offset(addr, offset);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+void w64(uintptr_t addr, uint64_t data)
+{
+    iowrite64(addr, data);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "")
+void w64o(uintptr_t addr, uint32_t offset, uint64_t data)
+{
+    iowrite64_offset(addr, offset, data);
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/adcc/adcc.c b/spe-freertos-bsp/fsp/source/drivers/adcc/adcc.c
new file mode 100644
index 0000000..4dce86c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/adcc/adcc.c
@@ -0,0 +1,431 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                   // for bool
+#include <stdint.h>                    // for uint32_t, uint8_t, UINT32_...
+#include <string.h>                    // for NULL
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>            // for CT_ASSERT
+#include <soc-common/hw-const.h>       // IWYU pragma: keep
+
+/* Hardware headers */
+//#include <aradcc.h>                  // for ADCC_CTL0_0, ADCC_TIMING_CTL0_0...
+
+/* Late FSP headers */
+#include <error/common-errors.h>       // for error_t, E_SUCCESS
+#include <misc/attributes.h>           // for UNUSED
+#include <misc/nvrm_drf.h>             // NV_DRF_* macros
+#include <reg-access/reg-access.h>     // for readl_base_offset, writel_base_of...
+#include <misc/bitops.h>               // for BIT, bit_number
+#include <clk/clk-tegra.h>             // for tegra_clk_enable, ...
+#include <soc-common/clk-tegra-hw.h>   // for tegra_clk_adcc_os_undiv, ...
+
+/* Module specific headers */
+#include <adcc/adcc.h>                 // for adcc_init, adcc_start_scan...
+#include <adcc/adcc-errors.h>          // for E_ADCC_NULL_PTR, E_ADCC_...
+#include <adcc/adcc-priv.h>            // for struct adcc_id
+#include <adcc/sections-adcc.h>        // Immune from CT_ASSERT protection
+
+#define ADCC_CTL0_0         0x00UL
+#define ADCC_TIMING_CTL0_0  0x04UL
+#define ADCC_SCAN_SEL_0     0x08UL
+#define ADCC_SCAN_WINDOW_0  0x0CUL
+#define ADCC_CH0_SAMPLE_0   0x10UL
+#define ADCC_CH_OFFSET      0x04UL
+#define ADCC_CTL1_0         0x2CUL
+
+#define ADCC_SMPL_VALID     BIT(12U)
+#define ADCC_SMPL_VAL_MSK   0x3FFUL
+#define ADCC_SCAN_EN        BIT(0U)
+#define ADCC_SCAN_SEL_MSK   0x3FUL
+#define ADCC_TMG_CTL_MSK    0xFFFFUL
+#define ADC_CONV_CYC_SHFT   28U
+#define ADCC_PD             BIT(31U)
+#define ADCC_CONT           0UL
+#define ADCC_ONE_SHOT       BIT(1U)
+#define ADCC_WAIT_TIME      0x45UL
+#define ADCC_CH_SZ_MASK     0x00FFFFFFUL
+#define ADC_WAIT_SEL_SHFT   0x8U
+
+static bool adcc_inited = false;
+static uint32_t wait_time = 64U;
+
+static inline uint32_t
+adcc_readl(const struct adcc_id * const id,
+           uint32_t offset)
+{
+    return readl_base_offset(id->base_addr, offset);
+}
+
+static inline void
+adcc_writel(const struct adcc_id * const id,
+            uint32_t val,
+            uint32_t offset)
+{
+    writel_base_offset(val, id->base_addr, offset);
+}
+
+static inline void
+adcc_reset_chans(const struct adcc_id *id)
+{
+    uint32_t i;
+    uint32_t val = 0UL;
+    uint32_t ch_base;
+
+    for (i = 0UL; i <= ADCC_NCHANS; i++) {
+        ch_base = ADCC_CH0_SAMPLE_0 + (i * ADCC_CH_OFFSET);
+        val = adcc_readl(id, ch_base);
+        val &= ~ADCC_SMPL_VALID;
+        adcc_writel(id, val, ch_base);
+    }
+}
+
+static void
+adcc_configure_control_regs(const struct adcc_id *id,
+                            const uint32_t enabled_chans)
+{
+    uint32_t val;
+
+    val = enabled_chans & ADCC_SCAN_SEL_MSK;
+    adcc_writel(id, val, ADCC_SCAN_SEL_0);
+}
+
+SECTION_ADCC_TEXT static void
+adcc_configure_scan_mode(const struct adcc_id *id, bool continuous)
+{
+    uint32_t mode;
+
+    mode = continuous ? ADCC_CONT : ADCC_ONE_SHOT;
+    adcc_writel(id, mode, ADCC_CTL0_0);
+}
+
+SECTION_ADCC_TEXT static uint32_t
+adcc_get_wait_time(const struct adcc_id *id,
+                   uint32_t sampling_dur)
+{
+    uint32_t val = 0x0U;
+
+    switch (sampling_dur) {
+        case 16U:
+            val = 0x0U;
+            break;
+        case 32U:
+            val = 0x0U;
+            break;
+        case 64U:
+            val = 0x0U;
+            break;
+        case 128U:
+            wait_time = 128U;
+            val = 0x1U;
+            break;
+        default:
+            break;
+    }
+
+    return val;
+}
+
+SECTION_ADCC_TEXT static uint32_t
+adcc_get_conv_cycle(const struct adcc_id *id,
+                    uint32_t sampling_dur)
+{
+    uint32_t val = 0x1U;
+
+    switch (sampling_dur) {
+        case 16U:
+            val = 0x0U;
+            break;
+        case 32U:
+            val = 0x1U;
+            break;
+        case 64U:
+            val = 0x2U;
+            break;
+        case 128U:
+            val = 0x3U;
+            break;
+        default:
+            break;
+    }
+
+    return val;
+}
+
+SECTION_ADCC_TEXT static void
+adcc_configure_pad_ctl(const struct adcc_id *id,
+                       const struct adcc_conf *conf)
+{
+    uint32_t val;
+    uint32_t conv_cycles;
+
+    /* program the conversion cycles aka paramter C in the IAS */
+    val = adcc_readl(id, ADCC_CTL1_0);
+    conv_cycles = adcc_get_conv_cycle(id, conf->sampling_dur);
+    val |= conv_cycles << ADC_CONV_CYC_SHFT;
+    val |= adcc_get_wait_time(id, conf->sampling_dur) << ADC_WAIT_SEL_SHFT;
+    adcc_writel(id, val, ADCC_CTL1_0);
+
+    /* program init wait time */
+    val = 2U + (wait_time + 3U) * 1U;
+    adcc_writel(id, val, ADCC_TIMING_CTL0_0);
+
+    /* program the averaging window of samples */
+    val = conf->avg_window & ADCC_CH_SZ_MASK;
+    adcc_writel(id, val, ADCC_SCAN_WINDOW_0);
+}
+
+SECTION_ADCC_TEXT static void
+adcc_clear_power_down(const struct adcc_id *id)
+{
+    uint32_t val;
+
+    val = adcc_readl(id, ADCC_CTL0_0);
+    val &= ~ADCC_PD;
+    adcc_writel(id, val, ADCC_CTL0_0);
+}
+
+SECTION_ADCC_TEXT static error_t
+adcc_configure_clk_rst(const struct adcc_id *id, uint32_t clk_src)
+{
+    error_t ret;
+    const struct tegra_clk  *clk;
+
+    switch (clk_src) {
+        case ADCC_CLK_SRC_PLLP:
+            clk = tegra_clk_adcc_pll_p;
+            ret = tegra_clk_set_rate(clk, 40000000);
+            if (ret != E_SUCCESS) {
+                ret = E_ADCC_CLK_EN;
+                goto out;
+            }
+            break;
+        case ADCC_CLK_SRC_OSC_UNDIV:
+        default:
+            clk = tegra_clk_adcc_osc_undiv;
+            break;
+    }
+
+    ret = tegra_clk_enable(clk);
+    if (ret != E_SUCCESS) {
+        ret = E_ADCC_CLK_EN;
+        goto out;
+    }
+
+    ret = tegra_clk_reset_pulse(id->rst, 2U);
+    if (ret != E_SUCCESS) {
+        ret = E_ADCC_CLK_RST;
+    }
+
+out:
+    return ret;
+}
+
+SECTION_ADCC_TEXT error_t
+adcc_read_data(const struct adcc_id *id,
+               struct adcc_data *data)
+{
+    error_t   ret = E_SUCCESS;
+    uint32_t  ch_base;
+    uint32_t  val;
+    uint32_t  chan;
+    uint32_t  chans;
+
+    if (id == NULL || data == NULL) {
+        ret = E_ADCC_NULL_PTR;
+        goto out;
+    }
+
+    if (!adcc_inited) {
+        ret = E_ADCC_NO_INIT;
+        goto out;
+    }
+
+    chans = adcc_readl(id, ADCC_SCAN_SEL_0) & ADCC_SCAN_SEL_MSK;
+    data->enabled_chans = chans;
+
+    /*
+     * VLD bit is set for enabled channels in order. Instead of reading
+     * every channel's VLD bit, read the last channel of the selected
+     * channels. If this indicates VLD, rest of the channels are also
+     * expected to as the HW sets them in order.
+     */
+    chan = 31U - __builtin_clz(chans);
+    ch_base = ADCC_CH0_SAMPLE_0 + (chan * ADCC_CH_OFFSET);
+    do {
+        val = adcc_readl(id, ch_base);
+    } while ((val & ADCC_SMPL_VALID) == 0UL);
+
+    /* fetch all enabled channel samples */
+    while (chans != 0UL) {
+        chan = bit_number(chans);
+        ch_base = ADCC_CH0_SAMPLE_0 + (chan * ADCC_CH_OFFSET);
+        val = adcc_readl(id, ch_base);
+        data->ch_data[chan] = val & ADCC_SMPL_VAL_MSK;
+        val &= ~ADCC_SMPL_VALID;
+        adcc_writel(id, val, ch_base);
+        chans &= ~BIT(chan);
+    }
+
+out:
+    return ret;
+}
+
+SECTION_ADCC_TEXT error_t
+adcc_read_chan_data(const struct adcc_id *id,
+                    uint32_t chan,
+                    uint32_t *data)
+{
+    error_t   ret = E_SUCCESS;
+    uint32_t  ch_base;
+    uint32_t  val;
+
+    if (id == NULL) {
+        ret = E_ADCC_NULL_PTR;
+        goto out;
+    }
+
+    if (!adcc_inited) {
+        ret = E_ADCC_NO_INIT;
+        goto out;
+    }
+
+    if (chan >= ADCC_NCHANS) {
+        ret = E_ADCC_INVALID_CHAN;
+        goto out;
+    }
+
+    val = adcc_readl(id, ADCC_SCAN_SEL_0) & ADCC_SCAN_SEL_MSK;
+    if ((val & BIT(chan)) == 0UL) {
+        ret = E_ADCC_CHAN_NOT_ENABLED;
+        goto out;
+    }
+
+    ch_base = ADCC_CH0_SAMPLE_0 + (chan * ADCC_CH_OFFSET);
+    do {
+        val = adcc_readl(id, ch_base);
+    } while ((val & ADCC_SMPL_VALID) == 0UL);
+    *data = val & ADCC_SMPL_VAL_MSK;
+    val &= ~ADCC_SMPL_VALID;
+    adcc_writel(id, val, ch_base);
+
+out:
+    return ret;
+}
+
+SECTION_ADCC_TEXT error_t
+adcc_stop_scan(const struct adcc_id *id)
+{
+    error_t   ret = E_SUCCESS;
+    uint32_t  ctl_reg;
+
+    if (id == NULL) {
+        ret = E_ADCC_NULL_PTR;
+        goto out;
+    }
+
+    if (!adcc_inited) {
+        ret = E_ADCC_NO_INIT;
+        goto out;
+    }
+
+    ctl_reg = adcc_readl(id, ADCC_CTL0_0);
+    ctl_reg &= ~ADCC_SCAN_EN;
+    adcc_writel(id, ctl_reg, ADCC_CTL0_0);
+    /* FIXME: Use a timeout based and return timed out error below */
+    do {
+        ctl_reg = adcc_readl(id, ADCC_CTL0_0);
+    } while ((ctl_reg & ADCC_SCAN_EN) != 0UL);
+
+out:
+    return ret;
+}
+
+SECTION_ADCC_TEXT error_t
+adcc_start_scan(const struct adcc_id *id)
+{
+    error_t   ret = E_SUCCESS;
+    uint32_t  ctl_reg;
+
+    if (id == NULL) {
+        ret = E_ADCC_NULL_PTR;
+        goto out;
+    }
+
+    if (!adcc_inited) {
+        ret = E_ADCC_NO_INIT;
+        goto out;
+    }
+
+    adcc_reset_chans(id);
+    ctl_reg = adcc_readl(id, ADCC_CTL0_0);
+    ctl_reg |= ADCC_SCAN_EN;
+    adcc_writel(id, ctl_reg, ADCC_CTL0_0);
+
+out:
+    return ret;
+}
+
+SECTION_ADCC_INIT_TEXT error_t
+adcc_init(const struct adcc_id *id,
+          const struct adcc_conf *conf)
+{
+    error_t   ret = E_SUCCESS;
+    uint32_t  max_chan;
+    uint32_t  enabled_chans;
+
+    if (id == NULL) {
+        ret = E_ADCC_NULL_PTR;
+        goto out;
+    }
+
+    ret = adcc_configure_clk_rst(id, conf->clk_src);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    enabled_chans = conf->enabled_chans;
+    max_chan = 31U - __builtin_clz(enabled_chans);
+    if (max_chan >= ADCC_NCHANS) {
+        ret = E_ADCC_INVALID_PARAM;
+        goto out;
+    }
+
+    adcc_clear_power_down(id);
+    adcc_configure_pad_ctl(id, conf);
+    adcc_configure_scan_mode(id, !conf->mode);
+    adcc_reset_chans(id);
+    adcc_configure_control_regs(id, enabled_chans);
+
+    adcc_inited = true;
+
+out:
+    return ret;
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/adcc/module-adcc-nosafety-config.mk b/spe-freertos-bsp/fsp/source/drivers/adcc/module-adcc-nosafety-config.mk
new file mode 100644
index 0000000..2d12e45
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/adcc/module-adcc-nosafety-config.mk
@@ -0,0 +1,41 @@
+#
+# Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-adcc-nosafety-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-osa*.mk' files.
+MODULE_ADCC_NOSAFETY_CONFIG        := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_ADCC_NOSAFETY_DEPENDS       := SOC CLUSTER CPL OSA FSP_COMMON
+$(foreach _,$(MODULE_ADCC_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_ADCC_NOSAFETY_SOURCE_DIR     = $(FSP_COMMON_REPO)/drivers/adcc
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_ADCC_NOSAFETY_INCLUDES       =
diff --git a/spe-freertos-bsp/fsp/source/drivers/adcc/module-adcc-nosafety.mk b/spe-freertos-bsp/fsp/source/drivers/adcc/module-adcc-nosafety.mk
new file mode 100644
index 0000000..deb4a24
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/adcc/module-adcc-nosafety.mk
@@ -0,0 +1,63 @@
+#
+# Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-adcc-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_ADCC_NOSAFETY_NAME          := ADCC_NOSAFETY
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_ADCC_NOSAFETY_DEFINED       := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_ADCC_NOSAFETY_DEPENDS       := ADCC_NOSAFETY SOC CPL OSA
+$(foreach _,$(CONFIG_ADCC_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_ADCC_NOSAFETY_C_SRC          =
+MODULE_ADCC_NOSAFETY_C_SRC         += $(MODULE_ADCC_NOSAFETY_SOURCE_DIR)/adcc.c
+MODULE_ADCC_NOSAFETY_C_SRC         += $(CPL_SOC_IDS)/adcc-ids.c
+
+#
+# Assembly source
+MODULE_ADCC_NOSAFETY_ASM_SRC        =
+
+#
+# Special C Flags
+MODULE_ADCC_NOSAFETY_C_FLAGS        =
+
+#
+# Special ASM Flags
+MODULE_ADCC_NOSAFETY_ASM_FLAGS      =
diff --git a/spe-freertos-bsp/fsp/source/drivers/aodmic/module-aodmic-nosafety-config.mk b/spe-freertos-bsp/fsp/source/drivers/aodmic/module-aodmic-nosafety-config.mk
new file mode 100644
index 0000000..0b7e3d0
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/aodmic/module-aodmic-nosafety-config.mk
@@ -0,0 +1,54 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-aodmic-nosafety-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to
+#   VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_AODMIC_NOSAFETY_CONFIG                := 1
+
+#
+# Define a something similar to header guard protection...for makefiles
+# instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_AODMIC_NOSAFETY_DEFINED               := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_AODMIC_NOSAFETY_DEPENDS               := SOC CLUSTER CPL GPCDMA
+$(foreach _,$(MODULE_AODMIC_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_AODMIC_NOSAFETY_DRIVERS_DIR            = $(FSP_COMMON_REPO)/drivers/aodmic
+MODULE_AODMIC_NOSAFETY_SOURCE_DIR             = $(MODULE_AODMIC_NOSAFETY_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_AODMIC_NOSAFETY_INCLUDES               =
diff --git a/spe-freertos-bsp/fsp/source/drivers/aodmic/module-aodmic-nosafety.mk b/spe-freertos-bsp/fsp/source/drivers/aodmic/module-aodmic-nosafety.mk
new file mode 100644
index 0000000..16cedcd
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/aodmic/module-aodmic-nosafety.mk
@@ -0,0 +1,65 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-aodmic-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to
+#   VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_AODMIC_NOSAFETY_NAME                  := AODMIC_NOSAFETY
+
+#
+# Define a something similar to header guard protection...for makefiles
+# instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_AODMIC_NOSAFETY_DEFINED               := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_AODMIC_NOSAFETY_DEPENDS               := AODMIC_NOSAFETY SOC CPL GPCDMA
+$(foreach _,$(CONFIG_AODMIC_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_AODMIC_NOSAFETY_C_SRC                  =
+MODULE_AODMIC_NOSAFETY_C_SRC                 += $(MODULE_AODMIC_NOSAFETY_DRIVERS_DIR)/tegra-aodmic.c
+MODULE_AODMIC_NOSAFETY_C_SRC                 += $(CPL_SOC_IDS)/aodmic-tegra-ids.c
+MODULE_AODMIC_NOSAFETY_C_SRC                 += $(CPL_SOC_PORT)/aodmic-port.c
+
+#
+# Assembly source
+MODULE_AODMIC_NOSAFETY_ASM_SRC                =
+
+#
+# Special C Flags
+MODULE_AODMIC_NOSAFETY_C_FLAGS                =
+
+#
+# Special ASM Flags
+MODULE_AODMIC_NOSAFETY_ASM_FLAGS              =
diff --git a/spe-freertos-bsp/fsp/source/drivers/aodmic/tegra-aodmic.c b/spe-freertos-bsp/fsp/source/drivers/aodmic/tegra-aodmic.c
new file mode 100644
index 0000000..b4b8dd9
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/aodmic/tegra-aodmic.c
@@ -0,0 +1,553 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                    // for true, false
+#include <stddef.h>                     // for NULL
+#include <stdint.h>                     // for uint32_t, uint8_t, int32_t
+                                        // IWYU pragma: no_include <errno.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+#include <misc/nvrm_drf.h>              // for NV_FLD_SET_DRF_DEF, NV_DRF_DEF
+
+/* Hardware headers */
+#include <araodmic.h>
+
+/* Late FSP headers */
+#include <error/common-errors.h>        // for MODULE_ID_AODMIC, E_SUCCESS
+#include <osa/rtos-values.h>            // for rtosPASS, rtosFALSE
+#include <osa/rtos-queue.h>             // for rtosQueueReceive, rtosQueueCr...
+#include <osa/rtos-semaphore.h>         // for rtosSemaphoreRelease, rtosSem...
+#include <osa/rtos-task.h>              // for rtosTaskYieldFromISR
+#include <cpu/type-conversion.h>        // for fsp_c_u32_ptr_to_u64
+#include <gpcdma/gpcdma.h>              // for gpcdma_xfer, gpcdma_abort
+#include <misc/macros.h>                // for END_RFD_BLOCK, START_RFD_BLOCK
+#include <reg-access/reg-access.h>      // for readl, writel
+
+/* Module-specific FSP headers */
+#include <aodmic/aodmic-errors.h>       // for E_AODMIC_NULL_POINTER, E_AODM...
+#include <aodmic/sections-aodmic.h>     // for SECTION_AODMIC_...
+#include <aodmic/tegra-aodmic-priv.h>   // for tegra_aodmic_ctlr, tegra_aodm...
+#include <aodmic/tegra-aodmic.h>        // for tegra_aodmic_config, TEGRA_AO...
+#include <port/aodmic-port.h>           // for aodmic_port_clock_disable
+#include <processor/tegra-aodmic-hw.h>  // for AODMIC_GPCDMA_REQ_SEL
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx")
+CT_ASSERT(FSP__MISC__NVRM_DRF_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_VALUES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_QUEUE_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_SEMAPHORE_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__TYPE_CONVERSION_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPCDMA__GPCDMA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__AODMIC__AODMIC_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__AODMIC__TEGRA_AODMIC_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__AODMIC__TEGRA_AODMIC_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PORT__AODMIC_PORT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__TEGRA_AODMIC_HW_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx")
+
+SECTION_AODMIC_TEXT static inline uint32_t
+aodmic_readl(struct tegra_aodmic_ctlr *ctlr,
+             uint32_t offset)
+{
+    return readl(ctlr->id.base_addr + offset);
+}
+
+SECTION_AODMIC_TEXT static inline void
+aodmic_writel(struct tegra_aodmic_ctlr *ctlr,
+              uint32_t value,
+              uint32_t offset)
+{
+    writel(value, ctlr->id.base_addr + offset);
+}
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx")
+
+/* Callback from GPCDMA upon completion of transfer */
+SECTION_AODMIC_TEXT static void
+tegra_aodmic_gpcdma_callback(void *callback_param,
+                             dma_status status)
+{
+    struct tegra_aodmic_ctlr *ctlr;
+    rtosError free_buf_avail;
+    rtosBool higher_prio_task_woken = rtosFALSE;
+    uint64_t filled_buf;
+
+    ctlr = (struct tegra_aodmic_ctlr *)callback_param;
+
+    /* Address of filled buffer */
+    filled_buf = ctlr->dma_xfer.dst_addr;
+
+    /* Next write position */
+    ctlr->free_pos = (ctlr->free_pos + 1u) % ctlr->num_periods;
+    ctlr->dma_xfer.dst_addr = fsp_c_u32_ptr_to_u64((uint32_t *)(ctlr->data +
+                                (ctlr->free_pos * ctlr->period_bytes)));
+
+    /* If reset is already flagged, then wait for it to clear */
+    if (ctlr->reset) {
+        ctlr->xrun_cnt++;
+        goto out;
+    }
+
+    /* Acquire next free buffer */
+    free_buf_avail = rtosSemaphoreAcquireFromISR(ctlr->rtosSemaphore_free_buf,
+                        &higher_prio_task_woken);
+
+    /* No free buffer indicates overflow */
+    if (free_buf_avail != rtosPASS) {
+        ctlr->reset = true; /* flag for buffer reset */
+        ctlr->overflow_count++;  /* log overflow */
+    }
+
+    /* Post available buffer for consumption */
+    rtosQueueSendToBackFromISR(ctlr->rtosQueue_filled_buf, &filled_buf,
+                                &higher_prio_task_woken);
+
+    rtosTaskYieldFromISR(higher_prio_task_woken);
+
+out:
+    return;
+}
+
+/**
+ * @brief open and initialize AODMIC instance
+ *
+ * @pre gpcdma_init() has been called
+ *
+ * @param[in] ctlr:        AODMIC controller instance
+ * @param[in] config:      Configuration structure
+ *
+ * @retval E_SUCCESS                     indicates success
+ * @retval E_AODMIC_NULL_POINTER         indicates NULL pointer was passed
+ * @retval E_AODMIC_INVALID_SAMPLE_RATE  invalid sample rate
+ * @retval E_AODMIC_INVALID_CHANNELS     invalid channel configuration
+ * @retval E_AODMIC_INVALID_SAMPLE_WIDTH invalid sample width
+ * @retval E_AODMIC_INVALID_PERIOD       invalid period
+ * @retval E_AODMIC_MEM_ALLOC_FAILURE    gpcdma_buf_size too small
+ * @retval E_AODMIC_SEM_CREATE_FAILURE   failed rtos object creation
+ */
+SECTION_AODMIC_INIT_TEXT error_t
+tegra_aodmic_open(struct tegra_aodmic_ctlr *ctlr,
+                  const struct tegra_aodmic_config *config)
+{
+    uint32_t osr, num_channels, period_bytes;
+    uint32_t ctrl_reg, fifo_ctrl_reg, dbg_ctrl_reg, enable_reg;
+    error_t ret_val = E_SUCCESS;
+
+    if ((config == NULL) || (ctlr == NULL)) {
+        ret_val = E_AODMIC_NULL_POINTER;
+        goto out;
+    }
+
+    /* Initialize memory pointers in ctlr to NULL */
+    ctlr->data                   = NULL;
+    ctlr->rtosSemaphore_free_buf = NULL;
+    ctlr->rtosQueue_filled_buf   = NULL;
+
+    if (config->gpcdma_buf == NULL) {
+        ret_val = E_AODMIC_NULL_POINTER;
+        goto out;
+    }
+
+    if (config->num_periods < 2UL) {
+        ret_val = E_AODMIC_CONFIGURATION_NA;
+        goto out;
+    }
+
+    /* Setup clock as per sample rate configuration */
+    /* Clock = OSR * sample_rate                    */
+    switch (config->sample_rate) {
+    case TEGRA_AODMIC_RATE_8KHZ:
+    case TEGRA_AODMIC_RATE_16KHZ:
+    case TEGRA_AODMIC_RATE_44KHZ:
+    case TEGRA_AODMIC_RATE_48KHZ:
+        break;
+    default:
+        ret_val = E_AODMIC_INVALID_SAMPLE_RATE;
+        goto out;
+    }
+    ctlr->sample_rate = (uint32_t)config->sample_rate;
+    /* OSR is tied to OSR64 for AODMIC */
+    osr = 1u << (AODMIC_CTRL_0_OSR_OSR64 + 6u);
+    ret_val = aodmic_port_clock_set_rate(ctlr->id.aodmic_hw_handle,
+                                        (osr * ctlr->sample_rate));
+    if (ret_val != E_SUCCESS) {
+        goto out;
+    }
+
+    ret_val = aodmic_port_clock_reset_config(ctlr->id.aodmic_hw_handle);
+    if (ret_val != E_SUCCESS) {
+        goto out;
+    }
+
+    /* Read control register */
+    ctrl_reg = aodmic_readl(ctlr, AODMIC_CTRL_0);
+
+    /* Setup channel configuration in control register */
+    switch (config->channel_config) {
+    case TEGRA_AODMIC_CHANNEL_MONO_LEFT:
+        num_channels = 1;
+        ctrl_reg =
+            NV_FLD_SET_DRF_DEF(AODMIC, CTRL,
+                    CHANNEL_SELECT, LEFT, ctrl_reg);
+        break;
+    case TEGRA_AODMIC_CHANNEL_MONO_RIGHT:
+        num_channels = 1;
+        ctrl_reg =
+            NV_FLD_SET_DRF_DEF(AODMIC, CTRL,
+                    CHANNEL_SELECT, RIGHT, ctrl_reg);
+        break;
+    case TEGRA_AODMIC_CHANNEL_STEREO:
+        num_channels = 2;
+        ctrl_reg =
+            NV_FLD_SET_DRF_DEF(AODMIC, CTRL,
+                    CHANNEL_SELECT, STEREO, ctrl_reg);
+        break;
+
+    default:
+        ret_val = E_AODMIC_INVALID_CHANNELS;
+        goto out;
+    }
+    ctlr->num_channels = num_channels;
+    aodmic_writel(ctlr, ctrl_reg, AODMIC_CTRL_0);
+
+    /* Read sample width configuration */
+    if ((config->sample_width != TEGRA_AODMIC_BITS_PER_SAMPLE_16) &&
+        (config->sample_width != TEGRA_AODMIC_BITS_PER_SAMPLE_32)) {
+            ret_val = E_AODMIC_INVALID_SAMPLE_WIDTH;
+            goto out;
+    }
+    ctlr->samp_bytes = (uint32_t)config->sample_width;
+
+    /* Setup interrupt threshold in FIFO control register */
+    fifo_ctrl_reg = NV_DRF_NUM(AODMIC, APB_FIFO_CTRL, THRESHOLD,
+                    TEGRA_AODMIC_FIFO_THRESHOLD);
+    aodmic_writel(ctlr, fifo_ctrl_reg, AODMIC_APB_FIFO_CTRL_0);
+
+    /* SC filter is enabled by default, enable DCR filter here */
+    dbg_ctrl_reg = aodmic_readl(ctlr, AODMIC_DBG_CTRL_0);
+    dbg_ctrl_reg = NV_FLD_SET_DRF_DEF(AODMIC, DBG_CTRL,
+                        DCR_ENABLE, ENABLE, dbg_ctrl_reg);
+    aodmic_writel(ctlr, dbg_ctrl_reg, AODMIC_DBG_CTRL_0);
+
+    /* Allocate driver buffer */
+    if (((config->period_size % TEGRA_AODMIC_FIFO_THRESHOLD) != 0u) ||
+         (config->num_periods < TEGRA_AODMIC_MIN_ALLOWED_PERIODS)   ||
+         (config->num_periods > AODMIC_MAX_NUM_PERIODS)) {
+            ret_val = E_AODMIC_INVALID_PERIOD;
+            goto out;
+    }
+    /* Driver buffer may be viewed as a queue of    */
+    /* num_periods buffers each of size period_size */
+    period_bytes = config->period_size *
+                    num_channels * TEGRA_AODMIC_WORD_SIZE;
+    if (config->gpcdma_buf_size <  (period_bytes * config->num_periods)) {
+        ret_val = E_AODMIC_MEM_ALLOC_FAILURE;
+        goto out;
+    }
+    ctlr->data = config->gpcdma_buf;
+    ctlr->period_bytes = period_bytes;
+    ctlr->num_periods  = config->num_periods;
+
+    /* Create semaphore for tracking free buffers */
+     rtosSemaphoreCreateCounting(&ctlr->rtosSemaphore_object,
+                ctlr->num_periods /* uxMaxCount */,
+                0             /* uxInitialCount */,
+                (void **)&ctlr->rtosSemaphore_free_buf);
+    if (ctlr->rtosSemaphore_free_buf == NULL) {
+        ret_val = E_AODMIC_SEM_CREATE_FAILURE;
+        goto out;
+    }
+
+    /* Create queue for tracking filled buffers */
+    rtosQueueCreate(ctlr->rtosQueue_object_mem,
+                    rtosQueueSize(AODMIC_MAX_NUM_PERIODS, sizeof(uint64_t)),
+                    ctlr->num_periods /* uxQueueLength */,
+                    sizeof(uint64_t)    /* uxItemSize */,
+                    (void **)&ctlr->rtosQueue_filled_buf);
+    if (ctlr->rtosQueue_filled_buf == NULL) {
+        ret_val = E_AODMIC_SEM_CREATE_FAILURE;
+        goto out;
+    }
+
+    /* Set timeout at queue receive to total buffer duration */
+    ctlr->max_read_timeout =
+        ((config->period_size * ctlr->num_periods * 1000u) / ctlr->sample_rate) /
+        rtosTICK_RATE_MS;
+
+    /* GPCDMA contoller ID and channel for transfer from AODMIC FIFO */
+    ctlr->dma_id       = config->dma_id;
+    ctlr->dma_chan_num = config->dma_chan_num;
+    /*$$  IT IS ASSUMED THAT THE GPCDMA CONTROLLER AND THE SELECTED  $$*/
+    /*$$  CHANNEL ARE INITIALIZED PRIOR TO CALLING THIS FUNCTION     $$*/
+
+    /* Setup DMA transfer parameters */
+    ctlr->dma_xfer.direction      = GPCDMA_XFER_DIR_IO_TO_MEM;
+    ctlr->dma_xfer.bus_width      = GPCDMA_IO_BUS_WIDTH_32;
+    ctlr->dma_xfer.burst_size     = TEGRA_AODMIC_FIFO_THRESHOLD;
+    ctlr->dma_xfer.src_addr       = (uint64_t)ctlr->id.base_addr +
+                                    AODMIC_APB_FIFO_CTRL_RD_DATA_0;
+    ctlr->dma_xfer.src_addr_wrap  = 1;
+    ctlr->dma_xfer.dst_addr       = 0; /* To be filled later */
+    ctlr->dma_xfer.dst_addr_wrap  = 0;
+    ctlr->dma_xfer.continuous     = true;
+    ctlr->dma_xfer.period_len     = period_bytes;
+    ctlr->dma_xfer.xfer_count     = (period_bytes * config->num_periods);
+    ctlr->dma_xfer.en_flow_ctrl   = true;
+    ctlr->dma_xfer.slave_req      = AODMIC_GPCDMA_REQ_SEL;
+    ctlr->dma_xfer.synchronous    = false;
+    ctlr->dma_xfer.timeout        = 0;
+    ctlr->dma_xfer.callback       = tegra_aodmic_gpcdma_callback;
+    ctlr->dma_xfer.callback_param = ctlr;
+
+    /* Enable AODMIC */
+    enable_reg = NV_DRF_DEF(AODMIC, ENABLE, ENABLE, TRUE);
+    aodmic_writel(ctlr, enable_reg, AODMIC_ENABLE_0);
+
+    /* Return success */
+    ctlr->dma_running    = false;
+    ctlr->init_done      = true;
+    ctlr->reset          = true;
+    ctlr->xrun_cnt       = 0;
+    ctlr->overflow_count = 0;
+
+out:
+    if(ret_val != E_SUCCESS) {
+        /* Release all resources and return error */
+        tegra_aodmic_close(ctlr);
+    }
+    return ret_val;
+}
+
+/**
+ * @brief Close AODMIC instance
+ *
+ * @pre none
+ *
+ * @param[in] ctlr:                 AODMIC controller instance
+ *
+ * @retval E_SUCCESS                indicates success
+ * @retval E_AODMIC_NULL_POINTER    detected a null pointer
+ */
+SECTION_AODMIC_TEXT error_t
+tegra_aodmic_close(struct tegra_aodmic_ctlr *ctlr)
+{
+    uint32_t reg_val;
+    error_t ret_val = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret_val = E_AODMIC_NULL_POINTER;
+        goto out;
+    }
+
+    if (ctlr->init_done) {
+        ctlr->init_done = false;
+
+        /* Abort any DMA transfer in progress */
+        gpcdma_abort((const struct gpcdma_id *)ctlr->dma_id, ctlr->dma_chan_num);
+
+        /* Reset AODMIC */
+        reg_val = NV_DRF_DEF(AODMIC, SOFT_RESET, SOFT_RESET, TRUE);
+        aodmic_writel(ctlr, reg_val, AODMIC_SOFT_RESET_0);
+
+        /* Disable AODMIC */
+        reg_val = NV_DRF_DEF(AODMIC, ENABLE, ENABLE, FALSE);
+        aodmic_writel(ctlr, reg_val, AODMIC_ENABLE_0);
+
+        /* Disable AODMIC clock */
+        ret_val = aodmic_port_clock_disable(ctlr->id.aodmic_hw_handle);
+        if (ret_val != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+    /* Release resources that may have been acquired */
+    if (ctlr->rtosQueue_filled_buf != NULL) {
+        rtosQueueDelete(ctlr->rtosQueue_filled_buf);
+        ctlr->rtosQueue_filled_buf = NULL;
+    }
+    if (ctlr->rtosSemaphore_free_buf != NULL) {
+        rtosSemaphoreDelete(ctlr->rtosSemaphore_free_buf);
+        ctlr->rtosSemaphore_free_buf = NULL;
+    }
+
+out:
+    return ret_val;
+}
+
+/**
+ * @brief Read captured samples
+ *
+ * @pre the function tegra_aodmic_open() has been called
+ *
+ * @param[in] ctlr:        AODMIC controller instance
+ * @param[in] count:       number of bytes to capture
+ *
+ * @retval E_SUCCESS                  success
+ * @retval E_AODMIC_NULL_POINTER      detected a null pointer
+ * @retval E_AODMIC_CONFIGURATION_NA  count of 0 not allowed
+ * @retval E_AODMIC_NOT_INITIALIZED   tegra_aodmic_open() not called prior
+ * @retval E_AODMIC_BUF_INVALID       null data pointer
+ * @retval E_AODMIC_READ_TIMEOUT      timeout waiting for queue
+ */
+SECTION_AODMIC_INIT_TEXT error_t
+tegra_aodmic_read(struct tegra_aodmic_ctlr *ctlr,
+                  void *data,
+                  uint32_t count)
+{
+    rtosError status;
+    uint32_t i;
+    uint8_t *write_buf;
+    int32_t pcm_samp;
+    error_t ret_val = E_SUCCESS;
+
+    if (ctlr == NULL){
+        ret_val = E_AODMIC_NULL_POINTER;
+        goto out;
+    }
+
+    if (count == 0u) {
+        ret_val = E_AODMIC_CONFIGURATION_NA;
+        goto out;
+    }
+
+    if (!(ctlr->init_done)) {
+        ret_val = E_AODMIC_NOT_INITIALIZED;
+        goto out;
+    }
+
+    if (data == NULL) {
+        ret_val = E_AODMIC_BUF_INVALID;
+        goto out;
+    }
+    write_buf = data;
+
+    /* Reset buffer queue, which may be at */
+    /* init or due to buffer overflow      */
+    if (ctlr->reset) {
+        /* Drain out any buffers that may already be filled */
+        do {
+            status = rtosQueueReceive(ctlr->rtosQueue_filled_buf,
+                        &ctlr->read_ptr,
+                        0);
+        } while (status == rtosPASS);
+        ctlr->read_ptr      = NULL;
+        ctlr->bytes_to_read = 0;
+
+        /* Setup all buffers as free (for DMA to write) */
+        do {
+            status = rtosSemaphoreRelease(ctlr->rtosSemaphore_free_buf);
+        } while (status == rtosPASS);
+
+        ctlr->xrun_cnt = 0;
+        ctlr->reset = false;
+    }
+
+    if (!(ctlr->dma_running)) {
+        /* Trigger first DMA transfer */
+        ctlr->dma_running = true;
+        ctlr->free_pos = 0;
+        rtosSemaphoreAcquire(ctlr->rtosSemaphore_free_buf, 0);
+        ctlr->dma_xfer.dst_addr = fsp_c_u32_ptr_to_u64(
+                                    (uint32_t *)ctlr->data);
+        ret_val = gpcdma_transfer(
+                    (const struct gpcdma_id *)ctlr->dma_id,
+                    ctlr->dma_chan_num,
+                    &ctlr->dma_xfer);
+        if (ret_val != E_SUCCESS) {
+            ctlr->dma_running = false;
+            goto out;
+        }
+    }
+
+    /* Read PCM data from filled buffers */
+    for (i = 0; i < count; i += ctlr->samp_bytes) {
+        /* If current buffer is exhausted, proceed to next buffer */
+        if (ctlr->bytes_to_read == 0u) {
+            /* Release consumed buffer for writing */
+            if (ctlr->read_ptr != NULL) {
+                rtosSemaphoreRelease(ctlr->rtosSemaphore_free_buf);
+            }
+
+            /* Get next buffer from filled queue */
+            ctlr->read_ptr = NULL;
+            status = rtosQueueReceive(ctlr->rtosQueue_filled_buf,
+                        &ctlr->read_ptr,
+                        ctlr->max_read_timeout);
+            if (status != rtosPASS) {
+                ret_val = E_AODMIC_READ_TIMEOUT;
+                goto out;
+            }
+            ctlr->bytes_to_read = ctlr->period_bytes;
+        }
+
+        /* AODMIC provides 24-bit PCM packed in 32 bits,  */
+        /* Little Endian, aligned to LSB (i.e. bits 23:0) */
+        pcm_samp             = (*((int32_t *)(ctlr->read_ptr))) << 8;
+        ctlr->read_ptr      += TEGRA_AODMIC_WORD_SIZE;
+        ctlr->bytes_to_read -= TEGRA_AODMIC_WORD_SIZE;
+
+        /* Format PCM sample to requested width */
+        switch (ctlr->samp_bytes) {
+        case 2:
+            *((int16_t *)(write_buf + i)) = (int16_t)
+                            (pcm_samp >> 16);
+            break;
+        case 4:
+            *((int32_t *)(write_buf + i)) = pcm_samp;
+            break;
+        default:
+            ret_val = E_AODMIC_INVALID_SAMPLE_RATE;
+            break;
+        }
+    }
+
+out:
+    return ret_val;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/ast/module-ast-config.mk b/spe-freertos-bsp/fsp/source/drivers/ast/module-ast-config.mk
new file mode 100644
index 0000000..03b3f3d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/ast/module-ast-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-ast-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_AST_CONFIG               := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_AST_DEPENDS              := SOC CLUSTER CPL OSA FSP_COMMON
+$(foreach _,$(MODULE_AST_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_AST_DRIVERS_DIR           = $(FSP_COMMON_REPO)/drivers/ast
+MODULE_AST_SOURCE_DIR            = $(MODULE_AST_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_AST_INCLUDES              =
diff --git a/spe-freertos-bsp/fsp/source/drivers/ast/module-ast.mk b/spe-freertos-bsp/fsp/source/drivers/ast/module-ast.mk
new file mode 100644
index 0000000..6c3ea76
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/ast/module-ast.mk
@@ -0,0 +1,63 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-ast.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_AST_NAME                 := AST
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_AST_DEFINED              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_AST_DEPENDS              := AST SOC CPL OSA
+$(foreach _,$(CONFIG_AST_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_AST_C_SRC                 =
+MODULE_AST_C_SRC                += $(MODULE_AST_DRIVERS_DIR)/tegra-ast.c
+MODULE_AST_C_SRC                += $(CPL_SOC_IDS)/ast-tegra-ids.c
+
+#
+# Assembly source
+MODULE_AST_ASM_SRC               =
+
+#
+# Special C Flags
+MODULE_AST_C_FLAGS               =
+
+#
+# Special ASM Flags
+MODULE_AST_ASM_FLAGS             =
diff --git a/spe-freertos-bsp/fsp/source/drivers/ast/tegra-ast.c b/spe-freertos-bsp/fsp/source/drivers/ast/tegra-ast.c
new file mode 100644
index 0000000..6077ea7
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/ast/tegra-ast.c
@@ -0,0 +1,1163 @@
+/*
+ * Copyright (c) 2019-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/* Compiler headers */
+#include <stdint.h>                 // for uint32_t, uint8_t, uint64_t
+#include <stdbool.h>                // for bool, true, false
+#include <string.h>                 // for memset, NULL
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>         // for CT_ASSERT
+#include <soc-common/hw-const.h>    // Must appear before any hwinc files
+
+/* Hardware headers */
+#include <araps_ast.h>              // for APS_AST_CONTROL_0, APS_AST_REGION...
+
+/* Late FSP headers */
+#include <cpu/type-conversion.h>    // for fsp_c_v_ptr_to_uptr, FSP__MISC_...
+#include <debug/assert.h>           // for ASSERT, FSP__DEBUG__ASSERT_H
+#include <error/common-errors.h>    // for E_SUCCESS, error_t
+#include <misc/bitops.h>            // for hilo_to_64, HI32, LOW32, FSP__MIS...
+#include <misc/macros.h>            // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <reg-access/reg-access.h>  // for readl_base_offset, writel_base_of...
+
+/* Module-specific FSP headers */
+#include <ast/ast-errors.h>         // for E_AST_INVALID_INPUT_PARAMETERS
+#include <ast/sections-ast.h>       // Immune from CT_ASSERT protection
+#include <ast/tegra-ast.h>          // for ast_tegra_id, tegra_ast_region_map
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__TYPE_CONVERSION_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ASSERT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__AST__AST_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__AST__TEGRA_AST_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+#define LO_SHIFT APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_SHIFT
+
+#define MAX_VMINDEX            MK_U32_CONST(15)
+#define AST_INSTANCE_R5_INDEX  AST_INSTANCE_0
+#define AST_INSTANCE_DMA_INDEX AST_INSTANCE_1
+#define AST_REGION_BASE        APS_AST_REGION_0_SLAVE_BASE_LO_0
+#define AST_REG(_r_)           ((_r_) - AST_REGION_BASE)
+
+
+/* Special values returned from VMINDEX search */
+#define VMINDEX_PHYSICAL_STREAM_ID (MAX_VMINDEX + MK_U32_CONST(1))
+
+SECTION_AST_TEXT static inline bool
+ast_instance_valid(uint8_t instance_mask)
+{
+    bool        valid           = true;
+    uint8_t     instance;
+
+    instance = instance_mask & AST_INSTANCE_R5_AND_DMA;
+
+    if ((instance == 0U)
+        || ((tegra_ast_get_num_regions() > 8U)
+            && (instance == AST_INSTANCE_R5_AND_DMA))) {
+        valid = false;
+    }
+
+    return valid;
+}
+
+SECTION_AST_TEXT
+static inline uint32_t ast_region_base(uint32_t ast_base,
+                                       uint8_t region)
+{
+    const uint32_t region_stride = APS_AST_REGION_1_MASK_LO_0 -
+                                   APS_AST_REGION_0_MASK_LO_0;
+    INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    return ast_base + AST_REGION_BASE + ((uint32_t)region * region_stride);
+}
+
+SECTION_AST_TEXT
+static inline uint32_t streamid_ctl_reg(uint32_t ast_base,
+                                        uint8_t vmindex)
+{
+    uint32_t ctl_stride = APS_AST_STREAMID_CTL_1 - APS_AST_STREAMID_CTL_0;
+
+    INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    return ast_base + APS_AST_STREAMID_CTL_0 + ((uint32_t)vmindex * ctl_stride);
+}
+
+SECTION_AST_TEXT
+static bool ast_is_global_locked(uint32_t ast_base)
+{
+    bool status = false;
+
+    uint32_t val = readl_base_offset(ast_base, APS_AST_CONTROL_0);
+
+    if (((val & APS_AST_CONTROL_0_Lock_FIELD) >>
+        APS_AST_CONTROL_0_Lock_SHIFT) == MK_U32_CONST(0x01)) {
+        status = true;
+    }
+    return status;
+}
+
+SECTION_AST_TEXT
+bool tegra_ast_is_global_locked(void)
+{
+    return ast_is_global_locked(ast_tegra_id[AST_INSTANCE_R5_INDEX]) ||
+           ast_is_global_locked(ast_tegra_id[AST_INSTANCE_DMA_INDEX]);
+}
+
+SECTION_AST_TEXT
+static error_t ast_get_vmindex(uint32_t ast_base,
+                               uint8_t stream_id,
+                               bool *return_is_enabled,
+                               uint8_t *VMIndex)
+{
+    uint32_t mask = APS_AST_STREAMID_CTL_0_READ_MASK;
+    uint32_t expected_val;
+    uint8_t  free_vmindex = (uint8_t)MAX_VMINDEX + 2U;
+    error_t  err = E_SUCCESS;
+
+    expected_val = (uint32_t)(stream_id & APS_AST_STREAMID_CTL_StreamID_DEFAULT_MASK) <<
+                    APS_AST_STREAMID_CTL_StreamID_SHIFT;
+    expected_val |= APS_AST_STREAMID_CTL_Enable_FIELD;
+
+    for (uint8_t tmpIndex = 0; tmpIndex <= MAX_VMINDEX; tmpIndex++) {
+        uint32_t val = readl(streamid_ctl_reg(ast_base, tmpIndex)) & mask;
+
+        if (val == expected_val) {
+            *return_is_enabled = true;
+            free_vmindex = tmpIndex;
+            goto out;
+        }
+
+        /*
+         * Select last free tmpIndex in order to avoid
+         * collision w/ kernel and bootloader
+         */
+        if ((val & APS_AST_STREAMID_CTL_Enable_FIELD) != MK_U32_CONST(0x1)) {
+            free_vmindex = tmpIndex;
+        }
+    }
+
+    *return_is_enabled = false;
+out:
+    *VMIndex = free_vmindex;
+    if(free_vmindex > VMINDEX_PHYSICAL_STREAM_ID) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_VMINDEX;
+    }
+    return err;
+}
+
+SECTION_AST_TEXT
+static error_t ast_set_streamid(uint32_t ast_base,
+                                uint8_t vmindex,
+                                uint8_t stream_id)
+{
+    uint32_t sid_ctl;
+    uint32_t val;
+    error_t  err = E_SUCCESS;
+
+    /* ast_get_vmindex ensures that ast_base != 0 */
+    sid_ctl = APS_AST_STREAMID_CTL_Enable_FIELD;
+    sid_ctl |= ((uint32_t)(stream_id & APS_AST_STREAMID_CTL_StreamID_DEFAULT_MASK) <<
+               APS_AST_STREAMID_CTL_StreamID_SHIFT);
+    writel(sid_ctl, streamid_ctl_reg(ast_base, vmindex));
+
+    /* Check that write was not blocked */
+    val = readl(streamid_ctl_reg(ast_base, vmindex));
+    if ((val & APS_AST_STREAMID_CTL_READ_MASK) != sid_ctl) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_VMINDEX;
+    }
+
+    return err;
+}
+
+SECTION_AST_TEXT
+static error_t ast_add_streamid(uint32_t ast_base,
+                                uint8_t stream_id)
+{
+    uint8_t VMIndex;
+    error_t err = E_SUCCESS;
+    bool    already_enabled;
+
+    err = ast_get_vmindex(ast_base, stream_id, &already_enabled, &VMIndex);
+    if (err != E_SUCCESS) {
+        goto out;
+    }
+
+    if (already_enabled) {
+        goto out;
+    }
+
+    INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-383, DR: SWE-FSP-004-SWSADR.docx");
+    err = ast_set_streamid(ast_base, VMIndex, stream_id);
+out:
+    return err;
+}
+
+SECTION_AST_TEXT error_t
+tegra_ast_addr_add_streamid(uint8_t stream_id,
+                            uint32_t base)
+{
+    error_t     err = E_SUCCESS;
+
+    if (base == 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    err = ast_add_streamid(base, stream_id);
+    if (err != E_SUCCESS) {
+        goto out;
+    }
+
+  out:
+    return err;
+}
+
+SECTION_AST_TEXT
+error_t tegra_ast_add_streamid(uint8_t stream_id, uint8_t instance_mask)
+{
+    error_t err = E_SUCCESS;
+
+    if (!ast_instance_valid(instance_mask)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    if ((instance_mask & AST_INSTANCE_R5) != 0U) {
+        err = tegra_ast_addr_add_streamid(stream_id,
+                                          ast_tegra_id[AST_INSTANCE_R5_INDEX]);
+        if (err != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+    if ((instance_mask & AST_INSTANCE_DMA) != 0U) {
+        INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-383, DR: SWE-FSP-004-SWSADR.docx");
+        err = tegra_ast_addr_add_streamid(stream_id,
+                                          ast_tegra_id[AST_INSTANCE_DMA_INDEX]);
+    }
+
+out:
+    return err;
+}
+
+SECTION_AST_TEXT
+static void ast_enable_region(uint32_t ast_base,
+                              uint8_t region, uint8_t vmindex,
+                              iova master, uint64_t slave,
+                              uint64_t size)
+{
+    uint32_t region_base = ast_region_base(ast_base, region);
+    uint32_t hi, lo;
+    uint32_t snoopEnable = APS_AST_REGION_0_CONTROL_0_Snoop_DEFAULT_MASK <<
+                           APS_AST_REGION_0_CONTROL_0_Snoop_SHIFT;
+    uint32_t physicalStreamEnable = APS_AST_REGION_0_CONTROL_0_Physical_DEFAULT_MASK <<
+                                    APS_AST_REGION_0_CONTROL_0_Physical_SHIFT;
+    uint32_t tmpIndex = (uint32_t)(vmindex & APS_AST_REGION_0_CONTROL_0_VMIndex_DEFAULT_MASK) <<
+                        APS_AST_REGION_0_CONTROL_0_VMIndex_SHIFT;
+    uint32_t control = 0U;
+
+    /*
+     * PhysicalStreamEnable field of the region control register is RWGL protected.
+     * If the client needs to enable a region with Physical streamID:
+     *   - If PhysicalStreamEnable field is already set to 0x1, no action needed.
+     *   - If PhysicalStreamEnable field is 0x0:
+     *      - If global lock bit is set, region cannot be enabled with physical stream ID and
+     *        error should be returned. This is taken care by the parent API
+     *        tegra_ast_enable_phy_region that checks for the global lock status and region
+     *        PhysicalStreamEnable field.
+     *      - If global lock bit is not set, region can still be enabled with physical streamID
+     *        by setting the PhysicalStreamEnable field
+     * If the client needs to enable a region with non-physical streamID, no need to control the
+     * PhysicalStreamEnable field.
+     */
+    if ((vmindex == VMINDEX_PHYSICAL_STREAM_ID) && !ast_is_global_locked(ast_base)) {
+        control |= physicalStreamEnable;
+    } else {
+        control |= tmpIndex;
+    }
+    control |= snoopEnable;
+    writel_base_offset(control, region_base, AST_REG(APS_AST_REGION_0_CONTROL_0));
+
+    ASSERT(size != 0UL);
+    INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-559, DR: SWE-FSP-048-SWSADR.docx");
+    hi = HI32((uint64_t)(size - 1UL));
+    INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-559, DR: SWE-FSP-048-SWSADR.docx");
+    lo = (LOW32(size - 1UL) >> LO_SHIFT);
+
+    control = (hi & APS_AST_REGION_0_MASK_HI_0_Mask_DEFAULT_MASK) <<
+               APS_AST_REGION_0_MASK_HI_0_Mask_SHIFT;
+    writel_base_offset(control, region_base, AST_REG(APS_AST_REGION_0_MASK_HI_0));
+
+    control = (uint32_t)(lo & APS_AST_REGION_0_MASK_LO_0_Mask_DEFAULT_MASK) <<
+               APS_AST_REGION_0_MASK_LO_0_Mask_SHIFT;
+    writel_base_offset(control, region_base, AST_REG(APS_AST_REGION_0_MASK_LO_0));
+
+    INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-559, DR: SWE-FSP-048-SWSADR.docx");
+    hi = HI32(master);
+    INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-559, DR: SWE-FSP-048-SWSADR.docx");
+    lo = (LOW32(master) >> LO_SHIFT);
+    control = (hi & APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_DEFAULT_MASK) <<
+               APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_SHIFT;
+    writel_base_offset(control, region_base, AST_REG(APS_AST_REGION_0_MASTER_BASE_HI_0));
+
+    control = (uint32_t)(lo & APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_DEFAULT_MASK) <<
+               APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_SHIFT;
+    writel_base_offset(control, region_base, AST_REG(APS_AST_REGION_0_MASTER_BASE_LO_0));
+
+    INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-559, DR: SWE-FSP-048-SWSADR.docx");
+    hi = HI32(slave);
+    INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-559, DR: SWE-FSP-048-SWSADR.docx");
+    lo = (LOW32(slave) >> LO_SHIFT);
+    control = (hi & APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_DEFAULT_MASK) <<
+               APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_SHIFT;
+    writel_base_offset(control, region_base, AST_REG(APS_AST_REGION_0_SLAVE_BASE_HI_0));
+
+    control = (uint32_t)(lo & APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_DEFAULT_MASK) <<
+               APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_SHIFT;
+    control |= APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_FIELD;
+    writel_base_offset(control, region_base, AST_REG(APS_AST_REGION_0_SLAVE_BASE_LO_0));
+}
+
+SECTION_AST_TEXT error_t
+tegra_ast_addr_enable_region(uint8_t region,
+                             uint8_t stream_id,
+                             iova master,
+                             uint64_t slave,
+                             uint64_t size,
+                             uint32_t base)
+{
+    bool     already_enabled;
+    uint8_t  vmindex;
+    error_t  err = E_SUCCESS;
+    uint64_t slave_address_mask = MK_U64_ADDR_CONST(0xFFFFFFFF);
+    uint64_t iova_address_mask = MK_U64_ADDR_CONST(0xFFFFFFFFFF);
+    uint64_t region_size_mask = MK_U64_ADDR_CONST(0xFFF);
+
+    if ((region > MAX_REGION_INDEX) ||
+        ((slave & ~slave_address_mask) != 0U) ||
+        ((master & ~iova_address_mask) != 0U) ||
+        (size == 0U) || ((size - 1U) > slave_address_mask) ||
+        ((size & region_size_mask) != 0U) || ((size & (size - 1U)) != 0U)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    if ((((size - 1UL) & slave) != 0UL) ||
+        (((size - 1UL) & master) != 0UL)) {
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    err = tegra_ast_addr_add_streamid(stream_id, base);
+    if (err != E_SUCCESS) {
+        goto out;
+    }
+
+    err = ast_get_vmindex(base, stream_id, &already_enabled, &vmindex);
+    if (err != E_SUCCESS) {
+        goto out;
+    }
+
+    if (!already_enabled) {
+        /* Setting streamID should also enable the VM */
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_VMINDEX;
+        goto out;
+    }
+
+    ast_enable_region(base, region, vmindex, master, slave, size);
+
+out:
+    return err;
+}
+
+SECTION_AST_TEXT
+error_t tegra_ast_enable_region(uint8_t region, uint8_t stream_id,
+                                iova master, uint64_t slave,
+                                uint64_t size, uint8_t instance_mask)
+{
+    error_t  err = E_SUCCESS;
+
+    if (!ast_instance_valid(instance_mask)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    if ((instance_mask & AST_INSTANCE_R5) != 0U) {
+        err = tegra_ast_addr_enable_region(region, stream_id,
+                                           master, slave, size,
+                                           ast_tegra_id[AST_INSTANCE_R5_INDEX]);
+        if (err != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+    if ((instance_mask & AST_INSTANCE_DMA) != 0U) {
+        err = tegra_ast_addr_enable_region(region, stream_id,
+                                           master, slave, size,
+                                           ast_tegra_id[AST_INSTANCE_DMA_INDEX]);
+        if (err != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+out:
+    return err;
+}
+
+SECTION_AST_TEXT error_t
+tegra_ast_addr_disable_region(uint8_t region,
+                              uint32_t base)
+{
+    uint32_t    region_base;
+    uint32_t    control;
+    error_t     err             = E_SUCCESS;
+
+    if ((region > MAX_REGION_INDEX) || (base == 0U)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    region_base = ast_region_base(base, region);
+    control = readl_base_offset(region_base, AST_REG(APS_AST_REGION_0_SLAVE_BASE_LO_0));
+    control &= ~APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_FIELD;
+    writel_base_offset(control, region_base, AST_REG(APS_AST_REGION_0_SLAVE_BASE_LO_0));
+
+out:
+    return err;
+}
+
+SECTION_AST_TEXT
+error_t tegra_ast_disable_region(uint8_t region, uint8_t instance_mask)
+{
+    error_t err = E_SUCCESS;
+
+    if (!ast_instance_valid(instance_mask)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    if ((instance_mask & AST_INSTANCE_R5) != 0U) {
+        err = tegra_ast_addr_disable_region(region,
+                                            ast_tegra_id[AST_INSTANCE_R5_INDEX]);
+        if (err != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+    if ((instance_mask & AST_INSTANCE_DMA) != 0U) {
+        err = tegra_ast_addr_disable_region(region,
+                                            ast_tegra_id[AST_INSTANCE_DMA_INDEX]);
+        if (err != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+out:
+    return err;
+}
+
+SECTION_AST_TEXT error_t
+tegra_ast_addr_disable_default_region(uint32_t base)
+{
+    error_t     err             = E_SUCCESS;
+
+    if (tegra_ast_get_num_regions() <= 8U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_NOT_SUPPORTED;
+        goto out;
+    }
+
+    if (base == 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    writel(0U, base + AST_DM_REGION_SLAVE_BASE_LO);
+
+out:
+    return err;
+}
+
+SECTION_AST_TEXT
+static error_t ast_get_region_stream_id(uint32_t ast_base,
+                                        uint8_t region,
+                                        uint8_t *streamID)
+{
+    uint32_t region_base = ast_region_base(ast_base, region);
+    uint32_t val;
+    error_t  err = E_SUCCESS;
+    uint8_t  vmindex;
+
+    val = readl_base_offset(region_base, AST_REG(APS_AST_REGION_0_SLAVE_BASE_LO_0));
+
+    if ((val & APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_FIELD) != 0x01U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_REGION_DISABLED;
+        goto out;
+    }
+
+    val = readl_base_offset(region_base, AST_REG(APS_AST_REGION_0_CONTROL_0));
+
+    if ((val & APS_AST_REGION_0_CONTROL_0_Physical_FIELD) != 0U) {
+        /*
+         * Return error code indicating the request is invalid for regions
+         * mapped with physical streamID
+         */
+        err = E_AST_INVALID_PHY_REGION_REQUEST;
+        goto out;
+    }
+
+    INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-559, DR: SWE-FSP-048-SWSADR.docx");
+    vmindex = (uint8_t)((uint32_t)(val & APS_AST_REGION_0_CONTROL_0_VMIndex_FIELD) >>
+               APS_AST_REGION_0_CONTROL_0_VMIndex_SHIFT);
+    val = readl(streamid_ctl_reg(ast_base, vmindex));
+
+    if ((val & APS_AST_STREAMID_CTL_0_Enable_FIELD) != 0x01U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_REGION_STREAMID_DISABLED;
+        goto out;
+    }
+
+    INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-559, DR: SWE-FSP-048-SWSADR.docx");
+    *streamID = (uint8_t)((uint32_t)(val & APS_AST_STREAMID_CTL_0_StreamID_FIELD) >>
+                 APS_AST_STREAMID_CTL_0_StreamID_SHIFT);
+out:
+    return err;
+}
+
+SECTION_AST_TEXT error_t
+tegra_ast_addr_get_region_stream_id(uint8_t region,
+                                    uint8_t *streamID,
+                                    uint32_t base)
+{
+    error_t err = E_SUCCESS;
+
+    if ((base == 0U)
+        || (region > MAX_REGION_INDEX)
+        || (streamID == NULL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    err = ast_get_region_stream_id(base, region, streamID);
+    if (err != E_SUCCESS) {
+        goto out;
+    }
+
+out:
+    return err;
+}
+
+SECTION_AST_TEXT
+error_t tegra_ast_get_region_stream_id(uint8_t region,
+                                       uint8_t *streamID,
+                                       uint8_t instance_mask)
+{
+    error_t err = E_SUCCESS;
+    uint8_t ast_instance = instance_mask & AST_INSTANCE_R5_AND_DMA;
+    uint32_t    ast_base;
+
+    if ((ast_instance == AST_INSTANCE_R5_AND_DMA)
+        || (ast_instance == 0U)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+
+    ast_base = ((ast_instance & AST_INSTANCE_R5) == AST_INSTANCE_R5)
+               ? ast_tegra_id[AST_INSTANCE_R5_INDEX]
+               : ast_tegra_id[AST_INSTANCE_DMA_INDEX];
+
+    INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-383, DR: SWE-FSP-004-SWSADR.docx");
+    err = tegra_ast_addr_get_region_stream_id(region, streamID, ast_base);
+
+out:
+    return err;
+}
+
+SECTION_AST_TEXT
+static error_t ast_get_region_mapping(uint32_t ast_base, uint8_t region,
+                                      struct tegra_ast_region_map *return_region_map)
+{
+    uint32_t region_base = ast_region_base(ast_base, region);
+    uint32_t hi, lo;
+    uint64_t mask;
+    uint8_t  vmindex;
+    error_t  err;
+
+    hi = readl_base_offset(region_base, AST_REG(APS_AST_REGION_0_SLAVE_BASE_HI_0));
+    lo = readl_base_offset(region_base, AST_REG(APS_AST_REGION_0_SLAVE_BASE_LO_0));
+
+    if (return_region_map == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    return_region_map->is_enabled =
+                ((lo & APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_FIELD) == 0x01U);
+
+    lo &= APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_FIELD;
+    return_region_map->slave_base = hilo_to_64(hi, lo);
+
+    hi = readl_base_offset(region_base, AST_REG(APS_AST_REGION_0_MASK_HI_0));
+    lo = readl_base_offset(region_base, AST_REG(APS_AST_REGION_0_MASK_LO_0))
+         | ~APS_AST_REGION_0_MASK_LO_0_READ_MASK;
+
+    mask = hilo_to_64(hi, lo);
+    INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    return_region_map->size = mask + 1U;
+
+    hi = readl_base_offset(region_base, AST_REG(APS_AST_REGION_0_MASTER_BASE_HI_0));
+    lo = readl_base_offset(region_base, AST_REG(APS_AST_REGION_0_MASTER_BASE_LO_0));
+
+    return_region_map->master_base = hilo_to_64(hi, lo);
+
+    vmindex = (uint8_t)(readl_base_offset(region_base, AST_REG(APS_AST_REGION_0_CONTROL_0))
+                         & (APS_AST_REGION_0_CONTROL_0_VMIndex_FIELD >>
+                         APS_AST_REGION_0_CONTROL_0_VMIndex_SHIFT));
+
+    return_region_map->vmindex = vmindex;
+    INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-383, DR: SWE-FSP-004-SWSADR.docx");
+    err = ast_get_region_stream_id(ast_base, region, &return_region_map->stream_id);
+out:
+    return err;
+}
+
+SECTION_AST_TEXT error_t
+tegra_ast_addr_get_region_mapping(uint8_t region,
+                                  struct tegra_ast_region_map *return_region_map,
+                                  uint32_t base)
+{
+    error_t err = E_SUCCESS;
+
+    if ((base == 0U)
+        || (region > MAX_REGION_INDEX)
+        || (return_region_map == NULL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    (void)memset(return_region_map, 0, sizeof(*return_region_map));
+
+    return_region_map->is_phy_region = false;
+
+    INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-383, DR: SWE-FSP-004-SWSADR.docx");
+    err = ast_get_region_mapping(base, region, return_region_map);
+
+    if (err == E_AST_INVALID_PHY_REGION_REQUEST) {
+        return_region_map->is_phy_region = true;
+        err = E_SUCCESS;
+    }
+
+out:
+   return err;
+}
+
+SECTION_AST_TEXT
+error_t tegra_ast_get_region_mapping(uint8_t region,
+                                     struct tegra_ast_region_map *return_region_map,
+                                     uint8_t instance_mask)
+{
+    error_t err = E_SUCCESS;
+    uint8_t ast_instance = instance_mask & AST_INSTANCE_R5_AND_DMA;
+    uint32_t    ast_base;
+
+    if ((ast_instance == AST_INSTANCE_R5_AND_DMA)
+        || (ast_instance == 0U)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    ast_base = ((ast_instance & AST_INSTANCE_R5) == AST_INSTANCE_R5)
+               ? ast_tegra_id[AST_INSTANCE_R5_INDEX]
+               : ast_tegra_id[AST_INSTANCE_DMA_INDEX];
+
+    err = tegra_ast_addr_get_region_mapping(region, return_region_map, ast_base);
+
+    if (err == E_AST_INVALID_PHY_REGION_REQUEST) {
+        return_region_map->is_phy_region = true;
+        err = E_SUCCESS;
+    }
+
+out:
+   return err;
+}
+
+SECTION_AST_TEXT
+iova tegra_ast_map_pointer_to_iova(const struct tegra_ast_region_map *map,
+                                   const void *pointer)
+{
+    return tegra_ast_map_slave_to_iova(map, (uint64_t)(fsp_c_v_ptr_to_uptr(pointer)));
+}
+
+SECTION_AST_TEXT
+uint64_t tegra_ast_get_local_pointer_value(const struct tegra_ast_region_map *map,
+                                           const iova iova_addr)
+{
+    return tegra_ast_map_iova_to_slave(map, iova_addr);
+}
+
+SECTION_AST_TEXT
+iova tegra_ast_map_slave_to_iova(const struct tegra_ast_region_map *map,
+                                 const uint64_t slave)
+{
+    uint64_t mask;
+    iova     addr = IOVA_NULL;
+    uint64_t slave_address_mask = MK_U64_ADDR_CONST(0xFFFFFFFF);
+    uint64_t region_size_mask = MK_U64_ADDR_CONST(0xFFF);
+
+    if ((map == NULL) ||
+        (map->size == 0U) || ((map->size - 1U) > slave_address_mask) ||
+        ((map->size & region_size_mask) != 0U) ||
+        ((map->size & (map->size - 1U)) != 0U) ||
+        ((map->slave_base & (map->size - 1U)) != 0U) ||
+        ((map->master_base & (map->size - 1U)) != 0U) ||
+        ((slave & ~slave_address_mask) != 0U)) {
+        goto out;
+    }
+
+    mask = map->size - 1ULL;
+
+    if ((slave & ~mask) == map->slave_base) {
+        addr = (slave & mask) | map->master_base;
+    }
+out:
+    return addr;
+}
+
+SECTION_AST_TEXT
+uint64_t tegra_ast_map_iova_to_slave(const struct tegra_ast_region_map *map,
+                                     const iova iova_addr)
+{
+    uint64_t mask;
+    uint64_t slave_addr = 0ULL;
+    uint64_t slave_address_mask = MK_U64_ADDR_CONST(0xFFFFFFFF);
+    uint64_t iova_address_mask = MK_U64_ADDR_CONST(0xFFFFFFFFFF);
+    uint64_t region_size_mask = MK_U64_ADDR_CONST(0xFFF);
+
+    if ((map == NULL) ||
+        (map->size == 0U) || ((map->size - 1U) > slave_address_mask) ||
+        ((map->size & region_size_mask) != 0U) ||
+        ((map->size & (map->size - 1U)) != 0U) ||
+        ((map->slave_base & (map->size - 1U)) != 0U) ||
+        ((map->master_base & (map->size - 1U)) != 0U) ||
+        ((iova_addr & ~iova_address_mask) != 0U)) {
+        goto out;
+    }
+
+    mask = map->size - 1ULL;
+
+    if ((iova_addr & ~mask) == map->master_base) {
+        slave_addr = (iova_addr & mask) | map->slave_base;
+    }
+out:
+    return slave_addr;
+}
+
+SECTION_AST_TEXT static error_t
+ast_addr_set_default_vmindex(uint32_t base,
+                             uint8_t stream_id)
+{
+    error_t  err = E_SUCCESS;
+    uint32_t control;
+    bool     already_enabled;
+    uint8_t  vmindex;
+
+    err = ast_get_vmindex(base, stream_id, &already_enabled, &vmindex);
+    if (err != E_SUCCESS) {
+        goto out;
+    }
+    if (!already_enabled) {
+        err = ast_set_streamid(base, vmindex, stream_id);
+        if (err != E_SUCCESS){
+            goto out;
+        }
+    }
+
+    control = readl_base_offset(base, APS_AST_CONTROL_0);
+    control |= ((uint32_t)(vmindex & APS_AST_CONTROL_0_DefVMIndex_DEFAULT_MASK) <<
+                APS_AST_CONTROL_0_DefVMIndex_SHIFT);
+    writel_base_offset(control, base, APS_AST_CONTROL_0);
+
+out:
+    return err;
+}
+
+SECTION_AST_TEXT static error_t
+ast_addr_set_default_stream_id(uint8_t stream_id,
+                               uint32_t base,
+                               bool phy)
+{
+    error_t  err = E_SUCCESS;
+    uint32_t physicalStreamEnable = APS_AST_CONTROL_0_DefPhysical_DEFAULT_MASK <<
+                                    APS_AST_CONTROL_0_DefPhysical_SHIFT;
+    uint32_t control;
+
+    if (base == 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    if (phy) {
+        /* Set DefPhysical bit in the AST_control_register */
+        control = readl_base_offset(base, APS_AST_CONTROL_0);
+
+        /*
+         * If AST is global locked and physicalStreamEnable is unset,
+         * return error
+         */
+        if (ast_is_global_locked(base)) {
+            if ((control & APS_AST_CONTROL_0_DefPhysical_DEFAULT_MASK) == 0U) {
+                err = E_AST_GLOBALLY_LOCKED;
+                goto out;
+            }
+        } else {
+            control |= physicalStreamEnable;
+            writel_base_offset(control, base, APS_AST_CONTROL_0);
+            }
+    } else {
+        err = tegra_ast_addr_add_streamid(stream_id, base);
+        if (err != E_SUCCESS) {
+            goto out;
+        }
+
+        /* Clear DefPhysical bit in the AST_control_register */
+        /*
+         * Setting VMIndex for default access needs the global lock bit to be
+         * unset. Return error if global lock is set
+         */
+        if (ast_is_global_locked(base)) {
+            err = E_AST_GLOBALLY_LOCKED;
+            goto out;
+        }
+        control = readl_base_offset(base, APS_AST_CONTROL_0);
+        control &= ~physicalStreamEnable;
+        writel_base_offset(control, base, APS_AST_CONTROL_0);
+    }
+
+  out:
+    return err;
+}
+
+
+SECTION_AST_TEXT error_t
+tegra_ast_addr_set_default_stream_id(uint8_t stream_id,
+                                     uint32_t base,
+                                     bool phy) {
+    error_t  err = E_SUCCESS;
+
+    if (base == 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    err = ast_addr_set_default_stream_id(stream_id, base, phy);
+    if (err != E_SUCCESS) {
+        goto out;
+    }
+
+    /* Set DefVMindex */
+    INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-383, DR: SWE-FSP-004-SWSADR.docx");
+    err = ast_addr_set_default_vmindex(base, stream_id);
+
+out:
+    return err;
+}
+
+SECTION_AST_TEXT
+error_t tegra_ast_set_default_stream_id(uint8_t stream_id, uint8_t instance_mask,
+                                        bool phy) {
+    error_t  err = E_SUCCESS;
+
+    if (!ast_instance_valid(instance_mask)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    if ((instance_mask & AST_INSTANCE_R5) != 0U) {
+        err = ast_addr_set_default_stream_id(stream_id,
+                                             ast_tegra_id[AST_INSTANCE_R5_INDEX],
+                                             phy);
+        if (err != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+    if ((instance_mask & AST_INSTANCE_DMA) != 0U) {
+        err = ast_addr_set_default_stream_id(stream_id,
+                                             ast_tegra_id[AST_INSTANCE_DMA_INDEX],
+                                             phy);
+        if (err != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+        /* Set DefVMindex */
+        INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-383, DR: SWE-FSP-004-SWSADR.docx");
+    if ((instance_mask & AST_INSTANCE_R5) != 0U) {
+        err = ast_addr_set_default_vmindex(ast_tegra_id[AST_INSTANCE_R5_INDEX],
+                                           stream_id);
+        if (err != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+    if ((instance_mask & AST_INSTANCE_DMA) != 0U) {
+        err = ast_addr_set_default_vmindex(ast_tegra_id[AST_INSTANCE_DMA_INDEX],
+                                           stream_id);
+        if (err != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+out:
+    return err;
+}
+
+SECTION_AST_TEXT error_t
+tegra_ast_addr_enable_phy_region(uint8_t region,
+                                 iova master,
+                                 uint64_t slave,
+                                 uint64_t size,
+                                 uint32_t base)
+{
+    error_t  err = E_SUCCESS;
+    uint64_t slave_address_mask = MK_U64_ADDR_CONST(0xFFFFFFFF);
+    uint64_t iova_address_mask = MK_U64_ADDR_CONST(0xFFFFFFFFFF);
+    uint64_t region_size_mask = MK_U64_ADDR_CONST(0xFFF);
+    uint32_t reg;
+    uint32_t region_base;
+
+    if ((region > MAX_REGION_INDEX)
+        || ((slave & ~slave_address_mask) != 0U)
+        || ((master & ~iova_address_mask) != 0U)
+        || (size == 0U)
+        || ((size - 1U) > slave_address_mask)
+        || ((size & region_size_mask) != 0U)
+        || ((size & (size - 1U)) != 0U)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    if ((((size - 1UL) & slave) != 0UL)
+        || (((size - 1UL) & master) != 0UL)) {
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    region_base = ast_region_base(base, region);
+    reg = readl_base_offset(region_base, AST_REG(APS_AST_REGION_0_CONTROL_0));
+
+    /*
+     * Physical field is RWGL protected in region control register.
+     * If Physical field is unset and global lock is set, region cannot
+     * be enabled with Physical streamid. Return error.
+     */
+    if (ast_is_global_locked(ast_tegra_id[AST_INSTANCE_R5_INDEX]) &&
+        ((reg & APS_AST_REGION_0_CONTROL_0_Physical_FIELD) == 0U)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_GLOBALLY_LOCKED;
+        goto out;
+    }
+
+    ast_enable_region(base, region,
+                      (uint8_t)VMINDEX_PHYSICAL_STREAM_ID,
+                      master,
+                      slave,
+                      size);
+
+out:
+    return err;
+}
+
+SECTION_AST_TEXT
+error_t tegra_ast_enable_phy_region(uint8_t region,
+                                    iova master,
+                                    uint64_t slave,
+                                    uint64_t size,
+                                    uint8_t instance_mask)
+{
+    error_t  err = E_SUCCESS;
+
+    if (!ast_instance_valid(instance_mask)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    if ((instance_mask & AST_INSTANCE_R5) != 0U) {
+        err = tegra_ast_addr_enable_phy_region(region, master, slave, size,
+                                               ast_tegra_id[AST_INSTANCE_R5_INDEX]);
+        if (err != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+    if ((instance_mask & AST_INSTANCE_DMA) != 0U) {
+        err = tegra_ast_addr_enable_phy_region(region, master, slave, size,
+                                               ast_tegra_id[AST_INSTANCE_DMA_INDEX]);
+        if (err != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+out:
+    return err;
+}
+
+SECTION_AST_TEXT error_t
+tegra_ast_addr_enable_region_vmindex(uint8_t region,
+                                     iova master,
+                                     uint64_t slave,
+                                     uint64_t size,
+                                     uint32_t base,
+                                     uint8_t vmindex)
+{
+    error_t  err = E_SUCCESS;
+    uint64_t slave_address_mask = MK_U64_ADDR_CONST(0xFFFFFFFF);
+    uint64_t iova_address_mask = MK_U64_ADDR_CONST(0xFFFFFFFFFF);
+    uint64_t region_size_mask = MK_U64_ADDR_CONST(0xFFF);
+
+    if ((region > MAX_REGION_INDEX)
+        || (base == 0U)
+        || ((slave & ~slave_address_mask) != 0U)
+        || ((master & ~iova_address_mask) != 0U)
+        || (size == 0U)
+        || ((size - 1U) > slave_address_mask)
+        || ((size & region_size_mask) != 0U)
+        || ((size & (size - 1U)) != 0U)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    if ((((size - 1UL) & slave) != 0UL)
+        || (((size - 1UL) & master) != 0UL)) {
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    if(vmindex > VMINDEX_PHYSICAL_STREAM_ID) {
+        err = E_AST_INVALID_VMINDEX;
+        goto out;
+    }
+
+    ast_enable_region(base, region, vmindex, master, slave, size);
+
+out:
+    return err;
+}
+
+SECTION_AST_TEXT
+error_t tegra_ast_enable_region_vmindex(uint8_t region,
+                                      iova master,
+                                      uint64_t slave,
+                                      uint64_t size,
+                                      uint8_t instance_mask,
+                                      uint8_t vmindex)
+{
+    error_t  err = E_SUCCESS;
+
+    if (!ast_instance_valid(instance_mask)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_AST_INVALID_INPUT_PARAMETERS;
+        goto out;
+    }
+
+    if ((instance_mask & AST_INSTANCE_R5) != 0U) {
+        err = tegra_ast_addr_enable_region_vmindex(region,
+                                                   master,
+                                                   slave,
+                                                   size,
+                                                   ast_tegra_id[AST_INSTANCE_R5_INDEX],
+                                                   vmindex);
+        if (err != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+    if ((instance_mask & AST_INSTANCE_DMA) != 0U) {
+        err = tegra_ast_addr_enable_region_vmindex(region,
+                                                   master,
+                                                   slave,
+                                                   size,
+                                                   ast_tegra_id[AST_INSTANCE_DMA_INDEX],
+                                                   vmindex);
+        if (err != E_SUCCESS) {
+            goto out;
+        }
+    }
+out:
+    return err;
+}
+
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/car/car-clk.c b/spe-freertos-bsp/fsp/source/drivers/car/car-clk.c
new file mode 100644
index 0000000..ee949b5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/car/car-clk.c
@@ -0,0 +1,241 @@
+/* Copyright (c) 2020-2021 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stddef.h>                     // for NULL
+#include <stdbool.h>                    // for bool, false
+#include <stdint.h>                     // for uint32_t, uint8_t, UINT8_MAX, UIN...
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD...
+#include <error/common-errors.h>        // for E_SUCCESS, error_t
+
+/* Module-specific FSP headers */
+#include <car/car-sections.h>           // for SECTION_CAR_TEXT, ...
+#include <car/car-errors.h>             // for E_CAR_ERR_NULL_PTR, E_CAR_ERR_NO_...
+#include <car/car-reg.h>                // for register access functions...
+#include <car/car-clk.h>                // for declarations...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_REG_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_CLK_H, "Header file missing or invalid.")
+
+
+SECTION_CAR_TEXT
+static bool car_clk_op_is_enabled(const struct car_clk_inf *clk)
+{
+    bool ret = false;
+
+    if (clk != NULL) {
+        if ((car_reg_rd(clk->en_reg) & clk->en_msk) != 0U)
+            ret = true;
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+static error_t car_clk_op_enable_bit(const struct car_clk_inf *clk)
+{
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (clk != NULL) {
+        if (clk->en_msk == 0U) {
+            ret = E_CAR_CLOCK_OP_NOT_SUPPORTED;
+        } else {
+            car_reg_rdwr(clk->en_reg, clk->en_msk, clk->en_msk);
+            ret = E_SUCCESS;
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+static error_t car_clk_op_disable_bit(const struct car_clk_inf *clk)
+{
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (clk != NULL) {
+        if (clk->en_msk == 0U) {
+            ret = E_CAR_CLOCK_OP_NOT_SUPPORTED;
+        } else {
+            car_reg_rdwr(clk->en_reg, 0U, clk->en_msk);
+            ret = E_SUCCESS;
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_RODATA
+const struct car_clk_op_able car_clk_op_able_bit = {
+    .clk_is_enabled = car_clk_op_is_enabled,
+    .clk_enable = car_clk_op_enable_bit,
+    .clk_disable = car_clk_op_disable_bit,
+};
+
+
+SECTION_CAR_TEXT
+static error_t car_clk_op_enable_reg(const struct car_clk_inf *clk)
+{
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (clk != NULL) {
+        if (clk->en_msk == 0U) {
+            ret = E_CAR_CLOCK_OP_NOT_SUPPORTED;
+        } else {
+            car_reg_wr(clk->en_reg + 0x04U, clk->en_msk);
+            ret = E_SUCCESS;
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+static error_t car_clk_op_disable_reg(const struct car_clk_inf *clk)
+{
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (clk != NULL) {
+        if (clk->en_msk == 0U) {
+            ret = E_CAR_CLOCK_OP_NOT_SUPPORTED;
+        } else {
+            car_reg_wr(clk->en_reg + 0x08U, clk->en_msk);
+            ret = E_SUCCESS;
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_RODATA
+const struct car_clk_op_able car_clk_op_able_reg = {
+    .clk_is_enabled = car_clk_op_is_enabled,
+    .clk_enable = car_clk_op_enable_reg,
+    .clk_disable = car_clk_op_disable_reg,
+};
+
+
+
+SECTION_CAR_TEXT
+static error_t clk_get_hz_in(const struct car_clk_inf *clk, int64_t *hz_in)
+{
+    error_t ret = E_CAR_NULL_PTR;
+
+    if ((clk != NULL) && (hz_in != NULL)) {
+        if ((clk->pclk != NULL) && (clk->pclk->op_rate != NULL) && (clk->pclk->op_rate->clk_hz_get != NULL)) {
+            ret = clk->pclk->op_rate->clk_hz_get((struct car_clk_inf *)clk->pclk, hz_in);
+        } else {
+            ret = E_CAR_CLOCK_OP_NOT_SUPPORTED;
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+static error_t car_clk_op_hz_get(const struct car_clk_inf *clk, int64_t *hz_out)
+{
+    int64_t hz_in;
+    uint32_t divider;
+    error_t ret = E_CAR_NULL_PTR;
+
+    if ((clk != NULL) && (hz_out != NULL)) {
+        ret = clk_get_hz_in(clk, &hz_in);
+        if (ret == E_SUCCESS) {
+            if ((clk->op_div != NULL) && (clk->op_div->clk_div_calc_out != NULL)) {
+                divider = clk->op_div->clk_div_calc_out(clk);
+            } else {
+                divider = car_reg_rd_val(clk->div_reg, clk->div_msk);
+                divider = divider + 1U;
+            }
+            *hz_out = hz_in / divider;
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+static error_t car_clk_op_hz_set(const struct car_clk_inf *clk, int64_t hz_out)
+{
+    int64_t hz_in;
+    uint32_t divider;
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (clk != NULL) {
+        if ((clk->hz_max != 0ULL) && (hz_out > clk->hz_max)) {
+            ret = E_CAR_CLOCK_HZ_NOT_SUPPORTED;
+        } else if ((clk->hz_min != 0ULL) && (hz_out < clk->hz_min)) {
+            ret = E_CAR_CLOCK_HZ_NOT_SUPPORTED;
+        } else {
+            ret = clk_get_hz_in(clk, &hz_in);
+            if (ret == E_SUCCESS) {
+                if (hz_out != 0LL) {
+                    if ((clk->op_div != NULL) && (clk->op_div->clk_div_calc_in != NULL)) {
+                        divider = clk->op_div->clk_div_calc_in(hz_in, hz_out);
+                    } else {
+                        divider = hz_in / hz_out;
+                        if (divider > 0) {
+                            divider = divider - 1U;
+                        }
+                    }
+                    car_reg_rdwr_val(clk->div_reg, clk->div_msk, divider);
+                } else {
+                    ret = E_CAR_CLOCK_HZ_NOT_SUPPORTED;
+                }
+            }
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_RODATA
+const struct car_clk_op_rate car_clk_op_rate_dflt = {
+    .clk_hz_get = car_clk_op_hz_get,
+    .clk_hz_set = car_clk_op_hz_set,
+};
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
diff --git a/spe-freertos-bsp/fsp/source/drivers/car/car-fmon.c b/spe-freertos-bsp/fsp/source/drivers/car/car-fmon.c
new file mode 100644
index 0000000..ef083a4
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/car/car-fmon.c
@@ -0,0 +1,380 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stddef.h>                     // for NULL
+#include <stdbool.h>                    // for bool, false
+#include <stdint.h>                     // for uint32_t, uint8_t, UINT8_MAX, UIN...
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+#include <soc-common/hw-const.h>        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD...
+#include <error/common-errors.h>        // for E_SUCCESS, error_t
+#include <misc/bitops.h>                // for BIT, bit_number, FSP__MISC__BITOPS_H
+
+/* Module-specific FSP headers */
+#include <car/car-sections.h>           // for SECTION_CAR_TEXT ...
+#include <car/car-errors.h>             // for E_CAR_ERR_NULL_PTR, E_CAR_ERR_NO_...
+#include <car/car-reg.h>                // for register access functions...
+#include <car/car-math.h>               // for safe math functions...
+#include <car/car-clk.h>                // for clock structures...
+#include <car/car-fmon.h>               // for frequency monitor structures...
+#include <port/car-port.h>              // for platform functions...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_REG_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_MATH_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_CLK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_FMON_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PORT__CAR_PORT_H, "Header file missing or invalid.")
+
+
+SECTION_CAR_TEXT
+static error_t car_fmon_clk_hz_get(const struct car_fmon_inf *fmon, uint64_t *hz)
+{
+    error_t ret = E_CAR_NULL_PTR;
+
+    if ((fmon->clk != NULL) && (hz != NULL)) {
+        ret = E_CAR_CLOCK_OP_NOT_SUPPORTED;
+        if ((fmon->clk->op_rate != NULL) && (fmon->clk->op_rate->clk_hz_get != NULL)) {
+            ret = fmon->clk->op_rate->clk_hz_get(fmon->clk, (int64_t *)hz);
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+bool car_fmon_is_enabled(const struct car_fmon_inf *fmon)
+{
+    uint32_t val;
+    bool ret = false;
+
+    if (fmon != NULL) {
+        val = car_reg_rd_val(fmon->reg_cfg, fmon->reg_cfg_msk_en);
+        if (val != 0U) {
+            ret = true;
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+uint32_t car_fmon_enable_status(const struct car_fmon_inf *fmon)
+{
+    uint32_t data = 0U;
+
+    if (fmon != NULL) {
+        data = car_reg_rd(fmon->reg_en_sts);
+        data &= fmon->reg_en_sts_msk;
+    }
+    return data;
+}
+
+SECTION_CAR_TEXT
+uint64_t car_fmon_timeout_us(const struct car_fmon_inf *fmon)
+{
+    uint64_t delay_us = 1ULL;
+    uint64_t hz;
+    error_t ret;
+
+    if (fmon != NULL) {
+        ret = car_fmon_clk_hz_get(fmon, &hz);
+        if (ret == E_SUCCESS) {
+            hz *= 6ULL;
+            hz += (fmon->clk_ref << 2);
+            hz += (fmon->clk_err << 2);
+            hz = 1000000ULL / hz; /* Hz => us */
+            if (delay_us < hz) {
+                delay_us = hz;
+            }
+        }
+    }
+    return delay_us;
+}
+
+SECTION_CAR_TEXT
+static void car_fmon_delay_us(const struct car_fmon_inf *fmon)
+{
+    car_port_udelay(car_fmon_timeout_us(fmon));
+}
+
+SECTION_CAR_TEXT
+static error_t car_fmon_reg_rdwr_verify(uint32_t reg, uint32_t mask, uint32_t val, uint64_t to_us)
+{
+    uint64_t ticks_start;
+    uint64_t ticks_us;
+    uint32_t i;
+    error_t ret = E_CAR_FMON_HW_TIMEOUT;
+
+    for (i = 0; i < CAR_FMON_RDWR_VERIFY_N; i = i + 1U) {
+        car_reg_rdwr_val(reg, mask, val);
+        ticks_start = car_port_get_time_ticks();
+        do {
+            if (car_reg_rd_val(reg, mask) == val) {
+                ret = E_SUCCESS;
+                goto out;
+            }
+
+            ticks_us = car_port_get_time_delta_us(ticks_start);
+        } while (ticks_us < to_us);
+    }
+
+out:
+    return ret;
+}
+
+SECTION_CAR_TEXT
+static error_t car_fmon_count_load_en(const struct car_fmon_inf *fmon, bool enable)
+{
+    uint64_t ticks_start;
+    uint64_t ticks_us;
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (fmon != NULL) {
+        if (enable == true) {
+            /* load_data = 0x1 */
+            car_reg_rdwr_val(fmon->reg_data_ctrl, fmon->reg_data_ctrl_msk_en, fmon->reg_data_ctrl_msk_en);
+        } else {
+            /* load_data = 0x0 && register_count_select = 0x0 */
+            car_reg_wr(fmon->reg_data_ctrl, 0);
+        }
+        /* wait for load_data_done */
+        ret = E_CAR_FMON_HW_TIMEOUT;
+        ticks_start = car_port_get_time_ticks();
+        do {
+            ticks_us = car_port_get_time_delta_us(ticks_start);
+            if (car_reg_rd_val(fmon->reg_data_sts_done, fmon->reg_data_sts_done_msk)) {
+                ret = E_SUCCESS;
+                break;
+            }
+
+            if (ticks_us > 3ULL) {
+                break;
+            }
+
+            car_port_udelay(1ULL);
+        } while (true);
+    }
+
+    return ret;
+}
+
+SECTION_CAR_TEXT
+static error_t car_fmon_count_load(const struct car_fmon_inf *fmon,
+                                   uint32_t *cnt, uint32_t sel)
+{
+    error_t ret;
+
+    /* load_data = 0x0 */
+    ret = car_fmon_count_load_en(fmon, false);
+    if (ret == E_SUCCESS) {
+        /* register count select */
+        car_reg_rdwr_val(fmon->reg_data_ctrl, fmon->reg_data_ctrl_msk_sel, sel);
+        /* load_data = 0x1 */
+        ret = car_fmon_count_load_en(fmon, true);
+        if (ret == E_SUCCESS) {
+            /* check load_data_sel_status */
+            if ((car_reg_rd_val(fmon->reg_data_sts_sel, fmon->reg_data_sts_sel_msk) == sel)) {
+                /* read load data val */
+                *cnt = car_reg_rd(fmon->reg_data_val);
+                /* load_data = 0x0 */
+                ret = car_fmon_count_load_en(fmon, false);
+            } else {
+                ret = E_CAR_FMON_HW_LOGIC;
+            }
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t car_fmon_counts(const struct car_fmon_inf *fmon, uint32_t *cnts)
+{
+    uint32_t i;
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (fmon != NULL) {
+        if (car_fmon_is_enabled(fmon) == true) {
+            if (cnts == NULL) {
+                /* caller can clear counters without reading them */
+                ret = E_SUCCESS;
+                goto clear;
+            }
+
+            /* freeze counter storage */
+            car_reg_rdwr_val(fmon->reg_cntr_ctrl, fmon->reg_cntr_ctrl_msk_hld, fmon->reg_cntr_ctrl_msk_hld);
+
+            for (i = 0; i < fmon->cnt->cnt_sel_n; i = i + 1U) {
+                ret = car_fmon_count_load(fmon, &cnts[fmon->cnt->cnt_sel_0_i + i], fmon->cnt->cnt_sel_0 + i);
+                if (ret != E_SUCCESS) {
+                    goto clear;
+                }
+            }
+
+            ret = car_fmon_count_load(fmon, &cnts[fmon->cnt->cnt_sel_min_i], fmon->cnt->cnt_sel_min);
+            ret |= car_fmon_count_load(fmon, &cnts[fmon->cnt->cnt_sel_max_i], fmon->cnt->cnt_sel_max);
+            cnts[fmon->cnt->cnt_ref_win_i] = car_reg_rd_val(fmon->reg_ref_win_cnt,
+                                                            fmon->reg_ref_win_cnt_msk);
+            cnts[fmon->cnt->cnt_ref_win_dc_chk_i] = car_reg_rd_val(fmon->reg_ref_win_dc_chk_cnt,
+                                                                   fmon->reg_ref_win_dc_chk_cnt_msk);
+clear:
+            /* clear counts */
+            car_reg_rdwr_val(fmon->reg_cntr_ctrl, fmon->reg_cntr_ctrl_msk_clr, fmon->reg_cntr_ctrl_msk_clr);
+            /* unfreeze counter storage */
+            car_reg_rdwr_val(fmon->reg_cntr_ctrl, fmon->reg_cntr_ctrl_msk_hld, 0);
+        } else {
+            ret = E_CAR_FMON_NO_DATA;
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t car_fmon_clk_hz_calc(const struct car_fmon_inf *fmon, uint32_t *cnts, uint64_t *hz)
+{
+    int64_t cnt;
+    int64_t ref_win;
+    uint32_t i;
+    uint32_t n;
+    error_t ret = car_fmon_counts(fmon, cnts);
+
+    if ((ret == E_SUCCESS) && (cnts != NULL)) {
+        cnt = 0;
+        n = 0;
+        for (i = 0; i < fmon->cnt->cnt_sel_n; i = i + 1U) {
+            if ((cnts[fmon->cnt->cnt_sel_0_i + i] != 0) && (cnts[fmon->cnt->cnt_sel_0_i + i] != UINT32_MAX)) {
+                cnt += (int64_t)cnts[fmon->cnt->cnt_sel_0_i + i];
+                n = n + 1U;
+            }
+        }
+
+        if (n > 0) {
+            cnt *= (int64_t)fmon->clk_ref;
+            ref_win = (int64_t)cnts[fmon->cnt->cnt_ref_win_i];
+            ref_win *= (int64_t)n;
+            *hz = (uint64_t)car_div_s64(cnt, ref_win);
+        } else {
+            ret = E_CAR_FMON_NO_DATA;
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t car_fmon_shutdown(const struct car_fmon_inf *fmon)
+{
+    uint32_t data;
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (fmon != NULL) {
+        data = (fmon->reg_cfg_msk_rprt |
+                fmon->reg_cfg_msk_ref_en |
+                fmon->reg_cfg_msk_cntr_en |
+                fmon->reg_cfg_msk_en);
+        car_reg_rdwr_val(fmon->reg_cfg, data, 0);
+        car_fmon_delay_us(fmon);
+        data = car_fmon_enable_status(fmon);
+        if (data == 0U) {
+            ret = E_SUCCESS;
+        } else {
+            ret = E_CAR_FMON_HW_LOGIC;
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t car_fmon_startup(const struct car_fmon_inf *fmon)
+{
+    uint64_t delay_us;
+    uint32_t thr_lo = 0U;
+    uint32_t thr_hi = UINT32_MAX;
+    uint32_t data;
+    error_t ret;
+
+    ret = car_fmon_shutdown(fmon);
+    if (ret == E_SUCCESS) {
+        delay_us = car_fmon_timeout_us(fmon);
+        /* monitoring window period */
+        ret = car_fmon_reg_rdwr_verify(fmon->reg_thr_lo, fmon->reg_thr_lo_msk, thr_lo, delay_us);
+        ret |= car_fmon_reg_rdwr_verify(fmon->reg_thr_hi, fmon->reg_thr_hi_msk, thr_hi, delay_us);
+        /* fault action */
+        ret |= car_fmon_reg_rdwr_verify(fmon->reg_flt_actn, fmon->reg_flt_actn_msk, fmon->reg_flt_actn_msk, delay_us);
+        /* configuration */
+        car_reg_rdwr_val(fmon->reg_cfg, fmon->reg_cfg_msk_rprt, fmon->reg_cfg_msk_rprt);
+        car_reg_rdwr_val(fmon->reg_cfg, fmon->reg_cfg_msk_ref_en, fmon->reg_cfg_msk_ref_en);
+        car_reg_rdwr_val(fmon->reg_cfg, fmon->reg_cfg_msk_cntr_en, fmon->reg_cfg_msk_cntr_en);
+        car_reg_rdwr_val(fmon->reg_cfg, fmon->reg_cfg_msk_en, fmon->reg_cfg_msk_en);
+        /* verify */
+        data = (fmon->reg_cfg_msk_rprt |
+                fmon->reg_cfg_msk_ref_en |
+                fmon->reg_cfg_msk_cntr_en |
+                fmon->reg_cfg_msk_en);
+        if ((car_reg_rd(fmon->reg_cfg) & data) != data) {
+            ret = E_CAR_FMON_HW_LOGIC;
+            goto out;
+        }
+
+        /* monitor enable status with timeout */
+        car_port_udelay(delay_us);
+        data = car_fmon_enable_status(fmon);
+        if (data != fmon->reg_en_sts_msk) {
+            ret = E_CAR_FMON_HW_LOGIC;
+            goto out;
+        }
+
+        /* test for fault */
+        data = car_reg_rd(fmon->reg_flt_sts);
+        data &= fmon->reg_flt_sts_msk_ro;
+        if (data != 0U) {
+            ret = E_CAR_FMON_FAULT;
+        }
+    }
+out:
+    return ret;
+}
+
diff --git a/spe-freertos-bsp/fsp/source/drivers/car/car-hpll.c b/spe-freertos-bsp/fsp/source/drivers/car/car-hpll.c
new file mode 100644
index 0000000..f2f4b3b
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/car/car-hpll.c
@@ -0,0 +1,277 @@
+/* Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/* Compiler headers */
+#include <stddef.h>                     // for NULL
+#include <stdbool.h>                    // for bool, false
+#include <stdint.h>                     // for uint32_t, uint8_t, UINT8_MAX, UIN...
+#include <string.h>                     // for memset
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+#include <soc-common/hw-const.h>        // Must appear before any hwinc files
+
+/* Hardware headers */
+#include <arclk_rst.h>                  // for CLK_RST_CONTROLLER_?_BASE_0...
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <error/common-errors.h>        // for E_SUCCESS, error_t
+
+/* Module-specific FSP headers */
+#include <car/car-sections.h>           // for SECTION_CAR_TEXT, ...
+#include <car/car-errors.h>             // for E_CAR_ERR_NULL_PTR, E_CAR_ERR_NO_...
+#include <car/car-reg.h>                // for register access functions...
+#include <car/car-math.h>               // for math functions, ...
+#include <car/car-pll.h>                // for pll functions, ...
+#include <car/car-hpll.h>               // for hpll functions, ...
+#include <port/car-port.h>              // for car_port_udelay...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_REG_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_MATH_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_PLL_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_HPLL_H, "Header file missing or invalid.")
+
+
+SECTION_CAR_TEXT
+static error_t car_hpll_disable(const struct car_pll_inf *pll)
+{
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (pll != NULL) {
+        ret = car_pll_select(pll, CAR_PLL_SEL_XTAL);
+        if (ret == E_SUCCESS) {
+            car_reg_rdwr(pll->en_reg, 0U, pll->en_msk);
+            car_reg_rdwr(pll->iddq_reg, pll->iddq_msk, pll->iddq_msk);
+            car_port_udelay(2ULL);
+            car_reg_rdwr(pll->rst_reg, 0U, pll->rst_msk);
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+static error_t car_hpll_enable(const struct car_pll_inf *pll)
+{
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (pll != NULL) {
+        if ((*pll->sts & CAR_PLL_STS_HZ_SET) == CAR_PLL_STS_HZ_SET) {
+            car_reg_rdwr(pll->iddq_reg, 0U, pll->iddq_msk);
+            car_port_udelay(5ULL);
+            car_reg_rdwr(pll->rst_reg, pll->rst_msk, pll->rst_msk);
+            car_reg_rdwr(pll->en_reg, pll->en_msk, pll->en_msk);
+            if (car_reg_rd_val(pll->mdiv_reg, pll->mdiv_msk) == MK_U32_CONST(1)) {
+                car_port_udelay(50ULL);
+            } else {
+                car_port_udelay(100ULL);
+            }
+            ret = car_pll_wait_lock(pll);
+            if (ret == E_SUCCESS) {
+                ret = car_pll_select(pll, CAR_PLL_SEL_PLL);
+            }
+        } else {
+            ret = E_CAR_PLL_NO_INIT;
+        }
+    }
+    return ret;
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_CAR_TEXT static void car_hpll_fracstep_set(const struct car_pll_inf *pll, struct car_pll_cfg *cfg_cur, struct car_pll_cfg *cfg_new)
+{
+    int16_t dx;
+    int32_t ndivf;
+    int32_t fstep;
+    int32_t s;
+    uint32_t val;
+
+    if (pll->fracstep_msk != 0U) {
+        dx = cfg_new->sdm_din - cfg_cur->sdm_din;
+        if ((cfg_new->n != cfg_cur->n) && (dx != 0)) {
+            ndivf = cfg_new->sdm_din;
+        } else {
+            ndivf = dx;
+        }
+        if (ndivf != 0) {
+            s = (ndivf < 0) ? -1 : 1;
+            fstep = car_abs_s32(ndivf) / 4;
+            fstep = s * max(fstep, 1000);
+        } else {
+            fstep = 0;
+        }
+        val = (uint32_t)fstep;
+        car_reg_rdwr_val(pll->fracstep_reg, pll->fracstep_msk, val);
+    }
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_CAR_TEXT static void car_hpll_frac_set(const struct car_pll_inf *pll, struct car_pll_cfg *cfg_new)
+{
+    uint32_t val;
+
+    if (pll->frac_msk != 0U) {
+        val = (uint32_t)cfg_new->sdm_din;
+        car_reg_rdwr_val(pll->frac_reg, pll->frac_msk, val);
+        if (pll->enfrac_msk != 0U) {
+            if (val == 0U) {
+                car_reg_rdwr_val(pll->enfrac_reg, pll->enfrac_msk, val);
+            } else {
+                car_reg_rdwr_val(pll->enfrac_reg, 0U, pll->enfrac_msk);
+            }
+        }
+    }
+}
+
+SECTION_CAR_TEXT
+static void car_hpll_freq_set(const struct car_pll_inf *pll,
+                              struct car_pll_cfg *cfg_cur, struct car_pll_cfg *cfg_new)
+{
+    car_hpll_fracstep_set(pll, cfg_cur, cfg_new);
+    car_pll_nmp_set(pll, cfg_new);
+    car_hpll_frac_set(pll, cfg_new);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_CAR_TEXT static bool car_hpll_nmp_is_equal(struct car_pll_cfg *a, struct car_pll_cfg *b)
+{
+    return (a->n == b->n) &&
+           (a->m == b->m) &&
+           (a->p == b->p) &&
+           (a->sdm_din == b->sdm_din);
+}
+
+SECTION_CAR_TEXT
+static error_t car_hpll_nmp_set (const struct car_pll_inf *pll,
+                                 struct car_pll_cfg *cfg_cur, struct car_pll_cfg *cfg_new)
+{
+    uint32_t newp;
+    error_t ret = E_SUCCESS;
+
+    if (car_hpll_nmp_is_equal(cfg_cur, cfg_new)) {
+        /* nothing */
+    } else if (!pll->op->pll_is_enabled(pll)) {
+        car_hpll_freq_set (pll, cfg_cur, cfg_new);
+    } else if (cfg_new->p >= cfg_cur->p) {
+        car_hpll_freq_set (pll, cfg_cur, cfg_new);
+        ret = car_pll_wait_lock(pll);
+    } else {
+        newp = cfg_new->p;
+        cfg_new->p = cfg_cur->p;
+        car_hpll_freq_set (pll, cfg_cur, cfg_new);
+        ret = car_pll_wait_lock(pll);
+        if (ret == E_SUCCESS) {
+            cfg_new->p = newp;
+            car_pll_nmp_set(pll, cfg_new);
+        }
+    }
+    return ret;
+}
+
+static error_t car_hpll_nmp_calc(const struct car_pll_inf *pll,
+                                 struct car_pll_cfg *cfg_cur, struct car_pll_cfg *cfg_new,
+                                 int64_t hz_in, int64_t hz_out)
+{
+    const struct car_pll_spec *spec = *pll->spec;
+    const bool en = pll->op->pll_is_enabled(pll);
+    const struct car_pll_cfg *cfg;
+    int32_t p;
+    error_t ret;
+
+    if (en && !(spec->flags & CAR_PLL_FLG_HAS_DYNAMIC_RAMP)) {
+        ret = E_CAR_CLOCK_OP_NOT_SUPPORTED;
+    } else {
+        car_pll_nmp_get(pll, cfg_cur);
+        cfg = car_pll_cfg_get(pll, hz_in, hz_out);
+        if (cfg != NULL) {
+            *cfg_new = *cfg;
+            ret = E_SUCCESS;
+        } else {
+            p = en ? (int32_t)cfg_cur->p : -1;
+            ret = car_pll_cfg_calc(pll, hz_in, hz_out, INT64_MAX, cfg_new, p);
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+static int64_t car_hpll_hz_set(const struct car_pll_inf *pll,
+                               int64_t hz_in, int64_t hz_out)
+{
+    struct car_pll_cfg cfg_cur;
+    struct car_pll_cfg cfg_new;
+    error_t ret;
+    int64_t hz_ret = E_CAR_NULL_PTR;
+
+    if (pll != NULL) {
+        memset(&cfg_cur, 0, sizeof(cfg_cur));
+        memset(&cfg_new, 0, sizeof(cfg_new));
+        ret = car_hpll_nmp_calc(pll, &cfg_cur, &cfg_new, hz_in, hz_out);
+        if (ret == E_SUCCESS) {
+            ret = car_hpll_nmp_set (pll, &cfg_cur, &cfg_new);
+        }
+        if (ret == E_SUCCESS) {
+            hz_ret = car_pll_hz_calc(pll, &cfg_new, hz_in);
+            *pll->sts |= CAR_PLL_STS_HZ_SET;
+        } else {
+            hz_ret = (int64_t)ret;
+        }
+    }
+    return hz_ret;
+}
+
+SECTION_CAR_RODATA
+const struct car_pll_op car_pll_op_hpll = {
+    .frac_allowed = NULL,
+    .pll_is_enabled = car_pll_is_enabled,
+    .pll_enable = car_hpll_enable,
+    .pll_disable = car_hpll_disable,
+    .pll_hz_set = car_hpll_hz_set,
+    .pll_hz_get = car_pll_hz_get,
+};
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
diff --git a/spe-freertos-bsp/fsp/source/drivers/car/car-math.c b/spe-freertos-bsp/fsp/source/drivers/car/car-math.c
new file mode 100644
index 0000000..c764358
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/car/car-math.c
@@ -0,0 +1,153 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stddef.h>                     // for NULL
+#include <stdbool.h>                    // for bool, false
+#include <stdint.h>                     // for uint32_t, uint8_t, UINT8_MAX, UIN...
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD...
+#include <misc/math_secure.h>           // for the math
+
+/* Module-specific FSP headers */
+#include <car/car-sections.h>           // for SECTION_CAR_TEXT, ...
+#include <car/car-math.h>               // for declarations...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MATH_SECURE_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_MATH_H, "Header file missing or invalid.")
+
+
+SECTION_CAR_TEXT
+int64_t car_add_s64(int64_t a, int64_t b)
+{
+    int64_t c = (int64_t)sadd_u64(a, b, OVERFLOW_ACTION_0);
+
+    return c;
+}
+
+SECTION_CAR_TEXT
+int64_t car_sub_s64(int64_t a, int64_t b)
+{
+    int64_t c = (int64_t)ssub_u64(a, b, OVERFLOW_ACTION_0);
+
+    return c;
+}
+
+SECTION_CAR_TEXT
+int64_t car_mul_s64(int64_t a, int64_t b)
+{
+    int64_t c = (int64_t)smul_u64(a, b, OVERFLOW_ACTION_0);
+
+    return c;
+}
+
+SECTION_CAR_TEXT
+int64_t car_div_s64(int64_t a, int64_t b)
+{
+    int64_t c = 0LL;
+
+    /* Even though a division by 0 would trigger a fatal error already,
+     * add a check for divisor == 0 here to inform coverity we really check
+     * for this case. This avoids an INT32-C violation.
+     */
+    if ((b == 0) || ((a == INT64_MIN) && (b == -1LL))) {
+        /* nothing */
+    } else {
+        c = a / b;
+    }
+    return c;
+}
+
+SECTION_CAR_TEXT
+/* divide unsigned numbers by rounding to nearest integer */
+int64_t car_div64_round(int64_t n, int64_t d)
+{
+    int64_t ret;
+
+    /* Simplest way to do round-to-nearest division with unsigned
+     * numbers in C would be:
+     *  return (n + d/2)/d;
+     *
+     * But this does not work with very large numbers (i.e. n+d/2
+     * will overflow when both numbers are close to INT64_MAX)
+     *
+     * Hence compute same with more elborate algorithm:
+     */
+    ret = n / d;
+    if ((n % d) != 0) {
+        if ((n % d) >= car_add_s64(d / 2, d % 2)) {
+            ret = car_add_s64(ret, 1LL);
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+int64_t car_range_s64(int64_t x, int64_t x_min, int64_t x_max)
+{
+    if ((x_min != 0LL) && (x < x_min)) {
+        x = x_min;
+    } else if ((x_max != 0LL) && (x > x_max)) {
+        x = x_max;
+    }
+    return x;
+}
+
+SECTION_CAR_TEXT
+int32_t car_abs_s32(int32_t x)
+{
+    return (x >= 0) ? (uint32_t)x : (0U - (uint32_t)x);
+}
+
+SECTION_CAR_TEXT
+int64_t car_abs_s64(int64_t x)
+{
+    return (x >= 0) ? (uint64_t)x : (0U - (uint64_t)x);
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
diff --git a/spe-freertos-bsp/fsp/source/drivers/car/car-pll.c b/spe-freertos-bsp/fsp/source/drivers/car/car-pll.c
new file mode 100644
index 0000000..6999984
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/car/car-pll.c
@@ -0,0 +1,505 @@
+/* Copyright (c) 2021-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stddef.h>                     // for NULL
+#include <stdbool.h>                    // for bool, false
+#include <stdint.h>                     // for uint32_t, uint8_t, UINT8_MAX, UIN...
+#include <string.h>                     // for memset
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+#include <soc-common/hw-const.h>        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <arclk_rst.h>                  // for CLK_RST_CONTROLLER_PLLFSI_BASE_0...
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD...
+#include <error/common-errors.h>        // for E_SUCCESS, error_t
+#include <misc/bitops.h>                // for BIT, bit_number, FSP__MISC__BITOPS_H
+
+/* Module-specific FSP headers */
+#include <car/car-sections.h>           // for SECTION_CAR_TEXT, ...
+#include <car/car-errors.h>             // for E_CAR_ERR_NULL_PTR, E_CAR_ERR_NO_...
+#include <car/car-reg.h>                // for register access functions...
+#include <car/car-math.h>               // for math functions...
+#include <car/car-pll.h>                // for PLL declarations...
+#include <port/car-port.h>              // for platform functions...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_REG_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_MATH_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_PLL_H, "Header file missing or invalid.")
+
+
+SECTION_CAR_TEXT
+error_t car_pll_wait_lock_us(const struct car_pll_inf *pll, uint64_t t_us)
+{
+    uint64_t ticks_start;
+    uint64_t ticks_us;
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (pll != NULL) {
+        ticks_start = car_port_get_time_ticks();
+        do {
+            if (car_reg_rd(pll->lock_reg) & pll->lock_msk) {
+                ret = E_SUCCESS;
+                break;
+            }
+
+            ticks_us = car_port_get_time_delta_us(ticks_start);
+            if (ticks_us > t_us) {
+                ret = E_CAR_PLL_NO_LOCK;
+                break;
+            }
+
+            car_port_udelay(5ULL);
+        } while (true);
+    }
+
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t car_pll_wait_lock(const struct car_pll_inf *pll)
+{
+    return car_pll_wait_lock_us(pll, CAR_PLL_LOCK_DELAY);
+}
+
+/* calc MDIV and adjust if VCO range cannot be met
+ * with possible range of NDIV.
+ */
+SECTION_CAR_TEXT
+static int64_t car_pll_calc_m(const struct car_pll_spec *spec, int64_t hz_in)
+{
+    const int64_t max_m = (int64_t)spec->max_m;
+    const int64_t max_n = (int64_t)spec->max_n;
+    const int64_t min_m = (int64_t)spec->min_m;
+    const int64_t min_n = (int64_t)spec->min_n;
+    int64_t vmin;
+    int64_t vmax;
+    int64_t cf;
+    int64_t m;
+
+    if (spec->min_m != spec->max_m) {
+        m = DIV_ROUND_UP(hz_in, spec->cf_max);
+        vmin = (hz_in * min_n) / m;
+        if (vmin > spec->vco_min) {
+            m = DIV_ROUND_UP(hz_in * min_n, spec->vco_min);
+        }
+        vmax = (hz_in * max_n) / m;
+        cf = hz_in / m;
+        if ((m < min_m) || (m > max_m) || (cf < spec->cf_min) || (cf > spec->cf_max) || (vmax < spec->vco_max)) {
+            m = E_CAR_INVALID_PARAM;
+        }
+    } else {
+        m = spec->min_m;
+    }
+    return m;
+}
+
+SECTION_CAR_TEXT
+static int64_t car_pll_calc_n(const struct car_pll_spec *spec, int64_t f_in,
+                              int64_t target_vco, uint32_t flags, int32_t *frac)
+{
+    const bool round_down = ((flags & CAR_PLL_FLG_ROUND_DOWN) != 0U);
+    const bool nofrac = ((flags & CAR_PLL_FLG_FRAC_NDIV) == 0U);
+    const int64_t min_n = (int64_t)spec->min_n;
+    const int64_t max_n = (int64_t)spec->max_n;
+    const int64_t mul = (int64_t)1LL << spec->frac_width;
+    const int64_t dy = mul / 2LL;
+    int64_t n;
+    int64_t f;
+
+    /* note that target_vco is actually the VCO target multiplied
+     * by fractional "accuracy" multiplied by m
+     */
+    if (round_down) {
+        n = car_div_s64(target_vco, f_in);
+    } else {
+        n = car_div64_round(target_vco, f_in);
+    }
+
+    if (nofrac) {
+        f = 0;
+    } else if (spec->type == CAR_PLL_TYPE_ANALOG) {
+        f = car_sub_s64(n % mul, dy);
+        /* intentionally round down */
+        n = n / mul;
+    } else {
+        f = car_add_s64(n, dy) % mul;
+        f = car_sub_s64(f, dy);
+        n = car_div64_round(n, mul);
+    }
+    n = car_range_s64(n, min_n, max_n);
+    *frac = (int32_t)(f);
+    return n;
+}
+
+/* if p_pref can satisfy vco range, return that */
+SECTION_CAR_TEXT
+static int64_t car_pll_calc_p(const struct car_pll_spec *spec, int64_t rate,
+                              int64_t vco_min, int64_t vco_max, int32_t p_pref, uint32_t flags)
+{
+    const bool round_down = ((flags & CAR_PLL_FLG_ROUND_DOWN) != 0U);
+    const int64_t max_p = (int64_t)spec->max_p;
+    const int64_t min_p = (int64_t)spec->min_p;
+    int64_t vco_mid;
+    int64_t p = 0;
+    int64_t xd;
+    int64_t nd;
+
+    if ((p_pref > 0) && (car_range_s64(rate, vco_min / p_pref, vco_max / p_pref)) != 0LL) {
+        p = p_pref;
+    } else if (((flags & CAR_PLL_FLG_USE_MID_VCO) != 0U) && (rate != 0)) {
+        vco_mid = car_add_s64(vco_max, vco_min) / 2LL;
+        p = car_div64_round(vco_mid, rate);
+    } else if (rate != 0) {
+        p = vco_max / rate;
+    }
+    p = max(p, min_p);
+    /* handle a special case that can happen if vco range cannot
+     * cover all possible frequencies. In other words, case when
+     * vco_max < 2 * vco_min
+     */
+    if (car_mul_s64(p, rate) < vco_min) {
+        /* when not rounding to nearest, always select higher
+         * P. Otherwise select P that gives closer match */
+        xd = car_sub_s64(rate, (vco_max / (p + 1)));
+        nd = (vco_min / p) - rate;
+        if (round_down || (xd <= nd)) {
+            ++p;
+        }
+    }
+    p = min(p, max_p);
+    return p;
+}
+
+/* scale rate, vco_min, and vco_max to precision of
+ * fractional step (if fractions are enabled)
+ */
+SECTION_CAR_TEXT
+static int64_t car_pll_scale(const struct car_pll_spec *spec, uint32_t flags)
+{
+    const bool nofrac = ((flags & CAR_PLL_FLG_FRAC_NDIV) == 0U);
+    int64_t mul;
+
+    if (nofrac) {
+        mul = 1LL;
+    } else {
+        mul = (int64_t)1LL << spec->frac_width;
+    }
+    return mul;
+}
+
+SECTION_CAR_TEXT
+static int64_t car_pll_round(int64_t hz, int64_t dy, bool up)
+{
+    const int64_t r = hz % dy;
+    int64_t ret_hz = hz;
+
+    if (r > 0) {
+        if (up) {
+            ret_hz += dy - r;
+        } else {
+            ret_hz -= r;
+        }
+    }
+    return ret_hz;
+}
+
+SECTION_CAR_TEXT
+error_t car_pll_nmp_calc(const struct car_pll_spec *spec, struct car_pll_nmp *nmp,
+                         int64_t hz_out, int64_t hz_in, int32_t p_pref, uint32_t flags)
+{
+    int64_t m, n, p;
+    int64_t target_vco;
+    const int64_t fx = car_pll_scale(spec, flags);
+    int64_t vco_min = spec->vco_min;
+    int64_t vco_max = spec->vco_max;
+    int64_t rate;
+    int64_t mul;
+    int32_t frac;
+    error_t ret = E_SUCCESS;
+
+    if (hz_in > spec->clkin_max) {
+        ret = E_CAR_INVALID_PARAM;
+        goto out;
+    }
+
+    m = car_pll_calc_m(spec, hz_in);
+    if (m < 0) {
+        ret = (int32_t)m;
+        goto out;
+    }
+
+    /* rate cannot ever go beyond vco_max */
+    rate = car_range_s64(hz_out, 1LL, vco_max);
+    /* preserve accuracy with following calculations */
+    mul = car_mul_s64(fx, m);
+    vco_min = car_mul_s64(vco_min, mul);
+    vco_max = car_mul_s64(vco_max, mul);
+    rate = car_mul_s64(rate, mul);
+    /* clamp vco_min and vco_max to frequencies that can be
+     * actually achieved. In practice this makes difference only
+     * when fractions are disabled because only then we could end
+     * up violating vco ranges in any meaningful amount
+     */
+    vco_min = car_pll_round(vco_min, hz_in, true);
+    vco_max = car_pll_round(vco_max, hz_in, false);
+    p = car_pll_calc_p(spec, rate, vco_min, vco_max, p_pref, flags);
+    target_vco = car_mul_s64(p, rate);
+    target_vco = car_range_s64(target_vco, vco_min, vco_max);
+    n = car_pll_calc_n(spec, hz_in, target_vco, flags, &frac);
+    nmp->n = (uint32_t)n;
+    nmp->m = (uint32_t)m;
+    nmp->p = (uint32_t)p;
+    nmp->frac = frac;
+
+out:
+    return ret;
+}
+
+SECTION_CAR_TEXT
+static int64_t libpll_calc_rate(const struct car_pll_inf *pll,
+                                const struct car_pll_nmp *nmp,
+                                int64_t hz_in, uint32_t flags)
+{
+    const struct car_pll_spec *spec = *pll->spec;
+    const bool enfrac = ((flags & CAR_PLL_FLG_FRAC_NDIV) != 0U);
+    const bool hpll = (spec->type != CAR_PLL_TYPE_ANALOG);
+    const int64_t fx = (int64_t)1LL << spec->frac_width;
+    int64_t hz_out;
+    int64_t n;
+
+    n = car_mul_s64(nmp->n, fx);
+    if (hpll) {
+        n = car_add_s64(n, nmp->frac);
+    } else if (enfrac) {
+        n = car_add_s64(n, nmp->frac);
+        n = car_add_s64(n, fx / 2LL);
+    } else {
+        /* nothing */
+    }
+    hz_out = hz_in / nmp->m;
+    hz_out = car_mul_s64(hz_out, n);
+    hz_out /= nmp->p;
+    hz_out /= fx;
+    return hz_out;
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_CAR_TEXT int64_t car_pll_hz_calc(const struct car_pll_inf *pll, struct car_pll_cfg *cfg, int64_t hz_in)
+{
+    const uint32_t flags = cfg->en_sdm ? CAR_PLL_FLG_FRAC_NDIV : 0U;
+    const struct car_pll_nmp nmp = {
+        .n = max(cfg->n, 1U),
+        .m = max(cfg->m, 1U),
+        .p = max(cfg->p, 1U),
+        .frac = cfg->sdm_din,
+    };
+
+    return libpll_calc_rate(pll, &nmp, hz_in, flags);
+}
+
+SECTION_CAR_TEXT
+static bool car_pll_en_frac(const struct car_pll_inf *pll)
+{
+    bool en;
+
+    if (pll->op->frac_allowed != NULL) {
+        en = pll->op->frac_allowed(pll);
+    } else {
+        en = (pll->frac_msk != 0U);
+    }
+    return en;
+}
+
+error_t car_pll_cfg_calc(const struct car_pll_inf *pll,
+                         int64_t hz_in, int64_t hz_out, int64_t hz_max,
+                         struct car_pll_cfg *cfg, int32_t p_curr)
+{
+    const bool enfrac = car_pll_en_frac(pll);
+    uint32_t flags = enfrac ? CAR_PLL_FLG_FRAC_NDIV : 0U;
+    struct car_pll_nmp nmp;
+    int64_t rrate;
+    error_t ret;
+
+    ret = car_pll_nmp_calc(*pll->spec, &nmp, hz_out, hz_in, p_curr, flags);
+    if (ret == E_SUCCESS) {
+        /* if hz_max is exceeded, recalculate with rounding down */
+        rrate = libpll_calc_rate(pll, &nmp, hz_in, flags);
+        if (rrate > hz_max) {
+            /*
+             * the car_pll_nmp_calc below differs from the one above only in
+             * flags, which doesn't affect return status. so, if the
+             * previous call of car_pll_nmp_calc returns 0, this one will
+             * return 0 too.
+             */
+            CAR_RET_UNUSED(car_pll_nmp_calc(*pll->spec, &nmp, hz_in, hz_out, p_curr,
+                                            flags | CAR_PLL_FLG_ROUND_DOWN));
+        }
+        memset(cfg, 0, sizeof(*cfg));
+        cfg->n = nmp.n;
+        cfg->m = nmp.m;
+        cfg->p = nmp.p;
+        /* for calculated PLL parameters, en_ssc is always 0 */
+        cfg->sdm_din = (int16_t)(nmp.frac);
+        cfg->en_sdm = enfrac;
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+void car_pll_nmp_get(const struct car_pll_inf *pll, struct car_pll_cfg *cfg)
+{
+    uint32_t v;
+
+    cfg->n = car_reg_rd_val(pll->ndiv_reg, pll->ndiv_msk);
+    cfg->m = car_reg_rd_val(pll->mdiv_reg, pll->mdiv_msk);
+    if (pll->pdiv_msk != 0U) {
+        cfg->p = car_reg_rd_val(pll->pdiv_reg, pll->pdiv_msk);
+    } else {
+        cfg->p = 1U;
+    }
+    if (pll->frac_msk != 0U) {
+        v = car_reg_rd_val(pll->frac_reg, pll->frac_msk);
+        cfg->sdm_din = (int16_t)v;
+    } else {
+        cfg->sdm_din = 0;
+    }
+    if (pll->enfrac_msk != 0) {
+        v = car_reg_rd_val(pll->enfrac_reg, pll->enfrac_msk);
+        cfg->en_sdm = (v != 0U);
+    } else {
+        cfg->en_sdm = false;
+    }
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_CAR_TEXT void car_pll_nmp_set(const struct car_pll_inf *pll, struct car_pll_cfg *cfg)
+{
+    if (pll->mdiv_msk != 0U) {
+        car_reg_rdwr_val(pll->mdiv_reg, pll->mdiv_msk, cfg->m);
+    }
+    if (pll->ndiv_msk != 0U) {
+        car_reg_rdwr_val(pll->ndiv_reg, pll->ndiv_msk, cfg->n);
+    }
+    if (pll->pdiv_msk != 0U) {
+        car_reg_rdwr_val(pll->pdiv_reg, pll->pdiv_msk, cfg->p);
+    }
+}
+
+SECTION_CAR_TEXT
+int64_t car_pll_hz_get(const struct car_pll_inf *pll, int64_t hz_in)
+{
+    struct car_pll_cfg cfg;
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (pll != NULL) {
+        car_pll_nmp_get(pll, &cfg);
+        ret = car_pll_hz_calc(pll, &cfg, hz_in);
+    }
+    return (int64_t)ret;
+}
+
+SECTION_CAR_TEXT
+const struct car_pll_cfg *car_pll_cfg_get(const struct car_pll_inf *pll,
+                                          int64_t hz_in, int64_t hz_out)
+{
+    const struct car_pll_cfg *cfgs = *pll->cfgs;
+    const struct car_pll_cfg *nearest = NULL;
+    int64_t err = INT64_MAX;
+    int64_t diff;
+    uint32_t i;
+
+    if (cfgs != NULL) {
+        for (i = 0; (i < *pll->cfgs_n) && (err > 0); i = i + 1U) {
+            if (cfgs[i].hz_in == hz_in) {
+                diff = car_abs_s64(hz_out - cfgs[i].hz_out);
+                if (diff <= err) {
+                    nearest = &cfgs[i];
+                    err = diff;
+                }
+            }
+        }
+    }
+
+    return nearest;
+}
+
+SECTION_CAR_TEXT
+error_t car_pll_select(const struct car_pll_inf *pll, uint32_t sel)
+{
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (pll != NULL) {
+        if (pll->sel_msk != 0U) {
+            car_reg_rdwr_val(pll->sel_reg, pll->sel_msk, sel);
+        }
+        ret = E_SUCCESS;
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+bool car_pll_is_enabled(const struct car_pll_inf *pll)
+{
+    uint32_t en = false;
+
+    if (pll != NULL) {
+        if (pll->en_msk == 0U) {
+            en = true;
+        } else {
+            en = (bool)(car_reg_rd(pll->en_reg) & pll->en_msk);
+        }
+    }
+    return en;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
diff --git a/spe-freertos-bsp/fsp/source/drivers/car/car-reg.c b/spe-freertos-bsp/fsp/source/drivers/car/car-reg.c
new file mode 100644
index 0000000..d227d99
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/car/car-reg.c
@@ -0,0 +1,137 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stddef.h>                     // for NULL
+#include <stdbool.h>                    // for bool, false
+#include <stdint.h>                     // for uint32_t, uint8_t, UINT8_MAX, UIN...
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+#include <soc-common/hw-const.h>        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>            // for NV_ADDRESS_MAP_CAR_BASE
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD...
+#include <reg-access/reg-access.h>      // for readl_base_offset, writel_base_of...
+#include <misc/bitops.h>                // for BIT, bit_number, FSP__MISC__BITOPS_H
+
+/* Module-specific FSP headers */
+#include <car/car-sections.h>           // for SECTION_CAR_TEXT, ...
+#include <car/car-reg.h>                // for register access declarations...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_REG_H, "Header file missing or invalid.")
+
+
+static inline uint32_t car_reg(uint32_t offset)
+{
+    return (NV_ADDRESS_MAP_CAR_BASE + offset);
+}
+
+SECTION_CAR_TEXT
+static uint32_t car_reg_msk2shft(uint32_t mask) {
+    uint32_t shift;
+
+    if (mask != 0U) {
+        shift = bit_number(mask);
+    } else {
+        shift = 0;
+    }
+    return shift;
+}
+
+SECTION_CAR_TEXT
+uint32_t car_reg_rd(uint32_t offset)
+{
+    return readl(car_reg(offset));
+}
+
+SECTION_CAR_TEXT
+void car_reg_wr(uint32_t offset, uint32_t data)
+{
+    writel(data, car_reg(offset));
+    return;
+}
+
+SECTION_CAR_TEXT
+uint32_t car_reg_rdwr(uint32_t offset, uint32_t data, uint32_t mask) {
+    uint32_t data_rdwr;
+
+    data_rdwr = readl(car_reg(offset));
+    data_rdwr &= ~mask;
+    data_rdwr |= data;
+    writel(data_rdwr, car_reg(offset));
+    return data_rdwr;
+}
+
+SECTION_CAR_TEXT
+uint32_t car_reg_rd_val(uint32_t offset, uint32_t mask) {
+    uint32_t val;
+
+    val = readl(car_reg(offset));
+    val &= mask;
+    val >>= car_reg_msk2shft(mask);
+    return val;
+}
+
+SECTION_CAR_TEXT
+uint32_t car_reg_rdwr_val(uint32_t offset, uint32_t mask, uint32_t val) {
+    uint32_t shift;
+
+    if (mask != 0) {
+        shift = car_reg_msk2shft(mask);
+        if (val > (mask >> shift)) {
+            val = mask >> shift;
+        }
+    } else {
+        shift = 0;
+    }
+
+    return car_reg_rdwr(offset, val << shift, mask);
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
diff --git a/spe-freertos-bsp/fsp/source/drivers/car/car-rst.c b/spe-freertos-bsp/fsp/source/drivers/car/car-rst.c
new file mode 100644
index 0000000..4f0f484
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/car/car-rst.c
@@ -0,0 +1,146 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stddef.h>                     // for NULL
+#include <stdbool.h>                    // for bool, false
+#include <stdint.h>                     // for uint32_t, uint8_t, UINT8_MAX, UIN...
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD...
+#include <error/common-errors.h>        // for E_SUCCESS, error_t
+
+/* Module-specific FSP headers */
+#include <car/car-sections.h>           // for SECTION_CAR_TEXT, ...
+#include <car/car-errors.h>             // for E_CAR_ERR_NULL_PTR, E_CAR_ERR_NO_...
+#include <car/car-reg.h>                // for register access functions...
+#include <car/car-rst.h>                // for reset declarations...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_REG_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_RST_H, "Header file missing or invalid.")
+
+
+SECTION_CAR_TEXT
+static bool car_rst_op_is_asserted(const struct car_rst_inf *rst)
+{
+    bool ret = false;
+
+    if (rst != NULL) {
+        if ((car_reg_rd(rst->reg) & rst->msk) != 0U)
+            ret = true;
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+static error_t car_rst_op_assert_bit(const struct car_rst_inf *rst)
+{
+    error_t ret = E_CAR_INVALID_RESET_ID;
+
+    if (rst != NULL) {
+        car_reg_rdwr(rst->reg, rst->msk, rst->msk);
+        ret = E_SUCCESS;
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+static error_t car_rst_op_deassert_bit(const struct car_rst_inf *rst)
+{
+    error_t ret = E_CAR_INVALID_RESET_ID;
+
+    if (rst != NULL) {
+        car_reg_rdwr(rst->reg, 0U, rst->msk);
+        ret = E_SUCCESS;
+    }
+    return ret;
+}
+
+SECTION_CAR_RODATA
+const struct car_rst_op car_rst_op_bit = {
+    .rst_is_asserted = car_rst_op_is_asserted,
+    .rst_assert = car_rst_op_assert_bit,
+    .rst_deassert = car_rst_op_deassert_bit,
+};
+
+
+SECTION_CAR_TEXT
+static error_t car_rst_op_assert_reg(const struct car_rst_inf *rst)
+{
+    error_t ret = E_CAR_INVALID_RESET_ID;
+
+    if (rst != NULL) {
+        car_reg_wr(rst->reg + 0x04U, rst->msk);
+        ret = E_SUCCESS;
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+static error_t car_rst_op_deassert_reg(const struct car_rst_inf *rst)
+{
+    error_t ret = E_CAR_INVALID_RESET_ID;
+
+    if (rst != NULL) {
+        car_reg_wr(rst->reg + 0x08U, rst->msk);
+        ret = E_SUCCESS;
+    }
+    return ret;
+}
+
+SECTION_CAR_RODATA
+const struct car_rst_op car_rst_op_reg = {
+    .rst_is_asserted = car_rst_op_is_asserted,
+    .rst_assert = car_rst_op_assert_reg,
+    .rst_deassert = car_rst_op_deassert_reg,
+};
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
diff --git a/spe-freertos-bsp/fsp/source/drivers/car/module-car-nosafety-config.mk b/spe-freertos-bsp/fsp/source/drivers/car/module-car-nosafety-config.mk
new file mode 100644
index 0000000..95c77be
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/car/module-car-nosafety-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-car-nosafety-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-osa*.mk' files.
+MODULE_CAR_NOSAFETY_CONFIG              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_CAR_NOSAFETY_DEPENDS             := SOC CLUSTER CPL OSA FSP_COMMON
+$(foreach _,$(MODULE_CAR_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_CAR_NOSAFETY_DRIVERS_DIR		     = $(FSP_COMMON_REPO)/drivers/car
+MODULE_CAR_NOSAFETY_SOURCE_DIR		     = $(MODULE_CAR_NOSAFETY_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_CAR_NOSAFETY_INCLUDES             =
diff --git a/spe-freertos-bsp/fsp/source/drivers/car/module-car-nosafety.mk b/spe-freertos-bsp/fsp/source/drivers/car/module-car-nosafety.mk
new file mode 100644
index 0000000..38007fa
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/car/module-car-nosafety.mk
@@ -0,0 +1,73 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-car-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_CAR_NOSAFETY_NAME                := CAR_NOSAFETY
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_CAR_NOSAFETY_DEFINED             := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_CAR_NOSAFETY_DEPENDS             := CAR_NOSAFETY SOC CPL OSA
+$(foreach _,$(CONFIG_CAR_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_CAR_NOSAFETY_C_SRC		         =
+MODULE_CAR_NOSAFETY_C_SRC               += $(MODULE_CAR_NOSAFETY_DRIVERS_DIR)/car-reg.c
+MODULE_CAR_NOSAFETY_C_SRC               += $(MODULE_CAR_NOSAFETY_DRIVERS_DIR)/car-math.c
+MODULE_CAR_NOSAFETY_C_SRC               += $(MODULE_CAR_NOSAFETY_DRIVERS_DIR)/car-rst.c
+MODULE_CAR_NOSAFETY_C_SRC               += $(MODULE_CAR_NOSAFETY_DRIVERS_DIR)/car-clk.c
+MODULE_CAR_NOSAFETY_C_SRC               += $(MODULE_CAR_NOSAFETY_DRIVERS_DIR)/car-pll.c
+MODULE_CAR_NOSAFETY_C_SRC               += $(MODULE_CAR_NOSAFETY_DRIVERS_DIR)/car-hpll.c
+MODULE_CAR_NOSAFETY_C_SRC               += $(MODULE_CAR_NOSAFETY_DRIVERS_DIR)/car-fmon.c
+MODULE_CAR_NOSAFETY_C_SRC		        += $(CPL_SOC_PORT)/car-port.c
+MODULE_CAR_NOSAFETY_C_SRC		        += $(CPL_SOC_PORT)/fsi-car-rst.c
+MODULE_CAR_NOSAFETY_C_SRC		        += $(CPL_SOC_PORT)/fsi-car-clk.c
+MODULE_CAR_NOSAFETY_C_SRC		        += $(CPL_SOC_PORT)/fsi-car-pll.c
+MODULE_CAR_NOSAFETY_C_SRC		        += $(CPL_SOC_PORT)/fsi-car-fmon.c
+
+#
+# Assembly source
+MODULE_CAR_NOSAFETY_ASM_SRC              =
+
+#
+# Special C Flags
+MODULE_CAR_NOSAFETY_C_FLAGS              =
+
+#
+# Special ASM Flags
+MODULE_CAR_NOSAFETY_ASM_FLAGS            =
diff --git a/spe-freertos-bsp/fsp/source/drivers/chipid/chip-id.c b/spe-freertos-bsp/fsp/source/drivers/chipid/chip-id.c
new file mode 100644
index 0000000..c2cd5c8
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/chipid/chip-id.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                   // for uint8_t, uint32_t
+#include <stdbool.h>                  // for false, bool, true
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>           // for CT_ASSERT
+#include <soc-common/hw-const.h>      /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>          // for NV_ADDRESS_MAP_FUSE_BASE, NV_AD...
+
+/* Late FSP headers */
+#include <misc/macros.h>              // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <reg-access/reg-access.h>    // for readl, FSP__REG_ACCESS__REG_ACC...
+
+/* Module-specific FSP headers */
+#include <chipid/chip-id.h>           // for FSP__CHIPID__CHIP_ID_H, tegra_g...
+#include <chipid/sections-chip-id.h>  // Immune from CT_ASSERT protection
+
+#include <soc-common/chipid-tegra-hw.h> // TEGRA_FUSE_ADDRESS_MAP_SIZE
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CHIPID__CHIP_ID_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+#define MISCREG_HIDREV_0              4U
+
+#define HIDREV_0_MAJORREV_SHIFT       4U
+#define HIDREV_0_CHIPID_SHIFT         8U
+#define HIDREV_0_MINORREV_SHIFT      16U
+#define HIDREV_0_PLATFORM_SHIFT      20U
+#define HIDREV_0_PLATFORM_SHIFT      20U
+#define HIDREV_0_PLATFORM_SILICON     0U
+#define HIDREV_0_PLATFORM_FPGA        2U
+#define HIDREV_0_PLATFORM_VDK         8U
+
+#define HIDREV_0_MAJORREV_MASK       ((uint32_t)0xf << HIDREV_0_MAJORREV_SHIFT)
+#define HIDREV_0_CHIPID_MASK          ((uint32_t)0xff << HIDREV_0_CHIPID_SHIFT)
+#define HIDREV_0_MINORREV_MASK       ((uint32_t)0xf << HIDREV_0_MINORREV_SHIFT)
+#define HIDREV_0_PLATFORM_MASK       ((uint32_t)0xf << HIDREV_0_PLATFORM_SHIFT)
+
+#define FUSE_OPT_SUBREVISION_0    0x248U
+#define FUSE_OPT_SUBREVISION_SHIFT    0U
+#define FUSE_OPT_SUBREVISION_MASK ((uint32_t)0xf << FUSE_OPT_SUBREVISION_SHIFT)
+
+#define FUSE_SKU_INFO_0           0x110U
+#define FUSE_SKU_INFO_SHIFT           0U
+#define FUSE_SKU_INFO_MASK              ((uint32_t)0xff << FUSE_SKU_INFO_SHIFT)
+
+/**
+ * @brief ChipID information.
+ *
+ * @chip_id Chip ID value.
+ * @major_rev Chip major revision.
+ * @minor_rev Chip minor revision.
+ * @sub_rev  Chip sub revision.
+ * @sku_id  Chip SKU ID.
+ * @platform_is_silicon Specifies whether platform is silicon or not.
+ * @chip_data_initialized Specifies whether chip data is initialized or not.
+ *
+ */
+struct chip_info {
+    uint8_t chip_id;
+    uint8_t major_rev;
+    uint8_t minor_rev;
+    uint8_t sub_rev;
+    uint8_t sku_id;
+    bool platform_is_silicon;
+    bool platform_is_fpga;
+    bool platform_is_vdk;
+    bool chip_data_initialized;
+};
+
+static struct chip_info chip_data SECTION_CHIPID_DATA = {
+    .platform_is_silicon = (bool)false,
+    .chip_data_initialized = (bool)false,
+};
+
+static SECTION_CHIPID_INIT_TEXT void tegra_chipid_init(void)
+{
+    uint32_t val;
+
+    val = readl((uint32_t)NV_ADDRESS_MAP_MISC_BASE + MISCREG_HIDREV_0);
+
+    /* Get chip ID */
+    INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-559, DR: SWE-FSP-048-SWSADR.docx");
+    chip_data.chip_id = (uint8_t)((uint32_t)(val & HIDREV_0_CHIPID_MASK) >> HIDREV_0_CHIPID_SHIFT);
+
+    /* Get Major Revision */
+    INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-559, DR: SWE-FSP-048-SWSADR.docx");
+    chip_data.major_rev = (uint8_t)((uint32_t)(val & HIDREV_0_MAJORREV_MASK) >> HIDREV_0_MAJORREV_SHIFT);
+
+    /* Get Minor Revision */
+    INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-559, DR: SWE-FSP-048-SWSADR.docx");
+    chip_data.minor_rev = (uint8_t)((uint32_t)(val & HIDREV_0_MINORREV_MASK) >> HIDREV_0_MINORREV_SHIFT);
+
+    if (HIDREV_0_PLATFORM_SILICON == ((uint32_t)(val & HIDREV_0_PLATFORM_MASK) >> HIDREV_0_PLATFORM_SHIFT)) {
+        chip_data.platform_is_silicon = true;
+    }
+
+    if (HIDREV_0_PLATFORM_FPGA == ((uint32_t)(val & HIDREV_0_PLATFORM_MASK) >> HIDREV_0_PLATFORM_SHIFT)) {
+        chip_data.platform_is_fpga = true;
+    }
+
+    if (HIDREV_0_PLATFORM_VDK == ((uint32_t)(val & HIDREV_0_PLATFORM_MASK) >> HIDREV_0_PLATFORM_SHIFT)) {
+        chip_data.platform_is_vdk = true;
+    }
+
+    /* Get Sub Revision from Fuse*/
+    val = readl((uint32_t)NV_ADDRESS_MAP_FUSE_BASE + FUSE_OPT_SUBREVISION_0);
+    INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-559, DR: SWE-FSP-048-SWSADR.docx");
+    chip_data.sub_rev = (uint8_t)((val & FUSE_OPT_SUBREVISION_MASK) >> FUSE_OPT_SUBREVISION_SHIFT);
+
+    /* Get SKU Info from Fuse*/
+    val = readl((uint32_t)NV_ADDRESS_MAP_FUSE_BASE + FUSE_SKU_INFO_0);
+    INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-559, DR: SWE-FSP-048-SWSADR.docx");
+    chip_data.sku_id = (uint8_t)((val & FUSE_SKU_INFO_MASK) >> FUSE_SKU_INFO_SHIFT);
+
+    chip_data.chip_data_initialized = true;
+}
+
+SECTION_CHIPID_TEXT uint16_t tegra_get_platform(void)
+{
+    uint8_t chip_id = tegra_get_chipid();
+    uint8_t major = tegra_get_major_rev();
+
+    return ((((uint16_t)chip_id) << 4U) | major);
+}
+
+SECTION_CHIPID_TEXT uint8_t tegra_get_chipid(void)
+{
+    /* Check if chip data is initialized or not */
+    if (chip_data.chip_data_initialized == false) {
+        tegra_chipid_init();
+    }
+
+    return chip_data.chip_id;
+}
+
+SECTION_CHIPID_TEXT uint8_t tegra_get_major_rev(void)
+{
+    /* Check if chip data is initialized or not */
+    if (chip_data.chip_data_initialized == false) {
+        tegra_chipid_init();
+    }
+
+    return chip_data.major_rev;
+}
+
+SECTION_CHIPID_TEXT uint8_t tegra_get_minor_rev(void)
+{
+    /* Check if chip data is initialized or not */
+    if (chip_data.chip_data_initialized == false) {
+        tegra_chipid_init();
+    }
+
+    return chip_data.minor_rev;
+}
+
+SECTION_CHIPID_TEXT bool tegra_platform_is_silicon(void)
+{
+    /* Check if chip data is initialized or not */
+    if (chip_data.chip_data_initialized == false) {
+        tegra_chipid_init();
+    }
+
+    return chip_data.platform_is_silicon;
+}
+
+SECTION_CHIPID_TEXT bool tegra_platform_is_vdk(void)
+{
+    /* Check if chip data is initialized or not */
+    if (chip_data.chip_data_initialized == false) {
+        tegra_chipid_init();
+    }
+
+    return chip_data.platform_is_vdk;
+}
+
+SECTION_CHIPID_TEXT bool tegra_platform_is_fpga(void)
+{
+    /* Check if chip data is initialized or not */
+    if (chip_data.chip_data_initialized == false) {
+        tegra_chipid_init();
+    }
+
+    return chip_data.platform_is_fpga;
+}
+
+SECTION_CHIPID_TEXT uint8_t tegra_get_sub_rev(void)
+{
+    /* Check if chip data is initialized or not */
+    if (chip_data.chip_data_initialized == false) {
+        tegra_chipid_init();
+    }
+
+    return chip_data.sub_rev;
+}
+
+SECTION_CHIPID_TEXT uint8_t tegra_get_sku_id(void)
+{
+    /* Check if chip data is initialized or not */
+    if (chip_data.chip_data_initialized == false) {
+        tegra_chipid_init();
+    }
+
+    return chip_data.sku_id;
+}
+
+SECTION_CHIPID_TEXT bool tegra_fuse_control_read(uint32_t offset, uint32_t *val)
+{
+    bool ret = false;
+
+    if (!val) {
+        goto out;
+    }
+
+    if (offset >= TEGRA_FUSE_ADDRESS_MAP_SIZE) {
+        *val = 0U;
+        goto out;
+    }
+
+    *val = readl((uint32_t)NV_ADDRESS_MAP_FUSE_BASE + offset);
+    ret = true;
+
+out:
+    return ret;
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/chipid/module-chipid-config.mk b/spe-freertos-bsp/fsp/source/drivers/chipid/module-chipid-config.mk
new file mode 100644
index 0000000..1d49ccb
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/chipid/module-chipid-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-chipid-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_CHIPID_CONFIG            := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_CHIPID_DEPENDS           := SOC CLUSTER CPL OSA FSP_COMMON
+$(foreach _,$(MODULE_CHIPID_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_CHIPID_DRIVERS_DIR        = $(FSP_COMMON_REPO)/drivers/chipid
+MODULE_CHIPID_SOURCE_DIR         = $(MODULE_CHIPID_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_CHIPID_INCLUDES           =
diff --git a/spe-freertos-bsp/fsp/source/drivers/chipid/module-chipid.mk b/spe-freertos-bsp/fsp/source/drivers/chipid/module-chipid.mk
new file mode 100644
index 0000000..d58e92e
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/chipid/module-chipid.mk
@@ -0,0 +1,62 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-chipid.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_CHIPID_NAME              := CHIPID
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_CHIPID_DEFINED           := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_CHIPID_DEPENDS           := CHIPID SOC
+$(foreach _,$(CONFIG_CHIPID_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_CHIPID_C_SRC              =
+MODULE_CHIPID_C_SRC             += $(MODULE_CHIPID_DRIVERS_DIR)/chip-id.c
+
+#
+# Assembly source
+MODULE_CHIPID_ASM_SRC            =
+
+#
+# Special C Flags
+MODULE_CHIPID_C_FLAGS            =
+
+#
+# Special ASM Flags
+MODULE_CHIPID_ASM_FLAGS          =
diff --git a/spe-freertos-bsp/fsp/source/drivers/comb-uart/comb-uart-client.c b/spe-freertos-bsp/fsp/source/drivers/comb-uart/comb-uart-client.c
new file mode 100644
index 0000000..03a299d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/comb-uart/comb-uart-client.c
@@ -0,0 +1,404 @@
+/*
+ * Copyright (c) 2021-2023 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/* Compiler headers */
+#include <stdbool.h>                         // for true
+#include <stdint.h>                          // for uint32_t
+#include <stddef.h>                          // for NULL
+
+/* HW headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                  // for CT_ASSERT
+#include <soc-common/hw-const.h>             /* Must appear before any hwinc files */
+
+/* Late FSP headers */
+#include <error/common-errors.h>             // for E_SUCCESS, error_t, FSP_...
+#include <misc/attributes.h>                 // for FSP__MISC__ATTRIBUTES_H
+#include <misc/bitops.h>                     // for BIT
+#include <reg-access/reg-access.h>           // for readl, writel, FSP__REG_...
+#include <delay/delay.h>                     // for get_time_ticks
+#include <irq/safe-irqs.h>                   // for irq_safe_enable, irq_safe_disable..
+#include <tke/tke-tegra.h>
+#include <cpu/barriers.h>
+
+/* Module-specific FSP headers */
+#include <comb-uart/sections-comb-uart.h>    // Immune from CT_ASSERT protection
+#include <comb-uart/comb-uart-errors.h>      // for E_COMB_UART_...
+#include <comb-uart/comb-uart.h>             // for comb_uart_init, comb_uart...
+#include <comb-uart/comb-uart-priv.h>        // for comb_uart_id...
+#include <comb-uart/comb-uart-port.h>        // for comb_uart_port_...
+
+/* Shared mailbox protocol bits */
+#define COMB_UART_PKT_SIZE_SHIFT    (24U)
+#define COMB_UART_PKT_FLUSH_BIT     BIT(26U)
+#define COMB_UART_PKT_TAG_BIT       BIT(31U)
+#define COMB_UART_MAX_PKTS          (3U)
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__DELAY__DELAY_H, "Header file missing or invalid.")
+
+/* RX/TX timeout */
+#define COMB_UART_TIMEOUT_USEC          (10000UL)
+#define COMB_UART_TIMEOUT_WAIT_USEC     (10UL)
+
+/* init timeout */
+#define COMB_UART_INIT_TIMEOUT_USEC     (500000UL)
+
+/* status flags for tx and rx enable */
+static bool tx_enabled                  SECTION_COMB_UART_DATA = false;
+static bool rx_enabled                  SECTION_COMB_UART_DATA = false;
+
+/* tx buffer and number of bytes in the tx buf */
+static char tx_buf[64]                  SECTION_COMB_UART_DATA;
+static uint32_t tx_bytes                SECTION_COMB_UART_DATA = 0;
+
+/**
+ * Helper function to wait for mailbox tag bit to be cleared.
+ */
+SECTION_COMB_UART_TEXT bool
+comb_uart_is_tx_ready(const struct comb_uart_id *id)
+{
+    uint32_t val;
+
+    val = readl(id->tx_sm_reg);
+
+    return (val & COMB_UART_PKT_TAG_BIT) == 0UL;
+}
+
+/**
+ * Helper function to wait for mailbox tag bit to be cleared for specified
+ * timeout.
+ */
+static inline error_t
+comb_uart_wait_tx_timeout(const struct comb_uart_id *id,
+                          const uint64_t timeout_usec)
+{
+    error_t  ret = E_SUCCESS;
+    uint64_t tcurr = 0ULL;
+    uint64_t start;
+
+    if (!comb_uart_is_tx_ready(id)) {
+        ret = E_COMB_UART_TIMEDOUT;
+        start = comb_uart_port_get_elapsed_usecs(0ULL);
+
+        do {
+            if (comb_uart_is_tx_ready(id)) {
+                ret = E_SUCCESS;
+                break;
+            }
+
+            tcurr = comb_uart_port_get_elapsed_usecs(0ULL);
+
+        } while ((tcurr - start) < timeout_usec);
+    }
+
+    return ret;
+}
+
+/**
+ * Helper function to wait for mailbox tag bit to be cleared or return
+ * timeout.
+ */
+static inline error_t
+comb_uart_wait_tx(const struct comb_uart_id *id)
+{
+    return comb_uart_wait_tx_timeout(id, COMB_UART_TIMEOUT_USEC);
+}
+
+/**
+ * Helper function to create a tx packet to be sent to SPE adhering
+ * to the combined uart protocol.
+ */
+static inline uint32_t
+comb_uart_get_tx_val(const struct comb_uart_id *id,
+                     const char *buf,
+                     const uint32_t buf_size,
+                     const bool flush)
+{
+    uint32_t to_write;
+    uint32_t tx;
+    uint32_t ch;
+
+    to_write = buf_size;
+
+    /* Initialize TX value */
+    tx = COMB_UART_PKT_TAG_BIT |
+         (flush ? COMB_UART_PKT_FLUSH_BIT : 0u) |
+         (to_write << COMB_UART_PKT_SIZE_SHIFT);
+
+    /* Add the characters into the TX value */
+    for (uint32_t i = 0U; i < to_write; i += 1UL) {
+        ch = (uint8_t)buf[i];
+        tx |= ch << (i * 8U);
+    }
+
+    return tx;
+}
+
+/**
+ * Helper function to write 1-3 characters to SPE, wait for mailbox
+ * tag bit to be  cleared and return how many bytes were written or
+ * E_COMB_UART_TIMEDOUT if transfer timed out.
+ */
+SECTION_COMB_UART_TEXT static error_t
+comb_uart_write(const struct comb_uart_id *id,
+                const char *buf,
+                const uint32_t nbytes,
+                const bool flush,
+                uint32_t *written)
+{
+    error_t  ret;
+    uint32_t to_write;
+    uint32_t tx;
+
+    to_write = (nbytes > COMB_UART_MAX_PKTS) ? COMB_UART_MAX_PKTS : nbytes;
+
+    /* Initialize TX value */
+    tx = comb_uart_get_tx_val(id, buf, to_write, flush);
+
+    /* Write to SPE mailbox */
+    writel(tx, id->tx_sm_reg);
+
+    /* Wait for SPE mailbox to be cleared */
+    ret = comb_uart_wait_tx(id);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    /* update the chars written */
+    *written = to_write;
+
+out:
+    return ret;
+}
+
+SECTION_COMB_UART_TEXT void
+comb_uart_putc_now(const struct comb_uart_id *id,
+                   const char ch)
+{
+    uint32_t            tx;
+
+    tx = COMB_UART_PKT_TAG_BIT | COMB_UART_PKT_FLUSH_BIT
+         | (1U << COMB_UART_PKT_SIZE_SHIFT)
+         | (uint32_t)ch;
+
+    /* Write to SPE mailbox */
+    writel(tx, id->tx_sm_reg);
+
+    /* Wait until character has been seen */
+    while (!comb_uart_is_tx_ready(id)) {
+    }
+}
+
+SECTION_COMB_UART_TEXT static error_t
+comb_uart_flush(const struct comb_uart_id *id,
+                const bool wait)
+{
+    error_t    ret = E_SUCCESS;
+    const char *src;
+    uint32_t   nbytes;
+    uint32_t   written = 0UL;
+
+    if (!tx_enabled) {
+        ret = E_COMB_UART_NO_TX;
+        goto out;
+    }
+
+    nbytes = tx_bytes;
+    if (nbytes > 0u) {
+        src = tx_buf;
+        do {
+            ret = comb_uart_write(id, src, nbytes, false, &written);
+            if (ret != E_SUCCESS) {
+                ret = E_COMB_UART_TIMEDOUT;
+                break;
+            }
+            nbytes -= written;
+            src = &src[written];
+        } while (nbytes > 0u);
+
+        /*
+         * XXX: If there's a timeout, does this just throw away the
+         * un-sent characters?
+         */
+
+        /* Send the flush bit if requested */
+        tx_bytes = 0;
+        if (wait) {
+            UNUSED(comb_uart_write(id, src, 0u, wait, &written));
+        }
+    }
+
+out:
+    return ret;
+}
+
+SECTION_COMB_UART_TEXT error_t
+comb_uart_tx_flush(const struct comb_uart_id *id)
+{
+    return comb_uart_flush(id, true);
+}
+
+SECTION_COMB_UART_TEXT error_t
+comb_uart_putc(const struct comb_uart_id *id,
+               const char ch)
+{
+    error_t ret = E_SUCCESS;
+
+    enter_critical();
+
+    /* Push character to TX buffer */
+    tx_buf[tx_bytes++] = ch;
+
+    /* Flush on newline or if buffer is full */
+    if ((ch == '\n') || (tx_bytes == sizeof(tx_buf))) {
+        ret = comb_uart_flush(id, false);
+    }
+
+    exit_critical();
+
+    return ret;
+}
+
+SECTION_COMB_UART_TEXT bool
+comb_uart_tx_ready(const struct comb_uart_id *id)
+{
+    return tx_bytes < sizeof(tx_buf);
+}
+
+SECTION_COMB_UART_TEXT void
+comb_uart_puts(const struct comb_uart_id *id,
+               const char *s)
+{
+    while (*s != '\0') {
+        UNUSED(comb_uart_putc(id, *s++));
+    }
+}
+
+SECTION_COMB_UART_TEXT void
+comb_uart_send(const struct comb_uart_id *id,
+               const char *d,
+               const uint32_t len)
+{
+    uint32_t i;
+
+    for (i = 0UL; i < len; i += 1UL) {
+        UNUSED(comb_uart_putc(id, *d++));
+    }
+}
+
+SECTION_COMB_UART_INIT_TEXT static error_t
+comb_uart_tx_init(const struct comb_uart_id *id)
+{
+    error_t    ret = E_SUCCESS;
+    uint32_t   tx;
+    const char ch = '\n';
+
+    /* if no tx hsp sm register, return with an error */
+    if (id->tx_sm_reg == 0UL) {
+        ret = E_COMB_UART_NULL_PTR;
+        goto out;
+    }
+
+    /**
+     * check to ensure combined uart server is alive by sending
+     * a '\n' char.
+     */
+    tx = comb_uart_get_tx_val(id, &ch, 1, false);
+    writel(tx, id->tx_sm_reg);
+
+    /**
+     * wait for server to clear the mailbox. If
+     * the wait times out, server did not respond and tx failed.
+     */
+    ret = comb_uart_wait_tx_timeout(id, COMB_UART_INIT_TIMEOUT_USEC);
+    if (ret != E_SUCCESS) {
+        tx_enabled = false;
+        goto out;
+    }
+
+    tx_enabled = true;
+
+out:
+    return ret;
+}
+
+SECTION_COMB_UART_INIT_TEXT static error_t
+comb_uart_rx_init(const struct comb_uart_id *id)
+{
+    error_t ret = E_SUCCESS;
+
+    /* okay to not use rx */
+    if (id->supports_rx) {
+        if (id->rx_sm_reg == 0UL) {
+            ret = E_COMB_UART_NULL_PTR;
+            goto out;
+        } else {
+            rx_enabled = true;
+        }
+    }
+
+out:
+    return ret;
+}
+
+SECTION_COMB_UART_INIT_TEXT error_t
+comb_uart_init(const struct comb_uart_id *id)
+{
+    error_t ret = E_SUCCESS;
+
+    ret = comb_uart_tx_init(id);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    ret = comb_uart_rx_init(id);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+out:
+    return ret;
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/comb-uart/comb-uart-ops.c b/spe-freertos-bsp/fsp/source/drivers/comb-uart/comb-uart-ops.c
new file mode 100644
index 0000000..41cfa4f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/comb-uart/comb-uart-ops.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                // for uint32_t
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>        // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>   // for E_SUCCESS, error_t
+#include <misc/macros.h>           // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <comb-uart/comb-uart.h>   // for comb_uart_...
+
+/* Module-specific FSP headers */
+#include <debug/debug-uart.h>      // for dbg_uart_ops...
+#include <debug/sections-debug.h>  // Immune from CT_ASSERT protection
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__COMB_UART__COMB_UART_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+static inline error_t
+dbg_comb_uart_init(void *data)
+{
+    const struct comb_uart_id *id = (const struct comb_uart_id *)data;
+
+    return comb_uart_init(id);
+}
+
+static inline void
+dbg_comb_uart_putc(void *data,
+                   const char ch)
+{
+    const struct comb_uart_id *id = (const struct comb_uart_id *)data;
+
+    comb_uart_putc(id, ch);
+}
+
+static inline void
+dbg_comb_uart_puts(void *data,
+                   const char *s)
+{
+    const struct comb_uart_id *id = (const struct comb_uart_id *)data;
+
+    comb_uart_puts(id, s);
+}
+
+static inline void
+dbg_comb_uart_putd(void *data,
+                   const char *d,
+                   uint32_t len)
+{
+    const struct comb_uart_id *id = (const struct comb_uart_id *)data;
+
+    comb_uart_send(id, d, len);
+}
+
+static inline void
+dbg_comb_uart_tx_flush(void *data)
+{
+    const struct comb_uart_id *id = (const struct comb_uart_id *)data;
+
+    comb_uart_tx_flush(id);
+}
+
+static inline bool
+dbg_comb_uart_tx_ready(void *data)
+{
+    const struct comb_uart_id *id = (const struct comb_uart_id *)data;
+
+    return comb_uart_tx_ready(id);
+}
+
+const struct dbg_uart_ops dbg_comb_uart_ops = {
+    .init     = &dbg_comb_uart_init,
+    .putc     = &dbg_comb_uart_putc,
+    .putd     = &dbg_comb_uart_putd,
+    .puts     = &dbg_comb_uart_puts,
+    .flush    = &dbg_comb_uart_tx_flush,
+    .tx_ready = &dbg_comb_uart_tx_ready,
+};
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/comb-uart/module-comb-uart-nosafety-config.mk b/spe-freertos-bsp/fsp/source/drivers/comb-uart/module-comb-uart-nosafety-config.mk
new file mode 100644
index 0000000..2a2038f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/comb-uart/module-comb-uart-nosafety-config.mk
@@ -0,0 +1,41 @@
+#
+# Copyright (c) 2020-2021 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-comb-uart-nosafety-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-osa*.mk' files.
+MODULE_COMB_UART_NOSAFETY_CONFIG        := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_COMB_UART_NOSAFETY_DEPENDS       := SOC CLUSTER CPL FSP_COMMON
+$(foreach _,$(MODULE_COMB_UART_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_COMB_UART_NOSAFETY_SOURCE_DIR     = $(FSP_COMMON_REPO)/drivers/comb-uart
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_COMB_UART_NOSAFETY_INCLUDES       =
diff --git a/spe-freertos-bsp/fsp/source/drivers/comb-uart/module-comb-uart-nosafety.mk b/spe-freertos-bsp/fsp/source/drivers/comb-uart/module-comb-uart-nosafety.mk
new file mode 100644
index 0000000..576ae89
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/comb-uart/module-comb-uart-nosafety.mk
@@ -0,0 +1,65 @@
+#
+# Copyright (c) 2021-2022 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-comb-uart-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_COMB_UART_NOSAFETY_NAME          := COMB_UART_NOSAFETY
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_COMB_UART_NOSAFETY_DEFINED       := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_COMB_UART_NOSAFETY_DEPENDS       := COMB_UART_NOSAFETY SOC CPL
+$(foreach _,$(CONFIG_COMB_UART_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_COMB_UART_NOSAFETY_C_SRC          =
+MODULE_COMB_UART_NOSAFETY_C_SRC         += $(MODULE_COMB_UART_NOSAFETY_SOURCE_DIR)/comb-uart-client.c
+MODULE_COMB_UART_NOSAFETY_C_SRC		+= $(MODULE_COMB_UART_NOSAFETY_SOURCE_DIR)/comb-uart-ops.c
+MODULE_COMB_UART_NOSAFETY_C_SRC         += $(CPL_SOC_IDS)/comb-uart-ids.c
+MODULE_COMB_UART_NOSAFETY_C_SRC         += $(CPL_SOC_PORT)/comb-uart-port.c
+
+#
+# Assembly source
+MODULE_COMB_UART_NOSAFETY_ASM_SRC        =
+
+#
+# Special C Flags
+MODULE_COMB_UART_NOSAFETY_C_FLAGS        =
+
+#
+# Special ASM Flags
+MODULE_COMB_UART_NOSAFETY_ASM_FLAGS      =
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/armv7-exception.c b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/armv7-exception.c
new file mode 100644
index 0000000..46cc352
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/armv7-exception.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2018-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                        // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+#include <misc/attributes.h>               // for UNUSED, WEAK
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <debug/abort-sys-codes.h>         // for ABORT_EXCEPTION, FSP__DEBU...
+#include <debug/abort.h>                   // for tegra_abort, FSP__DEBUG__A...
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <cpu/armv7-exception.h>           // for armv7_exception_t, FSP__AR...
+#include <cpu/armv7-regs.h>                // for rd_adfsr, rd_aifsr, rd_dfar
+#include <cpu/sections-exception.h>        // Immune from CT_ASSERT protection
+#include <cpu/armv7-mpu-regs.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ABORT_SYS_CODES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ABORT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_EXCEPTION_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_REGS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
+/**
+ * exception_hook()     - default exception hook
+ *
+ * @exception:          pointer to an exception structure
+ *
+ * This function is the default exception hook.  It is defined as a weak
+ * function so that if the application doesn't provide an exception hook
+ * this will be called instead.
+ *
+ * Return Values:
+ *      none
+ */
+SECTION_EXCEPTION_TEXT WEAK void
+exception_hook(const armv7_exception_t * const exception)
+{
+    UNUSED((exception->frame->sp));
+    UNUSED((exception));
+}
+
+/**
+ * armv7_exception()    - called when the CPU experiences an exception
+ *
+ * @type:               type of the exception
+ * @frame:              pointer to the exception frame that contains
+ *                      various state about the CPU (registers and such)
+ *
+ * This function is called when the CPU experiences an exception.  It will
+ * take the existing state that is captured by the earlier handler and
+ * adds additional information that may be useful in determining the cause
+ * of the exception.  It will also call an application specific hook to
+ * allow for application specific operations to report the exception.
+ *
+ * Return Values:
+ *      This function does not return
+ */
+SECTION_EXCEPTION_TEXT void
+armv7_exception(uint32_t type, struct armv7_exception_frame *frame)
+{
+    armv7_exception_t       exception;
+
+    r5mpu_disable();
+
+    exception.type  = type;
+    exception.frame = frame;
+    exception.dfar  = rd_dfar();
+    exception.dfsr  = rd_dfsr();
+    exception.adfsr = rd_adfsr();
+    exception.ifar  = rd_ifar();
+    exception.ifsr  = rd_ifsr();
+    exception.aifsr = rd_aifsr();
+
+    exception_hook(&exception);
+
+    tegra_abort(ABORT_EXCEPTION, type);
+
+    /* Not Reached */
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/armv7-exceptions.S b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/armv7-exceptions.S
new file mode 100644
index 0000000..6b4db62
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/armv7-exceptions.S
@@ -0,0 +1,147 @@
+@
+@ Copyright (c) 2015-2020, NVIDIA CORPORATION.  All rights reserved.
+@
+@ Redistribution and use in source and binary forms, with or without
+@ modification, are permitted provided that the following conditions
+@ are met:
+@  * Redistributions of source code must retain the above copyright
+@    notice, this list of conditions and the following disclaimer.
+@  * Redistributions in binary form must reproduce the above copyright
+@    notice, this list of conditions and the following disclaimer in the
+@    documentation and/or other materials provided with the distribution.
+@  * Neither the name of NVIDIA CORPORATION nor the names of its
+@    contributors may be used to endorse or promote products derived
+@    from this software without specific prior written permission.
+@
+@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+@ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+@ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+@ PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+@ CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+@ EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+@ PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+@ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+@ OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+@ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+@
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <asm/asm.h>
+
+/* Module-specific FSP headers */
+#include <cpu/armv7-exception.h>
+#include <cpu/sections-exception.h>
+
+#define MODE_MASK 0x1f
+#define MODE_FIQ 0x11
+#define MODE_IRQ 0x12
+#define MODE_SVC 0x13
+#define MODE_ABT 0x17
+#define MODE_UND 0x1b
+#define MODE_SYS 0x1f
+
+#define THUMB_BIT 0x20
+
+.extern armv7_exception
+	.section	SECTION_NAME_EXCEPTION_TEXT, "ax"
+	.arm
+	.syntax		unified
+	.align 4
+FUNCTION(_Data_Abort_Handler)
+	sub lr, lr, #8
+	stmfd sp!, {r0-r12, lr}
+	mov r0, #DATA_ABORT
+	b common_handler
+END_FUNCTION(_Data_Abort_Handler)
+
+FUNCTION(_Prefetch_Abort_Handler)
+	sub lr, lr, #4
+	stmfd sp!, {r0-r12, lr}
+	mov r0, #PREFETCH_ABORT
+	b common_handler
+END_FUNCTION(_Prefetch_Abort_Handler)
+
+FUNCTION(_Undefined_Instruction_Handler)
+	stmfd sp!, {r0-r12, lr}
+	mov r0, #UNDEFINED_INSTRUCTION
+	@ Update lr:
+	sub lr, lr, #4
+	mrs r4, spsr
+	tst r4, #THUMB_BIT
+	beq 1f
+	@ Thumb mode, fix lr offset:
+	add lr, lr, #2
+1:
+	str lr, [sp, #52]
+	b common_handler
+END_FUNCTION(_Undefined_Instruction_Handler)
+
+@ r0: exception type
+@ r1: exception frame/saved registers
+@ r2: temporary cpsr to change modes
+@ r3: saved cpsr
+@ r4: spsr
+common_handler:
+	mrs r4, spsr
+	stmfd sp!, {r4}
+	mrs r3, cpsr
+	bic r2, r3, #MODE_MASK
+	mov r1, sp
+
+	bic r4, #~MODE_MASK
+	teq r4, #MODE_FIQ
+	beq mode_fiq
+	teq r4, #MODE_IRQ
+	beq mode_irq
+	teq r4, #MODE_SVC
+	beq mode_svc
+	teq r4, #MODE_ABT
+	beq mode_abt
+	teq r4, #MODE_UND
+	beq mode_und
+
+	@ If M field isn't valid, just pretend it's SYS
+	orr r2, r2, #MODE_SYS
+	b common_end
+
+mode_fiq:
+	orr r2, r2, #MODE_FIQ
+	@ FIQ mode also has banked r8-r12. We should fix the saved registers.
+	msr cpsr_c, r2
+	add r5, r1, #36
+	stmea r5, {r8-r12}
+	b common_end
+
+mode_irq:
+	orr r2, r2, #MODE_IRQ
+	b common_end
+
+mode_svc:
+	orr r2, r2, #MODE_SVC
+	b common_end
+
+mode_abt:
+	orr r2, r2, #MODE_ABT
+	b common_end
+
+mode_und:
+	orr r2, r2, #MODE_UND
+
+common_end:
+	msr cpsr_c, r2
+	@ Below 2 lines are quivalent to stmfd r1!, {sp, lr} but armclang compiler
+	@ asserts a warning if sp is used in the list. Hence use 2 str instructions
+	str lr, [r1, #-4]!
+	str sp, [r1, #-4]!
+	msr cpsr_c, r3
+	@ Need to subtract 4 for alignment
+	sub sp, r1, #4
+	blx armv7_exception
+	b .
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/armv7-mpu-asm-dynamic-hdr.c b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/armv7-mpu-asm-dynamic-hdr.c
new file mode 100644
index 0000000..16a52d8
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/armv7-mpu-asm-dynamic-hdr.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2015-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                     // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                        // for U32_C, FSP_MISRA_BLOC...
+#include <misc/generate-asm-hdr.h>              // for ASM_OFFSET macros...
+
+/* Module-specific FSP headers */
+#include <cpu/barriers.h>                       // for barrier_compiler, bar...
+#include <cpu/sections-armv7-mpu.h>             // Immune from CT_ASSERT protection
+#include <ospl/rtos-port.h>                     // for struct mpuParameters...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__GENERATE_ASM_HDR_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__BARRIERS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+
+/**
+ * @file armv7-mpu-asm-hdr.c
+ * @brief Generates the MPU asm/C header defines.
+ */
+
+SECTION_MPU_INIT_TEXT
+void mpuParameters_asm_hdr(void);
+
+void mpuParameters_asm_hdr(void)
+{
+    ASM_OFFSET(MPU_INDEX_OFFSET, struct mpuParameters, index);
+    ASM_OFFSET(MPU_BASE_OFFSET, struct mpuParameters, base);
+    ASM_SIZEOF(MPU_PARM_LENGTH, struct mpuParameters);
+    barrier_compiler();
+}
+
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/armv7-mpu-asm.S b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/armv7-mpu-asm.S
new file mode 100644
index 0000000..d31dd9b
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/armv7-mpu-asm.S
@@ -0,0 +1,192 @@
+/*
+ * Copyright (c) 2015-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <armv7-mpu.h>                                  /* Immune from CT_ASSERT protection */
+#include <cpu/sections-armv7-mpu.h>
+#if defined(MPU_DYNAMIC_HEADERS) && (MPU_DYNAMIC_HEADERS == 1)
+#include "armv7-mpu-asm-dynamic-hdr.h"
+#else
+#include <cpu/armv7-mpu-asm-static-hdr.h>
+#endif
+
+/*
+ * ARMV7_MPU_RESTORE_REGION
+ *
+ * Macro that restores a single MPU region
+ *
+ * Inputs:
+ *      R0:     pointer to mpuParameters_t structure
+ *      R7:     0
+ *
+ * Outputs:
+ *      R0:     pointer to next mpuParameters_t structure
+ *
+ * Registers affected:
+ *      R1, R2, R3
+ */
+        .macro  ARMV7_MPU_RESTORE_REGION
+             LDR        R1, [R0, MPU_INDEX_OFFSET] // get the region index
+             MCR        p15, #0, R1, c6, c2, #0 // set region number
+             MCR        p15, #0, R7, c6, c1, #2 // disable region
+             ADD        R0, R0, MPU_BASE_OFFSET // point to values to be loaded
+             LDMIA      R0!, {R1-R3}            // R0 will point to next struct
+             MCR        p15, #0, R1, c6, c1, #0 // setup base address
+             MCR        p15, #0, R2, c6, c1, #4 // setup access permissions
+             MCR        p15, #0, R3, c6, c1, #2 // setup size
+        .endm
+
+/*
+ * ARMV7_MPU_RESTORE_REGIONS
+ *
+ * Macro to restore a Task's MPU regions.  It is a wrapper that will
+ * invoke ARMV7_MPU_RESTORE_REGION "n" times.
+ *
+ * Inputs:
+ *      R0:     pointer to first element in an array of mpuParameters_t
+ *              structures that represent the MPU regions to be restored
+ *      R7:     0
+ *
+ * Outputs:
+ *      R0:     pointer past the last mpuParameters_t structure of the MPU
+ *              regions being restored.
+ *
+ * Registers affected:
+ *      Registers affected by ARMV7_MPU_RESTORE_REGION
+ */
+        .macro  ARMV7_MPU_RESTORE_REGIONS n
+        .if \n
+        ARMV7_MPU_RESTORE_REGION
+        ARMV7_MPU_RESTORE_REGIONS "(\n-1)"
+        .endif
+        .endm
+
+
+	.section	SECTION_STR_MPU_TEXT, "ax"
+	.arm
+	.syntax		unified
+/*
+ * armv7_task_mpu_restore()	- restores a task's MPU context
+ *
+ * @task_mpu:	pointer to a task_mpu_regions_t structure that represents
+ *		the task's MPU state that is to be restored.  It is expected
+ *		that this pointer is in R0.
+ *
+ * This function will restore the task's MPU context so that the task will
+ * be able to be dispatched and function correctly after a context switch.
+ *
+ * Return Values:
+ *	none
+ */
+	.global		armv7_task_mpu_restore
+	.type		armv7_task_mpu_restore, %function
+	.balign		4
+armv7_task_mpu_restore:
+	PUSH		{ R0, R1, R2, R3, R7, LR }
+	MOV		R7, #0
+	ARMV7_MPU_RESTORE_REGIONS	MPU_NTASK_REGIONS
+	POP		{ R0, R1, R2, R3, R7, PC }
+
+/*
+ * ARMV7_MPU_DISABLE_REGION
+ *
+ * Macro that disables a single MPU region
+ *
+ * Inputs:
+ *      R0:     pointer to mpuParameters_t structure
+ *      R7:     0
+ *
+ * Outputs:
+ *      R0:     pointer to next mpuParameters_t structure
+ *
+ * Registers affected:
+ *      R1
+ */
+        .macro  ARMV7_MPU_DISABLE_REGION	n
+             LDR        R1, [R0, MPU_INDEX_OFFSET] // get the region index
+             MCR        p15, #0, R1, c6, c2, #0 // set region number
+             MCR        p15, #0, R7, c6, c1, #2 // disable region
+	     ADD        R0, R0, MPU_PARM_LENGTH // move to next region
+        .endm
+
+/*
+ * ARMV7_MPU_DISABLE_REGIONS
+ *
+ * Macro to disable a Task's MPU regions.  It is a wrapper that will
+ * invoke ARMV7_MPU_DISABLE_REGION "n" times.
+ *
+ * Inputs:
+ *      R0:     pointer to mpuParameters_t structure
+ *      R7:     0
+ *
+ * Outputs:
+ *	none
+ *
+ * Registers affected:
+ *      Registers affected by ARMV7_MPU_DISABLE_REGION
+ */
+        .macro  ARMV7_MPU_DISABLE_REGIONS n
+        .if \n
+        ARMV7_MPU_DISABLE_REGION  \n
+        ARMV7_MPU_DISABLE_REGIONS "(\n-1)"
+        .endif
+        .endm
+
+
+	.section	SECTION_STR_MPU_TEXT, "ax"
+	.arm
+	.syntax		unified
+/*
+ * armv7_task_mpu_disable()	- disables a task's MPU context
+ *
+ * This function will disable a task's MPU context.
+ *
+ * Inputs:
+ *	task_regions	A pointer to an array of mpuParameter structures
+ *			that contains exactly MPU_NTASK_REGIONS.  It is
+ *                      expected that this value is in R0.
+ *
+ * Return Values:
+ *	none
+ */
+	.global		armv7_task_mpu_disable
+	.type		armv7_task_mpu_disable, %function
+	.balign		4
+armv7_task_mpu_disable:
+	PUSH		{ R0, R1, R7, LR }
+	MOV		R7, #0
+	ARMV7_MPU_DISABLE_REGIONS	MPU_NTASK_REGIONS
+	POP		{ R0, R1, R7, PC }
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/armv7-mpu.c b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/armv7-mpu.c
new file mode 100644
index 0000000..00fd2d3
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/armv7-mpu.c
@@ -0,0 +1,1390 @@
+/*
+ * Copyright (c) 2015-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                            // for bool, true, false
+#include <stdint.h>                             // for uint32_t, uintptr_t
+#include <string.h>                             // for NULL, memcpy, size_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                     // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <ospl/rtos-port.h>                     // for portBaseType, portUnsignedB...
+#include <cpu/type-conversion.h>                // for fsp_c_v_ptr_to_uptr
+#include <debug/assert.h>                       // for ASSERT, FSP__DEBUG__A...
+#include <misc/attributes.h>                    // for WEAK, UNUSED, FSP__MI...
+#include <misc/bitops.h>                        // for BIT, bit_number, BIT32
+#include <misc/macros.h>                        // for U32_C, FSP_MISRA_BLOC...
+#include <misc/nvrm_drf.h>                      // for NV_DRF_NUM, FSP__MISC...
+
+/* Module-specific FSP headers */
+#include <armv7-mpu.h>                          // for MPU_MAX_REGIONS, MPU_...
+#include <cpu/armv7-mpu.h>                      // for R5_DRSR_0_EN_LSB, R5_...
+#include <cpu/armv7-mpu-regs.h>                 // for r5mpu_region_disable
+#include <cpu/armv7-mpu-safertos-priv.h>        // for vPortTaskHandleToMPUP...
+#include <cpu/armv7-mpu-safertos.h>             // for mpuParameters_t, r5mp...
+#include <cpu/sections-armv7-mpu.h>             // Immune from CT_ASSERT protection
+#include <cpu/barriers.h>                       // for barrier_compiler, bar...
+#include <cpu/built-ins.h>                      // for arm_builtin_clz, FSP_...
+#include <irq/safe-irqs.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__TYPE_CONVERSION_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ASSERT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__NVRM_DRF_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_MPU_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_MPU_REGS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_MPU_SAFERTOS_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_MPU_SAFERTOS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_9, "Approval: Bug 200532001, DR: SWE-FSP-016-SWSADR.docx")
+/**
+ * @file armv7-mpu.c
+ * @brief Implements the various MPU interfaces
+ *
+ * The implementation of the various function that are exposed to the
+ * application firmware and those functions that are needed by SafeRTOS.
+ */
+
+/**
+ * @brief MPU Initialized
+ *
+ * Indicates if the various MPU structures (and the MPU HW itself) has
+ * been initialized.
+ *
+ * This is intended to be a catch if the various callbacks provided by
+ * this code to SafeRTOS are called without the MPU structures being
+ * initialized.
+ */
+static bool                     r5mpu_initialized       SECTION_MPU_DATA = false;
+
+/**
+ * @brief MPU Global Regions
+ *
+ * This is here as a "weak" definition in case the application firmware
+ * doesn't define it.
+ */
+mpuParameters_t                 mpu_global_regions[MPU_NGLOBAL_REGIONS] WEAK
+                                                                SECTION_MPU_DATA;
+
+/**
+ * @brief Task regions array for the xApplicationCopy* functions.
+ *
+ * This is an array of pointers to mpuParameters structures that are ordered
+ * based upon the index of the pointed to mpuParameters structures.  The
+ * array itself represents the ordered regions that apply to the current
+ * task.
+ *
+ * It is permissable to have NULL pointers in this array.
+ *
+ * This array  will be updated when one of the xApplicationCopy* functions
+ * is called and the task handle is different from the previous task handle.
+ */
+static mpuParameters_t          *task_regions[MPU_MAX_REGIONS] SECTION_MPU_DATA;
+
+/**
+ * @brief  Kernel regions array for the xApplicationCopy* functions.
+ *
+ * This is an array of pointers. Each valid pointer points to an
+ * mpuParameters structure. Each mpuParameters structure
+ * contains information to manage per-task MPU regions. Each
+ * region has a unique index value defined within the
+ * mpuParameters structure for that region. This array of
+ * pointers is ordered according to those region index values
+ * and represents the ordered regions that are always accessible
+ * to the kernel or any code that is not running in task context
+ * (e.g. ISRs).
+ *
+ * It is permissable to have NULL pointers in this array.
+ */
+static mpuParameters_t          *kernel_regions[MPU_MAX_REGIONS] SECTION_MPU_DATA;
+
+/**
+ * @brief Previous Task Handle
+ *
+ * This contains the task handle of the previous task that performed
+ * any xApplicationCopy* functions.  It is used to determine if the
+ * task_regions array needs to be updated to reflect the regions of
+ * a new task.
+ */
+static portTaskHandleType       prev_check_task SECTION_MPU_DATA = NULL;
+
+/**
+ * @brief Array to map R5 MPU permissions to r5mpu_check_access_t
+ *
+ * This maps the access permissions contained in the access field in
+ * the mpuParameters structure to a value suitable for the permissions
+ * field.
+ *
+ * This array is only accessed by r5mpu_init() and r5mpu_task_region_init()
+ * and is not accessed again.
+ */
+static uint8_t                  mpu_access_check_map[8] SECTION_MPU_INIT_DATA = {
+    [0] = R5MPU_CHECK_PRIV_NONE | R5MPU_CHECK_USER_NONE,
+    [1] = R5MPU_CHECK_PRIV_RW   | R5MPU_CHECK_USER_NONE,
+    [2] = R5MPU_CHECK_PRIV_RW   | R5MPU_CHECK_USER_READ,
+    [3] = R5MPU_CHECK_PRIV_RW   | R5MPU_CHECK_USER_RW,
+    [4] = R5MPU_CHECK_PRIV_NONE | R5MPU_CHECK_USER_NONE,
+    [5] = R5MPU_CHECK_PRIV_READ | R5MPU_CHECK_USER_NONE,
+    [6] = R5MPU_CHECK_PRIV_READ | R5MPU_CHECK_USER_READ,
+    [7] = R5MPU_CHECK_PRIV_NONE | R5MPU_CHECK_USER_NONE,
+};
+
+/**
+ * @brief R5 MPU not initialized hook
+ *
+ * This is a default hook that can be overridden by the application
+ * to handle cases when one of the MPU functions is called when the
+ * MPU has not been initialized.
+ *
+ * @return None
+ */
+SECTION_MPU_TEXT WEAK void
+r5mpu_not_initialized_hook(void)
+{
+    /*
+     * This function does nothing as it is the default hook.
+     * The application firmware can override this if it wants
+     * to perform some other operation (like abort).
+     */
+    barrier_compiler();
+}
+
+/**
+ * @brief R5 MPU re-initialization attempted
+ *
+ * This is a default hook that can be overridden by the application
+ * to handle cases when re-initialization of the MPU is attempted.
+ *
+ * @return None
+ */
+SECTION_MPU_TEXT WEAK void
+r5mpu_reinitialize_hook(const mpuParameters_t * const region)
+{
+    /*
+     * This function does nothing as it is the default hook.
+     * The application firmware can override this if it wants
+     * to perform some other operation (like abort).
+     */
+    UNUSED(region);
+    barrier_compiler();
+}
+
+/**
+ * @brief Application specific context switch callout
+ *
+ * This function is the default hook that can be overridden by the
+ * application for when it wants to perform some specific work prior
+ * the MPU switch occuring.
+ *
+ * @param [in]  oldTaskData     pointer to opaque data that is contained
+ *                              in the MPU data structure for the task being
+ *                              switched away from
+ * @param [in]  newTaskData     pointer to opaque data that is conteined
+ *                              in the MPU data structure for the task being
+ *                              switched to
+ *
+ * @return None
+ */
+SECTION_MPU_TEXT WEAK void
+vApplicationTaskContextSwitchHook(const void *oldTaskData,
+                                  const void *newTaskData)
+{
+    /*
+     * This function does nothing as it is the default hook.
+     * The application firmware can override this if it wants
+     * to perform some other operation (like abort).
+     */
+    UNUSED(oldTaskData);
+    UNUSED(newTaskData);
+    barrier_compiler();
+}
+
+/**
+ * @brief Initialize task_regions array for current task
+ *
+ * This function will initialize the task's check region array for use
+ * by the other check range functions.
+ *
+ * @pre r5mpu_init() must have been called.
+ * @pre r5mpu_task_region_init() must have been called for the task.
+ * @pre the supplied task handle must represent a valid task.
+ *
+ * @param[in]  task     task handle of the task who's ranges are to be
+ *                      initialized
+ * @param[in]  regions  pointer to the array containing the task's
+ *                      mpuParameters structures
+ *
+ * @return None
+ */
+SECTION_MPU_TEXT static void
+vApplicationCheckTaskRangeInit(portTaskHandleType task,
+                               mpuParameters_t * regions)
+{
+    uint32_t            i;
+    mpuParameters_t     const *prev_region;
+
+    /*
+     * See if the task check array is still valid
+     */
+    if ((prev_check_task != NULL)
+        && (prev_check_task == task)) {
+        goto out;
+    }
+
+    /*
+     * Clear out the entries in the task check array from the previous
+     * task
+     */
+    if (prev_check_task != NULL) {
+        prev_region = vPortTaskHandleToMPUPointer(prev_check_task);
+
+        if (prev_region != NULL) {
+            for (i = 0UL; i < U32_C(MPU_NTASK_REGIONS); i += 1UL) {
+                task_regions[prev_region[i].index] = NULL;
+            }
+        }
+    }
+
+    /*
+     * Set up the task check array for the new task
+     */
+    if (regions != NULL) {
+        for (i = 0UL; i < U32_C(MPU_NTASK_REGIONS); i += 1UL) {
+            /*
+             * Fill the task_regions[i] with the current
+             * task's regions.
+             */
+            task_regions[regions[i].index] = &regions[i];
+        }
+    }
+
+    /*
+     * Update the previous check task if a valid task handle
+     * was passed.
+     */
+    if (task != NULL) {
+        prev_check_task = task;
+    }
+
+  out:
+    return;
+}
+
+/**
+ * @brief Check a range to determine if it is covered by the region
+ *
+ * This function will check a single mpuParameters structure to determine
+ * if the specified range falls within it and has the appropriate access
+ * permissions.  It will update the start and length if any part of the
+ * supplied range overlaps the region and has the correct access permissions.
+ *
+ * @pre None
+ *
+ * @param[in]     region   pointer to a single mpuParameters_t structure
+ * @param[in,out] start    pointer to starting address the of range.  The value
+ *                         pointed to will potentially be updated if it the
+ *                         value is within the region
+ * @param[in,out]  length  pointer to the length of therange in bytes.  The value
+ *                         pointed to will potentially be updated if the range
+ *                         exists within the region
+ *
+ * @retval true  Part of the range falls within the region
+ * @retval false No part of the range falls within the region
+ */
+SECTION_MPU_TEXT static bool
+bApplicationCheckRange(mpuParameters_t const * region,
+                       uintptr_t *start,
+                       uint32_t *length)
+{
+    uintptr_t           begin           = *start;
+    INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-451, DR: SWE-FSP-046-SWSADR.docx");
+    uintptr_t           end             = *start + *length - 1UL;
+    uintptr_t           region_end;
+    bool                matched         = false;
+
+    /*
+     * Determine if any part of the supplied range is within the region
+     */
+    INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-451, DR: SWE-FSP-046-SWSADR.docx");
+    region_end = region->base + region->size - 1UL;
+
+    /*
+     * Determine if there is any part of the range that is covered
+     * by the region
+     */
+    if ((begin >= region->base)
+        && (end <= region_end)) {
+        /*
+         * The range is completely contained within the region
+         * so there will be nothing left to check
+         */
+        *start = 0UL;
+        *length = 0UL;
+
+        matched = true;
+    } else if ((end >= region->base)
+               && (end <= region_end)) {
+        /*
+         * The end of the range overlaps the region so adjust
+         * the length but leave the start alone.
+         */
+        INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-451, DR: SWE-FSP-046-SWSADR.docx");
+        *length -= end - region->base + 1UL;
+        matched = true;
+    } else if ((begin >= region->base)
+               && (begin <= region_end)) {
+        /*
+         * The start of the range overlaps the region so adjust
+         * both the start and length.
+         */
+        *start = region_end + 1UL;
+        INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-451, DR: SWE-FSP-046-SWSADR.docx");
+        *length = end - *start + 1UL;
+        matched = true;
+    } else {
+        /*
+         * Nothing to do in this case.
+         */
+    }
+
+    return matched;
+}
+
+/**
+ * @brief Check that range has access
+ *
+ * This function will check that the address range and required permissions
+ * are allowed.
+ *
+ * @pre None
+ *
+ * @param[in]  regions  pointer to an array of ordered regions to check
+ * @param[in]  access   access permissions required
+ * @param[in]  addr     address in task
+ * @param[in]  length   length of range
+ *
+ * @retval  true   range is valid against the supplied ordered list of regions
+ *                 and has the requested permissions.
+ * @retval  false  range is not valid against the supplied ordered list of
+ *                 regions or does not have the requested permissions.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_MPU_TEXT static bool bApplicationCheckAddrRange(mpuParameters_t *regions[],
+                           r5mpu_check_access_t access,
+                           const void * const addr,
+                           uint32_t length)
+{
+    bool                valid           = false;
+    uint32_t            i;
+    uintptr_t           start;
+    uint32_t            remaining       = length;
+    mpuParameters_t     const *cur_region;
+    r5mpu_check_access_t cur_access     = access;
+
+    /*
+     * If we get a 0 length then pass it.
+     */
+    if (length == 0UL) {
+        valid = true;
+        goto out;
+    }
+
+    /*
+     * A request to copy from NULL with a non-zero length
+     * will fail.
+     */
+    if (addr == NULL) {
+        goto out;
+    }
+
+    start = fsp_c_v_ptr_to_uptr(addr);
+
+    /*
+     * Make sure that the address/length combination makes sense,
+     * that is that addr + length < UINT32_MAX
+     */
+    if (start > (UINTPTR_MAX - length)) {
+            goto out;
+    }
+
+    /*
+     * Scan through the task regions and see if access is allowed
+     */
+    for (i = 0UL; i < U32_C(MPU_MAX_REGIONS); i += 1UL) {
+        cur_region = regions[U32_C(MPU_MAX_REGIONS) - i - 1UL];
+
+        /*
+         * Skip the region if it isn't valid
+         */
+        if ((cur_region == NULL)
+            || ((cur_region->flags & R5MPU_FL_VALID) == 0U)) {
+            continue;
+        }
+
+        if (bApplicationCheckRange(cur_region, &start, &remaining)) {
+            INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-616, DR: SWE-FSP-050-SWSADR.docx");
+            cur_access &= access & cur_region->permissions;
+            if (remaining == 0UL) {
+                if (cur_access == access) {
+                    valid = true;
+                }
+                break;
+            }
+        }
+    }
+
+  out:
+    return valid;
+}
+
+/**
+ * @brief Check that a task's address range is valid
+ *
+ * This function will check that a task's address range is valid for
+ * the requested permissions.
+ *
+ * @param[in]  taskAddr  Address in the task's address space to be checked
+ * @param[in]  uxLength  Length of range to be checked
+ * @param[in]  access    permissions to be used for the check
+ * @param[in]  priv      indicates if the task is privileged (true) or
+ *                       unprivileged (false)
+ *
+ * @retval  true   task's region is valid for the permissions
+ * @retval  false  task's region is not valid for the permissions
+ */
+SECTION_MPU_TEXT static bool
+bCheckTaskAddrRange(const void *taskAddr,
+                    portUnsignedBaseType uxLength,
+                    r5mpu_check_access_t access,
+                    bool priv)
+{
+    bool                rc              = true;
+
+#if ((defined(MPU_COPY_PRIV_CHECK)) && (MPU_COPY_PRIV_CHECK == 1))
+    UNUSED(priv);
+#else
+    if (!priv)
+#endif
+    {
+        rc = bApplicationCheckAddrRange(task_regions,
+                                        access, taskAddr,
+                                        (uint32_t)uxLength);
+     }
+
+    return rc;
+}
+
+/**
+ * @brief Check to see if a copy is valid
+ *
+ * This function will determine if the requested copy can be performed.
+ *
+ * @param[in]  xCurrentTaskHandle  handle to the current task whose context
+ *                                 the copy will be performed under.  If NULL
+ *                                 assume the context is privileged, otherwise
+ *                                 use the task's privilege
+ * @param[in]  pvDestAddr          destination address (e.g. will be written to)
+ * @param[in]  pvSourceAddr        source address (e.g. will be read from)
+ * @param[in]  uxLength            number of bytes in the copy
+ * @param[in]  direction           indicates the direction of the copy
+ *                                 - true  = task to kernel
+ *                                 - false = kernel to task
+ *
+ * @retval  true   copy can proceed
+ * @retval  false  copy cannot proceed
+ */
+SECTION_MPU_TEXT static bool
+bApplicationCheckCopyValid(portTaskHandleType xCurrentTaskHandle,
+                           const void *pvDestAddr,
+                           const void *pvSourceAddr,
+                           portUnsignedBaseType uxLength,
+                           bool direction)
+{
+    bool                        rc              = true;
+    uint32_t                    irq_state;
+
+    irq_state = disable_interrupts();
+
+    /*
+     * Allow the copy to proceed if the length is 0 because it
+     * won't do anything anyway.
+     */
+    if (uxLength == 0UL) {
+        goto out;
+    }
+
+    if ((pvDestAddr == NULL)
+        || (pvSourceAddr == NULL)) {
+        rc = false;
+        goto out;
+    }
+
+#if (defined(MPU_COPY_CHECK) && (MPU_COPY_CHECK==1))
+    bool                        priv;
+    const void                  *kernelAddr;
+    const void                  *taskAddr;
+    r5mpu_check_access_t        kernAccess;
+    r5mpu_check_access_t        taskAccess;
+    mpuParameters_t             *region;
+
+    if (!r5mpu_initialized) {
+        r5mpu_not_initialized_hook();
+        goto out;
+    }
+
+    /*
+     * Determine if the task is privileged or not.
+     */
+    priv = (xCurrentTaskHandle == NULL) ? true
+           : (uxPortTaskSystemModeSetting(xCurrentTaskHandle) == R5_PSR_MODE_SYSTEM);
+
+    if (direction) {
+        kernelAddr = pvDestAddr;
+        kernAccess = R5MPU_CHECK_PRIV_WRITE;
+        taskAddr   = pvSourceAddr;
+        taskAccess = (priv) ? R5MPU_CHECK_PRIV_READ : R5MPU_CHECK_USER_READ;
+    } else {
+        kernelAddr = pvSourceAddr;
+        kernAccess = R5MPU_CHECK_PRIV_READ;
+        taskAddr   = pvDestAddr;
+        taskAccess = (priv) ? R5MPU_CHECK_PRIV_WRITE : R5MPU_CHECK_USER_WRITE;
+    }
+
+    /*
+     * Setup the task's region check array.
+     */
+    region = vPortTaskHandleToMPUPointer(xCurrentTaskHandle);
+
+    vApplicationCheckTaskRangeInit(xCurrentTaskHandle, region);
+
+    /*
+     * Make sure that the kernel address falls within the
+     * expected ranges and has the correct permissions.
+     */
+    if (!bCheckTaskAddrRange(kernelAddr, uxLength, kernAccess, priv)) {
+        rc = false;
+        goto out;
+    }
+
+    /*
+     * Make sure that the task's address falls within the
+     * expected ranges and has the correct permissions.
+     */
+    if (!bCheckTaskAddrRange(taskAddr, uxLength, taskAccess, priv)) {
+        rc = false;
+        goto out;
+    }
+#endif
+
+  out:
+    restore_interrupts(irq_state);
+
+    return rc;
+}
+
+/**
+ * @brief Check to see if a copy in an ISR is valid
+ *
+ * This function will determine if the requested copy can be performed
+ * while in an ISR
+ *
+ * @param[in]  pvDestinationAddr   destination address (e.g. will be written to)
+ * @param[in]  pvSourceAddr        source address (e.g. will be read from)
+ * @param[in]  uxLength            number of bytes in the copy
+ *
+ * @retval  true   copy can proceed
+ * @retval  false  copy cannot proceed
+ */
+SECTION_MPU_TEXT static bool
+bApplicationCheckISRAddrRange(const void *pvDestinationAddr,
+                              const void *pvSourceAddr,
+                              portUnsignedBaseType uxLength)
+{
+    bool        rc      = true;
+
+    /*
+     * Allow the copy to proceed if the length is 0 because it
+     * won't do anything anyway.
+     */
+    if (uxLength == 0UL) {
+        goto out;
+    }
+
+    if ((pvDestinationAddr == NULL)
+        || (pvSourceAddr == NULL)) {
+        rc = false;
+        goto out;
+    }
+
+#if (defined(MPU_COPY_CHECK) && (MPU_COPY_CHECK==1))
+
+    if (!r5mpu_initialized) {
+        r5mpu_not_initialized_hook();
+    } else {
+
+#if (defined(MPU_COPY_KERNEL_CHECK) && (MPU_COPY_KERNEL_CHECK==1))
+
+        if ((!bApplicationCheckAddrRange(kernel_regions,
+                                         R5MPU_CHECK_PRIV_WRITE,
+                                         pvDestinationAddr,
+                                         (uint32_t)uxLength))
+            || (!bApplicationCheckAddrRange(kernel_regions,
+                                            R5MPU_CHECK_PRIV_READ,
+                                            pvSourceAddr,
+                                            (uint32_t)uxLength))) {
+            rc = false;
+        }
+
+#endif
+
+    }
+
+#endif
+
+  out:
+    return rc;
+}
+
+/**
+ * @brief Initialize an MPU region structure
+ *
+ * This function assumes that most of the structure has already been
+ * initialized (more than likely statically).  This fills in any remaining
+ * fields in the data structure from the information already present.
+ *
+ * @pre If set_mpu is true, then the R5's MPU must be disabled.  If set_mpu
+ *      is false, then there is no requirement on the state of the R5's MPU.
+ *
+ * @param[in]  region    pointer to an mpuParameters structure
+ * @param[in]  set_mpu   boolean that indicates if the actual MPU region
+ *                       in the R5 should be set or if this is only used
+ *                       to initialize the mpuParameters structure.
+ *
+ * @return None
+ */
+SECTION_MPU_INIT_TEXT void
+r5mpu_region_init(mpuParameters_t *const region,
+                  bool set_mpu)
+{
+    uint32_t            access;
+    uint32_t            size;
+    uint32_t            first_bit;
+
+    ASSERT(region != NULL);
+    ASSERT(region->index < U32_C(MPU_MAX_REGIONS));
+
+    /*
+     * Skip over regions that have already been initialized
+     * calling the reinitialize hook as necessary.
+     */
+    if ((region->flags & R5MPU_FL_INIT) != 0U) {
+        r5mpu_reinitialize_hook(region);
+        goto out;
+    }
+
+    if ((region->flags & R5MPU_FL_VALID) != 0U) {
+        /*
+         * Deal with regions that couldn't specify the size at compile time
+         */
+        if ((region->flags & R5MPU_FL_END) != 0U) {
+            ASSERT(region->size > region->base);
+
+            size = region->size - region->base;
+            region->size = size;
+            INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-616, DR: SWE-FSP-050-SWSADR.docx");
+            region->flags &= ~R5MPU_FL_END;
+            region->flags |= R5MPU_FL_SIZE;
+        }
+
+        ASSERT((region->flags & (uint32_t)R5MPU_FL_SIZE) != 0U);
+
+        access = (uint32_t)(region->access & R5_DRACR_AP_MASK) >> R5_DRACR_AP_SHIFT;
+        region->permissions = mpu_access_check_map[access];
+
+        /*
+         * The minimum size of a region is 32 bytes, so force the size
+         * to be at least 32 bytes.
+         */
+        size = region->size;
+        if (size < 32UL) {
+            size = 32UL;
+        }
+
+        /*
+         * Make sure that the size is a power-of-2.  Adjust the
+         * resultant size to be the next larger power-of-2 as
+         * necessary.
+         */
+        first_bit = 31UL - arm_builtin_clz(size);
+
+        if (BIT(first_bit) < size) {
+            first_bit += 1UL;
+            size = BIT(first_bit);
+        }
+
+        /*
+         * Make sure that the resulting base and size will cover the
+         * original region.
+         *
+         * At present, this will cause an ASSERT if the resulting
+         * region doesn't cover the originally specified region.  It
+         * is not clear if adjusting the region further is the correct
+         * thing to do given that in some cases that may interfere with
+         * how overlapping regions would behave.
+         */
+        ASSERT(size >= region->size);
+        ASSERT(((region->base & ~(size - 1UL)) + size) >= (region->base + region->size));
+
+        /*
+         * Clear the bits of base that correspond to the size
+         * That is, we know that size is now a power-of-2, so
+         * clear the low order bits of the base address so that
+         * it too is aligned to the same power-of-2.
+         *
+         * NOTE: it is OK to do this, because the R5 MPU would
+         * have done it, so nothing is really changed with this
+         * in terms of correct/incorrect behavior.
+         */
+
+        INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+        region->base &= ~(size - 1UL);
+        region->size = size;
+
+        region->encoded_size = NV_DRF_NUM(R5, DRSR, RSIZE,
+                                          r5mpu_size(size))
+                               | NV_DRF_NUM(R5, DRSR, EN, 1UL);
+        if (set_mpu) {
+            r5mpu_region_config(region->index,
+                                region->base,
+                                region->encoded_size,
+                                region->access);
+            /* Update the region state to initialized */
+            region->flags |= R5MPU_FL_INIT;
+        }
+    } else {
+        region->encoded_size = 0UL;
+        if (set_mpu) {
+            r5mpu_region_disable(region->index);
+        }
+    }
+
+  out:
+    return;
+}
+
+/**
+ * @brief Initialize a task's regions
+ *
+ * This function will initialize the mpuParameters structures in the passed
+ * array (that contains exactly MPU_NTASK_REGIONS structures).  It does *not*
+ * program the MPU with those mappings.
+ *
+ * @pre r5mpu_init must have already been called to set up the global
+ *      regions.
+ *
+ * @param[in]  task_regions   A pointer to an array of mpuParameters structures
+ *                            that contains MPU_NTASK_REGIONS elements, that
+ *                            represent the MPU regions for a specific task
+ *
+ * @return None
+ */
+SECTION_MPU_INIT_TEXT void
+r5mpu_task_region_init(mpuParameters_t *task_mpu_regions)
+{
+    uint32_t            i;
+    uint32_t            used;
+    uint32_t            unused_index;
+    uint32_t            bit;
+    uint32_t            max_regions_mask;
+
+    if (!r5mpu_initialized) {
+        r5mpu_not_initialized_hook();
+        goto out;
+    }
+
+    used = 0UL;
+
+    if (task_mpu_regions != NULL) {
+
+        max_regions_mask = BIT(MPU_MAX_REGIONS) - 1UL;
+
+        /*
+         * Go through and see which are the used indecies
+         * first go through the global regions.
+         *
+         * Assumption here is that the indecies for all of
+         * the global regions are defined regardless of the
+         * region being enabled or not.
+         */
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        for (i = 0UL; i < (uint32_t)MPU_NGLOBAL_REGIONS; i += 1UL) {
+            bit = BIT32_FN(mpu_global_regions[i].index);
+            ASSERT((used & bit) == 0UL);
+            used |= bit;
+        }
+
+        /*
+         * Now go through and figure out which indecies
+         * are used by the task.
+         */
+        for (i = 0UL; i < U32_C(MPU_NTASK_REGIONS); i += 1UL) {
+            if ((task_mpu_regions[i].flags & R5MPU_FL_VALID) != 0U) {
+                bit = BIT32_FN(task_mpu_regions[i].index);
+                ASSERT((used & bit) == 0UL);
+                used |= bit;
+            }
+        }
+
+        /*
+         * Sanity check to make sure used does not have invalid indices
+         */
+        ASSERT((used & (~max_regions_mask)) == 0UL);
+
+        /*
+         * By now we should have all the used indices. Now go through
+         * and assign unused MPU indices to the disabled per-task regions
+         */
+        for (i = 0UL; i < U32_C(MPU_NTASK_REGIONS); i += 1UL) {
+            if ((task_mpu_regions[i].flags & R5MPU_FL_VALID) == 0U) {
+                /*
+                 * find the bit position of the first zero
+                 */
+                unused_index = bit_number(~used);
+                task_mpu_regions[i].index = unused_index;
+                used |= BIT32_FN(unused_index);
+            }
+        }
+
+        /*
+         * Initialize the task's MPU region structures
+         */
+        for (i = 0UL; i < U32_C(MPU_NTASK_REGIONS); i += 1UL) {
+            r5mpu_region_init(&task_mpu_regions[i], false);
+        }
+    }
+
+  out:
+    return;
+}
+
+/**
+ * @brief Iinitialize the MPU
+ *
+ * This function will initialize the MPU initializing the global array
+ * of mpuParameters structures, writing the appropriate values contained
+ * in those structures into the MPU, disabling any unused (including task
+ * related MPU entries) and doing the overall enabling of the MPU.
+ *
+ * @pre None
+ *
+ * @return None
+ */
+SECTION_MPU_INIT_TEXT void
+r5mpu_init(void)
+{
+    uint32_t            i;
+    uint32_t            n_regions;
+    mpuParameters_t     *region;
+
+    ASSERT((U32_C(MPU_MAX_REGIONS)) <= r5mpu_region_count());
+
+    /*
+     * Prevent re-initializing the MPU data structures and MPU HW
+     * once they've already been initializaed.
+     */
+    if (r5mpu_initialized) {
+        r5mpu_reinitialize_hook(NULL);
+
+    }
+
+    n_regions = r5mpu_region_count();
+
+    r5mpu_disable();
+
+    /*
+     * Disable all regions
+     */
+    for (i = 0UL; i < n_regions; i += 1UL) {
+        r5mpu_region_disable(i);
+    }
+
+    for (i = 0UL; i < U32_C(MPU_MAX_REGIONS); i += 1UL) {
+        task_regions[i] = NULL;
+        kernel_regions[i] = NULL;
+    }
+
+    /*
+     * Initialize the MPU with the global regions
+     */
+    INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+    for (i = 0UL; i < (uint32_t)MPU_NGLOBAL_REGIONS; i += 1UL) {
+        region = &mpu_global_regions[i];
+
+        r5mpu_region_init(region, true);
+
+        /*
+         * Place the region based upon it's priority
+         */
+        if ((region->flags & R5MPU_FL_VALID) != 0U) {
+            task_regions[region->index] = region;
+            kernel_regions[region->index] = region;
+        }
+    }
+
+    r5mpu_enable();
+    barrier_memory_complete();
+
+    r5mpu_initialized = true;
+
+    return;
+}
+
+/**
+ * @brief Application specific task switch handling
+ *
+ * This function is called by the context switch code in SafeRTOS.
+ * It will perform the necessary low level operations necessary to
+ * tear down the MPU mappings from the current task and set them up
+ * for the next task.
+ *
+ * @pre MPU must be enabled via r5mpu_init().
+ * @pre The task's region arrays must be properly initialized by
+ *      calling r5mpu_task_region_init().
+ * @pre The handle specified by currentTask must represent a valid task
+ * @pre The handle specified by nextTask must represent a valid task
+ *
+ * @param[in] currentTask  A valid task handle to the current task
+ *                         or NULL.
+ * @param[in] nextTask     A valid task handle to the next task
+ *                         or NULL.
+ *
+ * @return None
+ */
+SECTION_MPU_TEXT void
+vApplicationTaskSwitch(const xTCB *pxTCBOfTaskSwitchedOut,
+                       const xTCB *pxTCBOfTaskSwitchedIn)
+{
+    mpuParameters_t     *cur_region;
+    mpuParameters_t     *next_region;
+    const void          *old_task_data;
+    const void          *new_task_data;
+
+    if (!r5mpu_initialized) {
+        r5mpu_not_initialized_hook();
+        goto out;
+    }
+
+    next_region = (pxTCBOfTaskSwitchedIn == NULL) ? NULL :
+                    pxTCBOfTaskSwitchedIn->pxMPUParameters;
+    cur_region = (pxTCBOfTaskSwitchedOut == NULL) ? NULL :
+                    pxTCBOfTaskSwitchedOut->pxMPUParameters;
+
+    new_task_data = (next_region == NULL) ? NULL : next_region->task_data;
+    old_task_data = (cur_region == NULL) ? NULL : cur_region->task_data;
+
+    /*
+     * Call application's context switch hook
+     */
+    vApplicationTaskContextSwitchHook(old_task_data, new_task_data);
+
+    /*
+     * Only restore the MPU task mappings if:
+     * - there are actually task mappings (by the build)
+     * - the current task and next task are different
+     * - the MPU region pointers are different
+     */
+    if ((U32_C(MPU_NTASK_REGIONS) > 0UL)
+        && (pxTCBOfTaskSwitchedOut != pxTCBOfTaskSwitchedIn)
+        && (cur_region != next_region)) {
+
+        /*
+         * If the next task has per-task mappings, then set them up
+         * otherwise disable the per-task mappings.
+         */
+        if (next_region != NULL) {
+            armv7_task_mpu_restore(next_region);
+        } else {
+            /*
+             * Next task has no per task regions, so disable
+             * the per task MPU entries to avoid erroneous mappings.
+             *
+             * If current task has no per task regions either,
+             * nothing needs to be done as the per-task regions have
+             * already been disabled.
+             */
+            /*
+             * NOTE: cur_region is not checked for NULL here.  A previous
+             * check ensures that cur_region != next_region and that
+             * next_region == NULL on this branch, so cur_region cannot
+             * be NULL.
+             */
+            armv7_task_mpu_disable(cur_region);
+        }
+    }
+
+  out:
+    return;
+}
+
+/**
+ * @brief Copy data from a task to kernel
+ *
+ * This function will copy data from the specified task to kernel and will
+ * check to make sure that:
+ * -# the address specified for the task is readable by the task
+ * -# the address specified for the kernel is writable
+ *
+ * This function must be called from a non-interrupt context.
+ *
+ * This function is only callable from privileged mode.  It will return an
+ * error if called from user mode.
+ *
+ * @pre r5mpu_init() must have been called to set up the global regions
+ * @pre r5mpu_task_region_init() must have been called to setup the task's
+ *      regions if there are any for the task.
+ * @pre the task handle specified by fromTask must represent a valid task.
+ *
+ * @param[in]   xCurrentTaskHandle           task being copied to
+ * @param[in]   pvKernelDestinationAddress   address in the kernel being
+ *                                           copied to
+ * @param[in[   pvApplicationSourceAddress   address in the the task being
+ *                                           copied from
+ * @param[in]   uxLength                     number of bytes being copied
+ *
+ * @retval   pdPASS   Copy occurred
+ * @retval   pdFAIL   Copy could not proceed
+ */
+SECTION_MPU_TEXT portBaseType
+xApplicationCopyDataFromTask(portTaskHandleType xCurrentTaskHandle,
+                             void *pvKernelDestinationAddress,
+                             const void *pvApplicationSourceAddress,
+                             portUnsignedBaseType uxLength)
+{
+    portBaseType                rc              = pdFAIL;
+
+    if (bApplicationCheckCopyValid(xCurrentTaskHandle,
+                                   (const void *)pvKernelDestinationAddress,
+                                   pvApplicationSourceAddress,
+                                   uxLength, true)) {
+
+        /*
+         * It is possible to have NULL values for the addresses in certain
+         * cases.  It will only happen when uxLength is 0.  However, the
+         * operation of memcpy() is undefined if either of the pointers is NULL
+         * even if the length is 0.  So to avoid the undefined behavior we skip
+         * calling memcpy() in those cases.
+         *
+         * bApplicationCheckCopyValid will eliminate all other cases where the
+         * pointers are NULL, so it is only necessary to check for NULL and not
+         * call memcpy() in those cases (the copy would have had a 0 length and
+         * not done anything anyway).
+         */
+        if ((pvKernelDestinationAddress != NULL) && (pvApplicationSourceAddress != NULL)) {
+            (void)memcpy(pvKernelDestinationAddress,
+                         pvApplicationSourceAddress,
+                         (size_t)uxLength);
+        }
+        rc = pdPASS;
+    }
+
+    return rc;
+}
+
+#if (defined(SAFERTOS_MAJOR) && (SAFERTOS_MAJOR == 9))
+/**
+ * @brief Copy data to a new task from the kernel
+ *
+ * This function will copy data from the kernel to the specified task and will
+ * check to make sure that:
+ * -# the address specified for the task is writable by the task
+ * -# the address specified for the kernel is readable
+ *
+ * This function must be called from a non-interrupt context.
+ *
+ * This function is only callable from privileged mode.  It will return an
+ * error if called from user mode.
+ *
+ * @pre r5mpu_init() must have been called to set up the global regions
+ * @pre r5mpu_task_region_init() must have been called to setup the new task's
+ *      regions if there are any for the task.
+ * @pre the task handle specified by xNewTaskHandle must represent a valid task
+ *
+ * @param[in]   xCurrentTaskHandle              task being copied from
+ * @param[in]   xNewTaskHandle                  task being copied to
+ * @param[in]   pvApplicationDestinationAddress address in the task being
+                                                copied to
+ * @param[in[   pvKernelSourceAddress           address in the kernel being
+                                                copied from
+ * @param[in]   uxLength                        number of bytes being copied
+ *
+ * @retval  pdPASS   copy occurred
+ * @retval  pdFAIL   copy could not proceed
+ */
+SECTION_MPU_TEXT portBaseType
+xApplicationCopyDataToNewTask(portTaskHandleType xCurrentTaskHandle,
+                portTaskHandleType xNewTaskHandle,
+                void *pvApplicationDestinationAddress,
+                const void *pvKernelSourceAddress,
+                portUnsignedBaseType uxLength)
+{
+    portBaseType                rc              = pdFAIL;
+
+    if (bApplicationCheckCopyValid(xNewTaskHandle,
+                        (const void *)pvApplicationDestinationAddress,
+                        pvKernelSourceAddress,
+                        uxLength, false)) {
+
+    /*
+     * It is possible to have NULL values for the addresses in certain
+     * cases.  It will only happen when uxLength is 0.  However, the
+     * operation of memcpy() is undefined if either of the pointers is NULL
+     * even if the length is 0.  So to avoid the undefined behavior we skip
+     * calling memcpy() in those cases.
+     *
+     * bApplicationCheckCopyValid will eliminate all other cases where the
+     * pointers are NULL, so it is only necessary to check for NULL and not
+     * call memcpy() in those cases (the copy would have had a 0 length and
+     * not done anything anyway).
+     */
+        if ((pvApplicationDestinationAddress != NULL) &&
+                                (pvKernelSourceAddress != NULL)) {
+            (void)memcpy(pvApplicationDestinationAddress,
+                         pvKernelSourceAddress,
+                         (size_t)uxLength);
+        }
+        rc = pdPASS;
+    }
+
+    return rc;
+}
+#endif
+
+/**
+ * @brief Copy data to a task from the kernel
+ *
+ * This function will copy data from the kernel to the specified task and will
+ * check to make sure that:
+ * -# the address specified for the task is writable by the task
+ * -# the address specified for the kernel is readable
+ *
+ * This function must be called from a non-interrupt context.
+ *
+ * This function is only callable from privileged mode.  It will return an
+ * error if called from user mode.
+ *
+ * @pre r5mpu_init() must have been called to set up the global regions
+ * @pre r5mpu_task_region_init() must have been called to setup the task's
+ *      regions if there are any for the task.
+ * @pre the task handle specified by toTask must represent a valid task.
+ *
+ * @param[in]   xCurrentTaskHandle                task being copied to
+ * @param[in]   pvApplicationDestinationAddress   address in the task being
+ *                                                copied to
+ * @param[in[   pvKernelSourceAddress             address in the kernel being
+ *                                                copied from
+ * @param[in]   uxLength                          number of bytes being copied
+ *
+ * @retval  pdPASS   copy occurred
+ * @retval  pdFAIL   copy could not proceed
+ */
+SECTION_MPU_TEXT portBaseType
+xApplicationCopyDataToTask(portTaskHandleType xCurrentTaskHandle,
+                void *pvApplicationDestinationAddress,
+                const void *pvKernelSourceAddress,
+                portUnsignedBaseType uxLength)
+{
+    portBaseType                rc              = pdFAIL;
+
+    if (bApplicationCheckCopyValid(xCurrentTaskHandle,
+                                   (const void *)pvApplicationDestinationAddress,
+                                   pvKernelSourceAddress,
+                                   uxLength, false)) {
+
+        /*
+         * It is possible to have NULL values for the addresses in certain
+         * cases.  It will only happen when uxLength is 0.  However, the
+         * operation of memcpy() is undefined if either of the pointers is NULL
+         * even if the length is 0.  So to avoid the undefined behavior we skip
+         * calling memcpy() in those cases.
+         *
+         * bApplicationCheckCopyValid will eliminate all other cases where the
+         * pointers are NULL, so it is only necessary to check for NULL and not
+         * call memcpy() in those cases (the copy would have had a 0 length and
+         * not done anything anyway).
+         */
+        if ((pvApplicationDestinationAddress != NULL) && (pvKernelSourceAddress != NULL)) {
+            (void)memcpy(pvApplicationDestinationAddress,
+                         pvKernelSourceAddress,
+                         (size_t)uxLength);
+        }
+        rc = pdPASS;
+    }
+
+    return rc;
+}
+
+/**
+ * @brief Copy data from ISR to the kernel
+ *
+ * This function will copy data from the ISR into the kernel.  Since the ISR
+ * will have the same access mappings as the kernel, it will only perform
+ * kernel access checks.  That is, it cannot depend upon what the current
+ * task has mapped.
+ *
+ * This function is only callable from an ISR.  It will return an
+ * error if called when not in an ISR.
+ *
+ * @pre r5mpu_init() must have been called to set up the global regions.
+ *
+ * @param[in]   pvKernelDestinationAddress   address in the kernel being
+ *                                           copied to
+ * @param[in[   pvApplicationSourceAddress   address in the the task being
+ *                                           copied from
+ * @param[in]   uxLength                     number of bytes being copied
+ *
+ * @retval pdPASS   the copy occurred
+ * @retval pdFAIL   the copy could not proceed
+ */
+SECTION_MPU_TEXT portBaseType
+xApplicationCopyDataFromISR(void *pvKernelDestinationAddress,
+                            const void *pvApplicationSourceAddress,
+                            portUnsignedBaseType uxLength)
+{
+    portBaseType                rc              = pdFAIL;
+
+    if (bApplicationCheckISRAddrRange(pvKernelDestinationAddress,
+                                      pvApplicationSourceAddress,
+                                      uxLength)) {
+
+        /*
+         * It is possible to have NULL values for the addresses in certain
+         * cases.  It will only happen when uxLength is 0.  However, the
+         * operation of memcpy() is undefined if either of the pointers is NULL
+         * even if the length is 0.  So to avoid the undefined behavior we skip
+         * calling memcpy() in those cases.
+         *
+         * bApplicationCheckCopyValid will eliminate all other cases where the
+         * pointers are NULL, so it is only necessary to check for NULL and not
+         * call memcpy() in those cases (the copy would have had a 0 length and
+         * not done anything anyway).
+         */
+        if ((pvKernelDestinationAddress != NULL) && (pvApplicationSourceAddress != NULL)) {
+            (void)memcpy(pvKernelDestinationAddress,
+                         pvApplicationSourceAddress,
+                         (size_t)uxLength);
+        }
+        rc = pdPASS;
+    }
+
+    return rc;
+}
+
+/**
+ * @brief Copy data from task to ISR
+ *
+ * This function will copy data from the kernel into the ISR.  Since the ISR
+ * will have the same access mappings as the kernel, it will only perform
+ * kernel access checks.  That is, it cannot depend upon what the current
+ * task has mapped.
+ *
+ * @pre r5mpu_init() must have been called to set up the global regions.
+ *
+ * This function is only callable from an ISR.  It will return an
+ * error if called from user mode.
+ *
+ * @param[in]   pvApplicationDestinationAddress   address in the task being
+ *                                                copied to
+ * @param[in[   pvKernelSourceAddress             address in the the kernel
+ *                                                being copied from
+ * @param[in]   uxLength                          number of bytes being copied
+ *
+ * @retval pdPASS   the copy occurred
+ * @retval pdFAIL   the copy could not proceed
+ */
+SECTION_MPU_TEXT portBaseType
+xApplicationCopyDataToISR(void *pvApplicationDestinationAddress,
+                          const void *pvKernelSourceAddress,
+                          portUnsignedBaseType uxLength)
+{
+    portBaseType                rc              = pdFAIL;
+
+    if (bApplicationCheckISRAddrRange((const void *)pvApplicationDestinationAddress,
+                                      pvKernelSourceAddress,
+                                      uxLength)) {
+
+        /*
+         * It is possible to have NULL values for the addresses in certain
+         * cases.  It will only happen when uxLength is 0.  However, the
+         * operation of memcpy() is undefined if either of the pointers is NULL
+         * even if the length is 0.  So to avoid the undefined behavior we skip
+         * calling memcpy() in those cases.
+         *
+         * bApplicationCheckCopyValid will eliminate all other cases where the
+         * pointers are NULL, so it is only necessary to check for NULL and not
+         * call memcpy() in those cases (the copy would have had a 0 length and
+         * not done anything anyway).
+         */
+        if ((pvApplicationDestinationAddress != NULL) && (pvKernelSourceAddress != NULL)) {
+            (void)memcpy(pvApplicationDestinationAddress,
+                         pvKernelSourceAddress,
+                         (size_t)uxLength);
+        }
+        rc = pdPASS;
+    }
+
+    return rc;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_9, "Approval: Bug 200532001, DR: SWE-FSP-016-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/cortex-r5/cache-cortex-r5.c b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/cortex-r5/cache-cortex-r5.c
new file mode 100644
index 0000000..656a875
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/cortex-r5/cache-cortex-r5.c
@@ -0,0 +1,470 @@
+/*
+ * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                        // for uint32_t
+#include <string.h>                        // for size_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/type-conversion.h>           // for fsp_c_v_ptr_to_uptr, FSP...
+#include <misc/attributes.h>               // for UNUSED_NONCONST_PTR
+#include <misc/bitops.h>                   // for BIT, EXTRACT, FSP__MISC__B...
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <cpu/armv7-cache.h>               // for bpiall, CACHE_LINE_SIZE
+#include <cpu/armv7-regs.h>                // for rd_sctlr, wr_sctlr, rd_actlr
+#include <cpu/barriers.h>                  // for barrier_cache_op_complete
+#include <cpu/cache.h>                     // for FSP__CPU__CACHE_H
+#include <cpu/sections-cache.h>            // Immune from CT_ASSERT protection
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__CPU__TYPE_CONVERSION_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_CACHE_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_REGS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__BARRIERS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__CACHE_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @brief Convert address/length to number of cache lines
+ *
+ * This function will report the number of lines (including partial lines)
+ * that are covered by the range described by addr and length.
+ *
+ * @param[in] addr:    Address of start of range
+ * @param[in] length:  number of bytes in range
+ *
+ * @return number of cache lines covered by the range
+ */
+static inline uint32_t
+cache_len_to_lines(const uint32_t addr, const size_t length)
+{
+    uint32_t    n_lines;
+
+    /*
+     * Compute how many cache lines are covered by the data.
+     *
+     * It takes into account where the data lies within the cache
+     * line as the data may occupy an additional cache line based
+     * upon where it starts in the cache line.
+     */
+
+    INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    n_lines = ((addr & (~CACHE_LINE_MASK)) + length + CACHE_LINE_SIZE - 1UL)
+              / CACHE_LINE_SIZE;
+
+    return n_lines;
+}
+
+/**
+ * @brief Clean a region of dCache
+ *
+ * This function will cause any "dirty" data in the dCache in the
+ * specified range to be written back to memory.  The data may still
+ * reside in the dCache (e.g. it was not invalidated).
+ *
+ * If the specified range does not align with integral numbers of
+ * cache lines, more data may be "cleaned" than was actually specified.
+ *
+ * @param[in] base:   Address of start of range to be cleaned
+ * @param[in] length: Number of bytes in the range to be cleaned
+ *
+ * @return none
+ */
+SECTION_CACHE_TEXT void
+dcache_clean(const void * const base, const size_t length)
+{
+    uint32_t            addr;
+    uint32_t            nlines;
+
+    addr = fsp_c_v_ptr_to_uptr(base);
+
+    /*
+     * Compute how many cache lines are covered by the data that
+     * need to be cleaned.
+     */
+    nlines = cache_len_to_lines(addr, length);
+
+    /*
+     * Align the address to the start of a cache line.
+     */
+    addr &= CACHE_LINE_MASK;
+
+    while (nlines != 0UL) {
+        dccmvac(addr);
+        INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+        addr += CACHE_LINE_SIZE;
+        nlines -= 1UL;
+    }
+
+    barrier_cache_op_complete();
+}
+
+/**
+ * @brief Invalidate a region of dCache
+ *
+ * This function will cause the specified region in the dCache to be
+ * invalidated.  That is, that data will no longer reside in the dCache
+ * at the completion of this function.
+ *
+ * If the specified range does not align with integral numbers of
+ * cache lines, more data may be invalidated than was actually specified.
+ *
+ * @param[in] base:   Address of start of range to be invalidated
+ * @param[in] length: Number of bytes in the range to be invalidated
+ *
+ * @return none
+ */
+SECTION_CACHE_TEXT void
+dcache_invalidate(void *const base, const size_t length)
+{
+    uint32_t            addr;
+    uint32_t            nlines;
+
+    UNUSED_NONCONST_PTR(base);
+    addr = fsp_c_v_ptr_to_uptr(base);
+
+    /*
+     * Compute how many cache lines are covered by the data that
+     * need to be invalidated.
+     */
+    nlines = cache_len_to_lines(addr, length);
+
+    /*
+     * Align the address to the start of a cache line
+     */
+    addr &= CACHE_LINE_MASK;
+
+    while (nlines != 0UL) {
+        dcimvac(addr);
+        INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+        addr += CACHE_LINE_SIZE;
+        nlines -= 1UL;
+    }
+
+    barrier_cache_op_complete();
+}
+
+/**
+ * @brief Invalidate entire dCache
+ *
+ * This function will cause the entire dCache to be invalidated
+ *
+ * @return none
+ */
+SECTION_CACHE_TEXT void
+dcache_invalidate_all(void)
+{
+    dcivall();
+
+    barrier_cache_op_complete();
+}
+
+/**
+ * @brief Invalidate the entire iCache
+ *
+ * This function will cause the entire icache contents to be invalidated.
+ *
+ * @return none
+ */
+SECTION_CACHE_TEXT void
+icache_invalidate_all(void)
+{
+    iciallu();
+    barrier_cache_op_complete();
+    bpiall();
+}
+
+/**
+ * @brief Invalidate a region of iCache
+ *
+ * This function will cause the specified region in the iCache to be
+ * invalidated.  That is, that data will no longer reside in the iCache
+ * at the completion of this function.
+ *
+ * If the specified range does not align with integral numbers of
+ * cache lines, more data may be invalidated than was actually specified.
+ *
+ * @param[in] base:   Address of start of range to be invalidated
+ * @param[in] length: Number of bytes in the range to be invalidated
+ *
+ * @return none
+ */
+SECTION_CACHE_TEXT void
+icache_invalidate(void * const base, const size_t length)
+{
+    uint32_t            addr;
+    uint32_t            nlines;
+
+    UNUSED_NONCONST_PTR(base);
+    addr = fsp_c_v_ptr_to_uptr(base);
+
+    /*
+     * Compute how many cache lines are covered by the code that
+     * need to be invalidated.
+     */
+    nlines = cache_len_to_lines(addr, length);
+
+    /*
+     * Align the address to the start of a cache line
+     */
+    addr &= CACHE_LINE_MASK;
+
+    while (nlines != 0UL) {
+        icimvau(addr);
+        INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+        addr += CACHE_LINE_SIZE;
+        nlines -= 1UL;
+    }
+
+    barrier_cache_op_complete();
+    bpiall();
+}
+
+/**
+ * @brief Clean entire dCache
+ *
+ * This function will cause all of the dirty lines in the dCache to be
+ * "cleaned".  That is, any dirty lines in the dCache will be written
+ * back to DRAM.
+ *
+ * This will only clean the L1 dCache as the R5 only has L1 caches.
+ *
+ * @return none
+ */
+SECTION_CACHE_TEXT void
+dcache_clean_all(void)
+{
+    uint32_t    ccsidr;
+    uint32_t    num_ways;
+    uint32_t    num_sets;
+    uint32_t    way;
+    uint32_t    set;
+    uint32_t    dccsw_param;
+
+    /*
+     * Write CSSELR (Cache Size SELection Register)
+     * Note that this implicitly selects the data cache
+     * which is OK since we're cleaning the data cache.
+     */
+    wr_csselr(0UL);
+    barrier_instruction_synchronization();
+
+    /* Read CCSIDR (CaChe Size ID Register) */
+    ccsidr = rd_ccsidr();
+
+    /*
+     * Note: num_ways *must* be less than or equal to 4 in order for
+     * the shift in setting up the dccsw_param to work properly.
+     * There cannot be a run-time check for this (e.g. an assert) because
+     * that would introduce a cyclic dependency:
+     *          assert-->abort-->dcache_clean_all-->assert-->...
+     *
+     * This shouldn't be a problem except if this code is moved to something
+     * other than an R5.  The R5 will always have num_ways <= 4.
+     */
+    num_ways = EXTRACT(ccsidr, 12U, 3U, uint32_t) + 1UL;
+    num_sets = EXTRACT(ccsidr, 27U, 13U, uint32_t) + 1UL;
+
+    for (set = 0UL; set < num_sets; set += 1UL) {
+        for (way = 0UL; way < num_ways; way += 1UL) {
+            dccsw_param = way << 30;
+            dccsw_param |= set << 5;
+
+            dccsw(dccsw_param);
+
+        }
+    }
+
+    barrier_cache_op_complete();
+}
+
+/**
+ * @brief Disable all caches
+ *
+ * This function will disable the iCache and dCache.  It will also ensure
+ * that any dirty lines in the dCache have been completely written to DRAM
+ * before this function returns.
+ *
+ * @return none
+ */
+SECTION_CACHE_INIT_TEXT void
+cache_disable(void)
+{
+    uint32_t    sctlr;
+
+    sctlr = rd_sctlr();
+
+    if ((sctlr & BIT(2)) != 0U) {
+        dcache_clean_all();
+    }
+
+    sctlr &= ~BIT(12);          /* instruction cache disable */
+    sctlr &= ~BIT(2);            /* data cache disable */
+
+    barrier_memory_complete();
+    wr_sctlr(sctlr);
+
+    barrier_instruction_synchronization();
+}
+
+/**
+ * @brief Enable all caches
+ *
+ * This function will enable the iCache and dCache.  It will ensure that
+ * the contents of the caches are invalid (e.g. there is no data or instructions
+ * in the cache) before enabling the caches.
+ *
+ * @return none
+ */
+SECTION_CACHE_INIT_TEXT void
+cache_enable(void)
+{
+    uint32_t sctlr;
+
+    sctlr = rd_sctlr();
+
+    sctlr |= BIT(12);           /* instruction cache enable */
+    sctlr |= BIT(2);            /* data cache enable */
+
+    barrier_memory_complete();
+
+    dcache_invalidate_all();
+    icache_invalidate_all();
+    bpiall();
+
+    wr_sctlr(sctlr);
+    barrier_instruction_synchronization();
+}
+
+/**
+ * @brief Enable all caches with ECC enabled
+ *
+ * This function will enable the iCache and dCache with ECC enabled.  It
+ * follows the Sequence Reference 8.5.5. of Cortex R5 TRM (Disabling or
+ * enabling error checking).
+ *
+ * @return none
+ */
+SECTION_CACHE_INIT_TEXT void
+cache_enable_ecc(void)
+{
+        uint32_t actlr;
+
+        cache_disable();
+
+        actlr = rd_actlr();
+        actlr &= ~(0x7UL << 3);
+        actlr |= 0x5UL << 3;    // do not generate abort on ECC errors,
+                                // enable HW error recovery
+
+        /*
+         * WAR for ARM R5 Erratum 780125
+         * See nvbugs 200322274 for details
+         *
+         * Dsiable write burst in the AXI master (DBWR: bit 14)
+         */
+        actlr |= BIT(14);
+        wr_actlr(actlr);
+
+        barrier_memory_complete();
+
+        cache_enable();
+}
+
+/**
+ * @brief Clean a region of dCache
+ *
+ * This function will cause any "dirty" data in the dCache in the
+ * specified range to be written back to memory.  The data may still
+ * reside in the dCache (e.g. it was not invalidated).
+ *
+ * If the specified range does not align with integral numbers of
+ * cache lines, more data may be "cleaned" than was actually specified.
+ *
+ * @param[in] base   Address of start of range to be cleaned
+ * @param[in] length Number of bytes in the range to be cleaned
+ *
+ * @return none
+ *
+ * @deprecated dcache_clean() should be used instead.
+ */
+SECTION_CACHE_TEXT void
+cache_clean(const void * const base, size_t length)
+{
+    dcache_clean(base, length);
+}
+
+/**
+ * @brief Invalidate a region of dCache
+ *
+ * This function will cause the specified region in the dCache to be
+ * invalidated.  That is, that data will no longer reside in the dCache
+ * at the completion of this function.
+ *
+ * If the specified range does not align with integral numbers of
+ * cache lines, more data may be invalidated than was actually specified.
+ *
+ * @param[in] base:   Address of start of range to be invalidated
+ * @param[in] length: Number of bytes in the range to be invalidated
+ *
+ * @return none
+ *
+ * @deprecated dcache_invalidate() should be used instead.
+ */
+SECTION_CACHE_TEXT void
+cache_invalidate(void * const base, size_t length)
+{
+    dcache_invalidate(base, length);
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/cortex-r5/irqapi-cortex-r5.c b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/cortex-r5/irqapi-cortex-r5.c
new file mode 100644
index 0000000..76caf9d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/cortex-r5/irqapi-cortex-r5.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2015-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>               // for bool
+#include <stdint.h>                // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>        // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <irq/safe-irqs.h>         // for in_critical
+#include <misc/macros.h>           // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <cpu/armv7-mpu.h>         // for FSP__CPU__ARMV7_MPU_H, R5_C...
+#include <cpu/armv7-regs.h>        // for rd_cpsr, FSP__CPU__ARMV7_RE...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_MPU_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_REGS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+static inline uint32_t arm_get_i_bit(void)
+{
+	uint32_t cpsr;
+
+	cpsr = rd_cpsr();
+
+	return (uint32_t)(cpsr & R5_CPSR_IRQ_MASK) >> R5_CPSR_IRQ_SHIFT;
+}
+
+bool in_critical(void)
+{
+	return (arm_get_i_bit() != 0U);
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/cortex-r5/module-cpl-cortex-r5-config.mk b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/cortex-r5/module-cpl-cortex-r5-config.mk
new file mode 100644
index 0000000..4678d5d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/cortex-r5/module-cpl-cortex-r5-config.mk
@@ -0,0 +1,64 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cpl-cortex-r5-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-cpl_*.mk' files.
+MODULE_CPL_CONFIG                   := 1
+MODULE_CPL_CORTEX_R5_CONFIG         := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_CPL_DEPENDS                  := SOC CLUSTER
+$(foreach _,$(MODULE_CPL_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Define ARCH variables
+ARCH                                := arm
+ISA                                 := armv7
+CPU                                 := cortex-r5
+
+#
+# Location of source code files
+CPL_SOC_IDS                          = $(FSP_COMMON_REPO)/soc/$(SOC)/ids/$(CLUSTER)
+CPL_SOC_IDS_CMN                      = $(FSP_COMMON_REPO)/soc/$(SOC)/ids/soc-common
+CPL_SOC_PORT                         = $(FSP_COMMON_REPO)/soc/$(SOC)/port/$(CLUSTER)
+CPL_VIC_DIR                          = $(FSP_COMMON_REPO)/drivers/vic
+CPL_ARCH_DIR                         = $(FSP_COMMON_REPO)/drivers/cpu/$(ARCH)
+CPL_ISA_DIR                          = $(FSP_COMMON_REPO)/drivers/cpu/$(ARCH)/$(ISA)
+MODULE_CPL_CORTEX_R5_SOURCE_DIR      =
+MODULE_CPL_CORTEX_R5_SOURCE_DIR     += $(CPL_SOC_IDS)
+MODULE_CPL_CORTEX_R5_SOURCE_DIR     += $(CPL_SOC_IDS_CMN)
+MODULE_CPL_CORTEX_R5_SOURCE_DIR     += $(CPL_SOC_PORT)
+MODULE_CPL_CORTEX_R5_SOURCE_DIR     += $(CPL_VIC_DIR)
+MODULE_CPL_CORTEX_R5_SOURCE_DIR     += $(CPL_ISA_DIR)/$(CPU)
+MODULE_CPL_CORTEX_R5_SOURCE_DIR     += $(CPL_ARCH_DIR)/common
+MODULE_CPL_CORTEX_R5_SOURCE_DIR     += $(CPL_ISA_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_CPL_CORTEX_R5_INCLUDES        = -I $(FSP_COMMON_REPO)/include/osa/$(OSA)/$(ARCH)/$(ISA)/$(CPU)
+MODULE_CPL_CORTEX_R5_INCLUDES       += -I $(FSP_COMMON_REPO)/include/cpu/$(ARCH)/$(ISA)
+MODULE_CPL_CORTEX_R5_INCLUDES       += -I $(FSP_COMMON_REPO)/include/cpu/$(ARCH)/$(ISA)/$(CPU)
+MODULE_CPL_CORTEX_R5_INCLUDES       += -I $(FSP_COMMON_REPO)/include/cpu/$(ARCH)/common
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/cortex-r5/module-cpl-cortex-r5.mk b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/cortex-r5/module-cpl-cortex-r5.mk
new file mode 100644
index 0000000..3ea22b0
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv7/cortex-r5/module-cpl-cortex-r5.mk
@@ -0,0 +1,101 @@
+#
+# Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cpl-cortex-r5.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_CPL_CORTEX_R5_NAME       := CPL_CORTEX_R5
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_CPL_DEFINED              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_CPU_DEPENDS              := CPL SOC OSA DEBUG_NOSAFETY CPL_CORTEX_R5
+$(foreach _,$(CONFIG_CPU_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_CPL_CORTEX_R5_C_SRC       =
+MODULE_CPL_CORTEX_R5_C_SRC      += $(CPL_VIC_DIR)/irqapi-vic.c
+MODULE_CPL_CORTEX_R5_C_SRC      += $(CPL_VIC_DIR)/vic-init.c
+MODULE_CPL_CORTEX_R5_C_SRC      += $(CPL_SOC_IDS)/irqapi-vic-ids.c
+MODULE_CPL_CORTEX_R5_C_SRC      += $(CPL_ARCH_DIR)/common/arm-vic.c
+MODULE_CPL_CORTEX_R5_C_SRC      += $(CPL_ARCH_DIR)/$(CPU)/cache-cortex-r5.c
+MODULE_CPL_CORTEX_R5_C_SRC      += $(CPL_ISA_DIR)/armv7-exception.c
+MODULE_CPL_CORTEX_R5_C_SRC      += $(CPL_ISA_DIR)/armv7-mpu.c
+MODULE_CPL_CORTEX_R5_C_SRC      += $(CPL_ARCH_DIR)/common/irqapi-arm.c
+MODULE_CPL_CORTEX_R5_C_SRC      += $(CPL_ARCH_DIR)/$(CPU)/irqapi-cortex-r5.c
+
+#
+# Assembly source
+MODULE_CPL_CORTEX_R5_ASM_SRC     =
+MODULE_CPL_CORTEX_R5_ASM_SRC    += $(CPL_VIC_DIR)/vic-asm.S
+MODULE_CPL_CORTEX_R5_ASM_SRC    += $(CPL_ISA_DIR)/armv7-exceptions.S
+MODULE_CPL_CORTEX_R5_ASM_SRC    += $(CPL_ISA_DIR)/armv7-mpu-asm.S
+
+#
+# Special C Flags
+MODULE_CPL_CORTEX_R5_C_FLAGS     =
+
+#
+# Special ASM Flags
+MODULE_CPL_CORTEX_R5_ASM_FLAGS   =
+
+#
+# Instructs the makefile system that there is a module-specific dependency.
+# A few pieces are needed to make this work:
+#   MODULE_$(MODULE_NAME)_TARGET_ENABLED             = 1 Tells the FSP makefile system that this module has a custom target
+#   MODULE_$(MODULE_NAME)_TARGET_NAMES               = List of one or more target names (can be more than one)
+#                                                    =   This recipe will be dynamically created in the master makefile;
+#                                                        no need to create it here.
+#   MODULE_CPL_CORTEX_R5_TARGET_RECIPE               = List of recipe/dependencies to be built (made) by $(MODULE_$(MODULE_NAME)_TARGET_NAMES)
+#   $(MODULE_$(MODULE_NAME)_TARGET_NAMES)_AFLAGS     = Compiler ASM-FLAGS used to compile this module
+#   $(MODULE_$(MODULE_NAME)_TARGET_NAMES)_CFLAGS     = Compiler C-FLAGS used to compile this module
+MODULE_CPL_CORTEX_R5_TARGET_ENABLED                  = 1
+MODULE_CPL_CORTEX_R5_TARGET_NAMES                    = MODULE_CPL_CORTEX_R5_DYNAMIC_HEADERS
+MODULE_CPL_CORTEX_R5_TARGET_RECIPE                   = armv7-mpu-asm-dynamic-hdr.h
+MODULE_CPL_CORTEX_R5_DYNAMIC_HEADERS_AFLAGS          =
+MODULE_CPL_CORTEX_R5_DYNAMIC_HEADERS_CFLAGS          = -MT $(DYNAMIC_SRC_DIR)/$(addsuffix .s,$(notdir $(basename $@)-interim))
+MODULE_CPL_CORTEX_R5_DYNAMIC_HEADERS_CFLAGS         += -MMD
+MODULE_CPL_CORTEX_R5_DYNAMIC_HEADERS_CFLAGS         += -MP
+MODULE_CPL_CORTEX_R5_DYNAMIC_HEADERS_CFLAGS         += -MF $(DYNAMIC_DEP_DIR)/$(notdir $(basename $@)-interim).d
+
+armv7-mpu-asm-dynamic-hdr.h: armv7-mpu-asm-dynamic-hdr.c | GLOBAL_dirs
+	@echo  [$(SOC)][C-\>ASM] $(notdir $(subst $(TEGRA_TOP)/,,$<))
+	@$(CC) -c -S $(MODULE_CPL_CORTEX_R5_DYNAMIC_HEADERS_AFLAGS) \
+                    $(MODULE_CPL_CORTEX_R5_DYNAMIC_HEADERS_CFLAGS) \
+                    $< -o $(DYNAMIC_SRC_DIR)/$(addsuffix .s,$(notdir $(basename $@)-interim))
+	@echo  [$(SOC)][ASM-\>HDR] $(notdir $(subst .c,.h,$(subst $(TEGRA_TOP)/,,$<)))
+	@$(GREP) -o '#define[ \t][ \t]*[^( |\t)]*[ \t][ \t]*[^( |\t|\$)]*' $(DYNAMIC_SRC_DIR)/$(addsuffix .s,$(notdir $(basename $@)-interim)) > $(DYNAMIC_HDR_DIR)/$@
+
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv8/cortex-r52/module-cpl-cortex-r52-config.mk b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv8/cortex-r52/module-cpl-cortex-r52-config.mk
new file mode 100644
index 0000000..0543d96
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv8/cortex-r52/module-cpl-cortex-r52-config.mk
@@ -0,0 +1,56 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cpl-cortex-r52-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-cpl_*.mk' files.
+MODULE_CPL_CONFIG                   := 1
+MODULE_CPL_CORTEX_R52_CONFIG        := 1
+
+#
+# Define ARCH variables
+ARCH                                := arm
+ISA                                 := armv8
+CPU                                 := cortex-r52
+
+#
+# Location of source code files
+CPL_SOC_IDS                          = $(FSP_COMMON_REPO)/soc/$(SOC)/ids/$(CLUSTER)
+CPL_SOC_IDS_CMN                      = $(FSP_COMMON_REPO)/soc/$(SOC)/ids/soc-common
+CPL_SOC_PORT                         = $(FSP_COMMON_REPO)/soc/$(SOC)/port/$(CLUSTER)
+CPL_ARCH_DIR                         = $(FSP_COMMON_REPO)/drivers/cpu/$(ARCH)
+CPL_ISA_DIR                          = $(FSP_COMMON_REPO)/drivers/cpu/$(ARCH)/$(ISA)
+MODULE_CPL_CORTEX_R52_SOURCE_DIR     =
+MODULE_CPL_CORTEX_R52_SOURCE_DIR    += $(CPL_SOC_IDS)
+MODULE_CPL_CORTEX_R52_SOURCE_DIR    += $(CPL_SOC_IDS_CMN)
+MODULE_CPL_CORTEX_R52_SOURCE_DIR    += $(CPL_SOC_PORT)
+MODULE_CPL_CORTEX_R52_SOURCE_DIR    += $(CPL_VIC_DIR)
+MODULE_CPL_CORTEX_R52_SOURCE_DIR    += $(CPL_ISA_DIR)/$(CPU)
+MODULE_CPL_CORTEX_R52_SOURCE_DIR    += $(CPL_ARCH_DIR)/common
+MODULE_CPL_CORTEX_R52_SOURCE_DIR    += $(CPL_ISA_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_CPL_CORTEX_R52_INCLUDES       = -I $(FSP_COMMON_REPO)/include/osa/$(OSA)/$(ARCH)/$(ISA)/$(CPU)
+MODULE_CPL_CORTEX_R52_INCLUDES      += -I $(FSP_COMMON_REPO)/include/cpu/$(ARCH)/$(ISA)
+MODULE_CPL_CORTEX_R52_INCLUDES      += -I $(FSP_COMMON_REPO)/include/cpu/$(ARCH)/$(ISA)/$(CPU)
+MODULE_CPL_CORTEX_R52_INCLUDES      += -I $(FSP_COMMON_REPO)/include/cpu/$(ARCH)/common
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv8/cortex-r52/module-cpl-cortex-r52.mk b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv8/cortex-r52/module-cpl-cortex-r52.mk
new file mode 100644
index 0000000..5fc0a48
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/armv8/cortex-r52/module-cpl-cortex-r52.mk
@@ -0,0 +1,61 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cpl-cortex-r52.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_CPL_CORTEX_R52_NAME      := CPL_CORTEX_R52
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_CPL_DEFINED              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_CPU_DEPENDS              := CPL CPL_CORTEX_R52
+$(foreach _,$(CONFIG_CPU_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_CPL_CORTEX_R52_C_SRC      =
+
+#
+# Assembly source
+MODULE_CPL_CORTEX_R52_ASM_SRC    =
+
+#
+# Special C Flags
+MODULE_CPL_CORTEX_R52_C_FLAGS    =
+
+#
+# Special ASM Flags
+MODULE_CPL_CORTEX_R52_ASM_FLAGS  =
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/arm/common/arm-vic.c b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/common/arm-vic.c
new file mode 100644
index 0000000..05b6d24
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/common/arm-vic.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                 // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>         // for CT_ASSERT
+#include <soc-common/hw-const.h>    /* Must appear before hwinc files */
+
+/* Hardware headers */
+#include <araps_vic.h>              // for APS_VIC_VICVECTADDR0_0, APS_VIC_V...
+
+/* Late FSP headers */
+#include <cpu/type-conversion.h>    // for fsp_v_fn_ptr_to_uptr, FSP__MISC__T...
+#include <debug/assert.h>           // for ASSERT, FSP__DEBUG__ASSERT_H
+#include <misc/bitops.h>            // for BIT, FSP__MISC__BITOPS_H
+#include <misc/macros.h>            // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <reg-access/reg-access.h>  // for writel_base_offset, readl_base_of...
+
+/* Module-specific FSP headers */
+#include <cpu/arm-vic.h>            // for arm_vic_context, ARM_VIC_IRQ_COUNT
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__TYPE_CONVERSION_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ASSERT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARM_VIC_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+void arm_vic_enable(uint32_t vic_base, uint32_t irq)
+{
+        writel_base_offset(BIT32_FN(irq), vic_base, APS_VIC_VICINTENABLE_0);
+}
+
+void arm_vic_disable(uint32_t vic_base, uint32_t irq)
+{
+        writel_base_offset(BIT32_FN(irq), vic_base, APS_VIC_VICINTENCLEAR_0);
+}
+
+void arm_vic_disable_all(uint32_t vic_base)
+{
+        writel_base_offset(~0U, vic_base, APS_VIC_VICINTENCLEAR_0);
+}
+
+void arm_vic_gen_software_int(uint32_t vic_base, uint32_t irq)
+{
+        writel_base_offset(BIT32_FN(irq), vic_base, APS_VIC_VICSOFTINT_0);
+}
+
+void arm_vic_clear_software_int(uint32_t vic_base, uint32_t irq)
+{
+        writel_base_offset(BIT32_FN(irq), vic_base, APS_VIC_VICSOFTINTCLEAR_0);
+}
+
+void arm_vic_set_isr_vect_addr(uint32_t vic_base, uint32_t irq,
+                                void (*isr_vect_addr)(void))
+{
+        ASSERT(irq < MAX_ARM_VIC_IRQS);
+
+        writel_base_offset((uint32_t)fsp_v_fn_ptr_to_uptr(isr_vect_addr), vic_base,
+                (uint32_t)APS_VIC_VICVECTADDR0_0 +
+                (uint32_t)(irq * (APS_VIC_VICVECTADDR1_0 - APS_VIC_VICVECTADDR0_0)));
+}
+
+uint32_t arm_vic_read_irq_status(uint32_t vic_base)
+{
+        return readl_base_offset(vic_base, APS_VIC_VICIRQSTATUS_0);
+}
+
+uint32_t arm_vic_read_fiq_status(uint32_t vic_base)
+{
+        return readl_base_offset(vic_base, APS_VIC_VICFIQSTATUS_0);
+}
+
+uint32_t arm_vic_read_raw_int_status(uint32_t vic_base)
+{
+        return readl_base_offset(vic_base, APS_VIC_VICRAWINTR_0);
+}
+
+void arm_vic_write_intselect(uint32_t vic_base, uint32_t intselect)
+{
+        writel_base_offset(intselect, vic_base, APS_VIC_VICINTSELECT_0);
+}
+
+uint32_t arm_vic_read_intselect(uint32_t vic_base)
+{
+        return readl_base_offset(vic_base, APS_VIC_VICINTSELECT_0);
+}
+
+void arm_vic_write_intenable(uint32_t vic_base, uint32_t intenable)
+{
+        writel_base_offset(intenable, vic_base, APS_VIC_VICINTENABLE_0);
+}
+
+uint32_t arm_vic_read_intenable(uint32_t vic_base)
+{
+        return readl_base_offset(vic_base, APS_VIC_VICINTENABLE_0);
+}
+
+void arm_vic_save_state(uint32_t vic_base, struct arm_vic_context *ctx)
+{
+        uint32_t i;
+
+        for (i = 0; i < ARM_VIC_IRQ_COUNT; i++) {
+                ctx->vect_addr[i] = readl_base_offset(vic_base, (uint32_t)APS_VIC_VICVECTADDR0_0 +
+                        (i * (uint32_t)(APS_VIC_VICVECTADDR1_0 - APS_VIC_VICVECTADDR0_0)));
+        }
+        ctx->intenable = readl_base_offset(vic_base, APS_VIC_VICINTENABLE_0);
+        ctx->intselect = readl_base_offset(vic_base, APS_VIC_VICINTSELECT_0);
+}
+
+void arm_vic_restore_state(uint32_t vic_base, const struct arm_vic_context *ctx)
+{
+        uint32_t i;
+
+        for (i = 0; i < ARM_VIC_IRQ_COUNT; i++) {
+                writel_base_offset(ctx->vect_addr[i], vic_base, (uint32_t)APS_VIC_VICVECTADDR0_0 +
+                        (i * (uint32_t)(APS_VIC_VICVECTADDR1_0 - APS_VIC_VICVECTADDR0_0)));
+        }
+        writel_base_offset(~(ctx->intenable), vic_base, APS_VIC_VICINTENCLEAR_0);
+        writel_base_offset(ctx->intenable, vic_base, APS_VIC_VICINTENABLE_0);
+        writel_base_offset(ctx->intselect, vic_base, APS_VIC_VICINTSELECT_0);
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/arm/common/irqapi-arm.c b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/common/irqapi-arm.c
new file mode 100644
index 0000000..d93c276
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/arm/common/irqapi-arm.c
@@ -0,0 +1,120 @@
+/*
+ * Copyright (c) 2015-2023 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>               // for bool
+#include <stdint.h>                // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>        // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <irq/safe-irqs.h>         // for irq_callback_fn, enter_critical
+#include <misc/attributes.h>       // for UNUSED
+#include <misc/macros.h>           // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <error/common-errors.h>   // for E_SUCCESS, error_t
+
+/* Module-specific FSP headers */
+#include <cpu/barriers.h>          // for barrier_compiler
+#include <cpu/armv7-mpu.h>         // for FSP__CPU__ARMV7_MPU_H, R5_P...
+#include <cpu/armv7-regs.h>        // for rd_cpsr, FSP__CPU__ARMV7_RE...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__BARRIERS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_MPU_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_REGS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+static inline uint32_t arm_get_mode(void)
+{
+    uint32_t cpsr;
+
+    cpsr = rd_cpsr();
+    return cpsr & R5_PSR_MODE_MASK;
+}
+
+bool in_interrupt(void)
+{
+    uint32_t mode = arm_get_mode();
+    return (mode == R5_PSR_MODE_FIQ) || (mode == R5_PSR_MODE_IRQ);
+}
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
+/* Weak dummy implementation for users with their own IRQ handling. */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+__attribute__((weak)) error_t irq_safe_set_handler(uint32_t irq, irq_callback_fn routine, void *data)
+{
+    UNUSED((irq));
+    UNUSED((&routine));
+    UNUSED((data));
+
+    return E_SUCCESS;
+}
+
+/* Weak dummy implementation for users with their own IRQ handling. */
+__attribute__((weak))
+void irq_handler(uint32_t irq)
+{
+    (void) irq;
+}
+
+/* Weak dummy implementation for users with their own implementation. */
+__attribute__((weak))
+void exit_critical(void)
+{
+    barrier_compiler();
+}
+
+/* Weak dummy implementation for users with their own implementation. */
+__attribute__((weak))
+void enter_critical(void)
+{
+    barrier_compiler();
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/exception.S b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/exception.S
new file mode 100644
index 0000000..efdb088
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/exception.S
@@ -0,0 +1,39 @@
+/**
+ * @file exception.S
+ *
+ * @brief Default assembly exception handler
+ *
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS`` AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "cpu/asm-helpers.h"
+
+.section ".text.exception_entry","ax",@progbits
+.balign 4
+FUNC exception_entry
+    jal riscv_panic
+EFUNC exception_entry
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/io_csb_over_pri.c b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/io_csb_over_pri.c
new file mode 100644
index 0000000..013e0d6
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/io_csb_over_pri.c
@@ -0,0 +1,47 @@
+/* _NVRM_COPYRIGHT_BEGIN_
+ *
+ * Copyright 2019-2020 by NVIDIA Corporation.  All rights reserved.  All
+ * information contained herein is proprietary and confidential to NVIDIA
+ * Corporation.  Any use, reproduction, or disclosure without the written
+ * permission of NVIDIA Corporation is prohibited.
+ *
+ * _NVRM_COPYRIGHT_END_
+ */
+#include NVRISCV64_MANUAL_ADDRESS_MAP
+#include <misc/nvmisc_drf.h>
+#if NVRISCV_IS_ENGINE_pmu
+#include <dev_pwr_csb.h>
+#endif
+#include <cpu/peregrine.h>
+#include <cpu/io.h>
+
+uint32_t csb_read(uint32_t addr)
+{
+#if NVRISCV_IS_ENGINE_pmu
+    if (((uintptr_t)addr <= DEVICE_EXTENT(NV_CPWR_THERM)) &&
+            ((uintptr_t)addr >= DEVICE_BASE(NV_CPWR_THERM)))
+    {
+        return pri_read(addr);
+    }
+    else
+#endif
+    {
+        return pri_read((FALCON_BASE +
+                        (addr >> NVRISCV_HAS_CSB_OVER_PRI_SHIFT)));
+    }
+}
+
+void csb_write(uint32_t addr, uint32_t val)
+{
+#ifdef NVRISCV_IS_ENGINE_pmu
+    if (((uintptr_t)addr <= DEVICE_EXTENT(NV_CPWR_THERM)) &&
+        ((uintptr_t)addr >= DEVICE_BASE(NV_CPWR_THERM)))
+    {
+        pri_write(addr, val);
+    }
+    else
+#endif
+    {
+        pri_write((FALCON_BASE + (addr >> NVRISCV_HAS_CSB_OVER_PRI_SHIFT)), val);
+    }
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/io_dio.c b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/io_dio.c
new file mode 100644
index 0000000..ca807da
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/io_dio.c
@@ -0,0 +1,413 @@
+/* _NVRM_COPYRIGHT_BEGIN_
+ *
+ * Copyright 2021-2023 by NVIDIA Corporation.  All rights reserved.  All
+ * information contained herein is proprietary and confidential to NVIDIA
+ * Corporation.  Any use, reproduction, or disclosure without the written
+ * permission of NVIDIA Corporation is prohibited.
+ *
+ * _NVRM_COPYRIGHT_END_
+ */
+#include <stdbool.h>
+#include <stddef.h>
+
+#include <misc/nvmisc_drf.h>
+#include <cpu/io_local.h>
+#include <cpu/io_dio.h>
+
+/* =============================================================================
+ * DIO additional macros
+ * ========================================================================== */
+#ifdef UTF_UCODE_BUILD
+uint32_t g_dio_max_wait = DIO_MAX_WAIT_DEFAULT;
+#   define DIO_MAX_WAIT g_dio_max_wait
+#else
+#   define DIO_MAX_WAIT 0xfffffffeU
+#endif
+
+// sw defines to unify hw manual defined dio registers fields
+// NV_PRGNLCL_FALCON_x and
+// NV_PRGNLCL_FALCON_DIO_x(i) with
+// NV_PRGNLCL_DIO_x
+//
+#define NV_PRGNLCL_DIO_DOC_CTRL_RESET_XMSB                                   16U
+#define NV_PRGNLCL_DIO_DOC_CTRL_RESET_XLSB                                   16U
+#define NV_PRGNLCL_DIO_DOC_CTRL_EMPTY_XMSB                                   18U
+#define NV_PRGNLCL_DIO_DOC_CTRL_EMPTY_XLSB                                   18U
+#define NV_PRGNLCL_DIO_DOC_CTRL_WR_FINISHED_XMSB                             19U
+#define NV_PRGNLCL_DIO_DOC_CTRL_WR_FINISHED_XLSB                             19U
+#define NV_PRGNLCL_DIO_DOC_CTRL_RD_FINISHED_XMSB                             20U
+#define NV_PRGNLCL_DIO_DOC_CTRL_RD_FINISHED_XLSB                             20U
+#define NV_PRGNLCL_DIO_DOC_CTRL_WR_ERROR_XMSB                                21U
+#define NV_PRGNLCL_DIO_DOC_CTRL_WR_ERROR_XLSB                                21U
+#define NV_PRGNLCL_DIO_DOC_CTRL_RD_ERROR_XMSB                                22U
+#define NV_PRGNLCL_DIO_DOC_CTRL_RD_ERROR_XLSB                                22U
+#define NV_PRGNLCL_DIO_DOC_CTRL_PROTOCOL_ERROR_XMSB                          23U
+#define NV_PRGNLCL_DIO_DOC_CTRL_PROTOCOL_ERROR_XLSB                          23U
+#define NV_PRGNLCL_DIO_DIC_CTRL_COUNT_XMSB                                    7U
+#define NV_PRGNLCL_DIO_DIC_CTRL_COUNT_XLSB                                    0U
+#define NV_PRGNLCL_DIO_DIC_CTRL_VALID_XMSB                                   19U
+#define NV_PRGNLCL_DIO_DIC_CTRL_VALID_XLSB                                   19U
+#define NV_PRGNLCL_DIO_DIC_CTRL_POP_XMSB                                     20U
+#define NV_PRGNLCL_DIO_DIC_CTRL_POP_XLSB                                     20U
+
+// sw defines for specific DOC Dx interface
+//
+#if NVRISCV_HAS_DIO_SE
+#define NV_PRGNLCL_DIO_DOC_D0_SEHUB_READ_XMSB                                16U
+#define NV_PRGNLCL_DIO_DOC_D0_SEHUB_READ_XLSB                                16U
+#define NV_PRGNLCL_DIO_DOC_D0_SEHUB_ADDR_XMSB                                15U
+#define NV_PRGNLCL_DIO_DOC_D0_SEHUB_ADDR_XLSB                                 0U
+#define NV_PRGNLCL_DIO_DOC_D1_SEHUB_WDATA_XMSB                               31U
+#define NV_PRGNLCL_DIO_DOC_D1_SEHUB_WDATA_XLSB                                0U
+#endif // NVRISCV_HAS_DIO_SE
+#if NVRISCV_HAS_DIO_SNIC
+#define NV_PRGNLCL_DIO_DOC_D0_SNIC_WDATA_XMSB                                31U
+#define NV_PRGNLCL_DIO_DOC_D0_SNIC_WDATA_XLSB                                 0U
+#define NV_PRGNLCL_DIO_DOC_D1_SNIC_ADDR_XMSB                                 31U
+#define NV_PRGNLCL_DIO_DOC_D1_SNIC_ADDR_XLSB                                  0U
+#define NV_PRGNLCL_DIO_DOC_D2_SNIC_READ_XMSB                                  0U
+#define NV_PRGNLCL_DIO_DOC_D2_SNIC_READ_XLSB                                  0U
+#endif // NVRISCV_HAS_DIO_SNIC
+#if NVRISCV_HAS_DIO_FBHUB
+#define NV_PRGNLCL_DIO_DOC_D0_FBHUB_READ_XMSB                                16U
+#define NV_PRGNLCL_DIO_DOC_D0_FBHUB_READ_XLSB                                16U
+#define NV_PRGNLCL_DIO_DOC_D0_FBHUB_ADDR_XMSB                                15U
+#define NV_PRGNLCL_DIO_DOC_D0_FBHUB_ADDR_XLSB                                 0U
+#define NV_PRGNLCL_DIO_DOC_D1_FBHUB_WDATA_XMSB                               31U
+#define NV_PRGNLCL_DIO_DOC_D1_FBHUB_WDATA_XLSB                                0U
+#endif // NVRISCV_HAS_DIO_FBHUB
+
+/* =============================================================================
+ * DIO control registers
+ * ========================================================================== */
+typedef struct
+{
+    uint32_t doc_ctrl;
+    uint32_t doc_d0, doc_d1, doc_d2;
+    uint32_t dic_ctrl;
+    uint32_t dic_d0, dic_d1, dic_d2;
+    uint32_t dio_error;
+} DIO_CTRL_REGS;
+
+static const DIO_CTRL_REGS dio_ctrl_regs_array[] =
+{
+    // DIO_TYPE_INVALID
+    //
+    {},
+#if NVRISCV_HAS_DIO_SE
+    // DIO_TYPE_SE
+    //
+    {
+        NV_PRGNLCL_FALCON_DOC_CTRL,
+        NV_PRGNLCL_FALCON_DOC_D0,
+        NV_PRGNLCL_FALCON_DOC_D1,
+        NV_PRGNLCL_FALCON_DOC_D2,
+        NV_PRGNLCL_FALCON_DIC_CTRL,
+        NV_PRGNLCL_FALCON_DIC_D0,
+        NV_PRGNLCL_FALCON_DIC_D1,
+        NV_PRGNLCL_FALCON_DIC_D2,
+        NV_PRGNLCL_FALCON_DIO_ERR,
+    },
+#endif // NVRISCV_HAS_DIO_SE
+#if NVRISCV_HAS_DIO_SNIC
+    // DIO_TYPE_SNIC
+    //
+    {
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DOC_CTRL(0),
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DOC_D0(0),
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DOC_D1(0),
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DOC_D2(0),
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DIC_CTRL(0),
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DIC_D0(0),
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DIC_D1(0),
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DIC_D2(0),
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DIO_ERR(0),
+    },
+#endif // NVRISCV_HAS_DIO_SNIC
+#if NVRISCV_HAS_DIO_FBHUB
+    // DIO_TYPE_FBHUB
+    //
+    {
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DOC_CTRL(0),
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DOC_D0(0),
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DOC_D1(0),
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DOC_D2(0),
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DIC_CTRL(0),
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DIC_D0(0),
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DIC_D1(0),
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DIC_D2(0),
+        (uint32_t)NV_PRGNLCL_FALCON_DIO_DIO_ERR(0),
+    },
+#endif // NVRISCV_HAS_DIO_FBHUB
+};
+
+/* =============================================================================
+ * DIO core helper functions
+ * ========================================================================== */
+static error_t
+dio_send_request
+(
+    DIO_TYPE type,
+    DIO_OPERATION operation,
+    uint32_t addr,
+    const uint32_t *p_data
+);
+
+static error_t
+dio_wait_for_doc_empty (DIO_TYPE type);
+
+static error_t
+dio_wait_for_operation_complete
+(
+    DIO_TYPE type,
+    DIO_OPERATION operation,
+    uint32_t *p_data
+);
+
+static bool
+dio_if_timeout (uint32_t *p_timer_count);
+
+static error_t
+dio_reset (DIO_TYPE type);
+
+/* =============================================================================
+ * DIO API implementation
+ * ========================================================================== */
+// add the PORT information
+error_t
+dio_read_write
+(
+    DIO_PORT port,
+    DIO_OPERATION operation,
+    uint32_t addr,
+    uint32_t *p_data
+)
+{
+    error_t status = E_SUCCESS;
+
+    if ((port.dio_type == DIO_TYPE_INVALID) ||
+        (port.dio_type >= DIO_TYPE_END)) {
+        status = (E_NOTSUPPORTED);
+    }
+
+    if (status == E_SUCCESS) {
+        status = dio_wait_for_doc_empty(port.dio_type);
+    }
+
+    if (status == E_SUCCESS) {
+        status = dio_send_request(port.dio_type, operation, addr, p_data);
+    }
+
+    if (status == E_SUCCESS) {
+        status = (dio_wait_for_operation_complete(port.dio_type, operation, p_data));
+    }
+
+    return status;
+} /* dio_read_write() */
+
+/* =============================================================================
+ * DIO core helper functions implementation
+ * ========================================================================== */
+/*!
+ * @brief   Send single dio read or write request
+ * @details Request is sent by populating corresponding DOCDx registers based on
+ *          DIO_TYPE and operation.
+ */
+static error_t
+dio_send_request
+(
+    DIO_TYPE type,
+    DIO_OPERATION operation,
+    uint32_t addr,
+    const uint32_t *p_data
+)
+{
+    error_t status = (E_SUCCESS);
+    switch (type) {
+#if NVRISCV_HAS_DIO_SE
+        case DIO_TYPE_SE:
+            local_write(dio_ctrl_regs_array[type].doc_d1,
+                DRF_NUM(_PRGNLCL, _DIO_DOC_D1, _SEHUB_WDATA,
+                    (operation == DIO_OPERATION_RD) ? 0U : *p_data));
+            local_write(dio_ctrl_regs_array[type].doc_d0,
+                DRF_NUM(_PRGNLCL, _DIO_DOC_D0, _SEHUB_READ,
+                    (operation == DIO_OPERATION_RD) ? 1U : 0U) |
+                DRF_NUM(_PRGNLCL, _DIO_DOC_D0, _SEHUB_ADDR, addr));
+            break;
+#endif // NVRISCV_HAS_DIO_SE
+#if NVRISCV_HAS_DIO_SNIC
+        case DIO_TYPE_SNIC:
+            local_write(dio_ctrl_regs_array[type].doc_d2,
+                DRF_NUM(_PRGNLCL, _DIO_DOC_D2, _SNIC_READ,
+                    (operation == DIO_OPERATION_RD) ? 1U : 0U));
+            local_write(dio_ctrl_regs_array[type].doc_d1,
+                DRF_NUM(_PRGNLCL, _DIO_DOC_D1, _SNIC_ADDR, addr));
+            local_write(dio_ctrl_regs_array[type].doc_d0,
+                DRF_NUM(_PRGNLCL, _DIO_DOC_D0, _SNIC_WDATA,
+                    (operation == DIO_OPERATION_RD) ? 0U : *p_data));
+            break;
+#endif // NVRISCV_HAS_DIO_SNIC
+#if NVRISCV_HAS_DIO_FBHUB
+        case DIO_TYPE_FBHUB:
+            local_write(dio_ctrl_regs_array[type].doc_d1,
+                DRF_NUM(_PRGNLCL, _DIO_DOC_D1, _FBHUB_WDATA,
+                    (operation == DIO_OPERATION_RD) ? 0U : *p_data));
+            local_write(dio_ctrl_regs_array[type].doc_d0,
+                DRF_NUM(_PRGNLCL, _DIO_DOC_D0, _FBHUB_READ,
+                    (operation == DIO_OPERATION_RD) ? 1U : 0U) |
+                DRF_NUM(_PRGNLCL, _DIO_DOC_D0, _FBHUB_ADDR, addr));
+            break;
+#endif // NVRISCV_HAS_DIO_FBHUB
+        default:
+            status = (E_NOTSUPPORTED);
+            break;
+    }
+    return status;
+} /* dio_send_request() */
+
+/*!
+ * @brief    Wait for free entry in DOC
+ * @details  The function tries to take a free entry in DOC and exit with no DIO
+ *           errors.
+ */
+static error_t
+dio_wait_for_doc_empty (DIO_TYPE type)
+{
+    uint32_t timer_count = 0U;
+    uint32_t doc_ctrl = 0U;
+    uint32_t dio_error_code = 0U;
+    error_t  status = (E_SUCCESS);
+    do {
+        doc_ctrl = local_read(dio_ctrl_regs_array[type].doc_ctrl);
+
+        if ((DRF_VAL(_PRGNLCL, _DIO_DOC_CTRL, _WR_ERROR, doc_ctrl) |
+             DRF_VAL(_PRGNLCL, _DIO_DOC_CTRL, _RD_ERROR, doc_ctrl) |
+             DRF_VAL(_PRGNLCL, _DIO_DOC_CTRL, _PROTOCOL_ERROR, doc_ctrl)) != 0U) {
+            dio_error_code = local_read(dio_ctrl_regs_array[type].dio_error);
+            status = dio_reset(type);
+            if (status == E_SUCCESS) {
+                status = ((dio_error_code != 0U) ? E_INVALID_PARAM : E_FAULT);
+            }
+        }
+
+        if (dio_if_timeout(&timer_count)) {
+            status = dio_reset(type);
+            if (status == E_SUCCESS) {
+                status = (E_TIMEOUT);
+            }
+        }
+
+    } while ((status == (E_SUCCESS)) &&
+             (DRF_VAL(_PRGNLCL, _DIO_DOC_CTRL, _EMPTY, doc_ctrl) == 0U));
+
+    return status;
+} /* dio_wait_for_doc_empty() */
+
+/*!
+ * @brief    Wait for operation to complete and get response for read.
+ * @details  We make sure no error is caused by the operation.
+ */
+static error_t
+dio_wait_for_operation_complete
+(
+    DIO_TYPE type,
+    DIO_OPERATION operation,
+    uint32_t *p_data
+)
+{
+    uint32_t timer_count = 0U;
+    uint32_t doc_ctrl = 0U;
+    uint32_t dio_error_code = 0U;
+    error_t  status = (E_SUCCESS);
+    do {
+        doc_ctrl = local_read(dio_ctrl_regs_array[type].doc_ctrl);
+        if ((DRF_VAL(_PRGNLCL, _DIO_DOC_CTRL, _WR_ERROR, doc_ctrl) |
+             DRF_VAL(_PRGNLCL, _DIO_DOC_CTRL, _RD_ERROR, doc_ctrl) |
+             DRF_VAL(_PRGNLCL, _DIO_DOC_CTRL, _PROTOCOL_ERROR, doc_ctrl)) != 0U) {
+            dio_error_code = local_read(dio_ctrl_regs_array[type].dio_error);
+            status = dio_reset(type);
+            if (status == E_SUCCESS) {
+                status = ((dio_error_code != 0U) ? E_INVALID_PARAM : E_FAULT);
+            }
+        }
+
+        if (dio_if_timeout(&timer_count)) {
+            status = dio_reset(type);
+            if (status == E_SUCCESS) {
+                status = (E_TIMEOUT);
+            }
+        }
+
+    } while ((status == (E_SUCCESS)) && (((operation == DIO_OPERATION_RD) ?
+        DRF_VAL(_PRGNLCL, _DIO_DOC_CTRL, _RD_FINISHED, doc_ctrl) :
+        DRF_VAL(_PRGNLCL, _DIO_DOC_CTRL, _WR_FINISHED, doc_ctrl)) == 0U));
+
+    // check dic_ctrl once doc_ctrl indicate operation done
+    //
+    timer_count = 0U;
+    if ((status == (E_SUCCESS)) && (operation == DIO_OPERATION_RD)) {
+        uint32_t dic_ctrl = 0U;
+        do {
+            dic_ctrl = local_read(dio_ctrl_regs_array[type].dic_ctrl);
+            if (dio_if_timeout(&timer_count)) {
+                status = dio_reset(type);
+                if (status == E_SUCCESS) {
+                    status = (E_TIMEOUT);
+                }
+            }
+
+        } while ((status == (E_SUCCESS)) &&
+                 (DRF_VAL(_PRGNLCL, _DIO_DIC_CTRL, _COUNT, dic_ctrl) == 0U));
+
+        // pop data and clear
+        //
+        if (status == (E_SUCCESS)) {
+            local_write(dio_ctrl_regs_array[type].dic_ctrl,
+                DRF_NUM(_PRGNLCL, _DIO_DIC_CTRL, _POP, 0x1U));
+            *p_data = local_read(dio_ctrl_regs_array[type].dic_d0);
+            local_write(dio_ctrl_regs_array[type].dic_ctrl,
+                DRF_NUM(_PRGNLCL, _DIO_DIC_CTRL, _VALID, 0x1U));
+        }
+    }
+
+    return status;
+} /* dio_wait_for_operation_complete */
+
+/*!
+ * @brief  Check the given counter reaches timeout
+ */
+static bool
+dio_if_timeout (uint32_t *p_timer_count)
+{
+    bool b_timeout = (*p_timer_count >= DIO_MAX_WAIT);
+    if (b_timeout == false)
+    {
+        (*p_timer_count)++;
+    }
+    return b_timeout;
+} /* dio_if_timeout */
+
+/*!
+ * @brief  Set clear bit and wait it to be cleared by hw on finish
+ */
+static error_t
+dio_reset (DIO_TYPE type)
+{
+    error_t status = (E_SUCCESS);
+    uint32_t timer_count = 0U;
+
+    local_write(dio_ctrl_regs_array[type].doc_ctrl,
+        DRF_NUM(_PRGNLCL, _DIO_DOC_CTRL, _RESET, 0x1U));
+
+    while (FLD_TEST_DRF_NUM(_PRGNLCL, _DIO_DOC_CTRL, _RESET, 0x1U,
+            local_read(dio_ctrl_regs_array[type].doc_ctrl))) {
+        if (dio_if_timeout(&timer_count)) {
+            status = (E_TIMEOUT);
+            break;
+        }
+    }
+
+    return status;
+} /* dio_reset */
+
+/*** end of file ***/
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/module-cpl-nvriscv-config.mk b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/module-cpl-nvriscv-config.mk
new file mode 100644
index 0000000..6fcf7f6
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/module-cpl-nvriscv-config.mk
@@ -0,0 +1,58 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cpl-nvriscv-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-cpl_*.mk' files.
+MODULE_CPL_CONFIG                   := 1
+MODULE_CPL_NVRISCV_CONFIG           := 1
+
+#
+# Define ARCH variables
+ARCH                                := nvidia
+ISA                                 := riscv
+CPU                                 := nvriscv
+
+#
+# Location of source code files
+CPL_SOC_IDS                          = $(FSP_COMMON_REPO)/soc/$(SOC)/ids/$(CLUSTER)
+CPL_SOC_IDS_CMN                      = $(FSP_COMMON_REPO)/soc/$(SOC)/ids/soc-common
+CPL_SOC_PORT                         = $(FSP_COMMON_REPO)/soc/$(SOC)/port/$(CLUSTER)
+CPL_VIC_DIR                          = $(FSP_COMMON_REPO)/drivers/vic
+CPL_ARCH_DIR                         = $(FSP_COMMON_REPO)/drivers/cpu/$(ARCH)
+CPL_ISA_DIR                          = $(FSP_COMMON_REPO)/drivers/cpu/$(ARCH)/$(ISA)
+MODULE_CPL_NVRISCV_SOURCE_DIR        =
+MODULE_CPL_NVRISCV_SOURCE_DIR       += $(CPL_SOC_IDS)
+MODULE_CPL_NVRISCV_SOURCE_DIR       += $(CPL_SOC_IDS_CMN)
+MODULE_CPL_NVRISCV_SOURCE_DIR       += $(CPL_SOC_PORT)
+MODULE_CPL_NVRISCV_SOURCE_DIR       += $(CPL_VIC_DIR)
+MODULE_CPL_NVRISCV_SOURCE_DIR       += $(CPL_ISA_DIR)/$(CPU)
+MODULE_CPL_NVRISCV_SOURCE_DIR       += $(CPL_ARCH_DIR)/common
+MODULE_CPL_NVRISCV_SOURCE_DIR       += $(CPL_ISA_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_CPL_NVRISCV_INCLUDES          = -I $(FSP_COMMON_REPO)/include/osa/$(OSA)/$(ARCH)/$(ISA)/$(CPU)
+MODULE_CPL_NVRISCV_INCLUDES         += -I $(FSP_COMMON_REPO)/include/cpu/$(ARCH)/$(ISA)
+MODULE_CPL_NVRISCV_INCLUDES         += -I $(FSP_COMMON_REPO)/include/cpu/$(ARCH)/$(ISA)/$(CPU)
+MODULE_CPL_NVRISCV_INCLUDES         += -I $(FSP_COMMON_REPO)/include/cpu/$(ARCH)/common
+MODULE_CPL_NVRISCV_INCLUDES         += -I $(FSP_COMMON_REPO)/include/cpu/$(ARCH)/$(ISA)/common
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/module-cpl-nvriscv.mk b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/module-cpl-nvriscv.mk
new file mode 100644
index 0000000..c7b72a1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/module-cpl-nvriscv.mk
@@ -0,0 +1,90 @@
+# # Copyright (c) 2020-2023, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cpl-nvriscv.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_CPL_NVRISCV_NAME         := CPL_NVRISCV
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_CPL_DEFINED              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_CPU_DEPENDS              := CPL_NVRISCV CPL
+$(foreach _,$(CONFIG_CPU_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_CPL_NVRISCV_C_SRC         =
+
+ifeq ($(NVRISCV_FEATURE_MPU),y)
+MODULE_CPL_NVRISCV_C_SRC        += $(CPL_ISA_DIR)/riscv-mpu.c
+endif
+
+ifeq ($(NVRISCV_FEATURE_DIO),y)
+MODULE_CPL_NVRISCV_C_SRC        += $(CPL_ISA_DIR)/io_dio.c
+endif
+
+ifeq ($(NVRISCV_HAS_CSB_MMIO),n)
+ifeq ($(NVRISCV_HAS_PRI),y)
+ifeq ($(NVRISCV_HAS_CSB_OVER_PRI),y)
+MODULE_CPL_NVRISCV_C_SRC        += $(CPL_ISA_DIR)/io_csb_over_pri.c
+endif
+endif
+endif
+
+ifeq ($(NVRISCV_HAS_SBI),y)
+MODULE_CPL_NVRISCV_C_SRC        += $(CPL_ISA_DIR)/shutdown_sbi.c
+else
+MODULE_CPL_NVRISCV_C_SRC        += $(CPL_ISA_DIR)/shutdown_m.c
+endif
+
+#
+# Assembly source
+MODULE_CPL_NVRISCV_ASM_SRC       =
+
+ifeq ($(NVRISCV_FEATURE_START),y)
+MODULE_CPL_NVRISCV_ASM_SRC      += $(CPL_ISA_DIR)/start.S
+endif
+
+ifeq ($(NVRISCV_FEATURE_EXCEPTION),y)
+MODULE_CPL_NVRISCV_ASM_SRC      += $(CPL_ISA_DIR)/exception.S
+endif
+
+#
+# Special C Flags
+MODULE_CPL_NVRISCV_C_FLAGS       =
+
+#
+# Special ASM Flags
+MODULE_CPL_NVRISCV_ASM_FLAGS     =
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/riscv-mpu.c b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/riscv-mpu.c
new file mode 100644
index 0000000..7bbe204
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/riscv-mpu.c
@@ -0,0 +1,433 @@
+/* _NVRM_COPYRIGHT_BEGIN_
+ *
+ * Copyright 2020-2022 by NVIDIA Corporation.  All rights reserved.  All
+ * information contained herein is proprietary and confidential to NVIDIA
+ * Corporation.  Any use, reproduction, or disclosure without the written
+ * permission of NVIDIA Corporation is prohibited.
+ *
+ * _NVRM_COPYRIGHT_END_
+ */
+
+
+
+#include <stddef.h>
+#include <misc/bitops.h>            // for BIT64, bitmap ops
+#include <libc-lite/libc.h>         // for memset
+#include <misc/nvmisc_drf.h>        // before riscv-mpu.h
+#include <cpu/riscv-mpu.h>
+#include <cpu/csr.h>
+
+//
+// MISRA 1.2 RFD: Inline assembly
+// MISRA 4.9 RFD: function-like macros
+// MISRA 15.1 RFD: Forward gotos
+// MISRA 8.7 RFD: Functions with external linkage only referenced in one translation unit
+//
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
+
+//
+// each value of SMPUIDX allows us to access this many MPU entries via
+// NV_RISCV_CSR_SMPUACC and NV_RISCV_CSR_SMPUDTY
+//
+#define MPUIDX2_ENTRIES_PER_INDEX DRF_SIZE(NV_RISCV_CSR_SMPUACC_ACC)
+
+/**
+ * @brief Select a HW MPU Entry. subsequent accesses to SMPUVA, SMPUPA,
+ * SMPURNG, and SMPUATTR will access the selected entry.
+ *
+ * @param[in]  index index of the HW MPU entry to select.
+ *
+ * @return None
+ */
+static void mpu_idx_select(uint64_t index)
+{
+    csr_write(NV_RISCV_CSR_SMPUIDX,
+              DRF_NUM64(_RISCV, _CSR_SMPUIDX, _INDEX, index));
+}
+
+/**
+ * @brief Select a HW MPU Entry block. subsequent accesses to SMPUACC
+ * and SMPUDTY will access the selected entry.
+ *
+ * @param[in]  index start index of the HW MPU entry block to select.
+ *
+ * @return None
+ */
+static void mpu_idx2_select(uint8_t index)
+{
+    uint8_t reg = index / MPUIDX2_ENTRIES_PER_INDEX;
+
+    csr_write(NV_RISCV_CSR_SMPUIDX2, DRF_NUM64(_RISCV, _CSR_SMPUIDX2, _IDX, reg));
+}
+
+error_t
+mpu_init(mpu_context_t *p_ctx)
+{
+    error_t status = E_SUCCESS;
+    uint64_t smpuctl;
+    uint8_t idx;
+
+    if (p_ctx == NULL)
+    {
+        status = E_INVALID_PARAM;
+        goto out;
+    }
+
+    (void) memset(p_ctx, 0, sizeof(mpu_context_t));
+
+    //
+    // Read the entry count. The number of entries could be
+    // limited by M-mode code if some entries are used by another partition
+    //
+    smpuctl = csr_read(NV_RISCV_CSR_SMPUCTL);
+    p_ctx->mpu_entry_count = (uint8_t) DRF_VAL64(_RISCV_CSR, _SMPUCTL, _ENTRY_COUNT, smpuctl);
+
+    // Build entries for existing MPU settings
+    for (idx = 0; idx < p_ctx->mpu_entry_count; idx++)
+    {
+        // Check if the MPU entry has already been set
+        mpu_idx_select(idx);
+        uint64_t virt_addr = csr_read(NV_RISCV_CSR_SMPUVA);
+        if (FLD_TEST_DRF_NUM64(_RISCV_CSR, _SMPUVA, _VLD, 1U, virt_addr))
+        {
+            bitmap_set_bit(p_ctx->mpu_reserved_bitmap, NV_RISCV_CSR_MPU_ENTRY_COUNT / BITMAP_ELEMENT_SIZE, idx);
+        }
+    }
+
+out:
+    return status;
+}
+
+error_t
+mpu_enable(void)
+{
+    csr_write(NV_RISCV_CSR_SATP,
+        DRF_DEF64(_RISCV_CSR, _SATP, _MODE, _NVMPU) |
+        DRF_DEF64(_RISCV_CSR, _SATP, _ASID, _BARE)  |
+        DRF_DEF64(_RISCV_CSR, _SATP, _PPN, _BARE));
+    return E_SUCCESS;
+}
+
+error_t
+mpu_reserve_entry(mpu_context_t *p_ctx, uint32_t search_origin, mpu_handle_t *p_reserved_handle)
+{
+    error_t status = E_FAULT;
+    uint32_t idx;
+
+    if ((p_ctx == NULL) || (p_reserved_handle == NULL))
+    {
+        status = E_INVALID_PARAM;
+        goto out;
+    }
+
+    for (idx = search_origin; idx < p_ctx->mpu_entry_count; idx++)
+    {
+        if (!bitmap_test_bit(p_ctx->mpu_reserved_bitmap, NV_RISCV_CSR_MPU_ENTRY_COUNT / BITMAP_ELEMENT_SIZE, idx))
+        {
+            bitmap_set_bit(p_ctx->mpu_reserved_bitmap, NV_RISCV_CSR_MPU_ENTRY_COUNT / BITMAP_ELEMENT_SIZE, idx);
+            *p_reserved_handle = idx;
+            status = E_SUCCESS;
+            goto out;
+        }
+    }
+
+out:
+    return status;
+}
+
+error_t
+mpu_free_entry(mpu_context_t *p_ctx, mpu_handle_t handle)
+{
+    error_t status = E_SUCCESS;
+
+    if ((p_ctx == NULL) ||
+        (handle >= p_ctx->mpu_entry_count) ||
+        (!bitmap_test_bit(p_ctx->mpu_reserved_bitmap, NV_RISCV_CSR_MPU_ENTRY_COUNT / BITMAP_ELEMENT_SIZE, handle)))
+    {
+        status = E_INVALID_PARAM;
+        goto out;
+    }
+
+    bitmap_clear_bit(p_ctx->mpu_reserved_bitmap, NV_RISCV_CSR_MPU_ENTRY_COUNT / BITMAP_ELEMENT_SIZE, handle);
+
+out:
+    return status;
+}
+
+error_t
+mpu_write_entry
+(
+    const mpu_context_t *p_ctx,
+    mpu_handle_t handle,
+    uint64_t va,
+    uint64_t pa,
+    uint64_t rng,
+    uint64_t attr
+)
+{
+    error_t status = E_SUCCESS;
+
+    if ((p_ctx == NULL) ||
+        (handle >= p_ctx->mpu_entry_count) ||
+        (!bitmap_test_bit(p_ctx->mpu_reserved_bitmap, NV_RISCV_CSR_MPU_ENTRY_COUNT / BITMAP_ELEMENT_SIZE, handle)))
+    {
+        status = E_INVALID_PARAM;
+        goto out;
+    }
+
+    mpu_idx_select(handle);
+    csr_clear(NV_RISCV_CSR_SMPUVA, DRF_NUM64(_RISCV_CSR, _SMPUVA, _VLD, 1));
+    csr_write(NV_RISCV_CSR_SMPUPA, pa);
+    csr_write(NV_RISCV_CSR_SMPURNG, rng);
+    csr_write(NV_RISCV_CSR_SMPUATTR, attr);
+    csr_write(NV_RISCV_CSR_SMPUVA, va);
+
+out:
+    return status;
+}
+
+error_t
+mpu_read_entry
+(
+    const mpu_context_t *p_ctx,
+    mpu_handle_t handle,
+    uint64_t *p_va,
+    uint64_t *p_pa,
+    uint64_t *p_rng,
+    uint64_t *p_attr
+)
+{
+    error_t status = E_SUCCESS;
+
+    if ((p_ctx == NULL) ||
+        (handle >= p_ctx->mpu_entry_count) ||
+        (!bitmap_test_bit(p_ctx->mpu_reserved_bitmap, NV_RISCV_CSR_MPU_ENTRY_COUNT / BITMAP_ELEMENT_SIZE, handle)))
+    {
+        status = E_INVALID_PARAM;
+        goto out;
+    }
+
+    mpu_idx_select(handle);
+    if (p_va != NULL)
+    {
+        *p_va = csr_read(NV_RISCV_CSR_SMPUVA);
+    }
+
+    if (p_pa != NULL)
+    {
+        *p_pa = csr_read(NV_RISCV_CSR_SMPUPA);
+    }
+
+    if (p_rng != NULL)
+    {
+        *p_rng = csr_read(NV_RISCV_CSR_SMPURNG);
+    }
+
+    if (p_attr != NULL)
+    {
+        *p_attr = csr_read(NV_RISCV_CSR_SMPUATTR);
+    }
+
+out:
+    return status;
+}
+
+error_t
+mpu_enable_entry(const mpu_context_t *p_ctx, mpu_handle_t handle)
+{
+    error_t status = E_SUCCESS;
+
+    if ((p_ctx == NULL) ||
+        (handle >= p_ctx->mpu_entry_count) ||
+        (!bitmap_test_bit(p_ctx->mpu_reserved_bitmap, NV_RISCV_CSR_MPU_ENTRY_COUNT / BITMAP_ELEMENT_SIZE, handle)))
+    {
+        status = E_INVALID_PARAM;
+        goto out;
+    }
+
+    mpu_idx_select(handle);
+    csr_set(NV_RISCV_CSR_SMPUVA, DRF_NUM64(_RISCV_CSR, _SMPUVA, _VLD, 1));
+
+out:
+    return status;
+}
+
+error_t
+mpu_disable_entry(const mpu_context_t *p_ctx, mpu_handle_t handle)
+{
+    error_t status = E_SUCCESS;
+
+    if ((p_ctx == NULL) ||
+        (handle >= p_ctx->mpu_entry_count) ||
+        (!bitmap_test_bit(p_ctx->mpu_reserved_bitmap, NV_RISCV_CSR_MPU_ENTRY_COUNT / BITMAP_ELEMENT_SIZE, handle)))
+    {
+        status = E_INVALID_PARAM;
+        goto out;
+    }
+
+    mpu_idx_select(handle);
+    csr_clear(NV_RISCV_CSR_SMPUVA, DRF_NUM64(_RISCV_CSR, _SMPUVA, _VLD, 1));
+
+out:
+    return status;
+}
+
+error_t
+mpu_is_accessed(const mpu_context_t *p_ctx, mpu_handle_t handle, bool *b_accessed)
+{
+    error_t status = E_SUCCESS;
+    uint64_t smpuacc;
+    uint8_t idx_to_test;
+
+    if ((p_ctx == NULL) ||
+        (handle >= p_ctx->mpu_entry_count) ||
+        (!bitmap_test_bit(p_ctx->mpu_reserved_bitmap, NV_RISCV_CSR_MPU_ENTRY_COUNT / BITMAP_ELEMENT_SIZE, handle)) ||
+        (b_accessed == NULL))
+    {
+        status = E_INVALID_PARAM;
+        goto out;
+    }
+
+    mpu_idx2_select((uint8_t)handle);
+    smpuacc = csr_read(NV_RISCV_CSR_SMPUACC);
+    idx_to_test = (uint8_t) handle % MPUIDX2_ENTRIES_PER_INDEX;
+    *b_accessed = ((smpuacc & BIT64(idx_to_test)) != 0U);
+
+out:
+    return status;
+}
+
+error_t
+mpu_is_dirty(const mpu_context_t *p_ctx, mpu_handle_t handle, bool *b_dirty)
+{
+    error_t status = E_SUCCESS;
+    uint64_t smpudty;
+    uint8_t idx_to_test;
+
+    if ((p_ctx == NULL) ||
+        (handle >= p_ctx->mpu_entry_count) ||
+        (!bitmap_test_bit(p_ctx->mpu_reserved_bitmap, NV_RISCV_CSR_MPU_ENTRY_COUNT / BITMAP_ELEMENT_SIZE, handle)) ||
+        (b_dirty == NULL))
+    {
+        status = E_INVALID_PARAM;
+        goto out;
+    }
+
+    mpu_idx2_select((uint8_t)handle);
+    smpudty = csr_read(NV_RISCV_CSR_SMPUDTY);
+    idx_to_test = (uint8_t) handle % MPUIDX2_ENTRIES_PER_INDEX;
+    *b_dirty = ((smpudty & BIT64(idx_to_test)) != 0U);
+
+out:
+    return status;
+}
+
+error_t
+mpu_clear_accessed_bit(const mpu_context_t *p_ctx, mpu_handle_t handle)
+{
+    error_t status = E_SUCCESS;
+    uint8_t idx_to_clear;
+
+    if ((p_ctx == NULL) ||
+        (handle >= p_ctx->mpu_entry_count) ||
+        (!bitmap_test_bit(p_ctx->mpu_reserved_bitmap, NV_RISCV_CSR_MPU_ENTRY_COUNT / BITMAP_ELEMENT_SIZE, handle)))
+    {
+        status = E_INVALID_PARAM;
+        goto out;
+    }
+
+    mpu_idx2_select((uint8_t)handle);
+    idx_to_clear = (uint8_t) handle % MPUIDX2_ENTRIES_PER_INDEX;
+    csr_clear(NV_RISCV_CSR_SMPUACC, BIT64(idx_to_clear));
+
+out:
+    return status;
+}
+
+error_t
+mpu_clear_dirty_bit(const mpu_context_t *p_ctx, mpu_handle_t handle)
+{
+    error_t status = E_SUCCESS;
+    uint8_t idx_to_clear;
+
+    if ((p_ctx == NULL) ||
+        (handle >= p_ctx->mpu_entry_count) ||
+        (!bitmap_test_bit(p_ctx->mpu_reserved_bitmap, NV_RISCV_CSR_MPU_ENTRY_COUNT / BITMAP_ELEMENT_SIZE, handle)))
+    {
+        status = E_INVALID_PARAM;
+        goto out;
+    }
+
+    mpu_idx2_select((uint8_t)handle);
+    idx_to_clear = (uint8_t) handle % MPUIDX2_ENTRIES_PER_INDEX;
+    csr_clear(NV_RISCV_CSR_SMPUDTY, BIT64(idx_to_clear));
+
+out:
+    return status;
+}
+
+error_t
+mpu_va_to_pa(const mpu_context_t *p_ctx, uint64_t va, bool b_only_enabled, uint64_t *p_pa)
+{
+    error_t status = E_INVALID_PARAM;
+    uint8_t idx;
+
+    if ((p_ctx == NULL) || (p_pa == NULL))
+    {
+        status = E_INVALID_PARAM;
+        goto out;
+    }
+
+    for (idx = 0; idx < p_ctx->mpu_entry_count; idx++)
+    {
+        if (bitmap_test_bit(p_ctx->mpu_reserved_bitmap, NV_RISCV_CSR_MPU_ENTRY_COUNT / BITMAP_ELEMENT_SIZE, idx))
+        {
+            mpu_idx_select(idx);
+            uint64_t va_reg = csr_read(NV_RISCV_CSR_SMPUVA);
+            uint64_t va_base = va_reg & ~NV_RISCV_CSR_MPU_PAGE_MASK;
+            uint64_t rng;
+
+            //If entry is disabled or va is below range, don't check this entry
+            if ((b_only_enabled && FLD_TEST_DRF_NUM64(_RISCV_CSR, _SMPUVA, _VLD, 0U, va_reg)) ||
+                (va_base > va))
+            {
+                continue;
+            }
+
+            rng = csr_read(NV_RISCV_CSR_SMPURNG) & ~NV_RISCV_CSR_MPU_PAGE_MASK;
+
+            // check for overflow in va_base + rng (CERT-C). Shoudln't happen in a sanely-programmed entry.
+            if ((UINT64_MAX - va_base) < rng)
+            {
+                continue;
+            }
+
+            if (va < (va_base + rng))
+            {
+                //Do a manual translation
+                uint64_t pa_base = csr_read(NV_RISCV_CSR_SMPUPA) & ~NV_RISCV_CSR_MPU_PAGE_MASK;
+
+                // check for overflow in (va - va_base) + pa_base; (CERT-C). Shoudln't happen in a sanely-programmed entry.
+                if ((UINT64_MAX - pa_base) < (va - va_base))
+                {
+                    continue;
+                }
+
+                *p_pa = (va - va_base) + pa_base;
+                status = E_SUCCESS;
+                break;
+            }
+        }
+    }
+
+out:
+    return status;
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/shutdown_m.c b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/shutdown_m.c
new file mode 100644
index 0000000..2928ea5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/shutdown_m.c
@@ -0,0 +1,106 @@
+/**
+ * @file shutdown_m.c
+ *
+ * @brief Describes behavior of shutdown API in M-Mode.
+ *
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS`` AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/gcc_attrs.h>
+#include <misc/gcc_builtins.h>
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+#include <cpu/csr.h>
+
+/* Late FSP headers */
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <cpu/shutdown.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__SHUTDOWN_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__CSR_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__GCC_ATTRS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__GCC_BUILTINS_H, "Header file missing or invalid.")
+
+GCC_ATTR_NAKED
+GCC_ATTR_NORETURN
+GCC_ATTR_NO_SSP
+static void riscv_shutdown_int(void)
+{
+    __asm__("csrw   mie,  zero \n" // Disable interrupts
+            "csrrw  zero, 0x800, zero\n" // lwfenceIO
+#if defined(NV_RISCV_CSR_MOPT)
+            "csrrwi zero, 0x7d8, 0\n" // write MOPT.HALT
+#endif
+            "1: \n"
+            "j      1b\n" // infinite loop if halt fails (or not available)
+    );
+    _Static_assert(NV_RISCV_CSR_LWFENCEIO == 0x800,
+                   "LWFENCEIO address has changed. Update assembly in riscv_shutdown_int.");
+    _Static_assert(NV_RISCV_CSR_MOPT == 0x7d8,
+                   "MOPT address has changed. Update assembly in riscv_shutdown_int.");
+    _Static_assert(NV_RISCV_CSR_MOPT_CMD_HALT == 0,
+                   "MOPT_CMD_HALT value has changed. Update assembly in riscv_shutdown_int.");
+    NVRV_BUILTIN_UNREACHABLE();
+}
+
+GCC_ATTR_NAKED
+GCC_ATTR_NORETURN
+GCC_ATTR_NO_SSP
+void riscv_panic(void)
+{
+    riscv_shutdown_int();
+}
+
+GCC_ATTR_NORETURN
+GCC_ATTR_NO_SSP
+void riscv_shutdown(void)
+{
+    riscv_shutdown_int();
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/** end of file **/
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/shutdown_sbi.c b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/shutdown_sbi.c
new file mode 100644
index 0000000..c7397c3
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/shutdown_sbi.c
@@ -0,0 +1,96 @@
+/**
+ * @file shutdown_sbi.c
+ *
+ * @brief Describes behavior of shutdown API in S-Mode.
+ *
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS`` AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/gcc_attrs.h>
+#include <misc/gcc_builtins.h>
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>       // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <cpu/shutdown.h>
+#include <cpu/sbi.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__SBI_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__SHUTDOWN_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__GCC_ATTRS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__GCC_BUILTINS_H, "Header file missing or invalid.")
+
+GCC_ATTR_NAKED
+GCC_ATTR_NOINLINE
+GCC_ATTR_NORETURN
+GCC_ATTR_NO_SSP
+void riscv_panic(void)
+{
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ ("li a7, 8 \n" // SBI_EXTENSION_SHUTDOWN
+             "li a6, 0 \n" // SBI_NVFUNC_FIRST
+             "ecall \n"
+             "1: \n"
+             "j 1b \n"
+    );
+    // If one of those assert is triggered, that means function needs to be updated
+    _Static_assert(SBI_EXTENSION_SHUTDOWN == 8, "Shutdown extension id changed.");
+    _Static_assert(SBI_NVFUNC_FIRST == 0, "Function id changed.");
+    NVRV_BUILTIN_UNREACHABLE();
+}
+
+GCC_ATTR_NORETURN
+GCC_ATTR_NO_SSP
+void riscv_shutdown(void)
+{
+    (void) sbicall0((int32_t)SBI_EXTENSION_SHUTDOWN, (int32_t)SBI_NVFUNC_FIRST);
+    NVRV_BUILTIN_UNREACHABLE();
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/** end of file **/
diff --git a/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/start.S b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/start.S
new file mode 100644
index 0000000..29a5060
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/cpu/nvidia/riscv/nvriscv/start.S
@@ -0,0 +1,116 @@
+/**
+ * @file start.S
+ *
+ * @brief Default assembly startup code
+ *
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS`` AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <cpu/csr.h>
+#include <cpu/asm-helpers.h>
+
+.section ".text.startup","ax",@progbits
+.balign 4
+FUNC startup
+    j    do_reset
+
+do_reset:
+    ZREG(x1)
+    ZREG(x2)
+    ZREG(x3)
+    ZREG(x4)
+    ZREG(x5)
+    ZREG(x6)
+    ZREG(x7)
+    ZREG(x8)
+    ZREG(x9)
+    ZREG(x10)
+    ZREG(x11)
+    ZREG(x12)
+    ZREG(x13)
+    ZREG(x14)
+    ZREG(x15)
+    ZREG(x16)
+    ZREG(x17)
+    ZREG(x18)
+    ZREG(x19)
+    ZREG(x20)
+    ZREG(x21)
+    ZREG(x22)
+    ZREG(x23)
+    ZREG(x24)
+    ZREG(x25)
+    ZREG(x26)
+    ZREG(x27)
+    ZREG(x28)
+    ZREG(x29)
+    ZREG(x30)
+    ZREG(x31)
+
+    // write mtvec and make sure it sticks
+#if NVRISCV_FEATURE_EXCEPTION == 1
+    la    t0, exception_entry
+#else
+    la    t0, riscv_panic_trampoline
+#endif
+
+#if (NVRISCV_CONFIG_CPU_MODE==3)
+    csrw  mtvec, t0
+#endif
+#if (NVRISCV_HAS_S_MODE == 1)
+    csrw  stvec, t0
+#endif
+
+    // write mrsp on specific chips due to HW bug
+    // See https://nvbugs/3342254
+#if ((NVRISCV_IS_CHIP_ls10 == 1) || (NVRISCV_IS_CHIP_gh100==1)) && (NVRISCV_CONFIG_CPU_MODE==3)
+    csrw NV_RISCV_CSR_MRSP, zero
+#endif
+
+    la    sp, _stack_bottom
+    LREG  sp, 0(sp)
+    addi  sp, sp, -0x10
+    SREG  zero, 0(sp)
+    SREG  zero, 8(sp)
+    jal   main
+    // halt the core one way or another
+    jal   riscv_shutdown
+_end:
+    j _end
+EFUNC startup
+
+#if NVRISCV_FEATURE_EXCEPTION == 0
+.balign 4
+FUNC riscv_panic_trampoline
+    jal riscv_panic
+EFUNC riscv_panic_trampoline
+#endif
+
+// We need that dereference to handle chips where dmem is far away from imem
+  .balign 8
+_stack_bottom:
+  .dword _libnvriscv_stack_bottom
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/abort.c b/spe-freertos-bsp/fsp/source/drivers/debug/abort.c
new file mode 100644
index 0000000..1dd5802
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/abort.c
@@ -0,0 +1,222 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stddef.h>                 // for NULL
+#include <stdint.h>                 // for uint32_t
+#include <stdbool.h>                // for true
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>         // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <osa/rtos-task.h>          // for rtosTaskGetCurrentTaskHandle, rto...
+#include <osa/rtos-values.h>        // for rtosTRUE
+#include <cpu/armv7-regs.h>         // for disable_interrupts, FSP__ARM__ARM...
+#include <cpu/barriers.h>           // for barrier_compiler, barrier_memory_...
+#include <cpu/cache.h>              // for dcache_clean_all, FSP__ARM__COMMO...
+#include <error/common-errors.h>    // for error_t
+#include <misc/attributes.h>        // for NO_RETURN, WEAK
+#include <misc/macros.h>            // START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <debug/abort-sys-codes.h>  // for ABORT_RTOS, FSP__DEBUG__ABORT_SYS...
+#include <debug/abort.h>            // for FSP__DEBUG__ABORT_H, abort_full
+#include <debug/sections-abort.h>   // Immune from CT_ASSERT protection
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_VALUES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_REGS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__BARRIERS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__CACHE_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ABORT_SYS_CODES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ABORT_H, "Header file missing or invalid.")
+
+/**
+ * abort_hook()         - default abort hook function
+ *
+ * @reason:             abort reason code
+ * @xErrorCode:         error or argument to the abort
+ * @xHandleOfTaskWithError:     task where the error originated from
+ * @pcErrorString:      string to be reported with the error
+ *
+ * This function is a weakly bound function that serves as the default
+ * implemenation of the abort hook in the case when an application doesn't
+ * define its own version.
+ *
+ * Return Value:
+ *      none
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx", MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+SECTION_ABORT_TEXT WEAK void
+abort_hook(const uint32_t reason,
+           error_t xErrorCode,
+           rtosTaskHandle xHandleOfTaskWithError,
+           const char *pcErrorString)
+{
+}
+
+/**
+ * abort_full()         - abort to allow all arguments to be provided
+ *
+ * @reason:             abort reason code
+ * @xErrorCode:         error or argument to the abort
+ * @xHandleOfTaskWithError:     task where the error originated from
+ * @pcErrorString:      string to be reported with the error
+ *
+ * This is the full form of abort that unifies the various other interfaces
+ * when the system fails.
+ *
+ * This function does not return.
+ */
+SECTION_ABORT_TEXT NO_RETURN void
+abort_full(const uint32_t reason,
+           error_t xErrorCode,
+           rtosTaskHandle xHandleOfTaskWithError,
+           const char *pcErrorString)
+{
+    /*
+     * Don't allow anything else to run after this point.
+     */
+    (void)disable_interrupts();
+
+    /*
+     * Call the abort_hook.
+     */
+    abort_hook(reason, xErrorCode, xHandleOfTaskWithError, pcErrorString);
+
+    /*
+     * Wait for all operations to complete and to clean the
+     * dCache so that someone can examine DRAM if they so wish.
+     */
+    barrier_memory_order();
+    barrier_memory_complete();
+    dcache_clean_all();
+
+    /*
+     * Done.
+     */
+    while (true) {
+        /*
+         * Make sure that the infinite loop has side effects
+         * so that the optimizer doesn't try move or remove it.
+         */
+        barrier_compiler();
+    }
+
+    /*
+     * Never reached.
+     */
+}
+
+/**
+ * tegra_abort()        - signal an abort and halt the R5
+ *
+ * @reason:             abort reason code
+ * @arg:                a 32-bit argument
+ *
+ * This function will "abort" the exectution of the R5.  This is generally
+ * called because some fatal condition has been detected and continued
+ * execution is ill advised.
+ *
+ * It will disable the watchdog as well as suspending all tasks and stopping
+ * the scheduler.  It will also disable all interrupts.
+ *
+ * Prior to entering into an infinte loop, it will call an "abort hook" to
+ * allow the platform to run some additional code.
+ */
+SECTION_ABORT_TEXT void
+tegra_abort(const uint32_t reason,
+            const uint32_t arg)
+{
+    rtosTaskHandle      cur_task        = NULL;
+
+    /*
+     * When getting the current task handle, make sure that the
+     * scheduler is running (mainly to make sure that it's been
+     * initialized/statrted)
+     */
+    if (rtosTaskIsSchedulerStarted() == rtosTRUE) {
+        cur_task = rtosTaskGetCurrentTaskHandle();
+    }
+
+    abort_full(reason, (error_t)arg, cur_task, NULL);
+
+    /*
+     * Never reached.
+     */
+}
+
+/**
+ * error_hook           - SafeRTOS will call this when it has a fatal error
+ *
+ * @xHandleOfTaskWithError:     handle of task that was running when error
+ *                              occured
+ * @pcErrorString:              pointer to string to be reported
+ * @xErrorCode:                 Error code to be reported
+ *
+ * This function will be called when there SafeRTOS detects a fatal error.
+ * The objective of this function is to report the error and then "safe"
+ * the system.
+ *
+ * This function is not to be called directly execept by SafeRTOS.
+ *
+ * This function does not return.
+ */
+SECTION_ABORT_TEXT void
+error_hook(rtosTaskHandle xHandleOfTaskWithError,
+           const char *pcErrorString,
+           error_t xErrorCode)
+{
+    abort_full(ABORT_RTOS, xErrorCode,
+               xHandleOfTaskWithError, pcErrorString);
+
+    /*
+     * Never reached.
+     */
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/assert.c b/spe-freertos-bsp/fsp/source/drivers/debug/assert.c
new file mode 100644
index 0000000..4c9a0b5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/assert.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                 // for uint32_t
+#include <stdbool.h>                // for bool
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>         // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>        // for FSP__MISC__ATTRIBUTES_H, NO_RETURN
+#include <misc/macros.h>            // START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <debug/abort.h>            // for tegra_abort, FSP__DEBUG__ABORT_H	// IWYU pragma: keep
+#include <debug/assert.h>           // for FSP__DEBUG__ASSERT_H, assert_hook
+#include <debug/sections-assert.h>  // Immune from CT_ASSERT protection
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ABORT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ASSERT_H, "Header file missing or invalid.")
+
+/**
+ * assert_hook()        - default assert hook function
+ *
+ * @filename:           pointer to a string that contains the filename
+ *                      where the assert occurred.
+ * @linenum:            integer representing the line number in @filename
+ *                      where the assert occurred
+ *
+ * This function is a weakly bound function that serves as the default
+ * implementation of the assert hook if an application doesn't define
+ * its own version.
+ *
+ * Return Value:
+ *      none
+ */
+SECTION_ASSERT_ERR_TEXT WEAK void
+assert_hook(const char * const filename,
+            const uint32_t linenum)
+{
+}
+
+/*
+ * Split out for easier debugging.  It should not be  called other than
+ * from assert().  Having it not be static means that it won't get
+ * inlined.
+ */
+void asserted(const char * const filename,
+              const uint32_t linenum)   NO_RETURN;
+
+/**
+ * asserted()           - log the fact that an assert fired
+ *
+ * @filename:           pointer to a string that represents the name of
+ *                      the file where the assert failed.
+ * @linenum:            integer that represents the line number within
+ *                      @filename where the assert failed.
+ *
+ * This function is called by assert() when the assertion check
+ * fails.
+ *
+ * It is split out as a separate function for ease of setting a breakpoint
+ * in the debugger in order to more easily catch assertion failures.
+ *
+ * Return Values:
+ *      This function never returns
+ */
+SECTION_ASSERT_ERR_TEXT void
+asserted(const char * const filename,
+         const uint32_t linenum)
+{
+    assert_hook(filename, linenum);
+    tegra_abort(ABORT_ASSERT, 0U);
+}
+
+/**
+ * assert()             - check to see if an assertion has failed
+ *
+ * @assertion:          A boolean that is the result of an assertion check.
+ *                      If true, the assertion passed and this function will
+ *                      just return.  If false, the assertion failed and this
+ *                      function will log the assertion failure and abort.
+ * @filename:           A pointer to a string that represents the name of
+ *                      the file with the assertion check.
+ * @linenum:            The binary value of the line number within @filename
+ *                      of the assertion check.
+ *
+ * This function implements an assertion check that can be placed in various
+ * places in the code to check for impossible or fatal conditions.  It is
+ * intended that code desiring assertion checks should not call this function
+ * directly but instead use a macro that wrappers the call and the generation
+ * of the appropriate pointers (see ASSERT in debug/assert.h
+ * how this is done).
+ *
+ * Return Values:
+ *      none
+ */
+SECTION_ASSERT_TEXT void
+fsp_assert(const bool assertion,
+       const char * const filename,
+       const uint32_t linenum)
+{
+    if (!assertion) {
+        asserted(filename, linenum);
+    }
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/datasizes.c b/spe-freertos-bsp/fsp/source/drivers/debug/datasizes.c
new file mode 100644
index 0000000..7dd3d01
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/datasizes.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2014-2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+#include <limits.h>
+
+/* Early FSP headers */
+#include <misc/macros.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+
+#pragma message "content of SIZE_MAX: " STR(SIZE_MAX)
+#pragma message "content of INT_MAX: " STR(INT_MAX)
+#pragma message "content of INT32_MAX: " STR(INT32_MAX)
+#pragma message "content of UINT_MAX: " STR(UINT_MAX)
+#pragma message "content of UINT32_MAX: " STR(UINT32_MAX)
+#pragma message "content of LONG_MAX: " STR(LONG_MAX)
+#pragma message "content of size_t: " STR(__SIZE_TYPE__)
+#pragma message "content of sizeof(uint32_t): " STR(sizeof(uint32_t))
+#pragma message "content of sizeof(unsigned long): " STR(sizeof(unsigned long))
+#pragma message "content of sizeof(void *()): " STR(sizeof(void *()))
+#pragma message "content of __LONG_MAX__: " STR(__LONG_MAX__)
+#pragma message "content of UINTPTR_MAX: " STR(UINTPTR_MAX)
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/debug-fmt.c b/spe-freertos-bsp/fsp/source/drivers/debug/debug-fmt.c
new file mode 100644
index 0000000..a9da4a0
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/debug-fmt.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>               // for bool, false, true
+#include <stdint.h>                // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>        // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>           // for ARRAY_SIZE
+
+/* Module-specific FSP headers */
+#include <debug/debug-fmt.h>       // for FSP__DEBUG__DEBUG_FMT_H, dbg_putdec
+#include <debug/debug-uart.h>      // for dbg_putc, dbg_puts, FSP__DEBUG__DE...
+#include <debug/sections-debug.h>  // for SECTION_DEBUG_TEXT, SECTION_DEBUG_...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__DEBUG_FMT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__DEBUG_UART_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+SECTION_DEBUG_TEXT static char
+nibble_to_hex(uint32_t n)
+{
+    if (n < 10)
+        return '0' + n;
+    return 'a' + n - 10;
+}
+
+SECTION_DEBUG_TEXT void
+dbg_puthex8(uint32_t n)
+{
+    dbg_puts("0x");
+    dbg_putc(nibble_to_hex((n >> 28) & 0xf));
+    dbg_putc(nibble_to_hex((n >> 24) & 0xf));
+    dbg_putc(nibble_to_hex((n >> 20) & 0xf));
+    dbg_putc(nibble_to_hex((n >> 16) & 0xf));
+    dbg_putc(nibble_to_hex((n >> 12) & 0xf));
+    dbg_putc(nibble_to_hex((n >>  8) & 0xf));
+    dbg_putc(nibble_to_hex((n >>  4) & 0xf));
+    dbg_putc(nibble_to_hex( n        & 0xf));
+}
+
+/* This lookup table avoids the integer division (div /= 10) */
+SECTION_DEBUG_DATA
+static uint32_t divisors[] =
+{
+    1U,
+    10U,
+    100U,
+    1000U,
+    10000U,
+    100000U,
+    1000000U,
+    10000000U,
+    100000000U,
+    1000000000U
+};
+
+SECTION_DEBUG_TEXT void
+dbg_putdec(uint32_t n)
+{
+    int32_t i;
+    bool keep_print = false;
+    uint32_t div;
+    uint32_t res;
+
+    if (n == 0) {
+        dbg_putc('0');
+        return;
+    }
+
+    for (i = ARRAY_SIZE(divisors) - 1; i >= 0; i--) {
+        div = divisors[i];
+        if (n >= div) {
+            keep_print = true;
+            res = n / div;
+            dbg_putc(res + '0');
+            n -= res * div;
+        } else if (keep_print) {
+            dbg_putc('0');
+        }
+    }
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/debug-print.c b/spe-freertos-bsp/fsp/source/drivers/debug/debug-print.c
new file mode 100644
index 0000000..85e7250
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/debug-print.c
@@ -0,0 +1,1132 @@
+/*
+ * Copyright (c) 2014-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <ctype.h>                      // for isdigit
+#include <stdarg.h>                     // for va_arg, va_list, va_end, va_s...
+#include <stdbool.h>                    // for bool, true, false
+#include <stdint.h>                     // for uint32_t, int32_t, uint64_t
+#include <string.h>                     // for size_t, NULL, memset, memcpy
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/armv7-regs.h>             // for disable_interrupts, restore_i...
+#include <irq/safe-irqs.h>
+#include <misc/bitops.h>                // for BIT, FSP__MISC__BITOPS_H
+#include <misc/macros.h>                // for ARRAY_SIZE
+
+/* Module-specific FSP headers */
+#include <debug/assert.h>               // for ASSERT, FSP__DEBUG__ASSERT_H
+#include <debug/debug-print.h>          // for dbg_printf, dbg_snprintf, dbg...
+#include <debug/debug-uart.h>           // for dbg_puts, FSP__DEBUG__DEBUG_U...
+#include <debug/sections-debug.h>       // Immune from CT_ASSERT protection
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__CPU__ARMV7_REGS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ABORT_SYS_CODES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ASSERT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__DEBUG_UART_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+#define DBG_PRINT_BUFF_LEN              160
+
+typedef uint32_t        format_flags_t;
+
+#define DBG_FMT_FL_ALTERNATE            ((format_flags_t)BIT(0))
+#define DBG_FMT_FL_ZERO_PAD             ((format_flags_t)BIT(1))
+#define DBG_FMT_FL_LEFT_ADJUST          ((format_flags_t)BIT(2))
+#define DBG_FMT_FL_BLANK_POSITIVE       ((format_flags_t)BIT(3))
+#define DBG_FMT_FL_ALWAYS_SIGN          ((format_flags_t)BIT(4))
+#define DBG_FMT_FL_LENGTH_CHAR          ((format_flags_t)BIT(5))
+#define DBG_FMT_FL_LENGTH_SHORT         ((format_flags_t)BIT(6))
+#define DBG_FMT_FL_LENGTH_LONG          ((format_flags_t)BIT(7))
+#define DBG_FMT_FL_LENGTH_LONG_LONG     ((format_flags_t)BIT(8))
+
+#define DBG_FMT_FL_LENGTH_MASK          (DBG_FMT_FL_LENGTH_CHAR                 \
+                                         | DBG_FMT_FL_LENGTH_SHORT              \
+                                         | DBG_FMT_FL_LENGTH_LONG               \
+                                         | DBG_FMT_FL_LENGTH_LONG_LONG)
+
+
+typedef union {
+    int64_t             sint64;
+    uint64_t            uint64;
+    int32_t             sint32;
+    uint32_t            uint32;
+    int16_t             sint16;
+    uint16_t            uint16;
+    int8_t              sint8;
+    uint8_t             uint8;
+    char                ch;
+    char                *string;
+} format_value_t;
+
+/* This lookup table avoids the integer division (div /= 10) */
+static const uint32_t divisors[]        SECTION_DEBUG_RODATA =
+{
+    1000000000U,
+    100000000U,
+    10000000U,
+    1000000U,
+    100000U,
+    10000U,
+    1000U,
+    100U,
+    10U,
+    1U,
+};
+
+#define NUM_DECIMAL_DIGITS      (ARRAY_SIZE(divisors))
+#define DECIMAL_BUFF_LEN        (NUM_DECIMAL_DIGITS + 2U)
+
+#define NUM_OCTAL_DIGITS        11U
+#define OCTAL_BUFF_LEN          (NUM_OCTAL_DIGITS + 2U)
+
+static const char       upper_hex[]     SECTION_DEBUG_RODATA = "0123456789ABCDEF";
+static const char       lower_hex[]     SECTION_DEBUG_RODATA = "0123456789abcdef";
+
+#define NUM_HEX_NIBBLES         (sizeof(uint32_t) * 2U)
+#define HEX_BUFF_LEN            (NUM_HEX_NIBBLES + 3U)
+
+SECTION_DEBUG_TEXT static size_t
+dbg_format_copy_string(char *strp,
+                       char *buffp,
+                       size_t limit,
+                       size_t field_width,
+                       bool left_adjust)
+{
+    size_t      len;
+    uint32_t    offset          = 0;
+    size_t      width           = field_width;
+
+    ASSERT(strp != NULL);
+    ASSERT(buffp != NULL);
+
+    if (width > limit) {
+        width = limit;
+    }
+
+    len = strlen(strp);
+    if (len > limit) {
+        len = limit;
+    }
+
+    if (width > len) {
+        memset(buffp, ' ', width);
+    } else {
+        width = len;
+    }
+
+    if (left_adjust) {
+        offset = width - len;
+    }
+
+    memcpy(&buffp[offset], strp, len);
+
+    return width;
+}
+
+SECTION_DEBUG_TEXT static void
+int32_to_decimal_str(int32_t value,
+                     size_t n_digits,
+                     size_t field_width,
+                     char *buffp,
+                     format_flags_t flags)
+{
+    int32_t             val;
+    uint32_t            i;
+    uint32_t            digit;
+    size_t              width           = field_width;
+    bool                emitted         = false;
+    bool                negative;
+    bool                zero_pad;
+    char                *bp             = buffp;
+    const uint32_t      *divs;
+
+    ASSERT(buffp != NULL);
+
+    /* Handle n_digits == 0 */
+    if (n_digits == 0UL) {
+        *bp = ' ';
+        return;
+    }
+
+    negative = value < 0;
+    val = negative ? -value : value;
+
+    if (width > n_digits) {
+        width = n_digits;
+    }
+
+    zero_pad = (flags & DBG_FMT_FL_ZERO_PAD) != 0U;
+
+    if ((flags & DBG_FMT_FL_BLANK_POSITIVE) != 0U) {
+        *bp++ = negative ? '-' : ' ';
+    }
+
+    if ((flags & DBG_FMT_FL_ALWAYS_SIGN) != 0U) {
+        *bp++ = negative ? '-' : '+';
+    }
+
+    if (((flags & (DBG_FMT_FL_BLANK_POSITIVE | DBG_FMT_FL_ALWAYS_SIGN)) == 0U)
+        && negative) {
+        *bp++ = '-';
+    }
+
+    divs = &divisors[NUM_DECIMAL_DIGITS - n_digits];
+
+    for (i = 0U; i < n_digits; i += 1U) {
+        digit = val / divs[i];
+        val %= divs[i];
+
+        if (zero_pad
+            && (i >= (n_digits - width))) {
+            emitted = true;
+        }
+
+        if ((digit != 0U)
+            || emitted) {
+            emitted = true;
+            *bp++ = '0' + digit;
+        }
+    }
+
+    /*
+     * Handle the case where the value is 0 and there's
+     * no zero pad.
+     */
+    if (!emitted) {
+        *bp = '0';
+    }
+}
+
+SECTION_DEBUG_TEXT static void
+uint32_to_decimal_str(uint32_t value,
+                      size_t n_digits,
+                      size_t field_width,
+                      char *buffp,
+                      bool zero_pad)
+{
+    uint32_t            i;
+    uint32_t            digit;
+    size_t              width           = field_width;
+    uint32_t            val             = value;
+    bool                emitted         = false;
+    char                *bp             = buffp;
+    const uint32_t      *divs;
+
+    ASSERT(buffp != NULL);
+
+    /* Handle n_digits == 0 */
+    if (n_digits == 0UL) {
+        *bp = ' ';
+        return;
+    }
+
+    if (width > n_digits) {
+        width = n_digits;
+    }
+
+    divs = &divisors[NUM_DECIMAL_DIGITS - n_digits];
+
+    for (i = 0U; i < n_digits; i += 1U) {
+        digit = val / divs[i];
+        val %= divs[i];
+
+        if (zero_pad
+            && (i >= (n_digits - width))) {
+            emitted = true;
+        }
+
+        if ((digit != 0U)
+            || emitted) {
+            emitted = true;
+            *bp++ = '0' + digit;
+        }
+    }
+
+    /*
+     * Handle the case where the value is 0 and there's
+     * no zero pad.
+     */
+    if (!emitted) {
+        *bp = '0';
+    }
+}
+
+SECTION_DEBUG_TEXT static void
+uint32_to_octal_str(uint32_t value,
+                    size_t n_digits,
+                    size_t field_width,
+                    char *buffp,
+                    bool zero_pad)
+{
+    uint32_t    i;
+    uint32_t    digit;
+    size_t      width           = field_width;
+    char        *bp             = buffp;
+    bool        emitted         = false;
+
+    ASSERT(buffp != NULL);
+
+    /* Handle n_digits == 0 */
+    if (n_digits == 0UL) {
+        *bp = ' ';
+        return;
+    }
+
+    if (width > n_digits) {
+        width = n_digits;
+    }
+
+    for (i = 0U; i < n_digits; i += 1U) {
+        digit = (value >> (3U * (n_digits - 1U - i))) & 0x07U;
+
+        if (zero_pad
+            && (i >= (n_digits - width))) {
+            emitted = true;
+        }
+
+        if ((digit != 0U)
+            || emitted) {
+            emitted = true;
+            *bp++ = '0' + digit;
+        }
+    }
+
+    /*
+     * Handle the case where the value is 0 and there's
+     * no zero pad.
+     */
+    if (!emitted) {
+        *bp = '0';
+    }
+}
+
+SECTION_DEBUG_TEXT static void
+uint32_to_hex_str(uint32_t value,
+                  size_t n_digits,
+                  size_t field_width,
+                  char *buffp,
+                  const char *hex_chars,
+                  bool zero_pad)
+{
+    uint32_t    i;
+    uint32_t    nibble;
+    size_t      width           = field_width;
+    char        *bp             = buffp;
+    bool        emitted         = false;
+
+    ASSERT(buffp != NULL);
+    ASSERT(hex_chars != NULL);
+
+    /* Handle n_digits == 0 */
+    if (n_digits == 0UL) {
+        *bp = ' ';
+        return;
+    }
+
+    if (width > n_digits) {
+        width = n_digits;
+    }
+
+    for (i = 0U; i < n_digits; i += 1U) {
+        nibble = (value >> (4U * (n_digits - 1U - i))) & 0x0FU;
+
+        if (zero_pad
+            && (i >= (n_digits - width))) {
+            emitted = true;
+        }
+
+        if ((nibble != 0U)
+            || emitted) {
+            emitted = true;
+            *bp++ = hex_chars[nibble];
+        }
+    }
+
+    /*
+     * Handle the case where the value is 0 and there's
+     * no zero pad.
+     */
+    if (!emitted) {
+        *bp = '0';
+    }
+}
+
+SECTION_DEBUG_TEXT static void
+dbg_format_signed_decimal(format_value_t value,
+                          format_flags_t flags,
+                          size_t field_width,
+                          char **bufp,
+                          size_t *countp)
+{
+    size_t      count;
+    size_t      width                   = field_width;
+    char        buff[DECIMAL_BUFF_LEN];
+    char        *bp;
+    int32_t     val                     = 0;
+    uint32_t    n_digits                = 0;
+
+    ASSERT(bufp != NULL);
+    ASSERT(*bufp != NULL);
+    ASSERT(countp != NULL);
+    ASSERT(field_width <= *countp);
+
+    bp = *bufp;
+    count = *countp;
+
+    memset(buff, 0, DECIMAL_BUFF_LEN);
+
+    if ((flags & DBG_FMT_FL_LENGTH_CHAR) != 0) {
+        val = value.uint8;
+        n_digits = 3;
+    }
+
+    if ((flags & DBG_FMT_FL_LENGTH_SHORT) != 0) {
+        val = value.uint16;
+        n_digits = 5;
+    }
+
+    if ((flags & DBG_FMT_FL_LENGTH_LONG) != 0) {
+        val = value.uint32;
+        n_digits = 10;
+    }
+
+    int32_to_decimal_str(val, n_digits, width, buff, flags);
+
+    width = dbg_format_copy_string(buff, bp, count, width,
+                                   ((flags & DBG_FMT_FL_LEFT_ADJUST) != 0));
+
+    *bufp += width;
+    *countp -= width;
+
+}
+
+SECTION_DEBUG_TEXT static void
+dbg_format_unsigned_decimal(format_value_t value,
+                            format_flags_t flags,
+                            size_t field_width,
+                            char **bufp,
+                            size_t *countp)
+{
+    size_t      count;
+    size_t      width                   = field_width;
+    char        buff[DECIMAL_BUFF_LEN];
+    char        *bp;
+    uint32_t    val                     = 0;
+    uint32_t    n_digits                = 0;
+
+    ASSERT(bufp != NULL);
+    ASSERT(*bufp != NULL);
+    ASSERT(countp != NULL);
+    ASSERT(field_width <= *countp);
+
+    bp = *bufp;
+    count = *countp;
+
+    memset(buff, 0, DECIMAL_BUFF_LEN);
+
+    if ((flags & DBG_FMT_FL_LENGTH_CHAR) != 0) {
+        val = value.uint8;
+        n_digits = 3;
+    }
+
+    if ((flags & DBG_FMT_FL_LENGTH_SHORT) != 0) {
+        val = value.uint16;
+        n_digits = 5;
+    }
+
+    if ((flags & DBG_FMT_FL_LENGTH_LONG) != 0) {
+        val = value.uint32;
+        n_digits = 10;
+    }
+
+    uint32_to_decimal_str(val, n_digits, width, buff,
+                          (flags & DBG_FMT_FL_ZERO_PAD) != 0);
+
+    width = dbg_format_copy_string(buff, bp, count, width,
+                                   ((flags & DBG_FMT_FL_LEFT_ADJUST) != 0));
+
+    *bufp += width;
+    *countp -= width;
+}
+
+SECTION_DEBUG_TEXT static void
+dbg_format_octal(format_value_t value,
+                 format_flags_t flags,
+                 size_t field_width,
+                 char **bufp,
+                 size_t *countp)
+{
+    size_t      count;
+    size_t      width                   = field_width;
+    char        buff[OCTAL_BUFF_LEN];
+    char        *bp;
+    char        *sp;
+    uint32_t    val                     = 0;
+    uint32_t    n_digits                = 0;
+
+    ASSERT(bufp != NULL);
+    ASSERT(*bufp != NULL);
+    ASSERT(countp != NULL);
+    ASSERT(field_width <= *countp);
+
+    bp = *bufp;
+    count = *countp;
+
+    memset(buff, 0, OCTAL_BUFF_LEN);
+
+    if ((flags & DBG_FMT_FL_ALTERNATE) != 0) {
+        buff[0] = '0';
+        sp = &buff[1];
+    } else {
+        sp = &buff[0];
+    }
+
+    if ((flags & DBG_FMT_FL_LENGTH_CHAR) != 0) {
+        val = value.uint8;
+        n_digits = 3;
+    }
+
+    if ((flags & DBG_FMT_FL_LENGTH_SHORT) != 0) {
+        val = value.uint16;
+        n_digits = 6;
+    }
+
+    if ((flags & DBG_FMT_FL_LENGTH_LONG) != 0) {
+        val = value.uint32;
+        n_digits = 11;
+    }
+
+    uint32_to_octal_str(val, n_digits, width, sp,
+                        (flags & DBG_FMT_FL_ZERO_PAD) != 0);
+
+    width = dbg_format_copy_string(buff, bp, count, width,
+                                   ((flags & DBG_FMT_FL_LEFT_ADJUST) != 0));
+
+    *bufp += width;
+    *countp -= width;
+}
+
+SECTION_DEBUG_TEXT static void
+dbg_format_lower_hex(format_value_t value,
+                     format_flags_t flags,
+                     size_t field_width,
+                     char **bufp,
+                     size_t *countp)
+{
+    char        *bp;
+    size_t      count;
+    size_t      width                   = field_width;
+    char        buff[HEX_BUFF_LEN];
+    char        *sp;
+    uint32_t    val                     = 0;
+    uint32_t    n_digits                = 0;
+
+    ASSERT(bufp != NULL);
+    ASSERT(*bufp != NULL);
+    ASSERT(countp != NULL);
+    ASSERT(field_width <= *countp);
+
+    bp = *bufp;
+    count = *countp;
+
+    memset(buff, 0, HEX_BUFF_LEN);
+
+    if ((flags & DBG_FMT_FL_ALTERNATE) != 0) {
+        buff[0] = '0';
+        buff[1] = 'x';
+        sp = &buff[2];
+    } else {
+        sp = &buff[0];
+    }
+
+    if ((flags & DBG_FMT_FL_LENGTH_CHAR) != 0) {
+        val = value.uint8;
+        n_digits = sizeof(uint8_t) * 2U;
+    }
+
+    if ((flags & DBG_FMT_FL_LENGTH_SHORT) != 0) {
+        val = value.uint16;
+        n_digits = sizeof(uint16_t) * 2U;
+    }
+
+    if ((flags & DBG_FMT_FL_LENGTH_LONG) != 0) {
+        val = value.uint32;
+        n_digits = sizeof(uint32_t) * 2U;
+    }
+
+    uint32_to_hex_str(val, n_digits, width, sp, lower_hex,
+                      (flags & DBG_FMT_FL_ZERO_PAD) != 0);
+
+    width = dbg_format_copy_string(buff, bp, count, width,
+                                   ((flags & DBG_FMT_FL_LEFT_ADJUST) != 0));
+
+    *bufp += width;
+    *countp -= width;
+}
+
+SECTION_DEBUG_TEXT static void
+dbg_format_upper_hex(format_value_t value,
+                      format_flags_t flags,
+                      size_t field_width,
+                      char **bufp,
+                      size_t *countp)
+{
+    char        *bp;
+    size_t      count;
+    size_t      width                   = field_width;
+    char        buff[HEX_BUFF_LEN];
+    char        *sp;
+    uint32_t    val                     = 0;
+    uint32_t    n_digits                = 0;
+
+    ASSERT(bufp != NULL);
+    ASSERT(*bufp != NULL);
+    ASSERT(countp != NULL);
+    ASSERT(field_width <= *countp);
+
+    bp = *bufp;
+    count = *countp;
+
+    memset(buff, 0, HEX_BUFF_LEN);
+
+    if ((flags & DBG_FMT_FL_ALTERNATE) != 0) {
+        buff[0] = '0';
+        buff[1] = 'X';
+        sp = &buff[2];
+    } else {
+        sp = &buff[0];
+    }
+
+    if ((flags & DBG_FMT_FL_LENGTH_CHAR) != 0) {
+        val = value.uint8;
+        n_digits = sizeof(uint8_t) * 2U;
+    }
+
+    if ((flags & DBG_FMT_FL_LENGTH_SHORT) != 0) {
+        val = value.uint16;
+        n_digits = sizeof(uint16_t) * 2U;
+    }
+
+    if ((flags & DBG_FMT_FL_LENGTH_LONG) != 0) {
+        val = value.uint32;
+        n_digits = sizeof(uint32_t) * 2U;
+    }
+
+    uint32_to_hex_str(val, n_digits, width, sp, upper_hex,
+                      (flags & DBG_FMT_FL_ZERO_PAD) != 0);
+
+    width = dbg_format_copy_string(buff, bp, count, width,
+                                   ((flags & DBG_FMT_FL_LEFT_ADJUST) != 0));
+
+    *bufp += width;
+    *countp -= width;
+}
+
+SECTION_DEBUG_TEXT static void
+dbg_format_char(char value,
+                format_flags_t flags,
+                size_t field_width,
+                char **bufp,
+                size_t *countp)
+{
+    char        *bp;
+    size_t      width           = field_width;
+
+    ASSERT(bufp != NULL);
+    ASSERT(*bufp != NULL);
+    ASSERT(countp != NULL);
+    ASSERT(field_width <= *countp);
+
+    bp = *bufp;
+
+    if (width > 0) {
+        memset(bp, ' ', width);
+    } else {
+        width = 1;
+    }
+
+    if ((flags & DBG_FMT_FL_LEFT_ADJUST) != 0) {
+        bp[0] = value;
+    } else {
+        bp[width - 1] = value;
+    }
+
+    *bufp += width;
+    *countp -= width;
+}
+
+static void
+dbg_format_string(char *strp,
+                  format_flags_t flags,
+                  size_t field_width,
+                  char **bufp,
+                  size_t *countp)
+{
+    char        *bp;
+    char        *sp;
+    size_t      count;
+    size_t      width           = field_width;
+
+    ASSERT(bufp != NULL);
+    ASSERT(*bufp != NULL);
+    ASSERT(countp != NULL);
+    ASSERT(field_width <= *countp);
+
+    bp = *bufp;
+    count = *countp;
+
+    if (strp == NULL) {
+        sp = (char *)"(NULL)";
+    } else {
+        sp = strp;
+    }
+
+    width = dbg_format_copy_string(sp, bp, count, width,
+                                   ((flags & DBG_FMT_FL_LEFT_ADJUST) != 0));
+
+    *bufp += width;
+    *countp -= width;
+}
+
+
+
+SECTION_DEBUG_TEXT static size_t
+dbg_get_num(char **bufp)
+{
+    size_t      value           = 0;
+    char        *bp;
+
+    ASSERT(bufp != NULL);
+    ASSERT(*bufp != NULL);
+
+    bp = *bufp;
+
+    INLINE_RFD(MISRA, DEVIATE, Directive_4_6, "Approval: Bug 200543266, DR: SWE-FSP-003-SWSADR.docx");
+    while ((*bp != '\0') && (isdigit((int)*bp) != 0)) {
+        value *= 10;
+        value += *bp - '0';
+        bp += 1;
+    }
+
+    *bufp = bp;
+
+    return value;
+}
+
+SECTION_DEBUG_TEXT static format_flags_t
+dbg_process_modifiers(char **fmtp,
+                      size_t count,
+                      size_t *field_widthp)
+{
+    char                *fp;
+    format_flags_t      flags           = 0;
+    size_t              field_width     = 0;
+    bool                find_flags      = true;
+
+    ASSERT(fmtp != NULL);
+    ASSERT(*fmtp != NULL);
+    ASSERT(field_widthp != NULL);
+
+    fp = *fmtp;
+
+    if (count == 0) {
+        goto out;
+    }
+
+    /*
+     * Get the flag characters
+     */
+    while (find_flags) {
+        switch (*fp) {
+        case '#':
+            flags |= DBG_FMT_FL_ALTERNATE;
+            fp += 1;
+            break;
+
+        case '0':
+            flags |= DBG_FMT_FL_ZERO_PAD;
+            fp += 1;
+            break;
+
+        case '-':
+            flags |= DBG_FMT_FL_LEFT_ADJUST;
+            fp += 1;
+            break;
+
+        case ' ':
+            flags |= DBG_FMT_FL_BLANK_POSITIVE;
+            fp += 1;
+            break;
+
+        case '+':
+            flags |= DBG_FMT_FL_ALWAYS_SIGN;
+            fp += 1;
+            break;
+
+        default:
+            find_flags = false;
+            break;
+        }
+    }
+
+    if (*fp == '\0') {
+        goto out;
+    }
+
+    /*
+     * Get the field width if there is one
+     */
+    field_width = dbg_get_num(&fp);
+    if (field_width > count) {
+        field_width = count;
+    }
+
+    if (*fp == '\0') {
+        goto out;
+    }
+
+    /*
+     * Get a length modifier if there is one
+     */
+    switch (*fp) {
+    case 'h':
+        fp += 1;
+        if (*fp == 'h') {
+            flags |= DBG_FMT_FL_LENGTH_CHAR;
+            fp += 1;
+        } else {
+            flags |= DBG_FMT_FL_LENGTH_SHORT;
+        }
+        break;
+
+    case 'l':
+        fp += 1;
+        if (*fp == 'l') {
+            flags |= DBG_FMT_FL_LENGTH_LONG_LONG;
+            fp += 1;
+        } else {
+            flags |= DBG_FMT_FL_LENGTH_LONG;
+        }
+        break;
+
+    default:
+        break;
+    }
+
+    /*
+     * Clean up the flags
+     */
+    if ((flags & DBG_FMT_FL_LEFT_ADJUST) != 0) {
+        flags &= ~DBG_FMT_FL_ZERO_PAD;
+    }
+
+    if ((flags & DBG_FMT_FL_ALWAYS_SIGN) != 0) {
+        flags &= ~DBG_FMT_FL_BLANK_POSITIVE;
+    }
+
+    if ((flags & DBG_FMT_FL_LENGTH_MASK) == 0U) {
+        flags |= DBG_FMT_FL_LENGTH_LONG;
+    }
+
+  out:
+    *fmtp = fp;
+    *field_widthp = field_width;
+
+    return flags;
+}
+
+SECTION_DEBUG_TEXT int32_t
+dbg_vsnprintf(char *buff,
+              size_t size,
+              const char *format,
+              va_list ap)
+{
+    size_t              count           = size - 1;
+    char                *bp             = buff;
+    char                *fp             = (char *)format;
+    format_flags_t      flags           = 0;
+    size_t              field_width;
+    format_value_t      val;
+
+    ASSERT(buff != NULL);
+    ASSERT(format != NULL);
+
+    memset(bp, 0, size);
+
+    while ((*fp != '\0')
+           && (count > 0)) {
+        switch (*fp) {
+        case '%':
+            fp += 1;
+            if (*fp == '%') {
+                *bp++ = *fp++;
+                count -= 1;
+            } else {
+                flags = dbg_process_modifiers(&fp, count, &field_width);
+
+                /*
+                 * Get conversion
+                 */
+                switch (*fp) {
+                case 'd':
+                case 'i':
+                    if ((flags & DBG_FMT_FL_LENGTH_LONG) != 0) {
+                        val.sint32 = va_arg(ap, int32_t);
+                    }
+
+                    if ((flags & DBG_FMT_FL_LENGTH_CHAR) != 0U) {
+                        val.sint8 = va_arg(ap, int32_t);
+                    }
+
+                    if ((flags & DBG_FMT_FL_LENGTH_SHORT) != 0U) {
+                        val.sint16 = va_arg(ap, int32_t);
+                    }
+
+                    if ((flags & DBG_FMT_FL_LENGTH_LONG_LONG) != 0U) {
+                        val.sint64 = va_arg(ap, int64_t);
+                    }
+
+                    dbg_format_signed_decimal(val, flags, field_width,
+                                              &bp, &count);
+                    fp += 1;
+                    break;
+
+                case 'o':
+                    if ((flags & DBG_FMT_FL_LENGTH_LONG) != 0) {
+                        val.uint32 = va_arg(ap, uint32_t);
+                    }
+
+                    if ((flags & DBG_FMT_FL_LENGTH_CHAR) != 0U) {
+                        val.uint8 = va_arg(ap, uint32_t);
+                    }
+
+                    if ((flags & DBG_FMT_FL_LENGTH_SHORT) != 0U) {
+                        val.uint16 = va_arg(ap, uint32_t);
+                    }
+
+                    if ((flags & DBG_FMT_FL_LENGTH_LONG_LONG) != 0U) {
+                        val.uint64 = va_arg(ap, uint64_t);
+                    }
+
+                    dbg_format_octal(val, flags, field_width, &bp, &count);
+                    fp += 1;
+                    break;
+
+                case 'u':
+                    if ((flags & DBG_FMT_FL_LENGTH_LONG) != 0) {
+                        val.uint32 = va_arg(ap, uint32_t);
+                    }
+
+                    if ((flags & DBG_FMT_FL_LENGTH_CHAR) != 0U) {
+                        val.uint8 = va_arg(ap, uint32_t);
+                    }
+
+                    if ((flags & DBG_FMT_FL_LENGTH_SHORT) != 0U) {
+                        val.uint16 = va_arg(ap, uint32_t);
+                    }
+
+                    if ((flags & DBG_FMT_FL_LENGTH_LONG_LONG) != 0U) {
+                        val.uint64 = va_arg(ap, uint64_t);
+                    }
+
+                    dbg_format_unsigned_decimal(val, flags, field_width,
+                                                &bp, &count);
+                    fp += 1;
+                    break;
+
+                case 'x':
+                    if ((flags & DBG_FMT_FL_LENGTH_LONG) != 0) {
+                        val.uint32 = va_arg(ap, uint32_t);
+                    }
+
+                    if ((flags & DBG_FMT_FL_LENGTH_CHAR) != 0U) {
+                        val.uint8 = va_arg(ap, uint32_t);
+                    }
+
+                    if ((flags & DBG_FMT_FL_LENGTH_SHORT) != 0U) {
+                        val.uint16 = va_arg(ap, uint32_t);
+                    }
+
+                    if ((flags & DBG_FMT_FL_LENGTH_LONG_LONG) != 0U) {
+                        val.uint64 = va_arg(ap, uint64_t);
+                    }
+
+                    dbg_format_lower_hex(val, flags, field_width, &bp, &count);
+                    fp += 1;
+                    break;
+
+                case 'X':
+                    if ((flags & DBG_FMT_FL_LENGTH_LONG) != 0) {
+                        val.uint32 = va_arg(ap, uint32_t);
+                    }
+
+                    if ((flags & DBG_FMT_FL_LENGTH_CHAR) != 0U) {
+                        val.uint8 = va_arg(ap, uint32_t);
+                    }
+
+                    if ((flags & DBG_FMT_FL_LENGTH_SHORT) != 0U) {
+                        val.uint16 = va_arg(ap, uint32_t);
+                    }
+
+                    if ((flags & DBG_FMT_FL_LENGTH_LONG_LONG) != 0U) {
+                        val.uint64 = va_arg(ap, uint64_t);
+                    }
+
+                    dbg_format_upper_hex(val, flags, field_width, &bp, &count);
+                    fp += 1;
+                    break;
+
+                case 'p':
+                    val.uint32 = va_arg(ap, uint32_t);
+                    dbg_format_lower_hex(val, flags, field_width, &bp, &count);
+                    fp += 1;
+                    break;
+
+                case 'c':
+                    val.ch = va_arg(ap, int32_t);
+                    dbg_format_char(val.ch, flags, field_width, &bp, &count);
+                    fp += 1;
+                    break;
+
+                case 's':
+                    val.string = va_arg(ap, char *);
+                    dbg_format_string(val.string, flags, field_width,
+                                      &bp, &count);
+                    fp += 1;
+                    break;
+
+                default:
+                    break;
+                }
+            }
+            break;
+
+        case '\n':
+            *bp++ = '\r';
+            if (count > 1) {
+                *bp++ = '\n';
+                count -= 1;
+            }
+
+            fp += 1;
+            count -= 1;
+            break;
+
+        default:
+            *bp++ = *fp++;
+        }
+    }
+
+    return bp - buff;
+}
+
+SECTION_DEBUG_TEXT int32_t
+dbg_snprintf(char *buff,
+             size_t size,
+             const char *format,
+             ...)
+{
+    int32_t     count;
+    va_list     ap;
+
+    va_start(ap, format);
+
+    count = dbg_vsnprintf(buff, size,
+                          format, ap);
+
+    va_end(ap);
+
+    return count;
+}
+
+static char             print_buffer[DBG_PRINT_BUFF_LEN]        SECTION_DEBUG_DATA;
+
+SECTION_DEBUG_TEXT int32_t
+dbg_vprintf(const char *format,
+            va_list ap)
+{
+    int32_t     count;
+
+    enter_critical();
+
+    count = dbg_vsnprintf(print_buffer, DBG_PRINT_BUFF_LEN,
+                          format, ap);
+
+    dbg_puts(print_buffer);
+
+    exit_critical();
+
+    return count;
+}
+
+
+SECTION_DEBUG_TEXT int32_t
+dbg_printf(const char *format,
+           ...)
+{
+    int32_t     count;
+    va_list     ap;
+
+    enter_critical();
+
+    va_start(ap, format);
+    count = dbg_vsnprintf(print_buffer, DBG_PRINT_BUFF_LEN,
+                          format, ap);
+
+    va_end(ap);
+
+    dbg_puts(print_buffer);
+
+    exit_critical();
+
+    return count;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/debug-uart.c b/spe-freertos-bsp/fsp/source/drivers/debug/debug-uart.c
new file mode 100644
index 0000000..67e8583
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/debug-uart.c
@@ -0,0 +1,177 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>        // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>   // for E_SUCCESS, error_t
+#include <misc/macros.h>           // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <processor/debug-hw.h>    // for DEBUG_UART, FSP__PROCESSOR__DEBUG_...
+
+/* Module-specific FSP headers */
+#include <debug/assert.h>          // for ASSERT, FSP__DEBUG__ASSERT_H
+#include <debug/debug-uart.h>      // for FSP__DEBUG__DEBUG_UART_H, dbg_flush
+#include <debug/sections-debug.h>  // Immune from CT_ASSERT protection
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__DEBUG_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ASSERT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__DEBUG_UART_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+extern const struct dbg_uart_ops dbg_standalone_uart_ops;
+extern const struct dbg_uart_ops dbg_comb_uart_ops;
+
+/**
+ *
+ * Defaults to standalone uart ops to not break the builds
+ * for existing clients. At some point, this needs to be
+ * revisited.
+ */
+static struct dbg_uart_ops *ops = NULL;
+static void *uart_ctlr = NULL;
+
+static inline struct dbg_uart_ops *c_ptr_to_nc_ptr(const struct dbg_uart_ops *input)
+{
+    union cast_c_ptr_to_nc_ptr {
+        const struct dbg_uart_ops *input;
+        struct dbg_uart_ops *output;
+    };
+    union cast_c_ptr_to_nc_ptr t;
+
+    t.input = input;
+
+    return t.output;
+}
+
+#if defined(DEBUG_COMB_UART)
+static inline void *c_tcu_ptr_to_v_ptr(const struct comb_uart_id *input)
+{
+    union cast_c_tcu_ptr_to_v_ptr {
+        const struct comb_uart_id* input;
+        void *output;
+    };
+    union cast_c_tcu_ptr_to_v_ptr t;
+
+    t.input = input;
+
+    return t.output;
+}
+#endif
+
+SECTION_DEBUG_TEXT void
+dbg_init_uart_ops(uint32_t uart_mode)
+{
+    switch (uart_mode) {
+        case UART_MODE_TCU:
+            ops = c_ptr_to_nc_ptr(&dbg_comb_uart_ops);
+#if defined(DEBUG_COMB_UART)
+            uart_ctlr = c_tcu_ptr_to_v_ptr(&DEBUG_COMB_UART);
+#endif
+            break;
+        case UART_MODE_STANDALONE:
+        default:
+            ops = c_ptr_to_nc_ptr(&dbg_standalone_uart_ops);
+            uart_ctlr = &DEBUG_UART;
+            break;
+    }
+}
+
+
+SECTION_DEBUG_TEXT void
+dbg_init(void)
+{
+    error_t rc = -1;
+
+    /* default to standalone if not registered */
+    if (ops == NULL) {
+        ops = c_ptr_to_nc_ptr(&dbg_standalone_uart_ops);
+        uart_ctlr = &DEBUG_UART;
+    }
+
+    if (ops->init != NULL) {
+        rc = ops->init(uart_ctlr);
+    }
+
+    ASSERT(rc == E_SUCCESS);
+}
+
+SECTION_DEBUG_TEXT void
+dbg_putc(char c)
+{
+    ops->putc(uart_ctlr, c);
+}
+
+SECTION_DEBUG_TEXT void
+dbg_putd(const char *d, uint32_t len)
+{
+    ops->putd(uart_ctlr, d, len);
+}
+
+SECTION_DEBUG_TEXT void
+dbg_puts(const char *s)
+{
+    ops->puts(uart_ctlr, s);
+}
+
+SECTION_DEBUG_TEXT void
+dbg_flush(void)
+{
+    ops->flush(uart_ctlr);
+}
+
+SECTION_DEBUG_TEXT bool
+dbg_tx_ready(void)
+{
+    return ops->tx_ready(uart_ctlr);
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/debug-wait.c b/spe-freertos-bsp/fsp/source/drivers/debug/debug-wait.c
new file mode 100644
index 0000000..31aff9e
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/debug-wait.c
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>        // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/barriers.h>          // for barrier_compiler, FSP__ARM__COMMON...
+#include <misc/macros.h>           // START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <debug/sections-debug.h>  // Immune from CT_ASSERT protection
+#include <debug/tegra-debug.h>     // for DEBUG_WAIT_BOOT_FL, FSP__DEBUG__TE...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__CPU__BARRIERS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__TEGRA_DEBUG_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/*
+ * This variable must be marked "volatile" since the intent is that the
+ * debugger will modify this value, so it is necessary for the generated
+ * code to always read this variable when it is polling it.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx", MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+volatile uint32_t       debug_wait_flags        SECTION_DEBUG_DATA = 0;
+
+/*
+ * This variable is used to re-initialize the tegra_debug_wait_flags variable
+ * each time that tegra_debugger_wait() is called.  This allows different
+ * calls to tegra_debugger_wait() to still wait even if a debugger reset the
+ * contents of tegra_debug_wait_flags on a previous call.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx", MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+uint32_t                debug_wait_init         SECTION_DEBUG_DATA
+                                        = DEBUG_WAIT_BOOT_FL;
+
+/**
+ * debugger_wait_bp()     - internal debugger wait
+ *
+ * @wait_flag:                  Type of wait
+ *
+ * This function will wait until a specific bit (or bits) in the variable
+ * tegra_debug_wait_flags has been cleared.
+ *
+ * This function is called when the wait is to be performed.  This allows
+ * for a debugger to set a breakpoint on this function when a wait is
+ * expected.
+ *
+ * Return Values:
+ *      none
+ */
+void
+debugger_wait_bp(const uint32_t wait_flag)
+{
+    /*
+     * Wait until the flags are cleared
+     */
+    while ((debug_wait_flags & wait_flag) != 0) {
+        barrier_compiler();
+    }
+}
+
+/**
+ * debugger_wait()              - waits for the debugger to clear a flag
+ *
+ * @wait_flag:                  flag that the debugger has to clear in order
+ *                              for the function to exit.
+ *
+ * This function will wait on a specific bit (or bits) in the variable
+ * tegra_debugger_wait_flags have been cleared.  This variable is set to
+ * the initial values on entry so that this can be called multiple times
+ * and will wait appropriately each time this function is called.
+ *
+ * Return Values:
+ *      none
+ */
+void
+debugger_wait(const uint32_t wait_flag)
+{
+    /*
+     * Set the wait variable.  When the debugger breaks in, it will
+     * clear the variable.
+     */
+    debug_wait_flags = debug_wait_init;
+
+    if ((debug_wait_flags & wait_flag) != 0) {
+        debugger_wait_bp(wait_flag);
+    }
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/debug.c b/spe-freertos-bsp/fsp/source/drivers/debug/debug.c
new file mode 100644
index 0000000..e9960cf
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/debug.c
@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2014-2021 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdarg.h>                   // for va_list, va_end, va_start
+#include <stdbool.h>                  // for true, bool, false
+#include <stdint.h>                   // for uint32_t
+#include <stdio.h>                    // for vsnprintf
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>           // for CT_ASSERT
+#include <soc-common/hw-const.h>      /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <aruart.h>                   // for UART_IER_DLAB_0_0, UART_IIR_FCR_0
+
+/* Late FSP headers */
+#include <clk/clk-tegra.h>            // for tegra_clk_enable, tegra_clk_res...
+#include <misc/macros.h>              // for ARRAY_SIZE
+#include <processor/debug-hw.h>       // for TEGRA_DBG_UART_BASE, TEGRA_DBG_...
+#include <reg-access/reg-access.h>    // for writel, readl
+#include <soc-common/clk-tegra-hw.h>  // for TEGRA_DBG_UART_CLK
+
+/* Module-specific FSP headers */
+#include <debug/debug.h>              // for dbg_3rdparty_init, dbg_flush, dbg...
+#include <debug/printf-isr.h>         // for PRINTF_ISR_BUFSIZE, printf_isr
+#include <chipid/chip-id.h>           // for tegra_platform_is_silicon
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CLK__CLK_TEGRA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__DEBUG_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__CLK_TEGRA_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__DEBUG_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__PRINTF_ISR_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#define TEGRA_DBG_UART_TX       (TEGRA_DBG_UART_BASE + UART_THR_DLAB_0_0)
+#define TEGRA_DBG_UART_LSR      (TEGRA_DBG_UART_BASE + UART_LSR_0)
+#define TEGRA_DBG_UART_LSR_THRE (UART_LSR_0_THRE_EMPTY << UART_LSR_0_THRE_SHIFT)
+#define TEGRA_DBG_UART_LSR_TMTY (UART_LSR_0_TMTY_EMPTY << UART_LSR_0_TMTY_SHIFT)
+
+#define TEGRA_DBG_UART_LCR      (TEGRA_DBG_UART_BASE + UART_LCR_0)
+#define TEGRA_DBG_UART_LCR_WD_SIZE \
+        (UART_LCR_0_WD_SIZE_WORD_LENGTH_8 << UART_LCR_0_WD_SIZE_SHIFT)
+#define TEGRA_DBG_UART_LCR_PAR \
+        (UART_LCR_0_PAR_NO_PARITY << UART_LCR_0_PAR_SHIFT)
+#define TEGRA_DBG_UART_LCR_STOP \
+        (UART_LCR_0_STOP_DISABLE << UART_LCR_0_STOP_SHIFT)
+#define TEGRA_DBG_UART_LCR_DLAB \
+        (UART_LCR_0_DLAB_ENABLE << UART_LCR_0_DLAB_SHIFT)
+
+#define TEGRA_DBG_UART_IER_DLAB_IE_RHR \
+        (UART_IER_DLAB_0_0_IE_RHR_ENABLE << UART_IER_DLAB_0_0_IE_RHR_SHIFT)
+
+#define TEGRA_DBG_UART_IIR_FCR  (TEGRA_DBG_UART_BASE + UART_IIR_FCR_0)
+#define TEGRA_DBG_UART_IIR_FCR_EN_FIFO \
+        (UART_IIR_FCR_0_FCR_EN_FIFO_ENABLE << UART_IIR_FCR_0_FCR_EN_FIFO_SHIFT)
+#define TEGRA_DBG_UART_IIR_FCR_RX_CLR \
+        (UART_IIR_FCR_0_RX_CLR_CLEAR << UART_IIR_FCR_0_RX_CLR_SHIFT)
+#define TEGRA_DBG_UART_IIR_FCR_TX_CLR \
+        (UART_IIR_FCR_0_TX_CLR_CLEAR << UART_IIR_FCR_0_TX_CLR_SHIFT)
+
+#define TEGRA_DBG_UART_THR_DLAB (TEGRA_DBG_UART_BASE + UART_THR_DLAB_0_0)
+#define TEGRA_DBG_UART_IER_DLAB (TEGRA_DBG_UART_BASE + UART_IER_DLAB_0_0)
+
+static bool inited = false;
+
+void dbg_init(void)
+{
+        uint32_t lcr = TEGRA_DBG_UART_LCR_WD_SIZE | TEGRA_DBG_UART_LCR_PAR |
+                TEGRA_DBG_UART_LCR_STOP;
+
+        /* Setup UART to 8n1 */
+#ifdef TEGRA_DBG_UART_CLK
+        if (tegra_platform_is_silicon()) {
+                tegra_clk_set_rate(TEGRA_DBG_UART_CLK, TEGRA_DBG_UART_BAUD * 16);
+                tegra_clk_enable(TEGRA_DBG_UART_CLK);
+                tegra_clk_reset_clear(TEGRA_DBG_UART_RST);
+        }
+
+        writel(lcr | TEGRA_DBG_UART_LCR_DLAB, TEGRA_DBG_UART_LCR);
+        writel(0x1, TEGRA_DBG_UART_THR_DLAB); /* Divider LSB */
+        writel(0x0, TEGRA_DBG_UART_IER_DLAB); /* Divider MSB */
+#endif
+        writel(lcr, TEGRA_DBG_UART_LCR);
+        writel(0x0, TEGRA_DBG_UART_IIR_FCR);
+        writel(TEGRA_DBG_UART_IER_DLAB_IE_RHR, TEGRA_DBG_UART_IER_DLAB);
+        writel(TEGRA_DBG_UART_IIR_FCR_EN_FIFO,TEGRA_DBG_UART_IIR_FCR);
+        writel(TEGRA_DBG_UART_IIR_FCR_EN_FIFO |
+               TEGRA_DBG_UART_IIR_FCR_RX_CLR |
+               TEGRA_DBG_UART_IIR_FCR_TX_CLR, TEGRA_DBG_UART_IIR_FCR);
+        /* WAR to clear any pending interrupts after clearing the FIFOs */
+        writel(0, TEGRA_DBG_UART_IER_DLAB);
+        writel(TEGRA_DBG_UART_IER_DLAB_IE_RHR, TEGRA_DBG_UART_IER_DLAB);
+
+        inited = true;
+}
+
+void dbg_3rdparty_init(void)
+{
+        inited = true;
+}
+
+void dbg_putc(char c)
+{
+        if (!inited)
+                return;
+
+        while (!(readl(TEGRA_DBG_UART_LSR) & TEGRA_DBG_UART_LSR_THRE))
+                ;
+        writel(c, TEGRA_DBG_UART_TX);
+}
+
+void dbg_putd(const char *d, uint32_t len)
+{
+        uint32_t i;
+        for (i = 0; i < len; i++)
+                dbg_putc(*d++);
+}
+
+void dbg_puts(const char *s)
+{
+        while (*s)
+                dbg_putc(*s++);
+}
+
+static char nibble_to_hex(uint32_t n)
+{
+        if (n < 10)
+                return '0' + n;
+        return 'a' + n - 10;
+}
+
+void dbg_puthex8(uint32_t n)
+{
+        dbg_puts("0x");
+        dbg_putc(nibble_to_hex((n >> 28) & 0xf));
+        dbg_putc(nibble_to_hex((n >> 24) & 0xf));
+        dbg_putc(nibble_to_hex((n >> 20) & 0xf));
+        dbg_putc(nibble_to_hex((n >> 16) & 0xf));
+        dbg_putc(nibble_to_hex((n >> 12) & 0xf));
+        dbg_putc(nibble_to_hex((n >>  8) & 0xf));
+        dbg_putc(nibble_to_hex((n >>  4) & 0xf));
+        dbg_putc(nibble_to_hex( n        & 0xf));
+}
+
+/* This lookup table avoids the integer division (div /= 10) */
+static uint32_t divisors[] = {1, 10, 100, 1000, 10000, 100000, 1000000,
+                                10000000, 100000000, 1000000000};
+
+void dbg_putdec(uint32_t n)
+{
+        int32_t i;
+        bool keep_print = false;
+        uint32_t div;
+        uint32_t res;
+
+        if (n == 0) {
+                dbg_putc('0');
+                return;
+        }
+
+        INLINE_RFD(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx", MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx");
+        for (i = ARRAY_SIZE(divisors) - 1; i >= 0; i--) {
+                div = divisors[i];
+                if (n >= div) {
+                        keep_print = true;
+                        res = n / div;
+                        dbg_putc(res + '0');
+                        n -= res * div;
+                } else if (keep_print) {
+                        dbg_putc('0');
+                }
+        }
+}
+
+int32_t vprintf_isr(const char *fmt, va_list ap)
+{
+        char msg[PRINTF_ISR_BUFSIZE];
+        int32_t ret;
+
+        ret = vsnprintf(msg, PRINTF_ISR_BUFSIZE, fmt, ap);
+
+        if (ret > 0)
+        {
+                ret = (ret > PRINTF_ISR_BUFSIZE) ? PRINTF_ISR_BUFSIZE : ret;
+                dbg_putd(msg, ret);
+        }
+
+        return ret;
+}
+
+int32_t printf_isr(const char *fmt, ...)
+{
+        va_list args;
+        int32_t ret;
+
+        va_start(args, fmt);
+        ret = vprintf_isr(fmt, args);
+        va_end(args);
+
+        return ret;
+}
+
+void dbg_flush(void)
+{
+        while (!(readl(TEGRA_DBG_UART_LSR) & TEGRA_DBG_UART_LSR_TMTY))
+                ;
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/module-datasizes-nosafety-config.mk b/spe-freertos-bsp/fsp/source/drivers/debug/module-datasizes-nosafety-config.mk
new file mode 100644
index 0000000..619c326
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/module-datasizes-nosafety-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-datasizes-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_DATASIZES_NOSAFETY_CONFIG        := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_DATASIZES_NOSAFETY_DEPENDS       :=
+$(foreach _,$(MODULE_DATASIZES_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+DATASIZES_DIR                            = $(FSP_COMMON_REPO)/drivers/debug
+MODULE_DATASIZES_NOSAFETY_SOURCE_DIR     = $(DATASIZES_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_DATASIZES_NOSAFETY_INCLUDES       =
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/module-datasizes-nosafety.mk b/spe-freertos-bsp/fsp/source/drivers/debug/module-datasizes-nosafety.mk
new file mode 100644
index 0000000..7a3df42
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/module-datasizes-nosafety.mk
@@ -0,0 +1,62 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-datasizes-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_DATASIZES_NOSAFETY_NAME          := DATASIZES_NOSAFETY
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_DATASIZES_NOSAFETY_DEFINED       := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_DATASIZES_NOSAFETY_DEPENDS       := DATASIZES_NOSAFETY
+$(foreach _,$(CONFIG_DATASIZES_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_DATASIZES_NOSAFETY_C_SRC          =
+MODULE_DATASIZES_NOSAFETY_C_SRC         += $(DATASIZES_DIR)/datasizes.c
+
+#
+# Assembly source
+MODULE_DATASIZES_NOSAFETY_ASM_SRC        =
+
+#
+# Special C Flags
+MODULE_DATASIZES_NOSAFETY_C_FLAGS        =
+
+#
+# Special ASM Flags
+MODULE_DATASIZES_NOSAFETY_ASM_FLAGS      =
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/module-debug-nosafety-config.mk b/spe-freertos-bsp/fsp/source/drivers/debug/module-debug-nosafety-config.mk
new file mode 100644
index 0000000..e7ca230
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/module-debug-nosafety-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-debug-nosafety-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_DEBUG_NOSAFETY_CONFIG            := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_DEBUG_NOSAFETY_DEPENDS           := SOC CLUSTER CPL OSA FSP_COMMON
+$(foreach _,$(MODULE_DEBUG_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+DEBUG_DIR                                = $(FSP_COMMON_REPO)/drivers/debug
+MODULE_DEBUG_NOSAFETY_SOURCE_DIR         = $(DEBUG_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_DEBUG_NOSAFETY_INCLUDES           =
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/module-debug-nosafety.mk b/spe-freertos-bsp/fsp/source/drivers/debug/module-debug-nosafety.mk
new file mode 100644
index 0000000..e46b1ef
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/module-debug-nosafety.mk
@@ -0,0 +1,64 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-debug-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_DEBUG_NOSAFETY_NAME              := DEBUG_NOSAFETY
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_DEBUG_NOSAFETY_DEFINED           := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_DEBUG_NOSAFETY_DEPENDS           := DEBUG_NOSAFETY SOC CPL OSA
+$(foreach _,$(CONFIG_DEBUG_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_DEBUG_NOSAFETY_C_SRC              =
+MODULE_DEBUG_NOSAFETY_C_SRC             += $(DEBUG_DIR)/abort.c
+MODULE_DEBUG_NOSAFETY_C_SRC             += $(DEBUG_DIR)/assert.c
+MODULE_DEBUG_NOSAFETY_C_SRC             += $(DEBUG_DIR)/debug-wait.c
+
+#
+# Assembly source
+MODULE_DEBUG_NOSAFETY_ASM_SRC            =
+
+#
+# Special C Flags
+MODULE_DEBUG_NOSAFETY_C_FLAGS            =
+
+#
+# Special ASM Flags
+MODULE_DEBUG_NOSAFETY_ASM_FLAGS          =
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/module-lib-print-nosafety-config.mk b/spe-freertos-bsp/fsp/source/drivers/debug/module-lib-print-nosafety-config.mk
new file mode 100644
index 0000000..cb659a3
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/module-lib-print-nosafety-config.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-lib-print-nosafety-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_LIB_PRINT_NOSAFETY_CONFIG        := 1
+
+#
+# Location of source code files
+LIB_PRINT_DIR                            = $(FSP_COMMON_REPO)/drivers/debug
+MODULE_LIB_PRINT_NOSAFETY_SOURCE_DIR     = $(LIB_PRINT_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_LIB_PRINT_NOSAFETY_INCLUDES       =
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/module-lib-print-nosafety.mk b/spe-freertos-bsp/fsp/source/drivers/debug/module-lib-print-nosafety.mk
new file mode 100644
index 0000000..d3198b0
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/module-lib-print-nosafety.mk
@@ -0,0 +1,64 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-lib-print-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_LIB_PRINT_NOSAFETY_NAME          := LIB_PRINT
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_LIB_PRINT_NOSAFETY_DEFINED       := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_LIB_PRINT_NOSAFETY_DEPENDS       := LIB_PRINT_NOSAFETY SOC
+$(foreach _,$(CONFIG_LIB_PRINT_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_LIB_PRINT_NOSAFETY_C_SRC          =
+MODULE_LIB_PRINT_NOSAFETY_C_SRC         += $(LIB_PRINT_DIR)/debug.c
+MODULE_LIB_PRINT_NOSAFETY_C_SRC         += $(LIB_PRINT_DIR)/print.c
+MODULE_LIB_PRINT_NOSAFETY_C_SRC         += $(LIB_PRINT_DIR)/retarget-stdio.c
+
+#
+# Assembly source
+MODULE_LIB_PRINT_NOSAFETY_ASM_SRC        =
+
+#
+# Special C Flags
+MODULE_LIB_PRINT_NOSAFETY_C_FLAGS        =
+
+#
+# Special ASM Flags
+MODULE_LIB_PRINT_NOSAFETY_ASM_FLAGS      =
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/module-standalone-print-nosafety-config.mk b/spe-freertos-bsp/fsp/source/drivers/debug/module-standalone-print-nosafety-config.mk
new file mode 100644
index 0000000..5062714
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/module-standalone-print-nosafety-config.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-standalone-print-nosafety-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_STANDALONE_PRINT_NOSAFETY_CONFIG     := 1
+
+#
+# Location of source code files
+STANDALONE_PRINT_DIR                         = $(FSP_COMMON_REPO)/drivers/debug
+MODULE_STANDALONE_PRINT_NOSAFETY_SOURCE_DIR  = $(STANDALONE_PRINT_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_STANDALONE_PRINT_NOSAFETY_INCLUDES    =
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/module-standalone-print-nosafety.mk b/spe-freertos-bsp/fsp/source/drivers/debug/module-standalone-print-nosafety.mk
new file mode 100644
index 0000000..50b6044
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/module-standalone-print-nosafety.mk
@@ -0,0 +1,64 @@
+#
+# Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-standalone-print-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_STANDALONE_PRINT_NOSAFETY_NAME       := STANDALONE_PRINT
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_STANDALONE_PRINT_NOSAFETY_DEFINED    := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_STANDALONE_PRINT_NOSAFETY_DEPENDS    := STANDALONE_PRINT_NOSAFETY
+$(foreach _,$(CONFIG_STANDALONE_PRINT_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_STANDALONE_PRINT_NOSAFETY_C_SRC       =
+MODULE_STANDALONE_PRINT_NOSAFETY_C_SRC      += $(STANDALONE_PRINT_DIR)/debug-fmt.c
+MODULE_STANDALONE_PRINT_NOSAFETY_C_SRC      += $(STANDALONE_PRINT_DIR)/debug-print.c
+MODULE_STANDALONE_PRINT_NOSAFETY_C_SRC      += $(STANDALONE_PRINT_DIR)/debug-uart.c
+
+#
+# Assembly source
+MODULE_STANDALONE_PRINT_NOSAFETY_ASM_SRC     =
+
+#
+# Special C Flags
+MODULE_STANDALONE_PRINT_NOSAFETY_C_FLAGS     =
+
+#
+# Special ASM Flags
+MODULE_STANDALONE_PRINT_NOSAFETY_ASM_FLAGS   =
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/nvriscv/module-debug-nvriscv-nosafety-config.mk b/spe-freertos-bsp/fsp/source/drivers/debug/nvriscv/module-debug-nvriscv-nosafety-config.mk
new file mode 100644
index 0000000..e36cd9f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/nvriscv/module-debug-nvriscv-nosafety-config.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-debug-nvriscv-nosafety-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_DEBUG_NVRISCV_NOSAFETY_CONFIG     := 1
+
+#
+# Location of source code files
+DEBUG_NVRISCV_DIR                         = $(FSP_COMMON_REPO)/drivers/debug/nvriscv
+MODULE_DEBUG_NVRISCV_NOSAFETY_SOURCE_DIR  = $(DEBUG_NVRISCV_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_DEBUG_NVRISCV_NOSAFETY_INCLUDES    =
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/nvriscv/module-debug-nvriscv-nosafety.mk b/spe-freertos-bsp/fsp/source/drivers/debug/nvriscv/module-debug-nvriscv-nosafety.mk
new file mode 100644
index 0000000..666211f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/nvriscv/module-debug-nvriscv-nosafety.mk
@@ -0,0 +1,63 @@
+#
+# Copyright (c) 2022, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-debug-nvriscv-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_DEBUG_NVRISCV_NOSAFETY_NAME          := DEBUG_NVRISCV
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_DEBUG_NVRISCV_NOSAFETY_DEFINED       := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_DEBUG_NVRISCV_NOSAFETY_DEPENDS       := DEBUG_NVRISCV_NOSAFETY
+$(foreach _,$(CONFIG_DEBUG_NVRISCV_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_DEBUG_NVRISCV_NOSAFETY_C_SRC          =
+MODULE_DEBUG_NVRISCV_NOSAFETY_C_SRC			+= $(DEBUG_NVRISCV_DIR)/print.c
+MODULE_DEBUG_NVRISCV_NOSAFETY_C_SRC			+= $(DEBUG_NVRISCV_DIR)/vprintfmt.c
+
+#
+# Assembly source
+MODULE_DEBUG_NVRISCV_NOSAFETY_ASM_SRC        =
+
+#
+# Special C Flags
+MODULE_DEBUG_NVRISCV_NOSAFETY_C_FLAGS        =
+
+#
+# Special ASM Flags
+MODULE_DEBUG_NVRISCV_NOSAFETY_ASM_FLAGS      =
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/nvriscv/print.c b/spe-freertos-bsp/fsp/source/drivers/debug/nvriscv/print.c
new file mode 100644
index 0000000..aff65e1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/nvriscv/print.c
@@ -0,0 +1,326 @@
+/*
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdarg.h>
+#include <limits.h>
+
+/* Early FSP headers */
+#include <misc/nvmisc_drf.h>
+
+/* Hardware headers */
+#include <cpu/fence.h>
+
+/* Late FSP headers */
+#include <libc-lite/libc.h>
+#include <cpu/io.h>
+
+/* Module-specific FSP headers */
+#include <debug/nvriscv/debug/debug.h>
+#include <debug/nvriscv/debug/print.h>
+#include <debug/nvriscv/debug/vprintfmt.h>
+
+static bool bPrintEnabled = false;
+
+//
+// Local copy of buffer metadata - we don't trust buffer shared with CPU.
+//
+static NVRISCV_DEBUG_BUFFER printBuffer;
+static volatile uint8_t *printBufferData;
+
+#if NVRISCV_CONFIG_DEBUG_PRINT_USES_QUEUES
+static uint32_t queueHeadAddr;
+static uint32_t queueTailAddr;
+#endif
+
+#if NVRISCV_CONFIG_DEBUG_PRINT_METADATA_IN_BUFFER
+static volatile NVRISCV_DEBUG_BUFFER *printBufferTarget;
+#endif
+
+#if NVRISCV_CONFIG_DEBUG_PRINT_USES_SWGEN
+static uint8_t printBufferInterrupt; // SWGEN 0 / 1
+#endif
+
+static const char s_hex_table[16] = "0123456789ABCDEF";
+
+//------------------------------------------------------------------------------
+// Code
+//------------------------------------------------------------------------------
+static bool printBufferIsFull(void)
+{
+    uint32_t wo;
+
+    // Optimized modulo operation
+    wo = printBuffer.writeOffset + 1;
+    if (wo >= printBuffer.bufferSize)
+    {
+        wo -= printBuffer.bufferSize;
+    }
+
+
+#if NVRISCV_CONFIG_DEBUG_PRINT_METADATA_IN_BUFFER
+    printBuffer.readOffset = printBufferTarget->readOffset;
+#endif
+
+// Check queues (if enabled) *after* we read offset from buffer. That way
+// both can be enabled, but queue takes precedence.
+#if NVRISCV_CONFIG_DEBUG_PRINT_USES_QUEUES
+    // re-read register if we think we run out of buffer space
+    if (printBuffer.readOffset == wo)
+    {
+        printBuffer.readOffset = pri_read(queueTailAddr);
+    }
+#endif
+
+    return printBuffer.readOffset == wo;
+}
+
+static void debugLogsFlush(void)
+{
+    //
+    // Ensure logs reach system memory, increment corresponding offset and
+    // send notification (interrupt) to client RM.
+    // MK TODO: maybe lightweight fence if there is no fbif?
+    //
+#if !NVRISCV_HAS_FBIF || NVRISCV_WAR_FBIF_IS_DEAD
+    riscv_lw_fence_io();
+#else
+    riscv_fence_rw();
+#endif
+
+#if NVRISCV_PLATFORM_IS_CMOD
+#if NVRISCV_CONFIG_DEBUG_PRINT_METADATA_IN_BUFFER
+    printBuffer.readOffset = printBufferTarget->readOffset;
+#endif
+
+    // This is based on Cmod print code
+    local_write(NV_PRGNLCL_FALCON_DEBUGINFO, 0x15c0de02); //start code
+    local_write(NV_PRGNLCL_FALCON_DEBUGINFO, 0x00000000); //number
+    while (printBuffer.readOffset != printBuffer.writeOffset)
+    {
+        local_write(NV_PRGNLCL_FALCON_DEBUGINFO, (uint32_t)(printBufferData[printBuffer.readOffset]) );
+        // Optimized modulo operation
+        printBuffer.readOffset = printBuffer.readOffset + 1;
+        if (printBuffer.readOffset >= printBuffer.bufferSize)
+        {
+            printBuffer.readOffset -= printBuffer.bufferSize;
+        }
+    }
+    local_write(NV_PRGNLCL_FALCON_DEBUGINFO, 0x0e0dc0de); //end code
+
+#if NVRISCV_CONFIG_DEBUG_PRINT_METADATA_IN_BUFFER
+    printBufferTarget->readOffset = printBuffer.readOffset;
+#endif
+#else //NVRISCV_PLATFORM_IS_CMOD
+#if NVRISCV_CONFIG_DEBUG_PRINT_USES_QUEUES
+    pri_write(queueHeadAddr,
+             printBuffer.writeOffset);
+#endif
+
+#if NVRISCV_CONFIG_DEBUG_PRINT_METADATA_IN_BUFFER
+    printBufferTarget->writeOffset = printBuffer.writeOffset;
+#endif
+
+#if NVRISCV_CONFIG_DEBUG_PRINT_USES_SWGEN
+    if (printBufferInterrupt == 0)
+        local_write(NV_PRGNLCL_FALCON_IRQSSET, DRF_DEF(_PRGNLCL, _FALCON_IRQSSET, _SWGEN0, _SET));
+    else
+        local_write(NV_PRGNLCL_FALCON_IRQSSET, DRF_DEF(_PRGNLCL, _FALCON_IRQSSET, _SWGEN1, _SET));
+#endif
+#endif //NVRISCV_PLATFORM_IS_CMOD
+}
+
+static void debugPutchar(int ch, void *pArg GCC_ATTR_UNUSED)
+{
+    // If buffer is full, notify client RM and stall GSP
+    if (printBufferIsFull())
+    {
+        debugLogsFlush();
+        do
+        {
+        } while (printBufferIsFull());
+    }
+
+    // Replace newline with null char for ease of displaying debug logs
+    if (ch == '\n')
+    {
+        ch = '\0';
+    }
+
+    printBufferData[printBuffer.writeOffset] = (uint8_t)ch;
+
+    // Optimized modulo operation
+    printBuffer.writeOffset = printBuffer.writeOffset + 1;
+    if (printBuffer.writeOffset >= printBuffer.bufferSize)
+    {
+        printBuffer.writeOffset -= printBuffer.bufferSize;
+    }
+}
+
+bool printInitEx(void *pBuffer, uint16_t bufferSize, uint32_t queueHeadPri, uint32_t queueTailPri, uint8_t swgenNo)
+{
+    if (pBuffer == NULL)
+    {
+        return false;
+    }
+
+    if (bufferSize & 0x7)
+    {
+        return false;
+    }
+
+    if (bufferSize < sizeof(printBuffer) + 16)
+    {
+        return false;
+    }
+
+    if ((uintptr_t)pBuffer & 0x7)
+    {
+        return false;
+    }
+
+#if NVRISCV_CONFIG_DEBUG_PRINT_USES_QUEUES
+    queueHeadAddr = queueHeadPri;
+    queueTailAddr = queueTailPri;
+#else
+    (void) queueHeadPri;
+    (void) queueTailPri;
+#endif
+
+#if NVRISCV_CONFIG_DEBUG_PRINT_USES_SWGEN
+    if (swgenNo > 1)
+    {
+        return false;
+    }
+
+    printBufferInterrupt = swgenNo;
+#else
+    (void) swgenNo;
+#endif
+
+    printBufferData = pBuffer;
+    printBuffer.readOffset = 0;
+    printBuffer.writeOffset = 0;
+    printBuffer.bufferSize = (uint32_t)bufferSize - (uint32_t)sizeof(printBuffer);
+    printBuffer.magic = NVRISCV_DEBUG_BUFFER_MAGIC;
+
+    // Let last character be always null char for ease of displaying debug logs
+    printBufferData[printBuffer.bufferSize - 1] = '\0';
+
+#if NVRISCV_CONFIG_DEBUG_PRINT_USES_QUEUES
+    printBuffer.readOffset = pri_read(queueTailAddr);
+    printBuffer.writeOffset = pri_read(queueHeadAddr);
+
+    // Optimized modulo operation
+    if (printBuffer.writeOffset >= printBuffer.bufferSize)
+    {
+        printBuffer.writeOffset -= printBuffer.bufferSize;
+        pri_write(queueHeadAddr, printBuffer.writeOffset);
+    }
+#endif
+
+#if NVRISCV_CONFIG_DEBUG_PRINT_METADATA_IN_BUFFER
+    printBufferTarget = (volatile NVRISCV_DEBUG_BUFFER *)(((uint8_t*)pBuffer) + bufferSize - sizeof(NVRISCV_DEBUG_BUFFER));
+    printBufferTarget->readOffset = printBuffer.readOffset;
+    printBufferTarget->writeOffset = printBuffer.writeOffset;
+    printBufferTarget->bufferSize = printBuffer.bufferSize;
+    printBufferTarget->magic = printBuffer.magic;
+#endif
+
+    bPrintEnabled = true;
+
+    return true;
+}
+
+bool printInit(void *pBuffer, uint16_t bufferSize,
+               uint8_t queueNo GCC_ATTR_UNUSED, uint8_t swgenNo)
+{
+#if NVRISCV_CONFIG_DEBUG_PRINT_USES_QUEUES
+    (void) pBuffer;
+    (void) bufferSize;
+    (void) swgenNo;
+    return false; // We can't do queues with legacy print init, return error
+#else
+    return printInitEx(pBuffer, bufferSize, 0, 0, swgenNo);
+#endif // NVRISCV_CONFIG_DEBUG_PRINT_USES_QUEUES
+}
+
+
+
+int putchar(int c)
+{
+    if (bPrintEnabled)
+    {
+        debugPutchar(c, 0);
+        debugLogsFlush();
+    }
+    return 0;
+}
+
+int puts(const char *pStr)
+{
+    if ((pStr != NULL) && bPrintEnabled)
+    {
+        for (; *pStr; pStr++)
+        {
+            debugPutchar(*pStr, 0);
+        }
+        debugLogsFlush();
+    }
+    return 0;
+}
+
+void putHex(unsigned count, unsigned long value)
+{
+    if (bPrintEnabled)
+    {
+        while (count)
+        {
+            count--;
+            putchar(s_hex_table[(value >> (count * 4)) & 0xF]);
+        }
+        debugLogsFlush();
+    }
+}
+
+int printf(const char *pFmt, ...)
+{
+    va_list ap;
+
+    va_start(ap, pFmt);
+
+    if (bPrintEnabled)
+    {
+        vprintfmt(debugPutchar, 0, pFmt, ap);
+
+        debugLogsFlush();
+    }
+    va_end(ap);
+
+    return 0;
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/nvriscv/vprintfmt.c b/spe-freertos-bsp/fsp/source/drivers/debug/nvriscv/vprintfmt.c
new file mode 100644
index 0000000..86fe07d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/nvriscv/vprintfmt.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2013-2021, NVIDIA Corporation.  All rights reserved.
+ *
+ * NVIDIA Corporation and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA Corporation is strictly prohibited.
+ */
+
+/*
+ * This file originates from Tegra code base:
+ * Repo: git-master.nvidia.com:12001/tegra/bootloader/nvtboot
+ * Branch: Master
+ * Commit: 5dc8a5123649165aa9adca7d976e5df79d6bb176
+ * File: common/lib/debug/nvtboot_debug.c
+ * File MD5: 9e36645a615840f2248bb9c195cd1d90
+ * This code was mostly ported by Sukanto Ghosh (form previous Tegra bootloaders).
+ *
+ * libnvriscv version is branched off chips_a:
+ * //sw/dev/gpu_drv/chips_a/uproc/nvriscv/shlib/src/shlib/nv_vprintfmt.c#3
+ */
+
+/* Debug printf utilities, semihosting, assertion, etc */
+#include <stdarg.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#include <debug/nvriscv/debug/vprintfmt.h>
+
+#define PRINTNUM_MAX_LEN 64
+
+#if (__riscv_xlen == 32)
+#define VPRINTFMT_UNSIGNE_LONG_TYPE unsigned long
+#else // (__riscv_xlen == 32)
+#define VPRINTFMT_UNSIGNE_LONG_TYPE unsigned long long
+#endif // (__riscv_xlen == 32)
+
+static int s_printNum(void (*putch)(int, void*), void *putdat,
+                    VPRINTFMT_UNSIGNE_LONG_TYPE n, int sign, int pad,
+                    int alternate_form, unsigned radix, char padchar)
+{
+    static const char digits[] = "0123456789abcdefghijklmnopqrstuvwxyz";
+    int len = 0;
+    int total;
+    VPRINTFMT_UNSIGNE_LONG_TYPE x = n;
+
+    // calculate length
+    do
+    {
+        x /= radix;
+        len++;
+    } while (x > 0u);
+
+    if (sign < 0)
+    {
+        len++;
+    }
+
+    if (alternate_form)
+    {
+        if (radix == 8u)
+        {
+            len++;
+        } else if (radix == 16u)
+        {
+            len += 2;
+        }
+    }
+
+    if (len > pad)
+    {
+        total = len;
+        pad = 0;
+    }
+    else
+    {
+        total = pad;
+        pad -= len;
+    }
+
+    // pad
+    while (pad--)
+    {
+        putch(padchar, putdat);
+    }
+
+    // write sign
+    if (sign < 0)
+    {
+        putch('-', putdat);
+        len--;
+    }
+
+    // prefix '0x' (hex-values) or '0' (octal-values)
+    if (alternate_form)
+    {
+        if (radix == 8)
+        {
+            putch('0', putdat);
+            len--;
+        } else if (radix == 16)
+        {
+            putch('0', putdat);
+            putch('x', putdat);
+            len -= 2;
+        }
+    }
+
+    // write integer
+    if (len > PRINTNUM_MAX_LEN)
+    {
+        len = PRINTNUM_MAX_LEN;
+    }
+
+    {
+        char num[PRINTNUM_MAX_LEN];
+        int i;
+
+        x = n;
+        i = len;
+        while (i--)
+        {
+            num[i] = digits[x % radix];
+            x /= radix;
+        }
+        for (i=0; i<len; ++i)
+        {
+            putch(num[i], putdat);
+        }
+    }
+
+    return total;
+}
+
+int vprintfmt(void (*putch)(int, void*), void *putdat,
+              const char* pFormat, va_list ap)
+{
+    const char* f = pFormat;
+    int total = 0; // total chars written
+    char padchar = ' ';
+
+    while (1)
+    {
+        int wrote = 0;
+        char cur = *(f++);
+
+        // end of pFormat
+        if (cur == '\0')
+        {
+            break;
+        }
+
+        // pFormatted argument
+        if (cur != '%')
+        {
+            // print string literals
+            putch(cur, putdat);
+            wrote = 1;
+        }
+        else
+        {
+            const char* arg = f;
+            int pad = 0;
+            int longint = 0;
+            int sign = 0;
+            int base = 0;
+            int alternate_form = 0;
+
+            if (*arg == '#')
+            {
+                alternate_form = 1;
+                arg++;
+            }
+
+            // support for %0N zero-padding
+            if (*arg == '0')
+            {
+                padchar = '0';
+                arg++;
+            }
+
+            while ((*arg >= '0') && (*arg <= '9'))
+            {
+                pad *= 10;
+                pad += (*(arg++)) - '0';
+            }
+
+            if (*arg == 'p')
+            {
+                // %p == %#lx
+                alternate_form = 1;
+                longint = 1;
+            }
+
+            if (*arg == 'l')
+            {
+                arg++;
+                longint = 1;
+#if (__riscv_xlen == 32)
+                if (*(arg) == 'l')
+                {
+                    arg++;
+                    longint = 2;
+                }
+#endif // (__riscv_xlen == 32)
+            }
+
+            switch (*(arg++))
+            {
+            case 'i':
+            case 'd':
+                sign = 1;
+                __attribute__((fallthrough));
+            case 'u':
+                base = 10;
+                __attribute__((fallthrough));
+            case 'o':
+                if (!base)
+                    base = 8;
+                __attribute__((fallthrough));
+            case 'p':
+            case 'x':
+            case 'X':
+                {
+                    VPRINTFMT_UNSIGNE_LONG_TYPE val;
+
+                    if (!base)
+                        base = 16;
+
+                    if (longint == 2)
+                    {
+                        long long int tmp = va_arg(ap, long long int);
+                        if ((sign) && (tmp < 0))
+                        {
+                            sign = -1;
+                            tmp = -tmp;
+                        }
+                        val = (VPRINTFMT_UNSIGNE_LONG_TYPE int)tmp;
+                    } else if (longint == 1)
+                    {
+                        long int tmp = va_arg(ap, long int);
+                        if ((sign) && (tmp < 0))
+                        {
+                            sign = -1;
+                            tmp = -tmp;
+                        }
+                        val = (unsigned long int)tmp;
+                    } else
+                    {
+                        int tmp = va_arg(ap, int);
+                        if ((sign) && (tmp < 0))
+                        {
+                            sign = -1;
+                            tmp = -tmp;
+                        }
+                        val = (unsigned int)tmp;
+                    }
+
+                    wrote = s_printNum(putch, putdat, val, sign, pad,
+                                       alternate_form, (unsigned)base, padchar);
+                }
+                break;
+            case 's':
+                {
+                    char* val = va_arg(ap, char *);
+
+                    wrote = 0;
+                    while (val[wrote])
+                    {
+                        putch(val[wrote], putdat);
+                        wrote++;
+                    }
+
+                    if (wrote == 0)
+                    {
+                        f = arg;
+                        wrote = -2;
+                    }
+                }
+                break;
+            case 'c':
+                {
+                    char val = (char)va_arg(ap, unsigned);
+
+                    putch(val, putdat);
+                    wrote = 1;
+                }
+                break;
+            case '%':
+                putch('%', putdat);
+                wrote = 1;
+                break;
+            default:
+                // unsupported, just return with whatever already printed
+                wrote = -1;
+                break;
+            }
+
+            if (wrote >= 0)
+                f = arg;
+        }
+
+        if (wrote == -1)
+            break;
+
+        // put this after the previous if statement (wrote == 0)
+        if (wrote == -2)
+        {
+            wrote = 0;
+        }
+
+        total += wrote;
+    }
+
+    return total;
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/print.c b/spe-freertos-bsp/fsp/source/drivers/debug/print.c
new file mode 100644
index 0000000..d578abe
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/print.c
@@ -0,0 +1,85 @@
+/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdarg.h>            // for va_end, va_start
+#include <stdint.h>            // for uint32_t
+#include <stdio.h>             // for va_list, printf, vprintf
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>    // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>       // START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <debug/print.h>       // for FSP__DEBUG__PRINT_H, print_driver, pri...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__PRINT_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+static uint32_t print_log_level = PRINT_LEVEL_INFO;
+
+void print_message(uint32_t level,
+                   const char *format,
+                   ...)
+{
+    va_list args;
+
+    if (level <= print_log_level) {
+        va_start(args, format);
+        vprintf(format, args);
+        va_end(args);
+    }
+}
+
+void set_print_log_level(const uint32_t level)
+{
+    print_log_level = level;
+}
+
+uint32_t get_print_log_level(void)
+{
+    return print_log_level;
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/debug/retarget-stdio.c b/spe-freertos-bsp/fsp/source/drivers/debug/retarget-stdio.c
new file mode 100644
index 0000000..b057a09
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/debug/retarget-stdio.c
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * ARM Standardlib STDIO retargeting for bare metal OS-less environment.
+ *
+ */
+
+/* Compiler headers */
+#include <stdio.h>           // for FILE, fputc
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>  // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <debug/debug.h>     // for dbg_putd, FSP__DEBUG__DEBUG_H
+#include <misc/macros.h>     // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__DEBUG__DEBUG_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+/* FILE is typedef’d in stdio.h. */
+FILE __stdout;
+
+INLINE_RFD(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx", MISRA, DEVIATE, Directive_4_6, "Approval: Bug 200543266, DR: SWE-FSP-003-SWSADR.docx")
+int fputc(int ch, FILE *f)
+{
+        char tempch = ch;
+
+        dbg_putd(&tempch, 1);
+
+        return ch;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/external/ivclib/module-ivclib-nosafety-config.mk b/spe-freertos-bsp/fsp/source/drivers/external/ivclib/module-ivclib-nosafety-config.mk
new file mode 100644
index 0000000..ffdba16
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/external/ivclib/module-ivclib-nosafety-config.mk
@@ -0,0 +1,54 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-ivclib-nosafety-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to
+#   VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_IVCLIB_NOSAFETY_CONFIG           := 1
+
+#
+# Define a something similar to header guard protection...for makefiles
+# instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_IVCLIB_NOSAFETY_DEFINED          := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_IVCLIB_NOSAFETY_DEPENDS          := CPL
+$(foreach _,$(MODULE_IVCLIB_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_IVCLIB_NOSAFETY_DRIVERS_DIR       = $(FSP_IVCLIB_REPO)/ivc
+MODULE_IVCLIB_NOSAFETY_SOURCE_DIR        = $(MODULE_IVCLIB_NOSAFETY_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_IVCLIB_NOSAFETY_INCLUDES          = -I $(FSP_IVCLIB_REPO)/include
diff --git a/spe-freertos-bsp/fsp/source/drivers/external/ivclib/module-ivclib-nosafety.mk b/spe-freertos-bsp/fsp/source/drivers/external/ivclib/module-ivclib-nosafety.mk
new file mode 100644
index 0000000..abb3ba0
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/external/ivclib/module-ivclib-nosafety.mk
@@ -0,0 +1,60 @@
+#
+# Copyright (c) 2020-2021 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-ivclib-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to
+#   VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_IVCLIB_NOSAFETY_NAME             := IVCLIB_NOSAFETY  
+
+#
+# Define a something similar to header guard protection...for makefiles
+# instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_IVCLIB_NOSAFETY_DEFINED          := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_IVCLIB_NOSAFETY_DEPENDS          := IVCLIB_NOSAFETY
+$(foreach _,$(CONFIG_IVCLIB_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_IVCLIB_NOSAFETY_C_SRC             =
+MODULE_IVCLIB_NOSAFETY_C_SRC            += $(MODULE_IVCLIB_NOSAFETY_DRIVERS_DIR)/tegra-ivc.c
+MODULE_IVCLIB_NOSAFETY_C_SRC            += $(MODULE_IVCLIB_NOSAFETY_DRIVERS_DIR)/sivc.c
+
+#
+# Special C Flags
+MODULE_IVCLIB_NOSAFETY_C_FLAGS           =
+
+#
+# Special ASM Flags
+MODULE_IVCLIB_NOSAFETY_ASM_FLAGS         =
diff --git a/spe-freertos-bsp/fsp/source/drivers/fbdma/fbdma.c b/spe-freertos-bsp/fsp/source/drivers/fbdma/fbdma.c
new file mode 100644
index 0000000..8b008e1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/fbdma/fbdma.c
@@ -0,0 +1,417 @@
+/* _NVRM_COPYRIGHT_BEGIN_
+ *
+ * Copyright 2020-2022 by NVIDIA Corporation.  All rights reserved.  All
+ * information contained herein is proprietary and confidential to NVIDIA
+ * Corporation.  Any use, reproduction, or disclosure without the written
+ * permission of NVIDIA Corporation is prohibited.
+ *
+ * _NVRM_COPYRIGHT_END_
+ */
+
+/*!
+ * @file    fbdma.c
+ * @brief   FBDMA driver
+ *
+ * Used to load data from FB to IMEM/DMEM and vice-versa.
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <misc/nvmisc_drf.h>
+
+#include <fbdma/fbdma.h>
+#include <cpu/io_local.h>
+
+//
+// MISRA 1.2 RFD: #pragma usage
+// MISRA 4.9 RFD: function-like macros
+// MISRA 15.1 RFD: Forward gotos
+// MISRA 8.7 RFD: Functions with external linkage only referenced in one translation unit
+//
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
+
+#if NVRISCV_FEATURE_SCP
+#include <scp/scp.h>
+#include <misc/ct-assert.h>
+
+#ifndef SCP_REGISTER_SIZE
+#error "SCP_REGISTER_SIZE not defined!"
+#endif
+
+CT_ASSERT(SCP_REGISTER_SIZE % DMA_BLOCK_SIZE_MIN == 0U,
+    "Minimum SCPDMA transfer size is not aligned to minimum FBDMA block size!");
+#endif
+
+#if (NVRISCV_IMEM_SIZE == 0U) || (NVRISCV_DMEM_SIZE == 0U)
+#error "NVRISCV_IMEM_SIZE and NVRISCV_DMEM_SIZE must be configured"
+#endif
+
+/**
+ * @brief Create a NV_PRGNLCL_FALCON_DMATRFCMD register value for a dma transfer
+ *
+ * @param[in] tcm_pa The RISCV PA for the TCM buffer. Must be aligned to DMA_BLOCK_SIZE_MIN,
+ * but DMA_BLOCK_SIZE_MAX alignement is optimal.
+ * @param[in] aperture_offset The external address (GPU PA or GPU VA) in the aperture
+ * determined by dma_idx. The type of memory to access is determined by FBIF_APERTURE_CFG.memType
+ * (on engines with FBIF) or by TFBIF_APERTURE_CFG.swid (on engines with TFBIF).
+ * memutils_riscv_pa_to_target_offset can be used to translate a RISCV PA to a GPU PA/VA suitable for
+ * this argument. Must be aligned to DMA_BLOCK_SIZE_MIN, but DMA_BLOCK_SIZE_MAX alignement
+ * is optimal.
+ * @param[in] size_bytes The number of bytes to transfer. Must have a granularity of
+ * DMA_BLOCK_SIZE_MIN, but DMA_BLOCK_SIZE_MAX granularity is optimal.
+ * @param[in] dma_idx Aperture index to use (0-7).
+ * @param[in] b_read_ext Transfer direction. true: External->TCM. false: TCM->External
+ * @param[out] p_dma_cmd The NV_PRGNLCL_FALCON_DMATRFCMD register value to use for this transfer.
+ * @param[out] p_tcm_offset The offset of tcm_pa from the start of its TCM.
+ *
+ * @return E_SUCCESS on success.
+ *         E_INVALID_PARAM if tcm_pa is not a valid TCM address or if size_bytes, tcm_offset,
+ * or aperture_offset are not properly aligned.
+ */
+static error_t
+create_dma_command(
+    uint64_t tcm_pa,
+    uint64_t size_bytes,
+    uint8_t  dma_idx,
+    bool     b_read_ext,
+    uint32_t *p_dma_cmd,
+    uint32_t *p_tcm_offset
+)
+{
+    error_t status = E_SUCCESS;
+    bool b_tcm_imem = false;
+    uint32_t dma_cmd = 0;
+    uint32_t tcm_offset = 0;
+    uint64_t tcm_buf_end;
+
+    // overflow check for tcm_pa + size_bytes
+    if ((UINT64_MAX - tcm_pa) < size_bytes)
+    {
+        status = E_INVALID_PARAM;
+        goto out;
+    }
+    else
+    {
+        tcm_buf_end = tcm_pa + size_bytes - 1U;
+    }
+
+    // tcm_pa is in ITCM or DTCM?
+    if ((tcm_pa >= NV_RISCV_AMAP_IMEM_START) &&
+        (tcm_buf_end < (NV_RISCV_AMAP_IMEM_START + (uint64_t)NVRISCV_IMEM_SIZE)))
+    {
+        b_tcm_imem = true;
+        tcm_offset = (uint32_t)((tcm_pa - NV_RISCV_AMAP_IMEM_START) & 0xFFFFFFFFU);
+    }
+    else if ((tcm_pa >= NV_RISCV_AMAP_DMEM_START) &&
+        (tcm_buf_end < (NV_RISCV_AMAP_DMEM_START + (uint64_t)NVRISCV_DMEM_SIZE)))
+    {
+        tcm_offset = (uint32_t)((tcm_pa - NV_RISCV_AMAP_DMEM_START) & 0xFFFFFFFFU);
+    }
+    else
+    {
+        status = E_INVALID_PARAM;
+        goto out;
+    }
+
+    if (b_tcm_imem)
+    {
+        dma_cmd = FLD_SET_DRF(_PRGNLCL, _FALCON_DMATRFCMD, _IMEM, _TRUE, dma_cmd);
+    }
+    else
+    {
+        dma_cmd = FLD_SET_DRF(_PRGNLCL, _FALCON_DMATRFCMD, _IMEM, _FALSE, dma_cmd);
+        dma_cmd = FLD_SET_DRF(_PRGNLCL, _FALCON_DMATRFCMD, _SET_DMTAG, _TRUE, dma_cmd);
+    }
+
+    if (b_read_ext) // Ext -> TCM
+    {
+        dma_cmd = FLD_SET_DRF(_PRGNLCL, _FALCON_DMATRFCMD, _WRITE, _FALSE, dma_cmd);
+    }
+    else // TCM -> Ext
+    {
+        dma_cmd = FLD_SET_DRF(_PRGNLCL, _FALCON_DMATRFCMD, _WRITE, _TRUE, dma_cmd);
+    }
+
+    if (dma_idx <= DMA_MAX_DMAIDX)
+    {
+        dma_cmd = FLD_SET_DRF_NUM(_PRGNLCL, _FALCON_DMATRFCMD, _CTXDMA, dma_idx, dma_cmd);
+    }
+    else
+    {
+        status = E_INVALID_PARAM;
+        goto out;
+    }
+
+    *p_dma_cmd = dma_cmd;
+    *p_tcm_offset = tcm_offset;
+
+out:
+    return status;
+}
+
+/**
+ * @brief Kick off a DMA transfer between TCM PA and External memory
+ *
+ * @param[in] tcm_offset The offset of the TCM address from the start of that TCM.
+ * @param[in] aperture_offset The external address (GPU PA or GPU VA) in the aperture
+ *            determined by dma_idx. This can be a GPU VA or GPU PA.
+ * @param[in] size_bytes The number of bytes to DMA.
+ * @param[in] dma_cmd The value to write into the NV_PRGNLCL_FALCON_DMATRFCMD register,
+ * excluding the size field. size will be determined inside this function.
+ *
+ * @return E_SUCCESS on success.
+ *         E_INVALID_PARAM if aperture_offset is not a valid address or size_bytes, tcm_pa,
+ *          or aperture_offset do not meet minimum alignment requirements.
+ *
+ * @pre The FBIF/TFBIF aperture referenced by dma_idx must have been configured by
+ * fbifConfigureAperture or tfbifConfigureAperture. If the aperture is configured
+ * to use a GPU VA, a context must be bound.
+ */
+static error_t
+fbdma_xfer(
+    uint32_t tcm_offset,
+    uint64_t aperture_offset,
+    uint64_t size_bytes,
+    uint32_t dma_cmd
+)
+{
+    error_t err = E_SUCCESS;
+    uint32_t dma_block_size;
+    uint8_t dma_enc_block_size;
+    uint32_t current_tcm_offset = tcm_offset;
+    uint64_t bytes_remaining = size_bytes;
+    uint32_t dma_cmd_with_block_size = dma_cmd;
+    uint32_t fb_offset;
+
+    if (((aperture_offset | size_bytes | tcm_offset) & (DMA_BLOCK_SIZE_MIN - 1U)) != 0U)
+    {
+        err = E_INVALID_PARAM;
+        goto out;
+    }
+
+    // When REQUIRE_CTX = true, DMAs without a CTX bound will report idle immediately but won't actually be issued
+    local_write(NV_PRGNLCL_FALCON_DMACTL,
+        DRF_DEF(_PRGNLCL, _FALCON_DMACTL, _REQUIRE_CTX, _FALSE));
+
+    //
+    // Break up aperture_offset into a base/offset to be used in DMATRFBASE, TRFFBOFFS
+    // Note: We cannot use current_tcm_offset for both TRFMOFFS and TRFFBOFFS because this
+    // would require us to calculate a DMATRFBASE value by subtracting
+    // (aperture_offset - current_tcm_offset) and this may result in a misaligned value
+    // which we cannot program into DMATRFBASE.
+    //
+    fb_offset = (uint32_t) (aperture_offset & 0xFFU);
+
+    // Check for overflows (CERT-C INT30 violation in current_tcm_offset += dma_block_size; fb_offset += dma_block_size;)
+    // There is no codepath which allows current_tcm_offset + size_bytes to overflow. This check is just to appease CERT-C.
+    if (((UINT64_MAX - current_tcm_offset) < size_bytes) ||
+        ((UINT64_MAX - fb_offset) < size_bytes))
+    {
+        err = E_INVALID_PARAM;
+        goto out;
+    }
+
+    local_write(NV_PRGNLCL_FALCON_DMATRFBASE, (uint32_t)((aperture_offset >> 8U) & 0xffffffffU));
+#ifdef NV_PRGNLCL_FALCON_DMATRFBASE1
+    local_write(NV_PRGNLCL_FALCON_DMATRFBASE1, (uint32_t)(((aperture_offset >> 8U) >> 32U) & 0xffffffffU));
+#else //NV_PRGNLCL_FALCON_DMATRFBASE1
+    if ((((aperture_offset >> 8U) >> 32U) & 0xffffffffU) != 0U)
+    {
+        err = E_INVALID_PARAM;
+        goto out;
+    }
+#endif //NV_PRGNLCL_FALCON_DMATRFBASE1
+
+    while (bytes_remaining != 0U)
+    {
+        // Wait if we're full
+        while (FLD_TEST_DRF(_PRGNLCL, _FALCON_DMATRFCMD, _FULL, _TRUE, local_read(NV_PRGNLCL_FALCON_DMATRFCMD)))
+        {
+        }
+
+        local_write(NV_PRGNLCL_FALCON_DMATRFMOFFS, current_tcm_offset); // This is fine as long as caller does error checking.
+        local_write(NV_PRGNLCL_FALCON_DMATRFFBOFFS, fb_offset);
+
+        // Determine the largest pow2 block transfer size of the remaining data
+        dma_block_size = LOWESTBIT(current_tcm_offset | fb_offset | DMA_BLOCK_SIZE_MAX);
+
+        // Reduce the dma_block_size to not exceed remaining data.
+        while (dma_block_size > bytes_remaining)
+        {
+            dma_block_size >>= 1U;
+        }
+
+        // Convert the pow2 block size to block size encoding
+        dma_enc_block_size = (uint8_t)BIT_IDX_32(dma_block_size / DMA_BLOCK_SIZE_MIN);
+        dma_cmd_with_block_size = FLD_SET_DRF_NUM(_PRGNLCL, _FALCON_DMATRFCMD, _SIZE, dma_enc_block_size, dma_cmd);
+
+        local_write(NV_PRGNLCL_FALCON_DMATRFCMD, dma_cmd_with_block_size);
+
+        bytes_remaining -= dma_block_size;
+        current_tcm_offset += dma_block_size;
+        fb_offset += dma_block_size;
+    }
+
+out:
+    return err;
+}
+
+error_t
+fbdma_pa
+(
+    uint64_t tcm_pa,
+    uint64_t aperture_offset,
+    uint64_t size_bytes,
+    uint8_t  dma_idx,
+    bool     b_read_ext
+)
+{
+    error_t ret;
+    uint32_t tcm_offset;
+    uint32_t dma_cmd;
+
+    ret = create_dma_command(tcm_pa, size_bytes, dma_idx, b_read_ext, &dma_cmd, &tcm_offset);
+    if (ret != E_SUCCESS)
+    {
+        goto out;
+    }
+
+    // Nothing to copy, bail after checks
+    if (size_bytes == 0U)
+    {
+        ret = E_SUCCESS;
+        goto out;
+    }
+
+    ret = fbdma_xfer(tcm_offset, aperture_offset, size_bytes, dma_cmd);
+    if (ret != E_SUCCESS)
+    {
+        goto out;
+    }
+
+    INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-1795, DR: SWE-FSP-062-SWSADR.docx");
+    ret = fbdma_wait_completion();
+
+out:
+    return ret;
+}
+
+error_t
+fbdma_pa_async(uint64_t tcm_pa,
+               uint64_t aperture_offset,
+               uint64_t size_bytes,
+               uint8_t  dma_idx,
+               bool     b_read_ext
+)
+{
+    error_t ret;
+    uint32_t tcm_offset;
+    uint32_t dma_cmd;
+
+    ret = create_dma_command(tcm_pa, size_bytes, dma_idx, b_read_ext, &dma_cmd, &tcm_offset);
+    if (ret != E_SUCCESS)
+    {
+        goto out;
+    }
+
+    // Nothing to copy, bail after checks
+    if (size_bytes == 0U)
+    {
+        ret = E_SUCCESS;
+        goto out;
+    }
+
+    INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-1795, DR: SWE-FSP-062-SWSADR.docx");
+    ret = fbdma_xfer(tcm_offset, aperture_offset, size_bytes, dma_cmd);
+
+out:
+    return ret;
+}
+
+error_t
+fbdma_wait_completion(void)
+{
+    error_t err = E_SUCCESS;
+    uint32_t dmatrfcmd;
+    uint32_t dmainfo;
+
+    // Wait for completion of any remaining transfers
+    do {
+        dmatrfcmd = local_read(NV_PRGNLCL_FALCON_DMATRFCMD);
+    }
+    while (FLD_TEST_DRF(_PRGNLCL, _FALCON_DMATRFCMD, _IDLE, _FALSE, dmatrfcmd));
+
+    if (FLD_TEST_DRF(_PRGNLCL, _FALCON_DMATRFCMD, _ERROR, _TRUE, dmatrfcmd))
+    {
+        err = E_FAULT;
+        goto out;
+    }
+
+    dmainfo = local_read(NV_PRGNLCL_FALCON_DMAINFO_CTL);
+    if (FLD_TEST_DRF(_PRGNLCL, _FALCON_DMAINFO_CTL, _INTR_ERR_COMPLETION, _TRUE, dmainfo))
+    {
+        // Received DMA NACK, clear it and return error
+        dmainfo = FLD_SET_DRF(_PRGNLCL, _FALCON_DMAINFO_CTL, _INTR_ERR_COMPLETION, _CLR, dmainfo);
+        local_write(NV_PRGNLCL_FALCON_DMAINFO_CTL, dmainfo);
+        err = E_BUSY;
+        goto out;
+    }
+
+out:
+    return err;
+}
+
+#if NVRISCV_FEATURE_SCP || defined(TEST_SCPTOEXTMEM)
+error_t
+fbdma_scp_to_extmem(
+    uint64_t aperture_offset,
+    uint64_t size_bytes,
+    uint8_t dma_idx
+)
+{
+    error_t ret;
+
+    // Nothing to copy
+    if (size_bytes == 0U)
+    {
+        return E_SUCCESS;
+    }
+
+    if ((((size_bytes | aperture_offset) & (SCP_REGISTER_SIZE - 1U)) != 0U) ||
+        (dma_idx > DMA_MAX_DMAIDX))
+    {
+        return E_INVALID_PARAM;
+    }
+
+    //
+    // Set dma_cmd:
+    // - write to Extmem
+    // - enable direct bypass shortcut path from SCP
+    // - dma_idx
+    //
+    uint32_t dma_cmd = DRF_DEF(_PRGNLCL, _FALCON_DMATRFCMD, _WRITE, _TRUE) |
+                DRF_NUM(_PRGNLCL, _FALCON_DMATRFCMD, _SEC, 2U) |
+                DRF_NUM(_PRGNLCL, _FALCON_DMATRFCMD, _CTXDMA, dma_idx);
+
+    //
+    // call fbdma_xfer with tcm_offset=0, since this value won't get used anyways:
+    // Data is sourced from SCP.
+    //
+    ret = fbdma_xfer(0U, aperture_offset, size_bytes, dma_cmd);
+    if (ret != E_SUCCESS)
+    {
+        return ret;
+    }
+
+    INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-1795, DR: SWE-FSP-062-SWSADR.docx");
+    return fbdma_wait_completion();
+}
+#endif // NVRISCV_FEATURE_SCP
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/fbdma/fbif.c b/spe-freertos-bsp/fsp/source/drivers/fbdma/fbif.c
new file mode 100644
index 0000000..1275e97
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/fbdma/fbif.c
@@ -0,0 +1,101 @@
+/* _NVRM_COPYRIGHT_BEGIN_
+ *
+ * Copyright 2021-2022 by NVIDIA Corporation.  All rights reserved.  All
+ * information contained herein is proprietary and confidential to NVIDIA
+ * Corporation.  Any use, reproduction, or disclosure without the written
+ * permission of NVIDIA Corporation is prohibited.
+ *
+ * _NVRM_COPYRIGHT_END_
+ */
+
+/*!
+ * @file    fbif.c
+ * @brief   FBIF driver
+ *
+ * Used to configure FBIF apertures
+ */
+
+#include <stddef.h>
+#include <misc/nvmisc_drf.h>
+
+#include <fbdma/fbif.h>
+#include <cpu/io_local.h>
+
+//
+// MISRA 4.9 RFD: function-like macros
+// MISRA 15.1 RFD: Forward gotos
+// MISRA 8.7 RFD: Functions with external linkage only referenced in one translation unit
+//
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
+
+//The register manual currently doesn't define this as an indexed field.
+//Because of this, we need to define our own. We have asked the hardware
+//Folks to provide an indexed field definition in the manuals, so we don't
+//need to do this here.
+#define NV_PRGNLCL_FBIF_REGIONCFG_T_XMSB(i) (((i)*4U)+3U)
+#define NV_PRGNLCL_FBIF_REGIONCFG_T_XLSB(i) ((i)*4U)
+
+error_t
+fbif_configure_aperture
+(
+    const fbif_aperture_cfg_t *p_cfgs,
+    uint8_t num_cfgs
+)
+{
+    error_t err = E_SUCCESS;
+    uint8_t idx;
+    uint32_t regioncfg;
+
+    if (p_cfgs == NULL)
+    {
+        err = E_INVALID_PARAM;
+        goto out;
+    }
+
+    regioncfg = local_read(NV_PRGNLCL_FBIF_REGIONCFG);
+
+    for (idx = 0U; idx < num_cfgs; idx++)
+    {
+        if ((p_cfgs[idx].aperture_idx >= FBIF_NUM_APERTURES) ||
+            (p_cfgs[idx].target >= FBIF_TRANSCFG_TARGET_COUNT) ||
+            (p_cfgs[idx].l2c_wr >= FBIF_TRANSCFG_L2C_COUNT) ||
+            (p_cfgs[idx].l2c_rd >= FBIF_TRANSCFG_L2C_COUNT) ||
+            (p_cfgs[idx].region_id >= (1U << DRF_SIZE(NV_PRGNLCL_FBIF_REGIONCFG_T0)))
+        )
+        {
+            err = E_INVALID_PARAM;
+            goto out;
+        }
+
+        regioncfg = FLD_IDX_SET_DRF_NUM(_PRGNLCL, _FBIF_REGIONCFG, _T,
+                                        p_cfgs[idx].aperture_idx, p_cfgs[idx].region_id, regioncfg);
+
+        local_write(NV_PRGNLCL_FBIF_TRANSCFG((uint32_t)p_cfgs[idx].aperture_idx),
+            DRF_NUM(_PRGNLCL, _FBIF_TRANSCFG, _TARGET, p_cfgs[idx].target) |
+            DRF_NUM(_PRGNLCL, _FBIF_TRANSCFG, _MEM_TYPE,
+                ((p_cfgs[idx].b_target_va) ?
+                NV_PRGNLCL_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL : NV_PRGNLCL_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL)) |
+            DRF_NUM(_PRGNLCL, _FBIF_TRANSCFG, _L2C_WR, p_cfgs[idx].l2c_wr) |
+            DRF_NUM(_PRGNLCL, _FBIF_TRANSCFG, _L2C_RD, p_cfgs[idx].l2c_rd) |
+            DRF_NUM(_PRGNLCL, _FBIF_TRANSCFG, _WACHK0, p_cfgs[idx].b_fbif_transcfg_wachk0_enable ? 1 : 0) |
+            DRF_NUM(_PRGNLCL, _FBIF_TRANSCFG, _WACHK1, p_cfgs[idx].b_fbif_transcfg_wachk1_enable ? 1 : 0) |
+            DRF_NUM(_PRGNLCL, _FBIF_TRANSCFG, _RACHK0, p_cfgs[idx].b_fbif_transcfg_rachk0_enable ? 1 : 0) |
+            DRF_NUM(_PRGNLCL, _FBIF_TRANSCFG, _RACHK1, p_cfgs[idx].b_fbif_transcfg_rachk1_enable ? 1 : 0)
+#ifdef NV_PRGNLCL_FBIF_TRANSCFG_ENGINE_ID_FLAG
+            //Some instances of the FBIF do not have this field
+            | DRF_NUM(_PRGNLCL, _FBIF_TRANSCFG, _ENGINE_ID_FLAG, p_cfgs[idx].b_engine_id_flag_own ? 1 : 0)
+#endif //NV_PRGNLCL_FBIF_TRANSCFG_ENGINE_ID_FLAG
+            );
+    }
+
+    local_write(NV_PRGNLCL_FBIF_REGIONCFG, regioncfg);
+
+out:
+    return err;
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/fbdma/memutils.c b/spe-freertos-bsp/fsp/source/drivers/fbdma/memutils.c
new file mode 100644
index 0000000..5d32535
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/fbdma/memutils.c
@@ -0,0 +1,144 @@
+/* _NVRM_COPYRIGHT_BEGIN_
+ *
+ * Copyright 2021-2022 by NVIDIA Corporation.  All rights reserved.  All
+ * information contained herein is proprietary and confidential to NVIDIA
+ * Corporation.  Any use, reproduction, or disclosure without the written
+ * permission of NVIDIA Corporation is prohibited.
+ *
+ * _NVRM_COPYRIGHT_END_
+ */
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+#include <error/common-errors.h>
+
+#include <fbdma/memutils.h>
+#include <cpu/io_local.h>
+
+//
+// MISRA 4.9 RFD: function-like macros
+// MISRA 15.1 RFD: Forward gotos
+// MISRA 8.7 RFD: Functions with external linkage only referenced in one translation unit
+//
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
+
+#if NVRISCV_HAS_FBIF
+#include <fbdma/fbif.h>
+#endif // NVRISCV_HAS_FBIF
+
+#if NVRISCV_HAS_FBIF
+error_t
+memutils_riscv_pa_to_fbif_aperture
+(
+    uintptr_t pa,
+    fbif_transcfg_target_t *p_target,
+    uint64_t *p_offset
+)
+{
+    riscv_mem_target_t mem_target;
+    error_t status;
+
+    if (p_target == NULL)
+    {
+        status = E_INVALID_PARAM;
+        goto out;
+    }
+
+    // Obtain the memory target and offset for the provided physical address.
+    status = memutils_riscv_pa_to_target_offset(pa, &mem_target, p_offset);
+    if(status != E_SUCCESS)
+    {
+        goto out;
+    }
+
+    // Translate the memory target to its corresponding FBIF target.
+    switch (mem_target)
+    {
+        case RISCV_MEM_TARGET_FBGPA:
+            *p_target = FBIF_TRANSCFG_TARGET_LOCAL_FB;
+            break;
+
+        case RISCV_MEM_TARGET_SYSGPA:
+            //
+            // Just assume coherent here as this value is meant to be
+            // passed to dmaPa() anyway.
+            //
+            *p_target = FBIF_TRANSCFG_TARGET_COHERENT_SYSTEM;
+            break;
+
+        default:
+            status = E_INVALID_PARAM;
+            break;
+    }
+
+out:
+    return status;
+}
+#endif // NVRISCV_HAS_FBIF
+
+error_t
+memutils_riscv_pa_to_target_offset
+(
+    uintptr_t pa,
+    riscv_mem_target_t *p_target,
+    uint64_t *p_offset
+)
+{
+    error_t status = E_SUCCESS;
+    riscv_mem_target_t target;
+    uint64_t offset;
+
+    // Determine which memory region pa resides in.
+    if (memutils_mem_addr_in_range(pa, NV_RISCV_AMAP_IMEM_START, NV_RISCV_AMAP_IMEM_END))
+    {
+        target = RISCV_MEM_TARGET_IMEM;
+        offset = pa - NV_RISCV_AMAP_IMEM_START;
+    }
+    else if (memutils_mem_addr_in_range(pa, NV_RISCV_AMAP_DMEM_START, NV_RISCV_AMAP_DMEM_END))
+    {
+        target = RISCV_MEM_TARGET_DMEM;
+        offset = pa - NV_RISCV_AMAP_DMEM_START;
+    }
+#ifdef NV_RISCV_AMAP_FBGPA_START
+    else if (memutils_mem_addr_in_range(pa, NV_RISCV_AMAP_FBGPA_START, NV_RISCV_AMAP_FBGPA_END))
+    {
+        target = RISCV_MEM_TARGET_FBGPA;
+        offset = pa - NV_RISCV_AMAP_FBGPA_START;
+    }
+#endif // NV_RISCV_AMAP_FBGPA_START
+#ifdef NV_RISCV_AMAP_SYSGPA_START
+    else if (memutils_mem_addr_in_range(pa, NV_RISCV_AMAP_SYSGPA_START, NV_RISCV_AMAP_SYSGPA_END))
+    {
+        target = RISCV_MEM_TARGET_SYSGPA;
+        offset = pa - NV_RISCV_AMAP_SYSGPA_START;
+    }
+#endif // NV_RISCV_AMAP_SYSGPA_START
+    else
+    {
+        // Not a supported memory region.
+        status = E_INVALID_PARAM;
+        goto out;
+    }
+
+    // Return target/offset information as requested.
+    if (p_target != NULL)
+    {
+        *p_target = target;
+    }
+
+    if (p_offset != NULL)
+    {
+        *p_offset = offset;
+    }
+
+out:
+    return status;
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/fbdma/module-fbdma-config.mk b/spe-freertos-bsp/fsp/source/drivers/fbdma/module-fbdma-config.mk
new file mode 100644
index 0000000..d35dcbe
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/fbdma/module-fbdma-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-fbdma-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_FBDMA_CONFIG               := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_FBDMA_DEPENDS              := CPL FSP_COMMON
+$(foreach _,$(MODULE_FBDMA_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_FBDMA_DRIVERS_DIR           = $(FSP_COMMON_REPO)/drivers/fbdma
+MODULE_FBDMA_SOURCE_DIR            = $(MODULE_FBDMA_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_FBDMA_INCLUDES              =
diff --git a/spe-freertos-bsp/fsp/source/drivers/fbdma/module-fbdma.mk b/spe-freertos-bsp/fsp/source/drivers/fbdma/module-fbdma.mk
new file mode 100644
index 0000000..4e1f372
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/fbdma/module-fbdma.mk
@@ -0,0 +1,77 @@
+#
+# Copyright (c) 2020-2023, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-fbdma.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_FBDMA_NAME                 := FBDMA
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_FBDMA_DEFINED              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_FBDMA_DEPENDS              := FBDMA CPL
+$(foreach _,$(CONFIG_FBDMA_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_FBDMA_C_SRC                 =
+
+MODULE_FBDMA_C_SRC                += $(MODULE_FBDMA_DRIVERS_DIR)/memutils.c
+
+ifeq ($(NVRISCV_FEATURE_DMA),y)
+ifeq ($(NVRISCV_HAS_FBDMA),y)
+MODULE_FBDMA_C_SRC                += $(MODULE_FBDMA_DRIVERS_DIR)/fbdma.c
+endif
+endif
+
+ifeq ($(NVRISCV_HAS_FBIF),y)
+MODULE_FBDMA_C_SRC                += $(MODULE_FBDMA_DRIVERS_DIR)/fbif.c
+endif
+
+ifeq ($(NVRISCV_HAS_TFBIF),y)
+MODULE_FBDMA_C_SRC                += $(MODULE_FBDMA_DRIVERS_DIR)/tfbif.c
+endif
+
+#
+# Assembly source
+MODULE_FBDMA_ASM_SRC               =
+
+#
+# Special C Flags
+MODULE_FBDMA_C_FLAGS               =
+
+#
+# Special ASM Flags
+MODULE_FBDMA_ASM_FLAGS             =
diff --git a/spe-freertos-bsp/fsp/source/drivers/fbdma/tfbif.c b/spe-freertos-bsp/fsp/source/drivers/fbdma/tfbif.c
new file mode 100644
index 0000000..474dd25
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/fbdma/tfbif.c
@@ -0,0 +1,106 @@
+/* _NVRM_COPYRIGHT_BEGIN_
+ *
+ * Copyright 2020-2022 by NVIDIA Corporation.  All rights reserved.  All
+ * information contained herein is proprietary and confidential to NVIDIA
+ * Corporation.  Any use, reproduction, or disclosure without the written
+ * permission of NVIDIA Corporation is prohibited.
+ *
+ * _NVRM_COPYRIGHT_END_
+ */
+
+/*!
+ * @file    tfbif.c
+ * @brief   TFBIF driver
+ *
+ * Used to configure TFBIF apertures
+ */
+
+#include <stddef.h>
+#include <misc/nvmisc_drf.h>
+
+#include <fbdma/tfbif.h>
+#include <cpu/io_local.h>
+
+//
+// MISRA 4.9 RFD: function-like macros
+// MISRA 15.1 RFD: Forward gotos
+// MISRA 8.7 RFD: Functions with external linkage only referenced in one translation unit
+//
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
+
+
+//The register manuals currently don't define these as indexed fields.
+//Because of this, we need to define our own. We have asked the hardware
+//Folks to provide indexed field definitions in the manuals, so we don't
+//need to do this here.
+#define NV_PRGNLCL_TFBIF_TRANSCFG_ATT_SWID(i)     ((i)*4u+1U):((i)*4U)
+#define NV_PRGNLCL_TFBIF_TRANSCFG_ATT_SWID_XMSB(i)     ((i)*4U+1U)
+#define NV_PRGNLCL_TFBIF_TRANSCFG_ATT_SWID_XLSB(i)     ((i)*4U)
+
+#define NV_PRGNLCL_TFBIF_REGIONCFG_T_VPR(i)       ((i)*4U+3U):((i)*4U+3U)
+#define NV_PRGNLCL_TFBIF_REGIONCFG_T_VPR_XMSB(i)       ((i)*4U+3U)
+#define NV_PRGNLCL_TFBIF_REGIONCFG_T_VPR_XLSB(i)       ((i)*4U+3U)
+
+#define NV_PRGNLCL_TFBIF_REGIONCFG1_T_APERT_ID(i) ((i)*8U+4U):((i)*8U)
+#define NV_PRGNLCL_TFBIF_REGIONCFG1_T_APERT_ID_XMSB(i) ((i)*8U+4U)
+#define NV_PRGNLCL_TFBIF_REGIONCFG1_T_APERT_ID_XLSB(i) ((i)*8U)
+
+#define NV_PRGNLCL_TFBIF_REGIONCFG2_T_APERT_ID(i) (((i)-4U)*8U+4U):(((i)-4U)*8U)
+#define NV_PRGNLCL_TFBIF_REGIONCFG2_T_APERT_ID_XMSB(i) (((i)-4U)*8U+4U)
+#define NV_PRGNLCL_TFBIF_REGIONCFG2_T_APERT_ID_XLSB(i) (((i)-4U)*8U)
+
+error_t
+tfbif_configure_aperture
+(
+    const tfbif_aperture_cfg_t *p_cfgs,
+    uint8_t num_cfgs
+)
+{
+    error_t err = E_SUCCESS;
+    uint8_t idx;
+    uint32_t transcfg, regioncfg, regioncfg1, regioncfg2;
+
+    if (p_cfgs == NULL)
+    {
+        err = E_INVALID_PARAM;
+        goto out;
+    }
+
+    transcfg = local_read(NV_PRGNLCL_TFBIF_TRANSCFG);
+    regioncfg = local_read(NV_PRGNLCL_TFBIF_REGIONCFG);
+    regioncfg1 = local_read(NV_PRGNLCL_TFBIF_REGIONCFG1);
+    regioncfg2 = local_read(NV_PRGNLCL_TFBIF_REGIONCFG2);
+
+    for (idx = 0; idx < num_cfgs; idx++)
+    {
+        if (p_cfgs[idx].aperture_idx >= TFBIF_NUM_APERTURES ||
+            p_cfgs[idx].swid >= (1 << DRF_SIZE(NV_PRGNLCL_TFBIF_TRANSCFG_ATT0_SWID)) ||
+            p_cfgs[idx].aperture_id >= (1 << DRF_SIZE(NV_PRGNLCL_TFBIF_REGIONCFG1_T0_APERT_ID))
+        )
+        {
+            err = E_INVALID_PARAM;
+            goto out;
+        }
+
+        transcfg = FLD_IDX_SET_DRF_NUM(_PRGNLCL, _TFBIF_TRANSCFG, _ATT_SWID, p_cfgs[idx].aperture_idx, p_cfgs[idx].swid, transcfg);
+        regioncfg = FLD_IDX_SET_DRF_NUM(_PRGNLCL, _TFBIF_REGIONCFG, _T_VPR, p_cfgs[idx].aperture_idx, p_cfgs[idx].b_vpr, regioncfg);
+        if (p_cfgs[idx].aperture_idx <= 3)
+        {
+            regioncfg1 = FLD_IDX_SET_DRF_NUM(_PRGNLCL, _TFBIF_REGIONCFG1, _T_APERT_ID, p_cfgs[idx].aperture_idx, p_cfgs[idx].aperture_id, regioncfg1);
+        }
+        else
+        {
+            regioncfg2 = FLD_IDX_SET_DRF_NUM(_PRGNLCL, _TFBIF_REGIONCFG2, _T_APERT_ID, p_cfgs[idx].aperture_idx - 4, p_cfgs[idx].aperture_id, regioncfg2);
+        }
+    }
+
+    local_write(NV_PRGNLCL_TFBIF_TRANSCFG, transcfg);
+    local_write(NV_PRGNLCL_TFBIF_REGIONCFG, regioncfg);
+    local_write(NV_PRGNLCL_TFBIF_REGIONCFG1, regioncfg1);
+    local_write(NV_PRGNLCL_TFBIF_REGIONCFG2, regioncfg2);
+
+out:
+    return err;
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/gpcdma/gpcdma.c b/spe-freertos-bsp/fsp/source/drivers/gpcdma/gpcdma.c
new file mode 100644
index 0000000..e140286
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/gpcdma/gpcdma.c
@@ -0,0 +1,1025 @@
+_Pragma("coverity compliance block(include) \
+         (deviate MISRA_C_2012_Rule_1_2 \"Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx\") \
+         (deviate MISRA_C_2012_Directive_4_8 \"Approval: Bug 200534384, DR: SWE-FSP-011-SWSADR.docx\")")
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                   // for bool
+#include <stdint.h>                    // for uint32_t, uint8_t, UINT32_...
+#include <string.h>                    // for NULL
+                                       // IWYU pragma: no_include <errno.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>            // for CT_ASSERT
+#include <soc-common/hw-const.h>       // IWYU pragma: keep
+#include <soc-common/argpcdma-defs.h>  // GPCDMA_CHANNEL_CH...
+
+/* Hardware headers */
+#include <misc/nvrm_drf.h>             // NV_DRF_* macros
+
+/* Late FSP headers */
+#include <cpu/type-conversion.h>       // for fsp_c_v_ptr_to_u32
+#include <error/common-errors.h>       // for error_t, E_SUCCESS
+#include <irq/safe-irqs.h>             // for in_interrupt, irq_safe_enable, irq_safe_set...
+#include <misc/attributes.h>           // for UNUSED
+#include <misc/bitops.h>               // for BIT, bit_number, FSP__MISC__BITOPS_H
+#include <misc/macros.h>               // for ARRAY_SIZE
+#include <reg-access/reg-access.h>     // for readl_base_offset, writel_base_of...
+#include <debug/assert.h>              // for ASSERT, ...
+#include <delay/delay.h>               // for udelay
+#include <lock/smplock-up.h>           // for smp_unlock_irqrestore, smp_loc...
+
+/* Module specific headers */
+#include <gpcdma/gpcdma-errors.h>      // for E_GPCDMA_NULL_PTR, E_GPCDMA_...
+#include <gpcdma/sections-gpcdma.h>    // Immune from CT_ASSERT protection
+#include <gpcdma/gpcdma-priv.h>        // for struct gpcdma_id, gpcdma_channel...
+#include <gpcdma/gpcdma-port.h>        // for gpcdma_port_...
+#include <gpcdma/gpcdma.h>             // for gpcdma_xfer and gpcdma_* apis
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__ARGPCDMA_DEFS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__TYPE_CONVERSION_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ASSERT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DELAY__DELAY_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__LOCK__SMPLOCK_UP_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPCDMA__GPCDMA_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPCDMA__GPCDMA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPCDMA__GPCDMA_PORT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPCDMA__GPCDMA_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+#define GPCDMA_ADDR_MASK     0xFFFFFFFFUL
+#define GPCDMA_HI_ADDR_MASK  0xFFU
+#define GPCDMA_HI_ADDR_SHIFT 32UL
+
+SECTION_GPCDMA_TEXT static inline uint32_t
+gpcdma_chan_readl(const struct gpcdma_channel *dma_chan,
+                  uint32_t reg)
+{
+    return readl_base_offset(dma_chan->chan_base, reg);
+}
+
+SECTION_GPCDMA_TEXT static inline void
+gpcdma_chan_writel(const struct gpcdma_channel *dma_chan,
+                   uint32_t val,
+                   uint32_t reg)
+{
+    writel_base_regoffset(val, dma_chan->chan_base, reg);
+}
+
+SECTION_GPCDMA_TEXT static inline bool
+gpcdma_chan_is_valid(const struct gpcdma_id *id,
+                     uint32_t chan_num)
+{
+    return (chan_num < ARRAY_SIZE(id->channels));
+}
+
+SECTION_GPCDMA_TEXT static inline struct
+gpcdma_channel *gpcdma_chan(const struct gpcdma_id *id,
+                            uint32_t chan_num)
+{
+    return id->channels[chan_num];
+}
+
+SECTION_GPCDMA_TEXT static inline uint32_t
+gpcdma_chan_base(const struct gpcdma_id *id,
+                 uint32_t chan)
+{
+    const uint32_t channel_stride = GPCDMA_CHANNEL_CH1_CSR_0 -
+                                        GPCDMA_CHANNEL_CH0_CSR_0;
+
+    INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    return id->conf.base_addr + (chan * channel_stride);
+}
+
+#if defined(HW_BUG_200667678) && (HW_BUG_200667678 == 1)
+SECTION_GPCDMA_TEXT static inline void
+gpcdma_disable_virtualization(const struct gpcdma_id *id)
+{
+    writel_base_regoffset(0UL, id->conf.base_addr,
+                          GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0);
+}
+#endif
+
+/* Create list of buffers each equal to period_len for the cyclic mode */
+SECTION_GPCDMA_TEXT static error_t
+gpcdma_create_list(struct gpcdma_xfer const *transfer, uint32_t id)
+{
+    struct gpcdma_buf_desc desc;
+    uint32_t el_cnt, period_len, rem_len;
+    uint64_t src_addr, dst_addr, cont_buf, const_buf;
+    error_t ret = E_SUCCESS;
+
+    dst_addr = transfer->dst_addr;
+    src_addr = transfer->src_addr;
+    rem_len = transfer->xfer_count;
+    period_len = transfer->period_len;
+    el_cnt = rem_len / period_len;
+
+    if (transfer->direction == GPCDMA_XFER_DIR_IO_TO_MEM) {
+        cont_buf = dst_addr;
+        const_buf = src_addr;
+    } else {
+        cont_buf = src_addr;
+        const_buf = dst_addr;
+    }
+
+    ret = gpcdma_port_init_queue(id, el_cnt, sizeof(struct gpcdma_buf_desc));
+
+    if (ret != E_SUCCESS) {
+        goto out_no_del;
+    }
+
+    while ((rem_len != 0UL) && (ret == E_SUCCESS)) {
+        if (transfer->direction == GPCDMA_XFER_DIR_IO_TO_MEM) {
+            desc.src_addr = (uint32_t)(const_buf & GPCDMA_ADDR_MASK);
+            desc.dst_addr = (uint32_t)(cont_buf & GPCDMA_ADDR_MASK);
+            desc.hi_src_addr = (uint32_t)((const_buf >> GPCDMA_HI_ADDR_SHIFT) &
+                                          GPCDMA_HI_ADDR_MASK);
+            desc.hi_dst_addr = (uint32_t)((cont_buf >> GPCDMA_HI_ADDR_SHIFT) &
+                                          GPCDMA_HI_ADDR_MASK);
+        } else {
+            desc.src_addr = (uint32_t)(cont_buf & GPCDMA_ADDR_MASK);
+            desc.dst_addr = (uint32_t)(const_buf & GPCDMA_ADDR_MASK);
+            desc.hi_src_addr = (uint32_t)((cont_buf >> GPCDMA_HI_ADDR_SHIFT) &
+                                          GPCDMA_HI_ADDR_MASK);
+            desc.hi_dst_addr = (uint32_t)((const_buf >> GPCDMA_HI_ADDR_SHIFT) &
+                                          GPCDMA_HI_ADDR_MASK);
+        }
+        ret = gpcdma_port_send_desc_to_back(id, (void *)&desc, 0UL, false);
+
+        if (ret != E_SUCCESS) {
+            continue;
+        }
+
+        if (rem_len < period_len) {
+            ret = E_GPCDMA_INVALID_PARAM;
+        } else {
+            rem_len -= period_len;
+        }
+
+        if ((UINT64_MAX - cont_buf) < period_len) {
+            ret = E_GPCDMA_INVALID_PARAM;
+        } else {
+            cont_buf += period_len;
+        }
+    }
+
+    if (ret != E_SUCCESS) {
+        gpcdma_port_delete_queue(id);
+    }
+
+out_no_del:
+    return ret;
+}
+/* End of cyclic mode codes */
+
+SECTION_GPCDMA_TEXT static inline uint32_t
+gpcdma_wcount_to_wrap_sz(uint32_t wcount,
+                         bool io_wrap)
+{
+    uint32_t wrap = 0UL;
+
+    if (wcount == 0UL) {
+        goto out;
+    }
+
+    /*
+     * mmio address wrap : 2^n where n ranges from 0 to 6
+     * mc address wrap : 2^n where n ranges from 5 to 11
+     */
+    wrap = io_wrap ? (bit_number(wcount) + 1UL) :
+                     ((bit_number(wcount) + 1UL) - 5UL);
+
+out:
+    return wrap;
+}
+
+SECTION_GPCDMA_TEXT static inline void
+gpcdma_configure_wcount(const struct gpcdma_channel *dma_chan)
+{
+    /*
+     * byte count register expects the value to be in words.
+     * Value N means (N + 1) words transfer request size.
+     */
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-451, Example-5, DR: SWE-FSP-046-SWSADR.docx");
+    gpcdma_chan_writel(dma_chan, (dma_chan->words_to_xfer - 1UL),
+                       GPCDMA_CHANNEL_CH0_WCOUNT_0);
+}
+
+SECTION_GPCDMA_TEXT static inline void
+gpcdma_configure_mc_sequencer(const struct gpcdma_channel *dma_chan,
+                              const struct gpcdma_xfer *xfer,
+                              bool src_io,
+                              bool dst_io)
+{
+    uint32_t val;
+    uint32_t mc_src_wrap, mc_dst_wrap;
+
+    mc_src_wrap = src_io ? 0UL :
+                    gpcdma_wcount_to_wrap_sz(xfer->src_addr_wrap, false);
+    mc_dst_wrap = dst_io ? 0UL :
+                    gpcdma_wcount_to_wrap_sz(xfer->dst_addr_wrap, false);
+
+    /*
+     * FIXME: Figure out a way to drive this burst size by xfer->burst_size.
+     */
+    val = NV_DRF_DEF(GPCDMA, CHANNEL_CH0_MC_SEQ, MC_BURST, DMA_BURST_16WORDS) |
+        NV_DRF_DEF(GPCDMA, CHANNEL_CH0_MC_SEQ, MC_REQ_CNT, DEFAULT) |
+        NV_DRF_NUM(GPCDMA, CHANNEL_CH0_MC_SEQ, MC_ADDR_WRAP0, mc_src_wrap) |
+        NV_DRF_NUM(GPCDMA, CHANNEL_CH0_MC_SEQ, MC_ADDR_WRAP1, mc_dst_wrap);
+
+    /* program the stream ids depending on the xfer direction */
+    switch (xfer->direction) {
+    case GPCDMA_XFER_DIR_MEM_TO_MEM:
+        val |= NV_DRF_NUM(GPCDMA, CHANNEL_CH0_MC_SEQ,
+                          STREAMID0, xfer->src_sid);
+        val |= NV_DRF_NUM(GPCDMA, CHANNEL_CH0_MC_SEQ,
+                          STREAMID1, xfer->dst_sid);
+        break;
+    case GPCDMA_XFER_DIR_IO_TO_MEM:
+        val |= NV_DRF_NUM(GPCDMA, CHANNEL_CH0_MC_SEQ,
+                          STREAMID0, xfer->dst_sid);
+        break;
+    case GPCDMA_XFER_DIR_MEM_TO_IO:
+        val |= NV_DRF_NUM(GPCDMA, CHANNEL_CH0_MC_SEQ,
+                          STREAMID0, xfer->src_sid);
+        break;
+
+    default:
+        /* will never run into this as the transfer is already validated */
+        break;
+    }
+
+    gpcdma_chan_writel(dma_chan, val, GPCDMA_CHANNEL_CH0_MC_SEQ_0);
+}
+
+SECTION_GPCDMA_TEXT static inline void
+gpcdma_configure_mmio_sequencer(const struct gpcdma_channel *dma_chan,
+                                const struct gpcdma_xfer *xfer,
+                                bool src_io,
+                                bool dst_io)
+{
+    uint32_t val = 0UL;
+    uint32_t io_wrap;
+
+    /*
+     * MMIO sequencer needs to be programmed only for IO2MEM or MEM2IO
+     * transfers.
+     */
+    if (src_io || dst_io) {
+        val = NV_DRF_NUM(GPCDMA, CHANNEL_CH0_MMIO_SEQ, MMIO_BUS_WIDTH,
+                         xfer->bus_width);
+        INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-451, Example-5, DR: SWE-FSP-046-SWSADR.docx");
+        val |= NV_DRF_NUM(GPCDMA, CHANNEL_CH0_MMIO_SEQ, MMIO_BURST,
+                          (xfer->burst_size - 1UL));
+        io_wrap = src_io ? gpcdma_wcount_to_wrap_sz(xfer->src_addr_wrap, true) :
+                           gpcdma_wcount_to_wrap_sz(xfer->dst_addr_wrap, true);
+        val |= NV_DRF_NUM(GPCDMA, CHANNEL_CH0_MMIO_SEQ, MMIO_ADDR_WRAP, io_wrap);
+    }
+
+    gpcdma_chan_writel(dma_chan, val, GPCDMA_CHANNEL_CH0_MMIO_SEQ_0);
+}
+
+SECTION_GPCDMA_TEXT static inline void
+gpcdma_clear_error_status(const struct gpcdma_channel *dma_chan)
+{
+    gpcdma_chan_writel(dma_chan, 0xFFFFFFFFUL,
+                       GPCDMA_CHANNEL_CH0_ERR_STA_0);
+}
+
+SECTION_GPCDMA_TEXT static inline void
+gpcdma_configure_hi_adr_ptr(const struct gpcdma_channel *dma_chan,
+                            uint32_t hi_src_ptr, uint32_t hi_dst_ptr)
+{
+    uint32_t val;
+
+    val = NV_DRF_NUM(GPCDMA, CHANNEL_CH0_HI_ADR_PTR,
+                     HI_DST_PTR, hi_dst_ptr) |
+          NV_DRF_NUM(GPCDMA, CHANNEL_CH0_HI_ADR_PTR,
+                     HI_SRC_PTR, hi_src_ptr);
+
+    gpcdma_chan_writel(dma_chan, val, GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0);
+}
+
+SECTION_GPCDMA_TEXT static inline void
+gpcdma_configure_addr_ptrs(const struct gpcdma_channel *dma_chan,
+                           uint32_t src_addr, uint32_t dst_addr)
+{
+    gpcdma_chan_writel(dma_chan, src_addr, GPCDMA_CHANNEL_CH0_SRC_PTR_0);
+    gpcdma_chan_writel(dma_chan, dst_addr, GPCDMA_CHANNEL_CH0_DST_PTR_0);
+}
+
+SECTION_GPCDMA_TEXT static inline void
+gpcdma_configure_csr(const struct gpcdma_channel *dma_chan,
+                     const struct gpcdma_xfer *xfer,
+                     uint32_t dma_mode)
+{
+    uint32_t val;
+
+    val = dma_mode;
+    if (xfer->en_flow_ctrl) {
+        val |= NV_DRF_NUM(GPCDMA, CHANNEL_CH0_CSR, REQ_SEL,
+                          xfer->slave_req);
+    }
+
+    if (xfer->continuous) {
+        val |= NV_DRF_DEF(GPCDMA, CHANNEL_CH0_CSR, ONCE, CYCLIC_MODE);
+    } else {
+        val |= NV_DRF_DEF(GPCDMA, CHANNEL_CH0_CSR, ONCE, SINGLE_BLOCK);
+    }
+    val |= NV_DRF_DEF(GPCDMA, CHANNEL_CH0_CSR, IRQ_MASK, ENABLE) |
+           NV_DRF_DEF(GPCDMA, CHANNEL_CH0_CSR, IE_EOC, ENABLE) |
+           NV_DRF_DEF(GPCDMA, CHANNEL_CH0_CSR, WEIGHT, DEFAULT) |
+           NV_DRF_DEF(GPCDMA, CHANNEL_CH0_CSR, ENB, ENABLE);
+
+    gpcdma_chan_writel(dma_chan, val, GPCDMA_CHANNEL_CH0_CSR_0);
+}
+
+SECTION_GPCDMA_TEXT static error_t
+gpcdma_get_xfer_dma_mode(const struct gpcdma_xfer *transfer,
+                         uint32_t *dma_mode,
+                         bool *src_io,
+                         bool *dst_io)
+{
+    error_t ret = E_SUCCESS;
+
+    switch (transfer->direction) {
+    case GPCDMA_XFER_DIR_MEM_TO_IO:
+        *dma_mode = (transfer->en_flow_ctrl) ?
+            NV_DRF_DEF(GPCDMA, CHANNEL_CH0_CSR, DMA_MODE, MEM2IO_FC) :
+            NV_DRF_DEF(GPCDMA, CHANNEL_CH0_CSR, DMA_MODE, MEM2IO_NO_FC);
+        *src_io = false;
+        *dst_io = true;
+        break;
+    case GPCDMA_XFER_DIR_IO_TO_MEM:
+        *dma_mode = (transfer->en_flow_ctrl) ?
+            NV_DRF_DEF(GPCDMA, CHANNEL_CH0_CSR, DMA_MODE, IO2MEM_FC) :
+            NV_DRF_DEF(GPCDMA, CHANNEL_CH0_CSR, DMA_MODE, IO2MEM_NO_FC);
+        *src_io = true;
+        *dst_io = false;
+        break;
+    case GPCDMA_XFER_DIR_MEM_TO_MEM:
+        *dma_mode = NV_DRF_DEF(GPCDMA, CHANNEL_CH0_CSR, DMA_MODE, MEM2MEM);
+        *src_io = false;
+        *dst_io = false;
+        break;
+    default:
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPCDMA_INVALID_XFER_DIR;
+        break;
+    }
+
+    return ret;
+}
+
+SECTION_GPCDMA_TEXT static inline error_t
+gpcdma_validate_flow_cntrl(const struct gpcdma_xfer *xfer)
+{
+    error_t ret = E_SUCCESS;
+
+    if (xfer->en_flow_ctrl) {
+        if (xfer->slave_req > GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_DEFAULT_MASK) {
+            INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+            ret = E_GPCDMA_INVALID_FC_REQ_ID;
+        }
+    }
+
+    return ret;
+}
+
+SECTION_GPCDMA_TEXT static error_t
+gpcdma_validate_wrap(uint32_t wrap,
+                     bool io_addr)
+{
+    error_t     ret = E_SUCCESS;
+    uint32_t    val;
+    uint32_t    wrap_mask;
+
+    /* wrap must be a power of 2 */
+    if ((wrap > 0UL) && ((wrap & (wrap - 1UL)) != 0UL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPCDMA_INVALID_ADDR_WRAP;
+        goto out;
+    }
+
+    val = gpcdma_wcount_to_wrap_sz(wrap, io_addr);
+    wrap_mask = (io_addr ?
+                 GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK :
+                 GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK);
+
+    if (val > wrap_mask) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPCDMA_INVALID_ADDR_WRAP;
+        goto out;
+    }
+
+out:
+    return ret;
+}
+
+SECTION_GPCDMA_TEXT static error_t
+gpcdma_validate_xfer(struct gpcdma_channel *dma_chan,
+                     struct gpcdma_xfer const *xfer,
+                     bool src_io,
+                     bool dst_io)
+{
+    error_t     ret = E_SUCCESS;
+    uint32_t    align_mask;
+
+    /* check if callback exists for asynchronous transfers */
+    if (!xfer->synchronous && (xfer->callback == NULL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPCDMA_NO_CALLBACK_ASYNC;
+        goto out;
+    }
+
+    /* Sanity check for continuous mode */
+    if (xfer->continuous) {
+        if (xfer->period_len == 0UL) {
+            ret = E_GPCDMA_INVALID_PARAM;
+            goto out;
+        }
+        if ((xfer->period_len & 3UL) != 0UL) {
+            ret = E_GPCDMA_INVALID_PARAM;
+            goto out;
+        }
+        if ((xfer->xfer_count % xfer->period_len) != 0UL) {
+            ret = E_GPCDMA_INVALID_PARAM;
+            goto out;
+        }
+        if (xfer->direction == GPCDMA_XFER_DIR_MEM_TO_MEM) {
+            ret = E_GPCDMA_INVALID_PARAM;
+            goto out;
+        }
+    }
+
+    /* update the channel callback */
+    dma_chan->callback = (xfer->synchronous) ? NULL : xfer->callback;
+    dma_chan->cdata = xfer->callback_param;
+    dma_chan->synchronous = xfer->synchronous;
+
+    /* check if the transfer size is word aligned */
+    if ((xfer->xfer_count == 0UL) || ((xfer->xfer_count & 0x3UL) != 0UL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPCDMA_INVALID_XFER_SIZE;
+        goto out;
+    }
+
+    /*
+     * for IO2MEM or MEM2IO, transfer size should be aligned to MMIO burst
+     * size. MMIO burst_size is represented in words. Convert it to bytes
+     * in computing the mask for alignment check.
+     */
+    align_mask = (xfer->burst_size << 2) - 1UL;
+    if (((xfer->xfer_count & align_mask) != 0UL) && (src_io || dst_io)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPCDMA_INVALID_XFER_SIZE_IO;
+        goto out;
+    }
+
+    /*
+     * validate [MC/IO] source address wrap and destination address wrap fields
+     * of the transfer.
+     */
+    ret = gpcdma_validate_wrap(xfer->src_addr_wrap, src_io);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+    ret = gpcdma_validate_wrap(xfer->dst_addr_wrap, dst_io);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    /*
+     * IO address needs to be aligned with IO address wrap size.
+     * MC address needs to be word aligned.
+     */
+    align_mask = (xfer->src_addr_wrap != 0UL) ? (xfer->src_addr_wrap - 1UL) : 0UL;
+    if (((xfer->src_addr & 0x3UL) != 0UL) || (src_io &&
+            ((xfer->src_addr & align_mask) != 0UL))) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPCDMA_UNALIGNED_SRC;
+        goto out;
+    }
+    align_mask = (xfer->dst_addr_wrap != 0UL) ? (xfer->dst_addr_wrap - 1UL) : 0UL;
+    if (((xfer->dst_addr & 0x3UL) != 0UL) || (dst_io &&
+            ((xfer->dst_addr & align_mask) != 0UL))) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPCDMA_UNALIGNED_DST;
+        goto out;
+    }
+
+    /*
+     * If flow control is enabled, validate the slave request ID.
+     */
+    ret = gpcdma_validate_flow_cntrl(xfer);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+out:
+    return ret;
+}
+
+SECTION_GPCDMA_TEXT static error_t
+gpcdma_get_chan_context(const struct gpcdma_id *id,
+                        uint32_t chan_num,
+                        struct gpcdma_channel **dma_chan)
+{
+    error_t ret = E_SUCCESS;
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPCDMA_NULL_PTR;
+        goto out;
+    }
+
+    if (!id->inited) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPCDMA_NOT_INITED;
+        goto out;
+    }
+
+    if (!gpcdma_chan_is_valid(id, chan_num)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPCDMA_INVALID_PARAM;
+        goto out;
+    }
+
+    *dma_chan = gpcdma_chan(id, chan_num);
+
+out:
+    return ret;
+}
+
+SECTION_GPCDMA_TEXT static error_t
+gpcdma_pause(const struct gpcdma_channel *dma_chan)
+{
+    uint32_t timeout;
+    uint32_t csre;
+    error_t ret = E_SUCCESS;
+
+    if ((dma_chan == NULL) || !dma_chan->busy) {
+        ret = E_INVALID_PARAM;
+        goto out;
+    }
+
+    timeout = GPCDMA_BURST_COMPLETION_TIMEOUT;
+    csre = gpcdma_chan_readl(dma_chan, GPCDMA_CHANNEL_CH0_CSRE_0);
+    csre |= NV_DRF_DEF(GPCDMA, CHANNEL_CH0_CSRE, DMA_ACTIVITY, PAUSE);
+    gpcdma_chan_writel(dma_chan, csre, GPCDMA_CHANNEL_CH0_CSRE_0);
+
+    /* Wait until busy bit is de-asserted */
+    do {
+        if (((gpcdma_chan_readl(dma_chan, GPCDMA_CHANNEL_CH0_STA_0) &
+            GPCDMA_CHANNEL_CH0_STA_0_BSY_FIELD)) == 0UL) {
+           break;
+        }
+        udelay(GPCDMA_BURST_COMPLETE_TIME);
+        timeout = (timeout < GPCDMA_BURST_COMPLETE_TIME) ? 0UL :
+                   (timeout - GPCDMA_BURST_COMPLETE_TIME);
+    } while (timeout > 0UL);
+
+    if (timeout == 0UL) {
+        ret = E_TIMEOUT;
+    }
+
+out:
+    return ret;
+}
+
+SECTION_GPCDMA_TEXT static inline void
+gpcdma_resume(const struct gpcdma_channel *dma_chan)
+{
+    uint32_t csre;
+
+    csre = gpcdma_chan_readl(dma_chan, GPCDMA_CHANNEL_CH0_CSRE_0);
+    csre &= NV_DRF_DEF(GPCDMA, CHANNEL_CH0_CSRE, DMA_ACTIVITY, RESUME);
+    gpcdma_chan_writel(dma_chan, csre, GPCDMA_CHANNEL_CH0_CSRE_0);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_GPCDMA_TEXT void gpcdma_chan_irq(void *data)
+{
+    INLINE_RFD(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx");
+    struct gpcdma_channel   *dma_chan = (struct gpcdma_channel *)fsp_c_v_ptr_to_v_ptr(data);
+    struct gpcdma_buf_desc  desc;
+    uint32_t                status;
+
+    smp_lock(dma_chan->lock);
+
+    if (!dma_chan->continuous) {
+        ASSERT(irq_safe_disable(dma_chan->irq) == E_SUCCESS);
+        dma_chan->busy = false;
+    }
+
+    /* Clear the DMA interrupt first */
+    status = gpcdma_chan_readl(dma_chan, GPCDMA_CHANNEL_CH0_STA_0);
+    if (NV_DRF_VAL(GPCDMA, CHANNEL_CH0_STA, ISE_EOC, status) != 0UL) {
+        gpcdma_chan_writel(dma_chan, status, GPCDMA_CHANNEL_CH0_STA_0);
+    }
+
+    if (dma_chan->synchronous) {
+        UNUSED((gpcdma_port_chan_sync_end(dma_chan->id)));
+    } else {
+        if (dma_chan->continuous) {
+            ASSERT(gpcdma_port_get_desc(dma_chan->id, &desc, 0UL,
+                   true) == E_SUCCESS);
+            ASSERT(gpcdma_port_send_desc_to_back(dma_chan->id,
+                   &desc, 0, true) == E_SUCCESS);
+            gpcdma_configure_addr_ptrs(dma_chan, desc.src_addr,
+                                       desc.dst_addr);
+            gpcdma_configure_hi_adr_ptr(dma_chan, desc.hi_src_addr,
+                                        desc.hi_dst_addr);
+            dma_chan->total_bytes = dma_chan->total_bytes +
+                                            (dma_chan->words_to_xfer * 4ULL);
+        }
+        dma_chan->callback(dma_chan->cdata, DMA_STATUS_COMPLETE);
+    }
+    smp_unlock(dma_chan->lock);
+}
+
+SECTION_GPCDMA_TEXT static error_t
+gpcdma_program_cycl_mode(struct gpcdma_xfer const *xfer,
+                         struct gpcdma_channel *dma_chan, bool first)
+{
+    error_t  ret = E_SUCCESS;
+    int32_t  i;
+    struct   gpcdma_buf_desc desc;
+    uint32_t st;
+
+    if (gpcdma_port_get_desc(dma_chan->id, &desc, 0UL,
+                             false) != E_SUCCESS) {
+        ret = E_GPCDMA_QUEUE_OP_FAIL;
+        goto op_failed;
+    }
+
+    if (first) {
+        dma_chan->words_to_xfer = xfer->period_len >> 2UL;
+        dma_chan->continuous = true;
+        dma_chan->total_bytes = 0;
+    } else {
+        i = 20;
+        do {
+            st = gpcdma_chan_readl(dma_chan, GPCDMA_CHANNEL_CH0_STA_0);
+            if ((st & GPCDMA_CHANNEL_CH0_STA_0_BSY_FIELD) != 0UL) {
+                break;
+            }
+            udelay(1);
+            i--;
+        } while (i != 0);
+
+        if (i == 0) {
+            ret = E_GPCDMA_CONT_MODE_OP_FAIL;
+            goto op_failed;
+        }
+    }
+
+    gpcdma_configure_addr_ptrs(dma_chan, desc.src_addr, desc.dst_addr);
+    gpcdma_configure_hi_adr_ptr(dma_chan, desc.hi_src_addr, desc.hi_dst_addr);
+
+    if (gpcdma_port_send_desc_to_back(dma_chan->id, &desc, 0UL,
+                                      false) != E_SUCCESS) {
+        ret = E_GPCDMA_QUEUE_OP_FAIL;
+        goto op_failed;
+    }
+
+op_failed:
+    return ret;
+}
+
+SECTION_GPCDMA_TEXT error_t
+gpcdma_transfer(const struct gpcdma_id *id,
+                uint32_t chan_num,
+                struct gpcdma_xfer const *xfer)
+{
+    error_t     ret = E_SUCCESS;
+    struct      gpcdma_channel *dma_chan;
+    uint32_t    dma_mode;
+    bool        src_io, dst_io;
+    uint32_t    flags = 0;
+    uint32_t    src_addr, dst_addr, hi_src_ptr, hi_dst_ptr;
+
+    if (xfer == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPCDMA_NULL_PTR;
+        goto out;
+    }
+
+    if (xfer->synchronous && xfer->continuous) {
+        ret = E_GPCDMA_INVALID_XFER_MODE;
+        goto out;
+    }
+
+    ret = gpcdma_get_chan_context(id, chan_num, &dma_chan);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    smp_lock_irqsave(dma_chan->lock, &flags);
+    if (dma_chan->busy) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPCDMA_CHAN_BUSY;
+        goto unlock_out;
+    }
+
+    ret = gpcdma_get_xfer_dma_mode(xfer, &dma_mode, &src_io, &dst_io);
+    if (ret != E_SUCCESS) {
+        goto unlock_out;
+    }
+
+    ret = gpcdma_validate_xfer(dma_chan, xfer, src_io, dst_io);
+    if (ret != E_SUCCESS) {
+        goto unlock_out;
+    }
+
+    dma_chan->continuous = false;
+    src_addr = (uint32_t)(xfer->src_addr & GPCDMA_ADDR_MASK);
+    dst_addr = (uint32_t)(xfer->dst_addr & GPCDMA_ADDR_MASK);
+    hi_src_ptr = (uint32_t)((xfer->src_addr >> GPCDMA_HI_ADDR_SHIFT) &
+                            GPCDMA_HI_ADDR_MASK);
+    hi_dst_ptr = (uint32_t)((xfer->dst_addr >> GPCDMA_HI_ADDR_SHIFT) &
+                            GPCDMA_HI_ADDR_MASK);
+    dma_chan->words_to_xfer = xfer->xfer_count >> 2UL;
+
+    if (xfer->continuous) {
+        ret = gpcdma_create_list(xfer, dma_chan->id);
+        if (ret != E_SUCCESS) {
+            ret = E_GPCDMA_QUEUE_ALLOC_FAIL;
+            goto unlock_out;
+        }
+        ret = gpcdma_program_cycl_mode(xfer, dma_chan, true);
+        if (ret != E_SUCCESS) {
+            goto op_failed;
+        }
+    } else {
+        gpcdma_configure_addr_ptrs(dma_chan, src_addr, dst_addr);
+        gpcdma_configure_hi_adr_ptr(dma_chan, hi_src_ptr, hi_dst_ptr);
+    }
+
+    gpcdma_clear_error_status(dma_chan);
+    gpcdma_configure_mc_sequencer(dma_chan, xfer, src_io, dst_io);
+    gpcdma_configure_mmio_sequencer(dma_chan, xfer, src_io, dst_io);
+    gpcdma_configure_wcount(dma_chan);
+    dma_chan->busy = true;
+    gpcdma_configure_csr(dma_chan, xfer, dma_mode);
+
+    /*
+     * For the continuous or cyclic mode, next buffer needs to be
+     * programmed right away after CSR.
+     */
+    if (dma_chan->continuous) {
+        ret = gpcdma_program_cycl_mode(xfer, dma_chan, false);
+        if (ret != E_SUCCESS) {
+            goto op_failed;
+        }
+    }
+
+    ret = irq_safe_enable(dma_chan->irq);
+    if (ret != E_SUCCESS) {
+        goto op_failed;
+    }
+
+    /*
+     * For synchronous transfers, the driver relies on the port specific
+     * implementation of some kind of synchronization mechanism until the
+     * DMA transfer is complete.
+     */
+    smp_unlock_irqrestore(dma_chan->lock, &flags);
+    if (dma_chan->callback == NULL) {
+        ret = gpcdma_port_chan_sync(chan_num, xfer->timeout);
+        if (ret != E_SUCCESS) {
+            (void)gpcdma_abort(id, chan_num);
+            dma_chan->busy = false;
+            goto out;
+        }
+    }
+
+op_failed:
+    if (ret != E_SUCCESS) {
+        if (xfer->continuous) {
+            gpcdma_chan_writel(dma_chan, 0UL, GPCDMA_CHANNEL_CH0_CSR_0);
+            gpcdma_port_delete_queue(dma_chan->id);
+        }
+    }
+
+unlock_out:
+    if (ret != E_SUCCESS) {
+        smp_unlock_irqrestore(dma_chan->lock, &flags);
+        dma_chan->busy = false;
+    }
+
+out:
+    return ret;
+}
+
+SECTION_GPCDMA_TEXT error_t
+gpcdma_get_bytes_xferred(const struct gpcdma_id *id,
+                         uint32_t chan_num,
+                         uint64_t *xfer_count)
+{
+    error_t                 ret = E_SUCCESS;
+    struct gpcdma_channel   *dma_chan;
+    uint32_t                flags = 0;
+
+    if (xfer_count == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPCDMA_NULL_PTR;
+        goto out;
+    }
+
+    ret = gpcdma_get_chan_context(id, chan_num, &dma_chan);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    smp_lock_irqsave(dma_chan->lock, &flags);
+    ret = gpcdma_pause(dma_chan);
+    if (ret != E_SUCCESS) {
+        goto unlock_out;
+    }
+
+    if (!dma_chan->continuous) {
+        *xfer_count = gpcdma_chan_readl(dma_chan,
+                                        GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0);
+        *xfer_count = (*xfer_count) * 4ULL;
+    } else {
+        *xfer_count = gpcdma_chan_readl(dma_chan,
+                                        GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0);
+        *xfer_count = dma_chan->words_to_xfer - *xfer_count;
+        *xfer_count = (*xfer_count) * 4ULL;
+        if ((UINT64_MAX - *xfer_count) < dma_chan->total_bytes) {
+            ret = E_GPCDMA_INVALID_PARAM;
+            goto unlock_out;
+        }
+        *xfer_count = (*xfer_count) + dma_chan->total_bytes;
+    }
+
+    gpcdma_resume(dma_chan);
+
+unlock_out:
+    smp_unlock_irqrestore(dma_chan->lock, &flags);
+
+out:
+    return ret;
+}
+
+SECTION_GPCDMA_TEXT error_t
+gpcdma_abort(const struct gpcdma_id *id,
+             uint32_t chan_num)
+{
+    error_t                 ret = E_SUCCESS;
+    struct gpcdma_channel   *dma_chan;
+    uint32_t                flags = 0;
+
+    ret = gpcdma_get_chan_context(id, chan_num, &dma_chan);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    dma_chan->busy = false;
+    smp_lock_irqsave(dma_chan->lock, &flags);
+    if (dma_chan->busy) {
+        /* Disable IRQ and then disable the channel */
+        ret = irq_safe_disable(dma_chan->irq);
+        if (ret != E_SUCCESS) {
+            goto unlock_out;
+        }
+        gpcdma_chan_writel(dma_chan, 0, GPCDMA_CHANNEL_CH0_CSR_0);
+        dma_chan->busy = false;
+
+        /*
+         * This function can be called internally from gpcdma_transfer()
+         * for synchronous xfers, and there's no callback for those.
+         */
+        if (dma_chan->callback != NULL) {
+            dma_chan->callback(dma_chan->cdata, DMA_STATUS_ABORTED);
+        }
+    } else {
+        ret = E_GPCDMA_CHAN_NOT_BUSY;
+    }
+
+unlock_out:
+    smp_unlock_irqrestore(dma_chan->lock, &flags);
+out:
+    return ret;
+}
+
+SECTION_GPCDMA_INIT_TEXT error_t
+gpcdma_init(struct gpcdma_id *id)
+{
+    error_t                 ret = E_SUCCESS;
+    uint32_t                i;
+    struct gpcdma_channel   *dma_chan;
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPCDMA_NULL_PTR;
+        goto out;
+    }
+
+    if ((id->conf.base_addr == 0UL) || (id->conf.base_addr == UINT32_MAX)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPCDMA_INVALID_PARAM;
+        goto out;
+    }
+
+    if (id->inited) {
+        goto out;
+    }
+
+    /* setup per channel attributes */
+    for (i = 0UL; i < ARRAY_SIZE(id->channels); i += 1UL) {
+        dma_chan = id->channels[i];
+
+        dma_chan->chan_base = gpcdma_chan_base(id, i);
+        dma_chan->irq = id->conf.irqs[i];
+        dma_chan->id = i;
+        dma_chan->busy = false;
+        dma_chan->total_bytes = 0;
+        smp_lock_init(dma_chan->lock);
+
+        /* port specific per channel setup hook */
+        ret = gpcdma_port_chan_setup(dma_chan->id);
+
+        if (ret == E_SUCCESS) {
+            ret = irq_safe_set_handler(dma_chan->irq, gpcdma_chan_irq, dma_chan);
+        }
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+
+    }
+
+    /* port specific GPCDMA controller setup hook */
+    ret = gpcdma_port_init(id);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    /**
+     * WAR for HW Bug 200667678: Disable virtualization for GPCDMA and
+     * cluster DMAs out of reset.
+     */
+#if defined(HW_BUG_200667678) && (HW_BUG_200667678 == 1)
+    gpcdma_disable_virtualization(id);
+#endif
+
+    id->inited = true;
+
+out:
+    return ret;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_8, "Approval: Bug 200534384, DR: SWE-FSP-011-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/gpcdma/module-gpcdma-config.mk b/spe-freertos-bsp/fsp/source/drivers/gpcdma/module-gpcdma-config.mk
new file mode 100644
index 0000000..2edf015
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/gpcdma/module-gpcdma-config.mk
@@ -0,0 +1,54 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-gpcdma-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to
+#   VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_GPCDMA_CONFIG                := 1
+
+#
+# Define a something similar to header guard protection...for makefiles
+# instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_GPCDMA_DEFINED               := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_GPCDMA_DEPENDS               := SOC CLUSTER CPL
+$(foreach _,$(MODULE_GPCDMA_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_GPCDMA_DRIVERS_DIR            = $(FSP_COMMON_REPO)/drivers/gpcdma
+MODULE_GPCDMA_SOURCE_DIR             = $(MODULE_GPCDMA_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_GPCDMA_INCLUDES               =
diff --git a/spe-freertos-bsp/fsp/source/drivers/gpcdma/module-gpcdma.mk b/spe-freertos-bsp/fsp/source/drivers/gpcdma/module-gpcdma.mk
new file mode 100644
index 0000000..c8f5411
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/gpcdma/module-gpcdma.mk
@@ -0,0 +1,70 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-gpcdma.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to
+#   VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_GPCDMA_NAME                  := GPCDMA
+
+#
+# Define a something similar to header guard protection...for makefiles
+# instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_GPCDMA_DEFINED               := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_GPCDMA_DEPENDS               := GPCDMA SOC CPL
+$(foreach _,$(CONFIG_GPCDMA_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_GPCDMA_C_SRC                  =
+MODULE_GPCDMA_C_SRC                 += $(MODULE_GPCDMA_DRIVERS_DIR)/gpcdma.c
+MODULE_GPCDMA_C_SRC                 += $(CPL_SOC_IDS)/gpcdma-ids.c
+
+#
+# If the client module does not need 'gpcdma-port.c' use this MAKEFILE flag to
+# ignore it.
+MODULE_GPCDMA_C_SRC                 += $(CPL_SOC_PORT)/gpcdma-port.c
+
+#
+# Assembly source
+MODULE_GPCDMA_ASM_SRC                =
+MODULE_GPCDMA_ASM_SRC               += $(CPL_SOC_PORT)/gpcdma-irq.S
+
+#
+# Special C Flags
+MODULE_GPCDMA_C_FLAGS                =
+
+#
+# Special ASM Flags
+MODULE_GPCDMA_ASM_FLAGS              =
diff --git a/spe-freertos-bsp/fsp/source/drivers/gpio/module-gpio-config.mk b/spe-freertos-bsp/fsp/source/drivers/gpio/module-gpio-config.mk
new file mode 100644
index 0000000..ca5c0c0
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/gpio/module-gpio-config.mk
@@ -0,0 +1,54 @@
+#
+# Copyright (c) 2020 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-gpio-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to
+#   VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_GPIO_CONFIG            := 1
+
+#
+# Define a something similar to header guard protection...for makefiles
+# instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_GPIO_DEFINED           := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_GPIO_DEPENDS           := SOC CLUSTER CPL
+$(foreach _,$(MODULE_GPIO_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_GPIO_DRIVERS_DIR       = $(FSP_COMMON_REPO)/drivers/gpio
+MODULE_GPIO_SOURCE_DIR        = $(MODULE_GPIO_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_GPIO_INCLUDES          =
diff --git a/spe-freertos-bsp/fsp/source/drivers/gpio/module-gpio.mk b/spe-freertos-bsp/fsp/source/drivers/gpio/module-gpio.mk
new file mode 100644
index 0000000..6b93664
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/gpio/module-gpio.mk
@@ -0,0 +1,71 @@
+#
+# Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-gpio.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to
+#   VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_GPIO_NAME                := GPIO
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_GPIO_DEFINED             := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_GPIO_DEPENDS             := GPIO SOC CPL
+$(foreach _,$(CONFIG_GPIO_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_GPIO_C_SRC                =
+MODULE_GPIO_C_SRC               += $(MODULE_GPIO_DRIVERS_DIR)/tegra-gpio.c
+MODULE_GPIO_C_SRC               += $(CPL_SOC_IDS)/gpio-tegra-ids.c
+ifeq ($(SOC),t234)
+    MODULE_GPIO_C_SRC           += $(CPL_SOC_IDS)/gpio-main-tegra-ids.c
+    MODULE_GPIO_C_SRC           += $(CPL_SOC_IDS)/gpio-aon-tegra-ids.c
+endif
+ifeq ($(SOC),t239)
+    MODULE_GPIO_C_SRC           += $(CPL_SOC_IDS)/gpio-main-tegra-ids.c
+    MODULE_GPIO_C_SRC           += $(CPL_SOC_IDS)/gpio-aon-tegra-ids.c
+endif
+
+#
+# Assembly source
+MODULE_GPIO_ASM_SRC              =
+
+#
+# Special C Flags
+MODULE_GPIO_C_FLAGS              =
+
+#
+# Special ASM Flags
+MODULE_GPIO_ASM_FLAGS            =
diff --git a/spe-freertos-bsp/fsp/source/drivers/gpio/tegra-gpio.c b/spe-freertos-bsp/fsp/source/drivers/gpio/tegra-gpio.c
new file mode 100644
index 0000000..f312e36
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/gpio/tegra-gpio.c
@@ -0,0 +1,1268 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
+ *
+ * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
+ * property and proprietary rights in and to this material, related
+ * documentation and any modifications thereto. Any use, reproduction,
+ * disclosure or distribution of this material and related documentation
+ * without an express license agreement from NVIDIA CORPORATION or
+ * its affiliates is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                        //for uint32_t
+#include <stddef.h>                        //for NULL
+#include <stdbool.h>                       //for bool
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+#include <soc-common/hw-const.h>           // for MK_U32_CONSTANT
+
+/* Hardware headers */
+#include <argpio_sw.h>                     // for GPIO_A_ENABLE_CONFIG_00_0...
+
+/* Late FSP headers */
+#include <reg-access/reg-access.h>         // for readl_base_offset, writel_base_offset
+#include <irq/safe-irqs.h>                      // for irq_safe_enable, irq_safe_set_handler, ...
+#include <misc/bitops.h>                   // for BIT, BIT32, bit_number
+#include <misc/macros.h>                   // for START_RFD_BLOCk, END_RFD_BLOCK, INLINE_RFD
+#include <error/common-errors.h>           // for E_SUCCESS, error_t
+#include <misc/nvrm_drf.h>                 // for NV_FLD_SET_DRF_NUM, NV_DRF_NUM
+
+/* Module headers */
+#include <gpio/gpio-error.h>               // For E_GPIO_INVALID_GPIO_IRQ,E_GPIO_INVALID_IRQ_HANDLER
+#include <gpio/sections-gpio.h>            // Immune from CT_ASSERT protection
+#include <gpio/tegra-gpio.h>               // For tegra_gpio_direction_in.....
+#include <gpio/tegra-gpio-priv.h>          // For struct tegra_gpio_id....
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__NVRM_DRF_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPIO__GPIO_ERROR_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPIO__TEGRA_GPIO_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPIO__TEGRA_GPIO_PRIV_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+#endif
+
+/**
+ * @defgroup PRIVATE_DATA
+ * @{
+ */
+/** Maximum number of IRQ types supported by the GPIO */
+#define TEGRA_GPIO_IRQ_TYPES    0x4U
+/** Maximum number of IRQ levels supported by the GPIO */
+#define TEGRA_GPIO_IRQ_LEVELS   0x2U
+
+/* Static global variables saving copy of GPIO SoC data and
+number of controllers registered */
+static struct tegra_gpio_id **ctrls;
+/** Variable to store number of controllers requested by the client */
+static uint32_t nctrls;
+
+/** Default mask for bank gpio IRQ */
+#define TEGRA_GPIO_IRQ_MASK    0xFFUL
+/** @} */
+
+
+/**
+ * @defgroup PRIVATE_API
+ * @{
+ */
+/**
+ * @brief Extract a GPIO controller ID from a global GPIO ID.
+ *
+ * No error-range-checking is performed on the parameters or returned value.
+ *
+ * @param[in] global_id    The global ID of the GPIO.
+ *
+ * @retval ctrl_id The GPIO controller ID.
+ */
+static inline uint32_t gpio_ctrl_id_of_global_id(uint32_t global_id)
+{
+    return global_id >> 16;
+}
+
+/**
+ * @brief Extract a controller-relative GPIO ID from a global GPIO ID.
+ *
+ * No error-range-checking is performed on the parameters or returned value.
+ *
+ * @param[in] global_id    The global ID of the GPIO.
+ *
+ * @retval gpio_id The controller-relative GPIO ID of the GPIO.
+ */
+static inline uint32_t gpio_gpio_id_of_global_id(uint32_t global_id)
+{
+    return global_id & 0xffffUL;
+}
+
+/**
+ * @brief Check if the input GPIO is valid
+ *
+ * @param[in] id   Pointer to GPIO controller data
+ * @param[in] gpio Input GPIO number local to the controller
+ *
+ * @retval true  GPIO is valid
+ * @retval false GPIO is invalid
+ */
+
+static inline bool gpio_valid(const struct tegra_gpio_id *id,
+                              uint32_t gpio)
+{
+    uint32_t bank = gpio >> MK_U32_CONST(3);
+    uint32_t gpio_id = gpio % GPIOS_PER_BANK;
+
+    return (bank < id->bank_count) && (gpio_id < id->num_pins[bank]);
+}
+
+/**
+ * @brief Generate GPIO register address.
+ *
+ * @param[in] id Pointer  GPIO controller data
+ * @param[in] bank_gpio   Local GPIO number
+ * @param[in] gpio_regnum Offset of GPIO configuration register relative to
+ *                        GPIO_N_ENABLE_CONFIG_00_0
+ *
+ * @retval u32_value Absolute address of the GPIO register
+ */
+static inline uint32_t gpio_reg(const struct tegra_gpio_id *id,
+                           uint32_t bank_gpio,
+                           uint32_t gpio_regnum)
+{
+    uint32_t bank = bank_gpio / GPIOS_PER_BANK;
+    uint32_t gpio = bank_gpio % GPIOS_PER_BANK;
+    uint32_t bank_base = id->bank_bases[bank];
+
+    INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-449, Example-1, Example-3, DR: SWE-FSP-045-SWSADR.docx");
+    return id->base_addr + bank_base + (gpio_regnum - GPIO_A_ENABLE_CONFIG_00_0) +
+        (gpio * (GPIO_A_ENABLE_CONFIG_01_0 - GPIO_A_ENABLE_CONFIG_00_0));
+}
+/** @} */
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_enable_irq(uint32_t gpio)
+{
+    uint32_t                   ctrl_id = gpio_ctrl_id_of_global_id(gpio);
+    uint32_t                   gpio_id = gpio_gpio_id_of_global_id(gpio);
+    uint32_t                   gpio_bank;
+    uint32_t                   gpio_pin;
+    uint32_t                   val, out_en;
+    const struct tegra_gpio_id *id;
+    error_t                    err = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+    id = ctrls[ctrl_id];
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (!gpio_valid(id, gpio_id)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    out_en = NV_DRF_VAL(GPIO, A_ENABLE_CONFIG_00, IN_OUT, val);
+    /* Return error if GPIO is configured for output mode */
+    if (out_en != 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CFQ_REQ;
+        goto out;
+    }
+
+    gpio_bank = gpio_id / GPIOS_PER_BANK;
+    gpio_pin = gpio_id % GPIOS_PER_BANK;
+
+    if (id->isr_status == true) {
+        if ((id->irqs == NULL) || (id->nirqs == 0U)) {
+            INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+            err = E_GPIO_INVALID_GPIO_IRQ;
+            goto out;
+        } else if (id->irq_handlers[gpio_id].handler == NULL) {
+            INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+            err = E_GPIO_INVALID_IRQ_HANDLER;
+            goto out;
+        } else {
+            id->bank_irq_status[gpio_bank] |= (uint8_t)((1UL << gpio_pin) & TEGRA_GPIO_IRQ_MASK);
+        }
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    val |= NV_DRF_DEF(GPIO, A_ENABLE_CONFIG_00, INTERRUPT_FUNCTION, ENABLE);
+    writel(val, gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+
+out:
+    return err;
+}
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_enable_timestamp(uint32_t gpio)
+{
+    uint32_t                   ctrl_id = gpio_ctrl_id_of_global_id(gpio);
+    uint32_t                   gpio_id = gpio_gpio_id_of_global_id(gpio);
+    uint32_t                   val, out_en;
+    const struct tegra_gpio_id *id;
+    error_t                    err = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (!gpio_valid(id, gpio_id)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    out_en = NV_DRF_VAL(GPIO, A_ENABLE_CONFIG_00, IN_OUT, val);
+    /* Return error if GPIO is configured for output mode */
+    if (out_en != 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CFQ_REQ;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    val |= NV_DRF_DEF(GPIO, A_ENABLE_CONFIG_00, TIMESTAMPING_FUNCTION, ENABLE);
+    writel(val, gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+
+out:
+    return err;
+}
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_disable_timestamp(uint32_t gpio)
+{
+    uint32_t                   ctrl_id = gpio_ctrl_id_of_global_id(gpio);
+    uint32_t                   gpio_id = gpio_gpio_id_of_global_id(gpio);
+    uint32_t     val;
+    const struct tegra_gpio_id *id;
+    error_t      err = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (!gpio_valid(id, gpio_id)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    val &= ~NV_DRF_DEF(GPIO, A_ENABLE_CONFIG_00, TIMESTAMPING_FUNCTION, ENABLE);
+    writel(val, gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+
+out:
+    return err;
+}
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_disable_irq(uint32_t gpio)
+{
+    uint32_t                   ctrl_id = gpio_ctrl_id_of_global_id(gpio);
+    uint32_t                   gpio_id = gpio_gpio_id_of_global_id(gpio);
+    uint32_t                   gpio_bank;
+    uint32_t                   gpio_pin;
+    uint32_t     val;
+    const struct tegra_gpio_id *id;
+    error_t      err = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (!gpio_valid(id, gpio_id)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO;
+        goto out;
+    }
+
+    gpio_bank = gpio_id / GPIOS_PER_BANK;
+    gpio_pin = gpio_id % GPIOS_PER_BANK;
+
+    if (id->isr_status == true) {
+        if ((id->irqs == NULL) || (id->nirqs == 0U)) {
+            INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+            err = E_GPIO_INVALID_GPIO_IRQ;
+            goto out;
+        } else if (id->irq_handlers[gpio_id].handler == NULL) {
+            INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+            err = E_GPIO_INVALID_IRQ_HANDLER;
+            goto out;
+        } else {
+            id->bank_irq_status[gpio_bank] &= (uint8_t)((uint32_t)(~(1UL << gpio_pin))
+                                                 & TEGRA_GPIO_IRQ_MASK);
+        }
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    val &= ~NV_DRF_DEF(GPIO, A_ENABLE_CONFIG_00, INTERRUPT_FUNCTION, ENABLE);
+    writel(val, gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+
+out:
+    return err;
+}
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_set_irq_type(uint32_t gpio,
+                                tegra_gpio_irq_type type,
+                                tegra_gpio_irq_level level)
+{
+    uint32_t                   ctrl_id = gpio_ctrl_id_of_global_id(gpio);
+    uint32_t                   gpio_id = gpio_gpio_id_of_global_id(gpio);
+    uint32_t     val, out_en;
+    const struct tegra_gpio_id *id;
+    error_t      err = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (!gpio_valid(id, gpio_id)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    out_en = NV_DRF_VAL(GPIO, A_ENABLE_CONFIG_00, IN_OUT, val);
+    /* Return error if GPIO is configured for output mode */
+    if (out_en != 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CFQ_REQ;
+        goto out;
+    }
+
+    if (level >= TEGRA_GPIO_IRQ_LEVELS) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_IRQ_LEVEL;
+        goto out;
+    }
+
+     if(type >= TEGRA_GPIO_IRQ_TYPES) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_IRQ_TYPE;
+        goto out;
+     }
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    val = NV_FLD_SET_DRF_NUM(GPIO, A_ENABLE_CONFIG_00, TRIGGER_LEVEL,
+                             level, val);
+    val = NV_FLD_SET_DRF_NUM(GPIO, A_ENABLE_CONFIG_00, TRIGGER_TYPE,
+                             type, val);
+    writel(val, gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+
+out:
+    return err;
+}
+
+/**
+ * @addtogroup PRIVATE_API
+ * @{
+ */
+/**
+ * @brief Clear interrupt on GPIO
+ *
+ * @param[in] id   Input GPIO controller data
+ * @param[in] gpio Local GPIO number
+ *
+ * @retval None
+ */
+SECTION_GPIO_TEXT
+static void tegra_gpio_clear_irq(const struct tegra_gpio_id *id,
+                                 uint32_t gpio)
+{
+    uint32_t val;
+
+    val = NV_DRF_DEF(GPIO, A_INTERRUPT_CLEAR_00, GPIO_INTERRUPT_CLEAR, CLEAR);
+    writel(val, gpio_reg(id, gpio, GPIO_A_INTERRUPT_CLEAR_00_0));
+}
+/** @} */
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_clear_irq_status(uint32_t gpio)
+{
+    uint32_t                   ctrl_id = gpio_ctrl_id_of_global_id(gpio);
+    uint32_t                   gpio_id = gpio_gpio_id_of_global_id(gpio);
+    const struct tegra_gpio_id *id;
+    uint32_t val, out_en;
+    error_t      err = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (!gpio_valid(id, gpio_id)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    out_en = NV_DRF_VAL(GPIO, A_ENABLE_CONFIG_00, IN_OUT, val);
+    /* Return error if GPIO is configured for output mode */
+    if (out_en != 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CFQ_REQ;
+        goto out;
+    }
+
+    tegra_gpio_clear_irq(id, gpio_id);
+
+out:
+    return err;
+}
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_read_irq_status(uint32_t gpio, bool *irq_status)
+{
+    uint32_t                   ctrl_id = gpio_ctrl_id_of_global_id(gpio);
+    uint32_t                   gpio_id = gpio_gpio_id_of_global_id(gpio);
+    uint32_t                   gpio_pin = gpio_id % GPIOS_PER_BANK;
+    uint32_t                   gpio_bank = gpio_id / GPIOS_PER_BANK;
+    uint32_t                   val, out_en;
+    const struct tegra_gpio_id *id;
+    error_t      err = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (irq_status == NULL) {
+        err = E_GPIO_NULL_INPUT_PARAMETER;
+        goto out;
+    }
+
+    if (!gpio_valid(id, gpio_id)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    out_en = NV_DRF_VAL(GPIO, A_ENABLE_CONFIG_00, IN_OUT, val);
+    /* Return error if GPIO is configured for output mode */
+    if (out_en != 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CFQ_REQ;
+        goto out;
+    }
+
+    INLINE_RFD(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx", CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    val = readl(id->base_addr + id->bank_bases[gpio_bank] + id->irq_status_offset);
+    *irq_status = ((val & (1UL << gpio_pin)) != 0U);
+
+out:
+    return err;
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_GPIO_TEXT void tegra_gpio_irq_handler(void *data)
+{
+    const struct tegra_gpio_id *id;
+    uint32_t             bank;
+    uint32_t             gpio;
+    uint32_t             val;
+
+    if (data == NULL) {
+        goto irq_exit;
+    }
+
+    INLINE_RFD(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx");
+    id = (struct tegra_gpio_id const *)data;
+    for (bank = 0; bank < id->bank_count; bank++) {
+        if (id->bank_irq_status[bank] == 0U) {
+               continue;
+        }
+        INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-449, Example-1, Example-3, DR: SWE-FSP-045-SWSADR.docx");
+        val = readl(id->base_addr + id->bank_bases[bank] + id->irq_status_offset);
+        while (val != 0UL) {
+            gpio = bit_number(val);
+            val &= ~BIT32_FN(gpio);
+            INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-449, Example-3, DR: SWE-FSP-045-SWSADR.docx");
+            gpio += bank * GPIOS_PER_BANK;
+            tegra_gpio_clear_irq(id, gpio);
+            if (id->irq_handlers[gpio].handler != NULL) {
+                id->irq_handlers[gpio].handler(
+                        id->irq_handlers[gpio].data);
+            }
+        }
+    }
+
+irq_exit:
+    return;
+}
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_set_irq_handler(uint32_t gpio,
+                                          void (*handler)(void *hdata),
+                                          void *data)
+{
+    uint32_t             ctrl_id = gpio_ctrl_id_of_global_id(gpio);
+    uint32_t             gpio_id = gpio_gpio_id_of_global_id(gpio);
+    const struct tegra_gpio_id *id;
+    uint32_t val, out_en;
+    error_t              err = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (!gpio_valid(id, gpio_id)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    out_en = NV_DRF_VAL(GPIO, A_ENABLE_CONFIG_00, IN_OUT, val);
+    /* Return error if GPIO is configured for output mode */
+    if (out_en != 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CFQ_REQ;
+        goto out;
+    }
+
+    if ((id->irqs == NULL) || (id->nirqs == 0U)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_IRQ;
+        goto out;
+    }
+
+    if (handler == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_IRQ_HANDLER;
+        goto out;
+    }
+    enter_critical();
+    id->irq_handlers[gpio_id].handler = handler;
+    id->irq_handlers[gpio_id].data = data;
+    exit_critical();
+
+out:
+    return err;
+}
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_clear_irq_handler(uint32_t gpio)
+{
+    uint32_t             ctrl_id = gpio_ctrl_id_of_global_id(gpio);
+    uint32_t             gpio_id = gpio_gpio_id_of_global_id(gpio);
+    const struct tegra_gpio_id *id;
+    uint32_t             val;
+    uint32_t             irq_en;
+    error_t              err = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (!gpio_valid(id, gpio_id)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO;
+        goto out;
+    }
+
+    if ((id->irqs == NULL) || (id->nirqs == 0U)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_IRQ;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    irq_en = NV_DRF_VAL(GPIO, A_ENABLE_CONFIG_00, INTERRUPT_FUNCTION, val);
+    if (irq_en != 0UL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_IRQ;
+        goto out;
+    }
+    enter_critical();
+    id->irq_handlers[gpio_id].handler = NULL;
+    id->irq_handlers[gpio_id].data = NULL;
+    exit_critical();
+
+out:
+    return err;
+}
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_set_debounce(uint32_t gpio,
+                                uint32_t debounce_ms)
+{
+    uint32_t                   ctrl_id = gpio_ctrl_id_of_global_id(gpio);
+    uint32_t                   gpio_id = gpio_gpio_id_of_global_id(gpio);
+    uint32_t                   val = 0UL, out_en;
+    const struct tegra_gpio_id *id;
+    error_t                    err = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (!gpio_valid(id, gpio_id)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    out_en = NV_DRF_VAL(GPIO, A_ENABLE_CONFIG_00, IN_OUT, val);
+    /* Return error if GPIO is configured for output mode */
+    if (out_en != 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CFQ_REQ;
+        goto out;
+    }
+
+    if (debounce_ms == 0UL) {
+        val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+        val &= ~NV_DRF_DEF(GPIO, A_ENABLE_CONFIG_00, DEBOUNCE_FUNCTION, ENABLE);
+        writel(val, gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+        goto out;
+    }
+
+    val |= NV_DRF_NUM(GPIO, A_DEBOUNCE_THRESHOLD_00, DEBOUNCE_THRESHOLD, debounce_ms);
+    writel(val, gpio_reg(id, gpio_id, GPIO_A_DEBOUNCE_THRESHOLD_00_0));
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    val |= NV_DRF_DEF(GPIO, A_ENABLE_CONFIG_00, DEBOUNCE_FUNCTION, ENABLE);
+    writel(val, gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+
+out:
+    return err;
+}
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_direction_in(uint32_t gpio)
+{
+    uint32_t                   ctrl_id = gpio_ctrl_id_of_global_id(gpio);
+    uint32_t                   gpio_id = gpio_gpio_id_of_global_id(gpio);
+    uint32_t                   val;
+    const struct tegra_gpio_id *id;
+    error_t                    err = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (!gpio_valid(id, gpio_id)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    val |=
+        NV_DRF_DEF(GPIO, A_ENABLE_CONFIG_00, GPIO_ENABLE, ENABLE) |
+        NV_DRF_DEF(GPIO, A_ENABLE_CONFIG_00, IN_OUT, IN);
+    writel(val, gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+
+out:
+    return err;
+}
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_direction_out(uint32_t gpio,
+                                 bool value)
+{
+    uint32_t                   ctrl_id = gpio_ctrl_id_of_global_id(gpio);
+    uint32_t                   gpio_id = gpio_gpio_id_of_global_id(gpio);
+    uint32_t                   val, irq_en, tms_en;
+    const struct tegra_gpio_id *id;
+    error_t                    err = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (!gpio_valid(id, gpio_id)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    irq_en = NV_DRF_VAL(GPIO, A_ENABLE_CONFIG_00, INTERRUPT_FUNCTION, val);
+    tms_en = NV_DRF_VAL(GPIO, A_ENABLE_CONFIG_00, TIMESTAMPING_FUNCTION, val);
+
+    /* Return error if interrupt or timestamping function is enabled for the GPIO */
+    if ((irq_en != 0U) || (tms_en != 0U)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CFQ_REQ;
+        goto out;
+    }
+
+    val =
+        NV_DRF_NUM(GPIO, A_OUTPUT_VALUE_00, GPIO_OUT_VAL, value ? 1UL : 0UL);
+    writel(val, gpio_reg(id, gpio_id, GPIO_A_OUTPUT_VALUE_00_0));
+
+    val =
+        NV_DRF_DEF(GPIO, A_OUTPUT_CONTROL_00, GPIO_OUT_CONTROL, DRIVEN);
+    writel(val, gpio_reg(id, gpio_id, GPIO_A_OUTPUT_CONTROL_00_0));
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    val |=
+        NV_DRF_DEF(GPIO, A_ENABLE_CONFIG_00, GPIO_ENABLE, ENABLE) |
+        NV_DRF_DEF(GPIO, A_ENABLE_CONFIG_00, IN_OUT, OUT);
+    writel(val, gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+
+out:
+    return err;
+}
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_get_direction(uint32_t gpio, uint32_t *gpio_dir)
+{
+    uint32_t                   ctrl_id = gpio_ctrl_id_of_global_id(gpio);
+    uint32_t                   gpio_id = gpio_gpio_id_of_global_id(gpio);
+    uint32_t                   val;
+    const struct tegra_gpio_id *id;
+    error_t                    err = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (gpio_dir == NULL) {
+        err = E_GPIO_NULL_INPUT_PARAMETER;
+        goto out;
+    }
+
+    if (!gpio_valid(id, gpio_id)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    *gpio_dir = NV_DRF_VAL(GPIO, A_ENABLE_CONFIG_00, IN_OUT, val);
+
+out:
+    return err;
+}
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_get_output_value(uint32_t gpio,
+                                    bool *gpio_val)
+{
+    uint32_t                   ctrl_id = gpio_ctrl_id_of_global_id(gpio);
+    uint32_t                   gpio_id = gpio_gpio_id_of_global_id(gpio);
+    uint32_t                   val;
+    uint32_t                   gpio_cfg;
+    const struct tegra_gpio_id *id;
+    error_t                    ret = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (gpio_val == NULL) {
+        ret = E_GPIO_NULL_INPUT_PARAMETER;
+        goto out;
+    }
+
+    if (!gpio_valid(id, gpio_id)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPIO_INVALID_GPIO;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    gpio_cfg = NV_DRF_VAL(GPIO, A_ENABLE_CONFIG_00, IN_OUT, val);
+    if (gpio_cfg == 0UL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPIO_INVALID_CFQ_REQ;
+    }
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_OUTPUT_VALUE_00_0));
+
+    *gpio_val = NV_DRF_VAL(GPIO, A_OUTPUT_VALUE_00, GPIO_OUT_VAL, val) != 0U;
+
+out:
+    return ret;
+}
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_get_input_value(uint32_t gpio,
+                                   bool     *gpio_val)
+{
+    uint32_t                   ctrl_id = gpio_ctrl_id_of_global_id(gpio);
+    uint32_t                   gpio_id = gpio_gpio_id_of_global_id(gpio);
+    uint32_t                   val, out_en;
+    const struct tegra_gpio_id *id;
+    error_t                    ret = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (gpio_val == NULL) {
+        ret = E_GPIO_NULL_INPUT_PARAMETER;
+        goto out;
+    }
+
+    if (!gpio_valid(id, gpio_id)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPIO_INVALID_GPIO;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    out_en = NV_DRF_VAL(GPIO, A_ENABLE_CONFIG_00, IN_OUT, val);
+    /* Return error if GPIO is configured for output mode */
+    if (out_en != 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_GPIO_INVALID_CFQ_REQ;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_INPUT_00_0));
+
+    *gpio_val = NV_DRF_VAL(GPIO, A_INPUT_00, GPIO_IN, val) != 0U;
+
+out:
+    return ret;
+}
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_get_value(uint32_t gpio,
+                             bool *gpio_val)
+{
+    uint32_t                   ctrl_id = gpio_ctrl_id_of_global_id(gpio);
+    uint32_t                   gpio_id = gpio_gpio_id_of_global_id(gpio);
+    uint32_t                   val;
+    uint32_t                   gpio_cfg;
+    const struct tegra_gpio_id *id;
+    error_t                    err = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (gpio_val == NULL) {
+        err = E_GPIO_NULL_INPUT_PARAMETER;
+        goto out;
+    }
+
+    if (!gpio_valid(id, gpio_id)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    gpio_cfg = NV_DRF_VAL(GPIO, A_ENABLE_CONFIG_00, IN_OUT, val);
+    if (gpio_cfg == 0UL) {
+        val = readl(gpio_reg(id, gpio_id, GPIO_A_INPUT_00_0));
+        *gpio_val = NV_DRF_VAL(GPIO, A_INPUT_00, GPIO_IN, val) != 0U;
+    } else {
+        val = readl(gpio_reg(id, gpio_id, GPIO_A_OUTPUT_VALUE_00_0));
+        *gpio_val = NV_DRF_VAL(GPIO, A_OUTPUT_VALUE_00, GPIO_OUT_VAL, val) != 0U;
+    }
+
+out:
+    return err;
+}
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_set_value(uint32_t gpio,
+                             bool value)
+{
+    uint32_t                   ctrl_id = gpio_ctrl_id_of_global_id(gpio);
+    uint32_t                   gpio_id = gpio_gpio_id_of_global_id(gpio);
+    uint32_t                   val, out_en;
+    const struct tegra_gpio_id *id;
+    error_t                    err = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (!gpio_valid(id, gpio_id)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO;
+        goto out;
+    }
+
+    val = readl(gpio_reg(id, gpio_id, GPIO_A_ENABLE_CONFIG_00_0));
+    out_en = NV_DRF_VAL(GPIO, A_ENABLE_CONFIG_00, IN_OUT, val);
+    /* Return error if GPIO is configured for input mode */
+    if (out_en == 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CFQ_REQ;
+        goto out;
+    }
+
+    val =
+        NV_DRF_NUM(GPIO, A_OUTPUT_VALUE_00, GPIO_OUT_VAL, value ? 1UL : 0UL);
+    writel(val, gpio_reg(id, gpio_id, GPIO_A_OUTPUT_VALUE_00_0));
+
+out:
+    return err;
+}
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_suspend(uint32_t ctrl_id)
+{
+    struct tegra_gpio_id       const *id;
+    uint32_t                   i;
+    error_t                    err = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if ((id->irqs == NULL) || (id->nirqs == 0U)) {
+        goto out;
+    }
+
+    for (i = 0UL; i < id->nirqs; i++) {
+        if (id->irqs[i] == UINT32_MAX) {
+            INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+            err = E_GPIO_INVALID_GPIO_IRQ;
+        }
+        if (err == E_SUCCESS) {
+            err = irq_safe_disable(id->irqs[i]);
+        }
+        if (err != E_SUCCESS) {
+            break;
+        }
+    }
+
+out:
+    return err;
+}
+
+SECTION_GPIO_TEXT
+error_t tegra_gpio_resume(uint32_t ctrl_id)
+{
+    struct tegra_gpio_id       const *id;
+    uint32_t                   i;
+    error_t                    err = E_SUCCESS;
+
+    if (ctrl_id >= nctrls) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_GPIO_CTRL_ID;
+        goto out;
+    }
+
+    id = ctrls[ctrl_id];
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if ((id->irqs == NULL) || (id->nirqs == 0U)) {
+        goto out;
+    }
+
+    for (i = 0UL; i < id->nirqs; i++) {
+        if (id->irqs[i] == UINT32_MAX) {
+            INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+            err = E_GPIO_INVALID_GPIO_IRQ;
+        }
+        if (err == E_SUCCESS) {
+            err = irq_safe_disable(id->irqs[i]);
+        }
+        if (err != E_SUCCESS) {
+            break;
+        }
+    }
+
+out:
+    return err;
+}
+
+/**
+ * @addtogroup PRIVATE_API
+ * @{
+ */
+/**
+ * @brief Register input GPIO controller to the driver
+ *
+ * @param[in] id Input GPIO controller data
+ *
+ * @retval E_GPIO_INVALID_CTRL_DATA NULL/Invalid controller data
+ * @retval E_GPIO_INVALID_GPIO_IRQ  Invalid controller IRQ data
+ * @retval E_VIC_INVALID_VECTOR     Invalid controller IRQ mapped to VIC.
+ * @retval E_SUCCESS                Input GPIO controller registered successfully
+ */
+SECTION_GPIO_INIT_TEXT
+static error_t tegra_gpio_do_init(struct tegra_gpio_id *id)
+{
+    uint32_t             i;
+    error_t              err = E_SUCCESS;
+
+    if ((id == NULL) || (id->bank_bases == NULL) || (id->num_pins == NULL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    if (!id->isr_status) {
+        goto out;
+    }
+
+    if ((id->irqs == NULL) || (id->nirqs == 0U) || (id->irq_handlers == NULL) ||
+        (id->bank_irq_status == NULL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    for (i = 0UL; i < id->nirqs; i++) {
+        if (id->irqs[i] == UINT32_MAX) {
+            INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+            err = E_GPIO_INVALID_GPIO_IRQ;
+        }
+        if (err == E_SUCCESS) {
+            err = irq_safe_set_handler(id->irqs[i], tegra_gpio_irq_handler, id);
+        }
+        if (err == E_SUCCESS) {
+            err = irq_safe_enable(id->irqs[i]);
+        }
+        if (err != E_SUCCESS) {
+            break;
+        }
+    }
+
+out:
+    return err;
+}
+/** @} */
+
+SECTION_GPIO_INIT_TEXT
+error_t tegra_gpio_init(struct tegra_gpio_id **ids, uint32_t num_ctrls)
+{
+    uint32_t             i;
+    error_t              err = E_SUCCESS;
+
+    if (ids == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_NULL_INPUT_PARAMETER;
+        goto out;
+    }
+
+    if (num_ctrls > MAX_GPIO_CONTROLLERS) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_GPIO_INVALID_CTRL_DATA;
+        goto out;
+    }
+
+    ctrls = ids;
+    nctrls = num_ctrls;
+
+    for (i = 0U; i < nctrls; i++) {
+        err = tegra_gpio_do_init(ctrls[i]);
+        if (err != E_SUCCESS) {
+            break;
+        }
+    }
+
+out:
+    return err;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/hsp/hsp-tegra-dummy-isr-sm-128.c b/spe-freertos-bsp/fsp/source/drivers/hsp/hsp-tegra-dummy-isr-sm-128.c
new file mode 100644
index 0000000..d9eccd5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/hsp/hsp-tegra-dummy-isr-sm-128.c
@@ -0,0 +1,79 @@
+_Pragma("coverity compliance block(include) \
+         (deviate MISRA_C_2012_Rule_1_2 \"Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx\") \
+         (deviate MISRA_C_2012_Directive_4_8 \"Approval: Bug 200534384, DR: SWE-FSP-011-SWSADR.docx\")")
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                 // for uint32_t, uint8_t, UINT8_MAX, UIN...
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>         // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>        // for UNUSED, WEAK
+#include <misc/macros.h>            // for END_RFD_BLOCK, START_RFD_BLOCK
+
+
+/* Module-specific FSP headers */
+#include <hsp/hsp-tegra.h>           // for tegra_hsp_suspend_ctx, FSP__HSP__...
+#include <hsp/sections-hsp.h>        // Immune from CT_ASSERT protection
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HSP__HSP_TEGRA_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+// IWYU pragma: no_forward_declare tegra_hsp_id
+/* Dummy implementation for SOCs without 128-bit mailbox support */
+SECTION_HSP_TEXT void
+tegra_hsp_sm128_irq_handler(const struct tegra_hsp_id *id,
+                            uint32_t sm)
+{
+    UNUSED((id));
+    UNUSED((sm));
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_8, "Approval: Bug 200534384, DR: SWE-FSP-011-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/hsp/hsp-tegra-sm-128.c b/spe-freertos-bsp/fsp/source/drivers/hsp/hsp-tegra-sm-128.c
new file mode 100644
index 0000000..dedb7ec
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/hsp/hsp-tegra-sm-128.c
@@ -0,0 +1,317 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                // for bool, false
+#include <stddef.h>                 // for NULL
+#include <stdint.h>                 // for uint32_t, uint8_t, UINT8_MAX, UIN...
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>         // for CT_ASSERT
+#include <soc-common/hw-const.h>    /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>        // for NV_ADDRESS_MAP_TOP0_HSP_COMMON_SIZE
+#include <arhsp_shrd_mbox.h>        // for HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0...
+
+/* Late FSP headers */
+#include <error/common-errors.h>    // for E_SUCCESS, error_t
+#include <misc/bitops.h>            // for BIT, bit_number, FSP__MISC__BITOPS_H
+#include <misc/macros.h>            // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <reg-access/reg-access.h>  // for readl_base_offset, writel_base_of...
+
+/* Module-specific FSP headers */
+#include <hsp/hsp-errors.h>          // for E_HSP_ERR_NULL_PTR, E_HSP_ERR_NO_...
+#include <hsp/hsp-tegra-defs.h>      // for HSP_COMMON_SIZE, HSP_DBELL_OFFSET...
+#include <hsp/hsp-tegra-priv.h>      // for tegra_hsp_id, tegra_hsp_conf, teg...
+#include <hsp/hsp-tegra.h>           // for tegra_hsp_suspend_ctx, FSP__HSP__...
+#include <soc-common/hsp-tegra-sm.h> // for tegra_hsp_sm_produce_128...
+#include <hsp/sections-hsp.h>        // Immune from CT_ASSERT protection
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HSP__HSP_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HSP__HSP_TEGRA_DEFS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HSP__HSP_TEGRA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HSP__HSP_TEGRA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HSP__HSP_TEGRA_SM_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @brief HSP 128-bit shared mailbox registers offset
+ *
+ * Defines the HSP shared mailbox registers offset for the 128-bit variant.
+ */
+#define HSP_SM_TYPE1_TAG_OFFSET    (0x40UL)
+#define HSP_SM_TYPE1_DATA0_OFFSET  (0x48UL)
+#define HSP_SM_TYPE1_DATA1_OFFSET  (0x4cUL)
+#define HSP_SM_TYPE1_DATA2_OFFSET  (0x50UL)
+#define HSP_SM_TYPE1_DATA3_OFFSET  (0x54UL)
+
+
+static inline uint32_t
+hsp_sm_128_offset(uint32_t sm_index,
+                  uint32_t offset)
+{
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-451, DR: SWE-FSP-046-SWSADR.docx");
+    return (HSP_COMMON_SIZE + (HSP_SHRD_MBOX_OFFSET * sm_index) + offset);
+}
+
+static inline void
+tegra_hsp_sm_write_128(const struct tegra_hsp_id *id,
+                       uint32_t index,
+                       hsp128_t const *value,
+                       uint32_t tag)
+{
+    writel_base_offset(value->d0, id->conf.base_addr,
+                       hsp_sm_128_offset(index, HSP_SM_TYPE1_DATA0_OFFSET));
+    writel_base_offset(value->d1, id->conf.base_addr,
+                       hsp_sm_128_offset(index, HSP_SM_TYPE1_DATA1_OFFSET));
+    writel_base_offset(value->d2, id->conf.base_addr,
+                       hsp_sm_128_offset(index, HSP_SM_TYPE1_DATA2_OFFSET));
+    writel_base_offset(value->d3, id->conf.base_addr,
+                       hsp_sm_128_offset(index, HSP_SM_TYPE1_DATA3_OFFSET));
+    writel_base_offset(tag, id->conf.base_addr,
+                       hsp_sm_128_offset(index, HSP_SM_TYPE1_TAG_OFFSET));
+}
+
+static inline void
+tegra_hsp_sm_read_128(const struct tegra_hsp_id *id,
+                      uint32_t index,
+                      hsp128_t *data)
+{
+    data->d0 = readl_base_offset(id->conf.base_addr,
+                          hsp_sm_128_offset(index, HSP_SM_TYPE1_DATA0_OFFSET));
+    data->d1 = readl_base_offset(id->conf.base_addr,
+                          hsp_sm_128_offset(index, HSP_SM_TYPE1_DATA1_OFFSET));
+    data->d2 = readl_base_offset(id->conf.base_addr,
+                          hsp_sm_128_offset(index, HSP_SM_TYPE1_DATA2_OFFSET));
+    data->d3 = readl_base_offset(id->conf.base_addr,
+                          hsp_sm_128_offset(index, HSP_SM_TYPE1_DATA3_OFFSET));
+    data->tag = readl_base_offset(id->conf.base_addr,
+                          hsp_sm_128_offset(index, HSP_SM_TYPE1_TAG_OFFSET));
+}
+
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
+SECTION_HSP_TEXT error_t
+tegra_hsp_sm_produce_128(const struct tegra_hsp_id *id,
+                         uint32_t sm,
+                         hsp128_t const *value)
+{
+    error_t ret = E_SUCCESS;
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    if (sm >= id->n_sm) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_MBOX;
+        goto out;
+    }
+
+    tegra_hsp_sm_write_128(id, sm, value, HSP_SHRD_MBOX_TAG_FIELD);
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_sm_consume_128(const struct tegra_hsp_id *id,
+                         uint32_t sm,
+                         hsp128_t *data)
+{
+    error_t ret;
+
+    ret = tegra_hsp_sm_peek_128(id, sm, data);
+
+    if (ret == E_SUCCESS) {
+        ret = tegra_hsp_sm_vacate_128(id, sm);
+    }
+
+    return ret;
+}
+
+SECTION_HSP_TEXT bool
+tegra_hsp_sm_128_is_empty(const struct tegra_hsp_id *id,
+                          uint32_t sm)
+{
+    bool     ret;
+    hsp128_t data;
+
+    if (id == NULL) {
+        ret = false;
+        goto out;
+    }
+
+    if (sm >= id->n_sm) {
+        ret = false;
+        goto out;
+    }
+
+    tegra_hsp_sm_read_128(id, sm, &data);
+
+    ret = ((data.tag  & HSP_SHRD_MBOX_TAG_FIELD) == 0U);
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_sm_peek_128(const struct tegra_hsp_id *id,
+                      uint32_t sm,
+                      hsp128_t *data)
+{
+    error_t  ret = E_SUCCESS;
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    if (sm >= id->n_sm) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_MBOX;
+        goto out;
+    }
+
+    tegra_hsp_sm_read_128(id, sm, data);
+
+    if ((data->tag & HSP_SHRD_MBOX_TAG_FIELD) == 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_EMPTY_MBOX;
+        goto out;
+    }
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_sm_vacate_128(const struct tegra_hsp_id *id,
+                        uint32_t sm)
+{
+    error_t  ret;
+    hsp128_t data = {
+        .d0 = 0UL,
+        .d1 = 0UL,
+        .d2 = 0UL,
+        .d3 = 0UL,
+    };
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    if (sm >= id->n_sm) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_MBOX;
+        goto out;
+    }
+
+    tegra_hsp_sm_write_128(id, sm, &data, 0);
+    ret = E_SUCCESS;
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT void
+tegra_hsp_sm128_irq_handler(const struct tegra_hsp_id *id,
+                            uint32_t sm)
+{
+    hsp_sm_data_t value;
+    void          *cb_data;
+
+    cb_data = id->sm[sm].opaque;
+    tegra_hsp_sm_read_128(id, sm, &value.sm.data);
+    id->sm[sm].callback(cb_data, &value);
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_set_sm_type(struct tegra_hsp_id *id,
+                      uint32_t sm,
+                      uint32_t type)
+{
+    error_t  ret = E_SUCCESS;
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    if (sm >= id->n_sm) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_MBOX;
+        goto out;
+    }
+
+    switch(type) {
+        case HSP_SM_TYPE_32:
+            id->sm[sm].wide = false;
+            break;
+        case HSP_SM_TYPE_128:
+            id->sm[sm].wide = true;
+            break;
+        default:
+            ret = E_HSP_ERR_NO_MBOX;
+            break;
+    }
+
+out:
+    return ret;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/hsp/hsp-tegra.c b/spe-freertos-bsp/fsp/source/drivers/hsp/hsp-tegra.c
new file mode 100644
index 0000000..665da88
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/hsp/hsp-tegra.c
@@ -0,0 +1,1114 @@
+/*
+ * Copyright (c) 2019-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                // for bool, false
+#include <stddef.h>                 // for NULL
+#include <stdint.h>                 // for uint32_t, uint8_t, UINT8_MAX, UIN...
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>         // for CT_ASSERT
+#include <soc-common/hw-const.h>    /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <arhsp_dbell.h>            // for HSP_DBELL_0_ENABLE_0, HSP_DBELL_0...
+#include <arhsp_int.h>              // for HSP_INT_DIMENSIONING_0_nDB_SHIFT
+
+
+/* Late FSP headers */
+#include <osa/rtos-task.h>          // for rtosTaskEnterCritical, rtosTaskEx...
+#include <osa/rtos-values.h>        // for rtosFALSE
+#include <cpu/type-conversion.h>    // for fsp_c_v_ptr_to_v_ptr
+#include <error/common-errors.h>    // for E_SUCCESS, error_t
+#include <irq/safe-irqs.h>          // for in_interrupt, irq_safe_enable, irq_set...
+#include <misc/attributes.h>        // for FSP__MISC__ATTRIBUTES_H, UNUSED
+#include <misc/bitops.h>            // for BIT, bit_number, FSP__MISC__BITOPS_H
+#include <misc/macros.h>            // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <reg-access/reg-access.h>  // for readl_base_offset, writel_base_of...
+
+/* Module-specific FSP headers */
+#include <hsp/hsp-errors.h>          // for E_HSP_ERR_NULL_PTR, E_HSP_ERR_NO_...
+#include <hsp/hsp-tegra-defs.h>      // for HSP_COMMON_SIZE, HSP_DBELL_OFFSET...
+#include <hsp/hsp-tegra-priv.h>      // for tegra_hsp_id, tegra_hsp_conf, teg...
+#include <hsp/hsp-tegra.h>           // for tegra_hsp_suspend_ctx, FSP__HSP__...
+#include <hsp/sections-hsp.h>        // Immune from CT_ASSERT protection
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_VALUES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__TYPE_CONVERSION_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HSP__HSP_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HSP__HSP_TEGRA_DEFS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HSP__HSP_TEGRA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HSP__HSP_TEGRA_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file hsp-tegra.c
+ * @brief Implementation of Tegra HSP driver
+ */
+
+#define HSP_nSM_FIELD   (1U)
+#define HSP_nSS_FIELD   (2U)
+#define HSP_nAS_FIELD   (3U)
+#define HSP_nDB_FIELD   (4U)
+#define HSP_nSI_FIELD   (5U)
+
+#define HSP_GET_nSM_FIELD(_reg_) (((_reg_) & HSP_INT_DIMENSIONING_0_nSM_FIELD) \
+                                           >> HSP_INT_DIMENSIONING_0_nSM_SHIFT)
+#define HSP_GET_nSS_FIELD(_reg_) (((_reg_) & HSP_INT_DIMENSIONING_0_nSS_FIELD) \
+                                           >> HSP_INT_DIMENSIONING_0_nSS_SHIFT)
+#define HSP_GET_nAS_FIELD(_reg_) (((_reg_) & HSP_INT_DIMENSIONING_0_nAS_FIELD) \
+                                           >> HSP_INT_DIMENSIONING_0_nAS_SHIFT)
+#define HSP_GET_nSI_FIELD(_reg_) (((_reg_) & HSP_INT_DIMENSIONING_0_nSI_FIELD) \
+                                           >> HSP_INT_DIMENSIONING_0_nSI_SHIFT)
+#define HSP_GET_nDB_FIELD(_reg_) (((_reg_) & HSP_INT_DIMENSIONING_0_nDB_FIELD) \
+                                            >> HSP_INT_DIMENSIONING_0_nDB_SHIFT)
+
+static inline uint32_t
+hsp_ie_offset(uint32_t si_index)
+{
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-451, DR: SWE-FSP-046-SWSADR.docx");
+    return ((uint32_t)HSP_INT_IE + (uint32_t)(HSP_INT_IE_OFFSET * si_index));
+}
+
+static inline uint32_t
+hsp_sm_ie_offset(uint32_t sm_index,
+                 uint32_t offset)
+{
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-451, DR: SWE-FSP-046-SWSADR.docx");
+    return (HSP_COMMON_SIZE + (HSP_SHRD_MBOX_OFFSET * sm_index) + offset);
+}
+
+static inline uint32_t
+hsp_sm_offset(uint32_t sm_index)
+{
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-451, DR: SWE-FSP-046-SWSADR.docx");
+    return (HSP_COMMON_SIZE + (HSP_SHRD_MBOX_OFFSET * sm_index));
+}
+
+static inline uint32_t
+hsp_db_offset(uint32_t host,
+              uint32_t offset)
+{
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-451, DR: SWE-FSP-046-SWSADR.docx");
+    return ((uint32_t)(HSP_DBELL_OFFSET * host) + offset);
+}
+
+static inline uint32_t
+hsp_ss_offset(uint32_t ss_index,
+              uint32_t offset)
+{
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-451, DR: SWE-FSP-046-SWSADR.docx");
+    return ((HSP_SHRD_SEM_OFFSET * ss_index) + offset);
+}
+
+static inline uint8_t
+hsp_int_dimensioning_field(uint32_t reg_val, uint32_t field)
+{
+    uint32_t val = 0UL;
+
+    switch(field) {
+        case HSP_nSM_FIELD:
+            val = HSP_GET_nSM_FIELD(reg_val);
+            break;
+        case HSP_nSS_FIELD:
+            val = HSP_GET_nSS_FIELD(reg_val);
+            break;
+        case HSP_nAS_FIELD:
+            val = HSP_GET_nAS_FIELD(reg_val);
+            break;
+        case HSP_nDB_FIELD:
+            val = HSP_GET_nDB_FIELD(reg_val);
+            break;
+        case HSP_nSI_FIELD:
+            val = HSP_GET_nSI_FIELD(reg_val);
+            break;
+        default:
+            /* Default case == NOP */
+            break;
+    }
+
+    return (uint8_t)val;
+}
+
+static inline void
+tegra_hsp_si_writel(const struct tegra_hsp_id *id,
+                    uint32_t value)
+{
+    writel_base_offset(value, id->conf.base_addr,
+                       hsp_ie_offset(id->conf.si_index));
+}
+
+static inline uint32_t
+tegra_hsp_si_readl(const struct tegra_hsp_id *id)
+{
+    return readl_base_offset(id->conf.base_addr,
+                             hsp_ie_offset(id->conf.si_index));
+}
+
+static inline void
+tegra_hsp_sm_writel(const struct tegra_hsp_id *id,
+                    uint32_t index,
+                    uint32_t value)
+{
+    writel_base_offset(value, id->conf.base_addr, hsp_sm_offset(index));
+}
+
+static inline uint32_t
+tegra_hsp_sm_readl(const struct tegra_hsp_id *id,
+                   uint32_t index)
+{
+    return readl_base_offset(id->conf.base_addr, hsp_sm_offset(index));
+}
+
+static inline void tegra_hsp_sm_ie_writel(const struct tegra_hsp_id *id,
+                                          uint32_t index,
+                                          uint32_t ie_offset,
+                                          uint32_t value)
+{
+    writel_base_offset(value, id->conf.base_addr,
+                       hsp_sm_ie_offset(index, ie_offset));
+}
+
+static inline void
+tegra_hsp_db_writel(const struct tegra_hsp_id *id,
+                    uint32_t host,
+                    uint32_t value,
+                    uint32_t offset)
+{
+    writel_base_offset(value, id->db_base, hsp_db_offset(host, offset));
+}
+
+static inline uint32_t
+tegra_hsp_db_readl(const struct tegra_hsp_id *id,
+                   uint32_t host,
+                   uint32_t offset)
+{
+    return readl_base_offset(id->db_base, hsp_db_offset(host, offset));
+}
+
+static inline void
+tegra_hsp_db_self_writel(const struct tegra_hsp_id *id,
+                         uint32_t value,
+                         uint32_t offset)
+{
+    tegra_hsp_db_writel(id, id->conf.host, value, offset);
+}
+
+static inline uint32_t
+tegra_hsp_db_self_readl(const struct tegra_hsp_id *id,
+                        uint32_t offset)
+{
+    return tegra_hsp_db_readl(id, id->conf.host, offset);
+}
+
+static inline error_t tegra_hsp_ss_writel(const struct tegra_hsp_id *id,
+                                          uint32_t index,
+                                          uint32_t offset,
+                                          uint32_t value)
+{
+    error_t ret;
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    if (index >= id->n_ss) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_SHRD_SMPHR;
+        goto out;
+    }
+
+    writel_base_offset(value, id->ss_base, hsp_ss_offset(index, offset));
+
+    ret = E_SUCCESS;
+
+out:
+    return ret;
+}
+
+static inline error_t tegra_hsp_ss_readl(const struct tegra_hsp_id *id,
+                                         uint32_t index,
+                                         uint32_t offset,
+                                         uint32_t *return_value)
+{
+    error_t ret;
+
+    if ((id == NULL) || (return_value == NULL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    if (index >= id->n_ss) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_SHRD_SMPHR;
+        goto out;
+    }
+
+    *return_value = readl_base_offset(id->ss_base,
+                                      hsp_ss_offset(index, offset));
+
+    ret = E_SUCCESS;
+
+out:
+    return ret;
+}
+
+static inline uint32_t tegra_hsp_ir_readl(const struct tegra_hsp_id *id)
+{
+    return readl_base_offset(id->conf.base_addr, HSP_INT_IR_0);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_HSP_TEXT void tegra_hsp_db_irq_handler(void *data)
+{
+    INLINE_RFD(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx");
+    const struct tegra_hsp_id *id = (const struct tegra_hsp_id *)data;
+    uint32_t db_pending;
+    rtosBool higher_prio_task_woken = (rtosBool) rtosFALSE;
+    uint32_t source;
+
+    db_pending = tegra_hsp_db_self_readl(id, HSP_DBELL_0_PENDING_0);
+    tegra_hsp_db_self_writel(id, db_pending, HSP_DBELL_0_PENDING_0);
+
+    while (db_pending != 0U) {
+        source = bit_number(db_pending);
+        db_pending &= ~BIT32_FN(source);
+        id->db_callback(source, &higher_prio_task_woken);
+    }
+
+    rtosTaskYieldFromISR(higher_prio_task_woken);
+}
+
+SECTION_HSP_TEXT static error_t
+tegra_hsp_sm_disable(struct tegra_hsp_id *id,
+                     uint32_t sm,
+                     uint32_t ie_offset)
+{
+    error_t ret = E_SUCCESS;
+
+    /* protect against accessing an instance that is power-gated */
+    if (id->suspended) {
+        goto out;
+    }
+
+    if (id->conf.si_index == (uint8_t)UINT8_MAX) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_INTR;
+        goto out;
+    }
+
+    if (sm >= id->n_sm) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_MBOX;
+        goto out;
+    }
+
+    if (!in_interrupt()) {
+        rtosTaskEnterCritical();
+    }
+
+    if (ie_offset != 0U) {
+        tegra_hsp_sm_ie_writel(id, sm, ie_offset, 0U);
+    } else {
+        id->sie_mask &= ~BIT(sm + HSP_INT_IE_0_mbox_empty_enable_SHIFT);
+        id->sie_mask &= ~BIT(sm + HSP_INT_IE_0_mbox_full_enable_SHIFT);
+
+        if (tegra_hsp_si_readl(id) != id->sie_mask) {
+            tegra_hsp_si_writel(id, id->sie_mask);
+        }
+    }
+
+    /* FIXME: sync interrupt handler here */
+    id->sm[sm].callback = NULL;
+
+    if (!in_interrupt()) {
+        rtosTaskExitCritical();
+    }
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT static void
+tegra_hsp_sm32_irq_handler(const struct tegra_hsp_id *id,
+                           uint32_t sm)
+{
+    hsp_sm_data_t value;
+    void          *cb_data;
+
+    cb_data = id->sm[sm].opaque;
+    value.sm.val = tegra_hsp_sm_readl(id, sm);
+    id->sm[sm].callback(cb_data, &value);
+}
+
+SECTION_HSP_TEXT static void
+tegra_hsp_sm_irq_handler(struct tegra_hsp_id *id,
+                         uint32_t mask)
+{
+    uint32_t sm_mask = mask;
+    uint32_t i;
+
+    while (sm_mask != 0U) {
+        i = bit_number(sm_mask);
+
+        if (id->sm[i].callback != NULL) {
+            if (id->sm[i].wide) {
+                tegra_hsp_sm128_irq_handler(id, i);
+            } else {
+                tegra_hsp_sm32_irq_handler(id, i);
+            }
+        } else {
+            (void)tegra_hsp_sm_disable(id, i, 0U);
+        }
+
+        sm_mask &= ~BIT(i);
+    }
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_HSP_TEXT void tegra_hsp_irq_handler(void *data)
+{
+    INLINE_RFD(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx");
+    struct tegra_hsp_id *id = (struct tegra_hsp_id *)fsp_c_v_ptr_to_v_ptr(data);
+    uint32_t ie = tegra_hsp_si_readl(id);
+    uint32_t ir = tegra_hsp_ir_readl(id);
+    uint32_t full_mask;
+    uint32_t empty_mask;
+
+    if (ie != id->sie_mask) {
+        tegra_hsp_si_writel(id, id->sie_mask);
+    }
+
+    ir &= id->sie_mask;
+
+    full_mask = (uint32_t)(ir & HSP_INT_IR_0_mbox_full_assert_FIELD)
+                                >> HSP_INT_IR_0_mbox_full_asserted_SHIFT;
+
+    tegra_hsp_sm_irq_handler(id, full_mask);
+
+    empty_mask = (ir & HSP_INT_IR_0_mbox_empty_asserted_FIELD)
+                               >> HSP_INT_IR_0_mbox_empty_asserted_SHIFT;
+
+    tegra_hsp_sm_irq_handler(id, empty_mask);
+}
+
+SECTION_HSP_INIT_TEXT error_t
+tegra_hsp_init(struct tegra_hsp_id *id)
+{
+    uint32_t val;
+    uint32_t i;
+    error_t ret = E_SUCCESS;
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    if (id->inited) {
+        goto out;
+    }
+
+    val = readl_base_offset(id->conf.base_addr, HSP_INT_DIMENSIONING_0);
+    id->n_sm = hsp_int_dimensioning_field(val, HSP_nSM_FIELD);
+    id->n_ss = hsp_int_dimensioning_field(val, HSP_nSS_FIELD);
+    id->n_as = hsp_int_dimensioning_field(val, HSP_nAS_FIELD);
+    id->n_db = hsp_int_dimensioning_field(val, HSP_nDB_FIELD);
+    id->n_si = hsp_int_dimensioning_field(val, HSP_nSI_FIELD);
+
+    if (id->n_ss > 0U) {
+        INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+        id->ss_base = id->conf.base_addr + ((uint32_t)(1U + ((uint32_t)id->n_sm >> 1U)) << 16U);
+    }
+
+    if (id->n_db > 0U) {
+        INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+        id->db_base = id->conf.base_addr +
+                ((uint32_t)(1U + ((uint32_t)id->n_sm >> 1U) + id->n_ss + id->n_as) << 16U);
+    }
+
+    /* default to 32-bit type shared mailboxes */
+    if (id->n_sm > 0U) {
+        for (i = 0UL; i < id->n_sm; i += 1UL) {
+            id->sm[i].wide = false;
+        }
+    }
+
+    if ((id->conf.sh_irq != UINT32_MAX) && (id->conf.si_index != (uint8_t)UINT8_MAX)) {
+        /* Disable all shared interrupt sources */
+        tegra_hsp_si_writel(id, id->sie_mask);
+        ret = irq_safe_set_handler((uint32_t)id->conf.sh_irq, tegra_hsp_irq_handler, (void*)id);
+        if (ret == E_SUCCESS) {
+            ret = irq_safe_enable((uint32_t)id->conf.sh_irq);
+        }
+    }
+
+    if (ret == E_SUCCESS) {
+        id->inited = true;
+    }
+
+out:
+    return ret;
+}
+
+SECTION_HSP_INIT_TEXT error_t
+tegra_hsp_db_init(struct tegra_hsp_id *id,
+                  uint32_t enabled_masters,
+                  tegra_hsp_db_callback callback)
+{
+    error_t ret;
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    if (callback == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_INVALID_CALLBACK;
+        goto out;
+    }
+
+    UNUSED((tegra_hsp_init(id)));
+
+    if (id->n_db == 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_DB;
+        goto out;
+    }
+    id->db_callback = callback;
+
+    ret = irq_safe_set_handler((uint32_t)id->conf.db_irq, tegra_hsp_db_irq_handler, (void*)id);
+    if (ret == E_SUCCESS) {
+        ret = irq_safe_enable((uint32_t)id->conf.db_irq);
+    }
+
+    /* Enable the interrupt from <enabled_master> */
+    if (ret == E_SUCCESS) {
+        tegra_hsp_db_self_writel(id, enabled_masters, HSP_DBELL_0_ENABLE_0);
+    }
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_sm_produce(const struct tegra_hsp_id *id,
+                     uint32_t sm,
+                     uint32_t value)
+{
+    error_t ret = E_SUCCESS;
+    uint32_t reg_val;
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    /* protect against accessing an instance that is power-gated */
+    if (id->suspended) {
+        goto out;
+    }
+
+    if (sm >= id->n_sm) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_MBOX;
+        goto out;
+    }
+
+    reg_val = HSP_SHRD_MBOX_TAG_FIELD | value;
+#if defined(HW_BUG_200395605) && (HW_BUG_200395605 == 1)
+    if (reg_val == DEAD1001) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_INVALID_DATA;
+        goto out;
+    }
+#endif
+
+    tegra_hsp_sm_writel(id, sm, reg_val);
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_sm_consume(const struct tegra_hsp_id *id,
+                     uint32_t sm,
+                     uint32_t *data)
+{
+    error_t ret;
+
+    ret = tegra_hsp_sm_peek(id, sm, data);
+
+    if (ret == E_SUCCESS) {
+        ret = tegra_hsp_sm_vacate(id, sm);
+    }
+
+    return ret;
+}
+
+SECTION_HSP_TEXT bool
+tegra_hsp_sm_is_empty(const struct tegra_hsp_id *id,
+                      uint32_t sm)
+{
+    bool ret;
+    uint32_t v;
+
+    if (id == NULL) {
+        ret = false;
+        goto out;
+    }
+
+    /* protect against accessing an instance that is power-gated */
+    if (id->suspended) {
+        ret = true;
+        goto out;
+    }
+
+    if (sm >= id->n_sm) {
+        ret = false;
+        goto out;
+    }
+
+    v = tegra_hsp_sm_readl(id, sm);
+
+    ret = ((v & HSP_SHRD_MBOX_TAG_FIELD) == 0U);
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_sm_peek(const struct tegra_hsp_id *id,
+                  uint32_t sm,
+                  uint32_t *data)
+{
+    error_t ret = E_SUCCESS;
+    uint32_t v;
+
+    if ((id == NULL) || (data == NULL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    /* protect against accessing an instance that is power-gated */
+    if (id->suspended) {
+        goto out;
+    }
+
+    if (sm >= id->n_sm) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_MBOX;
+        goto out;
+    }
+
+    v = tegra_hsp_sm_readl(id, sm);
+
+    if ((v & HSP_SHRD_MBOX_TAG_FIELD) == 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_EMPTY_MBOX;
+        goto out;
+    }
+
+    *data = (v & HSP_SHRD_MBOX_DATA_FIELD);
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_sm_vacate(const struct tegra_hsp_id *id,
+                    uint32_t sm)
+{
+    error_t ret = E_SUCCESS;
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    if (id->suspended) {
+        goto out;
+    }
+
+    if (sm >= id->n_sm) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_MBOX;
+        goto out;
+    }
+
+    tegra_hsp_sm_writel(id, sm, 0);
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT static void
+tegra_hsp_sm_enable(struct tegra_hsp_id *id,
+                    uint32_t sm,
+                    uint32_t ie_offset,
+                    uint32_t setbit,
+                    uint32_t clrbit,
+                    tegra_hsp_sm_callback cb,
+                    void *data)
+{
+    if (!in_interrupt()) {
+        rtosTaskEnterCritical();
+    }
+
+    id->sm[sm].callback = cb;
+    id->sm[sm].opaque = data;
+    id->sie_mask |= BIT32_FN(setbit);
+    id->sie_mask &= ~BIT32_FN(clrbit);
+
+    if (id->sie_mask != tegra_hsp_si_readl(id)) {
+        tegra_hsp_si_writel(id, id->sie_mask);
+    }
+
+    tegra_hsp_sm_ie_writel(id, sm, ie_offset, 1U);
+
+    if (!in_interrupt()) {
+        rtosTaskExitCritical();
+    }
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_sm_full_enable(struct tegra_hsp_id *id,
+                         uint32_t sm,
+                         tegra_hsp_sm_callback cb,
+                         void *data)
+{
+    error_t  ret = E_SUCCESS;
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    /* protect against accessing an instance that is power-gated */
+    if (id->suspended) {
+        goto out;
+    }
+
+    if (id->conf.si_index == (uint8_t)UINT8_MAX) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_INTR;
+        goto out;
+    }
+
+    if (sm >= id->n_sm) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_MBOX;
+        goto out;
+    }
+
+    tegra_hsp_sm_enable(id, sm, HSP_SHRD_MBOX_FULL_IE_OFFSET,
+                (uint32_t)HSP_INT_IE_0_mbox_full_enable_SHIFT + sm,
+                (uint32_t)HSP_INT_IE_0_mbox_empty_enable_SHIFT + sm,
+                cb, data);
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_sm_full_disable(struct tegra_hsp_id *id,
+                          uint32_t sm)
+{
+    INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+    return (id == NULL) ? E_HSP_ERR_NULL_PTR :
+                tegra_hsp_sm_disable(id, sm, HSP_SHRD_MBOX_FULL_IE_OFFSET);
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_sm_empty_enable(struct tegra_hsp_id *id,
+                          uint32_t sm,
+                          tegra_hsp_sm_callback cb,
+                          void *data)
+{
+    error_t ret = E_SUCCESS;
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    /* protect against accessing an instance that is power-gated */
+    if (id->suspended) {
+        goto out;
+    }
+
+    if (id->conf.si_index == (uint8_t)UINT8_MAX) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_INTR;
+        goto out;
+    }
+
+    if (sm >= id->n_sm) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_MBOX;
+        goto out;
+    }
+
+    tegra_hsp_sm_enable(id, sm, HSP_SHRD_MBOX_EMPTY_IE_OFFSET,
+                (uint32_t)HSP_INT_IE_0_mbox_empty_enable_SHIFT + sm,
+                (uint32_t)HSP_INT_IE_0_mbox_full_enable_SHIFT + sm,
+                cb, data);
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_sm_empty_disable(struct tegra_hsp_id *id,
+                           uint32_t sm)
+{
+    INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+    return (id == NULL) ? E_HSP_ERR_NULL_PTR :
+                tegra_hsp_sm_disable(id, sm, HSP_SHRD_MBOX_EMPTY_IE_OFFSET);
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_db_ring(const struct tegra_hsp_id *id,
+                  uint32_t target)
+{
+    error_t ret;
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    if (id->db_base == 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_DB;
+        goto out;
+    }
+
+    tegra_hsp_db_writel(id, target, 1, HSP_DBELL_0_TRIGGER_0);
+
+    ret = E_SUCCESS;
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_db_enable_master(const struct tegra_hsp_id *id,
+                           uint32_t enabled_masters)
+{
+    error_t ret;
+    uint32_t enable;
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    if (id->db_base == 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_DB;
+        goto out;
+    }
+
+    if (!in_interrupt()) {
+        rtosTaskEnterCritical();
+    }
+
+    enable = tegra_hsp_db_self_readl(id, HSP_DBELL_0_ENABLE_0);
+    enable |= enabled_masters;
+    tegra_hsp_db_self_writel(id, enable, HSP_DBELL_0_ENABLE_0);
+
+    if (!in_interrupt()) {
+        rtosTaskExitCritical();
+    }
+
+    ret = E_SUCCESS;
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_db_disable_master(const struct tegra_hsp_id *id,
+                            uint32_t disabled_masters)
+{
+    error_t ret;
+    uint32_t enable;
+
+    if (id == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    if (id->db_base == 0U) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NO_DB;
+        goto out;
+    }
+
+    if (!in_interrupt()) {
+        rtosTaskEnterCritical();
+    }
+
+    enable = tegra_hsp_db_self_readl(id, HSP_DBELL_0_ENABLE_0);
+    enable &= ~disabled_masters;
+    tegra_hsp_db_self_writel(id, enable, HSP_DBELL_0_ENABLE_0);
+
+    if (!in_interrupt()) {
+        rtosTaskExitCritical();
+    }
+
+    ret = E_SUCCESS;
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_suspend(struct tegra_hsp_id *id,
+                  struct tegra_hsp_suspend_ctx *sctx)
+{
+    error_t ret = E_SUCCESS;
+
+    if ((id == NULL) || (sctx == NULL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    if ((id->conf.sh_irq != UINT32_MAX) &&
+                    (id->conf.si_index != (uint8_t)UINT8_MAX)) {
+
+        /* This statement only execute if (sctx != NULL).  Normally, we would put in a check here
+         * to ensure that condition.  However, in this case, that check isn't needed due to the
+         * conditional statements above.  The 'if' clause above ((id == NULL) || (sctx == NULL))
+         * guarantees that (sctx != NULL), therefore, this check is not needed below.
+         * Fixes MISRA Rule 14.3 violation. */
+        sctx->si_enable = tegra_hsp_si_readl(id);
+        ret = irq_safe_disable((uint32_t)id->conf.sh_irq);
+
+    }
+    if ((ret == E_SUCCESS) && (id->conf.db_irq != UINT32_MAX)) {
+
+        /* This statement only execute if (sctx != NULL).  Normally, we would put in a check here
+         * to ensure that condition.  However, in this case, that check isn't needed due to the
+         * conditional statements above.  The 'if' clause above ((id == NULL) || (sctx == NULL))
+         * guarantees that (sctx != NULL), therefore, this check is not needed below.
+         * Fixes MISRA Rule 14.3 violation. */
+        sctx->db_enable = tegra_hsp_db_self_readl(id, HSP_DBELL_0_ENABLE_0);
+        ret = irq_safe_disable((uint32_t)id->conf.db_irq);
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+    id->suspended = (ret == E_SUCCESS) ? true : false;
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_resume(struct tegra_hsp_id *id,
+                 const struct tegra_hsp_suspend_ctx *sctx)
+{
+    error_t ret = E_SUCCESS;
+
+    if ((id == NULL) || (sctx == NULL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_HSP_ERR_NULL_PTR;
+        goto out;
+    }
+
+    if (id->conf.db_irq != UINT32_MAX) {
+
+        /* This statement only execute if (sctx != NULL).  Normally, we would put in a check here
+         * to ensure that condition.  However, in this case, that check isn't needed due to the
+         * conditional statements above.  The 'if' clause above ((id == NULL) || (sctx == NULL))
+         * guarantees that (sctx != NULL), therefore, this check is not needed below.
+         * Fixes MISRA Rule 14.3 violation. */
+        tegra_hsp_db_self_writel(id, sctx->db_enable, HSP_DBELL_0_ENABLE_0);
+        ret = irq_safe_enable((uint32_t)id->conf.db_irq);
+    }
+    if ((ret == E_SUCCESS) && (id->conf.sh_irq != UINT32_MAX) &&
+                    (id->conf.si_index != (uint8_t)UINT8_MAX)) {
+
+        /* This statement only execute if (sctx != NULL).  Normally, we would put in a check here
+         * to ensure that condition.  However, in this case, that check isn't needed due to the
+         * conditional statements above.  The 'if' clause above ((id == NULL) || (sctx == NULL))
+         * guarantees that (sctx != NULL), therefore, this check is not needed below.
+         * Fixes MISRA Rule 14.3 violation. */
+        tegra_hsp_si_writel(id, sctx->si_enable);
+
+        INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-1795, DR: SWE-FSP-062-SWSADR.docx");
+        ret = irq_safe_enable((uint32_t)id->conf.sh_irq);
+    }
+
+    id->suspended = (ret == E_SUCCESS) ? false : true;
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_ss_read(const struct tegra_hsp_id *id,
+                  uint32_t index,
+                  uint32_t *value)
+{
+    return tegra_hsp_ss_readl(id, index, HSP_SHRD_SEM_STA, value);
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_ss_set(const struct tegra_hsp_id *id,
+                 uint32_t index,
+                 uint32_t data)
+{
+    error_t ret;
+
+    /**
+     * parameter check for HW bug 200395605 (HSP IAS 7.3.1 SW WAR)
+     */
+#if defined(HW_BUG_200395605) && (HW_BUG_200395605 == 1)
+    if ((data & HSP_SS_FORBIDDEN_BITS) != 0U) {
+        ret = E_HSP_ERR_INVALID_DATA;
+        goto out;
+    }
+#endif
+
+    ret = tegra_hsp_ss_writel(id, index, HSP_SHRD_SEM_SET, data);
+
+#if defined(HW_BUG_200395605) && (HW_BUG_200395605 == 1)
+out:
+#endif
+    return ret;
+}
+
+SECTION_HSP_TEXT error_t
+tegra_hsp_ss_clear(const struct tegra_hsp_id * id,
+                   uint32_t index,
+                   uint32_t data)
+{
+    return tegra_hsp_ss_writel(id, index, HSP_SHRD_SEM_CLR, data);
+}
+
+SECTION_HSP_TEXT uint32_t
+tegra_hsp_sm_count(const struct tegra_hsp_id *id)
+{
+    uint32_t ret;
+    uint32_t val;
+
+    if (id == NULL) {
+        ret = 0U;
+        goto out;
+    }
+
+    val = readl_base_offset(id->conf.base_addr, HSP_INT_DIMENSIONING_0);
+
+    ret = hsp_int_dimensioning_field(val, HSP_nSM_FIELD);
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT uint32_t
+tegra_hsp_ss_count(const struct tegra_hsp_id *id)
+{
+    uint32_t ret;
+    uint32_t val;
+
+    if (id == NULL) {
+        ret = 0U;
+        goto out;
+    }
+
+    val = readl_base_offset(id->conf.base_addr, HSP_INT_DIMENSIONING_0);
+
+    ret = hsp_int_dimensioning_field(val, HSP_nSS_FIELD);
+
+out:
+    return ret;
+}
+
+SECTION_HSP_TEXT uint32_t
+tegra_hsp_db_count(const struct tegra_hsp_id *id)
+{
+    uint32_t ret;
+    uint32_t val;
+
+    if (id == NULL) {
+        ret = 0U;
+        goto out;
+    }
+
+    val = readl_base_offset(id->conf.base_addr, HSP_INT_DIMENSIONING_0);
+
+    ret = hsp_int_dimensioning_field(val, HSP_nDB_FIELD);
+
+out:
+    return ret;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/hsp/module-hsp-config.mk b/spe-freertos-bsp/fsp/source/drivers/hsp/module-hsp-config.mk
new file mode 100644
index 0000000..560736f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/hsp/module-hsp-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-hsp-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_HSP_CONFIG               := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_HSP_DEPENDS              := SOC CLUSTER CPL OSA FSP_COMMON
+$(foreach _,$(MODULE_HSP_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_HSP_DRIVERS_DIR           = $(FSP_COMMON_REPO)/drivers/hsp
+MODULE_HSP_SOURCE_DIR            = $(MODULE_HSP_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_HSP_INCLUDES              =
diff --git a/spe-freertos-bsp/fsp/source/drivers/hsp/module-hsp.mk b/spe-freertos-bsp/fsp/source/drivers/hsp/module-hsp.mk
new file mode 100644
index 0000000..2a79722
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/hsp/module-hsp.mk
@@ -0,0 +1,69 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-hsp.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_HSP_NAME                 := HSP
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_HSP_DEFINED              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_HSP_DEPENDS              := HSP SOC CPL OSA
+$(foreach _,$(CONFIG_HSP_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_HSP_C_SRC                 =
+MODULE_HSP_C_SRC                += $(MODULE_HSP_DRIVERS_DIR)/hsp-tegra.c
+MODULE_HSP_C_SRC                += $(CPL_SOC_IDS)/hsp-tegra-ids.c
+ifeq ($(SOC), t194)
+MODULE_HSP_C_SRC                += $(MODULE_HSP_DRIVERS_DIR)/hsp-tegra-dummy-isr-sm-128.c
+else
+MODULE_HSP_C_SRC                += $(MODULE_HSP_DRIVERS_DIR)/hsp-tegra-sm-128.c
+endif
+
+#
+# Assembly source
+MODULE_HSP_ASM_SRC               =
+MODULE_HSP_ASM_SRC              += $(CPL_SOC_PORT)/hsp-irq.S
+
+#
+# Special C Flags
+MODULE_HSP_C_FLAGS               =
+
+#
+# Special ASM Flags
+MODULE_HSP_ASM_FLAGS             =
diff --git a/spe-freertos-bsp/fsp/source/drivers/i2c/i2c-core-async.c b/spe-freertos-bsp/fsp/source/drivers/i2c/i2c-core-async.c
new file mode 100644
index 0000000..debf0f4
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/i2c/i2c-core-async.c
@@ -0,0 +1,191 @@
+/*
+ * Copyright (c) 2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                      // for true
+#include <stdint.h>                       // for uint16_t, uint32_t, uint8_t
+#include <string.h>                       // for NULL, memcpy, size_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>               // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>          // for E_INVALID_PARAM, E_SUCCESS...
+
+/* Module-specific FSP headers */
+#include <i2c/i2c-errors.h>               // for E_I2C_INVALID_OPS, FSP__I2C...
+#include <i2c/i2c-config.h>               // for i2c_handle, ...
+#include <i2c/i2c-hw-ops.h>               // for i2c_hw_ops, FSP__I2C__I2C_H...
+#include <i2c/i2c-tegra.h>                // for i2c_xfer_msg, tegra_i2c_init
+#include <i2c/i2c-tegra-async.h>          // for tegra_i2c_get_xfer_state
+#include <i2c/i2c.h>                      // for i2c_handle, FSP__I2C__I2C_H
+#include <i2c/i2c-async.h>                // for i2c_start_async_xfer, i2c_f...
+#include <soc-common/i2c-dependencies.h>  // for appfw_mutex_acquire, appfw_...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_CONFIG_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_HW_OPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_TEGRA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_TEGRA_ASYNC_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_ASYNC_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__I2C_DEPENDENCIES_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/* Custom Defines */
+#define I2C_MUTEX_TIMEOUT_US           1000U
+
+/* Stuct Definitions and Declarations */
+
+/* API Definitions */
+
+error_t i2c_start_async_xfer(const struct i2c_handle *hi2c,
+                            struct i2c_xfer_msg *msgs, uint32_t num_msgs,
+                            void *client_data, i2c_async_callback async_cb)
+{
+    error_t ret;
+    error_t tmp;
+    uint32_t i;
+
+    if ((hi2c == NULL) ||
+        (msgs == NULL) ||
+        (async_cb == NULL) ||
+        ((num_msgs == 0UL))) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid (%s) params provided, ret - 0x%x\n", __func__,
+                    ((hi2c == NULL) ? "hi2c" :
+                     ((pdata == NULL) ? "pdata" :
+                      ((async_cb == NULL) ? "async_cb" : "num_data"))),
+                     (int32_t)ret);
+        goto out;
+    }
+
+    for (i = 0U; i < num_msgs; i++) {
+        if (msgs[i].buf_len == 0U) {
+            INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+            ret = E_INVALID_PARAM;
+            i2c_pr_error("%s: invalid msg[%lu].buf_len, ret - 0x%x\n", __func__,
+                            i, (int32_t)ret);
+            goto out;
+        }
+    }
+
+    ret = appfw_mutex_acquire(hi2c->ctrl_id, I2C_MUTEX_TIMEOUT_US);
+    if (ret != E_SUCCESS) {
+        i2c_pr_error("%s: failed to acquire mutex, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto release;
+    }
+
+    if (hi2c->hw_ops->start_async_xfer != NULL) {
+        ret = hi2c->hw_ops->start_async_xfer(hi2c->hi2c_tegra, msgs, num_msgs,
+                                            client_data, async_cb);
+    } else {
+        ret = E_I2C_INVALID_OPS;
+        i2c_pr_error("%s: invalid hi2c->hw_ops->start_async_xfer, ret - 0x%x\n",
+                        __func__, (int32_t)ret);
+    }
+
+release:
+    /* Release mutex if start transfer failed. */
+    if (ret != E_SUCCESS) {
+        tmp = appfw_mutex_release(hi2c->ctrl_id);
+        if (tmp != E_SUCCESS) {
+            i2c_pr_error("%s: failed to release mutex, ret - 0x%x\n", __func__,
+                            (int32_t) ret);
+        }
+    }
+
+out:
+    return ret;
+}
+
+error_t i2c_finish_async_xfer(const struct i2c_handle *hi2c, error_t xfer_ret)
+{
+    error_t ret;
+    error_t tmp;
+
+    if (hi2c == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid hi2c, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto out;
+    }
+
+    if (hi2c->hw_ops->finish_async_xfer != NULL) {
+        ret = hi2c->hw_ops->finish_async_xfer(hi2c->hi2c_tegra, xfer_ret);
+    } else {
+        ret = E_I2C_INVALID_OPS;
+        i2c_pr_error("%s: invalid hi2c->hw_ops->finish_async_xfer, ret - 0x%x\n",
+                        __func__, (int32_t)ret);
+    }
+
+    tmp = appfw_mutex_release(hi2c->ctrl_id);
+    if (ret == E_SUCCESS) {
+        ret = tmp;
+        i2c_pr_error("%s: failed to release mutex, ret - 0x%x\n", __func__,
+                (int32_t) ret);
+    }
+
+out:
+    return ret;
+}
+
+error_t i2c_get_xfer_state(const struct i2c_handle *hi2c, uint32_t *state,
+                            uint32_t *msgs_xfered)
+{
+    error_t ret = E_SUCCESS;
+
+    if ((hi2c == NULL) || (state == NULL) || (msgs_xfered == NULL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid %s, ret - 0x%x\n", __func__,
+                        ((hi2c == NULL) ? "hi2c" :
+                         (state == NULL) ? "state" : "msgs_xfered"),
+                        (int32_t)ret);
+        goto out;
+    }
+
+    if (hi2c->hi2c_tegra != NULL) {
+        *state = tegra_i2c_get_xfer_state(hi2c->hi2c_tegra, msgs_xfered);
+    } else {
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid hi2c->hi2c_tegra, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+    }
+
+out:
+    return ret;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/i2c/i2c-core.c b/spe-freertos-bsp/fsp/source/drivers/i2c/i2c-core.c
new file mode 100644
index 0000000..a9e67f4
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/i2c/i2c-core.c
@@ -0,0 +1,459 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                      // for true
+#include <stdint.h>                       // for uint16_t, uint32_t, uint8_t
+#include <string.h>                       // for NULL, memcpy, size_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>               // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>          // for E_INVALID_PARAM, E_SUCCESS...
+#include <misc/attributes.h>              // for UNUSED
+#include <misc/macros.h>                  // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <i2c/i2c-errors.h>               // for E_I2C_INVALID_OPS, FSP__I2C...
+#include <i2c/i2c-hw-ops.h>               // for i2c_hw_ops, FSP__I2C__I2C_H...
+#include <i2c/i2c-tegra.h>                // for i2c_xfer_msg, tegra_i2c_init
+#include <i2c/i2c.h>                      // for i2c_handle, FSP__I2C__I2C_H
+#include <soc-common/i2c-dependencies.h>  // for appfw_mutex_acquire, appfw_...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_CONFIG_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_HW_OPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_TEGRA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__I2C_DEPENDENCIES_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/* Custom Defines */
+/* First msg contains the slave address and second contains data to transfer */
+#define I2C_REG_XFER_NUM_MSGS       2U
+#define I2C_XFER_NUM_MSGS           1U
+
+/* Struct Definitions and Declarations */
+
+/* API Definitions */
+
+error_t i2c_reg_write_data(const struct i2c_handle *hi2c, uint16_t slave_address,
+                           uint8_t reg_address, uint16_t flags, uint8_t const *pdata,
+                           uint16_t num_data, uint32_t timeout)
+{
+    struct i2c_xfer_msg msg;
+    error_t ret;
+    uint8_t data[I2C_PKT_XFER_MAX_BYTES];
+
+    data[0] = reg_address;
+
+    if ((hi2c == NULL) || (pdata == NULL) || (num_data == 0U)
+            || (num_data > (I2C_PKT_XFER_MAX_BYTES - 1U))) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid (%s) params provided, ret - 0x%x\n", __func__,
+                    ((hi2c == NULL) ? "hi2c" :
+                        ((pdata == NULL) ? "pdata" : "num_data")), (int32_t)ret);
+        goto out;
+    }
+
+    UNUSED((memcpy(&data[1], pdata, (size_t)num_data)));
+    msg.dev_addr = slave_address;
+    msg.pwbuf = data;
+    msg.buf_len = num_data + 1U;
+    msg.xfer_flags = flags;
+
+    ret = i2c_do_transfer(hi2c, &msg, I2C_XFER_NUM_MSGS, timeout);
+
+out:
+    return ret;
+}
+
+error_t i2c_reg_read_data(const struct i2c_handle *hi2c, uint16_t slave_address,
+                          uint8_t reg_address, uint16_t flags, uint8_t *pdata,
+                          uint16_t num_data, uint32_t timeout)
+{
+    struct i2c_xfer_msg m[I2C_REG_XFER_NUM_MSGS];
+    error_t ret;
+
+    if ((hi2c == NULL) || (pdata == NULL) || (num_data == 0ULL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid (%s) params provided, ret - 0x%x\n", __func__,
+                    ((hi2c == NULL) ? "hi2c" :
+                        ((pdata == NULL) ? "pdata" : "num_data")), (int32_t)ret);
+        goto out;
+    }
+
+    m[0].dev_addr = slave_address;
+    m[0].pwbuf = &reg_address;
+    m[0].buf_len = 1U;
+    m[0].xfer_flags = flags;
+
+    m[1].dev_addr = slave_address;
+    m[1].prbuf = pdata;
+    m[1].buf_len = num_data;
+    m[1].xfer_flags = flags;
+    m[1].xfer_flags |= (uint16_t)I2C_XFER_FLAG_RD;
+
+    ret = i2c_do_transfer(hi2c, m, I2C_REG_XFER_NUM_MSGS, timeout);
+
+out:
+    return ret;
+}
+
+error_t i2c_send_data(const struct i2c_handle *hi2c, uint16_t slave_address,
+                      uint16_t flags, const uint8_t *pdata, uint32_t num_data,
+                      uint32_t timeout)
+{
+    struct i2c_xfer_msg m;
+    error_t ret;
+
+    if ((hi2c == NULL) || (pdata == NULL) || (num_data == 0U)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid (%s) params provided, ret - 0x%x\n", __func__,
+                    ((hi2c == NULL) ? "hi2c" :
+                        ((pdata == NULL) ? "pdata" : "num_data")), (int32_t)ret);
+        goto out;
+    }
+
+    m.dev_addr = slave_address;
+    m.pwbuf = pdata;
+    m.buf_len = (uint16_t)num_data;
+    m.xfer_flags = flags;
+
+    ret = i2c_do_transfer(hi2c, &m, I2C_XFER_NUM_MSGS, timeout);
+
+out:
+    return ret;
+}
+
+error_t i2c_receive_data(const struct i2c_handle *hi2c, uint16_t slave_address,
+                         uint16_t flags, uint8_t *pdata, uint32_t num_data,
+                         uint32_t timeout)
+{
+    struct i2c_xfer_msg m;
+    error_t ret;
+
+    if ((hi2c == NULL) || (pdata == NULL) || (num_data == 0U)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid (%s) params provided, ret - 0x%x\n", __func__,
+                    ((hi2c == NULL) ? "hi2c" :
+                        ((pdata == NULL) ? "pdata" : "num_data")), (int32_t)ret);
+        goto out;
+    }
+
+    m.dev_addr = slave_address;
+    m.prbuf = pdata;
+    m.buf_len = (uint16_t)num_data;
+    m.xfer_flags = flags;
+    m.xfer_flags |= (uint16_t)I2C_XFER_FLAG_RD;
+
+    ret = i2c_do_transfer(hi2c, &m, I2C_XFER_NUM_MSGS, timeout);
+
+out:
+    return ret;
+}
+
+error_t i2c_do_transfer(const struct i2c_handle *hi2c,
+                        struct i2c_xfer_msg *msgs,
+                        uint32_t num_msgs, uint32_t timeout)
+{
+    error_t ret;
+    error_t tmp;
+    uint32_t i;
+
+    if ((hi2c == NULL) || (msgs == NULL) || (num_msgs == 0UL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid (%s) params provided, ret - 0x%x\n", __func__,
+                    ((hi2c == NULL) ? "hi2c" :
+                        ((msgs == NULL) ? "msgs" : "num_data")), (int32_t)ret);
+        goto out;
+    }
+
+    for (i = 0U; i < num_msgs; i++) {
+        if (msgs[i].buf_len == 0U){
+            INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+            ret = E_INVALID_PARAM;
+            i2c_pr_error("%s: invalid msg[%lu].buf_len, ret - 0x%x\n", __func__,
+                            i, (int32_t)ret);
+            goto out;
+        }
+    }
+
+    ret = appfw_mutex_acquire(hi2c->ctrl_id, timeout);
+    if (ret != E_SUCCESS) {
+        i2c_pr_error("%s: failed to acquire mutex, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto out;
+    }
+
+    if (hi2c->hw_ops->xfer != NULL) {
+        ret = hi2c->hw_ops->xfer(hi2c->hi2c_tegra, msgs, num_msgs, timeout);
+    } else {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_I2C_INVALID_OPS;
+        i2c_pr_error("%s: invalid hi2c->hw_ops->xfer, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+    }
+
+    tmp = appfw_mutex_release(hi2c->ctrl_id);
+    if (ret == E_SUCCESS) {
+        if (tmp != E_SUCCESS) {
+            ret = tmp;
+            i2c_pr_error("%s: failed to release mutex, ret - 0x%x\n", __func__,
+                            (int32_t)ret);
+        }
+    }
+
+out:
+    return ret;
+}
+
+error_t i2c_get_bus_state(const struct i2c_handle *hi2c, uint32_t *state)
+{
+    error_t ret = E_SUCCESS;
+
+    if ((hi2c == NULL) || (hi2c->hw_ops == NULL) || (state == NULL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid (%s) params provided, ret - 0x%x\n", __func__,
+                    ((hi2c == NULL) ? "hi2c" :
+                        ((hi2c->hw_ops == NULL) ? "hi2c->hw_ops" : "state")),
+                    (int32_t)ret);
+        goto out;
+    }
+
+    if(hi2c->hw_ops->get_bus_state == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_I2C_INVALID_OPS;
+        i2c_pr_error("%s: invalid hi2c->hw_ops->get_bus_state, ret - 0x%x\n",
+                        __func__, (int32_t)ret);
+        goto out;
+    }
+
+    ret = hi2c->hw_ops->get_bus_state(hi2c->hi2c_tegra, state);
+
+out:
+    return ret;
+}
+
+error_t i2c_suspend(const struct i2c_handle *hi2c)
+{
+    error_t ret;
+
+    if ((hi2c == NULL) || (hi2c->hw_ops == NULL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid (%s) params provided, ret - 0x%x\n", __func__,
+                    ((hi2c == NULL) ? "hi2c" : "hi2c->hw_ops"), (int32_t)ret);
+        goto out;
+    }
+
+    if (hi2c->hw_ops->suspend == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_I2C_INVALID_OPS;
+        i2c_pr_error("%s: invalid hi2c->hw_ops->suspend, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto out;
+    }
+
+    ret = hi2c->hw_ops->suspend(hi2c->hi2c_tegra);
+
+out:
+    return ret;
+}
+
+error_t i2c_resume(const struct i2c_handle *hi2c)
+{
+    error_t ret;
+
+    if ((hi2c == NULL) || (hi2c->hw_ops == NULL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid (%s) params provided, ret - 0x%x\n", __func__,
+                    ((hi2c == NULL) ? "hi2c" : "hi2c->hw_ops"), (int32_t)ret);
+        goto out;
+    }
+
+    if (hi2c->hw_ops->resume == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_I2C_INVALID_OPS;
+        i2c_pr_error("%s: invalid hi2c->hw_ops->resume, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto out;
+    }
+
+    ret = hi2c->hw_ops->resume(hi2c->hi2c_tegra);
+
+out:
+    return ret;
+}
+
+error_t i2c_controller_pre_init(uint32_t ctrl_id, struct i2c_handle *hi2c)
+{
+    error_t ret;
+    const struct i2c_config_data *pi2c_config;
+
+    if (ctrl_id > I2C_MAX_CTRLS) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid ctrl_id - %lu, allowed MAX - %u, ret - 0x%x\n",
+                        __func__, ctrl_id, I2C_MAX_CTRLS, (int32_t)ret);
+        goto out;
+    }
+
+    if (hi2c != NULL) {
+        if (hi2c->enabled) {
+            i2c_pr_debug("%s: i2c controller already enabled\n", __func__);
+            ret = E_SUCCESS;
+            goto out;
+        }
+    } else {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: hi2c not declared, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto out;
+    }
+
+#ifdef I2C_CUSTOM_PORT_INIT
+    ret = appfw_port_init(ctrl_id);
+    if (ret != E_SUCCESS) {
+        i2c_pr_error("%s: appfw_port_init failed, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto out;
+    }
+#else
+    ret = appfw_mutex_create(ctrl_id);
+    if (ret != E_SUCCESS) {
+        i2c_pr_error("%s: failed to acquire mutex, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto out;
+    }
+#endif
+
+    pi2c_config = i2c_get_config_data(ctrl_id);
+    if (pi2c_config == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid pi2c_config\n", __func__);
+        goto out;
+    }
+
+    if ((pi2c_config->ctrl_clk_rate < I2C_CLK_RATE_SM) ||
+            (pi2c_config->bus_clk_rate < I2C_CLK_RATE_SM)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid bus_clk_rate(%u)/ctrl_clk_rate(%u),"
+                        " ret - 0x%x\n", __func__, pi2c_config->ctrl_clk_rate,
+                        pi2c_config->bus_clk_rate, (int32_t)ret);
+        goto out;
+    }
+
+    hi2c->hi2c_tegra = i2c_get_tegra_handle(ctrl_id);
+    if (hi2c->hi2c_tegra == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: hi2c->hi2c_tegra not declared, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto out;
+    }
+
+    ret = tegra_i2c_pre_init(ctrl_id, hi2c->hi2c_tegra);
+    if (ret != E_SUCCESS) {
+        i2c_pr_error("%s: tegra_i2c_pre_init failed, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto out;
+    }
+
+    hi2c->pre_init_done = true;
+
+out:
+    return ret;
+}
+
+error_t i2c_controller_init(uint32_t ctrl_id, struct i2c_handle *hi2c)
+{
+    error_t ret;
+
+    if (ctrl_id > I2C_MAX_CTRLS) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid ctrl_id - %lu, allowed MAX - %u, ret - 0x%x\n",
+                        __func__, ctrl_id, I2C_MAX_CTRLS, (int32_t)ret);
+        goto out;
+    }
+
+    if (hi2c != NULL) {
+        if (hi2c->enabled) {
+            i2c_pr_debug("%s: i2c controller already enabled\n", __func__);
+            ret = E_SUCCESS;
+            goto out;
+        }
+    } else {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: hi2c not declared, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto out;
+    }
+
+    if (!hi2c->pre_init_done) {
+        ret = i2c_controller_pre_init(ctrl_id, hi2c);
+        if (ret != E_SUCCESS) {
+            i2c_pr_error("%s: i2c_controller_pre_init failed, ret - 0x%x\n",
+                            __func__, (int32_t)ret);
+            goto out;
+        }
+    }
+
+    ret = tegra_i2c_init(ctrl_id, hi2c->hi2c_tegra, &hi2c->hw_ops);
+    if (ret != E_SUCCESS) {
+        i2c_pr_error("%s: tegra_i2c_init failed, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto out;
+    }
+
+    i2c_pr_info("%s: i2c controller init success\n", __func__);
+    hi2c->ctrl_id = ctrl_id;
+    hi2c->enabled = true;
+out:
+    return ret;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/i2c/i2c-tegra-async.c b/spe-freertos-bsp/fsp/source/drivers/i2c/i2c-tegra-async.c
new file mode 100644
index 0000000..9653049
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/i2c/i2c-tegra-async.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                      // for false, true, bool
+#include <stddef.h>                       // for NULL
+#include <stdint.h>                       // for uint32_t, uint8_t, UINT32_C
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>               // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>          // for E_SUCCESS, E_INVALID_PARAM,...
+#include <misc/attributes.h>              // for UNUSED
+#include <misc/macros.h>                  // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <i2c/i2c-errors.h>               // for E_I2C_IO, E_I2C_ARB_LOST
+#include <i2c/i2c-tegra.h>                // for i2c_tegra_handle, i2c_xfer_msg
+#include <i2c/i2c.h>                      // for I2C_BUS_BUSY, I2C_SCL_BUSY
+#include <soc-common/i2c-dependencies.h>  // for appfw_udelay, appfw_timer_c...
+#include <i2c/i2c-tegra-async.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_TEGRA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_TEGRA_ASYNC_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__I2C_DEPENDENCIES_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/* Custom Defines */
+
+/* Struct Definitions and Declarations */
+
+/* API definitions */
+error_t tegra_i2c_start_async_xfer(struct i2c_tegra_handle *hi2c_tegra,
+                        struct i2c_xfer_msg *msgs, uint32_t num_msgs,
+                        void *client_data, i2c_async_callback async_xfer_cb)
+{
+    uint32_t i;
+    error_t ret;
+    const struct i2c_xfer_msg *this;
+    const struct i2c_xfer_msg *next;
+
+    ret = tegra_i2c_acquire(hi2c_tegra);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    ret = tegra_i2c_check_state(hi2c_tegra);
+    if (ret != E_SUCCESS) {
+        /* Assuming the worst possible scenario in the previous transfer */
+        INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-1795, DR: SWE-FSP-062-SWSADR.docx");
+        UNUSED((tegra_i2c_hw_init(hi2c_tegra)));
+        goto release;
+    }
+
+    ret = tegra_i2c_validate_msgs(msgs, num_msgs);
+    if (ret < 0) {
+        goto release;
+    }
+
+    /* Default transfer variables */
+    hi2c_tegra->is_async_xfer = true;
+    hi2c_tegra->async_xfer_cb = async_xfer_cb;
+    hi2c_tegra->client_data = client_data;
+    hi2c_tegra->xfer_status = I2C_XFER_REQUESTED;
+    hi2c_tegra->msgs = msgs;
+    hi2c_tegra->bytes_to_xfer = msgs[0].buf_len;
+    hi2c_tegra->msg_index = 0;
+
+    for (i = 0U; i < num_msgs; i++) {
+        this = &msgs[i];
+        next = ((i + 1U) < num_msgs) ? &msgs[i + 1U] : NULL;
+
+        /*
+         * Ignoring the wait time return as the async transfer does not need to
+         * wait for intterupt.
+         */
+        INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-1795, DR: SWE-FSP-062-SWSADR.docx");
+        UNUSED(tegra_i2c_xfer_one_msg(hi2c_tegra, this, next));
+    }
+
+    hi2c_tegra->xfer_status = I2C_XFER_STARTED;
+
+release:
+    /* Clk needs to be enabled throughout the xfer */
+    if (ret != E_SUCCESS) {
+        /* Above failure reasons take priority than release return */
+        INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-1795, DR: SWE-FSP-062-SWSADR.docx");
+        UNUSED(tegra_i2c_release(hi2c_tegra));
+    }
+
+out:
+    return ret;
+}
+
+error_t tegra_i2c_finish_async_xfer(const struct i2c_tegra_handle *hi2c_tegra,
+                                        error_t xfer_ret)
+{
+    error_t ret = E_SUCCESS;
+    error_t tmp = E_SUCCESS;
+
+    /* Skip handling for ARB lost */
+    if ((xfer_ret != E_SUCCESS) && ((xfer_ret != E_I2C_ARB_LOST))) {
+        ret = tegra_i2c_hw_init(hi2c_tegra);
+    }
+
+    tmp = tegra_i2c_release(hi2c_tegra);
+    if (ret == E_SUCCESS) {
+        ret = tmp;
+    }
+
+    return ret;
+}
+
+uint32_t tegra_i2c_get_xfer_state(const struct i2c_tegra_handle *hi2c_tegra,
+                                    uint32_t *msgs_xfered)
+{
+    *msgs_xfered = hi2c_tegra->msg_index;
+    return hi2c_tegra->xfer_status;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/i2c/i2c-tegra.c b/spe-freertos-bsp/fsp/source/drivers/i2c/i2c-tegra.c
new file mode 100644
index 0000000..4a3d4c3
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/i2c/i2c-tegra.c
@@ -0,0 +1,1631 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                      // for false, true, bool
+#include <stddef.h>                       // for NULL
+#include <stdint.h>                       // for uint32_t, uint8_t, UINT32_C
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>               // for CT_ASSERT
+
+/* Hardware headers */
+#include <soc-common/hw-const.h>
+#include <ari2c.h>                        // for I2C_I2C_INTERFACE_TIMING_0_...
+
+/* Late FSP headers */
+#include <error/common-errors.h>          // for E_SUCCESS, E_INVALID_PARAM,...
+#include <misc/attributes.h>              // for UNUSED
+#include <misc/macros.h>                  // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <misc/nvrm_drf.h>                // for NV_FLD_SET_DRF_NUM, NV_DRF_NUM
+#include <reg-access/reg-access.h>        // for readl, readl_base_offset
+
+/* Module-specific FSP headers */
+#include <i2c/i2c-config.h>               // for i2c_config_data
+#include <i2c/i2c-errors.h>               // for E_I2C_IO, E_I2C_ARB_LOST
+#include <i2c/i2c-hw-ops.h>               // for FSP__I2C__I2C_HW_OPS_H, i2c...
+#include <i2c/i2c-tegra.h>                // for i2c_tegra_handle, i2c_xfer_msg
+#include <i2c/i2c.h>                      // for I2C_BUS_BUSY, I2C_SCL_BUSY
+#include <processor/i2c-tegra-hw.h>       // for i2c_hw_handle, i2c_get_hw_h...
+#include <soc-common/i2c-defs.h>          // for I2C_TX_FIFO, I2C_FIFO_CONTROL
+#include <soc-common/i2c-dependencies.h>  // for appfw_udelay, appfw_timer_c...
+#ifdef I2C_ASYNC_XFER
+#include <i2c/i2c-tegra-async.h>          // for tegra_i2c_acquire, tegra_i2...
+#endif
+
+/** @file i2c-tegra.c */
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__NVRM_DRF_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_CONFIG_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_HW_OPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_TEGRA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__I2C_TEGRA_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__I2C_DEFS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__I2C_DEPENDENCIES_H, "Header file missing or invalid.")
+#ifdef I2C_ASYNC_XFER
+CT_ASSERT(FSP__I2C__I2C_TEGRA_ASYNC_H, "Header file missing or invalid.")
+#endif
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+#endif
+
+/* Custom Defines */
+/* Common apis need to be exposed to i2c-tegra-async.c */
+#ifdef I2C_ASYNC_XFER
+#define SUPPORT_APIS(x) x
+#else
+#define SUPPORT_APIS(x) static x
+#endif
+
+/**
+ * @defgroup I2C_INTERNAL_MACROS Macros internal to tegra i2c driver
+ * @{
+ */
+/** Convert Bytes to Words */
+#define CONV_TO_WORD_CEIL(x)            ((((x) % 4U) != 0U) ? \
+                                            (((x) / 4U) + 1U) : ((x) / 4U))
+
+/** Convert Seconds to Micro Seconds */
+#define I2C_SECONDS_TO_US               1000000ULL
+/** Register read polling delay in Micro Seconds */
+#define I2C_REG_POLL_DELAY_US           1U
+/** Register read polling timeout in Micro Seconds */
+#define I2C_REG_POLL_TIMEOUT_US         (2U * 1000U)
+/** Delay between CLK assert and Deassert */
+#define RESET_DELAY                     5U
+/** Bit field for stopping the transfer after current message */
+#define MSG_END_STOP                    0U
+/** Bit field to send repeated start after current message is transferred */
+#define MSG_END_REPEAT_START            1U
+/** Bit field to continue transfer without repeated start */
+#define MSG_END_CONTINUE                2U
+/**
+ * Magic value written to transfer return state variable before starting a
+ * transaction
+ * */
+#define TEGRA_I2C_ISR_RET_MAGIC         0xBABA
+/** msg is a read operation */
+#define msg_is_read(msg) (((uint32_t)(msg)->xfer_flags & I2C_XFER_FLAG_RD) != 0U)
+/** msg does not use repeated start for the transfer */
+#define msg_nostart(msg) (((uint32_t)(msg)->xfer_flags & I2C_XFER_FLAG_NOSTART) != 0U)
+/** msg continues without ACK from slave */
+#define msg_ignore_nak(msg) (((uint32_t)(msg)->xfer_flags & I2C_XFER_FLAG_IGNORE_NAK) != 0U)
+#define MASKED_REG_READ(x, mask) ((readl(x)) & (mask))
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx")
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_20_10, "Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx")
+#endif
+
+/** Assign prod settings based on selected mode */
+#define I2C_PRODS(_mode)                        \
+    .tlow = I2C_I2C_INTERFACE_TIMING_0_0_TLOW__PROD_C_##_mode,  \
+    .thigh = I2C_I2C_INTERFACE_TIMING_0_0_THIGH__PROD_C_##_mode, \
+    .tsu_sta = I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA__PROD_C_##_mode, \
+    .thd_sta = I2C_I2C_INTERFACE_TIMING_1_0_THD_STA__PROD_C_##_mode, \
+    .tsu_sto = I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO__PROD_C_##_mode, \
+    .tbuf = I2C_I2C_INTERFACE_TIMING_1_0_TBUF__PROD_C_##_mode, \
+    .thd_dat = I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT__PROD,  \
+    .mstr_tcapture = I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT__PROD, \
+    .slv_tcapture = I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT__PROD,
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_20_10, "Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx")
+#endif
+
+/** @} */
+
+/**
+ * @struct tegra_i2c_prod
+ * @brief Struct Definitions and Declarations
+ *
+ * @{
+ */
+struct tegra_i2c_prod {
+    /** Low period of the SCL clock */
+    uint32_t tlow;
+    /** High period of the SCL clock */
+    uint32_t thigh;
+    /** Set-up time for a Repeated START condition */
+    const uint32_t tsu_sta;
+    /** Hold time for a (repeated) START condition */
+    const uint32_t thd_sta;
+    /** Set-up time for STOP condition **/
+    const uint32_t tsu_sto;
+    /** Bus free time between STOP and START conditions */
+    const uint32_t tbuf;
+    /** Data hold time in SM/FM/Fm+ speed modes */
+    const uint32_t thd_dat;
+    /**
+     * Used to tune the Master Controller Data Capture Period. <br>
+     * Shifts the sampling point of SDA line by (Tcpature_dat+1) i2c_clk cycles
+     * from SCL rising edge. <br>
+     * 0 = This field is not used, SDA line is sampled on SCL rising edge. <br>
+     * Program to a value that is less than 3 or I2C_CLK_DIVISOR_STD_FAST_MODE
+     * or I2C_CLK_DIVISOR_HSMODE whichever is lower based on speed mode.
+     */
+    const uint32_t mstr_tcapture;
+    /**
+     * Used to tune the Slave Controller Data Capture Period. <br>
+     * Shifts the sampling point of SDA line by (Tcpature_dat+1) i2c_clk cycles
+     * from SCL rising edge. <br>
+     * 0 = This field is not used, SDA line is sampled on SCL rising edge. <br>
+     * Program to a value that is less than half (1/2) of SCL High time in
+     * number of i2c_clk cycles.
+     */
+    const uint32_t slv_tcapture;
+};
+/** @} */
+
+/* API definitions */
+/** @defgroup I2C_TEGRA_INTERNAL_APIS Internal Static APIs */
+/**
+ * @brief Return the remaining timeout in microseconds.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] timeout   Timeout value which should not exceed.
+ * @param[in] start     Timer value at the beginning of the transfer.
+ * @retval <value > 0>  Timeout remaining.
+ * @retval 0            Timeout reached/exceeded.0
+ */
+static uint32_t tegra_i2c_timeout_remaining(uint32_t timeout, uint64_t start)
+{
+    uint64_t timer_elapsed = 0ULL;
+    uint32_t ret = 0U;
+
+    timer_elapsed = appfw_timer_cur_us() - start;
+    if (timer_elapsed <= (uint64_t)timeout) {
+        ret = timeout - ((uint32_t)timer_elapsed);
+    }
+
+    return ret;
+}
+
+/**
+ * @brief Read from an I2C controller specific register.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_hw   i2c_hw_handle structure corresponding to the controller.
+ * @param[in] reg       Offset of the register to be read.
+ * @retval 32-bit_ret   Value read from the register.
+ */
+static uint32_t tegra_i2c_readl(const struct i2c_hw_handle *hi2c_hw,
+            uint32_t reg)
+{
+    return readl_base_offset(hi2c_hw->base, reg);
+}
+
+/**
+ * @brief Write to an I2C controller specific register.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_hw   i2c_hw_handle structure corresponding to the controller.
+ * @param[in] val       value to be written to the register.
+ * @param[in] reg       Offset of the register to be read.
+ */
+static void tegra_i2c_writel(const struct i2c_hw_handle *hi2c_hw, uint32_t val,
+            uint32_t reg)
+{
+    writel_base_offset(val, hi2c_hw->base, reg);
+}
+
+/**
+ * @brief Mask specific interrupt bits in the Interrupt mask register.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_hw   i2c_hw_handle structure corresponding to the controller.
+ * @param[in] mask      mask value to be written.
+ */
+static void tegra_i2c_mask_irq(const struct i2c_hw_handle *hi2c_hw, uint32_t mask)
+{
+    uint32_t int_mask = tegra_i2c_readl(hi2c_hw, I2C_INTERRUPT_MASK_REGISTER_0);
+
+    int_mask &= ~mask;
+    tegra_i2c_writel(hi2c_hw, int_mask, I2C_INTERRUPT_MASK_REGISTER_0);
+}
+
+/**
+ * @brief Unmask specific interrupt bits in the Interrupt mask register.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_hw   i2c_hw_handle structure corresponding to the controller.
+ * @param[in] mask      mask value to be written.
+ */
+static void tegra_i2c_unmask_irq(const struct i2c_hw_handle *hi2c_hw, uint32_t mask)
+{
+    uint32_t int_mask = tegra_i2c_readl(hi2c_hw, I2C_INTERRUPT_MASK_REGISTER_0);
+
+    int_mask |= mask;
+    tegra_i2c_writel(hi2c_hw, int_mask, I2C_INTERRUPT_MASK_REGISTER_0);
+}
+
+/**
+ * @brief Set/Clear specific bits from a register value.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_hw   i2c_hw_handle structure corresponding to the controller.
+ * @param[in] reg       Offset of the register to be read.
+ * @param[in] clr       Bits to be cleared.
+ * @param[in] set       Bits to be set.
+ */
+static void tegra_i2c_modifyl(const struct i2c_hw_handle *hi2c_hw, uint32_t reg,
+             uint32_t clr, uint32_t set)
+{
+    uint32_t value = readl_base_offset(hi2c_hw->base, reg);
+    value &= ~clr;
+    value |= set;
+    writel_base_offset(value, hi2c_hw->base, reg);
+}
+
+/**
+ * @brief Poll a specific register address for a value.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] address   address of the register to be read.
+ * @param[in] mask      mask for the register value.
+ * @param[in] value     Expected value.
+ * @param[in] timeout   Timeout for polling.
+ * @retval E_SUCCESS    Expected value read from the register.
+ * @retval E_FAULT      Expected value not read from the register.
+ */
+static error_t tegra_i2c_poll_reg(const uint32_t address, const uint32_t mask,
+                const uint32_t value, uint32_t timeout)
+{
+    INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+    error_t ret = E_FAULT;
+    uint64_t timer_start;
+    uint64_t timer_cur;
+
+    timer_start = appfw_timer_cur_us();
+    do {
+        if (MASKED_REG_READ(address, mask) == value) {
+            ret = E_SUCCESS;
+            break;
+        }
+        /*
+         * NOTE: no yield in interrupt state
+         * 10 times polled in the given timeout in non-interrupt mode.
+         */
+        appfw_udelay(I2C_REG_POLL_DELAY_US);
+        timer_cur = appfw_timer_cur_us();
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    } while ((timer_cur - timer_start) < timeout);
+
+    if (ret != E_SUCCESS) {
+        if (MASKED_REG_READ(address, mask) == value) {
+            ret = E_SUCCESS;
+        }
+    }
+
+    return ret;
+}
+
+/**
+ * @brief Apply prod settings corresponding to mode of operation.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ */
+static void tegra_i2c_apply_prod(const struct i2c_tegra_handle *hi2c_tegra)
+{
+    struct tegra_i2c_prod const *prod;
+    uint32_t val;
+
+    static struct tegra_i2c_prod prod_sm = {
+        I2C_PRODS(SM)
+    };
+
+    static struct tegra_i2c_prod prod_fm = {
+        I2C_PRODS(FM)
+    };
+
+    static struct tegra_i2c_prod prod_fmplus = {
+        I2C_PRODS(FMPLUS)
+    };
+
+    if (hi2c_tegra->pi2c_config->bus_clk_rate <= I2C_CLK_RATE_SM) {
+        prod = &prod_sm;
+    } else if (hi2c_tegra->pi2c_config->bus_clk_rate <= I2C_CLK_RATE_FM) {
+        prod = &prod_fm;
+    } else {
+        prod = &prod_fmplus;
+    }
+
+#ifdef CUSTOM_TIMING_PARAMS
+    /* Overwrite the timing parameters from FW configuration if valid */
+    if (hi2c_tegra->pi2c_config->thigh != UINT32_MAX) {
+        prod->thigh = hi2c_tegra->pi2c_config->thigh;
+    }
+    if (hi2c_tegra->pi2c_config->tlow != UINT32_MAX) {
+        prod->tlow = hi2c_tegra->pi2c_config->tlow;
+    }
+#endif
+
+    val = tegra_i2c_readl(hi2c_tegra->hi2c_hw, I2C_I2C_INTERFACE_TIMING_0_0);
+    val = NV_FLD_SET_DRF_NUM(I2C, I2C_INTERFACE_TIMING_0, TLOW,
+                                prod->tlow, val);
+    val = NV_FLD_SET_DRF_NUM(I2C, I2C_INTERFACE_TIMING_0, THIGH,
+                                prod->thigh, val);
+    tegra_i2c_writel(hi2c_tegra->hi2c_hw, val, I2C_I2C_INTERFACE_TIMING_0_0);
+
+    val = tegra_i2c_readl(hi2c_tegra->hi2c_hw, I2C_I2C_INTERFACE_TIMING_1_0);
+    val = NV_FLD_SET_DRF_NUM(I2C, I2C_INTERFACE_TIMING_1, TSU_STA,
+                                prod->tsu_sta, val);
+    val = NV_FLD_SET_DRF_NUM(I2C, I2C_INTERFACE_TIMING_1, THD_STA,
+                                prod->thd_sta, val);
+    val = NV_FLD_SET_DRF_NUM(I2C, I2C_INTERFACE_TIMING_1, TSU_STO,
+                                prod->tsu_sto, val);
+    val = NV_FLD_SET_DRF_NUM(I2C, I2C_INTERFACE_TIMING_1, TBUF,
+                                prod->tbuf, val);
+    tegra_i2c_writel(hi2c_tegra->hi2c_hw, val, I2C_I2C_INTERFACE_TIMING_1_0);
+
+    /* following registers are only in >t194 */
+    val = tegra_i2c_readl(hi2c_tegra->hi2c_hw, I2C_I2C_INTERFACE_TIMING_2_0);
+    val = NV_FLD_SET_DRF_NUM(I2C, I2C_INTERFACE_TIMING_2, THD_DAT,
+                                prod->thd_dat, val);
+    tegra_i2c_writel(hi2c_tegra->hi2c_hw, val, I2C_I2C_INTERFACE_TIMING_2_0);
+
+    val = tegra_i2c_readl(hi2c_tegra->hi2c_hw, I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0);
+    val = NV_FLD_SET_DRF_NUM(I2C, I2C_MSTR_DATA_CAPTURE_TIMING, TCAPTURE_DAT,
+                                prod->mstr_tcapture, val);
+    tegra_i2c_writel(hi2c_tegra->hi2c_hw, val, I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0);
+
+    val = tegra_i2c_readl(hi2c_tegra->hi2c_hw, I2C_I2C_SLV_DATA_CAPTURE_TIMING_0);
+    val = NV_FLD_SET_DRF_NUM(I2C, I2C_SLV_DATA_CAPTURE_TIMING, TCAPTURE_DAT,
+                                prod->slv_tcapture, val);
+    tegra_i2c_writel(hi2c_tegra->hi2c_hw, val, I2C_I2C_SLV_DATA_CAPTURE_TIMING_0);
+}
+
+/**
+ * @brief Configure the clock rate specified in the port layer.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ * @retval appfw_*_returns  return value from port layer apis.
+ * @retval E_INVALID_PARAM  Invalid configuration parameters.
+ */
+static error_t tegra_i2c_clock_conf(const struct i2c_tegra_handle *hi2c_tegra)
+{
+    int64_t  ret;
+    uint64_t val = 0U;
+    uint64_t t_val;
+    uint32_t clk_divider, x;
+    uint32_t tlow, thigh, reg;
+    const struct i2c_config_data *pi2c_config = hi2c_tegra->pi2c_config;
+    const struct i2c_hw_handle *hi2c_hw = hi2c_tegra->hi2c_hw;
+
+    ret = appfw_configure_ctrl_clk_rate(hi2c_hw->ctrl_id);
+    if (ret < 0) {
+        i2c_pr_error("%s: failed to configure requested clock rate, ret - %x\n",
+                        __func__, (int32_t)ret);
+        goto out;
+    }
+    val = (uint64_t)ret;
+
+    /* Read tlow and thigh from hardware */
+    reg = tegra_i2c_readl(hi2c_hw, I2C_I2C_INTERFACE_TIMING_0_0);
+    tlow = NV_DRF_VAL(I2C, I2C_INTERFACE_TIMING_0, TLOW, reg);
+    thigh = NV_DRF_VAL(I2C, I2C_INTERFACE_TIMING_0, THIGH, reg);
+
+    /*
+     * w.r.t T186_I2C_IAS 11.1.1
+     * bus_clk_rate = (source_clk) / (Tlow+Thigh+x)*(N+1)
+     * if N > 3 then x = 2
+     * if N <=3 then x = 3
+     * Solve for N, x with above eq
+     * if N > 3
+     * => N+1 > 4
+     * => (source_clk) / (bus_clk_rate) > 4(Tlow+Thigh)+8
+     * If above exp is true => x = 2 and N can be calculated.
+     * Similarly for N <= 3
+     */
+    x = ((val / pi2c_config->bus_clk_rate) > ((4U * (tlow + thigh)) + 8U))
+        ? 2U : 3U;
+
+    /*
+     * clk_divider value is rounded up so that we do not
+     * exceed the bus_clk_rate value
+     */
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    t_val = (val /
+                (((uint64_t)tlow + thigh + x) *
+                (uint64_t)pi2c_config->bus_clk_rate));
+    if (t_val > UINT32_MAX) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid t_val param\n", __func__);
+        goto out;
+    }
+    clk_divider = (uint32_t)t_val;
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    if ((val % (((uint64_t)tlow + thigh + x) *
+                (uint64_t)pi2c_config->bus_clk_rate)) != 0U) {
+        if (clk_divider != UINT32_MAX) {
+            clk_divider++;
+        }
+    }
+
+    /*
+     clk divisor is n+1 divisor, write n to the I2C_CLK_DIVISOR
+     register, hw increments it by 1.
+    */
+    if (clk_divider != 0U) {
+        clk_divider--;
+    }
+
+    if (pi2c_config->bus_clk_rate <= I2C_CLK_RATE_FMPLUS) {
+        clk_divider <<= I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT;
+    }
+
+    tegra_i2c_modifyl(hi2c_hw, I2C_CLK_DIVISOR, I2C_CLK_DIVISOR_STD_FAST_MASK,
+                            clk_divider);
+
+    tegra_i2c_writel(hi2c_hw, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
+
+out:
+    if (ret >= 0) {
+        ret = E_SUCCESS;
+    }
+
+    return (error_t)ret;
+}
+
+/**
+ * @brief Flush I2C Controller specific FIFOs.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_hw   i2c_hw_handle structure corresponding to the controller.
+ * @retval carry_return returns value returned from tegra_i2c_poll_reg().
+ */
+static error_t tegra_i2c_flush_fifos(const struct i2c_hw_handle *hi2c_hw)
+{
+    error_t err;
+
+    tegra_i2c_modifyl(hi2c_hw, I2C_FIFO_CONTROL, 0U,
+             I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH);
+
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    err = tegra_i2c_poll_reg(hi2c_hw->base + I2C_FIFO_CONTROL,
+            I2C_FIFO_CONTROL_TX_FLUSH | I2C_FIFO_CONTROL_RX_FLUSH,
+            0U, I2C_REG_POLL_TIMEOUT_US);
+    if (err != E_SUCCESS) {
+    }
+
+    return err;
+}
+
+/**
+ * @brief Load controller specific configuration.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_hw   i2c_hw_handle structure corresponding to the controller.
+ * @retval carry_return returns value returned from tegra_i2c_poll_reg().
+ */
+static error_t tegra_i2c_config_load(const struct i2c_hw_handle *hi2c_hw)
+{
+    error_t err;
+    uint32_t val;
+
+    val = NV_DRF_NUM(I2C, I2C_CONFIG_LOAD, MSTR_CONFIG_LOAD, 1U);
+    tegra_i2c_writel(hi2c_hw, val, I2C_I2C_CONFIG_LOAD_0);
+
+    /** I2C IAS section 7.1.1.5:
+     *
+     * SW has to wait until these bits are auto-cleared before
+     * going for any further programming. The wait time is not
+     * more than 100ns for apb_clk = 100MHz and i2c_clk =
+     * 100MHz. And at apb_clk = 20MHz and i2c_clk = 20MHz, it is
+     * not more than 500ns time.
+     */
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    err = tegra_i2c_poll_reg(hi2c_hw->base + I2C_I2C_CONFIG_LOAD_0,
+            I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_FIELD, 0U, I2C_REG_POLL_TIMEOUT_US);
+    if (err != E_SUCCESS) {
+    }
+
+    return err;
+}
+
+/**
+ * @brief Issue controller soft reset.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_hw   i2c_hw_handle structure corresponding to the controller.
+ */
+static void tegra_i2c_master_reset(const struct i2c_hw_handle *hi2c_hw)
+{
+    tegra_i2c_modifyl(hi2c_hw, I2C_MSTR_RESET, 0U, I2C_MSTR_SOFT_RESET);
+    appfw_udelay(2);
+    tegra_i2c_modifyl(hi2c_hw, I2C_MSTR_RESET, I2C_MSTR_SOFT_RESET, 0);
+    appfw_udelay(2);
+}
+
+/**
+ * @brief Copy data from RX FIFO to caller msg buffer.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_tegra       i2c_tegra_handle corresponding to the controller.
+ * @param[in] msg              pointer to message contents.
+ * @retval E_SUCCESS           data transferred to buffer from RX FIFO.
+ * @retval E_I2C_RX_FIFO_ERROR buffer length and RX FIFO data length mismatch.
+ */
+static error_t tegra_i2c_read_rx_msg(struct i2c_tegra_handle *hi2c_tegra,
+                                      const struct i2c_xfer_msg *msg)
+{
+    error_t ret = E_SUCCESS;
+    uint32_t i = 0U;
+    uint32_t cnt;
+    uint32_t val;
+    uint32_t rx_index = hi2c_tegra->rx_index;
+
+    /* check that RX fifo has (at least) expected amount of data */
+    val = tegra_i2c_readl(hi2c_tegra->hi2c_hw, I2C_MST_FIFO_STATUS_0);
+    cnt = NV_DRF_VAL(I2C, MST_FIFO_STATUS, RX_FIFO_FULL_CNT, val);
+
+    cnt = min(cnt, CONV_TO_WORD_CEIL(hi2c_tegra->bytes_to_xfer));
+
+    /* Stop when required number of (4 words) are read */
+    while (i < cnt) {
+        val = tegra_i2c_readl(hi2c_tegra->hi2c_hw, I2C_I2C_RX_FIFO_0);
+
+        if (rx_index < msg->buf_len) {
+            msg->prbuf[rx_index] = (uint8_t)(val & 0xffU);
+            ++rx_index;
+        }
+        if (rx_index < msg->buf_len) {
+            msg->prbuf[rx_index] = (uint8_t)((val >> 8U) & 0xffU);
+            ++rx_index;
+        }
+        if (rx_index < msg->buf_len) {
+            msg->prbuf[rx_index] = (uint8_t)((val >> 16U) & 0xffU);
+            ++rx_index;
+        }
+        if (rx_index < msg->buf_len) {
+            msg->prbuf[rx_index] = (uint8_t)((val >> 24U) & 0xffU);
+            ++rx_index;
+        }
+        ++i;
+    }
+
+    hi2c_tegra->rx_index = rx_index;
+    if (rx_index > msg->buf_len) {
+        ret = E_I2C_RX_FIFO_ERROR;
+        i2c_pr_error("%s: failed to read index %lu, buf_len - %hu, ret - 0x%x\n",
+                __func__, rx_index, msg->buf_len, (int32_t)ret);
+    } else {
+        hi2c_tegra->bytes_to_xfer = msg->buf_len - rx_index;
+    }
+
+    return ret;
+}
+
+/**
+ * @brief Create and send packet header for the message being transferred.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_tegra       i2c_tegra_handle corresponding to the controller.
+ * @param[in] xfer_msg         pointer to message contents.
+ * @param[in] msg_end          message end configuration<br>
+ *                              MSG_END_STOP, MSG_END_REPEAT_START, MSG_END_CONTINUE
+ * @retval E_SUCCESS           data transferred to buffer from RX FIFO.
+ * @retval E_I2C_RX_FIFO_ERROR buffer length and RX FIFO data length mismatch.
+ */
+static void tegra_i2c_send_packet_hdr(const struct i2c_tegra_handle *hi2c_tegra,
+                 const struct i2c_xfer_msg *xfer_msg,
+                 uint32_t msg_end)
+{
+    uint32_t xfer_packet_header;
+    uint32_t xfer_payload_size;
+    uint32_t xfer_io_header;
+
+    xfer_packet_header =
+        PACKET_HEADER0_PROTOCOL_I2C
+        | (hi2c_tegra->hi2c_hw->ctrl_id << PACKET_HEADER0_CONT_ID_SHIFT)
+        | (1UL << PACKET_HEADER0_PACKET_ID_SHIFT);
+
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-451, DR: SWE-FSP-046-SWSADR.docx");
+    xfer_payload_size = xfer_msg->buf_len - 1UL;
+
+    xfer_io_header = I2C_HEADER_IE;
+    xfer_io_header |=
+        ((msg_end == MSG_END_CONTINUE) ?
+          I2C_HEADER_CONTINUE_XFER :
+          ((msg_end == MSG_END_REPEAT_START) ?
+            I2C_HEADER_REPEAT_START : 0U));
+
+    xfer_io_header |=
+        (((xfer_msg->xfer_flags & I2C_XFER_FLAG_TEN) != 0U) ?
+          (uint32_t)(xfer_msg->dev_addr | I2C_HEADER_10BIT_ADDR) :
+          ((uint32_t)xfer_msg->dev_addr << I2C_HEADER_SLAVE_ADDR_SHIFT));
+
+    xfer_io_header |=
+        ((msg_ignore_nak(xfer_msg)) ? I2C_HEADER_CONT_ON_NAK : 0U);
+
+    xfer_io_header |=
+        ((msg_is_read(xfer_msg)) ? I2C_HEADER_READ : 0U);
+
+    xfer_io_header |=
+        ((hi2c_tegra->pi2c_config->bus_clk_rate == I2C_CLK_RATE_HS)
+            ? (I2C_HEADER_HIGHSPEED_MODE |
+                ((uint32_t)(hi2c_tegra->pi2c_config->hs_master_code & 0x7U)
+                << I2C_HEADER_MASTER_ADDR_SHIFT))
+            : 0U);
+
+    tegra_i2c_writel(hi2c_tegra->hi2c_hw, xfer_packet_header, I2C_TX_FIFO);
+    tegra_i2c_writel(hi2c_tegra->hi2c_hw, xfer_payload_size, I2C_TX_FIFO);
+    tegra_i2c_writel(hi2c_tegra->hi2c_hw, xfer_io_header, I2C_TX_FIFO);
+}
+
+/**
+ * @brief Copy data from msg buffer to TX FIFO.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_tegra       i2c_tegra_handle corresponding to the controller.
+ * @param[in] msg              pointer to message contents.
+ */
+static void tegra_i2c_send_tx_data(struct i2c_tegra_handle *hi2c_tegra,
+                                   const struct i2c_xfer_msg *msg)
+{
+    uint32_t i = 0U;
+    uint32_t cnt;
+    uint32_t val = 0U;
+    uint32_t tx_index = hi2c_tegra->tx_index;
+
+    cnt = min(msg->buf_len, 512U);
+
+    /* Stop when required number of (4 words) are written */
+    while (i < CONV_TO_WORD_CEIL(cnt)) {
+        if (tx_index < msg->buf_len) {
+            val = msg->pwbuf[tx_index];
+            ++tx_index;
+        }
+        if (tx_index < msg->buf_len) {
+            val |= (uint32_t)msg->pwbuf[tx_index] << 8U;
+            ++tx_index;
+        }
+        if (tx_index < msg->buf_len) {
+            val |= (uint32_t)msg->pwbuf[tx_index] << 16U;
+            ++tx_index;
+        }
+        if (tx_index < msg->buf_len) {
+            val |= (uint32_t)msg->pwbuf[tx_index] << 24U;
+            ++tx_index;
+        }
+        ++i;
+
+        tegra_i2c_writel(hi2c_tegra->hi2c_hw, val, I2C_I2C_TX_PACKET_FIFO_0);
+    }
+
+    hi2c_tegra->tx_index = tx_index;
+    hi2c_tegra->bytes_to_xfer = msg->buf_len - tx_index;
+}
+
+/**
+ * @brief Message end bit logic
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] next              next message to be transferred.
+ * @retval MSG_END_STOP         no more messages to transfer.
+ * @retval MSG_END_CONTINUE     continue without a repeated start.
+ * @retval MSG_END_REPEAT_START send repeat start after current message.
+ */
+static uint32_t msg_end_type(const struct i2c_xfer_msg *next)
+{
+    uint32_t msg_end;
+
+    if (next == NULL) {
+        msg_end = MSG_END_STOP;
+    } else if (msg_nostart(next)) {
+        msg_end = MSG_END_CONTINUE;
+    } else {
+        msg_end = MSG_END_REPEAT_START;
+    }
+
+    return msg_end;
+}
+
+/**
+ * @brief Configure and load configuration for the i2c controller.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ * @retval carry_return     return value returned from tegra_i2c_flush_fifos()
+ * @retval carry_return     return value returned from tegra_i2c_config_load()
+ */
+static error_t tegra_i2c_conf(const struct i2c_tegra_handle *hi2c_tegra)
+{
+    error_t err;
+    uint32_t val;
+
+    val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
+            I2C_CNFG_MULTI_MASTER_MODE;
+    if (hi2c_tegra->pi2c_config->bus_clk_rate <= I2C_CLK_RATE_FM) {
+        val |= ((uint32_t)0x2U << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
+    }
+
+    tegra_i2c_writel(hi2c_tegra->hi2c_hw, val, I2C_CNFG_REG);
+
+    err = tegra_i2c_flush_fifos(hi2c_tegra->hi2c_hw);
+    if (err != E_SUCCESS) {
+        i2c_pr_error("%s: failed to flush fifos, ret - 0x%x\n", __func__,
+                        (int32_t)err);
+        goto out;
+    }
+
+    err = tegra_i2c_config_load(hi2c_tegra->hi2c_hw);
+    /* The following test technically isn't needed because the return
+     * value falls through to return err.  However, without this test,
+     * MISRA generates a Directive 4.7 violation (required). */
+    if (err != E_SUCCESS) {
+        i2c_pr_error("%s: tegra_i2c_config_load failed\n", __func__);
+        goto out;
+    }
+
+    tegra_i2c_writel(hi2c_tegra->hi2c_hw, 0U, I2C_INTERRUPT_MASK_REGISTER_0);
+out:
+    return err;
+}
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+SUPPORT_APIS(error_t tegra_i2c_hw_init(const struct i2c_tegra_handle *hi2c_tegra))
+{
+    error_t err;
+
+    err = appfw_clk_reset_pulse(hi2c_tegra->ctrl_id, RESET_DELAY);
+    if (err != E_SUCCESS) {
+        i2c_pr_error("%s: appfw_clk_reset_pulse failed, ret - 0x%x\n", __func__,
+                        (int32_t)err);
+        goto out;
+    }
+
+    tegra_i2c_apply_prod(hi2c_tegra);
+
+    err = tegra_i2c_clock_conf(hi2c_tegra);
+    if (err != E_SUCCESS) {
+        i2c_pr_error("%s: tegra_i2c_clock_conf failed, ret - 0x%x\n", __func__,
+                        (int32_t)err);
+        goto out;
+    }
+
+    err = tegra_i2c_conf(hi2c_tegra);
+    if (err != E_SUCCESS) {
+        i2c_pr_error("%s: tegra_i2c_conf failed, ret - 0x%x\n", __func__,
+                        (int32_t)err);
+        goto out;
+    }
+
+    /* Programming trigger levels to 1 word. */
+    tegra_i2c_writel(hi2c_tegra->hi2c_hw, 0U, I2C_FIFO_CONTROL);
+
+    if (!hi2c_tegra->is_initialized) {
+        tegra_i2c_master_reset(hi2c_tegra->hi2c_hw);
+    }
+
+out:
+    return err;
+}
+#endif
+
+/**
+ * @brief Recover the state machine from Arbitration loss.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ */
+static void tegra_i2c_arb_lost_recovery(const struct i2c_tegra_handle *hi2c_tegra)
+{
+    uint32_t v = 0;
+
+    /* NOTE: all error return values in this function are
+     * intentionally suppressed. The I2C transaction is already
+     * failed. This routine tries to recover the bus with best effort
+     * principle */
+
+    if (!hi2c_tegra->hi2c_hw->is_multimaster) {
+        INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-1795, DR: SWE-FSP-062-SWSADR.docx");
+        UNUSED((tegra_i2c_hw_init(hi2c_tegra)));
+
+        v |= NV_DRF_NUM(I2C, I2C_BUS_CLEAR_CONFIG, BC_SCLK_THRESHOLD, 9U);
+        v |= NV_DRF_NUM(I2C, I2C_BUS_CLEAR_CONFIG, BC_STOP_COND, 1U);
+        v |= NV_DRF_NUM(I2C, I2C_BUS_CLEAR_CONFIG, BC_TERMINATE, 1U);
+
+        tegra_i2c_writel(hi2c_tegra->hi2c_hw, v, I2C_I2C_BUS_CLEAR_CONFIG_0);
+        INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-1795, DR: SWE-FSP-062-SWSADR.docx");
+        UNUSED((tegra_i2c_config_load(hi2c_tegra->hi2c_hw)));
+        v |= NV_DRF_NUM(I2C, I2C_BUS_CLEAR_CONFIG, BC_ENABLE, 1U);
+        tegra_i2c_writel(hi2c_tegra->hi2c_hw, v, I2C_I2C_BUS_CLEAR_CONFIG_0);
+        INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-1795, DR: SWE-FSP-062-SWSADR.docx");
+        UNUSED((tegra_i2c_config_load(hi2c_tegra->hi2c_hw)));
+
+        appfw_udelay(10U);
+        tegra_i2c_writel(hi2c_tegra->hi2c_hw, I2C_INT_BUS_CLEAR_DONE, I2C_INTERRUPT_STATUS_REGISTER_0);
+    }
+}
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+SUPPORT_APIS(error_t tegra_i2c_validate_msgs(const struct i2c_xfer_msg *msgs,
+                                                uint32_t num))
+{
+    error_t ret = 1;
+    uint32_t i;
+    const struct i2c_xfer_msg *msg;
+
+    if ((msgs == NULL) || (num == 0U)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid (%s) params, ret - 0x%x\n", __func__,
+                    (msgs == NULL) ? "msgs" : "num", (int32_t)ret);
+        goto out;
+    }
+
+    for (i = 0U; i < num; ++i) {
+        msg = &msgs[i];
+        if (msg->buf_len == 0U) {
+            INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+            ret = E_INVALID_PARAM;
+            i2c_pr_error("%s: msg[%lu] validation failed, ret - 0x%x\n",
+                            __func__, i, (int32_t)ret);
+            break;
+        }
+    }
+
+out:
+    return ret;
+}
+
+SUPPORT_APIS(error_t tegra_i2c_acquire(const struct i2c_tegra_handle *hi2c_tegra))
+{
+    error_t err;
+
+    /* In case of suspended state i2c-acquire should fail */
+    if (hi2c_tegra->is_suspended) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_INVALID_STATE;
+        i2c_pr_error("%s: controller in suspended state, ret - 0x%x\n", __func__,
+                        (int32_t)err);
+        goto out;
+    }
+
+    err = appfw_clk_enable(hi2c_tegra->ctrl_id);
+
+out:
+    return err;
+}
+
+SUPPORT_APIS(error_t tegra_i2c_release(const struct i2c_tegra_handle *hi2c_tegra))
+{
+    return appfw_clk_disable(hi2c_tegra->ctrl_id);
+}
+#endif
+
+/**
+ * @brief Return the interrupt status register value.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ * @retval reg_value        value read from the interrupt status register.
+ */
+static uint32_t tegra_i2c_intr_status(const struct i2c_tegra_handle *hi2c_tegra)
+{
+    uint32_t val;
+
+    val = tegra_i2c_readl(hi2c_tegra->hi2c_hw, I2C_INTERRUPT_STATUS_REGISTER_0);
+    /* Discard FIFO status interrupt bits, they are always
+     * masked and irrelevant to the logic of this driver */
+    val = NV_FLD_SET_DRF_NUM(I2C, INTERRUPT_STATUS_REGISTER, TFIFO_DATA_REQ, 0U, val);
+    val = NV_FLD_SET_DRF_NUM(I2C, INTERRUPT_STATUS_REGISTER, RFIFO_DATA_REQ, 0U, val);
+
+    return val;
+}
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+SUPPORT_APIS(error_t tegra_i2c_check_state(
+                            const struct i2c_tegra_handle *hi2c_tegra))
+{
+    error_t ret = E_SUCCESS;
+    uint32_t val;
+
+    /* expect that TX and RX fifos are empty */
+    val = tegra_i2c_readl(hi2c_tegra->hi2c_hw, I2C_MST_FIFO_STATUS_0);
+    if (val != NV_RESETVAL(I2C, MST_FIFO_STATUS)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_I2C_FIFO_STATUS;
+        i2c_pr_error("%s: TX/RX fifos not empty, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto out;
+    }
+
+    /* no interrupt should be pending */
+    if (tegra_i2c_intr_status((const struct i2c_tegra_handle *)hi2c_tegra)
+                    != 0U) {
+        ret = E_I2C_STALE_INT;
+        i2c_pr_error("%s: stale interrupts present, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+    }
+out:
+    return ret;
+}
+#endif
+
+/**
+ * @brief Disable packet mode for the i2c controller.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ */
+static void tegra_i2c_disable_packet_mode(const struct i2c_tegra_handle *hi2c_tegra)
+{
+    uint32_t val;
+
+    val = tegra_i2c_readl(hi2c_tegra->hi2c_hw, I2C_CNFG_REG);
+    val = val & ~I2C_CNFG_PACKET_MODE_EN;
+    tegra_i2c_writel(hi2c_tegra->hi2c_hw, val, I2C_CNFG_REG);
+    /* We will reinit hw again and the error returned can be ignored */
+    INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-383, DR: SWE-FSP-004-SWSADR.docx");
+    UNUSED(tegra_i2c_config_load(hi2c_tegra->hi2c_hw));
+}
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+void tegra_i2c_irq_handler(uint32_t ctrl_id)
+{
+    struct i2c_tegra_handle *hi2c_tegra = i2c_get_tegra_handle(ctrl_id);
+    const struct i2c_xfer_msg *cur = &hi2c_tegra->msgs[hi2c_tegra->msg_index];
+    error_t ret = E_SUCCESS;
+    uint32_t status;
+    bool end_xfer = false;
+
+    hi2c_tegra->xfer_status = I2C_XFER_IN_PROGRESS;
+    status = tegra_i2c_readl(hi2c_tegra->hi2c_hw, I2C_INTERRUPT_STATUS_REGISTER_0);
+    i2c_pr_debug("%s: interrupt status reg - 0x%lx\n", __func__, status);
+
+    if ((status & I2C_INT_NO_ACK) != 0U) {
+        tegra_i2c_disable_packet_mode(hi2c_tegra);
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_I2C_NACK;
+        i2c_pr_error("%s: NACK error - Slave not present, ret - 0x%x\n",
+                        __func__, (int32_t)ret);
+        end_xfer = true;
+        goto out;
+    }
+
+    if ((status & I2C_INT_ARB_LOST) != 0U) {
+        tegra_i2c_arb_lost_recovery(hi2c_tegra);
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_I2C_ARB_LOST;
+        i2c_pr_error("%s: ARB lost error, ret - 0x%x\n", __func__, ret);
+        end_xfer = true;
+        goto out;
+    }
+
+    if ((msg_is_read(cur)) && ((status & I2C_INT_RX_FIFO_DATA_REQ) != 0U)) {
+        if (hi2c_tegra->bytes_to_xfer > 0U) {
+            ret = tegra_i2c_read_rx_msg(hi2c_tegra, cur);
+            if (ret != E_SUCCESS) {
+                i2c_pr_error("%s: failed to read msg from RX FIFO, ret - 0x%x\n",
+                                __func__, (int32_t)ret);
+                end_xfer = true;
+            }
+        } else {
+            ret = E_I2C_RX_FIFO_UNDERFLOW;
+            i2c_pr_error("%s: RX FIFO underflow, ret - 0x%x\n", __func__,
+                            (int32_t)ret);
+            end_xfer = true;
+        }
+    }
+
+    if ((!msg_is_read(cur)) && ((status & I2C_INT_TX_FIFO_DATA_REQ) != 0U)) {
+        if (hi2c_tegra->bytes_to_xfer > 0U) {
+            tegra_i2c_send_tx_data(hi2c_tegra, cur);
+            ret = E_SUCCESS;
+        } else {
+            tegra_i2c_mask_irq(hi2c_tegra->hi2c_hw, I2C_INT_TX_FIFO_DATA_REQ);
+        }
+    }
+
+    if ((status & I2C_INT_PACKET_XFER_COMPLETE) != 0U) {
+        if (hi2c_tegra->bytes_to_xfer != 0U) {
+            ret = E_I2C_XFER_COMPLETE;
+        } else {
+            hi2c_tegra->msg_index++;
+            hi2c_tegra->bytes_to_xfer =
+                        hi2c_tegra->msgs[hi2c_tegra->msg_index].buf_len;
+            tegra_i2c_mask_irq(hi2c_tegra->hi2c_hw, I2C_INT_PACKET_XFER_COMPLETE);
+            ret = E_SUCCESS;
+            if (hi2c_tegra->msg_index < hi2c_tegra->num_msgs) {
+                /* We are only ending the current msg transfer here. */
+                end_xfer = true;
+            }
+        }
+    }
+
+    if ((status & I2C_INT_ALL_PACKETS_XFER_COMPLETE) != 0U) {
+        hi2c_tegra->xfer_status = I2C_XFER_COMPLETED;
+        end_xfer = true;
+    }
+
+out:
+    if (ret != E_SUCCESS) {
+        /* Error occured, mask all interrupts */
+        tegra_i2c_mask_irq(hi2c_tegra->hi2c_hw, I2C_INT_NO_ACK |
+                        I2C_INT_ARB_LOST | I2C_INT_PACKET_XFER_COMPLETE |
+                        I2C_INT_ALL_PACKETS_XFER_COMPLETE |
+                        I2C_INT_RX_FIFO_DATA_REQ |
+                        I2C_INT_TX_FIFO_DATA_REQ);
+    }
+
+    tegra_i2c_writel(hi2c_tegra->hi2c_hw, status, I2C_INTERRUPT_STATUS_REGISTER_0);
+
+    hi2c_tegra->end_xfer = end_xfer;
+    hi2c_tegra->isr_ret = ret;
+
+#ifdef I2C_ASYNC_XFER
+    if (hi2c_tegra->is_async_xfer &&
+            hi2c_tegra->end_xfer &&
+            (hi2c_tegra->async_xfer_cb != NULL)) {
+        hi2c_tegra->async_xfer_cb(hi2c_tegra->client_data, ret);
+    }
+#endif
+}
+#endif
+
+/**
+ * @brief Start the i2c transfer with the validated messages.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ * @param[in] cur           current message being transferred.
+ * @param[in] next          next message to be transferred.
+ */
+static void tegra_i2c_xfer_start(struct i2c_tegra_handle *hi2c_tegra,
+                              const struct i2c_xfer_msg *cur,
+                              const struct i2c_xfer_msg *next)
+{
+    uint32_t msg_end = msg_end_type(next);
+    uint32_t mask = I2C_INT_ARB_LOST |
+                    I2C_INT_NO_ACK |
+                    I2C_INT_TX_FIFO_OVERFLOW |
+                    I2C_INT_RX_FIFO_UNDERFLOW;
+
+    tegra_i2c_unmask_irq(hi2c_tegra->hi2c_hw, mask);
+
+    tegra_i2c_send_packet_hdr(hi2c_tegra, cur, msg_end);
+
+    if (!msg_is_read(cur)) {
+        tegra_i2c_send_tx_data(hi2c_tegra, cur);
+    } else {
+        mask |= I2C_INT_RX_FIFO_DATA_REQ;
+    }
+
+    mask |= I2C_INT_PACKET_XFER_COMPLETE;
+    tegra_i2c_unmask_irq(hi2c_tegra->hi2c_hw, mask);
+}
+
+/**
+ * @brief Poll the isr return value for successful transfer.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ * @param[in] timeout       polling timeout value.
+ * @param[in] delay         time to wait and start polling.
+ * @retval E_SUCCESS        Transfer successful.
+ * @retval E_TIMEOUT        poll timed out.
+ * @retval carry_return     returns error returned by appfw_wait_irq()
+ * @retval carry_return     returns error assigned in tegra_i2c_irq_handler()
+ */
+static error_t tegra_i2c_poll_isr_ret(const struct i2c_tegra_handle *hi2c_tegra,
+                                        uint32_t timeout, uint32_t delay)
+{
+    error_t ret = E_TIMEOUT;
+    uint64_t timer_start = appfw_timer_cur_us();
+    uint32_t timeout_remaining = timeout;
+#ifdef I2C_POLLING_XFER
+    uint32_t status;
+    uint32_t int_mask;
+#endif
+
+    do {
+#ifdef I2C_POLLING_XFER
+        appfw_udelay((timeout_remaining == timeout) ? delay :
+                                            I2C_REG_POLL_DELAY_US);
+
+        int_mask = tegra_i2c_readl(hi2c_tegra->hi2c_hw,
+                                        I2C_INTERRUPT_MASK_REGISTER_0);
+        status = tegra_i2c_readl(hi2c_tegra->hi2c_hw,
+                                    I2C_INTERRUPT_STATUS_REGISTER_0);
+        if ((status & int_mask) != 0U) {
+            tegra_i2c_irq_handler(hi2c_tegra->ctrl_id);
+            ret = hi2c_tegra->isr_ret;
+        }
+
+        if (hi2c_tegra->end_xfer) {
+            break;
+        }
+#else
+        /* Pass remaining timeout as available timeout */
+        ret = appfw_wait_irq(hi2c_tegra->ctrl_id, timeout_remaining);
+        if (ret == E_SUCCESS) {
+            ret = hi2c_tegra->isr_ret;
+        } else {
+            ret = E_TIMEOUT;
+        }
+
+        /* delay check is just to avoid misra and cert-c unused var errors */
+        if (hi2c_tegra->end_xfer || (delay > timeout)) {
+            break;
+        }
+#endif
+        timeout_remaining = tegra_i2c_timeout_remaining(timeout,
+                                                            timer_start);
+    } while (timeout_remaining > 0U);
+
+    return ret;
+}
+
+/**
+ * @brief process the return value from isr.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ * @param[in] timeout       timeout value for the transfer.
+ * @param[in] delay         time to wait and start processing the transfer.
+ * @retval E_SUCCESS        Transfer is successful.
+ * @retval carry_return     returns error returned by tegra_i2c_poll_isr_ret()
+ */
+static error_t tegra_i2c_process_xfer(const struct i2c_tegra_handle *hi2c_tegra,
+                                uint32_t timeout, uint32_t delay)
+{
+    error_t ret = E_SUCCESS;
+
+#ifndef I2C_POLLING_XFER
+    appfw_irq_enable(hi2c_tegra->ctrl_id);
+#endif
+    ret = tegra_i2c_poll_isr_ret(hi2c_tegra, timeout, delay);
+#ifndef I2C_POLLING_XFER
+    appfw_irq_disable(hi2c_tegra->ctrl_id);
+#endif
+
+    if (ret != E_SUCCESS) {
+        i2c_pr_error("%s: Polling for isr return failed\n", __func__);
+        /* Transfer return takes precedence */
+        INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-1795, DR: SWE-FSP-062-SWSADR.docx");
+        UNUSED(tegra_i2c_hw_init(hi2c_tegra));
+    }
+
+    return ret;
+}
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+SUPPORT_APIS(uint64_t tegra_i2c_xfer_one_msg(struct i2c_tegra_handle *hi2c_tegra,
+                            const struct i2c_xfer_msg *this,
+                            const struct i2c_xfer_msg *next))
+{
+    uint32_t bytes_to_xfer;
+    uint16_t buf_len_w;
+    uint32_t fifo_trig_words;
+    uint32_t fifo_trig = tegra_i2c_readl(hi2c_tegra->hi2c_hw, I2C_FIFO_CONTROL);
+    uint64_t wait_time;
+
+    /* Set state variables for each message */
+    hi2c_tegra->end_xfer = false;
+    hi2c_tegra->isr_ret = TEGRA_I2C_ISR_RET_MAGIC;
+    hi2c_tegra->rx_index = 0;
+    hi2c_tegra->tx_index = 0;
+
+    /* set trigger to one interrupt for all DATA REQ optimisation */
+    buf_len_w = CONV_TO_WORD_CEIL(this->buf_len);
+    fifo_trig_words = min(buf_len_w, I2C_FIFO_MAX_SIZE_W);
+    if (!msg_is_read(this)) {
+        fifo_trig &= fifo_trig_words << I2C_FIFO_CONTROL_TX_TRIG_SHIFT;
+    } else {
+        fifo_trig &= fifo_trig_words << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
+    }
+    tegra_i2c_writel(hi2c_tegra->hi2c_hw, fifo_trig, I2C_FIFO_CONTROL);
+
+    tegra_i2c_xfer_start(hi2c_tegra, this, next);
+
+    /*
+     * Wait time(in us) for data to be written on bus. Adding the packet
+     * header bytes in the calculation to account for HW delays in transfer
+     * initiation. The time needed for transferring 1B of data is 9 clock
+     * cycles.
+     *
+     * Note: This is not ideal wait time, but fixes most of the timing
+     * mismatches in HW while transferring more than one message. The
+     * trade-off on performance for the extra delay is negligible.
+     */
+    bytes_to_xfer = (I2C_PACKET_HEADER_SIZE_W + fifo_trig_words) * WORD_TO_BYTES;
+    wait_time = DIV_ROUND_UP(I2C_SECONDS_TO_US * bytes_to_xfer,
+            hi2c_tegra->pi2c_config->bus_clk_rate);
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    wait_time *= 9U;
+
+    return wait_time;
+}
+#endif
+
+/**
+ * @brief Transfer the messages one after another.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ * @param[in] msgs          messages to be transferred.
+ * @param[in] num_msgs      number of messages to be transferred.
+ * @param[in] timeout       timeout for the complete transfer.
+ * @retval E_SUCCESS        transfer completed successfully.
+ * @retval E_TIMEOUT        Timeout before successful transfer.
+ * @retval carry_return     returns error returned by tegra_i2c_process_xfer()
+ */
+static error_t tegra_i2c_xfer_msg_by_msg(struct i2c_tegra_handle *hi2c_tegra,
+                              struct i2c_xfer_msg *msgs, uint32_t num_msgs,
+                              uint32_t timeout)
+{
+    error_t ret;
+    uint32_t tmp;
+    const struct i2c_xfer_msg *this;
+    const struct i2c_xfer_msg *next;
+    uint64_t timer_start = appfw_timer_cur_us();
+    uint32_t timeout_remaining = timeout;
+    uint64_t wait_time;
+
+    hi2c_tegra->msgs = msgs;
+    hi2c_tegra->num_msgs = num_msgs;
+    hi2c_tegra->msg_index = 0;
+
+    for (tmp = 0U; tmp < num_msgs; tmp++) {
+        this = &msgs[tmp];
+        next = ((tmp + 1U) < num_msgs) ? &msgs[tmp + 1U] : NULL;
+
+        hi2c_tegra->bytes_to_xfer = this->buf_len;
+        wait_time = tegra_i2c_xfer_one_msg(hi2c_tegra, this, next);
+
+        timeout_remaining = tegra_i2c_timeout_remaining(timeout, timer_start);
+        i2c_pr_debug("%s: Processing msg[%d], timeout remaining - %d\n",
+                     __func__, tmp, timeout_remaining);
+
+        if ((timeout_remaining > 0U) &&
+                (wait_time < (uint64_t)timeout_remaining)) {
+            ret = tegra_i2c_process_xfer(hi2c_tegra, timeout_remaining,
+                                         (uint32_t)wait_time);
+        } else {
+            ret = E_TIMEOUT;
+            i2c_pr_error("%s: transfer timedout. msgs xfered(%lu)."
+                   " remaining(%lu), ret - 0x%x\n",
+                            __func__, tmp, num_msgs - tmp, (int32_t)ret);
+        }
+
+        if (ret != E_SUCCESS) {
+            i2c_pr_error("%s: msg[%lu] failed to xfer, ret - 0x%x\n", __func__,
+                            tmp, (int32_t)ret);
+            break;
+        }
+        hi2c_tegra->xfer_status = I2C_XFER_IN_PROGRESS;
+    }
+
+    return ret;
+}
+
+/**
+ * @brief Function definition for i2c_hw_xfer typedef function pointer.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ * @param[in] msgs          messages to be transferred.
+ * @param[in] num_msgs      number of messages to be transferred.
+ * @param[in] timeout       timeout for the complete transfer.
+ * @retval E_SUCCESS        transfer completed successfully.
+ * @retval carry_return     returns error returned by tegra_i2c_acquire()
+ * @retval carry_return     returns error returned by tegra_i2c_check_state()
+ * @retval carry_return     returns error returned by tegra_i2c_validate_msgs()
+ * @retval carry_return     returns error returned by tegra_i2c_xfer_msg_by_msg()
+ * @retval carry_return     returns error returned by tegra_i2c_release()
+ */
+static error_t tegra_i2c_xfer(struct i2c_tegra_handle *hi2c_tegra,
+                              struct i2c_xfer_msg *msgs, uint32_t num_msgs,
+                              uint32_t timeout)
+{
+    error_t ret;
+    error_t tmp;
+
+#ifdef I2C_ASYNC_XFER
+    hi2c_tegra->is_async_xfer = false;
+    hi2c_tegra->async_xfer_cb = NULL;
+    hi2c_tegra->client_data = NULL;
+    hi2c_tegra->xfer_status = I2C_XFER_REQUESTED;
+#endif
+
+    ret = tegra_i2c_acquire(hi2c_tegra);
+    if (ret != E_SUCCESS) {
+        i2c_pr_error("%s: failed to acquire controller, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto out;
+    }
+
+    ret = tegra_i2c_check_state(hi2c_tegra);
+    if (ret != E_SUCCESS) {
+        /* Assuming the worst possible scenario in the previous transfer */
+        INLINE_RFD(MISRA, DEVIATE, Directive_4_7, "Approval: JIRA TID-1795, DR: SWE-FSP-062-SWSADR.docx");
+        UNUSED((tegra_i2c_hw_init(hi2c_tegra)));
+        i2c_pr_error("%s: i2c hw not ready for transfer, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto release;
+    }
+
+    ret = tegra_i2c_validate_msgs(msgs, num_msgs);
+    if (ret < 0) {
+        i2c_pr_error("%s: msgs validation failed, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto release;
+    }
+
+    ret = tegra_i2c_xfer_msg_by_msg(hi2c_tegra, msgs, num_msgs,
+                                        timeout);
+
+release:
+    tmp = tegra_i2c_release(hi2c_tegra);
+    if (tmp != E_SUCCESS) {
+        i2c_pr_error("%s: failed to release controller, ret - 0x%x\n", __func__,
+                        (int32_t)tmp);
+        ret = (ret == E_SUCCESS) ? tmp : ret;
+    }
+
+out:
+    return ret;
+}
+
+/**
+ * @brief Function definition for i2c_get_bus_status typedef function pointer.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ * @param[out] state        state of the bus as defined in I2C_HW_BUS_STATUS
+ * @retval E_SUCCESS        bus state returned successfully.
+ * @retval carry_return     returns error returned by tegra_i2c_acquire()
+ * @retval carry_return     returns error returned by tegra_i2c_release()
+ */
+static error_t tegra_i2c_get_bus_state(const struct i2c_tegra_handle *hi2c_tegra,
+                    uint32_t *state)
+{
+    error_t ret;
+    uint32_t bus_status;
+    *state = 0U;
+
+    ret = tegra_i2c_acquire(hi2c_tegra);
+    if (ret != E_SUCCESS) {
+        i2c_pr_error("%s: failed to acquire controller, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto out;
+    }
+
+    bus_status = tegra_i2c_readl(hi2c_tegra->hi2c_hw, I2C_BUS_STATUS);
+
+    ret = tegra_i2c_release(hi2c_tegra);
+    if (ret != E_SUCCESS) {
+        i2c_pr_error("%s: failed to release controller, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto out;
+    }
+
+    if ((bus_status & I2C_BUS_STATUS_SCL_MASK) != 0U) {
+        *state |= I2C_SCL_BUSY;
+    }
+
+    if ((bus_status & I2C_BUS_STATUS_SDA_MASK) != 0U) {
+        *state |= I2C_SDA_BUSY;
+    }
+
+    if ((bus_status & I2C_BUS_STATUS_BUSY_MASK) != 0U) {
+        *state |= I2C_BUS_BUSY;
+    }
+
+out:
+    return ret;
+}
+
+/**
+ * @brief Function definition for i2c_hw_suspend typedef function pointer.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ * @retval E_SUCCESS        bus state returned successfully.
+ * @retval E_INVALID_PARAM  Invalid hi2c_tegra structure data.
+ * @retval E_INVALID_STATE  Controller already suspended.
+ */
+static error_t tegra_i2c_suspend(struct i2c_tegra_handle *hi2c_tegra)
+{
+    error_t ret = E_SUCCESS;
+
+    if ((hi2c_tegra == NULL) || (hi2c_tegra->hi2c_hw == NULL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid (%s) params, ret - 0x%x\n", __func__,
+                        (hi2c_tegra == NULL) ? "hi2c_tegra" :
+                            "hi2c_tegra->hi2c_hw", (int32_t)ret);
+        goto out;
+    }
+
+    if (hi2c_tegra->is_suspended) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_STATE;
+        i2c_pr_error("%s: controller already suspended, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto out;
+    }
+
+    hi2c_tegra->is_suspended = true;
+out:
+    return ret;
+}
+
+/**
+ * @brief Function definition for i2c_hw_suspend typedef function pointer.
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ * @retval E_SUCCESS        bus state returned successfully.
+ * @retval E_INVALID_PARAM  Invalid hi2c_tegra structure data.
+ * @retval E_INVALID_STATE  Controller not in suspended state.
+ * @retval carry_return     returns error returned by tegra_i2c_acquire()
+ * @retval carry_return     returns error returned by tegra_i2c_hw_init()
+ * @retval carry_return     returns error returned by tegra_i2c_release()
+ */
+static error_t tegra_i2c_resume(struct i2c_tegra_handle *hi2c_tegra)
+{
+    error_t ret = E_SUCCESS;
+    error_t tmp = E_SUCCESS;
+
+    if (hi2c_tegra == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_PARAM;
+        i2c_pr_error("%s: hi2c_tegra not declared, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+        goto out;
+    }
+
+    if (!hi2c_tegra->is_suspended) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_INVALID_STATE;
+        i2c_pr_error("%s: controller not in suspended state, ret - 0x%x\n",
+                        __func__, (int32_t)ret);
+        goto out;
+    }
+
+    /* Allow access to HW */
+    hi2c_tegra->is_suspended = false;
+
+    ret = tegra_i2c_acquire(hi2c_tegra);
+    if (ret == E_SUCCESS) {
+        ret = tegra_i2c_hw_init(hi2c_tegra);
+        if(ret != E_SUCCESS) {
+            i2c_pr_error("%s: tegra_i2c_hw_init failed, ret - 0x%x\n", __func__,
+                            (int32_t)ret);
+        }
+    } else {
+        i2c_pr_error("%s: failed to acquire controller, ret - 0x%x\n", __func__,
+                        (int32_t)ret);
+    }
+
+    tmp = tegra_i2c_release(hi2c_tegra);
+    if (tmp != E_SUCCESS) {
+        i2c_pr_error("%s: failed to release controller, ret - 0x%x", __func__,
+                        (int32_t)tmp);
+        ret = (ret == E_SUCCESS) ? tmp : ret;
+    }
+
+out:
+    if (hi2c_tegra != NULL) {
+        hi2c_tegra->is_suspended = (ret != E_SUCCESS);
+    }
+    return ret;
+}
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+error_t tegra_i2c_pre_init(uint32_t ctrl_id, struct i2c_tegra_handle *hi2c_tegra)
+{
+    error_t err = E_SUCCESS;
+
+    hi2c_tegra->ctrl_id = ctrl_id;
+    hi2c_tegra->hi2c_hw = i2c_get_hw_handle(ctrl_id);
+    hi2c_tegra->pi2c_config = i2c_get_config_data(ctrl_id);
+
+    if ((hi2c_tegra->hi2c_hw == NULL) ||
+        (hi2c_tegra->pi2c_config == NULL)) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        err = E_INVALID_PARAM;
+        i2c_pr_error("%s: invalid (%s) params provided, ret - 0x%x\n", __func__,
+                    (hi2c_tegra->hi2c_hw == NULL) ? "hi2c_tegra->hi2c_hw" :
+                        "hi2c_tegra->pi2c_config", (int32_t)err);
+    }
+
+    hi2c_tegra->pre_init_done = true;
+
+    return err;
+}
+
+error_t tegra_i2c_init(uint32_t ctrl_id, struct i2c_tegra_handle *hi2c_tegra,
+                struct i2c_hw_ops **hw_ops)
+{
+    error_t err = E_SUCCESS;
+    error_t tmp = E_SUCCESS;
+    static struct i2c_hw_ops tegra_hw_ops = {
+        .xfer = &tegra_i2c_xfer,
+#ifdef I2C_ASYNC_XFER
+        .start_async_xfer = &tegra_i2c_start_async_xfer,
+        .finish_async_xfer = &tegra_i2c_finish_async_xfer,
+#endif
+        .suspend = &tegra_i2c_suspend,
+        .resume = &tegra_i2c_resume,
+        .get_bus_state = &tegra_i2c_get_bus_state,
+    };
+
+    /* Setting to default values */
+    hi2c_tegra->is_initialized = false;
+    hi2c_tegra->is_suspended = false;
+    *hw_ops = NULL;
+
+    if (!hi2c_tegra->pre_init_done) {
+        err = tegra_i2c_pre_init(ctrl_id, hi2c_tegra);
+        if (err != E_SUCCESS) {
+            i2c_pr_error("%s: tegra_i2c_pre_init failed, ret - 0x%x\n", __func__,
+                            (int32_t)err);
+            goto out;
+        }
+    }
+
+    err = tegra_i2c_acquire(hi2c_tegra);
+    if (err == E_SUCCESS) {
+        err = tegra_i2c_hw_init(hi2c_tegra);
+    } else {
+        i2c_pr_error("%s: failed to acquire mutex, ret - 0x%x\n", __func__,
+                        (int32_t)err);
+    }
+
+    tmp = tegra_i2c_release(hi2c_tegra);
+    if (tmp != E_SUCCESS) {
+        i2c_pr_error("%s: failed to release mutex, ret - 0x%x\n", __func__,
+                        (int32_t)tmp);
+        err = (err == E_SUCCESS) ? tmp : err;
+    }
+
+    if (err == E_SUCCESS) {
+        hi2c_tegra->is_initialized = true;
+        *hw_ops = &tegra_hw_ops;
+    }
+
+out:
+    return err;
+}
+#endif
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/i2c/module-i2c-config.mk b/spe-freertos-bsp/fsp/source/drivers/i2c/module-i2c-config.mk
new file mode 100644
index 0000000..4a7f5af
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/i2c/module-i2c-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-i2c-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_I2C_CONFIG               := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_I2C_DEPENDS              := SOC CLUSTER CPL OSA FSP_COMMON
+$(foreach _,$(MODULE_I2C_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_I2C_DRIVERS_DIR           = $(FSP_COMMON_REPO)/drivers/i2c
+MODULE_I2C_SOURCE_DIR            = $(MODULE_I2C_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_I2C_INCLUDES              =
diff --git a/spe-freertos-bsp/fsp/source/drivers/i2c/module-i2c.mk b/spe-freertos-bsp/fsp/source/drivers/i2c/module-i2c.mk
new file mode 100644
index 0000000..bc654a1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/i2c/module-i2c.mk
@@ -0,0 +1,69 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-i2c.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_I2C_NAME                 := I2C
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_I2C_DEFINED              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_I2C_DEPENDS              := I2C SOC CPL OSA TKE
+$(foreach _,$(CONFIG_I2C_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_I2C_C_SRC                 =
+MODULE_I2C_C_SRC                += $(MODULE_I2C_DRIVERS_DIR)/i2c-core.c
+MODULE_I2C_C_SRC                += $(MODULE_I2C_DRIVERS_DIR)/i2c-tegra.c
+ifeq ($(I2C_ASYNC_XFER), 1)
+MODULE_I2C_C_SRC                += $(MODULE_I2C_DRIVERS_DIR)/i2c-core-async.c
+MODULE_I2C_C_SRC                += $(MODULE_I2C_DRIVERS_DIR)/i2c-tegra-async.c
+endif
+MODULE_I2C_C_SRC                += $(CPL_SOC_PORT)/i2c-port.c
+MODULE_I2C_C_SRC                += $(CPL_SOC_IDS)/i2c-tegra-ids.c
+
+#
+# Assembly source
+MODULE_I2C_ASM_SRC               = $(CPL_SOC_PORT)/i2c-irq.S
+
+#
+# Special C Flags
+MODULE_I2C_C_FLAGS               =
+
+#
+# Special ASM Flags
+MODULE_I2C_ASM_FLAGS             =
diff --git a/spe-freertos-bsp/fsp/source/drivers/lib/module-lib-nosafety-config.mk b/spe-freertos-bsp/fsp/source/drivers/lib/module-lib-nosafety-config.mk
new file mode 100644
index 0000000..4bd623a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/lib/module-lib-nosafety-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-lib-config-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_LIB_NOSAFETY_CONFIG              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_LIB_NOSAFETY_DEPENDS             := SOC CLUSTER CPL OSA FSP_COMMON
+$(foreach _,$(MODULE_LIB_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_LIB_NOSAFETY_DRIVERS_DIR          = $(FSP_COMMON_REPO)/drivers/lib
+MODULE_LIB_NOSAFETY_SOURCE_DIR           = $(MODULE_LIB_NOSAFETY_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_LIB_NOSAFETY_INCLUDES             =
diff --git a/spe-freertos-bsp/fsp/source/drivers/lib/module-lib-nosafety.mk b/spe-freertos-bsp/fsp/source/drivers/lib/module-lib-nosafety.mk
new file mode 100644
index 0000000..2bad888
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/lib/module-lib-nosafety.mk
@@ -0,0 +1,62 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-lib-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_LIB_NOSAFETY_NAME                := LIB_NOSAFETY
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_LIB_NOSAFETY_DEFINED             := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_LIB_NOSAFETY_DEPENDS             := LIB_NOSAFETY SOC CPL OSA DEBUG_NOSAFETY
+$(foreach _,$(CONFIG_LIB_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_LIB_NOSAFETY_C_SRC                =
+MODULE_LIB_NOSAFETY_C_SRC               += $(MODULE_LIB_NOSAFETY_DRIVERS_DIR)/stack-guard.c
+
+#
+# Assembly source
+MODULE_LIB_NOSAFETY_ASM_SRC              =
+
+#
+# Special C Flags
+MODULE_LIB_NOSAFETY_C_FLAGS              =
+
+#
+# Special ASM Flags
+MODULE_LIB_NOSAFETY_ASM_FLAGS            =
diff --git a/spe-freertos-bsp/fsp/source/drivers/lib/stack-guard.c b/spe-freertos-bsp/fsp/source/drivers/lib/stack-guard.c
new file mode 100644
index 0000000..bc07644
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/lib/stack-guard.c
@@ -0,0 +1,140 @@
+/* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file stack-guard.c
+ * @brief Implementation of stack guard
+ *
+ * Provides implementations of the data and functions necessary for
+ * the compiler to generate stack guard code when any version of the
+ * -fstack-protector compiler switches is specified for any of the files.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                    // for uintptr_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>            // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <debug/abort-sys-codes.h>     // for ABORT_STACK, FSP__DEBUG__ABORT...
+#include <debug/abort.h>               // for tegra_abort, FSP__DEBUG__ABORT_H
+#include <misc/attributes.h>           // for NO_RETURN
+#include <misc/macros.h>               // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <lib/sections-stack-guard.h>  // Immune from CT_ASSERT protection
+#include <lib/stack-guard.h>           // for FSP__LIB__STACK_GUARD_H, __sta...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                CERTC, DEVIATE, DCL37_C, "Approval:  Bug 2731179, DR: SWE-FSP-036-SWSADR.docx")
+CT_ASSERT(FSP__DEBUG__ABORT_SYS_CODES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ABORT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__LIB__STACK_GUARD_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @brief Initial Stack Check Value
+ *
+ * The value that will be placed on the stack of a function that upon
+ * exit will be checked if any version of -fstack-guard is specified
+ * on the command line of the compiler.
+ *
+ * This value is here so that the variable __stack_chk_guard is
+ * always initialized to a non-zero value.
+ */
+#define STACK_CHK_GUARD_VALUE   ((uintptr_t)(0xDEADBEEFUL))
+
+/**
+ * @brief Stack Variable
+ *
+ * Contains the value that will be used to place a guard value on the
+ * stack and again to check that value when a function is about to return.
+ *
+ * It will be initialized to a non-zero value but it is expected that
+ * the application code will overwrite the contentes with a randomized
+ * value during initialization.
+ */
+extern uintptr_t __stack_chk_guard;
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_9, "Approval: Bug 200532001, DR: SWE-FSP-016-SWSADR.docx")
+INLINE_RFD(MISRA, DEVIATE, Rule_21_2, "Approval: JIRA TID-1063, DR: SWE-FSP-053-SWSADR.docx")
+uintptr_t __stack_chk_guard     SECTION_STACKGUARD_DATA  = STACK_CHK_GUARD_VALUE;
+
+/**
+ * @brief Initialize Stack Guard Variable
+ *
+ * This function will initialize the stack guard variable with the
+ * supplied value.  This allows the application a means to initialize
+ * the stack check variable with a (hopefully) randomized value.
+ *
+ * @param[in] check_value  Value to be used to check if the stack has
+ *                         been overwritten.
+ *
+ * @return None
+ */
+SECTION_STACKGUARD_INIT_TEXT void
+stack_chk_init(uintptr_t check_value)
+{
+    __stack_chk_guard = check_value;
+}
+
+
+/**
+ * @brief Stack Check Failure
+ *
+ * Called when the guard value on the stack has been overwritten.
+ *
+ * @return Does not return
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_21_2, "Approval: JIRA TID-1063, DR: SWE-FSP-053-SWSADR.docx")
+NO_RETURN SECTION_STACKGUARD_TEXT void __stack_chk_fail(void)
+{
+    uint8_t             stack;
+
+    tegra_abort(ABORT_STACK, (uint32_t)&stack);
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_9, "Approval: Bug 200532001, DR: SWE-FSP-016-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              CERTC, DEVIATE, DCL37_C, "Approval:  Bug 2731179, DR: SWE-FSP-036-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/libc-lite/memops.c b/spe-freertos-bsp/fsp/source/drivers/libc-lite/memops.c
new file mode 100644
index 0000000..142c10c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/libc-lite/memops.c
@@ -0,0 +1,134 @@
+/**
+* @file memops.c
+*
+* @brief Exposes a handful of libc-lite utility functions used by other
+*        modules.
+*
+* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* * Neither the name of NVIDIA CORPORATION nor the names of its
+* contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#include <stddef.h>
+#include <stdint.h>
+#include <misc/ct-assert.h>
+#include <misc/macros.h>
+
+#include <cpu/type-conversion.h>
+#include <libc-lite/libc.h>
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_6, "Approval: Bug 200543266, DR: SWE-FSP-003-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                MISRA, DEVIATE, Rule_21_2, "Approval: Jira TID-1970, DR: SWE-FSP-066-SWSADR.docx",
+                CERTC, DEVIATE, DCL37_C, "Approval: Bug 2731179, DR: SWE-FSP-067-SWSADR.docx")
+
+
+void *memcpy(void *dst, const void *src, size_t n)
+{
+    START_RFD_BLOCK(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx")
+    char *d = (char *)(dst);
+    const char *s = (const char *)(src);
+    END_RFD_BLOCK(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx")
+
+    // CERTC INT30 fix - integer wrap-around
+    // MISRA RULE 14.4 fix - return essential boolean type
+    for (size_t j=n; j > 0U ; j--)
+    {
+        *d = *s;
+
+        // MISRA RULE 13.3 fix - increment separated from pointer dereference
+        d++;
+        s++;
+    }
+
+    return dst;
+}
+
+int memcmp(const void *s1, const void *s2, size_t n)
+{
+    START_RFD_BLOCK(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx")
+    const uint8_t *d = (const uint8_t *)(s1);
+    const uint8_t *s = (const uint8_t *)(s2);
+    END_RFD_BLOCK(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx")
+    int32_t cmp = 0;
+
+    // CERTC INT30 fix - integer wrap-around
+    // MISRA RULE 14.4 fix - return essential boolean type
+    for (size_t j=n ; j > 0U ; j--)
+    {
+        // MISRA RULE 10.3 fix - explicit conversion to int32_t
+        int32_t x = (int32_t)(*s) - (int32_t)(*d);
+
+        // MISRA RULE 14.4 fix - return essential boolean type
+        if (x != 0)
+        {
+            // MISRA RULE 15.5 fix - temp var to pass to return statement
+            cmp = x;
+            break;
+        }
+
+        // MISRA RULE 13.3 fix - increment separated from pointer dereference
+        d++;
+        s++;
+    }
+
+    return cmp;
+}
+
+void *memset(void *s, int c, size_t n)
+{
+    INLINE_RFD(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx");
+    uint8_t *p = (uint8_t *)(s);
+    uint8_t set_c;
+
+    // check "c" and clip to max value if out of bounds
+    if (c > UINT8_MAX)
+    {
+        set_c = UINT8_MAX;
+    }
+    else
+    {
+        set_c = (uint8_t)c;
+    }
+
+    // CERTC INT30 fix - integer wrap-around
+    // MISRA RULE 14.4 fix - return essential boolean type
+    for (size_t j=n ; j > 0U ; j--)
+    {
+        *p = set_c;
+
+        // MISRA RULE 13.3 fix - increment separated from pointer dereference
+        p++;
+    }
+
+    return s;
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_6, "Approval: Bug 200543266, DR: SWE-FSP-003-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              MISRA, DEVIATE, Rule_21_2, "Approval: Jira TID-1970, DR: SWE-FSP-066-SWSADR.docx",
+              CERTC, DEVIATE, DCL37_C, "Approval: Bug 2731179, DR: SWE-FSP-067-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/libc-lite/module-libc-lite-config.mk b/spe-freertos-bsp/fsp/source/drivers/libc-lite/module-libc-lite-config.mk
new file mode 100644
index 0000000..0fc4684
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/libc-lite/module-libc-lite-config.mk
@@ -0,0 +1,54 @@
+#
+# Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile utilities message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-libc-lite-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to
+#   VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_LIBC_LITE_CONFIG                 := 1
+
+#
+# Define a something similar to header guard protection...for makefiles
+# instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_LIBC_LITE_DEFINED                := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_LIBC_LITE_DEPENDS                := CPL
+$(foreach _,$(MODULE_LIBC_LITE_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_LIBC_LITE_DRIVERS_DIR             = $(FSP_COMMON_REPO)/drivers/libc-lite
+MODULE_LIBC_LITE_SOURCE_DIR              = $(MODULE_LIBC_LITE_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_LIBC_LITE_INCLUDES                =
diff --git a/spe-freertos-bsp/fsp/source/drivers/libc-lite/module-libc-lite.mk b/spe-freertos-bsp/fsp/source/drivers/libc-lite/module-libc-lite.mk
new file mode 100644
index 0000000..883b768
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/libc-lite/module-libc-lite.mk
@@ -0,0 +1,63 @@
+#
+# Copyright (c) 2021-2023, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile utility functions
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-libc-lite.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to
+#   VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_LIBC_LITE_NAME                   := LIBC_LITE
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_LIBC_LITE_DEFINED                := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_LIBC_LITE_DEPENDS                := LIBC_LITE CPL
+$(foreach _,$(CONFIG_LIBC_LITE_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_LIBC_LITE_C_SRC                   =
+
+MODULE_LIBC_LITE_C_SRC                  += $(MODULE_LIBC_LITE_DRIVERS_DIR)/memops.c
+
+#
+# Assembly source
+MODULE_LIBC_LITE_ASM_SRC                 =
+
+#
+# Special C Flags
+MODULE_LIBC_LITE_C_FLAGS                 =
+
+#
+# Special ASM Flags
+MODULE_LIBC_LITE_ASM_FLAGS               =
diff --git a/spe-freertos-bsp/fsp/source/drivers/lic/lic-tegra.c b/spe-freertos-bsp/fsp/source/drivers/lic/lic-tegra.c
new file mode 100644
index 0000000..075103d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/lic/lic-tegra.c
@@ -0,0 +1,427 @@
+/*
+ * Copyright (c) 2020-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                // for bool, false
+#include <stddef.h>                 // for NULL
+#include <stdint.h>                 // for uint32_t, uint8_t, UINT8_MAX, UIN...
+                                    // IWYU pragma: no_include <errno.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>         // for CT_ASSERT
+#include <soc-common/hw-const.h>    /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>        // for NV_ADDRESS_MAP_LIC_BASE
+#include <arintr_ctlr.h>            // for INTR_CTLR_CHANNEL0_SLICE0_IER_0...
+
+/* Late FSP headers */
+#include <error/common-errors.h>    // for E_SUCCESS, error_t
+#include <misc/bitops.h>            // for BIT, bit_number, FSP__MISC__BITOPS_H
+#include <reg-access/reg-access.h>  // for readl_base_offset, writel_base_of...
+#include <irq/safe-irqs.h>          // for in_interrupt, enter_critical, exi...
+#include <misc/macros.h>            // for ARRAY_SIZE,...
+
+/* Module-specific FSP headers */
+#include <lic/lic-errors.h>         // for E_LIC_ERR_NULL_PTR, E_LIC_ERR_NO_...
+#include <lic/lic-tegra-priv.h>     // for tegra_lic_id, ...
+#include <lic/lic-tegra.h>          // for tegra_lic_int, ...
+#include <lic/sections-lic.h>       // for SECTION_LIC_TEXT, ...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx")
+    CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__LIC__LIC_ERRORS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__LIC__LIC_TEGRA_PRIV_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__LIC__LIC_TEGRA_H, "Header file missing or invalid.")
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx")
+#define LIC_IER_REG         INTR_CTLR_CHANNEL0_SLICE0_IER_0
+#define LIC_IER_SET_REG     INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0
+#define LIC_IER_CLR_REG     INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0
+#define LIC_IDR_REG         INTR_CTLR_CHANNEL0_SLICE0_IDR_0
+#define LIC_IEP_CLASS_REG   INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0
+#define LIC_VIRQ_REG        INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0
+#define LIC_VFIQ_REG        INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0
+
+#define LIC_CHAN_OFFSET \
+    (INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0 - INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0)
+#define LIC_SLICE_OFFSET \
+    (INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0 - INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx")
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx")
+
+static inline uint32_t
+lic_reg(uint32_t offset)
+{
+    INLINE_RFD(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx", CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-451, DR: SWE-FSP-046-SWSADR.docx");
+    return (NV_ADDRESS_MAP_LIC_BASE + offset);
+}
+
+static inline uint32_t
+lic_chan_slice_reg(uint8_t chan, uint8_t slice, uint32_t offset)
+{
+    INLINE_RFD(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx", CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-451, DR: SWE-FSP-046-SWSADR.docx");
+    return ((chan * LIC_CHAN_OFFSET) + (slice * LIC_SLICE_OFFSET) + offset);
+}
+
+static inline uint32_t
+lic_slice_reg(uint32_t reg, uint8_t slice)
+{
+    INLINE_RFD(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx", CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-451, DR: SWE-FSP-046-SWSADR.docx");
+    return reg + (slice * LIC_SLICE_OFFSET);
+}
+
+static inline uint32_t
+lic_ier_set(uint8_t chan, uint8_t slice)
+{
+
+    return lic_reg(lic_chan_slice_reg(chan, slice, LIC_IER_SET_REG));
+}
+
+static inline uint32_t
+lic_ier_clr(uint8_t chan, uint8_t slice)
+{
+
+    return lic_reg(lic_chan_slice_reg(chan, slice, LIC_IER_CLR_REG));
+}
+
+static inline uint32_t
+lic_iep_class(uint8_t chan, uint8_t slice)
+{
+    return lic_reg(lic_chan_slice_reg(chan, slice, LIC_IEP_CLASS_REG));
+}
+
+static inline uint32_t
+lic_virq(uint8_t chan, uint8_t slice)
+{
+    return lic_reg(lic_chan_slice_reg(chan, slice, LIC_VIRQ_REG));
+}
+
+static inline uint32_t
+lic_vfiq(uint8_t chan, uint8_t slice)
+{
+    return lic_reg(lic_chan_slice_reg(chan, slice, LIC_VFIQ_REG));
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx", MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
+SECTION_LIC_TEXT void tegra_lic_irq_handler(void *data)
+{
+    INLINE_RFD(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx");
+    const lic_irq_context_t   *ctx = (lic_irq_context_t *)data;
+    const struct tegra_lic_id *id  = ctx->id;
+    uint8_t                   chan = ctx->chan;
+    uint32_t                  virq[LIC_MAX_SLICES];
+    uint8_t                   slice = 0;
+    uint32_t                  slice_map = 0;
+    uint32_t                  lic_irq, irq;
+    uint32_t                  mask;
+    uint32_t                  irqs_left = ctx->irqs_set;
+    uint32_t                  reg;
+    irq_callback_fn           isr_handler;
+
+    reg = ctx->is_vfiq ? lic_vfiq(chan, slice) : lic_virq(chan, slice);
+
+    while (irqs_left != 0UL) {
+        lic_irq = bit_number(irqs_left);
+        INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-449, Example-4, DR: SWE-FSP-045-SWSADR.docx");
+        irq = lic_irq + id->conf.lic_irq_base;
+        slice = id->lic_map[lic_irq].slice;
+        mask = BIT32_FN(id->lic_map[lic_irq].bit);
+        isr_handler = id->lic_map[lic_irq].routine;
+
+        if ((slice_map & BIT32_FN(slice)) == 0UL) {
+            virq[slice] = readl(lic_slice_reg(reg, slice));
+            slice_map = BIT32_FN(slice);
+        }
+
+        if ((virq[slice] & mask) != 0UL) {
+            if (isr_handler != NULL) {
+                isr_handler(id->lic_map[lic_irq].cb_data);
+            } else {
+                irq_handler(irq);
+            }
+        }
+
+        irqs_left &= ~BIT32_FN(lic_irq);
+    }
+
+}
+
+SECTION_LIC_TEXT error_t
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
+tegra_lic_irq_enable(const struct tegra_lic_id *id,
+                     uint32_t irq)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t lic_irq;
+    uint32_t irq_line;
+    uint8_t  chan;
+
+    if (id == NULL) {
+        ret = E_LIC_NULL_PTR;
+        goto out;
+    }
+
+    if (irq < id->conf.lic_irq_base) {
+        ret = E_LIC_INVALID_IRQ;
+        goto out;
+    }
+
+    lic_irq = irq - id->conf.lic_irq_base;
+    if (lic_irq >= id->lic_map_size) {
+        ret = E_LIC_INVALID_IRQ;
+        goto out;
+    }
+
+    irq_line = id->lic_map[lic_irq].local_irq - (uint32_t)id->conf.local_irq_base;
+    if (irq_line > id->num_lic_irq_lines) {
+        ret = E_LIC_INVALID_IRQ;
+        goto out;
+    }
+    chan = id->irq_contexts[irq_line]->chan;
+
+    if (!in_interrupt()) {
+        enter_critical();
+    }
+
+    writel(BIT32_FN(id->lic_map[lic_irq].bit),
+           lic_ier_set(chan, id->lic_map[lic_irq].slice));
+
+    if (!in_interrupt()) {
+        exit_critical();
+    }
+
+out:
+    return ret;
+}
+
+SECTION_LIC_TEXT error_t
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
+tegra_lic_irq_disable(const struct tegra_lic_id *id,
+                      uint32_t irq)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t lic_irq;
+    uint32_t irq_line;
+    uint8_t  chan;
+
+    if (id == NULL) {
+        ret = E_LIC_NULL_PTR;
+        goto out;
+    }
+
+    if (irq < id->conf.lic_irq_base) {
+        ret = E_LIC_INVALID_IRQ;
+        goto out;
+    }
+
+    lic_irq = irq - id->conf.lic_irq_base;
+    if (lic_irq >= id->lic_map_size) {
+        ret = E_LIC_INVALID_IRQ;
+        goto out;
+    }
+
+    irq_line = id->lic_map[lic_irq].local_irq - (uint32_t)id->conf.local_irq_base;
+    if (irq_line > id->num_lic_irq_lines) {
+        ret = E_LIC_INVALID_IRQ;
+        goto out;
+    }
+    chan = id->irq_contexts[irq_line]->chan;
+
+    if (!in_interrupt()) {
+        enter_critical();
+    }
+
+    writel(BIT32_FN(id->lic_map[lic_irq].bit),
+           lic_ier_clr(chan, id->lic_map[lic_irq].slice));
+
+    if (!in_interrupt()) {
+        exit_critical();
+    }
+
+out:
+    return ret;
+}
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_15_4, "Approval: Bug 200532006, DR: SWE-FSP-029-SWSADR.docx")
+static error_t
+tegra_lic_validate_irq_context(const struct tegra_lic_id *id)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t i;
+    uint32_t chan;
+    uint8_t  max_chan;
+
+    for (i = 0UL; i < id->num_lic_irq_lines; i += 1UL) {
+        if (id->irq_contexts[i] == NULL) {
+            ret = E_LIC_INVALID_PARAM;
+            goto out;
+        }
+
+        chan  = id->irq_contexts[i]->chan;
+        max_chan = id->conf.base_chan;
+        max_chan += id->conf.num_chans;
+        if ((chan < id->conf.base_chan) || (chan >= max_chan)) {
+            ret = E_LIC_INVALID_PARAM;
+            goto out;
+        }
+
+        id->irq_contexts[i]->irqs_set = 0UL;
+    }
+
+out:
+    return ret;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_15_4, "Approval: Bug 200532006, DR: SWE-FSP-029-SWSADR.docx")
+
+static void
+tegra_lic_configure_lic_map(const struct tegra_lic_id *id)
+{
+    const lic_irq_context_t *irq_ctx;
+    uint32_t                i;
+    uint8_t                 chan;
+    uint32_t                iep;
+    bool                    is_vfiq;
+    uint16_t                irq_line;
+    uint8_t                 slice;
+
+    for (i = 0UL; i < id->lic_map_size; i += 1UL) {
+        slice = id->lic_map[i].slice;
+        irq_line = id->lic_map[i].local_irq;
+        INLINE_RFD(CERTC, DEVIATE, INT30_C,"Approval: JIRA TID-449, Example-4, DR: SWE-FSP-045-SWSADR.docx");
+        irq_line -= id->conf.local_irq_base;
+        irq_ctx = id->irq_contexts[irq_line];
+        chan  = irq_ctx->chan;
+        is_vfiq = irq_ctx->is_vfiq;
+
+        iep = readl(lic_iep_class(chan, slice));
+
+        if (is_vfiq) {
+            iep |= BIT32_FN(id->lic_map[i].bit);
+        }
+        writel(iep, lic_iep_class(chan, slice));
+
+        writel(BIT32_FN(id->lic_map[i].bit), lic_ier_clr(chan, slice));
+
+        id->irq_contexts[irq_line]->irqs_set |= BIT(i);
+    }
+
+}
+
+static error_t
+tegra_lic_set_irq_handlers(const struct tegra_lic_id *id)
+{
+    lic_irq_context_t *irq_ctx;
+    uint32_t          i;
+    uint32_t          local_irq;
+    error_t           ret = E_SUCCESS;
+
+    for (i = 0UL; i < id->num_lic_irq_lines; i += 1UL) {
+        irq_ctx = id->irq_contexts[i];
+        local_irq = id->conf.local_irq_base + i;
+
+        ret = irq_safe_set_handler(local_irq, tegra_lic_irq_handler, (void*)irq_ctx);
+        if (ret == E_SUCCESS) {
+            ret = irq_safe_enable(local_irq);
+        }
+        if (ret != E_SUCCESS) {
+            break;
+        }
+    }
+  
+    return ret;
+}
+
+SECTION_LIC_INIT_TEXT error_t
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
+tegra_lic_init(struct tegra_lic_id *id,
+               const lic_irq_t *lic_map,
+               const uint32_t lic_map_size)
+{
+    error_t  ret = E_SUCCESS;
+
+    if (id == NULL) {
+        ret = E_LIC_NULL_PTR;
+        goto out;
+    }
+
+    if (id->conf.num_chans == 0UL) {
+        ret = E_LIC_NO_CHANS;
+        goto out;
+    }
+
+    if ((lic_map == NULL) || (lic_map_size == 0UL)) {
+        ret = E_LIC_NO_MAP;
+        goto out;
+    }
+    id->lic_map = lic_map;
+    id->lic_map_size = lic_map_size;
+
+    if (id->num_lic_irq_lines == 0UL) {
+        ret = E_LIC_NO_IRQ;
+        goto out;
+    }
+
+    if (id->num_lic_irq_lines != (id->conf.num_chans * 2UL)) {
+        ret = E_LIC_INVALID_PARAM;
+        goto out;
+    }
+
+    ret = tegra_lic_validate_irq_context(id);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    tegra_lic_configure_lic_map(id);
+
+    ret = tegra_lic_set_irq_handlers(id);
+
+out:
+    return ret;
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/lic/module-lic-config.mk b/spe-freertos-bsp/fsp/source/drivers/lic/module-lic-config.mk
new file mode 100644
index 0000000..174b5b2
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/lic/module-lic-config.mk
@@ -0,0 +1,54 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-lic-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to
+#   VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_LIC_CONFIG               := 1
+
+#
+# Define a something similar to header guard protection...for makefiles
+# instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_LIC_DEFINED              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_LIC_DEPENDS              := SOC CLUSTER CPL
+$(foreach _,$(MODULE_LIC_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_LIC_DRIVERS_DIR           = $(FSP_COMMON_REPO)/drivers/lic
+MODULE_LIC_SOURCE_DIR            = $(MODULE_LIC_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_LIC_INCLUDES              =
diff --git a/spe-freertos-bsp/fsp/source/drivers/lic/module-lic.mk b/spe-freertos-bsp/fsp/source/drivers/lic/module-lic.mk
new file mode 100644
index 0000000..fd6eb6e
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/lic/module-lic.mk
@@ -0,0 +1,64 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-lic.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to
+#   VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_LIC_NAME                 := LIC
+
+#
+# Define a something similar to header guard protection...for makefiles
+# instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_LIC_DEFINED              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_LIC_DEPENDS              := LIC SOC CPL
+$(foreach _,$(CONFIG_LIC_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_LIC_C_SRC                 =
+MODULE_LIC_C_SRC                += $(MODULE_LIC_DRIVERS_DIR)/lic-tegra.c
+MODULE_LIC_C_SRC                += $(CPL_SOC_IDS)/lic-tegra-ids.c
+
+#
+# Assembly source
+MODULE_LIC_ASM_SRC               = $(CPL_SOC_PORT)/lic-irq.S
+
+#
+# Special C Flags
+MODULE_LIC_C_FLAGS               =
+
+#
+# Special ASM Flags
+MODULE_LIC_ASM_FLAGS             =
diff --git a/spe-freertos-bsp/fsp/source/drivers/logger/logger.c b/spe-freertos-bsp/fsp/source/drivers/logger/logger.c
new file mode 100644
index 0000000..a1605c8
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/logger/logger.c
@@ -0,0 +1,389 @@
+/*
+ * Copyright (c) 2019-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                 // for bool, false, true
+#include <stdint.h>                  // for uint32_t, uint8_t, uint16_t, uin...
+#include <string.h>                  // for NULL, memcpy
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>          // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <osa/rtos-task.h>           // for rtosTaskEnterCritical, rtosTaskE...
+#include <debug/assert.h>            // for ASSERT, FSP__DEBUG__ASSERT_H
+#include <irq/safe-irqs.h>           // for in_interrupt, FSP__IRQ__SAFE_IRQS_H
+#include <misc/attributes.h>         // for WEAK, FSP__MISC__ATTRIBUTES_H
+#include <misc/bitops.h>             // for LOW32
+#include <misc/macros.h>             // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <tke/tke-tegra.h>           // for tegra_tke_get_tsc64
+
+/* Module-specific FSP headers */
+#include <logger-config.h>           // Immune from CT_ASSERT protection
+#include <logger/logger-private.h>   // for log_buff_t, LEB_STATE_EMPTY, LEB...
+#include <logger/logger.h>           // for FSP__LOGGER__LOGGER_H, log_entry
+#include <logger/sections-logger.h>  // Immune from CT_ASSERT protection
+#include <logger/logger-data.h>      // for log_entry_t, log_arg_t, log_meta...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ASSERT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__TKE__TKE_TEGRA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__LOGGER__LOGGER_PRIVATE_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__LOGGER__LOGGER_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__LOGGER__LOGGER_DATA_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+log_buff_t      log_buffers[NUM_LOG_BUFFERS]            SECTION_LOG_BSS;
+uint32_t        cur_buff_num            SECTION_LOG_DATA      = 0;
+log_buff_t      *log_cur_buff           SECTION_LOG_DATA      = NULL;
+uint32_t        dropped_log_entries     SECTION_LOG_DATA      = 0;
+
+uint32_t log_level                      SECTION_LOG_DATA
+                                        = DEFAULT_LOG_LEVEL;
+
+/*
+ * Define the print hook as a weak symbol so that if the application wants
+ * to define it with an initializer, that will take precedence.
+ */
+log_hook_t      log_print_hook          WEAK SECTION_LOG_DATA;
+
+/**
+ * log_set_level_mask()       - set the level mask for logging
+ *
+ * @mask:       mask of the levels that will cause log entries to be emitted
+ *
+ * This function will set the mask of the levels that will allow log entries
+ * to be emitted.
+ *
+ * Return Values:
+ *      none
+ */
+SECTION_LOG_ADMIN_TEXT void
+log_set_level_mask(const uint32_t mask)
+{
+    log_level = mask;
+}
+
+/**
+ * log_get_level_mask()       - get the current level mask for logging
+ *
+ * This function will return the current mask of the levels used for logging.
+ *
+ * Return Values:
+ *      current level mask
+ */
+SECTION_LOG_ADMIN_TEXT uint32_t
+log_get_level_mask(void)
+{
+    return(log_level);
+}
+
+/**
+ * log_buffer_empty()          - make a log buffer appear empty
+ *
+ * @buff:       pointer to the log buffer that is to be initialized to the
+ *              empty state.
+ *
+ * This function will initialize a log_buff_t to be in the empty state.
+ * This function should be called anytime that a log buffer is to be reset
+ * to its empty state.
+ *
+ * Return Values:
+ *      none.
+ */
+SECTION_LOG_TEXT static void
+log_buffer_empty(log_buff_t * const buff)
+{
+    ASSERT(buff != NULL);
+
+    buff->next = 0;
+    buff->state = LEB_STATE_EMPTY;
+    buff->remaining = LOG_BUFFER_SIZE;
+}
+
+/**
+ * log_buffer_switch()        - switch to a new buffer if necessary
+ *
+ * @buff:       pointer to the current buffer
+ *
+ * This function determines if the current buffer can be used for storing
+ * additional log entries.  If the current buffer cannot be used, it will
+ * switch to using another buffer.
+ *
+ * If the new buffer is chosen its contents will be overwritten (that is
+ * when it is chosen, the buffer will be set to the empty state).  The only
+ * time that this does not occur is if the buffer is being copied.  In which
+ * case any new log entries will be dropped until there is a buffer that is
+ * available.
+ *
+ * Return Values:
+ *      NULL            no buffers are available (they're in the copying
+ *                      state)
+ *      others          pointer to a buffer that can be used to store log
+ *                      entries.
+ */
+SECTION_LOG_TEXT static log_buff_t *
+log_buffer_switch(log_buff_t * const buff)
+{
+    log_buff_t          *new_buff       = buff;
+    uint32_t            buff_num;
+
+    ASSERT(buff != NULL);
+
+    switch (new_buff->state) {
+    case LEB_STATE_EMPTY:
+    case LEB_STATE_PARTIAL:
+        /*
+         * OK to use the current buffer.
+         */
+        break;
+
+    case LEB_STATE_FULL:
+    case LEB_STATE_TOCOPY:
+    case LEB_STATE_COPYING:
+        /*
+         * Have to switch to the next buffer
+         */
+        buff_num = (cur_buff_num + 1) % NUM_LOG_BUFFERS;
+        new_buff = &log_buffers[buff_num];
+        if ((new_buff->state == LEB_STATE_TOCOPY)
+            || (new_buff->state == LEB_STATE_COPYING)) {
+            /*
+             * Cannot touch a buffer that's actively being
+             * copied.  So we'll have to drop any trace points
+             * until the copy has completed.
+             */
+            new_buff = NULL;
+        } else {
+            log_buffer_empty(new_buff);
+            cur_buff_num = buff_num;
+            log_cur_buff = new_buff;
+        }
+        break;
+    }
+
+    return new_buff;
+}
+
+/**
+ * log_buffer_get()           - get a buffer to use to hold log entries
+ *
+ * This function will return a pointer to a log buffer that can be used
+ * to hold log entries.
+ *
+ * Return Values:
+ *      NULL            no buffers are available
+ *      others          pointer to a buffer that can be used to store log
+ *                      entries.
+ */
+SECTION_LOG_TEXT static log_buff_t *
+log_buffer_get(void)
+{
+    log_buff_t  *buff   = NULL;
+
+    /*
+     * Handle initialization
+     */
+    if (log_cur_buff == NULL) {
+        cur_buff_num = 0;
+        log_cur_buff = &log_buffers[0];
+        buff = log_cur_buff;
+        log_buffer_empty(buff);
+    } else {
+        /*
+         * Make sure that the current buffer can be used.
+         * If not, move to another one.
+         */
+        buff = log_buffer_switch(log_cur_buff);
+    }
+
+    return buff;
+}
+
+/**
+ * log_entry() -        add a log entry
+ *
+ * @token:              pointer to the meta-data structure for the log entry
+ * @n_args:             number of actual args in log_args_t structure
+ * @args:               pointer to a log_args_t structure
+ *
+ * This function will add a log entry into a log buffer.  It will construct
+ * a log entry and attempt to place it in to a log buffer.
+ *
+ * Return Values:
+ *      none
+ */
+SECTION_LOG_TEXT void
+log_entry(const log_metadata_t * const token,
+          const uint8_t n_args,
+          log_args_t args)
+{
+    log_buff_t          *buff           = NULL;
+    log_entry_t         *lep;
+    uint8_t             *le_args;
+    uint64_t            now;
+    bool                full            = false;
+    bool                from_isr;
+    uint32_t            le_size;
+
+    ASSERT(token != NULL);
+    ASSERT(args != NULL);
+
+    from_isr = in_interrupt();
+
+    if (!from_isr) {
+        rtosTaskEnterCritical();
+    }
+
+    /*
+     * Determine if there is a print "hook"
+     */
+    if ((log_print_hook != NULL)
+        && ((token->flags & LOG_FL_PRINT) != 0)) {
+        (*log_print_hook)(token, n_args, args);
+        goto out;
+    }
+
+    buff = log_buffer_get();
+    if (buff == NULL) {
+        /*
+         * There are no buffers that have space for any
+         * log entries, so just drop this log entry on
+         * the floor.
+         */
+        dropped_log_entries += 1;
+        goto out;
+    }
+
+    /*
+     * See if there is enough space in the current buffer
+     * for the new log entry.
+     */
+    le_size = sizeof(log_entry_t) + (n_args * sizeof(log_arg_t));
+    if (le_size > buff->remaining) {
+        /*
+         * Mark the current buffer as full and queue it
+         */
+        buff->state = LEB_STATE_FULL;
+        log_buffer_push(buff);
+
+        /*
+         * Get a new buffer
+         */
+        buff = log_buffer_get();
+        if (buff == NULL) {
+            /*
+             * There are no buffers that have space for any
+             * trace points, so just drop this trace point
+             * on the floor.
+             */
+            dropped_log_entries += 1;
+            goto out;
+        }
+    }
+
+    lep = (log_entry_t *)&buff->buffer[buff->next];
+    buff->next += le_size;
+
+    if (buff->next >= LOG_BUFFER_SIZE) {
+        buff->state = LEB_STATE_FULL;
+        full = true;
+    }
+
+    now = tegra_tke_get_tsc64();
+
+    if (buff->state == LEB_STATE_EMPTY) {
+        buff->start_time = now;
+        buff->last_time = now;
+        buff->state = LEB_STATE_PARTIAL;
+    }
+
+    lep->delta_time = LOW32(now - buff->last_time);
+    buff->last_time = now;
+
+    lep->token = (log_token_t)token;
+    lep->n_bytes = (uint16_t)le_size;
+    lep->n_fixed_args = 0;
+    lep->fixed_flags = 0;
+    if (n_args > 0) {
+        le_args = ((uint8_t *)lep) + sizeof(log_entry_t);
+        memcpy(le_args, args, n_args * sizeof(log_arg_t));
+    }
+
+  out:
+    if (!from_isr) {
+        if (full) {
+            log_buffer_push(buff);
+        }
+
+        rtosTaskExitCritical();
+    }
+
+    return;
+}
+
+/**
+ * log_buffer_push()            - pushes a log buffer to memory
+ *
+ * @buff:               Buffer to be pushed
+ *
+ * This function will push a buffer to memory so that it is visible to
+ * the rest of the system.
+ *
+ * This particular version is a "stub".  It does not do anything to the
+ * buffer, so it will be re-used when selected again.
+ * It has a "weak" linkage so that the application can implement its own
+ * version.
+ */
+SECTION_LOG_TEXT WEAK void
+log_buffer_push(log_buff_t * const buff)
+{
+    (void)buff;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/logger/module-logger-nosafety-config.mk b/spe-freertos-bsp/fsp/source/drivers/logger/module-logger-nosafety-config.mk
new file mode 100644
index 0000000..b9ccb78
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/logger/module-logger-nosafety-config.mk
@@ -0,0 +1,45 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-logger-nosafety-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_LOGGER_NOSAFETY_CONFIG           := 1
+
+#
+# Location of source code files
+LOGGER_DIR                               = $(FSP_COMMON_REPO)/drivers/logger
+MODULE_LOGGER_NOSAFETY_SOURCE_DIR        = $(LOGGER_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_LOGGER_NOSAFETY_INCLUDES          =
+
+#
+# Configuration options.  These can be specified to control how the firmware
+# is built.  Setting the option=1 (e.g. DEBUG=1) will enable the option and
+# setting the option to 0 (e.g. DEBUG=0) will disable the option.
+#
+# DEFAULT_LOG_LEVEL     Serves as a divisor to help calculate clock
+#                               rate.
+#
+DEFAULT_LOG_LEVEL                       ?= 0
diff --git a/spe-freertos-bsp/fsp/source/drivers/logger/module-logger-nosafety.mk b/spe-freertos-bsp/fsp/source/drivers/logger/module-logger-nosafety.mk
new file mode 100644
index 0000000..1553018
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/logger/module-logger-nosafety.mk
@@ -0,0 +1,65 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-logger-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_LOGGER_NOSAFETY_NAME             := LOGGER_NOSAFETY
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_LOGGER_NOSAFETY_DEFINED          := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_LOGGER_NOSAFETY_DEPENDS          := LOGGER_NOSAFETY SOC CPL OSA DEBUG_NOSAFETY TKE
+$(foreach _,$(CONFIG_LOGGER_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_LOGGER_NOSAFETY_C_SRC             =
+MODULE_LOGGER_NOSAFETY_C_SRC            += $(LOGGER_DIR)/logger.c
+
+#
+# Assembly source
+MODULE_LOGGER_NOSAFETY_ASM_SRC           =
+
+#
+# Special C Flags
+MODULE_LOGGER_NOSAFETY_C_FLAGS           =
+ifndef LOG_LEVEL
+MODULE_LOGGER_NOSAFETY_C_FLAGS          += -DDEFAULT_LOG_LEVEL=$(DEFAULT_LOG_LEVEL)
+endif
+
+#
+# Special ASM Flags
+MODULE_LOGGER_NOSAFETY_ASM_FLAGS         =
diff --git a/spe-freertos-bsp/fsp/source/drivers/osa/freertosv10/arm/armv7/cortex-r5/module-ospl-config.mk b/spe-freertos-bsp/fsp/source/drivers/osa/freertosv10/arm/armv7/cortex-r5/module-ospl-config.mk
new file mode 100644
index 0000000..98c591f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/osa/freertosv10/arm/armv7/cortex-r5/module-ospl-config.mk
@@ -0,0 +1,47 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-ospl-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-cpl_*.mk' files.
+MODULE_OSPL_CONFIG              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_OSPL_DEPENDS             := SOC CLUSTER CPL OSA FSP_COMMON
+$(foreach _,$(MODULE_OSPL_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-osp*.mk' files.
+MODULE_OSPL_DEFINED             := 1
+
+#
+# Location of source code files
+OSPL_DIR                         = $(FSP_COMMON_REPO)/drivers/osa/$(OSA)/$(ARCH)/$(ISA)/$(CPU)
+MODULE_OSPL_SOURCE_DIR           = $(OSPL_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_OSPL_INCLUDES             =
diff --git a/spe-freertos-bsp/fsp/source/drivers/osa/freertosv10/arm/armv7/cortex-r5/module-ospl.mk b/spe-freertos-bsp/fsp/source/drivers/osa/freertosv10/arm/armv7/cortex-r5/module-ospl.mk
new file mode 100644
index 0000000..f39ba21
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/osa/freertosv10/arm/armv7/cortex-r5/module-ospl.mk
@@ -0,0 +1,61 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-ospl.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_OSPL_NAME                := OSPL
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_OSPL_DEFINED             := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_OSPL_DEPENDS             := OSPL SOC CPL OSA
+$(foreach _,$(CONFIG_OSPL_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_OSPL_C_SRC                =
+
+#
+# Assembly source
+MODULE_OSPL_ASM_SRC              =
+
+#
+# Special C Flags
+MODULE_OSPL_C_FLAGS              =
+
+#
+# Special ASM Flags
+MODULE_OSPL_ASM_FLAGS            =
diff --git a/spe-freertos-bsp/fsp/source/drivers/osa/littlekernel/arm/armv8/cortex-r52/module-ospl-config.mk b/spe-freertos-bsp/fsp/source/drivers/osa/littlekernel/arm/armv8/cortex-r52/module-ospl-config.mk
new file mode 100644
index 0000000..98c591f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/osa/littlekernel/arm/armv8/cortex-r52/module-ospl-config.mk
@@ -0,0 +1,47 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-ospl-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-cpl_*.mk' files.
+MODULE_OSPL_CONFIG              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_OSPL_DEPENDS             := SOC CLUSTER CPL OSA FSP_COMMON
+$(foreach _,$(MODULE_OSPL_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-osp*.mk' files.
+MODULE_OSPL_DEFINED             := 1
+
+#
+# Location of source code files
+OSPL_DIR                         = $(FSP_COMMON_REPO)/drivers/osa/$(OSA)/$(ARCH)/$(ISA)/$(CPU)
+MODULE_OSPL_SOURCE_DIR           = $(OSPL_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_OSPL_INCLUDES             =
diff --git a/spe-freertos-bsp/fsp/source/drivers/osa/littlekernel/arm/armv8/cortex-r52/module-ospl.mk b/spe-freertos-bsp/fsp/source/drivers/osa/littlekernel/arm/armv8/cortex-r52/module-ospl.mk
new file mode 100644
index 0000000..f39ba21
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/osa/littlekernel/arm/armv8/cortex-r52/module-ospl.mk
@@ -0,0 +1,61 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-ospl.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_OSPL_NAME                := OSPL
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_OSPL_DEFINED             := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_OSPL_DEPENDS             := OSPL SOC CPL OSA
+$(foreach _,$(CONFIG_OSPL_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_OSPL_C_SRC                =
+
+#
+# Assembly source
+MODULE_OSPL_ASM_SRC              =
+
+#
+# Special C Flags
+MODULE_OSPL_C_FLAGS              =
+
+#
+# Special ASM Flags
+MODULE_OSPL_ASM_FLAGS            =
diff --git a/spe-freertos-bsp/fsp/source/drivers/osa/module-osa-config.mk b/spe-freertos-bsp/fsp/source/drivers/osa/module-osa-config.mk
new file mode 100644
index 0000000..24e22dc
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/osa/module-osa-config.mk
@@ -0,0 +1,41 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-osa-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-osa*.mk' files.
+MODULE_OSA_CONFIG               := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_OSA_DEPENDS              := SOC CLUSTER CPL
+$(foreach _,$(MODULE_OSA_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_OSA_SOURCE_DIR            =
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_OSA_INCLUDES              = -I $(FSP_COMMON_REPO)/include/osa/$(OSA)
diff --git a/spe-freertos-bsp/fsp/source/drivers/osa/module-osa.mk b/spe-freertos-bsp/fsp/source/drivers/osa/module-osa.mk
new file mode 100644
index 0000000..21626b4
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/osa/module-osa.mk
@@ -0,0 +1,61 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-osa.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_OSA_NAME                 := OSA
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_OSA_DEFINED              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_OSA_DEPENDS              := OSA
+$(foreach _,$(CONFIG_OSA_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_OSA_C_SRC                 =
+
+#
+# Assembly source
+MODULE_OSA_ASM_SRC               =
+
+#
+# Special C Flags
+MODULE_OSA_C_FLAGS               =
+
+#
+# Special ASM Flags
+MODULE_OSA_ASM_FLAGS             =
diff --git a/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/arm/armv7/cortex-r5/module-ospl-config.mk b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/arm/armv7/cortex-r5/module-ospl-config.mk
new file mode 100644
index 0000000..98c591f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/arm/armv7/cortex-r5/module-ospl-config.mk
@@ -0,0 +1,47 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-ospl-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-cpl_*.mk' files.
+MODULE_OSPL_CONFIG              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_OSPL_DEPENDS             := SOC CLUSTER CPL OSA FSP_COMMON
+$(foreach _,$(MODULE_OSPL_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-osp*.mk' files.
+MODULE_OSPL_DEFINED             := 1
+
+#
+# Location of source code files
+OSPL_DIR                         = $(FSP_COMMON_REPO)/drivers/osa/$(OSA)/$(ARCH)/$(ISA)/$(CPU)
+MODULE_OSPL_SOURCE_DIR           = $(OSPL_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_OSPL_INCLUDES             =
diff --git a/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/arm/armv7/cortex-r5/module-ospl.mk b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/arm/armv7/cortex-r5/module-ospl.mk
new file mode 100644
index 0000000..f7b04fc
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/arm/armv7/cortex-r5/module-ospl.mk
@@ -0,0 +1,63 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-ospl.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_OSPL_NAME                := OSPL
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_OSPL_DEFINED             := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_OSPL_DEPENDS             := OSPL SOC CPL OSA
+$(foreach _,$(CONFIG_OSPL_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_OSPL_C_SRC                =
+MODULE_OSPL_C_SRC               += $(OSPL_DIR)/rtos-port-timer.c
+MODULE_OSPL_C_SRC               += $(OSPL_DIR)/rtos-port-task.c
+
+#
+# Assembly source
+MODULE_OSPL_ASM_SRC              =
+
+#
+# Special C Flags
+MODULE_OSPL_C_FLAGS              =
+
+#
+# Special ASM Flags
+MODULE_OSPL_ASM_FLAGS            =
diff --git a/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/arm/armv7/cortex-r5/rtos-port-task.c b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/arm/armv7/cortex-r5/rtos-port-task.c
new file mode 100644
index 0000000..0c6b5ba
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/arm/armv7/cortex-r5/rtos-port-task.c
@@ -0,0 +1,162 @@
+/* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                     // for int32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/type-conversion.h>        // for fsp_i32_to_u32
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <osa/sections-osa.h>           // Immune from CT_ASSERT protection
+#include <osa/rtos-task.h>              // for rtosTaskCreate, rtosTaskInitializeSche...
+#include <osa/rtos-priv.h>              // for SETFIELD, SETFIELD_t
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__CPU__TYPE_CONVERSION_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_PRIV_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx")
+/**
+ * rtosTaskCreate()             - rtos wrapper for xTaskCreate()
+ *
+ * @pxTaskParameters:           pointer to the parameter structure that will
+ *                              specify the attributes of the task being
+ *                              created.
+ * @pxCreatedTask:              pointer to where the task handle for the newly
+ *                              created task will be stored.
+ *
+ * This function is a wrapper for xTaskCreate in SafeRTOS.  It provides
+ * a translation of the structures and types used by NVIDIA code to those
+ * used by SafeRTOS.
+ *
+ * Return Values:
+ *      rtosPASS        if the task was created successfully
+ *      other values    if the task could not be created successfully
+ */
+SECTION_OSA_CREATE_TEXT
+rtosError
+rtosTaskCreate(const rtosTaskParameters * const pxTaskParameters,
+               rtosTaskHandle *pxCreatedTask)
+{
+    xTaskParameters     xParms;
+    xTaskParameters     *pxParms        = &xParms;
+
+    SETFIELD(pxParms, pxTaskParameters, pvTaskCode);
+    SETFIELD(pxParms, pxTaskParameters, pcTaskName);
+    SETFIELD(pxParms, pxTaskParameters, pxTCB);
+    SETFIELD(pxParms, pxTaskParameters, pcStackBuffer);
+    SETFIELD(pxParms, pxTaskParameters, uxStackDepthBytes);
+    SETFIELD(pxParms, pxTaskParameters, pvParameters);
+    SETFIELD(pxParms, pxTaskParameters, uxPriority);
+    SETFIELD(pxParms, pxTaskParameters, pvObject);
+    INLINE_RFD(MISRA, DEVIATE, Rule_10_5, "Approval: Bug 200532009, DR: SWE-FSP-020-SWSADR.docx");
+    SETFIELD_t(pxParms, int32_t, pxTaskParameters, xUsingFPU);
+    SETFIELD(pxParms, pxTaskParameters, uxPrivilegeLevel);
+    SETFIELD(pxParms, pxTaskParameters, pxMPUParameters);
+
+    /*
+     * Call the SafeRTOS API to create the task
+     */
+    return xTaskCreate(pxParms, pxCreatedTask);
+}
+
+
+/**
+ * rtosTaskInitializeScheduler()        - rtos wrapper for xTaskInitializeScheduler()
+ *
+ * @pxSchedInitParameters:      pointer to a structure that contains the
+ *                              parameters that are used to initialize the
+ *                              SafeRTOS scheduler.
+ *
+ * This function is a wrapper for xTaskInitializeScheduler in SafeRTOS.  It
+ * provides a translation of the structures and types used by NVIDIA code to
+ * those used by SafeRTOS.
+ *
+ * Return Values:
+ *      none
+ */
+SECTION_OSA_INIT_TEXT
+rtosError
+rtosTaskInitializeScheduler(const rtosSchedParameters * const pxSchedInitParameters)
+{
+    xPORT_INIT_PARAMETERS       xParms;
+    xPORT_INIT_PARAMETERS       *pxParms        = &xParms;
+
+    SETFIELD(pxParms, pxSchedInitParameters, ulCPUClockHz);
+    SETFIELD(pxParms, pxSchedInitParameters, ulTickRateHz);
+    SETFIELD(pxParms, pxSchedInitParameters, uxAdditionalStackCheckMarginBytes);
+    SETFIELD(pxParms, pxSchedInitParameters, pcIdleTaskStackBuffer);
+    SETFIELD(pxParms, pxSchedInitParameters, uxIdleTaskStackSizeBytes);
+    INLINE_RFD(MISRA, DEVIATE, Rule_10_5, "Approval: Bug 200532009, DR: SWE-FSP-020-SWSADR.docx");
+    SETFIELD_t(pxParms, int32_t, pxSchedInitParameters, xIdleTaskUsingFPU);
+    SETFIELD(pxParms, pxSchedInitParameters, pvIdleTaskTLSObject);
+    SETFIELD(pxParms, pxSchedInitParameters, uxTimerTaskPriority);
+    SETFIELD(pxParms, pxSchedInitParameters, uxTimerTaskStackSize);
+    SETFIELD(pxParms, pxSchedInitParameters, pcTimerTaskStackBuffer);
+    SETFIELD(pxParms, pxSchedInitParameters, uxTimerCommandQueueLength);
+    SETFIELD(pxParms, pxSchedInitParameters, uxTimerCommandQueueBufferSize);
+    SETFIELD(pxParms, pxSchedInitParameters, pcTimerCommandQueueBuffer);
+    SETFIELD(pxParms, pxSchedInitParameters, pxIdleTaskMPUParameters);
+    SETFIELD(pxParms, pxSchedInitParameters, pxTimerTaskMPUParameters);
+
+    /* Always set idle task privilege level to pdTRUE */
+    INLINE_RFD(MISRA, DEVIATE, Rule_10_5, "Approval: Bug 200532009, DR: SWE-FSP-020-SWSADR.docx");
+    pxParms->uxIdleTaskPrivilegeLevel = fsp_i32_to_u32(pdTRUE);
+
+    /*
+     * Call the SafeRTOS API to initialize the scheduler.
+     */
+    return xTaskInitializeScheduler(pxParms);
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/arm/armv7/cortex-r5/rtos-port-timer.c b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/arm/armv7/cortex-r5/rtos-port-timer.c
new file mode 100644
index 0000000..6189640
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/arm/armv7/cortex-r5/rtos-port-timer.c
@@ -0,0 +1,95 @@
+_Pragma("coverity compliance block(include) \
+         (deviate MISRA_C_2012_Rule_1_2 \"Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx\") \
+         (deviate MISRA_C_2012_Directive_4_8 \"Approval: Bug 200534384, DR: SWE-FSP-011-SWSADR.docx\")")
+/* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                     // for int32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <osa/sections-osa.h>           // Immune from CT_ASSERT protection
+#include <osa/rtos-priv.h>              // for SETFIELD, SETFIELD_t
+#include <osa/rtos-timer.h>             // for rtosTimerCreate
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_TIMER_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx")
+SECTION_OSA_CREATE_TEXT
+rtosError
+rtosTimerCreate(const rtosTimerInitParametersType * const pxTimerParameters,
+                rtosTimerHandle *pxTimerHandle)
+{
+    timerInitParametersType  xParams;
+    timerInitParametersType  *pxParams = &xParams;
+
+    SETFIELD(pxParams, pxTimerParameters, pcTimerName);
+    SETFIELD(pxParams, pxTimerParameters, xTimerPeriodInTicks);
+    INLINE_RFD(MISRA, DEVIATE, Rule_10_5, "Approval: Bug 200532009, DR: SWE-FSP-020-SWSADR.docx");
+    SETFIELD_t(pxParams, int32_t, pxTimerParameters, xIsPeriodic);
+    SETFIELD(pxParams, pxTimerParameters, xTimerID);
+    SETFIELD(pxParams, pxTimerParameters, pxNewTimer);
+    SETFIELD(pxParams, pxTimerParameters, pxCallbackFunction);
+    SETFIELD(pxParams, pxTimerParameters, pxTimerInstance);
+    SETFIELD(pxParams, pxTimerParameters, pvObject);
+
+    /*
+     * Call the SafeRTOS API to create a timer
+     */
+    return xTimerCreate(pxParams, pxTimerHandle);
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_8, "Approval: Bug 200534384, DR: SWE-FSP-011-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/nvidia/riscv/nvriscv/module-ospl-config.mk b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/nvidia/riscv/nvriscv/module-ospl-config.mk
new file mode 100644
index 0000000..8bc4ac1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/nvidia/riscv/nvriscv/module-ospl-config.mk
@@ -0,0 +1,47 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-ospl-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-cpl_*.mk' files.
+MODULE_OSPL_CONFIG              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_OSPL_DEPENDS             := OSA
+$(foreach _,$(MODULE_OSPL_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-osp*.mk' files.
+MODULE_OSPL_DEFINED             := 1
+
+#
+# Location of source code files
+OSPL_DIR                         = $(FSP_COMMON_REPO)/drivers/osa/$(OSA)/$(ARCH)/$(ISA)/$(CPU)
+MODULE_OSPL_SOURCE_DIR           = $(OSPL_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_OSPL_INCLUDES             =
diff --git a/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/nvidia/riscv/nvriscv/module-ospl.mk b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/nvidia/riscv/nvriscv/module-ospl.mk
new file mode 100644
index 0000000..09d9538
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv8/nvidia/riscv/nvriscv/module-ospl.mk
@@ -0,0 +1,63 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-ospl.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_OSPL_NAME                := OSPL
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_OSPL_DEFINED             := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_OSPL_DEPENDS             := OSPL OSA
+$(foreach _,$(CONFIG_OSPL_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_OSPL_C_SRC                =
+MODULE_OSPL_C_SRC               +=
+MODULE_OSPL_C_SRC               +=
+
+#
+# Assembly source
+MODULE_OSPL_ASM_SRC              =
+
+#
+# Special C Flags
+MODULE_OSPL_C_FLAGS              =
+
+#
+# Special ASM Flags
+MODULE_OSPL_ASM_FLAGS            =
diff --git a/spe-freertos-bsp/fsp/source/drivers/osa/safertosv9/arm/armv7/cortex-r5/module-ospl-config.mk b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv9/arm/armv7/cortex-r5/module-ospl-config.mk
new file mode 100644
index 0000000..98c591f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv9/arm/armv7/cortex-r5/module-ospl-config.mk
@@ -0,0 +1,47 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-ospl-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-cpl_*.mk' files.
+MODULE_OSPL_CONFIG              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_OSPL_DEPENDS             := SOC CLUSTER CPL OSA FSP_COMMON
+$(foreach _,$(MODULE_OSPL_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-osp*.mk' files.
+MODULE_OSPL_DEFINED             := 1
+
+#
+# Location of source code files
+OSPL_DIR                         = $(FSP_COMMON_REPO)/drivers/osa/$(OSA)/$(ARCH)/$(ISA)/$(CPU)
+MODULE_OSPL_SOURCE_DIR           = $(OSPL_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_OSPL_INCLUDES             =
diff --git a/spe-freertos-bsp/fsp/source/drivers/osa/safertosv9/arm/armv7/cortex-r5/module-ospl.mk b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv9/arm/armv7/cortex-r5/module-ospl.mk
new file mode 100644
index 0000000..f7b04fc
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv9/arm/armv7/cortex-r5/module-ospl.mk
@@ -0,0 +1,63 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-ospl.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_OSPL_NAME                := OSPL
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_OSPL_DEFINED             := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_OSPL_DEPENDS             := OSPL SOC CPL OSA
+$(foreach _,$(CONFIG_OSPL_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_OSPL_C_SRC                =
+MODULE_OSPL_C_SRC               += $(OSPL_DIR)/rtos-port-timer.c
+MODULE_OSPL_C_SRC               += $(OSPL_DIR)/rtos-port-task.c
+
+#
+# Assembly source
+MODULE_OSPL_ASM_SRC              =
+
+#
+# Special C Flags
+MODULE_OSPL_C_FLAGS              =
+
+#
+# Special ASM Flags
+MODULE_OSPL_ASM_FLAGS            =
diff --git a/spe-freertos-bsp/fsp/source/drivers/osa/safertosv9/arm/armv7/cortex-r5/rtos-port-task.c b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv9/arm/armv7/cortex-r5/rtos-port-task.c
new file mode 100644
index 0000000..350aeee
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv9/arm/armv7/cortex-r5/rtos-port-task.c
@@ -0,0 +1,155 @@
+/* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                     // for int32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <osa/sections-osa.h>           // Immune from CT_ASSERT protection
+#include <osa/rtos-task.h>              // for rtosTaskCreate, rtosTaskInitializeSche...
+#include <osa/rtos-priv.h>              // for SETFIELD, SETFIELD_t
+#include <ospl/rtos-port.h>             // for portTickType..,
+
+
+/* The SVC stack base address - Based on the value from the linker script */
+extern rtosUInt32Type Image$$SVC_STACK$$ZI$$Limit;
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__OSA__RTOS_PRIV_H, "Header file missing or invalid.")
+
+/**
+ * rtosTaskCreate()             - rtos wrapper for xTaskCreate()
+ *
+ * @pxTaskParameters:           pointer to the parameter structure that will
+ *                              specify the attributes of the task being
+ *                              created.
+ * @pxCreatedTask:              pointer to where the task handle for the newly
+ *                              created task will be stored.
+ *
+ * This function is a wrapper for xTaskCreate in SafeRTOS.  It provides
+ * a translation of the structures and types used by NVIDIA code to those
+ * used by SafeRTOS.
+ *
+ * Return Values:
+ *      rtosPASS        if the task was created successfully
+ *      other values    if the task could not be created successfully
+ */
+SECTION_OSA_CREATE_TEXT
+rtosError
+rtosTaskCreate(const rtosTaskParameters * const pxTaskParameters,
+               rtosTaskHandle *pxCreatedTask)
+{
+    xTaskParameters     xParms;
+    xTaskParameters     *pxParms        = &xParms;
+
+    SETFIELD(pxParms, pxTaskParameters, pvTaskCode);
+    SETFIELD(pxParms, pxTaskParameters, pcTaskName);
+    SETFIELD(pxParms, pxTaskParameters, pxTCB);
+    SETFIELD(pxParms, pxTaskParameters, pcStackBuffer);
+    SETFIELD(pxParms, pxTaskParameters, uxStackDepthBytes);
+    SETFIELD(pxParms, pxTaskParameters, pvParameters);
+    SETFIELD(pxParms, pxTaskParameters, uxPriority);
+    SETFIELD(pxParms, pxTaskParameters, pvObject);
+    SETFIELD_t(pxParms, int32_t, pxTaskParameters, xUsingFPU);
+    SETFIELD(pxParms, pxTaskParameters, uxPrivilegeLevel);
+    SETFIELD(pxParms, pxTaskParameters, pxMPUParameters);
+
+    /*
+     * Call the SafeRTOS API to create the task
+     */
+    return xTaskCreate(pxParms, pxCreatedTask);
+}
+
+
+/**
+ * rtosTaskInitializeScheduler()        - rtos wrapper for xTaskInitializeScheduler()
+ *
+ * @pxSchedInitParameters:      pointer to a structure that contains the
+ *                              parameters that are used to initialize the
+ *                              SafeRTOS scheduler.
+ *
+ * This function is a wrapper for xTaskInitializeScheduler in SafeRTOS.  It
+ * provides a translation of the structures and types used by NVIDIA code to
+ * those used by SafeRTOS.
+ *
+ * Return Values:
+ *      none
+ */
+SECTION_OSA_INIT_TEXT
+rtosError
+rtosTaskInitializeScheduler(const rtosSchedParameters * const pxSchedInitParameters)
+{
+    xPORT_INIT_PARAMETERS       xParms;
+    xPORT_INIT_PARAMETERS       *pxParms        = &xParms;
+
+    SETFIELD(pxParms, pxSchedInitParameters, ulCPUClockHz);
+    SETFIELD(pxParms, pxSchedInitParameters, ulTickRateHz);
+    SETFIELD(pxParms, pxSchedInitParameters, uxAdditionalStackCheckMarginBytes);
+    SETFIELD(pxParms, pxSchedInitParameters, pcIdleTaskStackBuffer);
+    SETFIELD(pxParms, pxSchedInitParameters, uxIdleTaskStackSizeBytes);
+    SETFIELD_t(pxParms, int32_t, pxSchedInitParameters, xIdleTaskUsingFPU);
+    SETFIELD(pxParms, pxSchedInitParameters, pvIdleTaskTLSObject);
+    SETFIELD(pxParms, pxSchedInitParameters, uxTimerTaskPriority);
+    SETFIELD(pxParms, pxSchedInitParameters, uxTimerTaskStackSize);
+    SETFIELD(pxParms, pxSchedInitParameters, pcTimerTaskStackBuffer);
+    SETFIELD(pxParms, pxSchedInitParameters, uxTimerCommandQueueLength);
+    SETFIELD(pxParms, pxSchedInitParameters, uxTimerCommandQueueBufferSize);
+    SETFIELD(pxParms, pxSchedInitParameters, pcTimerCommandQueueBuffer);
+    SETFIELD(pxParms, pxSchedInitParameters, pxIdleTaskMPUParameters);
+    SETFIELD(pxParms, pxSchedInitParameters, pxTimerTaskMPUParameters);
+
+    /* Always set idle task privilege level to pdTRUE */
+    pxParms->uxIdleTaskPrivilegeLevel = pdTRUE;
+
+#if defined(SAFERTOS_VARIANT_SVC) && (SAFERTOS_VARIANT_SVC == 1)
+    pxParms->pcSVCStackBaseAddress = (void *)&Image$$SVC_STACK$$ZI$$Limit;
+#endif
+
+    /*
+     * Call the SafeRTOS API to initialize the scheduler.
+     */
+    return xTaskInitializeScheduler(pxParms);
+}
+
+
diff --git a/spe-freertos-bsp/fsp/source/drivers/osa/safertosv9/arm/armv7/cortex-r5/rtos-port-timer.c b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv9/arm/armv7/cortex-r5/rtos-port-timer.c
new file mode 100644
index 0000000..2655260
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/osa/safertosv9/arm/armv7/cortex-r5/rtos-port-timer.c
@@ -0,0 +1,82 @@
+/* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                     // for int32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <osa/sections-osa.h>           // Immune from CT_ASSERT protection
+#include <osa/rtos-priv.h>              // for SETFIELD, SETFIELD_t
+#include <ospl/rtos-port.h>             // for portTickType..,
+#include <osa/rtos-timer.h>             // for rtosTimerCreate
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__OSA__RTOS_PRIV_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__OSA__RTOS_TIMER_H, "Header file missing or invalid.")
+
+SECTION_OSA_CREATE_TEXT
+rtosError
+rtosTimerCreate(const rtosTimerInitParametersType * const pxTimerParameters,
+                rtosTimerHandle *pxTimerHandle)
+{
+    timerInitParametersType  xParams;
+    timerInitParametersType  *pxParams = &xParams;
+
+    SETFIELD(pxParams, pxTimerParameters, pcTimerName);
+    SETFIELD(pxParams, pxTimerParameters, xTimerPeriodInTicks);
+    SETFIELD_t(pxParams, int32_t, pxTimerParameters, xIsPeriodic);
+    SETFIELD(pxParams, pxTimerParameters, xTimerID);
+    SETFIELD(pxParams, pxTimerParameters, pxNewTimer);
+    SETFIELD(pxParams, pxTimerParameters, pxCallbackFunction);
+    SETFIELD(pxParams, pxTimerParameters, pxTimerInstance);
+    SETFIELD(pxParams, pxTimerParameters, pvObject);
+    SETFIELD(pxParams, pxTimerParameters, xTaskToNotify);
+
+    /*
+     * Call the SafeRTOS API to create a timer
+     */
+    return xTimerCreate(pxParams, pxTimerHandle);
+}
+
+
diff --git a/spe-freertos-bsp/fsp/source/drivers/scp/module-scp-config.mk b/spe-freertos-bsp/fsp/source/drivers/scp/module-scp-config.mk
new file mode 100644
index 0000000..1eeb7e8
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/scp/module-scp-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2022, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-scp-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_SCP_CONFIG               := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_SCP_DEPENDS              := CPL FSP_COMMON FBDMA
+$(foreach _,$(MODULE_SCP_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_SCP_DRIVERS_DIR           = $(FSP_COMMON_REPO)/drivers/scp
+MODULE_SCP_SOURCE_DIR            = $(MODULE_SCP_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_SCP_INCLUDES              =
diff --git a/spe-freertos-bsp/fsp/source/drivers/scp/module-scp.mk b/spe-freertos-bsp/fsp/source/drivers/scp/module-scp.mk
new file mode 100644
index 0000000..52351a5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/scp/module-scp.mk
@@ -0,0 +1,70 @@
+#
+# Copyright (c) 2022, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-scp.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_SCP_NAME                   := SCP
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_SCP_DEFINED                := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_SCP_DEPENDS                := SCP CPL FBDMA
+$(foreach _,$(CONFIG_SCP_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_SCP_C_SRC                   =
+
+ifeq ($(NVRISCV_FEATURE_SCP),y)
+MODULE_SCP_C_SRC                  += $(MODULE_SCP_DRIVERS_DIR)/scp_crypt.c
+MODULE_SCP_C_SRC                  += $(MODULE_SCP_DRIVERS_DIR)/scp_direct.c
+MODULE_SCP_C_SRC                  += $(MODULE_SCP_DRIVERS_DIR)/scp_general.c
+MODULE_SCP_C_SRC                  += $(MODULE_SCP_DRIVERS_DIR)/scp_private.c
+MODULE_SCP_C_SRC                  += $(MODULE_SCP_DRIVERS_DIR)/scp_rand.c
+MODULE_SCP_C_SRC                  += $(MODULE_SCP_DRIVERS_DIR)/scp_sanity.c
+endif
+
+#
+# Assembly source
+MODULE_SCP_ASM_SRC                 =
+
+#
+# Special C Flags
+MODULE_SCP_C_FLAGS                 =
+
+#
+# Special ASM Flags
+MODULE_SCP_ASM_FLAGS               =
diff --git a/spe-freertos-bsp/fsp/source/drivers/scp/scp_crypt.c b/spe-freertos-bsp/fsp/source/drivers/scp/scp_crypt.c
new file mode 100644
index 0000000..fa51615
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/scp/scp_crypt.c
@@ -0,0 +1,1911 @@
+/**
+ * @file        scp_crypt.c
+ * @brief       Cryptographic SCP features.
+ *
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !NVRISCV_FEATURE_SCP
+#error "Attempting to build scp_crypt.c but the SCP driver is disabled!"
+#endif // NVRISCV_FEATURE_SCP
+
+
+/* Compiler headers */
+#include <stdbool.h>                    // for bool, true, false
+#include <stddef.h>                     // for size_t, NULL
+#include <stdint.h>                     // for uint8_t, uintptr_t, etc.
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for HEADER_CHECK
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>        // for error_t, common error codes
+#include <fbdma/memutils.h>             // for memutils_mem_has_overlap
+#include <misc/nvmisc_drf.h>            // for DRF macros (for scp_direct.h)
+
+/* Module-specific FSP headers */
+#include <scp/scp-errors.h>             // for SCP error codes
+#include <scp/scp_common.h>             // for scp_register_index_t
+#include <scp/scp_crypt.h>              // for scp_key_desc_t, etc.
+#include <scp/scp_direct.h>             // for SCP primitives
+#include <scp/scp_private.h>            // for scp_pvt_*
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The HEADER_CHECK macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+HEADER_CHECK(FSP__ERROR__COMMON_ERRORS_H)
+HEADER_CHECK(FSP__FBDMA__MEMUTILS_H)
+HEADER_CHECK(FSP__MISC__NVMISC_DRF_H)
+HEADER_CHECK(FSP__SCP__SCP_ERRORS_H)
+HEADER_CHECK(FSP__SCP__SCP_COMMON_H)
+HEADER_CHECK(FSP__SCP__SCP_CRYPT_H)
+HEADER_CHECK(FSP__SCP__SCP_DIRECT_H)
+HEADER_CHECK(FSP__SCP__SCP_PRIVATE_H)
+
+
+/**
+ * @brief The chmod value for a secure-keyable-only register ACL.
+ *
+ * Intended to protect encryption/decryption keys in secure contexts.
+ */
+#define SCP_REGISTER_ACL_KEY 0x1U
+
+
+//
+// Prototypes for local helper functions.
+// See definitions for details.
+//
+static error_t s_scp_Crypt(const scp_key_desc_t * p_key_desc,
+                           scp_cipher_mode_t      cipher_mode,
+                           uintptr_t              source_pa,
+                           uintptr_t              dest_pa,
+                           size_t                 size,
+                           uintptr_t              context_pa,
+                           bool                   b_decrypt);
+
+static error_t s_scp_Cmac(const scp_key_desc_t * p_key_desc,
+                          scp_cmac_mode_t        cmac_mode,
+                          uintptr_t              source_pa,
+                          size_t                 size,
+                          uintptr_t              context_pa);
+
+static error_t s_scp_Load_Key(const scp_key_desc_t * p_key_desc);
+
+static error_t s_scp_Load_Buffer_Key(uintptr_t key_pa);
+
+static error_t s_scp_Load_Register_Key(scp_register_index_t reg_index);
+
+static error_t s_scp_Load_Ecb_Key(uint8_t secret_index, uintptr_t salt_pa);
+
+static error_t s_scp_Load_Cbc_Key(uint8_t secret_index, uintptr_t salt_pa,
+                                  uintptr_t iv_pa);
+
+static error_t s_scp_Load_Cmac_Key(uint8_t      secret_index,
+                                   uintptr_t    message_pa,
+                                   size_t       size,
+                                   bool         b_padded);
+
+static error_t s_scp_Load_Crypt_Sequence(scp_cipher_mode_t  cipher_mode,
+                                         bool               b_decrypt);
+
+static error_t s_scp_Load_Ecb_Sequence(bool b_decrypt);
+
+static error_t s_scp_Load_Cbc_Sequence(bool b_decrypt);
+
+static error_t s_scp_Load_Ctr_Sequence(void);
+
+static error_t s_scp_Load_Hash_Sequence(void);
+
+static error_t s_scp_Load_Cmac_Sequence(void);
+
+static error_t s_scp_Complete_Cmac(uintptr_t final_pa, bool b_padded);
+
+
+/**
+ * @copydoc scp_Encrypt
+ */
+error_t
+scp_Encrypt
+(
+    const scp_key_desc_t *  p_key_desc,
+    scp_cipher_mode_t       cipher_mode,
+    uintptr_t               source_pa,
+    uintptr_t               dest_pa,
+    size_t                  size,
+    uintptr_t               context_pa
+)
+{
+    return s_scp_Crypt(p_key_desc, cipher_mode, source_pa, dest_pa, size,
+                       context_pa, false);
+}
+
+/**
+ * @copydoc scp_Decrypt
+ */
+error_t
+scp_Decrypt
+(
+    const scp_key_desc_t *  p_key_desc,
+    scp_cipher_mode_t       cipher_mode,
+    uintptr_t               source_pa,
+    uintptr_t               dest_pa,
+    size_t                  size,
+    uintptr_t               context_pa
+)
+{
+    return s_scp_Crypt(p_key_desc, cipher_mode, source_pa, dest_pa, size,
+                       context_pa, true);
+}
+
+/**
+ * @copydoc scp_Dmhash
+ */
+error_t
+scp_Dmhash
+(
+    uintptr_t   source_pa,
+    size_t      size,
+    uintptr_t   dest_pa,
+    uintptr_t   init_pa
+)
+{
+    error_t status = E_SUCCESS;
+
+    // Verify driver state before proceeding further.
+    if (!g_scp_state.b_initialized)
+    {
+        // Early exit as clean-up code may not be able to execute safely.
+        return E_SCP_NOT_READY;
+    }
+
+    // This function cannot be called from direct mode.
+    if (g_scp_state.b_direct_mode_active)
+    {
+        // Early exit as clean-up code may not be able to execute safely.
+        return E_INVALID_STATE;
+    }
+
+    // Verify access to lockable SCP registers/fields.
+    if (scp_pvt_Is_Access_Restricted())
+    {
+        // Early exit as clean-up code may not be able to execute safely.
+        return E_SCP_INVALID_LOCK_STATE;
+    }
+
+    // Verify source buffer.
+    status = scp_pvt_Validate_Buffer(source_pa, size, false);
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+    // Verify byte count.
+    if ((size == 0U) || (size % SCP_KEY_SIZE != 0U))
+    {
+        status = E_SCP_INVALID_REQUEST;
+        goto cleanup;
+    }
+
+    // Verify destination buffer.
+    status = scp_pvt_Validate_Buffer(dest_pa, SCP_BLOCK_SIZE, true);
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+    // Verify initial hash buffer.
+    status = scp_pvt_Validate_Buffer(init_pa, SCP_BLOCK_SIZE, false);
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+    // Load initial hash value into register-index one.
+    status = scp_pvt_Load_Buffer(init_pa, SCP_REGISTER_INDEX_1);
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+    // Load sequencer zero with the instructions for DmHash and update Ku.
+    status = s_scp_Load_Hash_Sequence();
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+    // Run the input data through the sequence we loaded above.
+    status = scp_pvt_Run_Sequence(source_pa, (uintptr_t)NULL, size);
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+    // Read the final hash value out of register-index one.
+    status = scp_pvt_Store_Buffer(SCP_REGISTER_INDEX_1, dest_pa);
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+cleanup:
+    //
+    // Clear the sequencers to free them up for future use and prevent
+    // anything accidentally carrying forward into other interfaces.
+    //
+    scp_pvt_Reset_Sequencers();
+
+    //
+    // Clear the SCP GPRs to scrub any potentially sensitive data from them and
+    // unlock their associated ACLs. Report failures only if no higher-priority
+    // error is already pending.
+    //
+    error_t clear_status = scp_pvt_Clear_All();
+    if (status == E_SUCCESS)
+    {
+        status = clear_status;
+    }
+
+    // Done.
+    return status;
+}
+
+/**
+ * @copydoc scp_Cmac
+ */
+error_t
+scp_Cmac
+(
+    const scp_key_desc_t *  p_key_desc,
+    scp_cmac_mode_t         cmac_mode,
+    uintptr_t               source_pa,
+    size_t                  size,
+    uintptr_t               dest_pa,
+    uintptr_t               context_pa
+)
+{
+    error_t status = E_SUCCESS;
+
+    // Verify driver state before proceeding further.
+    if (!g_scp_state.b_initialized)
+    {
+        // Early exit as clean-up code may not be able to execute safely.
+        return E_SCP_NOT_READY;
+    }
+
+    // This function cannot be called from direct mode.
+    if (g_scp_state.b_direct_mode_active)
+    {
+        // Early exit as clean-up code may not be able to execute safely.
+        return E_INVALID_STATE;
+    }
+
+    // Verify access to lockable SCP registers/fields.
+    if (scp_pvt_Is_Access_Restricted())
+    {
+        // Early exit as clean-up code may not be able to execute safely.
+        return E_SCP_INVALID_LOCK_STATE;
+    }
+
+    // Verify destination buffer (other parameters validated by s_scp_Cmac()).
+    status = scp_pvt_Validate_Buffer(dest_pa, SCP_BLOCK_SIZE, true);
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+    // Perform CMAC computation.
+    status = s_scp_Cmac(p_key_desc, cmac_mode, source_pa, size, context_pa);
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+    // Read the final CMAC value out of register-index one.
+    status = scp_pvt_Store_Buffer(SCP_REGISTER_INDEX_1, dest_pa);
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+cleanup:
+    //
+    // Clear the sequencers to free them up for future use and prevent
+    // anything accidentally carrying forward into other interfaces.
+    //
+    scp_pvt_Reset_Sequencers();
+
+    //
+    // Clear the SCP GPRs to scrub any potentially sensitive data from them and
+    // unlock their associated ACLs. Report failures only if no higher-priority
+    // error is already pending.
+    //
+    error_t clear_status = scp_pvt_Clear_All();
+    if (status == E_SUCCESS)
+    {
+        status = clear_status;
+    }
+
+    // Done.
+    return status;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Encrypts or decrypts an arbitary buffer of data using AES-128.
+ *
+ * Encrypts or decrypts the first size bytes of data from source_pa using the
+ * key described by p_key_desc and writes the result to dest_pa. Uses an AES-128
+ * block cipher operating in the mode indicated by cipher_mode as the encryption
+ * or decryption algorithm. If applicable, SCP_BLOCK_SIZE bytes from context_pa
+ * are used as the initial contextual input to the cipher. Performs a
+ * decryption operation if b_decrypt is true and an encryption operation
+ * otherwise.
+ *
+ * Should p_key_desc describe a derived key, the s_scp_Crypt() function will
+ * perform the indicated key-derivation operation automatically. See the
+ * relevant SCP_KEY_* macros for details.
+ *
+ * Note that it is permissible for source_pa and dest_pa to reference the same
+ * memory locations (i.e. to facilitate encrypting or decrypting data in-
+ * place). However, the use of buffers that only partially overlap is
+ * prohibited and will result in an error.
+ *
+ * In the event that dest_pa refers to an external memory location, the
+ * application must ensure that it has first called scp_Configure_Shortcut() (or
+ * used the SCP_EXTERNAL_DEST() helper macro) to configure the shortcut-DMA
+ * path accordingly.
+ *
+ * @param[in]  p_key_desc   A pointer to the key-descriptor to be used for the
+ *                          encryption or decryption operation. Applications
+ *                          should acquire this parameter through one of the
+ *                          provided SCP_KEY_* macros.
+ *
+ * @param[in]  cipher_mode  The block-cipher mode of operation to use.
+ *
+ * @param[in]  source_pa    The physical address of the input buffer to be
+ *                          encrypted or decrypted. Must be aligned to
+ *                          SCP_BUFFER_ALIGNMENT and contain at least size
+ *                          bytes. Supports IMEM and DMEM locations only.
+ *
+ * @param[out] dest_pa      The physical address of the output buffer to which
+ *                          the encrypted or decrypted data is to be written.
+ *                          Must be aligned to SCP_BUFFER_ALIGNMENT and have at
+ *                          least size bytes of capacity. Permitted to overlap
+ *                          with source_pa only if exactly equal. Supports IMEM,
+ *                          DMEM, and external locations.
+ *
+ * @param[in]  size         The number of bytes to process from source_pa. Must
+ *                          be a nonzero multiple of SCP_BLOCK_SIZE.
+ *
+ * @param[in]  context_pa   The physical address of the input buffer containing
+ *                          the initialization vector (CBC) or initial counter
+ *                          value with nonce (CTR) to be used for the
+ *                          encryption or decryption operation. Must be aligned
+ *                          to SCP_BUFFER_ALIGNMENT and contain at least
+ *                          SCP_BLOCK_SIZE bytes. Required to be zero (NULL)
+ *                          for ECB mode. Supports IMEM and DMEM locations
+ *                          only.
+ *
+ * @param[in]  b_decrypt    A boolean value indicating whether to decrypt the
+ *                          data from source_pa rather than encrypting it.
+ *
+ * @retval E_SUCCESS                    if data was encrypted or decrypted
+ *                                      successfully.
+ *
+ * @retval E_SCP_NOT_READY              if the SCP driver has not been
+ *                                      initialized.
+ *
+ * @retval E_SCP_INVALID_OBJECT         if p_key_desc does not point to a valid
+ *                                      key-descriptor.
+ *
+ * @retval E_SCP_INVALID_OBJECT_BUFFER  if p_key_desc was constructed with a
+ *                                      zero (NULL) or incorrectly-aligned
+ *                                      address, or a pointer to an unsupported
+ *                                      memory location (e.g. EMEM), or a buffer
+ *                                      that overflows the memory region in
+ *                                      which it resides, or a buffer of invalid
+ *                                      size.
+ *
+ * @retval E_SCP_INVALID_INDEX          if p_key_desc was constructed with an
+ *                                      invalid register or hardware-secret
+ *                                      index, or references secret-index zero.
+ *
+ * @retval E_PERM                       if p_key_desc was constructed with a
+ *                                      hardware-secret index that the
+ *                                      application does not have permission to
+ *                                      use.
+ *
+ * @retval E_SCP_INVALID_POINTER        if one or more of p_key_desc, source_pa,
+ *                                      or dest_pa is zero/NULL, or context_pa
+ *                                      is zero (NULL) and cipher_mode is not
+ *                                      SCP_CIPHER_MODE_ECB.
+ *
+ * @retval E_SCP_INVALID_ADDRESS        if one or more of source_pa, dest_pa, or
+ *                                      context_pa is incorrectly aligned, or
+ *                                      the buffers referenced by source_pa and
+ *                                      dest_pa overlap without being equal.
+ *
+ * @retval E_SCP_INVALID_BASE           if one or more of source_pa, dest_pa, or
+ *                                      context_pa points to an unsupported
+ *                                      memory region (e.g. EMEM).
+ *
+ * @retval E_SCP_INVALID_REQUEST        if size is zero or is not a multiple of
+ *                                      SCP_BLOCK_SIZE.
+ *
+ * @retval E_SCP_INVALID_OPERATION      if cipher_mode is not a valid
+ *                                      scp_cipher_mode_t value, or cipher_mode
+ *                                      is SCP_CIPHER_MODE_ECB and context_pa is
+ *                                      nonzero (non-NULL).
+ *
+ * @retval E_SCP_FEATURE_NOT_ENABLED    if dest_pa is located in external memory
+ *                                      but the application does not have
+ *                                      shortcut-DMA support enabled.
+ *
+ * @retval E_SCP_INVALID_DMA_SPECIFIER  if dest_pa is located in external memory
+ *                                      but the application has not called
+ *                                      scp_Configure_Shortcut() to configure
+ *                                      the shortcut-DMA path.
+ *
+ * @retval E_SCP_OUT_OF_RANGE           if one or more of the buffers referenced
+ *                                      by source_pa, dest_pa, or context_pa
+ *                                      overflows the memory region in which it
+ *                                      resides.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_INVALID_STATE              if calls to this function are prohibited
+ *                                      because the SCP driver is operating in
+ *                                      direct mode.
+ *
+ * @retval E_SCP_INVALID_LOCK_STATE     if access to certain necessary registers
+ *                                      is being blocked by SCP lockdown.
+ *
+ * @retval E_FAULT                      if an IO-PMP fault was detected.
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ */
+static error_t
+s_scp_Crypt
+(
+    const scp_key_desc_t *  p_key_desc,
+    scp_cipher_mode_t       cipher_mode,
+    uintptr_t               source_pa,
+    uintptr_t               dest_pa,
+    size_t                  size,
+    uintptr_t               context_pa,
+    bool                    b_decrypt
+)
+{
+    error_t status = E_SUCCESS;
+
+    // Verify driver state before proceeding further.
+    if (!g_scp_state.b_initialized)
+    {
+        // Early exit as clean-up code may not be able to execute safely.
+        return E_SCP_NOT_READY;
+    }
+
+    // This function cannot be called from direct mode.
+    if (g_scp_state.b_direct_mode_active)
+    {
+        // Early exit as clean-up code may not be able to execute safely.
+        return E_INVALID_STATE;
+    }
+
+    // Verify access to lockable SCP registers/fields.
+    if (scp_pvt_Is_Access_Restricted())
+    {
+        // Early exit as clean-up code may not be able to execute safely.
+        return E_SCP_INVALID_LOCK_STATE;
+    }
+
+    // Verify source buffer.
+    status = scp_pvt_Validate_Buffer(source_pa, size, false);
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+    // Verify destination buffer.
+    status = scp_pvt_Validate_Buffer(dest_pa, size, true);
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+    // Check for partial overlap (exact aliasing is fine).
+    if ((source_pa != dest_pa) &&
+        memutils_mem_has_overlap(source_pa, size, dest_pa, size))
+    {
+        status = E_SCP_INVALID_ADDRESS;
+        goto cleanup;
+    }
+
+    // Verify byte count.
+    if ((size == 0U) || (size % SCP_BLOCK_SIZE != 0U))
+    {
+        status = E_SCP_INVALID_REQUEST;
+        goto cleanup;
+    }
+
+    // Verify mode of operation.
+    switch (cipher_mode)
+    {
+        case SCP_CIPHER_MODE_ECB:
+            // No context in ECB mode.
+            if (context_pa != (uintptr_t)NULL)
+            {
+                status = E_SCP_INVALID_OPERATION;
+                goto cleanup;
+            }
+            break;
+
+        case SCP_CIPHER_MODE_CBC:
+        case SCP_CIPHER_MODE_CTR:
+            // Verify context buffer for other modes.
+            status = scp_pvt_Validate_Buffer(context_pa, SCP_BLOCK_SIZE, false);
+            if (status != E_SUCCESS)
+            {
+                goto cleanup;
+            }
+            break;
+
+        default:
+            // Not a recognized block-cipher mode.
+            status = E_SCP_INVALID_OPERATION;
+            goto cleanup;
+    }
+
+    // Verify key-descriptor, load key into register-index zero, and update Ku.
+    status = s_scp_Load_Key(p_key_desc);
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+    // Load initial context information (if any) into register-index one.
+    if (context_pa != (uintptr_t)NULL)
+    {
+        status = scp_pvt_Load_Buffer(context_pa, SCP_REGISTER_INDEX_1);
+        if (status != E_SUCCESS)
+        {
+            goto cleanup;
+        }
+    }
+
+    // Load sequencer zero with the instructions for the selected cipher mode.
+    status = s_scp_Load_Crypt_Sequence(cipher_mode, b_decrypt);
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+    // Run the input data through the sequence we loaded above.
+    status = scp_pvt_Run_Sequence(source_pa, dest_pa, size);
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+cleanup:
+    //
+    // Clear the sequencers to free them up for future use and prevent
+    // anything accidentally carrying forward into other interfaces.
+    //
+    scp_pvt_Reset_Sequencers();
+
+    //
+    // Clear the SCP GPRs to scrub any potentially sensitive data from them and
+    // unlock their associated ACLs. Report failures only if no higher-priority
+    // error is already pending.
+    //
+    error_t clear_status = scp_pvt_Clear_All();
+    if (status == E_SUCCESS)
+    {
+        status = clear_status;
+    }
+
+    // Done.
+    return status;
+}
+
+/**
+ * @brief Computes the CMAC of an arbitrary buffer of data.
+ *
+ * Computes the CMAC of the first size bytes of data from source_pa using the
+ * key described by p_key_desc and writes the result to SCP register-index one.
+ * Uses an AES-128 block cipher for the operation. If provided, SCP_BLOCK_SIZE
+ * bytes from context_pa are used as the initial contextual input (IV) for the
+ * computation.
+ *
+ * When cmac_mode is SCP_CMAC_MODE_PARTIAL, s_scp_Cmac() skips the final step of
+ * the CMAC computation, thus allowing the result to be chained into a future
+ * call via context_pa. The full CMAC result can then be obtained by passing
+ * SCP_CMAC_MODE_COMPLETE, as is done for singular, unchained calls.
+ *
+ * Notice that it is the application's responsibility to pad the source message
+ * if needed (by appending 0b10...0 per the CMAC specification) and to signal
+ * that padding has occurred by setting cmac_mode to SCP_CMAC_MODE_PADDED in
+ * place of SCP_CMAC_MODE_COMPLETE.
+ *
+ * Should p_key_desc describe a derived key, the s_scp_Cmac() function will
+ * perform the indicated key-derivation operation automatically. See the
+ * relevant SCP_KEY_* macros for details.
+ *
+ * Note that this function uses register-indices zero through three for
+ * intermediate storage and also loads instructions into sequencer zero. The
+ * caller is responsible for clearing these resources before returning to the
+ * client application.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre The SCP driver must not be operating in direct mode.
+ * @pre Must be called from a secure context if SCP lockdown is enabled.
+ *
+ * @param[in]  p_key_desc   A pointer to the key-descriptor to be used for the
+ *                          CMAC computation. Applications should acquire this
+ *                          parameter through one of the provided SCP_KEY_*
+ *                          macros.
+ *
+ * @param[in]  cmac_mode    The CMAC mode of operation to use. See the
+ *                          documentation for scp_cmac_mode_t for a list of
+ *                          supported values.
+ *
+ * @param[in]  source_pa    The physical address of the input buffer for which
+ *                          the CMAC will be computed. Must be aligned to
+ *                          SCP_BUFFER_ALIGNMENT and contain at least size
+ *                          bytes. Supports IMEM and DMEM locations only.
+ *
+ * @param[in]  size         The number of bytes to process from source_pa. Must
+ *                          be a nonzero multiple of SCP_BLOCK_SIZE.
+ *
+ * @param[in]  context_pa   The physical address of the input buffer containing
+ *                          the result of a prior partial CMAC computation, if
+ *                          applicable. Must be aligned to SCP_BUFFER_ALIGNMENT
+ *                          and contain at least SCP_BLOCK_SIZE bytes. Should
+ *                          be zero (NULL) or should point to an all-zero
+ *                          buffer if not continuing a prior computation.
+ *                          Supports IMEM and DMEM locations only.
+ *
+ * @retval E_SUCCESS                    if CMAC was computed successfully.
+ *
+ * @retval E_SCP_INVALID_OBJECT         if p_key_desc does not point to a valid
+ *                                      key-descriptor.
+ *
+ * @retval E_SCP_INVALID_OBJECT_BUFFER  if p_key_desc was constructed with a
+ *                                      zero (NULL) or incorrectly-aligned
+ *                                      address, or a pointer to an unsupported
+ *                                      memory location (e.g. EMEM), or a buffer
+ *                                      that overflows the memory region in
+ *                                      which it resides, or a buffer of invalid
+ *                                      size.
+ *
+ * @retval E_SCP_INVALID_INDEX          if p_key_desc was constructed with an
+ *                                      invalid register or hardware-secret
+ *                                      index, or references secret-index zero.
+ *
+ * @retval E_PERM                       if p_key_desc was constructed with a
+ *                                      hardware-secret index that the
+ *                                      application does not have permission to
+ *                                      use.
+ *
+ * @retval E_SCP_INVALID_POINTER        if one or both of p_key_desc or
+ *                                      source_pa is zero/NULL.
+ *
+ * @retval E_SCP_INVALID_ADDRESS        if one or both of source_pa or
+ *                                      context_pa is incorrectly aligned, or
+ *                                      the buffers referenced by source_pa and
+ *                                      context_pa overlap.
+ *
+ * @retval E_SCP_INVALID_BASE           if one or both of source_pa or
+ *                                      context_pa points to an unsupported
+ *                                      memory region (e.g. EMEM).
+ *
+ * @retval E_SCP_INVALID_REQUEST        if size is zero or is not a multiple of
+ *                                      SCP_BLOCK_SIZE.
+ *
+ * @retval E_SCP_INVALID_OPERATION      if cmac_mode is not a valid
+ *                                      scp_cmac_mode_t value.
+ *
+ * @retval E_SCP_OUT_OF_RANGE           if one or both of the buffers referenced
+ *                                      by source_pa or context_pa overflows the
+ *                                      memory region in which it resides.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_FAULT                      if an IO-PMP fault was detected.
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ */
+static error_t
+s_scp_Cmac
+(
+    const scp_key_desc_t *  p_key_desc,
+    scp_cmac_mode_t         cmac_mode,
+    uintptr_t               source_pa,
+    size_t                  size,
+    uintptr_t               context_pa
+)
+{
+    error_t     status      = E_SUCCESS;
+    size_t      batch_size  = size;
+    bool        b_padded    = false;
+
+    // Verify source buffer.
+    status = scp_pvt_Validate_Buffer(source_pa, size, false);
+    if (status != E_SUCCESS)
+    {
+        return status;
+    }
+
+    // Verify byte count.
+    if ((size == 0U) || (size % SCP_BLOCK_SIZE != 0U))
+    {
+        return E_SCP_INVALID_REQUEST;
+    }
+
+    // Verify context buffer, if provided.
+    if (context_pa != (uintptr_t)NULL)
+    {
+        status = scp_pvt_Validate_Buffer(context_pa, SCP_BLOCK_SIZE, false);
+        if (status != E_SUCCESS)
+        {
+            return status;
+        }
+
+        // Check for overlap with source buffer.
+        if (memutils_mem_has_overlap(source_pa, size, context_pa,
+                SCP_BLOCK_SIZE))
+        {
+            return E_SCP_INVALID_ADDRESS;
+        }
+    }
+
+    // Verify mode of operation.
+    switch (cmac_mode)
+    {
+        case SCP_CMAC_MODE_PADDED:
+            b_padded = true;
+            // Fall-through.
+
+        case SCP_CMAC_MODE_COMPLETE:
+            //
+            // The final block in non-partial messages requires special
+            // handling, so exclude it from the inital batch.
+            //
+            batch_size -= SCP_BLOCK_SIZE;
+            break;
+
+        case SCP_CMAC_MODE_PARTIAL:
+            // Nothing to do.
+            break;
+
+        default:
+            // Not a recognized operating mode.
+            return E_SCP_INVALID_OPERATION;
+    }
+
+    // Verify key-descriptor, load key into register-index zero, and update Ku.
+    status = s_scp_Load_Key(p_key_desc);
+    if (status != E_SUCCESS)
+    {
+        return status;
+    }
+
+    // Load initial context information if provided.
+    if (context_pa != (uintptr_t)NULL)
+    {
+        status = scp_pvt_Load_Buffer(context_pa, SCP_REGISTER_INDEX_1);
+        if (status != E_SUCCESS)
+        {
+            return status;
+        }
+    }
+    // Otherwise, use zero.
+    else
+    {
+        status = scp_pvt_Clear_Reg(SCP_REGISTER_INDEX_1);
+        if (status != E_SUCCESS)
+        {
+            return status;
+        }
+    }
+
+    // Load sequencer zero with the instructions for CMAC.
+    status = s_scp_Load_Cmac_Sequence();
+    if (status != E_SUCCESS)
+    {
+        return status;
+    }
+
+    // Run the input data through the sequence we loaded above.
+    status = scp_pvt_Run_Sequence(source_pa, (uintptr_t)NULL, batch_size);
+    if (status != E_SUCCESS)
+    {
+        return status;
+    }
+
+    // Handle the final block if needed.
+    if (batch_size != size)
+    {
+        status = s_scp_Complete_Cmac((source_pa + batch_size), b_padded);
+        if (status != E_SUCCESS)
+        {
+            return status;
+        }
+    }
+
+    // Done.
+    return status;
+}
+
+/**
+ * @brief Validates a key-descriptor and then loads the key it describes to R0.
+ *
+ * Checks the provided key-descriptor for errors and then loads the key it
+ * describes into register-index zero. Automatically performs any key-
+ * derivation operations as required and updates the key register (Ku) to
+ * point to the newly-loaded key.
+ *
+ * Note that this function may use register-indices one through three for
+ * intermediate storage and may load instructions into sequencer zero.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre The SCP driver must not be operating in direct mode.
+ * @pre For register-type keys, the source register must be writable and
+ *      fetchable if called from an insecure context.
+ *
+ * @param[in]  p_key_desc   A pointer to the key-descriptor to be processed.
+ *
+ * @retval E_SUCCESS                    if key was loaded successfully.
+ *
+ * @retval E_SCP_INVALID_OBJECT         if p_key_desc does not point to a valid
+ *                                      key-descriptor.
+ *
+ * @retval E_SCP_INVALID_OBJECT_BUFFER  if p_key_desc was constructed with a
+ *                                      zero (NULL) or incorrectly-aligned
+ *                                      address, or a pointer to an unsupported
+ *                                      memory location (e.g. EMEM), or a buffer
+ *                                      that overflows the memory region in
+ *                                      which it resides, or a buffer of invalid
+ *                                      size.
+ *
+ * @retval E_SCP_INVALID_INDEX          if p_key_desc was constructed with an
+ *                                      invalid register or hardware-secret
+ *                                      index, or references secret-index zero.
+ *
+ * @retval E_PERM                       if p_key_desc was constructed with a
+ *                                      hardware-secret index that the
+ *                                      application does not have permission to
+ *                                      use.
+ *
+ * @retval E_SCP_INVALID_POINTER        if p_key_desc is NULL.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_FAULT                      if an IO-PMP fault was detected.
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ */
+static error_t
+s_scp_Load_Key
+(
+    const scp_key_desc_t * p_key_desc
+)
+{
+    error_t status;
+
+    // Check for valid pointer.
+    if (p_key_desc == NULL)
+    {
+        return E_SCP_INVALID_POINTER;
+    }
+
+    // Load the requested key based on its type.
+    switch (p_key_desc->key_type)
+    {
+        case SCP_KEY_TYPE_RAW_BUFFER:
+            status = s_scp_Load_Buffer_Key(p_key_desc->raw_buffer_pa);
+            break;
+
+        case SCP_KEY_TYPE_RAW_REGISTER:
+            status = s_scp_Load_Register_Key(p_key_desc->raw_register_index);
+            break;
+
+        case SCP_KEY_TYPE_DERIVED_ECB:
+            status = s_scp_Load_Ecb_Key(p_key_desc->ecb_secret_index,
+                                        p_key_desc->ecb_salt_pa);
+            break;
+
+        case SCP_KEY_TYPE_DERIVED_CBC:
+            status = s_scp_Load_Cbc_Key(p_key_desc->cbc_secret_index,
+                                        p_key_desc->cbc_salt_pa,
+                                        p_key_desc->cbc_iv_pa);
+            break;
+
+        case SCP_KEY_TYPE_DERIVED_CMAC:
+            status = s_scp_Load_Cmac_Key(p_key_desc->cmac_secret_index,
+                                         p_key_desc->cmac_message_pa,
+                                         p_key_desc->cmac_size,
+                                         p_key_desc->cmac_padded);
+            break;
+
+        default:
+            // Not a recognized key type.
+            return E_SCP_INVALID_OBJECT;
+    }
+
+    // Report any errors to the caller.
+    if (status != E_SUCCESS)
+    {
+        return status;
+    }
+
+    //
+    // Restrict the key's associated ACL to the bare minimum required for
+    // encryption and decryption operations.
+    //
+    if (scp_pvt_Is_Secure())
+    {
+        scp_chmod(SCP_REGISTER_ACL_KEY, SCP_REGISTER_INDEX_0);
+    }
+
+    // Update the key register to point to the newly-loaded key.
+    scp_key(SCP_REGISTER_INDEX_0);
+
+    // Wait for the above operations to complete.
+    scp_wait_dma();
+
+    // Check for any unexpected failures.
+    if (scp_check_dma(true) != E_SUCCESS)
+    {
+        return E_SCP_GENERIC;
+    }
+
+    // Key was loaded successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @brief Loads a raw key from the provided buffer into R0.
+ *
+ * Validates the buffer referenced by key_pa and then loads the first
+ * SCP_KEY_SIZE bytes from it into register-index zero.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ *
+ * @param[in]  key_pa   The physical address of the input buffer containing the
+ *                      raw key to be loaded.
+ *
+ * @retval E_SUCCESS                    if key was loaded successfully.
+ *
+ * @retval E_SCP_INVALID_OBJECT_BUFFER  if key_pa is zero (NULL) or incorrectly-
+ *                                      aligned, or points to an unsupported
+ *                                      memory location (e.g. EMEM), or
+ *                                      references a buffer that overflows the
+ *                                      memory region in which it resides.
+ *
+ * @retval E_FAULT                      if an IO-PMP fault was detected.
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ */
+static error_t
+s_scp_Load_Buffer_Key
+(
+    uintptr_t key_pa
+)
+{
+    // Validate the source buffer.
+    if (scp_pvt_Validate_Buffer(key_pa, SCP_KEY_SIZE, false) != E_SUCCESS)
+    {
+        return E_SCP_INVALID_OBJECT_BUFFER;
+    }
+
+    // Load into register-index zero.
+    return scp_pvt_Load_Buffer(key_pa, SCP_REGISTER_INDEX_0);
+}
+
+/**
+ * @brief Loads a raw key from the indicated SCP GPR into R0.
+ *
+ * Copies the contents of the register specified by reg_index into register-
+ * index zero. Clears the source register after copying.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre The source register must be writable and fetchable if called from an
+ *      insecure context.
+ *
+ * @param[in]  reg_index    The index of the SCP register containing the raw
+ *                          key to be loaded.
+ *
+ * @retval E_SUCCESS                    if key was loaded successfully.
+ *
+ * @retval E_SCP_INVALID_INDEX          if reg_index is not a valid
+ *                                      scp_register_index_t value.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ */
+static error_t
+s_scp_Load_Register_Key
+(
+    scp_register_index_t reg_index
+)
+{
+    // Validate the register index.
+    if (reg_index > SCP_REGISTER_INDEX_7)
+    {
+        return E_SCP_INVALID_INDEX;
+    }
+
+    // No-op if already in R0.
+    if (reg_index == SCP_REGISTER_INDEX_0)
+    {
+        return E_SUCCESS;
+    }
+
+    // Copy into register-index zero.
+    scp_mov(reg_index, SCP_REGISTER_INDEX_0);
+    scp_wait_dma();
+
+    // Check for any unexpected failures.
+    if (scp_check_dma(true) != E_SUCCESS)
+    {
+        return E_SCP_GENERIC;
+    }
+
+    // Clear the source register.
+    return scp_pvt_Clear_Reg(reg_index);
+}
+
+/**
+ * @brief Loads a key derived via AES-ECB of a provided salt value into R0.
+ *
+ * Performs AES-ECB encryption on the first SCP_BLOCK_SIZE bytes from salt_pa,
+ * using the hardware-secret indicated by secret_index as the key, and stores
+ * the result in register-index zero.
+ *
+ * Note that this function uses register-index one for intermediate values.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ *
+ * @param[in]  secret_index The index of the hardware-secret to be used in the
+ *                          key-derivation process.
+ *
+ * @param[in]  salt_pa      The physical address of the input buffer containing
+ *                          the salt value to be used in the key-derivation
+ *                          process.
+ *
+ * @retval E_SUCCESS                    if key was loaded successfully.
+ *
+ * @retval E_SCP_INVALID_OBJECT_BUFFER  if salt_pa is zero (NULL) or
+ *                                      incorrectly-aligned, or points to an
+ *                                      unsupported memory location (e.g. EMEM),
+ *                                      or references a buffer that overflows
+ *                                      the memory region in which it resides.
+ *
+ * @retval E_SCP_INVALID_INDEX          if secret_index is not a valid SCP
+ *                                      secret-index, or references secret-index
+ *                                      zero.
+ *
+ * @retval E_PERM                       if secret_index references a hardware-
+ *                                      secret that the application does not
+ *                                      have permission to use.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_FAULT                      if an IO-PMP fault was detected.
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ */
+static error_t
+s_scp_Load_Ecb_Key
+(
+    uint8_t     secret_index,
+    uintptr_t   salt_pa
+)
+{
+    error_t status;
+
+    // Verify context (hardware secrets cannot be used in insecure contexts).
+    if (!scp_pvt_Is_Secure())
+    {
+        return E_PERM;
+    }
+
+    // Validate the secret index.
+    // TODO(COREUCODES-1846): Reinstate check against SCP_SECRET_INDEX_CLEAR.
+    if (secret_index >= SCP_SECRET_COUNT)
+    {
+        return E_SCP_INVALID_INDEX;
+    }
+
+    // Validate the salt buffer.
+    if (scp_pvt_Validate_Buffer(salt_pa, SCP_BLOCK_SIZE, false) != E_SUCCESS)
+    {
+        return E_SCP_INVALID_OBJECT_BUFFER;
+    }
+
+    // Load the salt value into a temporary register.
+    scp_load(salt_pa, SCP_REGISTER_INDEX_1);
+    scp_wait_dma();
+
+    // Load the hardware secret into the destination register.
+    scp_secret(secret_index, SCP_REGISTER_INDEX_0);
+
+    // Encrypt the salt with the hardware secret.
+    scp_key(SCP_REGISTER_INDEX_0);
+    scp_encrypt(SCP_REGISTER_INDEX_1, SCP_REGISTER_INDEX_0);
+
+    // Wait for completion.
+    scp_wait_dma();
+
+    // Check for any failures.
+    status = scp_check_dma(true);
+    if ((status == E_PERM) || (status == E_FAULT))
+    {
+        // Bubble up permissions and IO-PMP errors.
+        return status;
+    }
+    else if (status != E_SUCCESS)
+    {
+        // No other errors are expected.
+        return E_SCP_GENERIC;
+    }
+
+    // Clear the temporary register.
+    return scp_pvt_Clear_Reg(SCP_REGISTER_INDEX_1);
+}
+
+/**
+ * @brief Loads a key derived via AES-CBC of a provided salt value into R0.
+ *
+ * Performs AES-CBC encryption on the first SCP_BLOCK_SIZE bytes from salt_pa,
+ * using the hardware-secret indicated by secret_index as the key and the first
+ * SCP_BLOCK_SIZE bytes from iv_pa as the initialization vector, and stores
+ * the result in register-index zero.
+ *
+ * Note that this function uses register-index one for intermediate values.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ *
+ * @param[in]  secret_index The index of the hardware-secret to be used in the
+ *                          key-derivation process.
+ *
+ * @param[in]  salt_pa      The physical address of the input buffer containing
+ *                          the salt value to be used in the key-derivation
+ *                          process.
+ *
+ * @param[in]  iv_pa        The physical address of the input buffer containing
+ *                          the initialization vector to be used in the key-
+ *                          derivation process.
+ *
+ * @retval E_SUCCESS                    if key was loaded successfully.
+ *
+ * @retval E_SCP_INVALID_OBJECT_BUFFER  if one or more of salt_pa or iv_pa is
+ *                                      zero (NULL) or incorrectly-aligned, or
+ *                                      points to an unsupported memory location
+ *                                      (e.g. EMEM), or references a buffer that
+ *                                      overflows the memory region in which it
+ *                                      resides.
+ *
+ * @retval E_SCP_INVALID_INDEX          if secret_index is not a valid SCP
+ *                                      secret-index, or references secret-index
+ *                                      zero.
+ *
+ * @retval E_PERM                       if secret_index references a hardware-
+ *                                      secret that the application does not
+ *                                      have permission to use.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_FAULT                      if an IO-PMP fault was detected.
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ */
+static error_t
+s_scp_Load_Cbc_Key
+(
+    uint8_t     secret_index,
+    uintptr_t   salt_pa,
+    uintptr_t   iv_pa
+)
+{
+    error_t status;
+
+    // Verify context (hardware secrets cannot be used in insecure contexts).
+    if (!scp_pvt_Is_Secure())
+    {
+        return E_PERM;
+    }
+
+    // Validate the secret index.
+    // TODO(COREUCODES-1846): Reinstate check against SCP_SECRET_INDEX_CLEAR.
+    if (secret_index >= SCP_SECRET_COUNT)
+    {
+        return E_SCP_INVALID_INDEX;
+    }
+
+    // Validate the salt buffer.
+    if (scp_pvt_Validate_Buffer(salt_pa, SCP_BLOCK_SIZE, false) != E_SUCCESS)
+    {
+        return E_SCP_INVALID_OBJECT_BUFFER;
+    }
+
+    // Validate the IV buffer.
+    if (scp_pvt_Validate_Buffer(iv_pa, SCP_BLOCK_SIZE, false) != E_SUCCESS)
+    {
+        return E_SCP_INVALID_OBJECT_BUFFER;
+    }
+
+    // Load the IV and salt values into registers.
+    scp_load(iv_pa, SCP_REGISTER_INDEX_0);
+    scp_load(salt_pa, SCP_REGISTER_INDEX_1);
+    scp_wait_dma();
+
+    // XOR the IV and salt as the first step of CBC encryption.
+    scp_xor(SCP_REGISTER_INDEX_0, SCP_REGISTER_INDEX_1);
+
+    // Load the hardware secret into the destination register.
+    scp_secret(secret_index, SCP_REGISTER_INDEX_0);
+
+    // Encrypt the XORed salt with the hardware secret.
+    scp_key(SCP_REGISTER_INDEX_0);
+    scp_encrypt(SCP_REGISTER_INDEX_1, SCP_REGISTER_INDEX_0);
+
+    // Wait for completion.
+    scp_wait_dma();
+
+    // Check for any failures.
+    status = scp_check_dma(true);
+    if ((status == E_PERM) || (status == E_FAULT))
+    {
+        // Bubble up permissions and IO-PMP errors.
+        return status;
+    }
+    else if (status != E_SUCCESS)
+    {
+        // No other errors are expected.
+        return E_SCP_GENERIC;
+    }
+
+    // Clear the temporary register.
+    return scp_pvt_Clear_Reg(SCP_REGISTER_INDEX_1);
+}
+
+/**
+ * @brief Loads a key derived via AES-CMAC of a provided message into R0.
+ *
+ * Computes the CMAC of the first size bytes from message_pa, using the
+ * hardware-secret indicated by secret_index as the key, and stores the result
+ * in register-index zero. Assumes that the input has been padded per the CMAC
+ * specification if b_padded is true.
+ *
+ * Note that this function uses register-indices one through three for
+ * intermediate values and also loads instructions into sequencer zero.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre The SCP driver must not be operating in direct mode.
+ *
+ * @param[in]  secret_index The index of the hardware-secret to be used in the
+ *                          key-derivation process.
+ *
+ * @param[in]  message_pa   The physical address of the input buffer containing
+ *                          the message to be used in the key-derivation
+ *                          process.
+ *
+ * @param[in]  size         The number of bytes to process from message_pa.
+ *
+ * @param[in]  b_padded     A boolean value indicating whether the source
+ *                          message contains padding.
+ *
+ * @retval E_SUCCESS                    if key was loaded successfully.
+ *
+ * @retval E_SCP_INVALID_OBJECT_BUFFER  if message_pa is zero (NULL) or
+ *                                      incorrectly-aligned, or points to an
+ *                                      unsupported memory location (e.g. EMEM),
+ *                                      or references a buffer that overflows
+ *                                      the memory region in which it resides,
+ *                                      or references a buffer of invalid size.
+ *
+ * @retval E_SCP_INVALID_INDEX          if secret_index is not a valid SCP
+ *                                      secret-index, or references secret-index
+ *                                      zero.
+ *
+ * @retval E_PERM                       if secret_index references a hardware-
+ *                                      secret that the application does not
+ *                                      have permission to use.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_FAULT                      if an IO-PMP fault was detected.
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ */
+static error_t
+s_scp_Load_Cmac_Key
+(
+    uint8_t     secret_index,
+    uintptr_t   message_pa,
+    size_t      size,
+    bool        b_padded
+)
+{
+    error_t status;
+
+    // Verify context (hardware secrets cannot be used in insecure contexts).
+    if (!scp_pvt_Is_Secure())
+    {
+        return E_PERM;
+    }
+
+    // Validate the secret index.
+    // TODO(COREUCODES-1846): Reinstate check against SCP_SECRET_INDEX_CLEAR.
+    if (secret_index >= SCP_SECRET_COUNT)
+    {
+        return E_SCP_INVALID_INDEX;
+    }
+
+    // Load the requested hardware secret.
+    scp_secret(secret_index, SCP_REGISTER_INDEX_0);
+    scp_wait_dma();
+
+    // Check for any failures.
+    status = scp_check_dma(true);
+    if (status == E_PERM)
+    {
+        // Bubble up permissions errors.
+        return status;
+    }
+    else if (status != E_SUCCESS)
+    {
+        // No other errors are expected.
+        return E_SCP_GENERIC;
+    }
+
+    // Generate derived key in register-index one.
+    status = s_scp_Cmac(SCP_KEY_RAW_REGISTER(SCP_REGISTER_INDEX_0),
+        b_padded ? SCP_CMAC_MODE_PADDED : SCP_CMAC_MODE_COMPLETE,
+        message_pa, size, (uintptr_t)NULL);
+    switch (status)
+    {
+        // Continue on success.
+        case E_SUCCESS:
+            break;
+
+        // Translate buffer-related errors.
+        case E_SCP_INVALID_POINTER:
+        case E_SCP_INVALID_ADDRESS:
+        case E_SCP_INVALID_BASE:
+        case E_SCP_INVALID_REQUEST:
+        case E_SCP_OUT_OF_RANGE:
+            return E_SCP_INVALID_OBJECT_BUFFER;
+
+        // Bubble-up other plausible errors.
+        case E_SCP_INSUFFICIENT_RESOURCES:
+        case E_FAULT:
+            return status;
+
+        // Anything else is unexpected.
+        default:
+            return E_SCP_GENERIC;
+    }
+
+    // Move key to destination register.
+    scp_mov(SCP_REGISTER_INDEX_1, SCP_REGISTER_INDEX_0);
+    scp_wait_dma();
+
+    // Check for any unexpected failures.
+    if (scp_check_dma(true) != E_SUCCESS)
+    {
+        return E_SCP_GENERIC;
+    }
+
+    // Clear the source register.
+    return scp_pvt_Clear_Reg(SCP_REGISTER_INDEX_1);
+}
+
+/**
+ * @brief Loads the requested cryptographic algorithm into sequencer zero.
+ *
+ * Loads sequencer zero with the set of SCP instructions corresponding to a
+ * single iteration of the requested block-cipher algorithm. Uses the
+ * decryption form if b_decrypt is true and the encryption form otherwise.
+ *
+ * The loaded algorithm assumes that key material has already been loaded to
+ * register-index zero and has also been selected via the scp_key()
+ * instruction. It further assumes that any context information has been loaded
+ * to register-index one and that register-indices two and three are available
+ * for use as intermediate storage.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ *
+ * @param[in]  cipher_mode  The block-cipher algorithm to load.
+ *
+ * @param[in]  b_decrypt    A boolean value indicating whether to load the
+ *                          decryption sequence for the selected algorithm
+ *                          rather than the encryption sequence.
+ *
+ * @retval E_SUCCESS                if algorithm was loaded successfully.
+ * @retval E_SCP_GENERIC            if an unexpected error occurred.
+ */
+static error_t
+s_scp_Load_Crypt_Sequence
+(
+    scp_cipher_mode_t   cipher_mode,
+    bool                b_decrypt
+)
+{
+    // Load the correct sequence for the requested block-cipher mode.
+    switch (cipher_mode)
+    {
+        case SCP_CIPHER_MODE_ECB:
+            return s_scp_Load_Ecb_Sequence(b_decrypt);
+
+        case SCP_CIPHER_MODE_CBC:
+            return s_scp_Load_Cbc_Sequence(b_decrypt);
+
+        case SCP_CIPHER_MODE_CTR:
+            return s_scp_Load_Ctr_Sequence();
+
+        default:
+            //
+            // Not a recognized block-cipher mode. This should have been
+            // validated already by the caller so treat as unexpected.
+            //
+            return E_SCP_GENERIC;
+    }
+}
+
+/**
+ * @brief Loads the SCP instructions for AES-ECB into sequencer zero.
+ *
+ * Loads sequencer zero with the set of SCP instructions corresponding to a
+ * single iteration of AES-ECB encryption/decryption. Uses the decryption
+ * algorithm if b_decrypt is true and the encryption algorithm otherwise.
+ *
+ * The loaded algorithm assumes that key material has already been loaded to
+ * register-index zero and has also been selected via the scp_key()
+ * instruction (but not yet converted via scp_rkey10(), if applicable). It
+ * further assumes that register-index two is available for use as intermediate
+ * storage.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ *
+ * @param[in]  b_decrypt    A boolean value indicating whether to load the
+ *                          decryption sequence rather than the encryption
+ *                          sequence.
+ *
+ * @retval E_SUCCESS                if instructions were loaded successfully.
+ * @retval E_SCP_GENERIC            if an unexpected error occurred.
+ */
+static error_t
+s_scp_Load_Ecb_Sequence
+(
+    bool b_decrypt
+)
+{
+    // Prepare to write three instructions to sequencer zero.
+    scp_load_trace0(3U);
+    {
+        // Load the next block of plaintext/ciphertext to process.
+        scp_push(SCP_REGISTER_INDEX_2);
+
+        if (b_decrypt)
+        {
+            // Decrypt the ciphertext in-place.
+            scp_decrypt(SCP_REGISTER_INDEX_2, SCP_REGISTER_INDEX_2);
+        }
+        else
+        {
+            // Encrypt the plaintext in-place.
+            scp_encrypt(SCP_REGISTER_INDEX_2, SCP_REGISTER_INDEX_2);
+        }
+
+        // Store the resulting ciphertext/plaintext.
+        scp_fetch(SCP_REGISTER_INDEX_2);
+    }
+
+    //
+    // Convert the key loaded in register-index zero to the form required for
+    // decryption operations, if applicable. This only needs to be done once,
+    // hence its exclusion from the above sequencer load.
+    //
+    if (b_decrypt)
+    {
+        scp_rkey10(SCP_REGISTER_INDEX_0, SCP_REGISTER_INDEX_0);
+    }
+
+    // Wait for completion.
+    scp_wait_dma();
+
+    // Check for any unexpected failures.
+    if (scp_check_dma(true) != E_SUCCESS)
+    {
+        return E_SCP_GENERIC;
+    }
+
+    // Sequence loaded successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @brief Loads the SCP instructions for AES-CBC into sequencer zero.
+ *
+ * Loads sequencer zero with the set of SCP instructions corresponding to a
+ * single iteration of AES-CBC encryption/decryption. Uses the decryption
+ * algorithm if b_decrypt is true and the encryption algorithm otherwise.
+ *
+ * The loaded algorithm assumes that key material has already been loaded to
+ * register-index zero and has also been selected via the scp_key()
+ * instruction (but not yet converted via scp_rkey10(), if applicable). It
+ * further assumes that the initialization vector has been loaded to register-
+ * index one and that register-indices two and three are available for use as
+ * intermediate storage.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ *
+ * @param[in]  b_decrypt    A boolean value indicating whether to load the
+ *                          decryption sequence rather than the encryption
+ *                          sequence.
+ *
+ * @retval E_SUCCESS                if instructions were loaded successfully.
+ * @retval E_SCP_GENERIC            if an unexpected error occurred.
+ */
+static error_t
+s_scp_Load_Cbc_Sequence
+(
+    bool b_decrypt
+)
+{
+    // Split because decryption requires an extra instruction over encryption.
+    if (b_decrypt)
+    {
+        // Prepare to write five instructions to sequencer zero.
+        scp_load_trace0(5U);
+        {
+            // Load the next block of ciphertext to process.
+            scp_push(SCP_REGISTER_INDEX_2);
+
+            // Decrypt non-destructively.
+            scp_decrypt(SCP_REGISTER_INDEX_2, SCP_REGISTER_INDEX_3);
+
+            // XOR with the current "IV" to obtain the plaintext.
+            scp_xor(SCP_REGISTER_INDEX_1, SCP_REGISTER_INDEX_3);
+
+            // Carry the original ciphertext forward as the new "IV".
+            scp_mov(SCP_REGISTER_INDEX_2, SCP_REGISTER_INDEX_1);
+
+            // Store the resulting plaintext.
+            scp_fetch(SCP_REGISTER_INDEX_3);
+        }
+
+        //
+        // Convert the key loaded in register-index zero to the form required
+        // for decryption operations. This only needs to be done once, hence
+        // its exclusion from the above sequencer load.
+        //
+        scp_rkey10(SCP_REGISTER_INDEX_0, SCP_REGISTER_INDEX_0);
+    }
+    else
+    {
+        // Prepare to write four instructions to sequencer zero.
+        scp_load_trace0(4U);
+        {
+            // Load the next block of plaintext to process.
+            scp_push(SCP_REGISTER_INDEX_2);
+
+            // XOR with the current "IV".
+            scp_xor(SCP_REGISTER_INDEX_1, SCP_REGISTER_INDEX_2);
+
+            // Encrypt to obtain the ciphertext and save as the new "IV".
+            scp_encrypt(SCP_REGISTER_INDEX_2, SCP_REGISTER_INDEX_1);
+
+            // Store the resulting ciphertext.
+            scp_fetch(SCP_REGISTER_INDEX_1);
+        }
+    }
+
+    // Wait for completion.
+    scp_wait_dma();
+
+    // Check for any unexpected failures.
+    if (scp_check_dma(true) != E_SUCCESS)
+    {
+        return E_SCP_GENERIC;
+    }
+
+    // Sequence loaded successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @brief Loads the SCP instructions for AES-CTR into sequencer zero.
+ *
+ * Loads sequencer zero with the set of SCP instructions corresponding to a
+ * single iteration of AES-CTR encryption/decryption.
+ *
+ * The loaded algorithm assumes that key material has already been loaded to
+ * register-index zero and has also been selected via the scp_key()
+ * instruction. It further assumes that the initial counter value (with nonce)
+ * has been loaded to register-index one and that register-indices two and
+ * three are available for use as intermediate storage.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ *
+ * @retval E_SUCCESS                if instructions were loaded successfully.
+ * @retval E_SCP_GENERIC            if an unexpected error occurred.
+ */
+static error_t
+s_scp_Load_Ctr_Sequence(void)
+{
+    // Prepare to write five instructions to sequencer zero.
+    scp_load_trace0(5U);
+    {
+        // Load the next block of plaintext/ciphertext to process.
+        scp_push(SCP_REGISTER_INDEX_3);
+
+        // Encrypt the current counter value (with nonce) non-destructively.
+        scp_encrypt(SCP_REGISTER_INDEX_1, SCP_REGISTER_INDEX_2);
+
+        // XOR with the current block to obtain the ciphertext/plaintext.
+        scp_xor(SCP_REGISTER_INDEX_2, SCP_REGISTER_INDEX_3);
+
+        // Update the current counter value.
+        scp_add(1U, SCP_REGISTER_INDEX_1);
+
+        // Store the resulting ciphertext/plaintext.
+        scp_fetch(SCP_REGISTER_INDEX_3);
+    }
+
+    // Wait for completion.
+    scp_wait_dma();
+
+    // Check for any unexpected failures.
+    if (scp_check_dma(true) != E_SUCCESS)
+    {
+        return E_SCP_GENERIC;
+    }
+
+    // Sequence loaded successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @brief Loads the SCP instructions for DmHash into sequencer zero.
+ *
+ * Loads sequencer zero with the set of SCP instructions required to compute
+ * the Davies-Meyer hash of a single block of data. Also updates the key
+ * register (Ku).
+ *
+ * The loaded algorithm assumes that the initial hash value (H0) has been
+ * loaded to register-index one and that register-indices two and three are
+ * available for use as intermediate storage.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ *
+ * @retval E_SUCCESS                if instructions were loaded successfully.
+ * @retval E_SCP_GENERIC            if an unexpected error occurred.
+ */
+static error_t
+s_scp_Load_Hash_Sequence(void)
+{
+    // Prepare to write three instructions to sequencer zero.
+    scp_load_trace0(3U);
+    {
+        // Load the next block of the message to process.
+        scp_push(SCP_REGISTER_INDEX_2);
+
+        // Encrypt the previous hash value with the message.
+        scp_encrypt(SCP_REGISTER_INDEX_1, SCP_REGISTER_INDEX_3);
+
+        // XOR with the previous hash value to obtain the new hash value.
+        scp_xor(SCP_REGISTER_INDEX_3, SCP_REGISTER_INDEX_1);
+    }
+
+    //
+    // Select the register from which the encrypt stage of each sequencer
+    // iteration will source its key. This only needs to be specified once,
+    // hence its exclusion from the above sequencer load.
+    //
+    scp_key(SCP_REGISTER_INDEX_2);
+
+    // Wait for completion.
+    scp_wait_dma();
+
+    // Check for any unexpected failures.
+    if (scp_check_dma(true) != E_SUCCESS)
+    {
+        return E_SCP_GENERIC;
+    }
+
+    // Sequence loaded successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @brief Loads the SCP instructions for CMAC into sequencer zero.
+ *
+ * Loads sequencer zero with the set of SCP instructions required to compute
+ * the CMAC of a single intermediate block of data.
+ *
+ * The loaded algorithm assumes that key material has already been loaded to
+ * register-index zero and has also been selected via the scp_key()
+ * instruction. It further assumes that the initialization vector, if any, has
+ * been loaded to register-index one and that register-index two is available
+ * for use as intermediate storage.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ *
+ * @retval E_SUCCESS                if instructions were loaded successfully.
+ * @retval E_SCP_GENERIC            if an unexpected error occurred.
+ */
+static error_t
+s_scp_Load_Cmac_Sequence(void)
+{
+    // Prepare to write three instructions to sequencer zero.
+    scp_load_trace0(3U);
+    {
+        // Load the next block of the message to process.
+        scp_push(SCP_REGISTER_INDEX_2);
+
+        // XOR with the current MAC value (or IV).
+        scp_xor(SCP_REGISTER_INDEX_1, SCP_REGISTER_INDEX_2);
+
+        // Encrypt to obtain the new MAC value.
+        scp_encrypt(SCP_REGISTER_INDEX_2, SCP_REGISTER_INDEX_1);
+    }
+
+    // Wait for completion.
+    scp_wait_dma();
+
+    // Check for any unexpected failures.
+    if (scp_check_dma(true) != E_SUCCESS)
+    {
+        return E_SCP_GENERIC;
+    }
+
+    // Sequence loaded successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @brief Completes a CMAC computation by handling a message's final block.
+ *
+ * Generates the correct CMAC subkey per the value of b_padded and uses it to
+ * tweak the first SCP_BLOCK_SIZE bytes from final_pa before computing the final
+ * CMAC result from it and the intermediate value in SCP register-index one.
+ *
+ * Assumes that key material has already been loaded to register-index zero and
+ * has also been selected via the scp_key() instruction. Further assumes that
+ * register-indices two and three are available for use as intermediate storage.
+ *
+ * Note that the caller is responsible for validating final_pa before passing it
+ * to this function, and is also responsible for clearing the intermediate
+ * registers when finished.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Register-index one must be fetchable.
+ *
+ * @param[in]  final_pa     The physical address of the final block of the
+ *                          input message. Must be aligned to and contain at
+ *                          least SCP_BLOCK_SIZE bytes. Supports IMEM and DMEM
+ *                          locations only.
+ *
+ * @param[in]  b_padded     A boolean value indicating whether the input
+ *                          message has been padded per the CMAC specification.
+ *
+ * @retval E_SUCCESS                    if CMAC was completed successfully.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_FAULT                      if an IO-PMP fault was detected.
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ */
+static error_t
+s_scp_Complete_Cmac
+(
+    uintptr_t   final_pa,
+    bool        b_padded
+)
+{
+    error_t status;
+
+    // Load the final message block.
+    status = scp_pvt_Load_Buffer(final_pa, SCP_REGISTER_INDEX_2);
+    if (status != E_SUCCESS)
+    {
+        return status;
+    }
+
+    // Ensure that register-index three is zero.
+    status = scp_pvt_Clear_Reg(SCP_REGISTER_INDEX_3);
+    if (status != E_SUCCESS)
+    {
+        return status;
+    }
+
+    // Generate the first CMAC subkey.
+    scp_encrypt(SCP_REGISTER_INDEX_3, SCP_REGISTER_INDEX_3);
+    scp_cmac_sk(SCP_REGISTER_INDEX_3, SCP_REGISTER_INDEX_3);
+
+    // Generate the second subkey if needed.
+    if (b_padded)
+    {
+        scp_cmac_sk(SCP_REGISTER_INDEX_3, SCP_REGISTER_INDEX_3);
+    }
+
+    // Tweak the final message block using the relevant subkey.
+    scp_xor(SCP_REGISTER_INDEX_3, SCP_REGISTER_INDEX_2);
+
+    // XOR with the current MAC value.
+    scp_xor(SCP_REGISTER_INDEX_1, SCP_REGISTER_INDEX_2);
+
+    // Encrypt to obtain the final MAC value.
+    scp_encrypt(SCP_REGISTER_INDEX_2, SCP_REGISTER_INDEX_1);
+
+    // Wait for completion.
+    scp_wait_dma();
+
+    // Check for any unexpected failures.
+    if (scp_check_dma(true) != E_SUCCESS)
+    {
+        return E_SCP_GENERIC;
+    }
+
+    // Done.
+    return status;
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/scp/scp_direct.c b/spe-freertos-bsp/fsp/source/drivers/scp/scp_direct.c
new file mode 100644
index 0000000..e4ce8b5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/scp/scp_direct.c
@@ -0,0 +1,516 @@
+/**
+ * @file        scp_direct.c
+ * @brief       Low-level SCP primitives.
+ *
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !NVRISCV_FEATURE_SCP
+#error "Attempting to build scp_direct.c but the SCP driver is disabled!"
+#endif // NVRISCV_FEATURE_SCP
+
+
+/* Compiler headers */
+#include <stdbool.h>                    // for bool, true
+#include <stdint.h>                     // for uint32_t, uintptr_t, etc.
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for HEADER_CHECK
+#include <misc/nvmisc_drf.h>            // for DRF macros
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/io.h>                     // for local_read, local_write
+#include <cpu/iopmp.h>                  // for iopmp_has_error
+#include <error/common-errors.h>        // for error_t, common error codes
+#include <fbdma/memutils.h>             // for memutils_riscv_pa_to_target_offset
+#include <misc/macros.h>                // for INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <scp/scp-errors.h>             // for SCP error codes
+#include <scp/scp_common.h>             // for scp_register_index_t
+#include <scp/scp_direct.h>             // for scp_transfer_size_t, etc.
+#include <scp/scp_private.h>            // for scp_pvt_*
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The HEADER_CHECK macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+HEADER_CHECK(FSP__MISC__NVMISC_DRF_H)
+HEADER_CHECK(FSP__CPU__IO_H)
+HEADER_CHECK(FSP__CPU__IOPMP_H)
+HEADER_CHECK(FSP__ERROR__COMMON_ERRORS_H)
+HEADER_CHECK(FSP__FBDMA__MEMUTILS_H)
+HEADER_CHECK(FSP__MISC__MACROS_H)
+HEADER_CHECK(FSP__SCP__SCP_ERRORS_H)
+HEADER_CHECK(FSP__SCP__SCP_COMMON_H)
+HEADER_CHECK(FSP__SCP__SCP_DIRECT_H)
+HEADER_CHECK(FSP__SCP__SCP_PRIVATE_H)
+
+
+/**
+ * @brief Initiates a single SCPDMA transfer.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ *
+ * @param[inout] offset    The IMEM/DMEM offset for the transfer. Ignored for
+ *                         shortcut transfers (32-bit).
+ *
+ * @param[in]    suppress  Whether to avoid issuing a corresponding push/fetch
+ *                         instruction for this transfer (ENABLE / DISABLE).
+ *
+ * @param[in]    shortcut  Whether to enable the shortcut path for direct
+ *                         transfer to FB/SYSMEM. Only valid for writes (ENABLE
+ *                         / DISABLE).
+ *
+ * @param[in]    imem      Whether to target IMEM rather than DMEM. Ignored for
+ *                         shortcut transfers (TRUE / FALSE).
+ *
+ * @param[in]    write     Indicates transfer direction. Here "write" means a
+ *                         transfer from memory to the SCP unit (TRUE / FALSE).
+ *
+ * @param[in]    size      The number of bytes to transfer. Must be a valid
+ *                         scp_transfer_size_t value, or zero for non-suppressed
+ *                         transfers.
+ *
+ * @param[in]    gpr       The SCP register to target in the corresponding push
+ *                         /fetch instruction. Must be a valid
+ *                         scp_register_index_t value, or zero for suppressed
+ *                         transfers.
+ */
+#define SCP_TRANSFER(offset, suppress, shortcut, imem, write, size, gpr) do { \
+    INLINE_RFD(CERTC, DEVIATE, INT31_C, "Bug: TODO, DR: TODO - NVRISCV_RISCV_AMAP_IMEM/DMEM_END < UINT32_MAX") \
+    uint32_t local_offset = (uint32_t) offset;                             \
+    local_write(NV_PRGNLCL_RISCV_SCPDMATRFMOFFS,                            \
+        DRF_NUM(_PRGNLCL_RISCV, _SCPDMATRFMOFFS, _OFFS, local_offset));    \
+                                                                           \
+    local_write(NV_PRGNLCL_RISCV_SCPDMATRFCMD,                              \
+        DRF_DEF(_PRGNLCL_RISCV, _SCPDMATRFCMD, _SUPPRESS, _##suppress)  |  \
+        DRF_DEF(_PRGNLCL_RISCV, _SCPDMATRFCMD, _SHORTCUT, _##shortcut)  |  \
+        DRF_DEF(_PRGNLCL_RISCV, _SCPDMATRFCMD, _IMEM,     _##imem    )  |  \
+        DRF_DEF(_PRGNLCL_RISCV, _SCPDMATRFCMD, _WRITE,    _##write   )  |  \
+        DRF_NUM(_PRGNLCL_RISCV, _SCPDMATRFCMD, _SIZE,     size       )  |  \
+        DRF_NUM(_PRGNLCL_RISCV, _SCPDMATRFCMD, _GPR,      gpr        )  |  \
+        DRF_DEF(_PRGNLCL_RISCV, _SCPDMATRFCMD, _CCI_EX,   _SCPDMA    )     \
+    );                                                                     \
+} while(0)
+
+
+/**
+ * @brief Tracks load/store failures for scp_check_dma() to report later.
+ */
+static error_t s_transfer_status = E_SUCCESS;
+
+
+//
+// Prototypes for local helper functions.
+// See definitions for details.
+//
+static inline error_t   s_scp_Get_Error(void);
+static inline void      s_scp_Clear_Error(void);
+
+
+/**
+ * @copydoc scp_Start_Direct
+ */
+error_t
+scp_Start_Direct(void)
+{
+    // Verify driver state before proceeding further.
+    if (!g_scp_state.b_initialized)
+    {
+        return E_SCP_NOT_READY;
+    }
+
+    // Skip entry if already in direct mode.
+    if (g_scp_state.b_direct_mode_active)
+    {
+        return E_SCP_NOTHING_TO_DO;
+    }
+
+    //
+    // The high-level SCP interfaces are written such that the SCP GPRs should
+    // already be cleared and unlocked, the sequencers should already be empty,
+    // any SCPDMA errors should already be handled, and the SCP unit should
+    // already be idle before this function is even called. Therefore, we have
+    // nothing to do here besides updating the internal driver state.
+    //
+    g_scp_state.b_direct_mode_active = true;
+
+    // Direct mode was started successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @copydoc scp_Stop_Direct
+ */
+error_t
+scp_Stop_Direct(void)
+{
+    // Verify driver state before proceeding further.
+    if (!g_scp_state.b_initialized)
+    {
+        return E_SCP_NOT_READY;
+    }
+
+    // Skip exit if not in direct mode in the first place.
+    if (!g_scp_state.b_direct_mode_active)
+    {
+        return E_SCP_NOTHING_TO_DO;
+    }
+
+    // Verify access to lockable SCP registers/fields.
+    if (scp_pvt_Is_Access_Restricted())
+    {
+        return E_SCP_INVALID_LOCK_STATE;
+    }
+
+    //
+    // Wait for idle before issuing the pipe reset. Otherwise, we may end up
+    // corrupting the result of some prior operation that's still pending.
+    //
+    scp_wait_dma();
+
+    //
+    // Do a full pipe reset. This ensures that the SCP unit isn't in some weird
+    // state (e.g. stalled, in the middle of a sequencer load, etc.).
+    //
+    scp_pvt_Reset_Pipeline();
+
+    //
+    // Clear the sequencers to prevent anything accidentally carrying forward
+    // into higher-level operations.
+    //
+    scp_pvt_Reset_Sequencers();
+
+    //
+    // Clear any pending SCPDMA errors the application may have neglected to
+    // deal with (or else we might get false failures from scp_pvt_Clear_All()).
+    // Ignore result explicitly to avoid coverity errors.
+    //
+    (void) scp_check_dma(true);
+
+    // Clear and unlock the GPRs.
+    error_t clear_status = scp_pvt_Clear_All();
+    if (clear_status != E_SUCCESS)
+    {
+        return clear_status;
+    }
+
+    // Update internal state.
+    g_scp_state.b_direct_mode_active = false;
+
+    // Direct mode was stopped successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @copydoc scp_load
+ */
+void
+scp_load
+(
+    uintptr_t               source_pa,
+    scp_register_index_t    reg_index
+)
+{
+    riscv_mem_target_t  mem_target;
+    uint64_t            mem_offset;
+
+    //
+    // Determine which memory region source_pa points to and obtain the offset
+    // of source_pa into said region.
+    //
+    if (memutils_riscv_pa_to_target_offset(source_pa, &mem_target, &mem_offset)
+            != E_SUCCESS)
+    {
+        // Track for scp_check_dma() to report later.
+        s_transfer_status = E_SCP_INVALID_BASE;
+    }
+    // Issue a transfer from IMEM.
+    else if (mem_target == RISCV_MEM_TARGET_IMEM)
+    {
+        // We assume that IMEM does not exceed 2^32 bytes in size.
+        SCP_TRANSFER(mem_offset, DISABLE, DISABLE, TRUE, TRUE, 0U, reg_index);
+    }
+    // Issue a transfer from DMEM.
+    else if (mem_target == RISCV_MEM_TARGET_DMEM)
+    {
+        // We assume that DMEM does not exceed 2^32 bytes in size.
+        SCP_TRANSFER(mem_offset, DISABLE, DISABLE, FALSE, TRUE, 0U, reg_index);
+    }
+    // Invalid memory region.
+    else
+    {
+        // Track for scp_check_dma() to report later.
+        s_transfer_status = E_SCP_INVALID_BASE;
+    }
+}
+
+/**
+ * @copydoc scp_store
+ */
+void
+scp_store
+(
+    scp_register_index_t    reg_index,
+    uintptr_t               dest_pa
+)
+{
+    riscv_mem_target_t  mem_target;
+    uint64_t            mem_offset;
+
+    //
+    // Determine which memory region dest_pa points to and obtain the offset
+    // of dest_pa into said region.
+    //
+    if (memutils_riscv_pa_to_target_offset(dest_pa, &mem_target, &mem_offset) !=
+        E_SUCCESS)
+    {
+        // Track for scp_check_dma() to report later.
+        s_transfer_status = E_SCP_INVALID_BASE;
+    }
+    // Issue a transfer to IMEM.
+    else if (mem_target == RISCV_MEM_TARGET_IMEM)
+    {
+        // We assume that IMEM does not exceed 2^32 bytes in size.
+        SCP_TRANSFER(mem_offset, DISABLE, DISABLE, TRUE, FALSE, 0U, reg_index);
+    }
+    // Issue a transfer to DMEM.
+    else if (mem_target == RISCV_MEM_TARGET_DMEM)
+    {
+        // We assume that DMEM does not exceed 2^32 bytes in size.
+        SCP_TRANSFER(mem_offset, DISABLE, DISABLE, FALSE, FALSE, 0U, reg_index);
+    }
+    // Issue a transfer to external memory (shortcut).
+    else if ((mem_target == RISCV_MEM_TARGET_FBGPA) ||
+             (mem_target == RISCV_MEM_TARGET_SYSGPA))
+    {
+        SCP_TRANSFER(0U, DISABLE, ENABLE, FALSE, FALSE, 0U, reg_index);
+    }
+    // Invalid memory region.
+    else
+    {
+        // Track for scp_check_dma() to report later.
+        s_transfer_status = E_SCP_INVALID_BASE;
+    }
+}
+
+/**
+ * @copydoc scp_queue_read
+ */
+void
+scp_queue_read
+(
+    uintptr_t           source_pa,
+    scp_transfer_size_t size
+)
+{
+    riscv_mem_target_t  mem_target;
+    uint64_t            mem_offset;
+
+    //
+    // Determine which memory region source_pa points to and obtain the offset
+    // of source_pa into said region.
+    //
+    if (memutils_riscv_pa_to_target_offset(source_pa, &mem_target, &mem_offset)
+            != E_SUCCESS)
+    {
+        // Track for scp_check_dma() to report later.
+        s_transfer_status = E_SCP_INVALID_BASE;
+    }
+    // Queue a transfer from IMEM.
+    else if (mem_target == RISCV_MEM_TARGET_IMEM)
+    {
+        // We assume that IMEM does not exceed 2^32 bytes in size.
+        SCP_TRANSFER(mem_offset, ENABLE, DISABLE, TRUE, TRUE, size, 0U);
+    }
+    // Queue a transfer from DMEM.
+    else if (mem_target == RISCV_MEM_TARGET_DMEM)
+    {
+        // We assume that DMEM does not exceed 2^32 bytes in size.
+        SCP_TRANSFER(mem_offset, ENABLE, DISABLE, FALSE, TRUE, size, 0U);
+    }
+    // Invalid memory region.
+    else
+    {
+        // Track for scp_check_dma() to report later.
+        s_transfer_status = E_SCP_INVALID_BASE;
+    }
+}
+
+/**
+ * @copydoc scp_queue_write
+ */
+void
+scp_queue_write
+(
+    uintptr_t           dest_pa,
+    scp_transfer_size_t size
+)
+{
+    riscv_mem_target_t  mem_target;
+    uint64_t            mem_offset;
+
+    //
+    // Determine which memory region dest_pa points to and obtain the offset
+    // of dest_pa into said region.
+    //
+    if (memutils_riscv_pa_to_target_offset(dest_pa, &mem_target, &mem_offset) !=
+        E_SUCCESS)
+    {
+        // Track for scp_check_dma() to report later.
+        s_transfer_status = E_SCP_INVALID_BASE;
+    }
+    // Queue a transfer to IMEM.
+    else if (mem_target == RISCV_MEM_TARGET_IMEM)
+    {
+        // We assume that IMEM does not exceed 2^32 bytes in size.
+        SCP_TRANSFER(mem_offset, ENABLE, DISABLE, TRUE, FALSE, size, 0U);
+    }
+    // Queue a transfer to DMEM.
+    else if (mem_target == RISCV_MEM_TARGET_DMEM)
+    {
+        // We assume that DMEM does not exceed 2^32 bytes in size.
+        SCP_TRANSFER(mem_offset, ENABLE, DISABLE, FALSE, FALSE, size, 0U);
+    }
+    // Queue a transfer to external memory (shortcut).
+    else if ((mem_target == RISCV_MEM_TARGET_FBGPA) ||
+             (mem_target == RISCV_MEM_TARGET_SYSGPA))
+    {
+        SCP_TRANSFER(0U, ENABLE, ENABLE, FALSE, FALSE, size, 0U);
+    }
+    // Invalid memory region.
+    else
+    {
+        // Track for scp_check_dma() to report later.
+        s_transfer_status = E_SCP_INVALID_BASE;
+    }
+}
+
+/**
+ * @copydoc scp_check_dma
+ */
+error_t
+scp_check_dma
+(
+    bool b_clear
+)
+{
+    error_t final_status;
+
+    // Give first precedence to errors cached from prior load/store operations.
+    if (s_transfer_status != E_SUCCESS)
+    {
+        final_status = s_transfer_status;
+    }
+    else
+    {
+        // Next, check for errors flagged by the SCPDMA hardware.
+        final_status = s_scp_Get_Error();
+
+        // Finally, check for general IO-PMP errors.
+        if ((final_status == E_SUCCESS) && iopmp_has_error())
+        {
+            final_status = E_FAULT;
+        }
+    }
+
+    //
+    // Clear any errors if requested. Note that we don't clear IO-PMP errors as
+    // the user may want to investigate them in more detail.
+    //
+    if (b_clear)
+    {
+        s_transfer_status = E_SUCCESS;
+        s_scp_Clear_Error();
+    }
+
+    return final_status;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Checks for and returns any pending SCPDMA errors.
+ *
+ * @pre The SCPDMA hardware must be idle.
+ *
+ * @retval E_SUCCESS                if no errors were reported.
+ *
+ * @retval E_SCP_INVALID_ADDRESS    if an SCPDMA transfer was initiated with an
+ *                                  offset that is not aligned to its size.
+ *
+ * @retval E_PERM                   if a CCI secret instruction was initiated
+ *                                  with a hardware-secret index that the
+ *                                  application does not have permission to
+ *                                  use.
+ */
+static inline error_t
+s_scp_Get_Error(void)
+{
+    const uint32_t reg = local_read(NV_PRGNLCL_RISCV_SCPDMAPOLL);
+
+    // Check for bad alignment.
+    if (FLD_TEST_DRF(_PRGNLCL_RISCV, _SCPDMAPOLL, _ERROR_CODE,
+        _NOT_SIZE_ALIGNED, reg))
+    {
+        return E_SCP_INVALID_ADDRESS;
+    }
+    // Check for bad secret index.
+    else if (FLD_TEST_DRF(_PRGNLCL_RISCV, _SCPDMAPOLL, _ERROR_CODE,
+        _SECRET_NOT_ALLOWED, reg))
+    {
+        return E_PERM;
+    }
+    // No errors reported.
+    else
+    {
+        return E_SUCCESS;
+    }
+}
+
+/**
+ * @brief Clears any pending SCPDMA errors.
+ *
+ * @pre The SCPDMA hardware must be idle.
+ */
+static inline void
+s_scp_Clear_Error(void)
+{
+    local_write(NV_PRGNLCL_RISCV_SCPDMAPOLL,
+        FLD_SET_DRF_NUM(_PRGNLCL_RISCV, _SCPDMAPOLL, _ERROR_CLR, 1U,
+            local_read(NV_PRGNLCL_RISCV_SCPDMAPOLL)));
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/scp/scp_general.c b/spe-freertos-bsp/fsp/source/drivers/scp/scp_general.c
new file mode 100644
index 0000000..8d9c30b
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/scp/scp_general.c
@@ -0,0 +1,929 @@
+/**
+ * @file        scp_general.c
+ * @brief       General SCP operations.
+ *
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !NVRISCV_FEATURE_SCP
+#error "Attempting to build scp_general.c but the SCP driver is disabled!"
+#endif // NVRISCV_FEATURE_SCP
+
+
+/* Compiler headers */
+#include <stdbool.h>                    // for bool, true, false
+#include <stdint.h>                     // for uint8_t, uint32_t, etc.
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for HEADER_CHECK
+#include <misc/nvmisc_drf.h>            // for DRF macros
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/devicemap.h>              // for DEVICEMAP_HAS_ACCESS
+#include <cpu/io.h>                     // for local_read, local_write
+#include <cpu/iopmp.h>                  // for IOPMP_IS_CAPTURE_ENABLED
+#include <error/common-errors.h>        // for error_t, common error codes
+#include <misc/macros.h>                // for INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <scp/scp-errors.h>             // for SCP error codes
+#include <scp/scp_common.h>             // for scp_register_index_t
+#include <scp/scp_direct.h>             // for SCP primitives
+#include <scp/scp_general.h>            // for scp_init_flag_t
+#include <scp/scp_private.h>            // for scp_pvt_*
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The HEADER_CHECK macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+HEADER_CHECK(FSP__MISC__NVMISC_DRF_H)
+HEADER_CHECK(FSP__CPU__DEVICEMAP_H)
+HEADER_CHECK(FSP__CPU__IO_H)
+HEADER_CHECK(FSP__CPU__IOPMP_H)
+HEADER_CHECK(FSP__ERROR__COMMON_ERRORS_H)
+HEADER_CHECK(FSP__MISC__MACROS_H)
+HEADER_CHECK(FSP__SCP__SCP_ERRORS_H)
+HEADER_CHECK(FSP__SCP__SCP_COMMON_H)
+HEADER_CHECK(FSP__SCP__SCP_DIRECT_H)
+HEADER_CHECK(FSP__SCP__SCP_GENERAL_H)
+HEADER_CHECK(FSP__SCP__SCP_PRIVATE_H)
+
+
+//
+// Prototypes for local helper functions.
+// See definitions for details.
+//
+static error_t     s_scp_Forget_Signature(void);
+static error_t     s_scp_Recover_Insecure(void);
+
+static bool        s_scp_Has_Interrupt(void);
+
+static inline bool s_scp_Is_Active(void);
+static inline bool s_scp_Is_Present(void);
+static inline bool s_scp_Is_Secure_Capable(void);
+
+static inline void s_scp_Clear_Interrupts(void);
+static inline void s_scp_Disable_Interrupts(void);
+static inline void s_scp_Enable_Interrupts(void);
+
+static inline void s_scp_Disable_Processing(void);
+static inline void s_scp_Enable_Processing(void);
+
+static inline void s_scp_Reset_Configuration(void);
+static inline void s_scp_Reset_Controls(void);
+static inline void s_scp_Reset_Secret_63(void);
+static inline void s_scp_Reset_State(void);
+
+
+/**
+ * @copydoc scp_Init
+ */
+error_t
+scp_Init
+(
+    scp_init_flag_t flags
+)
+{
+    error_t status;
+
+    //
+    // Reset the internal driver state before doing anything else. This
+    // prevents, e.g., stale state from some other partition carrying over into
+    // this one, even in the event of an early-exit later in this function.
+    //
+    s_scp_Reset_State();
+
+    // Verify that the host Peregrine actually contains an SCP unit.
+    if (!s_scp_Is_Present())
+    {
+        return E_NOTSUPPORTED;
+    }
+
+    //
+    // Check that we have sufficient access rights to the necessary device-map
+    // groups. We do this just as a courtesy check at init and not in every
+    // interface.
+    //
+    if (!DEVICEMAP_HAS_ACCESS(MMODE, SCP,   READ)  ||
+        !DEVICEMAP_HAS_ACCESS(MMODE, SCP,   WRITE) ||
+        !DEVICEMAP_HAS_ACCESS(MMODE, IOPMP, READ))
+    {
+        return E_PERM;
+    }
+
+#if NVRISCV_CONFIG_CPU_MODE != 3
+    // Not operating in M-mode so check S/U as well.
+    if (!DEVICEMAP_HAS_ACCESS(SUBMMODE, SCP,   READ)  ||
+        !DEVICEMAP_HAS_ACCESS(SUBMMODE, SCP,   WRITE) ||
+        !DEVICEMAP_HAS_ACCESS(SUBMMODE, IOPMP, READ))
+    {
+        return E_PERM;
+    }
+#endif // NVRISCV_CONFIG_CPU_MODE != 3
+
+    // Verify that IO-PMP error-capture is enabled for CPDMA transfers.
+    if (!IOPMP_IS_CAPTURE_ENABLED(CPDMA))
+    {
+        return E_INVALID_STATE;
+    }
+
+    // Verify that SCP lockdown is correctly configured.
+    if (s_scp_Is_Secure_Capable() != scp_pvt_Is_Lockdown_Enabled())
+    {
+        return E_SCP_INVALID_LOCK_STATE;
+    }
+
+    // Verify access to lockable SCP registers/fields.
+    if (scp_pvt_Is_Access_Restricted())
+    {
+        return E_SCP_INVALID_LOCK_STATE;
+    }
+
+    //
+    // Ensure the SCP unit is idle before trying to reset it. Otherwise, we
+    // may corrupt the result of some prior operation that's still pending.
+    //
+    if (scp_poll_dma())
+    {
+        return E_BUSY;
+    }
+
+    //
+    // Hardware state has been verified. Check that the configuration flags
+    // are valid as well before initiating any changes.
+    //
+    if (flags != SCP_INIT_FLAG_DEFAULT)
+    {
+        // No other flags are supported currently.
+        return E_SCP_INVALID_FLAGS;
+    }
+
+    //
+    // Concurrent SCP usage is not supported, so the unit is expected to remain
+    // idle throughout initialization regardless, but disable processing anyway
+    // as a precautionary measure.
+    //
+    s_scp_Disable_Processing();
+
+    // Disable any interrupts that could cause us to stall later.
+    s_scp_Disable_Interrupts();
+
+    //
+    // Clear any already-pending interrupts or SCPDMA errors so we can check
+    // later that we didn't unexpectedly trigger any new ones ourselves.
+    //
+    s_scp_Clear_Interrupts();
+    (void) scp_check_dma(true);
+
+    //
+    // Perform a pipe reset and clear the sequencers. We also disable RNG at
+    // this point (applications can explicitly re-enable later if needed).
+    //
+    s_scp_Reset_Controls();
+
+    //
+    // Reset the carry-chain, endianness, stall-timeout, etc. to their
+    // default values.
+    //
+    s_scp_Reset_Configuration();
+
+    //
+    // Re-enable processing now that configuration is complete. Needs to be
+    // done before attempting to clear registers or we'll hang.
+    //
+    s_scp_Enable_Processing();
+
+    if (!scp_pvt_Is_Secure())
+    {
+        //
+        // Ensure we have fetchable access to the general-purpose registers
+        // before trying to clear them. Secure code can do this via the
+        // scp_secret() primitive (which scp_pvt_Zero_All() issues automatically
+        // if needed) but insecure code requires the alternative approach
+        // invoked here.
+        //
+        // Note that any subsequent driver code that causes these permissions
+        // to be revoked again will also make sure to restore them before
+        // returning, thus bypassing the need for this special procedure
+        // beyond first-time initialization.
+        //
+        // In the event that one or more of the general-purpose registers lack
+        // insecure-writable access (Wi), we will have no means of recovering
+        // access whatsoever and will simply error out when we catch the
+        // ensuing write-violation interrupt below.
+        //
+        status = s_scp_Recover_Insecure();
+        if (status != E_SUCCESS)
+        {
+            return status;
+        }
+    }
+
+    // Clear the contents of all general-purpose registers.
+    status = scp_pvt_Zero_All();
+    if (status != E_SUCCESS)
+    {
+        return status;
+    }
+
+    if (scp_pvt_Is_Secure())
+    {
+        //
+        // Relax the ACLs of the general-purpose registers so insecure code is
+        // not locked out later on. It is critical that we only do this if
+        // scp_pvt_Zero_All() succeeded entirely, hence the interrupt check.
+        //
+        if (!s_scp_Has_Interrupt())
+        {
+            status = scp_pvt_Unlock_All();
+            if (status != E_SUCCESS)
+            {
+                return status;
+            }
+        }
+
+        //
+        // Invalidate the engine's signature/hash. This will generate an
+        // interrupt if the signature register is already invalid, hence doing
+        // it while they're still disabled.
+        //
+        // Note that the RISC-V BootROM normally performs this step itself but
+        // we repeat it here anyway as a defense-in-depth measure.
+        //
+        status = s_scp_Forget_Signature();
+        if (status != E_SUCCESS)
+        {
+            return status;
+        }
+    }
+
+    //
+    // Check for any unexpected interrupts. There are very few realistic
+    // scenarios in which we would ever hit this condition, so we just return
+    // a generic error code here without investigating further.
+    //
+    if (s_scp_Has_Interrupt())
+    {
+        return E_SCP_GENERIC;
+    }
+
+    //
+    // Clear any non-fatal interrupts we may have triggered and then enable a
+    // reasonable subset of them for the application.
+    //
+    s_scp_Clear_Interrupts();
+    s_scp_Enable_Interrupts();
+
+    // Update internal state to reflect completed initialization.
+    g_scp_state.b_initialized = true;
+
+    // Initialization was successful.
+    return E_SUCCESS;
+}
+
+/**
+ * @copydoc scp_Shutdown
+ */
+error_t
+scp_Shutdown(void)
+{
+    error_t current_status, final_status = E_SUCCESS;
+
+    // Skip shutdown if already done.
+    if (g_scp_state.b_shutdown)
+    {
+        return E_SCP_NOTHING_TO_DO;
+    }
+
+    // Verify driver state before proceeding further.
+    if (!g_scp_state.b_initialized)
+    {
+        return E_SCP_NOT_READY;
+    }
+
+    // Verify access to lockable SCP registers/fields.
+    if (scp_pvt_Is_Access_Restricted())
+    {
+        return E_SCP_INVALID_LOCK_STATE;
+    }
+
+    //
+    // Ensure the SCP unit is idle before trying to shut it down. Otherwise,
+    // we may corrupt the result of some prior operation that's still pending.
+    //
+    if (s_scp_Is_Active())
+    {
+        return E_BUSY;
+    }
+
+    // Disable any interrupts that could cause us to stall later.
+    s_scp_Disable_Interrupts();
+
+    //
+    // Clear any already-pending interrupts or SCPDMA errors so we can check
+    // later that we didn't unexpectedly trigger any new ones.
+    //
+    s_scp_Clear_Interrupts();
+    (void) scp_check_dma(true);
+
+    //
+    // Perform a pipe reset and clear the sequencers. It's important to do this
+    // before attempting to clear the registers in case the application forgot
+    // to properly exit direct mode, or encountered a stall. We also disable
+    // RNG at this point.
+    //
+    s_scp_Reset_Controls();
+
+    //
+    // Ensure processing is enabled in case, e.g., the application is calling
+    // this function in response to a fatal error.
+    //
+    s_scp_Enable_Processing();
+
+    if (!scp_pvt_Is_Secure())
+    {
+        //
+        // Try to ensure that we have fetchable access to the general-purpose
+        // registers before attempting to clear them. scp_pvt_Zero_All() will
+        // handle this automatically for secure contexts, but insecure contexts
+        // require the alternative procedure used here.
+        //
+        // Realistically, this should only be necessary if the application has
+        // been misusing direct mode, but we do it anyway to maximize our
+        // chances of a clean shutdown.
+        //
+        current_status = s_scp_Recover_Insecure();
+        if (final_status == E_SUCCESS)
+        {
+            final_status = current_status;
+        }
+    }
+
+    // Clear the contents of all general-purpose registers.
+    current_status = scp_pvt_Zero_All();
+    if (final_status == E_SUCCESS)
+    {
+        final_status = current_status;
+    }
+
+    //
+    // Relax the ACLs of the general-purpose registers so insecure code can
+    // freely use them afterwards. It is critical that we only do this if
+    // scp_pvt_Zero_All() succeeded entirely, hence the extra check.
+    //
+    if (scp_pvt_Is_Secure() && !s_scp_Has_Interrupt() &&
+        (final_status == E_SUCCESS))
+    {
+        final_status = scp_pvt_Unlock_All();
+    }
+
+    //
+    // Check for any unexpected interrupts. There are very few realistic
+    // scenarios in which we would ever hit this condition, so we just return
+    // a generic error code here without investigating further.
+    //
+    if (s_scp_Has_Interrupt() && (final_status == E_SUCCESS))
+    {
+        final_status = E_SCP_GENERIC;
+    }
+
+    // Disable further processing until the SCP unit is needed again.
+    s_scp_Disable_Processing();
+
+    // Clear any interrupts we may have triggered.
+    s_scp_Clear_Interrupts();
+
+    // Reset the source for secret-index 63 (hardware recommendation).
+    s_scp_Reset_Secret_63();
+
+    // Clear internal driver state.
+    s_scp_Reset_State();
+
+    //
+    // Update internal state to reflect completed shutdown. The driver will no
+    // longer be in a usable state by this point, even if some prior operation
+    // failed, so we do this unconditionally.
+    //
+    g_scp_state.b_shutdown = true;
+
+    // Shutdown complete.
+    return final_status;
+}
+
+/**
+ * @copydoc scp_Is_Debug
+ */
+bool
+scp_Is_Debug(void)
+{
+    return !FLD_TEST_DRF(_PRGNLCL_SCP, _CTL_STAT, _DEBUG_MODE, _DISABLED,
+                         local_read(NV_PRGNLCL_SCP_CTL_STAT));
+}
+
+/**
+ * @copydoc scp_Clear_Reg
+ */
+error_t
+scp_Clear_Reg
+(
+    scp_register_index_t reg_index
+)
+{
+    // Verify driver state before proceeding further.
+    if (!g_scp_state.b_initialized)
+    {
+        return E_SCP_NOT_READY;
+    }
+
+    // Ensure the provided register index is valid.
+    if (reg_index > SCP_REGISTER_INDEX_7)
+    {
+        return E_SCP_INVALID_INDEX;
+    }
+
+    // Clear the selected register and unlock its associated ACL if needed.
+    return scp_pvt_Clear_Reg(reg_index);
+}
+
+/**
+ * @copydoc scp_Clear_All
+ */
+error_t
+scp_Clear_All(void)
+{
+    // Verify driver state before proceeding further.
+    if (!g_scp_state.b_initialized)
+    {
+        return E_SCP_NOT_READY;
+    }
+
+    // Clear all GPRs and unlock their associated ACLs if needed.
+    return scp_pvt_Clear_All();
+}
+
+/**
+ * @copydoc scp_Configure_Shortcut
+ */
+error_t
+scp_Configure_Shortcut
+(
+    uint8_t dma_index
+)
+{
+    // Verify driver state before proceeding further.
+    if (!g_scp_state.b_initialized)
+    {
+        return E_SCP_NOT_READY;
+    }
+
+    // Invalidate previous setting, if any.
+    g_scp_state.b_shortcut_configured = false;
+
+    // Check that shortcut-DMA support is enabled.
+    if (!NVRISCV_DRIVER_SCP_SHORTCUT_ENABLED)
+    {
+        return E_SCP_FEATURE_NOT_ENABLED;
+    }
+
+    // Ensure the provided DMA index is valid.
+    if (dma_index > DRF_MASK(NV_PRGNLCL_FALCON_DMATRFCMD_CTXDMA))
+    {
+        return E_SCP_INVALID_INDEX;
+    }
+
+    // Update internal state.
+    g_scp_state.b_shortcut_configured = true;
+    g_scp_state.dma_index             = dma_index;
+
+    // Shortcut-DMA path was configured successfully.
+    return E_SUCCESS;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Invalidates the engine's signature/hash.
+ *
+ * Intended as an internal-only convenience wrapper for scp_forget_sig().
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre This function must only be called from secure contexts.
+ *
+ * @retval E_SUCCESS        if signature/hash was invalidated successfully.
+ * @retval E_SCP_GENERIC    if an unexpected error occurred.
+ */
+static error_t
+s_scp_Forget_Signature(void)
+{
+    // Invalidate the engine's signature/hash.
+    scp_forget_sig();
+
+    // Wait for completion.
+    scp_wait_dma();
+
+    // Check for any unexpected failures.
+    if (scp_check_dma(true) != E_SUCCESS)
+    {
+        return E_SCP_GENERIC;
+    }
+
+    // Signature/hash invalidated successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @brief Recovers insecure access to the SCP GPRs.
+ *
+ * Recovers insecure-fetchable and insecure-keyable access to the SCP GPRs.
+ *
+ * Requires that insecure-writable access (Wi) is already present for all
+ * registers. Only intended to be called from insecure contexts.
+ *
+ * Note that this function makes use of the SCP unit's RNG hardware and does
+ * NOT preserve its configuration settings, or the contents of the affected
+ * GPRs.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre SCP lockdown must be disabled.
+ *
+ * @retval E_SUCCESS        if access was recovered successfully.
+ * @retval E_SCP_GENERIC    if an unexpected error occurred.
+ */
+static error_t
+s_scp_Recover_Insecure(void)
+{
+    //
+    // The only way an insecure context can recover access to an SCP GPR
+    // previously locked by a secure context is by loading data of some kind
+    // into it, which will overwrite the GPR's previous contents and reset its
+    // associated ACL to a fully-open state.
+    //
+    // Unfortunately, declaring a temporary buffer to load data from is out of
+    // the question here as we have no means of obtaining said buffer's
+    // physical address in order to initiate an SCPDMA transfer. That leaves
+    // the "rand" instruction as the only other practical means of getting
+    // insecure data into the GPRs.
+    //
+    // Of course, for even this to work, we need to already have insecure-
+    // writable (Wi) access to the target GPRs or we'll trigger a write-
+    // violation interrupt, hence the pre-condition listed in the function
+    // description.
+    //
+    // As of SCP RNG v2.0, the RNG hardware should be usable "out of the box",
+    // so we don't bother with any configuration here (since the actual entropy
+    // of the values we produce is irrelevant).
+    //
+
+    // Ensure that the RNG hardware is enabled.
+    scp_pvt_Enable_Rand();
+
+    //
+    // Load a true-random number into register-index zero. This will
+    // overwrite any (potentially sensitive) prior contents and unlock the
+    // register's associated ACL to a fully-open state.
+    //
+    scp_rand(SCP_REGISTER_INDEX_0);
+
+    //
+    // Copy the true-random number from register-index zero into the remaining
+    // GPRs, thus effectively copying its fully-open ACL to each of them as
+    // well.
+    //
+    scp_mov(SCP_REGISTER_INDEX_0, SCP_REGISTER_INDEX_1);
+    scp_mov(SCP_REGISTER_INDEX_0, SCP_REGISTER_INDEX_2);
+    scp_mov(SCP_REGISTER_INDEX_0, SCP_REGISTER_INDEX_3);
+    scp_mov(SCP_REGISTER_INDEX_0, SCP_REGISTER_INDEX_4);
+    scp_mov(SCP_REGISTER_INDEX_0, SCP_REGISTER_INDEX_5);
+    scp_mov(SCP_REGISTER_INDEX_0, SCP_REGISTER_INDEX_6);
+    scp_mov(SCP_REGISTER_INDEX_0, SCP_REGISTER_INDEX_7);
+
+    // Wait for completion.
+    scp_wait_dma();
+
+    // Disable the RNG hardware.
+    scp_pvt_Disable_Rand();
+
+    // Check for any unexpected failures.
+    if (scp_check_dma(true) != E_SUCCESS)
+    {
+        return E_SCP_GENERIC;
+    }
+
+    // Registers unlocked successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @brief Checks for pending SCP interrupts.
+ *
+ * @retval true  if there are interrupts pending.
+ * @retval false if there are no interrupts pending.
+ *
+ * @note This function only checks for interrupts that would represent
+ *       genuine error conditions in the context of initialization or
+ *       shutdown and ignores all others.
+ */
+static bool
+s_scp_Has_Interrupt(void)
+{
+    uint32_t reg;
+
+    // Read interrupt status.
+    reg = local_read(NV_PRGNLCL_SCP_INTR);
+
+    // ACL violations and security violations are always relevant.
+    if (FLD_TEST_DRF(_PRGNLCL_SCP, _INTR, _ACL_VIO,      _PENDING, reg) ||
+        FLD_TEST_DRF(_PRGNLCL_SCP, _INTR, _SECURITY_VIO, _PENDING, reg))
+    {
+        return true;
+    }
+
+    // Only certain command errors are relevant so investigate further.
+    if (FLD_TEST_DRF(_PRGNLCL_SCP, _INTR, _CMD_ERROR, _PENDING, reg))
+    {
+        // Obtain error details.
+        reg = local_read(NV_PRGNLCL_SCP_CMD_ERROR);
+
+        // Check for relevant errors.
+        if (FLD_TEST_DRF(_PRGNLCL_SCP, _CMD_ERROR, _UNDEFINED,
+                _TRUE, reg) ||
+            FLD_TEST_DRF(_PRGNLCL_SCP, _CMD_ERROR, _SEQ_EMPTY,
+                _TRUE, reg) ||
+            FLD_TEST_DRF(_PRGNLCL_SCP, _CMD_ERROR, _SEQ_OVERFLOW,
+                _TRUE, reg) ||
+            FLD_TEST_DRF(_PRGNLCL_SCP, _CMD_ERROR, _SIG_INSECURE,
+                _TRUE, reg) ||
+            FLD_TEST_DRF(_PRGNLCL_SCP, _CMD_ERROR, _CHMOD_INSECURE,
+                _TRUE, reg) ||
+            FLD_TEST_DRF(_PRGNLCL_SCP, _CMD_ERROR, _SECRET_INSECURE,
+                _TRUE, reg) ||
+            FLD_TEST_DRF(_PRGNLCL_SCP, _CMD_ERROR, _SEQ_INST_WHILE_LOADING,
+                _TRUE, reg))
+        {
+            return true;
+        }
+    }
+
+    // No relevant pending interrupts.
+    return false;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Checks the SCP unit for activity.
+ *
+ * Checks whether the SCP unit is currently active. Does not check for pending
+ * activity (i.e. CCI transfers queued while processing is disabled).
+ *
+ * @retval true  if the SCP unit is busy.
+ * @retval false if the SCP unit is idle.
+ */
+static inline bool
+s_scp_Is_Active(void)
+{
+    return FLD_TEST_DRF(_PRGNLCL_SCP, _STATUS, _SCP_ACTIVE, _TRUE,
+                        local_read(NV_PRGNLCL_SCP_STATUS));
+}
+
+/**
+ * @brief Checks whether the host engine contains an SCP unit.
+ *
+ * @retval true  if the SCP unit is present.
+ * @retval false if the SCP unit is absent.
+ */
+static inline bool
+s_scp_Is_Present(void)
+{
+    return FLD_TEST_DRF(_PRGNLCL_FALCON, _HWCFG2, _SCP, _ENABLE,
+                        local_read(NV_PRGNLCL_FALCON_HWCFG2));
+}
+
+/**
+ * @brief Checks whether the host engine is able to operate in a secure context.
+ *
+ * @retval true  if the host engine is capable of operating in a secure context.
+ * @retval false if the host engine is not capable of operating in a secure
+ *               context.
+ *
+ * @note To check whether the host engine is currently operating in a secure
+ *       context, use scp_pvt_Is_Secure() instead.
+ */
+static inline bool
+s_scp_Is_Secure_Capable(void)
+{
+    return FLD_TEST_DRF64(_RISCV_CSR, _XSPM, _XSECM, _SEC,
+                          csr_read(NV_RISCV_CSR_XSPM));
+}
+
+/**
+ * @brief Clears any pending SCP interrupts.
+ */
+static inline void
+s_scp_Clear_Interrupts(void)
+{
+    // Clear the main interrupt register first.
+    local_write(NV_PRGNLCL_SCP_INTR,
+        DRF_DEF(_PRGNLCL_SCP, _INTR, _RAND_READY,           _RESET) |
+        DRF_DEF(_PRGNLCL_SCP, _INTR, _ACL_VIO,              _RESET) |
+        DRF_DEF(_PRGNLCL_SCP, _INTR, _SECURITY_VIO,         _RESET) |
+        DRF_DEF(_PRGNLCL_SCP, _INTR, _CMD_ERROR,            _RESET) |
+        DRF_DEF(_PRGNLCL_SCP, _INTR, _STEP,                 _RESET) |
+        DRF_DEF(_PRGNLCL_SCP, _INTR, _RNDHOLDOFF_REQUESTED, _RESET) |
+        DRF_DEF(_PRGNLCL_SCP, _INTR, _STALL_TIMEOUT,        _RESET));
+
+    // Clear any ACL violations.
+    local_write(NV_PRGNLCL_SCP_ACL_VIO,
+        DRF_DEF(_PRGNLCL_SCP, _ACL_VIO, _CHMOD_RELAX_VIO, _CLEAR) |
+        DRF_DEF(_PRGNLCL_SCP, _ACL_VIO, _FETCH_VIO,       _CLEAR) |
+        DRF_DEF(_PRGNLCL_SCP, _ACL_VIO, _WR_VIO,          _CLEAR));
+
+    // Can't clear security violations.
+
+    // Clear any command errors.
+    local_write(NV_PRGNLCL_SCP_CMD_ERROR,
+        DRF_DEF(_PRGNLCL_SCP, _CMD_ERROR, _UNDEFINED,              _CLEAR) |
+        DRF_DEF(_PRGNLCL_SCP, _CMD_ERROR, _SEQ_EMPTY,              _CLEAR) |
+        DRF_DEF(_PRGNLCL_SCP, _CMD_ERROR, _SEQ_OVERFLOW,           _CLEAR) |
+        DRF_DEF(_PRGNLCL_SCP, _CMD_ERROR, _SEQ_INST_WHILE_LOADING, _CLEAR) |
+        DRF_DEF(_PRGNLCL_SCP, _CMD_ERROR, _SIG_INSECURE,           _CLEAR) |
+        DRF_DEF(_PRGNLCL_SCP, _CMD_ERROR, _SIG_INVALID,            _CLEAR) |
+        DRF_DEF(_PRGNLCL_SCP, _CMD_ERROR, _CHMOD_INSECURE,         _CLEAR) |
+        DRF_DEF(_PRGNLCL_SCP, _CMD_ERROR, _SECRET_INSECURE,        _CLEAR));
+}
+
+/**
+ * @brief Disables all SCP interrupts.
+ */
+static inline void
+s_scp_Disable_Interrupts(void)
+{
+    // Disable all interrupts.
+    local_write(NV_PRGNLCL_SCP_INTR_EN,
+        DRF_DEF(_PRGNLCL_SCP, _INTR_EN, _RAND_READY,            _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _INTR_EN, _ACL_VIO,               _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _INTR_EN, _SECURITY_VIO,          _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _INTR_EN, _CMD_ERROR,             _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _INTR_EN, _STEP,                  _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _INTR_EN, _RNDHOLDOFF_REQUESTED,  _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _INTR_EN, _STALL_TIMEOUT,         _DISABLED));
+}
+
+/**
+ * @brief Enables a critical subset of SCP interrupts.
+ */
+static inline void
+s_scp_Enable_Interrupts(void)
+{
+    // Enable only critical interrupts that shouldn't be ignored.
+    local_write(NV_PRGNLCL_SCP_INTR_EN,
+        DRF_DEF(_PRGNLCL_SCP, _INTR_EN, _RAND_READY,            _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _INTR_EN, _ACL_VIO,               _ENABLED)  |
+        DRF_DEF(_PRGNLCL_SCP, _INTR_EN, _SECURITY_VIO,          _ENABLED)  |
+        DRF_DEF(_PRGNLCL_SCP, _INTR_EN, _CMD_ERROR,             _ENABLED)  |
+        DRF_DEF(_PRGNLCL_SCP, _INTR_EN, _STEP,                  _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _INTR_EN, _RNDHOLDOFF_REQUESTED,  _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _INTR_EN, _STALL_TIMEOUT,         _DISABLED));
+}
+
+/**
+ * @brief Disables all processing of SCP commands.
+ */
+static inline void
+s_scp_Disable_Processing(void)
+{
+    local_write(NV_PRGNLCL_SCP_CTL0,
+        DRF_DEF(_PRGNLCL_SCP, _CTL0, _CTL_EN,            _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _CTL0, _SEQ_EN,            _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _CTL0, _SF_CMD_IFACE_EN,   _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _CTL0, _SF_PUSH_IFACE_EN,  _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _CTL0, _SF_FETCH_IFACE_EN, _DISABLED));
+}
+
+/**
+ * @brief Enables processing of SCP commands.
+ */
+static inline void
+s_scp_Enable_Processing(void)
+{
+    local_write(NV_PRGNLCL_SCP_CTL0,
+        DRF_DEF(_PRGNLCL_SCP, _CTL0, _CTL_EN,            _ENABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _CTL0, _SEQ_EN,            _ENABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _CTL0, _SF_CMD_IFACE_EN,   _ENABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _CTL0, _SF_PUSH_IFACE_EN,  _ENABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _CTL0, _SF_FETCH_IFACE_EN, _ENABLED));
+}
+
+/**
+ * @brief Resets the SCP hardware to its default configuration settings.
+ *
+ * These values have been confirmed by the hardware team.
+ */
+static inline void
+s_scp_Reset_Configuration(void)
+{
+    //
+    // Casting to uint32_t as these constants are technically signed and will
+    // produce a warning otherwise. There should be no risk of overflow here
+    // since these constants are reasonably assumed to fit within the 32-bit
+    // CFG0 register they're defined for.
+    //
+    INLINE_RFD(CERTC, DEVIATE, INT31_C, "Bug: TODO, DR: TODO - perceived sign of bitmap is irrelevant for correctly initializing the register.")
+    local_write(NV_PRGNLCL_SCP_CFG0, (uint32_t)
+        DRF_DEF(_PRGNLCL_SCP, _CFG0, _STALL_TIMEOUT, _INIT)   |
+        DRF_DEF(_PRGNLCL_SCP, _CFG0, _CARRY_CHAIN,   _64)     |
+        DRF_DEF(_PRGNLCL_SCP, _CFG0, _CMD_FLUSH,     _FALSE)  |
+        DRF_DEF(_PRGNLCL_SCP, _CFG0, _AES_ENDIAN,    _BIG)    |
+        DRF_DEF(_PRGNLCL_SCP, _CFG0, _PUSH_ENDIAN,   _LITTLE) |
+        DRF_DEF(_PRGNLCL_SCP, _CFG0, _FETCH_ENDIAN,  _LITTLE) |
+        DRF_DEF(_PRGNLCL_SCP, _CFG0, _CMAC_ENDIAN,   _BIG)    |
+        DRF_DEF(_PRGNLCL_SCP, _CFG0, _ADD_ENDIAN,    _BIG));
+}
+
+/**
+ * @brief Resets the SCP pipeline and sequencers. Also disables RNG.
+ *
+ * @pre Must be called from a secure context if SCP lockdown is enabled.
+ */
+static inline void
+s_scp_Reset_Controls(void)
+{
+    uint32_t reg;
+
+    //
+    // Disable RNG and request pipe and sequencer resets. We also disable some
+    // debug-only features here that must not be active in production.
+    //
+    local_write(NV_PRGNLCL_SCP_CTL1,
+        DRF_DEF(_PRGNLCL_SCP, _CTL1, _SF_PUSH_BYPASS,   _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _CTL1, _SF_FETCH_BYPASS,  _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _CTL1, _SF_FETCH_AS_ZERO, _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _CTL1, _RNG_EN,           _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _CTL1, _RNG_FAKE_MODE,    _DISABLED) |
+        DRF_DEF(_PRGNLCL_SCP, _CTL1, _PIPE_RESET,       _TASK)     |
+        DRF_DEF(_PRGNLCL_SCP, _CTL1, _SEQ_CLEAR,        _TASK));
+
+    // Wait for the pipe and sequencer resets to complete.
+    do
+    {
+        reg = local_read(NV_PRGNLCL_SCP_CTL1);
+    } while (FLD_TEST_DRF(_PRGNLCL_SCP, _CTL1, _PIPE_RESET, _PENDING, reg) ||
+             FLD_TEST_DRF(_PRGNLCL_SCP, _CTL1, _SEQ_CLEAR,  _PENDING, reg));
+}
+
+/**
+ * @brief Resets the source of secret-index 63 per hardware recommendation.
+ */
+static inline void
+s_scp_Reset_Secret_63(void)
+{
+    local_write(NV_PRGNLCL_SCP_SECRET63_CTL,
+        DRF_DEF(_PRGNLCL_SCP, _SECRET63_CTL, _SEL, _PKEY));
+}
+
+/**
+ * @brief Resets the driver's internal state.
+ */
+static inline void
+s_scp_Reset_State(void)
+{
+    g_scp_state.b_initialized         = false;
+    g_scp_state.b_shutdown            = false;
+    g_scp_state.b_direct_mode_active  = false;
+    g_scp_state.b_rand_configured     = false;
+    g_scp_state.b_shortcut_configured = false;
+    g_scp_state.dma_index             = UINT8_MAX;
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/scp/scp_private.c b/spe-freertos-bsp/fsp/source/drivers/scp/scp_private.c
new file mode 100644
index 0000000..15dbc35
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/scp/scp_private.c
@@ -0,0 +1,799 @@
+/**
+ * @file        scp_private.c
+ * @brief       Private interfaces for internal use by the SCP driver.
+ *
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !NVRISCV_FEATURE_SCP
+#error "Attempting to build scp_private.c but the SCP driver is disabled!"
+#endif // NVRISCV_FEATURE_SCP
+
+
+/* Compiler headers */
+#include <stdbool.h>                    // for bool, true, false
+#include <stddef.h>                     // for size_t, NULL
+#include <stdint.h>                     // for uintptr_t, uint64_t, etc.
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for HEADER_CHECK
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>        // for error_t, common error codes
+#if NVRISCV_DRIVER_SCP_SHORTCUT_ENABLED
+#include <fbdma/fbdma.h>                // for fbdma_scp_to_extmem
+#endif // NVRISCV_DRIVER_SCP_SHORTCUT_ENABLED
+#include <fbdma/memutils.h>             // for memutils_riscv_pa_to_target_offset
+#include <misc/macros.h>                // for INLINE_RFD
+#include <misc/nvmisc_drf.h>            // for DRF macros
+
+/* Module-specific FSP headers */
+#include <scp/scp-errors.h>             // for SCP error codes
+#include <scp/scp_common.h>             // for scp_register_index_t, etc.
+#include <scp/scp_direct.h>             // for SCP primitives
+#include <scp/scp_private.h>            // for SCP_SECRET_INDEX_CLEAR, etc.
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The HEADER_CHECK macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+HEADER_CHECK(FSP__ERROR__COMMON_ERRORS_H)
+#if NVRISCV_DRIVER_SCP_SHORTCUT_ENABLED
+HEADER_CHECK(FSP__FBDMA__FBDMA_H)
+#endif // NVRISCV_DRIVER_SCP_SHORTCUT_ENABLED
+HEADER_CHECK(FSP__FBDMA__MEMUTILS_H)
+HEADER_CHECK(FSP__MISC__MACROS_H)
+HEADER_CHECK(FSP__MISC__NVMISC_DRF_H)
+HEADER_CHECK(FSP__SCP__SCP_ERRORS_H)
+HEADER_CHECK(FSP__SCP__SCP_COMMON_H)
+HEADER_CHECK(FSP__SCP__SCP_DIRECT_H)
+HEADER_CHECK(FSP__SCP__SCP_PRIVATE_H)
+
+
+/**
+ * @brief The chmod value for a fully-open register ACL.
+ */
+#define SCP_REGISTER_ACL_ALL 0x1FU
+
+/**
+ * @brief The maximum supported size for a single SCPDMA transfer, in bytes.
+ */
+#define SCP_TRANSFER_LIMIT 256U
+
+
+//
+// Prototypes for local helper functions.
+// See definitions for details.
+//
+static error_t s_scp_Unlock_Reg(scp_register_index_t reg_index);
+static error_t s_scp_Zero_Reg(scp_register_index_t reg_index);
+
+
+/**
+ * @copydoc scp_pvt_Clear_Reg
+ */
+error_t
+scp_pvt_Clear_Reg
+(
+    scp_register_index_t reg_index
+)
+{
+    error_t status;
+
+    // Clear the register's contents.
+    status = s_scp_Zero_Reg(reg_index);
+    if (status != E_SUCCESS)
+    {
+        return status;
+    }
+
+    //
+    // In secure contexts, s_scp_Zero_Reg() will have locked out insecure access
+    // to the target register, so restore it here. In insecure contexts, the
+    // register is assumed to already be accessible (or else s_scp_Zero_Reg()
+    // would have triggered an ACL violation).
+    //
+    if (scp_pvt_Is_Secure())
+    {
+        status = s_scp_Unlock_Reg(reg_index);
+        if (status != E_SUCCESS)
+        {
+            return status;
+        }
+    }
+
+    // Register cleared successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @copydoc scp_pvt_Clear_All
+ */
+error_t
+scp_pvt_Clear_All(void)
+{
+    error_t                 current_status, final_status = E_SUCCESS;
+    scp_register_index_t    reg_index;
+
+    //
+    // Clear each register in turn. To ensure we always clear as much data as
+    // possible, we avoid exiting immediately on failure here and instead
+    // simply track any errors for later.
+    //
+    for (reg_index = SCP_REGISTER_INDEX_0;
+         reg_index < SCP_REGISTER_INDEX_COUNT;
+         reg_index++)
+    {
+        current_status = scp_pvt_Clear_Reg(reg_index);
+        if (current_status != E_SUCCESS)
+        {
+            final_status = current_status;
+        }
+    }
+
+    // Registers cleared.
+    return final_status;
+}
+
+/**
+ * @copydoc scp_pvt_Unlock_All
+ */
+error_t
+scp_pvt_Unlock_All(void)
+{
+    error_t                 current_status, final_status = E_SUCCESS;
+    scp_register_index_t    reg_index;
+
+    //
+    // Unlock each register in turn. To ensure we always unlock as many GPRs as
+    // possible, we avoid exiting immediately on failure here and instead
+    // simply track any errors for later.
+    //
+    for (reg_index = SCP_REGISTER_INDEX_0;
+         reg_index < SCP_REGISTER_INDEX_COUNT;
+         reg_index++)
+    {
+        current_status = s_scp_Unlock_Reg(reg_index);
+        if (current_status != E_SUCCESS)
+        {
+            final_status = current_status;
+        }
+    }
+
+    // Registers unlocked.
+    return final_status;
+}
+
+/**
+ * @copydoc scp_pvt_Zero_All
+ */
+error_t
+scp_pvt_Zero_All(void)
+{
+    error_t                 current_status, final_status = E_SUCCESS;
+    scp_register_index_t    reg_index;
+
+    //
+    // Zero each register in turn. To ensure we always zero as many GPRs as
+    // possible, we avoid exiting immediately on failure here and instead
+    // simply track any errors for later.
+    //
+    for (reg_index = SCP_REGISTER_INDEX_0;
+         reg_index < SCP_REGISTER_INDEX_COUNT;
+         reg_index++)
+    {
+        current_status = s_scp_Zero_Reg(reg_index);
+        if (current_status != E_SUCCESS)
+        {
+            final_status = current_status;
+        }
+    }
+
+    // Registers zeroed.
+    return final_status;
+}
+
+/**
+ * @copydoc scp_pvt_Load_Buffer
+ */
+error_t
+scp_pvt_Load_Buffer
+(
+    uintptr_t               source_pa,
+    scp_register_index_t    reg_index
+)
+{
+    error_t status;
+
+    // Load into the selected register.
+    scp_load(source_pa, reg_index);
+
+    // Wait for completion.
+    scp_wait_dma();
+
+    // Check for any failures.
+    status = scp_check_dma(true);
+    if (status == E_FAULT)
+    {
+        // Bubble up IO-PMP errors.
+        return status;
+    }
+    else if (status != E_SUCCESS)
+    {
+        // No other errors are expected.
+        return E_SCP_GENERIC;
+    }
+
+    // Data was loaded successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @copydoc scp_pvt_Store_Buffer
+ */
+error_t
+scp_pvt_Store_Buffer
+(
+    scp_register_index_t    reg_index,
+    uintptr_t               dest_pa
+)
+{
+    error_t status;
+
+    // Write to the destination buffer.
+    scp_store(reg_index, dest_pa);
+
+#if NVRISCV_DRIVER_SCP_SHORTCUT_ENABLED
+    riscv_mem_target_t  dest_target;
+    uint64_t            dest_offset;
+
+    // Obtain the global target/offset pair for the destination buffer.
+    if (memutils_riscv_pa_to_target_offset(dest_pa, &dest_target, &dest_offset)
+            != E_SUCCESS)
+    {
+        // This should have been validated by the caller.
+        return E_SCP_GENERIC;
+    }
+
+    // Complete the follow-up transfer to external memory, if applicable.
+    if ((dest_target == RISCV_MEM_TARGET_FBGPA) ||
+        (dest_target == RISCV_MEM_TARGET_SYSGPA))
+    {
+        if (fbdma_scp_to_extmem(dest_offset, SCP_REGISTER_SIZE,
+                g_scp_state.dma_index) != E_SUCCESS)
+        {
+            //
+            // This should never happen so long as the caller has properly
+            // sanitized dest_pa and ensured that the shortcut-DMA path has
+            // been configured.
+            //
+            return E_SCP_GENERIC;
+        }
+    }
+#endif // NVRISCV_DRIVER_SCP_SHORTCUT_ENABLED
+
+    // Wait for completion.
+    scp_wait_dma();
+
+    // Check for any failures.
+    status = scp_check_dma(true);
+    if (status == E_FAULT)
+    {
+        // Bubble up IO-PMP errors.
+        return status;
+    }
+    else if (status != E_SUCCESS)
+    {
+        // No other errors are expected.
+        return E_SCP_GENERIC;
+    }
+
+    // Data was stored successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @copydoc scp_pvt_Validate_Buffer
+ */
+error_t
+scp_pvt_Validate_Buffer
+(
+    uintptr_t   base_pa,
+    size_t      size,
+    bool        b_allow_external
+)
+{
+    riscv_mem_target_t  base_target, end_target;
+    uint64_t            base_offset;
+
+    // Check base address for zero/NULL.
+    if (base_pa == (uintptr_t)NULL)
+    {
+        return E_SCP_INVALID_POINTER;
+    }
+
+    // Convert to global target/offset pair.
+    if (memutils_riscv_pa_to_target_offset(base_pa, &base_target, &base_offset)
+            != E_SUCCESS)
+    {
+        return E_SCP_INVALID_BASE;
+    }
+
+    // Ensure the target memory region is supported.
+    switch (base_target)
+    {
+        // IMEM and DMEM are always supported.
+        case RISCV_MEM_TARGET_IMEM:
+        case RISCV_MEM_TARGET_DMEM:
+            break;
+
+        //
+        // FB and SYSMEM are supported only for output buffers and only if the
+        // shortcut-DMA path has been enabled and configured.
+        //
+        case RISCV_MEM_TARGET_FBGPA:
+        case RISCV_MEM_TARGET_SYSGPA:
+            {
+                if (!b_allow_external)
+                {
+                    return E_SCP_INVALID_BASE;
+                }
+
+                if (!NVRISCV_DRIVER_SCP_SHORTCUT_ENABLED)
+                {
+                    return E_SCP_FEATURE_NOT_ENABLED;
+                }
+
+                if (!g_scp_state.b_shortcut_configured)
+                {
+                    return E_SCP_INVALID_DMA_SPECIFIER;
+                }
+            }
+            break;
+
+        // No other locations are supported.
+        default:
+            return E_SCP_INVALID_BASE;
+    }
+
+    //
+    // Obtain the offset of the final byte in the buffer (accounting for the
+    // edge case of a zero-sized buffer).
+    //
+    const size_t end_index = (size - (size > 0U));
+
+    // Ensure the buffer does not overflow uintptr_t.
+    if ((end_index > UINTPTR_MAX) || ((UINTPTR_MAX - end_index) < base_pa))
+    {
+        return E_SCP_OUT_OF_RANGE;
+    }
+
+    // Obtain the physical address of the final byte in the buffer.
+    const uintptr_t end_pa = base_pa + end_index;
+
+    // Ensure the buffer does not overflow the target memory region.
+    if ((memutils_riscv_pa_to_target_offset(end_pa, &end_target, NULL) !=
+        E_SUCCESS) || (end_target != base_target))
+    {
+        return E_SCP_OUT_OF_RANGE;
+    }
+
+    // Ensure the offset into the target memory region is correctly aligned.
+    if (!NV_IS_ALIGNED64(base_offset, SCP_BUFFER_ALIGNMENT))
+    {
+        return E_SCP_INVALID_ADDRESS;
+    }
+
+    // Buffer validated successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @copydoc scp_pvt_Run_Sequence
+ */
+error_t
+scp_pvt_Run_Sequence
+(
+    uintptr_t   source_pa,
+    uintptr_t   dest_pa,
+    size_t      size
+)
+{
+    riscv_mem_target_t  dest_target;
+    uint64_t            source_offset, dest_offset;
+
+    // Track which parameters are present.
+    const bool b_has_input  = (source_pa != (uintptr_t)NULL);
+    const bool b_has_output = (dest_pa   != (uintptr_t)NULL);
+
+    // Obtain the aperture offset of the source buffer, if any.
+    if (b_has_input)
+    {
+        if (memutils_riscv_pa_to_target_offset(source_pa, NULL,
+                &source_offset) != E_SUCCESS)
+        {
+            // This should have been validated by the caller.
+            return E_SCP_GENERIC;
+        }
+    }
+
+    // Obtain the global target/offset pair for the destination buffer, if any.
+    if (b_has_output)
+    {
+        if (memutils_riscv_pa_to_target_offset(dest_pa, &dest_target,
+                &dest_offset) != E_SUCCESS)
+        {
+            // This should have been validated by the caller.
+            return E_SCP_GENERIC;
+        }
+    }
+
+#if NVRISCV_DRIVER_SCP_SHORTCUT_ENABLED
+    //
+    // Track whether the destination buffer (if any) is located in an external
+    // memory region.
+    //
+    const bool b_external_dest = (b_has_output &&
+        ((dest_target == RISCV_MEM_TARGET_FBGPA) ||
+         (dest_target == RISCV_MEM_TARGET_SYSGPA)));
+#endif // NVRISCV_DRIVER_SCP_SHORTCUT_ENABLED
+
+    // Continue processing until no data remains.
+    while (size > 0U)
+    {
+        scp_transfer_size_t transfer_size;
+        uint8_t             num_iterations;
+
+        //
+        // Determine the maximum number of bytes we can process this iteration
+        // based on the alignment of the source and destination buffers (as
+        // applicable), and the constraints of the SCPDMA unit.
+        //
+        // Note that the cast to uint32_t is safe so long as SCP_TRANSFER_LIMIT
+        // is less than 2^32, which we can reasonably assume will always be
+        // true.
+        //
+        INLINE_RFD(CERTC, DEVIATE, INT31_C, "Bug: TODO, DR: TODO - the cast to uint32_t is safe so long as SCP_TRANSFER_LIMIT is less than 2^32");
+        uint32_t batch_size = (uint32_t)LOWESTBIT(
+                                  (b_has_input  ? source_offset : 0U) |
+                                  (b_has_output ? dest_offset   : 0U) |
+                                  SCP_TRANSFER_LIMIT);
+
+        //
+        // Ensure that the computed size does not exceed the quantity of data
+        // remaining to be processed.
+        //
+        while (batch_size > size)
+        {
+            batch_size >>= 1U;
+        }
+
+        //
+        // Convert to an equivalent SCPDMA transfer size and corresponding
+        // number of sequencer iterations (assuming at most one push and/or
+        // fetch instruction per loop).
+        //
+        switch (batch_size)
+        {
+            case (16U * SCP_REGISTER_SIZE):
+                transfer_size  = SCP_TRANSFER_SIZE_16R;
+                num_iterations = 16U;
+                break;
+
+            case (8U * SCP_REGISTER_SIZE):
+                transfer_size  = SCP_TRANSFER_SIZE_8R;
+                num_iterations = 8U;
+                break;
+
+            case (4U * SCP_REGISTER_SIZE):
+                transfer_size  = SCP_TRANSFER_SIZE_4R;
+                num_iterations = 4U;
+                break;
+
+            case (2U * SCP_REGISTER_SIZE):
+                transfer_size  = SCP_TRANSFER_SIZE_2R;
+                num_iterations = 2U;
+                break;
+
+            case (1U * SCP_REGISTER_SIZE):
+                transfer_size  = SCP_TRANSFER_SIZE_1R;
+                num_iterations = 1U;
+                break;
+
+            default:
+                //
+                // This should never happen unless the caller has failed to
+                // ensure that source_pa, dest_pa, and size are aligned
+                // properly.
+                //
+                return E_SCP_GENERIC;
+        }
+
+        // Queue the next batch of data to read from the source (if any).
+        if (b_has_input)
+        {
+            scp_queue_read(source_pa, transfer_size);
+        }
+
+        // Queue the next batch of data to write to the destination (if any).
+        if (b_has_output)
+        {
+            scp_queue_write(dest_pa, transfer_size);
+        }
+
+        // Execute the computed number of sequencer iterations.
+        scp_loop_trace0(num_iterations);
+
+#if NVRISCV_DRIVER_SCP_SHORTCUT_ENABLED
+        // Complete the follow-up transfer to external memory, if applicable.
+        if (b_external_dest)
+        {
+            if (fbdma_scp_to_extmem(dest_offset, batch_size,
+                    g_scp_state.dma_index) != E_SUCCESS)
+            {
+                //
+                // This should never happen so long as the caller has properly
+                // sanitized dest_pa and ensured that the shortcut-DMA path has
+                // been configured.
+                //
+                return E_SCP_GENERIC;
+            }
+        }
+#endif // NVRISCV_DRIVER_SCP_SHORTCUT_ENABLED
+
+        // Wait for the current batch to finish processing.
+        scp_wait_dma();
+
+        // Check for any failures.
+        error_t status = scp_check_dma(true);
+        if (status == E_FAULT)
+        {
+            // Bubble up IO-PMP errors.
+            return status;
+        }
+        else if (status != E_SUCCESS)
+        {
+            // No other errors are expected.
+            return E_SCP_GENERIC;
+        }
+
+        // Update pointers.
+        source_pa += batch_size;
+        dest_pa += batch_size;
+
+        // Update aperture offsets.
+        if (b_has_input)
+        {
+            source_offset += batch_size;
+        }
+
+        if (b_has_output)
+        {
+            dest_offset += batch_size;
+        }
+
+        // Update bytes remaining.
+        size -= batch_size;
+    }
+
+    // Data was processed successfully.
+    return E_SUCCESS;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Resets the ACL of the specified SCP GPR to a fully-open state.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ *
+ * @param[in] reg_index The index of the SCP register to unlock.
+ *
+ * @retval E_SUCCESS        if the register was unlocked successfully.
+ * @retval E_SCP_GENERIC    if an unexpected error occurred.
+ *
+ * @note This function must only be called from secure contexts and requires
+ *       that both secure permissions (Fs and Ks) are already present for the
+ *       register being unlocked.
+ *
+ * @note As a precaution, the target register's contents are cleared after
+ *       unlocking. It is recommended that callers also clear the register
+ *       before unlocking by calling s_scp_Zero_Reg() and checking that it
+ *       succeeded.
+ */
+static error_t
+s_scp_Unlock_Reg
+(
+    scp_register_index_t reg_index
+)
+{
+    //
+    // Enable all permissions in the ACL of the specified register.
+    //
+    // Some concerns were raised that this creates a dangerous potential ROP
+    // gadget for an attacker to leverage, but we don't have any other options
+    // for recovering the insecure-write (Wi) permission at this point.
+    //
+    // We did consider reducing the number of permissions we grant here, but
+    // that would require sprinkling additional code throughout other parts of
+    // the SCP driver in order to recover the remaining insecure-fetch (Fi) and
+    // insecure-key (Ki) permissions on-demand. It's also unlikely that such an
+    // alternative approach would buy us much addditional security as any
+    // attacker with ROP capabilities can likely also manipulate function
+    // arguments anyway.
+    //
+    scp_chmod(SCP_REGISTER_ACL_ALL, reg_index);
+
+    //
+    // Clear the register's contents. This gives us some protection against the
+    // aforementioned ROP threat as it makes leaking sensitive information a
+    // bit harder.
+    //
+    // Note that we don't need to go through the extra steps that
+    // s_scp_Zero_Reg() follows here since the target register is expected to be
+    // fetchable already.
+    //
+    scp_xor(reg_index, reg_index);
+
+    // Wait for completion.
+    scp_wait_dma();
+
+    //
+    // Check for failure. The SCPDMA itself should never fail here (we'd get
+    // an interrupt instead if the actual chmod or xor instructions failed),
+    // but we check anyway to be safe.
+    //
+    if (scp_check_dma(true) != E_SUCCESS)
+    {
+        return E_SCP_GENERIC;
+    }
+
+    // Register unlocked successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @brief Zeroes the specified SCP GPR.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre The target register must be writable and fetchable if called from an
+ *      insecure context.
+ *
+ * @param[in] reg_index The index of the SCP register to zero.
+ *
+ * @retval E_SUCCESS                    if the register was zeroed successfully.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ *
+ * @note Calling this function from a secure context will leave the specified
+ *       SCP GPR inaccessible from insecure contexts until explicitly unlocked
+ *       later.
+ */
+static error_t
+s_scp_Zero_Reg
+(
+    scp_register_index_t reg_index
+)
+{
+    //
+    // In order for the xor operation below to succeed, the target register
+    // must have its fetchable attribute set in its associated ACL. We can
+    // ensure this in secure contexts by first loading a fetchable hardware
+    // secret into the register, which we do here.
+    //
+    // Insecure contexts do not have this option but are also not expected to
+    // ever encounter a non-fetchable register unless the application has been
+    // misusing certain direct-mode interfaces (in which case we'll simply end
+    // up triggering an ACL violation).
+    //
+    if (scp_pvt_Is_Secure())
+    {
+        // Load secret-index zero to ensure the target register is fetchable.
+        scp_secret(SCP_SECRET_INDEX_CLEAR, reg_index);
+
+        // Wait for completion.
+        scp_wait_dma();
+
+        // Check for failures.
+        error_t status = scp_check_dma(true);
+
+        //
+        // Catch denied access to the hardware secret. We return a unique
+        // error code here to help differentiate this failure from other
+        // permissions errors that higher-level interfaces using this function
+        // may return.
+        //
+        if (status == E_PERM)
+        {
+            return E_SCP_INSUFFICIENT_RESOURCES;
+        }
+        //
+        // Other failures shouldn't be possible here so just return a generic
+        // error on the off chance we hit one somehow.
+        //
+        else if (status != E_SUCCESS)
+        {
+            return E_SCP_GENERIC;
+        }
+    }
+
+    // Clear the register's contents.
+    scp_xor(reg_index, reg_index);
+
+    // Wait for completion.
+    scp_wait_dma();
+
+    //
+    // Check for failure. The SCPDMA itself should never fail here (we'd get
+    // an interrupt instead if the actual xor instruction failed), but we
+    // check anyway to be safe.
+    //
+    if (scp_check_dma(true) != E_SUCCESS)
+    {
+        return E_SCP_GENERIC;
+    }
+
+    // Register was zeroed successfully.
+    return E_SUCCESS;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @copydoc g_scp_state
+ */
+scp_state_t g_scp_state =
+{
+    // Not initialized until scp_Init() is called.
+    .b_initialized          = false,
+
+    // Not shutdown until scp_Shutdown() is called.
+    .b_shutdown             = false,
+
+    // Direct mode must be requested by the application.
+    .b_direct_mode_active   = false,
+
+    // RNG hardware must be configured explicitly.
+    .b_rand_configured      = false,
+
+    // Shortcut path must be configured explicitly.
+    .b_shortcut_configured  = false,
+    .dma_index              = UINT8_MAX,
+};
diff --git a/spe-freertos-bsp/fsp/source/drivers/scp/scp_rand.c b/spe-freertos-bsp/fsp/source/drivers/scp/scp_rand.c
new file mode 100644
index 0000000..a771026
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/scp/scp_rand.c
@@ -0,0 +1,498 @@
+/**
+ * @file        scp_rand.c
+ * @brief       SCP features for random-number generation.
+ *
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !NVRISCV_FEATURE_SCP
+#error "Attempting to build scp_rand.c but the SCP driver is disabled!"
+#endif // NVRISCV_FEATURE_SCP
+
+
+/* Compiler headers */
+#include <stdbool.h>                    // for bool, true, false
+#include <stddef.h>                     // for size_t, NULL
+#include <stdint.h>                     // for uintptr_t, uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for HEADER_CHECK
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/io.h>                     // for local_read, local_write
+#include <error/common-errors.h>        // for error_t, common error codes
+#include <misc/nvmisc_drf.h>            // for DRF macros
+
+/* Module-specific FSP headers */
+#include <scp/scp-errors.h>             // for SCP error codes
+#include <scp/scp_common.h>             // for scp_register_index_t
+#include <scp/scp_direct.h>             // for SCP primitives
+#include <scp/scp_general.h>            // for scp_Is_Debug
+#include <scp/scp_private.h>            // for scp_pvt_*
+#include <scp/scp_rand.h>               // for SCP_RAND_SIZE, etc.
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The HEADER_CHECK macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+HEADER_CHECK(FSP__CPU__IO_H)
+HEADER_CHECK(FSP__ERROR__COMMON_ERRORS_H)
+HEADER_CHECK(FSP__MISC__NVMISC_DRF_H)
+HEADER_CHECK(FSP__SCP__SCP_ERRORS_H)
+HEADER_CHECK(FSP__SCP__SCP_COMMON_H)
+HEADER_CHECK(FSP__SCP__SCP_DIRECT_H)
+HEADER_CHECK(FSP__SCP__SCP_GENERAL_H)
+HEADER_CHECK(FSP__SCP__SCP_PRIVATE_H)
+HEADER_CHECK(FSP__SCP__SCP_RAND_H)
+
+
+/**
+ * @brief Default tap selections for the two non-SCC ring-oscillators.
+ *
+ * Values taken from https://confluence.nvidia.com/x/MO1QGw.
+ *
+ * @macro-title Default ring-oscillator tap selections.
+ *
+ * @SCP_DEFAULT_RO_TAP_A    Tap selection for ring-oscillator A.
+ * @SCP_DEFAULT_RO_TAP_B    Tap selection for ring-oscillator B.
+ */
+#define SCP_DEFAULT_RO_TAP_A 0x7U
+#define SCP_DEFAULT_RO_TAP_B 0x5U
+
+
+//
+// Prototypes for local helper functions.
+// See definitions for details.
+//
+static error_t     s_scp_Load_Rand_Sequence(void);
+
+static inline bool s_scp_Is_Rand_Enabled(void);
+
+static inline void s_scp_Configure_Oscillators(void);
+
+static inline void s_scp_Disable_Fake_Rand(void);
+static inline void s_scp_Enable_Fake_Rand(void);
+
+
+/**
+ * @copydoc scp_Configure_Rand
+ */
+error_t
+scp_Configure_Rand
+(
+    scp_rand_config_t config
+)
+{
+    // Verify driver state before proceeding further.
+    if (!g_scp_state.b_initialized)
+    {
+        return E_SCP_NOT_READY;
+    }
+
+    // Invalidate previous configuration settings, if any.
+    g_scp_state.b_rand_configured = false;
+
+    // This function cannot be called from direct mode.
+    if (g_scp_state.b_direct_mode_active)
+    {
+        return E_INVALID_STATE;
+    }
+
+    // Verify access to lockable SCP registers/fields.
+    if (scp_pvt_Is_Access_Restricted())
+    {
+        return E_SCP_INVALID_LOCK_STATE;
+    }
+
+    // Ensure that the RNG hardware is not currently active.
+    if (s_scp_Is_Rand_Enabled())
+    {
+        return E_BUSY;
+    }
+
+    // Apply the desired configuration settings.
+    switch (config)
+    {
+        case SCP_RAND_CONFIG_DEFAULT:
+            // Tap the ring-oscillators at their recommended lengths.
+            s_scp_Configure_Oscillators();
+
+            // Ensure that deterministic mode is off.
+            s_scp_Disable_Fake_Rand();
+            break;
+
+        case SCP_RAND_CONFIG_FAKE:
+            // Build-time configuration is mandatory per security-bar rules.
+            if (!NVRISCV_DRIVER_SCP_FAKE_RNG_ENABLED)
+            {
+                return E_SCP_FEATURE_NOT_ENABLED;
+            }
+
+            // Deterministic mode is not permitted in production.
+            if (!scp_Is_Debug())
+            {
+                return E_SCP_INVALID_REQUEST;
+            }
+
+            //
+            // Enable deterministic mode as requested (no further configuration
+            // is needed as of SCP RNG v2.0).
+            //
+            s_scp_Enable_Fake_Rand();
+            break;
+
+        default:
+            // Not a recognized configuration.
+            return E_INVALID_PARAM;
+    }
+
+    // Perform a pipe reset to clear any residual RNG data.
+    scp_pvt_Reset_Pipeline();
+
+    // Update internal state.
+    g_scp_state.b_rand_configured = true;
+
+    // Configuration settings were applied successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @copydoc scp_Start_Rand
+ */
+error_t
+scp_Start_Rand(void)
+{
+    // Verify driver state before proceeding further.
+    if (!g_scp_state.b_initialized)
+    {
+        return E_SCP_NOT_READY;
+    }
+
+    // Ensure that the RNG hardware has been properly configured.
+    if (!g_scp_state.b_rand_configured)
+    {
+        return E_INVALID_STATE;
+    }
+
+    // Verify access to lockable SCP registers/fields.
+    if (scp_pvt_Is_Access_Restricted())
+    {
+        return E_SCP_INVALID_LOCK_STATE;
+    }
+
+    // Check whether the RNG hardware is already running.
+    if (s_scp_Is_Rand_Enabled())
+    {
+        return E_SCP_NOTHING_TO_DO;
+    }
+
+    // Start the RNG hardware.
+    scp_pvt_Enable_Rand();
+
+    // RNG hardware was started successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @copydoc scp_Stop_Rand
+ */
+error_t
+scp_Stop_Rand(void)
+{
+    // Verify driver state before proceeding further.
+    if (!g_scp_state.b_initialized)
+    {
+        return E_SCP_NOT_READY;
+    }
+
+    // Verify access to lockable SCP registers/fields.
+    if (scp_pvt_Is_Access_Restricted())
+    {
+        return E_SCP_INVALID_LOCK_STATE;
+    }
+
+    // Check whether the RNG hardware is already stopped.
+    if (!s_scp_Is_Rand_Enabled())
+    {
+        return E_SCP_NOTHING_TO_DO;
+    }
+
+    //
+    // Make sure the SCP unit is idle before disabling RNG. Otherwise, we may
+    // cause some pending RNG operation to hang.
+    //
+    scp_wait_dma();
+
+    // Stop the RNG hardware.
+    scp_pvt_Disable_Rand();
+
+    // RNG hardware was stopped successfully.
+    return E_SUCCESS;
+}
+
+/**
+ * @copydoc scp_Get_Rand
+ */
+error_t
+scp_Get_Rand
+(
+    uintptr_t   dest_pa,
+    size_t      size,
+    uintptr_t   context_pa
+)
+{
+    error_t status = E_SUCCESS;
+
+    // Verify driver state before proceeding further.
+    if (!g_scp_state.b_initialized)
+    {
+        // Early exit as clean-up code may not be able to execute safely.
+        return E_SCP_NOT_READY;
+    }
+
+    // This function cannot be called from direct mode.
+    if (g_scp_state.b_direct_mode_active)
+    {
+        // Early exit as clean-up code may not be able to execute safely.
+        return E_INVALID_STATE;
+    }
+
+    // Verify access to lockable SCP registers/fields.
+    if (scp_pvt_Is_Access_Restricted())
+    {
+        // Early exit as clean-up code may not be able to execute safely.
+        return E_SCP_INVALID_LOCK_STATE;
+    }
+
+    // Make sure the RNG hardware is active and properly configured.
+    if (!s_scp_Is_Rand_Enabled() || !g_scp_state.b_rand_configured)
+    {
+        status = E_SCP_INVALID_OPERATION;
+        goto cleanup;
+    }
+
+    // Verify destination buffer.
+    status = scp_pvt_Validate_Buffer(dest_pa, size, true);
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+    // Verify byte count.
+    if ((size == 0U) || (size % SCP_RAND_SIZE != 0U))
+    {
+        status = E_SCP_INVALID_REQUEST;
+        goto cleanup;
+    }
+
+    // Handle context buffer, if provided.
+    if (context_pa != (uintptr_t)NULL)
+    {
+        // Verify context buffer.
+        status = scp_pvt_Validate_Buffer(context_pa, SCP_RAND_SIZE, false);
+        if (status != E_SUCCESS)
+        {
+            goto cleanup;
+        }
+
+        // Load initial context information into register-index one.
+        status = scp_pvt_Load_Buffer(context_pa, SCP_REGISTER_INDEX_1);
+        if (status != E_SUCCESS)
+        {
+            goto cleanup;
+        }
+    }
+
+    // Load sequencer zero with the instructions for RNG and update Ku.
+    status = s_scp_Load_Rand_Sequence();
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+    // Run the sequence we loaded above to generate the output data.
+    status = scp_pvt_Run_Sequence((uintptr_t)NULL, dest_pa, size);
+    if (status != E_SUCCESS)
+    {
+        goto cleanup;
+    }
+
+cleanup:
+    //
+    // Clear the sequencers to free them up for future use and prevent
+    // anything accidentally carrying forward into other interfaces.
+    //
+    scp_pvt_Reset_Sequencers();
+
+    //
+    // Clear the SCP GPRs to scrub any potentially sensitive data from them and
+    // unlock their associated ACLs. Report failures only if no higher-priority
+    // error is already pending.
+    //
+    error_t clear_status = scp_pvt_Clear_All();
+    if (status == E_SUCCESS)
+    {
+        status = clear_status;
+    }
+
+    // Done.
+    return status;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Loads the SCP instructions for RNG into sequencer zero.
+ *
+ * Loads sequencer zero with the set of SCP instructions required to generate a
+ * single block of true-random data. Also updates the key register (Ku).
+ *
+ * The loaded algorithm assumes that the initial context value, if any, has
+ * been loaded to register-index one and that register-indices two and three
+ * are available for use as intermediate storage.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ *
+ * @retval E_SUCCESS                if instructions were loaded successfully.
+ * @retval E_SCP_GENERIC            if an unexpected error occurred.
+ */
+static error_t
+s_scp_Load_Rand_Sequence(void)
+{
+    // Prepare to write five instructions to sequencer zero.
+    scp_load_trace0(5U);
+    {
+        //
+        // Improve RNG quality by collecting entropy across two consecutive
+        // random numbers.
+        //
+        scp_rand(SCP_REGISTER_INDEX_2);
+        scp_rand(SCP_REGISTER_INDEX_3);
+
+        // Mix the current context value into the first number.
+        scp_xor(SCP_REGISTER_INDEX_1, SCP_REGISTER_INDEX_2);
+
+        //
+        // Whiten the second number with an encryption step using the above
+        // value as the key. The result will be carried forward as the new
+        // context value to be used in the next iteration.
+        //
+        scp_encrypt(SCP_REGISTER_INDEX_3, SCP_REGISTER_INDEX_1);
+
+        // Store the random data we produced.
+        scp_fetch(SCP_REGISTER_INDEX_1);
+    }
+
+    //
+    // Select the register from which the encrypt stage of each sequencer
+    // iteration will source its key. This only needs to be specified once,
+    // hence its exclusion from the above sequencer load.
+    //
+    scp_key(SCP_REGISTER_INDEX_2);
+
+    // Wait for completion.
+    scp_wait_dma();
+
+    // Check for any unexpected failures.
+    if (scp_check_dma(true) != E_SUCCESS)
+    {
+        return E_SCP_GENERIC;
+    }
+
+    // Sequence loaded successfully.
+    return E_SUCCESS;
+}
+
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Checks whether the SCP unit's RNG hardware is enabled.
+ *
+ * @pre Must be called from a secure context if SCP lockdown is enabled.
+ *
+ * @retval true  if the RNG hardware is enabled.
+ * @retval false if the RNG hardware is disabled.
+ */
+static inline bool
+s_scp_Is_Rand_Enabled(void)
+{
+    return FLD_TEST_DRF(_PRGNLCL_SCP, _CTL1, _RNG_EN, _ENABLED,
+                        local_read(NV_PRGNLCL_SCP_CTL1));
+}
+
+/**
+ * @brief Configures the ring-oscillators for the SCP unit's RNG hardware.
+ *
+ * @pre Must be called from a secure context if SCP lockdown is enabled.
+ */
+static inline void
+s_scp_Configure_Oscillators(void)
+{
+    uint32_t reg = local_read(NV_PRGNLCL_SCP_RNDCTL11);
+
+    reg = FLD_SET_DRF_NUM(_PRGNLCL_SCP, _RNDCTL11, _AUTOCAL_STATIC_TAP_A,
+                          SCP_DEFAULT_RO_TAP_A, reg);
+    reg = FLD_SET_DRF_NUM(_PRGNLCL_SCP, _RNDCTL11, _AUTOCAL_STATIC_TAP_B,
+                          SCP_DEFAULT_RO_TAP_B, reg);
+
+    local_write(NV_PRGNLCL_SCP_RNDCTL11, reg);
+}
+
+/**
+ * @brief Disables deterministic mode for the SCP unit's RNG hardware.
+ *
+ * @pre Must be called from a secure context if SCP lockdown is enabled.
+ */
+static inline void
+s_scp_Disable_Fake_Rand(void)
+{
+    local_write(NV_PRGNLCL_SCP_CTL1,
+        FLD_SET_DRF(_PRGNLCL_SCP, _CTL1, _RNG_FAKE_MODE, _DISABLED,
+            local_read(NV_PRGNLCL_SCP_CTL1)));
+}
+
+/**
+ * @brief Enables deterministic mode for the SCP unit's RNG hardware.
+ *
+ * @pre Must be called from a secure context if SCP lockdown is enabled.
+ */
+static inline void
+s_scp_Enable_Fake_Rand(void)
+{
+    local_write(NV_PRGNLCL_SCP_CTL1,
+        FLD_SET_DRF(_PRGNLCL_SCP, _CTL1, _RNG_FAKE_MODE, _ENABLED,
+            local_read(NV_PRGNLCL_SCP_CTL1)));
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/scp/scp_sanity.c b/spe-freertos-bsp/fsp/source/drivers/scp/scp_sanity.c
new file mode 100644
index 0000000..32656a3
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/scp/scp_sanity.c
@@ -0,0 +1,112 @@
+/**
+ * @file        scp_sanity.c
+ * @brief       Global sanity checks for the SCP driver.
+ *
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#if !NVRISCV_FEATURE_SCP
+#error "Attempting to build scp_sanity.c but the SCP driver is disabled!"
+#endif // NVRISCV_FEATURE_SCP
+
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for HEADER_CHECK
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/nvmisc_drf.h>            // for DRF macros (for scp_direct.h)
+
+/* Module-specific FSP headers */
+#include <scp/scp_common.h>             // for scp_register_index_t, etc.
+#include <scp/scp_crypt.h>              // for SCP_BLOCK_SIZE, SCP_KEY_SIZE
+#include <scp/scp_direct.h>             // for SCP_REGISTER_SIZE
+#include <scp/scp_private.h>            // for SCP_SECRET_INDEX_CLEAR
+#include <scp/scp_rand.h>               // for SCP_RAND_SIZE
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The HEADER_CHECK macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+HEADER_CHECK(FSP__MISC__NVMISC_DRF_H)
+HEADER_CHECK(FSP__SCP__SCP_COMMON_H)
+HEADER_CHECK(FSP__SCP__SCP_CRYPT_H)
+HEADER_CHECK(FSP__SCP__SCP_DIRECT_H)
+HEADER_CHECK(FSP__SCP__SCP_PRIVATE_H)
+HEADER_CHECK(FSP__SCP__SCP_RAND_H)
+
+
+//
+// Keeping these constants distinct helps insulate external clients against
+// future hardware changes, but also complicates the internal driver logic
+// somewhat. To get around this, we simply assume them to be equivalent for
+// now and defer any complicated logic updates until that assumption no longer
+// holds.
+//
+_Static_assert((SCP_BLOCK_SIZE       == SCP_REGISTER_SIZE) &&
+               (SCP_BUFFER_ALIGNMENT == SCP_REGISTER_SIZE) &&
+               (SCP_KEY_SIZE         == SCP_REGISTER_SIZE) &&
+               (SCP_RAND_SIZE        == SCP_REGISTER_SIZE) ,
+    "One or more of the core size constants used by the SCP driver no longer "
+    "match the SCP register size. Substantial updates may need to be made to "
+    "the internal driver logic to accommodate."
+);
+
+//
+// The enumeration constants for the SCP GPRs have both short- and long-form
+// names as a compromise between the stylistic consistency perferred by some
+// clients and the brevity preferred by others. This check loosely ensures that
+// the two formats remain in sync with each other.
+//
+_Static_assert(SCP_RCOUNT == SCP_REGISTER_INDEX_COUNT,
+    "Mismatch detected between the short and long forms of the "
+    "scp_register_index_t enumeration constants."
+);
+
+//
+// The specific value of this constant is mandated by the microcode security
+// bar and is also assumed by the SCP driver in order to simplify certain input
+// -validation checks. It should therefore only be changed with care and prior
+// approval.
+//
+_Static_assert(SCP_SECRET_INDEX_CLEAR == 0U,
+    "The secret index selected by the SCP driver for clearing registers in "
+    "secure mode does not match the value mandated by the microcode security "
+    "bar. Please ensure that you have received the proper prior approvals "
+    "before making this change, and remember to update all affected input-"
+    "validation routines and API documentation accordingly."
+);
diff --git a/spe-freertos-bsp/fsp/source/drivers/sha-nvriscv/module-sha-nvriscv-config.mk b/spe-freertos-bsp/fsp/source/drivers/sha-nvriscv/module-sha-nvriscv-config.mk
new file mode 100644
index 0000000..37b91e7
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/sha-nvriscv/module-sha-nvriscv-config.mk
@@ -0,0 +1,65 @@
+#
+# @file module-sha-nvriscv-config.mk
+# 
+# @brief SHA-NVRISCV config makefile for libFSP.
+# 
+# Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+# * Neither the name of NVIDIA CORPORATION nor the names of its
+# contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-sha-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_SHA_NVRISCV_CONFIG               := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_SHA_NVRISCV_DEPENDS              := FSP_COMMON
+MODULE_SHA_NVRISCV_DEPENDS              := SHA_NVRISCV
+$(foreach _,$(MODULE_SHA_NVRISCV_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_SHA_NVRISCV_DRIVERS_DIR           = $(FSP_COMMON_REPO)/drivers/sha-nvriscv
+MODULE_SHA_NVRISCV_SOURCE_DIR            = $(MODULE_SHA_NVRISCV_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+#MODULE_SHA_NVRISCV_INCLUDES              = $(FSP_COMMON_REPO)/include/sha
diff --git a/spe-freertos-bsp/fsp/source/drivers/sha-nvriscv/module-sha-nvriscv.mk b/spe-freertos-bsp/fsp/source/drivers/sha-nvriscv/module-sha-nvriscv.mk
new file mode 100644
index 0000000..1be22c9
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/sha-nvriscv/module-sha-nvriscv.mk
@@ -0,0 +1,87 @@
+#
+# @file module-sha-nvriscv.mk
+#
+# @brief SHA-NVRISCV makefile for libFSP.
+#
+# Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution.
+# * Neither the name of NVIDIA CORPORATION nor the names of its
+# contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-sha-nvriscv.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_SHA_NVRISCV_NAME                 := SHA_NVRISCV
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_SHA_NVRISCV_DEFINED              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_SHA_NVRISCV_DEPENDS              := SHA_NVRISCV
+$(foreach _,$(CONFIG_SHA_NVRISCV_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_SHA_NVRISCV_C_SRC                 =
+
+ifeq ($(NVRISCV_FEATURE_SHA),y)
+MODULE_SHA_NVRISCV_C_SRC                += $(MODULE_SHA_NVRISCV_DRIVERS_DIR)/sha.c
+endif
+
+#
+# Assembly source
+MODULE_SHA_NVRISCV_ASM_SRC               =
+
+#
+# Special C Flags
+MODULE_SHA_NVRISCV_C_FLAGS               =
+
+#
+# Special ASM Flags
+MODULE_SHA_NVRISCV_ASM_FLAGS             =
diff --git a/spe-freertos-bsp/fsp/source/drivers/sha-nvriscv/sha.c b/spe-freertos-bsp/fsp/source/drivers/sha-nvriscv/sha.c
new file mode 100644
index 0000000..53a991d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/sha-nvriscv/sha.c
@@ -0,0 +1,1447 @@
+/**
+ * @file sha.c
+ *
+ * @brief SHA library for SHA-2 and HMAC SHA-2.
+ *
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stddef.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <error/common-errors.h>
+
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/type-conversion.h>
+#include <misc/macros.h>
+#include <cpu/csr.h>
+#include <cpu/io.h>
+#include <cpu/io_dio.h>
+#include <cpu/io_local.h>
+#include <cpu/ptimer.h>
+#include <libc-lite/libc.h>
+#include <misc/nvmisc_drf.h>
+#include <misc/bitops.h>
+
+/* Module-specific FSP headers */
+#include <sha-nvriscv/sha.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: TODO, DR: TODO")
+
+HEADER_CHECK(FSP__ERROR__COMMON_ERRORS_H)
+HEADER_CHECK(FSP__MISC__MACROS_H)
+HEADER_CHECK(FSP__CPU__TYPE_CONVERSION_H)
+HEADER_CHECK(FSP__CPU__IO_H)
+HEADER_CHECK(FSP__CPU__IO_DIO_H)
+HEADER_CHECK(FSP__LIBC__LIBC_H)
+HEADER_CHECK(FSP__MISC__NVMISC_DRF_H)
+HEADER_CHECK(FSP__MISC__BITOPS_H)
+HEADER_CHECK(FSP__SHA_NVRISCV__SHA_H)
+HEADER_CHECK(FSP__SHA_NVRISCV__SHA_ERRORS_H)
+
+// sync with PTIMER, currently 100ms is safe for the longest message
+#define SHA_ENGINE_IDLE_TIMEOUT_NS          (100000000ULL)
+// sync with PTIMER, base on idle timeout, HW recommend SHA_ENGINE_IDLE_TIMEOUT_NS + 20ns
+#define SHA_ENGINE_SW_RESET_TIMEOUT_NS      ((SHA_ENGINE_IDLE_TIMEOUT_NS) + 20ULL)
+#define SHA_ENGINE_HALT_TIMEOUT_NS          (SHA_ENGINE_IDLE_TIMEOUT_NS)
+#define SHA_MSG_BYTES_MAX                   (BIT_TO_BYTE_LENGTH(UINT32_MAX))
+#define HMAC_SHA_IPAD_MASK                  ((uint8_t)0x36)
+#define HMAC_SHA_OPAD_MASK                  ((uint8_t)0x5C)
+#define HMAC_SHA_MAX_BLOCK_SIZE_BYTE        SHA_512_BLOCK_SIZE_BYTE
+#define HMAC_SHA_MAX_HASH_SIZE_BYTE         SHA_512_HASH_SIZE_BYTE
+
+//TODO: Remove this when moving to nvriscv and use byteswap function from utils
+#define NV_BYTESWAP32(a) (      \
+    (((a) & 0xff000000U) >> 24U) |  \
+    (((a) & 0x00ff0000U) >> 8U)  |  \
+    (((a) & 0x0000ff00U) << 8U)  |  \
+    (((a) & 0x000000ffU) << 24U) )
+
+/* Private Function Declaration */
+static void     sha_set_init_vector(SHA_ALGO_ID algo_id);
+static error_t  sha_wait_engine_idle(uint64_t time_out_ns);
+static error_t  sha_engine_soft_reset(uint64_t time_out_ns);
+static error_t  sha_wait_for_busy(uint64_t time_out_ns);
+static error_t  sha_get_config_encode_mode(SHA_ALGO_ID algo_id, uint8_t* p_mode);
+static bool     sha_hmac_is_sha_algo_supported(SHA_ALGO_ID algo_id);
+static bool     sha_task_config_is_valid
+(
+    const SHA_CONTEXT *p_sha_context,
+    const SHA_TASK_CONFIG *p_task_cfg
+);
+static inline uint64_t pointer_to_address(uint8_t* buf);
+static inline bool timeout_is_hit(uint64_t start_time, uint64_t timeout);
+static inline error_t sha_get_result_word(uint32_t register_index, uint8_t* result, bool b_scrub_reg);
+
+
+/*!
+ * @brief Execute SHA engine halt
+ *
+ * @return E_SUCCESS if halt engine successfully
+ *         E_SHA_ENG_ERROR if failed.
+ *
+ */
+error_t
+sha_engine_halt
+(
+    void
+)
+{
+    uint32_t reg = 0;
+    error_t status = E_SUCCESS;
+
+    reg = local_read(NV_PRGNLCL_FALCON_SHA_OPERATION);
+    reg = FLD_SET_DRF(_PRGNLCL_FALCON, _SHA_OPERATION, _HALT, _ENABLE, reg);
+    local_write(NV_PRGNLCL_FALCON_SHA_OPERATION, reg);
+
+    reg = local_read(NV_PRGNLCL_FALCON_SHA_STATUS);
+
+    if (!FLD_TEST_DRF(_PRGNLCL, _FALCON_SHA, _STATUS_STATE, _HALTED, reg))
+    {
+        status = E_SHA_ENG_ERROR;
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Acquire SHA mutex
+ *
+ * @param[in] mutex_token The mutex_token allocated by client to acquire SHA mutex.
+ *
+ * @return E_SUCCESS if acquire or release mutex successfuly.
+ *         E_SHA_MUTEX_ACQUIRE_FAILED if failed.
+ *
+ */
+error_t
+sha_acquire_mutex
+(
+    uint8_t mutex_token
+)
+{
+    uint32_t reg = 0;
+    bool locked = false;
+    error_t status = E_SUCCESS;
+
+    if (mutex_token == 0U)
+    {
+        status = E_INVALID_PARAM;
+    }
+
+    if (status == E_SUCCESS)
+    {
+        reg = local_read(NV_PRGNLCL_FALCON_SHA_MUTEX_STATUS);
+        locked = FLD_TEST_DRF_NUM(_PRGNLCL, _FALCON_SHA_MUTEX_STATUS, _LOCKED, mutex_token, reg);
+        if (locked)
+        {
+            status = E_SHA_MUTEX_ACQUIRE_FAILED; // mutex blocked
+        }
+    }
+
+    if (status == E_SUCCESS)
+    {
+        reg = DRF_NUM(_PRGNLCL, _FALCON_SHA_MUTEX, _VAL, mutex_token);
+        local_write(NV_PRGNLCL_FALCON_SHA_MUTEX , reg);
+        reg = local_read(NV_PRGNLCL_FALCON_SHA_MUTEX_STATUS);
+        locked = FLD_TEST_DRF_NUM(_PRGNLCL, _FALCON_SHA_MUTEX_STATUS, _LOCKED, mutex_token, reg);
+
+        status = locked ? E_SUCCESS : E_SHA_MUTEX_ACQUIRE_FAILED;
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Release SHA mutex
+ *
+ * @param[in] mutex_token The mutex_token allocated by client to release SHA mutex.
+ *
+ * @return E_SUCCESS if acquire or release mutex successfuly.
+ *         E_SHA_MUTEX_ACQUIRE_FAILED if failed.
+ *
+ */
+error_t
+sha_release_mutex
+(
+    uint8_t mutex_token
+)
+{
+    uint32_t reg = 0;
+    bool unlocked = false;
+    error_t status = E_SUCCESS;
+
+    if (mutex_token == 0U)
+    {
+        status = E_INVALID_PARAM;
+    }
+    if (status == E_SUCCESS)
+    {
+        reg = DRF_NUM(_PRGNLCL, _FALCON_SHA_MUTEX_RELEASE, _VAL, mutex_token);
+        local_write(NV_PRGNLCL_FALCON_SHA_MUTEX_RELEASE, reg);
+        reg = local_read(NV_PRGNLCL_FALCON_SHA_MUTEX_STATUS);
+        unlocked = FLD_TEST_DRF(_PRGNLCL, _FALCON_SHA_MUTEX_STATUS, _LOCKED, _INIT, reg);
+
+        status = unlocked ? E_SUCCESS : E_SHA_MUTEX_RELEASE_FAILED;
+    }
+
+    return status;
+}
+
+/*!
+ * @brief To get SHA hash size in byte per SHA algorithm id
+ *
+ * @param[in]  algo_id SHA algorithm id
+ * @param[out] *p_size The pointer to save return hash size
+ *
+ * @return E_SUCCESS if get hash size successfully.
+ *         E_INVALID_PARAM if failed.
+ *
+ */
+error_t
+sha_get_hash_size_byte
+(
+    SHA_ALGO_ID  algo_id,
+    uint32_t     *p_size
+)
+{
+    error_t status = E_SUCCESS;
+    if (p_size == NULL)
+    {
+        status = E_INVALID_PARAM;
+    }
+    if (status == E_SUCCESS)
+    {
+        switch (algo_id)
+        {
+            case SHA_ALGO_ID_SHA_1:
+                *p_size = SHA_1_HASH_SIZE_BYTE;
+                break;
+
+            case SHA_ALGO_ID_SHA_224:
+                *p_size = SHA_224_HASH_SIZE_BYTE;
+                break;
+
+            case SHA_ALGO_ID_SHA_256:
+                *p_size = SHA_256_HASH_SIZE_BYTE;
+                break;
+
+            case SHA_ALGO_ID_SHA_384:
+                *p_size = SHA_384_HASH_SIZE_BYTE;
+                break;
+
+            case SHA_ALGO_ID_SHA_512:
+                *p_size = SHA_512_HASH_SIZE_BYTE;
+                break;
+
+            case SHA_ALGO_ID_SHA_512_224:
+                *p_size = SHA_512_224_HASH_SIZE_BYTE;
+                break;
+
+            case SHA_ALGO_ID_SHA_512_256:
+                *p_size = SHA_512_256_HASH_SIZE_BYTE;
+                break;
+
+            default:
+                status = E_INVALID_PARAM;
+                break;
+        }
+    }
+    return status;
+}
+
+/*!
+ * @brief To get SHA block size in byte per SHA algorithm id
+ *
+ * @param[in]  algo_id SHA algorithm id
+ * @param[out] *p_size The pointer to save return block size
+ *
+ * @return E_SUCCESS if get hash size successfully.
+ *         E_INVALID_PARAM if failed.
+ *
+ */
+error_t
+sha_get_block_size_byte
+(
+    SHA_ALGO_ID  algo_id,
+    uint32_t     *p_size
+)
+{
+    error_t status = E_SUCCESS;
+    if (p_size == NULL)
+    {
+        status = E_INVALID_PARAM;
+    }
+    if (status == E_SUCCESS)
+    {
+        switch (algo_id)
+        {
+            case SHA_ALGO_ID_SHA_1:
+                *p_size = SHA_1_BLOCK_SIZE_BYTE;
+                break;
+
+            case SHA_ALGO_ID_SHA_224:
+                *p_size = SHA_224_BLOCK_SIZE_BYTE;
+                break;
+
+            case SHA_ALGO_ID_SHA_256:
+                *p_size = SHA_256_BLOCK_SIZE_BYTE;
+                break;
+
+            case SHA_ALGO_ID_SHA_384:
+                *p_size = SHA_384_BLOCK_SIZE_BYTE;
+                break;
+
+            case SHA_ALGO_ID_SHA_512:
+                *p_size = SHA_512_BLOCK_SIZE_BYTE;
+                break;
+
+            case SHA_ALGO_ID_SHA_512_224:
+                *p_size = SHA_512_224_BLOCK_SIZE_BYTE;
+                break;
+
+            case SHA_ALGO_ID_SHA_512_256:
+                *p_size = SHA_512_256_BLOCK_SIZE_BYTE;
+                break;
+
+            default:
+                status = E_INVALID_PARAM;
+                break;
+        }
+    }
+    return status;
+}
+
+/*!
+ * @brief Initilaize SHA operation.
+ *
+ * @param[in] p_sha_context The designated SHA context
+ *
+ * @return E_SUCCESS if initialization is successfuly; otherwise NVRV_ERR_SHA_XXX return.
+ *
+ * Please refer to 17. Programming Guidelines in SHA IAS to get more detail description.
+ */
+error_t
+sha_operation_init
+(
+    const SHA_CONTEXT      *p_sha_context
+)
+{
+    uint32_t reg;
+    uint32_t msg_size, i;
+    uint8_t  enc_mode = 0;
+    error_t status = E_SUCCESS;
+
+    if (p_sha_context == NULL)
+    {
+        status = E_INVALID_PARAM;
+    }
+    if (status == E_SUCCESS)
+    {
+        msg_size = p_sha_context->msg_size;
+
+        if (msg_size > SHA_MSG_BYTES_MAX)
+        {
+            status = E_INVALID_PARAM;
+        }
+    }
+    if (status == E_SUCCESS)
+    {
+        /* Issue HALT when SHA state is IDLE or HALTED will be dropped silently.
+         * So we only halt SHA engine when it's at busy state.
+         */
+        reg = local_read(NV_PRGNLCL_FALCON_SHA_STATUS);
+
+        if (FLD_TEST_DRF(_PRGNLCL, _FALCON_SHA, _STATUS_STATE, _BUSY, reg))
+        {
+            status = sha_wait_for_busy(SHA_ENGINE_HALT_TIMEOUT_NS);
+        }
+    }
+
+    if (status == E_SUCCESS)
+    {
+        status = sha_engine_soft_reset(SHA_ENGINE_SW_RESET_TIMEOUT_NS);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        status = sha_get_config_encode_mode(p_sha_context->algo_id, &enc_mode);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        reg = DRF_NUM(_PRGNLCL, _FALCON_SHA_CONFIG, _ENC_MODE, enc_mode) |
+                    DRF_DEF(_PRGNLCL, _FALCON_SHA_CONFIG, _ENC_ALG, _SHA) |
+                    DRF_DEF(_PRGNLCL, _FALCON_SHA_CONFIG, _DST, _HASH_REG);
+        local_write(NV_PRGNLCL_FALCON_SHA_CONFIG, reg);
+
+        /*
+         * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+         * SW reset should clear NV_CSEC_FALCON_SHA_MSG_LENGTH(i) and NV_CSEC_FALCON_SHA_MSG_LEFT(i)
+         * But we observed NV_CSEC_FALCON_SHA_MSG_LEFT(i) still has garbage values.
+         * So we still clear these all registers to make sure operation able to work correctly.
+         * !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+         *
+         * TODO: Reset SHA_HASH_RESULT registers after soft reset as these are not cleared by it.
+         *       Add bool arument to check for chaining tasks before clearing results.
+         *
+         */
+        for (i = 0; i < NV_PRGNLCL_FALCON_SHA_MSG_LENGTH__SIZE_1; i++)
+        {
+            local_write(NV_PRGNLCL_FALCON_SHA_MSG_LENGTH(i), 0);
+        }
+
+        for (i = 0; i < NV_PRGNLCL_FALCON_SHA_MSG_LEFT__SIZE_1; i++)
+        {
+            local_write(NV_PRGNLCL_FALCON_SHA_MSG_LEFT(i), 0);
+        }
+
+        /*
+         * In NIST spec, the MIN unit for SHA message is bit, but in real case, we just use byte unit.
+         * Although HW provide 4 registers for message length and left message length separately,
+         * but currently SW just uses one 32-bit register for SHA length(0x1FFFFFFF bytes)
+         * In real case usage, openSSL supports byte unit as well.
+         * And it should be enough for current requirement.
+         */
+
+        // Set bit length
+        local_write(NV_PRGNLCL_FALCON_SHA_MSG_LENGTH(0U), BYTE_TO_BIT_LENGTH(msg_size));
+    }
+    return status;
+}
+
+/*!
+ * @brief Insert SHA task configuration.
+ *
+ * @param[in] p_sha_context The designated SHA context
+ * @param[in] p_task_cfg The designated SHA task config
+ *
+ * @return E_SUCCESS if task config is inserted successfully; otherwise return NVRV_ERR_SHA_XXX.
+ *
+ * Please refer to 17. Programming Guidelines in SHA IAS to get more detail
+ *
+ */
+error_t
+sha_insert_task
+(
+    SHA_CONTEXT *p_sha_context,
+    const SHA_TASK_CONFIG *p_task_cfg
+)
+{
+    uint32_t reg, tmp;
+    SHA_ALGO_ID  algo_id;
+    error_t status = E_SUCCESS;
+    uint64_t msg_addr;
+    uint32_t left_msg_length = 0;
+
+    if ((p_sha_context == NULL) ||
+        (p_task_cfg == NULL))
+    {
+        status = E_INVALID_PARAM;
+    }
+    if (status == E_SUCCESS)
+    {
+        if (sha_task_config_is_valid(p_sha_context, p_task_cfg))
+        {
+            algo_id = p_sha_context->algo_id;
+            left_msg_length = p_sha_context->msg_size;
+        }
+        else
+        {
+            status = E_INVALID_PARAM;
+        }
+    }
+    if (status == E_SUCCESS)
+    {
+        status = sha_wait_engine_idle(SHA_ENGINE_IDLE_TIMEOUT_NS);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        // For each task, we need to set length for left message, bit unit.
+        local_write(NV_PRGNLCL_FALCON_SHA_MSG_LEFT(0U), BYTE_TO_BIT_LENGTH(left_msg_length));
+
+        //TODO: Add validation for all things from p_task_cfg!
+        // set source address
+        msg_addr = p_task_cfg->addr;
+        local_write(NV_PRGNLCL_FALCON_SHA_IN_ADDR , LOW32(msg_addr));
+
+        reg = DRF_NUM(_PRGNLCL, _FALCON_SHA_IN_ADDR_HI, _MSB, HI32(msg_addr)) |
+              DRF_NUM(_PRGNLCL, _FALCON_SHA_IN_ADDR_HI, _SZ, p_task_cfg->size);
+        local_write(NV_PRGNLCL_FALCON_SHA_IN_ADDR_HI, reg);
+
+
+        // Set source config
+        // TODO: Rename variables such as tmp to appropriate ones.
+        tmp = DRF_SIZE(NV_PRGNLCL_FALCON_SHA_IN_ADDR_HI_MSB);
+        tmp = (HI32(msg_addr)) >> tmp;
+        reg = DRF_NUM(_PRGNLCL, _FALCON_SHA_SRC_CONFIG, _FB_BASE, tmp) |
+              DRF_NUM(_PRGNLCL, _FALCON_SHA_SRC_CONFIG, _CTXDMA, p_task_cfg->dma_idx) |
+              DRF_NUM(_PRGNLCL, _FALCON_SHA_SRC_CONFIG, _SRC, p_task_cfg->src_type);
+        local_write(NV_PRGNLCL_FALCON_SHA_SRC_CONFIG , reg);
+
+        // Set task config
+        reg = 0;
+        if (p_task_cfg->b_default_hash_iv)
+        {
+            // sha512-224 sha512-256, SW needs to set initial vector.
+            if ((algo_id == SHA_ALGO_ID_SHA_512_224) ||
+                (algo_id == SHA_ALGO_ID_SHA_512_256))
+            {
+                sha_set_init_vector(algo_id);
+                reg = FLD_SET_DRF(_PRGNLCL_FALCON, _SHA_TASK_CONFIG, _HW_INIT_HASH, _DISABLE, reg);
+            }
+            else
+            {
+                reg = FLD_SET_DRF(_PRGNLCL_FALCON, _SHA_TASK_CONFIG, _HW_INIT_HASH, _ENABLE, reg);
+            }
+        }
+        else
+        {
+            reg = FLD_SET_DRF(_PRGNLCL_FALCON, _SHA_TASK_CONFIG, _HW_INIT_HASH, _DISABLE, reg);
+        }
+        local_write(NV_PRGNLCL_FALCON_SHA_TASK_CONFIG, reg);
+
+        // Trigger OP start
+        reg = 0;
+        reg = FLD_SET_DRF(_PRGNLCL_FALCON, _SHA_OPERATION, _LAST_BUF, _TRUE, reg);
+        reg = FLD_SET_DRF(_PRGNLCL_FALCON, _SHA_OPERATION, _OP, _START, reg);
+        local_write(NV_PRGNLCL_FALCON_SHA_OPERATION, reg);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        status = sha_wait_engine_idle(SHA_ENGINE_IDLE_TIMEOUT_NS);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        // Check if any error interrupt asserted
+        reg = local_read(NV_PRGNLCL_FALCON_SHA_ERR_STATUS);
+
+        if (reg == 0U)
+        {
+            // Use msg_size to track left message length.
+            p_sha_context->msg_size = left_msg_length - p_task_cfg->size;
+        }
+        else
+        {
+            status = E_SHA_ENG_ERROR;
+        }
+    }
+    return status;
+
+}
+
+/*!
+ * @brief Read SHA hash result.
+ *
+ * @param[in]  p_sha_context The designated SHA context
+ * @param[out] p_buf The output buffer to save computed SHA hash value
+ * @param[in]  buf_size The output buffer size.
+ * @param[in]  b_scrub_reg true to clear hash registers after hash is read out; false doesn't clear hash registers.
+ *
+ * @return E_SUCCESS if hash read successfully; otherwise return NVRV_ERR_SHA_XXX.
+ *
+ */
+error_t
+sha_read_hash_result
+(
+    const SHA_CONTEXT *p_sha_context,
+    bool b_scrub_reg
+)
+{
+    error_t        status = E_SUCCESS;
+    uint32_t       num_words = 0;
+    bool           b_double_word = false;
+
+    if (p_sha_context == NULL)
+    {
+        status = E_INVALID_PARAM;
+    }
+    else if (p_sha_context->p_buf_out == NULL)
+    {
+        status = E_INVALID_PARAM;
+    }
+    else
+    {
+        uint32_t hash_size_bytes, block_size_bytes;
+
+        // Format inputs
+        status = sha_get_hash_size_byte(p_sha_context->algo_id, &hash_size_bytes);
+        num_words = hash_size_bytes >> 2;
+        if (status == E_SUCCESS)
+        {
+            status = sha_get_block_size_byte(p_sha_context->algo_id, &block_size_bytes);
+        }
+        if (status == E_SUCCESS)
+        {
+            // SHA384 and up have 128B blocks. These algorithms all report results as double-words.
+            b_double_word = (block_size_bytes == SHA_384_BLOCK_SIZE_BYTE);
+            status = (p_sha_context->buf_size == hash_size_bytes) ? E_SUCCESS : E_INVALID_PARAM;
+        }
+    }
+
+    if (status == E_SUCCESS)
+    {
+        uint8_t* p_dest = p_sha_context->p_buf_out;
+        uint32_t index = 0;
+
+        for (uint32_t word = 0; word < num_words; word++)
+        {
+            if (b_double_word)
+            {
+                bool most_sig_word = (word & 1U) == 1U;
+                if (most_sig_word)
+                {
+                    INLINE_RFD(CERTC, FP, INT30_C, "Under Review: Bug TID-1900, DR: TODO")
+                    index = word - 1U;
+                }
+                else
+                {
+                    INLINE_RFD(CERTC, FP, INT30_C, "Under Review: Bug TID-1900, DR: TODO")
+                    index = word + 1U;
+                }
+            }
+            else
+            {
+                index = word;
+            }
+
+            status = sha_get_result_word(index, p_dest, b_scrub_reg);
+            if (status == E_SUCCESS)
+            {
+                p_dest = &p_dest[sizeof(uint32_t)];
+            }
+            else
+            {
+                break;
+            }
+        }
+    }
+    return status;
+}
+
+/*!
+ * @brief Run single task through SHA HW.
+ *
+ * @param[in] p_task_cfg The designated SHA task config
+ * @param[in] p_sha_ctx  The struct containing SHA task parameters and output buffer pointer.
+ *
+ * @return E_SUCCESS if hash read successfully; otherwise return NVRV_ERR_SHA_XXX.
+ *
+ */
+error_t sha_run_single_task_common
+(
+    const SHA_TASK_CONFIG *p_task_cfg,
+    SHA_CONTEXT     *p_sha_ctx
+)
+{
+    error_t status = E_SUCCESS;
+    bool has_mutex = false;
+
+    if ((p_task_cfg == NULL) || (p_sha_ctx == NULL))
+    {
+        status = E_INVALID_PARAM;
+    }
+    else if ((p_sha_ctx->msg_size == 0UL) ||
+            (p_sha_ctx->msg_size > SHA_MSG_BYTES_MAX) ||
+            (p_sha_ctx->p_buf_out == NULL) ||
+            (p_sha_ctx->mutex_token == 0UL) ||
+
+            // Only DMEM operations are supported in current SW driver. We can extend to IMEM/FB if necessary.
+            (p_task_cfg->src_type != NV_PRGNLCL_FALCON_SHA_SRC_CONFIG_SRC_DMEM) ||
+            ((p_task_cfg->size + p_task_cfg->addr) >= NV_RISCV_AMAP_DMEM_END) ||
+            ((p_task_cfg->size + p_task_cfg->addr) >= NV_RISCV_AMAP_DMEM_END) ||
+            (p_task_cfg->size == 0UL))
+    {
+        status = E_INVALID_PARAM;
+    }
+    else
+    {
+        status = sha_acquire_mutex(p_sha_ctx->mutex_token);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        has_mutex = true;
+    }
+
+    if (status == E_SUCCESS)
+    {
+        status = sha_operation_init(p_sha_ctx);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        status = sha_insert_task(p_sha_ctx, p_task_cfg);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        status = sha_read_hash_result(p_sha_ctx, true);
+    }
+
+    if (has_mutex)
+    {
+        status = sha_release_mutex(p_sha_ctx->mutex_token);
+    }
+    return status;
+}
+
+
+/*!
+ * @brief Initilaize SHA HW to start HMAC SHA-256 operation.
+ * @param[in] p_hmac_context The designated HMAC SHA-256 context
+ *
+ * @return E_SUCCESS if initialization is successfuly; otherwise NVRV_ERR_SHA_XXX return.
+ *
+ */
+error_t
+sha_hmac_operation_init
+(
+    HMAC_CONTEXT *p_hmac_context
+)
+{
+    error_t      status                        = E_SUCCESS;
+    uint32_t         loop_count                     = 0;
+    uint32_t         algo_block_size_byte             = 0;
+    SHA_CONTEXT      *p_sha_context                  = NULL;
+    SHA_TASK_CONFIG  task_cfg;
+    uint8_t          ipad[HMAC_SHA_MAX_BLOCK_SIZE_BYTE] = {0};
+
+    if (p_hmac_context == NULL)
+    {
+        status = E_INVALID_PARAM;
+    }
+    if (status == E_SUCCESS)
+    {
+        p_sha_context = &(p_hmac_context->sha_context);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        status = sha_get_block_size_byte(p_sha_context->algo_id, &algo_block_size_byte);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        // Ensure context is initialized and valid.
+        if ((p_sha_context->msg_size == 0U)                     ||
+            !sha_hmac_is_sha_algo_supported(p_sha_context->algo_id)||
+            (p_hmac_context->key_size > algo_block_size_byte)     ||
+            (p_hmac_context->key_size == 0U))
+        {
+            status = E_INVALID_PARAM;
+        }
+        else
+        {
+            /*
+             * Initialize first SHA session - first hash will be H(inner key || message).
+             * msg_size will be decremented by algo_hash_size_byte after call to sha_insert_task
+             */
+            p_sha_context->msg_size = p_sha_context->msg_size + algo_block_size_byte;
+        }
+    }
+
+    if (status == E_SUCCESS)
+    {
+        status = sha_operation_init(p_sha_context);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        // Generate inner key.
+        (void) memset(ipad, 0, algo_block_size_byte);
+        (void) memcpy(ipad, &(p_hmac_context->key_buffer), p_hmac_context->key_size);
+        for (loop_count = 0; loop_count < algo_block_size_byte; loop_count++)
+        {
+           ipad[loop_count] = ipad[loop_count] ^ HMAC_SHA_IPAD_MASK;
+        }
+
+        task_cfg.src_type        = NV_PRGNLCL_FALCON_SHA_SRC_CONFIG_SRC_DMEM;
+        task_cfg.b_default_hash_iv = true;
+        task_cfg.dma_idx         = 0;      // dma_idx is unused here since src_type is DMEM
+        task_cfg.size           = algo_block_size_byte;
+
+        task_cfg.addr           =  pointer_to_address(ipad);
+    }
+
+    // Add inner key to hash.
+    if (status == E_SUCCESS)
+    {
+        status = sha_insert_task(p_sha_context, &task_cfg);
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Insert HMAC-SHA-256 task configuration.
+ *       Task is basically plain textfor which Hash needs to be computed
+ *
+ * @param[in] p_hmac_context The designated HMAC SHA-256 context
+ * @param[in] p_task_cfg The designated SHA task config
+ *            p_task_cfg->b_default_hash_iv should always be set to NV_FALSE for HMAC computation
+ *            if not done then API itself forces it to NV_FALSE.
+ *
+ * @return E_SUCCESS if task config is inserted successfully; otherwise return NVRV_ERR_SHA_XXX.
+ */
+error_t
+sha_hmac_insert_task
+(
+    HMAC_CONTEXT    *p_hmac_context,
+    SHA_TASK_CONFIG *p_task_cfg
+)
+{
+    error_t status = E_SUCCESS;
+
+    if ((p_hmac_context == NULL) ||
+        (p_task_cfg == NULL) ||
+        (!sha_hmac_is_sha_algo_supported(p_hmac_context->sha_context.algo_id)))
+    {
+        status = E_INVALID_PARAM;
+    }
+    else
+    {
+        /*
+         * b_default_hash_iv is expected to be false since already SHA computation is begin in
+         * sha_hmac_operation_init where SHA(K xor ipad) is computed
+         * If this is set to true complete hash value gets modified hence forcing it to false
+         */
+        p_task_cfg->b_default_hash_iv = false;
+    }
+
+    if (status == E_SUCCESS)
+    {
+        status = sha_insert_task(&(p_hmac_context->sha_context), p_task_cfg);
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Read HMAC-SHA result
+ *        This API concludes the HMAC-SHA operation and reads out Hash result in output buffer.
+ * @param[in] p_hmac_context The designated HMAC SHA context
+ * @return E_SUCCESS if task config is inserted successfully; otherwise return NVRV_ERR_SHA_XXX.
+ */
+error_t
+sha_hmac_read_hash_result
+(
+    const HMAC_CONTEXT *p_hmac_context
+)
+{
+    error_t         status                                    = E_SUCCESS;
+    uint32_t        msg_size                                   = 0;
+    uint32_t        loop_count                                 = 0;
+    uint32_t        algo_block_size_byte                         = 0;
+    uint32_t        algo_hash_size_byte                          = 0;
+    const SHA_CONTEXT     *p_sha_context;
+    SHA_CONTEXT     temp_sha_context;
+    SHA_TASK_CONFIG task_cfg;
+    uint8_t         opad[HMAC_SHA_MAX_BLOCK_SIZE_BYTE]        = {0};
+    uint8_t        inner_digest[HMAC_SHA_MAX_HASH_SIZE_BYTE]  = {0};
+
+    if (p_hmac_context == NULL)
+    {
+        status = E_INVALID_PARAM;
+    }
+    else
+    {
+        p_sha_context = &(p_hmac_context->sha_context);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        status = sha_get_block_size_byte(p_sha_context->algo_id , &algo_block_size_byte);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        // Ensure context is initialized and valid.
+        if (!sha_hmac_is_sha_algo_supported(p_sha_context->algo_id)       ||
+            (p_hmac_context->key_size > algo_block_size_byte)              ||
+            (p_hmac_context->key_size == 0U))
+        {
+            status = E_INVALID_PARAM;
+        }
+        else
+        {
+            temp_sha_context           = p_hmac_context->sha_context;
+            temp_sha_context.p_buf_out = inner_digest;
+        }
+    }
+
+    if (status == E_SUCCESS)
+    {
+        status = sha_read_hash_result(&temp_sha_context, true);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        // Generate outer key.
+        (void) memset(opad, 0, algo_block_size_byte);
+        (void) memcpy(opad, &(p_hmac_context->key_buffer), p_hmac_context->key_size);
+        for (loop_count = 0; loop_count < algo_block_size_byte; loop_count++)
+        {
+           opad[loop_count] = opad[loop_count] ^ HMAC_SHA_OPAD_MASK;
+        }
+    }
+
+    // Initialize new SHA session for H(outer key || H(inner key || message)).
+    if (status == E_SUCCESS)
+    {
+        status = sha_get_hash_size_byte(p_sha_context->algo_id, &algo_hash_size_byte);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        msg_size = algo_block_size_byte + algo_hash_size_byte;
+
+        temp_sha_context.msg_size = msg_size;
+    }
+
+    if (status == E_SUCCESS)
+    {
+        status = sha_operation_init(&temp_sha_context);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        task_cfg.src_type        = NV_PRGNLCL_FALCON_SHA_SRC_CONFIG_SRC_DMEM;
+        task_cfg.b_default_hash_iv = true;
+        task_cfg.dma_idx         = 0;      // dma_idx is unused here since src_type is DMEM
+        task_cfg.size           = algo_block_size_byte;
+
+        task_cfg.addr           = pointer_to_address(opad);
+    }
+
+    // Add outer key to hash, ensuring we use default IV.
+    if (status == E_SUCCESS)
+    {
+        status = sha_insert_task(&temp_sha_context, &task_cfg);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        task_cfg.src_type        = NV_PRGNLCL_FALCON_SHA_SRC_CONFIG_SRC_DMEM;
+        task_cfg.b_default_hash_iv = false;
+        task_cfg.dma_idx         = 0;      // dma_idx is unused here since src_type is DMEM
+        task_cfg.size           = algo_hash_size_byte;
+
+        task_cfg.addr           = pointer_to_address(inner_digest);
+    }
+
+    // Add H(inner key || message) to digest, resulting in HMAC.
+    if (status == E_SUCCESS)
+    {
+        status = sha_insert_task(&temp_sha_context, &task_cfg);
+    }
+
+    // Output HMAC.
+    if (status == E_SUCCESS)
+    {
+        status = sha_read_hash_result(p_sha_context, true);
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Run single task through HMAC-SHA.
+ *        When application has the complete plain text data then this API can be used
+ *        This will compute Hash for plain text as well as return the result in output buffer of task_cfg.
+ *
+ * @param[in] p_hmac_context The struct containing HMAC SHA task parameters and output buffer pointer.
+ * @param[in] p_task_cfg     The designated HMAC SHA task config
+ *            p_task_cfg->b_default_hash_iv should always be set to NV_FALSE for HMAC computation
+ *            if not done then API itself forces it to NV_FALSE.
+ *
+ * @return E_SUCCESS if hash read successfully; otherwise return NVRV_ERR_SHA_XXX.
+ */
+error_t sha_hmac_run_single_task_common
+(
+    HMAC_CONTEXT *p_hmac_context,
+    SHA_TASK_CONFIG *p_task_cfg
+)
+{
+    error_t status = E_SUCCESS;
+    bool has_mutex = false;
+
+    if ((p_task_cfg == NULL) || (p_hmac_context == NULL))
+    {
+        status = E_INVALID_PARAM;
+    }
+    else if ((p_hmac_context->sha_context.msg_size == 0U) ||
+            (p_hmac_context->sha_context.msg_size > SHA_MSG_BYTES_MAX) ||
+            (p_hmac_context->sha_context.p_buf_out == NULL) ||
+            (p_hmac_context->sha_context.mutex_token == 0U) ||
+
+            // Only DMEM operations are supported in current SW driver. We can extend to IMEM/FB if necessary.
+            (p_task_cfg->src_type != NV_PRGNLCL_FALCON_SHA_SRC_CONFIG_SRC_DMEM) ||
+            ((p_task_cfg->size + p_task_cfg->addr) >= NV_RISCV_AMAP_DMEM_END) ||
+            ((p_task_cfg->size + p_task_cfg->addr) >= NV_RISCV_AMAP_DMEM_END) ||
+            (p_task_cfg->size  == 0U))
+    {
+        status = E_INVALID_PARAM;
+    }
+    else
+    {
+        status = sha_acquire_mutex(p_hmac_context->sha_context.mutex_token);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        has_mutex = true;
+    }
+
+    if (status == E_SUCCESS)
+    {
+        status = sha_hmac_operation_init(p_hmac_context);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        status = sha_hmac_insert_task(p_hmac_context, p_task_cfg);
+    }
+
+    if (status == E_SUCCESS)
+    {
+        status = sha_hmac_read_hash_result(p_hmac_context);
+    }
+
+    if (has_mutex)
+    {
+        status = sha_release_mutex(p_hmac_context->sha_context.mutex_token);
+    }
+
+    return status;
+}
+
+
+/**********************************
+* Private Function Definition
+**********************************/
+
+
+/*!
+ * @brief To set initial vector for SHA-512-224 and SHA-512-256.
+ *
+ * @param[in] algo_id The SHA algorithm id.
+ *
+ */
+static void
+sha_set_init_vector
+(
+    SHA_ALGO_ID algo_id
+)
+{
+    size_t arr_len = 0;
+    static const uint32_t sha_512_224_iv[16] = {
+        0x19544DA2, 0x8C3D37C8, 0x89DCD4D6, 0x73E19966,
+        0x32FF9C82, 0x1DFAB7AE, 0x582F9FCF, 0x679DD514,
+        0x7BD44DA8, 0x0F6D2B69, 0x04C48942, 0x77E36F73,
+        0x6A1D36C8, 0x3F9D85A8, 0x91D692A1, 0x1112E6AD
+    };
+
+    static const uint32_t sha_512_256_iv[16] = {
+        0xFC2BF72C, 0x22312194, 0xC84C64C2, 0x9F555FA3,
+        0x6F53B151, 0x2393B86B, 0x5940EABD, 0x96387719,
+        0xA88EFFE3, 0x96283EE2, 0x53863992, 0xBE5E1E25,
+        0x2C85B8AA, 0x2B0199FC, 0x81C52CA2, 0x0EB72DDC
+    };
+
+    if (algo_id == SHA_ALGO_ID_SHA_512_224)
+    {
+        arr_len = sizeof(sha_512_224_iv)/sizeof(sha_512_224_iv[0]);
+        for (size_t i = 0; i < arr_len; i++)
+        {
+            local_write(LOW32(NV_PRGNLCL_FALCON_SHA_HASH_RESULT(i)), sha_512_224_iv[i]);
+        }
+    }
+    else // algo_id == SHA_ALGO_ID_SHA_512_256
+    {
+        arr_len = sizeof(sha_512_256_iv)/sizeof(sha_512_256_iv[0]);
+        for(size_t i = 0; i < arr_len; i++)
+        {
+            local_write(LOW32(NV_PRGNLCL_FALCON_SHA_HASH_RESULT(i)), sha_512_256_iv[i]);
+        }
+    }
+}
+
+/*!
+ * @brief To check SHA task configuration.
+ *
+ * @param[in] p_sha_context The designated SHA context
+ * @param[in] p_task_cfg The designated SHA task config
+ *
+ * @return true if task config is valid; otherwise return false.
+ *
+ */
+static bool
+sha_task_config_is_valid
+(
+    const SHA_CONTEXT *p_sha_context,
+    const SHA_TASK_CONFIG *p_task_cfg
+)
+{
+    bool b_valid = true;
+
+    /*
+     * We use p_sha_context->msg_size to track left message length.
+     * Once left message size is less(or equal to) than inserted task size,
+     * This means this is the last task. Only the last task size doesn't
+     * have to be aligned with block size.
+     */
+    if (p_sha_context->msg_size == p_task_cfg->size)
+    {
+        b_valid = true;
+    }
+
+    else if (p_sha_context->msg_size < p_task_cfg->size)
+    {
+        b_valid = false;
+    }
+    else
+    {
+        switch (p_sha_context->algo_id)
+        {
+            case SHA_ALGO_ID_SHA_1:
+            case SHA_ALGO_ID_SHA_224:
+            case SHA_ALGO_ID_SHA_256:
+                b_valid = NV_IS_ALIGNED(p_task_cfg->size, SHA_256_BLOCK_SIZE_BYTE);
+            break;
+
+            case SHA_ALGO_ID_SHA_384:
+            case SHA_ALGO_ID_SHA_512:
+            case SHA_ALGO_ID_SHA_512_224:
+            case SHA_ALGO_ID_SHA_512_256:
+                b_valid = NV_IS_ALIGNED(p_task_cfg->size, SHA_512_BLOCK_SIZE_BYTE);
+            break;
+
+            default:
+                b_valid = false;
+            break;
+        }
+    }
+    return b_valid;
+}
+
+/*
+ * @brief This function checks whether particular SHA_ALGO_ID is supported for HMAC computation.
+ * @param[in] algo_id SHA ALGO Id
+ *
+ * @return true if SHA_ALGO_ID is supported else false.
+ */
+static bool sha_hmac_is_sha_algo_supported
+(
+    SHA_ALGO_ID algo_id
+)
+{
+    bool supported;
+    switch (algo_id)
+    {
+        case SHA_ALGO_ID_SHA_256:
+        case SHA_ALGO_ID_SHA_384:
+        case SHA_ALGO_ID_SHA_512:
+            supported = true;
+            break;
+        default:
+            supported = false;
+            break;
+    }
+    return supported;
+}
+
+/*!
+ * @brief Wait for SHA engine idle
+ *
+ * @param[in] time_out_ns Timeout initialization value
+ *
+ * @return E_SUCCESS if engine enter idle state successfuly.
+ *         E_SHA_ENG_ERROR if SHA halted status asserted
+ *         E_SHA_WAIT_IDLE_TIMEOUT if timeout detected
+ */
+static error_t
+sha_wait_for_busy
+(
+    uint64_t time_out_ns
+)
+{
+    uint32_t    reg;
+    uint64_t    start_time;
+    error_t     status = E_SUCCESS;
+
+    start_time = ptimer_read();
+
+    do
+    {
+        reg = local_read(NV_PRGNLCL_FALCON_SHA_STATUS);
+
+        if (timeout_is_hit(start_time, time_out_ns))
+        {
+            status = E_SHA_WAIT_IDLE_TIMEOUT;
+            break;
+        }
+    } while (FLD_TEST_DRF(_PRGNLCL, _FALCON_SHA, _STATUS_STATE, _BUSY, reg));
+
+    return status;
+}
+
+/*!
+ * @brief Wait for SHA engine idle
+ *
+ * @param[in] time_out_ns Timeout initialization value
+ *
+ * @return E_SUCCESS if engine enter idle state successfuly.
+ *         E_SHA_ENG_ERROR if SHA halted status asserted
+ *         E_SHA_WAIT_IDLE_TIMEOUT if timeout detected
+ */
+static error_t
+sha_wait_engine_idle
+(
+    uint64_t time_out_ns
+)
+{
+    uint32_t    reg;
+    uint64_t    start_time;
+    error_t     status = E_SUCCESS;
+
+    start_time = ptimer_read();
+
+    do
+    {
+        reg = local_read(NV_PRGNLCL_FALCON_SHA_STATUS);
+        if (FLD_TEST_DRF(_PRGNLCL, _FALCON_SHA, _STATUS_STATE, _HALTED, reg))
+        {
+            status = E_SHA_ENG_ERROR;
+        }
+        if (timeout_is_hit(start_time, time_out_ns) && (status == E_SUCCESS))
+        {
+            status = E_SHA_WAIT_IDLE_TIMEOUT;
+        }
+        if(status != E_SUCCESS)
+        {
+            break;
+        }
+    } while (FLD_TEST_DRF(_PRGNLCL, _FALCON_SHA, _STATUS_STATE, _BUSY, reg));
+
+    return status;
+}
+
+/*!
+ * @brief Execute SHA engine soft reset and wait for engine idle
+ *
+ * @param[in] time_out_ns Timeout initialization value
+ *
+ * @return E_SUCCESS if reset and enter idle state successfuly.
+           E_SHA_WAIT_IDLE_TIMEOUT/SW_RESET_TIMEOUT if timeout detected
+ *
+ */
+static error_t
+sha_engine_soft_reset
+(
+    uint64_t time_out_ns
+)
+{
+    uint32_t    reg;
+    uint64_t    start_time = 0;
+    error_t status = E_SUCCESS;
+
+    reg = local_read(NV_PRGNLCL_FALCON_SHA_STATUS);
+
+    if (FLD_TEST_DRF(_PRGNLCL, _FALCON_SHA, _STATUS_STATE, _BUSY, reg))
+    {
+        status = sha_engine_halt();
+    }
+
+    if (status == E_SUCCESS)
+    {
+        reg = FLD_SET_DRF(_PRGNLCL_FALCON, _SHA_OPERATION, _SOFTRESET, _ENABLE, reg);
+        local_write(NV_PRGNLCL_FALCON_SHA_OPERATION, reg);
+
+        start_time = ptimer_read();
+
+        // wait for soft reset clear
+        do
+        {
+            reg = local_read(NV_PRGNLCL_FALCON_SHA_OPERATION);
+
+            if (timeout_is_hit(start_time, time_out_ns))
+            {
+                status = E_SHA_SW_RESET_TIMEOUT;
+                break;
+            }
+        } while (FLD_TEST_DRF(_PRGNLCL_FALCON, _SHA_OPERATION, _SOFTRESET, _ENABLE, reg));
+    }
+
+    if (status == E_SUCCESS)
+    {
+        status = sha_wait_engine_idle(SHA_ENGINE_IDLE_TIMEOUT_NS);
+    }
+
+    return status;
+}
+
+/*!
+ * @brief To get SHA encode value per SHA algorithm id
+ *
+ * @param[in]  algo_id SHA algorithm id
+ * @param[out] *p_mode The pointer to save encode value
+ *
+ * @return E_SUCCESS if get encode value successfully.
+ *         E_INVALID_PARAM if failed.
+ *
+ */
+static error_t
+sha_get_config_encode_mode
+(
+    SHA_ALGO_ID algo_id,
+    uint8_t     *p_mode
+)
+{
+    error_t status = E_SUCCESS;
+    switch (algo_id)
+    {
+        case SHA_ALGO_ID_SHA_1:
+            *p_mode = NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_MODE_SHA1;
+            break;
+        case SHA_ALGO_ID_SHA_224:
+            *p_mode = NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_MODE_SHA224;
+            break;
+        case SHA_ALGO_ID_SHA_256:
+            *p_mode = NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_MODE_SHA256;
+            break;
+        case SHA_ALGO_ID_SHA_384:
+            *p_mode = NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_MODE_SHA384;
+            break;
+        case SHA_ALGO_ID_SHA_512:
+            *p_mode = NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_MODE_SHA512;
+            break;
+        case SHA_ALGO_ID_SHA_512_224:
+            *p_mode = NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_MODE_SHA512_224;
+            break;
+        case SHA_ALGO_ID_SHA_512_256:
+            *p_mode = NV_PRGNLCL_FALCON_SHA_CONFIG_ENC_MODE_SHA512_256;
+            break;
+        default:
+            status = E_INVALID_PARAM;
+            break;
+    }
+
+    return status;
+}
+
+/*!
+ * @brief Convert a pointer to a uint64_t so that it can be passed as 64b address to sha engine
+ *        indicating location of data to hash.
+ *
+ * @param[in]  buf               pointer to buffer/data to hash
+ *
+ * @return uint64_t
+ *
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "TODO: The need for this deviation will be removed when COREUCODES-2066 is resolved")
+static inline uint64_t pointer_to_address(uint8_t* buf)
+{
+    INLINE_RFD(MISRA, DEVIATE, Rule_11_4, "TODO: The need for this deviation will be removed when COREUCODES-2066 is resolved")
+    return (uint64_t) buf;
+}
+
+/*!
+ * @brief Identify if a timeout has been hit (accounting for integer overflow)
+ *
+ * @param[in]  start_time        start time of operation
+ * @param[in]  timeout           max duration to wait before timeout
+ *
+ * @return E_SUCCESS if fetch configuration can be set correctly; otherwise return E_INVALID_PARAM.
+ *
+ */
+static inline bool timeout_is_hit(uint64_t start_time, uint64_t timeout)
+{
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Under Review: Bug TID-1899, DR: TODO")
+    return (ptimer_read() - start_time) > timeout;
+}
+
+/*!
+ * @brief Get Hash Result. Guard against illegal reads.
+ *
+ * @param[in]  register_index   register to read from [0,SHA_MAX_RESULT_REGISTER]
+ * @param[out] result           buffer to write result into
+ * @param[in]  b_scrub_reg      scrub (zero) hash result after read if true
+ *
+ * @return E_SUCCESS if read is valid, E_INVALID_PARAM otherwise
+ *
+ */
+static inline error_t sha_get_result_word(uint32_t register_index, uint8_t* result, bool b_scrub_reg)
+{
+    error_t status = E_SUCCESS;
+    if((result == NULL) || (register_index > NV_PRGNLCL_FALCON_SHA_HASH_RESULT__SIZE_1))
+    {
+        status = E_INVALID_PARAM; // Unreachable due to input formatting in sha_read_hash_result
+    }
+    else
+    {
+        INLINE_RFD(CERTC, FP, INT30_C, "Under Review: Bug TID-1901, DR: TODO")
+        uint32_t reg = NV_PRGNLCL_FALCON_SHA_HASH_RESULT(register_index);
+        uint32_t hash = local_read(reg);
+        hash = NV_BYTESWAP32(hash);
+        (void) memcpy(result, (uint8_t*) &hash, sizeof(hash));
+        if(b_scrub_reg)
+        {
+            local_write(reg, 0);
+        }
+    }
+    return status;
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_7, "Approval: TODO, DR: TODO")
+
+
+/*** end of file ***/
diff --git a/spe-freertos-bsp/fsp/source/drivers/spi-mst/module-spi-mst-nosafety-config.mk b/spe-freertos-bsp/fsp/source/drivers/spi-mst/module-spi-mst-nosafety-config.mk
new file mode 100644
index 0000000..d2f471b
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/spi-mst/module-spi-mst-nosafety-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-spi-mst-config-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-osa*.mk' files.
+MODULE_SPI_MST_NOSAFETY_CONFIG          := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_SPI_MST_NOSAFETY_DEPENDS         := SOC CLUSTER CPL FSP_COMMON
+$(foreach _,$(MODULE_SPI_MST_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_SPI_MST_NOSAFETY_DRIVERS_DIR      = $(FSP_COMMON_REPO)/drivers/spi-mst
+MODULE_SPI_MST_NOSAFETY_SOURCE_DIR       = $(MODULE_SPI_MST_NOSAFETY_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_SPI_MST_NOSAFETY_INCLUDES         =
diff --git a/spe-freertos-bsp/fsp/source/drivers/spi-mst/module-spi-mst-nosafety.mk b/spe-freertos-bsp/fsp/source/drivers/spi-mst/module-spi-mst-nosafety.mk
new file mode 100644
index 0000000..c0ad833
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/spi-mst/module-spi-mst-nosafety.mk
@@ -0,0 +1,68 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-spi-mst-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_SPI_MST_NOSAFETY_NAME            := SPI_MST_NOSAFETY
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_SPI_MST_NOSAFETY_DEFINED         := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_SPI_MST_NOSAFETY_DEPENDS         := SPI_MST_NOSAFETY SOC CPL
+$(foreach _,$(CONFIG_SPI_MST_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_SPI_MST_NOSAFETY_C_SRC            =
+MODULE_SPI_MST_NOSAFETY_C_SRC           += $(MODULE_SPI_MST_NOSAFETY_DRIVERS_DIR)/spi.c
+MODULE_SPI_MST_NOSAFETY_C_SRC           += $(CPL_SOC_IDS)/spi-ids.c
+
+#
+# If the client module does not need 'spi-port.c' use this MAKEFILE flag to
+# ignore it.
+MODULE_SPI_MST_NOSAFETY_C_SRC           += $(CPL_SOC_IDS)/spi-port.c
+
+#
+# Assembly source
+MODULE_SPI_MST_NOSAFETY_ASM_SRC          =
+
+#
+# Special C Flags
+MODULE_SPI_MST_NOSAFETY_C_FLAGS          =
+
+#
+# Special ASM Flags
+MODULE_SPI_MST_NOSAFETY_ASM_FLAGS        =
diff --git a/spe-freertos-bsp/fsp/source/drivers/spi-mst/spi.c b/spe-freertos-bsp/fsp/source/drivers/spi-mst/spi.c
new file mode 100644
index 0000000..dab7a8f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/spi-mst/spi.c
@@ -0,0 +1,1201 @@
+/*
+ * Copyright (c) 2015-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                   // for bool
+#include <stdint.h>                    // for uint32_t, uint8_t, UINT32_...
+#include <stddef.h>                    // for NULL
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>            // for CT_ASSERT
+#include <soc-common/hw-const.h>       // IWYU pragma: keep
+
+/* Hardware headers */
+#include <arspi.h>
+
+/* Late FSP headers */
+#include <misc/nvrm_drf.h>             // NV_DRF_* macros
+#include <cpu/type-conversion.h>       // for fsp_c_v_ptr_to_u32
+#include <error/common-errors.h>       // for error_t, E_SUCCESS
+#include <misc/attributes.h>           // for UNUSED
+#include <irq/safe-irqs.h>             // for in_interrupt, irq_enable, irq_set...
+#include <misc/bitops.h>               // for BIT, bit_number, FSP__MISC__BITOPS_H
+#include <misc/macros.h>               // for ARRAY_SIZE
+#include <reg-access/reg-access.h>     // for readl_base_offset, writel_base_of...
+#include <delay/delay.h>               // for udelay
+#include <processor/cache-hw.h>        // for CACHE_LINE_SIZE...
+
+/* Module specific headers */
+#include <spi/spi-errors.h>            // for E_SPI_NULL_PTR, E_SPI_...
+#include <spi/spi.h>                   // for spi_init...
+#include <spi/sections-spi.h>          // Immune from CT_ASSERT protection
+#include <spi/spi-priv.h>              // for struct spi_ctlr, spi_ctrl...
+#include <spi/spi-port.h>              // for spi_port_...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__TYPE_CONVERSION_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DELAY__DELAY_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SPI__SPI_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SPI__SPI_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SPI__SPI_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SPI__SPI_PORT_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+#define SPI_ERR             (NV_DRF_DEF(SPI, FIFO_STATUS, ERR, ERROR))
+#define SPI_FIFO_ERROR      (NV_DRF_DEF(SPI, FIFO_STATUS, RX_FIFO_UNF, \
+                                 ERROR) | \
+                             NV_DRF_DEF(SPI, FIFO_STATUS, RX_FIFO_OVF, \
+                                 ERROR) | \
+                             NV_DRF_DEF(SPI, FIFO_STATUS, TX_FIFO_UNF, \
+                                 ERROR) | \
+                             NV_DRF_DEF(SPI, FIFO_STATUS, RX_FIFO_OVF, \
+                                 ERROR))
+#define SPI_FIFO_EMPTY      (NV_DRF_DEF(SPI, FIFO_STATUS, RX_FIFO_EMPTY, \
+                                 EMPTY) | \
+                             NV_DRF_DEF(SPI, FIFO_STATUS, TX_FIFO_EMPTY, \
+                                 EMPTY))
+
+#define SPI_FIFO_DEPTH              64U
+#define DATA_DIR_TX                 BIT(0)
+#define DATA_DIR_RX                 BIT(1)
+
+#define SPI_FIFO_FLUSH_MAX_DELAY    2000UL  /* usec */
+
+#define SPI_SPEED_TAP_DELAY_MARGIN  35000000UL  /* usec */
+#define SPI_DEFAULT_RX_TAP_DELAY    10U  /* usec */
+
+#define SPI_TRANSFER_TIMEOUT        3000UL /* usec */
+
+static inline uint32_t
+spi_readl(struct spi_ctlr *ctlr,
+                uint32_t reg)
+{
+    return readl(ctlr->conf.base_addr + reg);
+}
+
+static inline void
+spi_writel(struct spi_ctlr *ctlr,
+                 uint32_t val,
+                 uint32_t reg)
+{
+    writel(val, ctlr->conf.base_addr + reg);
+}
+
+SECTION_SPI_TEXT static void
+handle_xfer_err(struct spi_ctlr *ctlr)
+{
+    uint32_t errs = 0UL;
+
+    if ((ctlr->cur_direction & DATA_DIR_TX) && (ctlr->tx_status)) {
+        errs += 1UL;
+    }
+
+    if ((ctlr->cur_direction & DATA_DIR_RX) && (ctlr->rx_status)) {
+        errs += 2UL;
+    }
+
+    if (errs != 0UL) {
+        spi_port_clk_reset_pulse(ctlr, 2);
+    }
+}
+
+SECTION_SPI_TEXT static void
+spi_clear_status(struct spi_ctlr *ctlr)
+{
+    uint32_t val;
+
+    /* Write 1 to clear status register */
+    val = spi_readl(ctlr, SPI_TRANSFER_STATUS_0);
+    spi_writel(ctlr, val, SPI_TRANSFER_STATUS_0);
+
+    val = spi_readl(ctlr, SPI_INTR_MASK_0);
+    if ((val & NV_DRF_DEF(SPI, INTR_MASK, RDY_INTR_MASK, DEFAULT_MASK)) == 0UL) {
+        val |= (NV_DRF_DEF(SPI, INTR_MASK, RDY_INTR_MASK, DEFAULT_MASK) |
+                NV_DRF_DEF(SPI, INTR_MASK, RX_FIFO_UNF_INTR_MASK,
+                           DEFAULT_MASK) |
+                NV_DRF_DEF(SPI, INTR_MASK, TX_FIFO_UNF_INTR_MASK,
+                           DEFAULT_MASK) |
+                NV_DRF_DEF(SPI, INTR_MASK, RX_FIFO_OVF_INTR_MASK,
+                           DEFAULT_MASK) |
+                NV_DRF_DEF(SPI, INTR_MASK, TX_FIFO_OVF_INTR_MASK,
+                           DEFAULT_MASK));
+        spi_writel(ctlr, val, SPI_INTR_MASK_0);
+    }
+
+    /* Clear FIFO status error if any */
+    val = spi_readl(ctlr, SPI_FIFO_STATUS_0);
+    if (val & SPI_ERR) {
+        spi_writel(ctlr, SPI_ERR | SPI_FIFO_ERROR, SPI_FIFO_STATUS_0);
+    }
+}
+
+SECTION_SPI_TEXT void
+spi_master_isr(void *data)
+{
+    struct spi_ctlr *ctlr = (struct spi_ctlr *)data;
+    uint32_t        cmd1;
+    bool            isr_yield_flag = false;
+
+    cmd1 = spi_readl(ctlr, SPI_COMMAND_0);
+    ctlr->status_reg = spi_readl(ctlr, SPI_FIFO_STATUS_0);
+
+    if ((cmd1 & NV_DRF_DEF(SPI, COMMAND, Tx_EN, ENABLE)) != 0UL) {
+        ctlr->tx_status = ctlr->status_reg &
+                          (NV_DRF_DEF(SPI, FIFO_STATUS, TX_FIFO_UNF, ERROR) |
+                           NV_DRF_DEF(SPI, FIFO_STATUS, TX_FIFO_OVF, ERROR));
+    }
+
+    if ((cmd1 & NV_DRF_DEF(SPI, COMMAND, Rx_EN, ENABLE)) != 0UL) {
+        ctlr->rx_status = ctlr->status_reg &
+                          (NV_DRF_DEF(SPI, FIFO_STATUS, RX_FIFO_UNF, ERROR) |
+                           NV_DRF_DEF(SPI, FIFO_STATUS, RX_FIFO_OVF, ERROR));
+    }
+
+    spi_clear_status(ctlr);
+
+    if (((cmd1 & NV_DRF_DEF(SPI, COMMAND, Tx_EN, ENABLE)) == 0UL) &&
+            ((cmd1 & NV_DRF_DEF(SPI, COMMAND, Rx_EN, ENABLE)) == 0UL)) {
+            /* SPI: spurious interrupt */
+        goto out;
+    }
+
+    handle_xfer_err(ctlr);
+
+    UNUSED((spi_port_xfer_sync_end(ctlr)));
+
+out:
+    spi_port_isr_exit(ctlr, isr_yield_flag);
+}
+
+static uint32_t
+spi_calculate_curr_xfer_param(struct spi_ctlr *ctlr,
+                              struct spi_xfer *xfer)
+{
+    uint32_t remain_len = xfer->len - ctlr->cur_pos;
+    uint32_t max_word;
+    uint32_t max_len;
+    uint32_t total_fifo_words;
+    bool     spi_no_dma = ctlr->cdata[xfer->chip_select].spi_no_dma;
+
+    ctlr->bytes_per_word = (xfer->bits_per_word - 1) / 8 + 1;
+
+    /*
+     * SPI transfer length should be multiple of SPI word size
+     * where SPI word size should be power-of-two multiple
+     */
+    if (ctlr->bytes_per_word == 3) {
+        ctlr->bytes_per_word = 4;
+    }
+
+    if ((xfer->bits_per_word == 8 || xfer->bits_per_word == 16 ||
+            xfer->bits_per_word == 32) && (remain_len > 3)) {
+        ctlr->is_packed = 1;
+        ctlr->words_per_32bit = 32 / xfer->bits_per_word;
+    } else {
+        ctlr->is_packed = 0;
+        ctlr->words_per_32bit = 1;
+    }
+
+    if (ctlr->is_packed) {
+        max_len = remain_len;
+        if (spi_no_dma) {
+            max_len = min(max_len, (SPI_FIFO_DEPTH * 4));
+        }
+        ctlr->curr_dma_words = max_len / ctlr->bytes_per_word;
+        total_fifo_words = (max_len + 3) / 4;
+    } else {
+        max_word = (remain_len - 1) / ctlr->bytes_per_word + 1;
+        if (spi_no_dma) {
+            max_word = min(max_word, SPI_FIFO_DEPTH);
+        }
+        ctlr->curr_dma_words = max_word;
+        total_fifo_words = max_word;
+    }
+
+    return total_fifo_words;
+}
+
+static uint32_t
+spi_fill_tx_fifo_from_client_txbuf(struct spi_ctlr *ctlr,
+                                   struct spi_xfer *xfer)
+{
+    uint32_t nbytes;
+    uint32_t tx_empty_count;
+    uint32_t fifo_status;
+    uint32_t max_n_32bit;
+    uint32_t i, count, byte_count;
+    uint32_t x;
+    uint32_t written_words;
+    uint32_t fifo_words_left;
+    uint8_t *tx_buf = (uint8_t *)xfer->tx_buf + ctlr->cur_tx_pos;
+
+    fifo_status = spi_readl(ctlr, SPI_FIFO_STATUS_0);
+    tx_empty_count = NV_DRF_VAL(SPI, FIFO_STATUS, TX_FIFO_EMPTY_COUNT,
+                                fifo_status);
+
+    if (ctlr->is_packed) {
+        fifo_words_left = tx_empty_count * ctlr->words_per_32bit;
+        written_words = min(fifo_words_left, ctlr->curr_dma_words);
+        nbytes = written_words * ctlr->bytes_per_word;
+        max_n_32bit = DIV_ROUND_UP(nbytes, 4);
+        byte_count = 4UL;
+    } else {
+        max_n_32bit = min(ctlr->curr_dma_words, tx_empty_count);
+        written_words = max_n_32bit;
+        nbytes = written_words * ctlr->bytes_per_word;
+        byte_count = ctlr->bytes_per_word;
+    }
+
+    for (count = 0UL; count < max_n_32bit; count++) {
+        x = 0UL;
+        for (i = 0UL; (i < byte_count) && nbytes; i += 1UL, nbytes -= 1UL) {
+            x |= ((*tx_buf++) << (i * 8));
+        }
+        spi_writel(ctlr, x, SPI_TX_FIFO_0);
+    }
+
+    ctlr->cur_tx_pos += written_words * ctlr->bytes_per_word;
+
+    return written_words;
+}
+
+static uint32_t
+spi_read_rx_fifo_to_client_rxbuf(struct spi_ctlr *ctlr,
+                                 struct spi_xfer *xfer)
+{
+    uint32_t rx_full_count;
+    uint32_t fifo_status;
+    uint32_t i, count;
+    uint32_t x;
+    uint32_t read_words = 0;
+    uint32_t len;
+    uint8_t  *rx_buf = (uint8_t *)xfer->rx_buf + ctlr->cur_rx_pos;
+
+    fifo_status = spi_readl(ctlr, SPI_FIFO_STATUS_0);
+    rx_full_count = NV_DRF_VAL(SPI, FIFO_STATUS, RX_FIFO_FULL_COUNT,
+                               fifo_status);
+
+    if (ctlr->is_packed) {
+        len = ctlr->curr_dma_words * ctlr->bytes_per_word;
+        for (count = 0UL; count < rx_full_count; count++) {
+            x = spi_readl(ctlr, SPI_RX_FIFO_0);
+            for (i = 0UL; len && (i < 4UL); i += 1UL, len -= 1UL) {
+                *rx_buf++ = (x >> (i * 8U)) & 0xFFU;
+            }
+        }
+        ctlr->cur_rx_pos += ctlr->curr_dma_words * ctlr->bytes_per_word;
+        read_words += ctlr->curr_dma_words;
+    } else {
+        for (count = 0UL; count < rx_full_count; count++) {
+            x = spi_readl(ctlr, SPI_RX_FIFO_0);
+            for (i = 0UL; (i < ctlr->bytes_per_word); i += 1UL) {
+                *rx_buf++ = (x >> (i * 8U)) & 0xFFU;
+            }
+        }
+        ctlr->cur_rx_pos += rx_full_count * ctlr->bytes_per_word;
+        read_words += rx_full_count;
+    }
+
+    return read_words;
+}
+
+static void
+spi_copy_client_txbuf_to_spi_txbuf(struct spi_ctlr *ctlr,
+                                   struct spi_xfer *xfer)
+{
+    uint32_t i;
+    int32_t count;
+    uint32_t x;
+    uint32_t offset;
+    uint8_t *tx_c_buf;
+    uint32_t base;
+    uint32_t *tx_buf = (uint32_t *)((uint8_t *)xfer->tx_buf + ctlr->cur_tx_pos);
+    uint32_t nbytes = ctlr->curr_dma_words * ctlr->bytes_per_word;
+
+    if (!ctlr->is_packed) {
+        tx_c_buf = (uint8_t *)xfer->tx_buf + ctlr->cur_tx_pos +
+                        nbytes - 1;
+        /* curr_dma_words and fifo_words are same for unpacked mode */
+        for (count = ctlr->curr_dma_words - 1; count >= 0; count--) {
+            x = 0;
+            for (i = 0; nbytes && (i < ctlr->bytes_per_word);
+                        i++) {
+                offset = (--nbytes) % (ctlr->bytes_per_word);
+                x |= (*tx_c_buf--) << (offset * 8);
+            }
+            tx_buf[count] = x;
+        }
+        /**
+         * The following cache flush is needed only for unpacked mode
+         * as for packed mode you do not need to modify the tx buffer
+         */
+        if (xfer->flags & BIT(TEGRA_SPI_XFER_HANDLE_CACHE)) {
+            /**
+             * Align buffer address and length to cache line size
+             * and flush the cache
+             */
+            base = (uint32_t) xfer->tx_buf & CACHE_LINE_MASK;
+            spi_port_cache_clean((void *)base, (((ctlr->curr_dma_words * 4) +
+                                 (CACHE_LINE_SIZE - 1)) & CACHE_LINE_MASK));
+        }
+    }
+}
+
+static void
+spi_copy_spi_rxbuf_to_client_rxbuf(struct spi_ctlr *ctlr,
+                                   struct spi_xfer *xfer)
+{
+    uint32_t i;
+    uint32_t count;
+    uint32_t x;
+    uint32_t rx_mask;
+    uint32_t base;
+    uint32_t *rx_buf = (uint32_t *)((uint8_t *)xfer->rx_buf +
+                       ctlr->cur_rx_pos);
+    uint8_t  *rx_c_buf = (uint8_t *)xfer->rx_buf +
+                         ctlr->cur_rx_pos;
+
+    /**
+     * Align buffer address and length to cache line size
+     * and invalidate the cache
+     */
+    if (xfer->flags & BIT(TEGRA_SPI_XFER_HANDLE_CACHE)) {
+        base = (uint32_t) xfer->rx_buf & CACHE_LINE_MASK;
+        spi_port_cache_invalidate((void *)base,
+                ((xfer->len + (CACHE_LINE_SIZE - 1)) &
+                CACHE_LINE_MASK));
+    }
+    if (!ctlr->is_packed) {
+        rx_mask = ((uint64_t)1 << xfer->bits_per_word) - 1;
+        for (count = 0; count < ctlr->curr_dma_words; count++) {
+            x = rx_buf[count];
+            x &= rx_mask;
+            rx_c_buf = (uint8_t *)&rx_buf[count];
+            for (i = 0; (i < ctlr->bytes_per_word); i++) {
+                *rx_c_buf++ = (x >> (i*8)) & 0xFF;
+            }
+        }
+    }
+    ctlr->cur_rx_pos += ctlr->curr_dma_words * ctlr->bytes_per_word;
+}
+
+SECTION_SPI_TEXT static error_t
+spi_check_and_clear_fifo(struct spi_ctlr *ctlr)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t status;
+    uint32_t cnt;
+
+    /* Make sure that Rx and Tx FIFO are empty */
+    status = spi_readl(ctlr, SPI_FIFO_STATUS_0);
+    if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
+        /* flush the FIFO */
+        status = NV_FLD_SET_DRF_DEF(SPI, FIFO_STATUS,
+                                    RX_FIFO_FLUSH, FLUSH, status);
+        status = NV_FLD_SET_DRF_DEF(SPI, FIFO_STATUS,
+                                    TX_FIFO_FLUSH, FLUSH, status);
+        spi_writel(ctlr, status, SPI_FIFO_STATUS_0);
+        for (cnt = 0UL; cnt != SPI_FIFO_FLUSH_MAX_DELAY; cnt += 1UL) {
+            status = spi_readl(ctlr, SPI_FIFO_STATUS_0);
+            if ((status & SPI_FIFO_EMPTY) == SPI_FIFO_EMPTY) {
+                goto out;
+            }
+            udelay(1);
+        }
+        ret =  E_SPI_FIFO_NON_EMPTY;
+    }
+
+out:
+    return ret;
+}
+
+SECTION_SPI_TEXT static error_t
+spi_start_dma_transfer(struct spi_ctlr *ctlr,
+                       struct spi_xfer *xfer)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t val = 0;
+    uint32_t cmd1;
+    uint32_t intr_mask = 0UL;
+    uint32_t len;
+    uint32_t burst_size;
+
+    /* For half duplex, ensure rx and tx transfers are not enabled.
+     * If rx and tx transfers are enabled, return error.
+     */
+    if (ctlr->dma_chans.tx == ctlr->dma_chans.rx) {
+        if ((ctlr->cur_direction & DATA_DIR_TX) &&
+                (ctlr->cur_direction & DATA_DIR_RX)) {
+            ret = E_SPI_XFER_NOT_SUPPORTED;
+            goto out;
+        }
+    }
+
+    val = NV_FLD_SET_DRF_NUM(SPI, DMA_BLK_SIZE, DMA_BLOCK_SIZE,
+                             (ctlr->curr_dma_words - 1), val);
+    spi_writel(ctlr, val, SPI_DMA_BLK_SIZE_0);
+
+    if (ctlr->is_packed) {
+        len = DIV_ROUND_UP(ctlr->curr_dma_words * ctlr->bytes_per_word, 4) * 4;
+    } else {
+        len = ctlr->curr_dma_words * 4;
+    }
+
+    /* Set attention level based on length of transfer.
+     * DMA burst size and SPI trigger level should be same.
+     */
+    val = 0;
+    if (len & 0xF) {
+        val |= NV_DRF_DEF(SPI, DMA_CTL, TX_TRIG, TRIG1) |
+               NV_DRF_DEF(SPI, DMA_CTL, RX_TRIG, TRIG1);
+        burst_size = 1;
+    } else if (((len) >> 4) & 0x1) {
+        val |= NV_DRF_DEF(SPI, DMA_CTL, TX_TRIG, TRIG4) |
+               NV_DRF_DEF(SPI, DMA_CTL, RX_TRIG, TRIG4);
+        burst_size = 4;
+    } else {
+        val |= NV_DRF_DEF(SPI, DMA_CTL, TX_TRIG, TRIG8) |
+               NV_DRF_DEF(SPI, DMA_CTL, RX_TRIG, TRIG8);
+        burst_size = 8;
+    }
+
+    if ((ctlr->cur_direction & DATA_DIR_TX) ||
+            (ctlr->cur_direction & DATA_DIR_RX)) {
+        intr_mask = spi_readl(ctlr, SPI_INTR_MASK_0);
+        intr_mask &= ~(NV_DRF_DEF(SPI, INTR_MASK ,
+                                  RDY_INTR_MASK, DEFAULT_MASK) |
+                       NV_DRF_DEF(SPI, INTR_MASK,
+                                  TX_FIFO_UNF_INTR_MASK, DEFAULT_MASK) |
+                       NV_DRF_DEF(SPI, INTR_MASK,
+                                  RX_FIFO_UNF_INTR_MASK, DEFAULT_MASK) |
+                       NV_DRF_DEF(SPI, INTR_MASK,
+                                  TX_FIFO_OVF_INTR_MASK, DEFAULT_MASK) |
+                       NV_DRF_DEF(SPI, INTR_MASK,
+                                  RX_FIFO_OVF_INTR_MASK, DEFAULT_MASK));
+        spi_writel(ctlr, intr_mask, SPI_INTR_MASK_0);
+    }
+
+    spi_writel(ctlr, val, SPI_DMA_CTL_0);
+    ctlr->dma_ctrl_reg_val = val;
+    if (ctlr->cur_direction & DATA_DIR_TX) {
+        spi_copy_client_txbuf_to_spi_txbuf(ctlr, xfer);
+        ret = spi_port_start_tx_dma(ctlr, xfer, len, burst_size);
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+    }
+    if (ctlr->cur_direction & DATA_DIR_RX) {
+        ret = spi_port_start_rx_dma(ctlr, xfer, len, burst_size);
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+    ctlr->is_curr_dma_xfer = true;
+    cmd1 = ctlr->cmd1_reg_val;
+    if (ctlr->cur_direction & DATA_DIR_TX) {
+        cmd1 |= NV_DRF_DEF(SPI, COMMAND, Tx_EN, ENABLE);
+    }
+    if (ctlr->cur_direction & DATA_DIR_RX) {
+        cmd1 |= NV_DRF_DEF(SPI, COMMAND, Rx_EN, ENABLE);
+    }
+    spi_writel(ctlr, cmd1, SPI_COMMAND_0);
+
+    val |= NV_DRF_DEF(SPI, DMA_CTL, DMA_EN, ENABLE);
+    spi_writel(ctlr, val, SPI_DMA_CTL_0);
+
+out:
+    return ret;
+}
+
+SECTION_SPI_TEXT static error_t
+spi_start_pio_transfer(struct spi_ctlr *ctlr,
+                       struct spi_xfer *xfer)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t val = 0UL;
+    uint32_t cur_words;
+    uint32_t intr_mask;
+
+    if (ctlr->cur_direction & DATA_DIR_TX) {
+        cur_words = spi_fill_tx_fifo_from_client_txbuf(ctlr, xfer);
+    } else {
+        cur_words = ctlr->curr_dma_words;
+    }
+
+    val = NV_FLD_SET_DRF_NUM(SPI, DMA_BLK_SIZE, DMA_BLOCK_SIZE,
+                             (cur_words - 1), val);
+    spi_writel(ctlr, val, SPI_DMA_BLK_SIZE_0);
+
+    intr_mask = spi_readl(ctlr, SPI_INTR_MASK_0);
+    intr_mask &= ~(NV_DRF_DEF(SPI, INTR_MASK , RDY_INTR_MASK, DEFAULT_MASK) |
+                   NV_DRF_DEF(SPI, INTR_MASK,
+                              TX_FIFO_UNF_INTR_MASK, DEFAULT_MASK) |
+                   NV_DRF_DEF(SPI, INTR_MASK,
+                              RX_FIFO_UNF_INTR_MASK, DEFAULT_MASK) |
+                   NV_DRF_DEF(SPI, INTR_MASK,
+                              TX_FIFO_OVF_INTR_MASK, DEFAULT_MASK) |
+                   NV_DRF_DEF(SPI, INTR_MASK,
+                              RX_FIFO_OVF_INTR_MASK, DEFAULT_MASK));
+    spi_writel(ctlr, intr_mask, SPI_INTR_MASK_0);
+
+    val = 0UL;
+    spi_writel(ctlr, val, SPI_DMA_CTL_0);
+    ctlr->dma_ctrl_reg_val = val;
+
+    ctlr->is_curr_dma_xfer = false;
+    val = ctlr->cmd1_reg_val;
+    if (ctlr->cur_direction & DATA_DIR_TX) {
+        val |= NV_DRF_DEF(SPI, COMMAND, Tx_EN, ENABLE);
+    }
+    if (ctlr->cur_direction & DATA_DIR_RX) {
+        val |= NV_DRF_DEF(SPI, COMMAND, Rx_EN, ENABLE);
+    }
+    spi_writel(ctlr, val, SPI_COMMAND_0);
+
+    val = NV_FLD_SET_DRF_DEF(SPI, COMMAND, PIO, PIO, val);
+    spi_writel(ctlr, val, SPI_COMMAND_0);
+
+    return ret;
+}
+
+SECTION_SPI_TEXT static error_t
+spi_clk_set_rate(struct spi_ctlr *ctlr,
+                 uint32_t rate)
+{
+    error_t ret = E_SUCCESS;
+
+    /* TODO: Change parent to support lower frequencies
+     * Currently there is no option to change parent for a clock
+     * minimum supported frequency on PLLP is 3.5MHz
+     */
+
+    spi_port_clk_disable(ctlr);
+
+    ret = spi_port_clk_set_rate(ctlr, rate);
+    if (ret != E_SUCCESS) {
+        ret = E_SPI_CLK_SET_RATE;
+        goto out;
+    }
+
+    ret = spi_port_clk_enable(ctlr);
+    if (ret != E_SUCCESS) {
+        ret = E_SPI_CLK_EN;
+        goto out;
+    }
+
+out:
+    return ret;
+}
+
+SECTION_SPI_TEXT error_t
+spi_suspend(struct spi_ctlr *ctlr)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret =E_SPI_NULL_PTR;
+        goto out;
+    }
+
+    if (ctlr->busy) {
+        ret = E_SPI_CTLR_BUSY;
+        goto out;
+    }
+
+    spi_port_clk_disable(ctlr);
+
+out:
+    return ret;
+}
+
+SECTION_SPI_TEXT error_t
+spi_resume(struct spi_ctlr *ctlr)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret =E_SPI_NULL_PTR;
+        goto out;
+    }
+
+    ret = spi_port_clk_set_rate(ctlr, ctlr->spi_clk_rate);
+
+out:
+    return ret;
+}
+
+SECTION_SPI_TEXT static void
+spi_configure_cmd1_reg(struct spi_ctlr *ctlr,
+                       struct spi_xfer *xfer)
+{
+    uint32_t  command1;
+    uint32_t  cs_pol_bit[MAX_CHIP_SELECT] = {
+                NV_DRF_DEF(SPI, COMMAND, CS_POL_INACTIVE0, HIGH),
+                NV_DRF_DEF(SPI, COMMAND, CS_POL_INACTIVE1, HIGH),
+                NV_DRF_DEF(SPI, COMMAND, CS_POL_INACTIVE2, HIGH),
+                NV_DRF_DEF(SPI, COMMAND, CS_POL_INACTIVE3, HIGH),
+    };
+
+    command1 = ctlr->def_cmd1_reg_val;
+    if (xfer->mode & TEGRA_SPI_CS_HIGH) {
+        command1 &= ~cs_pol_bit[xfer->chip_select];
+    } else {
+        command1 |= cs_pol_bit[xfer->chip_select];
+    }
+
+    command1 = NV_FLD_SET_DRF_NUM(SPI, COMMAND, CS_SEL, xfer->chip_select,
+                                  command1);
+
+    ctlr->def_cmd1_reg_val = command1;
+
+    command1 = NV_FLD_SET_DRF_NUM(SPI, COMMAND, BIT_LENGTH,
+                                  (xfer->bits_per_word - 1), command1);
+    command1 = NV_FLD_SET_DRF_NUM(SPI, COMMAND, MODE,
+                                  (xfer->mode & 0x3), command1);
+    command1 = NV_FLD_SET_DRF_DEF(SPI, COMMAND, CS_SW_HW, SOFTWARE, command1);
+    command1 = NV_FLD_SET_DRF_NUM(SPI, COMMAND, CS_SW_VAL,
+                                  (xfer->mode & TEGRA_SPI_CS_HIGH), command1);
+
+    if (xfer->mode & TEGRA_SPI_LSBYTE_FIRST) {
+        command1 = NV_FLD_SET_DRF_DEF(SPI, COMMAND, En_LE_Byte,
+                                      FIRST, command1);
+    } else {
+        command1 = NV_FLD_SET_DRF_DEF(SPI, COMMAND, En_LE_Byte,
+                                      LAST, command1);
+    }
+
+    if (xfer->mode & TEGRA_SPI_LSB_FIRST) {
+        command1 = NV_FLD_SET_DRF_DEF(SPI, COMMAND, En_LE_Bit, FIRST, command1);
+    } else {
+        command1 = NV_FLD_SET_DRF_DEF(SPI, COMMAND, En_LE_Bit, LAST, command1);
+    }
+
+    if (xfer->mode & TEGRA_SPI_3WIRE) {
+        command1 = NV_FLD_SET_DRF_DEF(SPI, COMMAND, BIDIR, BIDIR,
+                        command1);
+    } else {
+        command1 = NV_FLD_SET_DRF_DEF(SPI, COMMAND, BIDIR, NORMAL,
+                        command1);
+    }
+
+    if ((xfer->rx_nbits == TEGRA_SPI_NBITS_DUAL) ||
+            (xfer->tx_nbits == TEGRA_SPI_NBITS_DUAL)) {
+        command1 = NV_FLD_SET_DRF_DEF(SPI, COMMAND, BOTH_EN_BIT,
+                        ENABLE, command1);
+    }
+
+    if (ctlr->is_packed) {
+        command1 |= NV_DRF_DEF(SPI, COMMAND, PACKED, ENABLE);
+    } else {
+        command1 &= ~(NV_DRF_DEF(SPI, COMMAND, PACKED, ENABLE));
+    }
+
+    command1 &= ~(NV_DRF_DEF(SPI, COMMAND, CS_SEL, DEFAULT_MASK) |
+                  NV_DRF_DEF(SPI, COMMAND, Tx_EN, DEFAULT_MASK) |
+                  NV_DRF_DEF(SPI, COMMAND, Rx_EN, DEFAULT_MASK));
+
+    ctlr->cmd1_reg_val = command1;
+}
+
+SECTION_SPI_TEXT static void
+spi_init_ctlr_context(struct spi_ctlr *ctlr)
+{
+    ctlr->cur_pos = 0UL;
+    ctlr->cur_rx_pos = 0UL;
+    ctlr->cur_tx_pos = 0UL;
+    ctlr->tx_status = 0UL;
+    ctlr->rx_status = 0UL;
+    ctlr->cur_direction = 0UL;
+}
+
+SECTION_SPI_TEXT static error_t
+spi_handle_message(struct spi_ctlr *ctlr,
+                   struct spi_xfer *xfer)
+{
+    error_t ret = E_SUCCESS;
+    bool    reset = false;
+
+    if (!ctlr->is_curr_dma_xfer) {
+        if (ctlr->cur_direction & DATA_DIR_RX) {
+            spi_read_rx_fifo_to_client_rxbuf(ctlr, xfer);
+            ctlr->cur_pos = ctlr->cur_rx_pos;
+        } else {
+            ctlr->cur_pos = ctlr->cur_tx_pos;
+        }
+    } else {
+        if (ctlr->tx_dma_status != E_SUCCESS) {
+            if (ctlr->cur_direction & DATA_DIR_TX) {
+                spi_port_tx_dma_xfer_abort(ctlr);
+                reset = true;
+            }
+        }
+        if (ctlr->rx_dma_status != E_SUCCESS) {
+            if (ctlr->cur_direction & DATA_DIR_RX) {
+                spi_port_rx_dma_xfer_abort(ctlr);
+                reset = true;
+            }
+        }
+        if (reset) {
+            spi_port_clk_reset_pulse(ctlr, 2);
+            ret = E_SPI_DMA_XFER_FAIL;
+            goto out;
+        }
+
+        if (ctlr->cur_direction & DATA_DIR_TX) {
+            ctlr->cur_tx_pos += ctlr->curr_dma_words * ctlr->bytes_per_word;
+            ctlr->cur_pos = ctlr->cur_tx_pos;
+        }
+        if (ctlr->cur_direction & DATA_DIR_RX) {
+            spi_copy_spi_rxbuf_to_client_rxbuf(ctlr, xfer);
+            ctlr->cur_pos = ctlr->cur_rx_pos;
+        }
+    }
+
+out:
+    return ret;
+}
+
+SECTION_SPI_TEXT static error_t
+spi_wait_on_message_xfer(struct spi_ctlr *ctlr)
+{
+    error_t  ret = E_SUCCESS;
+    bool     xfer_timeout = false;
+
+    ret = irq_safe_enable(ctlr->conf.irq);
+    if (ret != E_SUCCESS) {
+        spi_port_clk_disable(ctlr);
+        goto out;
+    }
+    /*
+     * For synchronous transfers, the driver relies on the port specific
+     * implementation of some kind of synchronization mechanism until the
+     * SPI transfer is complete.
+     */
+    ret = spi_port_xfer_sync(ctlr, SPI_TRANSFER_TIMEOUT);
+    (void)irq_safe_disable(ctlr->conf.irq);
+    if (ret != E_SUCCESS) {
+        xfer_timeout = true;
+        spi_port_clk_reset_pulse(ctlr, 2);
+    }
+
+    if (xfer_timeout || ctlr->rx_status || ctlr->tx_status) {
+        if (ctlr->is_curr_dma_xfer) {
+            if (ctlr->cur_direction & DATA_DIR_TX) {
+                spi_port_tx_dma_xfer_abort(ctlr);
+            }
+            if (ctlr->cur_direction & DATA_DIR_RX) {
+                spi_port_rx_dma_xfer_abort(ctlr);
+            }
+        }
+        ret = E_SPI_XFER_ERR;
+        goto out;
+    }
+
+out:
+    return ret;
+}
+
+SECTION_SPI_TEXT static error_t
+spi_transfer_remain_message(struct spi_ctlr *ctlr,
+                            struct spi_xfer *xfer)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t total_fifo_words;
+
+    total_fifo_words = spi_calculate_curr_xfer_param(ctlr, xfer);
+    if (ctlr->is_curr_dma_xfer) {
+        /* Make sure that Rx and Tx FIFO are empty */
+        ret = spi_check_and_clear_fifo(ctlr);
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+
+        if (total_fifo_words > SPI_FIFO_DEPTH) {
+            ret = spi_start_dma_transfer(ctlr, xfer);
+        } else {
+            ret = spi_start_pio_transfer(ctlr, xfer);
+        }
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+    } else {
+        ret = spi_start_pio_transfer(ctlr, xfer);
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+    ret = spi_wait_on_message_xfer(ctlr);
+
+out:
+    return ret;
+}
+
+SECTION_SPI_TEXT static error_t
+spi_start_transfer_one(struct spi_ctlr *ctlr,
+                       struct spi_xfer *xfer)
+{
+    error_t   ret = E_SUCCESS;
+    uint32_t  total_fifo_words;
+    uint32_t  speed;
+
+    spi_init_ctlr_context(ctlr);
+
+    ctlr->cur_xfer = xfer;
+    total_fifo_words = spi_calculate_curr_xfer_param(ctlr, xfer);
+
+    if (xfer->rx_buf != NULL) {
+        ctlr->cur_direction |= DATA_DIR_RX;
+    }
+    if (xfer->tx_buf != NULL) {
+        ctlr->cur_direction |= DATA_DIR_TX;
+    }
+
+    /* Return if neither RX or TX is requested OR
+     * not all words are available
+     */
+    if ((ctlr->cur_direction == 0UL) ||
+        ((xfer->len % ctlr->bytes_per_word) != 0UL)) {
+        ret = E_SPI_INVALID_PARAM;
+        goto out;
+    }
+
+    speed = (xfer->spi_clk_rate != 0UL) ? xfer->spi_clk_rate :
+            ctlr->cdata[xfer->chip_select].spi_max_clk_rate;
+    if (speed != ctlr->spi_clk_rate) {
+        ret = spi_clk_set_rate(ctlr, speed);
+        if (ret != E_SUCCESS) {
+            goto out;
+        } else {
+            ctlr->spi_clk_rate = speed;
+        }
+    }
+
+    spi_clear_status(ctlr);
+
+    spi_configure_cmd1_reg(ctlr, xfer);
+
+    /* Make sure that Rx and Tx FIFO are empty */
+    ret = spi_check_and_clear_fifo(ctlr);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    if (total_fifo_words > SPI_FIFO_DEPTH) {
+        ret = spi_start_dma_transfer(ctlr, xfer);
+    } else {
+        ret = spi_start_pio_transfer(ctlr, xfer);
+    }
+
+out:
+    return ret;
+}
+
+
+SECTION_SPI_TEXT static error_t
+spi_dma_init(struct spi_ctlr *ctlr)
+{
+    error_t ret = E_SUCCESS;
+
+    ret = spi_port_dma_init(ctlr);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    /* Full duplex transactions require 2 channels. Check your POR
+     * to ensure 2 channels are supported.
+     */
+    if (ctlr->en_full_duplex) {
+        /* check for 2 different dma channels if full duplex
+         * is supported.
+         */
+        if (ctlr->dma_chans.tx == ctlr->dma_chans.rx) {
+            ret = E_SPI_FD_MODE_NO_SUPPORT;
+            goto out;
+        }
+    }
+
+out:
+    return ret;
+}
+
+SECTION_SPI_TEXT static void
+spi_dma_config_setup(struct spi_ctlr *ctlr,
+              struct spi_master_init *setting)
+{
+    /* TODO: figure out if there is a way to validate these params */
+    ctlr->dma_id = setting->dma_id;
+    ctlr->dma_chans.tx = setting->dma_chans.tx;
+    ctlr->dma_chans.rx = setting->dma_chans.rx;
+    ctlr->dma_slave_req = setting->dma_slave_req;
+}
+
+SECTION_SPI_TEXT error_t
+spi_transfer(struct spi_ctlr *ctlr,
+             struct spi_xfer *xfer)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL || xfer == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_SPI_NULL_PTR;
+        goto out;
+    }
+
+    if (!ctlr->inited) {
+        ret = E_SPI_NO_INIT;
+        goto out;
+    }
+
+    if (xfer->len == 0) {
+        ret = E_SPI_INVALID_PARAM;
+        goto out;
+    }
+
+    if (ctlr->busy) {
+        ret = E_SPI_CTLR_BUSY;
+        goto out;
+    }
+
+    ctlr->busy = true;
+
+    if (xfer->flags & BIT(TEGRA_SPI_XFER_FIRST_MSG)) {
+        ret = spi_start_transfer_one(ctlr, xfer);
+    } else {
+        ret = spi_transfer_remain_message(ctlr, xfer);
+    }
+
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    ret = spi_wait_on_message_xfer(ctlr);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    ret = spi_handle_message(ctlr, xfer);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    if (ctlr->cur_pos == xfer->len) {
+        goto out;
+    }
+
+    while (1) {
+        ret = spi_transfer_remain_message(ctlr, xfer);
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+
+        ret = spi_handle_message(ctlr, xfer);
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+
+        if (ctlr->cur_pos == xfer->len) {
+            break;
+        }
+    }
+
+out:
+    /* de-assert CS to end the transaction */
+    if (ret == E_SUCCESS &&
+               ((xfer->flags & BIT(TEGRA_SPI_XFER_LAST_MSG)) != 0UL)) {
+        spi_writel(ctlr, ctlr->def_cmd1_reg_val, SPI_COMMAND_0);
+    }
+
+    if (ctlr != NULL) {
+        ctlr->busy = false;
+    }
+
+    return ret;
+}
+
+SECTION_SPI_INIT_TEXT error_t
+spi_client_setup(struct spi_ctlr *ctlr,
+                 struct spi_client_setting *setting)
+{
+    error_t                   ret = E_SUCCESS;
+    struct spi_client_setting *cdata;
+    uint32_t                  command2_reg;
+
+    if (ctlr == NULL || setting == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_SPI_NULL_PTR;
+        goto out;
+    }
+
+    if (!ctlr->inited) {
+        ret = E_SPI_NO_INIT;
+        goto out;
+    }
+
+    if (ctlr->busy) {
+        ret = E_SPI_CTLR_BUSY;
+        goto out;
+    }
+
+    if (setting->spi_max_clk_rate == 0UL) {
+        ret = E_SPI_INVALID_CLK_RATE;
+        goto out;
+    }
+
+    cdata = &ctlr->cdata[setting->chip_select];
+    cdata->chip_select = setting->chip_select;
+    cdata->cs_setup_clk_count = setting->cs_setup_clk_count;
+    cdata->cs_hold_clk_count = setting->cs_hold_clk_count;
+    cdata->cs_inactive_cycles = setting->cs_inactive_cycles;
+    cdata->set_rx_tap_delay = setting->set_rx_tap_delay;
+    cdata->spi_max_clk_rate = setting->spi_max_clk_rate;
+    cdata->spi_no_dma = setting->spi_no_dma;
+
+    ret = spi_port_clk_set_rate(ctlr, setting->spi_max_clk_rate);
+    if (ret != E_SUCCESS) {
+        ret = E_SPI_CLK_SET_RATE;
+        goto out;
+    }
+    ctlr->spi_clk_rate = setting->spi_max_clk_rate;
+
+    ctlr->def_cmd2_reg_val = spi_readl(ctlr, SPI_COMMAND2_0);
+    command2_reg = ctlr->def_cmd2_reg_val;
+
+    if (cdata->set_rx_tap_delay) {
+        if (ctlr->spi_clk_rate > SPI_SPEED_TAP_DELAY_MARGIN) {
+            command2_reg = NV_FLD_SET_DRF_NUM(SPI, COMMAND2,
+                                              Rx_Clk_TAP_DELAY,
+                                              SPI_DEFAULT_RX_TAP_DELAY,
+                                              command2_reg);
+        }
+    }
+    spi_writel(ctlr, command2_reg, SPI_COMMAND2_0);
+
+out:
+    return ret;
+}
+
+SECTION_SPI_INIT_TEXT error_t
+spi_init(struct spi_ctlr *ctlr,
+         struct spi_master_init *setting)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL || setting == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_SPI_NULL_PTR;
+        goto out;
+    }
+
+    if (ctlr->inited) {
+        ret = E_SPI_REINIT;
+        goto out;
+    }
+
+    ctlr->spi_clk_rate = setting->spi_max_clk_rate;
+    ctlr->busy = false;
+
+    spi_dma_config_setup(ctlr, setting);
+
+    /* Set SPI controller clock rate */
+    ret = spi_port_clk_set_rate(ctlr, ctlr->spi_clk_rate);
+    if (ret!= E_SUCCESS) {
+        goto out;
+    }
+
+    /* enable the clock for SPI controller */
+    ret = spi_port_clk_enable(ctlr);
+    if (ret!= E_SUCCESS) {
+        goto out;
+    }
+
+    /* assert followed by deassert the reset for SPI controller */
+    ret = spi_port_clk_reset_pulse(ctlr, 2);
+    if (ret!= E_SUCCESS) {
+        goto out;
+    }
+
+    /* Initialize the SPI DMA */
+    ret = spi_dma_init(ctlr);
+    if (ret!= E_SUCCESS) {
+        spi_port_clk_disable(ctlr);
+        goto out;
+    }
+
+    if (ctlr->conf.irq != UINT32_MAX) {
+        /* register irq handler */
+        ret = irq_safe_set_handler(ctlr->conf.irq, spi_master_isr, ctlr);
+        if (ret != E_SUCCESS) {
+            spi_port_clk_disable(ctlr);
+            goto out;
+        }
+    }
+
+    /* port specific SPI controller setup callout */
+    ret = spi_port_init(ctlr);
+    if (ret != E_SUCCESS) {
+        spi_port_clk_disable(ctlr);
+        goto out;
+    }
+
+    ctlr->def_cmd1_reg_val = NV_DRF_DEF(SPI, COMMAND, M_S, MASTER) |
+                             NV_DRF_DEF(SPI, COMMAND, CS_SW_VAL, HIGH) |
+                             NV_DRF_DEF(SPI, COMMAND, CS_POL_INACTIVE3, HIGH) |
+                             NV_DRF_DEF(SPI, COMMAND, CS_POL_INACTIVE2, HIGH) |
+                             NV_DRF_DEF(SPI, COMMAND, CS_POL_INACTIVE1, HIGH) |
+                             NV_DRF_DEF(SPI, COMMAND, CS_POL_INACTIVE0, HIGH);
+    spi_writel(ctlr, ctlr->def_cmd1_reg_val, SPI_COMMAND_0);
+
+    ctlr->inited = true;
+
+out:
+    return ret;
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/spi-slv/module-spi-slv-nosafety-config.mk b/spe-freertos-bsp/fsp/source/drivers/spi-slv/module-spi-slv-nosafety-config.mk
new file mode 100644
index 0000000..298e505
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/spi-slv/module-spi-slv-nosafety-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-spi-slv-nosafety-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-osa*.mk' files.
+MODULE_SPI_SLV_NOSAFETY_CONFIG          := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_SPI_SLV_NOSAFETY_DEPENDS         := SOC CLUSTER CPL FSP_COMMON
+$(foreach _,$(MODULE_SPI_SLV_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_SPI_SLV_NOSAFETY_DRIVERS_DIR      = $(FSP_COMMON_REPO)/drivers/spi-slv
+MODULE_SPI_SLV_NOSAFETY_SOURCE_DIR       = $(MODULE_SPI_SLV_NOSAFETY_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_SPI_SLV_NOSAFETY_INCLUDES         =
diff --git a/spe-freertos-bsp/fsp/source/drivers/spi-slv/module-spi-slv-nosafety.mk b/spe-freertos-bsp/fsp/source/drivers/spi-slv/module-spi-slv-nosafety.mk
new file mode 100644
index 0000000..d9a2077
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/spi-slv/module-spi-slv-nosafety.mk
@@ -0,0 +1,71 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-spi-slv-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_SPI_SLV_NOSAFETY_NAME            := SPI_SLV_NOSAFETY
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_SPI_SLV_NOSAFETY_DEFINED         := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_SPI_SLV_NOSAFETY_DEPENDS         := SPI_SLV_NOSAFETY SOC CPL
+$(foreach _,$(CONFIG_SPI_SLV_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_SPI_SLV_NOSAFETY_C_SRC            =
+MODULE_SPI_SLV_NOSAFETY_C_SRC           += $(MODULE_SPI_SLV_NOSAFETY_DRIVERS_DIR)/spi-slave.c
+MODULE_SPI_SLV_NOSAFETY_C_SRC           += $(CPL_SOC_IDS)/spi-ids.c
+
+#
+# If the client module does not need 'spi-port.c' use this MAKEFILE flag to
+# ignore it.
+ifndef IGNORE_SPI_PORT
+MODULE_SPI_SLV_NOSAFETY_C_SRC           += $(CPL_SOC_PORT)/spi-port.c
+endif
+
+#
+# Assembly source
+MODULE_SPI_SLV_NOSAFETY_ASM_SRC          =
+#MODULE_SPI_SLV_NOSAFETY_ASM_SRC        += $(CPL_SOC_PORT)/spi-irq.S
+
+#
+# Special C Flags
+MODULE_SPI_SLV_NOSAFETY_C_FLAGS          =
+
+#
+# Special ASM Flags
+MODULE_SPI_SLV_NOSAFETY_ASM_FLAGS        =
diff --git a/spe-freertos-bsp/fsp/source/drivers/spi-slv/spi-slave.c b/spe-freertos-bsp/fsp/source/drivers/spi-slv/spi-slave.c
new file mode 100644
index 0000000..f55beed
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/spi-slv/spi-slave.c
@@ -0,0 +1,1115 @@
+/*
+ * Copyright (c) 2017-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                   // for bool
+#include <stdint.h>                    // for uint32_t, uint8_t, UINT32_...
+#include <stddef.h>                    // for NULL
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>            // for CT_ASSERT
+#include <soc-common/hw-const.h>       // IWYU pragma: keep
+#include <soc-common/argpcdma-defs.h>  // GPCDMA_CHANNEL_CH...
+
+/* Hardware headers */
+#include <arspi.h>
+
+/* Late FSP headers */
+#include <misc/nvrm_drf.h>             // NV_DRF_* macros
+#include <cpu/type-conversion.h>       // for fsp_c_v_ptr_to_u32
+#include <error/common-errors.h>       // for error_t, E_SUCCESS
+#include <irq/safe-irqs.h>             // for in_interrupt, irq_enable, irq_set...
+#include <misc/attributes.h>           // for UNUSED
+#include <misc/bitops.h>               // for BIT, bit_number, FSP__MISC__BITOPS_H
+#include <misc/macros.h>               // for ARRAY_SIZE
+#include <reg-access/reg-access.h>     // for readl_base_offset, writel_base_of...
+#include <delay/delay.h>               //
+#include <processor/cache-hw.h>        //
+
+/* Module specific headers */
+#include <spi/spi-errors.h>            // for E_SPI_NULL_PTR, E_SPI_...
+#include <spi-slv/spi-slave.h>         //
+#include <spi/sections-spi.h>          // Immune from CT_ASSERT protection
+#include <spi/spi-priv.h>              // for struct spi_ctlr, spi_ctrl...
+#include <spi/spi-port.h>              // for spi_port_...
+
+#define SPI_CS_INACTIVE_ERR     (NV_DRF_DEF(SPI, FIFO_STATUS, CS_INACTIVE, DEFAULT_MASK))
+#define SPI_ERR                 (NV_DRF_DEF(SPI, FIFO_STATUS, ERR, ERROR))
+#define SPI_FIFO_ERROR          (NV_DRF_DEF(SPI, FIFO_STATUS, RX_FIFO_UNF, \
+                                     ERROR) | \
+                                 NV_DRF_DEF(SPI, FIFO_STATUS, RX_FIFO_OVF, \
+                                     ERROR) | \
+                                 NV_DRF_DEF(SPI, FIFO_STATUS, TX_FIFO_UNF, \
+                                     ERROR) | \
+                                 NV_DRF_DEF(SPI, FIFO_STATUS, RX_FIFO_OVF, \
+                                     ERROR))
+#define SPI_FIFO_EMPTY          (NV_DRF_DEF(SPI, FIFO_STATUS, RX_FIFO_EMPTY, \
+                                     EMPTY) | \
+                                 NV_DRF_DEF(SPI, FIFO_STATUS, TX_FIFO_EMPTY, \
+                                     EMPTY))
+
+#define SPI_INTR_DEFAULT_MASK   (NV_DRF_DEF(SPI, INTR_MASK, CS_INTR_MASK, \
+                                     DEFAULT_MASK) | \
+                                 NV_DRF_DEF(SPI, INTR_MASK, FRAME_END_INTR_MASK, \
+                                     DEFAULT_MASK) | \
+                                 NV_DRF_DEF(SPI, INTR_MASK, RX_FIFO_UNF_INTR_MASK, \
+                                     DEFAULT_MASK) | \
+                                 NV_DRF_DEF(SPI, INTR_MASK, TX_FIFO_UNF_INTR_MASK, \
+                                     DEFAULT_MASK) | \
+                                 NV_DRF_DEF(SPI, INTR_MASK, RX_FIFO_UNF_INTR_MASK, \
+                                     DEFAULT_MASK) | \
+                                 NV_DRF_DEF(SPI, INTR_MASK, RX_FIFO_OVF_INTR_MASK, \
+                                     DEFAULT_MASK) | \
+                                 NV_DRF_DEF(SPI, INTR_MASK, TX_FIFO_OVF_INTR_MASK, \
+                                     DEFAULT_MASK) | \
+                                 NV_DRF_DEF(SPI, INTR_MASK, RDY_INTR_MASK, \
+                                     DEFAULT_MASK))
+
+#define SPI_TX_FIFO_EMPTY       NV_DRF_DEF(SPI, FIFO_STATUS, TX_FIFO_EMPTY, \
+                                    EMPTY)
+
+#define SPI_FIFO_DEPTH              64
+#define DATA_DIR_TX                 BIT(0)
+#define DATA_DIR_RX                 BIT(1)
+#define SPI_MISC_EXT_CLK_EN         BIT(30)
+#define SPI_FIFO_FLUSH_MAX_DELAY    2000 /* usec */
+
+#define SPI_TRANSFER_TIMEOUT        (50 * 1000 /* usec */)
+
+static struct spi_slave_init_setup default_slave_setting = {
+    .dma_id             = NULL,
+    .dma_chans.tx       = 0UL,
+    .dma_chans.rx       = 0UL,
+    .spi_max_clk_rate   = SPI_DEFAULT_MAX_CLK,
+    .dma_slave_req      = 0UL,
+};
+
+static inline uint32_t
+spi_slave_readl(struct spi_ctlr *ctlr,
+                uint32_t reg)
+{
+    return readl(ctlr->conf.base_addr + reg);
+}
+
+static inline void
+spi_slave_writel(struct spi_ctlr *ctlr,
+                 uint32_t val,
+                 uint32_t reg)
+{
+    writel(val, ctlr->conf.base_addr + reg);
+}
+
+static void
+spi_slave_ext_clk_enable(struct spi_ctlr *ctlr,
+                         bool enable)
+{
+    uint32_t misc_reg = 0;
+
+    misc_reg = spi_slave_readl(ctlr, SPI_MISC_0);
+    /* Enable external clock bit in SPI_MISC_REG */
+    if (enable) {
+        misc_reg |= SPI_MISC_EXT_CLK_EN;
+    } else {
+        misc_reg &= (~SPI_MISC_EXT_CLK_EN);
+    }
+
+    spi_slave_writel(ctlr, misc_reg, SPI_MISC_0);
+}
+
+static void
+spi_slave_dma_setup(struct spi_ctlr *ctlr,
+                    struct spi_slave_init_setup *setting)
+{
+    /* TODO: figure out if there is a way to validate these params */
+    if (ctlr->slave_dma_support) {
+        ctlr->dma_id = setting->dma_id;
+        ctlr->dma_chans.tx = setting->dma_chans.tx;
+        ctlr->dma_chans.rx = setting->dma_chans.rx;
+        ctlr->dma_slave_req = setting->dma_slave_req;
+    }
+}
+
+static uint32_t
+spi_calculate_curr_xfer_param(struct spi_ctlr *ctlr,
+                              struct spi_xfer *xfer)
+{
+    uint32_t remain_len = xfer->len - ctlr->cur_pos;
+    uint32_t max_word;
+    uint32_t max_len;
+    uint32_t total_fifo_words;
+    bool     spi_no_dma = ctlr->cdata[xfer->chip_select].spi_no_dma;
+
+    ctlr->bytes_per_word = (xfer->bits_per_word - 1) / 8 + 1;
+
+    if ((xfer->bits_per_word == 8 || xfer->bits_per_word == 16 ||
+            xfer->bits_per_word == 32) && (remain_len > 3)) {
+        ctlr->is_packed = 1;
+        ctlr->words_per_32bit = 32 / xfer->bits_per_word;
+    } else {
+        ctlr->is_packed = 0;
+        ctlr->words_per_32bit = 1;
+    }
+
+    if (ctlr->is_packed) {
+        max_len = remain_len;
+        if (spi_no_dma) {
+            max_len = min(max_len, (SPI_FIFO_DEPTH * 4));
+        }
+        ctlr->curr_dma_words = max_len / ctlr->bytes_per_word;
+        total_fifo_words = (max_len + 3) / 4;
+    } else {
+        max_word = (remain_len - 1) / ctlr->bytes_per_word + 1;
+        if (spi_no_dma) {
+            max_word = min(max_word, SPI_FIFO_DEPTH);
+        }
+        ctlr->curr_dma_words = max_word;
+        total_fifo_words = max_word;
+    }
+
+    return total_fifo_words;
+}
+
+static uint32_t
+spi_fill_tx_fifo_from_client_txbuf(struct spi_ctlr *ctlr,
+                                   struct spi_xfer *xfer)
+{
+    uint32_t nbytes;
+    uint32_t tx_empty_count;
+    uint32_t fifo_status;
+    uint32_t max_n_32bit;
+    uint32_t i, count, byte_count;
+    uint32_t x;
+    uint32_t written_words;
+    uint32_t fifo_words_left;
+    uint8_t *tx_buf = (uint8_t *)xfer->tx_buf + ctlr->cur_tx_pos;
+
+    fifo_status = spi_slave_readl(ctlr, SPI_FIFO_STATUS_0);
+    tx_empty_count = NV_DRF_VAL(SPI, FIFO_STATUS, TX_FIFO_EMPTY_COUNT,
+                    fifo_status);
+
+    if (ctlr->is_packed) {
+        fifo_words_left = tx_empty_count * ctlr->words_per_32bit;
+        written_words = min(fifo_words_left, ctlr->curr_dma_words);
+        nbytes = written_words * ctlr->bytes_per_word;
+        max_n_32bit = DIV_ROUND_UP(nbytes, 4);
+        byte_count = 4;
+    } else {
+        max_n_32bit = min(ctlr->curr_dma_words, tx_empty_count);
+        written_words = max_n_32bit;
+        nbytes = written_words * ctlr->bytes_per_word;
+        byte_count = ctlr->bytes_per_word;
+    }
+
+    for (count = 0; count < max_n_32bit; count++) {
+        x = 0;
+        for (i = 0; (i < byte_count) && nbytes; i++, nbytes--)
+            x |= ((*tx_buf++) << (i * 8));
+        spi_slave_writel(ctlr, x, SPI_TX_FIFO_0);
+    }
+
+    ctlr->cur_tx_pos += written_words * ctlr->bytes_per_word;
+
+    return written_words;
+}
+
+static uint32_t
+spi_read_rx_fifo_to_client_rxbuf(struct spi_ctlr *ctlr,
+                                 struct spi_xfer *xfer)
+{
+    uint32_t rx_full_count;
+    uint32_t fifo_status;
+    uint32_t i, count;
+    uint32_t x;
+    uint32_t read_words = 0;
+    uint32_t len;
+    uint8_t *rx_buf = (uint8_t *)xfer->rx_buf + ctlr->cur_rx_pos;
+
+    fifo_status = spi_slave_readl(ctlr, SPI_FIFO_STATUS_0);
+    rx_full_count = NV_DRF_VAL(SPI, FIFO_STATUS, RX_FIFO_FULL_COUNT,
+                    fifo_status);
+
+    if (ctlr->is_packed) {
+        len = ctlr->curr_dma_words * ctlr->bytes_per_word;
+        for (count = 0; count < rx_full_count; count++) {
+            x = spi_slave_readl(ctlr, SPI_RX_FIFO_0);
+            for (i = 0; len && (i < 4); i++, len--) {
+                *rx_buf++ = (x >> (i * 8)) & 0xFF;
+            }
+        }
+        ctlr->cur_rx_pos += ctlr->curr_dma_words * ctlr->bytes_per_word;
+        read_words += ctlr->curr_dma_words;
+    } else {
+        for (count = 0; count < rx_full_count; count++) {
+            x = spi_slave_readl(ctlr, SPI_RX_FIFO_0);
+            for (i = 0; (i < ctlr->bytes_per_word); i++) {
+                *rx_buf++ = (x >> (i * 8)) & 0xFF;
+            }
+        }
+        ctlr->cur_rx_pos += rx_full_count * ctlr->bytes_per_word;
+        read_words += rx_full_count;
+    }
+
+    return read_words;
+}
+
+static void
+spi_copy_client_txbuf_to_spi_txbuf(struct spi_ctlr *ctlr,
+                                   struct spi_xfer *xfer)
+{
+    uint32_t i;
+    int32_t count;
+    uint32_t x;
+    uint32_t offset;
+    uint8_t *tx_c_buf;
+    uint32_t base;
+    uint32_t *tx_buf = (uint32_t *)((uint8_t *)xfer->tx_buf + ctlr->cur_tx_pos);
+    uint32_t nbytes = ctlr->curr_dma_words * ctlr->bytes_per_word;
+
+    if (!ctlr->is_packed) {
+        tx_c_buf = (uint8_t *)xfer->tx_buf + ctlr->cur_tx_pos +
+                        nbytes - 1;
+        /* curr_dma_words and fifo_words are same for unpacked mode */
+        for (count = ctlr->curr_dma_words - 1; count >= 0; count--) {
+            x = 0;
+            for (i = 0; nbytes && (i < ctlr->bytes_per_word);
+                        i++) {
+                offset = (--nbytes) % (ctlr->bytes_per_word);
+                x |= (*tx_c_buf--) << (offset * 8);
+            }
+            tx_buf[count] = x;
+        }
+        /**
+         * The following cache flush is needed only for unpacked mode
+         * as for packed mode you do not need to modify the tx buffer
+         */
+        if (xfer->flags & BIT(TEGRA_SPI_XFER_HANDLE_CACHE)) {
+            /**
+             * Align buffer address and length to cache line size
+             * and flush the cache
+             */
+            base = (uint32_t) xfer->tx_buf & CACHE_LINE_MASK;
+            spi_port_cache_clean((void *)base, (((ctlr->curr_dma_words * 4) +
+                    (CACHE_LINE_SIZE - 1)) & CACHE_LINE_MASK));
+        }
+    }
+}
+
+static void
+spi_copy_spi_rxbuf_to_client_rxbuf(struct spi_ctlr *ctlr,
+                                   struct spi_xfer *xfer)
+{
+    unsigned int i;
+    unsigned int count;
+    unsigned int x;
+    unsigned int rx_mask;
+    uint32_t base;
+    uint32_t *rx_buf = (uint32_t *)((uint8_t *)xfer->rx_buf +
+                        ctlr->cur_rx_pos);
+    uint8_t *rx_c_buf = (uint8_t *)xfer->rx_buf +
+                    ctlr->cur_rx_pos;
+
+    /**
+     * Align buffer address and length to cache line size
+     * and invalidate the cache
+     */
+    if (xfer->flags & BIT(TEGRA_SPI_XFER_HANDLE_CACHE)) {
+        base = (uint32_t) xfer->rx_buf & CACHE_LINE_MASK;
+        spi_port_cache_invalidate((void *)base,
+                ((xfer->len + (CACHE_LINE_SIZE - 1)) &
+                CACHE_LINE_MASK));
+    }
+    if (!ctlr->is_packed) {
+        rx_mask = ((uint64_t)1 << xfer->bits_per_word) - 1;
+        for (count = 0; count < ctlr->curr_dma_words; count++) {
+            x = rx_buf[count];
+            x &= rx_mask;
+            rx_c_buf = (uint8_t *)&rx_buf[count];
+            for (i = 0; (i < ctlr->bytes_per_word); i++) {
+                *rx_c_buf++ = (x >> (i*8)) & 0xFF;
+            }
+        }
+    }
+    ctlr->cur_rx_pos += ctlr->curr_dma_words * ctlr->bytes_per_word;
+}
+
+SECTION_SPI_TEXT static void
+handle_pio_err_xfer(struct spi_ctlr *ctlr)
+{
+    if (ctlr->tx_status || ctlr->rx_status) {
+        spi_port_clk_reset_pulse(ctlr, 2);
+    }
+}
+
+SECTION_SPI_TEXT static void
+handle_dma_err_xfer(struct spi_ctlr *ctlr)
+{
+    uint32_t errs = 0UL;
+
+    if ((ctlr->cur_direction & DATA_DIR_TX) && (ctlr->tx_status)) {
+        errs += 1UL;
+    }
+
+    if ((ctlr->cur_direction & DATA_DIR_RX) && (ctlr->rx_status)) {
+        errs += 2UL;
+    }
+
+    if (errs != 0UL) {
+        spi_port_clk_reset_pulse(ctlr, 2);
+    }
+}
+
+SECTION_SPI_TEXT static void
+spi_clear_status(struct spi_ctlr *ctlr)
+{
+    uint32_t val;
+
+    /* Write 1 to clear status register */
+    val = spi_slave_readl(ctlr, SPI_TRANSFER_STATUS_0);
+    spi_slave_writel(ctlr, val, SPI_TRANSFER_STATUS_0);
+    val = spi_slave_readl(ctlr, SPI_INTR_MASK_0);
+
+    if (NV_DRF_VAL(SPI, INTR_MASK, RDY_INTR_MASK, val) == 0) {
+        val = NV_FLD_SET_DRF_DEF(SPI, INTR_MASK , CS_INTR_MASK, ENABLE,
+        NV_FLD_SET_DRF_DEF(SPI, INTR_MASK, TX_FIFO_OVF_INTR_MASK, ENABLE,
+        NV_FLD_SET_DRF_DEF(SPI, INTR_MASK, RX_FIFO_OVF_INTR_MASK, ENABLE,
+        NV_FLD_SET_DRF_DEF(SPI, INTR_MASK, TX_FIFO_UNF_INTR_MASK, ENABLE,
+        NV_FLD_SET_DRF_DEF(SPI, INTR_MASK, RX_FIFO_UNF_INTR_MASK, ENABLE,
+        NV_FLD_SET_DRF_DEF(SPI, INTR_MASK, RDY_INTR_MASK, ENABLE,
+        val ))))));
+
+        spi_slave_writel(ctlr, val, SPI_INTR_MASK_0);
+    }
+
+    /* Clear FIFO status error if any */
+    val = spi_slave_readl(ctlr, SPI_FIFO_STATUS_0);
+    if (val & SPI_ERR) {
+        spi_slave_writel(ctlr, SPI_ERR | SPI_FIFO_ERROR |
+                    SPI_CS_INACTIVE_ERR,
+                    SPI_FIFO_STATUS_0);
+    }
+}
+
+SECTION_SPI_TEXT void
+spi_slave_isr(void *data)
+{
+    struct spi_ctlr *ctlr = (struct spi_ctlr *)data;
+    uint32_t        cmd1;
+    bool            isr_yield_flag = false;
+
+    cmd1 = spi_slave_readl(ctlr, SPI_COMMAND_0);
+    ctlr->status_reg = spi_slave_readl(ctlr, SPI_FIFO_STATUS_0);
+
+    if ((cmd1 & NV_DRF_DEF(SPI, COMMAND, Tx_EN, ENABLE)) != 0UL) {
+        ctlr->tx_status = ctlr->status_reg &
+                          (NV_DRF_DEF(SPI, FIFO_STATUS, TX_FIFO_UNF, ERROR) |
+                           NV_DRF_DEF(SPI, FIFO_STATUS, TX_FIFO_OVF, ERROR));
+    }
+
+    if ((cmd1 & NV_DRF_DEF(SPI, COMMAND, Rx_EN, ENABLE)) != 0UL) {
+        ctlr->rx_status = ctlr->status_reg &
+                          (NV_DRF_DEF(SPI, FIFO_STATUS, RX_FIFO_UNF, ERROR) |
+                           NV_DRF_DEF(SPI, FIFO_STATUS, RX_FIFO_OVF, ERROR));
+    }
+    spi_clear_status(ctlr);
+
+    if (((cmd1 & NV_DRF_DEF(SPI, COMMAND, Tx_EN, ENABLE)) == 0UL) &&
+            ((cmd1 & NV_DRF_DEF(SPI, COMMAND, Rx_EN, ENABLE)) == 0UL)) {
+            /* SPI: spurious interrupt */
+        goto out;
+    }
+
+    if (!ctlr->is_curr_dma_xfer) {
+        handle_pio_err_xfer(ctlr);
+    } else {
+        if (ctlr->slave_dma_support) {
+            handle_dma_err_xfer(ctlr);
+        }
+    }
+
+    UNUSED((spi_port_xfer_sync_end(ctlr)));
+
+out:
+    spi_port_isr_exit(ctlr, isr_yield_flag);
+}
+
+SECTION_SPI_TEXT static error_t
+spi_dma_init(struct spi_ctlr *ctlr)
+{
+    error_t ret = E_SUCCESS;
+
+    ret = spi_port_dma_init(ctlr);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    /* Full duplex transactions require 2 channels. Check your POR
+     * to ensure 2 channels are supported.
+     */
+    if (ctlr->en_full_duplex) {
+        /* check for 2 different dma channels if full duplex
+         * is supported.
+         */
+        if (ctlr->dma_chans.tx == ctlr->dma_chans.rx) {
+            ret = E_SPI_FD_MODE_NO_SUPPORT;
+            goto out;
+        }
+    }
+
+out:
+    return ret;
+}
+
+SECTION_SPI_TEXT static error_t
+spi_check_and_clear_fifo(struct spi_ctlr *ctlr)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t status;
+    uint32_t cnt = 0UL;
+
+    /* Make sure that Rx and Tx FIFO are empty */
+    status = spi_slave_readl(ctlr, SPI_FIFO_STATUS_0);
+    if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
+        /* flush the FIFO */
+        status = NV_FLD_SET_DRF_DEF(SPI, FIFO_STATUS,
+                                    RX_FIFO_FLUSH, FLUSH, status);
+        status = NV_FLD_SET_DRF_DEF(SPI, FIFO_STATUS,
+                                    TX_FIFO_FLUSH, FLUSH, status);
+        spi_slave_writel(ctlr, status, SPI_FIFO_STATUS_0);
+        while (cnt != SPI_FIFO_FLUSH_MAX_DELAY) {
+            status = spi_slave_readl(ctlr, SPI_FIFO_STATUS_0);
+            if ((status & SPI_FIFO_EMPTY) == SPI_FIFO_EMPTY) {
+                goto out;
+            }
+            udelay(1);
+            cnt += 1UL;
+        }
+        ret =  E_SPI_FIFO_NON_EMPTY;
+    }
+
+out:
+    return ret;
+}
+
+SECTION_SPI_TEXT static error_t
+spi_slave_start_dma_transfer(struct spi_ctlr *ctlr,
+                             struct spi_xfer *xfer)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t val = 0, cmd1;
+    uint32_t intr_mask = 0UL;
+    uint32_t len;
+    uint32_t burst_size;
+
+    /* For half duplex, ensure rx and tx transfers are not enabled.
+     * If rx and tx transfers are enabled, return error.
+     */
+    if (ctlr->dma_chans.tx == ctlr->dma_chans.rx) {
+        if ((ctlr->cur_direction & DATA_DIR_TX) &&
+                (ctlr->cur_direction & DATA_DIR_RX)) {
+            ret = E_SPI_XFER_NOT_SUPPORTED;
+            goto out;
+        }
+    }
+
+    val = NV_FLD_SET_DRF_NUM(SPI, DMA_BLK_SIZE, DMA_BLOCK_SIZE,
+                             (ctlr->curr_dma_words - 1), val);
+    spi_slave_writel(ctlr, val, SPI_DMA_BLK_SIZE_0);
+
+    if (ctlr->is_packed) {
+        len = DIV_ROUND_UP(ctlr->curr_dma_words * ctlr->bytes_per_word, 4) * 4;
+    } else {
+        len = ctlr->curr_dma_words * 4;
+    }
+
+    /* Set attention level based on length of transfer.
+     * DMA burst size and SPI trigger level should be same.
+     */
+    val = 0;
+    if (len & 0xF) {
+        val |= NV_DRF_DEF(SPI, DMA_CTL, TX_TRIG, TRIG1) |
+               NV_DRF_DEF(SPI, DMA_CTL, RX_TRIG, TRIG1);
+        burst_size = 1;
+    } else if (((len) >> 4) & 0x1) {
+        val |= NV_DRF_DEF(SPI, DMA_CTL, TX_TRIG, TRIG4) |
+               NV_DRF_DEF(SPI, DMA_CTL, RX_TRIG, TRIG4);
+        burst_size = 4;
+    } else {
+        val |= NV_DRF_DEF(SPI, DMA_CTL, TX_TRIG, TRIG8) |
+               NV_DRF_DEF(SPI, DMA_CTL, RX_TRIG, TRIG8);
+        burst_size = 8;
+    }
+
+    if (ctlr->cur_direction & DATA_DIR_TX) {
+        spi_copy_client_txbuf_to_spi_txbuf(ctlr, xfer);
+        ret = spi_port_start_tx_dma(ctlr, xfer, len, burst_size);
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+    }
+    if (ctlr->cur_direction & DATA_DIR_RX) {
+        ret = spi_port_start_rx_dma(ctlr, xfer, len, burst_size);
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+    }
+    spi_slave_writel(ctlr, val, SPI_DMA_CTL_0);
+    ctlr->dma_ctrl_reg_val = val;
+
+    intr_mask = NV_FLD_SET_DRF_DEF(SPI, INTR_MASK , CS_INTR_MASK, DISABLE,
+        NV_FLD_SET_DRF_DEF(SPI, INTR_MASK, TX_FIFO_OVF_INTR_MASK, DISABLE,
+        NV_FLD_SET_DRF_DEF(SPI, INTR_MASK, RX_FIFO_OVF_INTR_MASK, DISABLE,
+        NV_FLD_SET_DRF_DEF(SPI, INTR_MASK, TX_FIFO_UNF_INTR_MASK, DISABLE,
+        NV_FLD_SET_DRF_DEF(SPI, INTR_MASK, RX_FIFO_UNF_INTR_MASK, DISABLE,
+        NV_FLD_SET_DRF_DEF(SPI, INTR_MASK, RDY_INTR_MASK, DISABLE,
+        intr_mask ))))));
+
+    spi_slave_writel(ctlr, intr_mask, SPI_INTR_MASK_0);
+
+    ctlr->is_curr_dma_xfer = true;
+    cmd1 = ctlr->cmd1_reg_val;
+    if (ctlr->cur_direction & DATA_DIR_TX)
+        cmd1 |= NV_DRF_DEF(SPI, COMMAND, Tx_EN, ENABLE);
+    if (ctlr->cur_direction & DATA_DIR_RX)
+        cmd1 |= NV_DRF_DEF(SPI, COMMAND, Rx_EN, ENABLE);
+    spi_slave_writel(ctlr, cmd1, SPI_COMMAND_0);
+
+    val |= NV_DRF_DEF(SPI, DMA_CTL, DMA_EN, ENABLE);
+    spi_slave_writel(ctlr, val, SPI_DMA_CTL_0);
+
+out:
+    return ret;
+}
+
+SECTION_SPI_TEXT static error_t
+spi_slave_start_pio_transfer(struct spi_ctlr *ctlr,
+                             struct spi_xfer *xfer)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t val = 0UL;
+    uint32_t cur_words;
+    uint32_t intr_mask = SPI_INTR_DEFAULT_MASK;
+
+    if (ctlr->cur_direction & DATA_DIR_TX) {
+        cur_words = spi_fill_tx_fifo_from_client_txbuf(ctlr, xfer);
+    } else {
+        cur_words = ctlr->curr_dma_words;
+    }
+
+    val = NV_FLD_SET_DRF_NUM(SPI, DMA_BLK_SIZE, DMA_BLOCK_SIZE,
+                             (cur_words - 1), val);
+
+    spi_slave_writel(ctlr, val, SPI_DMA_BLK_SIZE_0);
+
+    intr_mask = NV_FLD_SET_DRF_DEF(SPI, INTR_MASK , CS_INTR_MASK, DISABLE,
+        NV_FLD_SET_DRF_DEF(SPI, INTR_MASK, TX_FIFO_UNF_INTR_MASK, DISABLE,
+        NV_FLD_SET_DRF_DEF(SPI, INTR_MASK, RX_FIFO_UNF_INTR_MASK, DISABLE,
+        NV_FLD_SET_DRF_DEF(SPI, INTR_MASK, RDY_INTR_MASK, DISABLE,
+        intr_mask ))));
+
+    spi_slave_writel(ctlr, intr_mask, SPI_INTR_MASK_0);
+
+    val = 0UL;
+    spi_slave_writel(ctlr, val, SPI_DMA_CTL_0);
+    ctlr->dma_ctrl_reg_val = val;
+
+    ctlr->is_curr_dma_xfer = false;
+    val = ctlr->cmd1_reg_val;
+    if (ctlr->cur_direction & DATA_DIR_TX) {
+        val |= NV_DRF_DEF(SPI, COMMAND, Tx_EN, ENABLE);
+    }
+    if (ctlr->cur_direction & DATA_DIR_RX) {
+        val |= NV_DRF_DEF(SPI, COMMAND, Rx_EN, ENABLE);
+    }
+    spi_slave_writel(ctlr, val, SPI_COMMAND_0);
+
+    val = NV_FLD_SET_DRF_DEF(SPI, COMMAND, PIO, PIO, val);
+    spi_slave_writel(ctlr, val, SPI_COMMAND_0);
+    spi_slave_ext_clk_enable(ctlr, true);
+
+    return ret;
+}
+
+SECTION_SPI_TEXT static void
+spi_configure_cmd1_reg(struct spi_ctlr *ctlr,
+                       struct spi_xfer *xfer)
+{
+    uint32_t  command1;
+    uint32_t  cs_pol_bit[MAX_CHIP_SELECT] = {
+                NV_DRF_DEF(SPI, COMMAND, CS_POL_INACTIVE0, HIGH),
+                NV_DRF_DEF(SPI, COMMAND, CS_POL_INACTIVE1, HIGH),
+                NV_DRF_DEF(SPI, COMMAND, CS_POL_INACTIVE2, HIGH),
+                NV_DRF_DEF(SPI, COMMAND, CS_POL_INACTIVE3, HIGH),
+    };
+
+    command1 = ctlr->def_cmd1_reg_val;
+    if (xfer->mode & TEGRA_SPI_CS_HIGH) {
+        command1 &= ~cs_pol_bit[xfer->chip_select];
+    } else {
+        command1 |= cs_pol_bit[xfer->chip_select];
+    }
+
+    ctlr->def_cmd1_reg_val = command1;
+
+    command1 = NV_FLD_SET_DRF_NUM(SPI, COMMAND, BIT_LENGTH,
+                                  (xfer->bits_per_word - 1), command1);
+    command1 = NV_FLD_SET_DRF_NUM(SPI, COMMAND, MODE,
+                                  (xfer->mode & 0x3), command1);
+    command1 = NV_FLD_SET_DRF_DEF(SPI, COMMAND, CS_SW_HW, SOFTWARE, command1);
+    command1 = NV_FLD_SET_DRF_NUM(SPI, COMMAND, CS_SW_VAL,
+                                  (xfer->mode & TEGRA_SPI_CS_HIGH), command1);
+
+    if (xfer->mode & TEGRA_SPI_LSBYTE_FIRST) {
+        command1 = NV_FLD_SET_DRF_DEF(SPI, COMMAND, En_LE_Byte,
+                                      FIRST, command1);
+    } else {
+        command1 = NV_FLD_SET_DRF_DEF(SPI, COMMAND, En_LE_Byte,
+                                      LAST, command1);
+    }
+
+    if (xfer->mode & TEGRA_SPI_LSB_FIRST) {
+        command1 = NV_FLD_SET_DRF_DEF(SPI, COMMAND, En_LE_Bit, FIRST, command1);
+    } else {
+        command1 = NV_FLD_SET_DRF_DEF(SPI, COMMAND, En_LE_Bit, LAST, command1);
+    }
+
+    command1 = NV_FLD_SET_DRF_DEF(SPI, COMMAND, BIDIR, NORMAL, command1);
+
+    if (ctlr->is_packed) {
+        command1 |= NV_DRF_DEF(SPI, COMMAND, PACKED, ENABLE);
+    } else {
+        command1 &= ~(NV_DRF_DEF(SPI, COMMAND, PACKED, ENABLE));
+    }
+
+    command1 = NV_FLD_SET_DRF_DEF(SPI, COMMAND, CS_SEL, CS0, command1);
+    command1 = NV_FLD_SET_DRF_DEF(SPI, COMMAND, Tx_EN, DISABLE, command1);
+    command1 = NV_FLD_SET_DRF_DEF(SPI, COMMAND, Rx_EN, DISABLE, command1);
+
+    command1 = NV_FLD_SET_DRF_NUM(SPI, COMMAND, CS_SEL, xfer->chip_select,
+                                  command1);
+
+    spi_slave_writel(ctlr, command1, SPI_COMMAND_0);
+    ctlr->cmd1_reg_val = command1;
+
+}
+
+SECTION_SPI_TEXT static error_t
+spi_slave_handle_message(struct spi_ctlr *ctlr,
+                         struct spi_xfer *xfer)
+{
+    error_t ret = E_SUCCESS;
+    bool    reset = false;
+
+    if (!ctlr->is_curr_dma_xfer) {
+        if (ctlr->cur_direction & DATA_DIR_RX) {
+            spi_read_rx_fifo_to_client_rxbuf(ctlr, xfer);
+            ctlr->cur_pos = ctlr->cur_rx_pos;
+        } else {
+            ctlr->cur_pos = ctlr->cur_tx_pos;
+        }
+    } else {
+        if (ctlr->tx_dma_status != E_SUCCESS) {
+            if (ctlr->cur_direction & DATA_DIR_TX) {
+                spi_port_tx_dma_xfer_abort(ctlr);
+                reset = true;
+            }
+        }
+        if (ctlr->tx_dma_status != E_SUCCESS) {
+            if (ctlr->cur_direction & DATA_DIR_RX) {
+                spi_port_rx_dma_xfer_abort(ctlr);
+                reset = true;
+            }
+        }
+        if (reset) {
+            spi_port_clk_reset_pulse(ctlr, 2);
+            ret = E_SPI_DMA_XFER_FAIL;
+            goto out;
+        }
+
+        if (ctlr->cur_direction & DATA_DIR_TX) {
+            ctlr->cur_tx_pos += ctlr->curr_dma_words * ctlr->bytes_per_word;
+            ctlr->cur_pos = ctlr->cur_tx_pos;
+        }
+        if (ctlr->cur_direction & DATA_DIR_RX) {
+            spi_copy_spi_rxbuf_to_client_rxbuf(ctlr, xfer);
+            ctlr->cur_pos = ctlr->cur_rx_pos;
+        }
+    }
+
+out:
+    return ret;
+}
+
+SECTION_SPI_TEXT static error_t
+spi_wait_on_message_xfer(struct spi_ctlr *ctlr)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t int_source;
+    uint32_t cmd1_reg_val;
+    uint32_t prog_byte_per_word;
+    uint32_t rx_full_count;
+    bool     xfer_timeout = false;
+
+    cmd1_reg_val = spi_slave_readl(ctlr, SPI_COMMAND_0);
+    /*
+     * For synchronous transfers, the driver relies on the port specific
+     * implementation of some kind of synchronization mechanism until the
+     * SPI transfer is complete.
+     */
+    ret = spi_port_xfer_sync(ctlr, SPI_TRANSFER_TIMEOUT);
+    if (ret == E_SUCCESS) {
+        int_source = ctlr->status_reg;
+    } else {
+        xfer_timeout = true;
+        /* disable PIO bit if transfer timed out */
+        if (ctlr->is_curr_dma_xfer == false) {
+            spi_slave_writel(ctlr,(0x7fffffff & cmd1_reg_val), SPI_COMMAND_0);
+        }
+        spi_port_clk_reset_pulse(ctlr, 2);
+        spi_check_and_clear_fifo(ctlr);
+    }
+
+    if (xfer_timeout || ctlr->rx_status || ctlr->tx_status) {
+        if (ctlr->is_curr_dma_xfer) {
+            if (ctlr->cur_direction & DATA_DIR_TX) {
+                spi_port_tx_dma_xfer_abort(ctlr);
+            }
+            if (ctlr->cur_direction & DATA_DIR_RX) {
+                spi_port_rx_dma_xfer_abort(ctlr);
+            }
+        }
+        ret = E_SPI_XFER_ERR;
+        goto out;
+    }
+
+    if (int_source & SPI_CS_INACTIVE_ERR) {
+        rx_full_count = NV_DRF_VAL(SPI, FIFO_STATUS,
+                                   RX_FIFO_FULL_COUNT, int_source);
+        prog_byte_per_word = spi_slave_readl(ctlr, SPI_DMA_BLK_SIZE_0);
+        /* CS_INACTIVE deassert interrupt is considered as error only when
+         * number of bytes transferred are less than programmed bytes
+         */
+        if (((ctlr->cur_direction & DATA_DIR_RX) &&
+            (rx_full_count != prog_byte_per_word + 1)) ||
+            ((ctlr->cur_direction & DATA_DIR_TX) &&
+            !(int_source & SPI_TX_FIFO_EMPTY))) {
+                spi_port_clk_reset_pulse(ctlr, 2);
+                spi_check_and_clear_fifo(ctlr);
+                ret = E_SPI_XFER_ERR;
+        }
+    }
+
+out:
+    return ret;
+}
+
+SECTION_SPI_TEXT static void
+spi_init_ctlr_context(struct spi_ctlr *ctlr)
+{
+    ctlr->cur_pos = 0UL;
+    ctlr->cur_rx_pos = 0UL;
+    ctlr->cur_tx_pos = 0UL;
+    ctlr->tx_status = 0UL;
+    ctlr->rx_status = 0UL;
+    ctlr->cur_direction = 0UL;
+}
+
+SECTION_SPI_TEXT static error_t
+spi_start_transfer_one(struct spi_ctlr *ctlr,
+                       struct spi_xfer *xfer)
+{
+    error_t   ret = E_SUCCESS;
+    uint32_t  total_fifo_words;
+
+    spi_init_ctlr_context(ctlr);
+
+    ctlr->cur_xfer = xfer;
+    total_fifo_words = spi_calculate_curr_xfer_param(ctlr, xfer);
+
+    if (xfer->rx_buf != NULL) {
+        ctlr->cur_direction |= DATA_DIR_RX;
+    }
+    if (xfer->tx_buf != NULL) {
+        ctlr->cur_direction |= DATA_DIR_TX;
+    }
+
+    /* Return if neither RX or TX is requested OR
+     * not all words are available
+     */
+    if ((ctlr->cur_direction == 0UL) ||
+        ((xfer->len % ctlr->bytes_per_word) != 0UL)) {
+        ret = E_SPI_INVALID_PARAM;
+        goto out;
+    }
+
+    spi_clear_status(ctlr);
+
+    spi_configure_cmd1_reg(ctlr, xfer);
+
+    /* Make sure that Rx and Tx FIFO are empty */
+    ret = spi_check_and_clear_fifo(ctlr);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    if (total_fifo_words > SPI_FIFO_DEPTH) {
+        ret = spi_slave_start_dma_transfer(ctlr, xfer);
+    } else {
+        ret = spi_slave_start_pio_transfer(ctlr, xfer);
+    }
+
+out:
+    return ret;
+}
+
+SECTION_SPI_TEXT static error_t
+spi_slave_transfer_remain_message(struct spi_ctlr *ctlr,
+                                  struct spi_xfer *xfer)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t total_fifo_words;
+
+    total_fifo_words = spi_calculate_curr_xfer_param(ctlr, xfer);
+    if (ctlr->is_curr_dma_xfer) {
+        /* Make sure that Rx and Tx FIFO are empty */
+        ret = spi_check_and_clear_fifo(ctlr);
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+
+        if (total_fifo_words > SPI_FIFO_DEPTH) {
+            ret = spi_slave_start_dma_transfer(ctlr, xfer);
+        } else {
+            ret = spi_slave_start_pio_transfer(ctlr, xfer);
+        }
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+    } else {
+        ret = spi_slave_start_pio_transfer(ctlr, xfer);
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+    ret = spi_wait_on_message_xfer(ctlr);
+
+out:
+    return ret;
+}
+
+SECTION_SPI_TEXT error_t
+spi_slave_transfer(struct spi_ctlr *ctlr,
+                   struct spi_xfer *xfer)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL || xfer == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_SPI_NULL_PTR;
+        goto out;
+    }
+
+    if (xfer->len == 0) {
+        goto out;
+    }
+
+    ctlr->busy = true;
+    /* switch off ext clk before programming registers */
+    spi_slave_ext_clk_enable(ctlr, false);
+    spi_port_clk_reset_pulse(ctlr, 2);
+
+    if (xfer->flags & BIT(TEGRA_SPI_XFER_FIRST_MSG)) {
+        ret = spi_start_transfer_one(ctlr, xfer);
+    } else {
+        ret = spi_slave_transfer_remain_message(ctlr, xfer);
+    }
+
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    ret = spi_wait_on_message_xfer(ctlr);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    ret = spi_slave_handle_message(ctlr, xfer);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    if (ctlr->cur_pos == xfer->len) {
+        goto out;
+    }
+
+    while (1) {
+        ret = spi_slave_transfer_remain_message(ctlr, xfer);
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+
+        ret = spi_slave_handle_message(ctlr, xfer);
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+
+        if (ctlr->cur_pos == xfer->len) {
+            break;
+        }
+    }
+
+out:
+    if (ctlr != NULL) {
+        ctlr->busy = false;
+    }
+
+    return ret;
+}
+
+SECTION_SPI_INIT_TEXT error_t
+spi_slave_setup(struct spi_ctlr *ctlr,
+                struct spi_client_setting *setting)
+{
+    error_t                   ret = E_SUCCESS;
+    struct spi_client_setting *cdata;
+
+    if (ctlr == NULL || setting == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_SPI_NULL_PTR;
+        goto out;
+    }
+
+    if (setting->spi_max_clk_rate == 0UL) {
+        ret = E_SPI_INVALID_CLK_RATE;
+        goto out;
+    }
+
+    cdata = &ctlr->cdata[setting->chip_select];
+    cdata->chip_select = setting->chip_select;
+    cdata->spi_max_clk_rate = setting->spi_max_clk_rate;
+    cdata->spi_no_dma = setting->spi_no_dma;
+
+    ret = spi_port_clk_set_rate(ctlr, (setting->spi_max_clk_rate * 3) >> 1);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    ctlr->spi_clk_rate = (setting->spi_max_clk_rate * 3) >> 1;
+
+out:
+    return ret;
+}
+
+SECTION_SPI_INIT_TEXT error_t
+spi_slave_init(struct spi_ctlr *ctlr,
+               struct spi_slave_init_setup *setting)
+{
+    error_t ret = E_SUCCESS;
+
+    /* sanity check the controller pointer */
+    if (ctlr == NULL) {
+        INLINE_RFD(MISRA, FP, Rule_10_8, "Approval: JIRA TID-412, DR: SWE-FSP-021-SWSADR.docx");
+        ret = E_SPI_NULL_PTR;
+        goto out;
+    }
+
+    /* sanity check for setting pointer */
+    if (setting == NULL) {
+        setting = &default_slave_setting;
+    }
+
+    ctlr->spi_clk_rate = (setting->spi_max_clk_rate) ?
+                         setting->spi_max_clk_rate :
+                         default_slave_setting.spi_max_clk_rate;
+
+    spi_slave_dma_setup(ctlr, setting);
+
+    ctlr->busy = false;
+
+    /* Set slave controller clk 1.5 times the bus frequency */
+    ret = spi_port_clk_set_rate(ctlr, ((ctlr->spi_clk_rate *3) >>1));
+    if (ret!= E_SUCCESS) {
+        goto out;
+    }
+
+    /* enable the clock for the UART controller */
+    ret = spi_port_clk_enable(ctlr);
+    if (ret!= E_SUCCESS) {
+        goto out;
+    }
+
+    /* reset the SPI slave controller */
+    ret = spi_port_clk_reset_pulse(ctlr, 2);
+    if (ret!= E_SUCCESS) {
+        goto out;
+    }
+
+    spi_slave_ext_clk_enable(ctlr, false);
+
+    /*
+     * FIXME: DMA path is not yet verified for spi-slave driver.
+     * Currently we support PIO mode only.
+     */
+    if (ctlr->slave_dma_support) {
+        ret = spi_dma_init(ctlr);
+        if (ret != E_SUCCESS) {
+            ret = E_SPI_INIT_FAIL;
+            spi_port_clk_disable(ctlr);
+            goto out;
+        }
+    }
+
+    if (ctlr->conf.irq != UINT32_MAX) {
+        /* register irq handler and enable irq */
+        ret = irq_safe_set_handler(ctlr->conf.irq, spi_slave_isr, ctlr);
+        if (ret != E_SUCCESS) {
+            spi_port_clk_disable(ctlr);
+            goto out;
+        }
+        ret = irq_safe_enable(ctlr->conf.irq);
+        if (ret != E_SUCCESS) {
+            spi_port_clk_disable(ctlr);
+            goto out;
+        }
+    }
+
+    /* port specific SPI controller setup callout */
+    ret = spi_port_init(ctlr);
+    if (ret != E_SUCCESS) {
+        spi_port_clk_disable(ctlr);
+        goto out;
+    }
+
+    ctlr->def_cmd1_reg_val = NV_DRF_DEF(SPI, COMMAND, M_S, SLAVE) |
+                             NV_DRF_DEF(SPI, COMMAND, En_LE_Byte, FIRST) |
+                             NV_DRF_DEF(SPI, COMMAND, CS_SEL, CS0);
+    spi_slave_writel(ctlr, ctlr->def_cmd1_reg_val, SPI_COMMAND_0);
+
+out:
+    return ret;
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/ssp/module-ssp-config.mk b/spe-freertos-bsp/fsp/source/drivers/ssp/module-ssp-config.mk
new file mode 100644
index 0000000..ccd9163
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/ssp/module-ssp-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-ssp-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_SSP_CONFIG               := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_SSP_DEPENDS              := CPL FSP_COMMON
+$(foreach _,$(MODULE_SSP_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_SSP_DRIVERS_DIR           = $(FSP_COMMON_REPO)/drivers/ssp
+MODULE_SSP_SOURCE_DIR            = $(MODULE_SSP_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_SSP_INCLUDES              =
diff --git a/spe-freertos-bsp/fsp/source/drivers/ssp/module-ssp.mk b/spe-freertos-bsp/fsp/source/drivers/ssp/module-ssp.mk
new file mode 100644
index 0000000..ceb063f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/ssp/module-ssp.mk
@@ -0,0 +1,70 @@
+#
+# Copyright (c) 2020-2023, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-ssp.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_SSP_NAME                 := SSP
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_SSP_DEFINED              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_SSP_DEPENDS              := SSP CPL
+$(foreach _,$(CONFIG_SSP_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_SSP_C_SRC                 =
+
+ifeq ($(NVRISCV_FEATURE_SSP), y)
+MODULE_SSP_C_SRC                += $(MODULE_SSP_DRIVERS_DIR)/ssp.c
+endif
+#
+# Assembly source
+MODULE_SSP_ASM_SRC               =
+
+#
+# Special C Flags
+MODULE_SSP_C_FLAGS               =
+
+ifeq ($(NVRISCV_FEATURE_SSP), y)
+MODULE_SSP_C_FLAGS += -fstack-protector-strong
+MODULE_SSP_C_FLAGS += --param=ssp-buffer-size=4
+MODULE_SSP_C_FLAGS += -Wstack-protector
+endif
+
+#
+# Special ASM Flags
+MODULE_SSP_ASM_FLAGS             =
diff --git a/spe-freertos-bsp/fsp/source/drivers/ssp/ssp.c b/spe-freertos-bsp/fsp/source/drivers/ssp/ssp.c
new file mode 100644
index 0000000..34d92fa
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/ssp/ssp.c
@@ -0,0 +1,121 @@
+/* _NVRM_COPYRIGHT_BEGIN_
+ *
+ * Copyright 2020 by NVIDIA Corporation.  All rights reserved.  All
+ * information contained herein is proprietary and confidential to NVIDIA
+ * Corporation.  Any use, reproduction, or disclosure without the written
+ * permission of NVIDIA Corporation is prohibited.
+ *
+ * _NVRM_COPYRIGHT_END_
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <misc/gcc_attrs.h>
+#include <cpu/shutdown.h>
+#include <ssp/ssp.h>
+#include <error/common-errors.h>
+#if !NVRISCV_FEATURE_SSP_FORCE_SW_CANARY
+#include <misc/nvmisc_drf.h>
+#include <scp/scp.h>
+#endif // NVRISCV_FEATURE_SSP_FORCE_SW_CANARY
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx")
+
+#define CHECK_ERROR_OR_GOTO(X, Y)   \
+({                                  \
+    ret = X;                        \
+    if (ret != E_SUCCESS)           \
+    {                               \
+       goto Y;                      \
+    }                               \
+})
+
+/*
+ * For baremetal image, it can stay as is.
+ * For multi-partition images, it likely nees to be written in some shared data
+ * segment and then stored/restored on partition entry/exit
+ */
+GCC_ATTR_SECTION(".data.libnvriscv.__stack_chk_guard")
+uintptr_t __stack_chk_guard  = 0;
+
+#if !NVRISCV_FEATURE_SSP_FORCE_SW_CANARY
+GCC_ATTR_SECTION(".data.libnvriscv.ssp_scpdma_buf")
+GCC_ATTR_ALIGNED(SCP_RAND_SIZE) static uintptr_t ssp_scpdma_buf[SCP_RAND_SIZE / sizeof(uint64_t)] = {0,};
+#endif
+
+GCC_ATTR_NAKED
+GCC_ATTR_NORETURN
+GCC_ATTR_NO_SSP
+void __stack_chk_fail(void)
+{
+#if NVRISCV_FEATURE_SSP_ENABLE_FAIL_HOOK
+    __asm__("jal ssp_check_fail_hook");
+#endif // NVRISCV_FEATURE_SSP_ENABLE_FAIL_HOOK
+    __asm__("j riscv_panic");
+}
+
+GCC_ATTR_NO_SSP
+void ssp_set_canary(uintptr_t canary)
+{
+    __stack_chk_guard = canary;
+}
+
+uintptr_t ssp_get_canary(void)
+{
+    return __stack_chk_guard;
+}
+
+#if !NVRISCV_FEATURE_SSP_FORCE_SW_CANARY
+GCC_ATTR_NO_SSP
+error_t ssp_generate_and_set_canary_with_init(void)
+{
+    error_t ret = E_SUCCESS;
+
+    CHECK_ERROR_OR_GOTO((scp_Init(SCP_INIT_FLAG_DEFAULT)), out);
+
+    CHECK_ERROR_OR_GOTO((scp_Configure_Rand(SCP_RAND_CONFIG_DEFAULT)), out);
+
+    CHECK_ERROR_OR_GOTO((scp_Start_Rand()), out);
+
+    CHECK_ERROR_OR_GOTO((ssp_generate_and_set_canary()), out);
+
+    ret = scp_Shutdown();
+
+out:
+    return ret;
+
+}
+
+GCC_ATTR_NO_SSP
+error_t ssp_generate_and_set_canary(void)
+{
+    error_t ret = E_SUCCESS;
+    uint32_t attempts=10; // Try 10 times to get proper number
+
+    ssp_scpdma_buf[0] = 0;
+
+    while (attempts--)
+    {
+        CHECK_ERROR_OR_GOTO((scp_Get_Rand((uintptr_t)&ssp_scpdma_buf, sizeof(ssp_scpdma_buf), 0)), out);
+
+        if (ssp_scpdma_buf[0] != 0)
+        {
+            ssp_set_canary(ssp_scpdma_buf[0]);
+            goto out;
+        }
+    }
+
+    ret = E_TIMEOUT;
+
+out:
+    // Wipe buffer to avoid canary leak
+    ssp_scpdma_buf[0] = 0;
+    return ret;
+}
+#endif // NVRISCV_FEATURE_SSP_FORCE_SW_CANARY
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/tke/module-tke-config.mk b/spe-freertos-bsp/fsp/source/drivers/tke/module-tke-config.mk
new file mode 100644
index 0000000..f984654
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/tke/module-tke-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-tke-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_TKE_CONFIG               := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_TKE_DEPENDS              := SOC CLUSTER CPL OSA FSP_COMMON
+$(foreach _,$(MODULE_TKE_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_TKE_DRIVERS_DIR           = $(FSP_COMMON_REPO)/drivers/tke
+MODULE_TKE_SOURCE_DIR            = $(MODULE_TKE_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_TKE_INCLUDES              =
diff --git a/spe-freertos-bsp/fsp/source/drivers/tke/module-tke.mk b/spe-freertos-bsp/fsp/source/drivers/tke/module-tke.mk
new file mode 100644
index 0000000..9e88fe4
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/tke/module-tke.mk
@@ -0,0 +1,66 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-tke.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_TKE_NAME                 := TKE
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_TKE_DEFINED              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_TKE_DEPENDS              := TKE SOC CPL OSA
+$(foreach _,$(CONFIG_TKE_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_TKE_C_SRC                 =
+MODULE_TKE_C_SRC                += $(MODULE_TKE_DRIVERS_DIR)/tke-tegra.c
+MODULE_TKE_C_SRC                += $(MODULE_TKE_DRIVERS_DIR)/tke/tke-tegra-udelay.c
+MODULE_TKE_C_SRC                += $(MODULE_TKE_DRIVERS_DIR)/tke/tke-tegra-tsc-fixed.c
+MODULE_TKE_C_SRC                += $(CPL_SOC_IDS)/tke-tegra-ids.c
+
+#
+# Assembly source
+MODULE_TKE_ASM_SRC               =
+MODULE_TKE_ASM_SRC              += $(CPL_SOC_PORT)/tke-irq.S
+
+#
+# Special C Flags
+MODULE_TKE_C_FLAGS               =
+
+#
+# Special ASM Flags
+MODULE_TKE_ASM_FLAGS             =
diff --git a/spe-freertos-bsp/fsp/source/drivers/tke/tke-tegra-tsc-fixed.c b/spe-freertos-bsp/fsp/source/drivers/tke/tke-tegra-tsc-fixed.c
new file mode 100644
index 0000000..4b1a33f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/tke/tke-tegra-tsc-fixed.c
@@ -0,0 +1,242 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                 // for uint64_t, uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>         // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <ospl/rtos-port.h>         // for rtosTICK_RATE_MS
+#include <misc/bitops.h>            // for hilo_to_64, FSP__MISC__BITOPS_H
+#include <misc/macros.h>            // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <tke/sections-tke.h>       // Immune from CT_ASSERT protection
+#include <tke/tke-tegra.h>          // for tegra_tke_get_tsc64, FSP__TKE__TK...
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__TKE__TKE_TEGRA_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Number of nanoseconds per tic of TSC
+ */
+#define TEGRA_TKE_TSC_NS_PER_TIC        32U
+
+/**
+ * div_by_1000()        - return value divided by 1000
+ *
+ * @value:      64-bit value that is to be divided by 1000
+ *
+ * This function will divide a 64-bit value by 1000.  It will do it so
+ * as not to pull in the general 64-bit divide code.
+ *
+ * Return Value:
+ *      64-bit value representing the input divided by 1000.
+ */
+SECTION_TKE_TEXT static uint64_t
+div_by_1000(const uint64_t value)
+{
+    uint32_t    value_hi;
+    uint32_t    value_lo;
+    uint64_t    result;
+
+    /*
+     * There isn't a 64-bit divide on the R5 and to avoid
+     * pulling in a lot of library code, a bit of a "cheat"
+     * is being done here.
+     *
+     * The idea is that if value fits in 32-bits then perform
+     * a 32-bit divide and expand it back to 64-bits (where it
+     * is known that the upper 32-bits will be 0).
+     *
+     * If the upper 32-bits of value are not zero, then approximate
+     * the divide with some shifts and adds.  Since the result is
+     * being used by timer functions, super high accuracy is not
+     * absolutely required.
+     */
+    INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-559, DR: SWE-FSP-048-SWSADR.docx");
+    value_hi = HI32(value);
+    if (value_hi == 0U) {
+        INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-559, DR: SWE-FSP-048-SWSADR.docx");
+        value_lo = LOW32(value);
+        value_lo /= 1000U;
+        result = PACK64(value_lo, value_hi);
+    } else {
+        /*
+         * Approximate dividing by 1000
+         *
+         * Division is really an approximation and is really
+         * just multiplication by the reciprocal (e.g. x / 1000
+         * is equivalent to x * 1/1000).  So what the code is
+         * doing is multiplying the value by 1/1000 (or the
+         * approximation thereof).
+         *
+         * The series for x/1000 (for at least to the accuracy we
+         * need) is:
+         * x/1000 ~= x/2^10 + x/2^16 + x/2^17 + x/2^21 + x/2^24
+         *
+         * It could argued that for the timing needs that only the
+         * first term is sufficient but computing the extra terms
+         * is not expensive and results in a closer approximation.
+         */
+    START_RFD_BLOCK(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+        result = value >> 10;
+        result += value >> 16;
+        result += value >> 17;
+        result += value >> 21;
+        result += value >> 24;
+        END_RFD_BLOCK(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    }
+
+    return result;
+}
+
+/**
+ * tegra_tke_convert_usecs_to_ticks()      - Convert a microsecond value to ticks
+ *
+ * @value:              a value in microseconds to be converted
+ *
+ * This function will covert a value that is represented in microseconds and
+ * convert that to the equivalent number of ticks (with lower resolution of
+ * course).
+ *
+ * Return Values:
+ *      number of ticks that represents the value
+ */
+SECTION_TKE_TEXT uint64_t
+tegra_tke_convert_usecs_to_ticks(const uint64_t value)
+{
+    uint64_t    ticks;
+
+    ticks = div_by_1000(value) / rtosTICK_RATE_MS;
+
+    return ticks;
+}
+
+/* TSC timestamp at nanosecond resolution */
+SECTION_TKE_TEXT uint64_t
+tegra_tke_get_tsc_ns(void)
+{
+        /* TSC (cntfid0) is usually 31.25MHz, cntperiod is 32 ns */
+        return tegra_tke_get_tsc64() * TEGRA_TKE_TSC_NS_PER_TIC;
+}
+
+/* Convert nanosecond to TSC timestamp*/
+SECTION_TKE_TEXT uint64_t
+tegra_tke_ns_to_tsc(uint64_t ns)
+{
+        /* TSC is 31.25MHz = 32 ns, devide by 32*/
+        return (ns / TEGRA_TKE_TSC_NS_PER_TIC);
+}
+
+/* Convert TSC timestamp to nanosecond resolution */
+SECTION_TKE_TEXT uint64_t
+tegra_tke_tsc_to_ns(uint64_t tsc)
+{
+        /* TSC is 31.25MHz = 32 ns */
+        INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+        return tsc * TEGRA_TKE_TSC_NS_PER_TIC;
+}
+
+SECTION_TKE_TEXT uint64_t
+tegra_tke_get_elapsed_usec(uint32_t prev_tsc_hi, uint32_t prev_tsc_low)
+{
+        uint64_t result, curr_tsc, prev_tsc;
+
+        curr_tsc = tegra_tke_get_tsc64();
+        prev_tsc = hilo_to_64(prev_tsc_hi, prev_tsc_low);
+
+        /* cntfid0 holds the base frequency of the tsc.
+         * This will always be the frequency tsc runs.
+         * There is no plan to change it for tegra
+         */
+        INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+        result = div_by_1000((curr_tsc - prev_tsc) * TEGRA_TKE_TSC_NS_PER_TIC);
+
+        return result;
+}
+
+/**
+ * tegra_tke_get_elapsed_usecs64()  - Return elapsed microseconds
+ *
+ * @start:      value of TSC at the start of the period of when
+ *              the elapsed time is being computed.
+ *
+ * Return Value:
+ *      the number of microseconds that have elapsed between when
+ *      the start time was taken and this function called.  This is
+ *      a 64-bit value.
+ */
+SECTION_TKE_TEXT uint64_t
+tegra_tke_get_elapsed_usecs64(const uint64_t start)
+{
+    uint64_t    elapsed;
+    uint64_t    now;
+    uint64_t    elapsed_tsc;
+
+    now = tegra_tke_get_tsc64();
+
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    elapsed_tsc = now - start;
+
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    elapsed = div_by_1000(elapsed_tsc * TEGRA_TKE_TSC_NS_PER_TIC);
+
+    return elapsed;
+}
+
+SECTION_TKE_INIT_TEXT void
+tegra_tsc_init(void)
+{
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/tke/tke-tegra-tsc-var.c b/spe-freertos-bsp/fsp/source/drivers/tke/tke-tegra-tsc-var.c
new file mode 100644
index 0000000..2e0d0b8
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/tke/tke-tegra-tsc-var.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2015-2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                 // for uint64_t, uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>         // for CT_ASSERT
+#include <soc-common/hw-const.h>    /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>        // for NV_ADDRESS_MAP_TSC_IMPL_BASE
+
+/* Late FSP headers */
+#include <misc/bitops.h>            // for hilo_to_64, FSP__MISC__BITOPS_H
+#include <reg-access/reg-access.h>  // for readl, FSP__REG_ACCESS__REG_ACCESS_H
+
+/* Module-specific FSP headers */
+#include <tke/sections-tke.h>       // Immune from CT_ASSERT protection
+#include <tke/tke-tegra-regs.h>     // for FSP__TKE__TKE_TEGRA_REGS_H, TSC_B...
+#include <tke/tke-tegra.h>          // for tegra_tke_get_tsc64, FSP__TKE__TK...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__TKE__TKE_TEGRA_REGS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__TKE__TKE_TEGRA_H, "Header file missing or invalid.")
+
+static uint32_t cntfid0         SECTION_TKE_DATA;
+static uint32_t cntperiod       SECTION_TKE_DATA;
+
+/* TSC timestamp at nanosecond resolution */
+SECTION_TKE_TEXT uint64_t
+tegra_tke_get_tsc_ns(void)
+{
+        /* TSC (cntfid0) is usually 31.25MHz, cntperiod is 32 ns */
+        return tegra_tke_get_tsc64() * cntperiod;
+}
+
+/* Convert nanosecond to TSC timestamp*/
+SECTION_TKE_TEXT uint64_t
+tegra_tke_ns_to_tsc(uint64_t ns)
+{
+        /* TSC is 31.25MHz = 32 ns, devide by 32*/
+        return (cntperiod != 0U) ? (ns / cntperiod) : 0ULL;
+}
+
+/* Convert TSC timestamp to nanosecond resolution */
+SECTION_TKE_TEXT uint64_t
+tegra_tke_tsc_to_ns(uint64_t tsc)
+{
+        /* TSC is 31.25MHz = 32 ns */
+        return tsc * cntperiod;
+}
+
+SECTION_TKE_TEXT uint64_t
+tegra_tke_get_elapsed_usec(uint32_t prev_tsc_hi, uint32_t prev_tsc_low)
+{
+        uint64_t result, curr_tsc, prev_tsc;
+
+        curr_tsc = tegra_tke_get_tsc64();
+        prev_tsc = hilo_to_64(prev_tsc_hi, prev_tsc_low);
+
+        /* cntfid0 holds the base frequency of the tsc.
+         * This will always be the frequency tsc runs.
+         * There is no plan to change it for tegra
+         */
+        result = (curr_tsc - prev_tsc) * cntperiod / 1000;
+
+        return result;
+}
+
+/**
+ * tegra_tke_get_elapsed_usecs64()  - Return elapsed microseconds
+ *
+ * @start:      value of TSC at the start of the period of when
+ *              the elapsed time is being computed.
+ *
+ * Return Value:
+ *      the number of microseconds that have elapsed between when
+ *      the start time was taken and this function called.  This is
+ *      a 64-bit value.
+ */
+SECTION_TKE_TEXT uint64_t
+tegra_tke_get_elapsed_usecs64(const uint64_t start)
+{
+    uint64_t    elapsed;
+    uint64_t    now;
+    uint64_t    elapsed_tsc;
+
+    now = tegra_tke_get_tsc64();
+
+    elapsed_tsc = now - start;
+
+    elapsed = (elapsed_tsc * cntperiod) / 1000;
+
+    return elapsed;
+}
+
+SECTION_TKE_INIT_TEXT void
+tegra_tsc_init(void)
+{
+        uint32_t m0, r0, d0;
+        uint32_t val;
+
+        val = readl(NV_ADDRESS_MAP_TSC_IMPL_BASE + TSC_MTSCANNR_0);
+
+        m0 = (val & TSC_MTSCANNR_0_M0_MASK) >> TSC_MTSCANNR_0_M0_SHIFT;
+        r0 = (val & TSC_MTSCANNR_0_R0_MASK) >> TSC_MTSCANNR_0_R0_SHIFT;
+
+        val = readl(NV_ADDRESS_MAP_TSC_IMPL_BASE + TSC_MTSCANDR_0);
+        d0 = (val & TSC_MTSCANDR_0_D0_MASK) >> TSC_MTSCANDR_0_D0_SHIFT;
+
+        cntfid0 = (TSC_BASE_RATE / d0) * (d0 * r0 + m0);
+        cntperiod = 1000000000U / cntfid0;
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/tke/tke-tegra-udelay.c b/spe-freertos-bsp/fsp/source/drivers/tke/tke-tegra-udelay.c
new file mode 100644
index 0000000..4a7eb66
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/tke/tke-tegra-udelay.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2015-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                     // for uint64_t
+#include <stdbool.h>                    // for bool
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <osa/rtos-task.h>              // for rtosTaskIsSchedulerStarted
+#include <cpu/barriers.h>               // for barrier_compiler, FSP__ARM__COMMON_...
+#include <delay/delay.h>                // for FSP__DELAY__DELAY_H, get_time_delta_us
+#include <irq/safe-irqs.h>              // for in_critical, in_interrupt
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <tke/tke-tegra.h>              // for tegra_tke_get_elapsed_usecs64, tegr...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__BARRIERS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DELAY__DELAY_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__TKE__TKE_TEGRA_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
+void udelay(uint64_t delay_us)
+{
+        bool cant_yield;
+        uint64_t start = tegra_tke_get_tsc64();
+
+        cant_yield = in_interrupt();
+        if (!cant_yield) {
+                /* xTaskGetSchedulerState can't be called from an ISR */
+                cant_yield = (!rtosTaskIsSchedulerStarted()) || in_critical();
+        }
+
+        INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+        while ((tegra_tke_get_elapsed_usecs64(start)) <= delay_us) {
+                if (cant_yield) {
+                        barrier_compiler();
+                } else {
+                        rtosTaskYield();
+                }
+        }
+}
+
+uint64_t get_time_ticks(void)
+{
+        return tegra_tke_get_elapsed_usecs64(0ULL);
+}
+
+uint64_t get_time_delta_us(uint64_t ticks_start)
+{
+        return tegra_tke_get_elapsed_usecs64(ticks_start);
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/tke/tke-tegra.c b/spe-freertos-bsp/fsp/source/drivers/tke/tke-tegra.c
new file mode 100644
index 0000000..551ac77
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/tke/tke-tegra.c
@@ -0,0 +1,272 @@
+/*
+ * Copyright (c) 2015-2021 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                // for bool, true
+#include <stddef.h>                 // for NULL
+#include <stdint.h>                 // for uint32_t, uint64_t
+                                    // IWYU pragma: no_include <errno.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>         // for CT_ASSERT
+#include <soc-common/hw-const.h>    /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <artke_top.h>              // for TKE_TOP_SHARED_TKETSC0_0, TKE_TOP...
+
+/* Late FSP headers */
+#include <osa/rtos-task.h>          // for rtosSystemTickHandler
+#include <debug/assert.h>           // for ASSERT, FSP__DEBUG__ASSERT_H
+#include <error/common-errors.h>    // for E_SUCCESS
+#include <irq/safe-irqs.h>          // for irq_safe_disable, irq_safe_enable, irq_safe_set_...
+#include <misc/attributes.h>        // for FSP__MISC__ATTRIBUTES_H, UNUSED
+#include <misc/bitops.h>            // for hilo_to_64, FSP__MISC__BITOPS_H
+#include <misc/macros.h>            // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <reg-access/reg-access.h>  // for readl_base_offset, writel_base_of...
+
+/* Module-specific FSP headers */
+#include <tke/sections-tke.h>       // Immune from CT_ASSERT protection
+#include <tke/tke-tegra-priv.h>     // for tegra_tke_id, tegra_tke_conf, tke...
+#include <tke/tke-tegra-regs.h>     // for TKE_TIMER_TMRCR_0, TKE_TIMER_TMRSR_0
+#include <tke/tke-tegra.h>          // for FSP__TKE__TKE_TEGRA_H, tegra_tke_...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ASSERT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__TKE__TKE_TEGRA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__TKE__TKE_TEGRA_REGS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__TKE__TKE_TEGRA_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+static inline uint32_t
+tegra_tke_timer_readl(const struct tegra_tke_id *id, uint32_t reg)
+{
+        return readl_base_offset(id->conf.base_addr, reg);
+}
+
+static inline void
+tegra_tke_timer_writel(const struct tegra_tke_id *id, uint32_t val, uint32_t reg)
+{
+        writel_base_offset(val, id->conf.base_addr, reg);
+}
+
+SECTION_TKE_TEXT void
+tegra_tke_set_up_timer(struct tegra_tke_id *id, uint32_t clk_src_sel,
+                       bool periodic, uint32_t divisor,
+                       tegra_tke_timer_callback callback, void *data)
+{
+        uint32_t tmrcr;
+        error_t  err;
+
+        ASSERT(divisor != 0UL);
+        id->callback = callback;
+        id->data = data;
+
+        /* select timer clock source */
+        tegra_tke_timer_writel(id, clk_src_sel, TKE_TIMER_TMRCSSR_0);
+
+        /* Disable timer, set cycle counter */
+        tmrcr = (divisor - 1U) & TKE_TIMER_TMRCR_0_PTV;
+        tegra_tke_timer_writel(id, tmrcr, TKE_TIMER_TMRCR_0);
+
+        /* Clear timer interrupts. */
+        tegra_tke_timer_writel(id, TKE_TIMER_TMRSR_0_INTR_CLR, TKE_TIMER_TMRSR_0);
+
+        /* Enable timer and configure timer type. */
+        tmrcr |= TKE_TIMER_TMRCR_0_EN;
+        if (periodic) {
+                tmrcr |= TKE_TIMER_TMRCR_0_PER;
+        }
+        tegra_tke_timer_writel(id, tmrcr, TKE_TIMER_TMRCR_0);
+
+        if (id->conf.irq != TEGRA_TKE_NO_IRQ) {
+                err = irq_safe_set_handler(id->conf.irq, tegra_tke_irq, (void *)id);
+                ASSERT(err == E_SUCCESS);
+                err = irq_safe_enable(id->conf.irq);
+                ASSERT(err == E_SUCCESS);
+        }
+}
+
+SECTION_TKE_TEXT void
+tegra_tke_stop_timer(const struct tegra_tke_id *id)
+{
+        uint32_t tmrcr;
+        error_t  err;
+
+        if (id->conf.irq != TEGRA_TKE_NO_IRQ) {
+                err = irq_safe_disable(id->conf.irq);
+                ASSERT(err == E_SUCCESS);
+        }
+
+        tmrcr = tegra_tke_timer_readl(id, TKE_TIMER_TMRCR_0);
+        tmrcr &= ~TKE_TIMER_TMRCR_0_EN;
+        tegra_tke_timer_writel(id, tmrcr, TKE_TIMER_TMRCR_0);
+}
+
+SECTION_TKE_TEXT uint32_t
+tegra_tke_get_pcv(const struct tegra_tke_id *id)
+{
+        uint32_t val;
+
+        val = tegra_tke_timer_readl(id, TKE_TIMER_TMRSR_0);
+
+        return val & TKE_TIMER_TMRSR_0_PCV;
+}
+
+SECTION_TKE_TEXT void
+tegra_tke_enable_timer_irq(const struct tegra_tke_id *id)
+{
+        error_t  err;
+
+        if (id->conf.irq != TEGRA_TKE_NO_IRQ) {
+                err = irq_safe_enable(id->conf.irq);
+                ASSERT(err == E_SUCCESS);
+        }
+}
+
+SECTION_TKE_TEXT void
+tegra_tke_disable_timer_irq(const struct tegra_tke_id *id)
+{
+        error_t  err;
+
+        if (id->conf.irq != TEGRA_TKE_NO_IRQ) {
+                err = irq_safe_disable(id->conf.irq);
+                ASSERT(err == E_SUCCESS);
+        }
+}
+
+SECTION_TKE_TEXT void
+tegra_tke_clear_timer_irq(const struct tegra_tke_id *id)
+{
+        tegra_tke_timer_writel(id, TKE_TIMER_TMRSR_0_INTR_CLR,
+                TKE_TIMER_TMRSR_0);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_TKE_TEXT void tegra_tke_irq(void *tke_id)
+{
+	INLINE_RFD(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx");
+	const struct tegra_tke_id *id = (const void *)tke_id;
+
+        tegra_tke_clear_timer_irq(id);
+
+        if (id->callback != NULL) {
+                id->callback(id->data);
+        }
+}
+
+SECTION_TKE_TEXT void
+tegra_tke_get_tsc(uint32_t *tsc_hi, uint32_t *tsc_lo)
+{
+        uint64_t tsc = tegra_tke_get_tsc64();
+
+        INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-559, DR: SWE-FSP-048-SWSADR.docx");
+        *tsc_lo = LOW32(tsc);
+        INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-559, DR: SWE-FSP-048-SWSADR.docx");
+        *tsc_hi = HI32(tsc);
+}
+
+/* TSC timestamp from 31.25 MHz clock (32 ns cycle) */
+SECTION_TKE_TEXT uint32_t
+tegra_tke_get_tsc32(void)
+{
+        return readl_base_offset(tke_top_base, TKE_TOP_SHARED_TKETSC0_0);
+}
+
+SECTION_TKE_TEXT uint64_t
+tegra_tke_get_tsc64(void)
+{
+        uint32_t hi0, lo, hi;
+
+        /*
+         * Here is how the code to handle rollover of the upper word:
+         * Always read twice the MSW, pattern is read MSW, LSW, MSW.
+         * If the two MSW are OK then it's done, otherwise read LSW a
+         * second time, and keep the second set of both values
+         */
+        hi0 = readl_base_offset(tke_top_base, TKE_TOP_SHARED_TKETSC1_0);
+        lo = readl_base_offset(tke_top_base, TKE_TOP_SHARED_TKETSC0_0);
+        hi = readl_base_offset(tke_top_base, TKE_TOP_SHARED_TKETSC1_0);
+
+        if (hi0 != hi) {
+                lo = readl_base_offset(tke_top_base, TKE_TOP_SHARED_TKETSC0_0);
+        }
+
+        return hilo_to_64(hi, lo);
+}
+
+SECTION_TKE_TEXT uint32_t
+tegra_tke_get_usec(void)
+{
+        return readl_base_offset(tke_top_base, TKE_TOP_SHARED_TKEUSEC_0);
+}
+
+SECTION_TKE_TEXT uint32_t
+tegra_tke_get_osc(void)
+{
+        return readl_base_offset(tke_top_base, TKE_TOP_SHARED_TKEOSC_0);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_TKE_TEXT static void tegra_tke_os_tick(void * data)
+{
+        UNUSED((data));
+
+        rtosSystemTickHandler();
+}
+
+SECTION_TKE_INIT_TEXT void
+tegra_tke_set_up_tick(struct tegra_tke_id *id, uint32_t clk_src,
+                                uint32_t divisor)
+{
+        tegra_tke_set_up_timer(id, clk_src, true, divisor, tegra_tke_os_tick,
+                                NULL);
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/uart-sbsa/module-uart-sbsa-nosafety-config.mk b/spe-freertos-bsp/fsp/source/drivers/uart-sbsa/module-uart-sbsa-nosafety-config.mk
new file mode 100644
index 0000000..e47f171
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/uart-sbsa/module-uart-sbsa-nosafety-config.mk
@@ -0,0 +1,41 @@
+#
+# Copyright (c) 2020-2021 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-uart-sbsa-nosafety-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-osa*.mk' files.
+MODULE_UART_SBSA_NOSAFETY_CONFIG        := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_UART_SBSA_NOSAFETY_DEPENDS       := SOC CLUSTER CPL OSA FSP_COMMON
+$(foreach _,$(MODULE_UART_SBSA_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_UART_SBSA_NOSAFETY_SOURCE_DIR     = $(FSP_COMMON_REPO)/drivers/uart-sbsa
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_UART_SBSA_NOSAFETY_INCLUDES       =
diff --git a/spe-freertos-bsp/fsp/source/drivers/uart-sbsa/module-uart-sbsa-nosafety.mk b/spe-freertos-bsp/fsp/source/drivers/uart-sbsa/module-uart-sbsa-nosafety.mk
new file mode 100644
index 0000000..fb8f719
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/uart-sbsa/module-uart-sbsa-nosafety.mk
@@ -0,0 +1,66 @@
+#
+# Copyright (c) 2020-2022 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-uart-sbsa-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_UART_SBSA_NOSAFETY_NAME          := UART_SBSA_NOSAFETY
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_UART_SBSA_NOSAFETY_DEFINED       := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_UART_SBSA_NOSAFETY_DEPENDS       := UART_SBSA_NOSAFETY SOC CPL OSA
+$(foreach _,$(CONFIG_UART_SBSA_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_UART_SBSA_NOSAFETY_C_SRC          =
+MODULE_UART_SBSA_NOSAFETY_C_SRC         += $(MODULE_UART_SBSA_NOSAFETY_SOURCE_DIR)/uart-sbsa.c
+MODULE_UART_SBSA_NOSAFETY_C_SRC		+= $(MODULE_UART_SBSA_NOSAFETY_SOURCE_DIR)/uart-sbsa-ops.c
+MODULE_UART_SBSA_NOSAFETY_C_SRC         += $(CPL_SOC_IDS)/uart-tegra-ids.c
+MODULE_UART_SBSA_NOSAFETY_C_SRC         += $(CPL_SOC_PORT)/uart-port.c
+
+#
+# Assembly source
+MODULE_UART_SBSA_NOSAFETY_ASM_SRC        =
+#MODULE_UART_SBSA_NOSAFETY_ASM_SRC       = $(CPL_SOC_PORT)/uart-irq.S
+
+#
+# Special C Flags
+MODULE_UART_SBSA_NOSAFETY_C_FLAGS        =
+
+#
+# Special ASM Flags
+MODULE_UART_SBSA_NOSAFETY_ASM_FLAGS      =
diff --git a/spe-freertos-bsp/fsp/source/drivers/uart-sbsa/uart-sbsa-ops.c b/spe-freertos-bsp/fsp/source/drivers/uart-sbsa/uart-sbsa-ops.c
new file mode 100644
index 0000000..9360094
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/uart-sbsa/uart-sbsa-ops.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>        // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>   // for E_SUCCESS, error_t
+#include <misc/macros.h>           // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <uart-sbsa/uart-sbsa.h>   // for sbsa_uart_flush_tx_hw_fifo, sbsa...
+
+/* Module-specific FSP headers */
+#include <debug/debug-uart.h>      // for dbg_uart_ops...
+#include <debug/sections-debug.h>  // Immune from CT_ASSERT protection
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__UART__SBSA_UART_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+static const struct tegra_uart_conf debug_uart_conf SECTION_DEBUG_DATA =
+{
+    .parity         = TEGRA_UART_NO_PARITY,
+    .stop_bits      = TEGRA_UART_STOP_BITS_1,
+    .data_bits      = TEGRA_UART_DATA_BITS_8,
+    .baud           = 115200U,
+};
+
+static inline error_t
+dbg_uart_init(void *data)
+{
+    struct tegra_uart_ctlr *ctlr = (struct tegra_uart_ctlr *)data;
+
+    return sbsa_uart_init_hw(ctlr, &debug_uart_conf);
+}
+
+static inline void
+dbg_uart_putc(void *data,
+              const char ch)
+{
+    const struct tegra_uart_ctlr *ctlr = (const struct tegra_uart_ctlr *)data;
+
+    sbsa_uart_write_char(ctlr, ch);
+}
+
+static inline void
+dbg_uart_puts(void *data,
+              const char *s)
+{
+    const struct tegra_uart_ctlr *ctlr = (const struct tegra_uart_ctlr *)data;
+
+    sbsa_uart_write_string(ctlr, s);
+}
+
+static inline void
+dbg_uart_putd(void *data,
+              const char *d,
+              uint32_t len)
+{
+    const struct tegra_uart_ctlr *ctlr = (const struct tegra_uart_ctlr *)data;
+
+    sbsa_uart_write_now(ctlr, d, len);
+}
+
+static inline void
+dbg_uart_tx_flush(void *data)
+{
+    const struct tegra_uart_ctlr *ctlr = (const struct tegra_uart_ctlr *)data;
+
+    sbsa_uart_flush_tx_hw_fifo(ctlr);
+}
+
+static inline bool
+dbg_uart_is_tx_ready(void *data)
+{
+    const struct tegra_uart_ctlr *ctlr = (const struct tegra_uart_ctlr *)data;
+
+    return sbsa_uart_is_tx_ready(ctlr);
+}
+
+const struct dbg_uart_ops dbg_standalone_uart_ops = {
+    .init     = &dbg_uart_init,
+    .putc     = &dbg_uart_putc,
+    .puts     = &dbg_uart_puts,
+    .putd     = &dbg_uart_putd,
+    .flush    = &dbg_uart_tx_flush,
+    .tx_ready = &dbg_uart_is_tx_ready,
+};
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/uart-sbsa/uart-sbsa.c b/spe-freertos-bsp/fsp/source/drivers/uart-sbsa/uart-sbsa.c
new file mode 100644
index 0000000..0ba4426
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/uart-sbsa/uart-sbsa.c
@@ -0,0 +1,949 @@
+/*
+ * Copyright (c) 2021-2023 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/* Compiler headers */
+#include <stdbool.h>                         // for true
+#include <stdint.h>                          // for uint32_t
+#include <stddef.h>                          // for NULL
+
+/* HW headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                  // for CT_ASSERT
+#include <soc-common/hw-const.h>             /* Must appear before any hwinc files */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>             // for E_SUCCESS, error_t, FSP_...
+#include <misc/attributes.h>                 // for FSP__MISC__ATTRIBUTES_H
+#include <misc/bitops.h>                     // for BIT
+#include <reg-access/reg-access.h>           // for readl, writel, FSP__REG_...
+#include <irq/safe-irqs.h>                   // for irq_enable, irq_disable...
+#include <delay/delay.h>                     // for get_time_ticks
+
+/* Module-specific FSP headers */
+#include <uart/sections-uart.h>              // Immune from CT_ASSERT protection
+#include <uart/uart-errors.h>                // for E_UART_ERR_CONFIG, ...
+#include <uart/uart.h>                       // for tegra_uart_conf, ...
+#include <uart/tegra-uart-priv.h>            // for tegra_uart_ctlr, tegra_u...
+#include <uart/uart-port.h>                  // for uart_port_...
+#include <uart-sbsa/uart-sbsa.h>             // for sbsa_uart_...
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+
+#define SBSA_UARTDR_0                  0x00UL
+#define SBSA_UARTRSR_0                 0x04UL
+#define SBSA_UARTIBRD_0                0x24UL
+#define SBSA_UARTFR_0                  0x18UL
+#define SBSA_UARTLCR_H_0               0x2CUL
+#define SBSA_UARTCR_0                  0x30UL
+#define SBSA_UARTIFLS_0                0x34UL
+#define SBSA_UARTIMSC_0                0x38UL
+#define SBSA_UARTRIS_0                 0x3CUL
+#define SBSA_UARTMIS_0                 0x40UL
+#define SBSA_UARTICR_0                 0x44UL
+
+#define SBSA_UARTIFLS_0_TX_TRIG_1_8    0x0U
+#define SBSA_UARTIFLS_0_TX_TRIG_1_4    0x1U
+#define SBSA_UARTIFLS_0_TX_TRIG_1_2    0x2U
+#define SBSA_UARTIFLS_0_TX_TRIG_3_4    0x3U
+#define SBSA_UARTIFLS_0_TX_TRIG_7_8    0x4U
+#define SBSA_UARTIFLS_0_RX_TRIG_1_8    0x0U
+#define SBSA_UARTIFLS_0_RX_TRIG_1_4    0x1U
+#define SBSA_UARTIFLS_0_RX_TRIG_1_2    0x2U
+#define SBSA_UARTIFLS_0_RX_TRIG_3_4    0x3U
+#define SBSA_UARTIFLS_0_RX_TRIG_7_8    0x4U
+
+#define SBSA_UARTIFLS_0_TXIFLS_SHIFT   0x0U
+#define SBSA_UARTIFLS_0_RXIFLS_SHIFT   0x3U
+#define SBSA_UARTCR_0_TXE_SHIFT        0x8U
+#define SBSA_UARTCR_0_RXE_SHIFT        0x9U
+#define SBSA_UARTCR_0_UARTEN_SHIFT     0x0U
+#define SBSA_UARTLCR_H_0_PEN_SHIFT     0x1U
+#define SBSA_UARTLCR_H_0_EPS_SHIFT     0x2U
+#define SBSA_UARTLCR_H_0_FEN_SHIFT     0x4U
+#define SBSA_UARTLCR_H_0_STP2_SHIFT    0x3U
+#define SBSA_UARTLCR_H_0_WLEN_SHIFT    0x5U
+
+#define SBSA_UARTLCR_H_0_WLEN_WORD_LENGTH_5 0x0U
+#define SBSA_UARTLCR_H_0_WLEN_WORD_LENGTH_6 0x1U
+#define SBSA_UARTLCR_H_0_WLEN_WORD_LENGTH_7 0x2U
+#define SBSA_UARTLCR_H_0_WLEN_WORD_LENGTH_8 0x3U
+
+#define SBSA_UARTFR_0_TXFE                  BIT(7U)
+#define SBSA_UARTFR_0_RXFE                  BIT(4U)
+#define SBSA_UARTFR_0_BUSY                  BIT(3U)
+#define SBSA_UARTIMSC_0_TXIM                BIT(5U)
+#define SBSA_UARTIMSC_0_RXIM                BIT(4U)
+#define SBSA_UARTIMSC_0_RTIM                BIT(6U)
+#define SBSA_UARTRIS_RTRIS                  BIT(6U)
+#define SBSA_UARTRIS_RXRIS                  BIT(4U)
+#define SBSA_UARTRIS_TXRIS                  BIT(5U)
+#define SBSA_UART_ISR_NO_INT                0x0U
+#define SBSA_UART_IRQ_MASK                  0x7FFUL
+#define SBSA_UARTCR_0_TXE_TX_ENABLE         0x1U
+#define SBSA_UARTCR_0_RXE_RX_ENABLE         0x1U
+#define SBSA_UARTCR_0_UARTEN_UART_ENABLE    0x1U
+#define SBSA_UARTLCR_H_0_PEN_NO_PARITY      0x0U
+#define SBSA_UARTLCR_H_0_PEN_PARITY         0x1U
+#define SBSA_UARTLCR_H_0_EPS_ODD            0x0U
+#define SBSA_UARTLCR_H_0_EPS_EVEN           0x1U
+#define SBSA_UARTLCR_H_0_STP2_ONE           0x0U
+#define SBSA_UARTLCR_H_0_STP2_TWO           0x1U
+#define SBSA_UARTLCR_H_0_FEN_ENABLE         0x1U
+
+static inline uint32_t
+sbsa_uart_readl(const struct tegra_uart_ctlr * const ctlr,
+                 uint32_t offset)
+{
+    return readl_base_offset(ctlr->id.base_addr, offset);
+}
+
+static inline void
+sbsa_uart_writel(const struct tegra_uart_ctlr * const ctlr,
+                  uint32_t val,
+                  uint32_t offset)
+{
+        writel_base_offset(val, ctlr->id.base_addr, offset);
+}
+
+
+static inline void
+sbsa_uart_putc(const struct tegra_uart_ctlr * const ctlr,
+                char c)
+{
+    while (!sbsa_uart_is_tx_ready(ctlr)) {
+    }
+
+    sbsa_uart_writel(ctlr, c, SBSA_UARTDR_0);
+}
+
+static inline char
+sbsa_uart_getc(const struct tegra_uart_ctlr * const ctlr)
+{
+    while ((sbsa_uart_readl(ctlr, SBSA_UARTFR_0) & SBSA_UARTFR_0_RXFE) != 0U);
+
+    return sbsa_uart_readl(ctlr, SBSA_UARTDR_0);
+}
+
+SECTION_UART_TEXT bool
+sbsa_uart_is_tx_ready(const struct tegra_uart_ctlr * const ctlr)
+{
+    return (sbsa_uart_readl(ctlr, SBSA_UARTFR_0) & SBSA_UARTFR_0_BUSY) == 0UL;
+}
+
+SECTION_UART_TEXT error_t
+sbsa_uart_flush_tx_hw_fifo(const struct tegra_uart_ctlr * const ctlr)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (!ctlr->initialized) {
+        ret = E_UART_NO_INIT;
+        goto out;
+    }
+
+    while ((sbsa_uart_readl(ctlr, SBSA_UARTFR_0) &
+                   SBSA_UARTFR_0_TXFE) == 0UL);
+
+out:
+    return ret;
+}
+
+SECTION_UART_TEXT error_t
+sbsa_uart_write_now(const struct tegra_uart_ctlr * const ctlr,
+                    const char *buf,
+                    uint32_t count)
+{
+    error_t     ret = E_SUCCESS;
+    uint32_t    i;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (buf == NULL) {
+        ret = E_UART_INVALID_PARAM;
+        goto out;
+    }
+
+    if (!ctlr->initialized) {
+        ret = E_UART_NO_INIT;
+        goto out;
+    }
+
+    for (i = 0U; i < count; i += 1U) {
+        sbsa_uart_putc(ctlr, *buf++);
+    }
+
+out:
+    return ret;
+}
+
+SECTION_UART_TEXT error_t
+sbsa_uart_write_char(const struct tegra_uart_ctlr * const ctlr,
+                     const char c)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (!ctlr->initialized) {
+        ret = E_UART_NO_INIT;
+        goto out;
+    }
+
+    sbsa_uart_putc(ctlr, c);
+
+out:
+    return ret;
+}
+
+SECTION_UART_TEXT error_t
+sbsa_uart_write_string(const struct tegra_uart_ctlr * const ctlr,
+                       const char *buf)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (buf == NULL) {
+        ret = E_UART_INVALID_PARAM;
+        goto out;
+    }
+
+    if (!ctlr->initialized) {
+        ret = E_UART_NO_INIT;
+        goto out;
+    }
+
+    while (*buf != '\0') {
+        sbsa_uart_putc(ctlr, *buf++);
+    }
+
+out:
+    return ret;
+}
+
+static inline uint64_t
+sbsa_uart_get_elapsed_ticks(uint64_t tstart, uint64_t timeout)
+{
+    uint64_t tcurr = uart_port_get_elapsed_usecs(0ULL);
+    uint64_t elapsed = 0UL;
+
+    if ((tcurr - tstart) < timeout) {
+        elapsed = (timeout - (tcurr - tstart));
+    }
+
+    return elapsed;
+}
+
+static void
+sbsa_uart_disable_tx_interrupt(const struct tegra_uart_ctlr *ctlr)
+{
+    uint32_t irq_mask;
+
+    UNUSED(irq_safe_disable(ctlr->id.irq));
+    irq_mask = sbsa_uart_readl(ctlr, SBSA_UARTIMSC_0);
+    if ((irq_mask & SBSA_UARTIMSC_0_TXIM) != 0UL) {
+        sbsa_uart_writel(ctlr,
+                         irq_mask & ~SBSA_UARTIMSC_0_TXIM,
+                         SBSA_UARTIMSC_0);
+    }
+    UNUSED(irq_safe_enable(ctlr->id.irq));
+}
+
+static void
+sbsa_uart_enable_tx_interrupt(const struct tegra_uart_ctlr *ctlr)
+{
+    uint32_t irq_mask;
+
+    UNUSED(irq_safe_disable(ctlr->id.irq));
+    irq_mask = sbsa_uart_readl(ctlr, SBSA_UARTIMSC_0);
+    if ((irq_mask & SBSA_UARTIMSC_0_TXIM) == 0UL) {
+        sbsa_uart_writel(ctlr,
+                         irq_mask | SBSA_UARTIMSC_0_TXIM,
+                         SBSA_UARTIMSC_0);
+    }
+    UNUSED(irq_safe_enable(ctlr->id.irq));
+}
+
+static void
+sbsa_uart_enable_rx_interrupt(const struct tegra_uart_ctlr *ctlr)
+{
+    uint32_t irq_mask;
+
+    /*
+     * RX interrupt is enabled once in init. No need to place it in
+     * the critical section.
+     */
+    irq_mask = sbsa_uart_readl(ctlr, SBSA_UARTIMSC_0);
+
+    /* Enable the rx timeout and rx interrupt */
+    sbsa_uart_writel(ctlr,
+                     irq_mask | SBSA_UARTIMSC_0_RXIM | SBSA_UARTIMSC_0_RTIM,
+                     SBSA_UARTIMSC_0);
+}
+
+SECTION_UART_TEXT error_t
+sbsa_uart_write(const struct tegra_uart_ctlr * const ctlr,
+                const char *buf,
+                uint32_t count,
+                uint32_t *written,
+                uint64_t timeout)
+{
+    uint64_t    tstart;
+    uint64_t    timeout_left = 0;
+    uint32_t    write_cnt = 0UL;
+    error_t     ret = E_SUCCESS;
+    uint32_t    fr;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (buf == NULL || written == NULL) {
+        ret = E_UART_INVALID_PARAM;
+        goto out;
+    }
+
+    if (!ctlr->initialized) {
+        ret = E_UART_NO_INIT;
+        goto out;
+    }
+
+    if (count == 0UL) {
+        goto out;
+    }
+
+    tstart = uart_port_get_elapsed_usecs(0ULL);
+
+    if (ctlr->id.irq == UINT32_MAX) {
+        for (write_cnt = 0UL; write_cnt < count; write_cnt++) {
+            do {
+                fr = sbsa_uart_readl(ctlr, SBSA_UARTFR_0);
+                if ((fr & SBSA_UARTFR_0_BUSY) == 0UL) {
+                    sbsa_uart_writel(ctlr, *buf, SBSA_UARTDR_0);
+                    buf++;
+                }
+                timeout_left = sbsa_uart_get_elapsed_ticks(tstart, timeout);
+            } while (timeout_left != 0);
+        }
+        goto out;
+    }
+
+    for (write_cnt = 0UL; write_cnt < count; write_cnt++) {
+        ret = uart_port_tx_queue_send(ctlr, buf, 0);
+        if (ret == E_UART_QUEUE_FULL) {
+            sbsa_uart_enable_tx_interrupt(ctlr);
+            timeout_left = sbsa_uart_get_elapsed_ticks(tstart, timeout);
+            ret = uart_port_tx_queue_send(ctlr, buf, timeout_left);
+            if (ret != E_SUCCESS) {
+                break;
+            }
+        }
+        buf++;
+    }
+
+    if (write_cnt != 0UL) {
+        sbsa_uart_enable_tx_interrupt(ctlr);
+    }
+
+out:
+    if (written != NULL) {
+        *written = write_cnt;
+    }
+    return ret;
+}
+
+SECTION_UART_TEXT error_t
+sbsa_uart_flush_tx_fifo(const struct tegra_uart_ctlr * const ctlr)
+{
+    error_t   ret = E_SUCCESS;
+    char      c;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    sbsa_uart_disable_tx_interrupt(ctlr);
+    while (1) {
+        ret = uart_port_tx_queue_receive(ctlr, &c, 0);
+        if (ret != E_SUCCESS) {
+            ret = E_UART_FLUSH_TX_FIFO_FAIL;
+            break;
+        }
+        sbsa_uart_putc(ctlr, c);
+    }
+
+out:
+    return ret;
+}
+
+SECTION_UART_TEXT error_t
+sbsa_uart_read_char(const struct tegra_uart_ctlr * const ctlr,
+                    char *c)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (c == NULL) {
+        ret = E_UART_INVALID_PARAM;
+        goto out;
+    }
+
+    if (!ctlr->initialized) {
+        ret = E_UART_NO_INIT;
+        goto out;
+    }
+
+    *c = sbsa_uart_getc(ctlr);
+
+out:
+    return ret;
+}
+
+SECTION_UART_TEXT error_t
+sbsa_uart_read(const struct tegra_uart_ctlr * const ctlr,
+               char *buf,
+               uint32_t count,
+               uint32_t *read,
+               uint64_t timeout)
+{
+    error_t     ret = E_SUCCESS;
+    uint64_t    tstart;
+    uint64_t    timeout_left = 0;
+    uint32_t    read_cnt = 0UL;
+    uint32_t    fr;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (buf == NULL) {
+        ret = E_UART_INVALID_PARAM;
+        goto out;
+    }
+
+    if (!ctlr->initialized) {
+        ret = E_UART_NO_INIT;
+        goto out;
+    }
+
+    if (count == 0UL) {
+        goto out;
+    }
+
+    tstart = uart_port_get_elapsed_usecs(0ULL);
+
+    if (ctlr->id.irq == UINT32_MAX) {
+        for (read_cnt = 0; read_cnt < count; read_cnt += 1UL) {
+            do {
+                fr = sbsa_uart_readl(ctlr, SBSA_UARTFR_0);
+                if ((fr & SBSA_UARTFR_0_RXFE) == 0U) {
+                    *buf = sbsa_uart_readl(ctlr, SBSA_UARTDR_0);
+                    buf++;
+                }
+                timeout_left = sbsa_uart_get_elapsed_ticks(tstart, timeout);
+            } while (timeout_left != 0);
+        }
+        goto out;
+    }
+
+    timeout_left = timeout;
+    for (read_cnt = 0UL; read_cnt < count; read_cnt += 1UL) {
+        ret = uart_port_rx_queue_receive(ctlr,
+                                         buf,
+                                         timeout_left);
+        if (ret != E_SUCCESS) {
+            break;
+        }
+        buf++;
+        timeout_left = sbsa_uart_get_elapsed_ticks(tstart, timeout);
+    }
+
+out:
+    *read = read_cnt;
+    return ret;
+}
+
+SECTION_UART_TEXT static void
+sbsa_uart_irq_handler(void *data)
+{
+    const struct tegra_uart_ctlr *ctlr = (const struct tegra_uart_ctlr *)data;
+    uint32_t  isr;
+    uint32_t  lsr;
+    uint32_t  irq_mask;
+    char      c_in, c_out;
+    error_t   status;
+    bool      isr_yield_flag = false;
+
+    isr = sbsa_uart_readl(ctlr, SBSA_UARTRIS_0) & SBSA_UART_IRQ_MASK;
+    if (isr == SBSA_UART_ISR_NO_INT) {
+        goto out;
+    }
+
+    /* RX timeout or RX data available */
+    if (((isr & SBSA_UARTRIS_RTRIS) != 0UL) ||
+                ((isr & SBSA_UARTRIS_RXRIS) != 0UL)) {
+        do {
+            c_in = sbsa_uart_readl(ctlr, SBSA_UARTDR_0) & 0xFFU;
+            status = uart_port_rx_queue_send_from_isr(ctlr,
+                                                      &c_in,
+                                                      &isr_yield_flag);
+            if (status != E_SUCCESS) {
+                break;
+            }
+            lsr = sbsa_uart_readl(ctlr, SBSA_UARTFR_0);
+        } while ((lsr & SBSA_UARTFR_0_RXFE) == 0UL);
+    }
+
+    /* TX holding register empty */
+    if ((isr & SBSA_UARTRIS_TXRIS) != 0UL) {
+        do {
+            status = uart_port_tx_queue_receive_from_isr(ctlr,
+                                                         &c_out,
+                                                         &isr_yield_flag);
+            if (status != E_SUCCESS) {
+                /* if no data in queue, disable the TX interrupts */
+                  irq_mask = sbsa_uart_readl(ctlr, SBSA_UARTIMSC_0);
+                  sbsa_uart_writel(ctlr,
+                                   irq_mask & ~SBSA_UARTIMSC_0_TXIM,
+                                   SBSA_UARTIMSC_0);
+                  break;
+            }
+            sbsa_uart_writel(ctlr, c_out, SBSA_UARTDR_0);
+            lsr = sbsa_uart_readl(ctlr, SBSA_UARTFR_0);
+        } while ((lsr & SBSA_UARTFR_0_TXFE) != 0UL);
+    }
+
+out:
+    uart_port_isr_exit(ctlr, isr_yield_flag);
+}
+
+static inline void
+sbsa_uart_configure_tx_fifo_level(const struct tegra_uart_ctlr * const ctlr)
+{
+    uint32_t fifo_lvl;
+
+    fifo_lvl = (SBSA_UARTIFLS_0_TX_TRIG_1_8 << SBSA_UARTIFLS_0_TXIFLS_SHIFT);
+
+    sbsa_uart_writel(ctlr, fifo_lvl, SBSA_UARTIFLS_0);
+}
+
+static inline void
+sbsa_uart_configure_fifo_level(const struct tegra_uart_ctlr * const ctlr)
+{
+    uint32_t fifo_lvl;
+
+    fifo_lvl = (SBSA_UARTIFLS_0_TX_TRIG_1_8 << SBSA_UARTIFLS_0_TXIFLS_SHIFT) |
+               (SBSA_UARTIFLS_0_RX_TRIG_1_8 << SBSA_UARTIFLS_0_RXIFLS_SHIFT);
+
+    sbsa_uart_writel(ctlr, fifo_lvl, SBSA_UARTIFLS_0);
+}
+
+static inline void
+sbsa_uart_configure_tx_ctrl(const struct tegra_uart_ctlr * const ctlr)
+{
+    uint32_t cr;
+
+    cr = (SBSA_UARTCR_0_TXE_TX_ENABLE << SBSA_UARTCR_0_TXE_SHIFT);
+
+    sbsa_uart_writel(ctlr, cr, SBSA_UARTCR_0);
+}
+
+static inline void
+sbsa_uart_configure_ctrl(const struct tegra_uart_ctlr * const ctlr)
+{
+    uint32_t cr;
+
+    cr = (SBSA_UARTCR_0_TXE_TX_ENABLE << SBSA_UARTCR_0_TXE_SHIFT) |
+         (SBSA_UARTCR_0_RXE_RX_ENABLE << SBSA_UARTCR_0_RXE_SHIFT);
+
+    sbsa_uart_writel(ctlr, cr, SBSA_UARTCR_0);
+}
+
+static inline void
+sbsa_uart_enable(const struct tegra_uart_ctlr * const ctlr)
+{
+    uint32_t cr;
+
+    cr = sbsa_uart_readl(ctlr, SBSA_UARTCR_0);
+    cr |= (SBSA_UARTCR_0_UARTEN_UART_ENABLE << SBSA_UARTCR_0_UARTEN_SHIFT);
+
+    sbsa_uart_writel(ctlr, cr, SBSA_UARTCR_0);
+}
+
+static inline error_t
+sbsa_uart_get_parity_mode(const struct tegra_uart_ctlr * const ctlr,
+                          uint32_t parity_conf,
+                          uint32_t *parity)
+{
+    error_t ret = E_SUCCESS;
+
+    switch (parity_conf) {
+    case SBSA_UART_NO_PARITY:
+        *parity = (SBSA_UARTLCR_H_0_PEN_NO_PARITY << SBSA_UARTLCR_H_0_PEN_SHIFT);
+        break;
+    case SBSA_UART_ODD_PARITY:
+        *parity = (SBSA_UARTLCR_H_0_EPS_ODD << SBSA_UARTLCR_H_0_EPS_SHIFT) |
+                  (SBSA_UARTLCR_H_0_PEN_PARITY << SBSA_UARTLCR_H_0_PEN_SHIFT);
+        break;
+    case SBSA_UART_EVEN_PARITY:
+        *parity = (SBSA_UARTLCR_H_0_EPS_EVEN << SBSA_UARTLCR_H_0_EPS_SHIFT) |
+                  (SBSA_UARTLCR_H_0_PEN_PARITY << SBSA_UARTLCR_H_0_PEN_SHIFT);
+        break;
+    default:
+        ret = E_UART_ERR_CONFIG;
+        break;
+    }
+
+    return ret;
+}
+
+static inline error_t
+sbsa_uart_get_data_frame_len(const struct tegra_uart_ctlr * const ctlr,
+                             uint32_t data_conf,
+                             uint32_t *data_bits)
+{
+    error_t ret = E_SUCCESS;
+
+    switch (data_conf) {
+    case SBSA_UART_DATA_BITS_5:
+        *data_bits = (SBSA_UARTLCR_H_0_WLEN_WORD_LENGTH_5 <<
+                      SBSA_UARTLCR_H_0_WLEN_SHIFT);
+        break;
+    case SBSA_UART_DATA_BITS_6:
+        *data_bits = (SBSA_UARTLCR_H_0_WLEN_WORD_LENGTH_6 <<
+                      SBSA_UARTLCR_H_0_WLEN_SHIFT);
+        break;
+    case SBSA_UART_DATA_BITS_7:
+        *data_bits = (SBSA_UARTLCR_H_0_WLEN_WORD_LENGTH_7 <<
+                      SBSA_UARTLCR_H_0_WLEN_SHIFT);
+        break;
+    case SBSA_UART_DATA_BITS_8:
+        *data_bits = (SBSA_UARTLCR_H_0_WLEN_WORD_LENGTH_8 <<
+                      SBSA_UARTLCR_H_0_WLEN_SHIFT);
+        break;
+    default:
+        ret = E_UART_ERR_CONFIG;
+        break;
+    }
+
+    return ret;
+}
+
+static inline error_t
+sbsa_uart_get_stop_bits_len(const struct tegra_uart_ctlr * const ctlr,
+                            uint32_t stop_conf,
+                            uint32_t *stop_bits)
+{
+    error_t ret = E_SUCCESS;
+
+    switch (stop_conf) {
+    case SBSA_UART_STOP_BITS_1:
+        *stop_bits = (SBSA_UARTLCR_H_0_STP2_ONE << SBSA_UARTLCR_H_0_STP2_SHIFT);
+        break;
+    case SBSA_UART_STOP_BITS_2:
+        *stop_bits = (SBSA_UARTLCR_H_0_STP2_TWO << SBSA_UARTLCR_H_0_STP2_SHIFT);
+        break;
+    default:
+        ret = E_UART_ERR_CONFIG;
+        break;
+    }
+
+    return ret;
+}
+
+static inline void
+sbsa_uart_configure_line_ctrl(const struct tegra_uart_ctlr * const ctlr,
+                              uint32_t parity,
+                              uint32_t data_bits,
+                              uint32_t stop_bits)
+{
+    uint32_t lcr;
+
+    /*
+     * configure the data line attributes - data bits, stop bits and parity
+     * also enable the FIFO.
+     */
+    lcr = parity | data_bits | stop_bits |
+            (SBSA_UARTLCR_H_0_FEN_ENABLE << SBSA_UARTLCR_H_0_FEN_SHIFT);
+
+    sbsa_uart_writel(ctlr, lcr, SBSA_UARTLCR_H_0);
+}
+
+static error_t
+sbsa_uart_config(struct tegra_uart_ctlr * const ctlr,
+                 const struct tegra_uart_conf * const conf)
+{
+    error_t   ret = E_SUCCESS;
+    uint32_t  parity;
+    uint32_t  data_bits = 0UL;
+    uint32_t  stop_bits = 0UL;
+
+    /* reset the UART controller */
+    uart_port_clk_reset_pulse(ctlr, 10);
+
+    /* configure the clock rate based on the baud rate */
+    uart_port_clk_set_rate(ctlr, conf->baud * 16);
+
+    /* enable the clock for the UART controller */
+    uart_port_clk_enable(ctlr);
+
+    /* port specific init such as pinmux settings to select the UART */
+    uart_port_init(ctlr);
+
+    /* generate the parity mode based on input configuration */
+    ret = sbsa_uart_get_parity_mode(ctlr, conf->parity, &parity);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    /* fetch the data frame length in bits */
+    ret = sbsa_uart_get_data_frame_len(ctlr, conf->data_bits, &data_bits);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    /* fetch the stop bits length */
+    ret = sbsa_uart_get_stop_bits_len(ctlr, conf->stop_bits, &stop_bits);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    /* reset the data line attributes by clearing line control register */
+    sbsa_uart_writel(ctlr, 0x0, SBSA_UARTLCR_H_0);
+
+    /* clear all the interrupts */
+    sbsa_uart_writel(ctlr, 0x0, SBSA_UARTICR_0);
+
+    /* configure the line control register */
+    sbsa_uart_configure_line_ctrl(ctlr, parity, data_bits, stop_bits);
+
+out:
+    return ret;
+}
+
+SECTION_UART_INIT_TEXT error_t
+sbsa_uart_init_hw(struct tegra_uart_ctlr * const ctlr,
+                   const struct tegra_uart_conf * const conf)
+{
+    error_t   ret = E_SUCCESS;
+
+    /* sanity check the controller pointer */
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    /* sanity check for invalid conf parameter */
+    if (conf == NULL) {
+        ret = E_UART_INVALID_PARAM;
+        goto out;
+    }
+
+    /* configure the UART */
+    sbsa_uart_config(ctlr, conf);
+
+    /* configure the uart control register */
+    sbsa_uart_configure_ctrl(ctlr);
+
+    /* configure the uart fifo level */
+    sbsa_uart_configure_fifo_level(ctlr);
+
+    /* enable the uart */
+    sbsa_uart_enable(ctlr);
+
+    /* enable the rx interrupt */
+    sbsa_uart_enable_rx_interrupt(ctlr);
+
+    if (ctlr->id.irq != UINT32_MAX) {
+        /* register irq handler and enable irq */
+        ret = irq_safe_set_handler(ctlr->id.irq, sbsa_uart_irq_handler, ctlr);
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+        ret = irq_safe_enable(ctlr->id.irq);
+    }
+
+    /* indicate the controller is initialized */
+    if (ret == E_SUCCESS) {
+        ctlr->initialized = true;
+    }
+
+out:
+    if (ret != E_SUCCESS) {
+        uart_port_clk_disable(ctlr);
+    }
+
+    return ret;
+}
+
+SECTION_UART_INIT_TEXT error_t
+sbsa_uart_3rdparty_init(struct tegra_uart_ctlr *ctlr,
+                        const struct tegra_uart_conf * const conf)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (conf == NULL) {
+        ret = E_UART_INVALID_PARAM;
+        goto out;
+    }
+
+    /*
+     * Do the minimum required for configuring the UART if not already done.
+     */
+    if (!uart_port_is_configured(ctlr)) {
+        ret = sbsa_uart_config(ctlr, conf);
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+
+        /* configure the uart control register */
+        sbsa_uart_configure_tx_ctrl(ctlr);
+
+        /* configure the uart fifo level */
+        sbsa_uart_configure_tx_fifo_level(ctlr);
+
+        /* enable the uart */
+        sbsa_uart_enable(ctlr);
+    }
+
+    /* indicate the controller is initialized */
+    ctlr->initialized = true;
+
+out:
+    return ret;
+}
+
+SECTION_UART_INIT_TEXT error_t
+sbsa_uart_init(struct tegra_uart_ctlr *ctlr,
+               const struct tegra_uart_conf * const conf)
+{
+    error_t     ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (conf == NULL) {
+        ret = E_UART_INVALID_PARAM;
+        goto out;
+    }
+
+    /* check if UART is already configured by a 3rd party and skip the init */
+    if (uart_port_is_configured(ctlr)) {
+        ctlr->initialized = true;
+        goto out;
+    }
+
+    /* check if irq is supported */
+    if (ctlr->id.irq == UINT32_MAX) {
+        goto skip_queues;
+    }
+
+    /* create the TX sw buffer for interrupt driven TX */
+    ret = uart_port_tx_queue_create(ctlr);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    /* create the RX sw buffer for interrupt driven RX */
+    ret = uart_port_rx_queue_create(ctlr);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+skip_queues:
+    ret = sbsa_uart_init_hw(ctlr, conf);
+
+out:
+    return ret;
+}
+
+error_t sbsa_uart_deinit(struct tegra_uart_ctlr *ctlr)
+{
+    error_t     ret = E_SUCCESS;
+
+    ctlr->initialized = false;
+
+    ret = uart_port_tx_queue_delete(ctlr);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    ret = uart_port_rx_queue_delete(ctlr);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    ret = uart_port_clk_disable(ctlr);
+
+out:
+    return ret;
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/uart/module-uart-nosafety-config.mk b/spe-freertos-bsp/fsp/source/drivers/uart/module-uart-nosafety-config.mk
new file mode 100644
index 0000000..6d28687
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/uart/module-uart-nosafety-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-uart-nosafety-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_UART_NOSAFETY_CONFIG             := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_UART_NOSAFETY_DEPENDS            :=
+$(foreach _,$(MODULE_UART_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_UART_NOSAFETY_DRIVERS_DIR         = $(FSP_COMMON_REPO)/drivers/uart
+MODULE_UART_NOSAFETY_SOURCE_DIR          = $(MODULE_UART_NOSAFETY_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_UART_NOSAFETY_INCLUDES            =
diff --git a/spe-freertos-bsp/fsp/source/drivers/uart/module-uart-nosafety.mk b/spe-freertos-bsp/fsp/source/drivers/uart/module-uart-nosafety.mk
new file mode 100644
index 0000000..009f794
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/uart/module-uart-nosafety.mk
@@ -0,0 +1,64 @@
+#
+# Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-uart-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_UART_NOSAFETY_NAME               := UART_NOSAFETY
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_UART_NOSAFETY_DEFINED            := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_UART_NOSAFETY_DEPENDS            := UART_NOSAFETY SOC
+$(foreach _,$(CONFIG_UART_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_UART_NOSAFETY_C_SRC               =
+MODULE_UART_NOSAFETY_C_SRC              += $(MODULE_UART_NOSAFETY_DRIVERS_DIR)/tegra-uart.c
+MODULE_UART_NOSAFETY_C_SRC		+= $(MODULE_UART_NOSAFETY_DRIVERS_DIR)/tegra-uart-ops.c
+MODULE_UART_NOSAFETY_C_SRC              += $(FSP_COMMON_REPO)/soc/$(SOC)/ids/soc-common/uart-tegra-ids.c
+
+#
+# Assembly source
+MODULE_UART_NOSAFETY_ASM_SRC             =
+
+#
+# Special C Flags
+MODULE_UART_NOSAFETY_C_FLAGS             =
+
+#
+# Special ASM Flags
+MODULE_UART_NOSAFETY_ASM_FLAGS           =
diff --git a/spe-freertos-bsp/fsp/source/drivers/uart/tegra-uart-ops.c b/spe-freertos-bsp/fsp/source/drivers/uart/tegra-uart-ops.c
new file mode 100644
index 0000000..43952d5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/uart/tegra-uart-ops.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>        // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>   // for E_SUCCESS, error_t
+#include <misc/macros.h>           // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <uart/tegra-uart.h>       // for tegra_uart_flush_tx_hw_fifo, tegra...
+
+/* Module-specific FSP headers */
+#include <debug/debug-uart.h>      // for dbg_uart_ops...
+#include <debug/sections-debug.h>  // Immune from CT_ASSERT protection
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__UART__TEGRA_UART_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+static const struct tegra_uart_conf debug_uart_conf SECTION_DEBUG_DATA =
+{
+    .parity         = TEGRA_UART_NO_PARITY,
+    .stop_bits      = TEGRA_UART_STOP_BITS_1,
+    .data_bits      = TEGRA_UART_DATA_BITS_8,
+    .baud           = 115200U,
+};
+
+static inline error_t
+dbg_uart_init(void *data)
+{
+    struct tegra_uart_ctlr *ctlr = (struct tegra_uart_ctlr *)data;
+
+    return tegra_uart_init_hw(ctlr, &debug_uart_conf);
+}
+
+static inline void
+dbg_uart_putc(void *data,
+              const char ch)
+{
+    const struct tegra_uart_ctlr *ctlr = (const struct tegra_uart_ctlr *)data;
+
+    tegra_uart_write_char(ctlr, ch);
+}
+
+static inline void
+dbg_uart_puts(void *data,
+              const char *s)
+{
+    const struct tegra_uart_ctlr *ctlr = (const struct tegra_uart_ctlr *)data;
+
+    tegra_uart_write_string(ctlr, s);
+}
+
+static inline void
+dbg_uart_putd(void *data,
+              const char *d,
+              uint32_t len)
+{
+    const struct tegra_uart_ctlr *ctlr = (const struct tegra_uart_ctlr *)data;
+
+    tegra_uart_write(ctlr, d, len);
+}
+
+static inline void
+dbg_uart_tx_flush(void *data)
+{
+    const struct tegra_uart_ctlr *ctlr = (const struct tegra_uart_ctlr *)data;
+
+    tegra_uart_flush_tx_hw_fifo(ctlr);
+}
+
+static inline bool
+dbg_uart_is_tx_ready(void *data)
+{
+    const struct tegra_uart_ctlr *ctlr = (const struct tegra_uart_ctlr *)data;
+
+    return tegra_uart_is_tx_ready(ctlr);
+}
+
+const struct dbg_uart_ops dbg_standalone_uart_ops = {
+    .init     = &dbg_uart_init,
+    .putc     = &dbg_uart_putc,
+    .puts     = &dbg_uart_puts,
+    .putd     = &dbg_uart_putd,
+    .flush    = &dbg_uart_tx_flush,
+    .tx_ready = &dbg_uart_is_tx_ready,
+};
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/uart/tegra-uart.c b/spe-freertos-bsp/fsp/source/drivers/uart/tegra-uart.c
new file mode 100644
index 0000000..805254a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/uart/tegra-uart.c
@@ -0,0 +1,280 @@
+/*
+* Copyright (c) 2014-2022, NVIDIA CORPORATION.  All rights reserved.
+*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/* Compiler headers */
+#include <stdbool.h>                         // for true
+#include <stdint.h>                          // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                  // for CT_ASSERT
+#include <soc-common/hw-const.h>             /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <aruart.h>                          // for UART_LCR_0_WD_SIZE_SHIFT
+
+/* Late FSP headers */
+#include <clk/clk-tegra.h>                   // for tegra_clk_disable, tegra...
+#include <error/common-errors.h>             // for E_SUCCESS, error_t, FSP_...
+#include <misc/attributes.h>                 // for FSP__MISC__ATTRIBUTES_H
+#include <misc/macros.h>                     // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <processor/tegra-uart-hw-params.h>  // for UART_CLOCKS, UART_CAR_AC...
+#include <reg-access/reg-access.h>           // for readl, writel, FSP__REG_...
+
+/* Module-specific FSP headers */
+#include <uart/sections-uart.h>              // Immune from CT_ASSERT protection
+#include <uart/tegra-uart-priv.h>            // for tegra_uart_ctlr, tegra_u...
+#include <uart/tegra-uart.h>                 // for tegra_uart_conf, FSP__UA...
+#include <uart/uart-errors.h>                // for E_UART_ERR_CONFIG, FSP__...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CLK__CLK_TEGRA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__TEGRA_UART_HW_PARAMS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__UART__TEGRA_UART_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__UART__TEGRA_UART_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__UART__UART_ERRORS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+#define TEGRA_UART_LCR_DLAB             (UART_LCR_0_DLAB_ENABLE << UART_LCR_0_DLAB_SHIFT)
+#define TEGRA_UART_IER_THRE             (UART_IER_DLAB_0_0_IE_THR_ENABLE << UART_IER_DLAB_0_0_IE_THR_SHIFT)
+#define TEGRA_UART_LSR_RDY              (UART_LSR_0_RDR_DATA_IN_FIFO << UART_LSR_0_RDR_SHIFT)
+#define TEGRA_UART_LSR_TX_FIFO_FULL     (UART_LSR_0_TX_FIFO_FULL_FULL << UART_LSR_0_TX_FIFO_FULL_SHIFT)
+#define TEGRA_UART_LSR_THRE_EMPTY       (UART_LSR_0_THRE_EMPTY << UART_LSR_0_THRE_SHIFT)
+#define TEGRA_UART_LSR_TX_SHIFT_EMPTY   (UART_LSR_0_TMTY_EMPTY << UART_LSR_0_TMTY_SHIFT)
+#define TEGRA_UART_IIR_NO_INT           (UART_IIR_FCR_0_IS_STA_NO_INTR_PEND << UART_IIR_FCR_0_IS_STA_SHIFT)
+
+
+static inline uint32_t
+tegra_uart_readl(const struct tegra_uart_ctlr * const ctlr,
+                 uint32_t offset)
+{
+    offset += ctlr->id.base_addr;
+
+    return readl(offset);
+}
+
+static inline void
+tegra_uart_writel(const struct tegra_uart_ctlr * const ctlr,
+                  uint32_t val,
+                  uint32_t offset)
+{
+        offset += ctlr->id.base_addr;
+        writel(val, offset);
+}
+
+SECTION_UART_INIT_TEXT error_t
+tegra_uart_init_hw(struct tegra_uart_ctlr * const ctlr,
+                   const struct tegra_uart_conf * const conf)
+{
+    error_t     rc              = E_SUCCESS;
+    uint32_t    fcr;
+    uint32_t    divisor;
+    uint32_t    comm_param;
+
+#ifdef UART_CAR_ACCESS
+    tegra_clk_enable(ctlr->id.hw_handle->clk);
+    tegra_clk_reset_pulse(ctlr->id.hw_handle->rst, 10);
+#endif
+
+    /* Program the FCR register */
+    fcr = (UART_IIR_FCR_0_FCR_EN_FIFO_ENABLE << UART_IIR_FCR_0_FCR_EN_FIFO_SHIFT);
+    fcr |= (UART_IIR_FCR_0_TX_TRIG_FIFO_COUNT_GREATER_8 <<
+            UART_IIR_FCR_0_TX_TRIG_SHIFT);
+    fcr |= (UART_IIR_FCR_0_RX_TRIG_FIFO_COUNT_GREATER_4 <<
+            UART_IIR_FCR_0_RX_TRIG_SHIFT);
+    tegra_uart_writel(ctlr, fcr, UART_IIR_FCR_0);
+
+#ifdef UART_CLOCKS
+        tegra_clk_set_rate((ctlr->id.hw_handle->clk), conf->baud * 16);
+#endif
+
+    divisor = 1;
+
+    switch (conf->parity) {
+    case TEGRA_UART_NO_PARITY:
+        comm_param = (UART_LCR_0_PAR_NO_PARITY << UART_LCR_0_PAR_SHIFT);
+        break;
+    case TEGRA_UART_ODD_PARITY:
+        comm_param = (UART_LCR_0_EVEN_DISABLE << UART_LCR_0_EVEN_SHIFT) |
+                     (UART_LCR_0_PAR_PARITY << UART_LCR_0_PAR_SHIFT);
+        break;
+    case TEGRA_UART_EVEN_PARITY:
+        comm_param = (UART_LCR_0_EVEN_ENABLE << UART_LCR_0_EVEN_SHIFT) |
+                     (UART_LCR_0_PAR_PARITY << UART_LCR_0_PAR_SHIFT);
+        break;
+    default:
+        rc = E_UART_ERR_CONFIG;
+        goto conf_err;
+    }
+
+    switch (conf->data_bits) {
+    case TEGRA_UART_DATA_BITS_5:
+        comm_param |= (UART_LCR_0_WD_SIZE_WORD_LENGTH_5 <<
+                       UART_LCR_0_WD_SIZE_SHIFT);
+        break;
+    case TEGRA_UART_DATA_BITS_6:
+        comm_param |= (UART_LCR_0_WD_SIZE_WORD_LENGTH_6 <<
+                       UART_LCR_0_WD_SIZE_SHIFT);
+        break;
+    case TEGRA_UART_DATA_BITS_7:
+        comm_param |= (UART_LCR_0_WD_SIZE_WORD_LENGTH_7 <<
+                       UART_LCR_0_WD_SIZE_SHIFT);
+        break;
+    case TEGRA_UART_DATA_BITS_8:
+        comm_param |= (UART_LCR_0_WD_SIZE_WORD_LENGTH_8 <<
+                       UART_LCR_0_WD_SIZE_SHIFT);
+        break;
+    default:
+        rc = E_UART_ERR_CONFIG;
+        goto conf_err;
+    }
+
+    if (conf->stop_bits == TEGRA_UART_STOP_BITS_2)
+        comm_param |= (UART_LCR_0_STOP_ENABLE << UART_LCR_0_STOP_SHIFT);
+
+    tegra_uart_writel(ctlr, 0x0, UART_LCR_0);
+    tegra_uart_writel(ctlr, 0x0, UART_IER_DLAB_0_0);
+
+    tegra_uart_writel(ctlr, comm_param | TEGRA_UART_LCR_DLAB, UART_LCR_0);
+    tegra_uart_writel(ctlr, divisor & 0xFF, UART_THR_DLAB_0_0);
+    tegra_uart_writel(ctlr, ((divisor >> 8) & 0xFF), UART_IER_DLAB_0_0);
+    tegra_uart_writel(ctlr, comm_param & ~TEGRA_UART_LCR_DLAB, UART_LCR_0);
+
+    /* dummy read to ensure write is posted */
+    tegra_uart_readl(ctlr, UART_SPR_0);
+
+    ctlr->initialized = true;
+
+  conf_err:
+    if (rc != E_SUCCESS) {
+#ifdef UART_CLOCKS
+        tegra_clk_disable(ctlr->id.hw_handle->clk);
+#endif
+    }
+
+    return rc;
+}
+
+SECTION_UART_TEXT void
+tegra_uart_flush_tx_hw_fifo(const struct tegra_uart_ctlr * const ctlr)
+{
+    if (ctlr->initialized) {
+        while ((tegra_uart_readl(ctlr, UART_LSR_0) & TEGRA_UART_LSR_TX_SHIFT_EMPTY) == 0U) {
+        }
+    }
+}
+
+SECTION_UART_TEXT bool
+tegra_uart_is_tx_ready(const struct tegra_uart_ctlr * const ctlr)
+{
+    bool        empty = false;
+
+    if (!ctlr->initialized) {
+        goto out;
+    }
+
+    empty = (tegra_uart_readl(ctlr, UART_LSR_0) & TEGRA_UART_LSR_THRE_EMPTY) != 0U;
+
+  out:
+    return empty;
+}
+
+
+SECTION_UART_TEXT void
+tegra_uart_write_char(const struct tegra_uart_ctlr * const ctlr,
+                      const char c)
+{
+    if (!ctlr->initialized) {
+        goto out;
+    }
+
+    while (!tegra_uart_is_tx_ready(ctlr)) {
+    }
+    tegra_uart_writel(ctlr, c, UART_THR_DLAB_0_0);
+
+  out:
+    return;
+}
+
+SECTION_UART_TEXT void
+tegra_uart_write(const struct tegra_uart_ctlr * const ctlr,
+                 const char *buf,
+                 uint32_t count)
+{
+    uint32_t    i;
+
+    for (i = 0; i < count; i += 1U) {
+        tegra_uart_write_char(ctlr, *buf++);
+    }
+}
+
+SECTION_UART_TEXT void
+tegra_uart_write_string(const struct tegra_uart_ctlr * const ctlr,
+                        const char *buf)
+{
+    while (*buf != '\0') {
+        tegra_uart_write_char(ctlr, *buf++);
+    }
+}
+
+SECTION_UART_TEXT char
+tegra_uart_read_char(const struct tegra_uart_ctlr * const ctlr)
+{
+    char        ch              = '\0';
+
+    if (!ctlr->initialized) {
+        goto out;
+    }
+
+    while ((tegra_uart_readl(ctlr, UART_LSR_0) & TEGRA_UART_LSR_RDY) == 0U) {
+    }
+
+    ch = (char)tegra_uart_readl(ctlr, UART_THR_DLAB_0_0);
+
+  out:
+    return ch;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/utc/module-utc-nosafety-config.mk b/spe-freertos-bsp/fsp/source/drivers/utc/module-utc-nosafety-config.mk
new file mode 100644
index 0000000..3d3f895
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/utc/module-utc-nosafety-config.mk
@@ -0,0 +1,41 @@
+#
+# Copyright (c) 2023 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-utc-nosafety-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-osa*.mk' files.
+MODULE_UTC_NOSAFETY_CONFIG        := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_UTC_NOSAFETY_DEPENDS       := SOC CLUSTER CPL FSP_COMMON
+$(foreach _,$(MODULE_UTC_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_UTC_NOSAFETY_SOURCE_DIR     = $(FSP_COMMON_REPO)/drivers/utc
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_UTC_NOSAFETY_INCLUDES       =
diff --git a/spe-freertos-bsp/fsp/source/drivers/utc/module-utc-nosafety.mk b/spe-freertos-bsp/fsp/source/drivers/utc/module-utc-nosafety.mk
new file mode 100644
index 0000000..5d109d4
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/utc/module-utc-nosafety.mk
@@ -0,0 +1,64 @@
+#
+# Copyright (c) 2023 NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-utc-nosafety.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_UTC_NOSAFETY_NAME          := UTC_NOSAFETY
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_UTC_NOSAFETY_DEFINED       := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_UTC_NOSAFETY_DEPENDS       := UTC_NOSAFETY SOC CPL
+$(foreach _,$(CONFIG_UTC_NOSAFETY_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_UTC_NOSAFETY_C_SRC          =
+MODULE_UTC_NOSAFETY_C_SRC         += $(MODULE_UTC_NOSAFETY_SOURCE_DIR)/utc-client.c
+MODULE_UTC_NOSAFETY_C_SRC         += $(CPL_SOC_IDS)/utc-ids.c
+MODULE_UTC_NOSAFETY_C_SRC         += $(CPL_SOC_PORT)/utc-port.c
+
+#
+# Assembly source
+MODULE_UTC_NOSAFETY_ASM_SRC        =
+
+#
+# Special C Flags
+MODULE_UTC_NOSAFETY_C_FLAGS        =
+
+#
+# Special ASM Flags
+MODULE_UTC_NOSAFETY_ASM_FLAGS      =
diff --git a/spe-freertos-bsp/fsp/source/drivers/utc/utc-client.c b/spe-freertos-bsp/fsp/source/drivers/utc/utc-client.c
new file mode 100644
index 0000000..fa02a72
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/utc/utc-client.c
@@ -0,0 +1,594 @@
+/*
+ * Copyright (c) 2023 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/* Compiler headers */
+#include <stdbool.h>                        // for true
+#include <stdint.h>                         // for uint32_t
+#include <stddef.h>                         // for NULL
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                 // for CT_ASSERT
+#include <soc-common/hw-const.h>            /* Must appear before any hwinc files */
+
+/* HW headers */
+#include <address_map_new.h>                // for NV_ADDRESS_MAP_UTC_...
+#include <arutc.h>                          // for utc registers
+
+/* Late FSP headers */
+#include <misc/nvrm_drf.h>                  // for NV_DRF* macros
+#include <error/common-errors.h>            // for E_SUCCESS, error_t, FSP_...
+#include <irq/safe-irqs.h>                  // for irq_safe_enable...
+#include <debug/assert.h>                   // for ASSERT
+#include <misc/macros.h>                    // for UNUSED
+
+/* Module-specific FSP headers */
+#include <utc/utc-mmio.h>                   // for readl, writel_...
+#include <utc/sections-utc.h>               // Immune from CT_ASSERT protection
+#include <utc/utc-errors.h>                 // for E_UTC_...
+#include <utc/utc.h>                        // for utc_init, utc...
+#include <utc/utc-port.h>                   // for utc_port_...
+#include <utc/utc-priv.h>                   // for utc_id...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__UTC__UTC_MMIO_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+
+#define UTC_COMMON_BASE         NV_ADDRESS_MAP_UTC_COMMON_32BITBASE
+#define UTC_COMMON_LIMIT        NV_ADDRESS_MAP_UTC_COMMON_32BITLIMIT
+#define UTC_LIMIT               NV_ADDRESS_MAP_UTC_32BITLIMIT
+
+#define COMMON_REG(x)           (UTC_COMMON_##x##_0)
+#define TX_REG(x)               (UTC_TX_CLIENT_1_##x##_0)
+#define RX_REG(x)               (UTC_RX_CLIENT_1_##x##_0)
+
+#define COMMON_DRF(r, f, v)     NV_DRF_VAL(UTC_COMMON, r, f, v)
+#define TX_DRF(r, f, v)         NV_DRF_VAL(UTC_TX_CLIENT_1, r, f, v)
+#define RX_DRF(r, f, v)         NV_DRF_VAL(UTC_RX_CLIENT_1, r, f, v)
+#define TX_DRF_NUM(r, f, n)     NV_DRF_NUM(UTC_TX_CLIENT_1, r, f, n)
+#define RX_DRF_NUM(r, f, n)     NV_DRF_NUM(UTC_RX_CLIENT_1, r, f, n)
+
+#define UTC_CLIENT_ID_MAX       16U
+#define UTC_TX_FIFO_SZ          128U
+
+/* status flags */
+static bool rx_enabled = false;
+static bool utc_poll   = false;
+static bool utc_inited = false;
+
+static uintptr_t rx_queue;
+
+static inline uint32_t
+utc_common_reg(const uint32_t reg)
+{
+    const uint32_t addr = UTC_BASE + reg;
+
+    ASSERT((addr >= UTC_COMMON_BASE)  && (addr < UTC_COMMON_LIMIT));
+
+    return addr;
+}
+
+static inline uint32_t
+utc_client_reg(const struct utc_client *cl, uint32_t reg)
+{
+    const uint32_t addr = cl->base + reg;
+
+    ASSERT((addr >= UTC_BASE)  && (addr < UTC_LIMIT));
+
+    return addr;
+}
+
+static inline void
+utc_writel(const struct utc_client *cl, uint32_t val, uint32_t reg)
+{
+    const uint32_t addr = utc_client_reg(cl, reg);
+
+    writel(val, addr);
+}
+
+static inline uint32_t
+utc_readl(const struct utc_client *cl, uint32_t reg)
+{
+    return readl(utc_client_reg(cl, reg));
+}
+
+static void
+utc_tx_init(const struct utc_client *cl)
+{
+    uint32_t val = 0U;
+
+    /* perform a soft reset to start with a clean slate */
+    val = TX_DRF_NUM(COMMAND, SOFT_RESET, 1U);
+    utc_writel(cl, val, TX_REG(COMMAND));
+
+    /* drain any existing interrupts */
+    utc_writel(cl, 0U, TX_REG(INTR_MASK));
+
+    /* enable TX */
+    val = TX_DRF_NUM(ENABLE, ENABLE, 1U);
+    utc_writel(cl, val, TX_REG(ENABLE));
+}
+
+static error_t
+utc_rx_init(const struct utc_client *cl)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t val = 0U;
+
+    /* okay to not use rx */
+    if (!cl->enable_rx) {
+        goto out;
+    }
+
+    ret = utc_port_rx_queue_create(&rx_queue);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    /* perform a soft reset to start with a clean slate */
+    val = RX_DRF_NUM(COMMAND, SOFT_RESET, 1U);
+    utc_writel(cl, val, RX_REG(COMMAND));
+
+    /* drain any existing interrupts */
+    utc_writel(cl, 0U, RX_REG(INTR_MASK));
+
+    /* Enable RX_REQ interrupts */
+    if (!utc_poll) {
+        val = RX_DRF_NUM(INTR_MASK, RX_REQ, 1U);
+        utc_writel(cl, val, RX_REG(INTR_MASK));
+    }
+
+    /* Enable RX */
+    val = RX_DRF_NUM(ENABLE, ENABLE, 1U);
+    utc_writel(cl, val, RX_REG(ENABLE));
+
+    rx_enabled = true;
+
+out:
+    return ret;
+}
+
+static error_t
+utc_validate_global_cfg(const struct utc_client *cl)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t val;
+
+    val = readl(utc_common_reg(COMMON_REG(ENABLE)));
+    val = COMMON_DRF(ENABLE, ENABLE, val);
+    if (val == 0U) {
+        ret = E_UTC_NOT_INITED;
+        goto out;
+    }
+
+out:
+    return ret;
+}
+
+static inline void
+utc_write_char(const struct utc_client *cl, const char ch)
+{
+    uint32_t fr;
+
+    do {
+        fr = utc_readl(cl, TX_REG(FIFO_STATUS));
+        fr = TX_DRF(FIFO_STATUS, FULL, fr);
+    } while (fr != 0U);
+
+    utc_writel(cl, ch, TX_REG(TX_DATA));
+}
+
+static void
+utc_handle_rx_req_irq(const struct utc_client *cl, bool *isr_flag)
+{
+    error_t  status = E_SUCCESS;
+    uint32_t occupancy;
+    uint32_t c_in;
+    uint32_t i;
+
+    occupancy = utc_readl(cl, RX_REG(FIFO_OCCUPANCY)) & 0xFFU;
+    for (i = 0U; i < occupancy; i += 1U) {
+        c_in = utc_readl(cl, RX_REG(RX_DATA)) & 0xFFU;
+        status = utc_port_rx_queue_send_from_isr(rx_queue,
+                                                 (char *)&c_in,
+                                                 isr_flag);
+        if (status != E_SUCCESS) {
+            break;
+        }
+    }
+}
+
+static void
+utc_irq_handler(void *data)
+{
+    const struct utc_client *cl = (const struct utc_client *)data;
+    uint32_t isr;
+    uint32_t rx_req;
+    bool     isr_flag;
+
+    isr = utc_readl(cl, RX_REG(INTR_STATUS));
+    do {
+        rx_req = RX_DRF(INTR_STATUS, RX_REQ, isr);
+        if (rx_req != 0U) {
+            utc_handle_rx_req_irq(cl, &isr_flag);
+        }
+        utc_writel(cl, isr, RX_REG(INTR_CLEAR));
+        isr = utc_readl(cl, RX_REG(INTR_STATUS));
+    } while (isr != 0U);
+
+    utc_port_isr_exit(isr_flag);
+}
+
+static inline uint64_t
+utc_get_elapsed_ticks(uint64_t tstart, uint64_t timeout)
+{
+    uint64_t tcurr = utc_port_get_elapsed_usecs(0ULL);
+    uint64_t elapsed = 0UL;
+
+    if ((tcurr - tstart) < timeout) {
+        elapsed = (timeout - (tcurr - tstart));
+    }
+
+    return elapsed;
+}
+
+SECTION_UTC_TEXT error_t
+utc_is_tx_ready(const struct utc_client *cl, bool *ready)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t fr;
+
+    if ((cl == NULL) || (ready == NULL)) {
+        ret = E_UTC_NULL_PTR;
+        goto out;
+    }
+
+    if (!utc_inited) {
+        ret = E_UTC_NOT_INITED;
+        goto out;
+    }
+
+    fr = utc_readl(cl, TX_REG(FIFO_STATUS));
+    fr = TX_DRF(FIFO_STATUS, FULL, fr);
+    *ready = (fr == 0U);
+
+out:
+    return ret;
+}
+
+SECTION_UTC_TEXT error_t
+utc_get_tx_empty_space(const struct utc_client *cl, uint8_t *count)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t occupancy;
+
+    if ((cl == NULL) || (count == NULL)) {
+        ret = E_UTC_NULL_PTR;
+        goto out;
+    }
+
+    if (!utc_inited) {
+        ret = E_UTC_NOT_INITED;
+        goto out;
+    }
+
+    occupancy = utc_readl(cl, TX_REG(FIFO_OCCUPANCY)) & 0xFFU;
+    *count = (uint8_t)(UTC_TX_FIFO_SZ - occupancy);
+
+out:
+    return ret;
+}
+
+SECTION_UTC_TEXT error_t
+utc_puts(const struct utc_client *cl, const char *s)
+{
+    error_t ret = E_SUCCESS;
+
+    if ((cl == NULL) || (s == NULL)) {
+        ret = E_UTC_NULL_PTR;
+        goto out;
+    }
+
+    if (!utc_inited) {
+        ret = E_UTC_NOT_INITED;
+        goto out;
+    }
+
+    while (*s != '\0') {
+        utc_write_char(cl, *s++);
+    }
+
+out:
+    return ret;
+}
+
+SECTION_UTC_TEXT error_t
+utc_putc(const struct utc_client *cl, const char ch)
+{
+    error_t ret = E_SUCCESS;
+
+    if (cl == NULL) {
+        ret = E_UTC_NULL_PTR;
+        goto out;
+    }
+
+    if (!utc_inited) {
+        ret = E_UTC_NOT_INITED;
+        goto out;
+    }
+
+    utc_write_char(cl, ch);
+
+out:
+    return ret;
+}
+
+SECTION_UTC_TEXT error_t
+utc_write_now(const struct utc_client *cl,
+              const char *buf,
+              uint32_t count)
+{
+    error_t ret = E_SUCCESS;
+    uint32_t i;
+
+    if ((cl == NULL) || (buf == NULL)) {
+        ret = E_UTC_NULL_PTR;
+        goto out;
+    }
+
+    if (!utc_inited) {
+        ret = E_UTC_NOT_INITED;
+        goto out;
+    }
+
+    if (count == 0UL) {
+        goto out;
+    }
+
+    for (i = 0U; i < count; i += 1U) {
+        utc_write_char(cl, *buf);
+        buf++;
+    }
+
+out:
+    return ret;
+}
+
+SECTION_UTC_TEXT error_t
+utc_write(const struct utc_client *cl,
+          const char *buf,
+          uint32_t count,
+          uint32_t *written,
+          uint64_t timeout_us)
+{
+    error_t  ret = E_SUCCESS;
+    uint64_t tstart;
+    uint64_t timeout_left = 0UL;
+    uint32_t write_cnt = 0UL;
+    uint32_t fr;
+
+    if ((cl == NULL) || (buf == NULL) || (written == NULL)) {
+        ret = E_UTC_NULL_PTR;
+        goto out;
+    }
+
+    if (!utc_inited) {
+        ret = E_UTC_NOT_INITED;
+        goto out;
+    }
+
+    if (count == 0UL) {
+        goto out;
+    }
+
+    tstart = utc_port_get_elapsed_usecs(0ULL);
+    do {
+        fr = utc_readl(cl, TX_REG(FIFO_STATUS));
+        fr = TX_DRF(FIFO_STATUS, FULL, fr);
+        if (fr == 0U) {
+            utc_writel(cl, *buf, TX_REG(TX_DATA));
+            buf++;
+            write_cnt += 1UL;
+        }
+        timeout_left = utc_get_elapsed_ticks(tstart, timeout_us);
+    } while ((write_cnt < count) && (timeout_left != 0U));
+
+    if (timeout_left == 0U) {
+        ret = E_UTC_TIMED_OUT;
+    }
+
+    *written = write_cnt;
+
+out:
+    return ret;
+}
+
+SECTION_UTC_TEXT error_t
+utc_tx_flush(const struct utc_client *cl)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t val = 0U;
+
+    if (cl == NULL) {
+        ret = E_UTC_NULL_PTR;
+        goto out;
+    }
+
+    if (!utc_inited) {
+        ret = E_UTC_NOT_INITED;
+        goto out;
+    }
+
+    val = TX_DRF_NUM(COMMAND, FLUSH, 1U);
+    utc_writel(cl, val, TX_REG(COMMAND));
+
+out:
+    return ret;
+}
+
+SECTION_UTC_TEXT error_t
+utc_getc(const struct utc_client *cl, char *ch)
+{
+    error_t  ret = E_SUCCESS;
+    uint32_t fr;
+
+    if ((cl == NULL) || (ch == NULL)) {
+        ret = E_UTC_NULL_PTR;
+        goto out;
+    }
+
+    if (!utc_inited) {
+        ret = E_UTC_NOT_INITED;
+        goto out;
+    }
+
+    if (!rx_enabled) {
+        ret = E_UTC_RX_DISABLED;
+        goto out;
+    }
+
+    do {
+        fr = utc_readl(cl, RX_REG(FIFO_STATUS));
+        fr = RX_DRF(FIFO_STATUS, EMPTY, fr);
+    } while (fr != 0U);
+
+    *ch = utc_readl(cl, RX_REG(RX_DATA)) & 0xFFU;
+
+out:
+    return ret;
+}
+
+SECTION_UTC_TEXT error_t
+utc_read(const struct utc_client *cl,
+         char *buf,
+         uint32_t count,
+         uint32_t *read,
+         uint64_t timeout_us)
+{
+    error_t  ret = E_SUCCESS;
+    uint64_t tstart;
+    uint64_t timeout_left = 0;
+    uint32_t read_cnt = 0UL;
+
+    if ((cl == NULL) || (buf == NULL)) {
+        ret = E_UTC_NULL_PTR;
+        goto out;
+    }
+
+    if (!utc_inited) {
+        ret = E_UTC_NOT_INITED;
+        goto out;
+    }
+
+    if (!rx_enabled) {
+        ret = E_UTC_RX_DISABLED;
+        goto out;
+    }
+
+    if (count == 0UL) {
+        goto out;
+    }
+
+    tstart = utc_port_get_elapsed_usecs(0ULL);
+    timeout_left = timeout_us;
+    for (read_cnt = 0UL; read_cnt < count; read_cnt += 1UL) {
+        ret = utc_port_rx_queue_receive(rx_queue,
+                                        buf,
+                                        timeout_left);
+        if (ret != E_SUCCESS) {
+            break;
+        }
+        buf++;
+        timeout_left = utc_get_elapsed_ticks(tstart, timeout_us);
+    }
+
+out:
+    *read = read_cnt;
+    return ret;
+}
+
+SECTION_UTC_INIT_TEXT error_t
+utc_client_init(const struct utc_client *cl)
+{
+    error_t ret = E_SUCCESS;
+    uint32_t cl_base = 0U;
+
+    if (cl == NULL) {
+        ret = E_UTC_NULL_PTR;
+        goto out;
+    }
+
+    if ((cl->id == 0U) || (cl->id > UTC_CLIENT_ID_MAX)) {
+        ret = E_UTC_INVALID_PARAM;
+        goto out;
+    }
+
+    cl_base = CL_BASE(cl->id);
+    ASSERT((cl_base >= UTC_BASE) && (cl_base < UTC_LIMIT));
+    ASSERT(cl_base == cl->base);
+
+    ret = utc_validate_global_cfg(cl);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    if (cl->irq == UINT32_MAX) {
+        utc_poll = true;
+    }
+
+    utc_tx_init(cl);
+    ret = utc_rx_init(cl);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    if (!utc_poll) {
+        ret = irq_safe_set_handler(cl->irq, utc_irq_handler, (void*)cl);
+        if (ret == E_SUCCESS) {
+            ret = irq_safe_enable(cl->irq);
+        }
+    }
+
+    if (ret == E_SUCCESS) {
+        utc_inited = true;
+    }
+
+out:
+    return ret;
+}
diff --git a/spe-freertos-bsp/fsp/source/drivers/vic/irqapi-vic.c b/spe-freertos-bsp/fsp/source/drivers/vic/irqapi-vic.c
new file mode 100644
index 0000000..c187c0f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/vic/irqapi-vic.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2018-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>               // for uint32_t
+#include <stddef.h>               // for NULL
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>       // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/arm-vic.h>          // for arm_vic_disable, arm_vic_enable
+#include <debug/abort.h>          // for tegra_abort, FSP__DEBUG__ABORT_H
+#include <irq/safe-irqs.h>        // for irq_safe_disable, irq_safe_enable
+#include <misc/bitops.h>          // for EXTRACT
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <misc/attributes.h>      // for WEAK
+#include <error/common-errors.h>  // for error_t, E_SUCCESS, MODULE_ID_VIC...
+
+/* Module-specific FSP headers */
+#include <vic/tegra-vic.h>        // for TEGRA_INTERRUPT_TO_IRQ, TEGRA_INTER...
+#include <vic/vic-abort-codes.h>  // for ABORT_BAD_IRQ, FSP__VIC__VIC_ABORT_...
+#include <vic/sections-vic.h>     // Immune from CT_ASSERT protection
+#include <vic/vic-ld.h>           // for vic_base_addr, irq_vect_t...
+#include <vic/vic-errors.h>       // for E_VIC_INVALID_VECTOR_ID, ...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__CPU__ARM_VIC_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ABORT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__VIC__TEGRA_VIC_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__VIC__VIC_ABORT_CODES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__VIC__VIC_LD_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__VIC__VIC_ERRORS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * irq_safe_enable()   - enables the interrupt on a particular vector
+ *
+ * @vector:     interrupt vector number (VIC and IRQ are encoded in the
+ *              vector number) to be enabled.
+ *
+ * This function will enable the vector to generate interrupts.  Until this
+ * function is called, no interrupts from the indicated vector will be presented
+ * to the CPU.
+ */
+SECTION_VIC_TEXT WEAK error_t
+irq_safe_enable(const uint32_t vector)
+{
+    uint32_t    vic;
+    uint32_t    irq;
+    error_t     err = E_SUCCESS;
+
+    if (vector > MAX_VIC_INTERRUPT_VECTOR) {
+        err = E_VIC_INVALID_VECTOR;
+        goto out;
+    }
+
+    vic     = TEGRA_INTERRUPT_TO_VIC(vector);
+    irq     = TEGRA_INTERRUPT_TO_IRQ(vector);
+
+    arm_vic_enable(vic_base_addr[vic], irq);
+
+out:
+    return err;
+}
+
+/**
+ * irq_safe_disable()  - disables the interrupt on a particular vector
+ *
+ * @vector:     interrupt vector number (VIC and IRQ are encoded in the
+ *              vector number) to be disabled.
+ *
+ * This function will disable the vector to prevent it from generating
+ * interrupts.  After this function has been called, no interrupts from the
+ * specified vector will be presented to the CPU.
+ */
+SECTION_VIC_TEXT WEAK error_t
+irq_safe_disable(const uint32_t vector)
+{
+    uint32_t    vic;
+    uint32_t    irq;
+    error_t     err = E_SUCCESS;
+
+    if (vector > MAX_VIC_INTERRUPT_VECTOR) {
+        err = E_VIC_INVALID_VECTOR;
+        goto out;
+    }
+
+    vic     = TEGRA_INTERRUPT_TO_VIC(vector);
+    irq     = TEGRA_INTERRUPT_TO_IRQ(vector);
+
+    arm_vic_disable(vic_base_addr[vic], irq);
+
+out:
+    return err;
+}
+
+SECTION_VIC_TEXT error_t
+irq_state_safe_save(const uint32_t vic, irq_context *ctx)
+{
+    error_t err = E_SUCCESS;
+
+    if (vic > MAX_VIC_INSTANCE_ID) {
+        err = E_VIC_INVALID_VIC_INSTANCE;
+        goto out;
+    }
+
+    if (ctx == NULL) {
+        err = E_VIC_NULL_INPUT_PARAMETER;
+        goto out;
+    }
+
+    arm_vic_save_state(vic_base_addr[vic], ctx);
+
+out:
+    return err;
+}
+
+SECTION_VIC_TEXT error_t
+irq_state_safe_restore(const uint32_t vic, const irq_context *const ctx)
+{
+    error_t err = E_SUCCESS;
+
+    if (vic > MAX_VIC_INSTANCE_ID) {
+        err = E_VIC_INVALID_VIC_INSTANCE;
+        goto out;
+    }
+
+    if (ctx == NULL) {
+        err = E_VIC_NULL_INPUT_PARAMETER;
+        goto out;
+    }
+
+    arm_vic_restore_state(vic_base_addr[vic], ctx);
+
+out:
+    return err;
+}
+
+/**
+ * bad_irq()            - ISR to be called for an unrecognized interrupt
+ *
+ * @vector:     interrupt vector number (VIC and IRQ are encoded in the
+ *              vector number) that generated the unrecognized interrupt.
+ *
+ * This function is the interrupt handler that gets called for any interrupt
+ * vector that does not otherwise have a registered interrupt handler.
+ *
+ * Return Values:
+ *      none
+ *
+ * This function is not expected to return.
+ */
+SECTION_VIC_ERROR_TEXT void
+bad_irq(const irq_vect_t vector)
+{
+    tegra_abort(ABORT_BAD_IRQ, EXTRACT(vector, 15U, 0U, uint32_t));
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/vic/vic-asm.S b/spe-freertos-bsp/fsp/source/drivers/vic/vic-asm.S
new file mode 100644
index 0000000..fa23e34
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/vic/vic-asm.S
@@ -0,0 +1,48 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION &
+ * AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
+ *
+ * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
+ * property and proprietary rights in and to this material, related
+ * documentation and any modifications thereto. Any use, reproduction,
+ * disclosure or distribution of this material and related documentation
+ * without an express license agreement from NVIDIA CORPORATION or
+ * its affiliates is strictly prohibited.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <soc-common/hw-const.h>        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <araps_vic.h>
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>
+
+/* Module-specific FSP headers */
+#include <vic/vic-asm.h>
+
+	.section	SECTION_STR_VIC_TEXT, "ax"
+	.arm
+	.syntax		unified
+/*
+ * Code to handle the end of interrupt processing.
+ *
+ * Defines the vic0_isr_end and vic1_isr_end functions
+ */
+	ACK_VIC0_IRQ	vic0_isr_end
+	rtosIRQ_EXIT
+
+	ACK_VIC1_IRQ	vic1_isr_end
+	rtosIRQ_EXIT
+
+.if MAX_VIC_CONTROLLER == 4
+	ACK_VIC2_IRQ	vic2_isr_end
+	rtosIRQ_EXIT
+
+	ACK_VIC3_IRQ	vic3_isr_end
+	rtosIRQ_EXIT
+.endif
diff --git a/spe-freertos-bsp/fsp/source/drivers/vic/vic-init.c b/spe-freertos-bsp/fsp/source/drivers/vic/vic-init.c
new file mode 100644
index 0000000..13740d0
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/vic/vic-init.c
@@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>               // for uint32_t
+#include <string.h>               // for NULL
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>       // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/arm-vic.h>          // for arm_vic_set_isr_vect_addr, FSP__ARM...
+#include <misc/linker-symbols.h>  // for IMAGE_SYM_BASE
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <error/common-errors.h>  // for error_t, E_SUCCESS
+
+/* Module-specific FSP headers */
+#include <vic/tegra-vic.h>        // for num_isr_map_entries, FSP__VIC__TEGR...
+#include <vic/sections-vic.h>     // Immune from CT_ASSERT protection
+#include <vic/vic-ld.h>           // for vic_isr_map_s, Image$$VIC_ISR_MAP$$...
+#include <vic/vic-errors.h>       // for E_VIC_INVALID_VECTOR_ID, ....
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__CPU__ARM_VIC_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__LINKER_SYMBOLS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__VIC__TEGRA_VIC_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__VIC__VIC_LD_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__VIC__VIC_ERRORS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @brief safe_tegra_vic_init()
+ *
+ * This function will initialize the various VICs and setup the vector
+ * addresses for each vector.
+ *
+ * No input argument.
+ *
+ * @pre Client driver has mapped ISR for respective device
+ * interrupts using isr_map_entry.
+ *
+ * @func_req_id 9373448
+ *
+ * @retval E_SUCCESS                   For success
+ * @retval E_VIC_INVALID_VECTOR        ISR map entry with invalid vector ID
+ * @retval E_VIC_NULL_IRQ_HANDLER      ISR map entry with NULL interrupt handler
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_15_4, "Approval: Bug 200532006, DR: SWE-FSP-029-SWSADR.docx")
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
+SECTION_VIC_INIT_TEXT error_t tegra_safe_vic_init(void)
+{
+    uint32_t                    i;
+    const struct vic_isr_map_s  *entry;
+    uint32_t                    vic;
+    uint32_t                    irq_num;
+    error_t                     err = E_SUCCESS;
+
+    for (i = 0; i < num_isr_map_entries(); i += 1U) {
+        entry = &(((struct vic_isr_map_s *)&IMAGE_SYM_BASE(VIC_ISR_MAP))[i]);
+        if (entry->vector > MAX_VIC_INTERRUPT_VECTOR) {
+            err = E_VIC_INVALID_VECTOR;
+            break;
+        }
+        if (entry->isr_handler == NULL) {
+            err = E_VIC_NULL_IRQ_HANDLER;
+            break;
+        }
+
+        vic = TEGRA_INTERRUPT_TO_VIC(entry->vector);
+        irq_num = TEGRA_INTERRUPT_TO_IRQ(entry->vector);
+        arm_vic_set_isr_vect_addr(vic_base_addr[vic],
+                                  irq_num,
+                                  entry->isr_handler);
+    }
+
+    return err;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_15_4, "Approval: Bug 200532006, DR: SWE-FSP-029-SWSADR.docx")
+
+
+/**
+ * @brief tegra_vic_init()
+ *
+ * This function will initialize the various VICs and set up the vector
+ * addresses for each vector. The function skips the entries with invalid
+ * value of vector id or isr_handler
+ *
+ * No input arguments and return value.
+ *
+ * @pre Client driver has mapped ISR for respective device
+ * interrupts using isr_map_entry.
+ *
+ * @func_req_id 9373448
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx")
+SECTION_VIC_INIT_TEXT void tegra_vic_init(void)
+{
+    uint32_t             i;
+    const struct vic_isr_map_s  *entry;
+    uint32_t             vic;
+    uint32_t             irq_num;
+
+    for (i = 0; i < num_isr_map_entries(); i += 1U) {
+        entry = &(((struct vic_isr_map_s *)&IMAGE_SYM_BASE(VIC_ISR_MAP))[i]);
+        if ((entry->vector <= MAX_VIC_INTERRUPT_VECTOR) &&
+            (entry->isr_handler != NULL)) {
+            vic = TEGRA_INTERRUPT_TO_VIC(entry->vector);
+            irq_num = TEGRA_INTERRUPT_TO_IRQ(entry->vector);
+            arm_vic_set_isr_vect_addr(vic_base_addr[vic],
+                                      irq_num,
+                                      entry->isr_handler);
+        }
+    }
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/watchdog/module-no-watchdog-config.mk b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-no-watchdog-config.mk
new file mode 100644
index 0000000..206d978
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-no-watchdog-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-no-watchdog-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_NO_WATCHDOG_CONFIG           := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_NO_WATCHDOG_DEPENDS          :=
+$(foreach _,$(MODULE_NO_WATCHDOG_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_NO_WATCHDOG_DRIVERS_DIR       = $(FSP_COMMON_REPO)/drivers/watchdog
+MODULE_NO_WATCHDOG_SOURCE_DIR        = $(MODULE_NO_WATCHDOG_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_NO_WATCHDOG_INCLUDES          =
diff --git a/spe-freertos-bsp/fsp/source/drivers/watchdog/module-no-watchdog.mk b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-no-watchdog.mk
new file mode 100644
index 0000000..9af1b37
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-no-watchdog.mk
@@ -0,0 +1,62 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-no-watchdog.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_NO_WATCHDOG_NAME         := NO_WATCHDOG
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_NO_WATCHDOG_DEFINED      := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_NO_WATCHDOG_DEPENDS      := NO_WATCHDOG SOC CPL OSA DEBUG_NOSAFETY
+$(foreach _,$(CONFIG_NO_WATCHDOG_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_NO_WATCHDOG_C_SRC         =
+MODULE_NO_WATCHDOG_C_SRC        += $(MODULE_NO_WATCHDOG_DRIVERS_DIR)/watchdog-stubs.c
+
+#
+# Assembly source
+MODULE_NO_WATCHDOG_ASM_SRC       =
+
+#
+# Special C Flags
+MODULE_NO_WATCHDOG_C_FLAGS       =
+
+#
+# Special ASM Flags
+MODULE_NO_WATCHDOG_ASM_FLAGS     =
diff --git a/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog-config.mk b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog-config.mk
new file mode 100644
index 0000000..43bd03d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-watchdog-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_WATCHDOG_CONFIG          := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_WATCHDOG_DEPENDS         :=
+$(foreach _,$(MODULE_WATCHDOG_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_WATCHDOG_DRIVERS_DIR      = $(FSP_COMMON_REPO)/drivers/watchdog
+MODULE_WATCHDOG_SOURCE_DIR       = $(MODULE_WATCHDOG_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_WATCHDOG_INCLUDES         =
diff --git a/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog-statistics-config.mk b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog-statistics-config.mk
new file mode 100644
index 0000000..cb4ae1e
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog-statistics-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-watchdog-statistics-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_WATCHDOG_STATISTICS_CONFIG       := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_WATCHDOG_STATISTICS_DEPENDS      :=
+$(foreach _,$(MODULE_WATCHDOG_STATISTICS_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_WATCHDOG_STATISTICS_DRIVERS_DIR   = $(FSP_COMMON_REPO)/drivers/watchdog
+MODULE_WATCHDOG_STATISTICS_SOURCE_DIR    = $(MODULE_WATCHDOG_STATISTICS_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_WATCHDOG_STATISTICS_INCLUDES      =
diff --git a/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog-statistics.mk b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog-statistics.mk
new file mode 100644
index 0000000..ed98dc5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog-statistics.mk
@@ -0,0 +1,62 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-watchdog-statistics.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_WATCHDOG_STATISTICS_NAME         := WATCHDOG_STATISTICS
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_WATCHDOG_STATISTICS_DEFINED      := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_WATCHDOG_STATISTICS_DEPENDS      := WATCHDOG_STATISTICS
+$(foreach _,$(CONFIG_WATCHDOG_STATISTICS_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_WATCHDOG_STATISTICS_C_SRC         =
+MODULE_WATCHDOG_STATISTICS_C_SRC        += $(MODULE_WATCHDOG_STATISTICS_DRIVERS_DIR)/watchdog-statistics.c
+
+#
+# Assembly source
+MODULE_WATCHDOG_STATISTICS_ASM_SRC       =
+
+#
+# Special C Flags
+MODULE_WATCHDOG_STATISTICS_C_FLAGS       = -DWATCHDOG_STATISTICS=1
+
+#
+# Special ASM Flags
+MODULE_WATCHDOG_STATISTICS_ASM_FLAGS     =
diff --git a/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog-task-config.mk b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog-task-config.mk
new file mode 100644
index 0000000..8404c76
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog-task-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-watchdog-task-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_WATCHDOG_TASK_CONFIG         := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_WATCHDOG_TASK_DEPENDS        := LOGGER_NOSAFETY WDT
+$(foreach _,$(MODULE_WATCHDOG_TASK_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_WATCHDOG_TASK_DRIVERS_DIR     = $(FSP_COMMON_REPO)/drivers/watchdog
+MODULE_WATCHDOG_TASK_SOURCE_DIR      = $(MODULE_WATCHDOG_TASK_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_WATCHDOG_TASK_INCLUDES        =
diff --git a/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog-task.mk b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog-task.mk
new file mode 100644
index 0000000..215c9ba
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog-task.mk
@@ -0,0 +1,62 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-watchdog-task.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_WATCHDOG_TASK_NAME       := WATCHDOG_TASK
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_WATCHDOG_TASK_DEFINED    := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_WATCHDOG_TASK_DEPENDS    := WATCHDOG_TASK LOGGER_NOSAFETY WDT
+$(foreach _,$(CONFIG_WATCHDOG_TASK_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_WATCHDOG_TASK_C_SRC       =
+MODULE_WATCHDOG_TASK_C_SRC      += $(MODULE_WATCHDOG_TASK_DRIVERS_DIR)/watchdog-task.c
+
+#
+# Assembly source
+MODULE_WATCHDOG_TASK_ASM_SRC     =
+
+#
+# Special C Flags
+MODULE_WATCHDOG_TASK_C_FLAGS     =
+
+#
+# Special ASM Flags
+MODULE_WATCHDOG_TASK_ASM_FLAGS   =
diff --git a/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog.mk b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog.mk
new file mode 100644
index 0000000..9ecea5a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-watchdog.mk
@@ -0,0 +1,62 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-watchdog.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_WATCHDOG_NAME            := WATCHDOG
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_WATCHDOG_DEFINED         := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_WATCHDOG_DEPENDS         := WATCHDOG SOC CPL OSA DEBUG_NOSAFETY TKE
+$(foreach _,$(CONFIG_WATCHDOG_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_WATCHDOG_C_SRC            =
+MODULE_WATCHDOG_C_SRC           += $(MODULE_WATCHDOG_DRIVERS_DIR)/watchdog.c
+
+#
+# Assembly source
+MODULE_WATCHDOG_ASM_SRC          =
+
+#
+# Special C Flags
+MODULE_WATCHDOG_C_FLAGS          =
+
+#
+# Special ASM Flags
+MODULE_WATCHDOG_ASM_FLAGS        =
diff --git a/spe-freertos-bsp/fsp/source/drivers/watchdog/module-wdt-config.mk b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-wdt-config.mk
new file mode 100644
index 0000000..8025d34
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-wdt-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE),1)
+$(info Including:  module-wdt-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_WDT_CONFIG               := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_WDT_DEPENDS              :=
+$(foreach _,$(MODULE_WDT_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_WDT_DRIVERS_DIR           = $(FSP_COMMON_REPO)/drivers/watchdog
+MODULE_WDT_SOURCE_DIR            = $(MODULE_WDT_DRIVERS_DIR)
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_WDT_INCLUDES              =
diff --git a/spe-freertos-bsp/fsp/source/drivers/watchdog/module-wdt.mk b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-wdt.mk
new file mode 100644
index 0000000..efe708c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/watchdog/module-wdt.mk
@@ -0,0 +1,64 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-wdt.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_WDT_NAME                 := WDT
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_WDT_DEFINED              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_WDT_DEPENDS              := WDT SOC CPL OSA
+$(foreach _,$(CONFIG_WDT_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_WDT_C_SRC                 =
+MODULE_WDT_C_SRC                += $(MODULE_WDT_DRIVERS_DIR)/wdt-tegra.c
+MODULE_WDT_C_SRC                += $(CPL_SOC_IDS)/wdt-tegra-ids.c
+
+#
+# Assembly source
+MODULE_WDT_ASM_SRC               =
+MODULE_WDT_ASM_SRC              += $(CPL_SOC_PORT)/wdt-irq.S
+
+#
+# Special C Flags
+MODULE_WDT_C_FLAGS               =
+
+#
+# Special ASM Flags
+MODULE_WDT_ASM_FLAGS             =
diff --git a/spe-freertos-bsp/fsp/source/drivers/watchdog/watchdog-statistics.c b/spe-freertos-bsp/fsp/source/drivers/watchdog/watchdog-statistics.c
new file mode 100644
index 0000000..d49f4d6
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/watchdog/watchdog-statistics.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                            // for uint64_t, UINT64_MAX
+#include <string.h>                            // for NULL, memcpy
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                    // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <osa/rtos-task.h>                     // for rtosTaskEnterCritical
+#include <debug/assert.h>                      // for ASSERT
+#include <error/common-errors.h>               // for E_SUCCESS, error_t
+#include <misc/attributes.h>                   // for UNUSED
+#include <misc/macros.h>                       // for START_RFD_BLOCK, END_RFD_BLOCK, ...
+
+/* Module-specific FSP headers */
+#include <watchdog/sections-watchdog.h>        // Immune from CT_ASSERT protection
+#include <watchdog/watchdog-errors.h>          // for E_WDT_ERR_NULL_PTR
+#include <watchdog/watchdog-statistics.h>      // for WatchdogStatistics
+#include <watchdog/watchdog-internal.h>        // for WatchdogTaskState, Wat...
+#include <watchdog/watchdog.h>                 // for WatchdogGetTaskStatistics
+#include <watchdog/watchdog-stats-internal.h>  // for WatchdogStatsAddItem
+#include <watchdog/watchdog-types.h>           // for WatchdogTaskID
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ASSERT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_STATISTICS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_INTERNAL_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_STATS_INTERNAL_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_TYPES_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file watchdog-statistics.c
+ * @brief Implementation of Watchdog Statistics
+ */
+
+/*
+ * There is no point in attempting to compile this file if
+ * watchdog statistics are not enabled.  This checks for that
+ * and causes an error to be reported.
+ */
+#if !defined(WATCHDOG_STATISTICS) || (WATCHDOG_STATISTICS != 1)
+#error "WATCHDOG_STATISTICS != 1"
+#endif
+
+SECTION_WATCHDOG_INIT_TEXT void
+WatchdogStatsInit(WatchdogTaskState *state)
+{
+    ASSERT(state != NULL);
+
+    state->taskStats.maxItemsInQueue = 0;
+    state->taskStats.itemStats.count = 0;
+    state->taskStats.itemStats.accumulatedTime = 0;
+    state->taskStats.itemStats.minTime = UINT64_MAX;
+    state->taskStats.itemStats.maxTime = 0;
+}
+
+SECTION_WATCHDOG_TEXT void
+WatchdogStatsAddItem(WatchdogTaskState *state)
+{
+    WatchdogTaskStatistics      *stats;
+
+    ASSERT(state != NULL);
+
+    stats = &state->taskStats;
+
+    /*
+     * Track the maximum number of items that have
+     * appeared in the queue.
+     */
+    if (state->itemsInQueue > stats->maxItemsInQueue) {
+        stats->maxItemsInQueue = state->itemsInQueue;
+    }
+}
+
+SECTION_WATCHDOG_TEXT void
+WatchdogStatsStartItem(const WatchdogTaskState *state)
+{
+    UNUSED(state);
+}
+
+SECTION_WATCHDOG_TEXT void
+WatchdogStatsCompleteItem(WatchdogTaskState *state,
+                          uint64_t completeTime)
+{
+    WatchdogStatistics          *stats;
+    uint64_t                    deltaT;
+    uint64_t                    maxTimeout;
+    uint64_t                    histIndex;
+
+    ASSERT(state != NULL);
+    ASSERT(state->taskTimeout > 0ULL);
+
+    stats = &state->taskStats.itemStats;
+
+    deltaT = completeTime - state->lastStartTime;
+    stats->accumulatedTime += deltaT;
+
+    if (stats->minTime > deltaT) {
+        stats->minTime = deltaT;
+    }
+
+    if (stats->maxTime < deltaT) {
+        stats->maxTime = deltaT;
+    }
+
+    /*
+     * Compute the index into the histogram that represents the
+     * percentage (decimals...0-9, 10-19, 20-29, etc).
+     */
+    maxTimeout = state->taskTimeout;
+    histIndex = (WATCHDOG_STATS_NUM_BUCKETS * deltaT) / maxTimeout;
+
+    stats->histogram[histIndex] += 1U;
+
+    stats->count += 1U;
+}
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx")
+SECTION_WATCHDOG_TEXT error_t
+WatchdogGetTaskStatistics(const WatchdogTaskID ID,
+                          WatchdogTaskStatistics *stats)
+{
+    error_t                 rc              = E_SUCCESS;
+    const WatchdogTaskState *statep         = NULL;
+
+    rc = WatchdogValidateID(ID);
+    if (rc != E_SUCCESS) {
+        goto out;
+    }
+
+    if (stats == NULL) {
+        rc = E_WDT_ERR_NULL_PTR;
+        goto out;
+    }
+
+    statep = &watchdogState[ID];
+
+    rtosTaskEnterCritical();
+
+    (void)memcpy(stats, &statep->taskStats, sizeof(WatchdogTaskStatistics));
+
+    rtosTaskExitCritical();
+
+  out:
+    return rc;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/watchdog/watchdog-stubs.c b/spe-freertos-bsp/fsp/source/drivers/watchdog/watchdog-stubs.c
new file mode 100644
index 0000000..a64d722
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/watchdog/watchdog-stubs.c
@@ -0,0 +1,213 @@
+_Pragma("coverity compliance block(include) \
+         (deviate MISRA_C_2012_Rule_1_2 \"Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx\") \
+         (deviate MISRA_C_2012_Directive_4_8 \"Approval: Bug 200534384, DR: SWE-FSP-011-SWSADR.docx\")")
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stddef.h>                        // for NULL
+#include <stdint.h>                        // for uint64_t, uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <osa/rtos-task.h>                 // for rtosTaskHandle
+#include <debug/assert.h>                  // for ASSERT, MODULE_ID_ABORT
+#include <error/common-errors.h>           // for error_t, E_SUCCESS
+#include <misc/attributes.h>               // for WEAK, UNUSED
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <watchdog/sections-watchdog.h>    /* Immune from CT_ASSERT protection */
+#include <watchdog/watchdog.h>             // for WatchdogAddItem, WatchdogA...
+#include <watchdog/watchdog-errors.h>      // for E_WDT_ERR_NO_STATS
+#include <watchdog/watchdog-statistics.h>  // for WatchdogTaskStatistics
+#include <watchdog/watchdog-types.h>       // for WatchdogTaskID
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ASSERT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_STATISTICS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_TYPES_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file watchdog-stubs.c
+ * @brief Stubs for watchdog APIs if the watchdog framework is not used
+ */
+
+SECTION_WATCHDOG_INIT_TEXT WEAK error_t
+WatchdogInit(uint64_t minTimeout,
+             uint64_t maxTimeout,
+             uint64_t defaultTimeout)
+{
+    UNUSED(minTimeout);
+    UNUSED(maxTimeout);
+    UNUSED(defaultTimeout);
+
+    return E_SUCCESS;
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_WATCHDOG_INIT_TEXT WEAK error_t WatchdogTaskMonitor(const rtosTaskHandle taskID, uint64_t maxTime, WatchdogTaskID *pID)
+{
+    UNUSED(taskID);
+    UNUSED(maxTime);
+
+    ASSERT(pID != NULL);
+
+    *pID = 0;
+    return E_SUCCESS;
+}
+
+SECTION_WATCHDOG_TEXT WEAK error_t
+WatchdogAddItem(const WatchdogTaskID ID)
+{
+    UNUSED(ID);
+
+    return E_SUCCESS;
+}
+
+SECTION_WATCHDOG_TEXT WEAK error_t
+WatchdogAddItemFromISR(const WatchdogTaskID ID)
+{
+    UNUSED(ID);
+
+    return E_SUCCESS;
+}
+
+SECTION_WATCHDOG_TEXT WEAK error_t
+WatchdogTaskStartItem(const WatchdogTaskID ID)
+{
+    UNUSED(ID);
+
+    return E_SUCCESS;
+}
+
+SECTION_WATCHDOG_TEXT WEAK error_t
+WatchdogStartItem(void)
+{
+    return E_SUCCESS;
+}
+
+SECTION_WATCHDOG_TEXT WEAK error_t
+WatchdogTaskCompleteItem(WatchdogTaskID ID)
+{
+    UNUSED(ID);
+
+    return E_SUCCESS;
+}
+
+SECTION_WATCHDOG_TEXT WEAK error_t
+WatchdogCompleteItem(void)
+{
+    return E_SUCCESS;
+}
+
+SECTION_WATCHDOG_TEXT WEAK error_t
+WatchdogCheckStatus(void)
+{
+    return E_SUCCESS;
+}
+
+SECTION_WATCHDOG_TEXT WEAK error_t
+WatchdogCheckTaskStatus(const WatchdogTaskID ID)
+{
+    UNUSED(ID);
+
+    return E_SUCCESS;
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_WATCHDOG_TEXT WEAK error_t WatchdogGetTaskID(const rtosTaskHandle taskID, WatchdogTaskID *pID)
+{
+    ASSERT(pID != NULL);
+
+    UNUSED(taskID);
+
+    *pID = 0;
+    return E_SUCCESS;
+}
+
+SECTION_WATCHDOG_TEXT WEAK error_t
+WatchdogGetNumTaskIDs(uint32_t *pNumTaskIDs)
+{
+    ASSERT(pNumTaskIDs != NULL);
+
+    *pNumTaskIDs = 0;
+
+    return E_SUCCESS;
+}
+
+SECTION_WATCHDOG_TEXT WEAK error_t
+WatchdogCallbackTaskOutOfBounds(WatchdogTaskID ID)
+{
+    UNUSED(ID);
+
+    return E_SUCCESS;
+}
+
+SECTION_WATCHDOG_TEXT WEAK error_t
+WatchdogCallbackApplicationCheck(void)
+{
+    return E_SUCCESS;
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_WATCHDOG_TEXT WEAK error_t WatchdogGetTaskStatistics(const WatchdogTaskID ID, WatchdogTaskStatistics *stats)
+{
+    UNUSED(ID);
+    UNUSED(stats);
+
+    return E_WDT_ERR_NO_STATS;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_8, "Approval: Bug 200534384, DR: SWE-FSP-011-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/watchdog/watchdog-task.c b/spe-freertos-bsp/fsp/source/drivers/watchdog/watchdog-task.c
new file mode 100644
index 0000000..67481d9
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/watchdog/watchdog-task.c
@@ -0,0 +1,396 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                       // for false, true
+#include <stddef.h>                        // for NULL
+#include <stdint.h>                        // for uintptr_t, uint32_t, uint8_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <osa/rtos-errors.h>               // for E_RTOS_NEXT_UNBLOCK_TIME_E...
+#include <osa/rtos-event-group.h>          // for rtosEventGroupSetBitsFromISR
+#include <osa/rtos-task.h>                 // for rtosTaskYieldFromISR
+#include <osa/rtos-values.h>               // for rtosPASS, rtosFAIL, rtosFALSE
+#include <armv7-mpu.h>                     // for MPU_NTASK_REGIONS
+#include <cpu/armv7-mpu.h>                 // for R5_DRACR_AP_PRIV_RW, R5_DR...
+#include <cpu/armv7-mpu-safertos.h>        // for mpuParameters_t, R5MPU_CHE...
+#include <cpu/sections-armv7-mpu.h>        // Immune from CT_ASSERT protection
+#include <debug/abort-codes.h>             // for ABORT_CODE
+#include <debug/assert.h>                  // for ASSERT, tegra_abort
+#include <error/common-errors.h>           // for E_SUCCESS, error_t
+#include <hw-config/vic-irqs.h>            // for INTERRUPT_WDTFIQ, INTERRUP...
+#include <irq/safe-irqs.h>                 // for irq_safe_enable
+#include <logger-config.h>                 // for LOG_LEVEL_INFO_ENABLE, LOG...
+#include <logger/logger.h>                 // for LOG_INFO, LOG_WARN, LOG_ERROR
+#include <logger/logger-data.h>            // for LOG_FL_ERROR, LOG_FL_NONE
+#include <misc/attributes.h>               // for UNUSED, ALIGN, FSP__MISC__...
+#include <misc/bitops.h>                   // for BIT
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, ...
+
+/* Module-specific FSP headers */
+#include <sections/sections-strings.h>     // Immune from CT_ASSERT protection
+#include <watchdog/sections-watchdog.h>    // Immune from CT_ASSERT protection
+#include <watchdog/watchdog-logging.h>     // for WATCHDOG_LOG_INIT, WATCHDO...
+#include <watchdog/watchdog-task.h>        // for WatchdogInitParameters
+#include <watchdog/watchdog.h>             // for WatchdogCheckStatus, Watch...
+#include <watchdog/wdt-tegra-priv.h>       // for tegra_wdt
+#include <watchdog/tegra-safe-wdt.h>       // for tegra_safe_wdt_conf, ...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSA__RTOS_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_EVENT_GROUP_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_VALUES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_MPU_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_MPU_SAFERTOS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ABORT_CODES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ASSERT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HW_CONFIG__VIC_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__LOGGER__LOGGER_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__LOGGER__LOGGER_DATA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_LOGGING_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WDT_TEGRA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__TEGRA_SAFE_WDT_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_9, "Approval: Bug 200532001, DR: SWE-FSP-016-SWSADR.docx")
+static rtosEventGroupHandle     WatchdogSignal         SECTION_WATCHDOG_DATA;
+static rtosEventGroup           WatchdogSignalMemory   SECTION_WATCHDOG_DATA;
+
+static struct tegra_wdt_conf    wdt_conf               SECTION_WATCHDOG_INIT_DATA;
+
+extern struct tegra_wdt         tegra_wdt_instance     SECTION_WATCHDOG_DATA;
+
+static rtosTick                 WatchdogPetPeriod      SECTION_WATCHDOG_DATA;
+
+static uint8_t  WatchdogTaskStack[WATCHDOG_STACK_DEPTH] SECTION_WATCHDOG_PRIV_STACKS
+                                                ALIGN(WATCHDOG_STACK_DEPTH);
+static uint8_t  WatchdogTCB[rtosTCB_OVERHEAD_BYTES]     SECTION_WATCHDOG_DATA;
+
+static const char       WatchdogTask_name[] SECTION_STRINGS_RODATA = "Watchdog";
+
+static void WatchdogTaskCode(void *parameters);
+
+rtosTaskParameters WatchdogTaskParams SECTION_WATCHDOG_INIT_DATA = {
+    .pvTaskCode         = WatchdogTaskCode,
+    .pcTaskName         = &WatchdogTask_name[0],
+    .pxTCB              = WatchdogTCB,
+    .pcStackBuffer      = WatchdogTaskStack,
+    .uxStackDepthBytes  = WATCHDOG_STACK_DEPTH,
+    .pvParameters       = NULL,
+    .uxPriority         = 0,            // to be set by WatchdogTaskInit()
+    .pvObject           = NULL,
+    .xUsingFPU          = rtosFALSE,
+    .pxMPUParameters    = NULL,         // to be set by WatchdogTaskInit()
+    .uxPrivilegeLevel   = RTOS_SYSTEM_MODE,
+};
+
+/*
+ * Watchdog Task's MPU Regions
+ *
+ * This defines the watchdog task's stack region.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_11_4, "Approval: Bug 200532002, DR: SWE-FSP-063-SWSADR.docx")
+static mpuParameters_t watchdog_task_mpu_regions[MPU_NTASK_REGIONS] SECTION_MPU_DATA =
+{
+    [0]  = {
+        .flags          = R5MPU_FL_VALID | R5MPU_FL_SIZE,
+        .index          = 0,                    // filled in by WatchdogTaskInit
+        .permissions    = R5MPU_CHECK_PRIV_RW,
+        .access         = R5_DRACR_NORMAL_CACHED
+                        | R5_DRACR_XN | R5_DRACR_AP_PRIV_RW,
+        .base           = (uintptr_t)WatchdogTaskStack,
+        .size           = WATCHDOG_STACK_DEPTH,
+    },
+};
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_9, "Approval: Bug 200532001, DR: SWE-FSP-016-SWSADR.docx",
+              MISRA, DEVIATE, Rule_11_4, "Approval: Bug 200532002, DR: SWE-FSP-063-SWSADR.docx")
+
+/*
+ * Events that can be signalled
+ */
+#define WATCHDOG_LVL1_TIMEOUT   BIT(0)          // WDT FIQ interrupt fired
+#define WATCHDOG_LVL2_TIMEOUT   BIT(1)          // WDT IRQ interrupt fired
+#define WATCHDOG_PET_TIMER      BIT(2)          // time to pet the WDT
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_WATCHDOG_ERROR_TEXT static void Watchdog_fiq_callback(uint32_t status, void *data)
+{
+    rtosError   rc;
+    rtosBool    wake;
+
+    UNUSED(status);
+    UNUSED(data);
+
+    LOG_ERROR(WATCHDOG_LOG_LVL1_TIMEOUT, LOG_FL_ERROR, 0);
+
+    /*
+     * Indicate that the WDT FIQ occurred
+     */
+    rc = rtosEventGroupSetBitsFromISR(WatchdogSignal, WATCHDOG_LVL1_TIMEOUT,
+                                      &wake);
+    ASSERT(rc == rtosPASS);
+    /*
+     * XXX: TODO
+     * Better error handling
+     */
+
+    rtosTaskYieldFromISR(wake);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_WATCHDOG_ERROR_TEXT static void Watchdog_irq_callback(uint32_t status, void *data)
+{
+    rtosError   rc;
+    rtosBool    wake;
+
+    UNUSED(status);
+    UNUSED(data);
+
+    LOG_INFO(WATCHDOG_LOG_LVL2_TIMEOUT, LOG_FL_NONE, 0);
+
+    /*
+     * Indicate the the WDT IRQ occurred
+     */
+    rc = rtosEventGroupSetBitsFromISR(WatchdogSignal, WATCHDOG_LVL2_TIMEOUT,
+                                      &wake);
+    ASSERT(rc == rtosPASS);
+    /*
+     * XXX: TODO
+     * Better error handling
+     */
+
+    rtosTaskYieldFromISR(wake);
+}
+
+SECTION_WATCHDOG_TEXT WEAK error_t
+WatchdogCallbackApplicationCheck(void)
+{
+    return E_SUCCESS;
+}
+
+SECTION_WATCHDOG_INIT_TEXT rtosError
+WatchdogTaskInit(const void * const parameters)
+{
+    rtosError                   rc      = rtosPASS;
+    error_t                     err;
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx", MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR: SWE-FSP-024-SWSADR.docx")
+    WatchdogInitParameters      *parms  = (WatchdogInitParameters *)parameters;
+
+    LOG_INFO(WATCHDOG_LOG_INIT, LOG_FL_START, 0);
+
+    ASSERT(parms != NULL);
+
+    WatchdogPetPeriod = parms->pet_period;
+    WatchdogTaskParams.uxPriority = parms->task_priority;
+
+    /*
+     * Determine if the watchdog task should setup an MPU
+     * region for its stack.
+     */
+    if (parms->watchdog_mpu) {
+        watchdog_task_mpu_regions[0].index = parms->stack_priority;
+        WatchdogTaskParams.pxMPUParameters = watchdog_task_mpu_regions;
+    }
+
+    rc = rtosEventGroupCreate(&WatchdogSignalMemory, &WatchdogSignal);
+    if (rc != rtosPASS) {
+        goto exit;
+    }
+
+    /*
+     * Initialize the watchdog framework
+     */
+    err = WatchdogInit(parms->min_timeout,
+                       parms->max_timeout,
+                       parms->default_timeout);
+    if (err != E_SUCCESS) {
+        rc = rtosFAIL;
+        goto exit;
+    }
+
+    /*
+     * Set up the Watchdog HW
+     */
+
+    /*
+     * Initializing the Watchdog timer Configuration register
+     * NvTimer0 as source which is set for RTOS 1ms periodic timer.
+     * Period set for 15 of 1msec timer
+     * Enabled all irqs
+     * Threshold set to default value
+     */
+    wdt_conf.tmrsrc = 0x0;
+    wdt_conf.period = parms->hw_period;
+    wdt_conf.irq_en = true;
+    wdt_conf.fiq_en = true;
+    wdt_conf.remoteIrq_en = true;
+    wdt_conf.sys_dbg_rst_en = false;
+    wdt_conf.sys_por_rst_en = false;
+    wdt_conf.tsc_ref_en = false;
+    wdt_conf.err_threshold = 0x7;
+    wdt_conf.irq_callback = Watchdog_irq_callback;
+    wdt_conf.irq_data = NULL;
+    wdt_conf.fiq_callback = Watchdog_fiq_callback;
+    wdt_conf.fiq_data = NULL;
+
+    err = tegra_safe_wdt_setup(&tegra_wdt_instance.id, &wdt_conf);
+    if (err != E_SUCCESS) {
+        goto exit;
+    }
+
+    /*
+     * Make sure that the watchdog timer will be enabled.
+     */
+    if (!parms->wdt_enabled) {
+        goto exit;
+    }
+
+    /* Start the watchdog timer*/
+    err = tegra_safe_wdt_start(&tegra_wdt_instance.id);
+    if (err != E_SUCCESS) {
+        goto exit;
+    }
+
+    err = irq_safe_enable(INTERRUPT_WDTFIQ);
+    ASSERT(err == E_SUCCESS);
+    err = irq_safe_enable(INTERRUPT_WDTIRQ);
+    ASSERT(err == E_SUCCESS);
+
+  exit:
+    LOG_INFO(WATCHDOG_LOG_INIT, LOG_FL_END, rc);
+    return rc;
+}
+
+/*
+ * RTOS task for managing the watchdog timer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_WATCHDOG_TEXT NO_RETURN static void WatchdogTaskCode(void *parameters)
+{
+    rtosError           rc;
+    rtosEventBits       events;
+    rtosEventBits       wait_events;
+
+    UNUSED(parameters);
+    while (true) {
+        wait_events = (WATCHDOG_LVL1_TIMEOUT | WATCHDOG_LVL2_TIMEOUT);
+
+        LOG_INFO(WATCHDOG_LOG_SLEEP, LOG_FL_NONE, 0);
+
+        /*
+         * Wait for the WDT to report a timeout or a specific amount
+         * of time has elapsed.
+         */
+        rc = rtosEventGroupWaitBits(WatchdogSignal, wait_events,
+                                    false, false, &events,
+                                    WatchdogPetPeriod);
+
+        LOG_INFO(WATCHDOG_LOG_WAKEUP, LOG_FL_NONE, rc, events);
+
+        if (rc != rtosPASS) {
+            if (rc == E_RTOS_NEXT_UNBLOCK_TIME_EXPIRED) {
+                events |= WATCHDOG_PET_TIMER;
+            } else {
+                continue;
+            }
+        }
+
+        /*
+         * If the event was caused by FIQ or IRQ from the
+         * watchdog hardware, abort to the ccplex and let
+         * it deal with it.
+         */
+        if ((events & (WATCHDOG_LVL1_TIMEOUT | WATCHDOG_LVL2_TIMEOUT)) != 0UL) {
+            tegra_abort(ABORT_CODE(WATCHDOG, 0U), events);
+        }
+
+        /*
+         * So far eveything is OK.  Go check the tasks to make
+         * sure that they've made progress
+         */
+        rc = WatchdogCheckStatus();
+        if (rc != E_SUCCESS) {
+            LOG_WARN(WATCHDOG_LOG_TIMEOUT, LOG_FL_ERROR, rc);
+            continue;
+        }
+
+        /*
+         * Check to see if the application has other checks
+         * to perform
+         */
+        if (WatchdogCallbackApplicationCheck() != E_SUCCESS) {
+            LOG_WARN(WATCHDOG_LOG_APPLICATION, LOG_FL_ERROR, 0UL);
+            continue;
+        }
+
+        /*
+         * Reset the watchdog timer
+         */
+        rc = tegra_safe_wdt_start(&tegra_wdt_instance.id);
+        if (rc != E_SUCCESS) {
+            LOG_WARN(WATCHDOG_LOG_TIMEOUT, LOG_FL_ERROR, rc);
+            continue;
+        }
+    }
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/watchdog/watchdog.c b/spe-freertos-bsp/fsp/source/drivers/watchdog/watchdog.c
new file mode 100644
index 0000000..4c1d388
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/watchdog/watchdog.c
@@ -0,0 +1,646 @@
+_Pragma("coverity compliance block(include) \
+         (deviate MISRA_C_2012_Rule_1_2 \"Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx\") \
+         (deviate MISRA_C_2012_Directive_4_8 \"Approval: Bug 200534384, DR: SWE-FSP-011-SWSADR.docx\")")
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                                // for bool, false, true
+#include <stddef.h>                                 // for NULL
+#include <stdint.h>                                 // for uint64_t, uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                         // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <osa/rtos-task.h>                          // for rtosTaskEnterCritical
+#include <debug/abort-codes.h>                      // for ABORT_CODE, FSP__...
+#include <debug/abort.h>                            // for tegra_abort, FSP_...
+#include <error/common-errors.h>                    // for E_SUCCESS, error_t
+#include <misc/attributes.h>                        // for WEAK
+#include <misc/bitops.h>                            // for LOW32, HI32
+#include <misc/macros.h>                            // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <watchdog-config.h>                        // Immune from CT_ASSERT protection
+#include <watchdog/sections-watchdog.h>             // Immune from CT_ASSERT protection
+#include <watchdog/watchdog-errors.h>               // for E_WDT_ERR_TASK_OU...
+#include <watchdog/watchdog-internal.h>             // for WatchdogTaskState
+#include <watchdog/watchdog.h>                      // for FSP__WATCHDOG__WA...
+#include <watchdog/watchdog-statistics.h>           // for WatchdogTaskStati...
+#include <watchdog/watchdog-statistics-internal.h>  // for WatchdogStatsAddItem
+#include <watchdog/watchdog-types.h>                // for WatchdogTaskID
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ABORT_CODES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ABORT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_INTERNAL_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_STATISTICS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_STATISTICS_INTERNAL_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_TYPES_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file watchdog.c
+ * @brief Implementation of Watchdog framework
+ */
+
+/**
+ * @brief State of all monitored tasks
+ *
+ * This array is used by the watchdog framework to track the state of all
+ * of the tasks that are being monitored.
+ */
+WatchdogTaskState        watchdogState[WATCHDOG_MAX_TASKS]
+                                                        SECTION_WATCHDOG_DATA;
+
+/**
+ * @brief Number of monitored tasks
+ *
+ * Number of tasks that have been registered with the watchdog framework
+ * to be monitored.
+ */
+static uint32_t                 num_tasks       SECTION_WATCHDOG_DATA = 0;
+
+/**
+ * @brief Watchdog framework initialized
+ *
+ * A boolean that indicates if the watchdog framework has been initialized
+ * or not.
+ */
+static bool                     init            SECTION_WATCHDOG_DATA = false;
+
+/**
+ * @brief Minimum task timeout
+ *
+ * A value set during initialization of the watchdog framework that indicates
+ * the minimum value that can be specified for a timeout when a task is
+ * registered to be monitored.
+ */
+static uint64_t                 wdt_min_timeout SECTION_WATCHDOG_INIT_DATA = 0;
+
+/**
+ * @brief Maximum task timeout
+ *
+ * A value set during initialization of the watchdog framework that indicates
+ * the maximum value that can be specified for a timeout when a task is
+ * registered to be monitored.
+ */
+static uint64_t                 wdt_max_timeout SECTION_WATCHDOG_INIT_DATA = 0;
+
+/**
+ * @brief Default task timeout
+ *
+ * A value set during initialization of the watchdog framework that indicates
+ * the default value that will be used for a timeout when a task is registered
+ * to be monitored if the task does not specify a timeout value.
+ */
+static uint64_t                 wdt_default_timeout SECTION_WATCHDOG_INIT_DATA = 0;
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx")
+SECTION_WATCHDOG_TEXT error_t
+WatchdogValidateID(const WatchdogTaskID ID)
+{
+    error_t                 rc              = E_SUCCESS;
+    const WatchdogTaskState *statep;
+
+    if (!init) {
+        rc = E_WDT_ERR_WATCHDOG_NOT_INIT;
+        goto out;
+    }
+
+    if (ID >= num_tasks) {
+        rc = E_WDT_ERR_NO_TASK;
+        goto out;
+    }
+
+    statep = &watchdogState[ID];
+
+    if (statep->taskStatus == WATCHDOG_NOT_MONITORED) {
+        rc = E_WDT_ERR_NO_TASK;
+        goto out;
+    }
+
+  out:
+    return rc;
+
+}
+
+SECTION_WATCHDOG_INIT_TEXT error_t
+WatchdogInit(uint64_t minTimeout,
+             uint64_t maxTimeout,
+             uint64_t defaultTimeout)
+{
+    error_t     rc      = E_SUCCESS;
+
+    /*
+     * Perform various bounds checks on the timeout values:
+     * 1) min <= max
+     * 2) max < 2^32
+     * 3) min <= default <= max
+     */
+    if (minTimeout > maxTimeout) {
+        rc = E_WDT_ERR_INVALID_TIMEOUT;
+        goto out;
+    }
+
+    if ((defaultTimeout < minTimeout)
+        || (defaultTimeout > maxTimeout)) {
+        rc = E_WDT_ERR_INVALID_TIMEOUT;
+        goto out;
+    }
+
+    /*
+     * Set the variables to be used when checking a task's max time
+     */
+    wdt_min_timeout = minTimeout;
+    wdt_max_timeout = maxTimeout;
+    wdt_default_timeout = defaultTimeout;
+
+    init = true;
+
+  out:
+    return rc;
+}
+
+SECTION_WATCHDOG_INIT_TEXT error_t
+WatchdogTaskMonitor(const rtosTaskHandle taskID,
+                    uint64_t maxTime,
+                    WatchdogTaskID *pID)
+{
+    error_t             rc              = E_SUCCESS;
+    uint64_t            timeout         = maxTime;
+    WatchdogTaskState   *statep;
+
+    if (!init) {
+        rc = E_WDT_ERR_WATCHDOG_NOT_INIT;
+        goto out;
+    }
+
+    /*
+     * Check that maxTime is within bounds
+     */
+    if (maxTime > wdt_max_timeout) {
+        rc = E_WDT_ERR_INVALID_TIMEOUT;
+        goto out;
+    }
+
+    /*
+     * If maxTime is too small, use a default value
+     */
+    if (maxTime < wdt_min_timeout) {
+        timeout = wdt_default_timeout;
+    }
+
+    /*
+     * Make sure that we have space for adding another
+     * task to be monitored.
+     */
+    if (num_tasks >= WATCHDOG_MAX_TASKS) {
+        rc = E_WDT_ERR_TOO_MANY_TASKS;
+        goto out;
+    }
+
+    statep = &watchdogState[num_tasks];
+
+    /*
+     * Make sure that the next slot isn't actually
+     * used.
+     */
+    if (statep->taskStatus != WATCHDOG_NOT_MONITORED) {
+        rc = E_WDT_ERR_DUPLICATE_TASK;
+        goto out;
+    }
+
+    /*
+     * Set up the watchdog monitor entry.
+     */
+    statep->taskStatus  = WATCHDOG_TASK_WAITING;
+    statep->taskID      = taskID;
+    statep->taskTimeout = timeout;
+
+    WatchdogStatsInit(statep);
+
+    *pID = num_tasks;
+    num_tasks += 1UL;
+
+  out:
+    return rc;
+}
+
+SECTION_WATCHDOG_TEXT error_t
+WatchdogAddItem(const WatchdogTaskID ID)
+{
+    error_t             rc              = E_SUCCESS;
+    WatchdogTaskState   *statep;
+
+    rc = WatchdogValidateID(ID);
+    if (rc != E_SUCCESS) {
+        goto out;
+    }
+
+    statep = &watchdogState[ID];
+
+    rtosTaskEnterCritical();
+
+    statep->itemsInQueue += 1U;
+
+    WatchdogStatsAddItem(statep);
+
+    rtosTaskExitCritical();
+
+  out:
+    return rc;
+}
+
+SECTION_WATCHDOG_TEXT error_t
+WatchdogAddItemFromISR(const WatchdogTaskID ID)
+{
+    error_t             rc              = E_SUCCESS;
+    WatchdogTaskState   *statep;
+
+    rc = WatchdogValidateID(ID);
+    if (rc != E_SUCCESS) {
+        goto out;
+    }
+
+    statep = &watchdogState[ID];
+
+    statep->itemsInQueue += 1U;
+
+  out:
+    return rc;
+}
+
+SECTION_WATCHDOG_TEXT error_t
+WatchdogTaskStartItem(const WatchdogTaskID ID)
+{
+    error_t             rc              = E_SUCCESS;
+    WatchdogTaskState   *statep;
+
+    rc = WatchdogValidateID(ID);
+    if (rc != E_SUCCESS) {
+        goto out;
+    }
+
+    statep = &watchdogState[ID];
+
+    rtosTaskEnterCritical();
+
+    /*
+     * Make sure that there's actually work to do
+     */
+    if (statep->itemsInQueue == 0UL) {
+        rc = E_WDT_ERR_NO_WORK;
+        goto out_critical;
+    }
+
+    /*
+     * Make sure that the task has completed previous
+     * work prior to starting next piece of work
+     */
+    if (statep->taskStatus == WATCHDOG_ITEM_STARTED) {
+        rc = E_WDT_ERR_SEQUENCE;
+        goto out_critical;
+    }
+
+    /*
+     * Make sure that the task hasn't previously
+     * timed out
+     */
+    if (statep->taskStatus == WATCHDOG_ITEM_TIMEOUT) {
+        rc = E_WDT_ERR_TASK_OUT_OF_BOUNDS;
+        goto out_critical;
+    }
+
+    /*
+     * Capture the time and indicate that the task
+     * has started work
+     */
+    statep->lastStartTime = WatchdogGetTime();
+    statep->taskStatus = WATCHDOG_ITEM_STARTED;
+
+    WatchdogStatsStartItem(statep);
+
+  out_critical:
+    rtosTaskExitCritical();
+
+  out:
+    return rc;
+}
+
+SECTION_WATCHDOG_TEXT error_t
+WatchdogStartItem(void)
+{
+    error_t             rc              = E_SUCCESS;
+    rtosTaskHandle      task;
+    WatchdogTaskID      id;
+
+    if (!init) {
+        rc = E_WDT_ERR_WATCHDOG_NOT_INIT;
+        goto out;
+    }
+
+    /*
+     * Get the watchdog ID of the current task
+     */
+    task = rtosTaskGetCurrentTaskHandle();
+    rc = WatchdogGetTaskID(task, &id);
+    if (rc != E_SUCCESS) {
+        goto out;
+    }
+
+    rc = WatchdogTaskStartItem(id);
+
+  out:
+    return rc;
+}
+
+SECTION_WATCHDOG_TEXT error_t
+WatchdogTaskCompleteItem(WatchdogTaskID ID)
+{
+    error_t             rc              = E_SUCCESS;
+    WatchdogTaskState   *statep;
+    uint64_t            now;
+
+    rc = WatchdogValidateID(ID);
+    if (rc != E_SUCCESS) {
+        goto out;
+    }
+
+    rtosTaskEnterCritical();
+
+    statep = &watchdogState[ID];
+
+    /*
+     * Make sure that there's actually work to do
+     */
+    if (statep->itemsInQueue == 0UL) {
+        rc = E_WDT_ERR_NO_WORK;
+        goto out_critical;
+    }
+
+    /*
+     * Make sure that the task is actually processing
+     * work.
+     */
+    if (statep->taskStatus != WATCHDOG_ITEM_STARTED) {
+        rc = E_WDT_ERR_SEQUENCE;
+        goto out_critical;
+    }
+
+    statep->itemsInQueue -= 1U;
+
+    /*
+     * Make sure that there wasn't a timeout
+     */
+    now = WatchdogGetTime();
+    if ((now - statep->lastStartTime) <= statep->taskTimeout) {
+        statep->taskStatus = WATCHDOG_ITEM_COMPLETED;
+    } else {
+        statep->taskStatus = WATCHDOG_ITEM_TIMEOUT;
+
+        (void)WatchdogCallbackTaskOutOfBounds(ID);
+
+        rc = E_WDT_ERR_TASK_OUT_OF_BOUNDS;
+    }
+
+    WatchdogStatsCompleteItem(statep, now);
+
+  out_critical:
+    rtosTaskExitCritical();
+
+  out:
+    return rc;
+}
+
+SECTION_WATCHDOG_TEXT error_t
+WatchdogCompleteItem(void)
+{
+    error_t             rc              = E_SUCCESS;
+    rtosTaskHandle      task;
+    WatchdogTaskID      id;
+
+    if (!init) {
+        rc = E_WDT_ERR_WATCHDOG_NOT_INIT;
+        goto out;
+    }
+
+    /*
+     * Get the watchdog ID of the current task
+     */
+    task = rtosTaskGetCurrentTaskHandle();
+    rc = WatchdogGetTaskID(task, &id);
+    if (rc != E_SUCCESS) {
+        goto out;
+    }
+
+    rc = WatchdogTaskCompleteItem(id);
+
+  out:
+    return rc;
+}
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_15_4, "Approval: Bug 200532006, DR: SWE-FSP-029-SWSADR.docx")
+SECTION_WATCHDOG_TEXT error_t
+WatchdogCheckStatus(void)
+{
+    error_t                 rc              = E_SUCCESS;
+    error_t                 err             = E_SUCCESS;
+    const WatchdogTaskState *statep;
+    WatchdogTaskID          id;
+
+    if (!init) {
+        rc = E_WDT_ERR_WATCHDOG_NOT_INIT;
+        goto out;
+    }
+
+    for (id = 0; id < num_tasks; id += 1UL) {
+        statep = &watchdogState[id];
+
+        /*
+         * Skip over non-active tasks
+         */
+        if ((statep->taskStatus == WATCHDOG_NOT_MONITORED)
+            || (statep->taskStatus == WATCHDOG_TASK_WAITING)) {
+            continue;
+        }
+
+        rc = WatchdogCheckTaskStatus(id);
+        if (rc == E_WDT_ERR_TASK_OUT_OF_BOUNDS) {
+            rc = WatchdogCallbackTaskOutOfBounds(id);
+            if (rc == E_WDT_ERR_DONE) {
+                rc = E_WDT_ERR_TASK_OUT_OF_BOUNDS;
+                break;
+            }
+
+            err = E_WDT_ERR_TASK_OUT_OF_BOUNDS;
+        }
+
+        if (rc != E_SUCCESS) {
+            break;
+        }
+    }
+
+  out:
+    return (err == E_SUCCESS) ? rc : err;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_15_4, "Approval: Bug 200532006, DR: SWE-FSP-029-SWSADR.docx")
+
+SECTION_WATCHDOG_TEXT error_t
+WatchdogCheckTaskStatus(const WatchdogTaskID ID)
+{
+    error_t                 rc              = E_SUCCESS;
+    const WatchdogTaskState *statep;
+    uint64_t                now;
+
+    rc = WatchdogValidateID(ID);
+    if (rc != E_SUCCESS) {
+        goto out;
+    }
+
+    statep = &watchdogState[ID];
+
+    rtosTaskEnterCritical();
+
+    if (statep->taskStatus == WATCHDOG_ITEM_TIMEOUT) {
+        rc = E_WDT_ERR_TASK_OUT_OF_BOUNDS;
+        goto out_critical;
+    }
+
+    if (statep->taskStatus == WATCHDOG_ITEM_STARTED) {
+        now = WatchdogGetTime();
+        if ((now - statep->lastStartTime) > statep->taskTimeout) {
+            rc = E_WDT_ERR_TASK_OUT_OF_BOUNDS;
+        }
+    }
+
+  out_critical:
+    rtosTaskExitCritical();
+
+  out:
+    return rc;
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_WATCHDOG_TEXT error_t WatchdogGetTaskID(const rtosTaskHandle taskID, WatchdogTaskID *pID)
+{
+    error_t                 rc              = E_WDT_ERR_NO_TASK;
+    const WatchdogTaskState *statep;
+    WatchdogTaskID          id;
+
+    if (!init) {
+        rc = E_WDT_ERR_WATCHDOG_NOT_INIT;
+        goto out;
+    }
+
+    if (pID == NULL) {
+        rc = E_WDT_ERR_NULL_PTR;
+        goto out;
+    }
+
+    for (id = 0; id < num_tasks; id += 1UL) {
+        statep = &watchdogState[id];
+
+        if (statep->taskID == taskID) {
+            *pID = id;
+            rc = E_SUCCESS;
+            break;
+        }
+    }
+
+  out:
+    return rc;
+}
+
+SECTION_WATCHDOG_TEXT error_t
+WatchdogGetNumTaskIDs(uint32_t *pNumTaskIDs)
+{
+    error_t             rc              = E_SUCCESS;
+
+    if (!init) {
+        rc = E_WDT_ERR_WATCHDOG_NOT_INIT;
+        goto out;
+    }
+
+    if (pNumTaskIDs == NULL) {
+        rc = E_WDT_ERR_NULL_PTR;
+        goto out;
+    }
+
+    *pNumTaskIDs = num_tasks;
+
+  out:
+    return rc;
+}
+
+SECTION_WATCHDOG_TEXT WEAK error_t
+WatchdogCallbackTaskOutOfBounds(WatchdogTaskID ID)
+{
+    tegra_abort(ABORT_CODE(WDT, 1U), ID);
+
+    /*
+     * Not reached but needed to keep the compiler happy
+     */
+    return E_WDT_ERR_DONE;
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_WATCHDOG_TEXT WEAK error_t WatchdogGetTaskStatistics(const WatchdogTaskID ID, WatchdogTaskStatistics *stats)
+{
+    UNUSED(ID);
+    UNUSED(stats);
+    return E_WDT_ERR_NO_STATS;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_8, "Approval: Bug 200534384, DR: SWE-FSP-011-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/drivers/watchdog/wdt-tegra.c b/spe-freertos-bsp/fsp/source/drivers/watchdog/wdt-tegra.c
new file mode 100644
index 0000000..32e583b
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/drivers/watchdog/wdt-tegra.c
@@ -0,0 +1,498 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                   // for false, true
+#include <stdint.h>                    // for uint32_t, uint8_t
+#include <stddef.h>                    // IWYU pragma: keep
+                                       // for NULL
+#include <string.h>                    // for offsetof
+                                       // IWYU pragma: no_include <errno.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>            // for CT_ASSERT
+#include <soc-common/hw-const.h>       /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <artke_top.h>                 // for BASE_ADDRESS_TKE_TOP_WDT0, TKE...
+
+/* Late FSP headers */
+#include <osa/rtos-task.h>             // for rtosTaskEnterCritical, rtosTas...
+#include <error/common-errors.h>       // for E_SUCCESS, error_t
+#include <irq/safe-irqs.h>             // for in_interrupt, irq_safe_disable, irq...
+#include <misc/attributes.h>           // for FSP_ALIGNOF
+#include <misc/macros.h>               // for CONTAINER_OF
+#include <misc/nvrm_drf.h>             // for NV_DRF_NUM, FSP__MISC__NVRM_DRF_H
+#include <reg-access/reg-access.h>     // for readl_base_offset, writel_base...
+#include <debug/assert.h>              // for ASSERT
+
+/* Module-specific FSP headers */
+#include <watchdog/sections-wdt.h>     // Immune from CT_ASSERT protection
+#include <watchdog/watchdog-errors.h>  // for E_WDT_ERR_IRQ_CONFIG, E_WDT_ER...
+#include <watchdog/wdt-tegra-priv.h>   // for tegra_wdt, tegra_wdt_id, FSP__...
+#include <watchdog/tegra-safe-wdt.h>   // for tegra_safe_wdt_conf, ...
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__NVRM_DRF_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ASSERT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WDT_TEGRA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__TEGRA_SAFE_WDT_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+#define TEGRA_WDT_CONFIG_0              U32_C(TKE_TOP_WDT0_WDTCR_0 - BASE_ADDRESS_TKE_TOP_WDT0)
+#define TEGRA_WDT_STATUS_0              U32_C(TKE_TOP_WDT0_WDTSR_0 - BASE_ADDRESS_TKE_TOP_WDT0)
+#define TEGRA_WDT_COMMAND_0             U32_C(TKE_TOP_WDT0_WDTCMDR_0 - BASE_ADDRESS_TKE_TOP_WDT0)
+#define TEGRA_WDT_WINDOW_CONFIG_0       U32_C(TKE_TOP_WDT0_WDTFWCR_0 - BASE_ADDRESS_TKE_TOP_WDT0)
+#define TEGRA_WDT_UNLOCK_PATTERN_0      U32_C(TKE_TOP_WDT0_WDTUR_0 - BASE_ADDRESS_TKE_TOP_WDT0)
+#define TEGRA_WDT_UNLOCK_PATTERN_VALUE  0xC45AUL
+#define TEGRA_WDT_UNLOCK_CRC32          0xEDB88320UL
+
+static inline const struct tegra_wdt *
+tegra_wdt_from_id(const struct tegra_wdt_id *id)
+{
+    uint32_t wdtptr = fsp_c_wdtid_ptr_to_u32(id) - offsetof(struct tegra_wdt, id);
+    return fsp_u32_to_c_wdt_ptr(wdtptr);
+}
+
+static inline uint32_t
+tegra_wdt_readl(const struct tegra_wdt_id *id,
+                uint32_t reg)
+{
+    return readl_base_offset(id->base_addr, reg);
+}
+
+static inline void
+tegra_wdt_writel(const struct tegra_wdt_id *id,
+                 uint32_t val, uint32_t reg)
+{
+    writel_base_offset(val, id->base_addr, reg);
+}
+
+static SECTION_WDT_TEXT void
+tegra_wdt_unlock(const struct tegra_wdt_id *id)
+{
+    const struct tegra_wdt      *wdt_dev        = tegra_wdt_from_id(id);
+    uint32_t                    val;
+
+    if (wdt_dev->challenge_response) {
+        /*
+         * The Challenge is a LFSR value, present in the Unlock
+         * register.
+         *
+         * The Response is the next value of the LFSR, that needs to
+         * be written in the Unlock register.
+         *
+         * The LFSR uses the classical CRC-32 polynomial operating
+         * in shift right (reversed) direction, that is the next
+         * value is calculated as
+         *
+         * LFSR = (LFSR >> 1) ^ ((LFSR & 0x1) ? 0xEDB88320 : 0)
+         */
+        val = tegra_wdt_readl(id, TEGRA_WDT_UNLOCK_PATTERN_0);
+        val = (val >> 1) ^ (((val & 1UL) != 0UL) ? TEGRA_WDT_UNLOCK_CRC32 : 0UL);
+    } else {
+        val = TEGRA_WDT_UNLOCK_PATTERN_VALUE;
+    }
+
+    tegra_wdt_writel(id, val, TEGRA_WDT_UNLOCK_PATTERN_0);
+}
+
+static SECTION_WDT_TEXT void
+tegra_wdt_ack_internal(const struct tegra_wdt_id *id)
+{
+    tegra_wdt_unlock(id);
+    UNUSED(tegra_safe_wdt_start(id));
+}
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx")
+SECTION_WDT_TEXT error_t
+tegra_safe_wdt_start(const struct tegra_wdt_id *id)
+{
+    error_t                     rc              = E_SUCCESS;
+    const struct tegra_wdt      *wdt_dev;
+    uint32_t                    val;
+
+    if (id == NULL) {
+        rc = E_WDT_ERR_NULL_PTR;
+        goto out;
+    }
+
+    wdt_dev = tegra_wdt_from_id(id);
+
+    /*
+     * When written to 1b, enable the counter operation, load the counter
+     * with Period and starts downcounting, resets the expiration count to
+     * 0 and clears all status flags.
+     */
+    val = NV_DRF_NUM(TKE_TOP, WDT0_WDTCMDR, StartCounter, 1UL);
+    tegra_wdt_writel(id, val, TEGRA_WDT_COMMAND_0);
+
+    if (wdt_dev->irq_callback != NULL) {
+        rc = irq_safe_enable(id->irq);
+        if (rc != E_SUCCESS) {
+            goto out;
+        }
+    }
+    if (wdt_dev->fiq_callback != NULL) {
+        rc = irq_safe_enable(id->fiq);
+        if ((rc != E_SUCCESS) && (wdt_dev->irq_callback != NULL)) {
+            ASSERT(irq_safe_disable(id->irq) == E_SUCCESS);
+        }
+    }
+
+  out:
+    return rc;
+}
+
+SECTION_WDT_ERROR_TEXT error_t
+tegra_safe_wdt_stop(const struct tegra_wdt_id *id)
+{
+    error_t                     rc              = E_SUCCESS;
+    const struct tegra_wdt      *wdt_dev;
+    uint32_t                    val;
+
+    if (id == NULL) {
+        rc = E_WDT_ERR_NULL_PTR;
+        goto out;
+    }
+
+    wdt_dev = tegra_wdt_from_id(id);
+
+    /*
+     * Only working if the unlock register (WDTUR{w}) has been
+     * programmed before with the correct pattern. Writing to the command
+     * register always clears the unlock register.
+     * If written DisableCounter to 1b, while WDT counter is enabled and the
+     * unlock register contains the unlock pattern, the watchdog transitions
+     * back to disabled.
+     */
+
+    if (!in_interrupt()) {
+        rtosTaskEnterCritical();
+    }
+
+    tegra_wdt_unlock(id);
+
+    val = NV_DRF_NUM(TKE_TOP, WDT0_WDTCMDR, DisableCounter, 1UL);
+    tegra_wdt_writel(id, val, TEGRA_WDT_COMMAND_0);
+
+    if (wdt_dev->irq_callback != NULL) {
+        rc = irq_safe_disable(id->irq);
+        if (rc != E_SUCCESS) {
+            goto exit;
+        }
+    }
+    if (wdt_dev->fiq_callback != NULL) {
+        rc = irq_safe_disable(id->fiq);
+        if ((rc != E_SUCCESS) && (wdt_dev->irq_callback != NULL)) {
+            ASSERT(irq_safe_enable(id->irq) == E_SUCCESS);
+        }
+    }
+
+exit:
+    if (!in_interrupt()) {
+        rtosTaskExitCritical();
+    }
+
+  out:
+    return rc;
+}
+
+SECTION_WDT_ERROR_TEXT error_t
+tegra_safe_wdt_stop_from_isr(const struct tegra_wdt_id *id)
+{
+    return tegra_safe_wdt_stop(id);
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_WDT_ERROR_TEXT void tegra_safe_wdt_irq(void *data)
+{
+    error_t                     rc;
+    INLINE_RFD(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx");
+    const struct tegra_wdt_id   *id             = data;
+    const struct tegra_wdt      *wdt_dev;
+    uint32_t                    status          = 0;
+
+    ASSERT(id != NULL);
+
+    wdt_dev = tegra_wdt_from_id(id);
+
+    rc = tegra_safe_wdt_read_status(id, &status);
+    ASSERT(rc == E_SUCCESS);
+
+    if (wdt_dev->irq_callback != NULL) {
+        if (wdt_dev->irq_ack_by_callback) {
+            rc = irq_safe_disable(id->irq);
+            ASSERT(rc == E_SUCCESS);
+        } else {
+            tegra_wdt_ack_internal(id);
+        }
+        wdt_dev->irq_callback(status, wdt_dev->irq_data);
+    }
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_WDT_ERROR_TEXT void tegra_safe_wdt_fiq(void *data)
+{
+    error_t                     rc;
+    INLINE_RFD(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx");
+    const struct tegra_wdt_id   *id             = data;
+    const struct tegra_wdt      *wdt_dev;
+    uint32_t                    status          = 0;
+
+    ASSERT(id != NULL);
+
+    wdt_dev = tegra_wdt_from_id(id);
+
+    rc = tegra_safe_wdt_read_status(id, &status);
+    ASSERT(rc == E_SUCCESS);
+
+    if (wdt_dev->fiq_callback != NULL) {
+        if (wdt_dev->fiq_ack_by_callback) {
+            rc = irq_safe_disable(id->fiq);
+            ASSERT(rc == E_SUCCESS);
+        } else {
+            tegra_wdt_ack_internal(id);
+        }
+        wdt_dev->fiq_callback(status, wdt_dev->fiq_data);
+    }
+}
+
+SECTION_WDT_TEXT error_t
+tegra_safe_wdt_read_status(const struct tegra_wdt_id *id,
+                           uint32_t *status)
+{
+    error_t             rc              = E_SUCCESS;
+
+    if (id == NULL) {
+        rc = E_WDT_ERR_NULL_PTR;
+        goto out;
+    }
+
+    *status = tegra_wdt_readl(id, TEGRA_WDT_STATUS_0);
+
+  out:
+    return rc;
+}
+
+SECTION_WDT_TEXT error_t
+tegra_safe_wdt_ack(const struct tegra_wdt_id *id)
+{
+    error_t                     rc              = E_SUCCESS;
+    const struct tegra_wdt      *wdt_dev;
+
+    if (id == NULL) {
+        rc = E_WDT_ERR_NULL_PTR;
+        goto out;
+    }
+
+    wdt_dev = tegra_wdt_from_id(id);
+
+    if (!in_interrupt()) {
+        rtosTaskEnterCritical();
+    }
+
+    tegra_wdt_ack_internal(id);
+
+    if (wdt_dev->irq_ack_by_callback) {
+        rc = irq_safe_enable(id->irq);
+        if (rc != E_SUCCESS) {
+            goto exit;
+        }
+    }
+    if (wdt_dev->fiq_ack_by_callback) {
+        rc = irq_safe_enable(id->fiq);
+        if ((rc != E_SUCCESS) && wdt_dev->irq_ack_by_callback) {
+            ASSERT(irq_safe_disable(id->irq) == E_SUCCESS);
+        }
+    }
+
+exit:
+    if (!in_interrupt()) {
+        rtosTaskExitCritical();
+    }
+
+  out:
+    return rc;
+}
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+SECTION_WDT_INIT_TEXT error_t tegra_safe_wdt_setup(struct tegra_wdt_id *id, const struct tegra_wdt_conf *conf)
+{
+    struct tegra_wdt    *wdt_dev;
+    uint32_t            val;
+    error_t             err = E_SUCCESS;
+
+    if ((id == NULL)
+        || (conf == NULL)) {
+        err = E_WDT_ERR_NULL_PTR;
+        goto out;
+    }
+
+    wdt_dev = fsp_c_wdt_ptr_to_wdt_ptr(tegra_wdt_from_id(id));
+
+    if ((conf->tmrsrc & ~TKE_TOP_WDT0_WDTCR_0_TimerSource_DEFAULT_MASK) != 0U) {
+        err = E_WDT_ERR_TMRSRC_INVALID;
+        goto out;
+    }
+
+    if ((conf->err_threshold & ~TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_DEFAULT_MASK) != 0UL) {
+        err = E_WDT_ERR_THRESHOLD_INVALID;
+        goto out;
+    }
+
+    if (conf->irq_en && (conf->irq_callback == NULL)) {
+        err = E_WDT_ERR_IRQ_CONFIG;
+        goto out;
+    }
+
+    if (conf->fiq_en && (conf->fiq_callback == NULL)) {
+        err = E_WDT_ERR_IRQ_CONFIG;
+        goto out;
+    }
+
+    wdt_dev->irq_ack_by_callback = conf->irq_en && conf->irq_ack_by_callback;
+    wdt_dev->irq_callback = conf->irq_en ? conf->irq_callback : NULL;
+    wdt_dev->irq_data = conf->irq_data;
+    wdt_dev->fiq_ack_by_callback = conf->fiq_en && conf->fiq_ack_by_callback;
+    wdt_dev->fiq_callback = conf->fiq_en ? conf->fiq_callback : NULL;
+    wdt_dev->fiq_data = conf->fiq_data;
+
+    val =
+        NV_DRF_NUM(TKE_TOP, WDT0_WDTCR, TimerSource, conf->tmrsrc) |
+        NV_DRF_NUM(TKE_TOP, WDT0_WDTCR, Period, conf->period) |
+        NV_DRF_NUM(TKE_TOP, WDT0_WDTCR, LocalInterruptEnable, conf->irq_en ? 1UL : 0UL) |
+        NV_DRF_NUM(TKE_TOP, WDT0_WDTCR, LocalFIQEnable, conf->fiq_en ? 1UL : 0UL) |
+        NV_DRF_NUM(TKE_TOP, WDT0_WDTCR, RemoteInterruptEnable, conf->remoteIrq_en ? 1UL : 0UL) |
+        NV_DRF_NUM(TKE_TOP, WDT0_WDTCR, SystemDebugResetEnable, conf->sys_dbg_rst_en ? 1UL : 0UL) |
+        NV_DRF_NUM(TKE_TOP, WDT0_WDTCR, SystemPOResetEnable, conf->sys_por_rst_en ? 1UL : 0UL) |
+        NV_DRF_NUM(TKE_TOP, WDT0_WDTCR, TscReferenceEnable, conf->tsc_ref_en ? 1UL : 0UL) |
+        NV_DRF_NUM(TKE_TOP, WDT0_WDTCR, ErrorThreshold, conf->err_threshold);
+
+    tegra_wdt_writel(id, val, TEGRA_WDT_CONFIG_0);
+
+    /* Explicitly disable windowed operation mode */
+    err = tegra_safe_disable_wdt_windowed_operation(id);
+    if (err != E_SUCCESS) {
+        goto out;
+    }
+
+    if ((val & NV_DRF_NUM(TKE_TOP, WDT0_WDTCR, ChallengeResponseEnable, 1UL)) != 0UL) {
+        wdt_dev->challenge_response = true;
+    } else {
+        wdt_dev->challenge_response = false;
+    }
+
+    if (conf->irq_en) {
+        err = irq_safe_set_handler(id->irq, tegra_safe_wdt_irq, (void *)id);
+        if (err != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+    if (conf->fiq_en) {
+        err = irq_safe_set_handler(id->fiq, tegra_safe_wdt_fiq, (void *)id);
+        if (err != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+out:
+    return err;
+}
+
+SECTION_WDT_TEXT error_t
+tegra_safe_enable_wdt_windowed_operation(const struct tegra_wdt_id *id,
+                                         uint8_t start_level,
+                                         uint8_t start_count)
+{
+    uint32_t val;
+    error_t  err = E_SUCCESS;
+
+    if (id == NULL) {
+        err = E_WDT_ERR_NULL_PTR;
+        goto out;
+    }
+
+    val = NV_DRF_NUM(TKE_TOP, WDT0_WDTFWCR, StartLevel, start_level) |
+          NV_DRF_NUM(TKE_TOP, WDT0_WDTFWCR, StartCount, start_count);
+    tegra_wdt_writel(id, val, TEGRA_WDT_WINDOW_CONFIG_0);
+
+    val = tegra_wdt_readl(id, TEGRA_WDT_CONFIG_0);
+    val |= NV_DRF_NUM(TKE_TOP, WDT0_WDTCR, WindowedOperationEnable, 0x1UL);
+    tegra_wdt_writel(id, val, TEGRA_WDT_CONFIG_0);
+
+out:
+    return err;
+}
+
+SECTION_WDT_TEXT error_t
+tegra_safe_disable_wdt_windowed_operation(const struct tegra_wdt_id *id)
+{
+    uint32_t val;
+    error_t err = E_SUCCESS;
+
+    if (id == NULL) {
+        err = E_WDT_ERR_NULL_PTR;
+        goto out;
+    }
+
+    val = tegra_wdt_readl(id, TEGRA_WDT_CONFIG_0);
+    val &= ~NV_DRF_NUM(TKE_TOP, WDT0_WDTCR, WindowedOperationEnable, 0x1UL);
+    tegra_wdt_writel(id, val, TEGRA_WDT_CONFIG_0);
+
+out:
+    return err;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/include/adcc/adcc-errors.h b/spe-freertos-bsp/fsp/source/include/adcc/adcc-errors.h
new file mode 100644
index 0000000..26c37dc
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/adcc/adcc-errors.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ADCC__ADCC_ERRORS_H
+#define ADCC__ADCC_ERRORS_H
+#define FSP__ADCC__ADCC_ERRORS_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>         // IWYU pragma: export
+#include <misc/macros.h>            // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+
+/**
+ * @file adcc-errors.h
+ * @brief Error codes that are specific to the adcc
+ */
+
+#define E_ADCC_NULL_PTR               MODULE_ERROR(ADCC, 0UL)
+#define E_ADCC_INVALID_PARAM          MODULE_ERROR(ADCC, 1UL)
+#define E_ADCC_CLK_EN                 MODULE_ERROR(ADCC, 2UL)
+#define E_ADCC_CLK_RST                MODULE_ERROR(ADCC, 3UL)
+#define E_ADCC_NO_INIT                MODULE_ERROR(ADCC, 4UL)
+#define E_ADCC_INVALID_CHAN           MODULE_ERROR(ADCC, 5UL)
+#define E_ADCC_CHAN_NOT_ENABLED       MODULE_ERROR(ADCC, 6UL)
+
+#endif  /* ADCC__ADCC_ERRORS_H */
diff --git a/spe-freertos-bsp/fsp/source/include/adcc/adcc-priv.h b/spe-freertos-bsp/fsp/source/include/adcc/adcc-priv.h
new file mode 100644
index 0000000..e0c7121
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/adcc/adcc-priv.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ADCC__ADCC_PRIV_H
+#define ADCC__ADCC_PRIV_H
+#define FSP__ADCC__ADCC_PRIV_H                      1
+
+/**
+ * @file adcc/adcc-tegra-priv.h
+ * @brief Structures that are internal to the ADCC driver
+ */
+
+/* Compiler headers */
+#include <stdbool.h>
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <adcc/adcc.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ADCC__ADCC_H, "Header file missing or invalid.")
+
+/*
+ * Declaration for tera_rst/clk that allows the structs/APIs to take a pointer
+ * to it without actually defining its contents here.
+ */
+struct tegra_rst;
+
+/**
+ * @brief ADCC controller context structure
+ *
+ * Structure that is used by the ADCC driver to manage the ADCC controller
+ * during run time.
+ *
+ * @base_addr   base address of the controller
+ * @rst         controller reset configuration
+ * @clk         controller clock configuration
+ */
+struct adcc_id {
+    uint32_t                base_addr;
+    const struct tegra_rst  *rst;
+};
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/adcc/adcc.h b/spe-freertos-bsp/fsp/source/include/adcc/adcc.h
new file mode 100644
index 0000000..1d4086c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/adcc/adcc.h
@@ -0,0 +1,196 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ADCC__ADCC_H
+#define ADCC__ADCC_H
+#define FSP__ADCC__ADCC_H       1
+
+#define ADCC_MODE_SINGLE_SHOT   1U
+#define ADCC_MODE_CONT_MODE     0U
+
+#define ADCC_CLK_SRC_OSC_UNDIV  0U
+#define ADCC_CLK_SRC_PLLP       1U
+
+/**
+ * @file adcc/adcc-tegra-priv.h
+ * @brief Structures that are internal to the ADCC driver
+ */
+
+/* Compiler headers */
+#include <stdbool.h>
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>
+
+/**
+ * ADCC controllers support 6 channels. Hence,
+ * setting number of ADCC channels as 6.
+ */
+#define ADCC_NCHANS 6U
+
+/*
+ * Declaration for adcc_id that allows the APIs to take a pointer to it
+ * without actually defining its contents here.
+ */
+struct adcc_id;
+
+/**
+ * @brief ADCC channels samples
+ *
+ * Structure that is used by the ADCC driver to fetch the samples from
+ * all the ADCC channels.
+ *
+ * @ch_data          array containing all the channels samples
+ * @enabled_chans    bit mask of the enabled channels
+ */
+struct adcc_data {
+    uint32_t  ch_data[ADCC_NCHANS];
+    uint32_t  enabled_chans;
+};
+
+/**
+ * @brief ADCC configuration
+ *
+ * Structure that stores the configuration details that is used by the
+ * ADCC driver.
+ *
+ * @enabled_chans    bit mask of the enabled channels
+ * @sampling_dur     sampling duration
+ * @avg_window       averaging window duration
+ * @mode             single shot or continuous mode
+ * @clk_src          adcc clock source
+ * @chans_lb_data    adcc channels loop back data
+ */
+struct adcc_conf {
+    uint32_t  enabled_chans;
+    uint32_t  sampling_dur;
+    uint32_t  avg_window;
+    uint32_t  mode;
+    uint32_t  clk_src;
+    uint64_t  chans_lb_data;
+};
+
+/**
+ * @brief Read all ADCC channels samples
+ *
+ * @jama_func_req_id xxxxxxx
+ *
+ * This function fetches the samples read on all ADCC channel.
+ *
+ * @pre the function adcc_init() has been called
+ *
+ * @param[in] id          pointer to the ADCC descriptor instance.
+ * @param[in] data        pointer to store the channels samples read.
+ *
+ * @retval E_SUCCESS        indicates success
+ * @retval E_ADCC_NULL_PTR  invalid id paramter passed
+ * @retval E_ADCC_NO_INIT   adcc is not initialized
+ */
+error_t adcc_read_data(const struct adcc_id *id,
+                       struct adcc_data *data);
+
+/**
+ * @brief Read an ADCC channel's sample
+ *
+ * @jama_func_req_id xxxxxxx
+ *
+ * This function fetches the sample read on an ADCC channel specified.
+ *
+ * @pre the function adcc_init() has been called
+ *
+ * @param[in] id          pointer to the ADCC descriptor instance.
+ * @param[in] chan        channel index in [0, ADCC_NCHANS - 1]
+ * @param[in] data        pointer to store the read channel sample
+ *
+ * @retval E_SUCCESS                indicates success
+ * @retval E_ADCC_NULL_PTR          invalid id paramter passed
+ * @retval E_ADCC_NO_INIT           adcc is not initialized
+ * @retval E_ADCC_INVALID_CHAN      invalid chan id passed
+ * @retval E_ADCC_CHAN_NOT_ENABLED  invalid chan id passed
+ */
+error_t adcc_read_chan_data(const struct adcc_id *id,
+                            uint32_t chan,
+                            uint32_t *data);
+
+/**
+ * @brief Stop the ADCC channel scan
+ *
+ * @jama_func_req_id xxxxxxx
+ *
+ * This function disables the ADCC channel scanning.
+ *
+ * @pre the function adcc_init() has been called
+ *
+ * @param[in] id          pointer to the ADCC descriptor instance.
+ *
+ * @retval E_SUCCESS        indicates success
+ * @retval E_ADCC_NULL_PTR  invalid id paramter passed
+ * @retval E_ADCC_NO_INIT   adcc is not initialized
+ */
+error_t adcc_stop_scan(const struct adcc_id *id);
+
+/**
+ * @brief Start the ADCC channel scan
+ *
+ * @jama_func_req_id xxxxxxx
+ *
+ * This function enables the ADCC channel scanning.
+ *
+ * @pre the function adcc_init() has been called
+ *
+ * @param[in] id          pointer to the ADCC descriptor instance.
+ *
+ * @retval E_SUCCESS        indicates success
+ * @retval E_ADCC_NULL_PTR  invalid id paramter passed
+ * @retval E_ADCC_NO_INIT   adcc is not initialized
+ */
+error_t adcc_start_scan(const struct adcc_id *id);
+
+/**
+ * @brief Initialize the ADCC context
+ *
+ * @jama_func_req_id xxxxxxx
+ *
+ * This function initializes the ADCC context for an instance.
+ *
+ * @param[in] id          pointer to the ADCC descriptor instance.
+ * @param[conf]           adcc configuration.
+ *
+ * @retval E_SUCCESS        indicates success
+ * @retval E_ADCC_NULL_PTR  invalid paramter passed
+ */
+error_t adcc_init(const struct adcc_id *id,
+                  const struct adcc_conf *conf);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/adcc/sections-adcc.h b/spe-freertos-bsp/fsp/source/include/adcc/sections-adcc.h
new file mode 100644
index 0000000..207773d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/adcc/sections-adcc.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ADCC__SECTIONS_ADCC_H
+#define ADCC__SECTIONS_ADCC_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_ADCC_DATA           SECTION_BUILDER(adcc,                    data)
+#define SECTION_NAME_ADCC_RODATA         SECTION_BUILDER(adcc,                    rodata)
+#define SECTION_NAME_ADCC_TEXT           SECTION_BUILDER(adcc,                    text)
+#define SECTION_NAME_ADCC_INIT_DATA      SECTION_BUILDER(init.adcc,               data)
+#define SECTION_NAME_ADCC_INIT_TEXT      SECTION_BUILDER(init.adcc,               text)
+
+#define SECTION_STR_ADCC_TEXT            STR(SECTION_NAME_ADCC_TEXT)
+#define SECTION_STR_ADCC_RODATA          STR(SECTION_NAME_ADCC_RODATA)
+#define SECTION_STR_ADCC_DATA            STR(SECTION_NAME_ADCC_DATA)
+#define SECTION_STR_ADCC_INIT_TEXT       STR(SECTION_NAME_ADCC_INIT_TEXT)
+#define SECTION_STR_ADCC_INIT_DATA       STR(SECTION_NAME_ADCC_INIT_DATA)
+
+#define SECTION_ADCC_TEXT                SECTION(SECTION_STR_ADCC_TEXT)
+#define SECTION_ADCC_RODATA              SECTION(SECTION_STR_ADCC_RODATA)
+#define SECTION_ADCC_DATA                SECTION(SECTION_STR_ADCC_DATA)
+#define SECTION_ADCC_INIT_TEXT           SECTION(SECTION_STR_ADCC_INIT_TEXT)
+#define SECTION_ADCC_INIT_DATA           SECTION(SECTION_STR_ADCC_INIT_DATA)
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/aodmic/aodmic-errors.h b/spe-freertos-bsp/fsp/source/include/aodmic/aodmic-errors.h
new file mode 100644
index 0000000..a140cdd
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/aodmic/aodmic-errors.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef AODMIC__AODMIC_ERRORS_H_
+#define AODMIC__AODMIC_ERRORS_H_
+#define FSP__AODMIC__AODMIC_ERRORS_H                    1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for END_RFD_BLOCK, START_RFD_BLOCK
+#include <base/module-id.h>     // IWYU pragma: export
+                                // IWYU pragma: no_include "base/module-id.h"
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx")
+/* Error codes */
+#define E_AODMIC_CONFIGURATION_NA       MODULE_ERROR(AODMIC, 0x01UL)
+#define E_AODMIC_INVALID_SAMPLE_RATE    MODULE_ERROR(AODMIC, 0x02UL)
+#define E_AODMIC_CLK_RATE_ERROR         MODULE_ERROR(AODMIC, 0x03UL)
+#define E_AODMIC_INVALID_CHANNELS       MODULE_ERROR(AODMIC, 0x04UL)
+#define E_AODMIC_INVALID_SAMPLE_WIDTH   MODULE_ERROR(AODMIC, 0x05UL)
+#define E_AODMIC_INVALID_PERIOD         MODULE_ERROR(AODMIC, 0x06UL)
+#define E_AODMIC_MEM_ALLOC_FAILURE      MODULE_ERROR(AODMIC, 0x07UL)
+#define E_AODMIC_SEM_CREATE_FAILURE     MODULE_ERROR(AODMIC, 0x08UL)
+#define E_AODMIC_NOT_INITIALIZED        MODULE_ERROR(AODMIC, 0x09UL)
+#define E_AODMIC_BUF_INVALID            MODULE_ERROR(AODMIC, 0x0AUL)
+#define E_AODMIC_READ_TIMEOUT           MODULE_ERROR(AODMIC, 0x0BUL)
+#define E_AODMIC_NULL_POINTER           MODULE_ERROR(AODMIC, 0x0CUL)
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/aodmic/sections-aodmic.h b/spe-freertos-bsp/fsp/source/include/aodmic/sections-aodmic.h
new file mode 100644
index 0000000..a0dc8a4
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/aodmic/sections-aodmic.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef AODMIC__SECTIONS_AODMIC_H
+#define AODMIC__SECTIONS_AODMIC_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_AODMIC_DATA        SECTION_BUILDER(aodmic,                 data)
+#define SECTION_NAME_AODMIC_RODATA      SECTION_BUILDER(aodmic,                 rodata)
+#define SECTION_NAME_AODMIC_TEXT        SECTION_BUILDER(aodmic,                 text)
+#define SECTION_NAME_AODMIC_INIT_DATA   SECTION_BUILDER(init.aodmic,            data)
+#define SECTION_NAME_AODMIC_INIT_TEXT   SECTION_BUILDER(init.aodmic,            text)
+
+#define SECTION_STR_AODMIC_TEXT         STR(SECTION_NAME_AODMIC_TEXT)
+#define SECTION_STR_AODMIC_RODATA       STR(SECTION_NAME_AODMIC_RODATA)
+#define SECTION_STR_AODMIC_DATA         STR(SECTION_NAME_AODMIC_DATA)
+#define SECTION_STR_AODMIC_INIT_TEXT    STR(SECTION_NAME_AODMIC_INIT_TEXT)
+#define SECTION_STR_AODMIC_INIT_DATA    STR(SECTION_NAME_AODMIC_INIT_DATA)
+
+#define SECTION_AODMIC_TEXT             SECTION(SECTION_STR_AODMIC_TEXT)
+#define SECTION_AODMIC_RODATA           SECTION(SECTION_STR_AODMIC_RODATA)
+#define SECTION_AODMIC_DATA             SECTION(SECTION_STR_AODMIC_DATA)
+#define SECTION_AODMIC_INIT_TEXT        SECTION(SECTION_STR_AODMIC_INIT_TEXT)
+#define SECTION_AODMIC_INIT_DATA        SECTION(SECTION_STR_AODMIC_INIT_DATA)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/aodmic/tegra-aodmic-priv.h b/spe-freertos-bsp/fsp/source/include/aodmic/tegra-aodmic-priv.h
new file mode 100644
index 0000000..8a377ba
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/aodmic/tegra-aodmic-priv.h
@@ -0,0 +1,121 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef AODMIC__TEGRA_AODMIC_PRIV_H_
+#define AODMIC__TEGRA_AODMIC_PRIV_H_
+#define FSP__AODMIC__TEGRA_AODMIC_PRIV_H                1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <osa/rtos-queue.h>
+#include <gpcdma/gpcdma.h>
+#include <misc/macros.h>                // for END_RFD_BLOCK, START_RFD_BLOCK
+
+/* Module-specific FSP headers */
+#include <aodmic/tegra-aodmic.h>        // for AODMIC_MAX_NUM_PERIODS
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSA__RTOS_QUEUE_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPCDMA__GPCDMA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/* Internal hardcodings of AODMIC */
+#define TEGRA_AODMIC_WORD_SIZE        4u   /* 4 bytes  */
+#define TEGRA_AODMIC_FIFO_SIZE        32u  /* 32 words */
+
+/* AODMIC interrupt threshold */
+#define TEGRA_AODMIC_FIFO_THRESHOLD   (TEGRA_AODMIC_FIFO_SIZE / 2u)
+
+#define TEGRA_AODMIC_MIN_ALLOWED_PERIODS (2UL)
+
+struct tegra_aodmic_id {
+    uint32_t base_addr;
+    const struct aodmic_port_clk_rst *aodmic_hw_handle;
+    uint32_t irq;
+};
+
+struct tegra_aodmic_ctlr {
+    const struct tegra_aodmic_id id;
+
+    /* PCM configuration */
+    uint32_t sample_rate;  /* In Hz */
+    uint32_t num_channels; /* Channel count */
+    uint32_t samp_bytes;   /* Bytes per sample */
+
+    /* GPCDMA configuration */
+    struct gpcdma_id *dma_id;   /* DMA instance ID */
+    uint32_t dma_chan_num; /* DMA channel no. */
+    struct gpcdma_xfer dma_xfer;     /* DMA transfer parameters */
+
+    /* Driver data buffer */
+    uint8_t *data;         /* Data pointer (of num_periods length) */
+    uint32_t period_bytes;  /* Size of each period in data buffer */
+    uint32_t num_periods;   /* No. of periods */
+
+    /* Buffer control */
+    rtosSemaphoreBuffer rtosSemaphore_object; /* statically allocated object */
+    rtosSemaphoreHandle rtosSemaphore_free_buf; /* Count of free periods */
+    uint8_t rtosQueue_object_mem[            /* queue object and queue data */
+                rtosQueueSize(AODMIC_MAX_NUM_PERIODS, sizeof(uint64_t))];
+    rtosQueueHandle rtosQueue_filled_buf;   /* Queue of filled periods */
+    rtosTick max_read_timeout;    /* Timeout at queue receive */
+    uint32_t free_pos;      /* Next available free period (for writing) */
+    uint8_t *read_ptr;     /* Location of period to read */
+    uint32_t bytes_to_read; /* Bytes available to read */
+
+    /* Control information */
+    bool     init_done;
+    bool     dma_running;
+    bool     reset;
+    uint32_t xrun_cnt;
+
+    /* Error Logging */
+    uint32_t overflow_count;
+};
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/aodmic/tegra-aodmic.h b/spe-freertos-bsp/fsp/source/include/aodmic/tegra-aodmic.h
new file mode 100644
index 0000000..068ed4d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/aodmic/tegra-aodmic.h
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2015-2021 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef AODMIC__TEGRA_AODMIC_H
+#define AODMIC__TEGRA_AODMIC_H
+#define FSP__AODMIC__TEGRA_AODMIC_H                     1
+
+/* Compiler headers */
+#include <stdint.h>
+                                        // IWYU pragma: no_include <errno.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>        // for MODULE_ID_AODMIC, E_SUCCESS
+#include <misc/macros.h>                // for END_RFD_BLOCK, START_RFD_BLOCK
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+
+// IWYU pragma: no_forward_declare tegra_aodmic_ctlr
+struct tegra_aodmic_ctlr;
+
+/* Supported sample rates */
+enum tegra_aodmic_sample_rate {
+    TEGRA_AODMIC_RATE_8KHZ  =  8000,
+    TEGRA_AODMIC_RATE_16KHZ = 16000,
+    TEGRA_AODMIC_RATE_44KHZ = 44100,
+    TEGRA_AODMIC_RATE_48KHZ = 48000,
+    TEGRA_AODMIC_NUM_RATES
+};
+
+/* Supported channel configurations */
+enum tegra_aodmic_channel_config {
+    TEGRA_AODMIC_CHANNEL_MONO_LEFT,
+    TEGRA_AODMIC_CHANNEL_MONO_RIGHT,
+    TEGRA_AODMIC_CHANNEL_STEREO,
+    TEGRA_AODMIC_NUM_CHANNEL_CONFIGS
+};
+
+/*
+ * Supported sample widths
+ *  AODMIC provides samples at 24 bit sample width,
+ *  which will be scaled as per below configuration
+ */
+enum tegra_aodmic_sample_width {
+    TEGRA_AODMIC_BITS_PER_SAMPLE_16 = 2,
+    TEGRA_AODMIC_BITS_PER_SAMPLE_32 = 4,
+};
+
+/*
+ * This relates to the Queue size in the driver. It is statically
+ * allocated for the largest number supported, so this number
+ * should only be raised in rare cases where quadruple data buffering
+ * is deemed insufficient.  Double buffering is the typical usage.
+ */
+#define AODMIC_MAX_NUM_PERIODS (4)
+
+/*
+ * @brief AODMIC config structure
+ * PCM configuration:
+ * @sample_rate         As per tegra_aodmic_sample_rate
+ * @channel_config      As per tegra_aodmic_channel_config
+ * @sample_width        As per tegra_aodmic_sample_width
+ * DMA configuration:
+ * @period_size         DMA interrupt interval (in sample frames),
+ *                      must be multiple of 16
+ * @num_periods         2 <= num_periods <= AODMIC_MAX_NUM_PERIODS
+ * DMA instance:
+ * @gpcdma_id           GPCDMA instance handle
+ * @dma_chan_num        GPCDMA channel no. to use (0 - 7)
+ *
+ * GPCDMA Data Buffers
+ * @gpcdma_buf          Pointer to data buffer that will be
+ *                      used exclusively by the driver, i.e. application should
+ *                      create but never directly access this buffer.
+ * @gpcdma_buf_size     This is the size of the buffer created. It must be at
+ *                      least period_size*num_periods*4*num_channels where
+ *                      num_channels=1 for mono channel configurations and
+ *                      num_channels=2 for stereo channel configutations. If
+ *                      this condition is not met the driver will return an
+ *                      error code of E_AODMIC_MEM_ALLOC_FAILURE.
+ */
+struct tegra_aodmic_config {
+    /* PCM configuration */
+    enum tegra_aodmic_sample_rate    sample_rate;
+    enum tegra_aodmic_channel_config channel_config;
+    enum tegra_aodmic_sample_width   sample_width;
+
+    /* DMA configuration */
+    uint32_t                         period_size;
+    uint32_t                         num_periods;
+
+    /* DMA instance */
+    struct gpcdma_id                *dma_id;
+    uint32_t                         dma_chan_num;
+
+    /* GPCDMA Data Buffers */
+    uint8_t                         *gpcdma_buf;
+    uint32_t                         gpcdma_buf_size;
+};
+
+/**
+ * @brief open and initialize AODMIC instance
+ *
+ * @pre gpcdma_init() has been called
+ *
+ * @param[in] ctlr:        AODMIC controller instance
+ * @param[in] config:      Configuration structure
+ *
+ * @retval E_SUCCESS                     indicates success
+ * @retval E_AODMIC_NULL_POINTER         indicates NULL pointer was passed
+ * @retval E_AODMIC_INVALID_SAMPLE_RATE  invalid sample rate
+ * @retval E_AODMIC_INVALID_CHANNELS     invalid channel configuration
+ * @retval E_AODMIC_INVALID_SAMPLE_WIDTH invalid sample width
+ * @retval E_AODMIC_INVALID_PERIOD       invalid period
+ * @retval E_AODMIC_MEM_ALLOC_FAILURE    gpcdma_buf_size too small
+ * @retval E_AODMIC_SEM_CREATE_FAILURE   failed rtos object creation
+ */
+error_t
+tegra_aodmic_open(struct tegra_aodmic_ctlr *ctlr,
+                  const struct tegra_aodmic_config *config);
+
+/**
+ * @brief Read captured samples
+ *
+ * @pre the function tegra_aodmic_open() has been called
+ *
+ * @param[in] ctlr:        AODMIC controller instance
+ * @param[in] count:       number of bytes to capture
+ *
+ * @retval E_SUCCESS                  success
+ * @retval E_AODMIC_NULL_POINTER      detected a null pointer
+ * @retval E_AODMIC_CONFIGURATION_NA  count of 0 not allowed
+ * @retval E_AODMIC_NOT_INITIALIZED   tegra_aodmic_open() not called prior
+ * @retval E_AODMIC_BUF_INVALID       null data pointer
+ * @retval E_AODMIC_READ_TIMEOUT      timeout waiting for queue
+ */
+error_t
+tegra_aodmic_read(struct tegra_aodmic_ctlr *ctlr,
+                  void *data,
+                  uint32_t count);
+
+/**
+ * @brief Close AODMIC instance
+ *
+ * @pre none
+ *
+ * @param[in] ctlr:                 AODMIC controller instance
+ *
+ * @retval E_SUCCESS                indicates success
+ * @retval E_AODMIC_NULL_POINTER    detected a null pointer
+ */
+error_t
+tegra_aodmic_close(struct tegra_aodmic_ctlr *ctlr);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/asm/asm.h b/spe-freertos-bsp/fsp/source/include/asm/asm.h
new file mode 100644
index 0000000..cccbdf9
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/asm/asm.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2018-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ *
+ * This file is derived from LittleKernel include/asm.h provided under the
+ * following license terms:
+ *
+ * Copyright (c) 2008-2013 Travis Geiselbrecht
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files
+ * (the "Software"), to deal in the Software without restriction,
+ * including without limitation the rights to use, copy, modify, merge,
+ * publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so,
+ * subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
+ * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
+ * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef ASM__ASM_H
+#define ASM__ASM_H
+#define FSP__ASM__ASM_H                                 1
+
+/*
+ * @brief Macros to declare the start of a global function, local function
+ * and end of a local or global function.
+ */
+#define FUNCTION(x) .global x; .type x, STT_FUNC; x:
+#define LOCAL_FUNCTION(x) .type x, STT_FUNC; x:
+#define END_FUNCTION(x) .L##x##_end0 : .size x, (.L##x##_end0 - x)
+
+/*
+ * @brief Macros to declare the start of global data and local data  in asm
+ */
+#define DATA(x) .global x; .type x, STT_OBJECT; x:
+#define LOCAL_DATA(x) .type x, STT_OBJECT; x:
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/ast/ast-errors.h b/spe-freertos-bsp/fsp/source/include/ast/ast-errors.h
new file mode 100644
index 0000000..00d41aa
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/ast/ast-errors.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef AST__AST_ERRORS_H
+#define AST__AST_ERRORS_H
+#define FSP__AST__AST_ERRORS_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "base/module-id.h"
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @brief Macro definitions for errors from AST layer
+ *
+ * @macro-title AST error codes
+ *
+ * @E_AST_INVALID_VMINDEX             Error value returned for invalid VM index
+ * @E_AST_INVALID_AST_BASE            Error value returned for invalid or NULL
+ *                                    AST base addresses
+ * @E_AST_GLOBALLY_LOCKED             Error value returned if request could not
+ *                                    be processed because AST is globally locked.
+ * @E_AST_REGION_DISABLED             Error value returned if request could not
+ *                                    be processed because AST region is disabled
+ * @E_AST_REGION_STREAMID_DISABLED    Error value returned if request could not
+ *                                    be processed because AST region streamID is
+ *                                    disabled
+ * E_AST_INVALID_INPUT_PARAMETERS     Error value returned for invalid or NULL
+ *                                    input parameters
+ * E_AST_INVALID_PHY_REGION_REQUEST   Error value returned when the request is
+ *                                    not applicable to regions mapped with
+ *                                    physical streamID
+ * E_AST_NOT_SUPPORTED                Error value returned when the function
+ *                                    is not supported on a particular SoC
+ */
+#define E_AST_INVALID_VMINDEX            MODULE_ERROR(AST,1UL)
+#define E_AST_INVALID_AST_BASE           MODULE_ERROR(AST,2UL)
+#define E_AST_GLOBALLY_LOCKED            MODULE_ERROR(AST,3UL)
+#define E_AST_REGION_DISABLED            MODULE_ERROR(AST,4UL)
+#define E_AST_REGION_STREAMID_DISABLED   MODULE_ERROR(AST,5UL)
+#define E_AST_INVALID_INPUT_PARAMETERS   MODULE_ERROR(AST,6UL)
+#define E_AST_INVALID_PHY_REGION_REQUEST MODULE_ERROR(AST,7UL)
+#define E_AST_NOT_SUPPORTED              MODULE_ERROR(AST,8UL)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/ast/sections-ast.h b/spe-freertos-bsp/fsp/source/include/ast/sections-ast.h
new file mode 100644
index 0000000..f441227
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/ast/sections-ast.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef AST__SECTIONS_AST_H
+#define AST__SECTIONS_AST_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME            TYPE)   */
+#define SECTION_NAME_AST_DATA           SECTION_BUILDER(ast,            data)
+#define SECTION_NAME_AST_RODATA         SECTION_BUILDER(ast,            rodata)
+#define SECTION_NAME_AST_TEXT           SECTION_BUILDER(ast,            text)
+#define SECTION_NAME_AST_INIT_DATA      SECTION_BUILDER(init.ast,       data)
+#define SECTION_NAME_AST_INIT_TEXT      SECTION_BUILDER(init.ast,       text)
+
+#define SECTION_STR_AST_TEXT            STR(SECTION_NAME_AST_TEXT)
+#define SECTION_STR_AST_RODATA          STR(SECTION_NAME_AST_RODATA)
+#define SECTION_STR_AST_DATA            STR(SECTION_NAME_AST_DATA)
+#define SECTION_STR_AST_INIT_TEXT       STR(SECTION_NAME_AST_INIT_TEXT)
+#define SECTION_STR_AST_INIT_DATA       STR(SECTION_NAME_AST_INIT_DATA)
+
+#define SECTION_AST_TEXT                SECTION(SECTION_STR_AST_TEXT)
+#define SECTION_AST_RODATA              SECTION(SECTION_STR_AST_RODATA)
+#define SECTION_AST_DATA                SECTION(SECTION_STR_AST_DATA)
+#define SECTION_AST_INIT_TEXT           SECTION(SECTION_STR_AST_INIT_TEXT)
+#define SECTION_AST_INIT_DATA           SECTION(SECTION_STR_AST_INIT_DATA)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
+
diff --git a/spe-freertos-bsp/fsp/source/include/ast/tegra-ast.h b/spe-freertos-bsp/fsp/source/include/ast/tegra-ast.h
new file mode 100644
index 0000000..afd52a1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/ast/tegra-ast.h
@@ -0,0 +1,637 @@
+/*
+ * Copyright (c) 2019-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef AST__TEGRA_AST_H
+#define AST__TEGRA_AST_H
+#define FSP__AST__TEGRA_AST_H                           1
+
+/* Compiler headers */
+#include <stdint.h>               // for uint8_t, uint64_t, uint32_t
+#include <stdbool.h>              // for bool
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>       // for CT_ASSERT
+#include <soc-common/hw-const.h>  // for MK_U32_CONST
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <error/common-errors.h>  // for error_t
+
+/* Module-specific FSP headers */
+#include <soc-common/ast-defs.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__AST_DEFS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @brief AST instance macro definitions
+ *
+ * @macro-title AST instance mask macros
+ *
+ * @MK_U32_CONST             Defines a u32 constant value
+ * @MAX_AST_CONTROLLER       Defines maximum number of AST instances per cluster.
+ * @AST_INSTANCE_R5          Mask to configure R5 instance.
+ * @AST_INSTANCE_DMA         Mask to configure DMA instance.
+ * @AST_INSTANCE_R5_AND_DMA  Mask to configure both R5 and DMA instances.
+ * @MAX_REGION_INDEX         Max value of valid region index
+ */
+#define MAX_AST_CONTROLLER      MK_U32_CONST(2)
+#define AST_INSTANCE_0          MK_U32_CONST(0)
+#define AST_INSTANCE_1          MK_U32_CONST(1)
+#define AST_INSTANCE_R5         (uint8_t)(1U << AST_INSTANCE_0)
+#define AST_INSTANCE_DMA        (uint8_t)(1U << AST_INSTANCE_1)
+#define AST_INSTANCE_R5_AND_DMA (AST_INSTANCE_R5 | AST_INSTANCE_DMA)
+#define MAX_REGION_INDEX        (AST_NUM_REGIONS - 1U)
+
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+const extern uint32_t ast_tegra_id[MAX_AST_CONTROLLER];
+
+typedef uint64_t iova;
+
+#define IOVA_NULL          ((iova)0U)
+
+/**
+ * @brief Structure defining the AST region map
+ *
+ * @master_base   Base address of the translated region in the system address
+ *                space.
+ * @slave_base    Base address of the translated region in the local address
+ *                space
+ * @size          Size of the translated region. Size should be defined as a
+ *                power of 2 multiple of the align address and less than the
+ *                size of the private address space
+ * @streamid      StreamID used with the translated region. StreamID value for a
+ *                VM is assigned by the hypervisor. This is don't care value for
+ *                regions mapped with physical streamID.
+ * @is_phy_region Indicator if the requested region is mapped using physical
+ *                streamID
+ * @vmindex       VMIndex used by the region
+ * @is_enabled    Indicated if the region is enabled
+ */
+struct tegra_ast_region_map {
+        iova      master_base;
+        uint64_t  slave_base;
+        uint64_t  size;
+        uint8_t   stream_id;
+        bool      is_phy_region;
+        uint8_t   vmindex;
+        bool      is_enabled;
+};
+
+/**
+ * @brief Enable an AST region for address translation
+ * This API should be used to enable regions mapped with virtual
+ * streamID.
+ *
+ * @param[in] region        Region number [0 - MAX_REGION_INDEX]
+ * @param[in] stream_id     StreamID used with region as assigned by
+ *                          the hypervisor.
+ * @param[in] master        Base address in SoC address space
+ * @param[in] slave         Base address in private address space
+ * @param[in] size          Size of the region. Should be less than size
+ *                          of the private address space
+ * @param[in] instance_mask AST instance mask [AST_INSTANCE_R5,
+ *                          AST_INSTANCE_DMA, AST_INSTANCE_R5_AND_DMA]
+ *
+ * @pre
+ * - Region size must be programmed as power of 2 multiple of the align
+ *   address.
+ * - Regions may not overlap.
+ * - Master and slave base addresses must be aligned to the region size.
+ *
+ * @func_req_id 10551222
+ *
+ * @retval 0                                For success
+ * @retval E_AST_INVALID_VMINDEX            If streamID could not be set
+ * @retval E_AST_INVALID_INPUT_PARAMETERS   For invalid region and instance_mask
+ */
+error_t tegra_ast_enable_region(uint8_t region, uint8_t stream_id,
+                                iova master, uint64_t slave,
+                                uint64_t size, uint8_t instance_mask);
+
+/**
+ * @brief Enable an AST region for address translation
+ * This API should be used to enable regions mapped with virtual
+ * streamID.
+ *
+ * @param[in] region        Region number [0 - MAX_REGION_INDEX]
+ * @param[in] stream_id     StreamID used with region as assigned by
+ *                          the hypervisor.
+ * @param[in] master        Base address in SoC address space
+ * @param[in] slave         Base address in private address space
+ * @param[in] size          Size of the region. Should be less than size
+ *                          of the private address space
+ * @param[in] base          base address of the AST instance
+ *
+ * @pre
+ * - Region size must be programmed as power of 2 multiple of the align
+ *   address.
+ * - Regions may not overlap.
+ * - Master and slave base addresses must be aligned to the region size.
+ *
+ * @func_req_id 10551222
+ *
+ * @retval 0                                For success
+ * @retval E_AST_INVALID_VMINDEX            If streamID could not be set
+ * @retval E_AST_INVALID_INPUT_PARAMETERS   For invalid region and instance_mask
+ */
+error_t tegra_ast_addr_enable_region(uint8_t region, uint8_t stream_id,
+                                     iova master, uint64_t slave,
+                                     uint64_t size, uint32_t base);
+
+/**
+ * @brief Disable an AST region.
+ *
+ * Disables an AST region.
+ *
+ * @func_req_id 10551345
+ *
+ * @param[in] region         Region number [0 - MAX_REGION_INDEX]
+ * @param[in] instance_mask  AST instance mask [AST_INSTANCE_R5,
+ *                           AST_INSTANCE_DMA, AST_INSTANCE_R5_AND_DMA]
+ *
+ * @retval 0                                For success
+ * @retval E_AST_INVALID_INPUT_PARAMETERS   For invalid region and instance_mask
+ */
+error_t tegra_ast_disable_region(uint8_t region, uint8_t instance_mask);
+
+/**
+ * @brief Disable an AST region.
+ *
+ * Disables an AST region.
+ *
+ * @func_req_id 10551345
+ *
+ * @param[in] region         Region number [0 - MAX_REGION_INDEX]
+ * @param[in] base           base address of the AST instance
+ *
+ * @retval 0                                For success
+ * @retval E_AST_INVALID_INPUT_PARAMETERS   For invalid region and instance_mask
+ */
+error_t tegra_ast_addr_disable_region(uint8_t region, uint32_t base);
+
+/**
+ * @brief Disable default AST region.
+ *
+ * Disables the default AST region.
+ *
+ * @func_req_id 10551345
+ *
+ * @param[in] base           base address of the AST instance
+ *
+ * @retval 0                                For success
+ * @retval E_AST_NOT_SUPPORTED              For SoCs where default AST region
+ *                                          is not supported
+ * @retval E_AST_INVALID_INPUT_PARAMETERS   For invalid region and instance_mask
+ */
+error_t tegra_ast_addr_disable_default_region(uint32_t base);
+
+/**
+ * @brief Get mapping for an AST region.
+ *
+ * @param[in]  region        Region number [0 - MAX_REGION_INDEX]
+ * @param[out] region_map    Pointer to tegra_ast_region_map structure to store
+ *                           region map
+ * @param[in]  instance_mask AST instance mask [AST_INSTANCE_R5,
+ *                                              AST_INSTANCE_DMA]
+ *
+ * @func_req_id 10551651
+ *
+ * @retval 0                                For success
+ * @retval E_AST_REGION_DISABLED            If input AST region is disabled
+ * @retval E_AST_INVALID_INPUT_PARAMETERS   For Null input region_map pointer
+ * @retval E_AST_REGION_STREAMID_DISABLED   If region streamid is disabled
+ */
+error_t tegra_ast_get_region_mapping(uint8_t region,
+                                     struct tegra_ast_region_map *return_region_map,
+                                     uint8_t instance_mask);
+
+/**
+ * @brief Get mapping for an AST region.
+ *
+ * @param[in]  region        Region number [0 - MAX_REGION_INDEX]
+ * @param[in]  base          base address of the AST instance
+ * @param[out] region_map    Pointer to tegra_ast_region_map structure to store
+ *                           region map
+ *
+ * @func_req_id 10551651
+ *
+ * @retval 0                                For success
+ * @retval E_AST_REGION_DISABLED            If input AST region is disabled
+ * @retval E_AST_INVALID_INPUT_PARAMETERS   For Null input region_map pointer
+ * @retval E_AST_REGION_STREAMID_DISABLED   If region streamid is disabled
+ */
+error_t tegra_ast_addr_get_region_mapping(uint8_t region,
+                                          struct tegra_ast_region_map *return_region_map,
+                                          uint32_t base);
+
+/**
+ * @brief Get the StreamID used with an AST region.
+ *
+ * @param[in] region        Region number [0 - MAX_REGION_INDEX]
+ * @param[out] streamID     Variable to capture stream ID
+ * @param[in] instance_mask AST instance mask [AST_INSTANCE_R5,
+ *                                             AST_INSTANCE_DMA]
+ *
+ * @func_req_id 10551687
+ *
+ * @retval 0                                For success
+ * @retval E_AST_REGION_DISABLED            If input AST region is disabled
+ * @retval E_AST_REGION_STREAMID_DISABLED   If region streamid is disabled
+ * @retval E_AST_INVALID_INPUT_PARAMETERS   For Null input region_map pointer
+ * @retval E_AST_INVALID_PHY_REGION_REQUEST Request not applicable as the region
+ *                                          is mapped with physical streamID
+ */
+error_t tegra_ast_get_region_stream_id(uint8_t region, uint8_t *streamID,
+                                       uint8_t instance_mask);
+
+/**
+ * @brief Get the StreamID used with an AST region.
+ *
+ * @param[in] region        Region number [0 - MAX_REGION_INDEX]
+ * @param[in] base          base address of the AST instance to be used
+ * @param[out] streamID     Variable to capture stream ID
+ *
+ * @func_req_id 10551687
+ *
+ * @retval 0                                For success
+ * @retval E_AST_REGION_DISABLED            If input AST region is disabled
+ * @retval E_AST_REGION_STREAMID_DISABLED   If region streamid is disabled
+ * @retval E_AST_INVALID_INPUT_PARAMETERS   For Null input region_map pointer
+ * @retval E_AST_INVALID_PHY_REGION_REQUEST Request not applicable as the region
+ *                                          is mapped with physical streamID
+ */
+error_t tegra_ast_addr_get_region_stream_id(uint8_t region, uint8_t *streamID,
+                                            uint32_t base);
+
+/**
+ * @brief Add and enable a StreamID.
+ *
+ * @param[in] stream_id     StreamID to add. StreamID for a VM is specified by
+ *                          hypervisor
+ * @param[in] instance_mask AST instance mask [AST_INSTANCE_R5,
+ *                          AST_INSTANCE_DMA, AST_INSTANCE_R5_AND_DMA]
+ *
+ * @func_req_id 10551702
+ *
+ * @retval 0                        For success
+ * @retval E_AST_INVALID_VMINDEX    If streamID could not be set
+ */
+error_t tegra_ast_add_streamid(uint8_t stream_id, uint8_t instance_mask);
+
+/**
+ * @brief Add and enable a StreamID.
+ *
+ * @param[in] stream_id     StreamID to add. StreamID for a VM is specified by
+ *                          hypervisor
+ * @param[in] base          base address of the AST instance to be used
+ *
+ * @func_req_id 10551702
+ *
+ * @retval 0                        For success
+ * @retval E_AST_INVALID_VMINDEX    If streamID could not be set
+ */
+error_t tegra_ast_addr_add_streamid(uint8_t stream_id, uint32_t base);
+
+/**
+ * @brief Check if AST is globally locked.
+ *
+ * It is not possible to change the Physical StreamID or define new
+ * regions with Physical StreamID if AST is globally locked.
+ *
+ * @func_req_id 10604979
+ *
+ * @retval true  if AST is globally locked
+ * @retval false if AST is not globally locked
+ */
+bool tegra_ast_is_global_locked(void);
+
+/**
+ * @brief Map pointer to IOVA in ast region.
+ *
+ * Returns IOVA address for pointer in the slave address space
+ *
+ * @param[in] map     AST region mapping
+ * @param[in] pointer Input pointer in the slave address space
+ *
+ * @func_req_id 10683207
+ *
+ * @retval IOVA_address If input slave address is valid and lies with the
+ *                      AST region map
+ * @retval IOVA_NULL    Otherwise
+ */
+iova tegra_ast_map_pointer_to_iova(const struct tegra_ast_region_map *map,
+                                   const void *pointer);
+
+/**
+ * @brief Map IOVA to local pointer value in ast region.
+ *
+ * Returns pointer value in local address space corresponding to the input IOVA
+ *
+ * @param[in] map  AST region mapping
+ * @param[in] iova 40-bit valid I/O virtual address
+ *
+ * @func_req_id 10684041
+ *
+ * @retval Slave_address_pointer_value  If input IOVA is valid and lies withing the
+ *                                      AST region map
+ * @retval 0                            Otherwise
+ */
+uint64_t tegra_ast_get_local_pointer_value(const struct tegra_ast_region_map *map,
+                                           const iova iova_addr);
+
+/**
+ * @brief Map slave address to IOVA in ast region.
+ *
+ * Returns IOVA corresponding to the local address in slave address space.
+ *
+ * @param[in] map   AST region mapping
+ * @param[in] slave Input slave address
+ *
+ * @func_req_id 10683153
+ *
+ * @retval IOVA      If input slave address is valid and lies within the AST
+ *                   region map
+ * @retval IOVA_NULL Otherwise
+ */
+iova tegra_ast_map_slave_to_iova(const struct tegra_ast_region_map *map,
+                                 const uint64_t slave);
+
+/**
+ * @brief Map IOVA to slave address in ast region.
+ *
+ * Returns address in slave address space corresponding to the input IOVA
+ *
+ * @param[in] map  AST region mapping
+ * @param[in] iova 40-bit valid I/O virtual address
+ *
+ * @func_req_id 10683234
+ *
+ * @retval slave_address If input IOVA is valid and lies within the AST region
+ *                       map
+ * @retval 0             Otherwise
+ */
+uint64_t tegra_ast_map_iova_to_slave(const struct tegra_ast_region_map *map,
+                                     const iova iova_addr);
+
+/**
+ * @brief Set Default Stream ID
+ * Enables physical stream ID or adds an entry to the streamID control table for default access
+ *
+ * @param[in] stream_id     StreamID value to be set as specified by the hypervisor
+ * @param[in] instance_mask AST instance mask [AST_INSTANCE_R5,
+ *                          AST_INSTANCE_DMA, AST_INSTANCE_R5_AND_DMA]
+ * @param[in] phy           Bool variable to set input stream ID as physical streamID
+ *
+ * @func_req_id 13063249
+ *
+ * @retval 0                        For success
+ * @retval E_AST_GLOBALLY_LOCKED    Physical stream ID could not be set as AST
+ *                                  is globally locked
+ * @retval E_AST_INVALID_VMINDEX    If streamID could not be set.
+ */
+error_t tegra_ast_set_default_stream_id(uint8_t stream_id, uint8_t instance_mask,
+                                        bool phy);
+
+/**
+ * @brief Set Default Stream ID
+ * Enables physical stream ID or adds an entry to the streamID control table for default access
+ *
+ * @param[in] stream_id     StreamID value to be set as specified by the hypervisor
+ * @param[in] base          base address of the AST instance to be used
+ * @param[in] phy           Bool variable to set input stream ID as physical streamID
+ *
+ * @func_req_id 13063249
+ *
+ * @retval 0                        For success
+ * @retval E_AST_GLOBALLY_LOCKED    Physical stream ID could not be set as AST
+ *                                  is globally locked
+ * @retval E_AST_INVALID_VMINDEX    If streamID could not be set.
+ */
+error_t tegra_ast_addr_set_default_stream_id(uint8_t stream_id,
+                                             uint32_t base,
+                                             bool phy);
+
+/**
+ * @brief Enable an AST region with physical streamID
+ *
+ * @param[in] region        Region number [0 - MAX_REGION_INDEX]
+ * @param[in] master        Base address in SoC address space
+ * @param[in] slave         Base address in private address space
+ * @param[in] size          Size of the region. Should be less than size
+ *                          of the private address space
+ * @param[in] instance_mask AST instance mask [AST_INSTANCE_R5,
+ *                          AST_INSTANCE_DMA, AST_INSTANCE_R5_AND_DMA]
+ *
+ * @pre
+ * - Region size must be programmed as power of 2 multiple of the align
+ *   address.
+ * - Regions may not overlap.
+ * - Master and slave base addresses must be aligned to the region size.
+ *
+ * @func_req_id 10551222
+ *
+ * @retval 0                                For success
+ * @retval E_AST_GLOBALLY_LOCKED            Region could not be enabled as AST
+ *                                          is globally locked
+ * @retval E_AST_INVALID_INPUT_PARAMETERS   For invalid region index,
+ *                                          instance_mask, master/slave address
+ *                                          and size of the region.
+ */
+error_t tegra_ast_enable_phy_region(uint8_t region,
+                                    iova master,
+                                    uint64_t slave,
+                                    uint64_t size,
+                                    uint8_t instance_mask);
+
+/**
+ * @brief Enable an AST region with physical streamID
+ *
+ * @param[in] region        Region number [0 - MAX_REGION_INDEX]
+ * @param[in] master        Base address in SoC address space
+ * @param[in] slave         Base address in private address space
+ * @param[in] size          Size of the region. Should be less than size
+ *                          of the private address space
+ * @param[in] base          Base address of the AST instance to be used
+ *
+ * @pre
+ * - Region size must be programmed as power of 2 multiple of the align
+ *   address.
+ * - Regions may not overlap.
+ * - Master and slave base addresses must be aligned to the region size.
+ *
+ * @func_req_id 10551222
+ *
+ * @retval 0                                For success
+ * @retval E_AST_GLOBALLY_LOCKED            Region could not be enabled as AST
+ *                                          is globally locked
+ * @retval E_AST_INVALID_INPUT_PARAMETERS   For invalid region index,
+ *                                          instance_mask, master/slave address
+ *                                          and size of the region.
+ */
+error_t tegra_ast_addr_enable_phy_region(uint8_t region,
+                                         iova master,
+                                         uint64_t slave,
+                                         uint64_t size,
+                                         uint32_t base);
+
+/**
+ * @brief Enable an AST region with streamid pre-programmed in the
+ * input region
+ * This API shall be used to enable regions mapped with virtual
+ * streamID.
+ *
+ * For most firmwares, the streamID is pre-programmed in the region control
+ * register and cannot be accessed. In such cases, the client shall call
+ * tegra_ast_get_region_mapping() to get the region details.
+ * If the region is not enabled, the client shall call this function to enable
+ * the region with data obtained from tegra_ast_get_region_mapping().
+ * As an example,
+ *           err = tegra_ast_get_region_mapping(region, &return_region_map,
+ *                                              AST_INSTANCE_R5);
+ *           if (err != SUCCESS) {
+ *               goto out;
+ *           }
+ *           if (!return_region_map->is_enabled &&
+ *               !return_region_map->is_physical) {
+ *               err = tegra_ast_enable_region_index(region,
+ *                                             return_region_map->master,
+ *                                             return_region_map->slave,
+ *                                             return_region_map->size,
+ *                                             return_region_map->vmindex,
+ *                                             AST_INSTANCE_R5)
+ *           }
+ *
+ * @param[in] region        Region number [0 - MAX_REGION_INDEX]
+ * @param[in] master        Base address in SoC address space
+ * @param[in] slave         Base address in private address space
+ * @param[in] size          Size of the region. Should be less than size
+ *                          of the private address space
+ *                          to the client streamID
+ * @param[in] instance_mask AST instance mask [AST_INSTANCE_R5,
+ *                          AST_INSTANCE_DMA, AST_INSTANCE_R5_AND_DMA]
+ *                          master & slave base addresses
+ * @param[in] vmindex       VMIndex value to be used for the region corresponding
+ *
+ * @pre
+ * - Region size must be programmed as power of 2 multiple of the align
+ *   address.
+ * - Regions may not overlap.
+ * - Master and slave base addresses must be aligned to the region size.
+ * - Region streamid is pre-programmed in the AST registers
+ *
+ * @retval 0                                For success
+ * @retval E_AST_INVALID_VMINDEX            Out of range vmindex
+ * @retval E_AST_INVALID_INPUT_PARAMETERS   For invalid region and instance_mask
+ */
+error_t tegra_ast_enable_region_vmindex(uint8_t  region,
+                                        iova     master,
+                                        uint64_t slave,
+                                        uint64_t size,
+                                        uint8_t  instance_mask,
+                                        uint8_t  vmindex);
+
+/**
+ * @brief Enable an AST region with streamid pre-programmed in the
+ * input region
+ * This API shall be used to enable regions mapped with virtual
+ * streamID.
+ *
+ * For most firmwares, the streamID is pre-programmed in the region control
+ * register and cannot be accessed. In such cases, the client shall call
+ * tegra_ast_get_region_mapping() to get the region details.
+ * If the region is not enabled, the client shall call this function to enable
+ * the region with data obtained from tegra_ast_get_region_mapping().
+ * As an example,
+ *           err = tegra_ast_get_region_mapping(region, &return_region_map,
+ *                                              AST_INSTANCE_R5);
+ *           if (err != SUCCESS) {
+ *               goto out;
+ *           }
+ *           if (!return_region_map->is_enabled &&
+ *               !return_region_map->is_physical) {
+ *               err = tegra_ast_enable_region_index(region,
+ *                                             return_region_map->master,
+ *                                             return_region_map->slave,
+ *                                             return_region_map->size,
+ *                                             return_region_map->vmindex,
+ *                                             AST_INSTANCE_R5)
+ *           }
+ *
+ * @param[in] region        Region number [0 - MAX_REGION_INDEX]
+ * @param[in] master        Base address in SoC address space
+ * @param[in] slave         Base address in private address space
+ * @param[in] size          Size of the region. Should be less than size
+ *                          of the private address space
+ * @param[in] base          Base address of the AST to be used
+ * @param[in] vmindex       VMIndex value to be used for the region corresponding
+ *                          master & slave base addresses
+ *                          to the client streamID
+ *
+ * @pre
+ * - Region size must be programmed as power of 2 multiple of the align
+ *   address.
+ * - Regions may not overlap.
+ * - Master and slave base addresses must be aligned to the region size.
+ * - Region streamid is pre-programmed in the AST registers
+ *
+ * @retval 0                                For success
+ * @retval E_AST_INVALID_VMINDEX            Out of range vmindex
+ * @retval E_AST_INVALID_INPUT_PARAMETERS   For invalid region and instance_mask
+ */
+error_t tegra_ast_addr_enable_region_vmindex(uint8_t  region,
+                                             iova     master,
+                                             uint64_t slave,
+                                             uint64_t size,
+                                             uint32_t base,
+                                             uint8_t  vmindex);
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif /* AST__TEGRA_AST_H */
diff --git a/spe-freertos-bsp/fsp/source/include/base/module-id.h b/spe-freertos-bsp/fsp/source/include/base/module-id.h
new file mode 100644
index 0000000..51c771d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/base/module-id.h
@@ -0,0 +1,107 @@
+/* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef BASE__MODULE_ID_H
+#define BASE__MODULE_ID_H
+#define FSP__BASE__MODULE_ID_H                          1
+
+#include <misc/macros.h>
+
+/*
+ * Module IDs are chosen so that when they are combined with a
+ * subsystem's local errors, the resultant global value is a negative
+ * (as in less than 0) value.
+ */
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#define MODULE_ID_RTOS          0UL
+#define MODULE_ID_FDT           1UL
+#define MODULE_ID_COMMON        2UL
+#define MODULE_ID_ABORT         3UL
+#define MODULE_ID_ASSERT        4UL
+#define MODULE_ID_VIC           5UL
+#define MODULE_ID_TKE           6UL
+#define MODULE_ID_WDT           7UL
+#define MODULE_ID_WATCHDOG      8UL
+#define MODULE_ID_I2C           9UL
+#define MODULE_ID_HSP           10UL
+#define MODULE_ID_AST           11UL
+#define MODULE_ID_LIC           12UL
+#define MODULE_ID_TCU           13UL
+#define MODULE_ID_SMATH         14UL
+#define MODULE_ID_UART          15UL
+#define MODULE_ID_GPCDMA        16UL
+#define MODULE_ID_GPIO          17UL
+#define MODULE_ID_SPI           18UL
+#define MODULE_ID_CAR           19UL
+#define MODULE_ID_COMB_UART     20UL
+#define MODULE_ID_AODMIC        21UL
+#define MODULE_ID_ADCC          22UL
+#define MODULE_ID_SHA_NVRISCV   23UL
+#define MODULE_ID_SCP           24UL
+#define MODULE_ID_UTC           25UL
+
+
+#define MODULE_ID_APPLICATION   64UL
+
+/*
+ * Error ID manipulation
+ *
+ * Note: These can't use the BIT manipulation macros because the compiler
+ * will complain about shifts being out of range when used as an initializer
+ * index in an array.
+ *
+ * Negation is equivalent to 2's compliment conversion: -(val) = ~(val) + 1
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_20_10, "Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx")
+#define MODULE_ERROR_SIZE               (24UL)
+#define MODULE_ERROR_ID(_id_)           (((uint32_t)(MODULE_ID_##_id_)) << MODULE_ERROR_SIZE)
+#define MODULE_ERROR_VAL(_id_, _code_)  (MODULE_ERROR_ID(_id_) | (uint32_t)(_code_))
+
+#if (!defined(PROJECT_BAREMETAL))
+// RTOS requires error codes to be negative
+// NOTE: Does LittleKernel need to be included here as well?
+#define MODULE_ERROR(_id_, _code_)      ((error_t)-(int32_t)MODULE_ERROR_VAL(_id_, _code_))
+#define MODULE_ERROR_CODE_MASK          ((1UL << MODULE_ERROR_SIZE) - 1UL)
+#define MODULE_ERROR_ID_MASK            ((1UL << (32UL - MODULE_ERROR_SIZE)) - 1UL)
+#define MODULE_ERROR_CODE(_err_)        (((uint32_t)(-(_err_))) & MODULE_ERROR_CODE_MASK)
+#define MODULE_ERROR_MODULE(_err_)      ((((uint32_t)(-(_err_))) >> MODULE_ERROR_SIZE) & MODULE_ERROR_ID_MASK)
+#else
+// Error codes that do not have to be SafeRTOS compatible
+#define MODULE_ERROR(_id_, _code_)      ((error_t)MODULE_ERROR_VAL(_id_, _code_))
+#define MODULE_ERROR_CODE_MASK          ((1UL << MODULE_ERROR_SIZE) - 1UL)
+#define MODULE_ERROR_ID_MASK            ((1UL << (32UL - MODULE_ERROR_SIZE)) - 1UL)
+#define MODULE_ERROR_CODE(_err_)        (((uint32_t)(_err_)) & MODULE_ERROR_CODE_MASK)
+#define MODULE_ERROR_MODULE(_err_)      ((((uint32_t)(_err_)) >> MODULE_ERROR_SIZE) & MODULE_ERROR_ID_MASK)
+#endif
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Rule_20_10, "Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif /* BASE__MODULE_ID_H */
diff --git a/spe-freertos-bsp/fsp/source/include/car/car-clk.h b/spe-freertos-bsp/fsp/source/include/car/car-clk.h
new file mode 100644
index 0000000..a90914c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/car/car-clk.h
@@ -0,0 +1,166 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CAR__CAR_CLK_H
+#define CAR__CAR_CLK_H
+#define FSP__CAR__CAR_CLK_H             1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD...
+#include <error/common-errors.h>        // for error_t
+
+/* Module-specific FSP headers */
+#include <car/car-fmon.h>               // for frequency monitor structures...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_FMON_H, "Header file missing or invalid.")
+
+/**
+ * @file car/car-clk.h
+ * @brief Structures that are internal to the CAR driver
+ */
+
+struct car_clk_inf;
+/**
+ * @brief Structure defining clock enable/disable operations.
+ *
+ * @clk_is_enabled  returns clock enable status
+ * @clk_enable  function to enable clock.
+ * @clk_disable  function to disable clock.
+ */
+struct car_clk_op_able {
+    bool (*clk_is_enabled)(const struct car_clk_inf *clk);
+    error_t (*clk_enable)(const struct car_clk_inf *clk);
+    error_t (*clk_disable)(const struct car_clk_inf *clk);
+};
+
+/**
+ * @brief Structure defining clock rate operations.
+ *
+ * @clk_hz_set  function to set clock rate.
+ * @clk_hz_get  function to get clock rate.
+ */
+struct car_clk_op_rate {
+    error_t (*clk_hz_set)(const struct car_clk_inf *clk, int64_t hz_out);
+    error_t (*clk_hz_get)(const struct car_clk_inf *clk, int64_t *hz_out);
+};
+
+/**
+ * @brief Structure defining clock div calc operations.
+ *
+ * @clk_div_calc_in   function to calculate divisor set to reg.
+ * @clk_div_calc_out  function to calculate divisor get from reg.
+ */
+struct car_clk_op_div {
+    uint32_t (*clk_div_calc_in) (int64_t hz_in, int64_t hz_out);
+    uint32_t (*clk_div_calc_out)(const struct car_clk_inf *clk);
+};
+
+
+extern const struct car_clk_op_able car_clk_op_able_bit;
+extern const struct car_clk_op_able car_clk_op_able_reg;
+extern const struct car_clk_op_rate car_clk_op_rate_dflt;
+
+/**
+ * @brief Structure defining clock information
+ *
+ * @fmon  frequency monitor
+ * @pclk  parent clock
+ * @op_able  functions to enable/disable the clock
+ * @op_rate  functions to set/get clock rate
+ * @op_div   functions to calculate device clock divisor
+ * @rate_min  minimum rate allowed
+ * @rate_max  maximum rate allowed
+ * @en_reg  clock enable/disable register
+ * @en_msk  clock enable/disable mask
+ * @div_reg  clock divisor register
+ * @div_msk  clock divisor mask
+ */
+struct car_clk_inf {
+    const struct car_fmon_inf *fmon;
+    const struct car_clk_inf *pclk;
+    const struct car_clk_op_able *op_able;
+    const struct car_clk_op_rate *op_rate;
+    const struct car_clk_op_div *op_div;
+    int64_t hz_min;
+    int64_t hz_max;
+    uint32_t en_reg;
+    uint32_t en_msk;
+    uint32_t div_reg;
+    uint32_t div_msk;
+};
+
+/**
+ * @brief Define a clock
+ *
+ * Fills the car_clk_inf ormation structure with the info
+ * associated with the clock.
+ */
+#define CLK_INF(_i, _oa, _er, _em, _dr, _dm,    \
+                _dv, _or, _hn, _hx, _pc, _fm)   \
+    [_i] = {                                    \
+        .op_able = _oa,                         \
+        .en_reg = _er,                          \
+        .en_msk = _em,                          \
+        .div_reg = _dr,                         \
+        .div_msk = _dm,                         \
+        .op_div = _dv,                          \
+        .op_rate = _or,                         \
+        .hz_min = _hn,                          \
+        .hz_max = _hx,                          \
+        .pclk = _pc,                            \
+        .fmon = _fm,                            \
+    }
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif /* CAR__CAR_CLK_H */
+
diff --git a/spe-freertos-bsp/fsp/source/include/car/car-errors.h b/spe-freertos-bsp/fsp/source/include/car/car-errors.h
new file mode 100644
index 0000000..d2be895
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/car/car-errors.h
@@ -0,0 +1,116 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CAR__CAR_ERRORS_H
+#define CAR__CAR_ERRORS_H
+#define FSP__CAR__CAR_ERRORS_H          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "base/module-id.h"
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+
+/**
+ * @file car-errors.h
+ * @brief Error codes that are specific to CAR
+ */
+
+/*
+ * @brief Macro definitions for errors from CAR layer
+ *
+ * @macro-title CAR error codes
+ *
+ * @E_CAR_NULL_PTR                      Error value returned if input pointer
+ *                                      is NULL.
+ * @E_CAR_INVALID_PARAM                 Error value returned if input value is
+ *                                      invalid.
+ * @E_CAR_INVALID_RESET_ID              Error value returned if input reset ID
+ *                                      is invalid.
+ * @E_CAR_INVALID_CLOCK_ID              Error value returned if input clock ID
+ *                                      is invalid.
+ * @E_CAR_INVALID_FMON_ID               Error value returned if input frequency
+ *                                      monitor ID is invalid.
+ * @E_CAR_PLL_NO_INIT                   Error value returned if PLL has not
+ *                                      been initialized yet.
+ * @E_CAR_PLL_NO_LOCK                   Error value returned if PLL does not
+ *                                      lock after being enabled.
+ * @E_CAR_CLOCK_OP_NOT_SUPPORTED        Error value returned if the clock does
+ *                                      not support the operation.
+ * @E_CAR_CLOCK_HZ_NOT_SUPPORTED        Error value returned if the clock does
+ *                                      not support the requested frequency.
+ * @E_CAR_FMON_HW_LOGIC                 Error value returned if the FMON register
+ *                                      logic algorithm failed.
+ * @E_CAR_FMON_HW_TIMEOUT               Error value returned if the FMON HW did not
+ *                                      respond correctly within the allocated time.
+ * @E_CAR_FMON_FAULT                    Error value returned when a FMON fault is
+ *                                      detected.
+ * @E_CAR_FMON_NO_DATA                  Error value returned when the FMON HW has no
+ *                                      data to work with. This is typical when it
+ *                                      first starts.
+ */
+#define E_CAR_NULL_PTR                  MODULE_ERROR(CAR, 1UL)
+#define E_CAR_INVALID_PARAM             MODULE_ERROR(CAR, 2UL)
+#define E_CAR_INVALID_RESET_ID          MODULE_ERROR(CAR, 3UL)
+#define E_CAR_INVALID_CLOCK_ID          MODULE_ERROR(CAR, 4UL)
+#define E_CAR_INVALID_FMON_ID           MODULE_ERROR(CAR, 5UL)
+#define E_CAR_PLL_NO_INIT               MODULE_ERROR(CAR, 6UL)
+#define E_CAR_PLL_NO_LOCK               MODULE_ERROR(CAR, 7UL)
+#define E_CAR_CLOCK_OP_NOT_SUPPORTED    MODULE_ERROR(CAR, 8UL)
+#define E_CAR_CLOCK_HZ_NOT_SUPPORTED    MODULE_ERROR(CAR, 9UL)
+#define E_CAR_FMON_HW_LOGIC             MODULE_ERROR(CAR, 10UL)
+#define E_CAR_FMON_HW_TIMEOUT           MODULE_ERROR(CAR, 11UL)
+#define E_CAR_FMON_FAULT                MODULE_ERROR(CAR, 12UL)
+#define E_CAR_FMON_NO_DATA              MODULE_ERROR(CAR, 13UL)
+#define E_CAR_ERROR_N                   MODULE_ERROR(CAR, 14UL) /* must be the number of errors */
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif /* CAR__CAR_ERRORS_H */
+
diff --git a/spe-freertos-bsp/fsp/source/include/car/car-fmon.h b/spe-freertos-bsp/fsp/source/include/car/car-fmon.h
new file mode 100644
index 0000000..6257aed
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/car/car-fmon.h
@@ -0,0 +1,219 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CAR__CAR_FMON_H
+#define CAR__CAR_FMON_H
+#define FSP__CAR__CAR_FMON_H            1
+
+/* Compiler headers */
+#include <stdint.h>                     // for uint8_t, uint64_t, uint32_t
+#include <stdbool.h>                    // for bool
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <error/common-errors.h>        // for error_t
+
+/* Module-specific FSP headers */
+#include <car/car-clk.h>                // for clock structures, ...
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_CLK_H, "Header file missing or invalid.")
+
+
+/**
+ * @file car/car-fmon.h
+ * @brief Structures that are internal to the CAR driver
+ */
+
+#define CAR_FMON_RDWR_VERIFY_N          (3)
+
+
+/**
+ * @brief Structure defining frequency monitor (FMON)
+ *        information
+ */
+struct car_fmon_count_inf {
+    uint8_t cnt_sel_min;
+    uint8_t cnt_sel_max;
+    uint8_t cnt_sel_0;
+    uint8_t cnt_sel_n;
+    uint8_t cnt_sel_min_i;
+    uint8_t cnt_sel_max_i;
+    uint8_t cnt_sel_0_i;
+    uint8_t cnt_ref_win_i;
+    uint8_t cnt_ref_win_dc_chk_i;
+};
+
+struct car_fmon_inf {
+    const struct car_fmon_count_inf *cnt;
+    const struct car_clk_inf *clk;
+    uint64_t clk_ref;
+    uint64_t clk_err;
+    uint32_t reg_thr_hi;
+    uint32_t reg_thr_hi_msk;
+    uint32_t reg_thr_lo;
+    uint32_t reg_thr_lo_msk;
+    uint32_t reg_ref_win_cnt;
+    uint32_t reg_ref_win_cnt_msk;
+    uint32_t reg_ref_win_dc_chk_cnt;
+    uint32_t reg_ref_win_dc_chk_cnt_msk;
+    uint32_t reg_flt_actn;
+    uint32_t reg_flt_actn_msk;
+    uint32_t reg_cfg;
+    uint32_t reg_cfg_msk_rprt;
+    uint32_t reg_cfg_msk_ref_en;
+    uint32_t reg_cfg_msk_cntr_en;
+    uint32_t reg_cfg_msk_en;
+    uint32_t reg_en_sts;
+    uint32_t reg_en_sts_msk;
+    uint32_t reg_flt_sts;
+    uint32_t reg_flt_sts_msk_clr;
+    uint32_t reg_flt_sts_msk_ro;
+    uint32_t reg_data_ctrl;
+    uint32_t reg_data_ctrl_msk_sel;
+    uint32_t reg_data_ctrl_msk_en;
+    uint32_t reg_data_sts_done;
+    uint32_t reg_data_sts_done_msk;
+    uint32_t reg_data_sts_sel;
+    uint32_t reg_data_sts_sel_msk;
+    uint32_t reg_data_val;
+    uint32_t reg_data_val_msk;
+    uint32_t reg_cntr_ctrl;
+    uint32_t reg_cntr_ctrl_msk_hld;
+    uint32_t reg_cntr_ctrl_msk_clr;
+};
+
+
+/**
+ * @brief Read frequency monitor select counters.
+ *
+ * @param fmon Pointer to car_fmon_inf structure.
+ * @param cnts Pointer to write counter data to.
+ *             There must be enough memory for all of the
+ *             car_fmon_inf->cnt_sel_* counter data + 1.
+ *             Optional: Set cnts to NULL to reset the
+ *             counters without reading them (returns
+ *             E_SUCCESS).
+ * @return E_SUCCESS
+ *         E_CAR_NULL_PTR
+ *         E_CAR_FMON_NO_DATA
+ *         E_CAR_FMON_HW_LOGIC
+ *         E_CAR_FMON_HW_TIMEOUT
+ */
+error_t car_fmon_counts(const struct car_fmon_inf *fmon, uint32_t *cnts);
+
+/**
+ * @brief Calculate the input clock frequency (the frequency
+ *        that FMON is monitoring).
+ *
+ * @param fmon Pointer to car_fmon_inf structure.
+ * @param cnts Pointer to write select counter data to.
+ *             There must be enough memory for all of the
+ *             car_fmon_inf->cnt_sel_* counter data + 1.
+ *             Optional: Set cnts to NULL to reset the
+ *             counters without reading them (returns
+ *             E_SUCCESS).
+ * @param hz Pointer to write the calculated frequency to.
+ * @return E_SUCCESS
+ *         E_CAR_NULL_PTR
+ *         E_CAR_FMON_NO_DATA
+ *         E_CAR_FMON_HW_LOGIC
+ *         E_CAR_FMON_HW_TIMEOUT
+ */
+error_t car_fmon_clk_hz_calc(const struct car_fmon_inf *fmon, uint32_t *cnts, uint64_t *hz);
+
+/**
+ * @brief Get frequency monitor (FMON) default hardware timeout.
+ *
+ * The function returns the amount of time in microseconds that
+ * should be allowed for the FMON hardware to process the
+ * programming.
+ *
+ * @param fmon Pointer to car_fmon_inf structure.
+ * @return Timeout in microseconds.
+ */
+uint64_t car_fmon_timeout_us(const struct car_fmon_inf *fmon);
+
+/**
+ * @brief Frequency Monitor (FMON) enabled?.
+ *
+ * @retval  true/false
+ */
+bool car_fmon_is_enabled(const struct car_fmon_inf *fmon);
+
+/**
+ * @brief Read Frequency Monitor (FMON) enable status register
+ *        (reg_en_sts).
+ *
+ * @param fmon Pointer to car_fmon_inf structure.
+ * @return FMON enable status register data.
+ */
+uint32_t car_fmon_enable_status(const struct car_fmon_inf *fmon);
+
+/**
+ * @brief  Frequency Monitor (FMON) startup.
+ *
+ * @param fmon Pointer to car_fmon_inf structure.
+ * @return E_SUCCESS
+ *         E_CAR_NULL_PTR
+ *         E_CAR_FMON_HW_LOGIC
+ *         E_CAR_FMON_HW_TIMEOUT
+ */
+error_t car_fmon_startup(const struct car_fmon_inf *fmon);
+
+/**
+ * @brief  Frequency Monitor (FMON) shutdown.
+ *
+ * @param fmon Pointer to car_fmon_inf structure.
+ * @return E_SUCCESS
+ *         E_CAR_NULL_PTR
+ *         E_CAR_FMON_HW_LOGIC
+ *         E_CAR_FMON_HW_TIMEOUT
+ *         E_CAR_FMON_FAULT
+ */
+error_t car_fmon_shutdown(const struct car_fmon_inf *fmon);
+
+#endif /* CAR__CAR_FMON_H */
+
diff --git a/spe-freertos-bsp/fsp/source/include/car/car-hpll.h b/spe-freertos-bsp/fsp/source/include/car/car-hpll.h
new file mode 100644
index 0000000..4ba626c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/car/car-hpll.h
@@ -0,0 +1,121 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CAR__CAR_HPLL_H
+#define CAR__CAR_HPLL_H
+#define FSP__CAR__CAR_HPLL_H            1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD...
+
+/* Module-specific FSP headers */
+#include <car/car-pll.h>                // for pll functions, ...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+/**
+ * @file car/car-hpll.h
+ * @brief Structures that are internal to the CAR driver
+ */
+
+extern const struct car_pll_op car_pll_op_hpll;
+
+/**
+ * @brief Define HPLL information
+ *
+ * Fills the PLL configuration structure with the info
+ * associated with the PLL.
+ */
+#define HPLL_INF(_i, _spec, _cfg, _cfg_n, _sts,                                     \
+                 _sel_r, _sel_m, _rst_r, _rst_m, _en_r, _en_m, _iddq_r, _iddq_m,    \
+                 _mdiv_r, _mdiv_m, _ndiv_r, _ndiv_m, _pdiv_r, _pdiv_m,              \
+                 _frac_r, _frac_m, _enfrac_r, _enfrac_m, _fracstep_r, _fracstep_m,  \
+                 _iref_r, _iref_m, _lock_r, _lock_m, _lckdet_r, _lckdet_m,          \
+                 _freqlock_m, _ss_cntl_r)                                           \
+    [_i] = {                                                                        \
+        .op = &car_pll_op_hpll,                                                     \
+        .spec = _spec,                                                              \
+        .cfgs = _cfg,                                                               \
+        .cfgs_n = _cfg_n,                                                           \
+        .sts = _sts,                                                                \
+        .sel_reg = _sel_r,                                                          \
+        .sel_msk = _sel_m,                                                          \
+        .rst_reg = _rst_r,                                                          \
+        .rst_msk = _rst_m,                                                          \
+        .en_reg = _en_r,                                                            \
+        .en_msk = _en_m,                                                            \
+        .iddq_reg = _iddq_r,                                                        \
+        .iddq_msk = _iddq_m,                                                        \
+        .mdiv_reg = _mdiv_r,                                                        \
+        .mdiv_msk = _mdiv_m,                                                        \
+        .ndiv_reg = _ndiv_r,                                                        \
+        .ndiv_msk = _ndiv_m,                                                        \
+        .pdiv_reg = _pdiv_r,                                                        \
+        .pdiv_msk = _pdiv_m,                                                        \
+        .frac_reg = _frac_r,                                                        \
+        .frac_msk = _frac_m,                                                        \
+        .enfrac_reg = _enfrac_r,                                                    \
+        .enfrac_msk = _enfrac_m,                                                    \
+        .fracstep_reg = _fracstep_r,                                                \
+        .fracstep_msk = _fracstep_m,                                                \
+        .iref_reg = _iref_r,                                                        \
+        .iref_msk = _iref_m,                                                        \
+        .lock_reg = _lock_r,                                                        \
+        .lock_msk = _lock_m,                                                        \
+        .lckdet_reg = _lckdet_r,                                                    \
+        .lckdet_msk = _lckdet_m,                                                    \
+        .freqlock_msk = _freqlock_m,                                                \
+        .ss_cntl_reg = _ss_cntl_r,                                                  \
+    }
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif /* CAR__CAR_HPLL_H */
+
diff --git a/spe-freertos-bsp/fsp/source/include/car/car-math.h b/spe-freertos-bsp/fsp/source/include/car/car-math.h
new file mode 100644
index 0000000..f225995
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/car/car-math.h
@@ -0,0 +1,97 @@
+/* Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CAR__CAR_MATH_H
+#define CAR__CAR_MATH_H
+#define FSP__CAR__CAR_MATH_H            1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD...
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+
+/**
+ * WAR: CAR_FALSE can be used with do { ... } while (CAR_FALSE)
+ * loops instead of while(0) or while(false), both of which seem
+ * to confuse coverity to report rule 14.4 violations (The
+ * condition expression "0" does not have an essentially boolean
+ * type).
+ */
+#define CAR_FALSE                       (0 == 1)
+#define CAR_TRUE                        (!CAR_FALSE)
+
+/**
+ * CAR_RET_UNUSED is for ignoring function return values in a
+ * way that we can later simply grep for them. This is
+ * acceptable way of defining explicitly a function return value
+ * as uninteresting for MISRA-C Rule 17.7.
+ */
+#define CAR_RET_UNUSED(...) \
+    do {                    \
+       (void) __VA_ARGS__ ; \
+    } while(CAR_FALSE)
+
+int64_t car_add_s64(int64_t a, int64_t b);
+int64_t car_sub_s64(int64_t a, int64_t b);
+int64_t car_mul_s64(int64_t a, int64_t b);
+int64_t car_div_s64(int64_t a, int64_t b);
+int64_t car_div64_round(int64_t n, int64_t d);
+int64_t car_range_s64(int64_t x, int64_t x_min, int64_t x_max);
+int32_t car_abs_s32(int32_t x);
+int64_t car_abs_s64(int64_t x);
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif /* CAR__CAR_MATH_H */
+
+
diff --git a/spe-freertos-bsp/fsp/source/include/car/car-pll.h b/spe-freertos-bsp/fsp/source/include/car/car-pll.h
new file mode 100644
index 0000000..9f37e58
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/car/car-pll.h
@@ -0,0 +1,238 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CAR__CAR_PLL_H
+#define CAR__CAR_PLL_H
+#define FSP__CAR__CAR_PLL_H             1
+
+/**
+ * @file car/car-fsi-priv.h
+ * @brief Structures that are internal to the CAR driver
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD...
+#include <error/common-errors.h>        // for error_t
+#include <misc/bitops.h>                // for BIT, bit_number, FSP__MISC__BITOPS_H
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+
+/**
+ * @file car/car-pll.h
+ * @brief Structures that are internal to the CAR driver
+ */
+#define CAR_PLL_LOCK_DELAY              (50)
+
+#define CAR_PLL_FLG_USE_MID_VCO         BIT(0)
+#define CAR_PLL_FLG_ROUND_DOWN          BIT(1)
+#define CAR_PLL_FLG_FRAC_NDIV           BIT(2)
+#define CAR_PLL_FLG_HAS_DYNAMIC_RAMP    BIT(3)
+
+#define CAR_PLL_STS_HZ_SET              BIT(4)
+
+#define CAR_PLL_SEL_XTAL                (0)
+#define CAR_PLL_SEL_PLL                 (1)
+
+enum car_pll_type {
+    CAR_PLL_TYPE_ANALOG = 1,
+    CAR_PLL_TYPE_HPLL12 = 2,
+    CAR_PLL_TYPE_HPLL16 = 3,
+    CAR_PLL_TYPE_HPLL40 = 4,
+};
+
+struct car_pll_spec {
+    enum car_pll_type type;
+    uint32_t flags;
+    uint32_t lock_time;
+    uint32_t frac_width;
+    uint32_t min_n;
+    uint32_t max_n;
+    uint32_t min_m;
+    uint32_t max_m;
+    uint32_t min_p;
+    uint32_t max_p;
+    int64_t cf_min;
+    int64_t cf_max;
+    int64_t vco_min;
+    int64_t vco_max;
+    int64_t clkin_max;
+};
+
+struct car_pll_nmp {
+    uint32_t n;
+    uint32_t m;
+    uint32_t p;
+    int32_t frac;
+};
+
+/**
+ * @brief Structure defining PLL values for a specific
+ *        frequency.
+ */
+struct car_pll_cfg {
+    int64_t hz_in;
+    int64_t hz_out;
+    uint32_t n;
+    uint32_t m;
+    uint32_t p;
+    bool en_sdm;
+    bool en_ssc;
+    int16_t sdm_din;
+    int16_t sdm_ssc_min;
+    int16_t sdm_ssc_max;
+    int16_t sdm_ssc_step;
+    uint16_t sscmax;
+    uint8_t sscinc;
+    uint8_t sscincintrv;
+};
+
+/**
+ * @brief Define PLL frequency
+ *
+ * Fills the PLL configuration structure with the info
+ * associated with the PLL.
+ */
+#define PLL_CFG(_i, _hz_in, _hz_out, _n, _m, _p,                              \
+                _en_sdm, _sdm_din, _sdm_ssc_min, _sdm_ssc_max, _sdm_ssc_step, \
+                _en_ssc, _sscmax, _sscinc, _sscincintrv)                      \
+    [_i] = {                                                                  \
+        .hz_in = _hz_in,                                                      \
+        .hz_out = _hz_out,                                                    \
+        .n = _n,                                                              \
+        .m = _m,                                                              \
+        .p = _p,                                                              \
+        .en_sdm = _en_sdm,                                                    \
+        .en_ssc = _en_ssc,                                                    \
+        .sdm_din = _sdm_din,                                                  \
+        .sdm_ssc_min = _sdm_ssc_min,                                          \
+        .sdm_ssc_max = _sdm_ssc_max,                                          \
+        .sdm_ssc_step = _sdm_ssc_step,                                        \
+        .sscmax = _sscmax,                                                    \
+        .sscinc = _sscinc,                                                    \
+        .sscincintrv = _sscincintrv,                                          \
+    }
+
+struct car_pll_op;
+
+struct car_pll_inf {
+    const struct car_pll_op *op;
+    const struct car_pll_spec **spec;
+    const struct car_pll_cfg **cfgs;
+    uint32_t *cfgs_n;
+    uint32_t *sts;
+    uint32_t sel_reg;
+    uint32_t sel_msk;
+    uint32_t rst_reg;
+    uint32_t rst_msk;
+    uint32_t en_reg;
+    uint32_t en_msk;
+    uint32_t iddq_reg;
+    uint32_t iddq_msk;
+    uint32_t mdiv_reg;
+    uint32_t mdiv_msk;
+    uint32_t ndiv_reg;
+    uint32_t ndiv_msk;
+    uint32_t pdiv_reg;
+    uint32_t pdiv_msk;
+    uint32_t frac_reg;
+    uint32_t frac_msk;
+    uint32_t enfrac_reg;
+    uint32_t enfrac_msk;
+    uint32_t fracstep_reg;
+    uint32_t fracstep_msk;
+    uint32_t iref_reg;
+    uint32_t iref_msk;
+    uint32_t lock_reg;
+    uint32_t lock_msk;
+    uint32_t lckdet_reg;
+    uint32_t lckdet_msk;
+    uint32_t freqlock_msk;
+    uint32_t ss_cntl_reg;
+};
+
+/**
+ * @brief Structure defining PLL operations
+ *
+ */
+struct car_pll_op {
+    bool (*frac_allowed)(const struct car_pll_inf *pll);
+    bool (*pll_is_enabled)(const struct car_pll_inf *pll);
+    error_t (*pll_enable)(const struct car_pll_inf *pll);
+    error_t (*pll_disable)(const struct car_pll_inf *pll);
+    int64_t (*pll_hz_set)(const struct car_pll_inf *pll, int64_t hz_in, int64_t hz_out);
+    int64_t (*pll_hz_get)(const struct car_pll_inf *pll, int64_t hz_in);
+};
+
+
+error_t car_pll_wait_lock_us(const struct car_pll_inf *pll, uint64_t t_us);
+error_t car_pll_wait_lock(const struct car_pll_inf *pll);
+int64_t car_pll_hz_calc(const struct car_pll_inf *pll,
+                        struct car_pll_cfg *cfg, int64_t hz_in);
+void car_pll_nmp_get(const struct car_pll_inf *pll, struct car_pll_cfg *cfg);
+void car_pll_nmp_set(const struct car_pll_inf *pll, struct car_pll_cfg *cfg);
+error_t car_pll_nmp_calc(const struct car_pll_spec *spec, struct car_pll_nmp *nmp,
+                         int64_t hz_in, int64_t f_in, int32_t p_pref, uint32_t flags);
+const struct car_pll_cfg *car_pll_cfg_get(const struct car_pll_inf *pll,
+                                          int64_t hz_in, int64_t hz_out);
+error_t car_pll_cfg_calc(const struct car_pll_inf *pll,
+                         int64_t hz_in, int64_t hz_out, int64_t hz_max,
+                         struct car_pll_cfg *cfg, int32_t p_curr);
+int64_t car_pll_hz_get(const struct car_pll_inf *pll, int64_t hz_in);
+error_t car_pll_select(const struct car_pll_inf *pll, uint32_t sel);
+bool car_pll_is_enabled(const struct car_pll_inf *pll);
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif /* CAR__CAR_PLL_H */
+
diff --git a/spe-freertos-bsp/fsp/source/include/car/car-reg.h b/spe-freertos-bsp/fsp/source/include/car/car-reg.h
new file mode 100644
index 0000000..02f3ea5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/car/car-reg.h
@@ -0,0 +1,126 @@
+/* Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CAR__CAR_REG_H
+#define CAR__CAR_REG_H
+#define FSP__CAR__CAR_REG_H             1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+
+/**
+ * @brief Read a CAR MMIO register.
+ *
+ * @param offset The register offset from the CAR MMIO base address.
+ * @return Value read from register.
+ */
+uint32_t car_reg_rd(uint32_t offset);
+
+/**
+ * @brief Write a value to a CAR MMIO register.
+ *
+ * @param offset The register offset from the CAR MMIO base
+ *               address.
+ * @param data The value to write to the register.
+ * @return Void.
+ */
+void car_reg_wr(uint32_t offset, uint32_t data);
+
+/**
+ * @brief Read, modify, write to a CAR MMIO register.
+ *
+ * @param offset The register offset from the CAR MMIO base
+ *               address.
+ * @param data The data in the mask field to write.
+ * @param mask The mask of the field(s) to modify and write.
+ * @return The value written to register.
+ */
+uint32_t car_reg_rdwr(uint32_t offset, uint32_t data, uint32_t mask);
+
+/**
+ * @brief Read a value from a CAR MMIO register field.
+ *
+ * The purpose of the function is to read the value from a
+ * register field regardless of the fields bit alignment with
+ * the register.
+ * For example:
+ * Register data  = 0x12345678
+ * Mask           = 0x000FF000
+ * Value returned = 0x00000045
+ *
+ * @param offset The register offset from the CAR MMIO base
+ *               address.
+ * @param mask The mask of the data field to read.
+ * @return The value read from register field shifted to bit
+ *         zero.
+ */
+uint32_t car_reg_rd_val(uint32_t offset, uint32_t mask);
+
+/**
+ * @brief Write a value to a CAR MMIO register field.
+ *
+ * The purpose of the function is to write a value to a register
+ * field regardless of the fields bit alignment with the
+ * register.
+ * For example:
+ * Register data = 0x00000000
+ * Mask          = 0x000FF000
+ * Value         = 0x00000045
+ * Register data = 0x00045000
+ *
+ * @param offset The register offset from the CAR MMIO base
+ *               address.
+ * @param mask The mask of the data field to write.
+ * @param val The value to write to the field.
+ * @return The register data written to the register.
+ */
+uint32_t car_reg_rdwr_val(uint32_t offset, uint32_t mask, uint32_t val);
+
+#endif /* CAR__CAR_REG_H */
+
diff --git a/spe-freertos-bsp/fsp/source/include/car/car-rst.h b/spe-freertos-bsp/fsp/source/include/car/car-rst.h
new file mode 100644
index 0000000..008ffdc
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/car/car-rst.h
@@ -0,0 +1,131 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CAR__CAR_RST_H
+#define CAR__CAR_RST_H
+#define FSP__CAR__CAR_RST_H             1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD...
+#include <error/common-errors.h>        // for error_t
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+
+/**
+ * @file car/car-rst.h
+ * @brief Structures that are internal to the CAR driver
+ */
+
+/**
+ * @brief Structure defining reset information
+ *
+ * @ops   Reset interface operations.
+ * @label Reset signal name as defined by hardware.
+ * @flags Boolean details about the reset signal.
+ * @reg   The reset's main register offset in CAR.
+ * @bit   The bit position that controls the reset.
+ */
+struct car_rst_inf {
+    const struct car_rst_op *op;
+    uint32_t flags;
+    uint32_t reg;
+    uint32_t msk;
+};
+
+/**
+ * @brief Structure defining reset operations
+ *
+ * @rst_assert   Function to assert the reset.
+ * @rst_deassert Function to deassert the reset.
+ */
+struct car_rst_op {
+    bool (*rst_is_asserted)(const struct car_rst_inf *rst);
+    error_t (*rst_assert)(const struct car_rst_inf *rst);
+    error_t (*rst_deassert)(const struct car_rst_inf *rst);
+};
+
+extern const struct car_rst_op car_rst_op_bit;
+extern const struct car_rst_op car_rst_op_reg;
+
+/**
+ * @brief Define a bit controlled reset signal
+ *
+ * Fills the reset structure with the info associated with a bit
+ * controlled reset.
+ */
+#define CAR_RST_TYPE_B(_i, _f, _r, _m)  \
+    [_i] = {                            \
+        .op = &car_rst_op_bit,          \
+        .flags = _f,                    \
+        .reg = _r,                      \
+        .msk = _m,                      \
+    }
+
+/**
+ * @brief Define a register controlled reset signal
+ *
+ * Fills the reset structure with the info associated with a
+ * register controlled reset.
+ */
+#define CAR_RST_TYPE_R(_i, _f, _r, _m)  \
+    [_i] = {                            \
+        .op = &car_rst_op_reg,          \
+        .flags = _f,                    \
+        .reg = _r,                      \
+        .msk = _m,                      \
+    }
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif /* CAR__CAR_RST_H */
+
diff --git a/spe-freertos-bsp/fsp/source/include/car/car-sections.h b/spe-freertos-bsp/fsp/source/include/car/car-sections.h
new file mode 100644
index 0000000..d23fe40
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/car/car-sections.h
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CAR__SECTIONS_CAR_H
+#define CAR__SECTIONS_CAR_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>            // for SECTION
+#include <misc/macros.h>                // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+#define SECTION_NAME_CAR_TEXT           .text.car
+#define SECTION_NAME_CAR_RODATA         .rodata.car
+#define SECTION_NAME_CAR_DATA           .data.car
+#define SECTION_NAME_CAR_INIT_TEXT      .text.init.car
+#define SECTION_NAME_CAR_INIT_DATA      .data.init.car
+
+#define SECTION_STR_CAR_TEXT            STR(SECTION_NAME_CAR_TEXT)
+#define SECTION_STR_CAR_RODATA          STR(SECTION_NAME_CAR_RODATA)
+#define SECTION_STR_CAR_DATA            STR(SECTION_NAME_CAR_DATA)
+#define SECTION_STR_CAR_INIT_TEXT       STR(SECTION_NAME_CAR_INIT_TEXT)
+#define SECTION_STR_CAR_INIT_DATA       STR(SECTION_NAME_CAR_INIT_DATA)
+
+#define SECTION_CAR_TEXT                SECTION(SECTION_STR_CAR_TEXT)
+#define SECTION_CAR_RODATA              SECTION(SECTION_STR_CAR_RODATA)
+#define SECTION_CAR_DATA                SECTION(SECTION_STR_CAR_DATA)
+#define SECTION_CAR_INIT_TEXT           SECTION(SECTION_STR_CAR_INIT_TEXT)
+#define SECTION_CAR_INIT_DATA           SECTION(SECTION_STR_CAR_INIT_DATA)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif /* CAR__SECTIONS_CAR_H */
+
diff --git a/spe-freertos-bsp/fsp/source/include/chipid/chip-id.h b/spe-freertos-bsp/fsp/source/include/chipid/chip-id.h
new file mode 100644
index 0000000..4a23012
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/chipid/chip-id.h
@@ -0,0 +1,223 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2019-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
+ *
+ * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
+ * property and proprietary rights in and to this material, related
+ * documentation and any modifications thereto. Any use, reproduction,
+ * disclosure or distribution of this material and related documentation
+ * without an express license agreement from NVIDIA CORPORATION or
+ * its affiliates is strictly prohibited.
+ */
+
+#ifndef CHIPID__CHIP_ID_H
+#define CHIPID__CHIP_ID_H
+#define FSP__CHIPID__CHIP_ID_H                          1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>        // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+/* Module-specific FSP headers */
+
+/**
+ * @brief Defines for the Tegra Platform ID
+ *
+ * @macro-title Tegra Platform ID
+ * @TEGRA_PLATFORM_ID_T186 Platform ID for Tegra T186
+ * @TEGRA_PLATFORM_ID_T194 Platform ID for Tegra T194
+ * @TEGRA_PLATFORM_ID_T234 Platform ID for Tegra T234
+ * @TEGRA_PLATFORM_ID_T239 Platform ID for Tegra T239
+ * @TEGRA_PLATFORM_ID_T264 Platform ID for Tegra T264
+ */
+#define TEGRA_PLATFORM_ID_T186 0x186
+#define TEGRA_PLATFORM_ID_T194 0x194
+#define TEGRA_PLATFORM_ID_T234 0x234
+#define TEGRA_PLATFORM_ID_T239 0x239
+#define TEGRA_PLATFORM_ID_T264 0x264
+
+/**
+ * @brief Defines for the Tegra CHIP ID
+ *
+ * @macro-title Tegra SOC Name
+ * @TEGRA_SOC_NAME_T18X Chip ID for Tegra T18x
+ * @TEGRA_SOC_NAME_T19X Chip ID for Tegra T19x
+ * @TEGRA_SOC_NAME_T23X Chip ID for Tegra T23x
+ * @TEGRA_SOC_NAME_T26X Chip ID for Tegra T26x
+ */
+#define TEGRA_SOC_NAME_T18X 0x18
+#define TEGRA_SOC_NAME_T19X 0x19
+#define TEGRA_SOC_NAME_T23X 0x23
+#define TEGRA_SOC_NAME_T26X 0x26
+
+/**
+ * @brief Defines for the Tegra Major Revision number
+ *
+ * @macro-title Tegra Major Revision
+ * @TEGRA_MAJOR_REVISION_A Tegra Chip Major Revision 'A'
+ * @TEGRA_MAJOR_REVISION_B Tegra Chip Major Revision 'B'
+ * @TEGRA_MAJOR_REVISION_C Tegra Chip Major Revision 'C'
+ * @TEGRA_MAJOR_REVISION_D Tegra Chip Major Revision 'D'
+ * @TEGRA_MAJOR_REVISION_E Tegra Chip Major Revision 'E'
+ * @TEGRA_MAJOR_REVISION_F Tegra Chip Major Revision 'F'
+ * @TEGRA_MAJOR_REVISION_G Tegra Chip Major Revision 'G'
+ * @TEGRA_MAJOR_REVISION_H Tegra Chip Major Revision 'H'
+ * @TEGRA_MAJOR_REVISION_I Tegra Chip Major Revision 'I'
+ */
+#define TEGRA_MAJOR_REVISION_A 0x1
+#define TEGRA_MAJOR_REVISION_B 0x2
+#define TEGRA_MAJOR_REVISION_C 0x3
+#define TEGRA_MAJOR_REVISION_D 0x4
+#define TEGRA_MAJOR_REVISION_E 0x5
+#define TEGRA_MAJOR_REVISION_F 0x6
+#define TEGRA_MAJOR_REVISION_G 0x7
+#define TEGRA_MAJOR_REVISION_H 0x8
+#define TEGRA_MAJOR_REVISION_I 0x9
+
+/**
+ * @brief Defines for the Tegra Minor Revision number
+ *
+ * @macro-title Tegra Minor Revision
+ * @TEGRA_MINOR_REVISION_1 Tegra Chip Minor Revision number 1
+ * @TEGRA_MINOR_REVISION_2 Tegra Chip Minor Revision number 2
+ */
+#define TEGRA_MINOR_REVISION_1 0x1
+#define TEGRA_MINOR_REVISION_2 0x2
+
+/**
+ * @brief Defines for the Tegra Sub Revision
+ *
+ * @macro-title Tegra Sub Revision
+ * @TEGRA_SUB_REVISION_P Tegra Chip Sub Revision 'P'
+ * @TEGRA_SUB_REVISION_Q Tegra Chip Sub Revision 'Q'
+ * @TEGRA_SUB_REVISION_R Tegra Chip Sub Revision 'R'
+ */
+#define TEGRA_SUB_REVISION_P 0x1
+#define TEGRA_SUB_REVISION_Q 0x2
+#define TEGRA_SUB_REVISION_R 0x3
+#define TEGRA_SUB_NONE 0x0
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @brief Get the platforms id
+ *
+ * The api internally calls tegra_get_chipid and tegra_get_major_rev and returns
+ * the actual platoform ID. +
+ * Ex - for platform T239, +
+ * tegra_get_chipid returns - 0x23 +
+ * tegra_get_major_rev returns - 0x9 +
+ * tegra_get_platform returns - 0x239
+ *
+ * @jama_func_req_id ?
+ *
+ * @retval 0x186 Tegra 186 platform
+ * @retval 0x194 Tegra 194 platform
+ * @retval 0x234 Tegra 234 platform
+ * @retval 0x239 Tegra 239 platform
+ * @retval 0x264 Tegra 264 platform
+ */
+uint16_t tegra_get_platform(void);
+
+/**
+ * @brief Get the Tegra chip family identifier
+ *
+ * @jama_func_req_id 8160164
+ *
+ * @retval TEGRA_SOC_NAME_T18X Tegra chip family identifier for T18X chips
+ * @retval TEGRA_SOC_NAME_T19X Tegra chip family identifier for T19X chips
+ * @retval TEGRA_SOC_NAME_T26X Tegra chip family identifier for T26X chips
+ */
+uint8_t tegra_get_chipid(void);
+
+/**
+ * @brief Get the chip major revision number
+ *
+ * @jama_func_req_id 8160170
+ *
+ * @retval TEGRA_MAJOR_REVISION_A Tegra chip major revision is A
+ * @retval TEGRA_MAJOR_REVISION_B Tegra chip major revision is B
+ */
+uint8_t tegra_get_major_rev(void);
+
+/**
+ * @brief Get the minor revision number
+ *
+ * @jama_func_req_id 8161055
+ *
+ * @retval TEGRA_MINOR_REVISION_1 Tegra chip minor revision is 1
+ * @retval TEGRA_MINOR_REVISION_2 Tegra chip minor revision is 2
+ */
+uint8_t tegra_get_minor_rev(void);
+
+/**
+ * @brief Check if running on actual silicon
+ *
+ * @jama_func_req_id 8161334
+ *
+ * @retval True If the API is called on Silicon
+ * @retval False If the API is called on non-silicon platform
+ */
+bool tegra_platform_is_silicon(void);
+
+/**
+ * @brief Check if running on fpga
+ *
+ * @jama_func_req_id 8161334
+ *
+ * @retval True If the API is called on fpga
+ * @retval False If the API is called on silicon or simulation platform
+ */
+bool tegra_platform_is_fpga(void);
+
+/**
+ * @brief Check if running on vdk
+ *
+ * @jama_func_req_id 8161334
+ *
+ * @retval True If the API is called on VDK
+ * @retval False If the API is called on silicon platform
+ */
+bool tegra_platform_is_vdk(void);
+
+/**
+ * @brief Get sub revision number
+ *
+ * @jama_func_req_id 8191178
+ *
+ * @retval TEGRA_SUB_REVISION_P Tegra chip sub revision is 1
+ * @retval TEGRA_SUB_REVISION_Q Tegra chip sub revision is 2
+ * @retval TEGRA_SUB_REVISION_R Tegra chip sub revision is 3
+ * @retval TEGRA_NO_SUB_REVISION Tegra chip with no sub revision
+ */
+uint8_t tegra_get_sub_rev(void);
+
+/**
+ * @brief Get tegra chip sku
+ *
+ * @jama_func_req_id 8247959
+ *
+ * @retval >0 Tegra chip SKU ID
+ */
+uint8_t tegra_get_sku_id(void);
+
+/**
+ * @brief Read fuse register
+ *
+ * @param[in] offset The register offset from the FUSE base
+ * @param[out] val   Value read from register.
+ *
+ * @retval true for read success else false
+ */
+bool tegra_fuse_control_read(uint32_t offset, uint32_t *val);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/chipid/sections-chip-id.h b/spe-freertos-bsp/fsp/source/include/chipid/sections-chip-id.h
new file mode 100644
index 0000000..364a040
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/chipid/sections-chip-id.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef CHIPID__SECTIONS_CHIP_ID_H
+#define CHIPID__SECTIONS_CHIP_ID_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME            TYPE)   */
+#define SECTION_NAME_CHIPID_DATA        SECTION_BUILDER(chipid,         data)
+#define SECTION_NAME_CHIPID_RODATA      SECTION_BUILDER(chipid,         rodata)
+#define SECTION_NAME_CHIPID_TEXT        SECTION_BUILDER(chipid,         text)
+#define SECTION_NAME_CHIPID_INIT_DATA   SECTION_BUILDER(init.chipid,    data)
+#define SECTION_NAME_CHIPID_INIT_TEXT   SECTION_BUILDER(init.chipid,    text)
+
+#define SECTION_STR_CHIPID_RODATA       STR(SECTION_NAME_CHIPID_RODATA)
+#define SECTION_STR_CHIPID_DATA         STR(SECTION_NAME_CHIPID_DATA)
+#define SECTION_STR_CHIPID_INIT_DATA    STR(SECTION_NAME_CHIPID_INIT_DATA)
+#define SECTION_STR_CHIPID_TEXT         STR(SECTION_NAME_CHIPID_TEXT)
+#define SECTION_STR_CHIPID_INIT_TEXT    STR(SECTION_NAME_CHIPID_INIT_TEXT)
+
+#define SECTION_CHIPID_RODATA           SECTION(SECTION_STR_CHIPID_RODATA)
+#define SECTION_CHIPID_DATA             SECTION(SECTION_STR_CHIPID_DATA)
+#define SECTION_CHIPID_INIT_DATA        SECTION(SECTION_STR_CHIPID_INIT_DATA)
+#define SECTION_CHIPID_TEXT             SECTION(SECTION_STR_CHIPID_TEXT)
+#define SECTION_CHIPID_INIT_TEXT        SECTION(SECTION_STR_CHIPID_INIT_TEXT)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/clk/clk-tegra.h b/spe-freertos-bsp/fsp/source/include/clk/clk-tegra.h
new file mode 100644
index 0000000..665e035
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/clk/clk-tegra.h
@@ -0,0 +1,146 @@
+/*
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This header defines a standard simple interface by which clocks can be
+ * manipulated. The intent is to provide the same API on all SoCs and clocks,
+ * even though the clock register layout may be quite different across those
+ * variations. It is quite likely that multiple implementations of this API
+ * will exist to cater for the SoC-to-SoC register differences.
+ */
+
+#ifndef CLK__CLK_TEGRA_H
+#define CLK__CLK_TEGRA_H
+#define FSP__CLK__CLK_TEGRA_H                           1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/*
+ * This is the handle or ID of a clock as used by the clock API.
+ *
+ * Each clock is identified by a pointer to a configuration structure so that
+ * only configuration data for the exact set of clocks that is referenced is
+ * included in the final binary.
+ *
+ * Each SoC supports a different set of clocks. The exact set of legal clock
+ * IDs is defined by the SoC-specific <clk-tegra-hw.h>.
+*/
+// IWYU pragma: no_forward_declare tegra_clk
+struct tegra_clk;
+
+/*
+ * This is the handle or ID of a parent clock as used by the clock API.
+ *
+ * This handle is similar to that for struct tegra_clk. However, parent clocks
+ * cannot be enabled or disabled. They can only have their clock rates set, so
+ * that other clocks sourced by these clocks can have divisors set up correctly.
+ *
+ * Each SoC supports a different set of clocks. The exact set of legal clock
+ * IDs is defined by the SoC-specific <clk-tegra-hw.h>.
+*/
+// IWYU pragma: no_forward_declare tegra_parent_clk
+struct tegra_parent_clk;
+
+/*
+ * This is the handle or ID of a clock as used by the clock API.
+ */
+// IWYU pragma: no_forward_declare tegra_rst
+struct tegra_rst;
+
+/*
+ * Initialize the clock API.
+ * For example, this may read/calculate the rates of clocks that the API
+ * does not control, but uses as a parent for clocks that it does control.
+ *
+ * Returns 0 on success, other values on failure.
+ */
+int32_t tegra_clk_init(void);
+
+/*
+ * Enable or disable a clock.
+ *
+ * Returns 0 on success, other values on failure.
+ */
+int32_t tegra_clk_enable(const struct tegra_clk *clk);
+int32_t tegra_clk_disable(const struct tegra_clk *clk);
+
+/*
+ * Check if a clock is enabled.
+ *
+ * Returns true if clock is enabled.
+ */
+bool tegra_clk_is_clk_enabled(const struct tegra_clk *clk);
+
+/*
+ * Assert or release a reset signal.
+ *
+ * Returns 0 on success, other values on failure.
+ */
+int32_t tegra_clk_reset_set(const struct tegra_rst *rst);
+int32_t tegra_clk_reset_clear(const struct tegra_rst *rst);
+
+/*
+ * Check if a reset is deasserted.
+ *
+ * Returns true if reset is deasserted.
+ */
+bool tegra_reset_is_reset_deasserted(const struct tegra_rst *rst);
+
+/*
+ * Assert, delay, and release a reset signal.
+ *
+ * Returns 0 on success, other values on failure.
+ */
+int32_t tegra_clk_reset_pulse(const struct tegra_rst *rst, uint32_t delay_us);
+
+/*
+ * Sets the rate of a clock.
+ *
+ * Returns 0 on success, other values on failure.
+ */
+int32_t tegra_clk_set_rate(const struct tegra_clk *clk, uint32_t rate_hz);
+
+/*
+ * Sets the rate of a parent clock.
+ *
+ * Depending on the implementation, may not actually change the clock rate.
+ *
+ * Returns 0 on success, other values on failure.
+ */
+int32_t tegra_parent_clk_set_rate(struct tegra_parent_clk *clk, uint32_t rate_hz);
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/comb-uart/comb-uart-errors.h b/spe-freertos-bsp/fsp/source/include/comb-uart/comb-uart-errors.h
new file mode 100644
index 0000000..f74e6c9
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/comb-uart/comb-uart-errors.h
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef COMB_UART__COMB_UART_ERRORS_H
+#define COMB_UART__COMB_UART_ERRORS_H
+#define FSP__COMB_UART__COMB_UART_ERRORS_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>         // IWYU pragma: export
+#include <misc/macros.h>            // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file comb-uart-errors.h
+ * @brief Error codes that are specific to the combined uart
+ */
+
+#define E_COMB_UART_NULL_PTR               MODULE_ERROR(COMB_UART, 0UL)
+#define E_COMB_UART_INVALID_PARAM          MODULE_ERROR(COMB_UART, 1UL)
+#define E_COMB_UART_TIMEDOUT               MODULE_ERROR(COMB_UART, 2UL)
+#define E_COMB_UART_NO_TX                  MODULE_ERROR(COMB_UART, 3UL)
+
+#endif  /* COMB_UART__COMB_UART_ERRORS_H */
diff --git a/spe-freertos-bsp/fsp/source/include/comb-uart/comb-uart-port.h b/spe-freertos-bsp/fsp/source/include/comb-uart/comb-uart-port.h
new file mode 100644
index 0000000..0e9d62d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/comb-uart/comb-uart-port.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef COMB_UART__COMB_UART_PORT_H
+#define COMB_UART__COMB_UART_PORT_H
+#define FSP__COMB_UART__COMB_UART_PORT_H             1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/**
+ * @brief returns the elapsed microseconds from a reference.
+ *
+ * @param[in] start      value of time stamp counter at the start of the period of
+ *                       when the elapsed time is being computed.
+ *
+ * @retval               the number of microseconds that have elapsed between when
+ *                       the start time was taken and this function called.
+ */
+uint64_t comb_uart_port_get_elapsed_usecs(const uint64_t start);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/comb-uart/comb-uart-priv.h b/spe-freertos-bsp/fsp/source/include/comb-uart/comb-uart-priv.h
new file mode 100644
index 0000000..d476cd6
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/comb-uart/comb-uart-priv.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef COMB_UART__COMB_UART_PRIV_H
+#define COMB_UART__COMB_UART_PRIV_H
+#define FSP__COMB_UART__COMB_UART_PRIV_H                      1
+
+/**
+ * @file comb-uart/comb-uart-priv.h
+ * @brief Structures that are internal to the COMB_UART driver
+ */
+
+/* Compiler headers */
+#include <stdbool.h>
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <comb-uart/comb-uart.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__COMB_UART__COMB_UART_H, "Header file missing or invalid.")
+
+/*Calculate SM base address from HSP base and SM number */
+#define HSP_SM_BASE(base, sm)   ((uint32_t)(base) + (0x8000u * (uint32_t)(sm)))
+
+/**
+ * @brief combined uart context structure
+ *
+ * Structure that is used by the combined uart client driver to manage
+ * during run time.
+ *
+ * @tx_sm_reg    TX mailbox register
+ * @rx_sm_reg    RX mailbox register
+ * @supports_rx  flag to indicate input support
+ */
+struct comb_uart_id {
+    const uint32_t tx_sm_reg;
+    const uint32_t rx_sm_reg;
+    const bool     supports_rx;
+};
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/comb-uart/comb-uart.h b/spe-freertos-bsp/fsp/source/include/comb-uart/comb-uart.h
new file mode 100644
index 0000000..86431f1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/comb-uart/comb-uart.h
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef COMB_UART__COMB_UART_H
+#define COMB_UART__COMB_UART_H
+#define FSP__COMB_UART__COMB_UART_H                      1
+
+/**
+ * @file comb-uart/comb-uart.h
+ * @brief functions for performing combined uart operations.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>        // for error_t, FSP__ERROR__COMMON...
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Declaration for comb_uart_id that allows the APIs to take a pointer to it
+ * without actually defining its contents here.
+ */
+struct comb_uart_id;
+
+/**
+ * @brief Output a single character to combined UART
+ *
+ * Writes a single character to the combined UART.  It does not use
+ * any services outside of this function.  It is intended for early
+ * boot debug when no services are available.
+ *
+ * @param[in] id        combined uart context
+ * @param[in] ch        character to be written
+ *
+ */
+void comb_uart_putc_now(const struct comb_uart_id *id,
+                        const char ch);
+
+/**
+ * @brief output a string via the combined UART protocol.
+ *
+ * @pre comb_uart_init() has been called
+ *
+ * @param[in] id   combined uart context
+ * @param[in] s    string to output
+ *
+ * @retval E_SUCCESS                        indicates success
+ * @retval E_COMB_UART_NULL_PTR             invalid id paramter passed
+ * @retval E_COMB_UART_TIMEDOUT             server timed out
+ */
+void comb_uart_puts(const struct comb_uart_id *id,
+                    const char *s);
+
+/**
+ * @brief output data via the combined UART protocol.
+ *
+ * @pre comb_uart_init() has been called
+ *
+ * @param[in] id   combined uart context
+ * @param[in] d    data buffer to output
+ * @param[in] len  len of the data buffer
+ *
+ * @retval E_SUCCESS                        indicates success
+ * @retval E_COMB_UART_NULL_PTR             invalid id paramter passed
+ * @retval E_COMB_UART_TIMEDOUT             server timed out
+ */
+void comb_uart_send(const struct comb_uart_id *id,
+                    const char *d,
+                    const uint32_t len);
+
+/**
+ * @brief output a char via the combined UART protocol.
+ *
+ * @pre comb_uart_init() has been called
+ *
+ * @param[in] id   combined uart context
+ * @param[in] ch   character to output
+ *
+ * @retval E_SUCCESS                        indicates success
+ * @retval E_COMB_UART_NULL_PTR             invalid id paramter passed
+ * @retval E_COMB_UART_TIMEDOUT             server timed out
+ */
+error_t comb_uart_putc(const struct comb_uart_id *id,
+                       const char ch);
+
+/**
+ * @brief tx flush operation via the combined UART protocol.
+ *
+ * @pre comb_uart_init() has been called
+ *
+ * @param[in] id   combined uart context
+ * @param[in] wait flag to indicate wait until the tx buffer is flushed
+ *
+ * @retval E_SUCCESS                        indicates success
+ * @retval E_COMB_UART_NULL_PTR             invalid id paramter passed
+ * @retval E_COMB_UART_TIMEDOUT             server timed out
+ */
+error_t comb_uart_tx_flush(const struct comb_uart_id *id);
+
+/**
+ * @brief global initialization of the COMB_UART context.
+ *
+ * @pre None
+ *
+ * @param[in] id combined uart context
+ *
+ * @retval E_SUCCESS                        indicates success
+ * @retval E_COMB_UART_NULL_PTR             invalid id paramter passed
+ * @retval E_COMB_UART_TIMEDOUT             server timed out
+ */
+error_t comb_uart_init(const struct comb_uart_id *id);
+
+/**
+ * @brief Indicate if TX is ready for a character
+ *
+ * @pre None
+ *
+ * @param[in] id combined uart context
+ *
+ * @retval true                             a character can be sent at this
+ *                                          time
+ * @retval false                            a character cannot be sent at this
+ *                                          time
+ */
+bool comb_uart_is_tx_ready(const struct comb_uart_id *id);
+
+/**
+ * @brief Indicate if combined UART can accept another character
+ *
+ * @pre None
+ *
+ * @param[in] id combined uart context
+ *
+ * @retval true                             a character can be sent at this
+ *                                          time
+ * @retval false                            a character cannot be sent at this
+ *                                          time
+ */
+bool comb_uart_tx_ready(const struct comb_uart_id *id);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/comb-uart/sections-comb-uart.h b/spe-freertos-bsp/fsp/source/include/comb-uart/sections-comb-uart.h
new file mode 100644
index 0000000..91ffd31
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/comb-uart/sections-comb-uart.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef COMB_UART__SECTIONS_COMB_UART_H
+#define COMB_UART__SECTIONS_COMB_UART_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_COMB_UART_DATA        SECTION_BUILDER(comb-uart,                 data)
+#define SECTION_NAME_COMB_UART_RODATA      SECTION_BUILDER(comb-uart,                 rodata)
+#define SECTION_NAME_COMB_UART_TEXT        SECTION_BUILDER(comb-uart,                 text)
+#define SECTION_NAME_COMB_UART_INIT_DATA   SECTION_BUILDER(init.comb-uart,            data)
+#define SECTION_NAME_COMB_UART_INIT_TEXT   SECTION_BUILDER(init.comb-uart,            text)
+
+#define SECTION_STR_COMB_UART_TEXT         STR(SECTION_NAME_COMB_UART_TEXT)
+#define SECTION_STR_COMB_UART_RODATA       STR(SECTION_NAME_COMB_UART_RODATA)
+#define SECTION_STR_COMB_UART_DATA         STR(SECTION_NAME_COMB_UART_DATA)
+#define SECTION_STR_COMB_UART_INIT_TEXT    STR(SECTION_NAME_COMB_UART_INIT_TEXT)
+#define SECTION_STR_COMB_UART_INIT_DATA    STR(SECTION_NAME_COMB_UART_INIT_DATA)
+
+#define SECTION_COMB_UART_TEXT             SECTION(SECTION_STR_COMB_UART_TEXT)
+#define SECTION_COMB_UART_RODATA           SECTION(SECTION_STR_COMB_UART_RODATA)
+#define SECTION_COMB_UART_DATA             SECTION(SECTION_STR_COMB_UART_DATA)
+#define SECTION_COMB_UART_INIT_TEXT        SECTION(SECTION_STR_COMB_UART_INIT_TEXT)
+#define SECTION_COMB_UART_INIT_DATA        SECTION(SECTION_STR_COMB_UART_INIT_DATA)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cortex-r5/cpu/mmio-access.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cortex-r5/cpu/mmio-access.h
new file mode 100644
index 0000000..f90c042
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cortex-r5/cpu/mmio-access.h
@@ -0,0 +1,188 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__MMIO_ACCESS_H
+#define CPU__MMIO_ACCESS_H
+#define FSP__CPU__MMIO_ACCESS_H                         1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/type-conversion.h>
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__CPU__TYPE_CONVERSION_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+/**
+ * @file mmio-access.h
+ * @brief functions that provide access to read and write the memory
+ * mapped hardware registers.
+ */
+
+/**
+ * @brief Read a 32-bit value from a memory mapped register
+ *
+ * @jama_func_req_id 8314409
+ *
+ * Provides an alias for 'readl' from <reg-access/reg-access.h>.
+ *
+ * This function will read a 32-bit value from the memory mapped register
+ * specified by the address parameter passed.
+ *
+ * @param[in] addr Address of the memory mapped register
+ *
+ * @return contents of the register
+ */
+static inline uint32_t ioread32(uintptr_t addr)
+{
+    return *(fsp_u32_to_vl_u32_ptr(addr));
+}
+
+/**
+ * @brief Read a 32-bit value from a memory mapped register address
+ *
+ * @jama_func_req_id 8314409
+ *
+ * Provides an alias for 'readl_base_offset' from <reg-access/reg-access.h>.
+ *
+ * This function will read a 32-bit value from the memory mapped register
+ * specified by the address computed by the sum of the passed parameters
+ * base and offset.
+ *
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register
+ *
+ * @return contents of the register
+ */
+static inline uint32_t ioread32_offset(uintptr_t base, uint32_t offset)
+{
+    uint32_t data;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__ (
+            "ldr %0, [%1, %2]\n\t"
+            : "=r" (data)
+            : "r" (base), "Ir" (offset)
+    );
+
+    return data;
+}
+
+/**
+ * @brief Write a 32-bit value to a memory mapped register
+ *
+ * @jama_func_req_id 8314412
+ *
+ * Provides an alias for 'writel' from <reg-access/reg-access.h>.
+ *
+ * This function will write a 32-bit value to the memory mapped register
+ * specified by the address parameter passed.
+ *
+ * @param[in] addr Address of the memory mapped register
+ * @param[in] data value to be written to the memory mapped register
+ */
+static inline void iowrite32(uintptr_t addr, uint32_t data)
+{
+    *(fsp_u32_to_vl_u32_ptr(addr))= data;
+}
+
+/**
+ * @brief Write a 32-bit value to a memory mapped register address
+ *
+ * @jama_func_req_id 8314412
+ *
+ * Provides an alias for 'writel_base_offset' from <reg-access/reg-access.h>.
+ *
+ * This function will write a 32-bit value to the memory mapped register
+ * address computed by the sum of the passed parameters base and offset.
+ *
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register; offset is immediate value
+ * @param[in] data value to be written to the memory mapped register
+ */
+static inline void iowrite32_offset(uintptr_t base, uint32_t offset, uint32_t data)
+{
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__ (
+            "str %0, [%1, %2]\n\t"
+            :
+            : "r" (data), "r" (base), "Ir" (offset)
+            : "memory"
+    );
+}
+
+/**
+ * @brief Write a 32-bit value to a memory mapped register address
+ *
+ * @jama_func_req_id 8314412
+ *
+ * Provides an alias for 'writel_base_regoffset' from <reg-access/reg-access.h>.
+ *
+ * This function will write a 32-bit value to the memory mapped register
+ * address computed by the sum of the passed parameters base and offset.
+ *
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register; offset is register value
+ * @param[in] data value to be written to the memory mapped register
+ */
+static inline void iowrite32_regoffset(uintptr_t base, uint32_t offset, uint32_t data)
+{
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__ (
+            "str %0, [%1, %2]\n\t"
+            :
+            : "r" (data), "r" (base), "r" (offset)
+            : "memory"
+    );
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cortex-r5/cpu/sections-cache.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cortex-r5/cpu/sections-cache.h
new file mode 100644
index 0000000..daf7b17
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cortex-r5/cpu/sections-cache.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef CPU__SECTIONS_CACHE_H
+#define CPU__SECTIONS_CACHE_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME            TYPE)   */
+#define SECTION_NAME_CACHE_TEXT         SECTION_BUILDER(cache,          text)
+#define SECTION_NAME_CACHE_RODATA       SECTION_BUILDER(cache,          rodata)
+#define SECTION_NAME_CACHE_DATA         SECTION_BUILDER(cache,          data)
+#define SECTION_NAME_CACHE_INIT_TEXT    SECTION_BUILDER(init.cache,     text)
+#define SECTION_NAME_CACHE_INIT_DATA    SECTION_BUILDER(init.cache,     data)
+
+#define SECTION_STR_CACHE_TEXT          STR(SECTION_NAME_CACHE_TEXT)
+#define SECTION_STR_CACHE_RODATA        STR(SECTION_NAME_CACHE_RODATA)
+#define SECTION_STR_CACHE_DATA          STR(SECTION_NAME_CACHE_DATA)
+#define SECTION_STR_CACHE_INIT_TEXT     STR(SECTION_NAME_CACHE_INIT_TEXT)
+#define SECTION_STR_CACHE_INIT_DATA     STR(SECTION_NAME_CACHE_INIT_DATA)
+
+#define SECTION_CACHE_TEXT              SECTION(SECTION_STR_CACHE_TEXT)
+#define SECTION_CACHE_RODATA            SECTION(SECTION_STR_CACHE_RODATA)
+#define SECTION_CACHE_DATA              SECTION(SECTION_STR_CACHE_DATA)
+#define SECTION_CACHE_INIT_TEXT         SECTION(SECTION_STR_CACHE_INIT_TEXT)
+#define SECTION_CACHE_INIT_DATA         SECTION(SECTION_STR_CACHE_INIT_DATA)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cortex-r5/reg-access/reg-access.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cortex-r5/reg-access/reg-access.h
new file mode 100644
index 0000000..c497ad2
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cortex-r5/reg-access/reg-access.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef REG_ACCESS__REG_ACCESS_H
+#define REG_ACCESS__REG_ACCESS_H
+#define FSP__REG_ACCESS__REG_ACCESS_H                   1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/mmio-access.h>      // for ioread32, iowrite32, ...
+#include <cpu/type-conversion.h>
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__CPU__MMIO_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__TYPE_CONVERSION_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file reg-access.h
+ * @brief functions that provide access to read and write the memory
+ * mapped hardware registers.
+ */
+
+/**
+ * @brief Read a 32-bit value from a memory mapped register
+ *
+ * @jama_func_req_id 8314409
+ *
+ * This function will read a 32-bit value from the memory mapped register
+ * specified by the address parameter passed.
+ *
+ * @param[in] addr Address of the memory mapped register
+ *
+ * @return contents of the register
+ */
+static inline uint32_t readl(uint32_t addr)
+{
+    return ioread32(addr);
+}
+
+/**
+ * @brief Read a 32-bit value from a memory mapped register address
+ *
+ * @jama_func_req_id 8314409
+ *
+ * This function will read a 32-bit value from the memory mapped register
+ * specified by the address computed by the sum of the passed parameters
+ * base and offset.
+ *
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register
+ *
+ * @return contents of the register
+ */
+static inline uint32_t readl_base_offset(uint32_t base, uint32_t offset)
+{
+    return ioread32_offset(base, offset);
+}
+
+/**
+ * @brief Write a 32-bit value to a memory mapped register
+ *
+ * @jama_func_req_id 8314412
+ *
+ * This function will write a 32-bit value to the memory mapped register
+ * specified by the address parameter passed.
+ *
+ * @param[in] data value to be written to the memory mapped register
+ * @param[in] addr Address of the memory mapped register
+ */
+static inline void writel(uint32_t data, uint32_t addr)
+{
+    iowrite32(addr, data);
+}
+
+/**
+ * @brief Write a 32-bit value to a memory mapped register address
+ *
+ * @jama_func_req_id 8314412
+ *
+ * This function will write a 32-bit value to the memory mapped register
+ * address computed by the sum of the passed parameters base and offset.
+ *
+ * @param[in] data value to be written to the memory mapped register
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register; offset is immediate value
+ */
+static inline void writel_base_offset(uint32_t data, uint32_t base, uint32_t offset)
+{
+    iowrite32_offset(base, offset, data);
+}
+
+/**
+ * @brief Write a 32-bit value to a memory mapped register address
+ *
+ * @jama_func_req_id 8314412
+ *
+ * This function will write a 32-bit value to the memory mapped register
+ * address computed by the sum of the passed parameters base and offset.
+ *
+ * @param[in] data value to be written to the memory mapped register
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register; offset is register value
+ */
+static inline void writel_base_regoffset(uint32_t data, uint32_t base, uint32_t offset)
+{
+    iowrite32_regoffset(base, offset, data);
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-cache.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-cache.h
new file mode 100644
index 0000000..2ac1684
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-cache.h
@@ -0,0 +1,262 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__ARMV7_CACHE_H
+#define CPU__ARMV7_CACHE_H
+#define FSP__CPU__ARMV7_CACHE_H                  1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/**
+ * @file armv7-cache.h
+ * @brief Assembly functions that implement the ARM V7 cache instructions
+ */
+
+#define CACHE_LINE_SIZE         32UL
+#define CACHE_LINE_MASK         (~(CACHE_LINE_SIZE - 1UL))
+
+/**
+ * @brief Invalidate branch predictor all
+ *
+ * Allows for the BPIALL instruction to be placed in C code.  It will
+ * invalidate the entire state of the branch predictor.
+ *
+ * @return none
+ */
+static inline void
+bpiall(void)
+{
+    __asm__ __volatile__(
+        "mcr    p15, 0, %0, c7, c5, 6\n\t"
+        : : "r" (0) : "memory"
+        );
+}
+
+/**
+ * @brief Invalidate branch predictor by VA
+ *
+ * Allows for the BPIMVA instruction to be placed in C code.  It will
+ * invalidate the specified virtual address from the branch predictor.
+ *
+ * @param[in] addr Virtual address to be removed from the branch predictor.
+ *
+ * @return none
+ */
+static inline void
+bpimva(uint32_t addr)
+{
+    __asm__ __volatile__(
+        "mcr    p15, 0, %0, c7, c5, 7\n\t"
+        : : "r" (addr) : "memory"
+        );
+}
+
+/**
+ * @brief Instruction cache line invalidate by VA
+ *
+ * Allows for the ICIMVAU instruction to be placed in C code.  It will
+ * invalidate the cache line that contains the specified virtual address
+ * from the iCache.
+ *
+ * @param[in] addr Virtual address of the cache line in the iCache to
+ * be invalidated.
+ *
+ * @return none
+ */
+static inline void
+icimvau(uint32_t addr)
+{
+    __asm__ __volatile__(
+        "mcr    p15, 0, %0, c7, c5, 1\n\t"
+        : : "r" (addr) : "memory"
+        );
+}
+
+/**
+ * @brief Instruction cache invalidate all
+ *
+ * Allows for the ICIALLU instruction to be placed in C code.  It will
+ * invalidate the entire iCache.
+ *
+ * @return none
+ */
+static inline void
+iciallu(void)
+{
+    __asm__ __volatile__(
+        "mcr    p15, 0, %0, c7, c5, 0\n\t"
+        : : "r" (0) : "memory"
+        );
+}
+
+/**
+ * @brief Data cache line clean by VA to PoC
+ *
+ * Allows for the DCCMVAC instruction to be placed in C code.  It will
+ * clean the indicated cache line.  That is, if the cache line is "dirty"
+ * it will be written back to DRAM but the data will remain in the dCache.
+ *
+ * The "clean" is done to the point of coherence in the cache hierarchy.
+ *
+ * @param[in] addr Virtual address of the cache line in the dCache to
+ * be invalidated.
+ *
+ * @return none
+ */
+static inline void
+dccmvac(uint32_t addr)
+{
+    __asm__ __volatile__(
+        "mcr    p15, 0, %0, c7, c10, 1\n\t"
+        : : "r" (addr) : "memory"
+        );
+}
+
+/**
+ * @brief Data cache line clean by VA to PoU
+ *
+ * Allows for the DCCMVAU instruction to be placed in C code.  It will
+ * clean the indicated cache line.  That is, if the cache line is "dirty"
+ * it will be written back to DRAM but the data will remain in the dCache.
+ *
+ * The "clean" is done to the point of unification in the cache hierarchy.
+ *
+ * @param[in] addr Virtual address of the cache line in the dCache to
+ * be cleaned.
+ *
+ * @return none
+ */
+static inline void
+dccmvau(uint32_t addr)
+{
+    __asm__ __volatile__(
+        "mcr    p15, 0, %0, c7, c11, 1\n\t"
+        : : "r" (addr) : "memory"
+        );
+}
+
+/**
+ * @brief Data cache line invalidate by VA to PoC
+ *
+ * Allows for the DCIMVAC instruction to be placed in C code.  It will
+ * invalidate the indicated cache line.
+ *
+ * The invalidation is done to the point of coherence.
+ *
+ * @param[in] addr Virtual address of the cache line in the dCache to
+ * be invalidated.
+ *
+ * @return none
+ */
+static inline void
+dcimvac(uint32_t addr)
+{
+    __asm__ __volatile__(
+        "mcr    p15, 0, %0, c7, c6, 1\n\t"
+        : : "r" (addr) : "memory"
+        );
+}
+
+/**
+ * @brief Data cache line clean and invaliate by VA to PoC
+ *
+ * Allows for the DCCIMVAC instruction to be placed in C code.  It will first
+ * clean the indicated cache line (e.g. if the line is "dirty" it will be
+ * written out to DRAM) before having the cache line invalidated (e.g. removed)
+ * from the dCache.
+ *
+ * This operation is performed to the point of coherence.
+ *
+ * @param[in] addr Virtual address of the cache line in the dCache to be
+ * cleaned and then invalidated.
+ *
+ * @return none
+ */
+static inline void
+dccimvac(uint32_t addr)
+{
+    __asm__ __volatile__(
+        "mcr    p15, 0, %0, c7, c14, 1\n\t"
+        : : "r" (addr) : "memory"
+        );
+}
+
+/**
+ * @brief Invalidate all data caches
+ *
+ * Allows for the DCIVALL instruction to be placed in C code.  It will cause
+ * all data caches to be invalidated.
+ *
+ * @return none
+ */
+static inline void
+dcivall(void)
+{
+    __asm__ __volatile__(
+        "mcr p15, 0, %0, c15, c5, 0\n\t"
+        : : "r" (0) : "memory"
+        );
+}
+
+/**
+ * @brief Data cache line clean by set/way
+ *
+ * Allows for the DCCSW instruction to be placed in C code.  It will cause
+ * the cache line specified by the set_way parameter to be cleaned (e.g. if
+ * the cache line is dirty, it will be written to DRAM).
+ *
+ * @param[in] set_way
+ * @parblock
+ * This is the set and way in the cache that is to  be cleaned.
+ *
+ * Bits 31:30 specify the way in the dCache
+ *
+ * Bits 13:5 specify the set in the dCache
+ * @endparblock
+ *
+ * @return none
+ */
+static inline void
+dccsw(uint32_t set_way)
+{
+    __asm__ __volatile__(
+        "mcr    p15, 0, %0, c7, c10, 2\n\t"
+        : : "r" (set_way) : "memory"
+        );
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-exception.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-exception.h
new file mode 100644
index 0000000..7af121a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-exception.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2015-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__ARMV7_EXCEPTION_H
+#define CPU__ARMV7_EXCEPTION_H
+#define FSP__CPU__ARMV7_EXCEPTION_H              1
+
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+_Pragma("coverity compliance block(include) \
+         (deviate MISRA_C_2012_Rule_20_10 \"Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx\") \
+         (deviate MISRA_C_2012_Rule_2_5 \"Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx\")")
+#endif
+#define DATA_ABORT 0
+#define PREFETCH_ABORT 1
+#define UNDEFINED_INSTRUCTION 2
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+_Pragma("coverity compliance end_block(include) \
+         MISRA_C_2012_Rule_20_10 MISRA_C_2012_Rule_2_5")
+#endif
+
+#ifndef __ASSEMBLER__
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+struct armv7_exception_frame {
+        uint32_t sp;
+        uint32_t lr;
+        uint32_t spsr;
+        uint32_t r0;
+        uint32_t r1;
+        uint32_t r2;
+        uint32_t r3;
+        uint32_t r4;
+        uint32_t r5;
+        uint32_t r6;
+        uint32_t r7;
+        uint32_t r8;
+        uint32_t r9;
+        uint32_t r10;
+        uint32_t r11;
+        uint32_t r12;
+        uint32_t pc;
+};
+
+void armv7_exception(uint32_t type, struct armv7_exception_frame *frame);
+
+typedef struct {
+    uint32_t                            type;
+    struct armv7_exception_frame        *frame;
+    uint32_t                            dfar;
+    uint32_t                            dfsr;
+    uint32_t                            adfsr;
+    uint32_t                            ifar;
+    uint32_t                            ifsr;
+    uint32_t                            aifsr;
+} armv7_exception_t;
+
+
+void exception_hook(const armv7_exception_t * const exception);
+
+#endif /* !defined __ASSEMBLER__ */
+
+#endif /* !defined CPU__ARMV7_EXCEPTION_H */
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-mpu-asm-static-hdr.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-mpu-asm-static-hdr.h
new file mode 100644
index 0000000..5c80e7e
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-mpu-asm-static-hdr.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file provides the interfaces for the SafeRTOS MPU functions for
+ * ARMv7 CPUs (notably the Cortex R5)
+ */
+#ifndef CPU__ARMV7_MPU_ASM_STATIC_HDR_H
+#define CPU__ARMV7_MPU_ASM_STATIC_HDR_H
+#define FSP__CPU__ARMV7_MPU_ASM_STATIC_HDR_H    1
+
+/*
+ * Offsets in mpuParameters structure.  These *must* match
+ * the structure layout.
+ */
+#define MPU_INDEX_OFFSET        #8      // offset of index field
+#define MPU_BASE_OFFSET         #16     // offset of base field
+
+/*
+ * Length of the mpuParameters structure.  It *must* match the
+ * structure layout.
+ */
+#define MPU_PARM_LENGTH         #28     // number of bytes
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-mpu-regs.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-mpu-regs.h
new file mode 100644
index 0000000..be37a7a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-mpu-regs.h
@@ -0,0 +1,364 @@
+/*
+ * Copyright (c) 2015-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__ARMV7_MPU_REGS_H
+#define CPU__ARMV7_MPU_REGS_H
+#define FSP__CPU__ARMV7_MPU_REGS_H               1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/nvrm_drf.h>
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <cpu/armv7-regs.h>
+#include <cpu/armv7-mpu.h>
+#include <cpu/built-ins.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__NVRM_DRF_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_REGS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_MPU_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__BUILT_INS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file armv7-mpu-regs.h
+ * @brief Functions that provide access to MPU specific registers.
+ */
+
+/**
+ * @brief Read MPU Region Number Register
+ *
+ * Returns the contents of the MPU Region number register.  This register
+ * selects the particular MPU region registers will be accessed.
+ *
+ * @pre None
+ *
+ * @return MPU Region Number Register
+ */
+static inline uint32_t
+r5mpu_rd_rgnr(void)
+{
+    uint32_t    rgnr;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__("mrc p15, 0, %0, c6, c2, 0\n\t" : "=r" (rgnr));
+
+    return rgnr;
+}
+
+/**
+ * @brief Write MPU Region Number Register
+ *
+ * Writes the contents of the MPU Region Number Register.  This register
+ * selects which MPU region registers will be accessed.
+ *
+ * @pre None
+ *
+ * @param[in]   region  Region number to be written into the MPU Region
+ *                      Number Register.
+ *
+ * @return None
+ */
+static inline void
+r5mpu_wr_rgnr(uint32_t region)
+{
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__("mcr p15, 0, %0, c6, c2, 0\n\t" : : "r" (region));
+}
+
+/**
+ * @brief Read MPU Region Base Address Register
+ *
+ * Reads the contents of the MPU Region Base Address Register.  This register
+ * must have been previously selected by writing to the MPU Region Number
+ * Register in order to select the correct region.
+ *
+ * @pre None
+ *
+ * @return Contents of the MPU Region Base Address Register
+ */
+static inline uint32_t
+r5mpu_rd_bar(void)
+{
+    uint32_t    bar;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__("mrc p15, 0, %0, c6, c1, 0\n\t" : "=r" (bar));
+
+    return bar;
+}
+
+/**
+ * @brief Write MPU Region Base Address Register
+ *
+ * Writes the contents of the MPU Region Base Address Register.  This register
+ * must have been previously selected by writing to the MPU Region Number
+ * Register in order to select the correct region.
+ *
+ * @pre None
+ *
+ * @param[in]   bar  Base Address that is to be written into the prevously
+ *                   selected MPU region.
+ *
+ * @return None
+ */
+static inline void
+r5mpu_wr_bar(uint32_t bar)
+{
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__("mcr p15, 0, %0, c6, c1, 0\n\t" : : "r" (bar));
+}
+
+/**
+ * @brief Read MPU Region Size and Enable Register
+ *
+ * Reads the contents of the MPU Region Size and Enable Register.  This register
+ * must have been previously selected by writing to the MPU Region Number
+ * Register in order to select the correct region.
+ *
+ * @pre None
+ *
+ * @return Contents of the MPU Region Size and Enable Register
+ */
+static inline uint32_t
+r5mpu_rd_size(void)
+{
+    uint32_t    size;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__("mrc p15, 0, %0, c6, c1, 2\n\t" : "=r" (size));
+
+    return size;
+}
+
+/**
+ * @brief Write MPU Region Size and Enable Register
+ *
+ * Writes the contents of the MPU Region Size and Enable Register.  This register
+ * must have been previously selected by writing to the MPU Region Number
+ * Register in order to select the correct region.
+ *
+ * @pre None
+ *
+ * @param[in]   size  Size and enable that is to be written into the prevously
+ *                    selected MPU region.
+ *
+ * @return None
+ */
+static inline void
+r5mpu_wr_size(uint32_t size)
+{
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__("mcr p15, 0, %0, c6, c1, 2\n\t" : : "r" (size));
+}
+
+/**
+ * @brief Read MPU Region Access Control Register
+ *
+ * Reads the contents of the MPU Region Access Control Register.  This register
+ * must have been previously selected by writing to the MPU Region Number
+ * Register in order to select the correct region.
+ *
+ * @pre None
+ *
+ * @return Contents of the MPU Region Access Control Register
+ */
+static inline uint32_t
+r5mpu_rd_access(void)
+{
+    uint32_t    access;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__("mrc p15, 0, %0, c6, c1, 4\n\t" : "=r" (access));
+
+    return access;
+}
+
+/**
+ * @brief Write MPU Region Access Control Register
+ *
+ * Writes the contents of the MPU Region Access Control Register.  This register
+ * must have been previously selected by writing to the MPU Region Number
+ * Register in order to select the correct region.
+ *
+ * @pre None
+ *
+ * @param[in]   access  Access Control that is to be written to the previously
+ *                      selected MPU region.
+ *
+ * @return None
+ */
+static inline void
+r5mpu_wr_access(uint32_t access)
+{
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__("mcr p15, 0, %0, c6, c1, 4\n\t" : : "r" (access));
+}
+
+/**
+ * @brief Configures a specific MPU region
+ *
+ * Sets the indicated MPU region's registers:
+ *   - MPU Region Base Address
+ *   - MPU Region Size and Enable
+ *   - MPU Region Access Control
+ *
+ * The values passed as arguments to this function must be according to
+ * the values specified in Section 4.3.21 of the ARM Cortex R5 Technical
+ * Reference Manual.
+ *
+ * @pre MPU region being configured must have been disabled prior to using
+ *      this function.
+ *
+ * @param[in]   region  MPU region number to be configured
+ * @param[in]   base    base address of the region
+ * @param[in]   size    encoded size of the region
+ * @param[in]   access  access permissions for the region
+ *
+ * @return None
+ */
+static inline void
+r5mpu_region_config(uint32_t region,
+                    uint32_t base,
+                    uint32_t size,
+                    uint32_t access)
+{
+    r5mpu_wr_rgnr(region);
+    r5mpu_wr_bar(base);
+    r5mpu_wr_access(access);
+    r5mpu_wr_size(size);
+}
+
+/**
+ * @brief Disable a specific MPU region
+ *
+ * This function will disable the indicated MPU region.  To re-enable the
+ * region, r5MPU_region_config() must be called specifying all of the values.
+ *
+ * @pre None
+ *
+ * @param[in]  region  MPU region number to be disabled.
+ *
+ * @return None
+ */
+static inline void
+r5mpu_region_disable(uint32_t region)
+{
+    r5mpu_wr_rgnr(region);
+    r5mpu_wr_size(0UL);
+}
+
+/**
+ * @brief Enable the MPU
+ *
+ * This function will enable the MPU.  The various MPU regions must have
+ * been setup prior to this function being called.
+ *
+ * @pre None
+ *
+ * @return None
+ */
+static inline void
+r5mpu_enable(void)
+{
+    uint32_t sctlr;
+
+    sctlr = rd_sctlr();
+    sctlr = NV_FLD_SET_DRF_NUM(R5, SCTLR, BR, 0U, sctlr);
+    sctlr = NV_FLD_SET_DRF_NUM(R5, SCTLR, M, 1U, sctlr);
+    wr_sctlr(sctlr);
+}
+
+/**
+ * @brief Disable the MPU
+ *
+ * This function will disable the MPU. This restores the MPU's default mapping.
+ * Careful attention must be paid to code layout so that execution can
+ * successfully continue after this call executes.
+ *
+ * @pre None
+ *
+ * @return None
+ */
+static inline void
+r5mpu_disable(void)
+{
+    uint32_t sctlr;
+
+    sctlr = rd_sctlr();
+    sctlr = NV_FLD_SET_DRF_NUM(R5, SCTLR, M, 0U, sctlr);
+    wr_sctlr(sctlr);
+}
+
+/**
+ * @brief Convert a size to an MPU encoding
+ *
+ * Convert a region size in bytes to the MPU's register encoding of the region
+ * size. The supplied number of bytes must have a single bit set, and be at
+ * least 32. The intention is for this function call to result in a compile-
+ * time constant where possible, hence its presence in the header file.
+ *
+ * @pre None
+ *
+ * @param[in]  size_bytes  The number of bytes to be covered by the region
+ *
+ * @return MPU encoded size value
+ */
+static inline uint32_t
+r5mpu_size(uint32_t size_bytes)
+{
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    return 31UL - arm_builtin_clz(size_bytes - 1U);
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-mpu-safertos-priv.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-mpu-safertos-priv.h
new file mode 100644
index 0000000..d21f16c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-mpu-safertos-priv.h
@@ -0,0 +1,228 @@
+/*
+ * Copyright (c) 2019-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__ARMV7_MPU_SAFERTOS_PRIV_H
+#define CPU__ARMV7_MPU_SAFERTOS_PRIV_H
+#define FSP__CPU__ARMV7_MPU_SAFERTOS_PRIV_H      1
+
+/* Compiler headers */
+#include <stddef.h>                  // for NULL
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>          // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>             // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <osa/rtos-task.h>           // for xTCB, portTaskHandleType
+#include <cpu/armv7-mpu-safertos.h>  // for mpuParameters_t, FSP__CPU__ARMV7...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_MPU_SAFERTOS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file armv7-mpu-safertos-priv.h
+ * @brief Internal functions for managing the MPU under SafeRTOS
+ *
+ * This file provides the interfaces for the SafeRTOS MPU functions for
+ * ARMv7 CPUs (notably the Cortex R5) that are used internally by the
+ * MPU driver code and should not be used by application code.
+ */
+
+/**
+ * @brief Restore a task's MPU regions
+ *
+ * This function restores the specified task's regions in that it
+ * programs the MPU as indicated by the array of region structures
+ * supplied.
+ *
+ * For performance reasons, this function is implemented in assembler
+ * and as a consequence any error checking should be performed prior
+ * to calling this function as it is not expected to do any validation
+ * checking.  That is, it will take the information contained in the
+ * supplied regions array and just write the appropriate values into
+ * the MPU.
+ *
+ * @pre MPU must be enabled via r5mpu_init().
+ * @pre The task's region array must be properly initialized by
+ *      calling r5mpu_task_region_init().
+ *
+ * @param[in]  task_regions  A pointer to an array of mpuParameter
+ *                           structures that contains exactly
+ *                           MPU_NTASK_REGIONS.
+ * @return None
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+void armv7_task_mpu_restore(mpuParameters_t *task_regions);
+
+/**
+ * @brief Disable the per-task MPU regions
+ *
+ * This function disables the per-task MPU regions. The regions
+ * to be disabled are passed in as an argument.
+ *
+ * @pre MPU must be enabled via r5mpu_init().
+ *
+ * @param[in]  task_regions  A point to an array of mpuParameter
+ *                           structures that contains exactly
+ *                           MPU_NTASK_REGIONS.
+ *
+ * @return None
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+void armv7_task_mpu_disable(mpuParameters_t *task_regions);
+
+#if !defined(safertosapiSVC_API_PORT_MAJOR_VERSION)
+/**
+ * @brief Application specific task switch handling
+ *
+ * This function is called by the context switch code in SafeRTOS.
+ * It will perform the necessary low level operations necessary to
+ * tear down the MPU mappings from the current task and set them up
+ * for the next task.
+ *
+ * @pre MPU must be enabled via r5mpu_init().
+ * @pre The task's region arrays must be properly initialized by
+ *      calling r5mpu_task_region_init().
+ *
+ * @param[in] currentTask  A valid task handle to the current task
+ *                         or NULL.
+ * @param[in] nextTask     A valid task handle to the next task
+ *                         or NULL.
+ *
+ * @return None
+ */
+void vApplicationTaskSwitch(const xTCB *pxTCBOfTaskSwitchedOut,
+                            const xTCB *pxTCBOfTaskSwitchedIn);
+#endif
+
+/**
+ * @brief Return a pointer to a task's TCB
+ *
+ * This function will, given a task handle, return a pointer to that
+ * task's TCB structure.
+ *
+ * @pre Task represended by xCurrentTaskHandle must have been created.
+ *
+ * @param[in] xCurrentTaskHandle Task handle of the task whose TCB
+ *                               pointer is to be returned.  The task
+ *                               handle is assumed to be valid as this
+ *                               function is called where the task handle
+ *                               is supplied from SafeRTOS.
+ *
+ * @return pointer to an xTCB structure for the given task.
+ */
+static inline xTCB *
+vPortTaskHandleToTCB(const portTaskHandleType xCurrentTaskHandle)
+{
+    xTCB        *pxTCB;
+
+    INLINE_RFD(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx");
+    pxTCB = (xTCB *)xCurrentTaskHandle;
+
+    return pxTCB;
+}
+
+/**
+ * @brief Return a pointer to a task's MPU regions
+ *
+ * This function will, given a task handle, return a pointer to that
+ * task's MPU parameter array.
+ *
+ * @pre Task represented by xCurrentTaskHandle must have been created.
+ *
+ * @param[in] xCurrentTaksHandle Task handle of the task whose MPU
+ *                               parameters are to be returned.  The
+ *                               task handle is assumed to be valid
+ *                               as this function is called where the
+ *                               task handle is supplied from SafeRTOS.
+ *
+ * @return pointer to the task's array of mpuParameter_t structures.  NULL
+ *         if the task has no per-task MPU regions.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+static inline mpuParameters_t * vPortTaskHandleToMPUPointer(const portTaskHandleType xCurrentTaskHandle)
+{
+    const xTCB          *pxTCB;
+
+    INLINE_RFD(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx");
+    pxTCB = (const xTCB *)xCurrentTaskHandle;
+
+    return (pxTCB == NULL) ? NULL : pxTCB->pxMPUParameters;
+}
+
+/**
+ * @brief Return the task's System Mode Setting
+ *
+ * This function will, given a task handle, return the value of the
+ * the task's system mode setting.
+ *
+ * @pre None
+ *
+ * @param[in] xCurrentTaskHandle Task handle of the task for which its
+ *                               system mode setting value is to be
+ *                               returned.  The task handle is assumed
+ *                               to be valid as this function is called
+ *                               from where the task handle has been
+ *                               supplied from SafeRTOS.
+ *
+ * @retval R5_PSR_MODE_SYSTEM    when the task is privileged
+ * @retval R5_PSR_MODE_USER      when the task is unprivileged
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+static inline portUInt32Type uxPortTaskSystemModeSetting(const portTaskHandleType xCurrentTaskHandle)
+{
+    const xTCB          *pxTCB;
+
+    INLINE_RFD(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx");
+    pxTCB = (const xTCB *)xCurrentTaskHandle;
+
+    return pxTCB->ulSystemModeSetting;
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-mpu-safertos.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-mpu-safertos.h
new file mode 100644
index 0000000..4005496
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-mpu-safertos.h
@@ -0,0 +1,328 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file provides the interfaces for the SafeRTOS MPU functions for
+ * ARMv7 CPUs (notably the Cortex R5)
+ */
+#ifndef CPU__ARMV7_MPU_SAFERTOS_H
+#define CPU__ARMV7_MPU_SAFERTOS_H
+#define FSP__CPU__ARMV7_MPU_SAFERTOS_H           1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/nvrm_drf.h>
+
+/* Module-specific FSP headers */
+#include <armv7-mpu.h>                                  /* Immune from CT_ASSERT protection */
+#include <cpu/armv7-mpu.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__NVRM_DRF_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_MPU_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file armv7-mpu-safertos.h
+ * @brief Definitions and interfaces to use the MPU under SafeRTOS
+ *
+ * This file provides definitions, data structures and interfaces that
+ * are necessary for an application to use the MPU driver.
+ */
+
+/**
+ * @brief Type for representing an MPU Region number
+ */
+typedef uint32_t        r5mpu_region_num_t;
+
+/**
+ * @brief Type for representing MPU Check Access for a region
+ *
+ * The values R5MPU_CHECK_* values (below) can be logical OR'd together
+ * to create the desired access for a region.
+ */
+typedef uint8_t         r5mpu_check_access_t;
+
+/**
+ * @brief No Privileged Access for a region.
+ */
+#define R5MPU_CHECK_PRIV_NONE   ((r5mpu_check_access_t)0x00U)
+
+/**
+ * Privileged Read Access for a region.
+ */
+#define R5MPU_CHECK_PRIV_READ   ((r5mpu_check_access_t)0x01U)
+
+/**
+ * @brief Privileged Write Access for a region.
+ */
+#define R5MPU_CHECK_PRIV_WRITE  ((r5mpu_check_access_t)0x02U)
+
+/**
+ * @brief No Unprivileged Access for a region.
+ */
+#define R5MPU_CHECK_USER_NONE   ((r5mpu_check_access_t)0x00U)
+
+/**
+ * @brief Unprivileged Read Access for a region.
+ */
+#define R5MPU_CHECK_USER_READ   ((r5mpu_check_access_t)0x04U)
+
+/**
+ * @brief Unprivileged Write Access for a region.
+ */
+#define R5MPU_CHECK_USER_WRITE  ((r5mpu_check_access_t)0x08U)
+
+/**
+ * @brief Privileged Read and Write Access for a region.
+ */
+#define R5MPU_CHECK_PRIV_RW     (R5MPU_CHECK_PRIV_READ | R5MPU_CHECK_PRIV_WRITE)
+
+/**
+ * @brief Unprivileged Read and Write Access for a region.
+ */
+#define R5MPU_CHECK_USER_RW     (R5MPU_CHECK_USER_READ | R5MPU_CHECK_USER_WRITE)
+
+/**
+ * @brief Type representing the flags in mpuParameters structure
+ */
+typedef uint8_t         r5mpu_flags_t;
+
+/**
+ * @brief Region is valid
+ */
+#define R5MPU_FL_VALID          ((r5mpu_flags_t)0x01U)
+
+/**
+ * @brief The size field in mpuParameters structure contains a size.
+ */
+#define R5MPU_FL_SIZE           ((r5mpu_flags_t)0x02U)
+
+/**
+ * The size field in mpuParameters structure contains an ending address.
+ * During r5mpu_init() and r5mpu_task_region_init(), these fields will
+ * be converted to a size by subtracting the base field from the size
+ * field.
+ */
+#define R5MPU_FL_END            ((r5mpu_flags_t)0x04U)
+
+/**
+ * Indicate that the structure has been initialized.
+ */
+#define R5MPU_FL_INIT           ((r5mpu_flags_t)0x80U)
+
+/**
+ * @brief MPU parameters structure
+ *
+ * This structure contains the information that is necessary for
+ * initializing the MPU and managing per-task MPU regions.  This
+ * structure is generally used in arrays of either MPU_NGLOBAL_REGIONS
+ * (for mpu_global_regions) or MPU_NTASK_REGIONS for the per-task
+ * MPU regions.
+ * @flags         The flags that indicate the state of the structure.
+ * @permissions   The permissions that will be used for validating if a
+ *                range is allowed to access a region.
+ * @task_data     per-task data that can be supplied. This is opaque to the
+ *                MPU code.
+ * @index         The MPU region number that the region corresponds to.
+ * @size          The size of the region if R5MPU_FL_SIZE is set in flags.
+ *                The end address of the region if R5MPU_FL_END is set in flags.
+ * @base          The base address of the region.
+ * @access        The access and memory type of the region.  See armv7-mpu.h
+ *                for the acceptable values in this field.
+ * @encoded_size  The encoded size of the MPU region.  It is of a form that
+ *                is directly usable by the MPU hardware.  This field will
+ *                be filled in/overwritten by calls to r5mpu_init() or
+ *                r5mpu_task_region_init().
+ */
+typedef struct mpuParameters {
+    r5mpu_flags_t       flags;          // flags on how to interprete fields
+    r5mpu_check_access_t permissions;   // access for checking permissions
+    uint8_t             pad[2];         // padding to align next field
+    void                *task_data;     // per task data (opaque to MPU code)
+    r5mpu_region_num_t  index;          // region index
+    uint32_t            size;           // size (in bytes) of region
+    // the following fields must be kept in this order to allow for
+    // fast programming of the MPU during a context switch.  They
+    // must also be at the end of the structure.
+    uint32_t            base;           // base address for region
+    uint32_t            access;         // access permissions
+    uint32_t            encoded_size;   // encoded size - direct set of MPU
+} mpuParameters_t;
+
+/**
+ * @brief Global MPU regions
+ *
+ * The global MPU regions that are common across all tasks.  It must
+ * be initialized (usually staticlly) prior to calling r5mpu_init().
+ */
+extern mpuParameters_t  mpu_global_regions[MPU_NGLOBAL_REGIONS];
+
+/**
+ * @brief Initialize a Task's MPU region
+ *
+ * This function will initialize the supplied task's MPU region so that
+ * it is useable by the context switch and copy check code.
+ *
+ * @pre r5mpu_init must have already been called to set up the global
+ *      regions.
+ *
+ * @param[in]  task_regions   A pointer to an array of mpuParameters structures
+ *                            that contains MPU_NTASK_REGIONS elements, that
+ *                            represent the MPU regions for a specific task
+ *
+ * @return None
+ */
+void r5mpu_task_region_init(mpuParameters_t *task_mpu_regions);
+
+/**
+ * @brief Initialize Global MPU state
+ *
+ * This function will initialize the MPU for use.  It will perform the
+ * following operations:
+ * - finish initializing the global MPU regions contained in mpu_global_regions.
+ * - initialize all of the MPU regions in the hardware according to the
+ *   contents of mpu_global_regions and disabling any per-task regions.
+ * - enabling the MPU hardware
+ *
+ * @pre mpu_global_regions must have at least one region defined that is
+ *      not disabled.
+ *
+ * @return None
+ */
+void r5mpu_init(void);
+
+/**
+ * @brief Initialize an MPU region structure
+ *
+ * This function assumes that most of the structure has already been
+ * initialized (more than likely statically).  This fills in any remaining
+ * fields in the data structure from the information already present.
+ *
+ * @pre If set_mpu is true, then the R5's MPU must be disabled.  If set_mpu
+ *      is false, then there is no requirement on the state of the R5's MPU.
+ *
+ * @param[in]  region    pointer to an mpuParameters structure
+ * @param[in]  set_mpu   boolean that indicates if the actual MPU region
+ *                       in the R5 should be set or if this is only used
+ *                       to initialize the mpuParameters structure.
+ *
+ * @return None
+ */
+void r5mpu_region_init(mpuParameters_t *const region,
+                       bool set_mpu);
+
+/**
+ * @brief Return the number of MPU regions
+ *
+ * Returns the number of MPU regions that are supported by the R5 CPU.
+ *
+ * @return number of MPU regions supported by the R5 CPU.
+ */
+static inline uint32_t
+r5mpu_region_count(void)
+{
+    uint32_t        mpuir;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 4\n\t" : "=r" (mpuir));
+
+    return NV_DRF_VAL(R5, MPUIR, DREGION, mpuir);
+}
+
+/**
+ * @brief R5 MPU not initialized hook
+ *
+ * This is a default hook that can be overridden by the application
+ * to handle cases when one of the MPU functions is called when the
+ * MPU has not been initialized.
+ *
+ * @return None
+ */
+void r5mpu_not_initialized_hook(void);
+
+/**
+ * @brief R5 MPU re-initialization attempted
+ *
+ * This is a default hook that can be overridden by the application
+ * to handle cases when re-initialization of the MPU is attempted.
+ *
+ * @param[in]  region  pointer to region that was already initialized.
+ *                     NULL indicates that r5mpu_init was called again.
+ *
+ * @return None
+ */
+void r5mpu_reinitialize_hook(const mpuParameters_t * const region);
+
+/**
+ * @brief Application specific context switch callout
+ *
+ * This function will be called by the MPU context switch code to allow
+ * for the application to perform some specific work prior to the MPU
+ * switch occuring.
+ *
+ * @param [in]  oldTaskData     pointer to opaque data that is contained
+ *                              in the MPU data structure for the task being
+ *                              switched away from
+ * @param [in]  newTaskData     pointer to opaque data that is conteined
+ *                              in the MPU data structure for the task being
+ *                              switched to
+ *
+ * @return None
+ */
+void vApplicationTaskContextSwitchHook(const void *oldTaskData,
+                                       const void *newTaskData);
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-mpu.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-mpu.h
new file mode 100644
index 0000000..ad52054
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-mpu.h
@@ -0,0 +1,258 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__ARMV7_MPU_H
+#define CPU__ARMV7_MPU_H
+#define FSP__CPU__ARMV7_MPU_H                    1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/bitops.h>
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file armv7-mpu.h
+ * @brief Defines for the register layout of the MPU
+ */
+
+/**
+ * @brief R5 Processor Modes
+ *
+ * @macro-title R5 Processor Modes
+ */
+#define R5_PSR_MODE_USER        0x10UL  // user mode
+#define R5_PSR_MODE_FIQ         0x11UL  // processing an FIQ
+#define R5_PSR_MODE_IRQ         0x12UL  // processing an IRQ
+#define R5_PSR_MODE_SUPER       0x13UL  // supervisor mode
+#define R5_PSR_MODE_ABORT       0x17UL  // processing an abort
+#define R5_PSR_MODE_UNDEF       0x1BUL  // undefined exception
+#define R5_PSR_MODE_SYSTEM      0x1FUL  // system mode
+
+#define R5_PSR_MODE_MASK        0x1FUL  // mask for extracting processor mode
+
+/**
+ * @brief CPSR register bit-masks
+ *
+ * @macro-title CPSR bit fields
+ */
+#define R5_CPSR_IRQ_SHIFT 7U
+#define R5_CPSR_IRQ_MASK  (1U << R5_CPSR_IRQ_SHIFT)
+
+#define R5_CPSR_FIQ_SHIFT 6U
+#define R5_CPSR_FIQ_MASK  (1U << R5_CPSR_FIQ_SHIFT)
+
+/**
+ * @brief MPU Region Memory Attributes
+ *
+ * MPU Region Memory Attributes
+ *
+ * See section 4.3.21 of the ARM Cortex R5 Technical Reference Manual for
+ * additional descriptions of these bits and what they do.
+ *
+ * The following bits define how the R5 will access a region of memory that
+ * has been described by an individual MPU region.
+ *
+ * These bits are used in the setting of an MPU region's access control
+ * register.
+ */
+#define R5_DRACR_TEX_SHIFT      3
+#define R5_DRACR_S_SHIFT        2
+#define R5_DRACR_C_SHIFT        1
+#define R5_DRACR_B_SHIFT        0
+
+/**
+ * @brief Strongly ordered memory
+ */
+#define R5_DRACR_STRONGLY_ORDERED               (0UL << R5_DRACR_TEX_SHIFT)
+
+/**
+ * @brief Shareable device memory
+ */
+#define R5_DRACR_SHAREABLE_DEV                  ((0UL << R5_DRACR_TEX_SHIFT) | \
+                                                BIT(R5_DRACR_B_SHIFT))
+
+/**
+ * @brief Device memory
+ */
+#define R5_DRACR_DEV                            (2UL << R5_DRACR_TEX_SHIFT)
+
+/**
+ * @brief Uncached Shareable memory
+ */
+#define R5_DRACR_NORMAL_UNCACHED_SHAREABLE      (1UL << R5_DRACR_TEX_SHIFT) | \
+                                                BIT(R5_DRACR_S_SHIFT)
+
+/**
+ * @brief Uncached memory
+ */
+#define R5_DRACR_NORMAL_UNCACHED                (1UL << R5_DRACR_TEX_SHIFT)
+
+/**
+ * @brief Cached shareable memory
+ */
+#define R5_DRACR_NORMAL_CACHED_SHAREABLE        ((1UL << R5_DRACR_TEX_SHIFT) | \
+                                                BIT(R5_DRACR_S_SHIFT) | \
+                                                BIT(R5_DRACR_C_SHIFT) | \
+                                                BIT(R5_DRACR_B_SHIFT))
+
+/**
+ * @brief Cached memory
+ */
+#define R5_DRACR_NORMAL_CACHED                  ((1UL << R5_DRACR_TEX_SHIFT) | \
+                                                BIT(R5_DRACR_C_SHIFT) | \
+                                                BIT(R5_DRACR_B_SHIFT))
+
+/**
+ * @brief MPU Region Memory Access
+ *
+ * See section 4.3.21 of the ARM Cortex R5 Technical Reference Manual for
+ * additional descriptions of these bits and what they do.
+ *
+ * The following define the access permissions for a region of memory that
+ * has been described by an individual MPU region.
+ *
+ * These bits are used in the setting of an MPU region's access control
+ * register.
+ */
+/**
+ * @brief No exectute
+ */
+#define R5_DRACR_XN             (1UL << 12)
+
+#define R5_DRACR_AP_SHIFT       8
+#define R5_DRACR_AP_MASK        (7UL << R5_DRACR_AP_SHIFT)
+
+/**
+ * @brief No access allowed
+ */
+#define R5_DRACR_AP_NONE        (0UL << R5_DRACR_AP_SHIFT)
+
+/**
+ * @brief Privileged Read/Write, No User access
+ */
+#define R5_DRACR_AP_PRIV_RW     (1UL << R5_DRACR_AP_SHIFT)
+
+/**
+ * @brief User Read Only, Privileged Read/Write
+ */
+#define R5_DRACR_AP_USER_RO     (2UL << R5_DRACR_AP_SHIFT)
+
+/**
+ * @brief User Read/Write, Privileged Read/Write
+ */
+#define R5_DRACR_AP_USER_RW     (3UL << R5_DRACR_AP_SHIFT)
+
+/**
+ * @brief Privileged Read Only, No User access
+ */
+#define R5_DRACR_AP_PRIV_RO     (5UL << R5_DRACR_AP_SHIFT)
+
+/**
+ * @brief Privileged Read Only, User Read Only
+ */
+#define R5_DRACR_AP_ALL_RO      (6UL << R5_DRACR_AP_SHIFT)
+
+/*
+ * When debugging with DS5 and DStream, it is necessary to
+ * have the code reagions be writable since the debugger
+ * needs to insert breakpoint instructions into the code.
+ */
+#if defined(DS5_DEBUG_ENABLE) && (DS5_DEBUG_ENABLE == 1)
+#define R5_DRACR_AP_USER_CODE   R5_DRACR_AP_USER_RW
+#define R5_DRACR_AP_PRIV_CODE   R5_DRACR_AP_PRIV_RW
+#else
+/**
+ * @brief User Code Access - synonym for User Read Only
+ */
+#define R5_DRACR_AP_USER_CODE   R5_DRACR_AP_USER_RO
+
+/**
+ * @brief Privileged Code Access - synonym for Privileged Read Only
+ */
+#define R5_DRACR_AP_PRIV_CODE   R5_DRACR_AP_PRIV_RO
+#endif
+
+/*
+ * Some synonyms for memory access
+ */
+#define R5_DRACR_AP_RW          R5_DRACR_AP_USER_RW
+#define R5_DRACR_AP_RO          R5_DRACR_AP_USER_RO
+
+#define R5_MPUIR_0_DREGION_RANGE        15:8
+#define R5_MPUIR_0_DREGION_MSB          MK_SHIFT_CONST(15)
+#define R5_MPUIR_0_DREGION_LSB          MK_SHIFT_CONST(8)
+
+#define R5_DRSR_0_RSIZE_RANGE           5:1
+#define R5_DRSR_0_RSIZE_MSB             MK_SHIFT_CONST(5)
+#define R5_DRSR_0_RSIZE_LSB             MK_SHIFT_CONST(1)
+
+#define R5_DRSR_0_EN_RANGE              0:0
+#define R5_DRSR_0_EN_MSB                MK_SHIFT_CONST(0)
+#define R5_DRSR_0_EN_LSB                MK_SHIFT_CONST(0)
+
+#define R5_SCTLR_0_BR_RANGE             17:17
+#define R5_SCTLR_0_BR_MSB               MK_SHIFT_CONST(17)
+#define R5_SCTLR_0_BR_LSB               MK_SHIFT_CONST(17)
+
+#define R5_SCTLR_0_M_RANGE              0:0
+#define R5_SCTLR_0_M_MSB                MK_SHIFT_CONST(0)
+#define R5_SCTLR_0_M_LSB                MK_SHIFT_CONST(0)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-pmu-regs.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-pmu-regs.h
new file mode 100644
index 0000000..0b1c56c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-pmu-regs.h
@@ -0,0 +1,694 @@
+/*
+ * Copyright (c) 2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__ARMV7_PMU_REGS_H
+#define CPU__ARMV7_PMU_REGS_H
+#define FSP__CPU__ARMV7_PMU_REGS_H               1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/nvrm_drf.h>
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <misc/bitops.h>
+
+/* Module-specific FSP headers */
+#include <cpu/armv7-regs.h>
+#include <cpu/built-ins.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__NVRM_DRF_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__BUILT_INS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file armv7-pmu-regs.h
+ * @brief Functions that provide access to PMU specific registers.
+ */
+
+/*
+ * R5 PMU events
+ */
+#define ARMV7_PMU_SW_INCR               0x00
+#define ARMV7_PMU_ICACHE_MISS           0x01
+#define ARMV7_PMU_DCACHE_MISS           0x03
+#define ARMV7_PMU_DCACHE_ACCESS         0x04
+#define ARMV7_PMU_DATA_READ_EXEC        0x06
+#define ARMV7_PMU_DATA_WRITE_EXEC       0x07
+#define ARMV7_PMU_INSTR_EXEC            0x08
+#define ARMV7_PMU_DUAL_ISSUE_EXEC       0x5E
+#define ARMV7_PMU_EXCEPTION_TAKEN       0x09
+#define ARMV7_PMU_EXCEPTION_RETURN      0x0A
+#define ARMV7_PMU_CONTEXT_ID_CHANGED    0x0B
+#define ARMV7_PMU_PC_CHANGED            0x0C
+#define ARMV7_PMU_BRANCH_IMMEDIATE      0x0D
+#define ARMV7_PMU_PROC_RETURN           0x0E
+#define ARMV7_PMU_UNALIGNED_ACCESS      0x0F
+#define ARMV7_PMU_BRANCH_NOT_PREDICTED  0x10
+#define ARMV7_PMU_CYCLE_COUNT           0x11
+#define ARMV7_PMU_BRANCH_PREDICTION     0x12
+#define ARMV7_PMU_STALL_INST_BUFFER     0x40
+#define ARMV7_PMU_STALL_DATA_DEPEND     0x41
+#define ARMV7_PMU_DCACHE_WRITE_BACK     0x42
+#define ARMV7_PMU_EXT_MEM_REQ           0x43
+#define ARMV7_PMU_STALL_LSU_BUSY        0x44
+#define ARMV7_PMU_STORE_BUFF_DRAIN      0x45
+#define ARMV7_PMU_FIQ_DISABLED_CYCLES   0x46
+#define ARMV7_PMU_IRQ_DISABLED_CYCLES   0x47
+#define ARMV7_PMU_ETMEXTOUT0            0x48
+#define ARMV7_PMU_ETMEXTOUT1            0x49
+#define ARMV7_PMU_ICACHE_TAG_RAM_ERR    0x4A
+#define ARMV7_PMU_ICACHE_DATA_RAM_ERR   0x4B
+#define ARMV7_PMU_DCACHE_DIRTY_ERR      0x4C
+#define ARMV7_PMU_DCACHE_DATA_RAM_ERR   0x4D
+#define ARMV7_PMU_TCM_PREFETCH_ECC      0x4E
+#define ARMV7_PMU_TCU_LDSTORE_ECC       0x4F
+#define ARMV7_PMU_ST_BUFF_MERGE         0x50
+#define ARMV7_PMU_LSU_STALL_FULL_ST_BUFF        0x51
+#define ARMV7_PMU_LSU_STALL_FULL_ST_Q   0x52
+#define ARMV7_PMU_IDIV_EXEC             0x53
+#define ARMV7_PMU_IDIV_STALL            0x54
+#define ARMV7_PMU_PLD_LINEFILL          0x55
+#define ARMV7_PMU_PLD_LINEFILL_SHORTAGE 0x56
+#define ARMV7_PMU_NON_CACHE_AXI         0x57
+#define ARMV7_PMU_ICACHE_ACCESS         0x58
+#define ARMV7_PMU_ST_BUFF_TWO_SLOTS     0x59
+#define ARMV7_PMU_DUAL_ISSUE_A          0x5A
+#define ARMV7_PMU_DUAL_ISSUE_B1_B2_F2_F2D       0x5B
+#define ARMV7_PMU_DUAL_ISSUE_OTHER      0x5C
+#define ARMV7_PMU_DOUBLE_FLOAT_INST     0x5D
+#define ARMV7_PMU_DCACHE_DATA_ECC       0x60
+#define ARMV7_PMU_DACHE_TAG_ECC         0x61
+#define ARMV7_PMU_LIVELOCK              0x62
+#define ARMV7_PMU_ATCM_MULTI_BIT_ECC    0x64
+#define ARMV7_PMU_B0TCM_MULTI_BIT_ECC   0x65
+#define ARMV7_PMU_B1TCM_MULTI_BIT_ECC   0x66
+#define ARMV7_PMU_ATCM_SINGLE_BIT_ECC   0x67
+#define ARMV7_PMU_B0TCM_SINGLE_BIT_ECC  0x68
+#define ARMV7_PMU_B1TCM_SINGLE_BIT_ECC  0x69
+#define ARMV7_PMU_TCM_CORR_ECC_LD_ST    0x6A
+#define ARMV7_PMU_TCM_CORR_ECC_PREFETCH 0x6B
+#define ARMV7_PMU_TCM_FATAL_ECC_AXI     0x6C
+#define ARMV7_PMU_TCM_CORR_ECC_AXI      0x6D
+#define ARMV7_PMU_CORRECTABLE_EVENTS    0x6E
+#define ARMV7_PMU_FATAL_EVENTS          0x6F
+#define ARMV7_PMU_CORR_BUS_FAULTS       0x70
+#define ARMV7_PMU_FATAL_BUS_FAULTS      0x71
+#define ARMV7_PMU_DCACHE_ACCESSES       0x72
+#define ARMV7_PMU_DCACHE_INVALIDATE     0x73
+#define ARMV7_PMU_CYCLE_COUNT2          0xFF
+
+/*****************************************************
+ * Macros for accessing fields in the PMCR register
+ *****************************************************/
+/*
+ * Get the Implementer code from the PMCR
+ */
+#define ARMV7_PMCR_GET_IMP(pmcr)        (EXTRACT(pmcr, 31, 24))
+
+/*
+ * Get the ID code from the PMCR
+ */
+#define ARMV7_PMCR_GET_IDCODE(pmcr)     (EXTRACT(pmcr, 23, 16))
+
+/*
+ * Get the number of PMU counters implemented
+ */
+#define ARMV7_PMCR_GET_N(pmcr)          (EXTRACT(pmcr, 15, 11))
+
+#define ARMV7_PMCR_DP   BIT(5)          // disable PMCCNTR
+#define ARMV7_PMCR_X    BIT(4)          // enable export of events to event bus
+#define ARMV7_PMCR_D    BIT(3)          // count ever 64th processor cycle
+#define ARMV7_PMCR_C    BIT(2)          // cycle counter reset
+#define ARMV7_PMCR_P    BIT(1)          // event counter reset
+#define ARMV7_PMCR_E    BIT(0)          // enable all counters
+
+
+/*****************************************************
+ * Macros for accessing fields in the following registers
+ *      PMCNTENSET
+ *      PMCNTENCLR
+ *      PMOVSR
+ *      PMSWINC
+ *      PMINTENSET
+ *      PMINTENCLR
+ *****************************************************/
+#define ARMV7_PMCNT_C   BIT(31)         // cycle counter
+#define ARMV7_PMCNT_P2  BIT(2)          // counter 2 enable
+#define ARMV7_PMCNT_P1  BIT(1)          // counter 1 enable
+#define ARMV7_PMCNT_P0  BIT(0)          // counter 0 enable
+
+
+/*****************************************************
+ * Macros for accessing fields in the PMSELR register
+ *****************************************************/
+#define ARMV7_PMSEL_GET(selr)   (EXTRACT(selr, 4, 0))
+#define ARMV7_PMSEL_MASK        MASK(4, 0)
+
+
+/*****************************************************
+ * Macros for accessing fields in the PMXEVTYPER registers
+ *****************************************************/
+#define ARMV7_EVENT_SEL_GET(xevselr)    (EXTRACT(xevselr, 7, 0))
+#define ARMV7_EVENT_SEL_SET(xevselr, sel)       (INSERT(xevselr, 7, 0, sel)
+
+
+/*****************************************************
+ * Macros for accessing fields in the PMUSERENR register
+ *****************************************************/
+#define ARMV7_USER_EN   BIT(0)          // enable PMU access from USER mode
+
+/**
+ * @brief Read Performance Monitor Control Register
+ *
+ * This function returns the current contents of the PMCR.
+ *
+ * Refer to section 6.3.1 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @return uint32_t     value of the PMCR
+ */
+static inline uint32_t
+rd_PMCR(void)
+{
+    uint32_t    reg;
+
+    __asm__ __volatile__("mrc p15, 0, %0, c9, c12, 0\n\t" : "=r" (reg));
+
+    return reg;
+}
+
+/**
+ * @brief Write Performance Monitor Control Register
+ *
+ * This function writes new contents to the PMCR.
+ *
+ * Refer to section 6.3.1 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @param [in] reg      value to be written to the PMCR.
+ *
+ * @return none
+ */
+static inline void
+wr_PMCR(uint32_t reg)
+{
+    __asm__ __volatile__("mcr p15, 0, %0, c9, c12, 0\n\t" : : "r" (reg));
+}
+
+/**
+ * @brief Read Count Enable Set Register
+ *
+ * This function returns the current contents of the PMCNTENSET register.
+ *
+ * Refer to section 6.3.2 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @return uint32_t     value of the PMCNTENSET register
+ */
+static inline uint32_t
+rd_PMCNTENSET(void)
+{
+    uint32_t    reg;
+
+    __asm__ __volatile__("mrc p15, 0, %0, c9, c12, 1\n\t" : "=r" (reg));
+
+    return reg;
+}
+
+/**
+ * @brief Write Count Enable Set Register
+ *
+ * This function writes a value into the PMCNTENSET register.
+ *
+ * Refer to section 6.3.2 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @param [in] reg      value to be written into the PMCNTENSET register
+ *
+ * @return none
+ */
+static inline void
+wr_PMCNTENSET(uint32_t reg)
+{
+    __asm__ __volatile__("mcr p15, 0, %0, c9, c12, 1\n\t" : : "r" (reg));
+}
+
+/**
+ * @brief Read Count Enable Clear Register
+ *
+ * This function reads the current value of the PMCNTENCLR register.
+ *
+ * Refer to section 6.3.3 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @return uint32_t     value of the PMCNTENCLR register
+ */
+static inline uint32_t
+rd_PMCNTENCLR(void)
+{
+    uint32_t    reg;
+
+    __asm__ __volatile__("mrc p15, 0, %0, c9, c12, 2\n\t" : "=r" (reg));
+
+    return reg;
+}
+
+/**
+ * @brief Write Count Enable Clear Register
+ *
+ * This function writes a value into the PMCNTENCLR register.
+ *
+ * Refer to section 6.3.3 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @param [in] reg      value to be written into the PMCNTENSET register
+ *
+ * @return none
+ */
+static inline void
+wr_PMCNTENCLR(uint32_t reg)
+{
+    __asm__ __volatile__("mcr p15, 0, %0, c9, c12, 2\n\t" : : "r" (reg));
+}
+
+/**
+ * @brief Read Overflow Flag Status Register
+ *
+ * This function reads the current value of the PMOVSR register.
+ *
+ * Refer to section 6.3.4 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @return uint32_t     value of the PMOVSR register
+ */
+static inline uint32_t
+rd_PMOVSR(void)
+{
+    uint32_t    reg;
+
+    __asm__ __volatile__("mrc p15, 0, %0, c9, c12, 3\n\t" : "=r" (reg));
+
+    return reg;
+}
+
+/**
+ * @brief Write Overflow Flag Status Register
+ *
+ * This function writes a value into the PMOVSR register.
+ *
+ * Refer to section 6.3.4 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @param [in] reg      value to be written into the PMOVSR register
+ *
+ * @return none
+ */
+static inline void
+wr_PMOVSR(uint32_t reg)
+{
+    __asm__ __volatile__("mcr p15, 0, %0, c9, c12, 3\n\t" : : "r" (reg));
+}
+
+/**
+ * @brief Write Software Increment Register
+ *
+ * This function writes a value into the PMSWINC register.
+ *
+ * Refer to section 6.3.5 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @param [in] reg      value to be written into the PMSWINC register
+ *
+ * @return none
+ */
+static inline void
+wr_PMSWINC(uint32_t reg)
+{
+    __asm__ __volatile__("mcr p15, 0, %0, c9, c12, 4\n\t" : : "r" (reg));
+}
+
+/**
+ * @brief Read Performance Counter Selection Register
+ *
+ * This function reads the current value of the PMSELR register.
+ *
+ * Refer to section 6.3.6 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @return uint32_t     value of the PMSELR register
+ */
+static inline uint32_t
+rd_PMSELR(void)
+{
+    uint32_t    reg;
+
+    __asm__ __volatile__("mrc p15, 0, %0, c9, c12, 5\n\t" : "=r" (reg));
+
+    return reg;
+}
+
+/**
+ * @brief Write Performance Counter Selection Register
+ *
+ * This function writes a value into the PMSELR register.
+ *
+ * Refer to section 6.3.6 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @param [in] reg      value to be written into the PMSELR register
+ *
+ * @return none
+ */
+static inline void
+wr_PMSELR(uint32_t reg)
+{
+    __asm__ __volatile__("mcr p15, 0, %0, c9, c12, 5\n\t" : : "r" (reg));
+}
+
+/**
+ * @brief Read Cycle Count Register
+ *
+ * This function reads the current value of the PMCCNTR register.
+ *
+ * Refer to section 6.3.7 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @return uint32_t     value of the PMCCNTR register
+ */
+static inline uint32_t
+rd_PMCCNTR(void)
+{
+    uint32_t    reg;
+
+    __asm__ __volatile__("mrc p15, 0, %0, c9, c13, 0\n\t" : "=r" (reg));
+
+    return reg;
+}
+
+/**
+ * @brief Write Cycle Count Register
+ *
+ * This function writes a value into the PMCCNTR register.
+ *
+ * Refer to section 6.3.7 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @param [in] reg      value to be written into the PMCCNTR register
+ *
+ * @return none
+ */
+static inline void
+wr_PMCCNTR(uint32_t reg)
+{
+    __asm__ __volatile__("mcr p15, 0, %0, c9, c13, 0\n\t" : : "r" (reg));
+}
+
+/**
+ * @brief Read Event Type Selection Register
+ *
+ * This function reads the current value of the PMXEVTYPER register.
+ *
+ * Refer to section 6.3.8 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @return uint32_t     value of the PMXEVTYPER register
+ */
+static inline uint32_t
+rd_PMXEVTYPER(void)
+{
+    uint32_t    reg;
+
+    __asm__ __volatile__("mrc p15, 0, %0, c9, c13, 1\n\t" : "=r" (reg));
+
+    return reg;
+}
+
+/**
+ * @brief Write Event Type Selection Register
+ *
+ * This function writes a value into the PMXEVTYPER register.
+ *
+ * Refer to section 6.3.8 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @param [in] reg      value to be written into the PMXEVTYPER register
+ *
+ * @return none
+ */
+static inline void
+wr_PMXEVTYPER(uint32_t reg)
+{
+    __asm__ __volatile__("mcr p15, 0, %0, c9, c13, 1\n\t" : : "r" (reg));
+}
+
+/**
+ * @brief Read Event Count Register
+ *
+ * This function reads the current value of the PMXEVCNTR register.
+ *
+ * Refer to section 6.3.9 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @return uint32_t     value of the PMXEVCNTR register
+ */
+static inline uint32_t
+rd_PMXEVCNTR(void)
+{
+    uint32_t    reg;
+
+    __asm__ __volatile__("mrc p15, 0, %0, c9, c13, 2\n\t" : "=r" (reg));
+
+    return reg;
+}
+
+/**
+ * @brief Write Event Count Register
+ *
+ * This function writes a value into the PMXEVCNTR register.
+ *
+ * Refer to section 6.3.9 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @param [in] reg      value to be written into the PMXEVCNTR register
+ *
+ * @return none
+ */
+static inline void
+wr_PMXEVCNTR(uint32_t reg)
+{
+    __asm__ __volatile__("mcr p15, 0, %0, c9, c13, 2\n\t" : : "r" (reg));
+}
+
+/**
+ * @brief Read User Enable Register
+ *
+ * This function reads the current value of the PMUSERENR register.
+ *
+ * Refer to section 6.3.10 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @return uint32_t     value of the PMUSERENR register
+ */
+static inline uint32_t
+rd_PMUSERENR(void)
+{
+    uint32_t    reg;
+
+    __asm__ __volatile__("mrc p15, 0, %0, c9, c14, 0\n\t" : "=r" (reg));
+
+    return reg;
+}
+
+/**
+ * @brief Write User Enable Register
+ *
+ * This function writes a value into the PMUSERENR register.
+ *
+ * Refer to section 6.3.10 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @param [in] reg      value to be written into the PMUSERENR register
+ *
+ * @return none
+ */
+static inline void
+wr_PMUSERENR(uint32_t reg)
+{
+    __asm__ __volatile__("mcr p15, 0, %0, c9, c14, 0\n\t" : : "r" (reg));
+}
+
+/**
+ * @brief Read Interrupt Enable Set Register
+ *
+ * This function reads the current value of the PMINTENSET register.
+ *
+ * Refer to section 6.3.11 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @return uint32_t     value of the PMINTENSET register
+ */
+static inline uint32_t
+rd_PMINTENSET(void)
+{
+    uint32_t    reg;
+
+    __asm__ __volatile__("mrc p15, 0, %0, c9, c14, 1\n\t" : "=r" (reg));
+
+    return reg;
+}
+
+/**
+ * @brief Write Interrupt Enable Set Register
+ *
+ * This function writes a value into the PMINTENSET register.
+ *
+ * Refer to section 6.3.11 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @param [in] reg      value to be written into the PMINTENSET register
+ *
+ * @return none
+ */
+static inline void
+wr_PMINTENSET(uint32_t reg)
+{
+    __asm__ __volatile__("mcr p15, 0, %0, c9, c14, 1\n\t" : : "r" (reg));
+}
+
+/**
+ * @brief Read Interrupt Enable Clear Register
+ *
+ * This function reads the current value of the PMINTENCLR register.
+ *
+ * Refer to section 6.3.12 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @return uint32_t     value of the PMINTENCLR register
+ */
+static inline uint32_t
+rd_PMINTENCLR(void)
+{
+    uint32_t    reg;
+
+    __asm__ __volatile__("mrc p15, 0, %0, c9, c14, 2\n\t" : "=r" (reg));
+
+    return reg;
+}
+
+/**
+ * @brief Write Interrupt Enable Clear Register
+ *
+ * This function writes a value into the PMINTENCLR register.
+ *
+ * Refer to section 6.3.12 of the ARM Cortex R5 TRM (version 1.2) for details
+ * of this register.
+ *
+ * @param [in] reg      value to be written into the PMINTENCLR register
+ *
+ * @return none
+ */
+static inline void
+wr_PMINTENCLR(uint32_t reg)
+{
+    __asm__ __volatile__("mcr p15, 0, %0, c9, c14, 2\n\t" : : "r" (reg));
+}
+
+/**
+ * @brief Set up an event counter
+ *
+ * This function will set up an event counter so that it can count
+ * the specified event.
+ *
+ * @param [in] cntr_num         number of the event counter to be set up
+ * @param [in] event            ID of the event that is to be counted
+ *
+ * @return none
+ */
+static inline void
+pmu_set_event_counter(uint32_t cntr_num, uint32_t event)
+{
+    wr_PMSELR(cntr_num);
+    wr_PMXEVTYPER(event);
+}
+
+/**
+ * @brief Read an event counter
+ *
+ * This function will read the contents of the specified event counter.
+ *
+ * @param [in] cntr_num         number of the event counter that is to be read
+ *
+ * @return uint32_t             value contained in the indicated counter
+ */
+static inline uint32_t
+pmu_read_counter(uint32_t cntr_num)
+{
+    wr_PMSELR(cntr_num);
+
+    return rd_PMXEVCNTR();
+}
+
+/**
+ * @brief Clear an event counter
+ *
+ * This function will clear (set to 0) the specified event counter.
+ *
+ * @param [in] cntr_num         number of the event counter that is to be
+ *                              cleared
+ *
+ * @return none
+ */
+static inline void
+pmu_clear_counter(uint32_t cntr_num)
+{
+    wr_PMSELR(cntr_num);
+    wr_PMXEVCNTR(0);
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-regs.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-regs.h
new file mode 100644
index 0000000..cdd6edb
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/armv7-regs.h
@@ -0,0 +1,742 @@
+/*
+ * Copyright (c) 2017-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__ARMV7_REGS_H
+#define CPU__ARMV7_REGS_H
+#define FSP__CPU__ARMV7_REGS_H                   1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+#include <cpu/armv7-mpu.h>
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file armv7-regs.h
+ * @brief Assembly functions that provide access to control registers
+ */
+
+/**
+ * @brief Read Current Program Status Register
+ *
+ * Reads the contents of the CPSR register
+ *
+ * @return contents of CPSR register
+ */
+static inline uint32_t
+rd_cpsr(void)
+{
+    uint32_t val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__ (
+        "mrs %0, cpsr\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+static inline void
+wr_cpsr(uint32_t new_cpsr)
+{
+    __asm__ __volatile__ (
+        "msr cpsr_c, %0\n\t"
+        : /* no output */
+        : "r"(new_cpsr)
+        );
+}
+
+/**
+ * @brief Read Coprocessor Access Control Register
+ *
+ * Reads the contents of the CPACR register.
+ *
+ * @return contents of CPACR register
+ */
+static inline uint32_t
+rd_cpacr(void)
+{
+    uint32_t    val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 0, %0, c1, c0, 2\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+/**
+ * @brief Set the MPU Region Number Register
+ *
+ * Sets the MPU region number register so that a particular MPU region can
+ * be manipulated.
+ *
+ * @param[in] region Region number of the MPU region to provide access to
+ *
+ * @return none
+ */
+static inline void
+set_mpu_region(uint32_t region)
+{
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mcr p15, 0, %0, c6, c2, 0\n\t"
+        : : "r" (region)
+        );
+}
+
+/**
+ * @brief Read the MPU Region Base Register
+ *
+ * Reads the contents of the MPU Region Base Register for the region number
+ * that had been previously set.
+ *
+ * @return contents of the MPU Region Base Register
+ */
+static inline uint32_t
+rd_mpu_region_base(void)
+{
+    uint32_t    val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 0, %0, c6, c1, 0\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+/**
+ * @brief Read the MPU Region Access Control Register
+ *
+ * Reads the contents of the MPU Region Access Control Register for the region
+ * number that had been previously set.
+ *
+ * @return contents of the MPU Region Access Control Register
+ */
+static inline uint32_t
+rd_mpu_region_access(void)
+{
+    uint32_t    val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 0, %0, c6, c1, 4\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+/**
+ * @brief Read the MPU Region Size and Enable Register
+ *
+ * Reads the contents of the MPU Region Size and Enable Register for the
+ * region number that had been previously set.
+ *
+ * @return contents of the MPU Region Size and Enable Register
+ */
+static inline uint32_t
+rd_mpu_region_size(void)
+{
+    uint32_t    val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 0, %0, c6, c1, 2\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+/**
+ * @brief Read the BTCM Region Register
+ *
+ * Reads the contents of the BTCM Region Register which indicates the base
+ * address and size of the BTCM.
+ *
+ * @return contents of the BTCM Regiion Register
+ */
+static inline uint32_t
+rd_btcm_region(void)
+{
+    uint32_t    val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 0, %0, c9, c1, 0\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+/**
+ * @brief Read the ATCM Region Register
+ *
+ * Reads the contents of the ATCM Region Register which indicates the base
+ * address and size of the ATCM.
+ *
+ * @return contents of the ATCM Regiion Register
+ */
+static inline uint32_t
+rd_atcm_region(void)
+{
+    uint32_t    val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 0, %0, c9, c1, 1\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+/**
+ * @brief Read the Slave Port Control Register
+ *
+ * Reads the contents of the Slave Port Control Register.
+ *
+ * @return contents of the Slave Port Control Register
+ */
+static inline uint32_t
+rd_slave_port_control(void)
+{
+    uint32_t    val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 0, %0, c11, c0, 0\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+/**
+ * @brief Read the Normal AXI Peripheral Interface Region Register
+ *
+ * Reads the contents of the normal AXI Peripheral Interface Region Register
+ *
+ * @return contents of the normal AXI Peripheral Interface Region Register
+ */
+static inline uint32_t
+rd_normal_llpp(void)
+{
+    uint32_t    val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 0, %0, c15, c0, 1\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+/**
+ * @brief Read the Virtual AXI Peripheral Interface Region Register
+ *
+ * Reads the contents of the virtual AXI Peripheral Interface Region Register
+ *
+ * @return contents of the virtual AXI Peripheral Interface Region Register
+ */
+static inline uint32_t
+rd_virtual_llpp(void)
+{
+    uint32_t    val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 0, %0, c15, c0, 2\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+/**
+ * @brief Read AHB Peripheral Interface Register
+ *
+ * Reads the contents of the AHB Peripheral Interface Register
+ *
+ * @return contents of the AHB Peripheral Interface Register
+ */
+static inline uint32_t
+rd_ahb_pirr(void)
+{
+    uint32_t    val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 0, %0, c15, c0, 3\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+/**
+ * @brief Read Data Fault Status Register
+ *
+ * Reads the contents of the DFSR which contains status information
+ * regarding the source of the last data abort.
+ *
+ * @return contents of the DFSR
+ */
+static inline uint32_t
+rd_dfsr(void)
+{
+    uint32_t    val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 0, %0, c5, c0, 0\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+/**
+ * @brief Read Data Fault Address Register
+ *
+ * Reads the contents of the DFAR which contains the address of the
+ * fault when a synchronous abort occurs.
+ *
+ * @return contents of the DFAR
+ */
+static inline uint32_t
+rd_dfar(void)
+{
+    uint32_t    val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 0, %0, c6, c0, 0\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+
+/**
+ * @brief Read Instruction Fault Status Register
+ *
+ * Reads the contents of the IFSR which contains status information
+ * regarding the source of the last prefetch abort.
+ *
+ * @return contents of the IFSR
+ */
+static inline uint32_t
+rd_ifsr(void)
+{
+    uint32_t    val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 0, %0, c5, c0, 1\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+/**
+ * @brief Read Instruction Fault Address Register
+ *
+ * Reads the contents of the IFAR which contains the address of the
+ * instruction that caused a prefetch abort.
+ *
+ * @return contents of the IFAR
+ */
+static inline uint32_t
+rd_ifar(void)
+{
+    uint32_t    val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 0, %0, c6, c0, 2\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+/**
+ * @brief Read Auxilary Data Fault Status Register
+ *
+ * Reads the contents of the ADFSR which contains information about
+ * data parity, ECC and TCM errors.
+ *
+ * @return contents of the ADFSR
+ */
+static inline uint32_t
+rd_adfsr(void)
+{
+    uint32_t    val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 0, %0, c5, c1, 0\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+/**
+ * @brief Read Auxilary Instruction Fault Status Register
+ *
+ * Reads the contents of the AIFSR which contains information about
+ * instruction parity, ECC and TCM errors.
+ *
+ * @return contents of AIFSR
+ */
+static inline uint32_t
+rd_aifsr(void)
+{
+    uint32_t    val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 0, %0, c5, c1, 1\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+/**
+ * @brief Read Cache Level ID Register
+ *
+ * Reads the contents of the CLIDR register which indicates which cache
+ * levels are implemented.
+ *
+ * @return contents of CLIDR
+ */
+static inline uint32_t
+rd_clidr(void)
+{
+    uint32_t    clidr;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 1, %0, c0, c0, 1\n\t"
+        : "=r" (clidr)
+        );
+
+    return clidr;
+}
+
+/**
+ * @brief Read System Control Register
+ *
+ * Reads the contents of the SCTLR register which contains control and
+ * configuration information for:
+ *    memory alignment, endianness, protection and fault behavior
+ *    MPU and cache enables and cache replacement strategy
+ *    interrupts and the behvior of interrupt latency
+ *    location of exception vectors
+ *    program flow prediction
+ *
+ * @return contents of SCTLR
+ */
+static inline uint32_t
+rd_sctlr(void)
+{
+    uint32_t    sctlr;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc    p15, 0, %0, c1, c0, 0\n\t"
+        : "=r" (sctlr)
+        );
+
+    return sctlr;
+}
+
+/**
+ * @brief Write System Control Register
+ *
+ * Writes the contents of the SCTLR register which contains control and
+ * configuration information for:
+ *    memory alignment, endianness, protection and fault behavior
+ *    MPU and cache enables and cache replacement strategy
+ *    interrupts and the behvior of interrupt latency
+ *    location of exception vectors
+ *    program flow prediction
+ *
+ * @param[in] sctrl value to be written to SCTLR register
+ *
+ * @return none
+ */
+static inline void
+wr_sctlr(uint32_t sctlr)
+{
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mcr    p15, 0, %0, c1, c0, 0\n\t"
+        : : "r" (sctlr)
+        );
+}
+
+/**
+ * @brief Read Auxiliary Control Register
+ *
+ * Reads the contents of the ACTLR register which controls:
+ *    branch prediction
+ *    performance features
+ *    error and parity logic
+ *
+ * @return contents of ACLTR
+ */
+static inline uint32_t
+rd_actlr(void)
+{
+    uint32_t   actlr;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc    p15, 0, %0, c1, c0, 1\n\t"
+        : "=r" (actlr)
+        );
+
+    return actlr;
+}
+
+/**
+ * @brief Write Auxiliary Control Register
+ *
+ * Writes the contents of the ACTLR register which controls:
+ *    branch prediction
+ *    performance features
+ *    error and parity logic
+ *
+ * @param[in] actlr value to be written to ACTLR register
+ *
+ * @return none
+ */
+static inline void
+wr_actlr(uint32_t actlr)
+{
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mcr    p15, 0, %0, c1, c0, 1\n\t"
+        : : "r" (actlr)
+        );
+}
+
+/**
+ * @brief Read Secondary Auxiliary Control Register
+ *
+ * Reads the contents of the secondary ACTLR register which controls:
+ *    branch prediction
+ *    performance features
+ *    error and parity logic
+ *
+ * @return contents of the secondary ACLTR
+ */
+static inline uint32_t
+rd_secondary_actlr(void)
+{
+    uint32_t    val;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc p15, 0, %0, c15, c0, 1\n\t"
+        : "=r" (val)
+        );
+
+    return val;
+}
+
+/**
+ * @brief Write Secondary Auxiliary Control Register
+ *
+ * Writes the contents of the secondary ACTLR register which controls:
+ *    branch prediction
+ *    performance features
+ *    error and parity logic
+ *
+ * @param[in] actlr value to be written to the secondary ACTLR register
+ *
+ * @return none
+ */
+static inline void
+wr_secondary_actlr(uint32_t actlr)
+{
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mcr    p15, 0, %0, c15, c0, 1\n\t"
+        : : "r" (actlr)
+        );
+}
+
+/**
+ * @brief Read Cache Size Selection Register
+ *
+ * Reads the contents of the CSSELR register which is used to select
+ * which level of the cache is to be interrogated.
+ *
+ * @return contents of the CSSELR
+ */
+static inline uint32_t
+rd_csselr(void)
+{
+    uint32_t    csselr;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc    p15, 2, %0, c0, c0, 0\n\t"
+        : "=r" (csselr)
+        );
+
+    return csselr;
+}
+
+/**
+ * @brief Write Cache Size Selection Register
+ *
+ * Writes the contents of the CSSELR register to allow for the different
+ * caches and cache levels to be interrogated.
+ *
+ * @param[in] csselr Level of cache to be interrogated
+ *
+ * @return none
+ */
+static inline void
+wr_csselr(uint32_t csselr)
+{
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mcr    p15, 2, %0, c0, c0, 0\n\t"
+        : : "r" (csselr)
+        );
+}
+
+/**
+ * @brief Read Cache Size ID Register
+ *
+ * Reads the contents of the CCSIDR register.  Provides information about the
+ * size and behvior of the instruction or data cache.
+ *
+ * @return contents of the CCSIDR register
+ */
+static inline uint32_t
+rd_ccsidr(void)
+{
+    uint32_t    ccsidr;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__(
+        "mrc    p15, 1, %0, c0, c0, 0\n\t"
+        : "=r" (ccsidr)
+        );
+
+    return ccsidr;
+}
+
+#define R5_CPSR_IF_MASK        (R5_CPSR_IRQ_MASK | R5_CPSR_FIQ_MASK)
+
+/**
+ * disable_interrupts() Disable interrupts without using OS
+ *
+ * Code coverage cannot use OS services because OS services
+ * are being instrumented.
+ */
+static inline uint32_t
+disable_interrupts(void)
+{
+    uint32_t    cur_cpsr;
+
+    cur_cpsr = rd_cpsr();
+
+    wr_cpsr(cur_cpsr | R5_CPSR_IF_MASK);
+
+    return cur_cpsr;
+}
+
+/**
+ * restore_interrupts() Restore the interrupts to original mask
+ * @saved_mask          value saved from previous disable_interrupts() call
+ *
+ * Restore interrupts is used instead of enable interrupts disable/restore
+ * may be called from within a OS provided critical section
+ * (with interrupts disabled)
+ */
+static inline void
+restore_interrupts(uint32_t saved_mask)
+{
+    uint32_t    new_cpsr;
+
+    new_cpsr = rd_cpsr() & ~R5_CPSR_IF_MASK;
+    new_cpsr |= saved_mask & R5_CPSR_IF_MASK;
+
+    wr_cpsr(new_cpsr);
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/sections-armv7-mpu.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/sections-armv7-mpu.h
new file mode 100644
index 0000000..a46f6d9
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/sections-armv7-mpu.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef CPU__SECTIONS_ARMV7_MPU_H
+#define CPU__SECTIONS_ARMV7_MPU_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME            TYPE)   */
+#define SECTION_NAME_MPU_DATA           SECTION_BUILDER(mpu,            data)
+#define SECTION_NAME_MPU_TEXT           SECTION_BUILDER(mpu,            text)
+#define SECTION_NAME_MPU_INIT_DATA      SECTION_BUILDER(init.mpu,       data)
+#define SECTION_NAME_MPU_INIT_TEXT      SECTION_BUILDER(init.mpu,       text)
+
+#define SECTION_STR_MPU_TEXT            STR(SECTION_NAME_MPU_TEXT)
+#define SECTION_STR_MPU_DATA            STR(SECTION_NAME_MPU_DATA)
+#define SECTION_STR_MPU_INIT_TEXT       STR(SECTION_NAME_MPU_INIT_TEXT)
+#define SECTION_STR_MPU_INIT_DATA       STR(SECTION_NAME_MPU_INIT_DATA)
+
+#define SECTION_MPU_TEXT                SECTION(SECTION_STR_MPU_TEXT)
+#define SECTION_MPU_DATA                SECTION(SECTION_STR_MPU_DATA)
+#define SECTION_MPU_INIT_TEXT           SECTION(SECTION_STR_MPU_INIT_TEXT)
+#define SECTION_MPU_INIT_DATA           SECTION(SECTION_STR_MPU_INIT_DATA)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/sections-exception.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/sections-exception.h
new file mode 100644
index 0000000..b6fcbe1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/sections-exception.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef CPU__SECTIONS_EXCEPTION_H
+#define CPU__SECTIONS_EXCEPTION_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_EXCEPTION_DATA     SECTION_BUILDER(error.exception,        data)
+#define SECTION_NAME_EXCEPTION_TEXT     SECTION_BUILDER(error.exception,        text)
+
+#define SECTION_STR_EXCEPTION_TEXT      STR(SECTION_NAME_EXCEPTION_TEXT)
+#define SECTION_STR_EXCEPTION_DATA      STR(SECTION_NAME_EXCEPTION_DATA)
+
+#define SECTION_EXCEPTION_TEXT          SECTION(SECTION_STR_EXCEPTION_TEXT)
+#define SECTION_EXCEPTION_DATA          SECTION(SECTION_STR_EXCEPTION_DATA)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/smplock-types.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/smplock-types.h
new file mode 100644
index 0000000..166e2ef
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/smplock-types.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__SMPLOCK_TYPES_H
+#define CPU__SMPLOCK_TYPES_H
+#define FSP__CPU__SMPLOCK_TYPES_H                   1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/**
+ * @brief Armv7 architecture specific smplock structure
+ */
+typedef struct {
+    /*
+     * FIXME: smplocks are not used currently for FSP ARMV7. To avoid the
+     * compiler errors resulting from empty struct declarations, just create
+     * a uint32_t member field. This can be changed when the real use case
+     * arises.
+     */
+    uint32_t lock;
+} arch_smplock_t;
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/type-conversion.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/type-conversion.h
new file mode 100644
index 0000000..12b6338
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv7/cpu/type-conversion.h
@@ -0,0 +1,498 @@
+/*
+ * Copyright (c) 2018-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__TYPE_CONVERSION_H
+#define CPU__TYPE_CONVERSION_H
+#define FSP__CPU__TYPE_CONVERSION_H                     1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <string.h>             // for NULL, size_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>
+#include <misc/macros.h>         // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Table of abbreviations:
+ *   These abbreviations are used in type conversions.  The following letters, or combinations of
+ *   letters, preceeded by an underscore, shall mean the following:
+ * _c       : const
+ * _ch      : char
+ * _fn      : function
+ * _i32     : int32_t
+ * _li      : long int
+ * _ptr     : pointer
+ * _st      : size_t
+ * _u8      : uint8_t
+ * _u32     : uint32_t
+ * _upt     : uintptr_t
+ * _v       : void
+ * _vl      : volatile
+ *
+ */
+
+/*
+ * Table of Contents (abbreviations decoded as per table above):
+ *   fsp_c_v_ptr_to_c_ch_ptr
+ *   fsp_c_ch_ptr_to_v_ptr
+ *   fsp_c_v_ptr_to_v_ptr
+ *   fsp_c_ch_ptr_to_ch_ptr
+ *   fsp_i32_to_u32
+ *   fsp_li_to_st
+ *   fsp_i32_to_st
+ *   fsp_ch_to_u8
+ *   fsp_v_ptr_to_u8_ptr
+ *   fsp_u8_ptr_to_v_ptr
+ *   fsp_c_v_ptr_to_c_u8_ptr
+ *   fsp_c_v_ptr_to_uptr
+ *   fsp_c_v_ptr_to_u32
+ *   fsp_c_u32_ptr_to_u32
+ *   fsp_c_u32_ptr_to_u64
+ *   fsp_c_u8_ptr_to_u32
+ *   fsp_u32_to_u8_ptr
+ *   fsp_u32_to_vl_u32_ptr
+ *   fsp_v_fn_ptr_to_uptr
+ *
+ */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_19_2, "Approval: Bug 200543136, DR: SWE-FSP-033-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+/**
+ * Converts constant void pointer to constant char pointer.
+ *
+ * @param[in] ptr constant void pointer which will be coverted to constant char pointer.
+ * @param[out] ptr constant char pointer of constant void pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline const char *fsp_c_v_ptr_to_c_ch_ptr(const void *ptr)
+{
+    INLINE_RFD(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx");
+    return (const char *)ptr;
+}
+
+/**
+ * Converts constant char pointer to void pointer. Discards const correctness.
+ *
+ * @param[in] input constant char pointer which will be coverted to void pointer.
+ * @param[out] output void pointer of constant char pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline void *fsp_c_ch_ptr_to_v_ptr(const char *input)
+{
+CT_ASSERT(FSP_ALIGNOF(const char *) >= FSP_ALIGNOF(void *), "ASSERT due to data misalignment.")
+    CT_ASSERT(sizeof(const char *) == sizeof(void *), "ASSERT due to incompatible pointer sizes.")
+    union cast_fsp_c_ch_ptr_to_v_ptr {
+        const char *input;
+        void * output;
+    };
+    union cast_fsp_c_ch_ptr_to_v_ptr t;
+
+    t.input= input;
+    return t.output;
+}
+
+/**
+ * Converts constant void pointer non-constant.  Preserves 'const' for R-O APIs,
+ * and allows non-const for R-W APIs.
+ *
+ * @param[in] input constant void pointer which will be coverted to void pointer
+ * @param[out] output void pointer of constant void pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline void *fsp_c_v_ptr_to_v_ptr(const void *input)
+{
+CT_ASSERT(FSP_ALIGNOF(const void *) >= FSP_ALIGNOF(void *), "ASSERT due to data misalignment.")
+    CT_ASSERT(sizeof(const void *) == sizeof(void *), "ASSERT due to incompatible pointer sizes.")
+    union cast_fsp_c_v_ptr_to_v_ptr {
+        const void *input;
+        void * output;
+    };
+    union cast_fsp_c_v_ptr_to_v_ptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts constant char pointer to char pointer
+ *
+ * @param[in] input constant char pointer which will be coverted to char pointer
+ * @param[out] output char pointer of constant char pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline char* fsp_c_ch_ptr_to_ch_ptr(const char *input)
+{
+CT_ASSERT(FSP_ALIGNOF(const char *) >= FSP_ALIGNOF(char *), "ASSERT due to data misalignment.")
+    CT_ASSERT(sizeof(const char *) == sizeof(char *), "ASSERT due to incompatible pointer sizes.")
+    union cast_fsp_c_ch_ptr_to_ch_ptr {
+        const char *input;
+        char* output;
+    };
+    union cast_fsp_c_ch_ptr_to_ch_ptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts signed int to unsigned int
+ *
+ * @param[in] val int32_t which will be coverted to unsigned integer.
+ * @param[out] u_val unsigned integer value of int32_t.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline uint32_t fsp_i32_to_u32(int32_t input)
+{
+    union cast_fsp_i32_to_u32 {
+        int32_t input;
+        uint32_t output;
+    };
+    union cast_fsp_i32_to_u32 t;
+
+    t.input = input;
+    return t.output;
+}
+
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_6, "Approval: Bug 200543266, DR: SWE-FSP-003-SWSADR.docx")
+/**
+ * Converts signed long int to size_t
+ *
+ * @param[in] val long int which will be coverted to size_t.
+ * @param[out] u_val size_t value of int.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline size_t fsp_li_to_st(long int input)
+{
+    union cast_fsp_li_to_st {
+        long int input;
+        size_t output;
+    };
+    union cast_fsp_li_to_st t;
+
+    t.input = input;
+    return t.output;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_6, "Approval: Bug 200543266, DR: SWE-FSP-003-SWSADR.docx")
+
+/**
+ * Converts signed int to size_t
+ *
+ * @param[in] val int which will be coverted to size_t.
+ * @param[out] u_val size_t value of int.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline size_t fsp_i32_to_st(int32_t input)
+{
+    union cast_fsp_i32_to_st {
+        int32_t input;
+        size_t output;
+    };
+    union cast_fsp_i32_to_st t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts char to uint8_t
+ *
+ * @param[in] ch character which will be converted to unsigned character.
+ * @param[out] uchar unsigned char of given character.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline uint8_t fsp_ch_to_u8(char input)
+{
+CT_ASSERT(FSP_ALIGNOF(char) >= FSP_ALIGNOF(uint8_t), "ASSERT due to data misalignment.")
+    CT_ASSERT(sizeof(char) == sizeof(uint8_t), "ASSERT due to incompatible pointer sizes.")
+    union cast_fsp_ch_to_u8 {
+        char input;
+        uint8_t output;
+    };
+    union cast_fsp_ch_to_u8 t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts void pointer to struct uint8_t pointer.
+ *
+ * @param[in] input void pointer which will be coverted to uint8_t pointer.
+ * @param[out] output uint8_t pointer of void pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline uint8_t *fsp_v_ptr_to_u8_ptr(void *input)
+{
+CT_ASSERT(FSP_ALIGNOF(void *) >= FSP_ALIGNOF(uint8_t*), "ASSERT due to data misalignment.")
+    CT_ASSERT(sizeof(void *) == sizeof(uint8_t *), "ASSERT due to incompatible pointer sizes.")
+    union cast_fsp_v_ptr_to_u8_ptr {
+        void * input;
+        uint8_t *output;
+    };
+    union cast_fsp_v_ptr_to_u8_ptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts uint8_t pointer to void pointer.
+ *
+ * @param[in] input uint8_t pointer which will be converted to void pointer.
+ * @param[out] output void pointer of uint8_t pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline void *fsp_u8_ptr_to_v_ptr(uint8_t *input)
+{
+    CT_ASSERT(FSP_ALIGNOF(void *) >= FSP_ALIGNOF(uint8_t *), "ASSERT due to data misalignment.")
+    CT_ASSERT(sizeof(void *) == sizeof(uint8_t *), "ASSERT due to incompatible pointer sizes.")
+    union cast_fsp_u8_ptr_to_v_ptr {
+        uint8_t *input;
+        void *output;
+    };
+    union cast_fsp_u8_ptr_to_v_ptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+
+/**
+ * Converts constant void pointer to struct constant uint8_t pointer.
+ *
+ * @param[in] input constant void pointer which will be coverted to constant uint8_t pointer.
+ * @param[out] output constant uint8_t pointer of constant void pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline const uint8_t *fsp_c_v_ptr_to_c_u8_ptr(const void *input)
+{
+CT_ASSERT(FSP_ALIGNOF(const void *) >= FSP_ALIGNOF(const uint8_t *), "ASSERT due to data misalignment.")
+    CT_ASSERT(sizeof(const void *) == sizeof(const uint8_t *), "ASSERT due to incompatible pointer sizes.")
+    union cast_fsp_c_v_ptr_to_c_u8_ptr {
+        const void * input;
+        const uint8_t *output;
+    };
+    union cast_fsp_c_v_ptr_to_c_u8_ptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts const void pointer to uintptr_t
+ *
+ * @param[in] addr void pointer which will be coverted to uintptr_t
+ * @param[out] value uintptr_t value of void pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline uintptr_t fsp_c_v_ptr_to_uptr(const void *input)
+{
+    CT_ASSERT(FSP_ALIGNOF(const void *) >= FSP_ALIGNOF(uintptr_t *), "ASSERT due to data misalignment.");
+    CT_ASSERT(sizeof(const void *) == sizeof(uintptr_t *), "ASSERT due to incompatible pointer sizes.");
+    union cast_fsp_c_v_ptr_to_uptr {
+        const void *input;
+        uintptr_t output;
+    };
+    union cast_fsp_c_v_ptr_to_uptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts const void pointer to uint32_t
+ *
+ * @param[in] addr void pointer which will be coverted to uint32_t
+ * @param[out] value uint32_t value of void pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline uint32_t fsp_c_v_ptr_to_u32(const void *input)
+{
+    CT_ASSERT(FSP_ALIGNOF(const void *) >= FSP_ALIGNOF(uint32_t), "ASSERT due to data misalignment.");
+    CT_ASSERT(sizeof(const void *) == sizeof(uint32_t), "ASSERT due to incompatible pointer sizes.");
+    union cast_fsp_c_v_ptr_to_u32 {
+        const void *input;
+        uint32_t output;
+    };
+    union cast_fsp_c_v_ptr_to_u32 t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts const uint32_t pointer to uint32_t
+ *
+ * @param[in] addr uint32_t pointer which will be coverted to uint32_t
+ * @param[out] value uint32_t value of uint32_t pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline uint32_t fsp_c_u32_ptr_to_u32(const uint32_t *input)
+{
+    CT_ASSERT(sizeof(const uint32_t *) == sizeof(uint32_t), "ASSERT due to incompatible pointer sizes.");
+    union cast_fsp_c_u32_ptr_to_u32 {
+        const uint32_t *input;
+        uint32_t output;
+    };
+    union cast_fsp_c_u32_ptr_to_u32 t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts const uint8_t pointer to uint32_t
+ *
+ * @param[in] addr uint8_t pointer which will be coverted to uint32_t
+ * @param[out] value uint32_t value of uint8_t pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline uint32_t fsp_c_u8_ptr_to_u32(const uint8_t *input)
+{
+    CT_ASSERT(sizeof(const uint32_t *) == sizeof(uint32_t), "ASSERT due to incompatible pointer sizes.");
+    union cast_fsp_c_u8_ptr_to_u32 {
+        const uint8_t *input;
+        uint32_t output;
+    };
+    union cast_fsp_c_u8_ptr_to_u32 t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts uint32_t to uint8_t pointer
+ *
+ * @param[in] uint32_t addr which will be converted to uint8_t pointer.
+ * @param[out] uint8_t pointer of uint32_t value.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline uint8_t *fsp_u32_to_u8_ptr(uint32_t input)
+{
+    CT_ASSERT(sizeof(uint32_t *) == sizeof(uint32_t), "ASSERT due to incompatible pointer sizes.");
+    union cast_fsp_u32_to_u8_ptr {
+        uint32_t input;
+        uint8_t *output;
+    };
+    union cast_fsp_u32_to_u8_ptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts const uint32_t pointer to uint64_t
+ *
+ * @param[in] addr uint32_t pointer which will be coverted to uint64_t
+ * @param[out] value uint64_t value of uint32_t pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline uint64_t fsp_c_u32_ptr_to_u64(const uint32_t *input)
+{
+    CT_ASSERT(sizeof(const uint32_t *) == sizeof(uint32_t), "ASSERT due to incompatible pointer sizes.");
+    union cast_fsp_c_u32_ptr_to_u64 {
+        const uint32_t *input;
+        uint64_t output;
+    };
+    union cast_fsp_c_u32_ptr_to_u64 t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts uint32_t to volatile uint32_t pointer
+ *
+ * @param[in] addr unsigned integer which will be converted to volatile unsigned integer pointer.
+ * @param[out] value volatile unsigned integer pointer represented by unsigned integer addr
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline volatile uint32_t* fsp_u32_to_vl_u32_ptr(uint32_t input)
+{
+    CT_ASSERT(FSP_ALIGNOF(uint32_t) >= FSP_ALIGNOF(volatile uint32_t *), "ASSERT due to data misalignment.");
+    CT_ASSERT(sizeof(uint32_t) == sizeof(volatile uint32_t *), "ASSERT due to incompatible data sizes.");
+    union cast_fsp_u32_to_vl_u32_ptr {
+        uint32_t input;
+        volatile uint32_t *output;
+    };
+    union cast_fsp_u32_to_vl_u32_ptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts void (function pointer) to uintptr_t
+ *
+ * @param[in] fun_ptr pointer to function.
+ * @param[out] value uint32_t value of function pointer
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline uintptr_t fsp_v_fn_ptr_to_uptr(void (*input)(void))
+{
+    CT_ASSERT(FSP_ALIGNOF(void (*)(void)) >= FSP_ALIGNOF(uintptr_t), "ASSERT due to data misalignment.");
+    CT_ASSERT(sizeof(void (*)(void)) == sizeof(uintptr_t), "ASSERT due to incompatible data sizes.");
+    union cast_fsp_v_fn_ptr_to_uptr {
+        void (*input)(void);
+        uintptr_t output;
+    };
+    union cast_fsp_v_fn_ptr_to_uptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Rule_19_2, "Approval: Bug 200543136, DR: SWE-FSP-033-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv8/cortex-r52/cpu/mmio-access.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv8/cortex-r52/cpu/mmio-access.h
new file mode 100644
index 0000000..87f5d8b
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv8/cortex-r52/cpu/mmio-access.h
@@ -0,0 +1,188 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__MMIO_ACCESS_H
+#define CPU__MMIO_ACCESS_H
+#define FSP__CPU__MMIO_ACCESS_H                         1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/type-conversion.h>
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__CPU__TYPE_CONVERSION_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+/**
+ * @file mmio-access.h
+ * @brief functions that provide access to read and write the memory
+ * mapped hardware registers.
+ */
+
+/**
+ * @brief Read a 32-bit value from a memory mapped register
+ *
+ * @jama_func_req_id 8314409
+ *
+ * Provides an alias for 'readl' from <reg-access/reg-access.h>.
+ *
+ * This function will read a 32-bit value from the memory mapped register
+ * specified by the address parameter passed.
+ *
+ * @param[in] addr Address of the memory mapped register
+ *
+ * @return contents of the register
+ */
+static inline uint32_t ioread32(uintptr_t addr)
+{
+    return *fsp_upt_to_vl_u32_ptr(addr);
+}
+
+/**
+ * @brief Read a 32-bit value from a memory mapped register address
+ *
+ * @jama_func_req_id 8314409
+ *
+ * Provides an alias for 'readl_base_offset' from <reg-access/reg-access.h>.
+ *
+ * This function will read a 32-bit value from the memory mapped register
+ * specified by the address computed by the sum of the passed parameters
+ * base and offset.
+ *
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register
+ *
+ * @return contents of the register
+ */
+static inline uint32_t ioread32_offset(uintptr_t base, uint32_t offset)
+{
+    uint32_t data;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__ (
+            "ldr %0, [%1, %2]\n\t"
+            : "=r" (data)
+            : "r" (base), "Ir" (offset)
+    );
+
+    return data;
+}
+
+/**
+ * @brief Write a 32-bit value to a memory mapped register
+ *
+ * @jama_func_req_id 8314412
+ *
+ * Provides an alias for 'writel' from <reg-access/reg-access.h>.
+ *
+ * This function will write a 32-bit value to the memory mapped register
+ * specified by the address parameter passed.
+ *
+ * @param[in] addr Address of the memory mapped register
+ * @param[in] data value to be written to the memory mapped register
+ */
+static inline void iowrite32(uintptr_t addr, uint32_t data)
+{
+    *fsp_upt_to_vl_u32_ptr(addr) = data;
+}
+
+/**
+ * @brief Write a 32-bit value to a memory mapped register address
+ *
+ * @jama_func_req_id 8314412
+ *
+ * Provides an alias for 'writel_base_offset' from <reg-access/reg-access.h>.
+ *
+ * This function will write a 32-bit value to the memory mapped register
+ * address computed by the sum of the passed parameters base and offset.
+ *
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register; offset is immediate value
+ * @param[in] data value to be written to the memory mapped register
+ */
+static inline void iowrite32_offset(uintptr_t base, uint32_t offset, uint32_t data)
+{
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__ (
+            "str %0, [%1, %2]\n\t"
+            :
+            : "r" (data), "r" (base), "Ir" (offset)
+            : "memory"
+    );
+}
+
+/**
+ * @brief Write a 32-bit value to a memory mapped register address
+ *
+ * @jama_func_req_id 8314412
+ *
+ * Provides an alias for 'writel_base_regoffset' from <reg-access/reg-access.h>.
+ *
+ * This function will write a 32-bit value to the memory mapped register
+ * address computed by the sum of the passed parameters base and offset.
+ *
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register; offset is register value
+ * @param[in] data value to be written to the memory mapped register
+ */
+static inline void iowrite32_regoffset(uintptr_t base, uint32_t offset, uint32_t data)
+{
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__ (
+            "str %0, [%1, %2]\n\t"
+            :
+            : "r" (data), "r" (base), "r" (offset)
+            : "memory"
+    );
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv8/cortex-r52/reg-access/reg-access.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv8/cortex-r52/reg-access/reg-access.h
new file mode 100644
index 0000000..0e5a283
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv8/cortex-r52/reg-access/reg-access.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef REG_ACCESS__REG_ACCESS_H
+#define REG_ACCESS__REG_ACCESS_H
+#define FSP__REG_ACCESS__REG_ACCESS_H                   1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/mmio-access.h>
+#include <cpu/type-conversion.h>
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__CPU__MMIO_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__TYPE_CONVERSION_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file reg-access.h
+ * @brief functions that provide access to read and write the memory
+ * mapped hardware registers.
+ */
+
+/**
+ * @brief Read a 32-bit value from a memory mapped register
+ *
+ * @jama_func_req_id 8314409
+ *
+ * This function will read a 32-bit value from the memory mapped register
+ * specified by the address parameter passed.
+ *
+ * @param[in] addr Address of the memory mapped register
+ *
+ * @return contents of the register
+ */
+static inline uint32_t readl(uint32_t addr)
+{
+    return ioread32(addr);
+}
+
+/**
+ * @brief Read a 32-bit value from a memory mapped register address
+ *
+ * @jama_func_req_id 8314409
+ *
+ * This function will read a 32-bit value from the memory mapped register
+ * specified by the address computed by the sum of the passed parameters
+ * base and offset.
+ *
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register
+ *
+ * @return contents of the register
+ */
+static inline uint32_t readl_base_offset(uint32_t base, uint32_t offset)
+{
+    return ioread32_offset(base, offset);
+}
+
+/**
+ * @brief Write a 32-bit value to a memory mapped register
+ *
+ * @jama_func_req_id 8314412
+ *
+ * This function will write a 32-bit value to the memory mapped register
+ * specified by the address parameter passed.
+ *
+ * @param[in] data value to be written to the memory mapped register
+ * @param[in] addr Address of the memory mapped register
+ */
+static inline void writel(uint32_t data, uint32_t addr)
+{
+    iowrite32(addr, data);
+}
+
+/**
+ * @brief Write a 32-bit value to a memory mapped register address
+ *
+ * @jama_func_req_id 8314412
+ *
+ * This function will write a 32-bit value to the memory mapped register
+ * address computed by the sum of the passed parameters base and offset.
+ *
+ * @param[in] data value to be written to the memory mapped register
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register; offset is immediate value
+ */
+static inline void writel_base_offset(uint32_t data, uint32_t base, uint32_t offset)
+{
+    iowrite32_offset(base, offset, data);
+}
+
+/**
+ * @brief Write a 32-bit value to a memory mapped register address
+ *
+ * @jama_func_req_id 8314412
+ *
+ * This function will write a 32-bit value to the memory mapped register
+ * address computed by the sum of the passed parameters base and offset.
+ *
+ * @param[in] data value to be written to the memory mapped register
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register; offset is register value
+ */
+static inline void writel_base_regoffset(uint32_t data, uint32_t base, uint32_t offset)
+{
+    iowrite32_regoffset(base, offset, data);
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv8/cpu/smplock-types.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv8/cpu/smplock-types.h
new file mode 100644
index 0000000..68e0651
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv8/cpu/smplock-types.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__SMPLOCK_TYPES_H
+#define CPU__SMPLOCK_TYPES_H
+#define FSP__CPU__SMPLOCK_TYPES_H                   1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/**
+ * @brief Armv8 architecture specific smplock structure
+ */
+typedef struct {
+    /*
+     * FIXME: To be implemented depending on the ARMv8 usage model. In the
+     * interim, to avoid the compilation errors resulting from empty struct
+     * declarations, just create a uint32_t member field. This can be changed
+     * depending on the usage model.
+     */
+    uint32_t lock;
+} arch_smplock_t;
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/armv8/cpu/type-conversion.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv8/cpu/type-conversion.h
new file mode 100644
index 0000000..0811e66
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/armv8/cpu/type-conversion.h
@@ -0,0 +1,182 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__TYPE_CONVERSION_H
+#define CPU__TYPE_CONVERSION_H
+#define FSP__CPU__TYPE_CONVERSION_H                     1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <string.h>             // for NULL, size_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>
+#include <misc/macros.h>         // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Table of abbreviations:
+ *   These abbreviations are used in type conversions.  The following letters, or combinations of
+ *   letters, preceeded by an underscore, shall mean the following:
+ * _c       : const
+ * _ch      : char
+ * _fn      : function
+ * _i32     : int32_t
+ * _li      : long int
+ * _ptr     : pointer
+ * _st      : size_t
+ * _u8      : uint8_t
+ * _u32     : uint32_t
+ * _upt     : uintptr_t
+ * _v       : void
+ * _vl      : volatile
+ *
+ */
+
+/*
+ * Table of Contents (abbreviations decoded as per table above):
+ *   fsp_c_v_ptr_to_v_ptr
+ *   fsp_c_v_ptr_to_uptr
+ *   fsp_c_v_ptr_to_u32
+ *   fsp_upt_to_vl_u32_ptr
+ *
+ */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_19_2, "Approval: Bug 200543136, DR: SWE-FSP-033-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+/**
+ * Converts constant void pointer non-constant.  Preserves 'const' for R-O APIs,
+ * and allows non-const for R-W APIs.
+ *
+ * @param[in] input constant void pointer which will be coverted to void pointer
+ * @param[out] output void pointer of constant void pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline void *fsp_c_v_ptr_to_v_ptr(const void *input)
+{
+CT_ASSERT(FSP_ALIGNOF(const void *) >= FSP_ALIGNOF(void *), "ASSERT due to data misalignment.")
+    CT_ASSERT(sizeof(const void *) == sizeof(void *), "ASSERT due to incompatible pointer sizes.")
+    union cast_fsp_c_v_ptr_to_v_ptr {
+        const void *input;
+        void * output;
+    };
+    union cast_fsp_c_v_ptr_to_v_ptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts const void pointer to uintptr_t
+ *
+ * @param[in] addr void pointer which will be coverted to uintptr_t
+ * @param[out] value uintptr_t value of void pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline uintptr_t fsp_c_v_ptr_to_uptr(const void *input)
+{
+    CT_ASSERT(FSP_ALIGNOF(const void *) >= FSP_ALIGNOF(uintptr_t *), "ASSERT due to data misalignment.");
+    CT_ASSERT(sizeof(const void *) == sizeof(uintptr_t *), "ASSERT due to incompatible pointer sizes.");
+    union cast_fsp_c_v_ptr_to_uptr {
+        const void *input;
+        uintptr_t output;
+    };
+    union cast_fsp_c_v_ptr_to_uptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts const void pointer to uint32_t
+ *
+ * @param[in] addr void pointer which will be coverted to uint32_t
+ * @param[out] value uint32_t value of void pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline uint32_t fsp_c_v_ptr_to_u32(const void *input)
+{
+    CT_ASSERT(FSP_ALIGNOF(const void *) >= FSP_ALIGNOF(uint32_t), "ASSERT due to data misalignment.");
+    CT_ASSERT(sizeof(const void *) == sizeof(uint32_t), "ASSERT due to incompatible pointer sizes.");
+    union cast_fsp_c_v_ptr_to_u32 {
+        const void *input;
+        uint32_t output;
+    };
+    union cast_fsp_c_v_ptr_to_u32 t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts uintptr_t to volatile uint32_t pointer
+ *
+ * @param[in] addr unsigned integer which will be converted to volatile unsigned integer pointer.
+ * @param[out] value volatile unsigned integer pointer represented by unsigned integer addr
+ */
+static inline volatile uint32_t* fsp_upt_to_vl_u32_ptr(uintptr_t input)
+{
+    CT_ASSERT(FSP_ALIGNOF(uintptr_t) >= FSP_ALIGNOF(volatile uint32_t *), "ASSERT due to data misalignment.");
+    CT_ASSERT(sizeof(uintptr_t) == sizeof(volatile uint32_t *), "ASSERT due to incompatible data sizes.");
+    union cast_fsp_upt_to_vl_u32_ptr {
+        uintptr_t input;
+        volatile uint32_t *output;
+    };
+    union cast_fsp_upt_to_vl_u32_ptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Rule_19_2, "Approval: Bug 200543136, DR: SWE-FSP-033-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/common/cpu/arm-vic.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/common/cpu/arm-vic.h
new file mode 100644
index 0000000..6843cd1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/common/cpu/arm-vic.h
@@ -0,0 +1,258 @@
+/*
+ * Copyright (c) 2014-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__ARM_VIC_H
+#define CPU__ARM_VIC_H
+#define FSP__CPU__ARM_VIC_H                     1
+
+#ifndef __ASSEMBLER__
+/* Compiler headers */
+#include <stdint.h>
+#endif
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+#endif
+
+/** Maximum number of VIC instances per ARM processor */
+#define MAX_ARM_VICS        MK_U32_CONST(2)
+/** Maximum number of interrupts supported per VIC instance */
+#define ARM_VIC_IRQ_COUNT   MK_U32_CONST(32)
+/** Maximum number of VIC interrupts supported by the R5 processor */
+#define MAX_ARM_VIC_IRQS    (MAX_ARM_VICS * ARM_VIC_IRQ_COUNT)
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
+
+#ifndef __ASSEMBLER__
+/**
+ * @struct arm_vic_context
+ * @brief  Structure to save ARM VIC context
+ * @{
+ */
+struct arm_vic_context {
+    /** Array to store handlers for the VIC interrupts */
+    uint32_t vect_addr[ARM_VIC_IRQ_COUNT];
+    /** Interrupt enable status of the VIC instance */
+    uint32_t intenable;
+    /** Interrupt select status for the VIC instance */
+    uint32_t intselect;
+};
+/** @} */
+
+INLINE_RFD(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx", MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+typedef void (*arm_vic_handler)(void);
+
+/**
+ * @brief Enable ARM VIC interrupt
+ *
+ * @param[in] vic_base VIC instance ID [0 - (MAX_ARM_VICS - 1U)]
+ * @param[in] irq      IRQ offset per VIC instance [0 - (ARM_VIC_IRQ_COUNT - 1)]
+ */
+void arm_vic_enable(uint32_t vic_base, uint32_t irq);
+
+/**
+ * @brief Disable ARM VIC interrupt
+ *
+ * @param[in] vic_base VIC instance ID [0 - (MAX_ARM_VICS - 1U)]
+ * @param[in] irq      IRQ offset per VIC instance [0 - (ARM_VIC_IRQ_COUNT - 1)]
+ */
+void arm_vic_disable(uint32_t vic_base, uint32_t irq);
+
+/**
+ * @brief Disable all VIC interrupts
+ *
+ * Disables all interrupts for the input VIC instance
+ *
+ * @param[in] vic_base VIC instance ID [0 - (MAX_ARM_VICS - 1U)]
+ */
+void arm_vic_disable_all(uint32_t vic_base);
+
+/**
+ * @brief Trigger VIC interrupt from SW
+ *
+ * Generates interrupt on the input VIC IRQ line without the knowledge of HW
+ *
+ * @param[in] vic_base VIC instance ID [0 - (MAX_ARM_VICS - 1U)]
+ * @param[in] irq      IRQ offset per VIC instance [0 - (ARM_VIC_IRQ_COUNT - 1)]
+ */
+void arm_vic_gen_software_int(uint32_t vic_base, uint32_t irq);
+
+
+/**
+ * @brief Clear VIC interrupt triggered from SW
+ *
+ * Clears interrupt on the input VIC IRQ line triggered from SW without the knowledge of HW
+ *
+ * @param[in] vic_base VIC instance ID [0 - (MAX_ARM_VICS - 1U)]
+ * @param[in] irq      IRQ offset per VIC instance [0 - (ARM_VIC_IRQ_COUNT - 1)]
+ */
+void arm_vic_clear_software_int(uint32_t vic_base, uint32_t irq);
+
+/**
+ * @brief Register IRQ handler for the VIC interrupt.
+ * Maps input service routine to the VIC interrupt derived from VIC instance ID and IRQ offset
+ *
+ * @param[in] vic_base     VIC instance ID [0 - (MAX_ARM_VICS - 1U)]
+ * @param[in] irq          IRQ offset per VIC instance [0 - (ARM_VIC_IRQ_COUNT - 1)]
+ * @param     isr_vect_addr Handler to service the interrupt
+ */
+void arm_vic_set_isr_vect_addr(uint32_t vic_base, uint32_t irq, void (*isr_vect_addr)(void));
+
+/**
+ * @brief Read VIC IRQ enable status.
+ * Returns bit-mask value indicating enable status of VIC IRQs.
+ *
+ * @param[in] vic_base VIC instance ID [0 - (MAX_ARM_VICS - 1U)]
+ *
+ * @retval 32-bit value indicating IRQ enable status
+ */
+uint32_t arm_vic_read_irq_status(uint32_t vic_base);
+
+/**
+ * @brief Read VIC FIQ enable status.
+ * Returns bit-mask value indicating enable status of VIC FIQs.
+ *
+ * @param[in] vic_base VIC instance ID [0 - (MAX_ARM_VICS - 1U)]
+ *
+ * @retval 32-bit value indicating FIQ enable status
+ */
+uint32_t arm_vic_read_fiq_status(uint32_t vic_base);
+
+/**
+ * @brief Read raw IRQ enable status.
+ * Returns bit-mask value indicating raw enable status of VIC IRQs.
+ *
+ * @param[in] vic_base VIC instance ID [0 - (MAX_ARM_VICS - 1U)]
+ *
+ * @retval 32-bit value indicating raw IRQ enable status
+ */
+uint32_t arm_vic_read_raw_int_status(uint32_t vic_base);
+
+/**
+ * @brief Write to VIC interrupt select register
+ *
+ * @param[in] vic_base  VIC instance ID [0 - (MAX_ARM_VICS - 1U)]
+ *
+ * @param[in] intselect 32-bit interrupt select mask value
+ */
+void arm_vic_write_intselect(uint32_t vic_base, uint32_t intselect);
+
+/**
+ * @brief Read VIC interrupt select register
+ *
+ * @param[in] vic_base  VIC instance ID [0 - (MAX_ARM_VICS - 1U)]
+ *
+ * @retval 32-bit value indicating VIC interrupt select status
+ */
+uint32_t arm_vic_read_intselect(uint32_t vic_base);
+
+/**
+ * @brief Write to VIC interrupt enable register
+ *
+ * @param[in] vic_base  VIC instance ID [0 - (MAX_ARM_VICS - 1U)]
+ *
+ * @param[in] intenable 32-bit interrupt enable mask value
+ */
+void arm_vic_write_intenable(uint32_t vic_base, uint32_t intenable);
+
+/**
+ * @brief Read VIC interrupt select register
+ *
+ * @param[in] vic_base  VIC instance ID [0 - (MAX_ARM_VICS - 1U)]
+ *
+ * @retval 32-bit value indicating VIC interrupt enable status
+ */
+uint32_t arm_vic_read_intenable(uint32_t vic_base);
+
+/**
+ * @brief Save VIC context
+ * Calling this function saves the VIC state in the input context structure.
+ * VIC state comprises of:
+ *
+ * - Interrupt enable status
+ *
+ * - Interrupt select status
+ *
+ * - Map table to save registered interrupt handlers for the VIC interrupts
+ *
+ * @param[in] vic_base VIC instance ID [0 - (MAX_ARM_VICS - 1U)]
+ * @param[in] ctx      Pointer to context structure to save the VIC state
+ */
+void arm_vic_save_state(uint32_t vic_base, struct arm_vic_context *ctx);
+
+/**
+ * @brief Restore VIC context
+ * Calling this function restores the VIC state from the input context structure.
+ * VIC state comprises of:
+ *
+ * - Interrupt enable status
+ *
+ * -  Interrupt select status
+ *
+ * - Map table to save registered interrupt handlers for the VIC interrupts
+ *
+ * @param[in] vic_base VIC instance ID [0 - (MAX_ARM_VICS - 1U)]
+ * @param[in] ctx      Pointer to the context structure for restoring the VIC
+ *                     state
+ */
+void arm_vic_restore_state(uint32_t vic_base, const struct arm_vic_context *ctx);
+#endif
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/common/cpu/barriers.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/common/cpu/barriers.h
new file mode 100644
index 0000000..3cb1fd8
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/common/cpu/barriers.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2015-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__BARRIERS_H
+#define CPU__BARRIERS_H
+#define FSP__CPU__BARRIERS_H                    1
+
+/**
+ * @file barriers.h
+ * @brief Definitions for various synchronization barriers
+ */
+
+/**
+ * @brief Cache Op Completed Barrier
+ *
+ * This function will stall the pipeline until the pending
+ * cache operations have completed.
+ *
+ * @return none
+ */
+static inline void barrier_cache_op_complete(void)
+{
+    __asm__ __volatile__("dsb sy\n\t" : : : "memory");
+}
+
+/**
+ * @brief Compiler Barrier
+ *
+ * This function will prevent the compiler from optimizing away
+ * the portion of code that the function appears in.
+ *
+ * @return none
+ */
+static inline void barrier_compiler(void)
+{
+    __asm__ __volatile__("" : : : "memory");
+}
+
+/**
+ * @brief Memory Order Barrier
+ *
+ * This function will ensure that memory operations that appear
+ * after this function (in time) will be commited to memory after
+ * memory operations that appear before this function (in time).
+ *
+ * @return none
+ */
+static inline void barrier_memory_order(void)
+{
+    __asm__ __volatile__("dmb sy\n\t" : : : "memory");
+}
+
+/**
+ * @brief Memory Complete Barrier
+ *
+ * This function will stall the pipeline such that all pending
+ * memory operations complete before the next instruction is
+ * executed.
+ *
+ * @return none
+ */
+static inline void barrier_memory_complete(void)
+{
+    __asm__ __volatile__("dsb sy\n\t" : : : "memory");
+}
+
+/**
+ * @brief Instruction Synchronization Barrier
+ *
+ * This function causes the pipeline to be flushed such that all
+ * instructions that follow are fetched from cache or memory.  This
+ * ensures that the certain operations that affect the overall state
+ * of the processor are seen by instructions that follow this barrier.
+ *
+ * @return none
+ */
+static inline void barrier_instruction_synchronization(void)
+{
+    __asm__ __volatile__("isb sy\n\t" : : : "memory");
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/common/cpu/built-ins.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/common/cpu/built-ins.h
new file mode 100644
index 0000000..9f3f7e8
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/common/cpu/built-ins.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2015-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__BUILT_INS_H
+#define CPU__BUILT_INS_H
+#define FSP__CPU__BUILT_INS_H                    1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx", MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+/**
+ * @file built-ins.h
+ * @brief Definitions for various ARM built in instructions
+ */
+
+/**
+ * @brief Count Leading Zeros
+ *
+ * This function will return the number of leading zeros in
+ * a value.  If the value is 0 it will return 32.
+ *
+ * @return a value between 0 and 32 indicating the number of
+ * leading zeros in the input value.
+ */
+static inline uint32_t
+arm_builtin_clz(uint32_t value)
+{
+    uint32_t            count;
+
+    INLINE_RFD(MISRA, FP, Directive_4_3, "Approval: JIRA TID-1940, DR: SWE-FSP-065-SWSADR.docx");
+    __asm__ __volatile__("clz %0, %1\n\t"
+                         : "=r" (count) : "r" (value) );
+
+    return count;
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx", MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/common/cpu/cache-l2.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/common/cpu/cache-l2.h
new file mode 100644
index 0000000..a0af58a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/common/cpu/cache-l2.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2015-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__CACHE_L2_H
+#define CPU__CACHE_L2_H
+#define FSP__CPU__CACHE_L2_H                    1
+
+/* Compiler headers */
+#include <stddef.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/*
+ * Level 2 cache functions. Automatically called by the main cache functions
+ * at the appropriate time.
+ */
+
+void cache_l2_disable(void);
+void cache_l2_enable(void);
+void cache_l2_invalidate(void *base, size_t length);
+void cache_l2_clean(const void *base, size_t length);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/arm/common/cpu/cache.h b/spe-freertos-bsp/fsp/source/include/cpu/arm/common/cpu/cache.h
new file mode 100644
index 0000000..bf45fe5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/arm/common/cpu/cache.h
@@ -0,0 +1,226 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__CACHE_H
+#define CPU__CACHE_H
+#define FSP__CPU__CACHE_H                       1
+
+/* Compiler headers */
+#include <stddef.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/**
+ * @file cache.h
+ * @brief Interfaces for performing Cache operations.
+ */
+
+
+/**
+ * @brief Disable all caches
+ *
+ * This function will disable the iCache and dCache.  It will also ensure
+ * that any dirty lines in the dCache have been completely written to DRAM
+ * before this function returns.
+ *
+ * @func_req_id 8191502
+ *
+ * @return none
+ *
+ */
+void cache_disable(void);
+
+/**
+ * @brief Enable all caches
+ *
+ * This function will enable the iCache and dCache.  It will ensure that
+ * the contents of the caches are invalid (e.g. there is no data or instructions
+ * in the cache) before enabling the caches.
+ *
+ * @func_req_id 8191127
+ *
+ * @return none
+ */
+void cache_enable(void);
+
+/**
+ * @brief Enable all caches with ECC enabled
+ *
+ * This function will enable the iCache and dCache with ECC enabled.  It
+ * follows the Sequence Reference 8.5.5. of Cortex R5 TRM (Disabling or
+ * enabling error checking).
+ *
+ * @func_req_id 8345060
+ *
+ * @return none
+ */
+void cache_enable_ecc(void);
+
+/**
+ * @brief Invalidate a region of iCache
+ *
+ * This function will cause the specified region in the iCache to be
+ * invalidated.  That is, that data will no longer reside in the iCache
+ * at the completion of this function.
+ *
+ * If the specified range does not align with integral numbers of
+ * cache lines, more data may be invalidated than was actually specified.
+ *
+ * @param[in] base:   Address of start of range to be invalidated
+ * @param[in] length: Number of bytes in the range to be invalidated
+ *
+ * @func_req_id 8345075
+ *
+ * @return none
+ */
+void icache_invalidate(void * const base, const size_t length);
+
+/**
+ * @brief Invalidate the entire iCache
+ *
+ * This function will cause the entire icache contents to be invalidated.
+ *
+ * @func_req_id 8361851
+ *
+ * @return none
+ */
+void icache_invalidate_all(void);
+
+/**
+ * @brief Clean a region of dCache
+ *
+ * This function will cause any "dirty" data in the dCache in the
+ * specified range to be written back to memory.  The data may still
+ * reside in the dCache (e.g. it was not invalidated).
+ *
+ * If the specified range does not align with integral numbers of
+ * cache lines, more data may be "cleaned" than was actually specified.
+ *
+ * @param[in] base:   Address of start of range to be cleaned
+ * @param[in] length: Number of bytes in the range to be cleaned
+ *
+ * @func_req_id 8362199
+ *
+ * @return none
+ */
+void dcache_clean(const void * const base, const size_t length);
+
+/**
+ * @brief Invalidate a region of dCache
+ *
+ * This function will cause the specified region in the dCache to be
+ * invalidated.  That is, that data will no longer reside in the dCache
+ * at the completion of this function.
+ *
+ * If the specified range does not align with integral numbers of
+ * cache lines, more data may be invalidated than was actually specified.
+ *
+ * @param[in] base:   Address of start of range to be invalidated
+ * @param[in] length: Number of bytes in the range to be invalidated
+ *
+ * @func_req_id 8361983
+ *
+ * @return none
+ */
+void dcache_invalidate(void *const base, const size_t length);
+
+/**
+ * @brief Clean entire dCache
+ *
+ * This function will cause all of the dirty lines in the dCache to be
+ * "cleaned".  That is, any dirty lines in the dCache will be written
+ * back to DRAM.
+ *
+ * This will only clean the L1 dCache as the R5 only has L1 caches.
+ *
+ * @func_req_id 8362202
+ *
+ * @return none
+ */
+void dcache_clean_all(void);
+
+/**
+ * @brief Invalidate entire dCache
+ *
+ * This function will cause the entire dCache to be invalidated
+ *
+ * @func_req_id 8362076
+ *
+ * @return none
+ */
+void dcache_invalidate_all(void);
+
+/**
+ * @brief Invalidate a region of dCache
+ *
+ * This function will cause the specified region in the dCache to be
+ * invalidated.  That is, that data will no longer reside in the dCache
+ * at the completion of this function.
+ *
+ * If the specified range does not align with integral numbers of
+ * cache lines, more data may be invalidated than was actually specified.
+ *
+ * @param[in] base:   Address of start of range to be invalidated
+ * @param[in] length: Number of bytes in the range to be invalidated
+ *
+ * @func_req_id 8191673
+ *
+ * @return none
+ *
+ * @deprecated dcache_invalidate() should be used instead.
+ */
+void cache_invalidate(void * const base, size_t length);
+
+/**
+ * @brief Clean a region of dCache
+ *
+ * This function will cause any "dirty" data in the dCache in the
+ * specified range to be written back to memory.  The data may still
+ * reside in the dCache (e.g. it was not invalidated).
+ *
+ * If the specified range does not align with integral numbers of
+ * cache lines, more data may be "cleaned" than was actually specified.
+ *
+ * @param[in] base   Address of start of range to be cleaned
+ * @param[in] length Number of bytes in the range to be cleaned
+ *
+ * @func_req_id 8191682
+ *
+ * @return none
+ *
+ * @deprecated dcache_clean() should be used instead.
+ */
+void cache_clean(const void * const base, size_t length);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/asm-helpers.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/asm-helpers.h
new file mode 100644
index 0000000..67bdff9
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/asm-helpers.h
@@ -0,0 +1,91 @@
+/**
+ * @file asm_helpers.h
+ *
+ * @brief Portable NVRISC-V assembly macros
+ *
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS`` AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__ASM_HELPERS_H
+#define CPU__ASM_HELPERS_H
+#define FSP__CPU__ASM_HELPERS_H    1
+
+/*
+ * @file asm-helpers.h
+ * Macros to improve the portability of assembly code accross NVRISC-V
+ * architectures and improve the writing of assembly functions.
+ */
+
+/*
+ * @brief Macros to improve portability of assembly code
+ *
+ * @macro-title Portable Assembly Code
+ *
+ * @REGBYTES        Describes how many bytes per register
+ * @SREG            Instruction to store word from register
+ * @LREG            Instruction to load word into register
+ * @ZREG            Instruction to write zero into register
+ */
+#if (__riscv_xlen == 32U)
+#define REGBYTES    4U
+#define SREG        sw
+#define LREG        lw
+#else
+#define REGBYTES    8U
+#define SREG        sd
+#define LREG        ld
+#endif // (__riscv_xlen == 32)
+#define ZREG(rd)    mv rd, zero
+
+/**
+ * @brief Assembly function setup
+ *
+ * Set up an assembly function with a specified name.
+ *
+ * @param[in] name      Name of the assembly function to set up
+ */
+.macro FUNC name
+   .global \name
+   \name :
+   .func \name, \name
+    .type \name, STT_FUNC
+.endm
+
+/**
+ * @brief Assembly function teardown
+ *
+ * Tear down an assembly function with a specified name.
+ *
+ * @param[in] name      Name of the assembly function to tear down
+ */
+.macro EFUNC name
+    .endfunc
+    .size \name, .-\name
+.endm
+
+#endif /* CPU__ASM_HELPERS_H */
+/** end of file **/
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/barriers.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/barriers.h
new file mode 100644
index 0000000..e0787bb
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/barriers.h
@@ -0,0 +1,116 @@
+/**
+ * @file barriers.h
+ *
+ * @brief NVRISC-V implementation of barrier unit
+ *
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__BARRIER_H
+#define CPU__BARRIER_H
+#define FSP__CPU__BARRIER_H                       1
+
+/**
+ * @file barriers.h
+ * @brief Definitions for various synchronization barriers
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/macros.h>                  // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <misc/ct-assert.h>               // for CT_ASSERT
+
+/* Late FSP headers */
+#include <cpu/fence.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__FENCE_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @brief A general description of the function
+ *
+ * A more detailed description of the function
+ */
+static inline void barrier_cache_op_complete(void)
+{
+    riscv_lw_fence_rw();
+}
+
+/**
+ * @brief A general description of the function
+ *
+ * A more detailed description of the function
+ */
+static inline void barrier_compiler(void) {}
+
+/**
+ * @brief A general description of the function
+ *
+ * A more detailed description of the function
+ */
+static inline void barrier_memory_order(void)
+{
+    riscv_lw_fence_rw();
+}
+
+/**
+ * @brief A general description of the function
+ *
+ * A more detailed description of the function
+ */
+static inline void barrier_memory_complete(void)
+{
+    riscv_fence_rw();
+}
+
+/**
+ * @brief A general description of the function
+ *
+ * A more detailed description of the function
+ */
+static inline void barrier_instruction_synchronization(void)
+{
+    riscv_fence_instr();
+}
+
+#endif /* CPU__BARRIER_H */
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/cache.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/cache.h
new file mode 100644
index 0000000..6d141e1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/cache.h
@@ -0,0 +1,279 @@
+/**
+ * @file cache.h
+ *
+ * @brief Cache driver for NVRISC-V dev
+ *
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__CACHE_H
+#define CPU__CACHE_H
+#define FSP__CPU__CACHE_H                       1
+
+/* Compiler headers */
+#include <stddef.h>
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for UNUSED_NONCONST_PTR
+#include <misc/bitops.h>                   // for BIT, EXTRACT, FSP__MISC__B...
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <misc/nvmisc_drf.h>               // for DRF macros
+#include <cpu/type-conversion.h>           // for fsp_c_v_ptr_to_uptr, FSP...
+#include <cpu/csr.h>                       // for CSR macros
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__NVMISC_DRF_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__TYPE_CONVERSION_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__CSR_H, "Header file missing or invalid.")
+
+/**
+ * @file cache.h
+ * @brief Interfaces for performing Cache operations.
+ */
+
+/**
+ * @brief Cache line size
+ */
+#define RISCV_CACHE_LINE_SIZE    64UL
+
+/**
+ * @brief Type to specify the kind of address to use
+ */
+typedef enum
+{
+	RISCV_ADDR_TYPE_VA = 0,
+	RISCV_ADDR_TYPE_PA = 1,
+} riscv_addr_type_t;
+
+/**
+ * @brief Disable all caches
+ *
+ * This function will disable the iCache and dCache.  It will also ensure
+ * before this function returns.
+ *
+ * @note
+ * - M-mode only.
+ * - Should we have to do an explicit check or assert for M-mode.
+ * - Currently not implemented because there was no previous implementation in
+ *   libnvriscv.
+ */
+static inline void
+cache_disable(void) {}
+
+/**
+ * @brief Enable all caches
+ *
+ * This function will enable the iCache and dCache.  It will ensure that
+ * the contents of the caches are invalid (e.g. there is no data or instructions
+ * in the cache) before enabling the caches.
+ *
+ * @note
+ * - M-mode only.
+ * - Should we have to do an explicit check or assert for M-mode.
+ * - Currently not implemented because there was no previous implementation in
+ *   libnvriscv.
+ */
+static inline void
+cache_enable(void) {}
+
+/**
+ * @brief Invalidate the entire iCache
+ *
+ * This function will cause the entire icache contents to be invalidated.
+ */
+static inline void
+icache_invalidate_all(void)
+{
+    __asm__ volatile("fence.i");
+}
+
+/**
+ * @brief Invalidate a region of dCache
+ *
+ * This function will cause the specified region in the dCache to be
+ * invalidated.  That is, that data will no longer reside in the dCache
+ * at the completion of this function.
+ *
+ * If the specified range does not align with integral numbers of
+ * cache lines, more data may be invalidated than was actually specified.
+ *
+ * @param[in] base      Address of start of range to be invalidated
+ * @param[in] length    Number of bytes in the range to be invalidated
+ */
+static inline void
+dcache_invalidate(const void * const base, const size_t length)
+{
+    uintptr_t start;
+    uintptr_t end;
+
+    start = fsp_c_v_ptr_to_uptr(base);
+    end = start + ((uintptr_t)length);
+
+    start = (start & DRF_SHIFTMASK64(NV_RISCV_CSR_XDCACHEOP_ADDR)) |
+                DRF_DEF64(_RISCV_CSR, _XDCACHEOP, _ADDR_MODE, _VA) |
+                DRF_DEF64(_RISCV_CSR, _XDCACHEOP, _MODE, _INV_LINE);
+
+    for (;start < end; start += RISCV_CACHE_LINE_SIZE)
+    {
+        __asm__ volatile("csrrw x0, %0, %1" : :"i"(NV_RISCV_CSR_XDCACHEOP), "r"(start));
+    }
+}
+
+/**
+ * @brief Invalidate region of dCache using either PA or VA
+ *
+ * This function will cause the specified region in the dCache to be
+ * invalidated.  That is, that data will no longer reside in the dCache
+ * at the completion of this function.
+ *
+ * The addresses to invalidate may be specified to be either a
+ * virtual address or a physical address.
+ *
+ * If the specified range does not align with integral numbers of
+ * cache lines, more data may be invalidated than was actually specified.
+ *
+ * @param[in] base              Address of start of range to be invalidated
+ * @param[in] length            Number of bytes in the range to be invalidated
+ * @param[out] address_type     Type of address being passed as argument
+ */
+static inline void
+dcache_invalidate_address_type(const void * const base, const size_t length, riscv_addr_type_t address_type)
+{
+    uintptr_t start;
+    uintptr_t end;
+
+    start = fsp_c_v_ptr_to_uptr(base);
+    end = start + ((uintptr_t)length);
+
+    start = (start & DRF_SHIFTMASK64(NV_RISCV_CSR_XDCACHEOP_ADDR)) |
+                DRF_DEF64(_RISCV_CSR, _XDCACHEOP, _MODE, _INV_LINE);
+
+    // Set address mode depending address_type
+    if ( address_type == RISCV_ADDR_TYPE_VA)
+    {
+        start |= DRF_DEF64(_RISCV_CSR, _XDCACHEOP, _ADDR_MODE, _VA);
+    }
+    else if ( address_type == RISCV_ADDR_TYPE_PA )
+    {
+        start |= DRF_DEF64(_RISCV_CSR, _XDCACHEOP, _ADDR_MODE, _PA);
+    }
+    else
+    {
+        // Do nothing.
+    }
+
+    for (;start < end; start += RISCV_CACHE_LINE_SIZE)
+    {
+        __asm__ volatile("csrrw x0, %0, %1" : :"i"(NV_RISCV_CSR_XDCACHEOP), "r"(start));
+    }
+}
+
+/**
+ * @brief Invalidate entire dCache
+ *
+ * This function will cause the entire dCache to be invalidated
+ */
+static inline void
+dcache_invalidate_all(void)
+{
+    __asm__ volatile("csrrw x0, %0, %1" : :"i"(NV_RISCV_CSR_XDCACHEOP), "r"(0));
+}
+
+/**
+ * @brief Invalidate a region of dCache
+ *
+ * This function will cause the specified region in the dCache to be
+ * invalidated.  That is, that data will no longer reside in the dCache
+ * at the completion of this function.
+ *
+ * If the specified range does not align with integral numbers of
+ * cache lines, more data may be invalidated than was actually specified.
+ *
+ * @param[in] base      Address of start of range to be invalidated
+ * @param[in] length    Number of bytes in the range to be invalidated
+ *
+ * @deprecated dcache_invalidate() should be used instead.
+ */
+static inline void
+cache_invalidate(const void * const base, const size_t length)
+{
+    uintptr_t start;
+    uintptr_t end;
+
+    start = fsp_c_v_ptr_to_uptr(base);
+    end = start + ((uintptr_t)length);
+
+    start = (start & DRF_SHIFTMASK64(NV_RISCV_CSR_XDCACHEOP_ADDR)) |
+                DRF_DEF64(_RISCV_CSR, _XDCACHEOP, _ADDR_MODE, _VA) |
+                DRF_DEF64(_RISCV_CSR, _XDCACHEOP, _MODE, _INV_LINE);
+
+    for (;start < end; start += RISCV_CACHE_LINE_SIZE)
+    {
+        __asm__ volatile("csrrw x0, %0, %1" : :"i"(NV_RISCV_CSR_XDCACHEOP), "r"(start));
+    }
+}
+
+/**
+ * @brief Clean a region of dCache
+ *
+ * This function will cause any "dirty" data in the dCache in the
+ * specified range to be written back to memory.  The data may still
+ * reside in the dCache (e.g. it was not invalidated).
+ *
+ * If the specified range does not align with integral numbers of
+ * cache lines, more data may be "cleaned" than was actually specified.
+ *
+ * @param[in] base      Address of start of range to be cleaned
+ * @param[in] length    Number of bytes in the range to be cleaned
+ *
+ * @deprecated dcache_clean() should be used instead.
+ */
+#define cache_clean(base, length) ({ })
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif // FSP__CPU__CACHE_H
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/csr.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/csr.h
new file mode 100644
index 0000000..841af30
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/csr.h
@@ -0,0 +1,410 @@
+/**
+ * @file csr.h
+ *
+ * @brief NVRISC-V CSR Macros
+ *
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS`` AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__CSR_H
+#define CPU__CSR_H
+#define FSP__CPU__CSR_H                       1
+
+/*
+ * @file csr.h
+ * Macros to improve usability of NVRISC-V Control Status Register(s) (CSR).
+ * Provides CSRs with no operating mode that will be translated to the
+ * appropriate operating mode at compile-time. Also provides wrappers for
+ * CSR assembly functions for ease of use.
+ */
+
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+_Pragma("coverity compliance block(include) \
+         (deviate MISRA_C_2012_Rule_20_10 \"Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx\") \
+         (deviate MISRA_C_2012_Rule_2_5 \"Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx\")")
+#endif
+
+#if (__riscv_xlen == 32)
+#   include NVRISCV32_MANUAL_CSR
+#else
+#   include NVRISCV64_MANUAL_CSR
+#   ifndef NV_RISCV_CSR_MARCHID_ARCH_RST
+#       define NV_RISCV_CSR_MARCHID_ARCH_RST           ((NV_RISCV_CSR_MARCHID_MSB_RST         << 63UL) | \
+                                                        (NV_RISCV_CSR_MARCHID_RS1_RST         << 16UL) | \
+                                                        (NV_RISCV_CSR_MARCHID_CORE_MAJOR_RST  << 12UL) | \
+                                                        (NV_RISCV_CSR_MARCHID_CORE_MINOR_RST  <<  8UL))
+#       define NV_RISCV_CSR_MARCHID_ARCH_RST__SHIFTMASK 0xFFFFFFFFFFFFFF00ULL
+#   else
+#       define NV_RISCV_CSR_MARCHID_ARCH_RST__SHIFTMASK 0xFFFFFFFFFFFFFFFFULL
+#   endif
+#endif // (__riscv_xlen == 32)
+
+/*
+ * @brief Translate CSRX into appropriate operating mode
+ *
+ * macro-title CSRX Operating Mode Translation
+ *
+ * Table of prefixes:
+ *               NVRISCV_CONFIG_CPU_MODE
+ *        Macro  | 3 | 2 | 1 | 0 |
+ * NV_RISCV_CSRX | M |N/A| S |N/A|
+ * NV_RISCV_CSRU | M |N/A|   |N/A|
+ *
+ * @NV_RISCV_CSRX1(_A)              NV_RISCV_CSRX + _A
+ * @NV_RISCV_CSRX2(_A, _B)          NV_RISCV_CSRX + _A + _B
+ * @NV_RISCV_CSRX3(_A, _B, _C)      NV_RISCV_CSRX + _A + _B + _C
+ * @NV_RISCV_CSRU1(_A)              NV_RISCV_CSRU + _A
+ * @NV_RISCV_CSRU2(_A, _B)          NV_RISCV_CSRU + _A + _B
+ * @NV_RISCV_CSRU3(_A, _B, _C)      NV_RISCV_CSRU + _A + _B + _C
+ */
+#ifndef NVRISCV_CONFIG_CPU_MODE
+// If the kernel mode hasn't been defined, X versions default to M mode, and a warning is generated
+# warning "NVRISCV_CONFIG_CPU_MODE undefined, NV_RISCV_CSR_X* macros defaulting to M mode"
+# define NV_RISCV_CSRX1(_A)            NV_RISCV_CSR_M ## _A
+# define NV_RISCV_CSRX2(_A, _B)        NV_RISCV_CSR_M ## _A ## M ## _B
+# define NV_RISCV_CSRX3(_A, _B, _C)    NV_RISCV_CSR_M ## _A ## M ## _B ## M ## _C
+# define NV_RISCV_CSRU1(_A)            NV_RISCV_CSR_M ## _A
+# define NV_RISCV_CSRU2(_A, _B)        NV_RISCV_CSR_M ## _A ## M ## _B
+# define NV_RISCV_CSRU3(_A, _B, _C)    NV_RISCV_CSR_M ## _A ## M ## _B ## M ## _C
+#elif NVRISCV_CONFIG_CPU_MODE == 3
+// Machine mode
+# define NV_RISCV_CSRX1(_A)            NV_RISCV_CSR_M ## _A
+# define NV_RISCV_CSRX2(_A, _B)        NV_RISCV_CSR_M ## _A ## M ## _B
+# define NV_RISCV_CSRX3(_A, _B, _C)    NV_RISCV_CSR_M ## _A ## M ## _B ## M ## _C
+# define NV_RISCV_CSRU1(_A)            NV_RISCV_CSR_M ## _A
+# define NV_RISCV_CSRU2(_A, _B)        NV_RISCV_CSR_M ## _A ## M ## _B
+# define NV_RISCV_CSRU3(_A, _B, _C)    NV_RISCV_CSR_M ## _A ## M ## _B ## M ## _C
+#elif NVRISCV_CONFIG_CPU_MODE == 2
+// Hypervisor mode
+# error "Hypervisor mode unsupported"
+#elif NVRISCV_CONFIG_CPU_MODE == 1
+// Supervisor mode
+# define NV_RISCV_CSRX1(_A)            NV_RISCV_CSR_S ## _A
+# define NV_RISCV_CSRX2(_A, _B)        NV_RISCV_CSR_S ## _A ## S ## _B
+# define NV_RISCV_CSRX3(_A, _B, _C)    NV_RISCV_CSR_S ## _A ## S ## _B ## S ## _C
+# define NV_RISCV_CSRU1(_A)            NV_RISCV_CSR_ ## _A
+# define NV_RISCV_CSRU2(_A, _B)        NV_RISCV_CSR_ ## _A ## _B
+# define NV_RISCV_CSRU3(_A, _B, _C)    NV_RISCV_CSR_ ## _A ## _B ## _C
+#elif NVRISCV_CONFIG_CPU_MODE == 0
+// User mode
+# error "User mode unsupported"
+#endif
+
+//
+// These got renamed from UACCESSATTR to MACCESSATTR.
+// I believe they are otherwise completely identical.
+//
+// TODO VLAJA - rename to if NV_RISCV_CSR_MARCH_RST == 0 once manuals change
+#ifdef NV_RISCV_CSR_MFETCHATTR
+# define NV_RISCV_CSR_XACCESSATTR1(_A)  NV_RISCV_CSR_MLDSTATTR ## _A
+# define NV_RISCV_CSR_XACCESSATTR       NV_RISCV_CSR_MLDSTATTR
+#else
+# define NV_RISCV_CSR_XACCESSATTR1(_A)  NV_RISCV_CSR_UACCESSATTR ## _A
+# define NV_RISCV_CSR_XACCESSATTR       NV_RISCV_CSR_UACCESSATTR
+#endif
+
+#define NV_RISCV_CSR_XACCESSATTR_WPR__SHIFT \
+    NV_RISCV_CSR_XACCESSATTR1(_WPR__SHIFT)
+#define NV_RISCV_CSR_XACCESSATTR_WPR__SHIFTMASK \
+    NV_RISCV_CSR_XACCESSATTR1(_WPR__SHIFTMASK)
+#define NV_RISCV_CSR_XACCESSATTR_COHERENT__SHIFTMASK \
+    NV_RISCV_CSR_XACCESSATTR1(_COHERENT__SHIFTMASK)
+#define NV_RISCV_CSR_XACCESSATTR_CACHEABLE__SHIFTMASK \
+    NV_RISCV_CSR_XACCESSATTR1(_CACHEABLE__SHIFTMASK)
+
+//
+// Unified CSRs from manuals
+//
+// We provide X letter which will automatically expand to M/S
+//
+#define NV_RISCV_CSR_XMPU_PAGE_SIZE             NV_RISCV_CSR_MPU_PAGE_SIZE
+
+#define NV_RISCV_CSR_XCAUSE2                    NV_RISCV_CSRX1(CAUSE2)
+#define NV_RISCV_CSR_XTVEC                      NV_RISCV_CSRX1(TVEC)
+
+#define NV_RISCV_CSR_XCOUNTEREN                 NV_RISCV_CSRX1(COUNTEREN)
+#define NV_RISCV_CSR_XCOUNTEREN_TM              NV_RISCV_CSRX1(COUNTEREN_TM)
+#define NV_RISCV_CSR_XCOUNTEREN_TM_XMSB              NV_RISCV_CSRX1(COUNTEREN_TM_XMSB)
+#define NV_RISCV_CSR_XCOUNTEREN_TM_XLSB              NV_RISCV_CSRX1(COUNTEREN_TM_XLSB)
+#define NV_RISCV_CSR_XCOUNTEREN_CY              NV_RISCV_CSRX1(COUNTEREN_CY)
+#define NV_RISCV_CSR_XCOUNTEREN_CY_XMSB              NV_RISCV_CSRX1(COUNTEREN_CY_XMSB)
+#define NV_RISCV_CSR_XCOUNTEREN_CY_XLSB              NV_RISCV_CSRX1(COUNTEREN_CY_XLSB)
+#define NV_RISCV_CSR_XCOUNTEREN_IR              NV_RISCV_CSRX1(COUNTEREN_IR)
+#define NV_RISCV_CSR_XCOUNTEREN_IR_XMSB              NV_RISCV_CSRX1(COUNTEREN_IR_XMSB)
+#define NV_RISCV_CSR_XCOUNTEREN_IR_XLSB              NV_RISCV_CSRX1(COUNTEREN_IR_XLSB)
+
+#define NV_RISCV_CSR_XIE                        NV_RISCV_CSRX1(IE)
+#define NV_RISCV_CSR_XIE_XMSB                        NV_RISCV_CSRX1(IE_XMSB)
+#define NV_RISCV_CSR_XIE_XLSB                        NV_RISCV_CSRX1(IE_XLSB)
+#define NV_RISCV_CSR_XIE_XEIE                   NV_RISCV_CSRX2(IE_, EIE)
+#define NV_RISCV_CSR_XIE_XEIE_XMSB                   NV_RISCV_CSRX2(IE_, EIE_XMSB)
+#define NV_RISCV_CSR_XIE_XEIE_XLSB                   NV_RISCV_CSRX2(IE_, EIE_XLSB)
+#define NV_RISCV_CSR_XIE_XTIE                   NV_RISCV_CSRX2(IE_, TIE)
+#define NV_RISCV_CSR_XIE_XTIE_XMSB                   NV_RISCV_CSRX2(IE_, TIE_XMSB)
+#define NV_RISCV_CSR_XIE_XTIE_XLSB                   NV_RISCV_CSRX2(IE_, TIE_XLSB)
+#define NV_RISCV_CSR_XIE_XSIE                   NV_RISCV_CSRX2(IE_, SIE)
+#define NV_RISCV_CSR_XIE_XSIE_XMSB                   NV_RISCV_CSRX2(IE_, SIE_XMSB)
+#define NV_RISCV_CSR_XIE_XSIE_XLSB                   NV_RISCV_CSRX2(IE_, SIE_XLSB)
+
+#define NV_RISCV_CSR_XMPUATTR                   NV_RISCV_CSRX1(MPUATTR)
+#define NV_RISCV_CSR_XMPUIDX                    NV_RISCV_CSRX1(MPUIDX)
+#define NV_RISCV_CSR_XMPUIDX2                   NV_RISCV_CSRX1(MPUIDX2)
+#define NV_RISCV_CSR_XMPUIDX2_IDX               NV_RISCV_CSRX1(MPUIDX2_IDX)
+#define NV_RISCV_CSR_XMPUIDX2_IDX_XMSB               NV_RISCV_CSRX1(MPUIDX2_IDX_XMSB)
+#define NV_RISCV_CSR_XMPUIDX2_IDX_XLSB               NV_RISCV_CSRX1(MPUIDX2_IDX_XLSB)
+#define NV_RISCV_CSR_XMPUIDX_INDEX              NV_RISCV_CSRX1(MPUIDX_INDEX)
+#define NV_RISCV_CSR_XMPUIDX_INDEX_XMSB              NV_RISCV_CSRX1(MPUIDX_INDEX_XMSB)
+#define NV_RISCV_CSR_XMPUIDX_INDEX_XLSB              NV_RISCV_CSRX1(MPUIDX_INDEX_XLSB)
+#define NV_RISCV_CSR_XMPUVA                     NV_RISCV_CSRX1(MPUVA)
+#define NV_RISCV_CSR_XMPUPA                     NV_RISCV_CSRX1(MPUPA)
+#define NV_RISCV_CSR_XMPUPA_BASE                NV_RISCV_CSRX1(MPUPA_BASE)
+#define NV_RISCV_CSR_XMPUPA_BASE_XMSB                NV_RISCV_CSRX1(MPUPA_BASE_XMSB)
+#define NV_RISCV_CSR_XMPUPA_BASE_XLSB                NV_RISCV_CSRX1(MPUPA_BASE_XLSB)
+#define NV_RISCV_CSR_XMPURNG                    NV_RISCV_CSRX1(MPURNG)
+#define NV_RISCV_CSR_XMPURNG_RANGE              NV_RISCV_CSRX1(MPURNG_RANGE)
+#define NV_RISCV_CSR_XMPURNG_RANGE_XMSB              NV_RISCV_CSRX1(MPURNG_RANGE_XMSB)
+#define NV_RISCV_CSR_XMPURNG_RANGE_XLSB              NV_RISCV_CSRX1(MPURNG_RANGE_XLSB)
+#define NV_RISCV_CSR_XMPUATTR_WPR               NV_RISCV_CSRX1(MPUATTR_WPR)
+#define NV_RISCV_CSR_XMPUATTR_WPR_XMSB               NV_RISCV_CSRX1(MPUATTR_WPR_XMSB)
+#define NV_RISCV_CSR_XMPUATTR_WPR_XLSB               NV_RISCV_CSRX1(MPUATTR_WPR_XLSB)
+#define NV_RISCV_CSR_XMPUATTR_CACHEABLE         NV_RISCV_CSRX1(MPUATTR_CACHEABLE)
+#define NV_RISCV_CSR_XMPUATTR_CACHEABLE_XMSB         NV_RISCV_CSRX1(MPUATTR_CACHEABLE_XMSB)
+#define NV_RISCV_CSR_XMPUATTR_CACHEABLE_XLSB         NV_RISCV_CSRX1(MPUATTR_CACHEABLE_XLSB)
+#define NV_RISCV_CSR_XMPUATTR_COHERENT          NV_RISCV_CSRX1(MPUATTR_COHERENT)
+#define NV_RISCV_CSR_XMPUATTR_COHERENT_XMSB          NV_RISCV_CSRX1(MPUATTR_COHERENT_XMSB)
+#define NV_RISCV_CSR_XMPUATTR_COHERENT_XLSB          NV_RISCV_CSRX1(MPUATTR_COHERENT_XLSB)
+#define NV_RISCV_CSR_XMPUATTR_L2C_WR            NV_RISCV_CSRX1(MPUATTR_L2C_WR)
+#define NV_RISCV_CSR_XMPUATTR_L2C_WR_XMSB            NV_RISCV_CSRX1(MPUATTR_L2C_WR_XMSB)
+#define NV_RISCV_CSR_XMPUATTR_L2C_WR_XLSB            NV_RISCV_CSRX1(MPUATTR_L2C_WR_XLSB)
+#define NV_RISCV_CSR_XMPUATTR_L2C_RD            NV_RISCV_CSRX1(MPUATTR_L2C_RD)
+#define NV_RISCV_CSR_XMPUATTR_L2C_RD_XMSB            NV_RISCV_CSRX1(MPUATTR_L2C_RD_XMSB)
+#define NV_RISCV_CSR_XMPUATTR_L2C_RD_XLSB            NV_RISCV_CSRX1(MPUATTR_L2C_RD_XLSB)
+#define NV_RISCV_CSR_XMPUATTR_UR                NV_RISCV_CSRX1(MPUATTR_UR)
+#define NV_RISCV_CSR_XMPUATTR_UR_XMSB                NV_RISCV_CSRX1(MPUATTR_UR_XMSB)
+#define NV_RISCV_CSR_XMPUATTR_UR_XLSB                NV_RISCV_CSRX1(MPUATTR_UR_XLSB)
+#define NV_RISCV_CSR_XMPUATTR_XR                NV_RISCV_CSRX2(MPUATTR_, R)
+#define NV_RISCV_CSR_XMPUATTR_XR_XMSB                NV_RISCV_CSRX2(MPUATTR_, R_XMSB)
+#define NV_RISCV_CSR_XMPUATTR_XR_XLSB                NV_RISCV_CSRX2(MPUATTR_, R_XLSB)
+#define NV_RISCV_CSR_XMPUATTR_UW                NV_RISCV_CSRX1(MPUATTR_UW)
+#define NV_RISCV_CSR_XMPUATTR_UW_XMSB                NV_RISCV_CSRX1(MPUATTR_UW_XMSB)
+#define NV_RISCV_CSR_XMPUATTR_UW_XLSB                NV_RISCV_CSRX1(MPUATTR_UW_XLSB)
+#define NV_RISCV_CSR_XMPUATTR_XW                NV_RISCV_CSRX2(MPUATTR_, W)
+#define NV_RISCV_CSR_XMPUATTR_XW_XMSB                NV_RISCV_CSRX2(MPUATTR_, W_XMSB)
+#define NV_RISCV_CSR_XMPUATTR_XW_XLSB                NV_RISCV_CSRX2(MPUATTR_, W_XLSB)
+#define NV_RISCV_CSR_XMPUATTR_UX                NV_RISCV_CSRX1(MPUATTR_UX)
+#define NV_RISCV_CSR_XMPUATTR_UX_XMSB                NV_RISCV_CSRX1(MPUATTR_UX_XMSB)
+#define NV_RISCV_CSR_XMPUATTR_UX_XLSB                NV_RISCV_CSRX1(MPUATTR_UX_XLSB)
+#define NV_RISCV_CSR_XMPUATTR_XX                NV_RISCV_CSRX2(MPUATTR_, X)
+#define NV_RISCV_CSR_XMPUATTR_XX_XMSB                NV_RISCV_CSRX2(MPUATTR_, X_XMSB)
+#define NV_RISCV_CSR_XMPUATTR_XX_XLSB                NV_RISCV_CSRX2(MPUATTR_, X_XLSB)
+#define NV_RISCV_CSR_XMPUVA_VLD                 NV_RISCV_CSRX1(MPUVA_VLD)
+#define NV_RISCV_CSR_XMPUVA_VLD_XMSB                 NV_RISCV_CSRX1(MPUVA_VLD_XMSB)
+#define NV_RISCV_CSR_XMPUVA_VLD_XLSB                 NV_RISCV_CSRX1(MPUVA_VLD_XLSB)
+
+#define NV_RISCV_CSR_XSTATUS                    NV_RISCV_CSRX1(STATUS)
+#define NV_RISCV_CSR_XSTATUS_XIE                NV_RISCV_CSRX2(STATUS_, IE)
+#define NV_RISCV_CSR_XSTATUS_XIE_XMSB                NV_RISCV_CSRX2(STATUS_, IE_XMSB)
+#define NV_RISCV_CSR_XSTATUS_XIE_XLSB                NV_RISCV_CSRX2(STATUS_, IE_XLSB)
+#define NV_RISCV_CSR_XSTATUS_XIE_ENABLE         NV_RISCV_CSRX2(STATUS_, IE_ENABLE)
+#define NV_RISCV_CSR_XSTATUS_XIE_XTIE           NV_RISCV_CSRX3(STATUS_, IE_, TIE)
+#define NV_RISCV_CSR_XSTATUS_XIE_XTIE_XMSB           NV_RISCV_CSRX3(STATUS_, IE_, TIE_XMSB)
+#define NV_RISCV_CSR_XSTATUS_XIE_XTIE_XLSB           NV_RISCV_CSRX3(STATUS_, IE_, TIE_XLSB)
+#define NV_RISCV_CSR_XSTATUS_XPP                NV_RISCV_CSRX2(STATUS_, PP)
+#define NV_RISCV_CSR_XSTATUS_XPP_XMSB                NV_RISCV_CSRX2(STATUS_, PP_XMSB)
+#define NV_RISCV_CSR_XSTATUS_XPP_XLSB                NV_RISCV_CSRX2(STATUS_, PP_XLSB)
+#define NV_RISCV_CSR_XSTATUS_FS                 NV_RISCV_CSRX1(STATUS_FS)
+#define NV_RISCV_CSR_XSTATUS_FS_XMSB                 NV_RISCV_CSRX1(STATUS_FS_XMSB)
+#define NV_RISCV_CSR_XSTATUS_FS_XLSB                 NV_RISCV_CSRX1(STATUS_FS_XLSB)
+#define NV_RISCV_CSR_XSTATUS_FS_OFF             NV_RISCV_CSRX1(STATUS_FS_OFF)
+#define NV_RISCV_CSR_XSTATUS_FS_INITIAL         NV_RISCV_CSRX1(STATUS_FS_INITIAL)
+#define NV_RISCV_CSR_XSTATUS_FS_CLEAN           NV_RISCV_CSRX1(STATUS_FS_CLEAN)
+#define NV_RISCV_CSR_XSTATUS_FS_DIRTY           NV_RISCV_CSRX1(STATUS_FS_DIRTY)
+
+#define NV_RISCV_CSR_XDCACHEOP                  NV_RISCV_CSRU1(DCACHEOP)
+#define NV_RISCV_CSR_XDCACHEOP_ADDR             NV_RISCV_CSRU1(DCACHEOP_ADDR)
+#define NV_RISCV_CSR_XDCACHEOP_ADDR_XMSB             NV_RISCV_CSRU1(DCACHEOP_ADDR_XMSB)
+#define NV_RISCV_CSR_XDCACHEOP_ADDR_XLSB             NV_RISCV_CSRU1(DCACHEOP_ADDR_XLSB)
+#define NV_RISCV_CSR_XDCACHEOP_ADDR_MODE        NV_RISCV_CSRU1(DCACHEOP_ADDR_MODE)
+#define NV_RISCV_CSR_XDCACHEOP_ADDR_MODE_XMSB        NV_RISCV_CSRU1(DCACHEOP_ADDR_MODE_XMSB)
+#define NV_RISCV_CSR_XDCACHEOP_ADDR_MODE_XLSB        NV_RISCV_CSRU1(DCACHEOP_ADDR_MODE_XLSB)
+#define NV_RISCV_CSR_XDCACHEOP_ADDR_MODE_VA     NV_RISCV_CSRU1(DCACHEOP_ADDR_MODE_VA)
+#define NV_RISCV_CSR_XDCACHEOP_ADDR_MODE_PA     NV_RISCV_CSRU1(DCACHEOP_ADDR_MODE_PA)
+#define NV_RISCV_CSR_XDCACHEOP_MODE             NV_RISCV_CSRU1(DCACHEOP_MODE)
+#define NV_RISCV_CSR_XDCACHEOP_MODE_XMSB             NV_RISCV_CSRU1(DCACHEOP_MODE_XMSB)
+#define NV_RISCV_CSR_XDCACHEOP_MODE_XLSB             NV_RISCV_CSRU1(DCACHEOP_MODE_XLSB)
+#define NV_RISCV_CSR_XDCACHEOP_MODE_INV_LINE    NV_RISCV_CSRU1(DCACHEOP_MODE_INV_LINE)
+#define NV_RISCV_CSR_XFLUSH                     NV_RISCV_CSRU1(FLUSH)
+#define NV_RISCV_CSR_XSYSOPEN                   NV_RISCV_CSRX1(SYSOPEN)
+#define NV_RISCV_CSR_XMISCOPEN                  NV_RISCV_CSRX1(MISCOPEN)
+
+#define NV_RISCV_CSR_XCFG                       NV_RISCV_CSRX1(CFG)
+#define NV_RISCV_CSR_XCFG_XPOSTIO               NV_RISCV_CSRX2(CFG_, POSTIO)
+#define NV_RISCV_CSR_XCFG_XPOSTIO_XMSB               NV_RISCV_CSRX2(CFG_, POSTIO_XMSB)
+#define NV_RISCV_CSR_XCFG_XPOSTIO_XLSB               NV_RISCV_CSRX2(CFG_, POSTIO_XLSB)
+#define NV_RISCV_CSR_XCFG_XPOSTIO_TRUE          NV_RISCV_CSRX2(CFG_, POSTIO_TRUE)
+#define NV_RISCV_CSR_XCFG_XPOSTIO_FALSE         NV_RISCV_CSRX2(CFG_, POSTIO_FALSE)
+
+#define NV_RISCV_CSR_XRSP                       NV_RISCV_CSRX1(RSP)
+#define NV_RISCV_CSR_XRSP_XRSEC                 NV_RISCV_CSRX2(RSP_, RSEC)
+#define NV_RISCV_CSR_XRSP_XRSEC_XMSB                 NV_RISCV_CSRX2(RSP_, RSEC_XMSB)
+#define NV_RISCV_CSR_XRSP_XRSEC_XLSB                 NV_RISCV_CSRX2(RSP_, RSEC_XLSB)
+#define NV_RISCV_CSR_XRSP_XRSEC_INSEC           NV_RISCV_CSRX2(RSP_, RSEC_INSEC)
+#define NV_RISCV_CSR_XRSP_XRSEC_SEC             NV_RISCV_CSRX2(RSP_, RSEC_SEC)
+
+#define NV_RISCV_CSR_XSPM                       NV_RISCV_CSRX1(SPM)
+#define NV_RISCV_CSR_XSPM_XSECM                 NV_RISCV_CSRX2(SPM_, SECM)
+#define NV_RISCV_CSR_XSPM_XSECM_XMSB                NV_RISCV_CSRX2(SPM_, SECM_XMSB)
+#define NV_RISCV_CSR_XSPM_XSECM_XLSB                NV_RISCV_CSRX2(SPM_, SECM_XLSB)
+#define NV_RISCV_CSR_XSPM_XSECM_INSEC           NV_RISCV_CSRX2(SPM_, SECM_INSEC)
+#define NV_RISCV_CSR_XSPM_XSECM_SEC             NV_RISCV_CSRX2(SPM_, SECM_SEC)
+
+/**
+ * @brief CSR read
+ *
+ * Read from a CSR
+ *
+ * @param[in] csrnum    CSR address
+ *
+ * @return              value read from the CSR address
+ */
+#define csr_read(csrnum) ({ uint64_t _tmp; \
+    __asm__ volatile ("csrr %0, %1" : "=r"(_tmp) : "i"(csrnum)); \
+    _tmp; })
+
+/**
+ * @brief CSR write
+ *
+ * Write to a CSR
+ *
+ * @param[in] csrnum    CSR address
+ * @param[in] val       value to write
+ */
+#define csr_write(csrnum, val) ({ \
+    __asm__ volatile ("csrw %0, %1" ::"i"(csrnum), "r"(val)); })
+
+/**
+ * @brief CSR set
+ *
+ * Using a mask set the bits of a CSR
+ *
+ * @param[in] csrnum    CSR address
+ * @param[in] mask      bit mask
+ */
+#define csr_set(csrnum, mask) ({ \
+    __asm__ volatile ("csrs %0, %1" ::"i"(csrnum), "r"(mask)); })
+
+/**
+ * @brief CSR clear
+ *
+ * Using a mask clear the bits of a CSR
+ *
+ * @param[in] csrnum    CSR address
+ * @param[in] mask      bit mask
+ */
+#define csr_clear(csrnum, mask) ({ \
+    __asm__ volatile ("csrc %0, %1" ::"i"(csrnum), "r"(mask)); })
+
+/**
+ * @brief CSR atomic read and clear
+ *
+ * Atomic CSR read and clear
+ *
+ * @param[in] csrnum    CSR address
+ * @param[in] mask      bit mask
+ *
+ * @return              CSR value prior to clear
+ */
+#define csr_read_and_clear(csrnum, mask) ({ uint64_t _tmp; \
+    __asm__ volatile ("csrrc %0, %1, %2" : "=r"(_tmp) :"i"(csrnum), "r"(mask)); \
+    _tmp; })
+
+/**
+ * @brief CSR atomic read and set
+ *
+ * Atomic CSR read and set
+ *
+ * @param[in] csrnum    CSR address
+ * @param[in] mask      bit mask
+ *
+ * @return              CSR value prior to set
+ */
+#define csr_read_and_set(csrnum, mask) ({ uint64_t _tmp; \
+    __asm__ volatile ("csrrs %0, %1, %2" : "=r"(_tmp) :"i"(csrnum), "r"(mask)); \
+    _tmp; })
+
+/**
+ * @brief CSR atomic read and clear immediate
+ *
+ * Atomic CSR read and clear, where the mask is a 5-bit
+ * immediate.
+ *
+ * @param[in] csrnum    CSR address
+ * @param[in] mask      bit mask
+ *
+ * @return              CSR value prior to clear
+ */
+#define csr_read_and_clear_imm(csrnum, mask) ({ uint64_t _tmp; \
+    __asm__ volatile ("csrrc %0, %1, %2" : "=r"(_tmp) :"i"(csrnum), "i"(mask)); \
+    _tmp; })
+
+/**
+ * @brief CSR atomic read and set immediate
+ *
+ * Atomic CSR read and set, where the mask is a 5-bit
+ * immediate.
+ *
+ * @param[in] csrnum    CSR address
+ * @param[in] mask      bit mask
+ *
+ * @return              CSR value prior to set
+ */
+#define csr_read_and_set_imm(csrnum, mask) ({ uint64_t _tmp; \
+    __asm__ volatile ("csrrs %0, %1, %2" : "=r"(_tmp) :"i"(csrnum), "i"(mask)); \
+    _tmp; })
+
+/**
+ * @brief CSR atomic read and write immediate
+ *
+ * Atomic CSR read and write, where the mask is a 5-bit
+ * immediate.
+ *
+ * @param[in] csrnum    CSR address
+ * @param[in] mask      bit mask
+ *
+ * @return              CSR value prior to write
+ */
+#define csr_read_and_write_imm(csrnum, mask) ({ uint64_t _tmp; \
+    __asm__ volatile ("csrrwi %0, %1, %2" : "=r"(_tmp) :"i"(csrnum), "i"(mask)); \
+    _tmp; })
+
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+_Pragma("coverity compliance end_block(include) \
+         MISRA_C_2012_Rule_20_10 MISRA_C_2012_Rule_2_5")
+#endif
+
+#endif /* FSP__CPU__CSR_H */
+/** end of file **/
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/fence.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/fence.h
new file mode 100644
index 0000000..c2b6683
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/fence.h
@@ -0,0 +1,142 @@
+/**
+ * @file fence.h
+ *
+ * @brief NVRISC-V fence wrappers
+ *
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__FENCE_H
+#define CPU__FENCE_H
+#define FSP__CPU__FENCE_H                       1
+
+/*
+ * @file fence.h
+ * Lightweight fence, may not be coherent with rest of the system
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/macros.h>                  // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <misc/ct-assert.h>               // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/csr.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__CSR_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @brief lightweight io fence wrapper
+ */
+static inline void riscv_lw_fence_io(void)
+{
+    __asm__ volatile ("csrrw zero, %0, zero" : : "i"(NV_RISCV_CSR_LWFENCEIO));
+}
+
+/**
+ * @brief lightweight memory fence wrapper
+ */
+static inline void riscv_lw_fence_rw(void)
+{
+    __asm__ volatile ("csrrw zero, %0, zero" : : "i"(NV_RISCV_CSR_LWFENCEMEM));
+}
+
+/**
+ * @brief lightweight fence wrapper for io and memory
+ */
+static inline void riscv_lw_fence_rwio(void)
+{
+    __asm__ volatile ("csrrw zero, %0, zero" : : "i"(NV_RISCV_CSR_LWFENCEALL));
+}
+
+/**
+ * @brief heavy-weight io fence wrapper
+ */
+static inline void riscv_fence_io(void)
+{
+    __asm__ volatile ("fence io,io");
+}
+
+/**
+ * @brief heavy-weight memory fence wrapper
+ */
+static inline void riscv_fence_rw(void)
+{
+    __asm__ volatile ("fence rw,rw");
+}
+
+/**
+ * @brief heavy-weight fence wrapper for io and memory
+ */
+static inline void riscv_fence_rwio(void)
+{
+    __asm__ volatile ("fence iorw,iorw");
+}
+
+/**
+ * @brief heavy-weight supervisor fence wrapper
+ *
+ * Synchronize updates to in-memory management data structures
+ * with current execution.
+ *
+ * @param[in] asid      ASID value
+ * @param[in] vaddr     virtual address value
+ */
+static inline void riscv_sfence_vma(uint8_t asid, uint8_t vaddr)
+{
+    __asm__ volatile ("sfence.vma %0, %1" :: "r" (asid), "r" (vaddr));
+}
+
+/**
+ * @brief heavy-weight instruction fence
+ */
+static inline void riscv_fence_instr(void)
+{
+    __asm__ __volatile__("fence.i");
+}
+
+#endif /* FSP__CPU__FENCE_H */
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/sbi.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/sbi.h
new file mode 100644
index 0000000..9adb950
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/common/cpu/sbi.h
@@ -0,0 +1,330 @@
+/**
+ * @file sbi.h
+ *
+ * @brief NVRISC-V Software Binary Interface (SBI)
+ *
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS`` AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__SBI_H
+#define CPU__SBI_H
+#define FSP__CPU__SBI_H    1
+
+/*
+ * @file sbi.h
+ * NVRISC-V Software Binary Interface specification
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/gcc_attrs.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                   // for STR
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+_Static_assert(FSP__MISC__MACROS_H, "Header file missing or invalid.");
+
+//! @brief Standardized SBI error codes.
+typedef enum
+{
+    SBI_SUCCESS             = 0,
+    SBI_ERR_FAILURE         = -1,
+    SBI_ERR_NOT_SUPPORTED   = -2,
+    SBI_ERR_INVALID_PARAM   = -3,
+    SBI_ERR_DENIED          = -4,
+    SBI_ERR_INVALID_ADDRESS = -5,
+
+    SBI_ERROR_CODE__PADDING = -0x7FFFFFFFFFFFFFFFLL, // force to be signed 64bit type
+} SBI_ERROR_CODE;
+
+_Static_assert(sizeof(SBI_ERROR_CODE) == sizeof(int64_t), "SBI_ERROR_CODE size must be 8 bytes.");
+
+//! @brief SBI extension IDs.
+typedef enum
+{
+    /*! @brief Legacy set_timer extension
+     *
+     * void sbi_set_timer(uint64_t stime_value);
+     *
+     * @param[in]   stime_value     New mtimecmp value
+     */
+    SBI_EXTENSION_SET_TIMER = 0x00,
+
+    /*! @brief Legacy shutdown extension
+     *
+     * NORETURN void sbi_shutdown(void);
+     */
+    SBI_EXTENSION_SHUTDOWN = 0x08,
+
+    /*! @brief NVIDIA-specified extension.
+     *
+     * Function IDs are of the enum type SBI_NVIDIA_FUNCTION_ID.
+     */
+    SBI_EXTENSION_NVIDIA = 0x090001EB,
+} SBI_EXTENSION_ID;
+
+//! @brief NVIDIA-specific SBI functions.
+typedef enum
+{
+    SBI_NVFUNC_FIRST                 = 0,
+    SBI_NVFUNC_PARTITION_SWITCH      = 0,
+    SBI_NVFUNC_RELEASE_PRIV_LOCKDOWN = 1,
+    SBI_NVFUNC_TRACECTL_SET          = 2,
+    SBI_NVFUNC_FBIF_TRANSCFG_SET     = 3,
+    SBI_NVFUNC_FBIF_REGIONCFG_SET    = 4,
+    SBI_NVFUNC_TFBIF_TRANSCFG_SET    = 5,
+    SBI_NVFUNC_TFBIF_REGIONCFG_SET   = 6,
+} SBI_NVIDIA_FUNCTION_ID;
+
+//! @brief SBI return value structure.
+typedef struct
+{
+    //! @brief Error code.
+    int64_t error;
+    //! @brief Return value from the SBI call (or 0 if a void type SBI call).
+    int64_t value;
+} SBI_RETURN_VALUE;
+
+//-------------------------------------------------------------------------------------------------
+#define SBICALL GCC_ATTR_ALWAYSINLINE static inline
+#define CLOBBER_SBICALL "s0", "s1", "t0", "t1", "t2", "t3", "t4", "t5", "t6", "memory"
+/* For some reason marking TP and GP as clobbers doesn't actually work, so we manually save them */
+#define SBICALL_BODY \
+  "mv s0, gp\n" \
+  "mv s1, tp\n" \
+  "ecall\n" \
+  "mv tp, s1\n" \
+  "mv gp, s0\n" \
+
+/**
+ * @brief SBI Call
+ *
+ * @param[in] extension     sbi extension id
+ * @param[in] function      sbi function id
+ *
+ * @return                  sbi return struct
+ */
+SBICALL SBI_RETURN_VALUE sbicall0( int32_t extension, int32_t function )
+{
+    register int64_t a0_out __asm__( "a0" ) = 0L;
+    register int64_t a1_out __asm__( "a1" ) = 0L;
+
+    register int32_t a7 __asm__( "a7" ) = extension;
+    register int32_t a6 __asm__( "a6" ) = function;
+    __asm__ volatile (SBICALL_BODY
+                  : "+r"( a0_out ), "+r"( a1_out ), "+r"( a6 ), "+r"( a7 )
+                  :
+                  : "ra", CLOBBER_SBICALL, "a2", "a3", "a4", "a5");
+
+    return (SBI_RETURN_VALUE) { .error = a0_out, .value = a1_out };
+}
+
+/**
+ * @brief SBI Call with 1 Function Argument
+ *
+ * @param[in] extension     sbi extension id
+ * @param[in] function      sbi function id
+ * @param[in] arg0          function argument
+ *
+ * @return                  sbi return struct
+ */
+SBICALL SBI_RETURN_VALUE sbicall1( int32_t extension, int32_t function, uint64_t arg0 )
+{
+    register int64_t a0_out __asm__( "a0" ) = 0L;
+    register int64_t a1_out __asm__( "a1" ) = 0L;
+
+    register int32_t a7 __asm__( "a7" ) = extension;
+    register int32_t a6 __asm__( "a6" ) = function;
+    register uint64_t a0 __asm__( "a0" ) = arg0;
+    __asm__ volatile (SBICALL_BODY
+                  : "+r"( a0 ), "+r"( a1_out ), "+r"( a6 ), "+r"( a7 )
+                  :
+                  : "ra", CLOBBER_SBICALL, "a2", "a3", "a4", "a5");
+
+    return (SBI_RETURN_VALUE) { .error = a0_out, .value = a1_out };
+}
+
+/**
+ * @brief SBI Call with 2 Function Arguments
+ *
+ * @param[in] extension     sbi extension id
+ * @param[in] function      sbi function id
+ * @param[in] arg0..arg1    function arguments
+ *
+ * @return                  sbi return struct
+ */
+SBICALL SBI_RETURN_VALUE sbicall2( int32_t extension, int32_t function, uint64_t arg0, uint64_t arg1 )
+{
+    register int64_t a0_out __asm__( "a0" ) = 0L;
+    register int64_t a1_out __asm__( "a1" ) = 0L;
+
+    register int32_t a7 __asm__( "a7" ) = extension;
+    register int32_t a6 __asm__( "a6" ) = function;
+    register uint64_t a1 __asm__( "a1" ) = arg1;
+    register uint64_t a0 __asm__( "a0" ) = arg0;
+    __asm__ volatile (SBICALL_BODY
+                  : "+r"( a0 ), "+r"( a1 ), "+r"( a6 ), "+r"( a7 )
+                  :
+                  : "ra", CLOBBER_SBICALL, "a2", "a3", "a4", "a5");
+
+    return (SBI_RETURN_VALUE) { .error = a0_out, .value = a1_out };
+}
+
+/**
+ * @brief SBI Call with 3 Function Arguments
+ *
+ * @param[in] extension     sbi extension id
+ * @param[in] function      sbi function id
+ * @param[in] arg0..arg2    function arguments
+ *
+ * @return                  sbi return struct
+ */
+SBICALL SBI_RETURN_VALUE sbicall3( int32_t extension, int32_t function, uint64_t arg0, uint64_t arg1, uint64_t arg2 )
+{
+    register int64_t a0_out __asm__( "a0" ) = 0L;
+    register int64_t a1_out __asm__( "a1" ) = 0L;
+
+    register int32_t a7 __asm__( "a7" ) = extension;
+    register int32_t a6 __asm__( "a6" ) = function;
+    register uint64_t a2 __asm__( "a2" ) = arg2;
+    register uint64_t a1 __asm__( "a1" ) = arg1;
+    register uint64_t a0 __asm__( "a0" ) = arg0;
+    __asm__ volatile (SBICALL_BODY
+                  : "+r"( a0 ), "+r"( a1 ), "+r"( a2 ), "+r"( a6 ), "+r"( a7 )
+                  :
+                  : "ra", CLOBBER_SBICALL, "a3", "a4", "a5");
+
+    return (SBI_RETURN_VALUE) { .error = a0_out, .value = a1_out };
+}
+
+/**
+ * @brief SBI Call with 4 Function Arguments
+ *
+ * @param[in] extension     sbi extension id
+ * @param[in] function      sbi function id
+ * @param[in] arg0..arg3    function arguments
+ *
+ * @return                  sbi return struct
+ */
+SBICALL SBI_RETURN_VALUE sbicall4( int32_t extension, int32_t function, uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3 )
+{
+    register int64_t a0_out __asm__( "a0" ) = 0L;
+    register int64_t a1_out __asm__( "a1" ) = 0L;
+
+    register int32_t a7 __asm__( "a7" ) = extension;
+    register int32_t a6 __asm__( "a6" ) = function;
+    register uint64_t a3 __asm__( "a3" ) = arg3;
+    register uint64_t a2 __asm__( "a2" ) = arg2;
+    register uint64_t a1 __asm__( "a1" ) = arg1;
+    register uint64_t a0 __asm__( "a0" ) = arg0;
+    __asm__ volatile (SBICALL_BODY
+                  : "+r"( a0 ), "+r"( a1 ), "+r"( a2 ), "+r"( a3 ), "+r"( a6 ), "+r"( a7 )
+                  :
+                  : "ra", CLOBBER_SBICALL, "a4", "a5");
+
+    return (SBI_RETURN_VALUE) { .error = a0_out, .value = a1_out };
+}
+
+/**
+ * @brief SBI Call with 5 Function Arguments
+ *
+ * @param[in] extension     sbi extension id
+ * @param[in] function      sbi function id
+ * @param[in] arg0..arg4    function arguments
+ *
+ * @return                  sbi return struct
+ */
+SBICALL SBI_RETURN_VALUE sbicall5( int32_t extension, int32_t function, uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4 )
+{
+    register int64_t a0_out __asm__( "a0" ) = 0L;
+    register int64_t a1_out __asm__( "a1" ) = 0L;
+
+    register int32_t a7 __asm__( "a7" ) = extension;
+    register int32_t a6 __asm__( "a6" ) = function;
+    register uint64_t a4 __asm__( "a4" ) = arg4;
+    register uint64_t a3 __asm__( "a3" ) = arg3;
+    register uint64_t a2 __asm__( "a2" ) = arg2;
+    register uint64_t a1 __asm__( "a1" ) = arg1;
+    register uint64_t a0 __asm__( "a0" ) = arg0;
+    __asm__ volatile (SBICALL_BODY
+                  : "+r"( a0 ), "+r"( a1 ), "+r"( a2 ), "+r"( a3 ), "+r"( a4 ), "+r"( a6 ), "+r"( a7 )
+                  :
+                  : "ra", CLOBBER_SBICALL, "a5");
+
+    return (SBI_RETURN_VALUE) { .error = a0_out, .value = a1_out };
+}
+
+/**
+ * @brief SBI Call with 6 Function Arguments
+ *
+ * @param[in] extension     sbi extension id
+ * @param[in] function      sbi function id
+ * @param[in] arg0..arg5    function arguments
+ *
+ * @return                  sbi return struct
+ */
+SBICALL SBI_RETURN_VALUE sbicall6( int32_t extension, int32_t function, uint64_t arg0, uint64_t arg1, uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5 )
+{
+    register int64_t a0_out __asm__( "a0" ) = 0L;
+    register int64_t a1_out __asm__( "a1" ) = 0L;
+
+    register int32_t a7 __asm__( "a7" ) = extension;
+    register int32_t a6 __asm__( "a6" ) = function;
+    register uint64_t a5 __asm__( "a5" ) = arg5;
+    register uint64_t a4 __asm__( "a4" ) = arg4;
+    register uint64_t a3 __asm__( "a3" ) = arg3;
+    register uint64_t a2 __asm__( "a2" ) = arg2;
+    register uint64_t a1 __asm__( "a1" ) = arg1;
+    register uint64_t a0 __asm__( "a0" ) = arg0;
+    __asm__ volatile (SBICALL_BODY
+                  : "+r"( a0 ), "+r"( a1 ), "+r"( a2 ), "+r"( a3 ), "+r"( a4 ), "+r"( a5 ), "+r"( a6 ), "+r"( a7 )
+                  :
+                  : "ra", CLOBBER_SBICALL);
+
+    return (SBI_RETURN_VALUE) { .error = a0_out, .value = a1_out };
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif /* CPU__SBI_H */
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/cpu/devicemap.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/cpu/devicemap.h
new file mode 100644
index 0000000..e1ef5af
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/cpu/devicemap.h
@@ -0,0 +1,84 @@
+/**
+ * @file        devicemap.h
+ * @brief       Interfaces for the Peregrine Device Map.
+ *
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__DEVICEMAP_H
+#define CPU__DEVICEMAP_H
+#define FSP__CPU__DEVICEMAP_H 1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for HEADER_CHECK
+
+/* Hardware headers */
+
+/* Late FSP headers */
+// Clients must provide their own DRF headers.
+
+/* Module-specific FSP headers */
+#include <cpu/io.h>                     // for local_read
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The HEADER_CHECK macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+HEADER_CHECK(FSP__CPU__IO_H)
+
+
+/**
+ * @brief Checks access to a given device-map group.
+ *
+ * Checks whether the given operating mode (MMODE / SUBMMODE) has the
+ * requested access rights (READ / WRITE) to the specified device-map group.
+ *
+ * @param[in] mode  The operating mode to check (e.g. MMODE).
+ * @param[in] group The target device-map group (e.g. SCP).
+ * @param[in] type  The desired access type (e.g. READ).
+ *
+ * @retval true  if access is permitted.
+ * @retval false if access is denied.
+ */
+#define DEVICEMAP_HAS_ACCESS(mode, group, type) (                           \
+    FLD_IDX_TEST_DRF(_PRGNLCL_RISCV, _DEVICEMAP_RISCV##mode, _##type,       \
+        NV_PRGNLCL_DEVICE_MAP_GROUP_##group, _ENABLE,                       \
+        local_read(NV_PRGNLCL_RISCV_DEVICEMAP_RISCV##mode(                  \
+            NV_PRGNLCL_DEVICE_MAP_GROUP_##group /                           \
+            NV_PRGNLCL_RISCV_DEVICEMAP_RISCV##mode##_##type##__SIZE_1)))    \
+)
+
+#endif // CPU__DEVICEMAP_H
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/cpu/iopmp.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/cpu/iopmp.h
new file mode 100644
index 0000000..2fb2531
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/cpu/iopmp.h
@@ -0,0 +1,116 @@
+/**
+ * @file        iopmp.h
+ * @brief       Interfaces for the Peregrine IO-PMP controls.
+ *
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__IOPMP_H
+#define CPU__IOPMP_H
+#define FSP__CPU__IOPMP_H 1
+
+/* Compiler headers */
+#include <stdbool.h>                    // for bool
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for HEADER_CHECK
+
+/* Hardware headers */
+
+/* Late FSP headers */
+// Clients must provide their own DRF headers
+
+/* Module-specific FSP headers */
+#include <cpu/io.h>                     // for local_read
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The HEADER_CHECK macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+HEADER_CHECK(FSP__CPU__IO_H)
+
+
+/**
+ * @brief Temporary work-around for typo in PRGNLCL manual (bug #3394780).
+ */
+#ifndef NV_PRGNLCL_RISCV_IOPMP_ERR_STAT_VALID_TRUE
+#define NV_PRGNLCL_RISCV_IOPMP_ERR_STAT_VALID_TRUE \
+    NV_PRGNLCL_RISCV_IOPMP_ERR_STAT_VALID_TURE
+#endif
+
+
+/**
+ * @brief Checks whether error-capture is enabled for a given IO-PMP master.
+ *
+ * @param[in] master  The IO-PMP master to check (e.g. CPDMA).
+ *
+ * @retval true  if error-capture is enabled.
+ * @retval false if error-capture is disabled.
+ *
+ * @note Does not support vectored masters (use the _IDX variant instead).
+ */
+#define IOPMP_IS_CAPTURE_ENABLED(master) (                                    \
+    FLD_TEST_DRF(_PRGNLCL_RISCV, _IOPMP_ERR_CAPEN, _MASTER_##master, _ENABLE, \
+        local_read(NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN))                         \
+)
+
+/**
+ * @brief Checks whether error-capture is enabled for a vectored IO-PMP master.
+ *
+ * @param[in] master  The vectored IO-PMP master to check (e.g. PMB).
+ * @param[in] index   The index of the desired vector entry.
+ *
+ * @retval true  if error-capture is enabled.
+ * @retval false if error-capture is disabled.
+ */
+#define IOPMP_IS_CAPTURE_ENABLED_IDX(master, index) (                       \
+    FLD_IDX_TEST_DRF(_PRGNLCL_RISCV, _IOPMP_ERR_CAPEN, _MASTER_##master,    \
+        (index), _ENABLE, local_read(NV_PRGNLCL_RISCV_IOPMP_ERR_CAPEN))     \
+)
+
+
+/**
+ * @brief Checks whether an IO-PMP error is pending.
+ *
+ * @retval true  if an error is pending.
+ * @retval false otherwise.
+ */
+static inline bool
+iopmp_has_error(void)
+{
+    return FLD_TEST_DRF(_PRGNLCL_RISCV, _IOPMP_ERR_STAT, _VALID, _TRUE,
+        local_read(NV_PRGNLCL_RISCV_IOPMP_ERR_STAT));
+}
+
+#endif // CPU__IOPMP_H
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/cpu/peregrine.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/cpu/peregrine.h
new file mode 100644
index 0000000..3cc8845
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/cpu/peregrine.h
@@ -0,0 +1,128 @@
+/**
+ * @file peregrine.h
+ *
+ * @brief Engine-specific differences in Peregrine
+ *
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__PEREGRINE_H
+#define CPU__PEREGRINE_H
+#define FSP__CPU__PEREGRINE_H                       1
+
+/*!
+ * @file    engine.h
+ * @brief   This file hides header differences between different Peregrines.
+ */
+
+// Register headers
+#if (__riscv_xlen == 32)
+    #include NVRISCV32_MANUAL_LOCAL_IO
+#else
+    #include NVRISCV64_MANUAL_LOCAL_IO
+#endif // (__riscv_xlen == 32)
+
+#if defined(NVRISCV_IS_ENGINE_gsp)
+    #if (NVRISCV_HAS_PRI || NVRISCV_HAS_CSB_OVER_PRI)
+        #include <dev_falcon_v4.h>
+        #include <dev_riscv_pri.h>
+        #define FALCON_BASE   NV_FALCON_GSP_BASE
+    #endif
+    #if NVRISCV_HAS_PRI
+        #define RISCV_BASE    NV_FALCON2_GSP_BASE
+    #endif
+#elif defined(NVRISCV_IS_ENGINE_pmu)
+    #if (NVRISCV_HAS_PRI || NVRISCV_HAS_CSB_OVER_PRI)
+        #include <dev_falcon_v4.h>
+        #include <dev_riscv_pri.h>
+        #define FALCON_BASE   NV_FALCON_PWR_BASE
+    #endif
+    #if NVRISCV_HAS_PRI
+        #define RISCV_BASE    NV_FALCON2_PWR_BASE
+    #endif
+#elif defined(NVRISCV_IS_ENGINE_minion)
+    #if (NVRISCV_HAS_PRI || NVRISCV_HAS_CSB_OVER_PRI)
+        #include <dev_falcon_v4.h>
+        #include <dev_riscv_pri.h>
+        #define FALCON_BASE   NV_FALCON_MINION_BASE
+    #endif
+    #if NVRISCV_HAS_PRI
+        #define NV_FALCON2_MINION_BASE 0xA06400
+        #define RISCV_BASE    NV_FALCON2_MINION_BASE
+    #endif
+#elif defined(NVRISCV_IS_ENGINE_sec)
+    #if (NVRISCV_HAS_PRI || NVRISCV_HAS_CSB_OVER_PRI)
+        #include <dev_falcon_v4.h>
+        #include <dev_riscv_pri.h>
+        #define FALCON_BASE   0x840000
+    #endif
+    #if NVRISCV_HAS_PRI
+        #define RISCV_BASE    NV_FALCON2_SEC_BASE
+    #endif
+#elif defined(NVRISCV_IS_ENGINE_fsp)
+    #if (NVRISCV_HAS_PRI || NVRISCV_HAS_CSB_OVER_PRI)
+        #include <dev_falcon_v4.h>
+        #include <dev_riscv_pri.h>
+        #define FALCON_BASE   0x8F0000
+    #endif
+    #if NVRISCV_HAS_PRI
+        #define RISCV_BASE    NV_FALCON2_FSP_BASE
+    #endif
+#elif defined(NVRISCV_IS_ENGINE_nvdec)
+    #if (NVRISCV_HAS_PRI || NVRISCV_HAS_CSB_OVER_PRI)
+        #include <dev_falcon_v4.h>
+        #include <dev_riscv_pri.h>
+        // Use NVDEC0 base
+        #define FALCON_BASE   NV_FALCON_NVDEC0_BASE
+    #endif
+    #if NVRISCV_HAS_PRI
+        // Use NVDEC0 base
+        #define RISCV_BASE    NV_FALCON2_NVDEC0_BASE
+    #endif
+#elif NVRISCV_IS_ENGINE_soe
+    #if (NVRISCV_HAS_PRI || NVRISCV_HAS_CSB_OVER_PRI)
+        #include <dev_falcon_v4.h>
+        #include <dev_riscv_pri.h>
+        #define FALCON_BASE   0x840000
+    #endif
+    #if NVRISCV_HAS_PRI
+        #define RISCV_BASE    NV_FALCON2_SOE_BASE
+    #endif
+#elif NVRISCV_IS_ENGINE_pxuc
+    #if (NVRISCV_HAS_PRI || NVRISCV_HAS_CSB_OVER_PRI)
+        #include <dev_falcon_v4.h>
+        // TODO: restore to dev_riscv_pri.h when the FACLON2_*_BASE are restored
+        // bug 3575785
+        #include <dev_falcon_second_pri.h>
+        #define FALCON_BASE   0x828000
+    #endif
+    #if NVRISCV_HAS_PRI
+        #define RISCV_BASE    (FALCON_BASE + NV_PPXUC_FALCON2_BASE)
+    #endif
+#endif
+
+#endif /* CPU__PEREGRINE_H  */
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/cpu/riscv-mpu-safertos.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/cpu/riscv-mpu-safertos.h
new file mode 100644
index 0000000..e9bcb8f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/cpu/riscv-mpu-safertos.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file provides the interfaces for the SafeRTOS MPU functions for
+ * ARMv7 CPUs (notably the Cortex R5)
+ */
+#ifndef CPU__RISCV_MPU_SAFERTOS_H
+#define CPU__RISCV_MPU_SAFERTOS_H
+#define FSP__CPU__RISCV_MPU_SAFERTOS_H           1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/nvrm_drf.h>
+
+/* Module-specific FSP headers */
+#include <riscv-mpu.h>                                  /* Immune from CT_ASSERT protection */
+#include <cpu/riscv-mpu.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__MISC__NVRM_DRF_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__CPU__RISCV_MPU_H, "Header file missing or invalid.")
+
+/**
+ * @file riscv-mpu-safertos.h
+ * @brief Definitions and interfaces to use the MPU under SafeRTOS
+ *
+ * This file provides definitions, data structures and interfaces that
+ * are necessary for an application to use the MPU driver.
+ */
+
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/cpu/riscv-mpu.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/cpu/riscv-mpu.h
new file mode 100644
index 0000000..65c6077
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/cpu/riscv-mpu.h
@@ -0,0 +1,337 @@
+/*
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__RISCV_MPU_H
+#define CPU__RISCV_MPU_H
+#define FSP__CPU__RISCV_MPU_H                    1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <error/common-errors.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/bitops.h>
+#include <misc/macros.h>
+#include <cpu/csr.h>
+// clients must provide their own DRF headers
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @file riscv-mpu.h
+ * @brief Defines for the register layout of the MPU
+ */
+
+//
+// maximum number of entries provided by hardware.
+// The actual number of entries available in S mode may be smaller
+//
+//
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_20_10, "Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @brief This is the number of HW MPU entries.
+ */
+#define NV_RISCV_CSR_MPU_ENTRY_COUNT        (1U << DRF_SIZE(NV_RISCV_CSR_SMPUIDX_INDEX))
+
+/**
+ * @brief This is the index of the last HW MPU entry.
+ */
+#define NV_RISCV_CSR_MPU_ENTRY_MAX          (NV_RISCV_CSR_MPU_ENTRY_COUNT - 1U)
+
+/**
+ * @brief This is the page size which all to which all MPU Mappings' virtual address,
+ * physical address and size must be aligned.
+ */
+#define NV_RISCV_CSR_MPU_PAGE_SIZE          (1ULL << DRF_SHIFT64(NV_RISCV_CSR_SMPUPA_BASE))
+
+/**
+ * @brief This can be used to mask the lower bits of an address, which are an offset
+ * within the MPU page.
+ */
+#define NV_RISCV_CSR_MPU_PAGE_MASK          ((uint64_t)NV_RISCV_CSR_MPU_PAGE_SIZE - 1ULL)
+
+/**
+ * @brief This can be used to mask the upper bits of an address, which constitute an
+ * MPU page.
+ */
+#define NV_RISCV_CSR_MPU_ADDRESS_MASK       DRF_SHIFTMASK64(NV_RISCV_CSR_SMPUPA_BASE)
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_20_10, "Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @brief A handle to an MPU Entry. After being reserved by the MPU driver, the client
+ * can pass this handle into other MPU driver APIs to perform operations on this MPU entry.
+ */
+typedef uint32_t mpu_handle_t;
+
+/**
+ * @brief Context used by the MPU driver. The client should treat this as an opaque object
+ * and pass it into MPU driver APIs without directly touching its contents.
+ *
+ * ``mpu_entry_count``: The number of MPU entries owned by this S-mode partition. This is an
+ * internal field which should not be used by the client.
+ *
+ * ``mpu_reserved_bitmap``: Used by the driver to track the MPU Entry allocations. This is an
+ * internal field which should not be used by the client.
+ */
+typedef struct {
+    uint8_t mpu_entry_count;
+    bitmap_element_t mpu_reserved_bitmap[NV_RISCV_CSR_MPU_ENTRY_COUNT / BITMAP_ELEMENT_SIZE];
+} mpu_context_t;
+
+/**
+ * @brief Initializes the MPU driver. This function should be called before any other MPU
+ * driver APIs to initialize the MPU driver. Some MPU mappings may have been created before
+ * the driver initializes (eg: Bootloader), and this function will synchronize the driver's
+ * software state with the hardware state.
+ *
+ * This function should only be called once for each partition, and there should be only
+ * a single context for each partition. The caller should not allocate/use multiple contexts.
+ *
+ * @param[in] p_ctx A context struct which has been allocated by the caller.
+ *      mpu_init will populate it and the caller will pass it into subsequent MPU driver calls.
+ * @return E_SUCCESS on success
+ *         E_INVALID_PARAM if p_ctx is NULL
+ */
+error_t mpu_init(mpu_context_t *p_ctx);
+
+/**
+ * @brief Enables the MPU. This function should be called in use cases where the MPU hasn't
+ * already been enabled by the bootloader.
+ *
+ * @pre The client must call mpu_init and set up some MPU mappings for
+ * code/data prior to calling this. At the very least, the client should set up an identity
+ * mapping for the code region calling mpu_enable, to allow code to continue executing after
+ * the enablement.
+ *
+ * @return E_SUCCESS on success
+ */
+error_t mpu_enable(void);
+
+/**
+ * @brief Reserve an MPU entry.
+ *
+ * @pre The client must call mpu_init before calling this with the same mpu_context_t.
+ *
+ * @param[in] p_ctx A context struct which has been allocated by the caller and initialized by mpu_init.
+ * @param[in] search_origin is the lowest MPU index that can be reserved.
+ * Valid range: 0 to NV_RISCV_CSR_MPU_ENTRY_MAX
+ * @param[out] p_reserved_handle is a pointer to an mpu_handle_t where the reserved MPU Entry will be stored.
+ * @return E_SUCCESS if allcation succeeds
+ *         E_INVALID_PARAM if p_ctx or p_reserved_handle is NULL
+ *         E_FAULT if there are no free entries remaining
+ *
+ */
+error_t mpu_reserve_entry(mpu_context_t *p_ctx, uint32_t search_origin, mpu_handle_t *p_reserved_handle);
+
+/**
+ * @brief Free an MPU entry.
+ *
+ * @pre The client must have previously reserved this handle with mpu_reserve_entry.
+ *
+ * @param[in] p_ctx A context struct which has been allocated by the caller and initialized by mpu_init.
+ * @param[in] handle is a HW MPU entry. It has been previously reserved by mpu_reserve_entry.
+ * @return E_SUCCESS if freeing succeeds
+ *         E_INVALID_PARAM if p_ctx is NULL or handle is not an mpu_handle_t which has been reserved
+ * via mpu_reserve_entry and not already freed with a call to mpu_free_entry.
+ *
+ */
+error_t mpu_free_entry(mpu_context_t *p_ctx, mpu_handle_t handle);
+
+/**
+ * @brief Program a mapping into an MPU entry. pa and va and rng contain a
+ * NV_RISCV_CSR_MPU_PAGE_SIZE-aligned value in bits 10-63. The lower bits contain WPRIs and Valid bits.
+ * See the register manual for details.
+ *
+ * @pre The client must have previously reserved this handle with mpu_reserve_entry.
+ *
+ * @param[in] p_ctx A context struct which has been allocated by the caller and initialized by mpu_init.
+ * @param[in] handle indicates which entry to write. It has been previously reserved by mpu_reserve_entry.
+ * @param[in] va is the virtual address of the mapping, written directly into NV_RISCV_CSR_SMPUVA.
+ * Valid range: Any value. Bits 10-63 are the NV_RISCV_CSR_MPU_PAGE_SIZE-aligned address and the rest of
+ * the bits are flags in NV_RISCV_CSR_SMPUVA. Typically a client will use the NV_RISCV_CSR_SMPUVA_VLD bit
+ * to enable the entry.
+ * @param[in] pa is the physical address of the mapping, written directly into NV_RISCV_CSR_SMPUPA.
+ * Valid range: Any value. Bits 10-63 are the NV_RISCV_CSR_MPU_PAGE_SIZE-aligned address and the rest of
+ * the bits are ignored by the hardware.
+ * @param[in] rng is the range (length) of the mapping in bytes.
+ * Valid range: Any value. Bits 10-63 are the NV_RISCV_CSR_MPU_PAGE_SIZE-aligned size and the rest of
+ * the bits are ignored by the hardware.
+ * @param[in] attr are the attribute flags of the mapping, written directly into NV_RISCV_CSR_SMPUATTR.
+ * Valid range: Any value. Should be a combination of the NV_RISCV_CSR_SMPUATTR_x flags.
+ * @return E_SUCCESS if writing succeeds
+ *         E_INVALID_PARAM if p_ctx is NULL or handle is not a valid reserved handle
+ */
+error_t mpu_write_entry(const mpu_context_t *p_ctx, mpu_handle_t handle, uint64_t va, uint64_t pa, uint64_t rng, uint64_t attr);
+
+/**
+ * @brief Read a mapping from an MPU entry. Any of the pointer args may be set to NULL if the caller does not care about reading that value.
+ *
+ * @pre The client must have previously reserved this handle with mpu_reserve_entry.
+ *
+ * @param[in] p_ctx A context struct which has been allocated by the caller and initialized by mpu_init.
+ * @param[in] handle indicates which entry to read. It has been previously reserved by mpu_reserve_entry.
+ * @param[out] p_va is a pointer to a variable where the va value will be written.
+ *      This value is ORd with the enable bit (NV_RISCV_CSR_SMPUVA_VLD)
+ * @param[out] p_pa is a pointer to a variable where the pa value will be written
+ * @param[out] p_rng is a pointer to a variable where the rng value will be written
+ * @param[out] p_attr is a pointer to a variable where the attr value will be written
+ * @return E_SUCCESS if reading succeeds
+ *         E_INVALID_PARAM if p_ctx is NULL or handle is not a valid reserved handle
+ */
+error_t mpu_read_entry(const mpu_context_t *p_ctx, mpu_handle_t handle, uint64_t *p_va, uint64_t *p_pa, uint64_t *p_rng, uint64_t *p_attr);
+
+/**
+ * @brief Enable an MPU entry. The client does not need to call this if it has already
+ * called mpu_write_entry with the SMPUVA_VLD bit set. This API is mostly intended for
+ * re-enabling mappings which have been previously disabled via mpu_disable_entry.
+ *
+ * @pre The client must have previously reserved this handle with mpu_reserve_entry and written it with mpu_write_entry
+ *
+ * @param[in] p_ctx A context struct which has been allocated by the caller and initialized by mpu_init.
+ * @param[in] handle indicates which entry to enable. It has been previously reserved by mpu_reserve_entry
+ *         and written by mpu_write_entry
+ * @return E_SUCCESS if enablement succeeds
+ *         E_INVALID_PARAM if p_ctx is NULL or handle is not a valid reserved handle
+ */
+error_t mpu_enable_entry(const mpu_context_t *p_ctx, mpu_handle_t handle);
+
+/**
+ * @brief Disable an MPU entry.
+ *
+ * @pre The client must have previously reserved this handle with mpu_reserve_entry and written it with mpu_write_entry
+ *
+ * @param[in] p_ctx A context struct which has been allocated by the caller and initialized by mpu_init.
+ * @param[in] handle indicates which entry to disable. It has been previously reserved by mpu_reserve_entry,
+ *         and enabled with mpu_write_entry or mpu_enable_entry
+ * @return E_SUCCESS if disablement succeeds
+ *         E_INVALID_PARAM if p_ctx is NULL or handle is not a valid reserved handle
+ */
+error_t mpu_disable_entry(const mpu_context_t *p_ctx, mpu_handle_t handle);
+
+/**
+ * @brief Check whether the region mapped by an MPU entry has been accessed (read or executed)
+ * since the last time the Accessed bit was cleared.
+ *
+ * @pre The client must have previously reserved this handle with mpu_reserve_entry
+ *
+ * @param[in] p_ctx A context struct which has been allocated by the caller and initialized by mpu_init.
+ * @param[in] handle indicates which entry to check
+ * @param[out] b_accessed a pointer where the function will store whether the entry was accessed:
+ *         true if this region was read or executed since the last call to mpu_clear_accessed_bit
+ *         false if this region was not read or executed since the last call to mpu_clear_accessed_bit
+ * @return E_SUCCESS if access check succeeded
+ *         E_INVALID_PARAM if p_ctx or b_accessed is NULL or handle is not a valid reserved handle
+ */
+error_t mpu_is_accessed(const mpu_context_t *p_ctx, mpu_handle_t handle, bool *b_accessed);
+
+/**
+ * @brief Check whether the region mapped by an MPU entry has been written since the last time the
+ * Dirty bit was cleared.
+ *
+ * @pre The client must have previously reserved this handle with mpu_reserve_entry
+ *
+ * @param[in] p_ctx A context struct which has been allocated by the caller and initialized by mpu_init.
+ * @param[in] handle indicates which entry to check
+ * @param[out] b_dirty a pointer where the function will store whether the entry is dirty:
+ *         true if this region was written since the last call to mpu_clear_dirty_bit
+ *         false if this region was written since the last call to mpu_clear_dirty_bit
+ * @return E_SUCCESS if dirty check succeeded
+ *         E_INVALID_PARAM if p_ctx or b_dirty is NULL or handle is not a valid reserved handle
+ */
+error_t mpu_is_dirty(const mpu_context_t *p_ctx, mpu_handle_t handle, bool *b_dirty);
+
+/**
+ * @brief Clear the 'accessed' status of an MPU entry.
+ *
+ * @pre The client must have previously reserved this handle with mpu_reserve_entry
+ *
+ * @param[in] p_ctx A context struct which has been allocated by the caller and initialized by mpu_init.
+ * @param[in] handle indicates which entry to clear
+ * @return E_SUCCESS if dirty check succeeded
+ *         E_INVALID_PARAM if p_ctx is NULL or handle is not a valid reserved handle
+ */
+error_t mpu_clear_accessed_bit(const mpu_context_t *p_ctx, mpu_handle_t handle);
+
+/**
+ * @brief Clear the 'dirty' status of an MPU entry.
+ *
+ * @pre The client must have previously reserved this handle with mpu_reserve_entry
+ *
+ * @param[in] p_ctx A context struct which has been allocated by the caller and initialized by mpu_init.
+ * @param[in] handle indicates which entry to clear
+ * @return E_SUCCESS if dirty check succeeded
+ *         E_INVALID_PARAM if p_ctx is NULL or handle is not a valid reserved handle
+ */
+error_t mpu_clear_dirty_bit(const mpu_context_t *p_ctx, mpu_handle_t handle);
+
+/**
+ * @brief Translate a VA to a PA in software using the currently programmed MPU mappings. The translation
+ * is done by reading back the register values which have been programmed into the hardware. This may be
+ * an expensive operation.
+ *
+ * @pre The client must have previously reserved called mpu_init and created some entries.
+ *
+ * @param[in] p_ctx A context struct which has been allocated by the caller and initialized by mpu_init.
+ * @param[in] va is the virtual address to translate
+ * @param[out] p_pa is a pointer where the corresponding physical address will be stored
+ * @param[in] b_only_enabled if this is True, only the enabled MPU entries are searched,
+ *      otherwise, all reserved entries are searched
+ * @return E_SUCCESS if dirty check succeeded
+ *         E_INVALID_PARAM if p_ctx or p_pa is NULL or translation failed
+ */
+error_t mpu_va_to_pa(const mpu_context_t *p_ctx, uint64_t va, bool b_only_enabled, uint64_t *p_pa);
+
+#endif // CPU__RISCV_MPU_H
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/cpu_stdint.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/cpu_stdint.h
new file mode 100644
index 0000000..56f4142
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/cpu_stdint.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__CPU_STDINT_H
+#define CPU__CPU_STDINT_H
+#define FSP__CPU__CPU_STDINT_H                   1
+
+/* Compiler headers */
+#include <nvtypes.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/io.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/io.h
new file mode 100644
index 0000000..9ae79ac
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/io.h
@@ -0,0 +1,62 @@
+/**
+ * @file io.h
+ *
+ * @brief MMIO access to RISC-V/Peregrine apertures
+ *
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__IO_H
+#define CPU__IO_H
+#define FSP__CPU__IO_H                       1
+
+/**
+ * @file io.h
+ * @brief Provides access to Peregrine MMIO registers.
+ */
+
+#include <stdint.h>
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+#if NVRISCV_HAS_PRI
+#include <cpu/io_pri.h>
+#endif
+
+#if NVRISCV_HAS_CSB_MMIO
+#include <cpu/io_csb.h>
+#elif NVRISCV_HAS_PRI && NVRISCV_HAS_CSB_OVER_PRI
+uint32_t csb_read(uint32_t addr);
+void csb_write(uint32_t addr, uint32_t val);
+#endif
+
+#include <cpu/io_local.h>
+
+#if NVRISCV_HAS_DIO_SE || NVRISCV_HAS_DIO_SNIC || NVRISCV_HAS_DIO_FBHUB
+#include <cpu/io_dio.h>
+#endif
+
+#endif // CPU__IO_H
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/io_csb.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/io_csb.h
new file mode 100644
index 0000000..142c3d0
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/io_csb.h
@@ -0,0 +1,99 @@
+/**
+ * @file io_csb.h
+ *
+ * @brief RISC-V CSB access
+ *
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__IO_CSB_H
+#define CPU__IO_CSB_H
+#define FSP__CPU__IO_CSB_H                       1
+
+/**
+ * @file io_csb.h
+ * @brief Provides functions for accessing CSB aperture memory.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Late FSP headers */
+#include <cpu/mmio-access.h>            // for ioread32, iowrite32, ...
+
+/* NVRISCV conifgured headers */
+#if (__riscv_xlen == 32)
+#include NVRISCV32_MANUAL_ADDRESS_MAP
+#include NVRISCV32_MANUAL_LOCAL_IO
+#else
+#include NVRISCV64_MANUAL_ADDRESS_MAP
+#include NVRISCV64_MANUAL_LOCAL_IO
+#endif // (__riscv_xlen == 32)
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__CPU__MMIO_ACCESS_H, "Header file missing or invalid.")
+
+/**
+ * @brief Read from a CSB register
+ *
+ * @param[in] addr      address to read from within the aperture
+ *
+ * @return              contents of the register
+ */
+static inline uint32_t csb_read(uint32_t addr)
+{
+    return ioread32_offset(NV_RISCV_AMAP_INTIO_START, addr);
+}
+
+/**
+ * @brief Write to a CSB register
+ *
+ * @param[in] addr      address to read from within the aperture
+ * @param[in] val       value to write at the address
+ */
+static inline void csb_write(uint32_t addr, uint32_t val)
+{
+    iowrite32_offset(NV_RISCV_AMAP_INTIO_START, addr, val);
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif // CPU__IO_CSB_H
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/io_dio.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/io_dio.h
new file mode 100644
index 0000000..32ab9a5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/io_dio.h
@@ -0,0 +1,78 @@
+/* _NVRM_COPYRIGHT_BEGIN_
+ *
+ * Copyright 2021-2023 by NVIDIA Corporation.  All rights reserved.  All
+ * information contained herein is proprietary and confidential to NVIDIA
+ * Corporation.  Any use, reproduction, or disclosure without the written
+ * permission of NVIDIA Corporation is prohibited.
+ *
+ * _NVRM_COPYRIGHT_END_
+ */
+#ifndef CPU__IO_DIO_H
+#define CPU__IO_DIO_H
+#define FSP__CPU__IO_DIO_H                    1
+
+#include <error/common-errors.h>
+
+/* =============================================================================
+ * Public APIs
+ * ========================================================================== */
+#ifdef UTF_UCODE_BUILD
+extern uint32_t g_dio_max_wait;
+#define DIO_MAX_WAIT_DEFAULT 1U
+#endif
+
+typedef enum
+{
+    DIO_TYPE_INVALID = 0U,
+#if NVRISCV_HAS_DIO_SE
+    DIO_TYPE_SE,
+#endif // NVRISCV_HAS_DIO_SE
+#if NVRISCV_HAS_DIO_SNIC
+    DIO_TYPE_SNIC,
+#endif // NVRISCV_HAS_DIO_SNIC
+#if NVRISCV_HAS_DIO_FBHUB
+    DIO_TYPE_FBHUB,
+#endif // NVRISCV_HAS_DIO_FBHUB
+    DIO_TYPE_END
+} DIO_TYPE;
+
+typedef struct
+{
+    DIO_TYPE dio_type;
+    uint8_t port_idx;
+} DIO_PORT;
+
+typedef enum
+{
+    DIO_OPERATION_RD,
+    DIO_OPERATION_WR
+} DIO_OPERATION;
+
+
+/*!
+ * @brief   Perform one DIO read or write operation.
+ *
+ * @param[in]     port      container with one of the supported DIO type
+ * @param[in]     operation DIO_OPERATION_RD or DIO_OPERATION_WR
+ * @param[in]     addr      address
+ * @param[in/out] p_data    read back data for DIO_OPERATION_RD, or data input
+ *                          for DIO_OPERATION_WR.
+ *
+ * @return E_SUCCESS if operation finished successfully.
+ * @return E_NOTSUPPORTED if the combination of the inputs is not supported.
+ * @return E_TIMEOUT if operation timeout.
+ * @return E_FAULT if error reported through DOC_CTRL register.
+ * @return E_INVALID_PARAM if error reported through DOC_CTRL register and DIO_ERR_INFO
+ *         reports extra info.
+ */
+error_t
+dio_read_write
+(
+    DIO_PORT port,
+    DIO_OPERATION operation,
+    uint32_t addr,
+    uint32_t *p_data
+);
+
+#endif // CPU__IO_DIO_H
+/*** end of file ***/
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/io_local.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/io_local.h
new file mode 100644
index 0000000..9e58e33
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/io_local.h
@@ -0,0 +1,102 @@
+/**
+ * @file io_local.h
+ *
+ * @brief RISC-V LOCAL access
+ *
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__IO_LOCAL_H
+#define CPU__IO_LOCAL_H
+#define FSP__CPU__IO_LOCAL_H                       1
+
+/**
+ * @file io_local.h
+ * @brief Provides functions for accessing Local aperture memory.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/gcc_attrs.h>
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Late FSP headers */
+#include <cpu/mmio-access.h>            // for ioread32, iowrite32, ...
+
+#if (__riscv_xlen == 32)
+#include NVRISCV32_MANUAL_ADDRESS_MAP
+#include NVRISCV32_MANUAL_LOCAL_IO
+#else
+#include NVRISCV64_MANUAL_ADDRESS_MAP
+#include NVRISCV64_MANUAL_LOCAL_IO
+#endif // (__riscv_xlen == 32)
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__GCC_ATTRS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__MMIO_ACCESS_H, "Header file missing or invalid.")
+
+/**
+ * @brief Read from a local register using local IO offset
+ *
+ * @param[in] addr      address to read from within the aperture
+ *
+ * @return              contents of the register
+ */
+GCC_ATTR_ALWAYSINLINE
+static inline uint32_t local_read(uint32_t addr)
+{
+    return ioread32(addr);
+}
+
+/**
+ * @brief Write to a local register using local IO offset
+ *
+ * @param[in] addr      address to read from within the aperture
+ * @param[in] val       value to write at the address
+ */
+GCC_ATTR_ALWAYSINLINE
+static inline void local_write(uint32_t addr, uint32_t val)
+{
+    iowrite32(addr, val);
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif // CPU__IO_LOCAL_H
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/io_pri.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/io_pri.h
new file mode 100644
index 0000000..b7d09ac
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/io_pri.h
@@ -0,0 +1,149 @@
+/**
+ * @file io_pri.h
+ *
+ * @brief RISC-V PRI access
+ *
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__IO_PRI_H
+#define CPU__IO_PRI_H
+#define FSP__CPU__IO_PRI_H                       1
+
+/**
+ * @file io_pri.h
+ * @brief Provides functions for accessing PRI aperture memory.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/gcc_attrs.h>
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Late FSP headers */
+#include <cpu/peregrine.h>
+#include <cpu/mmio-access.h>            // for ioread32, iowrite32, ...
+
+/* NVRISCV conifgured headers */
+#include NVRISCV64_MANUAL_ADDRESS_MAP
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__GCC_ATTRS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__PEREGRINE_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__MMIO_ACCESS_H, "Header file missing or invalid.")
+
+/**
+ * @brief Read an arbitrary PRI register
+ *
+ * @param[in] addr      address to read from within the aperture
+ *
+ * @return              contents of the register
+ */
+GCC_ATTR_ALWAYSINLINE
+static inline uint32_t pri_read(uint32_t addr)
+{
+    return ioread32_offset(NV_RISCV_AMAP_PRIV_START, addr);
+}
+
+/**
+ * @brief Write to an arbitrary PRI register
+ *
+ * @param[in] addr      address to read from within the aperture
+ * @param[in] val       value to write at the address
+ */
+GCC_ATTR_ALWAYSINLINE
+static inline void pri_write(uint32_t addr, uint32_t val)
+{
+    iowrite32_offset(NV_RISCV_AMAP_PRIV_START, addr, val);
+}
+
+/**
+ * @brief Read from the Peregrine's Falcon block
+ *
+ * @param[in] addr      address to read from within the aperture
+ *
+ * @return              contents of the register
+ */
+GCC_ATTR_ALWAYSINLINE
+static inline uint32_t falcon_read(uint32_t offset)
+{
+    return ioread32_offset(FALCON_BASE, offset);
+}
+
+/**
+ * @brief Write to the Peregrine's Falcon block
+ *
+ * @param[in] addr      address to read from within the aperture
+ * @param[in] val       value to write at the address
+ */
+GCC_ATTR_ALWAYSINLINE
+static inline void falcon_write(uint32_t offset, uint32_t val)
+{
+    iowrite32_offset(FALCON_BASE, offset, val);
+}
+
+/**
+ * @brief Read from the Peregrine's RISC-V block
+ *
+ * @param[in] addr      address to read from within the aperture
+ *
+ * @return              contents of the register
+ */
+GCC_ATTR_ALWAYSINLINE
+static inline uint32_t riscv_read(uint32_t offset)
+{
+    return ioread32_offset(RISCV_BASE, offset);
+}
+
+/**
+ * @brief Write to the Peregrine's RISC-V block
+ *
+ * @param[in] addr      address to read from within the aperture
+ * @param[in] val       value to write at the address
+ */
+GCC_ATTR_ALWAYSINLINE
+static inline void riscv_write(uint32_t offset, uint32_t val)
+{
+    iowrite32_offset(RISCV_BASE, offset, val);
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif // CPU__IO_PRI_H
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/mmio-access.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/mmio-access.h
new file mode 100644
index 0000000..19646e2
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/mmio-access.h
@@ -0,0 +1,203 @@
+/* _NVRM_COPYRIGHT_BEGIN_
+ *
+ * Copyright 2021 by NVIDIA Corporation.  All rights reserved.  All
+ * information contained herein is proprietary and confidential to NVIDIA
+ * Corporation.  Any use, reproduction, or disclosure without the written
+ * permission of NVIDIA Corporation is prohibited.
+ *
+ * _NVRM_COPYRIGHT_END_
+ */
+
+#ifndef CPU__MMIO_ACCESS_H
+#define CPU__MMIO_ACCESS_H
+#define FSP__CPU__MMIO_ACCESS_H                         1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/type-conversion.h>
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-1579, DR: SWE-FSP-057-SWSADR.docx")
+CT_ASSERT(FSP__CPU__TYPE_CONVERSION_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file reg-access-nvgpu.h
+ * @brief functions that provide access to read and write the memory
+ * mapped hardware registers.
+ */
+
+/**
+ * @brief Read a 32-bit value from a memory mapped register
+ *
+ * @jama_func_req_id 8314409
+ *
+ * Provides an alias for 'readl' from <reg-access/reg-access.h>.
+ *
+ * This function will read a 32-bit value from the memory mapped register
+ * specified by the address parameter passed.
+ *
+ * @param[in] addr Address of the memory mapped register
+ *
+ * @return contents of the register
+ */
+static inline uint32_t ioread32(uintptr_t addr)
+{
+    return *fsp_upt_to_vl_u32_ptr(addr);
+}
+
+/**
+ * @brief Read a 32-bit value from a memory mapped register address
+ *
+ * @jama_func_req_id 8314409
+ *
+ * Provides an alias for 'readl_base_offset' from <reg-access/reg-access.h>.
+ *
+ * This function will read a 32-bit value from the memory mapped register
+ * specified by the address computed by the sum of the passed parameters
+ * base and offset.
+ *
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register
+ *
+ * @return contents of the register
+ */
+static inline uint32_t ioread32_offset(uintptr_t base, uint32_t offset)
+{
+    return ioread32(base+offset);
+}
+
+/**
+ * @brief Write a 32-bit value to a memory mapped register
+ *
+ * @jama_func_req_id 8314412
+ *
+ * Provides an alias for 'writel' from <reg-access/reg-access.h>.
+ *
+ * This function will write a 32-bit value to the memory mapped register
+ * specified by the address parameter passed.
+ *
+ * @param[in] addr Address of the memory mapped register
+ * @param[in] data value to be written to the memory mapped register
+ */
+static inline void iowrite32(uintptr_t addr, uint32_t data)
+{
+    *fsp_upt_to_vl_u32_ptr(addr) = data;
+}
+
+/**
+ * @brief Write a 32-bit value to a memory mapped register address
+ *
+ * @jama_func_req_id 8314412
+ *
+ * Provides an alias for 'writel_base_offset' from <reg-access/reg-access.h>.
+ *
+ * This function will write a 32-bit value to the memory mapped register
+ * address computed by the sum of the passed parameters base and offset.
+ *
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register; offset is immediate value
+ * @param[in] data value to be written to the memory mapped register
+ */
+static inline void iowrite32_offset(uintptr_t base, uint32_t offset, uint32_t data)
+{
+	iowrite32(base+offset, data);
+}
+
+/**
+ * @brief Read a 64-bit value from a memory mapped register
+ *
+ * @jama_func_req_id TBD
+ *
+ * This function will read a 64-bit value from the memory mapped register
+ * specified by the address parameter passed.
+ *
+ * @param[in] addr Address of the memory mapped register
+ *
+ * @return contents of the register
+ */
+static inline uint64_t ioread64(uintptr_t addr)
+{
+    return *fsp_upt_to_vl_u64_ptr(addr);
+}
+
+/**
+ * @brief Read a 64-bit value from a memory mapped register address
+ *
+ * @jama_func_req_id TBD
+ *
+ * This function will read a 64-bit value from the memory mapped register
+ * specified by the address computed by the sum of the passed parameters
+ * base and offset.
+ *
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register
+ *
+ * @return contents of the register
+ */
+static inline uint64_t ioread64_offset(uintptr_t base, uint32_t offset)
+{
+	return ioread64(base+offset);
+}
+
+/**
+ * @brief Write a 64-bit value to a memory mapped register
+ *
+ * @jama_func_req_id TBD
+ *
+ * This function will write a 64-bit value to the memory mapped register
+ * specified by the address parameter passed.
+ *
+ * @param[in] addr Address of the memory mapped register
+ * @param[in] data value to be written to the memory mapped register
+ */
+static inline void iowrite64(uintptr_t addr, uint64_t data)
+{
+    *fsp_upt_to_vl_u64_ptr(addr) = data;
+}
+
+/**
+ * @brief Write a 64-bit value to a memory mapped register address
+ *
+ * @jama_func_req_id TBD
+ *
+ * This function will write a 64-bit value to the memory mapped register
+ * address computed by the sum of the passed parameters base and offset.
+ *
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register; offset is immediate value
+ * @param[in] data value to be written to the memory mapped register
+ */
+static inline void iowrite64_offset(uintptr_t base, uint32_t offset, uint64_t data)
+{
+	iowrite64(base+offset, data);
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-1579, DR: SWE-FSP-057-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/perfctr.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/perfctr.h
new file mode 100644
index 0000000..118240a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/perfctr.h
@@ -0,0 +1,78 @@
+/**
+ * @file perfctr.h
+ *
+ * @brief Wrappers for riscv performance counter CSRs.
+ *
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef NVRISCV_PERFCTR_H
+#define NVRISCV_PERFCTR_H
+#include <stdint.h>
+#include <cpu/csr.h>
+
+/**
+ * @brief Atomically reads timer csr.
+ * @return Contents of time CSR.
+ *
+ * This register contains value of PTIMER (also available via PTIMER0/PTIMER1
+ * localIO registers).
+ *
+ * \warning This function requires permissions to execute.
+ * Invalid instruction exception will be thrown if they're not granted.
+ * - For M mode - it can always execute
+ * - For S mode, mcounteren.tm must be set
+ * - For U mode, mcounteren.tm and scounteren.tm must be set
+ */
+#define rdtime() csr_read(NV_RISCV_CSR_HPMCOUNTER_TIME)
+
+/**
+ * @brief Atomically reads cycle counter csr.
+ * @return Number of cpu cycles from arbitrary moment in time (RISC-V start)
+ *
+ * \warning This function requires permissions to execute.
+ * Invalid instruction exception will be thrown if they're not granted.
+ * - For M mode - it can always execute
+ * - For S mode, mcounteren.cy must be set
+ * - For U mode, mcounteren.cy and scounteren.cy must be set
+ */
+#define rdcycle() csr_read(NV_RISCV_CSR_HPMCOUNTER_CYCLE)
+
+/**
+ * @brief Atomically reads instruction retired counter csr.
+ * @return Number of instructions retired from arbitrary moment in time (RISC-V start)
+ *
+ * \warning This function requires permissions to execute.
+ * Invalid instruction exception will be thrown if they're not granted.
+ * - For M mode - it can always execute
+ * - For S mode, mcounteren.ir must be set
+ * - For U mode, mcounteren.ir and scounteren.ir must be set
+ */
+#define rdinstret() csr_read(NV_RISCV_CSR_HPMCOUNTER_INSTRET)
+
+#endif // NVRISCV_PERFCTR_H
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/ptimer.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/ptimer.h
new file mode 100644
index 0000000..9756cc7
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/ptimer.h
@@ -0,0 +1,59 @@
+/**
+ * @file ptimer.h
+ *
+ * @brief Chip-specific ptimer (main systick) read wrapper.
+ *
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIBNVRISCV_PTIMER_H
+#define LIBNVRISCV_PTIMER_H
+#include <stdint.h>
+#include <cpu/perfctr.h>
+
+#if NVRISCV_HAS_BINARY_PTIMER
+#define PTIMER_SHIFT 0
+#else // NVRISCV_HAS_BINARY_PTIMER
+#define PTIMER_SHIFT 5
+#endif // NVRISCV_HAS_BINARY_PTIMER
+
+/*!
+ * \brief Read 64-bit PTIMER
+ * \return PTIMER value (1ns resolution)
+ *
+ * This function reads PTIMER, avoiding non-trivial reads from two 32-bit
+ * localIO registers (PTIMER0/PTIMER1).
+ *
+ * \warning mcounteren.tm (for S- and U-mode) and scounteren.tm (for U-mode)
+ * must be set or this function will cause invalid instruction exception.
+ */
+static inline uint64_t ptimer_read(void)
+{
+    return rdtime() << PTIMER_SHIFT;
+}
+
+#endif // LIBNVRISCV_PTIMER_H
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/shutdown.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/shutdown.h
new file mode 100644
index 0000000..5c86aac
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/shutdown.h
@@ -0,0 +1,73 @@
+/**
+ * @file shutdown.h
+ *
+ * @brief NVRISC-V Shutdown API
+ *
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS`` AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__SHUTDOWN_H
+#define CPU__SHUTDOWN_H
+#define FSP__CPU__SHUTDOWN_H    1
+
+/*
+ * NVRISC-V Shutdown
+ * Functionality to halt or shutdown the NVRISC-V core.
+ */
+
+#include <misc/gcc_attrs.h>
+
+/**
+ * @brief Panic, fatal
+ *
+ * Halt or shut down the NVRISC-V core. Depending on the configured
+ * operating mode the code will either directly modify the registers (M)
+ * or use the SBI interface to send a request to the Separation Kernel (S).
+ * In the scenario that a proper shutdown fails the function will
+ * resort to an infinite loop in place.
+ *
+ * For additional security, the function is required to not use any
+ * stack memory.
+ */
+void riscv_panic(void) GCC_ATTR_NORETURN;
+
+/**
+ * @brief Gentle shutdown
+ *
+ * Properly shut down the NVRISC-V core. Depending on the configured
+ * operating mode the code will either directly modify the registers (M)
+ * or use the SBI interface to send a request to the Separation Kernel (S).
+ * In the scenario that a proper shutdown fails the function will
+ * resort to an infinite loop in place.
+ *
+ * For additional security, the function is required to not use any
+ * stack memory in M-mode.
+ */
+void riscv_shutdown(void) GCC_ATTR_NORETURN;
+
+#endif /* CPU__SHUTDOWN_H */
+/** end of file **/
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/type-conversion.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/type-conversion.h
new file mode 100644
index 0000000..f547d16
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/cpu/type-conversion.h
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CPU__TYPE_CONVERSION_H
+#define CPU__TYPE_CONVERSION_H
+#define FSP__CPU__TYPE_CONVERSION_H                     1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>
+#include <misc/macros.h>         // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Table of abbreviations:
+ *   These abbreviations are used in type conversions.  The following letters, or combinations of
+ *   letters, preceeded by an underscore, shall mean the following:
+ * _c       : const
+ * _ch      : char
+ * _fn      : function
+ * _i32     : int32_t
+ * _li      : long int
+ * _ptr     : pointer
+ * _st      : size_t
+ * _u8      : uint8_t
+ * _u32     : uint32_t
+ * _u64     : uint64_t
+ * _upt     : uintptr_t
+ * _v       : void
+ * _vl      : volatile
+ *
+ */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_19_2, "Approval: Bug 200543136, DR: SWE-FSP-033-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+/**
+ * Converts constant void pointer to constant char pointer.
+ *
+ * @param[in] ptr constant void pointer which will be coverted to constant char pointer.
+ * @param[out] ptr constant char pointer of constant void pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline const char *fsp_c_v_ptr_to_c_ch_ptr(const void *ptr)
+{
+    INLINE_RFD(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx");
+    return (const char *)ptr;
+}
+
+/**
+ * Converts void pointer to char pointer.
+ *
+ * @param[in] ptr void pointer which will be coverted to char pointer.
+ * @param[out] ptr char pointer of void pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline char *fsp_v_ptr_to_ch_ptr(void *ptr)
+{
+    INLINE_RFD(MISRA, DEVIATE, Rule_11_5, "Approval: Bug 200542277, DR:  SWE-FSP-024-SWSADR.docx");
+    return (char *)ptr;
+}
+
+/**
+ * Converts uintptr_t to volatile uint32_t pointer
+ *
+ * @param[in] addr unsigned integer which will be converted to volatile unsigned integer pointer.
+ * @param[out] value volatile unsigned integer pointer represented by unsigned integer addr
+ */
+static inline volatile uint32_t* fsp_upt_to_vl_u32_ptr(uintptr_t input)
+{
+    CT_ASSERT(FSP_ALIGNOF(uintptr_t) >= FSP_ALIGNOF(volatile uint32_t *), "ASSERT due to data misalignment.");
+    CT_ASSERT(sizeof(uintptr_t) == sizeof(volatile uint32_t *), "ASSERT due to incompatible data sizes.");
+    union cast_fsp_upt_to_vl_u32_ptr {
+        uintptr_t input;
+        volatile uint32_t *output;
+    };
+    union cast_fsp_upt_to_vl_u32_ptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts uintptr_t to volatile uint64_t pointer
+ *
+ * @param[in] addr unsigned integer which will be converted to volatile unsigned integer pointer.
+ * @param[out] value volatile unsigned integer pointer represented by unsigned integer addr
+ */
+static inline volatile uint64_t* fsp_upt_to_vl_u64_ptr(uintptr_t input)
+{
+    CT_ASSERT(FSP_ALIGNOF(uintptr_t) >= FSP_ALIGNOF(volatile uint64_t *), "ASSERT due to data misalignment.");
+    CT_ASSERT(sizeof(uintptr_t) == sizeof(volatile uint64_t *), "ASSERT due to incompatible data sizes.");
+    union cast_fsp_upt_to_vl_u64_ptr {
+        uintptr_t input;
+        volatile uint64_t *output;
+    };
+    union cast_fsp_upt_to_vl_u64_ptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts void pointer to uintptr_t
+ *
+ * @param[in] addr void pointer which will be coverted to uintptr_t
+ * @param[out] value uintptr_t value of void pointer.
+ */
+static inline uintptr_t fsp_v_ptr_to_uptr(void *input)
+{
+    CT_ASSERT(FSP_ALIGNOF(void *) >= FSP_ALIGNOF(uintptr_t *), "ASSERT due to data misalignment.");
+    CT_ASSERT(sizeof(void *) == sizeof(uintptr_t *), "ASSERT due to incompatible pointer sizes.");
+    union cast_fsp_v_ptr_to_uptr {
+        void *input;
+        uintptr_t output;
+    };
+    union cast_fsp_v_ptr_to_uptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts a constant void pointer to uintptr_t
+ *
+ * @param[in] addr const void pointer which will be coverted to uintptr_t
+ * @param[out] value uintptr_t value of void pointer.
+ */
+static inline uintptr_t fsp_c_v_ptr_to_uptr(const void *input)
+{
+    CT_ASSERT(FSP_ALIGNOF(const void *) >= FSP_ALIGNOF(uintptr_t *), "ASSERT due to data misalignment.");
+    CT_ASSERT(sizeof(const void *) == sizeof(uintptr_t *), "ASSERT due to incompatible pointer sizes.");
+    union cast_fsp_c_v_ptr_to_uptr {
+        const void *input;
+        uintptr_t output;
+    };
+    union cast_fsp_c_v_ptr_to_uptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts void pointer to struct uint8_t pointer.
+ *
+ * @param[in] input void pointer which will be coverted to uint8_t pointer.
+ * @param[out] output uint8_t pointer of void pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline uint8_t *fsp_v_ptr_to_u8_ptr(void *input)
+{
+CT_ASSERT(FSP_ALIGNOF(void *) >= FSP_ALIGNOF(uint8_t*), "ASSERT due to data misalignment.")
+    CT_ASSERT(sizeof(void *) == sizeof(uint8_t *), "ASSERT due to incompatible pointer sizes.")
+    union cast_fsp_v_ptr_to_u8_ptr {
+        void * input;
+        uint8_t *output;
+    };
+    union cast_fsp_v_ptr_to_u8_ptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts constant void pointer to struct constant uint8_t pointer.
+ *
+ * @param[in] input constant void pointer which will be coverted to constant uint8_t pointer.
+ * @param[out] output constant uint8_t pointer of constant void pointer.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_5_9, "Approval:  Bug 3255774, DR: SWE-FSP-056-SWSADR.docx")
+static inline const uint8_t *fsp_c_v_ptr_to_c_u8_ptr(const void *input)
+{
+CT_ASSERT(FSP_ALIGNOF(const void *) >= FSP_ALIGNOF(const uint8_t *), "ASSERT due to data misalignment.")
+    CT_ASSERT(sizeof(const void *) == sizeof(const uint8_t *), "ASSERT due to incompatible pointer sizes.")
+    union cast_fsp_c_v_ptr_to_c_u8_ptr {
+        const void * input;
+        const uint8_t *output;
+    };
+    union cast_fsp_c_v_ptr_to_c_u8_ptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_19_2, "Approval: Bug 200543136, DR: SWE-FSP-033-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/reg-access/reg-access.h b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/reg-access/reg-access.h
new file mode 100644
index 0000000..a7193ad
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/cpu/nvidia/riscv/nvriscv/reg-access/reg-access.h
@@ -0,0 +1,149 @@
+/* _NVRM_COPYRIGHT_BEGIN_
+ *
+ * Copyright 2014-2021 by NVIDIA Corporation.  All rights reserved.  All
+ * information contained herein is proprietary and confidential to NVIDIA
+ * Corporation.  Any use, reproduction, or disclosure without the written
+ * permission of NVIDIA Corporation is prohibited.
+ *
+ * _NVRM_COPYRIGHT_END_
+ */
+
+#ifndef REG_ACCESS__REG_ACCESS_H
+#define REG_ACCESS__REG_ACCESS_H
+#define FSP__REG_ACCESS__REG_ACCESS_H                   1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/mmio-access.h>      // for ioread32, iowrite32, ...
+#include <cpu/type-conversion.h>
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__CPU__MMIO_ACCESS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__TYPE_CONVERSION_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file reg-access.h
+ * @brief functions that provide access to read and write the memory
+ * mapped hardware registers.
+ */
+
+/**
+ * @brief Read a 32-bit value from a memory mapped register
+ *
+ * @jama_func_req_id 8314409
+ *
+ * This function will read a 32-bit value from the memory mapped register
+ * specified by the address parameter passed.
+ *
+ * @param[in] addr Address of the memory mapped register
+ *
+ * @return contents of the register
+ */
+static inline uint32_t readl(uint32_t addr)
+{
+    return ioread32(addr);
+}
+
+/**
+ * @brief Read a 32-bit value from a memory mapped register address
+ *
+ * @jama_func_req_id 8314409
+ *
+ * This function will read a 32-bit value from the memory mapped register
+ * specified by the address computed by the sum of the passed parameters
+ * base and offset.
+ *
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register
+ *
+ * @return contents of the register
+ */
+static inline uint32_t readl_base_offset(uint32_t base, uint32_t offset)
+{
+    return ioread32_offset(base, offset);
+}
+
+/**
+ * @brief Write a 32-bit value to a memory mapped register
+ *
+ * @jama_func_req_id 8314412
+ *
+ * This function will write a 32-bit value to the memory mapped register
+ * specified by the address parameter passed.
+ *
+ * @param[in] data value to be written to the memory mapped register
+ * @param[in] addr Address of the memory mapped register
+ *
+ * @return none
+ */
+static inline void writel(uint32_t data, uint32_t addr)
+{
+    iowrite32(addr, data);
+}
+
+/**
+ * @brief Write a 32-bit value to a memory mapped register address
+ *
+ * @jama_func_req_id 8314412
+ *
+ * This function will write a 32-bit value to the memory mapped register
+ * address computed by the sum of the passed parameters base and offset.
+ *
+ * @param[in] data value to be written to the memory mapped register
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register; offset is immediate value
+ *
+ * @return none
+ */
+static inline void writel_base_offset(uint32_t data, uint32_t base, uint32_t offset)
+{
+    iowrite32_offset(base, offset, data);
+}
+
+/**
+ * @brief Write a 32-bit value to a memory mapped register address
+ *
+ * @jama_func_req_id 8314412
+ *
+ * This function will write a 32-bit value to the memory mapped register
+ * address computed by the sum of the passed parameters base and offset.
+ *
+ * @param[in] data value to be written to the memory mapped register
+ * @param[in] base Base address of the memory mapped register
+ * @param[in] offset offset of the memory mapped register; offset is register value
+ *
+ * @return none
+ */
+static inline void writel_base_regoffset(uint32_t data, uint32_t base, uint32_t offset)
+{
+    iowrite32_regoffset(base, offset, data);
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/debug/abort-codes.h b/spe-freertos-bsp/fsp/source/include/debug/abort-codes.h
new file mode 100644
index 0000000..7d69980
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/debug/abort-codes.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DEBUG__ABORT_CODES_H
+#define DEBUG__ABORT_CODES_H
+#define FSP__DEBUG__ABORT_CODES_H                       1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <misc/bitops.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Abort codes are divided as follows:
+ * Bits         Field           Description
+ * 15-8         SUBSYSTEM       Which subsystem generated the Abort
+ * 7-0          CODE            Code which is specific to the sub-system
+ *
+ * The subsystems are free to define their own values for the CODE field.
+ * The values for the subsystem field are defined below along with various
+ * macros for constructing overall abort codes.
+ */
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_20_10, "Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx")
+#define MODULE_ABORT_ID(_id_)           (((uint32_t)(MODULE_ID_##_id_)) << 8UL)
+#define ABORT_CODE(_id_, _code_)        (MODULE_ABORT_ID(_id_)                  \
+                                         | (EXTRACT((_code_), 7UL, 0UL, uint32_t)))
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_20_10, "Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/debug/abort-sys-codes.h b/spe-freertos-bsp/fsp/source/include/debug/abort-sys-codes.h
new file mode 100644
index 0000000..933092f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/debug/abort-sys-codes.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DEBUG__ABORT_SYS_CODES_H
+#define DEBUG__ABORT_SYS_CODES_H
+#define FSP__DEBUG__ABORT_SYS_CODES_H                   1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "base/module-id.h"
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <debug/abort-codes.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__DEBUG__ABORT_CODES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+#define ABORT_RTOS              ABORT_CODE(ABORT, 0UL)
+#define ABORT_ASSERT            ABORT_CODE(ABORT, 1UL)
+#define ABORT_EXCEPTION         ABORT_CODE(ABORT, 2UL)
+#define ABORT_STACK             ABORT_CODE(ABORT, 3UL)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/debug/abort.h b/spe-freertos-bsp/fsp/source/include/debug/abort.h
new file mode 100644
index 0000000..cfab267
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/debug/abort.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef DEBUG__ABORT_H
+#define DEBUG__ABORT_H
+#define FSP__DEBUG__ABORT_H                             1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <osa/rtos-task.h>              // for rtosTaskHandle
+#include <misc/attributes.h>            // for NO_RETURN
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <error/common-errors.h>        // for error_t
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+void tegra_abort(const uint32_t reason,
+                 const uint32_t arg)          NO_RETURN;
+
+void
+abort_full(const uint32_t reason,
+           error_t xErrorCode,
+           rtosTaskHandle xHandleOfTaskWithError,
+           const char *pcErrorString)   NO_RETURN;
+
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx")
+#if defined(DEBUG_ABORTS) && (DEBUG_ABORTS==1)
+#define ABORT(_reason_, _arg_)          tegra_abort(_reason_, _arg_)
+#else
+#define ABORT(_reason_, _arg_)
+#endif
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/*
+ * Hook function that will be called when an abort occurs
+ */
+void abort_hook(const uint32_t reason,
+                error_t xErrorCode,
+                rtosTaskHandle xHandleOfTaskWithError,
+                const char *pcErrorString);
+
+/*
+ * Hook function supplied to SafeRTOS when it has a fatal error
+ */
+void error_hook(rtosTaskHandle xHandleOfTaskWithError,
+                const char *pcErrorString,
+                error_t xErrorCode)     NO_RETURN;
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/debug/assert.h b/spe-freertos-bsp/fsp/source/include/debug/assert.h
new file mode 100644
index 0000000..eff87da
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/debug/assert.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef DEBUG__ASSERT_H
+#define DEBUG__ASSERT_H
+#define FSP__DEBUG__ASSERT_H                            1
+
+/* Compiler headers */
+#include <stdint.h>                 // for uint32_t
+#include <stdbool.h>                // for bool
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>         // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>            // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <debug/abort.h>            // IWYU pragma: export
+                                    // IWYU pragma: no_include "debug/abort.h"
+#include <debug/abort-sys-codes.h>  // IWYU pragma: export
+                                    // IWYU pragma: no_include "debug/abort-sys-codes.h"
+#include <debug/sections-assert.h>  /* Immune from CT_ASSERT protection */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ABORT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ABORT_SYS_CODES_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+void fsp_assert(const bool assertion,
+            const char * const filename,
+            const uint32_t linenum)       SECTION_ASSERT_TEXT;
+
+#if defined(DEBUG_ASSERTS) && (DEBUG_ASSERTS==1)
+#define ASSERT(_b_)                                                             \
+        {                                                                       \
+        static const char f[] USED SECTION_ASSERT_RODATA = __FILE__;            \
+                                                                                \
+        fsp_assert(_b_, &f[0], __LINE__);                                           \
+        }
+#else
+#define ASSERT(_b_)             if (!(_b_)) { tegra_abort(ABORT_ASSERT, 0U); }
+#endif
+
+void assert_hook(const char * const filename,
+                 const uint32_t linenum);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/debug/debug-fmt.h b/spe-freertos-bsp/fsp/source/include/debug/debug-fmt.h
new file mode 100644
index 0000000..7379202
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/debug/debug-fmt.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DEBUG__DEBUG_FMT_H
+#define DEBUG__DEBUG_FMT_H
+#define FSP__DEBUG__DEBUG_FMT_H                             1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+void dbg_puthex8(uint32_t n);
+void dbg_putdec(uint32_t n);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/debug/debug-print.h b/spe-freertos-bsp/fsp/source/include/debug/debug-print.h
new file mode 100644
index 0000000..b6b81b7
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/debug/debug-print.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DEBUG__DEBUG_PRINT_H
+#define DEBUG__DEBUG_PRINT_H
+#define FSP__DEBUG__DEBUG_PRINT_H                             1
+
+/* Compiler headers */
+#include <stddef.h>
+#include <stdarg.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+int32_t dbg_printf(const char *fmt,
+               ...);
+
+int32_t dbg_snprintf(char *str,
+                 size_t size,
+                 const char *format,
+                 ...);
+
+int32_t dbg_vprintf(const char *fmt,
+                va_list ap);
+
+
+int32_t dbg_vsnprintf(char *str,
+                  size_t size,
+                  const char *format,
+                  va_list ap);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/debug/debug-uart.h b/spe-freertos-bsp/fsp/source/include/debug/debug-uart.h
new file mode 100644
index 0000000..520a610
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/debug/debug-uart.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2014-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DEBUG__DEBUG_UART_H
+#define DEBUG__DEBUG_UART_H
+#define FSP__DEBUG__DEBUG_UART_H        1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>        // for error_t
+
+/* Module-specific FSP headers */
+
+#define UART_MODE_STANDALONE 1U
+#define UART_MODE_TCU        2U
+
+/**
+ * @brief simple debug uart operations structure
+ *
+ * Describes the minimal debug UART controller operations.
+ *
+ * @init    callback to initialize the uart controller context.
+ * @putc    callback to write a char to the UART controller tx fifo.
+ * @putd    callback to write an amount of data to the UART controller tx fifo.
+ * @puts    callback to write a string to the UART controller tx fifo.
+ * @flush   callback to flush the uart controller tx fifo.
+ */
+struct dbg_uart_ops {
+    error_t (*init)     (void *ctlr);
+    void    (*putc)     (void *ctlr, const char ch);
+    void    (*putd)     (void *ctlr, const char *d, uint32_t len);
+    void    (*puts)     (void *ctlr, const char *s);
+    void    (*flush)    (void *ctlr);
+    bool    (*tx_ready) (void *ctlr);
+};
+
+void dbg_init_uart_ops(uint32_t uart_mode);
+void dbg_init(void);
+void dbg_putc(char c);
+void dbg_putd(const char *d, uint32_t len);
+void dbg_puts(const char *s);
+void dbg_flush(void);
+bool dbg_tx_ready(void);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/debug/debug.h b/spe-freertos-bsp/fsp/source/include/debug/debug.h
new file mode 100644
index 0000000..e92eb91
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/debug/debug.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DEBUG__DEBUG_H
+#define DEBUG__DEBUG_H
+#define FSP__DEBUG__DEBUG_H                             1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+void dbg_init(void);
+void dbg_3rdparty_init(void);
+void dbg_putc(char c);
+void dbg_putd(const char *d, uint32_t len);
+void dbg_puts(const char *s);
+void dbg_puthex8(uint32_t n);
+void dbg_putdec(uint32_t n);
+
+void dbg_flush(void);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/debug/nvriscv/debug/debug.h b/spe-freertos-bsp/fsp/source/include/debug/nvriscv/debug/debug.h
new file mode 100644
index 0000000..9a4350c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/debug/nvriscv/debug/debug.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef DEBUG__NVRISCV__DEBUG_H
+#define DEBUG__NVRISCV__DEBUG_H
+#define FSP__DEBUG__NVRISCV__DEBUG_H    1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+#define NVRISCV_DEBUG_BUFFER_MAGIC       0xF007BA11U
+
+typedef struct NVRISCV_DEBUG_BUFFER
+{
+    /* read offset updated by client RM */
+    uint32_t readOffset;
+
+    /* write offset updated by firmware RM */
+    uint32_t writeOffset;
+
+    /* buffer size configured by client RM */
+    uint32_t bufferSize;
+
+    /* magic number for header validation in nvwatch */
+    uint32_t magic;
+} NVRISCV_DEBUG_BUFFER;
+
+#endif // DEBUG__NVRISCV__DEBUG_H
diff --git a/spe-freertos-bsp/fsp/source/include/debug/nvriscv/debug/print.h b/spe-freertos-bsp/fsp/source/include/debug/nvriscv/debug/print.h
new file mode 100644
index 0000000..d4eda6d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/debug/nvriscv/debug/print.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef DEBUG__NVRISCV__PRINT_H
+#define DEBUG__NVRISCV__PRINT_H
+#define FSP__DEBUG__NVRISCV__PRINT_H    1
+
+/* Compiler headers */
+#include <stdarg.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/gcc_attrs.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+// Logging levels for ucode
+
+// Level not to be used (used to check for disabled prints)
+#define LEVEL_NONE     0
+
+// Levels below are printed if level passed is <= level from configuration
+
+//
+// Intened for messages that should be always printed. That may include
+// bootup/shutdown (for every stage), fatal crash etc.
+//
+#define LEVEL_ALWAYS   1
+// Critical (unrecoverable errors)
+#define LEVEL_CRIT     3
+// Ordinary errors, extra verbosity / information vs crit
+#define LEVEL_ERROR    5
+// Logs that may help understanding what's going on (but doesn't happen too often)
+#define LEVEL_INFO     7
+// Information useful for debugging
+#define LEVEL_DEBUG   10
+// Most verbose messages should be here (for example incoming RPC's)
+#define LEVEL_TRACE   15
+
+#define NVRISCV_DEBUG_PRINT_ENABLED (NVRISCV_CONFIG_DEBUG_PRINT_LEVEL > LEVEL_NONE)
+
+#if NVRISCV_DEBUG_PRINT_ENABLED
+int putchar(int c);
+int puts(const char *pStr);
+void putHex(unsigned count, unsigned long value);
+GCC_ATTR_FORMAT_PRINTF(1, 2) int printf(const char *pFmt, ...);
+#else
+static inline int putchar(int c GCC_ATTR_UNUSED) { return 0; }
+static inline int puts(const char *pStr GCC_ATTR_UNUSED) { return 0; }
+static inline void putHex(unsigned count GCC_ATTR_UNUSED,
+                          unsigned long value GCC_ATTR_UNUSED) { }
+
+GCC_ATTR_FORMAT_PRINTF(1, 2)
+static inline int printf(const char *pFmt GCC_ATTR_UNUSED, ...) { return 0; }
+#endif
+
+#define dbgPutchar(level, ch) do { if ((level) <= NVRISCV_CONFIG_DEBUG_PRINT_LEVEL) putchar(ch); } while(0)
+#define dbgPuts(level, str) do { if ((level) <= NVRISCV_CONFIG_DEBUG_PRINT_LEVEL) puts(str); } while (0)
+#define dbgPutHex(level, count, value) do { if ((level) <= NVRISCV_CONFIG_DEBUG_PRINT_LEVEL) putHex(count, value); } while (0)
+#define dbgPrintf(level, fmt, ...) do { if ((level) <= NVRISCV_CONFIG_DEBUG_PRINT_LEVEL) printf((fmt), ##__VA_ARGS__); } while (0)
+
+// String wrapper for non-standard print functions, string arrays etc.
+#define dbgStr(level, str) ((level) <= NVRISCV_CONFIG_DEBUG_PRINT_LEVEL ? str : "")
+
+#if NVRISCV_DEBUG_PRINT_ENABLED
+bool printInit(void *pBuffer, uint16_t bufferSize, uint8_t queueNo, uint8_t swgenNo);
+bool printInitEx(void *pBuffer, uint16_t bufferSize, uint32_t queueHeadPri, uint32_t queueTailPri, uint8_t swgenNo);
+#else
+static inline bool printInit(void *pBuffer GCC_ATTR_UNUSED,
+                             uint16_t bufferSize GCC_ATTR_UNUSED,
+                             uint8_t queueNo GCC_ATTR_UNUSED,
+                             uint8_t swgenNo GCC_ATTR_UNUSED)
+{
+    return true;
+}
+static inline bool printInitEx(void *pBuffer GCC_ATTR_UNUSED,
+                               uint16_t bufferSize GCC_ATTR_UNUSED,
+                               uint32_t queueHeadPri GCC_ATTR_UNUSED,
+                               uint32_t queueTailPri GCC_ATTR_UNUSED,
+                               uint8_t swgenNo GCC_ATTR_UNUSED)
+{
+    return true;
+}
+#endif // NVRISCV_DEBUG_PRINT_ENABLED
+
+#endif // DEBUG__NVRISCV__PRINT_H
diff --git a/spe-freertos-bsp/fsp/source/include/debug/nvriscv/debug/vprintfmt.h b/spe-freertos-bsp/fsp/source/include/debug/nvriscv/debug/vprintfmt.h
new file mode 100644
index 0000000..985e6c1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/debug/nvriscv/debug/vprintfmt.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef DEBUG__NVRISCV__VPRINTFMT_H
+#define DEBUG__NVRISCV__VPRINTFMT_H
+#define FSP__DEBUG__NVRISCV__VPRINTFMT_H    1
+
+/* Compiler headers */
+#include <stdarg.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+int vprintfmt(void (*putch)(int, void*), void *putdat,
+              const char* pFormat, va_list ap);
+
+#endif // DEBUG__NVRISCV__VPRINTFMT_H
diff --git a/spe-freertos-bsp/fsp/source/include/debug/print.h b/spe-freertos-bsp/fsp/source/include/debug/print.h
new file mode 100644
index 0000000..133452d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/debug/print.h
@@ -0,0 +1,77 @@
+/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DEBUG__PRINT_H
+#define DEBUG__PRINT_H
+#define FSP__DEBUG__PRINT_H                             1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+#define PRINT_LEVEL_ALWAYS         0UL
+#define PRINT_LEVEL_ERROR          1UL
+#define PRINT_LEVEL_WARNING        2UL
+#define PRINT_LEVEL_INFO           3UL
+#define PRINT_LEVEL_DEBUG          4UL
+#define PRINT_LEVEL_HIGHEST        5UL
+
+#if defined(USE_GCC) && (USE_GCC == 1)
+void print_message(uint32_t level,
+                   const char *format,
+                   ...)
+    __attribute__ ((format (__printf__, 2, 3)));
+
+#else
+void print_message(uint32_t level,
+                   const char *format,
+                   ...);
+#endif
+
+void set_print_log_level(const uint32_t level);
+uint32_t get_print_log_level(void);
+
+#define pr_warn(...)    \
+    print_message(PRINT_LEVEL_WARNING, __VA_ARGS__)
+
+#define pr_error(...)   \
+    print_message(PRINT_LEVEL_ERROR, __VA_ARGS__)
+
+#define pr_info(...)    \
+    print_message(PRINT_LEVEL_INFO, __VA_ARGS__)
+
+#define pr_debug(...)   \
+    print_message(PRINT_LEVEL_DEBUG, __VA_ARGS__)
+
+#endif /* DEBUG__PRINT_H */
diff --git a/spe-freertos-bsp/fsp/source/include/debug/printf-isr.h b/spe-freertos-bsp/fsp/source/include/debug/printf-isr.h
new file mode 100644
index 0000000..7657132
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/debug/printf-isr.h
@@ -0,0 +1,67 @@
+/*
+ * Copyright (c) 2015-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DEBUG__PRINTF_ISR_H
+#define DEBUG__PRINTF_ISR_H
+#define FSP__DEBUG__PRINTF_ISR_H                        1
+
+/* Compiler headers */
+#include <stdarg.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/*
+ * This header defines printf_isr(), which is a printf implementation that
+ * can be called from any context. It doesn't take locks or allocate memory.
+ * Therefore, it is safe to call from interrupt handlers, unlike printf().
+ *
+ * Limitations:
+ * - Output is limited to PRINTF_ISR_BUFSIZE characters. If necessary, this
+ * may be increased, but you may have to increase the IRQ stack size too.
+ * - You may not use the following specificers in the format string:
+ * %a, %A, %S, %ls, or any other that uses multibyte character strings.
+ * - There is no thread safety with respect to other printf() calls. Therefore,
+ * it is possible that output from a printf() and a printf_isr() might be
+ * mixed together.
+ */
+
+#define PRINTF_ISR_BUFSIZE 160
+
+int32_t printf_isr(const char *fmt, ...)
+	__attribute__ ((format (__printf__, 1, 2)));
+
+int32_t vprintf_isr(const char *fmt, va_list ap)
+	__attribute__ ((format (__printf__, 1, 0)));
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/debug/sections-abort.h b/spe-freertos-bsp/fsp/source/include/debug/sections-abort.h
new file mode 100644
index 0000000..7a277b1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/debug/sections-abort.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef DEBUG__SECTIONS_ABORT_H
+#define DEBUG__SECTIONS_ABORT_H
+#define FSP__DEBUG__SECTIONS_ABORT_H                    0
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_ABORT_DATA         SECTION_BUILDER(error.abort,            data)
+#define SECTION_NAME_ABORT_RODATA       SECTION_BUILDER(error.abort,            rodata)
+#define SECTION_NAME_ABORT_TEXT         SECTION_BUILDER(error.abort,            text)
+
+#define SECTION_STR_ABORT_TEXT          STR(SECTION_NAME_ABORT_TEXT)
+#define SECTION_STR_ABORT_DATA          STR(SECTION_NAME_ABORT_DATA)
+#define SECTION_STR_ABORT_RODATA        STR(SECTION_NAME_ABORT_RODATA)
+
+#define SECTION_ABORT_TEXT              SECTION(SECTION_STR_ABORT_TEXT)
+#define SECTION_ABORT_DATA              SECTION(SECTION_STR_ABORT_DATA)
+#define SECTION_ABORT_RODATA            SECTION(SECTION_STR_ABORT_RODATA)
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/debug/sections-assert.h b/spe-freertos-bsp/fsp/source/include/debug/sections-assert.h
new file mode 100644
index 0000000..5dede51
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/debug/sections-assert.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef DEBUG__SECTIONS_ASSERT_H
+#define DEBUG__SECTIONS_ASSERT_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_ASSERT_DATA        SECTION_BUILDER(assert,                 data)
+#define SECTION_NAME_ASSERT_RODATA      SECTION_BUILDER(assert,                 rodata)
+#define SECTION_NAME_ASSERT_TEXT        SECTION_BUILDER(assert,                 text)
+#define SECTION_NAME_ASSERT_ERR_DATA    SECTION_BUILDER(error.assert,           data)
+#define SECTION_NAME_ASSERT_ERR_TEXT    SECTION_BUILDER(error.assert,           text)
+
+#define SECTION_STR_ASSERT_TEXT         STR(SECTION_NAME_ASSERT_TEXT)
+#define SECTION_STR_ASSERT_RODATA       STR(SECTION_NAME_ASSERT_RODATA)
+#define SECTION_STR_ASSERT_DATA         STR(SECTION_NAME_ASSERT_DATA)
+#define SECTION_STR_ASSERT_ERR_TEXT     STR(SECTION_NAME_ASSERT_ERR_TEXT)
+#define SECTION_STR_ASSERT_ERR_DATA     STR(SECTION_NAME_ASSERT_ERR_TEXT)
+
+#define SECTION_ASSERT_TEXT             SECTION(SECTION_STR_ASSERT_TEXT)
+#define SECTION_ASSERT_RODATA           SECTION(SECTION_STR_ASSERT_RODATA)
+#define SECTION_ASSERT_DATA             SECTION(SECTION_STR_ASSERT_DATA)
+#define SECTION_ASSERT_ERR_TEXT         SECTION(SECTION_STR_ASSERT_ERR_TEXT)
+#define SECTION_ASSERT_ERR_DATA         SECTION(SECTION_STR_ASSERT_ERR_DATA)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/debug/sections-debug.h b/spe-freertos-bsp/fsp/source/include/debug/sections-debug.h
new file mode 100644
index 0000000..d64e0fa
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/debug/sections-debug.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DEBUG__SECTIONS_DEBUG_H
+#define DEBUG__SECTIONS_DEBUG_H
+#define FSP__DEBUG__SECTIONS_DEBUG_H                    0
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_DEBUG_BSS          SECTION_BUILDER(debug,                  bss)
+#define SECTION_NAME_DEBUG_DATA         SECTION_BUILDER(debug,                  data)
+#define SECTION_NAME_DEBUG_RODATA       SECTION_BUILDER(debug,                  rodata)
+#define SECTION_NAME_DEBUG_TEXT         SECTION_BUILDER(debug,                  text)
+
+#define SECTION_STR_DEBUG_TEXT          STR(SECTION_NAME_DEBUG_TEXT)
+#define SECTION_STR_DEBUG_RODATA        STR(SECTION_NAME_DEBUG_RODATA)
+#define SECTION_STR_DEBUG_DATA          STR(SECTION_NAME_DEBUG_DATA)
+#define SECTION_STR_DEBUG_BSS           STR(SECTION_NAME_DEBUG_BSS)
+
+#define SECTION_DEBUG_TEXT              SECTION(SECTION_STR_DEBUG_TEXT)
+#define SECTION_DEBUG_RODATA            SECTION(SECTION_STR_DEBUG_RODATA)
+#define SECTION_DEBUG_DATA              SECTION(SECTION_STR_DEBUG_DATA)
+#define SECTION_DEBUG_BSS               SECTION(SECTION_STR_DEBUG_BSS)
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/debug/tegra-debug.h b/spe-freertos-bsp/fsp/source/include/debug/tegra-debug.h
new file mode 100644
index 0000000..a14fd8e
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/debug/tegra-debug.h
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef DEBUG__TEGRA_DEBUG_H
+#define DEBUG__TEGRA_DEBUG_H
+#define FSP__DEBUG__TEGRA_DEBUG_H                       1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>
+#include <misc/bitops.h>
+#include <misc/macros.h>       // START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <debug/sections-debug.h>                       /* Immune from CT_ASSERT protection */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#define TEGRA_DEBUG_WAIT_BOOT           BIT(0)
+
+#if defined(DEBUG_WAIT) && (DEBUG_WAIT==1)
+#define DEBUG_WAIT_BOOT_FL              TEGRA_DEBUG_WAIT_BOOT
+#else
+#define DEBUG_WAIT_BOOT_FL              0
+#endif
+
+void debugger_wait(const uint32_t wait)         SECTION_DEBUG_TEXT;
+void debugger_wait_bp(const uint32_t wait)      NO_INLINE SECTION_DEBUG_TEXT;
+
+#if defined(DEBUG_WAIT) && (DEBUG_WAIT==1)
+#define DEBUGGER_WAIT(_w_)              debugger_wait(_w_)
+#else
+#define DEBUGGER_WAIT(_w_)
+#endif
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/delay/delay.h b/spe-freertos-bsp/fsp/source/include/delay/delay.h
new file mode 100644
index 0000000..4cbae5c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/delay/delay.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2014-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef DELAY__DELAY_H
+#define DELAY__DELAY_H
+#define FSP__DELAY__DELAY_H                             1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+void udelay(uint64_t delay_us);
+
+uint64_t get_time_ticks(void);
+uint64_t get_time_delta_us(uint64_t ticks_start);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/error/common-errors.h b/spe-freertos-bsp/fsp/source/include/error/common-errors.h
new file mode 100644
index 0000000..b96b1e7
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/error/common-errors.h
@@ -0,0 +1,99 @@
+/* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ERROR__COMMON_ERRORS_H
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <base/module-id.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "base/module-id.h"
+/* Module-specific FSP headers */
+
+/* Header guard protection
+ *   Had to be moved lower in the file to make use of the 'INLINE_RFD' macro */
+START_RFD_BLOCK(CERTC, DEVIATE, DCL37_C, "Approval:  Bug 2731179, DR: SWE-FSP-036-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#define ERROR__COMMON_ERRORS_H
+#define FSP__ERROR__COMMON_ERRORS_H                     1
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Common error codes
+ */
+#define E_SUCCESS               (error_t)(0UL)
+#define E_INVALID_PARAM         MODULE_ERROR(COMMON, 1UL)
+#define E_BUSY                  MODULE_ERROR(COMMON, 2UL)
+#define E_NOTSUPPORTED          MODULE_ERROR(COMMON, 3UL)
+#define E_TIMEOUT               MODULE_ERROR(COMMON, 4UL)
+#define E_PERM                  MODULE_ERROR(COMMON, 5UL)
+#define E_FAULT                 MODULE_ERROR(COMMON, 6UL)
+#define E_DT_BUS_INFO_NOT_FOUND MODULE_ERROR(COMMON, 7UL)
+#define E_NO_ACCESS             MODULE_ERROR(COMMON, 8UL)
+#define E_INVALID_STATE         MODULE_ERROR(COMMON, 9UL)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              CERTC, DEVIATE, DCL37_C, "Approval:  Bug 2731179, DR: SWE-FSP-036-SWSADR.docx")
+
+/*
+ * Common error-related typedef declarations
+ */
+#ifdef PROJECT_ERROR_T
+typedef PROJECT_ERROR_T error_t;
+// Sanity to confirm error_t can fit module error
+// module error size should at least be less than error_t
+CT_ASSERT((MODULE_ERROR_SIZE/8UL) < sizeof(error_t), "Incompatible error type for PROJECT_ERROR_T")
+#else
+typedef int32_t error_t;
+#endif
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/error/error.h b/spe-freertos-bsp/fsp/source/include/error/error.h
new file mode 100644
index 0000000..a1b0beb
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/error/error.h
@@ -0,0 +1,83 @@
+/* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ERROR__ERROR_H
+#define ERROR__ERROR_H
+#define FSP__ERROR__ERROR_H                             1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <aodmic/aodmic-errors.h>       // IWYU pragma: export
+                                        // IWYU pragma: no_include "aodmic/aodmic-errors.h"
+#include <ast/ast-errors.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ast/ast-errors.h"
+#include <error/common-errors.h>        // IWYU pragma: export
+                                        // IWYU pragma: no_include "error/common-errors.h"
+#include <hsp/hsp-errors.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "hsp/hsp-errors.h"
+#include <i2c/i2c-errors.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "i2c/i2c-errors.h"
+#include <osa/rtos-errors.h>            // IWYU pragma: export
+                                        // IWYU pragma: no_include "osa/rtos-errors.h"
+#include <scp/scp-errors.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "scp/scp-errors.h"
+#include <uart/uart-errors.h>           // IWYU pragma: export
+                                        // IWYU pragma: no_include "uart/uart-errors.h"
+#include <watchdog/watchdog-errors.h>   // IWYU pragma: export
+                                        // IWYU pragma: no_include "watchdog/watchdog-errors.h"
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__AODMIC__AODMIC_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__AST__AST_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HSP__HSP_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SCP__SCP_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__UART__UART_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_ERRORS_H, "Header file missing or invalid.")
+
+#endif /* ERROR__ERROR_H */
diff --git a/spe-freertos-bsp/fsp/source/include/fbdma/fbdma.h b/spe-freertos-bsp/fsp/source/include/fbdma/fbdma.h
new file mode 100644
index 0000000..d4d275c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/fbdma/fbdma.h
@@ -0,0 +1,170 @@
+/* _NVRM_COPYRIGHT_BEGIN_
+ *
+ * Copyright 2021-2022 by NVIDIA Corporation.  All rights reserved.  All
+ * information contained herein is proprietary and confidential to NVIDIA
+ * Corporation.  Any use, reproduction, or disclosure without the written
+ * permission of NVIDIA Corporation is prohibited.
+ *
+ * _NVRM_COPYRIGHT_END_
+ */
+#ifndef FBDMA__FBDMA_H
+#define FBDMA__FBDMA_H
+#define FSP__FBDMA__FBDMA_H 1
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <error/common-errors.h>
+
+#if (!NVRISCV_HAS_FBDMA) || (!NVRISCV_FEATURE_DMA)
+#error "This header cannot be used on an engine which does not support FBDMA."
+#endif // (!NVRISCV_HAS_FBDMA) || (!NVRISCV_FEATURE_DMA)
+
+#if NVRISCV_HAS_FBIF
+#include <fbdma/fbif.h>
+/**
+ * @brief The highest allowed value for the dma_idx argument.
+ */
+#define DMA_MAX_DMAIDX (FBIF_NUM_APERTURES-1U)
+
+#elif NVRISCV_HAS_TFBIF
+#include <fbdma/tfbif.h>
+/**
+ * @brief The highest allowed value for the dma_idx argument.
+ */
+#define DMA_MAX_DMAIDX (TFBIF_NUM_APERTURES-1U)
+
+#else
+#error "No FBIF or TFBIF"
+#endif
+
+/**
+ * @brief The minimum block size which FBDMA can transfer. All addresses
+ * and transfer sizes must be aligned to this.
+ */
+#define DMA_BLOCK_SIZE_MIN   0x4U
+
+/**
+ * @brief The maximum block size which FBDMA can transfer. The client can
+ * request a larger transfer than this but the driver will internally break it up
+ * into smaller transfers.
+ */
+#define DMA_BLOCK_SIZE_MAX   0x100U
+
+/**
+ * @brief DMA transfer between TCM PA and External memory. This is a synchronous transfer.
+ * The function will block until the transfer has completed.
+ *
+ * @param[in] tcm_pa The RISCV PA for the TCM buffer. Must be aligned to DMA_BLOCK_SIZE_MIN,
+ * but DMA_BLOCK_SIZE_MAX alignement is optimal.
+ * @param[in] aperture_offset The external address (GPU PA or GPU VA) in the aperture
+ * determined by dma_idx. The type of memory to access is determined by FBIF_APERTURE_CFG.memType
+ * (on engines with FBIF) or by TFBIF_APERTURE_CFG.swid (on engines with TFBIF).
+ * memutils_riscv_pa_to_target_offset can be used to translate a RISCV PA to a GPU PA/VA suitable for
+ * this argument. Must be aligned to DMA_BLOCK_SIZE_MIN, but DMA_BLOCK_SIZE_MAX alignement
+ * is optimal.
+ * @param[in] size_bytes The number of bytes to transfer. Must have a granularity of
+ * DMA_BLOCK_SIZE_MIN, but DMA_BLOCK_SIZE_MAX granularity is optimal.
+ * @param[in] dma_idx Aperture index to use (0 to DMA_MAX_DMAIDX)
+ * @param[in] b_read_ext Transfer direction. true: External->TCM. false: TCM->External
+ *
+ * @return E_SUCCESS on success
+ *         E_INVALID_PARAM if tcm_pa is not within the range of the ITCM or DTCM or
+ *         size_bytes, tcm_pa, or aperture_offset do not meet minimum alignment requirements.
+ *         E_BUSY if there is a DMA NACK
+ *         E_FAULT if there is a transfer error
+ *
+ * @pre The FBIF/TFBIF aperture referenced by dma_idx must have been configured by
+ * fbifConfigureAperture or tfbifConfigureAperture. If the aperture is configured
+ * to use a GPU VA, a context must be bound.
+ */
+error_t
+fbdma_pa(uint64_t tcm_pa,
+         uint64_t aperture_offset,
+         uint64_t size_bytes,
+         uint8_t  dma_idx,
+         bool     b_read_ext
+);
+
+/**
+ * @brief DMA transfer between TCM PA and External memory. This is an asynchronous transfer.
+ * this function does not wait for completion of DMA. It returns right away, allowing the
+ * client to call fbdma_pa_async again and queue up more requests.
+ *
+ * The client should call dmaWaitCompletion to ensure that all DMAs have completed.
+ *
+ * @param[in] tcm_pa The RISCV PA for the TCM buffer. Must be aligned to DMA_BLOCK_SIZE_MIN,
+ * but DMA_BLOCK_SIZE_MAX alignement is optimal.
+ * @param[in] aperture_offset The external address (GPU PA or GPU VA) in the aperture
+ * determined by dma_idx. The type of memory to access is determined by FBIF_APERTURE_CFG.memType
+ * (on engines with FBIF) or by TFBIF_APERTURE_CFG.swid (on engines with TFBIF).
+ * memutils_riscv_pa_to_target_offset can be used to translate a RISCV PA to a GPU PA/VA suitable for
+ * this argument. Must be aligned to DMA_BLOCK_SIZE_MIN, but DMA_BLOCK_SIZE_MAX alignement
+ * is optimal.
+ * @param[in] size_bytes The number of bytes to transfer. Must have a granularity of
+ * DMA_BLOCK_SIZE_MIN, but DMA_BLOCK_SIZE_MAX granularity is optimal.
+ * @param[in] dma_idx Aperture index to use (0-7).
+ * @param[in] b_read_ext Transfer direction. true: External->TCM. false: TCM->External.
+ *
+ * @return E_SUCCESS on success.
+ *         E_INVALID_PARAM if tcm_pa is not within the range of the ITCM or DTCM or
+ *         size_bytes, tcm_pa, or aperture_offset do not meet minimum alignment requirements.
+ *
+ * @pre The FBIF/TFBIF aperture referenced by dma_idx must have been configured by
+ * fbifConfigureAperture or tfbifConfigureAperture. If the aperture is configured
+ * to use a GPU VA, a context must be bound.
+ */
+error_t
+fbdma_pa_async(uint64_t tcm_pa,
+               uint64_t aperture_offset,
+               uint64_t size_bytes,
+               uint8_t  dma_idx,
+               bool     b_read_ext
+);
+
+/**
+ * @brief Wait for all DMA transfers to complete
+ *
+ * @return E_SUCCESS on success
+ *         E_FAULT if DMA HW returned an error
+ *         E_BUSY if DMA engine has returned a NACK
+ *
+ * @pre Should be called after fbdma_pa_async to ensure that DMAs have completed.
+ */
+error_t
+fbdma_wait_completion(void);
+
+#if NVRISCV_FEATURE_SCP
+
+/**
+ * @brief DMA transfer from SCP to FB/Sysmem. This function uses the direct bypass
+ * shortcut path from SCP: SCP registers --> SCPDMA --> FBDMA --> FB/SYSMEM
+ *
+ * @param[in] aperture_offset The external address (GPU PA or GPU VA) in the aperture
+ *            determined by dma_idx. This can be a GPU VA or GPU PA. Must be aligned
+              to SCP_REGISTER_SIZE.
+ * @param[in] size_bytes The number of bytes to DMA. This value must be a multiple of
+              SCP_REGISTER_SIZE and should generally match the size used to configure
+              the corresponding SCPDMA transfer.
+ * @param[in] dma_idx Aperture index to use (0 to DMA_MAX_dma_idx)
+ *
+ * @return E_SUCCESS on success
+ *         E_INVALID_PARAM if size_bytes or aperture_offset do not meet
+ *                                   minimum alignment requirements.
+ *         E_BUSY if there is a DMA NACK
+ *         E_FAULT if there is an error returned from the DMA hardware.
+ *
+ * @pre The FBIF/TFBIF aperture referenced by dma_idx must have been configured by
+ * fbifConfigureAperture or tfbifConfigureAperture. If the aperture is configured
+ * to use a GPU VA, a context must be bound. The caller must first call into the SCP
+ * driver to configure SCPDMA for the transfer.
+ */
+error_t
+fbdma_scp_to_extmem(
+    uint64_t aperture_offset,
+    uint64_t size_bytes,
+    uint8_t  dma_idx
+);
+
+#endif // NVRISCV_FEATURE_SCP
+
+#endif // FBDMA__FBDMA_H
diff --git a/spe-freertos-bsp/fsp/source/include/fbdma/fbif.h b/spe-freertos-bsp/fsp/source/include/fbdma/fbif.h
new file mode 100644
index 0000000..2f1951a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/fbdma/fbif.h
@@ -0,0 +1,128 @@
+/* _NVRM_COPYRIGHT_BEGIN_
+ *
+ * Copyright 2021-2022 by NVIDIA Corporation.  All rights reserved.  All
+ * information contained herein is proprietary and confidential to NVIDIA
+ * Corporation.  Any use, reproduction, or disclosure without the written
+ * permission of NVIDIA Corporation is prohibited.
+ *
+ * _NVRM_COPYRIGHT_END_
+ */
+#ifndef FBDMA__FBIF_H
+#define FBDMA__FBIF_H
+#define FSP__FBDMA__FBIF_H 1
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <error/common-errors.h>
+
+#ifndef NVRISCV_HAS_FBIF
+#error "This header should only be used on engines which have a FBIF block."
+#endif // NVRISCV_HAS_FBIF
+
+/**
+ * @brief The number of configurable FBIF apertures.
+ */
+#define FBIF_NUM_APERTURES 8U
+
+/**
+ * @brief Possible targets for external memory access. These enum values
+ * correspond to the TARGET field of the TRANSCFG register.
+ *
+ * @typedef-title fbif_transcfg_target_t
+ */
+typedef enum
+{
+    FBIF_TRANSCFG_TARGET_LOCAL_FB,
+    FBIF_TRANSCFG_TARGET_COHERENT_SYSTEM,
+    FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSTEM,
+    FBIF_TRANSCFG_TARGET_COUNT
+} fbif_transcfg_target_t;
+
+/**
+ * @brief L2 Cache eviction policies for external memory access. These enum
+ * values correspond to the L2C_WR and L2C_RD fields of the TRANSCFG register.
+ *
+ * @typedef-title fbif_transcfg_l2c_t
+ */
+typedef enum
+{
+    FBIF_TRANSCFG_L2C_L2_EVICT_FIRST,
+    FBIF_TRANSCFG_L2C_L2_EVICT_NORMAL,
+    FBIF_TRANSCFG_L2C_L2_EVICT_LAST,
+    FBIF_TRANSCFG_L2C_COUNT
+} fbif_transcfg_l2c_t;
+
+/**
+ * @brief Configuration struct for an FBIF Aperture. The fields in this structure
+ * are used to configure the FBIF_TRANSCFG and FBIF_REGIONCFG registers of the
+ * FBIF, which determine how the FBDMA engine will access external memory. More
+ * details on these fields can be found in the FBIF Hardware documentation.
+ *
+ * ``aperture_idx``: The aperture to configure (0-7)
+ *
+ * ``target``: External memory target. Programmed into the TARGET field of the
+ * FBIF_TRANSCFG register corresponding to this aperture.
+ *
+ * ``b_target_va``: Programmed into the MEM_TYPE field of the FBIF_TRANSCFG register
+ * corresponding to this aperture.
+ *  True : use virtual access opcode
+ *  False : use physical access opcode, based on 'target'
+ *
+ * ``l2c_wr``: L2 Cache eviction class for write requests. Programmed into the L2C_WR
+ * field of the FBIF_TRANSCFG register corresponding to this aperture.
+ *
+ * ``l2c_rd``: L2 Cache eviction class for read requests. Programmed into the L2C_RD
+ * field of the FBIF_TRANSCFG register corresponding to this aperture.
+ *
+ * ``b_fbif_transcfg_wachk0_enable``: Perform Address Check 0 on writes. Programmed into
+ * the WACHK0 field of the FBIF_TRANSCFG register corresponding to this aperture.
+ *
+ * ``fbif_transcfg_wachk1_enable``: Perform Address Check 1 on writes. Programmed into
+ * the WACHK1 field of the FBIF_TRANSCFG register corresponding to this aperture.
+ *
+ * ``fbif_transcfg_rachk0_enable``: Perform Address Check 0 on reads. Programmed into
+ * the RACHK0 field of the FBIF_TRANSCFG register corresponding to this aperture.
+ *
+ * ``fbif_transcfg_rachk1_enable``: Perform Address Check 1 on reads. Programmed into
+ * the RACHK1 field of the FBIF_TRANSCFG register corresponding to this aperture.
+ *
+ * ``b_engine_id_flag_own``: Selects the value to program into the ENGINE_ID_FLAG
+ *  field of the the FBIF_TRANSCFG register corresponding to this aperture.
+ *                   true : FBIF_TRANSCFG_ENGINE_ID_FLAG_OWN
+ *                   false : FBIF_TRANSCFG_ENGINE_ID_FLAG_BAR2_FN0
+ *
+ * ``region_id``: Value to program into the FBIF_REGIONCFG register corresponding
+ * to this aperture. This is the WPR_ID (0-3) which will be used for accesses
+ * through this aperture. 0 = Insecure accesses. 1-3 = Used when accessing a WPR.
+ */
+typedef struct {
+    uint8_t aperture_idx;
+    fbif_transcfg_target_t target;
+    bool b_target_va;
+    fbif_transcfg_l2c_t l2c_wr;
+    fbif_transcfg_l2c_t l2c_rd;
+    bool b_fbif_transcfg_wachk0_enable;
+    bool b_fbif_transcfg_wachk1_enable;
+    bool b_fbif_transcfg_rachk0_enable;
+    bool b_fbif_transcfg_rachk1_enable;
+    bool b_engine_id_flag_own;
+    uint8_t region_id;
+} fbif_aperture_cfg_t;
+
+/**
+ * @brief Configure some of the 8 DMA apertures in FBIF.
+ * A similar function (tfbif_configure_aperture) exists for TFBIF
+ * which is used on Tegra SOC engines. This function is not thread
+ * safe. The client must ensure that there is no chance of it being
+ * preempted by another task or ISR which may call a DMA function
+ * or touch the FBIF registers.
+ *
+ * @param[in] p_cfgs an array of fbif_aperture_cfg_t - one per aperture
+ * @param[in] num_cfgs is the size of cfgs (1-8)
+ * @return E_SUCCESS on success
+ *         E_INVALID_PARAM if cfgs is not sane.
+ *              Some of the cfgs may still be applied, even if this error is returned.
+ */
+error_t fbif_configure_aperture(const fbif_aperture_cfg_t *p_cfgs, uint8_t num_cfgs);
+
+#endif // FBDMA__FBIF_H
diff --git a/spe-freertos-bsp/fsp/source/include/fbdma/memutils.h b/spe-freertos-bsp/fsp/source/include/fbdma/memutils.h
new file mode 100644
index 0000000..9a0b909
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/fbdma/memutils.h
@@ -0,0 +1,142 @@
+/* _NVRM_COPYRIGHT_BEGIN_
+ *
+ * Copyright 2021-2022 by NVIDIA Corporation.  All rights reserved.  All
+ * information contained herein is proprietary and confidential to NVIDIA
+ * Corporation.  Any use, reproduction, or disclosure without the written
+ * permission of NVIDIA Corporation is prohibited.
+ *
+ * _NVRM_COPYRIGHT_END_
+ */
+#ifndef FBDMA__MEMUTILS_H
+#define FBDMA__MEMUTILS_H
+#define FSP__FBDMA__MEMUTILS_H 1
+
+#include <stddef.h>
+#include <stdint.h>
+
+#include <error/common-errors.h>
+
+#if NVRISCV_HAS_FBIF
+#include <fbdma/fbif.h>
+#endif // NVRISCV_HAS_FBIF
+
+/**
+ * @brief Memory targets supported by memutils_riscv_pa_to_target_offset()
+ *
+ * @typedef-title riscv_mem_target_t
+ */
+typedef enum
+{
+    RISCV_MEM_TARGET_IMEM,
+    RISCV_MEM_TARGET_DMEM,
+    RISCV_MEM_TARGET_FBGPA,
+    RISCV_MEM_TARGET_SYSGPA,
+} riscv_mem_target_t;
+
+
+#if NVRISCV_HAS_FBIF
+
+/**
+ * @brief Converts a RISCV PA to an FBIF target/offset pair. Target is one of
+ * the external memory types which Peregrine can access via FBIF (FB or SYSMEM)
+ * and offset is the offset within the physical address range of that memory type.
+ *
+ * @param[in]  pa       The RISCV PA to convert.
+ *
+ * @param[out] p_target  The target aperture (e.g. COHERENT_SYSTEM) that the PA
+ *                      resides within.
+ *
+ * @param[out] p_offset  The offset of the PA within the target aperture.
+ *
+ * @return E_SUCCESS       if successful.
+ * E_INVALID_PARAM if PA is not within the range of a valid memory aperture (SYSMEM or FB).
+ */
+error_t memutils_riscv_pa_to_fbif_aperture(uintptr_t pa, fbif_transcfg_target_t *p_target,
+    uint64_t *p_offset);
+
+#endif // NVRISCV_HAS_FBIF
+
+/**
+ * @brief Converts a RISCV PA to a global target/offset pair. Target is one of
+ * the available memory types which Peregrine can access (IMEM, DMEM, FB, SYSMEM)
+ * and offset is the offset within the physical address range of that memory type.
+ *
+ * @param[in]  pa       The RISCV PA to convert.
+ *
+ * @param[out] p_target  The memory target (e.g. SYSMEM) that the PA resides
+ *                      within (optional).
+ *
+ * @param[out] p_offset  The offset of the PA within the memory target
+ *                      (optional).
+ *
+ * @return E_SUCCESS       if successful.
+ * E_INVALID_PARAM if PA does not fall inside any of the supported memory targets.
+ */
+error_t memutils_riscv_pa_to_target_offset(uintptr_t pa, riscv_mem_target_t *p_target,
+    uint64_t *p_offset);
+
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Checks whether an address is contained within a memory region.
+ *
+ * @param[in]    check_addr      The address to check.
+ * @param[in]    region_start    The start address of the memory region.
+ * @param[in]    region_end      The end address of the memory region.
+ *
+ * @return true if the check address lies within the memory region.
+ *         false otherwise.
+ *
+ * @note The byte at region_end is not included in the memory region.
+ */
+static inline bool
+memutils_mem_addr_in_range
+(
+    uintptr_t check_addr,
+    uintptr_t region_start,
+    uintptr_t region_end
+)
+{
+    return ((check_addr >= region_start) && (check_addr < region_end));
+}
+
+/**
+ * @brief Checks whether two memory regions overlap.
+ *
+ * @param[in]    first_base      Base address of the first region.
+ * @param[in]    first_size      Size in bytes of the first region.
+ * @param[in]    second_base     Base address of the second region.
+ * @param[in]    second_size     Size in bytes of the second region.
+ *
+ * @return
+ *    true  if the memory regions overlap.
+ *    false if the memory regions do not overlap.
+ *
+ * @note in case of overflow, this function returns false
+ */
+static inline bool
+memutils_mem_has_overlap
+(
+    uintptr_t first_base,
+    size_t first_size,
+    uintptr_t second_base,
+    size_t second_size
+)
+{
+    bool ret;
+
+    if (((UINT64_MAX - first_base) < first_size) ||
+        ((UINT64_MAX - second_base) < second_size))
+    {
+        ret = false;
+    }
+    else
+    {
+        ret = ((second_base < (first_base  + first_size)) &&
+                (first_base  < (second_base + second_size)));
+    }
+
+    return ret;
+}
+
+#endif //FBDMA__MEMUTILS_H
diff --git a/spe-freertos-bsp/fsp/source/include/fbdma/tfbif.h b/spe-freertos-bsp/fsp/source/include/fbdma/tfbif.h
new file mode 100644
index 0000000..7e5b279
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/fbdma/tfbif.h
@@ -0,0 +1,67 @@
+/* _NVRM_COPYRIGHT_BEGIN_
+ *
+ * Copyright 2021-2022 by NVIDIA Corporation.  All rights reserved.  All
+ * information contained herein is proprietary and confidential to NVIDIA
+ * Corporation.  Any use, reproduction, or disclosure without the written
+ * permission of NVIDIA Corporation is prohibited.
+ *
+ * _NVRM_COPYRIGHT_END_
+ */
+#ifndef FBDMA__TFBIF_H
+#define FBDMA__TFBIF_H
+#define FSP__FBDMA__TFBIF_H 1
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <error/common-errors.h>
+
+#ifndef NVRISCV_HAS_TFBIF
+#error "This header should only be used on engines which have a TFBIF block."
+#endif // NVRISCV_HAS_TFBIF
+
+/**
+ * @brief The number of configurable TFBIF apertures.
+ */
+#define TFBIF_NUM_APERTURES 8U
+
+/**
+ * @brief Configuration struct for a TFBIF Aperture. This is the Tegra equivilant of
+ * FBIF_APERTURE_CFGThe fields in this structure are used to configure the TFBIF_TRANSCFG
+ * and TFBIF_REGIONCFG registers of the TFBIF, which determine how the FBDMA engine
+ * will access external memory. More details on these fields can be found in
+ * the TFBIF Hardware documentation.
+ *
+ * ``aperture_idx``: The aperture to configure (0-7). Programmed into the ATT_SWID
+ * field of the TFBIF_TRANSCFG register corresponding to this aperture.
+ *
+ * ``swid``: The SWID value for this aperture. Programmed into the ATT_SWID field
+ * of the TFBIF_TRANSCFG register corresponding to this aperture.
+ *
+ * ``b_vpr``: The VPR to use for this aperture. Programmed into the ATT_SWID field
+ * of the TFBIF_TRANSCFG register corresponding to this aperture.
+ *
+ * ``aperture_id``: Aperture ID AKA GSC_ID. Programmed into the Tx_APERT_ID field
+ * of the TFBIF_REGIONCFG register corresponding to this aperture.
+ */
+typedef struct {
+    uint8_t aperture_idx;
+    uint8_t swid;
+    bool b_vpr;
+    uint8_t aperture_id;
+} tfbif_aperture_cfg_t;
+
+/**
+ * @brief Configure some of the 8 DMA apertures in TFBIF.
+ * A similar function (fbifConfigureAperture) exists for FBIF
+ * Which is used on dGPU and Tegra iGPU engines. This function is not thread
+ * safe. The client must ensure that there is no chance of it being
+ * preempted by another Task or ISR which may call a DMA function
+ * or touch the TFBIF registers.
+ *
+ * @param[in] p_cfgs an array of tfbif_aperture_cfg_t - one per aperture
+ * @param[in] num_cfgs is the size of p_cfgs (1-8)
+ * @return E_SUCCESS on success
+ *         E_INVALID_PARAM if p_cfgs is not sane
+ */
+error_t tfbif_configure_aperture(const tfbif_aperture_cfg_t *p_cfgs, uint8_t num_cfgs);
+#endif // FBDMA__TFBIF_H
diff --git a/spe-freertos-bsp/fsp/source/include/gpcdma/gpcdma-errors.h b/spe-freertos-bsp/fsp/source/include/gpcdma/gpcdma-errors.h
new file mode 100644
index 0000000..1882397
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/gpcdma/gpcdma-errors.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GPCDMA__GPCDMA_ERRORS_H
+#define GPCDMA__GPCDMA_ERRORS_H
+#define FSP__GPCDMA__GPCDMA_ERRORS_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+// IWYU pragma: no_include "base/module-id.h"
+#include <base/module-id.h>         // IWYU pragma: export
+#include <misc/macros.h>            // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file gpcdma-errors.h
+ * @brief Error codes that are specific to the gpcdma
+ */
+
+#define E_GPCDMA_NULL_PTR               MODULE_ERROR(GPCDMA, 0UL)
+#define E_GPCDMA_INVALID_PARAM          MODULE_ERROR(GPCDMA, 1UL)
+#define E_GPCDMA_INVALID_XFER_DIR       MODULE_ERROR(GPCDMA, 2UL)
+#define E_GPCDMA_CHAN_BUSY              MODULE_ERROR(GPCDMA, 3UL)
+#define E_GPCDMA_NO_CALLBACK_ASYNC      MODULE_ERROR(GPCDMA, 4UL)
+#define E_GPCDMA_INVALID_XFER_SIZE      MODULE_ERROR(GPCDMA, 5UL)
+#define E_GPCDMA_INVALID_XFER_SIZE_IO   MODULE_ERROR(GPCDMA, 6UL)
+#define E_GPCDMA_UNALIGNED_SRC          MODULE_ERROR(GPCDMA, 7UL)
+#define E_GPCDMA_UNALIGNED_DST          MODULE_ERROR(GPCDMA, 8UL)
+#define E_GPCDMA_INVALID_FC_REQ_ID      MODULE_ERROR(GPCDMA, 9UL)
+#define E_GPCDMA_INVALID_ADDR_WRAP      MODULE_ERROR(GPCDMA, 10UL)
+#define E_GPCDMA_PORT_SYNC_TIMEOUT      MODULE_ERROR(GPCDMA, 11UL)
+#define E_GPCDMA_PORT_INIT_FAIL         MODULE_ERROR(GPCDMA, 12UL)
+#define E_GPCDMA_PORT_CHAN_SETUP_FAIL   MODULE_ERROR(GPCDMA, 13UL)
+#define E_GPCDMA_NOT_INITED             MODULE_ERROR(GPCDMA, 14UL)
+#define E_GPCDMA_CHAN_NOT_BUSY          MODULE_ERROR(GPCDMA, 15UL)
+#define E_GPCDMA_INVALID_XFER_MODE      MODULE_ERROR(GPCDMA, 16UL)
+#define E_GPCDMA_QUEUE_ALLOC_FAIL       MODULE_ERROR(GPCDMA, 17UL)
+#define E_GPCDMA_QUEUE_OP_FAIL          MODULE_ERROR(GPCDMA, 18UL)
+#define E_GPCDMA_CONT_MODE_OP_FAIL      MODULE_ERROR(GPCDMA, 19UL)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif  /* GPCDMA__GPCDMA_ERRORS_H */
diff --git a/spe-freertos-bsp/fsp/source/include/gpcdma/gpcdma-port.h b/spe-freertos-bsp/fsp/source/include/gpcdma/gpcdma-port.h
new file mode 100644
index 0000000..5485471
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/gpcdma/gpcdma-port.h
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GPCDMA__GPCDMA_PORT_H
+#define GPCDMA__GPCDMA_PORT_H
+#define FSP__GPCDMA__GPCDMA_PORT_H                      1
+
+/**
+ * @file gpcdma/gpcdma-port.h
+ * @brief APIs that the gpcdma controller driver depends on and needs to
+ *        be implemented by the gpcdma port layer.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                // for bool
+#include <stdint.h>
+                                    // IWYU pragma: no_include <errno.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* LateFSP headers */
+#include <error/common-errors.h>
+#include <misc/macros.h>            // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+// IWYU pragma: no_forward_declare gpcdma_id
+struct gpcdma_id;
+
+/**
+ * @brief gpcdma channel setup hook
+ *
+ * @jama_func_req_id 17662895
+ *
+ * This function is used to perform the port specific per-channel setup.
+ *
+ * @note called from function gpcdma_init()
+
+ * @param[in] chan_sem DMA channel id
+ *
+ * @retval E_SUCESS  on success
+ */
+error_t gpcdma_port_chan_setup(uint32_t chan_num);
+
+/**
+ * @brief gpcdma channel sync hook
+ *
+ * @jama_func_req_id 17663510
+ *
+ * This function is used to block/wait until the synchronous
+ * transfer is finished.
+ *
+ * @pre the function gpcdma_init() has been called
+ * @note called from gpcdma_transfer() for synchronous transfers
+ *
+ * @param[in] chan_sem DMA channel id
+ * @param[in] timeout Timeout to wait before bailing out
+ *
+ * @retval E_SUCESS                     on success
+ * @retval E_GPCDMA_INVALID_PARAM       invalid DMA channel id
+ * @retval E_GPCDMA_PORT_SYNC_TIMEOUT   timed out for synchronous transfers
+ */
+error_t gpcdma_port_chan_sync(uint32_t chan_num,
+                              uint32_t timeout);
+
+/**
+ * @brief gpcdma channel sync complete hook
+ *
+ * @jama_func_req_id 17671472
+ *
+ * This function is used to notify/unblock the channel that is blocked on
+ * a synchronous transfer.
+ *
+ * @pre the function gpcdma_init() has been called
+ * @note called from gpcdma_chan_irq() for synchronous transfers
+ *
+ * @param[in] chan_num  DMA channel id of the controller
+ *
+ * @retval E_SUCESS                 on success
+ * @retval E_GPCDMA_INVALID_PARAM   invalid DMA channel id
+ */
+error_t gpcdma_port_chan_sync_end(uint32_t chan_num);
+
+/**
+ * @brief gpcdma port specific controller init hook
+ *
+ * @jama_func_req_id 17662889
+ *
+ * @note called from function gpcdma_init()
+ *
+ * This function is used to perform some port specific init such
+ * as resetting the controller after the common init.
+ *
+ * @param[in] id dma controller context
+ *
+ * @retval E_SUCESS                 on success
+ * @retval E_GPCDMA_PORT_INIT_FAIL  port specific init failed
+ */
+error_t gpcdma_port_init(struct gpcdma_id *id);
+
+/**
+ * @brief gpcdma port specific queue creation and init function
+ *
+ * @note Only used during continuous mode
+ *
+ * This function is used to create queue to store the list of the
+ * buffers (src and dst) in cyclic/continuous mode.
+ *
+ * @param[in] chan_num dma channel number
+ * @param[in] nelems   number of elements to create queue for
+ * @param[in] el_size  size of the elements
+ *
+ * @retval E_SUCESS                 on success
+ * @retval E_GPCDMA_INVALID_PARAM   invalid parameters
+ * @retval E_GPCDMA_QUEUE_OP_FAIL   queue creation failed
+ */
+error_t gpcdma_port_init_queue(uint32_t chan_num, uint32_t nelems,
+                               uint32_t el_size);
+
+/**
+ * @brief gpcdma port specific queue delete/deinit function
+ *
+ * @note Only used during continuous mode
+ *
+ * This function is used to deinit or delete queue.
+ *
+ * @param[in] chan_num dma channel number
+ */
+void gpcdma_port_delete_queue(uint32_t chan_num);
+
+/**
+ * @brief gpcdma port specific get element function
+ *
+ * @note Only used during continuous mode
+ *
+ * This function is used to retrieve the element or descriptor from the queue.
+ *
+ * @param[in]  chan_num   dma channel number
+ * @param[out] ptr        store de-queued element
+ * @param[in]  timeout    timeout to wait dequeuing element
+ * @param[in]  from_isr   indicates if API is being called from ISR
+ *
+ * @retval E_SUCESS                 on success
+ * @retval E_GPCDMA_INVALID_PARAM   on invalid parameters
+ * @retval E_GPCDMA_QUEUE_OP_FAIL   on failure to retrieve the descriptor.
+ */
+error_t gpcdma_port_get_desc(uint32_t chan_num, void *ptr, uint32_t timeout,
+                             bool from_isr);
+
+/**
+ * @brief gpcdma port specific store element at the back function
+ *
+ * @note Only used during continuous mode
+ *
+ * This function is used to send or store the element or descriptor
+ * at the back of the queue.
+ *
+ * @param[in] chan_num dma channel number
+ * @param[in] ptr      element to store
+ * @param[in] timeout  timeout to wait dequeuing element
+ * @param[in] from_isr indicates if API is being called from ISR
+ *
+ * @retval E_SUCESS                 on success
+ * @retval E_GPCDMA_INVALID_PARAM   on invalid parameters
+ * @retval E_GPCDMA_QUEUE_OP_FAIL   on failure to retrieve the descriptor.
+ */
+error_t gpcdma_port_send_desc_to_back(uint32_t chan_num, void *ptr,
+                                      uint32_t timeout, bool from_isr);
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/gpcdma/gpcdma-priv.h b/spe-freertos-bsp/fsp/source/include/gpcdma/gpcdma-priv.h
new file mode 100644
index 0000000..6c33c2e
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/gpcdma/gpcdma-priv.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GPCDMA__GPCDMA_PRIV_H
+#define GPCDMA__GPCDMA_PRIV_H
+#define FSP__GPCDMA__GPCDMA_PRIV_H                      1
+
+/**
+ * @file gpcdma/gpcdma-tegra-priv.h
+ * @brief Structures that are internal to the GPCDMA driver
+ */
+
+/* Compiler headers */
+#include <stdbool.h>
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>            // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <gpcdma/gpcdma.h>
+#include <lock/smplock.h>
+#include <lock/smplock-up.h>        // for smplock_t
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPCDMA__GPCDMA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__LOCK__SMPLOCK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__LOCK__SMPLOCK_UP_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * Most of the AUXP GPCDMA controllers support 8 channels. Hence,
+ * setting number of DMA channels as 8.
+ */
+#define TEGRA_GPCDMA_NUM_CHANNELS 8
+
+struct gpcdma_hw_handle;
+
+/**
+ * @brief GPCDMA channel context
+ *
+ * Structure that describes the configuration of a GPCDMA controller.
+ *
+ * @chan_base       base address of the channel
+ * @id              channel identifier ranging from 0 to 7
+ * @irq             channel irq
+ * @total_bytes	    total bytes transferred so far in this channel
+ * @words_to_xfer   words to transfer
+ * @lock            per channel smplock for SMP systems
+ * @callback        callback to be executed for asynchronous transfers
+ * @cdata           opaque data pointer for the callback function
+ * @synchronous     indicates if the channel xfers are synchronous
+ * @continuous	    indicates if channel xfers are continuous
+ * @busy            indicates if the channel is busy
+ */
+struct gpcdma_channel {
+    uint32_t        chan_base;
+    uint32_t        id;
+    uint32_t        irq;
+    uint64_t        total_bytes;
+    uint32_t        words_to_xfer;
+    smplock_t       *lock;
+    dma_callback    *callback;
+    void            *cdata;
+    bool            synchronous;
+    bool            continuous;
+    bool            busy;
+};
+
+/**
+ * @brief GPCDMA controller configuration structure
+ *
+ * Structure that describes the configuration of a GPCDMA controller.
+ *
+ * @base_addr   base address of the controller
+ * @irqs        array of per channel irqs
+ * @hw_handle   port specific hw handle
+ */
+struct gpcdma_conf {
+    uint32_t                        base_addr;
+    const uint32_t                  irqs[TEGRA_GPCDMA_NUM_CHANNELS];
+    const struct gpcdma_hw_handle   *hw_handle;
+};
+
+/**
+ * @brief GPCDMA controller context structure
+ *
+ * Structure that is used by the GPCDMA driver to manage the GPCDMA controller
+ * during run time.
+ *
+ * @conf        GPCDMA controller instance configuration
+ * @channels    array of pointers to GPCDMA controller per-channel context
+ * @inited      GPCDMA controller initialization state
+ */
+struct gpcdma_id {
+    const struct gpcdma_conf    conf;
+    struct gpcdma_channel       *channels[TEGRA_GPCDMA_NUM_CHANNELS];
+    bool                        inited;
+};
+
+/**
+ * @brief GPCDMA source and destination buffers used in cyclic mode
+ *
+ * Structure that is used by the driver during cyclic mode. It will store
+ * buffer descriptors equal to period length specified during transfers.
+ *
+ * @src_addr    stores the source address
+ * @dst_addr    stores the destination address
+ */
+struct gpcdma_buf_desc {
+    uint32_t src_addr;
+    uint32_t dst_addr;
+    uint32_t hi_src_addr;
+    uint32_t hi_dst_addr;
+};
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/gpcdma/gpcdma.h b/spe-freertos-bsp/fsp/source/include/gpcdma/gpcdma.h
new file mode 100644
index 0000000..d89aeb1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/gpcdma/gpcdma.h
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef GPCDMA__GPCDMA_H
+#define GPCDMA__GPCDMA_H
+#define FSP__GPCDMA__GPCDMA_H                      1
+
+/**
+ * @file gpcdma/gpcdma-tegra.h
+ * @brief functions for performing DMA operations.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>
+#include <stdint.h>
+                                        // IWYU pragma: no_include <errno.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>        // for error_t, FSP__ERROR__COMMON...
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * The completion status of a DMA transfer.
+ *
+ * These values will be returned by DMA driver function which initiated DMA
+ * transfers. For asynchronous transfers, the value returned represents the
+ * status of submitting the request to the hardware. For synchronous
+ * transfers, the value returned represents the overall status of the
+ * transaction.
+ *
+ * For asynchronous transfers, these values will also be passed to the caller-
+ * supplied completion callback.
+ *
+ *                Ret async    Ret sync    Async callback
+ * NOT_INITIATED: Y            Y           N
+ * EXECUTING:     Y            N           N
+ * COMPLETE:      N            Y           Y
+ * ABORTED:       N            N           Y
+ * TIMEOUT:       N            Y           N
+ */
+typedef uint32_t dma_status;
+
+#define DMA_STATUS_NOT_INITIATED    0x0UL
+#define DMA_STATUS_EXECUTING        0x1UL
+#define DMA_STATUS_COMPLETE         0x2UL
+#define DMA_STATUS_ABORTED          0x3UL
+#define DMA_STATUS_TIMEOUT          0x4UL
+
+/**
+ * @brief dma callback function
+ *
+ * The function is called whenever a DMA transfer has completed.
+ *
+ * @param[in] callback_param A copy of a value passed to the DMA driver function
+ *                           that initiated the transfer. Clients may used this
+ *                           to pass context to the DMA completion callback.
+ * @param[in ]status Status of the transfer.
+ *
+ *@ return None
+ */
+typedef void dma_callback(void *callback_param, dma_status status);
+
+/* Supported DMA transfer combinations */
+typedef uint32_t gpcdma_transfer_direction;
+
+#define GPCDMA_XFER_DIR_MEM_TO_IO   0x0UL
+#define GPCDMA_XFER_DIR_IO_TO_MEM   0x1UL
+#define GPCDMA_XFER_DIR_MEM_TO_MEM  0x2UL
+
+/* Supported IO bus widths for DMA transfers */
+typedef uint32_t gpcdma_bus_width;
+
+#define GPCDMA_IO_BUS_WIDTH_8       0x0UL
+#define GPCDMA_IO_BUS_WIDTH_16      0x1UL
+#define GPCDMA_IO_BUS_WIDTH_32      0x2UL
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * direction:       A valid gpcdma_transfer_direction value.
+ * bus_width:       IO buswidth. A valid gpcdma_bus_width value.
+ * burst_size:      The number of words to transfer in each burst. Valid for
+ *                  both tx/rx transfers.
+ * src_addr:        The source address to read from.
+ * src_addr_wrap:   The number of word transfers to make before wrapping
+ *                  the src address. 0 represents no wrap.
+ *                  Legal values for io addr wrap are 2^n with n from
+ *                  0 through 6.
+ *                  Legal values for mc addr wrap are 2^n with n from
+ *                  5 through 11.
+ * dst_addr:        The target address to write to.
+ * dst_addr_wrap:   The number of word transfers to make before wrapping
+ *                  the mc address. 0 represents no wrap.
+ *                  Legal values for io addr wrap are 2^n with n from
+ *                  0 through 6.
+ *                  Legal values for mc addr wrap are 2^n with n from
+ *                  5 through 11.
+ * period_len:      Used in continuous mode, callback will be called at
+ *                  every period_len byte transfers. It has to be word
+ *                  aligned and value must be in bytes.
+ * xfer_count:      The number of bytes to be transferred. The value must
+ *                  be word aligned. If continuous mode is used, this value
+ *                  must be multiple of period_len parameter.
+ * timeout:         Timeout for synchronous transfers.
+ * callback:        A function to execute once the transfer is done.
+ *                  Callback is valid only for asynchronous transfers.
+ * callback_param:  Data to be passed as context to the callback function.
+ * slave_req:       HW specific slave request select value. Used for both
+ *                  rx/tx transfers.
+ * src_sid:         Source stream id.
+ * dst_sid:         Destination stream id.
+ * en_flow_ctrl:    Use rx/tx slave request or not.
+ * synchronous:     Execute a synchronous transfer or not.
+ *                  If true, wait till DMA transfer is done and return
+ *                  status.
+ *                  If false, return after starting DMA transfer and execute
+ *                  the provided callback upon transfer completion.
+ * continuous:      Set the DMA continuous transfer mode. This option is
+ *                  mutually exclusive with synchronous option above.
+ */
+struct gpcdma_xfer {
+    gpcdma_transfer_direction  direction;
+    gpcdma_bus_width           bus_width;
+    uint32_t                   burst_size;
+    uint64_t                   src_addr;
+    uint32_t                   src_addr_wrap;
+    uint64_t                   dst_addr;
+    uint32_t                   dst_addr_wrap;
+    uint32_t                   period_len;
+    uint32_t                   xfer_count;
+    uint32_t                   timeout;
+    dma_callback               *callback;
+    void                       *callback_param;
+    uint8_t                    slave_req;
+    uint8_t                    src_sid;
+    uint8_t                    dst_sid;
+    bool                       en_flow_ctrl;
+    bool                       synchronous;
+    bool                       continuous;
+};
+
+/* The identity of GPCDMA controller instance */
+// IWYU pragma: no_forward_declare gpcdma_id
+struct gpcdma_id;
+
+/**
+ * @brief global initialization of the GPCDMA controller.
+ *
+ * @jama_func_req_id 17644910
+ *
+ * @pre None
+ *
+ * @param[in] id        DMA controller context
+ *
+ * @retval E_SUCCESS                        indicates success
+ * @retval E_GPCDMA_NULL_PTR                invalid id paramter passed
+ * @retval E_GPCDMA_INVALID_PARAM           invalid controller base address
+ * @retval E_GPCDMA_PORT_INIT_FAIL          port specific init failed
+ * @retval E_GPCDMA_PORT_CHAN_SETUP_FAIL    port specific channel setup failed
+ */
+error_t gpcdma_init(struct gpcdma_id *id);
+
+/**
+ * @brief Execute DMA transfer on the specified channel.
+ *
+ * @jama_func_req_id 17645012
+ *
+ * For synchronous transfers, transfer status would be returned.
+ * For asynchronous transfers, provided callback would be executed upon
+ * transfer completion.
+ *
+ * @pre the function gpcdma_init() has been called
+ *
+ * @param[in] id        DMA controller context
+ * @param[in] chan_num  DMA channel id of the controller
+ * @param[in] xfer      DMA transfer details
+ *
+ * @retval E_SUCCESS                     indicates success
+ * @retval E_GPCDMA_NULL_PTR             invalid id paramter passed
+ * @retval E_GPCDMA_INVALID_PARAM        invalid DMA channel id
+ * @retval E_GPCDMA_CHAN_BUSY            DMA channel is busy
+ * @retval E_GPCDMA_INVALID_XFER_DIR     invalid transfer direction
+ * @retval E_GPCDMA_NO_CALLBACK_ASYNC    No callback provided for asynchrous
+ *                                       transfer
+ * @retval E_GPCDMA_INVALID_XFER_SIZE    invalid transfer size
+ * @retval E_GPCDMA_INVALID_XFER_SIZE_IO invalid transfer size for IO<->MEM
+ * @retval E_GPCDMA_UNALIGNED_SRC        unaligned source address
+ * @retval E_GPCDMA_UNALIGNED_DST        unaligned destination address
+ * @retval E_GPCDMA_INVALID_FC_REQ_ID    invalid flow control slave request id
+ * @retval E_GPCDMA_INVALID_ADDR_WRAP    invalid source/dest address wrap
+ * @retval E_GPCDMA_PORT_SYNC_TIMEOUT    timed out for synchronous transfers
+ */
+error_t gpcdma_transfer(const struct gpcdma_id *id,
+                        uint32_t chan_num,
+                        struct gpcdma_xfer const *xfer);
+
+/**
+ * @brief get transferred size of the transfer in progress
+ *
+ * @jama_func_req_id 17649722
+ *
+ * This function is used to fetch the number of bytes transferred
+ * successfully using DMA.
+ *
+ * @pre the function gpcdma_init() has been called
+ *
+ * @param[in]  id         DMA controller context
+ * @param[in]  chan_num   DMA channel id of the controller
+ * @param[out] xfer_count Total bytes transferred so far
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_GPCDMA_NULL_PTR invalid id paramter passed
+ * @retval E_GPCDMA_INVALID_PARAM invalid DMA channel id
+ */
+error_t gpcdma_get_bytes_xferred(const struct gpcdma_id *id,
+                                 uint32_t chan_num,
+                                 uint64_t *xfer_count);
+
+/**
+ * @brief Abort the DMA transfer in progress.
+ *
+ * @jama_func_req_id 17649740
+ *
+ * This function is used to abort the ongoing transfer on a dma channel.
+ *
+ * @pre the function gpcdma_init() has been called
+ *
+ * @param[in] id        DMA controller context
+ * @param[in] chan_num  DMA channel id of the controller
+ *
+ * @retval E_SUCCESS                        indicates success
+ * @retval E_GPCDMA_NULL_PTR                invalid id paramter passed
+ * @retval E_GPCDMA_INVALID_PARAM           invalid controller base address
+ */
+error_t gpcdma_abort(const struct gpcdma_id *id,
+                     uint32_t chan_num);
+
+/**
+ * @brief GPCDMA channel irq handler.
+ *
+ * @jama_func_req_id 17656319
+ *
+ * This function gets called whenever a DMA transfer is completed.
+ *
+ * @pre the function gpcdma_init() has been called
+ *
+ * @param[in] data pointer for GPCDMA channel context.
+ *
+ * @return None
+ */
+void gpcdma_chan_irq(void *data);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/gpcdma/sections-gpcdma.h b/spe-freertos-bsp/fsp/source/include/gpcdma/sections-gpcdma.h
new file mode 100644
index 0000000..a6a2634
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/gpcdma/sections-gpcdma.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GPCDMA__SECTIONS_GPCDMA_H
+#define GPCDMA__SECTIONS_GPCDMA_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_GPCDMA_DATA        SECTION_BUILDER(gpcdma,                 data)
+#define SECTION_NAME_GPCDMA_RODATA      SECTION_BUILDER(gpcdma,                 rodata)
+#define SECTION_NAME_GPCDMA_TEXT        SECTION_BUILDER(gpcdma,                 text)
+#define SECTION_NAME_GPCDMA_INIT_DATA   SECTION_BUILDER(init.gpcdma,            data)
+#define SECTION_NAME_GPCDMA_INIT_TEXT   SECTION_BUILDER(init.gpcdma,            text)
+
+#define SECTION_STR_GPCDMA_TEXT         STR(SECTION_NAME_GPCDMA_TEXT)
+#define SECTION_STR_GPCDMA_RODATA       STR(SECTION_NAME_GPCDMA_RODATA)
+#define SECTION_STR_GPCDMA_DATA         STR(SECTION_NAME_GPCDMA_DATA)
+#define SECTION_STR_GPCDMA_INIT_TEXT    STR(SECTION_NAME_GPCDMA_INIT_TEXT)
+#define SECTION_STR_GPCDMA_INIT_DATA    STR(SECTION_NAME_GPCDMA_INIT_DATA)
+
+#define SECTION_GPCDMA_TEXT             SECTION(SECTION_STR_GPCDMA_TEXT)
+#define SECTION_GPCDMA_RODATA           SECTION(SECTION_STR_GPCDMA_RODATA)
+#define SECTION_GPCDMA_DATA             SECTION(SECTION_STR_GPCDMA_DATA)
+#define SECTION_GPCDMA_INIT_TEXT        SECTION(SECTION_STR_GPCDMA_INIT_TEXT)
+#define SECTION_GPCDMA_INIT_DATA        SECTION(SECTION_STR_GPCDMA_INIT_DATA)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/gpio/gpio-error.h b/spe-freertos-bsp/fsp/source/include/gpio/gpio-error.h
new file mode 100644
index 0000000..4ccb47e
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/gpio/gpio-error.h
@@ -0,0 +1,76 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
+ *
+ * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
+ * property and proprietary rights in and to this material, related
+ * documentation and any modifications thereto. Any use, reproduction,
+ * disclosure or distribution of this material and related documentation
+ * without an express license agreement from NVIDIA CORPORATION or
+ * its affiliates is strictly prohibited.
+ */
+
+#ifndef GPIO__GPIO_ERROR_H
+#define GPIO__GPIO_ERROR_H
+#define FSP__GPIO__GPIO_ERROR_H   1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>               // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+// IWYU pragma: no_include "base/module-id.h"
+#include <base/module-id.h>               // IWYU pragma: export
+#include <misc/macros.h>                  // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
+
+/**
+ * @defgroup GPIO_Errors GPIO error macros
+ * @brief Define GPIO specific error codes.
+ * @{
+ */
+/** Error returned for invalid IRQ number */
+#define E_GPIO_INVALID_GPIO_IRQ           MODULE_ERROR(GPIO, 1UL)
+/** Error returned for invalid/NULL IRQ handler */
+#define E_GPIO_INVALID_IRQ_HANDLER        MODULE_ERROR(GPIO, 2UL)
+/** Error returned for invalid IRQ type */
+#define E_GPIO_INVALID_IRQ_TYPE           MODULE_ERROR(GPIO, 3UL)
+/** Error returned for invalid IRQ level */
+#define E_GPIO_INVALID_IRQ_LEVEL          MODULE_ERROR(GPIO, 4UL)
+/** Error returned for invalid GPIO number */
+#define E_GPIO_INVALID_GPIO               MODULE_ERROR(GPIO, 5UL)
+/** Error returned for invalid controller ID value */
+#define E_GPIO_INVALID_GPIO_CTRL_ID       MODULE_ERROR(GPIO, 6UL)
+/** Error returned for invalid/NULL controller data */
+#define E_GPIO_INVALID_CTRL_DATA          MODULE_ERROR(GPIO, 7UL)
+/** Error returned for NULL input parameters */
+#define E_GPIO_NULL_INPUT_PARAMETER       MODULE_ERROR(GPIO, 8UL)
+/** Error returned if the request is forbidden for the current state of the GPIO */
+#define E_GPIO_INVALID_CFQ_REQ            MODULE_ERROR(GPIO, 9UL)
+/** @} */
+#endif  /* GPIO__GPIO_ERRORS_H */
+
diff --git a/spe-freertos-bsp/fsp/source/include/gpio/sections-gpio.h b/spe-freertos-bsp/fsp/source/include/gpio/sections-gpio.h
new file mode 100644
index 0000000..5d02149
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/gpio/sections-gpio.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef GPIO__SECTIONS_GPIO_H
+#define GPIO__SECTIONS_GPIO_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_GPIO_DATA          SECTION_BUILDER(gpio,                   data)
+#define SECTION_NAME_GPIO_RODATA        SECTION_BUILDER(gpio,                   rodata)
+#define SECTION_NAME_GPIO_TEXT          SECTION_BUILDER(gpio,                   text)
+#define SECTION_NAME_GPIO_INIT_DATA     SECTION_BUILDER(init.gpio,              data)
+#define SECTION_NAME_GPIO_INIT_TEXT     SECTION_BUILDER(init.gpio,              text)
+
+#define SECTION_STR_GPIO_TEXT           STR(SECTION_NAME_GPIO_TEXT)
+#define SECTION_STR_GPIO_RODATA         STR(SECTION_NAME_GPIO_RODATA)
+#define SECTION_STR_GPIO_DATA           STR(SECTION_NAME_GPIO_DATA)
+#define SECTION_STR_GPIO_INIT_TEXT      STR(SECTION_NAME_GPIO_INIT_TEXT)
+#define SECTION_STR_GPIO_INIT_DATA      STR(SECTION_NAME_GPIO_INIT_DATA)
+
+#define SECTION_GPIO_TEXT               SECTION(SECTION_STR_GPIO_TEXT)
+#define SECTION_GPIO_RODATA             SECTION(SECTION_STR_GPIO_RODATA)
+#define SECTION_GPIO_DATA               SECTION(SECTION_STR_GPIO_DATA)
+#define SECTION_GPIO_INIT_TEXT          SECTION(SECTION_STR_GPIO_INIT_TEXT)
+#define SECTION_GPIO_INIT_DATA          SECTION(SECTION_STR_GPIO_INIT_DATA)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
+
diff --git a/spe-freertos-bsp/fsp/source/include/gpio/tegra-gpio-priv.h b/spe-freertos-bsp/fsp/source/include/gpio/tegra-gpio-priv.h
new file mode 100644
index 0000000..8297588
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/gpio/tegra-gpio-priv.h
@@ -0,0 +1,105 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
+ *
+ * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
+ * property and proprietary rights in and to this material, related
+ * documentation and any modifications thereto. Any use, reproduction,
+ * disclosure or distribution of this material and related documentation
+ * without an express license agreement from NVIDIA CORPORATION or
+ * its affiliates is strictly prohibited.
+ */
+
+#ifndef GPIO__TEGRA_GPIO_PRIV_H
+#define GPIO__TEGRA_GPIO_PRIV_H
+#define FSP__GPIO__TEGRA_GPIO_PRIV_H  1
+
+/* Compiler headers */
+#include <stdbool.h>                       // for bool
+#include <stdint.h>                        // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <soc-common/hw-const.h>           // for MK_U32_CONSTANT
+
+/* Hardware headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
+/**
+ * Number of GPIO pins per port/bank
+ */
+#define GPIOS_PER_BANK    MK_U32_CONST(8)
+
+/**
+ * @struct gpio_irq_handler
+ * @brief IRQ handler structure
+ * @{
+ */
+struct gpio_irq_handler {
+    /** Pointer to the interrupt service routine */
+    void (*handler)(void *hdata);
+    /** Data to be used by the interrupt handler */
+    void *data;
+};
+/** @} */
+
+/**
+ * @struct tegra_gpio_id
+ * @brief Tegra GPIO structure
+ * @{
+ */
+struct tegra_gpio_id {
+    /**  Base address of GPIO controller */
+    uint32_t                base_addr;
+    /** Number of GPIO banks/ports supported by the GPIO chip */
+    uint32_t                bank_count;
+    /** Pointer to an array storing base address of the GPIO banks. */
+    const uint32_t          *bank_bases;
+    /**
+     * Pointer to any array storing irq number of all the GPIO
+     * sub-controllers (HW controllers) supported by this instance.
+     */
+    uint32_t                *irqs;
+    /** Number of irqs supported by this GPIO controller */
+    uint32_t                nirqs;
+    /**
+     * Pointer to array storing IRQ handlers mapped one-to-one
+     * with the gpio pins
+     */
+    struct gpio_irq_handler *irq_handlers;
+    /** Offset of IRQ status register relative to the ENABLE_CONFIG register */
+    uint32_t                irq_status_offset;
+    /** Pointer to the array storing IRQ enable status per GPIO bank */
+    uint8_t                 *bank_irq_status;
+    /**
+     * Boolean variable indicating GPIO interrupt handling mechanism. Set it
+     * to false, if the client does not need GPIO interrupts or chooses to
+     * use its own interrupt handling mechanism instead of registering to
+     * the common GPIO IRQ handler.*/
+    bool                    isr_status;
+    /** Pointer to any array storing number of physical pins per bank */
+    const uint8_t           *num_pins;
+};
+/** @} */
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/gpio/tegra-gpio.h b/spe-freertos-bsp/fsp/source/include/gpio/tegra-gpio.h
new file mode 100644
index 0000000..4a995b5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/gpio/tegra-gpio.h
@@ -0,0 +1,541 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
+ *
+ * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
+ * property and proprietary rights in and to this material, related
+ * documentation and any modifications thereto. Any use, reproduction,
+ * disclosure or distribution of this material and related documentation
+ * without an express license agreement from NVIDIA CORPORATION or
+ * its affiliates is strictly prohibited.
+ */
+
+#ifndef GPIO__TEGRA_GPIO_H
+#define GPIO__TEGRA_GPIO_H
+#define FSP__GPIO__TEGRA_GPIO_H  1
+
+/* Compiler headers */
+#include <stdbool.h>              // for bool
+#include <stdint.h>               // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>       // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>  // for E_SUCCESS, error_t
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module FSP headers */
+#include <gpio/tegra-gpio-priv.h> // for struct tegra_gpio_id
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built int32_to the FSP source code.
+ */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+#endif
+
+#define MAX_GPIO_CONTROLLERS               2U
+
+// IWYU pragma: no_forward_declare tegra_gpio_id
+struct tegra_gpio_id;
+
+/**
+ * Define data types for GPIO IRQ type and level
+ */
+typedef uint32_t tegra_gpio_irq_type;
+typedef uint32_t tegra_gpio_irq_level;
+
+/**
+ * @defgroup IRQ_TYPES Define IRQ trigger types
+ * @brief Defines IRQ trigger types supported by the GPIO
+ * @{
+ */
+/** Macro defining no trigger for GPIO IRQ */
+#define TEGRA_GPIO_IRQ_NONE          ((tegra_gpio_irq_type)0UL)
+/** Macro defining level trigger IRQ */
+#define TEGRA_GPIO_IRQ_LEVEL         ((tegra_gpio_irq_type)1UL)
+/** Macro defining single edge trigger IRQ type */
+#define TEGRA_GPIO_IRQ_SINGLE_EDGE   ((tegra_gpio_irq_type)2UL)
+/** Macro defining double edge trigger IRQ type */
+#define TEGRA_GPIO_IRQ_DOUBLE_EDGE   ((tegra_gpio_irq_type)3UL)
+/** @} */
+
+/**
+ * @defgroup IRQ_LEVELS Define IRQ levels
+ * @brief Defines different IRQ levels supported by the GPIO
+ * @{
+ */
+/** Macro defining low level IRQ trigger */
+#define TEGRA_GPIO_IRQ_LOW_LEVEL     ((tegra_gpio_irq_level)0UL)
+/** Macro defining falling edge IRQ trigger */
+#define TEGRA_GPIO_IRQ_FALLING_EDGE  ((tegra_gpio_irq_level)0UL)
+/** Macro defining high level IRQ trigger */
+#define TEGRA_GPIO_IRQ_HIGH_LEVEL    ((tegra_gpio_irq_level)1UL)
+/** Macro defining rising edge IRQ trigger */
+#define TEGRA_GPIO_IRQ_RISING_EDGE   ((tegra_gpio_irq_level)1UL)
+/** @} */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
+
+/**
+ * @brief Construct a global GPIO ID.
+ *
+ * No error-range-checking is performed on the parameters or returned value.
+ *
+ * @param[in] ctrl_id    The unique ID of the GPIO controller.
+ * @param[in] gpio       The GPIO ID local to the controller.
+ *
+ * @retval global_gpio_id The global GPIO ID.
+ */
+static inline uint32_t gpio_global_id(uint8_t ctrl_id,
+                                      uint16_t gpio)
+{
+    return ((uint32_t)ctrl_id << 16) + (uint32_t)gpio;
+}
+
+/**
+ * @brief Initialize the GPIO controller
+ *
+ * This function enables the interrupts for the GPIO controller
+ * populated through the soc data and maps them to the generic GPIO
+ * interrupt handler.
+ *
+ * @param[in] ids     Array of pointer to the controller SoC data.
+ * @param[in] num_ctrls Number of GPIO controllers to be initialized
+ *
+ * @retval E_SUCCESS                    For Success
+ * @retval E_GPIO_INVALID_GPIO_IRQ      For invalid IRQ number
+ * @retval E_GPIO_INVALID_CONT_DATA     NULL pointer to controller data/Number
+ *                                      of controllers exceeds the maximum limit
+ */
+error_t tegra_gpio_init(struct tegra_gpio_id **ids, uint32_t num_ctrls);
+
+/**
+ * @brief Disable the GPIO interrupts across SC7 entry/power
+ * gating the hardware.
+ *
+ * This function disables the interrupts for the GPIO controllers
+ * populated through the soc data.
+ *
+ * @pre GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @param[in] ctrl_id ID of the GPIO controller to be suspended.
+ *
+ * @retval E_SUCCESS                    For Success
+ * @retval E_GPIO_INVALID_GPIO_IRQ      For invalid IRQ number
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID  Invalid controller ID
+ * @retval E_GPIO_INVALID_CONT_DATA     NULL pointer to controller data
+ */
+error_t tegra_gpio_suspend(uint32_t ctrl_id);
+
+/**
+ * @brief Enable the GPIO interrupts across SC7 exit/un-power gating
+ * the hardware.
+ *
+ * This function disables the interrupts for the GPIO controller
+ * populated through the soc data.
+ *
+ * @pre GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @param[in] ctrl_id ID of the GPIO controller to be resumed.
+ *
+ * @retval E_SUCCESS                    For Success
+ * @retval E_GPIO_INVALID_GPIO_IRQ      For invalid IRQ number
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID  Invalid controller ID
+ * @retval E_GPIO_INVALID_CONT_DATA     NULL pointer to controller data
+ */
+error_t tegra_gpio_resume(uint32_t ctrl_id);
+
+/**
+ * @brief Configure a GPIO to be an input.
+ *
+ * @pre GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @param[in] gpio Global GPIO number.
+ *
+ * @retval E_SUCCESS                     Success
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID   Invalid controller ID
+ * @retval E_GPIO_INVALID_GPIO           Invalid GPIO number
+ * @retval E_GPIO_INVALID_CONT_DATA      NULL pointer to controller data
+ */
+error_t tegra_gpio_direction_in(uint32_t gpio);
+
+/**
+ * @brief Configure a GPIO to be an output and set its initial output value.
+ * This is the raw value at the pin; the GPIO API performs no
+ * internal conversions to account for active-low signals, etc.
+ *
+ * @pre GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @param[in] gpio  Global GPIO number.
+ * @param[in] value The value to drive on the GPIO.
+ *
+ * @retval E_SUCCESS                     Success
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID   Invalid controller ID
+ * @retval E_GPIO_INVALID_GPIO           Invalid GPIO number
+ * @retval E_GPIO_INVALID_CFQ_REQ        Interrupt/Timestamping
+ *                                       function enabled for the GPIO
+ * @retval E_GPIO_INVALID_CONT_DATA      NULL pointer to controller data
+ */
+error_t tegra_gpio_direction_out(uint32_t gpio,
+                                 bool value);
+
+/**
+ * @brief Get direction of the GPIO
+ *
+ * Returns direction of GPIO as an integer value
+ *
+ * 0: GPIO configured for input mode
+ *
+ * 1: GPIO configured for output mode.
+ *
+ * @param[in]  gpio      Global GPIO number
+ * @param[out] gpio_dir  An in/out parameter that captures direction of the GPIO
+ *
+ * @pre GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @retval E_SUCCESS                     Success
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID   Invalid controller ID
+ * @retval E_GPIO_INVALID_GPIO           Invalid GPIO number
+ * @retval E_GPIO_INVALID_CONT_DATA      NULL pointer to controller data
+ */
+error_t tegra_gpio_get_direction(uint32_t gpio,
+                                 uint32_t *gpio_dir);
+
+/**
+ * @brief Retrieve the raw state of a GPIO.
+ *
+ * Returns raw value at the pin.
+ *
+ * False:       Success, signal is low.
+ *
+ * True:        Success, signal is high.
+ *
+ * The GPIO API performs no internal conversions to account
+ * for active-low signals, etc.
+ *
+ * @param[in]  gpio        Global GPIO number.
+ * @param[out] gpio_val    An in/out parameter that captures the raw value
+ *                         at the pin
+ *
+ * @pre GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @retval E_SUCCESS                     Success
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID   Invalid controller ID
+ * @retval E_GPIO_INVALID_GPIO           Invalid GPIO number
+ * @retval E_GPIO_INVALID_CONT_DATA      NULL pointer to controller data
+ */
+error_t tegra_gpio_get_value(uint32_t gpio,
+                             bool *gpio_val);
+
+/**
+ * @brief Retrieve the state of an output GPIO.
+ *
+ * Returns raw value at the pin.
+ *
+ * False:       Success, output signal is low.
+ *
+ * True:        Success, output signal is high.
+ *
+ * The GPIO API performs no internal conversions to account
+ * for active-low signals, etc.
+ *
+ * @pre
+ * - GPIO must be configured as an output
+ * - GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @param[in]  gpio        Global GPIO number.
+ * @param[out] gpio_val An in/out parameter that captures the raw value
+ *                         at the pin
+ *
+ * @retval E_SUCCESS                     Success
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID   Invalid controller ID
+ * @retval E_GPIO_INVALID_GPIO           Invalid GPIO number
+ * @retval E_GPIO_INVALID_CFQ_REQ        Output mode not enabled on the GPIO
+ * @retval E_GPIO_INVALID_CONT_DATA      NULL pointer to controller data
+ */
+error_t tegra_gpio_get_output_value(uint32_t gpio,
+                                    bool *gpio_val);
+
+/**
+ * @brief Retrieve the state of an input GPIO.
+ *
+ * Returns raw value at the pin
+ *
+ * False:       Success, input signal is low.
+ *
+ * True:        Success, input signal is high.
+ *
+ * The GPIO API performs no internal conversions to account
+ * for active-low signals, etc.
+ *
+ * @pre
+ * - GPIO must be configured as an input.
+ * - GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @param[in]  gpio        Global GPIO number.
+ * @param[out] gpio_val An in/out parameter that captures the raw value
+ *                        at the pin
+ *
+ * @retval E_SUCCESS                     Success
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID   Invalid controller ID
+ * @retval E_GPIO_INVALID_GPIO           Invalid GPIO number
+ * @retval E_GPIO_INVALID_CFQ_REQ        Output mode enabled on the GPIO
+ * @retval E_GPIO_INVALID_CONT_DATA      NULL pointer to controller data
+ */
+error_t tegra_gpio_get_input_value(uint32_t gpio,
+                                   bool *gpio_val);
+
+/**
+ * @brief Set the output state for a GPIO.
+ *
+ * Sets raw value at the pin.
+ *
+ * Request to drive the GPIO can take one of the following values
+ *
+ * True:  signal level high
+ *
+ * False: Signal level low.
+ *
+ * @pre
+ * - GPIO must be configured as an output.
+ * - GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @param[in] gpio  Global GPIO number.
+ * @param[in] value The value to drive on the GPIO.
+ *
+ * @retval E_SUCCESS                     Success
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID   Invalid controller ID
+ * @retval E_GPIO_INVALID_GPIO           Invalid GPIO number
+ * @retval E_GPIO_INVALID_CFQ_REQ        Output mode not enabled on the GPIO
+ * @retval E_GPIO_INVALID_CONT_DATA      NULL pointer to controller data
+ */
+error_t tegra_gpio_set_value(uint32_t gpio,
+                             bool value);
+
+/**
+ * @brief Set the debounce value for a GPIO.
+ *
+ * @pre
+ * - GPIO must be configured as an output
+ * - GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @param[in] gpio        Global GPIO number.
+ * @param[in] debounce_ms The value to program for debounce in milliseconds.
+ *
+ * @retval E_SUCCESS                     Success
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID   Invalid controller ID
+ * @retval E_GPIO_INVALID_GPIO           Invalid GPIO number
+ * @retval E_GPIO_INVALID_CFQ_REQ        Output mode enabled on the GPIO
+ * @retval E_GPIO_INVALID_CONT_DATA      NULL pointer to controller data
+ */
+error_t tegra_gpio_set_debounce(uint32_t gpio,
+                                uint32_t debounce_ms);
+
+/**
+ * @brief Set the irq type for a GPIO.
+ *
+ * @pre
+ * - GPIO must be configured as an input
+ * - GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @param[in] gpio   Global GPIO number.
+ * @param[in] type   Indicates the type based on tegra_gpio_irq_type.
+ * @param[in] level  Indicates the level based on tegra_gpio_irq_level.
+ *
+ * @retval E_SUCCESS                     Success
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID   Invalid controller ID
+ * @retval E_GPIO_INVALID_GPIO           Invalid GPIO number
+ * @retval E_GPIO_INVALID_CFQ_REQ        Output mode enabled on the GPIO
+ * @retval E_GPIO_INVALID_IRQ_LEVEL      Invalid IRQ level
+ * @retval E_GPIO_INVALID_IRQ_TYPE       Invalid IRQ type
+ * @retval E_GPIO_INVALID_CONT_DATA      NULL pointer to controller data
+ */
+error_t tegra_gpio_set_irq_type(uint32_t gpio,
+                                tegra_gpio_irq_type type,
+                                tegra_gpio_irq_level level);
+
+/**
+ * @brief Enable the IRQ for a GPIO.
+ *
+ * @pre
+ * - GPIO must be configured as an input
+ * - GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @param[in] gpio   Global GPIO number.
+ *
+ * @retval E_SUCCESS                     Success
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID   Invalid controller ID
+ * @retval E_GPIO_INVALID_GPIO           Invalid GPIO number
+ * @retval E_GPIO_INVALID_CFQ_REQ        Output mode enabled on the GPIO
+ * @retval E_GPIO_INVALID_GPIO_IRQ       Invalid IRQ number
+ * @retval E_GPIO_INAVLID_IRQ_HANDLER    NULL GPIO IRQ handler
+ * @retval E_GPIO_INVALID_CONT_DATA      NULL pointer to controller data
+ */
+error_t tegra_gpio_enable_irq(uint32_t gpio);
+
+/**
+ * @brief Enable the timestamping functionality for a GPIO.
+ *
+ * This API needs to be called for a GPIO that you are interested in
+ * monitoring using the HW timestamping engines such as GTE.
+ *
+ * @pre
+ * - GPIO must be configured as an input
+ * - GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @param[in] gpio   Global GPIO number.
+ *
+ * @retval E_SUCCESS                     Success
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID   Invalid controller ID
+ * @retval E_GPIO_INVALID_GPIO           Invalid GPIO number
+ * @retval E_GPIO_INVALID_CFQ_REQ        Output mode enabled on the GPIO
+ * @retval E_GPIO_INVALID_CONT_DATA      NULL pointer to controller data
+ */
+error_t tegra_gpio_enable_timestamp(uint32_t gpio);
+
+/**
+ * @brief Disable the timestamping functionality for a GPIO.
+ *
+ * @pre
+ * - GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @param[in] gpio   Global GPIO number.
+ *
+ * @retval E_SUCCESS                     Success
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID   Invalid controller ID
+ * @retval E_GPIO_INVALID_GPIO           Invalid GPIO number
+ * @retval E_GPIO_INVALID_CONT_DATA      NULL pointer to controller data
+ */
+error_t tegra_gpio_disable_timestamp(uint32_t gpio);
+
+/**
+ * @brief Disable the IRQ for a GPIO.
+ *
+ * @pre
+ * - GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @param[in] gpio   Global GPIO number.
+ *
+ * @retval E_SUCCESS                     Success
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID   Invalid controller ID
+ * @retval E_GPIO_INVALID_GPIO           Invalid GPIO number
+ * @retval E_GPIO_INVALID_GPIO_IRQ       Invalid IRQ number
+ * @retval E_GPIO_INAVLID_IRQ_HANDLER    NULL GPIO IRQ handler
+ * @retval E_GPIO_INVALID_CONT_DATA      NULL pointer to controller data
+ */
+error_t tegra_gpio_disable_irq(uint32_t gpio);
+
+/**
+ * @brief Register an interrupt service routine for a GPIO.
+ *
+ * @pre
+ * - GPIO must be configured as an input
+ * - GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @param[in] gpio      Global GPIO number.
+ * @param[in] handler   Pointer to the service routine.
+ * @param[in] data      opaque data pointer for the service routine.
+ *
+ * @retval E_SUCCESS                     Success
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID   Invalid controller ID
+ * @retval E_GPIO_INVALID_GPIO           Invalid GPIO number
+ * @retval E_GPIO_INVALID_CFQ_REQ        Output mode enabled on the GPIO
+ * @retval E_GPIO_INVALID_GPIO_IRQ       Invalid IRQ number
+ * @retval E_GPIO_INAVLID_IRQ_HANDLER    NULL GPIO IRQ handler
+ * @retval E_GPIO_INVALID_CONT_DATA      NULL pointer to controller data
+ */
+error_t tegra_gpio_set_irq_handler(uint32_t gpio,
+                                   void (*handler)(void *hdata),
+                                   void *data);
+
+/**
+ * @brief Unregister an interrupt service routine for a GPIO.
+ *
+ * @pre
+ * - GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @param[in] gpio  Global GPIO number.
+ *
+ * @retval E_SUCCESS                     Success
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID   Invalid controller ID
+ * @retval E_GPIO_INVALID_GPIO           Invalid GPIO number
+ * @retval E_GPIO_INVALID_GPIO_IRQ       Invalid IRQ number
+ * @retval E_GPIO_INVALID_CONT_DATA      NULL pointer to controller data
+ */
+error_t tegra_gpio_clear_irq_handler(uint32_t gpio);
+
+/**
+ * @brief Read IRQ status of a GPIO pin
+ *
+ * @pre
+ * - GPIO must be configured as an input
+ * - GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @param[in]  gpio        Global GPIO
+ * @param[out] irq_status  An in/out parameter to save IRQ status of the GPIO
+ *                         pin.
+ *
+ * @retval E_SUCCESS                     Success
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID   Invalid controller ID
+ * @retval E_GPIO_INVALID_GPIO           Invalid GPIO number
+ * @retval E_GPIO_INVALID_CFQ_REQ        Output mode enabled on the GPIO
+ * @retval E_GPIO_INVALID_GPIO_IRQ       Invalid IRQ number
+ * @retval E_GPIO_INVALID_CONT_DATA      NULL pointer to controller data
+ */
+error_t tegra_gpio_read_irq_status(uint32_t gpio, bool *irq_status);
+
+/**
+ * @brief Clear IRQ status of a GPIO pin
+ *
+ * @pre
+ * - GPIO must be configured as an input
+ * - GPIO controller should have been initialized as part of tegra_gpio_init
+ *
+ * @param[in] gpio Global GPIO number
+ *
+ * @retval E_SUCCESS                     Success
+ * @retval E_GPIO_INVALID_GPIO_CONT_ID   Invalid controller ID
+ * @retval E_GPIO_INVALID_GPIO           Invalid GPIO number
+ * @retval E_GPIO_INVALID_CFQ_REQ        Output mode enabled on the GPIO
+ * @retval E_GPIO_INVALID_GPIO_IRQ       Invalid IRQ number
+ * @retval E_GPIO_INVALID_CONT_DATA      NULL pointer to controller data
+ */
+error_t tegra_gpio_clear_irq_status(uint32_t gpio);
+
+/**
+ * @brief GPIO interrupt handler.
+ *
+ * This function calls the interrupt handler corresponding to the
+ * GPIO pin as mapped by the client using tegra_gpio_set_irq_handler.
+ *
+ * @pre
+ * - GPIO controller should have been initialized as part of tegra_gpio_init.
+ *
+ * @param[in] data Pointer to the GPIO controller data
+ *
+ * @return None
+ */
+void tegra_gpio_irq_handler(void *data);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/hsp/hsp-errors.h b/spe-freertos-bsp/fsp/source/include/hsp/hsp-errors.h
new file mode 100644
index 0000000..76459ad
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/hsp/hsp-errors.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef HSP__HSP_ERRORS_H
+#define HSP__HSP_ERRORS_H
+#define FSP__HSP__HSP_ERRORS_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>	// IWYU pragma: export
+                                // IWYU pragma: no_include "base/module-id.h"
+#include <misc/macros.h>        // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @file hsp-errors.h
+ * @brief Error codes that are specific to the hsp
+ */
+
+#define E_HSP_ERR_EMPTY_MBOX        MODULE_ERROR(HSP, 0UL)
+#define E_HSP_ERR_NULL_PTR          MODULE_ERROR(HSP, 1UL)
+#define E_HSP_ERR_NO_DB             MODULE_ERROR(HSP, 2UL)
+#define E_HSP_ERR_NO_MBOX           MODULE_ERROR(HSP, 3UL)
+#define E_HSP_ERR_NO_SHRD_SMPHR     MODULE_ERROR(HSP, 4UL)
+#define E_HSP_ERR_NO_INTR           MODULE_ERROR(HSP, 5UL)
+#define E_HSP_ERR_INVALID_CALLBACK  MODULE_ERROR(HSP, 6UL)
+INLINE_RFD(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx", MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#define E_HSP_ERR_INVALID_DATA      MODULE_ERROR(HSP, 7UL)
+
+#endif  /* HSP__HSP_ERRORS_H */
diff --git a/spe-freertos-bsp/fsp/source/include/hsp/hsp-tegra-defs.h b/spe-freertos-bsp/fsp/source/include/hsp/hsp-tegra-defs.h
new file mode 100644
index 0000000..1e4d590
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/hsp/hsp-tegra-defs.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef HSP__HSP_TEGRA_DEFS_H
+#define HSP__HSP_TEGRA_DEFS_H
+#define FSP__HSP__HSP_TEGRA_DEFS_H                      1
+
+/* Hardware headers */
+#include <address_map_new.h>        // for NV_ADDRESS_MAP_TOP0_HSP_COMMON_SIZE
+#include <arhsp_dbell.h>            // for HSP_DBELL_0_ENABLE_0, HSP_DBELL_0...
+#include <arhsp_int.h>              // for HSP_INT_DIMENSIONING_0_nDB_SHIFT
+#include <arhsp_shrd_mbox.h>        // for HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0...
+#include <arhsp_shrd_sem.h>         // for HSP_SHRD_SEM_0_SHRD_SMP_STA_0...
+
+/* Late FSP headers */
+#include <misc/macros.h>            // for START_RFD_BLOCk, END_RFD_BLOCK, INLINE_RFD
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+/**
+ * @file hsp/hsp-tegra-defs.h
+ * @brief defines that are internal to the HSP driver
+ */
+
+/**
+ * @brief HSP commmon instance size
+ *
+ * Defines the HSP instance size
+ */
+#define HSP_COMMON_SIZE ((uint32_t)(NV_ADDRESS_MAP_TOP0_HSP_COMMON_SIZE))
+
+/**
+ * @brief HSP interrupt enable register offset
+ *
+ * Defines the HSP interrupt enable register offset
+ */
+#define HSP_INT_IE_OFFSET (HSP_INT_IE_1 - HSP_INT_IE_0)
+
+/**
+ * @brief HSP shared mailbox registers offset
+ *
+ * Defines the HSP shared mailbox registers offset
+ */
+#define HSP_SHRD_MBOX_OFFSET \
+        ((uint32_t)HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0 - (uint32_t)HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0)
+
+#define HSP_SHRD_MBOX_FULL_IE_OFFSET \
+        ((uint32_t)HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0)
+
+#define HSP_SHRD_MBOX_EMPTY_IE_OFFSET \
+        ((uint32_t)HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0)
+
+/**
+ * @brief HSP shared mailbox TAG field bit mask
+ *
+ * Defines the bit mask for the HSP shared mailbox TAG field
+ */
+#define HSP_SHRD_MBOX_TAG_FIELD ((uint32_t)1 << HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_TAG_SHIFT)
+
+#define HSP_SHRD_MBOX_TAG_FULL (HSP_SHRD_MBOX_TAG_FIELD)
+#define HSP_SHRD_MBOX_TAG_EMPTY 0U
+
+/**
+ * @brief HSP shared mailbox DATA field bit mask
+ *
+ * Defines the bit mask for the HSP shared mailbox DATA field
+ */
+#define HSP_SHRD_MBOX_DATA_FIELD (HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_DATA_FIELD)
+
+/**
+ * @brief HSP doorbell registers offset
+ *
+ * Defines the HSP doorbell registers offset
+ */
+#define HSP_DBELL_OFFSET (HSP_DBELL_1_TRIGGER_0 - HSP_DBELL_0_TRIGGER_0)
+
+/**
+ * @brief HSP dimensioning field
+ *
+ * Defines the bit mask to extract the specific HSP dimensioning field
+ * for a HSP instance
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_20_10, "Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx")
+#define HSP_INT_DIMENSIONING_FIELD(regval, field) \
+        (((regval) >> HSP_INT_DIMENSIONING_0_ ## field ## _SHIFT) & \
+                (((uint32_t)0xf << HSP_INT_DIMENSIONING_0_ ## field ## _SHIFT) >> \
+                        HSP_INT_DIMENSIONING_0_ ## field ## _SHIFT))
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_20_10, "Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx")
+
+/**
+ * @brief shared semaphore status register offset
+ *
+ * Defines the HSP shared semaphore status register offset
+ */
+#define HSP_SHRD_SEM_STA    (HSP_SHRD_SEM_0_SHRD_SMP_STA_0)
+
+/**
+ * @brief shared semaphore set register offset
+ *
+ * Defines the HSP shared semaphore set register offset
+ */
+#define HSP_SHRD_SEM_SET    (HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0)
+
+/**
+ * @brief shared semaphore clear register offset
+ *
+ * Defines the HSP shared semaphore clear register offset
+ */
+#define HSP_SHRD_SEM_CLR    (HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0)
+
+/**
+ * @brief shared semaphore registers offset
+ *
+ * Defines the HSP shared semaphore registers offset
+ */
+#define HSP_SHRD_SEM_OFFSET  \
+    ((uint32_t)HSP_SHRD_SEM_1_SHRD_SMP_STA_0 - (uint32_t)HSP_SHRD_SEM_0_SHRD_SMP_STA_0)
+
+/**
+ * @brief HSP interrupt register mailbox full assert field
+ *
+ * Defines the mailbox full assert field for HSP interrupt register
+ */
+#define HSP_INT_IR_0_mbox_full_assert_FIELD \
+    ((uint32_t)0xFFU << HSP_INT_IR_0_mbox_full_asserted_SHIFT)
+
+/**
+ * @brief invalid data pattern for HSP shared mailbox register
+ *
+ * Defines the invalid data pattern for the HSP shared mailbox register
+ * due to the HW bug 200395605.
+ */
+#if defined(HW_BUG_200395605) && (HW_BUG_200395605 == 1)
+    #define DEAD1001 MK_U32_CONST(0xdead1001)
+#endif
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/hsp/hsp-tegra-priv.h b/spe-freertos-bsp/fsp/source/include/hsp/hsp-tegra-priv.h
new file mode 100644
index 0000000..38faf20
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/hsp/hsp-tegra-priv.h
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef HSP__HSP_TEGRA_PRIV_H
+#define HSP__HSP_TEGRA_PRIV_H
+#define FSP__HSP__HSP_TEGRA_PRIV_H                      1
+
+/**
+ * @file hsp/hsp-tegra-priv.h
+ * @brief Structures that are internal to the HSP driver
+ */
+
+/* Compiler headers */
+#include <stdbool.h>
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>        // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <hsp/hsp-tegra.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HSP__HSP_TEGRA_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @brief Maximum number of HSP shared mailboxes per instance
+ *
+ * Defines the maximum number of shared mailboxes that are available
+ * per instance.
+ */
+#define MAX_TEGRA_HSP_SM  8U
+
+/**
+ * @brief HSP configuration structure
+ *
+ * Structure that describes the configuration of a HSP instance.
+ *
+ * @base_addr       base address of the HSP instance
+ * @host_id         host identifier of the HSP instance
+ * @db_irq          doorbell irq number, UINT32_MAX if none
+ * @sh_irq          shared irq number, UINT32_MAX if none
+ * @si_index        which shared IRQ is used, UINT8_MAX if none
+ */
+struct tegra_hsp_conf {
+    uint32_t base_addr;
+    uint32_t host;
+    uint32_t db_irq;
+    uint32_t sh_irq;
+    uint8_t si_index;
+};
+
+/**
+ * @brief HSP mailbox callback configuration structure
+ *
+ * Structure that describes the callback configuration of a shared
+ * mailbox irq.
+ *
+ * @wide        32-bit or 128-bit
+ * @callback    callback for the mailbox irq
+ * @opaque      opaque data pointer for the callback
+ */
+struct hsp_sm {
+    bool wide;
+    tegra_hsp_sm_callback callback;
+    void *opaque;
+};
+
+/**
+ * @brief HSP context ID structure
+ *
+ * Structure that is used by the HSP driver to manage the HSP instance
+ * during run time.
+ *
+ * @conf            HSP configuration of an instance
+ * @db_callback     callback function on doorbell signal
+ * @db_base         doorbell base address
+ * @ss_base         shared semaphore base address
+ * @sie_mask        shared interrupt enable mask
+ * @sm              shared mailbox callback configuration array
+ * @n_sm            number of shared mailboxes
+ * @n_ss            number of shared semaphores
+ * @n_as            number of arbitrated semaphores
+ * @n_db            doorbell count
+ * @n_si            shared interrupt count
+ * @inited          initialization status
+ * @inited          suspend status across power gating states
+ */
+struct tegra_hsp_id {
+    struct tegra_hsp_conf const conf;
+    tegra_hsp_db_callback db_callback;
+    uint32_t db_base;
+    uint32_t ss_base;
+    uint32_t sie_mask;
+    struct hsp_sm sm[MAX_TEGRA_HSP_SM];
+    uint8_t n_sm;
+    uint8_t n_ss;
+    uint8_t n_as;
+    uint8_t n_db;
+    uint8_t n_si;
+    bool    inited;
+    bool    suspended;
+};
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/hsp/hsp-tegra.h b/spe-freertos-bsp/fsp/source/include/hsp/hsp-tegra.h
new file mode 100644
index 0000000..5c91548
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/hsp/hsp-tegra.h
@@ -0,0 +1,754 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef HSP__HSP_TEGRA_H
+#define HSP__HSP_TEGRA_H
+#define FSP__HSP__HSP_TEGRA_H                           1
+
+/* Compiler headers */
+#include <stdint.h>                     // for uint32_t
+#include <stdbool.h>                    // for bool
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <ospl/rtos-port.h>             // for FSP__OSPL__RTOS_PORT_H, rtosBool
+#include <error/common-errors.h>        // for error_t, FSP__ERROR__COMMON...
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file hsp-tegra.h
+ * @brief functions that provide access to various HSP registers.
+ */
+
+/** @defgroup hsp HSP – Hardware Synchronization Primitives
+ *
+ * HSP is a simple hardware block for communication between CCPLEX and
+ * auxiliary processor. There are SoC-wide "top" HSP blocks and HSP
+ * blocks specific to their auxiliary processor (SCE, APE, RCE, SPE
+ * and BPMP). The Top1 and HSP blocks for auxiliary processors provide
+ * 5 shared interrupts (8 in Top1), 8 shared mailboxes and 4 shared
+ * semaphores. The Top0 HSP block also provide doorbells and
+ * arbitrated semaphores, but only 2 shared semaphores.
+ *
+ * Each hardware instance is represented by hardware interface
+ * descriptor with type struct tegra_hsp_id specifying the hardware
+ * resources (like base address and interrupt line number) specific to
+ * the hardware instance and its user. There can be multiple interface
+ * descriptors referring to the same hardware instance, for example,
+ * the mailboxes on AON HSP are used by multiple processors for the
+ * combined UART.
+ *
+ * The hardware interface descriptor has a configuration field represented
+ * by struct tegra_hsp_conf that is read-only.
+ *
+ * All driver methods are passed a pointer to the hardware interface
+ * descriptor as their first argument.
+ *
+ * If a driver method is provided an uninitialized hardware interface
+ * descriptor, invalid shared mailbox number or invalid shared
+ * semaphore number, the method is a no-op will not read or write to
+ * the hardware, unless otherwise specified.
+ *
+ * All argument pointers must be non-NULL unless otherwise specified.
+ *
+ * @par HSP Dimensioning
+ *
+ * Each HSP instance has a dimensioning register describing the HW
+ * layout of the device:
+ * - number of shared mailboxes
+ * - number of shared semaphores
+ * - number of arbitrated semaphores (no implementation in common driver)
+ * - number of doorbells
+ * - number of shared interrupts
+ * The address map of the HSP instances vary and the above information
+ * is used to calculate offsets to blocks inside the HSP address
+ * space.
+ *
+ * @par HSP Shared Interrupts
+ *
+ * One of the shared interrupts lines is connected directly to the
+ * interrupt controller of the auxiliary processor. The rest of the
+ * shared interrupt lines are connected to LIC (Legacy Interrupt
+ * Controller, intermediate interrupt controller that can deliver
+ * interrupts to either CCPLEX CPUs or any of the auxiliary CPUs.
+ *
+ * The shared interrupt can combine interrupts from multiple sources:
+ * shared mailboxes, doorbell and arbitrated semaphores. One interrupt
+ * line is exclusively owned by single entity (VM running on CCPLEX or
+ * auxiliary processor).
+ *
+ * @par HSP Shared Mailboxes
+ *
+ * The shared mailboxes are 32-bit wide registers with a very simple
+ * interrupt mechanism controlled by their most significant bit.
+ * Their simplest operating model is single writer/single reader.
+ *
+ * Each shared mailbox has the following resources:
+ * - A 32 bit register
+ * - Full and empty interrupts controlled by the value of the MSB.
+ *   The MSB is interpreted as a Valid bit, so the full interrupt is
+ *   the value of the MSB and the empty interrupt is the inverted
+ *   value of the MSB.
+ * - Enable bits for full and empty interrupts
+ *
+ * @par HSP Shared Semaphores
+ *
+ * The shared semaphores are formed by three registers, each 32 bits wide:
+ * - A read-only register showing the current value of the semaphore
+ * - Two write-only registers to set and clear individual semaphore bits
+ *
+ * These semaphores can be used for synchronizing processors acting in
+ * a producer/consumer relationship, i.e. a pair of them can be used
+ * to implement either a two or four way handshake. Correct operation
+ * of the shared semaphores requires statically allocating an owner
+ * for each bit, as it is impossible to implement an atomic test and
+ * set (or similar operation) given the register interface.
+ *
+ * @{
+ */
+
+#define HSP_SM_TYPE_32          0UL
+#define HSP_SM_TYPE_128         1UL
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/*
+ * Declaration for tegra_hsp_id that allows the APIs to take a pointer to it
+ * without actually defining its contents here.
+ */
+// IWYU pragma: no_forward_declare tegra_hsp_id
+struct tegra_hsp_id;
+
+/**
+ * @brief HSP context saving structure
+ *
+ * Provides the context parameters to save and restore across power gating
+ * the hardware/SC7.  Used in tegra_hsp_[suspend/resume]().
+ *
+ * @db_enable	save the enable masters across power gating the HW
+ * @si_enable	save the shared interrupt enable status
+ */
+struct tegra_hsp_suspend_ctx {
+    uint32_t db_enable;
+    uint32_t si_enable;
+};
+
+/**
+ * @brief HSP mailbox 128-bit descriptor
+ *
+ * Provides a data type for the 128-bit data for the wider mailboxes.
+ *
+ * @d0          data represeting 0-31 bits of the 128-bit data
+ * @d1          data represeting 32-63 bits of the 128-bit data
+ * @d2          data represeting 64-95 bits of the 128-bit data
+ * @d3          data represeting 96-127 bits of the 128-bit data
+ * @tag         tag value to trigger the interrupt
+ */
+typedef struct {
+    uint32_t d0;
+    uint32_t d1;
+    uint32_t d2;
+    uint32_t d3;
+    uint32_t tag;
+} hsp128_t;
+
+/**
+ * @brief HSP mailbox data field descriptor
+ *
+ * Provides a data type for the data field of the shared mailboxes.
+ *
+ * @data        data field of the 128-bit mailbox
+ * @val         data field of the 32 bit mailbox
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_19_2, "Approval: Bug 200543136, DR: SWE-FSP-033-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+typedef struct {
+    union {
+        hsp128_t data;
+        uint32_t val;
+    } sm;
+} hsp_sm_data_t;
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_19_2, "Approval: Bug 200543136, DR: SWE-FSP-033-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @brief HSP doorbell callback function
+ *
+ * This is used to define the callback function that can be
+ * supplied and is called when a doorbell irq occurs.
+ *
+ * @param[in] source id of the processor that raised the doorbell signal
+ * @param[in] higher_prio_task_woken required for task context switch
+ *
+ * @return none
+ */
+typedef void (*tegra_hsp_db_callback)(uint32_t source,
+                                      rtosBool *higher_prio_task_woken);
+
+/**
+ * @brief HSP mailbox callback function
+ *
+ * This is used to define the callback function that can be
+ * supplied and is called when a mailbox irq occurs.
+ *
+ * @param[in] data  opaque data pointer for the callback
+ * @param[in] value pointer to the content of the shared mailbox
+ *
+ * @return none
+ */
+typedef void (*tegra_hsp_sm_callback)(void *data,
+                                      hsp_sm_data_t *value);
+
+/**
+ * @brief Initialize the HSP instance and setup doorbel callback
+ *
+ * @jama_func_req_id 12997720
+ *
+ * This function initializes the HSP context for an instance, registers the
+ * callback for doorbell irq and enables the masters to raise the doorbell.
+ *
+ * @param[in] id HSP instance.
+ * @param[in] enabled_masters bit mask of the master ids that can raise the
+ *            doorbell signal. valid masters are as follows:
+ *            TEGRA_HSP_DB_MASTER_CCPLEX
+ *            TEGRA_HSP_DB_MASTER_DPMU
+ *            TEGRA_HSP_DB_MASTER_BPMP
+ *            TEGRA_HSP_DB_MASTER_SPE
+ *            TEGRA_HSP_DB_MASTER_SCE
+ *            TEGRA_HSP_DB_MASTER_DMA
+ *            TEGRA_HSP_DB_MASTER_TSECA
+ *            TEGRA_HSP_DB_MASTER_TSECB
+ *            TEGRA_HSP_DB_MASTER_JTAGM
+ *            TEGRA_HSP_DB_MASTER_CSITE
+ *            TEGRA_HSP_DB_MASTER_APE
+ *            TEGRA_HSP_DB_MASTER_RCE
+ *            TEGRA_HSP_DB_MASTER_NON_SECURE
+ * @param[in] callback callback that gets called from HSP DB irq handler.
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_DB no doorbell support
+ * @retval E_HSP_ERR_INVALID_CALLBACK invalid doorbell callback
+ */
+error_t tegra_hsp_db_init(struct tegra_hsp_id *id,
+                          uint32_t enabled_masters,
+                          tegra_hsp_db_callback callback);
+
+/**
+ * @brief raise the doorbell signal for the target processor.
+ *
+ * @jama_func_req_id 10710297
+ *
+ * This function raises the doorbell signal to the target processor.
+ *
+ * @pre the function tegra_hsp_db_init() has been called
+ *
+ * @param[in] id HSP instance.
+ * @param[in] target master ID of the target. valid targets are:
+ *            TEGRA_HSP_DB_DPMU
+ *            TEGRA_HSP_DB_CCPLEX
+ *            TEGRA_HSP_DB_CCPLEX_TZ
+ *            TEGRA_HSP_DB_BPMP
+ *            TEGRA_HSP_DB_SPE
+ *            TEGRA_HSP_DB_SCE
+ *            TEGRA_HSP_DB_APE
+ *            TEGRA_HSP_DB_RCE
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_DB no doorbell support
+ */
+error_t tegra_hsp_db_ring(const struct tegra_hsp_id *id,
+                          uint32_t target);
+
+/**
+ * @brief enable the master ids that can raise doorbell signal
+ *
+ * @jama_func_req_id 10715379
+ *
+ * This function enables the master ids that can raise a doorbell
+ * signal to the this target processor.
+ *
+ * @pre the function tegra_hsp_db_init() has been called
+ *
+ * @param[in] id HSP instance.
+ * @param[in] enabled_masters bit mask of the master ids that can raise the
+ *            doorbell signal. Range: [0 - UINT16_MAX]
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_DB no doorbell support
+ */
+error_t tegra_hsp_db_enable_master(const struct tegra_hsp_id *id,
+                                   uint32_t enabled_masters);
+
+/**
+ * @brief disable the master ids that can raise doorbell signal
+ *
+ * @jama_func_req_id 10716165
+ *
+ * This function disbles the master ids to prevent servicing doorbell
+ * signals from this.
+ *
+ * @pre the function tegra_hsp_db_init() has been called
+ *
+ * @param[in] id HSP instance.
+ * @param[in] disabled_masters bit mask of the master ids that are disabled from
+ *            raising the doorbell signal. Range: [0- UNIT16_MAX].
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_DB no doorbell support
+ */
+error_t tegra_hsp_db_disable_master(const struct tegra_hsp_id *id,
+                                    uint32_t disabled_masters);
+
+/**
+ * @brief HSP doorbell irq handler.
+ *
+ * @jama_func_req_id 12999372
+ *
+ * This function gets called whenever a remote processor has raised a doorbell
+ * signal for this master.
+ *
+ * @pre the function tegra_hsp_db_init() has been called
+ *
+ * @param[in] data pointer for HSP context.
+ *
+ * @return None
+ */
+void tegra_hsp_db_irq_handler(void *data);
+
+/**
+ * @brief HSP mailbox irq handler.
+ *
+ * @jama_func_req_id 12999352
+ *
+ * This function gets called whenever a mailbox full/empty interrupt is
+ * triggered.
+ *
+ * @pre the function tegra_hsp_init() has been called
+ *
+ * @param[in] data pointer for HSP context.
+ *
+ * @return None
+ */
+void tegra_hsp_irq_handler(void *data);
+
+/**
+ * @brief save the HSP context across SC7 entry/power gating the hardware
+ *
+ * @jama_func_req_id 10707279
+ *
+ * This function preserves the context such as the enabled doorbells and SIs
+ * across power gating the hardware(SC7).
+ *
+ * @pre the function tegra_hsp_db_init()/tegra_hsp_init() has been called
+ *
+ * @param[in] id HSP instance.
+ * @param[in] sctx A pointer to where the saved context can be stored.
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ */
+error_t tegra_hsp_suspend(struct tegra_hsp_id *id,
+                          struct tegra_hsp_suspend_ctx *sctx);
+
+/**
+ * @brief resume the HSP context across SC7 exit/unpower gating the hardware
+ *
+ * @jama_func_req_id 10707285
+ *
+ * This function restores the context such as the enabled doorbells and SIs
+ * across power gating the hardware(SC7).
+ *
+ * @pre the function tegra_hsp_db_init()/tegra_hsp_init() has been called
+ *
+ * @param[in] id HSP instance.
+ * @param[in] sctx A pointer to where the saved context was previously stored.
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ */
+error_t tegra_hsp_resume(struct tegra_hsp_id *id,
+                         const struct tegra_hsp_suspend_ctx *sctx);
+
+/**
+ * @brief Initialize the HSP context
+ *
+ * @jama_func_req_id 10708482
+ *
+ * This function initializes the HSP context for an instance, enables the
+ * HSP doorbell and shared mailbox interrupts.
+ *
+ * @param[in] id pointer to the HSP descriptor instance.
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ */
+error_t tegra_hsp_init(struct tegra_hsp_id *id);
+
+/**
+ * @brief Enable HSP shared mailbox full interrupt.
+ *
+ * @jama_func_req_id 10709553
+ *
+ * This function enables the HSP shared mailbox full interrupt. This function
+ * defaults to 32-bit shared mailbox types if the client has not explicitly
+ * called tegra_hsp_set_sm_type() to indicate the mailbox width.
+ *
+ * @pre the function tegra_hsp_db_init()/tegra_hsp_init() has been called
+ *
+ * @param[in] id HSP instance.
+ * @param[in] sm Shared mailbox index. Range: [0- MAX SM INDEX of the instance]
+ * @param[in] cb callback to be called on an IRQ.
+ * @param[in] data opaque data pointer for the callback.
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_MBOX invalid shared mailbox index
+ * @retval E_HSP_ERR_NO_INTR no HSP interrupt support
+ */
+error_t tegra_hsp_sm_full_enable(struct tegra_hsp_id *id,
+                                 uint32_t sm,
+                                 tegra_hsp_sm_callback cb,
+                                 void *data);
+
+/**
+ * @brief Disable HSP shared mailbox full interrupt.
+ *
+ * @jama_func_req_id 10709868
+ *
+ * This function disables the HSP shared mailbox full interrupt.
+ *
+ * @pre the function tegra_hsp_db_init()/tegra_hsp_init() has been called
+ *
+ * @param[in] id HSP instance.
+ * @param[in] sm Shared mailbox index. Range: [0- MAX SM INDEX of the instance]
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_MBOX invalid shared mailbox index
+ * @retval E_HSP_ERR_NO_INTR no HSP interrupt support
+ */
+error_t tegra_hsp_sm_full_disable(struct tegra_hsp_id *id,
+                                  uint32_t sm);
+
+/**
+ * @brief Enable HSP shared mailbox empty interrupt.
+ *
+ * @jama_func_req_id 10709979
+ *
+ * This function enables the HSP shared mailbox empty interrupt. This function
+ * defaults to 32-bit shared mailbox types if the client has not explicitly
+ * called tegra_hsp_set_sm_type() to indicate the mailbox width.
+ *
+ * @pre the function tegra_hsp_db_init()/tegra_hsp_init() has been called
+ *
+ * @param[in] id HSP instance.
+ * @param[in] sm Shared mailbox index. Range: [0- MAX SM INDEX of the instance]
+ * @param[in] cb callback to be called on an IRQ.
+ * @param[in] data opaque data pointer for the callback.
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_MBOX invalid shared mailbox index
+ * @retval E_HSP_ERR_NO_INTR no HSP interrupt support
+ */
+error_t tegra_hsp_sm_empty_enable(struct tegra_hsp_id *id,
+                                  uint32_t sm,
+                                  tegra_hsp_sm_callback cb,
+                                  void *data);
+
+/**
+ * @brief Disable HSP shared mailbox empty interrupt.
+ *
+ * @jama_func_req_id 10710072
+ *
+ * This function disables the HSP shared mailbox empty interrupt.
+ *
+ * @pre the function tegra_hsp_db_init()/tegra_hsp_init() has been called
+ *
+ * @param[in] id HSP instance.
+ * @param[in] sm Shared mailbox index. Range: [0- MAX SM INDEX of the instance]
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_MBOX invalid shared mailbox index
+ * @retval E_HSP_ERR_NO_INTR no HSP interrupt support
+ */
+error_t tegra_hsp_sm_empty_disable(struct tegra_hsp_id *id,
+                                   uint32_t sm);
+
+/**
+ * @brief write to the HSP shared mailbox register with TAG bit
+ *
+ * @jama_func_req_id 10708650
+ *
+ * This function writes the mailbox register with the specified value in
+ * the data field and sets the TAG bit.
+ *
+ * @param[in] id HSP instance.
+ * @param[in] sm Shared mailbox index. Range: [0- MAX SM INDEX of the instance]
+ * @param[in] value value to be written to the data field.
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_MBOX invalid shared mailbox index
+ * @retval E_HSP_ERR_INVALID_DATA if 0xDEAD1001 is written due to HW bug 200395605
+ */
+error_t tegra_hsp_sm_produce(const struct tegra_hsp_id *id,
+                             uint32_t sm,
+                             uint32_t value);
+
+/**
+ * @brief read the HSP shared mailbox by clearing the contents
+ *
+ * @jama_func_req_id 10708695
+ *
+ * This function returns the data field of the shared mailbox register
+ * by clearing the contents of it.
+ *
+ * @param[in] id HSP instance.
+ * @param[in] sm Shared mailbox index. Range: [0- MAX SM INDEX of the instance]
+ * @param[in] data pointer to where the mailbox data field is written to.
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_MBOX invalid shared mailbox index
+ * @retval E_HSP_ERR_EMPTY_MBOX mailbox tag field is empty
+ */
+error_t tegra_hsp_sm_consume(const struct tegra_hsp_id *id,
+                             uint32_t sm,
+                             uint32_t *data);
+
+/**
+ * @brief read the HSP shared mailbox without clearing it
+ *
+ * @jama_func_req_id 10709247
+ *
+ * this function fetches the data field of the mailbox register
+ * without modifying its contents.
+ *
+ * @param[in] id HSP instance.
+ * @param[in] sm Shared mailbox index. Range: [0- MAX SM INDEX of the instance]
+ * @param[in] data pointer to where the mailbox data field is written to.
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_MBOX invalid shared mailbox index
+ * @retval E_HSP_ERR_EMPTY_MBOX mailbox tag field is empty
+ */
+error_t tegra_hsp_sm_peek(const struct tegra_hsp_id *id,
+                          uint32_t sm,
+                          uint32_t *data);
+
+/**
+ * @brief clear contents of the shared mailbox register
+ *
+ * @jama_func_req_id 10709412
+ *
+ * This function clears the contents of the shared mailbox register.
+ *
+ * @param[in] id HSP instance.
+ * @param[in] sm Shared mailbox index. Range: [0- MAX SM INDEX of the instance]
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_MBOX invalid shared mailbox index
+ */
+error_t tegra_hsp_sm_vacate(const struct tegra_hsp_id *id,
+                            uint32_t sm);
+
+/**
+ * @brief 128-bit shared mailbox irq handler
+ *
+ * @jama_func_req_id 10709412
+ *
+ * This function serves as the 128-bit shared mailbox irq handler and is
+ * called from the main HSP irq handler.
+ *
+ * @param[in] id   HSP instance.
+ * @param[in] sm   Shared mailbox index. Range: [0- MAX SM INDEX of the instance]
+ *
+ * @return none
+ */
+void tegra_hsp_sm128_irq_handler(const struct tegra_hsp_id *id,
+                                 uint32_t sm);
+
+/**
+ * @brief check if mailbox is empty or not
+ *
+ * @jama_func_req_id 10709223
+ *
+ * This function indicates whether the mailbox is empty or not.
+ *
+ * @param[in] id HSP instance.
+ * @param[in] sm Shared mailbox index to which data has to be written.
+ *            Range: [0- MAX SM INDEX of the instance]
+ *
+ * @retval True indicates that the mailbox is empty
+ * @retval False indicates that the mailbox is not empty
+ */
+bool tegra_hsp_sm_is_empty(const struct tegra_hsp_id *id,
+                           uint32_t sm);
+
+/**
+ * @brief read the contents of the shared semaphore register
+ *
+ * @jama_func_req_id 10701256
+ *
+ * This function returns the current value of the shared semaphore register.
+ *
+ * @pre the function tegra_hsp_db_init()/tegra_hsp_init() has been called
+ *
+ * @param[in] id HSP instance.
+ * @param[in] sm Shared semaphore index to which data has to be written.
+ *            Range: [0- MAX SS INDEX of the instance]
+ * @param[in] value A pointer to where the read value should be returned in.
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_SHRD_SMPHR invalid shared semaphore index
+ */
+error_t tegra_hsp_ss_read(const struct tegra_hsp_id *id,
+                          uint32_t index,
+                          uint32_t *value);
+
+/**
+ * @brief set specific bits in a shared semaphore register
+ *
+ * @jama_func_req_id 10701259
+ *
+ * This function sets the bits specified by the data parameter in
+ * the shared semaphore.
+ *
+ * @pre the function tegra_hsp_db_init()/tegra_hsp_init() has been called
+ *
+ * @param[in] id HSP instance.
+ * @param[in] sm Shared semaphore index to which data has to be written.
+ *            Range: [0- MAX SS INDEX of the instance]
+ * @param[in] data Specify the bits to be set in the semaphore.
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_SHRD_SMPHR invalid shared semaphore index
+ */
+error_t tegra_hsp_ss_set(const struct tegra_hsp_id *id,
+                         uint32_t index,
+                         uint32_t data);
+
+/**
+ * @brief clear specific bits in a shared semaphore register
+ *
+ * @jama_func_req_id 10707267
+ *
+ * This function clears the bits specified by the data parameter in
+ * the shared semaphore register.
+ *
+ * @pre the function tegra_hsp_db_init()/tegra_hsp_init() has been called
+ *
+ * @param[in] id HSP instance.
+ * @param[in] sm Shared semaphore index to which data has to be written.
+ *            Range: [0- MAX SS INDEX of the instance]
+ * @param[in] data Specify the bits to be cleared in the semaphore.
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_SHRD_SMPHR invalid shared semaphore index
+ */
+error_t tegra_hsp_ss_clear(const struct tegra_hsp_id *id,
+                           uint32_t index,
+                           uint32_t data);
+
+/**
+ * @brief Return number of shared mailboxes supported by hardware.
+ *
+ * @jama_func_req_id 12999380
+ *
+ * @param[in] id    Pointer to hardware interface descriptor
+ *
+ * @return Number of shared mailboxes.
+ *
+ * @note An uninitialized @a id is accepted.
+ */
+uint32_t tegra_hsp_sm_count(const struct tegra_hsp_id *id);
+
+/**
+ * @brief Return number of shared semaphores supported by hardware.
+ *
+ * @jama_func_req_id 12999420
+ *
+ * @param[in] id    Pointer to hardware interface descriptor
+ *
+ * @return Number of shared semaphores.
+ *
+ * @note An uninitialized @a id is accepted.
+ */
+uint32_t tegra_hsp_ss_count(const struct tegra_hsp_id *id);
+
+/**
+ * @brief Return number of doorbells supported by hardware.
+ *
+ * @jama_func_req_id 12999432
+ *
+ * @param[in] id    Pointer to hardware interface descriptor
+ *
+ * @return Number of doorbells.
+ *
+ * @note An uninitialized @a id is accepted.
+ */
+uint32_t tegra_hsp_db_count(const struct tegra_hsp_id *id);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/hsp/sections-hsp.h b/spe-freertos-bsp/fsp/source/include/hsp/sections-hsp.h
new file mode 100644
index 0000000..569d1e3
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/hsp/sections-hsp.h
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef HSP__SECTIONS_HSP_H
+#define HSP__SECTIONS_HSP_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_HSP_DATA           SECTION_BUILDER(hsp,                    data)
+#define SECTION_NAME_HSP_RODATA         SECTION_BUILDER(hsp,                    rodata)
+#define SECTION_NAME_HSP_TEXT           SECTION_BUILDER(hsp,                    text)
+#define SECTION_NAME_HSP_INIT_DATA      SECTION_BUILDER(init.hsp,               data)
+#define SECTION_NAME_HSP_INIT_TEXT      SECTION_BUILDER(init.hsp,               text)
+
+#define SECTION_STR_HSP_TEXT            STR(SECTION_NAME_HSP_TEXT)
+#define SECTION_STR_HSP_RODATA          STR(SECTION_NAME_HSP_RODATA)
+#define SECTION_STR_HSP_DATA            STR(SECTION_NAME_HSP_DATA)
+#define SECTION_STR_HSP_INIT_TEXT       STR(SECTION_NAME_HSP_INIT_TEXT)
+#define SECTION_STR_HSP_INIT_DATA       STR(SECTION_NAME_HSP_INIT_DATA)
+
+#define SECTION_HSP_TEXT                SECTION(SECTION_STR_HSP_TEXT)
+#define SECTION_HSP_RODATA              SECTION(SECTION_STR_HSP_RODATA)
+#define SECTION_HSP_DATA                SECTION(SECTION_STR_HSP_DATA)
+#define SECTION_HSP_INIT_TEXT           SECTION(SECTION_STR_HSP_INIT_TEXT)
+#define SECTION_HSP_INIT_DATA           SECTION(SECTION_STR_HSP_INIT_DATA)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/i2c/i2c-async.h b/spe-freertos-bsp/fsp/source/include/i2c/i2c-async.h
new file mode 100644
index 0000000..90eb26d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/i2c/i2c-async.h
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef I2C__I2C_ASYNC_H
+#define I2C__I2C_ASYNC_H
+#define FSP__I2C__I2C_ASYNC_H                                 1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/** @file i2c-async.h */
+
+/**
+ * @brief Start the Asynchronous i2c transfer
+ *
+ * Start an i2c transfer and return the control to the caller. Once the i2c
+ * controller initiates the transfer, tegra_i2c_irq_handler() handles the rest
+ * of the transfer and calls the callback function provided as input to this API.
+ * The current i2c async transfers support only read or write.
+ * Multiple/Mixed reads and writes is not supported.
+ * Imp - i2c_start_async_xfer enables the clocks for the i2c xfer. It is FW's
+ * responsibility to call i2c_finish_async_xfer to disable the clocks. The unwanted
+ * power drawn if i2c_finish_async_xfer is not called is not in the scope of this API.
+ *
+ * @pre The function i2c_controller_init() must be called before this function.
+ * Else, hi2c->hwops structure is not initialized and api returns
+ * E_INVALID_OPS.
+ *
+ * @param[in] hi2c          Pointer to I2C handle which is returned from
+ *                          i2c_controller_init().
+ * @param[in] msgs          Pointer to I2C messages containing the list of
+ *                          message to be transferred.
+ * @param[in] num_msgs      Number of messages in the msgs parameter.
+ * @param[in] client_data   Pointer to client-specific data
+ * @param[in] async_cb      Callback pointer to be called when xfer is completed.
+ * @retval E_SUCCESS        I2C transfer initiated successfully.
+ * @retval E_INVALID_PARAM  Invalid parameter is passed to the function. <br>
+ *                          T194 - allowed size of transfer is 500 Bytes. <br>
+ *                          T234 - allowed size of transfer is 65535 Bytes.
+ * @retval carry_return     Returns error returned by appfw_mutex_acquire().
+ * @retval E_INVALID_OPS    Invalid i2c_hw_ops::start_async_xfer is assigned in
+ *                          tegra handle.
+ * @retval carry_return     Returns error returned by
+ *                          i2c_hw_ops::start_async_xfer function.
+ * @retval carry_return     Returns error returned by appfw_mutex_release().
+ */
+error_t i2c_start_async_xfer(const struct i2c_handle *hi2c,
+                                struct i2c_xfer_msg *msgs, uint32_t num_msgs,
+                                void *client_data, i2c_async_callback async_cb);
+
+/**
+ * @brief Finish the Asynchronous i2c transfer
+ *
+ * FW calls this API to complete the transaction. In case the transfer returns error,
+ * the api handles error handling and disables the clocks. In case of successful
+ * transfers, only the clocks are disabled.
+ * @pre The function i2c_controller_init() must be called before this function.
+ * Else, hi2c->hwops structure is not initialized and api returns
+ * E_INVALID_OPS.
+ *
+ * @pre The function i2c_controller_init() must be called before this function.
+ * Else, hi2c->hwops structure is not initialized and api returns
+ * E_INVALID_OPS.
+ *
+ * @param[in] hi2c          Pointer to I2C handle which is returned from
+ *                          i2c_controller_init().
+ * @param[in] xfer_ret      Return value from the i2c transfer.
+ * @retval E_SUCCESS        I2C transfer completed successfully.
+ * @retval E_INVALID_OPS    Invalid i2c_hw_ops::finish_async_xfer is assigned in
+ *                          tegra handle.
+ * @retval carry_return     Returns error returned by
+ *                          i2c_hw_ops::finish_async_xfer function..
+ * @retval carry_return     Returns error returned by appfw_mutex_release().
+ */
+error_t i2c_finish_async_xfer(const struct i2c_handle *hi2c, error_t xfer_ret);
+
+/**
+ * @brief Get the state of I2C transfer.
+ *
+ * Return I2C transfer status. Status variables defined at "I2C Xfer status".
+ *
+ * @pre The function i2c_controller_init() must be called before this function.
+ * Else, hi2c->hwops structure is not initialized and api returns
+ * E_INVALID_OPS.
+ *
+ * @param[in] hi2c          Pointer to I2C handle which is returned from
+ *                          i2c_controller_init().
+ * @param[out] state        refer "I2C HW xfer status" macros for the return values.
+ * @param[out] msgs_xfered  Number of msgs transferred.
+ * @retval E_INVALID_PARAM  Invalid parameter is passed to the function.
+ * @retval carry_return     Returns error returned by tegra_i2c_get_xfer_state().
+ * @retval E_SUCCESS        Transfer status is successfully read.
+ */
+error_t i2c_get_xfer_state(const struct i2c_handle *hi2c, uint32_t *state,
+                            uint32_t *msgs_xfered);
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/i2c/i2c-config.h b/spe-freertos-bsp/fsp/source/include/i2c/i2c-config.h
new file mode 100644
index 0000000..7aea841
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/i2c/i2c-config.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef I2C__I2C_CONFIG_H
+#define I2C__I2C_CONFIG_H
+#define FSP__I2C__I2C_CONFIG_H                          1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/** @file i2c-config.h */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+
+/**
+ * @defgroup I2C_SUPPORTED_CLKS Clock rate macros
+ * @brief Defines for clock rates corresponding to i2c modes
+ * @{
+ */
+/** Standard Mode */
+#define I2C_CLK_RATE_SM                 100000U
+/** Fast Mode */
+#define I2C_CLK_RATE_FM                 400000U
+/** Fast Mode + */
+#define I2C_CLK_RATE_FMPLUS             1000000U
+/** High Speed Mode */
+#define I2C_CLK_RATE_HS                 3400000U
+/** @} */
+
+// IWYU pragma: no_forward_declare i2c_xfer_msg
+struct i2c_handle;
+struct i2c_xfer_msg;
+struct i2c_config_data;
+
+#ifdef I2C_ASYNC_XFER
+/**
+ * Define callback function type for transfer completion.
+ */
+typedef void (*i2c_async_callback)(void *i2c_client_data,
+                error_t xfer_ret);
+#endif
+/**
+ * @struct i2c_config_data
+ * @brief I2C controller and bus configuration data.
+ *
+ * @{
+ */
+struct i2c_config_data
+{
+/**
+ * Controller clock rate in Hz. <br>
+ *  Valid range - <100000, 4294967295>
+ */
+    uint32_t ctrl_clk_rate;
+/**
+ * Bus clock rate in Hz. <br>
+ *  Standard Mode  - 100000 <br>
+ *  Fast Mode      - 400000 <br>
+ *  Fast Mode Plus - 1000000
+ */
+    uint32_t bus_clk_rate;
+#ifdef CUSTOM_TIMING_PARAMS
+/**
+ * Interface timing prod setting parameter in us. <br>
+ *  Valid ranges: <br>
+ *  Standard Mode  - <4, 4294967295> <br>
+ *  Fast Mode      - <0, 4294967295> <br>
+ *  Fast Mode Plus - <0, 4294967295>
+ */
+    uint32_t thigh;
+/**
+ * Interface timing prod setting parameter in us. <br>
+ *  Valid Ranges: <br>
+ *  Standard Mode  - <4, 4294967295> <br>
+ *  Fast Mode      - <0, 4294967295> <br>
+ *  Fast Mode Plus - <0, 4294967295>
+ */
+    uint32_t tlow;
+#endif
+/**
+ * High speed master code. <br>
+ *  Valid range - <0, 4294967295>
+ */
+    uint32_t hs_master_code;
+};
+/** @} */
+
+/**
+ * @struct i2c_handle
+ * @brief Contains all relevant data for an i2c controller.
+ *
+ * @{
+ */
+struct i2c_handle
+{
+/** ID of the controller. */
+    uint32_t ctrl_id;
+/** Function pointers for HW operations */
+    struct i2c_hw_ops *hw_ops;
+/** Configuration data specific to the HW */
+    struct i2c_tegra_handle *hi2c_tegra;
+/** State variable for pre-init sequence */
+    bool pre_init_done;
+/**
+ * State of controller <br>
+ *  Enabled - True <br>
+ *  Disabled - False
+ */
+    bool enabled;
+};
+/** @} */
+
+/**
+ * @struct i2c_xfer_msg
+ * @brief I2C transfer message structure contains the message information -
+ * slave address, transfer flags, message data buffer and message length.
+ *
+ * @{
+ */
+struct i2c_xfer_msg
+{
+/** Slave address. It can be 7-bit or 10-bit address. */
+    uint16_t dev_addr;
+/**
+ * Transfer flags. Multiple transfer flags can be combined with OR
+ * operation. Check - SW Defined I2C Transfer flags section.
+ */
+    uint16_t xfer_flags;
+/**
+ * Length of the message. <br>
+ * Valid range - <1, 512>
+ */
+    uint16_t buf_len;
+/** Pointer to read message buffer. */
+    uint8_t *prbuf;
+/** Pointer to write message buffer. */
+    const uint8_t *pwbuf;
+};
+/** @} */
+
+#endif        /* FSP_I2C_I2C_CONFIG_H */
diff --git a/spe-freertos-bsp/fsp/source/include/i2c/i2c-errors.h b/spe-freertos-bsp/fsp/source/include/i2c/i2c-errors.h
new file mode 100644
index 0000000..2a63cbd
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/i2c/i2c-errors.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef I2C__I2C_ERRORS_H
+#define I2C__I2C_ERRORS_H
+#define FSP__I2C__I2C_ERRORS_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>	// IWYU pragma: export
+                                // IWYU pragma: no_include "base/module-id.h"
+#include <misc/macros.h>        // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/** @file i2c-errors.h */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+#endif
+
+/**
+ * @defgroup I2C_ERRORS Error IDs for I2C specific failures
+ *
+ * @brief Defines I2C unit specific errors.
+ * @{
+ */
+/** Arbitration error happened during data transfer. */
+#define E_I2C_ARB_LOST                   MODULE_ERROR(I2C, 1UL)
+/** Slave device has not acknowledged the transfer. */
+#define E_I2C_NACK                       MODULE_ERROR(I2C, 2UL)
+/** IO error happened during I2C function execution. */
+#define E_I2C_IO                         MODULE_ERROR(I2C, 3UL)
+/** HW specific operations are invalid. */
+#define E_I2C_INVALID_OPS                MODULE_ERROR(I2C, 4UL)
+/** RX Fifo underflow during a transaction. */
+#define E_I2C_RX_FIFO_UNDERFLOW          MODULE_ERROR(I2C, 5UL)
+/** TX Fifo overflow during a transaction. */
+#define E_I2C_TX_FIFO_OVERFLOW           MODULE_ERROR(I2C, 6UL)
+/** msg complete signal failed. */
+#define E_I2C_EVENT_SIGNAL_FAIL          MODULE_ERROR(I2C, 7UL)
+/** I2C SCL HW bus line is busy. */
+#define E_I2C_SCL_BUSY                   MODULE_ERROR(I2C, 8UL)
+/** I2C SDA HW bus line is busy. */
+#define E_I2C_SDA_BUSY                   MODULE_ERROR(I2C, 9UL)
+/** I2C HW bus line is busy. Transaction in progress. */
+#define E_I2C_BUS_BUSY                   MODULE_ERROR(I2C, 10UL)
+/** Stale data present in FIFOs */
+#define E_I2C_FIFO_STATUS                MODULE_ERROR(I2C, 11UL)
+/** Stale interrupt from previous transfer */
+#define E_I2C_STALE_INT                  MODULE_ERROR(I2C, 12UL)
+/** Transfer complete IRQ before actual data transfer */
+#define E_I2C_XFER_COMPLETE              MODULE_ERROR(I2C, 13UL)
+/** SW mismatch in data length and data buffer */
+#define E_I2C_RX_FIFO_ERROR              MODULE_ERROR(I2C, 14UL)
+/** @} */
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/i2c/i2c-hw-ops.h b/spe-freertos-bsp/fsp/source/include/i2c/i2c-hw-ops.h
new file mode 100644
index 0000000..de0948c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/i2c/i2c-hw-ops.h
@@ -0,0 +1,263 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef I2C__I2C_HW_OPS_H
+#define I2C__I2C_HW_OPS_H
+#define FSP__I2C__I2C_HW_OPS_H                          1
+
+/* Compiler headers */
+#include <stdint.h>                    // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>            // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>       // for error_t, FSP__ERROR__COMMON_ERRORS_H
+#include <misc/macros.h>               // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <i2c/i2c-tegra.h>             // for i2c_tegra_handle, FSP__I2C__I2C_TEGRA_H
+
+/** @file i2c-hw-ops.h */
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_TEGRA_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
+
+/**
+ * @defgroup I2C_HW_OPS_TYPEDEFS Typedefs for i2c hw functions.
+ * @{
+ */
+#ifdef I2C_ASYNC_XFER
+/**
+ * @brief Start async data transfer over the I2C bus.
+ *
+ * Function pointer to the function which implements the data transfer over the
+ * bus asynchronous. The data to be transfer is passed as a parameter to this
+ * function.
+ *
+ * @pre tegra_i2c_init() must be called before calling this function. Else,
+ * hwops structure is not initialized and api returns E_INVALID_OPS.
+ *
+ * @param[in] hi2c_tegra    Pointer to the HW I2C handle which is returned from
+ *                          tegra_i2c_init().
+ * @param[in] msgs          Pointer to I2C messages containing the list of
+ *                          messages to be transferred.
+ * @param[in] num_msgs      Number of messages in the msgs parameter.
+ * @param[in] client_data   Client data to be passed for the callback function.
+ * @param[in] async_cb      Callback function to be called when xfer is complete.
+ * @retval E_SUCCESS        Data transfer on the bus is successfully completed.
+ * @retval E_INVALID_STATE  Data transfer failed as bus is in suspended state.
+ * @retval carry_return     Return value from appfw_clk_enable() in port layer.
+ * @retval E_INVALID_PARAM  Invalid parameter is passed to the function.
+ * @retval E_I2C_IO         IO error happened during data transfer.
+ */
+typedef error_t (*i2c_hw_start_async_xfer)(struct i2c_tegra_handle *hi2c,
+                               struct i2c_xfer_msg *msgs,
+                               uint32_t num_msgs, void *client_data,
+                               i2c_async_callback async_cb);
+
+/**
+ * @brief Finish async data transfer over the I2C bus.
+ *
+ * Function pointer to the function which completes the data transfer over the
+ * bus. The return value provided by callback pointer is passed as input to
+ * current API.
+ *
+ * @pre tegra_i2c_init() must be called before calling this function. Else,
+ * hwops structure is not initialized and api returns E_INVALID_OPS. +
+ * i2c_hw_start_async_xfer should be called and the return value passed via the
+ * callback pointer should be passed as input to current API.
+ *
+ * @param[in] hi2c_tegra    Pointer to the HW I2C handle which is returned from
+ *                          tegra_i2c_init().
+ * @param[in] xfer_ret      Return value provided by the async_cb callback
+ *                          function.
+ * @retval E_SUCCESS        Data transfer on the bus is successfully completed.
+ * @retval E_INVALID_STATE  Data transfer failed as bus is in suspended state.
+ * @retval carry_return     Return value from appfw_clk_enable() in port layer.
+ * @retval carry_return     Return value from appfw_clk_reset_pulse() in port layer.
+ * @retval carry_return     Return value from appfw_configure_ctrl_clk_rate() in
+ * @retval E_INVALID_PARAM  Invalid parameter is passed to the function.
+ * @retval E_I2C_IO         IO error happened during data transfer.
+ */
+typedef error_t (*i2c_hw_finish_async_xfer)(
+                               const struct i2c_tegra_handle *hi2c_tegra,
+                               error_t xfer_ret);
+#endif
+
+/**
+ * @typedef i2c_hw_xfer
+ * @brief Do data transfer over the I2C bus.
+ *
+ * Function pointer to the function which implements the data transfer over the
+ * bus. The data to be transfer is passed as a parameter to this function.
+ *
+ * @pre tegra_i2c_init() must be called before calling this function. Else,
+ * hwops structure is not initialized and api returns E_INVALID_OPS.
+ *
+ * @param[in] hi2c_tegra    Pointer to the HW I2C handle which is returned from
+ *                          tegra_i2c_init().
+ * @param[in] msgs          Pointer to I2C messages containing the list of
+ *                          messages to be transferred.
+ * @param[in] num_msgs      Number of messages in the msgs parameter.
+ * @param[in] timeout       Maximum time to be allow to complete the transfer in
+ *                          microseconds.
+ *                          If data transfer is not completed in this stipulated
+ *                          time, data transfer is aborted and returned to the
+ *                          caller as E_TIMEOUT. If client can wait forever, 0
+ *                          is to be passed.
+ * @retval E_SUCCESS        Data transfer on the bus is successfully completed.
+ * @retval E_INVALID_STATE  Data transfer failed as bus is in suspended state.
+ * @retval carry_return     Return value from appfw_clk_enable() in port layer.
+ * @retval carry_return     Return value from appfw_clk_reset_pulse() in port layer.
+ * @retval carry_return     Return value from appfw_configure_ctrl_clk_rate() in
+ *                          port layer.
+ * @retval E_INVALID_PARAM  Invalid parameter is passed to the function. <br>
+ *                          T194 - allowed size of transfer is 125 words.
+ * @retval E_TIMEOUT        Possible reasons: <br>
+ *                          * Data transfer is not completed in given time. <br>
+ *                          * Flush FIFOs failed due to timeout. <br>
+ *                          * Failed to load config register. <br>
+ *                          Transfer is aborted. In this case, the function
+ *                          cleans the residuals FIFOs and gets ready for next
+ *                          transfer.
+ * @retval E_I2C_ARB_LOST   Arbitration error happened during data transfer on
+ *                          bus and transfer aborted.
+ * @retval E_I2C_NACK       Device has not acknowledged the transfer.
+ * @retval E_I2C_IO         IO error happened during data transfer.
+ * @retval E_I2C_TX_FIFO_OVERFLOW HW Transfer fifo overflow during the transfer.
+ * @retval E_I2C_RX_FIFO_UNDERFLOW HW Receive fifo underflow during the transfer.
+ * @retval carry_return     Return value from appfw_clk_disable() in port layer.
+ */
+typedef error_t (*i2c_hw_xfer)(struct i2c_tegra_handle *hi2c_tegra,
+                               struct i2c_xfer_msg *msgs,
+                               uint32_t num_msgs, uint32_t timeout);
+
+/**
+ * @typedef i2c_hw_suspend
+ * @brief Suspend the I2C bus and controller.
+ *
+ * Suspend the I2C bus and controller. After this call, no data transfer is
+ * possible on the bus until it is resumed by calling i2c_hw_resume().
+ *
+ * @pre tegra_i2c_init() must be called before calling this function. Else,
+ * hwops structure is not initialized and api returns E_INVALID_OPS.
+ *
+ * @param[in] hi2c_tegra    Pointer to HW I2C handle which is returned from
+ *                          tegra_i2c_init().
+ * @retval E_SUCCESS        Bus and controller are successfully suspended for
+ *                          any further transfers.
+ * @retval E_INVALID_PARAM  Invalid parameter is passed to the function.
+ * @retval E_INVALID_STATE  Bus is already in the suspended state.
+ * @retval E_I2C_IO         IO error happened during bus suspend.
+ */
+typedef error_t (*i2c_hw_suspend)(struct i2c_tegra_handle *hi2c_tegra);
+
+/**
+ * @typedef i2c_hw_resume
+ * @brief Resume the I2C bus and controller.
+ *
+ * Resume the I2C bus and controller. After this call, the bus is resumed for
+ * new data transfer which was suspended after call i2c_hw_suspend().
+ *
+ * @pre The function tegra_i2c_init() must be called before this function. Else,
+ * hwops structure is not initialized and api returns E_INVALID_OPS. Also the
+ * function i2c_hw_suspend() must be called for the bus to be in suspended state.
+ *
+ * @param[in] hi2c_hw       Pointer to I2C handle which is returned from
+ *                          tegra_i2c_init().
+ * @retval E_SUCCESS        Bus and controller are successfully resumed for
+ *                          further transfers.
+ * @retval E_INVALID_PARAM  Invalid handle is passed to the function.
+ * @retval E_INVALID_STATE  Bus is not in suspended state and trying to resume.
+ * @retval E_I2C_IO         IO error happened during bus resume.
+ */
+typedef error_t (*i2c_hw_resume)(struct i2c_tegra_handle *hi2c_tegra);
+
+/**
+ * @typedef i2c_get_bus_status
+ * @brief Get the state of I2C bus HW.
+ *
+ * Return if the SCL, SDA or BUS is busy or not.
+ *
+ * @pre tegra_i2c_init() must be called before calling this function. Else,
+ * hwops structure is not initialized and api returns E_INVALID_OPS.
+ *
+ * @param[in] hi2c_tegra    Pointer to HW I2C handle which is returned from
+ *                          tegra_i2c_init().
+ * @param[out] status       refer "I2C HW bus status" macros for the return values.
+ * @retval E_SUCCESS        Bus HW status is successfully read.
+ * @retval E_INVALID_PARAM  Invalid parameter is passed to the function. <br>
+ *                          T19x - allowed size of transfer is 500 bytes. <br>
+ *                          T23x - allowed size of transfer is 65535 bytes.
+ * @retval E_INVALID_OPS    Invalid resume hw_ops is assigned in tegra handle.
+ */
+typedef error_t (*i2c_get_bus_status)(const struct i2c_tegra_handle *hi2c_tegra,
+                        uint32_t *state);
+/** @} */
+
+/**
+ * @struct i2c_hw_ops
+ * @brief Structure for hw specific functions.
+ *
+ * This structure contains the function pointers for HW specific functions. The
+ * functions are implemented in HW specific I2C driver and the APIs are exported
+ * via this structure. The client of this driver needs to use the HW ops for the
+ * required functionalities.
+ *
+ * @{
+ */
+struct i2c_hw_ops
+{
+/** Function pointer to do data transfer on I2C bus. */
+    i2c_hw_xfer            xfer;
+#ifdef I2C_ASYNC_XFER
+/** Function pointer to start data transfer asynchronously on I2C bus. */
+    i2c_hw_start_async_xfer    start_async_xfer;
+/** Function pointer to stop data transfer asynchronously on I2C bus. */
+    i2c_hw_finish_async_xfer   finish_async_xfer;
+#endif
+/**
+ * Function pointer to suspend the controller and bus. The HW driver calls this
+ * function to suspend the controller and stop further transfers until it is
+ * resumed.
+ */
+    i2c_hw_suspend         suspend;
+/**
+ * Function pointer to resume the controller and bus. The HW driver calls this
+ * function to resume the controller and start data transfers on the bus.
+ */
+    i2c_hw_resume          resume;
+    i2c_get_bus_status     get_bus_state;
+};
+/** @} */
+
+#endif      /* I2C__I2C_HW_OPS_H */
diff --git a/spe-freertos-bsp/fsp/source/include/i2c/i2c-tegra-async.h b/spe-freertos-bsp/fsp/source/include/i2c/i2c-tegra-async.h
new file mode 100644
index 0000000..d46e76a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/i2c/i2c-tegra-async.h
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef I2C__I2C_TEGRA_ASYNC_H
+#define I2C__I2C_TEGRA_ASYNC_H
+#define FSP__I2C__I2C_TEGRA_ASYNC_H                           1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/** @file i2c-tegra-async.h */
+
+/* Internal functions between i2c-tegra.c and i2c-tegra-async.c */
+/**
+ * @addtogroup I2C_TEGRA_INTERNAL_APIS
+ * @{
+ */
+/**
+ * @brief Enable clocks for the I2C controller.
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ * @retval E_INVALID_STATE  Controller in suspended state.
+ * @retval carry_return     Returns error returned by appfw_clk_enable()
+ */
+error_t tegra_i2c_acquire(const struct i2c_tegra_handle *hi2c_tegra);
+
+/**
+ * @brief Disable clocks for the I2C controller.
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ * @retval carry_return     Return error returned by appfw_clk_disable()
+ */
+error_t tegra_i2c_release(const struct i2c_tegra_handle *hi2c_tegra);
+
+/**
+ * @brief Initialize the HW controller.
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ * @retval carry_return     Return error returned by appfw_clk_reset_pulse()
+ * @retval carry_return     Return error returned by tegra_i2c_clock_conf()
+ * @retval carry_return     Return error returned by tegra_i2c_conf()
+ */
+error_t tegra_i2c_hw_init(const struct i2c_tegra_handle *hi2c_tegra);
+
+/**
+ * @brief Checks if the input msgs for transfer are valid.
+ *
+ * @param[in] msgs          messages requested to be transferred.
+ * @param[in] num           number of messages being transferred.
+ * @retval E_SUCCESS        messages are valid for being transferred.
+ * @retval E_INVALID_PARAM  Invalid message parameters
+ */
+error_t tegra_i2c_validate_msgs(const struct i2c_xfer_msg *msgs, uint32_t num);
+
+/**
+ * @brief Transfer a message on the i2c bus.
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ * @param[in] this          current message being transferred.
+ * @param[in] next          next message to be transferred.
+ * @retval 64_bit           time for the message transfer to be initiated on the HW bus.
+ */
+uint64_t tegra_i2c_xfer_one_msg(struct i2c_tegra_handle *hi2c_tegra,
+        const struct i2c_xfer_msg *this, const struct i2c_xfer_msg *next);
+
+/**
+ * @brief Check that i2c controller is at expected state before xfer is attempted
+ *
+ * @param[in] hi2c_tegra      i2c_tegra_handle corresponding to the controller.
+ * @retval E_SUCCESS          HW is ready to start transfer.
+ * @retval E_I2C_FIFO_STATUS  FIFOS not empty.
+ * @retval E_I2C_STALE_INT    Pending interrupts from previous transfer.
+ */
+error_t tegra_i2c_check_state(const struct i2c_tegra_handle *hi2c_tegra);
+
+/**
+ * @brief Return i2c transfer state machine variable.
+ *
+ * @param[in] hi2c_tegra      i2c_tegra_handle corresponding to the controller.
+ * @param[out] msgs_xfered    number of messages transferred till now.
+ * @retval 32_bit_value       status value as defined in I2C_XFER_STATUS
+ */
+uint32_t tegra_i2c_get_xfer_state(const struct i2c_tegra_handle *hi2c_tegra,
+                                    uint32_t *msgs_xfered);
+
+/**
+ * @brief Tegra implementation for i2c_start_async_xfer
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ * @param[in] msgs          Pointer to I2C messages containing the list of
+ *                          message to be transferred.
+ * @param[in] num_msgs      Number of messages in the msgs parameter.
+ * @param[in] client_data   Pointer to client-specific data
+ * @param[in] async_xfer_cb Callback pointer to be called when xfer is completed.
+ * @retval E_SUCCESS        I2C transfer initiated successfully.
+ * @retval carry_return     Return error from tegra_i2c_acquire().
+ * @retval carry_return     Return error from tegra_i2c_check_state().
+ * @retval carry_return     Return error from tegra_i2c_validate_msgs().
+ */
+error_t tegra_i2c_start_async_xfer(struct i2c_tegra_handle *hi2c_tegra,
+        struct i2c_xfer_msg *msgs, uint32_t num_msgs,
+        void *client_data, i2c_async_callback async_xfer_cb);
+
+/**
+ * @brief Tegra implementation for i2c_finish_async_xfer
+ *
+ * @param[in] hi2c_tegra    i2c_tegra_handle corresponding to the controller.
+ * @param[in] xfer_ret      Return value from the i2c transfer.
+ * @retval E_SUCCESS        I2C transfer initiated successfully.
+ * @retval carry_return     Return error from tegra_i2c_hw_init().
+ * @retval carry_return     Return error from tegra_i2c_release().
+ */
+error_t tegra_i2c_finish_async_xfer(const struct i2c_tegra_handle *hi2c_tegra,
+        error_t xfer_ret);
+/** @} */
+
+#endif        /* FSP_I2C_I2C_TEGRA_ASYNC_H */
diff --git a/spe-freertos-bsp/fsp/source/include/i2c/i2c-tegra.h b/spe-freertos-bsp/fsp/source/include/i2c/i2c-tegra.h
new file mode 100644
index 0000000..f741815
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/i2c/i2c-tegra.h
@@ -0,0 +1,203 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef I2C__I2C_TEGRA_H
+#define I2C__I2C_TEGRA_H
+#define FSP__I2C__I2C_TEGRA_H                           1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <i2c/i2c-config.h>
+
+/** @file i2c-tegra.h */
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
+
+/**
+ * @defgroup I2C_XFER_FLAGS Flags for I2C transfer
+ * @brief Defines for I2C transfer flags constants.
+ *
+ * @{
+ */
+/** This flag tells that given transfer is read type i.e master reads data from slave. */
+#define I2C_XFER_FLAG_RD                       BIT(0)
+/** This flag tells that slave address is 10-bit address. */
+#define I2C_XFER_FLAG_TEN                      BIT(1)
+/** This flag tells that data transfer happens without repeat start. */
+#define I2C_XFER_FLAG_NOSTART                  BIT(2)
+/** This flag tells that transfer will continue even if there no ACK from slave. */
+#define I2C_XFER_FLAG_IGNORE_NAK               BIT(3)
+/** @} */
+
+#define I2C_PKT_XFER_MAX_BYTES                 500U
+#define I2C_FIFO_MAX_SIZE_W                    128U
+#define I2C_PACKET_HEADER_SIZE_W               3U
+#define WORD_TO_BYTES                          4U
+
+// IWYU pragma: no_forward_declare i2c_hw_ops
+struct i2c_tegra_handle;
+struct i2c_hw_ops;
+
+/**
+ * @struct i2c_tegra_handle
+ * @brief tegra specific controller data
+ *
+ * @{
+ */
+struct i2c_tegra_handle
+{
+/** Controller id */
+    uint32_t ctrl_id;
+/** HW specific data which is considered const throughout the unit. */
+    const struct i2c_hw_handle *hi2c_hw;
+/** Configurable parameters(Clock and HW timing). */
+    const struct i2c_config_data *pi2c_config;
+/** STate variable for pre-init sequence */
+    bool pre_init_done;
+
+    /* used at runtime */
+/** suspended state - True; Resumed - False */
+    bool is_suspended;
+/** initialized state - True; Uninitialized - False */
+    bool is_initialized;
+
+    /* transfer specific data */
+/** messages being transferred */
+    struct i2c_xfer_msg *msgs;
+    uint32_t num_msgs;
+/** bytes remaining to transfer */
+    uint32_t bytes_to_xfer;
+/** Status of the current transfer among -<br>
+ *  I2C_XFER_REQUESTED <br>
+ *  I2C_XFER_STARTED <br>
+ *  I2C_XFER_IN_PROGRESS <br>
+ *  I2C_XFER_COMPLETED
+ */
+    uint32_t xfer_status;
+/** return value from the irq handler */
+    error_t isr_ret;
+/** State variable to decide ending transfer */
+    bool end_xfer;
+/** message index for current message being transferred */
+    uint32_t msg_index;
+/** msg buffer index for read transfer */
+    uint32_t rx_index;
+/** msg buffer index for write transfer */
+    uint32_t tx_index;
+#ifdef I2C_ASYNC_XFER
+    bool is_async_xfer;
+    i2c_async_callback async_xfer_cb;
+    void *client_data;
+#endif
+};
+/** @} */
+
+/**
+ * @brief Initialize Tegra I2C controller OS Resources.
+ *
+ * This function implements the Tegra I2C controller specific OS resources
+ * initialization. This function gets the configuration data from the static
+ * data in i2c-port.c. If config data is null, corresponding error is returned.
+ * Sets pre_init_done to true upon successful pre-init.
+ *
+ * @param[in]  ctrl_id          I2C Controller ID which need to be initialized.
+ *                              The client needs to get the controller ID of
+ *                              required I2C bus from i2c-tegra.c.
+ * @param[out] hi2c_tegra       Pointer of tegra I2C handle structure where
+ *                              tegra specific parameters for an i2c controller
+ *                              are stored.
+ * @retval E_SUCCESS            Initialization of controller is successful
+ * @retval E_INVALID_CONFIG     Null configuration data in i2c-port.c.
+ * @retval E_INVALID_PARAM      Input parameter is invalid.
+ */
+error_t tegra_i2c_pre_init(uint32_t ctrl_id, struct i2c_tegra_handle *hi2c_tegra);
+
+/**
+ * @brief Initialize Tegra I2C controller
+ *
+ * This function implements the Tegra I2C controller specific initialization.
+ * This function gets the configuration data from the static data in i2c-port.c
+ * If config data is null, corresponding error is returned.
+ * Calls tegra_i2c_pre_init internally if pre_init_done not true.
+ *
+ * @param[in]  ctrl_id          I2C Controller ID which need to be initialized.
+ *                              The client needs to get the controller ID of
+ *                              required I2C bus from i2c-tegra.c.
+ * @param[out] hi2c_tegra       Pointer of tegra I2C handle structure where
+ *                              tegra specific parameters for an i2c controller
+ *                              are stored.
+ * @param[out] hw_ops           Pointer to Pointer of structure of I2C HW
+ *                              operations. The HW specific controller driver
+ *                              needs to update this structure. I2C core will
+ *                              use these HW functions to access the bus and
+ *                              configure the controller.
+ * @retval E_SUCCESS            Initialization of controller is successful
+ * @retval E_INVALID_CONFIG     Null configuration data in i2c-port.c.
+ * @retval E_INVALID_PARAM      Input parameter is invalid.
+ * @retval E_TIMEOUT            Possible reasons: <br>
+ *                              * Flush Fifos failed due to timeout. <br>
+ *                              * Failed to load config register.
+ */
+error_t tegra_i2c_init(uint32_t ctrl_id, struct i2c_tegra_handle *hi2c_tegra,
+                   struct i2c_hw_ops **hw_ops);
+
+/**
+ * @brief Interrupt handler for the I2C controller
+ *
+ * This function is used to implement the I2C interrupt handler. This function
+ * is called from the R5 ISR handler when I2C controller raises an interrupt.
+ * In case the FW uses threaded IRQs feature, THREADED_IRQS feature needs to
+ * defined. The FW needs to define the thread supposed to woken in case of the
+ * interrupt.
+ * The I2C controller raises the interrupt for the following reasons:
+ *
+ * - Space in Tx FIFO
+ * - Data available in Rx FIFO
+ * - Current Packet transfer completed.
+ * - All Packet transfer completed.
+ * - All Packets transfer Completed
+ *
+ * @param[in] ctrl_id Controller Id for which the interrupt is raised. This is
+ *                    provided when interrupt is setup.
+ */
+void tegra_i2c_irq_handler(uint32_t ctrl_id);
+
+#endif        /* FSP_I2C_I2C_TEGRA_H */
diff --git a/spe-freertos-bsp/fsp/source/include/i2c/i2c.h b/spe-freertos-bsp/fsp/source/include/i2c/i2c.h
new file mode 100644
index 0000000..7c3fdd5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/i2c/i2c.h
@@ -0,0 +1,426 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef I2C__I2C_H
+#define I2C__I2C_H
+#define FSP__I2C__I2C_H                                 1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <i2c/i2c-config.h>
+
+/* Config based headers */
+#ifdef CONFIG_I2C_ENABLE_PRINTS
+#include <debug/debug-print.h>
+#endif
+
+/** @file i2c.h */
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
+
+#ifdef CONFIG_I2C_ENABLE_PRINTS
+#define i2c_pr_error dbg_printf
+#define i2c_pr_info dbg_printf
+#ifdef CONFIG_I2C_ENABLE_DEBUG
+#define i2c_pr_debug dbg_printf
+#else
+#define i2c_pr_debug(...)
+#endif
+#else
+#define i2c_pr_debug(...)
+#define i2c_pr_info(...)
+#define i2c_pr_error(...)
+#endif
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
+
+/**
+ * @defgroup I2C_XFER_STATUS Macros for transfer status
+ * @brief Defines to interpret the xfer status return from i2c_get_xfer_state api.
+ *
+ * @{
+ */
+/** I2C transfer API invoked. */
+#define I2C_XFER_REQUESTED              BIT(0)
+/** I2C transfer packet header written to FIFO. */
+#define I2C_XFER_STARTED                BIT(1)
+/** I2C transfer interrupt received and being processed. */
+#define I2C_XFER_IN_PROGRESS            BIT(2)
+/** I2C transfer completed. */
+#define I2C_XFER_COMPLETED              BIT(3)
+/** @} */
+
+/**
+ * @defgroup I2C_HW_BUS_STATUS Macros for HW bus status
+ * @brief Defines to interpret the bus status return from i2c_get_bus_state api.
+ *
+ * @{
+ */
+/** Bit representation for I2C SCL is busy. */
+#define I2C_SCL_BUSY                BIT(0)
+/** Bit representation for I2C SDA is busy. */
+#define I2C_SDA_BUSY                BIT(1)
+/** Bit representation for I2C BUS is busy. */
+#define I2C_BUS_BUSY                BIT(2)
+/** parse the return values from i2c_get_bus_state api and return true if SCL is high. */
+#define I2C_IS_SCL_HIGH(status)     ((status & I2C_SCL_BUSY) != 0U)
+/** parse the return values from i2c_get_bus_state api and return true if SDA is high. */
+#define I2C_IS_SDA_HIGH(status)     ((status & I2C_SDA_BUSY) != 0U)
+/** parse the return values from i2c_get_bus_state api and return true if bus is free to use. */
+#define I2C_IS_BUS_FREE(status)     ((status & I2C_BUS_BUSY) != 0U)
+/** @} */
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
+
+/**
+ * @brief Initialize OS resources for I2C controller.
+ *
+ * This function initializes the OS resources i2c driver requires.
+ * Sets pre_init_done to true upon successful pre-init.
+ *
+ * @param[in]  ctrl_id          Controller ID which need to be initialized.
+ * @param[out] hi2c             Pointer to I2C handle structure where I2C
+ *                              handle is saved.
+ * @retval E_SUCCESS            Initialization of controller successfully done.
+ * @retval E_INVALID_PARAM      Input parameter is passed to the function.
+ * @retval E_INVALID_CONFIG     Null configuration data in i2c-port.c.
+ **/
+error_t i2c_controller_pre_init(uint32_t ctrl_id,
+                            struct i2c_handle *hi2c);
+
+/**
+ * @brief Initialize a controller with static configuration and controller ID.
+ *
+ * This function initializes the controller with static bus and controller
+ * configuration and controller ID. The list of controller IDs corresponding to
+ * the available HW controllers are given in soc-common/i2c-defs.h.
+ * Calls i2c_controller_pre_init internally if pre_init_done is not true.
+ *
+ * @param[in]  ctrl_id          Controller ID which need to be initialized.
+ * @param[out] hi2c             Pointer to I2C handle structure where I2C
+ *                              handle is saved.
+ * @retval E_SUCCESS            Initialization of controller successfully done.
+ * @retval E_INVALID_PARAM      Input parameter is passed to the function.
+ * @retval E_I2C_INVALID_OPS    HW specific operation is invalid.
+ * @retval E_INVALID_CONFIG     Null configuration data in i2c-port.c.
+ * @retval E_TIMEOUT            Possible reasons: <br>
+ *                                 * Flush FIFOs failed due to timeout. <br>
+ *                                 * Failed to load config register.
+ **/
+error_t i2c_controller_init(uint32_t ctrl_id,
+                            struct i2c_handle *hi2c);
+
+/**
+ * @brief Write data into the register of slave device.
+ *
+ * Write the data into a register of slave device. If more than one byte is
+ * written then register address is automatically incremented.
+ *
+ * @pre The function i2c_controller_init() must be called before this function.
+ * Else, hi2c->hwops structure is not initialized and api returns
+ * E_INVALID_OPS.
+ *
+ * @param[in] hi2c          Pointer to I2C handle which is returned from
+ *                          i2c_controller_init().
+ * @param[in] slave_address The slave device address to communicate with. This
+ *                          can be 7-bit or 10-bit.
+ * @param[in] reg_address   The register address in the slave device.
+ * @param[in] flags         Transfer flags. Multiple transfer flags can be ORed
+ *                          here.
+ * @param[in] pdata         Pointer to data to written to the slave device.
+ * @param[in] num_data      Number of bytes to be write.
+ * @param[in] timeout       Maximum time to be allow to complete the transfer.
+ *                          Unit of timeout is in Microseconds. <br>
+ *                          If data transfer is not completed in this time then
+ *                          data transfer is aborted and returned to the caller
+ *                          as E_TIMEOUT. If client can wait forever, 0 is to be
+ *                          passed.
+ * @retval E_SUCCESS        Data write into the device is successfully
+ *                          completed.
+ * @retval E_TIMEOUT        Data transfer is not completed in given time and the
+ *                          transfer is aborted. In this case, the function
+ *                          cleans the residual FIFOs and gets ready for the
+ *                          next transfer.
+ * @retval E_INVALID_PARAM  Invalid parameter is passed to the function. <br>
+ *                          T194 - allowed size of transfer is 500 bytes. <br>
+ *                          T234 - allowed size of transfer is 65535 bytes.
+ * @retval carry_return     Return value from appfw_mutex_acquire() in port layer.
+ * @retval carry_return     Return value from i2c_hw_ops::xfer
+ * @retval carry_return     Return value from appfw_mutex_release() in port layer.
+ */
+error_t i2c_reg_write_data(const struct i2c_handle *hi2c, uint16_t slave_address,
+                           uint8_t reg_address, uint16_t flags, uint8_t const *pdata,
+                           uint16_t num_data, uint32_t timeout);
+
+/**
+ * @brief Read data from a register of slave device.
+ *
+ * @pre The function i2c_controller_init() must be called before this function.
+ * Else, hi2c->hwops structure is not initialized and api returns
+ * E_INVALID_OPS.
+ *
+ * Read data from the given register of slave device. If more than one byte is
+ * read then register address is automatically incremented.
+ *
+ * @param[in] hi2c          Pointer to I2C handle which is returned from
+ *                          i2c_controller_init().
+ * @param[in] slave_address The slave device address to communicate with. This
+ *                          can be 7-bit or 10-bit.
+ * @param[in] reg_address   The register address in the slave device.
+ * @param[in] flags         Transfer flags. Multiple transfer flags can be ORed
+ *                          here.
+ * @param[in] pdata         Pointer to data buffer where read data is to be
+ *                          stored.
+ * @param[in] num_data      Number of bytes to be read.
+ * @param[in] timeout       Maximum time to be allow to complete the transfer.
+ *                          Unit of timeout is in Microseconds. <br>
+ *                          If data transfer is not completed in this time then
+ *                          data transfer is aborted and returned to the caller
+ *                          as E_TIMEOUT. If client can wait forever, 0 is to be
+ *                          passed.
+ * @retval E_SUCCESS        Data read into the device is successfully
+ *                          completed.
+ * @retval E_TIMEOUT        Data transfer is not completed in given time and the
+ *                          transfer is aborted. In this case, the function
+ *                          cleans the residual FIFOs and gets ready for the
+ *                          next transfer.
+ * @retval E_INVALID_PARAM  Invalid parameter is passed to the function. <br>
+ *                          T194 - allowed size of transfer is 500 bytes. <br>
+ *                          T234 - allowed size of transfer is 65535 bytes.
+ * @retval carry_return     Return value from appfw_mutex_acquire() in port layer.
+ * @retval carry_return     Return value from i2c_hw_ops::xfer.
+ * @retval carry_return     Return value from appfw_mutex_release() in port layer.
+ */
+error_t i2c_reg_read_data(const struct i2c_handle *hi2c, uint16_t slave_address,
+                          uint8_t reg_address, uint16_t flags, uint8_t *pdata,
+                          uint16_t num_data, uint32_t timeout);
+
+/**
+ * @brief Send the data to I2C bus.
+ *
+ * This function sends the data onto the I2C bus to a slave device.
+ *
+ * @pre The function i2c_controller_init() must be called before this function.
+ * Else, hi2c->hwops structure is not initialized and api returns
+ * E_INVALID_OPS.
+ *
+ * @param[in] hi2c          Pointer to I2C handle which is returned from
+ *                          i2c_controller_init().
+ * @param[in] slave_address The slave device address to communicate with. This
+ *                          can be 7-bit or 10-bit.
+ * @param[in] flags         Transfer flags. Multiple transfer flags can be ORed
+ *                          here.
+ * @param[in] pdata         Pointer to data buffer which need to be sent to the
+ *                          device.
+ * @param[in] num_data      Number of bytes to be sent.
+ * @param[in] timeout       Maximum time to be allow to complete the transfer.
+ *                          Unit of timeout is in Microseconds. <br>
+ *                          If data transfer is not completed in this time then
+ *                          data transfer is aborted and returned to the caller
+ *                          as E_TIMEOUT. If client can wait forever, 0 is to be
+ *                          passed.
+ * @retval E_SUCCESS        Sending of data to the bus is successful.
+ * @retval E_TIMEOUT        Data transfer is not completed in given time and the
+ *                          transfer is aborted. In this case, the function
+ *                          cleans the residual FIFOs and gets ready for the
+ *                          next transfer.
+ * @retval E_INVALID_PARAM  Invalid parameter is passed to the function. <br>
+ *                          T194 - allowed size of transfer is 500 bytes. <br>
+ *                          T234 - allowed size of transfer is 65535 bytes.
+ * @retval carry_return     Return value from appfw_mutex_acquire() in port layer.
+ * @retval carry_return     Return value from i2c_hw_ops::xfer
+ * @retval carry_return     Return value from appfw_mutex_release() in port layer.
+ */
+error_t i2c_send_data(const struct i2c_handle *hi2c, uint16_t slave_address,
+                      uint16_t flags, const uint8_t *pdata, uint32_t num_data,
+                      uint32_t timeout);
+
+/**
+ * @brief Receive data from I2C bus.
+ *
+ * This function reads the data on the I2C bus from a slave device.
+ *
+ * @pre The function i2c_controller_init() must be called before this function.
+ * Else, hi2c->hwops structure is not initialized and api returns
+ * E_INVALID_OPS.
+ *
+ * @param[in] hi2c          Pointer to I2C handle which is returned from
+ *                          i2c_controller_init().
+ * @param[in] slave_address The slave device address to communicate with. This
+ *                          can be 7-bit or 10-bit.
+ * @param[in] flags         Transfer flags. Multiple transfer flags can be ORed
+ *                          here.
+ * @param[in] pdata         Pointer to data buffer where receive data is to be
+ *                          saved.
+ * @param[in] num_data      Number of bytes to be receive.
+ * @param[in] timeout       Maximum time to be allow to complete the transfer.
+ *                          Unit of timeout is in Microseconds. <br>
+ *                          If data transfer is not completed in this time then
+ *                          data transfer is aborted and returned to the caller
+ *                          as E_TIMEOUT. If client can wait forever, 0 is to be
+ *                          passed.
+ * @retval E_SUCCESS        Receiving of data to the bus is successfully
+ *                          completed.
+ * @retval E_TIMEOUT        Data transfer is not completed in given time and the
+ *                          transfer is aborted. In this case, the function
+ *                          cleans the residual FIFOs and gets ready for the
+ *                          next transfer.
+ * @retval E_INVALID_PARAM  Invalid parameter is passed to the function. <br>
+ *                          T194 - allowed size of transfer is 500 bytes. <br>
+ *                          T234 - allowed size of transfer is 65535 bytes.
+ * @retval carry_return     Return value from appfw_mutex_acquire() in port layer.
+ * @retval carry_return     Return value from i2c_hw_ops::xfer.
+ * @retval carry_return     Return value from appfw_mutex_release() in port layer.
+ */
+error_t i2c_receive_data(const struct i2c_handle *hi2c, uint16_t slave_address,
+                         uint16_t flags, uint8_t *pdata, uint32_t num_data,
+                         uint32_t timeout);
+
+/**
+ * @brief Data transfer(read or write or both) over the I2C bus with a slave
+ * device
+ *
+ * This function implements the data transfer, read or write or combination of
+ * both over the I2C bus with a slave device. Data for multiple byte transfer
+ * can be provided as an array of messages. The repeat-start of data transfer is
+ * used between transfers. If flag M_NO_START is provided then start will not be
+ * sent again.
+ *
+ * @pre The function i2c_controller_init() must be called before this function.
+ * Else, hi2c->hwops structure is not initialized and api returns
+ * E_INVALID_OPS.
+ *
+ * @param[in] hi2c          Pointer to I2C handle which is returned from
+ *                          i2c_controller_init().
+ * @param[in] msgs          Pointer to I2C messages containing the list of
+ *                          message to be transferred.
+ * @param[in] num_msgs      Number of messages in the msgs parameter.
+ * @param[in] timeout       Maximum time to be allow to complete the transfer.
+ *                          Unit of timeout is in Microseconds. <br>
+ *                          If data transfer is not completed in this time then
+ *                          data transfer is aborted and returned to the caller
+ *                          as E_TIMEOUT. If client can wait forever, 0 is to be
+ *                          passed.
+ * @retval E_SUCCESS        Data transfer to the bus is successfully completed.
+ * @retval E_TIMEOUT        Data transfer is not completed in given time and the
+ *                          transfer is aborted. In this case, the function
+ *                          cleans the residual FIFOs and gets ready for the
+ *                          next transfer.
+ * @retval E_INVALID_PARAM  Invalid parameter is passed to the function. <br>
+ *                          T194 - allowed size of transfer is 500 bytes. <br>
+ *                          T234 - allowed size of transfer is 65535 bytes.
+ * @retval carry_return     Return value from appfw_mutex_acquire() in port layer.
+ * @retval carry_return     Return value from i2c_hw_ops::xfer.
+ * @retval carry_return     Return value from appfw_mutex_release() in port layer.
+ */
+error_t i2c_do_transfer(const struct i2c_handle *hi2c,
+                        struct i2c_xfer_msg *msgs,
+                        uint32_t num_msgs, uint32_t timeout);
+
+/**
+ * @brief Suspend the I2C bus and controller.
+ *
+ * Suspend the I2C bus and controller. After this call, no data transfer is
+ * possible on the bus until it is resumed by calling i2c_resume().
+ *
+ * @pre The function i2c_controller_init() must be called before this function.
+ * Else, hi2c->hwops structure is not initialized and api returns
+ * E_INVALID_OPS.
+ *
+ * @param[in] hi2c          Pointer to I2C handle which is returned from
+ *                          i2c_controller_init().
+ * @retval E_SUCCESS        Bus and controller are successfully suspended for
+ *                          any further transfers.
+ * @retval E_INVALID_PARAM  Invalid parameter is passed to the function.
+ * @retval E_INVALID_OPS    Invalid i2c_hw_ops::suspend is assigned in tegra handle.
+ * @retval E_INVALID_STATE  Bus is already in the suspended state.
+ * @retval E_I2C_IO         IO error happened during bus suspend.
+ */
+error_t i2c_suspend(const struct i2c_handle *hi2c);
+
+/**
+ * @brief Resume the I2C bus and controller.
+ *
+ * Resume the I2C bus and controller. After this call, the bus(which was
+ * suspended after call i2c_suspend) is resumed for new data transfers.
+ *
+ * @pre The function i2c_controller_init() must be called before this function.
+ * Else, hi2c->hwops structure is not initialized and api returns
+ * E_INVALID_OPS.
+ * Also the function i2c_suspend() must be called for the bus to be in suspended
+ * state.
+ *
+ * @param[in] hi2c          Pointer to I2C handle which is returned from
+ *                          i2c_controller_init().
+ * @retval E_SUCCESS        Bus and controller are successfully resumed for
+ *                          further transfers.
+ * @retval E_INVALID_PARAM  Invalid parameter is passed to the function.
+ * @retval E_INVALID_OPS    Invalid i2c_hw_ops::resume is assigned in tegra handle.
+ * @retval E_INVALID_STATE  Bus is not in suspended state and trying to resume.
+ * @retval E_I2C_IO         IO error happened during bus resume.
+ */
+error_t i2c_resume(const struct i2c_handle *hi2c);
+
+/**
+ * @brief Get the state of I2C bus HW.
+ *
+ * Return if the SCL, SDA or BUS is busy or not.
+ *
+ * @pre The function i2c_controller_init() must be called before this function.
+ * Else, hi2c->hwops structure is not initialized and api returns
+ * E_INVALID_OPS.
+ *
+ * @param[in] hi2c          Pointer to I2C handle which is returned from
+ *                          i2c_controller_init().
+ * @param[out] state        refer "I2C HW bus status" macros for the return values.
+ * @retval E_INVALID_PARAM  Invalid parameter is passed to the function.
+ * @retval E_INVALID_OPS    Invalid i2c_hw_ops::get_bus_state is assigned in tegra handle.
+ * @retval E_SUCCESS        Bus HW status is successfully read.
+ */
+error_t i2c_get_bus_state(const struct i2c_handle *hi2c, uint32_t *state);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/i2c/sections-i2c.h b/spe-freertos-bsp/fsp/source/include/i2c/sections-i2c.h
new file mode 100644
index 0000000..9e51a58
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/i2c/sections-i2c.h
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef I2C__SECTIONS_I2C_H
+#define I2C__SECTIONS_I2C_H
+#define FSP__I2C__SECTIONS_I2C_H                        0
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_I2C_DATA           SECTION_BUILDER(i2c,                    data)
+#define SECTION_NAME_I2C_RODATA         SECTION_BUILDER(i2c,                    rodata)
+#define SECTION_NAME_I2C_TEXT           SECTION_BUILDER(i2c,                    text)
+#define SECTION_NAME_I2C_INIT_DATA      SECTION_BUILDER(init.i2c,               data)
+#define SECTION_NAME_I2C_INIT_TEXT      SECTION_BUILDER(init.i2c,               text)
+
+#define SECTION_STR_I2C_RODATA          STR(SECTION_NAME_I2C_RODATA)
+#define SECTION_STR_I2C_DATA            STR(SECTION_NAME_I2C_DATA)
+#define SECTION_STR_I2C_INIT_DATA       STR(SECTION_NAME_I2C_INIT_DATA)
+#define SECTION_STR_I2C_TEXT            STR(SECTION_NAME_I2C_TEXT)
+#define SECTION_STR_I2C_INIT_TEXT       STR(SECTION_NAME_I2C_INIT_TEXT)
+
+#define SECTION_I2C_RODATA              SECTION(SECTION_STR_I2C_RODATA)
+#define SECTION_I2C_DATA                SECTION(SECTION_STR_I2C_DATA)
+#define SECTION_I2C_INIT_DATA           SECTION(SECTION_STR_I2C_INIT_DATA)
+#define SECTION_I2C_TEXT                SECTION(SECTION_STR_I2C_TEXT)
+#define SECTION_I2C_INIT_TEXT           SECTION(SECTION_STR_I2C_INIT_TEXT)
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/irq/safe-irqs.h b/spe-freertos-bsp/fsp/source/include/irq/safe-irqs.h
new file mode 100644
index 0000000..8f17859
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/irq/safe-irqs.h
@@ -0,0 +1,225 @@
+/*
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+  EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef IRQ__SAFE_IRQS_H
+#define IRQ__SAFE_IRQS_H
+#define FSP__IRQ__SAFE_IRQS_H                                1
+
+/* Compiler headers */
+#include <stdbool.h>
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>  // for error_t
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <vic/tegra-vic.h>        // for irq_context
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__VIC__TEGRA_VIC_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
+
+/** Pointer to irq callback function **/
+typedef void (*irq_callback_fn)(void *context);
+
+/**
+ * @brief Enable an interrupt
+ *
+ * This function enables a device interrupt using IRQ vector number.
+ * The IRQ vector number maps to the tegra interrupt number already known
+ * to the client.
+ *
+ * @pre
+ * - Basic initialization of vectored interrupt controller has been done with ISRs
+ * mapped to the respective valid interrupt sources.
+ *
+ * @param[in] vector IRQ number for the device interrupt
+ *                   [0 - MAX_VIC_INTERRUPT_VECTOR]
+ *
+ * @retval E_SUCCESS             For success.
+ * @retval E_VIC_INVALID_VECTOR  Invalid input vector ID
+ */
+error_t irq_safe_enable(const uint32_t vector);
+
+/**
+ * @brief Disable an interrupt
+ *
+ * This function disables a device interrupt using IRQ vector number.
+ * The IRQ vector number maps to tegra interrupt number already known
+ * to the client
+ *
+ * @pre
+ * - Basic initialization of vectored interrupt controller has been done with ISRs
+ * mapped to the respective valid interrupt sources.
+ *
+ * @param[in] vector IRQ number for the device interrupt
+ *                   [0 - MAX_VIC_INTERRUPT_VECTOR]
+ *
+ * @retval E_SUCCESS             For success.
+ * @retval E_VIC_INVALID_VECTOR  Invalid input vector ID
+ */
+error_t irq_safe_disable(const uint32_t vector);
+
+/**
+ * @brief Set IRQ handler for a device interrupt
+ *
+ * This function registers an ISR for a device's IRQ number.
+ *
+ * @param[in] irq     SW IRQ number for the device's interrupt
+ * @param[in] routine Function pointer to the ISR
+ * @param[in] data    Pointer to the input arguments required by the ISR
+ *
+ * @pre
+ * - Interrupts are set using dynamic configuration
+ *
+ * @retval E_SUCCESS                      For success.
+ * @retval E_VIC_INVALID_INPUT_PARAMETER  Invalid software IRQ number
+ * @retval E_VIC_NULL_INPUT_PARAMETER     NULL pointer to the ISR
+ */
+error_t irq_safe_set_handler(uint32_t irq,
+                             irq_callback_fn routine,
+                             void *data);
+
+/**
+ * @brief Call interrupt handler for the device interrupt
+ *
+ * This function calls the registered interrupt handler for
+ * the device interrupt using software IRQ number.
+ *
+ * @param[in] irq Software IRQ number.
+ *
+ * @pre
+ * - Interrupts are set using dynamic configuration
+ *
+ */
+void irq_handler(uint32_t irq);
+
+/**
+ * @brief Get CPU interrupt status
+ *
+ * This function reads the IRQ disable bit in the CPSR to check
+ * if CPU is in interrupt mode.
+ *
+ * @retval true  if CPU is in interrupt mode.
+ * @retval false for all other CPU modes.
+ *
+ */
+bool in_interrupt(void);
+
+/**
+ * @brief Get CPU critical interrupt status
+ *
+ * This function checks whether CPU is operating in FIQ mode or not.
+ *
+ * @retval true  if CPU is in FIQ mode
+ * @retval false for all other modes
+ *
+ */
+bool in_critical(void);
+
+/**
+ * @brief enter critical section
+ *
+ * This function enters critical section by disabling the interrupts.
+ *
+ * @return None
+ */
+void enter_critical(void);
+
+/**
+ * @brief exit critical section
+ *
+ * This function exits critical section by re-enabling the interrupts.
+ *
+ * @return None
+ */
+void exit_critical(void);
+
+/**
+ * @brief Save interrupt context
+ *
+ * This function saves the VIC interrupt context comprising of 32-bit
+ * interrupt enable mask, 32-bit interrupt priority mask and interrupt handlers.
+ *
+ * @param[in] vic VIC instance number [0 - MAX_VIC_INSTANCE_ID]
+ * @param[in] ctx Pointer to the irq_context structure pre-declared by the user
+ *                for saving the interrupt context of input VIC instance
+ *
+ * @retval E_SUCCESS                      For success.
+ * @retval E_VIC_INVALID_VIC_INSTANCE     Invalid VIC instance ID
+ * @retval E_VIC_NULL_INPUT_PARAMETER     NULL irq_context pointer
+ */
+error_t irq_state_safe_save(const uint32_t vic,
+                            irq_context *ctx);
+
+/**
+ * @brief Restore interrupt context
+ *
+ * This function restores the VIC interrupt context comprising of 32-bit
+ * interrupt enable mask, 32-bit interrupt priority mask and interrupt handlers.
+ *
+ * @param[in] vic VIC instance number [0 - MAX_VIC_INSTANCE_ID]
+ * @param[in] ctx Pointer to the irq_context structure with interrupt context
+ *                data for the input VIC instance saved by call to
+ *                save_irq_state().
+ *                Data stored in the input irq_context structure is written
+ *                back to the VIC registers restoring the context.
+ *
+ * @retval E_SUCCESS                      For success.
+ * @retval E_VIC_INVALID_VIC_INSTANCE     Invalid VIC instance ID
+ * @retval E_VIC_NULL_INPUT_PARAMETER     NULL irq_context pointer
+ */
+error_t irq_state_safe_restore(const uint32_t vic,
+                               const irq_context *const ctx);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/irq/tegra-lic-priv.h b/spe-freertos-bsp/fsp/source/include/irq/tegra-lic-priv.h
new file mode 100644
index 0000000..3f6ebb7
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/irq/tegra-lic-priv.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2016-2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef IRQ__TEGRA_LIC_PRIV_H
+#define IRQ__TEGRA_LIC_PRIV_H
+#define FSP__IRQ__TEGRA_LIC_PRIV_H                      1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/* Mapping of <irqs.h> numbers to LIC IRQs */
+struct tegra_lic_bitslice {
+	uint8_t bit;
+	uint8_t slice;
+};
+
+struct tegra_lic_id {
+	uint8_t base_channel;
+	uint8_t num_channels;
+	uint8_t num_slices;
+	uint16_t local_irq;
+	uint16_t lic_irq_base;
+	uint16_t lic_map_size;
+	const struct tegra_lic_bitslice *lic_map;
+};
+
+#define TEGRA_LIC_BITSLICE(lic) \
+	{ \
+	.bit = (NV_ADDRESS_MAP_ ## lic ## _INTR_ID) % 32, \
+	.slice = (NV_ADDRESS_MAP_ ## lic ## _INTR_ID) / 32, \
+	}
+
+#endif	/* FSP_IRQ_TEGRA_LIC_PRIV_H */
diff --git a/spe-freertos-bsp/fsp/source/include/irq/tegra-lic.h b/spe-freertos-bsp/fsp/source/include/irq/tegra-lic.h
new file mode 100644
index 0000000..f703feb
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/irq/tegra-lic.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2015-2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef IRQ__TEGRA_LIC_H
+#define IRQ__TEGRA_LIC_H
+#define FSP__IRQ__TEGRA_LIC_H                           1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+// IWYU pragma: no_forward_declare tegra_lic_id
+struct tegra_lic_id;
+
+void tegra_lic_init(const struct tegra_lic_id *id);
+void tegra_lic_enable(const struct tegra_lic_id *id, uint32_t irq);
+void tegra_lic_disable(const struct tegra_lic_id *id, uint32_t irq);
+
+#endif	/* FSP_IRQ_TEGRA_LIC_H */
diff --git a/spe-freertos-bsp/fsp/source/include/lib/sections-stack-guard.h b/spe-freertos-bsp/fsp/source/include/lib/sections-stack-guard.h
new file mode 100644
index 0000000..f70aa10
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/lib/sections-stack-guard.h
@@ -0,0 +1,93 @@
+/* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIB__SECTIONS_STACK_GUARD_H
+#define LIB__SECTIONS_STACK_GUARD_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                              SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_STACKGUARD_DATA            SECTION_BUILDER(stackguard,             data)
+#define SECTION_NAME_STACKGUARD_RODATA          SECTION_BUILDER(stackguard,             rodata)
+#define SECTION_NAME_STACKGUARD_TEXT            SECTION_BUILDER(stackguard,             text)
+#define SECTION_NAME_STACKGUARD_INIT_DATA       SECTION_BUILDER(init.stackguard,        data)
+#define SECTION_NAME_STACKGUARD_INIT_TEXT       SECTION_BUILDER(init.stackguard,        text)
+
+#define SECTION_STR_STACKGUARD_TEXT             STR(SECTION_NAME_STACKGUARD_TEXT)
+#define SECTION_STR_STACKGUARD_RODATA           STR(SECTION_NAME_STACKGUARD_RODATA)
+#define SECTION_STR_STACKGUARD_DATA             STR(SECTION_NAME_STACKGUARD_DATA)
+#define SECTION_STR_STACKGUARD_INIT_TEXT        STR(SECTION_NAME_STACKGUARD_INIT_TEXT)
+#define SECTION_STR_STACKGUARD_INIT_DATA        STR(SECTION_NAME_STACKGUARD_INIT_DATA)
+
+#define SECTION_STACKGUARD_TEXT                 SECTION(SECTION_STR_STACKGUARD_TEXT)
+#define SECTION_STACKGUARD_RODATA               SECTION(SECTION_STR_STACKGUARD_RODATA)
+#define SECTION_STACKGUARD_DATA                 SECTION(SECTION_STR_STACKGUARD_DATA)
+#define SECTION_STACKGUARD_INIT_TEXT            SECTION(SECTION_STR_STACKGUARD_INIT_TEXT)
+#define SECTION_STACKGUARD_INIT_DATA            SECTION(SECTION_STR_STACKGUARD_INIT_DATA)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/lib/stack-guard.h b/spe-freertos-bsp/fsp/source/include/lib/stack-guard.h
new file mode 100644
index 0000000..d8915b7
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/lib/stack-guard.h
@@ -0,0 +1,67 @@
+/* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIB__STACK_GUARD_H
+#define LIB__STACK_GUARD_H
+#define FSP__LIB__STACK_GUARD_H                         1
+
+#include <stdint.h>
+#include <misc/macros.h>         // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                CERTC, DEVIATE, DCL37_C, "Approval:  Bug 2731179, DR: SWE-FSP-036-SWSADR.docx")
+/**
+ * @file stack-guard.h
+ * @brief Definition of stack guard as required by compiler
+ */
+
+/**
+ * @brief Initialize Stack Guard Variable
+ *
+ * This function will initialize the stack guard variable with the
+ * supplied value.  This allows the application a means to initialize
+ * the stack check variable with a (hopefully) randomized value.
+ */
+void stack_chk_init(uintptr_t check_value);
+
+/**
+ * @brief Stack Check Failure
+ *
+ * Called when the guard value on the stack has been overwritten.
+ * This function should only be called by compiler generated code.  No
+ * application code should call this function.
+ *
+ * @return Does not return
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_21_2, "Approval: JIRA TID-1063, DR: SWE-FSP-053-SWSADR.docx")
+void __stack_chk_fail(void);
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              CERTC, DEVIATE, DCL37_C, "Approval:  Bug 2731179, DR: SWE-FSP-036-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/libc-lite/libc.h b/spe-freertos-bsp/fsp/source/include/libc-lite/libc.h
new file mode 100644
index 0000000..85bf458
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/libc-lite/libc.h
@@ -0,0 +1,129 @@
+/**
+* @file libc.h
+*
+* @brief Exposes a handful of libc-lite utility functions used by other
+*        modules.
+*
+* Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+* * Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* * Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* * Neither the name of NVIDIA CORPORATION nor the names of its
+* contributors may be used to endorse or promote products derived
+* from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+* OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef LIBC__LIBC_H
+#define LIBC__LIBC_H
+#define FSP__LIBC__LIBC_H                             1
+
+#include <stddef.h>
+#include <stdarg.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <misc/ct-assert.h>
+#include <misc/macros.h>
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_6, "Approval: Bug 200543266, DR: SWE-FSP-003-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                MISRA, DEVIATE, Rule_21_2, "Approval: Jira TID-1970, DR: SWE-FSP-066-SWSADR.docx",
+                CERTC, DEVIATE, DCL37_C, "Approval: Bug 2731179, DR: SWE-FSP-067-SWSADR.docx")
+
+/**
+ * @brief libc memcpy
+ *
+ * Freestanding version of memcpy for RISCV units.
+ * Copies n characters from the object pointer to by src
+ * into the object pointed to by dst.
+ *
+ * @param[out] dst      destination pointer
+ * @param[in] src       source pointer
+ * @param[in] n         number of bytes to copy
+ *
+ * @return              resulting destination pointer
+ */
+void   *memcpy(void *dst, const void *src, size_t n);
+
+/**
+ * @brief libc memcmp
+ *
+ * Freestanding version of memcpy for RISCV units.
+ * Compares the first n characters of the object pointed to
+ * by s1 to the first n characters of the object pointer to
+ * by s2.
+ *
+ * @param[in] s1    first pointer
+ * @param[in] s2    second pointer
+ * @param[in] n     number of bytes to compare
+ *
+ * @return          zero if both memories are equal, otherwise unequal
+ */
+int memcmp(const void *s1, const void *s2, size_t n);
+
+/**
+ * @brief libc memset
+ *
+ * Freestanding version of memset for RISCV units.
+ * Copies the value of c (converted into an unsigned char)
+ * into each of the first n characters of the object pointer to by s.
+ *
+ * @param[out] s        pointer to memory to set
+ * @param[in] c         character to set
+ * @param[in] n         number of words to set
+ *
+ * @return              pointer to memory set (s)
+ */
+void   *memset(void *s, int c, size_t n);
+
+/**
+ * @brief libc isprint
+ *
+ * Freestanding version of isprint for RISCV units.
+ * Tests for any printing character including space (' ').
+ *
+ * @param[in] c     character to print
+ *
+ * @return          zero if the character is print-able
+ *
+ * NOTES:
+ * - MISRA RULE 10.3 fix - explicit conversion of characters
+ */
+__attribute__( ( always_inline ) ) static inline int isprint(int c)
+{
+    int is_p = 0;
+
+    if ((c >= (int)(' ')) && (c <= (int)('~')))
+    {
+        is_p = 1;
+    }
+
+    return is_p;
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_6, "Approval: Bug 200543266, DR: SWE-FSP-003-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              MISRA, DEVIATE, Rule_21_2, "Approval: Jira TID-1970, DR: SWE-FSP-066-SWSADR.docx",
+              CERTC, DEVIATE, DCL37_C, "Approval: Bug 2731179, DR: SWE-FSP-067-SWSADR.docx")
+
+#endif // LIBNVRISCV_LIBC_H
diff --git a/spe-freertos-bsp/fsp/source/include/lic/lic-errors.h b/spe-freertos-bsp/fsp/source/include/lic/lic-errors.h
new file mode 100644
index 0000000..9ae3abc
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/lic/lic-errors.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIC__LIC_ERRORS_H
+#define LIC__LIC_ERRORS_H
+#define FSP__LIC__LIC_ERRORS_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>	            // IWYU pragma: export
+                                        // IWYU pragma: no_include "base/module-id.h"
+#include <misc/macros.h>                // for END_RFD_BLOCK, START_RFD_BLOCK
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+    CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @file lic-errors.h
+ * @brief Error codes that are specific to the lic
+ */
+
+#define E_LIC_NULL_PTR          MODULE_ERROR(LIC, 0UL)
+#define E_LIC_NO_CHANS          MODULE_ERROR(LIC, 1UL)
+#define E_LIC_NO_IRQ            MODULE_ERROR(LIC, 2UL)
+#define E_LIC_NO_MAP            MODULE_ERROR(LIC, 3UL)
+#define E_LIC_INVALID_PARAM     MODULE_ERROR(LIC, 4UL)
+#define E_LIC_INVALID_IRQ       MODULE_ERROR(LIC, 5UL)
+
+#endif  /* LIC__LIC_ERRORS_H */
diff --git a/spe-freertos-bsp/fsp/source/include/lic/lic-tegra-priv.h b/spe-freertos-bsp/fsp/source/include/lic/lic-tegra-priv.h
new file mode 100644
index 0000000..5ebd3f2
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/lic/lic-tegra-priv.h
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIC__LIC_TEGRA_PRIV_H
+#define LIC__LIC_TEGRA_PRIV_H
+#define FSP__LIC__LIC_TEGRA_PRIV_H                      1
+
+/**
+ * @file lic/lic-tegra-priv.h
+ * @brief Structures that are internal to the LIC driver
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                // for bool
+#include <stdint.h>                 // for uint8_t, uint32_t, uint16_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>         // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>            // for END_RFD_BLOCK, START_RFD_BLOCK
+
+/* Module-specific FSP headers */
+#include <lic/lic-tegra.h>          // for FSP__LIC__LIC_TEGRA_H, lic_irq_t
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+    CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__LIC__LIC_TEGRA_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @file lic/lic-tegra-priv.h
+ * @brief Structures that are internal to the LIC driver
+ */
+
+/**
+ * @brief LIC irq handler context
+ *
+ * Structure that describes the parameter to the LIC irq handler.
+ *
+ * @id            pointer to LIC context id structure
+ * @chan          channel that triggered the irq
+ * @irqs_set      irqs enabled on this channel
+ * @is_vfiq       if the channel is FIQ/IRQ
+ */
+typedef struct {
+    struct tegra_lic_id *id;
+    uint8_t             chan;
+    uint32_t            irqs_set;
+    bool                is_vfiq;
+} lic_irq_context_t;
+
+
+/**
+ * @brief LIC configuration structure
+ *
+ * Structure that describes the configuration of the LIC.
+ *
+ * @base_chan       base channel for the current R5 cluster
+ * @num_chans       number of LIC channels supported
+ * @num_slices      number of slices supported per channel
+ * @local_irq_base  base VIC interrupt number for the LIC interrupt lines
+ * @lic_irq_base    start of the LIC interrupts for the cluster
+ */
+struct tegra_lic_conf {
+    uint8_t         base_chan;
+    uint8_t         num_chans;
+    uint8_t         num_slices;
+    uint16_t        local_irq_base;
+    uint16_t        lic_irq_base;
+};
+
+/**
+ * @brief LIC context ID structure
+ *
+ * Structure that is used by the LIC driver to manage the LIC state
+ * during run time.
+ *
+ * @conf                LIC configuration for the R5 cluster
+ * @lic_map             pointer to the LIC irq mapping for the cluster
+ * @irq_contexts        Pointer to the irq contexts for the LIC interrupts to
+ *                      R5 throught the local VIC
+ * @lic_map_size        size of the LIC irq map for the cluster
+ * @num_lic_irq_lines   Number of irq lines for LIC to the local VIC
+ */
+struct tegra_lic_id {
+    const struct tegra_lic_conf conf;
+    const lic_irq_t             *lic_map;
+    lic_irq_context_t           **irq_contexts;
+    uint32_t                    lic_map_size;
+    const uint32_t              num_lic_irq_lines;
+};
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/lic/lic-tegra.h b/spe-freertos-bsp/fsp/source/include/lic/lic-tegra.h
new file mode 100644
index 0000000..cefb052
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/lic/lic-tegra.h
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIC__LIC_TEGRA_H
+#define LIC__LIC_TEGRA_H
+#define FSP__LIC__LIC_TEGRA_H                      1
+
+/* Compiler headers */
+#include <stdint.h>                     // for uint32_t
+#include <stddef.h>                     // for NULL
+                                        // IWYU pragma: no_include <errno.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>        // for error_t, FSP__ERROR__COMMON...
+#include <irq/safe-irqs.h>              // for irq_callback_fn
+#include <misc/macros.h>                // for END_RFD_BLOCK, START_RFD_BLOCK
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx")
+    CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+/**
+ * @file lic-tegra.h
+ * @brief functions that provide access to various LIC registers.
+ */
+
+/**
+ * @brief Maximum number of slices per LIC channel
+ *
+ * Defines the maximum number of slices that are available per channel.
+ */
+#define LIC_MAX_SLICES      11
+
+/**
+ * @brief Define a LIC interrupt
+ *
+ * Fills the LIC irq structure with the info associated with a LIC interrupt.
+ */
+#define TEGRA_LIC_INTERRUPT(_local_irq, _irq) \
+    { \
+        .local_irq    = (uint8_t)(_local_irq), \
+        .bit          = (uint8_t)(CONCAT(NV_ADDRESS_MAP_, CONCAT(_irq, _INTR_ID)) & 31U), \
+        .slice        = (uint8_t)(CONCAT(NV_ADDRESS_MAP_, CONCAT(_irq, _INTR_ID)) >> 5U), \
+        .routine      = NULL, \
+        .cb_data      = NULL, \
+    }
+
+/**
+ * @brief Define a LIC interrupt with handler
+ *
+ * Fills the LIC irq structure with the info associated with a LIC interrupt.
+ * This also fills the handler to support static mapping.
+ */
+#define TEGRA_LIC_INTERRUPT_H(_local_irq, _irq, _isr, _isr_data) \
+    { \
+        .local_irq    = (uint8_t)(_local_irq), \
+        .bit          = (uint8_t)(CONCAT(NV_ADDRESS_MAP_, CONCAT(_irq, _INTR_ID)) & 31U), \
+        .slice        = (uint8_t)(CONCAT(NV_ADDRESS_MAP_, CONCAT(_irq, _INTR_ID)) >> 5U), \
+        .routine      = _isr, \
+        .cb_data      = _isr_data, \
+    }
+
+/*
+ * Declaration for tegra_lic_id that allows the APIs to take a pointer to it
+ * without actually defining its contents here.
+ */
+// IWYU pragma: no_forward_declare tegra_lic_id
+struct tegra_lic_id;
+
+/**
+ * @brief LIC irq info
+ *
+ * Structure that describes the info associated with a LIC irq.
+ *
+ * @local_irq    VIC irq number corresponding to the LIC channel
+ * @bit          bit for the irq to be set in the respective slice
+ * @slice        slice corresponding to the irq with in the LIC channel
+ * @routine      handler corresponding to the irq
+ * @cb_data      opaque pointer to irq handler data
+ */
+typedef struct {
+    uint8_t          local_irq;
+    uint8_t          bit;
+    uint8_t          slice;
+    irq_callback_fn  routine;
+    void             *cb_data;
+} lic_irq_t;
+
+/**
+ * @brief LIC mailbox irq handler.
+ *
+ * This function gets called whenever an interrupt is asserted on one of the
+ * LIC lines connected to local VIC.
+ *
+ * @pre the function tegra_lic_init() has been called
+ *
+ * @param[in] data opaque pointer for LIC context.
+ *
+ * @return None
+ */
+void tegra_lic_irq_handler(void *data);
+
+/**
+ * @brief Enable LIC interrupt
+ *
+ * This function enables the LIC interrupt for an irq that is not directly
+ * connected to the local VIC.
+ *
+ * @pre the function tegra_lic_init() has been called
+ *
+ * @param[in] id  LIC instance.
+ * @param[in] irq irq to be enabled.
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_LIC_NULL_PTR invalid id paramter passed
+ * @retval E_LIC_NO_INTR no LIC interrupt support
+ */
+error_t tegra_lic_irq_enable(const struct tegra_lic_id *id,
+                             uint32_t irq);
+
+/**
+ * @brief Disable LIC interrupt
+ *
+ * This function enables the LIC interrupt for an irq that is not directly
+ * connected to the local VIC.
+ *
+ * @pre the function tegra_lic_init() has been called
+ *
+ * @param[in] id  LIC instance.
+ * @param[in] irq irq to be enabled.
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_LIC_NULL_PTR invalid id paramter passed
+ * @retval E_LIC_NO_INTR no LIC interrupt support
+ */
+error_t tegra_lic_irq_disable(const struct tegra_lic_id *id,
+                              uint32_t irq);
+/**
+ * @brief Initialize the LIC context
+ *
+ * This function initializes the LIC context for an instance, enables the
+ * LIC interrupts.
+ *
+ * @param[in] id           pointer to the LIC descriptor instance.
+ * @param[in] lic_map      pointer to the LIC irq mapping for the cluster
+ * @param[in] lic_map_size size of the LIC irq map for the cluster
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_LIC_NULL_PTR       invalid id paramter passed
+ * @retval E_LIC_NO_CHANS       no LIC channels supported
+ * @retval E_LIC_NO_MAP         no LIC map provided
+ * @retval E_LIC_NO_IRQ         no LIC irqs supported
+ * @retval E_LIC_INVALID_PARAM  invalid id fields
+ */
+error_t tegra_lic_init(struct tegra_lic_id *id,
+                       const lic_irq_t *lic_map,
+                       const uint32_t lic_map_size);
+
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/lic/sections-lic.h b/spe-freertos-bsp/fsp/source/include/lic/sections-lic.h
new file mode 100644
index 0000000..0573b10
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/lic/sections-lic.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIC__SECTIONS_LIC_H
+#define LIC__SECTIONS_LIC_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx")
+    CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_LIC_DATA           SECTION_BUILDER(lic,                    data)
+#define SECTION_NAME_LIC_RODATA         SECTION_BUILDER(lic,                    rodata)
+#define SECTION_NAME_LIC_TEXT           SECTION_BUILDER(lic,                    text)
+#define SECTION_NAME_LIC_INIT_DATA      SECTION_BUILDER(init.lic,               data)
+#define SECTION_NAME_LIC_INIT_TEXT      SECTION_BUILDER(init.lic,               text)
+
+#define SECTION_STR_LIC_TEXT            STR(SECTION_NAME_LIC_TEXT)
+#define SECTION_STR_LIC_RODATA          STR(SECTION_NAME_LIC_RODATA)
+#define SECTION_STR_LIC_DATA            STR(SECTION_NAME_LIC_DATA)
+#define SECTION_STR_LIC_INIT_TEXT       STR(SECTION_NAME_LIC_INIT_TEXT)
+#define SECTION_STR_LIC_INIT_DATA       STR(SECTION_NAME_LIC_INIT_DATA)
+
+#define SECTION_LIC_TEXT                SECTION(SECTION_STR_LIC_TEXT)
+#define SECTION_LIC_RODATA              SECTION(SECTION_STR_LIC_RODATA)
+#define SECTION_LIC_DATA                SECTION(SECTION_STR_LIC_DATA)
+#define SECTION_LIC_INIT_TEXT           SECTION(SECTION_STR_LIC_INIT_TEXT)
+#define SECTION_LIC_INIT_DATA           SECTION(SECTION_STR_LIC_INIT_DATA)
+
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/lock/smplock-smp.h b/spe-freertos-bsp/fsp/source/include/lock/smplock-smp.h
new file mode 100644
index 0000000..5d37d91
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/lock/smplock-smp.h
@@ -0,0 +1,119 @@
+/*
+* Copyright (c) 2020 NVIDIA CORPORATION.  All rights reserved.
+*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef LOCK__SMPLOCK_SMP_H
+#define LOCK__SMPLOCK_SMP_H
+#define FSP__LOCK__SMPLOCK_SMP_H                      1
+
+/**
+ * @file lock/fsp-smplock.h
+ * @brief functions for smplock locking primitive.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/**
+ * @brief FSP smplock structure
+ *
+ * Structure that encapsulates and abstracts the architecture specific
+ * smplock.
+ *
+ * @slock   architecture specific smplock
+ */
+typedef struct {
+    arch_smplock_t slock;
+} smplock_t;
+
+/**
+ * @brief initialization of the smplock.
+ *
+ * @param[in] lock pointer to the FSP smplock
+ *
+ * @return None
+ */
+void smp_lock_init(smplock_t *lock);
+
+/**
+ * @brief save the interrupts and acquire the lock.
+ *
+ * This function disables interrupts locally and provide the smplock on SMP.
+ *
+ * @param[in] lock   pointer to the FSP smplock
+ * @param[in] flags  flags to save the irq status
+ *
+ * @return None
+ */
+void smp_lock_irqsave(smplock_t *lock,
+                      uint32_t *flags);
+
+/**
+ * @brief restore the interrupts and release the lock.
+ *
+ * This function restores the interrupts to the state when the lock was
+ * acquired and releases the lock.
+ *
+ * @param[in] lock   pointer to the FSP smplock
+ * @param[in] flags  flags to restore the irq status
+ *
+ * @return None
+ */
+void smp_unlock_irqrestore(smplock_t *lock,
+                           uint32_t *flags);
+
+/**
+ * @brief acquire the lock without any interaction with interrupts.
+ *
+ * This function only acquires the smplock and does not interact with the
+ * interrupts in anyway.
+ *
+ * @param[in] lock pointer to the FSP smplock
+ *
+ * @return None
+ */
+void smp_lock(smplock_t *lock);
+
+/**
+ * @brief release the lock without any interaction with interrupts.
+ *
+ * This function only releases the smplock and does not interact with the
+ * interrupts in anyway.
+ *
+ * @param[in] lock pointer to the FSP smplock
+ *
+ * @return None
+ */
+void smp_unlock(smplock_t *lock);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/lock/smplock-up.h b/spe-freertos-bsp/fsp/source/include/lock/smplock-up.h
new file mode 100644
index 0000000..9663ea2
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/lock/smplock-up.h
@@ -0,0 +1,178 @@
+/*
+* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef LOCK__SMPLOCK_UP_H
+#define LOCK__SMPLOCK_UP_H
+#define FSP__LOCK__SMPLOCK_UP_H                      1
+
+/**
+ * @file lock/fsp-smplock.h
+ * @brief functions for smplock locking primitive.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                           // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                   // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/smplock-types.h>                // for arch_smplock_t
+#include <misc/attributes.h>                  // for UNUSED, FSP__MISC__ATTR...
+#include <misc/macros.h>                      // for END_RFD_BLOCK, START_RF...
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__CPU__SMPLOCK_TYPES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+/**
+ * @brief FSP smplock structure
+ *
+ * Structure that encapsulates and abstracts the architecture specific
+ * smplock.
+ *
+ * @slock   architecture specific smplock
+ */
+typedef struct {
+    arch_smplock_t slock;
+} smplock_t;
+
+/**
+ * @brief initialization of the smplock.
+ *
+ * This function is a NOP for UP systems.
+ *
+ * @param[in] lock pointer to the FSP smplock
+ *
+ * @return None
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+static inline void smp_lock_init(smplock_t *lock)
+{
+    UNUSED(lock);
+}
+
+/**
+ * @brief save the interrupts and acquire the lock.
+ *
+ * This function is a NOP for UP systems.
+ *
+ * @param[in] lock   pointer to the FSP smplock
+ * @param[in] flags  flags to save the irq status
+ *
+ * @return None
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+static inline void smp_lock_irqsave(smplock_t *lock, uint32_t *flags)
+{
+    UNUSED(lock);
+    UNUSED(flags);
+
+    /**
+     * NOTE: Ideally this function should disable the irq , save the
+     * irq state wihtout doing any locking. However, these wrappers
+     * are primarily added just to add SMP support for the FSP drivers.
+     * For UP systems, the expectation currently is that these result
+     * in a NOP. Should that change, this needs to be modified.
+     */
+}
+
+/**
+ * @brief restore the interrupts and release the lock.
+ *
+ * This function is a NOP for UP systems.
+ *
+ * @param[in] lock   pointer to the FSP smplock
+ * @param[in] flags  flags to restore the irq status
+ *
+ * @return None
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+static inline void smp_unlock_irqrestore(smplock_t *lock, uint32_t *flags)
+{
+    UNUSED(lock);
+    UNUSED(flags);
+
+    /**
+     * NOTE: Ideally this function should restore the irq from the
+     * saved irq state wihtout doing any locking. However, these wrappers
+     * are primarily added just to add SMP support for the FSP drivers.
+     * For UP systems, the expectation currently is that these result
+     * in a NOP. Should that change, this needs to be modified.
+     */
+}
+
+/**
+ * @brief acquire the lock without any interaction with interrupts.
+ *
+ * This function is a NOP for UP systems.
+ *
+ * @param[in] lock pointer to the FSP smplock
+ *
+ * @return None
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+static inline void smp_lock(smplock_t *lock)
+{
+    UNUSED(lock);
+}
+
+/**
+ * @brief release the lock without any interaction with interrupts.
+ *
+ * This function only releases the smplock and does not interact with the
+ * interrupts in anyway.
+ *
+ * @param[in] lock pointer to the FSP smplock
+ *
+ * @return None
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+static inline void smp_unlock(smplock_t *lock)
+{
+    UNUSED(lock);
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/lock/smplock.h b/spe-freertos-bsp/fsp/source/include/lock/smplock.h
new file mode 100644
index 0000000..014b1b9
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/lock/smplock.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef LOCK__SMPLOCK_H
+#define LOCK__SMPLOCK_H
+#define FSP__LOCK__SMPLOCK_H                      1
+
+/**
+ * @file lock/smplock.h
+ * @brief functions for smplock locking primitive.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                 // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                    // for START_INLINE_RFD, END_INLINE_RFD
+
+/* Module-specific FSP headers */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#include <cpu/smplock-types.h>
+#if (defined(CONFIG_SMP) && defined(NCPU) && (NCPU > 1))
+#include <lock/smplock-smp.h>
+    CT_ASSERT(FSP__LOCK__SMPLOCK_SMP_H, "Header file missing or invalid.")
+#else
+#include <lock/smplock-up.h>
+    CT_ASSERT(FSP__LOCK__SMPLOCK_UP_H, "Header file missing or invalid.")
+#endif
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/logger/logger-data.h b/spe-freertos-bsp/fsp/source/include/logger/logger-data.h
new file mode 100644
index 0000000..831e7e2
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/logger/logger-data.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef LOGGER__LOGGER_DATA_H
+#define LOGGER__LOGGER_DATA_H
+#define FSP__LOGGER__LOGGER_DATA_H                      1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <logger-config.h>                              /* Immune from CT_ASSERT protection */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/bitops.h>
+#include <misc/macros.h>             // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Note: This value can only be increased by changing several other
+ * macros.  Notably _GET_NTH_ARG, COUNT_ARGS, SET_ARGS_<n> and
+ * SET_EACH_ARG.
+ */
+#define MAX_LOG_ARGS            8
+
+#if (LOG_ARG_WIDTH == 32)
+typedef uint32_t                log_arg_t;
+#else
+#if (LOG_ARG_WIDTH == 64)
+typedef uint64_t                log_arg_t;
+#else
+#error "Unsupported value for LOG_ARG_WIDTH"
+#endif
+#endif
+
+typedef log_arg_t               log_args_t[MAX_LOG_ARGS];
+
+#if (LOG_TOKEN_WIDTH == 32)
+typedef uint32_t                log_token_t;
+#else
+#if (LOG_TOKEN_WIDTH == 64)
+typedef uint64_t                log_token_t;
+#else
+#error "Unsupported value for LOG_TOKEN_WIDTH"
+#endif
+#endif
+
+/*
+ * Logging Levels
+ *
+ * Allows for enabling/disabling different trace points based upon
+ * which levels are enabled.
+ */
+#define LOG_LEVEL_ALWAYS        BIT(31)
+#define LOG_LEVEL_PERF          BIT(30)
+#define LOG_LEVEL_ERROR         BIT(29)
+#define LOG_LEVEL_CRIT          BIT(28)
+#define LOG_LEVEL_WARN          BIT(27)
+#define LOG_LEVEL_IRQ           BIT(26)
+#define LOG_LEVEL_BOOT          BIT(25)
+#define LOG_LEVEL_INFO          BIT(17)
+#define LOG_LEVEL_DEBUG         BIT(16)
+
+#define PRINT_LEVEL_ALWAYS      BIT(15)
+#define PRINT_LEVEL_PERF        BIT(14)
+#define PRINT_LEVEL_ERROR       BIT(13)
+#define PRINT_LEVEL_CRIT        BIT(12)
+#define PRINT_LEVEL_WARN        BIT(11)
+#define PRINT_LEVEL_IRQ         BIT(10)
+#define PRINT_LEVEL_BOOT        BIT(9)
+#define PRINT_LEVEL_INFO        BIT(1)
+#define PRINT_LEVEL_DEBUG       BIT(0)
+
+#define LOG_LEVEL_ALL           MASK32(31, 16)
+#define PRINT_LEVEL_ALL         MASK32(15, 0)
+
+/*
+ * Flags that indicate some general attributes about the log entry.
+ */
+#define LOG_FL_ERROR            BIT(31)             // error
+#define LOG_FL_START            BIT(30)             // start of an operation
+#define LOG_FL_END              BIT(29)             // end of an operation
+#define LOG_FL_PERF             BIT(28)             // perf related log entry
+#define LOG_FL_PRINT            BIT(27)             // print vs log entry
+#define LOG_FL_NONE             (0U)                // no flags
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+/*
+ * Log Meta-data structure
+ */
+typedef struct log_metadata_s {
+    uint32_t            id;
+    uint32_t            flags;
+    uint32_t            level;
+    uint32_t            n_args;
+    const char          *id_name;
+    const char          *file;
+    uint32_t            line_no;
+    const char          *fmt_string;
+    uint32_t            num_fixed_strings;
+#if (MAX_FIXED_STRINGS > 0)
+    const char          *fixed_strings[MAX_FIXED_STRINGS];
+#endif
+} log_metadata_t;
+
+/*
+ * Individual Log Entry
+ *
+ * The delta time recorded in each log entry is the time from the previous
+ * log entry.  The first log entry in a block of log entries will have
+ * a delta time of 0 (it is referencing the absolute time of the block).
+ */
+typedef struct log_entry_s {
+    uint32_t            delta_time;     // time from previous log entry
+    uint16_t            n_bytes;        // number of bytes in the log entry
+    uint8_t             n_fixed_args;   // number of fixed arguments that
+                                        // preceed the regular arguments
+                                        // that will be interpreted by the
+                                        // fixed strings in the meta-data.
+    uint8_t             fixed_flags;    // mapping of fixed argument(s) to
+                                        // fixed strings in the meta-data.
+    log_token_t         token;          // token that maps to trace_info_t
+    // Any supplied arguments to the log entry will follow
+} log_entry_t;
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/logger/logger-headers.h b/spe-freertos-bsp/fsp/source/include/logger/logger-headers.h
new file mode 100644
index 0000000..88e8bbb
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/logger/logger-headers.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2018-2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef LOGGER__LOGGER_HEADERS_H
+#define LOGGER__LOGGER_HEADERS_H
+#define FSP__LOGGER__LOGGER_HEADERS_H                   1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <logger-config.h>                              /* Immune from CT_ASSERT protection */
+
+/*
+ * Log block header that is written to DRAM, the indicated number of
+ * log entries immediately follows the header.
+ */
+typedef struct log_block_hdr_s {
+    uint64_t            start_time;     // time at start of block
+    uint16_t            n_entries;      // number of log entries in block
+    uint16_t            reserved_1;     // reserved field
+    uint32_t            reserved_2;     // reserved field
+    uint8_t             pad[48];        // get block header to be 64 bytes
+} log_block_hdr_t;
+
+/*
+ * Header for the overall log in memory.
+ *
+ * In this particular implementation, the log buffer is a circular
+ * buffer that is managed by head and tail offsets (from the start
+ * of the buffer...assuming that the header is at the start of the
+ * buffer).
+ *
+ * Each field in the header is aligned to the start of a cache line
+ * (if the two endpoints have different cache line sizes, then the
+ * value chosen should be the larger of the two) to prevent potential
+ * corruption of the non-updated offset (e.g. if both head and tail
+ * offsets were in the same cache line, updating one of them could
+ * result in the other being overwitten with a stale value when the
+ * cacheline is written back to DRAM).
+ */
+typedef struct log_header_s {
+    uint32_t            block_size;
+    uint8_t             header_align[LOG_CACHE_LINE_SIZE - sizeof(uint32_t)];
+    uint32_t            head_offset;
+    uint8_t             tail_align[LOG_CACHE_LINE_SIZE - sizeof(uint32_t)];
+    uint32_t            tail_offset;
+    uint8_t             pad[LOG_CACHE_LINE_SIZE - sizeof(uint32_t)];
+} log_header_t;
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/logger/logger-private.h b/spe-freertos-bsp/fsp/source/include/logger/logger-private.h
new file mode 100644
index 0000000..0217d97
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/logger/logger-private.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef LOGGER__LOGGER_PRIVATE_H
+#define LOGGER__LOGGER_PRIVATE_H
+#define FSP__LOGGER__LOGGER_PRIVATE_H                   1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>             // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <logger-config.h>           /* Immune from CT_ASSERT protection */
+#include <logger/logger-data.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__LOGGER__LOGGER_DATA_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/*
+ * Internal definitions that are only used by the logging
+ * system itself.  Should not be visible outside of that.
+ */
+typedef uint32_t                log_buff_state_t;
+
+#define LEB_STATE_EMPTY         0       // buffer is empty
+#define LEB_STATE_PARTIAL       1       // buffer has some log entries
+#define LEB_STATE_FULL          2       // buffer is full
+#define LEB_STATE_TOCOPY        3       // buffer is to be copied
+#define LEB_STATE_COPYING       4       // buffer is actively being copied
+
+/*
+ * Internal log buffer
+ */
+typedef struct log_buff {
+    uint64_t            start_time;     // time of first entry in buffer
+    uint64_t            last_time;      // time of last entry in buffer
+    uint32_t            next;           // next available byte in buffer
+    uint32_t            remaining;      // remaining bytes in buffer
+    log_buff_state_t    state;          // state of the buffer
+    uint32_t            pad;            // to align next field
+    uint8_t             buffer[LOG_BUFFER_SIZE];
+} log_buff_t;
+
+typedef void (*log_hook_t)(const log_metadata_t * const token,
+                           const uint32_t n_args,
+                           log_args_t args);
+
+extern log_hook_t       log_print_hook;
+extern void             *log_log_area;
+extern log_buff_t       *log_cur_buff;
+extern log_buff_t       log_buffers[NUM_LOG_BUFFERS];
+extern uint32_t         cur_buff_num;
+
+void log_buffer_push(log_buff_t * const buff);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/logger/logger.h b/spe-freertos-bsp/fsp/source/include/logger/logger.h
new file mode 100644
index 0000000..96634b6
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/logger/logger.h
@@ -0,0 +1,251 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef LOGGER__LOGGER_H
+#define LOGGER__LOGGER_H
+#define FSP__LOGGER__LOGGER_H                           1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>         // for USED
+#include <misc/bitops.h>
+#include <misc/macros.h>             // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <logger-config.h>           // for LOG_ENABLE
+#include <logger/sections-logger.h>  /* Immune from CT_ASSERT protection */
+#include <logger/logger-data.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__LOGGER__LOGGER_DATA_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_20_10, "Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx")
+#define MODULE_LOG_ID(_id_)     (MODULE_ID_##_id_)
+
+#define LOG_ID(_major_, _minor_, _seq_)                                         \
+    ((INSERT(0U, 30, 16, (MODULE_LOG_ID(_major_))))                             \
+     | (INSERT(0U, 15, 8, _minor_))                                             \
+     | (INSERT(0U, 7, 0, _seq_)))
+
+void log_entry(const log_metadata_t * const token,
+               const uint8_t n_args,
+               log_args_t args);
+
+extern uint32_t                 log_level;
+
+#define LOG_GET_NTH_ARG(_1_, _2_, _3_, _4_, _5_, _6_, _7_, _8_, _arg_, ...)     \
+    _arg_
+
+#define LOG_COUNT_ARGS(...)                                                     \
+    LOG_GET_NTH_ARG(__VA_ARGS__, 8, 7, 6, 5, 4, 3, 2, 1, 0,)
+
+#define LOG_XFIRST(_X_, ...)    _X_
+#define LOG_FIRST(...)          LOG_XFIRST(##__VA_ARGS__)
+#define LOG_REST(_X_, ...)      __VA_ARGS__
+
+#define LOG_SET_NTH_ARG(_args_, _n_, _arg_)                                     \
+    (_args_)[(_n_)] = (log_arg_t)_arg_;
+
+#define LOG_SET_ARGS_0(_args_, _n_, ...)
+#define LOG_SET_ARGS_1(_args_, _n_, _arg_, ...)                                 \
+    LOG_SET_NTH_ARG(_args_, _n_, _arg_)
+#define LOG_SET_ARGS_2(_args_, _n_,_arg_, ...)                                  \
+    LOG_SET_NTH_ARG(_args_, _n_, _arg_)                                         \
+    LOG_SET_ARGS_1(_args_, (_n_) + 1, __VA_ARGS__)
+#define LOG_SET_ARGS_3(_args_, _n_, _arg_, ...)                                 \
+    LOG_SET_NTH_ARG(_args_, _n_, _arg_)                                         \
+    LOG_SET_ARGS_2(_args_, (_n_) + 1, __VA_ARGS__)
+#define LOG_SET_ARGS_4(_args_, _n_, _arg_, ...)                                 \
+    LOG_SET_NTH_ARG(_args_, _n_, _arg_)                                         \
+    LOG_SET_ARGS_3(_args_, (_n_) + 1, __VA_ARGS__)
+#define LOG_SET_ARGS_5(_args_, _n_, _arg_, ...)                                 \
+    LOG_SET_NTH_ARG(_args_, _n_, _arg_)                                         \
+    LOG_SET_ARGS_4(_args_, (_n_) + 1, __VA_ARGS__)
+#define LOG_SET_ARGS_6(_args_, _n_, _arg_, ...)                                 \
+    LOG_SET_NTH_ARG(_args_, _n_, _arg_)                                         \
+    LOG_SET_ARGS_5(_args_, (_n_) + 1, __VA_ARGS__)
+#define LOG_SET_ARGS_7(_args_, _n_, _arg_, ...)                                 \
+    LOG_SET_NTH_ARG(_args_, _n_, _arg_)                                         \
+    LOG_SET_ARGS_6(_args_, (_n_) + 1, __VA_ARGS__)
+#define LOG_SET_ARGS_8(_args_, _n_, _arg_, ...)                                 \
+    LOG_SET_NTH_ARG(_args_, _n_, _arg_)                                         \
+    LOG_SET_ARGS_7(_args_, (_n_) + 1, __VA_ARGS__)
+
+#define LOG_SET_EACH_ARG(_args_, ...)                                           \
+    LOG_GET_NTH_ARG(__VA_ARGS__,                                                \
+                 LOG_SET_ARGS_8, LOG_SET_ARGS_7, LOG_SET_ARGS_6, LOG_SET_ARGS_5,\
+                 LOG_SET_ARGS_4, LOG_SET_ARGS_3, LOG_SET_ARGS_2, LOG_SET_ARGS_1,\
+                 LOG_SET_ARGS_0,) (_args_, 0, __VA_ARGS__,)
+
+/*
+ * This version of the XLOGX macro does not provide the ability to
+ * set "fixed strings" as none of the other macros would fill them
+ * in or have the run-time ability to set the appropriate values.
+ */
+#define XLOGX(_level_, _id_, _id_str_, _flags_, _fmt_, ...)                     \
+    {                                                                           \
+        static const char SECTION_LOG_METADATA_STRINGS xxlog_id_str[] = _id_str_;\
+        static const char SECTION_LOG_METADATA_STRINGS xxlog_f_name[] = __FILE__;\
+        static const char SECTION_LOG_METADATA_STRINGS xxlog_fmt_str[] = _fmt_; \
+        static const log_metadata_t xxlog_metadata USED SECTION_LOG_METADATA_DATA = {\
+            .id         = _id_,                                                 \
+            .flags      = _flags_,                                              \
+            .level      = _level_,                                              \
+            .n_args     = LOG_COUNT_ARGS(__VA_ARGS__),                          \
+            .id_name    = &xxlog_id_str[0],                                     \
+            .file       = &xxlog_f_name[0],                                     \
+            .line_no    = __LINE__,                                             \
+            .fmt_string = &xxlog_fmt_str[0],                                    \
+            .num_fixed_strings = 0UL,                                             \
+        };                                                                      \
+        log_args_t         xxlog_log_args;                                      \
+        if (((_level_ & (LOG_LEVEL_ALWAYS | PRINT_LEVEL_ALWAYS)) != 0UL)          \
+            || ((_level_ & log_level) != 0UL)) {                                  \
+            LOG_SET_EACH_ARG(xxlog_log_args, __VA_ARGS__);                      \
+            log_entry(&xxlog_metadata, LOG_COUNT_ARGS(__VA_ARGS__),             \
+                      &xxlog_log_args[0]);                                      \
+        }                                                                       \
+    }
+
+#define LOGX(_level_, _id_, _id_str_, _flags_, ...)                             \
+    XLOGX(_level_, _id_, _id_str_, _flags_, "", __VA_ARGS__);
+
+#define XLOG(_level_, _id_, _id_str_, _flags_, ...)                             \
+    if ((LOG_ENABLE==1) && (_level_##_ENABLE==1)) {                             \
+        LOGX(_level_, _id_, _id_str_, _flags_, __VA_ARGS__);                    \
+    }
+
+#define LOG(_level_, _id_,  _flags_, ...)                                       \
+    if (LOG_ENABLE==1) {                                                        \
+        LOGX(_level_, _id_, #_id_, _flags_, __VA_ARGS__);                       \
+    }
+
+#define LOG_ERROR_ALWAYS(_id_, ...)                                                    \
+    LOG(LOG_LEVEL_ERROR, _id_, LOG_FL_ERROR, __VA_ARGS__);
+
+#define LOG_ALWAYS(_id_, _flags_, ...)                                          \
+    XLOG(LOG_LEVEL_ALWAYS, _id_, #_id_, _flags_, __VA_ARGS__)
+
+#define LOG_PERF(_id_, _flags_, ...)                                            \
+    XLOG(LOG_LEVEL_PERF, _id_, #_id_, _flags_, __VA_ARGS__)
+
+#define LOG_ERROR(_id_, _flags_, ...)                                           \
+    XLOG(LOG_LEVEL_ERROR, _id_, #_id_, _flags_, __VA_ARGS__)
+
+#define LOG_CRIT(_id_, _flags_, ...)                                            \
+    XLOG(LOG_LEVEL_CRIT, _id_, #_id_, _flags_, __VA_ARGS__)
+
+#define LOG_WARN(_id_, _flags_, ...)                                            \
+    XLOG(LOG_LEVEL_WARN, _id_, #_id_, _flags_, __VA_ARGS__)
+
+#define LOG_INFO(_id_, _flags_, ...)                                            \
+    XLOG(LOG_LEVEL_INFO, _id_, #_id_, _flags_, __VA_ARGS__)
+
+#define LOG_IRQ(_id_, _flags_, ...)                                             \
+    XLOG(LOG_LEVEL_IRQ, _id_, #_id_, _flags_, __VA_ARGS__)
+
+#define LOG_BOOT(_id_, _flags_, ...)                                            \
+    XLOG(LOG_LEVEL_BOOT, _id_, #_id_,_flags_, __VA_ARGS__)
+
+#define LOG_DEBUG(_id_, _flags_, ...)                                           \
+    XLOG(LOG_LEVEL_DEBUG, _id_, #_id_, _flags_, __VA_ARGS__)
+
+#define XPRINTX(_level_, _fmt_, ...)                                            \
+    XLOGX(_level_, DCE_LOG_PRINT, "",  LOG_FL_PRINT, _fmt_, __VA_ARGS__);
+
+#define XPRINT(_level_, _fmt_, ...)                                             \
+    if ((PRINT_ENABLE==1) && (_level_##_ENABLE==1)) {                           \
+        XPRINTX(_level_, _fmt_, __VA_ARGS__);                                   \
+    }
+
+#define LOGGING_PRINT(_level_, _fmt_, ...)                                              \
+    if (PRINT_ENABLE==1) {                                                      \
+        XPRINTX(_level_, _fmt_, __VA_ARGS__);                                   \
+    }
+
+#define print(_fmt_, ...)                                                       \
+    XPRINT(PRINT_LEVEL_ALWAYS, _fmt_, __VA_ARGS__);
+
+#define PRINT_ALWAYS(_fmt_, ...)                                                \
+    XPRINT(PRINT_LEVEL_ALWAYS, _fmt_, __VA_ARGS__);
+
+#define PRINT_PERF(_fmt_, ...)                                                  \
+    XPRINT(PRINT_LEVEL_PERF, _fmt_, __VA_ARGS__);
+
+#define PRINT_ERROR(_fmt_, ...)                                                 \
+    XPRINT(PRINT_LEVEL_ERROR, _fmt_, __VA_ARGS__);
+
+#define PRINT_CRIT(_fmt_, ...)                                                  \
+    XPRINT(PRINT_LEVEL_CRIT, _fmt_, __VA_ARGS__);
+
+#define PRINT_WARN(_fmt_, ...)                                                  \
+    XPRINT(PRINT_LEVEL_WARN, _fmt_, __VA_ARGS__);
+
+#define PRINT_INFO(_fmt_, ...)                                                  \
+    XPRINT(PRINT_LEVEL_INFO, _fmt_, __VA_ARGS__);
+
+#define PRINT_IRQ(_fmt_, ...)                                                   \
+    XPRINT(PRINT_LEVEL_IRQ, _fmt_, __VA_ARGS__);
+
+#define PRINT_BOOT(_fmt_, ...)                                                  \
+    XPRINT(PRINT_LEVEL_BOOT, _fmt_, __VA_ARGS__);
+
+#define PRINT_DEBUG(_fmt_, ...)                                                 \
+    XPRINT(PRINT_LEVEL_DEBUG, _fmt_, __VA_ARGS__);
+
+void log_set_level_mask(const uint32_t mask);
+uint32_t log_get_level_mask(void);
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              MISRA, DEVIATE, Rule_20_10, "Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/logger/sections-logger.h b/spe-freertos-bsp/fsp/source/include/logger/sections-logger.h
new file mode 100644
index 0000000..2ea1277
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/logger/sections-logger.h
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef LOGGER__SECTIONS_LOGGER_H
+#define LOGGER__SECTIONS_LOGGER_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                              SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_LOG_BSS                    SECTION_BUILDER(log,                    bss)
+#define SECTION_NAME_LOG_DATA                   SECTION_BUILDER(log,                    data)
+#define SECTION_NAME_LOG_TEXT                   SECTION_BUILDER(log,                    text)
+#define SECTION_NAME_LOG_ADMIN_TEXT             SECTION_BUILDER(admin.log,              text)
+#define SECTION_NAME_LOG_INIT_DATA              SECTION_BUILDER(init.log,               data)
+#define SECTION_NAME_LOG_INIT_TEXT              SECTION_BUILDER(init.log,               text)
+#define SECTION_NAME_LOG_METADATA_DATA          SECTION_BUILDER(metadata.data,          data)
+#define SECTION_NAME_LOG_METADATA_STRINGS       SECTION_BUILDER(metadata.strings,       data)
+
+
+#define SECTION_STR_LOG_TEXT                    STR(SECTION_NAME_LOG_TEXT)
+#define SECTION_STR_LOG_DATA                    STR(SECTION_NAME_LOG_DATA)
+#define SECTION_STR_LOG_BSS                     STR(SECTION_NAME_LOG_BSS)
+#define SECTION_STR_LOG_INIT_TEXT               STR(SECTION_NAME_LOG_INIT_TEXT)
+#define SECTION_STR_LOG_INIT_DATA               STR(SECTION_NAME_LOG_INIT_DATA)
+#define SECTION_STR_LOG_ADMIN_TEXT              STR(SECTION_NAME_LOG_ADMIN_TEXT)
+#define SECTION_STR_LOG_METADATA_STRINGS        STR(SECTION_NAME_LOG_METADATA_STRINGS)
+#define SECTION_STR_LOG_METADATA_DATA           STR(SECTION_NAME_LOG_METADATA_DATA)
+
+#define SECTION_LOG_TEXT                        SECTION(SECTION_STR_LOG_TEXT)
+#define SECTION_LOG_DATA                        SECTION(SECTION_STR_LOG_DATA)
+#define SECTION_LOG_BSS                         SECTION(SECTION_STR_LOG_BSS)
+#define SECTION_LOG_INIT_TEXT                   SECTION(SECTION_STR_LOG_INIT_TEXT)
+#define SECTION_LOG_INIT_DATA                   SECTION(SECTION_STR_LOG_INIT_DATA)
+#define SECTION_LOG_ADMIN_TEXT                  SECTION(SECTION_STR_LOG_ADMIN_TEXT)
+#define SECTION_LOG_METADATA_STRINGS            SECTION(SECTION_STR_LOG_METADATA_STRINGS)
+#define SECTION_LOG_METADATA_DATA               SECTION(SECTION_STR_LOG_METADATA_DATA)
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/misc/attributes.h b/spe-freertos-bsp/fsp/source/include/misc/attributes.h
new file mode 100644
index 0000000..1661c3b
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/misc/attributes.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef MISC__ATTRIBUTES_H
+#define MISC__ATTRIBUTES_H
+#define FSP__MISC__ATTRIBUTES_H                         1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>         // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+#ifndef __ASSEMBLER__
+
+#define NO_RETURN       __attribute__ ((noreturn))
+#define NAKED           __attribute__ ((naked))
+
+#ifdef LONG_CALLS
+#define LONG_CALL       __attribute__ ((__long_call__))
+#else
+#define LONG_CALL
+#endif
+
+#define NO_INLINE       __attribute__ ((noinline))
+#define SECTION(_s_)    __attribute__ ((section(_s_)))
+#define ALIAS(_s_)      __attribute__ ((alias(STR(_s_))))
+#define USED            __attribute__ ((used))
+#define WEAK            __attribute__ ((weak))
+#define ALIGN(_v_)      __attribute__ ((aligned(_v_)))
+
+#ifndef USE_C11
+#define C99_Alignof(_x_)    ((~sizeof(_x_))+1)
+#define FSP_ALIGNOF         C99_Alignof
+#else
+INLINE_RFD(MISRA, DEVIATE, Rule_1_4, "Approval: JIRA TID-1311, DR: SWE-FSP-061-SWSADR.docx")
+#define FSP_ALIGNOF         _Alignof
+#endif
+
+#define UNUSED(x)       ((void)x)
+
+/*
+ * Use UNUSED_NONCONST_PTR to declare deliberate design intent NOT to use const
+ * even though the contents of the data pointed to is not modified.
+ *
+ * MISRA flags non-const pointers when the data is untouched even though
+ * the data may be modified in future code updates or it is semantically changing.
+ *
+ * Please don't overuse. Prefer const data instead.
+ * It usually leads to a cleaner design and more efficient workflow.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_13, "Approval: Bug 2687886, DR: SWE-FSP-017-SWSADR.docx")
+inline static void UNUSED_NONCONST_PTR(void* whitelist_this)
+{
+        /*
+         * This is likely to be flagged with MISRA Directive 8.13 violation.
+         * It should be white-listed using static code scanning tools.
+         */
+
+        UNUSED(whitelist_this);
+}
+
+#endif
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/misc/bitops.h b/spe-freertos-bsp/fsp/source/include/misc/bitops.h
new file mode 100644
index 0000000..0c8ddbd
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/misc/bitops.h
@@ -0,0 +1,637 @@
+/*
+ * Copyright (c) 2016-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef MISC__BITOPS_H
+#define MISC__BITOPS_H
+#define FSP__MISC__BITOPS_H                             1
+
+#ifndef __ASSEMBLER__
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+#include <misc/ct-assert.h>
+#include <misc/macros.h>         // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+                CERTC, DEVIATE, DCL37_C, "Approval:  Bug 2731179, DR: SWE-FSP-036-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file bitops.h
+ * @brief functions and macros that provide bit manipulation support.
+ */
+
+/**
+ * @brief define a bit mask for the 16-bit value
+ *
+ * @jama_func_req_id 8218676
+ *
+ * This macro will set a bit represented by the bit-index in a half word.
+ *
+ * @param[in] _b_ 16-bit immediate value
+ *
+ * @result 16-bit value with the input bit-index set to 1.
+ */
+#define BIT16(_b_)  ((uint16_t)(((uint16_t)1U) << (_b_)))
+
+/**
+ * @brief define a bit mask for the 16-bit value
+ *
+ * @jama_func_req_id 8218676
+ *
+ * This macro will set a bit represented by the bit-index in a half word.
+ *
+ * @param[in] _b_ 16-bit variable
+ *
+ * @result 16-bit value with the input bit-index set to 1.
+ */
+static inline uint16_t BIT16_FN(uint16_t varbit)
+{
+    uint16_t retval = 0U;
+    if(varbit < 16U) {
+        INLINE_RFD(CERTC, FP, INT31_C, "Approval: JIRA TID-616, DR: SWE-FSP-050-SWSADR.docx");
+        retval = (uint16_t)((uint16_t)1U << varbit);
+    }
+    return retval;
+}
+
+/**
+ * @brief create bit mask of a specific field in a 16-bit value
+ *
+ * @jama_func_req_id 8245844
+ *
+ * This macro will create the bit mask of a field specified by msb and lsb
+ * indices in a 16-bit value.
+ *
+ * @param[in] _msb_ msb index
+ * @param[in] _lsb_ lsb index
+ *
+ * @result bit mask of the field specified by msb and lsb indices.
+ */
+#define MASK16(_msb_, _lsb_)                                                    \
+    (((uint16_t)(BIT16(_msb_) - (uint16_t)1U) | BIT16(_msb_)) &                 \
+     ((uint16_t)~(BIT16(_lsb_) - (uint16_t)1U)))
+
+/**
+ * @brief Extract a field specified by start and end bit in a 16-bit value
+ *
+ * @jama_func_req_id 8220128
+ *
+ * This macro will extract the bit-field specified by msb and lsb
+ * indices in a 16-bit value.
+ *
+ * @param[in] _x_ 16-bit value
+ * @param[in] _msb_ msb index
+ * @param[in] _lsb_ lsb index
+ * @param[in] _type_ return data type
+ *
+ * @result field specified by [msb, lsb] casted to return data type
+ */
+#define EXTRACT16(_x_, _msb_, _lsb_, _type_)                                    \
+    ((_type_)((_type_)((_x_) & MASK16(_msb_, _lsb_)) >> (_lsb_)))
+
+/**
+ * @brief Write to a specific field in a 16-bit value
+ *
+ * @jama_func_req_id 8245826
+ *
+ * This macro will write to a bit-field specified by msb and lsb
+ * indices in a 16-bit value.
+ *
+ * @param[in] _x_ 16-bit value
+ * @param[in] _msb_ msb index
+ * @param[in] _lsb_ lsb index
+ * @param[in] _value_ value to be written to the specific field
+ *
+ * @result 16-bit value with the modified field specified by msb and lsb indices
+ */
+#define INSERT16(_x_, _msb_, _lsb_, _value_)                                    \
+    ((((uint16_t)_x_) & ((uint16_t)~MASK16(_msb_, _lsb_)))                      \
+     | ((((uint16_t)_value_) << _lsb_) & MASK16(_msb_, _lsb_)))
+
+/**
+ * @brief define a bit mask for the 32-bit value
+ *
+ * @jama_func_req_id 8218670
+ *
+ * This macro will set a bit represented by the bit-index in a word.
+ *
+ * @param[in] _b_ 32-bit immediate value
+ *
+ * @result 32-bit value with the input bit-index set to 1.
+ */
+#define BIT32(_b_)  ((uint32_t)(((uint32_t)1U) << (_b_)))
+
+/**
+ * @brief define a bit mask for the 32-bit value
+ *
+ * @jama_func_req_id 8218670
+ *
+ * This macro will set a bit represented by the bit-index in a word.
+ *
+ * @param[in] _b_ 32-bit variable
+ *
+ * @result 32-bit value with the input bit-index set to 1.
+ */
+static inline uint32_t BIT32_FN(uint32_t varbit)
+{
+    uint32_t retval = 0U;
+    if(varbit < 32U) {
+        retval = (uint32_t)((uint32_t)1U << varbit);
+    }
+    return retval;
+}
+
+/**
+ * @brief create bit mask of a specific field in a 32-bit value
+ *
+ * @jama_func_req_id 8245850
+ *
+ * This macro will create the bit mask of a field specified by msb and lsb
+ * indices in a 32-bit value.
+ *
+ * @param[in] _msb_ msb index
+ * @param[in] _lsb_ lsb index
+ *
+ * @result bit mask of the field specified by msb and lsb indices.
+ */
+#define MASK32(_msb_, _lsb_)                                                    \
+    (((uint32_t)(BIT32(_msb_) - (uint32_t)1U) | BIT32(_msb_)) & ((uint32_t)~(BIT32(_lsb_) - (uint32_t)1U)))
+
+/**
+ * @brief Extract a field specified by start and end bit in a 32-bit value
+ *
+ * @jama_func_req_id 8220131
+ *
+ * This macro will extract the bit-field specified by msb and lsb
+ * indices in a 32-bit value.
+ *
+ * @param[in] _x_ 32-bit value
+ * @param[in] _msb_ msb index
+ * @param[in] _lsb_ lsb index
+ * @param[in] _type_ return data type
+ *
+ * @result field specified by [msb, lsb] casted to return data type
+ */
+#define EXTRACT32(_x_, _msb_, _lsb_, _type_)                                    \
+    ((_type_)((_type_)((_x_) & MASK32(_msb_, _lsb_)) >> (_lsb_)))
+
+/**
+ * @brief Write to a specific field in a 32-bit value
+ *
+ * @jama_func_req_id 8245829
+ *
+ * This macro will write to a bit-field specified by msb and lsb
+ * indices in a 32-bit value.
+ *
+ * @param[in] _x_ 32-bit value
+ * @param[in] _msb_ msb index
+ * @param[in] _lsb_ lsb index
+ * @param[in] _value_ value to be written to the specific field
+ *
+ * @result 32-bit value with the modified field specified by msb and lsb indices
+ */
+#define INSERT32(_x_, _msb_, _lsb_, _value_)                                    \
+    ((((uint32_t)_x_) & ((uint32_t)~MASK32(_msb_, _lsb_)))                      \
+     | ((((uint32_t)_value_) << _lsb_) & MASK32(_msb_, _lsb_)))
+
+/*
+ * Aliases for 32-bit operations
+ */
+#define BIT(_x_)                            BIT32(_x_)
+#define MASK(_msb_, _lsb_)                  MASK32(_msb_, _lsb_)
+#define EXTRACT(_x_, _msb_, _lsb_, _type_)  EXTRACT32(_x_, _msb_, _lsb_, _type_)
+#define INSERT(_x_, _msb_, _lsb_, _value_)  INSERT32(_x_, _msb_, _lsb_, _value_)
+
+/**
+ * @brief define a bit mask for the 64-bit value
+ *
+ * @jama_func_req_id 8218694
+ *
+ * This macro will set a bit represented by the bit-index in a 64-bit value.
+ *
+ * @param[in] _b_ 64-bit immediate value
+ *
+ * @result 64-bit value with the input bit-index set to 1.
+ */
+#define BIT64(_b_)  ((uint64_t)(((uint64_t)1U) << (_b_)))
+
+/**
+ * @brief define a bit mask for the 64-bit value
+ *
+ * @jama_func_req_id 8218694
+ *
+ * This macro will set a bit represented by the bit-index in a 64-bit value.
+ *
+ * @param[in] _b_ 64-bit variable
+ *
+ * @result 64-bit value with the input bit-index set to 1.
+ */
+static inline uint64_t BIT64_FN(uint64_t varbit)
+{
+    uint64_t retval = 0U;
+    if(varbit < 64U) {
+        retval = (uint64_t)((uint64_t)1U << varbit);
+    }
+    return retval;
+}
+
+/**
+ * @brief create bit mask of a specific field in a 64-bit value
+ *
+ * @jama_func_req_id 8245856
+ *
+ * This macro will create the bit mask of a field specified by msb and lsb
+ * indices in a 64-bit value.
+ *
+ * @param[in] _msb_ msb index
+ * @param[in] _lsb_ lsb index
+ *
+ * @result bit mask of the field specified by msb and lsb indices.
+ */
+#define MASK64(_msb_, _lsb_)                                                    \
+    (((uint64_t)(BIT64(_msb_) - (uint64_t)1U) | BIT64(_msb_)) & ((uint64_t)~(BIT64(_lsb_) - (uint64_t)1U)))
+
+/**
+ * @brief Extract a field specified by start and end bit in a 64-bit value
+ *
+ * @jama_func_req_id 8221487
+ *
+ * This macro will extract the bit-field specified by msb and lsb
+ * indices in a 64-bit value.
+ *
+ * @param[in] _x_ 64-bit value
+ * @param[in] _msb_ msb index
+ * @param[in] _lsb_ lsb index
+ * @param[in] _type_ return data type
+ *
+ * @result field specified by [msb, lsb] casted to return data type
+ */
+#define EXTRACT64(_x_, _msb_, _lsb_, _type_)                                    \
+    ((_type_)((_type_)((_x_) & MASK64(_msb_, _lsb_)) >> (_lsb_)))
+
+/**
+ * @brief Write to a specific field in a 64-bit value
+ *
+ * @jama_func_req_id 8245835
+ *
+ * This macro will write to a bit-field specified by msb and lsb
+ * indices in a 64-bit value.
+ *
+ * @param[in] _x_ 64-bit value
+ * @param[in] _msb_ msb index
+ * @param[in] _lsb_ lsb index
+ * @param[in] _value_ value to be written to the specific field
+ *
+ * @result 64-bit value with the modified field specified by msb and lsb indices
+ */
+#define INSERT64(_x_, _msb_, _lsb_, _value_)                                    \
+    ((((uint64_t)_x_) & ((uint64_t)~MASK64(_msb_, _lsb_)))                      \
+     | ((((uint64_t)_value_) << _lsb_) & MASK64(_msb_, _lsb_)))
+
+/**
+ * @brief Pack a 64-bit value from upper & lower 32-bit values
+ *
+ * @jama_func_req_id 8218523
+ *
+ * This macro creates the 64-bit value resulting from the MSW(upper 32-bit)
+ * and LSW(lower 32-bit) values.
+ *
+ * @param[in] _h_ upper 32-bit value
+ * @param[in] _l_ lower 32-bit value
+ *
+ * @result - 64-bit value resulting from the MSW and LSW
+ */
+#define PACK64(_l_, _h_)        ((((uint64_t)(_h_)) << 32) | (_l_))
+
+/**
+ * @brief Fetch the Most Significant Word from 64-bit value
+ *
+ * @jama_func_req_id 8218616
+ *
+ * This macro will fetch the Most significant word (lower 32-bits)
+ * from a 64-bit value.
+ *
+ * @param[in] _x_ 64-bit value
+ *
+ * @result Most significant word (upper 32-bits)
+ */
+#define HI32(_x_)               ((uint32_t)(((_x_) >> 32U) & 0xFFFFFFFFU))
+
+/**
+ * @brief Fetch the Least Significant Word from 64-bit value
+ *
+ * @jama_func_req_id 8218625
+ *
+ * This macro will fetch the Most significant word (upper 32-bits)
+ * from a 64-bit value.
+ *
+ * @param[in] _x_ 64-bit value
+ *
+ * @result Least significant word (lower 32-bits)
+ */
+#define LOW32(_x_)              ((uint32_t)((_x_) & 0xFFFFFFFFU))
+
+/*!
+ * @brief Utility functions to set/clear/test a bit in a bitmap.
+ * The bitmap is an array, allowing it to support more than 64 bits.
+ */
+
+/*!
+ * @brief The type used for each element of a bitmap.
+ * Note: Ideally we would use uintptr_t here to match the word size of this architecture.
+ * However, This requires us to do
+ *    #define BITMAP_ELEMENT_SIZE (sizeof(bitmap_element_t) * 8U)
+ * And this causes a CERT-C ARR39-C. Because of this, we have to fix it at 64 bits.
+ */
+typedef uint64_t bitmap_element_t;
+
+/*!
+ * @brief Number of bits per array element of _mpuEnableBitmap.
+ */
+#define BITMAP_ELEMENT_SIZE 64U
+
+/*!
+ * @brief Utility functions to set/clear/test a bit in a bitmap
+ *
+ * @param bm the bitmap in which to set/clear/test a bit
+ * @param index the index of the bit to set/clear/test
+ *
+ * @note It is up to the caller to ensure that index is within the bounds of bm.
+ *      bm must be at least the size of index / BITMAP_ELEMENT_SIZE.
+ */
+
+/**
+ * @brief set a bit in a bitmap
+ *
+ * @jama_func_req_id TODO
+ *
+ * This function will set a bit at position index in a bitmap spanning an array.
+ *
+ * @param bm the bitmap in which to set a bit
+ * @param index the index of the bit to set
+ */
+static inline void bitmap_set_bit(bitmap_element_t bm[], uint32_t bm_size, uint32_t index)
+{
+    if ((index / BITMAP_ELEMENT_SIZE) < bm_size)
+    {
+        bm[index / BITMAP_ELEMENT_SIZE] |=
+                (bitmap_element_t)((bitmap_element_t)1U << (index % BITMAP_ELEMENT_SIZE));
+    }
+}
+
+/**
+ * @brief clear a bit in a bitmap
+ *
+ * @jama_func_req_id TODO
+ *
+ * This function will clear a bit at position index in a bitmap spanning an array.
+ *
+ * @param bm the bitmap in which to clear a bit
+ * @param index the index of the bit to clear
+ */
+static inline void bitmap_clear_bit(bitmap_element_t bm[], uint32_t bm_size,  uint32_t index)
+{
+    if ((index / BITMAP_ELEMENT_SIZE) < bm_size)
+    {
+        bm[index / BITMAP_ELEMENT_SIZE] &=
+                (bitmap_element_t)(~((bitmap_element_t)1U << (index % BITMAP_ELEMENT_SIZE)));
+    }
+}
+
+/**
+ * @brief test a bit in a bitmap
+ *
+ * @jama_func_req_id TODO
+ *
+ * This function will test a bit at position index in a bitmap spanning an array.
+ *
+ * @param bm the bitmap in which to test a bit
+ * @param index the index of the bit to test
+ *
+ * @result True if the bit is set, False otherwise
+ */
+static inline bool bitmap_test_bit(const bitmap_element_t bm[], uint32_t bm_size, uint32_t index)
+{
+    bool ret = false;
+    if ((index / BITMAP_ELEMENT_SIZE) < bm_size)
+    {
+        ret = (((bm[index / BITMAP_ELEMENT_SIZE] >> (index % BITMAP_ELEMENT_SIZE)) & 1U) == 1U);
+    }
+
+    return ret;
+}
+
+#if __GNUC__ > 0
+#define HAS_BUILTIN_CTZ         1
+#else
+    #if __has_builtin(__builtin_ctz)
+    #define HAS_BUILTIN_CTZ     1
+    #else
+    #define HAS_BUILTIN_CTZ     0
+    #endif
+#endif
+
+/**
+ * @brief Compute the set bit index from the least significant bit
+ *
+ * @jama_func_req_id 8218484
+ *
+ * This function will fetch the bit index of the set bit from the LSB. In
+ * other words, counts the number of trailing zeroes.
+ *
+ * @param[in] value 32-bit value
+ *
+ * @return number of trailing zeroes or index of the bit set from LSB
+ */
+static inline uint32_t bit_number(uint32_t value)
+{
+#if HAS_BUILTIN_CTZ == 1
+        int32_t ret;
+        uint32_t n = 0;
+	INLINE_RFD(MISRA, DEVIATE, Directive_4_6, "Approval: Bug 200543266, DR: SWE-FSP-003-SWSADR.docx")
+        ret = (int32_t)__builtin_ctz((unsigned int)value);
+        if (ret > 0) {
+                n = (uint32_t)ret;
+        }
+
+        return n;
+#else
+
+        uint32_t lsb_only = value & ~(value - 1U);
+        uint32_t n = 0;
+
+        if (lsb_only == 0U)
+                n += 32U;
+        if ((lsb_only & 0xffff0000U) != 0U)
+                n += 16U;
+        if ((lsb_only & 0xff00ff00U) != 0U)
+                n += 8U;
+        if ((lsb_only & 0xf0f0f0f0U) != 0U)
+                n += 4U;
+        if ((lsb_only & 0xccccccccU) != 0U)
+                n += 2U;
+        if ((lsb_only & 0xaaaaaaaaU) != 0U)
+                n += 1U;
+
+        return n;
+#endif
+}
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+                MISRA, DEVIATE, Rule_15_4, "Approval: Bug 200532006, DR: SWE-FSP-029-SWSADR.docx")
+static inline uint32_t next_bit(
+        uint32_t firstbit,
+        uint32_t nbits,
+        const uint32_t words[],
+        uint32_t invert)
+{
+        uint32_t word;
+        uint32_t lsb_only;
+        uint32_t fbit = firstbit;
+        uint32_t ret;
+
+        for (;;) {
+                if (fbit >= nbits) {
+                        ret = nbits;
+                        goto out;
+                }
+
+                word = words[fbit / 32U] ^ invert;
+
+                /* Mask before firstbit */
+                word &= (uint32_t)(~((1UL << (fbit % 32UL)) - 1UL));
+
+                if (word != 0U) {
+                        break;
+                }
+
+                fbit = (fbit + 32U) & ~31U;
+        }
+
+        lsb_only = word & ~(word - 1U);
+
+        fbit = (fbit & ~31U) + bit_number(lsb_only);
+
+        if (fbit >= nbits) {
+                ret = nbits;
+                INLINE_RFD(MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx");
+                goto out;
+        }
+
+        ret = fbit;
+
+out:
+        return ret;
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_15_1, "Approval: Bug 3176459, DR: SWE-FSP-028-SWSADR.docx",
+              MISRA, DEVIATE, Rule_15_4, "Approval: Bug 200532006, DR: SWE-FSP-029-SWSADR.docx")
+
+static inline uint32_t next_one(
+        uint32_t firstbit,
+        uint32_t nbits,
+        const uint32_t words[])
+{
+        return next_bit(firstbit, nbits, words, 0U);
+}
+
+static inline uint32_t next_zero(
+        uint32_t firstbit,
+        uint32_t nbits,
+        const uint32_t words[])
+{
+        return next_bit(firstbit, nbits, words, ~0U);
+}
+
+/**
+ * @brief create a 64-bit value from MSW & LSW
+ *
+ * @jama_func_req_id 8218523
+ *
+ * This function creates the 64-bit value resulting from the MSW(upper 32-bit)
+ * and LSW(lower 32-bit) values.
+ *
+ * @param[in] hi32 upper 32-bit value
+ * @param[in] lo32 lower 32-bit value
+ *
+ * @result - 64-bit value resulting from the MSW and LSW
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_19_2, "Approval: Bug 200543136, DR: SWE-FSP-033-SWSADR.docx")
+static inline uint64_t hilo_to_64(
+        uint32_t hi32,
+        uint32_t lo32)
+{
+#if defined(__BYTE_ORDER__)
+        union {
+                struct {
+#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
+                        uint32_t lo32, hi32;
+#else
+                        uint32_t hi32, lo32;
+#endif
+                } value32;
+                uint64_t value64;
+        } value = { .value32 = { .hi32 = hi32, .lo32 = lo32 }};
+
+        return value.value64;
+#else
+        return ((uint64_t)hi32 << 32) | lo32;
+#endif
+}
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_19_2, "Approval: Bug 200543136, DR: SWE-FSP-033-SWSADR.docx")
+
+#endif
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              CERTC, DEVIATE, DCL37_C, "Approval:  Bug 2731179, DR: SWE-FSP-036-SWSADR.docx")
+#endif /* MISC__BITOPS_H */
diff --git a/spe-freertos-bsp/fsp/source/include/misc/ct-assert.h b/spe-freertos-bsp/fsp/source/include/misc/ct-assert.h
new file mode 100644
index 0000000..9897609
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/misc/ct-assert.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef MISC__CT_ASSERT_H
+#define MISC__CT_ASSERT_H
+
+/*
+ * Compile time assertion check
+ *
+ * If the asserted condition fails, it will result in a compilation error
+ * due to the fact that a boolean condition that is false will be 0 which
+ * results in a division by 0 (as seen by the compiler).
+ */
+#ifndef __ASSEMBLER__
+
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+_Pragma("coverity compliance block(include) \
+         (deviate MISRA_C_2012_Rule_20_10 \"Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx\") \
+         (deviate MISRA_C_2012_Rule_2_5 \"Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx\")")
+#endif
+#define DO_CT_CONCAT(_x_, _y_)    _x_##_y_
+#define CT_CONCAT(_a_, _b_)     DO_CT_CONCAT(_a_, _b_)
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+_Pragma("coverity compliance end_block(include) MISRA_C_2012_Rule_20_10")
+#endif
+
+#ifdef USE_C11
+#define CT_ASSERT(_cond_, _msg_)    _Static_assert(_cond_, _msg_);
+#else
+#define CT_ASSERT(_cond_, _msg_)                                                    \
+    enum { CT_CONCAT(ASSERT_LINE_, __COUNTER__) = 1/(int)(!!(_cond_)) };
+#endif // USE_C11
+
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+_Pragma("coverity compliance end_block(include) MISRA_C_2012_Rule_2_5")
+#endif
+#else
+
+#define CT_ASSERT(_cond_, _msg_)
+
+#endif // __ASSEMBLER__
+
+#define HEADER_CHECK(x) CT_ASSERT(x, "Header file missing or invalid.")
+
+#endif // MISC__CT_ASSERT_H
diff --git a/spe-freertos-bsp/fsp/source/include/misc/gcc_attrs.h b/spe-freertos-bsp/fsp/source/include/misc/gcc_attrs.h
new file mode 100644
index 0000000..8b831cb
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/misc/gcc_attrs.h
@@ -0,0 +1,91 @@
+/**
+ * @file gcc_attrs.h
+ *
+ * @brief GCC attribute macros
+ *
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS`` AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef MISC__GCC_ATTRS_H
+#define MISC__GCC_ATTRS_H
+#define FSP__MISC__GCC_ATTRS_H                         1
+
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+_Pragma("coverity compliance block(include) \
+         (deviate MISRA_C_2012_Rule_2_5 \"Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx\")")
+#endif
+
+/*
+ * GCC Attributes
+ * Defines macros for GCC attributes
+ */
+
+/*
+ * Common attributes
+ */
+#define GCC_ATTR_ALIGNED(X)                        __attribute__((aligned((X))))
+#define GCC_ATTR_SECTION(X)                        __attribute__((section((X))))
+#define GCC_ATTR_UNUSED                            __attribute__((unused))
+#define GCC_ATTR_USED                              __attribute__((used))
+#define GCC_ATTR_VISIBILITY_HIDDEN                 __attribute__((visibility("hidden")))
+#define GCC_ATTR_VISIBILITY_INTERNAL               __attribute__((visibility("internal")))
+#define GCC_ATTR_VISIBILITY_PROTECTED              __attribute__((visibility("protected")))
+#define GCC_ATTR_WEAK                              __attribute__((weak))
+
+/*
+ * Function only attributes
+ */
+#define GCC_ATTR_ALWAYSINLINE                      __attribute__((always_inline))
+#define GCC_ATTR_FORMAT_ARG(Idx)                   __attribute__((format_arg((Idx))))
+#define GCC_ATTR_FORMAT_PRINTF(Idx, firstToCheck)  __attribute__((format(printf, (Idx), (firstToCheck))))
+#define GCC_ATTR_NAKED                             __attribute__((naked))
+#define GCC_ATTR_NOINLINE                          __attribute__((noinline))
+#define GCC_ATTR_NONNULL(...)                      __attribute__((nonnull(__VA_ARGS__)))
+#define GCC_ATTR_NONNULL_ALL                       __attribute__((nonnull))
+#define GCC_ATTR_NORETURN                          __attribute__((noreturn))
+#define GCC_ATTR_PURE                              __attribute__((pure))
+#define GCC_ATTR_WARN_UNUSED                       __attribute__((warn_unused_result))
+#define GCC_ATTR_NO_SSP                            __attribute__((__optimize__("no-stack-protector")))
+
+/*
+ * Variable only attributes
+ */
+#define GCC_ATTR_CLEANUP(cleanupFcn)               __attribute__((cleanup((cleanupFcn))))
+#define GCC_ATTR_PACKED                            __attribute__((packed))
+
+/*
+ * Misc attributes
+ */
+#define GCC_ATTR_FALLTHROUGH                       __attribute__((fallthrough))
+
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+_Pragma("coverity compliance end_block(include) \
+         MISRA_C_2012_Rule_20_10 MISRA_C_2012_Rule_2_5")
+#endif
+
+#endif /* MISC__GCC_ATTRS_H */
+/** end of file **/
diff --git a/spe-freertos-bsp/fsp/source/include/misc/gcc_builtins.h b/spe-freertos-bsp/fsp/source/include/misc/gcc_builtins.h
new file mode 100644
index 0000000..94331e3
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/misc/gcc_builtins.h
@@ -0,0 +1,56 @@
+/**
+ * @file gcc_builtins.h
+ *
+ * @brief GCC builtin macros
+ *
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in the
+ *   documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS`` AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef MISC__GCC_BUILTINS_H
+#define MISC__GCC_BUILTINS_H
+#define FSP__MISC__GCC_BUILTINS_H                         1
+
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+_Pragma("coverity compliance block(include) \
+         (deviate MISRA_C_2012_Rule_2_5 \"Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx\")")
+#endif
+
+/*
+ * GCC Builtins
+ * Defines macros for GCC builtin functions
+ */
+
+#define NVRV_BUILTIN_OFFSETOF(type, member) __builtin_offsetof(type, member)
+#define NVRV_BUILTIN_UNREACHABLE            __builtin_unreachable
+
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+_Pragma("coverity compliance end_block(include) \
+         MISRA_C_2012_Rule_20_10 MISRA_C_2012_Rule_2_5")
+#endif
+
+#endif /* MISC__GCC_BUILTINS_H */
+/** end of file **/
diff --git a/spe-freertos-bsp/fsp/source/include/misc/generate-asm-hdr.h b/spe-freertos-bsp/fsp/source/include/misc/generate-asm-hdr.h
new file mode 100644
index 0000000..4d3fe68
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/misc/generate-asm-hdr.h
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * This file provides the interfaces for the SafeRTOS MPU functions for
+ * ARMv7 CPUs (notably the Cortex R5)
+ */
+#ifndef MISC__GENERATE_ASM_HDR_H
+#define MISC__GENERATE_ASM_HDR_H
+#define FSP__MISC__GENERATE_ASM_HDR_H   1
+
+/* Compiler headers */
+#include <stddef.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/**
+ * @file generate-asm-hdr.h
+ * @brief Generate C/asm data structure member offset defines.
+ *
+ * This file provides macros for generating data structure member
+ * offset defines that are used in both C source and assembly for
+ * the purpose of maintaining the offsets of the members.
+ */
+
+#define ASM_DEFINE(_s_, _v_)                                                  \
+    __asm__ __volatile__ ("##define " #_s_ " %0 \n" : : "i" (_v_))
+
+#define ASM_OFFSET(_sym_, _struct_, _member_)                                 \
+    ASM_DEFINE(_sym_, offsetof(_struct_, _member_))
+
+#define ASM_SIZEOF(_sym_, _struct_)                                           \
+    ASM_DEFINE(_sym_, sizeof(_struct_))
+
+#endif /* MISC__GENERATE_ASM_HDR_H */
diff --git a/spe-freertos-bsp/fsp/source/include/misc/linker-symbols.h b/spe-freertos-bsp/fsp/source/include/misc/linker-symbols.h
new file mode 100644
index 0000000..02e63f6
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/misc/linker-symbols.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2018-2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef MISC__LINKER_SYMBOLS_H
+#define MISC__LINKER_SYMBOLS_H
+#define FSP__MISC__LINKER_SYMBOLS_H                     1
+
+#include <misc/macros.h>
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_20_10, "Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#if (!defined(USE_GCC) || (USE_GCC==0))
+#define LINKER_SYM(_prefix_, _name_, _postfix_)                                 \
+        _prefix_##$$##_name_##$$##_postfix_
+#else
+#define LINKER_SYM(_prefix_, _name_, _postfix_)                                 \
+        _prefix_##_##_name_##_##_postfix_
+#endif
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_20_10, "Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx")
+
+#define LOAD_SYM_BASE(_name_)           LINKER_SYM(Load, _name_, Base)
+#define LOAD_SYM_LIMIT(_name_)          LINKER_SYM(Load, _name_, Limit)
+#define IMAGE_SYM_BASE(_name_)          LINKER_SYM(Image, _name_, Base)
+#define IMAGE_SYM_LIMIT(_name_)         LINKER_SYM(Image, _name_, Limit)
+#define IMAGE_SYM_LENGTH(_name_)        LINKER_SYM(Image, _name_, Length)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/misc/macros.h b/spe-freertos-bsp/fsp/source/include/misc/macros.h
new file mode 100644
index 0000000..d43181d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/misc/macros.h
@@ -0,0 +1,356 @@
+/*
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef MISC__MACROS_H
+#define MISC__MACROS_H
+#define FSP__MISC__MACROS_H                             1
+
+#ifndef __ASSEMBLER__
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+#endif
+
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+_Pragma("coverity compliance block(include) \
+        (deviate MISRA_C_2012_Rule_2_5 \"Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx\") \
+        (deviate MISRA_C_2012_Rule_20_10 \"Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx\") \
+        (deviate CERT_DCL37_C  \"Approval:  Bug 2731179, DR: SWE-FSP-036-SWSADR.docx\")")
+#endif
+/*
+ * Create wrappers for Coverity MISRA/CERTC _Pragma
+ *   inline block deviation records.  Feature is enabled in makefile with
+ *   FSP_COVERITY=1, or by passing FSP_COVERITY=1 on the command line to
+ *   the makefile.
+ */
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+  #define MISRA_Pragma(_p_) _Pragma(_p_)
+  #define TO_MISRA_Pragma(_a_) MISRA_Pragma(STR(_a_))
+  #define MISRA_START_DEVIATE(_r_, _d_) (CONCAT(deviate MISRA_C_2012_,_r_ _d_))
+  #define CERTC_START_DEVIATE(_r_, _d_) (CONCAT(deviate CERT_,_r_ _d_))
+  #define MISRA_START_FP(_r_, _d_) (CONCAT(false_positive MISRA_C_2012_,_r_ _d_))
+  #define CERTC_START_FP(_r_, _d_) (CONCAT(false_positive CERT_,_r_ _d_))
+  #define MISRA_END_DEVIATE(_r_, _d_) CONCAT(MISRA_C_2012_,_r_)
+  #define CERTC_END_DEVIATE(_r_, _d_) CONCAT(CERT_,_r_)
+
+  #define INLINE_RFD_SELECTOR(_c1_, _t1_, _r1_, _d1_, \
+                              _c2_, _t2_, _r2_, _d2_, \
+                              _c3_, _t3_, _r3_, _d3_, \
+                              _c4_, _t4_, _r4_, _d4_, \
+                              _c5_, _t5_, _r5_, _d5_, \
+                              _c6_, _t6_, _r6_, _d6_, \
+                              _c7_, _t7_, _r7_, _d7_, \
+                              _c8_, _t8_, _r8_, _d8_, \
+                              FUNC, ...) FUNC
+  #define INLINE_RFD_CHOOSER(...) \
+            INLINE_RFD_SELECTOR(__VA_ARGS__, INLINE_RFDx8,,,, \
+                                             INLINE_RFDx7,,,, \
+                                             INLINE_RFDx6,,,, \
+                                             INLINE_RFDx5,,,, \
+                                             INLINE_RFDx4,,,, \
+                                             INLINE_RFDx3,,,, \
+                                             INLINE_RFDx2,,,, \
+                                             INLINE_RFDx1, )
+  #define START_RFD_BLOCK_CHOOSER(...) \
+            INLINE_RFD_SELECTOR(__VA_ARGS__, START_RFD_BLOCKx8,,,, \
+                                             START_RFD_BLOCKx7,,,, \
+                                             START_RFD_BLOCKx6,,,, \
+                                             START_RFD_BLOCKx5,,,, \
+                                             START_RFD_BLOCKx4,,,, \
+                                             START_RFD_BLOCKx3,,,, \
+                                             START_RFD_BLOCKx2,,,, \
+                                             START_RFD_BLOCKx1, )
+  #define END_RFD_BLOCK_CHOOSER(...) \
+            INLINE_RFD_SELECTOR(__VA_ARGS__, END_RFD_BLOCKx8,,,, \
+                                             END_RFD_BLOCKx7,,,, \
+                                             END_RFD_BLOCKx6,,,, \
+                                             END_RFD_BLOCKx5,,,, \
+                                             END_RFD_BLOCKx4,,,, \
+                                             END_RFD_BLOCKx3,,,, \
+                                             END_RFD_BLOCKx2,,,, \
+                                             END_RFD_BLOCKx1, )
+  #define INLINE_RFD(...) INLINE_RFD_CHOOSER(__VA_ARGS__)(__VA_ARGS__)
+  #define START_RFD_BLOCK(...) START_RFD_BLOCK_CHOOSER(__VA_ARGS__)(__VA_ARGS__)
+  #define END_RFD_BLOCK(...) END_RFD_BLOCK_CHOOSER(__VA_ARGS__)(__VA_ARGS__)
+
+
+// Input:
+//   _c_:  Class:  MISRA, CERTC
+//   _t_:  Types:  DEVIATE, FP
+//   _r_:  Rule:   (e.g.) Rule_1_2, Directive_4_9, etc.
+//   _d_:  Description:  Text description including BUG number and RFD document name
+  #define INLINE_RFDx1(_c1_, _t1_, _r1_, _d1_) \
+                       TO_MISRA_Pragma(coverity compliance \
+                                                           _c1_##_START_##_t1_(_r1_,_d1_))
+  #define INLINE_RFDx2(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_) \
+                       TO_MISRA_Pragma(coverity compliance _c1_##_START_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_START_##_t2_(_r2_,_d2_))
+  #define INLINE_RFDx3(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                       _c3_, _t3_, _r3_, _d3_) \
+                       TO_MISRA_Pragma(coverity compliance _c1_##_START_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_START_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_START_##_t3_(_r3_,_d3_))
+  #define INLINE_RFDx4(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                       _c3_, _t3_, _r3_, _d3_, _c4_, _t4_, _r4_, _d4_) \
+                       TO_MISRA_Pragma(coverity compliance _c1_##_START_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_START_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_START_##_t3_(_r3_,_d3_) \
+                                                           _c4_##_START_##_t4_(_r4_,_d4_))
+  #define INLINE_RFDx5(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                       _c3_, _t3_, _r3_, _d3_, _c4_, _t4_, _r4_, _d4_, \
+                       _c5_, _t5_, _r5_, _d5_) \
+                       TO_MISRA_Pragma(coverity compliance _c1_##_START_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_START_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_START_##_t3_(_r3_,_d3_) \
+                                                           _c4_##_START_##_t4_(_r4_,_d4_) \
+                                                           _c5_##_START_##_t5_(_r5_,_d5_))
+  #define INLINE_RFDx6(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                       _c3_, _t3_, _r3_, _d3_, _c4_, _t4_, _r4_, _d4_, \
+                       _c5_, _t5_, _r5_, _d5_, _c6_, _t6_, _r6_, _d6_) \
+                       TO_MISRA_Pragma(coverity compliance _c1_##_START_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_START_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_START_##_t3_(_r3_,_d3_) \
+                                                           _c4_##_START_##_t4_(_r4_,_d4_) \
+                                                           _c5_##_START_##_t5_(_r5_,_d5_) \
+                                                           _c6_##_START_##_t6_(_r6_,_d6_))
+  #define INLINE_RFDx7(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                       _c3_, _t3_, _r3_, _d3_, _c4_, _t4_, _r4_, _d4_, \
+                       _c5_, _t5_, _r5_, _d5_, _c6_, _t6_, _r6_, _d6_, \
+                       _c7_, _t7_, _r7_, _d7_) \
+                       TO_MISRA_Pragma(coverity compliance _c1_##_START_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_START_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_START_##_t3_(_r3_,_d3_) \
+                                                           _c4_##_START_##_t4_(_r4_,_d4_) \
+                                                           _c5_##_START_##_t5_(_r5_,_d5_) \
+                                                           _c6_##_START_##_t6_(_r6_,_d6_) \
+                                                           _c7_##_START_##_t7_(_r7_,_d7_))
+  #define INLINE_RFDx8(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                       _c3_, _t3_, _r3_, _d3_, _c4_, _t4_, _r4_, _d4_, \
+                       _c5_, _t5_, _r5_, _d5_, _c6_, _t6_, _r6_, _d6_, \
+                       _c7_, _t7_, _r7_, _d7_, _c8_, _t8_, _r8_, _d8_) \
+                       TO_MISRA_Pragma(coverity compliance _c1_##_START_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_START_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_START_##_t3_(_r3_,_d3_) \
+                                                           _c4_##_START_##_t4_(_r4_,_d4_) \
+                                                           _c5_##_START_##_t5_(_r5_,_d5_) \
+                                                           _c6_##_START_##_t6_(_r6_,_d6_) \
+                                                           _c7_##_START_##_t7_(_r7_,_d7_) \
+                                                           _c8_##_START_##_t8_(_r8_,_d8_))
+  #define START_RFD_BLOCKx1(_c1_, _t1_, _r1_, _d1_) \
+                       TO_MISRA_Pragma(coverity compliance block(include) \
+                                                           _c1_##_START_##_t1_(_r1_,_d1_))
+  #define START_RFD_BLOCKx2(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_) \
+                       TO_MISRA_Pragma(coverity compliance block(include) \
+                                                           _c1_##_START_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_START_##_t2_(_r2_,_d2_))
+  #define START_RFD_BLOCKx3(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                            _c3_, _t3_, _r3_, _d3_) \
+                       TO_MISRA_Pragma(coverity compliance block(include) \
+                                                           _c1_##_START_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_START_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_START_##_t3_(_r3_,_d3_))
+  #define START_RFD_BLOCKx4(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                            _c3_, _t3_, _r3_, _d3_, _c4_, _t4_, _r4_, _d4_) \
+                       TO_MISRA_Pragma(coverity compliance block(include) \
+                                                           _c1_##_START_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_START_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_START_##_t3_(_r3_,_d3_) \
+                                                           _c4_##_START_##_t4_(_r4_,_d4_))
+  #define START_RFD_BLOCKx5(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                            _c3_, _t3_, _r3_, _d3_, _c4_, _t4_, _r4_, _d4_, \
+                            _c5_, _t5_, _r5_, _d5_) \
+                       TO_MISRA_Pragma(coverity compliance block(include) \
+                                                           _c1_##_START_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_START_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_START_##_t3_(_r3_,_d3_) \
+                                                           _c4_##_START_##_t4_(_r4_,_d4_) \
+                                                           _c5_##_START_##_t5_(_r5_,_d5_))
+  #define START_RFD_BLOCKx6(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                            _c3_, _t3_, _r3_, _d3_, _c4_, _t4_, _r4_, _d4_, \
+                            _c5_, _t5_, _r5_, _d5_, _c6_, _t6_, _r6_, _d6_) \
+                       TO_MISRA_Pragma(coverity compliance block(include) \
+                                                           _c1_##_START_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_START_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_START_##_t3_(_r3_,_d3_) \
+                                                           _c4_##_START_##_t4_(_r4_,_d4_) \
+                                                           _c5_##_START_##_t5_(_r5_,_d5_) \
+                                                           _c6_##_START_##_t6_(_r6_,_d6_))
+  #define START_RFD_BLOCKx7(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                            _c3_, _t3_, _r3_, _d3_, _c4_, _t4_, _r4_, _d4_, \
+                            _c5_, _t5_, _r5_, _d5_, _c6_, _t6_, _r6_, _d6_, \
+                            _c7_, _t7_, _r7_, _d7_) \
+                       TO_MISRA_Pragma(coverity compliance block(include) \
+                                                           _c1_##_START_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_START_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_START_##_t3_(_r3_,_d3_) \
+                                                           _c4_##_START_##_t4_(_r4_,_d4_) \
+                                                           _c5_##_START_##_t5_(_r5_,_d5_) \
+                                                           _c6_##_START_##_t6_(_r6_,_d6_) \
+                                                           _c7_##_START_##_t7_(_r7_,_d7_))
+  #define START_RFD_BLOCKx8(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                            _c3_, _t3_, _r3_, _d3_, _c4_, _t4_, _r4_, _d4_, \
+                            _c5_, _t5_, _r5_, _d5_, _c6_, _t6_, _r6_, _d6_, \
+                            _c7_, _t7_, _r7_, _d7_, _c8_, _t8_, _r8_, _d8_) \
+                       TO_MISRA_Pragma(coverity compliance block(include) \
+                                                           _c1_##_START_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_START_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_START_##_t3_(_r3_,_d3_) \
+                                                           _c4_##_START_##_t4_(_r4_,_d4_) \
+                                                           _c5_##_START_##_t5_(_r5_,_d5_) \
+                                                           _c6_##_START_##_t6_(_r6_,_d6_) \
+                                                           _c7_##_START_##_t7_(_r7_,_d7_) \
+                                                           _c8_##_START_##_t8_(_r8_,_d8_))
+  #define END_RFD_BLOCKx1(_c1_, _t1_, _r1_, _d1_) \
+                       TO_MISRA_Pragma(coverity compliance end_block(include) \
+                                                           _c1_##_END_##_t1_(_r1_,_d1_))
+  #define END_RFD_BLOCKx2(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_) \
+                       TO_MISRA_Pragma(coverity compliance end_block(include) \
+                                                           _c1_##_END_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_END_##_t2_(_r2_,_d2_))
+  #define END_RFD_BLOCKx3(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                          _c3_, _t3_, _r3_, _d3_) \
+                       TO_MISRA_Pragma(coverity compliance end_block(include) \
+                                                           _c1_##_END_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_END_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_END_##_t3_(_r3_,_d3_))
+  #define END_RFD_BLOCKx4(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                          _c3_, _t3_, _r3_, _d3_, _c4_, _t4_, _r4_, _d4_) \
+                       TO_MISRA_Pragma(coverity compliance end_block(include) \
+                                                           _c1_##_END_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_END_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_END_##_t3_(_r3_,_d3_) \
+                                                           _c4_##_END_##_t4_(_r4_,_d4_))
+  #define END_RFD_BLOCKx5(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                          _c3_, _t3_, _r3_, _d3_, _c4_, _t4_, _r4_, _d4_, \
+                          _c5_, _t5_, _r5_, _d5_) \
+                       TO_MISRA_Pragma(coverity compliance end_block(include) \
+                                                           _c1_##_END_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_END_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_END_##_t3_(_r3_,_d3_) \
+                                                           _c4_##_END_##_t4_(_r4_,_d4_) \
+                                                           _c5_##_END_##_t5_(_r5_,_d5_))
+  #define END_RFD_BLOCKx6(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                          _c3_, _t3_, _r3_, _d3_, _c4_, _t4_, _r4_, _d4_, \
+                          _c5_, _t5_, _r5_, _d5_, _c6_, _t6_, _r6_, _d6_) \
+                       TO_MISRA_Pragma(coverity compliance end_block(include) \
+                                                           _c1_##_END_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_END_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_END_##_t3_(_r3_,_d3_) \
+                                                           _c4_##_END_##_t4_(_r4_,_d4_) \
+                                                           _c5_##_END_##_t5_(_r5_,_d5_) \
+                                                           _c6_##_END_##_t6_(_r6_,_d6_))
+  #define END_RFD_BLOCKx7(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                          _c3_, _t3_, _r3_, _d3_, _c4_, _t4_, _r4_, _d4_, \
+                          _c5_, _t5_, _r5_, _d5_, _c6_, _t6_, _r6_, _d6_, \
+                          _c7_, _t7_, _r7_, _d7_) \
+                       TO_MISRA_Pragma(coverity compliance end_block(include) \
+                                                           _c1_##_END_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_END_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_END_##_t3_(_r3_,_d3_) \
+                                                           _c4_##_END_##_t4_(_r4_,_d4_) \
+                                                           _c5_##_END_##_t5_(_r5_,_d5_) \
+                                                           _c6_##_END_##_t6_(_r6_,_d6_) \
+                                                           _c7_##_END_##_t7_(_r7_,_d7_))
+  #define END_RFD_BLOCKx8(_c1_, _t1_, _r1_, _d1_, _c2_, _t2_, _r2_, _d2_, \
+                          _c3_, _t3_, _r3_, _d3_, _c4_, _t4_, _r4_, _d4_, \
+                          _c5_, _t5_, _r5_, _d5_, _c6_, _t6_, _r6_, _d6_, \
+                          _c7_, _t7_, _r7_, _d7_, _c8_, _t8_, _r8_, _d8_) \
+                       TO_MISRA_Pragma(coverity compliance end_block(include) \
+                                                           _c1_##_END_##_t1_(_r1_,_d1_) \
+                                                           _c2_##_END_##_t2_(_r2_,_d2_) \
+                                                           _c3_##_END_##_t3_(_r3_,_d3_) \
+                                                           _c4_##_END_##_t4_(_r4_,_d4_) \
+                                                           _c5_##_END_##_t5_(_r5_,_d5_) \
+                                                           _c6_##_END_##_t6_(_r6_,_d6_) \
+                                                           _c7_##_END_##_t7_(_r7_,_d7_) \
+                                                           _c8_##_END_##_t8_(_r8_,_d8_))
+#else
+  #define INLINE_RFD(...)
+  #define START_RFD_BLOCK(...)
+  #define END_RFD_BLOCK(...)
+#endif
+
+#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#define ARRAY_SSIZE(x) (int)(sizeof(x) / sizeof((x)[0]))
+
+#define SIZE_K(KB) (1024U * (KB))
+#define SIZE_M(MB) SIZE_K(1024U * (MB))
+
+#define DIV_ROUND_UP(x, y) (((x) + (y) - 1U) / (y))
+
+#define min(a, b) (((a) < (b)) ? (a) : (b))
+
+#define max(a, b) (((a) > (b)) ? (a) : (b))
+
+#define CONTAINER_OF(_ptr, _type, _field) \
+        (_type *)((char *)_ptr - offsetof(_type, _field))
+
+#ifndef U64_C
+#define U64_C(x) UINT64_C(x)
+#endif
+
+#ifndef U32_C
+#define U32_C(x) UINT32_C(x)
+#endif
+
+#ifndef U16_C
+#define U16_C(x) UINT16_C(x)
+#endif
+
+#ifndef U8_C
+#define U8_C(x) UINT8_C(x)
+#endif
+
+/* String concatenation */
+#define TO_STR(_s_)               #_s_
+#define STR(_string_)           TO_STR(_string_)
+
+#define DO_CONCAT(_x_, _y_)       _x_##_y_
+#define CONCAT(_a_, _b_)        DO_CONCAT(_a_, _b_)
+
+/* compiler specific section name for modules */
+#if defined(USE_GCC_SECTIONS) && (USE_GCC_SECTIONS == 1)
+#define SECTION_BUILDER(_name_, _type_) ._name_._type_
+#else
+#define SECTION_BUILDER(_name_, _type_) ._type_._name_
+#endif
+
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+_Pragma("coverity compliance end_block(include) \
+         MISRA_C_2012_Rule_2_5 MISRA_C_2012_Rule_20_10 CERT_DCL37_C")
+#endif
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/misc/math_secure.h b/spe-freertos-bsp/fsp/source/include/misc/math_secure.h
new file mode 100644
index 0000000..591bcf1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/misc/math_secure.h
@@ -0,0 +1,383 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef MISC__MATH_SECURE_H
+#define MISC__MATH_SECURE_H
+#define FSP__MISC__MATH_SECURE_H    1
+
+/* Compiler headers */
+#include <stdint.h>                 // for uint32_t, uint64_t, UINT32_MAX
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>         // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <debug/abort.h>            // for tegra_abort, FSP__DEBUG__ABORT_H
+#include <debug/abort-sys-codes.h>  // for ABORT_ASSERT, FSP__DEBUG__ABORT_S...
+#include <misc/attributes.h>        // for UNUSED, FSP__MISC__ATTRIBUTES_H
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ABORT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ABORT_SYS_CODES_H, "Header file missing or invalid.")
+
+/**
+ * @file fsp-math-secure.h
+ * @brief functions that provide secure arithmetic operations on unsigned
+ * types to ensure protection from wrapping.
+ */
+
+/**
+ * Note: This minimalistic library is only useful for detecting and protecting
+ * against overflow and not for a specific maxmum value.
+ */
+
+/**
+ * @brief overflow action modes
+ *
+ * @macro-title Overflow Action Modes
+ */
+#define OVERFLOW_ACTION_0       0U
+#define OVERFLOW_ACTION_MAX     1U
+#define OVERFLOW_ACTION_VAL     2U
+#define OVERFLOW_ACTION_ABORT   3U
+#define OVERFLOW_ACTION_MODES   4U
+
+/**
+ * @brief error codes for overflow
+ *
+ * @macro-title Error Codes for Unsigned 32-bit Overflow
+ */
+#define E_UNSIGNED_OVERFLOW     MODULE_ERROR_VAL(SMATH, 0UL)
+
+typedef uint32_t overflow_action_t;
+typedef uint64_t overflow_action64_t;
+
+/**
+ * @brief overflow action function
+ *
+ * This is used to define the overflow action function that can be
+ * is called when a user specifies an overflow action mode.
+ *
+ * @param[in] val value that resulted in an overflow
+ *
+ * @return 32-bit unsigned value
+ */
+typedef uint32_t (overflow_action)(uint32_t val);
+typedef uint64_t (overflow_action64)(uint64_t val);
+
+/**
+ * @brief returns 0 when an overflow occurs
+ *
+ * This is used to return 0 when an overflow occurs.
+ *
+ * @param[in] val resulting value of an operation that caused the wrap/overflow
+ *
+ * @return zero
+ */
+static inline uint32_t action_overflow_0(uint32_t val)
+{
+    UNUSED(val);
+
+    return 0U;
+}
+
+/**
+ * @brief returns the max value when an overflow occurs
+ *
+ * This is used to return the max uint32_t value when an overflow occurs.
+ *
+ * @param[in] val resulting value of an operation that caused the wrap/overflow
+ *
+ * @return uint32_t max value
+ */
+static inline uint32_t action_overflow_max(uint32_t val)
+{
+    UNUSED(val);
+
+    return UINT32_MAX;
+}
+
+/**
+ * @brief returns the overflown value when an overflow occurs
+ *
+ * This is used to return the actual resulting value after the overflow.
+ *
+ * @param[in] val resulting value of an operation that caused the wrap/overflow
+ *
+ * @return overflown value
+ */
+static inline uint32_t action_overflow_val(uint32_t val)
+{
+    return val;
+}
+
+/**
+ * @brief abort when an overflow occurs
+ *
+ * This is used to abort the execution when an overflow is detected
+ * and abort is specified as the resultant action of that.
+ *
+ * @param[in] val resulting value of an operation that caused the wrap/overflow
+ *
+ * @return none
+ */
+static inline uint32_t action_overflow_abort(uint32_t val)
+{
+    UNUSED(val);
+
+    tegra_abort(ABORT_ASSERT, E_UNSIGNED_OVERFLOW);
+
+    return 0U;
+}
+
+static overflow_action *const overflow_actions[OVERFLOW_ACTION_MODES] = {
+    [OVERFLOW_ACTION_0]     =   &action_overflow_0,
+    [OVERFLOW_ACTION_MAX]   =   &action_overflow_max,
+    [OVERFLOW_ACTION_VAL]   =   &action_overflow_val,
+    [OVERFLOW_ACTION_ABORT] =   &action_overflow_abort,
+};
+
+/**
+ * @brief returns 0 when an overflow occurs
+ *
+ * This is used to return 0 when an overflow occurs.
+ *
+ * @param[in] val resulting value of an operation that caused the wrap/overflow
+ *
+ * @return zero
+ */
+static inline uint64_t action_overflow64_0(uint64_t val)
+{
+    UNUSED(val);
+
+    return 0U;
+}
+
+/**
+ * @brief returns the max value when an overflow occurs
+ *
+ * This is used to return the max uint64_t value when an overflow occurs.
+ *
+ * @param[in] val resulting value of an operation that caused the wrap/overflow
+ *
+ * @return uint64_t max value
+ */
+static inline uint64_t action_overflow64_max(uint64_t val)
+{
+    UNUSED(val);
+
+    return UINT64_MAX;
+}
+
+/**
+ * @brief returns the overflown value when an overflow occurs
+ *
+ * This is used to return the actual resulting value after the overflow.
+ *
+ * @param[in] val resulting value of an operation that caused the wrap/overflow
+ *
+ * @return overflown value
+ */
+static inline uint64_t action_overflow64_val(uint64_t val)
+{
+    return val;
+}
+
+/**
+ * @brief abort when an overflow occurs
+ *
+ * This is used to abort the execution when an overflow is detected
+ * and abort is specified as the resultant action of that.
+ *
+ * @param[in] val resulting value of an operation that caused the wrap/overflow
+ *
+ * @return none
+ */
+static inline uint64_t action_overflow64_abort(uint64_t val)
+{
+    UNUSED(val);
+
+    tegra_abort(ABORT_ASSERT, E_UNSIGNED_OVERFLOW);
+
+    return 0U;
+}
+
+static overflow_action64 *const overflow_actions64[OVERFLOW_ACTION_MODES] = {
+    [OVERFLOW_ACTION_0]     =   &action_overflow64_0,
+    [OVERFLOW_ACTION_MAX]   =   &action_overflow64_max,
+    [OVERFLOW_ACTION_VAL]   =   &action_overflow64_val,
+    [OVERFLOW_ACTION_ABORT] =   &action_overflow64_abort,
+};
+
+/**
+ * @brief securely cast an unsigned 32-bit to unsigned 8-bit
+ *
+ * This is used to securely cast an unsigned 32-bit number to 8-bit
+ * number by taking care of wrapping.
+ *
+ * @param[in] a unsigned 32-bit number
+ *
+ * @return unsigned 8-bit number
+ */
+static inline uint8_t scast_u32_to_u8(uint32_t a)
+{
+    return (a > (uint32_t)UINT8_MAX) ? 0U : (uint8_t)a;
+}
+
+/**
+ * @brief securely cast an unsigned 64-bit to unsigned 64-bit
+ *
+ * This is used to securely cast an unsigned 64-bit number to 32-bit
+ * number by taking care of wrapping.
+ *
+ * @param[in] a unsigned 64-bit number
+ *
+ * @return unsigned 32-bit number
+ */
+static inline uint32_t scast_u64_to_u32(uint64_t a)
+{
+    return (a > (uint64_t)UINT32_MAX) ? 0U : (uint32_t)a;
+}
+
+/**
+ * @brief secure addition of unsigned 32-bit numbers
+ *
+ * This is used to add unsigned 32 bit numbers by taking care of
+ * wrapping using postcondition test solution.
+ *
+ * @param[in] a operand1
+ * @param[in] b operand2
+ *
+ * @return sum of the 2 params passed or 0 if wrapped
+ */
+static inline uint32_t sadd_u32(uint32_t a, uint32_t b, overflow_action_t action)
+{
+    uint32_t sum = a + b;
+
+    return (sum >= a) ? sum : overflow_actions[action](sum);
+}
+
+/**
+ * @brief secure substraction of unsigned 32-bits
+ *
+ * This is used to substract unsigned 32 bit numbers by taking care
+ * of wrapping.
+ *
+ * @param[in] a operand1
+ * @param[in] b operand2
+ *
+ * @return  diff of the 2 params passed or 0 if wrapped
+ */
+static inline uint32_t ssub_u32(uint32_t a, uint32_t b, overflow_action_t action)
+{
+    return (a > b) ? (a - b) : overflow_actions[action](a - b);
+}
+
+/**
+ * @brief secure multiplication of unsigned 32-bits
+ *
+ * This is used to multiply unsigned 32 bit numbers by taking care
+ * of wrapping.
+ *
+ * @param[in] a operand1
+ * @param[in] b operand2
+ *
+ * @return product of the 2 params passed or 0 if wrapped
+ */
+static inline uint32_t smul_u32(uint32_t a, uint32_t b, overflow_action_t action)
+{
+    uint32_t res = 0U;
+
+    if ((a == 0U) || (b == 0U)) {
+        goto out;
+    }
+
+    res = (a < (UINT32_MAX / b)) ? (a * b) : overflow_actions[action](a * b);
+
+out:
+    return res;
+}
+
+/**
+ * @brief secure addition of unsigned 64-bit numbers
+ *
+ * This is used to add unsigned 64 bit numbers by taking care of
+ * wrapping using postcondition test solution.
+ *
+ * @param[in] a operand1
+ * @param[in] b operand2
+ *
+ * @return sum of the 2 params passed or 0 if wrapped
+ */
+static inline uint64_t sadd_u64(uint64_t a, uint64_t b, overflow_action64_t action)
+{
+    uint64_t sum = a + b;
+
+    return (sum >= a) ? sum : overflow_actions[action](sum);
+}
+
+/**
+ * @brief secure substraction of unsigned 64-bits
+ *
+ * This is used to substract unsigned 64 bit numbers by taking care
+ * of wrapping.
+ *
+ * @param[in] a operand1
+ * @param[in] b operand2
+ *
+ * @return  diff of the 2 params passed or 0 if wrapped
+ */
+static inline uint64_t ssub_u64(uint64_t a, uint64_t b, overflow_action64_t action)
+{
+    return (a > b) ? (a - b) : overflow_actions[action](a - b);
+}
+
+/**
+ * @brief secure multiplication of unsigned 64-bits
+ *
+ * This is used to multiply unsigned 64 bit numbers by taking care
+ * of wrapping.
+ *
+ * @param[in] a operand1
+ * @param[in] b operand2
+ *
+ * @return product of the 2 params passed or 0 if wrapped
+ */
+static inline uint64_t smul_u64(uint64_t a, uint64_t b, overflow_action64_t action)
+{
+    uint64_t res = 0U;
+
+    if ((a == 0U) || (b == 0U)) {
+        goto out;
+    }
+
+    res = (a < (UINT64_MAX / b)) ? (a * b) : overflow_actions[action](a * b);
+
+out:
+    return res;
+}
+
+#endif /* FSP__MISC__MATH_SECURE_H */
diff --git a/spe-freertos-bsp/fsp/source/include/misc/nvmisc_drf.h b/spe-freertos-bsp/fsp/source/include/misc/nvmisc_drf.h
new file mode 100644
index 0000000..17ec096
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/misc/nvmisc_drf.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright 2020-21 NVIDIA Corporation.  All Rights Reserved.
+ *
+ * NVIDIA Corporation and its licensors retain all intellectual property and
+ * proprietary rights in and to this software and related documentation.  Any
+ * use, reproduction, disclosure or distribution of this software and related
+ * documentation without an express license agreement from NVIDIA Corporation
+ * is strictly prohibited.
+ */
+
+/*
+ * NOTE: Intended for use with NVGPU-style manuals. Not garunteed to work
+ * with other manual styles.
+ */
+
+#ifndef MISC__NVRM_DRF_H
+#define MISC__NVRM_DRF_H
+#define FSP__MISC__NVMISC_DRF_H                         1
+
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+_Pragma("coverity compliance block(include) \
+         (deviate MISRA_C_2012_Rule_20_10 \"Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx\") \
+         (deviate MISRA_C_2012_Rule_2_5 \"Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx\")")
+#endif
+
+#include <stdint.h>
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// Bit Macros
+//
+///////////////////////////////////////////////////////////////////////////////
+#define LOWESTBIT(x)                 ((x) &  (((x) - 1U) ^ (x)))
+
+// Index of the 'on' bit (assuming that there is only one).
+// Even if multiple bits are 'on', result is in range of 0-31.
+//
+// Use an inline function here. Using a macro causes
+// issues with code coverage since we cannot always hit the 5
+// conditionals in the macro implmentation.
+static inline uint8_t BIT_IDX_32(uint32_t n)
+{
+   return ((((n) & 0xFFFF0000U) != 0U) ? 0x10U: 0U) |
+            ((((n) & 0xFF00FF00U) != 0U) ? 0x08U: 0U) |
+            ((((n) & 0xF0F0F0F0U) != 0U) ? 0x04U: 0U) |
+            ((((n) & 0xCCCCCCCCU) != 0U) ? 0x02U: 0U) |
+            ((((n) & 0xAAAAAAAAU) != 0U) ? 0x01U: 0U);
+}
+
+
+// Index of the 'on' bit (assuming that there is only one).
+// Even if multiple bits are 'on', result is in range of 0-63.
+static inline uint8_t BIT_IDX_64(uint64_t n)
+{
+    return ((((n) & 0xFFFFFFFF00000000ULL) != 0U) ? 0x20U: 0U) |
+            ((((n) & 0xFFFF0000FFFF0000ULL) != 0U) ? 0x10U: 0U) |
+            ((((n) & 0xFF00FF00FF00FF00ULL) != 0U) ? 0x08U: 0U) |
+            ((((n) & 0xF0F0F0F0F0F0F0F0ULL) != 0U) ? 0x04U: 0U) |
+            ((((n) & 0xCCCCCCCCCCCCCCCCULL) != 0U) ? 0x02U: 0U) |
+            ((((n) & 0xAAAAAAAAAAAAAAAAULL) != 0U) ? 0x01U: 0U);
+}
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// Alignment Macros
+//
+///////////////////////////////////////////////////////////////////////////////
+#ifndef NV_ALIGN_DOWN
+#define NV_ALIGN_DOWN(v, gran)                 ((v) & ~((gran) - 1U))
+#endif
+
+#ifndef NV_ALIGN_UP
+#define NV_ALIGN_UP(v, gran)                   (((v) + ((gran) - 1U)) & ~((gran) - 1U))
+#endif
+
+#ifndef NV_ALIGN_DOWN64
+#define NV_ALIGN_DOWN64(v, gran)               ((v) & ~(((uint64_t)gran) - 1U))
+#endif
+
+#ifndef NV_ALIGN_UP64
+#define NV_ALIGN_UP64(v, gran)                 (((v) + ((gran) - 1U)) & ~(((uint64_t)gran) - 1U))
+#endif
+
+#ifndef NV_IS_ALIGNED
+#define NV_IS_ALIGNED(v, gran)                 (0U == ((v) & ((gran) - 1U)))
+#endif
+
+#ifndef NV_IS_ALIGNED64
+#define NV_IS_ALIGNED64(v, gran)               (0U == ((v) & (((uint64_t)gran) - 1U)))
+#endif
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// Register Field Access
+//
+///////////////////////////////////////////////////////////////////////////////
+
+#define DRF_HIBIT(x)                           (x ## _XMSB)
+#define DRF_LOBIT(x)                           (x ## _XLSB)
+
+#define DRF_EXTENT(drf)                        (drf ## _XMSB)
+#define DRF_BASE(drf)                          (drf ## _XLSB)
+
+#define DEVICE_EXTENT(drf)                     (drf ## _XMSB)
+#define DEVICE_BASE(drf)                       (drf ## _XLSB)
+
+#define DRF_IDX_EXTENT(drf,i)                  (drf ## _XMSB(i))
+#define DRF_IDX_BASE(drf,i)                    (drf ## _XLSB(i))
+
+#define DRF_SIZE(drf)                          ((drf ## _XMSB) - (drf ## _XLSB) + 1U)
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// Register Field Shifting and Masking
+//
+///////////////////////////////////////////////////////////////////////////////
+#define DRF_SHIFT(drf)                         ((drf ## _XLSB) % 32U)
+#define DRF_SHIFT64(drf)                       ((drf ## _XLSB) % 64U)
+#define DRF_IDX_SHIFT(drf,i)                   ((drf ## _XLSB(i)) % 32U)
+#define DRF_IDX_SHIFT64(drf,i)                 ((drf ## _XLSB(i)) % 64U)
+
+#define DRF_MASK(drf)                          (0xFFFFFFFFU >> (31U - ((drf ## _XMSB) % 32U) + ((drf ## _XLSB) % 32U)))
+#define DRF_MASK64(drf)                        (0xFFFFFFFFFFFFFFFFUL >> (63UL - ((drf ## _XMSB) % 64UL) + ((drf ## _XLSB) % 64UL)))
+#define DRF_IDX_MASK(drf,i)                    (0xFFFFFFFFU >> (31U - ((drf ## _XMSB(i)) % 32U) + ((drf ## _XLSB(i)) % 32U)))
+#define DRF_IDX_MASK64(drf,i)                  (0xFFFFFFFFFFFFFFFFUL >> (63UL - ((drf ## _XMSB(i)) % 64UL) + ((drf ## _XLSB(i)) % 64UL)))
+
+#define DRF_SHIFTMASK(drf)                     ((uint32_t)(0xFFFFFFFFU >> (31U - ((drf ## _XMSB) % 32U) + ((drf ## _XLSB) % 32U))) << ((drf ## _XLSB) % 32U))
+#define DRF_SHIFTMASK64(drf)                   ((uint64_t)(0xFFFFFFFFFFFFFFFFUL >> (63UL - ((drf ## _XMSB) % 64UL) + ((drf ## _XLSB) % 64UL))) << ((drf ## _XLSB) % 64U))
+
+#define DRF_IDX_SHIFTMASK(drf,i)               ((uint32_t)(0xFFFFFFFFU >> (31U - ((drf ## _XMSB(i)) % 32U) + ((drf ## _XLSB(i)) % 32U))) << ((drf ## _XLSB(i)) % 32U))
+#define DRF_IDX_SHIFTMASK64(drf,i)             ((uint64_t)(0xFFFFFFFFFFFFFFFFUL >> (63UL - ((drf ## _XMSB(i)) % 64UL) + ((drf ## _XLSB(i)) % 64UL))) << ((drf ## _XLSB(i)) % 64U))
+
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// Register Field Reading and Definition
+//
+///////////////////////////////////////////////////////////////////////////////
+#define DRF_DEF(d,r,f,c)                       (((uint32_t)(NV ## d ## r ## f ## c)) << DRF_SHIFT(NV ## d ## r ## f))
+#define DRF_DEF64(d,r,f,c)                     (((uint64_t)(NV ## d ## r ## f ## c)) << DRF_SHIFT64(NV ## d ## r ## f))
+#define DRF_IDX_DEF(d,r,f,i,c)                 (((uint32_t)(NV ## d ## r ## f ## c) << DRF_IDX_SHIFT(NV ## d ## r ## f,i))
+#define DRF_IDX_DEF64(d,r,f,i,c)               (((uint64_t)(NV ## d ## r ## f ## c)) << DRF_IDX_SHIFT64(NV ## d ## r ## f,i))
+
+#define DRF_NUM(d,r,f,n)                       ((((uint32_t)(n)) & DRF_MASK(NV ## d ## r ## f)) << DRF_SHIFT(NV ## d ## r ## f))
+#define DRF_NUM64(d,r,f,n)                     ((((uint64_t)(n)) & DRF_MASK64(NV ## d ## r ## f)) << DRF_SHIFT64(NV ## d ## r ## f))
+#define DRF_IDX_NUM(d,r,f,i,n)                 ((((uint32_t)(n)) & DRF_IDX_MASK(NV ## d ## r ## f,i)) << DRF_IDX_SHIFT(NV ## d ## r ## f,i))
+#define DRF_IDX_NUM64(d,r,f,i,n)               ((((uint64_t)(n)) & DRF_IDX_MASK64(NV ## d ## r ## f,i)) << DRF_IDX_SHIFT64(NV ## d ## r ## f,i))
+
+#define DRF_VAL(d,r,f,v)                       (((v) >> DRF_SHIFT(NV ## d ## r ## f)) & DRF_MASK(NV ## d ## r ## f))
+#define DRF_VAL64(d,r,f,v)                     ((((uint64_t)(v)) >> DRF_SHIFT64(NV ## d ## r ## f)) & DRF_MASK64(NV ## d ## r ## f))
+#define DRF_IDX_VAL(d,r,f,i,v)                 (((v) >> DRF_IDX_SHIFT(NV ## d ## r ## f,i)) & DRF_IDX_MASK(NV ## d ## r ## f,i))
+#define DRF_IDX_VAL64(d,r,f,i,v)               ((((uint64_t)(v)) >> DRF_IDX_SHIFT64(NV ## d ## r ## f,i)) & DRF_IDX_MASK64(NV ## d ## r ## f,i))
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// Register Field Modification
+//
+///////////////////////////////////////////////////////////////////////////////
+#define FLD_SET_DRF_NUM(d,r,f,n,v)             (((v) & ~DRF_SHIFTMASK(NV ## d ## r ## f)) | DRF_NUM(d,r,f,n))
+#define FLD_SET_DRF_NUM64(d,r,f,n,v)           ((((uint64_t)(v)) & ~DRF_SHIFTMASK64(NV ## d ## r ## f)) | DRF_NUM64(d,r,f,n))
+#define FLD_IDX_SET_DRF_NUM(d,r,f,i,n,v)       (((v) & ~DRF_IDX_SHIFTMASK(NV ## d ## r ## f,i)) | DRF_IDX_NUM(d,r,f,i,n))
+#define FLD_IDX_SET_DRF_NUM64(d,r,f,i,n,v)     ((((uint64_t)(v)) & ~DRF_IDX_SHIFTMASK64(NV ## d ## r ## f,i)) | DRF_IDX_NUM64(d,r,f,i,n))
+
+#define FLD_SET_DRF(d,r,f,c,v)                 (((v) & ~DRF_SHIFTMASK(NV ## d ## r ## f)) | DRF_DEF(d,r,f,c))
+#define FLD_SET_DRF64(d,r,f,c,v)               ((((uint64_t)(v)) & ~DRF_SHIFTMASK64(NV ## d ## r ## f)) | DRF_DEF64(d,r,f,c))
+#define FLD_IDX_SET_DRF(d,r,f,i,c,v)           (((v) & ~DRF_IDX_SHIFTMASK(NV ## d ## r ## f,i)) | DRF_IDX_DEF(d,r,f,i,c))
+#define FLD_IDX_SET_DRF64(d,r,f,i,c,v)         ((((uint64_t)(v)) & ~DRF_IDX_SHIFTMASK64(NV ## d ## r ## f,i)) | DRF_IDX_DEF64(d,r,f,i,c))
+
+#define RESETVAL(d,r)                          (NV ## d ## r ## _RESET_VAL)
+
+///////////////////////////////////////////////////////////////////////////////
+//
+// Register Field Test
+//
+///////////////////////////////////////////////////////////////////////////////
+#define FLD_TEST_DRF(d,r,f,c,v)                (DRF_VAL(d,r,f,(v)) == (NV ## d ## r ## f ## c))
+#define FLD_TEST_DRF64(d,r,f,c,v)              (DRF_VAL64(d,r,f,(v)) == (NV ## d ## r ## f ## c))
+#define FLD_IDX_TEST_DRF(d,r,f,i,c,v)          (DRF_IDX_VAL(d,r,f,i,(v)) == ((uint32_t)(NV ## d ## r ## f ## c)))
+#define FLD_IDX_TEST_DRF64(d,r,f,i,c,v)        (DRF_IDX_VAL64(d,r,f,i,(v)) == ((uint64_t)(NV ## d ## r ## f ## c)))
+
+#define FLD_TEST_DRF_NUM(d,r,f,n,v)            ((DRF_VAL(d,r,f,(v)) == (n)))
+#define FLD_TEST_DRF_NUM64(d,r,f,n,v)          (DRF_VAL64(d,r,f,(v)) == (n))
+
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+_Pragma("coverity compliance end_block(include) \
+         MISRA_C_2012_Rule_20_10 MISRA_C_2012_Rule_2_5")
+#endif
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/misc/nvmisc_macros.h b/spe-freertos-bsp/fsp/source/include/misc/nvmisc_macros.h
new file mode 100644
index 0000000..d3d24ca
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/misc/nvmisc_macros.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 1993-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA Corporation and its licensors retain all intellectual property and
+ * proprietary rights in and to this software and related documentation.  Any
+ * use, reproduction, disclosure or distribution of this software and related
+ * documentation without an express license agreement from NVIDIA Corporation
+ * is strictly prohibited.
+ */
+
+#ifndef MISC__NVMISC_MACROS_H
+#define MISC__NVMISC_MACROS_H
+#define FSP__MISC__NVMISC_MACROS_H                      1
+
+#ifdef __cplusplus
+extern "C" {
+#endif //__cplusplus
+
+/* These macros are taken from desktop driver branch file
+ *  $P4PATH/sw/dev/gpu_drv/$BRANCH/sdk/nvidia/inc/nvmisc.h
+ * This is to handle difference between DRF macros
+ * between Mobile and Desktop
+ */
+
+// nvmisc_macros.h can't access nvmisc.h in the Mobile tree... but in some places both are used.
+#if !defined(__NV_MISC_H) && !defined(NV_MISC_H)
+
+#define DEVICE_BASE(d)          (0 ? d)  // what's up with this name? totally non-parallel to the macros below
+#define DEVICE_EXTENT(d)        (1 ? d)  // what's up with this name? totally non-parallel to the macros below
+
+#ifdef NV_USE_FIELD_RANGE_DEFS // These macros are added to remove MISRA C rule 14.3 violations
+// Components which have defined HIGH_FIELD/LOW_FIELD can use below DRF macros
+#define DRF_BASE(drf)           (drf##_LOW_FIELD)
+#define DRF_EXTENT(drf)         (drf##_HIGH_FIELD)
+#define DRF_SHIFT(drf)          ((drf##_LOW_FIELD) % 32U)
+#define DRF_MASK(drf)           (0xFFFFFFFFU >> (31U - ((drf##_HIGH_FIELD) % 32U) + ((drf##_LOW_FIELD) % 32U)))
+
+#else // For components which have not defined HIGH_FIELD/LOW_FIELD
+
+// the first bit occupied by the field in a HW value (e.g., register)
+#define DRF_BASE(drf)           (NV_FALSE ? drf)
+
+// the last bit occupied by the field in a HW value
+#define DRF_EXTENT(drf)         (NV_TRUE ? drf)
+
+// the bit shift amount for accessing the field
+#define DRF_SHIFT(drf)          (((NvU32)DRF_BASE(drf)) % 32U)
+
+// bitmask for the value (unshifted)
+#define DRF_MASK(drf)           (0xFFFFFFFFU >> (31U - (((NvU32)DRF_EXTENT(drf)) % 32U) + (((NvU32)DRF_BASE(drf)) % 32U)))
+#endif
+
+// bitmask for the value (shifted for HW value)
+#define DRF_SHIFTMASK(drf)      (DRF_MASK(drf) << (DRF_SHIFT(drf)))
+
+// size of the field (in bits)
+#define DRF_SIZE(drf)           (DRF_EXTENT(drf) - DRF_BASE(drf) + 1U)
+
+// constant value for HW, e.g., reg |= DRF_DEF(A06F, _GP_ENTRY1, _LEVEL, _SUBROUTINE);
+#define DRF_DEF(d,r,f,c)        (((NvU32)(NV ## d ## r ## f ## c)) << (DRF_SHIFT(NV ## d ## r ## f)))
+
+// numeric value for HW, e.g., reg |= DRF_NUM(A06F, _GP_ENTRY1, _LENGTH, numWords);
+// Note: n should be unsigned 32-bit integer
+#define DRF_NUM(d,r,f,n)        ((((NvU32)(n)) & (DRF_MASK(NV ## d ## r ## f))) << (DRF_SHIFT(NV ## d ## r ## f)))
+
+// numeric value from HW value, e.g., unsigned int numWords = DRF_VAL(A06F, _GP_ENTRY1, _LENGTH, reg);
+// Note: v should be unsigned 32-bit integer
+#define DRF_VAL(d,r,f,v)        (((v) >> DRF_SHIFT(NV ## d ## r ## f)) & DRF_MASK(NV ## d ## r ## f))
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif //__cplusplus
+
+#endif //FSP_MISC_NVMISC_MACROS_H
diff --git a/spe-freertos-bsp/fsp/source/include/misc/nvrm_drf.h b/spe-freertos-bsp/fsp/source/include/misc/nvrm_drf.h
new file mode 100644
index 0000000..439d765
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/misc/nvrm_drf.h
@@ -0,0 +1,174 @@
+/*
+ * Copyright 2007-2020 NVIDIA Corporation.  All Rights Reserved.
+ *
+ * NVIDIA Corporation and its licensors retain all intellectual property and
+ * proprietary rights in and to this software and related documentation.  Any
+ * use, reproduction, disclosure or distribution of this software and related
+ * documentation without an express license agreement from NVIDIA Corporation
+ * is strictly prohibited.
+ */
+
+#ifndef MISC__NVRM_DRF_H
+#define MISC__NVRM_DRF_H
+#define FSP__MISC__NVRM_DRF_H                           1
+
+/**
+ *  @defgroup nvrm_drf RM DRF Macros
+ *
+ *  @ingroup nvddk_rm
+ *
+ * The following suite of macros are used for generating values to write into
+ * hardware registers, or for extracting fields from read registers.  The
+ * hardware headers have a RANGE define for each field in the register in the
+ * form of x:y, 'x' being the high bit, 'y' the lower.  Through a clever use
+ * of the C ternary operator, x:y may be passed into the macros below to
+ * geneate masks, shift values, etc.
+ *
+ * There are two basic flavors of DRF macros, the first is used to define
+ * a new register value from 0, the other is modifiying a field given a
+ * register value.  An example of the first:
+ *
+ * reg = NV_DRF_DEF( HW, REGISTER0, FIELD0, VALUE0 )
+ *     | NV_DRF_DEF( HW, REGISTER0, FIELD3, VALUE2 );
+ *
+ * To modify 'reg' from the previous example:
+ *
+ * reg = NV_FLD_SET_DRF_DEF( HW, REGISTER0, FIELD2, VALUE1, reg );
+ *
+ * To pass in numeric values instead of defined values from the header:
+ *
+ * reg = NV_DRF_NUM( HW, REGISTER3, FIELD2, 1024 );
+ *
+ * To read a value from a register:
+ *
+ * val = NV_DRF_VAL( HW, REGISTER3, FIELD2, reg );
+ *
+ * Some registers have non-zero reset values which may be extracted from the
+ * hardware headers via NV_RESETVAL.
+ */
+
+/*
+ * The NV_FIELD_* macros are helper macros for the public NV_DRF_* macros.
+ */
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+_Pragma("coverity compliance block(include) \
+         (deviate MISRA_C_2012_Rule_20_10 \"Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx\") \
+         (deviate MISRA_C_2012_Rule_2_5 \"Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx\")")
+#endif
+#define NV_FIELD_LOWBIT(x)      (x##_LSB)
+#define NV_FIELD_HIGHBIT(x)     (x##_MSB)
+#define NV_FIELD_SIZE(x)        (NV_FIELD_HIGHBIT(x)-NV_FIELD_LOWBIT(x)+1)
+#define NV_FIELD_SHIFT(x)       (x##_LSB %32U)
+#define NV_FIELD_MASK(x)        (0xFFFFFFFFUL>>(31U-(x##_MSB %32U)+(x##_LSB %32U)))
+#define NV_FIELD_BITS(val, x)   (((val) & NV_FIELD_MASK(x))<<NV_FIELD_SHIFT(x))
+#define NV_FIELD_SHIFTMASK(x)   (NV_FIELD_MASK(x)<< (NV_FIELD_SHIFT(x)))
+
+/*
+ * Dynamic versions of some of the above macros
+ */
+#define NV_DYN_FIELD_SHIFT(lsb)                 (lsb %32U)
+#define NV_DYN_FIELD_MASK(msb, lsb)             (0xFFFFFFFFUL>>(31U-(msb %32U)+(lsb %32U)))
+#define NV_DYN_FIELD_BITS(val, msb, lsb)        (((val) & NV_DYN_FIELD_MASK(msb, lsb))<<NV_DYN_FIELD_SHIFT(lsb))
+
+
+/*
+ * The NV_FIELD64_* macros are helper macros for the public NV_DRF64_* macros.
+ */
+#define NV_FIELD64_SHIFT(x) (x##_LSB %64UL)
+#define NV_FIELD64_MASK(x)  (0xFFFFFFFFFFFFFFFFULL>>(63UL-(x##_MSB %64UL)+(x##_LSB %64UL)))
+
+
+/** NV_DRF_DEF - define a new register value.
+
+    @ingroup nvrm_drf
+
+    @param d register domain (hardware block)
+    @param r register name
+    @param f register field
+    @param c defined value for the field
+ */
+#define NV_DRF_DEF(d,r,f,c) \
+    ((d##_##r##_0_##f##_##c) << NV_FIELD_SHIFT(d##_##r##_0_##f))
+
+/** NV_DRF_NUM - define a new register value.
+
+    @ingroup nvrm_drf
+
+    @param d register domain (hardware block)
+    @param r register name
+    @param f register field
+    @param n numeric value for the field
+ */
+#define NV_DRF_NUM(d,r,f,n) \
+    ((uint32_t)((n)& NV_FIELD_MASK(d##_##r##_0_##f)) << \
+        NV_FIELD_SHIFT(d##_##r##_0_##f))
+
+/** NV_DRF_VAL - read a field from a register.
+
+    @ingroup nvrm_drf
+
+    @param d register domain (hardware block)
+    @param r register name
+    @param f register field
+    @param v register value
+ */
+#define NV_DRF_VAL(d,r,f,v) \
+    (((v)>> NV_FIELD_SHIFT(d##_##r##_0_##f)) & \
+        NV_FIELD_MASK(d##_##r##_0_##f))
+
+/** NV_FLD_SET_DRF_NUM - modify a register field.
+
+    @ingroup nvrm_drf
+
+    @param d register domain (hardware block)
+    @param r register name
+    @param f register field
+    @param n numeric field value
+    @param v register value
+ */
+#define NV_FLD_SET_DRF_NUM(d,r,f,n,v) \
+    (((v) & ~NV_FIELD_SHIFTMASK(d##_##r##_0_##f)) | NV_DRF_NUM(d,r,f,n))
+
+/** NV_FLD_SET_DRF_DEF - modify a register field.
+
+    @ingroup nvrm_drf
+
+    @param d register domain (hardware block)
+    @param r register name
+    @param f register field
+    @param c defined field value
+    @param v register value
+ */
+#define NV_FLD_SET_DRF_DEF(d,r,f,c,v) \
+    (((v) & ~NV_FIELD_SHIFTMASK(d##_##r##_0_##f)) | \
+        NV_DRF_DEF(d,r,f,c))
+
+/** NV_RESETVAL - get the reset value for a register.
+
+    @ingroup nvrm_drf
+
+    @param d register domain (hardware block)
+    @param r register name
+ */
+#define NV_RESETVAL(d,r)    (d##_##r##_0_RESET_VAL)
+
+
+/** NV_DRF64_NUM - define a new 64-bit register value.
+
+    @ingroup nvrm_drf
+
+    @param d register domain
+    @param r register name
+    @param f register field
+    @param n numeric value for the field
+ */
+#define NV_DRF64_NUM(d,r,f,n) \
+    (((n)& NV_FIELD64_MASK(d##_##r##_0_##f)) << \
+        NV_FIELD64_SHIFT(d##_##r##_0_##f))
+
+#if (defined(FSP_COVERITY) && (FSP_COVERITY==1))
+_Pragma("coverity compliance end_block(include) \
+         MISRA_C_2012_Rule_20_10 MISRA_C_2012_Rule_2_5")
+#endif
+
+#endif // FSP_MISC_NVRM_DRF_H
diff --git a/spe-freertos-bsp/fsp/source/include/osa/freertosv10/arm/armv7/cortex-r5/ospl/rtos-port-asm.h b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/arm/armv7/cortex-r5/ospl/rtos-port-asm.h
new file mode 100644
index 0000000..827c65f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/arm/armv7/cortex-r5/ospl/rtos-port-asm.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2021 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef OSPL__RTOS_PORT_ASM_H
+#define OSPL__RTOS_PORT_ASM_H
+#define FSP__OSPL__RTOS_PORT_ASM_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+#ifdef __ASSEMBLER__
+
+.macro rtosIRQ_ENTRY
+    push { R0-R3, IP, LR }
+.endm
+
+.macro rtosIRQ_EXIT
+    b irq_end
+.endm
+
+#endif /* #ifdef __ASSEMBLER__ */
+#endif /* #ifndef OSPL__RTOS_PORT_ASM_H */
+
diff --git a/spe-freertos-bsp/fsp/source/include/osa/freertosv10/arm/armv7/cortex-r5/ospl/rtos-port.h b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/arm/armv7/cortex-r5/ospl/rtos-port.h
new file mode 100644
index 0000000..6c234d5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/arm/armv7/cortex-r5/ospl/rtos-port.h
@@ -0,0 +1,260 @@
+/* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSPL__RTOS_PORT_H
+#define OSPL__RTOS_PORT_H
+#define FSP__OSPL__RTOS_PORT_H                          1
+
+/* Compiler headers */
+#include <stdint.h>                         // for uint32_t, int32_t, int16_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <FreeRTOSConfig.h>                 // for configTICK_RATE_HZ, config...
+#include <FreeRTOS.h>                       // IWYU pragma: export
+                                            // IWYU pragma: no_include "FreeRTOS.h"
+#include <portmacro.h>                      // IWYU pragma: export
+                                            // IWYU pragma: no_include "portmacro.h"
+                                            // for UBaseType_t, portBASE_TYPE, portSTACK_TYPE
+#include <projdefs.h>                       // IWYU pragma: export
+                                            // IWYU pragma: no_include "projdefs.h"
+                                            // for TaskFunction_t
+#include <portable.h>                       // IWYU pragma: export
+                                            // IWYU pragma: no_include "portable.h"
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__CONFIG__FREERTOSCONFIG_H, "Header file missing or invalid.")
+
+/*
+ * Port specific types and data structures needed by nvosRTOS.h
+ *
+ * This file should not be included directly from any other file.
+ */
+
+/**
+ * @brief Make sure that the sizes of types defined by FreeRTOS are what they
+ * are expected to be.
+ */
+CT_ASSERT(sizeof(char) == sizeof(portCHAR), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(float) == sizeof(portFLOAT), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(double) == sizeof(portDOUBLE), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(long) == sizeof(portLONG), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(short) == sizeof(portSHORT), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(uint32_t) == sizeof(portSTACK_TYPE), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(long) == sizeof(portBASE_TYPE), "ASSERT due to data type mismatch.")
+
+/**
+ * @brief Provide wrapper type definitions for RTOS values to avoid exposing the
+ * FreeRTOS types directly.
+ *
+ * @typedef-title OSA variable type space
+ */
+typedef portBASE_TYPE           rtosError;
+typedef void                    *rtosTaskHandle;
+typedef void                    *rtosEventGroupHandle;
+typedef StaticEventGroup_t      rtosEventGroup;
+typedef void                    *rtosQueueHandle;
+typedef void                    *rtosTimerHandle;
+typedef void                    *rtosTimerLocalStorageObject;
+typedef uint32_t                portUInt32Type;
+typedef uint8_t                 portUInt8Type;
+typedef UBaseType_t             rtosUCount;
+typedef portSTACK_TYPE          rtosTick;
+typedef portBASE_TYPE           rtosBool;
+typedef portBASE_TYPE           rtosTimerIDType;
+typedef void                    *rtosMutexHandle;
+typedef void                    *rtosSemaphoreHandle;
+typedef void                    *rtosEventPollHandle;
+typedef UBaseType_t             rtosTaskNotifyBits;
+typedef UBaseType_t             rtosEventPollValue;
+typedef portBASE_TYPE           rtosTaskNotifyAction;
+typedef UBaseType_t             rtosTaskNotifyValue;
+typedef UBaseType_t             rtosPriority;
+typedef UBaseType_t             rtosInterruptState;
+typedef UBaseType_t             rtosMutexState;
+typedef unsigned long           rtosEventBits;
+typedef portSTACK_TYPE          rtosHz;
+typedef UBaseType_t             rtosPrivilegeLevel;
+typedef UBaseType_t             rtosUBaseType_t;
+typedef portBASE_TYPE           rtosPortBaseType;
+typedef void *			portTaskHandleType;
+typedef StaticSemaphore_t       rtosSemaphoreBuffer;
+typedef StaticQueue_t           rtosQueueBuffer;
+typedef StaticEventGroup_t      rtosEventGroupBuffer;
+typedef StaticTask_t            rtosTaskBuffer;
+typedef StackType_t             rtosStackType;
+
+/**
+ * @brief Provide wrapper definition for pointer to RTOS task function.
+ */
+typedef TaskFunction_t             rtosTaskFunction;
+
+
+/**
+ * @brief Provide wrapper definition for pointer to RTOS timer callback function
+ * which gets invoked when a timer expires.
+ */
+typedef void (*rtosTimerCallbackFunction)(void * pvParameters);
+
+/**
+ * @brief Structure supplied to rtosTaskCreate()
+ *
+ * @pvTaskCode        Pointer to task entry function
+ * @pcTaskName        Task descriptive name
+ * @pxTCB             Pointer to task control block
+ * @pcStackBuffer     Pointer to task stack buffer
+ * @uxStackDepthBytes Size of task stack buffer in bytes. The minimum
+ *                    allowable size for the stack buffer is portdependent.
+ * @pvParameters      Pointer to task parameters
+ * @uxPriority        Priority of task.
+ *                    Valid range is [0 - (configMAX_PRIORITIES - 1])
+ * @pvObject          Pointer to user defined data associated with this task.
+ * @xUsingFPU         Bool to indicate use of FPU
+ * @uxPrivilegeLevel  Task Privilege level
+ */
+typedef struct {
+    rtosTaskFunction     pvTaskCode;
+    char                *pcTaskName;
+    void                *pxTCB;
+    void                *pcStackBuffer;
+    rtosUCount           uxStackDepthBytes;
+    void                *pvParameters;
+    rtosPriority         uxPriority;
+    void                *pvObject;
+    rtosBool             xUsingFPU;
+    rtosPrivilegeLevel   uxPrivilegeLevel;
+} rtosTaskParameters;
+
+/**
+ * @brief Structure supplied to rtosTaskInitializeScheduler()
+ *
+ * @ulCPUClockHz                      Speed of the system clock
+ * @ulTickRateHz                      Desired frequency of kernel tick
+ * @uxAdditionalStackCheckMarginBytes Lower limit on number of bytes that
+ *                                    should be left in the stack post context
+ *                                    switch. Can be set greater than or equal
+ *                                    to 0
+ * @pcIdleTaskStackBuffer             Pointer to the lowest address of task
+ *                                    buffer to hold idle task
+ * @uxIdleTaskStackSizeBytes          Number of bytes in the stack buffer to be
+ *                                    kept for idle task. Should be greater
+ *                                    than 0
+ * @xIdleTaskUsingFPU                 Bool variable to indicate use of FPU by
+ *                                    idle task
+ * @uxIdleTaskPrivilegeLevel          Idle task privilege level
+ *                                    [RTOS_SYSTEM_MODE, RTOS_USER_MODE]
+ * @pvIdleTaskTLSObject               Idle task timer local storage object
+ * @uxTimerTaskPriority               Priority of timer service.
+ *                                    Valid range is [0 - (configMAX_PRIORITIES - 1)]
+ * @uxTimerTaskStackSize              Number of bytes in stack buffer to be kept
+ *                                    for timer task. Should be greater than 0
+ * @pcTimerTaskStackBuffer            Pointer to the timer task stack buffer.
+ * @uxTimerCommandQueueLength         Timer command queue length. Should be
+ *                                    greater than 0.
+ * @uxTimerCommandQueueBufferSize     Timer command queue buffer size.
+ *                                    Size of the buffer should be at
+ *                                    least enough to accomodate the entire
+ *                                    command queue
+ * @pcTimerCommandQueueBuffer         Pointer to timer command queue buffer
+ */
+typedef struct {
+    rtosHz              ulCPUClockHz;
+    rtosHz              ulTickRateHz;
+    rtosUCount          uxAdditionalStackCheckMarginBytes;
+    void                *pcIdleTaskStackBuffer;
+    rtosUCount          uxIdleTaskStackSizeBytes;
+    rtosBool            xIdleTaskUsingFPU;
+    rtosPrivilegeLevel  uxIdleTaskPrivilegeLevel;
+    void                *pvIdleTaskTLSObject;
+    rtosPriority        uxTimerTaskPriority;
+    rtosUCount          uxTimerTaskStackSize;
+    void                *pcTimerTaskStackBuffer;
+    rtosUCount          uxTimerCommandQueueLength;
+    rtosUCount          uxTimerCommandQueueBufferSize;
+    void                *pcTimerCommandQueueBuffer;
+} rtosSchedParameters;
+
+/**
+ * @brief Structure supplied to rtosTimerCreate()
+ *
+ * @pcTimerName         Descriptive name of the timer
+ * @xTimerPeriodInTicks Timer period in ticks. Should be greater than 0
+ * @xIsPeriodic         Bool variable to indicate if timer is periodic
+ * @xTimerID            Timer ID
+ * @pxNewTimer          Pointer to timer control block
+ * @pxCallbackFunction  Timer callback function
+ * @pxTimerInstance     Timer instance to which the timer belongs
+ * @pvObject            Pointer to user defined data associated with this timer.
+ */
+typedef struct {
+    const char                *pcTimerName;
+    rtosTick                  xTimerPeriodInTicks;
+    rtosBool                  xIsPeriodic;
+    rtosTimerIDType           xTimerID;
+    void                      *pxNewTimer;
+    rtosTimerCallbackFunction pxCallbackFunction;
+    void                      *pxTimerInstance;
+    void                      *pvObject;
+} rtosTimerInitParametersType;
+
+/**
+ * @brief Provide wrapper definitions for general architecture specific values
+ *
+ * @macro-title RTOS general architecture values
+ *
+ * @rtosMAX_DELAY             Defines maximum delay supported by rtos
+ * @rtosSTACK_IN_USE          Defines state value indicating stack is in use
+ * @rtosSTACK_NOT_IN_USE      Defines state value indicating stack is not in use
+ * @rtosTICK_COUNT_BITS       Defines number of bits used to represent tick
+ *                            count
+ * @rtosTICK_RATE_HZ          Defines frequency of the underlying RTOS scheduler
+ *                            tick
+ * @rtosTICK_RATE_MS          Defines number of ticks per millisecond.
+ */
+#define rtosMAX_DELAY                           portMAX_DELAY
+#define rtosSTACK_IN_USE                        portSTACK_IN_USE
+#define rtosSTACK_NOT_IN_USE                    portSTACK_NOT_IN_USE
+#define rtosTICK_COUNT_BITS                     portTICK_COUNT_NUM_BITS
+#define rtosTICK_RATE_HZ                        configTICK_RATE_HZ
+#define rtosTICK_RATE_MS                        portTICK_PERIOD_MS
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-errors.h b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-errors.h
new file mode 100644
index 0000000..51e2da3
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-errors.h
@@ -0,0 +1,328 @@
+/* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_ERRORS_H
+#define OSA__OSA_ERRORS_H
+#define FSP__OSA__OSA_ERRORS_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>  // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>  // for errSUPPLIED_BUFFER_TOO_SMALL, errBAD_OR_...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+
+/**
+ * @brief Mapping of FreeRTOS return codes to generic rtos error codes.
+ *
+ * @macro-title Public error codes from OSA layer
+ *
+ * @E_RTOS_SUPPLIED_BUFFER_TOO_SMALL              Error value returned if
+ *                                                supplied buffer is too small
+ *                                                to create a kernel object
+ * @E_RTOS_INVALID_PRIORITY                       Error value returned for
+ *                                                invalid task priority
+ * @E_RTOS_QUEUE_FULL                             Error value returned if queue
+ *                                                is full and cannot accept a
+ *                                                new request
+ * @E_RTOS_NULL_PARAMETER_SUPPLIED                Error value returned if null is
+ *                                                supplied as an input parameter
+ * @E_RTOS_INVALID_QUEUE_LENGTH                   Error value returned if
+ *                                                requested queue length
+ *                                                is invalid
+ * @E_RTOS_INVALID_TASK_CODE_POINTER              Error value returned for
+ *                                                invalid input task code pointer
+ * @E_RTOS_SCHEDULER_IS_SUSPENDED                 Error value returned if request
+ *                                                could not be processed because
+ *                                                the scheduler was suspended
+ * @E_RTOS_INVALID_TASK_HANDLE                    Error value returned for
+ *                                                invalid input task handle
+ * @E_RTOS_DID_NOT_YIELD                          Error value returned if task
+ *                                                did not yield for a yield
+ *                                                request
+ * @E_RTOS_TASK_ALREADY_SUSPENDED                 Error value returned if request
+ *                                                to suspend a task could not be
+ *                                                processed because the task
+ *                                                was already suspended.
+ * @E_RTOS_TASK_WAS_NOT_SUSPENDED                 Error value returned if request
+ *                                                to resume a task
+ *                                                could not be processed because
+ *                                                the task was not suspended.
+ * @E_RTOS_SCHEDULER_ALREADY_RUNNING              Error value returned if request
+ *                                                to start a scheduler could not
+ *                                                be processed because
+ *                                                scheduler was already running
+ * @E_RTOS_INVALID_QUEUE_HANDLE                   Error value returned for
+ *                                                invalid input queue handle
+ * @E_RTOS_INVALID_SEMAPHORE_HANDLE               Error value returned for
+ *                                                invalid input semaphore handle
+ * @E_RTOS_INVALID_MUTEX_HANDLE                   Error value returned for
+ *                                                invalid input mutex handle
+ * @E_RTOS_ERRONEOUS_UNBLOCK                      Error value returned for
+ *                                                erroneous request to
+ *                                                unblock a task
+ * @E_RTOS_QUEUE_EMPTY                           Error value returned if request
+ *                                                to pick a task from the queue
+ *                                                could not be processed because
+ *                                                queue was empty
+ * @E_RTOS_SEMAPHORE_ALREADY_TAKEN                Error value returned if request
+ *                                                to acquire a semaphore could
+ *                                                not be processed because
+ *                                                semaphore was already taken
+ * @E_RTOS_MUTEX_ALREADY_TAKEN                    Error value returned if
+ *                                                request to acquire a mutex
+ *                                                could not be processed because
+ *                                                mutex was already taken
+ * @E_RTOS_INVALID_TICK_VALUE                     Error value returned for
+ *                                                invalid input tick value
+ * @E_RTOS_INVALID_TASK_SELECTED                  Error value returned for
+ *                                                invalid task selection
+ * @E_RTOS_TASK_STACK_OVERFLOW                    Error value returned when task
+ *                                                stack overflows
+ * @E_RTOS_SCHEDULER_WAS_NOT_SUSPENDED            Error value returned if request
+ *                                                to resume scheduler could not
+ *                                                be processed because
+ *                                                scheduler was already running.
+ * @E_RTOS_INVALID_BUFFER_SIZE                    Error value returned for
+ *                                                invalid input buffer size
+ * @E_RTOS_BAD_OR_NO_TICK_RATE_CONFIGURATION      Error value returned for
+ *                                                invalid tick rate
+ * @E_RTOS_ERROR_IN_VECTOR_TABLE                  Error value returned for error
+ *                                                in vector table
+ * @E_RTOS_INVALID_MPU_REGION_CONFIGURATION       Error value returned for
+ *                                                invalid MPU region
+ *                                                configuration
+ * @E_RTOS_INVALID_MMU_REGION_CONFIGURATION       Error value returned for
+ *                                                invalid MMU region
+ *                                                configuration
+ * @E_RTOS_TASK_STACK_ALREADY_IN_USE              Error value returned if task
+ *                                                stack supplied to initialize a
+ *                                                scheduler is already in use
+ * @E_RTOS_NO_MPU_IN_DEVICE                       Error value returned if MPU
+ *                                                does not exist in the device
+ * @E_RTOS_EXECUTING_IN_UNPRIVILEGED_MODE         Error value returned if a task
+ *                                                is expected to run in
+ *                                                privileged mode but currently
+ *                                                running in unprivileged mode
+ * @E_RTOS_RTS_CALCULATION_ERROR                  Error value returned on
+ *                                                detection of rts calculation
+ *                                                error
+ * @E_RTOS_INVALID_PERCENTAGE_HANDLE              Error value returned for
+ *                                                invalid percentage handle
+ * @E_RTOS_INVALID_INITIAL_SEMAPHORE_COUNT        Error value returned for
+ *                                                invalid initial semaphore count
+ * @E_RTOS_ROM_INTEGRITY_CHECK_FAILED             Error value returned for ROM
+ *                                                integrity check failures
+ * @E_RTOS_IN_PROGRESS                            Error value returned if request
+ *                                                is already in progress
+ * @E_RTOS_INVALID_PARAMETERS                     Error value returned if
+ *                                                invalid value is set for
+ *                                                input parameter
+ * @E_RTOS_SPURIOUS_INTERRUPT                     Error value returned for
+ *                                                spurious interrupts
+ * @E_RTOS_SPURIOUS_FAST_INTERRUPT                Error value returned for
+                                                  spurious fast interrupts
+ * @E_RTOS_RAM_INTEGRITY_CHECK_FAILED             Error value returned for RAM
+ *                                                integrity check failure
+ * @E_RTOS_INVALID_TIMER_HANDLE                   Error value returned for
+ *                                                invalid timer handle
+ * @E_RTOS_INVALID_TIMER_TASK_INSTANCE            Error value returned for
+ *                                                invalid input timer task
+ *                                                instance
+ * @E_RTOS_TIMER_ALREADY_IN_USE                   Error value returned if request
+ *                                                to create a new timer could not
+ *                                                be processed because the
+ *                                                supplied timer handle was
+ *                                                already in use.
+ * @E_RTOS_NOTIFICATION_NOT_RECEIVED              Error value returned if
+ *                                                notification is
+ *                                                not received until timeout
+ * @E_RTOS_NOTIFICATION_ALREADY_PENDING           Error value returned if a new
+ *                                                request to wait for
+ *                                                notification arises while the
+ *                                                task is still waiting for
+ *                                                notification
+ * @E_RTOS_TASK_WAS_ALSO_ON_EVENT_LIST            Error value returned if the
+ *                                                task is already part of the
+ *                                                event list
+ * @E_RTOS_QUEUE_ALREADY_IN_USE                   Error value returned if request
+ *                                                to create a new queue could not
+ *                                                be processed because input
+ *                                                queue handle was already in use
+ * @E_RTOS_EVENT_GROUP_ALREADY_IN_USE             Error value returned if request
+ *                                                to create a new event group
+ *                                                could not be processed because
+ *                                                input event group handle was
+ *                                                already in use
+ * @E_RTOS_INVALID_EVENT_GROUP_HANDLE             Error value returned for
+ *                                                invalid input event group
+ *                                                handle
+ * @E_RTOS_EVENT_GROUP_BITS_NOT_SET               Error value returned if event
+ *                                                group bits could not be set
+ * @E_RTOS_EVENT_GROUP_DELETED                    Error value returned if event
+ *                                                group request could not be
+ *                                                processed as referred object
+ *                                                is deleted
+ * @E_RTOS_MUTEX_NOT_OWNED_BY_CALLER             Error value returned if mutex
+ *                                                request could not be processed
+ *                                                as mutex is not owned by
+ *                                                the caller
+ * @E_RTOS_MUTEX_CORRUPTED                        Error value returned if mutex
+ *                                                got corrupted
+ * @E_RTOS_NEXT_UNBLOCK_TIME_EXPIRED              Error value returned if next
+ *                                                unblock time for the referred
+ *                                                task expired
+ * @E_RTOS_WOKEN_UP_AFTER_NEXT_UNBLOCK_TIME       Error value returned if task
+ *                                                got unblocked after next
+ *                                                unblock time
+ * @E_RTOS_TICKLESS_MODE_NOT_SUPPORTED            Error value returned if
+ *                                                tickless mode is not supported
+ * @E_RTOS_SCHEDULER_IS_NOT_RUNNING               Error value returned if the request
+ *                                                could not be processed because
+ *                                                scheduler is not running
+ * @E_RTOS_EVENT_POLL_OBJECT_ALREADY_IN_USE       Error value returned if
+ *                                                request to create a new event
+ *                                                poll object could not be
+ *                                                processed as event poll object
+ *                                                handle was already in use
+ * @E_RTOS_EVENT_POLL_OBJECT_EVENTS_LIMIT_REACHED Error value returned if no
+ *                                                more target objects can be
+ *                                                registered with the referred
+ *                                                event poll object
+ * @E_RTOS_INVALID_EVENT_POLL_OPERATION           Error value returned for
+ *                                                invalid event poll operation
+ * @E_RTOS_INVALID_EVENT_POLL_HANDLE              Error value returned for
+ *                                                invalid event poll handle
+ * @E_RTOS_INVALID_EVENT_POLL_EVENTS              Error value returned for
+ *                                                invalid event poll events for
+ *                                                the target object
+ * @E_RTOS_NO_TASKS_CREATED                       Error value returned if
+ *                                                request to start a scheduler
+ *                                                could not be processed as no
+ *                                                tasks are created
+ * @E_RTOS_INVALID_ALIGNMENT                      Error returned for invalid byte
+ *                                                alignment
+ * @E_RTOS_EVENT_POLL_NO_EVENTS_OCCURRED          Error returned if no event has
+ *                                                occurred while waiting for
+ *                                                events registered with event
+ *                                                poll object
+ * @E_RTOS_INVALID_DATA_RANGE                     Error value returned for
+ *                                                invalid data range
+ * @E_RTOS_NO_TICK_SETUP_HOOK_DEFINED             Error value returned if no hook
+ *                                                has been defined to setup ticks
+ */
+#define E_RTOS_SUPPLIED_BUFFER_TOO_SMALL              errSUPPLIED_BUFFER_TOO_SMALL
+#define E_RTOS_INVALID_PRIORITY                       errINVALID_PRIORITY
+#define E_RTOS_QUEUE_FULL                             errQUEUE_FULL
+#define E_RTOS_INVALID_ALIGNMENT                      errINVALID_ALIGNMENT
+#define E_RTOS_NULL_PARAMETER_SUPPLIED                errNULL_PARAMETER_SUPPLIED
+#define E_RTOS_INVALID_QUEUE_LENGTH                   errINVALID_QUEUE_LENGTH
+#define E_RTOS_INVALID_TASK_CODE_POINTER              errINVALID_TASK_CODE_POINTER
+#define E_RTOS_SCHEDULER_IS_SUSPENDED                 errSCHEDULER_IS_SUSPENDED
+#define E_RTOS_INVALID_TASK_HANDLE                    errINVALID_TASK_HANDLE
+#define E_RTOS_DID_NOT_YIELD                          errDID_NOT_YIELD
+#define E_RTOS_TASK_ALREADY_SUSPENDED                 errTASK_ALREADY_SUSPENDED
+#define E_RTOS_TASK_WAS_NOT_SUSPENDED                 errTASK_WAS_NOT_SUSPENDED
+#define E_RTOS_NO_TASKS_CREATED                       errNO_TASKS_CREATED
+#define E_RTOS_SCHEDULER_ALREADY_RUNNING              errSCHEDULER_ALREADY_RUNNING
+#define E_RTOS_INVALID_QUEUE_HANDLE                   errINVALID_QUEUE_HANDLE
+#define E_RTOS_INVALID_SEMAPHORE_HANDLE               errINVALID_SEMAPHORE_HANDLE
+#define E_RTOS_INVALID_MUTEX_HANDLE                   errINVALID_MUTEX_HANDLE
+#define E_RTOS_ERRONEOUS_UNBLOCK                      errERRONEOUS_UNBLOCK
+#define E_RTOS_QUEUE_EMPTY                            errQUEUE_EMPTY
+#define E_RTOS_SEMAPHORE_ALREADY_TAKEN                errSEMAPHORE_ALREADY_TAKEN
+#define E_RTOS_MUTEX_ALREADY_TAKEN                    errMUTEX_ALREADY_TAKEN
+#define E_RTOS_INVALID_TICK_VALUE                     errINVALID_TICK_VALUE
+#define E_RTOS_INVALID_TASK_SELECTED                  errINVALID_TASK_SELECTED
+#define E_RTOS_TASK_STACK_OVERFLOW                    errTASK_STACK_OVERFLOW
+#define E_RTOS_SCHEDULER_WAS_NOT_SUSPENDED            errSCHEDULER_WAS_NOT_SUSPENDED
+#define E_RTOS_INVALID_BUFFER_SIZE                    errINVALID_BUFFER_SIZE
+#define E_RTOS_BAD_OR_NO_TICK_RATE_CONFIGURATION      errBAD_OR_NO_TICK_RATE_CONFIGURATION
+#define E_RTOS_ERROR_IN_VECTOR_TABLE                  errERROR_IN_VECTOR_TABLE
+#define E_RTOS_INVALID_MPU_REGION_CONFIGURATION       errINVALID_MPU_REGION_CONFIGURATION
+#define E_RTOS_INVALID_MMU_REGION_CONFIGURATION       errINVALID_MMU_REGION_CONFIGURATION
+#define E_RTOS_TASK_STACK_ALREADY_IN_USE              errTASK_STACK_ALREADY_IN_USE
+#define E_RTOS_NO_MPU_IN_DEVICE                       errNO_MPU_IN_DEVICE
+#define E_RTOS_EXECUTING_IN_UNPRIVILEGED_MODE         errEXECUTING_IN_UNPRIVILEGED_MODE
+#define E_RTOS_RTS_CALCULATION_ERROR                  errRTS_CALCULATION_ERROR
+#define E_RTOS_INVALID_PERCENTAGE_HANDLE              errINVALID_PERCENTAGE_HANDLE
+#define E_RTOS_INVALID_INITIAL_SEMAPHORE_COUNT        errINVALID_INITIAL_SEMAPHORE_COUNT
+#define E_RTOS_ROM_INTEGRITY_CHECK_FAILED             errROM_INTEGRITY_CHECK_FAILED
+#define E_RTOS_IN_PROGRESS                            errIN_PROGRESS
+#define E_RTOS_INVALID_PARAMETERS                     errINVALID_PARAMETERS
+#define E_RTOS_SPURIOUS_INTERRUPT                     errSPURIOUS_INTERRUPT
+#define E_RTOS_SPURIOUS_FAST_INTERRUPT                errSPURIOUS_FAST_INTERRUPT
+#define E_RTOS_RAM_INTEGRITY_CHECK_FAILED             errRAM_INTEGRITY_CHECK_FAILED
+#define E_RTOS_INVALID_TIMER_HANDLE                   errINVALID_TIMER_HANDLE
+#define E_RTOS_INVALID_TIMER_TASK_INSTANCE            errINVALID_TIMER_TASK_INSTANCE
+#define E_RTOS_TIMER_ALREADY_IN_USE                   errTIMER_ALREADY_IN_USE
+#define E_RTOS_NOTIFICATION_NOT_RECEIVED              errNOTIFICATION_NOT_RECEIVED
+#define E_RTOS_NOTIFICATION_ALREADY_PENDING           errNOTIFICATION_ALREADY_PENDING
+#define E_RTOS_TASK_WAS_ALSO_ON_EVENT_LIST            errTASK_WAS_ALSO_ON_EVENT_LIST
+#define E_RTOS_QUEUE_ALREADY_IN_USE                   errQUEUE_ALREADY_IN_USE
+#define E_RTOS_EVENT_GROUP_ALREADY_IN_USE             errEVENT_GROUP_ALREADY_IN_USE
+#define E_RTOS_INVALID_EVENT_GROUP_HANDLE             errINVALID_EVENT_GROUP_HANDLE
+#define E_RTOS_EVENT_GROUP_BITS_NOT_SET               errEVENT_GROUP_BITS_NOT_SET
+#define E_RTOS_EVENT_GROUP_DELETED                    errEVENT_GROUP_DELETED
+#define E_RTOS_MUTEX_NOT_OWNED_BY_CALLER              errMUTEX_NOT_OWNED_BY_CALLER
+#define E_RTOS_MUTEX_CORRUPTED                        errMUTEX_CORRUPTED
+#define E_RTOS_NEXT_UNBLOCK_TIME_EXPIRED              errNEXT_UNBLOCK_TIME_EXPIRED
+#define E_RTOS_WOKEN_UP_AFTER_NEXT_UNBLOCK_TIME       errWOKEN_UP_AFTER_NEXT_UNBLOCK_TIME
+#define E_RTOS_TICKLESS_MODE_NOT_SUPPORTED            errTICKLESS_MODE_NOT_SUPPORTED
+#define E_RTOS_EVENT_POLL_OBJECT_ALREADY_IN_USE       errEVENT_POLL_OBJECT_ALREADY_IN_USE
+#define E_RTOS_SCHEDULER_IS_NOT_RUNNING               errSCHEDULER_IS_NOT_RUNNING
+#define E_RTOS_EVENT_POLL_OBJECT_EVENTS_LIMIT_REACHED errEVENT_POLL_OBJECT_EVENTS_LIMIT_REACHED
+#define E_RTOS_INVALID_EVENT_POLL_OPERATION           err INVALID_EVENT_POLL_OPERATION
+#define E_RTOS_INVALID_EVENT_POLL_HANDLE              errINVALID_EVENT_POLL_HANDLE
+#define E_RTOS_INVALID_EVENT_POLL_EVENTS              errINVALID_EVENT_POLL_EVENTS
+#define E_RTOS_EVENT_POLL_NO_EVENTS_OCCURRED          errEVENT_POLL_NO_EVENTS_OCCURRED
+#define E_RTOS_INVALID_DATA_RANGE                     errINVALID_DATA_RANGE
+#define E_RTOS_NO_TICK_SETUP_HOOK_DEFINED             errNO_TICK_SETUP_HOOK_DEFINED
+#define E_RTOS_COULD_NOT_ALLOCATE_REQUIRED_MEMORY     errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY
+#define E_RTOS_QUEUE_BLOCKED                          errQUEUE_BLOCKED
+#define E_RTOS_QUEUE_YIELD                            errQUEUE_YIELD
+
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-event-group.h b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-event-group.h
new file mode 100644
index 0000000..970c189
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-event-group.h
@@ -0,0 +1,347 @@
+/* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_EVENT_GROUP_H
+#define OSA__OSA_EVENT_GROUP_H
+#define FSP__OSA__OSA_EVENT_GROUP_H                     1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosEventGroupHandle, rtosEventBits, rto...
+#include <osa/osa-values.h>             // for rtosPASS
+#include <event_groups.h>               // IWYU pragma: export
+                                        // IWYU pragma: no_include "event_groups.h"
+                                        // for xEventGroupClearBitsFromISR, xEvent...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+
+/**
+ * @brief Create an event group
+ *
+ * This function is a wrapper for xEventGroupCreate() in FreeRTOS to create an
+ * event group object.
+ * It uses static or non-static API depending on the buffer provided by the
+ * application writer.
+ * It updates pointer to the event group handle to point to the newly
+ * created event group
+ *
+ * @pre
+ * - A variable of type rtosEventGroup, r/w accessible to RTOS kernel at all
+ * times has been declared to handle the event group object
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in]  pxEventGroup       Pointer to the pre-declared event group variable
+ *                                of type rtosEventGroup
+ * @param[out] pxEventGroupHandle Pointer to the event group handle
+ *
+ * @retval rtosPASS on success
+ */
+static inline rtosError
+rtosEventGroupCreate(rtosEventGroup *pxEventGroup,
+                     rtosEventGroupHandle *pxEventGroupHandle)
+{
+    *pxEventGroupHandle = (pxEventGroup == NULL) ?
+                           xEventGroupCreate() :
+                           xEventGroupCreateStatic(pxEventGroup);
+     return rtosPASS;
+}
+
+/**
+ * @brief Delete an event group
+ *
+ * This function is a wrapper for xEventGroupDelete() in FreeRTOS to delete an
+ * event group object.
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from a non-interrupt context
+ *
+ * - Scheduler has been started.
+ *
+ * @param[in] xHandle Event group handle
+ *
+ * @retval rtosPASS                          on success
+ */
+static inline rtosError
+rtosEventGroupDelete(rtosEventGroupHandle xHandle)
+{
+    vEventGroupDelete(xHandle);
+    return rtosPASS;
+}
+
+/**
+ * @brief Get event group bits.
+ *
+ * This function is a wrapper for xEventGroupGetBits() in FreeRTOS to
+ * read the status of event group bits.
+ * It updates the pointer to event group bits with latest bit-mask of
+ * set fields in the event group.
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xHandle        Event group handle
+ * @param[in] pxEventBitsSet Pointer to event group bits
+ *
+ * @retval rtosPASS                          on success
+ */
+static inline rtosError
+rtosEventGroupGetBits(rtosEventGroupHandle xHandle,
+                      rtosEventBits *pxEventBitsSet)
+{
+    *pxEventBitsSet = xEventGroupGetBits(xHandle);
+    return rtosPASS;
+}
+
+/**
+ * @brief Get event group bits from ISR.
+ *
+ * This function is a wrapper for xEventGroupGetBitsFromISR() in FreeRTOS to
+ * read the status of event group bits from an ISR
+ * It updates the pointer to event group bits with latest bit-mask of set fields
+ * within the event group in an ISR context.
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xHandle        Event group handle
+ * @param[in] pxEventBitsSet Pointer to event group bits
+ *
+ * @retval rtosPASS                          on success
+ */
+static inline rtosError
+rtosEventGroupGetBitsFromISR(rtosEventGroupHandle xHandle,
+                             rtosEventBits *pxEventBitsSet)
+{
+    *pxEventBitsSet = xEventGroupGetBitsFromISR(xHandle);
+    return rtosPASS;
+}
+
+/**
+ * Set event group bits
+ *
+ * This function is a wrapper for xEventGroupSetBits() in FreeRTOS to set one
+ * or more bits to '1' in an event group
+ * Sets required fields within the event group based on bit-mask sent as an
+ * argument.
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xHandle    Event group handle
+ * @param[in] xBitsToSet Bit mask to set required fields in the event group
+ *                       Size of rtosEventBits type is platform dependent.
+ *                       For ARM Cortex-R5, it is 32-bits. Since most
+ *                       significant byte is used for control purposes, valid
+ *                       bit-mask range is 0 - 23 bits.
+ *
+ * @retval The value of the event group
+ */
+static inline rtosError
+rtosEventGroupSetBits(rtosEventGroupHandle xHandle,
+                      const rtosEventBits xBitsToSet)
+{
+    return xEventGroupSetBits(xHandle, xBitsToSet);
+}
+
+/**
+ * Set event group bits from ISR
+ *
+ * This function is a wrapper for xEventGroupSetBitsFromISR() in FreeRTOS to
+ * set one or more event group bits to '1' in an interrupt-context.
+ * Sets required fields within the event group based on bit-mask sent as an
+ * argument.
+ * It sets the value at pbHigherPriorityTaskWoken if calling this function
+ * unblocks a task of priority higher than currently running task indicating
+ * that a context switch is needed before exiting the ISR
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xHandle                    Event group handle
+ * @param[in] xBitsToSet                 Bit-mask to set required fields in the
+ *                                       event group. Valid bit-mask range for
+ *                                       ARM Cortex-R5 processor is 0 - 23 bits.
+ * @param[out] pbHigherPriorityTaskWoken Pointer to rtosbool variable
+ *
+ * @retval rtosPASS                          on success
+ * @retval rtosFAIL                          on failure
+ */
+static inline rtosError
+rtosEventGroupSetBitsFromISR(rtosEventGroupHandle xHandle,
+                             const rtosEventBits xBitsToSet,
+                             rtosBool *pbHigherPriorityTaskWoken)
+{
+    return xEventGroupSetBitsFromISR(xHandle,
+                                     xBitsToSet,
+                                     pbHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Clear required event group bits
+ *
+ * This function is a wrapper for xEventGroupClearBits() in FreeRTOS to clear
+ * one or more bits in an event group
+ * Clears required fields within the event group based on bit-mask sent as an
+ * argument.
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xHandle      Event group handle
+ * @param[in] xBitsToClear Bit-mask to clear required fields.
+ *                         Valid bit mask range for ARM Cortex-R5 processor is
+ *                         0 - 23 bits.
+ *
+ * @retval The value of the event group before the specified bits were cleared
+ */
+static inline rtosError
+rtosEventGroupClearBits(rtosEventGroupHandle xHandle,
+                        const rtosEventBits xBitsToClear)
+{
+    return xEventGroupClearBits(xHandle,
+                                xBitsToClear);
+}
+
+/**
+ * @brief Clear required event group bits from ISR
+ *
+ * This function is a wrapper for xEventGroupClearBitsFromISR() in FreeRTOS to
+ * clear one or more event group bits in an interrupt context.
+ * Clears required fields within the event group based on bit-mask sent as an
+ * argument.
+ * It sets value at pbHigherPriorityTaskWoken if calling this function unblocks
+ * a higher priority task than current task indicating a context switch is
+ * needed before exiting from ISR
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xHandle                    Event group handle
+ * @param[in] xBitsToClear               Bit-mask to clear required fields in
+ *                                       the event group. Valid bit-mask range
+ *                                       for ARM Cortex-R5 processor is 0 - 23
+ *                                       bits
+ * @param[out] pbHigherPriorityTaskWoken Pointer to rtosbool variable
+ *
+ * @retval rtosPASS                          on success
+ * @retval rtosFAIL                          on failure
+ */
+static inline rtosError
+rtosEventGroupClearBitsFromISR(rtosEventGroupHandle xHandle,
+                               const rtosEventBits xBitsToClear,
+                               rtosBool *pbHigherPriorityTaskWoken)
+{
+    (void)pbHigherPriorityTaskWoken;
+    return xEventGroupClearBitsFromISR(xHandle,
+                                       xBitsToClear);
+}
+
+/**
+ * @brief Wait for one or more bits to set within an event group until timeout
+ *
+ * This function is a wrapper for xEventGroupWaitBits() in FreeRTOS to wait until
+ * given pattern of event group bits is set
+ * Calling task blocks on waiting for required bit fields to be set as long as wait
+ * condition is met until timeout
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xHandle         Event group handle
+ * @param[in] xBitstoWaitFor  Bit-mask to check for required fields. Valid range
+ *                            of bit-mask on ARM Cortex-R5 processor is
+ *                            0 - 23 bits
+ * @param[in] xClearOnExit    Set this bool variable to clear all the bit fields
+ *                            before exiting wait
+ * @param[in] xWaitforAllBits Set this bool variable if all the required bit
+ *                            fields should be set to exit from wait
+ * @param[in] pxEventBitsSet  Pointer to event group bits. Before exiting from
+ *                            wait, value at this address is updated with the
+ *                            status of event group bits
+ * @param[in] xTicksToWait    Timeout in ticks for which the calling task should
+ *                            be held in blocked state waiting for the pattern
+ *                            condition to be set. A value of zero prevents the
+ *                            task from entering the blocked state.
+ *
+ * @retval   The value of the event group at the time either the bits being waited
+ *           for became set, or the block time expired.
+ */
+static inline rtosError
+rtosEventGroupWaitBits(rtosEventGroupHandle xHandle,
+                       const rtosEventBits xBitsToWaitFor,
+                       const rtosBool xClearOnExit,
+                       const rtosBool xWaitForAllBits,
+                       rtosEventBits *pxEventBitsSet,
+                       rtosTick xTicksToWait)
+{
+    (void)pxEventBitsSet;
+    return xEventGroupWaitBits(xHandle,
+                               xBitsToWaitFor,
+                               (portBASE_TYPE)xClearOnExit,
+                               (portBASE_TYPE)xWaitForAllBits,
+                               xTicksToWait);
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-mutex.h b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-mutex.h
new file mode 100644
index 0000000..96e4ec5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-mutex.h
@@ -0,0 +1,159 @@
+/* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_MUTEX_H
+#define OSA__OSA_MUTEX_H
+#define FSP__OSA__OSA_MUTEX_H                           1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosMutexHandle, FSP__OSPL__RTOS_PORT_H
+#include <osa/osa-values.h>             // for rtosPASS
+#include <semphr.h>                     // for xSemaphoreCreateMutex, xSemaphoreGiveRec...
+
+/**
+ * @brief Computes the size needed for rtosMutexCreate.
+ *
+ * @macro-title Get size of mutex object
+ *
+ * @retval NumberOfBytes Size of mutex object in bytes
+ */
+#define rtosMutexSize()         (1)
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+
+/**
+ * @brief Create a mutex lock
+ *
+ * This function is a wrapper for xMutexCreate() in FreeRTOS to create
+ * a mutex object.
+ * It uses static or non-static API depending on the buffer provided by the
+ * application writer.
+ * It updates pointer to the handle sent as an argument
+ * with newly created mutex
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle a mutex object
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pcMutexBuffer Pointer to the memory location at which mutex
+ *                          will be created. Size of the mutex buffer
+ *                          is rtosMutexSize()
+ *                          Mutex buffer shall be 4-byte aligned
+ *
+ * @retval    rtosPASS                         on success
+ */
+static inline rtosError
+rtosMutexCreate(void *pcMutexBuffer,
+                rtosMutexHandle *pxMutex)
+{
+    *pxMutex = (pcMutexBuffer == NULL) ?
+               xSemaphoreCreateMutex() :
+               xSemaphoreCreateMutexStatic(pcMutexBuffer);
+
+     return rtosPASS;
+}
+
+/**
+ * @brief Acquire a mutex
+ *
+ * This function is a wrapper for xMutexTake() in FreeRTOS to acquire a mutex
+ *
+ * @pre
+ * - A mutex has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xMutex     Mutex handle
+ * @param[in] xBlocktime Timeout in ticks to wait until mutex is acquired.
+ *                       A value of zero prevents the calling task from
+ *                       entering the Blocked state.
+ *
+ * @retval    rtosPASS   on success
+ * @retval    rtosFAIL   on failure
+ */
+static inline rtosError
+rtosMutexAcquire(rtosMutexHandle xMutex,
+                 rtosTick xBlockTime)
+{
+    return xSemaphoreTakeRecursive(xMutex,
+                      xBlockTime);
+}
+
+/**
+ * @brief Release acquired mutex
+ *
+ * This function is a wrapper for xMutexGive() in FreeRTOS to release
+ * an acquired mutex.
+ *
+ * @pre
+ * - A mutex has been created with a valid handle
+ *
+ * - Referred mutex was previously acquired.
+ *
+ * - Scheduler has been started
+ *
+ * - Called in a non-interrupt context
+ *
+ * @param[in] xMutex       Mutex handle
+ *
+ * @retval    rtosPASS     on success
+ * @retval    rtosFAIL     on failure
+ */
+static inline rtosError
+rtosMutexRelease(rtosMutexHandle xMutex)
+{
+    return xSemaphoreGiveRecursive(xMutex);
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-queue.h b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-queue.h
new file mode 100644
index 0000000..a1ee1b5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-queue.h
@@ -0,0 +1,530 @@
+/* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_QUEUE_H
+#define OSA__OSA_QUEUE_H
+#define FSP__OSA__OSA_QUEUE_H                           1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosError, rtosQueueHandle, rtosTick
+#include <osa/osa-values.h>             // for rtosPASS
+#include <queue.h>                      // IWYU pragma: export
+                                        // IWYU pragma: no_include "queue.h"
+                                        // for uxQueueMessagesWaiting, uxQueueSpacesAva...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+
+/**
+ * @brief rtosQueueSize() computes the size needed for rtosQueueCreate.
+ *
+ * @_n_                 max number of elements in queue
+ * @_s_                 size of a queue element
+ *
+ * @macro-title Get number of bytes required for the queue.
+ *
+ * @retval NumberOfBytes Size of queue in bytes
+ */
+#define rtosQueueSize(_n_, _s_) (((_n_) * (_s_)) + sizeof(rtosQueueBuffer))
+
+/**
+ * @brief Create a task queue
+ *
+ * This function is a wrapper for xQueueCreate() in FreeRTOS.
+ * It uses static or non-static API depending on the buffer provided by the
+ * application writer.
+ * It updates the pointer to the queue handle to point
+ * to the newly created queue
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle a queue object.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pcQueueMemory  Pointer to memory at which queue object
+ *                           will be created. Queue buffer should be 4-byte
+ *                           aligned.
+ * @param[in] uxBufferLength Buffer length to handle tasks. Should be equal to
+ *                           rtosQueueSize(_n_, _s_)
+ * @param[in] uxQueueLength  Maximum number of items the queue can hold
+ * @param[out] pxQueue       Pointer to queue handle
+ *
+ * @retval rtosPASS          On success
+ */
+static inline rtosError
+rtosQueueCreate(void *pcQueueMemory,
+                rtosUCount uxBufferLength,
+                rtosUCount uxQueueLength,
+                rtosUCount uxItemSize,
+                rtosQueueHandle *pxQueue)
+{
+    *pxQueue = (pcQueueMemory == NULL) ?
+                xQueueCreate(uxQueueLength,
+                        uxItemSize) :
+                xQueueCreateStatic(uxQueueLength,
+                        uxItemSize,
+                        (portUInt8Type *)pcQueueMemory + sizeof (rtosQueueBuffer),
+                        (rtosQueueBuffer *)pcQueueMemory);
+
+    return rtosPASS;
+}
+
+/**
+ * @brief Delete a task queue
+ *
+ * This function is a wrapper for vQueueDelete() in FreeRTOS.
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle a queue object.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pcQueueMemory  Pointer to memory at which queue object
+ *                           will be created. Queue buffer should be 4-byte
+ *                           aligned.
+ * @param[in] uxBufferLength Buffer length to handle tasks. Should be equal to
+ *                           rtosQueueSize(_n_, _s_)
+ * @param[in] uxQueueLength  Maximum number of items the queue can hold
+ * @param[out] pxQueue       Pointer to queue handle
+ *
+ * @retval rtosPASS          On success
+ */
+static inline rtosError
+rtosQueueDelete(rtosQueueHandle *pxQueue)
+{
+    vQueueDelete((QueueHandle_t) pxQueue);
+    return rtosPASS;
+}
+
+/**
+ * @brief Add an item at the end of a queue
+ *
+ * This function is a wrapper for xQueueSend() in FreeRTOS.
+ * Sends a item in the queue in First In First Out (FIFO) order.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xQueue         Queue handle
+ * @param[in] pvItemToQueue  Pointer to the item
+ * @param[in] xTicksToWait   Timeout in ticks to wait until the
+ *                           item gets added. A value of 0 prevents the task
+ *                           from entering blocked state.
+ *
+ * @retval rtosPASS          On success
+ * @retval E_RTOS_QUEUE_FULL Queue is full and item cannot be added
+ */
+static inline rtosError
+rtosQueueSend(rtosQueueHandle rtosQueue,
+              const void * const pvItemToQueue,
+              rtosTick xTicksToWait)
+{
+    return xQueueSend(rtosQueue,
+                      pvItemToQueue,
+                      xTicksToWait);
+}
+
+/**
+ * @brief Add an item at the front of a queue
+ *
+ * This function is a wrapper for xQueueSendToFront() in FreeRTOS.
+ * Sends an item in the queue in Last In First Out (LIFO) order.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xQueue         Queue handle
+ * @param[in] pvItemToQueue  Pointer to item
+ * @param[in] xTicksToWait   Timeout in ticks to wait until
+ *                           item gets added. A value of 0 prevents the task from
+ *                           entering blocked state
+ *
+ * @retval rtosPASS          On success
+ * @retval E_RTOS_QUEUE_FULL Queue is full and item cannot be added
+ */
+static inline rtosError
+rtosQueueSendToFront(rtosQueueHandle rtosQueue,
+                     const void * const pvItemToQueue,
+                     rtosTick xTicksToWait)
+{
+    return xQueueSendToFront(rtosQueue,
+                             pvItemToQueue,
+                             xTicksToWait);
+}
+
+/**
+ * @brief Pick an item from the queue
+ *
+ * This is a wrapper for xQueueReceive() in FreeRTOS
+ * It always picks item from the beginning of a queue.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xQueue       Queue handle
+ * @param[in] pvBuffer     Pointer to the buffer to copy the item. Length of
+ *                         buffer should be at least equal to the item size.
+ * @param[in] xTicksToWait Timeout in ticks to wait until item is picked.
+ *                         A value of 0 prevents the task from entering
+ *                         blocked state
+ *
+ * @retval rtosPASS        On success
+ * @retval rtosFAIL        On failure
+ */
+static inline rtosError
+rtosQueueReceive(rtosQueueHandle rtosQueue,
+                 void *const pvBuffer,
+                 rtosTick xTicksToWait)
+{
+    return xQueueReceive(rtosQueue,
+                         pvBuffer,
+                         xTicksToWait);
+}
+
+/**
+ * @brief Peek an item from queue
+ *
+ * This function is a wrapper for xQueuePeek() in FreeRTOS
+ * It picks an item without removing it from the queue.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xQueue       Queue handle
+ * @param[in] pvBuffer     Pointer to a buffer to copy the item.
+ *                         Length of the buffer should be at least equal to the
+ *                         queue item size.
+ * @param[in] xTicksToWait Timeout in ticks to wait until item is picked.
+ *                         A value of 0 prevents the task from entering the
+ *                         blocked state
+ *
+ * @retval rtosPASS        On success
+ * @retval rtosFAIL        On failure
+ */
+static inline rtosError
+rtosQueuePeek(rtosQueueHandle rtosQueue,
+              void *const pvBuffer,
+              rtosTick xTicksToWait)
+{
+    return xQueuePeek(rtosQueue,
+                      pvBuffer,
+                      xTicksToWait);
+}
+
+/**
+ * @brief Get number of waiting messages in the queue.
+ *
+ * This function is a wrapper for xQueueMessagesWaiting() in FreeRTOS.
+ * It updates value at pointer to a count variable sent as an argument
+ * with latest number of pending items in the queue.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xQueue              Queue handle
+ * @param[out] puxMessagesWaiting Pointer to a count variable
+ *
+ * @retval    The number of messages available in the queue.
+ */
+static inline rtosError
+rtosQueueMessageWaiting(rtosQueueHandle rtosQueue,
+                        rtosUCount *puxMessagesWaiting)
+{
+    (void)puxMessagesWaiting;
+    return uxQueueMessagesWaiting(rtosQueue);
+}
+
+/**
+ * @brief Add an item at the end of a queue from ISR
+ *
+ * This function is a wrapper for xQueueSendFromISR() in FreeRTOS.
+ * Adds an item to the queue from interrupt context in First In First Out (FIFO)
+ * It sets value at pointer to a bool variable sent as an
+ * argument if adding item to the queue unblocks a higher/equal priority task
+ * than the current active task.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] xQueue                     Queue handle
+ * @param[in] pvItemToQueue              Pointer to item
+ * @param[out] pbHigherPriorityTaskWoken Pointer to a bool variable
+ *                                       indicating current context.
+ * @retval rtosPASS          On success
+ * @retval E_RTOS_QUEUE_FULL Queue is full and item cannot be added
+ */
+static inline rtosError
+rtosQueueSendFromISR(rtosQueueHandle rtosQueue,
+                     const void *const pvItemToQueue,
+                     rtosBool *pbHigherPriorityTaskWoken)
+{
+    return xQueueSendFromISR(rtosQueue,
+                             pvItemToQueue,
+                             pbHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Add an item at the end of a queue from ISR
+ *
+ * This function is a wrapper for xQueueSendToBackFromISR() in FreeRTOS.
+ * Adds an item to the queue from interrupt context in First In First Out (FIFO)
+ * It sets value at pointer to a bool variable sent as an
+ * argument if adding item to the queue unblocks a higher/equal priority task
+ * than the current active task.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] xQueue                     Queue handle
+ * @param[in] pvItemToQueue              Pointer to item
+ * @param[out] pbHigherPriorityTaskWoken Pointer to a bool variable
+ *                                       indicating current context.
+ *
+ * @retval rtosPASS                      On success
+ * @retval E_RTOS_QUEUE_FULL             Queue full and item cannot be added
+ */
+static inline rtosError
+rtosQueueSendToBackFromISR(rtosQueueHandle rtosQueue,
+                     const void *const pvItemToQueue,
+                     rtosBool *pbHigherPriorityTaskWoken)
+{
+    return xQueueSendToBackFromISR(rtosQueue,
+                           pvItemToQueue,
+                           pbHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Add an item at the end of a queue from ISR
+ *
+ * This function is a wrapper for xQueueSendToBack() in FreeRTOS.
+ * Adds an item to the queue from interrupt context in First In First Out (FIFO)
+ * It sets value at pointer to a bool variable sent as an
+ * argument if adding item to the queue unblocks a higher/equal priority task
+ * than the current active task.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] xQueue                     Queue handle
+ * @param[in] pvItemToQueue              Pointer to item
+ * @param[out] pbHigherPriorityTaskWoken Pointer to a bool variable
+ *                                       indicating current context.
+ *
+ * @retval rtosPASS                      On success
+ * @retval E_RTOS_QUEUE_FULL             Queue full and item cannot be added
+ */
+static inline rtosError
+rtosQueueSendToBack(rtosQueueHandle rtosQueue,
+                     const void *const pvItemToQueue,
+                     rtosTick xTicksToWait)
+{
+    return xQueueSendToBack(rtosQueue,
+                           pvItemToQueue,
+                           xTicksToWait);
+}
+
+/**
+ * @brief Add an item at the front of a queue from ISR
+ *
+ * This function is a wrapper for xQueueSendToFrontFromISR() in FreeRTOS.
+ * Adds an item to the queue from interrupt context in Last In First Out (LIFO)
+ * order.
+ * It sets value at pointer to a bool variable sent as an argument if adding
+ * item to the queue unblocks a higher/equal priority task than the current
+ * active task.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] xQueue                     Queue handle
+ * @param[in] pvItemToQueue              Pointer to item
+ * @param[out] pbHigherPriorityTaskWoken Pointer to a bool variable
+ *                                       indicating current context.
+ *
+ * @retval rtosPASS                      On success
+ * @retval E_RTOS_QUEUE_FULL             Queue full and item cannot be added
+ */
+static inline rtosError
+rtosQueueSendToFrontFromISR(rtosQueueHandle rtosQueue,
+                            const void *const pvItemToQueue,
+                            rtosBool *pbHigherPriorityTaskWoken)
+{
+    return xQueueSendToFrontFromISR(rtosQueue,
+                                    pvItemToQueue,
+                                    pbHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Pick an item from the queue in interrupt context
+ *
+ * This function is a wrapper for xQueueReceiveFromISR() in FreeRTOS
+ * Picks item from the beginning of a queue in an interrupt context
+ * and sets value at pointer to a bool variable sent as an argument if calling
+ * this function unblocks a higher priority task than the current active task.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] xQueue                      Queue handle
+ * @param[in] pvBuffer                    Pointer to a buffer to copy the item.
+ *                                        Length of the buffer should be at
+ *                                        least equal to the item size.
+ * @param[out] pbHigherPriorityTaskWoken  Pointer to a bool variable
+ *                                        indicating current context.
+ *
+ * @retval rtosPASS                       On success
+ * @retval rtosFAIL                       On failure
+ */
+static inline rtosError
+rtosQueueReceiveFromISR(rtosQueueHandle rtosQueue,
+                        void *const pvBuffer,
+                        rtosBool *pbHigherPriorityTaskWoken)
+{
+    return xQueueReceiveFromISR(rtosQueue,
+                                pvBuffer,
+                                pbHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Pick an item from the queue in interrupt context
+ *
+ * This function is a wrapper for xQueueIsQueueFullFromISR() in FreeRTOS
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] xQueue                      Queue handle
+ * @param[in] pvBuffer                    Pointer to a buffer to copy the item.
+ *                                        Length of the buffer should be at
+ *                                        least equal to the item size.
+ * @param[out] pbHigherPriorityTaskWoken  Pointer to a bool variable
+ *                                        indicating current context.
+ *
+ * @retval rtosPASS                       On success
+ * @retval rtosFAIL                       On failure
+ */
+static inline rtosError
+rtosQueueIsQueueFullFromISR(rtosQueueHandle rtosQueue)
+{
+    return xQueueIsQueueFullFromISR(rtosQueue);
+}
+
+/**
+ * @brief Pick an item from the queue in interrupt context
+ *
+ * This function is a wrapper for uxQueueSpacesAvailable() in FreeRTOS
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] xQueue                      Queue handle
+ * @param[in] pvBuffer                    Pointer to a buffer to copy the item.
+ *                                        Length of the buffer should be at
+ *                                        least equal to the item size.
+ * @param[out] pbHigherPriorityTaskWoken  Pointer to a bool variable
+ *                                        indicating current context.
+ *
+ * @retval The number of spaces available in the queue.
+ */
+static inline rtosError
+rtosQueueSpacesAvailable(rtosQueueHandle rtosQueue)
+{
+    return uxQueueSpacesAvailable(rtosQueue);
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-semaphore.h b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-semaphore.h
new file mode 100644
index 0000000..763510c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-semaphore.h
@@ -0,0 +1,305 @@
+/* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_SEMAPHORE_H
+#define OSA__OSA_SEMAPHORE_H
+#define FSP__OSA__OSA_SEMAPHORE_H                       1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-sepcific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosError, rtosSemaphoreHandle, rtosBool
+#include <osa/osa-values.h>             // for rtosPASS
+#include <semphr.h>                     // IWYU pragma: export
+                                        // IWYU pragma: no_include "semphr.h"
+                                        // for vSemaphoreDelete, xSemaphoreCreateBinary
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+
+/**
+ * @brief rtosSemaphoreSize() computes the size needed for rtosSemaphoreCreate.
+ *
+ * @macro-title Get size of semaphore object
+ *
+ * @retval NumberOfBytes Size of semaphore object in bytes
+ */
+#define rtosSemaphoreSize()     4
+
+/**
+ * @brief Create a binary semaphore.
+ *
+ * This function is a wrapper for xSemaphoreCreateBinary() in FreeRTOS
+ * to create a binary semaphore object.
+ * It uses static or non-static API depending on the buffer provided by the
+ * application writer.
+ * It updates the handle sent as an argument to point to the newly
+ * created semaphore
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle a semaphore object.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pcSemaphoreMemory Pointer to the memory location at which
+ *                              semaphore object will be created.
+ *                              Clients shall use rtosSemaphoreSize() to get
+ *                              the size of this pre-allocated memory.
+ *                              Memory buffer shall be 4-byte aligned.
+ * @param[out] xpSemaphore      Pointer to the semaphore handle
+ *
+ * @retval rtosPASS             On success
+ */
+static inline rtosError
+rtosSemaphoreCreateBinary(void *pcSemaphoreMemory,
+                          rtosSemaphoreHandle *xpSemaphore)
+{
+    *xpSemaphore = (pcSemaphoreMemory == NULL) ?
+                    xSemaphoreCreateBinary() :
+                    xSemaphoreCreateBinaryStatic(pcSemaphoreMemory);
+    return rtosPASS;
+}
+
+/**
+ * @brief Create a counting semaphore
+ *
+ * This function is a wrapper for xSemaphoreCreateCounting() in FreeRTOS
+ * to create a counting semaphore object.
+ * It updates the handle sent as an argument to point to the newly
+ * created semaphore.
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle a semaphore object.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] uxMaxCount        Max limit of semaphore count.
+ *                              Should be set greater than 0
+ * @param[in] uxInitialCount    Min/Initial count of semaphore count.
+ *                              Should be set less than uxMaxCount
+ * @param[in] pcSemaphoreMemory Pointer to the memory location at which
+ *                              semaphore object will be created.
+ *                              Clients shall use rtosSemaphoreSize() to get
+ *                              the size of this pre-allocated memory.
+ *                              Memory buffer shall be 4-byte aligned.
+ * @param[out] xpSemaphore      Pointer to the semaphore handle
+ *
+ * @retval rtosPASS             On success
+ */
+static inline rtosError
+rtosSemaphoreCreateCounting(void *pcSemaphoreMemory,
+                            rtosUCount uxMaxCount,
+                            rtosUCount uxInitialCount,
+                            rtosSemaphoreHandle *xpSemaphore)
+{
+    *xpSemaphore = (pcSemaphoreMemory == NULL) ?
+                   xSemaphoreCreateCounting(uxMaxCount,
+                                            uxInitialCount) :
+                   xSemaphoreCreateCountingStatic(uxMaxCount,
+                                            uxInitialCount,
+                                            pcSemaphoreMemory);
+    return rtosPASS;
+}
+
+/**
+ * @brief Release a semaphore
+ *
+ * This function is a wrapper for xSemaphoreGive() in FreeRTOS to
+ * release an acquired semaphore.
+ *
+ * @pre
+ * - A semaphore has been created with a valid handle referring to it
+ *
+ * - Referred Semaphore was previously acquired
+ *
+ * - Called from a non-interrupt context.
+ *
+ * - Scheduler has been started.
+ *
+ * @param[in] xSemaphore Semaphore handle
+ *
+ * @retval rtosPASS      on success
+ * @retval rtosFAIL      on failure
+ */
+static inline rtosError
+rtosSemaphoreRelease(rtosSemaphoreHandle xSemaphore)
+{
+    return xSemaphoreGive(xSemaphore);
+}
+
+/**
+ * @brief Release a semaphore from ISR
+ *
+ * This function is a wrapper for xSemaphoreGiveFromISR() in FreeRTOS to
+ * release an acquired semaphore in interrupt context.
+ * It sets value at pointer to rtos bool variable sent
+ * as an argument if calling this API unblocks a task of priority equal
+ * to/higher than currently running task.
+ *
+ * @pre
+ * - A semaphore has been created with a valid handle referring to it.
+ *
+ * - Referred semaphore was previously acquired
+ *
+ * - Called from an interrupt context
+ *
+ * - Scheduler has been started.
+ *
+ * @param[in] xSemaphore                 Semaphore handle
+ * @param[out] pbHigherPriorityTaskWoken Pointer to a boolean variable
+ *
+ * @retval rtosPASS                      On success
+ * @retval E_RTOS_QUEUE_FULL             Queue is full and item cannot be added
+ */
+static inline rtosError
+rtosSemaphoreReleaseFromISR(rtosSemaphoreHandle xSemaphore,
+                            rtosBool *pbHigherPriorityTaskWoken)
+{
+    return xSemaphoreGiveFromISR(xSemaphore,
+                                 pbHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Acquire a semaphore
+ *
+ * This function is a wrapper for xSemaphoreTake() in FreeRTOS to
+ * acquire a semaphore.
+ *
+ * @pre
+ * - A semaphore has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context
+ *
+ * - Scheduler has been started.
+ *
+ * @param[in] xSemaphore   Semaphore handle
+ * @param[in] xTicksToWait Timeout in ticks to wait until semaphore is acquired.
+ *                         A value of zero prevents the calling task from
+ *                         entering the Blocked state waiting for semaphore.
+ *
+ * @retval rtosPASS        On success
+ * @retval rtosFAIL        On failure
+ */
+static inline rtosError
+rtosSemaphoreAcquire(rtosSemaphoreHandle xSemaphore,
+                     rtosTick xTicksToWait)
+{
+    return xSemaphoreTake(xSemaphore, xTicksToWait);
+}
+
+/**
+ * @brief Acquire semaphore from ISR
+ *
+ * This function is a wrapper for xSemaphoreTakeFromISR() in FreeRTOS to
+ * acquire a semaphore in interrupt context.
+ * It sets value at pointer to rtos bool variable sent as an argument
+ * if calling this API unblocks a task of priority equal to/higher than
+ * currently running task.
+ *
+ * @pre
+ * - A semaphore has been created with a valid handle referring to it
+ *
+ * - Called from an interrupt context
+ *
+ * - Scheduler has been started.
+ *
+ * @param[in] xSemaphore                 Semaphore handle
+ * @param[out] pbHigherPriorityTaskWoken Pointer to boolean variable
+ *
+ * @retval rtosPASS                      On success
+ * @retval rtosFAIL                      On failure
+ */
+static inline rtosError
+rtosSemaphoreAcquireFromISR(rtosSemaphoreHandle xSemaphore,
+                            rtosBool *pbHigherPriorityTaskWoken)
+{
+    return xSemaphoreTakeFromISR(xSemaphore,
+                                 pbHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Delete Semaphore
+ *
+ * This function is a wrapper for vSemaphoreDelete() in FreeRTOS.
+ * @pre
+ * - A semaphore has been created with a valid handle referring to it.
+ *
+ * @param[in] xSemaphore     Semaphore handle
+ *
+ * @retval rtosPASS          On success
+ */
+static inline rtosError
+rtosSemaphoreDelete(rtosSemaphoreHandle xSemaphore)
+{
+    vSemaphoreDelete(xSemaphore);
+    return rtosPASS;
+}
+
+/**
+ * @brief Get semaphore count depth
+ *
+ * @pre
+ * - A semaphore has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ *
+ * @param[in] xSemaphore     Semaphore handle
+ * @param[out] puxCountDepth Pointer to rtos count variable
+ *
+ * @retval rtosPASS           on success
+ */
+static inline rtosError
+rtosSemaphoreGetCountDepth(rtosSemaphoreHandle xSemaphore,
+                           rtosUCount *puxCountDepth)
+{
+    *puxCountDepth = uxSemaphoreGetCount(xSemaphore);
+    return rtosPASS;
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-task.h b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-task.h
new file mode 100644
index 0000000..a7f8102
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-task.h
@@ -0,0 +1,631 @@
+/* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_TASK_H
+#define OSA__OSA_TASK_H
+#define FSP__OSA__OSA_TASK_H                            1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosBool, rtosTaskHandle, rtosTick, rtos...
+#include <osa/osa-values.h>
+#include <task.h>                       // IWYU pragma: export
+                                        // IWYU pragma: no_include "task.h"
+                                        // for vTaskStartScheduler, uxTaskPriorityGet
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+
+#define rtosIDLE_PRIORITY                   tskIDLE_PRIORITY
+#define rtosTaskScheduler_Suspended         taskSCHEDULER_SUSPENDED
+#define rtosTaskScheduler_Not_Started       taskSCHEDULER_NOT_STARTED
+#define rtosTaskScheduler_Running           taskSCHEDULER_RUNNING
+
+/**
+ * @brief Initialize task scheduler
+ *
+ * This function is a wrapper for xTaskInitializeScheduler() in FreeRTOS to
+ * initialize a task scheduler.
+ * It configures scheduler private data and passes application specific data
+ * to the FreeRTOS scheduler by translating structures and types used by NVIDIA
+ * code to those used by FreeRTOS.
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it.
+ *
+ * - Scheduler init parameters have been set.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxSchedInitParameters Pointer to rtosSchedParameters structure
+ *                                  containing scheduler private data required for
+ *                                  initialization.
+ *
+ * @retval rtosPASS                 On success
+ */
+static inline rtosError
+rtosTaskInitializeScheduler(const rtosSchedParameters *const pxSchedInitParameters)
+{
+    (void) pxSchedInitParameters;
+    vTaskStartScheduler();
+    return rtosPASS;
+}
+
+/**
+ * @brief Create a task
+ *
+ * This function is a wrapper for xTaskCreate() in FreeRTOS to create a new
+ * task and place it in ready state. It provides a translation of structures
+ * and types used by NVIDIA code to those used by FreeRTOS.
+ * It uses static or non-static API depending on the buffer provided by the
+ * application writer.
+ * It updates the pointer to task handle using task init structure sent as
+ * an argument to refer to the newly created task.
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * initialized for the task control block.
+ *
+ * - Task init parameters have been initialized
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxTaskParameters Pointer to a rtosTaskParameters structure that
+ *                             contains the parameters used to create a task
+ * @param[out] pxCreatedTask   Pointer to task handle
+ *
+ * @retval rtosPASS success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED          Null pointer to handle/task
+ *                                                 init structure
+ * @retval E_RTOS_INVALID_PRIORITY                 Task priority above stated
+ *                                                 maximum
+ * @retval E_RTOS_INVALID_TASK_CODE_POINTER        Invalid pointer to task code
+ * @retval E_RTOS_TASK_STACK_ALREADY_IN_USE        Memory pointed by stack
+ *                                                 buffer already in use.
+ * @retval E_RTOS_INVALID_TASK_CODE_POINTER        Pointer to task code
+ *                                                 parameter is NULL
+ * @retval E_RTOS_INVALID_BYTE_ALIGMENT            Stack buffer not aligned
+ * @retval E_RTOS_INVALID_MPU_REGION_CONFIGURATION Improper size/alignment
+ *                                                 of mpu region
+ * @retval E_RTOS_SUPPLIED_BUFFER_TOO_SMALL        Supplied buffer not
+ *                                                 sufficient to hold task
+ * @retval E_RTOS_INVALID_BUFFER_SIZE              Buffer size not a power of 2
+ */
+static inline rtosError
+rtosTaskCreate(const rtosTaskParameters * const pxTaskParameters,
+               rtosTaskHandle *pxCreatedTask)
+{
+
+    if (pxTaskParameters->pxTCB == NULL)
+       return xTaskCreate (pxTaskParameters->pvTaskCode,
+                        pxTaskParameters->pcTaskName,
+                        pxTaskParameters->uxStackDepthBytes,
+                        pxTaskParameters->pvParameters,
+                        pxTaskParameters->uxPriority,
+                        (struct tskTaskControlBlock ** const) pxCreatedTask);
+       else {
+           *pxCreatedTask = (rtosTaskHandle *)xTaskCreateStatic (
+                        pxTaskParameters->pvTaskCode,
+                        pxTaskParameters->pcTaskName,
+                        pxTaskParameters->uxStackDepthBytes,
+                        pxTaskParameters->pvParameters,
+                        pxTaskParameters->uxPriority,
+                        pxTaskParameters->pcStackBuffer,
+                        pxTaskParameters->pxTCB);
+
+           return rtosPASS;
+       }
+}
+
+/**
+ * @brief Delete a task
+ *
+ * This function is a wrapper for xTaskDelete() in FreeRTOS to delete a task.
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * - Scheduler is in running state if the request is to delete the calling task
+ *
+ * @param[in] pxTaskToDelete Input task handle
+ *
+ * @retval rtosPASS          On success
+ */
+static inline rtosError
+rtosTaskDelete(rtosTaskHandle pxTaskToDelete)
+{
+    vTaskDelete(pxTaskToDelete);
+    return rtosPASS;
+}
+
+/**
+ * @brief Delay a task for required time
+ *
+ * This function is a wrapper for xTaskDelay() in FreeRTOS.
+ * Places active task in blocked state for fixed number of cycles.
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ *
+ * @param[in] xTicksToDelay Time in ticks to delay the task. A value of 0
+ *                          will cause the task to yield instead of entering the
+ *                          blocked state
+ *
+ * @retval rtosPASS         On success
+ */
+static inline rtosError
+rtosTaskDelay(rtosTick xTicksToDelay)
+{
+    vTaskDelay(xTicksToDelay);
+    return rtosPASS;
+}
+
+/**
+ * @brief Delay a task until specified time.
+ *
+ * This function is a wrapper for xTaskDelayUntil() in FreeRTOS.
+ * It delays active task for a fixed period and wakes it
+ * up again at tick(previous wake time + Delay time).
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxPreviousWakeTime Pointer to variable of type rtosTick
+ *                               having previous wake time. Must be initialized
+ *                               with current time before first use. Updated
+ *                               automatically by this call thereafter.
+ * @param[in] xTimeIncrement     Time for which task must be delayed
+ *                               (Cycle time period)
+ *
+ * @retval rtosPASS              On success
+ */
+static inline rtosError
+rtosTaskDelayUntil(rtosTick *pxPreviousWakeTime,
+                   rtosTick xTimeIncrement)
+{
+    vTaskDelayUntil(pxPreviousWakeTime, xTimeIncrement);
+    return rtosPASS;
+}
+
+/**
+ * @brief Get priority of task
+ *
+ * This function is a wrapper for xTaskPriorityGet() in FreeRTOS.
+ * It updates value at pointer to variable of type
+ * rtosPriority sent as an argument with latest priority of input task
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxTask      Input task handle
+ * @param[in] puxPriority Pointer to a variable holding task priority
+ *
+ * @retval The priority of xTask
+ */
+static inline rtosError
+rtosTaskPriorityGet(rtosTaskHandle pxTask,
+                    rtosPriority *puxPriority)
+{
+    return uxTaskPriorityGet(pxTask);
+}
+
+/**
+ * @brief Set priority of a task
+ *
+ * This function is a wrapper for xTaskPrioritySet() in FreeRTOS to
+ * change the priority of a task.
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxTask        Input task handle
+ * @param[in] uxNewPriority Input task priority. Maximum priority
+ *                          is (configMAX_PRIORITIES - 1)
+ *
+ * @retval rtosPASS         On success
+ */
+static inline rtosError
+rtosTaskPrioritySet(rtosTaskHandle pxTask,
+                    rtosPriority uxNewPriority)
+{
+    vTaskPrioritySet(pxTask, uxNewPriority);
+    return rtosPASS;
+}
+
+/**
+ * @brief Suspend a task
+ *
+ * This function is a wrapper for xTaskSuspend() in FreeRTOS.
+ * Places active task in suspended state
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxTaskToSuspend Input task handle. Value of NULL
+ *                            suspends the calling task
+ *
+ * @retval rtosPASS           On success
+ */
+static inline rtosError
+rtosTaskSuspend(rtosTaskHandle pxTaskToSuspend)
+{
+    vTaskSuspend(pxTaskToSuspend);
+    return rtosPASS;
+}
+
+/**
+ * @brief Resume a suspended task
+ *
+ * This function is a wrapper for xTaskResume() in FreeRTOS.
+ * Resumes a suspended task and puts it ready state.
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * - The task being referred was suspended.
+ *
+ * @param[in] pxTaskToResume Input task handle
+ *
+ * @retval rtosPASS          On success
+ */
+static inline rtosError
+rtosTaskResume(rtosTaskHandle pxTaskToResume)
+{
+    vTaskResume(pxTaskToResume);
+    return rtosPASS;
+}
+
+/**
+ * @brief Get handle of current task
+ *
+ * This function is a wrapper for xTaskGetCurrentTaskHandle() in FreeRTOS.
+ * It returns handle of current task.
+ * No input arguments needed.
+ *
+ * @pre
+ * - Scheduler has been initialized and started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @retval xHandle Handle of the current task
+ */
+static inline rtosTaskHandle
+rtosTaskGetCurrentTaskHandle(void)
+{
+    return xTaskGetCurrentTaskHandle();
+}
+
+/**
+ * @brief Start a task scheduler
+ *
+ * This function is a wrapper for xTaskStartScheduler() in FreeRTOS.
+ * It starts scheduler if a set of preconditions are met.
+ * This can be ignored by passing input argument xUserKernelConfigurationChecks
+ * as rtosFALSE in which case scheduler will start regardless of the state.
+ *
+ * @pre
+ * - Scheduler has been initialized
+ *
+ * - A task has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context
+ *
+ * - Called with CPU in privileged mode
+ *
+ * @param[in] xUserKernelConfigurationChecks Bool variable to be set for
+ *                                           checking the pre-conditions before
+ *                                           starting the scheduler.
+ *
+ * @retval rtsoPASS                          On success
+ */
+static inline rtosError
+rtosTaskStartScheduler(rtosBool xUserKernelConfigurationChecks)
+{
+    vTaskStartScheduler();
+    return rtosPASS;
+}
+
+/**
+ * @brief Suspend a scheduler
+ *
+ * This function is a wrapper for xTaskSuspendScheduler() in FreeRTOS
+ * It suspends scheduler irrespective of current state.
+ * No input arguments needed and returns none.
+ *
+ * @pre
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ */
+static inline void
+rtosTaskSuspendScheduler(void)
+{
+    vTaskSuspendAll();
+}
+
+/**
+ * @brief Resume suspended scheduler
+ *
+ * This function is a wrapper for xTaskResumeScheduler() in FreeRTOS.
+ * Transitions the suspended scheduler into active state.
+ * No input arguments needed.
+ *
+ * @pre
+ * - Scheduler has been started and currently in a suspended state
+ *
+ * - Called from a non-interrupt context
+ *
+ * @retval rtosPASS                       On success
+ * @retval rtosFAIL                       On failure
+ */
+static inline rtosBool
+rtosTaskResumeScheduler(void)
+{
+    return (rtosBool)xTaskResumeAll();
+}
+
+/**
+ * @brief Get ticks count
+ *
+ * This function is a wrapper for xTaskGetTickCount() in FreeRTOS.
+ * It returns ticks count since the scheduler was started.
+ * No input arguments needed.
+ *
+ * @pre
+ * - Called from a non-interrupt context.
+ *
+ * @retval xTicks Number of ticks passed since scheduler was started.
+ */
+static inline rtosTick
+rtosTaskGetTickCount(void)
+{
+    return xTaskGetTickCount();
+}
+
+/**
+ * @brief Get ticks count from ISR
+ *
+ * This function is a wrapper for xTaskGetTickCountFromISR() in FreeRTOS.
+ * Returns ticks count in an interrupt context since the scheduler was started.
+ * No input arguments needed.
+ *
+ * @pre
+ * - Called from an interrupt context
+ *
+ * @retval xTicks Number of ticks passed since scheduler was started.
+ */
+static inline rtosTick
+rtosTaskGetTickCountFromISR(void)
+{
+    return xTaskGetTickCountFromISR();
+}
+
+/**
+ * @brief Request task yield.
+ *
+ * This function is a wrapper for taskYIELD() in FreeRTOS.
+ * It enables yield to a task of equal/higher priority
+ * than current task. No input arguments needed and returns none.
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ */
+static inline void
+rtosTaskYield(void)
+{
+    taskYIELD();
+}
+
+/**
+ * @brief Request task yield from ISR
+ *
+ * This function is a wrapper for taskYIELD_FROM_ISR() in FreeRTOS.
+ * It enables yield in an interrupt context to a task of
+ * equal/higher priority than current task. Returns none.
+ * Does nothing if input argument is rtosFALSE.
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] xSwitchRequired Bool variable to indicate need for switch
+ */
+static inline void
+rtosTaskYieldFromISR(rtosPortBaseType xSwitchRequired)
+{
+    portYIELD_FROM_ISR(xSwitchRequired);
+}
+
+/**
+ * @brief Enter critical section
+ *
+ * This function is a wrapper for taskENTER_CRITICAL() in FreeRTOS.
+ * Enables a task to enter critical section.
+ * No input arguments needed and returns none.
+ *
+ * @pre
+ * - Called from a non-interrupt context
+ *
+ */
+static inline void
+rtosTaskEnterCritical(void)
+{
+    taskENTER_CRITICAL();
+}
+
+/**
+ * @brief Exit critical section
+ *
+ * This function is a wrapper for taskEXIT_CRITICAL() in FreeRTOS.
+ * Enables a task to exit from critical section.
+ * No input arguments needed and returns none.
+ *
+ * @pre
+ * - RTOS state must already be in critical section
+ *
+ * - Called from a non-interrupt context
+ *
+ */
+static inline void
+rtosTaskExitCritical(void)
+{
+    taskEXIT_CRITICAL();
+}
+
+
+/**
+ * @brief Disable interrupts
+ *
+ * This function is a wrapper for taskDISABLE_INTERRUPTS() in FreeRTOS.
+ * Disable all maskable interrupts
+ * No input arguments needed and returns none.
+ *
+ * @pre
+ * - RTOS state must already be in critical section
+ *
+ * - Called from a non-interrupt context
+ *
+ */
+static inline void
+rtosTaskDisableInterrupts(void)
+{
+    taskDISABLE_INTERRUPTS();
+}
+
+/**
+ * @brief Enable interrupts
+ *
+ * This function is a wrapper for taskENABLE_INTERRUPTS() in FreeRTOS.
+ * Enable all maskable interrupts
+ * No input arguments needed and returns none.
+ *
+ * @pre
+ * - RTOS state must already be in critical section
+ *
+ * - Called from a non-interrupt context
+ *
+ */
+static inline void
+rtosTaskEnableInterrupts(void)
+{
+    taskENABLE_INTERRUPTS();
+}
+
+/**
+ * @brief Retrieve scheduler status
+ *
+ * This function is a wrapper for xTaskIsSchedulerStarted() in FreeRTOS.
+ * Checks and returns true if there has been a successful call to
+ * rtosTaskStartScheduler()
+ * No input arguments
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @retval rtosTRUE  Scheduler has been started
+ * @retval rtosFALSE Otherwise
+ */
+static inline rtosBool
+rtosTaskIsSchedulerStarted(void)
+{
+    return (rtosBool)xTaskGetSchedulerState();
+}
+
+/**
+ * @brief Generate system tick
+ *
+ * This function is a wrapper for FreeRTOS_Tick_Handler() in FreeRTOS.
+ * It is used to generate system tick and should be called from the
+ * system tick handler.
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * No input arguments needed and returns none.
+ */
+static inline void rtosSystemTickHandler(void)
+{
+    FreeRTOS_Tick_Handler();
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-timer.h b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-timer.h
new file mode 100644
index 0000000..f4f20fc
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-timer.h
@@ -0,0 +1,333 @@
+/* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_TIMER_H
+#define OSA__OSA_TIMER_H
+#define FSP__OSA__OSA_TIMER_H                           1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosError, rtosTimerHandle, rtosTic
+#include <osa/osa-values.h>             // for rtosPASS
+#include <timers.h>                     // IWYU pragma: export
+                                        // IWYU pragma: no_include "timers.h"
+                                        // for pvTimerGetTimerID, xTimerIsTimerActive
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+
+/**
+ * @brief Create a timer.
+ *
+ * This function is a wrapper for xTimerCreate() in FreeRTOS.
+ * It updates the handle sent as
+ * an argument to point to the newly created timer
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle timer control block and instance parameters
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxTimerParameters Pointer to timer init parameter
+ *                              structure (rtosTimerInitParametersType)
+ * @param[out] pxTimerHandle    Pointer to timer handle
+ *
+ * @retval rtosPASS                           on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED     Null pointer to timer init
+ *                                            parameter/Timer handle
+ * @retval E_RTOS_INVALID_PARAMETERS          Invalid timer init parameters
+ * @retval E_RTOS_INVALID_TIMER_TASK_INSTANCE Invalid timer task instance
+ * @retval E_RTOS_TIMER_ALREADY_IN_USE        Input Timer handle is valid
+ *                                            and must be deleted before
+ *                                            creating a new timer
+ */
+rtosError
+rtosTimerCreate(const rtosTimerInitParametersType *const pxTimerParameters,
+                rtosTimerHandle *pxTimerHandle);
+
+/**
+ * @brief Start a timer
+ *
+ * This function is a wrapper for xTimerStart() in FreeRTOS.
+ * Calling task is held in blocked state for block time before successfully
+ * sending the start command to the timer
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xTimer     Timer handle
+ * @param[in] xBlockTime Block time in ticks
+ *
+ * @retval rtosPASS      On success
+ * @retval rtosFAIL      On failure
+ */
+static inline rtosError
+rtosTimerStart(rtosTimerHandle xTimer,
+               rtosTick xBlockTime)
+{
+    return xTimerStart(xTimer, xBlockTime);
+}
+
+/**
+ * @brief Stop a timer
+ *
+ * This function is a wrapper for xTimerStop() in FreeRTOS.
+ * Calling task is held in blocked state for block time before successfully
+ * sending stop command to the timer
+ *
+ * @pre
+ * - Referred timer has been started
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xTimer     Timer handle
+ * @param[in] xBlockTime Block time in ticks
+ *
+ * @retval rtosPASS      On success
+ * @retval rtosFAIL      On failure
+ */
+static inline rtosError
+rtosTimerStop(rtosTimerHandle xTimer,
+              rtosTick xBlockTime)
+{
+    return xTimerStop(xTimer, xBlockTime);
+}
+
+/**
+ * @brief Change timer period
+ *
+ * This function is a wrapper for xTimerChangePeriod() in FreeRTOS.
+ * Calling task is held in blocked state for block time before successfully
+ * sending change period command to the timer
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xTimer            Timer handle
+ * @param[in] xBlockTime        Block time in ticks
+ * @param[in] xNewPeriodInTicks New timer period in ticks. Should be
+ *                              greater than 0.
+ *
+ * @retval rtosPASS             On success
+ * @retval rtosFAIL             On failure
+ */
+static inline rtosError
+rtosTimerChangePeriod(rtosTimerHandle xTimer,
+                      rtosTick xNewPeriodInTicks,
+                      rtosTick xBlockTime)
+{
+    return xTimerChangePeriod(xTimer, xNewPeriodInTicks, xBlockTime);
+}
+
+/**
+ * @brief Delete a timer
+ *
+ * This function is a wrapper for xTimerDelete() in FreeRTOS.
+ * Calling task is held in blocked state for block time before successfully
+ * sending delete command to the timer
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xTimer     Timer handle
+ * @param[in] xBlockTime Block time in ticks
+ *
+ * @retval rtosPASS      On success
+ * @retval rtosFAIL      On failure
+ */
+static inline rtosError
+rtosTimerDelete(rtosTimerHandle xTimer,
+                rtosTick xBlockTime)
+{
+    return xTimerDelete(xTimer, xBlockTime);
+}
+
+// ISR friendly commands of the timer commands
+
+/**
+ * @brief Start a timer from ISR
+ *
+ * This function is a wrapper for xTimerStartFromISR() in FreeRTOS.
+ * It sets value at pxHigherPriorityTaskWoken if calling this function
+ * unblocks the timer service whose priority is equal to/higher than
+ * the current task
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xTimer                     Timer handle
+ * @param[out] pxHigherPriorityTaskWoken Pointer to rtosBool variable
+ *                                       to indicate current context
+ *
+ * @retval rtosPASS                      On success
+ * @retval rtosFAIL                      On failure
+ */
+static inline rtosError
+rtosTimerStartFromISR(rtosTimerHandle xTimer,
+                      rtosBool *pxHigherPriorityTaskWoken)
+{
+    return xTimerStartFromISR(xTimer, pxHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Stop a timer from ISR
+ *
+ * This function is a wrapper for xTimerStopFromISR() in FreeRTOS.
+ * It sets value at pxHigherPriorityTaskWoken if calling this function unblocks
+ * the timer service whose priority is equal to/higher than the current task
+ *
+ * @pre
+ * - Referred timer has been started
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xTimer                     Timer handle
+ * @param[out] pxHigherPriorityTaskWoken Pointer to rtosBool variable
+ *                                       to indicate current context
+ *
+ * @retval rtosPASS                      On success
+ * @retval rtosFAIL                      On failure
+ */
+static inline rtosError
+rtosTimerStopFromISR(rtosTimerHandle xTimer,
+                     rtosBool *pxHigherPriorityTaskWoken)
+{
+    return xTimerStopFromISR(xTimer, pxHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Change timer period from ISR
+ *
+ * This function is a wrapper for xTimerChangePeriodFromISR() in FreeRTOS.
+ * It sets value at pxHigherPriorityTaskWoken if calling this function unblocks
+ * the timer service whose priority is equal to/higher than the current task
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xTimer                     Timer handle
+ * @param[in] xNewPeriodInTicks          New timer period in ticks. Should be
+ *                                       greater than 0.
+ * @param[out] pxHigherPriorityTaskWoken Pointer to rtosBool variable
+ *                                       to indicate current context
+ *
+ * @retval rtosPASS                      On success
+ * @retval rtosFAIL                      On failure
+ */
+static inline rtosError
+rtosTimerChangePeriodFromISR(rtosTimerHandle xTimer,
+                             rtosTick xNewPeriodInTicks,
+                             rtosBool *pxHigherPriorityTaskWoken)
+{
+    return xTimerChangePeriodFromISR(xTimer, xNewPeriodInTicks,
+                                     pxHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Check if timer is active
+ *
+ * This function is a wrapper for xTimerIsTimerActive() in FreeRTOS.
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xTimer Timer handle
+ *
+ * @retval rtosTRUE                    if timer is active or exists in the
+ *                                     overflow timer list
+ * @retval rtosFALSE                   Timer not present in the active timer
+ */
+static inline rtosError
+rtosTimerIsTimerActive(rtosTimerHandle xTimer)
+{
+    return xTimerIsTimerActive(xTimer);
+}
+
+/**
+ * @brief Get timer ID
+ *
+ * This function is a wrapper for xTimerGetTimerID() in FreeRTOS.
+ * It updates value at pxTimerID with ID of the requested timer
+ * configured by the host application while creating it.
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in]  xTimer    Timer handle
+ * @param[out] pxTimerID Pointer to timer ID
+ *
+ * @retval rtosPASS      For valid timers
+ */
+static inline rtosError
+rtosTimerGetTimerID(rtosTimerHandle xTimer, rtosTimerIDType *pxTimerID)
+{
+    pvTimerGetTimerID(xTimer);
+    return rtosPASS;
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-values.h b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-values.h
new file mode 100644
index 0000000..e20fb5d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/osa-values.h
@@ -0,0 +1,113 @@
+/* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_VALUES_H
+#define OSA__OSA_VALUES_H
+#define FSP__OSA__OSA_VALUES_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for pdFALSE, pdTRUE, pdFAIL, pdPASS
+
+/**
+ * @brief Mapping of FreeRTOS values to rtos value space
+ *
+ * @macro-title RTOS boolean values published by OSA layer
+ *
+ * @rtosTRUE  Defines true state of a boolean variable
+ * @rtosFALSE Defines false state of a boolean variable
+ * @rtosPASS  Defines return value indicating success
+ * @rtosFAIL  Defines return value indicating failure
+ */
+#define rtosTRUE                                ((rtosBool)pdTRUE)
+#define rtosFALSE                               ((rtosBool)pdFALSE)
+#define rtosPASS                                pdPASS
+#define rtosFAIL                                pdFAIL
+
+/**
+ * @brief Mapping of FreeRTOS kernel version values to rtos value space
+ *
+ * @macro-title Kernel version values published by OSA layer.
+ *
+ * @rtosKERNEL_MAJOR_VERSION Defines kernel major version number
+ * @rtosKERNEL_MINOR_VERSION Defines kernel minor version number
+ */
+#define rtosKERNEL_VERSION_NUMBER               tskKERNEL_VERSION_NUMBER
+#define rtosKERNEL_MAJOR_VERSION                tskKERNEL_VERSION_MAJOR
+#define rtosKERNEL_MINOR_VERSION                tskKERNEL_VERSION_MINOR
+#define rtosKERNEL_MINOR_BUILD                  tskKERNEL_VERSION_BUILD
+
+/**
+ * @brief Mapping of FreeRTOS event group values to rtos value space
+ *
+ * @macro-title Event group values published by OSA layer
+ *
+ * @rtosEVENTGRP_CLEAR_EVENTS_ON_EXIT Defines bit-mask mapped to eventgroup
+ *                                    control flag set to clear event group
+ *                                    bits on exit
+ * @rtosEVENTGRP_WAIT_FOR_ALL_BITS    Defines bit-mask mapped to eventgroup
+ *                                    control flag, set to wait until all the
+ *                                    requested event group bits are set.
+ */
+#define rtosEVENTGRP_CLEAR_EVENTS_ON_EXIT       eventCLEAR_EVENTS_ON_EXIT_BIT
+#define rtosEVENTGRP_WAIT_FOR_ALL_BITS          eventWAIT_FOR_ALL_BITS
+#define rtosEVENTGRP_UNBLOCKED_DUE_TO_BIT_SET   eventUNBLOCKED_DUE_TO_BIT_SET
+#define rtosEVENTGRP_BITS_CONTROL_BYTES         eventEVENT_BITS_CONTROL_BYTES
+
+/**
+ * @brief Mapping of FreeRTOS mutex values to rtos value space
+ *
+ * @macro-title Mutex state values published by OSA layer
+ *
+ * @rtosMUTEX_AVAILABLE Defines state of a mutex object indicating lock is
+ *                      available
+ * @rtosMUTEX_TAKEN     Defines state of a mutex object indicating lock is
+ *                      acquired
+ */
+#define rtosMUTEX_TAKEN                         pdTRUE
+#define rtosMUTEX_AVAILABLE                     pdFALSE
+
+/**
+ * @brief Mapping of FreeRTOS semaphore values to rtos value space
+ *
+ * @macro-title Semaphore value published by OSA layer
+ *
+ * @rtosSEMA_GIVE_NOBLOCK Defines macro to be used for setting semaphore block
+ *                        time as 0.
+ */
+#define rtosSEMA_GIVE_NOBLOCK                   semGIVE_BLOCK_TIME
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/sections-osa.h b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/sections-osa.h
new file mode 100644
index 0000000..3f28b19
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/freertosv10/osa/sections-osa.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef OSA__SECTIONS_OSA_H
+#define OSA__SECTIONS_OSA_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>   // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>  // for SECTION, FSP__MISC__ATTRIBUTES_H
+#include <misc/macros.h>      // for SECTION_BUILDER, STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_OSA_DATA           SECTION_BUILDER(osa,                    data)
+#define SECTION_NAME_OSA_RODATA         SECTION_BUILDER(osa,                    rodata)
+#define SECTION_NAME_OSA_TEXT           SECTION_BUILDER(osa,                    text)
+#define SECTION_NAME_OSA_CREATE_TEXT    SECTION_BUILDER(create.osa,             text)
+#define SECTION_NAME_OSA_INIT_DATA      SECTION_BUILDER(init.osa,               data)
+#define SECTION_NAME_OSA_INIT_TEXT      SECTION_BUILDER(init.osa,               text)
+
+#define SECTION_STR_OSA_TEXT            STR(SECTION_NAME_OSA_TEXT)
+#define SECTION_STR_OSA_RODATA          STR(SECTION_NAME_OSA_RODATA)
+#define SECTION_STR_OSA_DATA            STR(SECTION_NAME_OSA_DATA)
+#define SECTION_STR_OSA_INIT_TEXT       STR(SECTION_NAME_OSA_INIT_TEXT)
+#define SECTION_STR_OSA_INIT_DATA       STR(SECTION_NAME_OSA_INIT_DATA)
+#define SECTION_STR_OSA_CREATE_TEXT     STR(SECTION_NAME_OSA_CREATE_TEXT)
+
+#define SECTION_OSA_TEXT                SECTION(SECTION_STR_OSA_TEXT)
+#define SECTION_OSA_RODATA              SECTION(SECTION_STR_OSA_RODATA)
+#define SECTION_OSA_DATA                SECTION(SECTION_STR_OSA_DATA)
+#define SECTION_OSA_INIT_TEXT           SECTION(SECTION_STR_OSA_INIT_TEXT)
+#define SECTION_OSA_INIT_DATA           SECTION(SECTION_STR_OSA_INIT_DATA)
+#define SECTION_OSA_CREATE_TEXT         SECTION(SECTION_STR_OSA_CREATE_TEXT)
+
+#endif
+
diff --git a/spe-freertos-bsp/fsp/source/include/osa/littlekernel/arm/armv8/cortex-r52/ospl/rtos-port.h b/spe-freertos-bsp/fsp/source/include/osa/littlekernel/arm/armv8/cortex-r52/ospl/rtos-port.h
new file mode 100644
index 0000000..db4609a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/littlekernel/arm/armv8/cortex-r52/ospl/rtos-port.h
@@ -0,0 +1,90 @@
+/* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSPL__RTOS_PORT_H
+#define OSPL__RTOS_PORT_H
+#define FSP__OSPL__RTOS_PORT_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+/*
+ * Port specific types and data structures needed by nvosRTOS.h
+ *
+ * This file should not be included directly from any other file.
+ */
+
+/* Declarations from <portmacro.h>      */
+typedef unsigned long           portBaseType;
+
+/* Declarations from <rtos-port.h>      */
+typedef portBaseType            rtosBool;
+
+/* Declarations from <projdefs.h>       */
+#define pdTRUE                  ( ( portBaseType ) 1 )
+#define pdFALSE                 ( ( portBaseType ) 0 )
+
+/**
+ * @brief Provide wrapper type definitions for RTOS values to avoid exposing the
+ * SafeRTOS types directly.
+ *
+ * @typedef-title OSA variable type space
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+typedef portBaseType            rtosBool;
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/littlekernel/osa/osa-task.h b/spe-freertos-bsp/fsp/source/include/osa/littlekernel/osa/osa-task.h
new file mode 100644
index 0000000..d780e4a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/littlekernel/osa/osa-task.h
@@ -0,0 +1,118 @@
+/* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_TASK_H
+#define OSA__OSA_TASK_H
+#define FSP__OSA__OSA_TASK_H                            1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosBool, rtosTaskHandle, rtosTick, rtos...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+
+typedef void                    *rtosTaskHandle;
+
+void enter_critical_section(void);
+void exit_critical_section(void);
+
+#define rtosTaskEnterCritical() enter_critical_section()
+#define rtosTaskExitCritical() exit_critical_section()
+
+/**
+ * @brief Request task yield from ISR
+ *
+ * This function is a wrapper for taskYIELD_FROM_ISR() in SafeRTOS.
+ * It enables yield in an interrupt context to a task of
+ * equal/higher priority than current task. Returns none.
+ * Does nothing if input argument is rtosFALSE.
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @func_req_id 8219153
+ *
+ * @param[in] xSwitchRequired Bool variable to indicate need for switch
+ */
+static inline void
+rtosTaskYieldFromISR(rtosBool xSwitchRequired)
+{
+    UNUSED( xSwitchRequired );
+}
+
+/**
+ * @brief Generate system tick
+ *
+ * This function is a wrapper for vTaskProcessSystemTickFromISR() in Little Kernel.
+ * It is used to generate system tick and should be called from the
+ * system tick handler.
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * No input arguments needed and returns none.
+ */
+static inline void rtosSystemTickHandler(void)
+{
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/littlekernel/osa/osa-values.h b/spe-freertos-bsp/fsp/source/include/osa/littlekernel/osa/osa-values.h
new file mode 100644
index 0000000..cbcb73f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/littlekernel/osa/osa-values.h
@@ -0,0 +1,64 @@
+/* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_VALUES_H
+#define OSA__OSA_VALUES_H
+#define FSP__OSA__OSA_VALUES_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // for rtosMutexHandle, FSP__OSPL__RTOS_PORT_H
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+/**
+ * @brief Mapping of SafeRTOS values to rtos value space
+ *
+ * @macro-title RTOS boolean values published by OSA layer
+ *
+ * @rtosTRUE  Defines true state of a boolean variable
+ * @rtosFALSE Defines false state of a boolean variable
+ * @rtosPASS  Defines return value indicating success
+ * @rtosFAIL  Defines return value indicating failure
+ */
+#define rtosTRUE                                ((rtosBool)pdTRUE)
+#define rtosFALSE                               ((rtosBool)pdFALSE)
+#define rtosPASS                                pdPASS
+#define rtosFAIL                                pdFAIL
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/rtos-errors.h b/spe-freertos-bsp/fsp/source/include/osa/rtos-errors.h
new file mode 100644
index 0000000..5fad891
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/rtos-errors.h
@@ -0,0 +1,63 @@
+/* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef OSA__RTOS_ERRORS_H
+#define OSA__RTOS_ERRORS_H
+#define FSP__OSA__RTOS_ERRORS_H                        1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <osa/osa-errors.h>      // IWYU pragma: export
+                                 // IWYU pragma: no_include "osa/osa-errors.h"
+#include <misc/macros.h>         // for START_RFD_BLOCK, END_RFD_BLOCK, ...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSA__OSA_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/rtos-event-group.h b/spe-freertos-bsp/fsp/source/include/osa/rtos-event-group.h
new file mode 100644
index 0000000..5b6178b
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/rtos-event-group.h
@@ -0,0 +1,64 @@
+/* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__RTOS_EVENT_GROUP_H
+#define OSA__RTOS_EVENT_GROUP_H
+#define FSP__OSA__RTOS_EVENT_GROUP_H                   1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific headers */
+#include <osa/osa-event-group.h>         // IWYU pragma: export
+                                         // IWYU pragma: no_include "osa/osa-event-group.h"
+#include <misc/macros.h>                 // for START_RFD_BLOCK, END_RFD_BLOCK, ...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSA__OSA_EVENT_GROUP_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/rtos-event-poll.h b/spe-freertos-bsp/fsp/source/include/osa/rtos-event-poll.h
new file mode 100644
index 0000000..79f270c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/rtos-event-poll.h
@@ -0,0 +1,58 @@
+/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__RTOS_EVENT_POLL_H
+#define OSA__RTOS_EVENT_POLL_H
+#define FSP__OSA__RTOS_EVENT_POLL_H                    1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <osa/osa-event-poll.h>  // IWYU pragma: export
+                                 // IWYU pragma: no_include "osa/osa-event-poll.h"
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSA__OSA_EVENT_POLL_H, "Header file missing or invalid.")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/rtos-mutex.h b/spe-freertos-bsp/fsp/source/include/osa/rtos-mutex.h
new file mode 100644
index 0000000..52c3d2a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/rtos-mutex.h
@@ -0,0 +1,58 @@
+/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__RTOS_MUTEX_H
+#define OSA__RTOS_MUTEX_H
+#define FSP__OSA__RTOS_MUTEX_H                         1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <osa/osa-mutex.h>       // IWYU pragma: export
+                                 // IWYU pragma: no_include "osa/osa-mutex.h"
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSA__OSA_MUTEX_H, "Header file missing or invalid.")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/rtos-priv.h b/spe-freertos-bsp/fsp/source/include/osa/rtos-priv.h
new file mode 100644
index 0000000..8ce8607
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/rtos-priv.h
@@ -0,0 +1,40 @@
+/* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__RTOS_PRIV_H
+#define OSA__RTOS_PRIV_H
+#define FSP__OSA__RTOS_PRIV_H                          1
+
+/*
+ * Copy parameter value from one variable type to another
+ * provided the parameter names are identical in both the variable
+ * types
+ */
+#define SETFIELD(_d_, _s_, _f_)                 (_d_)->_f_ = (_s_)->_f_
+#define SETFIELD_t(_d_, _st_, _s_, _f_)         (_d_)->_f_ = (_st_)(_s_)->_f_
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/rtos-queue.h b/spe-freertos-bsp/fsp/source/include/osa/rtos-queue.h
new file mode 100644
index 0000000..1b03372
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/rtos-queue.h
@@ -0,0 +1,58 @@
+/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__RTOS_QUEUE_H
+#define OSA__RTOS_QUEUE_H
+#define FSP__OSA__RTOS_QUEUE_H                         1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific headers */
+#include <osa/osa-queue.h>       // IWYU pragma: export
+                                 // IWYU pragma: no_include "osa/osa-queue.h"
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSA__OSA_QUEUE_H, "Header file missing or invalid.")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/rtos-semaphore.h b/spe-freertos-bsp/fsp/source/include/osa/rtos-semaphore.h
new file mode 100644
index 0000000..cbb1880
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/rtos-semaphore.h
@@ -0,0 +1,58 @@
+/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__RTOS_SEMAPHORE_H
+#define OSA__RTOS_SEMAPHORE_H
+#define FSP__OSA__RTOS_SEMAPHORE_H                     1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific headers */
+#include <osa/osa-semaphore.h>   // IWYU pragma: export
+                                 // IWYU pragma: no_include "osa/osa-semaphore.h"
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSA__OSA_SEMAPHORE_H, "Header file missing or invalid.")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/rtos-task.h b/spe-freertos-bsp/fsp/source/include/osa/rtos-task.h
new file mode 100644
index 0000000..7c91000
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/rtos-task.h
@@ -0,0 +1,63 @@
+/* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__RTOS_TASK_H
+#define OSA__RTOS_TASK_H
+#define FSP__OSA__RTOS_TASK_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>        // For START_RFD_BLOCK, END_RFD_BLOCK, ...
+
+/* Module-specific headers */
+#include <osa/osa-task.h>       // IWYU pragma: export
+                                // IWYU pragma: no_include "osa/osa-task.h"
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSA__OSA_TASK_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/rtos-timer.h b/spe-freertos-bsp/fsp/source/include/osa/rtos-timer.h
new file mode 100644
index 0000000..1f91315
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/rtos-timer.h
@@ -0,0 +1,59 @@
+/* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__RTOS_TIMER_H
+#define OSA__RTOS_TIMER_H
+#define FSP__OSA__RTOS_TIMER_H                         1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <osa/osa-timer.h>       // IWYU pragma: export
+                                 // IWYU pragma: no_include "osa/osa-timer.h"
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+CT_ASSERT(FSP__OSA__OSA_TIMER_H, "Header file missing or invalid.")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/rtos-values.h b/spe-freertos-bsp/fsp/source/include/osa/rtos-values.h
new file mode 100644
index 0000000..6d80182
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/rtos-values.h
@@ -0,0 +1,66 @@
+/* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__RTOS_VALUES_H
+#define OSA__RTOS_VALUES_H
+#define FSP__OSA__RTOS_VALUES_H                        1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>         // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <osa/osa-values.h>      // IWYU pragma: export
+                                 // IWYU pragma: no_include "osa/osa-values.h"
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__OSA_VALUES_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/rtos.h b/spe-freertos-bsp/fsp/source/include/osa/rtos.h
new file mode 100644
index 0000000..8591a62
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/rtos.h
@@ -0,0 +1,82 @@
+/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__RTOS_H
+#define OSA__RTOS_H
+#define FSP__OSA__RTOS_H                               1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <osa/rtos-values.h>             // IWYU pragma: export
+                                         // IWYU pragma: no_include "osa/rtos-values.h"
+#include <osa/rtos-errors.h>             // IWYU pragma: export
+                                         // IWYU pragma: no_include "osa/rtos-errors.h"
+#include <osa/rtos-task.h>               // IWYU pragma: export
+                                         // IWYU pragma: no_include "osa/rtos-task.h"
+#include <osa/rtos-timer.h>              // IWYU pragma: export
+                                         // IWYU pragma: no_include "osa/rtos-timer.h"
+#include <osa/rtos-queue.h>              // IWYU pragma: export
+                                         // IWYU pragma: no_include "osa/rtos-queue.h"
+#include <osa/rtos-semaphore.h>          // IWYU pragma: export
+                                         // IWYU pragma: no_include "osa/rtos-semaphore.h"
+#include <osa/rtos-mutex.h>              // IWYU pragma: export
+                                         // IWYU pragma: no_include "osa/rtos-mutex.h"
+#include <osa/rtos-event-group.h>        // IWYU pragma: export
+                                         // IWYU pragma: no_include "osa/rtos-event-group.h"
+#include <osa/rtos-event-poll.h>         // IWYU pragma: export
+                                         // IWYU pragma: no_include "osa/rtos-event-poll.h"
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSA__RTOS_VALUES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_TIMER_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_QUEUE_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_SEMAPHORE_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_MUTEX_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_EVENT_GROUP_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_EVENT_POLL_H, "Header file missing or invalid.")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv8/arm/armv7/cortex-r5/ospl/rtos-port-asm.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/arm/armv7/cortex-r5/ospl/rtos-port-asm.h
new file mode 100644
index 0000000..4af972b
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/arm/armv7/cortex-r5/ospl/rtos-port-asm.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2021-2022 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef OSPL__RTOS_PORT_ASM_H
+#define OSPL__RTOS_PORT_ASM_H
+#define FSP__OSPL__RTOS_PORT_ASM_H
+
+/* Compiler headers */
+#if defined(SAFERTOS_MINOR) && (SAFERTOS_MINOR>=2)
+#include <portIRQ.inc>
+#else
+#include <portIRQ.h>
+#endif
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+#ifdef __ASSEMBLER__
+
+.macro rtosIRQ_ENTRY
+    safertosIRQ_ENTRY
+    push        { R4-R11 }
+.endm
+
+.macro rtosIRQ_EXIT
+    pop         { R4-R11 }
+    safertosIRQ_EXIT
+.endm
+
+#endif /* #ifdef __ASSEMBLER__ */
+#endif /* #ifndef OSPL__RTOS_PORT_ASM_H */
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv8/arm/armv7/cortex-r5/ospl/rtos-port.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/arm/armv7/cortex-r5/ospl/rtos-port.h
new file mode 100644
index 0000000..23804d9
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/arm/armv7/cortex-r5/ospl/rtos-port.h
@@ -0,0 +1,349 @@
+/* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSPL__RTOS_PORT_H
+#define OSPL__RTOS_PORT_H
+#define FSP__OSPL__RTOS_PORT_H                          1
+
+/* Compiler headers */
+#include <stdint.h>                        // for uint32_t, int32_t, int16_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <SafeRTOSConfig.h>                // for configTICK_RATE_HZ, config...
+#include <portmacro.h>                     // IWYU pragma: export
+                                           // IWYU pragma: no_include "portmacro.h"
+#include <projdefs.h>                      // IWYU pragma: export
+                                           // IWYU pragma: no_include "projdefs.h"
+#include <portable.h>                      // IWYU pragma: export
+                                           // IWYU pragma: no_include "portable.h"
+#include <apiWrapper.h>                    // IWYU pragma: export
+                                           // IWYU pragma: no_include "apiWrapper.h"
+#include <portfeatures.h>                  // IWYU pragma: export
+                                           // IWYU pragma: no_include "portfeatures.h"
+#include <eventgroups.h>                   // for eventBitsType, eventGroupType
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <cpu/armv7-mpu-safertos.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__CONFIG__SAFERTOSCONFIG_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_MPU_SAFERTOS_H, "Header file missing or invalid.")
+
+/*
+ * Port specific types and data structures needed by nvosRTOS.h
+ *
+ * This file should not be included directly from any other file.
+ */
+
+/**
+ * @brief Make sure that the sizes of types defined by SafeRTOS are what they
+ * are expected to be.
+ */
+CT_ASSERT(sizeof(uint64_t) == sizeof(portUInt64Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(int64_t) == sizeof(portInt64Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(uint32_t) == sizeof(portUInt32Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(int32_t) == sizeof(portInt32Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(uint32_t) == sizeof(portUnsignedBaseType), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(int32_t) == sizeof(portBaseType), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(uint16_t) == sizeof(portUInt16Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(int16_t) == sizeof(portInt16Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(uint8_t) == sizeof(portUInt8Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(int8_t) == sizeof(portInt8Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(char) == sizeof(portCharType), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(uint32_t) == sizeof(portStackType), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(uint32_t) == sizeof(portTickType), "ASSERT due to data type mismatch.")
+
+/**
+ * @brief Provide wrapper type definitions for RTOS values to avoid exposing the
+ * SafeRTOS types directly.
+ *
+ * @typedef-title OSA variable type space
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+typedef portBaseType            rtosError;
+typedef void                    *rtosTaskHandle;
+typedef void                    *rtosEventGroupHandle;
+typedef eventGroupType          rtosEventGroup;
+typedef void                    *rtosQueueHandle;
+typedef void                    *rtosTimerHandle;
+typedef void                    *rtosTimerLocalStorageObject;
+typedef portUnsignedBaseType    rtosUCount;
+typedef portTickType            rtosTick;
+typedef portBaseType            rtosBool;
+typedef portBaseType            rtosTimerIDType;
+typedef void                    *rtosMutexHandle;
+typedef void                    *rtosSemaphoreHandle;
+typedef void                    *rtosEventPollHandle;
+typedef portUnsignedBaseType    rtosTaskNotifyBits;
+typedef portUnsignedBaseType    rtosEventPollValue;
+typedef portBaseType            rtosTaskNotifyAction;
+typedef portUnsignedBaseType    rtosTaskNotifyValue;
+typedef portUnsignedBaseType    rtosPriority;
+typedef portUnsignedBaseType    rtosInterruptState;
+typedef portUnsignedBaseType    rtosMutexState;
+typedef eventBitsType           rtosEventBits;
+typedef portUInt32Type          rtosHz;
+typedef portUnsignedBaseType    rtosPrivilegeLevel;
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @brief Sizes of objects that need to be statically allocated but whose
+ * contents are not visible to the application.
+ *
+ * @macro-title Macro definitions for size of kernel objects
+ *
+ * @rtosQUEUE_OVERHEAD_BYTES                    Defines size in bytes needed to
+ *                                              create a queue
+ * @rtosSEMAPHORE_OVERHEAD_BYTES                Defines size in bytes needed to
+ *                                              create a semaphore object
+ * @rtosMUTEX_OVERHEAD_BYTES                    Defines size in bytes needed to
+ *                                              create a mutex object
+ * @rtosEVENT_GROUP_OVERHEAD_BYTES              Defines size in bytes needed to
+ *                                              create an event group object
+ * @rtosTCB_OVERHEAD_BYTES                      Defines size in bytes needed for
+ *                                              task control block
+ * @rtosTIMER_CONTROL_BLOCK_OVERHEAD_BYTES      Defines size in bytes needed for
+ *                                              timer control block
+ * @rtosTIMER_INSTANCE_PARAMETER_OVERHEAD_BYTES Defines size in bytes needed for
+ *                                              timer instance parameters
+ * @rtosEVENT_POLL_OVERHEAD_BYTES               Defines size in bytes needed to
+ *                                              create an event poll object
+ */
+#define rtosQUEUE_OVERHEAD_BYTES                   portQUEUE_OVERHEAD_BYTES
+#define rtosSEMAPHORE_OVERHEAD_BYTES               portQUEUE_OVERHEAD_BYTES
+#define rtosMUTEX_OVERHEAD_BYTES                   portQUEUE_OVERHEAD_BYTES
+#define rtosEVENT_GROUP_OVERHEAD_BYTES             sizeof(eventGroupType)
+#define rtosTCB_OVERHEAD_BYTES                     sizeof(xTCB)
+#define rtosTIMER_CONTROL_BLOCK_OVERHEAD_BYTES     sizeof(timerControlBlockType)
+#define rtosTIMER_INSTANCE_PARAMETER_OVERHEAD_BYTES \
+        sizeof(struct timerInstanceParameters)
+#define rtosEVENT_POLL_OVERHEAD_BYTES(uxMaximumRegisteredObjectEvents) \
+        eventpollGET_REQUIRED_CREATE_BUFFER_SIZE(uxMaximumRegisteredObjectEvents)
+
+/**
+ * @brief Provide wrapper definition for pointer to RTOS task function.
+ */
+typedef pdTASK_CODE             rtosTaskFunction;
+
+/**
+ * @brief Provide a wrapper data type to encapsulate MPU related information
+ */
+typedef mpuParameters_t rtosMPURegionConfig;
+
+/**
+ * @brief Provide wrapper definition for pointer to RTOS timer callback function
+ * which gets invoked when a timer expires.
+ */
+typedef void (*rtosTimerCallbackFunction)(void * pvParameters);
+
+/**
+ * @brief Structure supplied to rtosTaskCreate()
+ *
+ * @pvTaskCode        Pointer to task entry function
+ * @pcTaskName        Task descriptive name
+ * @pxTCB             Pointer to task control block
+ * @pcStackBuffer     Pointer to task stack buffer
+ * @uxStackDepthBytes Size of task stack buffer in bytes. The minimum
+ *                    allowable size for the stack buffer is portdependent.
+ * @pvParameters      Pointer to task parameters
+ * @uxPriority        Priority of task.
+ *                    Valid range is [0 - (configMAX_PRIORITIES - 1])
+ * @pvObject          Pointer to user defined data associated with this task.
+ * @xUsingFPU         Bool to indicate use of FPU
+ * @uxPrivilegeLevel  Task Privilege level
+ * @pxMPUParameters   Pointer to task MPU parameters
+ */
+typedef struct {
+    rtosTaskFunction    pvTaskCode;
+    const char          *pcTaskName;
+    void                *pxTCB;
+    void                *pcStackBuffer;
+    rtosUCount          uxStackDepthBytes;
+    void                *pvParameters;
+    rtosPriority        uxPriority;
+    void                *pvObject;
+    rtosBool            xUsingFPU;
+    rtosPrivilegeLevel  uxPrivilegeLevel;
+    rtosMPURegionConfig *pxMPUParameters;
+} rtosTaskParameters;
+
+/**
+ * @brief Structure supplied to rtosTaskInitializeScheduler()
+ *
+ * @ulCPUClockHz                      Speed of the system clock
+ * @ulTickRateHz                      Desired frequency of kernel tick
+ * @uxAdditionalStackCheckMarginBytes Lower limit on number of bytes that
+ *                                    should be left in the stack post context
+ *                                    switch. Can be set greater than or equal
+ *                                    to 0
+ * @pcIdleTaskStackBuffer             Pointer to the lowest address of task
+ *                                    buffer to hold idle task
+ * @uxIdleTaskStackSizeBytes          Number of bytes in the stack buffer to be
+ *                                    kept for idle task. Should be greater
+ *                                    than 0
+ * @xIdleTaskUsingFPU                 Bool variable to indicate use of FPU by
+ *                                    idle task
+ * @uxIdleTaskPrivilegeLevel          Idle task privilege level
+ *                                    [RTOS_SYSTEM_MODE, RTOS_USER_MODE]
+ * @pxIdleTaskMPUParameters           Pointer to idle task MPU parameter
+ *                                    structure
+ * @pvIdleTaskTLSObject               Idle task timer local storage object
+ * @uxTimerTaskPriority               Priority of timer service.
+ *                                    Valid range is [0 - (configMAX_PRIORITIES - 1)]
+ * @uxTimerTaskStackSize              Number of bytes in stack buffer to be kept
+ *                                    for timer task. Should be greater than 0
+ * @pcTimerTaskStackBuffer            Pointer to the timer task stack buffer.
+ * @uxTimerCommandQueueLength         Timer command queue length. Should be
+ *                                    greater than 0.
+ * @uxTimerCommandQueueBufferSize     Timer command queue buffer size.
+ *                                    Size of the buffer should be at
+ *                                    least enough to accomodate the entire
+ *                                    command queue
+ * @pcTimerCommandQueueBuffer         Pointer to timer command queue buffer
+ * @pxTimerTaskMPUParameters          Pointer to timer task MPU parameters
+ */
+typedef struct {
+    rtosHz              ulCPUClockHz;
+    rtosHz              ulTickRateHz;
+    rtosUCount          uxAdditionalStackCheckMarginBytes;
+    void                *pcIdleTaskStackBuffer;
+    rtosUCount          uxIdleTaskStackSizeBytes;
+    rtosBool            xIdleTaskUsingFPU;
+    rtosPrivilegeLevel  uxIdleTaskPrivilegeLevel;
+    rtosMPURegionConfig *pxIdleTaskMPUParameters;
+    void                *pvIdleTaskTLSObject;
+    rtosPriority        uxTimerTaskPriority;
+    rtosUCount          uxTimerTaskStackSize;
+    void                *pcTimerTaskStackBuffer;
+    rtosUCount          uxTimerCommandQueueLength;
+    rtosUCount          uxTimerCommandQueueBufferSize;
+    void                *pcTimerCommandQueueBuffer;
+    rtosMPURegionConfig *pxTimerTaskMPUParameters;
+} rtosSchedParameters;
+
+/**
+ * @brief Structure supplied to rtosTimerCreate()
+ *
+ * @pcTimerName         Descriptive name of the timer
+ * @xTimerPeriodInTicks Timer period in ticks. Should be greater than 0
+ * @xIsPeriodic         Bool variable to indicate if timer is periodic
+ * @xTimerID            Timer ID
+ * @pxNewTimer          Pointer to timer control block
+ * @pxCallbackFunction  Timer callback function
+ * @pxTimerInstance     Timer instance to which the timer belongs
+ * @pvObject            Pointer to user defined data associated with this timer.
+ */
+typedef struct {
+    const char                *pcTimerName;
+    rtosTick                  xTimerPeriodInTicks;
+    rtosBool                  xIsPeriodic;
+    rtosTimerIDType           xTimerID;
+    void                      *pxNewTimer;
+    rtosTimerCallbackFunction pxCallbackFunction;
+    void                      *pxTimerInstance;
+    void                      *pvObject;
+} rtosTimerInitParametersType;
+
+/**
+ * @brief Wrapper structure for RTOS object-events
+ */
+#define rtosEventPollObjectEventsType eventPollObjectEventsType
+
+/**
+ * @brief Provide wrapper definitions for general architecture specific values
+ *
+ * @macro-title RTOS general architecture values
+ *
+ * @rtosMAX_DELAY             Defines maximum delay supported by rtos
+ * @rtosMAX_LIST_ITEM_VALUE   Defines maximum list items supported by rtos
+ * @rtosWORD_ALIGNMENT        Defines alignment value set for queue buffer
+ * @rtosWORD_ALIGNMENT_MASK   Defines alignment mask corresponding to alignment
+ *                            value set for queue buffer
+ * @rtosSTACK_ALIGNMENT       Defines alignment value set for stack buffer
+ * @rtosSTACK_ALIGNMENT_MASK  Defines alignment mask corresponding to alignment
+ *                            value set for stack buffer
+ * @rtosCONTEXT_SIZE_NO_FPU   Defines context size in bytes without FPU
+ * @rtosCONTEXT_SIZE_WITH_FPU Defines context size in bytes with FPU in use
+ * @rtosSTACK_IN_USE          Defines state value indicating stack is in use
+ * @rtosSTACK_NOT_IN_USE      Defines state value indicating stack is not in use
+ * @rtosTICK_COUNT_BITS       Defines number of bits used to represent tick
+ *                            count
+ * @rtosTICK_RATE_HZ          Defines frequency of the underlying RTOS scheduler
+ *                            tick
+ * @rtosTICK_RATE_MS          Defines number of ticks per millisecond.
+ */
+#define rtosMAX_DELAY                           portMAX_DELAY
+#define rtosMAX_LIST_ITEM_VALUE                 portMAX_LIST_ITEM_VALUE
+#define rtosWORD_ALIGNMENT                      portWORD_ALIGNMENT
+#define rtosWORD_ALIGNMENT_MASK                 portWORD_ALIGNMENT_MASK
+#define rtosSTACK_ALIGNMENT                     portSTACK_ALIGNMENT
+#define rtosSTACK_ALIGNMENT_MASK                portSTACK_ALIGNMENT_MASK
+#define rtosCONTEXT_SIZE_NO_FPU                 portCONTEXT_SIZE_BYTES_NO_FPU
+#define rtosCONTEXT_SIZE_WITH_FPU               portCONTEXT_SIZE_BYTES_WITH_FPU
+#define rtosSTACK_IN_USE                        portSTACK_IN_USE
+#define rtosSTACK_NOT_IN_USE                    portSTACK_NOT_IN_USE
+#define rtosTICK_COUNT_BITS                     portTICK_COUNT_NUM_BITS
+#define rtosTICK_RATE_HZ                        configTICK_RATE_HZ
+#define rtosTICK_RATE_MS                        configTICK_RATE_MS
+
+extern portUInt32Type xHookGetRTSCounter(void);
+
+/**
+ * @brief Provide macro definitions for ARM state values.
+ *
+ * @macro-title ARMV7 specific values
+ *
+ * @RTOS_SYSTEM_MODE Defines value indicating ARM system mode operation
+ * @RTOS_USER_MODE   Defines value indicating ARM user mode operation
+ */
+#define RTOS_SYSTEM_MODE                portPRIVILEGED_TASK
+#define RTOS_USER_MODE                  portUNPRIVILEGED_TASK
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv8/nvidia/riscv/nvriscv/ospl/rtos-port.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/nvidia/riscv/nvriscv/ospl/rtos-port.h
new file mode 100644
index 0000000..1e2d96b
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/nvidia/riscv/nvriscv/ospl/rtos-port.h
@@ -0,0 +1,322 @@
+/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSPL__RTOS_PORT_H
+#define OSPL__RTOS_PORT_H
+#define FSP__OSPL__RTOS_PORT_H                          1
+
+/* Compiler headers */
+#include <stdint.h>                        // for uint32_t, int32_t, int16_t
+#include <SafeRTOSConfig.h>                // for configTICK_RATE_HZ, config...
+#include <portmacro.h>                     // for portUnsignedBaseType, port...
+#include <projdefs.h>                      // for pdTASK_CODE
+//RRC #include <apiWrapper.h>                    // IWYU pragma: keep
+#include <list.h>                          // IWYU pragma: keep
+#include <eventgroups.h>                   // for eventBitsType, eventGroupType
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/riscv-mpu-safertos.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__CONFIG__SAFERTOSCONFIG_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARMV7_MPU_SAFERTOS_H)
+
+/*
+ * Port specific types and data structures needed by nvosRTOS.h
+ *
+ * This file should not be included directly from any other file.
+ */
+
+/**
+ * @brief Make sure that the sizes of types defined by SafeRTOS are what they
+ * are expected to be.
+ */
+CT_ASSERT(sizeof(uint64_t) == sizeof(portUInt64Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(int64_t) == sizeof(portInt64Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(uint32_t) == sizeof(portUInt32Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(int32_t) == sizeof(portInt32Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(uint32_t) == sizeof(portUnsignedBaseType), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(int32_t) == sizeof(portBaseType), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(uint16_t) == sizeof(portUInt16Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(int16_t) == sizeof(portInt16Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(uint8_t) == sizeof(portUInt8Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(int8_t) == sizeof(portInt8Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(char) == sizeof(portCharType), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(uint32_t) == sizeof(portStackType), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(uint32_t) == sizeof(portTickType), "ASSERT due to data type mismatch.")
+
+/**
+ * @brief Provide wrapper type definitions for RTOS values to avoid exposing the
+ * SafeRTOS types directly.
+ *
+ * @typedef-title OSA variable type space
+ */
+typedef portBaseType            rtosError;
+typedef void                    *rtosTaskHandle;
+typedef void                    *rtosEventGroupHandle;
+typedef eventGroupType          rtosEventGroup;
+typedef void                    *rtosQueueHandle;
+typedef void                    *rtosTimerHandle;
+typedef void                    *rtosTimerLocalStorageObject;
+typedef portUnsignedBaseType    rtosUCount;
+typedef portTickType            rtosTick;
+typedef portBaseType            rtosBool;
+typedef portBaseType            rtosTimerIDType;
+typedef void                    *rtosMutexHandle;
+typedef void                    *rtosSemaphoreHandle;
+typedef void                    *rtosEventPollHandle;
+typedef portUnsignedBaseType    rtosTaskNotifyBits;
+typedef portUnsignedBaseType    rtosEventPollValue;
+typedef portBaseType            rtosTaskNotifyAction;
+typedef portUnsignedBaseType    rtosTaskNotifyValue;
+typedef portUnsignedBaseType    rtosPriority;
+typedef portUnsignedBaseType    rtosInterruptState;
+typedef portUnsignedBaseType    rtosMutexState;
+typedef eventBitsType           rtosEventBits;
+typedef portUInt32Type          rtosHz;
+typedef portUnsignedBaseType    rtosPrivilegeLevel;
+
+/**
+ * @brief Sizes of objects that need to be statically allocated but whose
+ * contents are not visible to the application.
+ *
+ * @macro-title Macro definitions for size of kernel objects
+ *
+ * @rtosQUEUE_OVERHEAD_BYTES                    Defines size in bytes needed to
+ *                                              create a queue
+ * @rtosSEMAPHORE_OVERHEAD_BYTES                Defines size in bytes needed to
+ *                                              create a semaphore object
+ * @rtosMUTEX_OVERHEAD_BYTES                    Defines size in bytes needed to
+ *                                              create a mutex object
+ * @rtosEVENT_GROUP_OVERHEAD_BYTES              Defines size in bytes needed to
+ *                                              create an event group object
+ * @rtosTCB_OVERHEAD_BYTES                      Defines size in bytes needed for
+ *                                              task control block
+ * @rtosTIMER_CONTROL_BLOCK_OVERHEAD_BYTES      Defines size in bytes needed for
+ *                                              timer control block
+ * @rtosTIMER_INSTANCE_PARAMETER_OVERHEAD_BYTES Defines size in bytes needed for
+ *                                              timer instance parameters
+ * @rtosEVENT_POLL_OVERHEAD_BYTES               Defines size in bytes needed to
+ *                                              create an event poll object
+ */
+#define rtosQUEUE_OVERHEAD_BYTES                   portQUEUE_OVERHEAD_BYTES
+#define rtosSEMAPHORE_OVERHEAD_BYTES               portQUEUE_OVERHEAD_BYTES
+#define rtosMUTEX_OVERHEAD_BYTES                   portQUEUE_OVERHEAD_BYTES
+#define rtosEVENT_GROUP_OVERHEAD_BYTES             sizeof(eventGroupType)
+#define rtosTCB_OVERHEAD_BYTES                     sizeof(xTCB)
+#define rtosTIMER_CONTROL_BLOCK_OVERHEAD_BYTES     sizeof(timerControlBlockType)
+#define rtosTIMER_INSTANCE_PARAMETER_OVERHEAD_BYTES \
+        sizeof(struct timerInstanceParameters)
+#define rtosEVENT_POLL_OVERHEAD_BYTES(uxMaximumRegisteredObjectEvents) \
+        eventpollGET_REQUIRED_CREATE_BUFFER_SIZE(uxMaximumRegisteredObjectEvents)
+
+/**
+ * @brief Provide wrapper definition for pointer to RTOS task function.
+ */
+typedef pdTASK_CODE             rtosTaskFunction;
+
+/**
+ * @brief Provide a wrapper data type to encapsulate MPU related information
+ */
+typedef mpuParameters_t rtosMPURegionConfig;
+
+/**
+ * @brief Provide wrapper definition for pointer to RTOS timer callback function
+ * which gets invoked when a timer expires.
+ */
+typedef void (*rtosTimerCallbackFunction)(void * pvParameters);
+
+/**
+ * @brief Structure supplied to rtosTaskCreate()
+ *
+ * @pvTaskCode        Pointer to task entry function
+ * @pcTaskName        Task descriptive name
+ * @pxTCB             Pointer to task control block
+ * @pcStackBuffer     Pointer to task stack buffer
+ * @uxStackDepthBytes Size of task stack buffer in bytes
+ * @pvParameters      Pointer to task parameters
+ * @uxPriority        Priority of task
+ * @pvObject          Pointer to C++ object that tracks this structure.
+ * @xUsingFPU         Bool to indicate use of FPU
+ * @uxPrivilegeLevel  Task Privilege level
+ * @pxMPUParameters   Pointer to task MPU parameters
+ */
+typedef struct {
+    rtosTaskFunction    pvTaskCode;
+    const char          *pcTaskName;
+    void                *pxTCB;
+    void                *pcStackBuffer;
+    rtosUCount          uxStackDepthBytes;
+    void                *pvParameters;
+    rtosPriority        uxPriority;
+    void                *pvObject;
+    rtosBool            xUsingFPU;
+    rtosPrivilegeLevel  uxPrivilegeLevel;
+    rtosMPURegionConfig *pxMPUParameters;
+} rtosTaskParameters;
+
+/**
+ * @brief Structure supplied to rtosTaskInitializeScheduler()
+ *
+ * @ulCPUClockHz                      Speed of the system clock
+ * @ulTickRateHz                      Desired frequency of kernel tick
+ * @uxAdditionalStackCheckMarginBytes Lower limit on number of bytes that
+ *                                    should be left in the stack post context
+ *                                    switch
+ * @pcIdleTaskStackBuffer             Pointer to the lowest address of task
+ *                                    buffer to hold idle task
+ * @uxIdleTaskStackSizeBytes          Number of bytes in the stack buffer to be
+ *                                    kept for idle task
+ * @xIdleTaskUsingFPU                 Bool variable to indicate use of FPU by
+ *                                    idle task
+ * @uxIdleTaskPrivilegeLevel          Idle task privilege level
+ * @pxIdleTaskMPUParameters           Pointer to idle task MPU parameter
+ *                                    structure
+ * @pvIdleTaskTLSObject               Idle task timer local storage object
+ * @uxTimerTaskPriority               Priority of timer service
+ * @uxTimerTaskStackSize              Number of bytes in stack buffer to be kept
+ *                                    for timer task
+ * @pcTimerTaskStackBuffer            Pointer to the timer task stack buffer
+ * @uxTimerCommandQueueLength         Timer command queue length
+ * @uxTimerCommandQueueBufferSize     Timer command queue buffer size for handling
+ *                                    timer tasks
+ * @pcTimerCommandQueueBuffer         Pointer to timer command queue buffer
+ * @pxTimerTaskMPUParameters          Pointer to timer task MPU parameters
+ */
+typedef struct {
+    rtosHz              ulCPUClockHz;
+    rtosHz              ulTickRateHz;
+    rtosUCount          uxAdditionalStackCheckMarginBytes;
+    void                *pcIdleTaskStackBuffer;
+    rtosUCount          uxIdleTaskStackSizeBytes;
+    rtosBool            xIdleTaskUsingFPU;
+    rtosPrivilegeLevel  uxIdleTaskPrivilegeLevel;
+    rtosMPURegionConfig *pxIdleTaskMPUParameters;
+    void                *pvIdleTaskTLSObject;
+    rtosPriority        uxTimerTaskPriority;
+    rtosUCount          uxTimerTaskStackSize;
+    void                *pcTimerTaskStackBuffer;
+    rtosUCount          uxTimerCommandQueueLength;
+    rtosUCount          uxTimerCommandQueueBufferSize;
+    void                *pcTimerCommandQueueBuffer;
+    rtosMPURegionConfig *pxTimerTaskMPUParameters;
+} rtosSchedParameters;
+
+/**
+ * @brief Structure supplied to rtosTimerCreate()
+ *
+ * @pcTimerName         Descriptive name of the timer
+ * @xTimerPeriodInTicks Timer period in ticks
+ * @xIsPeriodic         Bool variable to indicate if timer is periodic
+ * @xTimerID            Timer ID
+ * @pxNewTimer          Pointer to timer control block
+ * @pxCallbackFunction  Timer callback function
+ * @pxTimerInstance     Timer instance to which the timer belongs
+ * @pvObject            Pointer to C++ object that tracks this structure.
+ */
+typedef struct {
+    const char                *pcTimerName;
+    rtosTick                  xTimerPeriodInTicks;
+    rtosBool                  xIsPeriodic;
+    rtosTimerIDType           xTimerID;
+    void                      *pxNewTimer;
+    rtosTimerCallbackFunction pxCallbackFunction;
+    void                      *pxTimerInstance;
+    void                      *pvObject;
+} rtosTimerInitParametersType;
+
+/**
+ * @brief Wrapper structure for RTOS object-events
+ */
+#define rtosEventPollObjectEventsType eventPollObjectEventsType
+
+/**
+ * @brief Provide wrapper definitions for general architecture specific values
+ *
+ * @macro-title RTOS general architecture values
+ *
+ * @rtosMAX_DELAY             Defines maximum delay supported by rtos
+ * @rtosMAX_LIST_ITEM_VALUE   Defines maximum list items supported by rtos
+ * @rtosWORD_ALIGNMENT        Defines alignment value set for queue buffer
+ * @rtosWORD_ALIGNMENT_MASK   Defines alignment mask corresponding to alignment
+ *                            value set for queue buffer
+ * @rtosSTACK_ALIGNMENT       Defines alignment value set for stack buffer
+ * @rtosSTACK_ALIGNMENT_MASK  Defines alignment mask corresponding to alignment
+ *                            value set for stack buffer
+ * @rtosCONTEXT_SIZE_NO_FPU   Defines context size in bytes without FPU
+ * @rtosCONTEXT_SIZE_WITH_FPU Defines context size in bytes with FPU in use
+ * @rtosSTACK_IN_USE          Defines state value indicating stack is in use
+ * @rtosSTACK_NOT_IN_USE      Defines state value indicating stack is not in use
+ * @rtosTICK_COUNT_BITS       Defines number of bits used to represent tick
+ *                            count
+ * @rtosTICK_RATE_HZ          Defines frequency of the underlying RTOS scheduler
+ *                            tick
+ * @rtosTICK_RATE_MS          Defines number of ticks per millisecond.
+ */
+#define rtosMAX_DELAY                           portMAX_DELAY
+#define rtosMAX_LIST_ITEM_VALUE                 portMAX_LIST_ITEM_VALUE
+#define rtosWORD_ALIGNMENT                      portWORD_ALIGNMENT
+#define rtosWORD_ALIGNMENT_MASK                 portWORD_ALIGNMENT_MASK
+#define rtosSTACK_ALIGNMENT                     portSTACK_ALIGNMENT
+#define rtosSTACK_ALIGNMENT_MASK                portSTACK_ALIGNMENT_MASK
+#define rtosCONTEXT_SIZE_NO_FPU                 portCONTEXT_SIZE_BYTES_NO_FPU
+#define rtosCONTEXT_SIZE_WITH_FPU               portCONTEXT_SIZE_BYTES_WITH_FPU
+#define rtosSTACK_IN_USE                        portSTACK_IN_USE
+#define rtosSTACK_NOT_IN_USE                    portSTACK_NOT_IN_USE
+#define rtosTICK_COUNT_BITS                     portTICK_COUNT_NUM_BITS
+#define rtosTICK_RATE_HZ                        configTICK_RATE_HZ
+#define rtosTICK_RATE_MS                        configTICK_RATE_MS
+
+extern portUInt32Type xHookGetRTSCounter(void);
+
+/**
+ * @brief Provide macro definitions for ARM state values.
+ *
+ * @macro-title ARMV7 specific values
+ *
+ * @RTOS_SYSTEM_MODE Defines value indicating ARM system mode operation
+ * @RTOS_USER_MODE   Defines value indicating ARM user mode operation
+ */
+#define RTOS_SYSTEM_MODE                portPRIVILEGED_TASK
+#define RTOS_USER_MODE                  portUNPRIVILEGED_TASK
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-errors.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-errors.h
new file mode 100644
index 0000000..97bf706
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-errors.h
@@ -0,0 +1,342 @@
+/* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_ERRORS_H
+#define OSA__OSA_ERRORS_H
+#define FSP__OSA__OSA_ERRORS_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>  // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>  // for FSP__BASE__MODULE_ID_H, MODULE_ERROR_MODULE
+#include <misc/macros.h>     // for START_RFD_BLOCK, END_RFD_BLOCK, ...
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>  // for errSUPPLIED_BUFFER_TOO_SMALL, errBAD_OR_...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+
+/*
+ * Ensure that the native SafeRTOS error code map can map into the global
+ * error code space with no other manipulation.
+ */
+CT_ASSERT(MODULE_ERROR_MODULE(errSUPPLIED_BUFFER_TOO_SMALL) == MODULE_ID_RTOS, "SafeRTOS error codes collide with FSP error codes.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @brief Mapping of SafeRTOS return codes to generic rtos error codes.
+ *
+ * @macro-title Public error codes from OSA layer
+ *
+ * @E_RTOS_SUPPLIED_BUFFER_TOO_SMALL              Error value returned if
+ *                                                supplied buffer is too small
+ *                                                to create a kernel object
+ * @E_RTOS_INVALID_PRIORITY                       Error value returned for
+ *                                                invalid task priority
+ * @E_RTOS_QUEUE_FULL                             Error value returned if queue
+ *                                                is full and cannot accept a
+ *                                                new request
+ * @E_RTOS_NULL_PARAMETER_SUPPLIED                Error value returned if null is
+ *                                                supplied as an input parameter
+ * @E_RTOS_INVALID_QUEUE_LENGTH                   Error value returned if
+ *                                                requested queue length
+ *                                                is invalid
+ * @E_RTOS_INVALID_TASK_CODE_POINTER              Error value returned for
+ *                                                invalid input task code pointer
+ * @E_RTOS_SCHEDULER_IS_SUSPENDED                 Error value returned if request
+ *                                                could not be processed because
+ *                                                the scheduler was suspended
+ * @E_RTOS_INVALID_TASK_HANDLE                    Error value returned for
+ *                                                invalid input task handle
+ * @E_RTOS_DID_NOT_YIELD                          Error value returned if task
+ *                                                did not yield for a yield
+ *                                                request
+ * @E_RTOS_TASK_ALREADY_SUSPENDED                 Error value returned if request
+ *                                                to suspend a task could not be
+ *                                                processed because the task
+ *                                                was already suspended.
+ * @E_RTOS_TASK_WAS_NOT_SUSPENDED                 Error value returned if request
+ *                                                to resume a task
+ *                                                could not be processed because
+ *                                                the task was not suspended.
+ * @E_RTOS_SCHEDULER_ALREADY_RUNNING              Error value returned if request
+ *                                                to start a scheduler could not
+ *                                                be processed because
+ *                                                scheduler was already running
+ * @E_RTOS_INVALID_QUEUE_HANDLE                   Error value returned for
+ *                                                invalid input queue handle
+ * @E_RTOS_INVALID_SEMAPHORE_HANDLE               Error value returned for
+ *                                                invalid input semaphore handle
+ * @E_RTOS_INVALID_MUTEX_HANDLE                   Error value returned for
+ *                                                invalid input mutex handle
+ * @E_RTOS_ERRONEOUS_UNBLOCK                      Error value returned for
+ *                                                erroneous request to
+ *                                                unblock a task
+ * @E_RTOS_QUEUE_EMPTY                           Error value returned if request
+ *                                                to pick a task from the queue
+ *                                                could not be processed because
+ *                                                queue was empty
+ * @E_RTOS_SEMAPHORE_ALREADY_TAKEN                Error value returned if request
+ *                                                to acquire a semaphore could
+ *                                                not be processed because
+ *                                                semaphore was already taken
+ * @E_RTOS_MUTEX_ALREADY_TAKEN                    Error value returned if
+ *                                                request to acquire a mutex
+ *                                                could not be processed because
+ *                                                mutex was already taken
+ * @E_RTOS_INVALID_TICK_VALUE                     Error value returned for
+ *                                                invalid input tick value
+ * @E_RTOS_INVALID_TASK_SELECTED                  Error value returned for
+ *                                                invalid task selection
+ * @E_RTOS_TASK_STACK_OVERFLOW                    Error value returned when task
+ *                                                stack overflows
+ * @E_RTOS_SCHEDULER_WAS_NOT_SUSPENDED            Error value returned if request
+ *                                                to resume scheduler could not
+ *                                                be processed because
+ *                                                scheduler was already running.
+ * @E_RTOS_INVALID_BUFFER_SIZE                    Error value returned for
+ *                                                invalid input buffer size
+ * @E_RTOS_BAD_OR_NO_TICK_RATE_CONFIGURATION      Error value returned for
+ *                                                invalid tick rate
+ * @E_RTOS_ERROR_IN_VECTOR_TABLE                  Error value returned for error
+ *                                                in vector table
+ * @E_RTOS_INVALID_MPU_REGION_CONFIGURATION       Error value returned for
+ *                                                invalid MPU region
+ *                                                configuration
+ * @E_RTOS_INVALID_MMU_REGION_CONFIGURATION       Error value returned for
+ *                                                invalid MMU region
+ *                                                configuration
+ * @E_RTOS_TASK_STACK_ALREADY_IN_USE              Error value returned if task
+ *                                                stack supplied to initialize a
+ *                                                scheduler is already in use
+ * @E_RTOS_NO_MPU_IN_DEVICE                       Error value returned if MPU
+ *                                                does not exist in the device
+ * @E_RTOS_EXECUTING_IN_UNPRIVILEGED_MODE         Error value returned if a task
+ *                                                is expected to run in
+ *                                                privileged mode but currently
+ *                                                running in unprivileged mode
+ * @E_RTOS_RTS_CALCULATION_ERROR                  Error value returned on
+ *                                                detection of rts calculation
+ *                                                error
+ * @E_RTOS_INVALID_PERCENTAGE_HANDLE              Error value returned for
+ *                                                invalid percentage handle
+ * @E_RTOS_INVALID_INITIAL_SEMAPHORE_COUNT        Error value returned for
+ *                                                invalid initial semaphore count
+ * @E_RTOS_ROM_INTEGRITY_CHECK_FAILED             Error value returned for ROM
+ *                                                integrity check failures
+ * @E_RTOS_IN_PROGRESS                            Error value returned if request
+ *                                                is already in progress
+ * @E_RTOS_INVALID_PARAMETERS                     Error value returned if
+ *                                                invalid value is set for
+ *                                                input parameter
+ * @E_RTOS_SPURIOUS_INTERRUPT                     Error value returned for
+ *                                                spurious interrupts
+ * @E_RTOS_SPURIOUS_FAST_INTERRUPT                Error value returned for
+                                                  spurious fast interrupts
+ * @E_RTOS_RAM_INTEGRITY_CHECK_FAILED             Error value returned for RAM
+ *                                                integrity check failure
+ * @E_RTOS_INVALID_TIMER_HANDLE                   Error value returned for
+ *                                                invalid timer handle
+ * @E_RTOS_INVALID_TIMER_TASK_INSTANCE            Error value returned for
+ *                                                invalid input timer task
+ *                                                instance
+ * @E_RTOS_TIMER_ALREADY_IN_USE                   Error value returned if request
+ *                                                to create a new timer could not
+ *                                                be processed because the
+ *                                                supplied timer handle was
+ *                                                already in use.
+ * @E_RTOS_NOTIFICATION_NOT_RECEIVED              Error value returned if
+ *                                                notification is
+ *                                                not received until timeout
+ * @E_RTOS_NOTIFICATION_ALREADY_PENDING           Error value returned if a new
+ *                                                request to wait for
+ *                                                notification arises while the
+ *                                                task is still waiting for
+ *                                                notification
+ * @E_RTOS_TASK_WAS_ALSO_ON_EVENT_LIST            Error value returned if the
+ *                                                task is already part of the
+ *                                                event list
+ * @E_RTOS_QUEUE_ALREADY_IN_USE                   Error value returned if request
+ *                                                to create a new queue could not
+ *                                                be processed because input
+ *                                                queue handle was already in use
+ * @E_RTOS_EVENT_GROUP_ALREADY_IN_USE             Error value returned if request
+ *                                                to create a new event group
+ *                                                could not be processed because
+ *                                                input event group handle was
+ *                                                already in use
+ * @E_RTOS_INVALID_EVENT_GROUP_HANDLE             Error value returned for
+ *                                                invalid input event group
+ *                                                handle
+ * @E_RTOS_EVENT_GROUP_BITS_NOT_SET               Error value returned if event
+ *                                                group bits could not be set
+ * @E_RTOS_EVENT_GROUP_DELETED                    Error value returned if event
+ *                                                group request could not be
+ *                                                processed as referred object
+ *                                                is deleted
+ * @E_RTOS_MUTEX_NOT_OWNED_BY_CALLER             Error value returned if mutex
+ *                                                request could not be processed
+ *                                                as mutex is not owned by
+ *                                                the caller
+ * @E_RTOS_MUTEX_CORRUPTED                        Error value returned if mutex
+ *                                                got corrupted
+ * @E_RTOS_NEXT_UNBLOCK_TIME_EXPIRED              Error value returned if next
+ *                                                unblock time for the referred
+ *                                                task expired
+ * @E_RTOS_WOKEN_UP_AFTER_NEXT_UNBLOCK_TIME       Error value returned if task
+ *                                                got unblocked after next
+ *                                                unblock time
+ * @E_RTOS_TICKLESS_MODE_NOT_SUPPORTED            Error value returned if
+ *                                                tickless mode is not supported
+ * @E_RTOS_SCHEDULER_IS_NOT_RUNNING               Error value returned if the request
+ *                                                could not be processed because
+ *                                                scheduler is not running
+ * @E_RTOS_EVENT_POLL_OBJECT_ALREADY_IN_USE       Error value returned if
+ *                                                request to create a new event
+ *                                                poll object could not be
+ *                                                processed as event poll object
+ *                                                handle was already in use
+ * @E_RTOS_EVENT_POLL_OBJECT_EVENTS_LIMIT_REACHED Error value returned if no
+ *                                                more target objects can be
+ *                                                registered with the referred
+ *                                                event poll object
+ * @E_RTOS_INVALID_EVENT_POLL_OPERATION           Error value returned for
+ *                                                invalid event poll operation
+ * @E_RTOS_INVALID_EVENT_POLL_HANDLE              Error value returned for
+ *                                                invalid event poll handle
+ * @E_RTOS_INVALID_EVENT_POLL_EVENTS              Error value returned for
+ *                                                invalid event poll events for
+ *                                                the target object
+ * @E_RTOS_NO_TASKS_CREATED                       Error value returned if
+ *                                                request to start a scheduler
+ *                                                could not be processed as no
+ *                                                tasks are created
+ * @E_RTOS_INVALID_ALIGNMENT                      Error returned for invalid byte
+ *                                                alignment
+ * @E_RTOS_EVENT_POLL_NO_EVENTS_OCCURRED          Error returned if no event has
+ *                                                occurred while waiting for
+ *                                                events registered with event
+ *                                                poll object
+ * @E_RTOS_INVALID_DATA_RANGE                     Error value returned for
+ *                                                invalid data range
+ * @E_RTOS_NO_TICK_SETUP_HOOK_DEFINED             Error value returned if no hook
+ *                                                has been defined to setup ticks
+ */
+#define E_RTOS_SUPPLIED_BUFFER_TOO_SMALL              errSUPPLIED_BUFFER_TOO_SMALL
+#define E_RTOS_INVALID_PRIORITY                       errINVALID_PRIORITY
+#define E_RTOS_QUEUE_FULL                             errQUEUE_FULL
+#define E_RTOS_INVALID_ALIGNMENT                      errINVALID_ALIGNMENT
+#define E_RTOS_NULL_PARAMETER_SUPPLIED                errNULL_PARAMETER_SUPPLIED
+#define E_RTOS_INVALID_QUEUE_LENGTH                   errINVALID_QUEUE_LENGTH
+#define E_RTOS_INVALID_TASK_CODE_POINTER              errINVALID_TASK_CODE_POINTER
+#define E_RTOS_SCHEDULER_IS_SUSPENDED                 errSCHEDULER_IS_SUSPENDED
+#define E_RTOS_INVALID_TASK_HANDLE                    errINVALID_TASK_HANDLE
+#define E_RTOS_DID_NOT_YIELD                          errDID_NOT_YIELD
+#define E_RTOS_TASK_ALREADY_SUSPENDED                 errTASK_ALREADY_SUSPENDED
+#define E_RTOS_TASK_WAS_NOT_SUSPENDED                 errTASK_WAS_NOT_SUSPENDED
+#define E_RTOS_NO_TASKS_CREATED                       errNO_TASKS_CREATED
+#define E_RTOS_SCHEDULER_ALREADY_RUNNING              errSCHEDULER_ALREADY_RUNNING
+#define E_RTOS_INVALID_QUEUE_HANDLE                   errINVALID_QUEUE_HANDLE
+#define E_RTOS_INVALID_SEMAPHORE_HANDLE               errINVALID_SEMAPHORE_HANDLE
+#define E_RTOS_INVALID_MUTEX_HANDLE                   errINVALID_MUTEX_HANDLE
+#define E_RTOS_ERRONEOUS_UNBLOCK                      errERRONEOUS_UNBLOCK
+#define E_RTOS_QUEUE_EMPTY                            errQUEUE_EMPTY
+#define E_RTOS_SEMAPHORE_ALREADY_TAKEN                errSEMAPHORE_ALREADY_TAKEN
+#define E_RTOS_SEMAPHORE_ALREADY_GIVEN                errSEMAPHORE_ALREADY_GIVEN
+#define E_RTOS_MUTEX_ALREADY_TAKEN                    errMUTEX_ALREADY_TAKEN
+#define E_RTOS_INVALID_TICK_VALUE                     errINVALID_TICK_VALUE
+#define E_RTOS_INVALID_TASK_SELECTED                  errINVALID_TASK_SELECTED
+#define E_RTOS_TASK_STACK_OVERFLOW                    errTASK_STACK_OVERFLOW
+#define E_RTOS_SCHEDULER_WAS_NOT_SUSPENDED            errSCHEDULER_WAS_NOT_SUSPENDED
+#define E_RTOS_INVALID_BUFFER_SIZE                    errINVALID_BUFFER_SIZE
+#define E_RTOS_BAD_OR_NO_TICK_RATE_CONFIGURATION      errBAD_OR_NO_TICK_RATE_CONFIGURATION
+#define E_RTOS_ERROR_IN_VECTOR_TABLE                  errERROR_IN_VECTOR_TABLE
+#define E_RTOS_INVALID_MPU_REGION_CONFIGURATION       errINVALID_MPU_REGION_CONFIGURATION
+#define E_RTOS_INVALID_MMU_REGION_CONFIGURATION       errINVALID_MMU_REGION_CONFIGURATION
+#define E_RTOS_TASK_STACK_ALREADY_IN_USE              errTASK_STACK_ALREADY_IN_USE
+#define E_RTOS_NO_MPU_IN_DEVICE                       errNO_MPU_IN_DEVICE
+#define E_RTOS_EXECUTING_IN_UNPRIVILEGED_MODE         errEXECUTING_IN_UNPRIVILEGED_MODE
+#define E_RTOS_RTS_CALCULATION_ERROR                  errRTS_CALCULATION_ERROR
+#define E_RTOS_INVALID_PERCENTAGE_HANDLE              errINVALID_PERCENTAGE_HANDLE
+#define E_RTOS_INVALID_INITIAL_SEMAPHORE_COUNT        errINVALID_INITIAL_SEMAPHORE_COUNT
+#define E_RTOS_ROM_INTEGRITY_CHECK_FAILED             errROM_INTEGRITY_CHECK_FAILED
+#define E_RTOS_IN_PROGRESS                            errIN_PROGRESS
+#define E_RTOS_INVALID_PARAMETERS                     errINVALID_PARAMETERS
+#define E_RTOS_SPURIOUS_INTERRUPT                     errSPURIOUS_INTERRUPT
+#define E_RTOS_SPURIOUS_FAST_INTERRUPT                errSPURIOUS_FAST_INTERRUPT
+#define E_RTOS_RAM_INTEGRITY_CHECK_FAILED             errRAM_INTEGRITY_CHECK_FAILED
+#define E_RTOS_INVALID_TIMER_HANDLE                   errINVALID_TIMER_HANDLE
+#define E_RTOS_INVALID_TIMER_TASK_INSTANCE            errINVALID_TIMER_TASK_INSTANCE
+#define E_RTOS_TIMER_ALREADY_IN_USE                   errTIMER_ALREADY_IN_USE
+#define E_RTOS_NOTIFICATION_NOT_RECEIVED              errNOTIFICATION_NOT_RECEIVED
+#define E_RTOS_NOTIFICATION_ALREADY_PENDING           errNOTIFICATION_ALREADY_PENDING
+#define E_RTOS_TASK_WAS_ALSO_ON_EVENT_LIST            errTASK_WAS_ALSO_ON_EVENT_LIST
+#define E_RTOS_QUEUE_ALREADY_IN_USE                   errQUEUE_ALREADY_IN_USE
+#define E_RTOS_EVENT_GROUP_ALREADY_IN_USE             errEVENT_GROUP_ALREADY_IN_USE
+#define E_RTOS_INVALID_EVENT_GROUP_HANDLE             errINVALID_EVENT_GROUP_HANDLE
+#define E_RTOS_EVENT_GROUP_BITS_NOT_SET               errEVENT_GROUP_BITS_NOT_SET
+#define E_RTOS_EVENT_GROUP_DELETED                    errEVENT_GROUP_DELETED
+#define E_RTOS_MUTEX_NOT_OWNED_BY_CALLER              errMUTEX_NOT_OWNED_BY_CALLER
+#define E_RTOS_MUTEX_CORRUPTED                        errMUTEX_CORRUPTED
+#define E_RTOS_NEXT_UNBLOCK_TIME_EXPIRED              errNEXT_UNBLOCK_TIME_EXPIRED
+#define E_RTOS_WOKEN_UP_AFTER_NEXT_UNBLOCK_TIME       errWOKEN_UP_AFTER_NEXT_UNBLOCK_TIME
+#define E_RTOS_TICKLESS_MODE_NOT_SUPPORTED            errTICKLESS_MODE_NOT_SUPPORTED
+#define E_RTOS_EVENT_POLL_OBJECT_ALREADY_IN_USE       errEVENT_POLL_OBJECT_ALREADY_IN_USE
+#define E_RTOS_SCHEDULER_IS_NOT_RUNNING               errSCHEDULER_IS_NOT_RUNNING
+#define E_RTOS_EVENT_POLL_OBJECT_EVENTS_LIMIT_REACHED errEVENT_POLL_OBJECT_EVENTS_LIMIT_REACHED
+#define E_RTOS_INVALID_EVENT_POLL_OPERATION           err INVALID_EVENT_POLL_OPERATION
+#define E_RTOS_INVALID_EVENT_POLL_HANDLE              errINVALID_EVENT_POLL_HANDLE
+#define E_RTOS_INVALID_EVENT_POLL_EVENTS              errINVALID_EVENT_POLL_EVENTS
+#define E_RTOS_EVENT_POLL_NO_EVENTS_OCCURRED          errEVENT_POLL_NO_EVENTS_OCCURRED
+#define E_RTOS_INVALID_DATA_RANGE                     errINVALID_DATA_RANGE
+#define E_RTOS_NO_TICK_SETUP_HOOK_DEFINED             errNO_TICK_SETUP_HOOK_DEFINED
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-event-group.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-event-group.h
new file mode 100644
index 0000000..f6158f7
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-event-group.h
@@ -0,0 +1,390 @@
+/* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_EVENT_GROUP_H
+#define OSA__OSA_EVENT_GROUP_H
+#define FSP__OSA__OSA_EVENT_GROUP_H                     1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, ...
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosEventGroupHandle, rtosEventBits, rto...
+#include <eventgroups.h>                // IWYU pragma: export
+                                        // IWYU pragma: no_include "eventgroups.h"
+                                        // for xEventGroupClearBitsFromISR, xEvent...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @brief Create an event group
+ *
+ * This function is a wrapper for xEventGroupCreate() in SafeRTOS to create an
+ * event group object.
+ * It updates pointer to the event group handle to point to the newly
+ * created event group
+ *
+ * @pre
+ * - A variable of type rtosEventGroup, r/w accessible to RTOS kernel at all
+ * times has been declared to handle the event group object
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in]  pxEventGroup       Pointer to the pre-declared event group variable
+ *                                of type rtosEventGroup
+ * @param[out] pxEventGroupHandle Pointer to the event group handle
+ *
+ * @retval rtosPASS on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null Input parameter
+ * @retval E_RTOS_EVENT_GROUP_ALREADY_IN_USE Event handle supplied is valid and
+ *                                           must be deleted before creating a
+ *                                           new group
+ * @retval E_RTOS_INVALID_DATA_RANGE         Error writing data to the output parameter
+ */
+static inline rtosError
+rtosEventGroupCreate(rtosEventGroup *pxEventGroup,
+                     rtosEventGroupHandle *pxEventGroupHandle)
+{
+    return xEventGroupCreate(pxEventGroup,
+                             pxEventGroupHandle);
+}
+
+/**
+ * @brief Delete an event group
+ *
+ * This function is a wrapper for xEventGroupDelete() in SafeRTOS to delete an
+ * event group object.
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from a non-interrupt context
+ *
+ * - Scheduler has been started.
+ *
+ * @param[in] xHandle Event group handle
+ *
+ * @retval rtosPASS                          on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null input parameter
+ * @retval E_RTOS_INVALID_EVENT_GROUP_HANDLE Invalid event group handle
+ */
+static inline rtosError
+rtosEventGroupDelete(rtosEventGroupHandle xHandle)
+{
+    return xEventGroupDelete(xHandle);
+}
+
+/**
+ * @brief Get event group bits.
+ *
+ * This function is a wrapper for xEventGroupGetBits() in SafeRTOS to
+ * read the status of event group bits.
+ * It updates the pointer to event group bits with latest bit-mask of
+ * set fields in the event group.
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xHandle        Event group handle
+ * @param[in] pxEventBitsSet Pointer to event group bits
+ *
+ * @retval rtosPASS                          on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null input parameter
+ * @retval E_RTOS_INVALID_EVENT_GROUP_HANDLE Invalid event group handle
+ * @retval E_RTOS_INVALID_DATA_RANGE         Error writing data to the output parameter
+ */
+static inline rtosError
+rtosEventGroupGetBits(rtosEventGroupHandle xHandle,
+                      rtosEventBits *pxEventBitsSet)
+{
+    return xEventGroupGetBits(xHandle,
+                              pxEventBitsSet);
+}
+
+/**
+ * @brief Get event group bits from ISR.
+ *
+ * This function is a wrapper for xEventGroupGetBitsFromISR() in SafeRTOS to
+ * read the status of event group bits from an ISR
+ * It updates the pointer to event group bits with latest bit-mask of set fields
+ * within the event group in an ISR context.
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xHandle        Event group handle
+ * @param[in] pxEventBitsSet Pointer to event group bits
+ *
+ * @retval rtosPASS                          on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null input parameter
+ * @retval E_RTOS_INVALID_EVENT_GROUP_HANDLE Invalid event group handle
+ * @retval E_RTOS_INVALID_DATA_RANGE         Error writing data to the output parameter
+ */
+static inline rtosError
+rtosEventGroupGetBitsFromISR(rtosEventGroupHandle xHandle,
+                             rtosEventBits *pxEventBitsSet)
+{
+    return xEventGroupGetBitsFromISR(xHandle,
+                                     pxEventBitsSet);
+}
+
+/**
+ * Set event group bits
+ *
+ * This function is a wrapper for xEventGroupSetBits() in SafeRTOS to set one
+ * or more bits to '1' in an event group
+ * Sets required fields within the event group based on bit-mask sent as an
+ * argument.
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xHandle    Event group handle
+ * @param[in] xBitsToSet Bit mask to set required fields in the event group
+ *                       Size of rtosEventBits type is platform dependent.
+ *                       For ARM Cortex-R5, it is 32-bits. Since most
+ *                       significant byte is used for control purposes, valid
+ *                       bit-mask range is 0 - 23 bits.
+ *
+ * @retval rtosPASS                          on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null input parameter
+ * @retval E_RTOS_INVALID_EVENT_GROUP_HANDLE Invalid event group handle
+ * @retval E_RTOS_INVALID_PARAMETERS         Invalid parameters
+ */
+static inline rtosError
+rtosEventGroupSetBits(rtosEventGroupHandle xHandle,
+                      const rtosEventBits xBitsToSet)
+{
+    return xEventGroupSetBits(xHandle,
+                              xBitsToSet);
+}
+
+/**
+ * Set event group bits from ISR
+ *
+ * This function is a wrapper for xEventGroupSetBitsFromISR() in SafeRTOS to
+ * set one or more event group bits to '1' in an interrupt-context.
+ * Sets required fields within the event group based on bit-mask sent as an
+ * argument.
+ * It sets the value at pbHigherPriorityTaskWoken if calling this function
+ * unblocks a task of priority higher than currently running task indicating
+ * that a context switch is needed before exiting the ISR
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xHandle                    Event group handle
+ * @param[in] xBitsToSet                 Bit-mask to set required fields in the
+ *                                       event group. Valid bit-mask range for
+ *                                       ARM Cortex-R5 processor is 0 - 23 bits.
+ * @param[out] pbHigherPriorityTaskWoken Pointer to rtosbool variable
+ *
+ * @retval rtosPASS                          on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null input parameter
+ * @retval E_RTOS_INVALID_EVENT_GROUP_HANDLE Invalid event group handle
+ * @retval E_RTOS_INVALID_PARAMETERS         Invalid parameters
+ * @retval E_RTOS_QUEUE_FULL                 Queue associated with event group
+ *                                           object is full and cannot accept
+ *                                           incoming event group request
+ * @retval E_RTOS_INVALID_DATA_RANGE         Error while copying data to the output
+ *                                           parameter
+ */
+static inline rtosError
+rtosEventGroupSetBitsFromISR(rtosEventGroupHandle xHandle,
+                             const rtosEventBits xBitsToSet,
+                             rtosBool *pbHigherPriorityTaskWoken)
+{
+    return xEventGroupSetBitsFromISR(xHandle,
+                                     xBitsToSet,
+                                     pbHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Clear required event group bits
+ *
+ * This function is a wrapper for xEventGroupClearBits() in SafeRTOS to clear
+ * one or more bits in an event group
+ * Clears required fields within the event group based on bit-mask sent as an
+ * argument.
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xHandle      Event group handle
+ * @param[in] xBitsToClear Bit-mask to clear required fields.
+ *                         Valid bit mask range for ARM Cortex-R5 processor is
+ *                         0 - 23 bits.
+ *
+ * @retval rtosPASS                          on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null input parameter
+ * @retval E_RTOS_INVALID_EVENT_GROUP_HANDLE Invalid event group handle
+ * @retval E_RTOS_INVALID_PARAMETERS         Invalid parameters
+ *
+ */
+static inline rtosError
+rtosEventGroupClearBits(rtosEventGroupHandle xHandle,
+                        const rtosEventBits xBitsToClear)
+{
+    return xEventGroupClearBits(xHandle,
+                                xBitsToClear);
+}
+
+/**
+ * @brief Clear required event group bits from ISR
+ *
+ * This function is a wrapper for xEventGroupClearBitsFromISR() in SafeRTOS to
+ * clear one or more event group bits in an interrupt context.
+ * Clears required fields within the event group based on bit-mask sent as an
+ * argument.
+ * It sets value at pbHigherPriorityTaskWoken if calling this function unblocks
+ * a higher priority task than current task indicating a context switch is
+ * needed before exiting from ISR
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xHandle                    Event group handle
+ * @param[in] xBitsToClear               Bit-mask to clear required fields in
+ *                                       the event group. Valid bit-mask range
+ *                                       for ARM Cortex-R5 processor is 0 - 23
+ *                                       bits
+ * @param[out] pbHigherPriorityTaskWoken Pointer to rtosbool variable
+ *
+ * @retval rtosPASS                          on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null input parameter
+ * @retval E_RTOS_INVALID_EVENT_GROUP_HANDLE Invalid event group handle
+ * @retval E_RTOS_INVALID_PARAMETERS         Invalid parameters
+ * @retval E_RTOS_QUEUE_FULL                 Queue associated with event group
+ *                                           object is full and cannot accept
+ *                                           incoming event group request
+ * @retval E_RTOS_INVALID_DATA_RANGE         Error while copying data to the output
+ *                                           parameter
+ */
+static inline rtosError
+rtosEventGroupClearBitsFromISR(rtosEventGroupHandle xHandle,
+                               const rtosEventBits xBitsToClear,
+                               rtosBool *pbHigherPriorityTaskWoken)
+{
+    return xEventGroupClearBitsFromISR(xHandle,
+                                       xBitsToClear,
+                                       pbHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Wait for one or more bits to set within an event group until timeout
+ *
+ * This function is a wrapper for xEventGroupWaitBits() in SafeRTOS to wait until
+ * given pattern of event group bits is set
+ * Calling task blocks on waiting for required bit fields to be set as long as wait
+ * condition is met until timeout
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xHandle         Event group handle
+ * @param[in] xBitstoWaitFor  Bit-mask to check for required fields. Valid range
+ *                            of bit-mask on ARM Cortex-R5 processor is
+ *                            0 - 23 bits
+ * @param[in] xClearOnExit    Set this bool variable to clear all the bit fields
+ *                            before exiting wait
+ * @param[in] xWaitforAllBits Set this bool variable if all the required bit
+ *                            fields should be set to exit from wait
+ * @param[in] pxEventBitsSet  Pointer to event group bits. Before exiting from
+ *                            wait, value at this address is updated with the
+ *                            status of event group bits
+ * @param[in] xTicksToWait    Timeout in ticks for which the calling task should
+ *                            be held in blocked state waiting for the pattern
+ *                            condition to be set. A value of zero prevents the
+ *                            task from entering the blocked state.
+ *
+ * @retval rtosPASS                          on success
+ * @retval E_RTOS_INVALID_EVENT_GROUP_HANDLE Invalid event group handle
+ * @retval E_RTOS_INVALID_PARAMETERS         Invalid parameters
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null parameter for event group
+ *                                           handle
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED     Scheduler is suspended
+ * @retval E_RTOS_EVENT_GROUP_DELETED        Event group deleted
+ * @retval E_RTOS_EVENT_GROUP_BITS_NOT_SET   Required event group bits not set
+ * @retval E_RTOS_INVALID_DATA_RANGE         Error while copying data to the output
+ *                                           parameter
+ */
+static inline rtosError
+rtosEventGroupWaitBits(rtosEventGroupHandle xHandle,
+                       const rtosEventBits xBitsToWaitFor,
+                       const rtosBool xClearOnExit,
+                       const rtosBool xWaitForAllBits,
+                       rtosEventBits *pxEventBitsSet,
+                       rtosTick xTicksToWait)
+{
+    return xEventGroupWaitBits(xHandle,
+                               xBitsToWaitFor,
+                               (portBaseType)xClearOnExit,
+                               (portBaseType)xWaitForAllBits,
+                               pxEventBitsSet,
+                               xTicksToWait);
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-event-poll.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-event-poll.h
new file mode 100644
index 0000000..ee00b24
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-event-poll.h
@@ -0,0 +1,310 @@
+/* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_EVENT_POLL_H
+#define OSA__OSA_EVENT_POLL_H
+#define FSP__OSA__OSA_EVENT_POLL_H                      1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosEventPollHandle, rtosUCount, rtosEve...
+#include <queue.h>                      // IWYU pragma: keep
+                                        // for xQUEUE
+#include <eventpoll.h>                  // IWYU pragma: export
+                                        // IWYU pragma: no_include "eventpoll.h"
+                                        // for eventPollObjectEventsType
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+
+/**
+ * @brief Computes the size needed for rtosEventPollCreate
+ *
+ * @macro-title Get size of event poll object
+ *
+ * @param[in] uxMaximumRegisteredObjectEvents Maximum number of object events supported with the event poll object
+ *
+ * @retval NumberOfBytes Size of event poll object in bytes.
+ */
+#define rtosEventPollSize(uxMaximumRegisteredObjectEvents)\
+        rtosEVENT_POLL_OVERHEAD_BYTES(uxMaximumRegisteredObjectEvents)
+
+/**
+ * @brief Create an event poll object
+ *
+ * This function is a wrapper for xEventPollCreate() in SafeRTOS to create
+ * an event poll object
+ * It updates pointer to the event poll handle to point to the newly
+ * created event group
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle an event poll object.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pcEventPollMemoryBuffer         Pointer to the memory at which
+ *                                            event poll object will be created
+ * @param[in] uxBufferLengthInBytes           Buffer length to handle event poll
+ *                                            group. It should be equal to
+ *                                            rtosEventPollSize()
+ * @param[in] uxMaximumRegisteredObjectEvents Limit on the number of targets
+ *                                            that can register to the event
+ *                                            poll group. Should be greater than 0.
+ * @param[in] xOwnerTaskHandle                Handle of task creating/owning the
+ *                                            event group.
+ * @param[out] pxEventPollHandle              Pointer to the event poll handle
+ *
+ * @retval rtosPASS                                on success
+ * @retval E_RTOS_EVENT_POLL_OBJECT_ALREADY_IN_USE Input event poll buffer already in
+ *                                                 use.
+ * @retval E_RTOS_INVALID_DATA_RANGE               Invalid input memory address
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED          Null parameter supplied for
+ *                                                 Event poll handle/Task handle
+ *                                                 /Memory buffer
+ * @retval E_RTOS_INVALID_ALIGNMENT                Input buffer not word aligned 
+ * @retval E_RTOS_INVALID_PARAMETERS               Invalid input parameter to
+ *                                                 set maximum number of
+ *                                                 registered objects.
+ * @retval E_RTOS_INVALID_BUFFER_SIZE              Invalid input buffer size
+ * @retval E_RTOS_INVALID_TASK_HANDLE              Invalid input task handle
+ */
+static inline rtosError
+rtosEventPollCreate(void *pcEventPollMemoryBuffer,
+                    rtosUCount uxBufferLengthInBytes,
+                    rtosUCount uxMaximumRegisteredObjectEvents,
+                    rtosTaskHandle xOwnerTaskHandle,
+                    rtosEventPollHandle * pxEventPollHandle)
+{
+    return xEventPollCreate((portInt8Type *)pcEventPollMemoryBuffer,
+                            uxBufferLengthInBytes, uxMaximumRegisteredObjectEvents,
+                            xOwnerTaskHandle, pxEventPollHandle);
+}
+
+/**
+ * @brief Register a target object event to the event poll object
+ *
+ * This function is a wrapper for xEventPollAddObjectEvents() in SafeRTOS
+ * It registers target object along with the specified events to the
+ * event poll group referenced using handle sent as an argument.
+ *
+ * @pre
+ * - An event poll object has been created with a valid handle referring to it
+ *
+ * - An RTOS kernel object has been created with a valid handle referring to it
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xEventPollHandle     Handle referring to the event poll group
+ * @param[in] pvTargetObjectHandle Handle referring to the target object.
+ * @param[in] uxEvents             Events to register with poll group concerning
+ *                                 target object
+ *
+ * @retval rtosPASS                                      on success
+ * @retval E_RTOS_INVALID_EVENT_POLL_OPERATION           Input target object is
+ *                                                       already registered with
+ *                                                       event poll object.
+ * @retval E_RTOS_EVENT_POLL_OBJECT_EVENTS_LIMIT_REACHED No more target objects
+ *                                                       can be registered with
+ *                                                       event poll object
+ * @retval E_RTOS_SCHEDULER_IS_NOT_RUNNING               Scheduler is not running
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED                Null set for event poll
+ *                                                       object handle/
+ *                                                       target object handle
+ * @retval E_RTOS_INVALID_EVENT_POLL_EVENTS              Attempt to set invalid
+ *                                                       events for the target
+ *                                                       object
+ * @retval E_RTOS_INVALID_EVENT_POLL_HANDLE              Invalid event poll handle
+ */
+static inline rtosError
+rtosEventPollAddObjectEvents(rtosEventPollHandle xEventPollHandle,
+                             void *pvTargetObjectHandle,
+                             rtosEventPollValue uxEvents)
+{
+    return xEventPollAddObjectEvents(xEventPollHandle, pvTargetObjectHandle, uxEvents);
+}
+
+/**
+ * @brief Modify object-events of a target object within event poll group
+ *
+ * This function is a wrapper for xEventPollModifyObjectEvents() in SafeRTOS.
+ * It modifies object-events concerning a target object registered with
+ * event poll group referred using handle sent as an argument.
+ *
+ * @pre
+ * - Target object associated with referred object event has been registered
+ * with an event poll object
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xEventPollHandle     Handle referring to the event poll group
+ * @param[in] pvTargetObjectHandle Handle referring to the target object.
+ * @param[in] uxEvents             Event poll value to be set for the target
+ *                                 object registered with poll group.
+ *
+ * @retval rtosPASS                            on success
+ * @retval E_RTOS_INVALID_EVENT_POLL_OPERATION Input target object not
+ *                                             registered with referred event
+ *                                             poll object.
+ * @retval E_RTOS_SCHEDULER_IS_NOT_RUNNING     Scheduler is not running
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED      Null set for event poll object
+ *                                             handle/Target object handle
+ * @retval E_RTOS_INVALID_EVENT_POLL_EVENTS    Attempt to set invalid events
+ *                                             for the target object
+ * @retval E_RTOS_INVALID_EVENT_POLL_HANDLE    Invalid event poll handle
+ */
+static inline rtosError
+rtosEventPollModifyObjectEvents(rtosEventPollHandle xEventPollHandle,
+                                const void *pvTargetObjectHandle,
+                                rtosEventPollValue uxEvents)
+{
+    return xEventPollModifyObjectEvents(xEventPollHandle, pvTargetObjectHandle,
+                                        uxEvents);
+}
+
+/**
+ * @brief Unregister target object along with associated events from event poll
+ * object
+ *
+ * This is a wrapper function for xEventPollRemoveObjectEvents() in SafeRTOS.
+ * It unregisters target-object along with its events from the event poll object
+ *
+ * @pre
+ * - Referred target object has been registered with the input event poll object.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xEventPollHandle     Handle referring to the event poll group
+ * @param[in] pvTargetObjectHandle Handle referring to the target object.
+ *
+ * @retval rtosTRUE                            on success
+ * @retval E_RTOS_SCHEDULER_IS_NOT_RUNNING     Scheduler is not running. Request
+ *                                             cannot be processed.
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED      Null set for event poll object/
+ *                                             Target object handle
+ * @retval E_RTOS_INVALID_EVENT_POLL_HANDLE    Invalid event poll handle
+ * @retval E_RTOS_INVALID_EVENT_POLL_OPERATION Input target object not registered
+ *                                             with referred event poll object.
+ */
+static inline rtosError
+rtosEventPollRemoveObjectEvents(rtosEventPollHandle xEventPollHandle,
+                                const void *pvTargetObjectHandle)
+{
+     return xEventPollRemoveObjectEvents(xEventPollHandle, pvTargetObjectHandle);
+}
+
+
+/**
+ * @brief Wait for an event registered with event poll object
+ *
+ * This function is a wrapper for xEventPollWait() in SafeRTOS.
+ * Object-events invoked by the event poll object referenced
+ * using supplied handle are copied to the input object-events array.
+ * If none of the registered object-events have occurred, this function blocks
+ * the calling task waiting for an object-event until timeout.
+ *
+ * @pre
+ * - Referred target object events have been registered with input event poll
+ * object.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xEventPollHandle         Handle referring to event poll object
+ * @param[in] uxObjectEventsArraySize  Size of input array to store object-event.
+ *                                     Should be at least equal to
+ *                                     uxMaximumRegisteredObjectEvents defined
+ *                                     during event poll object creation
+ * @param[in] xTicksToWait             Timeout in ticks to wait until an event occurs.
+ * @param[out] puxNumberOfObjectEvents Pointer to a count variable to store
+ *                                     number of object-events that occurred
+ * @param[out] axObjectEvents[]        Array to store info of object-events that
+ *                                     occurred. Length of this array should be at least
+ *                                     equal to uxMaximumRegisteredObjectEvents defined
+ *                                     during event poll object creation
+ *
+ * @retval rtosPASS                            on success.
+ * @retval E_RTOS_SCHEDULER_IS_NOT_RUNNING     Scheduler is not running. Request
+ *                                             cannot be processed.
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED      Null set for event poll object
+ *                                             handle/target object handle/array
+ *                                             to store object-events/pointer to
+ *                                             store number of object-events
+ * @retval E_RTOS_INVALID_EVENT_POLL_HANDLE    Invalid event poll handle
+ * @retval E_RTOS_INVALID_EVENT_POLL_OPERATION No object-event registered with
+ *                                             referred event poll object.
+ * @retval E_RTOS_INVALID_PARAMETERS           Zero size set for axObjectEvents
+ *                                             array
+ * @retval E_RTOS_INVALID_DATA_RANGE           Invalid length of the axObjectEvents
+ *                                             array.
+ * @retval E_RTOS_EVENT_GROUP_DELETED          Event group corresponding to the object
+ *                                             events deleted
+ * @retval E_RTOS_NO_EVENT_OCCURRED            No event occurred before the timeout
+ */
+static inline rtosError
+rtosEventPollWait(rtosEventPollHandle xEventPollHandle,
+                  rtosEventPollObjectEventsType axObjectEvents[],
+                  rtosUCount uxObjectEventsArraySize,
+                  rtosUCount * puxNumberOfObjectEvents,
+                  rtosTick xTicksToWait )
+{
+    return xEventPollWait(xEventPollHandle,
+                          (eventPollObjectEventsType *)axObjectEvents,
+                          uxObjectEventsArraySize, puxNumberOfObjectEvents,
+                          xTicksToWait);
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-mutex.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-mutex.h
new file mode 100644
index 0000000..73398aa
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-mutex.h
@@ -0,0 +1,197 @@
+/* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_MUTEX_H
+#define OSA__OSA_MUTEX_H
+#define FSP__OSA__OSA_MUTEX_H                           1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosMutexHandle, FSP__OSPL__RTOS_PORT_H
+#include <queue.h>                      // IWYU pragma: keep
+                                        // for xQUEUE
+#include <mutex.h>                      // IWYU pragma: export
+                                        // IWYU pragma: no_include "mutex.h"
+                                        // for xMutexGetState
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+
+/**
+ * @brief Computes the size needed for rtosMutexCreate.
+ *
+ *
+ * @retval NumberOfBytes Size of mutex object in bytes
+ */
+#define rtosMutexSize()         rtosMUTEX_OVERHEAD_BYTES
+
+/**
+ * @brief Create a mutex lock
+ *
+ * This function is a wrapper for xMutexCreate() in SafeRTOS to create
+ * a mutex object.
+ * It updates pointer to the handle sent as an argument
+ * with newly created mutex
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle a mutex object
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pcMutexBuffer Pointer to the memory location at which mutex
+ *                          will be created. Size of the mutex buffer
+ *                          is rtosMutexSize()
+ *                          Mutex buffer shall be 4-byte aligned
+ * @param[in] pxMutex       Mutex handle 
+ *
+ * @retval rtosPASS                         on success
+ * @retval E_RTOS_INVALID_BUFFER_SIZE       Invalid input buffer size
+ * @retval E_RTOS_QUEUE_ALREADY_IN_USE      A valid queue object referring to a
+ *                                          mutex already associated with
+ *                                          the input memory buffer
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED   NULL supplied for input parameters
+ * @retval E_RTOS_INVALID_DATA_RANGE        Data could not be written in the input buffer
+ * @retval E_RTOS_INVALID_ALIGNMENT         Input buffer is not word aligned
+ */
+static inline rtosError
+rtosMutexCreate(void *pcMutexBuffer,
+                rtosMutexHandle *pxMutex)
+{
+    return xMutexCreate((portInt8Type *)pcMutexBuffer,
+                        pxMutex);
+}
+
+/**
+ * @brief Acquire a mutex
+ *
+ * This function is a wrapper for xMutexTake() in SafeRTOS to acquire a mutex
+ *
+ * @pre
+ * - A mutex has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xMutex     Mutex handle
+ * @param[in] xBlockTime Timeout in ticks to wait until mutex is acquired.
+ *                       A value of zero prevents the calling task from
+ *                       entering the Blocked state.
+ *
+ * @retval rtosPASS                      on success
+ * @retval E_RTOS_INVALID_MUTEX_HANDLE   Invalid mutex handle
+ * @retval E_RTOS_MUTEX_ALREADY_TAKEN    Mutex already acquired
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED Scheduler suspended
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK      Error unblocking the owner task
+ */
+static inline rtosError
+rtosMutexAcquire(rtosMutexHandle xMutex,
+                 rtosTick xBlockTime)
+{
+    return xMutexTake(xMutex,
+                      xBlockTime);
+}
+
+/**
+ * @brief Release acquired mutex
+ *
+ * This function is a wrapper for xMutexGive() in SafeRTOS to release
+ * an acquired mutex.
+ *
+ * @pre
+ * - A mutex has been created with a valid handle
+ *
+ * - Referred mutex was previously acquired.
+ *
+ * - Scheduler has been started
+ *
+ * - Called in a non-interrupt context
+ *
+ * @param[in] xMutex Mutex handle
+ *
+ * @retval rtosPASS                         on success
+ * @retval E_RTOS_INVALID_MUTEX_HANDLE      Invalid handle
+ * @retval E_RTOS_MUTEX_NOT_OWNED_BY_CALLER Mutex not owned by the caller
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED    Scheduler suspended
+ * @retval E_RTOS_MUTEX_CORRUPTED           Corrupt mutex
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK         Error unblocking the owner task
+ */
+static inline rtosError
+rtosMutexRelease(rtosMutexHandle xMutex)
+{
+    return xMutexGive(xMutex);
+}
+
+/**
+ * @brief Get mutex state
+ *
+ * This function is a wrapper for xMutexGetState() in SafeRTOS to query whether
+ * a mutex is available or not.
+ * It updates pointer to type rtosMutexState with current state of mutex lock.
+ * Mutex State can take two values: rtosMUTEX_TAKEN & rtosMUTEX_AVAILABLE
+ *
+ * @pre
+ * - A mutex has been created with a valid handle referring to it
+ *
+ * @param[in] xMutex         Mutex handle
+ * @param[out] puxMutexState Pointer to variable of type rtosMutexState
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_MUTEX_HANDLE    Invalid mutex handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null mutex handle
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error writing data to the output parameter
+ */
+static inline rtosError
+rtosMutexGetState(rtosMutexHandle xMutex,
+                  rtosMutexState *puxMutexState)
+{
+    return xMutexGetState(xMutex,
+                          puxMutexState);
+}
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-queue.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-queue.h
new file mode 100644
index 0000000..a1d243f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-queue.h
@@ -0,0 +1,511 @@
+/* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_QUEUE_H
+#define OSA__OSA_QUEUE_H
+#define FSP__OSA__OSA_QUEUE_H                           1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+#include <misc/attributes.h>            // for UNUSED
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <osa/rtos-values.h>           // for rtosFALSE
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosQueueHandle, rtosTick, rtosUCoun
+#include <queue.h>                      // IWYU pragma: export
+                                        // IWYU pragma: no_include "queue.h"
+                                        // for xQueueReceiveFromISR, xQueueSendFro...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_VALUES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+
+/**
+ * @brief rtosQueueSize() computes the size needed for rtosQueueCreate.
+ *
+ * @_n_                 max number of elements in queue
+ * @_s_                 size of a queue element
+ *
+ * @macro-title Get number of bytes required for the queue.
+ *
+ * @func_req_id 8321837
+ *
+ * @retval NumberOfBytes Size of queue in bytes
+ */
+#define rtosQueueSize(_n_, _s_) (((_n_) * (_s_)) + rtosQUEUE_OVERHEAD_BYTES)
+
+/**
+ * @brief Create a task queue
+ *
+ * This function is a wrapper for xQueueCreate() in SafeRTOS.
+ * It updates the pointer to the queue handle to point
+ * to the newly created queue
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle a queue object.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pcQueueMemory  Pointer to memory at which queue object
+ *                           will be created. Queue buffer should be 4-byte
+ *                           aligned.
+ * @param[in] uxBufferLength Buffer length to handle tasks. Should be equal to
+ *                           rtosQueueSize(_n_, _s_)
+ * @param[in] uxQueueLength  Maximum number of items the queue can hold
+ * @param[in] uxItemSize     Size of the item to be stored in the queue
+ * @param[out] pxQueue       Pointer to queue handle
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_QUEUE_ALREADY_IN_USE    Queue at input memory location already in use
+ * @retval E_RTOS_INVALID_ALIGNMENT       Memory not word aligned
+ * @retval E_RTOS_INVALID_QUEUE_LENGTH    Invalid queue length
+ * @retval E_RTOS_INVALID_BUFFER_SIZE     Invalid buffer size
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null pointer to queue memory/handle
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error while copying data to the input
+ *                                        buffer
+ */
+static inline rtosError
+rtosQueueCreate(void *pcQueueMemory,
+                rtosUCount uxBufferLength,
+                rtosUCount uxQueueLength,
+                rtosUCount uxItemSize,
+                rtosQueueHandle *pxQueue)
+{
+    return xQueueCreate((portInt8Type *)pcQueueMemory,
+                        uxBufferLength,
+                        uxQueueLength,
+                        uxItemSize,
+                        pxQueue);
+}
+
+/*
+ * @brief: Delete queue
+ *
+ * This function does not exist in SafeRTOS, will return rtosPASS.
+ *
+ * @param[in] pxQueue       Pointer to queue handle
+ *
+ * @retval rtosPASS         on success
+ */
+static inline rtosError
+rtosQueueDelete(rtosQueueHandle *pxQueue)
+{
+    UNUSED(pxQueue);
+    return rtosPASS;
+}
+
+/**
+ * @brief Add an item at the end of a queue
+ *
+ * This function is a wrapper for xQueueSend() in SafeRTOS.
+ * Sends a item in the queue in First In First Out (FIFO) order.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] rtosQueue     Queue handle
+ * @param[in] pvItemToQueue Pointer to the item
+ * @param[in] xTicksToWait  Timeout in ticks to wait until the
+ *                          item gets added. A value of 0 prevents the task
+ *                          from entering blocked state.
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null item passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler suspended
+ * @retval E_RTOS_QUEUE_FULL              Queue is full and item cannot be added
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ */
+static inline rtosError
+rtosQueueSend(rtosQueueHandle rtosQueue,
+              const void * const pvItemToQueue,
+              rtosTick xTicksToWait)
+{
+    return xQueueSend(rtosQueue,
+                      pvItemToQueue,
+                      xTicksToWait);
+}
+
+/**
+ * @brief Add an item at the end of a queue
+ *
+ * This function is a wrapper for xQueueSend() in SafeRTOS.
+ * Sends an item in the queue in First In First Out (FIFO) order.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ *
+ *
+ * @param[in] rtosQueue     Queue handle
+ * @param[in] pvItemToQueue Pointer to the item
+ * @param[in] xTicksToWait  Timeout in ticks to wait until the
+ *                          item gets added. A value of 0 prevents the task
+ *                          from entering blocked state.
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null item passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler suspended
+ * @retval E_RTOS_QUEUE_FULL              Queue is full and item cannot be added
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ */
+static inline rtosError
+rtosQueueSendToBack(rtosQueueHandle rtosQueue,
+                    const void *const pvItemToQueue,
+                    rtosTick xTicksToWait)
+{
+    return xQueueSend(rtosQueue,
+                      pvItemToQueue,
+                      xTicksToWait);
+}
+
+/**
+ * @brief Add an item at the front of a queue
+ *
+ * This function is a wrapper for xQueueSendToFront() in SafeRTOS.
+ * Sends an item in the queue in Last In First Out (LIFO) order.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] rtosQueue     Queue handle
+ * @param[in] pvItemToQueue Pointer to item
+ * @param[in] xTicksToWait  Timeout in ticks to wait until
+ *                          item gets added. A value of 0 prevents the task from
+ *                          entering blocked state
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null item passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler suspended
+ * @retval E_RTOS_QUEUE_FULL              Queue is full and item cannot be added
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ */
+static inline rtosError
+rtosQueueSendToFront(rtosQueueHandle rtosQueue,
+                     const void * const pvItemToQueue,
+                     rtosTick xTicksToWait)
+{
+    return xQueueSendToFront(rtosQueue,
+                             pvItemToQueue,
+                             xTicksToWait);
+}
+
+/**
+ * @brief Pick an item from the queue
+ *
+ * This is a wrapper for xQueueReceive() in SafeRTOS
+ * It always picks item from the beginning of a queue.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] rtosQueue    Queue handle
+ * @param[in] pvBuffer     Pointer to the buffer to copy the item. Length of
+ *                         buffer should be at least equal to the item size.
+ * @param[in] xTicksToWait Timeout in ticks to wait until item is picked.
+ *                         A value of 0 prevents the task from entering
+ *                         blocked state
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null buffer passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler is suspended
+ * @retval E_RTOS_QUEUE_EMPTY             Empty queue
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ */
+static inline rtosError
+rtosQueueReceive(rtosQueueHandle rtosQueue,
+                 void *const pvBuffer,
+                 rtosTick xTicksToWait)
+{
+    return xQueueReceive(rtosQueue,
+                         pvBuffer,
+                         xTicksToWait);
+}
+
+/**
+ * @brief Peek an item from queue
+ *
+ * This function is a wrapper for xQueuePeek() in SafeRTOS
+ * It picks an item without removing it from the queue.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] rtosQueue    Queue handle
+ * @param[in] pvBuffer     Pointer to a buffer to copy the item.
+ *                         Length of the buffer should be at least equal to the
+ *                         queue item size.
+ * @param[in] xTicksToWait Timeout in ticks to wait until item is picked.
+ *                         A value of 0 prevents the task from entering the
+ *                         blocked state
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null buffer passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler is suspended
+ * @retval E_RTOS_QUEUE_EMPTY             Empty queue
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ */
+static inline rtosError
+rtosQueuePeek(rtosQueueHandle rtosQueue,
+              void *const pvBuffer,
+              rtosTick xTicksToWait)
+{
+    return xQueuePeek(rtosQueue,
+                      pvBuffer,
+                      xTicksToWait);
+}
+
+/**
+ * @brief Get number of waiting messages in the queue.
+ *
+ * This function is a wrapper for xQueueMessagesWaiting() in SafeRTOS.
+ * It updates value at pointer to a count variable sent as an argument
+ * with latest number of pending items in the queue.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in]  rtosQueue          Queue handle
+ * @param[out] puxMessagesWaiting Pointer to a count variable
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null pointer to count variable passed
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error while copying data to the
+ *                                        output parameter
+ */
+static inline rtosError
+rtosQueueMessageWaiting(rtosQueueHandle rtosQueue,
+                        rtosUCount *puxMessagesWaiting)
+{
+    return xQueueMessagesWaiting(rtosQueue,
+                                 puxMessagesWaiting);
+}
+
+/**
+ * @brief Add an item at the end of a queue from ISR
+ *
+ * This function is a wrapper for xQueueSendFromISR() in SafeRTOS.
+ * Adds an item to the queue from interrupt context in First In First Out (FIFO)
+ * It sets value at pointer to a bool variable sent as an
+ * argument if adding item to the queue unblocks a higher/equal priority task
+ * than the current active task.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] rtosQueue                  Queue handle
+ * @param[in] pvItemToQueue              Pointer to item
+ * @param[out] pbHigherPriorityTaskWoken Pointer to a bool variable
+ *                                       indicating current context.
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null item/context variable passed
+ * @retval E_RTOS_QUEUE_FULL              Queue full and item cannot be added
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error while copying data to the output
+ *                                        parameter
+ */
+static inline rtosError
+rtosQueueSendFromISR(rtosQueueHandle rtosQueue,
+                     const void *const pvItemToQueue,
+                     rtosBool *pbHigherPriorityTaskWoken)
+{
+    return xQueueSendFromISR(rtosQueue,
+                             pvItemToQueue,
+                             pbHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Add an item at the end of a queue from ISR
+ *
+ * This function is a wrapper for xQueueSendFromISR().
+ * Adds an item to the queue from interrupt context in First In First Out (FIFO)
+ * It sets value at pointer to a bool variable sent as an
+ * argument if adding item to the queue unblocks a higher/equal priority task
+ * than the current active task.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] rtosQueue                  Queue handle
+ * @param[in] pvItemToQueue              Pointer to item
+ * @param[out] pbHigherPriorityTaskWoken Pointer to a bool variable
+ *                                       indicating current context.
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null item/context variable passed
+ * @retval E_RTOS_QUEUE_FULL              Queue full and item cannot be added
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error while copying data to the output
+ *                                        parameter
+ */
+static inline rtosError
+rtosQueueSendToBackFromISR(rtosQueueHandle rtosQueue,
+                           const void *const pvItemToQueue,
+                           rtosBool *pbHigherPriorityTaskWoken)
+{
+    return xQueueSendFromISR(rtosQueue,
+                             pvItemToQueue,
+                             pbHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Add an item at the front of a queue from ISR
+ *
+ * This function is a wrapper for xQueueSendToFrontFromISR() in SafeRTOS.
+ * Adds an item to the queue from interrupt context in Last In First Out (LIFO)
+ * order.
+ * It sets value at pointer to a bool variable sent as an argument if adding
+ * item to the queue unblocks a higher/equal priority task than the current
+ * active task.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] rtosQueue                  Queue handle
+ * @param[in] pvItemToQueue              Pointer to item
+ * @param[out] pbHigherPriorityTaskWoken Pointer to a bool variable
+ *                                       indicating current context.
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null item/context variable passed
+ * @retval E_RTOS_QUEUE_FULL              Queue full and item cannot be added
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error while copying data to the output
+ *                                        parameter
+ */
+static inline rtosError
+rtosQueueSendToFrontFromISR(rtosQueueHandle rtosQueue,
+                            const void *const pvItemToQueue,
+                            rtosBool *pbHigherPriorityTaskWoken)
+{
+    return xQueueSendToFrontFromISR(rtosQueue,
+                                    pvItemToQueue,
+                                    pbHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Pick an item from the queue in interrupt context
+ *
+ * This function is a wrapper for xQueueReceiveFromISR() in SafeRTOS
+ * Picks item from the beginning of a queue in an interrupt context
+ * and sets value at pointer to a bool variable sent as an argument if calling
+ * this function unblocks a higher priority task than the current active task.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] rtosQueue                   Queue handle
+ * @param[in] pvBuffer                    Pointer to a buffer to copy the item.
+ *                                        Length of the buffer should be at
+ *                                        least equal to the item size.
+ * @param[out] pbHigherPriorityTaskWoken  Pointer to a bool variable
+ *                                        indicating current context.
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null buffer/context variable passed
+ * @retval E_RTOS_QUEUE_EMPTY             Empty queue
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error while copying data to the output
+ *                                        parameter                                    
+ */
+static inline rtosError
+rtosQueueReceiveFromISR(rtosQueueHandle rtosQueue,
+                        void *const pvBuffer,
+                        rtosBool *pbHigherPriorityTaskWoken)
+{
+    return xQueueReceiveFromISR(rtosQueue,
+                                pvBuffer,
+                                pbHigherPriorityTaskWoken);
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-semaphore.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-semaphore.h
new file mode 100644
index 0000000..b5ecd22
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-semaphore.h
@@ -0,0 +1,319 @@
+/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_SEMAPHORE_H
+#define OSA__OSA_SEMAPHORE_H
+#define FSP__OSA__OSA_SEMAPHORE_H                       1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-sepcific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosSemaphoreHandle, rtosUCount, rtosBool
+#include <queue.h>                      // IWYU pragma: keep
+                                        // for xQueueHandle, xQueueReceive, xQueueSend,.
+#include <semaphore.h>                  // IWYU pragma: export
+                                        // IWYU pragma: no_include "semaphore.h"
+                                        // for xSemaphoreGetCountDepth, xSemaphore...
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+
+/**
+ * @brief rtosSemaphoreSize() computes the size needed for rtosSemaphoreCreate.
+ *
+ * @retval NumberOfBytes Size of semaphore object in bytes
+ */
+#define rtosSemaphoreSize()     rtosSEMAPHORE_OVERHEAD_BYTES
+
+/**
+ * @brief Create a binary semaphore.
+ *
+ * This function is a wrapper for xSemaphoreCreateBinary() in SafeRTOS
+ * to create a binary semaphore object.
+ * It updates the handle sent as an argument to point to the newly
+ * created semaphore
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle a semaphore object.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pcSemaphoreMemory Pointer to the memory location at which
+ *                              semaphore object will be created.
+ *                              Clients shall use rtosSemaphoreSize() to get
+ *                              the size of this pre-allocated memory.
+ *                              Memory buffer shall be 4-byte aligned.
+ * @param[out] xpSemaphore      Pointer to the semaphore handle
+ *
+ * @retval rtosPASS                         on success
+ * @retval E_RTOS_INVALID_BUFFER_SIZE       Invalid input buffer size
+ * @retval E_RTOS_QUEUE_ALREADY_IN_USE      A valid queue object referring to a
+ *                                          semaphore already associated with
+ *                                          the input memory buffer
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED   NULL supplied for input parameters
+ * @retval E_RTOS_INVALID_DATA_RANGE        Data could not be written in the input buffer
+ * @retval E_RTOS_INVALID_ALIGNMENT         Input buffer is not word aligned
+ */
+static inline rtosError
+rtosSemaphoreCreateBinary(void *pcSemaphoreMemory,
+                          rtosSemaphoreHandle *xpSemaphore)
+{
+    return xSemaphoreCreateBinary((portInt8Type *)pcSemaphoreMemory,
+                                  xpSemaphore);
+}
+
+/**
+ * @brief Create a counting semaphore
+ *
+ * This function is a wrapper for xSemaphoreCreateCounting() in SafeRTOS
+ * to create a counting semaphore object.
+ * It updates the handle sent as an argument to point to the newly
+ * created semaphore.
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle a semaphore object.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] uxMaxCount        Max limit of semaphore count.
+ *                              Should be set greater than 0
+ * @param[in] uxInitialCount    Min/Initial count of semaphore count.
+ *                              Should be set less than uxMaxCount
+ * @param[in] pcSemaphoreMemory Pointer to the memory location at which
+ *                              semaphore object will be created.
+ *                              Clients shall use rtosSemaphoreSize() to get
+ *                              the size of this pre-allocated memory.
+ *                              Memory buffer shall be 4-byte aligned.
+ * @param[out] xpSemaphore      Pointer to the semaphore handle
+ *
+ * @retval rtosPASS                               on success
+ * @retval E_RTOS_INVALID_BUFFER_SIZE             Invalid input buffer size
+ * @retval E_RTOS_INVALID_INITIAL_SEMAPHORE_COUNT Invalid semaphore initial
+ * count
+ * @retval E_RTOS_QUEUE_ALREADY_IN_USE      A valid queue object referring to a
+ *                                          semaphore already associated with
+ *                                          the input memory buffer
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED   NULL supplied for input parameters
+ * @retval E_RTOS_INVALID_DATA_RANGE        Data could not be written in the input buffer
+ * @retval E_RTOS_INVALID_ALIGNMENT         Input buffer is not word aligned
+ */
+static inline rtosError
+rtosSemaphoreCreateCounting(void *pcSemaphoreMemory,
+                            rtosUCount uxMaxCount,
+                            rtosUCount uxInitialCount,
+                            rtosSemaphoreHandle *xpSemaphore)
+{
+    return xSemaphoreCreateCounting(uxMaxCount,
+                                    uxInitialCount,
+                                    (portInt8Type *)pcSemaphoreMemory,
+                                    xpSemaphore);
+}
+
+/**
+ * @brief Release a semaphore
+ *
+ * This function is a wrapper for xSemaphoreGive() in SafeRTOS to
+ * release an acquired semaphore.
+ *
+ * @pre
+ * - A semaphore has been created with a valid handle referring to it
+ *
+ * - Referred Semaphore was previously acquired
+ *
+ * - Called from a non-interrupt context.
+ *
+ * - Scheduler has been started.
+ *
+ * @func_req_id 8218883
+ *
+ * @param[in] xSemaphore Semaphore handle
+ *
+ * @retval rtosPASS                        on success
+ * @retval E_RTOS_INVALID_SEMAPHORE_HANDLE Invalid semaphore handle
+ * @retval E_RTOS_SEMAPHORE_ALREADY_GIVEN  Semaphore already released
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED  Null semaphore handle
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED   Scheduler suspended
+ */
+static inline rtosError
+rtosSemaphoreRelease(rtosSemaphoreHandle xSemaphore)
+{
+    return xSemaphoreGive(xSemaphore);
+}
+
+/**
+ * @brief Release a semaphore from ISR
+ *
+ * This function is a wrapper for xSemaphoreGiveFromISR() in SafeRTOS to
+ * release an acquired semaphore in interrupt context.
+ * It sets value at pointer to rtos bool variable sent
+ * as an argument if calling this API unblocks a task of priority equal
+ * to/higher than currently running task.
+ *
+ * @pre
+ * - A semaphore has been created with a valid handle referring to it.
+ *
+ * - Referred semaphore was previously acquired
+ *
+ * - Called from an interrupt context
+ *
+ * - Scheduler has been started.
+ *
+ * @func_req_id 8218883
+ *
+ * @param[in] xSemaphore                 Semaphore handle
+ * @param[out] pbHigherPriorityTaskWoken Pointer to a boolean variable
+ *
+ * @retval rtosPASS                        on success
+ * @retval E_RTOS_INVALID_SEMAPHORE_HANDLE Invalid handle
+ * @retval E_RTOS_SEMAPHORE_ALREADY_GIVEN  Semaphore released already
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED  Null semaphore handle
+ */
+static inline rtosError
+rtosSemaphoreReleaseFromISR(rtosSemaphoreHandle xSemaphore,
+                            rtosBool *pbHigherPriorityTaskWoken)
+{
+    return xSemaphoreGiveFromISR(xSemaphore,
+                                 pbHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Acquire a semaphore
+ *
+ * This function is a wrapper for xSemaphoreTake() in SafeRTOS to
+ * acquire a semaphore.
+ *
+ * @pre
+ * - A semaphore has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context
+ *
+ * - Scheduler has been started.
+ *
+ * @param[in] xSemaphore   Semaphore handle
+ * @param[in] xTicksToWait Timeout in ticks to wait until semaphore is acquired.
+ *                         A value of zero prevents the calling task from
+ *                         entering the Blocked state waiting for semaphore.
+ *
+ * @retval rtosPASS                        on success
+ * @retval E_RTOS_SEMAPHORE_ALREADY_TAKEN  Semaphore already taken
+ * @retval E_RTOS_INVALID_SEMAPHORE_HANDLE Invalid semaphore handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED  Null semaphore handle
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED   Scheduler is suspended
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK        Error unblocking the owner task
+ */
+static inline rtosError
+rtosSemaphoreAcquire(rtosSemaphoreHandle xSemaphore,
+                     rtosTick xTicksToWait)
+{
+    return xSemaphoreTake(xSemaphore, xTicksToWait);
+}
+
+/**
+ * @brief Acquire semaphore from ISR
+ *
+ * This function is a wrapper for xSemaphoreTakeFromISR() in SafeRTOS to
+ * acquire a semaphore in interrupt context.
+ * It sets value at pointer to RTOS bool variable sent as an argument
+ * if calling this API unblocks a task of priority equal to/higher than
+ * currently running task.
+ *
+ * @pre
+ * - A semaphore has been created with a valid handle referring to it
+ *
+ * - Called from an interrupt context
+ *
+ * - Scheduler has been started.
+ *
+ * @param[in] xSemaphore                 Semaphore handle
+ * @param[out] pbHigherPriorityTaskWoken Pointer to boolean variable
+ *
+ * @retval rtosPASS                        on success
+ * @retval E_RTOS_SEMAPHORE_ALREADY_TAKEN  Semaphore already taken
+ * @retval E_RTOS_INVALID_SEMAPHORE_HANDLE Invalid semaphore handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED  Null semaphore handle
+ * @retval E_RTOS_INVALID_DATA_RANGE       Error writing to the output parameter
+ */
+static inline rtosError
+rtosSemaphoreAcquireFromISR(rtosSemaphoreHandle xSemaphore,
+                            rtosBool *pbHigherPriorityTaskWoken)
+{
+    return xSemaphoreTakeFromISR(xSemaphore,
+                                 pbHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Get semaphore count depth
+ *
+ * This function is a wrapper for xSemaphoreGetCountDepth() in SafeRTOS.
+ * It sets value at pointer to RTOS count variable with current semaphore count.
+ * This represents the number of times that rtosSemaphoreAcquire()/
+ * rtosSemaphoreAcquireFromISR() can be successfully called before the next call
+ * to rtosSemaphoreRelease()/rtosSemaphoreReleaseFromISR() is made.
+ *
+ * @pre
+ * - A semaphore has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xSemaphore     Semaphore handle
+ * @param[out] puxCountDepth Pointer to RTOS count variable
+ *
+ * @retval rtosPASS                        on success
+ * @retval E_RTOS_INVALID_SEMAPHORE_HANDLE Invalid semaphore handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED  Null semaphore handle
+ * @retval E_RTOS_INVALID_DATA_RANGE       Error writing to the output parameter
+ */
+static inline rtosError
+rtosSemaphoreGetCountDepth(rtosSemaphoreHandle xSemaphore,
+                           rtosUCount *puxCountDepth)
+{
+    return xSemaphoreGetCountDepth(xSemaphore, puxCountDepth);
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-task.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-task.h
new file mode 100644
index 0000000..857d881
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-task.h
@@ -0,0 +1,859 @@
+/* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_TASK_H
+#define OSA__OSA_TASK_H
+#define FSP__OSA__OSA_TASK_H                            1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosBool, rtosTaskHandle, rtosTick, rtos...
+#include <task.h>                       // IWYU pragma: export
+                                        // IWYU pragma: no_include "task.h"
+                                        // for xTaskGetTickCountFromISR, xTaskIsSc...
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @brief rtosTCBSize() computes size of task TCB needed for rtosTaskCreate.
+ *
+ * @retval NumberOfBytes Size of TCB in bytes
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx", MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#define rtosTCBSize()           rtosTCB_OVERHEAD_BYTES
+
+/**
+ * @brief Initialize task scheduler
+ *
+ * This function is a wrapper for xTaskInitializeScheduler() in SafeRTOS to
+ * initialize a task scheduler.
+ * It configures scheduler private data and passes application specific data
+ * to the SafeRTOS scheduler by translating structures and types used by NVIDIA
+ * code to those used by SafeRTOS.
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it.
+ *
+ * - Scheduler init parameters have been set.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxSchedInitParameters Pointer to rtosSchedParameters structure
+ *                                  containing scheduler private data required for
+ *                                  initialization.
+ *
+ * @retval rtosPASS                              on success
+ * @retval E_RTOS_EXECUTING_IN_UNPRIVILEGED_MODE Processor in unprivileged mode
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED        Null init parameters
+ * @retval E_RTOS_QUEUE_ALREADY_IN_USE           A valid queue exists at the
+ *                                               input timer buffer provided as
+ *                                               part of scheduler parameters
+ * @retval E_RTOS_INVALID_ALIGNMENT              Input buffer not word aligned
+ * @retval E_RTOS_INVALID_QUEUE_LENGTH           Invalid timer queue length
+ * @retval E_RTOS_INVALID_BUFFER_SIZE            Invalid buffer size to
+ *                                               accommodate the timer or timer
+ *                                               task
+ * @retval E_RTOS_INVALID_DATA_RANGE             Error while copying data to the
+ *                                               input buffer
+ * @retval E_RTOS_INVALID_PRIORITY               Timer task priority above stated
+ *                                               maximum
+ * @retval E_RTOS_INVALID_TASK_CODE_POINTER      Invalid pointer to the timer
+ *                                               task code
+ * @retval E_RTOS_TASK_STACK_ALREADY_IN_USE      Timer task stackbuffer already
+ *                                               in use.
+ * @retval E_RTOS_SUPPLIED_BUFFER_TOO_SMALL      Supplied buffer not
+ *                                               sufficient to hold the timer task
+ */
+rtosError
+rtosTaskInitializeScheduler(const rtosSchedParameters *const pxSchedInitParameters);
+
+/**
+ * @brief Create a task
+ *
+ * This function is a wrapper for xTaskCreate() in SafeRTOS to create a new
+ * task and place it in ready state. It provides a translation of structures
+ * and types used by NVIDIA code to those used by SafeRTOS.
+ * It updates the pointer to task handle using task init structure sent as
+ * an argument to refer to the newly created task.
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * initialized for the task control block.
+ *
+ * - Task init parameters have been initialized
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxTaskParameters Pointer to a rtosTaskParameters structure that
+ *                             contains the parameters used to create a task
+ * @param[out] pxCreatedTask   Pointer to task handle
+ *
+ * @retval rtosPASS success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED          Null pointer to handle/task
+ *                                                 init structure
+ * @retval E_RTOS_INVALID_PRIORITY                 Task priority above stated
+ *                                                 maximum
+ * @retval E_RTOS_INVALID_TASK_CODE_POINTER        Invalid pointer to task code
+ * @retval E_RTOS_TASK_STACK_ALREADY_IN_USE        Memory pointed by stack
+ *                                                 buffer already in use.
+ * @retval E_RTOS_INVALID_ALIGMENT                 Stack buffer not word aligned
+ * @retval E_RTOS_SUPPLIED_BUFFER_TOO_SMALL        Supplied buffer not
+ *                                                 sufficient to hold the task
+ * @retval E_RTOS_INVALID_BUFFER_SIZE              Buffer size not a power of 2
+ * @retval E_RTOS_INVALID_DATA_RANGE               Error while copying data to the
+ *                                                 input buffer
+ */
+rtosError
+rtosTaskCreate(const rtosTaskParameters * const pxTaskParameters,
+               rtosTaskHandle *pxCreatedTask);
+
+/**
+ * @brief Delete a task
+ *
+ * This function is a wrapper for xTaskDelete() in SafeRTOS to delete a task.
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * - Scheduler is in running state if the request is to delete the calling task
+ *
+ * @param[in] pxTaskToDelete Input task handle
+ *
+ * @retval rtosPASS                   on success
+ * @retval E_RTOS_INVALID_TASK_HANDLE Invalid task handle
+ */
+static inline rtosError
+rtosTaskDelete(rtosTaskHandle pxTaskToDelete)
+{
+    return xTaskDelete(pxTaskToDelete);
+}
+
+/**
+ * @brief Delay a task for required time
+ *
+ * This function is a wrapper for xTaskDelay() in SafeRTOS.
+ * Places active task in blocked state for fixed number of cycles.
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xTicksToDelay Time in ticks to delay the task. A value of 0
+ *                          will cause the task to yield instead of entering the
+ *                          blocked state
+ *
+ * @retval rtosPASS                      on success
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED Scheduler suspended
+ */
+static inline rtosError
+rtosTaskDelay(rtosTick xTicksToDelay)
+{
+    return xTaskDelay(xTicksToDelay);
+}
+
+/**
+ * @brief Delay a task until specified time.
+ *
+ * This function is a wrapper for xTaskDelayUntil() in SafeRTOS.
+ * It delays active task for a fixed period and wakes it
+ * up again at tick(previous wake time + Delay time).
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxPreviousWakeTime Pointer to variable of type rtosTick
+ *                               having previous wake time. Must be initialized
+ *                               with current time before first use. Updated
+ *                               automatically by this call thereafter.
+ * @param[in] xTimeIncrement     Time for which task must be delayed
+ *                               (Cycle time period)
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler suspended
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null passed for previous wake time
+ * @retval E_RTOS_DID_NOT_YIELD           Context Yield did not happen
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error writing data to the output parameter
+ */
+static inline rtosError
+rtosTaskDelayUntil(rtosTick *pxPreviousWakeTime,
+                   rtosTick xTimeIncrement)
+{
+    return xTaskDelayUntil(pxPreviousWakeTime, xTimeIncrement);
+}
+
+/**
+ * @brief Get priority of task
+ *
+ * This function is a wrapper for xTaskPriorityGet() in SafeRTOS.
+ * It updates value at pointer to variable of type
+ * rtosPriority sent as an argument with latest priority of input task
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxTask      Input task handle
+ * @param[in] puxPriority Pointer to a variable holding task priority
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED NULL task handle/pointer
+ * @retval E_RTOS_INVALID_TASK_HANDLE     Invalid task handle
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error writing data to the output parameter
+ */
+static inline rtosError
+rtosTaskPriorityGet(rtosTaskHandle pxTask,
+                    rtosPriority *puxPriority)
+{
+    return xTaskPriorityGet(pxTask, puxPriority);
+}
+
+/**
+ * @brief Set priority of a task
+ *
+ * This function is a wrapper for xTaskPrioritySet() in SafeRTOS to
+ * change the priority of a task.
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxTask        Input task handle
+ * @param[in] uxNewPriority Input task priority. Maximum priority
+ *                          is (configMAX_PRIORITIES - 1)
+ *
+ * @retval rtosPASS                   on success
+ * @retval E_RTOS_INVALID_TASK_HANDLE Invalid task handle
+ * @retval E_RTOS_INVALID_PRIORITY    Invalid task priority
+ */
+static inline rtosError
+rtosTaskPrioritySet(rtosTaskHandle pxTask,
+                    rtosPriority uxNewPriority)
+{
+    return xTaskPrioritySet(pxTask, uxNewPriority);
+}
+
+/**
+ * @brief Suspend a task
+ *
+ * This function is a wrapper for xTaskSuspend() in SafeRTOS.
+ * Places active task in suspended state
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxTaskToSuspend Input task handle. Value of NULL
+ *                            suspends the calling task
+ *
+ * @retval rtosPASS                      on success
+ * @retval E_RTOS_SCHEDULER_SUSPENDED    Scheduler suspended
+ * @retval E_RTOS_INVALID_TASK_HANDLE    Invalid handle
+ * @retval E_RTOS_TASK_ALREADY_SUSPENDED Task already suspended
+ */
+static inline rtosError
+rtosTaskSuspend(rtosTaskHandle pxTaskToSuspend)
+{
+    return xTaskSuspend(pxTaskToSuspend);
+}
+
+/**
+ * @brief Resume a suspended task
+ *
+ * This function is a wrapper for xTaskResume() in SafeRTOS.
+ * Resumes a suspended task and puts it ready state.
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * - The task being referred was suspended.
+ *
+ * @param[in] pxTaskToResume Input task handle
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_TASK_WAS_NOT_SUSPENDED  Task was not suspended
+ * @retval E_RTOS_INVALID_TASK_HANDLE     Invalid handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null task handle
+ */
+static inline rtosError
+rtosTaskResume(rtosTaskHandle pxTaskToResume)
+{
+    return xTaskResume(pxTaskToResume);
+}
+
+/**
+ * @brief Get handle of current task
+ *
+ * This function is a wrapper for xTaskGetCurrentTaskHandle() in SafeRTOS.
+ * It returns handle of current task.
+ * No input arguments needed.
+ *
+ * @pre
+ * - Scheduler has been initialized and started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @retval xHandle Handle of the current task
+ */
+static inline rtosTaskHandle
+rtosTaskGetCurrentTaskHandle(void)
+{
+    return xTaskGetCurrentTaskHandle();
+}
+
+/**
+ * @brief Start a task scheduler
+ *
+ * This function is a wrapper for xTaskStartScheduler() in SafeRTOS.
+ * It starts scheduler if a set of preconditions are met.
+ * This can be ignored by passing input argument xUserKernelConfigurationChecks
+ * as rtosFALSE in which case scheduler will start regardless of the state.
+ *
+ * @pre
+ * - Scheduler has been initialized
+ *
+ * - A task has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context
+ *
+ * - Called with CPU in privileged mode
+ *
+ * @param[in] xUserKernelConfigurationChecks Bool variable to be set for
+ *                                           checking the pre-conditions before
+ *                                           starting the scheduler.
+ *
+ * @retval rtsoPASS                                 on success
+ * @retval E_RTOS_NO_TASKS_CREATED                  No tasks created
+ * @retval E_RTOS_SCHEDULER_ALREADY_RUNNING         Scheduler is already running
+ * @retval E_RTOS_BAD_OR_NO_TICK_RATE_CONFIGURATION Clock/tick rate parameter
+ *                                                  invalid/null
+ * @retval E_RTOS_EXECUTING_IN_UNPRIVILEGED_MODE    Processor in unprivileged
+ *                                                  mode
+ * @retval E_RTOS_INVALID_ALIGNMENT                 System stack address
+ *                                                  misaligned
+ * @retval E_RTOS_INVALID_BUFFER_SIZE               Size of the system stack is
+ *                                                  insufficient
+ * @retval E_RTOS_INVALID_PRIORITY                  Invalid priority for the idle task
+ * @retval E_RTOS_INVALID_TASK_CODE_POINTER         Invalid pointer to task code
+ * @retval E_RTOS_TASK_STACK_ALREADY_IN_USE         Memory pointed by stack
+ *                                                  buffer already in use.
+ * @retval E_RTOS_SUPPLIED_BUFFER_TOO_SMALL         Supplied buffer not
+ *                                                  sufficient to hold the idle task
+ *                                                  input buffer
+ */
+static inline rtosError
+rtosTaskStartScheduler(rtosBool xUserKernelConfigurationChecks)
+{
+    INLINE_RFD(MISRA, DEVIATE, Rule_10_5, "Approval: Bug 200532009, DR: SWE-FSP-020-SWSADR.docx");
+    return (rtosError)xTaskStartScheduler((portBaseType)xUserKernelConfigurationChecks);
+}
+
+/**
+ * @brief Suspend a scheduler
+ *
+ * This function is a wrapper for xTaskSuspendScheduler() in SafeRTOS
+ * It suspends scheduler irrespective of current state.
+ * Has no input arguments and returns none.
+ *
+ * @pre
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ */
+static inline void
+rtosTaskSuspendScheduler(void)
+{
+    vTaskSuspendScheduler();
+}
+
+/**
+ * @brief Resume suspended scheduler
+ *
+ * This function is a wrapper for xTaskResumeScheduler() in SafeRTOS.
+ * Transitions the suspended scheduler into active state.
+ * No input arguments needed.
+ *
+ * @pre
+ * - Scheduler has been started and currently in a suspended state
+ *
+ * - Called from a non-interrupt context
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_SCHEDULER_NOT_SUSPENDED Scheduler not suspended.
+ */
+static inline rtosError
+rtosTaskResumeScheduler(void)
+{
+    return xTaskResumeScheduler();
+}
+
+/**
+ * @brief Get ticks count
+ *
+ * This function is a wrapper for xTaskGetTickCount() in SafeRTOS.
+ * It returns ticks count since the scheduler was started.
+ * No input arguments needed.
+ *
+ * @pre
+ * - Called from a non-interrupt context.
+ *
+ * @retval xTicks Number of ticks passed since scheduler was started.
+ */
+static inline rtosTick
+rtosTaskGetTickCount(void)
+{
+    return xTaskGetTickCount();
+}
+
+/**
+ * @brief Get ticks count from ISR
+ *
+ * This function is a wrapper for xTaskGetTickCountFromISR() in SafeRTOS.
+ * Returns ticks count in an interrupt context since the scheduler was started.
+ * No input arguments needed.
+ *
+ * @pre
+ * - Called from an interrupt context
+ *
+ * @retval xTicks Number of ticks passed since scheduler was started.
+ */
+static inline rtosTick
+rtosTaskGetTickCountFromISR(void)
+{
+    return xTaskGetTickCountFromISR();
+}
+
+/**
+ * @brief Request task yield.
+ *
+ * This function is a wrapper for taskYIELD() in SafeRTOS.
+ * It enables yield to a task of equal/higher priority
+ * than current task. Has no input arguments and returns none.
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ */
+static inline void
+rtosTaskYield(void)
+{
+    taskYIELD();
+}
+
+/**
+ * @brief Request task yield from ISR
+ *
+ * This function is a wrapper for taskYIELD_FROM_ISR() in SafeRTOS.
+ * It enables yield in an interrupt context to a task of
+ * equal/higher priority than current task. Returns none.
+ * Does nothing if input argument is rtosFALSE.
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] xSwitchRequired Bool variable to indicate need for switch
+ */
+static inline void
+rtosTaskYieldFromISR(rtosBool xSwitchRequired)
+{
+    INLINE_RFD(MISRA, DEVIATE, Rule_10_5, "Approval: Bug 200532009, DR: SWE-FSP-020-SWSADR.docx");
+    taskYIELD_FROM_ISR(xSwitchRequired);
+}
+
+/**
+ * @brief Enter critical section
+ *
+ * This function is a wrapper for taskENTER_CRITICAL() in SafeRTOS.
+ * Enables a task to enter critical section.
+ * Has no input arguments and returns none.
+ *
+ * @pre
+ * - Called from a non-interrupt context
+ */
+static inline void
+rtosTaskEnterCritical(void)
+{
+    taskENTER_CRITICAL();
+}
+
+/**
+ * @brief Exit critical section
+ *
+ * This function is a wrapper for taskEXIT_CRITICAL() in SafeRTOS.
+ * Enables a task to exit from critical section.
+ * No input arguments needed and returns none.
+ *
+ * @pre
+ * - RTOS state must already be in critical section
+ *
+ * - Called from a non-interrupt context
+ */
+static inline void
+rtosTaskExitCritical(void)
+{
+    taskEXIT_CRITICAL();
+}
+
+/**
+ * @brief Mask required interrupts from ISR
+ *
+ * This function is a wrapper for taskSET_INTERRUPT_MASK_FROM_ISR() in SafeRTOS.
+ * Sets the interrupt mask to mask all interrupts at the
+ * configSYSTEM_INTERRUPT_PRIORITY or lower. This prevents any interrupts that
+ * call a system API function from interrupting the current interrupt handler
+ * It has significance only if interrupt nesting is supported on port.
+ * Input arguments none.
+ *
+ * @pre
+ * - Called only in interrupt context
+ *
+ * @func_req_id 8219165
+ *
+ * @retval uxOriginalInterruptState Original interrupt mask.
+ */
+static inline rtosInterruptState
+rtosTaskSetInterruptMaskFromISR(void)
+{
+    return taskSET_INTERRUPT_MASK_FROM_ISR();
+}
+
+/**
+ * @brief Unmask required interrupts from ISR
+ *
+ * This function is wrapper for taskCLEAR_INTERRUPT_MASK_FROM_ISR() in SafeRTOS.
+ * It clears interrupt mask set using rtosTaskSetInterruptMaskFromISR
+ * and retrieves the original mask based on input argument. Returns none.
+ *
+ * @pre
+ * - Called only in interrupt context
+ *
+ * @param[in] uxOriginalInterruptState Original interrupt mask
+ */
+static inline void
+rtosTaskClearInterruptMaskFromISR(rtosInterruptState uxOriginalInterruptState)
+{
+    taskCLEAR_INTERRUPT_MASK_FROM_ISR(uxOriginalInterruptState);
+}
+
+/**
+ * @brief Retrieve scheduler status
+ *
+ * This function is a wrapper for xTaskIsSchedulerStarted() in SafeRTOS.
+ * Checks and returns true if there has been a successful call to
+ * rtosTaskStartScheduler()
+ * No input arguments
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @retval rtosTRUE  Scheduler has been started
+ * @retval rtosFALSE Otherwise
+ */
+static inline rtosBool
+rtosTaskIsSchedulerStarted(void)
+{
+    INLINE_RFD(MISRA, DEVIATE, Rule_10_5, "Approval: Bug 200532009, DR: SWE-FSP-020-SWSADR.docx");
+    return (rtosBool)xTaskIsSchedulerStarted();
+}
+
+/**
+ * @brief Retrieve scheduler status from ISR
+ *
+ * This function is a wrapper for xTaskIsSchedulerStartedFromISR() in SafeRTOS
+ * Checks and returns true if there has been a successful call to
+ * rtosTaskStartScheduler()
+ * No input arguments
+ *
+ * @pre
+ * - Called from an interrupt context
+ *
+ * @retval rtosTRUE  Scheduler has been started
+ * @retval rtosFALSE Otherwise
+ */
+static inline rtosBool
+rtosTaskIsSchedulerStartedFromISR(void)
+{
+    INLINE_RFD(MISRA, DEVIATE, Rule_10_5, "Approval: Bug 200532009, DR: SWE-FSP-020-SWSADR.docx");
+    return (rtosBool)xTaskIsSchedulerStartedFromISR();
+}
+
+/**
+ * @brief Wait for notification from a calling task with timeout
+ *
+ * This function is a wrapper for xTaskNotifyWait() in SafeRTOS
+ * Each task has a notification value which is initialized to 0 when it is
+ * created.
+ * It blocks the calling task for notification from another task.
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] uxBitsToClearOnEntry    Bitmask to clear bits in the receiving
+ *                                    task notification value on entering wait.
+ *                                    Length of the bitmask is 32 bits
+ * @param[in] uxBitsToClearOnExit     Bitmask to clear bits in the receiving
+ *                                    task notification value before exiting wait
+ *                                    Length of the bitmask is 32 bits
+ * @param[in] xTicksToWait            Timeout in ticks to wait for notification
+ * @param[out] puxNotificationValue   Pointer to receiving task notification
+ *                                    value. Value at this pointer is updated
+ *                                    with calling task notification value as it
+ *                                    was before clearing the bits using
+ *                                    uxBitsToClearOnExit.
+ *
+ * @retval rtosPASS                         on success
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED    Scheduler is suspended.
+ * @retval E_RTOS_NOTIFICATION_NOT_RECEIVED No notification has been received
+ * @retval E_RTOS_INVALID_DATA_RANGE        Error writing data to the output
+ *                                          parameter
+ */
+static inline rtosError
+rtosTaskNotifyWait(rtosTaskNotifyBits uxBitsToClearOnEntry,
+                   rtosTaskNotifyBits uxBitsToClearOnExit,
+                   rtosTaskNotifyValue *puxNotificationValue,
+                   rtosTick xTicksToWait)
+{
+    return xTaskNotifyWait(uxBitsToClearOnEntry,
+                           uxBitsToClearOnExit,
+                           puxNotificationValue,
+                           xTicksToWait);
+}
+
+/**
+ * @brief Send notification to waiting task.
+ *
+ * This function is wrapper for rtosTaskNotifySend() in SafeRTOS.
+ * Each task has a notification value which is initialized to 0 when it is
+ * created.
+ * The function sends notification to a waiting task and updates the receiving
+ * task's notification as per the set criteria and value sent as an argument.
+ *
+ * Each task can take one of the following notification states:
+ *
+ *  - rtosNotification_NOT_WAITING - Not waiting for any notification from other
+ *                                   task
+ *
+ *  - rtosNotification_WAITING - Task is waiting for some notification
+ *
+ *  - rtosNotification_NOTIFIED - Task has sent a notification.
+ *
+ * Receiving task notification value can be updated using following criteria:
+ *
+ *  - rtosNotification_NO_ACTION Do not update task notification value
+ *
+ *  - rtosNotification_SET_BITS Set task notification value by ORing with uxValue
+ *
+ *  - rtosNotification_INCREMENT Increment the task notification value
+ *
+ *  - rtosNotification_SET_VALUE_WITH_OVERWRITE Copy uxValue to notification
+ *                                              value even if the previous value
+ *                                              has not been read by the task.
+ *
+ *  - rtosNotification_SET_VALUE_WITHOUT_OVERWRITE Set the receiving task's
+ *                                                 notification value only if
+ *                                                 there is no notification
+ *                                                 pending.
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Another task is waiting for some notification.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xTaskToNotify Handle of waiting task
+ * @param[in] uxValue       Notification value to be updated for receiving task
+ * @param[in] xAction       Receiving task notification update criteria
+ *
+ * @retval rtosPASS                            on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED      Null receiving task handle
+ * @retval E_RTOS_INVALID_TASK_HANDLE          Invalid task handle
+ * @retval E_RTOS_INVALID_PARAMETERS           Invalid notification value/action
+ * @retval E_RTOS_NOTIFICATION_ALREADY_PENDING Notification pending
+ */
+static inline rtosError
+rtosTaskNotifySend(rtosTaskHandle xTaskToNotify,
+                   rtosTaskNotifyAction xAction,
+                   rtosTaskNotifyValue uxValue)
+{
+    return xTaskNotifySend(xTaskToNotify,
+                           xAction,
+                           uxValue);
+}
+
+/**
+ * @brief Send notification to waiting task from ISR.
+ *
+ * This function is a wrapper for rtosTaskNotifySendFromISR() in SafeRTOS.
+ * Each task has a notification value which is initialized to 0 when it is
+ * created.
+ * It sends notification to a waiting task and updates
+ * receiving task's notification as per the set criteria and value sent as an
+ * argument.
+ *
+ * Each task can take one of the following notification states:
+ *
+ *  - rtosNotification_NOT_WAITING - Not waiting for any notification from other
+ *                    task
+ *
+ *  - rtosNotification_WAITING - Task is waiting for some notification
+ *
+ *  - rtosNotification_NOTIFIED - Task has sent a notification.
+ *
+ * Receiving task notification value can be updated using following criteria:
+ *
+ *  - rtosNotification_NO_ACTION Do not update task notification value
+ *
+ *  - rtosNotification_SET_BITS Set task notification value as per uxValue
+ *
+ *  - rtosNotification_INCREMENT Increment the task notification value
+ *
+ *  - rtosNotification_SET_VALUE_WITH_OVERWRITE Update task notification value
+ *                                              even if the previous
+ *                                              notification is pending.
+ *
+ *  - rtosNotification_SET_VALUE_WITHOUT_OVERWRITE Set the task's notification
+ *                                                 only if there is no pending
+ *                                                 notification
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Another task is waiting for some notification.
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xTaskToNotify              Handle of waiting task
+ * @param[in] uxValue                    Notification value to be updated
+ *                                       for receiving task
+ * @param[in] xAction                    Notification update criteria
+ * @param[in] pxHigherPriorityTaskWoken  An in/out parameter that is set if
+ *                                       calling this function wakes an higher or
+ *                                       equal priority task
+ *
+ * @retval rtosPASS                            on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED      Null receiving task handle
+ * @retval E_RTOS_INVALID_TASK_HANDLE          Invalid task handle
+ * @retval E_RTOS_INVALID_PARAMETERS           Invalid notification value/action
+ * @retval E_RTOS_NOTIFICATION_ALREADY_PENDING Notification pending
+ * @retval E_RTOS_INVALID_DATA_RANGE           Error writing data to the output
+ *                                             parameter
+ */
+static inline rtosError
+rtosTaskNotifySendFromISR(rtosTaskHandle xTaskToNotify,
+                          rtosTaskNotifyAction xAction,
+                          rtosTaskNotifyValue uxValue,
+                          rtosBool *pxHigherPriorityTaskWoken)
+{
+    return xTaskNotifySendFromISR(xTaskToNotify,
+                                  xAction,
+                                  uxValue,
+                                  pxHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Generate system tick
+ *
+ * This function is a wrapper for vTaskProcessSystemTickFromISR() in SafeRTOS.
+ * It is used to generate system tick and should be called from the
+ * system tick handler.
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * Has no input arguments and returns none.
+ */
+static inline void rtosSystemTickHandler(void)
+{
+    vTaskProcessSystemTickFromISR();
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-timer.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-timer.h
new file mode 100644
index 0000000..26e2de6
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-timer.h
@@ -0,0 +1,419 @@
+/* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_TIMER_H
+#define OSA__OSA_TIMER_H
+#define FSP__OSA__OSA_TIMER_H                           1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosTimerHandle, rtosTick, rtosBool, FSP...
+#include <queue.h>                      // IWYU pragma: keep
+                                        // for xQueueHandle
+#include <timers.h>                     // IWYU pragma: export
+                                        // IWYU pragma: no_include "timers.h"
+                                        // for xTimerChangePeriodFromISR, xTimerSt...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @brief Computes the size of pre-allocated memory required for timer control
+ * block
+ *
+ * @retval NumberOfBytes Size of Timer control block
+ */
+#define rtosTimerCBSize()     rtosTIMER_CONTROL_BLOCK_OVERHEAD_BYTES
+
+/**
+ * @brief Computes the size of pre-allocated memory required for timer parameter
+ * structure supplied as an input to rtosTimerCreate.
+ *
+ * @retval NumberOfBytes Size of timer instance parameters structure
+ */
+#define rtosTimerInstanceParametersSize() \
+                                     rtosTIMER_INSTANCE_PARAMETER_OVERHEAD_BYTES
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @brief Create a timer.
+ *
+ * This function is a wrapper for xTimerCreate() in SafeRTOS.
+ * It updates the handle sent as
+ * an argument to point to the newly created timer
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle timer control block and instance parameters
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxTimerParameters Pointer to timer init parameter
+ *                              structure (rtosTimerInitParametersType)
+ * @param[out] pxTimerHandle    Pointer to timer handle
+ *
+ * @retval rtosPASS                           on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED     Null pointer to timer init
+ *                                            parameter/Timer handle
+ * @retval E_RTOS_INVALID_PARAMETERS          Invalid timer init parameters
+ * @retval E_RTOS_INVALID_TIMER_TASK_INSTANCE Invalid timer task instance
+ * @retval E_RTOS_TIMER_ALREADY_IN_USE        Input Timer init parameter
+ *                                            already has a timer instance associated
+ *                                            with it.
+ * @retval E_RTOS_INVALID_DATA_RANGE          Error writing data to the memory buffer
+ */
+rtosError
+rtosTimerCreate(const rtosTimerInitParametersType *const pxTimerParameters,
+                rtosTimerHandle *pxTimerHandle);
+
+/**
+ * @brief Start a timer
+ *
+ * This function is a wrapper for xTimerStart() in SafeRTOS.
+ * Calling task is held in blocked state for block time before successfully
+ * sending the start command to the timer
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xTimer     Timer handle
+ * @param[in] xBlockTime Block time in ticks
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_TIMER_HANDLE    Invalid timer handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null timer handle passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler is suspended
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ * @retval E_RTOS_QUEUE_FULL              Timer command queue is full and
+ */
+static inline rtosError
+rtosTimerStart(rtosTimerHandle xTimer,
+               rtosTick xBlockTime)
+{
+    return xTimerStart(xTimer, xBlockTime);
+}
+
+/**
+ * @brief Stop a timer
+ *
+ * This function is a wrapper for xTimerStop() in SafeRTOS.
+ * Calling task is held in blocked state for block time before successfully
+ * sending stop command to the timer
+ *
+ * @pre
+ * - Referred timer has been started
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xTimer     Timer handle
+ * @param[in] xBlockTime Block time in ticks
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_TIMER_HANDLE    Invalid timer handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null timer handle passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler suspended
+ * @retval E_RTOS_QUEUE_FULL              Timer command queue is full and
+ *                                        cannot accept new requests
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ */
+static inline rtosError
+rtosTimerStop(rtosTimerHandle xTimer,
+              rtosTick xBlockTime)
+{
+    return xTimerStop(xTimer, xBlockTime);
+}
+
+/**
+ * @brief Change timer period
+ *
+ * This function is a wrapper for xTimerChangePeriod() in SafeRTOS.
+ * Calling task is held in blocked state for block time before successfully
+ * sending change period command to the timer
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xTimer            Timer handle
+ * @param[in] xBlockTime        Block time in ticks
+ * @param[in] xNewPeriodInTicks New timer period in ticks. Should be
+ *                              greater than 0.
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_TIMER_HANDLE    Invalid timer handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null timer handle passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler suspended
+ * @retval E_RTOS_QUEUE_FULL              Timer command queue is full and
+ *                                        cannot accept new requests
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ */
+static inline rtosError
+rtosTimerChangePeriod(rtosTimerHandle xTimer,
+                      rtosTick xNewPeriodInTicks,
+                      rtosTick xBlockTime)
+{
+    return xTimerChangePeriod(xTimer, xNewPeriodInTicks, xBlockTime);
+}
+
+/**
+ * @brief Delete a timer
+ *
+ * This function is a wrapper for xTimerDelete() in SafeRTOS.
+ * Calling task is held in blocked state for block time before successfully
+ * sending delete command to the timer
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xTimer     Timer handle
+ * @param[in] xBlockTime Block time in ticks
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_TIMER_HANDLE    Invalid timer handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null timer handle passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler suspended
+ * @retval E_RTOS_QUEUE_FULL              Timer command queue is full and
+ *                                        cannot accept new requests
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ */
+static inline rtosError
+rtosTimerDelete(rtosTimerHandle xTimer,
+                rtosTick xBlockTime)
+{
+    return xTimerDelete(xTimer, xBlockTime);
+}
+
+// ISR friendly commands of the timer commands
+
+/**
+ * @brief Start a timer from ISR
+ *
+ * This function is a wrapper for xTimerStartFromISR() in SafeRTOS.
+ * It sets value at pxHigherPriorityTaskWoken if calling this function
+ * unblocks the timer service whose priority is equal to/higher than
+ * the current task
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xTimer                     Timer handle
+ * @param[out] pxHigherPriorityTaskWoken Pointer to rtosBool variable
+ *                                       to indicate current context
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_TIMER_HANDLE    Invalid timer handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null timer handle passed
+ * @retval E_RTOS_QUEUE_FULL              Timer command queue is full and
+ *                                        cannot accept new requests
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error writing data to the output parameter
+ */
+static inline rtosError
+rtosTimerStartFromISR(rtosTimerHandle xTimer,
+                      rtosBool *pxHigherPriorityTaskWoken)
+{
+    return xTimerStartFromISR(xTimer, pxHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Stop a timer from ISR
+ *
+ * This function is a wrapper for xTimerStopFromISR() in SafeRTOS.
+ * It sets value at pxHigherPriorityTaskWoken if calling this function unblocks
+ * the timer service whose priority is equal to/higher than the current task
+ *
+ * @pre
+ * - Referred timer has been started
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xTimer                     Timer handle
+ * @param[out] pxHigherPriorityTaskWoken Pointer to rtosBool variable
+ *                                       to indicate current context
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_TIMER_HANDLE    Invalid timer handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null timer handle passed
+ * @retval E_RTOS_QUEUE_FULL              Timer command queue is full and
+ *                                        cannot accept new requests
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error writing data to the output parameter
+ */
+static inline rtosError
+rtosTimerStopFromISR(rtosTimerHandle xTimer,
+                     rtosBool *pxHigherPriorityTaskWoken)
+{
+    return xTimerStopFromISR(xTimer, pxHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Change timer period from ISR
+ *
+ * This function is a wrapper for xTimerChangePeriodFromISR() in SafeRTOS.
+ * It sets value at pxHigherPriorityTaskWoken if calling this function unblocks
+ * the timer service whose priority is equal to/higher than the current task
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xTimer                     Timer handle
+ * @param[in] xNewPeriodInTicks          New timer period in ticks. Should be
+ *                                       greater than 0.
+ * @param[out] pxHigherPriorityTaskWoken Pointer to rtosBool variable
+ *                                       to indicate current context
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_TIMER_HANDLE    Invalid timer handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null timer handle passed
+ * @retval E_RTOS_QUEUE_FULL              Timer command queue is full and
+ *                                        cannot accept new requests
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error writing data to the output parameter
+ */
+static inline rtosError
+rtosTimerChangePeriodFromISR(rtosTimerHandle xTimer,
+                             rtosTick xNewPeriodInTicks,
+                             rtosBool *pxHigherPriorityTaskWoken)
+{
+    return xTimerChangePeriodFromISR(xTimer, xNewPeriodInTicks,
+                                     pxHigherPriorityTaskWoken);
+}
+
+/**
+ * @brief Check if timer is active
+ *
+ * This function is a wrapper for xTimerIsTimerActive() in SafeRTOS.
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xTimer Timer handle
+ *
+ * @retval rtosTRUE                    if timer is active or exists in the
+ *                                     overflow timer list
+ * @retval rtosFALSE                   Timer not present in the active timer
+ *                                     list
+ * @retval E_RTOS_INVALID_TIMER_HANDLE Invalid timer handle
+ */
+static inline rtosError
+rtosTimerIsTimerActive(rtosTimerHandle xTimer)
+{
+    return xTimerIsTimerActive(xTimer);
+}
+
+/**
+ * @brief Get timer ID
+ *
+ * This function is a wrapper for xTimerGetTimerID() in SafeRTOS.
+ * It updates value at pxTimerID with ID of the requested timer
+ * configured by the host application while creating it.
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in]  xTimer    Timer handle
+ * @param[out] pxTimerID Pointer to timer ID
+ *
+ * @retval rtosPASS                       for valid timers
+ * @retval E_RTOS_INVALID_TIMER_HANDLE    Invalid timer handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null pointer referring to timer ID
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error writing data to the output parameter
+ */
+static inline rtosError
+rtosTimerGetTimerID(rtosTimerHandle xTimer, rtosTimerIDType *pxTimerID)
+{
+    return xTimerGetTimerID(xTimer, pxTimerID);
+}
+
+/**
+ * @brief Get timer local storage object
+ *
+ * This function is a wrapper for xTimerTLSObjectGet() in SafeRTOS.
+ * On success, this function returns pointer to timer local storage
+ * object defined in timer init parameters.
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Called from a timer callback function
+ *
+ * @param[in] xTimer Timer handle
+ *
+ * @retval NULL     for failure
+ * @retval TimerLSO Pointer to timer local storage object on success
+ */
+static inline rtosTimerLocalStorageObject
+rtosTimerTLSObjectGet(rtosTimerHandle xTimer)
+{
+    return pvTimerTLSObjectGet(xTimer);
+}
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-values.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-values.h
new file mode 100644
index 0000000..3ab8b2a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/osa-values.h
@@ -0,0 +1,190 @@
+/* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_VALUES_H
+#define OSA__OSA_VALUES_H
+#define FSP__OSA__OSA_VALUES_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // for rtosMutexHandle, FSP__OSPL__RTOS_PORT_H
+#include <eventgroups.h>                // for evgrpCLEAR_EVENTS_ON_EXIT_BIT, evgrpWAIT_FO...
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+/**
+ * @brief Mapping of SafeRTOS values to rtos value space
+ *
+ * @macro-title RTOS boolean values published by OSA layer
+ *
+ * @rtosTRUE  Defines true state of a boolean variable
+ * @rtosFALSE Defines false state of a boolean variable
+ * @rtosPASS  Defines return value indicating success
+ * @rtosFAIL  Defines return value indicating failure
+ */
+#define rtosTRUE                                ((rtosBool)pdTRUE)
+#define rtosFALSE                               ((rtosBool)pdFALSE)
+#define rtosPASS                                pdPASS
+#define rtosFAIL                                pdFAIL
+
+/**
+ * @brief Mapping of SafeRTOS kernel version values to rtos value space
+ *
+ * @macro-title Kernel version values published by OSA layer.
+ *
+ * @rtosKERNEL_MAJOR_VERSION Defines kernel major version number
+ * @rtosKERNEL_MINOR_VERSION Defines kernel minor version number
+ */
+#define rtosKERNEL_MAJOR_VERSION                pdKERNEL_MAJOR_VERSION
+#define rtosKERNEL_MINOR_VERSION                pdKERNEL_MINOR_VERSION
+
+/**
+ * @brief Mapping of SafeRTOS event group values to rtos value space
+ *
+ * @macro-title Event group values published by OSA layer
+ *
+ * @rtosEVENTGRP_CLEAR_EVENTS_ON_EXIT Defines bit-mask mapped to eventgroup
+ *                                    control flag set to clear event group
+ *                                    bits on exit
+ * @rtosEVENTGRP_WAIT_FOR_ALL_BITS    Defines bit-mask mapped to eventgroup
+ *                                    control flag, set to wait until all the
+ *                                    requested event group bits are set.
+ */
+#define rtosEVENTGRP_CLEAR_EVENTS_ON_EXIT       evgrpCLEAR_EVENTS_ON_EXIT_BIT
+#define rtosEVENTGRP_WAIT_FOR_ALL_BITS          evgrpWAIT_FOR_ALL_BITS
+
+/**
+ * @brief Mapping of SafeRTOS mutex values to rtos value space
+ *
+ * @macro-title Mutex state values published by OSA layer
+ *
+ * @rtosMUTEX_AVAILABLE Defines state of a mutex object indicating lock is
+ *                      available
+ * @rtosMUTEX_TAKEN     Defines state of a mutex object indicating lock is
+ *                      acquired
+ */
+#define rtosMUTEX_TAKEN                         mutexTAKEN
+#define rtosMUTEX_AVAILABLE                     mutexAVAILABLE
+
+/**
+ * @brief Mapping of SafeRTOS semaphore values to rtos value space
+ *
+ * @macro-title Semaphore value published by OSA layer
+ *
+ * @rtosSEMA_GIVE_NOBLOCK Defines macro to be used for setting semaphore block
+ *                        time as 0.
+ */
+#define rtosSEMA_GIVE_NOBLOCK                   semSEM_GIVE_BLOCK_TIME
+
+/**
+ * @brief Mapping of SafeRTOS task values to rtos value space
+ *
+ * @macro-title Task notification values published by OSA layer
+ *
+ * @rtosNotification_NO_ACTION                   Sending task shall use this
+ *                                               macro if no update is needed
+ *                                               to the receiving task
+ *                                               notification value
+ * @rtosNotification_SET_BITS                    Sending task shall use this
+ *                                               macro to update notification
+ *                                               value of receiving task by
+ *                                               ORing it with the sent value
+ *                                               of the receiving task
+ * @rtosNotification_INCREMENT                   Sending task shall use this
+ *                                               macro to increment notification
+ *                                               value of the receiving task
+ * @rtosNotification_SET_VALUE_WITH_OVERWRITE    Sending task shall use this
+ *                                               macro to set notification value
+ *                                               of the receiving task with
+ *                                               overwrite even if the previous
+ *                                               notification is pending
+ * @rtosNotification_SET_VALUE_WITHOUT_OVERWRITE Sending task shall use this
+ *                                               macro to set notification value
+ *                                               of the receiving task only if
+ *                                               there is no previous
+ *                                               notification pending
+ * @rtosNotification_NOT_WAITING                 Defines state of a task
+ *                                               indicating it's not waiting
+ *                                               for any notification
+ * @rtosNotification_WAITING                     Defines state of a task
+ *                                               indicating it's waiting
+ *                                               for a notification
+ * @rtosNotification_NOTIFIED                    Defines state of a task
+ *                                               indicating it has sent the
+ *                                               notification
+ * @rtosIDLE_PRIORITY                            Defines priority of an idle task
+ */
+#define rtosNotification_NO_ACTION                      taskNOTIFICATION_NO_ACTION
+#define rtosNotification_SET_BITS                       taskNOTIFICATION_SET_BITS
+#define rtosNotification_INCREMENT                      taskNOTIFICATION_INCREMENT
+#define rtosNotification_SET_VALUE_WITH_OVERWRITE       taskNOTIFICATION_SET_VALUE_WITH_OVERWRITE
+#define rtosNotification_SET_VALUE_WITHOUT_OVERWRITE    taskNOTIFICATION_SET_VALUE_WITHOUT_OVERWRITE
+#define rtosNotification_NOT_WAITING                    taskNOTIFICATION_NOT_WAITING
+#define rtosNotification_WAITING                        taskNOTIFICATION_WAITING
+#define rtosNotification_NOTIFIED                       taskNOTIFICATION_NOTIFIED
+#define rtosIDLE_PRIORITY                               taskIDLE_PRIORITY
+
+/**
+ * @brief Mapping of SafeRTOS event poll values to rtos value space
+ *
+ * @macro-title Event poll values published by OSA layer
+ *
+ * @rtoseventpollQUEUE_MESSAGE_WAITING      Defines event for a queue object
+ *                                          indicating the queue contains at
+ *                                          least one message waiting to be
+ *                                          received.
+ * @rtoseventpollQUEUE_SPACE_AVAILABLE      Defines event for a queue object
+ *                                          indicating the queue has space for
+ *                                          at least one message to be sent
+ * @rtoseventpollSEMAPHORE_AVAILABLE        Defines event for a semaphore object
+ *                                          indicating it is available
+ * @rtoseventpollMUTEX_AVAILABLE            Defines event for a mutex object
+ *                                          indicating it is available
+ * @rtoseventpollTASK_NOTIFICATION_RECEIVED Defines event for a task indicating
+ *                                          it has received a notification
+ * @rtoseventpollEVENT_GROUP_BITS_SET       Defines event for an eventgroup
+ *                                          object indicating requested
+ *                                          eventgroup bits are set.
+ */
+#define rtosEventPollQUEUE_MESSAGE_WAITING         eventpollQUEUE_MESSAGE_WAITING
+#define rtosEventPollQUEUE_SPACE_AVAILABLE         eventpollQUEUE_SPACE_AVAILABLE
+#define rtosEventPollSEMAPHORE_AVAILABLE           eventpollSEMAPHORE_AVAILABLE
+#define rtosEventPollMUTEX_AVAILABLE               eventpollMUTEX_AVAILABLE
+#define rtosEventPollTASK_NOTIFICATION_RECEIVED    eventpollTASK_NOTIFICATION_RECEIVED
+#define rtosEventPollEVENT_GROUP_BITS_SET          eventpollEVENT_GROUP_BITS_SET
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/sections-osa.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/sections-osa.h
new file mode 100644
index 0000000..958656a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv8/osa/sections-osa.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef OSA__SECTIONS_OSA_H
+#define OSA__SECTIONS_OSA_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_OSA_DATA           SECTION_BUILDER(osa,                    data)
+#define SECTION_NAME_OSA_RODATA         SECTION_BUILDER(osa,                    rodata)
+#define SECTION_NAME_OSA_TEXT           SECTION_BUILDER(osa,                    text)
+#define SECTION_NAME_OSA_CREATE_TEXT    SECTION_BUILDER(create.osa,             text)
+#define SECTION_NAME_OSA_INIT_DATA      SECTION_BUILDER(init.osa,               data)
+#define SECTION_NAME_OSA_INIT_TEXT      SECTION_BUILDER(init.osa,               text)
+
+#define SECTION_STR_OSA_TEXT            STR(SECTION_NAME_OSA_TEXT)
+#define SECTION_STR_OSA_RODATA          STR(SECTION_NAME_OSA_RODATA)
+#define SECTION_STR_OSA_DATA            STR(SECTION_NAME_OSA_DATA)
+#define SECTION_STR_OSA_INIT_TEXT       STR(SECTION_NAME_OSA_INIT_TEXT)
+#define SECTION_STR_OSA_INIT_DATA       STR(SECTION_NAME_OSA_INIT_DATA)
+#define SECTION_STR_OSA_CREATE_TEXT     STR(SECTION_NAME_OSA_CREATE_TEXT)
+
+#define SECTION_OSA_TEXT                SECTION(SECTION_STR_OSA_TEXT)
+#define SECTION_OSA_RODATA              SECTION(SECTION_STR_OSA_RODATA)
+#define SECTION_OSA_DATA                SECTION(SECTION_STR_OSA_DATA)
+#define SECTION_OSA_INIT_TEXT           SECTION(SECTION_STR_OSA_INIT_TEXT)
+#define SECTION_OSA_INIT_DATA           SECTION(SECTION_STR_OSA_INIT_DATA)
+#define SECTION_OSA_CREATE_TEXT         SECTION(SECTION_STR_OSA_CREATE_TEXT)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
+
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv9/arm/armv7/cortex-r5/ospl/rtos-port-asm.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/arm/armv7/cortex-r5/ospl/rtos-port-asm.h
new file mode 100644
index 0000000..8d22bb9
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/arm/armv7/cortex-r5/ospl/rtos-port-asm.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2021-2023 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef OSPL__RTOS_PORT_ASM_H
+#define OSPL__RTOS_PORT_ASM_H
+
+/* Compiler headers */
+#include <portIRQ.inc>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+#ifdef __ASSEMBLER__
+
+.macro rtosIRQ_ENTRY
+    safertosIRQ_ENTRY
+    push        { R4-R11 }
+.endm
+
+.macro rtosIRQ_EXIT
+    pop         { R4-R11 }
+    safertosIRQ_EXIT
+.endm
+
+#endif /* #ifdef __ASSEMBLER__ */
+
+#endif /* #ifndef OSPL__RTOS_PORT_ASM_H */
+
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv9/arm/armv7/cortex-r5/ospl/rtos-port.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/arm/armv7/cortex-r5/ospl/rtos-port.h
new file mode 100644
index 0000000..649aea3
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/arm/armv7/cortex-r5/ospl/rtos-port.h
@@ -0,0 +1,310 @@
+/* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSPL__RTOS_PORT_H
+#define OSPL__RTOS_PORT_H
+#define FSP__OSPL__RTOS_PORT_H                          1
+
+/* Compiler headers */
+#include <stdint.h>                        // for uint32_t, int32_t, int16_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <SafeRTOSConfig.h>                // for configTICK_RATE_HZ, config...
+                                           // IWYU pragma: no_include "portmacro.h"
+#include <SafeRTOS_API.h>                  // for safertosapiQUEUE_OVERHEAD_BYTES
+#include <eventGroupsAPI.h>                // for eventBitsType, eventGroupType
+#include <evtmplxAPI.h>                    // for evtMplxObjectEventsType
+#include <cpu/armv7-mpu-safertos.h>        // for mpuParameters_t
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__CPU__ARMV7_MPU_SAFERTOS_H, "Header file missing or invalid.")
+
+/*
+ * Port specific types and data structures needed by nvosRTOS.h
+ *
+ * This file should not be included directly from any other file.
+ */
+
+/**
+ * @brief Make sure that the sizes of types defined by SafeRTOS are what they
+ * are expected to be.
+ */
+CT_ASSERT(sizeof(int16_t) == sizeof(portInt16Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(uint8_t) == sizeof(portUInt8Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(int8_t) == sizeof(portInt8Type), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(char) == sizeof(portCharType), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(uint32_t) == sizeof(portStackType), "ASSERT due to data type mismatch.")
+CT_ASSERT(sizeof(uint32_t) == sizeof(portTickType), "ASSERT due to data type mismatch.")
+#endif
+
+/** @defgroup RTOS_TYPES RTOS data types
+ * @{
+ */
+/**
+ * @brief Provide wrapper type definitions for RTOS values to avoid exposing the
+ * SafeRTOS types directly.
+ */
+typedef portBaseType            rtosError;
+typedef void                    *rtosTaskHandle;
+typedef void                    *rtosEventGroupHandle;
+typedef eventGroupType          rtosEventGroup;
+typedef void                    *rtosQueueHandle;
+typedef void                    *rtosTimerHandle;
+typedef void                    *rtosTimerLocalStorageObject;
+typedef portUnsignedBaseType    rtosUCount;
+typedef portTickType            rtosTick;
+typedef portBaseType            rtosBool;
+typedef portBaseType            rtosTimerIDType;
+typedef void                    *rtosMutexHandle;
+typedef void                    *rtosSemaphoreHandle;
+typedef void                    *rtosEventPollHandle;
+typedef portUnsignedBaseType    rtosTaskNotifyBits;
+typedef portUnsignedBaseType    rtosEventPollValue;
+typedef portBaseType            rtosTaskNotifyAction;
+typedef portUnsignedBaseType    rtosTaskNotifyValue;
+typedef portUnsignedBaseType    rtosPriority;
+typedef portUnsignedBaseType    rtosInterruptState;
+typedef portUnsignedBaseType    rtosMutexState;
+typedef eventBitsType           rtosEventBits;
+typedef portUInt32Type          rtosHz;
+typedef portUnsignedBaseType    rtosPrivilegeLevel;
+typedef portUnsignedBaseType    rtosUInt32Type;
+/** @} */
+
+/**
+ * @defgroup RTOS_OBJECT_SIZE
+ * Sizes of objects that need to be statically allocated but
+ * whose contents are not visible to the application.
+ */
+/** @{ */
+/** Defines size in bytes needed to create a queue */
+#define rtosQUEUE_OVERHEAD_BYTES                   safertosapiQUEUE_OVERHEAD_BYTES
+/** Defines size in bytes needed to create a semaphore object */
+#define rtosSEMAPHORE_OVERHEAD_BYTES               safertosapiQUEUE_OVERHEAD_BYTES
+/** Defines size in bytes needed to create a mutex object */
+#define rtosMUTEX_OVERHEAD_BYTES                   safertosapiQUEUE_OVERHEAD_BYTES
+/** Defines size in bytes needed to create an event group object */
+#define rtosEVENT_GROUP_OVERHEAD_BYTES             sizeof(eventGroupType)
+/** Defines size in bytes needed for task control block */
+#define rtosTCB_OVERHEAD_BYTES                     sizeof(xTCB)
+/** Defines size in bytes needed for timer control block */
+#define rtosTIMER_CONTROL_BLOCK_OVERHEAD_BYTES     sizeof(timerControlBlockType)
+/** Defines size in bytes needed for timer instance parameters */
+#define rtosTIMER_INSTANCE_PARAMETER_OVERHEAD_BYTES \
+        sizeof(struct timerInstanceParameters)
+/** Defines size in bytes needed to create an event poll object */
+#define rtosEVENT_POLL_OVERHEAD_BYTES(uxMaximumRegisteredObjectEvents) \
+        evtmplxGET_REQUIRED_CREATE_BUFFER_SIZE(uxMaximumRegisteredObjectEvents)
+/** @} */
+
+/**
+ * @brief Provide wrapper definition for pointer to RTOS task function.
+ */
+typedef pdTASK_CODE             rtosTaskFunction;
+
+/**
+ * @brief Provide a wrapper data type to encapsulate MPU related information
+ */
+typedef mpuParameters_t rtosMPURegionConfig;
+
+/**
+ * @brief Provide wrapper definition for pointer to RTOS timer callback function
+ * which gets invoked when a timer expires.
+ */
+typedef void (*rtosTimerCallbackFunction)(void * pvParameters);
+
+/**
+ * @struct rtosTaskParameters
+ * @brief Structure with RTOS task parameters
+ * @{
+ */
+typedef struct {
+    /** Pointer to task entry function */
+    rtosTaskFunction    pvTaskCode;
+    /** Task descriptive name */
+    const char          *pcTaskName;
+    /** Pointer to task control block */
+    void                *pxTCB;
+    /** Pointer to task stack buffer */
+    void                *pcStackBuffer;
+    /** Size of task stack buffer in bytes. The minimum allowable size for the stack buffer is portdependent */
+    rtosUCount          uxStackDepthBytes;
+    /** Pointer to task parameters */
+    void                *pvParameters;
+    /** Priority of task. Valid range is [0 - (configMAX_PRIORITIES - 1]) */
+    rtosPriority        uxPriority;
+    /**  Pointer to user defined data associated with this task */
+    void                *pvObject;
+    /** Bool to indicate use of FPU */
+    rtosBool            xUsingFPU;
+    /** Task Privilege level */
+    rtosPrivilegeLevel  uxPrivilegeLevel;
+    /** Pointer to task MPU parameters */
+    rtosMPURegionConfig *pxMPUParameters;
+} rtosTaskParameters;
+/** @} */
+
+/**
+ * @struct rtosSchedParameters
+ * @brief Structure supplied to rtosTaskInitializeScheduler()
+ * @{
+ */
+typedef struct {
+    /** Speed of the system clock */
+    rtosHz              ulCPUClockHz;
+    /** Desired frequency of kernel tick */
+    rtosHz              ulTickRateHz;
+    /** Lower limit on number of bytes that should be left in the stack post context switch. Can be set greater than or equal to 0 */
+    rtosUCount          uxAdditionalStackCheckMarginBytes;
+    /** Pointer to the lowest address of task buffer to hold idle task*/
+#if defined(SAFERTOS_VARIANT_SVC) && (SAFERTOS_VARIANT_SVC == 1)
+    /** Base address for SVC stack */
+    void                *pcSVCStackBaseAddress;
+#endif
+    /** Pointer to the lowest address of task buffer to hold idle task */
+    void                *pcIdleTaskStackBuffer;
+    /** Number of bytes in the stack buffer to be kept for idle task. Should be greater than 0 */
+    rtosUCount          uxIdleTaskStackSizeBytes;
+    /** Bool variable to indicate use of FPU by idle task */
+    rtosBool            xIdleTaskUsingFPU;
+    /** Idle task privilege level [RTOS_SYSTEM_MODE, RTOS_USER_MODE] */
+    rtosPrivilegeLevel  uxIdleTaskPrivilegeLevel;
+    /** Pointer to idle task MPU parameter structure*/
+    rtosMPURegionConfig *pxIdleTaskMPUParameters;
+    /** Idle task timer local storage object */
+    void                *pvIdleTaskTLSObject;
+    /** Priority of timer service. Valid range is [0 - (configMAX_PRIORITIES - 1)]*/
+    rtosPriority        uxTimerTaskPriority;
+    /** Number of bytes in stack buffer to be kept for timer task. Should be greater than 0 */
+    rtosUCount          uxTimerTaskStackSize;
+    /** Pointer to the timer task stack buffer */
+    void                *pcTimerTaskStackBuffer;
+    /** Timer command queue length. Should be greater than 0 */
+    rtosUCount          uxTimerCommandQueueLength;
+    /** Timer command queue buffer size. Size of the buffer should be at least enough to accommodate the entire command queue */
+    rtosUCount          uxTimerCommandQueueBufferSize;
+    /** Pointer to timer command queue buffer */
+    void                *pcTimerCommandQueueBuffer;
+    /** Pointer to timer task MPU parameters */
+    rtosMPURegionConfig *pxTimerTaskMPUParameters;
+} rtosSchedParameters;
+/** @} */
+
+/**
+ * @struct rtosTimerInitParametersType
+ * @brief Structure supplied to rtosTimerCreate()
+ * @{
+ */
+typedef struct {
+    /** Descriptive name of the timer */
+    const char                *pcTimerName;
+    /** Timer period in ticks. Should be greater than 0 */
+    rtosTick                  xTimerPeriodInTicks;
+    /** Bool variable to indicate if timer is periodic */
+    rtosBool                  xIsPeriodic;
+    /** Timer ID */
+    rtosTimerIDType           xTimerID;
+    /** Pointer to timer control block */
+    void                      *pxNewTimer;
+    /** Timer callback function */
+    rtosTimerCallbackFunction pxCallbackFunction;
+    /** Timer instance to which the timer belongs */
+    void                      *pxTimerInstance;
+    /** Pointer to user defined data associated with this timer */
+    void                      *pvObject;
+    /** Task handle to notify about timer expiry */
+    rtosTaskHandle            xTaskToNotify;
+} rtosTimerInitParametersType;
+/** @} */
+
+/**
+ * @brief Wrapper structure for RTOS object-events
+ */
+#define rtosEventPollObjectEventsType evtMplxObjectEventsType 
+
+/**
+ * @defgroup RTOS_ARCH_VALUES Provide wrapper definitions for general architecture specific values
+ * @{
+ */
+/** Defines maximum delay supported by rtos */
+#define rtosMAX_DELAY                           safertosapiMAX_DELAY
+/** Defines maximum list items supported by rtos */
+#define rtosMAX_LIST_ITEM_VALUE                 portMAX_LIST_ITEM_VALUE
+/** Defines alignment value set for queue buffer */
+#define rtosWORD_ALIGNMENT                      safertosapiWORD_ALIGNMENT
+/** Defines alignment mask corresponding to alignment value set for queue buffer */
+#define rtosWORD_ALIGNMENT_MASK                 portWORD_ALIGNMENT_MASK
+/** Defines alignment value set for stack buffer */
+#define rtosSTACK_ALIGNMENT                     safertosapiSTACK_ALIGNMENT
+/** Defines alignment mask corresponding to alignment value set for stack buffer */
+#define rtosSTACK_ALIGNMENT_MASK                portSTACK_ALIGNMENT_MASK
+/** Defines context size in bytes without FPU */
+#define rtosCONTEXT_SIZE_NO_FPU                 portCONTEXT_SIZE_BYTES_NO_FPU
+/** Defines context size in bytes with FPU in use */
+#define rtosCONTEXT_SIZE_WITH_FPU               portCONTEXT_SIZE_BYTES_WITH_FPU
+/** Defines state value indicating stack is in use */
+#define rtosSTACK_IN_USE                        portSTACK_IN_USE
+/** Defines state value indicating stack is not in use */
+#define rtosSTACK_NOT_IN_USE                    portSTACK_NOT_IN_USE
+/** Defines state value indicating stack is not in use */
+#define rtosTICK_COUNT_BITS                     portTICK_COUNT_NUM_BITS
+/** Defines frequency of the underlying RTOS scheduler tick */
+#define rtosTICK_RATE_HZ                        configTICK_RATE_HZ
+/** Defines number of ticks per millisecond */
+#define rtosTICK_RATE_MS                        configTICK_RATE_MS
+/** @} */
+extern portUInt32Type xHookGetRTSCounter(void);
+
+/**
+ * @defgroup RTOS_OP_MODES Macro definitions for ARM state values.
+ * @}
+ */
+/** Defines value indicating ARM system mode operation */
+#define RTOS_SYSTEM_MODE                safertosapiPRIVILEGED_TASK
+/** Defines value indicating ARM system mode operation */
+#define RTOS_USER_MODE                  safertosapiUNPRIVILEGED_TASK
+#if defined(safertosapiSVC_API_PORT_RC_VERSION)
+/** Use SVC variant of SafeRTOS */
+#define RTOS_PORT_RC_VERSION            safertosapiSVC_API_PORT_RC_VERSION
+#endif
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-errors.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-errors.h
new file mode 100644
index 0000000..aeeba58
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-errors.h
@@ -0,0 +1,205 @@
+/* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_ERRORS_H
+#define OSA__OSA_ERRORS_H
+#define FSP__OSA__OSA_ERRORS_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>  // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>  // for FSP__BASE__MODULE_ID_H, MODULE_ERROR_MODULE
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>  // for errSUPPLIED_BUFFER_TOO_SMALL, errBAD_OR_...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+
+/*
+ * Ensure that the native SafeRTOS error code map can map into the global
+ * error code space with no other manipulation.
+ */
+CT_ASSERT(MODULE_ERROR_MODULE(errSUPPLIED_BUFFER_TOO_SMALL) == MODULE_ID_RTOS, "SafeRTOS error codes collide with FSP error codes.")
+/**
+ * @defgroup RTOS_ERROR RTOS error codes
+ * @{
+ */
+/** Error value returned if supplied buffer is too small to create a kernel object */
+#define E_RTOS_SUPPLIED_BUFFER_TOO_SMALL              errSUPPLIED_BUFFER_TOO_SMALL
+/** Error value returned for invalid task priority */
+#define E_RTOS_INVALID_PRIORITY                       errINVALID_PRIORITY
+/** Error value returned if queue is full and cannot accept a new request */
+#define E_RTOS_QUEUE_FULL                             errQUEUE_FULL
+/** Error returned for invalid byte alignment */
+#define E_RTOS_INVALID_ALIGNMENT                      errINVALID_ALIGNMENT
+/** Error value returned if null is supplied as an input parameter*/
+#define E_RTOS_NULL_PARAMETER_SUPPLIED                errNULL_PARAMETER_SUPPLIED
+/** Error value returned if requested queue length is invalid */
+#define E_RTOS_INVALID_QUEUE_LENGTH                   errINVALID_QUEUE_LENGTH
+/** Error value returned for invalid input task code pointer */
+#define E_RTOS_INVALID_TASK_CODE_POINTER              errINVALID_TASK_CODE_POINTER
+/** Error value returned if request could not be processed because the scheduler was suspended */
+#define E_RTOS_SCHEDULER_IS_SUSPENDED                 errSCHEDULER_IS_SUSPENDED
+/** Error value returned for invalid input task handle */
+#define E_RTOS_INVALID_TASK_HANDLE                    errINVALID_TASK_HANDLE
+/** Error value returned if task did not yield for a yield request */
+#define E_RTOS_DID_NOT_YIELD                          errDID_NOT_YIELD
+/** Error value returned if request to suspend a task could not be processed because the task was already suspended */
+#define E_RTOS_TASK_ALREADY_SUSPENDED                 errTASK_ALREADY_SUSPENDED
+/** Error value returned if request to resume a task could not be processed because the task was not suspended */
+#define E_RTOS_TASK_WAS_NOT_SUSPENDED                 errTASK_WAS_NOT_SUSPENDED
+/** Error value returned if request to start a scheduler could not be processed as no tasks are created */
+#define E_RTOS_NO_TASKS_CREATED                       errNO_TASKS_CREATED
+/** Error value returned if request to start a scheduler could not be processed because scheduler was already running */
+#define E_RTOS_SCHEDULER_ALREADY_RUNNING              errSCHEDULER_ALREADY_RUNNING
+/** Error value returned for invalid input queue handle*/
+#define E_RTOS_INVALID_QUEUE_HANDLE                   errINVALID_QUEUE_HANDLE
+/** Error value returned for invalid input semaphore handle*/
+#define E_RTOS_INVALID_SEMAPHORE_HANDLE               errINVALID_SEMAPHORE_HANDLE
+/** Error value returned for invalid input mutex handle*/
+#define E_RTOS_INVALID_MUTEX_HANDLE                   errINVALID_MUTEX_HANDLE
+/** Error value returned for erroneous request to unblock a task */
+#define E_RTOS_ERRONEOUS_UNBLOCK                      errERRONEOUS_UNBLOCK
+/** Error value returned if request to pick a task from the queue could not be processed because queue was empty */
+#define E_RTOS_QUEUE_EMPTY                            errQUEUE_EMPTY
+/** Error value returned if request to acquire a semaphore could not be processed because semaphore was already taken*/
+#define E_RTOS_SEMAPHORE_ALREADY_TAKEN                errSEMAPHORE_ALREADY_TAKEN
+/** Error value returned if request to release a semaphore could not be processed because semaphore was already given*/
+#define E_RTOS_SEMAPHORE_ALREADY_GIVEN                errSEMAPHORE_ALREADY_GIVEN
+/** Error value returned if request to acquire a mutex could not be processed because it was already taken*/
+#define E_RTOS_MUTEX_ALREADY_TAKEN                    errMUTEX_ALREADY_TAKEN
+/** Error value returned for invalid input tick value */
+#define E_RTOS_INVALID_TICK_VALUE                     errINVALID_TICK_VALUE
+/** Error value returned for invalid task selection */
+#define E_RTOS_INVALID_TASK_SELECTED                  errINVALID_TASK_SELECTED
+/** Error value returned when task stack overflows */
+#define E_RTOS_TASK_STACK_OVERFLOW                    errTASK_STACK_OVERFLOW
+/** Error value returned if request to resume scheduler could not be processed because scheduler was already running */
+#define E_RTOS_SCHEDULER_WAS_NOT_SUSPENDED            errSCHEDULER_WAS_NOT_SUSPENDED
+/** Error value returned for invalid input buffer size */
+#define E_RTOS_INVALID_BUFFER_SIZE                    errINVALID_BUFFER_SIZE
+/** Error value returned for invalid tick rate*/
+#define E_RTOS_BAD_OR_NO_TICK_RATE_CONFIGURATION      errBAD_OR_NO_TICK_RATE_CONFIGURATION
+/** Error value returned for error in the vector table */
+#define E_RTOS_ERROR_IN_VECTOR_TABLE                  errERROR_IN_VECTOR_TABLE
+/** Error value returned for invalid MPU configuration */
+#define E_RTOS_INVALID_MPU_REGION_CONFIGURATION       errINVALID_MPU_REGION_CONFIGURATION
+/** Error value returned for invalid MMU configuration */
+#define E_RTOS_INVALID_MMU_REGION_CONFIGURATION       errINVALID_MMU_REGION_CONFIGURATION
+/** Error value returned if task stack supplied to initialize a scheduler is already in use */
+#define E_RTOS_TASK_STACK_ALREADY_IN_USE              errTASK_STACK_ALREADY_IN_USE
+/** Error value returned if MPU does not exist in the device*/
+#define E_RTOS_NO_MPU_IN_DEVICE                       errNO_MPU_IN_DEVICE
+/** Error value returned if a task is expected to run in privileged mode but currently running in unprivileged mode */
+#define E_RTOS_EXECUTING_IN_UNPRIVILEGED_MODE         errEXECUTING_IN_UNPRIVILEGED_MODE
+/** Error value returned on detection of RTS calculation error */
+#define E_RTOS_RTS_CALCULATION_ERROR                  errRTS_CALCULATION_ERROR
+/** Error value returned for invalid percentage handle */
+#define E_RTOS_INVALID_PERCENTAGE_HANDLE              errINVALID_PERCENTAGE_HANDLE
+/** Error value returned for invalid initial semaphore count */
+#define E_RTOS_INVALID_INITIAL_SEMAPHORE_COUNT        errINVALID_INITIAL_SEMAPHORE_COUNT
+/** Error value returned for ROM integrity check failures*/
+#define E_RTOS_ROM_INTEGRITY_CHECK_FAILED             errROM_INTEGRITY_CHECK_FAILED
+/** Error value returned if request is already in progress*/
+#define E_RTOS_IN_PROGRESS                            errIN_PROGRESS
+/** Error value returned for invalid input parameters */
+#define E_RTOS_INVALID_PARAMETERS                     errINVALID_PARAMETERS
+/** Error value returned for spurious interrupt */
+#define E_RTOS_SPURIOUS_INTERRUPT                     errSPURIOUS_INTERRUPT
+/** Error value returned for spurious fast interrupt */
+#define E_RTOS_SPURIOUS_FAST_INTERRUPT                errSPURIOUS_FAST_INTERRUPT
+/** Error value returned for RAM integrity check failures */
+#define E_RTOS_RAM_INTEGRITY_CHECK_FAILED             errRAM_INTEGRITY_CHECK_FAILED
+/** Error value returned for invalid input timer handle */
+#define E_RTOS_INVALID_TIMER_HANDLE                   errINVALID_TIMER_HANDLE
+/** Error value returned for invalid timer task instance */
+#define E_RTOS_INVALID_TIMER_TASK_INSTANCE            errINVALID_TIMER_TASK_INSTANCE
+/** Error value returned if request to create a new timer could not be processed because the supplied timer handle was already in use */
+#define E_RTOS_TIMER_ALREADY_IN_USE                   errTIMER_ALREADY_IN_USE
+/** Error value returned if notification is not received until timeout */
+#define E_RTOS_NOTIFICATION_NOT_RECEIVED              errNOTIFICATION_NOT_RECEIVED
+/** Error value returned if a new request to wait for notification arises while the task is still waiting for notification */
+#define E_RTOS_NOTIFICATION_ALREADY_PENDING           errNOTIFICATION_ALREADY_PENDING
+/** Error value returned if the task is already part of the event list */
+#define E_RTOS_TASK_WAS_ALSO_ON_EVENT_LIST            errTASK_WAS_ALSO_ON_EVENT_LIST
+/** Error value returned if request to create a new queue could not be processed because input queue handle was already in use */
+#define E_RTOS_QUEUE_ALREADY_IN_USE                   errQUEUE_ALREADY_IN_USE
+/** Error value returned if request to create a new event group could not be processed because input event group handle was already in use */
+#define E_RTOS_EVENT_GROUP_ALREADY_IN_USE             errEVENT_GROUP_ALREADY_IN_USE
+/** Error value returned for invalid input event group handle*/
+#define E_RTOS_INVALID_EVENT_GROUP_HANDLE             errINVALID_EVENT_GROUP_HANDLE
+/** Error value returned if event group bits could not be set */
+#define E_RTOS_EVENT_GROUP_BITS_NOT_SET               errEVENT_GROUP_BITS_NOT_SET
+/** Error value returned if event group request could not be processed as referred object is deleted */
+#define E_RTOS_EVENT_GROUP_DELETED                    errEVENT_GROUP_DELETED
+/** Error value returned if mutex request could not be processed as mutex is not owned by the caller */
+#define E_RTOS_MUTEX_NOT_OWNED_BY_CALLER              errMUTEX_NOT_OWNED_BY_CALLER
+/** Error value returned if mutex got corrupted */
+#define E_RTOS_MUTEX_CORRUPTED                        errMUTEX_CORRUPTED
+/** Error value returned if next unblock time for the referred task expired */
+#define E_RTOS_NEXT_UNBLOCK_TIME_EXPIRED              errNEXT_UNBLOCK_TIME_EXPIRED
+/** Error value returned if task got unblocked after next unblock time */
+#define E_RTOS_WOKEN_UP_AFTER_NEXT_UNBLOCK_TIME       errWOKEN_UP_AFTER_NEXT_UNBLOCK_TIME
+/**Error value returned if tickless mode is not supported */
+#define E_RTOS_TICKLESS_MODE_NOT_SUPPORTED            errTICKLESS_MODE_NOT_SUPPORTED
+/** Error value returned if request to create a new event poll object could not be processed as event poll object handle was already in use */
+#define E_RTOS_EVENT_POLL_OBJECT_ALREADY_IN_USE       errEVT_MPLX_OBJECT_ALREADY_IN_USE
+/** Error value returned if the request could not be processed because scheduler is not running */
+#define E_RTOS_SCHEDULER_IS_NOT_RUNNING               errSCHEDULER_IS_NOT_RUNNING
+/** Error value returned if no more target objects can be registered with the referred event poll object */
+#define E_RTOS_EVENT_POLL_OBJECT_EVENTS_LIMIT_REACHED errEVT_MPLX_OBJECT_EVENTS_LIMIT_REACHED
+/** Error value returned for invalid event poll operation */
+#define E_RTOS_INVALID_EVENT_POLL_OPERATION           errINVALID_EVT_MPLX_OPERATION
+/** Error value returned for invalid event poll handle */
+#define E_RTOS_INVALID_EVENT_POLL_HANDLE              errINVALID_EVT_MPLX_HANDLE
+/** Error value returned for invalid event poll events for the target object */
+#define E_RTOS_INVALID_EVENT_POLL_EVENTS              errINVALID_EVT_MPLX_EVENTS
+/** Error returned if no event has occurred while waiting for events registered with event poll object */
+#define E_RTOS_EVENT_POLL_NO_EVENTS_OCCURRED          errEVT_MPLX_NO_EVENTS_OCCURRED
+/** Error value returned for invalid data range */
+#define E_RTOS_INVALID_DATA_RANGE                     errINVALID_DATA_RANGE
+/** Error value returned if no hook has been defined to setup ticks*/
+#define E_RTOS_NO_TICK_SETUP_HOOK_DEFINED             errNO_TICK_SETUP_HOOK_DEFINED
+/** @} */
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-event-group.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-event-group.h
new file mode 100644
index 0000000..3a8d179
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-event-group.h
@@ -0,0 +1,387 @@
+/* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_EVENT_GROUP_H
+#define OSA__OSA_EVENT_GROUP_H
+#define FSP__OSA__OSA_EVENT_GROUP_H                     1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>            // for UNUSED
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosEventGroupHandle, rtosEventBits, rto...
+#include <eventGroupsAPI.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "eventGroupsAPI.h"
+                                        // for xEventGroupClearBitsFromISR, xEvent...
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+#endif
+
+/**
+ * @brief Create an event group
+ *
+ * This function is a wrapper for xEventGroupCreate() in SafeRTOS to create an
+ * event group object.
+ * It updates pointer to the event group handle to point to the newly
+ * created event group
+ *
+ * @pre
+ * - A variable of type rtosEventGroup, r/w accessible to RTOS kernel at all
+ * times has been declared to handle the event group object
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in]  pxEventGroup       Pointer to the pre-declared event group variable
+ *                                of type rtosEventGroup
+ * @param[out] pxEventGroupHandle Pointer to the event group handle
+ *
+ * @retval rtosPASS on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null Input parameter
+ * @retval E_RTOS_EVENT_GROUP_ALREADY_IN_USE Event handle supplied is valid and
+ *                                           must be deleted before creating a
+ *                                           new group
+ * @retval E_RTOS_INVALID_DATA_RANGE         Error writing data to the output parameter
+ */
+static inline rtosError
+rtosEventGroupCreate(rtosEventGroup *pxEventGroup,
+                     rtosEventGroupHandle *pxEventGroupHandle)
+{
+    return xEventGroupCreate(pxEventGroup,
+                             pxEventGroupHandle);
+}
+
+/**
+ * @brief Delete an event group
+ *
+ * This function is a wrapper for xEventGroupDelete() in SafeRTOS to delete an
+ * event group object.
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from a non-interrupt context
+ *
+ * - Scheduler has been started.
+ *
+ * @param[in] xHandle Event group handle
+ *
+ * @retval rtosPASS                          on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null input parameter
+ * @retval E_RTOS_INVALID_EVENT_GROUP_HANDLE Invalid event group handle
+ */
+static inline rtosError
+rtosEventGroupDelete(rtosEventGroupHandle xHandle)
+{
+    return xEventGroupDelete(xHandle);
+}
+
+/**
+ * @brief Get event group bits.
+ *
+ * This function is a wrapper for xEventGroupGetBits() in SafeRTOS to
+ * read the status of event group bits.
+ * It updates the pointer to event group bits with latest bitmask of
+ * set fields in the event group.
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xHandle        Event group handle
+ * @param[in] pxEventBitsSet Pointer to event group bits
+ *
+ * @retval rtosPASS                          on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null input parameter
+ * @retval E_RTOS_INVALID_EVENT_GROUP_HANDLE Invalid event group handle
+ * @retval E_RTOS_INVALID_DATA_RANGE         Error writing data to the output parameter
+ */
+static inline rtosError
+rtosEventGroupGetBits(rtosEventGroupHandle xHandle,
+                      rtosEventBits *pxEventBitsSet)
+{
+    return xEventGroupGetBits(xHandle,
+                              pxEventBitsSet);
+}
+
+/**
+ * @brief Get event group bits from ISR.
+ *
+ * This function is a wrapper for xEventGroupGetBitsFromISR() in SafeRTOS to
+ * read the status of event group bits from an ISR
+ * It updates the pointer to event group bits with latest bitmask of set fields
+ * within the event group in an ISR context.
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xHandle        Event group handle
+ * @param[in] pxEventBitsSet Pointer to event group bits
+ *
+ * @retval rtosPASS                          on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null input parameter
+ * @retval E_RTOS_INVALID_EVENT_GROUP_HANDLE Invalid event group handle
+ * @retval E_RTOS_INVALID_DATA_RANGE         Error writing data to the output parameter
+ */
+static inline rtosError
+rtosEventGroupGetBitsFromISR(rtosEventGroupHandle xHandle,
+                             rtosEventBits *pxEventBitsSet)
+{
+    return xEventGroupGetBitsFromISR(xHandle,
+                                     pxEventBitsSet);
+}
+
+/**
+ * Set event group bits
+ *
+ * This function is a wrapper for xEventGroupSetBits() in SafeRTOS to set one
+ * or more bits to '1' in an event group
+ * Sets required fields within the event group based on bitmask sent as an
+ * argument.
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xHandle    Event group handle
+ * @param[in] xBitsToSet Bit mask to set required fields in the event group
+ *                       Size of rtosEventBits type is platform dependent.
+ *                       For ARM Cortex-R5, it is 32-bits. Since most
+ *                       significant byte is used for control purposes, valid
+ *                       bitmask range is 0 - 23 bits.
+ *
+ * @retval rtosPASS                          on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null input parameter
+ * @retval E_RTOS_INVALID_EVENT_GROUP_HANDLE Invalid event group handle
+ * @retval E_RTOS_INVALID_PARAMETERS         Invalid parameters
+ */
+static inline rtosError
+rtosEventGroupSetBits(rtosEventGroupHandle xHandle,
+                      const rtosEventBits xBitsToSet)
+{
+    return xEventGroupSetBits(xHandle,
+                              xBitsToSet);
+}
+
+/**
+ * Set event group bits from ISR
+ *
+ * This function is a wrapper for xEventGroupSetBitsFromISR() in SafeRTOS to
+ * set one or more event group bits to '1' in an interrupt-context.
+ * Sets required fields within the event group based on bitmask sent as an
+ * argument.
+ * It sets the value at pbHigherPriorityTaskWoken if calling this function
+ * unblocks a task of priority higher than currently running task indicating
+ * that a context switch is needed before exiting the ISR
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xHandle                    Event group handle
+ * @param[in] xBitsToSet                 Bitmask to set required fields in the
+ *                                       event group. Valid bitmask range for
+ *                                       ARM Cortex-R5 processor is 0 - 23 bits.
+ * @param[out] pbHigherPriorityTaskWoken Pointer to rtosbool variable
+ *
+ * @retval rtosPASS                          on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null input parameter
+ * @retval E_RTOS_INVALID_EVENT_GROUP_HANDLE Invalid event group handle
+ * @retval E_RTOS_INVALID_PARAMETERS         Invalid parameters
+ * @retval E_RTOS_QUEUE_FULL                 Queue associated with event group
+ *                                           object is full and cannot accept
+ *                                           incoming event group request
+ * @retval E_RTOS_INVALID_DATA_RANGE         Error while copying data to the output
+ *                                           parameter
+ */
+static inline rtosError
+rtosEventGroupSetBitsFromISR(rtosEventGroupHandle xHandle,
+                             const rtosEventBits xBitsToSet,
+                             rtosBool *pbHigherPriorityTaskWoken)
+{
+    UNUSED(pbHigherPriorityTaskWoken);
+    return xEventGroupSetBitsFromISR(xHandle,
+                                     xBitsToSet);
+}
+
+/**
+ * @brief Clear required event group bits
+ *
+ * This function is a wrapper for xEventGroupClearBits() in SafeRTOS to clear
+ * one or more bits in an event group
+ * Clears required fields within the event group based on bitmask sent as an
+ * argument.
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xHandle      Event group handle
+ * @param[in] xBitsToClear Bitmask to clear required fields.
+ *                         Valid bit mask range for ARM Cortex-R5 processor is
+ *                         0 - 23 bits.
+ *
+ * @retval rtosPASS                          on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null input parameter
+ * @retval E_RTOS_INVALID_EVENT_GROUP_HANDLE Invalid event group handle
+ * @retval E_RTOS_INVALID_PARAMETERS         Invalid parameters
+ *
+ */
+static inline rtosError
+rtosEventGroupClearBits(rtosEventGroupHandle xHandle,
+                        const rtosEventBits xBitsToClear)
+{
+    return xEventGroupClearBits(xHandle,
+                                xBitsToClear);
+}
+
+/**
+ * @brief Clear required event group bits from ISR
+ *
+ * This function is a wrapper for xEventGroupClearBitsFromISR() in SafeRTOS to
+ * clear one or more event group bits in an interrupt context.
+ * Clears required fields within the event group based on bitmask sent as an
+ * argument.
+ * It sets value at pbHigherPriorityTaskWoken if calling this function unblocks
+ * a higher priority task than current task indicating a context switch is
+ * needed before exiting from ISR
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xHandle                    Event group handle
+ * @param[in] xBitsToClear               Bitmask to clear required fields in
+ *                                       the event group. Valid bitmask range
+ *                                       for ARM Cortex-R5 processor is 0 - 23
+ *                                       bits
+ * @param[out] pbHigherPriorityTaskWoken Pointer to rtosbool variable
+ *
+ * @retval rtosPASS                          on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null input parameter
+ * @retval E_RTOS_INVALID_EVENT_GROUP_HANDLE Invalid event group handle
+ * @retval E_RTOS_INVALID_PARAMETERS         Invalid parameters
+ * @retval E_RTOS_QUEUE_FULL                 Queue associated with event group
+ *                                           object is full and cannot accept
+ *                                           incoming event group request
+ * @retval E_RTOS_INVALID_DATA_RANGE         Error while copying data to the output
+ *                                           parameter
+ */
+static inline rtosError
+rtosEventGroupClearBitsFromISR(rtosEventGroupHandle xHandle,
+                               const rtosEventBits xBitsToClear,
+                               rtosBool *pbHigherPriorityTaskWoken)
+{
+    UNUSED(pbHigherPriorityTaskWoken);
+    return xEventGroupClearBitsFromISR(xHandle,
+                                       xBitsToClear);
+}
+
+/**
+ * @brief Wait for one or more bits to set within an event group until timeout
+ *
+ * This function is a wrapper for xEventGroupWaitBits() in SafeRTOS to wait until
+ * given pattern of event group bits is set
+ * Calling task blocks on waiting for required bit fields to be set as long as wait
+ * condition is met until timeout
+ *
+ * @pre
+ * - An event group object has been created with a valid handle referring to it
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xHandle         Event group handle
+ * @param[in] xBitsToWaitFor  Bitmask to check for required fields. Valid range
+ *                            of bitmask on ARM Cortex-R5 processor is
+ *                            0 - 23 bits
+ * @param[in] xClearOnExit    Set this bool variable to clear all the bit fields
+ *                            before exiting wait
+ * @param[in] xWaitForAllBits Set this bool variable if all the required bit
+ *                            fields should be set to exit from wait
+ * @param[in] pxEventBitsSet  Pointer to event group bits. Before exiting from
+ *                            wait, value at this address is updated with the
+ *                            status of event group bits
+ * @param[in] xTicksToWait    Timeout in ticks for which the calling task should
+ *                            be held in blocked state waiting for the pattern
+ *                            condition to be set. A value of zero prevents the
+ *                            task from entering the blocked state.
+ *
+ * @retval rtosPASS                          on success
+ * @retval E_RTOS_INVALID_EVENT_GROUP_HANDLE Invalid event group handle
+ * @retval E_RTOS_INVALID_PARAMETERS         Invalid parameters
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null parameter for event group
+ *                                           handle
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED     Scheduler is suspended
+ * @retval E_RTOS_EVENT_GROUP_DELETED        Event group deleted
+ * @retval E_RTOS_EVENT_GROUP_BITS_NOT_SET   Required event group bits not set
+ * @retval E_RTOS_INVALID_DATA_RANGE         Error while copying data to the output
+ *                                           parameter
+ */
+static inline rtosError
+rtosEventGroupWaitBits(rtosEventGroupHandle xHandle,
+                       const rtosEventBits xBitsToWaitFor,
+                       const rtosBool xClearOnExit,
+                       const rtosBool xWaitForAllBits,
+                       rtosEventBits *pxEventBitsSet,
+                       rtosTick xTicksToWait)
+{
+    return xEventGroupWaitBits(xHandle,
+                               xBitsToWaitFor,
+                               (portBaseType)xClearOnExit,
+                               (portBaseType)xWaitForAllBits,
+                               pxEventBitsSet,
+                               xTicksToWait);
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-event-poll.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-event-poll.h
new file mode 100644
index 0000000..34aaa74
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-event-poll.h
@@ -0,0 +1,315 @@
+/* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_EVENT_POLL_H
+#define OSA__OSA_EVENT_POLL_H
+#define FSP__OSA__OSA_EVENT_POLL_H                      1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosEventPollHandle, rtosUCount, rtosEve...
+#include <queueAPI.h>                   // IWYU pragma: keep
+                                        // for xQUEUE
+#include <evtmplxAPI.h>                 // IWYU pragma: export
+                                        // IWYU pragma: no_include "evtmplxAPI.h"
+                                        // for eventPollObjectEventsType
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+#endif
+
+/**
+ * @brief Computes the size needed for rtosEventPollCreate
+ *
+ * @param[in] uxMaximumRegisteredObjectEvents Maximum number of object events
+ *                                            supported with the event poll
+ *                                            object
+ *
+ * @retval NumberOfBytes Size of event poll object in bytes.
+ */
+#define rtosEventPollSize(uxMaximumRegisteredObjectEvents)\
+        rtosEVENT_POLL_OVERHEAD_BYTES(uxMaximumRegisteredObjectEvents)
+
+/**
+ * @brief Create an event poll object
+ *
+ * This function is a wrapper for xEventPollCreate() in SafeRTOS to create
+ * an event poll object
+ * It updates pointer to the event poll handle to point to the newly
+ * created event group
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle an event poll object.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pcEventPollMemoryBuffer         Pointer to the memory at which
+ *                                            event poll object will be created
+ * @param[in] uxBufferLengthInBytes           Buffer length to handle event poll
+ *                                            group. It should be equal to
+ *                                            rtosEventPollSize()
+ * @param[in] uxMaximumRegisteredObjectEvents Limit on the number of targets
+ *                                            that can register to the event
+ *                                            poll group. Should be equal to
+ *                                            uxMaximumRegisteredObjectEvents used
+ *                                            while creating memory for the event
+ *                                            poll object
+ * @param[in] xOwnerTaskHandle                Handle of task creating/owning the
+ *                                            event group.
+ * @param[out] pxEventPollHandle              Pointer to the event poll handle
+ *
+ * @retval rtosPASS                                on success
+ * @retval E_RTOS_EVENT_POLL_OBJECT_ALREADY_IN_USE Input event poll buffer
+ *                                                 already in use
+ * @retval E_RTOS_INVALID_DATA_RANGE               Invalid input memory address
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED          Null parameter supplied for
+ *                                                 Event poll handle/Task handle
+ *                                                 /Memory buffer
+ * @retval E_RTOS_INVALID_ALIGNMENT                Input buffer not word aligned
+ * @retval E_RTOS_INVALID_PARAMETERS               Invalid input parameter to
+ *                                                 set maximum number of
+ *                                                 registered objects.
+ * @retval E_RTOS_INVALID_BUFFER_SIZE              Invalid input buffer size
+ * @retval E_RTOS_INVALID_TASK_HANDLE              Invalid input task handle
+ */
+static inline rtosError
+rtosEventPollCreate(void *pcEventPollMemoryBuffer,
+                    rtosUCount uxBufferLengthInBytes,
+                    rtosUCount uxMaximumRegisteredObjectEvents,
+                    rtosTaskHandle xOwnerTaskHandle,
+                    rtosEventPollHandle * pxEventPollHandle)
+{
+    return xEvtMplxCreate((portInt8Type *)pcEventPollMemoryBuffer,
+                            uxBufferLengthInBytes, uxMaximumRegisteredObjectEvents,
+                            xOwnerTaskHandle, pxEventPollHandle);
+}
+
+/**
+ * @brief Register a target object event to the event poll object
+ *
+ * This function is a wrapper for xEventPollAddObjectEvents() in SafeRTOS
+ * It registers target object along with the specified events to the
+ * event poll group referenced using handle sent as an argument.
+ *
+ * @pre
+ * - An event poll object has been created with a valid handle referring to it
+ *
+ * - An RTOS kernel object has been created with a valid handle referring to it
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xEventPollHandle     Handle referring to the event poll group
+ * @param[in] pvTargetObjectHandle Handle referring to the target object.
+ * @param[in] uxEvents             Events to register with poll group concerning
+ *                                 target object
+ *
+ * @retval rtosPASS                                      on success
+ * @retval E_RTOS_INVALID_EVENT_POLL_OPERATION           Input target object is
+ *                                                       already registered with
+ *                                                       event poll object.
+ * @retval E_RTOS_EVENT_POLL_OBJECT_EVENTS_LIMIT_REACHED No more target objects
+ *                                                       can be registered with
+ *                                                       event poll object
+ * @retval E_RTOS_SCHEDULER_IS_NOT_RUNNING               Scheduler is not running
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED                Null set for event poll
+ *                                                       object handle/
+ *                                                       target object handle
+ * @retval E_RTOS_INVALID_EVENT_POLL_EVENTS              Attempt to set invalid
+ *                                                       events for the target
+ *                                                       object
+ * @retval E_RTOS_INVALID_EVENT_POLL_HANDLE              Invalid event poll handle
+ */
+static inline rtosError
+rtosEventPollAddObjectEvents(rtosEventPollHandle xEventPollHandle,
+                             void *pvTargetObjectHandle,
+                             rtosEventPollValue uxEvents)
+{
+    return xEvtMplxAddObjectEvents(xEventPollHandle, pvTargetObjectHandle, uxEvents);
+}
+
+/**
+ * @brief Modify object-events of a target object within event poll group
+ *
+ * This function is a wrapper for xEventPollModifyObjectEvents() in SafeRTOS.
+ * It modifies object-events concerning a target object registered with
+ * event poll group referred using handle sent as an argument.
+ *
+ * @pre
+ * - Target object associated with referred object event has been registered
+ * with an event poll object
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xEventPollHandle     Handle referring to the event poll group
+ * @param[in] pvTargetObjectHandle Handle referring to the target object.
+ * @param[in] uxEvents             Event poll value to be set for the target
+ *                                 object registered with poll group.
+ *
+ * @retval rtosPASS                            on success
+ * @retval E_RTOS_INVALID_EVENT_POLL_OPERATION Input target object not
+ *                                             registered with referred event
+ *                                             poll object.
+ * @retval E_RTOS_SCHEDULER_IS_NOT_RUNNING     Scheduler is not running
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED      Null set for event poll object
+ *                                             handle/Target object handle
+ * @retval E_RTOS_INVALID_EVENT_POLL_EVENTS    Attempt to set invalid events
+ *                                             for the target object
+ * @retval E_RTOS_INVALID_EVENT_POLL_HANDLE    Invalid event poll handle
+ */
+static inline rtosError
+rtosEventPollModifyObjectEvents(rtosEventPollHandle xEventPollHandle,
+                                const void *pvTargetObjectHandle,
+                                rtosEventPollValue uxEvents)
+{
+    return xEvtMplxModifyObjectEvents(xEventPollHandle, pvTargetObjectHandle,
+                                        uxEvents);
+}
+
+/**
+ * @brief Unregister target object along with associated events from event poll
+ * object
+ *
+ * This is a wrapper function for xEventPollRemoveObjectEvents() in SafeRTOS.
+ * It unregisters target-object along with its events from the event poll object
+ *
+ * @pre
+ * - Referred target object has been registered with the input event poll object.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xEventPollHandle     Handle referring to the event poll group
+ * @param[in] pvTargetObjectHandle Handle referring to the target object.
+ *
+ * @retval rtosTRUE                            on success
+ * @retval E_RTOS_SCHEDULER_IS_NOT_RUNNING     Scheduler is not running. Request
+ *                                             cannot be processed.
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED      Null set for event poll object/
+ *                                             Target object handle
+ * @retval E_RTOS_INVALID_EVENT_POLL_HANDLE    Invalid event poll handle
+ * @retval E_RTOS_INVALID_EVENT_POLL_OPERATION Input target object not registered
+ *                                             with referred event poll object.
+ */
+static inline rtosError
+rtosEventPollRemoveObjectEvents(rtosEventPollHandle xEventPollHandle,
+                                const void *pvTargetObjectHandle)
+{
+     return xEvtMplxRemoveObjectEvents(xEventPollHandle, pvTargetObjectHandle);
+}
+
+
+/**
+ * @brief Wait for an event registered with event poll object
+ *
+ * This function is a wrapper for xEventPollWait() in SafeRTOS.
+ * Object-events invoked by the event poll object referenced
+ * using supplied handle are copied to the input object-events array.
+ * If none of the registered object-events have occurred, this function blocks
+ * the calling task waiting for an object-event until timeout.
+ *
+ * @pre
+ * - Referred target object events have been registered with input event poll
+ * object.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xEventPollHandle         Handle referring to event poll object
+ * @param[in] uxObjectEventsArraySize  Size of input array to store object-event.
+ *                                     Should be at least equal to
+ *                                     uxMaximumRegisteredObjectEvents defined
+ *                                     during event poll object creation
+ * @param[in] xTicksToWait             Timeout in ticks to wait until an event occurs.
+ * @param[out] puxNumberOfObjectEvents Pointer to a count variable to store
+ *                                     number of object-events that occurred
+ * @param[out] axObjectEvents[]        Array to store info of object-events that
+ *                                     occurred. Length of this array should be at least
+ *                                     equal to uxMaximumRegisteredObjectEvents defined
+ *                                     during event poll object creation
+ *
+ * @retval rtosPASS                            on success.
+ * @retval E_RTOS_SCHEDULER_IS_NOT_RUNNING     Scheduler is not running. Request
+ *                                             cannot be processed.
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED      Null set for event poll object
+ *                                             handle/target object handle/array
+ *                                             to store object-events/pointer to
+ *                                             store number of object-events
+ * @retval E_RTOS_INVALID_EVENT_POLL_HANDLE    Invalid event poll handle
+ * @retval E_RTOS_INVALID_EVENT_POLL_OPERATION No object-event registered with
+ *                                             referred event poll object.
+ * @retval E_RTOS_INVALID_PARAMETERS           Zero size set for axObjectEvents
+ *                                             array
+ * @retval E_RTOS_INVALID_DATA_RANGE           Invalid length of the axObjectEvents
+ *                                             array.
+ * @retval E_RTOS_EVENT_GROUP_DELETED          Event group corresponding to the object
+ *                                             events deleted
+ * @retval E_RTOS_NO_EVENT_OCCURRED            No event occurred before the timeout
+ */
+static inline rtosError
+rtosEventPollWait(rtosEventPollHandle xEventPollHandle,
+                  rtosEventPollObjectEventsType axObjectEvents[],
+                  rtosUCount uxObjectEventsArraySize,
+                  rtosUCount * puxNumberOfObjectEvents,
+                  rtosTick xTicksToWait )
+{
+    return xEvtMplxWait(xEventPollHandle,
+                          (evtMplxObjectEventsType *)axObjectEvents,
+                          uxObjectEventsArraySize, puxNumberOfObjectEvents,
+                          xTicksToWait);
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-mutex.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-mutex.h
new file mode 100644
index 0000000..467bdbd
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-mutex.h
@@ -0,0 +1,197 @@
+/* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_MUTEX_H
+#define OSA__OSA_MUTEX_H
+#define FSP__OSA__OSA_MUTEX_H                           1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosMutexHandle, FSP__OSPL__RTOS_PORT_H
+#include <queueAPI.h>                   // IWYU pragma: keep
+                                        // for xQUEUE
+#include <mutexAPI.h>                   // IWYU pragma: export
+                                        // IWYU pragma: no_include "mutex.h"
+                                        // for xMutexGetState
+
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+#endif
+/**
+ * @brief Computes the size needed for rtosMutexCreate.
+ *
+ * @retval NumberOfBytes Size of mutex object in bytes
+ */
+#define rtosMutexSize()         rtosMUTEX_OVERHEAD_BYTES
+
+/**
+ * @brief Create a mutex lock
+ *
+ * This function is a wrapper for xMutexCreate() in SafeRTOS to create
+ * a mutex object.
+ * It updates pointer to the handle sent as an argument
+ * with newly created mutex
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle a mutex object
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pcMutexBuffer Pointer to the memory location at which mutex
+ *                          will be created. Size of the mutex buffer
+ *                          is rtosMutexSize()
+ *                          Mutex buffer shall be 4-byte aligned
+ * @param[in] pxMutex       Mutex handle 
+ *
+ * @retval rtosPASS                         on success
+ * @retval E_RTOS_INVALID_BUFFER_SIZE       Invalid input buffer size
+ * @retval E_RTOS_QUEUE_ALREADY_IN_USE      A valid queue object referring to a
+ *                                          mutex already associated with
+ *                                          the input memory buffer
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED   NULL supplied for input parameters
+ * @retval E_RTOS_INVALID_DATA_RANGE        Data could not be written in the input buffer
+ * @retval E_RTOS_INVALID_ALIGNMENT         Input buffer is not word aligned
+ */
+static inline rtosError
+rtosMutexCreate(void *pcMutexBuffer,
+                rtosMutexHandle *pxMutex)
+{
+    return xMutexCreate((portInt8Type *)pcMutexBuffer,
+                        pxMutex);
+}
+
+/**
+ * @brief Acquire a mutex
+ *
+ * This function is a wrapper for xMutexTake() in SafeRTOS to acquire a mutex
+ *
+ * @pre
+ * - A mutex has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xMutex     Mutex handle
+ * @param[in] xBlockTime Timeout in ticks to wait until mutex is acquired.
+ *                       A value of zero prevents the calling task from
+ *                       entering the Blocked state.
+ *
+ * @retval rtosPASS                      on success
+ * @retval E_RTOS_INVALID_MUTEX_HANDLE   Invalid mutex handle
+ * @retval E_RTOS_MUTEX_ALREADY_TAKEN    Mutex already acquired
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED Scheduler suspended
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK      Error unblocking the owner task
+ */
+static inline rtosError
+rtosMutexAcquire(rtosMutexHandle xMutex,
+                 rtosTick xBlockTime)
+{
+    return xMutexTake(xMutex,
+                      xBlockTime);
+}
+
+/**
+ * @brief Release acquired mutex
+ *
+ * This function is a wrapper for xMutexGive() in SafeRTOS to release
+ * an acquired mutex.
+ *
+ * @pre
+ * - A mutex has been created with a valid handle
+ *
+ * - Referred mutex was previously acquired.
+ *
+ * - Scheduler has been started
+ *
+ * - Called in a non-interrupt context
+ *
+ * @param[in] xMutex Mutex handle
+ *
+ * @retval rtosPASS                         on success
+ * @retval E_RTOS_INVALID_MUTEX_HANDLE      Invalid handle
+ * @retval E_RTOS_MUTEX_NOT_OWNED_BY_CALLER Mutex not owned by the caller
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED    Scheduler suspended
+ * @retval E_RTOS_MUTEX_CORRUPTED           Corrupt mutex
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK         Error unblocking the owner task
+ */
+static inline rtosError
+rtosMutexRelease(rtosMutexHandle xMutex)
+{
+    return xMutexGive(xMutex);
+}
+
+/**
+ * @brief Get mutex state
+ *
+ * This function is a wrapper for xMutexGetState() in SafeRTOS to query whether
+ * a mutex is available or not.
+ * It updates pointer to type rtosMutexState with current state of mutex lock.
+ * Mutex State can take two values: rtosMUTEX_TAKEN & rtosMUTEX_AVAILABLE
+ *
+ * @pre
+ * - A mutex has been created with a valid handle referring to it
+ *
+ * @param[in] xMutex         Mutex handle
+ * @param[out] puxMutexState Pointer to variable of type rtosMutexState
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_MUTEX_HANDLE    Invalid mutex handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null mutex handle
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error writing data to the output parameter
+ */
+static inline rtosError
+rtosMutexGetState(rtosMutexHandle xMutex,
+                  rtosMutexState *puxMutexState)
+{
+    return xMutexGetState(xMutex,
+                          puxMutexState);
+}
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-queue.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-queue.h
new file mode 100644
index 0000000..12b440a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-queue.h
@@ -0,0 +1,510 @@
+/* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_QUEUE_H
+#define OSA__OSA_QUEUE_H
+#define FSP__OSA__OSA_QUEUE_H                           1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+#include <misc/attributes.h>            // for UNUSED
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <osa/rtos-values.h>           // for rtosFALSE
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosQueueHandle, rtosTick, rtosUCoun
+#include <SafeRTOS_API.h>               // for vTaskProcessSystemTickFromISR, xTaskIsSc...
+#include <apiBaseTypes.h>               // for portInt8Type
+#include <queueAPI.h>                   // IWYU pragma: export
+                                        // IWYU pragma: no_include "queueAPI.h"
+                                        // IWYU pragma: no_include "apiWrapper.h"
+                                        // for xQueueReceiveFromISR, xQueueSendFro...
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__OSA__RTOS_VALUES_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+#endif
+/**
+ * @brief rtosQueueSize() computes the size needed for rtosQueueCreate.
+ *
+ * _n_                 max number of elements in queue
+ *
+ * _s_                 size of a queue element
+ *
+ * @retval NumberOfBytes Size of queue in bytes
+ */
+#define rtosQueueSize(_n_, _s_) (((_n_) * (_s_)) + rtosQUEUE_OVERHEAD_BYTES)
+
+/**
+ * @brief Create a task queue
+ *
+ * This function is a wrapper for xQueueCreate() in SafeRTOS.
+ * It updates the pointer to the queue handle to point
+ * to the newly created queue
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle a queue object.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pcQueueMemory  Pointer to memory at which queue object
+ *                           will be created. Queue buffer should be 4-byte
+ *                           aligned.
+ * @param[in] uxBufferLength Buffer length to handle tasks. Should be equal to
+ *                           rtosQueueSize(_n_, _s_)
+ * @param[in] uxQueueLength  Maximum number of items the queue can hold
+ * @param[in] uxItemSize     Size of the item to be stored in the queue
+ * @param[out] pxQueue       Pointer to queue handle
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_QUEUE_ALREADY_IN_USE    Queue at input memory location already in use
+ * @retval E_RTOS_INVALID_ALIGNMENT       Memory not word aligned
+ * @retval E_RTOS_INVALID_QUEUE_LENGTH    Invalid queue length
+ * @retval E_RTOS_INVALID_BUFFER_SIZE     Invalid buffer size
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null pointer to queue memory/handle
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error while copying data to the input
+ *                                        buffer
+ */
+static inline rtosError
+rtosQueueCreate(void *pcQueueMemory,
+                rtosUCount uxBufferLength,
+                rtosUCount uxQueueLength,
+                rtosUCount uxItemSize,
+                rtosQueueHandle *pxQueue)
+{
+    return xQueueCreate((portInt8Type *)pcQueueMemory,
+                        uxBufferLength,
+                        uxQueueLength,
+                        uxItemSize,
+                        pxQueue);
+}
+
+/**
+ * @brief: Delete queue
+ *
+ * This function does not exist in SafeRTOS, will return rtosPASS.
+ *
+ * @param[in] pxQueue       Pointer to queue handle
+ *
+ * @retval rtosPASS         on success
+ */
+static inline rtosError
+rtosQueueDelete(rtosQueueHandle *pxQueue)
+{
+    UNUSED(pxQueue);
+    return rtosPASS;
+}
+
+/**
+ * @brief Add an item at the end of a queue
+ *
+ * This function is a wrapper for xQueueSend() in SafeRTOS.
+ * Sends a item in the queue in First In First Out (FIFO) order.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] rtosQueue     Queue handle
+ * @param[in] pvItemToQueue Pointer to the item
+ * @param[in] xTicksToWait  Timeout in ticks to wait until the
+ *                          item gets added. A value of 0 prevents the task
+ *                          from entering blocked state.
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null item passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler suspended
+ * @retval E_RTOS_QUEUE_FULL              Queue is full and item cannot be added
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ */
+static inline rtosError
+rtosQueueSend(rtosQueueHandle rtosQueue,
+              const void * const pvItemToQueue,
+              rtosTick xTicksToWait)
+{
+    return xQueueSend(rtosQueue,
+                      pvItemToQueue,
+                      xTicksToWait);
+}
+
+/**
+ * @brief Add an item at the end of a queue
+ *
+ * This function is a wrapper for xQueueSend() in SafeRTOS.
+ * Sends an item in the queue in First In First Out (FIFO) order.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ *
+ *
+ * @param[in] rtosQueue     Queue handle
+ * @param[in] pvItemToQueue Pointer to the item
+ * @param[in] xTicksToWait  Timeout in ticks to wait until the
+ *                          item gets added. A value of 0 prevents the task
+ *                          from entering blocked state.
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null item passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler suspended
+ * @retval E_RTOS_QUEUE_FULL              Queue is full and item cannot be added
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ */
+static inline rtosError
+rtosQueueSendToBack(rtosQueueHandle rtosQueue,
+                    const void *const pvItemToQueue,
+                    rtosTick xTicksToWait)
+{
+    return xQueueSend(rtosQueue,
+                      pvItemToQueue,
+                      xTicksToWait);
+}
+
+/**
+ * @brief Add an item at the front of a queue
+ *
+ * This function is a wrapper for xQueueSendToFront() in SafeRTOS.
+ * Sends an item in the queue in Last In First Out (LIFO) order.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] rtosQueue     Queue handle
+ * @param[in] pvItemToQueue Pointer to item
+ * @param[in] xTicksToWait  Timeout in ticks to wait until
+ *                          item gets added. A value of 0 prevents the task from
+ *                          entering blocked state
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null item passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler suspended
+ * @retval E_RTOS_QUEUE_FULL              Queue is full and item cannot be added
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ */
+static inline rtosError
+rtosQueueSendToFront(rtosQueueHandle rtosQueue,
+                     const void * const pvItemToQueue,
+                     rtosTick xTicksToWait)
+{
+    return xQueueSendToFront(rtosQueue,
+                             pvItemToQueue,
+                             xTicksToWait);
+}
+
+/**
+ * @brief Pick an item from the queue
+ *
+ * This is a wrapper for xQueueReceive() in SafeRTOS
+ * It always picks item from the beginning of a queue.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] rtosQueue    Queue handle
+ * @param[in] pvBuffer     Pointer to the buffer to copy the item. Length of
+ *                         buffer should be at least equal to the item size.
+ * @param[in] xTicksToWait Timeout in ticks to wait until item is picked.
+ *                         A value of 0 prevents the task from entering
+ *                         blocked state
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null buffer passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler is suspended
+ * @retval E_RTOS_QUEUE_EMPTY             Empty queue
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ */
+static inline rtosError
+rtosQueueReceive(rtosQueueHandle rtosQueue,
+                 void *const pvBuffer,
+                 rtosTick xTicksToWait)
+{
+    return xQueueReceive(rtosQueue,
+                         pvBuffer,
+                         xTicksToWait);
+}
+
+/**
+ * @brief Peek an item from queue
+ *
+ * This function is a wrapper for xQueuePeek() in SafeRTOS
+ * It picks an item without removing it from the queue.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] rtosQueue    Queue handle
+ * @param[in] pvBuffer     Pointer to a buffer to copy the item.
+ *                         Length of the buffer should be at least equal to the
+ *                         queue item size.
+ * @param[in] xTicksToWait Timeout in ticks to wait until item is picked.
+ *                         A value of 0 prevents the task from entering the
+ *                         blocked state
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null buffer passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler is suspended
+ * @retval E_RTOS_QUEUE_EMPTY             Empty queue
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ */
+static inline rtosError
+rtosQueuePeek(rtosQueueHandle rtosQueue,
+              void *const pvBuffer,
+              rtosTick xTicksToWait)
+{
+    return xQueuePeek(rtosQueue,
+                      pvBuffer,
+                      xTicksToWait);
+}
+
+/**
+ * @brief Get number of waiting messages in the queue.
+ *
+ * This function is a wrapper for xQueueMessagesWaiting() in SafeRTOS.
+ * It updates value at pointer to a count variable sent as an argument
+ * with latest number of pending items in the queue.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in]  rtosQueue          Queue handle
+ * @param[out] puxMessagesWaiting Pointer to a count variable
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null pointer to count variable passed
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error while copying data to the
+ *                                        output parameter
+ */
+static inline rtosError
+rtosQueueMessageWaiting(rtosQueueHandle rtosQueue,
+                        rtosUCount *puxMessagesWaiting)
+{
+    return xQueueMessagesWaiting(rtosQueue,
+                                 puxMessagesWaiting);
+}
+
+/**
+ * @brief Add an item at the end of a queue from ISR
+ *
+ * This function is a wrapper for xQueueSendFromISR() in SafeRTOS.
+ * Adds an item to the queue from interrupt context in First In First Out (FIFO)
+ * It sets value at pointer to a bool variable sent as an
+ * argument if adding item to the queue unblocks a higher/equal priority task
+ * than the current active task.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] rtosQueue                  Queue handle
+ * @param[in] pvItemToQueue              Pointer to item
+ * @param[out] pbHigherPriorityTaskWoken Pointer to a bool variable
+ *                                       indicating current context.
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null item/context variable passed
+ * @retval E_RTOS_QUEUE_FULL              Queue full and item cannot be added
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error while copying data to the output
+ *                                        parameter
+ */
+static inline rtosError
+rtosQueueSendFromISR(rtosQueueHandle rtosQueue,
+                     const void *const pvItemToQueue,
+                     rtosBool *pbHigherPriorityTaskWoken)
+{
+    UNUSED(pbHigherPriorityTaskWoken);
+    return xQueueSendFromISR(rtosQueue,
+                             pvItemToQueue);
+}
+
+/**
+ * @brief Add an item at the end of a queue from ISR
+ *
+ * This function is a wrapper for xQueueSendFromISR().
+ * Adds an item to the queue from interrupt context in First In First Out (FIFO)
+ * It sets value at pointer to a bool variable sent as an
+ * argument if adding item to the queue unblocks a higher/equal priority task
+ * than the current active task.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] rtosQueue                  Queue handle
+ * @param[in] pvItemToQueue              Pointer to item
+ * @param[out] pbHigherPriorityTaskWoken Pointer to a bool variable
+ *                                       indicating current context.
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null item/context variable passed
+ * @retval E_RTOS_QUEUE_FULL              Queue full and item cannot be added
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error while copying data to the output
+ *                                        parameter
+ */
+static inline rtosError
+rtosQueueSendToBackFromISR(rtosQueueHandle rtosQueue,
+                           const void *const pvItemToQueue,
+                           rtosBool *pbHigherPriorityTaskWoken)
+{
+    UNUSED(pbHigherPriorityTaskWoken);
+    return xQueueSendFromISR(rtosQueue, pvItemToQueue);
+}
+
+/**
+ * @brief Add an item at the front of a queue from ISR
+ *
+ * This function is a wrapper for xQueueSendToFrontFromISR() in SafeRTOS.
+ * Adds an item to the queue from interrupt context in Last In First Out (LIFO)
+ * order.
+ * It sets value at pointer to a bool variable sent as an argument if adding
+ * item to the queue unblocks a higher/equal priority task than the current
+ * active task.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] rtosQueue                  Queue handle
+ * @param[in] pvItemToQueue              Pointer to item
+ * @param[out] pbHigherPriorityTaskWoken Pointer to a bool variable
+ *                                       indicating current context.
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null item/context variable passed
+ * @retval E_RTOS_QUEUE_FULL              Queue full and item cannot be added
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error while copying data to the output
+ *                                        parameter
+ */
+static inline rtosError
+rtosQueueSendToFrontFromISR(rtosQueueHandle rtosQueue,
+                            const void *const pvItemToQueue,
+                            rtosBool *pbHigherPriorityTaskWoken)
+{
+    UNUSED(pbHigherPriorityTaskWoken);
+    return xQueueSendToFrontFromISR(rtosQueue,
+                                    pvItemToQueue);
+}
+
+/**
+ * @brief Pick an item from the queue in interrupt context
+ *
+ * This function is a wrapper for xQueueReceiveFromISR() in SafeRTOS
+ * Picks item from the beginning of a queue in an interrupt context
+ * and sets value at pointer to a bool variable sent as an argument if calling
+ * this function unblocks a higher priority task than the current active task.
+ *
+ * @pre
+ * - A queue has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] rtosQueue                   Queue handle
+ * @param[in] pvBuffer                    Pointer to a buffer to copy the item.
+ *                                        Length of the buffer should be at
+ *                                        least equal to the item size.
+ * @param[out] pbHigherPriorityTaskWoken  Pointer to a bool variable
+ *                                        indicating current context.
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_QUEUE_HANDLE    Invalid handle passed
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null buffer/context variable passed
+ * @retval E_RTOS_QUEUE_EMPTY             Empty queue
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error while copying data to the output
+ *                                        parameter                                    
+ */
+static inline rtosError
+rtosQueueReceiveFromISR(rtosQueueHandle rtosQueue,
+                        void *const pvBuffer,
+                        rtosBool *pbHigherPriorityTaskWoken)
+{
+    UNUSED(pbHigherPriorityTaskWoken);
+    return xQueueReceiveFromISR(rtosQueue,
+                                pvBuffer);
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-semaphore.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-semaphore.h
new file mode 100644
index 0000000..77c9905
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-semaphore.h
@@ -0,0 +1,318 @@
+/* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_SEMAPHORE_H
+#define OSA__OSA_SEMAPHORE_H
+#define FSP__OSA__OSA_SEMAPHORE_H                       1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-sepcific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosSemaphoreHandle, rtosUCount, rtosBool
+#include <queueAPI.h>                   // IWYU pragma: keep
+                                        // for xQueueHandle, xQueueReceive, xQueueSend,.
+#include <semaphoreAPI.h>               // IWYU pragma: export
+                                        // IWYU pragma: no_include "semaphore.h"
+                                        // for xSemaphoreGetCountDepth, xSemaphore...
+
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+#endif
+/**
+ * @brief rtosSemaphoreSize() computes the size needed for rtosSemaphoreCreate.
+ *
+ * @retval NumberOfBytes Size of semaphore object in bytes
+ */
+#define rtosSemaphoreSize()     rtosSEMAPHORE_OVERHEAD_BYTES
+
+/**
+ * @brief Create a binary semaphore.
+ *
+ * This function is a wrapper for xSemaphoreCreateBinary() in SafeRTOS
+ * to create a binary semaphore object.
+ * It updates the handle sent as an argument to point to the newly
+ * created semaphore
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle a semaphore object.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pcSemaphoreMemory Pointer to the memory location at which
+ *                              semaphore object will be created.
+ *                              Clients shall use rtosSemaphoreSize() to get
+ *                              the size of this pre-allocated memory.
+ *                              Memory buffer shall be 4-byte aligned.
+ * @param[out] xpSemaphore      Pointer to the semaphore handle
+ *
+ * @retval rtosPASS                         on success
+ * @retval E_RTOS_INVALID_BUFFER_SIZE       Invalid input buffer size
+ * @retval E_RTOS_QUEUE_ALREADY_IN_USE      A valid queue object referring to a
+ *                                          semaphore already associated with
+ *                                          the input memory buffer
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED   NULL supplied for input parameters
+ * @retval E_RTOS_INVALID_DATA_RANGE        Data could not be written in the input buffer
+ * @retval E_RTOS_INVALID_ALIGNMENT         Input buffer is not word aligned
+ */
+static inline rtosError
+rtosSemaphoreCreateBinary(void *pcSemaphoreMemory,
+                          rtosSemaphoreHandle *xpSemaphore)
+{
+    return xSemaphoreCreateBinary((portInt8Type *)pcSemaphoreMemory,
+                                  xpSemaphore);
+}
+
+/**
+ * @brief Create a counting semaphore
+ *
+ * This function is a wrapper for xSemaphoreCreateCounting() in SafeRTOS
+ * to create a counting semaphore object.
+ * It updates the handle sent as an argument to point to the newly
+ * created semaphore.
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle a semaphore object.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] uxMaxCount        Max limit of semaphore count.
+ *                              Should be set greater than 0
+ * @param[in] uxInitialCount    Min/Initial count of semaphore count.
+ *                              Should be set less than uxMaxCount
+ * @param[in] pcSemaphoreMemory Pointer to the memory location at which
+ *                              semaphore object will be created.
+ *                              Clients shall use rtosSemaphoreSize() to get
+ *                              the size of this pre-allocated memory.
+ *                              Memory buffer shall be 4-byte aligned.
+ * @param[out] xpSemaphore      Pointer to the semaphore handle
+ *
+ * @retval rtosPASS                               on success
+ * @retval E_RTOS_INVALID_BUFFER_SIZE             Invalid input buffer size
+ * @retval E_RTOS_INVALID_INITIAL_SEMAPHORE_COUNT Invalid semaphore initial
+ * count
+ * @retval E_RTOS_QUEUE_ALREADY_IN_USE      A valid queue object referring to a
+ *                                          semaphore already associated with
+ *                                          the input memory buffer
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED   NULL supplied for input parameters
+ * @retval E_RTOS_INVALID_DATA_RANGE        Data could not be written in the input buffer
+ * @retval E_RTOS_INVALID_ALIGNMENT         Input buffer is not word aligned
+ */
+static inline rtosError
+rtosSemaphoreCreateCounting(void *pcSemaphoreMemory,
+                            rtosUCount uxMaxCount,
+                            rtosUCount uxInitialCount,
+                            rtosSemaphoreHandle *xpSemaphore)
+{
+    return xSemaphoreCreateCounting(uxMaxCount,
+                                    uxInitialCount,
+                                    (portInt8Type *)pcSemaphoreMemory,
+                                    xpSemaphore);
+}
+
+/**
+ * @brief Release a semaphore
+ *
+ * This function is a wrapper for xSemaphoreGive() in SafeRTOS to
+ * release an acquired semaphore.
+ *
+ * @pre
+ * - A semaphore has been created with a valid handle referring to it
+ *
+ * - Referred Semaphore was previously acquired
+ *
+ * - Called from a non-interrupt context.
+ *
+ * - Scheduler has been started.
+ *
+ * @param[in] xSemaphore Semaphore handle
+ *
+ * @retval rtosPASS                        on success
+ * @retval E_RTOS_INVALID_SEMAPHORE_HANDLE Invalid semaphore handle
+ * @retval E_RTOS_SEMAPHORE_ALREADY_GIVEN  Semaphore already released
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED  Null semaphore handle
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED   Scheduler suspended
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK        Error unblocking the owner task
+ */
+static inline rtosError
+rtosSemaphoreRelease(rtosSemaphoreHandle xSemaphore)
+{
+    return xSemaphoreGive(xSemaphore);
+}
+
+/**
+ * @brief Release a semaphore from ISR
+ *
+ * This function is a wrapper for xSemaphoreGiveFromISR() in SafeRTOS to
+ * release an acquired semaphore in interrupt context.
+ * It sets value at pointer to RTOS bool variable sent
+ * as an argument if calling this API unblocks a task of priority equal
+ * to/higher than currently running task.
+ *
+ * @pre
+ * - A semaphore has been created with a valid handle referring to it.
+ *
+ * - Referred semaphore was previously acquired
+ *
+ * - Called from an interrupt context
+ *
+ * - Scheduler has been started.
+ *
+ * @param[in] xSemaphore                 Semaphore handle
+ * @param[out] pbHigherPriorityTaskWoken Pointer to a boolean variable
+ *
+ * @retval rtosPASS                        on success
+ * @retval E_RTOS_INVALID_SEMAPHORE_HANDLE Invalid handle
+ * @retval E_RTOS_SEMAPHORE_ALREADY_GIVEN  Semaphore released already
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED  Null semaphore handle
+ * @retval E_RTOS_INVALID_DATA_RANGE       Error writing to the output parameter
+ */
+static inline rtosError
+rtosSemaphoreReleaseFromISR(rtosSemaphoreHandle xSemaphore,
+                            rtosBool *pbHigherPriorityTaskWoken)
+{
+    UNUSED(pbHigherPriorityTaskWoken);
+    return xSemaphoreGiveFromISR(xSemaphore);
+}
+
+/**
+ * @brief Acquire a semaphore
+ *
+ * This function is a wrapper for xSemaphoreTake() in SafeRTOS to
+ * acquire a semaphore.
+ *
+ * @pre
+ * - A semaphore has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context
+ *
+ * - Scheduler has been started.
+ *
+ * @param[in] xSemaphore   Semaphore handle
+ * @param[in] xTicksToWait Timeout in ticks to wait until semaphore is acquired.
+ *                         A value of zero prevents the calling task from
+ *                         entering the Blocked state waiting for semaphore.
+ *
+ * @retval rtosPASS                        on success
+ * @retval E_RTOS_SEMAPHORE_ALREADY_TAKEN  Semaphore already taken
+ * @retval E_RTOS_INVALID_SEMAPHORE_HANDLE Invalid semaphore handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED  Null semaphore handle
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED   Scheduler is suspended
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK        Error unblocking the owner task
+ */
+static inline rtosError
+rtosSemaphoreAcquire(rtosSemaphoreHandle xSemaphore,
+                     rtosTick xTicksToWait)
+{
+    return xSemaphoreTake(xSemaphore, xTicksToWait);
+}
+
+/**
+ * @brief Acquire semaphore from ISR
+ *
+ * This function is a wrapper for xSemaphoreTakeFromISR() in SafeRTOS to
+ * acquire a semaphore in interrupt context.
+ * It sets value at pointer to RTOS bool variable sent as an argument
+ * if calling this API unblocks a task of priority equal to/higher than
+ * currently running task.
+ *
+ * @pre
+ * - A semaphore has been created with a valid handle referring to it
+ *
+ * - Called from an interrupt context
+ *
+ * - Scheduler has been started.
+ *
+ * @param[in] xSemaphore                 Semaphore handle
+ * @param[out] pbHigherPriorityTaskWoken Pointer to boolean variable
+ *
+ * @retval rtosPASS                        on success
+ * @retval E_RTOS_SEMAPHORE_ALREADY_TAKEN  Semaphore already taken
+ * @retval E_RTOS_INVALID_SEMAPHORE_HANDLE Invalid semaphore handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED  Null semaphore handle
+ * @retval E_RTOS_INVALID_DATA_RANGE       Error writing to the output parameter
+ */
+static inline rtosError
+rtosSemaphoreAcquireFromISR(rtosSemaphoreHandle xSemaphore,
+                            rtosBool *pbHigherPriorityTaskWoken)
+{
+    UNUSED(pbHigherPriorityTaskWoken);
+    return xSemaphoreTakeFromISR(xSemaphore);
+}
+
+/**
+ * @brief Get semaphore count depth
+ *
+ * This function is a wrapper for xSemaphoreGetCountDepth() in SafeRTOS.
+ * It sets value at pointer to RTOS count variable with current semaphore count.
+ * This represents the number of times that rtosSemaphoreAcquire()/
+ * rtosSemaphoreAcquireFromISR() can be successfully called before the next call
+ * to rtosSemaphoreRelease()/rtosSemaphoreReleaseFromISR() is made.
+ *
+ * @pre
+ * - A semaphore has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xSemaphore     Semaphore handle
+ * @param[out] puxCountDepth Pointer to RTOS count variable
+ *
+ * @retval rtosPASS                        on success
+ * @retval E_RTOS_INVALID_SEMAPHORE_HANDLE Invalid semaphore handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED  Null semaphore handle
+ * @retval E_RTOS_INVALID_DATA_RANGE       Error writing to the output parameter
+ */
+static inline rtosError
+rtosSemaphoreGetCountDepth(rtosSemaphoreHandle xSemaphore,
+                           rtosUCount *puxCountDepth)
+{
+    return xSemaphoreGetCountDepth(xSemaphore, puxCountDepth);
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-task.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-task.h
new file mode 100644
index 0000000..ff2a9b5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-task.h
@@ -0,0 +1,846 @@
+/* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_TASK_H
+#define OSA__OSA_TASK_H
+#define FSP__OSA__OSA_TASK_H                            1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>            // for UNUSED
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosBool, rtosTaskHandle, rtosTick, rtos...
+
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+#endif
+/**
+ * @brief rtosTCBSize() computes size of task TCB needed for rtosTaskCreate.
+ *
+ * @retval NumberOfBytes Size of TCB in bytes
+ */
+#define rtosTCBSize()           rtosTCB_OVERHEAD_BYTES
+
+/**
+ * @brief Initialize task scheduler
+ *
+ * This function is a wrapper for xTaskInitializeScheduler() in SafeRTOS to
+ * initialize a task scheduler.
+ * It configures scheduler private data and passes application specific data
+ * to the SafeRTOS scheduler by translating structures and types used by NVIDIA
+ * code to those used by SafeRTOS.
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it.
+ *
+ * - Scheduler init parameters have been set.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxSchedInitParameters Pointer to rtosSchedParameters structure
+ *                                  containing scheduler private data required for
+ *                                  initialization.
+ *
+ * @retval rtosPASS                              on success
+ * @retval E_RTOS_EXECUTING_IN_UNPRIVILEGED_MODE Processor in unprivileged mode
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED        Null init parameters
+ * @retval E_RTOS_QUEUE_ALREADY_IN_USE           A valid queue exists at the
+ *                                               input timer buffer provided as
+ *                                               part of scheduler parameters
+ * @retval E_RTOS_INVALID_ALIGNMENT              Input buffer not word aligned
+ * @retval E_RTOS_INVALID_QUEUE_LENGTH           Invalid timer queue length
+ * @retval E_RTOS_INVALID_BUFFER_SIZE            Invalid buffer size to
+ *                                               accommodate the timer or timer
+ *                                               task
+ * @retval E_RTOS_INVALID_DATA_RANGE             Error while copying data to the
+ *                                               input buffer
+ * @retval E_RTOS_INVALID_PRIORITY               Timer task priority above stated
+ *                                               maximum
+ * @retval E_RTOS_INVALID_TASK_CODE_POINTER      Invalid pointer to the timer
+ *                                               task code
+ * @retval E_RTOS_TASK_STACK_ALREADY_IN_USE      Timer task stackbuffer already
+ *                                               in use.
+ * @retval E_RTOS_SUPPLIED_BUFFER_TOO_SMALL      Supplied buffer not
+ *                                               sufficient to hold the timer task
+ */
+rtosError
+rtosTaskInitializeScheduler(const rtosSchedParameters *const pxSchedInitParameters);
+
+/**
+ * @brief Create a task
+ *
+ * This function is a wrapper for xTaskCreate() in SafeRTOS to create a new
+ * task and place it in ready state. It provides a translation of structures
+ * and types used by NVIDIA code to those used by SafeRTOS.
+ * It updates the pointer to task handle using task init structure sent as
+ * an argument to refer to the newly created task.
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * initialized for the task control block.
+ *
+ * - Task init parameters have been initialized
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxTaskParameters Pointer to a rtosTaskParameters structure that
+ *                             contains the parameters used to create a task
+ * @param[out] pxCreatedTask   Pointer to task handle
+ *
+ * @retval rtosPASS success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED          Null pointer to handle/task
+ *                                                 init structure
+ * @retval E_RTOS_INVALID_PRIORITY                 Task priority above stated
+ *                                                 maximum
+ * @retval E_RTOS_INVALID_TASK_CODE_POINTER        Invalid pointer to task code
+ * @retval E_RTOS_TASK_STACK_ALREADY_IN_USE        Memory pointed by stack
+ *                                                 buffer already in use.
+ * @retval E_RTOS_INVALID_ALIGNMENT                Stack buffer not word aligned
+ * @retval E_RTOS_SUPPLIED_BUFFER_TOO_SMALL        Supplied buffer not
+ *                                                 sufficient to hold the task
+ * @retval E_RTOS_INVALID_BUFFER_SIZE              Buffer size not a power of 2
+ * @retval E_RTOS_INVALID_DATA_RANGE               Error while copying data to the
+ *                                                 input buffer
+ */
+rtosError
+rtosTaskCreate(const rtosTaskParameters * const pxTaskParameters,
+               rtosTaskHandle *pxCreatedTask);
+
+/**
+ * @brief Delete a task
+ *
+ * This function is a wrapper for xTaskDelete() in SafeRTOS to delete a task.
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * - Scheduler is in running state if the request is to delete the calling task
+ *
+ * @param[in] pxTaskToDelete Input task handle
+ *
+ * @retval rtosPASS                   on success
+ * @retval E_RTOS_INVALID_TASK_HANDLE Invalid task handle
+ */
+static inline rtosError
+rtosTaskDelete(rtosTaskHandle pxTaskToDelete)
+{
+    return xTaskDelete(pxTaskToDelete);
+}
+
+/**
+ * @brief Delay a task for required time
+ *
+ * This function is a wrapper for xTaskDelay() in SafeRTOS.
+ * Places active task in blocked state for fixed number of cycles.
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] xTicksToDelay Time in ticks to delay the task. A value of 0
+ *                          will cause the task to yield instead of entering the
+ *                          blocked state
+ *
+ * @retval rtosPASS                      on success
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED Scheduler suspended
+ */
+static inline rtosError
+rtosTaskDelay(rtosTick xTicksToDelay)
+{
+    return xTaskDelay(xTicksToDelay);
+}
+
+/**
+ * @brief Delay a task until specified time.
+ *
+ * This function is a wrapper for xTaskDelayUntil() in SafeRTOS.
+ * It delays active task for a fixed period and wakes it
+ * up again at tick(previous wake time + Delay time).
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxPreviousWakeTime Pointer to variable of type rtosTick
+ *                               having previous wake time. Must be initialized
+ *                               with current time before first use. Updated
+ *                               automatically by this call thereafter.
+ * @param[in] xTimeIncrement     Time for which task must be delayed
+ *                               (Cycle time period)
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler suspended
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null passed for previous wake time
+ * @retval E_RTOS_DID_NOT_YIELD           Context Yield did not happen
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error writing data to the output parameter
+ */
+static inline rtosError
+rtosTaskDelayUntil(rtosTick *pxPreviousWakeTime,
+                   rtosTick xTimeIncrement)
+{
+    return xTaskDelayUntil(pxPreviousWakeTime, xTimeIncrement);
+}
+
+/**
+ * @brief Get priority of task
+ *
+ * This function is a wrapper for xTaskPriorityGet() in SafeRTOS.
+ * It updates value at pointer to variable of type
+ * rtosPriority sent as an argument with latest priority of input task
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxTask      Input task handle
+ * @param[in] puxPriority Pointer to a variable holding task priority
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED NULL task handle/pointer
+ * @retval E_RTOS_INVALID_TASK_HANDLE     Invalid task handle
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error writing data to the output parameter
+ */
+static inline rtosError
+rtosTaskPriorityGet(rtosTaskHandle pxTask,
+                    rtosPriority *puxPriority)
+{
+    return xTaskPriorityGet(pxTask, puxPriority);
+}
+
+/**
+ * @brief Set priority of a task
+ *
+ * This function is a wrapper for xTaskPrioritySet() in SafeRTOS to
+ * change the priority of a task.
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxTask        Input task handle
+ * @param[in] uxNewPriority Input task priority. Maximum priority
+ *                          is (configMAX_PRIORITIES - 1)
+ *
+ * @retval rtosPASS                   on success
+ * @retval E_RTOS_INVALID_TASK_HANDLE Invalid task handle
+ * @retval E_RTOS_INVALID_PRIORITY    Invalid task priority
+ */
+static inline rtosError
+rtosTaskPrioritySet(rtosTaskHandle pxTask,
+                    rtosPriority uxNewPriority)
+{
+    return xTaskPrioritySet(pxTask, uxNewPriority);
+}
+
+/**
+ * @brief Suspend a task
+ *
+ * This function is a wrapper for xTaskSuspend() in SafeRTOS.
+ * Places active task in suspended state
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxTaskToSuspend Input task handle. Value of NULL
+ *                            suspends the calling task
+ *
+ * @retval rtosPASS                      on success
+ * @retval E_RTOS_SCHEDULER_SUSPENDED    Scheduler suspended
+ * @retval E_RTOS_INVALID_TASK_HANDLE    Invalid handle
+ * @retval E_RTOS_TASK_ALREADY_SUSPENDED Task already suspended
+ */
+static inline rtosError
+rtosTaskSuspend(rtosTaskHandle pxTaskToSuspend)
+{
+    return xTaskSuspend(pxTaskToSuspend);
+}
+
+/**
+ * @brief Resume a suspended task
+ *
+ * This function is a wrapper for xTaskResume() in SafeRTOS.
+ * Resumes a suspended task and puts it ready state.
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it
+ *
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * - The task being referred was suspended.
+ *
+ * @param[in] pxTaskToResume Input task handle
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_TASK_WAS_NOT_SUSPENDED  Task was not suspended
+ * @retval E_RTOS_INVALID_TASK_HANDLE     Invalid handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null task handle
+ */
+static inline rtosError
+rtosTaskResume(rtosTaskHandle pxTaskToResume)
+{
+    return xTaskResume(pxTaskToResume);
+}
+
+/**
+ * @brief Get handle of current task
+ *
+ * This function is a wrapper for xTaskGetCurrentTaskHandle() in SafeRTOS.
+ * It returns handle of current task.
+ * No input arguments needed.
+ *
+ * @pre
+ * - Scheduler has been initialized and started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @retval xHandle Handle of the current task
+ */
+static inline rtosTaskHandle
+rtosTaskGetCurrentTaskHandle(void)
+{
+    return xTaskGetCurrentTaskHandle();
+}
+
+/**
+ * @brief Start a task scheduler
+ *
+ * This function is a wrapper for xTaskStartScheduler() in SafeRTOS.
+ * It starts scheduler if a set of preconditions are met.
+ * This can be ignored by passing input argument xUserKernelConfigurationChecks
+ * as rtosFALSE in which case scheduler will start regardless of the state.
+ *
+ * @pre
+ * - Scheduler has been initialized
+ *
+ * - A task has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context
+ *
+ * - Called with CPU in privileged mode
+ *
+ * @param[in] xUserKernelConfigurationChecks Bool variable to be set for
+ *                                           checking the pre-conditions before
+ *                                           starting the scheduler.
+ *
+ * @retval rtsoPASS                                 on success
+ * @retval E_RTOS_NO_TASKS_CREATED                  No tasks created
+ * @retval E_RTOS_SCHEDULER_ALREADY_RUNNING         Scheduler is already running
+ * @retval E_RTOS_BAD_OR_NO_TICK_RATE_CONFIGURATION Clock/tick rate parameter
+ *                                                  invalid/null
+ * @retval E_RTOS_EXECUTING_IN_UNPRIVILEGED_MODE    Processor in unprivileged
+ *                                                  mode
+ * @retval E_RTOS_INVALID_ALIGNMENT                 System stack address
+ *                                                  misaligned
+ * @retval E_RTOS_INVALID_BUFFER_SIZE               Size of the system stack is
+ *                                                  insufficient
+ * @retval E_RTOS_INVALID_PRIORITY                  Invalid priority for the idle task
+ * @retval E_RTOS_INVALID_TASK_CODE_POINTER         Invalid pointer to task code
+ * @retval E_RTOS_TASK_STACK_ALREADY_IN_USE         Memory pointed by stack
+ *                                                  buffer already in use.
+ * @retval E_RTOS_SUPPLIED_BUFFER_TOO_SMALL         Supplied buffer not
+ *                                                  sufficient to hold the idle task
+ *                                                  input buffer
+ */
+static inline rtosError
+rtosTaskStartScheduler(rtosBool xUserKernelConfigurationChecks)
+{
+    UNUSED(xUserKernelConfigurationChecks);
+    return (rtosError)xTaskStartScheduler();
+}
+
+/**
+ * @brief Suspend a scheduler
+ *
+ * This function is a wrapper for xTaskSuspendScheduler() in SafeRTOS
+ * It suspends scheduler irrespective of current state.
+ * Has no input arguments and returns none.
+ *
+ * @pre
+ * - Scheduler has been initialized and started.
+ *
+ * - Called from a non-interrupt context
+ *
+ */
+static inline void
+rtosTaskSuspendScheduler(void)
+{
+    vTaskSuspendScheduler();
+}
+
+/**
+ * @brief Resume suspended scheduler
+ *
+ * This function is a wrapper for xTaskResumeScheduler() in SafeRTOS.
+ * Transitions the suspended scheduler into active state.
+ * No input arguments needed.
+ *
+ * @pre
+ * - Scheduler has been started and currently in a suspended state
+ *
+ * - Called from a non-interrupt context
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_SCHEDULER_NOT_SUSPENDED Scheduler not suspended.
+ */
+static inline rtosError
+rtosTaskResumeScheduler(void)
+{
+    return xTaskResumeScheduler();
+}
+
+/**
+ * @brief Get ticks count
+ *
+ * This function is a wrapper for xTaskGetTickCount() in SafeRTOS.
+ * It returns ticks count since the scheduler was started.
+ * No input arguments needed.
+ *
+ * @pre
+ * - Called from a non-interrupt context.
+ *
+ * @retval xTicks Number of ticks passed since scheduler was started.
+ */
+static inline rtosTick
+rtosTaskGetTickCount(void)
+{
+    return xTaskGetTickCount();
+}
+
+/**
+ * @brief Get ticks count from ISR
+ *
+ * This function is a wrapper for xTaskGetTickCountFromISR() in SafeRTOS.
+ * Returns ticks count in an interrupt context since the scheduler was started.
+ * No input arguments needed.
+ *
+ * @pre
+ * - Called from an interrupt context
+ *
+ * @retval xTicks Number of ticks passed since scheduler was started.
+ */
+static inline rtosTick
+rtosTaskGetTickCountFromISR(void)
+{
+    return xTaskGetTickCountFromISR();
+}
+
+/**
+ * @brief Request task yield.
+ *
+ * This function is a wrapper for taskYIELD() in SafeRTOS.
+ * It enables yield to a task of equal/higher priority
+ * than current task. Has no input arguments and returns none.
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ */
+static inline void
+rtosTaskYield(void)
+{
+    safertosapiYIELD();
+}
+
+/**
+ * @brief Request task yield from ISR
+ *
+ * This function is a wrapper for taskYIELD_FROM_ISR() in SafeRTOS.
+ * It enables yield in an interrupt context to a task of
+ * equal/higher priority than current task. Returns none.
+ * Does nothing if input argument is rtosFALSE.
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context
+ *
+ * @param[in] xSwitchRequired Bool variable to indicate need for switch
+ */
+static inline void
+rtosTaskYieldFromISR(rtosBool xSwitchRequired)
+{
+    UNUSED(xSwitchRequired);
+    safertosapiYIELD_FROM_ISR();
+}
+
+/**
+ * @brief Enter critical section
+ *
+ * This function is a wrapper for taskENTER_CRITICAL() in SafeRTOS.
+ * Enables a task to enter critical section.
+ * Has no input arguments and returns none.
+ *
+ * @pre
+ * - Called from a non-interrupt context
+ */
+static inline void
+rtosTaskEnterCritical(void)
+{
+    safertosapiENTER_CRITICAL();
+}
+
+/**
+ * @brief Exit critical section
+ *
+ * This function is a wrapper for taskEXIT_CRITICAL() in SafeRTOS.
+ * Enables a task to exit from critical section.
+ * Has no input arguments and returns none.
+ *
+ * @pre
+ * - RTOS state must already be in critical section
+ *
+ * - Called from a non-interrupt context
+ */
+static inline void
+rtosTaskExitCritical(void)
+{
+   safertosapiEXIT_CRITICAL();
+}
+
+/**
+ * @brief Mask required interrupts from ISR
+ *
+ * This function is a wrapper for taskSET_INTERRUPT_MASK_FROM_ISR() in SafeRTOS.
+ * Sets the interrupt mask to mask all interrupts at the
+ * configSYSTEM_INTERRUPT_PRIORITY or lower. This prevents any interrupts that
+ * call a system API function from interrupting the current interrupt handler
+ * It has significance only if interrupt nesting is supported on port.
+ * Input arguments none.
+ *
+ * @pre
+ * - Called only in interrupt context
+ *
+ * @retval uxOriginalInterruptState Original interrupt mask.
+ */
+static inline rtosInterruptState
+rtosTaskSetInterruptMaskFromISR(void)
+{
+    return safertosapiSET_INTERRUPT_MASK_FROM_ISR();
+}
+
+/**
+ * @brief Unmask required interrupts from ISR
+ *
+ * This function is wrapper for taskCLEAR_INTERRUPT_MASK_FROM_ISR() in SafeRTOS.
+ * It clears interrupt mask set using rtosTaskSetInterruptMaskFromISR
+ * and retrieves the original mask based on input argument. Returns none.
+ *
+ * @pre
+ * - Called only in interrupt context
+ *
+ * @param[in] uxOriginalInterruptState Original interrupt mask
+ */
+static inline void
+rtosTaskClearInterruptMaskFromISR(rtosInterruptState uxOriginalInterruptState)
+{
+    safertosapiCLEAR_INTERRUPT_MASK_FROM_ISR(uxOriginalInterruptState);
+}
+
+/**
+ * @brief Retrieve scheduler status
+ *
+ * This function is a wrapper for xTaskIsSchedulerStarted() in SafeRTOS.
+ * Checks and returns true if there has been a successful call to
+ * rtosTaskStartScheduler()
+ * No input arguments
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * @retval rtosTRUE  Scheduler has been started
+ * @retval rtosFALSE Otherwise
+ */
+static inline rtosBool
+rtosTaskIsSchedulerStarted(void)
+{
+    return (rtosBool)xTaskIsSchedulerStarted();
+}
+
+/**
+ * @brief Retrieve scheduler status from ISR
+ *
+ * This function is a wrapper for xTaskIsSchedulerStartedFromISR() in SafeRTOS
+ * Checks and returns true if there has been a successful call to
+ * rtosTaskStartScheduler()
+ * No input arguments
+ *
+ * @pre
+ * - Called from an interrupt context
+ *
+ * @retval rtosTRUE  Scheduler has been started
+ * @retval rtosFALSE Otherwise
+ */
+static inline rtosBool
+rtosTaskIsSchedulerStartedFromISR(void)
+{
+    return (rtosBool)xTaskIsSchedulerStartedFromISRKrnl();
+}
+
+/**
+ * @brief Wait for notification from a calling task with timeout
+ *
+ * This function is a wrapper for xTaskNotifyWait() in SafeRTOS
+ * Each task has a notification value which is initialized to 0 when it is
+ * created.
+ * It blocks the calling task for notification from another task.
+ *
+ * @pre
+ * - A task has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] uxBitsToClearOnEntry    Bitmask to clear bits in the receiving
+ *                                    task notification value on entering wait.
+ *                                    Length of the bitmask is 32 bits
+ * @param[in] uxBitsToClearOnExit     Bitmask to clear bits in the receiving
+ *                                    task notification value before exiting wait
+ *                                    Length of the bitmask is 32 bits
+ * @param[in] xTicksToWait            Timeout in ticks to wait for notification
+ * @param[out] puxNotificationValue   Pointer to receiving task notification
+ *                                    value. Value at this pointer is updated
+ *                                    with calling task notification value as it
+ *                                    was before clearing the bits using
+ *                                    uxBitsToClearOnExit.
+ *
+ * @retval rtosPASS                         on success
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED    Scheduler is suspended.
+ * @retval E_RTOS_NOTIFICATION_NOT_RECEIVED No notification has been received
+ * @retval E_RTOS_INVALID_DATA_RANGE        Error writing data to the output
+ *                                          parameter
+ */
+static inline rtosError
+rtosTaskNotifyWait(rtosTaskNotifyBits uxBitsToClearOnEntry,
+                   rtosTaskNotifyBits uxBitsToClearOnExit,
+                   rtosTaskNotifyValue *puxNotificationValue,
+                   rtosTick xTicksToWait)
+{
+    return xTaskNotifyWait(uxBitsToClearOnEntry,
+                           uxBitsToClearOnExit,
+                           puxNotificationValue,
+                           xTicksToWait);
+}
+
+/**
+ * @brief Send notification to waiting task.
+ *
+ * This function is wrapper for rtosTaskNotifySend() in SafeRTOS.
+ * Each task has a notification value which is initialized to 0 when it is
+ * created.
+ * The function sends notification to a waiting task and updates the receiving
+ * task's notification as per the set criteria and value sent as an argument.
+ *
+ * Each task can take one of the following notification states:
+ *
+ *  - rtosNotification_NOT_WAITING - Not waiting for any notification from other
+ *                                   task
+ *
+ *  - rtosNotification_WAITING - Task is waiting for some notification
+ *
+ *  - rtosNotification_NOTIFIED - Task has sent a notification.
+ *
+ * Receiving task notification value can be updated using following criteria:
+ *
+ *  - rtosNotification_NO_ACTION Do not update task notification value
+ *
+ *  - rtosNotification_SET_BITS Set task notification value by ORing with uxValue
+ *
+ *  - rtosNotification_INCREMENT Increment the task notification value
+ *
+ *  - rtosNotification_SET_VALUE_WITH_OVERWRITE Copy uxValue to notification
+ *                                              value even if the previous value
+ *                                              has not been read by the task.
+ *
+ *  - rtosNotification_SET_VALUE_WITHOUT_OVERWRITE Set the receiving task's
+ *                                                 notification value only if
+ *                                                 there is no notification
+ *                                                 pending.
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Another task is waiting for some notification.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xTaskToNotify Handle of waiting task
+ * @param[in] uxValue       Notification value to be updated for receiving task
+ * @param[in] xAction       Receiving task notification update criteria
+ *
+ * @retval rtosPASS                            on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED      Null receiving task handle
+ * @retval E_RTOS_INVALID_TASK_HANDLE          Invalid task handle
+ * @retval E_RTOS_INVALID_PARAMETERS           Invalid notification value/action
+ * @retval E_RTOS_NOTIFICATION_ALREADY_PENDING Notification pending
+ */
+static inline rtosError
+rtosTaskNotifySend(rtosTaskHandle xTaskToNotify,
+                   rtosTaskNotifyAction xAction,
+                   rtosTaskNotifyValue uxValue)
+{
+    return xTaskNotifySend(xTaskToNotify,
+                           xAction,
+                           uxValue);
+}
+
+/**
+ * @brief Send notification to waiting task from ISR.
+ *
+ * This function is a wrapper for rtosTaskNotifySendFromISR() in SafeRTOS.
+ * Each task has a notification value which is initialized to 0 when it is
+ * created.
+ * It sends notification to a waiting task and updates
+ * receiving task's notification as per the set criteria and value sent as an
+ * argument.
+ *
+ * Each task can take one of the following notification states:
+ *
+ *  - rtosNotification_NOT_WAITING - Not waiting for any notification from other
+ *                    task
+ *
+ *  - rtosNotification_WAITING - Task is waiting for some notification
+ *
+ *  - rtosNotification_NOTIFIED - Task has sent a notification.
+ *
+ * Receiving task notification value can be updated using following criteria:
+ *
+ *  - rtosNotification_NO_ACTION Do not update task notification value
+ *
+ *  - rtosNotification_SET_BITS Set task notification value as per uxValue
+ *
+ *  - rtosNotification_INCREMENT Increment the task notification value
+ *
+ *  - rtosNotification_SET_VALUE_WITH_OVERWRITE Update task notification value
+ *                                              even if the previous
+ *                                              notification is pending.
+ *
+ *  - rtosNotification_SET_VALUE_WITHOUT_OVERWRITE Set the task's notification
+ *                                                 only if there is no pending
+ *                                                 notification
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Another task is waiting for some notification.
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xTaskToNotify              Handle of waiting task
+ * @param[in] uxValue                    Notification value to be updated
+ *                                       for receiving task
+ * @param[in] xAction                    Notification update criteria
+ * @param[in] pxHigherPriorityTaskWoken  An in/out parameter that is set if
+ *                                       calling this function wakes an higher or
+ *                                       equal priority task
+ *
+ * @retval rtosPASS                            on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED      Null receiving task handle
+ * @retval E_RTOS_INVALID_TASK_HANDLE          Invalid task handle
+ * @retval E_RTOS_INVALID_PARAMETERS           Invalid notification value/action
+ * @retval E_RTOS_NOTIFICATION_ALREADY_PENDING Notification pending
+ * @retval E_RTOS_INVALID_DATA_RANGE           Error writing data to the output
+ *                                             parameter
+ */
+static inline rtosError
+rtosTaskNotifySendFromISR(rtosTaskHandle xTaskToNotify,
+                          rtosTaskNotifyAction xAction,
+                          rtosTaskNotifyValue uxValue,
+                          rtosBool *pxHigherPriorityTaskWoken)
+{
+    UNUSED(pxHigherPriorityTaskWoken);
+    return xTaskNotifySendFromISR(xTaskToNotify,
+                                  xAction,
+                                  uxValue);
+}
+
+/**
+ * @brief Generate system tick
+ *
+ * This function is a wrapper for vTaskProcessSystemTickFromISR() in SafeRTOS.
+ * It is used to generate system tick and should be called from the
+ * system tick handler.
+ *
+ * @pre
+ * - Scheduler has been started.
+ *
+ * - Called from a non-interrupt context
+ *
+ * Has no input arguments and returns none.
+ */
+static inline void rtosSystemTickHandler(void)
+{
+    vTaskProcessSystemTickFromISR();
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-timer.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-timer.h
new file mode 100644
index 0000000..3659478
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-timer.h
@@ -0,0 +1,413 @@
+/* Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_TIMER_H
+#define OSA__OSA_TIMER_H
+#define FSP__OSA__OSA_TIMER_H                           1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "ospl/rtos-port.h"
+                                        // for rtosTimerHandle, rtosTick, rtosBool, FSP...
+#include <queueAPI.h>                   // IWYU pragma: keep
+                                        // for xQueueHandle
+#include <timersAPI.h>                  // IWYU pragma: export
+                                        // IWYU pragma: no_include "timersAPI.h"
+                                        // for xTimerChangePeriodFromISR, xTimerSt...
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__OSPL__RTOS_PORT_H, "Header file missing or invalid.")
+#endif
+
+/**
+ * @brief Computes the size of pre-allocated memory required for timer control
+ * block
+ *
+ * @retval NumberOfBytes Size of Timer control block
+ */
+#define rtosTimerCBSize()     rtosTIMER_CONTROL_BLOCK_OVERHEAD_BYTES
+
+/**
+ * @brief Computes the size of pre-allocated memory required for timer parameter
+ * structure supplied as an input to rtosTimerCreate.
+ *
+ * @retval NumberOfBytes Size of timer instance parameters structure
+ */
+#define rtosTimerInstanceParametersSize() \
+                                     rtosTIMER_INSTANCE_PARAMETER_OVERHEAD_BYTES
+
+/**
+ * @brief Create a timer.
+ *
+ * This function is a wrapper for xTimerCreate() in SafeRTOS.
+ * It updates the handle sent as
+ * an argument to point to the newly created timer
+ *
+ * @pre
+ * - A valid buffer, r/w accessible to the RTOS kernel at all times has been
+ * pre-allocated to handle timer control block and instance parameters
+ *
+ * - Called from a non-interrupt context
+ *
+ * @param[in] pxTimerParameters Pointer to timer init parameter
+ *                              structure (rtosTimerInitParametersType)
+ * @param[out] pxTimerHandle    Pointer to timer handle
+ *
+ * @retval rtosPASS                           on success
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED     Null pointer to timer init
+ *                                            parameter/Timer handle
+ * @retval E_RTOS_INVALID_PARAMETERS          Invalid timer init parameters
+ * @retval E_RTOS_INVALID_TIMER_TASK_INSTANCE Invalid timer task instance
+ * @retval E_RTOS_TIMER_ALREADY_IN_USE        Input Timer init parameter
+ *                                            already has a timer instance associated
+ *                                            with it.
+ * @retval E_RTOS_INVALID_DATA_RANGE          Error writing data to the memory buffer
+ */
+rtosError
+rtosTimerCreate(const rtosTimerInitParametersType *const pxTimerParameters,
+                rtosTimerHandle *pxTimerHandle);
+
+/**
+ * @brief Start a timer
+ *
+ * This function is a wrapper for xTimerStart() in SafeRTOS.
+ * Calling task is held in blocked state for block time before successfully
+ * sending the start command to the timer
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xTimer     Timer handle
+ * @param[in] xBlockTime Block time in ticks
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_TIMER_HANDLE    Invalid timer handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null timer handle passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler is suspended
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ * @retval E_RTOS_QUEUE_FULL              Timer command queue is full and
+ */
+static inline rtosError
+rtosTimerStart(rtosTimerHandle xTimer,
+               rtosTick xBlockTime)
+{
+    return xTimerStart(xTimer, xBlockTime);
+}
+
+/**
+ * @brief Stop a timer
+ *
+ * This function is a wrapper for xTimerStop() in SafeRTOS.
+ * Calling task is held in blocked state for block time before successfully
+ * sending stop command to the timer
+ *
+ * @pre
+ * - Referred timer has been started
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xTimer     Timer handle
+ * @param[in] xBlockTime Block time in ticks
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_TIMER_HANDLE    Invalid timer handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null timer handle passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler suspended
+ * @retval E_RTOS_QUEUE_FULL              Timer command queue is full and
+ *                                        cannot accept new requests
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ */
+static inline rtosError
+rtosTimerStop(rtosTimerHandle xTimer,
+              rtosTick xBlockTime)
+{
+    return xTimerStop(xTimer, xBlockTime);
+}
+
+/**
+ * @brief Change timer period
+ *
+ * This function is a wrapper for xTimerChangePeriod() in SafeRTOS.
+ * Calling task is held in blocked state for block time before successfully
+ * sending change period command to the timer
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xTimer            Timer handle
+ * @param[in] xBlockTime        Block time in ticks
+ * @param[in] xNewPeriodInTicks New timer period in ticks. Should be
+ *                              greater than 0.
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_TIMER_HANDLE    Invalid timer handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null timer handle passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler suspended
+ * @retval E_RTOS_QUEUE_FULL              Timer command queue is full and
+ *                                        cannot accept new requests
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ */
+static inline rtosError
+rtosTimerChangePeriod(rtosTimerHandle xTimer,
+                      rtosTick xNewPeriodInTicks,
+                      rtosTick xBlockTime)
+{
+    return xTimerChangePeriod(xTimer, xNewPeriodInTicks, xBlockTime);
+}
+
+/**
+ * @brief Delete a timer
+ *
+ * This function is a wrapper for xTimerDelete() in SafeRTOS.
+ * Calling task is held in blocked state for block time before successfully
+ * sending delete command to the timer
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xTimer     Timer handle
+ * @param[in] xBlockTime Block time in ticks
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_TIMER_HANDLE    Invalid timer handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null timer handle passed
+ * @retval E_RTOS_SCHEDULER_IS_SUSPENDED  Scheduler suspended
+ * @retval E_RTOS_QUEUE_FULL              Timer command queue is full and
+ *                                        cannot accept new requests
+ * @retval E_RTOS_ERRONEOUS_UNBLOCK       Error while unblocking the owner task
+ */
+static inline rtosError
+rtosTimerDelete(rtosTimerHandle xTimer,
+                rtosTick xBlockTime)
+{
+    return xTimerDelete(xTimer, xBlockTime);
+}
+
+// ISR friendly commands of the timer commands
+
+/**
+ * @brief Start a timer from ISR
+ *
+ * This function is a wrapper for xTimerStartFromISR() in SafeRTOS.
+ * It sets value at pxHigherPriorityTaskWoken if calling this function
+ * unblocks the timer service whose priority is equal to/higher than
+ * the current task
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xTimer                     Timer handle
+ * @param[out] pxHigherPriorityTaskWoken Pointer to rtosBool variable
+ *                                       to indicate current context
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_TIMER_HANDLE    Invalid timer handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null timer handle passed
+ * @retval E_RTOS_QUEUE_FULL              Timer command queue is full and
+ *                                        cannot accept new requests
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error writing data to the output parameter
+ */
+static inline rtosError
+rtosTimerStartFromISR(rtosTimerHandle xTimer,
+                      rtosBool *pxHigherPriorityTaskWoken)
+{
+    UNUSED(pxHigherPriorityTaskWoken);
+    return xTimerStartFromISR(xTimer);
+}
+
+/**
+ * @brief Stop a timer from ISR
+ *
+ * This function is a wrapper for xTimerStopFromISR() in SafeRTOS.
+ * It sets value at pxHigherPriorityTaskWoken if calling this function unblocks
+ * the timer service whose priority is equal to/higher than the current task
+ *
+ * @pre
+ * - Referred timer has been started
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xTimer                     Timer handle
+ * @param[out] pxHigherPriorityTaskWoken Pointer to rtosBool variable
+ *                                       to indicate current context
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_TIMER_HANDLE    Invalid timer handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null timer handle passed
+ * @retval E_RTOS_QUEUE_FULL              Timer command queue is full and
+ *                                        cannot accept new requests
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error writing data to the output parameter
+ */
+static inline rtosError
+rtosTimerStopFromISR(rtosTimerHandle xTimer,
+                     rtosBool *pxHigherPriorityTaskWoken)
+{
+    UNUSED(pxHigherPriorityTaskWoken);
+    return xTimerStopFromISR(xTimer);
+}
+
+/**
+ * @brief Change timer period from ISR
+ *
+ * This function is a wrapper for xTimerChangePeriodFromISR() in SafeRTOS.
+ * It sets value at pxHigherPriorityTaskWoken if calling this function unblocks
+ * the timer service whose priority is equal to/higher than the current task
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Scheduler has been started.
+ *
+ * - Called from an interrupt context.
+ *
+ * @param[in] xTimer                     Timer handle
+ * @param[in] xNewPeriodInTicks          New timer period in ticks. Should be
+ *                                       greater than 0.
+ * @param[out] pxHigherPriorityTaskWoken Pointer to rtosBool variable
+ *                                       to indicate current context
+ *
+ * @retval rtosPASS                       on success
+ * @retval E_RTOS_INVALID_TIMER_HANDLE    Invalid timer handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null timer handle passed
+ * @retval E_RTOS_QUEUE_FULL              Timer command queue is full and
+ *                                        cannot accept new requests
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error writing data to the output parameter
+ */
+static inline rtosError
+rtosTimerChangePeriodFromISR(rtosTimerHandle xTimer,
+                             rtosTick xNewPeriodInTicks,
+                             rtosBool *pxHigherPriorityTaskWoken)
+{
+    UNUSED(pxHigherPriorityTaskWoken);
+    return xTimerChangePeriodFromISR(xTimer, xNewPeriodInTicks);
+}
+
+/**
+ * @brief Check if timer is active
+ *
+ * This function is a wrapper for xTimerIsTimerActive() in SafeRTOS.
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in] xTimer Timer handle
+ *
+ * @retval rtosTRUE                    if timer is active or exists in the
+ *                                     overflow timer list
+ * @retval rtosFALSE                   Timer not present in the active timer
+ *                                     list
+ * @retval E_RTOS_INVALID_TIMER_HANDLE Invalid timer handle
+ */
+static inline rtosError
+rtosTimerIsTimerActive(rtosTimerHandle xTimer)
+{
+    return xTimerIsTimerActive(xTimer);
+}
+
+/**
+ * @brief Get timer ID
+ *
+ * This function is a wrapper for xTimerGetTimerID() in SafeRTOS.
+ * It updates value at pxTimerID with ID of the requested timer
+ * configured by the host application while creating it.
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Called from a non-interrupt context.
+ *
+ * @param[in]  xTimer    Timer handle
+ * @param[out] pxTimerID Pointer to timer ID
+ *
+ * @retval rtosPASS                       for valid timers
+ * @retval E_RTOS_INVALID_TIMER_HANDLE    Invalid timer handle
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED Null pointer referring to timer ID
+ * @retval E_RTOS_INVALID_DATA_RANGE      Error writing data to the output parameter
+ */
+static inline rtosError
+rtosTimerGetTimerID(rtosTimerHandle xTimer, rtosTimerIDType *pxTimerID)
+{
+    return xTimerGetTimerID(xTimer, pxTimerID);
+}
+
+/**
+ * @brief Get timer local storage object
+ *
+ * This function is a wrapper for xTimerTLSObjectGet() in SafeRTOS.
+ * On success, this function returns pointer to timer local storage
+ * object defined in timer init parameters.
+ *
+ * @pre
+ * - A timer has been created with a valid handle referring to it.
+ *
+ * - Called from a timer callback function
+ *
+ * @param[in] xTimer Timer handle
+ *
+ * @retval NULL     for failure
+ * @retval TimerLSO Pointer to timer local storage object on success
+ */
+static inline rtosTimerLocalStorageObject
+rtosTimerTLSObjectGet(rtosTimerHandle xTimer)
+{
+    return pvTimerTLSObjectGet(xTimer);
+}
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-values.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-values.h
new file mode 100644
index 0000000..d60d9d1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/osa-values.h
@@ -0,0 +1,140 @@
+/* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef OSA__OSA_VALUES_H
+#define OSA__OSA_VALUES_H
+#define FSP__OSA__OSA_VALUES_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <ospl/rtos-port.h>             // for rtosMutexHandle, FSP__OSPL__RTOS_PORT_H
+#include <eventGroupsAPI.h>             // for evgrpCLEAR_EVENTS_ON_EXIT_BIT, evgrpWAIT_FO...
+#include <taskAPI.h>                    // for taskNOTIFICATION_NO_ACTION
+#include <semaphoreAPI.h>               // for semSEM_GIVE_BLOCK_TIME
+#include <evtmplxAPI.h>                 // for evtmplxQUEUE_MESSAGE_WAITING, ...
+#include <projdefs.h>                   // for pdTRUE, pdFALSE
+
+/**
+ * @defgroup RTOS_VALUES Mapping of SafeRTOS values to RTOS value space
+ * @{
+ */
+/** Defines true state of a Boolean variable */
+#define rtosTRUE                                ((rtosBool)pdTRUE)
+/** Defines false state of a Boolean variable */
+#define rtosFALSE                               ((rtosBool)pdFALSE)
+/** Defines return value indicating success */
+#define rtosPASS                                pdPASS
+/** Defines return value indicating failure */
+#define rtosFAIL                                pdFAIL
+/** @} */
+
+/**
+ * @defgroup RTOS_KERNEL_VERSION Mapping of SafeRTOS kernel version values to RTOS value space
+ * @{
+ */
+/** Defines kernel major version number */
+#define rtosKERNEL_MAJOR_VERSION                pdKERNEL_MAJOR_VERSION
+/** Defines kernel minor version number */
+#define rtosKERNEL_MINOR_VERSION                pdKERNEL_MINOR_VERSION
+/** @} */
+
+/**
+ * @defgroup RTOS_EVENT_GROUP_VALUES Mapping of SafeRTOS event group values to RTOS value space
+ * @{
+ */
+/** Defines bitmask mapped to eventgroup control flag set to clear event group bits on exit */
+#define rtosEVENTGRP_CLEAR_EVENTS_ON_EXIT       evgrpCLEAR_EVENTS_ON_EXIT_BIT
+/** Defines bitmask mapped to eventgroup control flag, set to wait until all the requested event group bits are set*/
+#define rtosEVENTGRP_WAIT_FOR_ALL_BITS          evgrpWAIT_FOR_ALL_BITS
+/** @} */
+
+/**
+ * @defgroup RTOS_MUTEX_VALUES Mapping of SafeRTOS mutex values to RTOS value space
+ * @{
+ */
+/** Defines state of a mutex object indicating lock is available */
+#define rtosMUTEX_TAKEN                         mutexTAKEN
+/** Defines state of a mutex object indicating lock is acquired */
+#define rtosMUTEX_AVAILABLE                     mutexAVAILABLE
+/** @} */
+
+/**
+ * Defines macro to be used for setting semaphore block time as 0.
+ */
+#define rtosSEMA_GIVE_NOBLOCK                   semSEM_GIVE_BLOCK_TIME
+
+/**
+ * @defgroup RTOS_TASK_VALUES Mapping of SafeRTOS task values to RTOS value space
+ * @{
+ */
+/** Sending task shall use this macro if no update is needed to the receiving task  notification value */
+#define rtosNotification_NO_ACTION                      taskNOTIFICATION_NO_ACTION
+/** Sending task shall use this  macro to update notification value of receiving task by  ORing it with the sent value of the receiving task */
+#define rtosNotification_SET_BITS                       taskNOTIFICATION_SET_BITS
+/** Sending task shall use this macro to increment notification value of the receiving task */
+#define rtosNotification_INCREMENT                      taskNOTIFICATION_INCREMENT
+/** Sending task shall use this macro to set notification value of the receiving task with overwrite even if the previous notification is pending
+*/
+#define rtosNotification_SET_VALUE_WITH_OVERWRITE       taskNOTIFICATION_SET_VALUE_WITH_OVERWRITE
+/** Sending task shall use this macro to set notification value of the receiving task only if there is no previous notification pending */
+#define rtosNotification_SET_VALUE_WITHOUT_OVERWRITE    taskNOTIFICATION_SET_VALUE_WITHOUT_OVERWRITE
+/**  Defines state of a task indicating it's not waiting for any notification*/
+#define rtosNotification_NOT_WAITING                    taskNOTIFICATION_NOT_WAITING
+/** Defines state of a task indicating it's waiting for a notification */
+#define rtosNotification_WAITING                        taskNOTIFICATION_WAITING
+/** Defines state of a task indicating it has sent the notification */ 
+#define rtosNotification_NOTIFIED                       taskNOTIFICATION_NOTIFIED
+/** Defines priority of an idle task */
+#define rtosIDLE_PRIORITY                               taskIDLE_PRIORITY
+/** @} */
+
+/**
+ * @defgroup RTOS_EVENTPOLL_VALUES Mapping of SafeRTOS event poll values to RTOS value space
+ * @{
+ */
+/** Defines event for a queue object indicating the queue contains at least one message waiting to be received */
+#define rtosEventPollQUEUE_MESSAGE_WAITING         evtmplxQUEUE_MESSAGE_WAITING
+/** Defines event for a queue object indicating the queue has space for at least one message to be sent*/
+#define rtosEventPollQUEUE_SPACE_AVAILABLE         evtmplxQUEUE_SPACE_AVAILABLE
+/** Defines event for a semaphore object indicating it is available*/
+#define rtosEventPollSEMAPHORE_AVAILABLE           evtmplxSEMAPHORE_AVAILABLE
+/** Defines event for a mutex object indicating it is available*/
+#define rtosEventPollMUTEX_AVAILABLE               evtmplxMUTEX_AVAILABLE
+/** Defines event for a task indicating it has received a notification */
+#define rtosEventPollTASK_NOTIFICATION_RECEIVED    evtmplxTASK_NOTIFICATION_RECEIVED
+/** Defines event for an eventgroup object indicating requested eventgroup bits are set*/
+#define rtosEventPollEVENT_GROUP_BITS_SET          evtmplxEVENT_GROUP_BITS_SET
+/** @} */
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/sections-osa.h b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/sections-osa.h
new file mode 100644
index 0000000..ade0011
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/osa/safertosv9/osa/sections-osa.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef OSA__SECTIONS_OSA_H
+#define OSA__SECTIONS_OSA_H
+#define FSP__OSA__SECTIONS_OSA_H                        0
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_OSA_DATA           SECTION_BUILDER(osa,                    data)
+#define SECTION_NAME_OSA_RODATA         SECTION_BUILDER(osa,                    rodata)
+#define SECTION_NAME_OSA_TEXT           SECTION_BUILDER(osa,                    text)
+#define SECTION_NAME_OSA_CREATE_TEXT    SECTION_BUILDER(create.osa,             text)
+#define SECTION_NAME_OSA_INIT_DATA      SECTION_BUILDER(init.osa,               data)
+#define SECTION_NAME_OSA_INIT_TEXT      SECTION_BUILDER(init.osa,               text)
+
+#define SECTION_STR_OSA_TEXT            STR(SECTION_NAME_OSA_TEXT)
+#define SECTION_STR_OSA_RODATA          STR(SECTION_NAME_OSA_RODATA)
+#define SECTION_STR_OSA_DATA            STR(SECTION_NAME_OSA_DATA)
+#define SECTION_STR_OSA_INIT_TEXT       STR(SECTION_NAME_OSA_INIT_TEXT)
+#define SECTION_STR_OSA_INIT_DATA       STR(SECTION_NAME_OSA_INIT_DATA)
+#define SECTION_STR_OSA_CREATE_TEXT     STR(SECTION_NAME_OSA_CREATE_TEXT)
+
+#define SECTION_OSA_TEXT                SECTION(SECTION_STR_OSA_TEXT)
+#define SECTION_OSA_RODATA              SECTION(SECTION_STR_OSA_RODATA)
+#define SECTION_OSA_DATA                SECTION(SECTION_STR_OSA_DATA)
+#define SECTION_OSA_INIT_TEXT           SECTION(SECTION_STR_OSA_INIT_TEXT)
+#define SECTION_OSA_INIT_DATA           SECTION(SECTION_STR_OSA_INIT_DATA)
+#define SECTION_OSA_CREATE_TEXT         SECTION(SECTION_STR_OSA_CREATE_TEXT)
+
+#endif
+
diff --git a/spe-freertos-bsp/fsp/source/include/scp/scp-errors.h b/spe-freertos-bsp/fsp/source/include/scp/scp-errors.h
new file mode 100644
index 0000000..974d2dd
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/scp/scp-errors.h
@@ -0,0 +1,117 @@
+/**
+ * @file    scp-errors.h
+ *
+ * @brief   Error codes specific to the SCP module.
+ *
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SCP__SCP_ERRORS_H
+#define SCP__SCP_ERRORS_H
+#define FSP__SCP__SCP_ERRORS_H 1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for HEADER_CHECK
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>             // for MODULE_ERROR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The HEADER_CHECK macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+HEADER_CHECK(FSP__BASE__MODULE_ID_H)
+
+
+/**
+ * @brief Error codes specific to the SCP module.
+ *
+ * @macro-title SCP error codes.
+ *
+ * @E_SCP_INSUFFICIENT_RESOURCES    The caller is operating in secure mode but
+ *                                  access to secret-index zero is blocked.
+ * @E_SCP_INVALID_ADDRESS           A passed buffer is misaligned, or two
+ *                                  buffers overlap (when not permitted).
+ * @E_SCP_INVALID_BASE              A passed buffer resides in an unsupported
+ *                                  memory region.
+ * @E_SCP_INVALID_DMA_SPECIFIER     The caller has requested an operation that
+ *                                  requires a shortcut transfer but the
+ *                                  shortcut-DMA path has not been configured.
+ * @E_SCP_INVALID_FLAGS             The passed combination of flags is invalid.
+ * @E_SCP_INVALID_INDEX             A passed index value falls outside of its
+ *                                  supported range.
+ * @E_SCP_INVALID_LOCK_STATE        SCP lockdown is misconfigured.
+ * @E_SCP_INVALID_OBJECT            A passed compound argument is invalid.
+ * @E_SCP_INVALID_OBJECT_BUFFER     A passed compound argument contains an
+ *                                  invalid buffer element.
+ * @E_SCP_INVALID_OPERATION         The caller has requested an unrecognized
+ *                                  operation, or is attempting to perform a
+ *                                  recognized operation incorrectly.
+ * @E_SCP_INVALID_POINTER           A passed address is zero/NULL (when not
+ *                                  permitted).
+ * @E_SCP_INVALID_REQUEST           The caller has made a request that cannot be
+ *                                  serviced by the driver.
+ * @E_SCP_NOT_READY                 The SCP driver has not been initialized.
+ * @E_SCP_OUT_OF_RANGE              A passed buffer is of invalid size.
+ * @E_SCP_FEATURE_NOT_ENABLED       The requested operation requires the use of
+ *                                  a feature that has not been enabled.
+ * @E_SCP_GENERIC                   An unexpected error occurred.
+ * @E_SCP_NOTHING_TO_DO             The caller has requested an operation that
+ *                                  has no effect.
+ */
+#define E_SCP_INSUFFICIENT_RESOURCES    MODULE_ERROR(SCP,  0UL)
+#define E_SCP_INVALID_ADDRESS           MODULE_ERROR(SCP,  1UL)
+#define E_SCP_INVALID_BASE              MODULE_ERROR(SCP,  2UL)
+#define E_SCP_INVALID_DMA_SPECIFIER     MODULE_ERROR(SCP,  3UL)
+#define E_SCP_INVALID_FLAGS             MODULE_ERROR(SCP,  4UL)
+#define E_SCP_INVALID_INDEX             MODULE_ERROR(SCP,  5UL)
+#define E_SCP_INVALID_LOCK_STATE        MODULE_ERROR(SCP,  6UL)
+#define E_SCP_INVALID_OBJECT            MODULE_ERROR(SCP,  7UL)
+#define E_SCP_INVALID_OBJECT_BUFFER     MODULE_ERROR(SCP,  8UL)
+#define E_SCP_INVALID_OPERATION         MODULE_ERROR(SCP,  9UL)
+#define E_SCP_INVALID_POINTER           MODULE_ERROR(SCP, 10UL)
+#define E_SCP_INVALID_REQUEST           MODULE_ERROR(SCP, 11UL)
+#define E_SCP_NOT_READY                 MODULE_ERROR(SCP, 12UL)
+#define E_SCP_OUT_OF_RANGE              MODULE_ERROR(SCP, 13UL)
+#define E_SCP_FEATURE_NOT_ENABLED       MODULE_ERROR(SCP, 14UL)
+#define E_SCP_GENERIC                   MODULE_ERROR(SCP, 15UL)
+#define E_SCP_NOTHING_TO_DO             MODULE_ERROR(SCP, 16UL)
+
+#endif /* SCP__SCP_ERRORS_H */
diff --git a/spe-freertos-bsp/fsp/source/include/scp/scp.h b/spe-freertos-bsp/fsp/source/include/scp/scp.h
new file mode 100644
index 0000000..1f42849
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/scp/scp.h
@@ -0,0 +1,84 @@
+/**
+ * @file        scp.h
+ *
+ * @brief       Interfaces for the Security Co-Processor (SCP).
+ *
+ * @details     This is the top-level header file for the libFSP SCP
+ *              driver, which provides access to all supported SCP
+ *              functionality. For more information, please refer to the driver
+ *              documentation at https://confluence.nvidia.com/x/9y6gJQ.
+ *
+ * @note        Client applications should include only this top-level file
+ *              and should not directly include any other SCP headers.
+ *
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SCP__SCP_H
+#define SCP__SCP_H
+#define FSP__SCP__SCP_H 1
+
+#if !NVRISCV_FEATURE_SCP
+#error "This header cannot be used because the SCP driver is disabled."
+#endif // !NVRISCV_FEATURE_SCP
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for HEADER_CHECK
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <scp/scp-errors.h>
+#include <scp/scp_common.h>
+#include <scp/scp_crypt.h>
+#include <scp/scp_direct.h>
+#include <scp/scp_general.h>
+#include <scp/scp_rand.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The HEADER_CHECK macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+HEADER_CHECK(FSP__SCP__SCP_ERRORS_H)
+HEADER_CHECK(FSP__SCP__SCP_COMMON_H)
+HEADER_CHECK(FSP__SCP__SCP_CRYPT_H)
+HEADER_CHECK(FSP__SCP__SCP_DIRECT_H)
+HEADER_CHECK(FSP__SCP__SCP_GENERAL_H)
+HEADER_CHECK(FSP__SCP__SCP_RAND_H)
+
+#endif // SCP__SCP_H
diff --git a/spe-freertos-bsp/fsp/source/include/scp/scp_common.h b/spe-freertos-bsp/fsp/source/include/scp/scp_common.h
new file mode 100644
index 0000000..cf57751
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/scp/scp_common.h
@@ -0,0 +1,83 @@
+/**
+ * @file        scp_common.h
+ * @brief       Common SCP types and constants.
+ *
+ * @details     Contains all symbols not otherwise belonging to any specific
+ *              subcomponent of the SCP driver.
+ *
+ * @note        Client applications should include scp.h instead of this file.
+ *
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SCP__SCP_COMMON_H
+#define SCP__SCP_COMMON_H
+#define FSP__SCP__SCP_COMMON_H 1
+
+
+/**
+ * @brief The minimum required alignment for SCP buffers.
+ *
+ * The minimum required alignment for input and output buffers passed to
+ * SCP interfaces, in bytes. Note that this alignment only applies to buffer
+ * arguments and not to other interface parameters.
+ */
+#define SCP_BUFFER_ALIGNMENT 16U
+
+
+/**
+ * @brief A collection of enumerated values for referring to specific SCP GPRs.
+ */
+typedef enum scp_register_index_t
+{
+    // Long-form versions to match naming scheme.
+
+    SCP_REGISTER_INDEX_0 = 0,
+    SCP_REGISTER_INDEX_1,
+    SCP_REGISTER_INDEX_2,
+    SCP_REGISTER_INDEX_3,
+    SCP_REGISTER_INDEX_4,
+    SCP_REGISTER_INDEX_5,
+    SCP_REGISTER_INDEX_6,
+    SCP_REGISTER_INDEX_7,
+    SCP_REGISTER_INDEX_COUNT,
+
+    // Short-form versions for brevity.
+
+    SCP_R0 = 0,
+    SCP_R1,
+    SCP_R2,
+    SCP_R3,
+    SCP_R4,
+    SCP_R5,
+    SCP_R6,
+    SCP_R7,
+    SCP_RCOUNT,
+
+} scp_register_index_t;
+
+#endif // SCP__SCP_COMMON_H
diff --git a/spe-freertos-bsp/fsp/source/include/scp/scp_crypt.h b/spe-freertos-bsp/fsp/source/include/scp/scp_crypt.h
new file mode 100644
index 0000000..b96a5a9
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/scp/scp_crypt.h
@@ -0,0 +1,907 @@
+/**
+ * @file    scp_crypt.h
+ * @brief   Cryptographic SCP features.
+ *
+ * @note    Client applications should include scp.h instead of this file.
+ *
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SCP__SCP_CRYPT_H
+#define SCP__SCP_CRYPT_H
+#define FSP__SCP__SCP_CRYPT_H 1
+
+/* Compiler headers */
+#include <stdbool.h>                    // for bool
+#include <stddef.h>                     // for size_t
+#include <stdint.h>                     // for uint8_t, uintptr_t, etc.
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for HEADER_CHECK
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>        // for error_t
+
+/* Module-specific FSP headers */
+#include <scp/scp_common.h>             // for scp_register_index_t
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The HEADER_CHECK macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+HEADER_CHECK(FSP__ERROR__COMMON_ERRORS_H)
+HEADER_CHECK(FSP__SCP__SCP_COMMON_H)
+
+
+/**
+ * @brief Constructs a new key-descriptor with automatic storage duration.
+ *
+ * When a descriptor returned by this macro is passed to scp_Encrypt(),
+ * scp_Decrypt(), or scp_Cmac(), it instructs the callee to use the first
+ * SCP_KEY_SIZE bytes from key_pa as the encryption key for the requested
+ * operation.
+ *
+ * Note that the contents of key_pa are never copied or modified and must remain
+ * valid for the lifetime of the returned key-descriptor.
+ *
+ * @param[in] key_pa The physical address of the input buffer containing the
+ *                   desired raw key. Must be aligned to SCP_BUFFER_ALIGNMENT
+ *                   and contain at least SCP_KEY_SIZE bytes. Supports IMEM and
+ *                   DMEM locations only.
+ *
+ * @return A pointer to the new key-descriptor.
+ */
+#define SCP_KEY_RAW_BUFFER(key_pa) (              \
+    (const scp_key_desc_t *)&(scp_key_desc_t)     \
+    {                                             \
+        .key_type      = SCP_KEY_TYPE_RAW_BUFFER, \
+        .raw_buffer_pa = (uintptr_t)(key_pa),     \
+    }                                             \
+)
+
+/**
+ * @brief Constructs a new key-descriptor with automatic storage duration.
+ *
+ * When a descriptor returned by this macro is passed to scp_Encrypt(),
+ * scp_Decrypt(), or scp_Cmac(), it instructs the callee to use the data located
+ * in the register specified by reg_index as the encryption key for the
+ * requested operation. This mode is intended to support keys pulled in from
+ * KMEM.
+ *
+ * Note that the contents of the register will be cleared following use of the
+ * returned key-descriptor in an encryption, decryption, or CMAC operation.
+ * Additionally, the register's access-control list must permit keying of its
+ * contents in secure contexts, or full access in insecure contexts.
+ *
+ * @param[in] reg_index The index of the SCP register containing the desired
+ *                      raw key. Must be a valid scp_register_index_t value.
+ *
+ * @return A pointer to the new key-descriptor.
+ */
+#define SCP_KEY_RAW_REGISTER(reg_index) (                 \
+    (const scp_key_desc_t *)&(scp_key_desc_t)             \
+    {                                                     \
+        .key_type           = SCP_KEY_TYPE_RAW_REGISTER,  \
+        .raw_register_index = (reg_index),                \
+    }                                                     \
+)
+
+/**
+ * @brief Constructs a new key-descriptor with automatic storage duration.
+ *
+ * When a descriptor returned by this macro is passed to scp_Encrypt(),
+ * scp_Decrypt(), or scp_Cmac(), it instructs the callee to perform AES-ECB
+ * encryption on the first SCP_BLOCK_SIZE bytes from salt_pa, using the
+ * hardware-secret indicated by secret_index as the key. The result of this
+ * procedure is then used as the encryption key for the requested encryption,
+ * decryption, or CMAC operation.
+ *
+ * Note that the contents of salt_pa are never copied or modified and must
+ * remain valid for the lifetime of the returned key-descriptor. Additionally,
+ * the hardware-secret referred to by secret_index must have an access-control
+ * list that permits keying of its contents for the current operating context
+ * (secure or insecure).
+ *
+ * @param[in] secret_index  The index of the hardware-secret to be used in the
+ *                          key-derivation process. Must be a positive integer
+ *                          less than SCP_SECRET_COUNT.
+ *
+ * @param[in] salt_pa       The physical address of the input buffer containing
+ *                          the salt value to be used in the key-derivation
+ *                          process. Must be aligned to SCP_BUFFER_ALIGNMENT
+ *                          and contain at least SCP_BLOCK_SIZE bytes. Supports
+ *                          IMEM and DMEM locations only.
+ *
+ * @return A pointer to the new key-descriptor.
+ */
+#define SCP_KEY_DERIVED_ECB(secret_index, salt_pa) (   \
+    (const scp_key_desc_t *)&(scp_key_desc_t)          \
+    {                                                  \
+        .key_type         = SCP_KEY_TYPE_DERIVED_ECB,  \
+        .ecb_secret_index = (secret_index),            \
+        .ecb_salt_pa      = (uintptr_t)(salt_pa),      \
+    }                                                  \
+)
+
+/**
+ * @brief Constructs a new key-descriptor with automatic storage duration.
+ *
+ * When a descriptor returned by this macro is passed to scp_Encrypt(),
+ * scp_Decrypt(), or scp_Cmac(), it instructs the callee to perform AES-CBC
+ * encryption on the first SCP_BLOCK_SIZE bytes from salt_pa, using the
+ * hardware-secret indicated by secret_index as the key and the first
+ * SCP_BLOCK_SIZE bytes from iv_pa as the initialization vector. The result of
+ * this procedure is then used as the encryption key for the requested
+ * encryption, decryption, or CMAC operation.
+ *
+ * Note that the contents of salt_pa and iv_pa are never copied or modified and
+ * must remain valid for the lifetime of the returned key-descriptor.
+ * Additionally, the hardware-secret referred to by secret_index must have an
+ * access-control list that permits keying of its contents for the current
+ * operating context (secure or insecure).
+ *
+ * @param[in] secret_index  The index of the hardware-secret to be used in the
+ *                          key-derivation process. Must be a positive integer
+ *                          less than SCP_SECRET_COUNT.
+ *
+ * @param[in] salt_pa       The physical address of the input buffer containing
+ *                          the salt value to be used in the key-derivation
+ *                          process. Must be aligned to SCP_BUFFER_ALIGNMENT
+ *                          and contain at least SCP_BLOCK_SIZE bytes. Supports
+ *                          IMEM and DMEM locations only.
+ *
+ * @param[in] iv_pa         The physical address of the input buffer containing
+ *                          the initialization vector to be used in the key-
+ *                          derivation process. Must be aligned to
+ *                          SCP_BUFFER_ALIGNMENT and contain at least
+ *                          SCP_BLOCK_SIZE bytes. Supports IMEM and DMEM
+ *                          locations only.
+ *
+ * @return A pointer to the new key-descriptor.
+ */
+#define SCP_KEY_DERIVED_CBC(secret_index, salt_pa, iv_pa) ( \
+    (const scp_key_desc_t *)&(scp_key_desc_t)               \
+    {                                                       \
+        .key_type         = SCP_KEY_TYPE_DERIVED_CBC,       \
+        .cbc_secret_index = (secret_index),                 \
+        .cbc_salt_pa      = (uintptr_t)(salt_pa),           \
+        .cbc_iv_pa        = (uintptr_t)(iv_pa),             \
+    }                                                       \
+)
+
+/**
+ * @brief Constructs a new key-descriptor with automatic storage duration.
+ *
+ * When a descriptor returned by this macro is passed to scpEncrypt(),
+ * scpDecrypt(), or scpCmac(), it instructs the callee to compute the CMAC of
+ * the first size bytes from message_pa, using the hardware-secret indicated by
+ * secret_index as the key. The result of this procedure is then used as the
+ * encryption key for the requested encryption, decryption, or CMAC operation.
+ *
+ * Per NIST SP 800-108, it is assumed that message_pa contains the requisite
+ * counter, label, context, and length values in the form of a pre-concatenated
+ * bit string. In the event that this string is not a multiple of SCP_BLOCK_SIZE
+ * bytes in length, it is further assumed that the application has applied
+ * padding per the CMAC specification (i.e. by appending 0b10...0) and has
+ * signalled this padding by setting b_padded to true.
+ *
+ * Note that the contents of message_pa are never copied or modified and must
+ * remain valid for the lifetime of the returned key-descriptor. Additionally,
+ * the hardware-secret referred to by secret_index must have an access-control
+ * list that permits keying of its contents for the current operating context
+ * (secure or insecure).
+ *
+ * @param[in] secret_index  The index of the hardware-secret to be used in the
+ *                          key-derivation process. Must be a positive integer
+ *                          less than SCP_SECRET_COUNT.
+ *
+ * @param[in] message_pa    The physical address of the input buffer containing
+ *                          the message to be used in the key-derivation
+ *                          process. Must be aligned to SCP_BUFFER_ALIGNMENT
+ *                          and contain at least size bytes. Supports IMEM and
+ *                          DMEM locations only.
+ *
+ * @param[in] size          The number of bytes to process from message_pa. Must
+ *                          be a nonzero multiple of SCP_BLOCK_SIZE.
+ *
+ * @param[in] b_padded      A boolean value indicating whether the source
+ *                          message contains padding.
+ *
+ * @return A pointer to the new key-descriptor.
+ */
+#define SCP_KEY_DERIVED_CMAC(secret_index, message_pa, size, b_padded) (    \
+    (const scp_key_desc_t *)&(scp_key_desc_t)                               \
+    {                                                                       \
+        .key_type           = SCP_KEY_TYPE_DERIVED_CMAC,                    \
+        .cmac_secret_index  = (secret_index),                               \
+        .cmac_message_pa    = (uintptr_t)(message_pa),                      \
+        .cmac_size          = (size),                                       \
+        .cmac_padded        = (b_padded),                                   \
+    }                                                                       \
+)
+
+/**
+ * @brief The cryptographic block size.
+ *
+ * The size, in bytes, of a single block of data in the context of
+ * cryptographic operations.
+ */
+#define SCP_BLOCK_SIZE 16U
+
+/**
+ * @brief The cryptographic key size.
+ *
+ * The size, in bytes, of an encryption key in the context of cryptographic
+ * operations.
+ */
+#define SCP_KEY_SIZE 16U
+
+/**
+ * @brief The number of hardware secrets supported by the SCP unit.
+ */
+#define SCP_SECRET_COUNT 64U
+
+
+/**
+ * @brief A collection of supported block-cipher modes.
+ */
+typedef enum scp_cipher_mode_t
+{
+    SCP_CIPHER_MODE_ECB,
+    SCP_CIPHER_MODE_CBC,
+    SCP_CIPHER_MODE_CTR,
+} scp_cipher_mode_t;
+
+/**
+ * @brief A collection of supported operating modes for CMAC computations.
+ */
+typedef enum scp_cmac_mode_t
+{
+    SCP_CMAC_MODE_COMPLETE,
+    SCP_CMAC_MODE_PADDED,
+    SCP_CMAC_MODE_PARTIAL,
+} scp_cmac_mode_t;
+
+/**
+ * @brief A structure for describing cryptographic keys.
+ *
+ * A structure for communicating key information to applicable cryptographic
+ * interfaces. Should always be constructed using the provided SCP_KEY_* helper
+ * macros.
+ *
+ * @key_type            The type of key expressed by this key-descriptor.
+ *
+ * @raw_buffer_pa       The physical address of the source buffer containing
+ *                      the key (when key_type is SCP_KEY_TYPE_RAW_BUFFER).
+ *
+ * @raw_register_index  The index of the source register containing the key
+ *                      (when key_type is SCP_KEY_TYPE_RAW_REGISTER).
+ *
+ * @ecb_secret_index    The hardware secret to be used in the key-derivation
+ *                      process (when key_type is SCP_KEY_TYPE_DERIVED_ECB).
+ *
+ * @ecb_salt_pa         The physical address of the salt value to derive from
+ *                      (when key_type is SCP_KEY_TYPE_DERIVED_ECB).
+ *
+ * @cbc_secret_index    The hardware secret to be used in the key-derivation
+ *                      process (when key_type is SCP_KEY_TYPE_DERIVED_CBC).
+ *
+ * @cbc_salt_pa         The physical address of the salt value to derive from
+ *                      (when key_type is SCP_KEY_TYPE_DERIVED_CBC).
+ *
+ * @cbc_iv_pa           The physical address of the initialization vector for
+ *                      CBC (when key_type is SCP_KEY_TYPE_DERIVED_CBC).
+ *
+ * @cmac_secret_index   The hardware secret to be used in the key-derivation
+ *                      process (when key_type is SCP_KEY_TYPE_DERIVED_CMAC).
+ *
+ * @cmac_message_pa     The physical address of the message to derive from
+ *                      (when key_type is SCP_KEY_TYPE_DERIVED_CMAC).
+ *
+ * @cmac_size           The size of the message to derive from (when key_type is
+ *                      SCP_KEY_TYPE_DERIVED_CMAC).
+ *
+ * @cmac_padded         Whether the input message contains padding (when
+ *                      key_type is SCP_KEY_TYPE_DERIVED_CMAC).
+ */
+typedef struct scp_key_desc_t
+{
+    /**
+     * @brief A collection of supported key types.
+     *
+     * See the corresponding SCP_KEY_* helper macros for more information
+     * regarding the different supported key types.
+     */
+    enum scp_key_type_t
+    {
+        SCP_KEY_TYPE_RAW_BUFFER,
+        SCP_KEY_TYPE_RAW_REGISTER,
+
+        SCP_KEY_TYPE_DERIVED_ECB,
+        SCP_KEY_TYPE_DERIVED_CBC,
+        SCP_KEY_TYPE_DERIVED_CMAC,
+    } key_type;
+
+    // Type-specific key information.
+    union
+    {
+        // Information for RAW_BUFFER-type keys.
+        struct
+        {
+            uintptr_t               raw_buffer_pa;
+        };
+
+        // Information for RAW_REGISTER-type keys.
+        struct
+        {
+            scp_register_index_t    raw_register_index;
+        };
+
+        // Information for DERIVED_ECB-type keys.
+        struct
+        {
+            uint8_t                 ecb_secret_index;
+            uintptr_t               ecb_salt_pa;
+        };
+
+        // Information for DERIVED_CBC-type keys.
+        struct
+        {
+            uint8_t                 cbc_secret_index;
+            uintptr_t               cbc_salt_pa;
+            uintptr_t               cbc_iv_pa;
+        };
+
+        // Information for DERIVED_CMAC-type keys.
+        struct
+        {
+            uint8_t                 cmac_secret_index;
+            uintptr_t               cmac_message_pa;
+            size_t                  cmac_size;
+            bool                    cmac_padded;
+        };
+    };
+} scp_key_desc_t;
+
+
+/**
+ * @brief Encrypts an arbitary buffer of data using an AES-128 block cipher.
+ *
+ * Encrypts the first size bytes of data from source_pa using the key described
+ * by p_key_desc and writes the result to dest_pa. Uses an AES-128 block cipher
+ * operating in the mode indicated by cipher_mode as the encryption algorithm.
+ * If applicable, SCP_BLOCK_SIZE bytes from context_pa are used as the initial
+ * contextual input to the cipher.
+ *
+ * Should p_key_desc describe a derived key, the scp_Encrypt() function will
+ * perform the indicated key-derivation operation automatically. See the
+ * relevant SCP_KEY_* macros for details.
+ *
+ * Note that it is permissible for source_pa and dest_pa to reference the same
+ * memory location (i.e. to facilitate encrypting data in-place). However, the
+ * use of buffers that only partially overlap is prohibited and will result in
+ * an error.
+ *
+ * In the event that dest_pa refers to an external memory location, the
+ * application must ensure that it has first called scp_Configure_Shortcut() (or
+ * used the SCP_EXTERNAL_DEST() helper macro) to configure the shortcut-DMA
+ * path accordingly.
+ *
+ * @param[in]  p_key_desc   A pointer to the key-descriptor to be used for the
+ *                          encryption operation. Applications should acquire
+ *                          this parameter through one of the provided
+ *                          SCP_KEY_* macros.
+ *
+ * @param[in]  cipher_mode  The block-cipher mode of operation to use. See the
+ *                          documentation for scp_cipher_mode_t for a list of
+ *                          supported values.
+ *
+ * @param[in]  source_pa    The physical address of the input buffer to be
+ *                          encrypted. Must be aligned to SCP_BUFFER_ALIGNMENT
+ *                          and contain at least size bytes. Supports IMEM and
+ *                          DMEM locations only.
+ *
+ * @param[out] dest_pa      The physical address of the output buffer to which
+ *                          the encrypted data is to be written. Must be
+ *                          aligned to SCP_BUFFER_ALIGNMENT and have at least
+ *                          size bytes of capacity. Permitted to overlap with
+ *                          source_pa only if exactly equal. Supports IMEM,
+ *                          DMEM, and external locations.
+ *
+ * @param[in]  size         The number of bytes to process from source_pa. Must
+ *                          be a nonzero multiple of SCP_BLOCK_SIZE.
+ *
+ * @param[in]  context_pa   The physical address of the input buffer containing
+ *                          the initialization vector (CBC) or initial counter
+ *                          value with nonce (CTR) to be used for the
+ *                          encryption operation. Must be aligned to
+ *                          SCP_BUFFER_ALIGNMENT and contain at least
+ *                          SCP_BLOCK_SIZE bytes. Required to be zero (NULL)
+ *                          for ECB mode. Supports IMEM and DMEM locations
+ *                          only.
+ *
+ * @retval E_SUCCESS                    if data was encrypted successfully.
+ *
+ * @retval E_SCP_NOT_READY              if the SCP driver has not been
+ *                                      initialized.
+ *
+ * @retval E_SCP_INVALID_OBJECT         if p_key_desc does not point to a valid
+ *                                      key-descriptor.
+ *
+ * @retval E_SCP_INVALID_OBJECT_BUFFER  if p_key_desc was constructed with a
+ *                                      zero (NULL) or incorrectly-aligned
+ *                                      address, or a pointer to an unsupported
+ *                                      memory location (e.g. EMEM), or a buffer
+ *                                      that overflows the memory region in
+ *                                      which it resides, or a buffer of invalid
+ *                                      size.
+ *
+ * @retval E_SCP_INVALID_INDEX          if p_key_desc was constructed with an
+ *                                      invalid register or hardware-secret
+ *                                      index, or references secret-index zero.
+ *
+ * @retval E_PERM                       if p_key_desc was constructed with a
+ *                                      hardware-secret index that the
+ *                                      application does not have permission to
+ *                                      use.
+ *
+ * @retval E_SCP_INVALID_POINTER        if one or more of p_key_desc, source_pa,
+ *                                      or dest_pa is zero/NULL, or context_pa
+ *                                      is zero (NULL) and cipher_mode is not
+ *                                      SCP_CIPHER_MODE_ECB.
+ *
+ * @retval E_SCP_INVALID_ADDRESS        if one or more of source_pa, dest_pa, or
+ *                                      context_pa is incorrectly aligned, or
+ *                                      the buffers referenced by source_pa and
+ *                                      dest_pa overlap without being equal.
+ *
+ * @retval E_SCP_INVALID_BASE           if one or more of source_pa, dest_pa, or
+ *                                      context_pa points to an unsupported
+ *                                      memory region (e.g. EMEM).
+ *
+ * @retval E_SCP_INVALID_REQUEST        if size is zero or is not a multiple of
+ *                                      SCP_BLOCK_SIZE.
+ *
+ * @retval E_SCP_INVALID_OPERATION      if cipher_mode is not a valid
+ *                                      scp_cipher_mode_t value, or cipher_mode
+ *                                      is SCP_CIPHER_MODE_ECB and context_pa is
+ *                                      nonzero (non-NULL).
+ *
+ * @retval E_SCP_FEATURE_NOT_ENABLED    if dest_pa is located in external memory
+ *                                      but the application does not have
+ *                                      shortcut-DMA support enabled.
+ *
+ * @retval E_SCP_INVALID_DMA_SPECIFIER  if dest_pa is located in external memory
+ *                                      but the application has not called
+ *                                      scp_Configure_Shortcut() to configure
+ *                                      the shortcut-DMA path.
+ *
+ * @retval E_SCP_OUT_OF_RANGE           if one or more of the buffers referenced
+ *                                      by source_pa, dest_pa, or context_pa
+ *                                      overflows the memory region in which it
+ *                                      resides.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_INVALID_STATE              if calls to this function are prohibited
+ *                                      because the SCP driver is operating in
+ *                                      direct mode.
+ *
+ * @retval E_SCP_INVALID_LOCK_STATE     if access to certain necessary registers
+ *                                      is being blocked by SCP lockdown.
+ *
+ * @retval E_FAULT                      if an IO-PMP fault was detected.
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ */
+error_t scp_Encrypt(const scp_key_desc_t * p_key_desc,
+                    scp_cipher_mode_t      cipher_mode,
+                    uintptr_t              source_pa,
+                    uintptr_t              dest_pa,
+                    size_t                 size,
+                    uintptr_t              context_pa);
+
+/**
+ * @brief Decrypts an arbitary buffer of data using an AES-128 block cipher.
+ *
+ * Decrypts the first size bytes of data from source_pa using the key described
+ * by p_key_desc and writes the result to dest_pa. Uses an AES-128 block cipher
+ * operating in the mode indicated by cipher_mode as the decryption algorithm.
+ * If applicable, SCP_BLOCK_SIZE bytes from context_pa are used as the initial
+ * contextual input to the cipher.
+ *
+ * Should p_key_desc describe a derived key, the scp_Decrypt() function will
+ * perform the indicated key-derivation operation automatically. See the
+ * relevant SCP_KEY_* macros for details.
+ *
+ * Note that it is permissible for source_pa and dest_pa to reference the same
+ * memory location (i.e. to facilitate decrypting data in-place). However, the
+ * use of buffers that only partially overlap is prohibited and will result in
+ * an error.
+ *
+ * In the event that dest_pa refers to an external memory location, the
+ * application must ensure that it has first called scp_Configure_Shortcut() (or
+ * used the SCP_EXTERNAL_DEST() helper macro) to configure the shortcut-DMA
+ * path accordingly.
+ *
+ * @param[in]  p_key_desc   A pointer to the key-descriptor to be used for the
+ *                          decryption operation. Applications should acquire
+ *                          this parameter through one of the provided
+ *                          SCP_KEY_* macros.
+ *
+ * @param[in]  cipher_mode  The block-cipher mode of operation to use. See the
+ *                          documentation for scp_cipher_mode_t for a list of
+ *                          supported values.
+ *
+ * @param[in]  source_pa    The physical address of the input buffer to be
+ *                          decrypted. Must be aligned to SCP_BUFFER_ALIGNMENT
+ *                          and contain at least size bytes. Supports IMEM and
+ *                          DMEM locations only.
+ *
+ * @param[out] dest_pa      The physical address of the output buffer to which
+ *                          the decrypted data is to be written. Must be
+ *                          aligned to SCP_BUFFER_ALIGNMENT and have at least
+ *                          size bytes of capacity. Permitted to overlap with
+ *                          source_pa only if exactly equal. Supports IMEM,
+ *                          DMEM, and external locations.
+ *
+ * @param[in]  size         The number of bytes to process from source_pa. Must
+ *                          be a nonzero multiple of SCP_BLOCK_SIZE.
+ *
+ * @param[in]  context_pa   The physical address of the input buffer containing
+ *                          the initialization vector (CBC) or initial counter
+ *                          value with nonce (CTR) to be used for the
+ *                          decryption operation. Must be aligned to
+ *                          SCP_BUFFER_ALIGNMENT and contain at least
+ *                          SCP_BLOCK_SIZE bytes. Required to be zero (NULL)
+ *                          for ECB mode. Supports IMEM and DMEM locations
+ *                          only.
+ *
+ * @retval E_SUCCESS                    if data was decrypted successfully.
+ *
+ * @retval E_SCP_NOT_READY              if the SCP driver has not been
+ *                                      initialized.
+ *
+ * @retval E_SCP_INVALID_OBJECT         if p_key_desc does not point to a valid
+ *                                      key-descriptor.
+ *
+ * @retval E_SCP_INVALID_OBJECT_BUFFER  if p_key_desc was constructed with a
+ *                                      zero (NULL) or incorrectly-aligned
+ *                                      address, or a pointer to an unsupported
+ *                                      memory location (e.g. EMEM), or a buffer
+ *                                      that overflows the memory region in
+ *                                      which it resides, or a buffer of invalid
+ *                                      size.
+ *
+ * @retval E_SCP_INVALID_INDEX          if p_key_desc was constructed with an
+ *                                      invalid register or hardware-secret
+ *                                      index, or references secret-index zero.
+ *
+ * @retval E_PERM                       if p_key_desc was constructed with a
+ *                                      hardware-secret index that the
+ *                                      application does not have permission to
+ *                                      use.
+ *
+ * @retval E_SCP_INVALID_POINTER        if one or more of p_key_desc, source_pa,
+ *                                      or dest_pa is zero/NULL, or context_pa
+ *                                      is zero (NULL) and cipher_mode is not
+ *                                      SCP_CIPHER_MODE_ECB.
+ *
+ * @retval E_SCP_INVALID_ADDRESS        if one or more of source_pa, dest_pa, or
+ *                                      context_pa is incorrectly aligned, or
+ *                                      the buffers referenced by source_pa and
+ *                                      dest_pa overlap without being equal.
+ *
+ * @retval E_SCP_INVALID_BASE           if one or more of source_pa, dest_pa, or
+ *                                      context_pa points to an unsupported
+ *                                      memory region (e.g. EMEM).
+ *
+ * @retval E_SCP_INVALID_REQUEST        if size is zero or is not a multiple of
+ *                                      SCP_BLOCK_SIZE.
+ *
+ * @retval E_SCP_INVALID_OPERATION      if cipher_mode is not a valid
+ *                                      scp_cipher_mode_t value, or cipher_mode
+ *                                      is SCP_CIPHER_MODE_ECB and context_pa is
+ *                                      nonzero (non-NULL).
+ *
+ * @retval E_SCP_FEATURE_NOT_ENABLED    if dest_pa is located in external memory
+ *                                      but the application does not have
+ *                                      shortcut-DMA support enabled.
+ *
+ * @retval E_SCP_INVALID_DMA_SPECIFIER  if dest_pa is located in external memory
+ *                                      but the application has not called
+ *                                      scp_Configure_Shortcut() to configure
+ *                                      the shortcut-DMA path.
+ *
+ * @retval E_SCP_OUT_OF_RANGE           if one or more of the buffers referenced
+ *                                      by source_pa, dest_pa, or context_pa
+ *                                      overflows the memory region in which it
+ *                                      resides.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_INVALID_STATE              if calls to this function are prohibited
+ *                                      because the SCP driver is operating in
+ *                                      direct mode.
+ *
+ * @retval E_SCP_INVALID_LOCK_STATE     if access to certain necessary registers
+ *                                      is being blocked by SCP lockdown.
+ *
+ * @retval E_FAULT                      if an IO-PMP fault was detected.
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ */
+error_t scp_Decrypt(const scp_key_desc_t * p_key_desc,
+                    scp_cipher_mode_t      cipher_mode,
+                    uintptr_t              source_pa,
+                    uintptr_t              dest_pa,
+                    size_t                 size,
+                    uintptr_t              context_pa);
+
+/**
+ * @brief Computes the Davies-Meyer hash of an arbitrary buffer of data.
+ *
+ * Computes the Davies-Meyer hash of the first size bytes of data from source_pa
+ * and writes the result to dest_pa. Uses SCP_BLOCK_SIZE bytes from init_pa as
+ * the initial hash value.
+ *
+ * Note that it is permissible for dest_pa and init_pa to alias to the same
+ * memory location.
+ *
+ * In the event that dest_pa refers to an external memory location, the
+ * application must ensure that it has first called scp_Configure_Shortcut() (or
+ * used the SCP_EXTERNAL_DEST() helper macro) to configure the shortcut-DMA
+ * path accordingly.
+ *
+ * @param[in]  source_pa The physical address of the input buffer whose hash
+ *                       will be computed. Must be aligned to
+ *                       SCP_BUFFER_ALIGNMENT and contain at least size bytes.
+ *                       Supports IMEM and DMEM locations only.
+ *
+ * @param[in]  size      The number of bytes to process from source_pa. Must be
+ *                       a nonzero multiple of SCP_KEY_SIZE.
+ *
+ * @param[out] dest_pa   The physical address of the output buffer to which the
+ *                       computed hash value is to be written. Must be aligned
+ *                       to SCP_BUFFER_ALIGNMENT and have at least
+ *                       SCP_BLOCK_SIZE bytes of capacity. Supports IMEM, DMEM,
+ *                       and external locations.
+ *
+ * @param[in]  init_pa   The physical address of the input buffer containing the
+ *                       initial hash value H0 to be used in the computation.
+ *                       Must be aligned to SCP_BUFFER_ALIGNMENT and contain at
+ *                       least SCP_BLOCK_SIZE bytes. Permitted to alias to
+ *                       dest_pa. Supports IMEM and DMEM locations only.
+ *
+ * @retval E_SUCCESS                    if hash was computed successfully.
+ *
+ * @retval E_SCP_NOT_READY              if the SCP driver has not been
+ *                                      initialized.
+ *
+ * @retcal E_SCP_INVALID_POINTER        if one or more of source_pa, dest_pa, or
+ *                                      init_pa is zero/NULL.
+ *
+ * @retval E_SCP_INVALID_ADDRESS        if one or more of source_pa, dest_pa, or
+ *                                      init_pa is incorrectly aligned.
+ *
+ * @retval E_SCP_INVALID_BASE           if one or more of source_pa, dest_pa, or
+ *                                      init_pa points to an unsupported memory
+ *                                      location (e.g. EMEM).
+ *
+ * @retval E_SCP_INVALID_REQUEST        if size is zero or is not a multiple of
+ *                                      SCP_KEY_SIZE.
+ *
+ * @retval E_SCP_FEATURE_NOT_ENABLED    if dest_pa is located in external memory
+ *                                      but the application does not have
+ *                                      shortcut-DMA support enabled.
+ *
+ * @retval E_SCP_INVALID_DMA_SPECIFIER  if dest_pa is located in external memory
+ *                                      but the application has not called
+ *                                      scp_Configure_Shortcut() to configure
+ *                                      the shortcut-DMA path.
+ *
+ * @retval E_SCP_OUT_OF_RANGE           if one or more of the buffers referenced
+ *                                      by source_pa, dest_pa, or init_pa
+ *                                      overflows the memory region in which it
+ *                                      resides.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_INVALID_STATE              if calls to this function are prohibited
+ *                                      because the SCP driver is operating in
+ *                                      direct mode.
+ *
+ * @retval E_SCP_INVALID_LOCK_STATE     if access to certain necessary registers
+ *                                      is being blocked by SCP lockdown.
+ *
+ * @retval E_FAULT                      if an IO-PMP fault was detected.
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ */
+error_t scp_Dmhash(uintptr_t source_pa,
+                   size_t    size,
+                   uintptr_t dest_pa,
+                   uintptr_t init_pa);
+
+/**
+ * @brief Computes the CMAC of an arbitrary buffer of data.
+ *
+ * Computes the CMAC of the first size bytes of data from source_pa using the
+ * key described by p_key_desc and writes the result to dest_pa. Uses an AES-128
+ * block cipher for the operation. If provided, SCP_BLOCK_SIZE bytes from
+ * context_pa are used as the initial contextual input (IV) for the computation.
+ *
+ * When cmac_mode is SCP_CMAC_MODE_PARTIAL, scp_Cmac() skips the final step of
+ * the CMAC computation, thus allowing the result to be chained into a future
+ * call via context_pa. The full CMAC result can then be obtained by passing
+ * SCP_CMAC_MODE_COMPLETE, as is done for singular, unchained calls.
+ *
+ * Notice that it is the application's responsibility to pad the source message
+ * if needed (by appending 0b10...0 per the CMAC specification) and to signal
+ * that padding has occurred by setting cmac_mode to SCP_CMAC_MODE_PADDED in
+ * place of SCP_CMAC_MODE_COMPLETE.
+ *
+ * Should p_key_desc describe a derived key, the scp_Cmac() function will
+ * perform the indicated key-derivation operation automatically. See the
+ * relevant SCP_KEY_* macros for details.
+ *
+ * Note that it is permissible for dest_pa and context_pa to reference the same
+ * memory location (e.g. for easy chaining of partial computations - see
+ * above).
+ *
+ * In the event that dest_pa refers to an external memory location, the
+ * application must ensure that it has first called scp_Configure_Shortcut() (or
+ * used the SCP_EXTERNAL_DEST() helper macro) to configure the shortcut-DMA
+ * path accordingly.
+ *
+ * @param[in]  p_key_desc   A pointer to the key-descriptor to be used for the
+ *                          CMAC computation. Applications should acquire this
+ *                          parameter through one of the provided SCP_KEY_*
+ *                          macros.
+ *
+ * @param[in]  cmac_mode    The CMAC mode of operation to use. See the
+ *                          documentation for scp_cmac_mode_t for a list of
+ *                          supported values.
+ *
+ * @param[in]  source_pa    The physical address of the input buffer for which
+ *                          the CMAC will be computed. Must be aligned to
+ *                          SCP_BUFFER_ALIGNMENT and contain at least size
+ *                          bytes. Supports IMEM and DMEM locations only.
+ *
+ * @param[in]  size         The number of bytes to process from source_pa. Must
+ *                          be a nonzero multiple of SCP_BLOCK_SIZE.
+ *
+ * @param[out] dest_pa      The physical address of the output buffer to which
+ *                          the computed CMAC value is to be written. Must be
+ *                          aligned to SCP_BUFFER_ALIGNMENT and have at least
+ *                          SCP_BLOCK_SIZE bytes of capacity. Supports IMEM,
+ *                          DMEM, and external locations.
+ *
+ * @param[in]  context_pa   The physical address of the input buffer containing
+ *                          the result of a prior partial CMAC computation, if
+ *                          applicable. Must be aligned to SCP_BUFFER_ALIGNMENT
+ *                          and contain at least SCP_BLOCK_SIZE bytes. Should
+ *                          be zero (NULL) or should point to an all-zero
+ *                          buffer if not continuing a prior computation.
+ *                          Permitted to alias to dest_pa. Supports IMEM and
+ *                          DMEM locations only.
+ *
+ * @retval E_SUCCESS                    if CMAC was computed successfully.
+ *
+ * @retval E_SCP_NOT_READY              if the SCP driver has not been
+ *                                      initialized.
+ *
+ * @retval E_SCP_INVALID_OBJECT         if p_key_desc does not point to a valid
+ *                                      key-descriptor.
+ *
+ * @retval E_SCP_INVALID_OBJECT_BUFFER  if p_key_desc was constructed with a
+ *                                      zero (NULL) or incorrectly-aligned
+ *                                      address, or a pointer to an unsupported
+ *                                      memory location (e.g. EMEM), or a buffer
+ *                                      that overflows the memory region in
+ *                                      which it resides, or a buffer of invalid
+ *                                      size.
+ *
+ * @retval E_SCP_INVALID_INDEX          if p_key_desc was constructed with an
+ *                                      invalid register or hardware-secret
+ *                                      index, or references secret-index zero.
+ *
+ * @retval E_PERM                       if p_key_desc was constructed with a
+ *                                      hardware-secret index that the
+ *                                      application does not have permission to
+ *                                      use.
+ *
+ * @retval E_SCP_INVALID_POINTER        if one or more of p_key_desc, source_pa,
+ *                                      or dest_pa is zero/NULL.
+ *
+ * @retval E_SCP_INVALID_ADDRESS        if one or more of source_pa, dest_pa, or
+ *                                      context_pa is incorrectly aligned, or
+ *                                      the buffers referenced by source_pa and
+ *                                      context_pa overlap.
+ *
+ * @retval E_SCP_INVALID_BASE           if one or more of source_pa, dest_pa, or
+ *                                      context_pa points to an unsupported
+ *                                      memory region (e.g. EMEM).
+ *
+ * @retval E_SCP_INVALID_REQUEST        if size is zero or is not a multiple of
+ *                                      SCP_BLOCK_SIZE.
+ *
+ * @retval E_SCP_INVALID_OPERATION      if cmac_mode is not a valid
+ *                                      scp_cmac_mode_t value.
+ *
+ * @retval E_SCP_FEATURE_NOT_ENABLED    if dest_pa is located in external memory
+ *                                      but the application does not have
+ *                                      shortcut-DMA support enabled.
+ *
+ * @retval E_SCP_INVALID_DMA_SPECIFIER  if dest_pa is located in external memory
+ *                                      but the application has not called
+ *                                      scp_Configure_Shortcut() to configure
+ *                                      the shortcut-DMA path.
+ *
+ * @retval E_SCP_OUT_OF_RANGE           if one or more of the buffers referenced
+ *                                      by source_pa, dest_pa, or context_pa
+ *                                      overflows the memory region in which it
+ *                                      resides.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_INVALID_STATE              if calls to this function are prohibited
+ *                                      because the SCP driver is operating in
+ *                                      direct mode.
+ *
+ * @retval E_SCP_INVALID_LOCK_STATE     if access to certain necessary registers
+ *                                      is being blocked by SCP lockdown.
+ *
+ * @retval E_FAULT                      if an IO-PMP fault was detected.
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ */
+error_t scp_Cmac(const scp_key_desc_t * p_key_desc,
+                 scp_cmac_mode_t        cmac_mode,
+                 uintptr_t              source_pa,
+                 size_t                 size,
+                 uintptr_t              dest_pa,
+                 uintptr_t              context_pa);
+
+#endif // SCP__SCP_CRYPT_H
diff --git a/spe-freertos-bsp/fsp/source/include/scp/scp_direct.h b/spe-freertos-bsp/fsp/source/include/scp/scp_direct.h
new file mode 100644
index 0000000..a97107f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/scp/scp_direct.h
@@ -0,0 +1,674 @@
+/**
+ * @file    scp_direct.h
+ * @brief   Low-level SCP primitives.
+ *
+ * @note    Client applications should include scp.h instead of this file.
+ *
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SCP__SCP_DIRECT_H
+#define SCP__SCP_DIRECT_H
+#define FSP__SCP__SCP_DIRECT_H 1
+
+/* Compiler headers */
+#include <stdbool.h>                    // for bool
+#include <stdint.h>                     // for uint8_t, uintptr_t, etc.
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for HEADER_CHECK
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/io.h>                     // for local_read, local_write
+#include <error/common-errors.h>        // for error_t
+// Clients must provide their own DRF headers
+
+/* Module-specific FSP headers */
+#include <scp/scp_common.h>             // for scp_register_index_t
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The HEADER_CHECK macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+HEADER_CHECK(FSP__CPU__IO_H)
+HEADER_CHECK(FSP__ERROR__COMMON_ERRORS_H)
+HEADER_CHECK(FSP__SCP__SCP_COMMON_H)
+
+
+/**
+ * @brief Issues a single CCI instruction to the SCP unit.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ *
+ * @param[in] opcode    The CCI instruction to issue (e.g. XOR).
+ * @param[in] rx_or_imm A register index or 6-bit immediate value.
+ * @param[in] ry        A register index.
+ *
+ * @note The interpretation of the rx_or_imm and ry parameters is instruction-
+ *       dependent. They can be set to zero when not needed.
+ */
+#define SCP_INSTRUCTION(opcode, rx_or_imm, ry) (                        \
+    local_write(NV_PRGNLCL_RISCV_SCPDMATRFCMD,                          \
+        DRF_DEF(_PRGNLCL_RISCV, _SCPDMATRFCMD, _CCI_EX,    _CCI     ) | \
+        DRF_NUM(_PRGNLCL_RISCV, _SCPDMATRFCMD, _RY,        ry       ) | \
+        DRF_NUM(_PRGNLCL_RISCV, _SCPDMATRFCMD, _RX_OR_IMM, rx_or_imm) | \
+        DRF_DEF(_PRGNLCL_RISCV, _SCPDMATRFCMD, _OPCODE,    _##opcode)   \
+    )                                                                   \
+)
+
+/**
+ * @brief The size, in bytes, of each SCP GPR.
+ */
+#define SCP_REGISTER_SIZE 16U
+
+
+/**
+ * @brief A collection of supported transfer sizes for queued reads/writes.
+ */
+typedef enum scp_transfer_size_t
+{
+    SCP_TRANSFER_SIZE_1R  = NV_PRGNLCL_RISCV_SCPDMATRFCMD_SIZE_16B,
+    SCP_TRANSFER_SIZE_2R  = NV_PRGNLCL_RISCV_SCPDMATRFCMD_SIZE_32B,
+    SCP_TRANSFER_SIZE_4R  = NV_PRGNLCL_RISCV_SCPDMATRFCMD_SIZE_64B,
+    SCP_TRANSFER_SIZE_8R  = NV_PRGNLCL_RISCV_SCPDMATRFCMD_SIZE_128B,
+    SCP_TRANSFER_SIZE_16R = NV_PRGNLCL_RISCV_SCPDMATRFCMD_SIZE_256B,
+} scp_transfer_size_t;
+
+
+/**
+ * @brief Prepares the SCP driver for low-level operations.
+ *
+ * Prepares the SCP driver for low-level operations by entering direct mode.
+ * Applications must call scp_Start_Direct() before invoking any low-level SCP
+ * interfaces.
+ *
+ * @retval E_SUCCESS                if direct mode was started successfully.
+ *
+ * @retval E_SCP_NOT_READY          if the SCP driver has not been initialized.
+ *
+ * @retval E_SCP_NOTHING_TO_DO      if the SCP driver is already operating in
+ *                                  direct mode (no-op).
+ */
+error_t scp_Start_Direct(void);
+
+/**
+ * @brief Prepares the SCP driver for high-level operations.
+ *
+ * Prepares the SCP driver for high-level operations by exiting direct mode.
+ * Applications must call scp_Stop_Direct() before invoking any high-level SCP
+ * interfaces, unless otherwise noted.
+ *
+ * @pre The SCP GPRs must be fetchable and writable or an interrupt may occur.
+ *
+ * @retval E_SUCCESS                    if direct mode was stopped successfully.
+ *
+ * @retval E_SCP_NOT_READY              if the SCP driver has not been
+ *                                      initialized.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_SCP_INVALID_LOCK_STATE     if access to certain necessary registers
+ *                                      is being blocked by SCP lockdown.
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ *
+ * @retval E_SCP_NOTHING_TO_DO          if the SCP driver is not operating in
+ *                                      direct mode (no-op).
+ */
+error_t scp_Stop_Direct(void);
+
+/**
+ * @brief Loads data from a buffer into a general-purpose SCP register.
+ *
+ * Loads the first SCP_REGISTER_SIZE bytes from source_pa into the register
+ * specified by reg_index. Assumes that the destination register is writable.
+ *
+ * Applications can check the status of the underlying SCPDMA transfer using
+ * the provided scp_*_dma() interfaces.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] source_pa The physical address of the input buffer containing the
+ *                      data to be loaded. Must be aligned to and contain at
+ *                      least SCP_REGISTER_SIZE bytes. Supports IMEM and DMEM
+ *                      locations only.
+ *
+ * @param[in] reg_index The index of the SCP register to which the data is to
+ *                      be written.
+ */
+void scp_load(uintptr_t source_pa, scp_register_index_t reg_index);
+
+/**
+ * @brief Stores data from a general-purpose SCP register into a buffer.
+ *
+ * Writes the contents of the register specified by reg_index to the first
+ * SCP_REGISTER_SIZE bytes of dest_pa. Assumes that the source register is
+ * fetchable.
+ *
+ * Applications can check the status of the underlying SCPDMA transfer using
+ * the provided scp_*_dma() interfaces.
+ *
+ * In the event that dest_pa refers to an external memory location, the
+ * application is responsible for completing the corresponding shortcut-DMA
+ * transfer accordingly.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in]  reg_index The index of the SCP register containing the data to
+ *                       be stored.
+ *
+ * @param[out] dest_pa   The physical address of the output buffer to which the
+ *                       data is to be written. Must be aligned to and have
+ *                       capacity for at least SCP_REGISTER_SIZE bytes. Supports
+ *                       IMEM, DMEM, and external locations.
+ */
+void scp_store(scp_register_index_t reg_index, uintptr_t dest_pa);
+
+/**
+ * @brief Queues an SCPDMA transfer without issuing any push instructions.
+ *
+ * Queues a transfer of size bytes from source_pa but does not read any data
+ * until one or more subsequent push instructions are received. Generally used
+ * to feed sequencer programs.
+ *
+ * Applications can check the status of the underlying suppressed SCPDMA
+ * transfer using the provided scp_*_dma() interfaces.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] source_pa The physical address of the input buffer containing the
+ *                      data to be read. Must be aligned to and contain at
+ *                      least size bytes. Supports IMEM and DMEM locations
+ *                      only.
+ *
+ * @param[in] size      The number of bytes to read from source_pa. See the
+ *                      documentation for scp_transfer_size_t for supported
+ *                      values.
+ */
+void scp_queue_read(uintptr_t source_pa, scp_transfer_size_t size);
+
+/**
+ * @brief Queues an SCPDMA transfer without issuing any fetch instructions.
+ *
+ * Queues a transfer of size bytes to dest_pa but does not write any data until
+ * one or more subsequent fetch instructions are received. Generally used to
+ * feed sequencer programs.
+ *
+ * Applications can check the status of the underlying suppressed SCPDMA
+ * transfer using the provided scp_*_dma() interfaces.
+ *
+ * In the event that dest_pa refers to an external memory location, the
+ * application is responsible for queuing the corresponding shortcut-DMA
+ * transfer accordingly.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[out] dest_pa  The physical address of the output buffer to which the
+ *                      data is to be written. Must be aligned to and have
+ *                      capacity for at least size bytes. Supports IMEM, DMEM,
+ *                      and external locations.
+ *
+ * @param[in] size      The number of bytes to write to dest_pa. See the
+ *                      documentation for scp_transfer_size_t for supported
+ *                      values.
+ */
+void scp_queue_write(uintptr_t dest_pa, scp_transfer_size_t size);
+
+/**
+ * @brief Returns the active status of the SCPDMA unit.
+ *
+ * Applications can use scp_poll_dma() to determine whether a load, store,
+ * or CCI transfer has finished.
+ *
+ * @retval true  if the SCPDMA unit is active.
+ * @retval false if the SCPDMA unit is idle.
+ */
+static inline bool
+scp_poll_dma(void)
+{
+    return FLD_TEST_DRF(_PRGNLCL_RISCV, _SCPDMAPOLL, _DMA_ACTIVE, _ACTIVE,
+        local_read(NV_PRGNLCL_RISCV_SCPDMAPOLL));
+}
+
+/**
+ * @brief Polls the active status of the SCPDMA unit and returns when idle.
+ *
+ * Applications can use scp_wait_dma() to ensure that a prior load, store,
+ * or CCI transfer has finished.
+ */
+static inline void
+scp_wait_dma(void)
+{
+    while (scp_poll_dma())
+    {
+    }
+}
+
+/**
+ * @brief Checks for pending SCPDMA errors and then clears them if requested.
+ *
+ * Checks for pending SCPDMA errors. Clears them after reading if b_clear is
+ * true (IO-PMP errors are not cleared).
+ *
+ * Applications can use scp_check_dma() to determine whether a load, store, or
+ * CCI transfer has encountered problems.
+ *
+ * @pre The SCPDMA hardware must be idle.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] b_clear   A boolean value indicating whether the SCPDMA error
+ *                      status should be cleared before returning.
+ *
+ * @retval E_SUCCESS                if no errors were reported.
+ *
+ * @retval E_SCP_INVALID_ADDRESS    if an SCPDMA transfer was initiated with a
+ *                                  physical address whose offset is not
+ *                                  aligned to the transfer size.
+ *
+ * @retval E_SCP_INVALID_BASE       if an SCPDMA transfer was initiated with a
+ *                                  physical address that points to an
+ *                                  unsupported memory region (e.g. EMEM).
+ *
+ * @retval E_PERM                   if a CCI secret instruction was initiated
+ *                                  with a hardware-secret index that the
+ *                                  application does not have permission to
+ *                                  use.
+ *
+ * @retval E_FAULT                  if an IO-PMP fault was detected.
+ */
+error_t scp_check_dma(bool b_clear);
+
+///////////////////////////////////////////////////////////////////////////////
+// Begin instruction primitives. Refer to the IAS for full descriptions.
+
+/**
+ * @brief Adds a 6-bit immediate value to register ry.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] imm The 6-bit immediate value to add.
+ * @param[in] ry  The destination register to add to.
+ *
+ * @note The default carry-chain is 64 bits in length.
+ */
+static inline void
+scp_add(uint8_t imm, scp_register_index_t ry)
+{
+    SCP_INSTRUCTION(ADD, imm, ry);
+}
+
+/**
+ * @brief Performs a bitwise AND on the contents of registers rx and ry.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] rx The first operand register.
+ * @param[in] ry The second operand register and destination for the result.
+ */
+static inline void
+scp_and(scp_register_index_t rx, scp_register_index_t ry)
+{
+    SCP_INSTRUCTION(AND, rx, ry);
+}
+
+/**
+ * @brief Swaps the byte-order of the value in register rx.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] rx The source register containing the value to byte-swap.
+ * @param[in] ry The destination register to receive the byte-swapped result.
+ */
+static inline void
+scp_bswap(scp_register_index_t rx, scp_register_index_t ry)
+{
+    SCP_INSTRUCTION(BSWAP, rx, ry);
+}
+
+/**
+ * @brief Modifies the ACL of register ry.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] imm The new ACL value, encoded as {Wi,Fi,Ki,Fs,Ks} = imm[4:0].
+ * @param[in] ry  The register whose ACL will be updated.
+ *
+ * @note Only valid in secure contexts. Cannot grant secure permissions.
+ */
+static inline void
+scp_chmod(uint8_t imm, scp_register_index_t ry)
+{
+    SCP_INSTRUCTION(CHMOD, imm, ry);
+}
+
+/**
+ * @brief Generates the first of the two subkeys required for CMAC computation.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] rx The source register containing an encrypted zero value.
+ * @param[in] ry The destination register to receive the generated subkey.
+ *
+ * @note The initial step of encrypting zero must be completed separately.
+ */
+static inline void
+scp_cmac_sk(scp_register_index_t rx, scp_register_index_t ry)
+{
+    SCP_INSTRUCTION(CMAC_SK, rx, ry);
+}
+
+/**
+ * @brief Perform AES-128 decryption on the contents of register rx.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] rx The source register containing the ciphertext to decrypt.
+ * @param[in] ry The destination register to receive the decrypted plaintext.
+ *
+ * @note Obtains the key from the register specified in ku.
+ */
+static inline void
+scp_decrypt(scp_register_index_t rx, scp_register_index_t ry)
+{
+    SCP_INSTRUCTION(DECRYPT, rx, ry);
+}
+
+/**
+ * @brief Perform AES-128 encryption on the contents of register rx.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] rx The source register containing the plaintext to encrypt.
+ * @param[in] ry The destination register to receive the encrypted ciphertext.
+ *
+ * @note Obtains the key from the register specified in ku.
+ */
+static inline void
+scp_encrypt(scp_register_index_t rx, scp_register_index_t ry)
+{
+    SCP_INSTRUCTION(ENCRYPT, rx, ry);
+}
+
+/**
+ * @brief Offers the contents of register ry to the SCPDMA interface.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] ry The source register whose data will be fetched.
+ *
+ * @note Fetches zeroes if register ry lacks sufficient access rights.
+ */
+static inline void
+scp_fetch(scp_register_index_t ry)
+{
+    SCP_INSTRUCTION(FETCH, 0U, ry);
+}
+
+/**
+ * @brief Invalidates the engine's signature/hash.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @note Only valid in secure contexts.
+ */
+static inline void
+scp_forget_sig(void)
+{
+    SCP_INSTRUCTION(FORGET_SIG, 0U, 0U);
+}
+
+/**
+ * @brief Marks register ry as the key source for cryptographic operations.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] ry The source register from which key material will be read.
+ *
+ * @note Updates ku with the index of ry only (contents are not copied).
+ */
+static inline void
+scp_key(scp_register_index_t ry)
+{
+    SCP_INSTRUCTION(KEY, 0U, ry);
+}
+
+/**
+ * @brief Loads the next imm instructions into sequencer zero.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] imm The number of instructions to load (0-16).
+ *
+ * @note Resets the sequencer if imm is zero.
+ */
+static inline void
+scp_load_trace0(uint8_t imm)
+{
+    SCP_INSTRUCTION(LOAD_TRACE0, imm, 0U);
+}
+
+/**
+ * @brief Loads the next imm instructions into sequencer one.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] imm The number of instructions to load (0-16).
+ *
+ * @note Resets the sequencer if imm is zero.
+ */
+static inline void
+scp_load_trace1(uint8_t imm)
+{
+    SCP_INSTRUCTION(LOAD_TRACE1, imm, 0U);
+}
+
+/**
+ * @brief Invokes imm iterations of sequencer zero.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] imm The number of iterations to execute (0-63).
+ */
+static inline void
+scp_loop_trace0(uint8_t imm)
+{
+    SCP_INSTRUCTION(LOOP_TRACE0, imm, 0U);
+}
+
+/**
+ * @brief Invokes imm iterations of sequencer one.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] imm The number of iterations to execute (0-63).
+ */
+static inline void
+scp_loop_trace1(uint8_t imm)
+{
+    SCP_INSTRUCTION(LOOP_TRACE1, imm, 0U);
+}
+
+/**
+ * @brief Copies the contents of register rx into register ry.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] rx The source register to copy from.
+ * @param[in] ry The destination register to copy to.
+ */
+static inline void
+scp_mov(scp_register_index_t rx, scp_register_index_t ry)
+{
+    SCP_INSTRUCTION(MOV, rx, ry);
+}
+
+/**
+ * @brief No operation.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ */
+static inline void
+scp_nop(void)
+{
+    SCP_INSTRUCTION(NOP, 0U, 0U);
+}
+
+/**
+ * @brief Accepts data from the SCPDMA interface and stores in register ry.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] ry The destination register to receive the push data.
+ */
+static inline void
+scp_push(scp_register_index_t ry)
+{
+    SCP_INSTRUCTION(PUSH, 0U, ry);
+}
+
+/**
+ * @brief Writes a true random number to register ry.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] ry The destination register to receive the random number.
+ *
+ * @note Requires prior configuration of the RNG hardware. Not NIST-compliant.
+ */
+static inline void
+scp_rand(scp_register_index_t ry)
+{
+    SCP_INSTRUCTION(RAND, 0U, ry);
+}
+
+/**
+ * @brief Converts a decryption key into an equivalent encryption key.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] rx The source register containing the decryption key to convert.
+ * @param[in] ry The destination register to receive the encryption key.
+ *
+ * @note Inverse of the rkey10 instruction.
+ */
+static inline void
+scp_rkey1(scp_register_index_t rx, scp_register_index_t ry)
+{
+    SCP_INSTRUCTION(RKEY1, rx, ry);
+}
+
+/**
+ * @brief Converts an encryption key into an equivalent decryption key.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] rx The source register containing the encryption key to convert.
+ * @param[in] ry The destination register to receive the decryption key.
+ *
+ * @note Inverse of the rkey1 instruction.
+ */
+static inline void
+scp_rkey10(scp_register_index_t rx, scp_register_index_t ry)
+{
+    SCP_INSTRUCTION(RKEY10, rx, ry);
+}
+
+/**
+ * @brief Loads one of 64 hardware secrets into register ry.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] imm The index of the hardware secret to load (0-63).
+ * @param[in] ry  The destination register to receive the hardware secret.
+ *
+ * @note Only valid in secure contexts. ACL is updated accordingly.
+ */
+static inline void
+scp_secret(uint8_t imm, scp_register_index_t ry)
+{
+    SCP_INSTRUCTION(SECRET, imm, ry);
+}
+
+/**
+ * @brief Performs a bitwise XOR on the contents of registers rx and ry.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre Clients must enter direct mode before calling this function.
+ *
+ * @param[in] rx The first operand register.
+ * @param[in] ry The second operand register and destination for the result.
+ */
+static inline void
+scp_xor(scp_register_index_t rx, scp_register_index_t ry)
+{
+    SCP_INSTRUCTION(XOR, rx, ry);
+}
+
+// End instruction primitives.
+///////////////////////////////////////////////////////////////////////////////
+
+// Prevent external use of this macro.
+#undef SCP_INSTRUCTION
+
+#endif // SCP__SCP_DIRECT_H
diff --git a/spe-freertos-bsp/fsp/source/include/scp/scp_general.h b/spe-freertos-bsp/fsp/source/include/scp/scp_general.h
new file mode 100644
index 0000000..0b24303
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/scp/scp_general.h
@@ -0,0 +1,315 @@
+/**
+ * @file        scp_general.h
+ * @brief       General SCP operations.
+ *
+ * @note        Client applications should include scp.h instead of this file.
+ *
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SCP__SCP_GENERAL_H
+#define SCP__SCP_GENERAL_H
+#define FSP__SCP__SCP_GENERAL_H 1
+
+/* Compiler headers */
+#include <stdbool.h>                    // for bool
+#include <stdint.h>                     // for uint8_t, uintptr_t, etc.
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for HEADER_CHECK
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>        // for error_t
+// Clients must provide their own DRF headers
+
+/* Module-specific FSP headers */
+#include <scp/scp_common.h>             // for scp_register_index_t, etc.
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The HEADER_CHECK macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+HEADER_CHECK(FSP__ERROR__COMMON_ERRORS_H)
+HEADER_CHECK(FSP__SCP__SCP_COMMON_H)
+
+
+/**
+ * @brief Allocates a buffer whose base is aligned to SCP_BUFFER_ALIGNMENT.
+ *
+ * Allocates a buffer of size at least size whose base address is aligned to
+ * SCP_BUFFER_ALIGNMENT. The buffer has automatic storage duration.
+ *
+ * Note that the pointer returned by this macro may require virtual-to-physical
+ * conversion before it can be used in an SCP interface call, depending on the
+ * application's current operating mode. Furthermore, it is up to the
+ * application to ensure that the alignment properties of the returned pointer
+ * are preserved through the virtual-to-physical conversion process, if
+ * applicable.
+ *
+ * This macro is safe to call from direct mode.
+ *
+ * @param[in] size The desired size for the new buffer in bytes. This should
+ *                 generally be a nonzero multiple of one of the provided
+ *                 SCP_*_SIZE constants.
+ *
+ * @return A pointer to the newly-allocated buffer.
+ */
+#define SCP_ALIGNED_BUFFER(size) (                                    \
+    (uint8_t*)NV_ALIGN_UP64(                                          \
+        (uintptr_t)(uint8_t[(size) + SCP_BUFFER_ALIGNMENT - 1U]){0U}, \
+        SCP_BUFFER_ALIGNMENT                                          \
+    )                                                                 \
+)
+
+/**
+ * @brief Configures the shortcut-DMA path for an external destination buffer.
+ *
+ * Configures the shortcut path for transfers to external memory as if by
+ * calling scp_Configure_Shortcut(dma_index) and then returns dest_pa. Returns
+ * zero/NULL if configuration fails.
+ *
+ * This helper is meant to simplify the process of passing external buffers to
+ * applicable SCP interfaces by allowing for the shortcut-DMA path to be
+ * configured in-line. It also aims to lessen the risk of misconfigured
+ * shortcut transfers by encouraging applications to explicitly re-configure
+ * for each operation.
+ *
+ * Note that shortcut-DMA support must be enabled during build in order for
+ * this macro to succeed.
+ *
+ * @pre The selected DMA aperture must have been properly configured.
+ *
+ * @param[in] dest_pa   The physical address of the destination buffer.
+ * @param[in] dma_index The index of the DMA aperture to be used when
+ *                      transferring to the destination buffer.
+ *
+ * @retval dest_pa  if the shortcut-DMA path was configured successfully.
+ *
+ * @retval 0        if dma_index does not refer to a valid DMA aperture, or the
+ *                  application does not have shortcut-DMA support enabled, or
+ *                  the SCP driver has not been initialized.
+ */
+#define SCP_EXTERNAL_DEST(dest_pa, dma_index) (        \
+    (scp_Configure_Shortcut(dma_index) == E_SUCCESS) ? \
+    (dest_pa) : (uintptr_t)0U                          \
+)
+
+
+/**
+ * @brief A collection of flags that can be used to customize driver behaviour.
+ */
+typedef enum scp_init_flag_t
+{
+    /**
+     * @brief Use the recommended default configuration settings.
+     *
+     * @note Ignored if combined with other flags.
+     */
+    SCP_INIT_FLAG_DEFAULT = 0,
+
+} scp_init_flag_t;
+
+
+/**
+ * @brief Initializes the SCP driver and underlying hardware for use.
+ *
+ * Initializes the SCP driver for use. Applications must not call into any
+ * other SCP interfaces before executing scp_Init(), unless otherwise noted.
+ *
+ * After scp_Init() completes successfully, the SCP unit is guaranteed to be in
+ * a clean, safe state for the application to use.
+ *
+ * @param[in] flags A bitmask specifying the desired configuration settings for
+ *                  the SCP driver.
+ *
+ * @retval E_SUCCESS                    if initialization was successful.
+ *
+ * @retval E_SCP_INVALID_FLAGS          if flags is not a valid combination of
+ *                                      scp_init_flag_t values.
+ *
+ * @retval E_NOTSUPPORTED               if the host engine does not contain an
+ *                                      SCP unit.
+ *
+ * @retval E_PERM                       if the SCP unit or IO-PMP registers are
+ *                                      blocked in the host engine's device map.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_BUSY                       if the SCP unit is in use and cannot be
+ *                                      safely reset.
+ *
+ * @retval E_INVALID_STATE              if IO-PMP error-capture is disabled for
+ *                                      the CPDMA master.
+ *
+ * @retval E_SCP_INVALID_LOCK_STATE     if access to certain necessary registers
+ *                                      is being blocked by SCP lockdown, or the
+ *                                      host engine is secure-capable but SCP
+ *                                      lockdown is disabled.
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ */
+error_t scp_Init(scp_init_flag_t flags);
+
+/**
+ * @brief Clears all data from the SCP unit and disables further processing.
+ *
+ * Clears all data from the SCP unit and disables further processing of
+ * commands. Applications should invoke scp_Shutdown() as soon as SCP support is
+ * no longer needed (or at least before exiting).
+ *
+ * Should an application require SCP functionality again after issuing
+ * scp_Shutdown(), it must first invoke scp_Init() to initialize the driver
+ * again, unless otherwise noted.
+ *
+ * @retval E_SUCCESS                    if shutdown was successful.
+ *
+ * @retval E_SCP_NOT_READY              if the SCP driver has not been
+ *                                      initialized.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_BUSY                       if the SCP unit is in use and cannot be
+ *                                      safely reset.
+ *
+ * @retval E_SCP_INVALID_LOCK_STATE     if access to certain necessary registers
+ *                                      is being blocked by SCP lockdown.
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ *
+ * @retval E_SCP_NOTHING_TO_DO          if the SCP driver has already been shut
+ *                                      down (no-op).
+ */
+error_t scp_Shutdown(void);
+
+/**
+ * @brief Returns the debug status of the SCP unit.
+ *
+ * This function can be called regardless of whether the SCP driver has been
+ * initialized or shut down and is safe to call from direct mode.
+ *
+ * @retval  true  if the SCP unit is in debug mode.
+ * @retval  false if the SCP unit is not in debug mode.
+ */
+bool scp_Is_Debug(void);
+
+/**
+ * @brief Clears any data from the specified SCP GPR.
+ *
+ * This function is safe to call from direct mode.
+ *
+ * @pre The target register must be writable and fetchable if called from an
+ *      insecure context.
+ *
+ * @param[in] reg_index The index of the SCP register to clear.
+ *
+ * @retval E_SUCCESS                    if the register was cleared
+ *                                      successfully.
+ *
+ * @retval E_SCP_NOT_READY              if the SCP driver has not been
+ *                                      initialized.
+ *
+ * @retval E_SCP_INVALID_INDEX          if reg_index is not a valid
+ *                                      scp_register_index_t value.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ */
+error_t scp_Clear_Reg(scp_register_index_t reg_index);
+
+/**
+ * @brief Clears any data from all SCP GPRs.
+ *
+ * This function is safe to call from direct mode.
+ *
+ * @pre All GPRs must be writable and fetchable if called from an insecure
+ *      context.
+ *
+ * @retval E_SUCCESS                    if the registers were cleared
+ *                                      successfully.
+ *
+ * @retval E_SCP_NOT_READY              if the SCP driver has not been
+ *                                      initialized.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ */
+error_t scp_Clear_All(void);
+
+/**
+ * @brief Configures the shortcut-DMA path for transfers to external memory.
+ *
+ * Configures the shortcut path to be used by applicable interfaces when
+ * transferring data to external memory. Applications must call
+ * scp_Configure_Shortcut() (or the SCP_EXTERNAL_DEST() helper macro) before
+ * passing external destination buffers to any SCP interfaces.
+ *
+ * Once configured, the selected DMA aperture will be used for all future
+ * shortcut transfers until reconfigured by a subsequent call to
+ * scp_Configure_Shortcut().
+ *
+ * Note that the application is responsible for ensuring that the provided DMA
+ * aperture has itself been properly configured before use. Additionally,
+ * shortcut-DMA support must be enabled during build in order to leverage this
+ * feature.
+ *
+ * @param[in] dma_index The index of the DMA aperture to be used for shortcut
+ *                      transfers to external memory.
+ *
+ * @retval E_SUCCESS                    if the shortcut-DMA path was configured
+ *                                      successfully.
+ *
+ * @retval E_SCP_NOT_READY              if the SCP driver has not been
+ *                                      initialized.
+ *
+ * @retval E_SCP_INVALID_INDEX          if dma_index does not refer to a valid
+ *                                      DMA aperture.
+ *
+ * @retval E_SCP_FEATURE_NOT_ENABLED    if the application does not have
+ *                                      shortcut-DMA support enabled.
+ */
+error_t scp_Configure_Shortcut(uint8_t dma_index);
+
+#endif // SCP__SCP_GENERAL_H
diff --git a/spe-freertos-bsp/fsp/source/include/scp/scp_private.h b/spe-freertos-bsp/fsp/source/include/scp/scp_private.h
new file mode 100644
index 0000000..3e7f822
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/scp/scp_private.h
@@ -0,0 +1,473 @@
+/**
+ * @file        scp_private.h
+ * @brief       Private interfaces for internal use by the SCP driver.
+ *
+ * @note        Not intended for use by client applications.
+ *
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SCP__SCP_PRIVATE_H
+#define SCP__SCP_PRIVATE_H
+#define FSP__SCP__SCP_PRIVATE_H 1
+
+/* Compiler headers */
+#include <stdbool.h>                    // for bool
+#include <stddef.h>                     // for size_t
+#include <stdint.h>                     // for uint8_t, uintptr_t, etc.
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for HEADER_CHECK
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/csr.h>                    // for csr_read
+#include <cpu/io.h>                     // for local_read, local_write
+#include <error/common-errors.h>        // for error_t
+#include <misc/nvmisc_drf.h>            // for DRF macros
+
+/* Module-specific FSP headers */
+#include <scp/scp_common.h>             // for scp_register_index_t
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The HEADER_CHECK macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+HEADER_CHECK(FSP__CPU__CSR_H)
+HEADER_CHECK(FSP__CPU__IO_H)
+HEADER_CHECK(FSP__ERROR__COMMON_ERRORS_H)
+HEADER_CHECK(FSP__MISC__NVMISC_DRF_H)
+HEADER_CHECK(FSP__SCP__SCP_COMMON_H)
+
+
+/**
+ * @brief The hardware secret to use when clearing registers in secure contexts.
+ *
+ * @note Not to be used for any other purpose, per the security bar.
+ */
+#define SCP_SECRET_INDEX_CLEAR 0U
+
+
+/**
+ * @brief A structure describing the internal state of the SCP driver.
+ *
+ * @b_initialized           Tracks whether the driver has been initialized
+ *                          correctly. Most interfaces will early-out if this
+ *                          flag is not set.
+ *
+ * @b_shutdown              Tracks whether the driver has been shut down after a
+ *                          prior initialization. Mostly a courtesy feature to
+ *                          detect duplicate calls to scp_Shutdown().
+ *
+ * @b_direct_mode_active    Tracks whether the driver is currently operating in
+ *                          "direct mode", which affects whether certain higher-
+ *                          level interfaces are available.
+ *
+ * @b_rand_configured       Tracks whether the SCP unit's RNG hardware has been
+ *                          configured. Requests for random-number generation
+ *                          will be declined unless this flag is set.
+ *
+ * @b_shortcut_configured   Tracks whether the shortcut-DMA path has been
+ *                          configured. dma_index below is only valid if this
+ *                          flag is set and any requests for transfers to
+ *                          external memory will be declined otherwise.
+ *
+ * @dma_index               Stores the index of the DMA aperture to be used for
+ *                          shortcut transfers to external memory. Valid only if
+ *                          b_shortcut_configured is set.
+ */
+typedef struct scp_state_t
+{
+    bool    b_initialized           : 1;
+    bool    b_shutdown              : 1;
+    bool    b_direct_mode_active    : 1;
+    bool    b_rand_configured       : 1;
+    bool    b_shortcut_configured   : 1;
+    uint8_t dma_index;
+} scp_state_t;
+
+
+/**
+ * @brief Clears any data from the specified SCP GPR and then unlocks its ACL.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre The target register must be writable and fetchable if called from an
+ *      insecure context.
+ *
+ * @param[in] reg_index The index of the SCP register to clear.
+ *
+ * @retval E_SUCCESS                    if the register was cleared
+ *                                      successfully.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ *
+ * @note This is an internal-only version of scp_Clear_Reg() that skips certain
+ *       redundant checks.
+ */
+error_t scp_pvt_Clear_Reg(scp_register_index_t reg_index);
+
+/**
+ * @brief Clears any data from all SCP GPRs and then unlocks their ACLs.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre All GPRs must be writable and fetchable if called from an insecure
+ *      context.
+ *
+ * @retval E_SUCCESS                    if the registers were cleared
+ *                                      successfully.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ *
+ * @note This is an internal-only version of scp_Clear_All() that skips certain
+ *       redundant checks.
+ */
+error_t scp_pvt_Clear_All(void);
+
+/**
+ * @brief Resets the ACLs of all SCP GPRs to a fully-open state.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre This function must only be called from secure contexts.
+ * @pre All GPRs must have both secure permissions (Fs and Ks) enabled.
+ *
+ * @retval E_SUCCESS        if the registers were unlocked successfully.
+ * @retval E_SCP_GENERIC    if an unexpected error occurred.
+ *
+ * @note As a precaution, the contents of each register are cleared after
+ *       unlocking. It is recommended that callers also clear the registers
+ *       before unlocking by calling scp_pvt_Zero_All() and checking that it
+ *       succeeded.
+ */
+error_t scp_pvt_Unlock_All(void);
+
+/**
+ * @brief Zeroes all SCP GPRs.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre All GPRs must be writable and fetchable if called from an insecure
+ *      context.
+ *
+ * @retval E_SUCCESS                    if the registers were zeroed
+ *                                      successfully.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ *
+ * @note Calling this function from a secure context will leave the SCP GPRs
+ *       inaccessible from insecure contexts unless explicitly unlocked later.
+ */
+error_t scp_pvt_Zero_All(void);
+
+/**
+ * @brief Loads data from a buffer into a general-purpose SCP register.
+ *
+ * Loads the first SCP_REGISTER_SIZE bytes from source_pa into the register
+ * specified by reg_index. Assumes that the destination register is writable
+ * and that the caller has performed all necessary validation on source_pa and
+ * reg_index.
+ *
+ * Intended as an internal-only convenience wrapper for scp_load().
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ *
+ * @param[in]  source_pa    The physical address of the input buffer containing
+ *                          the data to be loaded. Must be aligned to and
+ *                          contain at least SCP_REGISTER_SIZE bytes. Supports
+ *                          IMEM and DMEM locations only.
+ *
+ * @param[in]  reg_index    The index of the SCP register to which the data is
+ *                          to be written.
+ *
+ * @retval E_SUCCESS                if data was loaded successfully.
+ * @retval E_FAULT                  if an IO-PMP fault was detected.
+ * @retval E_SCP_GENERIC            if an unexpected error occurred.
+ */
+error_t scp_pvt_Load_Buffer(uintptr_t               source_pa,
+                            scp_register_index_t    reg_index);
+
+/**
+ * @brief Stores data from a general-purpose SCP register into a buffer.
+ *
+ * Writes the contents of the register specified by reg_index to the first
+ * SCP_REGISTER_SIZE bytes of dest_pa. Assumes that the source register is
+ * fetchable and that the caller has performed all necessary validation on
+ * dest_pa and reg_index.
+ *
+ * In the event that dest_pa refers to an external memory location, the
+ * caller is also responsible for ensuring that the shortcut-DMA path has been
+ * properly enabled and configured accordingly.
+ *
+ * Intended as an internal-only convenience wrapper for scp_store().
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ *
+ * @param[in]  reg_index The index of the SCP register containing the data to
+ *                       be stored.
+ *
+ * @param[out] dest_pa   The physical address of the output buffer to which the
+ *                       data is to be written. Must be aligned to and have
+ *                       capacity for at least SCP_REGISTER_SIZE bytes. Supports
+ *                       IMEM, DMEM, and external locations.
+ *
+ * @retval E_SUCCESS                if data was stored successfully.
+ * @retval E_FAULT                  if an IO-PMP fault was detected.
+ * @retval E_SCP_GENERIC            if an unexpected error occurred.
+ */
+error_t scp_pvt_Store_Buffer(scp_register_index_t   reg_index,
+                             uintptr_t              dest_pa);
+
+/**
+ * @brief Validates an input/output buffer for use by a higher-level interface.
+ *
+ * Verifies that the input or output buffer pointed to by base_pa is located at
+ * a valid address within a supported memory region and is correctly aligned.
+ * Also ensures that shortcut-DMA support has been properly enabled and
+ * configured when b_allow_external is true.
+ *
+ * @param[in]  base_pa          The physical address of the buffer to validate.
+ *
+ * @param[in]  size             The size of the buffer to validate, in bytes.
+ *
+ * @param[in]  b_allow_external Whether to permit external memory locations.
+ *
+ * @retval E_SUCCESS                    if the buffer was validated
+ *                                      successfully.
+ *
+ * @retval E_SCP_INVALID_POINTER        if base_pa is zero (NULL).
+ *
+ * @retval E_SCP_VINALID_ADDRESS        if base_pa is incorrectly aligned.
+ *
+ * @retval E_SCP_INVALID_BASE           if base_pa points to an unsupported
+ *                                      memory region (e.g. EMEM).
+ *
+ * @retval E_SCP_FEATURE_NOT_ENABLED    if base_pa is located in external memory
+ *                                      but the application does not have
+ *                                      shortcut-DMA support enabled.
+ *
+ * @retval E_SCP_INVALID_DMA_SPECIFIER  if base_pa is located in external memory
+ *                                      but the application has not called
+ *                                      scp_Configure_Shortcut() to configure
+ *                                      the shortcut-DMA path.
+ *
+ * @retval E_SCP_OUT_OF_RANGE           if the buffer referenced by base_pa
+ *                                      overflows the memory region in which it
+ *                                      resides.
+ */
+error_t scp_pvt_Validate_Buffer(uintptr_t    base_pa,
+                                size_t       size,
+                                bool         b_allow_external);
+
+/**
+ * @brief Executes the program currently loaded in SCP sequencer zero.
+ *
+ * Repeatedly executes the sequencer program currently loaded into SCP
+ * sequencer zero until size bytes of data have been read from source_pa and/or
+ * written to dest_pa. Automatically breaks the input and/or output data into
+ * optimally-sized batches while processing.
+ *
+ * Note that the caller is assumed to have performed all necessary validation
+ * on source_pa, dest_pa, and size before passing them to this function. This
+ * includes verifying proper enablement and configuration of the shortcut-DMA
+ * path in the event that dest_pa refers to an external memory location.
+ *
+ * It is also assumed that the number of push/fetch instructions issued per
+ * iteration of the currently-loaded sequencer program exactly matches the
+ * values in the table below.
+ *
+ *       source_pa | dest_pa | pushes | fetches
+ *      -----------|---------|--------|---------
+ *        Present  | Present |   1    |    1
+ *        Present  | Absent  |   1    |    0
+ *        Absent   | Present |   0    |    1
+ *        Absent   | Absent  |   0    |    0
+ *
+ * While it is permissible to call this function with neither an input buffer
+ * nor an output buffer, doing so is likely to be less efficient than simply
+ * invoking the required number of sequencer iterations directly.
+ *
+ * @pre The SCP hardware must have been properly initialized.
+ * @pre The current security context must match that which was used to load the
+ *      sequencer program.
+ *
+ * @param[in]  source_pa    The physical address of the input buffer containing
+ *                          the data to be fed into the sequencer program (zero
+ *                          /NULL if none). Must be aligned to
+ *                          SCP_REGISTER_SIZE and contain at least size bytes.
+ *                          Supports IMEM and DMEM locations only.
+ *
+ * @param[out] dest_pa      The physical address of the output buffer to which
+ *                          the data produced by the sequencer program is to be
+ *                          written (zero/NULL if none). Must be aligned to
+ *                          SCP_REGISTER_SIZE and have at least size bytes of
+ *                          capacity. Supports IMEM, DMEM, and external
+ *                          locations.
+ *
+ * @param[in]  size         The number of bytes to process from source_pa and/or
+ *                          output to dest_pa. Must be a multiple of
+ *                          SCP_REGISTER_SIZE.
+ *
+ * @retval E_SUCCESS                if data was processed successfully.
+ * @retval E_FAULT                  if an IO-PMP fault was detected.
+ * @retval E_SCP_GENERIC            if an unexpected error occurred.
+ */
+error_t scp_pvt_Run_Sequence(uintptr_t  source_pa,
+                             uintptr_t  dest_pa,
+                             size_t     size);
+
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Disables the SCP unit's RNG hardware.
+ *
+ * @pre Must be called from a secure context if SCP lockdown is enabled.
+ */
+static inline void
+scp_pvt_Disable_Rand(void)
+{
+    local_write(NV_PRGNLCL_SCP_CTL1,
+        FLD_SET_DRF(_PRGNLCL_SCP, _CTL1, _RNG_EN, _DISABLED,
+            local_read(NV_PRGNLCL_SCP_CTL1)));
+}
+
+/**
+ * @brief Enables the SCP unit's RNG hardware.
+ *
+ * @pre Must be called from a secure context if SCP lockdown is enabled.
+ */
+static inline void
+scp_pvt_Enable_Rand(void)
+{
+    local_write(NV_PRGNLCL_SCP_CTL1,
+        FLD_SET_DRF(_PRGNLCL_SCP, _CTL1, _RNG_EN, _ENABLED,
+            local_read(NV_PRGNLCL_SCP_CTL1)));
+}
+
+/**
+ * @brief Checks whether SCP lockdown is enabled.
+ *
+ * @retval true     if SCP lockdown is enabled.
+ * @retval false    if SCP lockdown is disabled.
+ */
+static inline bool
+scp_pvt_Is_Lockdown_Enabled(void)
+{
+    return FLD_TEST_DRF(_PRGNLCL_SCP, _CTL_CFG, _LOCKDOWN_SCP, _ENABLE,
+        local_read(NV_PRGNLCL_SCP_CTL_CFG));
+}
+
+/**
+ * @brief Checks whether the host engine is operating in a secure context.
+ *
+ * @retval true     if the host engine is operating in a secure context.
+ * @retval false    if the host engine is operating in an insecure context.
+ */
+static inline bool
+scp_pvt_Is_Secure(void)
+{
+    return FLD_TEST_DRF64(_RISCV_CSR, _XRSP, _XRSEC, _SEC,
+                          csr_read(NV_RISCV_CSR_XRSP));
+}
+
+/**
+ * @brief Checks whether access to lockable SCP registers/fields is restricted.
+ *
+ * @retval true     if access is restricted.
+ * @retval false    if access is unrestricted.
+ */
+static inline bool
+scp_pvt_Is_Access_Restricted(void)
+{
+    return (scp_pvt_Is_Lockdown_Enabled() && !scp_pvt_Is_Secure());
+}
+
+/**
+ * @brief Requests a pipe reset. Waits for completion before returning.
+ *
+ * @pre Must be called from a secure context if SCP lockdown is enabled.
+ */
+static inline void
+scp_pvt_Reset_Pipeline(void)
+{
+    // Request a pipe reset.
+    local_write(NV_PRGNLCL_SCP_CTL1,
+        FLD_SET_DRF(_PRGNLCL_SCP, _CTL1, _PIPE_RESET, _TASK,
+            local_read(NV_PRGNLCL_SCP_CTL1)));
+
+    // Wait for the pipe reset to complete.
+    while (FLD_TEST_DRF(_PRGNLCL_SCP, _CTL1, _PIPE_RESET, _PENDING,
+        local_read(NV_PRGNLCL_SCP_CTL1)))
+    {
+    }
+}
+
+/**
+ * @brief Clears both SCP sequencers.
+ *
+ * @pre Must be called from a secure context if SCP lockdown is enabled.
+ */
+static inline void
+scp_pvt_Reset_Sequencers(void)
+{
+    // Request a reset of both sequencers.
+    local_write(NV_PRGNLCL_SCP_CTL1,
+        FLD_SET_DRF(_PRGNLCL_SCP, _CTL1, _SEQ_CLEAR, _TASK,
+            local_read(NV_PRGNLCL_SCP_CTL1)));
+
+    // Wait for the sequencer reset to complete.
+    while (FLD_TEST_DRF(_PRGNLCL_SCP, _CTL1, _SEQ_CLEAR, _PENDING,
+        local_read(NV_PRGNLCL_SCP_CTL1)))
+    {
+    }
+}
+
+///////////////////////////////////////////////////////////////////////////////
+
+/**
+ * @brief Global internal state variable.
+ */
+extern scp_state_t g_scp_state;
+
+#endif // SCP__SCP_PRIVATE_H
diff --git a/spe-freertos-bsp/fsp/source/include/scp/scp_rand.h b/spe-freertos-bsp/fsp/source/include/scp/scp_rand.h
new file mode 100644
index 0000000..32d2d8f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/scp/scp_rand.h
@@ -0,0 +1,279 @@
+/**
+ * @file    scp_rand.h
+ * @brief   SCP features for random-number generation.
+ *
+ * @note    Client applications should include scp.h instead of this file.
+ *
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SCP__SCP_RAND_H
+#define SCP__SCP_RAND_H
+#define FSP__SCP__SCP_RAND_H 1
+
+/* Compiler headers */
+#include <stddef.h>                     // for size_t
+#include <stdint.h>                     // for uintptr_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for HEADER_CHECK
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>        // for error_t
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The HEADER_CHECK macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+HEADER_CHECK(FSP__ERROR__COMMON_ERRORS_H)
+
+
+/**
+ * @brief The RNG block size.
+ *
+ * The size, in bytes, of a single block of data in the context of RNG
+ * operations.
+ */
+#define SCP_RAND_SIZE 16U
+
+
+/**
+ * @brief A collection of supported configurations for the SCP RNG hardware.
+ */
+typedef enum scp_rand_config_t
+{
+    /**
+     * @brief The default configuration recommended by hardware for optimal RNG.
+     */
+    SCP_RAND_CONFIG_DEFAULT,
+
+    /**
+     * @brief A configuration that generates fake, deterministic data.
+     *
+     * Intended for testing and debugging purposes. Note that this configuration
+     * is only supported when the SCP unit is in debug mode and also requires
+     * that fake-RNG support be enabled during build.
+     */
+    SCP_RAND_CONFIG_FAKE,
+
+} scp_rand_config_t;
+
+
+/**
+ * @brief Configures the SCP RNG hardware for use.
+ *
+ * Configures the SCP RNG hardware according to the value of config.
+ *
+ * Applications must call scp_Configure_Rand() before attempting to start the
+ * RNG hardware and must stop the hardware again before attempting to
+ * reconfigure, should the need arise.
+ *
+ * @param[in]  config           The hardware configuration to use. See the
+ *                              documentation for scp_rand_config_t for a list
+ *                              of supported values.
+ *
+ * @retval E_SUCCESS                    if configuration settings were applied
+ *                                      successfully.
+ *
+ * @retval E_SCP_NOT_READY              if the SCP driver has not been
+ *                                      initialized.
+ *
+ * @retval E_BUSY                       if the RNG hardware is currently running
+ *                                      and cannot be reconfigured.
+ *
+ * @retval E_INVALID_PARAM              if config is not a valid
+ *                                      scp_rand_config_t value.
+ *
+ * @retval E_SCP_INVALID_REQUEST        if config is SCP_RAND_CONFIG_FAKE but
+ *                                      the SCP unit is not in debug mode.
+ *
+ * @retval E_SCP_FEATURE_NOT_ENABLED    if config is SCP_RAND_CONFIG_FAKE but
+ *                                      the application does not have fake-RNG
+ *                                      support enabled.
+ *
+ * @retval E_INVALID_STATE              if calls to this function are prohibited
+ *                                      because the SCP driver is operating in
+ *                                      direct mode.
+ *
+ * @retval E_SCP_INVALID_LOCK_STATE     if access to certain necessary registers
+ *                                      is being blocked by SCP lockdown.
+ */
+error_t scp_Configure_Rand(scp_rand_config_t config);
+
+/**
+ * @brief Starts the SCP RNG hardware.
+ *
+ * Starts the SCP unit's RNG hardware. Applications must call scp_Start_Rand()
+ * before attempting to acquire random data from scp_Get_Rand() (or scp_rand()).
+ *
+ * Note that there is some delay between starting the RNG hardware and
+ * acquiring the first RNG data from it. The length of this delay is dictated
+ * by the specific hardware configuration set by scp_Configure_Rand() and
+ * manifests as increased latency in the execution of scp_Get_Rand().
+ *
+ * This function is safe to call from direct mode.
+ *
+ * @retval E_SUCCESS                if RNG hardware was started successfully.
+ *
+ * @retval E_SCP_NOT_READY          if the SCP driver has not been initialized.
+ *
+ * @retval E_INVALID_STATE          if the application has not called
+ *                                  scp_Configure_Rand() to configure the RNG
+ *                                  hardware for use.
+ *
+ * @retval E_SCP_INVALID_LOCK_STATE if access to certain necessary registers is
+ *                                  being blocked by SCP lockdown.
+ *
+ * @retval E_SCP_NOTHING_TO_DO      if the RNG hardware is already running (no-
+ *                                  op).
+ */
+error_t scp_Start_Rand(void);
+
+/**
+ * @brief Stops the SCP RNG hardware.
+ *
+ * Stops the SCP unit's RNG hardware. Applications must call scp_Stop_Rand()
+ * before attempting to reconfigure the RNG hardware via scp_Configure_Rand().
+ *
+ * This function is safe to call from direct mode.
+ *
+ * @retval E_SUCCESS                if RNG hardware was stopped successfully.
+ *
+ * @retval E_SCP_NOT_READY          if the SCP driver has not been initialized.
+ *
+ * @retval E_SCP_INVALID_LOCK_STATE if access to certain necessary registers is
+ *                                  being blocked by SCP lockdown.
+ *
+ * @retval E_SCP_NOTHING_TO_DO      if the RNG hardware is already stopped (no-
+ *                                  op).
+ */
+error_t scp_Stop_Rand(void);
+
+/**
+ * @brief Generates an arbitrary string of true-random data.
+ *
+ * Generates size bytes of true-random data and writes the result to dest_pa.
+ * Uses the first SCP_RAND_SIZE bytes from context_pa as a contextual input to
+ * the generation process, if provided.
+ *
+ * Applications must call scp_Start_Rand() to ensure that the RNG hardware is
+ * running before attempting to acquire data from scp_Get_Rand().
+ *
+ * Keep in mind that the quality of the data generated by scp_Get_Rand() is
+ * heavily influenced by the RNG hardware's specific configuration settings,
+ * which also affect the rate at which the random data is produced. These
+ * settings can be tuned via scp_Configure_Rand().
+ *
+ * In any case, the data produced by scp_Get_Rand() is not NIST-compliant and
+ * should not be used to generate encryption keys or initialization vectors.
+ *
+ * Note that it is permissible for dest_pa and context_pa to alias to the same
+ * memory location.
+ *
+ * In the event that dest_pa refers to an external memory location, the
+ * application must ensure that it has first called scp_Configure_Shortcut() (or
+ * used the SCP_EXTERNAL_DEST() helper macro) to configure the shortcut-DMA
+ * path accordingly.
+ *
+ * @param[out] dest_pa      The physical address of the output buffer to which
+ *                          the generated data is to be written. Must be
+ *                          aligned to SCP_BUFFER_ALIGNMENT and have at least
+ *                          size bytes of capacity. Supports IMEM, DMEM, and
+ *                          external locations.
+ *
+ * @param[in]  size         The number of bytes of data to generate. Must be a
+ *                          nonzero multiple of SCP_RAND_SIZE.
+ *
+ * @param[in]  context_pa   The physical address of the input buffer containing
+ *                          the initial context value to be factored into the
+ *                          generated data (zero/NULL if none). Must be aligned
+ *                          to SCP_BUFFER_ALIGNMENT and contain at least
+ *                          SCP_RAND_SIZE bytes. Permitted to alias to dest_pa.
+ *                          Supports IMEM and DMEM locations only.
+ *
+ * @retval E_SUCCESS                    if data was generated successfully.
+ *
+ * @retval E_SCP_NOT_READY              if the SCP driver has not been
+ *                                      initialized.
+ *
+ * @retval E_SCP_INVALID_OPERATION      if the RNG hardware is not running or
+ *                                      has not been properly configured.
+ *
+ * @retval E_SCP_INVALID_POINTER        if dest_pa is zero/NULL.
+ *
+ * @retval E_SCP_INVALID_ADDRESS        if one or more of dest_pa or context_pa
+ *                                      is incorrectly aligned.
+ *
+ * @retval E_SCP_INVALID_BASE           if one or more of dest_pa or context_pa
+ *                                      points to an unsupported memory region
+ *                                      (e.g. EMEM).
+ *
+ * @retval E_SCP_INVALID_REQUEST        if size is zero or is not a multiple of
+ *                                      SCP_RAND_SIZE.
+ *
+ * @retval E_SCP_FEATURE_NOT_ENABLED    if dest_pa is located in external memory
+ *                                      but the application does not have
+ *                                      shortcut-DMA support enabled.
+ *
+ * @retval E_SCP_INVALID_DMA_SPECIFIER  if dest_pa is located in external memory
+ *                                      but the application has not called
+ *                                      scp_Configure_Shortcut() to configure
+ *                                      the shortcut-DMA path.
+ *
+ * @retval E_SCP_OUT_OF_RANGE           if one or more of the buffers referenced
+ *                                      by dest_pa or context_pa overflows the
+ *                                      memory region in which it resides.
+ *
+ * @retval E_SCP_INSUFFICIENT_RESOURCES if the application lacks access to
+ *                                      secret-index zero (required in secure
+ *                                      contexts).
+ *
+ * @retval E_INVALID_STATE              if calls to this function are prohibited
+ *                                      because the SCP driver is operating in
+ *                                      direct mode.
+ *
+ * @retval E_SCP_INVALID_LOCK_STATE     if access to certain necessary registers
+ *                                      is being blocked by SCP lockdown.
+ *
+ * @retval E_FAULT                      if an IO-PMP fault was detected.
+ *
+ * @retval E_SCP_GENERIC                if an unexpected error occurred.
+ */
+error_t scp_Get_Rand(uintptr_t dest_pa, size_t size, uintptr_t context_pa);
+
+#endif // SCP__SCP_RAND_H
diff --git a/spe-freertos-bsp/fsp/source/include/sections/sections-base.h b/spe-freertos-bsp/fsp/source/include/sections/sections-base.h
new file mode 100644
index 0000000..518616d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/sections/sections-base.h
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef SECTIONS__SECTIONS_BASE_H
+#define SECTIONS__SECTIONS_BASE_H
+#define FSP__SECTIONS__SECTIONS_BASE_H                  0
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+/*
+ * Sections that should only be used in linker scripts and other special
+ * cases.
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_BSS                                                        .bss
+#define SECTION_NAME_DATA                                                       .data
+#define SECTION_NAME_RODATA                                                     .rodata
+#define SECTION_NAME_TEXT                                                       .text
+#define SECTION_NAME_VECTORS                                                    .vectors
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_INIT_DATA          SECTION_BUILDER(init,                   data)
+#define SECTION_NAME_INIT_RODATA        SECTION_BUILDER(init,                   rodata)
+#define SECTION_NAME_INIT_TEXT          SECTION_BUILDER(init,                   text)
+#define SECTION_NAME_DRAM_BSS           SECTION_BUILDER(dram,                   bss)
+#define SECTION_NAME_DRAM_DATA          SECTION_BUILDER(dram,                   data)
+#define SECTION_NAME_DRAM_RODATA        SECTION_BUILDER(dram,                   rodata)
+#define SECTION_NAME_DRAM_TEXT          SECTION_BUILDER(dram,                   text)
+#define SECTION_NAME_ERROR_BSS          SECTION_BUILDER(error,                  bss)
+#define SECTION_NAME_ERROR_DATA         SECTION_BUILDER(error,                  data)
+#define SECTION_NAME_ERROR_RODATA       SECTION_BUILDER(error,                  rodata)
+#define SECTION_NAME_ERROR_TEXT         SECTION_BUILDER(error,                  text)
+
+#define SECTION_STR_VECTORS             STR(SECTION_NAME_VECTORS)
+#define SECTION_STR_TEXT                STR(SECTION_NAME_TEXT)
+#define SECTION_STR_RODATA              STR(SECTION_NAME_RODATA)
+#define SECTION_STR_DATA                STR(SECTION_NAME_DATA)
+#define SECTION_STR_BSS                 STR(SECTION_NAME_BSS)
+#define SECTION_STR_INIT_TEXT           STR(SECTION_NAME_INIT_TEXT)
+#define SECTION_STR_INIT_RODATA         STR(SECTION_NAME_INIT_RODATA)
+#define SECTION_STR_INIT_DATA           STR(SECTION_NAME_INIT_DATA)
+#define SECTION_STR_DRAM_TEXT           STR(SECTION_NAME_DRAM_TEXT)
+#define SECTION_STR_DRAM_RODATA         STR(SECTION_NAME_DRAM_RODATA)
+#define SECTION_STR_DRAM_DATA           STR(SECTION_NAME_DRAM_DATA)
+#define SECTION_STR_DRAM_BSS            STR(SECTION_NAME_BSS)
+
+#define SECTION_VECTORS                 SECTION(SECTION_STR_VECTORS)
+#define SECTION_TEXT                    SECTION(SECTION_STR_TEXT)
+#define SECTION_RODATA                  SECTION(SECTION_STR_RODATA)
+#define SECTION_DATA                    SECTION(SECTION_STR_DATA)
+#define SECTION_BSS                     SECTION(SECTION_STR_BSS)
+#define SECTION_INIT_TEXT               SECTION(SECTION_STR_INIT_TEXT)
+#define SECTION_INIT_RODATA             SECTION(SECTION_STR_INIT_RODATA)
+#define SECTION_INIT_DATA               SECTION(SECTION_STR_INIT_DATA)
+#define SECTION_DRAM_TEXT               SECTION(SECTION_STR_DRAM_TEXT)
+#define SECTION_DRAM_RODATA             SECTION(SECTION_STR_DRAM_RODATA)
+#define SECTION_DRAM_DATA               SECTION(SECTION_STR_DRAM_DATA)
+#define SECTION_DRAM_BSS                SECTION(SECTION_STR_DRAM_BSS)
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/sections/sections-strings.h b/spe-freertos-bsp/fsp/source/include/sections/sections-strings.h
new file mode 100644
index 0000000..d6e6039
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/sections/sections-strings.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef SECTIONS__SECTIONS_STRINGS_H
+#define SECTIONS__SECTIONS_STRINGS_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_STRINGS_RODATA     SECTION_BUILDER(strings,                rodata)
+
+#define SECTION_STR_STRINGS_RODATA      STR(SECTION_NAME_STRINGS_RODATA)
+
+#define SECTION_STRINGS_RODATA          SECTION(SECTION_STR_STRINGS_RODATA)
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/sections/sections.h b/spe-freertos-bsp/fsp/source/include/sections/sections.h
new file mode 100644
index 0000000..7b8509c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/sections/sections.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef SECTIONS__SECTIONS_H
+#define SECTIONS__SECTIONS_H
+#define FSP__SECTIONS__SECTIONS_H                       1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/sha-nvriscv/sha-errors.h b/spe-freertos-bsp/fsp/source/include/sha-nvriscv/sha-errors.h
new file mode 100644
index 0000000..c75a255
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/sha-nvriscv/sha-errors.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SHA_NVRISCV__SHA_ERRORS_H
+#define SHA_NVRISCV__SHA_ERRORS_H
+#define FSP__SHA_NVRISCV__SHA_ERRORS_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "base/module-id.h"
+#include <misc/macros.h>                // for END_RFD_BLOCK, START_RFD_BLOCK
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+    CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @file sha-errors.h
+ * @brief Error codes that are specific to the sha
+ */
+
+#define E_SHA_ENG_ERROR             MODULE_ERROR(SHA_NVRISCV, 0UL)
+#define E_SHA_MUTEX_ACQUIRE_FAILED  MODULE_ERROR(SHA_NVRISCV, 1UL)
+#define E_SHA_MUTEX_RELEASE_FAILED  MODULE_ERROR(SHA_NVRISCV, 2UL)
+#define E_SHA_SW_RESET_TIMEOUT      MODULE_ERROR(SHA_NVRISCV, 3UL)
+#define E_SHA_WAIT_IDLE_TIMEOUT     MODULE_ERROR(SHA_NVRISCV, 4UL)
+
+#endif  /* SHA_NVRISCV__SHA_ERRORS_H */
diff --git a/spe-freertos-bsp/fsp/source/include/sha-nvriscv/sha.h b/spe-freertos-bsp/fsp/source/include/sha-nvriscv/sha.h
new file mode 100644
index 0000000..d02b884
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/sha-nvriscv/sha.h
@@ -0,0 +1,180 @@
+/**
+ * @file sha.h
+ *
+ * @brief SHA library for SHA-2 and HMAC SHA-2.
+ *
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution.
+ * * Neither the name of NVIDIA CORPORATION nor the names of its
+ * contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SHA_NVRISCV__SHA_H
+#define SHA_NVRISCV__SHA_H
+#define FSP__SHA_NVRISCV__SHA_H 1
+
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <cpu/type-conversion.h>
+#include <misc/macros.h>
+#include <error/common-errors.h>
+
+/* Module-specific FSP headers */
+#include <sha-nvriscv/sha-errors.h>
+
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#define BYTE_TO_BIT_LENGTH(a) ((a) << 3U)
+#define BIT_TO_BYTE_LENGTH(a) ((a) >> 3U)
+
+/* Size defines for SHA variants */
+#define SHA_1_BLOCK_SIZE_BYTE         (64U)
+#define SHA_1_BLOCK_SIZE_BIT          BYTE_TO_BIT_LENGTH(SHA_1_BLOCK_SIZE_BYTE)
+#define SHA_1_HASH_SIZE_BYTE          (20U)
+#define SHA_1_HASH_SIZE_BIT           BYTE_TO_BIT_LENGTH(SHA_1_HASH_SIZE_BYTE)
+
+#define SHA_224_BLOCK_SIZE_BYTE       (64U)
+#define SHA_224_BLOCK_SIZE_BIT        BYTE_TO_BIT_LENGTH(SHA_224_BLOCK_SIZE_BYTE)
+#define SHA_224_HASH_SIZE_BYTE        (28U)
+#define SHA_224_HASH_SIZE_BIT         BYTE_TO_BIT_LENGTH(SHA_224_HASH_SIZE_BYTE)
+
+#define SHA_256_BLOCK_SIZE_BYTE       (64U)
+#define SHA_256_BLOCK_SIZE_BIT        BYTE_TO_BIT_LENGTH(SHA_256_BLOCK_SIZE_BYTE)
+#define SHA_256_HASH_SIZE_BYTE        (32U)
+#define SHA_256_HASH_SIZE_BIT         BYTE_TO_BIT_LENGTH(SHA_256_HASH_SIZE_BYTE)
+
+#define SHA_384_BLOCK_SIZE_BYTE       (128U)
+#define SHA_384_BLOCK_SIZE_BIT        BYTE_TO_BIT_LENGTH(SHA_384_BLOCK_SIZE_BYTE)
+#define SHA_384_HASH_SIZE_BYTE        (48U)
+#define SHA_384_HASH_SIZE_BIT         BYTE_TO_BIT_LENGTH(SHA_384_HASH_SIZE_BYTE)
+
+#define SHA_512_BLOCK_SIZE_BYTE       (128U)
+#define SHA_512_BLOCK_SIZE_BIT        BYTE_TO_BIT_LENGTH(SHA_512_BLOCK_SIZE_BYTE)
+#define SHA_512_HASH_SIZE_BYTE        (64U)
+#define SHA_512_HASH_SIZE_BIT         BYTE_TO_BIT_LENGTH(SHA_512_HASH_SIZE_BYTE)
+
+#define SHA_512_224_BLOCK_SIZE_BYTE   (128U)
+#define SHA_512_224_BLOCK_SIZE_BIT    BYTE_TO_BIT_LENGTH(SHA_512_224_BLOCK_SIZE_BYTE)
+#define SHA_512_224_HASH_SIZE_BYTE    (28U)
+#define SHA_512_224_HASH_SIZE_BIT     BYTE_TO_BIT_LENGTH(SHA_512_224_HASH_SIZE_BYTE)
+
+#define SHA_512_256_BLOCK_SIZE_BYTE   (128U)
+#define SHA_512_256_BLOCK_SIZE_BIT    BYTE_TO_BIT_LENGTH(SHA_512_256_BLOCK_SIZE_BYTE)
+#define SHA_512_256_HASH_SIZE_BYTE    (32U)
+#define SHA_512_256_HASH_SIZE_BIT     BYTE_TO_BIT_LENGTH(SHA_512_256_HASH_SIZE_BYTE)
+
+/* Typedefs */
+typedef enum
+{
+    SHA_ALGO_ID_SHA_1       = (0U),
+    SHA_ALGO_ID_SHA_224,
+    SHA_ALGO_ID_SHA_256,
+    SHA_ALGO_ID_SHA_384,
+    SHA_ALGO_ID_SHA_512,
+    SHA_ALGO_ID_SHA_512_224,
+    SHA_ALGO_ID_SHA_512_256,
+    SHA_ALGO_ID_LAST
+} SHA_ALGO_ID;
+
+typedef struct
+{
+    uint8_t   src_type;
+    bool      b_default_hash_iv;
+    uint8_t   pad[2];
+    uint32_t  dma_idx;
+    uint32_t  size;
+    uint64_t  addr;
+} SHA_TASK_CONFIG;
+
+typedef struct
+{
+    SHA_ALGO_ID algo_id;
+    uint32_t    msg_size;
+    uint8_t     *p_buf_out;
+    uint32_t    buf_size;
+    uint8_t     mutex_token;
+} SHA_CONTEXT;
+
+typedef struct
+{
+    SHA_CONTEXT sha_context;
+    /*
+     *  key_buffer: Buffer to hold key used for HMAC operation. Maximum size is
+     *             SHA_512_BLOCK_SIZE_BYTE - if key is larger, user should hash first.
+     */
+    uint8_t key_buffer[SHA_512_BLOCK_SIZE_BYTE];
+
+    /*
+     *  key_size: Size of key in above buffer, in bytes.
+     */
+    uint32_t key_size;
+} HMAC_CONTEXT;
+
+/* Function Declarations */
+error_t sha_acquire_mutex(uint8_t mutex_token);
+error_t sha_release_mutex(uint8_t mutex_token);
+error_t sha_operation_init(const SHA_CONTEXT *p_sha_context);
+error_t sha_engine_halt(void);
+error_t sha_insert_task(SHA_CONTEXT *p_sha_context, const SHA_TASK_CONFIG *p_task_cfg);
+error_t sha_read_hash_result(const SHA_CONTEXT *p_sha_context, bool b_scrub_reg);
+error_t sha_get_hash_size_byte(SHA_ALGO_ID algo_id, uint32_t *p_size);
+error_t sha_get_block_size_byte(SHA_ALGO_ID algo_id, uint32_t *p_size);
+error_t sha_run_single_task_common(const SHA_TASK_CONFIG *p_task_cfg, SHA_CONTEXT *p_sha_ctx);
+error_t sha_hmac_operation_init(HMAC_CONTEXT *p_hmac_context);
+error_t sha_hmac_insert_task(HMAC_CONTEXT *p_hmac_context, SHA_TASK_CONFIG *p_task_cfg);
+error_t sha_hmac_read_hash_result(const HMAC_CONTEXT *p_hmac_context);
+error_t sha_hmac_run_single_task_common(HMAC_CONTEXT *p_hmac_context, SHA_TASK_CONFIG *p_task_cfg);
+
+/* Backward-compatibility for old code style */
+#define shaAcquireMutex                     sha_acquire_mutex
+#define shaReleaseMutex                     sha_release_mutex
+#define shaOperationInit                    sha_operation_init
+#define shaEngineHalt                       sha_engine_halt
+#define shaInsertTask                       sha_insert_task
+#define shaReadHashResult                   sha_read_hash_result
+#define shaGetHashSizeByte                  sha_get_hash_size_byte
+#define shaGetBlockSizeByte                 sha_get_block_size_byte
+#define shaRunSingleTaskCommon              sha_run_single_task_common
+#define shaHmacOperationInit                sha_hmac_operation_init
+#define shaHmacInsertTask                   sha_hmac_insert_task
+#define shaHmacReadHashResult               sha_hmac_read_hash_result
+#define shaHmacRunSingleTaskCommon          sha_hmac_run_single_task_common
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif // SHA_NVRISCV__SHA_H
+/*** end of file ***/
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/hw-config/vic-irqs.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/hw-config/vic-irqs.h
new file mode 100644
index 0000000..9859478
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/hw-config/vic-irqs.h
@@ -0,0 +1,137 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef HW_CONFIG__VIC_IRQS_H
+#define HW_CONFIG__VIC_IRQS_H
+#define FSP__HW_CONFIG__VIC_IRQS_H                      1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, ...
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>
+#include <vic/tegra-vic.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__VIC__TEGRA_VIC_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#define NUM_VICS                        2
+
+/*
+ * Define the various vectors where the VIC and IRQ are encoded into one value
+ */
+#define INTERRUPT_WDTFIQ                TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_WDTFIQ)
+#define INTERRUPT_WDTIRQ                TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_WDTIRQ)
+#define INTERRUPT_TIMER0                TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_TIMER0)
+#define INTERRUPT_TIMER1                TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_TIMER1)
+#define INTERRUPT_TIMER2                TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_TIMER2)
+#define INTERRUPT_TIMER3                TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_TIMER3)
+#define INTERRUPT_MBOX                  TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_MBOX)
+#define INTERRUPT_GTE                   TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_GTE)
+#define INTERRUPT_PMU                   TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_PMU)
+#define INTERRUPT_DMA0                  TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_DMA0)
+#define INTERRUPT_DMA1                  TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_DMA1)
+#define INTERRUPT_DMA2                  TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_DMA2)
+#define INTERRUPT_DMA3                  TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_DMA3)
+#define INTERRUPT_DMA4                  TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_DMA4)
+#define INTERRUPT_DMA5                  TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_DMA5)
+#define INTERRUPT_DMA6                  TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_DMA6)
+#define INTERRUPT_DMA7                  TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_DMA7)
+#define INTERRUPT_V0RSVD17              TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_V0RSVD17)
+#define INTERRUPT_I2C2                  TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_I2C2)
+#define INTERRUPT_I2C3                  TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_I2C3)
+#define INTERRUPT_SPI                   TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_SPI)
+#define INTERRUPT_DMIC                  TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_DMIC)
+#define INTERRUPT_UART_1                TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_UART_1)
+#define INTERRUPT_UART_J                TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_UART_J)
+#define INTERRUPT_CAN1_0                TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_CAN1_0)
+#define INTERRUPT_CAN1_1                TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_CAN1_1)
+#define INTERRUPT_CAN2_0                TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_CAN2_0)
+#define INTERRUPT_CAN2_1                TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_CAN2_1)
+#define INTERRUPT_LIC0                  TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_LIC0)
+#define INTERRUPT_LIC1                  TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_LIC1)
+#define INTERRUPT_LIC2                  TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_LIC2)
+#define INTERRUPT_LIC3                  TEGRA_INTERRUPT(0, NV_AON_INTERRUPT_LIC3)
+
+// VIC1 interrupts
+#define INTERRUPT_NOC_ERR               TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_NOC_ERR)
+#define INTERRUPT_GPIO                  TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_GPIO)
+#define INTERRUPT_WAKE0                 TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_WAKE0)
+#define INTERRUPT_PMC                   TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_PMC)
+#define INTERRUPT_V1RSVD4               TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_V1RSVD4)
+#define INTERRUPT_PM                    TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_PM)
+#define INTERRUPT_FPUINT                TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_FPUINT)
+#define INTERRUPT_V1RSVD7               TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_V1RSVD7)
+#define INTERRUPT_ACTMON                TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_ACTMON)
+#define INTERRUPT_AOWDT                 TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_AOWDT)
+#define INTERRUPT_TOP0_HSP_DB           TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_TOP0_HSP_DB)
+#define INTERRUPT_CTIIRQ                TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_CTIIRQ)
+#define INTERRUPT_NOC_SEC               TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_NOC_SEC)
+#define INTERRUPT_CAR                   TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_CAR)
+#define INTERRUPT_UART6                 TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_UART6)
+#define INTERRUPT_UART8                 TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_UART8)
+#define INTERRUPT_GPIO_3                TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_GPIO_3)
+#define INTERRUPT_CEC                   TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_CEC)
+#define INTERRUPT_V1RSVD18              TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_V1RSVD18)
+#define INTERRUPT_V1RSVD19              TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_V1RSVD19)
+#define INTERRUPT_V1RSVD20              TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_V1RSVD20)
+#define INTERRUPT_V1RSVD21              TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_V1RSVD21)
+#define INTERRUPT_V1RSVD22              TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_V1RSVD22)
+#define INTERRUPT_V1RSVD23              TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_V1RSVD23)
+#define INTERRUPT_V1RSVD24              TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_V1RSVD24)
+#define INTERRUPT_V1RSVD25              TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_V1RSVD25)
+#define INTERRUPT_V1RSVD26              TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_V1RSVD26)
+#define INTERRUPT_V1RSVD27              TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_V1RSVD27)
+#define INTERRUPT_V1RSVD28              TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_V1RSVD28)
+#define INTERRUPT_V1RSVD29              TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_V1RSVD29)
+#define INTERRUPT_V1RSVD30              TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_V1RSVD30)
+#define INTERRUPT_V1RSVD31              TEGRA_INTERRUPT(1, NV_AON_INTERRUPT_V1RSVD31)
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/aodmic-port-priv.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/aodmic-port-priv.h
new file mode 100644
index 0000000..ae4f209
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/aodmic-port-priv.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PORT__AODMIC_PORT_PRIV_H
+#define PORT__AODMIC_PORT_PRIV_H
+#define FSP__PORT__AODMIC_PORT_PRIV_H                        1
+
+/* Compiler headers */
+#include <stdint.h>                     // for uint8_t, uint32_t
+                                        // IWYU pragma: no_include <errno.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+struct aodmic_port_clk_rst {
+    const struct tegra_clk *clk;
+    const struct tegra_rst *rst;
+};
+
+
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+#endif /* PORT__AODMIC_PORT_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/aodmic-port.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/aodmic-port.h
new file mode 100644
index 0000000..b13f46e
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/aodmic-port.h
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PORT__AODMIC_PORT_H
+#define PORT__AODMIC_PORT_H
+#define FSP__PORT__AODMIC_PORT_H                        1
+
+/* Compiler headers */
+#include <stdint.h>                     // for uint8_t, uint32_t
+                                        // IWYU pragma: no_include <errno.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>        // for MODULE_ID_AODMIC, E_SUCCESS
+#include <misc/macros.h>                // for END_RFD_BLOCK, START_RFD_BLOCK
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+extern const struct aodmic_port_clk_rst aodmic_port_clk_rst_aon;
+
+error_t aodmic_port_clock_reset_config(const struct aodmic_port_clk_rst *hw_handle);
+
+error_t aodmic_port_clock_disable(const struct aodmic_port_clk_rst *hw_handle);
+
+error_t aodmic_port_clock_set_rate(const struct aodmic_port_clk_rst *hw_handle,
+                                    uint32_t sample_rate);
+
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+#endif /* PORT__AODMIC_PORT_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/gpcdma-port-priv.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/gpcdma-port-priv.h
new file mode 100644
index 0000000..4263bc2
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/gpcdma-port-priv.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GPCDMA__GPCDMA_PORT_PRIV_H
+#define GPCDMA__GPCDMA_PORT_PRIV_H
+#define FSP__PORT__GPCDMA_PORT_PRIV_H                      0
+
+/**
+ * @file gpcdma/gpcdma-port-priv-.h
+ * @brief provides context that is specific to the port layer.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* HW headers */
+
+/* Late FSP headers */
+
+struct gpcdma_hw_handle {
+    const struct tegra_rst *rst;
+};
+
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/i2c-port.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/i2c-port.h
new file mode 100644
index 0000000..e52449d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/i2c-port.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PORT__I2C_PORT_H
+#define PORT__I2C_PORT_H
+#define FSP__PORT__I2C_PORT_H                         1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+
+#endif      /* PORT__I2C_PORT_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/spi-port-priv.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/spi-port-priv.h
new file mode 100644
index 0000000..6afbe9e
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/spi-port-priv.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SPI__SPI_PORT_PRIV_H
+#define SPI__SPI_PORT_PRIV_H
+#define FSP__PORT__SPI_PORT_PRIV_H                      0
+
+/**
+ * @file spi/spi-port-priv.h
+ * @brief provides context that is specific to the port layer.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* HW headers */
+
+/* Late FSP headers */
+
+struct spi_hw_handle {
+    const struct tegra_rst *rst;
+    const struct tegra_clk *clk;
+};
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/uart-port-priv.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/uart-port-priv.h
new file mode 100644
index 0000000..fac77ec
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/port/uart-port-priv.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef UART__UART_PORT_PRIV_H
+#define UART__UART_PORT_PRIV_H
+#define FSP__PORT__UART_PORT_PRIV_H                      0
+
+#include <osa/rtos-queue.h>
+
+/**
+ * @file uart/uart-port-priv-.h
+ * @brief provides context that is specific to the port layer.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* HW headers */
+
+/* Late FSP headers */
+
+typedef rtosQueueHandle uart_queue_t;
+
+struct uart_hw_handle {
+    const struct tegra_clk *clk;
+    const struct tegra_rst *rst;
+};
+
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/cache-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/cache-hw.h
new file mode 100644
index 0000000..dc8681d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/cache-hw.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__CACHE_HW_H
+#define PROCESSOR__CACHE_HW_H
+#define FSP__PROCESSOR__CACHE_HW_H                      1
+
+#include <cpu/armv7-cache.h>
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/debug-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/debug-hw.h
new file mode 100644
index 0000000..05437f6
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/debug-hw.h
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2016-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__DEBUG_HW_H
+#define PROCESSOR__DEBUG_HW_H
+#define FSP__PROCESSOR__DEBUG_HW_H                      1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>
+
+/* Late FSP headers */
+#include <misc/macros.h>       // START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#define TEGRA_DBG_UART_BASE     NV_ADDRESS_MAP_UARTC_BASE
+#define TEGRA_DBG_UART_CLK      tegra_clk_uartc
+#define TEGRA_DBG_UART_RST      tegra_rst_uartc
+#define TEGRA_DBG_UART_BAUD     115200
+
+#ifdef TEGRA_UARTC_ENABLED
+extern struct tegra_uart_ctlr tegra_uart_ctlr_uartc;
+
+#ifndef DEBUG_UART
+#define DEBUG_UART      tegra_uart_ctlr_uartc
+#endif
+#endif
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/gpcdma-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/gpcdma-hw.h
new file mode 100644
index 0000000..18fbe66
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/gpcdma-hw.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GPCDMA_HW_H
+#define GPCDMA_HW_H
+#define FSP__PROCESSOR__GPCDMA_HW_H                  1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/macros.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+
+#define GPCDMA_CHAN0    gpcdma_chan0
+#define GPCDMA_CHAN1    gpcdma_chan1
+#define GPCDMA_CHAN2    gpcdma_chan2
+#define GPCDMA_CHAN3    gpcdma_chan3
+#define GPCDMA_CHAN4    gpcdma_chan4
+#define GPCDMA_CHAN5    gpcdma_chan5
+#define GPCDMA_CHAN6    gpcdma_chan6
+#define GPCDMA_CHAN7    gpcdma_chan7
+
+#ifndef __ASSEMBLER__
+
+extern struct gpcdma_id gpcdma_id_aon;
+extern struct gpcdma_channel gpcdma_chan0;
+extern struct gpcdma_channel gpcdma_chan1;
+extern struct gpcdma_channel gpcdma_chan2;
+extern struct gpcdma_channel gpcdma_chan3;
+extern struct gpcdma_channel gpcdma_chan4;
+extern struct gpcdma_channel gpcdma_chan5;
+extern struct gpcdma_channel gpcdma_chan6;
+extern struct gpcdma_channel gpcdma_chan7;
+
+#endif
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/gpio-tegra.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/gpio-tegra.h
new file mode 100644
index 0000000..f4c222a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/gpio-tegra.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GPIO_TEGRA_H
+#define GPIO_TEGRA_H
+#define FSP__PROCESSOR__GPIO_TEGRA_H                  1
+
+#include <gpio/tegra-gpio.h>            // for #define MAX_GPIO_CONTROLLERS
+#include <gpio/tegra-gpio-priv.h>       // for struct tegra_gpio_id
+
+/* DCE GPIO ID */
+extern struct tegra_gpio_id * tegra_gpio_id_aon[MAX_GPIO_CONTROLLERS];
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/hsp-tegra-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/hsp-tegra-hw.h
new file mode 100644
index 0000000..c80c3b0
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/hsp-tegra-hw.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PROCESSOR__HSP_TEGRA_HW_H
+#define PROCESSOR__HSP_TEGRA_HW_H
+#define FSP__PROCESSOR__HSP_TEGRA_HW_H                  1
+
+#include <misc/ct-assert.h>
+#include <soc-common/hsp-tegra-top-hw.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HSP_TEGRA_TOP_HW_H, "Header file missing or invalid.")
+
+#define TEGRA_HSP_ID_MBOX tegra_hsp_id_aon
+#define TEGRA_HSP_ID_DB   tegra_hsp_id_top0
+
+#ifndef __ASSEMBLER__
+
+/* This is the TOP HSP instance w/ AON interrupts */
+extern struct tegra_hsp_id tegra_hsp_id_aon;
+extern struct tegra_hsp_id tegra_hsp_id_bpmp;
+extern struct tegra_hsp_id tegra_hsp_id_fsi;
+extern struct tegra_hsp_id tegra_hsp_id_top0;
+extern struct tegra_hsp_id tegra_hsp_id_top1;
+extern struct tegra_hsp_id tegra_hsp_id_sce;
+
+#endif
+
+#endif /* PROCESSOR__HSP_TEGRA_HW_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/i2c-tegra-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/i2c-tegra-hw.h
new file mode 100644
index 0000000..60353ca
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/i2c-tegra-hw.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef I2C_TEGRA_HW_H
+#define I2C_TEGRA_HW_H
+#define FSP__PROCESSOR__I2C_TEGRA_HW_H                  1
+
+/* Compiler headers */
+#include <stdbool.h>              // for bool
+#include <stdint.h>               // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>       // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/bitops.h>          // for BIT
+
+/* Module-specific FSP headers */
+#include <soc-common/i2c-defs.h>  // for FSP__SOC_COMMON__I2C_DEFS_H, TEGRA1...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__I2C_DEFS_H, "Header file missing or invalid.")
+
+struct i2c_hw_handle;
+
+struct i2c_hw_handle {
+    const uint32_t ctrl_id;
+    const uint32_t base;
+    const struct tegra_clk *clk_data;
+    const struct tegra_rst *rst_data;
+    const uint32_t irq_no;
+    bool is_multimaster;
+};
+
+const struct i2c_hw_handle *i2c_get_hw_handle(uint32_t ctrl_id);
+
+/* @brief BIT vector for Valid i2c ids for SPE cluster. */
+#define VALID_I2C_IDS   (BIT(TEGRA234_I2C2) | BIT(TEGRA234_I2C8))
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/irqs-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/irqs-hw.h
new file mode 100644
index 0000000..7adfe00
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/irqs-hw.h
@@ -0,0 +1,95 @@
+/*
+* Copyright (c) 2020 NVIDIA CORPORATION.  All rights reserved.
+*
+* NVIDIA CORPORATION and its licensors retain all intellectual property
+* and proprietary rights in and to this software, related documentation
+* and any modifications thereto.  Any use, reproduction, disclosure or
+* distribution of this software and related documentation without an express
+* license agreement from NVIDIA CORPORATION is strictly prohibited.
+*/
+
+#ifndef PROCESSOR__IRQS_HW_H
+#define PROCESSOR__IRQS_HW_H
+#define FSP__PROCESSOR__IRQS_HW_H                       1
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#define MAX_VIC_CONTROLLER       2
+
+#define NV_AON_INTERRUPT_VIC0_BASE	0
+#define NV_AON_INTERRUPT_VIC1_BASE	32
+
+// VIC0 interrupts
+#define NV_AON_INTERRUPT_WDTFIQ   0
+#define NV_AON_INTERRUPT_WDTIRQ   1
+#define NV_AON_INTERRUPT_TIMER0   2
+#define NV_AON_INTERRUPT_TIMER1   3
+#define NV_AON_INTERRUPT_TIMER2   4
+#define NV_AON_INTERRUPT_TIMER3   5
+#define NV_AON_INTERRUPT_MBOX     6
+#define NV_AON_INTERRUPT_GTE      7
+#define NV_AON_INTERRUPT_PMU      8
+#define NV_AON_INTERRUPT_DMA0     9
+#define NV_AON_INTERRUPT_DMA1     10
+#define NV_AON_INTERRUPT_DMA2     11
+#define NV_AON_INTERRUPT_DMA3     12
+#define NV_AON_INTERRUPT_DMA4     13
+#define NV_AON_INTERRUPT_DMA5     14
+#define NV_AON_INTERRUPT_DMA6     15
+#define NV_AON_INTERRUPT_DMA7     16
+#define NV_AON_INTERRUPT_V0RSVD17 17
+#define NV_AON_INTERRUPT_I2C2     18
+#define NV_AON_INTERRUPT_I2C3     19
+#define NV_AON_INTERRUPT_SPI      20
+#define NV_AON_INTERRUPT_DMIC     21
+#define NV_AON_INTERRUPT_UART_1   22
+#define NV_AON_INTERRUPT_UART_J   23
+#define NV_AON_INTERRUPT_CAN1_0   24
+#define NV_AON_INTERRUPT_CAN1_1   25
+#define NV_AON_INTERRUPT_CAN2_0   26
+#define NV_AON_INTERRUPT_CAN2_1   27
+#define NV_AON_INTERRUPT_LIC0     28
+#define NV_AON_INTERRUPT_LIC1     29
+#define NV_AON_INTERRUPT_LIC2     30
+#define NV_AON_INTERRUPT_LIC3     31
+
+// VIC1 interrupts
+#define NV_AON_INTERRUPT_NOC_ERR   0
+#define NV_AON_INTERRUPT_GPIO      1
+#define NV_AON_INTERRUPT_WAKE0     2
+#define NV_AON_INTERRUPT_PMC       3
+#define NV_AON_INTERRUPT_V1RSVD4   4
+#define NV_AON_INTERRUPT_PM        5
+#define NV_AON_INTERRUPT_FPUINT    6
+#define NV_AON_INTERRUPT_V1RSVD7   7
+#define NV_AON_INTERRUPT_ACTMON    8
+#define NV_AON_INTERRUPT_AOWDT     9
+#define NV_AON_INTERRUPT_TOP0_HSP_DB 10
+#define NV_AON_INTERRUPT_CTIIRQ   11
+#define NV_AON_INTERRUPT_NOC_SEC  12
+#define NV_AON_INTERRUPT_CAR      13
+#define NV_AON_INTERRUPT_UART6    14
+#define NV_AON_INTERRUPT_UART8    15
+#define NV_AON_INTERRUPT_GPIO_3   16
+#define NV_AON_INTERRUPT_CEC 17
+#define NV_AON_INTERRUPT_V1RSVD18 18
+#define NV_AON_INTERRUPT_V1RSVD19 19
+#define NV_AON_INTERRUPT_V1RSVD20 20
+#define NV_AON_INTERRUPT_V1RSVD21 21
+#define NV_AON_INTERRUPT_V1RSVD22 22
+#define NV_AON_INTERRUPT_V1RSVD23 23
+#define NV_AON_INTERRUPT_V1RSVD24 24
+#define NV_AON_INTERRUPT_V1RSVD25 25
+#define NV_AON_INTERRUPT_V1RSVD26 26
+#define NV_AON_INTERRUPT_V1RSVD27 27
+#define NV_AON_INTERRUPT_V1RSVD28 28
+#define NV_AON_INTERRUPT_V1RSVD29 29
+#define NV_AON_INTERRUPT_V1RSVD30 30
+#define NV_AON_INTERRUPT_V1RSVD31 31
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif /* PROCESSOR__IRQS_HW_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/irqs-lic.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/irqs-lic.h
new file mode 100644
index 0000000..7c0a094
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/irqs-lic.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2017-2019 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PROCESSOR__IRQS_LIC_H
+#define PROCESSOR__IRQS_LIC_H
+#define FSP__PROCESSOR__IRQS_LIC_H                      1
+
+#define NR_VIC_IRQS 64UL
+
+#define AON_LIC_IRQ_BASE     NR_VIC_IRQS
+#define AON_LIC_IRQ_TOP_HSP1 (NR_VIC_IRQS)
+#define AON_LIC_IRQ_SPI1     (NR_VIC_IRQS + 1UL)
+#define AON_LIC_IRQ_SPI3     (NR_VIC_IRQS + 2UL)
+#define AON_LIC_IRQ_GPIO0    (NR_VIC_IRQS + 3UL)
+#define AON_LIC_IRQ_GPIO1    (NR_VIC_IRQS + 4UL)
+#define AON_LIC_IRQ_GPIO2    (NR_VIC_IRQS + 5UL)
+#define AON_LIC_IRQ_GPIO3    (NR_VIC_IRQS + 6UL)
+#define AON_LIC_IRQ_GPIO4    (NR_VIC_IRQS + 7UL)
+#define AON_LIC_IRQ_GPIO5    (NR_VIC_IRQS + 8UL)
+#define AON_LIC_IRQ_MAX      (NR_VIC_IRQS + 9UL)
+
+#define LIC0_IRQ_CONTEXT    lic0_irq_context
+#define LIC1_IRQ_CONTEXT    lic1_irq_context
+#define LIC2_IRQ_CONTEXT    lic2_irq_context
+#define LIC3_IRQ_CONTEXT    lic3_irq_context
+
+#ifndef __ASSEMBLER__
+
+#include <lic/lic-tegra-priv.h>
+
+extern struct tegra_lic_id tegra_lic_id_aon;
+extern lic_irq_context_t lic0_irq_context;
+extern lic_irq_context_t lic1_irq_context;
+extern lic_irq_context_t lic2_irq_context;
+extern lic_irq_context_t lic3_irq_context;
+
+#endif
+
+#endif /* PROCESSOR__IRQS_LIC_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/spi-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/spi-hw.h
new file mode 100644
index 0000000..d50a57f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/spi-hw.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SPI_HW_H
+#define SPI_HW_H
+#define FSP__PROCESSOR__SPI_HW_H                  1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/macros.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+
+#ifndef __ASSEMBLER__
+
+extern struct spi_ctlr spi_ctlr_spi1;
+extern struct spi_ctlr spi_ctlr_spi2;
+extern struct spi_ctlr spi_ctlr_spi3;
+
+#endif
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/tegra-aodmic-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/tegra-aodmic-hw.h
new file mode 100644
index 0000000..9ddd995
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/tegra-aodmic-hw.h
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PROCESSOR__TEGRA_AODMIC_HW_H
+#define PROCESSOR__TEGRA_AODMIC_HW_H
+#define FSP__PROCESSOR__TEGRA_AODMIC_HW_H               1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+#include <argpcdma_flv_8ch_non_safe.h>
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+#define AODMIC_GPCDMA_REQ_SEL GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_6
+
+extern struct tegra_aodmic_ctlr tegra_aodmic_ctlr_aon;
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/tegra-gpio-hw-params.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/tegra-gpio-hw-params.h
new file mode 100644
index 0000000..2c1b127
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/tegra-gpio-hw-params.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef PROCESSOR__GPIO_TEGRA_HW_PARAMS_H
+#define PROCESSOR__GPIO_TEGRA_HW_PARAMS_H
+#define FSP__PROCESSOR__GPIO_TEGRA_HW_PARAMS_H          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Late FSP headers */
+#include <processor/irqs-hw.h>          // for NV_AON_INTERRUPT_VIC1_BASE, ...
+#include <processor/irqs-lic.h>         // for AON_LIC_IRQ_GPIO0
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_LIC_H, "Header file missing or invalid.")
+
+#define TEGRA_MAIN_GPIO_ID0_IRQ         (AON_LIC_IRQ_GPIO0)
+#define TEGRA_MAIN_GPIO_ID1_IRQ         (AON_LIC_IRQ_GPIO1)
+#define TEGRA_MAIN_GPIO_ID2_IRQ         (AON_LIC_IRQ_GPIO2)
+#define TEGRA_MAIN_GPIO_ID3_IRQ         (AON_LIC_IRQ_GPIO3)
+#define TEGRA_MAIN_GPIO_ID4_IRQ         (AON_LIC_IRQ_GPIO4)
+#define TEGRA_MAIN_GPIO_ID5_IRQ         (AON_LIC_IRQ_GPIO5)
+#define TEGRA_AON_GPIO_IRQ              (NV_AON_INTERRUPT_GPIO + \
+                                         NV_AON_INTERRUPT_VIC1_BASE)
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/tegra-gpio-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/tegra-gpio-hw.h
new file mode 100644
index 0000000..85a0fe6
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/tegra-gpio-hw.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PROCESSOR__GPIO_TEGRA_HW_H
+#define PROCESSOR__GPIO_TEGRA_HW_H
+#define FSP__PROCESSOR__GPIO_TEGRA_HW_H                  1
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Late FSP headers */
+#include <soc-common/hw-const.h>        // for MK_U32_CONST
+
+/* Module-specific FSP headers */
+#include <gpio/tegra-gpio-priv.h>       // for struct tegra_gpio_id
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__GPIO__TEGRA_GPIO_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+/* GPIOs implemented by main GPIO controller */
+#define TEGRA_GPIO_BANK_ID_A    MK_U32_CONST(0)
+#define TEGRA_GPIO_BANK_ID_B    MK_U32_CONST(1)
+#define TEGRA_GPIO_BANK_ID_C    MK_U32_CONST(2)
+#define TEGRA_GPIO_BANK_ID_D    MK_U32_CONST(3)
+#define TEGRA_GPIO_BANK_ID_E    MK_U32_CONST(4)
+#define TEGRA_GPIO_BANK_ID_F    MK_U32_CONST(5)
+#define TEGRA_GPIO_BANK_ID_G    MK_U32_CONST(6)
+#define TEGRA_GPIO_BANK_ID_H    MK_U32_CONST(7)
+#define TEGRA_GPIO_BANK_ID_I    MK_U32_CONST(8)
+#define TEGRA_GPIO_BANK_ID_J    MK_U32_CONST(9)
+#define TEGRA_GPIO_BANK_ID_K    MK_U32_CONST(10)
+#define TEGRA_GPIO_BANK_ID_L    MK_U32_CONST(11)
+#define TEGRA_GPIO_BANK_ID_M    MK_U32_CONST(12)
+#define TEGRA_GPIO_BANK_ID_N    MK_U32_CONST(13)
+#define TEGRA_GPIO_BANK_ID_P    MK_U32_CONST(14)
+#define TEGRA_GPIO_BANK_ID_Q    MK_U32_CONST(15)
+#define TEGRA_GPIO_BANK_ID_R    MK_U32_CONST(16)
+#define TEGRA_GPIO_BANK_ID_S    MK_U32_CONST(17)
+#define TEGRA_GPIO_BANK_ID_T    MK_U32_CONST(18)
+#define TEGRA_GPIO_BANK_ID_U    MK_U32_CONST(19)
+#define TEGRA_GPIO_BANK_ID_V    MK_U32_CONST(20)
+#define TEGRA_GPIO_BANK_ID_X    MK_U32_CONST(21)
+#define TEGRA_GPIO_BANK_ID_Y    MK_U32_CONST(22)
+#define TEGRA_GPIO_BANK_ID_Z    MK_U32_CONST(23)
+#define TEGRA_GPIO_BANK_ID_AC   MK_U32_CONST(24)
+#define TEGRA_GPIO_BANK_ID_AD   MK_U32_CONST(25)
+#define TEGRA_GPIO_BANK_ID_AE   MK_U32_CONST(26)
+#define TEGRA_GPIO_BANK_ID_AF   MK_U32_CONST(27)
+#define TEGRA_GPIO_BANK_ID_AG   MK_U32_CONST(28)
+
+/* GPIOs implemented by AON GPIO controller */
+#define TEGRA_GPIO_BANK_ID_AA   MK_U32_CONST(0)
+#define TEGRA_GPIO_BANK_ID_BB   MK_U32_CONST(1)
+#define TEGRA_GPIO_BANK_ID_CC   MK_U32_CONST(2)
+#define TEGRA_GPIO_BANK_ID_DD   MK_U32_CONST(3)
+#define TEGRA_GPIO_BANK_ID_EE   MK_U32_CONST(4)
+#define TEGRA_GPIO_BANK_ID_GG   MK_U32_CONST(5)
+
+#define TEGRA_GPIO(bank, offset) ((TEGRA_GPIO_BANK_ID_##bank * 8) + offset)
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/tegra-uart-hw-params.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/tegra-uart-hw-params.h
new file mode 100644
index 0000000..ff82648
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/tegra-uart-hw-params.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2016-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__TEGRA_UART_HW_PARAMS_H
+#define PROCESSOR__TEGRA_UART_HW_PARAMS_H
+#define FSP__PROCESSOR__TEGRA_UART_HW_PARAMS_H          1
+
+#include <misc/ct-assert.h>
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <processor/irqs-hw.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+#ifndef TEGRA_UARTC_ENABLED
+#define TEGRA_UARTC_ENABLED
+#endif
+#define TEGRA_UARTC_IRQ NV_AON_INTERRUPT_UART_1
+
+#define TEGRA_UARTF_ENABLED
+#define TEGRA_UARTF_IRQ NV_AON_INTERRUPT_VIC1_BASE + NV_AON_INTERRUPT_UART6
+
+#define TEGRA_UARTH_ENABLED
+#define TEGRA_UARTH_IRQ NV_AON_INTERRUPT_VIC1_BASE + NV_AON_INTERRUPT_UART8
+
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/tke-tegra-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/tke-tegra-hw.h
new file mode 100644
index 0000000..15db7c7
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/aon/processor/tke-tegra-hw.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__TKE_TEGRA_HW_H
+#define PROCESSOR__TKE_TEGRA_HW_H
+#define FSP__PROCESSOR__TKE_TEGRA_HW_H                  1
+
+#include <misc/macros.h>
+
+extern struct tegra_tke_id tegra_tke_id_timer0;
+extern struct tegra_tke_id tegra_tke_id_timer1;
+extern struct tegra_tke_id tegra_tke_id_timer2;
+extern struct tegra_tke_id tegra_tke_id_timer3;
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#define TEGRA_TKE_TIMER_CLK_SRC_USECCNT		0
+#define TEGRA_TKE_TIMER_CLK_SRC_OSCCNT		1
+#define TEGRA_TKE_TIMER_CLK_SRC_TSC_BIT0	2
+#define TEGRA_TKE_TIMER_CLK_SRC_TSC_BIT12	3
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/bpmp/processor/cache-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/bpmp/processor/cache-hw.h
new file mode 100644
index 0000000..b59402c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/bpmp/processor/cache-hw.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__CACHE_HW_H
+#define PROCESSOR__CACHE_HW_H
+#define FSP__PROCESSOR__CACHE_HW_H                      1
+
+#define CACHE_LINE_SIZE	32
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/bpmp/processor/debug-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/bpmp/processor/debug-hw.h
new file mode 100644
index 0000000..e94d655
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/bpmp/processor/debug-hw.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__DEBUG_HW_H
+#define PROCESSOR__DEBUG_HW_H
+#define FSP__PROCESSOR__DEBUG_HW_H                      1
+
+#include <address_map_new.h>
+
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+#ifdef _NV_BUILD_LINSIM_
+#define TEGRA_DBG_UART_BASE     NV_ADDRESS_MAP_UARTA_BASE
+#elif defined(_NV_BUILD_FPGA_)
+#define TEGRA_DBG_UART_BASE     NV_ADDRESS_MAP_UARTC_BASE
+#else
+#define TEGRA_DBG_UART_BASE     NV_ADDRESS_MAP_UARTC_BASE
+#define TEGRA_DBG_UART_CLK      tegra_clk_uartc
+#define TEGRA_DBG_UART_RST      tegra_rst_uartc
+#define TEGRA_DBG_UART_BAUD     115200
+#endif
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/bpmp/processor/i2c-tegra-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/bpmp/processor/i2c-tegra-hw.h
new file mode 100644
index 0000000..4827c58
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/bpmp/processor/i2c-tegra-hw.h
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PROCESSOR__I2C_TEGRA_HW_H
+#define PROCESSOR__I2C_TEGRA_HW_H
+#define FSP__PROCESSOR__I2C_TEGRA_HW_H                  1
+
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/bitops.h>
+
+/* Module-specific FSP headers */
+#include <soc-common/i2c-defs.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__I2C_DEFS_H, "Header file missing or invalid.")
+
+struct i2c_hw_handle;
+
+struct i2c_hw_handle {
+    const uint32_t ctrl_id;
+    const uint32_t base;
+    const uint32_t clk_id;
+    const uint32_t rst_id;
+    const uint32_t irq_no;
+    const bool is_multimaster;
+};
+
+/**
+ * @brief BIT vector for Valid i2c ids for BPMP cluster.
+ */
+#define VALID_I2C_IDS   (BIT(TEGRA234_I2C5))
+
+const struct i2c_hw_handle *i2c_get_hw_handle(uint32_t ctrl_id);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/bpmp/processor/irqs-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/bpmp/processor/irqs-hw.h
new file mode 100644
index 0000000..cafa758
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/bpmp/processor/irqs-hw.h
@@ -0,0 +1,88 @@
+/*
+* Copyright (c) 2016-2019 NVIDIA CORPORATION.  All rights reserved.
+*
+* NVIDIA CORPORATION and its licensors retain all intellectual property
+* and proprietary rights in and to this software, related documentation
+* and any modifications thereto.  Any use, reproduction, disclosure or
+* distribution of this software and related documentation without an express
+* license agreement from NVIDIA CORPORATION is strictly prohibited.
+*/
+
+#ifndef PROCESSOR__IRQS_HW_H
+#define PROCESSOR__IRQS_HW_H
+#define FSP__PROCESSOR__IRQS_HW_H                       1
+
+#define MAX_VIC_CONTROLLER       2
+
+#define NV_BPMP_IRQ_VIC0_BASE	0
+#define NV_BPMP_IRQ_VIC1_BASE	32
+
+// VIC0 interrupts
+#define NV_BPMP_IRQ_WDTIRQ 0
+#define NV_BPMP_IRQ_TIMER0 1
+#define NV_BPMP_IRQ_TIMER1 2
+#define NV_BPMP_IRQ_TIMER2 3
+#define NV_BPMP_IRQ_TIMER3 4
+#define NV_BPMP_IRQ_WDTFIQ 5
+#define NV_BPMP_IRQ_HSP_DB 6
+#define NV_BPMP_IRQ_RSVD7  7
+#define NV_BPMP_IRQ_PM     8
+#define NV_BPMP_IRQ_CVC    9
+#define NV_BPMP_IRQ_H1XSNC 10
+#define NV_BPMP_IRQ_RSVD11 11
+#define NV_BPMP_IRQ_RSVD12 12
+#define NV_BPMP_IRQ_WAKE0  13
+#define NV_BPMP_IRQ_WAKE1  14
+#define NV_BPMP_IRQ_WAKE2  15
+#define NV_BPMP_IRQ_LIC0   16
+#define NV_BPMP_IRQ_LIC1   17
+#define NV_BPMP_IRQ_RSVD18 18
+#define NV_BPMP_IRQ_RSVD19 19
+#define NV_BPMP_IRQ_DMA0   20
+#define NV_BPMP_IRQ_DMA1   21
+#define NV_BPMP_IRQ_DMA2   22
+#define NV_BPMP_IRQ_DMA3   23
+#define NV_BPMP_IRQ_HSP_SI_0 24
+#define NV_BPMP_IRQ_FPUINT 25
+#define NV_BPMP_IRQ_GPMU   26
+#define NV_BPMP_IRQ_EDP    27
+#define NV_BPMP_IRQ_SCTHRM 28
+#define NV_BPMP_IRQ_RSVD29 29
+#define NV_BPMP_IRQ_AONPWRI2C 30
+#define NV_BPMP_IRQ_SOCPWRI2C 31
+
+// VIC1 interrupts
+#define NV_BPMP_IRQ_CPM0   0
+#define NV_BPMP_IRQ_CPM1   1
+#define NV_BPMP_IRQ_CPM3   2
+#define NV_BPMP_IRQ_RSVD3  3
+#define NV_BPMP_IRQ_RSVD4  4
+#define NV_BPMP_IRQ_RSVD5  5
+#define NV_BPMP_IRQ_UART   6
+#define NV_BPMP_IRQ_QSPI   7
+#define NV_BPMP_IRQ_PMUIRQ 8
+#define NV_BPMP_IRQ_CNTRL_ACTMON   9
+#define NV_BPMP_IRQ_BPMP_ACTMON    10
+#define NV_BPMP_IRQ_SIMON0 11
+#define NV_BPMP_IRQ_SIMON1 12
+#define NV_BPMP_IRQ_SIMON2 13
+#define NV_BPMP_IRQ_SIMON3 14
+#define NV_BPMP_IRQ_APBERR 15
+#define NV_BPMP_IRQ_GTE    16
+#define NV_BPMP_IRQ_APBSEC 17
+#define NV_BPMP_IRQ_CTIIRQ 18
+#define NV_BPMP_IRQ_HSP_SI_1 19
+#define NV_BPMP_IRQ_HSP_SI_2 20
+#define NV_BPMP_IRQ_HSP_SI_3 21
+#define NV_BPMP_IRQ_HSP_SI_4 22
+#define NV_BPMP_IRQ_CAR      23
+#define NV_BPMP_IRQ_V1RSVD24 24
+#define NV_BPMP_IRQ_V1RSVD25 25
+#define NV_BPMP_IRQ_V1RSVD26 26
+#define NV_BPMP_IRQ_V1RSVD27 27
+#define NV_BPMP_IRQ_V1RSVD28 28
+#define NV_BPMP_IRQ_V1RSVD29 29
+#define NV_BPMP_IRQ_V1RSVD30 30
+#define NV_BPMP_IRQ_V1RSVD31 31
+
+#endif /* PROCESSOR__IRQS_HW_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/bpmp/processor/tke-tegra-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/bpmp/processor/tke-tegra-hw.h
new file mode 100644
index 0000000..0461d04
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/bpmp/processor/tke-tegra-hw.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__TKE_TEGRA_HW_H
+#define PROCESSOR__TKE_TEGRA_HW_H
+#define FSP__PROCESSOR__TKE_TEGRA_HW_H                  1
+
+extern const struct tegra_tke_id tegra_tke_id_timer0;
+extern const struct tegra_tke_id tegra_tke_id_timer1;
+extern const struct tegra_tke_id tegra_tke_id_timer2;
+extern const struct tegra_tke_id tegra_tke_id_timer3;
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/dce/hw-config/hsp-config.h b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/hw-config/hsp-config.h
new file mode 100644
index 0000000..815bd84
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/hw-config/hsp-config.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef HW_CONFIG__HSP_CONFIG_H
+#define HW_CONFIG__HSP_CONFIG_H
+#define FSP__HW_CONFIG__HSP_CONFIG_H                      1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+/**
+ * R5 clusters on T234 no longer suffer from bug 200395605 and therefore
+ * do not need to exclude bits.
+ */
+#define HSP_SS_FORBIDDEN_BITS MK_U32_CONST(0)
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/dce/hw-config/vic-irqs.h b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/hw-config/vic-irqs.h
new file mode 100644
index 0000000..83e3995
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/hw-config/vic-irqs.h
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2018-2019 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef HW_CONFIG__VIC_IRQS_H
+#define HW_CONFIG__VIC_IRQS_H
+#define FSP__HW_CONFIG__VIC_IRQS_H                      1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <soc-common/hw-const.h>
+
+/* Hardware headers */
+#include <arsce_interrupts.h>
+#include <vic/tegra-vic.h>
+
+/* Late FSP headers */
+
+#define NUM_VICS                        2
+
+/*
+ * VIC0 Interrupts
+ */
+#define ISR_NUM_WDTFIQ                  NV_SCE_INTERRUPT_WDTFIQ
+#define ISR_NUM_WDTIRQ                  NV_SCE_INTERRUPT_WDTIRQ
+#define ISR_NUM_TIMER0                  NV_SCE_INTERRUPT_TIMER0
+#define ISR_NUM_TIMER1                  NV_SCE_INTERRUPT_TIMER1
+#define ISR_NUM_TIMER2                  NV_SCE_INTERRUPT_TIMER2
+#define ISR_NUM_TIMER3                  NV_SCE_INTERRUPT_TIMER3
+#define ISR_NUM_MBOX                    NV_SCE_INTERRUPT_MBOX
+#define ISR_NUM_GTE                     NV_SCE_INTERRUPT_GTE
+#define ISR_NUM_PMU                     NV_SCE_INTERRUPT_PMU
+#define ISR_NUM_DMA0                    NV_SCE_INTERRUPT_DMA0
+#define ISR_NUM_DMA1                    NV_SCE_INTERRUPT_DMA1
+#define ISR_NUM_DMA2                    NV_SCE_INTERRUPT_DMA2
+#define ISR_NUM_DMA3                    NV_SCE_INTERRUPT_DMA3
+#define ISR_NUM_DMA4                    NV_SCE_INTERRUPT_DMA4
+#define ISR_NUM_DMA5                    NV_SCE_INTERRUPT_DMA5
+#define ISR_NUM_DMA6                    NV_SCE_INTERRUPT_DMA6
+#define ISR_NUM_DMA7                    NV_SCE_INTERRUPT_DMA7
+#define ISR_NUM_LIC0                    NV_SCE_INTERRUPT_LIC0
+#define ISR_NUM_LIC1                    NV_SCE_INTERRUPT_LIC1
+#define ISR_NUM_LIC2                    NV_SCE_INTERRUPT_LIC2
+#define ISR_NUM_LIC3                    NV_SCE_INTERRUPT_LIC3
+#define ISR_NUM_V0RSVD21                NV_SCE_INTERRUPT_V0RSVD21
+#define ISR_NUM_HSM_CRITICAL_ERR        NV_SCE_INTERRUPT_HSM_CRITICAL_ERR
+#define ISR_NUM_VI_HP                   NV_SCE_INTERRUPT_VI_HP
+#define ISR_NUM_VI_LP                   NV_SCE_INTERRUPT_VI_LP
+#define ISR_NUM_HSM_HP                  NV_SCE_INTERRUPT_HSM_HP
+#define ISR_NUM_HSM_LP                  NV_SCE_INTERRUPT_HSM_LP
+#define ISR_NUM_V0RSVD27                NV_SCE_INTERRUPT_V0RSVD27
+#define ISR_NUM_V0RSVD28                NV_SCE_INTERRUPT_V0RSVD28
+#define ISR_NUM_V0RSVD29                NV_SCE_INTERRUPT_V0RSVD29
+#define ISR_NUM_V0RSVD30                NV_SCE_INTERRUPT_V0RSVD30
+#define ISR_NUM_V0RSVD31                NV_SCE_INTERRUPT_V0RSVD31
+
+/*
+ * VIC1 Interrupts
+ */
+#define ISR_NUM_V1RSVD0                 NV_SCE_INTERRUPT_V1RSVD0
+#define ISR_NUM_ACTMON                  NV_SCE_INTERRUPT_ACTMON
+#define ISR_NUM_FPUINT                  NV_SCE_INTERRUPT_FPUINT
+#define ISR_NUM_PM                      NV_SCE_INTERRUPT_PM
+#define ISR_NUM_MC_SBE                  NV_SCE_INTERRUPT_MC_SBE
+#define ISR_NUM_NOC_SECURE              NV_SCE_INTERRUPT_NOC_SECURE
+#define ISR_NUM_CAR                     NV_SCE_INTERRUPT_CAR
+#define ISR_NUM_V1RSVD7                 NV_SCE_INTERRUPT_V1RSVD7
+#define ISR_NUM_V1RSVD8                 NV_SCE_INTERRUPT_V1RSVD8
+#define ISR_NUM_V1RSVD9                 NV_SCE_INTERRUPT_V1RSVD9
+#define ISR_NUM_V1RSVD10                NV_SCE_INTERRUPT_V1RSVD10
+#define ISR_NUM_V1RSVD11                NV_SCE_INTERRUPT_V1RSVD11
+#define ISR_NUM_V1RSVD12                NV_SCE_INTERRUPT_V1RSVD12
+#define ISR_NUM_V1RSVD13                NV_SCE_INTERRUPT_V1RSVD13
+#define ISR_NUM_TOP0_HSP_DB             NV_SCE_INTERRUPT_TOP0_HSP_DB
+#define ISR_NUM_V1RSVD15                NV_SCE_INTERRUPT_V1RSVD15
+#define ISR_NUM_V1RSVD16                NV_SCE_INTERRUPT_V1RSVD16
+#define ISR_NUM_CTIIRQ                  NV_SCE_INTERRUPT_CTIIRQ
+#define ISR_NUM_V1RSVD18                NV_SCE_INTERRUPT_V1RSVD18
+#define ISR_NUM_I2C1                    NV_SCE_INTERRUPT_I2C1
+#define ISR_NUM_I2C3                    NV_SCE_INTERRUPT_I2C3
+#define ISR_NUM_I2C8                    NV_SCE_INTERRUPT_I2C8
+#define ISR_NUM_DISP                    NV_SCE_INTERRUPT_DISP
+#define ISR_NUM_V1RSVD23                NV_SCE_INTERRUPT_V1RSVD23
+#define ISR_NUM_HSP2_SI_0               NV_SCE_INTERRUPT_HSP2_SI_0
+#define ISR_NUM_HSP2_SI_1               NV_SCE_INTERRUPT_HSP2_SI_1
+#define ISR_NUM_HSP2_SI_2               NV_SCE_INTERRUPT_HSP2_SI_2
+#define ISR_NUM_HSP2_SI_3               NV_SCE_INTERRUPT_HSP2_SI_3
+#define ISR_NUM_HSP2_SI_4               NV_SCE_INTERRUPT_HSP2_SI_4
+#define ISR_NUM_HSP2_SI_5               NV_SCE_INTERRUPT_HSP2_SI_5
+#define ISR_NUM_HSP2_SI_6               NV_SCE_INTERRUPT_HSP2_SI_6
+#define ISR_NUM_HSP2_SI_7               NV_SCE_INTERRUPT_HSP2_SI_7
+
+/*
+ * Define the various vectors where the VIC and IRQ are encoded into one value
+ */
+#define INTERRUPT_WDTFIQ                TEGRA_INTERRUPT(0, ISR_NUM_WDTFIQ)
+#define INTERRUPT_WDTIRQ                TEGRA_INTERRUPT(0, ISR_NUM_WDTIRQ)
+#define INTERRUPT_TIMER0                TEGRA_INTERRUPT(0, ISR_NUM_TIMER0)
+#define INTERRUPT_TIMER1                TEGRA_INTERRUPT(0, ISR_NUM_TIMER1)
+#define INTERRUPT_TIMER2                TEGRA_INTERRUPT(0, ISR_NUM_TIMER2)
+#define INTERRUPT_TIMER3                TEGRA_INTERRUPT(0, ISR_NUM_TIMER3)
+#define INTERRUPT_MBOX                  TEGRA_INTERRUPT(0, ISR_NUM_MBOX)
+#define INTERRUPT_GTE                   TEGRA_INTERRUPT(0, ISR_NUM_GTE)
+#define INTERRUPT_PMU                   TEGRA_INTERRUPT(0, ISR_NUM_PMU)
+#define INTERRUPT_DMA0                  TEGRA_INTERRUPT(0, ISR_NUM_DMA0)
+#define INTERRUPT_DMA1                  TEGRA_INTERRUPT(0, ISR_NUM_DMA1)
+#define INTERRUPT_DMA2                  TEGRA_INTERRUPT(0, ISR_NUM_DMA2)
+#define INTERRUPT_DMA3                  TEGRA_INTERRUPT(0, ISR_NUM_DMA3)
+#define INTERRUPT_DMA4                  TEGRA_INTERRUPT(0, ISR_NUM_DMA4)
+#define INTERRUPT_DMA5                  TEGRA_INTERRUPT(0, ISR_NUM_DMA5)
+#define INTERRUPT_DMA6                  TEGRA_INTERRUPT(0, ISR_NUM_DMA6)
+#define INTERRUPT_DMA7                  TEGRA_INTERRUPT(0, ISR_NUM_DMA7)
+#define INTERRUPT_LIC0                  TEGRA_INTERRUPT(0, ISR_NUM_LIC0)
+#define INTERRUPT_LIC1                  TEGRA_INTERRUPT(0, ISR_NUM_LIC1)
+#define INTERRUPT_LIC2                  TEGRA_INTERRUPT(0, ISR_NUM_LIC2)
+#define INTERRUPT_LIC3                  TEGRA_INTERRUPT(0, ISR_NUM_LIC3)
+#define INTERRUPT_V0RSVD21              TEGRA_INTERRUPT(0, ISR_NUM_V0RSVD21)
+#define INTERRUPT_HSM_CRIT_ERR          TEGRA_INTERRUPT(0, ISR_NUM_HSM_CRITICAL_ERR)
+#define INTERRUPT_VI_HP                 TEGRA_INTERRUPT(0, ISR_NUM_VI_HP)
+#define INTERRUPT_VI_LP                 TEGRA_INTERRUPT(0, ISR_NUM_VI_LP)
+#define INTERRUPT_HSM_HP                TEGRA_INTERRUPT(0, ISR_NUM_HSM_HP)
+#define INTERRUPT_HSM_LP                TEGRA_INTERRUPT(0, ISR_NUM_HSM_LP)
+#define INTERRUPT_V0RSVD27              TEGRA_INTERRUPT(0, ISR_NUM_V0RSVD27)
+#define INTERRUPT_V0RSVD28              TEGRA_INTERRUPT(0, ISR_NUM_V0RSVD28)
+#define INTERRUPT_V0RSVD29              TEGRA_INTERRUPT(0, ISR_NUM_V0RSVD29)
+#define INTERRUPT_V0RSVD30              TEGRA_INTERRUPT(0, ISR_NUM_V0RSVD30)
+#define INTERRUPT_V0RSVD31              TEGRA_INTERRUPT(0, ISR_NUM_V0RSVD31)
+#define INTERRUPT_V1RSVD0               TEGRA_INTERRUPT(1, ISR_NUM_V1RSVD0)
+#define INTERRUPT_ACTMON                TEGRA_INTERRUPT(1, ISR_NUM_ACTMON)
+#define INTERRUPT_FPUINT                TEGRA_INTERRUPT(1, ISR_NUM_FPUINT)
+#define INTERRUPT_PM                    TEGRA_INTERRUPT(1, ISR_NUM_PM)
+#define INTERRUPT_MC_SBE                TEGRA_INTERRUPT(1, ISR_NUM_MC_SBE)
+#define INTERRUPT_NOC_SECURE            TEGRA_INTERRUPT(1, ISR_NUM_NOC_SECURE)
+#define INTERRUPT_CAR                   TEGRA_INTERRUPT(1, ISR_NUM_CAR)
+#define INTERRUPT_V1RSVD7               TEGRA_INTERRUPT(1, ISR_NUM_V1RSVD7)
+#define INTERRUPT_V1RSVD8               TEGRA_INTERRUPT(1, ISR_NUM_V1RSVD8)
+#define INTERRUPT_V1RSVD9               TEGRA_INTERRUPT(1, ISR_NUM_V1RSVD9)
+#define INTERRUPT_V1RSVD10              TEGRA_INTERRUPT(1, ISR_NUM_V1RSVD10)
+#define INTERRUPT_V1RSVD11              TEGRA_INTERRUPT(1, ISR_NUM_V1RSVD11)
+#define INTERRUPT_V1RSVD12              TEGRA_INTERRUPT(1, ISR_NUM_V1RSVD12)
+#define INTERRUPT_V1RSVD13              TEGRA_INTERRUPT(1, ISR_NUM_V1RSVD13)
+#define INTERRUPT_TOP0_HSP_DB           TEGRA_INTERRUPT(1, ISR_NUM_TOP0_HSP_DB)
+#define INTERRUPT_V1RSVD15              TEGRA_INTERRUPT(1, ISR_NUM_V1RSVD15)
+#define INTERRUPT_V1RSVD16              TEGRA_INTERRUPT(1, ISR_NUM_V1RSVD16)
+#define INTERRUPT_CTIIRQ                TEGRA_INTERRUPT(1, ISR_NUM_CTIIRQ)
+#define INTERRUPT_V1RSVD18              TEGRA_INTERRUPT(1, ISR_NUM_V1RSVD18)
+#define INTERRUPT_I2C1                  TEGRA_INTERRUPT(1, ISR_NUM_I2C1)
+#define INTERRUPT_I2C3                  TEGRA_INTERRUPT(1, ISR_NUM_I2C3)
+#define INTERRUPT_I2C8                  TEGRA_INTERRUPT(1, ISR_NUM_I2C8)
+#define INTERRUPT_DISP                  TEGRA_INTERRUPT(1, ISR_NUM_DISP)
+#define INTERRUPT_V1RSVD23              TEGRA_INTERRUPT(1, ISR_NUM_V1RSVD23)
+#define INTERRUPT_HSP2_SI_0             TEGRA_INTERRUPT(1, ISR_NUM_HSP2_SI_0)
+#define INTERRUPT_HSP2_SI_1             TEGRA_INTERRUPT(1, ISR_NUM_HSP2_SI_1)
+#define INTERRUPT_HSP2_SI_2             TEGRA_INTERRUPT(1, ISR_NUM_HSP2_SI_2)
+#define INTERRUPT_HSP2_SI_3             TEGRA_INTERRUPT(1, ISR_NUM_HSP2_SI_3)
+#define INTERRUPT_HSP2_SI_4             TEGRA_INTERRUPT(1, ISR_NUM_HSP2_SI_4)
+#define INTERRUPT_HSP2_SI_5             TEGRA_INTERRUPT(1, ISR_NUM_HSP2_SI_5)
+#define INTERRUPT_HSP2_SI_6             TEGRA_INTERRUPT(1, ISR_NUM_HSP2_SI_6)
+#define INTERRUPT_HSP2_SI_7             TEGRA_INTERRUPT(1, ISR_NUM_HSP2_SI_7)
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/dce/port/gpcdma-port-priv.h b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/port/gpcdma-port-priv.h
new file mode 100644
index 0000000..4263bc2
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/port/gpcdma-port-priv.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GPCDMA__GPCDMA_PORT_PRIV_H
+#define GPCDMA__GPCDMA_PORT_PRIV_H
+#define FSP__PORT__GPCDMA_PORT_PRIV_H                      0
+
+/**
+ * @file gpcdma/gpcdma-port-priv-.h
+ * @brief provides context that is specific to the port layer.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* HW headers */
+
+/* Late FSP headers */
+
+struct gpcdma_hw_handle {
+    const struct tegra_rst *rst;
+};
+
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/dce/port/uart-port-priv.h b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/port/uart-port-priv.h
new file mode 100644
index 0000000..fac77ec
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/port/uart-port-priv.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef UART__UART_PORT_PRIV_H
+#define UART__UART_PORT_PRIV_H
+#define FSP__PORT__UART_PORT_PRIV_H                      0
+
+#include <osa/rtos-queue.h>
+
+/**
+ * @file uart/uart-port-priv-.h
+ * @brief provides context that is specific to the port layer.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* HW headers */
+
+/* Late FSP headers */
+
+typedef rtosQueueHandle uart_queue_t;
+
+struct uart_hw_handle {
+    const struct tegra_clk *clk;
+    const struct tegra_rst *rst;
+};
+
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/cache-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/cache-hw.h
new file mode 100644
index 0000000..b59402c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/cache-hw.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__CACHE_HW_H
+#define PROCESSOR__CACHE_HW_H
+#define FSP__PROCESSOR__CACHE_HW_H                      1
+
+#define CACHE_LINE_SIZE	32
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/debug-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/debug-hw.h
new file mode 100644
index 0000000..57da300
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/debug-hw.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__DEBUG_HW_H
+#define PROCESSOR__DEBUG_HW_H
+#define FSP__PROCESSOR__DEBUG_HW_H                      1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <processor/tegra-uart-hw-params.h>
+#include <uart/tegra-uart-priv.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__TEGRA_UART_HW_PARAMS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__UART__TEGRA_UART_PRIV_H, "Header file missing or invalid.")
+
+#define DEBUG_COMB_UART      comb_uart_id_dce
+
+extern const struct comb_uart_id comb_uart_id_dce;
+
+#ifdef TEGRA_UARTA_ENABLED
+extern struct tegra_uart_ctlr tegra_uart_ctlr_uarta;
+
+#ifndef DEBUG_UART
+#define DEBUG_UART      tegra_uart_ctlr_uarta
+#endif
+#define TEGRA_DBG_UART_BASE     NV_ADDRESS_MAP_UARTA_BASE
+
+#endif
+
+#ifdef TEGRA_UARTC_ENABLED
+extern struct tegra_uart_ctlr tegra_uart_ctlr_uartc;
+
+#ifndef DEBUG_UART
+#define DEBUG_UART      tegra_uart_ctlr_uartc
+#endif
+#define TEGRA_DBG_UART_BASE     NV_ADDRESS_MAP_UARTC_BASE
+
+#endif
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/gpcdma-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/gpcdma-hw.h
new file mode 100644
index 0000000..7617694
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/gpcdma-hw.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GPCDMA_HW_H
+#define GPCDMA_HW_H
+#define FSP__PROCESSOR__GPCDMA_HW_H                  1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/macros.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+
+#define GPCDMA_CHAN0    gpcdma_chan0
+#define GPCDMA_CHAN1    gpcdma_chan1
+#define GPCDMA_CHAN2    gpcdma_chan2
+#define GPCDMA_CHAN3    gpcdma_chan3
+#define GPCDMA_CHAN4    gpcdma_chan4
+#define GPCDMA_CHAN5    gpcdma_chan5
+#define GPCDMA_CHAN6    gpcdma_chan6
+#define GPCDMA_CHAN7    gpcdma_chan7
+
+#ifndef __ASSEMBLER__
+
+extern struct gpcdma_id gpcdma_id_dce;
+extern struct gpcdma_channel gpcdma_chan0;
+extern struct gpcdma_channel gpcdma_chan1;
+extern struct gpcdma_channel gpcdma_chan2;
+extern struct gpcdma_channel gpcdma_chan3;
+extern struct gpcdma_channel gpcdma_chan4;
+extern struct gpcdma_channel gpcdma_chan5;
+extern struct gpcdma_channel gpcdma_chan6;
+extern struct gpcdma_channel gpcdma_chan7;
+
+#endif
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/gpio-tegra.h b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/gpio-tegra.h
new file mode 100644
index 0000000..eaa6b25
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/gpio-tegra.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GPIO_TEGRA_H
+#define GPIO_TEGRA_H
+#define FSP__PROCESSOR__GPIO_TEGRA_H                  1
+
+#include <gpio/tegra-gpio.h>            // for #define MAX_GPIO_CONTROLLERS
+#include <gpio/tegra-gpio-priv.h>       // for struct tegra_gpio_id
+
+/* DCE GPIO ID */
+extern struct tegra_gpio_id * tegra_gpio_id_dce[MAX_GPIO_CONTROLLERS];
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/hsp-tegra-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/hsp-tegra-hw.h
new file mode 100644
index 0000000..c292d42
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/hsp-tegra-hw.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PROCESSOR__HSP_TEGRA_HW_H
+#define PROCESSOR__HSP_TEGRA_HW_H
+#define FSP__PROCESSOR__HSP_TEGRA_HW_H                  1
+
+#include <misc/ct-assert.h>
+#include <soc-common/hsp-tegra-top-hw.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HSP_TEGRA_TOP_HW_H, "Header file missing or invalid.")
+
+#define TEGRA_HSP_ID_MBOX tegra_hsp_id_dce
+#define TEGRA_HSP_ID_DB   tegra_hsp_id_top0
+
+#ifndef __ASSEMBLER__
+
+/* This is the TOP HSP instance w/ AON interrupts */
+extern struct tegra_hsp_id tegra_hsp_id_top0;
+extern struct tegra_hsp_id tegra_hsp_id_self;
+extern struct tegra_hsp_id tegra_hsp_id_dce;
+
+#endif
+
+#endif /* PROCESSOR__HSP_TEGRA_HW_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/i2c-tegra-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/i2c-tegra-hw.h
new file mode 100644
index 0000000..fe7a52d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/i2c-tegra-hw.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef I2C_TEGRA_HW_H
+#define I2C_TEGRA_HW_H
+#define FSP__PROCESSOR__I2C_TEGRA_HW_H                  1
+
+/* Compiler headers */
+#include <stdbool.h>              // for bool
+#include <stdint.h>               // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>       // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/bitops.h>          // for BIT
+
+/* Module-specific FSP headers */
+#include <soc-common/i2c-defs.h>  // for FSP__SOC_COMMON__I2C_DEFS_H, TEGRA1...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__SOC_COMMON__I2C_DEFS_H, "Header file missing or invalid.")
+
+struct i2c_hw_handle;
+
+struct i2c_hw_handle {
+    const uint32_t ctrl_id;
+    const uint32_t base;
+    const struct tegra_clk *clk_data;
+    const struct tegra_rst *rst_data;
+    const uint32_t irq_no;
+    bool is_multimaster;
+};
+
+/**
+ * @brief BIT vector for Valid i2c ids for DCE cluster.
+ */
+#define VALID_I2C_IDS   (BIT(TEGRA234_I2C4) | BIT(TEGRA234_I2C6) | BIT(TEGRA234_I2C7))
+
+const struct i2c_hw_handle *i2c_get_hw_handle(uint32_t ctrl_id);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/irqs-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/irqs-hw.h
new file mode 100644
index 0000000..a623dc1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/irqs-hw.h
@@ -0,0 +1,95 @@
+/*
+ * Copyright (c) 2016-2019 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__IRQS_HW_H
+#define PROCESSOR__IRQS_HW_H
+#define FSP__PROCESSOR__IRQS_HW_H                       1
+
+#define MAX_VIC_CONTROLLER       2
+
+#ifndef NV_DCE_IRQ
+#define NV_DCE_IRQ(x) (x ## U)
+#endif
+
+/*
+ * XXX:TODO
+ *
+ * Validate that all of the interrupts are correct
+ */
+
+/* VIC0 interrupts */
+#define NV_DCE_IRQ_WDTFIQ       NV_DCE_IRQ(0)
+#define NV_DCE_IRQ_WDTIRQ       NV_DCE_IRQ(1)
+#define NV_DCE_IRQ_TIMER0       NV_DCE_IRQ(2)
+#define NV_DCE_IRQ_TIMER1       NV_DCE_IRQ(3)
+#define NV_DCE_IRQ_TIMER2       NV_DCE_IRQ(4)
+#define NV_DCE_IRQ_TIMER3       NV_DCE_IRQ(5)
+#define NV_DCE_IRQ_MBOX         NV_DCE_IRQ(6)
+#define NV_DCE_IRQ_GTE          NV_DCE_IRQ(7)
+#define NV_DCE_IRQ_PMU          NV_DCE_IRQ(8)
+#define NV_DCE_IRQ_DMA0         NV_DCE_IRQ(9)
+#define NV_DCE_IRQ_DMA1         NV_DCE_IRQ(10)
+#define NV_DCE_IRQ_DMA2         NV_DCE_IRQ(11)
+#define NV_DCE_IRQ_DMA3         NV_DCE_IRQ(12)
+#define NV_DCE_IRQ_DMA4         NV_DCE_IRQ(13)
+#define NV_DCE_IRQ_DMA5         NV_DCE_IRQ(14)
+#define NV_DCE_IRQ_DMA6         NV_DCE_IRQ(15)
+#define NV_DCE_IRQ_DMA7         NV_DCE_IRQ(16)
+#define NV_DCE_IRQ_LIC0         NV_DCE_IRQ(17)
+#define NV_DCE_IRQ_LIC1         NV_DCE_IRQ(18)
+#define NV_DCE_IRQ_LIC2         NV_DCE_IRQ(19)
+#define NV_DCE_IRQ_LIC3         NV_DCE_IRQ(20)
+#define NV_DCE_IRQ_V0RSVD21     NV_DCE_IRQ(21)
+#define NV_DCE_IRQ_V0RSVD22     NV_DCE_IRQ(22)
+#define NV_DCE_IRQ_VI_HP        NV_DCE_IRQ(23)
+#define NV_DCE_IRQ_VI_LP        NV_DCE_IRQ(24)
+#define NV_DCE_IRQ_HSM_HP       NV_DCE_IRQ(25)
+#define NV_DCE_IRQ_HSM_LP       NV_DCE_IRQ(26)
+#define NV_DCE_IRQ_CPU_ERR      NV_DCE_IRQ(27)
+#define NV_DCE_IRQ_SC_SYSINTR   NV_DCE_IRQ(28)
+#define NV_DCE_IRQ_SC_SYSINTL   NV_DCE_IRQ(29)
+#define NV_DCE_IRQ_SC_WARN      NV_DCE_IRQ(30)
+#define NV_DCE_IRQ_SC_INFO      NV_DCE_IRQ(31)
+
+/* VIC1 interrupts */
+#define NV_DCE_IRQ_APBERR       NV_DCE_IRQ(32)
+#define NV_DCE_IRQ_ACTMON       NV_DCE_IRQ(33)
+#define NV_DCE_IRQ_FPUINT       NV_DCE_IRQ(34)
+#define NV_DCE_IRQ_PM           NV_DCE_IRQ(35)
+#define NV_DCE_IRQ_MC_SBE       NV_DCE_IRQ(36)
+#define NV_DCE_IRQ_APBSEC       NV_DCE_IRQ(37)
+#define NV_DCE_IRQ_CAR          NV_DCE_IRQ(38)
+#define NV_DCE_IRQ_V1RSVD7      NV_DCE_IRQ(39)
+#define NV_DCE_IRQ_V1RSVD8      NV_DCE_IRQ(40)
+#define NV_DCE_IRQ_V1RSVD9      NV_DCE_IRQ(41)
+#define NV_DCE_IRQ_V1RSVD10     NV_DCE_IRQ(42)
+#define NV_DCE_IRQ_V1RSVD11     NV_DCE_IRQ(43)
+#define NV_DCE_IRQ_V1RSVD12     NV_DCE_IRQ(44)
+#define NV_DCE_IRQ_V1RSVD13     NV_DCE_IRQ(45)
+#define NV_DCE_IRQ_TOP0_HSP_DB  NV_DCE_IRQ(46)
+#define NV_DCE_IRQ_V1RSVD15     NV_DCE_IRQ(47)
+#define NV_DCE_IRQ_V1RSVD16     NV_DCE_IRQ(48)
+#define NV_DCE_IRQ_CTIIRQ       NV_DCE_IRQ(49)
+#define NV_DCE_IRQ_V1RSVD18     NV_DCE_IRQ(50)
+#define NV_DCE_IRQ_I2C1         NV_DCE_IRQ(51)
+#define NV_DCE_IRQ_I2C3         NV_DCE_IRQ(52)
+#define NV_DCE_IRQ_I2C8         NV_DCE_IRQ(53)
+#define NV_DCE_IRQ_V1RSVD22     NV_DCE_IRQ(54)
+#define NV_DCE_IRQ_V1RSVD23     NV_DCE_IRQ(55)
+#define NV_DCE_IRQ_V1RSVD24     NV_DCE_IRQ(56)
+#define NV_DCE_IRQ_V1RSVD25     NV_DCE_IRQ(57)
+#define NV_DCE_IRQ_V1RSVD26     NV_DCE_IRQ(58)
+#define NV_DCE_IRQ_V1RSVD27     NV_DCE_IRQ(59)
+#define NV_DCE_IRQ_V1RSVD28     NV_DCE_IRQ(60)
+#define NV_DCE_IRQ_V1RSVD29     NV_DCE_IRQ(61)
+#define NV_DCE_IRQ_V1RSVD30     NV_DCE_IRQ(62)
+#define NV_DCE_IRQ_V1RSVD31     NV_DCE_IRQ(63)
+
+#endif  /* FSP_SOC_T234_DCE_PROCESSOR_IRQS_HW_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/irqs-lic.h b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/irqs-lic.h
new file mode 100644
index 0000000..883cda1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/irqs-lic.h
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2019-2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__IRQS_LIC_H
+#define PROCESSOR__IRQS_LIC_H
+#define FSP__PROCESSOR__IRQS_LIC_H                      1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+#define NR_VIC_IRQS 64
+
+#define LIC_IRQ_BASE        NR_VIC_IRQS
+#define LIC0_IRQ_CONTEXT    lic0_irq_context
+#define LIC1_IRQ_CONTEXT    lic1_irq_context
+#define LIC2_IRQ_CONTEXT    lic2_irq_context
+#define LIC3_IRQ_CONTEXT    lic3_irq_context
+
+#ifndef __ASSEMBLER__
+
+#include <lic/lic-tegra-priv.h>
+
+extern struct tegra_lic_id tegra_lic_id_dce;
+extern lic_irq_context_t lic0_irq_context;
+extern lic_irq_context_t lic1_irq_context;
+extern lic_irq_context_t lic2_irq_context;
+extern lic_irq_context_t lic3_irq_context;
+
+#endif
+
+#endif /* PROCESSOR__IRQS_LIC_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/tegra-uart-hw-params.h b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/tegra-uart-hw-params.h
new file mode 100644
index 0000000..3d694fe
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/tegra-uart-hw-params.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__UART_TEGRA_HW_PARAMS_H
+#define PROCESSOR__UART_TEGRA_HW_PARAMS_H
+#define FSP__PROCESSOR__TEGRA_UART_HW_PARAMS_H          1
+
+#include <misc/ct-assert.h>
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <processor/irqs-hw.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+#ifndef TEGRA_UARTC_ENABLED
+#define TEGRA_UARTC_ENABLED
+#endif
+#define TEGRA_UARTC_IRQ         0
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/tke-tegra-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/tke-tegra-hw.h
new file mode 100644
index 0000000..91767b9
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/dce/processor/tke-tegra-hw.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__TKE_TEGRA_HW_H
+#define PROCESSOR__TKE_TEGRA_HW_H
+#define FSP__PROCESSOR__TKE_TEGRA_HW_H                  1
+
+extern struct tegra_tke_id tegra_tke_id_timer0;
+extern struct tegra_tke_id tegra_tke_id_timer1;
+extern struct tegra_tke_id tegra_tke_id_timer2;
+extern struct tegra_tke_id tegra_tke_id_timer3;
+
+#define TEGRA_TKE_TIMER_CLK_SRC_USECCNT         0
+#define TEGRA_TKE_TIMER_CLK_SRC_OSCCNT          1
+#define TEGRA_TKE_TIMER_CLK_SRC_TSC_BIT0        2
+#define TEGRA_TKE_TIMER_CLK_SRC_TSC_BIT12       3
+
+#endif  /* FSP_SOC_T234_DCE_PROCESSOR_TKE_TEGRA_HW_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-clk.h b/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-clk.h
new file mode 100644
index 0000000..8e388af
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-clk.h
@@ -0,0 +1,182 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef FSI__CAR_CLK_H
+#define FSI__CAR_CLK_H
+#define FSP__FSI__CAR_CLK_H             1
+
+/* Compiler headers */
+#include <stdint.h>                     // for uint8_t, uint64_t, uint32_t
+#include <stdbool.h>                    // for bool
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <error/common-errors.h>        // for error_t
+
+/* Module-specific FSP headers */
+#include <car/car-clk.h>                // for clock functions, ...
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_CLK_H, "Header file missing or invalid.")
+
+
+#define Hz                              (1LL)
+#define kHz                             (Hz * 1000)
+#define MHz                             (kHz * 1000)
+#define GHz                             (MHz * 1000)
+
+#define FSI_CLK_XTAL_HZ                 40000000ULL /* 40Mhz */
+#define FSI_CLK_VREFRO_HZ               50000000ULL /* 50Mhz */
+
+#define FSI_CLK_ID_XTAL                 0U
+#define FSI_CLK_ID_PLL                  1U
+#define FSI_CLK_ID_CHSM_CPU             2U
+#define FSI_CLK_ID_CSITE                3U
+#define FSI_CLK_ID_FABRIC_CLK           4U
+#define FSI_CLK_ID_FABRIC_PCLK          5U
+#define FSI_CLK_ID_JTAG                 6U
+#define FSI_CLK_ID_LA                   7U
+#define FSI_CLK_ID_MC                   8U
+#define FSI_CLK_ID_SE                   9U
+#define FSI_CLK_ID_SE_FR                10U
+#define FSI_CLK_ID_SPI0                 11U
+#define FSI_CLK_ID_SRAM_CLK             12U
+#define FSI_CLK_ID_SRAM_PCLK            13U
+#define FSI_CLK_ID_TS                   14U
+#define FSI_CLK_ID_UART0                15U
+#define FSI_CLK_ID_N                    16U
+
+extern const struct car_clk_inf fsi_clk_infs[FSI_CLK_ID_N];
+
+/**
+ * @brief Enable a clock.
+ *
+ * @param clk_id The FSI_CLK_ID_? define that is used to identify
+ *               a clock.
+ * @return E_SUCCESS
+ *         E_CAR_INVALID_CLOCK_ID
+ */
+error_t fsi_clk_enable(uint32_t clk_id);
+
+/**
+ * @brief Disable a clock.
+ *
+ * @param clk_id The FSI_CLK_ID_? define that is used to identify
+ *               a clock.
+ * @return E_SUCCESS
+ *         E_CAR_INVALID_CLOCK_ID
+ */
+error_t fsi_clk_disable(uint32_t clk_id);
+
+/**
+ * @brief Get the clock enable status.
+ *
+ * @param clk_id The FSI_CLK_ID_? define that is used to identify
+ *               a clock.
+ * @return True or false.
+ */
+bool fsi_clk_is_enabled(uint32_t clk_id);
+
+/**
+ * @brief Set the clock rate.
+ *
+ * @param clk_id The FSI_CLK_ID_? define that is used to identify
+ *               a clock.
+ * @param hz_out The requested clock rate in hertz.
+ * @return E_SUCCESS
+ *         E_CAR_INVALID_CLOCK_ID
+ */
+error_t fsi_clk_set_rate(uint32_t clk_id, int64_t hz_out);
+
+/**
+ * @brief Get the clock rate.
+ *
+ * @param clk_id The FSI_CLK_ID_? define that is used to identify
+ *               a clock.
+ * @param hz_out The pointer to put the clock rate in hertz.
+ * @return E_SUCCESS
+ *         E_CAR_INVALID_CLOCK_ID
+ */
+error_t fsi_clk_get_rate(uint32_t clk_id, int64_t *hz_out);
+
+
+// Bring-up specific functions:
+
+bool fsi_clk_fmon_is_enabled(void);
+void fsi_clk_fmon_enable(void);
+void fsi_clk_fmon_disable(void);
+
+/**
+ * @brief Set divider.
+ *
+ * @param clk_id The FSI_CLK_ID_? define that is used to identify
+ *               a clock.
+ * @param div The div value.
+ * @return E_SUCCESS
+ *         E_CAR_INVALID_CLOCK_ID
+ */
+error_t fsi_clk_set_div(uint32_t clk_id, uint32_t div);
+
+/**
+ * @brief  Get divider.
+ *
+ * @param clk_id The FSI_CLK_ID_? define that is used to identify
+ *               a clock.
+ * @param div The pointer to put the divider value.
+ * @return E_SUCCESS
+ *         E_CAR_INVALID_CLOCK_ID
+ */
+error_t fsi_clk_get_div(uint32_t clk_id, uint32_t *div);
+
+/**
+ * @brief Get CAR error_t string.
+ *
+ * @param err The error_t returned from a CAR function.
+ * @return The string describing the error_t code.
+ */
+const char *fsi_car_get_err_str(error_t err);
+
+#endif /* FSI__CAR_CLK_H */
+
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-fmon.h b/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-fmon.h
new file mode 100644
index 0000000..d94bf9e
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-fmon.h
@@ -0,0 +1,159 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef FSI__CAR_FMON_H
+#define FSI__CAR_FMON_H
+#define FSP__FSI__CAR_FMON_H            1
+
+/* Compiler headers */
+#include <stdint.h>                     // for uint8_t, uint64_t, uint32_t
+#include <stdbool.h>                    // for bool
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <error/common-errors.h>        // for error_t
+
+/* Module-specific FSP headers */
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+
+
+/* FMON IDs */
+#define FSI_FMON_ID_PLL             0U
+#define FSI_FMON_ID_CHSM            1U
+#define FSI_FMON_ID_FABRIC          2U
+#define FSI_FMON_ID_SPI             3U
+#define FSI_FMON_ID_TS              4U
+#define FSI_FMON_ID_XTAL            5U
+#define FSI_FMON_ID_N               6U
+
+extern const struct car_fmon_inf fsi_fmon_infs[FSI_FMON_ID_N];
+
+/* Counter offsets to clk_count member of fmon_clk_count structure */
+#define FSI_FMON_CLK_COUNT_MIN      (CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PLL_FSI_0_PLL_FSI_FMON_LOAD_DATA_SEL_MIN)
+#define FSI_FMON_CLK_COUNT_MAX      (CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PLL_FSI_0_PLL_FSI_FMON_LOAD_DATA_SEL_MAX)
+#define FSI_FMON_CLK_COUNT_LATEST   (CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PLL_FSI_0_PLL_FSI_FMON_LOAD_DATA_SEL_COUNT_0_Latest_Count)
+#define FSI_FMON_CLK_COUNT_1        (CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PLL_FSI_0_PLL_FSI_FMON_LOAD_DATA_SEL_COUNT_1)
+#define FSI_FMON_CLK_COUNT_2        (CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PLL_FSI_0_PLL_FSI_FMON_LOAD_DATA_SEL_COUNT_2)
+#define FSI_FMON_CLK_COUNT_3        (CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PLL_FSI_0_PLL_FSI_FMON_LOAD_DATA_SEL_COUNT_3)
+#define FSI_FMON_CLK_COUNT_EARLIEST (CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PLL_FSI_0_PLL_FSI_FMON_LOAD_DATA_SEL_COUNT_4_Earliest_Count)
+
+struct fsi_fmon_cnts {
+    uint32_t ref_win;
+    uint32_t ref_win_dc_chk;
+    uint32_t cnt_min;
+    uint32_t cnt_max;
+    uint32_t cnt_0_latest;
+    uint32_t cnt_1;
+    uint32_t cnt_2;
+    uint32_t cnt_3;
+    uint32_t cnt_4_earliest;
+};
+
+
+/**
+ * @brief Calculate clock frequency from frequency monitor
+ *        counters.
+ *
+ * @param clk_id The FSI_CLK_ID_? define that is used to identify
+ *               a clock.
+ * @param hz The pointer to put the frequency hertz.
+ * @return E_SUCCESS
+ *         E_CAR_FMON_NO_DATA
+ *         E_CAR_FMON_HW_LOGIC
+ *         E_CAR_FMON_HW_TIMEOUT
+ */
+error_t fsi_fmon_clk_hz_calc(uint32_t clk_id, uint64_t *hz);
+
+/**
+ * @brief Frequency Monitor (FMON) enabled?.
+ *
+ * @param clk_id The FSI_CLK_ID_? define that is used to identify
+ *               a clock.
+ * @retval  true/false
+ */
+bool fsi_fmon_is_enabled(uint32_t clk_id);
+
+/**
+ * @brief Frequency Monitor (FMON) startup.
+ *
+ * DEPRECATED! This is handled automatically by the FSP CAR
+ *             driver.
+ *
+ * @param clk_id The FSI_CLK_ID_? define that is used to identify
+ *               a clock.
+ * @return E_SUCCESS
+ *         E_CAR_FMON_HW_LOGIC
+ *         E_CAR_FMON_HW_TIMEOUT
+ */
+error_t fsi_fmon_startup(uint32_t clk_id);
+
+/**
+ * @brief Frequency Monitor (FMON) shutdown.
+ *
+ * DEPRECATED! This is handled automatically by the FSP CAR
+ *             driver.
+ *
+ * @param clk_id The FSI_CLK_ID_? define that is used to identify
+ *               a clock.
+ * @return E_SUCCESS
+ *         E_CAR_FMON_HW_LOGIC
+ *         E_CAR_FMON_HW_TIMEOUT
+ */
+error_t fsi_fmon_shutdown(uint32_t clk_id);
+
+/**
+ * @brief  Initialize frequency monitors
+ *
+ * DEPRECATED!
+ *
+ * @return E_SUCCESS
+ *         E_CAR_FMON_HW_LOGIC
+ *         E_CAR_FMON_HW_TIMEOUT
+ */
+error_t fsi_fmon_init(void);
+
+#endif /* FSI__CAR_FMON_H */
+
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-fsi.h b/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-fsi.h
new file mode 100644
index 0000000..a0979d6
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-fsi.h
@@ -0,0 +1,65 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef FSI__CAR_H
+#define FSI__CAR_H
+#define FSP__FSI__CAR_H             1
+
+/* Compiler headers */
+#include <stdint.h>                     // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>        // for error_t, FSP__ERROR__COMMON...
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+
+/*
+ * Declaration for tegra_car_id that allows the APIs to take a pointer to it
+ * without actually defining its contents here.
+ */
+struct tegra_car_id;
+
+#endif
+
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-pll.h b/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-pll.h
new file mode 100644
index 0000000..832f809
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-pll.h
@@ -0,0 +1,239 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef FSI__CAR_PLL_H
+#define FSI__CAR_PLL_H
+#define FSP__FSI__CAR_PLL_H             1
+
+/* Compiler headers */
+#include <stdint.h>                     // for uint8_t, uint64_t, uint32_t
+#include <stdbool.h>                    // for bool
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <error/common-errors.h>        // for error_t
+
+/* Module-specific FSP headers */
+#include <car/car-pll.h>                // for car_pll_spec, ...
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_PLL_H, "Header file missing or invalid.")
+
+/**
+ * @brief FSI CAR PLL voltage/frequency configuration:
+ *  Use the defines to select the frequency for the specific
+ *  voltage when calling fsi_pll_init.
+ */
+#define FSI_CAR_PLL_550mV_633MHz        0U
+#define FSI_CAR_PLL_600mV_897MHz        1U
+#define FSI_CAR_PLL_670mV_1300MHz       2U
+#define FSI_CAR_PLL_720mV_1300MHz       3U
+#define FSI_CAR_PLL_850mV_1610MHz       4U
+#define FSI_CAR_PLL_940mV_1610MHz       5U
+
+#define FSI_CAR_PLL_550mV_550MHz        6U
+#define FSI_CAR_PLL_600mV_780MHz        7U
+#define FSI_CAR_PLL_670mV_1130MHz       8U
+#define FSI_CAR_PLL_720mV_1130MHz       9U
+#define FSI_CAR_PLL_850mV_1400MHz       10U
+#define FSI_CAR_PLL_940mV_1400MHz       11U
+
+#define FSI_CAR_PLL_0mV_0MHz_NO_INIT    12U
+
+
+/**
+ * @brief PLL register configuration values typically used to
+ *        write directly to PLL registers. This can be used
+ *        during PLL initialization or fault recovery.
+ */
+struct fsi_pll_init_cfg {
+    int64_t hz;
+    uint8_t divm;
+    uint8_t divp;
+    uint8_t divn;
+    uint16_t divn_frac;
+    uint16_t frac_step;
+    uint32_t reg_misc_2;
+    uint32_t reg_misc_3;
+    uint32_t reg_misc_4;
+    uint32_t reg_misc_5;
+    uint32_t reg_misc_6;
+};
+
+/**
+ * @brief Read FSI PLL enable status.
+ *
+ * @return True or false.
+ */
+bool fsi_pll_is_enabled(void);
+
+/**
+ * @brief Enable FSI PLL.
+ *
+ * DEPRECATED! Use fsi_clk_enable with FSI_CLK_ID_PLL instead.
+ *
+ * @return E_SUCCESS
+ *         E_CAR_PLL_NO_LOCK
+ */
+error_t fsi_pll_enable(void);
+
+/**
+ * @brief Disable FSI PLL.
+ *
+ * DEPRECATED! Use fsi_clk_disable with FSI_CLK_ID_PLL instead.
+ *
+ * @return E_SUCCESS
+ */
+error_t fsi_pll_disable(void);
+
+/**
+ * @brief Set FSI PLL frequency.
+ *
+ * DEPRECATED! Use fsi_clk_set_rate with FSI_CLK_ID_PLL instead.
+ *
+ * @param hz_out Frequency in hertz.
+ * @return E_SUCCESS
+ *         E_CAR_INVALID_PARAM
+ */
+error_t fsi_pll_set_rate(int64_t hz_out);
+
+/**
+ * @brief Get FSI PLL frequency.
+ *
+ * DEPRECATED! Use fsi_clk_get_rate with FSI_CLK_ID_PLL instead.
+ *
+ * @param hz_out The pointer to where the frequency will be
+ *               written.
+ * @return E_SUCCESS
+ */
+error_t fsi_pll_get_rate(int64_t *hz_out);
+
+/**
+ * @brief Used to read the current car_pll_spec structure
+ *        of values.
+ *
+ * DEPRECATED! This is a debug/test feature.
+ *
+ * @param spec Pointer to the car_pll_spec structure that will
+ *             be populated with the current values.
+ * @return E_SUCCESS
+ *         E_CAR_NULL_PTR
+ */
+error_t fsi_pll_spec_get(struct car_pll_spec *spec);
+
+/**
+ * @brief Used to provide an alternate car_pll_spec structure of
+ *        values.
+ *
+ * DEPRECATED! This is a debug/test feature.
+ *
+ * @param spec Pointer to the car_pll_spec structure. If this
+ *             pointer is NULL then the default car_pll_spec
+ *             structure will be used. This is the mechanism to
+ *             reset to default values.
+ * @return E_SUCCESS
+ */
+error_t fsi_pll_spec_set(struct car_pll_spec *spec);
+
+/**
+ * @brief Used to provide a table of alternate car_pll_cfg
+ *        structure values.
+ *
+ * DEPRECATED! This is a debug/test feature.
+ *
+ * @param cfgs Pointer to the car_pll_cfg structure table. If
+ *             this pointer is NULL then the default car_pll_cfg
+ *             structure table will be used. This is the
+ *             mechanism to reset to the default table.
+ * @param cfgs_n The number of entries in the table. If this
+ *               value is 0 the car_pll_cfg feature is disabled.
+ * @return E_SUCCESS
+ */
+error_t fsi_pll_cfgs_set(struct car_pll_cfg *cfgs, uint32_t cfgs_n);
+
+/**
+ * @brief Read the PLL registers to populate the
+ *        fsi_pll_init_cfg structure. Typically used for a
+ *        read-modify-write to the PLL.
+ *
+ * DEPRECATED! This is a debug/test feature.
+ *
+ * @param cfg Pointer to the fsi_pll_init_cfg structure.
+ * @return E_SUCCESS
+ *         E_CAR_NULL_PTR
+ *         E_CAR_PLL_NO_INIT
+ *         E_CAR_PLL_NO_LOCK
+ */
+error_t fsi_pll_init_cfg_rd(struct fsi_pll_init_cfg *cfg);
+
+/**
+ * @brief Write the fsi_pll_init_cfg values directly to the PLL
+ *        registers. This can be used during PLL initialization
+ *        or fault recovery.
+ *
+ * DEPRECATED! This is a debug/test feature.
+ *
+ * @param cfg Pointer to the fsi_pll_init_cfg structure.
+ * @return E_SUCCESS
+ *         E_CAR_NULL_PTR
+ *         E_CAR_PLL_NO_INIT
+ *         E_CAR_PLL_NO_LOCK
+ */
+error_t fsi_pll_init_cfg_wr(struct fsi_pll_init_cfg *cfg);
+
+/**
+ * @brief Initialize FSI PLL.
+ *
+ * DEPRECATED! Just start using fsi_clk_ functions with
+ *             FSI_CLK_ID_PLL instead.
+ *
+ * @param pll_vf The PLL Voltage/Frequency selector.
+ * @return E_SUCCESS
+ *         E_CAR_INVALID_PARAM
+ */
+error_t fsi_pll_init(uint32_t pll_vf);
+
+#endif /* FSI__CAR_PLL_H */
+
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-port.h b/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-port.h
new file mode 100644
index 0000000..4123c41
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-port.h
@@ -0,0 +1,68 @@
+/* Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef FSI__CAR_PORT_H
+#define FSI__CAR_PORT_H
+#define FSP__PORT__CAR_PORT_H           1
+
+/**
+ * @file car/car-port.h
+ * @brief Structures that are internal to the CAR driver
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+
+void car_port_udelay(uint64_t delay_us);
+uint64_t car_port_get_time_ticks(void);
+uint64_t car_port_get_time_delta_us(uint64_t ticks_start);
+
+#endif /* FSI__CAR_PORT_H */
+
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-rst.h b/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-rst.h
new file mode 100644
index 0000000..7452858
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/car-rst.h
@@ -0,0 +1,133 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef FSI__CAR_RST_H
+#define FSI__CAR_RST_H
+#define FSP__FSI__CAR_RST_H             1
+
+/* Compiler headers */
+#include <stdint.h>                     // for uint8_t, uint64_t, uint32_t
+#include <stdbool.h>                    // for bool
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD...
+#include <error/common-errors.h>        // for error_t
+
+/* Module-specific FSP headers */
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+
+
+/**
+ * @brief FSI CAR reset IDs:
+ *  Use the reset ID to represent the reset device.
+ */
+#define FSI_CAR_RST_ID_CAN0             1U
+#define FSI_CAR_RST_ID_CAN1             2U
+#define FSI_CAR_RST_ID_CHSM_DBGRESETN   3U
+#define FSI_CAR_RST_ID_CHSM_NRESET      4U
+#define FSI_CAR_RST_ID_CHSM_PRESETDBGN  5U
+#define FSI_CAR_RST_ID_CHSM_SYSPORRESET 6U
+#define FSI_CAR_RST_ID_CSITE            7U
+#define FSI_CAR_RST_ID_LA               8U
+#define FSI_CAR_RST_ID_NCORE_0          9U
+#define FSI_CAR_RST_ID_NCORE_1          10U
+#define FSI_CAR_RST_ID_NCORE_2          11U
+#define FSI_CAR_RST_ID_NCORE_3          12U
+#define FSI_CAR_RST_ID_NCPUPOR_0        13U
+#define FSI_CAR_RST_ID_NCPUPOR_1        14U
+#define FSI_CAR_RST_ID_NCPUPOR_2        15U
+#define FSI_CAR_RST_ID_NCPUPOR_3        16U
+#define FSI_CAR_RST_ID_NTOPRESET        17U
+#define FSI_CAR_RST_ID_NPRESETDBG       18U
+#define FSI_CAR_RST_ID_SPI0             19U
+#define FSI_CAR_RST_ID_UART0            20U
+#define FSI_CAR_RST_ID_N                21U
+
+
+/**
+ * @brief Get the reset assert status.
+ *
+ * @param rst_id The FSI_CAR_RST_ID_? define that is used to identify
+ *               a reset signal.
+ * @return True or false
+ */
+bool fsi_rst_is_asserted(uint32_t rst_id);
+
+/**
+ * @brief Assert a reset.
+ *
+ * @param rst_id The FSI_CAR_RST_ID_? define that is used to identify
+ *               a reset signal.
+ * @return E_SUCCESS
+ *         E_CAR_INVALID_RESET_ID
+ */
+error_t fsi_rst_assert(uint32_t rst_id);
+
+/**
+ * @brief Deassert a reset.
+ *
+ * @param rst_id The FSI_CAR_RST_ID_? define that is used to identify
+ *               a reset signal.
+ * @return E_SUCCESS
+ *         E_CAR_INVALID_RESET_ID
+ */
+error_t fsi_rst_deassert(uint32_t rst_id);
+
+/**
+ * @brief Pulse a reset with an assert, delay for the specified
+ *        microseconds, and deassert.
+ *
+ * @param rst_id The FSI_CAR_RST_ID_? define that is used to identify
+ *               a reset signal.
+ * @param delay_us The delay in microseconds for the asserted
+ *                 reset signal.
+ * @return E_SUCCESS
+ *         E_CAR_INVALID_RESET_ID
+ */
+error_t fsi_rst_pulse(uint32_t rst_id, uint64_t delay_us);
+
+#endif /* FSI__CAR_RST_H */
+
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/gpcdma-port-priv.h b/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/gpcdma-port-priv.h
new file mode 100644
index 0000000..ccddf09
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/port/gpcdma-port-priv.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GPCDMA__GPCDMA_PORT_PRIV_H
+#define GPCDMA__GPCDMA_PORT_PRIV_H
+#define FSP__PORT__GPCDMA_PORT_PRIV_H                      0
+
+/**
+ * @file gpcdma/gpcdma-port-priv-.h
+ * @brief provides context that is specific to the port layer.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* HW headers */
+
+/* Late FSP headers */
+
+struct gpcdma_hw_handle {
+    const struct tegra_rst *rst;
+};
+
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/processor/irqs-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/processor/irqs-hw.h
new file mode 100644
index 0000000..243187d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/fsi/processor/irqs-hw.h
@@ -0,0 +1,61 @@
+/*
+* Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+*
+* NVIDIA CORPORATION and its licensors retain all intellectual property
+* and proprietary rights in and to this software, related documentation
+* and any modifications thereto.  Any use, reproduction, disclosure or
+* distribution of this software and related documentation without an express
+* license agreement from NVIDIA CORPORATION is strictly prohibited.
+*/
+
+#ifndef PROCESSOR__IRQS_HW_H
+#define PROCESSOR__IRQS_HW_H
+#define FSP__PROCESSOR__IRQS_HW_H                       1
+
+#define MAX_VIC_CONTROLLER       2
+#define NV_FSI_SPI_INTR_BASE    32
+#define NV_FSI_PPI_INTR_BASE    16
+
+/* SPI interupts source numbers starts */
+/* SPI irq must be added by 32 (NV_FSI_SPI_INTR_BASE) while using */
+#define NV_FSI_GIC_TIMER_INTR0 4
+#define NV_FSI_GIC_TIMER_INTR1 34
+#define NV_FSI_GIC_TIMER_INTR2 66
+#define NV_FSI_GIC_TIMER_INTR3 96
+#define NV_FSI_GIC_TOP_HSP2_SI0 21
+#define NV_FSI_GIC_TOP_HSP2_SI1 22
+
+#define NV_FSI_GIC_TOP_HSP2_SI2 44
+#define NV_FSI_GIC_TOP_HSP2_SI4 46
+#define NV_FSI_GIC_HSP_SI0 3
+#define NV_FSI_GIC_HSP_SI2 64
+#define NV_FSI_GIC_HSP_SI4 28
+#define NV_FSI_GIC_SCE_HSP1_SI2 15
+#define NV_FSI_GIC_SCE_HSP1_SI3 16
+#define NV_FSI_GIC_SCE_HSP1_SI4 36
+#define NV_FSI_GIC_SCE_HSP2_SI2 42
+#define NV_FSI_GIC_SCE_HSP2_SI4 17
+
+/* FSI GPCDMA interrupt numbers */
+#define NV_FSI_GIC_DMA_INTR0 26
+#define NV_FSI_GIC_DMA_INTR1 27
+#define NV_FSI_GIC_DMA_INTR2 52
+#define NV_FSI_GIC_DMA_INTR3 53
+#define NV_FSI_GIC_DMA_INTR4 67
+#define NV_FSI_GIC_DMA_INTR5 68
+#define NV_FSI_GIC_DMA_INTR6 97
+#define NV_FSI_GIC_DMA_INTR7 98
+#define NV_FSI_GIC_DMA_INTR8 99
+
+/* PPI interupt source numbers */
+/* PPI irq numbers must be added by 16 (PPI_BASE) while using*/
+#define NV_FSI_GIC_WDT_nIRQ0    0
+#define NV_FSI_GIC_WDT_nFIQ0    1
+#define NV_FSI_GIC_WDT_nIRQ1    0
+#define NV_FSI_GIC_WDT_nFIQ1    1
+#define NV_FSI_GIC_WDT_nIRQ2    0
+#define NV_FSI_GIC_WDT_nFIQ2    1
+#define NV_FSI_GIC_WDT_nIRQ3    0
+#define NV_FSI_GIC_WDT_nFIQ3    1
+
+#endif /* PROCESSOR__IRQS_HW_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/rce/hw-config/vic-irqs.h b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/hw-config/vic-irqs.h
new file mode 100644
index 0000000..39f8375
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/hw-config/vic-irqs.h
@@ -0,0 +1,105 @@
+/*
+ * t234/rce/hw-config/vic-irqs.h - Interrupts for safertos-common handlers
+ *
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef HW_CONFIG__VIC_IRQS_H
+#define HW_CONFIG__VIC_IRQS_H
+#define FSP__HW_CONFIG__VIC_IRQS_H                      1
+
+#include <misc/ct-assert.h>
+#include <processor/irqs-hw.h>
+#include <vic/tegra-vic.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__VIC__TEGRA_VIC_H, "Header file missing or invalid.")
+
+/*
+ * Define the various vectors where the VIC and IRQ are encoded into one value
+ */
+#define INTERRUPT_WDTFIQ            TEGRA_INTERRUPT(0, NV_RCE_IRQ_WDTFIQ)
+#define INTERRUPT_WDTIRQ            TEGRA_INTERRUPT(0, NV_RCE_IRQ_WDTIRQ)
+#define INTERRUPT_TIMER0            TEGRA_INTERRUPT(0, NV_RCE_IRQ_TIMER0)
+#define INTERRUPT_TIMER1            TEGRA_INTERRUPT(0, NV_RCE_IRQ_TIMER1)
+#define INTERRUPT_TIMER2            TEGRA_INTERRUPT(0, NV_RCE_IRQ_TIMER2)
+#define INTERRUPT_TIMER3            TEGRA_INTERRUPT(0, NV_RCE_IRQ_TIMER3)
+#define INTERRUPT_MBOX              TEGRA_INTERRUPT(0, NV_RCE_IRQ_MBOX)
+#define INTERRUPT_GTE               TEGRA_INTERRUPT(0, NV_RCE_IRQ_GTE)
+#define INTERRUPT_PMU               TEGRA_INTERRUPT(0, NV_RCE_IRQ_PMU)
+#define INTERRUPT_DMA0              TEGRA_INTERRUPT(0, NV_RCE_IRQ_DMA0)
+#define INTERRUPT_DMA1              TEGRA_INTERRUPT(0, NV_RCE_IRQ_DMA1)
+#define INTERRUPT_DMA2              TEGRA_INTERRUPT(0, NV_RCE_IRQ_DMA2)
+#define INTERRUPT_DMA3              TEGRA_INTERRUPT(0, NV_RCE_IRQ_DMA3)
+#define INTERRUPT_DMA4              TEGRA_INTERRUPT(0, NV_RCE_IRQ_DMA4)
+#define INTERRUPT_DMA5              TEGRA_INTERRUPT(0, NV_RCE_IRQ_DMA5)
+#define INTERRUPT_DMA6              TEGRA_INTERRUPT(0, NV_RCE_IRQ_DMA6)
+#define INTERRUPT_DMA7              TEGRA_INTERRUPT(0, NV_RCE_IRQ_DMA7)
+#define INTERRUPT_LIC0              TEGRA_INTERRUPT(0, NV_RCE_IRQ_LIC0)
+#define INTERRUPT_LIC1              TEGRA_INTERRUPT(0, NV_RCE_IRQ_LIC1)
+#define INTERRUPT_LIC2              TEGRA_INTERRUPT(0, NV_RCE_IRQ_LIC2)
+#define INTERRUPT_LIC3              TEGRA_INTERRUPT(0, NV_RCE_IRQ_LIC3)
+#define INTERRUPT_V0RSVD21          TEGRA_INTERRUPT(0, NV_RCE_IRQ_V0RSVD21)
+#define INTERRUPT_HSM_CRITICAL_ERR  TEGRA_INTERRUPT(0, NV_RCE_IRQ_HSM_CRITICAL_ERR)
+#define INTERRUPT_VI_HP             TEGRA_INTERRUPT(0, NV_RCE_IRQ_VI_HP)
+#define INTERRUPT_VI2_HP            TEGRA_INTERRUPT(0, NV_RCE_IRQ_VI2_HP)
+#define INTERRUPT_HSM_HP            TEGRA_INTERRUPT(0, NV_RCE_IRQ_HSM_HP)
+#define INTERRUPT_HSM_LP            TEGRA_INTERRUPT(0, NV_RCE_IRQ_HSM_LP)
+#define INTERRUPT_VI_LP             TEGRA_INTERRUPT(0, NV_RCE_IRQ_VI_LP)
+#define INTERRUPT_V0RSVD28          TEGRA_INTERRUPT(0, NV_RCE_IRQ_V0RSVD28)
+#define INTERRUPT_V0RSVD29          TEGRA_INTERRUPT(0, NV_RCE_IRQ_V0RSVD29)
+#define INTERRUPT_V0RSVD30          TEGRA_INTERRUPT(0, NV_RCE_IRQ_V0RSVD30)
+#define INTERRUPT_V0RSVD31          TEGRA_INTERRUPT(0, NV_RCE_IRQ_V0RSVD31)
+
+// VIC1 interrupts
+#define INTERRUPT_V1RSVD0           TEGRA_INTERRUPT(1, NV_RCE_IRQ_V1RSVD0)
+#define INTERRUPT_ACTMON            TEGRA_INTERRUPT(1, NV_RCE_IRQ_ACTMON)
+#define INTERRUPT_FPUINT            TEGRA_INTERRUPT(1, NV_RCE_IRQ_FPUINT)
+#define INTERRUPT_PM                TEGRA_INTERRUPT(1, NV_RCE_IRQ_PM)
+#define INTERRUPT_MC_SBE            TEGRA_INTERRUPT(1, NV_RCE_IRQ_MC_SBE)
+#define INTERRUPT_NOC_SECURE        TEGRA_INTERRUPT(1, NV_RCE_IRQ_NOC_SECURE)
+#define INTERRUPT_HSP1_SI_0         TEGRA_INTERRUPT(1, NV_RCE_IRQ_HSP1_SI_0)
+#define INTERRUPT_HSP1_SI_1         TEGRA_INTERRUPT(1, NV_RCE_IRQ_HSP1_SI_1)
+#define INTERRUPT_HSP1_SI_2         TEGRA_INTERRUPT(1, NV_RCE_IRQ_HSP1_SI_2)
+#define INTERRUPT_HSP1_SI_3         TEGRA_INTERRUPT(1, NV_RCE_IRQ_HSP1_SI_3)
+#define INTERRUPT_HSP1_SI_4         TEGRA_INTERRUPT(1, NV_RCE_IRQ_HSP1_SI_4)
+#define INTERRUPT_HSP1_SI_5         TEGRA_INTERRUPT(1, NV_RCE_IRQ_HSP1_SI_5)
+#define INTERRUPT_HSP1_SI_6         TEGRA_INTERRUPT(1, NV_RCE_IRQ_HSP1_SI_6)
+#define INTERRUPT_HSP1_SI_7         TEGRA_INTERRUPT(1, NV_RCE_IRQ_HSP1_SI_7)
+#define INTERRUPT_TOP0_HSP_DB       TEGRA_INTERRUPT(1, NV_RCE_IRQ_TOP0_HSP_DB)
+#define INTERRUPT_CAR               TEGRA_INTERRUPT(1, NV_RCE_IRQ_CAR)
+#define INTERRUPT_V1RSVD16          TEGRA_INTERRUPT(1, NV_RCE_IRQ_V1RSVD16)
+#define INTERRUPT_CTIIRQ            TEGRA_INTERRUPT(1, NV_RCE_IRQ_CTIIRQ)
+#define INTERRUPT_V1RSVD18          TEGRA_INTERRUPT(1, NV_RCE_IRQ_V1RSVD18)
+#define INTERRUPT_I2C1              TEGRA_INTERRUPT(1, NV_RCE_IRQ_I2C1)
+#define INTERRUPT_I2C3              TEGRA_INTERRUPT(1, NV_RCE_IRQ_I2C3)
+#define INTERRUPT_I2C8              TEGRA_INTERRUPT(1, NV_RCE_IRQ_I2C8)
+#define INTERRUPT_DISP              TEGRA_INTERRUPT(1, NV_RCE_IRQ_DISP)
+#define INTERRUPT_V1RSVD23          TEGRA_INTERRUPT(1, NV_RCE_IRQ_V1RSVD23)
+#define INTERRUPT_HSP2_SI_0         TEGRA_INTERRUPT(1, NV_RCE_IRQ_HSP2_SI_0)
+#define INTERRUPT_HSP2_SI_1         TEGRA_INTERRUPT(1, NV_RCE_IRQ_HSP2_SI_1)
+#define INTERRUPT_HSP2_SI_2         TEGRA_INTERRUPT(1, NV_RCE_IRQ_HSP2_SI_2)
+#define INTERRUPT_HSP2_SI_3         TEGRA_INTERRUPT(1, NV_RCE_IRQ_HSP2_SI_3)
+#define INTERRUPT_HSP2_SI_4         TEGRA_INTERRUPT(1, NV_RCE_IRQ_HSP2_SI_4)
+#define INTERRUPT_HSP2_SI_5         TEGRA_INTERRUPT(1, NV_RCE_IRQ_HSP2_SI_5)
+#define INTERRUPT_HSP2_SI_6         TEGRA_INTERRUPT(1, NV_RCE_IRQ_HSP2_SI_6)
+#define INTERRUPT_HSP2_SI_7         TEGRA_INTERRUPT(1, NV_RCE_IRQ_HSP2_SI_7)
+
+#endif  /* HW_CONFIG__VIC_IRQS_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/rce/port/gpcdma-port-priv.h b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/port/gpcdma-port-priv.h
new file mode 100644
index 0000000..4263bc2
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/port/gpcdma-port-priv.h
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GPCDMA__GPCDMA_PORT_PRIV_H
+#define GPCDMA__GPCDMA_PORT_PRIV_H
+#define FSP__PORT__GPCDMA_PORT_PRIV_H                      0
+
+/**
+ * @file gpcdma/gpcdma-port-priv-.h
+ * @brief provides context that is specific to the port layer.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* HW headers */
+
+/* Late FSP headers */
+
+struct gpcdma_hw_handle {
+    const struct tegra_rst *rst;
+};
+
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/rce/port/uart-port-priv.h b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/port/uart-port-priv.h
new file mode 100644
index 0000000..fac77ec
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/port/uart-port-priv.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef UART__UART_PORT_PRIV_H
+#define UART__UART_PORT_PRIV_H
+#define FSP__PORT__UART_PORT_PRIV_H                      0
+
+#include <osa/rtos-queue.h>
+
+/**
+ * @file uart/uart-port-priv-.h
+ * @brief provides context that is specific to the port layer.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* HW headers */
+
+/* Late FSP headers */
+
+typedef rtosQueueHandle uart_queue_t;
+
+struct uart_hw_handle {
+    const struct tegra_clk *clk;
+    const struct tegra_rst *rst;
+};
+
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/cache-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/cache-hw.h
new file mode 100644
index 0000000..b59402c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/cache-hw.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__CACHE_HW_H
+#define PROCESSOR__CACHE_HW_H
+#define FSP__PROCESSOR__CACHE_HW_H                      1
+
+#define CACHE_LINE_SIZE	32
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/debug-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/debug-hw.h
new file mode 100644
index 0000000..520c225
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/debug-hw.h
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__DEBUG_HW_H
+#define PROCESSOR__DEBUG_HW_H
+#define FSP__PROCESSOR__DEBUG_HW_H                      1
+
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>
+
+/* Late FSP headers */
+#include <processor/tegra-uart-hw-params.h>
+#include <uart/tegra-uart-priv.h>
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+#ifdef TEGRA_UARTF_ENABLED
+extern struct tegra_uart_ctlr tegra_uart_ctlr_uartf;
+
+#ifndef DEBUG_UART
+#define DEBUG_UART      tegra_uart_ctlr_uartf
+#endif
+
+#endif
+
+#ifdef TEGRA_UARTC_ENABLED
+extern struct tegra_uart_ctlr tegra_uart_ctlr_uartc;
+
+#ifndef DEBUG_UART
+#define DEBUG_UART      tegra_uart_ctlr_uartc
+#endif
+
+#endif
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/gpcdma-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/gpcdma-hw.h
new file mode 100644
index 0000000..abca098
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/gpcdma-hw.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef GPCDMA_HW_H
+#define GPCDMA_HW_H
+#define FSP__PROCESSOR__GPCDMA_HW_H                  1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/macros.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+
+#define GPCDMA_CHAN0    gpcdma_chan0
+#define GPCDMA_CHAN1    gpcdma_chan1
+#define GPCDMA_CHAN2    gpcdma_chan2
+#define GPCDMA_CHAN3    gpcdma_chan3
+#define GPCDMA_CHAN4    gpcdma_chan4
+#define GPCDMA_CHAN5    gpcdma_chan5
+#define GPCDMA_CHAN6    gpcdma_chan6
+#define GPCDMA_CHAN7    gpcdma_chan7
+
+#ifndef __ASSEMBLER__
+
+extern struct gpcdma_id gpcdma_id_rce;
+extern struct gpcdma_channel gpcdma_chan0;
+extern struct gpcdma_channel gpcdma_chan1;
+extern struct gpcdma_channel gpcdma_chan2;
+extern struct gpcdma_channel gpcdma_chan3;
+extern struct gpcdma_channel gpcdma_chan4;
+extern struct gpcdma_channel gpcdma_chan5;
+extern struct gpcdma_channel gpcdma_chan6;
+extern struct gpcdma_channel gpcdma_chan7;
+
+#endif
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/hsp-tegra-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/hsp-tegra-hw.h
new file mode 100644
index 0000000..d4b99cd
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/hsp-tegra-hw.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PROCESSOR__HSP_TEGRA_HW_H
+#define PROCESSOR__HSP_TEGRA_HW_H
+#define FSP__PROCESSOR__HSP_TEGRA_HW_H                  1
+
+#include <misc/ct-assert.h>
+#include <soc-common/hsp-tegra-top-hw.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HSP_TEGRA_TOP_HW_H, "Header file missing or invalid.")
+
+#define TEGRA_HSP_ID_MBOX tegra_hsp_id_rce
+#define TEGRA_HSP_ID_DB   tegra_hsp_id_top0
+
+#ifndef __ASSEMBLER__
+
+/* This is the TOP HSP instance w/ AON interrupts */
+extern struct tegra_hsp_id tegra_hsp_id_top0;
+extern struct tegra_hsp_id tegra_hsp_id_self;
+extern struct tegra_hsp_id tegra_hsp_id_rce;
+
+#endif
+
+#endif /* PROCESSOR__HSP_TEGRA_HW_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/irqs-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/irqs-hw.h
new file mode 100644
index 0000000..aa85872
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/irqs-hw.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (c) 2016-2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__IRQS_HW_H
+#define PROCESSOR__IRQS_HW_H
+#define FSP__PROCESSOR__IRQS_HW_H                       1
+
+#define MAX_VIC_CONTROLLER       2
+
+#ifndef NV_RCE_IRQ
+#define NV_RCE_IRQ(x) (x ## U)
+#endif
+
+/* VIC0 interrupts */
+#define NV_RCE_IRQ_WDTFIQ		NV_RCE_IRQ(0)
+#define NV_RCE_IRQ_WDTIRQ		NV_RCE_IRQ(1)
+#define NV_RCE_IRQ_TIMER0		NV_RCE_IRQ(2)
+#define NV_RCE_IRQ_TIMER1		NV_RCE_IRQ(3)
+#define NV_RCE_IRQ_TIMER2		NV_RCE_IRQ(4)
+#define NV_RCE_IRQ_TIMER3		NV_RCE_IRQ(5)
+#define NV_RCE_IRQ_MBOX		        NV_RCE_IRQ(6)
+#define NV_RCE_IRQ_GTE		        NV_RCE_IRQ(7)
+#define NV_RCE_IRQ_PMU		        NV_RCE_IRQ(8)
+#define NV_RCE_IRQ_DMA0		        NV_RCE_IRQ(9)
+#define NV_RCE_IRQ_DMA1		        NV_RCE_IRQ(10)
+#define NV_RCE_IRQ_DMA2		        NV_RCE_IRQ(11)
+#define NV_RCE_IRQ_DMA3		        NV_RCE_IRQ(12)
+#define NV_RCE_IRQ_DMA4		        NV_RCE_IRQ(13)
+#define NV_RCE_IRQ_DMA5		        NV_RCE_IRQ(14)
+#define NV_RCE_IRQ_DMA6		        NV_RCE_IRQ(15)
+#define NV_RCE_IRQ_DMA7		        NV_RCE_IRQ(16)
+#define NV_RCE_IRQ_LIC0		        NV_RCE_IRQ(17)
+#define NV_RCE_IRQ_LIC1		        NV_RCE_IRQ(18)
+#define NV_RCE_IRQ_LIC2		        NV_RCE_IRQ(19)
+#define NV_RCE_IRQ_LIC3		        NV_RCE_IRQ(20)
+#define NV_RCE_IRQ_V0RSVD21		NV_RCE_IRQ(21)
+#define NV_RCE_IRQ_HSM_CRITICAL_ERR	NV_RCE_IRQ(22)
+#define NV_RCE_IRQ_VI_HP		NV_RCE_IRQ(23)
+#define NV_RCE_IRQ_VI2_HP		NV_RCE_IRQ(24)
+#define NV_RCE_IRQ_HSM_HP		NV_RCE_IRQ(25)
+#define NV_RCE_IRQ_HSM_LP		NV_RCE_IRQ(26)
+#define NV_RCE_IRQ_VI_LP		NV_RCE_IRQ(27)
+#define NV_RCE_IRQ_V0RSVD28		NV_RCE_IRQ(28)
+#define NV_RCE_IRQ_V0RSVD29		NV_RCE_IRQ(29)
+#define NV_RCE_IRQ_V0RSVD30		NV_RCE_IRQ(30)
+#define NV_RCE_IRQ_V0RSVD31		NV_RCE_IRQ(31)
+
+/* VIC1 interrupts */
+#define NV_RCE_IRQ_V1RSVD0		NV_RCE_IRQ(32)
+#define NV_RCE_IRQ_ACTMON		NV_RCE_IRQ(33)
+#define NV_RCE_IRQ_FPUINT		NV_RCE_IRQ(34)
+#define NV_RCE_IRQ_PM			NV_RCE_IRQ(35)
+#define NV_RCE_IRQ_MC_SBE		NV_RCE_IRQ(36)
+#define NV_RCE_IRQ_NOC_SECURE		NV_RCE_IRQ(37)
+#define NV_RCE_IRQ_HSP1_SI_0		NV_RCE_IRQ(38)
+#define NV_RCE_IRQ_HSP1_SI_1		NV_RCE_IRQ(39)
+#define NV_RCE_IRQ_HSP1_SI_2		NV_RCE_IRQ(40)
+#define NV_RCE_IRQ_HSP1_SI_3		NV_RCE_IRQ(41)
+#define NV_RCE_IRQ_HSP1_SI_4		NV_RCE_IRQ(42)
+#define NV_RCE_IRQ_HSP1_SI_5		NV_RCE_IRQ(43)
+#define NV_RCE_IRQ_HSP1_SI_6		NV_RCE_IRQ(44)
+#define NV_RCE_IRQ_HSP1_SI_7		NV_RCE_IRQ(45)
+#define NV_RCE_IRQ_TOP0_HSP_DB		NV_RCE_IRQ(46)
+#define NV_RCE_IRQ_CAR			NV_RCE_IRQ(47)
+#define NV_RCE_IRQ_V1RSVD16		NV_RCE_IRQ(48)
+#define NV_RCE_IRQ_CTIIRQ		NV_RCE_IRQ(49)
+#define NV_RCE_IRQ_V1RSVD18		NV_RCE_IRQ(50)
+#define NV_RCE_IRQ_I2C1		        NV_RCE_IRQ(51)
+#define NV_RCE_IRQ_I2C3		        NV_RCE_IRQ(52)
+#define NV_RCE_IRQ_I2C8		        NV_RCE_IRQ(53)
+#define NV_RCE_IRQ_DISP			NV_RCE_IRQ(54)
+#define NV_RCE_IRQ_V1RSVD23		NV_RCE_IRQ(55)
+#define NV_RCE_IRQ_HSP2_SI_0		NV_RCE_IRQ(56)
+#define NV_RCE_IRQ_HSP2_SI_1		NV_RCE_IRQ(57)
+#define NV_RCE_IRQ_HSP2_SI_2		NV_RCE_IRQ(58)
+#define NV_RCE_IRQ_HSP2_SI_3		NV_RCE_IRQ(59)
+#define NV_RCE_IRQ_HSP2_SI_4		NV_RCE_IRQ(60)
+#define NV_RCE_IRQ_HSP2_SI_5		NV_RCE_IRQ(61)
+#define NV_RCE_IRQ_HSP2_SI_6		NV_RCE_IRQ(62)
+#define NV_RCE_IRQ_HSP2_SI_7		NV_RCE_IRQ(63)
+
+#endif  /* PROCESSOR__IRQS_HW_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/irqs-lic.h b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/irqs-lic.h
new file mode 100644
index 0000000..ed73052
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/irqs-lic.h
@@ -0,0 +1,74 @@
+/*
+ * Copyright (c) 2019-2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__IRQS_LIC_H
+#define PROCESSOR__IRQS_LIC_H
+#define FSP__PROCESSOR__IRQS_LIC_H                      1
+
+#include <misc/ct-assert.h>
+#include <irq/tegra-lic-priv.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__IRQ__TEGRA_LIC_PRIV_H, "Header file missing or invalid.")
+
+#define NR_VIC_IRQS 64
+
+enum {
+	RCE_LIC_IRQ_BASE = NR_VIC_IRQS,
+	RCE_LIC_IRQ_ISP = LIC_IRQ_BASE,
+	RCE_LIC_IRQ_NVCSI,
+	RCE_LIC_IRQ_HOST1X_CAM0,
+	RCE_LIC_IRQ_HOST1X_CAM1,
+	RCE_LIC_IRQ_HOST1X_VM1,
+	RCE_LIC_IRQ_HOST1X_VM2,
+	RCE_LIC_IRQ_HOST1X_VM3,
+	RCE_LIC_IRQ_HOST1X_VM4,
+	RCE_LIC_IRQ_HOST1X_VM5,
+	RCE_LIC_IRQ_HOST1X_VM6,
+	RCE_LIC_IRQ_HOST1X_VM7,
+	RCE_LIC_IRQ_HOST1X_VM8,
+	RCE_LIC_IRQ_UARTA,
+	RCE_LIC_IRQ_UARTG,
+	RCE_LIC_IRQ_I2C0,
+	RCE_LIC_IRQ_I2C2,
+	RCE_LIC_IRQ_I2C4,
+	RCE_LIC_IRQ_I2C5,
+	RCE_LIC_IRQ_I2C6,
+	RCE_LIC_IRQ_I2C7,
+	RCE_LIC_IRQ_I2C9,
+	RCE_LIC_IRQ_I2C10,
+	RCE_LIC_IRQ_VI_VM0,
+	RCE_LIC_IRQ_VI_VM1,
+	RCE_LIC_IRQ_VI_VM2,
+	RCE_LIC_IRQ_VI_VM3,
+	RCE_LIC_IRQ_VI_VM4,
+	RCE_LIC_IRQ_VI_VM5,
+	RCE_LIC_IRQ_VI_VM6,
+	RCE_LIC_IRQ_VI_VM7,
+	RCE_LIC_IRQ_VI_VM8,
+	RCE_LIC_IRQ_RCE_HSP1,
+	RCE_LIC_IRQ_RCE_HSP2,
+	RCE_LIC_IRQ_RCE_HSP3,
+	RCE_LIC_IRQ_RCE_HSP4,
+};
+
+extern const struct tegra_lic_id tegra_lic_id_rce;
+
+#endif /* PROCESSOR__IRQS_LIC_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/tegra-uart-hw-params.h b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/tegra-uart-hw-params.h
new file mode 100644
index 0000000..fcfe0dd
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/tegra-uart-hw-params.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__UART_TEGRA_HW_PARAMS_H
+#define PROCESSOR__UART_TEGRA_HW_PARAMS_H
+#define FSP__PROCESSOR__TEGRA_UART_HW_PARAMS_H          1
+
+#include <misc/ct-assert.h>
+#include <processor/irqs-hw.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/macros.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+
+#define TEGRA_UARTF_ENABLED
+#define TEGRA_UARTF_IRQ         UINT32_MAX
+#define UART_CLOCKS
+#define UART_CAR_ACCESS
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/tke-tegra-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/tke-tegra-hw.h
new file mode 100644
index 0000000..21f5447
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/rce/processor/tke-tegra-hw.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__TKE_TEGRA_HW_H
+#define PROCESSOR__TKE_TEGRA_HW_H
+#define FSP__PROCESSOR__TKE_TEGRA_HW_H                  1
+
+extern struct tegra_tke_id tegra_tke_id_timer0;
+extern struct tegra_tke_id tegra_tke_id_timer1;
+extern struct tegra_tke_id tegra_tke_id_timer2;
+extern struct tegra_tke_id tegra_tke_id_timer3;
+
+#define TEGRA_TKE_TIMER_CLK_SRC_USECCNT		0
+#define TEGRA_TKE_TIMER_CLK_SRC_OSCCNT		1
+#define TEGRA_TKE_TIMER_CLK_SRC_TSC_BIT0	2
+#define TEGRA_TKE_TIMER_CLK_SRC_TSC_BIT12	3
+
+#endif	/* PROCESSOR__TKE_TEGRA_HW_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/sce/processor/cache-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/sce/processor/cache-hw.h
new file mode 100644
index 0000000..b59402c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/sce/processor/cache-hw.h
@@ -0,0 +1,17 @@
+/*
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__CACHE_HW_H
+#define PROCESSOR__CACHE_HW_H
+#define FSP__PROCESSOR__CACHE_HW_H                      1
+
+#define CACHE_LINE_SIZE	32
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/sce/processor/debug-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/sce/processor/debug-hw.h
new file mode 100644
index 0000000..e94d655
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/sce/processor/debug-hw.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__DEBUG_HW_H
+#define PROCESSOR__DEBUG_HW_H
+#define FSP__PROCESSOR__DEBUG_HW_H                      1
+
+#include <address_map_new.h>
+
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+#ifdef _NV_BUILD_LINSIM_
+#define TEGRA_DBG_UART_BASE     NV_ADDRESS_MAP_UARTA_BASE
+#elif defined(_NV_BUILD_FPGA_)
+#define TEGRA_DBG_UART_BASE     NV_ADDRESS_MAP_UARTC_BASE
+#else
+#define TEGRA_DBG_UART_BASE     NV_ADDRESS_MAP_UARTC_BASE
+#define TEGRA_DBG_UART_CLK      tegra_clk_uartc
+#define TEGRA_DBG_UART_RST      tegra_rst_uartc
+#define TEGRA_DBG_UART_BAUD     115200
+#endif
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/sce/processor/hsp-tegra-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/sce/processor/hsp-tegra-hw.h
new file mode 100644
index 0000000..1ec98a6
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/sce/processor/hsp-tegra-hw.h
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PROCESSOR__HSP_TEGRA_HW_H
+#define PROCESSOR__HSP_TEGRA_HW_H
+#define FSP__PROCESSOR__HSP_TEGRA_HW_H                  1
+
+#include <misc/ct-assert.h>
+#include <soc-common/hsp-tegra-top-hw.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HSP_TEGRA_TOP_HW_H, "Header file missing or invalid.")
+
+#define TEGRA_HSP_ID_MBOX tegra_hsp_id_sce
+#define TEGRA_HSP_ID_DB   tegra_hsp_id_top0
+
+#ifndef __ASSEMBLER__
+
+/* This is the TOP HSP instance w/ AON interrupts */
+extern struct tegra_hsp_id tegra_hsp_id_top0;
+extern struct tegra_hsp_id tegra_hsp_id_sce;
+
+#endif
+
+#endif /* PROCESSOR__HSP_TEGRA_HW_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/sce/processor/irqs-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/sce/processor/irqs-hw.h
new file mode 100644
index 0000000..5315b2a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/sce/processor/irqs-hw.h
@@ -0,0 +1,88 @@
+/*
+* Copyright (c) 2016-2019 NVIDIA CORPORATION.  All rights reserved.
+*
+* NVIDIA CORPORATION and its licensors retain all intellectual property
+* and proprietary rights in and to this software, related documentation
+* and any modifications thereto.  Any use, reproduction, disclosure or
+* distribution of this software and related documentation without an express
+* license agreement from NVIDIA CORPORATION is strictly prohibited.
+*/
+
+#ifndef PROCESSOR__IRQS_HW_H
+#define PROCESSOR__IRQS_HW_H
+#define FSP__PROCESSOR__IRQS_HW_H                       1
+
+#define MAX_VIC_CONTROLLER       2
+
+#define NV_AON_INTERRUPT_VIC0_BASE	0
+#define NV_AON_INTERRUPT_VIC1_BASE	32
+
+// VIC0 interrupts
+#define	NV_SCE_IRQ_WDTFIQ	 	 0
+#define	NV_SCE_IRQ_WDTIRQ	 	 1
+#define	NV_SCE_IRQ_TIMER0	 	 2
+#define	NV_SCE_IRQ_TIMER1	 	 3
+#define	NV_SCE_IRQ_TIMER2	 	 4
+#define	NV_SCE_IRQ_TIMER3	 	 5
+#define	NV_SCE_IRQ_MBOX		 	 6
+#define	NV_SCE_IRQ_GTE		 	 7
+#define	NV_SCE_IRQ_PMU		 	 8
+#define	NV_SCE_IRQ_DMA0		 	 9
+#define	NV_SCE_IRQ_DMA1			10
+#define	NV_SCE_IRQ_DMA2			11
+#define	NV_SCE_IRQ_DMA3			12
+#define	NV_SCE_IRQ_DMA4			13
+#define	NV_SCE_IRQ_DMA5			14
+#define	NV_SCE_IRQ_DMA6			15
+#define	NV_SCE_IRQ_DMA7			16
+#define	NV_SCE_IRQ_LIC0			17
+#define	NV_SCE_IRQ_LIC1			18
+#define	NV_SCE_IRQ_LIC2			19
+#define	NV_SCE_IRQ_LIC3			20
+#define	NV_SCE_IRQ_V0RSVD21		21
+#define	NV_SCE_IRQ_HSM_CRITICAL_ERR	22
+#define	NV_SCE_IRQ_VI_HP		23
+#define	NV_SCE_IRQ_VI_LP		24
+#define	NV_SCE_IRQ_HSM_HP		25
+#define	NV_SCE_IRQ_HSM_LP		26
+#define	NV_SCE_IRQ_V0RSVD27		27
+#define	NV_SCE_IRQ_V0RSVD28		28
+#define	NV_SCE_IRQ_V0RSVD29		29
+#define	NV_SCE_IRQ_V0RSVD30		30
+#define	NV_SCE_IRQ_V0RSVD31		31
+
+/* VIC1 interrupts */
+#define NV_SCE_IRQ_NOC_NON_SECURE	32
+#define	NV_SCE_IRQ_ACTMON		33
+#define	NV_SCE_IRQ_FPUINT		34
+#define	NV_SCE_IRQ_PM			35
+#define	NV_SCE_IRQ_MC_SBE		36
+#define	NV_SCE_IRQ_NOC_SECURE		37
+#define	NV_SCE_IRQ_CAR			38
+#define	NV_SCE_IRQ_V1RSVD7		39
+#define	NV_SCE_IRQ_V1RSVD8		40
+#define	NV_SCE_IRQ_V1RSVD9		41
+#define	NV_SCE_IRQ_V1RSVD10		42
+#define	NV_SCE_IRQ_V1RSVD11		43
+#define	NV_SCE_IRQ_V1RSVD12		44
+#define	NV_SCE_IRQ_V1RSVD13		45
+#define	NV_SCE_IRQ_TOP0_HSP_DB		46
+#define	NV_SCE_IRQ_V1RSVD15		47
+#define	NV_SCE_IRQ_V1RSVD16		48
+#define	NV_SCE_IRQ_CTIIRQ		49
+#define	NV_SCE_IRQ_V1RSVD18		50
+#define	NV_SCE_IRQ_I2C1			51
+#define	NV_SCE_IRQ_I2C3			52
+#define	NV_SCE_IRQ_I2C8			53
+#define	NV_SCE_IRQ_V1RSVD22		54
+#define	NV_SCE_IRQ_V1RSVD23		55
+#define	NV_SCE_IRQ_V1RSVD24		56
+#define	NV_SCE_IRQ_V1RSVD25		57
+#define	NV_SCE_IRQ_V1RSVD26		58
+#define	NV_SCE_IRQ_V1RSVD27		59
+#define	NV_SCE_IRQ_V1RSVD28		60
+#define	NV_SCE_IRQ_V1RSVD29		61
+#define	NV_SCE_IRQ_V1RSVD30		62
+#define	NV_SCE_IRQ_V1RSVD31		63
+
+#endif /* PROCESSOR__IRQS_HW_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/sce/processor/tke-tegra-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/sce/processor/tke-tegra-hw.h
new file mode 100644
index 0000000..affa199
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/sce/processor/tke-tegra-hw.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2016-2019, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef PROCESSOR__TKE_TEGRA_HW_H
+#define PROCESSOR__TKE_TEGRA_HW_H
+#define FSP__PROCESSOR__TKE_TEGRA_HW_H                  1
+
+extern struct tegra_tke_id tegra_tke_id_timer0;
+extern struct tegra_tke_id tegra_tke_id_timer1;
+extern struct tegra_tke_id tegra_tke_id_timer2;
+extern struct tegra_tke_id tegra_tke_id_timer3;
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/argpcdma-defs.h b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/argpcdma-defs.h
new file mode 100644
index 0000000..cb27cd3
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/argpcdma-defs.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ARGPCDMA_DEFS_H
+#define ARGPCDMA_DEFS_H
+#define FSP__SOC_COMMON__ARGPCDMA_DEFS_H                  1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+#include <argpcdma_flv_32ch.h>   // IWYU pragma: export
+                                 // IWYU pragma: no_include "argpcdma_flv_32ch.h"
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+
+#define HW_BUG_200667678 1
+
+/* Defines for max timeout and time to wait for busy bit to clear */
+#define GPCDMA_BURST_COMPLETE_TIME          20U
+#define GPCDMA_BURST_COMPLETION_TIMEOUT     100U
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/ast-defs.h b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/ast-defs.h
new file mode 100644
index 0000000..25086a7
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/ast-defs.h
@@ -0,0 +1,46 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
+ *
+ * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
+ * property and proprietary rights in and to this material, related
+ * documentation and any modifications thereto. Any use, reproduction,
+ * disclosure or distribution of this material and related documentation
+ * without an express license agreement from NVIDIA CORPORATION or
+ * its affiliates is strictly prohibited.
+ */
+#ifndef AST_DEFS_H
+#define AST_DEFS_H
+#define FSP__SOC_COMMON__AST_DEFS_H     1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/**
+ * @brief Number of regions each AST provides
+ */
+#define AST_NUM_REGIONS         8U
+
+static inline uint32_t
+tegra_ast_get_num_regions(void)
+{
+    return AST_NUM_REGIONS;
+}
+
+/**
+ * @brief Slave base of the DM region that contains the enable bit
+ *
+ * Not implemented on this SoC.  The value isn't important because
+ * it's only here to allow for compilation.  It will never be used
+ * at run-time.
+ */
+#define AST_DM_REGION_SLAVE_BASE_LO     0U
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/chipid-tegra-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/chipid-tegra-hw.h
new file mode 100644
index 0000000..61b47ee
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/chipid-tegra-hw.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2022 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SOC_COMMON__CHIPID_TEGRA_HW_H
+#define SOC_COMMON__CHIPID_TEGRA_HW_H
+
+#define TEGRA_FUSE_ADDRESS_MAP_SIZE  NV_ADDRESS_MAP_FUSE_CONTROLLER_SIZE
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/clk-tegra-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/clk-tegra-hw.h
new file mode 100644
index 0000000..818e044
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/clk-tegra-hw.h
@@ -0,0 +1,118 @@
+/*
+ * Copyright (c) 2015-2021 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+#ifndef SOC_COMMON__CLK_TEGRA_HW_H
+#define SOC_COMMON__CLK_TEGRA_HW_H
+#define FSP__SOC_COMMON__CLK_TEGRA_HW_H                 1
+
+extern const struct tegra_clk tegra_clk_uarta_data;
+extern const struct tegra_clk tegra_clk_uartb_data;
+extern const struct tegra_clk tegra_clk_uartc_data;
+extern const struct tegra_clk tegra_clk_uartj_data;
+extern const struct tegra_clk tegra_clk_uartf_data;
+extern const struct tegra_clk tegra_clk_uartg_data;
+extern const struct tegra_clk tegra_clk_uarth_data;
+extern const struct tegra_clk tegra_clk_aon_i2c_slow_data;
+extern const struct tegra_clk tegra_clk_i2c_slow_data;
+extern const struct tegra_clk tegra_clk_i2c1_data;
+extern const struct tegra_clk tegra_clk_i2c2_data;
+extern const struct tegra_clk tegra_clk_i2c3_data;
+extern const struct tegra_clk tegra_clk_i2c4_data;
+extern const struct tegra_clk tegra_clk_i2c6_data;
+extern const struct tegra_clk tegra_clk_i2c7_data;
+extern const struct tegra_clk tegra_clk_i2c8_data;
+extern const struct tegra_clk tegra_clk_i2c10_data;
+extern const struct tegra_clk tegra_clk_aodmic_data;
+extern const struct tegra_clk tegra_clk_spi1_data;
+extern const struct tegra_clk tegra_clk_spi2_data;
+extern const struct tegra_clk tegra_clk_spi3_data;
+
+extern struct tegra_parent_clk tegra_parent_clk_pll_aon_data;
+extern struct tegra_parent_clk tegra_parent_clk_pll_p_data;
+extern struct tegra_parent_clk tegra_parent_clk_osc_undiv_data;
+
+extern const struct tegra_rst tegra_rst_uarta_data;
+extern const struct tegra_rst tegra_rst_uartb_data;
+extern const struct tegra_rst tegra_rst_uartc_data;
+extern const struct tegra_rst tegra_rst_uartj_data;
+extern const struct tegra_rst tegra_rst_uartf_data;
+extern const struct tegra_rst tegra_rst_uartg_data;
+extern const struct tegra_rst tegra_rst_uarth_data;
+extern const struct tegra_rst tegra_rst_i2c1_data;
+extern const struct tegra_rst tegra_rst_i2c2_data;
+extern const struct tegra_rst tegra_rst_i2c3_data;
+extern const struct tegra_rst tegra_rst_i2c4_data;
+extern const struct tegra_rst tegra_rst_i2c6_data;
+extern const struct tegra_rst tegra_rst_i2c7_data;
+extern const struct tegra_rst tegra_rst_i2c8_data;
+extern const struct tegra_rst tegra_rst_i2c10_data;
+extern const struct tegra_rst tegra_rst_aodmic_data;
+extern const struct tegra_rst tegra_rst_aon_gpcdma_data;
+extern const struct tegra_rst tegra_rst_sce_gpcdma_data;
+extern const struct tegra_rst tegra_rst_rce_gpcdma_data;
+extern const struct tegra_rst tegra_rst_dce_gpcdma_data;
+extern const struct tegra_rst tegra_rst_spi1_data;
+extern const struct tegra_rst tegra_rst_spi2_data;
+extern const struct tegra_rst tegra_rst_spi3_data;
+extern const struct tegra_rst tegra_rst_can0_data;
+extern const struct tegra_rst tegra_rst_can1_data;
+
+#define tegra_clk_uarta (&tegra_clk_uarta_data)
+#define tegra_clk_uartb (&tegra_clk_uartb_data)
+#define tegra_clk_uartc (&tegra_clk_uartc_data)
+#define tegra_clk_uartj (&tegra_clk_uartj_data)
+#define tegra_clk_uartf (&tegra_clk_uartf_data)
+#define tegra_clk_uartg (&tegra_clk_uartg_data)
+#define tegra_clk_uarth (&tegra_clk_uarth_data)
+#define tegra_clk_aon_i2c_slow (&tegra_clk_aon_i2c_slow_data)
+#define tegra_clk_i2c_slow (&tegra_clk_i2c_slow_data)
+#define tegra_clk_i2c1 (&tegra_clk_i2c1_data)
+#define tegra_clk_i2c2 (&tegra_clk_i2c2_data)
+#define tegra_clk_i2c3 (&tegra_clk_i2c3_data)
+#define tegra_clk_i2c4 (&tegra_clk_i2c4_data)
+#define tegra_clk_i2c6 (&tegra_clk_i2c6_data)
+#define tegra_clk_i2c7 (&tegra_clk_i2c7_data)
+#define tegra_clk_i2c8 (&tegra_clk_i2c8_data)
+#define tegra_clk_i2c10 (&tegra_clk_i2c10_data)
+#define tegra_clk_aodmic (&tegra_clk_aodmic_data)
+#define tegra_clk_spi1 (&tegra_clk_spi1_data)
+#define tegra_clk_spi2 (&tegra_clk_spi2_data)
+#define tegra_clk_spi3 (&tegra_clk_spi3_data)
+#define tegra_parent_clk_pll_aon tegra_parent_clk_pll_aon_data
+#define tegra_parent_clk_pll_p tegra_parent_clk_pll_p_data
+#define tegra_parent_clk_osc_undiv tegra_parent_clk_osc_undiv_data
+
+#define tegra_rst_uarta (&tegra_rst_uarta_data)
+#define tegra_rst_uartb (&tegra_rst_uartb_data)
+#define tegra_rst_uartc (&tegra_rst_uartc_data)
+#define tegra_rst_uartj (&tegra_rst_uartj_data)
+#define tegra_rst_uartf (&tegra_rst_uartf_data)
+#define tegra_rst_uartg (&tegra_rst_uartg_data)
+#define tegra_rst_uarth (&tegra_rst_uarth_data)
+#define tegra_rst_i2c1 (&tegra_rst_i2c1_data)
+#define tegra_rst_i2c2 (&tegra_rst_i2c2_data)
+#define tegra_rst_i2c3 (&tegra_rst_i2c3_data)
+#define tegra_rst_i2c4 (&tegra_rst_i2c4_data)
+#define tegra_rst_i2c6 (&tegra_rst_i2c6_data)
+#define tegra_rst_i2c7 (&tegra_rst_i2c7_data)
+#define tegra_rst_i2c8 (&tegra_rst_i2c8_data)
+#define tegra_rst_i2c10 (&tegra_rst_i2c10_data)
+#define tegra_rst_aodmic (&tegra_rst_aodmic_data)
+#define tegra_rst_aon_gpcdma (&tegra_rst_aon_gpcdma_data)
+#define tegra_rst_sce_gpcdma (&tegra_rst_sce_gpcdma_data)
+#define tegra_rst_rce_gpcdma (&tegra_rst_rce_gpcdma_data)
+#define tegra_rst_dce_gpcdma (&tegra_rst_dce_gpcdma_data)
+#define tegra_rst_spi1 (&tegra_rst_spi1_data)
+#define tegra_rst_spi2 (&tegra_rst_spi2_data)
+#define tegra_rst_spi3 (&tegra_rst_spi3_data)
+#define tegra_rst_can0 (&tegra_rst_can0_data)
+#define tegra_rst_can1 (&tegra_rst_can1_data)
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/hsp-tegra-sm.h b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/hsp-tegra-sm.h
new file mode 100644
index 0000000..b16d835
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/hsp-tegra-sm.h
@@ -0,0 +1,189 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef HSP__HSP_TEGRA_SM_H
+#define HSP__HSP_TEGRA_SM_H
+#define FSP__HSP__HSP_TEGRA_SM_H                           1
+
+/* Compiler headers */
+#include <stdint.h>                     // for uint32_t
+#include <stdbool.h>                    // for bool
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>        // for error_t, FSP__ERROR__COMMON...
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <hsp/hsp-tegra.h>              // hsp128_t, struct tegra_hsp_id...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @brief check if 128-bit mailbox is empty or not
+ *
+ * @jama_func_req_id 10709223
+ *
+ * This function indicates whether the 128-bit mailbox is empty or not.
+ *
+ * @param[in] id HSP instance.
+ * @param[in] sm Shared mailbox index to which data has to be written.
+ *            Range: [0- MAX SM INDEX of the instance]
+ *
+ * @retval True indicates that the mailbox is empty
+ * @retval False indicates that the mailbox is not empty
+ */
+bool tegra_hsp_sm_128_is_empty(const struct tegra_hsp_id *id,
+                               uint32_t sm);
+
+/**
+ * @brief clear contents of the 128-bit shared mailbox register
+ *
+ * @jama_func_req_id 10709412
+ *
+ * This function clears the contents of the 128-bit shared mailbox register.
+ *
+ * @param[in] id HSP instance.
+ * @param[in] sm Shared mailbox index. Range: [0- MAX SM INDEX of the instance]
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_MBOX invalid shared mailbox index
+ */
+error_t tegra_hsp_sm_vacate_128(const struct tegra_hsp_id *id,
+                                uint32_t sm);
+
+/**
+ * @brief read the 128-bit HSP shared mailbox without clearing it
+ *
+ * @jama_func_req_id 10709247
+ *
+ * this function fetches the 128-bit data field of the mailbox register
+ * without modifying its contents.
+ *
+ * @param[in] id    HSP instance.
+ * @param[in] sm    Shared mailbox index. Range: [0- MAX SM INDEX supported]
+ * @param[in] data  pointer to where the 128-bit mailbox data field is
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_MBOX invalid shared mailbox index
+ * @retval E_HSP_ERR_EMPTY_MBOX mailbox tag field is empty
+ */
+error_t tegra_hsp_sm_peek_128(const struct tegra_hsp_id *id,
+                              uint32_t sm,
+                              hsp128_t *data);
+
+/**
+ * @brief read the 128-bit HSP shared mailbox by clearing the contents
+ *
+ * @jama_func_req_id 10708695
+ *
+ * This function returns the 128-bit data field of the shared mailbox register
+ * by clearing the contents of it.
+ *
+ * @param[in] id    HSP instance.
+ * @param[in] sm    Shared mailbox index. Range: [0- MAX SM INDEX supported]
+ * @param[in] data  pointer to where the 128-bit mailbox data field is
+ *                  written to.
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_MBOX invalid shared mailbox index
+ * @retval E_HSP_ERR_EMPTY_MBOX mailbox tag field is empty
+ */
+error_t tegra_hsp_sm_consume_128(const struct tegra_hsp_id *id,
+                                 uint32_t sm,
+                                 hsp128_t *data);
+
+/**
+ * @brief write to the 128-bit HSP shared mailbox register with TAG bit
+ *
+ * @jama_func_req_id 10708650
+ *
+ * This function writes the mailbox register with the specified value in
+ * the 128-bit data field and sets the TAG bit.
+ *
+ * @param[in] id HSP instance.
+ * @param[in] sm Shared mailbox index. Range: [0- MAX SM INDEX of the instance]
+ * @param[in] value value to be written to the 128-bit data field.
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_MBOX invalid shared mailbox index
+ * @retval E_HSP_ERR_INVALID_DATA if 0xDEAD1001 is written due to HW bug 200395605
+ */
+error_t tegra_hsp_sm_produce_128(const struct tegra_hsp_id *id,
+                                 uint32_t sm,
+                                 hsp128_t const *value);
+
+/**
+ * @brief set HSP shared mailbox type.
+ *
+ * @jama_func_req_id 10710072
+ *
+ * This function sets the HSP shared mailbox type as to whether it is treated
+ * as 32-bit or 128-bit.
+ *
+ * @pre the function tegra_hsp_db_init()/tegra_hsp_init() has been called
+ *
+ * @param[in] id   HSP instance.
+ * @param[in] sm   Shared mailbox index. Range: [0- MAX SM INDEX of the instance]
+ * @param[in] type Shared mailbox type. Range: [HSP_SM_TYPE_32 - HSP_SM_TYPE_128]
+ *
+ * @retval E_SUCCESS indicates success
+ * @retval E_HSP_ERR_NULL_PTR invalid id paramter passed
+ * @retval E_HSP_ERR_NO_MBOX invalid shared mailbox index
+ */
+error_t tegra_hsp_set_sm_type(struct tegra_hsp_id *id,
+                              uint32_t sm,
+                              uint32_t type);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/hsp-tegra-top-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/hsp-tegra-top-hw.h
new file mode 100644
index 0000000..0ef41bb
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/hsp-tegra-top-hw.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SOC_COMMON__HSP_TEGRA_TOP_HW_H
+#define SOC_COMMON__HSP_TEGRA_TOP_HW_H
+#define FSP__SOC_COMMON__HSP_TEGRA_TOP_HW_H             1
+
+/* FIXME: There should be a header to define this: */
+/* define doorbell master ID */
+#define TEGRA_HSP_DB_MASTER_TZ                  0x0
+#define TEGRA_HSP_DB_MASTER_CCPLEX              0x1
+#define TEGRA_HSP_DB_MASTER_CCPMU               0x2
+#define TEGRA_HSP_DB_MASTER_BPMP_FW             0x3
+#define TEGRA_HSP_DB_MASTER_SPE                 0x4
+#define TEGRA_HSP_DB_MASTER_AON                 0x4
+#define TEGRA_HSP_DB_MASTER_SCE                 0x5
+#define TEGRA_HSP_DB_MASTER_DMA                 0x6
+#define TEGRA_HSP_DB_MASTER_TSECA_NONSECURE     0x7
+#define TEGRA_HSP_DB_MASTER_TSECB_NONSECURE     0x8
+#define TEGRA_HSP_DB_MASTER_JTAGM_DFT           0x9
+#define TEGRA_HSP_DB_MASTER_CSITE               0xA
+#define TEGRA_HSP_DB_MASTER_APE                 0xB
+#define TEGRA_HSP_DB_MASTER_PEATRANS            0xC
+#define TEGRA_HSP_DB_MASTER_NVDEC_NONSECURE     0xD
+#define TEGRA_HSP_DB_MASTER_RCE                 0xE
+#define TEGRA_HSP_DB_MASTER_NVDEC1_NONSECURE    0xF
+#define TEGRA_HSP_DB_MASTER_PSC_FW_USER         0x10
+#define TEGRA_HSP_DB_MASTER_PSC_FW_SUPERVISOR   0x11
+#define TEGRA_HSP_DB_MASTER_PSC_FW_MACHINE      0x12
+#define TEGRA_HSP_DB_MASTER_PSC_BOOT            0x13
+#define TEGRA_HSP_DB_MASTER_BPMP_BOOT           0x14
+#define TEGRA_HSP_DB_MASTER_TSECA_LIGHTSECURE   0x15
+#define TEGRA_HSP_DB_MASTER_TSECB_LIGHTSECURE   0x16
+#define TEGRA_HSP_DB_MASTER_NVDEC_LIGHTSECURE   0x17
+#define TEGRA_HSP_DB_MASTER_NVDEC1_LIGHTSECURE  0x18
+#define TEGRA_HSP_DB_MASTER_TSECA_HEAVYSECURE   0x19
+#define TEGRA_HSP_DB_MASTER_TSECB_HEAVYSECURE   0x1A
+#define TEGRA_HSP_DB_MASTER_NVDEC_HEAVYSECURE   0x1B
+#define TEGRA_HSP_DB_MASTER_NVDEC1_HEAVYSECURE  0x1C
+#define TEGRA_HSP_DB_MASTER_DCE                 0x1D
+#define TEGRA_HSP_DB_MASTER_CBB_INTERNAL        0x1E
+#define TEGRA_HSP_DB_MASTER_RSVD                0x3F
+#define TEGRA_HSP_DB_MASTER_MAXNUM              0x3F
+#define TEGRA_HSP_DB_MASTER_NON_SECURE          TEGRA_HSP_DB_MASTER_NVDEC1_NONSECURE
+
+/* FIXME: There should be a header to define this: */
+/* define doorbell number and usage*/
+#define TEGRA_HSP_DB_DPMU       0
+#define TEGRA_HSP_DB_CCPLEX     1
+#define TEGRA_HSP_DB_CCPLEX_TZ  2
+#define TEGRA_HSP_DB_BPMP       3
+#define TEGRA_HSP_DB_SPE        4
+#define TEGRA_HSP_DB_SCE        5
+#define TEGRA_HSP_DB_APE        6
+#define TEGRA_HSP_DB_RCE        7
+#define TEGRA_HSP_DB_DCE        8
+#define TEGRA_HSP_DB_PSC        9
+#define TEGRA_HSP_DB_MAXNUM     10
+
+#endif /* SOC_COMMON__HSP_TEGRA_TOP_HW_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/hw-const.h b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/hw-const.h
new file mode 100644
index 0000000..3f8e771
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/hw-const.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2019 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef SOC_COMMON__HW_CONST_H
+#define SOC_COMMON__HW_CONST_H
+#define FSP__SOC_COMMON__HW_CONST_H                     1
+
+#ifndef __ASSEMBLER__
+
+#include <misc/macros.h>
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_20_10, "Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#ifndef MK_U32_CONST
+#define MK_U32_CONST(_constant_)        (_constant_##UL)
+#endif
+
+#ifndef MK_ADDR_CONST
+#define MK_ADDR_CONST(_constant_)       (_constant_##UL)
+#endif
+
+#ifndef MK_ENUM_CONST
+#define MK_ENUM_CONST(_constant_)       (_constant_##UL)
+#endif
+
+#ifndef MK_MASK_CONST
+#define MK_MASK_CONST(_constant_)       (_constant_##UL)
+#endif
+
+#ifndef MK_SHIFT_CONST
+#define MK_SHIFT_CONST(_constant_)      (_constant_##UL)
+#endif
+
+#ifndef MK_FIELD_CONST
+#define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) << (_shift_))
+#endif
+
+#ifndef MK_U64_ADDR_CONST
+#define MK_U64_ADDR_CONST(_constant_)   (_constant_##ULL)
+#endif
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_20_10, "Approval: Bug 200532008, DR: SWE-FSP-035-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#else
+
+#define MK_U32_CONST(_constant_)        (_constant_)
+#define MK_ADDR_CONST(_constant_)       (_constant_)
+#define MK_ENUM_CONST(_constant_)       (_constant_)
+#define MK_MASK_CONST(_constant_)       (_constant_)
+#define MK_SHIFT_CONST(_constant_)      (_constant_)
+
+#define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) << (_shift_))
+
+#endif /* __ASSEMBLER__ */
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/i2c-defs.h b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/i2c-defs.h
new file mode 100644
index 0000000..5e6a011
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/i2c-defs.h
@@ -0,0 +1,287 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef I2C_DEFS_H
+#define I2C_DEFS_H
+#define FSP__SOC_COMMON__I2C_DEFS_H                  1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>  // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/bitops.h>     // for BIT, FSP__MISC__BITOPS_H
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+
+/**
+ * @brief Maximum I2C controller.
+ *
+ * Maximum number of I2C controller supported by the I2C drivers.
+ */
+#define TEGRA234_I2C1       1U
+#define TEGRA234_I2C2       2U
+#define TEGRA234_I2C3       3U
+#define TEGRA234_I2C4       4U
+#define TEGRA234_I2C5       5U
+#define TEGRA234_I2C6       6U
+#define TEGRA234_I2C7       7U
+#define TEGRA234_I2C8       8U
+#define TEGRA234_I2C9       9U
+#define TEGRA234_I2C10      10U
+#define TEGRA234_I2C_MAX    10U
+
+#define I2C_MAX_CTRLS       TEGRA234_I2C_MAX
+
+/**
+ * @brief Defines for I2C configuration register
+ *
+ * @I2C_CNFG_REG Config register offset
+ * @I2C_CNFG_DEBOUNCE_CNT_SHIFT Debounce count for sda and scl
+ * @I2C_CNFG_PACKET_MODE_EN 1 - intiate transfer in packet mode
+ * @I2C_CNFG_NEW_MASTER_FSM for compatibility with FSM
+ */
+#define I2C_CNFG_REG                        0x0U
+#define I2C_CNFG_DEBOUNCE_CNT_SHIFT         12U
+#define I2C_CNFG_MULTI_MASTER_MODE          BIT(17)
+#define I2C_CNFG_PACKET_MODE_EN             BIT(10U)
+#define I2C_CNFG_NEW_MASTER_FSM             BIT(11U)
+
+/**
+ * @brief Defines for I2C status register
+ *
+ * @I2C_STS_REG offset of Status register
+ * @I2C_STATUS_BUSY 1 - Busy 0 - Not Busy
+ */
+#define I2C_STS_REG                         0x1cU
+#define I2C_STATUS_BUSY                     BIT(8U)
+
+/**
+ * @brief Defines for I2C fifo register
+ *
+ * @I2C_TX_FIFO SW writes into this register
+ * @I2C_RX_FIFO SW reads from this register
+ */
+#define I2C_TX_FIFO                         0x050U
+#define I2C_RX_FIFO                         0x054U
+
+/**
+ * @brief Defines for I2C interrupt register
+ *
+ * @I2C_INT_MASK Interrupt mask register offset
+ * @I2C_INT_STATUS Interrupt status register offset
+ * @I2C_INT_SPURIOUS SW defined bit for spurious interrupts
+ * @I2C_INT_TXN_TIMEOUT SW defined bit for transaction timeout
+ * @I2C_INT_BUS_CLEAR_DONE Bus clear done status
+ * @I2C_INT_PACKET_XFER_COMPLETE A packet has been transferred succesfully
+ * @I2C_INT_ALL_PACKETS_XFER_COMPLETE All packets transferred succesfully
+ * @I2C_INT_TX_FIFO_OVERFLOW TX fifo overflow
+ * @I2C_INT_RX_FIFO_UNDERFLOW RX fifo overflow
+ * @I2C_INT_NO_ACK No Acknowledge from slave
+ * @I2C_INT_ARB_LOST Arbitration last
+ * @I2C_INT_TX_FIFO_DATA_REQ TX fifo data request
+ * @I2C_INT_RX_FIFO_DATA_REQ RX fifo data request
+ */
+#define I2C_INT_MASK                        0x064U
+#define I2C_INT_STATUS                      0x068U
+#define I2C_INT_SPURIOUS                    BIT(15U) /* sw-defined */
+#define I2C_INT_TXN_TIMEOUT                 BIT(14U) /* sw-defined */
+#define I2C_INT_DISABLE_PACKET_FAIL         BIT(13U) /* sw-defined */
+#define I2C_INT_EVENT_BIT_SET_FAIL          BIT(12U) /* sw-defined */
+#define I2C_INT_BUS_CLEAR_DONE              BIT(11U)
+#define I2C_INT_PACKET_XFER_COMPLETE        BIT(7U)
+#define I2C_INT_ALL_PACKETS_XFER_COMPLETE   BIT(6U)
+#define I2C_INT_TX_FIFO_OVERFLOW            BIT(5U)
+#define I2C_INT_RX_FIFO_UNDERFLOW           BIT(4U)
+#define I2C_INT_NO_ACK                      BIT(3U)
+#define I2C_INT_ARB_LOST                    BIT(2U)
+#define I2C_INT_TX_FIFO_DATA_REQ            BIT(1U)
+#define I2C_INT_RX_FIFO_DATA_REQ            BIT(0U)
+
+/**
+ * @brief Defines for I2C clock divisor register
+ *
+ * @I2C_CLK_DIVISOR clock divisor register offset
+ * @I2C_CLK_DIVISOR_STD_FAST_MASK Standard Fast mode mask
+ * @I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT Standard Fast mode shift bits
+ * @I2C_CLK_MULTIPLIER_STD_FAST_MODE Multiplier for Standard fast mode
+ */
+#define I2C_CLK_DIVISOR                     0x06cU
+#define I2C_CLK_DIVISOR_STD_FAST_MASK       (0xFFFFUL << 16U)
+#define I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT 16U
+#define I2C_CLK_MULTIPLIER_STD_FAST_MODE    8U
+
+/**
+ * @brief Defines for packet header fields as per I2C packet transfer protocol
+ *
+ * @I2C_HEADER_HIGHSPEED_MODE enable HS mode of operation
+ * @I2C_HEADER_CONT_ON_NAK Continue on No Ack from slave
+ * @I2C_HEADER_READ Read transaction
+ * @I2C_HEADER_10BIT_ADDR 10 bit slave address
+ * @I2C_HEADER_REPEAT_START to continue or end transaction
+ * @I2C_HEADER_CONTINUE_XFER Override Repeated start
+ * @I2C_HEADER_MASTER_ADDR_SHIFT High Speed mode Master code shift
+ * @I2C_HEADER_SLAVE_ADDR_SHIFT slave address shift
+ */
+#define I2C_HEADER_HIGHSPEED_MODE           BIT(22U)
+#define I2C_HEADER_CONT_ON_NAK              BIT(21U)
+#define I2C_HEADER_READ                     BIT(19U)
+#define I2C_HEADER_10BIT_ADDR               BIT(18U)
+#define I2C_HEADER_IE                       BIT(17U)
+#define I2C_HEADER_REPEAT_START             BIT(16U)
+#define I2C_HEADER_CONTINUE_XFER            BIT(15U)
+#define I2C_HEADER_MASTER_ADDR_SHIFT        12U
+#define I2C_HEADER_SLAVE_ADDR_SHIFT         1U
+
+/**
+ * @brief Defines for I2C configuration load register
+ *
+ * @I2C_CONFIG_LOAD_REG configuration load register offset
+ * @I2C_MSTR_CONFIG_LOAD load master configuration
+ * @I2C_SLV_CONFIG_LOAD load slave configuration
+ * @I2C_TIMEOUT_CONFIG_LOAD load timeout configuration
+ */
+#define I2C_CONFIG_LOAD_REG                 0x8cU
+#define I2C_MSTR_CONFIG_LOAD                BIT(0U)
+#define I2C_SLV_CONFIG_LOAD                 BIT(1U)
+#define I2C_TIMEOUT_CONFIG_LOAD             BIT(2U)
+
+/**
+ * @brief Defines for I2C clock enable override register
+ *
+ * @I2C_CLKEN_OVERRIDE clock enable override register offset
+ * @I2C_MST_CORE_CLKEN_OVR override for 2nd-level clock enable for I2C master
+ */
+#define I2C_CLKEN_OVERRIDE                  0x90U
+#define I2C_MST_CORE_CLKEN_OVR              1U
+
+/**
+ * @brief Defines for I2C interface timing Register
+ *
+ * @I2C_INTERFACE_TIMING Interface timing register offset
+ * @I2C_INTERFACE_MASK Interface timing register mask
+ * @I2C_THIGH_SHIFT bit shift value for THIGH
+ */
+#define I2C_INTERFACE_TIMING                0x94U
+#define I2C_INTERFACE_MASK                  (0x3FU)
+#define I2C_THIGH_SHIFT                     8U
+
+/**
+ * @brief Defines for I2C master reset register
+ *
+ * @I2C_MSTR_RESET master reset register offset
+ * @I2C_MSTR_SOFT_RESET 1 - reset master internal state, 0 - normal operation
+ */
+#define I2C_MSTR_RESET                      0xa8U
+#define I2C_MSTR_SOFT_RESET                 BIT(0U)
+
+/*
+ * FIFO size has been increased in T194 and to account for that,
+ * the FIFO control/status registers have been split into
+ * separate master and slave registers. Here we map the defines
+ * to the master registers, since that is sufficient for our use case.
+ */
+
+/**
+ * @brief Defines for I2C master packet transfer status register
+ *
+ * @I2C_PACKET_XFER_STATUS Number of packets transferred in the current packet
+ */
+#define I2C_PACKET_XFER_STATUS              0x0b0U
+
+/**
+ * @brief Defines for I2C master fifo control Register
+ *
+ * @I2C_FIFO_CONTROL Fifo control register offset
+ * @I2C_FIFO_CONTROL_TX_FLUSH Flush the TX fifo
+ * @I2C_FIFO_CONTROL_RX_FLUSH Flush the RX fifo
+ * @I2C_FIFO_CONTROL_TX_TRIG_SHIFT Master Transmit fifo trigger level shift
+ * @I2C_FIFO_CONTROL_RX_TRIG_SHIFT Master Receive fifo trigger level shift
+ */
+#define I2C_FIFO_CONTROL                    0x0b4U
+#define I2C_FIFO_CONTROL_TX_FLUSH           BIT(1U)
+#define I2C_FIFO_CONTROL_RX_FLUSH           BIT(0U)
+#define I2C_FIFO_CONTROL_TX_TRIG_SHIFT      16U
+#define I2C_FIFO_CONTROL_RX_TRIG_SHIFT      4U
+
+/**
+ * @brief Defines for I2C master fifo status Register
+ *
+ * @I2C_FIFO_STATUS Fifo status register offset
+ * @I2C_FIFO_STATUS_TX_MASK Transfer fifo empty slot count mask
+ * @I2C_FIFO_STATUS_TX_SHIFT Transfer fifo empty slot count shift
+ * @I2C_FIFO_STATUS_RX_MASK Receive fifo full slot count mask
+ * @I2C_FIFO_STATUS_RX_SHIFT Receive fifo full slot count shift
+ */
+#define I2C_FIFO_STATUS                     0x0b8U
+#define I2C_FIFO_STATUS_TX_MASK             0xff0000U
+#define I2C_FIFO_STATUS_TX_SHIFT            16U
+#define I2C_FIFO_STATUS_RX_MASK             0xffU
+#define I2C_FIFO_STATUS_RX_SHIFT            0U
+
+/**
+ * @brief Defines for I2C master fifo status Register
+ *
+ * @I2C_FIFO_STATUS Fifo status register offset
+ * @I2C_FIFO_STATUS_TX_MASK Transfer fifo empty slot count mask
+ * @I2C_FIFO_STATUS_TX_SHIFT Transfer fifo empty slot count shift
+ * @I2C_FIFO_STATUS_RX_MASK Receive fifo full slot count mask
+ * @I2C_FIFO_STATUS_RX_SHIFT Receive fifo full slot count shift
+ */
+#define I2C_FIFO_STATUS                     0x0b8U
+#define I2C_FIFO_STATUS_TX_MASK             0xff0000U
+#define I2C_FIFO_STATUS_TX_SHIFT            16U
+#define I2C_FIFO_STATUS_RX_MASK             0xffU
+#define I2C_FIFO_STATUS_RX_SHIFT            0U
+
+#define PACKET_HEADER0_PACKET_ID_SHIFT      16U
+#define PACKET_HEADER0_CONT_ID_SHIFT        12U
+#define PACKET_HEADER0_PROTOCOL_I2C         BIT(4U)
+
+#define I2C_BUS_STATUS                      0x0d0U
+#define I2C_BUS_STATUS_BUSY_MASK            BIT(0U)
+#define I2C_BUS_STATUS_SDA_MASK             BIT(1U)
+#define I2C_BUS_STATUS_SCL_MASK             BIT(2U)
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/i2c-dependencies.h b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/i2c-dependencies.h
new file mode 100644
index 0000000..f2a2009
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/i2c-dependencies.h
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SOC_COMMON__I2C_DEPENDENCIES_H
+#define SOC_COMMON__I2C_DEPENDENCIES_H
+#define FSP__SOC_COMMON__I2C_DEPENDENCIES_H             1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/bitops.h>
+#include <error/common-errors.h>
+
+/* Module-specific FSP headers */
+#include <processor/i2c-tegra-hw.h>
+#include <soc-common/i2c-defs.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__I2C_TEGRA_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__I2C_DEFS_H, "Header file missing or invalid.")
+
+/**
+ * @defgroup I2C_PORT_APIS Client Firmware Dependent Apis.
+ * @{
+ */
+#ifdef I2C_CUSTOM_PORT_INIT
+/* @brief Custom port init. Any FW specific OS implementations can be added in
+ * this API.
+ *
+ * @param[in] ctrl_id         I2C Controller ID
+ * @retval    E_SUCCESS       Message complete signalled.
+ * @retval    E_INVALID_PARAM Invalid ctrl_id.
+ * @retval    FW_error_code   error from FW event signal api.
+ */
+error_t appfw_port_init(uint32_t ctrl_id);
+#else
+
+/**
+ * @brief Create Mutex lock.
+ *
+ * @param[in] ctrl_id         I2C Controller ID
+ * @retval    E_SUCCESS       Message complete signalled.
+ * @retval    E_INVALID_PARAM Invalid ctrl_id.
+ * @retval    FW_error_code   error from FW event signal api.
+ */
+error_t appfw_mutex_create(uint32_t ctrl_id);
+#endif
+
+/**
+ * @brief Release Mutex lock.
+ *
+ * @param[in] ctrl_id         I2C Controller ID
+ * @retval    E_SUCCESS       Message complete signalled.
+ * @retval    E_INVALID_PARAM Invalid ctrl_id.
+ * @retval    FW_error_code   error from FW event signal api.
+ */
+error_t appfw_mutex_release(uint32_t ctrl_id);
+
+/**
+ * @brief Acquire Mutex lock.
+ *
+ * @param[in] ctrl_id         I2C Controller ID
+ * @param[in] timeout         timeout for the acquire operation.
+ * @retval    E_SUCCESS       Message complete signalled.
+ * @retval    E_INVALID_PARAM Invalid ctrl_id.
+ * @retval    FW_error_code   error from FW event signal api.
+ */
+error_t appfw_mutex_acquire(uint32_t ctrl_id, uint32_t timeout);
+
+/**
+ * @brief Wait I2C controller interrupt.
+ *
+ * @param[in] ctrl_id         I2C Controller ID
+ * @param[in] timeout         timeout in ms
+ * @retval    E_SUCCESS       Succesfully received IRQ
+ * @retval    E_TIMEOUT       IRQ not received within timeout
+ */
+error_t appfw_wait_irq(uint32_t ctrl_id, uint32_t timeout);
+
+/**
+ * @brief Get the current timer value in microseconds.
+ *
+ * @retval    64-bit             Current timer value
+ */
+uint64_t appfw_timer_cur_us(void);
+
+/**
+ * @brief Halt the task execution for specified microseconds.
+ *
+ * @param[in] delay           Time to halt the task execution.
+ */
+void appfw_udelay(uint32_t delay);
+
+/**
+ * @brief Assert, delay and deassert the reset signal.
+ *
+ * @param[in] ctrl_id         I2C Controller ID
+ * @param[in] delay           Delay between assert and deassert
+ * @retval    E_SUCCESS       Message complete signalled.
+ * @retval    E_INVALID_PARAM Invalid ctrl_id.
+ * @retval    FW_error_code   error from FW event signal api.
+ */
+error_t appfw_clk_reset_pulse(uint32_t ctrl_id, uint32_t delay);
+
+/**
+ * @brief Configure the clock rate for the controller corresponding to the
+ * controller ID passed. In case the FW has a clk_init before i2c_init,
+ * clk_get_rate() can be returned. If the FW does not have a dedicated clk_init,
+ * clk_set_rate() is to be returned.
+ *
+ * @param[in] ctrl_id         I2C Controller ID
+ * @retval    E_SUCCESS       Message complete signalled.
+ * @retval    E_INVALID_PARAM Invalid ctrl_id.
+ * @retval    FW_error_code   error from FW event signal api.
+ */
+int64_t appfw_configure_ctrl_clk_rate(uint32_t ctrl_id);
+
+/**
+ * @brief Enable the clk for the controller corresponding to the controller ID.
+ *
+ * @param[in] ctrl_id         I2C Controller ID
+ * @retval    E_SUCCESS       Message complete signalled.
+ * @retval    E_INVALID_PARAM Invalid ctrl_id.
+ * @retval    FW_error_code   error from FW event signal api.
+ */
+error_t appfw_clk_enable(uint32_t ctrl_id);
+
+/**
+ * @brief Disable the clk for the controller corresponding to the controller ID.
+ *
+ * @param[in] ctrl_id         I2C Controller ID
+ * @retval    E_SUCCESS       Message complete signalled.
+ * @retval    E_INVALID_PARAM Invalid ctrl_id.
+ * @retval    FW_error_code   error from FW event signal api.
+ */
+error_t appfw_clk_disable(uint32_t ctrl_id);
+
+/**
+ * @brief Enable the irq corresponding to the controller id passed
+ *
+ * @param[in] ctrl_id         I2C Controller ID
+ */
+void appfw_irq_enable(uint32_t ctrl_id);
+
+/**
+ * @brief Disable the irq corresponding to the controller id passed
+ *
+ * @param[in] ctrl_id         I2C Controller ID
+ */
+void appfw_irq_disable(uint32_t ctrl_id);
+
+/**
+ * @brief Return the configuration data corresponding to the controller id passed.
+ *
+ * @param[in] ctrl_id         I2C Controller ID
+ * @retval    NULL            Invalid controller ID
+ * @retval    struct_pointer  Pointer to valid structure
+ */
+struct i2c_config_data *i2c_get_config_data(uint32_t ctrl_id);
+
+/**
+ * @brief Return the pointer to the i2c_tegra_handle structure corresponding to
+ * the controller id passed.
+ *
+ * @param[in] ctrl_id         I2C Controller ID
+ * @retval    NULL            Invalid controller ID
+ * @retval    struct_pointer  Pointer to valid structure
+ */
+struct i2c_tegra_handle *i2c_get_tegra_handle(uint32_t ctrl_id);
+/** @} */
+
+#endif      /* I2C_DEPENDENCIES_H */
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/tegra-gpio-hw.h b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/tegra-gpio-hw.h
new file mode 100644
index 0000000..538c078
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/soc-common/tegra-gpio-hw.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PROCESSOR__GPIO_TEGRA_HW_H
+#define PROCESSOR__GPIO_TEGRA_HW_H
+#define FSP__PROCESSOR__GPIO_TEGRA_HW_H                  1
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Late FSP headers */
+#include <soc-common/hw-const.h>        // for MK_U32_CONST
+
+/* Module-specific FSP headers */
+#include <gpio/tegra-gpio.h>            // for #define MAX_GPIO_CONTROLLERS
+#include <gpio/tegra-gpio-priv.h>       // for struct tegra_gpio_id
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__GPIO__TEGRA_GPIO_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__GPIO__TEGRA_GPIO_PRIV_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+/* GPIOs implemented by main GPIO controller */
+#define TEGRA_GPIO_BANK_ID_A    MK_U32_CONST(0)
+#define TEGRA_GPIO_BANK_ID_B    MK_U32_CONST(1)
+#define TEGRA_GPIO_BANK_ID_C    MK_U32_CONST(2)
+#define TEGRA_GPIO_BANK_ID_D    MK_U32_CONST(3)
+#define TEGRA_GPIO_BANK_ID_E    MK_U32_CONST(4)
+#define TEGRA_GPIO_BANK_ID_F    MK_U32_CONST(5)
+#define TEGRA_GPIO_BANK_ID_G    MK_U32_CONST(6)
+#define TEGRA_GPIO_BANK_ID_H    MK_U32_CONST(7)
+#define TEGRA_GPIO_BANK_ID_I    MK_U32_CONST(8)
+#define TEGRA_GPIO_BANK_ID_J    MK_U32_CONST(9)
+#define TEGRA_GPIO_BANK_ID_K    MK_U32_CONST(10)
+#define TEGRA_GPIO_BANK_ID_L    MK_U32_CONST(11)
+#define TEGRA_GPIO_BANK_ID_M    MK_U32_CONST(12)
+#define TEGRA_GPIO_BANK_ID_N    MK_U32_CONST(13)
+#define TEGRA_GPIO_BANK_ID_P    MK_U32_CONST(14)
+#define TEGRA_GPIO_BANK_ID_Q    MK_U32_CONST(15)
+#define TEGRA_GPIO_BANK_ID_R    MK_U32_CONST(16)
+#define TEGRA_GPIO_BANK_ID_S    MK_U32_CONST(17)
+#define TEGRA_GPIO_BANK_ID_T    MK_U32_CONST(18)
+#define TEGRA_GPIO_BANK_ID_U    MK_U32_CONST(19)
+#define TEGRA_GPIO_BANK_ID_V    MK_U32_CONST(20)
+#define TEGRA_GPIO_BANK_ID_X    MK_U32_CONST(21)
+#define TEGRA_GPIO_BANK_ID_Y    MK_U32_CONST(22)
+#define TEGRA_GPIO_BANK_ID_Z    MK_U32_CONST(23)
+#define TEGRA_GPIO_BANK_ID_AC   MK_U32_CONST(24)
+#define TEGRA_GPIO_BANK_ID_AD   MK_U32_CONST(25)
+#define TEGRA_GPIO_BANK_ID_AE   MK_U32_CONST(26)
+#define TEGRA_GPIO_BANK_ID_AF   MK_U32_CONST(27)
+#define TEGRA_GPIO_BANK_ID_AG   MK_U32_CONST(28)
+
+/* GPIOs implemented by AON GPIO controller */
+#define TEGRA_GPIO_BANK_ID_AA   MK_U32_CONST(0)
+#define TEGRA_GPIO_BANK_ID_BB   MK_U32_CONST(1)
+#define TEGRA_GPIO_BANK_ID_CC   MK_U32_CONST(2)
+#define TEGRA_GPIO_BANK_ID_DD   MK_U32_CONST(3)
+#define TEGRA_GPIO_BANK_ID_EE   MK_U32_CONST(4)
+#define TEGRA_GPIO_BANK_ID_GG   MK_U32_CONST(5)
+
+#define TEGRA_GPIO(bank, offset) ((bank * 8) + offset)
+
+/* Main GPIO controller */
+extern struct tegra_gpio_id tegra_gpio_id_main;
+
+/* AON GPIO controller */
+extern struct tegra_gpio_id tegra_gpio_id_aon;
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/soc/t234/tsec/port/i2c-port.h b/spe-freertos-bsp/fsp/source/include/soc/t234/tsec/port/i2c-port.h
new file mode 100644
index 0000000..083d1ff
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/soc/t234/tsec/port/i2c-port.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2019-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef PORT__I2C_PORT_H
+#define PORT__I2C_PORT_H
+#define FSP__PORT__I2C_PORT_H                         1
+
+#include <misc/ct-assert.h>
+#include <osa/rtos.h>
+#include <delay/delay.h>
+#include <irq/safe-irqs.h>
+#include <clk/clk-tegra.h>
+#include <misc/attributes.h>
+#include <processor/i2c-tegra-hw.h>
+#include <soc-common/clk-tegra-hw.h>
+#include <soc-common/i2c-dependencies.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__OSA__RTOS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__DELAY__DELAY_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__IRQ__SAFE_IRQS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__CLK__CLK_TEGRA_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__PROCESSOR__I2C_TEGRA_HW_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__SOC_COMMON__CLK_TEGRA_HW_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__SOC_COMMON__I2C_DEPENDENCIES_H, "Header file missing or invalid.")
+
+#endif      /* PORT__I2C_PORT_H */
diff --git a/spe-freertos-bsp/fsp/source/include/spi-slv/spi-slave.h b/spe-freertos-bsp/fsp/source/include/spi-slv/spi-slave.h
new file mode 100644
index 0000000..4856f66
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/spi-slv/spi-slave.h
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2017-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SPI_SLAVE_H
+#define SPI_SLAVE_H
+
+#include <stdint.h>
+
+#include <spi/spi-priv.h>
+
+#define SPI_DEFAULT_MAX_CLK 10000000 /*10Mhz*/
+
+struct spi_slave_init_setup {
+    void                   *dma_id;
+    spi_dma_chan           dma_chans;
+	uint32_t               spi_max_clk_rate;
+	uint8_t                dma_slave_req;
+};
+
+void spi_slave_isr(void *data);
+
+/*
+ * Initialize and set the parameters of the requested SPI device
+ *
+ * Parameters:
+ * id:		SPI controller instance
+ * setting:	SPI device setting
+ *
+ * Returns:
+ * 0: Success
+ * Negative: error
+ */
+error_t spi_slave_setup(struct spi_ctlr *ctlr, struct spi_client_setting *setting);
+
+/*
+ * Execute SPI transfer(s) on the specified SPI slave device
+ *
+ * This function can transfer one or multiple SPI transfers.
+ *
+ * The code that submits tegra_spi_xfer to the lower layers is responsible for
+ * managing its memory.
+ *
+ * Parameters:
+ * id:		SPI controller instance
+ * xfer:	SPI transfer(s)
+ *
+ * Returns:
+ * 0: Success
+ * Negative: error
+ */
+error_t spi_slave_transfer(struct spi_ctlr *ctlr, struct spi_xfer *xfer);
+
+/*
+ * Initialize and set up the controller configuration
+ *
+ * Parameters:
+ * id:		SPI controller instance
+ * setting:	SPI controller setting
+ *
+ * Returns:
+ * 0: Success
+ * Negative: error
+ */
+error_t spi_slave_init(struct spi_ctlr *ctlr, struct spi_slave_init_setup *setting);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/spi/sections-spi.h b/spe-freertos-bsp/fsp/source/include/spi/sections-spi.h
new file mode 100644
index 0000000..c6f2d11
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/spi/sections-spi.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SPI__SECTIONS_SPI_H
+#define SPI__SECTIONS_SPI_H
+#define FSP__SPI__SECTIONS_SPI_H                    0
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_SPI_BSS           SECTION_BUILDER(spi,      bss)
+#define SECTION_NAME_SPI_DATA          SECTION_BUILDER(spi,      data)
+#define SECTION_NAME_SPI_RODATA        SECTION_BUILDER(spi,      rodata)
+#define SECTION_NAME_SPI_TEXT          SECTION_BUILDER(spi,      text)
+#define SECTION_NAME_SPI_INIT_TEXT     SECTION_BUILDER(init.spi, text)
+
+#define SECTION_STR_SPI_TEXT           STR(SECTION_NAME_SPI_TEXT)
+#define SECTION_STR_SPI_INIT_TEXT      STR(SECTION_NAME_SPI_INIT_TEXT)
+#define SECTION_STR_SPI_RODATA         STR(SECTION_NAME_SPI_RODATA)
+#define SECTION_STR_SPI_DATA           STR(SECTION_NAME_SPI_DATA)
+#define SECTION_STR_SPI_BSS            STR(SECTION_NAME_SPI_BSS)
+
+#define SECTION_SPI_TEXT               SECTION(SECTION_STR_SPI_TEXT)
+#define SECTION_SPI_INIT_TEXT          SECTION(SECTION_STR_SPI_INIT_TEXT)
+#define SECTION_SPI_RODATA             SECTION(SECTION_STR_SPI_RODATA)
+#define SECTION_SPI_DATA               SECTION(SECTION_STR_SPI_DATA)
+#define SECTION_SPI_BSS                SECTION(SECTION_STR_SPI_BSS)
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/spi/spi-errors.h b/spe-freertos-bsp/fsp/source/include/spi/spi-errors.h
new file mode 100644
index 0000000..f73ce99
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/spi/spi-errors.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SPI__SPI_ERRORS_H
+#define SPI__SPI_ERRORS_H
+#define FSP__SPI__SPI_ERRORS_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>     // IWYU pragma: export
+                                // IWYU pragma: no_include "base/module-id.h"
+#include <misc/macros.h>        // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @file uart-errors.h
+ * @brief Error codes that are specific to the SPI
+ */
+
+#define E_SPI_NULL_PTR                 MODULE_ERROR(SPI, 0UL)
+#define E_SPI_INVALID_PARAM            MODULE_ERROR(SPI, 1UL)
+#define E_SPI_ERR_CONFIG               MODULE_ERROR(SPI, 2UL)
+#define E_SPI_INIT_FAIL                MODULE_ERROR(SPI, 3UL)
+#define E_SPI_NO_INIT                  MODULE_ERROR(SPI, 4UL)
+#define E_SPI_REINIT                   MODULE_ERROR(SPI, 5UL)
+#define E_SPI_CLK_EN                   MODULE_ERROR(SPI, 6UL)
+#define E_SPI_CLK_RST                  MODULE_ERROR(SPI, 7UL)
+#define E_SPI_CLK_SET_RATE             MODULE_ERROR(SPI, 8UL)
+#define E_SPI_FIFO_NON_EMPTY           MODULE_ERROR(SPI, 9UL)
+#define E_SPI_XFER_NOT_SUPPORTED       MODULE_ERROR(SPI, 10UL)
+#define E_SPI_DMA_XFER_FAIL            MODULE_ERROR(SPI, 11UL)
+#define E_SPI_XFER_ERR                 MODULE_ERROR(SPI, 12UL)
+#define E_SPI_INVALID_CLK_RATE         MODULE_ERROR(SPI, 13UL)
+#define E_SPI_CTLR_BUSY                MODULE_ERROR(SPI, 14UL)
+#define E_SPI_PORT_INIT_FAIL           MODULE_ERROR(SPI, 15UL)
+#define E_SPI_PORT_DMA_INIT_FAIL       MODULE_ERROR(SPI, 16UL)
+#define E_SPI_PORT_SYNC_TIMEOUT        MODULE_ERROR(SPI, 17UL)
+#define E_SPI_FD_MODE_NO_SUPPORT       MODULE_ERROR(SPI, 18UL)
+
+#endif  /* SPI__SPI_ERRORS_H */
diff --git a/spe-freertos-bsp/fsp/source/include/spi/spi-port.h b/spe-freertos-bsp/fsp/source/include/spi/spi-port.h
new file mode 100644
index 0000000..ea26779
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/spi/spi-port.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SPI__SPI_PORT_H
+#define SPI__SPI_PORT_H
+#define FSP__SPI__SPI_PORT_H                      1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/bitops.h>
+#include <error/common-errors.h>
+
+/* Module-specific FSP headers */
+
+struct spi_ctlr;
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+
+void spi_port_isr_exit(const struct spi_ctlr *ctlr,
+                       bool isr_yield_flag);
+
+error_t  spi_port_init(struct spi_ctlr *ctlr);
+
+void spi_port_cache_invalidate(void *base,
+                               size_t length);
+
+void spi_port_cache_clean(void *base,
+                          size_t length);
+
+/**
+ * @brief Enable the clk for the controller corresponding to the controller ID.
+ *
+ * @jama_func_req_id xxxxxxxx
+ *
+ * @param[in] ctrl              UART Controller instance
+ * @retval    E_SUCCESS         clock enabled.
+ * @retval    E_UART_NULL_PARAM Null ctrl parameter.
+ */
+void  spi_port_clk_disable(struct spi_ctlr *ctlr);
+
+/**
+ * @brief Enable the clk for the controller corresponding to the controller ID.
+ *
+ * @jama_func_req_id xxxxxxxx
+ *
+ * @param[in] ctrl              UART Controller instance
+ * @retval    E_SUCCESS         clock enabled.
+ * @retval    E_UART_NULL_PARAM Null ctrl parameter.
+ */
+error_t spi_port_clk_enable(struct spi_ctlr *ctlr);
+
+/**
+ * @brief Assert, delay and deassert the reset signal.
+ *
+ * @jama_func_req_id xxxxxxxx
+ *
+ * @param[in] ctrl_id         UART Controller ID
+ * @param[in] delay           Delay between assert and deassert
+ * @retval    E_SUCCESS       reset successful.
+ * @retval    E_INVALID_PARAM Invalid ctrl_id.
+ */
+error_t spi_port_clk_reset_pulse(struct spi_ctlr *ctlr,
+                                 uint32_t delay);
+
+/**
+ * @brief Configure the clock rate for the controller corresponding to the
+ * controller ID passed.
+ *
+ * @jama_func_req_id xxxxxxxx
+ *
+ * @param[in] ctrl_id         UART Controller ID
+ * @retval    E_SUCCESS       Message complete signalled.
+ * @retval    E_INVALID_PARAM Invalid ctrl_id.
+ */
+error_t spi_port_clk_set_rate(struct spi_ctlr *ctlr,
+                              uint32_t rate);
+
+error_t spi_port_rx_dma_xfer_abort(struct spi_ctlr *ctlr);
+
+error_t spi_port_tx_dma_xfer_abort(struct spi_ctlr *ctlr);
+
+error_t spi_port_start_rx_dma(struct spi_ctlr *ctlr,
+                              struct spi_xfer *xfer,
+                              uint32_t len,
+                              uint32_t burst_size);
+
+error_t spi_port_start_tx_dma(struct spi_ctlr *ctlr,
+                              struct spi_xfer *xfer,
+                              uint32_t len,
+                              uint32_t burst_size);
+
+error_t spi_port_dma_init(struct spi_ctlr *ctlr);
+
+/**
+ * @brief spi transfer sync hook
+ *
+ * This function is used to block/wait until the synchronous
+ * transfer is finished.
+ *
+ * @pre the function spi_slave_init() has been called
+ *
+ * @param[in] ctlr    SPI controller instance
+ * @param[in] timeout Timeout to wait before bailing out
+ *
+ * @retval E_SUCESS                  on success
+ * @retval E_SPI_INVALID_PARAM       invalid DMA channel id
+ * @retval E_SPI_PORT_SYNC_TIMEOUT   timed out for synchronous transfers
+ */
+error_t spi_port_xfer_sync(struct spi_ctlr *ctlr,
+                           uint32_t timeout);
+
+/**
+ * @brief spi transfer sync complete hook
+ *
+ * This function is used to notify/unblock the task that is blocked on
+ * a synchronous spi transfer.
+ *
+ * @pre the function spi_init()/spi_slave_init() has been called
+ * @note called from spi_slave_isr()/spi_isr() for synchronous transfers
+ *
+ * @param[in] ctlr    SPI controller instance
+ *
+ * @retval E_SUCESS              on success
+ * @retval E_SPI_INVALID_PARAM   invalid SPI ctlr param
+ */
+error_t spi_port_xfer_sync_end(struct spi_ctlr *ctlr);
+
+#endif      /* UART_DEPENDENCIES_H */
diff --git a/spe-freertos-bsp/fsp/source/include/spi/spi-priv.h b/spe-freertos-bsp/fsp/source/include/spi/spi-priv.h
new file mode 100644
index 0000000..00e3f43
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/spi/spi-priv.h
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SPI_PRIV_H
+#define SPI_PRIV_H
+#define FSP__SPI__SPI_PRIV_H                      1
+
+/**
+ * @file spi/spi-priv.h
+ * @brief Structures that are internal to the SPI master and slave driver
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <spi/spi.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SPI__SPI_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#define MAX_CHIP_SELECT 4U
+
+/**
+ * @brief SPI controller configuration structure
+ *
+ * Structure that describes the configuration of a SPI controller.
+ *
+ * @base_addr   base address of the controller
+ * @irq         controller irq
+ * @hw_handle   port specific hw handle
+ */
+struct spi_conf {
+    uint32_t                    base_addr;
+    uint32_t                    irq;
+    const struct spi_hw_handle  *hw_handle;
+};
+
+/**
+ * @brief SPI controller context structure
+ *
+ * Structure that is used by the SPI driver to manage the SPI controller
+ * during run time.
+ *
+ * @conf                    SPI controller instance configuration
+ * @cdata                   client configuration data buffer
+ * @dma_id                  DMA instance
+ * @dma_chans               DMA channels with in the instance
+ * @cur_xfer                current transfer details
+ * @spi_clk_rate            controller clock rate
+ * @bits_per_word           bits per packet
+ * @words_per_32bit         packets per 32-bit
+ * @cur_pos                 current xfer position
+ * @bytes_per_word          bytes per packet
+ * @cur_dma_words           current dma words count
+ * @cur_direction           current xfer direction
+ * @cur_rx_pos              current rx position for the rx xfer
+ * @cur_tx_pos              current tx position for the tx xfer
+ * @dma_buf_size            dma buffer size
+ * @max_buf_size            max buffer size
+ * @tx_status               tx xfer status
+ * @rx_status               rx xfer status
+ * @status_reg              fifo status register value
+ * @cmd1_reg_val            current command1 register value
+ * @dma_ctrl_reg_val        dma control register value
+ * @def_cmd1_reg_val        default command1 register value
+ * @def_cmd2_reg_val        default command2 register value
+ * @spi_cs_timing           chip select timing
+ * @rx_dma_buf              rx dma buffer
+ * @tx_dma_buf              tx dma buffer
+ * @def_chip_select         default chip select
+ * @dma_slave_req           DMA slave request
+ * @dma_status              status of the dma transfer
+ * @is_curr_dma_xfer        flag indicating PIO/DMA current transfer
+ * @is_hw_based_cs          HW based chip select config
+ * @is_packed               current transfer packed status
+ * @busy                    controller status
+ * @slave_dma_support       DMA support for slave
+ * @inited                  controller initialization state
+ */
+struct spi_ctlr {
+    const struct spi_conf     conf;
+    struct spi_client_setting cdata[MAX_CHIP_SELECT];
+    void                      *dma_id;
+    spi_dma_chan              dma_chans;
+    struct spi_xfer           *cur_xfer;
+    uint32_t                  spi_clk_rate;
+    uint32_t                  bits_per_word;
+    uint32_t                  words_per_32bit;
+    uint32_t                  cur_pos;
+    uint32_t                  bytes_per_word;
+    uint32_t                  curr_dma_words;
+    uint32_t                  cur_direction;
+    uint32_t                  cur_rx_pos;
+    uint32_t                  cur_tx_pos;
+    uint32_t                  dma_buf_size;
+    uint32_t                  max_buf_size;
+    uint32_t                  tx_dma_status;
+    uint32_t                  rx_dma_status;
+    uint32_t                  tx_status;
+    uint32_t                  rx_status;
+    uint32_t                  status_reg;
+    uint32_t                  cmd1_reg_val;
+    uint32_t                  dma_ctrl_reg_val;
+    uint32_t                  def_cmd1_reg_val;
+    uint32_t                  def_cmd2_reg_val;
+    uint32_t                  spi_cs_timing;
+    uint32_t                  *rx_dma_buf;
+    uint32_t                  *tx_dma_buf;
+    uint8_t                   def_chip_select;
+    uint8_t                   dma_slave_req;
+    uint8_t                   dma_status;
+    bool                      is_curr_dma_xfer;
+    bool                      is_hw_based_cs;
+    bool                      is_packed;
+    bool                      busy;
+    bool                      en_full_duplex;
+    bool                      slave_dma_support;
+    bool                      inited;
+};
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/spi/spi.h b/spe-freertos-bsp/fsp/source/include/spi/spi.h
new file mode 100644
index 0000000..d06d912
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/spi/spi.h
@@ -0,0 +1,286 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SPI__SPI_H
+#define SPI__SPI_H
+#define FSP__SPI__SPI_H                      1
+
+/**
+ * @file spi/spi.h
+ * @brief functions for performing SPI operations.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>        // for error_t, FSP__ERROR__COMMON...
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+#define TEGRA_SPI_XFER_FIRST_MSG    3
+#define TEGRA_SPI_XFER_LAST_MSG     4
+#define TEGRA_SPI_XFER_HANDLE_CACHE 5
+
+#define TEGRA_SPI_NBITS_SINGLE  0x01            /* 1bit transfer */
+#define TEGRA_SPI_NBITS_DUAL    0x02            /* 2bits transfer */
+#define TEGRA_SPI_NBITS_QUAD    0x04            /* 4bits transfer, supported since T186 */
+
+#define TEGRA_SPI_CPHA          0x01            /* clock phase */
+#define TEGRA_SPI_CPOL          0x02            /* clock polarity */
+#define TEGRA_SPI_MODE_0        (0 | 0)         /* (original MicroWire) */
+#define TEGRA_SPI_MODE_1        (0 | TEGRA_SPI_CPHA)
+#define TEGRA_SPI_MODE_2        (TEGRA_SPI_CPOL | 0)
+#define TEGRA_SPI_MODE_3        (TEGRA_SPI_CPOL | TEGRA_SPI_CPHA)
+#define TEGRA_SPI_CS_HIGH       0x04            /* chipselect active high */
+#define TEGRA_SPI_LSB_FIRST     0x08            /* per-word bits-on-wire */
+#define TEGRA_SPI_3WIRE         0x10            /* SI/SO signals shared */
+#define TEGRA_SPI_LSBYTE_FIRST  0x1000          /* per-word bytes-on-wire */
+
+/*
+ * Declaration for spi_ctlr that allows the APIs to take a pointer to it
+ * without actually defining its contents here.
+ */
+struct spi_ctlr;
+
+/**
+ * @brief SPI DMA descriptor
+ *
+ * Provides a data type for the SPI dma channels for half/full duplex modes.
+ *
+ * @tx          TX dma channel
+ * @rx          TX dma channel
+ */
+typedef struct {
+    uint32_t tx, rx;
+} spi_dma_chan;
+
+/*
+ * Please refer to Tegra SPI HW manual for the meaning of following SPI timing
+ * settings
+ * chip_select:             specify which CS pin for this structure
+ * cs_setup_clk_count:      CS pin setup clock count
+ * cs_hold_clk_count:       CS pin hold clock count
+ * cs_inactive_cycles:      CS pin inactive clock count
+ * set_rx_tap_delay:        specify if the SPI device need to set RX tap delay
+ * spi_max_clk_rate:        specify the default clock rate of SPI client
+ * spi_no_dma:              flag to indicate pio or dma mode
+ */
+struct spi_client_setting {
+    uint32_t    spi_max_clk_rate;
+    int32_t     cs_setup_clk_count;
+    int32_t     cs_hold_clk_count;
+    int32_t     cs_inactive_cycles;
+    uint8_t     chip_select;
+    bool        set_rx_tap_delay;
+    bool        spi_no_dma;
+};
+
+/**
+ * @brief SPI master initialization configuration
+ *
+ * @dma_id              DMA ID of the associated GPCDMA channel
+ * @dma_channel         specify which GPCDMA channels to use for tx, rx
+ * @dma_slave_req       specify which GPCDMA slave req type is for this DMA
+ *                      request. Please check argpcdma*.h for appropriate
+ *                      setting
+ * @spi_max_clk_rate    specify the max clock rate of SPI controller
+ */
+struct spi_master_init {
+    void                   *dma_id;
+    spi_dma_chan           dma_chans;
+    uint32_t               spi_max_clk_rate;
+    uint8_t                dma_slave_req;
+};
+
+/**
+ * @brief SPI transfer descriptor
+ *
+ * @tx_buf          data to write to SPI device, or NULL if this is RX transfer
+ *                  the buffer memory need to be aligned for DMA transfer
+ * @rx_buf          buffer to hold read data, or NULL if this is TX transfer
+ *                  the buffer memory need to be aligned for DMA transfer
+ * @len             size of rx or tx buffer in bytes
+ * @spi_clk_rate    specify clock rate for current transfer
+ * @mode            spi transfer mode.
+ * @flags           Indicate first/last message.
+ * @tx_nbits        number of bits used for writing
+ * @rx_nbits        number of bits used for reading
+ * @chip select     chip select to be used for the transfer
+ * @bits_per_word   select bits_per_word
+ *
+ * When SPI can transfer in 1x,2x or 4x. It can get this tranfer information
+ * from device through tx_nbits and rx_nbits. In Bi-direction, these
+ * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
+ * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
+ */
+struct spi_xfer {
+    const void      *tx_buf;
+    void            *rx_buf;
+    uint32_t        len;
+    uint32_t        spi_clk_rate;
+    uint16_t        mode;
+    uint16_t        flags;
+    uint8_t         tx_nbits;
+    uint8_t         rx_nbits;
+    uint8_t         chip_select;
+    uint8_t         bits_per_word;
+};
+
+/**
+ * @brief SPI controller irq handler when configured as master.
+ *
+ * @jama_func_req_id xxxxxxxx
+ *
+ * This function gets called whenever a SPI controller configured.
+ * interrupt is triggered.
+ *
+ * @pre the function spi_init() has been called
+ *
+ * @param[in] data pointer for HSP context.
+ *
+ * @return None
+ */
+void spi_master_isr(void *data);
+
+/**
+ * @brief save the SPI controller context across low power state
+ *
+ * @jama_func_req_id xxxxxxxx
+ *
+ * This function restores the required controller context across power
+ * gating the hardware(SC7).
+ *
+ * @pre the function spi_init() has been called
+ *
+ * @param[in] id        SPI controller context
+ *
+ * @retval E_SUCCESS      indicates success
+ * @retval E_SPI_NULL_PTR invalid id paramter passed
+ */
+error_t spi_suspend(struct spi_ctlr *ctlr);
+
+/**
+ * @brief resume the SPI controller context across low power state
+ *
+ * @jama_func_req_id xxxxxxxx
+ *
+ * This function restores the required controller context across power
+ * gating the hardware(SC7).
+ *
+ * @pre the function spi_init() has been called
+ *
+ * @param[in] id        SPI controller context
+ *
+ * @retval E_SUCCESS      indicates success
+ * @retval E_SPI_NULL_PTR invalid id paramter passed
+ */
+error_t spi_resume(struct spi_ctlr *ctlr);
+
+/**
+ * @brief Execute a SPI transfer with the controller as the master.
+ *
+ * @jama_func_req_id xxxxxxxxx
+ *
+ * @pre the function spi_init() has been called
+ *
+ * @param[in] id        SPI controller context
+ * @param[in] xfer      SPI transfer details
+ *
+ * @retval E_SUCCESS                  indicates success
+ * @retval E_SPI_NULL_PTR             invalid id paramter passed
+ * @retval E_SPI_INVALID_PARAM        invalid DMA channel id
+ * @retval E_SPI_PORT_SYNC_TIMEOUT    transfer timed out
+ */
+error_t spi_transfer(struct spi_ctlr *ctlr,
+                     struct spi_xfer *xfer);
+
+/**
+ * @brief Client/slave setup for the SPI controller.
+ *
+ * @jama_func_req_id xxxxxxxxx
+ *
+ * @pre the function spi_init() has been called
+ *
+ * @param[in] id        SPI controller context
+ * @param[in] setting   SPI client configuration setting
+ *
+ * @retval E_SUCCESS                     indicates success
+ * @retval E_SPI_NULL_PTR                invalid id paramter passed
+ * @retval E_SPI_INVALID_PARAM           invalid controller base address
+ * @retval E_SPI_PORT_INIT_FAIL          port specific init failed
+ * @retval E_SPI_PORT_CHAN_SETUP_FAIL    port specific channel setup failed
+ */
+error_t spi_client_setup(struct spi_ctlr *ctlr,
+                         struct spi_client_setting *setting);
+
+/**
+ * @brief global initialization of the SPI controller.
+ *
+ * @jama_func_req_id xxxxxxxxx
+ *
+ * @pre None
+ *
+ * @param[in] id        SPI controller context
+ * @param[in] setting   SPI controller configuration setting
+ *
+ * @retval E_SUCCESS                     indicates success
+ * @retval E_SPI_NULL_PTR                invalid id paramter passed
+ * @retval E_SPI_INVALID_PARAM           invalid controller base address
+ * @retval E_SPI_PORT_INIT_FAIL          port specific init failed
+ * @retval E_SPI_PORT_CHAN_SETUP_FAIL    port specific channel setup failed
+ */
+error_t spi_init(struct spi_ctlr *ctlr,
+                 struct spi_master_init *setting);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/ssp/ssp.h b/spe-freertos-bsp/fsp/source/include/ssp/ssp.h
new file mode 100644
index 0000000..27ce951
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/ssp/ssp.h
@@ -0,0 +1,97 @@
+/* _NVRM_COPYRIGHT_BEGIN_
+ *
+ * Copyright 2021 by NVIDIA Corporation.  All rights reserved.  All
+ * information contained herein is proprietary and confidential to NVIDIA
+ * Corporation.  Any use, reproduction, or disclosure without the written
+ * permission of NVIDIA Corporation is prohibited.
+ *
+ * _NVRM_COPYRIGHT_END_
+ */
+#ifndef LIBNVRISCV_SSP_H
+#define LIBNVRISCV_SSP_H
+#include <stdint.h>
+#include <misc/gcc_attrs.h>
+#include <error/common-errors.h>
+
+#if NVRISCV_FEATURE_SSP_FORCE_SW_CANARY
+static inline error_t ssp_generate_and_set_canary_with_init(void) GCC_ATTR_WARN_UNUSED;
+static inline error_t ssp_generate_and_set_canary_with_init(void)
+{
+    return E_NOTSUPPORTED;
+}
+
+static inline error_t ssp_generate_and_set_canary(void) GCC_ATTR_WARN_UNUSED;
+static inline error_t ssp_generate_and_set_canary(void)
+{
+    return E_NOTSUPPORTED;
+}
+#else // NVRISCV_FEATURE_SSP_FORCE_SW_CANARY
+/*!
+ * \brief Initializes HWRNG, generates and sets stack canary.
+ * \return
+ *      NVRV_OK                success, canary is set
+ *      NVRV_ERR_NOT_SUPPORTED if SCP driver is not enabled
+ *      Other                  passed-through SCP errors
+ *
+ * This function:
+ * - Initializes HWRNG inside SCP (via SCP driver)
+ * - Generates and sets random with ssp_generate_and_set_canary()
+ * - Shuts down HWRNG
+ *
+ * \warning It should be called early at the start of module.
+ * \warning It should not be used, if module is using SCP for other purposes -
+ * in that case module should take care of SCP and just call ssp_generate_and_set_canary()
+ * \note Errors reported by this function should be considered fatal.
+ */
+error_t ssp_generate_and_set_canary_with_init(void) GCC_ATTR_WARN_UNUSED;
+
+/*!
+ * \brief Generates and sets stack canary.
+ * \return
+ *      NVRV_OK                success, canary is set
+ *      NVRV_ERR_NOT_SUPPORTED if SCP driver is not enabled
+ *      Other                  passed-through SCP errors
+ *
+ * This function generates random number using SCP HWRNG, then writes it to
+ * canary.
+ *
+ * \warning There are requirements regarding symbols used by this function when
+ * used.
+ * \warning This function assumes SSP is initialized and running.
+ * \note Errors reported by this function should be considered fatal.
+ */
+error_t ssp_generate_and_set_canary(void) GCC_ATTR_WARN_UNUSED;
+#endif // NVRISCV_FEATURE_SSP_FORCE_SW_CANARY
+
+/*!
+ * \brief Returns current canary value.
+ * \return canary value
+ *
+ * This function shuld be used to retrieve canary value for storage during
+ * partition or context switches (if canary can't be regenerated).
+ */
+uintptr_t ssp_get_canary(void);
+
+/*!
+ * \brief Sets current canary value.
+ * \param[in] canary
+ *
+ * This function should be used to:
+ * - Restore stack canary after partition or context switches
+ * - Configure canary if SCP is not used or not available.
+ */
+void ssp_set_canary(uintptr_t canary);
+
+#if NVRISCV_FEATURE_SSP_ENABLE_FAIL_HOOK
+/*!
+ * \brief Hook called if canary fails.
+ *
+ * \warning This hook shuold be (most likely) implemented in assembly and make
+ * sure stack is not used (as stack pointer is not reliable when this function
+ * is reached).
+ * \warning This hook should not return.
+ */
+extern void ssp_check_fail_hook(void) GCC_ATTR_NORETURN;
+#endif // NVRISCV_FEATURE_SSP_ENABLE_FAIL_HOOK
+
+#endif // LIBNVRISCV_SSP_H
diff --git a/spe-freertos-bsp/fsp/source/include/tke/sections-tke.h b/spe-freertos-bsp/fsp/source/include/tke/sections-tke.h
new file mode 100644
index 0000000..897a82b
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/tke/sections-tke.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef TKE__SECTIONS_TKE_H
+#define TKE__SECTIONS_TKE_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_TKE_DATA           SECTION_BUILDER(tke,                    data)
+#define SECTION_NAME_TKE_RODATA         SECTION_BUILDER(tke,                    rodata)
+#define SECTION_NAME_TKE_TEXT           SECTION_BUILDER(tke,                    text)
+#define SECTION_NAME_TKE_INIT_DATA      SECTION_BUILDER(init.tke,               data)
+#define SECTION_NAME_TKE_INIT_TEXT      SECTION_BUILDER(init.tke,               text)
+
+#define SECTION_STR_TKE_TEXT            STR(SECTION_NAME_TKE_TEXT)
+#define SECTION_STR_TKE_RODATA          STR(SECTION_NAME_TKE_RODATA)
+#define SECTION_STR_TKE_DATA            STR(SECTION_NAME_TKE_DATA)
+#define SECTION_STR_TKE_INIT_TEXT       STR(SECTION_NAME_TKE_INIT_TEXT)
+#define SECTION_STR_TKE_INIT_DATA       STR(SECTION_NAME_TKE_INIT_DATA)
+
+#define SECTION_TKE_TEXT                SECTION(SECTION_STR_TKE_TEXT)
+#define SECTION_TKE_RODATA              SECTION(SECTION_STR_TKE_RODATA)
+#define SECTION_TKE_DATA                SECTION(SECTION_STR_TKE_DATA)
+#define SECTION_TKE_INIT_TEXT           SECTION(SECTION_STR_TKE_INIT_TEXT)
+#define SECTION_TKE_INIT_DATA           SECTION(SECTION_STR_TKE_INIT_DATA)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/tke/tke-tegra-priv.h b/spe-freertos-bsp/fsp/source/include/tke/tke-tegra-priv.h
new file mode 100644
index 0000000..f6cb3fd
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/tke/tke-tegra-priv.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef TKE__TKE_TEGRA_PRIV_H
+#define TKE__TKE_TEGRA_PRIV_H
+#define FSP__TKE__TKE_TEGRA_PRIV_H                      1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <tke/tke-tegra.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__TKE__TKE_TEGRA_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+extern const uint32_t tke_top_base;
+
+#define TEGRA_TKE_NO_IRQ (~UINT32_C(0))
+
+/**
+ * @brief HW details of the TKE Timer.
+ *
+ * It contains the cluster and SOC-specific details of the timer. These details
+ * are present in the cluster specific tke-tegra-ids.c. This structure is used
+ * to communicate with the tke HW via the registers. Note that, no public api
+ * directly uses this structure to interface with a timer unit.
+ *
+ * @base_addr   Base address of TKE Timer
+ * @irq TKE     Timer IRQ number
+ */
+struct tegra_tke_conf
+{
+	uint32_t base_addr;
+    uint32_t irq;
+};
+
+/**
+ * @brief Tegra specific details of the TKE Timer.
+ *
+ * This structure contains the SW and HW details of the timer. The tke unit apis
+ * use this structure to interface with the timer HW and the SW APIs registered
+ * to the timers.
+ *
+ * @conf        Configuration for the tke context
+ * @callback    TKE Timer IRQ callback function.
+ * @data        Opaque data pointer for the timer callback function.
+ */
+struct tegra_tke_id
+{
+    struct tegra_tke_conf const conf;
+    tegra_tke_timer_callback callback;
+    void *data;
+};
+
+#endif  /* TKE__TKE_TEGRA_PRIV_H */
diff --git a/spe-freertos-bsp/fsp/source/include/tke/tke-tegra-regs.h b/spe-freertos-bsp/fsp/source/include/tke/tke-tegra-regs.h
new file mode 100644
index 0000000..e76676f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/tke/tke-tegra-regs.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2015-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef TKE__TKE_TEGRA_REGS_H
+#define TKE__TKE_TEGRA_REGS_H
+#define FSP__TKE__TKE_TEGRA_REGS_H                      1
+
+/* Late FSP headers */
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#define TKE_TIMER_TMRCR_0               0x0
+#define TKE_TIMER_TMRCR_0_PTV           0x1fffffffU
+#define TKE_TIMER_TMRCR_0_PER           BIT(30)
+#define TKE_TIMER_TMRCR_0_EN            BIT(31)
+
+#define TKE_TIMER_TMRSR_0               0x4
+#define TKE_TIMER_TMRSR_0_INTR_CLR      BIT(30)
+#define TKE_TIMER_TMRSR_0_PCV           0x1fffffffU
+
+#define TKE_TIMER_TMRCSSR_0             0x8
+
+#define TSC_MTSCANNR_0                  0x8
+#define TSC_MTSCANDR_0                  0xc
+
+#define TSC_MTSCANNR_0_M0_SHIFT         16
+#define TSC_MTSCANNR_0_R0_SHIFT         0
+#define TSC_MTSCANDR_0_D0_SHIFT         0
+#define TSC_MTSCANNR_0_M0_MASK          (0xfff << TSC_MTSCANNR_0_M0_SHIFT)
+#define TSC_MTSCANNR_0_R0_MASK          (0xfff << TSC_MTSCANNR_0_R0_SHIFT)
+#define TSC_MTSCANDR_0_D0_MASK          (0xfff << TSC_MTSCANDR_0_D0_SHIFT)
+
+#define TSC_BASE_RATE                   32768UL
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif  /* FSP_TKE_TKE_TEGRA_REGS_H */
diff --git a/spe-freertos-bsp/fsp/source/include/tke/tke-tegra.h b/spe-freertos-bsp/fsp/source/include/tke/tke-tegra.h
new file mode 100644
index 0000000..ee407ef
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/tke/tke-tegra.h
@@ -0,0 +1,315 @@
+/*
+ * Copyright (c) 2015-2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef TKE__TKE_TEGRA_H
+#define TKE__TKE_TEGRA_H
+#define FSP__TKE__TKE_TEGRA_H                           1
+
+/* Compiler headers */
+#include <stdbool.h>
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Declaration for tegra_tke_id that allows the APIs to take a pointer to it
+ * without actually defining its contents here.
+ */
+// IWYU pragma: no_forward_declare tegra_tke_id
+struct tegra_tke_id;
+
+/**
+ * @brief ISR Callback function - When an interrupt is raised, this function
+ * will be called by tegra_tke_isr for the timer that was registered. The
+ * callback function is registered during the set-up stage of the timer(function
+ * pointer is passed as an argument to the API).
+ */
+typedef void (*tegra_tke_timer_callback)(void * data);
+
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+/**
+ * @brief Defines for the available clock sources.
+ *
+ * @macro-title Timer Clock Sources
+ *
+ * @TEGRA_TKE_CLK_SRC_USECCNT       1 MHz
+ * @TEGRA_TKE_CLK_SRC_OSCCNT        clk_m
+ * @TEGRA_TKE_CLK_SRC_TSC_BIT0      31.25 MHz
+ * @TEGRA_TKE_CLK_SRC_TSC_BIT12     7.63 KHz
+ */
+#define TEGRA_TKE_CLK_SRC_USECCNT       0U
+#define TEGRA_TKE_CLK_SRC_OSCCNT        1U
+#define TEGRA_TKE_CLK_SRC_TSC_BIT0      2U
+#define TEGRA_TKE_CLK_SRC_TSC_BIT12     3U
+
+/** Maximum divisor for tke timers */
+#define TEGRA_TKE_MAX_TIMER 0x20000000UL
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @brief Initialize TSC and set up TSC to nanosecond conversion.
+ * The FW can use the fixed TSC to nanosecond conversion present in tke-tegra-tsc-fixed.c
+ * to avoid this api call.
+ *
+ * @jama_func_req_id 10797055
+ */
+void tegra_tsc_init(void);
+
+/**
+ * @brief Set up and start a Tegra timer.
+ *
+ * Timer has a PCV counter which starts from one minus the divisor and
+ * counts downwards. The interrupt or timer output is triggered when
+ * the PCV is 0 and a clock source tick occurs.
+ * If the param callback is non-NULL, an interrupt will also be enabled.
+ *
+ * @jama_func_req_id 10797115
+ *
+ * @param[in] id          The context id struct of the timer block.
+ * @param[in] clk_src_sel Clock source used to drive the timer. +
+ *                        Available CLK sources - <<Timer Clock Sources>>
+ * @param[in] periodic    If true, start timer in periodic mode.
+ *                        If false, start timer in one-shot mode.
+ * @param[in] divisor     The period of timer in clock source ticks.
+ *                        Divisor must be TEGRA_TKE_MAX_TIMER or less.
+ * @param[in] callback    The timer expiration callback invoked in irq context.
+ * @param[in] data        The parameter to the callback.
+ */
+void tegra_tke_set_up_timer(struct tegra_tke_id *id, uint32_t clk_src_sel,
+                        bool periodic, uint32_t divisor,
+                        tegra_tke_timer_callback callback, void *data);
+
+/**
+ * @brief Stop a Tegra timer.
+ *
+ * @jama_func_req_id 10797141
+ *
+ * @param[in] id        The context id struct of the timer block.
+ */
+void tegra_tke_stop_timer(const struct tegra_tke_id *id);
+
+/**
+ * @brief Get current period counter value of a Tegra timer.
+ *
+ * @jama_func_req_id 10802167
+ *
+ * @param[in] id        The context id struct of the timer block.
+ *
+ * @retval 32-bit       Period counter value.
+ */
+uint32_t tegra_tke_get_pcv(const struct tegra_tke_id *id);
+
+/**
+ * @brief Enable the timer interrupt.
+ *
+ * @jama_func_req_id 10803499
+ *
+ * @param[in] id        The context id struct of the timer block.
+ */
+void tegra_tke_enable_timer_irq(const struct tegra_tke_id *id);
+
+/**
+ * @brief Disable the timer interrupt.
+ *
+ * @jama_func_req_id 10805710
+ *
+ * @param[in] id        The context id struct of the timer block.
+ */
+void tegra_tke_disable_timer_irq(const struct tegra_tke_id *id);
+
+/**
+ * @brief Clear pending timer interrupt.
+ *
+ * @jama_func_req_id 10805857
+ *
+ * @param[in] id        The context id struct of the timer block.
+ */
+void tegra_tke_clear_timer_irq(const struct tegra_tke_id *id);
+
+/**
+ * @brief Timer interrupt function.
+ *
+ * @jama_func_req_id 10805902
+ *
+ * @param[in] tke_id      The context id struct of the timer block.
+ */
+void tegra_tke_irq(void *tke_id);
+
+/**
+ * @brief Get the 64-bit TSC timer from top_tke_base block.
+ *
+ * @jama_func_req_id 10806040
+ *
+ * @retval 64-bit       Current TSC value
+ */
+uint64_t tegra_tke_get_tsc64(void);
+
+/**
+ * @brief Get the TSC timer from top_tke_base block.
+ *
+ * @jama_func_req_id 10806043
+ *
+ * @param[out] tsc_hi   The upper 32 bits of TSC counter.
+ * @param[out] tsc_lo   The lower 32 bits of TSC counter.
+ */
+void tegra_tke_get_tsc(uint32_t *tsc_hi, uint32_t *tsc_lo);
+
+/**
+ * @brief Get the number of microseconds elapsed since given TCS timestamp.
+ *
+ * @pre Requires invoking tegra_tsc_init() from file "tke-tegra-tsc-var.c" to
+ * calculate tsc-to-nanoseconds conversion ratio dynamically. +
+ * If fixed predefined tsc-to-nanoseconds conversion ratio is used from file
+ * "tke-tegra-tsc-fixed.c", no precondition is required.
+ *
+ * @jama_func_req_id 11266658
+ *
+ * @param[in] prev_tsc_hi   The upper 32 bits of TSC timestamp.
+ * @param[in] prev_tsc_lo   The lower 32 bits of TSC timestamp.
+ *
+ * @retval 64-bit           Elapsed time in microseconds.
+ * @retval 0                pre-condition not met(only in specific cases mentioned).
+ */
+uint64_t tegra_tke_get_elapsed_usec(uint32_t prev_tsc_hi, uint32_t prev_tsc_low);
+
+/**
+ * @brief Get the usec counter value from top_tke_base.
+ *
+ * @jama_func_req_id 10815565
+ *
+ * @retval 32-bit           TKE counter value in microseconds
+ */
+uint32_t tegra_tke_get_usec(void);
+
+/**
+ * @brief Get the osc counter value from top_tke_base.
+ *
+ * @jama_func_req_id 10816111
+ *
+ * @retval 32-bit           OSC counter value.
+ */
+uint32_t tegra_tke_get_osc(void);
+
+/**
+ * @brief Get the low 32 bits of TSC counter value from top_tke_base.
+ *
+ * @jama_func_req_id 10816201
+ *
+ * @retval 32-bit           Lower 32-bits of TSC Counter value.
+ */
+uint32_t tegra_tke_get_tsc32(void);
+
+/**
+ * @brief Get the current TSC counter value as nanoseconds from top_tke_base.
+ *
+ * @pre Requires invoking tegra_tsc_init() from file "tke-tegra-tsc-var.c" to
+ * calculate tsc-to-nanoseconds conversion ratio dynamically. +
+ * If fixed predefined tsc-to-nanoseconds conversion ratio is used from file
+ * "tke-tegra-tsc-fixed.c", no precondition is required.
+ *
+ * @jama_func_req_id 10816420
+ *
+ * @retval 64-bit           Nanoseconds of TSC Counter value.
+ * @retval 0                pre-condition not met(only in specific cases mentioned).
+ */
+uint64_t tegra_tke_get_tsc_ns(void);
+
+/**
+ * @brief Converts a TSC timestamp to nanoseconds.
+ *
+ * @pre Requires invoking tegra_tsc_init() from file "tke-tegra-tsc-var.c" to
+ * calculate tsc-to-nanoseconds conversion ratio dynamically. +
+ * If fixed predefined tsc-to-nanoseconds conversion ratio is used from file
+ * "tke-tegra-tsc-fixed.c", no precondition is required.
+ *
+ * @jama_func_req_id 11223170
+ *
+ * @retval 64-bit           Nanoseconds converted value
+ * @retval 0                pre-condition not met(only in specific cases mentioned).
+ */
+uint64_t tegra_tke_tsc_to_ns(uint64_t tsc);
+
+/**
+ * @brief Converts nanoseconds to a TSC timestamp.
+ *
+ * @pre Requires invoking tegra_tsc_init() from file "tke-tegra-tsc-var.c" to
+ * calculate tsc-to-nanoseconds conversion ratio dynamically. +
+ * If fixed predefined tsc-to-nanoseconds conversion ratio is used from file
+ * "tke-tegra-tsc-fixed.c", no precondition is required.
+ *
+ * @retval 64-bit           Converted TSC timestamp value
+ * @retval 0                pre-condition not met(only in specific cases mentioned).
+ */
+
+uint64_t tegra_tke_ns_to_tsc(uint64_t ns);
+
+/**
+ * @brief Set up SafeRTOS tick timer.
+ *
+ * @jama_func_req_id 10816738
+ *
+ * @param[in] id            The context id struct of the timer block.
+ * @param[in] clk_src       Clock source used to drive the timer. +
+ *                          Available CLK sources <<Timer Clock Sources>>
+ * @param[in] divisor       The period of timer in clock source ticks.
+ */
+void tegra_tke_set_up_tick(struct tegra_tke_id *id, uint32_t clk_src,
+                                uint32_t divisor);
+
+/**
+ * @brief get elapsed microseconds
+ *
+ * @jama_func_req_id 10816807
+ *
+ * @param[in] start         Value of TSC at the start of period
+ *
+ * @retval 64-bit           Elapsed time in microseconds.
+ */
+uint64_t tegra_tke_get_elapsed_usecs64(const uint64_t start);
+
+/**
+ * @brief Convert a microsecond value to RTOS ticks
+ *
+ * @jama_func_req_id 10816846
+ *
+ * @param[in] value         Value in microseconds to be converted to RTOS ticks
+ *
+ * @retval 64-bit           Tick value.
+ */
+uint64_t tegra_tke_convert_usecs_to_ticks(const uint64_t value);
+
+#endif  /* FSP_TKE_TKE_TEGRA_H */
diff --git a/spe-freertos-bsp/fsp/source/include/uart-sbsa/uart-sbsa.h b/spe-freertos-bsp/fsp/source/include/uart-sbsa/uart-sbsa.h
new file mode 100644
index 0000000..274fc6a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/uart-sbsa/uart-sbsa.h
@@ -0,0 +1,328 @@
+/*
+ * Copyright (c) 2021-2022 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SBSA_UART_H
+#define SBSA_UART_H
+#define FSP__UART__SBSA_UART_H        1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <uart/uart.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__UART__UART_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @brief Initialize the already initialized UART instance
+ *
+ * This function initializes and configures the UART context for an instance
+ * that has already been initialized by a 3rdparty or another CPU.
+ *
+ * @param[in] ctrl      UART instance.
+ * @param[in] conf      UART configuration parameters.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      NULL paramters passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ */
+error_t sbsa_uart_3rdparty_init(struct tegra_uart_ctlr *ctlr,
+                                const struct tegra_uart_conf * const conf);
+
+/**
+ * @brief Initialize the UART instance and configure it
+ *
+ * This function initializes and configures the UART context for an instance.
+ *
+ * @param[in] ctrl      UART instance.
+ * @param[in] conf      UART configuration parameters.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      NULL paramters passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ * @retval E_UART_ERR_CONFIG    invalid configuration
+ */
+error_t sbsa_uart_init(struct tegra_uart_ctlr * const ctlr,
+                       const struct tegra_uart_conf * const conf);
+/**
+ * @brief Deinitialize the UART instance and configure it
+ *
+ * This function deinitializes instance.
+ *
+ * @param[in] ctrl      UART instance.
+ * @retval E_SUCCESS                    indicates success
+ * @retval E_UART_NULL_PTR              NULL paramters passed
+ * @E_CAR_CLOCK_OP_NOT_SUPPORTED        Error value returned if the clock does not support the operation.
+ * @E_CAR_FMON_HW_LOGIC                 Error value returned if the FMON register logic algorithm failed.
+
+ *
+ */
+error_t sbsa_uart_deinit(struct tegra_uart_ctlr * const ctlr);
+
+/**
+ * @brief Initialize the UART instance and configure it
+ *
+ * This function initializes and configures the UART context for an instance.
+ *
+ * @pre the function sbsaa_uart_init() has been called
+ *
+ * @param[in] ctrl      UART instance.
+ * @param[in] conf      UART configuration parameters.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      NULL paramters passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ * @retval E_UART_ERR_CONFIG    error in configuring the UART
+ */
+error_t sbsa_uart_init_hw(struct tegra_uart_ctlr * const ctlr,
+                          const struct tegra_uart_conf * const conf);
+
+/**
+ * @brief Flush the UART HW TX FIFO.
+ *
+ * This function flushes the software HW TX FIFO of the UART.
+ *
+ * @pre the function sbsa_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ * @retval E_UART_FLUSH_TIMEOUT flush timed out
+ */
+error_t sbsa_uart_flush_tx_hw_fifo(const struct tegra_uart_ctlr * const ctlr);
+
+/**
+ * @brief Flush the UART SW TX buffer.
+ *
+ * This function flushes the software TX buffer of the UART.
+ *
+ * @pre the function sbsa_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ * @param[in] timeout   timeout to flush the buffer.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ * @retval E_UART_FLUSH_TIMEOUT flush timed out
+ */
+error_t sbsa_uart_flush_tx_fifo(const struct tegra_uart_ctlr * const ctlr);
+
+/**
+ * @brief Write a character to the UART HW TX FIFO.
+ *
+ * This function writes a character to the UART HW TX FIFO.
+ *
+ * @pre the function sbsa_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ * @param[in] c         character to be written.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ */
+error_t sbsa_uart_write_char(const struct tegra_uart_ctlr * const ctlr,
+                             const char c);
+
+/**
+ * @brief Read a character from the UART HW RX FIFO.
+ *
+ * This function reads a character from the UART HW RX FIFO.
+ *
+ * @pre the function sbsa_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ * @param[in] c         pointer to where character read is to be written.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ */
+error_t sbsa_uart_read_char(const struct tegra_uart_ctlr * const ctlr,
+                            char *c);
+
+/**
+ * @brief Read from the UART RX buffer.
+ *
+ * This function reads data from the UART RX buffer.
+ *
+ * @pre the function sbsa_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ * @param[in] buf       pointer to store the data being read.
+ * @param[in] count     byte count of the data to be read.
+ * @param[in] read      byte count read.
+ * @param[in] timeout   timeout to return.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ * @retval E_UART_WRITE_TIMEOUT flush timed out
+ */
+error_t sbsa_uart_read(const struct tegra_uart_ctlr * const ctlr,
+                       char *buf,
+                       uint32_t count,
+                       uint32_t *read,
+                       uint64_t timeout);
+
+/**
+ * @brief Write to the UART TX buffer.
+ *
+ * This function writes the data to the SW TX buffer which in turn gets
+ * pushed to the HW TX FIFO.
+ *
+ * @pre the function sbsa_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ * @param[in] buf       pointer to the data to be written.
+ * @param[in] count     byte count of the data to be written.
+ * @param[in] written   byte count written.
+ * @param[in] timeout   timeout to return.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ * @retval E_UART_WRITE_TIMEOUT flush timed out
+ */
+error_t sbsa_uart_write(const struct tegra_uart_ctlr * const ctlr,
+                        const char *buf,
+                        uint32_t count,
+                        uint32_t *written,
+                        uint64_t timeout);
+
+/**
+ * @brief Write to the UART HW TX fifo.
+ *
+ * This function writes data to the UART HW TX FIFO.
+ *
+ * @pre the function sbsa_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ * @param[in] buf       pointer to the data to be written.
+ * @param[in] count     byte count of the data to be written.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ */
+error_t sbsa_uart_write_now(const struct tegra_uart_ctlr * const ctlr,
+                            const char *buf,
+                            uint32_t count);
+
+/**
+ * @brief Write a string to the UART TX buffer.
+ *
+ * This function writes a string to the SW TX buffer which in turn gets
+ * pushed to the HW TX FIFO.
+ *
+ * @pre the function sbsa_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ * @param[in] buf       pointer to the string.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ */
+error_t sbsa_uart_write_string(const struct tegra_uart_ctlr * const ctlr,
+                               const char *buf);
+
+/**
+ * @brief suspend the UART context.
+ *
+ * This function saves the UART context across power gating the HW.
+ *
+ * @pre the function sbsa_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ */
+error_t sbsa_uart_suspend(struct tegra_uart_ctlr * const ctlr);
+
+/**
+ * @brief resume the UART context.
+ *
+ * This function restores the UART context across power gating the HW.
+ *
+ * @pre the function sbsa_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ */
+error_t sbsa_uart_resume(struct tegra_uart_ctlr * const ctlr);
+
+/**
+ * @brief Indicate if the UART can take a character.
+ *
+ * This function will return an indication of the UART is able to take a
+ * character to transmit.
+ *
+ * @pre the function sbsa_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ *
+ * @retval true         UART can take a character
+ * @retval false        UART cannot take a character
+ */
+bool sbsa_uart_is_tx_ready(const struct tegra_uart_ctlr * const ctlr);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/uart/sections-uart.h b/spe-freertos-bsp/fsp/source/include/uart/sections-uart.h
new file mode 100644
index 0000000..cb05cdd
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/uart/sections-uart.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef UART__SECTIONS_UART_H
+#define UART__SECTIONS_UART_H
+#define FSP__UART__SECTIONS_UART_H                    0
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_UART_BSS           SECTION_BUILDER(uart,                   bss)
+#define SECTION_NAME_UART_DATA          SECTION_BUILDER(uart,                   data)
+#define SECTION_NAME_UART_RODATA        SECTION_BUILDER(uart,                   rodata)
+#define SECTION_NAME_UART_TEXT          SECTION_BUILDER(uart,                   text)
+#define SECTION_NAME_UART_INIT_TEXT     SECTION_BUILDER(init.uart,              text)
+
+#define SECTION_STR_UART_TEXT           STR(SECTION_NAME_UART_TEXT)
+#define SECTION_STR_UART_INIT_TEXT      STR(SECTION_NAME_UART_INIT_TEXT)
+#define SECTION_STR_UART_RODATA         STR(SECTION_NAME_UART_RODATA)
+#define SECTION_STR_UART_DATA           STR(SECTION_NAME_UART_DATA)
+#define SECTION_STR_UART_BSS            STR(SECTION_NAME_UART_BSS)
+
+#define SECTION_UART_TEXT               SECTION(SECTION_STR_UART_TEXT)
+#define SECTION_UART_INIT_TEXT          SECTION(SECTION_STR_UART_INIT_TEXT)
+#define SECTION_UART_RODATA             SECTION(SECTION_STR_UART_RODATA)
+#define SECTION_UART_DATA               SECTION(SECTION_STR_UART_DATA)
+#define SECTION_UART_BSS                SECTION(SECTION_STR_UART_BSS)
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/uart/tegra-uart-priv.h b/spe-freertos-bsp/fsp/source/include/uart/tegra-uart-priv.h
new file mode 100644
index 0000000..924dd65
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/uart/tegra-uart-priv.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef TEGRA_UART_PRIV_H
+#define TEGRA_UART_PRIV_H
+#define FSP__UART__TEGRA_UART_PRIV_H   1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <port/uart-port-priv.h>           // for uart_queue_t , struct uart_hw_handle
+#include <error/common-errors.h>
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @brief UART controller identification structure
+ *
+ * Structure that describes the identification of a UART controller.
+ *
+ * @base_addr   base address of the controller
+ * @irq         controller irq
+ * @hw_handle   port specific hw handle
+ */
+struct tegra_uart_id {
+    const uint32_t                base_addr;
+    const uint32_t                irq;
+    const struct uart_hw_handle   *hw_handle;
+};
+
+/**
+ * @brief UART controller context structure
+ *
+ * Structure that is used by the UART driver to manage the UART controller
+ * during run time.
+ *
+ * @conf         UART controller instance parameters
+ * @tx_queue     UART SW TX FIFO
+ * @rx_queue     UART SW RX FIFO
+ * @tx_sem       tx semaphore for mutual exlusion
+ * @initialized  UART controller initialization status
+ */
+struct tegra_uart_ctlr {
+    const struct tegra_uart_id  id;
+    uart_queue_t                tx_queue;
+    uart_queue_t                rx_queue;
+    bool                        initialized;
+};
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/uart/tegra-uart.h b/spe-freertos-bsp/fsp/source/include/uart/tegra-uart.h
new file mode 100644
index 0000000..4af0be0
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/uart/tegra-uart.h
@@ -0,0 +1,106 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef TEGRA_UART_H
+#define TEGRA_UART_H
+#define FSP__UART__TEGRA_UART_H        1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+typedef uint8_t         tegra_uart_parity_t;
+#define TEGRA_UART_NO_PARITY    ((tegra_uart_parity_t)1U)
+#define TEGRA_UART_ODD_PARITY   ((tegra_uart_parity_t)2U)
+#define TEGRA_UART_EVEN_PARITY  ((tegra_uart_parity_t)3U)
+
+typedef uint8_t         tegra_uart_stop_bits_t;
+#define TEGRA_UART_STOP_BITS_1  ((tegra_uart_stop_bits_t)1U)
+#define TEGRA_UART_STOP_BITS_2  ((tegra_uart_stop_bits_t)2U)
+
+typedef uint8_t         tegra_uart_data_bits_t;
+#define TEGRA_UART_DATA_BITS_5  ((tegra_uart_data_bits_t)1U)
+#define TEGRA_UART_DATA_BITS_6  ((tegra_uart_data_bits_t)2U)
+#define TEGRA_UART_DATA_BITS_7  ((tegra_uart_data_bits_t)3U)
+#define TEGRA_UART_DATA_BITS_8  ((tegra_uart_data_bits_t)4U)
+
+struct tegra_uart_conf {
+    tegra_uart_parity_t         parity;
+    tegra_uart_stop_bits_t      stop_bits;
+    tegra_uart_data_bits_t      data_bits;
+    uint32_t                    baud;
+};
+
+// IWYU pragma: no_forward_declare tegra_uart_ctlr
+struct tegra_uart_ctlr;
+
+error_t tegra_uart_init_hw(struct tegra_uart_ctlr * const ctlr,
+                           const struct tegra_uart_conf * const conf);
+void tegra_uart_flush_tx_hw_fifo(const struct tegra_uart_ctlr * const ctlr);
+void tegra_uart_write_char(const struct tegra_uart_ctlr * const ctlr,
+                           const char c);
+char tegra_uart_read_char(const struct tegra_uart_ctlr * const ctlr);
+void tegra_uart_write(const struct tegra_uart_ctlr * const ctlr,
+                      const char *buf,
+                      uint32_t count);
+void tegra_uart_write_string(const struct tegra_uart_ctlr * const ctlr,
+                             const char *buf);
+bool tegra_uart_is_tx_ready(const struct tegra_uart_ctlr * const ctlr);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/uart/uart-errors.h b/spe-freertos-bsp/fsp/source/include/uart/uart-errors.h
new file mode 100644
index 0000000..c36aaa6
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/uart/uart-errors.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef UART__UART_ERRORS_H
+#define UART__UART_ERRORS_H
+#define FSP__UART__UART_ERRORS_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>     // IWYU pragma: export
+                                // IWYU pragma: no_include "base/module-id.h"
+#include <misc/macros.h>        // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @file uart-errors.h
+ * @brief Error codes that are specific to the UART
+ */
+
+#define E_UART_NULL_PTR                 MODULE_ERROR(UART, 0UL)
+#define E_UART_INVALID_PARAM            MODULE_ERROR(UART, 1UL)
+#define E_UART_ERR_CONFIG               MODULE_ERROR(UART, 2UL)
+#define E_UART_INIT_FAIL                MODULE_ERROR(UART, 3UL)
+#define E_UART_NO_INIT                  MODULE_ERROR(UART, 4UL)
+#define E_UART_FLUSH_TX_FIFO_FAIL       MODULE_ERROR(UART, 5UL)
+#define E_UART_QUEUE_FULL               MODULE_ERROR(UART, 6UL)
+
+#endif  /* UART__UART_ERRORS_H */
diff --git a/spe-freertos-bsp/fsp/source/include/uart/uart-port.h b/spe-freertos-bsp/fsp/source/include/uart/uart-port.h
new file mode 100644
index 0000000..ffed6ba
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/uart/uart-port.h
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SOC_COMMON__UART_DEPENDENCIES_H
+#define SOC_COMMON__UART_DEPENDENCIES_H
+#define FSP__SOC_COMMON__UART_DEPENDENCIES_H             1
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/bitops.h>
+#include <error/common-errors.h>
+
+/* Module-specific FSP headers */
+
+struct tegra_uart_ctlr;
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+
+#define TEGRA_UART_BUF_SIZE          256
+
+error_t uart_port_rx_queue_receive(const struct tegra_uart_ctlr *ctlr,
+                                   char *c,
+                                   uint32_t timeout_left);
+
+error_t uart_port_rx_queue_send_from_isr(const struct tegra_uart_ctlr *ctlr,
+                                         char *c_in,
+                                         bool *isr_yield_flag);
+
+error_t uart_port_tx_queue_receive_from_isr(const struct tegra_uart_ctlr *ctlr,
+                                            char *c_out,
+                                            bool *isr_yield_flag);
+
+error_t uart_port_tx_queue_receive(const struct tegra_uart_ctlr *ctlr,
+                                   char *c,
+                                   uint32_t timeout_left);
+
+error_t uart_port_tx_queue_send(const struct tegra_uart_ctlr *ctlr,
+                                const char *c,
+                                uint32_t timeout_left);
+
+void uart_port_isr_exit(const struct tegra_uart_ctlr *ctlr,
+                        bool isr_yield_flag);
+
+bool uart_port_is_configured(const struct tegra_uart_ctlr *ctlr);
+
+/**
+ * @brief Create the UART TX sw buffer/queue for interrupt driven TX
+ *
+ * @jama_func_req_id xxxxxxxx
+ *
+ * @param[in] ctrl              UART Controller instance
+ * @retval    E_SUCCESS         tx queue creation success.
+ * @retval    E_UART_NULL_PARAM Null ctrl parameter.
+ */
+error_t uart_port_tx_queue_create(struct tegra_uart_ctlr *ctlr);
+
+/**
+ * @brief Create the UART RX sw buffer/queue for interrupt driven RX
+ *
+ * @jama_func_req_id xxxxxxxx
+ *
+ * @param[in] ctrl              UART Controller instance
+ * @retval    E_SUCCESS         rx queue creation success.
+ * @retval    E_UART_NULL_PARAM Null ctrl parameter.
+ */
+error_t uart_port_rx_queue_create(struct tegra_uart_ctlr *ctlr);
+
+/**
+ * @brief Delete the UART TX sw buffer/queue for interrupt driven RX
+ *
+ * @jama_func_req_id xxxxxxxx
+ *
+ * @param[in] ctrl              UART Controller instance
+ * @retval    E_SUCCESS         rx queue creation success.
+ * @retval    E_UART_NULL_PARAM Null ctrl parameter.
+ */
+error_t uart_port_tx_queue_delete(struct tegra_uart_ctlr *ctlr);
+
+/**
+ * @brief Delete the UART RX sw buffer/queue for interrupt driven RX
+ *
+ * @jama_func_req_id xxxxxxxx
+ *
+ * @param[in] ctrl              UART Controller instance
+ * @retval    E_SUCCESS         rx queue creation success.
+ * @retval    E_UART_NULL_PARAM Null ctrl parameter.
+ */
+error_t uart_port_rx_queue_delete(struct tegra_uart_ctlr *ctlr);
+
+/**
+ * @brief Perform the client specific controller init sequence such as pinmux
+ * settings.
+ *
+ * @jama_func_req_id xxxxxxxx
+ *
+ * @param[in] ctrl              UART Controller instance
+ * @retval    E_SUCCESS         init success.
+ * @retval    E_UART_NULL_PARAM Null ctrl parameter.
+ */
+error_t uart_port_init(struct tegra_uart_ctlr *ctlr);
+
+/**
+ * @brief disable the clk for the controller corresponding to the controller ID.
+ *
+ * @jama_func_req_id xxxxxxxx
+ *
+ * @param[in] ctrl              UART Controller instance
+ * @retval    E_SUCCESS         clock disabled.
+ * @retval    E_UART_NULL_PARAM Null ctrl parameter.
+ */
+error_t uart_port_clk_disable(struct tegra_uart_ctlr *ctlr);
+
+/**
+ * @brief Enable the clk for the controller corresponding to the controller ID.
+ *
+ * @jama_func_req_id xxxxxxxx
+ *
+ * @param[in] ctrl              UART Controller instance
+ * @retval    E_SUCCESS         clock enabled.
+ * @retval    E_UART_NULL_PARAM Null ctrl parameter.
+ */
+error_t uart_port_clk_enable(struct tegra_uart_ctlr *ctlr);
+
+/**
+ * @brief Assert, delay and deassert the reset signal.
+ *
+ * @jama_func_req_id xxxxxxxx
+ *
+ * @param[in] ctrl_id         UART Controller ID
+ * @param[in] delay           Delay between assert and deassert
+ * @retval    E_SUCCESS       reset successful.
+ * @retval    E_INVALID_PARAM Invalid ctrl_id.
+ */
+error_t uart_port_clk_reset_pulse(struct tegra_uart_ctlr *ctlr,
+                                  uint32_t delay);
+
+/**
+ * @brief Configure the clock rate for the controller corresponding to the
+ * controller ID passed.
+ *
+ * @jama_func_req_id xxxxxxxx
+ *
+ * @param[in] ctrl_id         UART Controller ID
+ * @retval    E_SUCCESS       Message complete signalled.
+ * @retval    E_INVALID_PARAM Invalid ctrl_id.
+ */
+error_t uart_port_clk_set_rate(struct tegra_uart_ctlr *ctlr, uint32_t rate);
+
+/**
+ * @brief returns the elapsed microseconds from a reference.
+ *
+ * @param[in] start      value of time stamp counter at the start of the period of
+ *                       when the elapsed time is being computed.
+ *
+ * @retval               the number of microseconds that have elapsed between when
+ *                       the start time was taken and this function called.
+ */
+uint64_t uart_port_get_elapsed_usecs(const uint64_t start);
+
+#endif      /* UART_DEPENDENCIES_H */
diff --git a/spe-freertos-bsp/fsp/source/include/uart/uart.h b/spe-freertos-bsp/fsp/source/include/uart/uart.h
new file mode 100644
index 0000000..601313d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/uart/uart.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2019-2021 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef UART_H
+#define UART_H
+#define FSP__UART__UART_H        1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+typedef uint8_t         tegra_uart_parity_t;
+#define TEGRA_UART_NO_PARITY    ((tegra_uart_parity_t)1U)
+#define TEGRA_UART_ODD_PARITY   ((tegra_uart_parity_t)2U)
+#define TEGRA_UART_EVEN_PARITY  ((tegra_uart_parity_t)3U)
+#define SBSA_UART_NO_PARITY     ((tegra_uart_parity_t)1U)
+#define SBSA_UART_ODD_PARITY    ((tegra_uart_parity_t)2U)
+#define SBSA_UART_EVEN_PARITY   ((tegra_uart_parity_t)3U)
+
+typedef uint8_t         tegra_uart_stop_bits_t;
+#define TEGRA_UART_STOP_BITS_1  ((tegra_uart_stop_bits_t)1U)
+#define TEGRA_UART_STOP_BITS_2  ((tegra_uart_stop_bits_t)2U)
+#define SBSA_UART_STOP_BITS_1   ((tegra_uart_stop_bits_t)1U)
+#define SBSA_UART_STOP_BITS_2   ((tegra_uart_stop_bits_t)2U)
+
+typedef uint8_t         tegra_uart_data_bits_t;
+#define TEGRA_UART_DATA_BITS_5  ((tegra_uart_data_bits_t)1U)
+#define TEGRA_UART_DATA_BITS_6  ((tegra_uart_data_bits_t)2U)
+#define TEGRA_UART_DATA_BITS_7  ((tegra_uart_data_bits_t)3U)
+#define TEGRA_UART_DATA_BITS_8  ((tegra_uart_data_bits_t)4U)
+#define SBSA_UART_DATA_BITS_5   ((tegra_uart_data_bits_t)1U)
+#define SBSA_UART_DATA_BITS_6   ((tegra_uart_data_bits_t)2U)
+#define SBSA_UART_DATA_BITS_7   ((tegra_uart_data_bits_t)3U)
+#define SBSA_UART_DATA_BITS_8   ((tegra_uart_data_bits_t)4U)
+
+/**
+ * @brief UART controller configuration structure
+ *
+ * Structure that describes the configuration of a UART controller.
+ *
+ * @parity      parity for the data frame
+ * @stop_bits   number of stop bits for the frame
+ * @data_bits   number of data bits for the data frame
+ * @baud        controller baud rate
+ */
+struct tegra_uart_conf {
+    tegra_uart_parity_t         parity;
+    tegra_uart_stop_bits_t      stop_bits;
+    tegra_uart_data_bits_t      data_bits;
+    uint32_t                    baud;
+};
+
+// IWYU pragma: no_forward_declare tegra_uart_ctlr
+struct tegra_uart_ctlr;
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/utc/sections-utc.h b/spe-freertos-bsp/fsp/source/include/utc/sections-utc.h
new file mode 100644
index 0000000..36ce0e7
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/utc/sections-utc.h
@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef UTC__SECTIONS_UTC_H
+#define UTC__SECTIONS_UTC_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                   SECTION_BUILDER(NAME         TYPE)   */
+#define SECTION_NAME_UTC_DATA        SECTION_BUILDER(utc,         data)
+#define SECTION_NAME_UTC_RODATA      SECTION_BUILDER(utc,         rodata)
+#define SECTION_NAME_UTC_TEXT        SECTION_BUILDER(utc,         text)
+#define SECTION_NAME_UTC_INIT_DATA   SECTION_BUILDER(init.utc,    data)
+#define SECTION_NAME_UTC_INIT_TEXT   SECTION_BUILDER(init.utc,    text)
+
+#define SECTION_STR_UTC_TEXT         STR(SECTION_NAME_UTC_TEXT)
+#define SECTION_STR_UTC_RODATA       STR(SECTION_NAME_UTC_RODATA)
+#define SECTION_STR_UTC_DATA         STR(SECTION_NAME_UTC_DATA)
+#define SECTION_STR_UTC_INIT_TEXT    STR(SECTION_NAME_UTC_INIT_TEXT)
+#define SECTION_STR_UTC_INIT_DATA    STR(SECTION_NAME_UTC_INIT_DATA)
+
+#define SECTION_UTC_TEXT             SECTION(SECTION_STR_UTC_TEXT)
+#define SECTION_UTC_RODATA           SECTION(SECTION_STR_UTC_RODATA)
+#define SECTION_UTC_DATA             SECTION(SECTION_STR_UTC_DATA)
+#define SECTION_UTC_INIT_TEXT        SECTION(SECTION_STR_UTC_INIT_TEXT)
+#define SECTION_UTC_INIT_DATA        SECTION(SECTION_STR_UTC_INIT_DATA)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/utc/utc-errors.h b/spe-freertos-bsp/fsp/source/include/utc/utc-errors.h
new file mode 100644
index 0000000..c485d9a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/utc/utc-errors.h
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef UTC__UTC_ERRORS_H
+#define UTC__UTC_ERRORS_H
+#define FSP__UTC__UTC_ERRORS_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>         // IWYU pragma: export
+#include <misc/macros.h>            // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file utc-errors.h
+ * @brief Error codes that are specific to the UTC
+ */
+
+#define E_UTC_NULL_PTR               MODULE_ERROR(UTC, 0UL)
+#define E_UTC_INVALID_PARAM          MODULE_ERROR(UTC, 1UL)
+#define E_UTC_TIMED_OUT              MODULE_ERROR(UTC, 2UL)
+#define E_UTC_NOT_INITED             MODULE_ERROR(UTC, 3UL)
+#define E_UTC_RX_DISABLED            MODULE_ERROR(UTC, 4UL)
+
+#endif  /* UTC__UTC_ERRORS_H */
diff --git a/spe-freertos-bsp/fsp/source/include/utc/utc-mmio.h b/spe-freertos-bsp/fsp/source/include/utc/utc-mmio.h
new file mode 100644
index 0000000..78cc466
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/utc/utc-mmio.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef UTC__UTC_MMIO_H
+#define UTC__UTC_MMIO_H
+#define FSP__UTC__UTC_MMIO_H                      1
+
+#if defined(UTC_UT_ENABLE)
+/* This file enables the client to mock the readl/writel calls to
+ * unit test the UTC driver.
+ */
+#include <utc-ut-mmio.h>
+#else
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <reg-access/reg-access.h>
+#endif
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/utc/utc-port.h b/spe-freertos-bsp/fsp/source/include/utc/utc-port.h
new file mode 100644
index 0000000..c1a81d4
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/utc/utc-port.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef UTC__UTC_PORT_H
+#define UTC__UTC_PORT_H
+#define FSP__UTC__UTC_PORT_H                      1
+
+#include <stddef.h>
+#include <stdint.h>
+
+/**
+ * @brief Receive a char on the UTC RX sw buffer with timeout.
+ *
+ * @param[in] rx_queue        address of rx_queue
+ * @param[in] c               pointer to where the char is written
+ * @param[in] timeout         timeout to block until
+ *
+ * @retval    E_SUCCESS         rx queue creation success.
+ * @retval    E_UTC_NULL_PARAM  null rx_queue/c parameters.
+ * @retval    other values      port specific error codes.
+ */
+error_t utc_port_rx_queue_receive(uintptr_t rx_queue,
+                                  char *c,
+                                  uint32_t timeout);
+
+/**
+ * @brief Send a char to the UTC RX sw buffer from interrupt context
+ *
+ * @param[in] rx_queue        address of rx_queue
+ * @param[in] c_in            buffer that holds the char
+ * @param[in] isr_yield_flag  pointer to where the context switch state is
+ *                            stored.
+ *
+ * @retval    E_SUCCESS         rx queue creation success.
+ * @retval    E_UTC_NULL_PARAM  null rx_queue/c parameters.
+ * @retval    other values      port specific error codes.
+ */
+error_t utc_port_rx_queue_send_from_isr(uintptr_t rx_queue,
+                                        char *c_in,
+                                        bool *isr_yield_flag);
+
+/**
+ * @brief isr exit callout
+ *
+ * @param[in] isr_yield_flag    flag that saves the context switch state
+ *                              from a previous call to *_send_from_isr()
+ */
+void utc_port_isr_exit(bool isr_yield_flag);
+
+/**
+ * @brief Create the UTC RX sw buffer/queue for interrupt driven RX
+ *
+ * @param[in] rx_queue          address of rx_queue
+
+ * @retval    E_SUCCESS         rx queue creation success.
+ * @retval    other values      port specific error codes.
+ */
+error_t utc_port_rx_queue_create(uintptr_t *rx_queue);
+
+/**
+ * @brief returns the elapsed microseconds from a reference.
+ *
+ * @param[in] start      value of time stamp counter at the start of the period of
+ *                       when the elapsed time is being computed.
+ *
+ * @retval               the number of microseconds that have elapsed between when
+ *                       the start time was taken and this function called.
+ */
+uint64_t utc_port_get_elapsed_usecs(const uint64_t start);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/utc/utc-priv.h b/spe-freertos-bsp/fsp/source/include/utc/utc-priv.h
new file mode 100644
index 0000000..f937209
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/utc/utc-priv.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef UTC__UTC_PRIV_H
+#define UTC__UTC_PRIV_H
+#define FSP__UTC__UTC_PRIV_H                      1
+
+/**
+ * @file utc/utc-priv.h
+ * @brief Structures that are internal to the UTC driver
+ */
+
+/* Compiler headers */
+#include <stdbool.h>
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+#include <address_map_new.h>
+#include <arutc.h>
+
+/* Late FSP headers */
+
+#define UTC_BASE               (NV_ADDRESS_MAP_UTC_32BITBASE)
+#define CLIENT_STRIDE          (UTC_TX_CLIENT_2_ENABLE_0 - UTC_TX_CLIENT_1_ENABLE_0)
+#define CL_BASE(cl_id)         (UTC_BASE + (cl_id - 1U) * CLIENT_STRIDE)
+
+#define DEFINE_UTC_CL(_name, _id, _irq, _en_rx)    \
+        const struct utc_client utc_id_##_name = { \
+            .base = CL_BASE(_id),                  \
+            .id = _id,                             \
+            .irq = _irq,                           \
+            .enable_rx = _en_rx,                   \
+        };
+
+/**
+ * @brief utc client context structure
+ *
+ * Structure that is used by the utc client driver to manage context
+ * during run time.
+ *
+ * @base            base address for the client
+ * @irq             irq number
+ * @id              client id
+ * @enable_rx       flag to indicate whether to enable rx.
+ */
+struct utc_client {
+    const uint32_t  base;
+    const uint32_t  irq;
+    const uint32_t  id;
+    const bool      enable_rx;
+};
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/utc/utc.h b/spe-freertos-bsp/fsp/source/include/utc/utc.h
new file mode 100644
index 0000000..1fcbaf3
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/utc/utc.h
@@ -0,0 +1,239 @@
+/*
+ * Copyright (c) 2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef UTC__UTC_H
+#define UTC__UTC_H
+#define FSP__UTC__UTC_H                      1
+
+/**
+ * @file utc/utc.h
+ * @brief functions for performing utc operations.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>        // for error_t, FSP__ERROR__COMMON...
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Declaration for utc_id that allows the APIs to take a pointer to it
+ * without actually defining its contents here.
+ */
+struct utc_client;
+
+/**
+ * @brief tx flush operation via the UTC.
+ *
+ * @pre utc_client_init() has been called
+ *
+ * @param[in] cl   utc client context
+ *
+ * @retval E_SUCCESS           indicates success
+ * @retval E_UTC_NULL_PTR      null cl paramter passed
+ * @retval E_UTC_NOT_INITED    utc not initialized.
+ */
+error_t utc_tx_flush(const struct utc_client *cl);
+
+/**
+ * @brief output a string via the UTC.
+ *
+ * @pre utc_client_init() has been called
+ *
+ * @param[in] cl   utc client context
+ * @param[in] s    string to output
+ *
+ * @retval E_SUCCESS           indicates success
+ * @retval E_UTC_NULL_PTR      null cl paramter passed
+ * @retval E_UTC_NOT_INITED    utc not initialized.
+ */
+error_t utc_puts(const struct utc_client *cl, const char *s);
+
+/**
+ * @brief output a char via the UTC.
+ *
+ * @pre utc_client_init() has been called
+ *
+ * @param[in] cl   utc context
+ * @param[in] ch   character to output
+ *
+ * @retval E_SUCCESS           indicates success
+ * @retval E_UTC_NULL_PTR      null cl paramter passed
+ * @retval E_UTC_NOT_INITED    utc not initialized.
+ */
+error_t utc_putc(const struct utc_client *cl, const char ch);
+
+/**
+ * @brief check if UTC TX can accept data.
+ *
+ * @pre utc_client_init() has been called
+ *
+ * @param[in] cl      utc context
+ * @param[in] ready   pointer to store the utc tx status
+ *
+ * @retval E_SUCCESS           indicates success
+ * @retval E_UTC_NULL_PTR      null cl paramter passed
+ * @retval E_UTC_NOT_INITED    utc not initialized.
+ */
+error_t utc_is_tx_ready(const struct utc_client *cl, bool *ready);
+
+/**
+ * @brief get TX fifo empty count.
+ *
+ * @pre utc_client_init() has been called
+ *
+ * @param[in] cl      utc context
+ * @param[in] ready   pointer to store the utc tx fifo empty count
+ *
+ * @retval E_SUCCESS           indicates success
+ * @retval E_UTC_NULL_PTR      null cl paramter passed
+ * @retval E_UTC_NOT_INITED    utc not initialized.
+ */
+error_t utc_get_tx_empty_space(const struct utc_client *cl, uint8_t *count);
+
+/**
+ * @brief output data via the UTC.
+ *
+ * This function outputs data to the UTC client TX FIFO.
+ *
+ * @pre the function utc_client_init() has been called
+ *
+ * @param[in] cl          UTC context for the client.
+ * @param[in] buf         buffer that has the data to be written.
+ * @param[in] count       byte count of the data to write.
+ *
+ * @retval E_SUCCESS           indicates success
+ * @retval E_UTC_NULL_PTR      null cl/buf/written paramter passed
+ * @retval E_UTC_NOT_INITED    utc not initialized.
+ */
+error_t utc_write_now(const struct utc_client *cl, const char *buf, uint32_t count);
+
+/**
+ * @brief output data via the UTC.
+ *
+ * This function outputs data to the UTC client TX FIFO.
+ *
+ * @pre the function utc_client_init() has been called
+ *
+ * @param[in] cl          UTC context for the client.
+ * @param[in] buf         buffer that has the data to be written.
+ * @param[in] count       byte count of the data to write.
+ * @param[in] written     byte count written.
+ * @param[in] timeout_us  timeout in us to return on expiry.
+ *
+ * @retval E_SUCCESS           indicates success
+ * @retval E_UTC_NULL_PTR      null cl/buf/written paramter passed
+ * @retval E_UTC_NOT_INITED    utc not initialized.
+ * @retval E_UTC_TIMED_OUT     utc timed out
+ */
+error_t utc_write(const struct utc_client *cl, const char *buf,
+                  uint32_t count, uint32_t *written, uint64_t timeout_us);
+
+/**
+ * @brief receive a char via the UTC.
+ *
+ * @pre utc_client_init() has been called
+ *
+ * @param[in] cl   utc context
+ * @param[in] ch   pointer to where the char is stored
+ *
+ * @retval E_SUCCESS           indicates success
+ * @retval E_UTC_NULL_PTR      null cl/ch paramter passed
+ * @retval E_UTC_NOT_INITED    utc not initialized.
+ * @retval E_UTC_RX_DISABLED   utc rx disabled
+ */
+error_t utc_getc(const struct utc_client *cl, char *ch);
+
+/**
+ * @brief Read from the UTC RX buffer.
+ *
+ * This function reads data from the UTC client RX FIFO.
+ *
+ * @pre the function utc_client_init() has been called
+ *
+ * @param[in] cl          UTC context for the client.
+ * @param[in] buf         pointer to store the data being read.
+ * @param[in] count       byte count of the data to be read.
+ * @param[in] read        byte count read.
+ * @param[in] timeout_us  timeout in us to return on expiry.
+ *
+ * @retval E_SUCCESS           indicates success
+ * @retval E_UTC_NULL_PTR      null cl/buf/read paramter passed
+ * @retval E_UTC_INVALID_PARAM invalid parameter passed
+ * @retval E_UTC_NOT_INITED    utc not initialized.
+ * @retval E_UTC_TIMED_OUT     utc timed out
+ * @retval E_UTC_RX_DISABLED   utc rx disabled
+ */
+error_t utc_read(const struct utc_client *cl, char *buf, uint32_t count,
+                 uint32_t *read, uint64_t timeout_us);
+
+/**
+ * @brief Initialization of the UTC context for the client.
+ *
+ * This API resets the client FIFOs, performs a sanity check of the global
+ * initialization performed by some micro-boot stage and enables TX/RX.
+ *
+ * @pre Some micro-boot stage has performed the UTC common configuration.
+ *
+ * @param[in] cl                utc context for this client
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UTC_NULL_PTR       null cl paramter passed
+ * @retval E_UTC_NOT_INITED     utc not enabled by BL.
+ * @retval E_UTC_INVALID_PARAM  utc client invalid id.
+ */
+error_t utc_client_init(const struct utc_client *cl);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/vic/sections-vic.h b/spe-freertos-bsp/fsp/source/include/vic/sections-vic.h
new file mode 100644
index 0000000..b31742d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/vic/sections-vic.h
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef VIC__SECTIONS_VIC_H
+#define VIC__SECTIONS_VIC_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_VIC_DATA           SECTION_BUILDER(vic,                    data)
+#define SECTION_NAME_VIC_TEXT           SECTION_BUILDER(vic,                    text)
+#define SECTION_NAME_VIC_ERROR_DATA     SECTION_BUILDER(error.vic,              data)
+#define SECTION_NAME_VIC_ERROR_TEXT     SECTION_BUILDER(error.vic,              text)
+#define SECTION_NAME_VIC_INIT_DATA      SECTION_BUILDER(init.vic,               data)
+#define SECTION_NAME_VIC_INIT_TEXT      SECTION_BUILDER(init.vic,               text)
+#define SECTION_NAME_VIC_ISRMAP_DATA    SECTION_BUILDER(isrmap.vic,             data)
+
+#define SECTION_STR_VIC_TEXT            STR(SECTION_NAME_VIC_TEXT)
+#define SECTION_STR_VIC_DATA            STR(SECTION_NAME_VIC_DATA)
+#define SECTION_STR_VIC_INIT_TEXT       STR(SECTION_NAME_VIC_INIT_TEXT)
+#define SECTION_STR_VIC_INIT_DATA       STR(SECTION_NAME_VIC_INIT_DATA)
+#define SECTION_STR_VIC_ERROR_TEXT      STR(SECTION_NAME_VIC_ERROR_TEXT)
+#define SECTION_STR_VIC_ERROR_DATA      STR(SECTION_NAME_VIC_ERROR_DATA)
+#define SECTION_STR_VIC_ISRMAP_DATA     STR(SECTION_NAME_VIC_ISRMAP_DATA)
+
+#define SECTION_VIC_TEXT                SECTION(SECTION_STR_VIC_TEXT)
+#define SECTION_VIC_DATA                SECTION(SECTION_STR_VIC_DATA)
+#define SECTION_VIC_INIT_TEXT           SECTION(SECTION_STR_VIC_INIT_TEXT)
+#define SECTION_VIC_INIT_DATA           SECTION(SECTION_STR_VIC_INIT_DATA)
+#define SECTION_VIC_ERROR_TEXT          SECTION(SECTION_STR_VIC_ERROR_TEXT)
+#define SECTION_VIC_ERROR_DATA          SECTION(SECTION_STR_VIC_ERROR_DATA)
+#define SECTION_VIC_ISRMAP_DATA         SECTION(SECTION_STR_VIC_ISRMAP_DATA)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/vic/tegra-vic.h b/spe-freertos-bsp/fsp/source/include/vic/tegra-vic.h
new file mode 100644
index 0000000..4205dfc
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/vic/tegra-vic.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (c) 2018-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef VIC__TEGRA_VIC_H
+#define VIC__TEGRA_VIC_H
+#define FSP__VIC__TEGRA_VIC_H                           1
+
+/* Compiler headers */
+#ifndef __ASSEMBLER__
+#include <stdint.h>                                     // for uint32_t
+#endif
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                             // for CT_ASSERT
+#include <soc-common/hw-const.h>                        // Must appear before any hwinc files
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/linker-symbols.h>                        // for IMAGE_SYM_BASE, IMAGE_SYM_LIMIT
+#include <misc/macros.h>                                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <processor/irqs-hw.h>                          // for MAX_VIC_CONTROLLER
+#ifndef __ASSEMBLER__
+#include <error/common-errors.h>                        // for uint32_t
+#endif
+
+/* Module-specific FSP headers */
+#include <cpu/arm-vic.h>                                // for ARM_VIC_IRQ_COUNT, FSP__ARM__COMMON...
+#include <vic/vic-ld.h>                                 // for FSP__VIC__VIC_LD_H, Image$$VIC_ISR_...
+#include <vic/sections-vic.h>                           // Immune from CT_ASSERT protection
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__LINKER_SYMBOLS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CPU__ARM_VIC_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__VIC__VIC_LD_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+#endif
+
+/*
+ * Tegra interrupt vector
+ *  * An interrupt vector is composed of:
+ * Bits            Description
+ * 31-5            VIC number
+ * 4-0             VIC IRQ
+ *
+ * NOTE: The following macros do not use the bit operations as they can be
+ * used in assembler. HW constant macros of the type "MK_*X*_CONST" allow the
+ * headers to be used by the assembler and the linker scripts.
+ * MK_SHIFT_CONST - Define a constant indicating shift amount.
+ * MK_U32_CONST   - Define a u32 constant
+ * MK_MASK_CONT   - Define a constant indicating bit-mask
+ */
+/**  Bitwise shift amount for VIC instance number in the vector */
+#define VIC_ID_SHIFT                    MK_SHIFT_CONST(5)
+/** Bit-mask for interrupt number in the VIC vector */
+#define VIC_IRQ_MASK                    (ARM_VIC_IRQ_COUNT - MK_U32_CONST(1))
+/** Bit-mask for VIC instance ID */
+#define VIC_INSTANCE_MASK               MK_MASK_CONST(0x7FFFFFF)
+/** Maximum valid value of VIC instance ID */
+#define MAX_VIC_INSTANCE_ID             ((uint32_t)(MAX_VIC_CONTROLLER) - 1U)
+/** Maximum valid value of interrupt vector */
+#define MAX_VIC_INTERRUPT_VECTOR        ((MAX_VIC_INSTANCE_ID << VIC_ID_SHIFT) | VIC_IRQ_MASK)
+/** Returns tegra interrupt vector based on VIC instance and IRQ numbers given as an input */
+#define TEGRA_INTERRUPT(_c_, _v_)       (((((_c_)) & VIC_INSTANCE_MASK) << VIC_ID_SHIFT) | ((_v_) & VIC_IRQ_MASK))
+/** Returns VIC instance number from the tegra interrupt vector. */
+#define TEGRA_INTERRUPT_TO_VIC(_x_)     (((_x_) >> VIC_ID_SHIFT) & VIC_INSTANCE_MASK)
+/** Returns IRQ number for the VIC instance from the tegra interrupt vector */
+#define TEGRA_INTERRUPT_TO_IRQ(_x_)     ((_x_) & VIC_IRQ_MASK)
+
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx")
+#endif
+#ifndef __ASSEMBLER__
+
+/**
+ * Converts (struct vic_isr_map_s *) to uint32_t
+ *
+ * @param[in] addr void pointer which will be converted to uintptr_t
+ * @retval value uintptr_t value of void pointer.
+ */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_19_2, "Approval: Bug 200543136, DR: SWE-FSP-033-SWSADR.docx")
+#endif
+static inline uint32_t vic_isr_ptr_to_uint32_t(struct vic_isr_map_s *addr)
+{
+    union type_cast_vic {
+        struct vic_isr_map_s *addr;
+        uint32_t addr_value;
+    };
+    union type_cast_vic t;
+
+    t.addr = addr;
+
+    return t.addr_value;
+}
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_19_2, "Approval: Bug 200543136, DR: SWE-FSP-033-SWSADR.docx")
+#endif
+
+/**
+ * @brief Structure exposed to save interrupt context
+ */
+typedef struct arm_vic_context irq_context;
+
+/**
+ * @brief Returns number of ISR map entries created by the clients
+ */
+static inline uint32_t num_isr_map_entries(void)
+{
+    uint32_t num_isr;
+
+    num_isr =  vic_isr_ptr_to_uint32_t(&IMAGE_SYM_LIMIT(VIC_ISR_MAP));
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    num_isr -= vic_isr_ptr_to_uint32_t(&IMAGE_SYM_BASE(VIC_ISR_MAP));
+
+    return num_isr / sizeof(struct vic_isr_map_s);
+}
+
+void tegra_vic_init(void)                       SECTION_VIC_INIT_TEXT;
+
+/**
+ * @brief Initialize the VIC controller.
+ *
+ * This function will initialize the various VICs and setup the vector
+ * addresses for each vector.
+ *
+ * No input argument.
+ *
+ * @pre Client driver has mapped ISR for respective device
+ * interrupts using isr_map_entry.
+ *
+ *
+ * @retval E_SUCCESS                   For success
+ * @retval E_VIC_INVALID_VECTOR        ISR map entry with invalid vector ID
+ * @retval E_VIC_NULL_IRQ_HANDLER      ISR map entry with NULL interrupt handler
+ */
+error_t tegra_safe_vic_init(void)               SECTION_VIC_INIT_TEXT;
+
+/**
+ *
+ * @brief This function is the interrupt handler that gets called for any interrupt
+ * vector that does not otherwise have a registered interrupt handler.
+ *
+ * @param[in] vector  Interrupt vector number (VIC and IRQ are encoded in the
+ *                    vector number) that generated the unrecognized interrupt.
+ *
+ * This function is not expected to return.
+ */
+void bad_irq(const uint32_t vector)           SECTION_VIC_ERROR_TEXT;
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
+#endif
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/vic/vic-abort-codes.h b/spe-freertos-bsp/fsp/source/include/vic/vic-abort-codes.h
new file mode 100644
index 0000000..45fa49a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/vic/vic-abort-codes.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef VIC__VIC_ABORT_CODES_H
+#define VIC__VIC_ABORT_CODES_H
+#define FSP__VIC__VIC_ABORT_CODES_H                     1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+#include <base/module-id.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "base/module-id.h"
+
+/* Late FSP headers */
+#include <debug/abort-codes.h>
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ABORT_CODES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
+/**
+ * @brief Defines abort code for unrecognized VIC interrupt
+ */
+#define ABORT_BAD_IRQ           ABORT_CODE(VIC, 0UL)
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/vic/vic-asm-giza.h b/spe-freertos-bsp/fsp/source/include/vic/vic-asm-giza.h
new file mode 100644
index 0000000..fa6b85f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/vic/vic-asm-giza.h
@@ -0,0 +1,145 @@
+/*
+ * Copyright (c) 2022 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* NOTE: This is a dummy header file to parse the doxygen comments for APIs
+ * implemented using assembly language. The file defines C function prototype
+ * corresponding to the ASM APIs and captures doxygen comments accordingly.
+ * This function won't be used for any software development and shall not be
+ * delivered to the customer
+ */
+
+/**
+ * @brief bad_irq_handler macro
+ *
+ * Defines the handler for an interrupt vector for which there is
+ * no other handler.  Calls the function:
+ *      void bad_irq(uint32_t vector)
+ *
+ * ASM MACRO: .macro  bad_irq_handler label, vector 
+ *
+ * @param[in] label  Label to be applied to the code
+ * @param[in] vector Tegra interrupt vector. It is a number that encodes both
+ *                   VIC instance ID and local IRQ number
+ *                   [0 - MAX_VIC_INTERRUPT_VECTOR]
+ */
+bad_irq_handler(label, vector);
+
+/**
+ * @brief Interrupt handler with address as input
+ *
+ * Interrupt handlers that take an address as a parameter to be passed
+ * to a C function with the prototype:
+ *     void func(void *addr)
+ *
+ * ASM MACRO: .macro  isr_addr         label, addr, func, vector 
+ *
+ * @param[in] label  Label to be applied to the code
+ * @param[in] addr   Address to be passed to the function
+ * @param[in] func   Function to be called
+ * @param[in] vector Tegra interrupt vector. It is a number that encodes both
+ *                   VIC instance ID and local IRQ number
+ *                   [0 - MAX_VIC_INTERRUPT_VECTOR]
+ *
+ */
+isr_addr(label, addr, func, vector);
+
+/**
+ * @brief Interrupt handler with value as an input to the function
+ * Interrupt handlers that take a value as a parameter to be passed
+ * to a C function with the prototype:
+ *     void func(uint32_t value)
+ *
+ * ASM MACRO : .macro  isr_value       label, value, func, vector  
+ *
+ * @param[in] label  Label to be applied to the code
+ * @param[in] value  16-bit constant value to be passed to the function
+ * @param[in] func   Function to be called
+ * @param[in] vector Tegra interrupt vector. It is a number that encodes both
+ *                   VIC instance ID and local IRQ number
+ *                   [0 - MAX_VIC_INTERRUPT_VECTOR]
+ *
+ */
+isr_value(label, value, func, vector);
+
+/**
+ * @brief ACK_VIC0_IRQ macro
+ *
+ * Acknowledges an interrupt originating from VIC0.
+ *
+ * ASM MACRO: .macro  ACK_VIC0_IRQ    label 
+ *
+ * Usage:
+ *      ACK_VIC0_IRQ label
+ *
+ * Registers Modified:
+ *      R0
+ *
+ */
+ACK_VIC0_IRQ(label);
+
+/**
+ * @brief ACK_VIC1_IRQ macro
+ *
+ * Acknowledges an interrupt originating from VIC1.
+ *
+ * ASM MACRO: .macro  ACK_VIC1_IRQ    label 
+ *
+ * Usage:
+ *      ACK_VIC1_IRQ label
+ *
+ * Registers Modified:
+ *      R0
+ *      R1
+ *
+ * @param[in] label Label to be applied to the code
+ */
+ACK_VIC1_IRQ(lable);
+
+/**
+ * @brief isr_map_entry macro
+ *
+ * Creates an ISR map entry
+ *
+ * ASM MACRO: .macro  isr_map_entry   vector, isr_fn 
+ *
+ * Usage:
+ *      isr_map_entry vector, isr_fn
+ *
+ * @param[in] vector Tegra interrupt vector. It is a number that encodes both
+ *                   VIC instance ID and local IRQ number
+ *                   [0 - MAX_VIC_INTERRUPT_VECTOR]
+ * @param[in] isr_fn Assembler ISR function that will be dispatched when an
+ *                   interrupt occurs
+ *
+ * @pre
+ * - Interrupts set using static configuration
+ *
+ */
+isr_map_entry(vector, isr_fn);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/vic/vic-asm.h b/spe-freertos-bsp/fsp/source/include/vic/vic-asm.h
new file mode 100644
index 0000000..5bae155
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/vic/vic-asm.h
@@ -0,0 +1,309 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2023 NVIDIA CORPORATION &
+ * AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: LicenseRef-NvidiaProprietary
+ *
+ * NVIDIA CORPORATION, its affiliates and licensors retain all intellectual
+ * property and proprietary rights in and to this material, related
+ * documentation and any modifications thereto. Any use, reproduction,
+ * disclosure or distribution of this material and related documentation
+ * without an express license agreement from NVIDIA CORPORATION or
+ * its affiliates is strictly prohibited.
+ */
+
+#ifndef VIC__VIC_ASM_H
+#define VIC__VIC_ASM_H
+#define FSP__VIC__VIC_ASM_H                             1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <ospl/rtos-port-asm.h>
+#include <hw-config/vic-irqs.h>
+
+/* Module-specific FSP headers */
+#include <vic/tegra-vic.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__VIC__TEGRA_VIC_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSPL__RTOS_PORT_ASM_H, "Header file missing or invalid.")
+
+#ifdef __ASSEMBLER__
+/*
+ * Macros used for generating code for interrupt handlers.
+ */
+
+/*
+ * External references used by these macros
+ */
+.extern bad_irq
+.type bad_irq, STT_FUNC
+
+.extern vic0_isr_end
+.type vic0_isr_end, STT_FUNC
+
+.extern vic1_isr_end
+.type vic1_isr_end, STT_FUNC
+
+#if defined(MAX_VIC_CONTROLLER) && (MAX_VIC_CONTROLLER == 4)
+.extern vic2_isr_end
+.type vic2_isr_end, STT_FUNC
+
+.extern vic3_isr_end
+.type vic3_isr_end, STT_FUNC
+#endif
+
+.extern vic_base_addr
+.type vic_base_addr, STT_OBJECT
+
+/**
+ * @brief bad_irq_handler macro
+ *
+ * Defines the handler for an interrupt vector for which there is
+ * no other handler.  Calls the function:
+ *      void bad_irq(uint32_t vector)
+ *
+ * @param[in] label  Label to be applied to the code
+ * @param[in] vector Tegra interrupt vector. It is a number that encodes both
+ *                   the VIC instance ID and local IRQ number
+ *                    [0 - MAX_VIC_INTERRUPT_VECTOR]
+ *
+ */
+.macro  bad_irq_handler label, vector
+        .global         \label
+        .balign         4
+\label :
+        rtosIRQ_ENTRY
+        MOV     R0, #\vector
+        BLX     bad_irq
+        B       .               // not reached
+.endm
+
+/**
+ * @brief Interrupt handler with address as input
+ *
+ * Interrupt handlers that take an address as a parameter to be passed
+ * to a C function with the prototype:
+ *     void func(void *addr)
+ *
+ * @param[in] label  Label to be applied to the code
+ * @param[in] addr   Address to be passed to the function
+ * @param[in] func   Function to be called
+ * @param[in] vector Tegra interrupt vector. It is a number that encodes both
+ *                   the VIC instance ID and local IRQ number
+ *                    [0 - MAX_VIC_INTERRUPT_VECTOR]
+ */
+.macro  isr_addr         label, addr, func, vector
+        .global         \label
+        .balign         4
+\label :
+        rtosIRQ_ENTRY
+        LDR     R0, =\addr
+        BLX     \func
+#if defined(MAX_VIC_CONTROLLER) && (MAX_VIC_CONTROLLER == 4)
+.if TEGRA_INTERRUPT_TO_VIC(\vector) == 3
+        B       vic3_isr_end
+.elseif TEGRA_INTERRUPT_TO_VIC(\vector) == 2
+        B       vic2_isr_end
+.elseif TEGRA_INTERRUPT_TO_VIC(\vector) == 1
+        B       vic1_isr_end
+.else
+        B       vic0_isr_end
+.endif
+#else
+.if TEGRA_INTERRUPT_TO_VIC(\vector) == 1
+        B       vic1_isr_end
+.else
+        B       vic0_isr_end
+.endif
+#endif
+.endm
+
+/**
+ * @brief Interrupt handler with value as an input to the function
+ * Interrupt handlers that take a value as a parameter to be passed
+ * to a C function with the prototype:
+ *     void func(uint32_t value)
+ *
+ * @param[in] label  Label to be applied to the code
+ * @param[in] value  16-bit constant value to be passed to the function
+ * @param[in] func   Function to be called
+ * @param[in] vector Tegra interrupt vector. It is a number that encodes both
+ *                   the VIC instance ID and local IRQ number
+ *                    [0 - MAX_VIC_INTERRUPT_VECTOR]
+ */
+.macro  isr_value       label, value, func, vector
+        .global         \label
+        .balign         4
+\label :
+        rtosIRQ_ENTRY
+        MOVW    R0, #\value
+        MOVT    R0, #0
+        BLX     \func
+#if defined(MAX_VIC_CONTROLLER) && (MAX_VIC_CONTROLLER == 4)
+.if TEGRA_INTERRUPT_TO_VIC(\vector) == 3
+        B       vic3_isr_end
+.elseif TEGRA_INTERRUPT_TO_VIC(\vector) == 2
+        B       vic2_isr_end
+.elseif TEGRA_INTERRUPT_TO_VIC(\vector) == 1
+        B       vic1_isr_end
+.else
+        B       vic0_isr_end
+.endif
+#else
+.if TEGRA_INTERRUPT_TO_VIC(\vector) == 1
+        B       vic1_isr_end
+.else
+        B       vic0_isr_end
+.endif
+#endif
+.endm
+
+/**
+ * @brief ACK_VIC0_IRQ macro
+ *
+ * Acknowledges an interrupt originating from VIC0.
+ *
+ * Usage:
+ *      ACK_VIC0_IRQ label
+ *
+ * Registers Modified:
+ *      R0
+ *
+ * @param[in] label Label to be applied to the code
+ */
+.macro  ACK_VIC0_IRQ    label
+        .global         \label
+        .balign         4
+\label :
+        LDR     R0, =vic_base_addr
+        LDR     R0, [R0]
+        STR     R0, [R0, #APS_VIC_VICADDRESS_0]
+.endm
+
+/**
+ * @brief ACK_VIC1_IRQ macro
+ *
+ * Acknowledges an interrupt originating from VIC1.
+ *
+ * Usage:
+ *      ACK_VIC1_IRQ label
+ *
+ * Registers Modified:
+ *      R0
+ *      R1
+ *
+ * @param[in] label Label to be applied to the code
+ */
+.macro  ACK_VIC1_IRQ    label
+        .global         \label
+        .balign         4
+\label :
+        LDR     R0, =vic_base_addr
+        LDR     R1, [R0, #4]
+        STR     R0, [R1, #APS_VIC_VICADDRESS_0]
+        LDR     R1, [R0]
+        STR     R0, [R1, #APS_VIC_VICADDRESS_0]
+.endm
+
+
+#if defined(MAX_VIC_CONTROLLER) && (MAX_VIC_CONTROLLER == 4)
+/**
+ * @brief ACK_VIC2_IRQ macro
+ *
+ * Acknowledges an interrupt originating from VIC1.
+ *
+ * Usage:
+ *      ACK_VIC2_IRQ label
+ *
+ * Registers Modified:
+ *      R0
+ *      R1
+ *
+ * @param[in] label Label to be applied to the code
+ */
+.macro  ACK_VIC2_IRQ    label
+        .global         \label
+        .balign         4
+\label :
+        LDR     R0, =vic_base_addr
+        LDR     R1, [R0, #8]
+        STR     R0, [R1, #APS_VIC_VICADDRESS_0]
+        LDR     R1, [R0, #4]
+        STR     R0, [R1, #APS_VIC_VICADDRESS_0]
+        LDR     R1, [R0]
+        STR     R0, [R1, #APS_VIC_VICADDRESS_0]
+.endm
+
+/**
+ * @brief ACK_VIC3_IRQ macro
+ *
+ * Acknowledges an interrupt originating from VIC1.
+ *
+ * Usage:
+ *      ACK_VIC3_IRQ label
+ *
+ * Registers Modified:
+ *      R0
+ *      R1
+ *
+ * @param[in] label Label to be applied to the code
+ */
+.macro  ACK_VIC3_IRQ    label
+        .global         \label
+        .balign         4
+\label :
+        LDR     R0, =vic_base_addr
+        LDR     R1, [R0, #12]
+        STR     R0, [R1, #APS_VIC_VICADDRESS_0]
+        LDR     R1, [R0, #8]
+        STR     R0, [R1, #APS_VIC_VICADDRESS_0]
+        LDR     R1, [R0, #4]
+        STR     R0, [R1, #APS_VIC_VICADDRESS_0]
+        LDR     R1, [R0]
+        STR     R0, [R1, #APS_VIC_VICADDRESS_0]
+.endm
+
+#endif
+
+/**
+ * @brief isr_map_entry macro
+ *
+ * Creates an ISR map entry
+ *
+ * Usage:
+ *      isr_map_entry vector, isr_fn
+ *
+ * @param[in] vector Tegra interrupt vector. It is a number that encodes both
+ *                   the VIC instance ID and local IRQ number
+ *                    [0 - MAX_VIC_INTERRUPT_VECTOR]
+ * @param[in] isr_fn Assembler ISR function that will be dispatched when an
+ *                   interrupt occurs
+ *
+ * @pre
+ * - Interrupts set using static configuration
+ *
+ */
+.macro  isr_map_entry   vector, isr_fn
+        .balign         8
+        .long   \vector
+        .long   \isr_fn
+.endm
+
+#endif // __ASSEMBLER__
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/vic/vic-errors.h b/spe-freertos-bsp/fsp/source/include/vic/vic-errors.h
new file mode 100644
index 0000000..4c73126
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/vic/vic-errors.h
@@ -0,0 +1,88 @@
+/*
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef VIC__VIC_ERRORS_H
+#define VIC__VIC_ERRORS_H
+#define FSP__VIC__VIC_ERRORS_H                          1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>             // IWYU pragma: export
+                                        // IWYU pragma: no_include "base/module-id.h"
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+#endif
+/*
+ * @defgroup VIC_ERRORS VIC error codes
+ * @brief Macro definitions for errors from IRQ and VIC layer
+ * @}
+ */
+/** Error value returned for invalid vector ID */
+#define E_VIC_INVALID_VECTOR               MODULE_ERROR(VIC,1UL)
+/** Error value returned for invalid VIC instance ID */
+#define E_VIC_INVALID_VIC_INSTANCE         MODULE_ERROR(VIC,2UL)
+/** Error value returned for NULL input parameter */
+#define E_VIC_NULL_INPUT_PARAMETER         MODULE_ERROR(VIC,3UL)
+/** Error value returned for invalid input parameter */
+#define E_VIC_INVALID_INPUT_PARAMETER      MODULE_ERROR(VIC,4UL)
+/** Error value returned for NULL ISR handler for an interrupt source */
+#define E_VIC_NULL_IRQ_HANDLER             MODULE_ERROR(VIC,5UL)
+/** @{ */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/vic/vic-ld.h b/spe-freertos-bsp/fsp/source/include/vic/vic-ld.h
new file mode 100644
index 0000000..87d0353
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/vic/vic-ld.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef VIC__VIC_LD_H
+#define VIC__VIC_LD_H
+#define FSP__VIC__VIC_LD_H                              1
+
+/* Compiler headers */
+#ifndef __ASSEMBLER__
+#include <stdint.h>               // for uint32_t
+#endif
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>       // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/linker-symbols.h>  // for FSP__MISC__LINKER_SYMBOLS_H, IMAGE_...
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>    // for FSP__PROCESSOR__IRQS_HW_H, MAX_VIC_...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+#ifndef DOXYGEN_SHOULD_SKIP_THIS
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__LINKER_SYMBOLS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
+
+#ifndef __ASSEMBLER__
+
+
+/** VIC interrupt vector */
+typedef uint32_t        irq_vect_t;
+
+/**
+ * @struct vic_isr_map_s
+ * @brief  VIC layer ISR map structure.
+ * @{
+ */
+struct vic_isr_map_s
+{
+    /** Tegra interrupt vector [0 - MAX_VIC_INTERRUPT_VECTOR] */
+    irq_vect_t          vector;
+    /** Pointer to the ISR for mapped tegra interrupt vector. Must not be NULL */
+    void                (*isr_handler)(void);
+};
+/** @} */
+extern struct vic_isr_map_s    IMAGE_SYM_BASE(VIC_ISR_MAP);
+extern struct vic_isr_map_s    IMAGE_SYM_LIMIT(VIC_ISR_MAP);
+const extern uint32_t vic_base_addr[MAX_VIC_CONTROLLER];
+
+#endif // __ASSEMBLER__
+#endif // VIC__VIC_LD_H
diff --git a/spe-freertos-bsp/fsp/source/include/watchdog/sections-watchdog.h b/spe-freertos-bsp/fsp/source/include/watchdog/sections-watchdog.h
new file mode 100644
index 0000000..99894ac
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/watchdog/sections-watchdog.h
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef WATCHDOG__SECTIONS_WATCHDOG_H
+#define WATCHDOG__SECTIONS_WATCHDOG_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                              SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_WATCHDOG_DATA              SECTION_BUILDER(watchdog,               data)
+#define SECTION_NAME_WATCHDOG_TEXT              SECTION_BUILDER(watchdog,               text)
+#define SECTION_NAME_WATCHDOG_ERROR_DATA        SECTION_BUILDER(error.watchdog,         data)
+#define SECTION_NAME_WATCHDOG_ERROR_TEXT        SECTION_BUILDER(error.watchdog,         text)
+#define SECTION_NAME_WATCHDOG_INIT_DATA         SECTION_BUILDER(init.watchdog,          data)
+#define SECTION_NAME_WATCHDOG_INIT_RODATA       SECTION_BUILDER(init.watchdog,          rodata)
+#define SECTION_NAME_WATCHDOG_INIT_TEXT         SECTION_BUILDER(init.watchdog,          text)
+#define SECTION_NAME_WATCHDOG_PRIV_STACKS       SECTION_BUILDER(stacks.priv.watchdog,   bss)
+
+#define SECTION_STR_WATCHDOG_TEXT               STR(SECTION_NAME_WATCHDOG_TEXT)
+#define SECTION_STR_WATCHDOG_DATA               STR(SECTION_NAME_WATCHDOG_DATA)
+#define SECTION_STR_WATCHDOG_INIT_TEXT          STR(SECTION_NAME_WATCHDOG_INIT_TEXT)
+#define SECTION_STR_WATCHDOG_INIT_DATA          STR(SECTION_NAME_WATCHDOG_INIT_DATA)
+#define SECTION_STR_WATCHDOG_INIT_RODATA        STR(SECTION_NAME_WATCHDOG_INIT_RODATA)
+#define SECTION_STR_WATCHDOG_ERROR_TEXT         STR(SECTION_NAME_WATCHDOG_ERROR_TEXT)
+#define SECTION_STR_WATCHDOG_ERROR_DATA         STR(SECTION_NAME_WATCHDOG_ERROR_DATA)
+#define SECTION_STR_WATCHDOG_PRIV_STACKS        STR(SECTION_NAME_WATCHDOG_PRIV_STACKS)
+
+#define SECTION_WATCHDOG_TEXT                   SECTION(SECTION_STR_WATCHDOG_TEXT)
+#define SECTION_WATCHDOG_DATA                   SECTION(SECTION_STR_WATCHDOG_DATA)
+#define SECTION_WATCHDOG_INIT_TEXT              SECTION(SECTION_STR_WATCHDOG_INIT_TEXT)
+#define SECTION_WATCHDOG_INIT_DATA              SECTION(SECTION_STR_WATCHDOG_INIT_DATA)
+#define SECTION_WATCHDOG_INIT_RODATA            SECTION(SECTION_STR_WATCHDOG_INIT_RODATA)
+#define SECTION_WATCHDOG_ERROR_TEXT             SECTION(SECTION_STR_WATCHDOG_ERROR_TEXT)
+#define SECTION_WATCHDOG_ERROR_DATA             SECTION(SECTION_STR_WATCHDOG_ERROR_DATA)
+#define SECTION_WATCHDOG_PRIV_STACKS            SECTION(SECTION_STR_WATCHDOG_PRIV_STACKS)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/watchdog/sections-wdt.h b/spe-freertos-bsp/fsp/source/include/watchdog/sections-wdt.h
new file mode 100644
index 0000000..faefb45
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/watchdog/sections-wdt.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef WATCHDOG__SECTIONS_WDT_H
+#define WATCHDOG__SECTIONS_WDT_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for SECTION
+#include <misc/macros.h>                   // for STR
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/*
+ * Define the section name string.  The ARM and GNU tools optimize sections
+ *  differently based on the section naming conventions.  If the correct section
+ *  naming convention isn't used, the linker will fail to remove unused sections.
+ *
+ * When compiling with ARM tools, section name should be: NAME.TYPE
+ * When compiling with GNU tools, section name should be: TYPE.NAME
+ */
+/*                                      SECTION_BUILDER(NAME                    TYPE)   */
+#define SECTION_NAME_WDT_DATA           SECTION_BUILDER(wdt,                    data)
+#define SECTION_NAME_WDT_TEXT           SECTION_BUILDER(wdt,                    text)
+#define SECTION_NAME_WDT_ERROR_DATA     SECTION_BUILDER(error.wdt,              data)
+#define SECTION_NAME_WDT_ERROR_TEXT     SECTION_BUILDER(error.wdt,              text)
+#define SECTION_NAME_WDT_INIT_DATA      SECTION_BUILDER(init.wdt,               data)
+#define SECTION_NAME_WDT_INIT_TEXT      SECTION_BUILDER(init.wdt,               text)
+
+#define SECTION_STR_WDT_TEXT            STR(SECTION_NAME_WDT_TEXT)
+#define SECTION_STR_WDT_DATA            STR(SECTION_NAME_WDT_DATA)
+#define SECTION_STR_WDT_INIT_TEXT       STR(SECTION_NAME_WDT_INIT_TEXT)
+#define SECTION_STR_WDT_INIT_DATA       STR(SECTION_NAME_WDT_INIT_DATA)
+#define SECTION_STR_WDT_ERROR_TEXT      STR(SECTION_NAME_WDT_ERROR_TEXT)
+#define SECTION_STR_WDT_ERROR_DATA      STR(SECTION_NAME_WDT_ERROR_DATA)
+
+#define SECTION_WDT_TEXT                SECTION(SECTION_STR_WDT_TEXT)
+#define SECTION_WDT_DATA                SECTION(SECTION_STR_WDT_DATA)
+#define SECTION_WDT_INIT_TEXT           SECTION(SECTION_STR_WDT_INIT_TEXT)
+#define SECTION_WDT_INIT_DATA           SECTION(SECTION_STR_WDT_INIT_DATA)
+#define SECTION_WDT_ERROR_TEXT          SECTION(SECTION_STR_WDT_ERROR_TEXT)
+#define SECTION_WDT_ERROR_DATA          SECTION(SECTION_STR_WDT_ERROR_DATA)
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/watchdog/tegra-safe-wdt.h b/spe-freertos-bsp/fsp/source/include/watchdog/tegra-safe-wdt.h
new file mode 100644
index 0000000..0b8c758
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/watchdog/tegra-safe-wdt.h
@@ -0,0 +1,383 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef WATCHDOG__TEGRA_SAFE_WDT_H
+#define WATCHDOG__TEGRA_SAFE_WDT_H
+#define FSP__WATCHDOG__TEGRA_SAFE_WDT_H                      1
+
+/**
+ * @file tegra-safe-wdt.h
+ * @brief Defines safe driver to Tegra WDT hardware
+ */
+
+/* Compiler headers */
+#include <stdbool.h>              // for bool
+#include <stdint.h>               // for uint8_t, uint32_t
+                                  // IWYU pragma: no_include <errno.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>       // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>  // for error_t, FSP__ERROR__COMMON_ERRORS_H
+#include <misc/macros.h>          // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+/*
+ * Definition for tegra_wdt_id that allows the APIs to take a pointer to
+ * it without actually defining its contents here.
+ */
+// IWYU pragma: no_forward_declare tegra_wdt_id
+struct tegra_wdt_id;
+
+/**
+ * @brief Watchdog Callback function
+ *
+ * This is used to define the call back function that can be
+ * supplied that is called when a watchdog IRQ or FIQ occurs.
+ *
+ * @pre None
+ *
+ * @param[in]  status  Status of the watchdog timer when the callback
+ *                     function was called
+ * @param[in]  data    Pointer to data to be supplied to the callback
+ *                     function.  The pointer was specified when the watchdog
+ *                     timer was initialized.
+ *
+ * @return None
+ */
+typedef void (*tegra_wdt_callback)(uint32_t status, void *data);
+
+/**
+ * @brief Watchdog Initialization Structure
+ *
+ * Provides the initialization parameters for a watchdog timer.  Used in
+ * tegra_safe_wdt_setup().
+ */
+struct tegra_wdt_conf
+{
+    uint8_t             tmrsrc;                 ///! TKE timer to use
+    uint8_t             period;                 ///! number of timer ticks
+                                                ///!  in watchdog period
+    bool                irq_en;                 ///! Enable IRQ
+    bool                fiq_en;                 ///! Enable FIQ
+    bool                remoteIrq_en;           ///! Enable generating remote
+                                                ///!  interrupt
+    bool                sys_dbg_rst_en;
+    bool                sys_por_rst_en;
+    bool                tsc_ref_en;
+    uint8_t             err_threshold;
+    bool                challenge_response;     ///! Only allow timer updates
+                                                ///!  after proper
+                                                ///!  challenge / response
+    bool                irq_ack_by_callback;    ///! IRQ is acknowleged by
+                                                ///!  callback function
+    bool                fiq_ack_by_callback;    ///! IRQ is acknowleged by
+                                                ///!  callback function
+    tegra_wdt_callback  irq_callback;           ///! IRQ callback function
+    void                *irq_data;              ///! Data supplied to IRQ
+                                                ///!  callback function
+    tegra_wdt_callback  fiq_callback;           ///! FIQ callback function
+    void                *fiq_data;              ///! Data supplied to IRQ
+                                                ///!  callback function
+};
+
+/*
+ * Tegra WDT driver
+ *
+ * To use WDT driver,
+ * 1. Call tegra_wdt_setup to setup watchdog timer first
+ * 2. Call tegra_wdt_start to enable watchdog timer
+ *
+ * The wdt driver IRQ/FIQ handler will ack the watchdog automatically. If
+ * you want to do it from the callback or from a scheduld task, set
+ * irq_ack_by_callback/fiq_ack_by_callback.
+ */
+
+/**
+ * @brief Initialize watchdog timer
+ *
+ * This function will initialize the specified watchdog timer according to
+ * the configuration parameters supplied.
+ *
+ * @note This function can only be called if the specified watchdog timer
+ * is disabled.  If the specified watchdog timer is enabled, then it is
+ * necessary to call either tegra_safe_wdt_stop() or
+ * tegra_safe_wdt_stop_from_isr() to first stop the watchdog timer.
+ *
+ * This function must be called from a non-interrupt context.
+ *
+ * @pre The specified watchdog timer must not be running.
+ *
+ * @param[in]  id    pointer to the tegra_wdt_id structure that represents
+ *                   the watchdog timer being setup
+ * @param[in]  conf  pointer to the tegra_wdt_conf structure that contains
+ *                   the configuration parameters to be used when initializing
+ *                   the watchdog timer.
+ *
+ * @return Error Code
+ *
+ * @retval E_SUCCESS                    watchdog timer was successfully
+ *                                      initialized
+ * @retval E_WDT_ERR_NULL_PTR           one of the pointers passed was NULL
+ * @retval E_WDT_ERR_IRQ_CONFIG         The watchdog's IRQ or FIQ was
+ *                                      enabled but no corresponding
+ *                                      callback function was specified
+ * @retval E_WDT_ERR_TMRSRC_INVALID     value specified for tmrsrc was invalid
+ * @retval E_WDT_ERR_THRESHOLD_INVALID  value specified for threshold was
+ *                                      invalid
+ */
+error_t tegra_safe_wdt_setup(struct tegra_wdt_id *id,
+                             const struct tegra_wdt_conf *conf);
+
+/**
+ * @brief Start Watchdog Timer
+ *
+ * This function will start the specified watchdog timer using the parameters
+ * that were supplied as part of tegra_safe_wdt_setup().
+ *
+ * This function can be called from either an interrupt context or a
+ * non-interrupt context.
+ *
+ * @pre The function tegra_safe_wdt_setup() must have been previously called.
+ *
+ * @param[in]  id  pointer to the tegra_wdt_id structure that represents the
+ *                 watchdog timer being started.
+ *
+ * @return Error Code
+ * @retval E_SUCCESS            status was returned successfully
+ * @retval E_WDT_ERR_NULL_PTR   id was NULL
+ */
+error_t tegra_safe_wdt_start(const struct tegra_wdt_id *id);
+
+/**
+ * @brief Acknowlege Watchdog Timer
+ *
+ * This function will acknowlege the specified watchdog timer and
+ * reset its operation so that it will restart its count.
+ *
+ * This function can be called from either an interrupt context or a
+ * non-interrupt context.
+ *
+ * @pre tegra_safe_wdt_setup() must have been previously called.
+ *
+ * @param[in]  id  pointer to the tegra_wdt_id structure that represents the
+ *                 watchdog timer being acknowleged.
+ *
+ * @return Error Code
+ * @retval E_SUCCESS            status was returned successfully
+ * @retval E_WDT_ERR_NULL_PTR   id was NULL
+ */
+error_t tegra_safe_wdt_ack(const struct tegra_wdt_id *id);
+
+/**
+ * @brief Stop watchdog timer
+ *
+ * This function will stop the specified watchdog timer.  It will stop it
+ * from counting and thus prevent it from generating an IRQ or FIQ from the
+ * watchdog timer.
+ *
+ * This function must be called from an interrupt context.
+ *
+ * @pre tegra_safe_wdt_setup() must have been previously called.
+ *
+ * @param[in]  id  pointer to the tegra_wdt_id structure that represents the
+ *                 watchdog timer being stopped.
+ *
+ * @return Error Code
+ * @retval E_SUCCESS            status was returned successfully
+ * @retval E_WDT_ERR_NULL_PTR   id was NULL
+ */
+error_t tegra_safe_wdt_stop_from_isr(const struct tegra_wdt_id *id);
+
+/**
+ * @brief Stop watchdog timer
+ *
+ * This function will stop the specified watchdog timer.  It will stop it
+ * from counting and thus prevent it from generating an IRQ or FIQ from the
+ * watchdog timer.
+ *
+ * This function must be called from a non-interrupt context.
+ *
+ * @pre tegra_safe_wdt_setup() must have been previously called.
+ *
+ * @param[in]  id  pointer to the tegra_wdt_id structure that represents the
+ *                 watchdog timer being stopped.
+ *
+ * @return Error Code
+ * @retval E_SUCCESS            status was returned successfully
+ * @retval E_WDT_ERR_NULL_PTR   id was NULL
+ */
+error_t tegra_safe_wdt_stop(const struct tegra_wdt_id *id);
+
+/**
+ * @brief Watchdog timer interrupt handler
+ *
+ * This function is responsible for servicing the watchdog IRQ.  The
+ * behavior of this function is dependent upon how the watchdog timer
+ * was configured.
+ *
+ * This function is called from the first level interrupt handler for
+ * the watchdog interrupt, so it will be called only from an interrupt
+ * context.
+ *
+ * @pre tegra_safe_wdt_setup() must have been previously called.
+ * @pre the watchdog timer must have been previously started
+ *
+ * @param[in]  id  pointer to the tegra_wdt_id structure that represents the
+ *                 watchdog timer that has generated an interrupt.
+ *
+ * @return None
+ */
+void tegra_safe_wdt_irq(void *data);
+
+/**
+ * @brief Watchdog timer fast interrupt handler
+ *
+ * This function is responsible for servicing the watchdog FIQ.  The
+ * behavior of this function is dependent upon how the watchdog timer
+ * was configured.
+ *
+ * This function is called from the first level interrupt handler for
+ * the watchdog fast interrupt, so it will be called only from an interrupt
+ * context.
+ *
+ * @pre tegra_safe_wdt_setup() must have been previously called.
+ * @pre the watchdog timer must have been previously started
+ *
+ * @param[in]  id  pointer to the tegra_wdt_id structure that represents the
+ *                 watchdog timer that has generated an FIQ interrupt.
+ *
+ * @return None
+ */
+void tegra_safe_wdt_fiq(void *data);
+
+/**
+ * @brief Read watchdog timer status
+ *
+ * This function will return the current status of the specified watchdog
+ * timer.
+ *
+ * This function can be called from either an interrupt context or a
+ * non-interrupt context.
+ *
+ * @pre None
+ *
+ * @param [in]  id      pointer to the tegra_wdt_id structure that represents
+ *                      the watchdog timer whose status is to be returned
+ * @param [in]  status  pointer to a 32-bit value that will be updated as a
+ *                      result of this call that contains the watchdog's
+ *                      timer status.  The value is interpreted as follows:
+ *
+ *   bit 0      Enabled                 1b when the counter is active
+ *
+ *                                      0b when the counter is disabled
+ *
+ *   bit 1      LocalIRQStatus          Current status of interrupt
+ *
+ *   bit 2      LocalFIQStatus          Current status of FIQ
+ *
+ *   bit 3      RemoteInterruptStatus   Current status of remote interrupt
+ *
+ *   bit 11:4   CurrentCount            Current value of the counter
+ *
+ *   bit 14:12  CurrentExpirationCount  Current count of expiration since
+ *                                      last start operation
+ *
+ *   bit 16     CurrentError            Current error reported to HSM
+ *
+ * @return Error Code
+ * @retval E_SUCCESS            status was returned successfully
+ * @retval E_WDT_ERR_NULL_PTR   one of the pointers passed was NULL
+ *
+ */
+error_t tegra_safe_wdt_read_status(const struct tegra_wdt_id *id,
+                                   uint32_t *status);
+
+
+/**
+ * @brief Enable windowed mode operation for the watchdog timer
+ *
+ * This function sets the timer window parameters, start level and start count
+ * and enables the windowed mode operation.
+ *
+ * @pre tegra_safe_wdt_setup should be run before calling this function
+ *
+ * @param[in]  id         pointer to the tegra_wdt_id structure that represents
+ *                        the watchdog timer whose status is to be returned
+ * @param[in] start_level Threshold for expiration level
+ * @param[in] start_count Number of cycles where rejection takes place at the
+ *                        start of that level
+ *
+ * @return Error Code
+ * @retval E_SUCCESS            status was returned successfully
+ * @retval E_WDT_ERR_NULL_PTR   one of the pointers passed was NULL
+ */
+error_t tegra_safe_enable_wdt_windowed_operation(const struct tegra_wdt_id *id,
+                                                 uint8_t start_level,
+                                                 uint8_t start_count);
+
+/**
+ * @brief Disable windowed mode operation for the watchdog timer
+ *
+ * This function disables the windowed mode operation for the watchdog timer
+ *
+ * @pre none
+ *
+ * @param[in]  id         pointer to the tegra_wdt_id structure that represents
+ *                        the watchdog timer whose status is to be returned
+ *
+ * @return Error Code
+ * @retval E_SUCCESS            status was returned successfully
+ * @retval E_WDT_ERR_NULL_PTR   one of the pointers passed was NULL
+ */
+error_t tegra_safe_disable_wdt_windowed_operation(const struct tegra_wdt_id *id);
+#endif /* WATCHDOG__WDT_TEGRA_H */
diff --git a/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-errors.h b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-errors.h
new file mode 100644
index 0000000..2a4a03d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-errors.h
@@ -0,0 +1,190 @@
+/* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef WATCHDOG__WATCHDOG_ERRORS_H
+#define WATCHDOG__WATCHDOG_ERRORS_H
+#define FSP__WATCHDOG__WATCHDOG_ERRORS_H                1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>     // IWYU pragma: export
+                                // IWYU pragma: no_include "base/module-id.h"
+#include <misc/macros.h>        // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file watchdog-errors.h
+ * @brief Error codes that are specific to the watchdog framework
+ */
+
+/**
+ * @brief No more processing of out of bounds tasks.
+ *
+ * Indicates that the framework should not report any additional tasks
+ * that are "out of bounds" during the current invokation of
+ * WatchdogCheckStatus().
+ */
+#define E_WDT_ERR_DONE                  MODULE_ERROR(WDT, 0UL)
+
+/**
+ * @brief Too many tasks being monitored.
+ *
+ * Indicates that more tasks are trying to be monitored than the
+ * watchdog framework has been configured for.
+ */
+#define E_WDT_ERR_TOO_MANY_TASKS        MODULE_ERROR(WDT, 1UL)
+
+/**
+ * @brief Task is already being monitored
+ *
+ * Indicates that the task to be monitored has already been registered to
+ * be monitored by the watchdog framework.
+ */
+#define E_WDT_ERR_DUPLICATE_TASK        MODULE_ERROR(WDT, 2UL)
+
+/**
+ * @brief NULL pointer has been passed
+ *
+ * Indicates that a pointer passed as an argument is NULL.
+ */
+#define E_WDT_ERR_NULL_PTR              MODULE_ERROR(WDT, 3UL)
+
+/**
+ * @brief Watchdog framework has not been initialized
+ *
+ * Indicates that one of the watchdog framework APIs has been called
+ * prior to WatchdogInit() being called.
+ */
+#define E_WDT_ERR_WATCHDOG_NOT_INIT     MODULE_ERROR(WDT, 4UL)
+
+/**
+ * @brief ID is not a valid task ID
+ *
+ * Indicates that the task ID supplied to one of the watchdog framework APIs does
+ * not represent a task that has been registered with the watchdog
+ * framework.
+ */
+#define E_WDT_ERR_NO_TASK               MODULE_ERROR(WDT, 5UL)
+
+/**
+ * @brief Task's execution time is out of bounds
+ *
+ * Indicates that the task's execution time exceeded its specified timeout.
+ */
+#define E_WDT_ERR_TASK_OUT_OF_BOUNDS    MODULE_ERROR(WDT, 6UL)
+
+/**
+ * @brief Task has no work to perform
+ *
+ * Indicates that a task tried to start work when no work had been queued for
+ * the task.
+ */
+#define E_WDT_ERR_NO_WORK               MODULE_ERROR(WDT, 7UL)
+
+/**
+ * @brief Sequence error in API calls
+ *
+ * Indicates that there was a sequence error in the order of calls to
+ * WatchdogStartItem() and WatchdogCompleteItem().
+ */
+#define E_WDT_ERR_SEQUENCE              MODULE_ERROR(WDT, 8UL)
+
+/**
+ * @brief Watchdog hardware should not be pet.
+ *
+ * Indication from a callback function that the watchdog hardware should not
+ * be "pet" at this time.
+ */
+#define E_WDT_ERR_NO_PET                MODULE_ERROR(WDT, 9UL)
+
+/**
+ * @brief Supplied timeout is invalid.
+ */
+#define E_WDT_ERR_INVALID_TIMEOUT       MODULE_ERROR(WDT, 10UL)
+
+/**
+ * @brief Watchdog callback configuration
+ *
+ * Watchdog interrupt was enabled but no callback function supplied.
+ */
+#define E_WDT_ERR_IRQ_CONFIG            MODULE_ERROR(WDT, 11UL)
+
+/**
+ * @brief Watchdog Timer Source Invalid
+ *
+ * Value specified for the watchdog timer source was not a valid
+ * value (e.g. it had non-zero bits in fields that should be 0).
+ */
+#define E_WDT_ERR_TMRSRC_INVALID        MODULE_ERROR(WDT, 12UL)
+
+/**
+ * @brief Watchdog Timer Threshold Invalid
+ *
+ * Value specified for the watchdog timer threshold was not a valid
+ * value (e.g. it had non-zero bits in fields that should be 0).
+ */
+#define E_WDT_ERR_THRESHOLD_INVALID     MODULE_ERROR(WDT, 13UL)
+
+/**
+ * @brief Watchdog Statistics Not Available
+ *
+ * A request was made to get the watchdog statistics for a task and
+ * watchdog statistics has not been configured in the build.
+ */
+#define E_WDT_ERR_NO_STATS              MODULE_ERROR(WDT, 14U)
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-internal.h b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-internal.h
new file mode 100644
index 0000000..809538b
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-internal.h
@@ -0,0 +1,163 @@
+/* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef WATCHDOG__WATCHDOG_INTERNAL_H
+#define WATCHDOG__WATCHDOG_INTERNAL_H
+#define FSP__WATCHDOG__WATCHDOG_INTERNAL_H      1
+
+/* Compiler headers */
+#include <stdint.h>                        // for uint64_t, uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <osa/osa-task.h>                  // for rtosTaskHandle
+#include <error/common-errors.h>           // for error_t
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <tke/tke-tegra.h>                 // for tegra_tke_get_tsc64
+
+/* Module-specific FSP headers */
+#include <watchdog-config.h>               // Immune from CT_ASSERT protection
+                                           // for WATCHDOG_MAX_TASKS
+#include <watchdog/watchdog-statistics.h>  // for WatchdogTaskStatistics
+#include <watchdog/watchdog-types.h>       // for WatchdogCount, WatchdogStatus
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSA__OSA_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__TKE__TKE_TEGRA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_STATISTICS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_TYPES_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file watchdog-internal.h
+ * @brief Internal definitions for watchdog framework
+ */
+
+/**
+ * @brief Watchdog Monitored Task State
+ *
+ * States that a task could be in that is monitored by the watchdog
+ * framework.
+ */
+#define WATCHDOG_NOT_MONITORED  0U      ///! Task is not monitored
+#define WATCHDOG_ITEM_STARTED   1U      ///! Task started processing an item
+#define WATCHDOG_ITEM_COMPLETED 2U      ///! Task completed processing an item
+#define WATCHDOG_ITEM_TIMEOUT   3U      ///! Task did not complete processing
+                                        ///!  within its timeout period
+#define WATCHDOG_TASK_WAITING   4U      ///! Task is waiting for work
+#define WATCHDOG_TASK_WARNING   5U
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_5, "Approval: Bug 3175244, DR: SWE-FSP-013-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+
+/**
+ * @brief Watchdog Tracking Structure
+ *
+ * This structure is used to track the state and operation of the various
+ * tasks that have been registered to be monitored by the Watchdog framework.
+ */
+typedef struct {
+    uint64_t            lastStartTime;  ///! Last time WatchdogStartItem() was
+                                        ///!  called for the task
+    uint64_t            taskTimeout;    ///! Timeout for the task.  Represents
+                                        ///!  the maximum amount of time that
+                                        ///!  may transpire between a call to
+                                        ///!  WatchdogStartItem() and a call to
+                                        ///!  WatchdogCompleteItem()
+    rtosTaskHandle      taskID;         ///! Task handle to the task being
+                                        ///!  monitored
+    WatchdogCount       itemsInQueue;   ///! Number of times that
+                                        ///!  WatchdogAddItem() has been called
+                                        ///!  vs number of times that
+                                        ///!  WatchdogStartItem() has been
+                                        ///!  called
+    WatchdogStatus      taskStatus;     ///! Monitored state of the task.
+#if defined(WATCHDOG_STATISTICS) && (WATCHDOG_STATISTICS==1)
+    WatchdogTaskStatistics taskStats;   ///! Statistics for the task
+#endif
+} WatchdogTaskState;
+
+extern WatchdogTaskState        watchdogState[WATCHDOG_MAX_TASKS];
+
+/**
+ * @brief Validate a watchdog task ID
+ *
+ * This function will validate a watchdog task ID to ensure that it
+ * is valid.
+ *
+ * @param [in] ID       ID to validate
+ *
+ * @return Error Code
+ *
+ * @retval E_SUCCESS    ID is a valid task ID
+ * @retval E_WDT_ERR_NO_TASK            indicates that the task ID was not valid
+ * @retval E_WDT_ERR_WATCHDOG_NOT_INIT  indicates that the watchdog framework
+ *                                      has not been initialized
+ */
+error_t
+WatchdogValidateID(const WatchdogTaskID ID);
+
+/**
+ * @brief Return current time
+ *
+ * Returns the current time to the caller in nano-seconds.
+ * Since this is a 64-bit value the rollover will happen in
+ * about 584 years.
+ *
+ * @pre TSC counter must be running
+ *
+ * @return 64-bit value that represents the current time in nano-seconds
+ */
+static inline uint64_t
+WatchdogGetTime(void)
+{
+    return tegra_tke_get_tsc64() << 5;
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-logging.h b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-logging.h
new file mode 100644
index 0000000..ac2de53
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-logging.h
@@ -0,0 +1,76 @@
+/* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef WATCHDOG__WATCHDOG_LOGGING_H
+#define WATCHDOG__WATCHDOG_LOGGING_H
+#define FSP__WATCHDOG__WATCHDOG_LOGGING_H               1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <logger/logger.h>
+#include <misc/macros.h>                // for START_RFD_BLOCK, END_RFD_BLOCK, ...
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__LOGGER__LOGGER_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @file watchdog-logging.h
+ * @brief Definitions for logging in watchdog code
+ */
+
+#define WATCHDOG_LOG_INIT               LOG_ID(WATCHDOG, 0x00U, 0U)
+#define WATCHDOG_LOG_LVL1_TIMEOUT       LOG_ID(WATCHDOG, 0x01U, 0U)
+#define WATCHDOG_LOG_LVL2_TIMEOUT       LOG_ID(WATCHDOG, 0x02U, 0U)
+#define WATCHDOG_LOG_WAKEUP             LOG_ID(WATCHDOG, 0x03U, 0U)
+#define WATCHDOG_LOG_SLEEP              LOG_ID(WATCHDOG, 0x04U, 0U)
+#define WATCHDOG_LOG_TIMEOUT            LOG_ID(WATCHDOG, 0x05U, 0U)
+#define WATCHDOG_LOG_APPLICATION        LOG_ID(WATCHDOG, 0x06U, 0U)
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-no-stats-internal.h b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-no-stats-internal.h
new file mode 100644
index 0000000..e1f13e6
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-no-stats-internal.h
@@ -0,0 +1,103 @@
+/* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef WATCHDOG__WATCHDOG_NO_STATS_INTERNAL_H
+#define WATCHDOG__WATCHDOG_NO_STATS_INTERNAL_H
+#define FSP__WATCHDOG__WATCHDOG_NO_STATS_INTERNAL_H     1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <watchdog/watchdog-internal.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_INTERNAL_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @file watchdog-no-stats-internal.h
+ * @brief Definitions for when Watchdog Statistics are not enabled
+ *
+ * This file provides the definitions so that the watchdog code
+ * builds and functions without the overhead of the statistics code.
+ *
+ * This file should not be included directly.  It should only be
+ * included by <watchdog/watchdog-statistics-internal.h>.
+ */
+
+static inline void
+WatchdogStatsInit(const WatchdogTaskState *state)
+{
+    UNUSED(state);
+}
+
+static inline void
+WatchdogStatsAddItem(const WatchdogTaskState *state)
+{
+    UNUSED(state);
+}
+
+static inline void
+WatchdogStatsStartItem(const WatchdogTaskState *state)
+{
+    UNUSED(state);
+}
+
+static inline void
+WatchdogStatsCompleteItem(const WatchdogTaskState *state,
+                          uint64_t completeTime)
+{
+    UNUSED(state);
+    UNUSED(completeTime);
+}
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-statistics-internal.h b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-statistics-internal.h
new file mode 100644
index 0000000..0fb9f37
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-statistics-internal.h
@@ -0,0 +1,75 @@
+/* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef WATCHDOG__WATCHDOG_STATISTICS_INTERNAL_H
+#define WATCHDOG__WATCHDOG_STATISTICS_INTERNAL_H
+#define FSP__WATCHDOG__WATCHDOG_STATISTICS_INTERNAL_H   1
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/**
+ * @file watchdog-statistics-internal.h
+ * @brief Wrapper for pulling in the statistics internals or not.
+ */
+
+#if defined(WATCHDOG_STATISTICS) && (WATCHDOG_STATISTICS==1)
+#include <watchdog/watchdog-stats-internal.h>       // IWYU pragma: export
+                                                    // IWYU pragma: no_include "watchdog/watchdog-stats-internal.h"
+#else
+#include <watchdog/watchdog-no-stats-internal.h>    // IWYU pragma: export
+                                                    // IWYU pragma: no_include "watchdog/watchdog-no-stats-internal.h"
+#endif
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#if defined(WATCHDOG_STATISTICS) && (WATCHDOG_STATISTICS==1)
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_STATS_INTERNAL_H, "Header file missing or invalid.")
+#else
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_NO_STATS_INTERNAL_H, "Header file missing or invalid.")
+#endif
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-statistics.h b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-statistics.h
new file mode 100644
index 0000000..527ae8e
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-statistics.h
@@ -0,0 +1,75 @@
+/* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef WATCHDOG__WATCHDOG_STATISTICS_H
+#define WATCHDOG__WATCHDOG_STATISTICS_H
+#define FSP__WATCHDOG__WATCHDOG_STATISTICS_H                 1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/**
+ * @file watchdog-statistics.h
+ * @brief Definitions for Watchdog Statistics
+ */
+
+/**
+ * @brief Number of watchdog histogram buckets
+ *
+ * This is defined as a constant but all of the code really assumes
+ * that the histogram is decimal based.
+ */
+#define WATCHDOG_STATS_NUM_BUCKETS      10U
+
+/**
+ * @brief Watchdog Statistics Structure
+ */
+typedef struct {
+    uint64_t            count;
+    uint64_t            accumulatedTime;
+    uint64_t            minTime;
+    uint64_t            maxTime;
+    uint64_t            histogram[WATCHDOG_STATS_NUM_BUCKETS];
+} WatchdogStatistics;
+
+/**
+ * @brief Watchdog Task Statistics Structure
+ */
+typedef struct {
+    uint64_t            maxItemsInQueue;
+    WatchdogStatistics  itemStats;
+} WatchdogTaskStatistics;
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-stats-internal.h b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-stats-internal.h
new file mode 100644
index 0000000..ffb2c48
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-stats-internal.h
@@ -0,0 +1,130 @@
+/* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef WATCHDOG__WATCHDOG_STATS_INTERNAL_H
+#define WATCHDOG__WATCHDOG_STATS_INTERNAL_H
+#define FSP__WATCHDOG__WATCHDOG_STATS_INTERNAL_H        1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>                       // for START_RFD_BLOCK, END_RFD_BLOCK, ...
+
+/* Module-specific FSP headers */
+#include <watchdog/watchdog-internal.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_INTERNAL_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/**
+ * @file watchdog-stats-internal.h
+ * @brief Definitions for when Watchdog statistics are enabled
+ *
+ * This file provides the definitions for when watchdog statistics are
+ * enabled so that statistics are gathered and can be retrieved.
+ *
+ * This file should not be included directly.  It should only be
+ * included by <watchdog/watchdog-statistics-internal.h>.
+ */
+
+/**
+ * @brief Initialize Watchdog Statistics for a monitored task
+ *
+ * This function will initialize the statistics structure for
+ * a watchdog monitored task.
+ *
+ * @param[in] state     pointer to a task's watchdog state structure.
+ *
+ * @return None
+ */
+void
+WatchdogStatsInit(WatchdogTaskState *state);
+
+/**
+ * @brief Capture statistics when an item is added to a task
+ *
+ * This function will update a task's statistics as a result of adding
+ * an item to the task's work queue.
+ *
+ * @param[in] state     pointer to a task's watchdog state structure.
+ *
+ * @return None
+ */
+void
+WatchdogStatsAddItem(WatchdogTaskState *state);
+
+/**
+ * @brief Capature statistics when a task starts work on an item
+ *
+ * This function will update a task's statistics as a result of starting
+ * to process an item on the task's work queue.
+ *
+ * @param[in] state     pointer to a task's watchdog state structure.
+ *
+ * @return None
+ */
+void
+WatchdogStatsStartItem(const WatchdogTaskState *state);
+
+/**
+ * @brief Capture statistics when a task completes work on an item
+ *
+ * This function will update a task's statistics as a result of completing
+ * processing of an item on the task's work queue.
+ *
+ * @param[in] state             pointer to a task's watchdog state structure.
+ * @param[in] completeTime      time when the item was completed.
+ *
+ * @return None
+ */
+void
+WatchdogStatsCompleteItem(WatchdogTaskState *state,
+                          uint64_t completeTime);
+
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-task.h b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-task.h
new file mode 100644
index 0000000..bb54e65
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-task.h
@@ -0,0 +1,143 @@
+/* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef WATCHDOG__WATCHDOG_TASK_H
+#define WATCHDOG__WATCHDOG_TASK_H
+#define FSP__WATCHDOG__WATCHDOG_TASK_H                  1
+
+/**
+ * @file watchdog-task.h
+ * @brief Definitions for use of watchdog task
+ */
+
+/* Compiler headers */
+#include <stdint.h>                   // for uint64_t, uint32_t
+#include <stdbool.h>                  // for bool
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>           // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <osa/rtos-task.h>            // for rtosTaskHandle
+#include <misc/macros.h>              // for START_RFD_BLOCK, END_RFD_BLOCK, ...
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+/*
+ * Watchdog Task's stack depth.
+ *
+ * In general this shouldn't need adjusting, but care must be taken
+ * in the case of the callbacks
+ */
+#define WATCHDOG_STACK_DEPTH    512
+
+/**
+ * @brief Watchdog Task Initialization Parameters
+ *
+ * Structure passed to the WatchdogTaskInit() function, this is used to
+ * initialize various aspects of the watchdog task.  This allows an
+ * application firmware to specify various attributes of the watchdog
+ * task without having to expose various internal apsects of the watchdog
+ * task itself.
+ */
+typedef struct {
+    uint8_t             hw_period;      // milliseconds for WDT timeout
+    bool                wdt_enabled;    // enable WDT timer
+    bool                watchdog_mpu;   // use per task MPU region
+    uint8_t             pad;            // pad to align next field
+    rtosTick            pet_period;     // milliseconds between pet attempts
+    rtosPriority        task_priority;  // priority of the watchdog task
+    uint32_t            stack_priority; // MPU priority for watchdog's stack
+    uint64_t            min_timeout;    // minimum value for a task timeout
+    uint64_t            max_timeout;    // maximum value for a task timeout
+    uint64_t            default_timeout;// default value for a task timeout
+} WatchdogInitParameters;
+
+/**
+ * @brief Task Parameters for Watchdog Task
+ *
+ * The task parameters that are to be used when the application firmware
+ * creates the watchdog task.  The values in this structure should not be
+ * modified by the application firmware.
+ */
+extern rtosTaskParameters       WatchdogTaskParams;
+
+/**
+ * @brief Initialize the watchdog task
+ *
+ * This function must be called prior to creating the watchdog task
+ * as it sets up various aspects of the task.  This function does not
+ * create the watchdog task.  It is the responsibility of the application
+ * firmware to create the watchdog task after this function has been called.
+ *
+ * @pre None
+ *
+ * @param[in] parameters  pointer to a WatchdogInitParameters structure that
+ *                        contains various initialization parameters specified
+ *                        by the application.  This is distinct from the
+ *                        rtosTaskParameters structure which is used by the
+ *                        RTOS to create and start the task
+ *
+ * @return Error Code
+ *
+ * @retval E_SUCCESS     initialization was performed successfully
+ * @retval E_RTOS_EVENT_GROUP_ALREADY_IN_USE Input event group already in use.
+ * @retval E_RTOS_NULL_PARAMETER_SUPPLIED    Null Input parameter
+ * @retval E_RTOS_EVENT_GROUP_ALREADY_IN_USE Event handle supplied is valid and
+ *                                           must be deleted before creating a
+ *                                           new group
+ * @retval E_WDT_ERR_IRQ_CONFIG         The watchdog's IRQ or FIQ was
+ *                                      enabled but no corresponding
+ *                                      callback function was specified
+ * @retval E_WDT_ERR_TMRSRC_INVALID     value specified for tmrsrc was invalid
+ * @retval E_WDT_ERR_THRESHOLD_INVALID  value specified for threshold was
+ *                                      invalid
+ * @retval rtosFAIL      initialization could not be performed
+ */
+rtosError WatchdogTaskInit(const void * const parameters);
+
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-types.h b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-types.h
new file mode 100644
index 0000000..d787358
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog-types.h
@@ -0,0 +1,91 @@
+/* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef WATCHDOG__WATCHDOG_TYPES_H
+#define WATCHDOG__WATCHDOG_TYPES_H
+#define FSP__WATCHDOG__WATCHDOG_TYPES_H                 1
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>            // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>               // for START_RFD_BLOCK, END_RFD_BLOCK
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+
+/**
+ * @file watchdog-types.h
+ * @brief Configuration of watchdog framework
+ */
+
+/**
+ * @brief Watchdog task ID
+ *
+ * An ID used by the watchdog framework to represent a task that is being
+ * monitored.
+ */
+typedef uint32_t        WatchdogTaskID;
+
+/**
+ * @brief Task's count of items
+ *
+ * Used to represent the number of WatchdogAddItem() calls without subsequent
+ * WatchdogStartItem() calls.  That is, the number of items that are queued
+ * waiting for the task to process.
+ */
+typedef uint32_t         WatchdogCount;
+
+/**
+ * @brief Task status
+ *
+ * Represents the state of a task that is monitored by the watchdog framework.
+ */
+typedef uint32_t         WatchdogStatus;
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/watchdog/watchdog.h b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog.h
new file mode 100644
index 0000000..91b38dd
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/watchdog/watchdog.h
@@ -0,0 +1,520 @@
+/* Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef WATCHDOG__WATCHDOG_H
+#define WATCHDOG__WATCHDOG_H
+#define FSP__WATCHDOG__WATCHDOG_H                       1
+
+/* Compiler headers */
+#include <stdint.h>                        // for uint64_t, uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <osa/rtos-task.h>                 // for rtosTaskHandle, FSP__OSA__...
+#include <error/common-errors.h>           // for error_t, FSP__ERROR__COMMO...
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <watchdog/watchdog-types.h>       // for WatchdogTaskID, FSP__WATCH...
+#include <watchdog/watchdog-statistics.h>  // for FSP__WATCHDOG__WATCHDOG_ST...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_TYPES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WATCHDOG_STATISTICS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @file watchdog.h
+ * @brief Exported structures and interfaces for watchdog operations.
+ */
+
+/**
+ * @brief Initialize the watchdog infrastructure
+ *
+ * Initializes the watchdog infrastructure to allow for the other
+ * watchdog APIs to be used.  If other APIs are called prior to this
+ * being, they will return an error.
+ *
+ * @pre None
+ *
+ * @param[in] minTimeout      minimum time (in nano-seconds) for a task's
+ *                            timeout value
+ * @param[in] maxTimeout      maximum time (in nano-seconds) for a task's
+ *                            timeout value
+ * @param[in] defaultTimeout  default value (in nano-seconds) to apply to
+ *                            a task's timeout
+ *
+ * @return Error code
+ * @retval E_SUCCESS    Watchdog infrastructure was initialized successfully.
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+error_t WatchdogInit(uint64_t minTimeout,
+                     uint64_t maxTimeout,
+                     uint64_t defaultTimeout);
+
+/**
+ * @brief Indicate that a task is to be monitored
+ *
+ * Indicate to the watchdog infrastructure that a task wants to be monitored
+ *
+ * @pre WatchdogInit() must have been previously called.
+ *
+ * @param[in]     taskID    RTOS task ID of the task to be monitored
+ * @param[in]     maxTime   maximum time the task can spend processing an item
+ * @param[in,out] pID       watchdog ID assigned to the task
+ *
+ * @return Error code
+ *
+ * @retval E_SUCCESS                    indicates that the task will now be
+ *                                      monitored
+ * @retval E_WDT_ERR_TOO_MANY_TASKS     indicates that there are too many tasks
+ *                                      being monitored
+ * @retval E_WDT_ERR_DUPLICATE_TASK     indicates that the task is already being
+ *                                      monitored
+ * @retval E_WDT_ERR_NULL_PTR           indicates that pID was NULL
+ * @retval E_WDT_ERR_WATCHDOG_NOT_INIT  indicates that the watchdog framework
+ *                                      has not been initialized
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+error_t WatchdogTaskMonitor(const rtosTaskHandle taskID, uint64_t maxTime,
+                            WatchdogTaskID *pID);
+
+/**
+ * @brief Indicate that an item is waiting to be processed
+ *
+ * Indicates that an item has been added for the indicated task to operate on.
+ *
+ * This cannot be called from interrupt context.
+ *
+ * @pre WatchdogInit() must have been previously called.
+ * @pre WatchdogTaskMonitor() must have been called to register the task to
+ *      be monitored.
+ *
+ * @param[in] ID  ID of the task whose work list has been added to
+ *
+ * @return Error Code
+ *
+ * @retval E_SUCCESS                    indicates that item was successfully
+ *                                      logged to the task
+ * @retval E_WDT_ERR_NO_TASK            indicates that the task ID was not valid
+ * @retval E_WDT_ERR_WATCHDOG_NOT_INIT  indicates that the watchdog framework
+ *                                      has not been initialized
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+error_t WatchdogAddItem(const WatchdogTaskID ID);
+
+/**
+ * @brief Indicate that an item is waiting to be processed.
+ *
+ * Indicates that an item has been added for the indicated task to operate on.
+ *
+ * This can only be called from an interrupt context.
+ *
+ * @pre WatchdogInit() must have been previously called.
+ * @pre WatchdogTaskMonitor() must have been called to register the task to
+ *      be monitored.
+ *
+ * @param[in] ID  ID of the task whose work list has been added to
+ *
+ * @return Error Code
+ *
+ * @retval E_SUCCESS                    indicates that item was successfully
+ *                                      logged to the task
+ * @retval E_WDT_ERR_NO_TASK            indicates that the task ID was not valid
+ * @retval E_WDT_ERR_WATCHDOG_NOT_INIT  indicates that the watchdog framework
+ *                                      has not been initialized
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+error_t WatchdogAddItemFromISR(const WatchdogTaskID ID);
+
+/**
+ * @brief Indicate that a task has started working on an item
+ *
+ * Informs the watchdog framework that the task has started working on a
+ * previously submitted item.
+ *
+ * @pre WatchdogInit() must have been previously called.
+ * @pre WatchdogTaskMonitor() must have been called to register the task to
+ *      be monitored.
+ * @pre WatchdogAddItem() or WatchdogAddItemFromISR() must have been called
+ *      such that it appears to the watchdog framework that there is work pending
+ *      for the task.
+ *
+ * @param[in] ID  ID of the task that is starting to work on an item
+ *
+ * @return Error Code
+ *
+ * @retval E_SUCCESS                     indicates that the watchdog framework
+ *                                       was successfully informed
+ * @retval E_WDT_ERR_NO_TASK             indicates that the task ID was not valid
+ * @retval E_WDT_ERR_NO_WORK             indicates that no items have been added
+ *                                       to indicate that there is actually work
+ *                                       for the task to perform
+ * @retval E_WDT_ERR_SEQUNECE            indicates that there was no intervening
+ *                                       WatchdogCompleteItem() after a previous
+ *                                       call to WatchdogStartItem()
+ * @retval E_WDT_ERR_TASK_OUT_OF_BOUNDS  indicates that the task exceeded its
+ *                                       timeout during a previous call to
+ *                                       WatchdogStartItem()
+ * @retval E_WDT_ERR_WATCHDOG_NOT_INIT   indicates that the watchdog framework
+ *                                       has not been initialized
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+error_t WatchdogTaskStartItem(const WatchdogTaskID ID);
+
+/**
+ * @brief Indicate that current task has started working on an item.
+ *
+ * Informs the watchdog framework that the current task has started working on a
+ * previously submitted item.
+ *
+ * This function must be called from a non-interrupt context.
+ *
+ * @pre WatchdogInit() must have been previously called.
+ * @pre WatchdogTaskMonitor() must have been called to register the task to
+ *      be monitored.
+ * @pre WatchdogAddItem() or WatchdogAddItemFromISR() must have been called
+ *      such that it appears to the watchdog framework that there is work pending
+ *      for the task.
+ *
+ * @return Error Code
+ *
+ * @retval E_SUCCESS                     indicates that the watchdog framework
+ *                                       was successfully informed
+ * @retval E_WDT_ERR_NO_TASK             indicates that the current task is not
+ *                                       monitored
+ * @retval E_WDT_ERR_NO_WORK             indicates that no items have been added
+ *                                       to indicate that there is actually work
+ *                                       to do
+ * @retval E_WDT_ERR_SEQUNECE            indicates that there was no intervening
+ *                                       WatchdogCompleteItem() after a previous
+ *                                       call to WatchdogStartItem()
+ * @retval E_WDT_ERR_TASK_OUT_OF_BOUNDS  indicates that the task exceeded its
+ *                                       timeout during a previous call to
+ *                                       WatchdogStartItem()
+ * @retval E_WDT_ERR_WATCHDOG_NOT_INIT   indicates that the watchdog framework
+ *                                       has not been initialized
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+error_t WatchdogStartItem(void);
+
+/**
+ * @brief Indicate a task has completed working on an item
+ *
+ * Informs the watchdog framework that the task has completed working on a
+ * previously submitted item.
+ *
+ * @pre WatchdogInit() must have been previously called.
+ * @pre WatchdogTaskMonitor() must have been called to register the task to
+ *      be monitored.
+ * @pre WatchdogAddItem() or WatchdogAddItemFromISR() must have been called
+ *      such that it appears to the watchdog framework that there is work queued
+ *      for the task.
+ *
+ * @param[in] ID  ID of the task that is completing work on an item
+ *
+ * @return Error Code
+ *
+ * @retval E_SUCCESS                     indicates that the watchdog framework
+ *                                       has been successfully informed
+ * @retval E_WDT_ERR_NO_TASK             indicates that this is being called
+ *                                       from a task that has not been
+ *                                       registered to be monitored or that the
+ *                                       ID is not a valid ID
+ * @retval E_WDT_ERR_NO_WORK             indicates that no items have been added
+ *                                       to indicate that there is actually work
+ *                                       to do
+ * @retval E_WDT_ERR_SEQUNECE            indicates that there was no intervening
+ *                                       WatchdogStartItem() after a previous
+ *                                       call to WatchdogCompleteItem()
+ * @retval E_WDT_ERR_TASK_OUT_OF_BOUNDS  indicates that the task exceeded its
+ *                                       timeout during a previous call to
+ *                                       WatchdogStartItem()
+ * @retval E_WDT_ERR_WATCHDOG_NOT_INIT   indicates that the watchdog framework
+ *                                       had not been initialized
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+error_t WatchdogTaskCompleteItem(WatchdogTaskID ID);
+
+/**
+ * @brief Indicate that current task has completed working on an item
+ *
+ * Informs the watchdog framework that the current task has completed working
+ * on a previously submitted item.
+ *
+ * This function must be called from a non-interrupt context.
+ *
+ * @pre WatchdogInit() must have been previously called.
+ * @pre WatchdogTaskMonitor() must have been called to register the task to
+ *      be monitored.
+ * @pre WatchdogTaskStartItem() or WatchdogStartItem() must have been previously
+ *      called with no other intervening calls to WatchdogTaskCompleteItem() or
+ *      WatchdogCompleteItem().
+ *
+ * @return Error Code
+ *
+ * @retval E_SUCCESS                     indicates that the watchdog framework
+ *                                       has been successfully informed
+ * @retval E_WDT_ERR_NO_TASK             indicates that this is being called
+ *                                       from a task that has not been
+ *                                       registered to be monitored
+ * @retval E_WDT_ERR_NO_WORK             indicates that no items have been added
+ *                                       to indicate that there is actually work
+ *                                       to do
+ * @retval E_WDT_ERR_SEQUNECE            indicates that there was no intervening
+ *                                       WatchdogStartItem() after a previous
+ *                                       call to WatchdogCompleteItem()
+ * @retval E_WDT_ERR_TASK_OUT_OF_BOUNDS  indicates that the task exceeded its
+ *                                       timeout during a previous call to
+ *                                       WatchdogStartItem()
+ * @retval E_WDT_ERR_WATCHDOG_NOT_INIT   indicates that the watchdog framework
+ *                                       had not been initialized
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+error_t WatchdogCompleteItem(void);
+
+/**
+ * @brief Check the state of all tasks being monitored
+ *
+ * Checks the state of all the tasks being monitored by the watchdog framework
+ * and return the overall state.
+ *
+ * This function must be called from a non-interrupt context.
+ *
+ * @pre WatchdogInit() must have been previously called.
+ * @pre WatchdogTaskMonitor() must have been called to register the task to
+ *      be monitored.
+ *
+ * @return Error Code
+ *
+ * @retval E_SUCCESS                     indicates that all tasks are within
+ *                                       their watchdog parameters
+ * @retval E_WDT_ERR_TASK_OUT_OF_BOUNDS  indicates that one or more tasks are
+ *                                       outside of the bounds specified
+ * @retval E_WDT_ERR_WATCHDOG_NOT_INIT   indicates that the watchdog framework
+ *                                       has not been initialized
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+error_t WatchdogCheckStatus(void);
+
+/**
+ * @brief Check the status of a particular task being monitored
+ *
+ * Checks the state of a particular task that is being monitored by the watchdog
+ * framework and return its state.
+ *
+ * This function will not invoke the callback WatchdogCallbackTaskOutOfBounds().
+ *
+ * This function must be called from a non-interrupt context.
+ *
+ * @pre WatchdogInit() must have been previously called.
+ * @pre WatchdogTaskMonitor() must have been called to register the task to
+ *      be monitored.
+ *
+ * @param[in] ID  ID of the task whose state is to be returned
+ *
+ * @return Error Code
+ *
+ * @return E_SUCCESS                     indicates that the task is within its
+ *                                       specified bounds
+ *         E_WDT_ERR_NO_TASK             indicates that the task ID does not
+ *                                       correspond to a monitored task
+ *         E_WDT_ERR_TASK_OUT_OF_BOUNDS  indicates that the task's execution
+ *                                       time exceeded it's specified timeout.
+ *         E_WDT_ERR_WATCHDOG_NOT_INIT   indicates that the watchdog framework
+ *                                       has not been initialized
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+error_t WatchdogCheckTaskStatus(const WatchdogTaskID ID);
+
+/**
+ * @brief Map an RTOS task ID to a watchdog task ID
+ *
+ * Maps an RTOS task ID to a watchdog task ID which is used by all other
+ * watchdog APIs.
+ *
+ * @pre WatchdogInit() must have been previously called.
+ * @pre WatchdogTaskMonitor() must have been called to register the task to
+ *      be monitored.
+ *
+ * @param[in]     taskID  handle to an RTOS task
+ * @param[in,out] pID     pointer to a variable that will be filled in which
+ *                        represents the watchdog task ID for the indicated
+ *                        RTOS task
+ *
+ * @return Error Code
+ *
+ * @retval E_SUCCESS                    indicates that the variable that is
+ *                                      pointed to by pID will be set to the
+ *                                      watchdog task ID for the RTOS task
+ * @retval E_WDT_ERR_NO_TASK            indicates that taskID does not map to a
+ *                                      known watchdog task ID
+ * @retval E_WDT_ERR_NULL_PTR           indicates that pID is NULL
+ * @retval E_WDT_ERR_WATCHDOG_NOT_INIT  indicates that the watchdog framework
+ *                                      has not been initialized
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+error_t WatchdogGetTaskID(const rtosTaskHandle taskID,
+                          WatchdogTaskID *pID);
+
+/**
+ * @brief Return maximum task ID in use
+ *
+ * Returns the maximum monitored task ID that is in use.
+ *
+ * @pre WatchdogInit() must have been previously called.
+ * @pre WatchdogTaskMonitor() must have been called to register the task to
+ *      be monitored.
+ *
+ * @param[in,out]  pNumTaskIDs  pointer to a variable that will be set to the
+ *                              maximum number of monitored task IDs
+ *
+ * @return Error Code
+ *
+ * @retval E_SUCCESS variable set with maximum number of monitored task IDs
+ * @retval E_WDT_ERR_NULL_PTR pNumTaskIDs is NULL
+ * @retval E_WDT_ERR_WATCHDOG_NOT_INIT indicates that the watchdog framework
+ *                                     has not been initialized
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+error_t WatchdogGetNumTaskIDs(uint32_t *pNumTaskIDs);
+
+/**
+ * @brief Callback when a task is "out of bounds"
+ *
+ * Called by the watchdog framework when a task fails to make sufficient
+ * progress.  This will only be called during the operation of the functions
+ * WatchdogCheckStatus() and WatchdogCompleteItem().
+ *
+ * This function is provided by the application (usually the task that
+ * is petting the watchdog hardware and calling WatchdogCheckStatus()).
+ *
+ * A "weak" version of this function is provided by the watchdog framework for
+ * the case when the application does not wish to provide a callback.  In that
+ * situation, the callback will cause a fatal abort.
+ *
+ * @pre WatchdogInit() must have been previously called.
+ * @pre WatchdogTaskMonitor() must have been called to register the task to
+ *      be monitored.
+ *
+ * @parm[in] ID  the ID of the task that failed to make progress.
+ *
+ * @return Error Code
+ *
+ * @retval E_SUCCESS       indicates that the framework should continue reporting
+ *                         other tasks that are "out of bounds"
+ * @retval E_WDT_ERR_DONE  indicates that the framework should not report any
+ *                         additional tasks that are "out of bounds" during the
+ *                         current invokation of WatchdogCheckStatus().
+ *
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+error_t WatchdogCallbackTaskOutOfBounds(WatchdogTaskID ID);
+
+/**
+ * @brief Callback to perform other checks
+ *
+ * Called when the watchdog task has determined that all tasks are operating
+ * properly.  It allows an application to perform it's own internal checks and
+ * if those checks fail, prevent the watchdog task from "petting" the watchdog
+ * hardware by returning E_WDT_ERR_NO_PET.
+ *
+ * This function is provided by the application.  This function will execute
+ * within the context of the watchdog task.
+ *
+ * A "weak" version of this function is provided by the watchdog task for the
+ * case when the application does not wish to provide a callback.  In that
+ * situation, the callback will return E_SUCCESS.
+ *
+ * @pre WatchdogInit() must have been previously called.
+ * @pre WatchdogTaskMonitor() must have been called to register the task to
+ *      be monitored.
+ *
+ * @return Error Code
+ *
+ * @retval E_SUCCESS         indicates that the watchdog hardware should be "pet"
+ * @retval E_WDT_ERR_NO_PET  indicates that the watchdog hardware should not
+ *                           be "pet"
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+error_t WatchdogCallbackApplicationCheck(void);
+
+/**
+ * @brief Return Watchdog Statistics for a Task
+ *
+ * This function will return the statistics structure that represents the
+ * statistics that have been collected by the watchdog framework about the
+ * task.
+ *
+ * If the watchdog framework has not been configured to collect statistics
+ * then this function will return an error.
+ *
+ * @pre WatchdogInit() must have been previously called.
+ * @pre WatchdogTaskMonitor() must have been called to register the task to
+ *      be monitored.
+ *
+ * @param[in] ID        the ID of the task whose statistics are to be returned
+ * @param[in] stats     a pointer to a WatchdogTaskStatistics structure to be
+ *                      filled in.
+ *
+ * @return Error Code
+ *
+ * @retval E_SUCCESS    indicates that the statistics were returned
+ * @retval E_WDT_ERR_NO_TASK            indicates that taskID does not map to a
+ *                                      known watchdog task ID
+ * @retval E_WDT_ERR_NULL_PTR           indicates that pID is NULL
+ * @retval E_WDT_ERR_WATCHDOG_NOT_INIT  indicates that the watchdog framework
+ *                                      has not been initialized
+ * @retval E_WDT_ERR_NO_STATS           statistics has not been configured
+ */
+INLINE_RFD(MISRA, DEVIATE, Rule_8_6, "Approval: JIRA TID-338, DR: SWE-FSP-008-SWSADR.docx")
+error_t WatchdogGetTaskStatistics(const WatchdogTaskID ID,
+                                  WatchdogTaskStatistics *stats);
+
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+#endif
diff --git a/spe-freertos-bsp/fsp/source/include/watchdog/wdt-tegra-priv.h b/spe-freertos-bsp/fsp/source/include/watchdog/wdt-tegra-priv.h
new file mode 100644
index 0000000..3f2ec1a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/watchdog/wdt-tegra-priv.h
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef WATCHDOG__WDT_TEGRA_PRIV_H
+#define WATCHDOG__WDT_TEGRA_PRIV_H
+#define FSP__WATCHDOG__WDT_TEGRA_PRIV_H                 1
+
+/**
+ * @file watchdog/wdt-tegra-priv.h
+ * @brief Structures that are internal to the WDT driver
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/attributes.h>               // for FSP_ALIGNOF
+#include <misc/macros.h>                   // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+
+/* Module-specific FSP headers */
+#include <watchdog/tegra-safe-wdt.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Rule_19_2, "Approval: Bug 200543136, DR: SWE-FSP-033-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__TEGRA_SAFE_WDT_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+/**
+ * @brief Watchdog ID Structure
+ *
+ * Structure the describes the implementation of a particular
+ * watchdog timer instance.
+ */
+struct tegra_wdt_id
+{
+    const char      *devname;           ///! Name of watchdog timer instance
+    uint32_t        base_addr;          ///! Base address of watchdog timer
+    uint32_t        irq;                ///! IRQ vector number for watchdog timer
+    uint32_t        fiq;                ///! FIQ vector number for watchdog timer
+};
+
+/**
+ * @brief Watchdog Timer Structure
+ *
+ * Structure that is used by the watchdog driver to manage the watchdog
+ * timer instance during run-time.
+ */
+struct tegra_wdt
+{
+    struct tegra_wdt_id         id;                     ///! Watchdog ID
+    tegra_wdt_callback          irq_callback;           ///! function to call
+                                                        ///!  on IRQ
+    void                        *irq_data;              ///! data to supply to
+                                                        ///!  irq_callback
+    tegra_wdt_callback          fiq_callback;           ///! function to call
+                                                        ///!  on FIQ
+    void                        *fiq_data;              ///! data to supply to
+                                                        ///!  fiq_callback
+    bool                        irq_ack_by_callback;    ///! ack IRQ in
+                                                        ///!  irq_callback, else
+                                                        ///!  ack in tegra_wdt_irq
+    bool                        fiq_ack_by_callback;    ///! ack FIQ in
+                                                        ///!  irq_callback, else
+                                                        ///!  ack in tegra_wdt_fiq
+    bool                        challenge_response;     ///! updates to watchdog
+                                                        ///!  timer requires a
+                                                        ///!  challenge /
+                                                        ///!  response
+    uint8_t                     pad;
+};
+
+/**
+ * Converts const struct tegra_wdt_id * to uint32_t.
+ *
+ * @param[in] input const struct tegra_wdt_id pointer which will be coverted to uint32_t
+ * @param[out] output uint32_t from const struct tegra_wdt_id pointer
+ */
+static inline uint32_t fsp_c_wdtid_ptr_to_u32(const struct tegra_wdt_id *input)
+{
+CT_ASSERT(FSP_ALIGNOF(const struct tegra_wdt_id *) >= FSP_ALIGNOF(uint32_t), "ASSERT due to data misalignment.")
+    CT_ASSERT(sizeof(const struct tegra_wdt_id *) == sizeof(uint32_t), "ASSERT due to incompatible pointer sizes.")
+    union cast_fsp_c_wdtid_ptr_to_u32 {
+        const struct tegra_wdt_id *input;
+        uint32_t output;
+    };
+    union cast_fsp_c_wdtid_ptr_to_u32 t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts uint32_t to const struct tegra_wdt *.
+ *
+ * @param[in] input uint32_t which will be converted to struct tegra_wdt pointer
+ * @param[out] output const struct tegra_wdt pointer from uint32_t
+ */
+static inline const struct tegra_wdt *fsp_u32_to_c_wdt_ptr(uint32_t input)
+{
+CT_ASSERT(FSP_ALIGNOF(uint32_t) >= FSP_ALIGNOF(const struct tegra_wdt *), "ASSERT due to data misalignment.")
+    CT_ASSERT(sizeof(uint32_t) == sizeof(const struct tegra_wdt *), "ASSERT due to incompatible pointer sizes.")
+    union cast_fsp_u32_to_c_wdt_ptr {
+        uint32_t input;
+        const struct tegra_wdt *output;
+    };
+    union cast_fsp_u32_to_c_wdt_ptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts const struct tegra_wdt * to struct tegra_wdt.
+ *
+ * @param[in] input const struct tegra_wdt which will be converted to struct tegra_wdt pointer
+ * @param[out] output struct tegra_wdt pointer from const struct tegra_wdt
+ */
+static inline struct tegra_wdt *fsp_c_wdt_ptr_to_wdt_ptr(const struct tegra_wdt *input)
+{
+CT_ASSERT(FSP_ALIGNOF(const struct tegra_wdt *) >= FSP_ALIGNOF(struct tegra_wdt *), "ASSERT due to data misalignment.")
+    CT_ASSERT(sizeof(const struct tegra_wdt *) == sizeof(struct tegra_wdt *), "ASSERT due to incompatible pointer sizes.")
+    union cast_fsp_c_wdt_ptr_to_wdt_ptr {
+        const struct tegra_wdt *input;
+        struct tegra_wdt *output;
+    };
+    union cast_fsp_c_wdt_ptr_to_wdt_ptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+/**
+ * Converts const struct tegra_wdt_id * to void *.
+ *
+ * @param[in] input const struct tegra_wdt_id which will be converted to void pointer
+ * @param[out] output void pointer from const struct tegra_wdt_id
+ */
+static inline void *fsp_c_wdtid_ptr_to_v_ptr(const struct tegra_wdt_id *input)
+{
+CT_ASSERT(FSP_ALIGNOF(const struct tegra_wdt_id *) >= FSP_ALIGNOF(void *), "ASSERT due to data misalignment.")
+    CT_ASSERT(sizeof(const struct tegra_wdt_id *) == sizeof(void *), "ASSERT due to incompatible pointer sizes.")
+    union cast_fsp_c_wdtid_ptr_to_v_ptr {
+        const struct tegra_wdt_id *input;
+        void *output;
+    };
+    union cast_fsp_c_wdtid_ptr_to_v_ptr t;
+
+    t.input = input;
+    return t.output;
+}
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_19_2, "Approval: Bug 200543136, DR: SWE-FSP-033-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+#endif  /* FSP_WATCHDOG_WDT_TEGRA_PRIV_H */
diff --git a/spe-freertos-bsp/fsp/source/include/watchdog/wdt-tegra.h b/spe-freertos-bsp/fsp/source/include/watchdog/wdt-tegra.h
new file mode 100644
index 0000000..64a73b1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/include/watchdog/wdt-tegra.h
@@ -0,0 +1,295 @@
+/*
+ * Copyright (c) 2015-2021 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef WATCHDOG__WDT_TEGRA_H
+#define WATCHDOG__WDT_TEGRA_H
+#define FSP__WATCHDOG__WDT_TEGRA_H                      1
+
+/**
+ * @file wdt-tegra.h
+ * @brief Compatibility header for WDT driver
+ */
+
+/* Compiler headers */
+#include <stdint.h>                     // IWYU pragma: no_include <errno.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>
+
+/* Module-specific FSP headers */
+#include <watchdog/tegra-safe-wdt.h>
+#include <watchdog/wdt-tegra-priv.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__TEGRA_SAFE_WDT_H, "Header file missing or invalid")
+CT_ASSERT(FSP__WATCHDOG__WDT_TEGRA_PRIV_H, "Header file missing or invalid")
+
+// IWYU pragma: no_forward_declare tegra_wdt_id
+
+/*
+ * Tegra WDT driver
+ *
+ * To use WDT driver,
+ * 1. Call tegra_wdt_setup to setup watchdog timer first
+ * 2. Call tegra_wdt_start to enable watchdog timer
+ *
+ * The wdt driver IRQ/FIQ handler will ack the watchdog automatically. If
+ * you want to do it from the callback or from a scheduld task, set
+ * irq_ack_by_callback/fiq_ack_by_callback.
+ */
+
+/**
+ * @brief Initialize watchdog timer
+ *
+ * This function will initialize the specified watchdog timer according to
+ * the configuration parameters supplied.
+ *
+ * @note This function can only be called if the specified watchdog timer
+ * is disabled.  If the specified watchdog timer is enabled, then it is
+ * necessary to call either tegra_wdt_stop() or tegra_wdt_stop_from_isr()
+ * to first stop the watchdog timer.
+ *
+ * This function must be called from a non-interrupt context.
+ *
+ * @pre The specified watchdog timer must not be running.
+ *
+ * @param[in]  id    pointer to the tegra_wdt_id structure that represents
+ *                   the watchdog timer being setup
+ * @param[in]  conf  pointer to the tegra_wdt_conf structure that contains
+ *                   the configuration parameters to be used when initializing
+ *                   the watchdog timer.
+ *
+ * @return Error Code
+ *
+ * @retval E_SUCCESS                    watchdog timer was successfully
+ *                                      initialized
+ * @retval E_WDT_ERR_IRQ_CONFIG         The watchdog's IRQ or FIQ was
+ *                                      enabled but no corresponding
+ *                                      callback function was specified
+ * @retval E_WDT_ERR_TMRSRC_INVALID     value specified for tmrsrc was invalid
+ * @retval E_WDT_ERR_THRESHOLD_INVALID  value specified for threshold was
+ *                                      invalid
+ */
+static inline error_t
+tegra_wdt_setup(const struct tegra_wdt_id *id,
+                const struct tegra_wdt_conf *conf)
+{
+    return tegra_safe_wdt_setup(fsp_c_wdtid_ptr_to_v_ptr(id), conf);
+}
+
+/**
+ * @brief Start Watchdog Timer
+ *
+ * This function will start the specified watchdog timer using the parameters
+ * that were supplied as part of tegra_wdt_setup().
+ *
+ * This function can be called from either an interrupt context or a
+ * non-interrupt context.
+ *
+ * @pre The function tegra_wdt_setup() must have been previously called.
+ *
+ * @param[in]  id  pointer to the tegra_wdt_id structure that represents the
+ *                 watchdog timer being started.
+ *
+ * @return None
+ */
+static inline void
+tegra_wdt_start(const struct tegra_wdt_id *id)
+{
+    (void)tegra_safe_wdt_start(id);
+}
+
+/**
+ * @brief Acknowlege Watchdog Timer
+ *
+ * This function will acknowlege the specified watchdog timer and
+ * reset its operation so that it will restart its count.
+ *
+ * This function can be called from either an interrupt context or a
+ * non-interrupt context.
+ *
+ * @rep tegra_wdt_setup() must have been previously called.
+ */
+static inline void
+tegra_wdt_ack(const struct tegra_wdt_id *id)
+{
+    (void)tegra_safe_wdt_ack(id);
+}
+
+/**
+ * @brief Stop watchdog timer
+ *
+ * This function will stop the specified watchdog timer.  It will stop it
+ * from counting and thus prevent it from generating an IRQ or FIQ from the
+ * watchdog timer.
+ *
+ * This function must be called from an interrupt context.
+ *
+ * @pre tegra_wdt_setup() must have been previously called.
+ *
+ * @param[in]  id  pointer to the tegra_wdt_id structure that represents the
+ *                 watchdog timer being stopped.
+ *
+ * @return None
+ */
+static inline void
+tegra_wdt_stop_from_isr(const struct tegra_wdt_id *id)
+{
+    (void)tegra_safe_wdt_stop_from_isr(id);
+}
+
+/**
+ * @brief Stop watchdog timer
+ *
+ * This function will stop the specified watchdog timer.  It will stop it
+ * from counting and thus prevent it from generating an IRQ or FIQ from the
+ * watchdog timer.
+ *
+ * This function must be called from a non-interrupt context.
+ *
+ * @pre tegra_wdt_setup() must have been previously called.
+ *
+ * @param[in]  id  pointer to the tegra_wdt_id structure that represents the
+ *                 watchdog timer being stopped.
+ *
+ * @return None
+ */
+static inline void
+tegra_wdt_stop(const struct tegra_wdt_id *id)
+{
+    (void)tegra_safe_wdt_stop(id);
+}
+
+/**
+ * @brief Watchdog timer interrupt handler
+ *
+ * This function is responsible for servicing the watchdog IRQ.  The
+ * behavior of this function is dependent upon how the watchdog timer
+ * was configured.
+ *
+ * This function is called from the first level interrupt handler for
+ * the watchdog interrupt, so it will be called only from an interrupt
+ * context.
+ *
+ * @pre tegra_wdt_setup() must have been previously called.
+ * @pre the watchdog timer must have been previously started
+ *
+ * @param[in]  id  pointer to the tegra_wdt_id structure that represents the
+ *                 watchdog timer that has generated an interrupt.
+ *
+ * @return None
+ */
+static inline void
+tegra_wdt_irq(void *id)
+{
+    (void)tegra_safe_wdt_irq(id);
+}
+
+/**
+ * @brief Watchdog timer fast interrupt handler
+ *
+ * This function is responsible for servicing the watchdog FIQ.  The
+ * behavior of this function is dependent upon how the watchdog timer
+ * was configured.
+ *
+ * This function is called from the first level interrupt handler for
+ * the watchdog fast interrupt, so it will be called only from an interrupt
+ * context.
+ *
+ * @pre tegra_wdt_setup() must have been previously called.
+ * @pre the watchdog timer must have been previously started
+ *
+ * @param[in]  id  pointer to the tegra_wdt_id structure that represents the
+ *                 watchdog timer that has generated an FIQ interrupt.
+ *
+ * @return None
+ */
+static inline void
+tegra_wdt_fiq(void *id)
+{
+    (void)tegra_safe_wdt_fiq(id);
+}
+
+/**
+ * @brief Read watchdog timer status
+ *
+ * This function will return the current status of the specified watchdog
+ * timer.
+ *
+ * This function can be called from either an interrupt context or a
+ * non-interrupt context.
+ *
+ * @pre None
+ *
+ * @return 32-bit value representing the watchdog timer status.  It is
+ *         interpreted as follows:
+ *
+ *   bit 0      Enabled                 1b when the counter is active
+ *
+ *                                      0b when the counter is disabled
+ *
+ *   bit 1      LocalIRQStatus          Current status of interrupt
+ *
+ *   bit 2      LocalFIQStatus          Current status of FIQ
+ *
+ *   bit 3      RemoteInterruptStatus   Current status of remote interrupt
+ *
+ *   bit 11:4   CurrentCount            Current value of the counter
+ *
+ *   bit 14:12  CurrentExpirationCount  Current count of expiration since
+ *                                      last start operation
+ *
+ *   bit 16     CurrentError            Current error reported to HSM
+ */
+static inline uint32_t
+tegra_wdt_read_status(const struct tegra_wdt_id *id)
+{
+    uint32_t    status;
+
+    (void)tegra_safe_wdt_read_status(id, &status);
+
+    return status;
+}
+
+#endif /* WATCHDOG__WDT_TEGRA_H */
diff --git a/spe-freertos-bsp/fsp/source/module-fsp-common-config.mk b/spe-freertos-bsp/fsp/source/module-fsp-common-config.mk
new file mode 100644
index 0000000..3fd2f44
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/module-fsp-common-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-fsp-common-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_FSP_COMMON_CONFIG        := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_FSP_COMMON_DEPENDS       :=
+$(foreach _,$(MODULE_FSP_COMMON_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+FSP_COMMON_INCLUDE               = $(FSP_COMMON_REPO)/include
+MODULE_FSP_COMMON_SOURCE_DIR     =
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_FSP_COMMON_INCLUDES       = -I $(FSP_COMMON_INCLUDE)
diff --git a/spe-freertos-bsp/fsp/source/module-fsp-common.mk b/spe-freertos-bsp/fsp/source/module-fsp-common.mk
new file mode 100644
index 0000000..e4612fb
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/module-fsp-common.mk
@@ -0,0 +1,61 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-fsp-common.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_FSP_COMMON_NAME          := FSP_COMMON
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_FSP_COMMON_DEFINED       := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_FSP_COMMON_DEPENDS       := FSP_COMMON
+$(foreach _,$(CONFIG_FSP_COMMON_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_FSP_COMMON_C_SRC          =
+
+#
+# Assembly source
+MODULE_FSP_COMMON_ASM_SRC        =
+
+#
+# Special C Flags
+MODULE_FSP_COMMON_C_FLAGS        =
+
+#
+# Special ASM Flags
+MODULE_FSP_COMMON_ASM_FLAGS      =
diff --git a/spe-freertos-bsp/fsp/source/soc/cluster/aon/module-cluster-aon-config.mk b/spe-freertos-bsp/fsp/source/soc/cluster/aon/module-cluster-aon-config.mk
new file mode 100644
index 0000000..782aab2
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/cluster/aon/module-cluster-aon-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cluster-aon-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-cluster_*.mk' files.
+MODULE_CLUSTER_CONFIG           := 1
+MODULE_CLUSTER_AON_CONFIG       := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_CLUSTER_DEPENDS          := SOC
+$(foreach _,$(MODULE_CLUSTER_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_CLUSTER_AON_SOURCE_DIR    =
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_CLUSTER_AON_INCLUDES      = -I $(FSP_COMMON_REPO)/include/soc/$(SOC)/$(CLUSTER)
diff --git a/spe-freertos-bsp/fsp/source/soc/cluster/aon/module-cluster-aon.mk b/spe-freertos-bsp/fsp/source/soc/cluster/aon/module-cluster-aon.mk
new file mode 100644
index 0000000..4a7363a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/cluster/aon/module-cluster-aon.mk
@@ -0,0 +1,61 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cluster-aon.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_CLUSTER_AON_NAME         := CLUSTER_AON
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_CLUSTER_DEFINED          := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_CLUSTER_DEPENDS          := CLUSTER_AON CLUSTER
+$(foreach _,$(CONFIG_CLUSTER_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_CLUSTER_AON_C_SRC        =
+
+#
+# Assembly source
+MODULE_CLUSTER_AON_ASM_SRC      =
+
+#
+# Special C Flags
+MODULE_CLUSTER_AON_C_FLAGS      = -DTEGRA_UARTC_ENABLED
+
+#
+# Special ASM Flags
+MODULE_CLUSTER_AON_ASM_FLAGS    =
diff --git a/spe-freertos-bsp/fsp/source/soc/cluster/bpmp/module-cluster-bpmp-config.mk b/spe-freertos-bsp/fsp/source/soc/cluster/bpmp/module-cluster-bpmp-config.mk
new file mode 100644
index 0000000..86607e8
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/cluster/bpmp/module-cluster-bpmp-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cluster-bpmp-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-cluster_*.mk' files.
+MODULE_CLUSTER_CONFIG           := 1
+MODULE_CLUSTER_BPMP_CONFIG      := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_CLUSTER_DEPENDS          := SOC
+$(foreach _,$(MODULE_CLUSTER_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_CLUSTER_BPMP_SOURCE_DIR   =
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_CLUSTER_BPMP_INCLUDES     = -I $(FSP_COMMON_REPO)/include/soc/$(SOC)/$(CLUSTER)
diff --git a/spe-freertos-bsp/fsp/source/soc/cluster/bpmp/module-cluster-bpmp.mk b/spe-freertos-bsp/fsp/source/soc/cluster/bpmp/module-cluster-bpmp.mk
new file mode 100644
index 0000000..cb20005
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/cluster/bpmp/module-cluster-bpmp.mk
@@ -0,0 +1,61 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cluster-bpmp.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_CLUSTER_BPMP_NAME        := CLUSTER_BPMP
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_CLUSTER_DEFINED          := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_CLUSTER_DEPENDS          := CLUSTER_BPMP CLUSTER
+$(foreach _,$(CONFIG_CLUSTER_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_CLUSTER_BPMP_C_SRC        =
+
+#
+# Assembly source
+MODULE_CLUSTER_BPMP_ASM_SRC      =
+
+#
+# Special C Flags
+MODULE_CLUSTER_BPMP_C_FLAGS      =
+
+#
+# Special ASM Flags
+MODULE_CLUSTER_BPMP_ASM_FLAGS    =
diff --git a/spe-freertos-bsp/fsp/source/soc/cluster/dce/module-cluster-dce-config.mk b/spe-freertos-bsp/fsp/source/soc/cluster/dce/module-cluster-dce-config.mk
new file mode 100644
index 0000000..988c121
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/cluster/dce/module-cluster-dce-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cluster-dce-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-cluster_*.mk' files.
+MODULE_CLUSTER_CONFIG           := 1
+MODULE_CLUSTER_DCE_CONFIG       := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_CLUSTER_DEPENDS          := SOC
+$(foreach _,$(MODULE_CLUSTER_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_CLUSTER_DCE_SOURCE_DIR    =
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_CLUSTER_DCE_INCLUDES      = -I $(FSP_COMMON_REPO)/include/soc/$(SOC)/$(CLUSTER)
diff --git a/spe-freertos-bsp/fsp/source/soc/cluster/dce/module-cluster-dce.mk b/spe-freertos-bsp/fsp/source/soc/cluster/dce/module-cluster-dce.mk
new file mode 100644
index 0000000..04367a5
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/cluster/dce/module-cluster-dce.mk
@@ -0,0 +1,61 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cluster-dce.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_CLUSTER_DCE_NAME         := CLUSTER_DCE
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_CLUSTER_DEFINED          := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_CLUSTER_DEPENDS          := CLUSTER_DCE CLUSTER
+$(foreach _,$(CONFIG_CLUSTER_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_CLUSTER_DCE_C_SRC         =
+
+#
+# Assembly source
+MODULE_CLUSTER_DCE_ASM_SRC       =
+
+#
+# Special C Flags
+MODULE_CLUSTER_DCE_C_FLAGS       =
+
+#
+# Special ASM Flags
+MODULE_CLUSTER_DCE_ASM_FLAGS     =
diff --git a/spe-freertos-bsp/fsp/source/soc/cluster/fsi/module-cluster-fsi-config.mk b/spe-freertos-bsp/fsp/source/soc/cluster/fsi/module-cluster-fsi-config.mk
new file mode 100644
index 0000000..bd8d47d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/cluster/fsi/module-cluster-fsi-config.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cluster-fsi-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-cluster_*.mk' files.
+MODULE_CLUSTER_CONFIG           := 1
+MODULE_CLUSTER_FSI_CONFIG       := 1
+
+#
+# Location of source code files
+MODULE_CLUSTER_FSI_SOURCE_DIR    =
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_CLUSTER_FSI_INCLUDES      = -I $(FSP_COMMON_REPO)/include/soc/$(SOC)/$(CLUSTER)
diff --git a/spe-freertos-bsp/fsp/source/soc/cluster/fsi/module-cluster-fsi.mk b/spe-freertos-bsp/fsp/source/soc/cluster/fsi/module-cluster-fsi.mk
new file mode 100644
index 0000000..b2cdca3
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/cluster/fsi/module-cluster-fsi.mk
@@ -0,0 +1,61 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cluster-fsi.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_CLUSTER_FSI_NAME         := CLUSTER_FSI
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_CLUSTER_DEFINED          := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_CLUSTER_DEPENDS          := CLUSTER_FSI CLUSTER
+$(foreach _,$(CONFIG_CLUSTER_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_CLUSTER_FSI_C_SRC         =
+
+#
+# Assembly source
+MODULE_CLUSTER_FSI_ASM_SRC       =
+
+#
+# Special C Flags
+MODULE_CLUSTER_FSI_C_FLAGS       =
+
+#
+# Special ASM Flags
+MODULE_CLUSTER_FSI_ASM_FLAGS     =
diff --git a/spe-freertos-bsp/fsp/source/soc/cluster/rce/module-cluster-rce-config.mk b/spe-freertos-bsp/fsp/source/soc/cluster/rce/module-cluster-rce-config.mk
new file mode 100644
index 0000000..6b5f9bd
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/cluster/rce/module-cluster-rce-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cluster-rce-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-cluster_*.mk' files.
+MODULE_CLUSTER_CONFIG           := 1
+MODULE_CLUSTER_RCE_CONFIG       := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_CLUSTER_DEPENDS          := SOC
+$(foreach _,$(MODULE_CLUSTER_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_CLUSTER_RCE_SOURCE_DIR    =
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_CLUSTER_RCE_INCLUDES      = -I $(FSP_COMMON_REPO)/include/soc/$(SOC)/$(CLUSTER)
diff --git a/spe-freertos-bsp/fsp/source/soc/cluster/rce/module-cluster-rce.mk b/spe-freertos-bsp/fsp/source/soc/cluster/rce/module-cluster-rce.mk
new file mode 100644
index 0000000..396db80
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/cluster/rce/module-cluster-rce.mk
@@ -0,0 +1,61 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cluster-rce.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_CLUSTER_RCE_NAME         := CLUSTER_RCE
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_CLUSTER_DEFINED          := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_CLUSTER_DEPENDS          := CLUSTER_RCE CLUSTER
+$(foreach _,$(CONFIG_CLUSTER_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_CLUSTER_RCE_C_SRC         =
+
+#
+# Assembly source
+MODULE_CLUSTER_RCE_ASM_SRC       =
+
+#
+# Special C Flags
+MODULE_CLUSTER_RCE_C_FLAGS       =
+
+#
+# Special ASM Flags
+MODULE_CLUSTER_RCE_ASM_FLAGS     =
diff --git a/spe-freertos-bsp/fsp/source/soc/cluster/sce/module-cluster-sce-config.mk b/spe-freertos-bsp/fsp/source/soc/cluster/sce/module-cluster-sce-config.mk
new file mode 100644
index 0000000..4b92b1c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/cluster/sce/module-cluster-sce-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cluster-sce-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-cluster_*.mk' files.
+MODULE_CLUSTER_CONFIG           := 1
+MODULE_CLUSTER_SCE_CONFIG       := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_CLUSTER_DEPENDS          := SOC
+$(foreach _,$(MODULE_CLUSTER_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_CLUSTER_SCE_SOUSCE_DIR    =
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_CLUSTER_SCE_INCLUDES      = -I $(FSP_COMMON_REPO)/include/soc/$(SOC)/$(CLUSTER)
diff --git a/spe-freertos-bsp/fsp/source/soc/cluster/sce/module-cluster-sce.mk b/spe-freertos-bsp/fsp/source/soc/cluster/sce/module-cluster-sce.mk
new file mode 100644
index 0000000..25cb762
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/cluster/sce/module-cluster-sce.mk
@@ -0,0 +1,61 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cluster-sce.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_CLUSTER_SCE_NAME         := CLUSTER_SCE
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_CLUSTER_DEFINED          := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_CLUSTER_DEPENDS          := CLUSTER_SCE CLUSTER
+$(foreach _,$(CONFIG_CLUSTER_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_CLUSTER_SCE_C_SRC         =
+
+#
+# Assembly source
+MODULE_CLUSTER_SCE_ASM_SRC       =
+
+#
+# Special C Flags
+MODULE_CLUSTER_SCE_C_FLAGS       =
+
+#
+# Special ASM Flags
+MODULE_CLUSTER_SCE_ASM_FLAGS     =
diff --git a/spe-freertos-bsp/fsp/source/soc/cluster/spe/module-cluster-spe-config.mk b/spe-freertos-bsp/fsp/source/soc/cluster/spe/module-cluster-spe-config.mk
new file mode 100644
index 0000000..ce4dd27
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/cluster/spe/module-cluster-spe-config.mk
@@ -0,0 +1,42 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cluster-spe-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-cluster_*.mk' files.
+MODULE_CLUSTER_CONFIG               := 1
+MODULE_CLUSTER_SPE_CONFIG           := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_CLUSTER_DEPENDS              := SOC
+$(foreach _,$(MODULE_CLUSTER_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Location of source code files
+MODULE_CLUSTER_SPE_SOURCE_DIR        =
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_CLUSTER_SPE_INCLUDES          = -I $(FSP_COMMON_REPO)/include/soc/$(SOC)/$(CLUSTER)
diff --git a/spe-freertos-bsp/fsp/source/soc/cluster/spe/module-cluster-spe.mk b/spe-freertos-bsp/fsp/source/soc/cluster/spe/module-cluster-spe.mk
new file mode 100644
index 0000000..3f2f16e
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/cluster/spe/module-cluster-spe.mk
@@ -0,0 +1,61 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cluster-spe.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_CLUSTER_SPE_NAME         := CLUSTER_SPE
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_CLUSTER_DEFINED          := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_CLUSTER_DEPENDS          := CLUSTER_SPE CLUSTER
+$(foreach _,$(CONFIG_CLUSTER_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_CLUSTER_SPE_C_SRC         =
+
+#
+# Assembly source
+MODULE_CLUSTER_SPE_ASM_SRC       =
+
+#
+# Special C Flags
+MODULE_CLUSTER_SPE_C_FLAGS       =
+
+#
+# Special ASM Flags
+MODULE_CLUSTER_SPE_ASM_FLAGS     =
diff --git a/spe-freertos-bsp/fsp/source/soc/cluster/tsec/module-cluster-tsec-config.mk b/spe-freertos-bsp/fsp/source/soc/cluster/tsec/module-cluster-tsec-config.mk
new file mode 100644
index 0000000..54cb1ba
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/cluster/tsec/module-cluster-tsec-config.mk
@@ -0,0 +1,35 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cluster-tsec-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-cluster_*.mk' files.
+MODULE_CLUSTER_CONFIG               := 1
+MODULE_CLUSTER_TSEC_CONFIG          := 1
+
+#
+# Location of source code files
+MODULE_CLUSTER_TSEC_SOURCE_DIR       =
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_CLUSTER_TSEC_INCLUDES         = -I $(FSP_COMMON_REPO)/include/soc/$(SOC)/$(CLUSTER)
diff --git a/spe-freertos-bsp/fsp/source/soc/cluster/tsec/module-cluster-tsec.mk b/spe-freertos-bsp/fsp/source/soc/cluster/tsec/module-cluster-tsec.mk
new file mode 100644
index 0000000..4b0d321
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/cluster/tsec/module-cluster-tsec.mk
@@ -0,0 +1,61 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-cluster-tsec.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_CLUSTER_TSEC_NAME        := CLUSTER_TSEC
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_CLUSTER_DEFINED          := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_CLUSTER_DEPENDS          := CLUSTER_TSEC CLUSTER
+$(foreach _,$(CONFIG_CLUSTER_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_CLUSTER_TSEC_C_SRC        =
+
+#
+# Assembly source
+MODULE_CLUSTER_TSEC_ASM_SRC      =
+
+#
+# Special C Flags
+MODULE_CLUSTER_TSEC_C_FLAGS      =
+
+#
+# Special ASM Flags
+MODULE_CLUSTER_TSEC_ASM_FLAGS    =
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/aodmic-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/aodmic-tegra-ids.c
new file mode 100644
index 0000000..79575e7
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/aodmic-tegra-ids.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>            // for CT_ASSERT
+
+/* Hardware headers */
+#include <address_map_new.h>           // for NV_ADDRESS_MAP_DMIC5_BASE
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>        // for INTERRUPT_DMIC
+#include <misc/macros.h>               // for END_RFD_BLOCK, START_RFD_BLOCK
+
+/* Module-specific FSP headers */
+#include <aodmic/sections-aodmic.h>    // for SECTION_AODMIC_...
+#include <aodmic/tegra-aodmic-priv.h>  // for tegra_aodmic_ctlr
+#include <port/aodmic-port.h>          // for aodmic_port_clk_rst_aon
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__HW_CONFIG__VIC_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__AODMIC__TEGRA_AODMIC_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PORT__AODMIC_PORT_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+SECTION_AODMIC_DATA
+struct tegra_aodmic_ctlr tegra_aodmic_ctlr_aon = {
+    .id = {
+        .base_addr = NV_ADDRESS_MAP_DMIC5_BASE,
+        .aodmic_hw_handle = &aodmic_port_clk_rst_aon,
+        .irq       = INTERRUPT_DMIC,
+    },
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/ast-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/ast-tegra-ids.c
new file mode 100644
index 0000000..e4e96fb
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/ast-tegra-ids.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+const uint32_t ast_tegra_id[] = {
+    NV_ADDRESS_MAP_AON_AST_0_BASE,
+    NV_ADDRESS_MAP_AON_AST_1_BASE
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/comb-uart-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/comb-uart-ids.c
new file mode 100644
index 0000000..82186b2
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/comb-uart-ids.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                       // for UINT32_MAX, UINT8_MAX
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>               // for CT_ASSERT
+#include <soc-common/hw-const.h>          /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>              // for NV_ADDRESS_MAP_AON_HSP_SM_BASE
+
+/* Late FSP headers */
+#include <comb-uart/comb-uart-priv.h>     // for comb_uart_id, FSP__HSP__HSP...
+#include <comb-uart/sections-comb-uart.h> // Immune from CT_ASSERT protection
+
+SECTION_COMB_UART_DATA
+const struct comb_uart_id comb_uart_id_aon = {
+    .tx_sm_reg   = 0UL,
+    .rx_sm_reg   = 0UL,
+    .supports_rx = false,
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/gpcdma-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/gpcdma-ids.c
new file mode 100644
index 0000000..78b3627
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/gpcdma-ids.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                 // for CT_ASSERT
+#include <soc-common/hw-const.h>            /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>                // for NV_ADDRESS_MAP_AON_DMA_BASE
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>             // for INTERRUPT_DMA...
+#include <soc-common/clk-tegra-hw.h>        // for tegra_rst_aon_gpcdma
+#include <gpcdma/gpcdma-priv.h>             // for struct gpcdma_id, gpcdma_channel
+#include <gpcdma/sections-gpcdma.h>         // Immune from CT_ASSERT
+#include <port/gpcdma-port-priv.h>          // Immune from CT_ASSERT
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/macros.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HW_CONFIG__VIC_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__CLK_TEGRA_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPCDMA__GPCDMA_PRIV_H, "Header file missing or invalid.")
+
+SECTION_GPCDMA_RODATA
+const struct gpcdma_hw_handle gpcdma_hw_handle_aon = {
+    .rst = tegra_rst_aon_gpcdma,
+};
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan0;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan1;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan2;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan3;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan4;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan5;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan6;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan7;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_id gpcdma_id_aon = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_AON_DMA_BASE,
+        .irqs = {
+            [0] = INTERRUPT_DMA0,
+            [1] = INTERRUPT_DMA1,
+            [2] = INTERRUPT_DMA2,
+            [3] = INTERRUPT_DMA3,
+            [4] = INTERRUPT_DMA4,
+            [5] = INTERRUPT_DMA5,
+            [6] = INTERRUPT_DMA6,
+            [7] = INTERRUPT_DMA7,
+        },
+        .hw_handle = &gpcdma_hw_handle_aon,
+    },
+    .channels = {
+        [0] = &gpcdma_chan0,
+        [1] = &gpcdma_chan1,
+        [2] = &gpcdma_chan2,
+        [3] = &gpcdma_chan3,
+        [4] = &gpcdma_chan4,
+        [5] = &gpcdma_chan5,
+        [6] = &gpcdma_chan6,
+        [7] = &gpcdma_chan7,
+    },
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/gpio-aon-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/gpio-aon-tegra-ids.c
new file mode 100644
index 0000000..053963e
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/gpio-aon-tegra-ids.c
@@ -0,0 +1,99 @@
+/*
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/* Compiler headers */
+#include <stdint.h>                                  // for uint32_t, ...
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                          // for CT_ASSERT
+
+/* Hardware headers */
+#include <address_map_new.h>                         // for NV_ADDRESS_MAP_AON_GPIO_0_BASE, NV_ADDRESS_MAP_GPIO_CTL0_BASE
+#include <argpio_aon_sw.h>                           // for GPIO_AA_ENABLE_CONFIG_00_0, ...
+
+/* Late FSP headers */
+#include <misc/macros.h>                             // for ARRAY_SIZE
+
+/* Module-specific FSP headers */
+#include <gpio/tegra-gpio-priv.h>                    // for struct gpio_irq_handler
+#include <processor/tegra-gpio-hw-params.h>          // for TEGRA_AON_GPIO_IRQ, TEGRA_GPIO_IRQ_STATUS_REG, ...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPIO__TEGRA_GPIO_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__GPIO_TEGRA_HW_PARAMS_H, "Header file missing or invalid.")
+
+#define TEGRA_GPIO_IRQ_STATUS_REG       (GPIO_AA_INTERRUPT_STATUS_G4_0 - \
+                                         GPIO_AA_ENABLE_CONFIG_00_0)
+
+static const uint32_t tegra_gpio_aon_bases[] = {
+    GPIO_AA_ENABLE_CONFIG_00_0,
+    GPIO_BB_ENABLE_CONFIG_00_0,
+    GPIO_CC_ENABLE_CONFIG_00_0,
+    GPIO_DD_ENABLE_CONFIG_00_0,
+    GPIO_EE_ENABLE_CONFIG_00_0,
+    GPIO_GG_ENABLE_CONFIG_00_0,
+};
+
+static struct gpio_irq_handler tegra_gpio_aon_handlers[
+                               ARRAY_SIZE(tegra_gpio_aon_bases) *
+                               GPIOS_PER_BANK];
+
+static uint32_t tegra_aon_gpio_id_irqs[] = {
+    TEGRA_AON_GPIO_IRQ,
+};
+
+static uint8_t aon_bank_irq_status[ARRAY_SIZE(tegra_gpio_aon_bases)] = {0};
+
+/* Number of pins per bank are captured by manual inspection of HW manuals */
+static const uint8_t num_pins_per_bank[ARRAY_SIZE(tegra_gpio_aon_bases)] = {8, 4, 8, 3, 8, 1};
+
+struct tegra_gpio_id tegra_gpio_id_aon = {
+    .base_addr         = NV_ADDRESS_MAP_AON_GPIO_0_BASE,
+    .bank_count        = ARRAY_SIZE(tegra_gpio_aon_bases),
+    .bank_bases        = tegra_gpio_aon_bases,
+    .irqs              = tegra_aon_gpio_id_irqs,
+    .nirqs             = ARRAY_SIZE(tegra_aon_gpio_id_irqs),
+    .irq_handlers      = tegra_gpio_aon_handlers,
+    .irq_status_offset = TEGRA_GPIO_IRQ_STATUS_REG,
+    .bank_irq_status   = aon_bank_irq_status,
+    .isr_status        = true,
+    .num_pins          = num_pins_per_bank,
+};
+
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/gpio-main-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/gpio-main-tegra-ids.c
new file mode 100644
index 0000000..a0e679f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/gpio-main-tegra-ids.c
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/* Compiler headers */
+#include <stdint.h>                                  // for uint32_t, ...
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                          // for CT_ASSERT
+
+/* Hardware headers */
+#include <address_map_new.h>                         // for NV_ADDRESS_MAP_AON_GPIO_0_BASE, NV_ADDRESS_MAP_GPIO_CTL0_BASE
+#include <argpio_sw.h>                               // for GPIO_A_ENABLE_CONFIG_00_0, ....
+
+/* Late FSP headers */
+#include <misc/macros.h>                             // for ARRAY_SIZE
+
+/* Module-specific FSP headers */
+#include <gpio/tegra-gpio-priv.h>                    // for struct gpio_irq_handler
+#include <processor/tegra-gpio-hw-params.h>          // for TEGRA_MAIN_GPIO_ID0_IRQ, TEGRA_GPIO_IRQ_STATUS_REG, ...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPIO__TEGRA_GPIO_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__GPIO_TEGRA_HW_PARAMS_H, "Header file missing or invalid.")
+
+#define TEGRA_GPIO_IRQ_STATUS_REG       (GPIO_N_INTERRUPT_STATUS_G4_0 - \
+                                         GPIO_N_ENABLE_CONFIG_00_0)
+
+static const uint32_t tegra_gpio_main_bases[] = {
+    GPIO_A_ENABLE_CONFIG_00_0,
+    GPIO_B_ENABLE_CONFIG_00_0,
+    GPIO_C_ENABLE_CONFIG_00_0,
+    GPIO_D_ENABLE_CONFIG_00_0,
+    GPIO_E_ENABLE_CONFIG_00_0,
+    GPIO_F_ENABLE_CONFIG_00_0,
+    GPIO_G_ENABLE_CONFIG_00_0,
+    GPIO_H_ENABLE_CONFIG_00_0,
+    GPIO_I_ENABLE_CONFIG_00_0,
+    GPIO_J_ENABLE_CONFIG_00_0,
+    GPIO_K_ENABLE_CONFIG_00_0,
+    GPIO_L_ENABLE_CONFIG_00_0,
+    GPIO_M_ENABLE_CONFIG_00_0,
+    GPIO_N_ENABLE_CONFIG_00_0,
+    GPIO_P_ENABLE_CONFIG_00_0,
+    GPIO_Q_ENABLE_CONFIG_00_0,
+    GPIO_R_ENABLE_CONFIG_00_0,
+    GPIO_X_ENABLE_CONFIG_00_0,
+    GPIO_Y_ENABLE_CONFIG_00_0,
+    GPIO_Z_ENABLE_CONFIG_00_0,
+    GPIO_AC_ENABLE_CONFIG_00_0,
+    GPIO_AD_ENABLE_CONFIG_00_0,
+    GPIO_AE_ENABLE_CONFIG_00_0,
+    GPIO_AF_ENABLE_CONFIG_00_0,
+    GPIO_AG_ENABLE_CONFIG_00_0,
+};
+
+static struct gpio_irq_handler tegra_gpio_main_handlers[
+                               ARRAY_SIZE(tegra_gpio_main_bases) *
+                               GPIOS_PER_BANK];
+
+static uint8_t main_bank_irq_status[ARRAY_SIZE(tegra_gpio_main_bases)] = {0};
+
+/* Number of pins per bank are captured by manual inspection of HW manuals */
+static const uint8_t num_pins_per_bank[ARRAY_SIZE(tegra_gpio_main_bases)] =
+                       {8, 1, 8, 4, 8, 6, 8, 8, 7, 6, 8, 4, 8, 8, 8, 8, 6, 8, 8, 8, 8, 4, 2, 4, 8};
+
+static uint32_t tegra_main_gpio_id_irqs[] = {
+    TEGRA_MAIN_GPIO_ID0_IRQ,
+    TEGRA_MAIN_GPIO_ID1_IRQ,
+    TEGRA_MAIN_GPIO_ID2_IRQ,
+    TEGRA_MAIN_GPIO_ID3_IRQ,
+    TEGRA_MAIN_GPIO_ID4_IRQ,
+    TEGRA_MAIN_GPIO_ID5_IRQ,
+};
+
+struct tegra_gpio_id tegra_gpio_id_main = {
+    .base_addr         = NV_ADDRESS_MAP_GPIO_CTL_BASE,
+    .bank_count        = ARRAY_SIZE(tegra_gpio_main_bases),
+    .bank_bases        = tegra_gpio_main_bases,
+    .irqs              = tegra_main_gpio_id_irqs,
+    .nirqs             = ARRAY_SIZE(tegra_main_gpio_id_irqs),
+    .irq_handlers      = tegra_gpio_main_handlers,
+    .irq_status_offset = TEGRA_GPIO_IRQ_STATUS_REG,
+    .bank_irq_status   = main_bank_irq_status,
+    .isr_status        = true,
+    .num_pins          = num_pins_per_bank,
+};
+
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/gpio-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/gpio-tegra-ids.c
new file mode 100644
index 0000000..8797865
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/gpio-tegra-ids.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+
+/* Main GPIO controller */
+extern struct tegra_gpio_id tegra_gpio_id_main;
+
+/* AON GPIO controller */
+extern struct tegra_gpio_id tegra_gpio_id_aon;
+
+struct tegra_gpio_id *const chips[] = {
+    &tegra_gpio_id_main,
+    &tegra_gpio_id_aon
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/hsp-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/hsp-tegra-ids.c
new file mode 100644
index 0000000..3eb0d8a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/hsp-tegra-ids.c
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                       // for UINT32_MAX, UINT8_MAX
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>               // for CT_ASSERT
+#include <soc-common/hw-const.h>          /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>              // for NV_ADDRESS_MAP_AON_HSP_BASE
+#include <arhsp_shrd_mbox.h>              // for HSP_SHRD_MBOX_MBOX_0_SHRD_M...
+
+/* Late FSP headers */
+#include <hsp/hsp-tegra-priv.h>           // for tegra_hsp_id, FSP__HSP__HSP...
+#include <hsp/sections-hsp.h>             // Immune from CT_ASSERT protection
+
+/* Module-specific FSP headers */
+#include <hw-config/vic-irqs.h>           // for INTERRUPT_MBOX, INTERRUPT_T...
+#include <processor/irqs-lic.h>           // for AON_LIC_IRQ_TOP_HSP0
+#include <soc-common/hsp-tegra-top-hw.h>  // for TEGRA_HSP_DB_SPE
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HSP__HSP_TEGRA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HW_CONFIG__VIC_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__HSP_TEGRA_TOP_HW_H, "Header file missing or invalid.")
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_top0 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_TOP0_HSP_BASE,
+        .host = TEGRA_HSP_DB_SPE,
+        .db_irq = INTERRUPT_TOP0_HSP_DB,
+        .sh_irq = UINT32_MAX,
+        .si_index = UINT8_MAX,
+    },
+    .inited = false,
+};
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_top1 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_TOP1_HSP_BASE,
+        .db_irq = UINT32_MAX,
+        .sh_irq = AON_LIC_IRQ_TOP_HSP1,
+        .si_index = 4,
+    },
+    .inited = false,
+};
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_fsi = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_FSI_HSP_BASE,
+        .db_irq = UINT32_MAX,
+        .sh_irq = UINT32_MAX,
+        .si_index = UINT8_MAX,
+    },
+    .inited = false,
+};
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_bpmp = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_BPMP_HSP_BASE,
+        .db_irq = UINT32_MAX,
+        .sh_irq = UINT32_MAX,
+        .si_index = UINT8_MAX,
+    },
+    .inited = false,
+};
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_aon = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_AON_HSP_BASE,
+        .db_irq = UINT32_MAX,
+        .sh_irq = INTERRUPT_MBOX,
+        .si_index = 0,
+    },
+    .inited = false,
+};
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_sce = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_SCE_HSP_BASE,
+        .db_irq = UINT32_MAX,
+        .sh_irq = UINT32_MAX,
+        .si_index = UINT8_MAX,
+    },
+    .inited = false,
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/i2c-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/i2c-tegra-ids.c
new file mode 100644
index 0000000..ca5e017
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/i2c-tegra-ids.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                  // for true
+#include <stddef.h>                   // for NULL
+#include <stdint.h>                   // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>           // for CT_ASSERT
+#include <soc-common/hw-const.h>      /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>          // for NV_ADDRESS_MAP_I2C2_BASE, NV_AD...
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>       // for FSP__HW_CONFIG__VIC_IRQS_H, INT...
+
+/* Module-specific FSP header files */
+#include <processor/i2c-tegra-hw.h>   // for i2c_hw_handle, FSP__PROCESSOR__...
+#include <soc-common/clk-tegra-hw.h>  // for FSP__SOC_COMMON__CLK_TEGRA_HW_H
+#include <soc-common/i2c-defs.h>      // for TEGRA234_I2C2, TEGRA234_I2C8
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HW_CONFIG__VIC_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__I2C_TEGRA_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__CLK_TEGRA_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__I2C_DEFS_H, "Header file missing or invalid.")
+
+static const struct i2c_hw_handle t234_i2c_ctrl2 = {
+    .ctrl_id = TEGRA234_I2C2,
+    .base = NV_ADDRESS_MAP_I2C2_BASE,
+    .clk_data = tegra_clk_i2c2,
+    .rst_data = tegra_rst_i2c2,
+    .irq_no = INTERRUPT_I2C2,
+    .is_multimaster = (bool)true,
+};
+
+static const struct i2c_hw_handle t234_i2c_ctrl8 = {
+    .ctrl_id = TEGRA234_I2C8,
+    .base = NV_ADDRESS_MAP_I2C8_BASE,
+    .clk_data = tegra_clk_i2c8,
+    .rst_data = tegra_rst_i2c8,
+    .irq_no = INTERRUPT_I2C3,
+    .is_multimaster = (bool)true,
+};
+
+const struct i2c_hw_handle *i2c_get_hw_handle(uint32_t ctrl_id)
+{
+    struct i2c_hw_handle const *hi2c_hw;
+
+    switch(ctrl_id) {
+    case TEGRA234_I2C2:
+        hi2c_hw = &t234_i2c_ctrl2;
+        break;
+    case TEGRA234_I2C8:
+        hi2c_hw = &t234_i2c_ctrl8;
+        break;
+    default:
+        hi2c_hw = NULL;
+        break;
+    }
+
+    return hi2c_hw;
+}
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/irqapi-vic-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/irqapi-vic-ids.c
new file mode 100644
index 0000000..ede3563
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/irqapi-vic-ids.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+
+uint32_t vic_base_addr[MAX_VIC_CONTROLLER] ={
+        NV_ADDRESS_MAP_AON_VIC_0_BASE,
+        NV_ADDRESS_MAP_AON_VIC_1_BASE
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/lic-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/lic-tegra-ids.c
new file mode 100644
index 0000000..5c20eaf
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/lic-tegra-ids.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                 // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>             // for INTERRUPT_LIC...
+#include <processor/irqs-lic.h>             // for AON_LIC_IRQ_BASE
+#include <lic/lic-tegra-priv.h>             // for struct tegra_lic_id,...
+#include <lic/sections-lic.h>               // Immune from CT_ASSERT
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/macros.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__HW_CONFIG__VIC_IRQS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__LIC__LIC_TEGRA_PRIV_H, "Header file missing or invalid.")
+
+#define AON_LIC_IRQ_LINES 4U
+#define AON_LIC_BASE_CHAN 2U
+#define AON_LIC_NUM_CHANS 2U
+
+SECTION_LIC_DATA
+struct tegra_lic_id tegra_lic_id_aon;
+
+SECTION_LIC_DATA
+lic_irq_context_t lic0_irq_context = {
+    .id      = &tegra_lic_id_aon,
+    .chan    = AON_LIC_BASE_CHAN,
+    .is_vfiq = false,
+};
+
+SECTION_LIC_DATA
+lic_irq_context_t lic1_irq_context = {
+    .id      = &tegra_lic_id_aon,
+    .chan    = AON_LIC_BASE_CHAN,
+    .is_vfiq = true,
+};
+
+SECTION_LIC_DATA
+lic_irq_context_t lic2_irq_context = {
+    .id      = &tegra_lic_id_aon,
+    .chan    = AON_LIC_BASE_CHAN + 1U,
+    .is_vfiq = false,
+};
+
+SECTION_LIC_DATA
+lic_irq_context_t lic3_irq_context = {
+    .id      = &tegra_lic_id_aon,
+    .chan    = AON_LIC_BASE_CHAN + 1U,
+    .is_vfiq = true,
+};
+
+static lic_irq_context_t *lic_irq_contexts[AON_LIC_IRQ_LINES] = {
+    &lic0_irq_context,
+    &lic1_irq_context,
+    &lic2_irq_context,
+    &lic3_irq_context,
+};
+
+struct tegra_lic_id tegra_lic_id_aon = {
+    .conf = {
+        .base_chan          = AON_LIC_BASE_CHAN,
+        .num_chans          = AON_LIC_NUM_CHANS,
+        .num_slices         = LIC_MAX_SLICES,
+        .local_irq_base     = (uint16_t)INTERRUPT_LIC0,
+        .lic_irq_base       = (uint16_t)AON_LIC_IRQ_BASE,
+    },
+    .irq_contexts      = lic_irq_contexts,
+    .num_lic_irq_lines = ARRAY_SIZE(lic_irq_contexts),
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/spi-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/spi-ids.c
new file mode 100644
index 0000000..b5435cc
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/spi-ids.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2017-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                  // for true
+#include <stddef.h>                   // for NULL
+#include <stdint.h>                   // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>           // for CT_ASSERT
+#include <soc-common/hw-const.h>      /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>         // for NV_ADDRESS_MAP_SPI2_BASE
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>       // for INTERRUPT_SPI
+#include <processor/irqs-lic.h>       // for INTERRUPT_SPIx
+#include <soc-common/clk-tegra-hw.h>  // for tegra_[rst/clk]_spi2
+
+/* Module-specific FSP header files */
+#include <spi/spi-priv.h>             // for spi_hw_handle, FSP__PROCESSOR__...
+#include <spi/sections-spi.h>         // for SECTION_SPI_...
+#include <port/spi-port-priv.h>       // Immune from CT_ASSERT
+
+#define INTERRUPT_SPI1  AON_LIC_IRQ_SPI1
+#define INTERRUPT_SPI3  AON_LIC_IRQ_SPI3
+
+SECTION_SPI_RODATA
+static const struct spi_hw_handle spi1_hw_handle = {
+    .rst = tegra_rst_spi1,
+    .clk = tegra_clk_spi1,
+};
+
+SECTION_SPI_RODATA
+static const struct spi_hw_handle spi2_hw_handle = {
+    .rst = tegra_rst_spi2,
+    .clk = tegra_clk_spi2,
+};
+
+SECTION_SPI_RODATA
+static const struct spi_hw_handle spi3_hw_handle = {
+    .rst = tegra_rst_spi3,
+    .clk = tegra_clk_spi3,
+};
+
+SECTION_SPI_DATA
+struct spi_ctlr spi_ctlr_spi1 = {
+	.conf = {
+		.base_addr = NV_ADDRESS_MAP_SPI1_BASE,
+        .hw_handle = &spi1_hw_handle,
+		.irq = INTERRUPT_SPI1,
+	},
+    .slave_dma_support = false,
+    .en_full_duplex = false,
+};
+
+SECTION_SPI_DATA
+struct spi_ctlr spi_ctlr_spi2 = {
+	.conf = {
+		.base_addr = NV_ADDRESS_MAP_SPI2_BASE,
+        .hw_handle = &spi2_hw_handle,
+		.irq = INTERRUPT_SPI,
+	},
+    .slave_dma_support = false,
+    .en_full_duplex = false,
+};
+
+SECTION_SPI_DATA
+struct spi_ctlr spi_ctlr_spi3 = {
+	.conf = {
+		.base_addr = NV_ADDRESS_MAP_SPI3_BASE,
+        .hw_handle = &spi3_hw_handle,
+		.irq = INTERRUPT_SPI3,
+	},
+    .slave_dma_support = false,
+    .en_full_duplex = false,
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/tke-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/tke-tegra-ids.c
new file mode 100644
index 0000000..e57ecd0
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/tke-tegra-ids.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                  // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>          // for CT_ASSERT
+#include <soc-common/hw-const.h>     /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>         // for NV_ADDRESS_MAP_AON_TKE_BASE, NV_...
+
+/* Late FSP headers */
+#include <tke/sections-tke.h>        // Immune from CT_ASSERT protection
+#include <tke/tke-tegra-priv.h>      // for tegra_tke_id, FSP__TKE__TKE_TEGR...
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>       // for FSP__PROCESSOR__IRQS_HW_H, NV_AO...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__TKE__TKE_TEGRA_PRIV_H, "Header file missing or invalid.")
+
+const uint32_t tke_top_base = NV_ADDRESS_MAP_AON_TKE_BASE;
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer0 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_AON_TKE_TMR_0_BASE,
+        .irq = NV_AON_INTERRUPT_TIMER0,
+    },
+};
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer1 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_AON_TKE_TMR_1_BASE,
+        .irq = NV_AON_INTERRUPT_TIMER1,
+    },
+};
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer2 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_AON_TKE_TMR_2_BASE,
+        .irq = NV_AON_INTERRUPT_TIMER2,
+    },
+};
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer3 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_AON_TKE_TMR_3_BASE,
+        .irq = NV_AON_INTERRUPT_TIMER3,
+    },
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/uart-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/uart-tegra-ids.c
new file mode 100644
index 0000000..084fda4
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/uart-tegra-ids.c
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                  // for true
+#include <stddef.h>                   // for NULL
+#include <stdint.h>                   // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>           // for CT_ASSERT
+#include <soc-common/hw-const.h>      /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>          // for NV_ADDRESS_MAP_UART2_BASE, NV_AD...
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>       // for FSP__HW_CONFIG__VIC_IRQS_H, INT...
+#include <soc-common/clk-tegra-hw.h>  // for FSP__SOC_COMMON__CLK_TEGRA_HW_H
+
+/* Module-specific FSP header files */
+#include <uart/tegra-uart-priv.h>     // for uart_ctlr_...
+#include <port/uart-port-priv.h>      // for uart_queue_t , struct uart_hw_handle
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HW_CONFIG__VIC_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__CLK_TEGRA_HW_H, "Header file missing or invalid.")
+
+#define TEGRA_UARTC_IRQ     INTERRUPT_UART_1
+#define TEGRA_UARTJ_IRQ     INTERRUPT_UART_J
+
+const struct uart_hw_handle uartc_hw_handle = {
+    .clk = tegra_clk_uartc,
+    .rst = tegra_rst_uartc,
+};
+
+const struct uart_hw_handle uartj_hw_handle = {
+    .clk = tegra_clk_uartj,
+    .rst = tegra_rst_uartj,
+};
+
+struct tegra_uart_ctlr tegra_uart_ctlr_uartc = {
+    .id = {
+        .base_addr  = NV_ADDRESS_MAP_UARTC_BASE,
+        .irq        = TEGRA_UARTC_IRQ,
+        .hw_handle  = &uartc_hw_handle,
+    },
+    .initialized = false,
+};
+
+struct tegra_uart_ctlr tegra_uart_ctlr_uartj = {
+    .id = {
+        .base_addr  = NV_ADDRESS_MAP_UARTJ_BASE,
+        .irq        = TEGRA_UARTJ_IRQ,
+        .hw_handle  = &uartj_hw_handle,
+    },
+    .initialized = false,
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/wdt-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/wdt-tegra-ids.c
new file mode 100644
index 0000000..eae988b
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/aon/wdt-tegra-ids.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>              // for CT_ASSERT
+#include <soc-common/hw-const.h>         /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>             // for NV_ADDRESS_MAP_AON_TKE_WDT_0...
+
+/* Late FSP headers */
+#include <misc/macros.h>                 // for START_RFD_BLOCK, END_RFD_BLOCK
+#include <watchdog/sections-watchdog.h>  // Immune from CT_ASSERT protection
+#include <watchdog/wdt-tegra-priv.h>     // for tegra_wdt
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>           // for NV_AON_INTERRUPT_WDTFIQ, NV_...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WDT_TEGRA_PRIV_H, "Header file missing or invalid.")
+
+extern struct tegra_wdt tegra_wdt_instance;
+
+SECTION_WATCHDOG_DATA
+struct tegra_wdt tegra_wdt_instance = {
+    .id = {
+        .devname        = "wdt",
+        .base_addr      = NV_ADDRESS_MAP_AON_TKE_WDT_0_BASE,
+        .irq            = NV_AON_INTERRUPT_WDTIRQ,
+        .fiq            = NV_AON_INTERRUPT_WDTFIQ,
+    },
+};
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/bpmp/ast-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/bpmp/ast-tegra-ids.c
new file mode 100644
index 0000000..a3326e1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/bpmp/ast-tegra-ids.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>
+
+/* Late FSP headers */
+
+/* Module-dependent FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+const uint32_t ast_tegra_id[] = {
+    NV_ADDRESS_MAP_BPMP_AST_0_BASE,
+    NV_ADDRESS_MAP_BPMP_AST_1_BASE
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/bpmp/i2c-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/bpmp/i2c-tegra-ids.c
new file mode 100644
index 0000000..4dfb791
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/bpmp/i2c-tegra-ids.c
@@ -0,0 +1,85 @@
+/*
+ *  * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *   *
+ *    * Redistribution and use in source and binary forms, with or without
+ *     * modification, are permitted provided that the following conditions
+ *      * are met:
+ *       *  * Redistributions of source code must retain the above copyright
+ *        *    notice, this list of conditions and the following disclaimer.
+ *         *  * Redistributions in binary form must reproduce the above copyright
+ *          *    notice, this list of conditions and the following disclaimer in the
+ *           *    documentation and/or other materials provided with the distribution.
+ *            *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *             *    contributors may be used to endorse or promote products derived
+ *              *    from this software without specific prior written permission.
+ *               *
+ *                * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ *                 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *                  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ *                   * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ *                    * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ *                     * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ *                      * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ *                       * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ *                        * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *                         * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *                          * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *                           */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+#include <mach/address_map_new_hex_misra.h>
+
+/* Late FSP headers */
+#include <misc/bitops.h>
+#include <clk.h>
+#include <mach/reset.h>
+#include <bpmp/irq.h>
+#undef ARRAY_SIZE
+#undef DIV_ROUND_UP
+
+/* Module-specific FSP header files */
+#include <processor/i2c-tegra-hw.h>
+#include <soc-common/i2c-dependencies.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__PROCESSOR__I2C_TEGRA_HW_H, "Header file missing or invalid.")
+
+const struct i2c_hw_handle t234_i2c_ctrl5 = {
+    .ctrl_id = TEGRA234_I2C5,	
+    .base = NV_ADDRESS_MAP_I2C5_BASE,
+    .clk_id = TEGRA234_CLK_I2C5,
+    .rst_id = TEGRA234_RESET_I2C5,
+    .irq_no = BPMP_INT_SOCPWRI2C,
+    .is_multimaster = false,
+};
+
+const struct i2c_hw_handle *i2c_get_hw_handle(uint32_t ctrl_id)
+{
+    const struct i2c_hw_handle *hi2c_hw;
+
+    switch (ctrl_id) {
+        case TEGRA234_I2C5:
+            hi2c_hw = &t234_i2c_ctrl5;
+            break;
+        default:
+            hi2c_hw = NULL;
+            break;
+							    }
+
+    return hi2c_hw;
+}
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/bpmp/irqapi-vic-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/bpmp/irqapi-vic-ids.c
new file mode 100644
index 0000000..1f9d1ba
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/bpmp/irqapi-vic-ids.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+
+uint32_t vic_base_addr[MAX_VIC_CONTROLLER] ={
+        NV_ADDRESS_MAP_BPMP_VIC_0_BASE,
+        NV_ADDRESS_MAP_BPMP_VIC_1_BASE
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/bpmp/tke-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/bpmp/tke-tegra-ids.c
new file mode 100644
index 0000000..111716f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/bpmp/tke-tegra-ids.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                  // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>          // for CT_ASSERT
+#include <soc-common/hw-const.h>     /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>         // for NV_ADDRESS_MAP_AON_TKE_BASE, NV_...
+
+/* Late FSP headers */
+#include <tke/tke-tegra-priv.h>      // for tegra_tke_id, FSP__TKE__TKE_TEGR...
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>       // for FSP__PROCESSOR__IRQS_HW_H, NV_AO...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__TKE__TKE_TEGRA_PRIV_H, "Header file missing or invalid.")
+
+const uint32_t tke_top_base = NV_ADDRESS_MAP_BPMP_TKE_BASE;
+
+struct tegra_tke_id tegra_tke_timer0 = {
+        .conf = {
+                .base_addr = NV_ADDRESS_MAP_BPMP_TKE_TMR_0_BASE,
+                .irq = NV_BPMP_IRQ_TIMER0,
+        },
+};
+extern const struct tegra_tke_id tegra_tke_id_timer0
+__attribute__((alias("tegra_tke_timer0")));
+
+struct tegra_tke_id tegra_tke_timer1 = {
+        .conf = {
+                .base_addr = NV_ADDRESS_MAP_BPMP_TKE_TMR_1_BASE,
+                .irq = NV_BPMP_IRQ_TIMER1,
+        },
+};
+extern const struct tegra_tke_id tegra_tke_id_timer1
+__attribute__((alias("tegra_tke_timer1")));
+
+struct tegra_tke_id tegra_tke_timer2 = {
+        .conf = {
+                .base_addr = NV_ADDRESS_MAP_BPMP_TKE_TMR_2_BASE,
+                .irq = NV_BPMP_IRQ_TIMER2,
+        },
+};
+extern const struct tegra_tke_id tegra_tke_id_timer2
+__attribute__((alias("tegra_tke_timer2")));
+
+struct tegra_tke_id tegra_tke_timer3 = {
+        .conf = {
+                .base_addr = NV_ADDRESS_MAP_BPMP_TKE_TMR_3_BASE,
+                .irq = NV_BPMP_IRQ_TIMER3,
+        },
+};
+extern const struct tegra_tke_id tegra_tke_id_timer3
+__attribute__((alias("tegra_tke_timer3")));
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/bpmp/wdt-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/bpmp/wdt-tegra-ids.c
new file mode 100644
index 0000000..451149f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/bpmp/wdt-tegra-ids.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>              // for CT_ASSERT
+#include <soc-common/hw-const.h>         /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>             // for NV_ADDRESS_MAP_AON_TKE_WDT_0...
+
+/* Late FSP headers */
+#include <misc/macros.h>                 // for START_RFD_BLOCK, END_RFD_BLOCK
+#include <watchdog/sections-watchdog.h>  // Immune from CT_ASSERT protection
+#include <watchdog/wdt-tegra-priv.h>     // for tegra_wdt
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>           // for NV_AON_INTERRUPT_WDTFIQ, NV_...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WDT_TEGRA_PRIV_H, "Header file missing or invalid.")
+
+extern struct tegra_wdt tegra_wdt_instance;
+
+SECTION_WATCHDOG_DATA
+struct tegra_wdt tegra_wdt_instance = {
+    .id = {
+        .devname        = "wdt",
+        .base_addr      = NV_ADDRESS_MAP_BPMP_TKE_WDT_0_BASE,
+        .irq            = NV_BPMP_IRQ_WDTIRQ,
+        .fiq            = NV_BPMP_IRQ_WDTFIQ,
+    },
+};
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/ast-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/ast-tegra-ids.c
new file mode 100644
index 0000000..1cf2df0
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/ast-tegra-ids.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+const uint32_t ast_tegra_id[] = {
+    NV_ADDRESS_MAP_DCE_AST_0_BASE,
+    NV_ADDRESS_MAP_DCE_AST_1_BASE
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/comb-uart-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/comb-uart-ids.c
new file mode 100644
index 0000000..c449133
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/comb-uart-ids.c
@@ -0,0 +1,48 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                       // for UINT32_MAX, UINT8_MAX
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>               // for CT_ASSERT
+#include <soc-common/hw-const.h>          /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>              // for NV_ADDRESS_MAP_AON_HSP_SM_BASE
+
+/* Late FSP headers */
+#include <comb-uart/comb-uart-priv.h>     // for comb_uart_id, FSP__HSP__HSP...
+#include <comb-uart/sections-comb-uart.h> // Immune from CT_ASSERT protection
+
+SECTION_COMB_UART_RODATA
+const struct comb_uart_id comb_uart_id_dce = {
+    .tx_sm_reg   = HSP_SM_BASE(NV_ADDRESS_MAP_AON_HSP_SM_BASE, 3),
+    .rx_sm_reg   = 0UL,
+    .supports_rx = false,
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/gpcdma-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/gpcdma-ids.c
new file mode 100644
index 0000000..36a9da3
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/gpcdma-ids.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                 // for CT_ASSERT
+#include <soc-common/hw-const.h>            /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>                // for NV_ADDRESS_MAP_AON_DMA_BASE
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>             // for INTERRUPT_DMA...
+#include <soc-common/clk-tegra-hw.h>        // for tegra_rst_aon_gpcdma
+#include <gpcdma/gpcdma-priv.h>             // for struct gpcdma_id, gpcdma_channel
+#include <gpcdma/sections-gpcdma.h>         // Immune from CT_ASSERT
+#include <port/gpcdma-port-priv.h>          // Immune from CT_ASSERT
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/macros.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HW_CONFIG__VIC_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__CLK_TEGRA_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPCDMA__GPCDMA_PRIV_H, "Header file missing or invalid.")
+
+SECTION_GPCDMA_RODATA
+const struct gpcdma_hw_handle gpcdma_hw_handle_dce = {
+    .rst = tegra_rst_dce_gpcdma,
+};
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan0;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan1;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan2;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan3;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan4;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan5;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan6;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan7;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_id gpcdma_id_dce = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_DCE_DMA_BASE,
+        .irqs = {
+            [0] = INTERRUPT_DMA0,
+            [1] = INTERRUPT_DMA1,
+            [2] = INTERRUPT_DMA2,
+            [3] = INTERRUPT_DMA3,
+            [4] = INTERRUPT_DMA4,
+            [5] = INTERRUPT_DMA5,
+            [6] = INTERRUPT_DMA6,
+            [7] = INTERRUPT_DMA7,
+        },
+        .hw_handle = &gpcdma_hw_handle_dce,
+    },
+    .channels = {
+        [0] = &gpcdma_chan0,
+        [1] = &gpcdma_chan1,
+        [2] = &gpcdma_chan2,
+        [3] = &gpcdma_chan3,
+        [4] = &gpcdma_chan4,
+        [5] = &gpcdma_chan5,
+        [6] = &gpcdma_chan6,
+        [7] = &gpcdma_chan7,
+    },
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/gpio-aon-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/gpio-aon-tegra-ids.c
new file mode 100644
index 0000000..234b291
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/gpio-aon-tegra-ids.c
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/* Compiler headers */
+#include <stdint.h>                                  // for uint32_t, ...
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                          // for CT_ASSERT
+
+/* Hardware headers */
+#include <address_map_new.h>                         // for NV_ADDRESS_MAP_AON_GPIO_0_BASE, NV_ADDRESS_MAP_GPIO_CTL0_BASE
+#include <argpio_aon_sw.h>                               // for GPIO_A_ENABLE_CONFIG_00_0, ....
+
+/* Late FSP headers */
+#include <misc/macros.h>                             // for ARRAY_SIZE
+
+/* Module-specific FSP headers */
+#include <gpio/tegra-gpio-priv.h>                    // for struct tegra_gpio_id
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__GPIO__TEGRA_GPIO_PRIV_H, "Header file missing or invalid.")
+
+#define TEGRA_GPIO_IRQ_STATUS_REG       (GPIO_AA_INTERRUPT_STATUS_G7_0 - \
+                                         GPIO_AA_ENABLE_CONFIG_00_0)
+
+static const uint32_t tegra_gpio_aon_bases[] = {
+    GPIO_AA_ENABLE_CONFIG_00_0,
+    GPIO_BB_ENABLE_CONFIG_00_0,
+    GPIO_CC_ENABLE_CONFIG_00_0,
+    GPIO_DD_ENABLE_CONFIG_00_0,
+    GPIO_EE_ENABLE_CONFIG_00_0,
+    GPIO_GG_ENABLE_CONFIG_00_0,
+};
+
+/* Number of pins per bank are captured by manual inspection of HW manuals */
+static const uint8_t num_pins_per_bank[ARRAY_SIZE(tegra_gpio_aon_bases)] = {8, 4, 8, 3, 8, 1};
+
+struct tegra_gpio_id tegra_gpio_id_aon = {
+    .base_addr         = NV_ADDRESS_MAP_AON_GPIO_0_BASE,
+    .bank_count        = ARRAY_SIZE(tegra_gpio_aon_bases),
+    .bank_bases        = tegra_gpio_aon_bases,
+    .irq_status_offset = TEGRA_GPIO_IRQ_STATUS_REG,
+    .isr_status        = false,
+    .num_pins          = num_pins_per_bank,
+};
+
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/gpio-main-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/gpio-main-tegra-ids.c
new file mode 100644
index 0000000..9c6f387
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/gpio-main-tegra-ids.c
@@ -0,0 +1,103 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/* Compiler headers */
+#include <stdint.h>                                  // for uint32_t, ...
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                          // for CT_ASSERT
+
+/* Hardware headers */
+#include <address_map_new.h>                         // for NV_ADDRESS_MAP_AON_GPIO_0_BASE, NV_ADDRESS_MAP_GPIO_CTL0_BASE
+#include <argpio_sw.h>                               // for GPIO_A_ENABLE_CONFIG_00_0, ....
+
+/* Late FSP headers */
+#include <misc/macros.h>                             // for ARRAY_SIZE
+
+/* Module-specific FSP headers */
+#include <gpio/tegra-gpio-priv.h>                    // for struct tegra_gpio_id
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__GPIO__TEGRA_GPIO_PRIV_H, "Header file missing or invalid.")
+
+#define TEGRA_GPIO_IRQ_STATUS_REG       (GPIO_N_INTERRUPT_STATUS_G7_0 - \
+                                         GPIO_N_ENABLE_CONFIG_00_0)
+
+static const uint32_t tegra_gpio_main_bases[] = {
+    GPIO_A_ENABLE_CONFIG_00_0,
+    GPIO_B_ENABLE_CONFIG_00_0,
+    GPIO_C_ENABLE_CONFIG_00_0,
+    GPIO_D_ENABLE_CONFIG_00_0,
+    GPIO_E_ENABLE_CONFIG_00_0,
+    GPIO_F_ENABLE_CONFIG_00_0,
+    GPIO_G_ENABLE_CONFIG_00_0,
+    GPIO_H_ENABLE_CONFIG_00_0,
+    GPIO_I_ENABLE_CONFIG_00_0,
+    GPIO_J_ENABLE_CONFIG_00_0,
+    GPIO_K_ENABLE_CONFIG_00_0,
+    GPIO_L_ENABLE_CONFIG_00_0,
+    GPIO_M_ENABLE_CONFIG_00_0,
+    GPIO_N_ENABLE_CONFIG_00_0,
+    GPIO_P_ENABLE_CONFIG_00_0,
+    GPIO_Q_ENABLE_CONFIG_00_0,
+    GPIO_R_ENABLE_CONFIG_00_0,
+    GPIO_X_ENABLE_CONFIG_00_0,
+    GPIO_Y_ENABLE_CONFIG_00_0,
+    GPIO_Z_ENABLE_CONFIG_00_0,
+    GPIO_AC_ENABLE_CONFIG_00_0,
+    GPIO_AD_ENABLE_CONFIG_00_0,
+    GPIO_AE_ENABLE_CONFIG_00_0,
+    GPIO_AF_ENABLE_CONFIG_00_0,
+    GPIO_AG_ENABLE_CONFIG_00_0,
+};
+
+/* Number of pins per bank are captured by manual inspection of HW manuals */
+static const uint8_t num_pins_per_bank[ARRAY_SIZE(tegra_gpio_main_bases)] =
+                       {8, 1, 8, 4, 8, 6, 8, 8, 7, 6, 8, 4, 8, 8, 8, 8, 6, 8, 8, 8, 8, 4, 2, 4, 8};
+
+struct tegra_gpio_id tegra_gpio_id_main = {
+    .base_addr         = NV_ADDRESS_MAP_GPIO_CTL_BASE,
+    .bank_count        = ARRAY_SIZE(tegra_gpio_main_bases),
+    .bank_bases        = tegra_gpio_main_bases,
+    .irq_status_offset = TEGRA_GPIO_IRQ_STATUS_REG,
+    .isr_status        = false,
+    .num_pins          = num_pins_per_bank,
+};
+
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/gpio-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/gpio-tegra-ids.c
new file mode 100644
index 0000000..ac7a1c7
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/gpio-tegra-ids.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stddef.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+#include <soc-common/tegra-gpio-hw.h>                   // for tegra_gpio_id_main
+#include <processor/gpio-tegra.h>
+
+/* Module-specific FSP headers */
+#include <gpio/tegra-gpio-priv.h>                       /* for struct tegra_gpio_id */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+
+    CT_ASSERT(FSP__GPIO__TEGRA_GPIO_PRIV_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__PROCESSOR__GPIO_TEGRA_HW_H, "Header file missing or invalid.")
+
+struct tegra_gpio_id * tegra_gpio_id_dce[MAX_GPIO_CONTROLLERS] = {
+    &tegra_gpio_id_main,
+    &tegra_gpio_id_aon,
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/hsp-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/hsp-tegra-ids.c
new file mode 100644
index 0000000..8b241a9
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/hsp-tegra-ids.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                       // for UINT32_MAX, UINT8_MAX
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>               // for CT_ASSERT
+#include <soc-common/hw-const.h>          /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>              // for NV_ADDRESS_MAP_DCE_HSP_BASE
+#include <arhsp_shrd_mbox.h>              // for HSP_SHRD_MBOX_MBOX_0_SHRD_M...
+
+/* Late FSP headers */
+#include <hsp/hsp-tegra-priv.h>           // for tegra_hsp_id, FSP__HSP__HSP...
+#include <hsp/sections-hsp.h>             // Immune from CT_ASSERT protection
+
+/* Module-specific FSP headers */
+#include <hw-config/vic-irqs.h>           // for FSP__HW_CONFIG__VIC_IRQS_H
+#include <soc-common/hsp-tegra-top-hw.h>  // for FSP__SOC_COMMON__HSP_TEGRA_...
+#include <vic/tegra-vic.h>                // for FSP__VIC__TEGRA_VIC_H
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HSP__HSP_TEGRA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HW_CONFIG__VIC_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__HSP_TEGRA_TOP_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__VIC__TEGRA_VIC_H, "Header file missing or invalid.")
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_top0 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_TOP0_HSP_BASE,
+        .host = TEGRA_HSP_DB_DCE,
+        .db_irq = INTERRUPT_TOP0_HSP_DB,
+        .sh_irq = UINT32_MAX,
+        .si_index = UINT8_MAX,
+    },
+};
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_dce = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_DCE_HSP_BASE,
+        .db_irq = UINT32_MAX,
+        .sh_irq = INTERRUPT_MBOX,
+        .si_index = 0,
+    },
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/i2c-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/i2c-tegra-ids.c
new file mode 100644
index 0000000..912af68
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/i2c-tegra-ids.c
@@ -0,0 +1,115 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                  // for true
+#include <stddef.h>                   // for NULL
+#include <stdint.h>                   // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>           // for CT_ASSERT
+#include <soc-common/hw-const.h>      /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>          // for NV_ADDRESS_MAP_I2C2_BASE, NV_AD...
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>       // for FSP__HW_CONFIG__VIC_IRQS_H, INT...
+
+/* Module-specific FSP header files */
+#include <processor/i2c-tegra-hw.h>   // for i2c_hw_handle, FSP__PROCESSOR__...
+#include <soc-common/clk-tegra-hw.h>  // for FSP__SOC_COMMON__CLK_TEGRA_HW_H
+#include <soc-common/i2c-defs.h>      // for TEGRA234_I2C2, TEGRA234_I2C8
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__HW_CONFIG__VIC_IRQS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__PROCESSOR__I2C_TEGRA_HW_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__SOC_COMMON__CLK_TEGRA_HW_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__SOC_COMMON__I2C_DEFS_H, "Header file missing or invalid.")
+
+static const struct i2c_hw_handle t234_i2c_ctrl4 = {
+    .ctrl_id = TEGRA234_I2C4,
+    .base = NV_ADDRESS_MAP_I2C4_BASE,
+    .clk_data = tegra_clk_i2c4,
+    .rst_data = tegra_rst_i2c4,
+    .irq_no = INTERRUPT_I2C3,
+    .is_multimaster = (bool)true,
+};
+static const struct i2c_hw_handle t234_i2c_ctrl6 = {
+    .ctrl_id = TEGRA234_I2C6,
+    .base = NV_ADDRESS_MAP_I2C6_BASE,
+    .clk_data = tegra_clk_i2c6,
+    .rst_data = tegra_rst_i2c6,
+    .irq_no = INTERRUPT_I2C3, // This is a dummy interrupt. DCE will use LIC mapping
+    .is_multimaster = (bool)true,
+};
+
+static const struct i2c_hw_handle t234_i2c_ctrl7 = {
+    .ctrl_id = TEGRA234_I2C7,
+    .base = NV_ADDRESS_MAP_I2C7_BASE,
+    .clk_data = tegra_clk_i2c7,
+    .rst_data = tegra_rst_i2c7,
+    .irq_no = INTERRUPT_I2C3, // This is a dummy interrupt. DCE will use LIC mapping
+    .is_multimaster = (bool)true,
+};
+
+const struct i2c_hw_handle *i2c_get_hw_handle(uint32_t ctrl_id)
+{
+    struct i2c_hw_handle const *hi2c_hw;
+
+    switch(ctrl_id) {
+    case TEGRA234_I2C4:
+        hi2c_hw = &t234_i2c_ctrl4;
+        break;
+
+    case TEGRA234_I2C6:
+        hi2c_hw = &t234_i2c_ctrl6;
+        break;
+
+    case TEGRA234_I2C7:
+        hi2c_hw = &t234_i2c_ctrl7;
+        break;
+
+    default:
+        hi2c_hw = NULL;
+        break;
+    }
+
+    return hi2c_hw;
+}
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/irqapi-vic-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/irqapi-vic-ids.c
new file mode 100644
index 0000000..c235949
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/irqapi-vic-ids.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP soudce code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+
+const uint32_t vic_base_addr[MAX_VIC_CONTROLLER] ={
+        NV_ADDRESS_MAP_DCE_VIC_0_BASE,
+        NV_ADDRESS_MAP_DCE_VIC_1_BASE
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/lic-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/lic-tegra-ids.c
new file mode 100644
index 0000000..5ca87b0
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/lic-tegra-ids.c
@@ -0,0 +1,111 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                 // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>             // for INTERRUPT_LIC...
+#include <processor/irqs-lic.h>             // for DCE_LIC_IRQ_BASE
+#include <lic/lic-tegra-priv.h>             // for struct tegra_lic_id,...
+#include <lic/sections-lic.h>               // Immune from CT_ASSERT
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/macros.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__HW_CONFIG__VIC_IRQS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__LIC__LIC_TEGRA_PRIV_H, "Header file missing or invalid.")
+
+#define DCE_LIC_IRQ_LINES 4U
+#define DCE_LIC_BASE_CHAN 8U
+#define DCE_LIC_NUM_CHANS 2U
+
+SECTION_LIC_DATA
+struct tegra_lic_id tegra_lic_id_dce;
+
+SECTION_LIC_DATA
+lic_irq_context_t lic0_irq_context = {
+    .id      = &tegra_lic_id_dce,
+    .chan    = DCE_LIC_BASE_CHAN,
+    .is_vfiq = false,
+};
+
+SECTION_LIC_DATA
+lic_irq_context_t lic1_irq_context = {
+    .id      = &tegra_lic_id_dce,
+    .chan    = DCE_LIC_BASE_CHAN,
+    .is_vfiq = true,
+};
+
+SECTION_LIC_DATA
+lic_irq_context_t lic2_irq_context = {
+    .id      = &tegra_lic_id_dce,
+    .chan    = DCE_LIC_BASE_CHAN + 1U,
+    .is_vfiq = false,
+};
+
+SECTION_LIC_DATA
+lic_irq_context_t lic3_irq_context = {
+    .id      = &tegra_lic_id_dce,
+    .chan    = DCE_LIC_BASE_CHAN + 1U,
+    .is_vfiq = true,
+};
+
+static lic_irq_context_t *lic_irq_contexts[DCE_LIC_IRQ_LINES] = {
+    &lic0_irq_context,
+    &lic1_irq_context,
+    &lic2_irq_context,
+    &lic3_irq_context,
+};
+
+struct tegra_lic_id tegra_lic_id_dce = {
+    .conf = {
+        .base_chan          = DCE_LIC_BASE_CHAN,
+        .num_chans          = DCE_LIC_NUM_CHANS,
+        .num_slices         = LIC_MAX_SLICES,
+        .local_irq_base     = (uint16_t)INTERRUPT_LIC0,
+        .lic_irq_base       = (uint16_t)LIC_IRQ_BASE,
+    },
+    .irq_contexts      = lic_irq_contexts,
+    .num_lic_irq_lines = ARRAY_SIZE(lic_irq_contexts),
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/tke-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/tke-tegra-ids.c
new file mode 100644
index 0000000..16a34ff
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/tke-tegra-ids.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+#include <address_map_new.h>
+
+/* Late FSP headers */
+#include <tke/tke-tegra-priv.h>
+#include <tke/sections-tke.h>                           /* Immune from CT_ASSERT protection */
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>
+#include <soc-common/hw-const.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP soudce code.
+ */
+CT_ASSERT(FSP__TKE__TKE_TEGRA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+const uint32_t tke_top_base = NV_ADDRESS_MAP_DCE_TKE_BASE;
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer0 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_DCE_TKE_TMR_0_BASE,
+        .irq = NV_DCE_IRQ_TIMER0,
+    },
+};
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer1 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_DCE_TKE_TMR_1_BASE,
+        .irq = NV_DCE_IRQ_TIMER1,
+    },
+};
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer2 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_DCE_TKE_TMR_2_BASE,
+        .irq = NV_DCE_IRQ_TIMER2,
+    },
+};
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer3 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_DCE_TKE_TMR_3_BASE,
+        .irq = NV_DCE_IRQ_TIMER3,
+    },
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/wdt-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/wdt-tegra-ids.c
new file mode 100644
index 0000000..13ed3fa
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/dce/wdt-tegra-ids.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>              // for CT_ASSERT
+
+/* Hardware headers */
+#include <address_map_new.h>             // for NV_ADDRESS_MAP_DCE_TKE_WDT_0...
+
+/* Late FSP headers */
+#include <misc/macros.h>                 // for START_RFD_BLOCK, END_RFD_BLOCK
+#include <watchdog/wdt-tegra-priv.h>     // for FSP__WATCHDOG__WDT_TEGRA_PRIV_H
+#include <watchdog/sections-watchdog.h>  /* Immune from CT_ASSERT protection */
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>           // for FSP__PROCESSOR__IRQS_HW_H
+#include <soc-common/hw-const.h>         // for FSP__SOC_COMMON__HW_CONST_H
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP soudce code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__WATCHDOG__WDT_TEGRA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+extern struct tegra_wdt tegra_wdt_instance;
+
+SECTION_WATCHDOG_DATA
+struct tegra_wdt tegra_wdt_instance = {
+    .id = {
+        .devname        = "wdt",
+        .base_addr      = NV_ADDRESS_MAP_DCE_TKE_WDT_0_BASE,
+        .irq            = NV_DCE_IRQ_WDTIRQ,
+        .fiq            = NV_DCE_IRQ_WDTFIQ,
+    },
+};
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/ast-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/ast-tegra-ids.c
new file mode 100644
index 0000000..49ba70a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/ast-tegra-ids.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+const uint32_t ast_tegra_id[] = {
+    NV_ADDRESS_MAP_FSI_CPU0_AST_BASE,
+    NV_ADDRESS_MAP_FSI_CPU1_AST_BASE,
+    NV_ADDRESS_MAP_FSI_CPU2_AST_BASE,
+    NV_ADDRESS_MAP_FSI_CPU3_AST_BASE
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/gpcdma-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/gpcdma-ids.c
new file mode 100644
index 0000000..7295dcc
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/gpcdma-ids.c
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                 // for CT_ASSERT
+#include <soc-common/hw-const.h>            /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>                // for NV_ADDRESS_MAP_AON_DMA_BASE
+
+/* Late FSP headers */
+#include <soc-common/clk-tegra-hw.h>        // for tegra_rst_aon_gpcdma
+#include <gpcdma/gpcdma-priv.h>             // for struct gpcdma_id, gpcdma_channel
+#include <gpcdma/sections-gpcdma.h>         // Immune from CT_ASSERT
+#include <port/gpcdma-port-priv.h>          // Immune from CT_ASSERT
+
+#include <processor/irqs-hw.h>       // for FSP__PROCESSOR__IRQS_HW_H
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/macros.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__SOC_COMMON__CLK_TEGRA_HW_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__GPCDMA__GPCDMA_PRIV_H, "Header file missing or invalid.")
+
+SECTION_GPCDMA_RODATA
+const struct gpcdma_hw_handle gpcdma_hw_handle_fsi = {
+    /* FIXME: add CLK for GPCDMA */
+    .rst = 0,
+};
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan0;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan1;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan2;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan3;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan4;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan5;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan6;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan7;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_id gpcdma_id_fsi = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_FSI_DMA_BASE,
+        .irqs = {
+            [0] = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_DMA_INTR0,
+            [1] = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_DMA_INTR1,
+            [2] = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_DMA_INTR2,
+            [3] = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_DMA_INTR3,
+            [4] = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_DMA_INTR4,
+            [5] = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_DMA_INTR5,
+            [6] = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_DMA_INTR6,
+            [7] = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_DMA_INTR7,
+        },
+        .hw_handle = &gpcdma_hw_handle_fsi,
+    },
+    .channels = {
+        [0] = &gpcdma_chan0,
+        [1] = &gpcdma_chan1,
+        [2] = &gpcdma_chan2,
+        [3] = &gpcdma_chan3,
+        [4] = &gpcdma_chan4,
+        [5] = &gpcdma_chan5,
+        [6] = &gpcdma_chan6,
+        [7] = &gpcdma_chan7,
+    },
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/gpio-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/gpio-tegra-ids.c
new file mode 100644
index 0000000..5a8c1f6
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/gpio-tegra-ids.c
@@ -0,0 +1,94 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+/* Compiler headers */
+#include <stdint.h>                                  // for uint32_t, ...
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                          // for CT_ASSERT
+
+/* Hardware headers */
+#include <address_map_new.h>                         // for NV_ADDRESS_MAP_AON_GPIO_0_BASE, NV_ADDRESS_MAP_GPIO_CTL0_BASE
+#include <argpio_sw.h>                               // for GPIO_A_ENABLE_CONFIG_00_0, ....
+
+/* Late FSP headers */
+#include <misc/macros.h>                             // for ARRAY_SIZE
+
+/* Module-specific FSP headers */
+#include <gpio/tegra-gpio-priv.h>                    // for struct gpio_irq_handler
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPIO__TEGRA_GPIO_PRIV_H, "Header file missing or invalid.")
+
+static const uint32_t tegra_fsi_gpio_ctl_0_bases[] = {
+    GPIO_U_ENABLE_CONFIG_00_0,
+    GPIO_V_ENABLE_CONFIG_00_0,
+};
+
+/* Number of pins per bank are captured by manual inspection of HW manuals */
+static const uint8_t ctl0_pins_per_bank[ARRAY_SIZE(tegra_fsi_gpio_ctl_0_bases)] = {8, 1};
+
+static const uint32_t tegra_fsi_gpio_ctl_1_bases[] = {
+    GPIO_S_ENABLE_CONFIG_00_0,
+    GPIO_T_ENABLE_CONFIG_00_0,
+//    GPIO_W_ENABLE_CONFIG_00_0,
+};
+
+/* Number of pins per bank are captured by manual inspection of HW manuals */
+static const uint8_t ctl1_pins_per_bank[ARRAY_SIZE(tegra_fsi_gpio_ctl_1_bases)] = {8, 2};
+
+struct tegra_gpio_id tegra_fsi_gpio_ctl_0_id = {
+    .base_addr         = NV_ADDRESS_MAP_FSI_GPIO_CTL0_BASE,
+    .bank_count        = ARRAY_SIZE(tegra_fsi_gpio_ctl_0_bases),
+    .bank_bases        = tegra_fsi_gpio_ctl_0_bases,
+    .num_pins          = ctl0_pins_per_bank,
+};
+
+struct tegra_gpio_id tegra_fsi_gpio_ctl_1_id = {
+    .base_addr         = NV_ADDRESS_MAP_FSI_GPIO_CTL1_BASE,
+    .bank_count        = ARRAY_SIZE(tegra_fsi_gpio_ctl_1_bases),
+    .bank_bases        = tegra_fsi_gpio_ctl_1_bases,
+    .num_pins          = ctl1_pins_per_bank,
+};
+
+struct tegra_gpio_id *const chips[] = {
+    &tegra_fsi_gpio_ctl_0_id,
+    &tegra_fsi_gpio_ctl_1_id
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/hsp-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/hsp-tegra-ids.c
new file mode 100644
index 0000000..f13769d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/hsp-tegra-ids.c
@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>               // for CT_ASSERT
+#include <soc-common/hw-const.h>          /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>              // for NV_ADDRESS_MAP_FSI_HSP_BASE
+#include <arhsp_shrd_mbox.h>              // for HSP_SHRD_MBOX_MBOX_0_SHRD_M...
+
+/* Late FSP headers */
+#include <hsp/hsp-tegra-priv.h>           // for tegra_hsp_id, FSP__HSP__HSP...
+#include <hsp/sections-hsp.h>             // Immune from CT_ASSERT protection
+#include <processor/irqs-hw.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__HSP__HSP_TEGRA_PRIV_H, "Header file missing or invalid.")
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_top2_hsp_tx = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_TOP2_HSP_BASE,
+        .sh_irq = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_TOP_HSP2_SI0,
+        .si_index = 0U,
+    },
+    .n_sm = 8U,
+    .n_ss = 4U,
+    .n_as = 0U,
+    .n_db = 0U,
+    .n_si = 8U,
+};
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_top2_hsp_rx = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_TOP2_HSP_BASE,
+        .sh_irq = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_TOP_HSP2_SI1,
+        .si_index = 1U,
+    },
+    .n_sm = 8U,
+    .n_ss = 4U,
+    .n_as = 0U,
+    .n_db = 0U,
+    .n_si = 8U,
+};
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_fsi_hsp_tx = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_FSI_HSP_BASE,
+        .sh_irq = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_HSP_SI0,
+        .si_index = 0U,
+    },
+    .n_sm = 8U,
+    .n_ss = 4U,
+    .n_as = 0U,
+    .n_db = 0U,
+    .n_si = 8U,
+};
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_fsi_hsp_rx = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_FSI_HSP_BASE,
+        .sh_irq = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_HSP_SI4,
+        .si_index = 4U,
+    },
+    .n_sm = 8U,
+    .n_ss = 4U,
+    .n_as = 0U,
+    .n_db = 0U,
+    .n_si = 8U,
+};
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_sce_hsp1_tx = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_SCE_HSP1_BASE,
+        .sh_irq = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_SCE_HSP1_SI2,
+        .si_index = 2U,
+    },
+    .n_sm = 8U,
+    .n_ss = 4U,
+    .n_as = 0U,
+    .n_db = 0U,
+    .n_si = 8U,
+};
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_sce_hsp1_rx = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_SCE_HSP1_BASE,
+        .sh_irq = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_SCE_HSP1_SI3,
+        .si_index = 3U,
+    },
+    .n_sm = 8U,
+    .n_ss = 4U,
+    .n_as = 0U,
+    .n_db = 0U,
+    .n_si = 8U,
+};
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_sce_hsp2_tx = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_SCE_HSP2_BASE,
+        .sh_irq = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_SCE_HSP2_SI2,
+        .si_index = 2U,
+    },
+    .n_sm = 8U,
+    .n_ss = 4U,
+    .n_as = 0U,
+    .n_db = 0U,
+    .n_si = 8U,
+};
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_sce_hsp2_rx = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_SCE_HSP2_BASE,
+        .sh_irq = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_SCE_HSP2_SI4,
+        .si_index = 4U,
+    },
+    .n_sm = 8U,
+    .n_ss = 4U,
+    .n_as = 0U,
+    .n_db = 0U,
+    .n_si = 8U,
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/tke-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/tke-tegra-ids.c
new file mode 100644
index 0000000..de91017
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/tke-tegra-ids.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                  // for uint32_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>          // for CT_ASSERT
+#include <soc-common/hw-const.h>     /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>         // for NV_ADDRESS_MAP_AON_TKE_BASE, NV_...
+
+/* Late FSP headers */
+#include <tke/sections-tke.h>        // Immune from CT_ASSERT protection
+#include <tke/tke-tegra-priv.h>      // for tegra_tke_id, FSP__TKE__TKE_TEGR...
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>       // for FSP__PROCESSOR__IRQS_HW_H, NV_AO...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__TKE__TKE_TEGRA_PRIV_H, "Header file missing or invalid.")
+
+const uint32_t tke_top_base = NV_ADDRESS_MAP_FSI_TKE_BASE;
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer0 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_FSI_TKE_TMR_0_BASE,
+        .irq = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_TIMER_INTR0,
+    },
+};
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer1 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_FSI_TKE_TMR_1_BASE,
+        .irq = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_TIMER_INTR1,
+    },
+};
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer2 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_FSI_TKE_TMR_2_BASE,
+        .irq = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_TIMER_INTR2,
+    },
+};
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer3 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_FSI_TKE_TMR_3_BASE,
+        .irq = NV_FSI_SPI_INTR_BASE + NV_FSI_GIC_TIMER_INTR3,
+    },
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/wdt-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/wdt-tegra-ids.c
new file mode 100644
index 0000000..9b9d363
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/fsi/wdt-tegra-ids.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>              // for CT_ASSERT
+#include <soc-common/hw-const.h>         /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>             // for NV_ADDRESS_MAP_AON_TKE_WDT_0...
+
+/* Late FSP headers */
+#include <misc/macros.h>                 // for START_RFD_BLOCK, END_RFD_BLOCK
+#include <watchdog/sections-watchdog.h>  // Immune from CT_ASSERT protection
+#include <watchdog/wdt-tegra-priv.h>     // for tegra_wdt
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>           // for NV_AON_INTERRUPT_WDTFIQ, NV_...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__WATCHDOG__WDT_TEGRA_PRIV_H, "Header file missing or invalid.")
+
+extern struct tegra_wdt tegra_wdt_instance;
+
+SECTION_WATCHDOG_DATA
+struct tegra_wdt tegra_wdt_instance = {
+    .id = {
+        .devname        = "wdt",
+        .base_addr      = NV_ADDRESS_MAP_FSI_TKE_WDT_0_BASE,
+        .irq            = NV_FSI_PPI_INTR_BASE + NV_FSI_GIC_WDT_nIRQ0,
+        .fiq            = NV_FSI_PPI_INTR_BASE + NV_FSI_GIC_WDT_nFIQ0,
+    },
+};
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/ast-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/ast-tegra-ids.c
new file mode 100644
index 0000000..f62ef10
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/ast-tegra-ids.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+const uint32_t ast_tegra_id[] = {
+    NV_ADDRESS_MAP_RCE_AST_0_BASE,
+    NV_ADDRESS_MAP_RCE_AST_1_BASE
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/gpcdma-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/gpcdma-ids.c
new file mode 100644
index 0000000..7ee9723
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/gpcdma-ids.c
@@ -0,0 +1,116 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                 // for CT_ASSERT
+#include <soc-common/hw-const.h>            /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>                // for NV_ADDRESS_MAP_RCE_DMA_BASE
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>             // for INTERRUPT_DMA...
+#include <soc-common/clk-tegra-hw.h>        // for tegra_rst_rce_gpcdma
+#include <gpcdma/gpcdma-priv.h>             // for struct gpcdma_id, gpcdma_channel
+#include <gpcdma/sections-gpcdma.h>         // Immune from CT_ASSERT
+#include <port/gpcdma-port-priv.h>          // Immune from CT_ASSERT
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/macros.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HW_CONFIG__VIC_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__CLK_TEGRA_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPCDMA__GPCDMA_PRIV_H, "Header file missing or invalid.")
+
+SECTION_GPCDMA_RODATA
+const struct gpcdma_hw_handle gpcdma_hw_handle_rce = {
+    .rst = tegra_rst_rce_gpcdma,
+};
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan0;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan1;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan2;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan3;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan4;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan5;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan6;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_channel gpcdma_chan7;
+
+SECTION_GPCDMA_DATA
+struct gpcdma_id gpcdma_id_rce = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_RCE_DMA_BASE,
+        .irqs = {
+            [0] = INTERRUPT_DMA0,
+            [1] = INTERRUPT_DMA1,
+            [2] = INTERRUPT_DMA2,
+            [3] = INTERRUPT_DMA3,
+            [4] = INTERRUPT_DMA4,
+            [5] = INTERRUPT_DMA5,
+            [6] = INTERRUPT_DMA6,
+            [7] = INTERRUPT_DMA7,
+        },
+        .hw_handle = &gpcdma_hw_handle_rce,
+    },
+    .channels = {
+        [0] = &gpcdma_chan0,
+        [1] = &gpcdma_chan1,
+        [2] = &gpcdma_chan2,
+        [3] = &gpcdma_chan3,
+        [4] = &gpcdma_chan4,
+        [5] = &gpcdma_chan5,
+        [6] = &gpcdma_chan6,
+        [7] = &gpcdma_chan7,
+    },
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/hsp-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/hsp-tegra-ids.c
new file mode 100644
index 0000000..3f35ce0
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/hsp-tegra-ids.c
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                       // for UINT32_MAX, UINT8_MAX
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>               // for CT_ASSERT
+#include <soc-common/hw-const.h>          /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>              // for NV_ADDRESS_MAP_DCE_HSP_BASE
+#include <arhsp_shrd_mbox.h>              // for HSP_SHRD_MBOX_MBOX_0_SHRD_M...
+
+/* Late FSP headers */
+#include <hsp/hsp-tegra-priv.h>           // for tegra_hsp_id, FSP__HSP__HSP...
+#include <hsp/sections-hsp.h>             // Immune from CT_ASSERT protection
+
+/* Module-specific FSP headers */
+#include <hw-config/vic-irqs.h>           // for FSP__HW_CONFIG__VIC_IRQS_H
+#include <processor/irqs-hw.h>            // for NV_RCE_IRQ_MBOX, NV_RCE_IRQ...
+#include <soc-common/hsp-tegra-top-hw.h>  // for FSP__SOC_COMMON__HSP_TEGRA_...
+#include <vic/tegra-vic.h>                // for FSP__VIC__TEGRA_VIC_H
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HSP__HSP_TEGRA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HW_CONFIG__VIC_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__HSP_TEGRA_TOP_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__VIC__TEGRA_VIC_H, "Header file missing or invalid.")
+
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_top0 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_TOP0_HSP_BASE,
+        .host = TEGRA_HSP_DB_RCE,
+        .db_irq = NV_RCE_IRQ_TOP0_HSP_DB,
+        .sh_irq = UINT32_MAX,
+        .si_index = UINT8_MAX,
+    },
+};
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_rce = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_RCE_HSP_BASE,
+        .db_irq = UINT32_MAX,
+        .sh_irq = NV_RCE_IRQ_MBOX,
+        .si_index = 0,
+    },
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/irqapi-vic-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/irqapi-vic-ids.c
new file mode 100644
index 0000000..daac7d4
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/irqapi-vic-ids.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP soudce code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+
+const uint32_t vic_base_addr[MAX_VIC_CONTROLLER] ={
+        NV_ADDRESS_MAP_RCE_VIC_0_BASE,
+        NV_ADDRESS_MAP_RCE_VIC_1_BASE
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/tke-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/tke-tegra-ids.c
new file mode 100644
index 0000000..25598ad
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/tke-tegra-ids.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+#include <address_map_new.h>
+
+/* Late FSP headers */
+#include <tke/tke-tegra-priv.h>
+#include <tke/sections-tke.h>                           /* Immune from CT_ASSERT protection */
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>
+#include <soc-common/hw-const.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP soudce code.
+ */
+CT_ASSERT(FSP__TKE__TKE_TEGRA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+const uint32_t tke_top_base = NV_ADDRESS_MAP_RCE_TKE_BASE;
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer0 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_RCE_TKE_TMR_0_BASE,
+        .irq = NV_RCE_IRQ_TIMER0,
+    },
+};
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer1 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_RCE_TKE_TMR_1_BASE,
+        .irq = NV_RCE_IRQ_TIMER1,
+    },
+};
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer2 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_RCE_TKE_TMR_2_BASE,
+        .irq = NV_RCE_IRQ_TIMER2,
+    },
+};
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer3 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_RCE_TKE_TMR_3_BASE,
+        .irq = NV_RCE_IRQ_TIMER3,
+    },
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/wdt-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/wdt-tegra-ids.c
new file mode 100644
index 0000000..7adfbbb
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/rce/wdt-tegra-ids.c
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>              // for CT_ASSERT
+
+/* Hardware headers */
+#include <address_map_new.h>             // for NV_ADDRESS_MAP_DCE_TKE_WDT_0...
+
+/* Late FSP headers */
+#include <misc/macros.h>                 // for START_RFD_BLOCK, END_RFD_BLOCK
+#include <watchdog/wdt-tegra-priv.h>     // for FSP__WATCHDOG__WDT_TEGRA_PRIV_H
+#include <watchdog/sections-watchdog.h>  /* Immune from CT_ASSERT protection */
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>           // for FSP__PROCESSOR__IRQS_HW_H
+#include <soc-common/hw-const.h>         // for FSP__SOC_COMMON__HW_CONST_H
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP soudce code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__WATCHDOG__WDT_TEGRA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+extern struct tegra_wdt tegra_wdt_instance;
+
+SECTION_WATCHDOG_DATA
+struct tegra_wdt tegra_wdt_instance = {
+    .id = {
+        .devname        = "wdt",
+        .base_addr      = NV_ADDRESS_MAP_RCE_TKE_WDT_0_BASE,
+        .irq            = NV_RCE_IRQ_WDTIRQ,
+        .fiq            = NV_RCE_IRQ_WDTFIQ,
+    },
+};
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/sce/ast-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/sce/ast-tegra-ids.c
new file mode 100644
index 0000000..c2e9a85
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/sce/ast-tegra-ids.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+
+const uint32_t ast_tegra_id[] = {
+    NV_ADDRESS_MAP_SCE_AST_0_BASE,
+    NV_ADDRESS_MAP_SCE_AST_1_BASE
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/sce/hsp-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/sce/hsp-tegra-ids.c
new file mode 100644
index 0000000..fadf42a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/sce/hsp-tegra-ids.c
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                       // for UINT32_MAX, UINT8_MAX
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>               // for CT_ASSERT
+#include <soc-common/hw-const.h>          /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>              // for NV_ADDRESS_MAP_DCE_HSP_BASE
+#include <arhsp_shrd_mbox.h>              // for HSP_SHRD_MBOX_MBOX_0_SHRD_M...
+
+/* Late FSP headers */
+#include <hsp/hsp-tegra-priv.h>           // for tegra_hsp_id, FSP__HSP__HSP...
+#include <hsp/sections-hsp.h>             // Immune from CT_ASSERT protection
+
+/* Module-specific FSP headers */
+#include <hw-config/vic-irqs.h>           // for FSP__HW_CONFIG__VIC_IRQS_H
+#include <soc-common/hsp-tegra-top-hw.h>  // for FSP__SOC_COMMON__HSP_TEGRA_...
+#include <vic/tegra-vic.h>                // for FSP__VIC__TEGRA_VIC_H
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HSP__HSP_TEGRA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__HW_CONFIG__VIC_IRQS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__HSP_TEGRA_TOP_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__VIC__TEGRA_VIC_H, "Header file missing or invalid.")
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_top0 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_TOP0_HSP_BASE,
+        .host = TEGRA_HSP_DB_SCE,
+        .db_irq = NV_SCE_IRQ_TOP0_HSP_DB,
+        .sh_irq = UINT32_MAX,
+        .si_index = UINT8_MAX,
+    },
+};
+
+SECTION_HSP_DATA
+struct tegra_hsp_id tegra_hsp_id_rce = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_SCE_HSP_BASE,
+        .db_irq = UINT32_MAX,
+        .sh_irq = NV_SCE_IRQ_MBOX,
+        .si_index = 0,
+    },
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/sce/irqapi-vic-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/sce/irqapi-vic-ids.c
new file mode 100644
index 0000000..65582f7
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/sce/irqapi-vic-ids.c
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+#include <soc-common/hw-const.h>                        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>
+
+/* Late FSP headers */
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP soudce code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+
+uint32_t vic_base_addr[MAX_VIC_CONTROLLER] ={
+        NV_ADDRESS_MAP_SCE_VIC_0_BASE,
+        NV_ADDRESS_MAP_SCE_VIC_1_BASE
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/sce/tke-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/sce/tke-tegra-ids.c
new file mode 100644
index 0000000..b31e51f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/sce/tke-tegra-ids.c
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2016-2020, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+#include <address_map_new.h>
+
+/* Late FSP headers */
+#include <tke/tke-tegra-priv.h>
+#include <tke/sections-tke.h>                           /* Immune from CT_ASSERT protection */
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>
+#include <soc-common/hw-const.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP soudce code.
+ */
+CT_ASSERT(FSP__TKE__TKE_TEGRA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+
+const uint32_t tke_top_base = NV_ADDRESS_MAP_SCE_TKE_BASE;
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer0 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_SCE_TKE_TMR_0_BASE,
+        .irq = NV_SCE_IRQ_TIMER0,
+    },
+};
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer1 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_SCE_TKE_TMR_1_BASE,
+        .irq = NV_SCE_IRQ_TIMER1,
+    },
+};
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer2 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_SCE_TKE_TMR_2_BASE,
+        .irq = NV_SCE_IRQ_TIMER2,
+    },
+};
+
+SECTION_TKE_DATA
+struct tegra_tke_id tegra_tke_id_timer3 = {
+    .conf = {
+        .base_addr = NV_ADDRESS_MAP_SCE_TKE_TMR_3_BASE,
+        .irq = NV_SCE_IRQ_TIMER3,
+    },
+};
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/sce/wdt-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/sce/wdt-tegra-ids.c
new file mode 100644
index 0000000..800c4bb
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/sce/wdt-tegra-ids.c
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>              // for CT_ASSERT
+
+/* Hardware headers */
+#include <address_map_new.h>             // for NV_ADDRESS_MAP_DCE_TKE_WDT_0...
+
+/* Late FSP headers */
+#include <misc/macros.h>                 // for START_RFD_BLOCK, END_RFD_BLOCK
+#include <watchdog/wdt-tegra-priv.h>     // for FSP__WATCHDOG__WDT_TEGRA_PRIV_H
+#include <watchdog/sections-watchdog.h>  /* Immune from CT_ASSERT protection */
+
+/* Module-specific FSP headers */
+#include <processor/irqs-hw.h>           // for FSP__PROCESSOR__IRQS_HW_H
+#include <soc-common/hw-const.h>         // for FSP__SOC_COMMON__HW_CONST_H
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP soudce code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__WATCHDOG__WDT_TEGRA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__IRQS_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+
+extern struct tegra_wdt tegra_wdt_instance;
+
+SECTION_WATCHDOG_DATA
+struct tegra_wdt tegra_wdt_instance = {
+    .id = {
+        .devname        = "wdt",
+        .base_addr      = NV_ADDRESS_MAP_SCE_TKE_WDT_0_BASE,
+        .irq            = NV_SCE_IRQ_WDTIRQ,
+        .fiq            = NV_SCE_IRQ_WDTFIQ,
+    },
+};
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Rule_8_7, "Approval: Bug 200531999, DR: SWE-FSP-015-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/soc-common/clk-tegra.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/soc-common/clk-tegra.c
new file mode 100644
index 0000000..5c18b84
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/soc-common/clk-tegra.c
@@ -0,0 +1,515 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                // for bool
+#include <stdint.h>                 // for uint32_t, int32_t, uint8_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>         // for CT_ASSERT
+#include <soc-common/hw-const.h>    /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>        // for NV_ADDRESS_MAP_CAR_BASE
+#include <arclk_rst.h>              // for CLK_RST_CONTROLLER_OSC_CTRL_0_OSC...
+
+/* Late FSP headers */
+#include <chipid/chip-id.h>         // for tegra_platform_is_silicon
+#include <clk/clk-tegra.h>          // for tegra_clk_disable, tegra_clk_enable
+#ifdef _NV_BUILD_FPGA_
+#include <clk-tegra-hw-cpu.h>       /* Immune from CT_ASSERT protection */
+#endif
+#include <delay/delay.h>            // for udelay
+#include <misc/bitops.h>            // for BIT
+#include <misc/nvrm_drf.h>          // for NV_DRF_DEF, NV_FIELD_HIGHBIT, NV_...
+#include <reg-access/reg-access.h>  // for writel, readl
+#include <chipid/chip-id.h>         // for tegra_platform_is_fpga
+
+/* Module-specific FSP header files */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CHIPID__CHIP_ID_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CLK__CLK_TEGRA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DELAY__DELAY_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__NVRM_DRF_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_0                0x00
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SET_0            0x04
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_CLR_0            0x08
+
+#define CLK_RST_CONTROLLER_RST_DEV_0                    0x00
+#define CLK_RST_CONTROLLER_RST_DEV_SET_0                0x04
+#define CLK_RST_CONTROLLER_RST_DEV_CLR_0                0x08
+
+#define LOWBIT     0
+#define HIGHBIT    1
+#define FIELD_RANGE(x) { \
+        [LOWBIT]  = NV_FIELD_LOWBIT(x), \
+        [HIGHBIT] = NV_FIELD_HIGHBIT(x) \
+}
+
+struct tegra_clk {
+        uint32_t enb_base_reg;
+        uint32_t src_reg;
+        uint8_t div_range[2]; /* [0]=LOWBIT [1]=HIGHBIT */
+        uint32_t div_enb; /* 0 if enable bit is not available */
+        uint8_t frac_width;
+        uint32_t clk_src;
+        const struct tegra_parent_clk *parent;
+};
+
+struct tegra_parent_clk {
+        uint32_t rate;
+};
+
+struct tegra_rst {
+        uint32_t rst_base_reg;
+};
+
+struct tegra_parent_clk tegra_parent_clk_osc_undiv_data = {
+        .rate = 0,
+};
+
+struct tegra_parent_clk tegra_parent_clk_pll_p_data = {
+        .rate = 408000000,
+};
+
+struct tegra_parent_clk tegra_parent_clk_pll_aon_data = {
+        .rate = 0,
+};
+
+const struct tegra_clk tegra_clk_uarta_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0,
+        .div_range = FIELD_RANGE(CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR),
+#if defined(_NV_BUILD_FPGA_) || defined(_NV_BUILD_LINSIM_)
+        .div_enb = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_UARTA, UARTA_DIV_ENB, DISABLE),
+#else
+        .div_enb = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_UARTA, UARTA_DIV_ENB, ENABLE),
+#endif
+        .frac_width = 1,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_UARTA, UARTA_CLK_SRC, PLLP_OUT0),
+        .parent = &tegra_parent_clk_pll_p_data,
+};
+
+const struct tegra_rst tegra_rst_uarta_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_UARTA_0,
+};
+
+const struct tegra_clk tegra_clk_uartb_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0,
+        .div_range = FIELD_RANGE(CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR),
+        .div_enb = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_UARTB, UARTB_DIV_ENB, ENABLE),
+        .frac_width = 1,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_UARTB, UARTB_CLK_SRC, PLLP_OUT0),
+        .parent = &tegra_parent_clk_pll_p_data,
+};
+
+const struct tegra_rst tegra_rst_uartb_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_UARTB_0,
+};
+
+const struct tegra_clk tegra_clk_uartc_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0,
+        .div_range = FIELD_RANGE(CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR),
+        .div_enb = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_UARTC, UARTC_DIV_ENB, ENABLE),
+        .frac_width = 1,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_UARTC, UARTC_CLK_SRC, OSC_UNDIV),
+        .parent = &tegra_parent_clk_osc_undiv_data,
+};
+
+const struct tegra_rst tegra_rst_uartc_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_UARTC_0,
+};
+
+const struct tegra_clk tegra_clk_uartf_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0,
+        .div_range = FIELD_RANGE(CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR),
+        .div_enb = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_UARTF, UARTF_DIV_ENB, ENABLE),
+        .frac_width = 1,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_UARTF, UARTF_CLK_SRC, PLLP_OUT0),
+        .parent = &tegra_parent_clk_pll_p_data,
+};
+
+const struct tegra_rst tegra_rst_uartf_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_UARTF_0,
+};
+
+const struct tegra_clk tegra_clk_uarth_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0,
+        .div_range = FIELD_RANGE(CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR),
+        .div_enb = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_UARTH, UARTH_DIV_ENB, ENABLE),
+        .frac_width = 1,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_UARTH, UARTH_CLK_SRC, PLLP_OUT0),
+        .parent = &tegra_parent_clk_pll_p_data,
+};
+
+const struct tegra_rst tegra_rst_uarth_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_UARTH_0,
+};
+
+const struct tegra_clk tegra_clk_uartj_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTJ_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ_0,
+        .div_range = FIELD_RANGE(CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ_0_UARTJ_CLK_DIVISOR),
+        .div_enb = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_UARTJ, UARTJ_DIV_ENB, ENABLE),
+        .frac_width = 1,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_UARTJ, UARTJ_CLK_SRC, OSC_UNDIV),
+        .parent = &tegra_parent_clk_osc_undiv_data,
+};
+
+const struct tegra_rst tegra_rst_uartj_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_UARTJ_0,
+};
+
+const struct tegra_clk tegra_clk_aon_i2c_slow_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0,
+        .div_range = FIELD_RANGE(CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR),
+        .div_enb = 0,
+        .frac_width = 1,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_AON_I2C_SLOW, AON_I2C_SLOW_CLK_SRC, PLLP_OUT0),
+        .parent = &tegra_parent_clk_pll_p_data,
+};
+
+const struct tegra_clk tegra_clk_i2c_slow_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0,
+        .div_range = FIELD_RANGE(CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR),
+        .div_enb = 0,
+        .frac_width = 1,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_I2C_SLOW, I2C_SLOW_CLK_SRC, PLLP_OUT0),
+        .parent = &tegra_parent_clk_pll_p_data,
+};
+
+const struct tegra_clk tegra_clk_i2c1_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0,
+        .div_range = FIELD_RANGE(CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR),
+        .div_enb = 0,
+        .frac_width = 0,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_I2C1, I2C1_CLK_SRC, PLLP_OUT0),
+        .parent = &tegra_parent_clk_pll_p_data,
+};
+
+const struct tegra_rst tegra_rst_i2c1_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_I2C1_0,
+};
+
+const struct tegra_clk tegra_clk_i2c2_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0,
+        .div_range = FIELD_RANGE(CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR),
+        .div_enb = 0,
+        .frac_width = 0,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_I2C2, I2C2_CLK_SRC, PLLP_OUT0),
+        .parent = &tegra_parent_clk_pll_p_data,
+};
+
+const struct tegra_rst tegra_rst_i2c2_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_I2C2_0,
+};
+
+const struct tegra_clk tegra_clk_i2c3_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0,
+        .div_range = FIELD_RANGE(CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR),
+        .div_enb = 0,
+        .frac_width = 0,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_I2C3, I2C3_CLK_SRC, PLLP_OUT0),
+        .parent = &tegra_parent_clk_pll_p_data,
+};
+
+const struct tegra_rst tegra_rst_i2c3_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_I2C3_0,
+};
+
+const struct tegra_clk tegra_clk_i2c4_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0,
+        .div_range = FIELD_RANGE(CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR),
+        .div_enb = 0,
+        .frac_width = 0,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_I2C4, I2C4_CLK_SRC, PLLP_OUT0),
+        .parent = &tegra_parent_clk_pll_p_data,
+};
+
+const struct tegra_rst tegra_rst_i2c4_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_I2C4_0,
+};
+
+const struct tegra_clk tegra_clk_i2c6_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0,
+        .div_range = FIELD_RANGE(CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR),
+        .div_enb = 0,
+        .frac_width = 0,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_I2C6, I2C6_CLK_SRC, PLLP_OUT0),
+        .parent = &tegra_parent_clk_pll_p_data,
+};
+
+const struct tegra_rst tegra_rst_i2c6_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_I2C6_0,
+};
+
+const struct tegra_clk tegra_clk_i2c7_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0,
+        .div_range = FIELD_RANGE(CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR),
+        .div_enb = 0,
+        .frac_width = 0,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_I2C7, I2C7_CLK_SRC, PLLP_OUT0),
+        .parent = &tegra_parent_clk_pll_p_data,
+};
+
+const struct tegra_rst tegra_rst_i2c7_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_I2C7_0,
+};
+
+const struct tegra_clk tegra_clk_i2c8_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0,
+        .div_range = FIELD_RANGE(CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR),
+        .div_enb = 0,
+        .frac_width = 0,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_I2C8, I2C8_CLK_SRC, PLLP_OUT0),
+        .parent = &tegra_parent_clk_pll_p_data,
+};
+
+const struct tegra_rst tegra_rst_i2c8_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_I2C8_0,
+};
+
+const struct tegra_rst tegra_rst_aon_gpcdma_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0,
+};
+
+const struct tegra_rst tegra_rst_sce_gpcdma_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0,
+};
+
+const struct tegra_rst tegra_rst_rce_gpcdma_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0,
+};
+
+const struct tegra_rst tegra_rst_dce_gpcdma_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_DCE_DMA_0,
+};
+
+const struct tegra_clk tegra_clk_aodmic_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0,
+        .div_range = FIELD_RANGE(CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR),
+        .div_enb = 0,
+        .frac_width = 1,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER,CLK_SOURCE_DMIC5, DMIC5_CLK_SRC, OSC_UNDIV),
+        .parent = &tegra_parent_clk_osc_undiv_data,
+};
+
+const struct tegra_rst tegra_rst_aodmic_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_DMIC5_0,
+};
+
+const struct tegra_clk tegra_clk_spi1_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0,
+        .div_range = FIELD_RANGE((uint8_t)CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR),
+        .div_enb = 0,
+        .frac_width = 1,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_SPI1, SPI1_CLK_SRC, PLLP_OUT0),
+        .parent = &tegra_parent_clk_pll_p_data,
+};
+
+const struct tegra_rst tegra_rst_spi1_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_SPI1_0,
+};
+
+const struct tegra_clk tegra_clk_spi2_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0,
+        .div_range = FIELD_RANGE(CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR),
+        .div_enb = 0,
+        .frac_width = 1,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_SPI2, SPI2_CLK_SRC, PLLP_OUT0),
+        .parent = &tegra_parent_clk_pll_p_data,
+};
+
+const struct tegra_rst tegra_rst_spi2_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_SPI2_0,
+};
+
+const struct tegra_clk tegra_clk_spi3_data = {
+        .enb_base_reg = CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0,
+        .src_reg = CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0,
+        .div_range = FIELD_RANGE((uint8_t)CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR),
+        .div_enb = 0,
+        .frac_width = 1,
+        .clk_src = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_SPI3, SPI3_CLK_SRC, PLLP_OUT0),
+        .parent = &tegra_parent_clk_pll_p_data,
+};
+
+const struct tegra_rst tegra_rst_spi3_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_SPI3_0,
+};
+
+const struct tegra_rst tegra_rst_can0_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_CAN1_0,
+};
+
+const struct tegra_rst tegra_rst_can1_data = {
+        .rst_base_reg = CLK_RST_CONTROLLER_RST_DEV_CAN2_0,
+};
+
+int32_t tegra_clk_init(void)
+{
+        uint32_t osc_undiv_rate = 38400000;
+        uint32_t val;
+        uint32_t osc_freq;
+
+        if (tegra_platform_is_fpga()) {
+            tegra_parent_clk_osc_undiv_data.rate = 19200000;
+            goto out;
+        }
+
+        val = readl(NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_OSC_CTRL_0);
+
+        osc_freq = NV_DRF_VAL(CLK_RST_CONTROLLER, OSC_CTRL, OSC_FREQ, val);
+        switch (osc_freq) {
+        case 0:
+                osc_undiv_rate = 13000000;
+                break;
+        case 1:
+                osc_undiv_rate = 16800000;
+                break;
+        case 4:
+                osc_undiv_rate = 19200000;
+                break;
+        case 5:
+                osc_undiv_rate = 38400000;
+                break;
+        case 8:
+                osc_undiv_rate = 12000000;
+                break;
+        case 9:
+                osc_undiv_rate = 48000000;
+                break;
+        case 12:
+                osc_undiv_rate = 26000000;
+                break;
+        default:
+                osc_undiv_rate = 38400000;
+                break;
+        }
+
+        tegra_parent_clk_osc_undiv_data.rate = osc_undiv_rate;
+out:
+        return 0;
+}
+
+int32_t tegra_clk_enable(const struct tegra_clk *clk)
+{
+        writel(BIT(0), NV_ADDRESS_MAP_CAR_BASE + clk->enb_base_reg + CLK_RST_CONTROLLER_CLK_OUT_ENB_SET_0);
+        return 0;
+}
+
+int32_t tegra_clk_disable(const struct tegra_clk *clk)
+{
+        writel(BIT(0), NV_ADDRESS_MAP_CAR_BASE + clk->enb_base_reg + CLK_RST_CONTROLLER_CLK_OUT_ENB_CLR_0);
+        return 0;
+}
+
+bool tegra_clk_is_clk_enabled(const struct tegra_clk *clk)
+{
+    uint32_t clk_en_sts;
+
+    clk_en_sts = readl(NV_ADDRESS_MAP_CAR_BASE + clk->enb_base_reg);
+    return ((BIT(0) & clk_en_sts) != 0UL);
+}
+
+bool tegra_reset_is_reset_deasserted(const struct tegra_rst *rst)
+{
+    uint32_t reset_sts;
+
+    reset_sts = readl(NV_ADDRESS_MAP_CAR_BASE + rst->rst_base_reg);
+    return ((BIT(0) & reset_sts) != 0UL);
+}
+
+int32_t tegra_clk_reset_set(const struct tegra_rst *rst)
+{
+        writel(BIT(0), NV_ADDRESS_MAP_CAR_BASE + rst->rst_base_reg + CLK_RST_CONTROLLER_RST_DEV_SET_0);
+        return 0;
+}
+
+int32_t tegra_clk_reset_clear(const struct tegra_rst *rst)
+{
+        writel(BIT(0), NV_ADDRESS_MAP_CAR_BASE + rst->rst_base_reg + CLK_RST_CONTROLLER_RST_DEV_CLR_0);
+        return 0;
+}
+
+int32_t tegra_clk_reset_pulse(const struct tegra_rst *rst, uint32_t delay_us)
+{
+        int32_t ret;
+
+        ret = tegra_clk_reset_set(rst);
+        if (ret)
+                return ret;
+
+        if (tegra_platform_is_silicon()) {
+                udelay(delay_us);
+        }
+
+        return tegra_clk_reset_clear(rst);
+}
+
+int32_t tegra_clk_set_rate(const struct tegra_clk *clk, uint32_t rate_hz)
+{
+        uint32_t divisor;
+        uint32_t val;
+
+        /*
+         * For now, we always round to ensure the clock runs no faster than
+         * the requested rate. If some clocks need other rounding options,
+         * we can add flags to struct tegra_clk for that.
+         */
+        divisor = (((clk->parent->rate) << clk->frac_width) + rate_hz - 1) / rate_hz;
+        divisor -= (1 << clk->frac_width);
+        if (divisor & ~NV_DYN_FIELD_MASK(clk->div_range[HIGHBIT], clk->div_range[LOWBIT]))
+                return 1;
+
+        val = NV_DYN_FIELD_BITS(divisor, clk->div_range[HIGHBIT], clk->div_range[LOWBIT]) |
+              clk->clk_src | clk->div_enb;
+
+        writel(val, NV_ADDRESS_MAP_CAR_BASE + clk->src_reg);
+
+        return 0;
+}
+
+int32_t tegra_parent_clk_set_rate(struct tegra_parent_clk *clk, uint32_t rate_hz)
+{
+        clk->rate = rate_hz;
+        return 0;
+}
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/ids/soc-common/uart-tegra-ids.c b/spe-freertos-bsp/fsp/source/soc/t234/ids/soc-common/uart-tegra-ids.c
new file mode 100644
index 0000000..950a3f9
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/ids/soc-common/uart-tegra-ids.c
@@ -0,0 +1,168 @@
+/*
+ * Copyright (c) 2016-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * NVIDIA CORPORATION and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA CORPORATION is strictly prohibited.
+ */
+
+/* Compiler headers */
+#include <stddef.h>                          // for NULL
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                  // for CT_ASSERT
+#include <soc-common/hw-const.h>             // Must appear before any hwinc files
+
+/* Hardware headers */
+#include <address_map_new.h>                 // for NV_ADDRESS_MAP_UARTF_BASE
+
+/* Late FSP headers */
+#include <misc/macros.h>                     // for START_RFD_BLOCK, END_RFD_BLOCK, INLINE_RFD
+#include <processor/tegra-uart-hw-params.h>  // for TEGRA_UARTF_ENABLED, TEG...
+#include <uart/tegra-uart-priv.h>            // for FSP__UART__TEGRA_UART_PR...
+
+/* Module-specific FSP header files */
+#include <soc-common/clk-tegra-hw.h>         // for FSP__SOC_COMMON__CLK_TEG...
+
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__UART__TEGRA_UART_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__CLK_TEGRA_HW_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_2_3, "Approval:  On-file, DR: SWE-FSP-010-SWSADR.docx")
+
+#ifdef TEGRA_UARTA_ENABLED
+#ifdef UART_CLOCKS
+const struct uart_hw_handle uarta_hw_handle = {
+        .clk = tegra_clk_uarta,
+        .rst = tegra_rst_uarta,
+};
+#endif
+
+struct tegra_uart_ctlr tegra_uart_ctlr_uarta = {
+        .id = {
+                .base_addr = NV_ADDRESS_MAP_UARTA_BASE,
+#ifdef UART_CLOCKS
+                .hw_handle  = &uarta_hw_handle,
+#else
+                .hw_handle = NULL,
+#endif
+                .irq = TEGRA_UARTA_IRQ,
+        },
+        .initialized = false,
+};
+extern struct tegra_uart_id tegra_uart_id_uarta __attribute__((alias("tegra_uart_ctlr_uarta")));
+#endif
+
+#ifdef TEGRA_UARTC_ENABLED
+#ifdef UART_CLOCKS
+const struct uart_hw_handle uartc_hw_handle = {
+        .clk = tegra_clk_uartc,
+        .rst = tegra_rst_uartc,
+};
+#endif
+
+struct tegra_uart_ctlr tegra_uart_ctlr_uartc = {
+        .id = {
+                .base_addr = NV_ADDRESS_MAP_UARTC_BASE,
+#ifdef UART_CLOCKS
+                .hw_handle  = &uartc_hw_handle,
+#else
+                .hw_handle = NULL,
+#endif
+                .irq = TEGRA_UARTC_IRQ,
+        },
+        .initialized = false,
+};
+extern struct tegra_uart_id tegra_uart_id_uartc __attribute__((alias("tegra_uart_ctlr_uartc")));
+#endif
+
+#ifdef TEGRA_UARTF_ENABLED
+#ifdef UART_CLOCKS
+const struct uart_hw_handle uartf_hw_handle = {
+        .clk = tegra_clk_uartf,
+        .rst = tegra_rst_uartf,
+};
+#endif
+
+struct tegra_uart_ctlr tegra_uart_ctlr_uartf = {
+        .id = {
+                .base_addr = NV_ADDRESS_MAP_UARTF_BASE,
+#ifdef UART_CLOCKS
+                .hw_handle  = &uartf_hw_handle,
+#else
+                .hw_handle = NULL,
+#endif
+                .irq = TEGRA_UARTF_IRQ,
+        },
+        .initialized = false,
+};
+extern struct tegra_uart_id tegra_uart_id_uartf __attribute__((alias("tegra_uart_ctlr_uartf")));
+#endif
+
+#ifdef TEGRA_UARTH_ENABLED
+#ifdef UART_CLOCKS
+const struct uart_hw_handle uarth_hw_handle = {
+        .clk = tegra_clk_uarth,
+        .rst = tegra_rst_uarth,
+};
+#endif
+
+struct tegra_uart_ctlr tegra_uart_ctlr_uarth = {
+        .id = {
+                .base_addr = NV_ADDRESS_MAP_UARTH_BASE,
+#ifdef UART_CLOCKS
+                .hw_handle  = &uarth_hw_handle,
+#else
+                .hw_handle = NULL,
+#endif
+                .irq = TEGRA_UARTH_IRQ,
+        },
+        .initialized = false,
+};
+
+extern struct tegra_uart_id tegra_uart_id_uarth __attribute__((alias("tegra_uart_ctlr_uarth")));
+
+#endif
+
+#ifdef TEGRA_UARTJ_ENABLED
+#ifdef UART_CLOCKS
+const struct uart_hw_handle uartj_hw_handle = {
+        .clk = tegra_clk_uartj,
+        .rst = tegra_rst_uartj,
+};
+#endif
+
+struct tegra_uart_ctlr tegra_uart_ctlr_uartj = {
+        .id = {
+                .base_addr = NV_ADDRESS_MAP_UARTJ_BASE,
+#ifdef UART_CLOCKS
+                .hw_handle  = &uartj_hw_handle,
+#else
+                .hw_handle = NULL,
+#endif
+                .irq = TEGRA_UARTJ_IRQ,
+        },
+        .initialized = false,
+};
+extern struct tegra_uart_id tegra_uart_id_uartj __attribute__((alias("tegra_uart_ctlr_uartj")));
+#endif
+
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/module-soc-t234-config.mk b/spe-freertos-bsp/fsp/source/soc/t234/module-soc-t234-config.mk
new file mode 100644
index 0000000..123abcc
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/module-soc-t234-config.mk
@@ -0,0 +1,55 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-soc-t234-config.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_SOC_CONFIG               := 1
+MODULE_SOC_T234_CONFIG          := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+MODULE_SOC_DEPENDS              :=
+$(foreach _,$(MODULE_SOC_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# Define SOC variables
+HW_PLATFORM                      = t23x
+SOC                              = t234
+
+#
+# Include <hwinc-*> directory rules
+ifndef NV_HWINC_T23X_CL
+include $(TEGRA_TOP)/hwinc-$(HW_PLATFORM)/rules.mk
+endif
+
+#
+# Location of source code files
+MODULE_SOC_T234_SOURCE_DIR       =
+
+#
+# Common includes '-I <INCLUDEDIR>'
+MODULE_SOC_T234_INCLUDES         = -I $(TEGRA_TOP)/hwinc-$(HW_PLATFORM)/$(NV_HWINC_T23X_CL)/$(HW_PLATFORM)
+MODULE_SOC_T234_INCLUDES        += -I $(TEGRA_TOP)/hwinc-private/$(HW_PLATFORM)/$(NV_HWINC_T23X_CL)/$(HW_PLATFORM)
+MODULE_SOC_T234_INCLUDES        += -I $(FSP_COMMON_REPO)/include/soc/$(SOC)
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/module-soc-t234.mk b/spe-freertos-bsp/fsp/source/soc/t234/module-soc-t234.mk
new file mode 100644
index 0000000..b632e77
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/module-soc-t234.mk
@@ -0,0 +1,62 @@
+#
+# Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+#
+# NVIDIA CORPORATION and its licensors retain all intellectual property
+# and proprietary rights in and to this software, related documentation
+# and any modifications thereto.  Any use, reproduction, disclosure or
+# distribution of this software and related documentation without an express
+# license agreement from NVIDIA CORPORATION is strictly prohibited.
+#
+
+#
+# Print makefile diagnostic message
+ifeq ($(VERBOSE), 1)
+$(info Including:  module-soc-t234.mk)
+endif
+
+#
+# Table of Contents:
+#   TOC:  Define the module name
+#   TOC:  Declare the module dependencies and check them
+#   TOC:  Declare the source directories, which automatically adds them to VPATH
+#   TOC:  Declare the include file directories needed by this module
+#   TOC:  Declare the C language files
+#   TOC:  Declare the Assembly language files
+#   TOC:  Declare C-Flags used by this module
+#   TOC:  Declare ASM-Flags used by this module
+
+#
+# Define module name:
+#   Once the module name is defined, it will be added to the MODULE_NAMES
+#   list.  This can be done manually (like it is here), or automatically
+#   on a per-application basis.
+MODULE_SOC_T234_NAME            := SOC_T234
+
+#
+# Define a something similar to header guard protection...for makefiles instead.
+#   This definition must exist for all 'module-soc_*.mk' files.
+MODULE_SOC_DEFINED              := 1
+
+#
+# Check for sub-make module dependencies.  For each of the module dependencies
+#   defined below, they must exist in the build before this (current) sub-make
+#   is called.
+CONFIG_SOC_DEPENDS              := SOC SOC_T234
+$(foreach _,$(CONFIG_SOC_DEPENDS),$(eval $(call CHECK_MAKEFILE_DEFINED,$_)))
+
+#
+# C Source
+MODULE_SOC_T234_C_SRC            =
+MODULE_SOC_T234_C_SRC           += $(CPL_SOC_IDS_CMN)/clk-tegra.c
+
+#
+# Assembly source
+MODULE_SOC_T234_ASM_SRC          =
+
+#
+# Special C Flags
+MODULE_SOC_T234_C_FLAGS          =
+
+#
+# Special ASM Flags
+MODULE_SOC_T234_ASM_FLAGS        =
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/aon/aodmic-port.c b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/aodmic-port.c
new file mode 100644
index 0000000..354701b
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/aodmic-port.c
@@ -0,0 +1,135 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                   // for uint8_t, uintptr_t, int32_t
+#include <stdio.h>                    // for NULL
+                                      // IWYU pragma: no_include <errno.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>           // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>      // for MODULE_ID_AODMIC, E_SUCCESS
+#include <chipid/chip-id.h>           // for tegra_platform_is_fpga
+#include <clk/clk-tegra.h>            // for tegra_clk_disable, tegra_clk_en...
+#include <misc/macros.h>              // for END_RFD_BLOCK, START_RFD_BLOCK
+#include <soc-common/clk-tegra-hw.h>  // for tegra_clk_enable, ...
+
+/* Module-specific FSP headers */
+#include <aodmic/aodmic-errors.h>     // for E_AODMIC_NULL_POINTER, E_AODMIC...
+#include <aodmic/sections-aodmic.h>   // for SECTION_AODMIC_...
+#include <port/aodmic-port.h>         // for aodmic_port_clock_reset_config, ...
+#include <port/aodmic-port-priv.h>    // for aodmic_port_clk_rst
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CHIPID__CHIP_ID_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CLK__CLK_TEGRA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__CLK_TEGRA_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__AODMIC__AODMIC_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PORT__AODMIC_PORT_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+
+SECTION_AODMIC_RODATA
+const struct aodmic_port_clk_rst aodmic_port_clk_rst_aon = {
+    .clk = tegra_clk_aodmic,
+    .rst = tegra_rst_aodmic,
+};
+
+SECTION_AODMIC_INIT_TEXT error_t
+aodmic_port_clock_reset_config(const struct aodmic_port_clk_rst *hw_handle)
+{
+    error_t ret_val = E_SUCCESS;
+
+    if (hw_handle == NULL) {
+        ret_val = E_AODMIC_NULL_POINTER;
+        goto out;
+    }
+
+    if(!tegra_platform_is_fpga()) {
+        /* Enable AODMIC clock */
+        tegra_clk_enable(hw_handle->clk);
+        tegra_clk_reset_pulse(hw_handle->rst, 2);
+    }
+
+out:
+    return ret_val;
+}
+
+SECTION_AODMIC_TEXT error_t
+aodmic_port_clock_disable(const struct aodmic_port_clk_rst *hw_handle)
+{
+    error_t ret_val = E_SUCCESS;
+
+    if (hw_handle == NULL) {
+        ret_val = E_AODMIC_NULL_POINTER;
+        goto out;
+    }
+
+    tegra_clk_disable(hw_handle->clk);
+
+out:
+    return ret_val;
+}
+
+SECTION_AODMIC_INIT_TEXT error_t
+aodmic_port_clock_set_rate(const struct aodmic_port_clk_rst *hw_handle,
+                           uint32_t sample_rate)
+{
+    int32_t status;
+    error_t ret_val = E_SUCCESS;
+
+    if (hw_handle == NULL) {
+        ret_val = E_AODMIC_NULL_POINTER;
+        goto out;
+    }
+
+    status = tegra_clk_set_rate(hw_handle->clk, sample_rate);
+    if (status) {
+        ret_val = E_AODMIC_CLK_RATE_ERROR;
+    }
+
+out:
+    return ret_val;
+}
+
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/aon/gpcdma-irq.S b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/gpcdma-irq.S
new file mode 100644
index 0000000..7d5600a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/gpcdma-irq.S
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sections/sections.h>
+#include <vic/vic-asm.h>
+#include <hw-config/vic-irqs.h>
+#include <processor/gpcdma-hw.h>
+#include <gpcdma/sections-gpcdma.h>
+
+    .section    SECTION_STR_GPCDMA_TEXT, "ax"
+    .arm
+    .syntax     unified
+
+    /**
+     * GPCDMA per channel interrupt handlers
+     * GPCDMA_CHAN[0-7] should be defined by the soc includes
+     */
+    isr_addr DMA0_isr, GPCDMA_CHAN0, gpcdma_chan_irq, INTERRUPT_DMA0
+    isr_addr DMA1_isr, GPCDMA_CHAN1, gpcdma_chan_irq, INTERRUPT_DMA1
+    isr_addr DMA2_isr, GPCDMA_CHAN2, gpcdma_chan_irq, INTERRUPT_DMA2
+    isr_addr DMA3_isr, GPCDMA_CHAN3, gpcdma_chan_irq, INTERRUPT_DMA3
+    isr_addr DMA4_isr, GPCDMA_CHAN4, gpcdma_chan_irq, INTERRUPT_DMA4
+    isr_addr DMA5_isr, GPCDMA_CHAN5, gpcdma_chan_irq, INTERRUPT_DMA5
+    isr_addr DMA6_isr, GPCDMA_CHAN6, gpcdma_chan_irq, INTERRUPT_DMA6
+    isr_addr DMA7_isr, GPCDMA_CHAN7, gpcdma_chan_irq, INTERRUPT_DMA7
+
+    /**
+     * Defines the portion of the ISR map array for GPCDMA
+     */
+    .section    SECTION_STR_VIC_ISRMAP_DATA, "a"
+
+    isr_map_entry    INTERRUPT_DMA0, DMA0_isr
+    isr_map_entry    INTERRUPT_DMA1, DMA1_isr
+    isr_map_entry    INTERRUPT_DMA2, DMA2_isr
+    isr_map_entry    INTERRUPT_DMA3, DMA3_isr
+    isr_map_entry    INTERRUPT_DMA4, DMA4_isr
+    isr_map_entry    INTERRUPT_DMA5, DMA5_isr
+    isr_map_entry    INTERRUPT_DMA6, DMA6_isr
+    isr_map_entry    INTERRUPT_DMA7, DMA7_isr
+
+    .end
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/aon/gpcdma-port.c b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/gpcdma-port.c
new file mode 100644
index 0000000..18ce545
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/gpcdma-port.c
@@ -0,0 +1,295 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                   // for uint32_t, uint8_t, UINT32_...
+#include <stddef.h>                   // for NULL
+#include <stdbool.h>                  // for bool
+                                      // IWYU pragma: no_include <errno.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>           // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <osa/rtos-task.h>            // for rtosTaskYieldFromISR
+#include <osa/rtos-semaphore.h>       // for rtosSemaphore...
+#include <osa/rtos-queue.h>	          // for rtosQueue
+#include <osa/rtos-values.h>          // for rtosBool
+#include <misc/attributes.h>          // for ALIGN
+#include <misc/macros.h>              // for ARRAY_SIZE
+#include <error/common-errors.h>      // for error_t, E_SUCCESS
+#include <clk/clk-tegra.h>            // for tegra_clk_reset_pulse
+
+/* Module specific headers */
+#include <gpcdma/gpcdma-errors.h>     // for E_GPCDMA_NULL_PTR, E_GPCDMA_...
+#include <gpcdma/gpcdma-priv.h>       // for struct gpcdma_id, gpcdma_channel...
+#include <gpcdma/gpcdma-port.h>       // for gpcdma_port_...
+#include <port/gpcdma-port-priv.h>    // Immune from CT_ASSERT protection
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/macros.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_SEMAPHORE_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_QUEUE_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_VALUES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CLK__CLK_TEGRA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPCDMA__GPCDMA_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPCDMA__GPCDMA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPCDMA__GPCDMA_PORT_H, "Header file missing or invalid.")
+
+static rtosSemaphoreHandle  chan_sems[TEGRA_GPCDMA_NUM_CHANNELS];
+static uint8_t              chan_sem_bufs[TEGRA_GPCDMA_NUM_CHANNELS][rtosSemaphoreSize()];
+
+/* Queue is only used during GPCDMA cyclic mode */
+#define GPCDMA_NUM_EL		     64UL /* Means 64 buf descriptors */
+#define GPCDMA_QUEUE_SIZE        rtosQueueSize(GPCDMA_NUM_EL, \
+                                               sizeof(struct gpcdma_buf_desc))
+static rtosQueueHandle chan_que[TEGRA_GPCDMA_NUM_CHANNELS];
+static uint8_t         chan_que_bufs[TEGRA_GPCDMA_NUM_CHANNELS][GPCDMA_QUEUE_SIZE];
+/* Adjust GPCDMA_NUM_EL based on application requirement */
+
+static inline bool is_dma_chan_valid(uint32_t chan_num)
+{
+    return chan_num < (uint32_t)TEGRA_GPCDMA_NUM_CHANNELS;
+}
+
+/* Queue implementation for the continuous or cyclic mode of tranfer */
+
+error_t gpcdma_port_init_queue(uint32_t chan_num, uint32_t nelems,
+                               uint32_t el_sz)
+{
+    rtosError status;
+
+    if (!is_dma_chan_valid(chan_num)) {
+        return E_GPCDMA_INVALID_PARAM;
+    }
+
+    if (nelems > GPCDMA_NUM_EL) {
+        return E_GPCDMA_INVALID_PARAM;
+    }
+
+    status = rtosQueueCreate(chan_que_bufs[chan_num],
+                     ARRAY_SIZE(chan_que_bufs[chan_num]), nelems, el_sz,
+                     &chan_que[chan_num]);
+    if (status != rtosPASS) {
+        return E_GPCDMA_QUEUE_OP_FAIL;
+    }
+
+    return E_SUCCESS;
+}
+
+void gpcdma_port_delete_queue(uint32_t chan_num)
+{
+    if (is_dma_chan_valid(chan_num)) {
+        rtosQueueDelete(chan_que[chan_num]);
+    }
+}
+
+error_t gpcdma_port_get_desc(uint32_t chan_num, void *ptr, uint32_t timeout,
+                             bool from_isr)
+{
+    rtosBool higher_prio_task_woken = rtosFALSE;
+    error_t ret = E_SUCCESS;
+
+    if (ptr == NULL) {
+        ret = E_GPCDMA_NULL_PTR;
+        goto out;
+    }
+    if (!is_dma_chan_valid(chan_num)) {
+        ret = E_GPCDMA_INVALID_PARAM;
+        goto out;
+    }
+
+    if (from_isr) {
+        if (rtosQueueReceiveFromISR(chan_que[chan_num], ptr,
+            &higher_prio_task_woken) != rtosPASS) {
+            ret = E_GPCDMA_QUEUE_OP_FAIL;
+        } else {
+            rtosTaskYieldFromISR(higher_prio_task_woken);
+        }
+    } else {
+        if (rtosQueueReceive(chan_que[chan_num], ptr,
+            (rtosTick)timeout) != rtosPASS) {
+            ret = E_GPCDMA_QUEUE_OP_FAIL;
+        }
+    }
+
+out:
+    return ret;
+}
+
+error_t gpcdma_port_send_desc_to_back(uint32_t chan_num, void *ptr,
+                                      uint32_t timeout, bool from_isr)
+{
+    rtosBool higher_prio_task_woken = rtosFALSE;
+    error_t ret = E_SUCCESS;
+
+    if (ptr == NULL) {
+        ret = E_GPCDMA_NULL_PTR;
+        goto out;
+    }
+    if (!is_dma_chan_valid(chan_num)) {
+        ret = E_GPCDMA_INVALID_PARAM;
+        goto out;
+    }
+
+    if (from_isr) {
+        if (rtosQueueSendToBackFromISR(chan_que[chan_num], ptr,
+            &higher_prio_task_woken) != rtosPASS) {
+            ret = E_GPCDMA_QUEUE_OP_FAIL;
+        } else {
+            rtosTaskYieldFromISR(higher_prio_task_woken);
+        }
+    } else {
+        if (rtosQueueSendToBack(chan_que[chan_num], ptr,
+            (rtosTick)timeout) != rtosPASS) {
+            ret = E_GPCDMA_QUEUE_OP_FAIL;
+        }
+    }
+
+out:
+    return ret;
+}
+/* End of queue implementation */
+
+error_t gpcdma_port_chan_sync(uint32_t chan_num,
+                              uint32_t timeout)
+{
+    error_t ret;
+
+    if (!is_dma_chan_valid(chan_num)) {
+        ret = E_GPCDMA_INVALID_PARAM;
+        goto out;
+    }
+
+    ret = rtosSemaphoreAcquire(chan_sems[chan_num], (rtosTick)timeout);
+    if (ret != rtosPASS) {
+        ret = E_GPCDMA_PORT_SYNC_TIMEOUT;
+        goto out;
+    }
+    ret = E_SUCCESS;
+
+out:
+    return ret;
+}
+
+error_t gpcdma_port_chan_sync_end(uint32_t chan_num)
+{
+    error_t ret;
+    rtosBool higher_prio_task_woken = rtosFALSE;
+
+    if (!is_dma_chan_valid(chan_num)) {
+        ret = E_GPCDMA_INVALID_PARAM;
+        goto out;
+    }
+
+    ret = rtosSemaphoreReleaseFromISR(chan_sems[chan_num],
+                                      &higher_prio_task_woken);
+    if (ret == rtosPASS) {
+        rtosTaskYieldFromISR(higher_prio_task_woken);
+        ret = E_SUCCESS;
+    }
+
+out:
+    return ret;
+}
+
+error_t gpcdma_port_chan_setup(uint32_t chan_num)
+{
+    error_t ret;
+    rtosUCount depth;
+
+    if (!is_dma_chan_valid(chan_num)) {
+        ret = E_GPCDMA_INVALID_PARAM;
+        goto out;
+    }
+
+    ret = rtosSemaphoreCreateBinary(chan_sem_bufs[chan_num],
+                                    &chan_sems[chan_num]);
+    if (ret != rtosPASS) {
+        ret = E_GPCDMA_PORT_CHAN_SETUP_FAIL;
+        goto out;
+    }
+
+    ret = rtosSemaphoreGetCountDepth(chan_sems[chan_num], &depth);
+    if (ret != rtosPASS) {
+        ret = E_GPCDMA_PORT_CHAN_SETUP_FAIL;
+        goto out;
+    }
+
+    if (depth == 0U) {
+        ret = E_SUCCESS;
+        goto out;
+    }
+
+    /*
+     * Make sure the semaphore state is empty initially so that it
+     * blocks on a notification from ISR.
+     */
+    ret = rtosSemaphoreAcquire(chan_sems[chan_num], (rtosTick)0);
+    if (ret != rtosPASS) {
+        ret = E_GPCDMA_PORT_CHAN_SETUP_FAIL;
+        goto out;
+    }
+    ret = E_SUCCESS;
+
+out:
+    return ret;
+}
+
+error_t gpcdma_port_init(struct gpcdma_id *id)
+{
+    error_t ret = E_SUCCESS;
+
+    if (id == NULL) {
+        ret = E_GPCDMA_NULL_PTR;
+        goto out;
+    }
+
+    ret = tegra_clk_reset_pulse(id->conf.hw_handle->rst, 2);
+    if (ret != 0) {
+        ret = E_GPCDMA_PORT_INIT_FAIL;
+    }
+
+out:
+    return ret;
+}
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/aon/hsp-irq.S b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/hsp-irq.S
new file mode 100644
index 0000000..1779b2c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/hsp-irq.S
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2019-2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>
+#include <processor/hsp-tegra-hw.h>
+#include <vic/vic-asm.h>
+
+/* Module-specific FSP headers */
+#include <hsp/sections-hsp.h>
+
+    .section    SECTION_STR_HSP_TEXT, "ax"
+    .arm
+    .syntax     unified
+
+    /**
+     * HSP interrupt handlers
+     * TEGRA_HSP_CTX_MBOX/DB should be defined by the soc includes
+     */
+    isr_addr MBOX_isr, TEGRA_HSP_ID_MBOX, tegra_hsp_irq_handler, INTERRUPT_MBOX
+    isr_addr TOP0_HSP_DB_isr, TEGRA_HSP_ID_DB, tegra_hsp_db_irq_handler, INTERRUPT_TOP0_HSP_DB
+
+    /**
+     * Defines the portion of the ISR map array for HSP
+     */
+    .section    SECTION_STR_VIC_ISRMAP_DATA, "a"
+
+    isr_map_entry    INTERRUPT_MBOX, MBOX_isr
+    isr_map_entry    INTERRUPT_TOP0_HSP_DB, TOP0_HSP_DB_isr
+
+    .end
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/aon/i2c-irq.S b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/i2c-irq.S
new file mode 100644
index 0000000..6da3ba2
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/i2c-irq.S
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2019-2021 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>        // defined by the application
+#include <sections/sections.h>
+#include <vic/vic-asm.h>
+
+/* Module-specific FSP header files */
+#include <i2c/sections-i2c.h>
+#include <soc-common/i2c-defs.h>
+
+    .section    SECTION_STR_I2C_TEXT, "ax"
+    .arm
+    .syntax     unified
+
+    /*
+     * I2C interrupt handlers
+     */
+    isr_value I2C_CTRL2_isr, TEGRA234_I2C2, tegra_i2c_irq_handler, \
+                INTERRUPT_I2C2
+    isr_value I2C_CTRL8_isr, TEGRA234_I2C8, tegra_i2c_irq_handler, \
+                INTERRUPT_I2C3
+
+    /*
+     * Defines the portion of the ISR map array for I2C
+     */
+    .section    SECTION_STR_VIC_ISRMAP_DATA, "a"
+
+    isr_map_entry    INTERRUPT_I2C2, I2C_CTRL2_isr
+    isr_map_entry    INTERRUPT_I2C3, I2C_CTRL8_isr
+
+    .end
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/aon/i2c-port.c b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/i2c-port.c
new file mode 100644
index 0000000..c9c8241
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/i2c-port.c
@@ -0,0 +1,335 @@
+/*
+ * Copyright (c) 2019-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>                      // for bool, false, true
+#include <stddef.h>                       // for NULL
+#include <stdint.h>                       // for uint32_t, uint64_t, int64_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>               // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <irq/safe-irqs.h>
+#include <osa/rtos-mutex.h>               // for rtosMutexAcquire, rtosMutex...
+#include <osa/rtos-values.h>              // for rtosPASS
+#include <clk/clk-tegra.h>                // for tegra_clk_disable, tegra_cl...
+#include <delay/delay.h>                  // for udelay
+#include <error/common-errors.h>          // for error_t, MODULE_ID_COMMON
+#include <tke/tke-tegra.h>                // for tegra_tke_convert_usecs_to_...
+#include <debug/assert.h>                 // for ASSERT, ...
+
+/* Module-specific FSP header files */
+#include <i2c/i2c-config.h>               // for i2c_config_data
+#include <i2c/i2c-tegra.h>                // for i2c_config_data, i2c_tegra_...
+#include <i2c/i2c.h>                      // for i2c_handle
+#include <port/i2c-port.h>                // for VALID_I2C_IDS
+#include <processor/i2c-tegra-hw.h>       // for i2c_get_hw_handle, i2c_hw_h...
+#include <soc-common/i2c-dependencies.h>  // for is_valid_i2c_id, appfw_clk_...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSA__RTOS_MUTEX_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_VALUES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CLK__CLK_TEGRA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DELAY__DELAY_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__TKE__TKE_TEGRA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DEBUG__ASSERT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_TEGRA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__I2C__I2C_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PORT__I2C_PORT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PROCESSOR__I2C_TEGRA_HW_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__SOC_COMMON__I2C_DEPENDENCIES_H, "Header file missing or invalid.")
+
+struct i2c_config_data pi2c_config_data[2];
+struct i2c_tegra_handle hi2c_tegra_all[2];
+static bool irq_raised[2];
+static rtosMutexHandle rwlock[2];
+static uint8_t MutexBuffer[2][rtosMutexSize()];
+
+/* VALID_I2C_IDS are defined in the cluster specific i2c-port.h file */
+static inline bool is_valid_i2c_id(uint32_t ctrl_id)
+{
+    bool ret;
+
+    if (ctrl_id < I2C_MAX_CTRLS) {
+        ret = (BIT(ctrl_id) & VALID_I2C_IDS) > 0U;
+    } else {
+        ret = false;
+    }
+
+    return ret;
+}
+
+static uint32_t map_id(uint32_t ctrl_id)
+{
+    uint32_t ret;
+
+    switch (ctrl_id) {
+    case 2U:
+        ret = 0U;
+        break;
+    case 8U:
+        ret = 1U;
+        break;
+    default:
+        /* Invalid Entry */
+        ret = 2U;
+        break;
+    }
+
+    return ret;
+}
+
+error_t appfw_wait_irq(uint32_t ctrl_id, uint32_t timeout_us)
+{
+    error_t ret = E_TIMEOUT;
+    uint64_t timer_start;
+    uint64_t timer_cur;
+    const struct i2c_hw_handle *hi2c_hw = i2c_get_hw_handle(ctrl_id);
+
+    if (!is_valid_i2c_id(ctrl_id)) {
+        ret = E_INVALID_PARAM;
+        goto out;
+    }
+
+    ret = irq_safe_enable(hi2c_hw->irq_no);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+    timer_start = appfw_timer_cur_us();
+    do {
+        if (irq_raised[(map_id(ctrl_id))]) {
+            ret = E_SUCCESS;
+            break;
+        }
+        timer_cur = appfw_timer_cur_us();
+    INLINE_RFD(CERTC, DEVIATE, INT30_C, "Approval: JIRA TID-449, DR: SWE-FSP-045-SWSADR.docx");
+    } while ((timer_cur - timer_start) < timeout_us);
+
+    irq_raised[map_id(ctrl_id)] = false;
+    ret = irq_safe_disable(hi2c_hw->irq_no);
+
+out:
+    return ret;
+}
+
+error_t appfw_mutex_acquire(uint32_t ctrl_id, uint32_t timeout)
+{
+    error_t ret;
+
+    if (!is_valid_i2c_id(ctrl_id)) {
+        ret = E_INVALID_PARAM;
+        goto out;
+    }
+
+    ret = rtosMutexAcquire(rwlock[map_id(ctrl_id)],
+            (uint32_t)tegra_tke_convert_usecs_to_ticks((const uint64_t)timeout));
+    if (ret == rtosPASS) {
+        ret = E_SUCCESS;
+    }
+
+out:
+    return ret;
+}
+
+error_t appfw_mutex_release(uint32_t ctrl_id)
+{
+    error_t ret;
+
+    if (!is_valid_i2c_id(ctrl_id)) {
+        ret = E_INVALID_PARAM;
+        goto out;
+    }
+
+    ret = rtosMutexRelease(rwlock[map_id(ctrl_id)]);
+    if (ret == rtosPASS) {
+        ret = E_SUCCESS;
+    }
+
+out:
+    return ret;
+}
+
+error_t appfw_mutex_create(uint32_t ctrl_id)
+{
+    error_t ret;
+
+    if (!is_valid_i2c_id(ctrl_id)) {
+        ret = E_INVALID_PARAM;
+        goto out;
+    }
+
+    ret = rtosMutexCreate(MutexBuffer[map_id(ctrl_id)], &rwlock[map_id(ctrl_id)]);
+    if (ret == rtosPASS) {
+        ret = E_SUCCESS;
+    }
+
+out:
+    return ret;
+}
+
+uint64_t appfw_timer_cur_us(void)
+{
+    return tegra_tke_get_usec();
+}
+
+void appfw_udelay(uint32_t delay)
+{
+    udelay(delay);
+}
+
+error_t appfw_clk_reset_pulse(uint32_t ctrl_id, uint32_t delay)
+{
+    error_t ret;
+    const struct i2c_hw_handle *hi2c_hw = i2c_get_hw_handle(ctrl_id);
+
+    if (!is_valid_i2c_id(ctrl_id)) {
+        ret = E_INVALID_PARAM;
+        goto out;
+    }
+
+    ret = tegra_clk_reset_pulse(hi2c_hw->rst_data, delay);
+
+out:
+    return ret;
+}
+
+int64_t appfw_configure_ctrl_clk_rate(uint32_t ctrl_id)
+{
+    error_t ret;
+    const struct i2c_hw_handle *hi2c_hw = i2c_get_hw_handle(ctrl_id);
+    struct i2c_config_data *config_data = i2c_get_config_data(ctrl_id);
+
+    if (!is_valid_i2c_id(ctrl_id)) {
+        ret = E_INVALID_PARAM;
+        goto out;
+    }
+
+    ret = tegra_clk_set_rate(hi2c_hw->clk_data, config_data->ctrl_clk_rate);
+    if (ret != 0) {
+        ret = E_INVALID_PARAM;
+    } else {
+        ret = config_data->ctrl_clk_rate;
+    }
+
+out:
+    return ret;
+}
+
+error_t appfw_clk_enable(uint32_t ctrl_id)
+{
+    error_t ret;
+    const struct i2c_hw_handle *hi2c_hw = i2c_get_hw_handle(ctrl_id);
+
+    if (!is_valid_i2c_id(ctrl_id)) {
+        ret = E_INVALID_PARAM;
+        goto out;
+    }
+
+    ret = tegra_clk_enable(hi2c_hw->clk_data);
+
+out:
+    return ret;
+}
+
+error_t appfw_clk_disable(uint32_t ctrl_id)
+{
+    error_t ret;
+    const struct i2c_hw_handle *hi2c_hw = i2c_get_hw_handle(ctrl_id);
+
+    if (!is_valid_i2c_id(ctrl_id)) {
+        ret = E_INVALID_PARAM;
+        goto out;
+    }
+
+    ret = tegra_clk_disable(hi2c_hw->clk_data);
+
+out:
+    return ret;
+}
+
+void appfw_irq_enable(uint32_t ctrl_id)
+{
+    const struct i2c_hw_handle *hi2c_hw = i2c_get_hw_handle(ctrl_id);
+
+    (void)irq_safe_enable(hi2c_hw->irq_no);
+}
+
+void appfw_irq_disable(uint32_t ctrl_id)
+{
+    const struct i2c_hw_handle *hi2c_hw = i2c_get_hw_handle(ctrl_id);
+
+    (void)irq_safe_disable(hi2c_hw->irq_no);
+}
+
+struct i2c_tegra_handle *i2c_get_tegra_handle(uint32_t ctrl_id)
+{
+    struct i2c_tegra_handle *ret;
+
+    if (!is_valid_i2c_id(ctrl_id)) {
+        ret = NULL;
+        goto out;
+    }
+
+    hi2c_tegra_all[map_id(ctrl_id)].ctrl_id = ctrl_id;
+    ret = &hi2c_tegra_all[map_id(ctrl_id)];
+
+out:
+    return ret;
+}
+
+struct i2c_config_data *i2c_get_config_data(uint32_t ctrl_id)
+{
+    struct i2c_config_data *ret;
+
+    if (!is_valid_i2c_id(ctrl_id)) {
+        ret = NULL;
+        goto out;
+    }
+
+    pi2c_config_data[map_id(ctrl_id)].bus_clk_rate = 100000U;
+    pi2c_config_data[map_id(ctrl_id)].ctrl_clk_rate = 136000000U;
+    pi2c_config_data[map_id(ctrl_id)].hs_master_code = 0U;
+    ret = &pi2c_config_data[map_id(ctrl_id)];
+
+out:
+    return ret;
+}
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/aon/lic-irq.S b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/lic-irq.S
new file mode 100644
index 0000000..c814a9e
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/lic-irq.S
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sections/sections.h>
+#include <vic/vic-asm.h>
+#include <hw-config/vic-irqs.h>
+#include <processor/irqs-lic.h>
+#include <lic/sections-lic.h>
+
+    .section    SECTION_STR_LIC_TEXT, "ax"
+    .arm
+    .syntax     unified
+
+    /**
+     * GPCLIC per channel interrupt handlers
+     * GPCLIC_CHAN[0-7] should be defined by the soc includes
+     */
+    isr_addr LIC0_isr, LIC0_IRQ_CONTEXT, tegra_lic_irq_handler, INTERRUPT_LIC0
+    isr_addr LIC1_isr, LIC1_IRQ_CONTEXT, tegra_lic_irq_handler, INTERRUPT_LIC1
+    isr_addr LIC2_isr, LIC2_IRQ_CONTEXT, tegra_lic_irq_handler, INTERRUPT_LIC2
+    isr_addr LIC3_isr, LIC3_IRQ_CONTEXT, tegra_lic_irq_handler, INTERRUPT_LIC3
+
+    /**
+     * Defines the portion of the ISR map array for GPCLIC
+     */
+    .section    SECTION_STR_VIC_ISRMAP_DATA, "a"
+
+    isr_map_entry    INTERRUPT_LIC0, LIC0_isr
+    isr_map_entry    INTERRUPT_LIC1, LIC1_isr
+    isr_map_entry    INTERRUPT_LIC2, LIC2_isr
+    isr_map_entry    INTERRUPT_LIC3, LIC3_isr
+
+    .end
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/aon/spi-port.c b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/spi-port.c
new file mode 100644
index 0000000..679442d
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/spi-port.c
@@ -0,0 +1,323 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                // for CT_ASSERT
+
+/* Hardware headers */
+#include <arspi.h>
+
+/* Late FSP headers */
+#include <osa/rtos-task.h>                 // for rtosTaskYieldFromISR
+#include <osa/rtos-semaphore.h>            // for rtosSemaphore...
+#include <osa/rtos-values.h>               // for rtosBool
+#include <error/common-errors.h>           // for E_SUCCESS, error_t, FSP_...
+#include <clk/clk-tegra.h>                 // for tegra_clk_enable, ...
+#include <cpu/type-conversion.h>           // for tegra_clk_enable, ...
+#include <cpu/cache.h>                     // for cache_clean, ...
+
+/* Module-specific FSP headers */
+#include <spi/sections-spi.h>              // for SECTION_SPI_ ...
+#include <spi/spi-errors.h>                // for E_SPI_ERR_CONFIG, ...
+#include <spi/spi-priv.h>                  // for spi_ctlr, ...
+#include <spi/spi-port.h>                  // for spi_port_...
+#include <port/spi-port-priv.h>            // Immune from CT_ASSERT
+#include <gpcdma/gpcdma.h>
+#include <gpcdma/gpcdma-errors.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__CLK__CLK_TEGRA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+static rtosSemaphoreHandle  spi_sem;
+static uint8_t              spi_sem_buf[rtosSemaphoreSize()];
+
+void spi_port_isr_exit(const struct spi_ctlr *ctlr,
+                       bool isr_yield_flag)
+{
+    (void) ctlr;
+
+    rtosTaskYieldFromISR(isr_yield_flag);
+}
+
+void spi_port_cache_invalidate(void * base,
+                               size_t length)
+{
+    cache_invalidate(base, length);
+}
+
+void spi_port_cache_clean(void * base,
+                          size_t length)
+{
+    cache_clean(base, length);
+}
+
+error_t spi_port_dma_init(struct spi_ctlr *ctlr)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL || ctlr->dma_id == NULL) {
+        ret = E_SPI_NULL_PTR;
+        goto out;
+    }
+
+    ret = gpcdma_init(ctlr->dma_id);
+
+out:
+    return ret;
+}
+
+error_t spi_port_init(struct spi_ctlr *ctlr)
+{
+    error_t ret;
+    rtosUCount depth;
+
+    if (ctlr == NULL) {
+        ret = E_SPI_NULL_PTR;
+        goto out;
+    }
+
+    ret = rtosSemaphoreCreateBinary(spi_sem_buf,
+                                    &spi_sem);
+    if (ret != rtosPASS) {
+        ret = E_SPI_PORT_INIT_FAIL;
+        goto out;
+    }
+
+    ret = rtosSemaphoreGetCountDepth(spi_sem, &depth);
+    if (ret != rtosPASS) {
+        ret = E_SPI_PORT_INIT_FAIL;
+        goto out;
+    }
+
+    if (depth == 0U) {
+        ret = E_SUCCESS;
+        goto out;
+    }
+
+    /*
+     * Make sure the semaphore state is empty initially so that it
+     * blocks on a notification from ISR.
+     */
+    ret = rtosSemaphoreAcquire(spi_sem, (rtosTick)0);
+    if (ret != rtosPASS) {
+        ret = E_SPI_PORT_INIT_FAIL;
+        goto out;
+    }
+    ret = E_SUCCESS;
+
+out:
+    return ret;
+}
+
+error_t spi_port_xfer_sync(struct spi_ctlr *ctlr,
+                           uint32_t timeout)
+{
+    error_t ret;
+
+    if (ctlr == NULL) {
+        ret = E_SPI_NULL_PTR;
+        goto out;
+    }
+
+    ret = rtosSemaphoreAcquire(spi_sem, (rtosTick)timeout);
+    if (ret != rtosPASS) {
+        ret = E_SPI_PORT_SYNC_TIMEOUT;
+        goto out;
+    }
+    ret = E_SUCCESS;
+
+out:
+    return ret;
+}
+
+error_t spi_port_xfer_sync_end(struct spi_ctlr *ctlr)
+{
+    error_t ret;
+    rtosBool higher_prio_task_woken = rtosFALSE;
+
+    if (ctlr == NULL) {
+        ret = E_SPI_NULL_PTR;
+        goto out;
+    }
+
+    ret = rtosSemaphoreReleaseFromISR(spi_sem,
+                                      &higher_prio_task_woken);
+    if (ret == rtosPASS) {
+        rtosTaskYieldFromISR(higher_prio_task_woken);
+        ret = E_SUCCESS;
+    }
+
+out:
+    return ret;
+}
+
+void spi_port_clk_disable(struct spi_ctlr *ctlr)
+{
+    if (ctlr != NULL) {
+        tegra_clk_disable(ctlr->conf.hw_handle->clk);
+    }
+}
+
+error_t spi_port_clk_enable(struct spi_ctlr *ctlr)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_SPI_NULL_PTR;
+        goto out;
+    }
+
+    ret = tegra_clk_enable(ctlr->conf.hw_handle->clk);
+    if (ret != 0) {
+        ret = E_SPI_CLK_EN;
+    }
+
+out:
+    return ret;
+}
+
+error_t spi_port_tx_dma_xfer_abort(struct spi_ctlr *ctlr)
+{
+    return gpcdma_abort(ctlr->dma_id, ctlr->dma_chans.tx);
+}
+
+error_t spi_port_rx_dma_xfer_abort(struct spi_ctlr *ctlr)
+{
+    return gpcdma_abort(ctlr->dma_id, ctlr->dma_chans.rx);
+}
+
+error_t spi_port_start_rx_dma(struct spi_ctlr *ctlr,
+                              struct spi_xfer *xfer,
+                              uint32_t len,
+                              uint32_t burst_size)
+{
+    uint8_t *rx_buf = (uint8_t *)xfer->rx_buf + ctlr->cur_rx_pos;
+
+    struct gpcdma_xfer dma_xfer = {
+        .direction = GPCDMA_XFER_DIR_IO_TO_MEM,
+        .bus_width = GPCDMA_IO_BUS_WIDTH_32,
+        .burst_size = burst_size,
+        .src_addr = (uint64_t)(ctlr->conf.base_addr + SPI_RX_FIFO_0),
+        .src_addr_wrap = 1,
+        .dst_addr = (uint64_t)(fsp_c_u8_ptr_to_u32(rx_buf)),
+        .dst_addr_wrap = 0,
+        .xfer_count = len,
+        .en_flow_ctrl = true,
+        .slave_req = ctlr->dma_slave_req,
+        .synchronous = true,
+        .timeout = 10,
+        .callback = NULL,
+        .callback_param = NULL,
+    };
+
+    return gpcdma_transfer(ctlr->dma_id, ctlr->dma_chans.rx, &dma_xfer);
+}
+
+error_t spi_port_start_tx_dma(struct spi_ctlr *ctlr,
+                              struct spi_xfer *xfer,
+                              uint32_t len,
+                              uint32_t burst_size)
+{
+    uint8_t *tx_buf = (uint8_t *)xfer->tx_buf + ctlr->cur_tx_pos;
+
+    struct gpcdma_xfer dma_xfer = {
+        .direction = GPCDMA_XFER_DIR_MEM_TO_IO,
+        .bus_width = GPCDMA_IO_BUS_WIDTH_32,
+        .burst_size = burst_size,
+        .src_addr = (uint64_t)(fsp_c_u8_ptr_to_u32(tx_buf)),
+        .src_addr_wrap = 0,
+        .dst_addr = (uint64_t)(ctlr->conf.base_addr + SPI_TX_FIFO_0),
+        .dst_addr_wrap = 1,
+        .xfer_count = len,
+        .en_flow_ctrl = true,
+        .slave_req = ctlr->dma_slave_req,
+        .synchronous = true,
+        .timeout = 10,
+        .callback = NULL,
+        .callback_param = NULL,
+    };
+
+    return gpcdma_transfer(ctlr->dma_id, ctlr->dma_chans.tx, &dma_xfer);
+}
+
+error_t spi_port_clk_reset_pulse(struct spi_ctlr *ctlr,
+                                 uint32_t delay)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_SPI_NULL_PTR;
+        goto out;
+    }
+
+    ret = tegra_clk_reset_pulse(ctlr->conf.hw_handle->rst, delay);
+    if (ret != 0) {
+        ret = E_SPI_CLK_RST;
+    }
+
+out:
+    return ret;
+}
+
+error_t spi_port_clk_set_rate(struct spi_ctlr *ctlr,
+                              uint32_t rate)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_SPI_NULL_PTR;
+        goto out;
+    }
+
+    ret = tegra_clk_set_rate(ctlr->conf.hw_handle->clk, rate);
+    if (ret != 0) {
+        ret = E_SPI_CLK_SET_RATE;
+    }
+
+out:
+    return ret;
+}
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/aon/tke-irq.S b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/tke-irq.S
new file mode 100644
index 0000000..aa4de9f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/tke-irq.S
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2018-2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>		// defined by the application, defines the interrupt map
+#include <vic/vic-asm.h>
+
+/* Module-specific FSP headers */
+#include <tke/sections-tke.h>
+
+	.section	SECTION_STR_TKE_TEXT, "ax"
+	.arm
+	.syntax		unified
+
+	/*
+	 * TKE interrupt handlers
+	 */
+	isr_addr TIMER0_isr, tegra_tke_id_timer0, tegra_tke_irq, INTERRUPT_TIMER0
+	isr_addr TIMER1_isr, tegra_tke_id_timer1, tegra_tke_irq, INTERRUPT_TIMER1
+	isr_addr TIMER2_isr, tegra_tke_id_timer2, tegra_tke_irq, INTERRUPT_TIMER2
+	isr_addr TIMER3_isr, tegra_tke_id_timer3, tegra_tke_irq, INTERRUPT_TIMER3
+
+	/*
+	 * Defines the portion of the ISR map array for TKE
+	 */
+	.section	SECTION_STR_VIC_ISRMAP_DATA, "a"
+
+	isr_map_entry	INTERRUPT_TIMER0, TIMER0_isr
+	isr_map_entry	INTERRUPT_TIMER1, TIMER1_isr
+	isr_map_entry	INTERRUPT_TIMER2, TIMER2_isr
+	isr_map_entry	INTERRUPT_TIMER3, TIMER3_isr
+
+	.end
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/aon/uart-port.c b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/uart-port.c
new file mode 100644
index 0000000..3b3dffe
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/uart-port.c
@@ -0,0 +1,363 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>       // for CT_ASSERT
+
+/* Hardware headers */
+#include <address_map_new.h>
+#include <arpadctl_AO.h>
+
+/* Late FSP headers */
+#include <reg-access/reg-access.h>
+#include <osa/rtos-values.h>
+#include <osa/rtos-errors.h>
+#include <osa/rtos-task.h>
+#include <osa/rtos-queue.h>
+#include <error/common-errors.h>             // for E_SUCCESS, error_t, FSP_...
+#include <clk/clk-tegra.h>                   // for tegra_clk_enable, ...
+
+/* Module-specific FSP headers */
+#include <uart/sections-uart.h>              // for SECTION_UART_ ...
+#include <uart/uart-errors.h>                // for E_UART_ERR_CONFIG, ...
+#include <uart/tegra-uart-priv.h>            // for tegra_uart_ctlr, ...
+#include <uart/uart-port.h>                  // for uart_port_...
+#include <port/uart-port-priv.h>             // for uart_queue_t , struct uart_hw_handle
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+                MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__CLK__CLK_TEGRA_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_QUEUE_H, "Header file missing or invalid.")
+END_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx",
+              MISRA, DEVIATE, Directive_4_9, "Approval:  On-file, DR: SWE-FSP-012-SWSADR.docx")
+
+#define UART_QUEUE_SIZE        rtosQueueSize(TEGRA_UART_BUF_SIZE, \
+                                             sizeof(char))
+
+error_t uart_port_rx_queue_send_from_isr(const struct tegra_uart_ctlr *ctlr,
+                                         char *c_in,
+                                         bool *isr_yield_flag)
+{
+    error_t ret = E_SUCCESS;
+    rtosError status;
+    rtosBool higher_prio_task_woken = rtosFALSE;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    status = rtosQueueSendFromISR(ctlr->rx_queue,
+                                  c_in,
+                                  &higher_prio_task_woken);
+    if (status != E_SUCCESS) {
+        ret = status;
+        goto out;
+    }
+    *isr_yield_flag = higher_prio_task_woken;
+
+out:
+    return ret;
+}
+
+error_t uart_port_tx_queue_receive_from_isr(const struct tegra_uart_ctlr *ctlr,
+                                            char *c_out,
+                                            bool *isr_yield_flag)
+{
+    error_t ret = E_SUCCESS;
+    rtosError status;
+    rtosBool higher_prio_task_woken = rtosFALSE;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    status = rtosQueueReceiveFromISR(ctlr->tx_queue,
+                                     c_out,
+                                     &higher_prio_task_woken);
+    if (status != rtosPASS) {
+        ret = status;
+        goto out;
+    }
+    *isr_yield_flag = higher_prio_task_woken;
+
+out:
+    return ret;
+}
+
+error_t uart_port_tx_queue_receive(const struct tegra_uart_ctlr *ctlr,
+                                   char *c,
+                                   uint32_t timeout_left)
+{
+    error_t   ret = E_SUCCESS;
+    rtosError status;
+    rtosTick  timeout = tegra_tke_convert_usecs_to_ticks(timeout_left);
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (timeout >= rtosMAX_DELAY) {
+        timeout = rtosMAX_DELAY;
+    }
+
+    status = rtosQueueReceive(ctlr->tx_queue,
+                              c,
+                              timeout);
+    if (status != rtosPASS) {
+        ret = status;
+        goto out;
+    }
+
+out:
+    return ret;
+}
+
+error_t uart_port_tx_queue_send(const struct tegra_uart_ctlr *ctlr,
+                                const char *c,
+                                uint32_t timeout_left)
+{
+    error_t   ret = E_SUCCESS;
+    rtosError status;
+    rtosTick  timeout = tegra_tke_convert_usecs_to_ticks(timeout_left);
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (timeout >= rtosMAX_DELAY) {
+        timeout = rtosMAX_DELAY;
+    }
+
+    status = rtosQueueSend(ctlr->tx_queue,
+                           c,
+                           timeout);
+    if (status != rtosPASS) {
+        ret = (status == E_RTOS_QUEUE_FULL) ? E_UART_QUEUE_FULL : status;
+        goto out;
+    }
+
+out:
+    return ret;
+}
+
+error_t uart_port_rx_queue_receive(const struct tegra_uart_ctlr *ctlr,
+                                   char *c,
+                                   uint32_t timeout_left)
+{
+    error_t   ret = E_SUCCESS;
+    rtosError status;
+    rtosTick  timeout = tegra_tke_convert_usecs_to_ticks(timeout_left);
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (timeout >= rtosMAX_DELAY) {
+        timeout = rtosMAX_DELAY;
+    }
+
+    status = rtosQueueReceive(ctlr->rx_queue,
+                              c,
+                              timeout);
+    if (status != rtosPASS) {
+        ret = status;
+        goto out;
+    }
+
+out:
+    return ret;
+}
+
+void uart_port_isr_exit(const struct tegra_uart_ctlr *ctlr,
+                        bool isr_yield_flag)
+{
+    (void) ctlr;
+
+    rtosTaskYieldFromISR(isr_yield_flag);
+}
+
+error_t uart_port_tx_queue_create(struct tegra_uart_ctlr *ctlr)
+{
+    error_t ret = E_SUCCESS;
+    rtosError status;
+    static char uart_tx_queue[UART_QUEUE_SIZE] SECTION_UART_DATA;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    status = rtosQueueCreate(uart_tx_queue,
+                             ARRAY_SIZE(uart_tx_queue),
+                             TEGRA_UART_BUF_SIZE,
+                             sizeof(char),
+                             &ctlr->tx_queue);
+    if (status != rtosPASS) {
+        ret = E_UART_INIT_FAIL;
+        goto out;
+    }
+
+out:
+    return ret;
+}
+
+error_t uart_port_rx_queue_create(struct tegra_uart_ctlr *ctlr)
+{
+    error_t ret = E_SUCCESS;
+    rtosError status;
+    static char uart_rx_queue[UART_QUEUE_SIZE] SECTION_UART_DATA;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    status = rtosQueueCreate(uart_rx_queue,
+                             ARRAY_SIZE(uart_rx_queue),
+                             TEGRA_UART_BUF_SIZE,
+                             sizeof(char),
+                             &ctlr->rx_queue);
+    if (status != rtosPASS) {
+        ret = E_UART_INIT_FAIL;
+        goto out;
+    }
+
+out:
+    return ret;
+}
+
+error_t uart_port_clk_disable(struct tegra_uart_ctlr *ctlr)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    tegra_clk_disable(ctlr->id.hw_handle->clk);
+
+out:
+    return ret;
+}
+
+error_t uart_port_clk_enable(struct tegra_uart_ctlr *ctlr)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    tegra_clk_enable(ctlr->id.hw_handle->clk);
+
+out:
+    return ret;
+}
+
+error_t uart_port_clk_reset_pulse(struct tegra_uart_ctlr *ctlr,
+                                  uint32_t delay)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    tegra_clk_reset_pulse(ctlr->id.hw_handle->rst, delay);
+
+out:
+    return ret;
+}
+
+error_t uart_port_clk_set_rate(struct tegra_uart_ctlr *ctlr,
+                               uint32_t rate)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    tegra_clk_set_rate(ctlr->id.hw_handle->clk, rate);
+
+out:
+    return ret;
+}
+
+bool uart_port_is_configured(const struct tegra_uart_ctlr *ctlr)
+{
+    bool ret = false;
+
+    if (ctlr == NULL) {
+        goto out;
+    }
+
+    ret = tegra_clk_is_clk_enabled(ctlr->id.hw_handle->clk) &&
+            tegra_reset_is_reset_deasserted(ctlr->id.hw_handle->rst);
+
+out:
+    return ret;
+}
+
+error_t uart_port_init(struct tegra_uart_ctlr *ctlr)
+{
+    writel(0x441, NV_ADDRESS_MAP_PADCTL_A14_BASE + PADCTL_AO_UART3_RX_0);
+    writel(0x441, NV_ADDRESS_MAP_PADCTL_A14_BASE + PADCTL_AO_UART3_TX_0);
+
+    return E_SUCCESS;
+}
+
+uint64_t uart_port_get_elapsed_usecs(const uint64_t start)
+{
+    return tegra_tke_get_elapsed_usecs64(start);
+}
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/aon/wdt-irq.S b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/wdt-irq.S
new file mode 100644
index 0000000..b0a03fa
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/aon/wdt-irq.S
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>		// defined by the application, defines the interrupt map
+#include <sections/sections.h>
+#include <vic/vic-asm.h>
+
+/* Module-specific FSP headers */
+#include <watchdog/sections-wdt.h>
+
+	.section	SECTION_STR_WDT_TEXT, "ax"
+	.arm
+	.syntax		unified
+
+	/*
+	 * Watchdog interrupt handlers
+	 */
+	isr_addr WDTFIQ_isr, tegra_wdt_instance, tegra_safe_wdt_fiq, INTERRUPT_WDTFIQ
+	isr_addr WDTIRQ_isr, tegra_wdt_instance, tegra_safe_wdt_irq, INTERRUPT_WDTIRQ
+
+	/*
+	 * Defines the portion of the ISR map array for watchdog
+	 */
+	.section	SECTION_STR_VIC_ISRMAP_DATA, "a"
+
+	isr_map_entry	INTERRUPT_WDTFIQ, WDTFIQ_isr
+	isr_map_entry	INTERRUPT_WDTIRQ, WDTIRQ_isr
+
+	.end
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/dce/gpcdma-irq.S b/spe-freertos-bsp/fsp/source/soc/t234/port/dce/gpcdma-irq.S
new file mode 100644
index 0000000..7d5600a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/dce/gpcdma-irq.S
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sections/sections.h>
+#include <vic/vic-asm.h>
+#include <hw-config/vic-irqs.h>
+#include <processor/gpcdma-hw.h>
+#include <gpcdma/sections-gpcdma.h>
+
+    .section    SECTION_STR_GPCDMA_TEXT, "ax"
+    .arm
+    .syntax     unified
+
+    /**
+     * GPCDMA per channel interrupt handlers
+     * GPCDMA_CHAN[0-7] should be defined by the soc includes
+     */
+    isr_addr DMA0_isr, GPCDMA_CHAN0, gpcdma_chan_irq, INTERRUPT_DMA0
+    isr_addr DMA1_isr, GPCDMA_CHAN1, gpcdma_chan_irq, INTERRUPT_DMA1
+    isr_addr DMA2_isr, GPCDMA_CHAN2, gpcdma_chan_irq, INTERRUPT_DMA2
+    isr_addr DMA3_isr, GPCDMA_CHAN3, gpcdma_chan_irq, INTERRUPT_DMA3
+    isr_addr DMA4_isr, GPCDMA_CHAN4, gpcdma_chan_irq, INTERRUPT_DMA4
+    isr_addr DMA5_isr, GPCDMA_CHAN5, gpcdma_chan_irq, INTERRUPT_DMA5
+    isr_addr DMA6_isr, GPCDMA_CHAN6, gpcdma_chan_irq, INTERRUPT_DMA6
+    isr_addr DMA7_isr, GPCDMA_CHAN7, gpcdma_chan_irq, INTERRUPT_DMA7
+
+    /**
+     * Defines the portion of the ISR map array for GPCDMA
+     */
+    .section    SECTION_STR_VIC_ISRMAP_DATA, "a"
+
+    isr_map_entry    INTERRUPT_DMA0, DMA0_isr
+    isr_map_entry    INTERRUPT_DMA1, DMA1_isr
+    isr_map_entry    INTERRUPT_DMA2, DMA2_isr
+    isr_map_entry    INTERRUPT_DMA3, DMA3_isr
+    isr_map_entry    INTERRUPT_DMA4, DMA4_isr
+    isr_map_entry    INTERRUPT_DMA5, DMA5_isr
+    isr_map_entry    INTERRUPT_DMA6, DMA6_isr
+    isr_map_entry    INTERRUPT_DMA7, DMA7_isr
+
+    .end
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/dce/hsp-irq.S b/spe-freertos-bsp/fsp/source/soc/t234/port/dce/hsp-irq.S
new file mode 100644
index 0000000..1779b2c
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/dce/hsp-irq.S
@@ -0,0 +1,62 @@
+/*
+ * Copyright (c) 2019-2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>
+#include <processor/hsp-tegra-hw.h>
+#include <vic/vic-asm.h>
+
+/* Module-specific FSP headers */
+#include <hsp/sections-hsp.h>
+
+    .section    SECTION_STR_HSP_TEXT, "ax"
+    .arm
+    .syntax     unified
+
+    /**
+     * HSP interrupt handlers
+     * TEGRA_HSP_CTX_MBOX/DB should be defined by the soc includes
+     */
+    isr_addr MBOX_isr, TEGRA_HSP_ID_MBOX, tegra_hsp_irq_handler, INTERRUPT_MBOX
+    isr_addr TOP0_HSP_DB_isr, TEGRA_HSP_ID_DB, tegra_hsp_db_irq_handler, INTERRUPT_TOP0_HSP_DB
+
+    /**
+     * Defines the portion of the ISR map array for HSP
+     */
+    .section    SECTION_STR_VIC_ISRMAP_DATA, "a"
+
+    isr_map_entry    INTERRUPT_MBOX, MBOX_isr
+    isr_map_entry    INTERRUPT_TOP0_HSP_DB, TOP0_HSP_DB_isr
+
+    .end
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/dce/lic-irq.S b/spe-freertos-bsp/fsp/source/soc/t234/port/dce/lic-irq.S
new file mode 100644
index 0000000..c814a9e
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/dce/lic-irq.S
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sections/sections.h>
+#include <vic/vic-asm.h>
+#include <hw-config/vic-irqs.h>
+#include <processor/irqs-lic.h>
+#include <lic/sections-lic.h>
+
+    .section    SECTION_STR_LIC_TEXT, "ax"
+    .arm
+    .syntax     unified
+
+    /**
+     * GPCLIC per channel interrupt handlers
+     * GPCLIC_CHAN[0-7] should be defined by the soc includes
+     */
+    isr_addr LIC0_isr, LIC0_IRQ_CONTEXT, tegra_lic_irq_handler, INTERRUPT_LIC0
+    isr_addr LIC1_isr, LIC1_IRQ_CONTEXT, tegra_lic_irq_handler, INTERRUPT_LIC1
+    isr_addr LIC2_isr, LIC2_IRQ_CONTEXT, tegra_lic_irq_handler, INTERRUPT_LIC2
+    isr_addr LIC3_isr, LIC3_IRQ_CONTEXT, tegra_lic_irq_handler, INTERRUPT_LIC3
+
+    /**
+     * Defines the portion of the ISR map array for GPCLIC
+     */
+    .section    SECTION_STR_VIC_ISRMAP_DATA, "a"
+
+    isr_map_entry    INTERRUPT_LIC0, LIC0_isr
+    isr_map_entry    INTERRUPT_LIC1, LIC1_isr
+    isr_map_entry    INTERRUPT_LIC2, LIC2_isr
+    isr_map_entry    INTERRUPT_LIC3, LIC3_isr
+
+    .end
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/dce/tke-irq.S b/spe-freertos-bsp/fsp/source/soc/t234/port/dce/tke-irq.S
new file mode 100644
index 0000000..aa4de9f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/dce/tke-irq.S
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2018-2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>		// defined by the application, defines the interrupt map
+#include <vic/vic-asm.h>
+
+/* Module-specific FSP headers */
+#include <tke/sections-tke.h>
+
+	.section	SECTION_STR_TKE_TEXT, "ax"
+	.arm
+	.syntax		unified
+
+	/*
+	 * TKE interrupt handlers
+	 */
+	isr_addr TIMER0_isr, tegra_tke_id_timer0, tegra_tke_irq, INTERRUPT_TIMER0
+	isr_addr TIMER1_isr, tegra_tke_id_timer1, tegra_tke_irq, INTERRUPT_TIMER1
+	isr_addr TIMER2_isr, tegra_tke_id_timer2, tegra_tke_irq, INTERRUPT_TIMER2
+	isr_addr TIMER3_isr, tegra_tke_id_timer3, tegra_tke_irq, INTERRUPT_TIMER3
+
+	/*
+	 * Defines the portion of the ISR map array for TKE
+	 */
+	.section	SECTION_STR_VIC_ISRMAP_DATA, "a"
+
+	isr_map_entry	INTERRUPT_TIMER0, TIMER0_isr
+	isr_map_entry	INTERRUPT_TIMER1, TIMER1_isr
+	isr_map_entry	INTERRUPT_TIMER2, TIMER2_isr
+	isr_map_entry	INTERRUPT_TIMER3, TIMER3_isr
+
+	.end
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/dce/wdt-irq.S b/spe-freertos-bsp/fsp/source/soc/t234/port/dce/wdt-irq.S
new file mode 100644
index 0000000..b18b0f1
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/dce/wdt-irq.S
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2018-2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>		// defined by the application, defines the interrupt map
+#include <sections/sections.h>
+#include <vic/vic-asm.h>
+
+/* Module-specific FSP headers */
+#include <watchdog/sections-wdt.h>
+
+	.section	SECTION_STR_WDT_TEXT, "ax"
+	.arm
+	.syntax		unified
+
+	/*
+	 * Watchdog interrupt handlers
+	 */
+	isr_addr WDTFIQ_isr, tegra_wdt_instance, tegra_safe_wdt_fiq, INTERRUPT_WDTFIQ
+	isr_addr WDTIRQ_isr, tegra_wdt_instance, tegra_safe_wdt_irq, INTERRUPT_WDTIRQ
+
+	/*
+	 * Defines the portion of the ISR map array for watchdog
+	 */
+	.section	SECTION_STR_VIC_ISRMAP_DATA, "a"
+
+	isr_map_entry	INTERRUPT_WDTFIQ, WDTFIQ_isr
+	isr_map_entry	INTERRUPT_WDTIRQ, WDTIRQ_isr
+
+	.end
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/fsi/car-port.c b/spe-freertos-bsp/fsp/source/soc/t234/port/fsi/car-port.c
new file mode 100644
index 0000000..ac4db84
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/fsi/car-port.c
@@ -0,0 +1,86 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stddef.h>                     // for NULL
+#include <stdbool.h>                    // for bool, false
+#include <stdint.h>                     // for uint32_t, uint8_t, UINT8_MAX, UIN...
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+//#include <chipid/chip-id.h>             // for tegra_platform_is_silicon...
+#include <delay/delay.h>                // for udelay...
+
+/* Module-specific FSP headers */
+#include <car/car-sections.h>           // for SECTION_CAR_TEXT, ...
+#include <port/car-port.h>              // for declarations...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+//CT_ASSERT(FSP__CHIPID__CHIP_ID_H, "Header file missing or invalid.")
+//CT_ASSERT(FSP__DELAY__DELAY_H, "Header file missing or invalid.")
+
+
+SECTION_CAR_TEXT
+/*
+ * tegra_platform_is_silicon is replaced with platform_is_silicon
+ */
+static bool platform_is_silicon(void)
+{
+    return true;
+}
+
+void car_port_udelay(uint64_t delay_us)
+{
+    if (platform_is_silicon()) {
+        udelay(delay_us);
+    }
+}
+
+uint64_t car_port_get_time_ticks(void)
+{
+    return get_time_ticks();
+}
+
+uint64_t car_port_get_time_delta_us(uint64_t ticks_start)
+{
+    return get_time_delta_us(ticks_start);
+}
+
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/fsi/fsi-car-clk.c b/spe-freertos-bsp/fsp/source/soc/t234/port/fsi/fsi-car-clk.c
new file mode 100644
index 0000000..ad0ed47
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/fsi/fsi-car-clk.c
@@ -0,0 +1,653 @@
+/* Copyright (c) 2020-2021 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stddef.h>                     // for NULL
+#include <stdbool.h>                    // for bool, false
+#include <stdint.h>                     // for uint32_t, uint8_t, UINT8_MAX, UIN...
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+#include <soc-common/hw-const.h>        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <arclk_rst.h>                  // for CLK_RST_CONTROLLER_FMON_CONFIG_PLL_FSI_0...
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for ARRAY_SIZE,...
+#include <error/common-errors.h>        // for E_SUCCESS, error_t
+#include <misc/bitops.h>                // for BIT, bit_number, FSP__MISC__BITOPS_H
+
+/* Module-specific FSP headers */
+#include <car/car-sections.h>           // for SECTION_CAR_TEXT, ...
+#include <car/car-errors.h>             // for E_CAR_ERR_NULL_PTR, E_CAR_ERR_NO_...
+#include <car/car-reg.h>                // for core functions, ...
+#include <car/car-fmon.h>               // for clock functions, ...
+#include <car/car-clk.h>                // for clock functions, ...
+#include <port/car-clk.h>               // for CLK index, ...
+#include <port/car-pll.h>               // for PLL index, ...
+#include <port/car-fmon.h>              // for FMON index, ...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_CLK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__FSI__CAR_CLK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__FSI__CAR_PLL_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__FSI__CAR_FMON_H, "Header file missing or invalid.")
+
+
+SECTION_CAR_TEXT
+static bool fsi_clk_op_xtal_is_enabled(const struct car_clk_inf *clk)
+{
+    return true;
+}
+
+SECTION_CAR_TEXT
+static error_t fsi_clk_op_xtal_enable(const struct car_clk_inf *clk)
+{
+    return E_SUCCESS;
+}
+
+SECTION_CAR_TEXT
+static error_t fsi_clk_op_xtal_disable(const struct car_clk_inf *clk)
+{
+    return E_CAR_CLOCK_OP_NOT_SUPPORTED;
+}
+
+SECTION_CAR_RODATA
+static const struct car_clk_op_able fsi_clk_op_able_xtal = {
+    .clk_is_enabled = fsi_clk_op_xtal_is_enabled,
+    .clk_enable = fsi_clk_op_xtal_enable,
+    .clk_disable = fsi_clk_op_xtal_disable,
+};
+
+SECTION_CAR_TEXT
+static error_t fsi_clk_op_xtal_hz_get(const struct car_clk_inf *clk, int64_t *hz_out)
+{
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (hz_out != NULL) {
+        *hz_out = FSI_CLK_XTAL_HZ;
+        ret = E_SUCCESS;
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+static error_t fsi_clk_op_xtal_hz_set(const struct car_clk_inf *clk, int64_t hz_out)
+{
+    return E_CAR_CLOCK_OP_NOT_SUPPORTED;
+}
+
+SECTION_CAR_RODATA
+static const struct car_clk_op_rate fsi_clk_op_rate_xtal = {
+    .clk_hz_get = fsi_clk_op_xtal_hz_get,
+    .clk_hz_set = fsi_clk_op_xtal_hz_set,
+};
+
+SECTION_CAR_TEXT
+static bool fsi_clk_op_pll_is_enabled(const struct car_clk_inf *clk)
+{
+    return fsi_pll_is_enabled();
+}
+
+SECTION_CAR_TEXT
+static error_t fsi_clk_op_pll_enable(const struct car_clk_inf *clk)
+{
+    return fsi_pll_enable();
+}
+
+SECTION_CAR_TEXT
+static error_t fsi_clk_op_pll_disable(const struct car_clk_inf *clk)
+{
+    return fsi_pll_disable();
+}
+
+SECTION_CAR_RODATA
+static const struct car_clk_op_able fsi_clk_op_able_pll = {
+    .clk_is_enabled = fsi_clk_op_pll_is_enabled,
+    .clk_enable = fsi_clk_op_pll_enable,
+    .clk_disable = fsi_clk_op_pll_disable,
+};
+
+SECTION_CAR_TEXT
+static uint32_t fsi_clk_div_2N_1_in(int64_t hz_in, int64_t hz_out)
+{
+    float divider = (float)hz_in / hz_out;
+    if (divider > 0) {
+        divider = 2 * (divider - 1U);
+    }
+    return divider;
+}
+
+SECTION_CAR_TEXT
+static uint32_t fsi_clk_div_2N_1_out(const struct car_clk_inf *clk)
+{
+    uint32_t divider = 0;
+    if ((clk != NULL)) {
+        divider = car_reg_rd_val(clk->div_reg, clk->div_msk);
+        divider = divider >> 1U;
+        divider += 1;
+    }
+    return divider;
+}
+
+SECTION_CAR_RODATA
+static const struct car_clk_op_div  car_clk_op_div_2N_1 = {
+    .clk_div_calc_in = fsi_clk_div_2N_1_in,
+    .clk_div_calc_out = fsi_clk_div_2N_1_out,
+};
+
+SECTION_CAR_TEXT
+static error_t fsi_clk_op_pll_hz_get(const struct car_clk_inf *clk, int64_t *hz_out)
+{
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (hz_out != NULL) {
+        if (fsi_pll_is_enabled() == true) {
+            ret = fsi_pll_get_rate(hz_out);
+        } else {
+            ret = fsi_clk_op_xtal_hz_get(NULL, hz_out);
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+static error_t fsi_clk_op_pll_hz_set(const struct car_clk_inf *clk, int64_t hz_out)
+{
+    return fsi_pll_set_rate(hz_out);
+}
+
+SECTION_CAR_RODATA
+static const struct car_clk_op_rate fsi_clk_op_rate_pll = {
+    .clk_hz_get = fsi_clk_op_pll_hz_get,
+    .clk_hz_set = fsi_clk_op_pll_hz_set,
+};
+
+
+SECTION_CAR_RODATA
+const struct car_clk_inf fsi_clk_infs[] = {
+    /* fsi_xtal_clk */
+    CLK_INF(FSI_CLK_ID_XTAL,
+            &fsi_clk_op_able_xtal,              /* op_able */
+            0,                                  /* en_reg */
+            0,                                  /* en_msk */
+            0,                                  /* div_reg */
+            0,                                  /* div_msk */
+            NULL,                               /* op_div */
+            &fsi_clk_op_rate_xtal,              /* op_rate */
+            40000000,                           /* rate_min */
+            40000000,                           /* rate_max */
+            NULL,                               /* pclk */
+            &fsi_fmon_infs[FSI_FMON_ID_XTAL]),  /* fmon */
+    /* fsi_pll_clk */
+    CLK_INF(FSI_CLK_ID_PLL,
+            &fsi_clk_op_able_pll,               /* op_able */
+            0,                                  /* en_reg */
+            0,                                  /* en_msk */
+            0,                                  /* div_reg */
+            0,                                  /* div_msk */
+            NULL,                               /* op_div */
+            &fsi_clk_op_rate_pll,               /* op_rate */
+            0,                                  /* rate_min */
+            0,                                  /* rate_max */
+            &fsi_clk_infs[FSI_CLK_ID_XTAL],     /* pclk */
+            &fsi_fmon_infs[FSI_FMON_ID_PLL]),   /* fmon */
+    /* fsi_chsm_cpu_clk */
+    CLK_INF(FSI_CLK_ID_CHSM_CPU,
+            &car_clk_op_able_bit,               /* op_able */
+            CLK_RST_CONTROLLER_FSICHSM_CPU_BASE_0_0, /* en_reg */
+            CLK_RST_CONTROLLER_FSICHSM_CPU_BASE_0_0_FSICHSM_CPU_CE_FIELD,
+            CLK_RST_CONTROLLER_FSICHSM_CPU_BASE_0_0, /* div_reg */
+            CLK_RST_CONTROLLER_FSICHSM_CPU_BASE_0_0_FSICHSM_CPU_DIVRATIO_FIELD,
+            NULL,                               /* op_div */
+            &car_clk_op_rate_dflt,              /* op_rate */
+            0,                                  /* rate_min */
+            0,                                  /* rate_max */
+            &fsi_clk_infs[FSI_CLK_ID_PLL],      /* pclk */
+            &fsi_fmon_infs[FSI_FMON_ID_CHSM]),  /* fmon */
+    /* fsi_fabric_clk */
+    CLK_INF(FSI_CLK_ID_FABRIC_CLK,
+            NULL,                               /* op_able */
+            0,                                  /* en_reg */
+            0,                                  /* en_msk */
+            CLK_RST_CONTROLLER_FSI_FABRIC_BASE_0_0,
+            CLK_RST_CONTROLLER_FSI_FABRIC_BASE_0_0_FSI_FABRIC_DIVRATIO_FIELD,
+            NULL,                               /* op_div */
+            &car_clk_op_rate_dflt,              /* op_rate */
+            0,                                  /* rate_min */
+            0,                                  /* rate_max */
+            &fsi_clk_infs[FSI_CLK_ID_PLL],      /* pclk */
+            &fsi_fmon_infs[FSI_FMON_ID_FABRIC]), /* fmon */
+    /* fsi_fabric_pclk */
+    CLK_INF(FSI_CLK_ID_FABRIC_PCLK,
+            NULL,                               /* op_able */
+            0,                                  /* en_reg */
+            0,                                  /* en_msk */
+            0,                                  /* div_reg */
+            0,                                  /* div_msk */
+            NULL,                               /* op_div */
+            &car_clk_op_rate_dflt,              /* op_rate */
+            0,                                  /* rate_min */
+            0,                                  /* rate_max */
+            &fsi_clk_infs[FSI_CLK_ID_PLL],      /* pclk */
+            &fsi_fmon_infs[FSI_FMON_ID_FABRIC]), /* fmon */
+    /* fsi_se_fr_clk */
+    CLK_INF(FSI_CLK_ID_SE_FR,
+            &car_clk_op_able_bit,               /* op_able */
+            0,                                  /* en_reg */
+            0,                                  /* en_msk */
+            0,                                  /* div_reg */
+            0,                                  /* div_msk */
+            NULL,                               /* op_div */
+            &car_clk_op_rate_dflt,              /* op_rate */
+            0,                                  /* rate_min */
+            0,                                  /* rate_max */
+            &fsi_clk_infs[FSI_CLK_ID_PLL],      /* pclk */
+            &fsi_fmon_infs[FSI_FMON_ID_FABRIC]), /* fmon */
+    /* fsi_se_clk */
+    CLK_INF(FSI_CLK_ID_SE,
+            &car_clk_op_able_bit,               /* op_able */
+            CLK_RST_CONTROLLER_FSI_MISC_CONFIG_0_0, /* en_reg */
+            CLK_RST_CONTROLLER_FSI_MISC_CONFIG_0_0_FSI_SE_CE_SHIFT,
+            0,                                  /* div_reg */
+            0,                                  /* div_msk */
+            NULL,                               /* op_div */
+            &car_clk_op_rate_dflt,              /* op_rate */
+            0,                                  /* rate_min */
+            0,                                  /* rate_max */
+            &fsi_clk_infs[FSI_CLK_ID_PLL],      /* pclk */
+            &fsi_fmon_infs[FSI_FMON_ID_FABRIC]), /* fmon */
+    /* fsi_sram_clk */
+    CLK_INF(FSI_CLK_ID_SRAM_CLK,
+            NULL,                               /* op_able */
+            0,                                  /* en_reg */
+            0,                                  /* en_msk */
+            0,                                  /* div_reg */
+            0,                                  /* div_msk */
+            NULL,                               /* op_div */
+            &car_clk_op_rate_dflt,              /* op_rate */
+            0,                                  /* rate_min */
+            0,                                  /* rate_max */
+            &fsi_clk_infs[FSI_CLK_ID_PLL],      /* pclk */
+            &fsi_fmon_infs[FSI_FMON_ID_FABRIC]), /* fmon */
+    /* fsi_sram_pclk */
+    CLK_INF(FSI_CLK_ID_SRAM_PCLK,
+            NULL,                               /* op_able */
+            0,                                  /* en_reg */
+            0,                                  /* en_msk */
+            0,                                  /* div_reg */
+            0,                                  /* div_msk */
+            NULL,                               /* op_div */
+            &car_clk_op_rate_dflt,              /* op_rate */
+            0,                                  /* rate_min */
+            0,                                  /* rate_max */
+            &fsi_clk_infs[FSI_CLK_ID_PLL],      /* pclk */
+            &fsi_fmon_infs[FSI_FMON_ID_FABRIC]), /* fmon */
+    /* fsi_uart0_baud_clk */
+    CLK_INF(FSI_CLK_ID_UART0,
+            &car_clk_op_able_reg,               /* op_able */
+            CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTFSI_0, /* en_reg */
+            CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTFSI_0_CLK_ENB_UARTFSI_FIELD,
+            CLK_RST_CONTROLLER_CLK_SOURCE_UARTFSI_0, /* div_reg */
+            CLK_RST_CONTROLLER_CLK_SOURCE_UARTFSI_0_UARTFSI_CLK_DIVISOR_FIELD,
+            &car_clk_op_div_2N_1,               /* op_div */
+            &car_clk_op_rate_dflt,              /* op_rate */
+            0,                                  /* rate_min */
+            0,                                  /* rate_max */
+            &fsi_clk_infs[FSI_CLK_ID_XTAL],     /* pclk */
+            NULL),                              /* fmon */
+    /* fsi_ts_clk */
+    CLK_INF(FSI_CLK_ID_TS,
+            &car_clk_op_able_bit,               /* op_able */
+            CLK_RST_CONTROLLER_FSI_TS_BASE_0_0, /* en_reg */
+            CLK_RST_CONTROLLER_FSI_TS_BASE_0_0_FSI_TS_CE_FIELD,
+            CLK_RST_CONTROLLER_FSI_TS_BASE_0_0, /* div_reg */
+            CLK_RST_CONTROLLER_FSI_TS_BASE_0_0_FSI_TS_DIVRATIO_FIELD,
+            &car_clk_op_div_2N_1,               /* op_div */
+            &car_clk_op_rate_dflt,              /* op_rate */
+            0,                                  /* rate_min */
+            0,                                  /* rate_max */
+            &fsi_clk_infs[FSI_CLK_ID_XTAL],     /* pclk */
+            &fsi_fmon_infs[FSI_FMON_ID_TS]),    /* fmon */
+    /* fsi_spi_clk */
+    CLK_INF(FSI_CLK_ID_SPI0,
+            &car_clk_op_able_bit,               /* op_able */
+            CLK_RST_CONTROLLER_FSI_SPI_BASE_0_0, /* en_reg */
+            CLK_RST_CONTROLLER_FSI_SPI_BASE_0_0_FSI_SPI_CE_FIELD,
+            CLK_RST_CONTROLLER_FSI_SPI_BASE_0_0, /* div_reg */
+            CLK_RST_CONTROLLER_FSI_SPI_BASE_0_0_FSI_SPI_DIVRATIO_FIELD,
+            NULL,                               /* op_div */
+            &car_clk_op_rate_dflt,              /* op_rate */
+            0,                                  /* rate_min */
+            0,                                  /* rate_max */
+            &fsi_clk_infs[FSI_CLK_ID_XTAL],     /* pclk */
+            &fsi_fmon_infs[FSI_FMON_ID_SPI]),   /* fmon */
+    /* fsi_mc_clk */
+    CLK_INF(FSI_CLK_ID_MC,
+            &car_clk_op_able_bit,               /* op_able */
+            CLK_RST_CONTROLLER_FSI_MISC_CONFIG_0_0, /* en_reg */
+            CLK_RST_CONTROLLER_FSI_MISC_CONFIG_0_0_FSI_MC_CE_FIELD,
+            0,                                  /* div_reg */
+            0,                                  /* div_msk */
+            NULL,                               /* op_div */
+            &car_clk_op_rate_dflt,              /* op_rate */
+            0,                                  /* rate_min */
+            0,                                  /* rate_max */
+            &fsi_clk_infs[FSI_CLK_ID_XTAL],     /* pclk */
+            NULL),                              /* fmon */
+    /* fsi_csite_clk */
+    CLK_INF(FSI_CLK_ID_CSITE,
+            &car_clk_op_able_bit,               /* op_able */
+            CLK_RST_CONTROLLER_FSI_MISC_CONFIG_0_0, /* en_reg */
+            CLK_RST_CONTROLLER_FSI_MISC_CONFIG_0_0_FSI_CSITE_CE_FIELD,
+            0,                                  /* div_reg */
+            0,                                  /* div_msk */
+            NULL,                               /* op_div */
+            &car_clk_op_rate_dflt,              /* op_rate */
+            0,                                  /* rate_min */
+            0,                                  /* rate_max */
+            &fsi_clk_infs[FSI_CLK_ID_PLL],      /* pclk */
+            &fsi_fmon_infs[FSI_FMON_ID_FABRIC]), /* fmon */
+    /* fsi_la_clk */
+    CLK_INF(FSI_CLK_ID_LA,
+            &car_clk_op_able_bit,               /* op_able */
+            CLK_RST_CONTROLLER_FSI_MISC_CONFIG_0_0, /* en_reg */
+            CLK_RST_CONTROLLER_FSI_MISC_CONFIG_0_0_FSI_LA_CE_FIELD,
+            0,                                  /* div_reg */
+            0,                                  /* div_msk */
+            NULL,                               /* op_div */
+            &car_clk_op_rate_dflt,              /* op_rate */
+            0,                                  /* rate_min */
+            0,                                  /* rate_max */
+            &fsi_clk_infs[FSI_CLK_ID_PLL],      /* pclk */
+            &fsi_fmon_infs[FSI_FMON_ID_FABRIC]), /* fmon */
+    /* fsi_jtag_reg_clk */
+    CLK_INF(FSI_CLK_ID_JTAG,
+            &car_clk_op_able_bit,               /* op_able */
+            CLK_RST_CONTROLLER_FSI_MISC_CONFIG_0_0, /* en_reg */
+            CLK_RST_CONTROLLER_FSI_MISC_CONFIG_0_0_FSI_JTAG_CE_FIELD,
+            0,                                  /* div_reg */
+            0,                                  /* div_msk */
+            NULL,                               /* op_div */
+            &car_clk_op_rate_dflt,              /* op_rate */
+            0,                                  /* rate_min */
+            0,                                  /* rate_max */
+            NULL,                               /* pclk */
+            NULL),                              /* fmon */
+};
+
+
+SECTION_CAR_DATA
+static bool fsi_clk_fmon = false;
+
+SECTION_CAR_TEXT
+bool fsi_clk_fmon_is_enabled(void)
+{
+    return fsi_clk_fmon;
+}
+
+SECTION_CAR_TEXT
+void fsi_clk_fmon_enable(void)
+{
+    fsi_clk_fmon = true;
+}
+
+SECTION_CAR_TEXT
+void fsi_clk_fmon_disable(void)
+{
+    fsi_clk_fmon = false;
+}
+
+SECTION_CAR_TEXT
+static struct car_clk_inf *fsi_clk_inf_get(uint32_t clk_id)
+{
+    struct car_clk_inf *clk = NULL;
+
+    if (clk_id < ARRAY_SIZE(fsi_clk_infs)) {
+        clk = (struct car_clk_inf *)&fsi_clk_infs[clk_id];
+    }
+    return clk;
+}
+
+SECTION_CAR_TEXT
+error_t fsi_clk_enable(uint32_t clk_id)
+{
+    struct car_clk_inf *clk = fsi_clk_inf_get(clk_id);
+    error_t ret = E_CAR_INVALID_CLOCK_ID;
+
+    if (clk != NULL) {
+        if (clk->op_able == NULL) {
+            ret = E_CAR_CLOCK_OP_NOT_SUPPORTED;
+        } else {
+            ret = clk->op_able->clk_enable(clk);
+            if (ret == E_SUCCESS) {
+                if ((clk->fmon != NULL) && (fsi_clk_fmon == true)) {
+                    ret = car_fmon_startup(clk->fmon);
+                }
+            }
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t fsi_clk_disable(uint32_t clk_id)
+{
+    struct car_clk_inf *clk = fsi_clk_inf_get(clk_id);
+    error_t ret = E_CAR_INVALID_CLOCK_ID;
+
+    if (clk != NULL) {
+        if (clk->op_able == NULL) {
+            ret = E_CAR_CLOCK_OP_NOT_SUPPORTED;
+        } else {
+            if (fsi_clk_fmon == true) {
+                ret = car_fmon_shutdown(clk->fmon);
+            } else {
+                ret = E_SUCCESS;
+            }
+            if (ret == E_SUCCESS || ret == E_CAR_NULL_PTR) {
+                ret = clk->op_able->clk_disable(clk);
+            }
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+bool fsi_clk_is_enabled(uint32_t clk_id)
+{
+    struct car_clk_inf *clk = fsi_clk_inf_get(clk_id);
+    bool ret = false;
+
+    if (clk != NULL) {
+        if (clk->op_able != NULL) {
+            ret = clk->op_able->clk_is_enabled(clk);
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t fsi_clk_set_rate(uint32_t clk_id, int64_t hz_out)
+{
+    bool enabled;
+    struct car_clk_inf *clk = fsi_clk_inf_get(clk_id);
+    error_t ret = E_CAR_INVALID_CLOCK_ID;
+
+    if (clk != NULL) {
+        if ((clk->op_rate != NULL) &&
+            (clk->op_rate->clk_hz_set != NULL)) {
+            enabled = fsi_clk_is_enabled(clk_id);
+            ret = fsi_clk_disable(clk_id);
+            if (ret == E_SUCCESS) {
+                ret = clk->op_rate->clk_hz_set(clk, hz_out);
+                if (ret == E_CAR_NULL_PTR) {
+                    ret = E_CAR_CLOCK_OP_NOT_SUPPORTED;
+                }
+                if (enabled == true) {
+                    ret = fsi_clk_enable(clk_id);
+                }
+            }
+        } else {
+            ret = E_CAR_CLOCK_OP_NOT_SUPPORTED;
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t fsi_clk_get_rate(uint32_t clk_id, int64_t *hz_out)
+{
+    struct car_clk_inf *clk = fsi_clk_inf_get(clk_id);
+    error_t ret = E_CAR_INVALID_CLOCK_ID;
+
+    if (clk != NULL) {
+        if (hz_out == NULL) {
+            ret = E_CAR_NULL_PTR;
+        } else {
+            if ((clk->op_rate != NULL) &&
+                (clk->op_rate->clk_hz_get != NULL)) {
+                ret = clk->op_rate->clk_hz_get(clk, hz_out);
+                if (ret == E_CAR_NULL_PTR) {
+                    ret = E_CAR_CLOCK_OP_NOT_SUPPORTED;
+                }
+            } else {
+                ret = E_CAR_CLOCK_OP_NOT_SUPPORTED;
+            }
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t fsi_clk_set_div(uint32_t clk_id, uint32_t div)
+{
+    bool enabled;
+    struct car_clk_inf *clk = fsi_clk_inf_get(clk_id);
+    error_t ret = E_CAR_INVALID_CLOCK_ID;
+
+    if (clk != NULL) {
+        ret = E_CAR_CLOCK_OP_NOT_SUPPORTED;
+        if ((clk->op_rate != NULL) && (clk->op_rate->clk_hz_set != NULL)) {
+            enabled = fsi_clk_is_enabled(clk_id);
+            ret = fsi_clk_disable(clk_id);
+            if ((ret == E_SUCCESS) && clk->div_msk != 0U) {
+                car_reg_rdwr_val(clk->div_reg, clk->div_msk, div);
+                if (enabled == true) {
+                    ret = fsi_clk_enable(clk_id);
+                }
+            }
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t fsi_clk_get_div(uint32_t clk_id, uint32_t *div)
+{
+    struct car_clk_inf *clk = fsi_clk_inf_get(clk_id);
+    error_t ret = E_CAR_INVALID_CLOCK_ID;
+
+    if (clk != NULL) {
+        ret = E_CAR_NULL_PTR;
+        if (div != NULL) {
+            if (clk->div_msk != 0U) {
+                *div = car_reg_rd_val(clk->div_reg, clk->div_msk);
+                ret = E_SUCCESS;
+            } else {
+                ret = E_CAR_CLOCK_OP_NOT_SUPPORTED;
+            }
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_RODATA
+#define str_E_SUCCESS                   "Success\n"
+#define str_E_CAR_NULL_PTR              "NULL pointer\n"
+#define str_E_CAR_INVALID_PARAM         "Invalid parameter\n"
+#define str_E_CAR_INVALID_RESET_ID      "Invalid reset ID\n"
+#define str_E_CAR_INVALID_CLOCK_ID      "Invalid clock ID\n"
+#define str_E_CAR_INVALID_FMON_ID       "Invalid FMON ID\n"
+#define str_E_CAR_PLL_NO_INIT           "PLL not initialized\n"
+#define str_E_CAR_PLL_NO_LOCK           "PLL not locked\n"
+#define str_E_CAR_CLOCK_OP_NOT_SUPPORTED "Clock operation not supported\n"
+#define str_E_CAR_CLOCK_HZ_NOT_SUPPORTED "Frequency not supported\n"
+#define str_E_CAR_FMON_HW_LOGIC         "FMON hardware logic\n"
+#define str_E_CAR_FMON_HW_TIMEOUT       "FMON hardware timeout\n"
+#define str_E_CAR_FMON_FAULT            "FMON fault\n"
+#define str_E_CAR_FMON_NO_DATA          "FMON no data\n"
+#define str_E_CAR_ERROR_N               "Unknown\n"
+
+static const char * const car_err_strs[] = {
+    [0]                                             = str_E_SUCCESS,
+    [MODULE_ERROR_CODE(E_CAR_NULL_PTR)]             = str_E_CAR_NULL_PTR,
+    [MODULE_ERROR_CODE(E_CAR_INVALID_PARAM)]        = str_E_CAR_INVALID_PARAM,
+    [MODULE_ERROR_CODE(E_CAR_INVALID_RESET_ID)]     = str_E_CAR_INVALID_RESET_ID,
+    [MODULE_ERROR_CODE(E_CAR_INVALID_CLOCK_ID)]     = str_E_CAR_INVALID_CLOCK_ID,
+    [MODULE_ERROR_CODE(E_CAR_INVALID_FMON_ID)]      = str_E_CAR_INVALID_FMON_ID,
+    [MODULE_ERROR_CODE(E_CAR_PLL_NO_INIT)]          = str_E_CAR_PLL_NO_INIT,
+    [MODULE_ERROR_CODE(E_CAR_PLL_NO_LOCK)]          = str_E_CAR_PLL_NO_LOCK,
+    [MODULE_ERROR_CODE(E_CAR_CLOCK_OP_NOT_SUPPORTED)] = str_E_CAR_CLOCK_OP_NOT_SUPPORTED,
+    [MODULE_ERROR_CODE(E_CAR_CLOCK_HZ_NOT_SUPPORTED)] = str_E_CAR_CLOCK_HZ_NOT_SUPPORTED,
+    [MODULE_ERROR_CODE(E_CAR_FMON_HW_LOGIC)]        = str_E_CAR_FMON_HW_LOGIC,
+    [MODULE_ERROR_CODE(E_CAR_FMON_HW_TIMEOUT)]      = str_E_CAR_FMON_HW_TIMEOUT,
+    [MODULE_ERROR_CODE(E_CAR_FMON_FAULT)]           = str_E_CAR_FMON_FAULT,
+    [MODULE_ERROR_CODE(E_CAR_FMON_NO_DATA)]         = str_E_CAR_FMON_NO_DATA,
+    [MODULE_ERROR_CODE(E_CAR_ERROR_N)]              = str_E_CAR_ERROR_N,
+};
+
+SECTION_CAR_TEXT
+const char *fsi_car_get_err_str(error_t err)
+{
+    uint32_t i = MODULE_ERROR_CODE(err);
+    uint32_t n = MODULE_ERROR_CODE(E_CAR_ERROR_N);
+    const char *str = car_err_strs[n];
+
+    if (i < n) {
+        str = car_err_strs[i];
+    }
+
+    return str;
+}
+
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/fsi/fsi-car-fmon.c b/spe-freertos-bsp/fsp/source/soc/t234/port/fsi/fsi-car-fmon.c
new file mode 100644
index 0000000..fdc2c44
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/fsi/fsi-car-fmon.c
@@ -0,0 +1,474 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stddef.h>                     // for NULL
+#include <stdbool.h>                    // for bool, false
+#include <stdint.h>                     // for uint32_t, uint8_t, UINT8_MAX, UIN...
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>         // for CT_ASSERT
+#include <soc-common/hw-const.h>    /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <arclk_rst.h>              // for CLK_RST_CONTROLLER_FMON_CONFIG_PLL_FSI_0...
+#include <arintr_ctlr.h>            // for INTR_CTLR_CHANNEL0_SLICE0_IER_0...
+
+/* Late FSP headers */
+#include <misc/macros.h>            // for ARRAY_SIZE,...
+#include <error/common-errors.h>    // for E_SUCCESS, error_t
+#include <misc/bitops.h>            // for BIT, bit_number, FSP__MISC__BITOPS_H
+
+/* Module-specific FSP headers */
+#include <car/car-sections.h>       // for SECTION_CAR_TEXT ...
+#include <car/car-errors.h>         // for E_CAR_ERR_NULL_PTR, E_CAR_ERR_NO_...
+#include <car/car-fmon.h>           // for core FMON functions...
+#include <port/car-port.h>              // for platform functions...
+#include <port/car-clk.h>           // for clock frequency defines, ...
+#include <port/car-fmon.h>          // for FMON API functions ...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+START_RFD_BLOCK(MISRA, DEVIATE, Rule_1_2, "Approval: Bug 200531996, DR: SWE-FSP-009-SWSADR.docx", MISRA, DEVIATE, Directive_4_9, "Approval: Bug 200531995, DR: SWE-FSP-012-SWSADR.docx")
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__BITOPS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_FMON_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__PORT__CAR_PORT_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__FSI__CAR_FMON_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__FSI__CAR_CLK_H, "Header file missing or invalid.")
+
+
+SECTION_CAR_RODATA
+const struct car_fmon_count_inf fsi_fmon_count_inf = {
+    .cnt_sel_min                = FSI_FMON_CLK_COUNT_MIN,
+    .cnt_sel_max                = FSI_FMON_CLK_COUNT_MAX,
+    .cnt_sel_0                  = FSI_FMON_CLK_COUNT_LATEST,
+    .cnt_sel_n                  = (FSI_FMON_CLK_COUNT_EARLIEST - FSI_FMON_CLK_COUNT_LATEST) + 1,
+    .cnt_sel_min_i              = (FSI_FMON_CLK_COUNT_MIN + 1),
+    .cnt_sel_max_i              = (FSI_FMON_CLK_COUNT_MAX + 1),
+    .cnt_sel_0_i                = (FSI_FMON_CLK_COUNT_LATEST + 1),
+    .cnt_ref_win_i              = 0,
+    .cnt_ref_win_dc_chk_i       = 1,
+};
+
+const struct car_fmon_inf fsi_fmon_infs[] = {
+    [FSI_FMON_ID_PLL] = {
+        .clk                    = &fsi_clk_infs[FSI_CLK_ID_PLL],
+        .clk_ref                = FSI_CLK_XTAL_HZ,
+        .clk_err                = FSI_CLK_XTAL_HZ,
+        .reg_thr_hi             = CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PLL_FSI_0,
+        .reg_thr_hi_msk         = CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_PLL_FSI_0_PLL_FSI_FMON_COUNT_THRESH_HIGH_FIELD,
+        .reg_thr_lo             = CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PLL_FSI_0,
+        .reg_thr_lo_msk         = CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_PLL_FSI_0_PLL_FSI_FMON_COUNT_THRESH_LOW_FIELD,
+        .reg_ref_win_cnt        = CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PLL_FSI_0,
+        .reg_ref_win_cnt_msk    = CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_PLL_FSI_0_PLL_FSI_FMON_REF_WINDOW_COUNT_FIELD,
+        .reg_ref_win_dc_chk_cnt = CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PLL_FSI_0,
+        .reg_ref_win_dc_chk_cnt_msk = CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_PLL_FSI_0_PLL_FSI_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD,
+        .reg_flt_actn           = CLK_RST_CONTROLLER_FMON_FAULT_ACTION_PLL_FSI_0,
+        .reg_flt_actn_msk       = 0,
+        .reg_cfg                = CLK_RST_CONTROLLER_FMON_CONFIG_PLL_FSI_0,
+        .reg_cfg_msk_rprt       = (CLK_RST_CONTROLLER_FMON_CONFIG_PLL_FSI_0_PLL_FSI_FMON_REPORT_OVERFLOW_ERROR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_PLL_FSI_0_PLL_FSI_FMON_REPORT_LOW_THRESH_VIOL_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_PLL_FSI_0_PLL_FSI_FMON_REPORT_HIGH_THRESH_VIOL_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_PLL_FSI_0_PLL_FSI_FMON_REPORT_DC_FAULT_VIOL_FIELD),
+        .reg_cfg_msk_ref_en     = CLK_RST_CONTROLLER_FMON_CONFIG_PLL_FSI_0_PLL_FSI_FMON_REF_CLK_WINDOW_EN_FIELD,
+        .reg_cfg_msk_cntr_en    = CLK_RST_CONTROLLER_FMON_CONFIG_PLL_FSI_0_PLL_FSI_FMON_ENABLE_FMON_COUNTER_FIELD,
+        .reg_cfg_msk_en         = CLK_RST_CONTROLLER_FMON_CONFIG_PLL_FSI_0_PLL_FSI_FMON_ENABLE_FIELD,
+        .reg_en_sts             = CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PLL_FSI_0,
+        .reg_en_sts_msk         = CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_PLL_FSI_0_READ_MASK,
+        .reg_flt_sts            = CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PLL_FSI_0,
+        .reg_flt_sts_msk_clr    = CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PLL_FSI_0_PLL_FSI_FMON_FAULT_CLEAR_FIELD,
+        .reg_flt_sts_msk_ro     = (CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PLL_FSI_0_PLL_FSI_FMON_FAULT_OUT_STATUS_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PLL_FSI_0_PLL_FSI_FMON_OVERFLOW_ERROR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PLL_FSI_0_PLL_FSI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PLL_FSI_0_PLL_FSI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_PLL_FSI_0_PLL_FSI_FMON_DC_FAULT_FIELD),
+        .reg_data_ctrl          = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PLL_FSI_0,
+        .reg_data_ctrl_msk_sel  = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PLL_FSI_0_PLL_FSI_FMON_LOAD_DATA_SEL_FIELD,
+        .reg_data_ctrl_msk_en   = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_PLL_FSI_0_PLL_FSI_FMON_LOAD_DATA_FIELD,
+        .reg_data_sts_done      = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PLL_FSI_0,
+        .reg_data_sts_done_msk  = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_PLL_FSI_0_PLL_FSI_FMON_LOAD_DATA_DONE_FIELD,
+        .reg_data_sts_sel       = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PLL_FSI_0,
+        .reg_data_sts_sel_msk   = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_PLL_FSI_0_PLL_FSI_FMON_LOAD_DATA_SEL_STATUS_FIELD,
+        .reg_data_val           = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PLL_FSI_0,
+        .reg_data_val_msk       = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_PLL_FSI_0_PLL_FSI_FMON_LOAD_DATA_VAL_FIELD,
+        .reg_cntr_ctrl          = CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PLL_FSI_0,
+        .reg_cntr_ctrl_msk_hld  = CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PLL_FSI_0_PLL_FSI_FMON_HOLD_COUNT_SAMPLES_FIELD,
+        .reg_cntr_ctrl_msk_clr  = (CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PLL_FSI_0_PLL_FSI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PLL_FSI_0_PLL_FSI_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_PLL_FSI_0_PLL_FSI_FMON_CLEAR_FMON_COUNTER_FIELD),
+        .cnt                    = &fsi_fmon_count_inf,
+    },
+    [FSI_FMON_ID_CHSM] = {
+        .clk                    = &fsi_clk_infs[FSI_CLK_ID_CHSM_CPU],
+        .clk_ref                = FSI_CLK_XTAL_HZ,
+        .clk_err                = FSI_CLK_XTAL_HZ,
+        .reg_thr_hi             = CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_FSI_CHSM_CPU_0,
+        .reg_thr_hi_msk         = CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_COUNT_THRESH_HIGH_FIELD,
+        .reg_thr_lo             = CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_FSI_CHSM_CPU_0,
+        .reg_thr_lo_msk         = CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_COUNT_THRESH_LOW_FIELD,
+        .reg_ref_win_cnt        = CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_FSI_CHSM_CPU_0,
+        .reg_ref_win_cnt_msk    = CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_REF_WINDOW_COUNT_FIELD,
+        .reg_ref_win_dc_chk_cnt = CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_FSI_CHSM_CPU_0,
+        .reg_ref_win_dc_chk_cnt_msk = CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD,
+        .reg_flt_actn           = CLK_RST_CONTROLLER_FMON_FAULT_ACTION_FSI_CHSM_CPU_0,
+        .reg_flt_actn_msk       = 0,
+        .reg_cfg                = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_CHSM_CPU_0,
+        .reg_cfg_msk_rprt       = (CLK_RST_CONTROLLER_FMON_CONFIG_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_REPORT_OVERFLOW_ERROR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_REPORT_LOW_THRESH_VIOL_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_REPORT_HIGH_THRESH_VIOL_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_REPORT_DC_FAULT_VIOL_FIELD),
+        .reg_cfg_msk_ref_en     = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_REF_CLK_WINDOW_EN_FIELD,
+        .reg_cfg_msk_cntr_en    = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_ENABLE_FMON_COUNTER_FIELD,
+        .reg_cfg_msk_en         = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_ENABLE_FIELD,
+        .reg_en_sts             = CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_FSI_CHSM_CPU_0,
+        .reg_en_sts_msk         = CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_FSI_CHSM_CPU_0_READ_MASK,
+        .reg_flt_sts            = CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_CHSM_CPU_0,
+        .reg_flt_sts_msk_clr    = CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_FAULT_CLEAR_FIELD,
+        .reg_flt_sts_msk_ro     = (CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_FAULT_OUT_STATUS_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_OVERFLOW_ERROR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_DC_FAULT_FIELD),
+        .reg_data_ctrl          = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_FSI_CHSM_CPU_0,
+        .reg_data_ctrl_msk_sel  = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_LOAD_DATA_SEL_FIELD,
+        .reg_data_ctrl_msk_en   = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_LOAD_DATA_FIELD,
+        .reg_data_sts_done      = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_FSI_CHSM_CPU_0,
+        .reg_data_sts_done_msk  = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_LOAD_DATA_DONE_FIELD,
+        .reg_data_sts_sel       = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_FSI_CHSM_CPU_0,
+        .reg_data_sts_sel_msk   = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_LOAD_DATA_SEL_STATUS_FIELD,
+        .reg_data_val           = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_FSI_CHSM_CPU_0,
+        .reg_data_val_msk       = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_LOAD_DATA_VAL_FIELD,
+        .reg_cntr_ctrl          = CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_CHSM_CPU_0,
+        .reg_cntr_ctrl_msk_hld  = CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_HOLD_COUNT_SAMPLES_FIELD,
+        .reg_cntr_ctrl_msk_clr  = (CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_CHSM_CPU_0_FSI_CHSM_CPU_FMON_CLEAR_FMON_COUNTER_FIELD),
+        .cnt                    = &fsi_fmon_count_inf,
+    },
+    [FSI_FMON_ID_FABRIC] = {
+        .clk                    = &fsi_clk_infs[FSI_CLK_ID_FABRIC_CLK],
+        .clk_ref                = FSI_CLK_XTAL_HZ,
+        .clk_err                = FSI_CLK_XTAL_HZ,
+        .reg_thr_hi             = CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_FSI_FABRIC_0,
+        .reg_thr_hi_msk         = CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_FSI_FABRIC_0_FSI_FABRIC_FMON_COUNT_THRESH_HIGH_FIELD,
+        .reg_thr_lo             = CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_FSI_FABRIC_0,
+        .reg_thr_lo_msk         = CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_FSI_FABRIC_0_FSI_FABRIC_FMON_COUNT_THRESH_LOW_FIELD,
+        .reg_ref_win_cnt        = CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_FSI_FABRIC_0,
+        .reg_ref_win_cnt_msk    = CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_FSI_FABRIC_0_FSI_FABRIC_FMON_REF_WINDOW_COUNT_FIELD,
+        .reg_ref_win_dc_chk_cnt = CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_FSI_FABRIC_0,
+        .reg_ref_win_dc_chk_cnt_msk = CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_FSI_FABRIC_0_FSI_FABRIC_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD,
+        .reg_flt_actn           = CLK_RST_CONTROLLER_FMON_FAULT_ACTION_FSI_FABRIC_0,
+        .reg_flt_actn_msk       = 0,
+        .reg_cfg                = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_FABRIC_0,
+        .reg_cfg_msk_rprt       = (CLK_RST_CONTROLLER_FMON_CONFIG_FSI_FABRIC_0_FSI_FABRIC_FMON_REPORT_OVERFLOW_ERROR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_FSI_FABRIC_0_FSI_FABRIC_FMON_REPORT_LOW_THRESH_VIOL_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_FSI_FABRIC_0_FSI_FABRIC_FMON_REPORT_HIGH_THRESH_VIOL_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_FSI_FABRIC_0_FSI_FABRIC_FMON_REPORT_DC_FAULT_VIOL_FIELD),
+        .reg_cfg_msk_ref_en     = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_FABRIC_0_FSI_FABRIC_FMON_REF_CLK_WINDOW_EN_FIELD,
+        .reg_cfg_msk_cntr_en    = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_FABRIC_0_FSI_FABRIC_FMON_ENABLE_FMON_COUNTER_FIELD,
+        .reg_cfg_msk_en         = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_FABRIC_0_FSI_FABRIC_FMON_ENABLE_FIELD,
+        .reg_en_sts             = CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_FSI_FABRIC_0,
+        .reg_en_sts_msk         = CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_FSI_FABRIC_0_READ_MASK,
+        .reg_flt_sts            = CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_FABRIC_0,
+        .reg_flt_sts_msk_clr    = CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_FABRIC_0_FSI_FABRIC_FMON_FAULT_CLEAR_FIELD,
+        .reg_flt_sts_msk_ro     = (CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_FABRIC_0_FSI_FABRIC_FMON_FAULT_OUT_STATUS_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_FABRIC_0_FSI_FABRIC_FMON_OVERFLOW_ERROR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_FABRIC_0_FSI_FABRIC_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_FABRIC_0_FSI_FABRIC_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_FABRIC_0_FSI_FABRIC_FMON_DC_FAULT_FIELD),
+        .reg_data_ctrl          = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_FSI_FABRIC_0,
+        .reg_data_ctrl_msk_sel  = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_FSI_FABRIC_0_FSI_FABRIC_FMON_LOAD_DATA_SEL_FIELD,
+        .reg_data_ctrl_msk_en   = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_FSI_FABRIC_0_FSI_FABRIC_FMON_LOAD_DATA_FIELD,
+        .reg_data_sts_done      = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_FSI_FABRIC_0,
+        .reg_data_sts_done_msk  = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_FSI_FABRIC_0_FSI_FABRIC_FMON_LOAD_DATA_DONE_FIELD,
+        .reg_data_sts_sel       = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_FSI_FABRIC_0,
+        .reg_data_sts_sel_msk   = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_FSI_FABRIC_0_FSI_FABRIC_FMON_LOAD_DATA_SEL_STATUS_FIELD,
+        .reg_data_val           = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_FSI_FABRIC_0,
+        .reg_data_val_msk       = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_FSI_FABRIC_0_FSI_FABRIC_FMON_LOAD_DATA_VAL_FIELD,
+        .reg_cntr_ctrl          = CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_FABRIC_0,
+        .reg_cntr_ctrl_msk_hld  = CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_FABRIC_0_FSI_FABRIC_FMON_HOLD_COUNT_SAMPLES_FIELD,
+        .reg_cntr_ctrl_msk_clr  = (CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_FABRIC_0_FSI_FABRIC_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_FABRIC_0_FSI_FABRIC_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_FABRIC_0_FSI_FABRIC_FMON_CLEAR_FMON_COUNTER_FIELD),
+        .cnt                    = &fsi_fmon_count_inf,
+    },
+    [FSI_FMON_ID_SPI] = {
+        .clk                    = &fsi_clk_infs[FSI_CLK_ID_SPI0],
+        .clk_ref                = FSI_CLK_XTAL_HZ,
+        .clk_err                = FSI_CLK_XTAL_HZ,
+        .reg_thr_hi             = CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_FSI_SPI_0,
+        .reg_thr_hi_msk         = CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_FSI_SPI_0_FSI_SPI_FMON_COUNT_THRESH_HIGH_FIELD,
+        .reg_thr_lo             = CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_FSI_SPI_0,
+        .reg_thr_lo_msk         = CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_FSI_SPI_0_FSI_SPI_FMON_COUNT_THRESH_LOW_FIELD,
+        .reg_ref_win_cnt        = CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_FSI_SPI_0,
+        .reg_ref_win_cnt_msk    = CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_FSI_SPI_0_FSI_SPI_FMON_REF_WINDOW_COUNT_FIELD,
+        .reg_ref_win_dc_chk_cnt = CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_FSI_SPI_0,
+        .reg_ref_win_dc_chk_cnt_msk = CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_FSI_SPI_0_FSI_SPI_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD,
+        .reg_flt_actn           = CLK_RST_CONTROLLER_FMON_FAULT_ACTION_FSI_SPI_0,
+        .reg_flt_actn_msk       = 0,
+        .reg_cfg                = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_SPI_0,
+        .reg_cfg_msk_rprt       = (CLK_RST_CONTROLLER_FMON_CONFIG_FSI_SPI_0_FSI_SPI_FMON_REPORT_OVERFLOW_ERROR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_FSI_SPI_0_FSI_SPI_FMON_REPORT_LOW_THRESH_VIOL_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_FSI_SPI_0_FSI_SPI_FMON_REPORT_HIGH_THRESH_VIOL_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_FSI_SPI_0_FSI_SPI_FMON_REPORT_DC_FAULT_VIOL_FIELD),
+        .reg_cfg_msk_ref_en     = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_SPI_0_FSI_SPI_FMON_REF_CLK_WINDOW_EN_FIELD,
+        .reg_cfg_msk_cntr_en    = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_SPI_0_FSI_SPI_FMON_ENABLE_FMON_COUNTER_FIELD,
+        .reg_cfg_msk_en         = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_SPI_0_FSI_SPI_FMON_ENABLE_FIELD,
+        .reg_en_sts             = CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_FSI_SPI_0,
+        .reg_en_sts_msk         = CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_FSI_SPI_0_READ_MASK,
+        .reg_flt_sts            = CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_SPI_0,
+        .reg_flt_sts_msk_clr    = CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_SPI_0_FSI_SPI_FMON_FAULT_CLEAR_FIELD,
+        .reg_flt_sts_msk_ro     = (CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_SPI_0_FSI_SPI_FMON_FAULT_OUT_STATUS_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_SPI_0_FSI_SPI_FMON_OVERFLOW_ERROR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_SPI_0_FSI_SPI_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_SPI_0_FSI_SPI_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_SPI_0_FSI_SPI_FMON_DC_FAULT_FIELD),
+        .reg_data_ctrl          = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_FSI_SPI_0,
+        .reg_data_ctrl_msk_sel  = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_FSI_SPI_0_FSI_SPI_FMON_LOAD_DATA_SEL_FIELD,
+        .reg_data_ctrl_msk_en   = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_FSI_SPI_0_FSI_SPI_FMON_LOAD_DATA_FIELD,
+        .reg_data_sts_done      = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_FSI_SPI_0,
+        .reg_data_sts_done_msk  = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_FSI_SPI_0_FSI_SPI_FMON_LOAD_DATA_DONE_FIELD,
+        .reg_data_sts_sel       = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_FSI_SPI_0,
+        .reg_data_sts_sel_msk   = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_FSI_SPI_0_FSI_SPI_FMON_LOAD_DATA_SEL_STATUS_FIELD,
+        .reg_data_val           = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_FSI_SPI_0,
+        .reg_data_val_msk       = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_FSI_SPI_0_FSI_SPI_FMON_LOAD_DATA_VAL_FIELD,
+        .reg_cntr_ctrl          = CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_SPI_0,
+        .reg_cntr_ctrl_msk_hld  = CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_SPI_0_FSI_SPI_FMON_HOLD_COUNT_SAMPLES_FIELD,
+        .reg_cntr_ctrl_msk_clr  = (CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_SPI_0_FSI_SPI_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_SPI_0_FSI_SPI_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_SPI_0_FSI_SPI_FMON_CLEAR_FMON_COUNTER_FIELD),
+        .cnt                    = &fsi_fmon_count_inf,
+    },
+    [FSI_FMON_ID_TS] = {
+        .clk                    = &fsi_clk_infs[FSI_CLK_ID_TS],
+        .clk_ref                = FSI_CLK_XTAL_HZ,
+        .clk_err                = FSI_CLK_XTAL_HZ,
+        .reg_thr_hi             = CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_FSI_TS_0,
+        .reg_thr_hi_msk         = CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_FSI_TS_0_FSI_TS_FMON_COUNT_THRESH_HIGH_FIELD,
+        .reg_thr_lo             = CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_FSI_TS_0,
+        .reg_thr_lo_msk         = CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_FSI_TS_0_FSI_TS_FMON_COUNT_THRESH_LOW_FIELD,
+        .reg_ref_win_cnt        = CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_FSI_TS_0,
+        .reg_ref_win_cnt_msk    = CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_FSI_TS_0_FSI_TS_FMON_REF_WINDOW_COUNT_FIELD,
+        .reg_ref_win_dc_chk_cnt = CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_FSI_TS_0,
+        .reg_ref_win_dc_chk_cnt_msk = CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_FSI_TS_0_FSI_TS_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD,
+        .reg_flt_actn           = CLK_RST_CONTROLLER_FMON_FAULT_ACTION_FSI_TS_0,
+        .reg_flt_actn_msk       = 0,
+        .reg_cfg                = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_TS_0,
+        .reg_cfg_msk_rprt       = (CLK_RST_CONTROLLER_FMON_CONFIG_FSI_TS_0_FSI_TS_FMON_REPORT_OVERFLOW_ERROR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_FSI_TS_0_FSI_TS_FMON_REPORT_LOW_THRESH_VIOL_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_FSI_TS_0_FSI_TS_FMON_REPORT_HIGH_THRESH_VIOL_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_FSI_TS_0_FSI_TS_FMON_REPORT_DC_FAULT_VIOL_FIELD),
+        .reg_cfg_msk_ref_en     = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_TS_0_FSI_TS_FMON_REF_CLK_WINDOW_EN_FIELD,
+        .reg_cfg_msk_cntr_en    = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_TS_0_FSI_TS_FMON_ENABLE_FMON_COUNTER_FIELD,
+        .reg_cfg_msk_en         = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_TS_0_FSI_TS_FMON_ENABLE_FIELD,
+        .reg_en_sts             = CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_FSI_TS_0,
+        .reg_en_sts_msk         = CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_FSI_TS_0_READ_MASK,
+        .reg_flt_sts            = CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_TS_0,
+        .reg_flt_sts_msk_clr    = CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_TS_0_FSI_TS_FMON_FAULT_CLEAR_FIELD,
+        .reg_flt_sts_msk_ro     = (CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_TS_0_FSI_TS_FMON_FAULT_OUT_STATUS_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_TS_0_FSI_TS_FMON_OVERFLOW_ERROR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_TS_0_FSI_TS_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_TS_0_FSI_TS_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_TS_0_FSI_TS_FMON_DC_FAULT_FIELD),
+        .reg_data_ctrl          = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_FSI_TS_0,
+        .reg_data_ctrl_msk_sel  = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_FSI_TS_0_FSI_TS_FMON_LOAD_DATA_SEL_FIELD,
+        .reg_data_ctrl_msk_en   = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_FSI_TS_0_FSI_TS_FMON_LOAD_DATA_FIELD,
+        .reg_data_sts_done      = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_FSI_TS_0,
+        .reg_data_sts_done_msk  = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_FSI_TS_0_FSI_TS_FMON_LOAD_DATA_DONE_FIELD,
+        .reg_data_sts_sel       = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_FSI_TS_0,
+        .reg_data_sts_sel_msk   = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_FSI_TS_0_FSI_TS_FMON_LOAD_DATA_SEL_STATUS_FIELD,
+        .reg_data_val           = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_FSI_TS_0,
+        .reg_data_val_msk       = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_FSI_TS_0_FSI_TS_FMON_LOAD_DATA_VAL_FIELD,
+        .reg_cntr_ctrl          = CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_TS_0,
+        .reg_cntr_ctrl_msk_hld  = CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_TS_0_FSI_TS_FMON_HOLD_COUNT_SAMPLES_FIELD,
+        .reg_cntr_ctrl_msk_clr  = (CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_TS_0_FSI_TS_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_TS_0_FSI_TS_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_TS_0_FSI_TS_FMON_CLEAR_FMON_COUNTER_FIELD),
+        .cnt                    = &fsi_fmon_count_inf,
+    },
+    [FSI_FMON_ID_XTAL] = {
+        .clk                    = &fsi_clk_infs[FSI_CLK_ID_XTAL],
+        .clk_ref                = FSI_CLK_VREFRO_HZ,
+        .clk_err                = FSI_CLK_VREFRO_HZ,
+        .reg_thr_hi             = CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_FSI_XTAL_0,
+        .reg_thr_hi_msk         = CLK_RST_CONTROLLER_FMON_THRESHOLD_HIGH_FSI_XTAL_0_FSI_XTAL_FMON_COUNT_THRESH_HIGH_FIELD,
+        .reg_thr_lo             = CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_FSI_XTAL_0,
+        .reg_thr_lo_msk         = CLK_RST_CONTROLLER_FMON_THRESHOLD_LOW_FSI_XTAL_0_FSI_XTAL_FMON_COUNT_THRESH_LOW_FIELD,
+        .reg_ref_win_cnt        = CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_FSI_XTAL_0,
+        .reg_ref_win_cnt_msk    = CLK_RST_CONTROLLER_FMON_REF_WINDOW_COUNT_FSI_XTAL_0_FSI_XTAL_FMON_REF_WINDOW_COUNT_FIELD,
+        .reg_ref_win_dc_chk_cnt = CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_FSI_XTAL_0,
+        .reg_ref_win_dc_chk_cnt_msk = CLK_RST_CONTROLLER_FMON_REF_WINDOW_DC_CHECK_COUNT_FSI_XTAL_0_FSI_XTAL_FMON_REF_WINDOW_DC_CHECK_COUNT_FIELD,
+        .reg_flt_actn           = CLK_RST_CONTROLLER_FMON_FAULT_ACTION_FSI_XTAL_0,
+        .reg_flt_actn_msk       = 0,
+        .reg_cfg                = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_XTAL_0,
+        .reg_cfg_msk_rprt       = (CLK_RST_CONTROLLER_FMON_CONFIG_FSI_XTAL_0_FSI_XTAL_FMON_REPORT_OVERFLOW_ERROR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_FSI_XTAL_0_FSI_XTAL_FMON_REPORT_LOW_THRESH_VIOL_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_FSI_XTAL_0_FSI_XTAL_FMON_REPORT_HIGH_THRESH_VIOL_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CONFIG_FSI_XTAL_0_FSI_XTAL_FMON_REPORT_DC_FAULT_VIOL_FIELD),
+        .reg_cfg_msk_ref_en     = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_XTAL_0_FSI_XTAL_FMON_REF_CLK_WINDOW_EN_FIELD,
+        .reg_cfg_msk_cntr_en    = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_XTAL_0_FSI_XTAL_FMON_ENABLE_FMON_COUNTER_FIELD,
+        .reg_cfg_msk_en         = CLK_RST_CONTROLLER_FMON_CONFIG_FSI_XTAL_0_FSI_XTAL_FMON_ENABLE_FIELD,
+        .reg_en_sts             = CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_FSI_XTAL_0,
+        .reg_en_sts_msk         = CLK_RST_CONTROLLER_FMON_ENABLE_STATUS_FSI_XTAL_0_READ_MASK,
+        .reg_flt_sts            = CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_XTAL_0,
+        .reg_flt_sts_msk_clr    = CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_XTAL_0_FSI_XTAL_FMON_FAULT_CLEAR_FIELD,
+        .reg_flt_sts_msk_ro     = (CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_XTAL_0_FSI_XTAL_FMON_FAULT_OUT_STATUS_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_XTAL_0_FSI_XTAL_FMON_OVERFLOW_ERROR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_XTAL_0_FSI_XTAL_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_XTAL_0_FSI_XTAL_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_FAULT_STATUS_FSI_XTAL_0_FSI_XTAL_FMON_DC_FAULT_FIELD),
+        .reg_data_ctrl          = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_FSI_XTAL_0,
+        .reg_data_ctrl_msk_sel  = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_FSI_XTAL_0_FSI_XTAL_FMON_LOAD_DATA_SEL_FIELD,
+        .reg_data_ctrl_msk_en   = CLK_RST_CONTROLLER_FMON_LOAD_DATA_CTRL_FSI_XTAL_0_FSI_XTAL_FMON_LOAD_DATA_FIELD,
+        .reg_data_sts_done      = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_FSI_XTAL_0,
+        .reg_data_sts_done_msk  = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_0_FSI_XTAL_0_FSI_XTAL_FMON_LOAD_DATA_DONE_FIELD,
+        .reg_data_sts_sel       = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_FSI_XTAL_0,
+        .reg_data_sts_sel_msk   = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_1_FSI_XTAL_0_FSI_XTAL_FMON_LOAD_DATA_SEL_STATUS_FIELD,
+        .reg_data_val           = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_FSI_XTAL_0,
+        .reg_data_val_msk       = CLK_RST_CONTROLLER_FMON_LOAD_DATA_STATUS_2_FSI_XTAL_0_FSI_XTAL_FMON_LOAD_DATA_VAL_FIELD,
+        .reg_cntr_ctrl          = CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_XTAL_0,
+        .reg_cntr_ctrl_msk_hld  = CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_XTAL_0_FSI_XTAL_FMON_HOLD_COUNT_SAMPLES_FIELD,
+        .reg_cntr_ctrl_msk_clr  = (CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_XTAL_0_FSI_XTAL_FMON_MIN_MAX_LASTN_COUNT_CLEAR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_XTAL_0_FSI_XTAL_FMON_MASK_MIN_MAX_COUNT_CLEAR_FIELD |
+                                   CLK_RST_CONTROLLER_FMON_CLEAR_COUNTER_FSI_XTAL_0_FSI_XTAL_FMON_CLEAR_FMON_COUNTER_FIELD),
+        .cnt                    = &fsi_fmon_count_inf,
+    },
+};
+
+SECTION_CAR_DATA
+static uint32_t fsi_clk_counts[sizeof(struct fsi_fmon_cnts)];
+
+SECTION_CAR_TEXT
+static struct car_fmon_inf *fsi_fmon_inf_get(uint32_t clk_id)
+{
+    struct car_fmon_inf *fmon = NULL;
+
+    if (clk_id < ARRAY_SIZE(fsi_clk_infs)) {
+        fmon = (struct car_fmon_inf *)fsi_clk_infs[clk_id].fmon;
+    }
+    return fmon;
+}
+
+bool fsi_fmon_is_enabled(uint32_t clk_id)
+{
+    struct car_fmon_inf *fmon = fsi_fmon_inf_get(clk_id);
+    bool ret = false;
+
+    if (fmon != NULL) {
+        ret = car_fmon_is_enabled(fmon);
+    }
+    return ret;
+}
+
+error_t fsi_fmon_clk_hz_calc(uint32_t clk_id, uint64_t *hz)
+{
+    struct car_fmon_inf *fmon = fsi_fmon_inf_get(clk_id);
+    error_t ret = E_CAR_INVALID_CLOCK_ID;
+
+    if (fmon != NULL) {
+        ret = car_fmon_clk_hz_calc(fmon, fsi_clk_counts, hz);
+    }
+    return ret;
+}
+
+error_t fsi_fmon_shutdown(uint32_t clk_id)
+{
+    struct car_fmon_inf *fmon = fsi_fmon_inf_get(clk_id);
+    error_t ret = E_CAR_INVALID_CLOCK_ID;
+
+    if (fmon != NULL) {
+        ret = car_fmon_shutdown(fmon);
+    }
+    return ret;
+}
+
+error_t fsi_fmon_startup(uint32_t clk_id)
+{
+    struct car_fmon_inf *fmon = fsi_fmon_inf_get(clk_id);
+    error_t ret = E_CAR_INVALID_CLOCK_ID;
+
+    if (fmon != NULL) {
+        ret = car_fmon_startup(fmon);
+    }
+    return ret;
+}
+
+error_t fsi_fmon_init(void)
+{
+    uint64_t ticks_start;
+    uint64_t ticks_us;
+    uint64_t delay_us;
+    uint32_t data;
+    uint32_t i;
+    error_t ret = E_SUCCESS;
+
+    ticks_start = car_port_get_time_ticks();
+    i = 0;
+    do {
+        ticks_us = car_port_get_time_delta_us(ticks_start);
+        data = car_fmon_enable_status(&fsi_fmon_infs[i]);
+        if (data != 0U) {
+            delay_us = car_fmon_timeout_us(&fsi_fmon_infs[i]);
+            if (delay_us > ticks_us) {
+                delay_us -= ticks_us;
+                car_port_udelay(delay_us);
+            } else {
+                ret = E_CAR_FMON_HW_TIMEOUT;
+                break;
+            }
+        } else {
+            ret = car_fmon_counts(&fsi_fmon_infs[i], fsi_clk_counts);
+            if (ret == E_SUCCESS) {
+                if ((fsi_clk_counts[fsi_fmon_infs[i].cnt->cnt_sel_min_i] == UINT32_MAX) &&
+                    (fsi_clk_counts[fsi_fmon_infs[i].cnt->cnt_sel_max_i] == 0U)) {
+                    ret = E_CAR_FMON_HW_LOGIC;
+                    break;
+                } else {
+                    i++;
+                }
+            } else {
+                break;
+            }
+        }
+    } while (i < FSI_FMON_ID_N);
+
+    return ret;
+}
+
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/fsi/fsi-car-pll.c b/spe-freertos-bsp/fsp/source/soc/t234/port/fsi/fsi-car-pll.c
new file mode 100644
index 0000000..aad5f0a
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/fsi/fsi-car-pll.c
@@ -0,0 +1,585 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stddef.h>                     // for NULL
+#include <stdbool.h>                    // for bool, false
+#include <stdint.h>                     // for uint32_t, uint8_t, UINT8_MAX, UIN...
+#include <string.h>                     // for memcpy
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+#include <soc-common/hw-const.h>        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <arclk_rst.h>                  // for CLK_RST_CONTROLLER_PLLFSI_BASE_0...
+
+/* Late FSP headers */
+#include <error/common-errors.h>        // for E_SUCCESS, error_t
+#include <misc/macros.h>                // for ARRAY_SIZE,...
+
+/* Module-specific FSP headers */
+#include <car/car-sections.h>           // for SECTION_CAR_TEXT, ...
+#include <car/car-errors.h>             // for E_CAR_ERR_NULL_PTR, E_CAR_ERR_NO_...
+#include <car/car-reg.h>                // for hardware access, ...
+#include <car/car-hpll.h>               // for HPLL functions, ...
+#include <port/car-pll.h>               // for PLL index, ...
+#include <port/car-clk.h>               // for CLK index, ...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_REG_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_HPLL_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__FSI__CAR_PLL_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__FSI__CAR_CLK_H, "Header file missing or invalid.")
+
+
+SECTION_CAR_RODATA
+static const struct fsi_pll_init_cfg fsi_pll_init_cfgs[] = {
+    [FSI_CAR_PLL_550mV_550MHz] = {
+        .hz                     = 550 * MHz,      /* hz */
+        .divm                   = 0x02,           /* divm */
+        .divp                   = 0x02,           /* divp */
+        .divn                   = 0x37,           /* divn */
+        .divn_frac              = 0x0000,         /* divn_frac */
+        .frac_step              = 0x0000,         /* frac_step */
+        .reg_misc_2             = 0x1F720F05,     /* reg_misc_2 */
+        .reg_misc_3             = 0x00000004,     /* reg_misc_3 */
+        .reg_misc_4             = 0x01CB0000,     /* reg_misc_4 */
+        .reg_misc_5             = 0x00000000,     /* reg_misc_5 */
+        .reg_misc_6             = 0x00000000,     /* reg_misc_6 */
+    },
+    [FSI_CAR_PLL_550mV_633MHz] = {
+        .hz                     = 633 * MHz,      /* hz */
+        .divm                   = 0x02,           /* divm */
+        .divp                   = 0x02,           /* divp */
+        .divn                   = 0x3F,           /* divn */
+        .divn_frac              = 0x0999,         /* divn_frac */
+        .frac_step              = 0x03E8,         /* frac_step */
+        .reg_misc_2             = 0x1F720F05,     /* reg_misc_2 */
+        .reg_misc_3             = 0x00000004,     /* reg_misc_3 */
+        .reg_misc_4             = 0x01CB03E8,     /* reg_misc_4 */
+        .reg_misc_5             = 0x00000000,     /* reg_misc_5 */
+        .reg_misc_6             = 0x00000000,     /* reg_misc_6 */
+    },
+    [FSI_CAR_PLL_600mV_780MHz] = {
+        .hz                     = 780 * MHz,      /* hz */
+        .divm                   = 0x02,           /* divm */
+        .divp                   = 0x02,           /* divp */
+        .divn                   = 0x4E,           /* divn */
+        .divn_frac              = 0x0000,         /* divn_frac */
+        .frac_step              = 0x0000,         /* frac_step */
+        .reg_misc_2             = 0x1F720F05,     /* reg_misc_2 */
+        .reg_misc_3             = 0x00000004,     /* reg_misc_3 */
+        .reg_misc_4             = 0x01CB0000,     /* reg_misc_4 */
+        .reg_misc_5             = 0x00000000,     /* reg_misc_5 */
+        .reg_misc_6             = 0x00000000,     /* reg_misc_6 */
+    },
+    [FSI_CAR_PLL_600mV_897MHz] = {
+        .hz                     = 897 * MHz,      /* hz_out */
+        .divm                   = 0x02,           /* divm */
+        .divp                   = 0x01,           /* divp */
+        .divn                   = 0x2C,           /* divn */
+        .divn_frac              = 0x1B33,         /* divn_frac */
+        .frac_step              = 0x06CC,         /* frac_step */
+        .reg_misc_2             = 0x1F720F05,     /* reg_misc_2 */
+        .reg_misc_3             = 0x00000004,     /* reg_misc_3 */
+        .reg_misc_4             = 0x01CB06CC,     /* reg_misc_4 */
+        .reg_misc_5             = 0x00000000,     /* reg_misc_5 */
+        .reg_misc_6             = 0x00000000,     /* reg_misc_6 */
+    },
+    [FSI_CAR_PLL_670mV_1130MHz] = {
+        .hz                     = 1130 * MHz,     /* hz */
+        .divm                   = 0x02,           /* divm */
+        .divp                   = 0x01,           /* divp */
+        .divn                   = 0x38,           /* divn */
+        .divn_frac              = 0x1000,         /* divn_frac */
+        .frac_step              = 0x0400,         /* frac_step */
+        .reg_misc_2             = 0x1F720F05,     /* reg_misc_2 */
+        .reg_misc_3             = 0x00000004,     /* reg_misc_3 */
+        .reg_misc_4             = 0x01CB0400,     /* reg_misc_4 */
+        .reg_misc_5             = 0x00000000,     /* reg_misc_5 */
+        .reg_misc_6             = 0x00000000,     /* reg_misc_6 */
+    },
+    [FSI_CAR_PLL_670mV_1300MHz] = {
+        .hz                     = 1300 * MHz,     /* hz */
+        .divm                   = 0x02,           /* divm */
+        .divp                   = 0x01,           /* divp */
+        .divn                   = 0x41,           /* divn */
+        .divn_frac              = 0x0000,         /* divn_frac */
+        .frac_step              = 0x0000,         /* frac_step */
+        .reg_misc_2             = 0x1F720F05,     /* reg_misc_2 */
+        .reg_misc_3             = 0x00000004,     /* reg_misc_3 */
+        .reg_misc_4             = 0x01CB0000,     /* reg_misc_4 */
+        .reg_misc_5             = 0x00000000,     /* reg_misc_5 */
+        .reg_misc_6             = 0x00000000,     /* reg_misc_6 */
+    },
+    [FSI_CAR_PLL_720mV_1130MHz] = {
+        .hz                     = 1130 * MHz,     /* hz */
+        .divm                   = 0x02,           /* divm */
+        .divp                   = 0x01,           /* divp */
+        .divn                   = 0x38,           /* divn */
+        .divn_frac              = 0x1000,         /* divn_frac */
+        .frac_step              = 0x0400,         /* frac_step */
+        .reg_misc_2             = 0x1F720F05,     /* reg_misc_2 */
+        .reg_misc_3             = 0x00000004,     /* reg_misc_3 */
+        .reg_misc_4             = 0x01CB0400,     /* reg_misc_4 */
+        .reg_misc_5             = 0x00000000,     /* reg_misc_5 */
+        .reg_misc_6             = 0x00000000,     /* reg_misc_6 */
+    },
+    [FSI_CAR_PLL_720mV_1300MHz] = {
+        .hz                     = 1300 * MHz,     /* hz */
+        .divm                   = 0x02,           /* divm */
+        .divp                   = 0x01,           /* divp */
+        .divn                   = 0x41,           /* divn */
+        .divn_frac              = 0x0000,         /* divn_frac */
+        .frac_step              = 0x0000,         /* frac_step */
+        .reg_misc_2             = 0x1F720F05,     /* reg_misc_2 */
+        .reg_misc_3             = 0x00000004,     /* reg_misc_3 */
+        .reg_misc_4             = 0x01CB0000,     /* reg_misc_4 */
+        .reg_misc_5             = 0x00000000,     /* reg_misc_5 */
+        .reg_misc_6             = 0x00000000,     /* reg_misc_6 */
+    },
+    [FSI_CAR_PLL_850mV_1400MHz] = {
+        .hz                     = 1400 * MHz,     /* hz */
+        .divm                   = 0x02,           /* divm */
+        .divp                   = 0x01,           /* divp */
+        .divn                   = 0x46,           /* divn */
+        .divn_frac              = 0x0000,         /* divn_frac */
+        .frac_step              = 0x0000,         /* frac_step */
+        .reg_misc_2             = 0x1F720F05,     /* reg_misc_2 */
+        .reg_misc_3             = 0x00000004,     /* reg_misc_3 */
+        .reg_misc_4             = 0x01CB0000,     /* reg_misc_4 */
+        .reg_misc_5             = 0x00000000,     /* reg_misc_5 */
+        .reg_misc_6             = 0x00000000,     /* reg_misc_6 */
+    },
+    [FSI_CAR_PLL_850mV_1610MHz] = {
+        .hz                     = 1610 * MHz,     /* hz */
+        .divm                   = 0x02,           /* divm */
+        .divp                   = 0x01,           /* divp */
+        .divn                   = 0x50,           /* divn */
+        .divn_frac              = 0x1000,         /* divn_frac */
+        .frac_step              = 0x0400,         /* frac_step */
+        .reg_misc_2             = 0x1F720F05,     /* reg_misc_2 */
+        .reg_misc_3             = 0x00000004,     /* reg_misc_3 */
+        .reg_misc_4             = 0x01CB0400,     /* reg_misc_4 */
+        .reg_misc_5             = 0x00000000,     /* reg_misc_5 */
+        .reg_misc_6             = 0x00000000,     /* reg_misc_6 */
+    },
+    [FSI_CAR_PLL_940mV_1400MHz] = {
+        .hz                     = 1400 * MHz,     /* hz */
+        .divm                   = 0x02,           /* divm */
+        .divp                   = 0x01,           /* divp */
+        .divn                   = 0x46,           /* divn */
+        .divn_frac              = 0x0000,         /* divn_frac */
+        .frac_step              = 0x0000,         /* frac_step */
+        .reg_misc_2             = 0x1F720F05,     /* reg_misc_2 */
+        .reg_misc_3             = 0x00000004,     /* reg_misc_3 */
+        .reg_misc_4             = 0x01CB0000,     /* reg_misc_4 */
+        .reg_misc_5             = 0x00000000,     /* reg_misc_5 */
+        .reg_misc_6             = 0x00000000,     /* reg_misc_6 */
+    },
+    [FSI_CAR_PLL_940mV_1610MHz] = {
+        .hz                     = 1610 * MHz,     /* hz */
+        .divm                   = 0x02,           /* divm */
+        .divp                   = 0x01,           /* divp */
+        .divn                   = 0x50,           /* divn */
+        .divn_frac              = 0x1000,         /* divn_frac */
+        .frac_step              = 0x0400,         /* frac_step */
+        .reg_misc_2             = 0x1F720F05,     /* reg_misc_2 */
+        .reg_misc_3             = 0x00000004,     /* reg_misc_3 */
+        .reg_misc_4             = 0x01CB0400,     /* reg_misc_4 */
+        .reg_misc_5             = 0x00000000,     /* reg_misc_5 */
+        .reg_misc_6             = 0x00000000,     /* reg_misc_6 */
+    },
+};
+
+SECTION_CAR_RODATA
+static const struct car_pll_cfg fsi_hpll_cfgs[] = {
+    PLL_CFG(FSI_CAR_PLL_550mV_550MHz,
+            40 * MHz,       /* hz_in */
+            550 * MHz,      /* hz_out */
+            0x37,           /* n */
+            0x02,           /* m */
+            0x02,           /* p */
+            false,          /* en_sdm */
+            false,          /* en_ssc */
+            0x0000,         /* sdm_din */
+            0x0000,         /* sdm_ssc_min */
+            0x0000,         /* sdm_ssc_max */
+            0x0000,         /* sdm_ssc_step */
+            0x0000,         /* sscmax */
+            0x00,           /* sscinc */
+            0x00),          /* sscincintrv */
+    PLL_CFG(FSI_CAR_PLL_550mV_633MHz,
+            40 * MHz,       /* hz_in */
+            633 * MHz,      /* hz_out */
+            0x3F,           /* n */
+            0x02,           /* m */
+            0x02,           /* p */
+            false,          /* en_sdm */
+            false,          /* en_ssc */
+            0x0000,         /* sdm_din */
+            0x0000,         /* sdm_ssc_min */
+            0x0000,         /* sdm_ssc_max */
+            0x0000,         /* sdm_ssc_step */
+            0x0000,         /* sscmax */
+            0x00,           /* sscinc */
+            0x00),          /* sscincintrv */
+    PLL_CFG(FSI_CAR_PLL_600mV_780MHz,
+            40 * MHz,       /* hz_in */
+            780 * MHz,      /* hz_out */
+            0x4E,           /* n */
+            0x02,           /* m */
+            0x02,           /* p */
+            false,          /* en_sdm */
+            false,          /* en_ssc */
+            0x0000,         /* sdm_din */
+            0x0000,         /* sdm_ssc_min */
+            0x0000,         /* sdm_ssc_max */
+            0x0000,         /* sdm_ssc_step */
+            0x0000,         /* sscmax */
+            0x00,           /* sscinc */
+            0x00),          /* sscincintrv */
+    PLL_CFG(FSI_CAR_PLL_600mV_897MHz,
+            40 * MHz,       /* hz_in */
+            897 * MHz,      /* hz_out */
+            0x2C,           /* n */
+            0x02,           /* m */
+            0x01,           /* p */
+            false,          /* en_sdm */
+            false,          /* en_ssc */
+            0x0000,         /* sdm_din */
+            0x0000,         /* sdm_ssc_min */
+            0x0000,         /* sdm_ssc_max */
+            0x0000,         /* sdm_ssc_step */
+            0x0000,         /* sscmax */
+            0x00,           /* sscinc */
+            0x00),          /* sscincintrv */
+    PLL_CFG(FSI_CAR_PLL_670mV_1130MHz,
+            40 * MHz,       /* hz_in */
+            1130 * MHz,     /* hz_out */
+            0x38,           /* n */
+            0x02,           /* m */
+            0x01,           /* p */
+            false,          /* en_sdm */
+            false,          /* en_ssc */
+            0x0000,         /* sdm_din */
+            0x0000,         /* sdm_ssc_min */
+            0x0000,         /* sdm_ssc_max */
+            0x0000,         /* sdm_ssc_step */
+            0x0000,         /* sscmax */
+            0x00,           /* sscinc */
+            0x00),          /* sscincintrv */
+    PLL_CFG(FSI_CAR_PLL_670mV_1300MHz,
+            40 * MHz,       /* hz_in */
+            1300 * MHz,     /* hz_out */
+            0x41,           /* n */
+            0x02,           /* m */
+            0x01,           /* p */
+            false,          /* en_sdm */
+            false,          /* en_ssc */
+            0x0000,         /* sdm_din */
+            0x0000,         /* sdm_ssc_min */
+            0x0000,         /* sdm_ssc_max */
+            0x0000,         /* sdm_ssc_step */
+            0x0000,         /* sscmax */
+            0x00,           /* sscinc */
+            0x00),          /* sscincintrv */
+    PLL_CFG(FSI_CAR_PLL_850mV_1400MHz,
+            40 * MHz,       /* hz_in */
+            1400 * MHz,     /* hz_out */
+            0x46,           /* n */
+            0x02,           /* m */
+            0x01,           /* p */
+            false,          /* en_sdm */
+            false,          /* en_ssc */
+            0x0000,         /* sdm_din */
+            0x0000,         /* sdm_ssc_min */
+            0x0000,         /* sdm_ssc_max */
+            0x0000,         /* sdm_ssc_step */
+            0x0000,         /* sscmax */
+            0x00,           /* sscinc */
+            0x00),          /* sscincintrv */
+    PLL_CFG(FSI_CAR_PLL_850mV_1610MHz,
+            40 * MHz,       /* hz_in */
+            1610 * MHz,     /* hz_out */
+            0x50,           /* n */
+            0x02,           /* m */
+            0x01,           /* p */
+            false,          /* en_sdm */
+            false,          /* en_ssc */
+            0x0000,         /* sdm_din */
+            0x0000,         /* sdm_ssc_min */
+            0x0000,         /* sdm_ssc_max */
+            0x0000,         /* sdm_ssc_step */
+            0x0000,         /* sscmax */
+            0x00,           /* sscinc */
+            0x00),          /* sscincintrv */
+};
+
+SECTION_CAR_RODATA
+static const struct car_pll_spec fsi_pll_spec = {
+    .type = CAR_PLL_TYPE_HPLL16,
+    .flags = CAR_PLL_FLG_HAS_DYNAMIC_RAMP,
+    .frac_width = 16,
+    .min_n = 1,
+    .min_m = 2,
+    .min_p = 1,
+    .clkin_max = 40 * MHz,
+    .vco_min = 650 * MHz,
+    .vco_max = 2000 * MHz,
+    .cf_min = 38400 * kHz,
+    .cf_max = 38400 * kHz,
+    .max_n = 255,
+    .max_m = 2,
+    .max_p = 2,
+};
+
+SECTION_CAR_DATA
+static const struct car_pll_spec *fsi_pll_spec_p = &fsi_pll_spec;
+static const struct car_pll_cfg *fsi_hpll_cfgs_p = fsi_hpll_cfgs;
+static uint32_t fsi_hpll_cfgs_n = ARRAY_SIZE(fsi_hpll_cfgs);
+static uint32_t fsi_hpll_status = 0;
+
+SECTION_CAR_RODATA
+static const struct car_pll_inf fsi_hpll_infs[] = {
+    HPLL_INF(0,
+             &fsi_pll_spec_p,           /* **spec */
+             &fsi_hpll_cfgs_p,          /* **cfgs */
+             &fsi_hpll_cfgs_n,          /* *cfgs_n */
+             &fsi_hpll_status,          /* *sts */
+             CLK_RST_CONTROLLER_FSI_CPU_BASE_0_0, /* sel_reg */
+             CLK_RST_CONTROLLER_FSI_CPU_BASE_0_0_FSICPU_CLK_SRC_SEL_FIELD, /* sel_msk */
+             CLK_RST_CONTROLLER_PLLFSI_MISC_0_0, /* rst_reg */
+             CLK_RST_CONTROLLER_PLLFSI_MISC_0_0_PLLFSI_RESETB_FIELD, /* rst_msk */
+             CLK_RST_CONTROLLER_PLLFSI_BASE_0, /* en_reg */
+             CLK_RST_CONTROLLER_PLLFSI_BASE_0_PLLFSI_ENABLE_FIELD, /* en_msk */
+             CLK_RST_CONTROLLER_PLLFSI_MISC_1_0, /* iddq_reg */
+             CLK_RST_CONTROLLER_PLLFSI_MISC_1_0_PLLFSI_IDDQ_FIELD, /* iddq_msk */
+             CLK_RST_CONTROLLER_PLLFSI_BASE_0, /* mdiv_reg */
+             CLK_RST_CONTROLLER_PLLFSI_BASE_0_PLLFSI_DIVM_FIELD, /* mdiv_msk */
+             CLK_RST_CONTROLLER_PLLFSI_MISC_1_0, /* ndiv_reg */
+             CLK_RST_CONTROLLER_PLLFSI_MISC_1_0_PLLFSI_DIVN_FIELD, /* ndiv_msk */
+             CLK_RST_CONTROLLER_PLLFSI_BASE_0, /* pdiv_reg */
+             CLK_RST_CONTROLLER_PLLFSI_BASE_0_PLLFSI_DIVP_FIELD, /* pdiv_msk */
+             CLK_RST_CONTROLLER_PLLFSI_MISC_1_0, /* frac_reg */
+             CLK_RST_CONTROLLER_PLLFSI_MISC_1_0_PLLFSI_DIVN_FRAC_FIELD, /* frac_msk */
+             0, /* enfrac_reg */
+             0, /* enfrac_msk */
+             CLK_RST_CONTROLLER_PLLFSI_MISC_4_0, /* fracstep_reg */
+             CLK_RST_CONTROLLER_PLLFSI_MISC_4_0_PLLFSI_FRAC_STEP_FIELD, /* fracstep_msk */
+             0, /* iref_reg */
+             0, /* iref_msk */
+             CLK_RST_CONTROLLER_PLLFSI_BASE_0, /* lock_reg */
+             CLK_RST_CONTROLLER_PLLFSI_BASE_0_PLLFSI_LOCK_FIELD, /* lock_msk */
+             0, /* lckdet_reg */
+             0, /* lckdet_msk */
+             CLK_RST_CONTROLLER_PLLFSI_BASE_0_PLLFSI_FREQ_LOCK_FIELD, /* freqlock_msk */
+             0), /* ss_cntl_reg */
+};
+
+
+SECTION_CAR_TEXT
+bool fsi_pll_is_enabled()
+{
+    return fsi_hpll_infs[0].op->pll_is_enabled(&fsi_hpll_infs[0]);
+}
+
+SECTION_CAR_TEXT
+error_t fsi_pll_enable()
+{
+    return fsi_hpll_infs[0].op->pll_enable(&fsi_hpll_infs[0]);
+}
+
+SECTION_CAR_TEXT
+error_t fsi_pll_disable()
+{
+    return fsi_hpll_infs[0].op->pll_disable(&fsi_hpll_infs[0]);
+}
+
+SECTION_CAR_TEXT
+error_t fsi_pll_set_rate(int64_t hz_out)
+{
+    int64_t hz_in;
+    error_t ret;
+
+    ret = fsi_clk_get_rate(FSI_CLK_ID_XTAL, &hz_in);
+    if (ret == E_SUCCESS) {
+        ret = fsi_hpll_infs[0].op->pll_hz_set(&fsi_hpll_infs[0], hz_in, hz_out);
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t fsi_pll_get_rate(int64_t *hz_out)
+{
+    int64_t hz_in;
+    error_t ret;
+
+    ret = fsi_clk_get_rate(FSI_CLK_ID_XTAL, &hz_in);
+    if (ret == E_SUCCESS) {
+        *hz_out = fsi_hpll_infs[0].op->pll_hz_get(&fsi_hpll_infs[0], hz_in);
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t fsi_pll_spec_get(struct car_pll_spec *spec)
+{
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (spec != NULL) {
+        memcpy(spec, *fsi_hpll_infs[0].spec, sizeof(*spec));
+        ret = E_SUCCESS;
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t fsi_pll_spec_set(struct car_pll_spec *spec)
+{
+    if (spec == NULL) {
+        fsi_pll_spec_p = &fsi_pll_spec;
+    } else {
+        fsi_pll_spec_p = spec;
+    }
+    return E_SUCCESS;
+}
+
+SECTION_CAR_TEXT
+error_t fsi_pll_cfgs_set(struct car_pll_cfg *cfgs, uint32_t cfgs_n)
+{
+    if (cfgs == NULL) {
+        fsi_hpll_cfgs_p = fsi_hpll_cfgs;
+        fsi_hpll_cfgs_n = ARRAY_SIZE(fsi_hpll_cfgs);
+    } else {
+        fsi_hpll_cfgs_p = cfgs;
+        fsi_hpll_cfgs_n = cfgs_n;
+    }
+    return E_SUCCESS;
+}
+
+SECTION_CAR_TEXT
+error_t fsi_pll_init_cfg_rd(struct fsi_pll_init_cfg *cfg)
+{
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (cfg != NULL) {
+        cfg->reg_misc_6 = car_reg_rd(CLK_RST_CONTROLLER_PLLFSI_MISC_6_0);
+        cfg->reg_misc_5 = car_reg_rd(CLK_RST_CONTROLLER_PLLFSI_MISC_5_0);
+        cfg->reg_misc_4 = car_reg_rd(CLK_RST_CONTROLLER_PLLFSI_MISC_4_0);
+        cfg->reg_misc_3 = car_reg_rd(CLK_RST_CONTROLLER_PLLFSI_MISC_3_0);
+        cfg->reg_misc_2 = car_reg_rd(CLK_RST_CONTROLLER_PLLFSI_MISC_2_0);
+        cfg->divm = (uint8_t)car_reg_rd_val(fsi_hpll_infs[0].mdiv_reg,
+                                            fsi_hpll_infs[0].mdiv_msk);
+        cfg->divn = (uint8_t)car_reg_rd_val(fsi_hpll_infs[0].ndiv_reg,
+                                            fsi_hpll_infs[0].ndiv_msk);
+        cfg->divp = (uint8_t)car_reg_rd_val(fsi_hpll_infs[0].pdiv_reg,
+                                            fsi_hpll_infs[0].pdiv_msk);
+        cfg->divn_frac = (uint16_t)car_reg_rd_val(fsi_hpll_infs[0].frac_reg,
+                                                  fsi_hpll_infs[0].frac_msk);
+        cfg->frac_step = (uint16_t)car_reg_rd_val(fsi_hpll_infs[0].fracstep_reg,
+                                                  fsi_hpll_infs[0].fracstep_msk);
+        ret = fsi_pll_get_rate(&cfg->hz);
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t fsi_pll_init_cfg_wr(struct fsi_pll_init_cfg *cfg)
+{
+    error_t ret = E_CAR_NULL_PTR;
+
+    if (cfg != NULL) {
+        /* disable PLL */
+        ret = fsi_pll_disable();
+        if (ret == E_SUCCESS) {
+            /* PLL programming */
+            car_reg_wr(CLK_RST_CONTROLLER_PLLFSI_MISC_6_0,
+                       cfg->reg_misc_6);
+            car_reg_wr(CLK_RST_CONTROLLER_PLLFSI_MISC_5_0,
+                       cfg->reg_misc_5);
+            car_reg_wr(CLK_RST_CONTROLLER_PLLFSI_MISC_4_0,
+                       cfg->reg_misc_4);
+            car_reg_wr(CLK_RST_CONTROLLER_PLLFSI_MISC_3_0,
+                       cfg->reg_misc_3);
+            car_reg_wr(CLK_RST_CONTROLLER_PLLFSI_MISC_2_0,
+                       cfg->reg_misc_2);
+            if (fsi_hpll_infs[0].mdiv_msk != 0U) {
+                car_reg_rdwr_val(fsi_hpll_infs[0].mdiv_reg,
+                                 fsi_hpll_infs[0].mdiv_msk,
+                                 cfg->divm);
+            }
+            if (fsi_hpll_infs[0].ndiv_msk != 0U) {
+                car_reg_rdwr_val(fsi_hpll_infs[0].ndiv_reg,
+                                 fsi_hpll_infs[0].ndiv_msk,
+                                 cfg->divn);
+            }
+            if (fsi_hpll_infs[0].pdiv_msk != 0U) {
+                car_reg_rdwr_val(fsi_hpll_infs[0].pdiv_reg,
+                                 fsi_hpll_infs[0].pdiv_msk,
+                                 cfg->divp);
+            }
+            if (fsi_hpll_infs[0].frac_msk != 0U) {
+                car_reg_rdwr_val(fsi_hpll_infs[0].frac_reg,
+                                 fsi_hpll_infs[0].frac_msk,
+                                 cfg->divn_frac);
+            }
+            /* flag the PLL is initialized */
+            fsi_hpll_status |= CAR_PLL_STS_HZ_SET;
+            /* enable PLL */
+            ret = fsi_pll_enable();
+        }
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t fsi_pll_init(uint32_t pll_vf)
+{
+    error_t ret = E_CAR_PLL_NO_INIT;
+
+    if (pll_vf < ARRAY_SIZE(fsi_pll_init_cfgs)) {
+        ret = fsi_pll_init_cfg_wr((struct fsi_pll_init_cfg *)&fsi_pll_init_cfgs[pll_vf]);
+    }
+    return ret;
+}
+
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/fsi/fsi-car-rst.c b/spe-freertos-bsp/fsp/source/soc/t234/port/fsi/fsi-car-rst.c
new file mode 100644
index 0000000..c4b87d3
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/fsi/fsi-car-rst.c
@@ -0,0 +1,237 @@
+/* Copyright (c) 2020-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stddef.h>                     // for NULL
+#include <stdbool.h>                    // for bool, false
+#include <stdint.h>                     // for uint32_t, uint8_t, UINT8_MAX, UIN...
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>             // for CT_ASSERT
+#include <soc-common/hw-const.h>        /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <arclk_rst.h>                  // for CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0...
+
+/* Late FSP headers */
+#include <misc/macros.h>                // for ARRAY_SIZE,...
+#include <chipid/chip-id.h>             // for tegra_platform_is_silicon...
+#include <delay/delay.h>                // for udelay...
+
+/* Module-specific FSP headers */
+#include <car/car-sections.h>           // for SECTION_CAR_TEXT, ...
+#include <car/car-errors.h>             // for E_CAR_INVALID_RESET_ID,_...
+#include <car/car-rst.h>                // for core functions, ...
+#include <port/car-port.h>              // for car_port_udelay...
+#include <port/car-rst.h>               // for reset index, ...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__MACROS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CHIPID__CHIP_ID_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__DELAY__DELAY_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__CAR__CAR_RST_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__FSI__CAR_RST_H, "Header file missing or invalid.")
+
+
+SECTION_CAR_RODATA
+static const struct car_rst_inf fsi_rst_infs[] = {
+    /* fsi_ncorereset0_reset_fsi_cpu_clk_srstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_NCORE_0,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0_SWR_FSI_NCORERESET0_RST_FIELD),
+    /* fsi_ncorereset1_reset_fsi_cpu_clk_srstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_NCORE_1,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0_SWR_FSI_NCORERESET1_RST_FIELD),
+    /* fsi_ncorereset2_reset_fsi_cpu_clk_srstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_NCORE_2,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0_SWR_FSI_NCORERESET2_RST_FIELD),
+    /* fsi_ncorereset3_reset_fsi_cpu_clk_srstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_NCORE_3,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0_SWR_FSI_NCORERESET3_RST_FIELD),
+    /* fsi_ncpuporreset0_reset_fsi_cpu_clk_srstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_NCPUPOR_0,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0_SWR_FSI_NCPUPORRESET0_RST_FIELD),
+    /* fsi_ncpuporreset1_reset_fsi_cpu_clk_srstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_NCPUPOR_1,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0_SWR_FSI_NCPUPORRESET1_RST_FIELD),
+    /* fsi_ncpuporreset2_reset_fsi_cpu_clk_srstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_NCPUPOR_2,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0_SWR_FSI_NCPUPORRESET2_RST_FIELD),
+    /* fsi_ncpuporreset3_reset_fsi_cpu_clk_srstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_NCPUPOR_3,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0_SWR_FSI_NCPUPORRESET3_RST_FIELD),
+    /* fsi_ntopreset_reset_fsi_cpu_clk_srstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_NTOPRESET,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0_SWR_FSI_NTOPRESET_RST_FIELD),
+    /* fsi_npresetdbg_reset_fsi_cpu_clk_srstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_NPRESETDBG,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CPU_0_SWR_FSI_NPRESETDBG_RST_FIELD),
+    /* fsi_chsm_sysporreset_reset_fsi_chsm_cpu_clk_srstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_CHSM_SYSPORRESET,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CHSM_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CHSM_0_SWR_CHSM_SYSPORESET_RST_FIELD),
+    /* fsi_chsm_nreset_reset_fsi_chsm_cpu_clk_srstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_CHSM_NRESET,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CHSM_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CHSM_0_SWR_CHSM_NRESET_RST_FIELD),
+    /* fsi_chsm_dbgresetn_reset_fsi_chsm_cpu_clk_srstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_CHSM_DBGRESETN,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CHSM_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CHSM_0_SWR_CHSM_DBGRESETN_RST_FIELD),
+    /* fsi_chsm_presetdbgn_reset_fsi_chsm_cpu_clk_srstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_CHSM_PRESETDBGN,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CHSM_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CHSM_0_SWR_CHSM_PRESETDBGN_RST_FIELD),
+    /* fsi_csite_reset_rstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_CSITE,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_DFD_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_DFD_0_SWR_FSI_CSITE_RST_FIELD),
+    /* fsi_la_reset_rstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_LA,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_DFD_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_DFD_0_SWR_FSI_LA_RST_FIELD),
+    /* fsi_can0_reset_rstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_CAN0,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CAN_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CAN_0_SWR_FSI_CAN0_RST_FIELD),
+    /* fsi_can1_reset_rstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_CAN1,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CAN_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_CAN_0_SWR_FSI_CAN1_RST_FIELD),
+    /* fsi_spi0_reset_rstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_SPI0,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_SPI_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_SPI_0_SWR_FSI_SPI0_RST_FIELD),
+    /* fsi_uart0_reset_rstn */
+    CAR_RST_TYPE_R(FSI_CAR_RST_ID_UART0,
+                   0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_UART_0,
+                   CLK_RST_CONTROLLER_RST_DEV_FSI_UART_0_SWR_FSI_UART0_RST_FIELD),
+};
+
+
+SECTION_CAR_TEXT
+static struct car_rst_inf *rst_inf_get(uint32_t rst_id)
+{
+    struct car_rst_inf *rst = NULL;
+
+    if ((rst_id < ARRAY_SIZE(fsi_rst_infs)) && (fsi_rst_infs[rst_id].op != NULL)) {
+        rst = (struct car_rst_inf *)&fsi_rst_infs[rst_id];
+    }
+    return rst;
+}
+
+SECTION_CAR_TEXT
+bool fsi_rst_is_asserted(uint32_t rst_id)
+{
+    bool ret = false;
+    struct car_rst_inf *rst = rst_inf_get(rst_id);
+
+    if (rst != NULL) {
+        ret = rst->op->rst_is_asserted(rst);
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t fsi_rst_assert(uint32_t rst_id)
+{
+    error_t ret = E_CAR_INVALID_RESET_ID;
+    struct car_rst_inf *rst = rst_inf_get(rst_id);
+
+    if (rst != NULL) {
+        ret = rst->op->rst_assert(rst);
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t fsi_rst_deassert(uint32_t rst_id)
+{
+    error_t ret = E_CAR_INVALID_RESET_ID;
+    struct car_rst_inf *rst = rst_inf_get(rst_id);
+
+    if (rst != NULL) {
+        ret = rst->op->rst_deassert(rst);
+    }
+    return ret;
+}
+
+SECTION_CAR_TEXT
+error_t fsi_rst_pulse(uint32_t rst_id, uint64_t delay_us)
+{
+    error_t ret = E_CAR_INVALID_RESET_ID;
+    struct car_rst_inf *rst = rst_inf_get(rst_id);
+
+    if (rst != NULL) {
+        ret = rst->op->rst_assert(rst);
+        car_port_udelay(delay_us);
+        ret |= rst->op->rst_deassert(rst);
+    }
+    return ret;
+}
+
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/rce/gpcdma-port.c b/spe-freertos-bsp/fsp/source/soc/t234/port/rce/gpcdma-port.c
new file mode 100644
index 0000000..917dbaa
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/rce/gpcdma-port.c
@@ -0,0 +1,206 @@
+/*
+ * Copyright (c) 2020-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>                   // for uint32_t, uint8_t, UINT32_...
+#include <stddef.h>                   // for NULL
+#include <stdbool.h>                  // for bool
+                                      // IWYU pragma: no_include <errno.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>           // for CT_ASSERT
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <osa/rtos-task.h>            // for rtosTaskYieldFromISR
+#include <osa/rtos-semaphore.h>       // for rtosSemaphore...
+#include <osa/rtos-values.h>          // for rtosBool
+#include <misc/attributes.h>          // for ALIGN
+#include <error/common-errors.h>      // for error_t, E_SUCCESS
+#include <clk/clk-tegra.h>            // for tegra_clk_reset_pulse
+
+/* Module specific headers */
+#include <gpcdma/gpcdma-errors.h>     // for E_GPCDMA_NULL_PTR, E_GPCDMA_...
+#include <gpcdma/gpcdma-priv.h>       // for struct gpcdma_id, gpcdma_channel...
+#include <gpcdma/gpcdma-port.h>       // for gpcdma_port_...
+#include <port/gpcdma-port-priv.h>    // Immune from CT_ASSERT protection
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/macros.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+CT_ASSERT(FSP__OSA__RTOS_TASK_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_SEMAPHORE_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__OSA__RTOS_VALUES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPCDMA__GPCDMA_ERRORS_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPCDMA__GPCDMA_PRIV_H, "Header file missing or invalid.")
+CT_ASSERT(FSP__GPCDMA__GPCDMA_PORT_H, "Header file missing or invalid.")
+
+static rtosSemaphoreHandle  chan_sems[TEGRA_GPCDMA_NUM_CHANNELS];
+static uint8_t              chan_sem_bufs[TEGRA_GPCDMA_NUM_CHANNELS][rtosSemaphoreSize()];
+
+/* Queue management used in continuous mode to store buffer descriptor */
+error_t gpcdma_port_init_queue(uint32_t chan_num, uint32_t nelems,
+                               uint32_t el_sz)
+{
+    UNUSED(chan_num);
+    UNUSED(nelems);
+    UNUSED(el_sz);
+    return E_NOTSUPPORTED;
+}
+
+void gpcdma_port_delete_queue(uint32_t chan_num)
+{
+    UNUSED(chan_num);
+}
+
+error_t gpcdma_port_get_desc(uint32_t chan_num, void *ptr, uint32_t timeout,
+                             bool from_isr)
+{
+    UNUSED(chan_num);
+    UNUSED(ptr);
+    UNUSED(timeout);
+    UNUSED(from_isr);
+    return E_NOTSUPPORTED;
+}
+
+error_t gpcdma_port_send_desc_to_back(uint32_t chan_num, void *ptr,
+                                      uint32_t timeout, bool from_isr)
+{
+    UNUSED(chan_num);
+    UNUSED(ptr);
+    UNUSED(timeout);
+    UNUSED(from_isr);
+    return E_NOTSUPPORTED;
+}
+/* End of queue management code */
+
+static inline bool is_dma_chan_valid(uint32_t chan_num)
+{
+    return chan_num < (uint32_t)TEGRA_GPCDMA_NUM_CHANNELS;
+}
+
+error_t gpcdma_port_chan_sync(uint32_t chan_num,
+                              uint32_t timeout)
+{
+    error_t ret;
+
+    if (!is_dma_chan_valid(chan_num)) {
+        ret = E_GPCDMA_INVALID_PARAM;
+        goto out;
+    }
+
+    ret = rtosSemaphoreAcquire(chan_sems[chan_num], (rtosTick)timeout);
+    if (ret != rtosPASS) {
+        ret = E_GPCDMA_PORT_SYNC_TIMEOUT;
+        goto out;
+    }
+    ret = E_SUCCESS;
+
+out:
+    return ret;
+}
+
+error_t gpcdma_port_chan_sync_end(uint32_t chan_num)
+{
+    error_t ret;
+    rtosBool higher_prio_task_woken = rtosFALSE;
+
+    if (!is_dma_chan_valid(chan_num)) {
+        ret = E_GPCDMA_INVALID_PARAM;
+        goto out;
+    }
+
+    ret = rtosSemaphoreReleaseFromISR(chan_sems[chan_num],
+                                      &higher_prio_task_woken);
+    if (ret == rtosPASS) {
+        rtosTaskYieldFromISR(higher_prio_task_woken);
+        ret = E_SUCCESS;
+    }
+
+out:
+    return ret;
+}
+
+error_t gpcdma_port_chan_setup(uint32_t chan_num)
+{
+    error_t ret;
+    rtosUCount depth;
+
+    if (!is_dma_chan_valid(chan_num)) {
+        ret = E_GPCDMA_INVALID_PARAM;
+        goto out;
+    }
+
+    ret = rtosSemaphoreCreateBinary(chan_sem_bufs[chan_num],
+                                    &chan_sems[chan_num]);
+    if (ret != rtosPASS) {
+        ret = E_GPCDMA_PORT_CHAN_SETUP_FAIL;
+        goto out;
+    }
+
+    ret = rtosSemaphoreGetCountDepth(chan_sems[chan_num], &depth);
+    if (ret != rtosPASS) {
+        ret = E_GPCDMA_PORT_CHAN_SETUP_FAIL;
+        goto out;
+    }
+
+    if (depth == 0U) {
+        ret = E_SUCCESS;
+        goto out;
+    }
+
+    /*
+     * Make sure the semaphore state is empty initially so that it
+     * blocks on a notification from ISR.
+     */
+    ret = rtosSemaphoreAcquire(chan_sems[chan_num], (rtosTick)0);
+    if (ret != rtosPASS) {
+        ret = E_GPCDMA_PORT_CHAN_SETUP_FAIL;
+        goto out;
+    }
+    ret = E_SUCCESS;
+
+out:
+    return ret;
+}
+
+error_t gpcdma_port_init(struct gpcdma_id *id)
+{
+    return E_SUCCESS;
+}
diff --git a/spe-freertos-bsp/fsp/source/soc/t234/port/rce/tke-irq.S b/spe-freertos-bsp/fsp/source/soc/t234/port/rce/tke-irq.S
new file mode 100644
index 0000000..aa4de9f
--- /dev/null
+++ b/spe-freertos-bsp/fsp/source/soc/t234/port/rce/tke-irq.S
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2018-2020 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <hw-config/vic-irqs.h>		// defined by the application, defines the interrupt map
+#include <vic/vic-asm.h>
+
+/* Module-specific FSP headers */
+#include <tke/sections-tke.h>
+
+	.section	SECTION_STR_TKE_TEXT, "ax"
+	.arm
+	.syntax		unified
+
+	/*
+	 * TKE interrupt handlers
+	 */
+	isr_addr TIMER0_isr, tegra_tke_id_timer0, tegra_tke_irq, INTERRUPT_TIMER0
+	isr_addr TIMER1_isr, tegra_tke_id_timer1, tegra_tke_irq, INTERRUPT_TIMER1
+	isr_addr TIMER2_isr, tegra_tke_id_timer2, tegra_tke_irq, INTERRUPT_TIMER2
+	isr_addr TIMER3_isr, tegra_tke_id_timer3, tegra_tke_irq, INTERRUPT_TIMER3
+
+	/*
+	 * Defines the portion of the ISR map array for TKE
+	 */
+	.section	SECTION_STR_VIC_ISRMAP_DATA, "a"
+
+	isr_map_entry	INTERRUPT_TIMER0, TIMER0_isr
+	isr_map_entry	INTERRUPT_TIMER1, TIMER1_isr
+	isr_map_entry	INTERRUPT_TIMER2, TIMER2_isr
+	isr_map_entry	INTERRUPT_TIMER3, TIMER3_isr
+
+	.end
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/FreeRTOSConfig.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/FreeRTOSConfig.h
new file mode 100644
index 0000000..e8598da
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/FreeRTOSConfig.h
@@ -0,0 +1,105 @@
+/* Copyright (c) 2015-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+#include <artimer.h>
+
+#define FSP__CONFIG__FREERTOSCONFIG_H			1
+#define configUSE_PREEMPTION				1
+#define configUSE_PORT_OPTIMISED_TASK_SELECTION		0
+#define configUSE_TICKLESS_IDLE				0
+#define configCPU_CLOCK_HZ				1000000
+#define configTICK_RATE_HZ				1000
+#define configMAX_PRIORITIES				32
+#define configMINIMAL_STACK_SIZE			128
+#define configMAX_TASK_NAME_LEN				16
+#define configUSE_16_BIT_TICKS				0
+#define configIDLE_SHOULD_YIELD				1
+#define configUSE_MUTEXES				1
+#define configUSE_RECURSIVE_MUTEXES			1
+#define configUSE_COUNTING_SEMAPHORES			1
+#define configUSE_ALTERNATIVE_API			0 /* Deprecated! */
+#define configQUEUE_REGISTRY_SIZE			10
+#define configUSE_QUEUE_SETS				0
+#define configUSE_TIME_SLICING				0
+#define configUSE_NEWLIB_REENTRANT			1
+#define configENABLE_BACKWARD_COMPATIBILITY		0
+
+/* Hook function related definitions. */
+#define configUSE_IDLE_HOOK				0
+#define configUSE_TICK_HOOK				0
+#define configCHECK_FOR_STACK_OVERFLOW			1
+#define configUSE_MALLOC_FAILED_HOOK			0
+
+/* Run time and task stats gathering related definitions. */
+#define configGENERATE_RUN_TIME_STATS			0
+#define configUSE_TRACE_FACILITY			0
+#define configUSE_STATS_FORMATTING_FUNCTIONS		0
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES				0
+#define configMAX_CO_ROUTINE_PRIORITIES			0
+
+/* Software timer related definitions. */
+#define configUSE_TIMERS				1
+#define configTIMER_TASK_PRIORITY			(configMAX_PRIORITIES - 1)
+#define configTIMER_QUEUE_LENGTH			10
+#define configTIMER_TASK_STACK_DEPTH			configMINIMAL_STACK_SIZE
+#define configSUPPORT_STATIC_ALLOCATION			1
+
+#define configASSERT( x ) if( ( x ) == pdFALSE ) { taskDISABLE_INTERRUPTS(); for( ;; ); }
+
+/* Set the following definitions to 1 to include the API function, or zero to exclude the API function. */
+#define INCLUDE_vTaskPrioritySet			1
+#define INCLUDE_uxTaskPriorityGet			1
+#define INCLUDE_vTaskDelete				1
+#define INCLUDE_vTaskSuspend				1
+#define INCLUDE_xTaskResumeFromISR			1
+#define INCLUDE_vTaskDelayUntil				1
+#define INCLUDE_vTaskDelay				1
+#define INCLUDE_xTaskGetSchedulerState			1
+#define INCLUDE_xTaskGetCurrentTaskHandle		1
+#define INCLUDE_uxTaskGetStackHighWaterMark		0
+#define INCLUDE_xTaskGetIdleTaskHandle			0
+#define INCLUDE_xTimerGetTimerDaemonTaskHandle		0
+#define INCLUDE_pcTaskGetTaskName			0
+#define INCLUDE_eTaskGetState				0
+#define INCLUDE_xEventGroupSetBitFromISR		1
+#define INCLUDE_xTimerPendFunctionCall			1
+
+#ifndef __ASSEMBLER__
+extern void setup_timer_interrupt(void);
+#define configSETUP_TICK_INTERRUPT() setup_timer_interrupt()
+
+#endif
+
+#define configCLEAR_TICK_INTERRUPT
+#define configACKNOWLEDGE_TICK_INTERRUPT
+
+#endif /* FREERTOS_CONFIG_H */
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/Makefile b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/Makefile
new file mode 100644
index 0000000..b8eb064
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/Makefile
@@ -0,0 +1,358 @@
+# Copyright (c) 2016-2023, NVIDIA CORPORATION. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#  * Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+#  * Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+#  * Neither the name of NVIDIA CORPORATION nor the names of its
+#    contributors may be used to endorse or promote products derived
+#    from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+# Macro for checking that each variable given in list $(1) is both defined
+# and has a non empty value in it.
+define NV_BUILD_VARIABLES_SANITY_CHECK
+$(foreach var,$(1),$(eval \
+  ifndef $(var)
+    _missing_vars := 1 $$(info ERROR: variable not set or empty: $(var))
+  endif)) \
+  $(if $(_missing_vars),$(error Environment sanity check failed))
+endef
+$(call NV_BUILD_VARIABLES_SANITY_CHECK,SPE_FREERTOS_BSP \
+	CROSS_COMPILE)
+
+RT_AUX_DIR ?= $(SPE_FREERTOS_BSP)/rt-aux-cpu-demo-fsp
+FREERTOS_DIR ?= $(SPE_FREERTOS_BSP)/FreeRTOSV10.4.3/FreeRTOS/Source
+FSP_SRC_DIR ?= $(SPE_FREERTOS_BSP)/fsp/source
+OUTDIR := $(RT_AUX_DIR)/out
+SOC_PATH := $(RT_AUX_DIR)/soc
+DOC_PATH := $(RT_AUX_DIR)/doc
+DOC_BUILD_PATH := $(OUTDIR)/docs
+CC := $(CROSS_COMPILE)gcc
+OBJCOPY := $(CROSS_COMPILE)objcopy
+OBJDUMP := $(CROSS_COMPILE)objdump
+
+ALL_BUILD_TARGETS := bin_t23x docs
+ALL_CLEAN_TARGETS := clean_t23x clean_docs
+
+# This must be the first rule
+.PHONY: all
+all: $(ALL_BUILD_TARGETS)
+
+hide := @
+show := @test '${hide}' != @ || echo '   '
+
+show_compile = ${show} CC ${notdir $<}
+define cmd_compile
+	$(CC) -c $(CFLAGS) -MD -MP -MF $(_tgt_depname) $< -o $@
+endef
+
+show_ldscript_cpp = ${show} CPP ${notdir $<}
+define cmd_ldscript_cpp
+	$(CC) -E $(CPPFLAGS) -MD -MP -MF $(_tgt_depname) -MT $@ -P -D __ASSEMBLY__ \
+		-x assembler-with-cpp $< -o $@
+endef
+
+show_link = ${show} LINK ${notdir $@}
+define cmd_link
+	$(CC) $(LDFLAGS) -nostartfiles \
+		-Xlinker -M -Xlinker -Map=$(patsubst %.elf,%.map,$@) \
+		-Xlinker --gc-sections \
+		-Xlinker -e_stext \
+		$(filter-out FORCE %.ld,$^) \
+		-T $(filter %.ld,$^) \
+		-o $@ -lc
+endef
+
+show_elf2bin = ${show} OBJCOPY ${notdir $@}
+define cmd_elf2bin
+	$(OBJCOPY) -O binary $< $@
+endef
+
+show_disassemble = ${show} DISASM ${notdir $@}
+define cmd_disassemble
+	$(OBJDUMP) -d $< > $@
+endef
+
+# This gives false-positives if x$1x appears multiple times in x$2x. However,
+# since we use this to compare command-lines, the chance of that happening is
+# remote, so we ignore this issue.
+cmds_differ = $(subst x$(strip $1)x,,x$(strip $2)x)
+
+need_rebuild = $$(filter-out FORCE,$$?)$$(call cmds_differ,$$(cmd_$2),$$(_tgt_cmd_$1))
+
+.PHONY: FORCE
+FORCE: | $(OBJDIR)
+
+# The echo _tgt_cmd_... command below and/or the parsing of $(_depname) by
+# make later will fail if $(cmd_$2) contains characters that are special to the
+# shell (echo) or make (parsing). This can be worked around by escaping the
+# data. However, a simpler suggestion is to keep $(cmd_*) simple, i.e "don't
+# do that".
+define gen_rule_body
+_depname := $1.d
+-include $$(_depname)
+
+$1: _tgt_depname := $$(_depname)
+$1: $3 FORCE
+	@set -e
+	@$$(if $(need_rebuild),rm -f $$(_tgt_depname))
+	@$$(if $(need_rebuild),$$(show_$2))
+	${hide}$$(if $(need_rebuild),$$(cmd_$2))
+	@$$(if $(need_rebuild),echo '_tgt_cmd_$$@ := $$(cmd_$2)' >> $$(_tgt_depname))
+endef
+
+gen_rule = $(eval $(gen_rule_body))
+
+define build_target
+
+SOC_TARGET := $(subst bin_,,$1)
+SPE_TARGET_DIR := $(SOC_PATH)/$(SOC_TARGET)
+include $(SPE_TARGET_DIR)/target_specific.mk
+
+OBJDIR := $(OUTDIR)/$(SOC_TARGET)
+ELF := $(OBJDIR)/spe.elf
+BIN := $(OBJDIR)/spe.bin
+DIS := $(OBJDIR)/spe.dis
+LDSCRIPT := $(OBJDIR)/spe.ld
+
+INCLUDES := \
+	. \
+	./include \
+	$(TARGET_INCLUDES) \
+	$(FSP_SRC_DIR)/include/ \
+	$(FSP_SRC_DIR)/include/osa/ \
+	$(FSP_SRC_DIR)/include/osa/freertosv10/ \
+	$(FSP_SRC_DIR)/include/osa/freertosv10/arm/armv7/cortex-r5/ \
+	$(FSP_SRC_DIR)/include/cpu/arm/armv7/cortex-r5/ \
+	$(FSP_SRC_DIR)/include/cpu/arm/common/ \
+	$(FSP_SRC_DIR)/include/cpu/arm/armv7/ \
+	$(FSP_SRC_DIR)/include/cpu/arm/armv7/cpu \
+	$(FREERTOS_DIR)/include \
+	$(FREERTOS_DIR)/portable/GCC/ARM_R5
+
+CPPFLAGS := \
+	$(addprefix -I,$(abspath $(INCLUDES))) \
+
+CFLAGS := \
+	$(CPPFLAGS) \
+	$(TARGET_CFLAGS) \
+	-DTEGRA_UARTC_ENABLED \
+	-mcpu=cortex-r5 -mthumb-interwork \
+	-fdata-sections -ffunction-sections -mlong-calls -g3 \
+	-mfloat-abi=softfp -mfpu=vfpv3-d16 \
+	-Wall -std=c99 -pedantic \
+	-Wstrict-prototypes -Wmissing-prototypes \
+	-Werror -Wpointer-arith -Wno-unknown-pragmas \
+	-Wfloat-equal -Wshadow -Wbad-function-cast \
+	-Wwrite-strings -Waggregate-return -Wmissing-declarations \
+	-Wmissing-format-attribute -Wno-deprecated-declarations -Wpacked \
+	-Wredundant-decls -Wnested-externs -Wunreachable-code -Wno-variadic-macros \
+	-DUSE_GCC=1
+
+ifeq ($(ENABLE_GPCDMA_FUNC), 1)
+	CFLAGS += -DENABLE_GPCDMA_FUNC
+endif
+
+ifeq ($(ENABLE_GPIO_APP), 1)
+	CFLAGS += -DENABLE_GPIO_APP
+endif
+
+ifeq ($(ENABLE_TIMER_APP), 1)
+	CFLAGS += -DENABLE_TIMER_APP
+endif
+
+ifeq ($(ENABLE_AODMIC_APP), 1)
+	CFLAGS += -DENABLE_AODMIC_APP
+endif
+
+ifeq ($(ENABLE_I2C_APP), 1)
+	CFLAGS += -DENABLE_I2C_APP
+	CFLAGS += -DI2C_CUSTOM_PORT_INIT
+endif
+
+ifeq ($(ENABLE_GTE_APP), 1)
+	CFLAGS += -DENABLE_GTE_APP
+endif
+
+ifeq ($(ENABLE_SPI_APP), 1)
+	CFLAGS += -DENABLE_SPI_APP
+endif
+
+ifeq ($(ENABLE_SPI_SLV_APP), 1)
+	CFLAGS += -DENABLE_SPI_SLV_APP
+endif
+
+ifeq ($(ENABLE_SPE_FOR_ORIN_NANO), 1)
+	CFLAGS += -DENABLE_SPE_FOR_ORIN_NANO
+endif
+
+LDFLAGS := \
+	$(CFLAGS)
+
+SRCS := \
+	$(TARGET_SRCS) \
+	$(FSP_SRC_DIR)/drivers/cpu/arm/armv7/armv7-exceptions.S \
+	$(FSP_SRC_DIR)/drivers/cpu/arm/common/irqapi-arm.c \
+	$(FSP_SRC_DIR)/drivers/cpu/arm/common/arm-vic.c \
+	$(FSP_SRC_DIR)/drivers/vic/irqapi-vic.c \
+	$(FSP_SRC_DIR)/drivers/cpu/arm/armv7/cortex-r5/irqapi-cortex-r5.c \
+	$(FSP_SRC_DIR)/drivers/cpu/arm/armv7/cortex-r5/cache-cortex-r5.c \
+	$(FSP_SRC_DIR)/drivers/cpu/arm/armv7/armv7-exception.c \
+	$(FSP_SRC_DIR)/drivers/tke/tke-tegra.c \
+	$(FSP_SRC_DIR)/drivers/tke/tke-tegra-tsc-fixed.c \
+	$(FSP_SRC_DIR)/drivers/tke/tke-tegra-udelay.c \
+	$(FSP_SRC_DIR)/drivers/hsp/hsp-tegra.c  \
+	$(FSP_SRC_DIR)/drivers/debug/abort.c \
+	$(FSP_SRC_DIR)/drivers/ast/tegra-ast.c \
+	$(FSP_SRC_DIR)/drivers/chipid/chip-id.c \
+	$(FREERTOS_DIR)/portable/GCC/ARM_R5/portASM.S \
+	$(FREERTOS_DIR)/list.c \
+	$(FREERTOS_DIR)/portable/MemMang/heap_3.c \
+	$(FREERTOS_DIR)/portable/GCC/ARM_R5/port.c \
+	$(FREERTOS_DIR)/queue.c \
+	$(FREERTOS_DIR)/tasks.c \
+	$(FREERTOS_DIR)/timers.c \
+	$(FREERTOS_DIR)/event_groups.c \
+	app/ivc-echo-task.c \
+	drivers/wake-tegra.c \
+	drivers/bpmp-ipc.c \
+	drivers/irq-handlers.S \
+	drivers/ivc-channels.c \
+	drivers/spe-vic.c \
+	drivers/spe-pm.c \
+	platform/tegra-ivc.c \
+	platform/debug_init.c \
+	platform/ivc-channel-ids.c \
+	platform/err-hook-printf.c \
+	platform/newlib-syscalls.c \
+	platform/print.c \
+	$(RT_AUX_DIR)/platform/tcu.c \
+	$(RT_AUX_DIR)/platform/uart-tegra.c \
+	main.c
+
+ifeq ($(ENABLE_GPCDMA_FUNC), 1)
+	SRCS += \
+		$(FSP_SRC_DIR)/drivers/gpcdma/gpcdma.c
+endif
+
+ifeq ($(ENABLE_GPIO_APP), 1)
+	SRCS += \
+		$(FSP_SRC_DIR)/drivers/gpio/tegra-gpio.c \
+		$(RT_AUX_DIR)/app/gpio-app.c
+endif
+
+ifeq ($(ENABLE_TIMER_APP), 1)
+	SRCS += \
+		$(RT_AUX_DIR)/app/timer-app.c
+endif
+
+ifeq ($(ENABLE_AODMIC_APP), 1)
+	SRCS += \
+		$(FSP_SRC_DIR)/drivers/aodmic/tegra-aodmic.c \
+		$(RT_AUX_DIR)/app/aodmic-app.c
+endif
+
+ifeq ($(ENABLE_I2C_APP), 1)
+	SRCS += \
+		$(FSP_SRC_DIR)/drivers/i2c/i2c-core.c \
+		$(FSP_SRC_DIR)/drivers/i2c/i2c-tegra.c \
+		$(RT_AUX_DIR)/drivers/i2c-port.c \
+		$(RT_AUX_DIR)/app/i2c-app.c \
+		$(SPE_TARGET_DIR)/src/i2c-app-priv.c
+endif
+
+ifeq ($(ENABLE_GTE_APP), 1)
+	SRCS += \
+		drivers/gte-tegra-ids.c \
+		drivers/gte-tegra.c \
+		$(RT_AUX_DIR)/app/gte-app.c
+endif
+
+ifeq ($(ENABLE_SPI_APP), 1)
+	SRCS += \
+		$(FSP_SRC_DIR)/drivers/spi-mst/spi.c \
+		$(RT_AUX_DIR)/app/spi-app.c
+endif
+
+ifeq ($(ENABLE_SPI_SLV_APP), 1)
+	SRCS += \
+		$(FSP_SRC_DIR)/drivers/spi-slv/spi-slave.c \
+		$(RT_AUX_DIR)/app/spi-slv-app.c
+endif
+
+objname = $(abspath $(addprefix $(OBJDIR)/,\
+	$(addsuffix .o,$(basename $(notdir $1)))))
+
+OBJS := $(call objname,$(SRCS))
+
+.PHONY: $1
+#
+# Set all target-specific variables here
+#
+$1: CFLAGS := $(CFLAGS)
+$1: OBJDIR := $(OBJDIR)
+$1: CPPFLAGS := $(CPPFLAGS)
+$1: LDFLAGS := $(LDFLAGS)
+
+$1: $(OBJDIR) $(BIN) $(ELF) $(DIS) $(LDSCRIPT)
+
+$(OBJDIR):
+	mkdir -p $(OBJDIR)
+
+$(foreach src,$(SRCS),$(call gen_rule,$(call objname,$(src)),compile,$(src)))
+
+$(call gen_rule,$(LDSCRIPT),ldscript_cpp,$(SPE_TARGET_DIR)/spe.ld.in)
+
+$(call gen_rule,$(ELF),link,$(OBJS) $(OBJDIR)/spe.ld,spe.map)
+
+$(call gen_rule,$(BIN),elf2bin,$(OBJDIR)/spe.elf)
+
+$(call gen_rule,$(DIS),disassemble,$(OBJDIR)/spe.elf)
+
+endef
+
+target_rules = $(eval $(value build_target))
+$(foreach target,$(filter-out docs, $(ALL_BUILD_TARGETS)),$(call target_rules,$(target)))
+
+$(DOC_BUILD_PATH):
+	mkdir -p $(DOC_BUILD_PATH)
+
+$(DOC_BUILD_PATH)/.stamp: $(DOC_PATH)/doxyfile | $(DOC_BUILD_PATH)
+	${show} DOXYGEN $<
+	${hide} export OUTDIR=$(OUTDIR) && doxygen $< 2>$(DOC_BUILD_PATH)/error_log.txt
+	${hide} touch $@
+
+.PHONY: docs
+docs: $(DOC_BUILD_PATH)/.stamp
+
+.PHONY: clean
+clean: $(ALL_CLEAN_TARGETS)
+
+define clean_target
+BUILD_DIR := $(subst clean_,,$(target))
+
+.PHONY: $(target)
+$(target): BUILD_DIR := $(BUILD_DIR)
+$(target):
+	${show} RMDIR $(BUILD_DIR)
+	${hide} rm -rf $(OUTDIR)/$(BUILD_DIR)
+endef
+
+$(foreach target,$(ALL_CLEAN_TARGETS),$(eval $(value clean_target)))
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/aodmic-app.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/aodmic-app.c
new file mode 100644
index 0000000..04b87be
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/aodmic-app.c
@@ -0,0 +1,245 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Creates one task that repeatedly reads AODMIC data using GPCDMA;
+ * prints zero crossing count and avg volume (mean square) periodically;
+ * triggers system wake if computed volume crosses a threshold
+ */
+
+/*
+ * NOTE: SPE should not enter its low power states while running this app
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <gpcdma/gpcdma.h>
+#include <processor/gpcdma-hw.h>
+#include <aodmic/tegra-aodmic.h>
+#include <processor/tegra-aodmic-hw.h>
+#include <wake-tegra.h>
+#include <wake-tegra-hw.h>
+#include <err-hook.h>
+
+#include "aodmic-app.h"
+
+#include <osa/rtos-task.h>
+
+#define TEST_AODMIC         tegra_aodmic_ctlr_aon
+
+/* GPCDMA channel - need to ensure that no other */
+/* application uses the same DMA channel         */
+#define AODMIC_DMA_CHANNEL  7
+
+/* Volume threshold for triggering system wake */
+#define SPE_CCPLEX_WAKE_THRESHOLD 1000000
+
+static void wake_trigger_ccplex_wake(void)
+{
+	tegra_wake_trigger_wake_event(&tegra_wake_id_wake);
+}
+
+static void aodmic_test_task(void *pvParameters)
+{
+	int status = 0, aodmic_opened = 0;
+	int i, buf_size, period_ms, num_channels;
+	(void)pvParameters; /* unused */
+	struct tegra_aodmic_config config;
+	char err_msg[100];
+	rtosTick start_time, end_time;
+	int j, zero_cross_l = 0, zero_cross_r = 0;
+	unsigned int vol_l = 0, vol_r = 0, temp_l, temp_r;
+	int16_t *buf = NULL;
+	int16_t prev_samp_l = 0, prev_samp_r = 0;
+	int16_t cur_samp_l, cur_samp_r;
+
+	/* AODMIC configuration (editable) */
+	config.sample_rate    = TEGRA_AODMIC_RATE_16KHZ;
+	config.channel_config = TEGRA_AODMIC_CHANNEL_STEREO;
+	config.period_size    = 256;
+	config.num_periods    = 2;
+
+	/*
+	 * Changes to config.sample_width would require changes
+	 * to data types (16 vs 32 bit), buffer sizes, as well
+	 * as the wakeup threshold.
+	 */
+	config.sample_width   = TEGRA_AODMIC_BITS_PER_SAMPLE_16;
+
+	switch (config.channel_config) {
+	case TEGRA_AODMIC_CHANNEL_MONO_LEFT:
+	case TEGRA_AODMIC_CHANNEL_MONO_RIGHT:
+		num_channels = 1;
+		break;
+	case TEGRA_AODMIC_CHANNEL_STEREO:
+		num_channels = 2;
+		break;
+
+	default:
+		sprintf(err_msg, "aodmic_test: invalid channel_config");
+		goto err_exit;
+	}
+
+	/* GPCDMA configuration */
+	config.dma_id         = &gpcdma_id_aon;
+	config.dma_chan_num   = AODMIC_DMA_CHANNEL;
+
+	/* buf_size for application data buffer */
+	buf_size = config.period_size * config.sample_width * num_channels;
+	/* Below is dependent on sample rate */
+	period_ms = config.period_size / config.sample_rate;
+
+	/* Allocate memory for application buffer */
+	buf = malloc(buf_size);
+	if (buf == NULL) {
+		sprintf(err_msg, "aodmic_test: Unable to allocate data buffer");
+		goto err_exit;
+	}
+
+	/* Allocate memory for driver buffers
+	 * - driver always uses 4 bytes/sample internally
+	 */
+	config.gpcdma_buf_size = config.period_size * config.num_periods * 4 * num_channels;
+	config.gpcdma_buf = malloc(config.gpcdma_buf_size);
+	if (config.gpcdma_buf == NULL) {
+		sprintf(err_msg, "aodmic_test: Unable to allocate driver buffer");
+		goto err_exit;
+	}
+	printf("aodmic_test: Opening AODMIC (channel %ld)...\n\r",
+		config.dma_chan_num);
+	status = tegra_aodmic_open(&TEST_AODMIC, &config);
+	if (status) {
+		sprintf(err_msg, "aodmic_test: Couldn't initialize AODMIC: %x", status);
+		goto err_exit;
+	}
+	aodmic_opened = 1;
+
+	printf("aodmic_test: Starting AODMIC read...\n\r");
+	start_time = rtosTaskGetTickCount();
+	for (i = 1; ; i++) {
+		status = tegra_aodmic_read(&TEST_AODMIC, buf, buf_size);
+		if (status) {
+			sprintf(err_msg, "aodmic_test: Couldn't read from AODMIC: %x", status);
+			rtosTaskDelay(period_ms);
+			continue;
+		}
+
+		temp_l = 0;
+		temp_r = 0;
+		for (j = 0; j < (config.period_size * num_channels); j += num_channels) {
+			cur_samp_l = buf[j];
+
+			/* Count zero crossings on both channels */
+			if (((prev_samp_l < 0) && (cur_samp_l >= 0)) ||
+			    ((prev_samp_l > 0) && (cur_samp_l <= 0))) {
+				zero_cross_l++;
+			}
+
+			prev_samp_l = cur_samp_l;
+
+			/* Accumulate capture volume on both channels */
+			temp_l += cur_samp_l * cur_samp_l;
+
+			if (num_channels == 2) {
+				cur_samp_r = buf[j+1];
+				if (((prev_samp_r < 0) && (cur_samp_r >= 0)) ||
+					((prev_samp_r > 0) && (cur_samp_r <= 0))) {
+					zero_cross_r++;
+				}
+				prev_samp_r = cur_samp_r;
+				temp_r += cur_samp_r * cur_samp_r;
+			}
+		}
+		vol_l += (temp_l / config.period_size);
+		if (num_channels == 2) {
+			vol_r += (temp_r / config.period_size);
+		}
+
+		if ((i % 30) == 0) {
+			/* Print tick count and zero crossing count - */
+			/*  useful to check correct AODMIC rate       */
+			end_time = rtosTaskGetTickCount();
+			if (num_channels == 2) {
+				printf("aodmic_test: Ticks: %u; Zero Crossings: L(%d) R(%d)\n\r",
+					(unsigned int)
+					((end_time - start_time) * rtosTICK_RATE_MS),
+					zero_cross_l, zero_cross_r);
+			} else {
+				printf("aodmic_test: Ticks: %u; Zero Crossings: (%d)\n\r",
+					(unsigned int)
+					((end_time - start_time) * rtosTICK_RATE_MS),
+					zero_cross_l);
+			}
+			zero_cross_l = 0;
+			zero_cross_r = 0;
+			start_time = rtosTaskGetTickCount();
+
+			/* CCPLEX wake - on volume trigger */
+			vol_l /= 30;
+			if (num_channels == 2) {
+				vol_r /= 30;
+				printf("aodmic_test: Computed volume: L(%u) R(%u)\n\r",
+					vol_l, vol_r);
+			} else {
+				printf("aodmic_test: Computed volume: (%u)\n\r", vol_l);
+			}
+			if ((vol_l >= SPE_CCPLEX_WAKE_THRESHOLD) ||
+			    (vol_r >= SPE_CCPLEX_WAKE_THRESHOLD)) {
+				printf("aodmic_test: !!! TRIGGERING CCPLEX WAKE !!!\n\r");
+				wake_trigger_ccplex_wake();
+			}
+			vol_l = 0;
+			vol_r = 0;
+		}
+	}
+
+err_exit:
+	error_hook(err_msg);
+
+	if (aodmic_opened)
+		tegra_aodmic_close(&TEST_AODMIC);
+	if (buf != NULL)
+		free(buf);
+	if (config.gpcdma_buf != NULL)
+		free(config.gpcdma_buf);
+
+	rtosTaskDelete(NULL);
+}
+
+void aodmic_app_init(void)
+{
+	rtosTaskParameters aodmic_test_task_params = {
+		.pvTaskCode = &aodmic_test_task,
+		.pcTaskName = (char *)"aodmictest",
+		.uxPriority = rtosIDLE_PRIORITY,
+		.pvParameters = NULL,
+		.uxStackDepthBytes = 1024,
+	};
+	printf("aodmic_test: Launching task...\n\r");
+	rtosTaskCreate(&aodmic_test_task_params, NULL);
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/aodmic-app.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/aodmic-app.h
new file mode 100644
index 0000000..ff9ece3
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/aodmic-app.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __AODMIC_APP_H
+#define __AODMIC_APP_H
+
+void aodmic_app_init(void);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/gpio-app.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/gpio-app.c
new file mode 100644
index 0000000..a5a53ce
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/gpio-app.c
@@ -0,0 +1,113 @@
+/*
+ * Copyright (c) 2017-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Note: Follow doc/gpio.txt to successfully run this demo app */
+
+#include <err-hook.h>
+#include <printf-isr.h>
+#include <stdio.h>
+#include <osa/rtos-task.h>
+#include <gpio/tegra-gpio.h>
+
+/* gpio-aon.h has GPIO_APP* defines */
+#include "gpio-aon.h"
+#include "gpio-app.h"
+
+#define GPIO_OUT_SET_DELAY	3000
+
+void can_gpio_irq_handler(void *data);
+
+void can_gpio_irq_handler(void *data)
+{
+	printf_isr("%s - gpio irq triggered - setting GPIO_APP_OUT to 0 \r\n",
+		   __func__);
+	tegra_gpio_set_value(GPIO_APP_OUT, 0);
+}
+
+static void gpio_app_task(void *pvParameters)
+{
+	(void)pvParameters;
+	int val;
+
+	val = tegra_gpio_direction_out(GPIO_APP_OUT, 0);
+	if (val) {
+		error_hook("tegra_gpio_direction_out failed\r\n");
+		return;
+	}
+
+	val = tegra_gpio_direction_in(GPIO_APP_IN);
+	if (val) {
+		error_hook("tegra_gpio_direction_in failed\r\n");
+		return;
+	}
+
+	val = tegra_gpio_set_irq_type(GPIO_APP_IN, TEGRA_GPIO_IRQ_SINGLE_EDGE,
+				TEGRA_GPIO_IRQ_RISING_EDGE);
+	if (val) {
+		error_hook("tegra_gpio_set_irq_type failed\r\n");
+		return;
+	}
+
+	val = tegra_gpio_set_irq_handler(GPIO_APP_IN, can_gpio_irq_handler, NULL);
+	if (val) {
+		error_hook("tegra_gpio_set_irq_handler failed\r\n");
+		return;
+	}
+
+	val = tegra_gpio_enable_irq(GPIO_APP_IN);
+	if (val) {
+		error_hook("tegra_gpio_enable_irq failed\r\n");
+		return;
+	}
+
+	while (1) {
+		printf("%s - Setting GPIO_APP_OUT to 1 - IRQ should trigger\r\n",
+		       __func__);
+		rtosTaskDelay(5);
+		tegra_gpio_set_value(GPIO_APP_OUT, 1);
+		rtosTaskDelay(GPIO_OUT_SET_DELAY);
+		tegra_gpio_set_value(GPIO_APP_OUT, 0);
+		rtosTaskDelay(GPIO_OUT_SET_DELAY);
+	};
+}
+
+void gpio_app_init(void)
+{
+	rtosTaskParameters gpio_app_task_params = {
+		.pvTaskCode = &gpio_app_task,
+		.pcTaskName = (char *)"gpioapp",
+		.uxPriority = rtosIDLE_PRIORITY,
+		.pvParameters = NULL,
+		.uxStackDepthBytes = 512,
+	};
+
+	int val = rtosTaskCreate(&gpio_app_task_params, NULL);
+
+	if (val != rtosPASS)
+		error_hook("xTaskCreate for gpio_app_task failed\r\n");
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/gpio-app.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/gpio-app.h
new file mode 100644
index 0000000..a7db58c
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/gpio-app.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+void gpio_app_init(void);
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/gte-app.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/gte-app.c
new file mode 100644
index 0000000..8952bf5
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/gte-app.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2019-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Note: Follow doc/gte-app.md for more information */
+
+#include <delay/delay.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <misc/macros.h>
+#include <misc/bitops.h>
+#include <err-hook.h>
+#include <gte-tegra.h>
+#include <gte-tegra-hw.h>
+#include <printf-isr.h>
+#include <gte-app.h>
+#include "gpio-aon.h"
+#include <gpio/tegra-gpio.h>
+
+#define GTE_TEST_FIFO_OCCUPANCY         1
+
+static void gte_irq_callback(void *data, struct tegra_gte_ts *gte_ts)
+{
+		const char *evname;
+
+		if (gte_ts->slice == 1 &&
+			gte_ts->bit_index == NV_AON_GTE_SLICE1_IRQ_GPIO)
+			evname = "GPIO IRQ";
+		else if (gte_ts->slice == 2 &&
+			gte_ts->bit_index == NV_AON_GTE_SLICE2_IRQ_GPIO_2)
+			evname = "GPIO_APP_IN";
+		else
+			evname = "Other";
+
+		printf_isr("Slice Id: %d, Event Id: %d (%s), Edge = %s, "
+					"Raw Time stamp = %x Time Stamp in nanosec %08llx\r\n",
+					gte_ts->slice, gte_ts->bit_index, evname,
+					gte_ts->bit_dir ? "rising" : "falling",
+					(unsigned int)(gte_ts->tsc >> 32),
+					(gte_ts->tsc));
+}
+
+void gte_app_init(void)
+{
+        /* Enable GPIO_APP_IN GPIO GTE timestamp */
+		tegra_gte_slice_set_enable_mask(&tegra_gte_id_aon,
+										2, /* slice number 2 */
+										BIT(GTE_SLICE_IRQ_GPIO));
+
+	       	error_t ret = tegra_gte_setup(&tegra_gte_id_aon, GTE_TEST_FIFO_OCCUPANCY,
+										gte_irq_callback, 0, 0, 0);
+		if (ret)
+			error_hook("GTE setup failed\r\n");
+
+		/* Enable timestamping on GPIO_APP_IN at GPIO controller */
+		ret = tegra_gpio_enable_timestamp(GPIO_APP_IN);
+		if (ret)
+			error_hook("gpio_enable_timestamp -failed\r\n");
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/i2c-app.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/i2c-app.c
new file mode 100644
index 0000000..0835e30
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/i2c-app.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Note: Follow doc/i2c-app.md to successfully run this demo app */
+
+#include <stdio.h>
+#include <string.h>
+#include <osa/rtos-task.h>
+#include <processor/i2c-tegra-hw.h>
+#include <misc/bitops.h>
+#include <err-hook.h>
+#include <i2c/i2c.h>
+#include "config.h"
+#include "i2c-app.h"
+#include "i2c-app-priv.h"
+
+#define I2C_TEST_BUS_CLKRATE	100000
+#define I2C_TEST_RETRIES	5
+#define I2C_TEST_DELAY		10000
+
+static void i2c_app_task(void *pvParameters)
+{
+	int count;
+	(void)pvParameters;
+	struct i2c_handle hi2c;
+
+	error_t ret = i2c_controller_init(I2C_AON_BUS_NUM, &hi2c);
+
+	if (ret != E_SUCCESS) {
+		error_hook("Couldn't initialize I2C\r\n");
+		goto done;
+	}
+	for (count = 0; count < I2C_TEST_RETRIES; count++) {
+		i2c_test(&hi2c);
+		rtosTaskDelay(I2C_TEST_DELAY);
+	}
+done:
+	rtosTaskDelete(NULL);
+}
+
+void i2c_app_init(void)
+{
+	int ret;
+	rtosTaskParameters i2c_app_task_params = {
+		.pvTaskCode = &i2c_app_task,
+		.pcTaskName = (char *)"i2ctest",
+		.uxPriority = rtosIDLE_PRIORITY,
+		.pvParameters = NULL,
+		.uxStackDepthBytes = 512,
+	};
+
+	ret = rtosTaskCreate(&i2c_app_task_params, NULL);
+	if (ret != rtosPASS)
+		error_hook("xTaskCreate for i2c_app_task failed\r\n");
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/i2c-app.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/i2c-app.h
new file mode 100644
index 0000000..5856543
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/i2c-app.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __I2C_APP_H
+#define __I2C_APP_H
+
+void i2c_app_init(void);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/ivc-echo-task.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/ivc-echo-task.c
new file mode 100644
index 0000000..3bb5578
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/ivc-echo-task.c
@@ -0,0 +1,235 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <stdbool.h>
+#include <stdarg.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <err-hook.h>
+#include <misc/bitops.h>
+#include <tegra-ivc.h>
+#include <ivc-echo-task.h>
+#include <ivc-channels.h>
+#include <dbgprintf.h>
+#include <osa/rtos-semaphore.h>
+#include <osa/rtos-mutex.h>
+#include <osa/rtos-task.h>
+#include <osa/rtos-event-group.h>
+
+#define EVENT_WAIT_BIT			BIT(0)
+#define EVENT_IVC_RAM_INITED_BIT	BIT(1)
+
+#define EVENT_WAIT_ALL_BITS	(EVENT_WAIT_BIT | \
+				EVENT_IVC_RAM_INITED_BIT)
+
+struct ivc_echo_task_state {
+	struct ivc_task_id *id;
+	rtosTaskHandle handle;
+	rtosEventGroupHandle wait_event;
+	rtosSemaphoreHandle ivc_sem;
+};
+
+static struct ivc_echo_task_state *ivc_state = NULL;
+
+static int ivc_echo_task_write_msg(void *data, int length)
+{
+	int ret;
+	char *tx_msg;
+	bool non_contig_available;
+
+	if (!ivc_state) {
+		error_hook("ivc_echo_task not init");
+		return -1;
+	}
+
+	if (length > ivc_state->id->ivc_ch->frame_size) {
+		error_hook("length larger than frame buffer size");
+		return -1;
+	}
+
+	rtosSemaphoreAcquire(ivc_state->ivc_sem, rtosMAX_DELAY);
+
+	ret = tegra_ivc_tx_get_contiguous_write_space(
+		ivc_state->id->ivc_ch, &tx_msg, &non_contig_available);
+	if (ret < 1) {
+		error_hook("tegra_ivc_tx_get_contiguous_write_space() failed");
+		goto exit;
+	}
+
+	memcpy(tx_msg, data, length);
+
+	ret = tegra_ivc_tx_send_buffers(ivc_state->id->ivc_ch, 1);
+	if (ret) {
+		error_hook("tegra_ivc_tx_send_buffers() failed");
+	}
+
+exit:
+	rtosSemaphoreRelease(ivc_state->ivc_sem);
+	return ret;
+}
+
+static void ivc_echo_task_process_ivc_messages(struct ivc_echo_task_state *state)
+{
+	int ret;
+	const char *rx_msg;
+	bool non_contig_available;
+	int count, i;
+
+	for (;;) {
+		rtosSemaphoreAcquire(state->ivc_sem, rtosMAX_DELAY);
+		count = tegra_ivc_rx_get_contiguous_read_available(
+			state->id->ivc_ch, &rx_msg, &non_contig_available);
+		rtosSemaphoreRelease(state->ivc_sem);
+		dbgprintf("IVC read count: %d\r\n", count);
+		if (count < 0) {
+			error_hook("tegra_ivc_rx_get_contiguous_read_available() failed");
+			return;
+		}
+		if (!count) {
+			return;
+		} else {
+			for (i = 0; i < count; i++) {
+				ivc_echo_task_write_msg((void *)rx_msg, 64);
+				rx_msg += 64;
+			}
+		}
+		rtosSemaphoreAcquire(state->ivc_sem, rtosMAX_DELAY);
+		ret = tegra_ivc_rx_notify_buffers_consumed(state->id->ivc_ch,
+			count);
+		rtosSemaphoreRelease(state->ivc_sem);
+		if (ret) {
+			error_hook("tegra_ivc_rx_notify_buffers_consumed() failed");
+			return;
+		}
+	}
+}
+
+static void ivc_echo_task(void *pvParameters)
+{
+	struct ivc_echo_task_state *state = pvParameters;
+	EventBits_t ret;
+
+	for (;;) {
+		ret = rtosEventGroupWaitBits(state->wait_event,
+					  EVENT_WAIT_ALL_BITS,
+					  pdFALSE,
+					  pdTRUE,
+					  NULL,
+					  rtosMAX_DELAY);
+		if ((ret & EVENT_WAIT_ALL_BITS) == EVENT_WAIT_ALL_BITS) {
+			rtosEventGroupClearBits(state->wait_event,
+					     EVENT_WAIT_BIT);
+			ivc_echo_task_process_ivc_messages(state);
+		}
+	}
+}
+
+void *ivc_echo_task_init(struct ivc_task_id *id)
+{
+	struct ivc_echo_task_state *state;
+	int ret;
+
+	state = calloc(1, sizeof(*state));
+	if (!state) {
+		error_hook("calloc(struct ivc_echo_task_state) failed");
+		return NULL;
+	}
+
+	state->id = id;
+
+	rtosEventGroupCreate(NULL, &state->wait_event);
+	if (state->wait_event == NULL) {
+		error_hook("xEventGroupCreate() failed");
+		free(state);
+		return NULL;
+	}
+
+	rtosMutexCreate(NULL, &state->ivc_sem);
+	if (!state->ivc_sem) {
+		error_hook("xSemaphoreCreateMutex() failed");
+		rtosEventGroupDelete(state->wait_event);
+		free(state);
+		return NULL;
+	}
+	rtosTaskParameters ivc_echo_task_params = {
+		.pvTaskCode = &ivc_echo_task,
+		.pcTaskName = (char *)"ivcecho",
+		.uxPriority = 1,
+		.pvParameters = state,
+		.uxStackDepthBytes = 512,
+	};
+
+	ret = rtosTaskCreate(&ivc_echo_task_params, state->handle);
+	if (ret != pdPASS) {
+		error_hook("xTaskCreate() failed");
+		rtosEventGroupDelete(state->wait_event);
+		rtosSemaphoreDelete(state->ivc_sem);
+		free(state);
+		return NULL;
+	}
+
+	ivc_state = state;
+
+	return state;
+}
+
+int ivc_echo_task_ivc_notified(void *statev,
+		 rtosPortBaseType *higher_prio_task_woken)
+{
+	struct ivc_echo_task_state *state = statev;
+	rtosPortBaseType ret;
+
+	ret = rtosEventGroupSetBitsFromISR(state->wait_event,
+					EVENT_WAIT_BIT,
+					higher_prio_task_woken);
+	if (ret != pdPASS) {
+		error_hook("xEventGroupSetBitsFromISR() failed");
+		return -1;
+	}
+
+	return 0;
+}
+
+int ivc_echo_task_ivc_inited(void *statev,
+		 rtosPortBaseType *higher_prio_task_woken)
+{
+	struct ivc_echo_task_state *state = statev;
+	rtosPortBaseType ret;
+
+	ret = rtosEventGroupSetBitsFromISR(state->wait_event,
+					EVENT_IVC_RAM_INITED_BIT,
+					higher_prio_task_woken);
+	if (ret != pdPASS) {
+		error_hook("xEventGroupSetBitsFromISR() failed");
+		return -1;
+	}
+
+	return 0;
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/spi-app.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/spi-app.c
new file mode 100644
index 0000000..824bc2e
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/spi-app.c
@@ -0,0 +1,132 @@
+/*
+ * Copyright (c) 2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <osa/rtos-task.h>
+#include <misc/macros.h>
+#include <misc/bitops.h>
+#include <argpcdma_ao.h>
+#include <spi/spi.h>
+#include <processor/spi-hw.h>
+#include <processor/gpcdma-hw.h>
+#include <printf-isr.h>
+#include <err-hook.h>
+
+
+#include "spi-app.h"
+
+#define SPI_TEST_CONTROLLER	spi_ctlr_spi2
+#define SPI_TEST_CLOCK_RATE	12000000
+#define SPI_TEST_DMA_TX_CHANNEL	2
+#define SPI_TEST_DMA_RX_CHANNEL	3
+
+#define SPI_TEST_RETRIES	5
+#define SPI_TEST_DELAY		5000
+
+static void spi_test_task(void *pvParameters)
+{
+	int ret, count;
+	(void)pvParameters; /* unused */
+	const uint8_t data_to_send[] = {0xab, 0xcd};
+	uint8_t data_to_read[] = {0x0, 0x0};
+	struct spi_client_setting spi_test_device[] = {
+		{
+			.chip_select = 0,
+			.set_rx_tap_delay = false,
+			.spi_max_clk_rate = SPI_TEST_CLOCK_RATE,
+			.spi_no_dma = false,
+		}
+	};
+	struct spi_master_init master_test_conf[] = {
+		{
+			.dma_id = &gpcdma_id_aon,
+			.dma_chans.tx = SPI_TEST_DMA_TX_CHANNEL,
+			.dma_chans.rx = SPI_TEST_DMA_RX_CHANNEL,
+			.spi_max_clk_rate = SPI_TEST_CLOCK_RATE,
+			.dma_slave_req = GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_SPI,
+		}
+	};
+
+	ret = spi_init(&SPI_TEST_CONTROLLER, master_test_conf);
+	if (ret) {
+		printf("spi_test: master init failed\r\n");
+		return;
+	}
+
+	ret = spi_client_setup(&SPI_TEST_CONTROLLER, spi_test_device);
+	if (ret) {
+		printf("spi_test: couldn't setup SPI device\r\n");
+		return;
+	}
+
+	struct spi_xfer xfer = {
+		.flags = BIT(TEGRA_SPI_XFER_FIRST_MSG) |
+			 BIT(TEGRA_SPI_XFER_LAST_MSG),
+		.tx_buf = data_to_send,
+		.rx_buf = data_to_read,
+		.len = ARRAY_SIZE(data_to_read),
+		.chip_select = 0,
+		.tx_nbits = TEGRA_SPI_NBITS_SINGLE,
+		.rx_nbits = TEGRA_SPI_NBITS_SINGLE,
+		.bits_per_word = 8,
+		.mode = TEGRA_SPI_MODE_0 | TEGRA_SPI_LSBYTE_FIRST,
+	};
+
+	for (count = 0; count < SPI_TEST_RETRIES; count++) {
+		ret = spi_transfer(&SPI_TEST_CONTROLLER, &xfer);
+		if (ret)
+			printf("SPI TX/RX failed\r\n");
+		else {
+			if (!memcmp(data_to_read, data_to_send,
+				    ARRAY_SIZE(data_to_read)))
+				printf("SPI test successful\r\n");
+			else
+				printf("Received incorrect data\r\n");
+		}
+		rtosTaskDelay(SPI_TEST_DELAY);
+	}
+	rtosTaskDelete(NULL);
+}
+
+void spi_app_init(void)
+{
+	int ret;
+
+	rtosTaskParameters spi_test_task_params = {
+		.pvTaskCode = &spi_test_task,
+		.pcTaskName = (char *)"spitest",
+		.uxPriority = rtosIDLE_PRIORITY,
+		.pvParameters = NULL,
+		.uxStackDepthBytes = 512,
+	};
+	printf("spi_test: Launching task...\n\r");
+	ret = rtosTaskCreate(&spi_test_task_params, NULL);
+	if (ret != rtosPASS)
+  		error_hook("xTaskCreate for spi_test_task_params\r\n");
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/spi-app.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/spi-app.h
new file mode 100644
index 0000000..427cf7d
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/spi-app.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SPI_APP_H
+#define __SPI_APP_H
+
+void spi_app_init(void);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/spi-slv-app.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/spi-slv-app.c
new file mode 100644
index 0000000..c8a5a2d
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/spi-slv-app.c
@@ -0,0 +1,147 @@
+/*
+ * Copyright (c) 2024, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <osa/rtos-task.h>
+#include <misc/macros.h>
+#include <misc/bitops.h>
+#include <argpcdma_ao.h>
+#include <spi-slv/spi-slave.h>
+#include <processor/spi-hw.h>
+#include <processor/gpcdma-hw.h>
+#include <printf-isr.h>
+#include <err-hook.h>
+
+
+#include "spi-slv-app.h"
+
+#define SPI_TEST_CONTROLLER	spi_ctlr_spi2
+#define SPI_TEST_CLOCK_RATE	12000000
+#define SPI_TEST_DMA_TX_CHANNEL	2
+#define SPI_TEST_DMA_RX_CHANNEL	3
+
+#define SPI_TEST_DELAY		500
+#define SPI_BUFFER_SIZE		2
+
+/* Data expected from Master */
+static uint8_t txBuffer[SPI_BUFFER_SIZE] = { 0xcc, 0x55 };
+
+static void spi_slv_test_task(void *pvParameters)
+{
+	int ret;
+	(void)pvParameters; /* unused */
+
+	uint8_t rx[SPI_BUFFER_SIZE];
+	uint32_t i = 0;
+	uint32_t errs = 0;
+	memset(rx, 0x0, ARRAY_SIZE(rx) * sizeof(uint8_t));
+
+	struct spi_client_setting spi_slv_test_device = {
+		.chip_select = 0U,
+		/* Optional params for cs */
+		.cs_setup_clk_count = 16,
+		.cs_hold_clk_count = 16,
+		.cs_inactive_cycles = 32,
+		.set_rx_tap_delay = false,
+		.spi_max_clk_rate = SPI_TEST_CLOCK_RATE,
+		.spi_no_dma = false,
+	};
+
+	struct spi_slave_init_setup spi_slv_setup = {
+		.dma_id = &gpcdma_id_aon,
+		.dma_chans.tx = SPI_TEST_DMA_TX_CHANNEL,
+		.dma_chans.rx = SPI_TEST_DMA_RX_CHANNEL,
+		.spi_max_clk_rate = SPI_TEST_CLOCK_RATE,
+		.dma_slave_req = GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_SPI,
+	};
+
+	ret = spi_slave_init(&SPI_TEST_CONTROLLER, &spi_slv_setup);
+	if (ret) {
+		printf("spi_slv_test: slave init failed\r\n");
+		goto out;
+	}
+
+	ret = spi_slave_setup(&SPI_TEST_CONTROLLER, &spi_slv_test_device);
+	if (ret) {
+		printf("spi_slv_test: couldn't setup SPI slave device\r\n");
+		goto out;
+	}
+
+	struct spi_xfer xfer = {
+		.flags = BIT(TEGRA_SPI_XFER_LAST_MSG) | BIT(TEGRA_SPI_XFER_FIRST_MSG),
+		.tx_buf = NULL,
+		.rx_buf = (uint8_t *)&rx,
+		.len = SPI_BUFFER_SIZE,
+		.chip_select = 0,
+		.tx_nbits = TEGRA_SPI_NBITS_SINGLE,
+		.rx_nbits = TEGRA_SPI_NBITS_SINGLE,
+		.bits_per_word = 8,
+		.mode = TEGRA_SPI_MODE_0 | TEGRA_SPI_LSBYTE_FIRST,
+	};
+
+	ret = spi_slave_transfer(&SPI_TEST_CONTROLLER, &xfer);
+	if (ret != E_SUCCESS) {
+		printf("spi_slave_test: not ready to accept the data\r\n");
+		goto out;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(rx); i++) {
+		if(rx[i] != txBuffer[i]) {
+			errs++;
+			break;
+		}
+	}
+
+	if (errs != 0) {
+		printf("** SPI Slave test Failed **\r\n");
+	} else {
+		printf("** SPI Slave test Passed **\r\n");
+	}
+
+out:
+	rtosTaskDelay(SPI_TEST_DELAY);
+	rtosTaskDelete(NULL);
+}
+
+void spi_slv_app_init(void)
+{
+	int ret;
+
+	rtosTaskParameters spi_slv_test_task_params = {
+		.pvTaskCode = &spi_slv_test_task,
+		.pcTaskName = (char *)"spi_slv_test",
+		.uxPriority = rtosIDLE_PRIORITY,
+		.pvParameters = NULL,
+		.uxStackDepthBytes = 512,
+	};
+	printf("spi_slv_test: Launching task...\n\r");
+	ret = rtosTaskCreate(&spi_slv_test_task_params, NULL);
+	if (ret != rtosPASS)
+		error_hook("xTaskCreate for spi_slv_test_task_params\r\n");
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/spi-slv-app.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/spi-slv-app.h
new file mode 100644
index 0000000..97208e9
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/spi-slv-app.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2024, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SPI_SLV_APP_H
+#define __SPI_SLV_APP_H
+
+void spi_slv_app_init(void);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/timer-app.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/timer-app.c
new file mode 100644
index 0000000..73117fc
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/timer-app.c
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+
+#include <printf-isr.h>
+#include <tke/tke-tegra.h>
+#include <processor/tke-tegra-hw.h>
+
+#include "timer-app.h"
+
+/* Demo timer app which sets up 5 second periodic timer, modify below define to
+ * adjust periodic value of the timer.
+ */
+#define TIMER2_PTV 5000000
+#define STOP_TIMER 10
+
+static void timer2_callback(void *data)
+{
+	static int count = 0;
+	uint32_t usec, osc, tsc_hi, tsc_lo;
+
+	usec = tegra_tke_get_usec();
+	osc = tegra_tke_get_osc();
+	tegra_tke_get_tsc(&tsc_hi, &tsc_lo);
+	printf_isr("Timer2 irq triggered, usec = %lu, osc = %lu "
+		   "tsc_hi = %lu, tsc_lo = %lu\r\n", usec, osc, tsc_hi, tsc_lo);
+	if (++count > STOP_TIMER)
+		tegra_tke_stop_timer(&tegra_tke_id_timer2);
+
+}
+
+void timer_app_init(void)
+{
+	tegra_tke_set_up_timer(&tegra_tke_id_timer2, TEGRA_TKE_CLK_SRC_USECCNT,
+			       true, TIMER2_PTV, timer2_callback, 0);
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/timer-app.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/timer-app.h
new file mode 100644
index 0000000..bbbf4f4
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/app/timer-app.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __TIMER_APP_H
+#define __TIMER_APP_H
+
+void timer_app_init(void);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/aodmic-app.md b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/aodmic-app.md
new file mode 100644
index 0000000..f654841
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/aodmic-app.md
@@ -0,0 +1,200 @@
+AODMIC Application (app/aodmic-app.c)
+==============================
+@tableofcontents
+
+The AODMIC application demonstrates how to operate the Digital Microphone (DMIC)
+interface from the SPE/AON processor. DMIC5 is located in the Always-On (AON)
+domain and is correspondingly referred to as AODMIC.  This demo additionally
+shows how AODMIC can be used as a system wake-up source.
+
+The app runs continuously and captures data from AODMIC using GPCDMA. It
+periodically prints the R5 CPU tick count and the zero crossing count (on both
+capture channels). These counts can be used to determine whether the AODMIC is
+running at the expected rate. The app also computes and prints the capture
+volume over fixed periods (computed as the mean square of the samples). Should
+the computed volume exceed a predefined threshold, it triggers a system wake
+event.
+
+The `sample_rate` parameter of the aodmic config structure can be set to any of
+these values:
+
+* `TEGRA_AODMIC_RATE_8KHZ`
+* `TEGRA_AODMIC_RATE_16KHZ` (default in `app/aodmic-app.c`)
+* `TEGRA_AODMIC_RATE_44KHZ` (44.1 kHz)
+* `TEGRA_AODMIC_RATE_48KHZ`
+
+**NOTE**: The AODMIC uses a fixed 64x oversampling rate.  The programmer must
+ensure that the corresponding clock speed falls within the supported range of
+the microphone.  For example, the 8 kHz sampling rate corresponds to a 512 kHz
+clock speed.  If the microphone supports 1 MHz - 3.25 MHz, then 16 kHz is the
+lowest clock speed that can be used.
+
+The `channel_config` parameter of the aodmic config structure can be set to any of
+these values:
+
+* `TEGRA_AODMIC_CHANNEL_STEREO` (default in `app/aodmic-app.c`)
+* `TEGRA_AODMIC_CHANNEL_MONO_LEFT`
+* `TEGRA_AODMIC_CHANNEL_MONO_RIGHT`
+
+The `num_periods` parameter of the aodmic config structure can set to any value in
+the range of 2 to `AODMIC_MAX_NUM_PERIODS` (default of 4).  The typical value
+for this parameter is 2 (i.e. double buffered I/O).  The value of
+`AODMIC_MAX_NUM_PERIODS` can be increased if necessary.  It is located in the file
+`fsp/source/include/aodmic/tegra-aodmic.h`.
+# Prerequisites
+
+Stereo PDM mics should be connected to the AODMIC pins on the respective
+Jetson platform. An example PDM mic part is
+https://www.mouser.in/datasheet/2/389/mp34dt01-m-955068.pdf. Details of the
+AODMIC pins are mentioned in the platform specific sections further down.
+
+# Jetson AGX Orin
+
+## Hardware Configuration
+
+AODMIC signals are available at the 40-pin header J30 with these pin mappings:
+- Pin 16 - DMIC5_DAT (CAN1_EN)
+- Pin 32 - DMIC5_CLK (CAN1_STB)
+
+Power and ground will also be needed for the PDM board.  A typical setup
+might use J30 Pin 1 (3.3V) and Pin 6 (GND).
+
+## Software Configuration
+
+1. Pinmuxing updates are recommended via generating new dtsi files using
+the pinmux spreadsheet.  For the purpose of performing a quick test, the pinmux files can be manually
+updated by editing `${L4T}/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi`:
+
+            --- a/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi
+            +++ b/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi
+            @@ -142,6 +142,22 @@
+                                            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                    };
+
+            +                       can1_stb_pbb0 {
+            +                               nvidia,pins = "can1_stb_pbb0";
+            +                               nvidia,function = "dmic5";
+            +                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+            +                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+            +                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+            +                       };
+            +
+            +                       can1_en_pbb1 {
+            +                               nvidia,pins = "can1_en_pbb1";
+            +                               nvidia,function = "dmic5";
+            +                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+            +                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
+            +                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+            +                       };
+            +
+                                    soc_gpio50_pbb2 {
+                                            nvidia,pins = "soc_gpio50_pbb2";
+                                            nvidia,function = "tsc";
+            @@ -989,22 +1005,6 @@
+                                            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                    };
+
+            -                       can1_stb_pbb0 {
+            -                               nvidia,pins = "can1_stb_pbb0";
+            -                               nvidia,function = "rsvd0";
+            -                               nvidia,pull = <TEGRA_PIN_PULL_UP>;
+            -                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
+            -                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+            -                       };
+            -
+            -                       can1_en_pbb1 {
+            -                               nvidia,pins = "can1_en_pbb1";
+            -                               nvidia,function = "rsvd0";
+            -                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+            -                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
+            -                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+            -                       };
+            -
+                                    can1_err_pbb3 {
+                                            nvidia,pins = "can1_err_pbb3";
+                                            nvidia,function = "rsvd0";
+
+
+2. Update gpio configuration as below in `${L4T}/bootloader/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi`
+
+            --- a/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi
+            +++ b/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi
+            @@ -117,8 +117,6 @@
+                            TEGRA234_AON_GPIO(AA, 1)
+                            TEGRA234_AON_GPIO(AA, 2)
+                            TEGRA234_AON_GPIO(AA, 3)
+            -               TEGRA234_AON_GPIO(BB, 0)
+            -               TEGRA234_AON_GPIO(BB, 1)
+                            TEGRA234_AON_GPIO(BB, 3)
+                            >;
+
+3. Modify firewall setting in `${L4T}/bootloader/tegra234-mb2-bct-scr-p3701-0000-override.dts` to allow SPE to write to the AODMIC clock register.
+
+            +++ b/bootloader/tegra234-mb2-bct-scr-p3701-0000-override.dts
+            @@ -24,6 +24,11 @@
+                           value = <0x18000606>;
+                       };
+
+            +          reg@2126 { /* CLK_RST_CONTROLLER_AON_SCR_DMIC5_0 */
+            +              exclusion-info = <3>;
+            +              value = <0x30001400>;
+            +          };
+            +
+                       reg@5114 { /* CBB_CENTRAL_CBB_FIREWALL_PWM5_BLF, READ_CTL */
+
+4. In `soc/t23x/target_specific.mk`, set `ENABLE_AODMIC_APP := 1` and rebuild the
+application. Copy the output to `${L4T}/bootloader/spe_t234.bin`.
+
+5. Reflash all partitions to ensure that the pinmux and firewall settings are updated on the board.
+
+6. Volume and zero-crossings are printed in the terminal.
+
+7. If the system is placed in suspended state, BPMP will disable
+the dmic5 clock at the subsequent system wake, upon which AODMIC capture
+will fail. You can patch this in either of two ways:
+    - On the running target execute prior to the first suspend:
+```
+# sudo su -c 'echo 1 > /sys/kernel/debug/bpmp/debug/clk/dmic5/state'
+```
+*or*
+    - Patch the platform BPMP DT file (e.g. `tegra234-bpmp-3701-0000-3737-0000.dtb`)
+  following these steps:
+        - Reconstruct the device tree source file from the DTB:
+
+                $ dtc -I dtb -O dts <BPMP DT file> -o <temp_file.dts>
+
+        - Patch the third and fourth arguments to the 'dmic5' entry in the
+        generated `temp_file.dts` file (third argument = <sample_rate*64>):
+
+            clocks {
+                lateinit {
+                    dmic5 = <0x86 0x5b 1024000 0x80000>;
+                };
+            };
+
+        - Recreate the DTB file from the patched DTS:
+
+                $ dtc -I dts -O dtb <temp_file.dts> -o <BPMP DT file>
+
+        - Flash the `bpmp-fw-dtb` partition, or perform a full flash.
+
+
+8. The command below may be executed on the running target in order to trigger
+system suspend:
+```
+# sudo systemctl suspend
+```
+
+9. After the system is placed in the suspended state,
+making a loud sound near the microphone will wake it up. The threshold can
+be adjusted via the `SPE_CCPLEX_WAKE_THRESHOLD` definition in `aodmic-app.c`.
+
+@note To demonstrate system wake, the corresponding wake event must be enabled
+by CCPLEX/BPMP. In this case the wake event is wake83. When the system goes to
+suspend state, the BPMP UART reports enabled masks of the wake events in the
+log. Verify that in this log bit 83 is set, both in the wake mask and in the
+Tier2 routing mask. For example:
+
+    WAKE_MASK[95:64] = 0x1ff200
+    TIER2[95:64] = 0xff200
+
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/compile-flash.md b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/compile-flash.md
new file mode 100644
index 0000000..e5b4dc5
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/compile-flash.md
@@ -0,0 +1,96 @@
+Compiling and Flashing {#rt-compiling}
+======================
+
+@tableofcontents
+
+This Document describes the steps to build and flash this project
+
+# TOOLCHAIN PREREQUISITE#
+
+You must download the external Toolchain. NVIDIA does not distribute this toolchain.
+
+arm-gnu-toolchain-13.2.rel1 (x86_64 Linux host):
+
+https://developer.arm.com/-/media/Files/downloads/gnu/13.2.rel1/binrel/arm-gnu-toolchain-13.2.rel1-x86_64-arm-none-eabi.tar.xz?rev=e434b9ea4afc4ed7998329566b764309&hash=CA590209F5774EE1C96E6450E14A3E26
+
+# BUILD
+
+Set the appropriate paths for the below variables:
+```
+export SPE_FREERTOS_BSP=<path to root directory where rt-aux-cpu-demo-fsp, fsp and freertos source directories reside>
+export CROSS_COMPILE=<path to installed cross compiler>/bin/arm-none-eabi-
+
+cd ${SPE_FREERTOS_BSP}/rt-aux-cpu-demo-fsp
+```
+
+## To build firmware for a specific platform
+
+Build firmware for t23x:
+```
+make bin_t23x
+```
+@note Build speed is significantly faster by using the `-j <jobs>` option with `make`.
+For example, `make -j16 bin_t23x`.
+
+## To build doxygen documents
+
+Make sure you have doxygen installed on your computer. For Ubuntu systems:
+```
+sudo apt-get install doxygen
+```
+To generate the documents:
+```
+make docs
+```
+The output can be found at `out/docs`.
+
+## To build everything
+
+```
+make
+```
+or
+```
+make all
+```
+The above commands build all the targets i.e. spe firmware binaries for all the
+SOCs and Doxygen documents.
+
+## Build artifacts
+
+The built SPE firmware binary can be found at `out/<soc>/spe.bin`.
+The doxygen build generates `out/docs/index.html` file. Open it
+using a browser to navigate the documentation.
+
+## To clean the build artifacts
+Clean everything (documentation and firmware):
+```
+	make clean
+```
+To clean t23x only firmware objects and build artifacts:
+```
+	make clean_t23x
+```
+To clean only doxygen generated files:
+```
+	make clean_docs
+```
+
+# FLASH
+
+1. Back up the original `spe_t234.bin` located in the
+following directory:
+```
+    Linux_for_Tegra/bootloader/
+```
+2. Copy the generated `out/<soc>/spe.bin` to the following locating, depending on your target.
+   - For the T234 SoC, copy it to:
+```
+         Linux_for_Tegra/bootloader/spe_t234.bin
+```
+   The `Linux_for_Tegra` directory is part of the extracted L4T build that
+   you used to flash the Jetson device.
+3. Use the command below to just flash only the spe-fw partition:
+```
+       sudo ./flash.sh -k A_spe-fw <T234 SoC based Jetson platforms> internal
+```
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/doxyfile b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/doxyfile
new file mode 100644
index 0000000..390eacd
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/doxyfile
@@ -0,0 +1,2485 @@
+# Doxyfile 1.8.14
+
+# This file describes the settings to be used by the documentation system
+# doxygen (www.doxygen.org) for a project.
+#
+# All text after a double hash (##) is considered a comment and is placed in
+# front of the TAG it is preceding.
+#
+# All text after a single hash (#) is considered a comment and will be ignored.
+# The format is:
+# TAG = value [value, ...]
+# For lists, items can also be appended using:
+# TAG += value [value, ...]
+# Values that contain spaces should be placed between quotes (\" \").
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+
+# This tag specifies the encoding used for all characters in the config file
+# that follow. The default is UTF-8 which is also the encoding used for all text
+# before the first occurrence of this tag. Doxygen uses libiconv (or the iconv
+# built into libc) for the transcoding. See
+# https://www.gnu.org/software/libiconv/ for the list of possible encodings.
+# The default value is: UTF-8.
+
+DOXYFILE_ENCODING      = UTF-8
+
+# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by
+# double-quotes, unless you are using Doxywizard) that should identify the
+# project for which the documentation is generated. This name is used in the
+# title of most generated pages and in a few other places.
+# The default value is: My Project.
+
+PROJECT_NAME           = "Jetson Sensor Processing Engine (SPE) Developer Guide"
+
+# The PROJECT_NUMBER tag can be used to enter a project or revision number. This
+# could be handy for archiving the generated documentation or if some version
+# control system is used.
+
+PROJECT_NUMBER         = r32.2
+
+# Using the PROJECT_BRIEF tag one can provide an optional one line description
+# for a project that appears at the top of each page and should give viewer a
+# quick idea about the purpose of the project. Keep the description short.
+
+PROJECT_BRIEF          =
+
+# With the PROJECT_LOGO tag one can specify a logo or an icon that is included
+# in the documentation. The maximum height of the logo should not exceed 55
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+
+PROJECT_LOGO           =
+
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path
+# into which the generated documentation will be written. If a relative path is
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+
+OUTPUT_DIRECTORY       = $(OUTDIR)
+
+# If the CREATE_SUBDIRS tag is set to YES then doxygen will create 4096 sub-
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+# putting all generated files in the same directory would otherwise causes
+# performance problems for the file system.
+# The default value is: NO.
+
+CREATE_SUBDIRS         = NO
+
+# If the ALLOW_UNICODE_NAMES tag is set to YES, doxygen will allow non-ASCII
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+# characters will be escaped, for example _xE3_x81_x84 will be used for Unicode
+# U+3044.
+# The default value is: NO.
+
+ALLOW_UNICODE_NAMES    = NO
+
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all
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+# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Catalan, Chinese,
+# Chinese-Traditional, Croatian, Czech, Danish, Dutch, English (United States),
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+# The default value is: English.
+
+OUTPUT_LANGUAGE        = English
+
+# If the BRIEF_MEMBER_DESC tag is set to YES, doxygen will include brief member
+# descriptions after the members that are listed in the file and class
+# documentation (similar to Javadoc). Set to NO to disable this.
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+BRIEF_MEMBER_DESC      = YES
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+# If the REPEAT_BRIEF tag is set to YES, doxygen will prepend the brief
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+
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+FULL_PATH_NAMES        = YES
+
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+# Note that you can specify absolute paths here, but also relative paths, which
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+# This tag requires that the tag FULL_PATH_NAMES is set to YES.
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+STRIP_FROM_PATH        =  C:/Users/kstone/git/vendor/nvidia/tegra \
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+
+# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first
+# line (until the first dot) of a Qt-style comment as the brief description. If
+# set to NO, the Qt-style will behave just like regular Qt-style comments (thus
+# requiring an explicit \brief command for a brief description.)
+# The default value is: NO.
+
+QT_AUTOBRIEF           = YES
+
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a
+# multi-line C++ special comment block (i.e. a block of //! or /// comments) as
+# a brief description. This used to be the default behavior. The new default is
+# to treat a multi-line C++ comment block as a detailed description. Set this
+# tag to YES if you prefer the old behavior instead.
+#
+# Note that setting this tag to YES also means that rational rose comments are
+# not recognized any more.
+# The default value is: NO.
+
+MULTILINE_CPP_IS_BRIEF = NO
+
+# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the
+# documentation from any documented member that it re-implements.
+# The default value is: YES.
+
+INHERIT_DOCS           = YES
+
+# If the SEPARATE_MEMBER_PAGES tag is set to YES then doxygen will produce a new
+# page for each member. If set to NO, the documentation of a member will be part
+# of the file/class/namespace that contains it.
+# The default value is: NO.
+
+SEPARATE_MEMBER_PAGES  = NO
+
+# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen
+# uses this value to replace tabs by spaces in code fragments.
+# Minimum value: 1, maximum value: 16, default value: 4.
+
+TAB_SIZE               = 4
+
+# This tag can be used to specify a number of aliases that act as commands in
+# the documentation. An alias has the form:
+# name=value
+# For example adding
+# "sideeffect=@par Side Effects:\n"
+# will allow you to put the command \sideeffect (or @sideeffect) in the
+# documentation, which will result in a user-defined paragraph with heading
+# "Side Effects:". You can put \n's in the value part of an alias to insert
+# newlines (in the resulting output). You can put ^^ in the value part of an
+# alias to insert a newline as if a physical newline was in the original file.
+
+ALIASES                =
+
+# This tag can be used to specify a number of word-keyword mappings (TCL only).
+# A mapping has the form "name=value". For example adding "class=itcl::class"
+# will allow you to use the command class in the itcl::class meaning.
+
+TCL_SUBST              =
+
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources
+# only. Doxygen will then generate output that is more tailored for C. For
+# instance, some of the names that are used will be different. The list of all
+# members will be omitted, etc.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_FOR_C  = YES
+
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or
+# Python sources only. Doxygen will then generate output that is more tailored
+# for that language. For instance, namespaces will be presented as packages,
+# qualified scopes will look different, etc.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_JAVA   = NO
+
+# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran
+# sources. Doxygen will then generate output that is tailored for Fortran.
+# The default value is: NO.
+
+OPTIMIZE_FOR_FORTRAN   = NO
+
+# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
+# sources. Doxygen will then generate output that is tailored for VHDL.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_VHDL   = NO
+
+# Doxygen selects the parser to use depending on the extension of the files it
+# parses. With this tag you can assign which parser to use for a given
+# extension. Doxygen has a built-in mapping, but you can override or extend it
+# using this tag. The format is ext=language, where ext is a file extension, and
+# language is one of the parsers supported by doxygen: IDL, Java, Javascript,
+# C#, C, C++, D, PHP, Objective-C, Python, Fortran (fixed format Fortran:
+# FortranFixed, free formatted Fortran: FortranFree, unknown formatted Fortran:
+# Fortran. In the later case the parser tries to guess whether the code is fixed
+# or free formatted code, this is the default for Fortran type files), VHDL. For
+# instance to make doxygen treat .inc files as Fortran files (default is PHP),
+# and .f files as C (default is Fortran), use: inc=Fortran f=C.
+#
+# Note: For files without extension you can use no_extension as a placeholder.
+#
+# Note that for custom extensions you also need to set FILE_PATTERNS otherwise
+# the files are not read by doxygen.
+
+EXTENSION_MAPPING      =
+
+# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments
+# according to the Markdown format, which allows for more readable
+# documentation. See http://daringfireball.net/projects/markdown/ for details.
+# The output of markdown processing is further processed by doxygen, so you can
+# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in
+# case of backward compatibilities issues.
+# The default value is: YES.
+
+MARKDOWN_SUPPORT       = YES
+
+# When the TOC_INCLUDE_HEADINGS tag is set to a non-zero value, all headings up
+# to that level are automatically included in the table of contents, even if
+# they do not have an id attribute.
+# Note: This feature currently applies only to Markdown headings.
+# Minimum value: 0, maximum value: 99, default value: 0.
+# This tag requires that the tag MARKDOWN_SUPPORT is set to YES.
+
+TOC_INCLUDE_HEADINGS   = 3
+
+# When enabled doxygen tries to link words that correspond to documented
+# classes, or namespaces to their corresponding documentation. Such a link can
+# be prevented in individual cases by putting a % sign in front of the word or
+# globally by setting AUTOLINK_SUPPORT to NO.
+# The default value is: YES.
+
+AUTOLINK_SUPPORT       = YES
+
+# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
+# to include (a tag file for) the STL sources as input, then you should set this
+# tag to YES in order to let doxygen match functions declarations and
+# definitions whose arguments contain STL classes (e.g. func(std::string);
+# versus func(std::string) {}). This also make the inheritance and collaboration
+# diagrams that involve STL classes more complete and accurate.
+# The default value is: NO.
+
+BUILTIN_STL_SUPPORT    = NO
+
+# If you use Microsoft's C++/CLI language, you should set this option to YES to
+# enable parsing support.
+# The default value is: NO.
+
+CPP_CLI_SUPPORT        = NO
+
+# Set the SIP_SUPPORT tag to YES if your project consists of sip (see:
+# https://www.riverbankcomputing.com/software/sip/intro) sources only. Doxygen
+# will parse them like normal C++ but will assume all classes use public instead
+# of private inheritance when no explicit protection keyword is present.
+# The default value is: NO.
+
+SIP_SUPPORT            = NO
+
+# For Microsoft's IDL there are propget and propput attributes to indicate
+# getter and setter methods for a property. Setting this option to YES will make
+# doxygen to replace the get and set methods by a property in the documentation.
+# This will only work if the methods are indeed getting or setting a simple
+# type. If this is not the case, or you want to show the methods anyway, you
+# should set this option to NO.
+# The default value is: YES.
+
+IDL_PROPERTY_SUPPORT   = NO
+
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
+# tag is set to YES then doxygen will reuse the documentation of the first
+# member in the group (if any) for the other members of the group. By default
+# all members of a group must be documented explicitly.
+# The default value is: NO.
+
+DISTRIBUTE_GROUP_DOC   = NO
+
+# If one adds a struct or class to a group and this option is enabled, then also
+# any nested class or struct is added to the same group. By default this option
+# is disabled and one has to add nested compounds explicitly via \ingroup.
+# The default value is: NO.
+
+GROUP_NESTED_COMPOUNDS = NO
+
+# Set the SUBGROUPING tag to YES to allow class member groups of the same type
+# (for instance a group of public functions) to be put as a subgroup of that
+# type (e.g. under the Public Functions section). Set it to NO to prevent
+# subgrouping. Alternatively, this can be done per class using the
+# \nosubgrouping command.
+# The default value is: YES.
+
+SUBGROUPING            = YES
+
+# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions
+# are shown inside the group in which they are included (e.g. using \ingroup)
+# instead of on a separate page (for HTML and Man pages) or section (for LaTeX
+# and RTF).
+#
+# Note that this feature does not work in combination with
+# SEPARATE_MEMBER_PAGES.
+# The default value is: NO.
+
+INLINE_GROUPED_CLASSES = NO
+
+# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions
+# with only public data fields or simple typedef fields will be shown inline in
+# the documentation of the scope in which they are defined (i.e. file,
+# namespace, or group documentation), provided this scope is documented. If set
+# to NO, structs, classes, and unions are shown on a separate page (for HTML and
+# Man pages) or section (for LaTeX and RTF).
+# The default value is: NO.
+
+INLINE_SIMPLE_STRUCTS  = NO
+
+# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or
+# enum is documented as struct, union, or enum with the name of the typedef. So
+# typedef struct TypeS {} TypeT, will appear in the documentation as a struct
+# with name TypeT. When disabled the typedef will appear as a member of a file,
+# namespace, or class. And the struct will be named TypeS. This can typically be
+# useful for C code in case the coding convention dictates that all compound
+# types are typedef'ed and only the typedef is referenced, never the tag name.
+# The default value is: NO.
+
+TYPEDEF_HIDES_STRUCT   = NO
+
+# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This
+# cache is used to resolve symbols given their name and scope. Since this can be
+# an expensive process and often the same symbol appears multiple times in the
+# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small
+# doxygen will become slower. If the cache is too large, memory is wasted. The
+# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range
+# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536
+# symbols. At the end of a run doxygen will report the cache usage and suggest
+# the optimal cache size from a speed point of view.
+# Minimum value: 0, maximum value: 9, default value: 0.
+
+LOOKUP_CACHE_SIZE      = 0
+
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+
+# If the EXTRACT_ALL tag is set to YES, doxygen will assume all entities in
+# documentation are documented, even if no documentation was available. Private
+# class members and static file members will be hidden unless the
+# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.
+# Note: This will also disable the warnings about undocumented members that are
+# normally produced when WARNINGS is set to YES.
+# The default value is: NO.
+
+EXTRACT_ALL            = YES
+
+# If the EXTRACT_PRIVATE tag is set to YES, all private members of a class will
+# be included in the documentation.
+# The default value is: NO.
+
+EXTRACT_PRIVATE        = NO
+
+# If the EXTRACT_PACKAGE tag is set to YES, all members with package or internal
+# scope will be included in the documentation.
+# The default value is: NO.
+
+EXTRACT_PACKAGE        = NO
+
+# If the EXTRACT_STATIC tag is set to YES, all static members of a file will be
+# included in the documentation.
+# The default value is: NO.
+
+EXTRACT_STATIC         = YES
+
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES, classes (and structs) defined
+# locally in source files will be included in the documentation. If set to NO,
+# only classes defined in header files are included. Does not have any effect
+# for Java sources.
+# The default value is: YES.
+
+EXTRACT_LOCAL_CLASSES  = NO
+
+# This flag is only useful for Objective-C code. If set to YES, local methods,
+# which are defined in the implementation section but not in the interface are
+# included in the documentation. If set to NO, only methods in the interface are
+# included.
+# The default value is: NO.
+
+EXTRACT_LOCAL_METHODS  = NO
+
+# If this flag is set to YES, the members of anonymous namespaces will be
+# extracted and appear in the documentation as a namespace called
+# 'anonymous_namespace{file}', where file will be replaced with the base name of
+# the file that contains the anonymous namespace. By default anonymous namespace
+# are hidden.
+# The default value is: NO.
+
+EXTRACT_ANON_NSPACES   = NO
+
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all
+# undocumented members inside documented classes or files. If set to NO these
+# members will be included in the various overviews, but no documentation
+# section is generated. This option has no effect if EXTRACT_ALL is enabled.
+# The default value is: NO.
+
+HIDE_UNDOC_MEMBERS     = NO
+
+# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all
+# undocumented classes that are normally visible in the class hierarchy. If set
+# to NO, these classes will be included in the various overviews. This option
+# has no effect if EXTRACT_ALL is enabled.
+# The default value is: NO.
+
+HIDE_UNDOC_CLASSES     = NO
+
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend
+# (class|struct|union) declarations. If set to NO, these declarations will be
+# included in the documentation.
+# The default value is: NO.
+
+HIDE_FRIEND_COMPOUNDS  = NO
+
+# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any
+# documentation blocks found inside the body of a function. If set to NO, these
+# blocks will be appended to the function's detailed documentation block.
+# The default value is: NO.
+
+HIDE_IN_BODY_DOCS      = NO
+
+# The INTERNAL_DOCS tag determines if documentation that is typed after a
+# \internal command is included. If the tag is set to NO then the documentation
+# will be excluded. Set it to YES to include the internal documentation.
+# The default value is: NO.
+
+INTERNAL_DOCS          = NO
+
+# If the CASE_SENSE_NAMES tag is set to NO then doxygen will only generate file
+# names in lower-case letters. If set to YES, upper-case letters are also
+# allowed. This is useful if you have classes or files whose names only differ
+# in case and if your file system supports case sensitive file names. Windows
+# and Mac users are advised to set this option to NO.
+# The default value is: system dependent.
+
+CASE_SENSE_NAMES       = YES
+
+# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with
+# their full class and namespace scopes in the documentation. If set to YES, the
+# scope will be hidden.
+# The default value is: NO.
+
+HIDE_SCOPE_NAMES       = NO
+
+# If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then doxygen will
+# append additional text to a page's title, such as Class Reference. If set to
+# YES the compound reference will be hidden.
+# The default value is: NO.
+
+HIDE_COMPOUND_REFERENCE= NO
+
+# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of
+# the files that are included by a file in the documentation of that file.
+# The default value is: YES.
+
+SHOW_INCLUDE_FILES     = NO
+
+# If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each
+# grouped member an include statement to the documentation, telling the reader
+# which file to include in order to use the member.
+# The default value is: NO.
+
+SHOW_GROUPED_MEMB_INC  = NO
+
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include
+# files with double quotes in the documentation rather than with sharp brackets.
+# The default value is: NO.
+
+FORCE_LOCAL_INCLUDES   = NO
+
+# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the
+# documentation for inline members.
+# The default value is: YES.
+
+INLINE_INFO            = YES
+
+# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the
+# (detailed) documentation of file and class members alphabetically by member
+# name. If set to NO, the members will appear in declaration order.
+# The default value is: YES.
+
+SORT_MEMBER_DOCS       = NO
+
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief
+# descriptions of file, namespace and class members alphabetically by member
+# name. If set to NO, the members will appear in declaration order. Note that
+# this will also influence the order of the classes in the class list.
+# The default value is: NO.
+
+SORT_BRIEF_DOCS        = NO
+
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the
+# (brief and detailed) documentation of class members so that constructors and
+# destructors are listed first. If set to NO the constructors will appear in the
+# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.
+# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief
+# member documentation.
+# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting
+# detailed member documentation.
+# The default value is: NO.
+
+SORT_MEMBERS_CTORS_1ST = NO
+
+# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy
+# of group names into alphabetical order. If set to NO the group names will
+# appear in their defined order.
+# The default value is: NO.
+
+SORT_GROUP_NAMES       = YES
+
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by
+# fully-qualified names, including namespaces. If set to NO, the class list will
+# be sorted only by class name, not including the namespace part.
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
+# Note: This option applies only to the class list, not to the alphabetical
+# list.
+# The default value is: NO.
+
+SORT_BY_SCOPE_NAME     = NO
+
+# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper
+# type resolution of all parameters of a function it will reject a match between
+# the prototype and the implementation of a member function even if there is
+# only one candidate or it is obvious which candidate to choose by doing a
+# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still
+# accept a match between prototype and implementation in such cases.
+# The default value is: NO.
+
+STRICT_PROTO_MATCHING  = NO
+
+# The GENERATE_TODOLIST tag can be used to enable (YES) or disable (NO) the todo
+# list. This list is created by putting \todo commands in the documentation.
+# The default value is: YES.
+
+GENERATE_TODOLIST      = NO
+
+# The GENERATE_TESTLIST tag can be used to enable (YES) or disable (NO) the test
+# list. This list is created by putting \test commands in the documentation.
+# The default value is: YES.
+
+GENERATE_TESTLIST      = NO
+
+# The GENERATE_BUGLIST tag can be used to enable (YES) or disable (NO) the bug
+# list. This list is created by putting \bug commands in the documentation.
+# The default value is: YES.
+
+GENERATE_BUGLIST       = NO
+
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or disable (NO)
+# the deprecated list. This list is created by putting \deprecated commands in
+# the documentation.
+# The default value is: YES.
+
+GENERATE_DEPRECATEDLIST= YES
+
+# The ENABLED_SECTIONS tag can be used to enable conditional documentation
+# sections, marked by \if <section_label> ... \endif and \cond <section_label>
+# ... \endcond blocks.
+
+ENABLED_SECTIONS       =
+
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the
+# initial value of a variable or macro / define can have for it to appear in the
+# documentation. If the initializer consists of more lines than specified here
+# it will be hidden. Use a value of 0 to hide initializers completely. The
+# appearance of the value of individual variables and macros / defines can be
+# controlled using \showinitializer or \hideinitializer command in the
+# documentation regardless of this setting.
+# Minimum value: 0, maximum value: 10000, default value: 30.
+
+MAX_INITIALIZER_LINES  = 30
+
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at
+# the bottom of the documentation of classes and structs. If set to YES, the
+# list will mention the files that were used to generate the documentation.
+# The default value is: YES.
+
+SHOW_USED_FILES        = YES
+
+# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This
+# will remove the Files entry from the Quick Index and from the Folder Tree View
+# (if specified).
+# The default value is: YES.
+
+SHOW_FILES             = YES
+
+# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces
+# page. This will remove the Namespaces entry from the Quick Index and from the
+# Folder Tree View (if specified).
+# The default value is: YES.
+
+SHOW_NAMESPACES        = NO
+
+# The FILE_VERSION_FILTER tag can be used to specify a program or script that
+# doxygen should invoke to get the current version for each file (typically from
+# the version control system). Doxygen will invoke the program by executing (via
+# popen()) the command command input-file, where command is the value of the
+# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided
+# by doxygen. Whatever the program writes to standard output is used as the file
+# version. For an example see the documentation.
+
+FILE_VERSION_FILTER    =
+
+# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed
+# by doxygen. The layout file controls the global structure of the generated
+# output files in an output format independent way. To create the layout file
+# that represents doxygen's defaults, run doxygen with the -l option. You can
+# optionally specify a file name after the option, if omitted DoxygenLayout.xml
+# will be used as the name of the layout file.
+#
+# Note that if you run doxygen from a directory containing a file called
+# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE
+# tag is left empty.
+
+LAYOUT_FILE            =
+
+# The CITE_BIB_FILES tag can be used to specify one or more bib files containing
+# the reference definitions. This must be a list of .bib files. The .bib
+# extension is automatically appended if omitted. This requires the bibtex tool
+# to be installed. See also https://en.wikipedia.org/wiki/BibTeX for more info.
+# For LaTeX the style of the bibliography can be controlled using
+# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the
+# search path. See also \cite for info how to create references.
+
+CITE_BIB_FILES         =
+
+#---------------------------------------------------------------------------
+# Configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+
+# The QUIET tag can be used to turn on/off the messages that are generated to
+# standard output by doxygen. If QUIET is set to YES this implies that the
+# messages are off.
+# The default value is: NO.
+
+QUIET                  = NO
+
+# The WARNINGS tag can be used to turn on/off the warning messages that are
+# generated to standard error (stderr) by doxygen. If WARNINGS is set to YES
+# this implies that the warnings are on.
+#
+# Tip: Turn warnings on while writing the documentation.
+# The default value is: YES.
+
+WARNINGS               = YES
+
+# If the WARN_IF_UNDOCUMENTED tag is set to YES then doxygen will generate
+# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag
+# will automatically be disabled.
+# The default value is: YES.
+
+WARN_IF_UNDOCUMENTED   = YES
+
+# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for
+# potential errors in the documentation, such as not documenting some parameters
+# in a documented function, or documenting parameters that don't exist or using
+# markup commands wrongly.
+# The default value is: YES.
+
+WARN_IF_DOC_ERROR      = YES
+
+# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that
+# are documented, but have no documentation for their parameters or return
+# value. If set to NO, doxygen will only warn about wrong or incomplete
+# parameter documentation, but not about the absence of documentation.
+# The default value is: NO.
+
+WARN_NO_PARAMDOC       = YES
+
+# If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when
+# a warning is encountered.
+# The default value is: NO.
+
+WARN_AS_ERROR          = NO
+
+# The WARN_FORMAT tag determines the format of the warning messages that doxygen
+# can produce. The string should contain the $file, $line, and $text tags, which
+# will be replaced by the file and line number from which the warning originated
+# and the warning text. Optionally the format may contain $version, which will
+# be replaced by the version of the file (if it could be obtained via
+# FILE_VERSION_FILTER)
+# The default value is: $file:$line: $text.
+
+WARN_FORMAT            = "$file:$line: $text"
+
+# The WARN_LOGFILE tag can be used to specify a file to which warning and error
+# messages should be written. If left blank the output is written to standard
+# error (stderr).
+
+WARN_LOGFILE           =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the input files
+#---------------------------------------------------------------------------
+
+# The INPUT tag is used to specify the files and/or directories that contain
+# documented source files. You may enter file names like myfile.cpp or
+# directories like /usr/src/myproject. Separate the files or directories with
+# spaces. See also FILE_PATTERNS and EXTENSION_MAPPING
+# Note: If this tag is empty the current directory is searched.
+
+INPUT                  = ./doc/welcome.md \
+                         ./doc/fsp.md \
+                         ./doc/compile-flash.md \
+                         ./doc/aodmic-app.md \
+                         ./doc/ivc.md \
+                         ./doc/gte-app.md \
+                         ./doc/gpio.md \
+                         ./doc/i2c-app.md \
+                         ./doc/spi-app.md \
+                         ./doc/timer-app.md \
+                         ./doc/faq.md \
+                         ./doc/third_party_legal.md \
+                         ./doc/nvidia_legal.md \
+
+
+# This tag can be used to specify the character encoding of the source files
+# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses
+# libiconv (or the iconv built into libc) for the transcoding. See the libiconv
+# documentation (see: https://www.gnu.org/software/libiconv/) for the list of
+# possible encodings.
+# The default value is: UTF-8.
+
+INPUT_ENCODING         = UTF-8
+
+# If the value of the INPUT tag contains directories, you can use the
+# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and
+# *.h) to filter out the source-files in the directories.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# read by doxygen.
+#
+# If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp,
+# *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h,
+# *.hh, *.hxx, *.hpp, *.h++, *.cs, *.d, *.php, *.php4, *.php5, *.phtml, *.inc,
+# *.m, *.markdown, *.md, *.mm, *.dox, *.py, *.pyw, *.f90, *.f95, *.f03, *.f08,
+# *.f, *.for, *.tcl, *.vhd, *.vhdl, *.ucf and *.qsf.
+
+FILE_PATTERNS          =
+
+# The RECURSIVE tag can be used to specify whether or not subdirectories should
+# be searched for input files as well.
+# The default value is: NO.
+
+RECURSIVE              = NO
+
+# The EXCLUDE tag can be used to specify files and/or directories that should be
+# excluded from the INPUT source files. This way you can easily exclude a
+# subdirectory from a directory tree whose root is specified with the INPUT tag.
+#
+# Note that relative paths are relative to the directory from which doxygen is
+# run.
+
+EXCLUDE                =
+
+# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or
+# directories that are symbolic links (a Unix file system feature) are excluded
+# from the input.
+# The default value is: NO.
+
+EXCLUDE_SYMLINKS       = NO
+
+# If the value of the INPUT tag contains directories, you can use the
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
+# certain files from those directories.
+#
+# Note that the wildcards are matched against the file with absolute path, so to
+# exclude all test directories for example use the pattern */test/*
+
+EXCLUDE_PATTERNS       =
+
+# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
+# (namespaces, classes, functions, etc.) that should be excluded from the
+# output. The symbol name can be a fully qualified name, a word, or if the
+# wildcard * is used, a substring. Examples: ANamespace, AClass,
+# AClass::ANamespace, ANamespace::*Test
+#
+# Note that the wildcards are matched against the file with absolute path, so to
+# exclude all test directories use the pattern */test/*
+
+EXCLUDE_SYMBOLS        =
+
+# The EXAMPLE_PATH tag can be used to specify one or more files or directories
+# that contain example code fragments that are included (see the \include
+# command).
+
+EXAMPLE_PATH           =
+
+
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and
+# *.h) to filter out the source-files in the directories. If left blank all
+# files are included.
+
+EXAMPLE_PATTERNS       =
+
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
+# searched for input files to be used with the \include or \dontinclude commands
+# irrespective of the value of the RECURSIVE tag.
+# The default value is: NO.
+
+EXAMPLE_RECURSIVE      = YES
+
+# The IMAGE_PATH tag can be used to specify one or more files or directories
+# that contain images that are to be included in the documentation (see the
+# \image command).
+
+IMAGE_PATH             = ./doc/nvimages
+
+
+# The INPUT_FILTER tag can be used to specify a program that doxygen should
+# invoke to filter for each input file. Doxygen will invoke the filter program
+# by executing (via popen()) the command:
+#
+# <filter> <input-file>
+#
+# where <filter> is the value of the INPUT_FILTER tag, and <input-file> is the
+# name of an input file. Doxygen will then use the output that the filter
+# program writes to standard output. If FILTER_PATTERNS is specified, this tag
+# will be ignored.
+#
+# Note that the filter must not add or remove lines; it is applied before the
+# code is scanned, but not when the output code is generated. If lines are added
+# or removed, the anchors will not be placed correctly.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# properly processed by doxygen.
+
+INPUT_FILTER           =
+
+# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
+# basis. Doxygen will compare the file name with each pattern and apply the
+# filter if there is a match. The filters are a list of the form: pattern=filter
+# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how
+# filters are used. If the FILTER_PATTERNS tag is empty or if none of the
+# patterns match the file name, INPUT_FILTER is applied.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# properly processed by doxygen.
+
+FILTER_PATTERNS        =
+
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
+# INPUT_FILTER) will also be used to filter the input files that are used for
+# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).
+# The default value is: NO.
+
+FILTER_SOURCE_FILES    = NO
+
+# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file
+# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and
+# it is also possible to disable source filtering for a specific pattern using
+# *.ext= (so without naming a filter).
+# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.
+
+FILTER_SOURCE_PATTERNS =
+
+# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that
+# is part of the input, its contents will be placed on the main page
+# (index.html). This can be useful if you have a project on for instance GitHub
+# and want to reuse the introduction page also for the doxygen output.
+
+USE_MDFILE_AS_MAINPAGE =
+
+#---------------------------------------------------------------------------
+# Configuration options related to source browsing
+#---------------------------------------------------------------------------
+
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will be
+# generated. Documented entities will be cross-referenced with these sources.
+#
+# Note: To get rid of all source code in the generated output, make sure that
+# also VERBATIM_HEADERS is set to NO.
+# The default value is: NO.
+
+SOURCE_BROWSER         = NO
+
+# Setting the INLINE_SOURCES tag to YES will include the body of functions,
+# classes and enums directly into the documentation.
+# The default value is: NO.
+
+INLINE_SOURCES         = NO
+
+# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any
+# special comment blocks from generated source code fragments. Normal C, C++ and
+# Fortran comments will always remain visible.
+# The default value is: YES.
+
+STRIP_CODE_COMMENTS    = YES
+
+# If the REFERENCED_BY_RELATION tag is set to YES then for each documented
+# function all documented functions referencing it will be listed.
+# The default value is: NO.
+
+REFERENCED_BY_RELATION = NO
+
+# If the REFERENCES_RELATION tag is set to YES then for each documented function
+# all documented entities called/used by that function will be listed.
+# The default value is: NO.
+
+REFERENCES_RELATION    = NO
+
+# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set
+# to YES then the hyperlinks from functions in REFERENCES_RELATION and
+# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will
+# link to the documentation.
+# The default value is: YES.
+
+REFERENCES_LINK_SOURCE = YES
+
+# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the
+# source code will show a tooltip with additional information such as prototype,
+# brief description and links to the definition and documentation. Since this
+# will make the HTML file larger and loading of large files a bit slower, you
+# can opt to disable this feature.
+# The default value is: YES.
+# This tag requires that the tag SOURCE_BROWSER is set to YES.
+
+SOURCE_TOOLTIPS        = YES
+
+# If the USE_HTAGS tag is set to YES then the references to source code will
+# point to the HTML generated by the htags(1) tool instead of doxygen built-in
+# source browser. The htags tool is part of GNU's global source tagging system
+# (see https://www.gnu.org/software/global/global.html). You will need version
+# 4.8.6 or higher.
+#
+# To use it do the following:
+# - Install the latest version of global
+# - Enable SOURCE_BROWSER and USE_HTAGS in the config file
+# - Make sure the INPUT points to the root of the source tree
+# - Run doxygen as normal
+#
+# Doxygen will invoke htags (and that will in turn invoke gtags), so these
+# tools must be available from the command line (i.e. in the search path).
+#
+# The result: instead of the source browser generated by doxygen, the links to
+# source code will now point to the output of htags.
+# The default value is: NO.
+# This tag requires that the tag SOURCE_BROWSER is set to YES.
+
+USE_HTAGS              = NO
+
+# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a
+# verbatim copy of the header file for each class for which an include is
+# specified. Set to NO to disable this.
+# See also: Section \class.
+# The default value is: YES.
+
+VERBATIM_HEADERS       = YES
+
+# If the CLANG_ASSISTED_PARSING tag is set to YES then doxygen will use the
+# clang parser (see: http://clang.llvm.org/) for more accurate parsing at the
+# cost of reduced performance. This can be particularly helpful with template
+# rich C++ code for which doxygen's built-in parser lacks the necessary type
+# information.
+# Note: The availability of this option depends on whether or not doxygen was
+# generated with the -Duse-libclang=ON option for CMake.
+# The default value is: NO.
+
+CLANG_ASSISTED_PARSING = NO
+
+# If clang assisted parsing is enabled you can provide the compiler with command
+# line options that you would normally use when invoking the compiler. Note that
+# the include paths will already be set by doxygen for the files and directories
+# specified with INPUT and INCLUDE_PATH.
+# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES.
+
+CLANG_OPTIONS          =
+
+# If clang assisted parsing is enabled you can provide the clang parser with the
+# path to the compilation database (see:
+# http://clang.llvm.org/docs/HowToSetupToolingForLLVM.html) used when the files
+# were built. This is equivalent to specifying the "-p" option to a clang tool,
+# such as clang-check. These options will then be passed to the parser.
+# Note: The availability of this option depends on whether or not doxygen was
+# generated with the -Duse-libclang=ON option for CMake.
+# The default value is: 0.
+
+CLANG_COMPILATION_DATABASE_PATH                                        = 0
+
+#---------------------------------------------------------------------------
+# Configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all
+# compounds will be generated. Enable this if the project contains a lot of
+# classes, structs, unions or interfaces.
+# The default value is: YES.
+
+ALPHABETICAL_INDEX     = YES
+
+# The COLS_IN_ALPHA_INDEX tag can be used to specify the number of columns in
+# which the alphabetical index list will be split.
+# Minimum value: 1, maximum value: 20, default value: 5.
+# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.
+
+COLS_IN_ALPHA_INDEX    = 5
+
+# In case all classes in a project start with a common prefix, all classes will
+# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag
+# can be used to specify a prefix (or a list of prefixes) that should be ignored
+# while generating the index headers.
+# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.
+
+IGNORE_PREFIX          =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the HTML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_HTML tag is set to YES, doxygen will generate HTML output
+# The default value is: YES.
+
+GENERATE_HTML          = YES
+
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: html.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_OUTPUT            = docs
+
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each
+# generated HTML page (for example: .htm, .php, .asp).
+# The default value is: .html.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_FILE_EXTENSION    = .html
+
+# The HTML_HEADER tag can be used to specify a user-defined HTML header file for
+# each generated HTML page. If the tag is left blank doxygen will generate a
+# standard header.
+#
+# To get valid HTML the header file that includes any scripts and style sheets
+# that doxygen needs, which is dependent on the configuration options used (e.g.
+# the setting GENERATE_TREEVIEW). It is highly recommended to start with a
+# default header using
+# doxygen -w html new_header.html new_footer.html new_stylesheet.css
+# YourConfigFile
+# and then modify the file new_header.html. See also section "Doxygen usage"
+# for information on how to generate the default header that doxygen normally
+# uses.
+# Note: The header is subject to change so you typically have to regenerate the
+# default header when upgrading to a newer version of doxygen. For a description
+# of the possible markers and block names see the documentation.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_HEADER            = ./doc/nv_header.html
+
+# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each
+# generated HTML page. If the tag is left blank doxygen will generate a standard
+# footer. See HTML_HEADER for more information on how to generate a default
+# footer and what special commands can be used inside the footer. See also
+# section "Doxygen usage" for information on how to generate the default footer
+# that doxygen normally uses.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_FOOTER            = ./doc/footer.html
+
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style
+# sheet that is used by each HTML page. It can be used to fine-tune the look of
+# the HTML output. If left blank doxygen will generate a default style sheet.
+# See also section "Doxygen usage" for information on how to generate the style
+# sheet that doxygen normally uses.
+# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as
+# it is more robust and this tag (HTML_STYLESHEET) will in the future become
+# obsolete.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_STYLESHEET        = ./doc/nv.css
+
+# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined
+# cascading style sheets that are included after the standard style sheets
+# created by doxygen. Using this option one can overrule certain style aspects.
+# This is preferred over using HTML_STYLESHEET since it does not replace the
+# standard style sheet and is therefore more robust against future updates.
+# Doxygen will copy the style sheet files to the output directory.
+# Note: The order of the extra style sheet files is of importance (e.g. the last
+# style sheet in the list overrules the setting of the previous ones in the
+# list). For an example see the documentation.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_EXTRA_STYLESHEET  =
+
+# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or
+# other source files which should be copied to the HTML output directory. Note
+# that these files will be copied to the base HTML output directory. Use the
+# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these
+# files. In the HTML_STYLESHEET file, use the file name only. Also note that the
+# files will be copied as-is; there are no commands or markers available.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_EXTRA_FILES       = ./doc/nvimages/spe_fw_arch.png \
+                         ./doc/nvimages/confidential.png \
+                         ./doc/nvimages/Nvidia.ico \
+                         ./doc/nvimages/NVLogo_2D_H.jpg
+
+
+# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen
+# will adjust the colors in the style sheet and background images according to
+# this color. Hue is specified as an angle on a colorwheel, see
+# https://en.wikipedia.org/wiki/Hue for more information. For instance the value
+# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300
+# purple, and 360 is red again.
+# Minimum value: 0, maximum value: 359, default value: 220.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_HUE    = 220
+
+# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors
+# in the HTML output. For a value of 0 the output will use grayscales only. A
+# value of 255 will produce the most vivid colors.
+# Minimum value: 0, maximum value: 255, default value: 100.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_SAT    = 100
+
+# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the
+# luminance component of the colors in the HTML output. Values below 100
+# gradually make the output lighter, whereas values above 100 make the output
+# darker. The value divided by 100 is the actual gamma applied, so 80 represents
+# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not
+# change the gamma.
+# Minimum value: 40, maximum value: 240, default value: 80.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_GAMMA  = 80
+
+# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
+# page will contain the date and time when the page was generated. Setting this
+# to YES can help to show when doxygen was last run and thus if the
+# documentation is up to date.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_TIMESTAMP         = YES
+
+# If the HTML_DYNAMIC_MENUS tag is set to YES then the generated HTML
+# documentation will contain a main index with vertical navigation menus that
+# are dynamically created via Javascript. If disabled, the navigation index will
+# consists of multiple levels of tabs that are statically embedded in every HTML
+# page. Disable this option to support browsers that do not have Javascript,
+# like the Qt help browser.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_DYNAMIC_MENUS     = YES
+
+# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
+# documentation will contain sections that can be hidden and shown after the
+# page has loaded.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_DYNAMIC_SECTIONS  = NO
+
+# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries
+# shown in the various tree structured indices initially; the user can expand
+# and collapse entries dynamically later on. Doxygen will expand the tree to
+# such a level that at most the specified number of entries are visible (unless
+# a fully collapsed tree already exceeds this amount). So setting the number of
+# entries 1 will produce a full collapsed tree by default. 0 is a special value
+# representing an infinite number of entries and will result in a full expanded
+# tree by default.
+# Minimum value: 0, maximum value: 9999, default value: 100.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_INDEX_NUM_ENTRIES = 100
+
+# If the GENERATE_DOCSET tag is set to YES, additional index files will be
+# generated that can be used as input for Apple's Xcode 3 integrated development
+# environment (see: https://developer.apple.com/tools/xcode/), introduced with
+# OSX 10.5 (Leopard). To create a documentation set, doxygen will generate a
+# Makefile in the HTML output directory. Running make will produce the docset in
+# that directory and running make install will install the docset in
+# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at
+# startup. See https://developer.apple.com/tools/creatingdocsetswithdoxygen.html
+# for more information.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_DOCSET        = NO
+
+# This tag determines the name of the docset feed. A documentation feed provides
+# an umbrella under which multiple documentation sets from a single provider
+# (such as a company or product suite) can be grouped.
+# The default value is: Doxygen generated docs.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_FEEDNAME        = "Doxygen generated docs"
+
+# This tag specifies a string that should uniquely identify the documentation
+# set bundle. This should be a reverse domain-name style string, e.g.
+# com.mycompany.MyDocSet. Doxygen will append .docset to the name.
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_BUNDLE_ID       = org.doxygen.Project
+
+# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify
+# the documentation publisher. This should be a reverse domain-name style
+# string, e.g. com.mycompany.MyDocSet.documentation.
+# The default value is: org.doxygen.Publisher.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_PUBLISHER_ID    = org.doxygen.Publisher
+
+# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.
+# The default value is: Publisher.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_PUBLISHER_NAME  = Publisher
+
+# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three
+# additional HTML index files: index.hhp, index.hhc, and index.hhk. The
+# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop
+# (see: http://www.microsoft.com/en-us/download/details.aspx?id=21138) on
+# Windows.
+#
+# The HTML Help Workshop contains a compiler that can convert all HTML output
+# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML
+# files are now used as the Windows 98 help format, and will replace the old
+# Windows help format (.hlp) on all Windows platforms in the future. Compressed
+# HTML files also contain an index, a table of contents, and you can search for
+# words in the documentation. The HTML workshop also contains a viewer for
+# compressed HTML files.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_HTMLHELP      = NO
+
+# The CHM_FILE tag can be used to specify the file name of the resulting .chm
+# file. You can add a path in front of the file if the result should not be
+# written to the html output directory.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+CHM_FILE               =
+
+# The HHC_LOCATION tag can be used to specify the location (absolute path
+# including file name) of the HTML help compiler (hhc.exe). If non-empty,
+# doxygen will try to run the HTML help compiler on the generated index.hhp.
+# The file has to be specified with full path.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+HHC_LOCATION           =
+
+# The GENERATE_CHI flag controls if a separate .chi index file is generated
+# (YES) or that it should be included in the master .chm file (NO).
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+GENERATE_CHI           = NO
+
+# The CHM_INDEX_ENCODING is used to encode HtmlHelp index (hhk), content (hhc)
+# and project file content.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+CHM_INDEX_ENCODING     =
+
+# The BINARY_TOC flag controls whether a binary table of contents is generated
+# (YES) or a normal table of contents (NO) in the .chm file. Furthermore it
+# enables the Previous and Next buttons.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+BINARY_TOC             = NO
+
+# The TOC_EXPAND flag can be set to YES to add extra items for group members to
+# the table of contents of the HTML help documentation and to the tree view.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+TOC_EXPAND             = YES
+
+# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
+# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that
+# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help
+# (.qch) of the generated HTML documentation.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_QHP           = NO
+
+# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify
+# the file name of the resulting .qch file. The path specified is relative to
+# the HTML output folder.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QCH_FILE               =
+
+# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help
+# Project output. For more information please see Qt Help Project / Namespace
+# (see: http://doc.qt.io/qt-4.8/qthelpproject.html#namespace).
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_NAMESPACE          = org.doxygen.Project
+
+# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt
+# Help Project output. For more information please see Qt Help Project / Virtual
+# Folders (see: http://doc.qt.io/qt-4.8/qthelpproject.html#virtual-folders).
+# The default value is: doc.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_VIRTUAL_FOLDER     = doc
+
+# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom
+# filter to add. For more information please see Qt Help Project / Custom
+# Filters (see: http://doc.qt.io/qt-4.8/qthelpproject.html#custom-filters).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_CUST_FILTER_NAME   =
+
+# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the
+# custom filter to add. For more information please see Qt Help Project / Custom
+# Filters (see: http://doc.qt.io/qt-4.8/qthelpproject.html#custom-filters).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_CUST_FILTER_ATTRS  =
+
+# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this
+# project's filter section matches. Qt Help Project / Filter Attributes (see:
+# http://doc.qt.io/qt-4.8/qthelpproject.html#filter-attributes).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_SECT_FILTER_ATTRS  =
+
+# The QHG_LOCATION tag can be used to specify the location of Qt's
+# qhelpgenerator. If non-empty doxygen will try to run qhelpgenerator on the
+# generated .qhp file.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHG_LOCATION           =
+
+# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be
+# generated, together with the HTML files, they form an Eclipse help plugin. To
+# install this plugin and make it available under the help contents menu in
+# Eclipse, the contents of the directory containing the HTML and XML files needs
+# to be copied into the plugins directory of eclipse. The name of the directory
+# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.
+# After copying Eclipse needs to be restarted before the help appears.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_ECLIPSEHELP   = NO
+
+# A unique identifier for the Eclipse help plugin. When installing the plugin
+# the directory name containing the HTML and XML files should also have this
+# name. Each documentation set should have its own identifier.
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.
+
+ECLIPSE_DOC_ID         = org.doxygen.Project
+
+# If you want full control over the layout of the generated HTML pages it might
+# be necessary to disable the index and replace it with your own. The
+# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top
+# of each HTML page. A value of NO enables the index and the value YES disables
+# it. Since the tabs in the index contain the same information as the navigation
+# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+DISABLE_INDEX          = NO
+
+# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
+# structure should be generated to display hierarchical information. If the tag
+# value is set to YES, a side panel will be generated containing a tree-like
+# index structure (just like the one that is generated for HTML Help). For this
+# to work a browser that supports JavaScript, DHTML, CSS and frames is required
+# (i.e. any modern browser). Windows users are probably better off using the
+# HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can
+# further fine-tune the look of the index. As an example, the default style
+# sheet generated by doxygen has an example that shows how to put an image at
+# the root of the tree instead of the PROJECT_NAME. Since the tree basically has
+# the same information as the tab index, you could consider setting
+# DISABLE_INDEX to YES when enabling this option.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_TREEVIEW      = YES
+
+# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that
+# doxygen will group on one line in the generated HTML documentation.
+#
+# Note that a value of 0 will completely suppress the enum values from appearing
+# in the overview section.
+# Minimum value: 0, maximum value: 20, default value: 4.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+ENUM_VALUES_PER_LINE   = 4
+
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used
+# to set the initial width (in pixels) of the frame in which the tree is shown.
+# Minimum value: 0, maximum value: 1500, default value: 250.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+TREEVIEW_WIDTH         = 250
+
+# If the EXT_LINKS_IN_WINDOW option is set to YES, doxygen will open links to
+# external symbols imported via tag files in a separate window.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+EXT_LINKS_IN_WINDOW    = NO
+
+# Use this tag to change the font size of LaTeX formulas included as images in
+# the HTML documentation. When you change the font size after a successful
+# doxygen run you need to manually remove any form_*.png images from the HTML
+# output directory to force them to be regenerated.
+# Minimum value: 8, maximum value: 50, default value: 10.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+FORMULA_FONTSIZE       = 10
+
+# Use the FORMULA_TRANSPARENT tag to determine whether or not the images
+# generated for formulas are transparent PNGs. Transparent PNGs are not
+# supported properly for IE 6.0, but are supported on all modern browsers.
+#
+# Note that when changing this option you need to delete any form_*.png files in
+# the HTML output directory before the changes have effect.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+FORMULA_TRANSPARENT    = YES
+
+# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see
+# https://www.mathjax.org) which uses client side Javascript for the rendering
+# instead of using pre-rendered bitmaps. Use this if you do not have LaTeX
+# installed or if you want to formulas look prettier in the HTML output. When
+# enabled you may also need to install MathJax separately and configure the path
+# to it using the MATHJAX_RELPATH option.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+USE_MATHJAX            = YES
+
+# When MathJax is enabled you can set the default output format to be used for
+# the MathJax output. See the MathJax site (see:
+# http://docs.mathjax.org/en/latest/output.html) for more details.
+# Possible values are: HTML-CSS (which is slower, but has the best
+# compatibility), NativeMML (i.e. MathML) and SVG.
+# The default value is: HTML-CSS.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_FORMAT         = HTML-CSS
+
+# When MathJax is enabled you need to specify the location relative to the HTML
+# output directory using the MATHJAX_RELPATH option. The destination directory
+# should contain the MathJax.js script. For instance, if the mathjax directory
+# is located at the same level as the HTML output directory, then
+# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax
+# Content Delivery Network so you can quickly see the result without installing
+# MathJax. However, it is strongly recommended to install a local copy of
+# MathJax from https://www.mathjax.org before deployment.
+# The default value is: https://cdnjs.cloudflare.com/ajax/libs/mathjax/2.7.2/.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_RELPATH        = https://cdnjs.cloudflare.com/ajax/libs/mathjax/2.7.2/
+
+# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax
+# extension names that should be enabled during MathJax rendering. For example
+# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_EXTENSIONS     =
+
+# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces
+# of code that will be used on startup of the MathJax code. See the MathJax site
+# (see: http://docs.mathjax.org/en/latest/output.html) for more details. For an
+# example see the documentation.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_CODEFILE       =
+
+# When the SEARCHENGINE tag is enabled doxygen will generate a search box for
+# the HTML output. The underlying search engine uses javascript and DHTML and
+# should work on any modern browser. Note that when using HTML help
+# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)
+# there is already a search function so this one should typically be disabled.
+# For large projects the javascript based search engine can be slow, then
+# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to
+# search using the keyboard; to jump to the search box use <access key> + S
+# (what the <access key> is depends on the OS and browser, but it is typically
+# <CTRL>, <ALT>/<option>, or both). Inside the search box use the <cursor down
+# key> to jump into the search results window, the results can be navigated
+# using the <cursor keys>. Press <Enter> to select an item or <escape> to cancel
+# the search. The filter options can be selected when the cursor is inside the
+# search box by pressing <Shift>+<cursor down>. Also here use the <cursor keys>
+# to select a filter and <Enter> or <escape> to activate or cancel the filter
+# option.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+SEARCHENGINE           = YES
+
+# When the SERVER_BASED_SEARCH tag is enabled the search engine will be
+# implemented using a web server instead of a web client using Javascript. There
+# are two flavors of web server based searching depending on the EXTERNAL_SEARCH
+# setting. When disabled, doxygen will generate a PHP script for searching and
+# an index file used by the script. When EXTERNAL_SEARCH is enabled the indexing
+# and searching needs to be provided by external tools. See the section
+# "External Indexing and Searching" for details.
+# The default value is: NO.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+SERVER_BASED_SEARCH    = NO
+
+# When EXTERNAL_SEARCH tag is enabled doxygen will no longer generate the PHP
+# script for searching. Instead the search results are written to an XML file
+# which needs to be processed by an external indexer. Doxygen will invoke an
+# external search engine pointed to by the SEARCHENGINE_URL option to obtain the
+# search results.
+#
+# Doxygen ships with an example indexer (doxyindexer) and search engine
+# (doxysearch.cgi) which are based on the open source search engine library
+# Xapian (see: https://xapian.org/).
+#
+# See the section "External Indexing and Searching" for details.
+# The default value is: NO.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+EXTERNAL_SEARCH        = NO
+
+# The SEARCHENGINE_URL should point to a search engine hosted by a web server
+# which will return the search results when EXTERNAL_SEARCH is enabled.
+#
+# Doxygen ships with an example indexer (doxyindexer) and search engine
+# (doxysearch.cgi) which are based on the open source search engine library
+# Xapian (see: https://xapian.org/). See the section "External Indexing and
+# Searching" for details.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+SEARCHENGINE_URL       =
+
+# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the unindexed
+# search data is written to a file for indexing by an external tool. With the
+# SEARCHDATA_FILE tag the name of this file can be specified.
+# The default file is: searchdata.xml.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+SEARCHDATA_FILE        = searchdata.xml
+
+# When SERVER_BASED_SEARCH and EXTERNAL_SEARCH are both enabled the
+# EXTERNAL_SEARCH_ID tag can be used as an identifier for the project. This is
+# useful in combination with EXTRA_SEARCH_MAPPINGS to search through multiple
+# projects and redirect the results back to the right project.
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+EXTERNAL_SEARCH_ID     =
+
+# The EXTRA_SEARCH_MAPPINGS tag can be used to enable searching through doxygen
+# projects other than the one defined by this configuration file, but that are
+# all added to the same external search index. Each project needs to have a
+# unique id set via EXTERNAL_SEARCH_ID. The search mapping then maps the id of
+# to a relative location where the documentation can be found. The format is:
+# EXTRA_SEARCH_MAPPINGS = tagname1=loc1 tagname2=loc2 ...
+# This tag requires that the tag SEARCHENGINE is set to YES.
+
+EXTRA_SEARCH_MAPPINGS  =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the LaTeX output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_LATEX tag is set to YES, doxygen will generate LaTeX output.
+# The default value is: YES.
+
+GENERATE_LATEX         = NO
+
+# The LATEX_OUTPUT tag is used to specify where the LaTeX docs will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: latex.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_OUTPUT           = latex
+
+# The LATEX_CMD_NAME tag can be used to specify the LaTeX command name to be
+# invoked.
+#
+# Note that when enabling USE_PDFLATEX this option is only used for generating
+# bitmaps for formulas in the HTML output, but not in the Makefile that is
+# written to the output directory.
+# The default file is: latex.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_CMD_NAME         = latex
+
+# The MAKEINDEX_CMD_NAME tag can be used to specify the command name to generate
+# index for LaTeX.
+# The default file is: makeindex.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+MAKEINDEX_CMD_NAME     = makeindex
+
+# If the COMPACT_LATEX tag is set to YES, doxygen generates more compact LaTeX
+# documents. This may be useful for small projects and may help to save some
+# trees in general.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+COMPACT_LATEX          = NO
+
+# The PAPER_TYPE tag can be used to set the paper type that is used by the
+# printer.
+# Possible values are: a4 (210 x 297 mm), letter (8.5 x 11 inches), legal (8.5 x
+# 14 inches) and executive (7.25 x 10.5 inches).
+# The default value is: a4.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+PAPER_TYPE             = a4
+
+# The EXTRA_PACKAGES tag can be used to specify one or more LaTeX package names
+# that should be included in the LaTeX output. The package can be specified just
+# by its name or with the correct syntax as to be used with the LaTeX
+# \usepackage command. To get the times font for instance you can specify :
+# EXTRA_PACKAGES=times or EXTRA_PACKAGES={times}
+# To use the option intlimits with the amsmath package you can specify:
+# EXTRA_PACKAGES=[intlimits]{amsmath}
+# If left blank no extra packages will be included.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+EXTRA_PACKAGES         =
+
+# The LATEX_HEADER tag can be used to specify a personal LaTeX header for the
+# generated LaTeX document. The header should contain everything until the first
+# chapter. If it is left blank doxygen will generate a standard header. See
+# section "Doxygen usage" for information on how to let doxygen write the
+# default header to a separate file.
+#
+# Note: Only use a user-defined header if you know what you are doing! The
+# following commands have a special meaning inside the header: $title,
+# $datetime, $date, $doxygenversion, $projectname, $projectnumber,
+# $projectbrief, $projectlogo. Doxygen will replace $title with the empty
+# string, for the replacement values of the other commands the user is referred
+# to HTML_HEADER.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_HEADER           =
+
+# The LATEX_FOOTER tag can be used to specify a personal LaTeX footer for the
+# generated LaTeX document. The footer should contain everything after the last
+# chapter. If it is left blank doxygen will generate a standard footer. See
+# LATEX_HEADER for more information on how to generate a default footer and what
+# special commands can be used inside the footer.
+#
+# Note: Only use a user-defined footer if you know what you are doing!
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_FOOTER           =
+
+# The LATEX_EXTRA_STYLESHEET tag can be used to specify additional user-defined
+# LaTeX style sheets that are included after the standard style sheets created
+# by doxygen. Using this option one can overrule certain style aspects. Doxygen
+# will copy the style sheet files to the output directory.
+# Note: The order of the extra style sheet files is of importance (e.g. the last
+# style sheet in the list overrules the setting of the previous ones in the
+# list).
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_EXTRA_STYLESHEET =
+
+# The LATEX_EXTRA_FILES tag can be used to specify one or more extra images or
+# other source files which should be copied to the LATEX_OUTPUT output
+# directory. Note that the files will be copied as-is; there are no commands or
+# markers available.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_EXTRA_FILES      =
+
+# If the PDF_HYPERLINKS tag is set to YES, the LaTeX that is generated is
+# prepared for conversion to PDF (using ps2pdf or pdflatex). The PDF file will
+# contain links (just like the HTML output) instead of page references. This
+# makes the output suitable for online browsing using a PDF viewer.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+PDF_HYPERLINKS         = YES
+
+# If the USE_PDFLATEX tag is set to YES, doxygen will use pdflatex to generate
+# the PDF file directly from the LaTeX files. Set this option to YES, to get a
+# higher quality PDF documentation.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+USE_PDFLATEX           = YES
+
+# If the LATEX_BATCHMODE tag is set to YES, doxygen will add the \batchmode
+# command to the generated LaTeX files. This will instruct LaTeX to keep running
+# if errors occur, instead of asking the user for help. This option is also used
+# when generating formulas in HTML.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_BATCHMODE        = NO
+
+# If the LATEX_HIDE_INDICES tag is set to YES then doxygen will not include the
+# index chapters (such as File Index, Compound Index, etc.) in the output.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_HIDE_INDICES     = NO
+
+# If the LATEX_SOURCE_CODE tag is set to YES then doxygen will include source
+# code with syntax highlighting in the LaTeX output.
+#
+# Note that which sources are shown also depends on other settings such as
+# SOURCE_BROWSER.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_SOURCE_CODE      = NO
+
+# The LATEX_BIB_STYLE tag can be used to specify the style to use for the
+# bibliography, e.g. plainnat, or ieeetr. See
+# https://en.wikipedia.org/wiki/BibTeX and \cite for more info.
+# The default value is: plain.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_BIB_STYLE        = plain
+
+# If the LATEX_TIMESTAMP tag is set to YES then the footer of each generated
+# page will contain the date and time when the page was generated. Setting this
+# to NO can help when comparing the output of multiple runs.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_LATEX is set to YES.
+
+LATEX_TIMESTAMP        = NO
+
+#---------------------------------------------------------------------------
+# Configuration options related to the RTF output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_RTF tag is set to YES, doxygen will generate RTF output. The
+# RTF output is optimized for Word 97 and may not look too pretty with other RTF
+# readers/editors.
+# The default value is: NO.
+
+GENERATE_RTF           = NO
+
+# The RTF_OUTPUT tag is used to specify where the RTF docs will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: rtf.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_OUTPUT             = rtf
+
+# If the COMPACT_RTF tag is set to YES, doxygen generates more compact RTF
+# documents. This may be useful for small projects and may help to save some
+# trees in general.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+COMPACT_RTF            = NO
+
+# If the RTF_HYPERLINKS tag is set to YES, the RTF that is generated will
+# contain hyperlink fields. The RTF file will contain links (just like the HTML
+# output) instead of page references. This makes the output suitable for online
+# browsing using Word or some other Word compatible readers that support those
+# fields.
+#
+# Note: WordPad (write) and others do not support links.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_HYPERLINKS         = NO
+
+# Load stylesheet definitions from file. Syntax is similar to doxygen's config
+# file, i.e. a series of assignments. You only have to provide replacements,
+# missing definitions are set to their default value.
+#
+# See also section "Doxygen usage" for information on how to generate the
+# default style sheet that doxygen normally uses.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_STYLESHEET_FILE    =
+
+# Set optional variables used in the generation of an RTF document. Syntax is
+# similar to doxygen's config file. A template extensions file can be generated
+# using doxygen -e rtf extensionFile.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_EXTENSIONS_FILE    =
+
+# If the RTF_SOURCE_CODE tag is set to YES then doxygen will include source code
+# with syntax highlighting in the RTF output.
+#
+# Note that which sources are shown also depends on other settings such as
+# SOURCE_BROWSER.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_RTF is set to YES.
+
+RTF_SOURCE_CODE        = NO
+
+#---------------------------------------------------------------------------
+# Configuration options related to the man page output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_MAN tag is set to YES, doxygen will generate man pages for
+# classes and files.
+# The default value is: NO.
+
+GENERATE_MAN           = NO
+
+# The MAN_OUTPUT tag is used to specify where the man pages will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it. A directory man3 will be created inside the directory specified by
+# MAN_OUTPUT.
+# The default directory is: man.
+# This tag requires that the tag GENERATE_MAN is set to YES.
+
+MAN_OUTPUT             = man
+
+# The MAN_EXTENSION tag determines the extension that is added to the generated
+# man pages. In case the manual section does not start with a number, the number
+# 3 is prepended. The dot (.) at the beginning of the MAN_EXTENSION tag is
+# optional.
+# The default value is: .3.
+# This tag requires that the tag GENERATE_MAN is set to YES.
+
+MAN_EXTENSION          = .3
+
+# The MAN_SUBDIR tag determines the name of the directory created within
+# MAN_OUTPUT in which the man pages are placed. If defaults to man followed by
+# MAN_EXTENSION with the initial . removed.
+# This tag requires that the tag GENERATE_MAN is set to YES.
+
+MAN_SUBDIR             =
+
+# If the MAN_LINKS tag is set to YES and doxygen generates man output, then it
+# will generate one additional man file for each entity documented in the real
+# man page(s). These additional files only source the real man page, but without
+# them the man command would be unable to find the correct page.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_MAN is set to YES.
+
+MAN_LINKS              = NO
+
+#---------------------------------------------------------------------------
+# Configuration options related to the XML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_XML tag is set to YES, doxygen will generate an XML file that
+# captures the structure of the code including all documentation.
+# The default value is: NO.
+
+GENERATE_XML           = NO
+
+# The XML_OUTPUT tag is used to specify where the XML pages will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: xml.
+# This tag requires that the tag GENERATE_XML is set to YES.
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diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/faq.md b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/faq.md
new file mode 100644
index 0000000..877b8f0
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/faq.md
@@ -0,0 +1,45 @@
+FAQ {#rt-faq}
+===
+@tableofcontents
+
+This section answers frequently asked questions.
+
+# Why do some modules stop working after a few seconds?
+
+Some modules work after the device powers up but then stop working after a
+few seconds. For example, I am configuring UART and GPIO in the application and
+few seconds later application stops working.
+
+@b Answer: This issue can happen when the kernel changes the configuration of a
+module that SPE is using. This is because SPE runs before linux kernel. Possible
+place to look is kernel device tree and making sure that module is disabled for
+the kernel.
+
+# Why do some modules fail to run or cause Cortex-R5 to crash/hang?
+
+I have modules that fail to run even though I checked all codes and settings in
+SPE.
+
+@b Answer: This issue can occur for the following reasons:
+
+- Incorrect SCR settings
+
+  Some modules have Security Configuration Registers (SCR). Acessing a module
+  that is configured with incorrect SCR settings may result in a system crash.
+
+- Clocks are not enabled or properly not configured
+
+# Why does my customized SPE firmware fail to flash?
+
+I successfully flashed the default firmware. But then flashing failed with when I tried to flash
+SPI firmware that I modified  to test my own code. I used the same flash command and the same
+device.
+
+@b Answer: Flashing customized SPE firmware can fail for several reasons:
+
+- The custom SPE firmware has a problem, which causes the SPE firmware to crash and the device to
+  hang. When that happens, the PC cannot communicate with the
+  device and the flash command cannot proceed.
+
+  To resolve this issue, carefully check the code you modified and ensure its logic and
+  settings are correct.
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/footer.html b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/footer.html
new file mode 100644
index 0000000..e468fcb
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/footer.html
@@ -0,0 +1,39 @@
+<!--BEGIN GENERATE_TREEVIEW-->
+<div id="nav-path" class="navpath">
+  <ul>
+    <li class="footer footer-left">
+      <a href="https://www.nvidia.com/en-us/about-nvidia/privacy-policy/" target="_blank">Privacy Policy</a> |
+      <a href="https://www.nvidia.com/en-us/privacy-center/" target="_blank">Manage My Privacy</a> |
+      <a href="https://www.nvidia.com/en-us/preferences/email-preferences/" target="_blank">Do Not Sell or Share My Data</a> |
+      <a href="https://www.nvidia.com/en-us/about-nvidia/terms-of-service/" target="_blank">Terms of Service</a> |
+      <a href="https://www.nvidia.com/en-us/about-nvidia/accessibility/" target="_blank">Accessibility</a> |
+      <a href="https://www.nvidia.com/en-us/about-nvidia/company-policies/" target="_blank">Corporate Policies</a> |
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diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/fsp.md b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/fsp.md
new file mode 100644
index 0000000..19d7fef
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/fsp.md
@@ -0,0 +1,62 @@
+FSP (Firmware Support Package)
+==================================
+
+@tableofcontents
+
+The FSP layer provides common set of on chip and bus peripheral drivers such as
+but not limited to gpio, i2c, spi, hsp, ast, aodmic for the various auxiliary
+processors present in the Jetson. This guide pertains to SPE or AON auxiliary
+processor. The FSP also provides operating system abstraction
+layer (OSA) to support different type and flavors of the operating systems,
+here we are only concerned about FreeRTOS. Since FSP houses common set of
+drivers across multiple of processors, it implements CPU abstraction layer (CPL)
+which abstracts away CPU primitives such as but not limited to cache management,
+barriers, memory managements. More details will be followed in later sections.
+
+# OSA Layer #
+The OSA provides the abstraction to underlying Real Time Operating System (RTOS)
+(FreeRTOS in this case). This helps in porting the firmware drivers/applications
+into different RTOS with little to no changes at the firmware drivers/application
+level. The following files that implement the FreeRTOS OSA can be found in the
+fsp/source/include/osa/freertosv10/osa directory:
+- Semaphore
+  - follow `osa-semaphore.h` for API details.
+- Mutex
+  - follow `osa-mutex.h` for API details.
+- Event Group
+  - follow `osa-event-group.h` for API details.
+- Queue
+  - follow `osa-queue.h` for API details.
+- Threads and real time scheduling
+  - follow `osa-task.h` for API details.
+- Timer
+  - follow `osa-timer.h` for API details.
+
+# CPL Layer #
+The FSP provides an abstraction to CPU configuration via CPL library.
+This library includes:
+- Cache configuration and control for enable/disable/flush/invalidate
+the caches
+  - follow `fsp/source/include/cpu/arm/common/cpu/cache.h` for API details.
+- Register access
+  - follow `fsp/source/include/cpu/arm/armv7/cortex-r5/reg-access/reg-access.h`
+  for API details.
+- CPU synchronization barriers
+  - follow `fsp/source/include/cpu/arm//common/cpu/barriers.h` for API details.
+- Vector Interrupt Control (VIC) for configuring, enabling and disabling
+interrupt and its handlers
+  - follow `fsp/source/include/cpu/arm/common/cpu/arm-vic.h` for API details.
+- Chip-ID to get SoC version and SKUs
+  - follow `fsp/source/include/chipid/chip-id.h` for API details.
+
+# Drivers #
+This layer implements common set up peripherals and on chip hardware module
+drivers. The drivers use OSA and CPL layers to implement CPU or OS specific
+primitives. For brevity this guide will not detail various drivers' APIs as it
+can be accessed from their respective header files. For example, API details to
+use GPIO driver are found at `fsp/source/include/gpio/tegra-gpio.h`.
+Additionally, some drivers use port layer implemented at
+`fsp/source/soc/<soc number>/port/aon` to abstract away processor specific
+implementation. Each driver or peripheral has associated ID structure
+implemented at `fsp/source/soc/<soc number>/ids/aon` which details
+peripheral instance related information like base address, irq.
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/gpio.md b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/gpio.md
new file mode 100644
index 0000000..5a18e2c
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/gpio.md
@@ -0,0 +1,167 @@
+GPIO Application (app/gpio-app.c)
+================================
+
+@tableofcontents
+
+GPIO application demonstrates how to access/manipulate Always On (AON) GPIOs from
+the SPE/AON processor.
+
+Pinmux changes are necessary in order for this demo to function correctly.
+These changes relate to the MB1 bootloader.  The recommended method for changing
+pinmux settings is to download the device-specific pinmux spreadsheet and
+generate an updated set of pinmux configuration files.  In the steps below some
+updates to various configuration files will be shown.  While the preferred method
+is to leverage the pinmux spreadsheet, manually modifying the files will also
+work for the purpose of quickly demonstrating GPIO functionality.
+
+# AGX Orin
+
+## Hardware Configuration
+The following pins from the 40 pin header (J30) should be connected together:
+   * Pin 16 (PBB1, output)
+   * Pin 32 (PBB0, input)
+
+## Software Configuration
+In order to access a AON GPIO from the Cortex-R5 SPE/AON for AGX Orin, the
+GPIO interrupt map and pinmux settings need to be updated as described in below
+steps.
+
+1. In `soc/t23x/target_specific.mk`, set `ENABLE_GPIO_APP := 1` and rebuild the
+application. Copy the output to `${L4T}/bootloader/spe_t234.bin`.
+
+2. Update gpio interrupt mapping as below in `${L4T}/bootloader/generic/BCT/tegra234-mb1-bct-gpioint-p3701-0000.dts`:
+
+         --- a/generic/BCT/tegra234-mb1-bct-gpioint-p3701-0000.dts
+         +++ b/generic/BCT/tegra234-mb1-bct-gpioint-p3701-0000.dts
+         @@ -234,7 +234,7 @@
+                     pin-7-int-line = <4>; // GPIO AA7 to INT0
+                  };
+                  port@BB {
+         -            pin-0-int-line = <4>; // GPIO BB0 to INT0
+         +            pin-0-int-line = <2>; // GPIO BB0 to INT2
+                     pin-1-int-line = <4>; // GPIO BB1 to INT0
+                     pin-2-int-line = <4>; // GPIO BB2 to INT0
+                     pin-3-int-line = <4>; // GPIO BB3 to INT0
+
+3. Update gpio configuration as below in `${L4T}/bootloader/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi`:
+
+         --- a/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi
+         +++ b/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi
+         @@ -118,12 +118,12 @@
+                                       TEGRA234_AON_GPIO(AA, 2)
+                                       TEGRA234_AON_GPIO(AA, 3)
+                                       TEGRA234_AON_GPIO(BB, 0)
+         -                              TEGRA234_AON_GPIO(BB, 1)
+                                       TEGRA234_AON_GPIO(BB, 3)
+                                       >;
+                                 gpio-output-low = <
+                                       TEGRA234_AON_GPIO(CC, 2)
+                                       TEGRA234_AON_GPIO(CC, 3)
+         +                              TEGRA234_AON_GPIO(BB, 1)
+                                       >;
+                                 gpio-output-high = <
+                                       >;
+
+4. Update pinmux configuration as below in the file `${L4T}/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi`:
+
+         --- a/generic/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi
+         +++ b/generic/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi
+         @@ -1000,9 +1000,9 @@
+                                 can1_en_pbb1 {
+                                       nvidia,pins = "can1_en_pbb1";
+                                       nvidia,function = "rsvd0";
+         -                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+         -                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
+         -                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+         +                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+         +                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+         +                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                 };
+5. Reflash all partitions to ensure that the gpio interrupt mappings
+   and pinmux settings are updated on the board.
+
+6. The demo should produce the following output on the terminal:
+
+         gpio_app_task - Setting GPIO_APP_OUT to 1 - IRQ should trigger
+         can_gpio_irq_handler - gpio irq triggered - setting GPIO_APP_OUT to 0
+
+
+# Orin Nano
+
+## Hardware Configuration
+The following pins from the 40 pin header (J12) should be connected together:
+   * Pin 5 (PDD1, output)
+   * Pin 3 (PDD2, input)
+
+## Software Configuration
+In order to access a AON GPIO from the Cortex-R5 SPE/AON for Orin Nano, the
+GPIO interrupt map and pinmux settings need to be updated as described in below
+steps.
+
+1. In `soc/t23x/target_specific.mk`, set `ENABLE_GPIO_APP := 1` and `ENABLE_SPE_FOR_ORIN_NANO := 1. Rebuild the
+application. Copy the output to `${L4T}/bootloader/spe_t234.bin`.
+
+2. Update gpio interrupt mapping as below in `${L4T}/bootloader/generic/BCT/tegra234-mb1-bct-gpioint-p3767-0000.dts`:
+
+         --- a/bootloader/generic/BCT/tegra234-mb1-bct-gpioint-p3767-0000.dts
+         +++ b/bootloader/generic/BCT/tegra234-mb1-bct-gpioint-p3767-0000.dts
+         @@ -252,7 +252,7 @@
+                  port@DD {
+                     pin-0-int-line = <4>; // GPIO DD0 to INT0
+                     pin-1-int-line = <4>; // GPIO DD1 to INT0
+         -           pin-2-int-line = <4>; // GPIO DD2 to INT0
+         +           pin-2-int-line = <2>; // GPIO DD2 to INT2
+                  };
+
+3. Update gpio configuration as below in `${L4T}/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi`:
+
+         --- a/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi
+         +++ b/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi
+         @@ -89,8 +89,10 @@
+                                 gpio-input = <
+                                       TEGRA234_AON_GPIO(EE, 2)
+                                       TEGRA234_AON_GPIO(EE, 4)
+         +                             TEGRA234_AON_GPIO(DD, 2)
+                                       >;
+                                 gpio-output-low = <
+         +                             TEGRA234_AON_GPIO(DD, 1)
+                                       TEGRA234_AON_GPIO(CC, 0)
+
+4. Update pinmux configuration as below in the file `${L4T}/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi`:
+
+
+         --- a/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi
+         +++ b/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi
+         @@ -134,19 +134,18 @@
+
+                                 gen8_i2c_scl_pdd1 {
+                                         nvidia,pins = "gen8_i2c_scl_pdd1";
+         -                               nvidia,function = "i2c8";
+         +                               nvidia,function = "rsvd1";
+                                         nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                         nvidia,tristate = <TEGRA_PIN_DISABLE>;
+         -                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+         +                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                         nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
+                                         nvidia,lpdr = <TEGRA_PIN_DISABLE>;
+                                 };
+
+                                 gen8_i2c_sda_pdd2 {
+                                         nvidia,pins = "gen8_i2c_sda_pdd2";
+         -                               nvidia,function = "i2c8";
+         -                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+         -                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+         +                               nvidia,function = "rsvd1";
+         +                               nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
+         +                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                         nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                         nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
+                                         nvidia,lpdr = <TEGRA_PIN_DISABLE>;
+
+5. Reflash all partitions to ensure that the gpio interrupt mappings
+   and pinmux settings are updated on the board.
+
+6. The demo should produce the following output on the terminal:
+
+         gpio_app_task - Setting GPIO_APP_OUT to 1 - IRQ should trigger
+         can_gpio_irq_handler - gpio irq triggered - setting GPIO_APP_OUT to 0
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/gte-app.md b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/gte-app.md
new file mode 100644
index 0000000..3eed6ee
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/gte-app.md
@@ -0,0 +1,107 @@
+GTE Application (app/gte-app.c)
+===============================
+
+@tableofcontents
+
+This section explains how to use the generic time-stamping engine (GTE).
+
+The GTE snoops a set of signals and presents the timestamped events to the software
+using FIFOs. There are three GTE instances/slices available to AON/SPE and each is
+32 bits wide. Refer to gte-tegra-hw.h for more information about signals mapping to slices.
+
+To determine the GTE pin mapping, refer to the pin-mux spreadsheet that corresponds
+to your module. There is a hidden column in the spreadsheet called "GTE" that lists
+the bit in slice 2 that corresponds to that pin.
+
+# Hardware Configuration
+The application demonstrates the GTE driver APIs and works with gpio-app
+to monitor the interrupt on the `GPIO_APP_IN` line. Refer to GPIO Application,
+for more information about wiring details.
+
+# Software Configuration
+
+## AGX Orin
+1. In `soc/t23x/target_specific.mk`, set `ENABLE_GTE_APP := 1`, rebuild the
+application, and copy the output to `${L4T}/bootloader/spe_t234.bin`.
+
+2. Disable GTE driver in the Linux kernel device tree, ensure that no other
+processors using the driver, and run source_sync.sh. The resulting dtsi file
+is located at `Linux_for_Tegra/sources/hardware/nvidia/t23x/nv-public/overlay/tegra234-p3737-0000+p3701-0000.dts`.
+Add the following code to disable hardware-timestamp under bus0 node.
+
+         +++ tegra234-p3737-0000+p3701-0000.dts
+         @@ -210,6 +210,10 @@
+                                        status = "okay";
+                                };
+
+         +                hardware-timestamp@c1e0000 {
+         +                       status = "disabled";
+         +                };
+         +
+                          mttcan@c310000 {
+                                 status = "okay";
+
+3. Rebuild the device tree and copy the dtb file to Linux_for_Tegra/dtb/ directory.
+4. Modify firewall setting in `${L4T}/bootloader/tegra234-mb2-bct-scr-p3701-0000-override.dts` to allow SPE
+   to read/write to the GTE register.
+```
+    +++ b/bootloader/tegra234-mb2-bct-scr-p3701-0000-override.dts
+    @@ -24,6 +24,11 @@
+                 value = <0x18000606>;
+             };
+
+    +        reg@1359 { /* GTE_GPIO_SCR_TESCR_0 */
+    +            exclusion-info = <2>;
+    +            value = <0x38001232>;
+    +        };
+    +
+             reg@5114 { /* CBB_CENTRAL_CBB_FIREWALL_PWM5_BLF, READ_CTL */
+```
+5. Reflash all partitions to ensure that the dtb and firewall settings are updated on the board.
+
+## Orin Nano
+1. In `soc/t23x/target_specific.mk`, set `ENABLE_GTE_APP := 1` and `ENABLE_SPE_FOR_ORIN_NANO := 1`. Rebuild the
+application, and copy the output to `${L4T}/bootloader/spe_t234.bin`.
+
+2. Disable GTE driver in the Linux kernel device tree, ensure that no other
+processors using the driver, and run source_sync.sh. The resulting dtsi file
+is located at `Linux_for_Tegra/sources/hardware/nvidia/t23x/nv-public/overlay/tegra234-p3768-0000+p3767-0000.dts`.
+Add the following code to disable hardware-timestamp under bus0 node.
+
+         +++ tegra234-p3768-0000+p3767-0000.dts
+         @@ -245,6 +245,10 @@
+                                        status = "okay";
+                                };
+
+         +                hardware-timestamp@c1e0000 {
+         +                       status = "disabled";
+         +                };
+         +
+                          mttcan@c310000 {
+                                 status = "okay";
+
+3. Rebuild the device tree and copy the dtb file to Linux_for_Tegra/dtb/ directory.
+4. Modify firewall setting in `${L4T}/bootloader/tegra234-firewall-config-base.dtsi` to allow SPE
+   to read/write to the GTE register.
+```
+    +++ b/bootloader/tegra234-firewall-config-base.dtsi
+    @@ -6814,7 +6814,7 @@
+         };
+
+            reg@1359 { /* GTE_GPIO_SCR_TESCR_0 */
+                exclusion-info = <3>;
+    -           value = <0x38000222>;
+    +           value = <0x38001232>;
+            };
+
+```
+5. Reflash all partitions to ensure that the dtb and firewall settings are updated on the board.
+
+# Result
+GTE ISR is called when the FIFO reaches the GTE_FIFO_OCCUPANCY threshold.
+On successful execution, GTE ISR following message:
+```
+gpio_app_task - Setting GPIO_APP_OUT to 1 - IRQ should trigger
+Slice Id: xx, Event Id: xx (Other), Edge = rising, Raw Time stamp = xx, Timestamp in nanosec = xx
+can_gpio_irq_handler - gpio irq triggered - setting GPIO_APP_OUT to 0
+```
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/i2c-app.md b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/i2c-app.md
new file mode 100644
index 0000000..8cfaf08
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/i2c-app.md
@@ -0,0 +1,74 @@
+I2C application (app/i2c-app.c)
+===============================
+
+@tableofcontents
+
+I2C application demonstrates how to access/manipulate Always On (AON) I2C from
+the SPE/AON processor. There are three I2C instances (2, 8 and 10) in AON
+domain, availability of the instance will be based on the Jetson platform being
+used.
+
+@note It is required to compile device tree and flash board to have them
+updated after making kernel device tree changes as described in following
+sections.
+
+
+## Hardware Configuration
+
+The sample app uses I2C bus 8 and BMI160 sensor module, similar to
+https://hackspark.fr/en/electronics/1341-6dof-bosch-6-axis-acceleration-gyro-gravity-sensor-gy-bmi160.html
+for the demo purposes.
+
+The I2C app accesses the 40 pin header J30 and expects I2C external module at the pin map
+shown below:
+
+- Pin 1  - 3.3V
+- Pin 3  - SDA
+- Pin 5  - SCL
+- Pin 34 - SAO
+- Pin 39 - GND
+
+The demo app reads BMI160 sensor ID. If the app successfully retrieves the
+correct ID, it prints the following message:
+
+    I2C test successful
+
+@note BMI160 is configured to have the I2C address 0x68 by connecting its SAO pin to
+Pin 34.
+
+## Software Configuration
+
+# Jetson AGX Orin and Orin Nano
+1. Make sure I2C bus 8 is disabled in linux kernel device tree and no other
+processors using it. In case of Orin Nano, it is disabled by default. For AGX Orin, the I2C bus 8 needs to be disabled.
+You must run source_sync.sh to get the dtsi file. After running source_sync.sh, the file is located at
+Linux_for_Tegra/sources/hardware/nvidia/t23x/nv-public/overlay/tegra234-p3737-0000+p3701-0000.dts.
+Disabling device node from the kernel makes that I2C controller and all the client devices
+attached to it unaccessible from the kernel.
+```
+    i2c@c250000 {
+            status = "disabled";
+    };
+```
+2. Compile the device tree and copy the dtb file to Linux_for_Tegra/dtb/ directory.
+3. Disable firewall setting in bootloader/tegra234-firewall-config-base.dtsi
+so that SPE can access I2C registers.
+```
+        reg@2130 { /* CLK_RST_CONTROLLER_AON_SCR_I2C8_0 */
+            exclusion-info = <3>;
+            value = <0x30001610>;
+        };
+```
+
+4. In `soc/t23x/target_specific.mk`, set `ENABLE_I2C_APP := 1` and rebuild the
+application. Copy the output to `${L4T}/bootloader/spe_t234.bin`
+
+5. Reflash all the partitions, including new device tree and SPE binaries
+generated from the above steps by referencing the instructions in the **Building the Kernel**
+section of the Linux Developer Guide.
+
+The demo app reads BMI160 sensor ID. If the app successfully retrieves the
+correct ID, it prints the following message:
+
+    I2C test successful
+
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/ivc.md b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/ivc.md
new file mode 100644
index 0000000..ee3fb95
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/ivc.md
@@ -0,0 +1,52 @@
+IVC (app/ivc-echo-task.c)
+=========================
+
+Inter VM Communication (IVC) provides interface to communicate between chip processors through a shared-memory channel. It uses Hardware Synchronization Primitives (HSP)
+for interprocessor synchronization through doorbell mechanism. The assertion of the doorbell signal indicates that
+the destination processor requires attention, typically because the source processor posted a message in memory.
+
+This application demonstrates the communication between CCPLEX and AON through a data_channel created by AON Echo driver
+where the data is sent from CCPLEX to AON and it's echoed back from AON to CCPLEX.
+
+# AGX Orin and Orin Nano
+1. The current IVC channel are described in the device tree repository. You must run source_sync.sh to get the dtsi file.
+After running source_sync.sh, the file is located at
+AGX Orin:  Linux_for_Tegra/source/hardware/nvidia/t23x/nv-public/nv-platform/tegra234-p3737-0000+p3701-xxxx-nv-common.dtsi
+Orin Nano: Linux_for_Tegra/source/hardware/nvidia/t23x/nv-public/nv-platform/tegra234-p3768-0000+p3767-xxxx-nv-common.dtsi
+
+2. To add/remove or enable/disable the channels in linux kernel, you must update the
+device tree entries in the above dtsi file. The following code shows how to enable the IVC echo channel:
+```
+        bus@0 {
++               aon_echo {
++                       status = "okay";
++               };
++
+
+```
+
+3. Compile the device tree and copy the dtb file to Linux_for_Tegra/dtb/ directory.
+4. Rebuild the device tree and reflash the board by referencing the instructions in the **Building the Kernel** section of the Linux Developer Guide.
+5. Build the SPE application, and copy the output to `${L4T}/bootloader/spe_t234.bin`.
+
+# How to test
+From the Linux kernel side, the `/sys/devices/platform/bus@0/bus@0:aon_echo/data_channel`
+node is used to communicate with AON after enabling echo channel as mentioned above.
+Messages sent to AON through this channel are echoed back to CCPLEX.
+```
+ubuntu@jetson:~$ sudo su -c 'echo tegra > /sys/devices/platform/bus@0/bus@0:aon_echo/data_channel'
+ubuntu@jetson:~$ cat /sys/devices/platform/bus@0/bus@0:aon_echo/data_channel
+tegra
+ubuntu@jetson:~$
+```
+
+# Sources
+The echo channel ivc code in the current firmware resides at:
+
+    rt-aux-cpu-demo-fsp/app/ivc-echo-task.c
+    rt-aux-cpu-demo-fsp/drivers/ivc-channels.c
+
+And the channel descriptions are at:
+
+    rt-aux-cpu-demo-fsp/platform/ivc-channel-ids.c
+    rt-aux-cpu-demo-fsp/soc/t23x/include/ivc-config.h
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/nv.css b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/nv.css
new file mode 100644
index 0000000..2098fca
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/nv.css
@@ -0,0 +1,1613 @@
+/*
+ * Copyright (c) 2007-2024 NVIDIA Corporation.  All rights reserved.
+ *
+ * NVIDIA Corporation and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
+ * license agreement from NVIDIA Corporation is strictly prohibited.
+ */
+
+/* The standard CSS for doxygen 1.8.7 */
+
+body, table, div, p, dl {
+    font-family: Trebuchet MS, Arial, Roboto,sans-serif;
+    font-size: 14px;
+
+}
+
+/* @group Heading Levels */
+
+/* Use NVIDIA Green 2 for H1-H3 headings */
+h1, h2, h3 {
+    color: #004831;
+    font-weight: bold
+}
+
+
+/* Use NVIDIA Green 2 for H1-H3 headings */
+h1.groupheader, h1 {
+    font-size: 100%;
+    color: #004831
+}
+
+.title {
+	font-size: 150%;
+	font-weight: bold;
+	margin: 10px 2px;
+}
+
+/* Use NVIDIA Green 2 for H1-H3 headings */
+h2.groupheader, h2 {
+    font-size: 120%;
+    color: #004831
+}
+
+/* Use NVIDIA Green 2 for H1-H3 headings */
+h3.groupheader {
+    font-size: 100%;
+    color: #004831
+}
+
+h1, h2, h3, h4, h5, h6 {
+	-webkit-transition: text-shadow 0.5s linear;
+	-moz-transition: text-shadow 0.5s linear;
+	-ms-transition: text-shadow 0.5s linear;
+	-o-transition: text-shadow 0.5s linear;
+	transition: text-shadow 0.5s linear;
+	margin-right: 15px;
+}
+
+/* Use NVIDIA Green for highlighting and glow */
+h1.glow, h2.glow, h3.glow, h4.glow, h5.glow, h6.glow {
+	text-shadow: 0 0 15px #76B900;
+}
+
+code {
+    font-family:'Courier New';
+        font-size:  90%;
+}
+
+dt {
+	font-weight: bold;
+}
+
+div.multicol {
+	-moz-column-gap: 1em;
+	-webkit-column-gap: 1em;
+	-moz-column-count: 3;
+	-webkit-column-count: 3;
+}
+
+p.startli, p.startdd {
+	margin-top: 2px;
+}
+
+p.starttd {
+	margin-top: 0px;
+}
+
+p.endli {
+	margin-bottom: 0px;
+}
+
+p.enddd {
+	margin-bottom: 4px;
+}
+
+p.endtd {
+	margin-bottom: 2px;
+}
+
+/* @end */
+
+caption {
+	font-weight: bold;
+}
+
+span.legend {
+        font-size: 70%;
+        text-align: center;
+}
+
+h3.version {
+        font-size: 90%;
+        text-align: center;
+}
+
+div.qindex, div.navtab{
+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
+}
+
+div.qindex, div.navpath {
+	width: 100%;
+	line-height: 140%;
+}
+
+div.navtab {
+	margin-right: 15px;
+}
+
+/* @group Link Styling */
+
+
+/* The corporate template's link color, close to NV Green 2 */
+a {
+        color: #006445;
+	font-weight: normal;
+        text-decoration: underline;
+}
+
+/* The corporate template's link color, close to NV Green 2 */
+a:link {
+    color: #006445
+}
+
+/* The corporate template's link color, close to NV Green 2 */
+a:visited {
+    color: #006445
+}
+
+/* Monochromatic version of NV Green 2. */
+.contents a:visited {
+    color: #80a499;
+}
+
+a:hover {
+	text-decoration: underline;
+}
+
+/* The corporate template's link color, close to NV Green 2 */
+a:link:active {
+     color: #006445
+}
+
+a.qindex {
+	font-weight: bold;
+}
+
+/* Very light slate blue */
+/* Followed by white and then */
+/* Yet another slate blue medium tone */
+a.qindexHL {
+	font-weight: bold;
+	background-color: #9CAFD4;
+	color: #ffffff;
+	border: 1px double #869DCA;
+}
+
+/* White */
+.contents a.qindexHL:visited {
+        color: #ffffff;
+}
+
+
+/* The corporate template's link color, close to NV Green 2 */
+a.el {
+        color: #006445;
+	font-weight: bold;
+}
+
+/* The corporate template's link color, close to NV Green 2 */
+a.elRef {
+    color: #006445;
+}
+
+a.code, a.code:visited, a.line, a.line:visited {
+	color: #4665A2;
+}
+
+a.codeRef, a.codeRef:visited, a.lineRef, a.lineRef:visited {
+	color: #4665A2;
+}
+
+/* Use NVIDIA Green for hover */
+a:hover {
+    color: #76B900;
+    text-decoration: underline;
+}
+
+/* Use NVIDIA Green for hover */
+a:visited:hover {
+    color: #76B900
+}
+
+
+
+
+/* @end */
+
+dl.el {
+	margin-left: -1cm;
+}
+
+
+/* Powdery blue/grey followed by almost washed out white of the same. */
+pre.fragment {
+        border: 1px solid #C4CFE5;
+        background-color: #FBFCFD;
+        padding: 4px 6px;
+        margin: 4px 8px 4px 2px;
+        overflow: auto;
+        word-wrap: break-word;
+        line-height: 125%;
+        font-family: monospace, fixed;
+        font-size: 85%;
+}
+
+div.fragment {
+        padding: 4px 6px;
+        margin: 4px 8px 4px 2px;
+	background-color: #FBFCFD;
+	border: 1px solid #C4CFE5;
+}
+
+div.line {
+	font-family: monospace, fixed;
+        font-size: 90%;
+	min-height: 13px;
+	line-height: 1.0;
+	text-wrap: unrestricted;
+	white-space: -moz-pre-wrap; /* Moz */
+	white-space: -pre-wrap;     /* Opera 4-6 */
+	white-space: -o-pre-wrap;   /* Opera 7 */
+	white-space: pre-wrap;      /* CSS3  */
+	word-wrap: break-word;      /* IE 5.5+ */
+	text-indent: -53px;
+	padding-left: 53px;
+	padding-bottom: 0px;
+	margin: 0px;
+	-webkit-transition-property: background-color, box-shadow;
+	-webkit-transition-duration: 0.5s;
+	-moz-transition-property: background-color, box-shadow;
+	-moz-transition-duration: 0.5s;
+	-ms-transition-property: background-color, box-shadow;
+	-ms-transition-duration: 0.5s;
+	-o-transition-property: background-color, box-shadow;
+	-o-transition-duration: 0.5s;
+	transition-property: background-color, box-shadow;
+	transition-duration: 0.5s;
+}
+
+/* Use NVIDIA Green for highlight and glow */
+div.line.glow {
+	background-color: #76B900;
+	box-shadow: 0 0 10px #76B900;
+}
+
+
+span.lineno {
+	padding-right: 4px;
+	text-align: right;
+	border-right: 2px solid #0F0;
+	background-color: #E8E8E8;
+        white-space: pre;
+}
+span.lineno a {
+	background-color: #D8D8D8;
+}
+
+span.lineno a:hover {
+	background-color: #C8C8C8;
+}
+/* Gradient from light grey through black to dark, slate grey */
+div.ah {
+	background-color: black;
+	font-weight: bold;
+	color: #ffffff;
+	margin-bottom: 3px;
+	margin-top: 3px;
+	padding: 0.2em;
+	border: solid thin #333;
+	border-radius: 0.5em;
+	-webkit-border-radius: .5em;
+	-moz-border-radius: .5em;
+	box-shadow: 2px 2px 3px #999;
+	-webkit-box-shadow: 2px 2px 3px #999;
+	-moz-box-shadow: rgba(0, 0, 0, 0.15) 2px 2px 2px;
+	background-image: -webkit-gradient(linear, left top, left bottom, from(#eee), to(#000),color-stop(0.3, #444));
+	background-image: -moz-linear-gradient(center top, #eee 0%, #444 40%, #000);
+}
+
+div.groupHeader {
+	margin-left: 16px;
+	margin-top: 12px;
+	font-weight: bold;
+}
+
+div.groupText {
+	margin-left: 16px;
+	font-style: italic;
+}
+
+body {
+	background-color: white;
+	color: black;
+        margin: 0;
+}
+
+div.contents {
+	margin-top: 10px;
+	margin-left: 12px;
+	margin-right: 8px;
+}
+
+/* This is the light bluish-grey */
+/* Powdery blue/grey */
+td.indexkey {
+	background-color: #EBEFF6;
+	font-weight: bold;
+	border: 1px solid #C4CFE5;
+	margin: 2px 0px 2px 0;
+	padding: 2px 10px;
+        white-space: nowrap;
+        vertical-align: top;
+}
+
+/* This is the light bluish-grey */
+/* Powdery blue/grey */
+td.indexvalue {
+	background-color: #EBEFF6;
+	border: 1px solid #C4CFE5;
+	padding: 2px 10px;
+	margin: 2px 0px;
+}
+
+/* Faded powdery blue/grey */
+tr.memlist {
+	background-color: #EEF1F7;
+}
+
+p.formulaDsp {
+	text-align: center;
+}
+
+img.formulaDsp {
+
+}
+
+img.formulaInl {
+	vertical-align: middle;
+}
+
+div.center {
+	text-align: center;
+        margin-top: 0px;
+        margin-bottom: 0px;
+        padding: 0px;
+}
+
+div.center img {
+	border: 0px;
+}
+
+address.footer {
+	text-align: right;
+	padding-right: 12px;
+}
+
+img.footer {
+	border: 0px;
+	vertical-align: middle;
+}
+
+/* @group Code Colorization */
+
+/* Forest green */
+span.keyword {
+	color: #008000
+}
+
+/* Brown */
+span.keywordtype {
+	color: #604020
+}
+
+/* Pumpkin */
+span.keywordflow {
+	color: #e08000
+}
+
+/* Burgandy */
+span.comment {
+	color: #800000
+}
+
+/* Military brown */
+span.preprocessor {
+	color: #806020
+}
+
+/* Navy blue */
+span.stringliteral {
+	color: #002080
+}
+
+/* Teal */
+span.charliteral {
+	color: #008080
+}
+
+/* Chartreuse */
+span.vhdldigit {
+	color: #ff00ff
+}
+
+/* Black */
+span.vhdlchar {
+	color: #000000
+}
+
+/* Purple */
+span.vhdlkeyword {
+	color: #700070
+}
+
+/* Red */
+span.vhdllogic {
+	color: #ff0000
+}
+
+blockquote {
+        background-color: #F7F8FB;
+        border-left: 2px solid #9CAFD4;
+        margin: 0 24px 0 4px;
+        padding: 0 12px 0 16px;
+}
+
+/* @end */
+
+/*
+.search {
+	color: #003399;
+	font-weight: bold;
+}
+
+form.search {
+	margin-bottom: 0px;
+	margin-top: 0px;
+}
+
+input.search {
+	font-size: 75%;
+	color: #000080;
+	font-weight: normal;
+	background-color: #e8eef2;
+}
+*/
+
+td.tiny {
+	font-size: 75%;
+}
+
+/* Darker version of the light bluish-grey */
+.dirtab {
+	padding: 4px;
+	border-collapse: collapse;
+	border: 1px solid #A3B4D7;
+}
+
+/* This is the light bluish-grey */
+th.dirtab {
+	background: #EBEFF6;
+	font-weight: bold;
+}
+
+/* NVIDIA pale table header green */
+hr {
+    height: 0px;
+    border: none;
+    border-top: 3px solid #DDEEBF;
+}
+
+hr.footer {
+	height: 1px;
+}
+
+/* @group Member Descriptions */
+
+table.memberdecls {
+	border-spacing: 0px;
+	padding: 0px;
+}
+
+.memberdecls td, .fieldtable tr {
+	-webkit-transition-property: background-color, box-shadow;
+	-webkit-transition-duration: 0.5s;
+	-moz-transition-property: background-color, box-shadow;
+	-moz-transition-duration: 0.5s;
+	-ms-transition-property: background-color, box-shadow;
+	-ms-transition-duration: 0.5s;
+	-o-transition-property: background-color, box-shadow;
+	-o-transition-duration: 0.5s;
+	transition-property: background-color, box-shadow;
+	transition-duration: 0.5s;
+}
+
+/* Use NVIDIA Green for highlight and glow */
+.memberdecls td.glow, .fieldtable tr.glow {
+	background-color: #76B900;
+	box-shadow: 0 0 15px #76B900;
+}
+/* Very faded slate blue */
+.mdescLeft, .mdescRight,
+.memItemLeft, .memItemRight,
+.memTemplItemLeft, .memTemplItemRight, .memTemplParams {
+	background-color: #F9FAFC;
+	border: none;
+	margin: 4px;
+	padding: 1px 0 0 8px;
+}
+
+/* Dark slate grey */
+.mdescLeft, .mdescRight {
+	padding: 0px 8px 4px 8px;
+	color: #555;
+}
+
+.memSeparator {
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+        line-height: 1px;
+        margin: 0px;
+        padding: 0px;
+}
+
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+}
+
+.memItemRight {
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+}
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+        white-space: nowrap;
+	font-size: 80%;
+}
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+	font-weight: normal;
+	margin-left: 9px;
+}
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+/* This is the light bluish-grey */
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+	background-color: #EBEFF6;
+	border: 1px solid #A3B4D7;
+	text-align: center;
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+	padding: 2px;
+}
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+}
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+        -moz-transition: box-shadow 0.5s linear;
+        -ms-transition: box-shadow 0.5s linear;
+        -o-transition: box-shadow 0.5s linear;
+        transition: box-shadow 0.5s linear;
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+}
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+}
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+        margin-left: 6px;
+}
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+}
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+        border-left: 1px solid #A8B8D9;
+        border-right: 1px solid #A8B8D9;
+        padding: 6px 0px 6px 0px;
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+        font-weight: bold;
+        text-shadow: 0px 1px 1px rgba(255, 255, 255, 0.9);
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+        border-top-right-radius: 4px;
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+        -moz-border-radius-topright: 4px;
+        -moz-border-radius-topleft: 4px;
+        /* webkit specific markup */
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+        -webkit-border-top-right-radius: 4px;
+        -webkit-border-top-left-radius: 4px;
+
+}
+
+/* Even darker version of the light-bluish grey */
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+        -moz-border-radius-bottomright: 4px;
+        -moz-box-shadow: rgba(0, 0, 0, 0.15) 5px 5px 5px;
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+        -webkit-border-bottom-right-radius: 4px;
+        -webkit-box-shadow: 5px 5px 5px rgba(0, 0, 0, 0.15);
+}
+
+dl.reflist dt {
+        padding: 5px;
+}
+
+dl.reflist dd {
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+        padding: 5px;
+}
+
+.paramkey {
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+}
+
+.paramtype {
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+}
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+	white-space: nowrap;
+}
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+}
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+}
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+}
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+}
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+}
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+}
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+}
+
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+	padding: 0px;
+}
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+}
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+}
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+	font-size: 58%;
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+	vertical-align: middle;
+}
+
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+
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+        margin: 10px 0px;
+        border-top: 1px solid #9CAFD4;
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+}
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+}
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+}
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+}
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+}
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+}
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+}
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+        padding-left: 2px;
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+}
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+}
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diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/nv_header.html b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/nv_header.html
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index 0000000..39b75de
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+ * NVIDIA Corporation and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
+ * and any modifications thereto.  Any use, reproduction, disclosure or
+ * distribution of this software and related documentation without an express
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diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/nvidia_legal.md b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/nvidia_legal.md
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+NVIDIA Legal Information
+========================
+
+@tableofcontents
+
+@section legal_notice Notice
+
+ALL NVIDIA DESIGN SPECIFICATIONS, REFERENCE BOARDS, FILES, DRAWINGS,
+DIAGNOSTICS, LISTS, AND OTHER DOCUMENTS (TOGETHER AND SEPARATELY, "MATERIALS")
+ARE BEING PROVIDED "AS IS." NVIDIA MAKES NO WARRANTIES, EXPRESS, IMPLIED,
+STATUTORY, OR OTHERWISE WITH RESPECT TO THE MATERIALS, AND ALL EXPRESS
+OR IMPLIED CONDITIONS, REPRESENTATIONS AND WARRANTIES, INCLUDING ANY IMPLIED
+WARRANTY OR CONDITION OF TITLE, MERCHANTABILITY, SATISFACTORY QUALITY, FITNESS
+FOR A PARTICULAR PURPOSE AND ON-INFRINGEMENT, ARE HEREBY EXCLUDED TO THE
+MAXIMUM EXTENT PERMITTED BY LAW.
+
+Information furnished is believed to be accurate and reliable. However,
+NVIDIA Corporation assumes no responsibility for the consequences of use of
+such information or for any infringement of patents or other rights of third
+parties that may result from its use. No license is granted by implication or
+otherwise under any patent or patent rights of NVIDIA Corporation.
+Specifications mentioned in this publication are subject to change without
+notice. This publication supersedes and replaces all information previously
+supplied. NVIDIA Corporation products are not authorized for use as critical
+components in life support devices or systems without express written
+approval of NVIDIA Corporation.
+
+@section legal_trademarks Trademarks
+
+NVIDIA, the NVIDIA logo, CUDA, DRIVE, Tegra, and TensorRT
+are trademarks or registered
+trademarks of NVIDIA Corporation in the United States and other countries.
+Other company and product names may be trademarks of the respective companies
+with which they are associated.
+
+HDMI, the HDMI logo, and High-Definition Multimedia Interface are trademarks
+or registered trademarks of HDMI Licensing LLC.
+
+ARM, AMBA, and ARM Powered are registered trademarks of ARM Limited.
+Cortex, MPCore and Mali are trademarks of ARM Limited.
+All other brands or product names are the property of their respective holders.
+"ARM" is used to represent ARM Holdings plc; its operating company ARM Limited;
+and the regional subsidiaries ARM Inc.; ARM KK; ARM Korea Limited.; ARM Taiwan Limited;
+ARM France SAS; ARM Consulting (Shanghai) Co. Ltd.; ARM Germany GmbH;
+ARM Embedded Technologies Pvt. Ltd.; ARM Norway, AS and ARM Sweden AB.
+
+@section legal_copyright Copyright
+
+@code
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+@endcode
+
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/nvimages/NVLogo_2D_H.jpg b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/nvimages/NVLogo_2D_H.jpg
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diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/nvimages/Nvidia.ico b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/nvimages/Nvidia.ico
new file mode 100644
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new file mode 100644
index 0000000..2f4dea4
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/nvimages/nv.css
@@ -0,0 +1,134 @@
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+ * Copyright (c) 2007-2021 NVIDIA Corporation.  All rights reserved.
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+ * NVIDIA Corporation and its licensors retain all intellectual property
+ * and proprietary rights in and to this software, related documentation
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+}
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diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/nvimages/spe_fw_arch.png b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/nvimages/spe_fw_arch.png
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diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/spi-app.md b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/spi-app.md
new file mode 100644
index 0000000..e119a83
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/spi-app.md
@@ -0,0 +1,371 @@
+SPI application (app/spi-app.c and app/spi-slv-app.c)
+==============================
+
+@tableofcontents
+
+SPI application demonstrates how to access/manipulate Always On (AON) SPI from
+the SPE/AON processor. SPI2 is in AON domain for both Jetson AGX Orin and Orin Nano.
+SPE/AON processor supports both SPI master and slave driver.
+Note that the application can utilize either the SPI master or SPI slave mode, but not both simultaneously.
+In both demonstrations, the SPI frequency is configured to be 12MHz.
+The SPI master application performs a loopback test, while the SPI slave application requires an SPI master
+to drive it for sending and receiving test data. Both applications send predefined bytes and compare the sent
+bytes with the received ones, displaying a successful message upon a match.
+
+@note It is required to compile device tree and flash board to have device tree
+updated after making kernel device tree changes as described in following
+sections.
+
+
+# Jetson AGX Orin
+
+## Hardware Configuration
+
+SPI Master
+
+User must short MISO and MOSI signals (follow below sections for pin map) in
+order to successfully run this app.
+SPI2 signals are available at connector J3 with below pin mappings.
+
+- Pin E61 - CLK
+- Pin D62 - MISO
+- Pin F60 - MOSI
+- Pin D60 - CS0
+
+SPI Slave
+
+User must connect a SPI master device to SPI2 slave pins available at connector J3 with below pin mappings.
+
+
+- CLK (Master)  -> Pin E61 (CLK) (Slave)
+- MISO (Master) <- Pin D62 (MISO) (Slave)
+- MOSI (Master) -> Pin F60 (MOSI) (Slave)
+- CS0 (Master)  -> Pin D60 (CS0) (Slave)
+
+@note SPI2 operates at a high level of 1.8V. Ensure your SPI master also uses 1.8V, or add a level shifter if using 3.3V.
+
+## Software Configuration
+
+1. Pinmuxing updates are recommended via generating new dtsi files using
+the pinmux spreadsheet.  For the purpose of performing a quick test, the pinmux files can be manually
+updated by editing `${L4T}/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi`.
+
+   SPI Master:
+
+            --- a/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi
+            +++ b/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi
+            @@ -915,18 +915,18 @@
+
+                                    spi2_sck_pcc0 {
+                                            nvidia,pins = "spi2_sck_pcc0";
+            -                               nvidia,function = "rsvd1";
+            -                               nvidia,pull = <TEGRA_PIN_PULL_UP>;
+            -                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
+            -                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+            +                               nvidia,function = "spi2";
+            +                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+            +                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+            +                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                            nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+                                            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
+                                    };
+
+                                    spi2_miso_pcc1 {
+                                            nvidia,pins = "spi2_miso_pcc1";
+            -                               nvidia,function = "rsvd1";
+            -                               nvidia,pull = <TEGRA_PIN_PULL_UP>;
+            +                               nvidia,function = "spi2";
+            +                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                            nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                            nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+            @@ -935,20 +935,20 @@
+
+                                    spi2_mosi_pcc2 {
+                                            nvidia,pins = "spi2_mosi_pcc2";
+            -                               nvidia,function = "rsvd1";
+            -                               nvidia,pull = <TEGRA_PIN_PULL_UP>;
+            -                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
+            -                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+            +                               nvidia,function = "spi2";
+            +                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+            +                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+            +                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                            nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+                                            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
+                                    };
+
+                                    spi2_cs0_pcc3 {
+                                            nvidia,pins = "spi2_cs0_pcc3";
+            -                               nvidia,function = "rsvd1";
+            -                               nvidia,pull = <TEGRA_PIN_PULL_UP>;
+            -                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
+            -                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+            +                               nvidia,function = "spi2";
+            +                               nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+            +                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+            +                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                            nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+                                            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
+                                    };
+
+   SPI Slave:
+
+            --- a/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi
+            +++ b/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3701-0000-a04.dtsi
+            @@ -899,7 +899,7 @@
+
+                                    spi2_sck_pcc0 {
+                                            nvidia,pins = "spi2_sck_pcc0";
+            -                               nvidia,function = "rsvd1";
+            +                               nvidia,function = "spi2";
+                                            nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                            nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+            @@ -909,17 +909,17 @@
+
+                                    spi2_miso_pcc1 {
+                                            nvidia,pins = "spi2_miso_pcc1";
+            -                               nvidia,function = "rsvd1";
+            +                               nvidia,function = "spi2";
+                                            nvidia,pull = <TEGRA_PIN_PULL_UP>;
+            -                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
+            -                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+            +                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+            +                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+                                            nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+                                            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
+                                    };
+
+                                    spi2_mosi_pcc2 {
+                                            nvidia,pins = "spi2_mosi_pcc2";
+            -                               nvidia,function = "rsvd1";
+            +                               nvidia,function = "spi2";
+                                            nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                            nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+            @@ -929,7 +929,7 @@
+
+                                    spi2_cs0_pcc3 {
+                                            nvidia,pins = "spi2_cs0_pcc3";
+            -                               nvidia,function = "rsvd1";
+            +                               nvidia,function = "spi2";
+                                            nvidia,pull = <TEGRA_PIN_PULL_UP>;
+                                            nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                                            nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+
+2. Update gpio configuration as below in `${L4T}/bootloader/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi`:
+
+            --- a/bootloader/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi
+            +++ b/bootloader/tegra234-mb1-bct-gpio-p3701-0000-a04.dtsi
+            @@ -125,10 +125,6 @@
+                                            TEGRA234_AON_GPIO(EE, 6)
+                                            TEGRA234_AON_GPIO(EE, 2)
+                                            TEGRA234_AON_GPIO(EE, 4)
+            -                               TEGRA234_AON_GPIO(CC, 0)
+            -                               TEGRA234_AON_GPIO(CC, 1)
+            -                               TEGRA234_AON_GPIO(CC, 2)
+            -                               TEGRA234_AON_GPIO(CC, 3)
+                                            TEGRA234_AON_GPIO(AA, 0)
+
+3. Modify firewall setting in `${L4T}/bootloader/tegra234-mb2-bct-scr-p3701-0000-override.dts` to allow SPE to read/write to the SPI2 register.
+
+            +++ b/bootloader/tegra234-mb2-bct-scr-p3701-0000-override.dts
+            @@ -24,6 +24,11 @@
+                           value = <0x18000606>;
+                       };
+
+            +          reg@2135 { /* CLK_RST_CONTROLLER_AON_SCR_SPI2_0 */
+            +              exclusion-info = <3>;
+            +              value = <0x30001410>;
+            +          };
+            +
+                       reg@5114 { /* CBB_CENTRAL_CBB_FIREWALL_PWM5_BLF, READ_CTL */
+
+4. For SPI Master app, In `soc/t23x/target_specific.mk`, set `ENABLE_SPI_APP := 1` and rebuild the application. Copy the output to `${L4T}/bootloader/spe_t234.bin`.
+
+   For SPI Slave app, In `soc/t23x/target_specific.mk`, set `ENABLE_SPI_SLV_APP := 1` and rebuild the application. Copy the output to `${L4T}/bootloader/spe_t234.bin`.
+
+
+5. Reflash all partitions to ensure that the pinmux and firewall settings are updated on the board.
+
+@note For SPI Slave app, make sure SPI master is setup first before slave because SCLK is provided from SPI master.
+
+# Jetson Orin Nano
+
+## Hardware Configuration
+
+SPI Master
+
+User must short MISO and MOSI signals (follow below sections for pin map) in
+order to successfully run this app.
+SPI2 signals are available at connector J2 with below pin mappings.
+
+- Pin 126 - CLK
+- Pin 127 - MISO
+- Pin 128 - MOSI
+- Pin 130 - CS0
+
+SPI Slave
+
+User must connect a SPI master device to SPI2 slave pins available at connector J2 with below pin mappings.
+
+
+- CLK (Master)  -> Pin 126 (CLK) (Slave)
+- MISO (Master) <- Pin 127 (MISO) (Slave)
+- MOSI (Master) -> Pin 128 (MOSI) (Slave)
+- CS0 (Master)  -> Pin 130 (CS0) (Slave)
+
+@note SPI2 operates at a high level of 1.8V. Ensure your SPI master also uses 1.8V, or add a level shifter if using 3.3V.
+
+## Software Configuration
+
+1. Pinmuxing updates are recommended via generating new dtsi files using
+the pinmux spreadsheet.  For the purpose of performing a quick test, the pinmux files can be manually
+updated by editing `${L4T}/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi`:
+
+   SPI Master:
+
+            --- a/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi
+            +++ b/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi
+            @@ -608,7 +608,7 @@
+
+                                    spi2_sck_pcc0 {
+                                            nvidia,pins = "spi2_sck_pcc0";
+            -                               nvidia,function = "rsvd1";
+            +                               nvidia,function = "spi2";
+                                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                            nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+            @@ -618,17 +618,17 @@
+
+                                    spi2_miso_pcc1 {
+                                            nvidia,pins = "spi2_miso_pcc1";
+            -                               nvidia,function = "rsvd1";
+            +                               nvidia,function = "spi2";
+                                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+            -                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+            -                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+            +                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
+            +                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                            nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+                                            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
+                                    };
+
+                                    spi2_mosi_pcc2 {
+                                            nvidia,pins = "spi2_mosi_pcc2";
+            -                               nvidia,function = "rsvd1";
+            +                               nvidia,function = "spi2";
+                                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                            nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+           @@ -638,7 +638,7 @@
+
+                                   spi2_cs0_pcc3 {
+                                            nvidia,pins = "spi2_cs0_pcc3";
+            -                               nvidia,function = "rsvd1";
+            +                               nvidia,function = "spi2";
+                                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                            nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+
+   SPI Slave:
+
+            --- a/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi
+            +++ b/bootloader/generic/BCT/tegra234-mb1-bct-pinmux-p3767-dp-a03.dtsi
+            @@ -608,17 +608,17 @@
+
+                                    spi2_sck_pcc0 {
+                                            nvidia,pins = "spi2_sck_pcc0";
+            -                               nvidia,function = "rsvd1";
+            +                               nvidia,function = "spi2";
+                                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+            -                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+            -                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+            +                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
+            +                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                            nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+                                            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
+                                    };
+
+                                    spi2_miso_pcc1 {
+                                            nvidia,pins = "spi2_miso_pcc1";
+            -                               nvidia,function = "rsvd1";
+            +                               nvidia,function = "spi2";
+                                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+                                            nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                                            nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+            @@ -628,20 +628,20 @@
+
+                                    spi2_mosi_pcc2 {
+                                            nvidia,pins = "spi2_mosi_pcc2";
+            -                               nvidia,function = "rsvd1";
+            +                               nvidia,function = "spi2";
+                                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+            -                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+            -                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+            +                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
+            +                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                            nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+                                            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
+                                    };
+
+                                    spi2_cs0_pcc3 {
+                                            nvidia,pins = "spi2_cs0_pcc3";
+            -                               nvidia,function = "rsvd1";
+            +                               nvidia,function = "spi2";
+                                            nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+            -                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+            -                               nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+            +                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
+            +                               nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+                                            nvidia,io-high-voltage = <TEGRA_PIN_DISABLE>;
+                                            nvidia,lpdr = <TEGRA_PIN_DISABLE>;
+                                    };
+
+2. Update gpio configuration as below in `${L4T}/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi`:
+
+          --- a/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi
+          +++ b/bootloader/tegra234-mb1-bct-gpio-p3767-dp-a03.dtsi
+          @@ -91,13 +91,9 @@
+                                          TEGRA234_AON_GPIO(EE, 4)
+                                          >;
+                                  gpio-output-low = <
+          -                               TEGRA234_AON_GPIO(CC, 0)
+          -                               TEGRA234_AON_GPIO(CC, 2)
+          -                               TEGRA234_AON_GPIO(CC, 3)
+                                          TEGRA234_AON_GPIO(AA, 4)
+                                          >;
+                                  gpio-output-high = <
+          -                               TEGRA234_AON_GPIO(CC, 1)
+                                          TEGRA234_AON_GPIO(AA, 5)
+                                          TEGRA234_AON_GPIO(BB, 3)
+                                          >;
+
+
+3. Modify firewall setting in `${L4T}/bootloader/tegra234-mb2-bct-scr-p3767-0000.dts` to allow SPE to read/write to the SPI2 register.
+
+            +++ b/bootloader/tegra234-mb2-bct-scr-p3767-0000.dts
+            @@ -810,6 +810,10 @@
+                                  exclusion-info = <0>;
+                                  value = <0x00000000>;
+                                  };
+            +                     reg@2135 { /* CLK_RST_CONTROLLER_AON_SCR_SPI2_0 */
+            +                     exclusion-info = <3>;
+            +                     value = <0x30001410>;
+            +                     };
+                                  reg@2228 { /* CLK_RST_CONTROLLER_ERR_COLLATOR_FSI_SCR_EC_SCR_0 */
+                                  exclusion-info = <0>;
+
+4. For SPI Master app, In `soc/t23x/target_specific.mk`, set `ENABLE_SPI_APP := 1` and rebuild the application. Copy the output to `${L4T}/bootloader/spe_t234.bin`.
+
+  For SPI Slave app, In `soc/t23x/target_specific.mk`, set `ENABLE_SPI_SLV_APP := 1` and rebuild the application. Copy the output to `${L4T}/bootloader/spe_t234.bin`.
+
+5. Reflash all partitions to ensure that the pinmux and firewall settings are updated on the board.
+
+@note For SPI Slave app, make sure SPI master is setup first before slave because SCLK is provided from SPI master.
+
+# Result
+The demo app sends predefined data and considers the test successful if it retrieves the same data.
+For the SPI Master application, it will display "SPI test successful" and for the SPI Slave
+application, it will display "SPI Slave test passed."
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/third_party_legal.md b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/third_party_legal.md
new file mode 100644
index 0000000..cd4e6d0
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/third_party_legal.md
@@ -0,0 +1,62 @@
+Open Source and Third-Party Licenses
+====================================
+@tableofcontents
+
+FreeRTOS is provided under the terms of the MIT license. The copy of the
+license is provided in FreeRTOS License section below.
+
+Application software, including Jetson Sensor Processing Engine
+support and sample code, is provided under the following terms:
+
+Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+* Redistributions of source code must retain the above copyright
+notice, this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in the
+documentation and/or other materials provided with the
+distribution.
+* Neither the name of NVIDIA CORPORATION nor the names of its
+contributors may be used to endorse or promote products derived
+from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND
+ANY
+EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL,
+EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
+USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
+DAMAGE.
+
+# FreeRTOS License #
+
+MIT License
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of
+this software and associated documentation files (the "Software"), to deal in
+the Software without restriction, including without limitation the rights to
+use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
+of the Software, and to permit persons to whom the Software is furnished to do
+so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
\ No newline at end of file
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/timer-app.md b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/timer-app.md
new file mode 100644
index 0000000..0640acd
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/timer-app.md
@@ -0,0 +1,15 @@
+Timer application (app/timer-app.c)
+===================================
+
+Application demonstrates the timer driver APIs and uses timer2 in 5 seconds
+periodic mode.
+
+The `ENABLE_TIMER_APP` flag in the `soc/*/target_specific.mk file`
+controls compilation of this demo app.
+
+When the app successfully executes, it
+displays the following message at every `TIMER2_PTV` seconds
+
+    Timer2 irq triggered
+
+Additionally, it calls the timer stop API after the count value reaches `STOP_TIMER`.
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/welcome.md b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/welcome.md
new file mode 100644
index 0000000..a38ae2f
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/doc/welcome.md
@@ -0,0 +1,96 @@
+@mainpage Welcome
+
+# Introduction #
+Welcome to the <i>Jetson Sensor Processing Engine (SPE) Developer Guide</i>.
+
+NVIDIA<sup>&reg;</sup> Jetson<sup>&trade;</sup>
+provides a built-in Cortex-R5 micro-controller within an always-on
+power domain known as Sensor Processing Engine (SPE) or AON Cluster. Example use cases
+SPE may enable includes sensor data processing, wake up management, UAV, robotics.
+
+SPE micro-controller has the following configurations:
+- ARM V7-R ISA
+- 32-kilobyte Instruction cache
+- 32-kilobyte Data cache
+- 256-kilobyte SRAM attached to TCM interface
+- Vectored Interrupt
+- 64-bit AXI master interface for DRAM request
+- 32-bit AXI master interface for MMIO request
+- 200MHz maximum and operating core clock speed
+
+The number of SPE peripherals and their instances will vary based on the Jetson
+platform.
+
+The AON cluster includes the following peripherals:
+- General purpose timers, Watchdog timer, Timestamp engine
+- I2C, SPI, CAN, UART, GPIO, PWM
+- DMIC (for voice wake functionality)
+
+@note SPE Software Development Kit may not implement or provide support for all
+the above peripherals.
+
+For detailed information on the SPE,
+see <i>NVIDIA Technical Reference Manual (TRM)</i> for the Jetson platform.
+
+# Supported Features by Platform
+
+|                 |  AGX Orin | Orin Nano |
+|-----------------|:---------:|:---------:|
+| AODMIC          |    [x]    |           |
+| GPIO            |    [x]    |    [x]    |
+| I2C             |    [x]    |    [x]    |
+| IVC             |    [x]    |    [x]    |
+| SC7-aodmic wake |    [x]    |           |
+| Timer           |    [x]    |    [x]    |
+| GTE             |    [x]    |    [x]    |
+| SPI             |    [x]    |    [x]    |
+| CAN             |           |           |
+| UART            |           |           |
+
+@note
+All the features of Orin Nano devkit can be applied to Orin NX module + Orin Nano carrier board
+
+Only the above platforms are supported.
+
+# The SPE BSP (Board Support Package) or SDK (Software development kit) #
+The SPE firmware is FreeRTOS V10.4.3 based. The SPE release package has
+following directory structure.
+- fsp/source: This includes common drivers, operating system and CPU
+abstraction layers. The FSP (firmware support package) details can be found at
+[FSP](doc/fsp.md). The relevant subdirectories are as
+follows:
+  - drivers: The common peripheral drivers.
+  - include: Header files, includes drivers, CPL (CPU Abstraction Layer) and OSA
+  (Operating System Abstraction) headers.
+  - soc: The SOC (system on chip) specific source codes.
+- rt-aux-cpu-demo-fsp: It includes demo peripheral apps, common drivers which
+are not part of the fsp, platform specific source code.
+  - app: Demo apps for the supported peripherals.
+  - doc: Documents.
+  - drivers: Common drivers which could not be part of the fsp/source.
+  - include: Header files
+  - platform: platform specific source code.
+  - soc: The chip specific sources and header files.
+  - FreeRTOSConfig.h: FreeRTOS config file.
+  - main.c: The application entry point.
+  - Makefile/target_specific.mk: The build system.
+- FreeRTOSV10.4.3/FreeRTOS/Source: FreeRTOS source code.
+
+## The SPE firmware layered view ##
+The overall architecture is as described in below
+![The SPE Firmware Overview](nvimages/spe_fw_arch.png)
+- \*rt-aux-cpu-demo-fsp/app does not include all the peripheral demo apps.
+  - There are multiple instances available for some peripherals as well on
+  chip hardware modules, for that detail, please follow chip specific
+  technical reference manual which should also list instance number falling
+  under SPE/AON domain. AON stands for always on and it can be interchangeably
+  used with SPE in this and other documents.
+- Where,
+  - IVC: Inter VM Communication, used to communicate with other on chip
+  processors through memory channels.
+  - TKE: Time Keeping Engine; follow SOC Technical reference manual for
+  more details.
+  - AST: Address Space Translation Unit; follow SOC Technical reference
+  manual for more details.
+  - HSP: Hardware Synchronization Primitives; follow SOC Technical reference
+  manual for more details.
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/bpmp-ipc.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/bpmp-ipc.c
new file mode 100644
index 0000000..05fd082
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/bpmp-ipc.c
@@ -0,0 +1,204 @@
+/* Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+
+#include <address_map_new.h>
+#include <err-hook.h>
+#include <hsp/hsp-tegra.h>
+#include <processor/hsp-tegra-hw.h>
+#include <misc/bitops.h>
+#include <mbox-aon.h>
+#include <reg-access/reg-access.h>
+
+#include <bpmp-ipc.h>
+#include <bpmp-ipc-protocol.h>
+#include <spe-pm.h>
+
+#include <dbgprintf.h>
+#include <ospl/rtos-port.h>
+#include <osa/rtos-queue.h>
+#include <osa/rtos-task.h>
+
+#define MAX_MESSAGES	31
+
+struct bpmp_ipc_msg {
+	uint32_t data;
+	bool dir_bpmp_to_spe;
+};
+
+static rtosQueueHandle bpmp_ipc_queue;
+
+static void bpmp_ipc_irq(void *dummy, hsp_sm_data_t *data)
+{
+	struct bpmp_ipc_msg msg;
+	rtosPortBaseType higher_prio_task_woken;
+	(void)dummy;
+
+	tegra_hsp_sm_vacate(&tegra_hsp_id_aon, MBOX_AON_BPMP);
+	data->sm.val &= ~MBOX_TAG_BIT;
+
+	msg.data = data->sm.val;
+	msg.dir_bpmp_to_spe = true;
+	if (rtosQueueSendToBackFromISR(bpmp_ipc_queue, &msg,
+		 &higher_prio_task_woken) != pdPASS)
+		error_hook("xQueueSendFromISR() failed");
+
+	portYIELD_FROM_ISR(higher_prio_task_woken);
+}
+
+void bpmp_ipc_send_now_from_isr(uint32_t data)
+{
+	tegra_hsp_sm_produce(&tegra_hsp_id_bpmp, MBOX_BPMP_BPMP, data);
+}
+
+void bpmp_ipc_send_now(uint32_t data)
+{
+	rtosTaskEnterCritical();
+	tegra_hsp_sm_produce(&tegra_hsp_id_bpmp, MBOX_BPMP_BPMP, data);
+	rtosTaskEnterCritical();
+}
+
+int bpmp_ipc_send_from_isr(uint32_t data,
+	rtosPortBaseType *higher_prio_task_woken)
+{
+	struct bpmp_ipc_msg msg;
+	int ret = 0;
+
+	msg.data = data;
+	msg.dir_bpmp_to_spe = false;
+	if (rtosQueueSendToBackFromISR(bpmp_ipc_queue, &msg,
+		higher_prio_task_woken) != pdPASS) {
+		error_hook("xQueueSendToBack() failed");
+		ret = -1;
+	}
+
+	return ret;
+}
+
+int bpmp_ipc_send(uint32_t data)
+{
+	struct bpmp_ipc_msg msg;
+	int ret = 0;
+
+	msg.data = data;
+	msg.dir_bpmp_to_spe = false;
+	if (rtosQueueSendToBack(bpmp_ipc_queue, &msg, 0) != pdPASS) {
+		error_hook("xQueueSendToBack() failed");
+		ret = -1;
+	}
+
+	return ret;
+}
+
+static void bpmp_ipc_task_process_ipc_queue(struct bpmp_ipc_msg *msg)
+{
+	if (msg->dir_bpmp_to_spe) {
+		switch (msg->data) {
+		case BPMP_IPC_MSG_BPMP_PING:
+			dbgprintf("ping successful from BPMP to SPE\r\n");
+			bpmp_ipc_send_now(BPMP_IPC_MSG_SPE_PING);
+			break;
+		case BPMP_IPC_MSG_SPE_PING_ACK:
+			dbgprintf("ping successful from SPE to BPMP\r\n");
+			break;
+		case BPMP_IPC_MSG_DRAM_WAKE_REQ_ACK:
+			dbgprintf("DRAM awake msg from BPMP\r\n");
+			/* FIXME: Is this the right call for DRAM awake */
+			spe_exit_sc7();
+			break;
+		case BPMP_IPC_MSG_SC7_ENTRY:
+			dbgprintf("BPMP informing SPE of SC7 entry\r\n");
+			spe_prepare_enter_sc7();
+			break;
+		case BPMP_IPC_MSG_SC7_EXIT:
+			dbgprintf("BPMP informing SPE of SC7 exit\r\n");
+			spe_exit_sc7();
+			break;
+		default:
+			error_hookf("Invalid IPC message from BPMP: %u\r\n", (unsigned int)msg->data);
+			break;
+		}
+	} else {
+		if (msg->data <= 0 || msg->data > BPMP_IPC_MSG_ID_MAX) {
+			error_hookf("SPE -> BPMP: Invalid IPC message: %u\r\n", (unsigned int)msg->data);
+			return;
+		}
+		dbgprintf("SPE -> BPMP: %u\r\n", (unsigned int)msg->data);
+		bpmp_ipc_send_now(msg->data);
+	}
+}
+
+static void bpmp_ipc_task(void *pvParameters)
+{
+	(void)pvParameters;
+	struct bpmp_ipc_msg msg;
+	rtosPortBaseType qret;
+
+	for (;;) {
+		qret = rtosQueueReceive(bpmp_ipc_queue, &msg, rtosMAX_DELAY);
+		if (qret != pdTRUE) {
+			error_hook("xQueueReceive() failed");
+			continue;
+		}
+		bpmp_ipc_task_process_ipc_queue(&msg);
+	}
+}
+
+int bpmp_ipc_init(void)
+{
+	rtosPortBaseType xStatus;
+	rtosTaskParameters bpmp_ipc_task_params = {
+		.pvTaskCode = &bpmp_ipc_task,
+		.pcTaskName = (char *)"bpmp_ipc_task",
+		.uxPriority = 2,
+		.pvParameters = NULL,
+		.uxStackDepthBytes = 512,
+	};
+
+	rtosQueueCreate(NULL, 0, MAX_MESSAGES,
+			sizeof(struct bpmp_ipc_msg), &bpmp_ipc_queue);
+	if (!bpmp_ipc_queue) {
+		error_hook("BPMP IPC xQueueCreate() failed");
+		return -1;
+	}
+
+	xStatus = rtosTaskCreate(&bpmp_ipc_task_params, NULL);
+	if (!xStatus) {
+		error_hook("bpmp_ipc_task creation failed");
+		rtosQueueDelete(bpmp_ipc_queue);
+		bpmp_ipc_queue = NULL;
+		return -1;
+	}
+
+	tegra_hsp_sm_full_enable(&tegra_hsp_id_aon, MBOX_AON_BPMP, bpmp_ipc_irq,
+			NULL);
+
+	return 0;
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/gte-tegra-ids.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/gte-tegra-ids.c
new file mode 100644
index 0000000..e925ddc
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/gte-tegra-ids.c
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <address_map_new.h>
+
+#include <processor/irqs-hw.h>
+#include <gte-tegra-priv.h>
+
+struct tegra_gte tegra_gte_aon = {
+	.id = {
+		.devname = "gte",
+		.base_addr = NV_ADDRESS_MAP_AON_GTE_BASE,
+		.irq = NV_AON_INTERRUPT_GTE,
+	},
+};
+extern struct tegra_gte_id tegra_gte_id_aon __attribute__((alias("tegra_gte_aon")));
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/gte-tegra.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/gte-tegra.c
new file mode 100644
index 0000000..716a965
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/gte-tegra.c
@@ -0,0 +1,208 @@
+/*
+ * Copyright (c) 2015-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+
+#include <argte_aps.h>
+#include <misc/nvrm_drf.h>
+#include <misc/bitops.h>
+
+#include <delay/delay.h>
+#include <err-hook.h>
+#include <gte-tegra-priv.h>
+#include <irq/safe-irqs.h>
+#include <misc/macros.h>
+#include <reg-access/reg-access.h>
+
+#define GTE_APS_SLICE_SIZE	(BASE_ADDRESS_GTE_APS_SLICE1 - BASE_ADDRESS_GTE_APS_SLICE0)
+
+struct tegra_gte_fifo_msg tegra_gte_msg;
+
+static inline uint32_t tegra_gte_readl(struct tegra_gte_id *id, uint32_t reg)
+{
+	return readl(id->base_addr + reg);
+}
+
+static inline void tegra_gte_writel(struct tegra_gte_id *id, uint32_t val, uint32_t reg)
+{
+	writel(val, id->base_addr + reg);
+}
+
+void tegra_gte_slice_set_enable_mask(struct tegra_gte_id *id, uint8_t slice, uint32_t bitmap)
+{
+	tegra_gte_writel(id, bitmap, (slice * GTE_APS_SLICE_SIZE) + GTE_APS_SLICE0_TETEN_0);
+}
+
+static void tegra_gte_get_status(struct tegra_gte_id *id, uint8_t *occupancy, bool *int_sts)
+{
+	uint32_t val;
+
+	val = tegra_gte_readl(id, GTE_APS_TESTATUS_0);
+
+	*int_sts = NV_DRF_VAL(GTE_APS, TESTATUS, INTERRUPT, val);
+	*occupancy = NV_DRF_VAL(GTE_APS, TESTATUS, OCCUPANCY, val);
+}
+
+static void tegra_gte_read_fifo(struct tegra_gte_id *id, struct tegra_gte_ts *ts)
+{
+	uint32_t encv, tsc_hi, tsc_lo;
+
+	encv = tegra_gte_readl(id, GTE_APS_TEENCV_0);
+
+	tsc_hi = tegra_gte_readl(id, GTE_APS_TETSCH_0);
+	tsc_lo = tegra_gte_readl(id, GTE_APS_TETSCL_0);
+	ts->tsc = (((uint64_t)tsc_hi) << 32) | tsc_lo;
+
+	tegra_gte_writel(id, GTE_APS_TECMD_0_CMD_POP, GTE_APS_TECMD_0);
+
+	ts->slice = NV_DRF_VAL(GTE_APS, TEENCV, SLICE, encv);
+	ts->bit_index = NV_DRF_VAL(GTE_APS, TEENCV, BITINDEX, encv);
+	ts->bit_dir = NV_DRF_VAL(GTE_APS, TEENCV, FALLING, encv);
+	ts->invalid = NV_DRF_VAL(GTE_APS, TEENCV, INVALID, encv);
+}
+
+void tegra_gte_irq(void *data)
+{
+	struct tegra_gte_id *id = data;
+	/* struct tegra_gte_id assumed to be first field in tegra_gte */
+	struct tegra_gte *gte_dev = (struct tegra_gte *)id;
+	struct tegra_gte_ts ts_data;
+	uint8_t occupancy, i;
+	bool int_sts;
+
+	tegra_gte_get_status(id, &occupancy, &int_sts);
+	for (i = 0; i < occupancy; i++) {
+		tegra_gte_read_fifo(id, &ts_data);
+		if (gte_dev->irq_callback)
+			gte_dev->irq_callback(gte_dev->irq_data, &ts_data);
+	}
+}
+
+void tegra_gte_dma_complete_handler(void *callback_param,
+				    enum dma_status status)
+{
+	/* struct tegra_gte_id assumed to be first field in tegra_gte */
+	struct tegra_gte *gte_dev = (struct tegra_gte *)callback_param;
+	struct tegra_gte_ts ts;
+	uint32_t tsc_lo, tsc_hi, acv;
+
+	if (status != DMA_STATUS_COMPLETE) {
+		error_hook("dma transter failed");
+		return;
+	}
+
+	ts.invalid = 0;
+	tsc_lo = tegra_gte_msg.tsc_lo;
+	tsc_hi = tegra_gte_msg.tsc_hi;
+	ts.tsc = (((uint64_t)tsc_hi) << 32) | tsc_lo;
+	ts.slice = NV_DRF_VAL(GTE_APS, TESRC, SLICE, tegra_gte_msg.src);
+	acv = tegra_gte_msg.pcv ^ tegra_gte_msg.ccv;
+
+	while (acv) {
+		ts.bit_index = __builtin_ctz(acv);
+		if ((tegra_gte_msg.pcv >> ts.bit_index) & BIT(0))
+			ts.bit_dir = 1;
+		else
+			ts.bit_dir = 0;
+		gte_dev->irq_callback(gte_dev->irq_data, &ts);
+		acv &= ~BIT(ts.bit_index);
+	}
+
+	gte_dev->dma_xfer((void *)gte_dev->id.base_addr, (void *)&tegra_gte_msg,
+			  sizeof(tegra_gte_msg), 8, 8);
+}
+
+error_t tegra_gte_setup(struct tegra_gte_id *id, uint32_t occupancy_threshold,
+		    tegra_gte_callback irq_callback,
+		    void *irq_data,
+		    tegra_gte_dma_xfer dma_xfer,
+		    bool dma_en)
+{
+	error_t ret = 0;
+	/* struct tegra_gte_id assumed to be first field in tegra_gte */
+	struct tegra_gte *gte_dev = (struct tegra_gte *)id;
+	uint32_t val;
+
+	if (occupancy_threshold &
+	    ~GTE_APS_TECTRL_0_OCCUPANCYTHRESHOLD_DEFAULT_MASK) {
+		error_hook("occupancy_threshold exceeds MAX value");
+		ret = 1;
+		goto out;
+	}
+
+	if (!irq_callback) {
+		error_hook("irq_callback is NULL");
+		ret = 1;
+		goto out;
+	}
+
+	gte_dev->irq_callback = irq_callback;
+	gte_dev->irq_data = irq_data;
+
+	if (dma_en) {
+		if (!dma_xfer) {
+			error_hook("dma_xfer is NULL");
+			ret = 1;
+			goto out;
+		}
+		gte_dev->dma_xfer = dma_xfer;
+		ret = irq_safe_disable(id->irq);
+		if (ret != E_SUCCESS) {
+			goto out;
+		}
+
+		val =
+			NV_DRF_NUM(GTE_APS, TECTRL, ENABLE, 1) |
+			NV_DRF_NUM(GTE_APS, TECTRL, INTERRUPTENABLE, 1) |
+			NV_DRF_NUM(GTE_APS, TECTRL, AUTOADVENABLE, 1) |
+			NV_DRF_NUM(GTE_APS, TECTRL, AUTOADVADDR, 3) |
+			NV_DRF_NUM(GTE_APS, TECTRL, OCCUPANCYTHRESHOLD, 1);
+		tegra_gte_writel(id, val, GTE_APS_TECTRL_0);
+
+		gte_dev->dma_xfer((void *)id->base_addr, (void *)&tegra_gte_msg,
+			  sizeof(tegra_gte_msg), 8, 8);
+	}
+	else {
+		val =
+			NV_DRF_NUM(GTE_APS, TECTRL, ENABLE, 1) |
+			NV_DRF_NUM(GTE_APS, TECTRL, INTERRUPTENABLE, 1) |
+			NV_DRF_NUM(GTE_APS, TECTRL, AUTOADVENABLE, 0) |
+			NV_DRF_NUM(GTE_APS, TECTRL, AUTOADVADDR, 0) |
+			NV_DRF_NUM(GTE_APS, TECTRL, OCCUPANCYTHRESHOLD, occupancy_threshold);
+		tegra_gte_writel(id, val, GTE_APS_TECTRL_0);
+
+		ret = irq_safe_set_handler(id->irq, tegra_gte_irq, id);
+		if (ret == E_SUCCESS) {
+			ret = irq_safe_enable(id->irq);
+		}
+	}
+
+out:
+	return ret;
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/i2c-port.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/i2c-port.c
new file mode 100644
index 0000000..5367a16
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/i2c-port.c
@@ -0,0 +1,350 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <irq/safe-irqs.h>
+#include <osa/rtos-mutex.h>
+#include <osa/rtos-values.h>
+#include <clk/clk-tegra.h>
+#include <delay/delay.h>
+#include <error/common-errors.h>
+#include <misc/macros.h>
+#include <tke/tke-tegra.h>
+#include <debug/assert.h>
+
+/* Module-specific FSP header files */
+#include <i2c/i2c-config.h>
+#include <i2c/i2c-tegra.h>
+#include <i2c/i2c.h>
+#include <port/i2c-port.h>
+#include <processor/i2c-tegra-hw.h>
+#include <soc-common/i2c-dependencies.h>
+
+#define I2C_NUM_CTRL	2
+
+struct i2c_config_data pi2c_config_data[I2C_NUM_CTRL];
+struct i2c_tegra_handle hi2c_tegra_all[I2C_NUM_CTRL];
+struct i2c_handle hi2c_all[I2C_NUM_CTRL];
+static bool irq_raised[I2C_NUM_CTRL];
+static rtosMutexHandle rwlock[I2C_NUM_CTRL];
+static uint8_t MutexBuffer[I2C_NUM_CTRL][rtosMutexSize()];
+
+error_t appfw_mutex_create(uint32_t ctrl_id);
+
+/* VALID_I2C_IDS are defined in the cluster specific i2c-port.h file */
+static inline bool is_valid_i2c_id(uint32_t ctrl_id)
+{
+    bool ret;
+
+    if (ctrl_id < I2C_MAX_CTRLS) {
+        ret = (BIT(ctrl_id) & VALID_I2C_IDS) > 0U;
+    } else {
+        ret = false;
+    }
+
+    return ret;
+}
+
+static uint32_t map_id(uint32_t ctrl_id)
+{
+	uint32_t ret;
+
+	switch (ctrl_id) {
+	case 2U:
+		ret = 0U;
+		break;
+	case 8U:
+		ret = 1U;
+		break;
+	default:
+		/* Invalid Entry */
+		ret = 2U;
+		break;
+	}
+
+	return ret;
+}
+
+error_t appfw_wait_irq(uint32_t ctrl_id, uint32_t timeout_us)
+{
+	error_t ret = E_TIMEOUT;
+	uint64_t timer_start;
+	uint64_t timer_cur;
+	const struct i2c_hw_handle *hi2c_hw = i2c_get_hw_handle(ctrl_id);
+
+	if (!is_valid_i2c_id(ctrl_id)) {
+		ret = E_INVALID_PARAM;
+		goto out;
+	}
+
+	ret = irq_safe_enable(hi2c_hw->irq_no);
+	if (ret != E_SUCCESS)
+		goto out;
+
+	timer_start = appfw_timer_cur_us();
+	do {
+		if (irq_raised[(map_id(ctrl_id))]) {
+			ret = E_SUCCESS;
+			break;
+		}
+		timer_cur = appfw_timer_cur_us();
+	} while ((timer_cur - timer_start) < timeout_us);
+
+	irq_raised[map_id(ctrl_id)] = false;
+	ret = irq_safe_disable(hi2c_hw->irq_no);
+
+out:
+	return ret;
+}
+
+error_t appfw_mutex_acquire(uint32_t ctrl_id, uint32_t timeout)
+{
+	error_t ret;
+
+	if (!is_valid_i2c_id(ctrl_id)) {
+		ret = E_INVALID_PARAM;
+		goto out;
+	}
+
+	ret = rtosMutexAcquire(rwlock[map_id(ctrl_id)],
+		(uint32_t)tegra_tke_convert_usecs_to_ticks((const uint64_t)timeout));
+
+	if (ret == rtosPASS)
+		ret = E_SUCCESS;
+
+out:
+	return ret;
+}
+
+error_t appfw_mutex_release(uint32_t ctrl_id)
+{
+	error_t ret;
+
+	if (!is_valid_i2c_id(ctrl_id)) {
+		ret = E_INVALID_PARAM;
+		goto out;
+	}
+
+	ret = rtosMutexRelease(rwlock[map_id(ctrl_id)]);
+	if (ret == rtosPASS)
+		ret = E_SUCCESS;
+
+out:
+	return ret;
+}
+
+error_t appfw_mutex_create(uint32_t ctrl_id)
+{
+	error_t ret;
+
+	if (!is_valid_i2c_id(ctrl_id)) {
+		ret = E_INVALID_PARAM;
+		goto out;
+	}
+
+	ret = rtosMutexCreate(MutexBuffer[map_id(ctrl_id)],
+			      &rwlock[map_id(ctrl_id)]);
+	if (ret == rtosPASS)
+		ret = E_SUCCESS;
+
+out:
+	return ret;
+}
+
+uint64_t appfw_timer_cur_us(void)
+{
+	return tegra_tke_get_usec();
+}
+
+void appfw_udelay(uint32_t delay)
+{
+	udelay(delay);
+}
+
+error_t appfw_clk_reset_pulse(uint32_t ctrl_id, uint32_t delay)
+{
+	error_t ret;
+	const struct i2c_hw_handle *hi2c_hw = i2c_get_hw_handle(ctrl_id);
+
+	if (!is_valid_i2c_id(ctrl_id)) {
+		ret = E_INVALID_PARAM;
+		goto out;
+	}
+
+	ret = tegra_clk_reset_pulse(hi2c_hw->rst_data, delay);
+
+out:
+	return ret;
+}
+
+int64_t appfw_configure_ctrl_clk_rate(uint32_t ctrl_id)
+{
+	error_t ret;
+	const struct i2c_hw_handle *hi2c_hw = i2c_get_hw_handle(ctrl_id);
+	struct i2c_config_data *config_data = i2c_get_config_data(ctrl_id);
+
+	if (!is_valid_i2c_id(ctrl_id)) {
+		ret = E_INVALID_PARAM;
+		goto out;
+	}
+
+	ret = tegra_clk_set_rate(hi2c_hw->clk_data,
+				 config_data->ctrl_clk_rate);
+	if (ret != 0)
+		ret = E_INVALID_PARAM;
+	else
+		ret = config_data->ctrl_clk_rate;
+
+out:
+	return ret;
+}
+
+error_t appfw_clk_enable(uint32_t ctrl_id)
+{
+	error_t ret;
+	const struct i2c_hw_handle *hi2c_hw = i2c_get_hw_handle(ctrl_id);
+
+	if (!is_valid_i2c_id(ctrl_id)) {
+		ret = E_INVALID_PARAM;
+		goto out;
+	}
+
+	ret = tegra_clk_enable(hi2c_hw->clk_data);
+
+out:
+	return ret;
+}
+
+error_t appfw_clk_disable(uint32_t ctrl_id)
+{
+	error_t ret;
+	const struct i2c_hw_handle *hi2c_hw = i2c_get_hw_handle(ctrl_id);
+
+	if (!is_valid_i2c_id(ctrl_id)) {
+		ret = E_INVALID_PARAM;
+		goto out;
+	}
+
+	ret = tegra_clk_disable(hi2c_hw->clk_data);
+
+out:
+	return ret;
+}
+
+static void tegra_i2c_irq(void *id)
+{
+	struct i2c_hw_handle *hi2c_hw = id;
+	uint32_t ctrl_id = hi2c_hw->ctrl_id;
+
+	irq_raised[map_id(ctrl_id)] = true;
+	tegra_i2c_irq_handler (ctrl_id);
+}
+
+void appfw_irq_enable(uint32_t ctrl_id)
+{
+    const struct i2c_hw_handle *hi2c_hw = i2c_get_hw_handle(ctrl_id);
+
+    (void)irq_safe_enable(hi2c_hw->irq_no);
+}
+
+void appfw_irq_disable(uint32_t ctrl_id)
+{
+    const struct i2c_hw_handle *hi2c_hw = i2c_get_hw_handle(ctrl_id);
+
+    (void)irq_safe_disable(hi2c_hw->irq_no);
+}
+
+struct i2c_tegra_handle *i2c_get_tegra_handle(uint32_t ctrl_id)
+{
+	struct i2c_tegra_handle *ret;
+
+	if (!is_valid_i2c_id(ctrl_id)) {
+		ret = NULL;
+		goto out;
+	}
+
+	hi2c_tegra_all[map_id(ctrl_id)].ctrl_id = ctrl_id;
+	ret = &hi2c_tegra_all[map_id(ctrl_id)];
+
+out:
+	return ret;
+}
+
+error_t appfw_port_init(uint32_t ctrl_id)
+{
+	error_t ret;
+	const struct i2c_hw_handle *hi2c_hw = i2c_get_hw_handle(ctrl_id);
+
+	if (!is_valid_i2c_id(ctrl_id)) {
+		ret = E_INVALID_PARAM;
+		goto out;
+	}
+
+	ret = irq_safe_set_handler(hi2c_hw->irq_no, tegra_i2c_irq,
+				   (void *)hi2c_hw);
+	if (ret != E_SUCCESS) {
+		i2c_pr_error("%s: failed to set handler, ret - 0x%x\n", __func__,
+						(int32_t)ret);
+		goto out;
+	}
+
+	ret = appfw_mutex_create(ctrl_id);
+	if (ret != E_SUCCESS) {
+		i2c_pr_error("%s: failed to acquire mutex, ret - 0x%x\n", __func__,
+						(int32_t)ret);
+		goto out;
+	}
+
+out:
+	return ret;
+}
+
+struct i2c_config_data *i2c_get_config_data(uint32_t ctrl_id)
+{
+	struct i2c_config_data *ret;
+
+	if (!is_valid_i2c_id(ctrl_id)) {
+		ret = NULL;
+		goto out;
+	}
+
+	pi2c_config_data[map_id(ctrl_id)].bus_clk_rate = 100000U;
+	pi2c_config_data[map_id(ctrl_id)].ctrl_clk_rate = 136000000U;
+	pi2c_config_data[map_id(ctrl_id)].hs_master_code = 0U;
+	ret = &pi2c_config_data[map_id(ctrl_id)];
+
+out:
+	return ret;
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/irq-handlers.S b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/irq-handlers.S
new file mode 100644
index 0000000..d9d7ae8
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/irq-handlers.S
@@ -0,0 +1,68 @@
+/* Copyright (c) 2015-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+.macro vic0_irq_handlers, num
+.if \num
+	vic0_irq_handlers "(\num-1)"
+
+	push	{r0-r3, ip, lr}
+	bl	spe_vic0_dispatch
+.endif
+.endm
+
+.macro vic1_irq_handlers, num
+.if \num
+	vic1_irq_handlers "(\num-1)"
+
+	push	{r0-r3, ip, lr}
+	bl	spe_vic1_dispatch
+.endif
+.endm
+
+	.section .text
+	.global spe_vic0_vectors
+	.global spe_vic0_vectors_end
+	.global spe_vic1_vectors
+	.global spe_vic1_vectors_end
+spe_vic0_dispatch:
+	adr	r0, (spe_vic0_vectors + 8)
+	sub	r0, lr, r0
+	lsr	r0, r0, #3
+	bl	spe_vic0_irq_handler
+	b	irq_end
+spe_vic0_vectors:
+	vic0_irq_handlers	32
+spe_vic0_vectors_end:
+spe_vic1_dispatch:
+	adr	r0, (spe_vic1_vectors + 8)
+	sub	r0, lr, r0
+	lsr	r0, r0, #3
+	bl	spe_vic1_irq_handler
+	b	irq_end
+spe_vic1_vectors:
+	vic1_irq_handlers	32
+spe_vic1_vectors_end:
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/ivc-channels.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/ivc-channels.c
new file mode 100644
index 0000000..c258b6a
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/ivc-channels.c
@@ -0,0 +1,205 @@
+/*
+ * Copyright (c) 2015-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include <address_map_new.h>
+
+#include <ast/tegra-ast.h>
+#include <araps_ast.h>
+#include <cpu/barriers.h>
+#include <err-hook.h>
+#include <debug/printf-isr.h>
+#include <tegra-ivc.h>
+#include <hsp/hsp-tegra.h>
+#include <processor/hsp-tegra-hw.h>
+#include <misc/bitops.h>
+
+#include <clk.h>
+#include <ivc-config.h>
+#include <ivc-channels.h>
+#include <mbox-aon.h>
+#include <dbgprintf.h>
+
+static bool ast_inited;
+static void *ccplex_task_states[IVC_NUM_CCPLEX_CHS];
+
+static int ivc_init_channels_from_ram_ccplex(BaseType_t *higher_prio_task_woken)
+{
+	int i, ret = 0;
+
+	for (i = 0; i < IVC_NUM_CCPLEX_CHS; i++) {
+		if (tegra_ivc_init_channel_from_ram(ivc_ccplex_task_ids[i]->ivc_ch)) {
+			error_hookf("tegra_ivc_init_channel_from_ram(%s) failed",
+					ivc_ccplex_task_ids[i]->name);
+			ret = -1;
+			continue;
+		}
+		if (ccplex_task_states[i] && ivc_ccplex_task_ids[i]->ops->init_complete)
+			ivc_ccplex_task_ids[i]->ops->init_complete(ccplex_task_states[i],
+					higher_prio_task_woken);
+	}
+
+	return ret;
+}
+
+static int ivc_channels_ivc_notified_ccplex_ns(BaseType_t *higher_prio_task_woken)
+{
+	int ret = -1;
+	int i;
+
+	for (i = 0; i < IVC_NUM_CCPLEX_CHS; i++)
+		if (ccplex_task_states[i] &&
+				ivc_ccplex_task_ids[i]->ops->notify)
+			ret = ivc_ccplex_task_ids[i]->ops->notify(
+					ccplex_task_states[i],
+					higher_prio_task_woken);
+
+	return ret;
+}
+
+static int ivc_carveout_ast_setup(uint32_t phys_addr, uint32_t carveout_size)
+{
+	if (carveout_size & (carveout_size - 1)) {
+		error_hookf("Carveout size not a power of 2: %lx", carveout_size);
+		return -1;
+	}
+
+	if (carveout_size < AST_MIN_CARVEOUT_SIZE) {
+		error_hookf("Carveout size is too small: %lx", carveout_size);
+		return -1;
+	}
+
+	if (phys_addr & (carveout_size - 1)) {
+		error_hookf("Carveout is not aligned: %lx/%lx", phys_addr, carveout_size);
+		return -1;
+	}
+
+	/*
+	 * The bootloader is responsible for initializing:
+	 *	- AST region 0 to point at SPE SYSRAM carve-out.
+	 *	- AST region 1 to point at SPE GSC DRAM carve-out.
+	 * The SPE firmware is responsible for initializing:
+	 *	- AST region 2 to point at the IVC carve-out in DRAM.
+	 */
+	if (tegra_ast_enable_region_vmindex(AST_IVC_REGION,
+			phys_addr, CCPLEX_CARVEOUT_BASE,
+			carveout_size, AST_INSTANCE_R5_AND_DMA, AON_STREAMID)) {
+		error_hook("AST init failed");
+		return -1;
+	}
+
+	barrier_memory_complete();
+
+	return 0;
+}
+
+static void ivc_ccplex_carveout_configure(BaseType_t *higher_prio_task_woken)
+{
+	static int count = 0;
+	uint32_t carveout_base;
+	uint32_t carveout_size;
+	int ret;
+
+	count++;
+	if (count > 1)
+		return;
+	ret = tegra_hsp_ss_read(&tegra_hsp_id_aon, IVC_CARVEOUT_BASE_SS_INDEX,
+				&carveout_base);
+	if (ret)
+		goto err;
+	tegra_hsp_ss_clear(&tegra_hsp_id_aon, IVC_CARVEOUT_BASE_SS_INDEX,
+				carveout_base);
+	ret = tegra_hsp_ss_read(&tegra_hsp_id_aon, IVC_CARVEOUT_SIZE_SS_INDEX,
+				&carveout_size);
+	if (ret)
+		goto err;
+	tegra_hsp_ss_clear(&tegra_hsp_id_aon, IVC_CARVEOUT_SIZE_SS_INDEX,
+				carveout_size);
+	dbgprintf_isr("carveout_addr : %x size : %x\r\n",
+			(unsigned int)carveout_base,
+			(unsigned int)carveout_size);
+	if (ivc_carveout_ast_setup(carveout_base, carveout_size))
+		return;
+	ivc_init_channels_from_ram_ccplex(higher_prio_task_woken);
+	ast_inited = true;
+	return;
+err:
+	error_hook("Error reading shared semaphore\n");
+}
+
+static void ccplex_ipc_irq(void *dummy, hsp_sm_data_t *data)
+{
+	BaseType_t higher_prio_task_woken;
+	(void)dummy;
+
+	tegra_hsp_sm_vacate(AON_CCPLEX_IVC_HSP_ID, MBOX_AON_CCPLEX_IVC_RX);
+	data->sm.val &= ~MBOX_TAG_BIT;
+
+	if (data->sm.val == SMBOX_IVC_READY_MSG) {
+		ivc_ccplex_carveout_configure(&higher_prio_task_woken);
+		clk_init_hw();
+	} else if (data->sm.val == SMBOX_IVC_NOTIFY) {
+		ivc_channels_ivc_notified_ccplex_ns(&higher_prio_task_woken);
+	} else {
+		error_hook("spurious MBOX irq");
+	}
+
+	portYIELD_FROM_ISR(higher_prio_task_woken);
+}
+
+int hsp_ivc_notify_ccplex(struct tegra_ivc_channel *channel, bool is_read)
+{
+	tegra_hsp_ss_set(&tegra_hsp_id_aon, IVC_NOTIFY_TX_SS, BIT(channel->channel_group));
+	tegra_hsp_sm_produce(AON_CCPLEX_IVC_HSP_ID, MBOX_AON_CCPLEX_IVC_TX,
+				SMBOX_IVC_NOTIFY);
+	return 0;
+}
+
+int ivc_init_channels_ccplex(void)
+{
+	int i;
+	int ret = 0;
+
+	for (i = 0; i < IVC_NUM_CCPLEX_CHS; i++) {
+		if (ivc_ccplex_task_ids[i]->ops->init) {
+			ccplex_task_states[i] = ivc_ccplex_task_ids[i]->ops->init(
+					ivc_ccplex_task_ids[i]);
+			if (!ccplex_task_states[i]) {
+				error_hookf("ivc: %s init failed",
+						ivc_ccplex_task_ids[i]->name);
+				ret = -1;
+			}
+		}
+	}
+	tegra_hsp_sm_full_enable(AON_CCPLEX_IVC_HSP_ID, MBOX_AON_CCPLEX_IVC_RX, ccplex_ipc_irq,
+					NULL);
+
+	return ret;
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/spe-pm.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/spe-pm.c
new file mode 100644
index 0000000..87193e9
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/spe-pm.c
@@ -0,0 +1,266 @@
+/* Copyright (c) 2015-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <string.h>
+
+#include <address_map_new.h>
+#include <araopm.h>
+#include <artke_top.h>
+#include <misc/nvrm_drf.h>
+
+#include <debug/debug.h>
+
+#include <irq/safe-irqs.h>
+#include <processor/irqs-hw.h>
+#include <cpu/cache.h>
+#include <delay/delay.h>
+#include <err-hook.h>
+#include <misc/bitops.h>
+#include <reg-access/reg-access.h>
+#include <spe-pm.h>
+#include <bpmp-ipc.h>
+#include <bpmp-ipc-protocol.h>
+#include <spe-vic.h>
+#include <wake-tegra.h>
+#include <wake-tegra-hw.h>
+
+#include <dbgprintf.h>
+#include <osa/rtos-event-group.h>
+#include <osa/rtos-task.h>
+
+#include <tcu.h>
+
+enum scx_state {
+	SC0,
+	SC7,
+};
+
+static enum scx_state current_soc_state = SC0;
+
+static void wake_trigger_soc_wake(void)
+{
+	tegra_wake_trigger_wake_event(&tegra_wake_id_wake);
+}
+
+/*
+ * FreeRTOS doesn't have condition variables. Here, we're using event groups
+ * to have similar functionality. Instead of a mutex, we're disabling/enabling
+ * interrupts for atomicity. Signal and wait functions for condition variables
+ * are replaced by xEventGroupWaitBits and xEventGroupSetBits, respectively.
+ *
+ * This relies on the fact that this port can context switch when interrupts are
+ * disabled. The interrupt disabled/enabled state is saved and restored over a
+ * context switch. The end result acts similar to atomically dropping and
+ * reacquiring a mutex when calling cond_wait.
+ */
+static rtosEventGroupHandle dram_events;
+static int num_dram_users = 0;
+static bool dram_is_available = true;
+static bool wake_triggered = false;
+
+#define EVENT_DRAM_USABLE_BIT (1 << 0)
+#define EVENT_DRAM_ACCESS_COMPLETE_BIT (1 << 1)
+
+#define EVENT_DRAM_ALL_BITS (EVENT_DRAM_USABLE_BIT | \
+			     EVENT_DRAM_ACCESS_COMPLETE_BIT)
+
+
+bool try_request_dram_access_from_isr(void)
+{
+	/*
+	 * This assumes that we don't have any nested interrupts, i.e all
+	 * interrupts are masked during the execution of this ISR.
+	 */
+	bool ret = dram_is_available;
+
+	if (ret) {
+		num_dram_users++;
+		rtosEventGroupClearBitsFromISR(dram_events,
+				EVENT_DRAM_ACCESS_COMPLETE_BIT, NULL);
+	}
+
+	return ret;
+}
+
+bool try_request_dram_access(void)
+{
+	bool ret;
+
+	rtosTaskEnterCritical();
+
+	ret = dram_is_available;
+	if (ret) {
+		num_dram_users++;
+		rtosEventGroupClearBits(dram_events,
+				EVENT_DRAM_ACCESS_COMPLETE_BIT);
+	}
+
+	rtosTaskExitCritical();
+	return ret;
+}
+
+void request_dram_access(void)
+{
+	rtosTaskEnterCritical();
+	num_dram_users++;
+	rtosEventGroupClearBits(dram_events, EVENT_DRAM_ACCESS_COMPLETE_BIT);
+	while (!dram_is_available) {
+		if (wake_triggered) {
+			rtosEventGroupWaitBits(dram_events,
+					       EVENT_DRAM_USABLE_BIT,
+					       pdFALSE,
+					       pdFALSE,
+					       NULL,
+					       rtosMAX_DELAY);
+			continue;
+		}
+
+		switch (current_soc_state) {
+		case SC7:
+			wake_trigger_soc_wake();
+			wake_triggered = true;
+			break;
+
+		case SC0:
+		default:
+			error_hook("Invalid SoC state!");
+		}
+	}
+	rtosTaskExitCritical();
+}
+
+bool dram_access_complete_from_isr(BaseType_t *woken)
+{
+	/*
+	 * This assumes that we don't have any nested interrupts, i.e all
+	 * interrupts are masked during the execution of this ISR.
+	 */
+	if (num_dram_users <= 0) {
+		error_hook("Unbalanced or too many calls to dram_access_complete*");
+		return false;
+	}
+
+	if (--num_dram_users != 0)
+		return true;
+
+	if (rtosEventGroupSetBitsFromISR(dram_events,
+			EVENT_DRAM_ACCESS_COMPLETE_BIT, woken) == pdFAIL) {
+		num_dram_users++;
+		return false;
+	}
+
+	return true;
+}
+
+void dram_access_complete(void)
+{
+	rtosTaskEnterCritical();
+
+	if (num_dram_users <= 0) {
+		error_hook("Unbalanced or too many calls to dram_access_complete*");
+	} else if (--num_dram_users == 0) {
+		rtosEventGroupSetBits(dram_events,
+				      EVENT_DRAM_ACCESS_COMPLETE_BIT);
+	}
+	rtosTaskExitCritical();
+}
+
+/* Interrupts should be disabled before calling this function */
+static void block_dram_access_from_isr(void)
+{
+	rtosEventGroupClearBits(dram_events,
+				EVENT_DRAM_USABLE_BIT);
+
+	while (num_dram_users > 0)
+		rtosEventGroupWaitBits(dram_events,
+				       EVENT_DRAM_ACCESS_COMPLETE_BIT,
+				       pdTRUE,
+				       pdFALSE,
+				       NULL,
+				       rtosMAX_DELAY);
+
+	dram_is_available = false;
+}
+
+/* Interrupts should be disabled before calling this function */
+static void allow_dram_access_from_isr(void)
+{
+	dram_is_available = true;
+	wake_triggered = false;
+	rtosEventGroupSetBits(dram_events, EVENT_DRAM_USABLE_BIT);
+}
+
+void spe_prepare_enter_sc7(void)
+{
+	rtosTaskEnterCritical();
+	dbgprintf("spe entering sc7\r\n");
+	block_dram_access_from_isr();
+	current_soc_state = SC7;
+	rtosTaskExitCritical();
+
+	pm_suspend_sc7();
+
+	tcu_suspend();
+
+	if (get_cache_power_status() == PM_RAM_ON)
+		cache_disable();
+	pm_turn_off_caches();
+	bpmp_ipc_send(BPMP_IPC_MSG_SC7_ENTRY_ACK);
+}
+
+void spe_exit_sc7(void)
+{
+	tcu_resume();
+
+	dbgprintf("spe exiting sc7\r\n");
+	pm_turn_on_caches();
+	if (get_cache_power_status() == PM_RAM_ON)
+		cache_enable();
+
+	pm_resume_sc7();
+
+	rtosTaskEnterCritical();
+	allow_dram_access_from_isr();
+	current_soc_state = SC0;
+	rtosTaskExitCritical();
+}
+
+int spe_pm_init(void)
+{
+	rtosEventGroupCreate(NULL, &dram_events);
+	if (!dram_events) {
+		error_hook("Couldn't create event queue for dram access.");
+		return 1;
+	}
+
+	rtosEventGroupClearBits(dram_events, EVENT_DRAM_ALL_BITS);
+
+	pm_hw_init();
+
+	return 0;
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/spe-vic.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/spe-vic.c
new file mode 100644
index 0000000..21f3538
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/spe-vic.c
@@ -0,0 +1,79 @@
+/* Copyright (c) 2015-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+
+#include <araps_vic.h>
+#include <address_map_new.h>
+
+#include <cpu/arm-vic.h>
+#include <misc/bitops.h>
+#include <reg-access/reg-access.h>
+
+#include <irq/safe-irqs.h>
+#include <spe-vic.h>
+
+#define NUM_VIC_IRQS	32
+
+void spe_vic0_irq_handler(unsigned int irq)
+{
+	irq_handler(irq);
+
+	writel(0, vic_base_addr[0] + APS_VIC_VICADDRESS_0);
+}
+
+void spe_vic1_irq_handler(unsigned int irq)
+{
+	irq_handler(irq + 32);
+
+	writel(0, vic_base_addr[1] + APS_VIC_VICADDRESS_0);
+	writel(0, vic_base_addr[0] + APS_VIC_VICADDRESS_0);
+}
+
+extern void spe_vic0_vectors(void);
+extern void spe_vic0_vectors_end(void);
+extern void spe_vic1_vectors(void);
+extern void spe_vic1_vectors_end(void);
+
+void spe_vic_init(void)
+{
+	uint32_t vic0_vector_size;
+	uint32_t vic1_vector_size;
+	int i;
+	void (*vic0_vector)(void) = spe_vic0_vectors;
+	void (*vic1_vector)(void) = spe_vic1_vectors;
+
+	vic0_vector_size = ((uint32_t)spe_vic0_vectors_end - (uint32_t)spe_vic0_vectors) / NUM_VIC_IRQS;
+	vic1_vector_size = ((uint32_t)spe_vic1_vectors_end - (uint32_t)spe_vic1_vectors) / NUM_VIC_IRQS;
+
+	for (i = 0; i < 32; i++) {
+		arm_vic_set_isr_vect_addr(vic_base_addr[0], i, vic0_vector);
+		arm_vic_set_isr_vect_addr(vic_base_addr[1], i, vic1_vector);
+		vic0_vector = (void (*)(void))((uint32_t) vic0_vector + vic0_vector_size);
+		vic1_vector = (void (*)(void))((uint32_t) vic1_vector + vic1_vector_size);
+	}
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/wake-tegra.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/wake-tegra.c
new file mode 100644
index 0000000..66e5bc0
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/drivers/wake-tegra.c
@@ -0,0 +1,119 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+
+#include <arwake.h>
+
+#include <misc/nvrm_drf.h>
+#include <misc/macros.h>
+#include <misc/bitops.h>
+#include <reg-access/reg-access.h>
+
+#include <wake-tegra.h>
+
+/*
+ * Current arwake.h is out of date and need to correct below registers
+ * Once arwake.h is updated, below registers define should be removed
+ */
+#undef WAKE_AOWAKE_TIER0_ROUTING_31_0_0
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0	0x4B4
+#undef WAKE_AOWAKE_TIER1_ROUTING_31_0_0
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0	0x4C0
+#undef WAKE_AOWAKE_DET_EN_0
+#define WAKE_AOWAKE_DET_EN_0			0x4F0
+
+#define TIER_SIZE \
+	(WAKE_AOWAKE_TIER1_ROUTING_31_0_0 - WAKE_AOWAKE_TIER0_ROUTING_31_0_0)
+
+static inline uint32_t tegra_wake_readl(struct tegra_wake_id *id, uint32_t reg)
+{
+	uint32_t wake_base = (uint32_t)id;
+
+	return readl(wake_base + reg);
+}
+
+static inline void tegra_wake_writel(struct tegra_wake_id *id, uint32_t val, uint32_t reg)
+{
+	uint32_t wake_base = (uint32_t)id;
+
+	writel(val, wake_base + reg);
+}
+
+void tegra_wake_route_event(struct tegra_wake_id *id, uint32_t wake_event,
+				  uint32_t tier, bool sel)
+{
+	uint32_t val, reg;
+
+	reg = WAKE_AOWAKE_TIER0_ROUTING_31_0_0 + (tier * TIER_SIZE);
+	reg += (wake_event / 32) * 4;
+	val = tegra_wake_readl(id, reg);
+	if (sel)
+		val |= BIT(wake_event % 32);
+	else
+		val &= ~BIT(wake_event % 32);
+	tegra_wake_writel(id, val, reg);
+}
+
+void tegra_wake_enable_event(struct tegra_wake_id *id, uint32_t wake_event)
+{
+	uint32_t reg;
+
+	reg = WAKE_AOWAKE_MASK_W_0 + (wake_event * 4);
+	tegra_wake_writel(id, WAKE_AOWAKE_MASK_W_0_MASK_UNMASK, reg);
+}
+
+void tegra_wake_disable_event(struct tegra_wake_id *id, uint32_t wake_event)
+{
+	uint32_t reg;
+
+	reg = WAKE_AOWAKE_MASK_W_0 + (wake_event * 4);
+	tegra_wake_writel(id, WAKE_AOWAKE_MASK_W_0_MASK_MASK, reg);
+}
+
+void tegra_wake_enable(struct tegra_wake_id *id)
+{
+	tegra_wake_writel(id, WAKE_AOWAKE_DET_EN_0_DET_ENABLE_TRUE,
+			  WAKE_AOWAKE_DET_EN_0);
+}
+
+void tegra_wake_disable(struct tegra_wake_id *id)
+{
+	tegra_wake_writel(id, WAKE_AOWAKE_DET_EN_0_DET_ENABLE_FALSE,
+			  WAKE_AOWAKE_DET_EN_0);
+}
+
+void tegra_wake_clear_irq(struct tegra_wake_id *id, uint32_t wake_event)
+{
+	tegra_wake_writel(id, 1, WAKE_AOWAKE_STATUS_W_0 + (wake_event * 4));
+}
+
+void tegra_wake_trigger_wake_event(struct tegra_wake_id *id)
+{
+	tegra_wake_writel(id, 1, WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0);
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/bpmp-ipc-protocol.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/bpmp-ipc-protocol.h
new file mode 100644
index 0000000..2225fb0
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/bpmp-ipc-protocol.h
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _BPMP_IPC_PROTOCOL_H_
+#define _BPMP_IPC_PROTOCOL_H_
+
+/*
+ * The handshake protocol (light weight IPC) between BPMP and
+ * SPE uses shared mail box, so that a different interrupt is
+ * used for this version instead of doorbell interrupts. We
+ * will be using two mail boxes, one for SPE -> BPMP and the
+ * other for BPMP -> SPE
+ */
+
+/*
+ *		SPE SHARED MAILBOX REGISTER: MBOX0
+ *
+ *			BPMP -> SPE
+ *
+ * When BPMP wishes to send a handshake message to SPE, it writes
+ * the message to DATA fild of MBOX0 and sets the TAG field
+ */
+
+/*
+ *		SPE SHARED MAILBOX REGISTER: MBOX1
+ *
+ *			SPE -> BPMP
+ *
+ * When SPE wishes to send a handshake message to SPE, it writes
+ * the message to DATA fild of MBOX1 and sets the TAG field
+ */
+
+/*
+ * The following macros indicate the message received.
+ * As we are using two mailboxes we can use the same
+ * message for ack while sending to BPMP
+ */
+
+/* MSG from SPE to BPMP */
+#define BPMP_IPC_MSG_BPMP_PING_ACK		1
+#define BPMP_IPC_MSG_DRAM_WAKE_REQ		2
+#define BPMP_IPC_MSG_SPE_PING			3
+#define BPMP_IPC_MSG_SC7_ENTRY_ACK		6
+#define BPMP_IPC_MSG_SC7_EXIT_ACK		7
+#define BPMP_IPC_MSG_ID_MAX			9
+
+/* MSG from BPMP to SPE */
+#define BPMP_IPC_MSG_BPMP_PING			1
+#define BPMP_IPC_MSG_DRAM_WAKE_REQ_ACK		2
+#define BPMP_IPC_MSG_SPE_PING_ACK		3
+#define BPMP_IPC_MSG_SC7_ENTRY			6
+#define BPMP_IPC_MSG_SC7_EXIT			7
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/bpmp-ipc.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/bpmp-ipc.h
new file mode 100644
index 0000000..5ca17a0
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/bpmp-ipc.h
@@ -0,0 +1,39 @@
+/* Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _BPMP_IPC_H_
+#define _BPMP_IPC_H_
+
+#include <stdbool.h>
+
+int bpmp_ipc_init(void);
+int bpmp_ipc_send(uint32_t data);
+int bpmp_ipc_send_from_isr(uint32_t data, BaseType_t *higher_prio_task_woken);
+void bpmp_ipc_send_now(uint32_t data);
+void bpmp_ipc_send_now_from_isr(uint32_t data);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/clk.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/clk.h
new file mode 100644
index 0000000..c6f9884
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/clk.h
@@ -0,0 +1,33 @@
+/* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef CLK_H
+#define CLK_H
+
+void clk_init_hw(void);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/dbgprintf.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/dbgprintf.h
new file mode 100644
index 0000000..1411d54
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/dbgprintf.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifdef ENABLE_DEBUG_PRINT
+#define dbgprintf printf
+#define dbgprintf_isr printf_isr
+#else
+static inline void dbgprintf(const char *fmt, ...)
+{
+}
+static inline void dbgprintf_isr(const char *fmt, ...)
+{
+}
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/debug_init.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/debug_init.h
new file mode 100644
index 0000000..aee858c
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/debug_init.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _DEBUG_INIT_H
+#define _DEBUG_INIT_H
+
+#include <stdint.h>
+
+void debug_early_init(void);
+void debug_init(uint32_t reg);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/dma.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/dma.h
new file mode 100644
index 0000000..1150c90
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/dma.h
@@ -0,0 +1,82 @@
+/*
+* Copyright (c) 2015-2022 NVIDIA CORPORATION.  All rights reserved.
+*
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+#ifndef _DMA_H_
+#define _DMA_H_
+
+/*
+ * This header defines the part of the DMA API that is common between DMA
+ * controller drivers.
+ *
+ * Since different DMA HW has different capabilities, the mechanism to control
+ * a DMA driver (i.e. initialize the driver, and initiate transfers) differs
+ * between drivers, and hence is not currently unified here.
+ *
+ * However, to simplify code that is portable across multiple DMA HW, certain
+ * status codes and callback types are unified here.
+ */
+
+/*
+ * The completion status of a DMA transfer.
+ *
+ * These values will be returned by DMA driver function which initiated DMA
+ * transfers. For asynchronous transfers, the value returned represents the
+ * status of submitting the request to the hardware. For synchronous
+ * transfers, the value returned represents the overall status of the
+ * transaction.
+ *
+ * For asynchronous transfers, these values will also be passed to the caller-
+ * supplied completion callback.
+ *
+ *                Ret async    Ret sync    Async callback
+ * NOT_INITIATED: Y            Y           N
+ * EXECUTING:     Y            N           N
+ * COMPLETE:      N            Y           Y
+ * ABORTED:       N            N           Y
+ * TIMEOUT:       N            Y           N
+ */
+enum dma_status {
+	DMA_STATUS_NOT_INITIATED,
+	DMA_STATUS_EXECUTING,
+	DMA_STATUS_COMPLETE,
+	DMA_STATUS_ABORTED,
+	DMA_STATUS_TIMEOUT,
+};
+
+/*
+ * The type of a function to call whenever a DMA transfer has completed.
+ *
+ * Parameters:
+ * callback_param:	A copy of a value passed to the DMA driver function
+ * 			that initiated the transfer. Clients may used this to
+ * 			pass context to the DMA completion callback.
+ * status:		Status of the transfer.
+ */
+typedef void dma_callback(void *callback_param, enum dma_status status);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/err-hook.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/err-hook.h
new file mode 100644
index 0000000..0aa6672
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/err-hook.h
@@ -0,0 +1,143 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef INCLUDED_ERR_HOOK_H
+#define INCLUDED_ERR_HOOK_H
+
+#include <stdbool.h>
+
+/*
+ * This header defines APIs that code can use to report errors or warnings
+ * that are discovered at run-time.
+ *
+ * This can be especially useful when an error is detected by code that has no
+ * way to report the error. For example, if an ISR attempts to send a message
+ * to a task so that it can handle the interrupt, but sending the message
+ * fails.
+ *
+ * It is expected that a variety of back-ends will implement these functions.
+ * One might simply printf the message to a log/UART for a developer to see.
+ * Another might reboot the CPU/SoC if a fatal error is detected, in order to
+ * attempt recovery.
+ *
+ * Irrespective of the backend, a developer might set a breakpoint in these
+ * functions in order to see whenever any kind of problem occurred.
+ */
+
+/*
+ * Don't call these; they're just protoypes for the user accessible functions
+ * below to use.
+ */
+void bug_hook_imp(const char *file, int line, const char *function,
+	const char *msg)
+	__attribute__ ((noreturn));
+void bug_hookf_imp(const char *file, int line, const char *function,
+	const char *msg, ...)
+	__attribute__ ((format (__printf__, 4, 5)))
+	__attribute__ ((noreturn));
+void error_hook_imp(const char *file, int line, const char *function,
+	const char *msg);
+void error_hookf_imp(const char *file, int line, const char *function,
+	const char *msg, ...)
+	__attribute__ ((format (__printf__, 4, 5)));
+void error_hookf_once_imp(bool *once,
+	const char *file, int line, const char *function, const char *msg, ...)
+	__attribute__ ((format (__printf__, 5, 6)));
+void warning_hook_imp(const char *file, int line, const char *function,
+	const char *msg);
+void warning_hookf_imp(const char *file, int line, const char *function,
+	const char *msg, ...)
+	__attribute__ ((format (__printf__, 4, 5)));
+void warning_hookf_once_imp(bool *once,
+	const char *file, int line, const char *function, const char *msg, ...)
+	__attribute__ ((format (__printf__, 5, 6)));
+
+/*
+ * The following are macros so that we can later decide to conditionally
+ * remove the parameters for production code (e.g. #indef DEBUG), if we wish.
+ */
+
+#ifndef FILENAME
+#define FILENAME __FILE__
+#endif
+
+/*
+ * Halt CPU until reset
+ */
+void halt_on_bug(void)
+	__attribute__ ((noreturn));
+
+/*
+ * Report that an fatal error occurred, along with a brief description of the
+ * problem.
+ */
+#define bug_hook(msg) \
+	bug_hook_imp(FILENAME, __LINE__, __func__, msg)
+
+#define bug_hookf(...) \
+	bug_hookf_imp(FILENAME, __LINE__, __func__, __VA_ARGS__)
+
+/*
+ * Report that an error occurred, along with a brief description of the
+ * problem.
+ */
+#define error_hook(msg) \
+	error_hook_imp(FILENAME, __LINE__, __func__, msg)
+
+#define error_hookf(...) \
+	error_hookf_imp(FILENAME, __LINE__, __func__, __VA_ARGS__)
+
+#define error_hookf_once(...) do { \
+		static bool once_ ## __LINE__; \
+		if (!once_ ##__LINE__) { \
+			error_hookf_once_imp(&once_ ## __LINE__, \
+					FILENAME, __LINE__, __func__, \
+					__VA_ARGS__); \
+		} \
+	} while(false)
+
+/*
+ * Report that a non-fatal problem occurred, along with a brief description of
+ * the problem.
+ */
+#define warning_hook(msg) \
+	warning_hook_imp(FILENAME, __LINE__, __func__, msg)
+
+#define warning_hookf(...) \
+	warning_hookf_imp(FILENAME, __LINE__, __func__, __VA_ARGS__)
+
+#define warning_hookf_once(...) do { \
+		static bool once_ ## __LINE__;	\
+		if (!once_ ##__LINE__) { \
+			warning_hookf_once_imp(&once_ ## __LINE__, \
+					FILENAME, __LINE__, __func__, \
+					__VA_ARGS__); \
+		}; \
+	} while(false)
+
+#endif	/* INCLUDED_ERR_HOOK_H */
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/gte-tegra-priv.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/gte-tegra-priv.h
new file mode 100644
index 0000000..4cc87ec
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/gte-tegra-priv.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2015-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _GTE_TEGRA_PRIV_H_
+#define _GTE_TEGRA_PRIV_H_
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <gte-tegra.h>
+
+struct tegra_gte_id {
+	const char *devname;
+	uint32_t base_addr;
+	uint32_t irq;
+};
+
+struct tegra_gte
+{
+	/*
+	 * The driver relies on this being the first field, since it casts
+	 * pointers between structs tegra_gte_id and tegra_gte.
+	 */
+	struct tegra_gte_id id;
+	tegra_gte_callback *irq_callback;
+	void *irq_data;
+	tegra_gte_dma_xfer *dma_xfer;
+};
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/gte-tegra.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/gte-tegra.h
new file mode 100644
index 0000000..a20c432
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/gte-tegra.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2015-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _GTE_TEGRA_H_
+#define _GTE_TEGRA_H_
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <dma.h>
+#include <error/common-errors.h>
+
+struct tegra_gte_id;
+
+/*
+ * Structure for GTE timestamp data
+ *
+ * Field:
+ * tsc:       Value of TSC for the captured event
+ * slice:     Indicate the slice for the captured event
+ * bit_index: Bit index in the slice of bit that flipped between the current
+ *            and previous value
+ * bit_dir:   Direction of the change for the identified bit
+ *            0: rising edge
+ *            1: falling edge
+ * invalid:   Indicates that the other field do not carry any valid information
+ */
+struct tegra_gte_ts {
+	uint64_t tsc;
+	uint8_t slice;
+	uint8_t bit_index;
+	bool bit_dir;
+	bool invalid;
+};
+
+/*
+ * This structure represents the in-memory layout of a message extracted from
+ * the GTE FIFO
+ */
+struct tegra_gte_fifo_msg {
+	uint32_t ctrl;
+	uint32_t tsc_hi;
+	uint32_t tsc_lo;
+	uint32_t src;
+	uint32_t ccv;
+	uint32_t pcv;
+	uint32_t encv;
+	uint32_t cmd;
+};
+
+/*
+ * IRQ callback function
+ *
+ * Parameters:
+ * data:      data context for irq
+ * ts_data:   FIFO data will be stored here
+  */
+typedef void tegra_gte_callback(void *data, struct tegra_gte_ts *ts_data);
+
+/*
+ * DMA transfer function
+ *
+ * Parameters:
+ * *src:           The source address to read from
+ * *dst:           The target address to write to
+ * len:            The number of bytes to be transferred.
+ * io_burst_size:  The number of words to transfer in each burst.
+ * src_addr_wrap:  The number of word transfers to make before wrapping
+ *                 the src address. 0 represents no wrap.
+ *                 Legal values for io addr wrap are 2^n with n from
+ *                 0 through 6.
+ *                 Legal values for mc addr wrap are 2^n with n from
+ *                 5 through 11.
+ * Returns:
+ * An enum dma_status value. See dma.h for details.
+ */
+typedef enum dma_status tegra_gte_dma_xfer(void *src, void *dst, uint32_t len,
+					   uint32_t io_burst_size,
+					   uint32_t src_addr_wrap);
+
+/*
+ * Tegra GTE driver
+ *
+ * To use this driver without DMA
+ * 1. Call tegra_gte_slice_set_enable_mask to enable which events to be monitored.
+ * 2. Call tegra_gte_setup with "dma_en = 0".
+ *
+ * To use this driver with DMA
+ * 1. Initialize DMA.
+ * 2. Implement a dma transfer function as asynchronous transfer and call.
+ *    tegra_gte_dma_complete_handler once the transfer is done.
+ * 3. Call tegra_gte_slice_set_enable_mask to enable which events to be monitored.
+ * 4. Call tegra_gte_setup with a dma transfer fucntion pointer
+ *    and set "dma_en = 1".
+ */
+
+/*
+ * DMA conplete handler
+ *
+ * This function should be called once dma transfer is done
+ * Parameters:
+ * callback_param:      GTE ID
+ * status:              An enum dma_status value. See dma.h for details.
+ */
+void tegra_gte_dma_complete_handler(void *callback_param, enum dma_status status);
+
+/*
+ * Initialize GTE
+ *
+ * Parameters:
+ * id:                  GTE ID
+ * occupancy_threshold: Generate an interrupt if the FIFO occupancy is larger
+ *                      than this limit. Only valid for DMA is diabled.
+ * irq_callback:        callback function for interrupt.
+ * irq_data:            data context for interrupt.
+ * dma_xfer:            DMA transfer fucntion
+ * dma_en:              Enable DMA function
+ *
+ * Returns:
+ * 0:                   Success
+ * Non-zero:            Error
+ */
+error_t tegra_gte_setup(struct tegra_gte_id *id, uint32_t occupancy_threshold,
+		    tegra_gte_callback irq_callback,
+		    void *irq_data,
+		    tegra_gte_dma_xfer dma_xfer,
+		    bool dma_en);
+
+/*
+ * Enable events to be monitored
+ */
+void tegra_gte_slice_set_enable_mask(struct tegra_gte_id *id, uint8_t slice, uint32_t bitmap);
+
+/*
+ * GTE interrupt handler
+ */
+void tegra_gte_irq(void *data);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/i2c-app-priv.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/i2c-app-priv.h
new file mode 100644
index 0000000..4997b55
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/i2c-app-priv.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __I2C_APP_PRIV_H
+#define __I2C_APP_PRIV_H
+
+#include <i2c/i2c.h>
+
+void i2c_test(struct i2c_handle *hi2c);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/init_padctrl.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/init_padctrl.h
new file mode 100644
index 0000000..62f73d8
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/init_padctrl.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2021 NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __INIT_PADCTRL_H
+#define __INIT_PADCTRL_H
+
+void init_padctrl(void);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/ivc-channels.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/ivc-channels.h
new file mode 100644
index 0000000..71aea09
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/ivc-channels.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _IVC_CHANNELS_H_
+#define _IVC_CHANNELS_H_
+
+#include <stdbool.h>
+#include <ospl/rtos-port.h>
+#include <tegra-ivc.h>
+#include <ivc-config.h>
+
+/* Structures used for descirbing the IVC Channel */
+
+struct ivc_task_id;
+extern struct ivc_task_id *ivc_ccplex_task_ids[IVC_NUM_CCPLEX_CHS];
+
+struct ivc_channel_ops {
+	void *(*init)(struct ivc_task_id *id);
+	int (*notify)(void *state, rtosPortBaseType *woken);
+	int (*init_complete)(void *state, rtosPortBaseType *woken);
+	void (*debug_enable)(rtosPortBaseType *woken, bool enable);
+};
+
+struct ivc_task_id {
+	const char *name;
+	struct tegra_ivc_channel *ivc_ch;
+	struct ivc_channel_ops *ops;
+	void *priv;
+};
+
+/*
+ * Initialize the associated handling code for CCPLEX IVC channels.
+ *
+ * Returns:
+ * 0:		OK.
+ * Other:	Error.
+ */
+int ivc_init_channels_ccplex(void);
+
+/*
+ * Notify CCPLEX that SPE has produced data on the IVC channel
+ */
+int hsp_ivc_notify_ccplex(struct tegra_ivc_channel *channel, bool is_read);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/ivc-echo-task.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/ivc-echo-task.h
new file mode 100644
index 0000000..691f1ed
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/ivc-echo-task.h
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2014-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _IVC_TASK_H_
+#define _IVC_TASK_H
+
+#include <ospl/rtos-port.h>
+
+struct ivc_task_id;
+
+/*
+ * Create and start an IVC echo task instance.
+ *
+ * Parameters:
+ * id:		Configuration parameters for this task instance. This pointer
+ *		must be valid for the duration of task execution.
+ *
+ * Returns:
+ * NULL:	Error.
+ * Other:	A task state handle, to be passed to other IVC echo task APIs.
+ */
+void *ivc_echo_task_init(struct ivc_task_id *id);
+
+/*
+ * Inform the IVC echo task that IVC state has changed.
+ *
+ * Parameters:
+ * state:	The result from calling ivc_echo_task_init().
+ *
+ * Returns:
+ * 0:		OK
+ * Other:	Error.
+ */
+int ivc_echo_task_ivc_notified(void *state,
+			       rtosPortBaseType *higher_prio_task_woken);
+
+/*
+ * Inform the IVC echo task that IVC RAM has been inited.
+ *
+ * Parameters:
+ * state:	The result from calling ivc_echo_task_init().
+ *
+ * Returns:
+ * 0:		OK
+ * Other:	Error.
+ */
+int ivc_echo_task_ivc_inited(void *state,
+			     rtosPortBaseType *higher_prio_task_woken);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/late-init.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/late-init.h
new file mode 100644
index 0000000..040ce31
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/late-init.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <error/common-errors.h>
+
+error_t spe_late_init(void);
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/lic-map.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/lic-map.h
new file mode 100644
index 0000000..ce09911
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/lic-map.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef LIC_MAP_H
+#define LIC_MAP_H
+
+/**
+ * @brief routine to fetch the AON/SPE lic map specific to hw platform.
+ */
+error_t get_aon_lic_map(const lic_irq_t **lic_map,
+                        uint32_t *lic_map_size);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/printf-isr.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/printf-isr.h
new file mode 100644
index 0000000..04b0eb0
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/printf-isr.h
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2015, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _PRINTF_ISR_
+#define _PRINTF_ISR_
+
+#include <stdarg.h>
+
+/*
+ * This header defines printf_isr(), which is a printf implementation that
+ * can be called from any context. It doesn't take locks or allocate memory.
+ * Therefore, it is safe to call from interrupt handlers, unlike printf().
+ *
+ * Limitations:
+ * - Output is limited to PRINTF_ISR_BUFSIZE characters. If necessary, this
+ * may be increased, but you may have to increase the IRQ stack size too.
+ * - You may not use the following specificers in the format string:
+ * %a, %A, %S, %ls, or any other that uses multibyte character strings.
+ * - There is no thread safety with respect to other printf() calls. Therefore,
+ * it is possible that output from a printf() and a printf_isr() might be
+ * mixed together.
+ */
+
+#define PRINTF_ISR_BUFSIZE 160
+
+int printf_isr(const char *fmt, ...)
+	__attribute__ ((format (__printf__, 1, 2)));
+
+int vprintf_isr(const char *fmt, va_list ap)
+	__attribute__ ((format (__printf__, 1, 0)));
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-errno.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-errno.h
new file mode 100644
index 0000000..5d52e18
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-errno.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SPE_ERRNO_H
+#define SPE_ERRNO_H
+
+#define SPE_E2BIG         7
+#define SPE_EAGAIN        11
+#define SPE_ENOMEM        12
+#define SPE_EINVAL        22
+#define SPE_ECONNRESET    104
+#define SPE_EOVERFLOW     139
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-errors.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-errors.h
new file mode 100644
index 0000000..405b111
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-errors.h
@@ -0,0 +1,68 @@
+/*
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SPE_ERRORS_H
+#define SPE_ERRORS_H
+
+#include <error/error.h>
+
+#define SPE_ERROR(_x_)                  (MODULE_ERROR(APPLICATION, (_x_)))
+
+#define E_SPE_ERR_NOT_IMPLEMENTED       SPE_ERROR(1U)
+#define E_SPE_ERR_NULL_PTR              SPE_ERROR(2U)
+#define E_SPE_ERR_TIMEOUT               SPE_ERROR(3U)
+#define E_BPMP_IPC_SEND_FROM_ISR_FAIL   SPE_ERROR(4U)
+#define E_BPMP_IPC_SEND_FAIL            SPE_ERROR(5U)
+#define E_BPMP_IPC_INIT_FAIL            SPE_ERROR(6U)
+#define E_TCU_PORT_INVALID              SPE_ERROR(7U)
+#define E_TCU_PREINIT_FAIL              SPE_ERROR(8U)
+#define E_TCU_INIT_FAIL                 SPE_ERROR(9U)
+#define E_TCU_CLIENT_NO_TX_QUEUE        SPE_ERROR(10U)
+#define E_TCU_CLIENT_NO_TX_TASK         SPE_ERROR(11U)
+#define E_TCU_CLIENT_TX_SETUP_FAIL      SPE_ERROR(12U)
+#define E_TCU_CLIENT_NO_RX_QUEUE        SPE_ERROR(13U)
+#define E_TCU_CLIENT_NO_RX_TASK         SPE_ERROR(14U)
+#define E_TCU_CLIENT_RX_SETUP_FAIL      SPE_ERROR(15U)
+#define E_TCU_EXT_CLIENTS_INIT_FAIL     SPE_ERROR(16U)
+#define E_AST_REGION_SIZE_INVALID       SPE_ERROR(17U)
+#define E_CCPLEX_IPC_INIT_FAIL          SPE_ERROR(18U)
+#define E_CCPLEX_IPC_NO_SUPPORT         SPE_ERROR(19U)
+#define E_CCPLEX_IPC_NOT_INITED         SPE_ERROR(20U)
+#define E_IVC_CHAN_INIT_FAIL            SPE_ERROR(21U)
+#define E_IVC_TASK_CREATE_FAIL          SPE_ERROR(22U)
+#define E_IVC_INVALID_CPU_ID            SPE_ERROR(23U)
+#define E_IVC_CHAN_NOTIFY_FAIL          SPE_ERROR(24U)
+#define E_IVC_INVALID_PARAM             SPE_ERROR(25U)
+#define E_INVALID_CLK_FREQ              SPE_ERROR(26U)
+#define E_INVALID_CLK_ID                SPE_ERROR(27U)
+#define E_INVALID_CLK_SRC               SPE_ERROR(28U)
+#define E_INVALID_PARENT_FREQ           SPE_ERROR(29U)
+#define E_TCU_NO_INIT                   SPE_ERROR(30U)
+#define E_TCU_NO_SUSPEND                SPE_ERROR(31U)
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-lic.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-lic.h
new file mode 100644
index 0000000..8752dee
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-lic.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SPE_LIC_H
+#define SPE_LIC_H
+
+#include <stdint.h>
+#include <error/common-errors.h>
+
+/**
+ * @brief routine to intialize AON/SPE lic context.
+ */
+error_t spe_lic_init(void);
+
+/**
+ * @brief routine to enable lic interrupt.
+ */
+void spe_lic_enable(const uint32_t irq);
+
+/**
+ * @brief routine to disable lic interrupt.
+ */
+void spe_lic_disable(const uint32_t irq);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-pm.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-pm.h
new file mode 100644
index 0000000..6a07c91
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-pm.h
@@ -0,0 +1,106 @@
+/* Copyright (c) 2015-2021 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __SPE_PM_H
+#define __SPE_PM_H
+
+#include <ospl/rtos-port.h>
+
+#include <stdbool.h>
+#include <config.h>
+
+enum pm_ram_pg_status {
+	PM_RAM_OFF,
+	PM_RAM_ON,
+	PM_RAM_ERROR
+};
+
+int spe_pm_init(void);
+
+void pm_hw_init(void);
+void pm_suspend_sc7(void);
+void pm_resume_sc7(void);
+void pm_turn_off_caches(void);
+void pm_turn_on_caches(void);
+
+/*
+ * Called after BPMP notifies SPE that the SoC is going to SC7 state
+ */
+void spe_prepare_enter_sc7(void);
+
+/*
+ * Called after BPMP notifies SPE that the SoC is going to SC8 state
+ */
+void spe_prepare_enter_sc8(void);
+
+/*
+ * Called after BPMP notifies SPE that the SoC is in SC0 after SC7/8 states
+ */
+void spe_exit_sc7(void);
+
+enum pm_ram_pg_status get_cache_power_status(void);
+
+/*
+ * Tries to access dram, doesn't block. Does not try to wake dram up on failure.
+ * Returns true on success. This should not be called from an ISR, see
+ * try_request_dram_access_from_isr() for that.
+ */
+bool try_request_dram_access(void);
+
+/*
+ * Tries to access dram, doesn't block. Does not try to wake dram up on failure.
+ * Returns true on success. This is the ISR-safe version.
+ */
+bool try_request_dram_access_from_isr(void);
+
+/*
+ * Requests access to dram. If available, it will return immediately. Else, it
+ * will block until dram becomes available. It will also send a signal to BPMP
+ * to wake the SoC up.
+ */
+void request_dram_access(void);
+
+/*
+ * This function should be called to indicate that a task is done using dram or
+ * other SoC resources. This should be called once for each call to
+ * request_dram_access, or a succesful call to try_request_dram_access.
+ * This should not be called from an ISR. See dram_access_complete_from_isr()
+ * for that.
+ */
+void dram_access_complete(void);
+
+/*
+ * This function should be called to indicate that a task is done using dram or
+ * other SoC resources. This should be called once for each call to
+ * request_dram_access, or a succesful call to try_request_dram_access.
+ * This is the ISR-safe version, however, it can fail if the timer daemon queue
+ * is full.
+ * Returns true on success.
+ */
+bool dram_access_complete_from_isr(rtosPortBaseType *higher_prio_task_woken);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-uart.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-uart.h
new file mode 100644
index 0000000..7627afe
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-uart.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef SPE_UART_H
+#define SPE_UART_H
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* local os headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>
+
+/* local headers */
+
+/*
+ * Declaration for tegra_uart_ctlr that allows the APIs to take a pointer to it
+ * without actually defining its contents here.
+ */
+struct tegra_uart_ctlr;
+
+/*
+ * Declaration for tegra_uart_conf that allows the APIs to take a pointer to it
+ * without actually defining its contents here.
+ */
+struct tegra_uart_conf;
+
+struct spe_uart_ops {
+    error_t (*init)(struct tegra_uart_ctlr * const ctlr,
+                    const struct tegra_uart_conf * const conf);
+    error_t (*init_3rdparty)(struct tegra_uart_ctlr * const ctlr,
+                            const struct tegra_uart_conf * const conf);
+    error_t (*write)(const struct tegra_uart_ctlr * const ctlr,
+                     const char *buf,
+                     uint32_t count,
+                     uint32_t *written,
+                     uint64_t timeout);
+    error_t (*write_now)(const struct tegra_uart_ctlr * const ctlr,
+                         const char *buf,
+                         uint32_t count);
+    error_t (*read)(const struct tegra_uart_ctlr * const ctlr,
+                    char *buf,
+                    uint32_t count,
+                    uint32_t *read,
+                    uint64_t timeout);
+    error_t (*flush)(const struct tegra_uart_ctlr * const ctlr);
+    error_t (*flush_hw)(const struct tegra_uart_ctlr * const ctlr);
+    error_t (*suspend)(struct tegra_uart_ctlr * const ctlr);
+    error_t (*resume)( struct tegra_uart_ctlr * const ctlr);
+};
+
+struct spe_uart {
+    struct tegra_uart_ctlr        *ctlr;
+    const struct tegra_uart_conf  *const conf;
+    const struct spe_uart_ops     *ops;
+};
+
+struct spe_uart *spe_uart_get(const uint32_t port_id);
+
+void spe_uart_write_now(const char *buf, uint32_t count);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-vic.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-vic.h
new file mode 100644
index 0000000..a0dad70
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/spe-vic.h
@@ -0,0 +1,35 @@
+/* Copyright (c) 2014-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SPE_VIC_H
+#define _SPE_VIC_H
+
+void spe_vic_init(void);
+void spe_vic0_irq_handler(unsigned int irq);
+void spe_vic1_irq_handler(unsigned int irq);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/tcu.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/tcu.h
new file mode 100644
index 0000000..42bda6b
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/tcu.h
@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2017-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef TCU_H
+#define TCU_H
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>
+#include <hsp/hsp-tegra.h>
+
+/* local headers */
+#include <osa/osa-task.h>
+#include <osa/osa-errors.h>
+
+typedef bool (*tcu_pre_enable_check)(void);
+
+/**
+ * @brief TCU controller identification structure
+ *
+ * Structure that describes the identification of a TCU client.
+ *
+ * @hsp_id        hsp context for the client
+ * @tx_id         tx hsp context for the client
+ * @enable_check  dynamic check to see if tcu needs to be enabled
+ * @tx_task       task handle for the tx task
+ * @tx_queue      queue for buffering tx data
+ * @rx_queue      queue for buffering rx data
+ * @recv_mbox     shared mailbox on which data is received
+ * @send_mbox     shared mailbox on which data is sent
+ * @id            client CPU id
+ * @tag           client identifier for tcu_muxer
+ * @aon_sm_for_tx indicates if the client uses AON mailbox for tx
+ * @enabled       indicates if the client is enabled
+ * @tx_fifo_full  indicates if the tx fifo is full
+ * @rx_enabled    indicates if the client has rx support
+ * @rx_timed_out  indicates if rx timeout occured
+ */
+typedef struct tcu_client {
+    struct tegra_hsp_id       *hsp_id;
+    struct tegra_hsp_id       *hsp_tx_id;
+    tcu_pre_enable_check      enable_check;
+    rtosTaskHandle            tx_task;
+    rtosQueueHandle           tx_queue;
+    rtosQueueHandle           rx_queue;
+    uint32_t                  recv_mbox;
+    uint32_t                  send_mbox;
+    uint8_t                   id;
+    uint8_t                   tag;
+    bool                      aon_sm_for_tx;
+    bool                      enabled;
+    bool                      tx_fifo_full;
+    bool                      rx_enabled;
+    bool                      rx_timedout;
+} tcu_client_t;
+
+/**
+ * @brief set the global enable state for the Tegra Combined UART server
+ *
+ * This function sets the enable state of TCU.
+ *
+ * @return None
+ */
+void set_tcu_status(bool enable);
+
+/**
+ * @brief get the global enable state for the Tegra Combined UART server
+ *
+ * This function gets the enable state of TCU.
+ *
+ * @return true/false
+ */
+bool is_tcu_enabled(void);
+
+/**
+ * @brief pre-init setup for the Tegra Combined UART server
+ *
+ * This function initializes the pre-init TCU context for the server.
+ *
+ * @retval E_SUCCESS           indicates success
+ * @retval E_TCU_PREINIT_FAIL  pre init failed
+ */
+error_t tcu_preinit(void);
+
+/**
+ * @brief Initialize the Tegra Combined UART server
+ *
+ * This function initializes the TCU context for the server.
+ *
+ * @param[in] uart_id uart port used by the TCU server.
+ *
+ * @retval E_SUCCESS         indicates success
+ * @retval E_TCU_INVALID_ID  invalid uart port passed
+ */
+error_t tcu_init(uint32_t uart_id);
+
+/**
+ * @brief Initialize the Tegra Combined UART tasks
+ *
+ * This function creates and initializes the TCU tasks for clients.
+ *
+ * @retval E_SUCCESS         indicates success
+ * @retval E_TCU_INIT_FAIL   tasks init failed
+ */
+error_t tcu_tasks_init(void);
+
+/**
+ * @brief save the TCU context across SC7 entry/power gating the hardware
+ *
+ * This function preserves the context of TCU  across power gating the
+ * hardware(SC7).
+ *
+ * @pre the function tcu_init() has been called
+ *
+ * @retval E_SUCCESS     indicates success
+ * @retval E_TCU_NO_INIT indicates TCU has not been initialized
+ */
+error_t tcu_suspend(void);
+
+/**
+ * @brief resume the TCU context across SC7 exit/unpower gating the hardware
+ *
+ * This function restores the TCU context across power gating the hardware(SC7).
+ *
+ * @pre the function tcu_init() has been called
+ *
+ * @retval E_SUCCESS     indicates success
+ * @retval E_TCU_NO_INIT indicates TCU has not been initialized
+ */
+error_t tcu_resume(void);
+
+/**
+ * @brief fetch the external TCU clients count
+ *
+ * This function fetches the number of external TCU clients that are supported.
+ *
+ * @retval number of clients supported. 0 if none.
+ */
+uint32_t get_tcu_client_count(void);
+
+/**
+ * @brief fetch TCU clients array supported
+ *
+ * This is used to fetch the TCU client descriptors array supported
+ * by the SPE TCU server.
+ *
+ * @return pointer to the client descriptors else NULL in the case
+ *         of none
+ */
+tcu_client_t* get_tcu_clients_handle(void);
+
+/**
+ * @brief fetch TCU client descriptor from tag to id mapped array
+ *
+ * This is used to fetch the TCU client descriptor from tag to id
+ * mapped array.
+ *
+ * @return pointer to the client descriptor else CCPLEX in the case
+ *         of none
+ */
+tcu_client_t* get_tcu_client_id(char tag);
+
+/**
+ * @brief fetch TCU client tx task parameters
+ *
+ * This is used to fetch the TCU client tx task parameters to be used for
+ * the task creation.
+ *
+ * @return pointer to the task parameters in case of success else NULL.
+ */
+const rtosTaskParameters* get_tcu_client_tx_task_params(uint8_t client_id);
+
+/**
+ * @brief fetch TCU client tx task parameters
+ *
+ * This is used to fetch the TCU client tx task parameters to be used for
+ * the task creation.
+ *
+ * @return pointer to the task parameters in case of success else NULL.
+ */
+const rtosTaskParameters* get_tcu_client_rx_task_params(uint8_t client_id);
+
+/**
+ * @brief fetch TCU client tx queue buffer pointer
+ *
+ * This is used to fetch the TCU client tx queue buffer to be used for
+ * queue creation.
+ *
+ * @return pointer to the queue buffer in memory in case of success else NULL.
+ */
+char* get_tcu_client_tx_queue_buf(uint8_t client_id);
+
+/**
+ * @brief fetch TCU client rx queue buffer pointer
+ *
+ * This is used to fetch the TCU client rx queue buffer to be used for
+ * queue creation.
+ *
+ * @return pointer to the queue buffer in memory in case of success else NULL.
+ */
+char* get_tcu_client_rx_queue_buf(uint8_t client_id);
+
+/**
+ * @brief print a message on the tcu console.
+ *
+ * This function spews a message on to the TCU uart.
+ *
+ * @pre the function tcu_init() has been called
+ *
+ * @param[in] msg_buf  buffer holding the message to be spewed.
+ * @param[in] len      length of the message to be spewed.
+ * @param[in] from_isr flag to indicate spew from isr.
+ *
+ * @retval number of characters sent to the TCU successfully
+ */
+int tcu_print_msg(const char* msg_buf, int len, bool from_isr);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/tegra-ivc.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/tegra-ivc.h
new file mode 100644
index 0000000..500dfac
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/tegra-ivc.h
@@ -0,0 +1,457 @@
+/*
+ * Copyright (c) 2015-2017, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _TEGRA_IVC_H_
+#define _TEGRA_IVC_H_
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/*
+ * Tegra IVC low-level IPC driver.
+ *
+ * Each IPC channel provides bi-directional communication between two entities
+ * (typically CPUs).
+ *
+ * The overall channel is built from two separate uni-directional channels, one
+ * for each direction of communication.
+ *
+ * Each of these uni-directional channels consists of a header and a data
+ * buffer, arranged contiguously in memory. The header is divided into two
+ * parts; one part written by the producer and read by the consumer, and the
+ * other part written by the consumer and read by the producer. The data buffer
+ * is divided into a fixed number of frames. These frames are used as a ring
+ * buffer.
+ *
+ * Each part of the header and each data frame is an exact multiples of the
+ * cache line size. If the cache line size differs on the CPUs, the larger
+ * cache line size must be assumed.
+ *
+ * The two uni-directional channels may be located at arbitrary memory
+ * locations; they need not be contiguous.
+ *
+ * Typically, inter-CPU interrupts are used to signal whenever relevant
+ * information has changed, such as when a producer has produced more data that
+ * the consumer should process, or the consumer has consumed data thus allowing
+ * the producer to produce more.
+ *
+ * This library does not directly deal with these interrupts. Rather:
+ * - Clients of the library are expected to call into the library whenever the
+ *   remote CPU notifies the local CPU of a change.
+ * - Whenever the library wishes to notify the remote CPU of a change, a
+ *   callback is executed to do so. The client of the library must implement
+ *   this callback as appropriate.
+ *
+ * This library performs all necessary cache management internally.
+ *
+ * This library never copies data into or out of the data buffers. Rather, it
+ * provides pointers to those buffers to its client, and expects the client to
+ * copy data as necessary, or perhaps fill/drain the buffers via DMA.
+ */
+
+struct tegra_ivc_channel;
+
+/*
+ * Callback from the tegra_ivc code to the host application indicating that
+ * the remote CPU should be notified of a change to the channel.
+ *
+ * Parameters:
+ * is_read:	True if the channel this CPU reads was updated. False if the
+ * 		channel this CPU writes was updated.
+ */
+typedef int (*tegra_ivc_notify_remote)(struct tegra_ivc_channel *channel,
+	bool is_read);
+
+/*
+ * Structure representing the local SW state associated with a channel.
+ * Clients are expected to fill in the "configuration" fields before calling
+ * any library function. The library manages the "Run-time state" fields
+ * entirely internally; clients should not use or modify these fields.
+ */
+struct tegra_ivc_channel {
+	// Configuration
+	// The channel this CPU writes to
+	void *write_header;
+	// The channel this CPU reads from
+	void *read_header;
+	uint32_t nframes;
+	uint32_t frame_size;
+	tegra_ivc_notify_remote notify_remote;
+	/* Group of channels activated by notify_remote() */
+	uint32_t channel_group;
+
+	// Run-time state
+	uint32_t write_count;
+	uint32_t read_count;
+};
+
+/*
+ * Initialize a channel object's local SW state, and the IPC buffer memory.
+ * This resets all channel headers in the IPC memory.
+ *
+ * Parameters:
+ * ch:		The structure describing the channel
+ *
+ * Returns:
+ * 0:		Success
+ * Non-zero:	Error
+ */
+int tegra_ivc_init_channel_in_ram(struct tegra_ivc_channel *ch);
+
+/*
+ * Initialize a channel object's local SW state, from already initialized or
+ * in-use IPC buffer memory.
+ *
+ * Parameters:
+ * ch:		The structure describing the channel
+ *
+ * Returns:
+ * 0:		Success
+ * Non-zero:	Error
+ */
+int tegra_ivc_init_channel_from_ram(struct tegra_ivc_channel *ch);
+
+/*
+ * Validate channel config.
+ */
+bool tegra_ivc_check_channel(void *write_header,
+			void *read_header,
+			uint32_t nframes,
+			uint32_t frame_size);
+
+/*
+ * Reset a channel object's local SW state using synchronization protocol.
+ *
+ * Parameters:
+ * ch:		The structure describing the channel
+ */
+void tegra_ivc_channel_reset(struct tegra_ivc_channel *ch);
+
+/*
+ * Ensure a channel object is synchronized.
+ *
+ * Parameters:
+ * ch:		The structure describing the channel
+ *
+ * Returns:
+ * false:	Synchronization in progress
+ * true:	Channel is synchronized
+ */
+bool tegra_ivc_channel_notified(struct tegra_ivc_channel *ch);
+
+/*
+ * Check if a channel object is synchronized.
+ *
+ * Parameters:
+ * ch:		The structure describing the channel
+ *
+ * Returns:
+ * false:	Synchronization in progress
+ * true:	Channel is synchronized
+ */
+bool tegra_ivc_channel_is_synchronized(struct tegra_ivc_channel *ch);
+
+/*
+ * Query the number of frames that are available for reception.
+ *
+ * The count value returned by this function may change over time as the remote
+ * CPU adds frames to the channel. However, it cannot normally decrease until
+ * a call to tegra_ivc_rx_notify_buffers_consumed().
+ *
+ * Callers should call this function only when notified of a change by the
+ * remote CPU, and cache the results. This function is relatively heavy-
+ * weight since it invalidates caches.
+ *
+ * Parameters:
+ * ch:		The structure describing the channel.
+ *
+  * Returns:
+ * Zero:	No data available.
+ * Positive:	The number of frames available.
+ */
+unsigned tegra_ivc_rx_get_read_available(struct tegra_ivc_channel *ch);
+
+/*
+ * Get a pointer to an RX frame.
+ *
+ * As IVC is a circular buffer, the available RX frames may not all be
+ * contiguous in RAM. This function can be used to access multiple RX frames
+ * without acknowledging the previous ones.
+ *
+ * If only the first (oldest) available RX frame or only contiguous RX frames
+ * needs to be accessed at once, then
+ * tegra_ivc_rx_get_contiguous_read_available() should be used instead.
+ *
+ * Note this function does not invalidate caches, nor perform any sanity check.
+ * It must only be used in conjunction with tegra_ivc_rx_get_read_available(),
+ * and the requested (zero-based) frame index must be strictly less than the
+ * number of available frames. Otherwise, behaviour is undefined.
+ *
+ * To acknowledge buffers and free space for further RX frames,
+ * tegra_ivc_rx_notify_buffers_consumed() must be called later.
+ *
+ * Parameters:
+ * ch:		The structure describing the channel.
+ * idx:		Frame index (0 is the oldest available RX frame)
+ *
+ * Returns:
+ * A pointer to the beginning of the requested frame.
+ */
+void *tegra_ivc_rx_get_read_frame(struct tegra_ivc_channel *ch, unsigned n);
+
+/*
+ * Query the number of contiguous RX frames that are available for reception.
+ *
+ * The available frames may not all be contiguous in RAM; multiple calls
+ * to tegra_ivc_tx_get_contiguous_read_available() may be required to obtain
+ * all available frames pointers, and process them.
+ *
+ * The count value returned by this function may change over time as the remote
+ * CPU adds frames to the channel.
+ *
+ * Callers should call this function only when notified of a change by the
+ * remote CPU, and cache the results. This function is relatively heavy-
+ * weight since it invalidates caches. The only exception is that when
+ * *non_contig_available == true, this function should be called again to
+ * retrieve a pointer to the wrapped buffers.
+ *
+ * The buffer pointer "returned" by this function will not advance unless
+ * tegra_ivc_rx_notify_buffers_consumed() is called.
+ *
+ * Parameters:
+ * ch:		The structure describing the channel.
+ *
+ * Updates:
+ * *buffer_out:	To point at the first frame containing data to process.
+ * *non_contig_available:
+ * 		true if more frames are available at this time, but are not in
+ * 		contiguous memory (i.e. the buffer wrapped).
+ * 		false if the returned frame count is not limited by buffer
+ * 		wrapping.
+ *
+ * Returns:
+ * Zero:	No data available.
+ * Positive:	The number of frames available.
+ */
+int tegra_ivc_rx_get_contiguous_read_available(struct tegra_ivc_channel *ch,
+	const char **buffer_out, bool *non_contig_available);
+
+/*
+ * Query the RX frames that are available for reception.
+ *
+ * The count value returned by this function may change over time as the remote
+ * CPU adds frames to the channel.
+ *
+ * Callers should call this function only when notified of a change by the
+ * remote CPU, and cache the results. This function is relatively heavy-
+ * weight since it invalidates caches. The only exception is that when
+ * *non_contig_available == true, this function should be called again to
+ * retrieve a pointer to the wrapped buffers.
+ *
+ * The buffer pointer "returned" by this function will not advance unless
+ * tegra_ivc_rx_notify_buffers_consumed() is called.
+ *
+ * Parameters:
+ * ch:		The structure describing the channel.
+ * count:	The number of frames to return.
+ *
+ * Updates:
+ * buffer_out[count]:	To point at the first frame containing data to process.
+ *
+ * Returns:
+ * Zero:	No data available.
+ * Positive:	The number of frames available (may be larger than count).
+ */
+int tegra_ivc_rx_get_frames(struct tegra_ivc_channel *ch,
+		const char *buffers_out[], unsigned count);
+
+/*
+ * Notify the remote producer that frames have been consumed.
+ *
+ * Only contiguous frames can be marked consumed; each call to
+ * tegra_ivc_rx_get_contiguous_read_available() should be paired with a number
+ * of calls to tegra_ivc_rx_notify_buffers_consumed(), with the "count"
+ * parameters adding up to tegra_ivc_rx_get_contiguous_read_available()'s
+ * return value.
+ *
+ * Callers should generally batch up calls to this function when processing
+ * multiple received frames, rather than repeatedly calling this function for
+ * each frame. This function cleans caches; batching calls reduces the
+ * overhead of the cache operations. Even so, throughput, latency, and
+ * pipelining requirements might require calling this function more often than
+ * once per call to tegra_ivc_rx_get_contiguous_read_available().
+ *
+ * Parameters:
+ * ch:		The structure describing the channel.
+ * count:	The number of frames consumed.
+ *
+ * Returns:
+ * 0:		Success
+ * Non-zero:	Error
+ */
+int tegra_ivc_rx_notify_buffers_consumed(struct tegra_ivc_channel *ch,
+	int count);
+
+/*
+ * Query the number of frame buffers that are available for sending.
+ *
+ * The count value returned by this function may change over time as the remote
+ * CPU frees used frame buffers. However, it cannot normally decrease until
+ * a call to tegra_ivc_tx_send_buffers().
+ *
+ * Callers should call this function only when notified of a change by the
+ * remote CPU, and cache the results. This function is relatively heavy-
+ * weight since it invalidates caches.
+ *
+ * Parameters:
+ * ch:		The structure describing the channel.
+ *
+  * Returns:
+ * Zero:	No space available.
+ * Positive:	The number of free frame buffers.
+ */
+unsigned tegra_ivc_tx_get_write_space(struct tegra_ivc_channel *ch);
+
+/*
+ * Get a pointer to an TX frame.
+ *
+ * As IVC is a circular buffer, the free TX frame buffes may not all be
+ * contiguous in RAM. This function can be used to access multiple TX frame
+ * buffers without committing the previous ones for sending.
+ *
+ * If only the first (oldest) available TX frame buffer or only contiguous TX
+ * frame buffers need to be accessed at once, then
+ * tegra_ivc_tx_get_contiguous_write_space() should be used instead.
+ *
+ * Note this function does not invalidate caches, nor perform any sanity check.
+ * It must only be used in conjunction with tegra_ivc_tx_get_write_space(),
+ * and the requested (zero-based) frame index must be strictly less than the
+ * number of available frames. Otherwise, behaviour is undefined.
+ *
+ * Parameters:
+ * ch:		The structure describing the channel.
+ * idx:		Frame index (0 is the oldest available RX frame)
+ *
+ * Returns:
+ * A pointer to the beginning of the requested frame.
+ */
+void *tegra_ivc_tx_get_write_buffer(struct tegra_ivc_channel *ch, unsigned n);
+
+/*
+ * Query the number of contiguous TX frames that are available for filling.
+ *
+ * The available frames may not all be contiguous in RAM; multiple calls
+ * to tegra_ivc_tx_get_contiguous_write_space() may be required to obtain
+ * all available frame pointers, and fill them.
+ *
+ * The count value returned by this function may change over time as the remote
+ * CPU consumes frames from the channel.
+ *
+ * Callers should call this function only when notified of a change by the
+ * remote CPU, and cache the results. This function is relatively heavy-
+ * weight since it invalidates caches.The only exception is that when
+ * *non_contig_available == true, this function could be called again to
+ * retrieve a pointer to the wrapped buffers.
+ *
+ * The buffer pointer "returned" by this function will not advance unless
+ * tegra_ivc_tx_send_buffers() is called.
+ *
+ * Parameters:
+ * ch:		The structure describing the channel.
+ *
+ * Updates:
+ * *buffer_out:	To point at the first frame into which data should be placed.
+ * *non_contig_available:
+ * 		true if more frames are available at this time, but are not in
+ * 		contiguous memory (i.e. the buffer wrapped).
+ * 		false if the returned frame count is not limited by buffer
+ * 		wrapping.
+ *
+ * Returns:
+ * Zero:	No data available.
+ * Positive:	The number of empty frames that may be filled.
+ */
+int tegra_ivc_tx_get_contiguous_write_space(struct tegra_ivc_channel *ch,
+	char **buffer_out, bool *non_contig_available);
+
+/*
+ * Query the number of TX frames that are available for filling.
+ *
+ * The available frames may not all be contiguous in RAM.
+ *
+ * The count value returned by this function may change over time as the remote
+ * CPU consumes frames from the channel.
+ *
+ * Callers should call this function only when notified of a change by the
+ * remote CPU, and cache the results. This function is relatively heavy-
+ * weight since it invalidates caches.
+ *
+ * The buffer pointers "returned" by this function will not advance unless
+ * tegra_ivc_tx_send_buffers() is called.
+ *
+ * Parameters:
+ * ch:		The structure describing the channel.
+ * count:	The number of frames to return.
+ *
+ * Updates:
+ * buffers_out[count]:	The frames into which data could be placed.
+ *
+ * Returns:
+ * Zero:	No data available.
+ * Positive:	The number of empty frames that may be filled.
+ */
+int tegra_ivc_tx_get_frames(struct tegra_ivc_channel *ch,
+		char **buffers_out, unsigned count);
+
+/*
+ * Notify the remote consumer that frames have been produced.
+ *
+ * Only contiguous frames can be marked produced; each call to
+ * tegra_ivc_tx_get_contiguous_write_space() should be paired with a number
+ * of calls to tegra_ivc_tx_send_buffers(), with the "count"
+ * parameters adding up to tegra_ivc_tx_get_contiguous_write_space()'s
+ * return value.
+ *
+ * Callers should generally batch up calls to this function when producing
+ * multiple frames, rather than repeatedly calling this function for
+ * each frame. This function cleans caches; batching calls reduces the
+ * overhead of the cache operations. Even so, throughput, latency, and
+ * pipelining requirements might require calling this function more often than
+ * once per call to tegra_ivc_tx_get_contiguous_write_space().
+ *
+ * Parameters:
+ * ch:		The structure describing the channel.
+ * count:	The number of frames consumed.
+ *
+ * Returns:
+ * 0:		Success
+ * Non-zero:	Error
+ */
+int tegra_ivc_tx_send_buffers(struct tegra_ivc_channel *ch, int count);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/tegra-lic.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/tegra-lic.h
new file mode 100644
index 0000000..151e7f2
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/tegra-lic.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2022 NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __TEGRA_LIC_H
+#define __TEGRA_LIC_H
+
+void lic_init(void);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/uart-errors.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/uart-errors.h
new file mode 100644
index 0000000..cddf2d6
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/uart-errors.h
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef UART_ERRORS_H
+#define UART_ERRORS_H
+
+/* Compiler headers */
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <base/module-id.h>     // IWYU pragma: export
+                                // IWYU pragma: no_include "base/module-id.h"
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__BASE__MODULE_ID_H, "Header file missing or invalid.")
+
+/**
+ * @file uart-errors.h
+ * @brief Error codes that are specific to the UART
+ */
+
+#define E_UART_NULL_PTR                 MODULE_ERROR(UART, 0UL)
+#define E_UART_INVALID_PARAM            MODULE_ERROR(UART, 1UL)
+#define E_UART_ERR_CONFIG               MODULE_ERROR(UART, 2UL)
+#define E_UART_INIT_FAIL                MODULE_ERROR(UART, 3UL)
+#define E_UART_NO_INIT                  MODULE_ERROR(UART, 4UL)
+#define E_UART_FLUSH_TX_FIFO_FAIL       MODULE_ERROR(UART, 5UL)
+
+#endif  /* UART__UART_ERRORS_H */
\ No newline at end of file
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/uart-hw.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/uart-hw.h
new file mode 100644
index 0000000..d15dd0c
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/uart-hw.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef UART_HW_H
+#define UART_HW_H
+
+extern struct tegra_uart_ctlr tegra_uart_ctlr_uartc;
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/uart-macros.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/uart-macros.h
new file mode 100644
index 0000000..2b4e67e
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/uart-macros.h
@@ -0,0 +1,172 @@
+/*
+ * Copyright (c) 2018-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef UART_MACROS_H
+#define UART_MACROS_H
+
+/* Compiler headers */
+#include <stdint.h>                 // for uint32_t, int32_t, uint8_t
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>         // for CT_ASSERT
+#include <soc-common/hw-const.h>    /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <address_map_new.h>        // for NV_ADDRESS_MAP_CAR_BASE
+#include <arclk_rst.h>              // for CLK_RST_CONTROLLER_....
+
+/* Late FSP headers */
+#include <reg-access/reg-access.h>
+#include <delay/delay.h>
+#include <misc/nvrm_drf.h>
+
+/**
+ * Read UARTx CAR register value.
+ */
+#define SPE_UART_CAR_READ(uart, reg)					\
+		(readl(NV_ADDRESS_MAP_CAR_BASE +			\
+		       CLK_RST_CONTROLLER_##reg##_##uart##_0))	\
+
+/**
+ * Write UARTx CAR register value.
+ */
+#define SPE_UART_CAR_WRITE(uart, reg, value)				\
+	do {								\
+		writel((value), NV_ADDRESS_MAP_CAR_BASE +			\
+		          CLK_RST_CONTROLLER_##reg##_##uart##_0);					\
+	} while (0 == 1)
+
+/**
+ * Read UARTx CAR register field value.
+ */
+#define SPE_UART_CAR_READ_FIELD(uart, reg, field) \
+		(NV_DRF_VAL(CLK_RST_CONTROLLER, reg##_##uart, \
+			   field, SPE_UART_CAR_READ(uart, reg)))
+
+/**
+ * Evaluate to true if UARTx CAR register field value matches.
+ */
+#define SPE_UART_CAR_IS_FIELD_DEF(uart, reg, field, def)		       \
+		(SPE_UART_CAR_READ_FIELD(uart, reg, field) ==		       \
+			CLK_RST_CONTROLLER_##reg##_##uart##_0_##field##_##def)
+
+/**
+ * Evaluate to true if UARTx clock is enabled.
+ */
+#define SPE_UART_IS_CLK_ENABLED(uart)				    \
+		(SPE_UART_CAR_IS_FIELD_DEF(uart, CLK_OUT_ENB,      \
+					    CLK_ENB_##uart, ENABLE))
+
+/**
+ * Evaluate to true if UARTx reset is deasserted.
+ */
+#define SPE_UART_IS_RESET_DEASSERTED(uart)				\
+		(SPE_UART_CAR_IS_FIELD_DEF(uart, RST_DEV,		\
+					    SWR_##uart##_RST, DISABLE))
+
+/**
+ * Enable UARTx clock in CAR
+ */
+#define SPE_UART_ENABLE_CLK(uart)					    \
+	do {								    \
+		const uint32_t value = NV_DRF_DEF(CLK_RST_CONTROLLER,	    \
+						  CLK_OUT_ENB_##uart##_SET, \
+						  SET_CLK_ENB_##uart,	    \
+						  ENABLE);		    \
+		writel(value, NV_ADDRESS_MAP_CAR_BASE +			    \
+			CLK_RST_CONTROLLER_CLK_OUT_ENB_##uart##_SET_0);						    \
+	} while (0 == 1)
+
+/**
+ * Assert UARTx reset
+ */
+#define SPE_UART_ASSERT_RESET(uart)					    \
+	do {								    \
+		const uint32_t value = NV_DRF_DEF(CLK_RST_CONTROLLER,	    \
+						  RST_DEV_##uart##_SET,	    \
+						  SET_SWR_##uart##_RST,	    \
+						  ENABLE);		    \
+		writel(value, NV_ADDRESS_MAP_CAR_BASE +			    \
+		          CLK_RST_CONTROLLER_RST_DEV_##uart##_SET_0);					    \
+	} while (0 == 1)
+
+/**
+ * Deassert UARTx reset
+ */
+#define SPE_UART_DEASSERT_RESET(uart)					    \
+	do {								    \
+		const uint32_t value = NV_DRF_DEF(CLK_RST_CONTROLLER,	    \
+						  RST_DEV_##uart##_CLR,	    \
+						  CLR_SWR_##uart##_RST,	    \
+						  ENABLE);		    \
+		writel(value, NV_ADDRESS_MAP_CAR_BASE +			    \
+		          CLK_RST_CONTROLLER_RST_DEV_##uart##_CLR_0);					    \
+	} while (0 == 1)
+
+/**
+ * Reset UARTx
+ */
+#define SPE_UART_RESET(uart)			\
+	do {					\
+		SPE_UART_ASSERT_RESET(uart);	\
+		udelay(5U);		\
+		SPE_UART_DEASSERT_RESET(uart);	\
+	} while (0 == 1)
+
+/**
+ * Reset UARTx and configure and enable clock for UARTx in one go.
+ */
+#define SPE_UART_ENABLE(uart, src, div_enb, div)		  \
+	do {							  \
+		uint32_t val = 0U;				  \
+								  \
+		SPE_UART_RESET(uart);				  \
+								  \
+		val = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER,	  \
+					   CLK_SOURCE_##uart,	  \
+					   uart##_CLK_SRC,	  \
+					   src,			  \
+					   val);		  \
+		val = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER,	  \
+					   CLK_SOURCE_##uart,	  \
+					   uart##_DIV_ENB,	  \
+					   div_enb,		  \
+					   val);		  \
+		val = NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER,	  \
+					   CLK_SOURCE_##uart,	  \
+					   uart##_CLK_DIVISOR,	  \
+					   (div),		  \
+					   val);		  \
+		SPE_UART_CAR_WRITE(uart, CLK_SOURCE, val);	  \
+								  \
+		SPE_UART_ENABLE_CLK(uart);			  \
+	} while (0 == 1)
+
+/* vim: set ts=8 noexpandtab: */
+
+#endif /* UART_MACROS_H */
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/uart-tegra-priv.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/uart-tegra-priv.h
new file mode 100644
index 0000000..0d31da9
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/uart-tegra-priv.h
@@ -0,0 +1,96 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef UART_TEGRA_PRIV_H
+#define UART_TEGRA_PRIV_H
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>
+#include <clk/clk-tegra.h>
+#include <osa/rtos-queue.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__CLK__CLK_TEGRA_H, "Header file missing or invalid.")
+
+/**
+ * @brief UART controller identification structure
+ *
+ * Structure that describes the identification of a UART controller.
+ *
+ * @base_addr   base address of the controller
+ * @clk         controller clock config data
+ * @reset       controller reset config data
+ * @irq         controller irq
+ */
+struct tegra_uart_id {
+    uint32_t                    base_addr;
+    const struct tegra_clk      *clk;
+    const struct tegra_rst      *reset;
+    uint32_t                    irq;
+};
+
+/**
+ * @brief UART controller context structure
+ *
+ * Structure that is used by the UART driver to manage the UART controller
+ * during run time.
+ *
+ * @conf         UART controller instance parameters
+ * @tx_queue     UART SW TX FIFO
+ * @rx_queue     UART SW RX FIFO
+ * @tx_sem       tx semaphore for mutual exlusion
+ * @initialized  UART controller initialization status
+ */
+struct tegra_uart_ctlr {
+    const struct tegra_uart_id    id;
+	rtosQueueHandle                  tx_queue;
+	rtosQueueHandle                  rx_queue;
+    bool                          initialized;
+};
+
+#endif
\ No newline at end of file
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/uart-tegra.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/uart-tegra.h
new file mode 100644
index 0000000..0ec26ae
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/uart-tegra.h
@@ -0,0 +1,283 @@
+/*
+ * Copyright (c) 2019-2022 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef UART_TEGRA_H
+#define UART_TEGRA_H
+
+/* Compiler headers */
+#include <stdint.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <error/common-errors.h>
+
+/* Module-specific FSP headers */
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+
+/*
+ * Declaration for tegra_uart_ctlr that allows the APIs to take a pointer to it
+ * without actually defining its contents here.
+ */
+struct tegra_uart_ctlr;
+
+/*
+ * Declaration for tegra_uart_conf that allows the APIs to take a pointer to it
+ * without actually defining its contents here.
+ */
+struct tegra_uart_conf;
+
+/**
+ * @brief Initialize the UART instance and configure it
+ *
+ * This function initializes and configures the UART context for an instance.
+ *
+ * @param[in] ctrl      UART instance.
+ * @param[in] conf      UART configuration parameters.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      NULL paramters passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ * @retval E_UART_ERR_CONFIG    invalid configuration
+ */
+error_t  tegra_uart_init(struct tegra_uart_ctlr *ctlr,
+                         const struct tegra_uart_conf * const conf);
+
+/**
+ * @brief Initialize the already initialized UART instance
+ *
+ * This function initializes and configures the UART context for an instance
+ * that has already been initialized by a 3rdparty or another CPU.
+ *
+ * @param[in] ctrl      UART instance.
+ * @param[in] conf      UART configuration parameters.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      NULL paramters passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ */
+error_t  tegra_uart_3rdparty_init(struct tegra_uart_ctlr *ctlr,
+                                  const struct tegra_uart_conf * const conf);
+
+/**
+ * @brief Flush the UART SW TX buffer.
+ *
+ * This function flushes the software TX buffer of the UART.
+ *
+ * @pre the function tegra_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ * @param[in] timeout   timeout to flush the buffer.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ * @retval E_UART_FLUSH_TIMEOUT flush timed out
+ */
+error_t tegra_uart_flush_tx_fifo(const struct tegra_uart_ctlr * const ctlr);
+
+/**
+ * @brief Flush the UART HW TX FIFO.
+ *
+ * This function flushes the software HW TX FIFO of the UART.
+ *
+ * @pre the function tegra_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ * @retval E_UART_FLUSH_TIMEOUT flush timed out
+ */
+error_t tegra_uart_flush_tx_hw_fifo(const struct tegra_uart_ctlr * const ctlr);
+
+/**
+ * @brief Write a character to the UART HW TX FIFO.
+ *
+ * This function writes a character to the UART HW TX FIFO.
+ *
+ * @pre the function tegra_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ * @param[in] c         character to be written.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ */
+error_t tegra_uart_write_char(const struct tegra_uart_ctlr * const ctlr,
+                              const char c);
+
+/**
+ * @brief Read a character from the UART HW RX FIFO.
+ *
+ * This function reads a character from the UART HW RX FIFO.
+ *
+ * @pre the function tegra_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ * @param[in] c         pointer to where character read is to be written.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ */
+error_t tegra_uart_read_char(const struct tegra_uart_ctlr * const ctlr,
+                             char *c);
+
+/**
+ * @brief Write to the UART HW TX fifo.
+ *
+ * This function writes data to the UART HW TX FIFO.
+ *
+ * @pre the function tegra_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ * @param[in] buf       pointer to the data to be written.
+ * @param[in] count     byte count of the data to be written.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ */
+error_t tegra_uart_write_now(const struct tegra_uart_ctlr * const ctlr,
+                             const char *buf,
+                             uint32_t count);
+
+/**
+ * @brief Write a string to the UART TX buffer.
+ *
+ * This function writes a string to the SW TX buffer which in turn gets
+ * pushed to the HW TX FIFO.
+ *
+ * @pre the function tegra_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ * @param[in] buf       pointer to the string.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ */
+error_t tegra_uart_write_string(const struct tegra_uart_ctlr * const ctlr,
+                                const char *buf);
+
+/**
+ * @brief Write to the UART TX buffer.
+ *
+ * This function writes the data to the SW TX buffer which in turn gets
+ * pushed to the HW TX FIFO.
+ *
+ * @pre the function tegra_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ * @param[in] buf       pointer to the data to be written.
+ * @param[in] count     byte count of the data to be written.
+ * @param[in] written   byte count written.
+ * @param[in] timeout   timeout to return.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ * @retval E_UART_WRITE_TIMEOUT flush timed out
+ */
+error_t tegra_uart_write(const struct tegra_uart_ctlr * const ctlr,
+                         const char *buf,
+                         uint32_t count,
+                         uint32_t *written,
+                         uint64_t timeout);
+
+/**
+ * @brief Read from the UART RX buffer.
+ *
+ * This function reads data from the UART RX buffer.
+ *
+ * @pre the function tegra_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ * @param[in] buf       pointer to store the data being read.
+ * @param[in] count     byte count of the data to be read.
+ * @param[in] read      byte count read.
+ * @param[in] timeout   timeout to return.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ * @retval E_UART_INVALID_PARAM invalid parameter passed
+ * @retval E_UART_WRITE_TIMEOUT flush timed out
+ */
+error_t tegra_uart_read(const struct tegra_uart_ctlr * const ctlr,
+                        char *buf,
+                        uint32_t count,
+                        uint32_t *read,
+                        uint64_t timeout);
+
+/**
+ * @brief suspend the UART context.
+ *
+ * This function saves the UART context across power gating the HW.
+ *
+ * @pre the function tegra_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ */
+error_t tegra_uart_suspend(struct tegra_uart_ctlr * const ctlr);
+
+/**
+ * @brief resume the UART context.
+ *
+ * This function restores the UART context across power gating the HW.
+ *
+ * @pre the function tegra_uart_init() has been called
+ *
+ * @param[in] ctlr      UART controller instance.
+ *
+ * @retval E_SUCCESS            indicates success
+ * @retval E_UART_NULL_PTR      invalid id paramter passed
+ */
+error_t tegra_uart_resume(struct tegra_uart_ctlr * const ctlr);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/wake-tegra-hw.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/wake-tegra-hw.h
new file mode 100644
index 0000000..30b81a5
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/wake-tegra-hw.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2016-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef WAKE_TEGRA_HW_H
+#define WAKE_TEGRA_HW_H
+
+#include <address_map_new.h>
+
+/*
+ * wake event defined in
+ * //hw/nvmobile/ip/socip/pmc/5.0/defs/public/registers/
+ */
+#define TEGRA_WAKE_EVENT_RTC		73
+#define TEGRA_WAKE_EVENT_SW_TRIGGER	83
+
+enum tegra_wake_tier {
+	TEGRA_WAKE_TIER0,
+	TEGRA_WAKE_TIER1,
+	TEGRA_WAKE_TIER2,
+};
+
+/*
+ * We cheat and use the HW register address instead of the address of a config
+ * structure as the WAKE ID for now. We still need a dummy definition of the
+ * struct to do that though; this is it.
+ */
+struct tegra_wake_id {
+	uint32_t dummy;
+};
+
+/*
+ * We intend: &tegra_wake_id == NV_ADDRESS_MAP_WAKE_BASE. This avoids
+ * having to allocate a struct to hold the value NV_ADDRESS_MAP_WAKE_BASE.
+ * If we ever need to store more configuration than just the register address,
+ * this can be converted to a struct at that time.
+ */
+#define tegra_wake_id_wake (*(struct tegra_wake_id *)NV_ADDRESS_MAP_WAKE_BASE)
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/wake-tegra.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/wake-tegra.h
new file mode 100644
index 0000000..d1d2b9a
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/include/wake-tegra.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2015-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef WAKE_TEGRA_H
+#define WAKE_TEGRA_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+struct tegra_wake_id;
+
+/*
+ * To use this driver:
+ *
+ * 1. Call tegra_wake_route_event to route wake event into desired tier level
+ * 2. Call tegra_wake_enable_irq to enable the irq of the selected wake event
+ * 2. Call tegra_wake_enable to enable wake event detection
+ */
+
+/*
+ * Route wake event into selected tier
+ *
+ * Parameters:
+ * id:		    The ID structure for the WAKE module
+ * wake_event:	The wake event to be routed
+ * tier:	    The wake event will be routed into this tier
+ * sel:		    0: Remove wake event from desired tier level
+ *		        1: Select wake event into desired tier level
+ */
+void tegra_wake_route_event(struct tegra_wake_id *id, uint32_t wake_event,
+				  uint32_t tier, bool sel);
+
+/*
+ * Enable selected wake event
+ *
+ * Parameters:
+ * id:		    The ID structure for the WAKE module
+ * wake_event:	The wake event is going to be enabled
+ */
+void tegra_wake_enable_event(struct tegra_wake_id *id, uint32_t wake_event);
+
+/*
+ * Disable selected wake event
+ *
+ * Parameters:
+ * id:		    The ID structure for the WAKE module
+ * wake_event:	The wake event is going to be disabled
+ */
+void tegra_wake_disable_event(struct tegra_wake_id *id, uint32_t wake_event);
+
+/*
+ * Enable wake event detection
+ *
+ * Parameters:
+ * id:		The ID structure for the WAKE module
+ */
+void tegra_wake_enable(struct tegra_wake_id *id);
+
+/*
+ * Disable wake event detection
+ *
+ * Parameters:
+ * id:		The ID structure for the WAKE module
+ */
+void tegra_wake_disable(struct tegra_wake_id *id);
+
+/*
+ * Clear wake interrupt status
+ *
+ * Parameters:
+ * id:		    The ID structure for the WAKE module.
+ * wake_event:	The wake event status to be clear
+ */
+void tegra_wake_clear_irq(struct tegra_wake_id *id, uint32_t wake_event);
+
+/*
+ * Trigger a wake event
+ *
+ * Parameters:
+ * id:		The ID structure for the WAKE module.
+ */
+void tegra_wake_trigger_wake_event(struct tegra_wake_id *id);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/main.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/main.c
new file mode 100644
index 0000000..102b4f1
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/main.c
@@ -0,0 +1,223 @@
+/*
+ * Copyright (c) 2014-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <address_map_new.h>
+#include <cpu/arm-vic.h>
+#include <arclk_rst.h>
+#include <araopm.h>
+#include <clk/clk-tegra.h>
+#include <cpu/cache.h>
+#include <delay/delay.h>
+#include <err-hook.h>
+#include <irq/safe-irqs.h>
+#include <processor/irqs-hw.h>
+#include <misc/bitops.h>
+#include <misc/nvrm_drf.h>
+
+#include <reg-access/reg-access.h>
+#include <spe-pm.h>
+#include <spe-vic.h>
+#include <stdio.h>
+#include <tke/tke-tegra.h>
+#include <processor/tke-tegra-hw.h>
+
+#include <bpmp-ipc.h>
+#include <hsp/hsp-tegra.h>
+#include <processor/hsp-tegra-hw.h>
+#include <ivc-channels.h>
+
+#include <osa/rtos-task.h>
+#include <osa/rtos-semaphore.h>
+#include <osa/rtos-timer.h>
+#include <late-init.h>
+#include <tcu.h>
+
+#if defined(ENABLE_GPCDMA_FUNC)
+#include <gpcdma/gpcdma.h>
+#include <gpcdma/gpcdma-errors.h>
+#include <processor/gpcdma-hw.h>
+#endif
+
+#if defined(ENABLE_AODMIC_APP)
+#include "app/aodmic-app.h"
+#endif
+
+#if defined(ENABLE_GPIO_APP)
+#include <gpio/tegra-gpio.h>
+extern struct tegra_gpio_id *chips[];
+#include <gpio-aon.h>
+#include "app/gpio-app.h"
+#endif
+
+#if defined(ENABLE_TIMER_APP)
+#include "app/timer-app.h"
+#endif
+
+#if defined(ENABLE_I2C_APP)
+#include "app/i2c-app.h"
+#endif
+
+#if defined(ENABLE_GTE_APP)
+#include <gte-app.h>
+#endif
+
+#include "config.h"
+#include "init_padctrl.h"
+#include "debug_init.h"
+#include "main.h"
+#include "tegra-lic.h"
+#include "app/spi-app.h"
+
+#if defined(ENABLE_SPI_SLV_APP)
+#include "app/spi-slv-app.h"
+#endif
+
+#define TEGRA_GPIO_AON_CHIPS_INDEX 1u
+#define TEGRA_GPIO_AON_NUM_CHIPS   1u
+
+int main(void)
+{
+	spe_vic_init();
+
+	lic_init();
+
+	init_padctrl();
+
+	tegra_tsc_init();
+
+	debug_early_init();
+
+	tegra_hsp_init(&tegra_hsp_id_aon);
+
+	if (bpmp_ipc_init())
+		printf("bpmp_ipc_init() failed\r\n");
+
+	if (spe_late_init()) {
+		error_hook("late init failed\r\n");
+		goto out;
+	}
+
+	/* Start the tasks and timer running. */
+	rtosTaskInitializeScheduler(NULL);
+
+out:
+	for( ;; )
+		;
+
+	return 0;
+}
+
+void main_task(void *params)
+{
+	tegra_clk_init();
+	debug_init(SCRATCH_SCRATCH_COMB);
+	if (ivc_init_channels_ccplex())
+		printf("ivc_init_channels_ccplex() failed\r\n");
+
+#if defined(ENABLE_GPCDMA_FUNC)
+	gpcdma_init(&gpcdma_id_aon);
+#endif
+
+#if defined(ENABLE_AODMIC_APP)
+	aodmic_app_init();
+#endif
+
+#if defined(ENABLE_GPIO_APP)
+	if (tegra_gpio_init(&chips[TEGRA_GPIO_AON_CHIPS_INDEX],
+				TEGRA_GPIO_AON_NUM_CHIPS))
+		error_hook("tegra_gpio_init() failed\r\n");
+	gpio_app_init();
+#endif
+
+#if defined(ENABLE_TIMER_APP)
+	timer_app_init();
+#endif
+
+#if defined(ENABLE_I2C_APP)
+	i2c_app_init();
+#endif
+
+#if defined(ENABLE_GTE_APP)
+	gte_app_init();
+#endif
+
+#if defined(ENABLE_SPI_APP)
+	spi_app_init();
+#endif
+
+#if defined(ENABLE_SPI_SLV_APP)
+	spi_slv_app_init();
+#endif
+
+	rtosTaskDelete(NULL);
+}
+
+/* Referenced from FreeRTOSConfig.h */
+void setup_timer_interrupt(void)
+{
+	tegra_tke_set_up_tick(&tegra_tke_id_timer0,
+				TIMER_CLK_SRC,
+				configCPU_CLOCK_HZ / configTICK_RATE_HZ);
+}
+
+/* Referenced from freertos */
+void vApplicationStackOverflowHook(TaskHandle_t pxTask, char *pcTaskName)
+{
+	(void)pcTaskName;
+	(void)pxTask;
+
+	printf("Stack Overflow");
+	rtosTaskDisableInterrupts();
+	for( ;; )
+		;
+}
+
+void vApplicationGetIdleTaskMemory(rtosTaskBuffer **ppxIdleTaskTCBBuffer,
+				   rtosStackType **ppxIdleTaskStackBuffer,
+				   portUInt32Type *pulIdleTaskStackSize)
+{
+	static rtosTaskBuffer xIdleTaskTCB;
+	static rtosStackType uxIdleTaskStack[configMINIMAL_STACK_SIZE];
+
+	*ppxIdleTaskTCBBuffer = &xIdleTaskTCB;
+	*ppxIdleTaskStackBuffer = uxIdleTaskStack;
+	*pulIdleTaskStackSize = configMINIMAL_STACK_SIZE;
+}
+
+void vApplicationGetTimerTaskMemory(rtosTaskBuffer **ppxTimerTaskTCBBuffer,
+				    rtosStackType **ppxTimerTaskStackBuffer,
+				    portUInt32Type *pulTimerTaskStackSize)
+{
+	static rtosTaskBuffer xTimerTaskTCB;
+	static rtosStackType uxTimerTaskStack[configTIMER_TASK_STACK_DEPTH];
+
+	*ppxTimerTaskTCBBuffer = &xTimerTaskTCB;
+	*ppxTimerTaskStackBuffer = uxTimerTaskStack;
+	*pulTimerTaskStackSize = configTIMER_TASK_STACK_DEPTH;
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/main.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/main.h
new file mode 100644
index 0000000..fdf5d90
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/main.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __MAIN_H
+#define __MAIN_H
+
+void main_task(void *params);
+
+#endif
+
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/debug_init.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/debug_init.c
new file mode 100644
index 0000000..682ec2c
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/debug_init.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <reg-access/reg-access.h>
+#include <debug/debug.h>
+#include <err-hook.h>
+#include <tcu.h>
+#include "debug_init.h"
+#include "config.h"
+
+void debug_early_init(void)
+{
+	tcu_preinit();
+}
+
+void debug_init(uint32_t reg)
+{
+	uint32_t scratch_reg = readl(reg);
+	int ret = 0;
+	uint32_t uart_port = 0;
+	if ((scratch_reg & SCRATCH_MAGIC_MASK_COMB) == SCRATCH_MAGIC_VAL_COMB) {
+		uart_port = scratch_reg & SCRATCH_UART_MASK_COMB;
+		switch (uart_port) {
+		case 2:
+			set_tcu_status(true);
+			tcu_tasks_init();
+			ret = tcu_init(uart_port);
+			printf("init uartc for combined uart\r\n");
+			break;
+		default:
+			printf("unknown scratch value (%d) for combined uart\r\n", (int)scratch_reg & SCRATCH_UART_MASK_COMB);
+			break;
+		}
+		if (ret)
+			error_hook("tcu_init() failed");
+	}
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/err-hook-printf.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/err-hook-printf.c
new file mode 100644
index 0000000..5c38d2e
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/err-hook-printf.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2015-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <stdarg.h>
+
+#include <err-hook.h>
+#include <irq/safe-irqs.h>
+#include <printf-isr.h>
+
+#include <osa/osa-task.h>
+
+static void err_msg(const char *err_type, const char *file, int line,
+		const char *function, const char *msg)
+{
+	if (in_critical()) {
+		printf_isr("%s %s:%d [%s] \"", err_type, file, line, function);
+		printf_isr("%s\"\r\n", msg);
+	} else {
+		printf("%s %s:%d [%s] \"", err_type, file, line, function);
+		printf("%s\"\r\n", msg);
+	}
+}
+
+__attribute__ ((format (__printf__, 5, 0)))
+static void err_printf(const char *err_type, const char *file, int line,
+		const char *function, const char *msg, va_list ap)
+{
+	if (in_critical()) {
+		printf_isr("%s %s:%d [%s] \"", err_type, file, line, function);
+	        vprintf_isr(msg, ap);
+		printf_isr("\"\r\n");
+	} else {
+		printf("%s %s:%d [%s] \"", err_type, file, line, function);
+	        vprintf(msg, ap);
+		printf("\"\r\n");
+	}
+}
+
+__attribute__ ((weak))
+void halt_on_bug(void)
+{
+	/* Prevent interrupts from firing */
+	rtosTaskEnterCritical();
+
+	for (;;) {
+	}
+}
+
+void bug_hook_imp(const char *file, int line, const char *function,
+	const char *msg)
+{
+	err_msg("BUG:", file, line, function, msg);
+	halt_on_bug();
+}
+
+void bug_hookf_imp(const char *file, int line, const char *function,
+	const char *msg, ...)
+{
+	va_list args;
+	va_start(args, msg);
+	err_printf("BUG:", file, line, function, msg, args);
+	va_end(args);
+	halt_on_bug();
+}
+
+void error_hookf_imp(const char *file, int line, const char *function,
+	const char *msg, ...)
+{
+	va_list args;
+	va_start(args, msg);
+	err_printf("ERROR:", file, line, function, msg, args);
+	va_end(args);
+}
+
+static inline bool has_been_done(bool *once)
+{
+	if (in_interrupt()) {
+		if (*once) {
+			return true;
+		}
+
+		*once = true;
+
+		return false;
+	} else {
+		rtosTaskEnterCritical();
+
+		if (*once) {
+			rtosTaskExitCritical();
+			return true;
+		}
+
+		*once = true;
+
+		rtosTaskExitCritical();
+
+		return false;
+	}
+}
+
+void error_hookf_once_imp(bool *once,
+		const char *file, int line, const char *function,
+		const char *msg, ...)
+{
+	if (!has_been_done(once)) {
+		va_list args;
+		va_start(args, msg);
+		err_printf("ERROR:", file, line, function, msg, args);
+		va_end(args);
+	}
+}
+
+void warning_hookf_imp(const char *file, int line, const char *function,
+	const char *msg, ...)
+{
+	va_list args;
+	va_start(args, msg);
+	err_printf("WARNING:", file, line, function, msg, args);
+	va_end(args);
+}
+
+void warning_hookf_once_imp(bool *once,
+		const char *file, int line, const char *function,
+		const char *msg, ...)
+{
+	if (!has_been_done(once)) {
+		va_list args;
+		va_start(args, msg);
+		err_printf("WARNING:", file, line, function, msg, args);
+		va_end(args);
+	}
+}
+
+void error_hook_imp(const char *file, int line, const char *function,
+	const char *msg)
+{
+	err_msg("ERROR:", file, line, function, msg);
+}
+
+void warning_hook_imp(const char *file, int line, const char *function,
+	const char *msg)
+{
+	err_msg("WARNING:", file, line, function, msg);
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/ivc-channel-ids.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/ivc-channel-ids.c
new file mode 100644
index 0000000..fe3cc85
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/ivc-channel-ids.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (c) 2016-2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <tegra-ivc.h>
+#include <ivc-channels.h>
+#include <ivc-config.h>
+#include <ivc-echo-task.h>
+
+static struct tegra_ivc_channel ivc_echo_ch = {
+	.write_header = (void *)IVC_ECHO_WRITE_HEADER,
+	.read_header = (void *)IVC_ECHO_READ_HEADER,
+	.nframes = IVC_ECHO_CH_NFRAMES,
+	.frame_size = IVC_ECHO_CH_FRAME_SIZE,
+	.notify_remote = hsp_ivc_notify_ccplex,
+	.channel_group = IVC_ECHO_CH_ID,
+};
+
+static struct ivc_channel_ops ivc_echo_ops = {
+	.init = ivc_echo_task_init,
+	.notify = ivc_echo_task_ivc_notified,
+	.init_complete = ivc_echo_task_ivc_inited,
+};
+
+static struct ivc_task_id ivc_echo_task_id = {
+	.name = "echo task",
+	.ivc_ch = &ivc_echo_ch,
+	.ops = &ivc_echo_ops,
+};
+
+struct ivc_task_id *ivc_ccplex_task_ids[IVC_NUM_CCPLEX_CHS] = {
+	&ivc_echo_task_id,
+};
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/newlib-syscalls.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/newlib-syscalls.c
new file mode 100644
index 0000000..609d3d6
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/newlib-syscalls.c
@@ -0,0 +1,139 @@
+/*
+ * Copyright (c) 2014-2024, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ *
+ * This file fills in the hooks needed by libc. Libc functions like
+ * malloc and printf.
+ *
+ */
+
+#include <string.h>
+#include <sys/stat.h>
+
+#include <osa/osa-task.h>
+
+#include <debug/debug.h>
+
+extern char _heap_start;
+extern char _heap_end;
+static char *_heap_watermark;
+
+void *_sbrk(int incr);
+void __malloc_lock(struct _reent *ptr);
+void __malloc_unlock(struct _reent *ptr);
+int _close(int file);
+int _fstat(int file, struct stat *st);
+int _isatty(int file);
+int _lseek(int file, int ptr, int dir);
+int _read(int file, char * ptr, int len);
+int _write(int file, char *ptr, int len);
+int _getpid(void);
+int _kill(int pid, int sig);
+void _exit(int status);
+
+int _total_incr = 0;
+void * __attribute__((weak)) _sbrk(int incr)
+{
+	char *brkval;
+
+	if (!_heap_watermark)
+		_heap_watermark = &_heap_start;
+
+	if (((&_heap_end) - _heap_watermark) < incr)
+		return (void *)-1;
+
+	brkval = _heap_watermark;
+	_heap_watermark += incr;
+
+	memset(brkval, 0, incr);
+	_total_incr += incr;
+
+	return brkval;
+}
+
+void __attribute__((weak)) __malloc_lock(struct _reent *ptr)
+{
+	rtosTaskSuspendScheduler();
+}
+
+void __attribute__((weak)) __malloc_unlock(struct _reent *ptr)
+{
+	rtosTaskResumeScheduler();
+}
+
+int __attribute__((weak)) _close(int file)
+{
+	return -1;
+}
+
+int __attribute__((weak)) _fstat(int file, struct stat *st)
+{
+	st->st_mode = S_IFCHR;
+	return 0;
+}
+
+int __attribute__((weak)) _isatty(int file)
+{
+	return 1;
+}
+
+int __attribute__((weak)) _lseek(int file, int ptr, int dir)
+{
+	return -1;
+}
+
+int __attribute__((weak)) _read(int file, char * ptr, int len)
+{
+	return -1;
+}
+
+int __attribute__((weak)) _write(int file, char *ptr, int len)
+{
+	if ((file != 1 && file != 2) || len <= 0)
+		return -1;
+
+	dbg_putd(ptr, len);
+
+	return len;
+}
+
+int __attribute__((weak)) _getpid(void)
+{
+	return -1;
+}
+
+int __attribute__((weak)) _kill(int pid, int sig)
+{
+	return -1;
+}
+
+void __attribute__((weak)) _exit(int status)
+{
+	return;
+}
\ No newline at end of file
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/print.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/print.c
new file mode 100644
index 0000000..ee6210b
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/print.c
@@ -0,0 +1,170 @@
+/*
+ * Copyright (c) 2019-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdarg.h>            // for va_end, va_start
+#include <stdint.h>            // for uint32_t
+#include <stdio.h>             // for vsnprintf
+
+/* local rtos headers */
+#include <osa/rtos-task.h>
+#include <osa/rtos-semaphore.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <irq/safe-irqs.h>
+
+/* Module-specific FSP headers */
+#include <debug/printf-isr.h>
+#include <debug/print.h>
+
+/* local headers */
+#include <spe-uart.h>
+#include <tcu.h>
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__DEBUG__PRINT_H, "Header file missing or invalid.")
+
+#define PRINTF_BUFSIZE     128UL
+
+static uint32_t print_log_level = PRINT_LEVEL_INFO;
+
+#if defined(USE_GCC) && (USE_GCC == 1)
+static int vprintf_msg(const char *fmt, va_list ap)
+    __attribute__ ((format (__printf__, 1, 0)));
+#endif
+
+static int print_msg(const char* msg_buf, int len, bool from_isr)
+{
+    uint32_t written = 0UL;
+
+    if (from_isr) {
+        spe_uart_write_now(msg_buf, len);
+        written = len;
+        goto out;
+    }
+    enter_critical();
+    spe_uart_write_now(msg_buf, len);
+    written = len;
+    exit_critical();
+
+out:
+    return written;
+}
+
+int32_t vprintf_isr(const char *fmt, va_list ap)
+{
+    char msg[PRINTF_ISR_BUFSIZE];
+    int ret;
+
+    ret = vsnprintf(msg, PRINTF_ISR_BUFSIZE, fmt, ap);
+
+    if (ret > 0)
+    {
+        ret = (ret > PRINTF_ISR_BUFSIZE) ? PRINTF_ISR_BUFSIZE : ret;
+        if (is_tcu_enabled()) {
+            tcu_print_msg(msg, ret, true);
+        } else {
+            print_msg(msg, ret, true);
+        }
+    }
+
+    return ret;
+}
+
+int32_t printf_isr(const char *fmt, ...)
+{
+    va_list args;
+    int ret;
+
+    va_start(args, fmt);
+    ret = vprintf_isr(fmt, args);
+    va_end(args);
+
+    return ret;
+}
+
+static int vprintf_msg(const char *fmt, va_list ap)
+{
+    char msg[PRINTF_BUFSIZE];
+    int ret;
+
+    ret = vsnprintf(msg, PRINTF_BUFSIZE, fmt, ap);
+
+    if (ret > 0)
+    {
+        ret = (ret > PRINTF_BUFSIZE) ? PRINTF_BUFSIZE : ret;
+        if (is_tcu_enabled()) {
+            tcu_print_msg(msg, ret, false);
+        } else {
+            print_msg(msg, ret, false);
+        }
+    }
+
+    return ret;
+}
+
+void print_message(uint32_t level,
+                   const char *format,
+                   ...)
+{
+    va_list args;
+
+    if (level <= print_log_level) {
+        va_start(args, format);
+        if (in_interrupt()) {
+            vprintf_isr(format, args);
+        } else {
+            vprintf_msg(format, args);
+        }
+        va_end(args);
+    }
+}
+
+void set_print_log_level(const uint32_t level)
+{
+    print_log_level = level;
+}
+
+uint32_t get_print_log_level(void)
+{
+    return print_log_level;
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/tcu.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/tcu.c
new file mode 100644
index 0000000..587293b
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/tcu.c
@@ -0,0 +1,905 @@
+/*
+ * Copyright (c) 2017-2023, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+
+/* local os headers */
+#include <osa/osa-task.h>
+#include <osa/osa-errors.h>
+#include <osa/osa-semaphore.h>
+#include <osa/osa-queue.h>
+#include <osa/osa-mutex.h>
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <chipid/chip-id.h>
+#include <error/common-errors.h>
+#include <hsp/hsp-tegra.h>
+#include <processor/hsp-tegra-hw.h>
+#include <debug/print.h>
+#include <misc/macros.h>
+#include <irq/safe-irqs.h>
+#include <tke/tke-tegra.h>
+#include <misc/bitops.h>
+
+/* local headers */
+#include <spe-uart.h>
+#include <mbox-aon.h>
+#include <tcu.h>
+#include <tcu-priv.h>
+#include <spe-errors.h>
+#include <err-hook.h>
+
+#define NUM_BYTES_FIELD_BIT       24U
+#define FLUSH_BIT                 26U
+#define HW_FLUSH_BIT              27U
+#define DMA_MODE_BIT              30U
+#define INTR_TRIGGER_BIT          31U
+#define NUM_BYTES(reg_val)        ((reg_val >> NUM_BYTES_FIELD_BIT) & 0x3U)
+
+#define SPE_TX_QUEUE_SIZE         rtos_queue_size(SPE_NUM_MSGS, \
+                                             sizeof(uint32_t))
+
+#define TCU_ESCAPE_START          0xFF
+#define TCU_ESCAPE_CHAR           0xFF
+#define TAG_ESCAPE_CHAR           0xFF
+#define TAG_ESCAPE_STRING         "\377"
+
+#define TAG_RESET                 0xFD
+#define TAG_BOOT_RESET_STRING     "\0\377\375"
+
+#define RX_TIMEOUT_MS             100UL
+#define RX_TIMEOUT_US             (RX_TIMEOUT_MS * 1000UL)
+
+#define ESCAPE                    2UL
+#define NORMAL                    1UL
+
+static struct spe_uart *uart = NULL;
+static bool tcu_enable       = false;
+static bool tcu_inited       = false;
+static bool tcu_preinited    = false;
+static bool tcu_suspended    = false;
+
+static rtosSemaphoreHandle tx_sem;
+
+static char spe_tx_fifo[SPE_NUM_MSGS][SPE_MSG_SIZE];
+
+static uint32_t spe_tx_wr = 0;
+static uint32_t spe_tx_rd = 0;
+
+static tcu_client_t spe_id = {
+    .tag = 0xe0,
+};
+static const tcu_client_t *last_id = NULL;
+static tcu_client_t *ext_clients;
+static uint32_t     nclients;
+
+/* spe tx task handle, used on notifications to the task */
+static rtosTaskHandle spe_tx_handle;
+
+/* spe rx task handle, used on notifications to the task */
+static rtosTaskHandle spe_rx_handle;
+
+static void spe_tx_task (void *param);
+static void spe_rx_task (void *param);
+static void
+tcu_print(const tcu_client_t *id,
+          const char *msg_buf,
+          int32_t len);
+int _write(int file, char *ptr, int len);
+
+rtos_task_define_s(spe_tx_task,
+                 spe_tx_task,
+                 (char *)"spe_tx",
+                 configMAX_PRIORITIES - 3,
+                 &spe_id,
+                 configMINIMAL_STACK_SIZE);
+
+rtos_task_define_s(spe_rx_task,
+                 spe_rx_task,
+                 (char *)"spe_rx",
+                 configMAX_PRIORITIES - 2,
+                 &spe_id,
+                 configMINIMAL_STACK_SIZE);
+
+void tcu_tx_task(void *param);
+void tcu_rx_task(void *param);
+
+int _write(int file, char *ptr, int len)
+{
+
+	if (len <= 0)
+		return len;
+
+	/* stderr */
+	if (file == 2) {
+
+		len = tcu_print_msg(ptr, len, true);
+		return len;
+	}
+
+	if (file != 1)
+		return -1;
+
+	/* stdout */
+	tcu_print(&spe_id, ptr, len);
+	return len;
+}
+
+void
+set_tcu_status(bool enable)
+{
+    tcu_enable = enable;
+}
+
+bool
+is_tcu_enabled(void)
+{
+    return tcu_enable;
+}
+
+static void
+tcu_raw_print(const char *str,
+              int32_t len)
+{
+    uint32_t written = 0UL;
+    uint32_t wcount = 0UL;
+    error_t  ret;
+
+    if (!tcu_inited) {
+        goto out;
+    }
+
+    if (in_interrupt() || in_critical() ||
+                (rtosTaskIsSchedulerStarted() == rtosFALSE)) {
+        uart->ops->write_now(uart->ctlr, str, len);
+        goto out;
+    }
+
+    while (written < len) {
+        ret = uart->ops->write(uart->ctlr,
+                               str,
+                               len - written,
+                               &wcount,
+                               rtosMAX_DELAY);
+        if (ret != E_SUCCESS) {
+            break;
+        }
+        written += wcount;
+    }
+
+out:
+    return;
+}
+
+static void
+tcu_dbg_putc(const char *str,
+             int32_t len)
+{
+    const char *buf, *tag_escape;
+    int32_t    remaining;
+    int32_t    current_len;
+
+    buf = str;
+    remaining = len;
+    while (remaining > 0) {
+        tag_escape = memchr(buf, TAG_ESCAPE_CHAR, remaining);
+
+        current_len = tag_escape ?
+                      tag_escape - buf + 1 :
+                      remaining;
+
+        tcu_raw_print(buf, current_len);
+        if (buf[current_len - 1] == TAG_ESCAPE_CHAR) {
+            tcu_raw_print(TAG_ESCAPE_STRING, 1);
+        }
+
+        buf += current_len;
+        remaining -= current_len;
+    }
+}
+
+static void
+tcu_print(const tcu_client_t *id,
+          const char *msg_buf,
+          int32_t len)
+{
+    char c;
+
+    if (last_id != id) {
+        tcu_raw_print(TAG_ESCAPE_STRING, 1);
+        c = id->tag;
+        tcu_raw_print(&c, 1);
+        last_id = id;
+    }
+
+    if (len > 0) {
+        tcu_dbg_putc(msg_buf, len);
+    }
+}
+
+int
+tcu_print_msg(const char* msg_buf,
+              int len,
+              bool from_isr)
+{
+    error_t status;
+
+    if (len <= 0) {
+        goto out;
+    }
+
+    if (from_isr || (rtosTaskIsSchedulerStarted() == rtosFALSE)) {
+        tcu_print(&spe_id, msg_buf, len);
+        goto out;
+    }
+
+    len = (len > SPE_MSG_SIZE) ? SPE_MSG_SIZE : len;
+
+    enter_critical();
+    memcpy(spe_tx_fifo[spe_tx_wr], msg_buf, len);
+    spe_tx_wr = (spe_tx_wr + 1) & (SPE_NUM_MSGS - 1);
+    exit_critical();
+
+    status = rtosQueueSend(spe_id.tx_queue,
+                             &len,
+                             tcu_inited ? rtosMAX_DELAY : 0);
+    if (status != rtosPASS) {
+        len = 0;
+        goto out;
+    }
+
+out:
+    return len;
+}
+
+static inline bool
+msg_needs_deferred_ack(uint32_t msg)
+{
+    return ((msg & (BIT(FLUSH_BIT) | BIT(HW_FLUSH_BIT))) != 0UL);
+}
+
+static void
+tcu_irq_handler(void *priv,
+                hsp_sm_data_t *value)
+{
+    tcu_client_t *client = (tcu_client_t *)priv;
+    rtosBool     higher_prio_task_woken = false;
+    uint32_t     data;
+    error_t      rc;
+
+    client->rx_enabled = true;
+    data = value->sm.val;
+    data &= ~MBOX_TAG_BIT;
+
+    rc = rtosQueueSendToBackFromISR(client->tx_queue,
+                                  &data,
+                                  &higher_prio_task_woken);
+    if (rc != rtosPASS) {
+        error_hook("rtosQueueSendFromISR() failed\r\n");
+        goto out;
+    }
+
+    if (msg_needs_deferred_ack(data)) {
+        (void) tegra_hsp_sm_full_disable(client->hsp_tx_id, client->recv_mbox);
+    } else if (rtosQueueIsQueueFullFromISR(client->tx_queue)) {
+        client->tx_fifo_full = true;
+        (void) tegra_hsp_sm_full_disable(client->hsp_tx_id, client->recv_mbox);
+    } else {
+        (void) tegra_hsp_sm_vacate(client->hsp_tx_id, client->recv_mbox);
+    }
+
+out:
+    rtosTaskYieldFromISR(higher_prio_task_woken);
+}
+
+static void
+tcu_process_tx_queue_msg(tcu_client_t *client,
+                         uint32_t msg)
+{
+    uint32_t nbytes;
+    uint32_t i;
+    error_t  rc;
+    char     buf[3];
+
+    /* fetch number of bytes from the message packet */
+    nbytes = NUM_BYTES(msg);
+
+    /* extract chars from message packet */
+    for (i = 0UL; i < nbytes; i += 1UL) {
+        buf[i] = (msg >> (i * 8U)) & 0xFFU;
+    }
+
+    /* acquire tx semaphore */
+    rc = rtosSemaphoreAcquire(tx_sem, rtosMAX_DELAY);
+    if (rc != rtosPASS) {
+        goto out;
+    }
+
+    tcu_print(client, buf, nbytes);
+
+    /* handle flush if specified */
+    if ((msg & BIT(HW_FLUSH_BIT)) != 0UL) {
+        (void) uart->ops->flush(uart->ctlr);
+        (void) uart->ops->flush_hw(uart->ctlr);
+    }
+
+    /* release tx semaphore */
+    rtosSemaphoreRelease(tx_sem);
+
+out:
+    return;
+}
+
+void
+tcu_tx_task(void *param)
+{
+    tcu_client_t *client = (tcu_client_t *)param;
+    uint32_t     msg;
+    error_t      status;
+    error_t      ret;
+    bool         tx_fifo_full;
+    rtosError    queue_available;
+
+    for (;;) {
+        /* check for any pending messages on the tx fifo */
+        status = rtosQueueReceive(client->tx_queue,
+                                    &msg,
+                                    rtosMAX_DELAY);
+        enter_critical();
+        if (status != rtosPASS) {
+            exit_critical();
+            continue;
+        }
+        tx_fifo_full = client->tx_fifo_full;
+        queue_available = rtosQueueSpacesAvailable(client->tx_queue);
+        exit_critical();
+
+        tcu_process_tx_queue_msg(client, msg);
+
+        if ((tx_fifo_full && queue_available != 0) ||
+                                   msg_needs_deferred_ack(msg)) {
+            /*
+             * Entering this block imples MBOX irq is disabled. Therefore,
+             * synchronization is not necessary.
+             */
+            client->tx_fifo_full = false;
+            ret = tegra_hsp_sm_vacate(client->hsp_tx_id, client->recv_mbox);
+            if (ret != E_SUCCESS) {
+                continue;
+            }
+            ret = tegra_hsp_sm_full_enable(client->hsp_tx_id,
+                                           client->recv_mbox,
+                                           tcu_irq_handler,
+                                           client);
+        }
+    }
+}
+
+static void
+send_rx_chars(tcu_client_t *client,
+              uint8_t *chs,
+              uint32_t len)
+{
+    uint32_t mbox_val;
+    uint32_t tstart;
+    uint32_t i;
+
+    mbox_val = (len << NUM_BYTES_FIELD_BIT) | BIT(INTR_TRIGGER_BIT);
+    for (i = 0UL; i < len; i += 1UL) {
+        mbox_val |= ((chs[i] & 0xFFU) << (i * 8U));
+    }
+
+    tstart = tegra_tke_get_usec();
+    while (!tegra_hsp_sm_is_empty(client->hsp_id, client->send_mbox)) {
+        if (client->rx_timedout) {
+            goto out;
+        }
+
+        if (tegra_tke_get_usec() - tstart > RX_TIMEOUT_US) {
+            client->rx_timedout = true;
+            goto out;
+        }
+    }
+
+    client->rx_timedout = false;
+    (void)tegra_hsp_sm_produce(client->hsp_id, client->send_mbox, mbox_val);
+
+out:
+    return;
+}
+
+void
+tcu_rx_task(void *param)
+{
+    tcu_client_t  *client = (tcu_client_t *)param;
+    uint8_t       chs[3];
+    uint8_t       ch;
+    uint32_t      len;
+    uint32_t      i;
+    error_t       status;
+
+    for (;;) {
+        len = 0UL;
+        for (i = 0UL; i < ARRAY_SIZE(chs); i += 1UL) {
+            /* check for any pending messages on the tx fifo */
+            status = rtosQueueReceive(client->rx_queue,
+                                        &ch,
+                                        (i == 0UL) ? rtosMAX_DELAY : 0);
+            if (status != rtosPASS) {
+                break;
+            }
+            chs[len++] = ch;
+        }
+
+        if ((len > 0UL) && client->rx_enabled) {
+            send_rx_chars(client, chs, len);
+        }
+    }
+}
+
+static void
+spe_rx_task (void *param)
+{
+    tcu_client_t *dest_id = &ext_clients[TCU_ID_CCPLEX];
+    error_t      ret;
+    char         c;
+    uint32_t     rcount = 0;
+    uint32_t     state = NORMAL;
+    (void)       param;
+
+    for (;;) {
+        ret = uart->ops->read(uart->ctlr, &c, 1, &rcount, rtosMAX_DELAY);
+        if (ret != E_SUCCESS) {
+            continue;
+        }
+
+        switch (state) {
+            case ESCAPE:
+                /* Handle escape char */
+                if (c == TCU_ESCAPE_CHAR) {
+                    (void)rtosQueueSend(dest_id->rx_queue, &c, 0);
+                } else if (c == TAG_RESET) {
+                    rtosSemaphoreAcquire(tx_sem, rtosMAX_DELAY);
+                    last_id = NULL;
+                    rtosSemaphoreRelease(tx_sem);
+                } else {
+                    /* void the input */
+                    if (c == spe_id.tag) {
+                         dest_id = &spe_id;
+                    } else {
+                        dest_id = get_tcu_client_id(c);
+                    }
+                }
+                state = NORMAL;
+                break;
+            default: /* case: NORMAL */
+                if (c == TCU_ESCAPE_START) {
+                    state = ESCAPE;
+                } else {
+                    (void)rtosQueueSend(dest_id->rx_queue, &c, 0);
+                }
+                break;
+        }
+    }
+}
+
+static void
+spe_tx_task (void *param)
+{
+    tcu_client_t *id = (tcu_client_t *)param;
+    error_t      status;
+    uint32_t     len;
+
+
+    /* flush the HW TX fifo */
+    uart->ops->flush_hw(uart->ctlr);
+
+    for (;;) {
+        /* check for any pending messages on the tx fifo */
+        status = rtosQueueReceive(id->tx_queue,
+                                    &len,
+                                    rtosMAX_DELAY);
+        if (status != rtosPASS) {
+            continue;
+        }
+        /* acquire tx semaphore */
+        status = rtosSemaphoreAcquire(tx_sem,
+                                  rtosMAX_DELAY);
+        if (status != rtosPASS) {
+            continue;
+        }
+
+        /* print message and update the read pointer in SPE tx fifo*/
+        tcu_print(id, spe_tx_fifo[spe_tx_rd], len);
+        spe_tx_rd = (spe_tx_rd + 1UL) & (SPE_NUM_MSGS - 1UL);
+
+        /* release tx semaphore */
+        rtosSemaphoreRelease(tx_sem);
+    }
+}
+
+error_t
+tcu_preinit(void)
+{
+    error_t ret = E_SUCCESS;
+
+    rtosQueueCreate(NULL,
+                    0,
+                    SPE_NUM_MSGS,
+                    sizeof(uint32_t),
+                    &spe_id.tx_queue);
+
+    if (!spe_id.tx_queue) {
+        ret = E_TCU_PREINIT_FAIL;
+        goto out;
+    }
+
+    tcu_preinited = true;
+
+out:
+    return ret;
+}
+
+error_t
+tcu_init(uint32_t uart_id)
+{
+    error_t ret = E_SUCCESS;
+
+    /* validate the uart controller id */
+    uart = spe_uart_get(uart_id);
+    if (uart == NULL || uart->ctlr == NULL) {
+        ret = E_TCU_PORT_INVALID;
+        goto out;
+    }
+
+    /* Initialize uart port */
+    if (tcu_enable) {
+        ret = uart->ops->init(uart->ctlr, uart->conf);
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+    } else {
+        ret = uart->ops->init_3rdparty(uart->ctlr, uart->conf);
+        goto out;
+    }
+
+    /* update the tcu uart controller init status */
+    tcu_inited = true;
+
+    tcu_raw_print(TAG_BOOT_RESET_STRING, 3);
+
+    /* create SPE tx queue only if preinit was not called.
+     * preinit is only needed for t19x and not for t23x as
+     * MB2 loads SPE on t23x and UART can be accessed from
+     * early boot.
+     */
+    if (!tcu_preinited) {
+        rtosQueueCreate(NULL,
+                        0,
+                        SPE_NUM_MSGS,
+                        sizeof(uint32_t),
+                        &spe_id.tx_queue);
+        if (!spe_id.tx_queue) {
+            ret = E_TCU_INIT_FAIL;
+            goto out;
+        }
+    }
+
+    rtosMutexCreate(NULL, &tx_sem);
+    if (!tx_sem) {
+        ret = E_TCU_INIT_FAIL;
+        goto out;
+    }
+    rtosSemaphoreRelease(tx_sem);
+
+out:
+    return ret;
+}
+
+static error_t
+tcu_client_setup_tx(tcu_client_t *client)
+{
+    error_t                ret = E_SUCCESS;
+    error_t                status;
+    const rtosTaskParameters *task_params;
+
+    /* create the client tx task queue */
+    status = rtosQueueCreate(NULL,
+                             0,
+                             EXT_CLIENT_MSG_SIZE,
+                             sizeof(uint32_t),
+                             &client->tx_queue);
+    if (!client->tx_queue) {
+        error_hookf("rtosQueueCreate(tcu_tx id %d) failed!\r\n", client->id);
+        ret = E_TCU_CLIENT_TX_SETUP_FAIL;
+        goto out;
+    }
+
+    /* fetch the client tx task parameters */
+    task_params = get_tcu_client_tx_task_params(client->id);
+
+     /* create the client tx task */
+    status = rtosTaskCreate(task_params, NULL);
+    if (status != rtosPASS) {
+        error_hookf("rtosTaskCreate(tcu_tx %d) failed!\r\n", client->id);
+        ret = E_TCU_CLIENT_TX_SETUP_FAIL;
+        goto out;
+    }
+
+    /* Initialize tx hsp if client does not use AON sm for tx */
+    if (client->aon_sm_for_tx) {
+        client->hsp_tx_id = &tegra_hsp_id_aon;
+    } else {
+        ret = tegra_hsp_init(client->hsp_tx_id);
+        if (ret != E_SUCCESS) {
+            error_hook("tcu_tx hsp init failed!\r\n");
+            goto out;
+        }
+    }
+
+    ret = tegra_hsp_sm_full_enable(client->hsp_tx_id,
+                                   client->recv_mbox,
+                                   tcu_irq_handler,
+                                   client);
+    if (ret != E_SUCCESS) {
+        error_hookf("hsp_sm_full_enable(tcu_tx %d) failed!\r\n", client->id);
+        ret = E_TCU_CLIENT_TX_SETUP_FAIL;
+    }
+
+out:
+    return ret;
+}
+
+static error_t
+tcu_client_setup_rx(tcu_client_t *client)
+{
+    error_t                ret = E_SUCCESS;
+    error_t                status;
+    const rtosTaskParameters *task_params;
+
+    /* It is okay to not support RX */
+    if (client->hsp_id == NULL) {
+        goto out;
+    }
+
+    /* support RX and create the client rx task queue */
+    status = rtosQueueCreate(NULL,
+                             0,
+                             EXT_CLIENT_RX_BUF_SIZE,
+                             1,
+                             &client->rx_queue);
+    if (!client->rx_queue) {
+        error_hookf("rtosQueueCreate(tcu_rx id %d) failed!\r\n", client->id);
+        ret = E_TCU_CLIENT_RX_SETUP_FAIL;
+        goto out;
+    }
+
+    /* fetch the client rx task parameters */
+    task_params = get_tcu_client_rx_task_params(client->id);
+    if (task_params == NULL) {
+        error_hookf("get_tcu_rx_task_params(id: %d) failed!\r\n", client->id);
+        ret = E_TCU_CLIENT_NO_RX_TASK;
+        goto out;
+    }
+
+    /* initialize the rx HSP context */
+    ret = tegra_hsp_init(client->hsp_id);
+    if (ret != E_SUCCESS) {
+        error_hook("tcu_rx hsp init failed!\r\n");
+        goto out;
+    }
+
+    /* create the rx task */
+    status = rtosTaskCreate(task_params, NULL);
+    if (status != rtosPASS) {
+        error_hookf("rtosTaskCreate(tcu_rx id %d) failed!\r\n", client->id);
+        ret = E_TCU_CLIENT_RX_SETUP_FAIL;
+    }
+
+out:
+    return ret;
+}
+
+static error_t
+tcu_clients_init(void)
+{
+    error_t      ret = E_SUCCESS;
+    uint32_t     i;
+    tcu_client_t *client;
+
+    nclients = get_tcu_client_count();
+
+    if (nclients == 0UL) {
+        goto out;
+    }
+
+    ext_clients = get_tcu_clients_handle();
+    for (i = 0UL; i < nclients; i += 1UL) {
+        client = &ext_clients[i];
+
+       /**
+         * For some platforms such as L4T, some clients are not even deasserted
+         * reset. Use this pre-enable check to decide whether to enable tcu for
+         * them.
+         */
+        if (client->enable_check != NULL) {
+            client->enabled = client->enable_check();
+        }
+
+        if (!client->enabled) {
+            continue;
+        }
+
+        client->rx_enabled = false;
+        client->rx_timedout = false;
+        client->tx_fifo_full = false;
+
+        ret = tcu_client_setup_rx(client);
+        if (ret != E_SUCCESS) {
+            error_hookf("tcu_client_setup_rx() failed!: %ld\r\n", ret);
+            break;
+        }
+
+        ret = tcu_client_setup_tx(client);
+        if (ret != E_SUCCESS) {
+            error_hookf("tcu_client_setup_tx() failed!: %ld\r\n", ret);
+            break;
+        }
+    }
+
+out:
+    return ret;
+}
+
+error_t
+tcu_tasks_init(void)
+{
+    error_t ret = E_SUCCESS;
+    error_t status;
+
+    /*
+     * create the SPE tx task which will buffer uart logging from
+     * SPE.
+     */
+    status = rtosTaskCreate(&spe_tx_task_params, &spe_tx_handle);
+    if (status != rtosPASS) {
+        ret = E_TCU_INIT_FAIL;
+        goto out;
+    }
+
+    status = rtosTaskCreate(&spe_rx_task_params, &spe_rx_handle);
+    if (status != rtosPASS) {
+        ret = E_TCU_INIT_FAIL;
+        goto out;
+    }
+
+    /* create the external clients TX and RX tasks */
+    ret = tcu_clients_init();
+    if (ret != E_SUCCESS) {
+        ret = E_TCU_EXT_CLIENTS_INIT_FAIL;
+    }
+
+out:
+    return ret;
+}
+
+
+error_t
+tcu_suspend(void)
+{
+    error_t         ret = E_SUCCESS;
+    error_t         rc;
+    tcu_client_t    *bpmp;
+    tcu_client_t    *ccplex;
+
+    if (!tcu_inited) {
+        ret = E_TCU_NO_INIT;
+        goto out;
+    }
+
+    bpmp = &ext_clients[TCU_ID_BPMP];
+    ccplex = &ext_clients[TCU_ID_CCPLEX];
+
+    rc = rtosSemaphoreAcquire(tx_sem, rtosMAX_DELAY);
+    if (rc != rtosPASS) {
+        ret = rc;
+        error_hook("tcu tx sem acquire failed!\r\n");
+        goto out;
+    }
+
+    tcu_print(bpmp, "", 0);
+    tcu_inited = false;
+
+    /* release tx semaphore */
+    rtosSemaphoreRelease(tx_sem);
+
+    ret = tegra_hsp_sm_full_disable(ccplex->hsp_tx_id, ccplex->recv_mbox);
+    if (ret != E_SUCCESS) {
+        error_hook("tcu ccplex tx irq disable failed!\r\n");
+    }
+
+    ret = uart->ops->flush(uart->ctlr);
+    if (ret != E_SUCCESS) {
+        error_hook("tcu flush failed!\r\n");
+    }
+
+    ret = uart->ops->flush_hw(uart->ctlr);
+    if (ret != E_SUCCESS) {
+        error_hook("tcu hw flush failed!\r\n");
+    }
+
+    ret = uart->ops->suspend(uart->ctlr);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    tcu_suspended = true;
+
+out:
+    return ret;
+}
+
+error_t
+tcu_resume(void)
+{
+    error_t ret = E_SUCCESS;
+    tcu_client_t *ccplex;
+
+    if (!tcu_suspended) {
+        ret = E_TCU_NO_SUSPEND;
+        goto out;
+    }
+
+    ccplex = &ext_clients[TCU_ID_CCPLEX];
+
+    ret = uart->ops->resume(uart->ctlr);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    tcu_inited = true;
+    tcu_suspended = false;
+
+    ret = tegra_hsp_sm_full_enable(ccplex->hsp_tx_id,
+                                   ccplex->recv_mbox,
+                                   tcu_irq_handler,
+                                   ccplex);
+    if (ret != E_SUCCESS) {
+        error_hook("tcu ccplex tx resume failed!\r\n");
+    }
+
+out:
+    return ret;
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/tegra-ivc.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/tegra-ivc.c
new file mode 100644
index 0000000..24b66a8
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/tegra-ivc.c
@@ -0,0 +1,704 @@
+/*
+ * Copyright (c) 2015-2018, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stddef.h>
+#include <string.h>
+
+#include <cpu/cache.h>
+#include <cpu/barriers.h>
+#include <tegra-ivc.h>
+
+/*
+ * FIXME: We may want to parameterize this in the future
+ * FIXME: We may want to ensure this is a multiple of the runtime cache line
+ *        size in the future.
+ */
+#define TEGRA_IVC_ALIGN 64
+
+/*
+ * IVC channel reset protocol.
+ *
+ * Each end uses its tx_channel.state to indicate its synchronization state.
+ * Declaring as anonymous enum so that the enum values can be compared directly
+ * with int32_t without any explicit conversion.
+ */
+enum {
+	/*
+	 * This value is zero for backwards compatibility with services that
+	 * assume channels to be initially zeroed. Such channels are in an
+	 * initially valid state, but cannot be asynchronously reset, and must
+	 * maintain a valid state at all times.
+	 *
+	 * The transmitting end can enter the established state from the sync or
+	 * ack state when it observes the receiving endpoint in the ack or
+	 * established state, indicating that has cleared the counters in our
+	 * rx_channel.
+	 */
+	ivc_state_established = 0,
+
+	/*
+	 * If an endpoint is observed in the sync state, the remote endpoint is
+	 * allowed to clear the counters it owns asynchronously with respect to
+	 * the current endpoint. Therefore, the current endpoint is no longer
+	 * allowed to communicate.
+	 */
+	ivc_state_sync,
+
+	/*
+	 * When the transmitting end observes the receiving end in the sync
+	 * state, it can clear the w_count and r_count and transition to the ack
+	 * state. If the remote endpoint observes us in the ack state, it can
+	 * return to the established state once it has cleared its counters.
+	 */
+	ivc_state_ack
+};
+
+/*
+ * This structure is divided into two-cache aligned parts, the first is only
+ * written through the write_header pointer, while the second is only written
+ * through the read_header pointer. This delineates ownership of the cache lines,
+ * which is critical to performance and necessary in non-cache coherent
+ * implementations.
+ */
+struct tegra_ivc_channel_header {
+	union {
+		struct {
+			uint32_t count;
+			int32_t state;
+		} d;
+		uint8_t align[TEGRA_IVC_ALIGN];
+	} write;
+	union {
+		struct {
+			uint32_t count;
+		} d;
+		uint8_t align[TEGRA_IVC_ALIGN];
+	} read;
+};
+
+static inline int tegra_ivc_notify_read_remote(struct tegra_ivc_channel *ch)
+{
+	return ch->notify_remote(ch, true);
+}
+
+static inline int tegra_ivc_notify_write_remote(struct tegra_ivc_channel *ch)
+{
+	return ch->notify_remote(ch, false);
+}
+
+static size_t tegra_ivc_total_channel_size(struct tegra_ivc_channel *ch)
+{
+	return sizeof(struct tegra_ivc_channel_header) +
+		(ch->nframes * ch->frame_size);
+}
+
+static void *tegra_ivc_pointer_after(struct tegra_ivc_channel *ch, void *header)
+{
+	uint8_t *p = header;
+	p += tegra_ivc_total_channel_size(ch);
+	return p;
+}
+
+/* Invalidate an entire channel header (both read and write sub-structs) */
+static void tegra_ivc_invalidate_header(struct tegra_ivc_channel_header *hdr)
+{
+	cache_invalidate(hdr, sizeof(*hdr));
+}
+
+/*
+ * Invalidate the entire channel header for our write path. This is required
+ * before we start communication over a channel for which the remote CPU has
+ * already set up the headers, so that we're completely in sync on both read
+ * and write counts.
+ */
+static void tegra_ivc_invalidate_entire_write_header(
+	struct tegra_ivc_channel *ch)
+{
+	tegra_ivc_invalidate_header(ch->write_header);
+}
+
+/*
+ * Invalidate the entire channel header for our read path. This is required
+ * before we start communication over a channel for which the remote CPU has
+ * already set up the headers, so that we're completely in sync on both read
+ * and write counts.
+ */
+static void tegra_ivc_invalidate_entire_read_header(
+	struct tegra_ivc_channel *ch)
+{
+	tegra_ivc_invalidate_header(ch->read_header);
+}
+
+/*
+ * Invalidate the remote portion of the header for our write path.
+ * That is, the read sub-struct of the write path header.
+ */
+static void tegra_ivc_invalidate_write_path_remote_header(
+	struct tegra_ivc_channel *ch)
+{
+	struct tegra_ivc_channel_header *hdr = ch->write_header;
+
+	cache_invalidate(&hdr->read.d, sizeof(hdr->read.d));
+}
+
+/*
+ * Invalidate the remote portion of the header for our read path.
+ * That is, the write sub-struct of the read path header.
+ */
+static void tegra_ivc_invalidate_read_path_remote_header(
+	struct tegra_ivc_channel *ch)
+{
+	struct tegra_ivc_channel_header *hdr = ch->read_header;
+
+	cache_invalidate(&hdr->write.d, sizeof(hdr->write.d));
+}
+
+/*
+ * Clean the local portion of the header for our write path.
+ * That is, the write sub-struct of the write path header.
+ */
+static void tegra_ivc_clean_write_path_local_header(struct tegra_ivc_channel *ch)
+{
+	struct tegra_ivc_channel_header *hdr = ch->write_header;
+
+	cache_clean(&hdr->write.d, sizeof(hdr->write.d));
+}
+
+/*
+ * Clean the local portion of the header for our read path.
+ * That is, the read sub-struct of the read path header.
+ */
+static void tegra_ivc_clean_read_path_local_header(struct tegra_ivc_channel *ch)
+{
+	struct tegra_ivc_channel_header *hdr = ch->read_header;
+
+	cache_clean(&hdr->read.d, sizeof(hdr->read.d));
+}
+
+static int tegra_ivc_validate_channel_conf(struct tegra_ivc_channel *ch)
+{
+	if (offsetof(struct tegra_ivc_channel_header, write) &
+			(TEGRA_IVC_ALIGN - 1))
+		return -1;
+	if (offsetof(struct tegra_ivc_channel_header, read) &
+			(TEGRA_IVC_ALIGN - 1))
+		return -1;
+	if (sizeof(struct tegra_ivc_channel_header) & (TEGRA_IVC_ALIGN - 1))
+		return -1;
+
+	if (((size_t)(ch->write_header)) & (TEGRA_IVC_ALIGN - 1))
+		return -1;
+	if (((size_t)(ch->read_header)) & (TEGRA_IVC_ALIGN - 1))
+		return -1;
+
+	if (ch->frame_size & (TEGRA_IVC_ALIGN - 1))
+		return -1;
+
+	if (ch->write_header < ch->read_header) {
+		if (tegra_ivc_pointer_after(ch, ch->write_header) >
+				ch->read_header)
+			return -1;
+	} else {
+		if (tegra_ivc_pointer_after(ch, ch->read_header) >
+				ch->write_header)
+			return -1;
+	}
+
+	return 0;
+}
+
+int tegra_ivc_init_channel_in_ram(struct tegra_ivc_channel *ch)
+{
+	size_t ch_size;
+
+	int ret = tegra_ivc_validate_channel_conf(ch);
+	if (ret)
+		return ret;
+
+	ch_size = tegra_ivc_total_channel_size(ch);
+	memset(ch->write_header, 0, ch_size);
+	memset(ch->read_header, 0, ch_size);
+
+	cache_clean(ch->write_header, ch_size);
+	cache_clean(ch->read_header, ch_size);
+
+	ch->write_count = 0;
+	ch->read_count = 0;
+
+	return 0;
+}
+
+int tegra_ivc_init_channel_from_ram(struct tegra_ivc_channel *ch)
+{
+	struct tegra_ivc_channel_header *wh = ch->write_header;
+	struct tegra_ivc_channel_header *rh = ch->read_header;
+
+	int ret = tegra_ivc_validate_channel_conf(ch);
+	if (ret)
+		return ret;
+
+	tegra_ivc_invalidate_entire_write_header(ch);
+	tegra_ivc_invalidate_entire_read_header(ch);
+
+	ch->write_count = wh->write.d.count;
+	ch->read_count = rh->read.d.count;
+
+	return 0;
+}
+
+void tegra_ivc_channel_reset(struct tegra_ivc_channel *ch)
+{
+	struct tegra_ivc_channel_header *tx_hdr = ch->write_header;
+
+	tx_hdr->write.d.state = ivc_state_sync;
+
+	tegra_ivc_clean_write_path_local_header(ch);
+	barrier_memory_order();
+	tegra_ivc_notify_write_remote(ch);
+}
+
+bool tegra_ivc_check_channel(void *write_header,
+			void *read_header,
+			uint32_t nframes,
+			uint32_t frame_size)
+{
+	struct tegra_ivc_channel check = {
+		.write_header = write_header,
+		.read_header = read_header,
+		.nframes = nframes,
+		.frame_size = frame_size,
+	};
+
+	return tegra_ivc_validate_channel_conf(&check) == 0;
+}
+
+/*
+ * ===============================================================
+ *  IVC State Transition Table - see tegra_ivc_channel_notified()
+ * ===============================================================
+ *
+ *	local	remote	action
+ *	-----	------	-----------------------------------
+ *	SYNC	EST	<none>
+ *	SYNC	ACK	reset counters; move to EST; notify
+ *	SYNC	SYNC	reset counters; move to ACK; notify
+ *	ACK	EST	move to EST; notify
+ *	ACK	ACK	move to EST; notify
+ *	ACK	SYNC	reset counters; move to ACK; notify
+ *	EST	EST	<none>
+ *	EST	ACK	<none>
+ *	EST	SYNC	reset counters; move to ACK; notify
+ *
+ * ===============================================================
+ */
+
+bool tegra_ivc_channel_notified(struct tegra_ivc_channel *ch)
+{
+	struct tegra_ivc_channel_header *tx_hdr = ch->write_header;
+	struct tegra_ivc_channel_header *rx_hdr = ch->read_header;
+	int32_t peer_state;
+
+	/* Copy the receiver's state out of shared memory. */
+	tegra_ivc_invalidate_read_path_remote_header(ch);
+	peer_state = rx_hdr->write.d.state;
+
+	if (peer_state == ivc_state_sync) {
+		/*
+		 * Order observation of ivc_state_sync before stores clearing
+		 * tx_hdr.
+		 */
+		barrier_memory_order();
+
+		/*
+		 * Reset tx_hdr counters. The remote end is in the SYNC
+		 * state and won't make progress until we change our state,
+		 * so the counters are not in use at this time.
+		 */
+		tx_hdr->write.d.count = 0;
+		rx_hdr->read.d.count = 0;
+
+		ch->write_count = 0;
+		ch->read_count = 0;
+
+		tegra_ivc_clean_read_path_local_header(ch);
+
+		/*
+		 * Ensure that counters appear cleared before new state can be
+		 * observed.
+		 */
+		barrier_memory_order();
+
+		/*
+		 * Move to ACK state. We have just cleared our counters, so it
+		 * is now safe for the remote end to start using these values.
+		 */
+		tx_hdr->write.d.state = ivc_state_ack;
+		tegra_ivc_clean_write_path_local_header(ch);
+
+		/*
+		 * Notify remote end to observe state transition.
+		 */
+		tegra_ivc_notify_write_remote(ch);
+
+	} else if ((tx_hdr->write.d.state == ivc_state_sync) &&
+			(peer_state == ivc_state_ack)) {
+		/*
+		 * Order observation of ivc_state_sync before stores clearing
+		 * tx_hdr.
+		 */
+		barrier_memory_order();
+
+		/*
+		 * Reset tx_hdr counters. The remote end is in the ACK
+		 * state and won't make progress until we change our state,
+		 * so the counters are not in use at this time.
+		 */
+		tx_hdr->write.d.count = 0;
+		rx_hdr->read.d.count = 0;
+
+		ch->write_count = 0;
+		ch->read_count = 0;
+
+		tegra_ivc_clean_read_path_local_header(ch);
+
+		/*
+		 * Ensure that counters appear cleared before new state can be
+		 * observed.
+		 */
+		barrier_memory_order();
+
+		/*
+		 * Move to ESTABLISHED state. We know that the remote end has
+		 * already cleared its counters, so it is safe to start
+		 * writing/reading on this channel.
+		 */
+		tx_hdr->write.d.state = ivc_state_established;
+
+		tegra_ivc_clean_write_path_local_header(ch);
+
+		/*
+		 * Notify remote end to observe state transition.
+		 */
+		tegra_ivc_notify_write_remote(ch);
+
+	} else if (tx_hdr->write.d.state == ivc_state_ack) {
+		/*
+		 * At this point, we have observed the peer to be in either
+		 * the ACK or ESTABLISHED state. Next, order observation of
+		 * peer state before storing to tx_hdr.
+		 */
+
+		barrier_memory_order();
+
+		/*
+		 * Move to ESTABLISHED state. We know that we have previously
+		 * cleared our counters, and we know that the remote end has
+		 * cleared its counters, so it is safe to start writing/reading
+		 * on this channel.
+		 */
+		tx_hdr->write.d.state = ivc_state_established;
+
+		tegra_ivc_clean_write_path_local_header(ch);
+
+		/*
+		 * Notify remote end to observe state transition.
+		 */
+		tegra_ivc_notify_write_remote(ch);
+
+	} else {
+		/*
+		 * There is no need to handle any further action. Either the
+		 * channel is already fully established, or we are waiting for
+		 * the remote end to catch up with our current state. Refer
+		 * to the diagram in "IVC State Transition Table" above.
+		 */
+	}
+
+	return tx_hdr->write.d.state == ivc_state_established;
+}
+
+bool tegra_ivc_channel_is_synchronized(struct tegra_ivc_channel *ch)
+{
+	struct tegra_ivc_channel_header *tx_hdr;
+	struct tegra_ivc_channel_header *rx_hdr;
+	int32_t peer_state;
+
+	if (ch == NULL)
+		return false;
+
+	tx_hdr = ch->write_header;
+	rx_hdr = ch->read_header;
+
+	tegra_ivc_invalidate_read_path_remote_header(ch);
+	peer_state = rx_hdr->write.d.state;
+
+	return peer_state == ivc_state_established &&
+		tx_hdr->write.d.state == ivc_state_established;
+}
+
+static void *tegra_ivc_frame_pointer(struct tegra_ivc_channel *ch,
+	struct tegra_ivc_channel_header *hdr, uint32_t frame)
+{
+	return (void *)(((char *)(hdr + 1)) + (ch->frame_size * frame));
+}
+
+static void *tegra_ivc_rx_get_raw_read_available(
+	struct tegra_ivc_channel *ch, unsigned *total, unsigned *wrapped)
+{
+	struct tegra_ivc_channel_header *hdr = ch->read_header;
+	uint32_t remote_write_count, avail;
+	void *buf = NULL;
+
+	tegra_ivc_invalidate_read_path_remote_header(ch);
+
+	remote_write_count = hdr->write.d.count;
+	/*
+	 * There is a control dependency from the read value of
+	 * remote_write_count to the calculation of avail to the decision by
+	 * the caller whether to read from a buffer at all. Hence, no barrier
+	 * is required here.
+	 */
+	avail = remote_write_count - ch->read_count;
+	*total = avail;
+	*wrapped = 0;
+
+	if (avail > 0) {
+		uint32_t index = ch->read_count % ch->nframes;
+
+		if ((index + avail) > ch->nframes) {
+			*wrapped = (index + avail) - ch->nframes;
+			avail = ch->nframes - index;
+		}
+
+		buf = tegra_ivc_frame_pointer(ch, hdr, index);
+		cache_invalidate(buf, avail * ch->frame_size);
+	}
+
+	return buf;
+}
+
+unsigned tegra_ivc_rx_get_read_available(struct tegra_ivc_channel *ch)
+{
+	struct tegra_ivc_channel_header *hdr = ch->read_header;
+	unsigned avail, wrap;
+
+	tegra_ivc_rx_get_raw_read_available(ch, &avail, &wrap);
+
+	if (wrap > 0)
+		cache_invalidate(hdr + 1, wrap * ch->frame_size);
+
+	return avail;
+}
+
+void *tegra_ivc_rx_get_read_frame(struct tegra_ivc_channel *ch, unsigned n)
+{
+	uint32_t idx = (ch->read_count + n) % ch->nframes;
+
+	return tegra_ivc_frame_pointer(ch, ch->read_header, idx);
+}
+
+int tegra_ivc_rx_get_contiguous_read_available(struct tegra_ivc_channel *ch,
+	const char **buffer_out, bool *non_contig_available)
+{
+	unsigned total, wrap;
+
+	*buffer_out = tegra_ivc_rx_get_raw_read_available(ch, &total, &wrap);
+	*non_contig_available = wrap > 0;
+	return total - wrap;
+}
+
+int tegra_ivc_rx_get_frames(struct tegra_ivc_channel *ch,
+	const char *buffers_out[], unsigned count)
+{
+	struct tegra_ivc_channel_header *hdr = ch->read_header;
+	uint32_t remote_write_count, count_available;
+	uint32_t read_index;
+	unsigned i;
+	char *buf;
+
+	tegra_ivc_invalidate_read_path_remote_header(ch);
+
+	remote_write_count = hdr->write.d.count;
+	/*
+	 * There is a control dependency from the read value of
+	 * remote_write_count to the calculation of count_available to the
+	 * decision by the caller whether to read from a buffer at all. Hence,
+	 * no barrier is required here.
+	 */
+	count_available = remote_write_count - ch->read_count;
+	if (count_available < count)
+		return 0;
+
+	read_index = ch->read_count % ch->nframes;
+
+	for (i = 0; i < count; i++) {
+		buf = tegra_ivc_frame_pointer(ch, hdr, read_index++);
+		cache_invalidate(buf, ch->frame_size);
+		buffers_out[i] = buf;
+		read_index %= ch->nframes;
+	}
+
+	return count_available;
+}
+
+int tegra_ivc_rx_notify_buffers_consumed(struct tegra_ivc_channel *ch,
+	int count)
+{
+	struct tegra_ivc_channel_header *hdr = ch->read_header;
+	uint32_t read_index;
+
+	read_index = ch->read_count % ch->nframes;
+	if ((read_index + count) > ch->nframes)
+		return -1;
+
+	/*
+	 * Ensure local reads/writes of/to the buffer complete before remote
+	 * CPU's fills
+	 */
+	barrier_memory_order();
+
+	ch->read_count += count;
+	hdr->read.d.count = ch->read_count;
+	tegra_ivc_clean_read_path_local_header(ch);
+
+	if (tegra_ivc_rx_get_read_available(ch) == ch->nframes - count)
+		return tegra_ivc_notify_read_remote(ch);
+	else
+		return 0;
+}
+
+static void *tegra_ivc_tx_get_raw_write_space(
+	struct tegra_ivc_channel *ch, unsigned *total, unsigned *wrapped)
+{
+	struct tegra_ivc_channel_header *hdr = ch->write_header;
+	uint32_t remote_read_count, avail;
+	void *buf = NULL;
+
+	tegra_ivc_invalidate_write_path_remote_header(ch);
+
+	remote_read_count = hdr->read.d.count;
+	/*
+	 * There is a control dependency from the read value of
+	 * remote_write_count to the calculation of avail to the decision by
+	 * the caller whether to read from a buffer at all. Hence, no barrier
+	 * is required here.
+	 */
+	avail = ch->nframes - (ch->write_count - remote_read_count);
+	*total = avail;
+	*wrapped = 0;
+
+	if (avail > 0) {
+		uint32_t index = ch->write_count % ch->nframes;
+
+		if ((index + avail) > ch->nframes)
+			*wrapped = (index + avail) - ch->nframes;
+
+		buf = tegra_ivc_frame_pointer(ch, hdr, index);
+	}
+
+	return buf;
+}
+
+unsigned tegra_ivc_tx_get_write_space(struct tegra_ivc_channel *ch)
+{
+	unsigned avail, wrap;
+
+	tegra_ivc_tx_get_raw_write_space(ch, &avail, &wrap);
+	return avail;
+}
+
+void *tegra_ivc_tx_get_write_buffer(struct tegra_ivc_channel *ch, unsigned n)
+{
+	uint32_t idx = (ch->write_count + n) % ch->nframes;
+
+	return tegra_ivc_frame_pointer(ch, ch->write_header, idx);
+}
+
+int tegra_ivc_tx_get_contiguous_write_space(struct tegra_ivc_channel *ch,
+	char **buffer_out, bool *non_contig_available)
+{
+	unsigned total, wrap;
+
+	*buffer_out = tegra_ivc_tx_get_raw_write_space(ch, &total, &wrap);
+	*non_contig_available = wrap > 0;
+	return total - wrap;
+}
+
+int tegra_ivc_tx_get_frames(struct tegra_ivc_channel *ch,
+		char *buffers_out[], unsigned count)
+{
+	struct tegra_ivc_channel_header *hdr = ch->write_header;
+	uint32_t remote_read_count, count_available;
+	uint32_t write_index;
+	unsigned i;
+
+	tegra_ivc_invalidate_write_path_remote_header(ch);
+
+	remote_read_count = hdr->read.d.count;
+	/*
+	 * There is a control dependency from the read value of
+	 * remote_read_count to the calculation of count_available to the
+	 * decision by the caller whether to write to a buffer at all. Hence,
+	 * no barrier is required here.
+	 */
+	count_available = ch->nframes - (ch->write_count - remote_read_count);
+	if (count_available < count)
+		return 0;
+
+	write_index = ch->write_count % ch->nframes;
+
+	for (i = 0; i < count; i++) {
+		buffers_out[i] = tegra_ivc_frame_pointer(ch, hdr, write_index++);
+		write_index %= ch->nframes;
+	}
+
+	return count_available;
+}
+
+int tegra_ivc_tx_send_buffers(struct tegra_ivc_channel *ch, int count)
+{
+	struct tegra_ivc_channel_header *hdr = ch->write_header;
+	uint32_t write_index;
+	char *write_buffer;
+
+	write_index = ch->write_count % ch->nframes;
+	if ((write_index + count) > ch->nframes)
+		return -1;
+
+	write_buffer = tegra_ivc_frame_pointer(ch, hdr, write_index);
+	cache_clean(write_buffer, count * ch->frame_size);
+
+	ch->write_count += count;
+	hdr->write.d.count = ch->write_count;
+	tegra_ivc_clean_write_path_local_header(ch);
+
+	if (tegra_ivc_tx_get_write_space(ch) == ch->nframes - count)
+		return tegra_ivc_notify_write_remote(ch);
+	else
+		return 0;
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/uart-tegra.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/uart-tegra.c
new file mode 100644
index 0000000..fec5262
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/platform/uart-tegra.c
@@ -0,0 +1,966 @@
+/*
+ * Copyright (c) 2019-2023 NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+
+/* Compiler headers */
+#include <stdbool.h>                         // for true
+#include <stdint.h>                          // for uint32_t
+#include <stddef.h>                          // for NULL
+
+/* local os headers */
+#include <osa/osa-task.h>
+#include <osa/osa-errors.h>
+
+/* Early FSP headers */
+#include <misc/ct-assert.h>                  // for CT_ASSERT
+#include <soc-common/hw-const.h>             /* Must appear before any hwinc files */
+
+/* Hardware headers */
+#include <aruart.h>                          // for UART_LCR_0_WD_SIZE_SHIFT
+#include <address_map_new.h>                 // NV_ADDRESS_MAP_...
+#include <arpadctl_AO.h>                     // PADCTL_AO_UART3_RX_0
+
+/* Late FSP headers */
+#include <chipid/chip-id.h>                  // tegra_platform_is_fpga...
+#include <clk/clk-tegra.h>                   // for tegra_clk_disable, tegra...
+#include <error/common-errors.h>             // for E_SUCCESS, error_t, FSP_...
+#include <misc/attributes.h>                 // for FSP__MISC__ATTRIBUTES_H
+#include <reg-access/reg-access.h>           // for readl, writel, FSP__REG_...
+#include <tke/tke-tegra.h>                   // for tegra_tke_ APIs
+#include <irq/safe-irqs.h>                   // for irq_safe_enable, irq_safe_disable...
+#include <delay/delay.h>                     // for get_time_ticks
+
+/* Module-specific FSP headers */
+#include <uart/sections-uart.h>              // Immune from CT_ASSERT protection
+#include <uart/uart.h>                       // for tegra_uart_conf,
+#include <uart/tegra-uart-priv.h>            // for tegra_uart_ctlr, tegra_u...
+#include <uart/uart-errors.h>                // for E_UART_ERR_CONFIG, ...
+
+/* local headers */
+#include <uart-tegra.h>                      // for tegra_uart_init, tegra_uart_..
+#include <uart-macros.h>                     // for SPE_UART_...
+
+/*
+ * Compile-time check for FSP header files
+ *   Each FSP header file contains a signature unique to that file, and the
+ *   FSP project.  The CT_ASSERT macro (contained in misc/ct-assert.h) can
+ *   check for this signature.  If it does not exist, then the build will
+ *   abort.
+ *
+ *   This is a trap for projects which have their own include files of the
+ *   same names, but different contents.  This trap ensures that only the
+ *   files from the FSP project, are built into the FSP source code.
+ */
+    CT_ASSERT(FSP__SOC_COMMON__HW_CONST_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__CLK__CLK_TEGRA_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__ERROR__COMMON_ERRORS_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__MISC__ATTRIBUTES_H, "Header file missing or invalid.")
+    CT_ASSERT(FSP__REG_ACCESS__REG_ACCESS_H, "Header file missing or invalid.")
+
+#define TEGRA_UART_LCR_DLAB             (UART_LCR_0_DLAB_ENABLE << \
+                                                UART_LCR_0_DLAB_SHIFT)
+#define TEGRA_UART_IER_THRE             (UART_IER_DLAB_0_0_IE_THR_ENABLE << \
+                                                UART_IER_DLAB_0_0_IE_THR_SHIFT)
+#define TEGRA_UART_LSR_RDY              (UART_LSR_0_RDR_DATA_IN_FIFO << \
+                                                UART_LSR_0_RDR_SHIFT)
+#define TEGRA_UART_LSR_TX_FIFO_FULL     (UART_LSR_0_TX_FIFO_FULL_FULL << \
+                                                UART_LSR_0_TX_FIFO_FULL_SHIFT)
+#define TEGRA_UART_LSR_THRE_EMPTY       (UART_LSR_0_THRE_EMPTY << \
+                                                UART_LSR_0_THRE_SHIFT)
+#define TEGRA_UART_LSR_TX_SHIFT_EMPTY   (UART_LSR_0_TMTY_EMPTY << \
+                                                UART_LSR_0_TMTY_SHIFT)
+#define TEGRA_UART_IIR_NO_INT           (UART_IIR_FCR_0_IS_STA_NO_INTR_PEND \
+                                                << UART_IIR_FCR_0_IS_STA_SHIFT)
+
+#define TEGRA_UART_IRQ_MASK             0x0FU
+#define TEGRA_UART_RX_TIMEOUT           0x0CU
+#define TEGRA_UART_RX_DATA_AVAILABLE    0x04U
+#define TEGRA_UART_THRE_EMPTY           0x02U
+#define TEGRA_UART_LINE_STS_ERR_INT     0x06U
+#define TEGRA_UART_MODEM_STS_INT        0x00U
+
+#define TEGRA_UART_BUF_SIZE          256
+
+static struct tegra_uart_conf uart_conf;
+
+static bool en_rx_irq = false;
+
+static inline uint32_t
+tegra_uart_readl(const struct tegra_uart_ctlr * const ctlr,
+                 uint32_t offset)
+{
+    return readl_base_offset(ctlr->id.base_addr, offset);
+}
+
+static inline void
+tegra_uart_writel(const struct tegra_uart_ctlr * const ctlr,
+                  uint32_t val,
+                  uint32_t offset)
+{
+        writel_base_offset(val, ctlr->id.base_addr, offset);
+}
+
+static inline void
+tegra_uart_putc(const struct tegra_uart_ctlr * const ctlr,
+                char c)
+{
+    uint32_t lsr;
+
+    do {
+        lsr = tegra_uart_readl(ctlr, UART_LSR_0);
+    } while ((lsr & TEGRA_UART_LSR_THRE_EMPTY) == 0UL);
+
+    tegra_uart_writel(ctlr, c, UART_THR_DLAB_0_0);
+}
+
+static inline char
+tegra_uart_getc(const struct tegra_uart_ctlr * const ctlr)
+{
+    while ((tegra_uart_readl(ctlr, UART_LSR_0) & TEGRA_UART_LSR_RDY) == 0U);
+
+    return tegra_uart_readl(ctlr, UART_THR_DLAB_0_0);
+}
+
+SECTION_UART_TEXT error_t
+tegra_uart_flush_tx_hw_fifo(const struct tegra_uart_ctlr * const ctlr)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (!ctlr->initialized) {
+        ret = E_UART_NO_INIT;
+        goto out;
+    }
+
+    while ((tegra_uart_readl(ctlr, UART_LSR_0) &
+                   TEGRA_UART_LSR_TX_SHIFT_EMPTY) == 0UL);
+
+out:
+    return ret;
+}
+
+SECTION_UART_TEXT error_t
+tegra_uart_write_now(const struct tegra_uart_ctlr * const ctlr,
+                     const char *buf,
+                     uint32_t count)
+{
+    error_t     ret = E_SUCCESS;
+    uint32_t    i;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (buf == NULL) {
+        ret = E_UART_INVALID_PARAM;
+        goto out;
+    }
+
+    if (!ctlr->initialized) {
+        ret = E_UART_NO_INIT;
+        goto out;
+    }
+
+    for (i = 0U; i < count; i += 1U) {
+        tegra_uart_putc(ctlr, *buf++);
+    }
+
+out:
+    return ret;
+}
+
+SECTION_UART_TEXT error_t
+tegra_uart_write_char(const struct tegra_uart_ctlr * const ctlr,
+                      const char c)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (!ctlr->initialized) {
+        ret = E_UART_NO_INIT;
+        goto out;
+    }
+
+    tegra_uart_putc(ctlr, c);
+
+out:
+    return ret;
+}
+
+SECTION_UART_TEXT error_t
+tegra_uart_write_string(const struct tegra_uart_ctlr * const ctlr,
+                        const char *buf)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (buf == NULL) {
+        ret = E_UART_INVALID_PARAM;
+        goto out;
+    }
+
+    if (!ctlr->initialized) {
+        ret = E_UART_NO_INIT;
+        goto out;
+    }
+
+    while (*buf != '\0') {
+        tegra_uart_putc(ctlr, *buf++);
+    }
+
+out:
+    return ret;
+}
+
+static inline rtosTick
+tegra_uart_get_elapsed_ticks(uint64_t tstart, uint64_t timeout)
+{
+    uint64_t tcurr = get_time_ticks();
+
+    if (timeout >= rtosMAX_DELAY) {
+        return rtosMAX_DELAY;
+    } else if ((tcurr - tstart) >= timeout) {
+        return 0;
+    } else {
+        return tegra_tke_convert_usecs_to_ticks(timeout - (tcurr - tstart));
+    }
+}
+
+static error_t
+tegra_uart_disable_thre_interrupt(const struct tegra_uart_ctlr *ctlr)
+{
+    uint32_t ier;
+    error_t ret;
+
+    ret = irq_safe_disable(ctlr->id.irq);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+    ier = tegra_uart_readl(ctlr, UART_IER_DLAB_0_0);
+    if ((ier & TEGRA_UART_IER_THRE) != 0UL) {
+        tegra_uart_writel(ctlr,
+                         ier & ~TEGRA_UART_IER_THRE,
+                         UART_IER_DLAB_0_0);
+    }
+    ret = irq_safe_enable(ctlr->id.irq);
+
+out:
+    return ret;
+}
+
+static error_t
+tegra_uart_enable_thre_interrupt(const struct tegra_uart_ctlr *ctlr)
+{
+    uint32_t ier;
+    error_t ret;
+
+    ret = irq_safe_disable(ctlr->id.irq);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+    ier = tegra_uart_readl(ctlr, UART_IER_DLAB_0_0);
+    if ((ier & TEGRA_UART_IER_THRE) == 0UL) {
+        tegra_uart_writel(ctlr,
+                         ier | TEGRA_UART_IER_THRE,
+                         UART_IER_DLAB_0_0);
+    }
+    ret = irq_safe_enable(ctlr->id.irq);
+
+out:
+    return ret;
+}
+
+static error_t
+tegra_uart_disable_rx_interrupt(const struct tegra_uart_ctlr *ctlr)
+{
+    uint32_t ier;
+    error_t ret;
+
+    ret = irq_safe_disable(ctlr->id.irq);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+    ier = tegra_uart_readl(ctlr, UART_IER_DLAB_0_0);
+    /* clear RX Interrupts */
+    ier &= ~((UART_IER_DLAB_0_0_IE_RHR_ENABLE << UART_IER_DLAB_0_0_IE_RHR_SHIFT) |
+             (UART_IER_DLAB_0_0_IE_RXS_ENABLE << UART_IER_DLAB_0_0_IE_RXS_SHIFT) |
+             (UART_IER_DLAB_0_0_IE_RX_TIMEOUT_ENABLE <<
+                                   UART_IER_DLAB_0_0_IE_RX_TIMEOUT_SHIFT));
+    tegra_uart_writel(ctlr, ier, UART_IER_DLAB_0_0);
+    en_rx_irq = false;
+    ret = irq_safe_enable(ctlr->id.irq);
+
+out:
+    return ret;
+}
+
+static error_t
+tegra_uart_enable_rx_interrupt(const struct tegra_uart_ctlr *ctlr)
+{
+    uint32_t ier;
+    error_t  ret;
+
+    ret = irq_safe_disable(ctlr->id.irq);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+    ier = tegra_uart_readl(ctlr, UART_IER_DLAB_0_0);
+    /* Enable RX Interrupts */
+    ier |= (UART_IER_DLAB_0_0_IE_RHR_ENABLE << UART_IER_DLAB_0_0_IE_RHR_SHIFT) |
+           (UART_IER_DLAB_0_0_IE_RXS_ENABLE << UART_IER_DLAB_0_0_IE_RXS_SHIFT) |
+           (UART_IER_DLAB_0_0_IE_RX_TIMEOUT_ENABLE <<
+                                   UART_IER_DLAB_0_0_IE_RX_TIMEOUT_SHIFT);
+    tegra_uart_writel(ctlr, ier, UART_IER_DLAB_0_0);
+    en_rx_irq = true;
+    ret = irq_safe_enable(ctlr->id.irq);
+
+out:
+    return ret;
+}
+
+SECTION_UART_TEXT error_t
+tegra_uart_write(const struct tegra_uart_ctlr * const ctlr,
+                 const char *buf,
+                 uint32_t count,
+                 uint32_t *written,
+                 uint64_t timeout)
+{
+    uint64_t    tstart;
+    rtosTick    timeout_left = 0;
+    uint32_t    write_cnt = 0UL;
+    error_t     status;
+    error_t     ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (buf == NULL || written == NULL) {
+        ret = E_UART_INVALID_PARAM;
+        goto out;
+    }
+
+    if (count == 0UL) {
+        goto out;
+    }
+
+    tstart = get_time_ticks();
+
+    for (write_cnt = 0UL; write_cnt < count; write_cnt++) {
+        status = rtosQueueSend(ctlr->tx_queue, buf, 0);
+        if (status == E_RTOS_QUEUE_FULL) {
+            ret = tegra_uart_enable_thre_interrupt(ctlr);
+            if (ret != E_SUCCESS) {
+               goto out;
+            }
+            timeout_left = tegra_uart_get_elapsed_ticks(tstart, timeout);
+            status = rtosQueueSend(ctlr->tx_queue, buf, timeout_left);
+            if (status != rtosPASS) {
+                break;
+            }
+        }
+        buf++;
+    }
+
+    if (write_cnt != 0UL) {
+        ret = tegra_uart_enable_thre_interrupt(ctlr);
+    }
+
+out:
+    *written = write_cnt;
+    return ret;
+}
+
+SECTION_UART_TEXT error_t
+tegra_uart_flush_tx_fifo(const struct tegra_uart_ctlr * const ctlr)
+{
+    error_t ret = E_SUCCESS;
+    error_t status;
+    char    c;
+
+
+    ret = tegra_uart_disable_thre_interrupt(ctlr);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+    while (1) {
+        status = rtosQueueReceive(ctlr->tx_queue, &c, 0);
+        if (status != rtosPASS) {
+            ret = E_UART_FLUSH_TX_FIFO_FAIL;
+            break;
+        }
+        tegra_uart_putc(ctlr, c);
+    }
+
+out:
+    return ret;
+}
+
+
+SECTION_UART_TEXT error_t
+tegra_uart_read_char(const struct tegra_uart_ctlr * const ctlr,
+                     char *c)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (c == NULL) {
+        ret = E_UART_INVALID_PARAM;
+        goto out;
+    }
+
+    if (!ctlr->initialized) {
+        ret = E_UART_NO_INIT;
+        goto out;
+    }
+
+    *c = tegra_uart_getc(ctlr);
+
+out:
+    return ret;
+}
+
+SECTION_UART_TEXT error_t
+tegra_uart_read(const struct tegra_uart_ctlr * const ctlr,
+                char *buf,
+                uint32_t count,
+                uint32_t *read,
+                uint64_t timeout)
+{
+    error_t     ret = E_SUCCESS;
+    uint64_t    tstart;
+    rtosTick    timeout_left = 0;
+    uint32_t    read_cnt;
+    error_t     status;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (buf == NULL) {
+        ret = E_UART_INVALID_PARAM;
+        goto out;
+    }
+
+    if (!en_rx_irq) {
+        ret = tegra_uart_enable_rx_interrupt(ctlr);
+    }
+
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+    timeout_left = tegra_tke_convert_usecs_to_ticks(timeout);
+    tstart = get_time_ticks();
+
+    for (read_cnt = 0UL; read_cnt < count; read_cnt += 1UL) {
+        status = rtosQueueReceive(ctlr->rx_queue,
+                                    buf,
+                                    timeout_left);
+        if (status != rtosPASS) {
+            ret = status;
+            break;
+        }
+        buf++;
+        timeout_left = tegra_uart_get_elapsed_ticks(tstart, timeout);
+    }
+    *read = read_cnt;
+
+out:
+    return ret;
+}
+
+SECTION_UART_TEXT static void
+tegra_uart_irq_handler(void *data)
+{
+    const struct tegra_uart_ctlr *ctlr = (const struct tegra_uart_ctlr *)data;
+    uint32_t  iir, ier;
+    uint32_t  lsr;
+    char      c_in, c_out;
+    rtosBool higher_prio_task_woken = rtosFALSE;
+    error_t   status;
+
+    while (1) {
+        iir = tegra_uart_readl(ctlr, UART_IIR_FCR_0) & TEGRA_UART_IRQ_MASK;
+        if (iir & TEGRA_UART_IIR_NO_INT) {
+            break;
+        }
+
+        switch (iir) {
+            case TEGRA_UART_LINE_STS_ERR_INT:
+                tegra_uart_readl(ctlr, UART_LSR_0);
+                break;
+            case TEGRA_UART_RX_TIMEOUT:
+            case TEGRA_UART_RX_DATA_AVAILABLE:
+                do {
+                    c_in = tegra_uart_readl(ctlr, UART_THR_DLAB_0_0) & 0xFFU;
+                    status = rtosQueueSendFromISR(ctlr->rx_queue,
+                                                      &c_in,
+                                                      &higher_prio_task_woken);
+                    if (status != rtosPASS) {
+                        break;
+                    }
+                    lsr = tegra_uart_readl(ctlr, UART_LSR_0);
+                } while ((lsr & TEGRA_UART_LSR_RDY) != 0UL);
+                break;
+            case TEGRA_UART_THRE_EMPTY:
+                do {
+                    status = rtosQueueReceiveFromISR(ctlr->tx_queue,
+                                                         &c_out,
+                                                         &higher_prio_task_woken);
+                    if (status != rtosPASS) {
+                        ier = tegra_uart_readl(ctlr, UART_IER_DLAB_0_0);
+                        tegra_uart_writel(ctlr,
+                                          ier & ~TEGRA_UART_IER_THRE,
+                                          UART_IER_DLAB_0_0);
+                        break;
+                    }
+                    tegra_uart_writel(ctlr, c_out, UART_THR_DLAB_0_0);
+                    lsr = tegra_uart_readl(ctlr, UART_LSR_0);
+                } while ((lsr & TEGRA_UART_LSR_THRE_EMPTY) != 0UL);
+                break;
+            case TEGRA_UART_MODEM_STS_INT:
+                tegra_uart_readl(ctlr, UART_MSR_0);
+                break;
+        }
+    }
+
+   rtosTaskYieldFromISR(higher_prio_task_woken);
+}
+
+static inline void
+tegra_uart_configure_fifo_ctlr(const struct tegra_uart_ctlr * const ctlr)
+{
+    uint32_t fcr;
+
+    fcr = (UART_IIR_FCR_0_FCR_EN_FIFO_ENABLE <<
+                UART_IIR_FCR_0_FCR_EN_FIFO_SHIFT);
+    fcr |= (UART_IIR_FCR_0_RX_CLR_CLEAR <<
+                UART_IIR_FCR_0_RX_CLR_SHIFT);
+    fcr |= (UART_IIR_FCR_0_TX_CLR_CLEAR <<
+                UART_IIR_FCR_0_TX_CLR_SHIFT);
+    fcr |= (UART_IIR_FCR_0_RX_TRIG_FIFO_COUNT_GREATER_8 <<
+                UART_IIR_FCR_0_RX_TRIG_SHIFT);
+    fcr |= (UART_IIR_FCR_0_TX_TRIG_FIFO_COUNT_GREATER_4 <<
+                UART_IIR_FCR_0_TX_TRIG_SHIFT);
+
+    tegra_uart_writel(ctlr, fcr, UART_IIR_FCR_0);
+}
+
+static inline error_t
+tegra_uart_get_parity_mode(const struct tegra_uart_ctlr * const ctlr,
+                           uint32_t parity_conf,
+                           uint32_t *parity)
+{
+    error_t ret = E_SUCCESS;
+
+    switch (parity_conf) {
+    case TEGRA_UART_NO_PARITY:
+        *parity = (UART_LCR_0_PAR_NO_PARITY << UART_LCR_0_PAR_SHIFT);
+        break;
+    case TEGRA_UART_ODD_PARITY:
+        *parity = (UART_LCR_0_EVEN_DISABLE << UART_LCR_0_EVEN_SHIFT) |
+                     (UART_LCR_0_PAR_PARITY << UART_LCR_0_PAR_SHIFT);
+        break;
+    case TEGRA_UART_EVEN_PARITY:
+        *parity = (UART_LCR_0_EVEN_ENABLE << UART_LCR_0_EVEN_SHIFT) |
+                     (UART_LCR_0_PAR_PARITY << UART_LCR_0_PAR_SHIFT);
+        break;
+    default:
+        ret = E_UART_ERR_CONFIG;
+        goto out;
+    }
+
+out:
+    return ret;
+}
+
+static inline error_t
+tegra_uart_get_data_frame_len(const struct tegra_uart_ctlr * const ctlr,
+                              uint32_t data_conf,
+                              uint32_t *data_bits)
+{
+    error_t ret = E_SUCCESS;
+
+    switch (data_conf) {
+    case TEGRA_UART_DATA_BITS_5:
+        *data_bits = (UART_LCR_0_WD_SIZE_WORD_LENGTH_5 <<
+                       UART_LCR_0_WD_SIZE_SHIFT);
+        break;
+    case TEGRA_UART_DATA_BITS_6:
+        *data_bits = (UART_LCR_0_WD_SIZE_WORD_LENGTH_6 <<
+                       UART_LCR_0_WD_SIZE_SHIFT);
+        break;
+    case TEGRA_UART_DATA_BITS_7:
+        *data_bits = (UART_LCR_0_WD_SIZE_WORD_LENGTH_7 <<
+                       UART_LCR_0_WD_SIZE_SHIFT);
+        break;
+    case TEGRA_UART_DATA_BITS_8:
+        *data_bits = (UART_LCR_0_WD_SIZE_WORD_LENGTH_8 <<
+                       UART_LCR_0_WD_SIZE_SHIFT);
+        break;
+    default:
+        ret = E_UART_ERR_CONFIG;
+        goto out;
+    }
+
+out:
+    return ret;
+}
+
+static inline error_t
+tegra_uart_get_stop_bits_len(const struct tegra_uart_ctlr * const ctlr,
+                             uint32_t stop_conf,
+                             uint32_t *stop_bits)
+{
+    error_t ret = E_SUCCESS;
+
+    switch (stop_conf) {
+    case TEGRA_UART_STOP_BITS_1:
+        *stop_bits = 0x0UL;
+        break;
+    case TEGRA_UART_STOP_BITS_2:
+        *stop_bits = (UART_LCR_0_STOP_ENABLE << UART_LCR_0_STOP_SHIFT);
+        break;
+    default:
+        ret = E_UART_ERR_CONFIG;
+        goto out;
+    }
+
+out:
+    return ret;
+}
+
+static void
+tegra_uart_baud_config(struct tegra_uart_ctlr * const ctlr,
+                       const uint32_t baud_divisor)
+{
+    /*
+     * program the baud rate divisor using DLL/DLM registers
+     * THR, RBR and DLL share the same address space.
+     * IER, DLM share the same address space.
+     * DLx registers are slected based on LCR.DLAB bit
+     */
+    tegra_uart_writel(ctlr, baud_divisor & 0xFFU, UART_THR_DLAB_0_0);
+    tegra_uart_writel(ctlr, ((baud_divisor >> 8) & 0xFFU), UART_IER_DLAB_0_0);
+}
+
+static void
+tegra_uart_pinmux_config(struct tegra_uart_ctlr * const ctlr)
+{
+    UNUSED(ctlr);
+
+	writel(0x440U, NV_ADDRESS_MAP_PADCTL_A14_BASE + PADCTL_AO_UART3_RX_0);
+	writel(0x440U, NV_ADDRESS_MAP_PADCTL_A14_BASE + PADCTL_AO_UART3_TX_0);
+}
+
+static void
+tegra_uart_clk_config(struct tegra_uart_ctlr * const ctlr)
+{
+    UNUSED(ctlr);
+
+    /*
+     * Source UARTC from OSC, which is 38.4 MHz except on FPGA,
+     * where it is 19.2 MHz.
+     */
+    if (tegra_platform_is_fpga()) {
+        /**
+         * Target baud rate = 115200
+         * Baud clock needed = 1.8432MHz
+         * OSC = 19.2MHz
+         * Value of divisor = 10.5 (smallest error)
+         * Divisor setting = (divisor - 1) * 2 = 19
+         */
+        SPE_UART_ENABLE(UARTC, OSC_UNDIV, ENABLE, 19U);
+    } else {
+        /**
+         * Target baud rate = 115200
+         * Baud clock needed = 1.8432MHz
+         * OSC = 38.4MHz
+         * Value of divisor = 21 (smallest error)
+         * Divisor setting = (divisor - 1) * 2 = 40
+         */
+        SPE_UART_ENABLE(UARTC, OSC_UNDIV, ENABLE, 40U);
+    }
+}
+
+SECTION_UART_INIT_TEXT static error_t
+tegra_uart_config(struct tegra_uart_ctlr * const ctlr,
+                  const struct tegra_uart_conf * const conf)
+{
+    error_t   ret = E_SUCCESS;
+    uint32_t  divisor = 0x1UL;
+    uint32_t  parity;
+    uint32_t  data_bits = 0UL;
+    uint32_t  stop_bits = 0UL;
+    uint32_t  comm_param;
+
+    /* sanity check the controller pointer */
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    /* sanity check for invalid conf parameter */
+    if (conf == NULL) {
+        ret = E_UART_INVALID_PARAM;
+        goto out;
+    }
+
+    if (!tegra_platform_is_silicon()) {
+        /* program the pinmux settings */
+        tegra_uart_pinmux_config(ctlr);
+    }
+
+    /* configure the uart clock */
+    tegra_uart_clk_config(ctlr);
+
+    /* configure the FIFO control register */
+    tegra_uart_configure_fifo_ctlr(ctlr);
+
+    /* generate the parity mode based on input configuration */
+    ret = tegra_uart_get_parity_mode(ctlr, conf->parity, &parity);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    /* fetch the data frame length in bits */
+    ret = tegra_uart_get_data_frame_len(ctlr, conf->data_bits, &data_bits);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    /* fetch the stop bits length */
+    ret = tegra_uart_get_stop_bits_len(ctlr, conf->stop_bits, &stop_bits);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    /* reset the data line attributes by clearing line control register */
+    tegra_uart_writel(ctlr, 0x0, UART_LCR_0);
+
+    /* clear all the interrupts */
+    tegra_uart_writel(ctlr, 0x0, UART_IER_DLAB_0_0);
+
+    /*
+     * configure the data line attributes - data bits, stop bits and parity
+     * also set the divisor latch access bit to program the divisor in the next
+     * step.
+     */
+    comm_param = parity | data_bits | stop_bits | TEGRA_UART_LCR_DLAB,
+    tegra_uart_writel(ctlr, comm_param, UART_LCR_0);
+
+    /* configure the baud rate divisor */
+    tegra_uart_baud_config(ctlr, divisor);
+
+    /* clear the LCR.DLAB to switch to the THR and IER address space */
+    tegra_uart_writel(ctlr, comm_param & ~TEGRA_UART_LCR_DLAB, UART_LCR_0);
+
+    /* dummy read to ensure write is posted */
+    tegra_uart_readl(ctlr, UART_SPR_0);
+
+out:
+    return ret;
+}
+
+SECTION_UART_INIT_TEXT static error_t
+tegra_uart_init_hw(struct tegra_uart_ctlr * const ctlr,
+                   const struct tegra_uart_conf * const conf)
+{
+    error_t   ret = E_SUCCESS;
+
+    ret = tegra_uart_config(ctlr, conf);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    /* register irq handler and enable irq */
+    ret = irq_safe_set_handler(ctlr->id.irq, tegra_uart_irq_handler, ctlr);
+    if (ret == E_SUCCESS) {
+        ret = irq_safe_enable(ctlr->id.irq);
+    }
+
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+    /* indicate the controller is initialized */
+    ctlr->initialized = true;
+
+out:
+    return ret;
+}
+
+static bool is_uart_c_configured(void)
+{
+    bool is_clk_enabled = SPE_UART_IS_CLK_ENABLED(UARTC);
+    bool is_reset_deasserted = SPE_UART_IS_RESET_DEASSERTED(UARTC);
+
+    return (is_clk_enabled && is_reset_deasserted);
+}
+
+SECTION_UART_INIT_TEXT error_t
+tegra_uart_3rdparty_init(struct tegra_uart_ctlr *ctlr,
+                         const struct tegra_uart_conf * const conf)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (conf == NULL) {
+        ret = E_UART_INVALID_PARAM;
+        goto out;
+    }
+
+    /*
+     * If SPE ends up booting first without TCU, do the minimum
+     * required for configuring the UART before BPMP takes over.
+     */
+    if (!is_uart_c_configured()) {
+        ret = tegra_uart_config(ctlr, conf);
+        if (ret != E_SUCCESS) {
+            goto out;
+        }
+    }
+
+    /* indicate the controller is initialized */
+    ctlr->initialized = true;
+
+out:
+    return ret;
+}
+
+SECTION_UART_INIT_TEXT error_t
+tegra_uart_init(struct tegra_uart_ctlr *ctlr,
+                const struct tegra_uart_conf * const conf)
+{
+    error_t     ret = E_SUCCESS;
+    error_t     status;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (conf == NULL) {
+        ret = E_UART_INVALID_PARAM;
+        goto out;
+    }
+    uart_conf.parity    =  conf->parity;
+    uart_conf.stop_bits =  conf->stop_bits;
+    uart_conf.data_bits =  conf->data_bits;
+    uart_conf.baud      =  conf->baud;
+
+    status = rtosQueueCreate(NULL,
+                             0,
+                             TEGRA_UART_BUF_SIZE,
+                             sizeof(char),
+                             &ctlr->tx_queue);
+    if (status != rtosPASS) {
+        ret = E_UART_INIT_FAIL;
+        goto out;
+    }
+
+    status = rtosQueueCreate(NULL,
+                             0,
+                             TEGRA_UART_BUF_SIZE,
+                             sizeof(char),
+                             &ctlr->rx_queue);
+    if (status != rtosPASS) {
+        ret = E_UART_INIT_FAIL;
+        goto out;
+    }
+
+    ret = tegra_uart_init_hw(ctlr, conf);
+
+out:
+    return ret;
+}
+
+SECTION_UART_TEXT error_t
+tegra_uart_suspend(struct tegra_uart_ctlr *ctlr)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    if (!ctlr->initialized) {
+        ret = E_UART_NO_INIT;
+        goto out;
+    }
+
+    ret = tegra_uart_disable_rx_interrupt(ctlr);
+
+out:
+    return ret;
+}
+
+SECTION_UART_TEXT error_t
+tegra_uart_resume(struct tegra_uart_ctlr *ctlr)
+{
+    error_t ret = E_SUCCESS;
+
+    if (ctlr == NULL) {
+        ret = E_UART_NULL_PTR;
+        goto out;
+    }
+
+    ret = tegra_uart_init_hw(ctlr, &uart_conf);
+    if (ret != E_SUCCESS) {
+        goto out;
+    }
+
+    if (!en_rx_irq) {
+        ret = tegra_uart_enable_rx_interrupt(ctlr);
+    }
+
+out:
+    return ret;
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/config/config.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/config/config.h
new file mode 100644
index 0000000..f869f06
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/config/config.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __CONFIG_T23X_H
+#define __CONFIG_T23X_H
+
+#include <processor/tke-tegra-hw.h>
+
+/* Source configuration */
+
+#define PM_USE_HW_SEQUENCER_FOR_PLLAON	1
+#define TIMER_CLK_SRC	TEGRA_TKE_CLK_SRC_USECCNT
+
+#define SCRATCH_SCRATCH_COMB	0xc3903e4 /* SCRATCH + SCRATCH_SCRATCH_14_COMB */
+#define SCRATCH_MAGIC_MASK_COMB	0xffff0000
+#define SCRATCH_MAGIC_VAL_COMB	0x1c1c0000
+#define SCRATCH_UART_MASK_COMB	0x0000ffff
+
+/* Source configuration ends */
+
+/* SoC and App specific includes */
+
+/* includes end */
+
+#define I2C_AON_BUS_NUM		8
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/address_map_new.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/address_map_new.h
new file mode 100644
index 0000000..a8d1efd
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/address_map_new.h
@@ -0,0 +1,13838 @@
+//
+// Copyright (c) 2022 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ADDRESS_MAP_NEW_H_INC
+#define ADDRESS_MAP_NEW_H_INC
+
+#define NV_ADDRESS_MAP_SYSTEM_AMAP_BASE 0x00000000
+#define NV_ADDRESS_MAP_SYSTEM_AMAP_LIMIT 0xffffffffff
+#define NV_ADDRESS_MAP_SYSTEM_AMAP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SYSTEM_AMAP_HEADER no_headers
+
+#define NV_ADDRESS_MAP_LOVEC_BASE 0x00000000
+#define NV_ADDRESS_MAP_LOVEC_LIMIT 0x0000ffff
+#define NV_ADDRESS_MAP_LOVEC_ADDR_LOCALITY CCPLEX
+#define NV_ADDRESS_MAP_LOVEC_HEADER no_headers
+
+#define NV_ADDRESS_MAP_MISC_BASE 0x00100000
+#define NV_ADDRESS_MAP_MISC_LIMIT 0x0017ffff
+#define NV_ADDRESS_MAP_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MISC_HEADER armiscreg.h;armiscreg_scr.h
+
+#define NV_ADDRESS_MAP_GBEUPHY_PLL0_BASE 0x01000000
+#define NV_ADDRESS_MAP_GBEUPHY_PLL0_LIMIT 0x01001fff
+#define NV_ADDRESS_MAP_GBEUPHY_PLL0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GBEUPHY_PLL0_HEADER aruphy_pll.h
+
+#define NV_ADDRESS_MAP_GBEUPHY_LANE0_BASE 0x01002000
+#define NV_ADDRESS_MAP_GBEUPHY_LANE0_LIMIT 0x01002fff
+#define NV_ADDRESS_MAP_GBEUPHY_LANE0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GBEUPHY_LANE0_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_GBEUPHY_LANE1_BASE 0x01003000
+#define NV_ADDRESS_MAP_GBEUPHY_LANE1_LIMIT 0x01003fff
+#define NV_ADDRESS_MAP_GBEUPHY_LANE1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GBEUPHY_LANE1_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_GBEUPHY_LANE2_BASE 0x01004000
+#define NV_ADDRESS_MAP_GBEUPHY_LANE2_LIMIT 0x01004fff
+#define NV_ADDRESS_MAP_GBEUPHY_LANE2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GBEUPHY_LANE2_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_GBEUPHY_LANE3_BASE 0x01005000
+#define NV_ADDRESS_MAP_GBEUPHY_LANE3_LIMIT 0x01005fff
+#define NV_ADDRESS_MAP_GBEUPHY_LANE3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GBEUPHY_LANE3_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_GBEUPHY_PLL1_BASE 0x01006000
+#define NV_ADDRESS_MAP_GBEUPHY_PLL1_LIMIT 0x01007fff
+#define NV_ADDRESS_MAP_GBEUPHY_PLL1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GBEUPHY_PLL1_HEADER aruphy_pll.h
+
+#define NV_ADDRESS_MAP_GBEUPHY_LANE4_BASE 0x01008000
+#define NV_ADDRESS_MAP_GBEUPHY_LANE4_LIMIT 0x01008fff
+#define NV_ADDRESS_MAP_GBEUPHY_LANE4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GBEUPHY_LANE4_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_GBEUPHY_LANE5_BASE 0x01009000
+#define NV_ADDRESS_MAP_GBEUPHY_LANE5_LIMIT 0x01009fff
+#define NV_ADDRESS_MAP_GBEUPHY_LANE5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GBEUPHY_LANE5_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_GBEUPHY_LANE6_BASE 0x0100a000
+#define NV_ADDRESS_MAP_GBEUPHY_LANE6_LIMIT 0x0100afff
+#define NV_ADDRESS_MAP_GBEUPHY_LANE6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GBEUPHY_LANE6_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_GBEUPHY_LANE7_BASE 0x0100b000
+#define NV_ADDRESS_MAP_GBEUPHY_LANE7_LIMIT 0x0100bfff
+#define NV_ADDRESS_MAP_GBEUPHY_LANE7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GBEUPHY_LANE7_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_GBEUPHY_PLL2_BASE 0x0100c000
+#define NV_ADDRESS_MAP_GBEUPHY_PLL2_LIMIT 0x0100dfff
+#define NV_ADDRESS_MAP_GBEUPHY_PLL2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GBEUPHY_PLL2_HEADER aruphy_pll.h
+
+#define NV_ADDRESS_MAP_TOP2_HSP_COMMON_BASE 0x01600000
+#define NV_ADDRESS_MAP_TOP2_HSP_COMMON_LIMIT 0x0160ffff
+#define NV_ADDRESS_MAP_TOP2_HSP_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP2_HSP_COMMON_HEADER arhsp_int.h;arhsp_int_scr.h
+
+#define NV_ADDRESS_MAP_TOP2_HSP_SM_0_1_BASE 0x01610000
+#define NV_ADDRESS_MAP_TOP2_HSP_SM_0_1_LIMIT 0x0161ffff
+#define NV_ADDRESS_MAP_TOP2_HSP_SM_0_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP2_HSP_SM_0_1_HEADER
+
+#define NV_ADDRESS_MAP_TOP2_HSP_SM_2_3_BASE 0x01620000
+#define NV_ADDRESS_MAP_TOP2_HSP_SM_2_3_LIMIT 0x0162ffff
+#define NV_ADDRESS_MAP_TOP2_HSP_SM_2_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP2_HSP_SM_2_3_HEADER
+
+#define NV_ADDRESS_MAP_TOP2_HSP_SM_4_5_BASE 0x01630000
+#define NV_ADDRESS_MAP_TOP2_HSP_SM_4_5_LIMIT 0x0163ffff
+#define NV_ADDRESS_MAP_TOP2_HSP_SM_4_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP2_HSP_SM_4_5_HEADER
+
+#define NV_ADDRESS_MAP_TOP2_HSP_SM_6_7_BASE 0x01640000
+#define NV_ADDRESS_MAP_TOP2_HSP_SM_6_7_LIMIT 0x0164ffff
+#define NV_ADDRESS_MAP_TOP2_HSP_SM_6_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP2_HSP_SM_6_7_HEADER
+
+#define NV_ADDRESS_MAP_TOP2_HSP_SS_0_BASE 0x01650000
+#define NV_ADDRESS_MAP_TOP2_HSP_SS_0_LIMIT 0x0165ffff
+#define NV_ADDRESS_MAP_TOP2_HSP_SS_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP2_HSP_SS_0_HEADER
+
+#define NV_ADDRESS_MAP_TOP2_HSP_SS_1_BASE 0x01660000
+#define NV_ADDRESS_MAP_TOP2_HSP_SS_1_LIMIT 0x0166ffff
+#define NV_ADDRESS_MAP_TOP2_HSP_SS_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP2_HSP_SS_1_HEADER
+
+#define NV_ADDRESS_MAP_TOP2_HSP_SS_2_BASE 0x01670000
+#define NV_ADDRESS_MAP_TOP2_HSP_SS_2_LIMIT 0x0167ffff
+#define NV_ADDRESS_MAP_TOP2_HSP_SS_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP2_HSP_SS_2_HEADER
+
+#define NV_ADDRESS_MAP_TOP2_HSP_SS_3_BASE 0x01680000
+#define NV_ADDRESS_MAP_TOP2_HSP_SS_3_LIMIT 0x0168ffff
+#define NV_ADDRESS_MAP_TOP2_HSP_SS_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP2_HSP_SS_3_HEADER
+
+#define NV_ADDRESS_MAP_MC8_BASE 0x01700000
+#define NV_ADDRESS_MAP_MC8_LIMIT 0x0170ffff
+#define NV_ADDRESS_MAP_MC8_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MC8_HEADER armc.h;armc_scr.h
+
+#define NV_ADDRESS_MAP_MC9_BASE 0x01710000
+#define NV_ADDRESS_MAP_MC9_LIMIT 0x0171ffff
+#define NV_ADDRESS_MAP_MC9_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MC9_HEADER armc.h;armc_scr.h
+
+#define NV_ADDRESS_MAP_MC10_BASE 0x01720000
+#define NV_ADDRESS_MAP_MC10_LIMIT 0x0172ffff
+#define NV_ADDRESS_MAP_MC10_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MC10_HEADER armc.h;armc_scr.h
+
+#define NV_ADDRESS_MAP_MC11_BASE 0x01730000
+#define NV_ADDRESS_MAP_MC11_LIMIT 0x0173ffff
+#define NV_ADDRESS_MAP_MC11_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MC11_HEADER armc.h;armc_scr.h
+
+#define NV_ADDRESS_MAP_MC12_BASE 0x01740000
+#define NV_ADDRESS_MAP_MC12_LIMIT 0x0174ffff
+#define NV_ADDRESS_MAP_MC12_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MC12_HEADER armc.h;armc_scr.h
+
+#define NV_ADDRESS_MAP_MC13_BASE 0x01750000
+#define NV_ADDRESS_MAP_MC13_LIMIT 0x0175ffff
+#define NV_ADDRESS_MAP_MC13_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MC13_HEADER armc.h;armc_scr.h
+
+#define NV_ADDRESS_MAP_MC14_BASE 0x01760000
+#define NV_ADDRESS_MAP_MC14_LIMIT 0x0176ffff
+#define NV_ADDRESS_MAP_MC14_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MC14_HEADER armc.h;armc_scr.h
+
+#define NV_ADDRESS_MAP_MC15_BASE 0x01770000
+#define NV_ADDRESS_MAP_MC15_LIMIT 0x0177ffff
+#define NV_ADDRESS_MAP_MC15_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MC15_HEADER armc.h;armc_scr.h
+
+#define NV_ADDRESS_MAP_EMC8_CORE_BASE 0x01780000
+#define NV_ADDRESS_MAP_EMC8_CORE_LIMIT 0x01780fff
+#define NV_ADDRESS_MAP_EMC8_CORE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC8_CORE_HEADER
+
+#define NV_ADDRESS_MAP_EMC8_CFG_BASE 0x01781000
+#define NV_ADDRESS_MAP_EMC8_CFG_LIMIT 0x01781fff
+#define NV_ADDRESS_MAP_EMC8_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC8_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EMC8_EC_BASE 0x01782000
+#define NV_ADDRESS_MAP_EMC8_EC_LIMIT 0x01782fff
+#define NV_ADDRESS_MAP_EMC8_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC8_EC_HEADER
+
+#define NV_ADDRESS_MAP_EMC8_TR_BASE 0x01783000
+#define NV_ADDRESS_MAP_EMC8_TR_LIMIT 0x01783fff
+#define NV_ADDRESS_MAP_EMC8_TR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC8_TR_HEADER
+
+#define NV_ADDRESS_MAP_EMC8_MISC_BASE 0x01784000
+#define NV_ADDRESS_MAP_EMC8_MISC_LIMIT 0x0178ffff
+#define NV_ADDRESS_MAP_EMC8_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC8_MISC_HEADER
+
+#define NV_ADDRESS_MAP_EMC9_CORE_BASE 0x01790000
+#define NV_ADDRESS_MAP_EMC9_CORE_LIMIT 0x01790fff
+#define NV_ADDRESS_MAP_EMC9_CORE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC9_CORE_HEADER
+
+#define NV_ADDRESS_MAP_EMC9_CFG_BASE 0x01791000
+#define NV_ADDRESS_MAP_EMC9_CFG_LIMIT 0x01791fff
+#define NV_ADDRESS_MAP_EMC9_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC9_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EMC9_EC_BASE 0x01792000
+#define NV_ADDRESS_MAP_EMC9_EC_LIMIT 0x01792fff
+#define NV_ADDRESS_MAP_EMC9_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC9_EC_HEADER
+
+#define NV_ADDRESS_MAP_EMC9_TR_BASE 0x01793000
+#define NV_ADDRESS_MAP_EMC9_TR_LIMIT 0x01793fff
+#define NV_ADDRESS_MAP_EMC9_TR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC9_TR_HEADER
+
+#define NV_ADDRESS_MAP_EMC9_MISC_BASE 0x01794000
+#define NV_ADDRESS_MAP_EMC9_MISC_LIMIT 0x0179ffff
+#define NV_ADDRESS_MAP_EMC9_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC9_MISC_HEADER
+
+#define NV_ADDRESS_MAP_EMC10_CORE_BASE 0x017a0000
+#define NV_ADDRESS_MAP_EMC10_CORE_LIMIT 0x017a0fff
+#define NV_ADDRESS_MAP_EMC10_CORE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC10_CORE_HEADER
+
+#define NV_ADDRESS_MAP_EMC10_CFG_BASE 0x017a1000
+#define NV_ADDRESS_MAP_EMC10_CFG_LIMIT 0x017a1fff
+#define NV_ADDRESS_MAP_EMC10_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC10_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EMC10_EC_BASE 0x017a2000
+#define NV_ADDRESS_MAP_EMC10_EC_LIMIT 0x017a2fff
+#define NV_ADDRESS_MAP_EMC10_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC10_EC_HEADER
+
+#define NV_ADDRESS_MAP_EMC10_TR_BASE 0x017a3000
+#define NV_ADDRESS_MAP_EMC10_TR_LIMIT 0x017a3fff
+#define NV_ADDRESS_MAP_EMC10_TR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC10_TR_HEADER
+
+#define NV_ADDRESS_MAP_EMC10_MISC_BASE 0x017a4000
+#define NV_ADDRESS_MAP_EMC10_MISC_LIMIT 0x017affff
+#define NV_ADDRESS_MAP_EMC10_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC10_MISC_HEADER
+
+#define NV_ADDRESS_MAP_EMC11_CORE_BASE 0x017b0000
+#define NV_ADDRESS_MAP_EMC11_CORE_LIMIT 0x017b0fff
+#define NV_ADDRESS_MAP_EMC11_CORE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC11_CORE_HEADER
+
+#define NV_ADDRESS_MAP_EMC11_CFG_BASE 0x017b1000
+#define NV_ADDRESS_MAP_EMC11_CFG_LIMIT 0x017b1fff
+#define NV_ADDRESS_MAP_EMC11_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC11_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EMC11_EC_BASE 0x017b2000
+#define NV_ADDRESS_MAP_EMC11_EC_LIMIT 0x017b2fff
+#define NV_ADDRESS_MAP_EMC11_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC11_EC_HEADER
+
+#define NV_ADDRESS_MAP_EMC11_TR_BASE 0x017b3000
+#define NV_ADDRESS_MAP_EMC11_TR_LIMIT 0x017b3fff
+#define NV_ADDRESS_MAP_EMC11_TR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC11_TR_HEADER
+
+#define NV_ADDRESS_MAP_EMC11_MISC_BASE 0x017b4000
+#define NV_ADDRESS_MAP_EMC11_MISC_LIMIT 0x017bffff
+#define NV_ADDRESS_MAP_EMC11_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC11_MISC_HEADER
+
+#define NV_ADDRESS_MAP_EMC12_CORE_BASE 0x017c0000
+#define NV_ADDRESS_MAP_EMC12_CORE_LIMIT 0x017c0fff
+#define NV_ADDRESS_MAP_EMC12_CORE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC12_CORE_HEADER
+
+#define NV_ADDRESS_MAP_EMC12_CFG_BASE 0x017c1000
+#define NV_ADDRESS_MAP_EMC12_CFG_LIMIT 0x017c1fff
+#define NV_ADDRESS_MAP_EMC12_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC12_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EMC12_EC_BASE 0x017c2000
+#define NV_ADDRESS_MAP_EMC12_EC_LIMIT 0x017c2fff
+#define NV_ADDRESS_MAP_EMC12_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC12_EC_HEADER
+
+#define NV_ADDRESS_MAP_EMC12_TR_BASE 0x017c3000
+#define NV_ADDRESS_MAP_EMC12_TR_LIMIT 0x017c3fff
+#define NV_ADDRESS_MAP_EMC12_TR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC12_TR_HEADER
+
+#define NV_ADDRESS_MAP_EMC12_MISC_BASE 0x017c4000
+#define NV_ADDRESS_MAP_EMC12_MISC_LIMIT 0x017cffff
+#define NV_ADDRESS_MAP_EMC12_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC12_MISC_HEADER
+
+#define NV_ADDRESS_MAP_EMC13_CORE_BASE 0x017d0000
+#define NV_ADDRESS_MAP_EMC13_CORE_LIMIT 0x017d0fff
+#define NV_ADDRESS_MAP_EMC13_CORE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC13_CORE_HEADER
+
+#define NV_ADDRESS_MAP_EMC13_CFG_BASE 0x017d1000
+#define NV_ADDRESS_MAP_EMC13_CFG_LIMIT 0x017d1fff
+#define NV_ADDRESS_MAP_EMC13_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC13_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EMC13_EC_BASE 0x017d2000
+#define NV_ADDRESS_MAP_EMC13_EC_LIMIT 0x017d2fff
+#define NV_ADDRESS_MAP_EMC13_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC13_EC_HEADER
+
+#define NV_ADDRESS_MAP_EMC13_TR_BASE 0x017d3000
+#define NV_ADDRESS_MAP_EMC13_TR_LIMIT 0x017d3fff
+#define NV_ADDRESS_MAP_EMC13_TR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC13_TR_HEADER
+
+#define NV_ADDRESS_MAP_EMC13_MISC_BASE 0x017d4000
+#define NV_ADDRESS_MAP_EMC13_MISC_LIMIT 0x017dffff
+#define NV_ADDRESS_MAP_EMC13_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC13_MISC_HEADER
+
+#define NV_ADDRESS_MAP_EMC14_CORE_BASE 0x017e0000
+#define NV_ADDRESS_MAP_EMC14_CORE_LIMIT 0x017e0fff
+#define NV_ADDRESS_MAP_EMC14_CORE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC14_CORE_HEADER
+
+#define NV_ADDRESS_MAP_EMC14_CFG_BASE 0x017e1000
+#define NV_ADDRESS_MAP_EMC14_CFG_LIMIT 0x017e1fff
+#define NV_ADDRESS_MAP_EMC14_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC14_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EMC14_EC_BASE 0x017e2000
+#define NV_ADDRESS_MAP_EMC14_EC_LIMIT 0x017e2fff
+#define NV_ADDRESS_MAP_EMC14_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC14_EC_HEADER
+
+#define NV_ADDRESS_MAP_EMC14_TR_BASE 0x017e3000
+#define NV_ADDRESS_MAP_EMC14_TR_LIMIT 0x017e3fff
+#define NV_ADDRESS_MAP_EMC14_TR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC14_TR_HEADER
+
+#define NV_ADDRESS_MAP_EMC14_MISC_BASE 0x017e4000
+#define NV_ADDRESS_MAP_EMC14_MISC_LIMIT 0x017effff
+#define NV_ADDRESS_MAP_EMC14_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC14_MISC_HEADER
+
+#define NV_ADDRESS_MAP_EMC15_CORE_BASE 0x017f0000
+#define NV_ADDRESS_MAP_EMC15_CORE_LIMIT 0x017f0fff
+#define NV_ADDRESS_MAP_EMC15_CORE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC15_CORE_HEADER
+
+#define NV_ADDRESS_MAP_EMC15_CFG_BASE 0x017f1000
+#define NV_ADDRESS_MAP_EMC15_CFG_LIMIT 0x017f1fff
+#define NV_ADDRESS_MAP_EMC15_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC15_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EMC15_EC_BASE 0x017f2000
+#define NV_ADDRESS_MAP_EMC15_EC_LIMIT 0x017f2fff
+#define NV_ADDRESS_MAP_EMC15_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC15_EC_HEADER
+
+#define NV_ADDRESS_MAP_EMC15_TR_BASE 0x017f3000
+#define NV_ADDRESS_MAP_EMC15_TR_LIMIT 0x017f3fff
+#define NV_ADDRESS_MAP_EMC15_TR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC15_TR_HEADER
+
+#define NV_ADDRESS_MAP_EMC15_MISC_BASE 0x017f4000
+#define NV_ADDRESS_MAP_EMC15_MISC_LIMIT 0x017fffff
+#define NV_ADDRESS_MAP_EMC15_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC15_MISC_HEADER
+
+#define NV_ADDRESS_MAP_MSS_NVLINK_8_BASE 0x01e00000
+#define NV_ADDRESS_MAP_MSS_NVLINK_8_LIMIT 0x01e1ffff
+#define NV_ADDRESS_MAP_MSS_NVLINK_8_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MSS_NVLINK_8_HEADER armssnvlink.h;armssnvlink_scr.h
+
+#define NV_ADDRESS_MAP_MSS_NVLINK_1_BASE 0x01f20000
+#define NV_ADDRESS_MAP_MSS_NVLINK_1_LIMIT 0x01f3ffff
+#define NV_ADDRESS_MAP_MSS_NVLINK_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MSS_NVLINK_1_HEADER armssnvlink.h;armssnvlink_scr.h
+
+#define NV_ADDRESS_MAP_MSS_NVLINK_2_BASE 0x01f40000
+#define NV_ADDRESS_MAP_MSS_NVLINK_2_LIMIT 0x01f5ffff
+#define NV_ADDRESS_MAP_MSS_NVLINK_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MSS_NVLINK_2_HEADER armssnvlink.h;armssnvlink_scr.h
+
+#define NV_ADDRESS_MAP_MSS_NVLINK_3_BASE 0x01f60000
+#define NV_ADDRESS_MAP_MSS_NVLINK_3_LIMIT 0x01f7ffff
+#define NV_ADDRESS_MAP_MSS_NVLINK_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MSS_NVLINK_3_HEADER armssnvlink.h;armssnvlink_scr.h
+
+#define NV_ADDRESS_MAP_MSS_NVLINK_4_BASE 0x01f80000
+#define NV_ADDRESS_MAP_MSS_NVLINK_4_LIMIT 0x01f9ffff
+#define NV_ADDRESS_MAP_MSS_NVLINK_4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MSS_NVLINK_4_HEADER armssnvlink.h;armssnvlink_scr.h
+
+#define NV_ADDRESS_MAP_MSS_NVLINK_5_BASE 0x01fa0000
+#define NV_ADDRESS_MAP_MSS_NVLINK_5_LIMIT 0x01fbffff
+#define NV_ADDRESS_MAP_MSS_NVLINK_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MSS_NVLINK_5_HEADER armssnvlink.h;armssnvlink_scr.h
+
+#define NV_ADDRESS_MAP_MSS_NVLINK_6_BASE 0x01fc0000
+#define NV_ADDRESS_MAP_MSS_NVLINK_6_LIMIT 0x01fdffff
+#define NV_ADDRESS_MAP_MSS_NVLINK_6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MSS_NVLINK_6_HEADER armssnvlink.h;armssnvlink_scr.h
+
+#define NV_ADDRESS_MAP_MSS_NVLINK_7_BASE 0x01fe0000
+#define NV_ADDRESS_MAP_MSS_NVLINK_7_LIMIT 0x01ffffff
+#define NV_ADDRESS_MAP_MSS_NVLINK_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MSS_NVLINK_7_HEADER armssnvlink.h;armssnvlink_scr.h
+
+#define NV_ADDRESS_MAP_TSA_NODE_0_BASE 0x02000000
+#define NV_ADDRESS_MAP_TSA_NODE_0_LIMIT 0x02000fff
+#define NV_ADDRESS_MAP_TSA_NODE_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_0_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_1_BASE 0x02001000
+#define NV_ADDRESS_MAP_TSA_NODE_1_LIMIT 0x02001fff
+#define NV_ADDRESS_MAP_TSA_NODE_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_1_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_2_BASE 0x02002000
+#define NV_ADDRESS_MAP_TSA_NODE_2_LIMIT 0x02002fff
+#define NV_ADDRESS_MAP_TSA_NODE_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_2_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_3_BASE 0x02003000
+#define NV_ADDRESS_MAP_TSA_NODE_3_LIMIT 0x02003fff
+#define NV_ADDRESS_MAP_TSA_NODE_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_3_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_4_BASE 0x02004000
+#define NV_ADDRESS_MAP_TSA_NODE_4_LIMIT 0x02004fff
+#define NV_ADDRESS_MAP_TSA_NODE_4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_4_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_5_BASE 0x02005000
+#define NV_ADDRESS_MAP_TSA_NODE_5_LIMIT 0x02005fff
+#define NV_ADDRESS_MAP_TSA_NODE_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_5_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_6_BASE 0x02006000
+#define NV_ADDRESS_MAP_TSA_NODE_6_LIMIT 0x02006fff
+#define NV_ADDRESS_MAP_TSA_NODE_6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_6_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_7_BASE 0x02007000
+#define NV_ADDRESS_MAP_TSA_NODE_7_LIMIT 0x02007fff
+#define NV_ADDRESS_MAP_TSA_NODE_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_7_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_8_BASE 0x02008000
+#define NV_ADDRESS_MAP_TSA_NODE_8_LIMIT 0x02008fff
+#define NV_ADDRESS_MAP_TSA_NODE_8_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_8_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_10_BASE 0x0200a000
+#define NV_ADDRESS_MAP_TSA_NODE_10_LIMIT 0x0200afff
+#define NV_ADDRESS_MAP_TSA_NODE_10_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_10_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_13_BASE 0x0200d000
+#define NV_ADDRESS_MAP_TSA_NODE_13_LIMIT 0x0200dfff
+#define NV_ADDRESS_MAP_TSA_NODE_13_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_13_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_14_BASE 0x0200e000
+#define NV_ADDRESS_MAP_TSA_NODE_14_LIMIT 0x0200efff
+#define NV_ADDRESS_MAP_TSA_NODE_14_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_14_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_16_BASE 0x02010000
+#define NV_ADDRESS_MAP_TSA_NODE_16_LIMIT 0x02010fff
+#define NV_ADDRESS_MAP_TSA_NODE_16_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_16_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_18_BASE 0x02012000
+#define NV_ADDRESS_MAP_TSA_NODE_18_LIMIT 0x02012fff
+#define NV_ADDRESS_MAP_TSA_NODE_18_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_18_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_21_BASE 0x02015000
+#define NV_ADDRESS_MAP_TSA_NODE_21_LIMIT 0x02015fff
+#define NV_ADDRESS_MAP_TSA_NODE_21_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_21_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_24_BASE 0x02018000
+#define NV_ADDRESS_MAP_TSA_NODE_24_LIMIT 0x02018fff
+#define NV_ADDRESS_MAP_TSA_NODE_24_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_24_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_25_BASE 0x02019000
+#define NV_ADDRESS_MAP_TSA_NODE_25_LIMIT 0x02019fff
+#define NV_ADDRESS_MAP_TSA_NODE_25_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_25_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_26_BASE 0x0201a000
+#define NV_ADDRESS_MAP_TSA_NODE_26_LIMIT 0x0201afff
+#define NV_ADDRESS_MAP_TSA_NODE_26_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_26_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_27_BASE 0x0201b000
+#define NV_ADDRESS_MAP_TSA_NODE_27_LIMIT 0x0201bfff
+#define NV_ADDRESS_MAP_TSA_NODE_27_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_27_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_29_BASE 0x0201d000
+#define NV_ADDRESS_MAP_TSA_NODE_29_LIMIT 0x0201dfff
+#define NV_ADDRESS_MAP_TSA_NODE_29_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_29_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_30_BASE 0x0201e000
+#define NV_ADDRESS_MAP_TSA_NODE_30_LIMIT 0x0201efff
+#define NV_ADDRESS_MAP_TSA_NODE_30_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_30_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_33_BASE 0x02021000
+#define NV_ADDRESS_MAP_TSA_NODE_33_LIMIT 0x02021fff
+#define NV_ADDRESS_MAP_TSA_NODE_33_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_33_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_36_BASE 0x02024000
+#define NV_ADDRESS_MAP_TSA_NODE_36_LIMIT 0x02024fff
+#define NV_ADDRESS_MAP_TSA_NODE_36_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_36_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_37_BASE 0x02025000
+#define NV_ADDRESS_MAP_TSA_NODE_37_LIMIT 0x02025fff
+#define NV_ADDRESS_MAP_TSA_NODE_37_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_37_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_39_BASE 0x02027000
+#define NV_ADDRESS_MAP_TSA_NODE_39_LIMIT 0x02027fff
+#define NV_ADDRESS_MAP_TSA_NODE_39_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_39_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_40_BASE 0x02028000
+#define NV_ADDRESS_MAP_TSA_NODE_40_LIMIT 0x02028fff
+#define NV_ADDRESS_MAP_TSA_NODE_40_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_40_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_42_BASE 0x0202a000
+#define NV_ADDRESS_MAP_TSA_NODE_42_LIMIT 0x0202afff
+#define NV_ADDRESS_MAP_TSA_NODE_42_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_42_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_44_BASE 0x0202c000
+#define NV_ADDRESS_MAP_TSA_NODE_44_LIMIT 0x0202cfff
+#define NV_ADDRESS_MAP_TSA_NODE_44_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_44_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_45_BASE 0x0202d000
+#define NV_ADDRESS_MAP_TSA_NODE_45_LIMIT 0x0202dfff
+#define NV_ADDRESS_MAP_TSA_NODE_45_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_45_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_46_BASE 0x0202e000
+#define NV_ADDRESS_MAP_TSA_NODE_46_LIMIT 0x0202efff
+#define NV_ADDRESS_MAP_TSA_NODE_46_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_46_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_48_BASE 0x02030000
+#define NV_ADDRESS_MAP_TSA_NODE_48_LIMIT 0x02030fff
+#define NV_ADDRESS_MAP_TSA_NODE_48_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_48_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_52_BASE 0x02034000
+#define NV_ADDRESS_MAP_TSA_NODE_52_LIMIT 0x02034fff
+#define NV_ADDRESS_MAP_TSA_NODE_52_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_52_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_53_BASE 0x02035000
+#define NV_ADDRESS_MAP_TSA_NODE_53_LIMIT 0x02035fff
+#define NV_ADDRESS_MAP_TSA_NODE_53_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_53_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_57_BASE 0x02039000
+#define NV_ADDRESS_MAP_TSA_NODE_57_LIMIT 0x02039fff
+#define NV_ADDRESS_MAP_TSA_NODE_57_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_57_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_58_BASE 0x0203a000
+#define NV_ADDRESS_MAP_TSA_NODE_58_LIMIT 0x0203afff
+#define NV_ADDRESS_MAP_TSA_NODE_58_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_58_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_60_BASE 0x0203c000
+#define NV_ADDRESS_MAP_TSA_NODE_60_LIMIT 0x0203cfff
+#define NV_ADDRESS_MAP_TSA_NODE_60_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_60_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_61_BASE 0x0203d000
+#define NV_ADDRESS_MAP_TSA_NODE_61_LIMIT 0x0203dfff
+#define NV_ADDRESS_MAP_TSA_NODE_61_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_61_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_63_BASE 0x0203f000
+#define NV_ADDRESS_MAP_TSA_NODE_63_LIMIT 0x0203ffff
+#define NV_ADDRESS_MAP_TSA_NODE_63_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_63_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_65_BASE 0x02041000
+#define NV_ADDRESS_MAP_TSA_NODE_65_LIMIT 0x02041fff
+#define NV_ADDRESS_MAP_TSA_NODE_65_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_65_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_67_BASE 0x02043000
+#define NV_ADDRESS_MAP_TSA_NODE_67_LIMIT 0x02043fff
+#define NV_ADDRESS_MAP_TSA_NODE_67_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_67_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_68_BASE 0x02044000
+#define NV_ADDRESS_MAP_TSA_NODE_68_LIMIT 0x02044fff
+#define NV_ADDRESS_MAP_TSA_NODE_68_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_68_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_72_BASE 0x02048000
+#define NV_ADDRESS_MAP_TSA_NODE_72_LIMIT 0x02048fff
+#define NV_ADDRESS_MAP_TSA_NODE_72_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_72_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_75_BASE 0x0204b000
+#define NV_ADDRESS_MAP_TSA_NODE_75_LIMIT 0x0204bfff
+#define NV_ADDRESS_MAP_TSA_NODE_75_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_75_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_77_BASE 0x0204d000
+#define NV_ADDRESS_MAP_TSA_NODE_77_LIMIT 0x0204dfff
+#define NV_ADDRESS_MAP_TSA_NODE_77_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_77_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_78_BASE 0x0204e000
+#define NV_ADDRESS_MAP_TSA_NODE_78_LIMIT 0x0204efff
+#define NV_ADDRESS_MAP_TSA_NODE_78_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_78_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_81_BASE 0x02051000
+#define NV_ADDRESS_MAP_TSA_NODE_81_LIMIT 0x02051fff
+#define NV_ADDRESS_MAP_TSA_NODE_81_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_81_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_83_BASE 0x02053000
+#define NV_ADDRESS_MAP_TSA_NODE_83_LIMIT 0x02053fff
+#define NV_ADDRESS_MAP_TSA_NODE_83_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_83_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_85_BASE 0x02055000
+#define NV_ADDRESS_MAP_TSA_NODE_85_LIMIT 0x02055fff
+#define NV_ADDRESS_MAP_TSA_NODE_85_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_85_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_90_BASE 0x0205a000
+#define NV_ADDRESS_MAP_TSA_NODE_90_LIMIT 0x0205afff
+#define NV_ADDRESS_MAP_TSA_NODE_90_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_90_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_96_BASE 0x02060000
+#define NV_ADDRESS_MAP_TSA_NODE_96_LIMIT 0x02060fff
+#define NV_ADDRESS_MAP_TSA_NODE_96_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_96_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_97_BASE 0x02061000
+#define NV_ADDRESS_MAP_TSA_NODE_97_LIMIT 0x02061fff
+#define NV_ADDRESS_MAP_TSA_NODE_97_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_97_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_98_BASE 0x02062000
+#define NV_ADDRESS_MAP_TSA_NODE_98_LIMIT 0x02062fff
+#define NV_ADDRESS_MAP_TSA_NODE_98_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_98_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_99_BASE 0x02063000
+#define NV_ADDRESS_MAP_TSA_NODE_99_LIMIT 0x02063fff
+#define NV_ADDRESS_MAP_TSA_NODE_99_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_99_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_100_BASE 0x02064000
+#define NV_ADDRESS_MAP_TSA_NODE_100_LIMIT 0x02064fff
+#define NV_ADDRESS_MAP_TSA_NODE_100_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_100_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_101_BASE 0x02065000
+#define NV_ADDRESS_MAP_TSA_NODE_101_LIMIT 0x02065fff
+#define NV_ADDRESS_MAP_TSA_NODE_101_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_101_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_104_BASE 0x02068000
+#define NV_ADDRESS_MAP_TSA_NODE_104_LIMIT 0x02068fff
+#define NV_ADDRESS_MAP_TSA_NODE_104_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_104_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_106_BASE 0x0206a000
+#define NV_ADDRESS_MAP_TSA_NODE_106_LIMIT 0x0206afff
+#define NV_ADDRESS_MAP_TSA_NODE_106_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_106_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_109_BASE 0x0206d000
+#define NV_ADDRESS_MAP_TSA_NODE_109_LIMIT 0x0206dfff
+#define NV_ADDRESS_MAP_TSA_NODE_109_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_109_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_110_BASE 0x0206e000
+#define NV_ADDRESS_MAP_TSA_NODE_110_LIMIT 0x0206efff
+#define NV_ADDRESS_MAP_TSA_NODE_110_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_110_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_117_BASE 0x02075000
+#define NV_ADDRESS_MAP_TSA_NODE_117_LIMIT 0x02075fff
+#define NV_ADDRESS_MAP_TSA_NODE_117_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_117_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_120_BASE 0x02078000
+#define NV_ADDRESS_MAP_TSA_NODE_120_LIMIT 0x02078fff
+#define NV_ADDRESS_MAP_TSA_NODE_120_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_120_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_123_BASE 0x0207b000
+#define NV_ADDRESS_MAP_TSA_NODE_123_LIMIT 0x0207bfff
+#define NV_ADDRESS_MAP_TSA_NODE_123_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_123_HEADER
+
+#define NV_ADDRESS_MAP_TMR_SHARED_BASE 0x02080000
+#define NV_ADDRESS_MAP_TMR_SHARED_LIMIT 0x0208ffff
+#define NV_ADDRESS_MAP_TMR_SHARED_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TMR_SHARED_HEADER
+
+#define NV_ADDRESS_MAP_TMR0_BASE 0x02090000
+#define NV_ADDRESS_MAP_TMR0_LIMIT 0x0209ffff
+#define NV_ADDRESS_MAP_TMR0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TMR0_HEADER
+
+#define NV_ADDRESS_MAP_TMR1_BASE 0x020a0000
+#define NV_ADDRESS_MAP_TMR1_LIMIT 0x020affff
+#define NV_ADDRESS_MAP_TMR1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TMR1_HEADER
+
+#define NV_ADDRESS_MAP_TMR2_BASE 0x020b0000
+#define NV_ADDRESS_MAP_TMR2_LIMIT 0x020bffff
+#define NV_ADDRESS_MAP_TMR2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TMR2_HEADER
+
+#define NV_ADDRESS_MAP_TMR3_BASE 0x020c0000
+#define NV_ADDRESS_MAP_TMR3_LIMIT 0x020cffff
+#define NV_ADDRESS_MAP_TMR3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TMR3_HEADER
+
+#define NV_ADDRESS_MAP_TMR4_BASE 0x020d0000
+#define NV_ADDRESS_MAP_TMR4_LIMIT 0x020dffff
+#define NV_ADDRESS_MAP_TMR4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TMR4_HEADER
+
+#define NV_ADDRESS_MAP_TMR5_BASE 0x020e0000
+#define NV_ADDRESS_MAP_TMR5_LIMIT 0x020effff
+#define NV_ADDRESS_MAP_TMR5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TMR5_HEADER
+
+#define NV_ADDRESS_MAP_TMR6_BASE 0x020f0000
+#define NV_ADDRESS_MAP_TMR6_LIMIT 0x020fffff
+#define NV_ADDRESS_MAP_TMR6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TMR6_HEADER
+
+#define NV_ADDRESS_MAP_TMR7_BASE 0x02100000
+#define NV_ADDRESS_MAP_TMR7_LIMIT 0x0210ffff
+#define NV_ADDRESS_MAP_TMR7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TMR7_HEADER
+
+#define NV_ADDRESS_MAP_TMR8_BASE 0x02110000
+#define NV_ADDRESS_MAP_TMR8_LIMIT 0x0211ffff
+#define NV_ADDRESS_MAP_TMR8_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TMR8_HEADER
+
+#define NV_ADDRESS_MAP_TMR9_BASE 0x02120000
+#define NV_ADDRESS_MAP_TMR9_LIMIT 0x0212ffff
+#define NV_ADDRESS_MAP_TMR9_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TMR9_HEADER
+
+#define NV_ADDRESS_MAP_TMR10_BASE 0x02130000
+#define NV_ADDRESS_MAP_TMR10_LIMIT 0x0213ffff
+#define NV_ADDRESS_MAP_TMR10_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TMR10_HEADER
+
+#define NV_ADDRESS_MAP_TMR11_BASE 0x02140000
+#define NV_ADDRESS_MAP_TMR11_LIMIT 0x0214ffff
+#define NV_ADDRESS_MAP_TMR11_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TMR11_HEADER
+
+#define NV_ADDRESS_MAP_TMR12_BASE 0x02150000
+#define NV_ADDRESS_MAP_TMR12_LIMIT 0x0215ffff
+#define NV_ADDRESS_MAP_TMR12_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TMR12_HEADER
+
+#define NV_ADDRESS_MAP_TMR13_BASE 0x02160000
+#define NV_ADDRESS_MAP_TMR13_LIMIT 0x0216ffff
+#define NV_ADDRESS_MAP_TMR13_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TMR13_HEADER
+
+#define NV_ADDRESS_MAP_TMR14_BASE 0x02170000
+#define NV_ADDRESS_MAP_TMR14_LIMIT 0x0217ffff
+#define NV_ADDRESS_MAP_TMR14_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TMR14_HEADER
+
+#define NV_ADDRESS_MAP_TMR15_BASE 0x02180000
+#define NV_ADDRESS_MAP_TMR15_LIMIT 0x0218ffff
+#define NV_ADDRESS_MAP_TMR15_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TMR15_HEADER
+
+#define NV_ADDRESS_MAP_WDT0_BASE 0x02190000
+#define NV_ADDRESS_MAP_WDT0_LIMIT 0x0219ffff
+#define NV_ADDRESS_MAP_WDT0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_WDT0_HEADER
+
+#define NV_ADDRESS_MAP_WDT1_BASE 0x021a0000
+#define NV_ADDRESS_MAP_WDT1_LIMIT 0x021affff
+#define NV_ADDRESS_MAP_WDT1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_WDT1_HEADER
+
+#define NV_ADDRESS_MAP_WDT2_BASE 0x021b0000
+#define NV_ADDRESS_MAP_WDT2_LIMIT 0x021bffff
+#define NV_ADDRESS_MAP_WDT2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_WDT2_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO0_BASE 0x02200000
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO0_LIMIT 0x02200fff
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO0_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO1_BASE 0x02201000
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO1_LIMIT 0x02201fff
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO1_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO2_BASE 0x02202000
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO2_LIMIT 0x02202fff
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO2_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO3_BASE 0x02203000
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO3_LIMIT 0x02203fff
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO3_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO4_BASE 0x02204000
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO4_LIMIT 0x02204fff
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO4_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO5_BASE 0x02205000
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO5_LIMIT 0x02205fff
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL_COMMON_GPIO5_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO0_BASE 0x02210000
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO0_LIMIT 0x02210fff
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO0_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO1_BASE 0x02211000
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO1_LIMIT 0x02211fff
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO1_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO2_BASE 0x02212000
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO2_LIMIT 0x02212fff
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO2_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO3_BASE 0x02213000
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO3_LIMIT 0x02213fff
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO3_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO4_BASE 0x02214000
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO4_LIMIT 0x02214fff
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO4_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO5_BASE 0x02215000
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO5_LIMIT 0x02215fff
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL0_GPIO5_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO0_BASE 0x02220000
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO0_LIMIT 0x02220fff
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO0_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO1_BASE 0x02221000
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO1_LIMIT 0x02221fff
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO1_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO2_BASE 0x02222000
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO2_LIMIT 0x02222fff
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO2_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO3_BASE 0x02223000
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO3_LIMIT 0x02223fff
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO3_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO4_BASE 0x02224000
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO4_LIMIT 0x02224fff
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO4_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO5_BASE 0x02225000
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO5_LIMIT 0x02225fff
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL1_GPIO5_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO0_BASE 0x02230000
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO0_LIMIT 0x02230fff
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO0_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO1_BASE 0x02231000
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO1_LIMIT 0x02231fff
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO1_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO2_BASE 0x02232000
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO2_LIMIT 0x02232fff
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO2_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO3_BASE 0x02233000
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO3_LIMIT 0x02233fff
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO3_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO4_BASE 0x02234000
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO4_LIMIT 0x02234fff
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO4_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO5_BASE 0x02235000
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO5_LIMIT 0x02235fff
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL2_GPIO5_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO0_BASE 0x02240000
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO0_LIMIT 0x02240fff
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO0_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO1_BASE 0x02241000
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO1_LIMIT 0x02241fff
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO1_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO2_BASE 0x02242000
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO2_LIMIT 0x02242fff
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO2_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO3_BASE 0x02243000
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO3_LIMIT 0x02243fff
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO3_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO4_BASE 0x02244000
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO4_LIMIT 0x02244fff
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO4_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO5_BASE 0x02245000
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO5_LIMIT 0x02245fff
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL3_GPIO5_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO0_BASE 0x02250000
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO0_LIMIT 0x02250fff
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO0_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO1_BASE 0x02251000
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO1_LIMIT 0x02251fff
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO1_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO2_BASE 0x02252000
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO2_LIMIT 0x02252fff
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO2_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO3_BASE 0x02253000
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO3_LIMIT 0x02253fff
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO3_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO4_BASE 0x02254000
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO4_LIMIT 0x02254fff
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO4_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO5_BASE 0x02255000
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO5_LIMIT 0x02255fff
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL4_GPIO5_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO0_BASE 0x02260000
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO0_LIMIT 0x02260fff
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO0_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO1_BASE 0x02261000
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO1_LIMIT 0x02261fff
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO1_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO2_BASE 0x02262000
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO2_LIMIT 0x02262fff
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO2_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO3_BASE 0x02263000
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO3_LIMIT 0x02263fff
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO3_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO4_BASE 0x02264000
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO4_LIMIT 0x02264fff
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO4_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO5_BASE 0x02265000
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO5_LIMIT 0x02265fff
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL5_GPIO5_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO0_BASE 0x02270000
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO0_LIMIT 0x02270fff
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO0_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO1_BASE 0x02271000
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO1_LIMIT 0x02271fff
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO1_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO2_BASE 0x02272000
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO2_LIMIT 0x02272fff
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO2_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO3_BASE 0x02273000
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO3_LIMIT 0x02273fff
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO3_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO4_BASE 0x02274000
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO4_LIMIT 0x02274fff
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO4_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO5_BASE 0x02275000
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO5_LIMIT 0x02275fff
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL6_GPIO5_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO0_BASE 0x02280000
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO0_LIMIT 0x02280fff
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO0_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO1_BASE 0x02281000
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO1_LIMIT 0x02281fff
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO1_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO2_BASE 0x02282000
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO2_LIMIT 0x02282fff
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO2_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO3_BASE 0x02283000
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO3_LIMIT 0x02283fff
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO3_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO4_BASE 0x02284000
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO4_LIMIT 0x02284fff
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO4_HEADER
+
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO5_BASE 0x02285000
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO5_LIMIT 0x02285fff
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPIO_CTL7_GPIO5_HEADER
+
+#define NV_ADDRESS_MAP_EQOS_MAC_HV_BASE 0x02300000
+#define NV_ADDRESS_MAP_EQOS_MAC_HV_LIMIT 0x0230ffff
+#define NV_ADDRESS_MAP_EQOS_MAC_HV_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MAC_HV_HEADER arether_qos.h;arether_core.h
+
+#define NV_ADDRESS_MAP_EQOS_MAC_RM_CFG_BASE 0x02310000
+#define NV_ADDRESS_MAP_EQOS_MAC_RM_CFG_LIMIT 0x0231efff
+#define NV_ADDRESS_MAP_EQOS_MAC_RM_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MAC_RM_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EQOS_MAC_RM_ERR_BASE 0x0231f000
+#define NV_ADDRESS_MAP_EQOS_MAC_RM_ERR_LIMIT 0x0231ffff
+#define NV_ADDRESS_MAP_EQOS_MAC_RM_ERR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MAC_RM_ERR_HEADER
+
+#define NV_ADDRESS_MAP_EQOS_MAC_VM0_BASE 0x02320000
+#define NV_ADDRESS_MAP_EQOS_MAC_VM0_LIMIT 0x0232ffff
+#define NV_ADDRESS_MAP_EQOS_MAC_VM0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MAC_VM0_HEADER arether_qos.h;arether_core.h
+
+#define NV_ADDRESS_MAP_EQOS_MAC_VM1_BASE 0x02330000
+#define NV_ADDRESS_MAP_EQOS_MAC_VM1_LIMIT 0x0233ffff
+#define NV_ADDRESS_MAP_EQOS_MAC_VM1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MAC_VM1_HEADER arether_qos.h;arether_core.h
+
+#define NV_ADDRESS_MAP_EQOS_MAC_VM2_BASE 0x02340000
+#define NV_ADDRESS_MAP_EQOS_MAC_VM2_LIMIT 0x0234ffff
+#define NV_ADDRESS_MAP_EQOS_MAC_VM2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MAC_VM2_HEADER arether_qos.h;arether_core.h
+
+#define NV_ADDRESS_MAP_EQOS_MAC_VM3_BASE 0x02350000
+#define NV_ADDRESS_MAP_EQOS_MAC_VM3_LIMIT 0x0235ffff
+#define NV_ADDRESS_MAP_EQOS_MAC_VM3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MAC_VM3_HEADER arether_qos.h;arether_core.h
+
+#define NV_ADDRESS_MAP_EQOS_MAC_VM4_BASE 0x02360000
+#define NV_ADDRESS_MAP_EQOS_MAC_VM4_LIMIT 0x0236ffff
+#define NV_ADDRESS_MAP_EQOS_MAC_VM4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MAC_VM4_HEADER arether_qos.h;arether_core.h
+
+#define NV_ADDRESS_MAP_EQOS_MAC_VM5_BASE 0x02370000
+#define NV_ADDRESS_MAP_EQOS_MAC_VM5_LIMIT 0x0237ffff
+#define NV_ADDRESS_MAP_EQOS_MAC_VM5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MAC_VM5_HEADER arether_qos.h;arether_core.h
+
+#define NV_ADDRESS_MAP_EQOS_MAC_VM6_BASE 0x02380000
+#define NV_ADDRESS_MAP_EQOS_MAC_VM6_LIMIT 0x0238ffff
+#define NV_ADDRESS_MAP_EQOS_MAC_VM6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MAC_VM6_HEADER arether_qos.h;arether_core.h
+
+#define NV_ADDRESS_MAP_EQOS_MAC_VM7_BASE 0x02390000
+#define NV_ADDRESS_MAP_EQOS_MAC_VM7_LIMIT 0x0239ffff
+#define NV_ADDRESS_MAP_EQOS_MAC_VM7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MAC_VM7_HEADER arether_qos.h;arether_core.h
+
+#define NV_ADDRESS_MAP_EQOS_MACSEC_BASE 0x023c0000
+#define NV_ADDRESS_MAP_EQOS_MACSEC_LIMIT 0x023effff
+#define NV_ADDRESS_MAP_EQOS_MACSEC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MACSEC_HEADER
+
+#define NV_ADDRESS_MAP_EQOS_MACSEC_TZ_BASE 0x023c0000
+#define NV_ADDRESS_MAP_EQOS_MACSEC_TZ_LIMIT 0x023cffff
+#define NV_ADDRESS_MAP_EQOS_MACSEC_TZ_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MACSEC_TZ_HEADER armacsec.h
+
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_BASE 0x023d0000
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_LIMIT 0x023dffff
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_HEADER armacsec.h
+
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_CFG_BASE 0x023d0000
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_CFG_LIMIT 0x023dcfff
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_TX_BYP_BASE 0x023dd000
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_TX_BYP_LIMIT 0x023ddfff
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_TX_BYP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_TX_BYP_HEADER
+
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_RX_BYP_BASE 0x023de000
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_RX_BYP_LIMIT 0x023defff
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_RX_BYP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_RX_BYP_HEADER
+
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_ERR_BASE 0x023df000
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_ERR_LIMIT 0x023dffff
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_ERR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MACSEC_RM_ERR_HEADER
+
+#define NV_ADDRESS_MAP_EQOS_MACSEC_VM_BASE 0x023e0000
+#define NV_ADDRESS_MAP_EQOS_MACSEC_VM_LIMIT 0x023effff
+#define NV_ADDRESS_MAP_EQOS_MACSEC_VM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MACSEC_VM_HEADER armacsec.h
+
+#define NV_ADDRESS_MAP_EQOS_MACSEC_VM_STATS_BASE 0x023e0000
+#define NV_ADDRESS_MAP_EQOS_MACSEC_VM_STATS_LIMIT 0x023eefff
+#define NV_ADDRESS_MAP_EQOS_MACSEC_VM_STATS_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MACSEC_VM_STATS_HEADER
+
+#define NV_ADDRESS_MAP_EQOS_MACSEC_VM_STS_ERR_BASE 0x023ef000
+#define NV_ADDRESS_MAP_EQOS_MACSEC_VM_STS_ERR_LIMIT 0x023effff
+#define NV_ADDRESS_MAP_EQOS_MACSEC_VM_STS_ERR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EQOS_MACSEC_VM_STS_ERR_HEADER
+
+#define NV_ADDRESS_MAP_HDACODEC_BASE 0x0242c000
+#define NV_ADDRESS_MAP_HDACODEC_LIMIT 0x0242cfff
+#define NV_ADDRESS_MAP_HDACODEC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HDACODEC_HEADER dev_hdacodec.h
+
+#define NV_ADDRESS_MAP_PADCTL_A0_BASE 0x02430000
+#define NV_ADDRESS_MAP_PADCTL_A0_LIMIT 0x02430fff
+#define NV_ADDRESS_MAP_PADCTL_A0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A0_HEADER arpadctl_G3.h;arpadctl_G3_scr.h
+
+#define NV_ADDRESS_MAP_PADCTL_A2_BASE 0x02432000
+#define NV_ADDRESS_MAP_PADCTL_A2_LIMIT 0x02432fff
+#define NV_ADDRESS_MAP_PADCTL_A2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A2_HEADER arpadctl_G5.h;arpadctl_G5_scr.h
+
+#define NV_ADDRESS_MAP_PADCTL_A4_BASE 0x02434000
+#define NV_ADDRESS_MAP_PADCTL_A4_LIMIT 0x02434fff
+#define NV_ADDRESS_MAP_PADCTL_A4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A4_HEADER arpadctl_G4.h;arpadctl_G4_scr.h
+
+#define NV_ADDRESS_MAP_PADCTL_A5_BASE 0x02435000
+#define NV_ADDRESS_MAP_PADCTL_A5_LIMIT 0x02435fff
+#define NV_ADDRESS_MAP_PADCTL_A5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A5_HEADER arpadctl_DEBUG.h;arpadctl_DEBUG_scr.h
+
+#define NV_ADDRESS_MAP_PADCTL_A6_BASE 0x02436000
+#define NV_ADDRESS_MAP_PADCTL_A6_LIMIT 0x02436fff
+#define NV_ADDRESS_MAP_PADCTL_A6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A6_HEADER arpadctl_EMMC.h;arpadctl_EMMC_scr.h
+
+#define NV_ADDRESS_MAP_PADCTL_A7_BASE 0x02437000
+#define NV_ADDRESS_MAP_PADCTL_A7_LIMIT 0x02437fff
+#define NV_ADDRESS_MAP_PADCTL_A7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A7_HEADER arpadctl_PEX_CTL.h;arpadctl_PEX_CTL_scr.h
+
+#define NV_ADDRESS_MAP_PADCTL_A8_BASE 0x02438000
+#define NV_ADDRESS_MAP_PADCTL_A8_LIMIT 0x02438fff
+#define NV_ADDRESS_MAP_PADCTL_A8_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A8_HEADER arpadctl_SDMMC1_HV.h;arpadctl_SDMMC1_HV_scr.h
+
+#define NV_ADDRESS_MAP_PADCTL_A11_BASE 0x0243b000
+#define NV_ADDRESS_MAP_PADCTL_A11_LIMIT 0x0243bfff
+#define NV_ADDRESS_MAP_PADCTL_A11_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A11_HEADER arpadctl_QSPI.h;arpadctl_QSPI_scr.h
+
+#define NV_ADDRESS_MAP_PADCTL_A13_BASE 0x0243d000
+#define NV_ADDRESS_MAP_PADCTL_A13_LIMIT 0x0243dfff
+#define NV_ADDRESS_MAP_PADCTL_A13_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A13_HEADER arpadctl_G2.h;arpadctl_G2_scr.h
+
+#define NV_ADDRESS_MAP_PADCTL_A16_BASE 0x02440000
+#define NV_ADDRESS_MAP_PADCTL_A16_LIMIT 0x02440fff
+#define NV_ADDRESS_MAP_PADCTL_A16_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A16_HEADER arpadctl_EDP.h;arpadctl_EDP_scr.h
+
+#define NV_ADDRESS_MAP_PADCTL_A17_BASE 0x02441000
+#define NV_ADDRESS_MAP_PADCTL_A17_LIMIT 0x02441fff
+#define NV_ADDRESS_MAP_PADCTL_A17_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A17_HEADER arpadctl_UFS.h;arpadctl_UFS_scr.h
+
+#define NV_ADDRESS_MAP_PADCTL_A20_BASE 0x02444000
+#define NV_ADDRESS_MAP_PADCTL_A20_LIMIT 0x02444fff
+#define NV_ADDRESS_MAP_PADCTL_A20_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A20_HEADER arpadctl_PEX_CTL_2.h;arpadctl_PEX_CTL_2_scr.h
+
+#define NV_ADDRESS_MAP_PADCTL_A21_BASE 0x02445000
+#define NV_ADDRESS_MAP_PADCTL_A21_LIMIT 0x02445fff
+#define NV_ADDRESS_MAP_PADCTL_A21_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A21_HEADER arpadctl_EQOS.h;arpadctl_EQOS_scr.h
+
+#define NV_ADDRESS_MAP_PADCTL_A24_BASE 0x02448000
+#define NV_ADDRESS_MAP_PADCTL_A24_LIMIT 0x02448fff
+#define NV_ADDRESS_MAP_PADCTL_A24_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A24_HEADER arpadctl_G7.h;arpadctl_G7_scr.h
+
+#define NV_ADDRESS_MAP_PADCTL_A25_BASE 0x02449000
+#define NV_ADDRESS_MAP_PADCTL_A25_LIMIT 0x02449fff
+#define NV_ADDRESS_MAP_PADCTL_A25_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A25_HEADER arpadctl_PEX_CTL_3.h;arpadctl_PEX_CTL_3_scr.h
+
+#define NV_ADDRESS_MAP_I2S7_BASE 0x02450000
+#define NV_ADDRESS_MAP_I2S7_LIMIT 0x0245ffff
+#define NV_ADDRESS_MAP_I2S7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_I2S7_HEADER arsafety_i2s.h
+
+#define NV_ADDRESS_MAP_I2S8_BASE 0x02460000
+#define NV_ADDRESS_MAP_I2S8_LIMIT 0x0246ffff
+#define NV_ADDRESS_MAP_I2S8_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_I2S8_HEADER arsafety_i2s.h
+
+#define NV_ADDRESS_MAP_MPHY_L0_BASE 0x02470000
+#define NV_ADDRESS_MAP_MPHY_L0_LIMIT 0x0247ffff
+#define NV_ADDRESS_MAP_MPHY_L0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MPHY_L0_HEADER armphy_tx_apb.h;armphy_rx_apb.h
+
+#define NV_ADDRESS_MAP_MPHY_L1_BASE 0x02480000
+#define NV_ADDRESS_MAP_MPHY_L1_LIMIT 0x0248ffff
+#define NV_ADDRESS_MAP_MPHY_L1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MPHY_L1_HEADER armphy_tx_apb.h;armphy_rx_apb.h
+
+#define NV_ADDRESS_MAP_MISC_ERR_COLLATOR_BASE 0x024e0000
+#define NV_ADDRESS_MAP_MISC_ERR_COLLATOR_LIMIT 0x024effff
+#define NV_ADDRESS_MAP_MISC_ERR_COLLATOR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MISC_ERR_COLLATOR_HEADER armisc_ec.h;armisc_ec_scr.h
+
+#define NV_ADDRESS_MAP_UFSHC_0_MMIO_BASE 0x02500000
+#define NV_ADDRESS_MAP_UFSHC_0_MMIO_LIMIT 0x0250ffff
+#define NV_ADDRESS_MAP_UFSHC_0_MMIO_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UFSHC_0_MMIO_HEADER arufshc_mmio_SNPS.h
+
+#define NV_ADDRESS_MAP_UFSHC_0_UNIPRO_AUX_BASE 0x02510000
+#define NV_ADDRESS_MAP_UFSHC_0_UNIPRO_AUX_LIMIT 0x02517fff
+#define NV_ADDRESS_MAP_UFSHC_0_UNIPRO_AUX_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UFSHC_0_UNIPRO_AUX_HEADER arufshc_aux_ctrl.h
+
+#define NV_ADDRESS_MAP_UFSHC_0_UNIPRO_FPGA_BASE 0x02518000
+#define NV_ADDRESS_MAP_UFSHC_0_UNIPRO_FPGA_LIMIT 0x0251ffff
+#define NV_ADDRESS_MAP_UFSHC_0_UNIPRO_FPGA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UFSHC_0_UNIPRO_FPGA_HEADER arufshc_fpga.h
+
+#define NV_ADDRESS_MAP_UFSHC_0_VIRT_BASE 0x02520000
+#define NV_ADDRESS_MAP_UFSHC_0_VIRT_LIMIT 0x0252ffff
+#define NV_ADDRESS_MAP_UFSHC_0_VIRT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UFSHC_0_VIRT_HEADER arufshc_virtualization.h
+
+#define NV_ADDRESS_MAP_GPCDMA_COMMON_0_BASE 0x02600000
+#define NV_ADDRESS_MAP_GPCDMA_COMMON_0_LIMIT 0x0260ffff
+#define NV_ADDRESS_MAP_GPCDMA_COMMON_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_COMMON_0_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH0_BASE 0x02610000
+#define NV_ADDRESS_MAP_GPCDMA_CH0_LIMIT 0x0261ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH0_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH1_BASE 0x02620000
+#define NV_ADDRESS_MAP_GPCDMA_CH1_LIMIT 0x0262ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH1_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH2_BASE 0x02630000
+#define NV_ADDRESS_MAP_GPCDMA_CH2_LIMIT 0x0263ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH2_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH3_BASE 0x02640000
+#define NV_ADDRESS_MAP_GPCDMA_CH3_LIMIT 0x0264ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH3_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH4_BASE 0x02650000
+#define NV_ADDRESS_MAP_GPCDMA_CH4_LIMIT 0x0265ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH4_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH5_BASE 0x02660000
+#define NV_ADDRESS_MAP_GPCDMA_CH5_LIMIT 0x0266ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH5_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH6_BASE 0x02670000
+#define NV_ADDRESS_MAP_GPCDMA_CH6_LIMIT 0x0267ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH6_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH7_BASE 0x02680000
+#define NV_ADDRESS_MAP_GPCDMA_CH7_LIMIT 0x0268ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH7_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH8_BASE 0x02690000
+#define NV_ADDRESS_MAP_GPCDMA_CH8_LIMIT 0x0269ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH8_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH8_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH9_BASE 0x026a0000
+#define NV_ADDRESS_MAP_GPCDMA_CH9_LIMIT 0x026affff
+#define NV_ADDRESS_MAP_GPCDMA_CH9_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH9_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH10_BASE 0x026b0000
+#define NV_ADDRESS_MAP_GPCDMA_CH10_LIMIT 0x026bffff
+#define NV_ADDRESS_MAP_GPCDMA_CH10_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH10_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH11_BASE 0x026c0000
+#define NV_ADDRESS_MAP_GPCDMA_CH11_LIMIT 0x026cffff
+#define NV_ADDRESS_MAP_GPCDMA_CH11_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH11_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH12_BASE 0x026d0000
+#define NV_ADDRESS_MAP_GPCDMA_CH12_LIMIT 0x026dffff
+#define NV_ADDRESS_MAP_GPCDMA_CH12_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH12_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH13_BASE 0x026e0000
+#define NV_ADDRESS_MAP_GPCDMA_CH13_LIMIT 0x026effff
+#define NV_ADDRESS_MAP_GPCDMA_CH13_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH13_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH14_BASE 0x026f0000
+#define NV_ADDRESS_MAP_GPCDMA_CH14_LIMIT 0x026fffff
+#define NV_ADDRESS_MAP_GPCDMA_CH14_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH14_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH15_BASE 0x02700000
+#define NV_ADDRESS_MAP_GPCDMA_CH15_LIMIT 0x0270ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH15_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH15_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH16_BASE 0x02710000
+#define NV_ADDRESS_MAP_GPCDMA_CH16_LIMIT 0x0271ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH16_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH16_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH17_BASE 0x02720000
+#define NV_ADDRESS_MAP_GPCDMA_CH17_LIMIT 0x0272ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH17_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH17_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH18_BASE 0x02730000
+#define NV_ADDRESS_MAP_GPCDMA_CH18_LIMIT 0x0273ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH18_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH18_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH19_BASE 0x02740000
+#define NV_ADDRESS_MAP_GPCDMA_CH19_LIMIT 0x0274ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH19_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH19_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH20_BASE 0x02750000
+#define NV_ADDRESS_MAP_GPCDMA_CH20_LIMIT 0x0275ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH20_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH20_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH21_BASE 0x02760000
+#define NV_ADDRESS_MAP_GPCDMA_CH21_LIMIT 0x0276ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH21_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH21_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH22_BASE 0x02770000
+#define NV_ADDRESS_MAP_GPCDMA_CH22_LIMIT 0x0277ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH22_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH22_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH23_BASE 0x02780000
+#define NV_ADDRESS_MAP_GPCDMA_CH23_LIMIT 0x0278ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH23_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH23_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH24_BASE 0x02790000
+#define NV_ADDRESS_MAP_GPCDMA_CH24_LIMIT 0x0279ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH24_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH24_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH25_BASE 0x027a0000
+#define NV_ADDRESS_MAP_GPCDMA_CH25_LIMIT 0x027affff
+#define NV_ADDRESS_MAP_GPCDMA_CH25_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH25_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH26_BASE 0x027b0000
+#define NV_ADDRESS_MAP_GPCDMA_CH26_LIMIT 0x027bffff
+#define NV_ADDRESS_MAP_GPCDMA_CH26_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH26_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH27_BASE 0x027c0000
+#define NV_ADDRESS_MAP_GPCDMA_CH27_LIMIT 0x027cffff
+#define NV_ADDRESS_MAP_GPCDMA_CH27_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH27_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH28_BASE 0x027d0000
+#define NV_ADDRESS_MAP_GPCDMA_CH28_LIMIT 0x027dffff
+#define NV_ADDRESS_MAP_GPCDMA_CH28_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH28_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH29_BASE 0x027e0000
+#define NV_ADDRESS_MAP_GPCDMA_CH29_LIMIT 0x027effff
+#define NV_ADDRESS_MAP_GPCDMA_CH29_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH29_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH30_BASE 0x027f0000
+#define NV_ADDRESS_MAP_GPCDMA_CH30_LIMIT 0x027fffff
+#define NV_ADDRESS_MAP_GPCDMA_CH30_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH30_HEADER
+
+#define NV_ADDRESS_MAP_GPCDMA_CH31_BASE 0x02800000
+#define NV_ADDRESS_MAP_GPCDMA_CH31_LIMIT 0x0280ffff
+#define NV_ADDRESS_MAP_GPCDMA_CH31_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPCDMA_CH31_HEADER
+
+#define NV_ADDRESS_MAP_AXBAR_BASE 0x02900800
+#define NV_ADDRESS_MAP_AXBAR_LIMIT 0x02900fff
+#define NV_ADDRESS_MAP_AXBAR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AXBAR_HEADER araxbar.h
+
+#define NV_ADDRESS_MAP_I2S1_BASE 0x02901000
+#define NV_ADDRESS_MAP_I2S1_LIMIT 0x029010ff
+#define NV_ADDRESS_MAP_I2S1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_I2S1_HEADER ari2s.h
+
+#define NV_ADDRESS_MAP_I2S2_BASE 0x02901100
+#define NV_ADDRESS_MAP_I2S2_LIMIT 0x029011ff
+#define NV_ADDRESS_MAP_I2S2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_I2S2_HEADER ari2s.h
+
+#define NV_ADDRESS_MAP_I2S3_BASE 0x02901200
+#define NV_ADDRESS_MAP_I2S3_LIMIT 0x029012ff
+#define NV_ADDRESS_MAP_I2S3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_I2S3_HEADER ari2s.h
+
+#define NV_ADDRESS_MAP_I2S4_BASE 0x02901300
+#define NV_ADDRESS_MAP_I2S4_LIMIT 0x029013ff
+#define NV_ADDRESS_MAP_I2S4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_I2S4_HEADER ari2s.h
+
+#define NV_ADDRESS_MAP_I2S5_BASE 0x02901400
+#define NV_ADDRESS_MAP_I2S5_LIMIT 0x029014ff
+#define NV_ADDRESS_MAP_I2S5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_I2S5_HEADER ari2s.h
+
+#define NV_ADDRESS_MAP_I2S6_BASE 0x02901500
+#define NV_ADDRESS_MAP_I2S6_LIMIT 0x029015ff
+#define NV_ADDRESS_MAP_I2S6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_I2S6_HEADER ari2s.h
+
+#define NV_ADDRESS_MAP_SFC1_BASE 0x02902000
+#define NV_ADDRESS_MAP_SFC1_LIMIT 0x029021ff
+#define NV_ADDRESS_MAP_SFC1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SFC1_HEADER arsfc.h
+
+#define NV_ADDRESS_MAP_SFC2_BASE 0x02902200
+#define NV_ADDRESS_MAP_SFC2_LIMIT 0x029023ff
+#define NV_ADDRESS_MAP_SFC2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SFC2_HEADER arsfc.h
+
+#define NV_ADDRESS_MAP_SFC3_BASE 0x02902400
+#define NV_ADDRESS_MAP_SFC3_LIMIT 0x029025ff
+#define NV_ADDRESS_MAP_SFC3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SFC3_HEADER arsfc.h
+
+#define NV_ADDRESS_MAP_SFC4_BASE 0x02902600
+#define NV_ADDRESS_MAP_SFC4_LIMIT 0x029027ff
+#define NV_ADDRESS_MAP_SFC4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SFC4_HEADER arsfc.h
+
+#define NV_ADDRESS_MAP_AMX1_BASE 0x02903000
+#define NV_ADDRESS_MAP_AMX1_LIMIT 0x029030ff
+#define NV_ADDRESS_MAP_AMX1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AMX1_HEADER aramx.h
+
+#define NV_ADDRESS_MAP_AMX2_BASE 0x02903100
+#define NV_ADDRESS_MAP_AMX2_LIMIT 0x029031ff
+#define NV_ADDRESS_MAP_AMX2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AMX2_HEADER aramx.h
+
+#define NV_ADDRESS_MAP_AMX3_BASE 0x02903200
+#define NV_ADDRESS_MAP_AMX3_LIMIT 0x029032ff
+#define NV_ADDRESS_MAP_AMX3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AMX3_HEADER aramx.h
+
+#define NV_ADDRESS_MAP_AMX4_BASE 0x02903300
+#define NV_ADDRESS_MAP_AMX4_LIMIT 0x029033ff
+#define NV_ADDRESS_MAP_AMX4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AMX4_HEADER aramx.h
+
+#define NV_ADDRESS_MAP_ADX1_BASE 0x02903800
+#define NV_ADDRESS_MAP_ADX1_LIMIT 0x029038ff
+#define NV_ADDRESS_MAP_ADX1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_ADX1_HEADER aradx.h
+
+#define NV_ADDRESS_MAP_ADX2_BASE 0x02903900
+#define NV_ADDRESS_MAP_ADX2_LIMIT 0x029039ff
+#define NV_ADDRESS_MAP_ADX2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_ADX2_HEADER aradx.h
+
+#define NV_ADDRESS_MAP_ADX3_BASE 0x02903a00
+#define NV_ADDRESS_MAP_ADX3_LIMIT 0x02903aff
+#define NV_ADDRESS_MAP_ADX3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_ADX3_HEADER aradx.h
+
+#define NV_ADDRESS_MAP_ADX4_BASE 0x02903b00
+#define NV_ADDRESS_MAP_ADX4_LIMIT 0x02903bff
+#define NV_ADDRESS_MAP_ADX4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_ADX4_HEADER aradx.h
+
+#define NV_ADDRESS_MAP_DMIC1_BASE 0x02904000
+#define NV_ADDRESS_MAP_DMIC1_LIMIT 0x029040ff
+#define NV_ADDRESS_MAP_DMIC1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DMIC1_HEADER ardmic.h
+
+#define NV_ADDRESS_MAP_DMIC2_BASE 0x02904100
+#define NV_ADDRESS_MAP_DMIC2_LIMIT 0x029041ff
+#define NV_ADDRESS_MAP_DMIC2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DMIC2_HEADER ardmic.h
+
+#define NV_ADDRESS_MAP_DMIC3_BASE 0x02904200
+#define NV_ADDRESS_MAP_DMIC3_LIMIT 0x029042ff
+#define NV_ADDRESS_MAP_DMIC3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DMIC3_HEADER ardmic.h
+
+#define NV_ADDRESS_MAP_DMIC4_BASE 0x02904300
+#define NV_ADDRESS_MAP_DMIC4_LIMIT 0x029043ff
+#define NV_ADDRESS_MAP_DMIC4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DMIC4_HEADER ardmic.h
+
+#define NV_ADDRESS_MAP_DSPK1_BASE 0x02905000
+#define NV_ADDRESS_MAP_DSPK1_LIMIT 0x029050ff
+#define NV_ADDRESS_MAP_DSPK1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DSPK1_HEADER ardspk.h
+
+#define NV_ADDRESS_MAP_DSPK2_BASE 0x02905100
+#define NV_ADDRESS_MAP_DSPK2_LIMIT 0x029051ff
+#define NV_ADDRESS_MAP_DSPK2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DSPK2_HEADER ardspk.h
+
+#define NV_ADDRESS_MAP_SPDIF1_BASE 0x02906000
+#define NV_ADDRESS_MAP_SPDIF1_LIMIT 0x029061ff
+#define NV_ADDRESS_MAP_SPDIF1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SPDIF1_HEADER arspdif.h
+
+#define NV_ADDRESS_MAP_AFC1_BASE 0x02907000
+#define NV_ADDRESS_MAP_AFC1_LIMIT 0x029070ff
+#define NV_ADDRESS_MAP_AFC1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AFC1_HEADER arafc.h
+
+#define NV_ADDRESS_MAP_AFC2_BASE 0x02907100
+#define NV_ADDRESS_MAP_AFC2_LIMIT 0x029071ff
+#define NV_ADDRESS_MAP_AFC2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AFC2_HEADER arafc.h
+
+#define NV_ADDRESS_MAP_AFC3_BASE 0x02907200
+#define NV_ADDRESS_MAP_AFC3_LIMIT 0x029072ff
+#define NV_ADDRESS_MAP_AFC3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AFC3_HEADER arafc.h
+
+#define NV_ADDRESS_MAP_AFC4_BASE 0x02907300
+#define NV_ADDRESS_MAP_AFC4_LIMIT 0x029073ff
+#define NV_ADDRESS_MAP_AFC4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AFC4_HEADER arafc.h
+
+#define NV_ADDRESS_MAP_AFC5_BASE 0x02907400
+#define NV_ADDRESS_MAP_AFC5_LIMIT 0x029074ff
+#define NV_ADDRESS_MAP_AFC5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AFC5_HEADER arafc.h
+
+#define NV_ADDRESS_MAP_AFC6_BASE 0x02907500
+#define NV_ADDRESS_MAP_AFC6_LIMIT 0x029075ff
+#define NV_ADDRESS_MAP_AFC6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AFC6_HEADER arafc.h
+
+#define NV_ADDRESS_MAP_OPE1_COMMON_BASE 0x02908000
+#define NV_ADDRESS_MAP_OPE1_COMMON_LIMIT 0x029080ff
+#define NV_ADDRESS_MAP_OPE1_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_OPE1_COMMON_HEADER arope.h
+
+#define NV_ADDRESS_MAP_OPE1_PEQ_BASE 0x02908100
+#define NV_ADDRESS_MAP_OPE1_PEQ_LIMIT 0x029081ff
+#define NV_ADDRESS_MAP_OPE1_PEQ_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_OPE1_PEQ_HEADER arpeq.h
+
+#define NV_ADDRESS_MAP_OPE1_MBDRC_BASE 0x02908200
+#define NV_ADDRESS_MAP_OPE1_MBDRC_LIMIT 0x029083ff
+#define NV_ADDRESS_MAP_OPE1_MBDRC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_OPE1_MBDRC_HEADER armbdrc.h
+
+#define NV_ADDRESS_MAP_SPKPROT1_BASE 0x02908c00
+#define NV_ADDRESS_MAP_SPKPROT1_LIMIT 0x02908fff
+#define NV_ADDRESS_MAP_SPKPROT1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SPKPROT1_HEADER
+
+#define NV_ADDRESS_MAP_MVC1_BASE 0x0290a000
+#define NV_ADDRESS_MAP_MVC1_LIMIT 0x0290a1ff
+#define NV_ADDRESS_MAP_MVC1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MVC1_HEADER armvc.h
+
+#define NV_ADDRESS_MAP_MVC2_BASE 0x0290a200
+#define NV_ADDRESS_MAP_MVC2_LIMIT 0x0290a3ff
+#define NV_ADDRESS_MAP_MVC2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MVC2_HEADER armvc.h
+
+#define NV_ADDRESS_MAP_AHC_BASE 0x0290b900
+#define NV_ADDRESS_MAP_AHC_LIMIT 0x0290baff
+#define NV_ADDRESS_MAP_AHC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AHC_HEADER arahc.h
+
+#define NV_ADDRESS_MAP_MIXER1_BASE 0x0290bb00
+#define NV_ADDRESS_MAP_MIXER1_LIMIT 0x0290c2ff
+#define NV_ADDRESS_MAP_MIXER1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MIXER1_HEADER armixer.h
+
+#define NV_ADDRESS_MAP_IQC1_BASE 0x0290e000
+#define NV_ADDRESS_MAP_IQC1_LIMIT 0x0290e1ff
+#define NV_ADDRESS_MAP_IQC1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_IQC1_HEADER
+
+#define NV_ADDRESS_MAP_IQC2_BASE 0x0290e200
+#define NV_ADDRESS_MAP_IQC2_LIMIT 0x0290e3ff
+#define NV_ADDRESS_MAP_IQC2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_IQC2_HEADER
+
+#define NV_ADDRESS_MAP_ARAD_BASE 0x0290e400
+#define NV_ADDRESS_MAP_ARAD_LIMIT 0x0290e7ff
+#define NV_ADDRESS_MAP_ARAD_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_ARAD_HEADER ararad.h
+
+#define NV_ADDRESS_MAP_ADMAIF_BASE 0x0290f000
+#define NV_ADDRESS_MAP_ADMAIF_LIMIT 0x0290ffff
+#define NV_ADDRESS_MAP_ADMAIF_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_ADMAIF_HEADER aradmaif.h
+
+#define NV_ADDRESS_MAP_ASRC_BASE 0x02910000
+#define NV_ADDRESS_MAP_ASRC_LIMIT 0x02911fff
+#define NV_ADDRESS_MAP_ASRC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_ASRC_HEADER arasrc.h
+
+#define NV_ADDRESS_MAP_APE_ADMA_GLOBAL_BASE 0x02930000
+#define NV_ADDRESS_MAP_APE_ADMA_GLOBAL_LIMIT 0x0293ffff
+#define NV_ADDRESS_MAP_APE_ADMA_GLOBAL_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_ADMA_GLOBAL_HEADER
+
+#define NV_ADDRESS_MAP_APE_ADMA_PAGE1_BASE 0x02940000
+#define NV_ADDRESS_MAP_APE_ADMA_PAGE1_LIMIT 0x0294ffff
+#define NV_ADDRESS_MAP_APE_ADMA_PAGE1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_ADMA_PAGE1_HEADER
+
+#define NV_ADDRESS_MAP_APE_ADMA_PAGE2_BASE 0x02950000
+#define NV_ADDRESS_MAP_APE_ADMA_PAGE2_LIMIT 0x0295ffff
+#define NV_ADDRESS_MAP_APE_ADMA_PAGE2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_ADMA_PAGE2_HEADER
+
+#define NV_ADDRESS_MAP_APE_ADMA_PAGE3_BASE 0x02960000
+#define NV_ADDRESS_MAP_APE_ADMA_PAGE3_LIMIT 0x0296ffff
+#define NV_ADDRESS_MAP_APE_ADMA_PAGE3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_ADMA_PAGE3_HEADER
+
+#define NV_ADDRESS_MAP_APE_ADMA_PAGE4_BASE 0x02970000
+#define NV_ADDRESS_MAP_APE_ADMA_PAGE4_LIMIT 0x0297ffff
+#define NV_ADDRESS_MAP_APE_ADMA_PAGE4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_ADMA_PAGE4_HEADER
+
+#define NV_ADDRESS_MAP_APE_AMISC_AMISC_BASE 0x02990000
+#define NV_ADDRESS_MAP_APE_AMISC_AMISC_LIMIT 0x029907ff
+#define NV_ADDRESS_MAP_APE_AMISC_AMISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_AMISC_AMISC_HEADER aramisc.h
+
+#define NV_ADDRESS_MAP_APE_AMISC_ACTMON_BASE 0x02990800
+#define NV_ADDRESS_MAP_APE_AMISC_ACTMON_LIMIT 0x02990bff
+#define NV_ADDRESS_MAP_APE_AMISC_ACTMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_AMISC_ACTMON_HEADER arunit_actmon.h
+
+#define NV_ADDRESS_MAP_APE_AMC_BASE 0x02993000
+#define NV_ADDRESS_MAP_APE_AMC_LIMIT 0x02993fff
+#define NV_ADDRESS_MAP_APE_AMC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_AMC_HEADER aramc.h
+
+#define NV_ADDRESS_MAP_APE_ACAST_BASE 0x02994000
+#define NV_ADDRESS_MAP_APE_ACAST_LIMIT 0x02995fff
+#define NV_ADDRESS_MAP_APE_ACAST_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_ACAST_HEADER araps_ast.h;araps_ast_scr.h
+
+#define NV_ADDRESS_MAP_APE_ADAST_BASE 0x02996000
+#define NV_ADDRESS_MAP_APE_ADAST_LIMIT 0x02997fff
+#define NV_ADDRESS_MAP_APE_ADAST_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_ADAST_HEADER araps_ast.h;araps_ast_scr.h
+
+#define NV_ADDRESS_MAP_APE_HSP_COMMON_BASE 0x029a0000
+#define NV_ADDRESS_MAP_APE_HSP_COMMON_LIMIT 0x029affff
+#define NV_ADDRESS_MAP_APE_HSP_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_HSP_COMMON_HEADER arhsp_int.h;arhsp_int_scr.h
+
+#define NV_ADDRESS_MAP_APE_HSP_SM_0_1_BASE 0x029b0000
+#define NV_ADDRESS_MAP_APE_HSP_SM_0_1_LIMIT 0x029bffff
+#define NV_ADDRESS_MAP_APE_HSP_SM_0_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_HSP_SM_0_1_HEADER
+
+#define NV_ADDRESS_MAP_APE_HSP_SM_2_3_BASE 0x029c0000
+#define NV_ADDRESS_MAP_APE_HSP_SM_2_3_LIMIT 0x029cffff
+#define NV_ADDRESS_MAP_APE_HSP_SM_2_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_HSP_SM_2_3_HEADER
+
+#define NV_ADDRESS_MAP_APE_HSP_SM_4_5_BASE 0x029d0000
+#define NV_ADDRESS_MAP_APE_HSP_SM_4_5_LIMIT 0x029dffff
+#define NV_ADDRESS_MAP_APE_HSP_SM_4_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_HSP_SM_4_5_HEADER
+
+#define NV_ADDRESS_MAP_APE_HSP_SM_6_7_BASE 0x029e0000
+#define NV_ADDRESS_MAP_APE_HSP_SM_6_7_LIMIT 0x029effff
+#define NV_ADDRESS_MAP_APE_HSP_SM_6_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_HSP_SM_6_7_HEADER
+
+#define NV_ADDRESS_MAP_APE_HSP_SS_0_BASE 0x029f0000
+#define NV_ADDRESS_MAP_APE_HSP_SS_0_LIMIT 0x029fffff
+#define NV_ADDRESS_MAP_APE_HSP_SS_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_HSP_SS_0_HEADER
+
+#define NV_ADDRESS_MAP_APE_HSP_SS_1_BASE 0x02a00000
+#define NV_ADDRESS_MAP_APE_HSP_SS_1_LIMIT 0x02a0ffff
+#define NV_ADDRESS_MAP_APE_HSP_SS_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_HSP_SS_1_HEADER
+
+#define NV_ADDRESS_MAP_APE_HSP_SS_2_BASE 0x02a10000
+#define NV_ADDRESS_MAP_APE_HSP_SS_2_LIMIT 0x02a1ffff
+#define NV_ADDRESS_MAP_APE_HSP_SS_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_HSP_SS_2_HEADER
+
+#define NV_ADDRESS_MAP_APE_HSP_SS_3_BASE 0x02a20000
+#define NV_ADDRESS_MAP_APE_HSP_SS_3_LIMIT 0x02a2ffff
+#define NV_ADDRESS_MAP_APE_HSP_SS_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_HSP_SS_3_HEADER
+
+#define NV_ADDRESS_MAP_APE_AGIC_PAGE0_BASE 0x02a40000
+#define NV_ADDRESS_MAP_APE_AGIC_PAGE0_LIMIT 0x02a4ffff
+#define NV_ADDRESS_MAP_APE_AGIC_PAGE0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_AGIC_PAGE0_HEADER aragic.h
+
+#define NV_ADDRESS_MAP_APE_AGIC_PAGE1_BASE 0x02a50000
+#define NV_ADDRESS_MAP_APE_AGIC_PAGE1_LIMIT 0x02a5ffff
+#define NV_ADDRESS_MAP_APE_AGIC_PAGE1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_AGIC_PAGE1_HEADER aragic.h
+
+#define NV_ADDRESS_MAP_APE_AGIC_PAGE2_BASE 0x02a60000
+#define NV_ADDRESS_MAP_APE_AGIC_PAGE2_LIMIT 0x02a6ffff
+#define NV_ADDRESS_MAP_APE_AGIC_PAGE2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_AGIC_PAGE2_HEADER aragic.h
+
+#define NV_ADDRESS_MAP_APE_AGIC_PAGE3_BASE 0x02a70000
+#define NV_ADDRESS_MAP_APE_AGIC_PAGE3_LIMIT 0x02a7ffff
+#define NV_ADDRESS_MAP_APE_AGIC_PAGE3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_AGIC_PAGE3_HEADER aragic.h
+
+#define NV_ADDRESS_MAP_APE_TKE_SHARED_BASE 0x02a80000
+#define NV_ADDRESS_MAP_APE_TKE_SHARED_LIMIT 0x02a8ffff
+#define NV_ADDRESS_MAP_APE_TKE_SHARED_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_TKE_SHARED_HEADER
+
+#define NV_ADDRESS_MAP_APE_TKE_TMR_0_BASE 0x02a90000
+#define NV_ADDRESS_MAP_APE_TKE_TMR_0_LIMIT 0x02a9ffff
+#define NV_ADDRESS_MAP_APE_TKE_TMR_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_TKE_TMR_0_HEADER
+
+#define NV_ADDRESS_MAP_APE_TKE_TMR_1_BASE 0x02aa0000
+#define NV_ADDRESS_MAP_APE_TKE_TMR_1_LIMIT 0x02aaffff
+#define NV_ADDRESS_MAP_APE_TKE_TMR_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_TKE_TMR_1_HEADER
+
+#define NV_ADDRESS_MAP_APE_TKE_TMR_2_BASE 0x02ab0000
+#define NV_ADDRESS_MAP_APE_TKE_TMR_2_LIMIT 0x02abffff
+#define NV_ADDRESS_MAP_APE_TKE_TMR_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_TKE_TMR_2_HEADER
+
+#define NV_ADDRESS_MAP_APE_TKE_TMR_3_BASE 0x02ac0000
+#define NV_ADDRESS_MAP_APE_TKE_TMR_3_LIMIT 0x02acffff
+#define NV_ADDRESS_MAP_APE_TKE_TMR_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_TKE_TMR_3_HEADER
+
+#define NV_ADDRESS_MAP_APE_TKE_WDT_0_BASE 0x02ad0000
+#define NV_ADDRESS_MAP_APE_TKE_WDT_0_LIMIT 0x02adffff
+#define NV_ADDRESS_MAP_APE_TKE_WDT_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_APE_TKE_WDT_0_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_128_BASE 0x02b00000
+#define NV_ADDRESS_MAP_TSA_NODE_128_LIMIT 0x02b00fff
+#define NV_ADDRESS_MAP_TSA_NODE_128_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_128_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_129_BASE 0x02b01000
+#define NV_ADDRESS_MAP_TSA_NODE_129_LIMIT 0x02b01fff
+#define NV_ADDRESS_MAP_TSA_NODE_129_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_129_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_130_BASE 0x02b02000
+#define NV_ADDRESS_MAP_TSA_NODE_130_LIMIT 0x02b02fff
+#define NV_ADDRESS_MAP_TSA_NODE_130_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_130_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_131_BASE 0x02b03000
+#define NV_ADDRESS_MAP_TSA_NODE_131_LIMIT 0x02b03fff
+#define NV_ADDRESS_MAP_TSA_NODE_131_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_131_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_132_BASE 0x02b04000
+#define NV_ADDRESS_MAP_TSA_NODE_132_LIMIT 0x02b04fff
+#define NV_ADDRESS_MAP_TSA_NODE_132_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_132_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_133_BASE 0x02b05000
+#define NV_ADDRESS_MAP_TSA_NODE_133_LIMIT 0x02b05fff
+#define NV_ADDRESS_MAP_TSA_NODE_133_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_133_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_134_BASE 0x02b06000
+#define NV_ADDRESS_MAP_TSA_NODE_134_LIMIT 0x02b06fff
+#define NV_ADDRESS_MAP_TSA_NODE_134_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_134_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_135_BASE 0x02b07000
+#define NV_ADDRESS_MAP_TSA_NODE_135_LIMIT 0x02b07fff
+#define NV_ADDRESS_MAP_TSA_NODE_135_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_135_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_136_BASE 0x02b08000
+#define NV_ADDRESS_MAP_TSA_NODE_136_LIMIT 0x02b08fff
+#define NV_ADDRESS_MAP_TSA_NODE_136_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_136_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_137_BASE 0x02b09000
+#define NV_ADDRESS_MAP_TSA_NODE_137_LIMIT 0x02b09fff
+#define NV_ADDRESS_MAP_TSA_NODE_137_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_137_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_138_BASE 0x02b0a000
+#define NV_ADDRESS_MAP_TSA_NODE_138_LIMIT 0x02b0afff
+#define NV_ADDRESS_MAP_TSA_NODE_138_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_138_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_139_BASE 0x02b0b000
+#define NV_ADDRESS_MAP_TSA_NODE_139_LIMIT 0x02b0bfff
+#define NV_ADDRESS_MAP_TSA_NODE_139_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_139_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_140_BASE 0x02b0c000
+#define NV_ADDRESS_MAP_TSA_NODE_140_LIMIT 0x02b0cfff
+#define NV_ADDRESS_MAP_TSA_NODE_140_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_140_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_141_BASE 0x02b0d000
+#define NV_ADDRESS_MAP_TSA_NODE_141_LIMIT 0x02b0dfff
+#define NV_ADDRESS_MAP_TSA_NODE_141_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_141_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_142_BASE 0x02b0e000
+#define NV_ADDRESS_MAP_TSA_NODE_142_LIMIT 0x02b0efff
+#define NV_ADDRESS_MAP_TSA_NODE_142_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_142_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_143_BASE 0x02b0f000
+#define NV_ADDRESS_MAP_TSA_NODE_143_LIMIT 0x02b0ffff
+#define NV_ADDRESS_MAP_TSA_NODE_143_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_143_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_144_BASE 0x02b10000
+#define NV_ADDRESS_MAP_TSA_NODE_144_LIMIT 0x02b10fff
+#define NV_ADDRESS_MAP_TSA_NODE_144_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_144_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_145_BASE 0x02b11000
+#define NV_ADDRESS_MAP_TSA_NODE_145_LIMIT 0x02b11fff
+#define NV_ADDRESS_MAP_TSA_NODE_145_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_145_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_146_BASE 0x02b12000
+#define NV_ADDRESS_MAP_TSA_NODE_146_LIMIT 0x02b12fff
+#define NV_ADDRESS_MAP_TSA_NODE_146_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_146_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_147_BASE 0x02b13000
+#define NV_ADDRESS_MAP_TSA_NODE_147_LIMIT 0x02b13fff
+#define NV_ADDRESS_MAP_TSA_NODE_147_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_147_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_148_BASE 0x02b14000
+#define NV_ADDRESS_MAP_TSA_NODE_148_LIMIT 0x02b14fff
+#define NV_ADDRESS_MAP_TSA_NODE_148_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_148_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_149_BASE 0x02b15000
+#define NV_ADDRESS_MAP_TSA_NODE_149_LIMIT 0x02b15fff
+#define NV_ADDRESS_MAP_TSA_NODE_149_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_149_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_150_BASE 0x02b16000
+#define NV_ADDRESS_MAP_TSA_NODE_150_LIMIT 0x02b16fff
+#define NV_ADDRESS_MAP_TSA_NODE_150_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_150_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_151_BASE 0x02b17000
+#define NV_ADDRESS_MAP_TSA_NODE_151_LIMIT 0x02b17fff
+#define NV_ADDRESS_MAP_TSA_NODE_151_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_151_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_152_BASE 0x02b18000
+#define NV_ADDRESS_MAP_TSA_NODE_152_LIMIT 0x02b18fff
+#define NV_ADDRESS_MAP_TSA_NODE_152_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_152_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_153_BASE 0x02b19000
+#define NV_ADDRESS_MAP_TSA_NODE_153_LIMIT 0x02b19fff
+#define NV_ADDRESS_MAP_TSA_NODE_153_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_153_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_154_BASE 0x02b1a000
+#define NV_ADDRESS_MAP_TSA_NODE_154_LIMIT 0x02b1afff
+#define NV_ADDRESS_MAP_TSA_NODE_154_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_154_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_155_BASE 0x02b1b000
+#define NV_ADDRESS_MAP_TSA_NODE_155_LIMIT 0x02b1bfff
+#define NV_ADDRESS_MAP_TSA_NODE_155_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_155_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_156_BASE 0x02b1c000
+#define NV_ADDRESS_MAP_TSA_NODE_156_LIMIT 0x02b1cfff
+#define NV_ADDRESS_MAP_TSA_NODE_156_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_156_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_157_BASE 0x02b1d000
+#define NV_ADDRESS_MAP_TSA_NODE_157_LIMIT 0x02b1dfff
+#define NV_ADDRESS_MAP_TSA_NODE_157_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_157_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_158_BASE 0x02b1e000
+#define NV_ADDRESS_MAP_TSA_NODE_158_LIMIT 0x02b1efff
+#define NV_ADDRESS_MAP_TSA_NODE_158_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_158_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_159_BASE 0x02b1f000
+#define NV_ADDRESS_MAP_TSA_NODE_159_LIMIT 0x02b1ffff
+#define NV_ADDRESS_MAP_TSA_NODE_159_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_159_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_160_BASE 0x02b20000
+#define NV_ADDRESS_MAP_TSA_NODE_160_LIMIT 0x02b20fff
+#define NV_ADDRESS_MAP_TSA_NODE_160_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_160_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_161_BASE 0x02b21000
+#define NV_ADDRESS_MAP_TSA_NODE_161_LIMIT 0x02b21fff
+#define NV_ADDRESS_MAP_TSA_NODE_161_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_161_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_162_BASE 0x02b22000
+#define NV_ADDRESS_MAP_TSA_NODE_162_LIMIT 0x02b22fff
+#define NV_ADDRESS_MAP_TSA_NODE_162_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_162_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_163_BASE 0x02b23000
+#define NV_ADDRESS_MAP_TSA_NODE_163_LIMIT 0x02b23fff
+#define NV_ADDRESS_MAP_TSA_NODE_163_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_163_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_164_BASE 0x02b24000
+#define NV_ADDRESS_MAP_TSA_NODE_164_LIMIT 0x02b24fff
+#define NV_ADDRESS_MAP_TSA_NODE_164_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_164_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_165_BASE 0x02b25000
+#define NV_ADDRESS_MAP_TSA_NODE_165_LIMIT 0x02b25fff
+#define NV_ADDRESS_MAP_TSA_NODE_165_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_165_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_166_BASE 0x02b26000
+#define NV_ADDRESS_MAP_TSA_NODE_166_LIMIT 0x02b26fff
+#define NV_ADDRESS_MAP_TSA_NODE_166_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_166_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_167_BASE 0x02b27000
+#define NV_ADDRESS_MAP_TSA_NODE_167_LIMIT 0x02b27fff
+#define NV_ADDRESS_MAP_TSA_NODE_167_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_167_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_168_BASE 0x02b28000
+#define NV_ADDRESS_MAP_TSA_NODE_168_LIMIT 0x02b28fff
+#define NV_ADDRESS_MAP_TSA_NODE_168_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_168_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_169_BASE 0x02b29000
+#define NV_ADDRESS_MAP_TSA_NODE_169_LIMIT 0x02b29fff
+#define NV_ADDRESS_MAP_TSA_NODE_169_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_169_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_170_BASE 0x02b2a000
+#define NV_ADDRESS_MAP_TSA_NODE_170_LIMIT 0x02b2afff
+#define NV_ADDRESS_MAP_TSA_NODE_170_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_170_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_171_BASE 0x02b2b000
+#define NV_ADDRESS_MAP_TSA_NODE_171_LIMIT 0x02b2bfff
+#define NV_ADDRESS_MAP_TSA_NODE_171_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_171_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_172_BASE 0x02b2c000
+#define NV_ADDRESS_MAP_TSA_NODE_172_LIMIT 0x02b2cfff
+#define NV_ADDRESS_MAP_TSA_NODE_172_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_172_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_173_BASE 0x02b2d000
+#define NV_ADDRESS_MAP_TSA_NODE_173_LIMIT 0x02b2dfff
+#define NV_ADDRESS_MAP_TSA_NODE_173_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_173_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_174_BASE 0x02b2e000
+#define NV_ADDRESS_MAP_TSA_NODE_174_LIMIT 0x02b2efff
+#define NV_ADDRESS_MAP_TSA_NODE_174_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_174_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_175_BASE 0x02b2f000
+#define NV_ADDRESS_MAP_TSA_NODE_175_LIMIT 0x02b2ffff
+#define NV_ADDRESS_MAP_TSA_NODE_175_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_175_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_176_BASE 0x02b30000
+#define NV_ADDRESS_MAP_TSA_NODE_176_LIMIT 0x02b30fff
+#define NV_ADDRESS_MAP_TSA_NODE_176_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_176_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_177_BASE 0x02b31000
+#define NV_ADDRESS_MAP_TSA_NODE_177_LIMIT 0x02b31fff
+#define NV_ADDRESS_MAP_TSA_NODE_177_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_177_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_178_BASE 0x02b32000
+#define NV_ADDRESS_MAP_TSA_NODE_178_LIMIT 0x02b32fff
+#define NV_ADDRESS_MAP_TSA_NODE_178_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_178_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_179_BASE 0x02b33000
+#define NV_ADDRESS_MAP_TSA_NODE_179_LIMIT 0x02b33fff
+#define NV_ADDRESS_MAP_TSA_NODE_179_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_179_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_180_BASE 0x02b34000
+#define NV_ADDRESS_MAP_TSA_NODE_180_LIMIT 0x02b34fff
+#define NV_ADDRESS_MAP_TSA_NODE_180_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_180_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_181_BASE 0x02b35000
+#define NV_ADDRESS_MAP_TSA_NODE_181_LIMIT 0x02b35fff
+#define NV_ADDRESS_MAP_TSA_NODE_181_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_181_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_182_BASE 0x02b36000
+#define NV_ADDRESS_MAP_TSA_NODE_182_LIMIT 0x02b36fff
+#define NV_ADDRESS_MAP_TSA_NODE_182_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_182_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_183_BASE 0x02b37000
+#define NV_ADDRESS_MAP_TSA_NODE_183_LIMIT 0x02b37fff
+#define NV_ADDRESS_MAP_TSA_NODE_183_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_183_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_184_BASE 0x02b38000
+#define NV_ADDRESS_MAP_TSA_NODE_184_LIMIT 0x02b38fff
+#define NV_ADDRESS_MAP_TSA_NODE_184_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_184_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_185_BASE 0x02b39000
+#define NV_ADDRESS_MAP_TSA_NODE_185_LIMIT 0x02b39fff
+#define NV_ADDRESS_MAP_TSA_NODE_185_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_185_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_186_BASE 0x02b3a000
+#define NV_ADDRESS_MAP_TSA_NODE_186_LIMIT 0x02b3afff
+#define NV_ADDRESS_MAP_TSA_NODE_186_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_186_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_187_BASE 0x02b3b000
+#define NV_ADDRESS_MAP_TSA_NODE_187_LIMIT 0x02b3bfff
+#define NV_ADDRESS_MAP_TSA_NODE_187_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_187_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_188_BASE 0x02b3c000
+#define NV_ADDRESS_MAP_TSA_NODE_188_LIMIT 0x02b3cfff
+#define NV_ADDRESS_MAP_TSA_NODE_188_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_188_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_189_BASE 0x02b3d000
+#define NV_ADDRESS_MAP_TSA_NODE_189_LIMIT 0x02b3dfff
+#define NV_ADDRESS_MAP_TSA_NODE_189_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_189_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_190_BASE 0x02b3e000
+#define NV_ADDRESS_MAP_TSA_NODE_190_LIMIT 0x02b3efff
+#define NV_ADDRESS_MAP_TSA_NODE_190_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_190_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_191_BASE 0x02b3f000
+#define NV_ADDRESS_MAP_TSA_NODE_191_LIMIT 0x02b3ffff
+#define NV_ADDRESS_MAP_TSA_NODE_191_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_191_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_192_BASE 0x02b40000
+#define NV_ADDRESS_MAP_TSA_NODE_192_LIMIT 0x02b40fff
+#define NV_ADDRESS_MAP_TSA_NODE_192_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_192_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_193_BASE 0x02b41000
+#define NV_ADDRESS_MAP_TSA_NODE_193_LIMIT 0x02b41fff
+#define NV_ADDRESS_MAP_TSA_NODE_193_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_193_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_194_BASE 0x02b42000
+#define NV_ADDRESS_MAP_TSA_NODE_194_LIMIT 0x02b42fff
+#define NV_ADDRESS_MAP_TSA_NODE_194_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_194_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_195_BASE 0x02b43000
+#define NV_ADDRESS_MAP_TSA_NODE_195_LIMIT 0x02b43fff
+#define NV_ADDRESS_MAP_TSA_NODE_195_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_195_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_196_BASE 0x02b44000
+#define NV_ADDRESS_MAP_TSA_NODE_196_LIMIT 0x02b44fff
+#define NV_ADDRESS_MAP_TSA_NODE_196_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_196_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_197_BASE 0x02b45000
+#define NV_ADDRESS_MAP_TSA_NODE_197_LIMIT 0x02b45fff
+#define NV_ADDRESS_MAP_TSA_NODE_197_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_197_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_198_BASE 0x02b46000
+#define NV_ADDRESS_MAP_TSA_NODE_198_LIMIT 0x02b46fff
+#define NV_ADDRESS_MAP_TSA_NODE_198_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_198_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_199_BASE 0x02b47000
+#define NV_ADDRESS_MAP_TSA_NODE_199_LIMIT 0x02b47fff
+#define NV_ADDRESS_MAP_TSA_NODE_199_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_199_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_200_BASE 0x02b48000
+#define NV_ADDRESS_MAP_TSA_NODE_200_LIMIT 0x02b48fff
+#define NV_ADDRESS_MAP_TSA_NODE_200_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_200_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_201_BASE 0x02b49000
+#define NV_ADDRESS_MAP_TSA_NODE_201_LIMIT 0x02b49fff
+#define NV_ADDRESS_MAP_TSA_NODE_201_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_201_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_202_BASE 0x02b4a000
+#define NV_ADDRESS_MAP_TSA_NODE_202_LIMIT 0x02b4afff
+#define NV_ADDRESS_MAP_TSA_NODE_202_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_202_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_203_BASE 0x02b4b000
+#define NV_ADDRESS_MAP_TSA_NODE_203_LIMIT 0x02b4bfff
+#define NV_ADDRESS_MAP_TSA_NODE_203_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_203_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_204_BASE 0x02b4c000
+#define NV_ADDRESS_MAP_TSA_NODE_204_LIMIT 0x02b4cfff
+#define NV_ADDRESS_MAP_TSA_NODE_204_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_204_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_205_BASE 0x02b4d000
+#define NV_ADDRESS_MAP_TSA_NODE_205_LIMIT 0x02b4dfff
+#define NV_ADDRESS_MAP_TSA_NODE_205_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_205_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_206_BASE 0x02b4e000
+#define NV_ADDRESS_MAP_TSA_NODE_206_LIMIT 0x02b4efff
+#define NV_ADDRESS_MAP_TSA_NODE_206_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_206_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_207_BASE 0x02b4f000
+#define NV_ADDRESS_MAP_TSA_NODE_207_LIMIT 0x02b4ffff
+#define NV_ADDRESS_MAP_TSA_NODE_207_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_207_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_208_BASE 0x02b50000
+#define NV_ADDRESS_MAP_TSA_NODE_208_LIMIT 0x02b50fff
+#define NV_ADDRESS_MAP_TSA_NODE_208_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_208_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_209_BASE 0x02b51000
+#define NV_ADDRESS_MAP_TSA_NODE_209_LIMIT 0x02b51fff
+#define NV_ADDRESS_MAP_TSA_NODE_209_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_209_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_210_BASE 0x02b52000
+#define NV_ADDRESS_MAP_TSA_NODE_210_LIMIT 0x02b52fff
+#define NV_ADDRESS_MAP_TSA_NODE_210_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_210_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_211_BASE 0x02b53000
+#define NV_ADDRESS_MAP_TSA_NODE_211_LIMIT 0x02b53fff
+#define NV_ADDRESS_MAP_TSA_NODE_211_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_211_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_212_BASE 0x02b54000
+#define NV_ADDRESS_MAP_TSA_NODE_212_LIMIT 0x02b54fff
+#define NV_ADDRESS_MAP_TSA_NODE_212_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_212_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_213_BASE 0x02b55000
+#define NV_ADDRESS_MAP_TSA_NODE_213_LIMIT 0x02b55fff
+#define NV_ADDRESS_MAP_TSA_NODE_213_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_213_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_214_BASE 0x02b56000
+#define NV_ADDRESS_MAP_TSA_NODE_214_LIMIT 0x02b56fff
+#define NV_ADDRESS_MAP_TSA_NODE_214_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_214_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_215_BASE 0x02b57000
+#define NV_ADDRESS_MAP_TSA_NODE_215_LIMIT 0x02b57fff
+#define NV_ADDRESS_MAP_TSA_NODE_215_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_215_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_216_BASE 0x02b58000
+#define NV_ADDRESS_MAP_TSA_NODE_216_LIMIT 0x02b58fff
+#define NV_ADDRESS_MAP_TSA_NODE_216_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_216_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_217_BASE 0x02b59000
+#define NV_ADDRESS_MAP_TSA_NODE_217_LIMIT 0x02b59fff
+#define NV_ADDRESS_MAP_TSA_NODE_217_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_217_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_218_BASE 0x02b5a000
+#define NV_ADDRESS_MAP_TSA_NODE_218_LIMIT 0x02b5afff
+#define NV_ADDRESS_MAP_TSA_NODE_218_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_218_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_219_BASE 0x02b5b000
+#define NV_ADDRESS_MAP_TSA_NODE_219_LIMIT 0x02b5bfff
+#define NV_ADDRESS_MAP_TSA_NODE_219_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_219_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_220_BASE 0x02b5c000
+#define NV_ADDRESS_MAP_TSA_NODE_220_LIMIT 0x02b5cfff
+#define NV_ADDRESS_MAP_TSA_NODE_220_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_220_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_221_BASE 0x02b5d000
+#define NV_ADDRESS_MAP_TSA_NODE_221_LIMIT 0x02b5dfff
+#define NV_ADDRESS_MAP_TSA_NODE_221_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_221_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_222_BASE 0x02b5e000
+#define NV_ADDRESS_MAP_TSA_NODE_222_LIMIT 0x02b5efff
+#define NV_ADDRESS_MAP_TSA_NODE_222_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_222_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_223_BASE 0x02b5f000
+#define NV_ADDRESS_MAP_TSA_NODE_223_LIMIT 0x02b5ffff
+#define NV_ADDRESS_MAP_TSA_NODE_223_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_223_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_224_BASE 0x02b60000
+#define NV_ADDRESS_MAP_TSA_NODE_224_LIMIT 0x02b60fff
+#define NV_ADDRESS_MAP_TSA_NODE_224_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_224_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_225_BASE 0x02b61000
+#define NV_ADDRESS_MAP_TSA_NODE_225_LIMIT 0x02b61fff
+#define NV_ADDRESS_MAP_TSA_NODE_225_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_225_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_226_BASE 0x02b62000
+#define NV_ADDRESS_MAP_TSA_NODE_226_LIMIT 0x02b62fff
+#define NV_ADDRESS_MAP_TSA_NODE_226_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_226_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_227_BASE 0x02b63000
+#define NV_ADDRESS_MAP_TSA_NODE_227_LIMIT 0x02b63fff
+#define NV_ADDRESS_MAP_TSA_NODE_227_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_227_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_228_BASE 0x02b64000
+#define NV_ADDRESS_MAP_TSA_NODE_228_LIMIT 0x02b64fff
+#define NV_ADDRESS_MAP_TSA_NODE_228_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_228_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_229_BASE 0x02b65000
+#define NV_ADDRESS_MAP_TSA_NODE_229_LIMIT 0x02b65fff
+#define NV_ADDRESS_MAP_TSA_NODE_229_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_229_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_230_BASE 0x02b66000
+#define NV_ADDRESS_MAP_TSA_NODE_230_LIMIT 0x02b66fff
+#define NV_ADDRESS_MAP_TSA_NODE_230_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_230_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_231_BASE 0x02b67000
+#define NV_ADDRESS_MAP_TSA_NODE_231_LIMIT 0x02b67fff
+#define NV_ADDRESS_MAP_TSA_NODE_231_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_231_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_232_BASE 0x02b68000
+#define NV_ADDRESS_MAP_TSA_NODE_232_LIMIT 0x02b68fff
+#define NV_ADDRESS_MAP_TSA_NODE_232_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_232_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_233_BASE 0x02b69000
+#define NV_ADDRESS_MAP_TSA_NODE_233_LIMIT 0x02b69fff
+#define NV_ADDRESS_MAP_TSA_NODE_233_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_233_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_234_BASE 0x02b6a000
+#define NV_ADDRESS_MAP_TSA_NODE_234_LIMIT 0x02b6afff
+#define NV_ADDRESS_MAP_TSA_NODE_234_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_234_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_235_BASE 0x02b6b000
+#define NV_ADDRESS_MAP_TSA_NODE_235_LIMIT 0x02b6bfff
+#define NV_ADDRESS_MAP_TSA_NODE_235_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_235_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_236_BASE 0x02b6c000
+#define NV_ADDRESS_MAP_TSA_NODE_236_LIMIT 0x02b6cfff
+#define NV_ADDRESS_MAP_TSA_NODE_236_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_236_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_237_BASE 0x02b6d000
+#define NV_ADDRESS_MAP_TSA_NODE_237_LIMIT 0x02b6dfff
+#define NV_ADDRESS_MAP_TSA_NODE_237_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_237_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_238_BASE 0x02b6e000
+#define NV_ADDRESS_MAP_TSA_NODE_238_LIMIT 0x02b6efff
+#define NV_ADDRESS_MAP_TSA_NODE_238_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_238_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_239_BASE 0x02b6f000
+#define NV_ADDRESS_MAP_TSA_NODE_239_LIMIT 0x02b6ffff
+#define NV_ADDRESS_MAP_TSA_NODE_239_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_239_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_240_BASE 0x02b70000
+#define NV_ADDRESS_MAP_TSA_NODE_240_LIMIT 0x02b70fff
+#define NV_ADDRESS_MAP_TSA_NODE_240_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_240_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_241_BASE 0x02b71000
+#define NV_ADDRESS_MAP_TSA_NODE_241_LIMIT 0x02b71fff
+#define NV_ADDRESS_MAP_TSA_NODE_241_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_241_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_242_BASE 0x02b72000
+#define NV_ADDRESS_MAP_TSA_NODE_242_LIMIT 0x02b72fff
+#define NV_ADDRESS_MAP_TSA_NODE_242_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_242_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_243_BASE 0x02b73000
+#define NV_ADDRESS_MAP_TSA_NODE_243_LIMIT 0x02b73fff
+#define NV_ADDRESS_MAP_TSA_NODE_243_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_243_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_244_BASE 0x02b74000
+#define NV_ADDRESS_MAP_TSA_NODE_244_LIMIT 0x02b74fff
+#define NV_ADDRESS_MAP_TSA_NODE_244_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_244_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_245_BASE 0x02b75000
+#define NV_ADDRESS_MAP_TSA_NODE_245_LIMIT 0x02b75fff
+#define NV_ADDRESS_MAP_TSA_NODE_245_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_245_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_246_BASE 0x02b76000
+#define NV_ADDRESS_MAP_TSA_NODE_246_LIMIT 0x02b76fff
+#define NV_ADDRESS_MAP_TSA_NODE_246_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_246_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_247_BASE 0x02b77000
+#define NV_ADDRESS_MAP_TSA_NODE_247_LIMIT 0x02b77fff
+#define NV_ADDRESS_MAP_TSA_NODE_247_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_247_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_248_BASE 0x02b78000
+#define NV_ADDRESS_MAP_TSA_NODE_248_LIMIT 0x02b78fff
+#define NV_ADDRESS_MAP_TSA_NODE_248_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_248_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_249_BASE 0x02b79000
+#define NV_ADDRESS_MAP_TSA_NODE_249_LIMIT 0x02b79fff
+#define NV_ADDRESS_MAP_TSA_NODE_249_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_249_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_250_BASE 0x02b7a000
+#define NV_ADDRESS_MAP_TSA_NODE_250_LIMIT 0x02b7afff
+#define NV_ADDRESS_MAP_TSA_NODE_250_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_250_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_251_BASE 0x02b7b000
+#define NV_ADDRESS_MAP_TSA_NODE_251_LIMIT 0x02b7bfff
+#define NV_ADDRESS_MAP_TSA_NODE_251_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_251_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_252_BASE 0x02b7c000
+#define NV_ADDRESS_MAP_TSA_NODE_252_LIMIT 0x02b7cfff
+#define NV_ADDRESS_MAP_TSA_NODE_252_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_252_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_253_BASE 0x02b7d000
+#define NV_ADDRESS_MAP_TSA_NODE_253_LIMIT 0x02b7dfff
+#define NV_ADDRESS_MAP_TSA_NODE_253_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_253_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_254_BASE 0x02b7e000
+#define NV_ADDRESS_MAP_TSA_NODE_254_LIMIT 0x02b7efff
+#define NV_ADDRESS_MAP_TSA_NODE_254_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_254_HEADER
+
+#define NV_ADDRESS_MAP_TSA_NODE_255_BASE 0x02b7f000
+#define NV_ADDRESS_MAP_TSA_NODE_255_LIMIT 0x02b7ffff
+#define NV_ADDRESS_MAP_TSA_NODE_255_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSA_NODE_255_HEADER
+
+#define NV_ADDRESS_MAP_MC4_BASE 0x02b80000
+#define NV_ADDRESS_MAP_MC4_LIMIT 0x02b8ffff
+#define NV_ADDRESS_MAP_MC4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MC4_HEADER armc.h;armc_scr.h
+
+#define NV_ADDRESS_MAP_MC5_BASE 0x02b90000
+#define NV_ADDRESS_MAP_MC5_LIMIT 0x02b9ffff
+#define NV_ADDRESS_MAP_MC5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MC5_HEADER armc.h;armc_scr.h
+
+#define NV_ADDRESS_MAP_MC6_BASE 0x02ba0000
+#define NV_ADDRESS_MAP_MC6_LIMIT 0x02baffff
+#define NV_ADDRESS_MAP_MC6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MC6_HEADER armc.h;armc_scr.h
+
+#define NV_ADDRESS_MAP_MC7_BASE 0x02bb0000
+#define NV_ADDRESS_MAP_MC7_LIMIT 0x02bbffff
+#define NV_ADDRESS_MAP_MC7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MC7_HEADER armc.h;armc_scr.h
+
+#define NV_ADDRESS_MAP_MC_SID_BASE 0x02c00000
+#define NV_ADDRESS_MAP_MC_SID_LIMIT 0x02c0ffff
+#define NV_ADDRESS_MAP_MC_SID_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MC_SID_HEADER armc_sid.h
+
+#define NV_ADDRESS_MAP_MCB_BASE 0x02c10000
+#define NV_ADDRESS_MAP_MCB_LIMIT 0x02c1ffff
+#define NV_ADDRESS_MAP_MCB_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MCB_HEADER armc.h;armc_scr.h
+
+#define NV_ADDRESS_MAP_MC0_BASE 0x02c20000
+#define NV_ADDRESS_MAP_MC0_LIMIT 0x02c2ffff
+#define NV_ADDRESS_MAP_MC0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MC0_HEADER armc.h;armc_scr.h
+
+#define NV_ADDRESS_MAP_MC1_BASE 0x02c30000
+#define NV_ADDRESS_MAP_MC1_LIMIT 0x02c3ffff
+#define NV_ADDRESS_MAP_MC1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MC1_HEADER armc.h;armc_scr.h
+
+#define NV_ADDRESS_MAP_MC2_BASE 0x02c40000
+#define NV_ADDRESS_MAP_MC2_LIMIT 0x02c4ffff
+#define NV_ADDRESS_MAP_MC2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MC2_HEADER armc.h;armc_scr.h
+
+#define NV_ADDRESS_MAP_MC3_BASE 0x02c50000
+#define NV_ADDRESS_MAP_MC3_LIMIT 0x02c5ffff
+#define NV_ADDRESS_MAP_MC3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MC3_HEADER armc.h;armc_scr.h
+
+#define NV_ADDRESS_MAP_EMCB_CORE_BASE 0x02c60000
+#define NV_ADDRESS_MAP_EMCB_CORE_LIMIT 0x02c60fff
+#define NV_ADDRESS_MAP_EMCB_CORE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMCB_CORE_HEADER
+
+#define NV_ADDRESS_MAP_EMCB_CFG_BASE 0x02c61000
+#define NV_ADDRESS_MAP_EMCB_CFG_LIMIT 0x02c61fff
+#define NV_ADDRESS_MAP_EMCB_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMCB_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EMCB_EC_BASE 0x02c62000
+#define NV_ADDRESS_MAP_EMCB_EC_LIMIT 0x02c62fff
+#define NV_ADDRESS_MAP_EMCB_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMCB_EC_HEADER
+
+#define NV_ADDRESS_MAP_EMCB_TR_BASE 0x02c63000
+#define NV_ADDRESS_MAP_EMCB_TR_LIMIT 0x02c63fff
+#define NV_ADDRESS_MAP_EMCB_TR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMCB_TR_HEADER
+
+#define NV_ADDRESS_MAP_EMCB_MISC_BASE 0x02c64000
+#define NV_ADDRESS_MAP_EMCB_MISC_LIMIT 0x02c6ffff
+#define NV_ADDRESS_MAP_EMCB_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMCB_MISC_HEADER
+
+#define NV_ADDRESS_MAP_EMC0_CORE_BASE 0x02c70000
+#define NV_ADDRESS_MAP_EMC0_CORE_LIMIT 0x02c70fff
+#define NV_ADDRESS_MAP_EMC0_CORE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC0_CORE_HEADER
+
+#define NV_ADDRESS_MAP_EMC0_CFG_BASE 0x02c71000
+#define NV_ADDRESS_MAP_EMC0_CFG_LIMIT 0x02c71fff
+#define NV_ADDRESS_MAP_EMC0_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC0_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EMC0_EC_BASE 0x02c72000
+#define NV_ADDRESS_MAP_EMC0_EC_LIMIT 0x02c72fff
+#define NV_ADDRESS_MAP_EMC0_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC0_EC_HEADER
+
+#define NV_ADDRESS_MAP_EMC0_TR_BASE 0x02c73000
+#define NV_ADDRESS_MAP_EMC0_TR_LIMIT 0x02c73fff
+#define NV_ADDRESS_MAP_EMC0_TR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC0_TR_HEADER
+
+#define NV_ADDRESS_MAP_EMC0_MISC_BASE 0x02c74000
+#define NV_ADDRESS_MAP_EMC0_MISC_LIMIT 0x02c7ffff
+#define NV_ADDRESS_MAP_EMC0_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC0_MISC_HEADER
+
+#define NV_ADDRESS_MAP_EMC1_CORE_BASE 0x02c80000
+#define NV_ADDRESS_MAP_EMC1_CORE_LIMIT 0x02c80fff
+#define NV_ADDRESS_MAP_EMC1_CORE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC1_CORE_HEADER
+
+#define NV_ADDRESS_MAP_EMC1_CFG_BASE 0x02c81000
+#define NV_ADDRESS_MAP_EMC1_CFG_LIMIT 0x02c81fff
+#define NV_ADDRESS_MAP_EMC1_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC1_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EMC1_EC_BASE 0x02c82000
+#define NV_ADDRESS_MAP_EMC1_EC_LIMIT 0x02c82fff
+#define NV_ADDRESS_MAP_EMC1_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC1_EC_HEADER
+
+#define NV_ADDRESS_MAP_EMC1_TR_BASE 0x02c83000
+#define NV_ADDRESS_MAP_EMC1_TR_LIMIT 0x02c83fff
+#define NV_ADDRESS_MAP_EMC1_TR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC1_TR_HEADER
+
+#define NV_ADDRESS_MAP_EMC1_MISC_BASE 0x02c84000
+#define NV_ADDRESS_MAP_EMC1_MISC_LIMIT 0x02c8ffff
+#define NV_ADDRESS_MAP_EMC1_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC1_MISC_HEADER
+
+#define NV_ADDRESS_MAP_EMC2_CORE_BASE 0x02c90000
+#define NV_ADDRESS_MAP_EMC2_CORE_LIMIT 0x02c90fff
+#define NV_ADDRESS_MAP_EMC2_CORE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC2_CORE_HEADER
+
+#define NV_ADDRESS_MAP_EMC2_CFG_BASE 0x02c91000
+#define NV_ADDRESS_MAP_EMC2_CFG_LIMIT 0x02c91fff
+#define NV_ADDRESS_MAP_EMC2_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC2_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EMC2_EC_BASE 0x02c92000
+#define NV_ADDRESS_MAP_EMC2_EC_LIMIT 0x02c92fff
+#define NV_ADDRESS_MAP_EMC2_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC2_EC_HEADER
+
+#define NV_ADDRESS_MAP_EMC2_TR_BASE 0x02c93000
+#define NV_ADDRESS_MAP_EMC2_TR_LIMIT 0x02c93fff
+#define NV_ADDRESS_MAP_EMC2_TR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC2_TR_HEADER
+
+#define NV_ADDRESS_MAP_EMC2_MISC_BASE 0x02c94000
+#define NV_ADDRESS_MAP_EMC2_MISC_LIMIT 0x02c9ffff
+#define NV_ADDRESS_MAP_EMC2_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC2_MISC_HEADER
+
+#define NV_ADDRESS_MAP_EMC3_CORE_BASE 0x02ca0000
+#define NV_ADDRESS_MAP_EMC3_CORE_LIMIT 0x02ca0fff
+#define NV_ADDRESS_MAP_EMC3_CORE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC3_CORE_HEADER
+
+#define NV_ADDRESS_MAP_EMC3_CFG_BASE 0x02ca1000
+#define NV_ADDRESS_MAP_EMC3_CFG_LIMIT 0x02ca1fff
+#define NV_ADDRESS_MAP_EMC3_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC3_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EMC3_EC_BASE 0x02ca2000
+#define NV_ADDRESS_MAP_EMC3_EC_LIMIT 0x02ca2fff
+#define NV_ADDRESS_MAP_EMC3_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC3_EC_HEADER
+
+#define NV_ADDRESS_MAP_EMC3_TR_BASE 0x02ca3000
+#define NV_ADDRESS_MAP_EMC3_TR_LIMIT 0x02ca3fff
+#define NV_ADDRESS_MAP_EMC3_TR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC3_TR_HEADER
+
+#define NV_ADDRESS_MAP_EMC3_MISC_BASE 0x02ca4000
+#define NV_ADDRESS_MAP_EMC3_MISC_LIMIT 0x02caffff
+#define NV_ADDRESS_MAP_EMC3_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC3_MISC_HEADER
+
+#define NV_ADDRESS_MAP_EMC4_CORE_BASE 0x02cb0000
+#define NV_ADDRESS_MAP_EMC4_CORE_LIMIT 0x02cb0fff
+#define NV_ADDRESS_MAP_EMC4_CORE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC4_CORE_HEADER
+
+#define NV_ADDRESS_MAP_EMC4_CFG_BASE 0x02cb1000
+#define NV_ADDRESS_MAP_EMC4_CFG_LIMIT 0x02cb1fff
+#define NV_ADDRESS_MAP_EMC4_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC4_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EMC4_EC_BASE 0x02cb2000
+#define NV_ADDRESS_MAP_EMC4_EC_LIMIT 0x02cb2fff
+#define NV_ADDRESS_MAP_EMC4_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC4_EC_HEADER
+
+#define NV_ADDRESS_MAP_EMC4_TR_BASE 0x02cb3000
+#define NV_ADDRESS_MAP_EMC4_TR_LIMIT 0x02cb3fff
+#define NV_ADDRESS_MAP_EMC4_TR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC4_TR_HEADER
+
+#define NV_ADDRESS_MAP_EMC4_MISC_BASE 0x02cb4000
+#define NV_ADDRESS_MAP_EMC4_MISC_LIMIT 0x02cbffff
+#define NV_ADDRESS_MAP_EMC4_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC4_MISC_HEADER
+
+#define NV_ADDRESS_MAP_EMC5_CORE_BASE 0x02cc0000
+#define NV_ADDRESS_MAP_EMC5_CORE_LIMIT 0x02cc0fff
+#define NV_ADDRESS_MAP_EMC5_CORE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC5_CORE_HEADER
+
+#define NV_ADDRESS_MAP_EMC5_CFG_BASE 0x02cc1000
+#define NV_ADDRESS_MAP_EMC5_CFG_LIMIT 0x02cc1fff
+#define NV_ADDRESS_MAP_EMC5_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC5_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EMC5_EC_BASE 0x02cc2000
+#define NV_ADDRESS_MAP_EMC5_EC_LIMIT 0x02cc2fff
+#define NV_ADDRESS_MAP_EMC5_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC5_EC_HEADER
+
+#define NV_ADDRESS_MAP_EMC5_TR_BASE 0x02cc3000
+#define NV_ADDRESS_MAP_EMC5_TR_LIMIT 0x02cc3fff
+#define NV_ADDRESS_MAP_EMC5_TR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC5_TR_HEADER
+
+#define NV_ADDRESS_MAP_EMC5_MISC_BASE 0x02cc4000
+#define NV_ADDRESS_MAP_EMC5_MISC_LIMIT 0x02ccffff
+#define NV_ADDRESS_MAP_EMC5_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC5_MISC_HEADER
+
+#define NV_ADDRESS_MAP_EMC6_CORE_BASE 0x02cd0000
+#define NV_ADDRESS_MAP_EMC6_CORE_LIMIT 0x02cd0fff
+#define NV_ADDRESS_MAP_EMC6_CORE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC6_CORE_HEADER
+
+#define NV_ADDRESS_MAP_EMC6_CFG_BASE 0x02cd1000
+#define NV_ADDRESS_MAP_EMC6_CFG_LIMIT 0x02cd1fff
+#define NV_ADDRESS_MAP_EMC6_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC6_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EMC6_EC_BASE 0x02cd2000
+#define NV_ADDRESS_MAP_EMC6_EC_LIMIT 0x02cd2fff
+#define NV_ADDRESS_MAP_EMC6_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC6_EC_HEADER
+
+#define NV_ADDRESS_MAP_EMC6_TR_BASE 0x02cd3000
+#define NV_ADDRESS_MAP_EMC6_TR_LIMIT 0x02cd3fff
+#define NV_ADDRESS_MAP_EMC6_TR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC6_TR_HEADER
+
+#define NV_ADDRESS_MAP_EMC6_MISC_BASE 0x02cd4000
+#define NV_ADDRESS_MAP_EMC6_MISC_LIMIT 0x02cdffff
+#define NV_ADDRESS_MAP_EMC6_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC6_MISC_HEADER
+
+#define NV_ADDRESS_MAP_EMC7_CORE_BASE 0x02ce0000
+#define NV_ADDRESS_MAP_EMC7_CORE_LIMIT 0x02ce0fff
+#define NV_ADDRESS_MAP_EMC7_CORE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC7_CORE_HEADER
+
+#define NV_ADDRESS_MAP_EMC7_CFG_BASE 0x02ce1000
+#define NV_ADDRESS_MAP_EMC7_CFG_LIMIT 0x02ce1fff
+#define NV_ADDRESS_MAP_EMC7_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC7_CFG_HEADER
+
+#define NV_ADDRESS_MAP_EMC7_EC_BASE 0x02ce2000
+#define NV_ADDRESS_MAP_EMC7_EC_LIMIT 0x02ce2fff
+#define NV_ADDRESS_MAP_EMC7_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC7_EC_HEADER
+
+#define NV_ADDRESS_MAP_EMC7_TR_BASE 0x02ce3000
+#define NV_ADDRESS_MAP_EMC7_TR_LIMIT 0x02ce3fff
+#define NV_ADDRESS_MAP_EMC7_TR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC7_TR_HEADER
+
+#define NV_ADDRESS_MAP_EMC7_MISC_BASE 0x02ce4000
+#define NV_ADDRESS_MAP_EMC7_MISC_LIMIT 0x02ceffff
+#define NV_ADDRESS_MAP_EMC7_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMC7_MISC_HEADER
+
+#define NV_ADDRESS_MAP_MSS_QUAL_BASE 0x02cf0000
+#define NV_ADDRESS_MAP_MSS_QUAL_LIMIT 0x02cfffff
+#define NV_ADDRESS_MAP_MSS_QUAL_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MSS_QUAL_HEADER arqualeng.h;arqualeng_scr.h
+
+#define NV_ADDRESS_MAP_UPHY_PLL0_BASE 0x02d00000
+#define NV_ADDRESS_MAP_UPHY_PLL0_LIMIT 0x02d01fff
+#define NV_ADDRESS_MAP_UPHY_PLL0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UPHY_PLL0_HEADER aruphy_pll.h
+
+#define NV_ADDRESS_MAP_UPHY_LANE0_BASE 0x02d02000
+#define NV_ADDRESS_MAP_UPHY_LANE0_LIMIT 0x02d02fff
+#define NV_ADDRESS_MAP_UPHY_LANE0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UPHY_LANE0_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_UPHY_LANE1_BASE 0x02d03000
+#define NV_ADDRESS_MAP_UPHY_LANE1_LIMIT 0x02d03fff
+#define NV_ADDRESS_MAP_UPHY_LANE1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UPHY_LANE1_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_UPHY_PLL1_BASE 0x02d04000
+#define NV_ADDRESS_MAP_UPHY_PLL1_LIMIT 0x02d05fff
+#define NV_ADDRESS_MAP_UPHY_PLL1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UPHY_PLL1_HEADER aruphy_pll.h
+
+#define NV_ADDRESS_MAP_UPHY_LANE2_BASE 0x02d06000
+#define NV_ADDRESS_MAP_UPHY_LANE2_LIMIT 0x02d06fff
+#define NV_ADDRESS_MAP_UPHY_LANE2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UPHY_LANE2_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_UPHY_LANE3_BASE 0x02d07000
+#define NV_ADDRESS_MAP_UPHY_LANE3_LIMIT 0x02d07fff
+#define NV_ADDRESS_MAP_UPHY_LANE3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UPHY_LANE3_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_UPHY_PLL2_BASE 0x02d08000
+#define NV_ADDRESS_MAP_UPHY_PLL2_LIMIT 0x02d09fff
+#define NV_ADDRESS_MAP_UPHY_PLL2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UPHY_PLL2_HEADER aruphy_pll.h
+
+#define NV_ADDRESS_MAP_UPHY_LANE4_BASE 0x02d0a000
+#define NV_ADDRESS_MAP_UPHY_LANE4_LIMIT 0x02d0afff
+#define NV_ADDRESS_MAP_UPHY_LANE4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UPHY_LANE4_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_UPHY_LANE5_BASE 0x02d0b000
+#define NV_ADDRESS_MAP_UPHY_LANE5_LIMIT 0x02d0bfff
+#define NV_ADDRESS_MAP_UPHY_LANE5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UPHY_LANE5_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_UPHY_LANE6_BASE 0x02d0c000
+#define NV_ADDRESS_MAP_UPHY_LANE6_LIMIT 0x02d0cfff
+#define NV_ADDRESS_MAP_UPHY_LANE6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UPHY_LANE6_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_UPHY_LANE7_BASE 0x02d0d000
+#define NV_ADDRESS_MAP_UPHY_LANE7_LIMIT 0x02d0dfff
+#define NV_ADDRESS_MAP_UPHY_LANE7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UPHY_LANE7_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_UPHY_PLL3_BASE 0x02d0e000
+#define NV_ADDRESS_MAP_UPHY_PLL3_LIMIT 0x02d0ffff
+#define NV_ADDRESS_MAP_UPHY_PLL3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UPHY_PLL3_HEADER aruphy_pll.h
+
+#define NV_ADDRESS_MAP_NVHSUPHY_PLL0_BASE 0x02f00000
+#define NV_ADDRESS_MAP_NVHSUPHY_PLL0_LIMIT 0x02f01fff
+#define NV_ADDRESS_MAP_NVHSUPHY_PLL0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVHSUPHY_PLL0_HEADER aruphy_pll.h
+
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE0_BASE 0x02f02000
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE0_LIMIT 0x02f02fff
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE0_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE1_BASE 0x02f03000
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE1_LIMIT 0x02f03fff
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE1_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE2_BASE 0x02f04000
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE2_LIMIT 0x02f04fff
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE2_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE3_BASE 0x02f05000
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE3_LIMIT 0x02f05fff
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE3_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE4_BASE 0x02f06000
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE4_LIMIT 0x02f06fff
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE4_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE5_BASE 0x02f07000
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE5_LIMIT 0x02f07fff
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE5_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE6_BASE 0x02f08000
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE6_LIMIT 0x02f08fff
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE6_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE7_BASE 0x02f09000
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE7_LIMIT 0x02f09fff
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVHSUPHY_LANE7_HEADER aruphy_lane.h
+
+#define NV_ADDRESS_MAP_NVHSUPHY_PLL1_BASE 0x02f0a000
+#define NV_ADDRESS_MAP_NVHSUPHY_PLL1_LIMIT 0x02f0bfff
+#define NV_ADDRESS_MAP_NVHSUPHY_PLL1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVHSUPHY_PLL1_HEADER aruphy_pll.h
+
+#define NV_ADDRESS_MAP_LIC_CH0_BASE 0x03000000
+#define NV_ADDRESS_MAP_LIC_CH0_LIMIT 0x030007ff
+#define NV_ADDRESS_MAP_LIC_CH0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_LIC_CH0_HEADER
+
+#define NV_ADDRESS_MAP_LIC_CH1_BASE 0x03000800
+#define NV_ADDRESS_MAP_LIC_CH1_LIMIT 0x03000fff
+#define NV_ADDRESS_MAP_LIC_CH1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_LIC_CH1_HEADER
+
+#define NV_ADDRESS_MAP_LIC_CH2_BASE 0x03001000
+#define NV_ADDRESS_MAP_LIC_CH2_LIMIT 0x030017ff
+#define NV_ADDRESS_MAP_LIC_CH2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_LIC_CH2_HEADER
+
+#define NV_ADDRESS_MAP_LIC_CH3_BASE 0x03001800
+#define NV_ADDRESS_MAP_LIC_CH3_LIMIT 0x03001fff
+#define NV_ADDRESS_MAP_LIC_CH3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_LIC_CH3_HEADER
+
+#define NV_ADDRESS_MAP_LIC_CH4_BASE 0x03002000
+#define NV_ADDRESS_MAP_LIC_CH4_LIMIT 0x030027ff
+#define NV_ADDRESS_MAP_LIC_CH4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_LIC_CH4_HEADER
+
+#define NV_ADDRESS_MAP_LIC_CH5_BASE 0x03002800
+#define NV_ADDRESS_MAP_LIC_CH5_LIMIT 0x03002fff
+#define NV_ADDRESS_MAP_LIC_CH5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_LIC_CH5_HEADER
+
+#define NV_ADDRESS_MAP_LIC_CH6_BASE 0x03003000
+#define NV_ADDRESS_MAP_LIC_CH6_LIMIT 0x030037ff
+#define NV_ADDRESS_MAP_LIC_CH6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_LIC_CH6_HEADER
+
+#define NV_ADDRESS_MAP_LIC_CH7_BASE 0x03003800
+#define NV_ADDRESS_MAP_LIC_CH7_LIMIT 0x03003fff
+#define NV_ADDRESS_MAP_LIC_CH7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_LIC_CH7_HEADER
+
+#define NV_ADDRESS_MAP_LIC_CH8_BASE 0x03004000
+#define NV_ADDRESS_MAP_LIC_CH8_LIMIT 0x030047ff
+#define NV_ADDRESS_MAP_LIC_CH8_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_LIC_CH8_HEADER
+
+#define NV_ADDRESS_MAP_LIC_CH9_BASE 0x03004800
+#define NV_ADDRESS_MAP_LIC_CH9_LIMIT 0x03004fff
+#define NV_ADDRESS_MAP_LIC_CH9_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_LIC_CH9_HEADER
+
+#define NV_ADDRESS_MAP_LIC_CH10_BASE 0x03005000
+#define NV_ADDRESS_MAP_LIC_CH10_LIMIT 0x030057ff
+#define NV_ADDRESS_MAP_LIC_CH10_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_LIC_CH10_HEADER
+
+#define NV_ADDRESS_MAP_LIC_CH11_BASE 0x03005800
+#define NV_ADDRESS_MAP_LIC_CH11_LIMIT 0x03005fff
+#define NV_ADDRESS_MAP_LIC_CH11_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_LIC_CH11_HEADER
+
+#define NV_ADDRESS_MAP_LIC_COMMON_BASE 0x0300f800
+#define NV_ADDRESS_MAP_LIC_COMMON_LIMIT 0x0300ffff
+#define NV_ADDRESS_MAP_LIC_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_LIC_COMMON_HEADER
+
+#define NV_ADDRESS_MAP_UARTA_BASE 0x03100000
+#define NV_ADDRESS_MAP_UARTA_LIMIT 0x0310ffff
+#define NV_ADDRESS_MAP_UARTA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UARTA_HEADER aruart.h
+
+#define NV_ADDRESS_MAP_UARTB_BASE 0x03110000
+#define NV_ADDRESS_MAP_UARTB_LIMIT 0x0311ffff
+#define NV_ADDRESS_MAP_UARTB_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UARTB_HEADER aruart.h
+
+#define NV_ADDRESS_MAP_UARTD_BASE 0x03130000
+#define NV_ADDRESS_MAP_UARTD_LIMIT 0x0313ffff
+#define NV_ADDRESS_MAP_UARTD_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UARTD_HEADER aruart.h
+
+#define NV_ADDRESS_MAP_UARTE_BASE 0x03140000
+#define NV_ADDRESS_MAP_UARTE_LIMIT 0x0314ffff
+#define NV_ADDRESS_MAP_UARTE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UARTE_HEADER aruart.h
+
+#define NV_ADDRESS_MAP_UARTF_BASE 0x03150000
+#define NV_ADDRESS_MAP_UARTF_LIMIT 0x0315ffff
+#define NV_ADDRESS_MAP_UARTF_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UARTF_HEADER aruart.h
+
+#define NV_ADDRESS_MAP_I2C1_BASE 0x03160000
+#define NV_ADDRESS_MAP_I2C1_LIMIT 0x0316ffff
+#define NV_ADDRESS_MAP_I2C1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_I2C1_HEADER ari2c.h
+
+#define NV_ADDRESS_MAP_UARTH_BASE 0x03170000
+#define NV_ADDRESS_MAP_UARTH_LIMIT 0x0317ffff
+#define NV_ADDRESS_MAP_UARTH_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UARTH_HEADER aruart.h
+
+#define NV_ADDRESS_MAP_I2C3_BASE 0x03180000
+#define NV_ADDRESS_MAP_I2C3_LIMIT 0x0318ffff
+#define NV_ADDRESS_MAP_I2C3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_I2C3_HEADER ari2c.h
+
+#define NV_ADDRESS_MAP_I2C4_BASE 0x03190000
+#define NV_ADDRESS_MAP_I2C4_LIMIT 0x0319ffff
+#define NV_ADDRESS_MAP_I2C4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_I2C4_HEADER ari2c.h
+
+#define NV_ADDRESS_MAP_I2C5_BASE 0x031a0000
+#define NV_ADDRESS_MAP_I2C5_LIMIT 0x031affff
+#define NV_ADDRESS_MAP_I2C5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_I2C5_HEADER ari2c.h
+
+#define NV_ADDRESS_MAP_I2C6_BASE 0x031b0000
+#define NV_ADDRESS_MAP_I2C6_LIMIT 0x031bffff
+#define NV_ADDRESS_MAP_I2C6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_I2C6_HEADER ari2c.h
+
+#define NV_ADDRESS_MAP_I2C7_BASE 0x031c0000
+#define NV_ADDRESS_MAP_I2C7_LIMIT 0x031cffff
+#define NV_ADDRESS_MAP_I2C7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_I2C7_HEADER ari2c.h
+
+#define NV_ADDRESS_MAP_UARTI_BASE 0x031d0000
+#define NV_ADDRESS_MAP_UARTI_LIMIT 0x031dffff
+#define NV_ADDRESS_MAP_UARTI_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UARTI_HEADER arsbsa_uart.h
+
+#define NV_ADDRESS_MAP_I2C9_BASE 0x031e0000
+#define NV_ADDRESS_MAP_I2C9_LIMIT 0x031effff
+#define NV_ADDRESS_MAP_I2C9_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_I2C9_HEADER ari2c.h
+
+#define NV_ADDRESS_MAP_SPI1_BASE 0x03210000
+#define NV_ADDRESS_MAP_SPI1_LIMIT 0x0321ffff
+#define NV_ADDRESS_MAP_SPI1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SPI1_HEADER arspi.h
+
+#define NV_ADDRESS_MAP_SPI3_BASE 0x03230000
+#define NV_ADDRESS_MAP_SPI3_LIMIT 0x0323ffff
+#define NV_ADDRESS_MAP_SPI3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SPI3_HEADER arspi.h
+
+#define NV_ADDRESS_MAP_SPI4_BASE 0x03240000
+#define NV_ADDRESS_MAP_SPI4_LIMIT 0x0324ffff
+#define NV_ADDRESS_MAP_SPI4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SPI4_HEADER arspi.h
+
+#define NV_ADDRESS_MAP_SPI5_BASE 0x03250000
+#define NV_ADDRESS_MAP_SPI5_LIMIT 0x0325ffff
+#define NV_ADDRESS_MAP_SPI5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SPI5_HEADER arspi.h
+
+#define NV_ADDRESS_MAP_QSPI0_BASE 0x03270000
+#define NV_ADDRESS_MAP_QSPI0_LIMIT 0x0327ffff
+#define NV_ADDRESS_MAP_QSPI0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_QSPI0_HEADER arqspi.h;arqspi_secure.h
+
+#define NV_ADDRESS_MAP_PWM1_BASE 0x03280000
+#define NV_ADDRESS_MAP_PWM1_LIMIT 0x0328ffff
+#define NV_ADDRESS_MAP_PWM1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PWM1_HEADER arpwm.h
+
+#define NV_ADDRESS_MAP_PWM2_BASE 0x03290000
+#define NV_ADDRESS_MAP_PWM2_LIMIT 0x0329ffff
+#define NV_ADDRESS_MAP_PWM2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PWM2_HEADER arpwm.h
+
+#define NV_ADDRESS_MAP_PWM3_BASE 0x032a0000
+#define NV_ADDRESS_MAP_PWM3_LIMIT 0x032affff
+#define NV_ADDRESS_MAP_PWM3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PWM3_HEADER arpwm.h
+
+#define NV_ADDRESS_MAP_PWM5_BASE 0x032c0000
+#define NV_ADDRESS_MAP_PWM5_LIMIT 0x032cffff
+#define NV_ADDRESS_MAP_PWM5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PWM5_HEADER arpwm.h
+
+#define NV_ADDRESS_MAP_PWM6_BASE 0x032d0000
+#define NV_ADDRESS_MAP_PWM6_LIMIT 0x032dffff
+#define NV_ADDRESS_MAP_PWM6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PWM6_HEADER arpwm.h
+
+#define NV_ADDRESS_MAP_PWM7_BASE 0x032e0000
+#define NV_ADDRESS_MAP_PWM7_LIMIT 0x032effff
+#define NV_ADDRESS_MAP_PWM7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PWM7_HEADER arpwm.h
+
+#define NV_ADDRESS_MAP_PWM8_BASE 0x032f0000
+#define NV_ADDRESS_MAP_PWM8_LIMIT 0x032fffff
+#define NV_ADDRESS_MAP_PWM8_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PWM8_HEADER arpwm.h
+
+#define NV_ADDRESS_MAP_QSPI1_BASE 0x03300000
+#define NV_ADDRESS_MAP_QSPI1_LIMIT 0x0330ffff
+#define NV_ADDRESS_MAP_QSPI1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_QSPI1_HEADER arqspi.h;arqspi_secure.h
+
+#define NV_ADDRESS_MAP_SDMMC1_IMPL_BASE 0x03400000
+#define NV_ADDRESS_MAP_SDMMC1_IMPL_LIMIT 0x0340ffff
+#define NV_ADDRESS_MAP_SDMMC1_IMPL_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SDMMC1_IMPL_HEADER arsdmmca.h
+
+#define NV_ADDRESS_MAP_SDMMC1B_BASE 0x03410000
+#define NV_ADDRESS_MAP_SDMMC1B_LIMIT 0x0341ffff
+#define NV_ADDRESS_MAP_SDMMC1B_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SDMMC1B_HEADER arsdmmca.h
+
+#define NV_ADDRESS_MAP_SDMMC4_IMPL_BASE 0x03460000
+#define NV_ADDRESS_MAP_SDMMC4_IMPL_LIMIT 0x0346ffff
+#define NV_ADDRESS_MAP_SDMMC4_IMPL_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SDMMC4_IMPL_HEADER arsdmmcab.h
+
+#define NV_ADDRESS_MAP_SDMMC4B_BASE 0x03470000
+#define NV_ADDRESS_MAP_SDMMC4B_LIMIT 0x0347ffff
+#define NV_ADDRESS_MAP_SDMMC4B_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SDMMC4B_HEADER arsdmmcab.h
+
+#define NV_ADDRESS_MAP_HDA_BASE 0x03510000
+#define NV_ADDRESS_MAP_HDA_LIMIT 0x0351ffff
+#define NV_ADDRESS_MAP_HDA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HDA_HEADER arhda.h
+
+#define NV_ADDRESS_MAP_XUSB_PADCTL_NONSECURE_BASE 0x03520000
+#define NV_ADDRESS_MAP_XUSB_PADCTL_NONSECURE_LIMIT 0x0352ffff
+#define NV_ADDRESS_MAP_XUSB_PADCTL_NONSECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_PADCTL_NONSECURE_HEADER
+
+#define NV_ADDRESS_MAP_XUSB_PADCTL_SECURE_BASE 0x03530000
+#define NV_ADDRESS_MAP_XUSB_PADCTL_SECURE_LIMIT 0x0353ffff
+#define NV_ADDRESS_MAP_XUSB_PADCTL_SECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_PADCTL_SECURE_HEADER
+
+#define NV_ADDRESS_MAP_XUSB_AO_BASE 0x03540000
+#define NV_ADDRESS_MAP_XUSB_AO_LIMIT 0x0354ffff
+#define NV_ADDRESS_MAP_XUSB_AO_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_AO_HEADER arxusb_ao.h
+
+#define NV_ADDRESS_MAP_XUSB_DEV_BAR0_BASE 0x03550000
+#define NV_ADDRESS_MAP_XUSB_DEV_BAR0_LIMIT 0x03557fff
+#define NV_ADDRESS_MAP_XUSB_DEV_BAR0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_DEV_BAR0_HEADER ardev_t_xusb_dev_xhci.h
+
+#define NV_ADDRESS_MAP_XUSB_DEV_CFG_BASE 0x03558000
+#define NV_ADDRESS_MAP_XUSB_DEV_CFG_LIMIT 0x0355ffff
+#define NV_ADDRESS_MAP_XUSB_DEV_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_DEV_CFG_HEADER ardev_t_fpci_xusb_dev.h;ardev_t_fpci_xusb_dev_0.h
+
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_CFG_BASE 0x03600000
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_CFG_LIMIT 0x0360ffff
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_CFG_HEADER ardev_t_fpci_xusb_0.h
+
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_BAR0_OP_BASE 0x03610000
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_BAR0_OP_LIMIT 0x0362ffff
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_BAR0_OP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_BAR0_OP_HEADER
+
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_BAR0_RT_BASE 0x03630000
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_BAR0_RT_LIMIT 0x0363ffff
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_BAR0_RT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_BAR0_RT_HEADER
+
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_BAR0_DB_BASE 0x03640000
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_BAR0_DB_LIMIT 0x0364ffff
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_BAR0_DB_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_BAR0_DB_HEADER
+
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_BAR2_BASE 0x03650000
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_BAR2_LIMIT 0x0365ffff
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_BAR2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_PF_BAR2_HEADER ardev_t_xusb_bar2.h
+
+#define NV_ADDRESS_MAP_XUSB_HOST_VF0_CFG_BASE 0x03660000
+#define NV_ADDRESS_MAP_XUSB_HOST_VF0_CFG_LIMIT 0x0366ffff
+#define NV_ADDRESS_MAP_XUSB_HOST_VF0_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_VF0_CFG_HEADER ardev_t_fpci_xusb_0.h
+
+#define NV_ADDRESS_MAP_XUSB_HOST_VF0_BAR0_OP_BASE 0x03670000
+#define NV_ADDRESS_MAP_XUSB_HOST_VF0_BAR0_OP_LIMIT 0x0368ffff
+#define NV_ADDRESS_MAP_XUSB_HOST_VF0_BAR0_OP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_VF0_BAR0_OP_HEADER
+
+#define NV_ADDRESS_MAP_XUSB_HOST_VF0_BAR0_RT_BASE 0x03690000
+#define NV_ADDRESS_MAP_XUSB_HOST_VF0_BAR0_RT_LIMIT 0x0369ffff
+#define NV_ADDRESS_MAP_XUSB_HOST_VF0_BAR0_RT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_VF0_BAR0_RT_HEADER
+
+#define NV_ADDRESS_MAP_XUSB_HOST_VF0_BAR0_DB_BASE 0x036a0000
+#define NV_ADDRESS_MAP_XUSB_HOST_VF0_BAR0_DB_LIMIT 0x036affff
+#define NV_ADDRESS_MAP_XUSB_HOST_VF0_BAR0_DB_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_VF0_BAR0_DB_HEADER
+
+#define NV_ADDRESS_MAP_XUSB_HOST_VF1_CFG_BASE 0x036b0000
+#define NV_ADDRESS_MAP_XUSB_HOST_VF1_CFG_LIMIT 0x036bffff
+#define NV_ADDRESS_MAP_XUSB_HOST_VF1_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_VF1_CFG_HEADER ardev_t_fpci_xusb_0.h
+
+#define NV_ADDRESS_MAP_XUSB_HOST_VF1_BAR0_OP_BASE 0x036c0000
+#define NV_ADDRESS_MAP_XUSB_HOST_VF1_BAR0_OP_LIMIT 0x036dffff
+#define NV_ADDRESS_MAP_XUSB_HOST_VF1_BAR0_OP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_VF1_BAR0_OP_HEADER
+
+#define NV_ADDRESS_MAP_XUSB_HOST_VF1_BAR0_RT_BASE 0x036e0000
+#define NV_ADDRESS_MAP_XUSB_HOST_VF1_BAR0_RT_LIMIT 0x036effff
+#define NV_ADDRESS_MAP_XUSB_HOST_VF1_BAR0_RT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_VF1_BAR0_RT_HEADER
+
+#define NV_ADDRESS_MAP_XUSB_HOST_VF1_BAR0_DB_BASE 0x036f0000
+#define NV_ADDRESS_MAP_XUSB_HOST_VF1_BAR0_DB_LIMIT 0x036fffff
+#define NV_ADDRESS_MAP_XUSB_HOST_VF1_BAR0_DB_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_VF1_BAR0_DB_HEADER
+
+#define NV_ADDRESS_MAP_XUSB_HOST_VF2_CFG_BASE 0x03700000
+#define NV_ADDRESS_MAP_XUSB_HOST_VF2_CFG_LIMIT 0x0370ffff
+#define NV_ADDRESS_MAP_XUSB_HOST_VF2_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_VF2_CFG_HEADER ardev_t_fpci_xusb_0.h
+
+#define NV_ADDRESS_MAP_XUSB_HOST_VF2_BAR0_OP_BASE 0x03710000
+#define NV_ADDRESS_MAP_XUSB_HOST_VF2_BAR0_OP_LIMIT 0x0372ffff
+#define NV_ADDRESS_MAP_XUSB_HOST_VF2_BAR0_OP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_VF2_BAR0_OP_HEADER
+
+#define NV_ADDRESS_MAP_XUSB_HOST_VF2_BAR0_RT_BASE 0x03730000
+#define NV_ADDRESS_MAP_XUSB_HOST_VF2_BAR0_RT_LIMIT 0x0373ffff
+#define NV_ADDRESS_MAP_XUSB_HOST_VF2_BAR0_RT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_VF2_BAR0_RT_HEADER
+
+#define NV_ADDRESS_MAP_XUSB_HOST_VF2_BAR0_DB_BASE 0x03740000
+#define NV_ADDRESS_MAP_XUSB_HOST_VF2_BAR0_DB_LIMIT 0x0374ffff
+#define NV_ADDRESS_MAP_XUSB_HOST_VF2_BAR0_DB_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_VF2_BAR0_DB_HEADER
+
+#define NV_ADDRESS_MAP_XUSB_HOST_VF3_CFG_BASE 0x03750000
+#define NV_ADDRESS_MAP_XUSB_HOST_VF3_CFG_LIMIT 0x0375ffff
+#define NV_ADDRESS_MAP_XUSB_HOST_VF3_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_VF3_CFG_HEADER ardev_t_fpci_xusb_0.h
+
+#define NV_ADDRESS_MAP_XUSB_HOST_VF3_BAR0_OP_BASE 0x03760000
+#define NV_ADDRESS_MAP_XUSB_HOST_VF3_BAR0_OP_LIMIT 0x0377ffff
+#define NV_ADDRESS_MAP_XUSB_HOST_VF3_BAR0_OP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_VF3_BAR0_OP_HEADER
+
+#define NV_ADDRESS_MAP_XUSB_HOST_VF3_BAR0_RT_BASE 0x03780000
+#define NV_ADDRESS_MAP_XUSB_HOST_VF3_BAR0_RT_LIMIT 0x0378ffff
+#define NV_ADDRESS_MAP_XUSB_HOST_VF3_BAR0_RT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_VF3_BAR0_RT_HEADER
+
+#define NV_ADDRESS_MAP_XUSB_HOST_VF3_BAR0_DB_BASE 0x03790000
+#define NV_ADDRESS_MAP_XUSB_HOST_VF3_BAR0_DB_LIMIT 0x0379ffff
+#define NV_ADDRESS_MAP_XUSB_HOST_VF3_BAR0_DB_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_XUSB_HOST_VF3_BAR0_DB_HEADER
+
+#define NV_ADDRESS_MAP_PEXCLK0_BASE 0x037a0000
+#define NV_ADDRESS_MAP_PEXCLK0_LIMIT 0x037a0fff
+#define NV_ADDRESS_MAP_PEXCLK0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PEXCLK0_HEADER arpcie_pexclk_padctl0.h
+
+#define NV_ADDRESS_MAP_PEXCLK2_BASE 0x037a1000
+#define NV_ADDRESS_MAP_PEXCLK2_LIMIT 0x037a1fff
+#define NV_ADDRESS_MAP_PEXCLK2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PEXCLK2_HEADER arpcie_pexclk_padctl2.h
+
+#define NV_ADDRESS_MAP_CV0_POD_BASE 0x037a3000
+#define NV_ADDRESS_MAP_CV0_POD_LIMIT 0x037a3fff
+#define NV_ADDRESS_MAP_CV0_POD_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CV0_POD_HEADER no_headers
+
+#define NV_ADDRESS_MAP_CV1_POD_BASE 0x037a4000
+#define NV_ADDRESS_MAP_CV1_POD_LIMIT 0x037a4fff
+#define NV_ADDRESS_MAP_CV1_POD_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CV1_POD_HEADER no_headers
+
+#define NV_ADDRESS_MAP_CV2_POD_BASE 0x037a5000
+#define NV_ADDRESS_MAP_CV2_POD_LIMIT 0x037a5fff
+#define NV_ADDRESS_MAP_CV2_POD_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CV2_POD_HEADER no_headers
+
+#define NV_ADDRESS_MAP_PEXCLK1_BASE 0x037a7000
+#define NV_ADDRESS_MAP_PEXCLK1_LIMIT 0x037a7fff
+#define NV_ADDRESS_MAP_PEXCLK1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PEXCLK1_HEADER arpcie_pexclk_padctl1.h
+
+#define NV_ADDRESS_MAP_MIPI_CAL_BASE 0x03990000
+#define NV_ADDRESS_MAP_MIPI_CAL_LIMIT 0x0399ffff
+#define NV_ADDRESS_MAP_MIPI_CAL_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MIPI_CAL_HEADER armipi_cal.h
+
+#define NV_ADDRESS_MAP_TACH_1_BASE 0x039b0000
+#define NV_ADDRESS_MAP_TACH_1_LIMIT 0x039bffff
+#define NV_ADDRESS_MAP_TACH_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TACH_1_HEADER artach.h
+
+#define NV_ADDRESS_MAP_TACH_0_BASE 0x039c0000
+#define NV_ADDRESS_MAP_TACH_0_LIMIT 0x039cffff
+#define NV_ADDRESS_MAP_TACH_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TACH_0_HEADER artach.h
+
+#define NV_ADDRESS_MAP_LIC_GTE0_BASE 0x03aa0000
+#define NV_ADDRESS_MAP_LIC_GTE0_LIMIT 0x03aaffff
+#define NV_ADDRESS_MAP_LIC_GTE0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_LIC_GTE0_HEADER argte_intr_ctlr.h;argte_intr_ctlr_scr.h
+
+#define NV_ADDRESS_MAP_LIC_GTE1_BASE 0x03ab0000
+#define NV_ADDRESS_MAP_LIC_GTE1_LIMIT 0x03abffff
+#define NV_ADDRESS_MAP_LIC_GTE1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_LIC_GTE1_HEADER argte_intr_ctlr.h;argte_intr_ctlr_scr.h
+
+#define NV_ADDRESS_MAP_TOP0_HSP_COMMON_BASE 0x03c00000
+#define NV_ADDRESS_MAP_TOP0_HSP_COMMON_LIMIT 0x03c0ffff
+#define NV_ADDRESS_MAP_TOP0_HSP_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP0_HSP_COMMON_HEADER arhsp_int.h;arhsp_int_scr.h
+
+#define NV_ADDRESS_MAP_TOP0_HSP_SM_0_1_BASE 0x03c10000
+#define NV_ADDRESS_MAP_TOP0_HSP_SM_0_1_LIMIT 0x03c1ffff
+#define NV_ADDRESS_MAP_TOP0_HSP_SM_0_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP0_HSP_SM_0_1_HEADER
+
+#define NV_ADDRESS_MAP_TOP0_HSP_SM_2_3_BASE 0x03c20000
+#define NV_ADDRESS_MAP_TOP0_HSP_SM_2_3_LIMIT 0x03c2ffff
+#define NV_ADDRESS_MAP_TOP0_HSP_SM_2_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP0_HSP_SM_2_3_HEADER
+
+#define NV_ADDRESS_MAP_TOP0_HSP_SM_4_5_BASE 0x03c30000
+#define NV_ADDRESS_MAP_TOP0_HSP_SM_4_5_LIMIT 0x03c3ffff
+#define NV_ADDRESS_MAP_TOP0_HSP_SM_4_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP0_HSP_SM_4_5_HEADER
+
+#define NV_ADDRESS_MAP_TOP0_HSP_SM_6_7_BASE 0x03c40000
+#define NV_ADDRESS_MAP_TOP0_HSP_SM_6_7_LIMIT 0x03c4ffff
+#define NV_ADDRESS_MAP_TOP0_HSP_SM_6_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP0_HSP_SM_6_7_HEADER
+
+#define NV_ADDRESS_MAP_TOP0_HSP_SS_0_BASE 0x03c50000
+#define NV_ADDRESS_MAP_TOP0_HSP_SS_0_LIMIT 0x03c5ffff
+#define NV_ADDRESS_MAP_TOP0_HSP_SS_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP0_HSP_SS_0_HEADER
+
+#define NV_ADDRESS_MAP_TOP0_HSP_SS_1_BASE 0x03c60000
+#define NV_ADDRESS_MAP_TOP0_HSP_SS_1_LIMIT 0x03c6ffff
+#define NV_ADDRESS_MAP_TOP0_HSP_SS_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP0_HSP_SS_1_HEADER
+
+#define NV_ADDRESS_MAP_TOP0_HSP_AS_0_BASE 0x03c70000
+#define NV_ADDRESS_MAP_TOP0_HSP_AS_0_LIMIT 0x03c7ffff
+#define NV_ADDRESS_MAP_TOP0_HSP_AS_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP0_HSP_AS_0_HEADER
+
+#define NV_ADDRESS_MAP_TOP0_HSP_AS_1_BASE 0x03c80000
+#define NV_ADDRESS_MAP_TOP0_HSP_AS_1_LIMIT 0x03c8ffff
+#define NV_ADDRESS_MAP_TOP0_HSP_AS_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP0_HSP_AS_1_HEADER
+
+#define NV_ADDRESS_MAP_TOP0_HSP_DB_0_BASE 0x03c90000
+#define NV_ADDRESS_MAP_TOP0_HSP_DB_0_LIMIT 0x03c9ffff
+#define NV_ADDRESS_MAP_TOP0_HSP_DB_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP0_HSP_DB_0_HEADER
+
+#define NV_ADDRESS_MAP_TOP1_HSP_COMMON_BASE 0x03d00000
+#define NV_ADDRESS_MAP_TOP1_HSP_COMMON_LIMIT 0x03d0ffff
+#define NV_ADDRESS_MAP_TOP1_HSP_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP1_HSP_COMMON_HEADER arhsp_int.h;arhsp_int_scr.h
+
+#define NV_ADDRESS_MAP_TOP1_HSP_SM_0_1_BASE 0x03d10000
+#define NV_ADDRESS_MAP_TOP1_HSP_SM_0_1_LIMIT 0x03d1ffff
+#define NV_ADDRESS_MAP_TOP1_HSP_SM_0_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP1_HSP_SM_0_1_HEADER
+
+#define NV_ADDRESS_MAP_TOP1_HSP_SM_2_3_BASE 0x03d20000
+#define NV_ADDRESS_MAP_TOP1_HSP_SM_2_3_LIMIT 0x03d2ffff
+#define NV_ADDRESS_MAP_TOP1_HSP_SM_2_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP1_HSP_SM_2_3_HEADER
+
+#define NV_ADDRESS_MAP_TOP1_HSP_SM_4_5_BASE 0x03d30000
+#define NV_ADDRESS_MAP_TOP1_HSP_SM_4_5_LIMIT 0x03d3ffff
+#define NV_ADDRESS_MAP_TOP1_HSP_SM_4_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP1_HSP_SM_4_5_HEADER
+
+#define NV_ADDRESS_MAP_TOP1_HSP_SM_6_7_BASE 0x03d40000
+#define NV_ADDRESS_MAP_TOP1_HSP_SM_6_7_LIMIT 0x03d4ffff
+#define NV_ADDRESS_MAP_TOP1_HSP_SM_6_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP1_HSP_SM_6_7_HEADER
+
+#define NV_ADDRESS_MAP_TOP1_HSP_SS_0_BASE 0x03d50000
+#define NV_ADDRESS_MAP_TOP1_HSP_SS_0_LIMIT 0x03d5ffff
+#define NV_ADDRESS_MAP_TOP1_HSP_SS_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP1_HSP_SS_0_HEADER
+
+#define NV_ADDRESS_MAP_TOP1_HSP_SS_1_BASE 0x03d60000
+#define NV_ADDRESS_MAP_TOP1_HSP_SS_1_LIMIT 0x03d6ffff
+#define NV_ADDRESS_MAP_TOP1_HSP_SS_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP1_HSP_SS_1_HEADER
+
+#define NV_ADDRESS_MAP_TOP1_HSP_SS_2_BASE 0x03d70000
+#define NV_ADDRESS_MAP_TOP1_HSP_SS_2_LIMIT 0x03d7ffff
+#define NV_ADDRESS_MAP_TOP1_HSP_SS_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP1_HSP_SS_2_HEADER
+
+#define NV_ADDRESS_MAP_TOP1_HSP_SS_3_BASE 0x03d80000
+#define NV_ADDRESS_MAP_TOP1_HSP_SS_3_LIMIT 0x03d8ffff
+#define NV_ADDRESS_MAP_TOP1_HSP_SS_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TOP1_HSP_SS_3_HEADER
+
+#define NV_ADDRESS_MAP_P2U_HSIO_0_BASE 0x03e00000
+#define NV_ADDRESS_MAP_P2U_HSIO_0_LIMIT 0x03e0ffff
+#define NV_ADDRESS_MAP_P2U_HSIO_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_HSIO_0_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_HSIO_1_BASE 0x03e10000
+#define NV_ADDRESS_MAP_P2U_HSIO_1_LIMIT 0x03e1ffff
+#define NV_ADDRESS_MAP_P2U_HSIO_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_HSIO_1_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_HSIO_2_BASE 0x03e20000
+#define NV_ADDRESS_MAP_P2U_HSIO_2_LIMIT 0x03e2ffff
+#define NV_ADDRESS_MAP_P2U_HSIO_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_HSIO_2_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_HSIO_3_BASE 0x03e30000
+#define NV_ADDRESS_MAP_P2U_HSIO_3_LIMIT 0x03e3ffff
+#define NV_ADDRESS_MAP_P2U_HSIO_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_HSIO_3_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_HSIO_4_BASE 0x03e40000
+#define NV_ADDRESS_MAP_P2U_HSIO_4_LIMIT 0x03e4ffff
+#define NV_ADDRESS_MAP_P2U_HSIO_4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_HSIO_4_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_HSIO_5_BASE 0x03e50000
+#define NV_ADDRESS_MAP_P2U_HSIO_5_LIMIT 0x03e5ffff
+#define NV_ADDRESS_MAP_P2U_HSIO_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_HSIO_5_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_HSIO_6_BASE 0x03e60000
+#define NV_ADDRESS_MAP_P2U_HSIO_6_LIMIT 0x03e6ffff
+#define NV_ADDRESS_MAP_P2U_HSIO_6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_HSIO_6_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_HSIO_7_BASE 0x03e70000
+#define NV_ADDRESS_MAP_P2U_HSIO_7_LIMIT 0x03e7ffff
+#define NV_ADDRESS_MAP_P2U_HSIO_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_HSIO_7_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_HSIO_XBAR_BASE 0x03e80000
+#define NV_ADDRESS_MAP_P2U_HSIO_XBAR_LIMIT 0x03e8ffff
+#define NV_ADDRESS_MAP_P2U_HSIO_XBAR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_HSIO_XBAR_HEADER arpcie_hsio_common.h
+
+#define NV_ADDRESS_MAP_P2U_NVHS_0_BASE 0x03e90000
+#define NV_ADDRESS_MAP_P2U_NVHS_0_LIMIT 0x03e9ffff
+#define NV_ADDRESS_MAP_P2U_NVHS_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_NVHS_0_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_NVHS_1_BASE 0x03ea0000
+#define NV_ADDRESS_MAP_P2U_NVHS_1_LIMIT 0x03eaffff
+#define NV_ADDRESS_MAP_P2U_NVHS_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_NVHS_1_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_NVHS_2_BASE 0x03eb0000
+#define NV_ADDRESS_MAP_P2U_NVHS_2_LIMIT 0x03ebffff
+#define NV_ADDRESS_MAP_P2U_NVHS_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_NVHS_2_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_NVHS_3_BASE 0x03ec0000
+#define NV_ADDRESS_MAP_P2U_NVHS_3_LIMIT 0x03ecffff
+#define NV_ADDRESS_MAP_P2U_NVHS_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_NVHS_3_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_NVHS_4_BASE 0x03ed0000
+#define NV_ADDRESS_MAP_P2U_NVHS_4_LIMIT 0x03edffff
+#define NV_ADDRESS_MAP_P2U_NVHS_4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_NVHS_4_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_NVHS_5_BASE 0x03ee0000
+#define NV_ADDRESS_MAP_P2U_NVHS_5_LIMIT 0x03eeffff
+#define NV_ADDRESS_MAP_P2U_NVHS_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_NVHS_5_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_NVHS_6_BASE 0x03ef0000
+#define NV_ADDRESS_MAP_P2U_NVHS_6_LIMIT 0x03efffff
+#define NV_ADDRESS_MAP_P2U_NVHS_6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_NVHS_6_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_NVHS_7_BASE 0x03f00000
+#define NV_ADDRESS_MAP_P2U_NVHS_7_LIMIT 0x03f0ffff
+#define NV_ADDRESS_MAP_P2U_NVHS_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_NVHS_7_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_NVHS_XBAR_BASE 0x03f10000
+#define NV_ADDRESS_MAP_P2U_NVHS_XBAR_LIMIT 0x03f1ffff
+#define NV_ADDRESS_MAP_P2U_NVHS_XBAR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_NVHS_XBAR_HEADER arpcie_nvhs_common.h
+
+#define NV_ADDRESS_MAP_P2U_GBE_0_BASE 0x03f20000
+#define NV_ADDRESS_MAP_P2U_GBE_0_LIMIT 0x03f2ffff
+#define NV_ADDRESS_MAP_P2U_GBE_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_GBE_0_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_GBE_1_BASE 0x03f30000
+#define NV_ADDRESS_MAP_P2U_GBE_1_LIMIT 0x03f3ffff
+#define NV_ADDRESS_MAP_P2U_GBE_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_GBE_1_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_GBE_2_BASE 0x03f40000
+#define NV_ADDRESS_MAP_P2U_GBE_2_LIMIT 0x03f4ffff
+#define NV_ADDRESS_MAP_P2U_GBE_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_GBE_2_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_GBE_3_BASE 0x03f50000
+#define NV_ADDRESS_MAP_P2U_GBE_3_LIMIT 0x03f5ffff
+#define NV_ADDRESS_MAP_P2U_GBE_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_GBE_3_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_GBE_4_BASE 0x03f60000
+#define NV_ADDRESS_MAP_P2U_GBE_4_LIMIT 0x03f6ffff
+#define NV_ADDRESS_MAP_P2U_GBE_4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_GBE_4_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_GBE_5_BASE 0x03f70000
+#define NV_ADDRESS_MAP_P2U_GBE_5_LIMIT 0x03f7ffff
+#define NV_ADDRESS_MAP_P2U_GBE_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_GBE_5_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_GBE_6_BASE 0x03f80000
+#define NV_ADDRESS_MAP_P2U_GBE_6_LIMIT 0x03f8ffff
+#define NV_ADDRESS_MAP_P2U_GBE_6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_GBE_6_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_GBE_7_BASE 0x03f90000
+#define NV_ADDRESS_MAP_P2U_GBE_7_LIMIT 0x03f9ffff
+#define NV_ADDRESS_MAP_P2U_GBE_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_GBE_7_HEADER dev_t_pcie_pipe2uphy.ref
+
+#define NV_ADDRESS_MAP_P2U_GBE_XBAR_BASE 0x03fa0000
+#define NV_ADDRESS_MAP_P2U_GBE_XBAR_LIMIT 0x03faffff
+#define NV_ADDRESS_MAP_P2U_GBE_XBAR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_P2U_GBE_XBAR_HEADER arpcie_gbe_common.h
+
+#define NV_ADDRESS_MAP_MGBE0_MAC_HV_BASE 0x06800000
+#define NV_ADDRESS_MAP_MGBE0_MAC_HV_LIMIT 0x0680ffff
+#define NV_ADDRESS_MAP_MGBE0_MAC_HV_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MAC_HV_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE0_MAC_RM_CFG_BASE 0x06810000
+#define NV_ADDRESS_MAP_MGBE0_MAC_RM_CFG_LIMIT 0x0681efff
+#define NV_ADDRESS_MAP_MGBE0_MAC_RM_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MAC_RM_CFG_HEADER
+
+#define NV_ADDRESS_MAP_MGBE0_MAC_RM_ERR_BASE 0x0681f000
+#define NV_ADDRESS_MAP_MGBE0_MAC_RM_ERR_LIMIT 0x0681ffff
+#define NV_ADDRESS_MAP_MGBE0_MAC_RM_ERR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MAC_RM_ERR_HEADER
+
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM0_BASE 0x06820000
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM0_LIMIT 0x0682ffff
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM0_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM1_BASE 0x06830000
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM1_LIMIT 0x0683ffff
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM1_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM2_BASE 0x06840000
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM2_LIMIT 0x0684ffff
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM2_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM3_BASE 0x06850000
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM3_LIMIT 0x0685ffff
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM3_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM4_BASE 0x06860000
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM4_LIMIT 0x0686ffff
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM4_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM5_BASE 0x06870000
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM5_LIMIT 0x0687ffff
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM5_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM6_BASE 0x06880000
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM6_LIMIT 0x0688ffff
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM6_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM7_BASE 0x06890000
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM7_LIMIT 0x0689ffff
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MAC_VM7_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE0_PCS_RM_BASE 0x068a0000
+#define NV_ADDRESS_MAP_MGBE0_PCS_RM_LIMIT 0x068affff
+#define NV_ADDRESS_MAP_MGBE0_PCS_RM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_PCS_RM_HEADER armgbe_pcs.h;armgbe_pcs_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_TZ_BASE 0x068c0000
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_TZ_LIMIT 0x068cffff
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_TZ_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_TZ_HEADER armacsec.h
+
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_RM_CFG_BASE 0x068d0000
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_RM_CFG_LIMIT 0x068dcfff
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_RM_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_RM_CFG_HEADER
+
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_RM_TX_BYP_BASE 0x068dd000
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_RM_TX_BYP_LIMIT 0x068ddfff
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_RM_TX_BYP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_RM_TX_BYP_HEADER
+
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_RM_RX_BYP_BASE 0x068de000
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_RM_RX_BYP_LIMIT 0x068defff
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_RM_RX_BYP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_RM_RX_BYP_HEADER
+
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_RM_ERR_BASE 0x068df000
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_RM_ERR_LIMIT 0x068dffff
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_RM_ERR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_RM_ERR_HEADER
+
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_VM_STATS_BASE 0x068e0000
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_VM_STATS_LIMIT 0x068eefff
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_VM_STATS_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_VM_STATS_HEADER
+
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_VM_STS_ERR_BASE 0x068ef000
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_VM_STS_ERR_LIMIT 0x068effff
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_VM_STS_ERR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE0_MACSEC_VM_STS_ERR_HEADER
+
+#define NV_ADDRESS_MAP_MGBE1_MAC_HV_BASE 0x06900000
+#define NV_ADDRESS_MAP_MGBE1_MAC_HV_LIMIT 0x0690ffff
+#define NV_ADDRESS_MAP_MGBE1_MAC_HV_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MAC_HV_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE1_MAC_RM_CFG_BASE 0x06910000
+#define NV_ADDRESS_MAP_MGBE1_MAC_RM_CFG_LIMIT 0x0691efff
+#define NV_ADDRESS_MAP_MGBE1_MAC_RM_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MAC_RM_CFG_HEADER
+
+#define NV_ADDRESS_MAP_MGBE1_MAC_RM_ERR_BASE 0x0691f000
+#define NV_ADDRESS_MAP_MGBE1_MAC_RM_ERR_LIMIT 0x0691ffff
+#define NV_ADDRESS_MAP_MGBE1_MAC_RM_ERR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MAC_RM_ERR_HEADER
+
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM0_BASE 0x06920000
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM0_LIMIT 0x0692ffff
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM0_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM1_BASE 0x06930000
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM1_LIMIT 0x0693ffff
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM1_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM2_BASE 0x06940000
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM2_LIMIT 0x0694ffff
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM2_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM3_BASE 0x06950000
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM3_LIMIT 0x0695ffff
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM3_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM4_BASE 0x06960000
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM4_LIMIT 0x0696ffff
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM4_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM5_BASE 0x06970000
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM5_LIMIT 0x0697ffff
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM5_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM6_BASE 0x06980000
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM6_LIMIT 0x0698ffff
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM6_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM7_BASE 0x06990000
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM7_LIMIT 0x0699ffff
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MAC_VM7_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE1_PCS_RM_BASE 0x069a0000
+#define NV_ADDRESS_MAP_MGBE1_PCS_RM_LIMIT 0x069affff
+#define NV_ADDRESS_MAP_MGBE1_PCS_RM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_PCS_RM_HEADER armgbe_pcs.h;armgbe_pcs_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_TZ_BASE 0x069c0000
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_TZ_LIMIT 0x069cffff
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_TZ_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_TZ_HEADER armacsec.h
+
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_RM_CFG_BASE 0x069d0000
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_RM_CFG_LIMIT 0x069dcfff
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_RM_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_RM_CFG_HEADER
+
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_RM_TX_BYP_BASE 0x069dd000
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_RM_TX_BYP_LIMIT 0x069ddfff
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_RM_TX_BYP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_RM_TX_BYP_HEADER
+
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_RM_RX_BYP_BASE 0x069de000
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_RM_RX_BYP_LIMIT 0x069defff
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_RM_RX_BYP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_RM_RX_BYP_HEADER
+
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_RM_ERR_BASE 0x069df000
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_RM_ERR_LIMIT 0x069dffff
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_RM_ERR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_RM_ERR_HEADER
+
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_VM_STATS_BASE 0x069e0000
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_VM_STATS_LIMIT 0x069eefff
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_VM_STATS_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_VM_STATS_HEADER
+
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_VM_STS_ERR_BASE 0x069ef000
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_VM_STS_ERR_LIMIT 0x069effff
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_VM_STS_ERR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE1_MACSEC_VM_STS_ERR_HEADER
+
+#define NV_ADDRESS_MAP_MGBE2_MAC_HV_BASE 0x06a00000
+#define NV_ADDRESS_MAP_MGBE2_MAC_HV_LIMIT 0x06a0ffff
+#define NV_ADDRESS_MAP_MGBE2_MAC_HV_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MAC_HV_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE2_MAC_RM_CFG_BASE 0x06a10000
+#define NV_ADDRESS_MAP_MGBE2_MAC_RM_CFG_LIMIT 0x06a1efff
+#define NV_ADDRESS_MAP_MGBE2_MAC_RM_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MAC_RM_CFG_HEADER
+
+#define NV_ADDRESS_MAP_MGBE2_MAC_RM_ERR_BASE 0x06a1f000
+#define NV_ADDRESS_MAP_MGBE2_MAC_RM_ERR_LIMIT 0x06a1ffff
+#define NV_ADDRESS_MAP_MGBE2_MAC_RM_ERR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MAC_RM_ERR_HEADER
+
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM0_BASE 0x06a20000
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM0_LIMIT 0x06a2ffff
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM0_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM1_BASE 0x06a30000
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM1_LIMIT 0x06a3ffff
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM1_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM2_BASE 0x06a40000
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM2_LIMIT 0x06a4ffff
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM2_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM3_BASE 0x06a50000
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM3_LIMIT 0x06a5ffff
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM3_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM4_BASE 0x06a60000
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM4_LIMIT 0x06a6ffff
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM4_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM5_BASE 0x06a70000
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM5_LIMIT 0x06a7ffff
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM5_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM6_BASE 0x06a80000
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM6_LIMIT 0x06a8ffff
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM6_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM7_BASE 0x06a90000
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM7_LIMIT 0x06a9ffff
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MAC_VM7_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE2_PCS_RM_BASE 0x06aa0000
+#define NV_ADDRESS_MAP_MGBE2_PCS_RM_LIMIT 0x06aaffff
+#define NV_ADDRESS_MAP_MGBE2_PCS_RM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_PCS_RM_HEADER armgbe_pcs.h;armgbe_pcs_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_TZ_BASE 0x06ac0000
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_TZ_LIMIT 0x06acffff
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_TZ_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_TZ_HEADER armacsec.h
+
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_RM_CFG_BASE 0x06ad0000
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_RM_CFG_LIMIT 0x06adcfff
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_RM_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_RM_CFG_HEADER
+
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_RM_TX_BYP_BASE 0x06add000
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_RM_TX_BYP_LIMIT 0x06addfff
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_RM_TX_BYP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_RM_TX_BYP_HEADER
+
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_RM_RX_BYP_BASE 0x06ade000
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_RM_RX_BYP_LIMIT 0x06adefff
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_RM_RX_BYP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_RM_RX_BYP_HEADER
+
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_RM_ERR_BASE 0x06adf000
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_RM_ERR_LIMIT 0x06adffff
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_RM_ERR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_RM_ERR_HEADER
+
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_VM_STATS_BASE 0x06ae0000
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_VM_STATS_LIMIT 0x06aeefff
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_VM_STATS_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_VM_STATS_HEADER
+
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_VM_STS_ERR_BASE 0x06aef000
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_VM_STS_ERR_LIMIT 0x06aeffff
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_VM_STS_ERR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE2_MACSEC_VM_STS_ERR_HEADER
+
+#define NV_ADDRESS_MAP_MGBE3_MAC_HV_BASE 0x06b00000
+#define NV_ADDRESS_MAP_MGBE3_MAC_HV_LIMIT 0x06b0ffff
+#define NV_ADDRESS_MAP_MGBE3_MAC_HV_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MAC_HV_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE3_MAC_RM_CFG_BASE 0x06b10000
+#define NV_ADDRESS_MAP_MGBE3_MAC_RM_CFG_LIMIT 0x06b1efff
+#define NV_ADDRESS_MAP_MGBE3_MAC_RM_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MAC_RM_CFG_HEADER
+
+#define NV_ADDRESS_MAP_MGBE3_MAC_RM_ERR_BASE 0x06b1f000
+#define NV_ADDRESS_MAP_MGBE3_MAC_RM_ERR_LIMIT 0x06b1ffff
+#define NV_ADDRESS_MAP_MGBE3_MAC_RM_ERR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MAC_RM_ERR_HEADER
+
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM0_BASE 0x06b20000
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM0_LIMIT 0x06b2ffff
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM0_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM1_BASE 0x06b30000
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM1_LIMIT 0x06b3ffff
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM1_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM2_BASE 0x06b40000
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM2_LIMIT 0x06b4ffff
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM2_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM3_BASE 0x06b50000
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM3_LIMIT 0x06b5ffff
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM3_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM4_BASE 0x06b60000
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM4_LIMIT 0x06b6ffff
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM4_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM5_BASE 0x06b70000
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM5_LIMIT 0x06b7ffff
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM5_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM6_BASE 0x06b80000
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM6_LIMIT 0x06b8ffff
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM6_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM7_BASE 0x06b90000
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM7_LIMIT 0x06b9ffff
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MAC_VM7_HEADER armgbe_mac.h;armgbe_mac_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE3_PCS_RM_BASE 0x06ba0000
+#define NV_ADDRESS_MAP_MGBE3_PCS_RM_LIMIT 0x06baffff
+#define NV_ADDRESS_MAP_MGBE3_PCS_RM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_PCS_RM_HEADER armgbe_pcs.h;armgbe_pcs_wrapper.h
+
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_TZ_BASE 0x06bc0000
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_TZ_LIMIT 0x06bcffff
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_TZ_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_TZ_HEADER armacsec.h
+
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_RM_CFG_BASE 0x06bd0000
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_RM_CFG_LIMIT 0x06bdcfff
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_RM_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_RM_CFG_HEADER
+
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_RM_TX_BYP_BASE 0x06bdd000
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_RM_TX_BYP_LIMIT 0x06bddfff
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_RM_TX_BYP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_RM_TX_BYP_HEADER
+
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_RM_RX_BYP_BASE 0x06bde000
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_RM_RX_BYP_LIMIT 0x06bdefff
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_RM_RX_BYP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_RM_RX_BYP_HEADER
+
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_RM_ERR_BASE 0x06bdf000
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_RM_ERR_LIMIT 0x06bdffff
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_RM_ERR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_RM_ERR_HEADER
+
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_VM_STATS_BASE 0x06be0000
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_VM_STATS_LIMIT 0x06beefff
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_VM_STATS_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_VM_STATS_HEADER
+
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_VM_STS_ERR_BASE 0x06bef000
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_VM_STS_ERR_LIMIT 0x06beffff
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_VM_STS_ERR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MGBE3_MACSEC_VM_STS_ERR_HEADER
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_GR0_BASE 0x07000000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_GR0_LIMIT 0x0700ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_GR0_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_GR0_HEADER arm_smmu_500_global.h;arm_smmu_500_global_sec.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_GR0_BASE 0x07000000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_GR0_LIMIT 0x07000fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_GR0_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_GR0_HEADER arm_smmu_500_global.h;arm_smmu_500_global_sec.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_GR1_BASE 0x07001000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_GR1_LIMIT 0x07001fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_GR1_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_GR1_HEADER arm_smmu_500_global_1.h;arm_smmu_500_global_sec_1.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_GID_BASE 0x07002000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_GID_LIMIT 0x07002fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_GID_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_GID_HEADER arm_smmu_500_integ_sec.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_PM_BASE 0x07003000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_PM_LIMIT 0x07003fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_PM_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_PM_HEADER arm_smmu_500_perf_mon.h;arm_smmu_500_perf_mon_sec.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_GR1_BASE 0x07010000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_GR1_LIMIT 0x0701ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_GR1_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_GR1_HEADER arm_smmu_500_global_1.h;arm_smmu_500_global_sec_1.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_GID_BASE 0x07020000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_GID_LIMIT 0x0702ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_GID_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_GID_HEADER arm_smmu_500_integ_sec.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_PM_BASE 0x07030000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_PM_LIMIT 0x0703ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_PM_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_PM_HEADER arm_smmu_500_perf_mon.h;arm_smmu_500_perf_mon_sec.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB0_BASE 0x07080000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB0_LIMIT 0x07080fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB0_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB0_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB1_BASE 0x07081000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB1_LIMIT 0x07081fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB1_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB1_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB2_BASE 0x07082000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB2_LIMIT 0x07082fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB2_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB2_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB3_BASE 0x07083000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB3_LIMIT 0x07083fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB3_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB3_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB4_BASE 0x07084000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB4_LIMIT 0x07084fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB4_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB4_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB5_BASE 0x07085000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB5_LIMIT 0x07085fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB5_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB5_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB6_BASE 0x07086000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB6_LIMIT 0x07086fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB6_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB6_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB7_BASE 0x07087000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB7_LIMIT 0x07087fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB7_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB7_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB8_BASE 0x07088000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB8_LIMIT 0x07088fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB8_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB8_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB9_BASE 0x07089000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB9_LIMIT 0x07089fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB9_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB9_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB10_BASE 0x0708a000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB10_LIMIT 0x0708afff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB10_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB10_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB11_BASE 0x0708b000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB11_LIMIT 0x0708bfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB11_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB11_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB12_BASE 0x0708c000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB12_LIMIT 0x0708cfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB12_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB12_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB13_BASE 0x0708d000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB13_LIMIT 0x0708dfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB13_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB13_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB14_BASE 0x0708e000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB14_LIMIT 0x0708efff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB14_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB14_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB15_BASE 0x0708f000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB15_LIMIT 0x0708ffff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB15_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB15_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB16_BASE 0x07090000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB16_LIMIT 0x07090fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB16_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB16_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB17_BASE 0x07091000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB17_LIMIT 0x07091fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB17_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB17_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB18_BASE 0x07092000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB18_LIMIT 0x07092fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB18_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB18_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB19_BASE 0x07093000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB19_LIMIT 0x07093fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB19_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB19_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB20_BASE 0x07094000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB20_LIMIT 0x07094fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB20_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB20_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB21_BASE 0x07095000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB21_LIMIT 0x07095fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB21_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB21_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB22_BASE 0x07096000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB22_LIMIT 0x07096fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB22_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB22_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB23_BASE 0x07097000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB23_LIMIT 0x07097fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB23_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB23_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB24_BASE 0x07098000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB24_LIMIT 0x07098fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB24_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB24_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB25_BASE 0x07099000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB25_LIMIT 0x07099fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB25_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB25_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB26_BASE 0x0709a000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB26_LIMIT 0x0709afff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB26_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB26_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB27_BASE 0x0709b000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB27_LIMIT 0x0709bfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB27_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB27_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB28_BASE 0x0709c000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB28_LIMIT 0x0709cfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB28_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB28_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB29_BASE 0x0709d000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB29_LIMIT 0x0709dfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB29_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB29_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB30_BASE 0x0709e000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB30_LIMIT 0x0709efff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB30_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB30_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB31_BASE 0x0709f000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB31_LIMIT 0x0709ffff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB31_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB31_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB32_BASE 0x070a0000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB32_LIMIT 0x070a0fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB32_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB32_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB33_BASE 0x070a1000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB33_LIMIT 0x070a1fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB33_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB33_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB34_BASE 0x070a2000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB34_LIMIT 0x070a2fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB34_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB34_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB35_BASE 0x070a3000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB35_LIMIT 0x070a3fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB35_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB35_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB36_BASE 0x070a4000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB36_LIMIT 0x070a4fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB36_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB36_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB37_BASE 0x070a5000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB37_LIMIT 0x070a5fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB37_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB37_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB38_BASE 0x070a6000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB38_LIMIT 0x070a6fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB38_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB38_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB39_BASE 0x070a7000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB39_LIMIT 0x070a7fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB39_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB39_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB40_BASE 0x070a8000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB40_LIMIT 0x070a8fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB40_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB40_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB41_BASE 0x070a9000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB41_LIMIT 0x070a9fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB41_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB41_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB42_BASE 0x070aa000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB42_LIMIT 0x070aafff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB42_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB42_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB43_BASE 0x070ab000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB43_LIMIT 0x070abfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB43_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB43_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB44_BASE 0x070ac000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB44_LIMIT 0x070acfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB44_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB44_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB45_BASE 0x070ad000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB45_LIMIT 0x070adfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB45_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB45_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB46_BASE 0x070ae000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB46_LIMIT 0x070aefff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB46_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB46_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB47_BASE 0x070af000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB47_LIMIT 0x070affff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB47_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB47_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB48_BASE 0x070b0000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB48_LIMIT 0x070b0fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB48_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB48_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB49_BASE 0x070b1000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB49_LIMIT 0x070b1fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB49_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB49_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB50_BASE 0x070b2000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB50_LIMIT 0x070b2fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB50_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB50_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB51_BASE 0x070b3000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB51_LIMIT 0x070b3fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB51_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB51_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB52_BASE 0x070b4000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB52_LIMIT 0x070b4fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB52_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB52_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB53_BASE 0x070b5000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB53_LIMIT 0x070b5fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB53_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB53_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB54_BASE 0x070b6000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB54_LIMIT 0x070b6fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB54_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB54_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB55_BASE 0x070b7000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB55_LIMIT 0x070b7fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB55_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB55_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB56_BASE 0x070b8000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB56_LIMIT 0x070b8fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB56_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB56_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB57_BASE 0x070b9000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB57_LIMIT 0x070b9fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB57_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB57_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB58_BASE 0x070ba000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB58_LIMIT 0x070bafff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB58_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB58_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB59_BASE 0x070bb000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB59_LIMIT 0x070bbfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB59_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB59_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB60_BASE 0x070bc000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB60_LIMIT 0x070bcfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB60_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB60_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB61_BASE 0x070bd000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB61_LIMIT 0x070bdfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB61_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB61_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB62_BASE 0x070be000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB62_LIMIT 0x070befff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB62_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB62_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB63_BASE 0x070bf000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB63_LIMIT 0x070bffff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB63_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB63_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB64_BASE 0x070c0000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB64_LIMIT 0x070c0fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB64_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB64_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB65_BASE 0x070c1000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB65_LIMIT 0x070c1fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB65_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB65_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB66_BASE 0x070c2000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB66_LIMIT 0x070c2fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB66_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB66_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB67_BASE 0x070c3000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB67_LIMIT 0x070c3fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB67_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB67_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB68_BASE 0x070c4000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB68_LIMIT 0x070c4fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB68_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB68_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB69_BASE 0x070c5000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB69_LIMIT 0x070c5fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB69_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB69_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB70_BASE 0x070c6000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB70_LIMIT 0x070c6fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB70_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB70_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB71_BASE 0x070c7000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB71_LIMIT 0x070c7fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB71_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB71_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB72_BASE 0x070c8000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB72_LIMIT 0x070c8fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB72_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB72_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB73_BASE 0x070c9000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB73_LIMIT 0x070c9fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB73_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB73_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB74_BASE 0x070ca000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB74_LIMIT 0x070cafff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB74_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB74_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB75_BASE 0x070cb000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB75_LIMIT 0x070cbfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB75_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB75_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB76_BASE 0x070cc000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB76_LIMIT 0x070ccfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB76_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB76_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB77_BASE 0x070cd000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB77_LIMIT 0x070cdfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB77_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB77_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB78_BASE 0x070ce000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB78_LIMIT 0x070cefff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB78_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB78_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB79_BASE 0x070cf000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB79_LIMIT 0x070cffff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB79_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB79_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB80_BASE 0x070d0000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB80_LIMIT 0x070d0fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB80_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB80_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB81_BASE 0x070d1000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB81_LIMIT 0x070d1fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB81_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB81_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB82_BASE 0x070d2000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB82_LIMIT 0x070d2fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB82_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB82_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB83_BASE 0x070d3000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB83_LIMIT 0x070d3fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB83_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB83_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB84_BASE 0x070d4000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB84_LIMIT 0x070d4fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB84_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB84_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB85_BASE 0x070d5000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB85_LIMIT 0x070d5fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB85_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB85_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB86_BASE 0x070d6000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB86_LIMIT 0x070d6fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB86_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB86_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB87_BASE 0x070d7000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB87_LIMIT 0x070d7fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB87_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB87_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB88_BASE 0x070d8000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB88_LIMIT 0x070d8fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB88_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB88_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB89_BASE 0x070d9000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB89_LIMIT 0x070d9fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB89_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB89_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB90_BASE 0x070da000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB90_LIMIT 0x070dafff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB90_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB90_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB91_BASE 0x070db000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB91_LIMIT 0x070dbfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB91_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB91_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB92_BASE 0x070dc000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB92_LIMIT 0x070dcfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB92_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB92_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB93_BASE 0x070dd000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB93_LIMIT 0x070ddfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB93_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB93_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB94_BASE 0x070de000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB94_LIMIT 0x070defff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB94_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB94_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB95_BASE 0x070df000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB95_LIMIT 0x070dffff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB95_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB95_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB96_BASE 0x070e0000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB96_LIMIT 0x070e0fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB96_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB96_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB97_BASE 0x070e1000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB97_LIMIT 0x070e1fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB97_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB97_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB98_BASE 0x070e2000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB98_LIMIT 0x070e2fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB98_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB98_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB99_BASE 0x070e3000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB99_LIMIT 0x070e3fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB99_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB99_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB100_BASE 0x070e4000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB100_LIMIT 0x070e4fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB100_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB100_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB101_BASE 0x070e5000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB101_LIMIT 0x070e5fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB101_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB101_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB102_BASE 0x070e6000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB102_LIMIT 0x070e6fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB102_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB102_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB103_BASE 0x070e7000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB103_LIMIT 0x070e7fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB103_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB103_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB104_BASE 0x070e8000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB104_LIMIT 0x070e8fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB104_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB104_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB105_BASE 0x070e9000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB105_LIMIT 0x070e9fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB105_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB105_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB106_BASE 0x070ea000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB106_LIMIT 0x070eafff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB106_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB106_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB107_BASE 0x070eb000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB107_LIMIT 0x070ebfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB107_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB107_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB108_BASE 0x070ec000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB108_LIMIT 0x070ecfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB108_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB108_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB109_BASE 0x070ed000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB109_LIMIT 0x070edfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB109_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB109_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB110_BASE 0x070ee000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB110_LIMIT 0x070eefff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB110_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB110_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB111_BASE 0x070ef000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB111_LIMIT 0x070effff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB111_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB111_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB112_BASE 0x070f0000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB112_LIMIT 0x070f0fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB112_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB112_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB113_BASE 0x070f1000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB113_LIMIT 0x070f1fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB113_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB113_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB114_BASE 0x070f2000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB114_LIMIT 0x070f2fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB114_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB114_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB115_BASE 0x070f3000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB115_LIMIT 0x070f3fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB115_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB115_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB116_BASE 0x070f4000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB116_LIMIT 0x070f4fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB116_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB116_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB117_BASE 0x070f5000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB117_LIMIT 0x070f5fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB117_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB117_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB118_BASE 0x070f6000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB118_LIMIT 0x070f6fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB118_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB118_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB119_BASE 0x070f7000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB119_LIMIT 0x070f7fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB119_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB119_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB120_BASE 0x070f8000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB120_LIMIT 0x070f8fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB120_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB120_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB121_BASE 0x070f9000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB121_LIMIT 0x070f9fff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB121_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB121_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB122_BASE 0x070fa000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB122_LIMIT 0x070fafff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB122_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB122_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB123_BASE 0x070fb000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB123_LIMIT 0x070fbfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB123_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB123_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB124_BASE 0x070fc000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB124_LIMIT 0x070fcfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB124_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB124_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB125_BASE 0x070fd000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB125_LIMIT 0x070fdfff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB125_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB125_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB126_BASE 0x070fe000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB126_LIMIT 0x070fefff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB126_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB126_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB127_BASE 0x070ff000
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB127_LIMIT 0x070fffff
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB127_ADDR_LOCALITY SYSTEM_CFG.SMMU3_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU3_4KB_PAGESIZE_CB127_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB0_BASE 0x07800000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB0_LIMIT 0x0780ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB0_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB0_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB1_BASE 0x07810000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB1_LIMIT 0x0781ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB1_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB1_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB2_BASE 0x07820000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB2_LIMIT 0x0782ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB2_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB2_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB3_BASE 0x07830000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB3_LIMIT 0x0783ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB3_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB3_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB4_BASE 0x07840000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB4_LIMIT 0x0784ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB4_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB4_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB5_BASE 0x07850000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB5_LIMIT 0x0785ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB5_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB5_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB6_BASE 0x07860000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB6_LIMIT 0x0786ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB6_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB6_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB7_BASE 0x07870000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB7_LIMIT 0x0787ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB7_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB7_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB8_BASE 0x07880000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB8_LIMIT 0x0788ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB8_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB8_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB9_BASE 0x07890000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB9_LIMIT 0x0789ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB9_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB9_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB10_BASE 0x078a0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB10_LIMIT 0x078affff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB10_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB10_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB11_BASE 0x078b0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB11_LIMIT 0x078bffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB11_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB11_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB12_BASE 0x078c0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB12_LIMIT 0x078cffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB12_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB12_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB13_BASE 0x078d0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB13_LIMIT 0x078dffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB13_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB13_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB14_BASE 0x078e0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB14_LIMIT 0x078effff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB14_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB14_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB15_BASE 0x078f0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB15_LIMIT 0x078fffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB15_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB15_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB16_BASE 0x07900000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB16_LIMIT 0x0790ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB16_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB16_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB17_BASE 0x07910000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB17_LIMIT 0x0791ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB17_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB17_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB18_BASE 0x07920000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB18_LIMIT 0x0792ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB18_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB18_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB19_BASE 0x07930000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB19_LIMIT 0x0793ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB19_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB19_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB20_BASE 0x07940000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB20_LIMIT 0x0794ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB20_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB20_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB21_BASE 0x07950000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB21_LIMIT 0x0795ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB21_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB21_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB22_BASE 0x07960000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB22_LIMIT 0x0796ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB22_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB22_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB23_BASE 0x07970000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB23_LIMIT 0x0797ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB23_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB23_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB24_BASE 0x07980000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB24_LIMIT 0x0798ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB24_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB24_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB25_BASE 0x07990000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB25_LIMIT 0x0799ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB25_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB25_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB26_BASE 0x079a0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB26_LIMIT 0x079affff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB26_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB26_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB27_BASE 0x079b0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB27_LIMIT 0x079bffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB27_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB27_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB28_BASE 0x079c0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB28_LIMIT 0x079cffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB28_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB28_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB29_BASE 0x079d0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB29_LIMIT 0x079dffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB29_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB29_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB30_BASE 0x079e0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB30_LIMIT 0x079effff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB30_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB30_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB31_BASE 0x079f0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB31_LIMIT 0x079fffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB31_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB31_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB32_BASE 0x07a00000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB32_LIMIT 0x07a0ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB32_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB32_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB33_BASE 0x07a10000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB33_LIMIT 0x07a1ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB33_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB33_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB34_BASE 0x07a20000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB34_LIMIT 0x07a2ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB34_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB34_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB35_BASE 0x07a30000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB35_LIMIT 0x07a3ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB35_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB35_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB36_BASE 0x07a40000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB36_LIMIT 0x07a4ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB36_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB36_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB37_BASE 0x07a50000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB37_LIMIT 0x07a5ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB37_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB37_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB38_BASE 0x07a60000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB38_LIMIT 0x07a6ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB38_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB38_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB39_BASE 0x07a70000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB39_LIMIT 0x07a7ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB39_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB39_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB40_BASE 0x07a80000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB40_LIMIT 0x07a8ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB40_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB40_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB41_BASE 0x07a90000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB41_LIMIT 0x07a9ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB41_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB41_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB42_BASE 0x07aa0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB42_LIMIT 0x07aaffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB42_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB42_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB43_BASE 0x07ab0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB43_LIMIT 0x07abffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB43_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB43_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB44_BASE 0x07ac0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB44_LIMIT 0x07acffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB44_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB44_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB45_BASE 0x07ad0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB45_LIMIT 0x07adffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB45_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB45_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB46_BASE 0x07ae0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB46_LIMIT 0x07aeffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB46_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB46_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB47_BASE 0x07af0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB47_LIMIT 0x07afffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB47_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB47_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB48_BASE 0x07b00000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB48_LIMIT 0x07b0ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB48_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB48_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB49_BASE 0x07b10000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB49_LIMIT 0x07b1ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB49_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB49_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB50_BASE 0x07b20000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB50_LIMIT 0x07b2ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB50_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB50_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB51_BASE 0x07b30000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB51_LIMIT 0x07b3ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB51_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB51_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB52_BASE 0x07b40000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB52_LIMIT 0x07b4ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB52_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB52_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB53_BASE 0x07b50000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB53_LIMIT 0x07b5ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB53_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB53_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB54_BASE 0x07b60000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB54_LIMIT 0x07b6ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB54_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB54_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB55_BASE 0x07b70000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB55_LIMIT 0x07b7ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB55_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB55_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB56_BASE 0x07b80000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB56_LIMIT 0x07b8ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB56_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB56_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB57_BASE 0x07b90000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB57_LIMIT 0x07b9ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB57_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB57_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB58_BASE 0x07ba0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB58_LIMIT 0x07baffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB58_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB58_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB59_BASE 0x07bb0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB59_LIMIT 0x07bbffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB59_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB59_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB60_BASE 0x07bc0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB60_LIMIT 0x07bcffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB60_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB60_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB61_BASE 0x07bd0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB61_LIMIT 0x07bdffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB61_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB61_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB62_BASE 0x07be0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB62_LIMIT 0x07beffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB62_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB62_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB63_BASE 0x07bf0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB63_LIMIT 0x07bfffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB63_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB63_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB64_BASE 0x07c00000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB64_LIMIT 0x07c0ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB64_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB64_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB65_BASE 0x07c10000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB65_LIMIT 0x07c1ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB65_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB65_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB66_BASE 0x07c20000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB66_LIMIT 0x07c2ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB66_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB66_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB67_BASE 0x07c30000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB67_LIMIT 0x07c3ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB67_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB67_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB68_BASE 0x07c40000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB68_LIMIT 0x07c4ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB68_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB68_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB69_BASE 0x07c50000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB69_LIMIT 0x07c5ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB69_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB69_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB70_BASE 0x07c60000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB70_LIMIT 0x07c6ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB70_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB70_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB71_BASE 0x07c70000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB71_LIMIT 0x07c7ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB71_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB71_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB72_BASE 0x07c80000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB72_LIMIT 0x07c8ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB72_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB72_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB73_BASE 0x07c90000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB73_LIMIT 0x07c9ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB73_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB73_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB74_BASE 0x07ca0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB74_LIMIT 0x07caffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB74_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB74_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB75_BASE 0x07cb0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB75_LIMIT 0x07cbffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB75_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB75_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB76_BASE 0x07cc0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB76_LIMIT 0x07ccffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB76_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB76_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB77_BASE 0x07cd0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB77_LIMIT 0x07cdffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB77_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB77_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB78_BASE 0x07ce0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB78_LIMIT 0x07ceffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB78_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB78_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB79_BASE 0x07cf0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB79_LIMIT 0x07cfffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB79_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB79_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB80_BASE 0x07d00000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB80_LIMIT 0x07d0ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB80_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB80_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB81_BASE 0x07d10000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB81_LIMIT 0x07d1ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB81_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB81_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB82_BASE 0x07d20000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB82_LIMIT 0x07d2ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB82_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB82_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB83_BASE 0x07d30000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB83_LIMIT 0x07d3ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB83_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB83_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB84_BASE 0x07d40000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB84_LIMIT 0x07d4ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB84_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB84_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB85_BASE 0x07d50000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB85_LIMIT 0x07d5ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB85_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB85_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB86_BASE 0x07d60000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB86_LIMIT 0x07d6ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB86_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB86_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB87_BASE 0x07d70000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB87_LIMIT 0x07d7ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB87_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB87_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB88_BASE 0x07d80000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB88_LIMIT 0x07d8ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB88_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB88_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB89_BASE 0x07d90000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB89_LIMIT 0x07d9ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB89_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB89_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB90_BASE 0x07da0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB90_LIMIT 0x07daffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB90_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB90_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB91_BASE 0x07db0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB91_LIMIT 0x07dbffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB91_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB91_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB92_BASE 0x07dc0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB92_LIMIT 0x07dcffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB92_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB92_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB93_BASE 0x07dd0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB93_LIMIT 0x07ddffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB93_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB93_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB94_BASE 0x07de0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB94_LIMIT 0x07deffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB94_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB94_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB95_BASE 0x07df0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB95_LIMIT 0x07dfffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB95_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB95_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB96_BASE 0x07e00000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB96_LIMIT 0x07e0ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB96_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB96_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB97_BASE 0x07e10000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB97_LIMIT 0x07e1ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB97_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB97_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB98_BASE 0x07e20000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB98_LIMIT 0x07e2ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB98_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB98_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB99_BASE 0x07e30000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB99_LIMIT 0x07e3ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB99_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB99_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB100_BASE 0x07e40000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB100_LIMIT 0x07e4ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB100_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB100_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB101_BASE 0x07e50000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB101_LIMIT 0x07e5ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB101_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB101_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB102_BASE 0x07e60000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB102_LIMIT 0x07e6ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB102_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB102_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB103_BASE 0x07e70000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB103_LIMIT 0x07e7ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB103_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB103_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB104_BASE 0x07e80000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB104_LIMIT 0x07e8ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB104_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB104_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB105_BASE 0x07e90000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB105_LIMIT 0x07e9ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB105_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB105_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB106_BASE 0x07ea0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB106_LIMIT 0x07eaffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB106_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB106_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB107_BASE 0x07eb0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB107_LIMIT 0x07ebffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB107_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB107_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB108_BASE 0x07ec0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB108_LIMIT 0x07ecffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB108_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB108_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB109_BASE 0x07ed0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB109_LIMIT 0x07edffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB109_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB109_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB110_BASE 0x07ee0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB110_LIMIT 0x07eeffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB110_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB110_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB111_BASE 0x07ef0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB111_LIMIT 0x07efffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB111_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB111_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB112_BASE 0x07f00000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB112_LIMIT 0x07f0ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB112_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB112_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB113_BASE 0x07f10000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB113_LIMIT 0x07f1ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB113_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB113_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB114_BASE 0x07f20000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB114_LIMIT 0x07f2ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB114_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB114_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB115_BASE 0x07f30000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB115_LIMIT 0x07f3ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB115_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB115_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB116_BASE 0x07f40000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB116_LIMIT 0x07f4ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB116_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB116_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB117_BASE 0x07f50000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB117_LIMIT 0x07f5ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB117_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB117_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB118_BASE 0x07f60000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB118_LIMIT 0x07f6ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB118_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB118_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB119_BASE 0x07f70000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB119_LIMIT 0x07f7ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB119_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB119_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB120_BASE 0x07f80000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB120_LIMIT 0x07f8ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB120_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB120_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB121_BASE 0x07f90000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB121_LIMIT 0x07f9ffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB121_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB121_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB122_BASE 0x07fa0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB122_LIMIT 0x07faffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB122_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB122_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB123_BASE 0x07fb0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB123_LIMIT 0x07fbffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB123_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB123_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB124_BASE 0x07fc0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB124_LIMIT 0x07fcffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB124_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB124_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB125_BASE 0x07fd0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB125_LIMIT 0x07fdffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB125_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB125_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB126_BASE 0x07fe0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB126_LIMIT 0x07feffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB126_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB126_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB127_BASE 0x07ff0000
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB127_LIMIT 0x07ffffff
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB127_ADDR_LOCALITY SYSTEM_CFG.SMMU3_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU3_64KB_PAGESIZE_CB127_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_GR0_BASE 0x08000000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_GR0_LIMIT 0x0800ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_GR0_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_GR0_HEADER arm_smmu_500_global.h;arm_smmu_500_global_sec.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_GR0_BASE 0x08000000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_GR0_LIMIT 0x08000fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_GR0_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_GR0_HEADER arm_smmu_500_global.h;arm_smmu_500_global_sec.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_GR1_BASE 0x08001000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_GR1_LIMIT 0x08001fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_GR1_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_GR1_HEADER arm_smmu_500_global_1.h;arm_smmu_500_global_sec_1.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_GID_BASE 0x08002000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_GID_LIMIT 0x08002fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_GID_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_GID_HEADER arm_smmu_500_integ_sec.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_PM_BASE 0x08003000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_PM_LIMIT 0x08003fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_PM_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_PM_HEADER arm_smmu_500_perf_mon.h;arm_smmu_500_perf_mon_sec.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_GR1_BASE 0x08010000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_GR1_LIMIT 0x0801ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_GR1_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_GR1_HEADER arm_smmu_500_global_1.h;arm_smmu_500_global_sec_1.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_GID_BASE 0x08020000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_GID_LIMIT 0x0802ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_GID_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_GID_HEADER arm_smmu_500_integ_sec.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_PM_BASE 0x08030000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_PM_LIMIT 0x0803ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_PM_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_PM_HEADER arm_smmu_500_perf_mon.h;arm_smmu_500_perf_mon_sec.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB0_BASE 0x08080000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB0_LIMIT 0x08080fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB0_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB0_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB1_BASE 0x08081000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB1_LIMIT 0x08081fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB1_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB1_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB2_BASE 0x08082000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB2_LIMIT 0x08082fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB2_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB2_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB3_BASE 0x08083000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB3_LIMIT 0x08083fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB3_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB3_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB4_BASE 0x08084000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB4_LIMIT 0x08084fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB4_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB4_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB5_BASE 0x08085000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB5_LIMIT 0x08085fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB5_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB5_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB6_BASE 0x08086000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB6_LIMIT 0x08086fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB6_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB6_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB7_BASE 0x08087000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB7_LIMIT 0x08087fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB7_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB7_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB8_BASE 0x08088000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB8_LIMIT 0x08088fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB8_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB8_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB9_BASE 0x08089000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB9_LIMIT 0x08089fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB9_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB9_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB10_BASE 0x0808a000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB10_LIMIT 0x0808afff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB10_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB10_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB11_BASE 0x0808b000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB11_LIMIT 0x0808bfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB11_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB11_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB12_BASE 0x0808c000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB12_LIMIT 0x0808cfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB12_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB12_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB13_BASE 0x0808d000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB13_LIMIT 0x0808dfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB13_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB13_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB14_BASE 0x0808e000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB14_LIMIT 0x0808efff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB14_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB14_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB15_BASE 0x0808f000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB15_LIMIT 0x0808ffff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB15_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB15_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB16_BASE 0x08090000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB16_LIMIT 0x08090fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB16_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB16_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB17_BASE 0x08091000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB17_LIMIT 0x08091fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB17_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB17_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB18_BASE 0x08092000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB18_LIMIT 0x08092fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB18_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB18_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB19_BASE 0x08093000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB19_LIMIT 0x08093fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB19_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB19_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB20_BASE 0x08094000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB20_LIMIT 0x08094fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB20_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB20_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB21_BASE 0x08095000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB21_LIMIT 0x08095fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB21_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB21_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB22_BASE 0x08096000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB22_LIMIT 0x08096fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB22_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB22_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB23_BASE 0x08097000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB23_LIMIT 0x08097fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB23_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB23_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB24_BASE 0x08098000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB24_LIMIT 0x08098fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB24_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB24_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB25_BASE 0x08099000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB25_LIMIT 0x08099fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB25_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB25_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB26_BASE 0x0809a000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB26_LIMIT 0x0809afff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB26_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB26_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB27_BASE 0x0809b000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB27_LIMIT 0x0809bfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB27_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB27_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB28_BASE 0x0809c000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB28_LIMIT 0x0809cfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB28_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB28_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB29_BASE 0x0809d000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB29_LIMIT 0x0809dfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB29_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB29_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB30_BASE 0x0809e000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB30_LIMIT 0x0809efff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB30_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB30_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB31_BASE 0x0809f000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB31_LIMIT 0x0809ffff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB31_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB31_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB32_BASE 0x080a0000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB32_LIMIT 0x080a0fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB32_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB32_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB33_BASE 0x080a1000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB33_LIMIT 0x080a1fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB33_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB33_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB34_BASE 0x080a2000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB34_LIMIT 0x080a2fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB34_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB34_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB35_BASE 0x080a3000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB35_LIMIT 0x080a3fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB35_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB35_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB36_BASE 0x080a4000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB36_LIMIT 0x080a4fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB36_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB36_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB37_BASE 0x080a5000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB37_LIMIT 0x080a5fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB37_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB37_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB38_BASE 0x080a6000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB38_LIMIT 0x080a6fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB38_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB38_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB39_BASE 0x080a7000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB39_LIMIT 0x080a7fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB39_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB39_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB40_BASE 0x080a8000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB40_LIMIT 0x080a8fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB40_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB40_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB41_BASE 0x080a9000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB41_LIMIT 0x080a9fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB41_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB41_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB42_BASE 0x080aa000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB42_LIMIT 0x080aafff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB42_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB42_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB43_BASE 0x080ab000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB43_LIMIT 0x080abfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB43_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB43_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB44_BASE 0x080ac000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB44_LIMIT 0x080acfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB44_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB44_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB45_BASE 0x080ad000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB45_LIMIT 0x080adfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB45_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB45_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB46_BASE 0x080ae000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB46_LIMIT 0x080aefff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB46_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB46_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB47_BASE 0x080af000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB47_LIMIT 0x080affff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB47_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB47_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB48_BASE 0x080b0000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB48_LIMIT 0x080b0fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB48_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB48_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB49_BASE 0x080b1000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB49_LIMIT 0x080b1fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB49_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB49_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB50_BASE 0x080b2000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB50_LIMIT 0x080b2fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB50_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB50_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB51_BASE 0x080b3000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB51_LIMIT 0x080b3fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB51_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB51_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB52_BASE 0x080b4000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB52_LIMIT 0x080b4fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB52_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB52_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB53_BASE 0x080b5000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB53_LIMIT 0x080b5fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB53_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB53_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB54_BASE 0x080b6000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB54_LIMIT 0x080b6fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB54_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB54_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB55_BASE 0x080b7000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB55_LIMIT 0x080b7fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB55_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB55_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB56_BASE 0x080b8000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB56_LIMIT 0x080b8fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB56_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB56_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB57_BASE 0x080b9000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB57_LIMIT 0x080b9fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB57_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB57_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB58_BASE 0x080ba000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB58_LIMIT 0x080bafff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB58_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB58_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB59_BASE 0x080bb000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB59_LIMIT 0x080bbfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB59_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB59_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB60_BASE 0x080bc000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB60_LIMIT 0x080bcfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB60_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB60_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB61_BASE 0x080bd000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB61_LIMIT 0x080bdfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB61_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB61_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB62_BASE 0x080be000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB62_LIMIT 0x080befff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB62_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB62_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB63_BASE 0x080bf000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB63_LIMIT 0x080bffff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB63_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB63_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB64_BASE 0x080c0000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB64_LIMIT 0x080c0fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB64_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB64_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB65_BASE 0x080c1000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB65_LIMIT 0x080c1fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB65_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB65_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB66_BASE 0x080c2000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB66_LIMIT 0x080c2fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB66_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB66_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB67_BASE 0x080c3000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB67_LIMIT 0x080c3fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB67_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB67_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB68_BASE 0x080c4000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB68_LIMIT 0x080c4fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB68_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB68_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB69_BASE 0x080c5000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB69_LIMIT 0x080c5fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB69_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB69_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB70_BASE 0x080c6000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB70_LIMIT 0x080c6fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB70_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB70_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB71_BASE 0x080c7000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB71_LIMIT 0x080c7fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB71_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB71_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB72_BASE 0x080c8000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB72_LIMIT 0x080c8fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB72_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB72_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB73_BASE 0x080c9000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB73_LIMIT 0x080c9fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB73_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB73_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB74_BASE 0x080ca000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB74_LIMIT 0x080cafff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB74_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB74_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB75_BASE 0x080cb000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB75_LIMIT 0x080cbfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB75_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB75_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB76_BASE 0x080cc000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB76_LIMIT 0x080ccfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB76_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB76_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB77_BASE 0x080cd000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB77_LIMIT 0x080cdfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB77_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB77_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB78_BASE 0x080ce000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB78_LIMIT 0x080cefff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB78_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB78_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB79_BASE 0x080cf000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB79_LIMIT 0x080cffff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB79_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB79_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB80_BASE 0x080d0000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB80_LIMIT 0x080d0fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB80_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB80_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB81_BASE 0x080d1000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB81_LIMIT 0x080d1fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB81_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB81_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB82_BASE 0x080d2000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB82_LIMIT 0x080d2fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB82_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB82_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB83_BASE 0x080d3000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB83_LIMIT 0x080d3fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB83_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB83_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB84_BASE 0x080d4000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB84_LIMIT 0x080d4fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB84_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB84_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB85_BASE 0x080d5000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB85_LIMIT 0x080d5fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB85_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB85_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB86_BASE 0x080d6000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB86_LIMIT 0x080d6fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB86_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB86_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB87_BASE 0x080d7000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB87_LIMIT 0x080d7fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB87_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB87_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB88_BASE 0x080d8000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB88_LIMIT 0x080d8fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB88_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB88_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB89_BASE 0x080d9000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB89_LIMIT 0x080d9fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB89_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB89_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB90_BASE 0x080da000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB90_LIMIT 0x080dafff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB90_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB90_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB91_BASE 0x080db000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB91_LIMIT 0x080dbfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB91_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB91_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB92_BASE 0x080dc000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB92_LIMIT 0x080dcfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB92_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB92_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB93_BASE 0x080dd000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB93_LIMIT 0x080ddfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB93_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB93_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB94_BASE 0x080de000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB94_LIMIT 0x080defff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB94_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB94_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB95_BASE 0x080df000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB95_LIMIT 0x080dffff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB95_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB95_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB96_BASE 0x080e0000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB96_LIMIT 0x080e0fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB96_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB96_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB97_BASE 0x080e1000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB97_LIMIT 0x080e1fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB97_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB97_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB98_BASE 0x080e2000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB98_LIMIT 0x080e2fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB98_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB98_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB99_BASE 0x080e3000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB99_LIMIT 0x080e3fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB99_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB99_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB100_BASE 0x080e4000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB100_LIMIT 0x080e4fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB100_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB100_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB101_BASE 0x080e5000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB101_LIMIT 0x080e5fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB101_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB101_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB102_BASE 0x080e6000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB102_LIMIT 0x080e6fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB102_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB102_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB103_BASE 0x080e7000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB103_LIMIT 0x080e7fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB103_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB103_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB104_BASE 0x080e8000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB104_LIMIT 0x080e8fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB104_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB104_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB105_BASE 0x080e9000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB105_LIMIT 0x080e9fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB105_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB105_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB106_BASE 0x080ea000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB106_LIMIT 0x080eafff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB106_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB106_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB107_BASE 0x080eb000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB107_LIMIT 0x080ebfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB107_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB107_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB108_BASE 0x080ec000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB108_LIMIT 0x080ecfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB108_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB108_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB109_BASE 0x080ed000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB109_LIMIT 0x080edfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB109_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB109_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB110_BASE 0x080ee000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB110_LIMIT 0x080eefff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB110_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB110_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB111_BASE 0x080ef000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB111_LIMIT 0x080effff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB111_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB111_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB112_BASE 0x080f0000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB112_LIMIT 0x080f0fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB112_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB112_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB113_BASE 0x080f1000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB113_LIMIT 0x080f1fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB113_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB113_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB114_BASE 0x080f2000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB114_LIMIT 0x080f2fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB114_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB114_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB115_BASE 0x080f3000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB115_LIMIT 0x080f3fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB115_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB115_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB116_BASE 0x080f4000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB116_LIMIT 0x080f4fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB116_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB116_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB117_BASE 0x080f5000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB117_LIMIT 0x080f5fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB117_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB117_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB118_BASE 0x080f6000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB118_LIMIT 0x080f6fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB118_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB118_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB119_BASE 0x080f7000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB119_LIMIT 0x080f7fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB119_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB119_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB120_BASE 0x080f8000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB120_LIMIT 0x080f8fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB120_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB120_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB121_BASE 0x080f9000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB121_LIMIT 0x080f9fff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB121_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB121_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB122_BASE 0x080fa000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB122_LIMIT 0x080fafff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB122_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB122_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB123_BASE 0x080fb000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB123_LIMIT 0x080fbfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB123_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB123_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB124_BASE 0x080fc000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB124_LIMIT 0x080fcfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB124_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB124_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB125_BASE 0x080fd000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB125_LIMIT 0x080fdfff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB125_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB125_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB126_BASE 0x080fe000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB126_LIMIT 0x080fefff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB126_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB126_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB127_BASE 0x080ff000
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB127_LIMIT 0x080fffff
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB127_ADDR_LOCALITY SYSTEM_CFG.SMMU4_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU4_4KB_PAGESIZE_CB127_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB0_BASE 0x08800000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB0_LIMIT 0x0880ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB0_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB0_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB1_BASE 0x08810000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB1_LIMIT 0x0881ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB1_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB1_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB2_BASE 0x08820000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB2_LIMIT 0x0882ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB2_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB2_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB3_BASE 0x08830000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB3_LIMIT 0x0883ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB3_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB3_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB4_BASE 0x08840000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB4_LIMIT 0x0884ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB4_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB4_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB5_BASE 0x08850000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB5_LIMIT 0x0885ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB5_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB5_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB6_BASE 0x08860000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB6_LIMIT 0x0886ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB6_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB6_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB7_BASE 0x08870000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB7_LIMIT 0x0887ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB7_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB7_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB8_BASE 0x08880000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB8_LIMIT 0x0888ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB8_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB8_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB9_BASE 0x08890000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB9_LIMIT 0x0889ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB9_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB9_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB10_BASE 0x088a0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB10_LIMIT 0x088affff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB10_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB10_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB11_BASE 0x088b0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB11_LIMIT 0x088bffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB11_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB11_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB12_BASE 0x088c0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB12_LIMIT 0x088cffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB12_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB12_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB13_BASE 0x088d0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB13_LIMIT 0x088dffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB13_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB13_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB14_BASE 0x088e0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB14_LIMIT 0x088effff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB14_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB14_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB15_BASE 0x088f0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB15_LIMIT 0x088fffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB15_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB15_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB16_BASE 0x08900000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB16_LIMIT 0x0890ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB16_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB16_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB17_BASE 0x08910000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB17_LIMIT 0x0891ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB17_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB17_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB18_BASE 0x08920000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB18_LIMIT 0x0892ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB18_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB18_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB19_BASE 0x08930000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB19_LIMIT 0x0893ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB19_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB19_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB20_BASE 0x08940000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB20_LIMIT 0x0894ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB20_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB20_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB21_BASE 0x08950000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB21_LIMIT 0x0895ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB21_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB21_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB22_BASE 0x08960000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB22_LIMIT 0x0896ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB22_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB22_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB23_BASE 0x08970000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB23_LIMIT 0x0897ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB23_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB23_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB24_BASE 0x08980000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB24_LIMIT 0x0898ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB24_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB24_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB25_BASE 0x08990000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB25_LIMIT 0x0899ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB25_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB25_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB26_BASE 0x089a0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB26_LIMIT 0x089affff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB26_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB26_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB27_BASE 0x089b0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB27_LIMIT 0x089bffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB27_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB27_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB28_BASE 0x089c0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB28_LIMIT 0x089cffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB28_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB28_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB29_BASE 0x089d0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB29_LIMIT 0x089dffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB29_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB29_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB30_BASE 0x089e0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB30_LIMIT 0x089effff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB30_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB30_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB31_BASE 0x089f0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB31_LIMIT 0x089fffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB31_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB31_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB32_BASE 0x08a00000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB32_LIMIT 0x08a0ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB32_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB32_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB33_BASE 0x08a10000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB33_LIMIT 0x08a1ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB33_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB33_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB34_BASE 0x08a20000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB34_LIMIT 0x08a2ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB34_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB34_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB35_BASE 0x08a30000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB35_LIMIT 0x08a3ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB35_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB35_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB36_BASE 0x08a40000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB36_LIMIT 0x08a4ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB36_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB36_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB37_BASE 0x08a50000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB37_LIMIT 0x08a5ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB37_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB37_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB38_BASE 0x08a60000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB38_LIMIT 0x08a6ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB38_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB38_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB39_BASE 0x08a70000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB39_LIMIT 0x08a7ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB39_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB39_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB40_BASE 0x08a80000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB40_LIMIT 0x08a8ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB40_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB40_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB41_BASE 0x08a90000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB41_LIMIT 0x08a9ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB41_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB41_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB42_BASE 0x08aa0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB42_LIMIT 0x08aaffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB42_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB42_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB43_BASE 0x08ab0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB43_LIMIT 0x08abffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB43_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB43_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB44_BASE 0x08ac0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB44_LIMIT 0x08acffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB44_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB44_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB45_BASE 0x08ad0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB45_LIMIT 0x08adffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB45_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB45_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB46_BASE 0x08ae0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB46_LIMIT 0x08aeffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB46_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB46_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB47_BASE 0x08af0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB47_LIMIT 0x08afffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB47_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB47_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB48_BASE 0x08b00000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB48_LIMIT 0x08b0ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB48_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB48_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB49_BASE 0x08b10000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB49_LIMIT 0x08b1ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB49_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB49_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB50_BASE 0x08b20000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB50_LIMIT 0x08b2ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB50_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB50_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB51_BASE 0x08b30000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB51_LIMIT 0x08b3ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB51_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB51_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB52_BASE 0x08b40000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB52_LIMIT 0x08b4ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB52_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB52_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB53_BASE 0x08b50000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB53_LIMIT 0x08b5ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB53_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB53_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB54_BASE 0x08b60000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB54_LIMIT 0x08b6ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB54_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB54_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB55_BASE 0x08b70000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB55_LIMIT 0x08b7ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB55_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB55_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB56_BASE 0x08b80000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB56_LIMIT 0x08b8ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB56_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB56_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB57_BASE 0x08b90000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB57_LIMIT 0x08b9ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB57_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB57_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB58_BASE 0x08ba0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB58_LIMIT 0x08baffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB58_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB58_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB59_BASE 0x08bb0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB59_LIMIT 0x08bbffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB59_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB59_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB60_BASE 0x08bc0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB60_LIMIT 0x08bcffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB60_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB60_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB61_BASE 0x08bd0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB61_LIMIT 0x08bdffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB61_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB61_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB62_BASE 0x08be0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB62_LIMIT 0x08beffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB62_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB62_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB63_BASE 0x08bf0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB63_LIMIT 0x08bfffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB63_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB63_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB64_BASE 0x08c00000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB64_LIMIT 0x08c0ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB64_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB64_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB65_BASE 0x08c10000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB65_LIMIT 0x08c1ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB65_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB65_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB66_BASE 0x08c20000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB66_LIMIT 0x08c2ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB66_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB66_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB67_BASE 0x08c30000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB67_LIMIT 0x08c3ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB67_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB67_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB68_BASE 0x08c40000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB68_LIMIT 0x08c4ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB68_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB68_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB69_BASE 0x08c50000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB69_LIMIT 0x08c5ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB69_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB69_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB70_BASE 0x08c60000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB70_LIMIT 0x08c6ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB70_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB70_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB71_BASE 0x08c70000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB71_LIMIT 0x08c7ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB71_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB71_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB72_BASE 0x08c80000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB72_LIMIT 0x08c8ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB72_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB72_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB73_BASE 0x08c90000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB73_LIMIT 0x08c9ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB73_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB73_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB74_BASE 0x08ca0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB74_LIMIT 0x08caffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB74_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB74_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB75_BASE 0x08cb0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB75_LIMIT 0x08cbffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB75_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB75_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB76_BASE 0x08cc0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB76_LIMIT 0x08ccffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB76_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB76_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB77_BASE 0x08cd0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB77_LIMIT 0x08cdffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB77_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB77_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB78_BASE 0x08ce0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB78_LIMIT 0x08ceffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB78_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB78_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB79_BASE 0x08cf0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB79_LIMIT 0x08cfffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB79_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB79_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB80_BASE 0x08d00000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB80_LIMIT 0x08d0ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB80_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB80_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB81_BASE 0x08d10000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB81_LIMIT 0x08d1ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB81_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB81_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB82_BASE 0x08d20000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB82_LIMIT 0x08d2ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB82_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB82_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB83_BASE 0x08d30000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB83_LIMIT 0x08d3ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB83_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB83_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB84_BASE 0x08d40000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB84_LIMIT 0x08d4ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB84_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB84_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB85_BASE 0x08d50000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB85_LIMIT 0x08d5ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB85_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB85_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB86_BASE 0x08d60000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB86_LIMIT 0x08d6ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB86_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB86_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB87_BASE 0x08d70000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB87_LIMIT 0x08d7ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB87_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB87_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB88_BASE 0x08d80000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB88_LIMIT 0x08d8ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB88_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB88_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB89_BASE 0x08d90000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB89_LIMIT 0x08d9ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB89_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB89_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB90_BASE 0x08da0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB90_LIMIT 0x08daffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB90_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB90_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB91_BASE 0x08db0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB91_LIMIT 0x08dbffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB91_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB91_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB92_BASE 0x08dc0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB92_LIMIT 0x08dcffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB92_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB92_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB93_BASE 0x08dd0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB93_LIMIT 0x08ddffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB93_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB93_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB94_BASE 0x08de0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB94_LIMIT 0x08deffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB94_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB94_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB95_BASE 0x08df0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB95_LIMIT 0x08dfffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB95_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB95_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB96_BASE 0x08e00000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB96_LIMIT 0x08e0ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB96_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB96_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB97_BASE 0x08e10000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB97_LIMIT 0x08e1ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB97_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB97_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB98_BASE 0x08e20000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB98_LIMIT 0x08e2ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB98_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB98_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB99_BASE 0x08e30000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB99_LIMIT 0x08e3ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB99_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB99_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB100_BASE 0x08e40000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB100_LIMIT 0x08e4ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB100_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB100_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB101_BASE 0x08e50000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB101_LIMIT 0x08e5ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB101_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB101_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB102_BASE 0x08e60000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB102_LIMIT 0x08e6ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB102_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB102_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB103_BASE 0x08e70000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB103_LIMIT 0x08e7ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB103_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB103_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB104_BASE 0x08e80000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB104_LIMIT 0x08e8ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB104_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB104_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB105_BASE 0x08e90000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB105_LIMIT 0x08e9ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB105_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB105_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB106_BASE 0x08ea0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB106_LIMIT 0x08eaffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB106_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB106_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB107_BASE 0x08eb0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB107_LIMIT 0x08ebffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB107_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB107_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB108_BASE 0x08ec0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB108_LIMIT 0x08ecffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB108_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB108_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB109_BASE 0x08ed0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB109_LIMIT 0x08edffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB109_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB109_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB110_BASE 0x08ee0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB110_LIMIT 0x08eeffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB110_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB110_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB111_BASE 0x08ef0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB111_LIMIT 0x08efffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB111_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB111_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB112_BASE 0x08f00000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB112_LIMIT 0x08f0ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB112_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB112_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB113_BASE 0x08f10000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB113_LIMIT 0x08f1ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB113_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB113_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB114_BASE 0x08f20000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB114_LIMIT 0x08f2ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB114_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB114_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB115_BASE 0x08f30000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB115_LIMIT 0x08f3ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB115_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB115_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB116_BASE 0x08f40000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB116_LIMIT 0x08f4ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB116_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB116_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB117_BASE 0x08f50000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB117_LIMIT 0x08f5ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB117_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB117_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB118_BASE 0x08f60000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB118_LIMIT 0x08f6ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB118_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB118_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB119_BASE 0x08f70000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB119_LIMIT 0x08f7ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB119_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB119_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB120_BASE 0x08f80000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB120_LIMIT 0x08f8ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB120_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB120_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB121_BASE 0x08f90000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB121_LIMIT 0x08f9ffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB121_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB121_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB122_BASE 0x08fa0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB122_LIMIT 0x08faffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB122_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB122_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB123_BASE 0x08fb0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB123_LIMIT 0x08fbffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB123_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB123_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB124_BASE 0x08fc0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB124_LIMIT 0x08fcffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB124_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB124_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB125_BASE 0x08fd0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB125_LIMIT 0x08fdffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB125_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB125_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB126_BASE 0x08fe0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB126_LIMIT 0x08feffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB126_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB126_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB127_BASE 0x08ff0000
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB127_LIMIT 0x08ffffff
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB127_ADDR_LOCALITY SYSTEM_CFG.SMMU4_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU4_64KB_PAGESIZE_CB127_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SCE_ATCM_CFG_EVP_BASE 0x0b000000
+#define NV_ADDRESS_MAP_SCE_ATCM_CFG_EVP_LIMIT 0x0b00ffff
+#define NV_ADDRESS_MAP_SCE_ATCM_CFG_EVP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_ATCM_CFG_EVP_HEADER
+
+#define NV_ADDRESS_MAP_SCE_VIC_0_BASE 0x0b020000
+#define NV_ADDRESS_MAP_SCE_VIC_0_LIMIT 0x0b02ffff
+#define NV_ADDRESS_MAP_SCE_VIC_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_VIC_0_HEADER araps_vic.h
+
+#define NV_ADDRESS_MAP_SCE_VIC_1_BASE 0x0b030000
+#define NV_ADDRESS_MAP_SCE_VIC_1_LIMIT 0x0b03ffff
+#define NV_ADDRESS_MAP_SCE_VIC_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_VIC_1_HEADER araps_vic.h
+
+#define NV_ADDRESS_MAP_SCE_AST_0_BASE 0x0b040000
+#define NV_ADDRESS_MAP_SCE_AST_0_LIMIT 0x0b04ffff
+#define NV_ADDRESS_MAP_SCE_AST_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_AST_0_HEADER araps_ast.h;araps_ast_scr.h
+
+#define NV_ADDRESS_MAP_SCE_AST_1_BASE 0x0b050000
+#define NV_ADDRESS_MAP_SCE_AST_1_LIMIT 0x0b05ffff
+#define NV_ADDRESS_MAP_SCE_AST_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_AST_1_HEADER araps_ast.h;araps_ast_scr.h
+
+#define NV_ADDRESS_MAP_SCE_DMA_COMMON_BASE 0x0b060000
+#define NV_ADDRESS_MAP_SCE_DMA_COMMON_LIMIT 0x0b06ffff
+#define NV_ADDRESS_MAP_SCE_DMA_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_DMA_COMMON_HEADER
+
+#define NV_ADDRESS_MAP_SCE_DMA_CH_0_BASE 0x0b070000
+#define NV_ADDRESS_MAP_SCE_DMA_CH_0_LIMIT 0x0b07ffff
+#define NV_ADDRESS_MAP_SCE_DMA_CH_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_DMA_CH_0_HEADER
+
+#define NV_ADDRESS_MAP_SCE_DMA_CH_1_BASE 0x0b080000
+#define NV_ADDRESS_MAP_SCE_DMA_CH_1_LIMIT 0x0b08ffff
+#define NV_ADDRESS_MAP_SCE_DMA_CH_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_DMA_CH_1_HEADER
+
+#define NV_ADDRESS_MAP_SCE_DMA_CH_2_BASE 0x0b090000
+#define NV_ADDRESS_MAP_SCE_DMA_CH_2_LIMIT 0x0b09ffff
+#define NV_ADDRESS_MAP_SCE_DMA_CH_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_DMA_CH_2_HEADER
+
+#define NV_ADDRESS_MAP_SCE_DMA_CH_3_BASE 0x0b0a0000
+#define NV_ADDRESS_MAP_SCE_DMA_CH_3_LIMIT 0x0b0affff
+#define NV_ADDRESS_MAP_SCE_DMA_CH_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_DMA_CH_3_HEADER
+
+#define NV_ADDRESS_MAP_SCE_DMA_CH_4_BASE 0x0b0b0000
+#define NV_ADDRESS_MAP_SCE_DMA_CH_4_LIMIT 0x0b0bffff
+#define NV_ADDRESS_MAP_SCE_DMA_CH_4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_DMA_CH_4_HEADER
+
+#define NV_ADDRESS_MAP_SCE_DMA_CH_5_BASE 0x0b0c0000
+#define NV_ADDRESS_MAP_SCE_DMA_CH_5_LIMIT 0x0b0cffff
+#define NV_ADDRESS_MAP_SCE_DMA_CH_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_DMA_CH_5_HEADER
+
+#define NV_ADDRESS_MAP_SCE_DMA_CH_6_BASE 0x0b0d0000
+#define NV_ADDRESS_MAP_SCE_DMA_CH_6_LIMIT 0x0b0dffff
+#define NV_ADDRESS_MAP_SCE_DMA_CH_6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_DMA_CH_6_HEADER
+
+#define NV_ADDRESS_MAP_SCE_DMA_CH_7_BASE 0x0b0e0000
+#define NV_ADDRESS_MAP_SCE_DMA_CH_7_LIMIT 0x0b0effff
+#define NV_ADDRESS_MAP_SCE_DMA_CH_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_DMA_CH_7_HEADER
+
+#define NV_ADDRESS_MAP_SCE_TKE_SHARED_BASE 0x0b0f0000
+#define NV_ADDRESS_MAP_SCE_TKE_SHARED_LIMIT 0x0b0fffff
+#define NV_ADDRESS_MAP_SCE_TKE_SHARED_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_TKE_SHARED_HEADER
+
+#define NV_ADDRESS_MAP_SCE_TKE_TMR_0_BASE 0x0b100000
+#define NV_ADDRESS_MAP_SCE_TKE_TMR_0_LIMIT 0x0b10ffff
+#define NV_ADDRESS_MAP_SCE_TKE_TMR_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_TKE_TMR_0_HEADER
+
+#define NV_ADDRESS_MAP_SCE_TKE_TMR_1_BASE 0x0b110000
+#define NV_ADDRESS_MAP_SCE_TKE_TMR_1_LIMIT 0x0b11ffff
+#define NV_ADDRESS_MAP_SCE_TKE_TMR_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_TKE_TMR_1_HEADER
+
+#define NV_ADDRESS_MAP_SCE_TKE_TMR_2_BASE 0x0b120000
+#define NV_ADDRESS_MAP_SCE_TKE_TMR_2_LIMIT 0x0b12ffff
+#define NV_ADDRESS_MAP_SCE_TKE_TMR_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_TKE_TMR_2_HEADER
+
+#define NV_ADDRESS_MAP_SCE_TKE_TMR_3_BASE 0x0b130000
+#define NV_ADDRESS_MAP_SCE_TKE_TMR_3_LIMIT 0x0b13ffff
+#define NV_ADDRESS_MAP_SCE_TKE_TMR_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_TKE_TMR_3_HEADER
+
+#define NV_ADDRESS_MAP_SCE_TKE_WDT_0_BASE 0x0b140000
+#define NV_ADDRESS_MAP_SCE_TKE_WDT_0_LIMIT 0x0b14ffff
+#define NV_ADDRESS_MAP_SCE_TKE_WDT_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_TKE_WDT_0_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP_COMMON_BASE 0x0b150000
+#define NV_ADDRESS_MAP_SCE_HSP_COMMON_LIMIT 0x0b15ffff
+#define NV_ADDRESS_MAP_SCE_HSP_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP_COMMON_HEADER arhsp_int.h;arhsp_int_scr.h
+
+#define NV_ADDRESS_MAP_SCE_HSP_SM_0_1_BASE 0x0b160000
+#define NV_ADDRESS_MAP_SCE_HSP_SM_0_1_LIMIT 0x0b16ffff
+#define NV_ADDRESS_MAP_SCE_HSP_SM_0_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP_SM_0_1_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP_SM_2_3_BASE 0x0b170000
+#define NV_ADDRESS_MAP_SCE_HSP_SM_2_3_LIMIT 0x0b17ffff
+#define NV_ADDRESS_MAP_SCE_HSP_SM_2_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP_SM_2_3_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP_SM_4_5_BASE 0x0b180000
+#define NV_ADDRESS_MAP_SCE_HSP_SM_4_5_LIMIT 0x0b18ffff
+#define NV_ADDRESS_MAP_SCE_HSP_SM_4_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP_SM_4_5_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP_SM_6_7_BASE 0x0b190000
+#define NV_ADDRESS_MAP_SCE_HSP_SM_6_7_LIMIT 0x0b19ffff
+#define NV_ADDRESS_MAP_SCE_HSP_SM_6_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP_SM_6_7_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP_SS_0_BASE 0x0b1a0000
+#define NV_ADDRESS_MAP_SCE_HSP_SS_0_LIMIT 0x0b1affff
+#define NV_ADDRESS_MAP_SCE_HSP_SS_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP_SS_0_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP_SS_1_BASE 0x0b1b0000
+#define NV_ADDRESS_MAP_SCE_HSP_SS_1_LIMIT 0x0b1bffff
+#define NV_ADDRESS_MAP_SCE_HSP_SS_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP_SS_1_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP_SS_2_BASE 0x0b1c0000
+#define NV_ADDRESS_MAP_SCE_HSP_SS_2_LIMIT 0x0b1cffff
+#define NV_ADDRESS_MAP_SCE_HSP_SS_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP_SS_2_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP_SS_3_BASE 0x0b1d0000
+#define NV_ADDRESS_MAP_SCE_HSP_SS_3_LIMIT 0x0b1dffff
+#define NV_ADDRESS_MAP_SCE_HSP_SS_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP_SS_3_HEADER
+
+#define NV_ADDRESS_MAP_SCE_GTE_BASE 0x0b1e0000
+#define NV_ADDRESS_MAP_SCE_GTE_LIMIT 0x0b1effff
+#define NV_ADDRESS_MAP_SCE_GTE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_GTE_HEADER argte_aps.h;argte_aps_scr.h
+
+#define NV_ADDRESS_MAP_SCE_PM_IMPL_BASE 0x0b1f0000
+#define NV_ADDRESS_MAP_SCE_PM_IMPL_LIMIT 0x0b1fffff
+#define NV_ADDRESS_MAP_SCE_PM_IMPL_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_PM_IMPL_HEADER arscepm.h;arscepm_scr.h
+
+#define NV_ADDRESS_MAP_SCE_ACTMON_BASE 0x0b200000
+#define NV_ADDRESS_MAP_SCE_ACTMON_LIMIT 0x0b20ffff
+#define NV_ADDRESS_MAP_SCE_ACTMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_ACTMON_HEADER arunit_actmon.h
+
+#define NV_ADDRESS_MAP_SCE_CFG_BASE 0x0b230000
+#define NV_ADDRESS_MAP_SCE_CFG_LIMIT 0x0b23ffff
+#define NV_ADDRESS_MAP_SCE_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_CFG_HEADER araps_proc_cfg.h
+
+#define NV_ADDRESS_MAP_HSM_BASE 0x0b240000
+#define NV_ADDRESS_MAP_HSM_LIMIT 0x0b24ffff
+#define NV_ADDRESS_MAP_HSM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HSM_HEADER arsce_hsm.h
+
+#define NV_ADDRESS_MAP_SCE_ATCM_EVP_EXT_BASE 0x0b400000
+#define NV_ADDRESS_MAP_SCE_ATCM_EVP_EXT_LIMIT 0x0b40ffff
+#define NV_ADDRESS_MAP_SCE_ATCM_EVP_EXT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_ATCM_EVP_EXT_HEADER arsce_evp.h
+
+#define NV_ADDRESS_MAP_SCE_BTCM_BASE 0x0b480000
+#define NV_ADDRESS_MAP_SCE_BTCM_LIMIT 0x0b4dffff
+#define NV_ADDRESS_MAP_SCE_BTCM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_BTCM_HEADER no_headers
+
+#define NV_ADDRESS_MAP_SCE_ICACHE_ACCESS_PORT_BASE 0x0b500000
+#define NV_ADDRESS_MAP_SCE_ICACHE_ACCESS_PORT_LIMIT 0x0b57ffff
+#define NV_ADDRESS_MAP_SCE_ICACHE_ACCESS_PORT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_ICACHE_ACCESS_PORT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_SCE_DCACHE_ACCESS_PORT_BASE 0x0b580000
+#define NV_ADDRESS_MAP_SCE_DCACHE_ACCESS_PORT_LIMIT 0x0b5fffff
+#define NV_ADDRESS_MAP_SCE_DCACHE_ACCESS_PORT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_DCACHE_ACCESS_PORT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_SCE_SN_AXI2APB_1_BASE 0x0b600000
+#define NV_ADDRESS_MAP_SCE_SN_AXI2APB_1_LIMIT 0x0b600fff
+#define NV_ADDRESS_MAP_SCE_SN_AXI2APB_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_SN_AXI2APB_1_HEADER
+
+#define NV_ADDRESS_MAP_SCE_MN_CPU_M_I_BASE 0x0b610000
+#define NV_ADDRESS_MAP_SCE_MN_CPU_M_I_LIMIT 0x0b610fff
+#define NV_ADDRESS_MAP_SCE_MN_CPU_M_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_MN_CPU_M_I_HEADER
+
+#define NV_ADDRESS_MAP_SCE_MN_CBB_I_BASE 0x0b611000
+#define NV_ADDRESS_MAP_SCE_MN_CBB_I_LIMIT 0x0b611fff
+#define NV_ADDRESS_MAP_SCE_MN_CBB_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_MN_CBB_I_HEADER
+
+#define NV_ADDRESS_MAP_SCE_MN_CPU_P_I_BASE 0x0b612000
+#define NV_ADDRESS_MAP_SCE_MN_CPU_P_I_LIMIT 0x0b612fff
+#define NV_ADDRESS_MAP_SCE_MN_CPU_P_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_MN_CPU_P_I_HEADER
+
+#define NV_ADDRESS_MAP_SCE_MN_DMA_M_I_BASE 0x0b613000
+#define NV_ADDRESS_MAP_SCE_MN_DMA_M_I_LIMIT 0x0b613fff
+#define NV_ADDRESS_MAP_SCE_MN_DMA_M_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_MN_DMA_M_I_HEADER
+
+#define NV_ADDRESS_MAP_SCE_MN_DMA_P_I_BASE 0x0b614000
+#define NV_ADDRESS_MAP_SCE_MN_DMA_P_I_LIMIT 0x0b614fff
+#define NV_ADDRESS_MAP_SCE_MN_DMA_P_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_MN_DMA_P_I_HEADER
+
+#define NV_ADDRESS_MAP_SCE_SN_AST0_T_BASE 0x0b615000
+#define NV_ADDRESS_MAP_SCE_SN_AST0_T_LIMIT 0x0b615fff
+#define NV_ADDRESS_MAP_SCE_SN_AST0_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_SN_AST0_T_HEADER
+
+#define NV_ADDRESS_MAP_SCE_SN_AST1_T_BASE 0x0b616000
+#define NV_ADDRESS_MAP_SCE_SN_AST1_T_LIMIT 0x0b616fff
+#define NV_ADDRESS_MAP_SCE_SN_AST1_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_SN_AST1_T_HEADER
+
+#define NV_ADDRESS_MAP_SCE_SN_CBB_T_BASE 0x0b617000
+#define NV_ADDRESS_MAP_SCE_SN_CBB_T_LIMIT 0x0b617fff
+#define NV_ADDRESS_MAP_SCE_SN_CBB_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_SN_CBB_T_HEADER
+
+#define NV_ADDRESS_MAP_SCE_SN_CPU_T_BASE 0x0b618000
+#define NV_ADDRESS_MAP_SCE_SN_CPU_T_LIMIT 0x0b618fff
+#define NV_ADDRESS_MAP_SCE_SN_CPU_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_SN_CPU_T_HEADER
+
+#define NV_ADDRESS_MAP_SCE_EN_CFG_BASE 0x0b619000
+#define NV_ADDRESS_MAP_SCE_EN_CFG_LIMIT 0x0b619fff
+#define NV_ADDRESS_MAP_SCE_EN_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_EN_CFG_HEADER
+
+#define NV_ADDRESS_MAP_SCE_FABRIC_ERR_COLLATOR_BASE 0x0b620000
+#define NV_ADDRESS_MAP_SCE_FABRIC_ERR_COLLATOR_LIMIT 0x0b620fff
+#define NV_ADDRESS_MAP_SCE_FABRIC_ERR_COLLATOR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_FABRIC_ERR_COLLATOR_HEADER
+
+#define NV_ADDRESS_MAP_SCE_ERR_COLLATOR_BASE 0x0b650000
+#define NV_ADDRESS_MAP_SCE_ERR_COLLATOR_LIMIT 0x0b65ffff
+#define NV_ADDRESS_MAP_SCE_ERR_COLLATOR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_ERR_COLLATOR_HEADER arsce_ec.h;arsce_ec_scr.h
+
+#define NV_ADDRESS_MAP_SCE_MISC_BASE 0x0b660000
+#define NV_ADDRESS_MAP_SCE_MISC_LIMIT 0x0b66ffff
+#define NV_ADDRESS_MAP_SCE_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_MISC_HEADER arsce_misc.h;arsce_misc_scr.h
+
+#define NV_ADDRESS_MAP_SCE_HSP1_COMMON_BASE 0x0b670000
+#define NV_ADDRESS_MAP_SCE_HSP1_COMMON_LIMIT 0x0b67ffff
+#define NV_ADDRESS_MAP_SCE_HSP1_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP1_COMMON_HEADER arhsp_int.h;arhsp_int_scr.h
+
+#define NV_ADDRESS_MAP_SCE_HSP1_SM_0_1_BASE 0x0b680000
+#define NV_ADDRESS_MAP_SCE_HSP1_SM_0_1_LIMIT 0x0b68ffff
+#define NV_ADDRESS_MAP_SCE_HSP1_SM_0_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP1_SM_0_1_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP1_SM_2_3_BASE 0x0b690000
+#define NV_ADDRESS_MAP_SCE_HSP1_SM_2_3_LIMIT 0x0b69ffff
+#define NV_ADDRESS_MAP_SCE_HSP1_SM_2_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP1_SM_2_3_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP1_SM_4_5_BASE 0x0b6a0000
+#define NV_ADDRESS_MAP_SCE_HSP1_SM_4_5_LIMIT 0x0b6affff
+#define NV_ADDRESS_MAP_SCE_HSP1_SM_4_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP1_SM_4_5_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP1_SM_6_7_BASE 0x0b6b0000
+#define NV_ADDRESS_MAP_SCE_HSP1_SM_6_7_LIMIT 0x0b6bffff
+#define NV_ADDRESS_MAP_SCE_HSP1_SM_6_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP1_SM_6_7_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP1_SS_0_BASE 0x0b6c0000
+#define NV_ADDRESS_MAP_SCE_HSP1_SS_0_LIMIT 0x0b6cffff
+#define NV_ADDRESS_MAP_SCE_HSP1_SS_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP1_SS_0_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP1_SS_1_BASE 0x0b6d0000
+#define NV_ADDRESS_MAP_SCE_HSP1_SS_1_LIMIT 0x0b6dffff
+#define NV_ADDRESS_MAP_SCE_HSP1_SS_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP1_SS_1_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP1_SS_2_BASE 0x0b6e0000
+#define NV_ADDRESS_MAP_SCE_HSP1_SS_2_LIMIT 0x0b6effff
+#define NV_ADDRESS_MAP_SCE_HSP1_SS_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP1_SS_2_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP1_SS_3_BASE 0x0b6f0000
+#define NV_ADDRESS_MAP_SCE_HSP1_SS_3_LIMIT 0x0b6fffff
+#define NV_ADDRESS_MAP_SCE_HSP1_SS_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP1_SS_3_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP2_COMMON_BASE 0x0b700000
+#define NV_ADDRESS_MAP_SCE_HSP2_COMMON_LIMIT 0x0b70ffff
+#define NV_ADDRESS_MAP_SCE_HSP2_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP2_COMMON_HEADER arhsp_int.h;arhsp_int_scr.h
+
+#define NV_ADDRESS_MAP_SCE_HSP2_SM_0_1_BASE 0x0b710000
+#define NV_ADDRESS_MAP_SCE_HSP2_SM_0_1_LIMIT 0x0b71ffff
+#define NV_ADDRESS_MAP_SCE_HSP2_SM_0_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP2_SM_0_1_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP2_SM_2_3_BASE 0x0b720000
+#define NV_ADDRESS_MAP_SCE_HSP2_SM_2_3_LIMIT 0x0b72ffff
+#define NV_ADDRESS_MAP_SCE_HSP2_SM_2_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP2_SM_2_3_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP2_SM_4_5_BASE 0x0b730000
+#define NV_ADDRESS_MAP_SCE_HSP2_SM_4_5_LIMIT 0x0b73ffff
+#define NV_ADDRESS_MAP_SCE_HSP2_SM_4_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP2_SM_4_5_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP2_SM_6_7_BASE 0x0b740000
+#define NV_ADDRESS_MAP_SCE_HSP2_SM_6_7_LIMIT 0x0b74ffff
+#define NV_ADDRESS_MAP_SCE_HSP2_SM_6_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP2_SM_6_7_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP2_SS_0_BASE 0x0b750000
+#define NV_ADDRESS_MAP_SCE_HSP2_SS_0_LIMIT 0x0b75ffff
+#define NV_ADDRESS_MAP_SCE_HSP2_SS_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP2_SS_0_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP2_SS_1_BASE 0x0b760000
+#define NV_ADDRESS_MAP_SCE_HSP2_SS_1_LIMIT 0x0b76ffff
+#define NV_ADDRESS_MAP_SCE_HSP2_SS_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP2_SS_1_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP2_SS_2_BASE 0x0b770000
+#define NV_ADDRESS_MAP_SCE_HSP2_SS_2_LIMIT 0x0b77ffff
+#define NV_ADDRESS_MAP_SCE_HSP2_SS_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP2_SS_2_HEADER
+
+#define NV_ADDRESS_MAP_SCE_HSP2_SS_3_BASE 0x0b780000
+#define NV_ADDRESS_MAP_SCE_HSP2_SS_3_LIMIT 0x0b78ffff
+#define NV_ADDRESS_MAP_SCE_HSP2_SS_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCE_HSP2_SS_3_HEADER
+
+#define NV_ADDRESS_MAP_RCE_ATCM_CFG_EVP_BASE 0x0b800000
+#define NV_ADDRESS_MAP_RCE_ATCM_CFG_EVP_LIMIT 0x0b80ffff
+#define NV_ADDRESS_MAP_RCE_ATCM_CFG_EVP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_ATCM_CFG_EVP_HEADER
+
+#define NV_ADDRESS_MAP_RCE_VIC_0_BASE 0x0b820000
+#define NV_ADDRESS_MAP_RCE_VIC_0_LIMIT 0x0b82ffff
+#define NV_ADDRESS_MAP_RCE_VIC_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_VIC_0_HEADER araps_vic.h
+
+#define NV_ADDRESS_MAP_RCE_VIC_1_BASE 0x0b830000
+#define NV_ADDRESS_MAP_RCE_VIC_1_LIMIT 0x0b83ffff
+#define NV_ADDRESS_MAP_RCE_VIC_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_VIC_1_HEADER araps_vic.h
+
+#define NV_ADDRESS_MAP_RCE_AST_0_BASE 0x0b840000
+#define NV_ADDRESS_MAP_RCE_AST_0_LIMIT 0x0b84ffff
+#define NV_ADDRESS_MAP_RCE_AST_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_AST_0_HEADER araps_ast.h;araps_ast_scr.h
+
+#define NV_ADDRESS_MAP_RCE_AST_1_BASE 0x0b850000
+#define NV_ADDRESS_MAP_RCE_AST_1_LIMIT 0x0b85ffff
+#define NV_ADDRESS_MAP_RCE_AST_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_AST_1_HEADER araps_ast.h;araps_ast_scr.h
+
+#define NV_ADDRESS_MAP_RCE_DMA_COMMON_BASE 0x0b860000
+#define NV_ADDRESS_MAP_RCE_DMA_COMMON_LIMIT 0x0b86ffff
+#define NV_ADDRESS_MAP_RCE_DMA_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_DMA_COMMON_HEADER
+
+#define NV_ADDRESS_MAP_RCE_DMA_CH_0_BASE 0x0b870000
+#define NV_ADDRESS_MAP_RCE_DMA_CH_0_LIMIT 0x0b87ffff
+#define NV_ADDRESS_MAP_RCE_DMA_CH_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_DMA_CH_0_HEADER
+
+#define NV_ADDRESS_MAP_RCE_DMA_CH_1_BASE 0x0b880000
+#define NV_ADDRESS_MAP_RCE_DMA_CH_1_LIMIT 0x0b88ffff
+#define NV_ADDRESS_MAP_RCE_DMA_CH_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_DMA_CH_1_HEADER
+
+#define NV_ADDRESS_MAP_RCE_DMA_CH_2_BASE 0x0b890000
+#define NV_ADDRESS_MAP_RCE_DMA_CH_2_LIMIT 0x0b89ffff
+#define NV_ADDRESS_MAP_RCE_DMA_CH_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_DMA_CH_2_HEADER
+
+#define NV_ADDRESS_MAP_RCE_DMA_CH_3_BASE 0x0b8a0000
+#define NV_ADDRESS_MAP_RCE_DMA_CH_3_LIMIT 0x0b8affff
+#define NV_ADDRESS_MAP_RCE_DMA_CH_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_DMA_CH_3_HEADER
+
+#define NV_ADDRESS_MAP_RCE_DMA_CH_4_BASE 0x0b8b0000
+#define NV_ADDRESS_MAP_RCE_DMA_CH_4_LIMIT 0x0b8bffff
+#define NV_ADDRESS_MAP_RCE_DMA_CH_4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_DMA_CH_4_HEADER
+
+#define NV_ADDRESS_MAP_RCE_DMA_CH_5_BASE 0x0b8c0000
+#define NV_ADDRESS_MAP_RCE_DMA_CH_5_LIMIT 0x0b8cffff
+#define NV_ADDRESS_MAP_RCE_DMA_CH_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_DMA_CH_5_HEADER
+
+#define NV_ADDRESS_MAP_RCE_DMA_CH_6_BASE 0x0b8d0000
+#define NV_ADDRESS_MAP_RCE_DMA_CH_6_LIMIT 0x0b8dffff
+#define NV_ADDRESS_MAP_RCE_DMA_CH_6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_DMA_CH_6_HEADER
+
+#define NV_ADDRESS_MAP_RCE_DMA_CH_7_BASE 0x0b8e0000
+#define NV_ADDRESS_MAP_RCE_DMA_CH_7_LIMIT 0x0b8effff
+#define NV_ADDRESS_MAP_RCE_DMA_CH_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_DMA_CH_7_HEADER
+
+#define NV_ADDRESS_MAP_RCE_TKE_SHARED_BASE 0x0b8f0000
+#define NV_ADDRESS_MAP_RCE_TKE_SHARED_LIMIT 0x0b8fffff
+#define NV_ADDRESS_MAP_RCE_TKE_SHARED_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_TKE_SHARED_HEADER
+
+#define NV_ADDRESS_MAP_RCE_TKE_TMR_0_BASE 0x0b900000
+#define NV_ADDRESS_MAP_RCE_TKE_TMR_0_LIMIT 0x0b90ffff
+#define NV_ADDRESS_MAP_RCE_TKE_TMR_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_TKE_TMR_0_HEADER
+
+#define NV_ADDRESS_MAP_RCE_TKE_TMR_1_BASE 0x0b910000
+#define NV_ADDRESS_MAP_RCE_TKE_TMR_1_LIMIT 0x0b91ffff
+#define NV_ADDRESS_MAP_RCE_TKE_TMR_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_TKE_TMR_1_HEADER
+
+#define NV_ADDRESS_MAP_RCE_TKE_TMR_2_BASE 0x0b920000
+#define NV_ADDRESS_MAP_RCE_TKE_TMR_2_LIMIT 0x0b92ffff
+#define NV_ADDRESS_MAP_RCE_TKE_TMR_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_TKE_TMR_2_HEADER
+
+#define NV_ADDRESS_MAP_RCE_TKE_TMR_3_BASE 0x0b930000
+#define NV_ADDRESS_MAP_RCE_TKE_TMR_3_LIMIT 0x0b93ffff
+#define NV_ADDRESS_MAP_RCE_TKE_TMR_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_TKE_TMR_3_HEADER
+
+#define NV_ADDRESS_MAP_RCE_TKE_WDT_0_BASE 0x0b940000
+#define NV_ADDRESS_MAP_RCE_TKE_WDT_0_LIMIT 0x0b94ffff
+#define NV_ADDRESS_MAP_RCE_TKE_WDT_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_TKE_WDT_0_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP_COMMON_BASE 0x0b950000
+#define NV_ADDRESS_MAP_RCE_HSP_COMMON_LIMIT 0x0b95ffff
+#define NV_ADDRESS_MAP_RCE_HSP_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP_COMMON_HEADER arhsp_int.h;arhsp_int_scr.h
+
+#define NV_ADDRESS_MAP_RCE_HSP_SM_0_1_BASE 0x0b960000
+#define NV_ADDRESS_MAP_RCE_HSP_SM_0_1_LIMIT 0x0b96ffff
+#define NV_ADDRESS_MAP_RCE_HSP_SM_0_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP_SM_0_1_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP_SM_2_3_BASE 0x0b970000
+#define NV_ADDRESS_MAP_RCE_HSP_SM_2_3_LIMIT 0x0b97ffff
+#define NV_ADDRESS_MAP_RCE_HSP_SM_2_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP_SM_2_3_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP_SM_4_5_BASE 0x0b980000
+#define NV_ADDRESS_MAP_RCE_HSP_SM_4_5_LIMIT 0x0b98ffff
+#define NV_ADDRESS_MAP_RCE_HSP_SM_4_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP_SM_4_5_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP_SM_6_7_BASE 0x0b990000
+#define NV_ADDRESS_MAP_RCE_HSP_SM_6_7_LIMIT 0x0b99ffff
+#define NV_ADDRESS_MAP_RCE_HSP_SM_6_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP_SM_6_7_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP_SS_0_BASE 0x0b9a0000
+#define NV_ADDRESS_MAP_RCE_HSP_SS_0_LIMIT 0x0b9affff
+#define NV_ADDRESS_MAP_RCE_HSP_SS_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP_SS_0_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP_SS_1_BASE 0x0b9b0000
+#define NV_ADDRESS_MAP_RCE_HSP_SS_1_LIMIT 0x0b9bffff
+#define NV_ADDRESS_MAP_RCE_HSP_SS_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP_SS_1_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP_SS_2_BASE 0x0b9c0000
+#define NV_ADDRESS_MAP_RCE_HSP_SS_2_LIMIT 0x0b9cffff
+#define NV_ADDRESS_MAP_RCE_HSP_SS_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP_SS_2_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP_SS_3_BASE 0x0b9d0000
+#define NV_ADDRESS_MAP_RCE_HSP_SS_3_LIMIT 0x0b9dffff
+#define NV_ADDRESS_MAP_RCE_HSP_SS_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP_SS_3_HEADER
+
+#define NV_ADDRESS_MAP_RCE_GTE_BASE 0x0b9e0000
+#define NV_ADDRESS_MAP_RCE_GTE_LIMIT 0x0b9effff
+#define NV_ADDRESS_MAP_RCE_GTE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_GTE_HEADER argte_aps.h;argte_aps_scr.h
+
+#define NV_ADDRESS_MAP_RCE_PM_IMPL_BASE 0x0b9f0000
+#define NV_ADDRESS_MAP_RCE_PM_IMPL_LIMIT 0x0b9fffff
+#define NV_ADDRESS_MAP_RCE_PM_IMPL_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_PM_IMPL_HEADER arscepm.h;arscepm_scr.h
+
+#define NV_ADDRESS_MAP_RCE_ACTMON_BASE 0x0ba00000
+#define NV_ADDRESS_MAP_RCE_ACTMON_LIMIT 0x0ba0ffff
+#define NV_ADDRESS_MAP_RCE_ACTMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_ACTMON_HEADER arunit_actmon.h
+
+#define NV_ADDRESS_MAP_RCE_CFG_BASE 0x0ba30000
+#define NV_ADDRESS_MAP_RCE_CFG_LIMIT 0x0ba3ffff
+#define NV_ADDRESS_MAP_RCE_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_CFG_HEADER araps_proc_cfg.h
+
+#define NV_ADDRESS_MAP_RCE_HSM_BASE 0x0ba40000
+#define NV_ADDRESS_MAP_RCE_HSM_LIMIT 0x0ba4ffff
+#define NV_ADDRESS_MAP_RCE_HSM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSM_HEADER arsce_hsm.h
+
+#define NV_ADDRESS_MAP_RCE_ATCM_EVP_EXT_BASE 0x0bc00000
+#define NV_ADDRESS_MAP_RCE_ATCM_EVP_EXT_LIMIT 0x0bc0ffff
+#define NV_ADDRESS_MAP_RCE_ATCM_EVP_EXT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_ATCM_EVP_EXT_HEADER arrce_evp.h
+
+#define NV_ADDRESS_MAP_RCE_BTCM_BASE 0x0bc80000
+#define NV_ADDRESS_MAP_RCE_BTCM_LIMIT 0x0bcdffff
+#define NV_ADDRESS_MAP_RCE_BTCM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_BTCM_HEADER no_headers
+
+#define NV_ADDRESS_MAP_RCE_ICACHE_ACCESS_PORT_BASE 0x0bd00000
+#define NV_ADDRESS_MAP_RCE_ICACHE_ACCESS_PORT_LIMIT 0x0bd7ffff
+#define NV_ADDRESS_MAP_RCE_ICACHE_ACCESS_PORT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_ICACHE_ACCESS_PORT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_RCE_DCACHE_ACCESS_PORT_BASE 0x0bd80000
+#define NV_ADDRESS_MAP_RCE_DCACHE_ACCESS_PORT_LIMIT 0x0bdfffff
+#define NV_ADDRESS_MAP_RCE_DCACHE_ACCESS_PORT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_DCACHE_ACCESS_PORT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_RCE_SN_AXI2APB_1_BASE 0x0be00000
+#define NV_ADDRESS_MAP_RCE_SN_AXI2APB_1_LIMIT 0x0be00fff
+#define NV_ADDRESS_MAP_RCE_SN_AXI2APB_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_SN_AXI2APB_1_HEADER
+
+#define NV_ADDRESS_MAP_RCE_MN_CPU_M_I_BASE 0x0be10000
+#define NV_ADDRESS_MAP_RCE_MN_CPU_M_I_LIMIT 0x0be10fff
+#define NV_ADDRESS_MAP_RCE_MN_CPU_M_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_MN_CPU_M_I_HEADER
+
+#define NV_ADDRESS_MAP_RCE_MN_CBB_I_BASE 0x0be11000
+#define NV_ADDRESS_MAP_RCE_MN_CBB_I_LIMIT 0x0be11fff
+#define NV_ADDRESS_MAP_RCE_MN_CBB_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_MN_CBB_I_HEADER
+
+#define NV_ADDRESS_MAP_RCE_MN_CPU_P_I_BASE 0x0be12000
+#define NV_ADDRESS_MAP_RCE_MN_CPU_P_I_LIMIT 0x0be12fff
+#define NV_ADDRESS_MAP_RCE_MN_CPU_P_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_MN_CPU_P_I_HEADER
+
+#define NV_ADDRESS_MAP_RCE_MN_DMA_M_I_BASE 0x0be13000
+#define NV_ADDRESS_MAP_RCE_MN_DMA_M_I_LIMIT 0x0be13fff
+#define NV_ADDRESS_MAP_RCE_MN_DMA_M_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_MN_DMA_M_I_HEADER
+
+#define NV_ADDRESS_MAP_RCE_MN_DMA_P_I_BASE 0x0be14000
+#define NV_ADDRESS_MAP_RCE_MN_DMA_P_I_LIMIT 0x0be14fff
+#define NV_ADDRESS_MAP_RCE_MN_DMA_P_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_MN_DMA_P_I_HEADER
+
+#define NV_ADDRESS_MAP_RCE_SN_AST0_T_BASE 0x0be15000
+#define NV_ADDRESS_MAP_RCE_SN_AST0_T_LIMIT 0x0be15fff
+#define NV_ADDRESS_MAP_RCE_SN_AST0_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_SN_AST0_T_HEADER
+
+#define NV_ADDRESS_MAP_RCE_SN_AST1_T_BASE 0x0be16000
+#define NV_ADDRESS_MAP_RCE_SN_AST1_T_LIMIT 0x0be16fff
+#define NV_ADDRESS_MAP_RCE_SN_AST1_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_SN_AST1_T_HEADER
+
+#define NV_ADDRESS_MAP_RCE_SN_CBB_T_BASE 0x0be17000
+#define NV_ADDRESS_MAP_RCE_SN_CBB_T_LIMIT 0x0be17fff
+#define NV_ADDRESS_MAP_RCE_SN_CBB_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_SN_CBB_T_HEADER
+
+#define NV_ADDRESS_MAP_RCE_SN_CPU_T_BASE 0x0be18000
+#define NV_ADDRESS_MAP_RCE_SN_CPU_T_LIMIT 0x0be18fff
+#define NV_ADDRESS_MAP_RCE_SN_CPU_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_SN_CPU_T_HEADER
+
+#define NV_ADDRESS_MAP_RCE_EN_CFG_BASE 0x0be19000
+#define NV_ADDRESS_MAP_RCE_EN_CFG_LIMIT 0x0be19fff
+#define NV_ADDRESS_MAP_RCE_EN_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_EN_CFG_HEADER
+
+#define NV_ADDRESS_MAP_RCE_FABRIC_ERR_COLLATOR_BASE 0x0be20000
+#define NV_ADDRESS_MAP_RCE_FABRIC_ERR_COLLATOR_LIMIT 0x0be20fff
+#define NV_ADDRESS_MAP_RCE_FABRIC_ERR_COLLATOR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_FABRIC_ERR_COLLATOR_HEADER
+
+#define NV_ADDRESS_MAP_RCE_ERR_COLLATOR_BASE 0x0be50000
+#define NV_ADDRESS_MAP_RCE_ERR_COLLATOR_LIMIT 0x0be5ffff
+#define NV_ADDRESS_MAP_RCE_ERR_COLLATOR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_ERR_COLLATOR_HEADER arsce_ec.h;arsce_ec_scr.h
+
+#define NV_ADDRESS_MAP_RCE_MISC_BASE 0x0be60000
+#define NV_ADDRESS_MAP_RCE_MISC_LIMIT 0x0be6ffff
+#define NV_ADDRESS_MAP_RCE_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_MISC_HEADER arsce_misc.h;arsce_misc_scr.h
+
+#define NV_ADDRESS_MAP_RCE_HSP1_COMMON_BASE 0x0be70000
+#define NV_ADDRESS_MAP_RCE_HSP1_COMMON_LIMIT 0x0be7ffff
+#define NV_ADDRESS_MAP_RCE_HSP1_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP1_COMMON_HEADER arhsp_int.h;arhsp_int_scr.h
+
+#define NV_ADDRESS_MAP_RCE_HSP1_SM_0_1_BASE 0x0be80000
+#define NV_ADDRESS_MAP_RCE_HSP1_SM_0_1_LIMIT 0x0be8ffff
+#define NV_ADDRESS_MAP_RCE_HSP1_SM_0_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP1_SM_0_1_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP1_SM_2_3_BASE 0x0be90000
+#define NV_ADDRESS_MAP_RCE_HSP1_SM_2_3_LIMIT 0x0be9ffff
+#define NV_ADDRESS_MAP_RCE_HSP1_SM_2_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP1_SM_2_3_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP1_SM_4_5_BASE 0x0bea0000
+#define NV_ADDRESS_MAP_RCE_HSP1_SM_4_5_LIMIT 0x0beaffff
+#define NV_ADDRESS_MAP_RCE_HSP1_SM_4_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP1_SM_4_5_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP1_SM_6_7_BASE 0x0beb0000
+#define NV_ADDRESS_MAP_RCE_HSP1_SM_6_7_LIMIT 0x0bebffff
+#define NV_ADDRESS_MAP_RCE_HSP1_SM_6_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP1_SM_6_7_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP1_SS_0_BASE 0x0bec0000
+#define NV_ADDRESS_MAP_RCE_HSP1_SS_0_LIMIT 0x0becffff
+#define NV_ADDRESS_MAP_RCE_HSP1_SS_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP1_SS_0_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP1_SS_1_BASE 0x0bed0000
+#define NV_ADDRESS_MAP_RCE_HSP1_SS_1_LIMIT 0x0bedffff
+#define NV_ADDRESS_MAP_RCE_HSP1_SS_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP1_SS_1_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP1_SS_2_BASE 0x0bee0000
+#define NV_ADDRESS_MAP_RCE_HSP1_SS_2_LIMIT 0x0beeffff
+#define NV_ADDRESS_MAP_RCE_HSP1_SS_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP1_SS_2_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP1_SS_3_BASE 0x0bef0000
+#define NV_ADDRESS_MAP_RCE_HSP1_SS_3_LIMIT 0x0befffff
+#define NV_ADDRESS_MAP_RCE_HSP1_SS_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP1_SS_3_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP2_COMMON_BASE 0x0bf00000
+#define NV_ADDRESS_MAP_RCE_HSP2_COMMON_LIMIT 0x0bf0ffff
+#define NV_ADDRESS_MAP_RCE_HSP2_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP2_COMMON_HEADER arhsp_int.h;arhsp_int_scr.h
+
+#define NV_ADDRESS_MAP_RCE_HSP2_SM_0_1_BASE 0x0bf10000
+#define NV_ADDRESS_MAP_RCE_HSP2_SM_0_1_LIMIT 0x0bf1ffff
+#define NV_ADDRESS_MAP_RCE_HSP2_SM_0_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP2_SM_0_1_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP2_SM_2_3_BASE 0x0bf20000
+#define NV_ADDRESS_MAP_RCE_HSP2_SM_2_3_LIMIT 0x0bf2ffff
+#define NV_ADDRESS_MAP_RCE_HSP2_SM_2_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP2_SM_2_3_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP2_SM_4_5_BASE 0x0bf30000
+#define NV_ADDRESS_MAP_RCE_HSP2_SM_4_5_LIMIT 0x0bf3ffff
+#define NV_ADDRESS_MAP_RCE_HSP2_SM_4_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP2_SM_4_5_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP2_SM_6_7_BASE 0x0bf40000
+#define NV_ADDRESS_MAP_RCE_HSP2_SM_6_7_LIMIT 0x0bf4ffff
+#define NV_ADDRESS_MAP_RCE_HSP2_SM_6_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP2_SM_6_7_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP2_SS_0_BASE 0x0bf50000
+#define NV_ADDRESS_MAP_RCE_HSP2_SS_0_LIMIT 0x0bf5ffff
+#define NV_ADDRESS_MAP_RCE_HSP2_SS_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP2_SS_0_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP2_SS_1_BASE 0x0bf60000
+#define NV_ADDRESS_MAP_RCE_HSP2_SS_1_LIMIT 0x0bf6ffff
+#define NV_ADDRESS_MAP_RCE_HSP2_SS_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP2_SS_1_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP2_SS_2_BASE 0x0bf70000
+#define NV_ADDRESS_MAP_RCE_HSP2_SS_2_LIMIT 0x0bf7ffff
+#define NV_ADDRESS_MAP_RCE_HSP2_SS_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP2_SS_2_HEADER
+
+#define NV_ADDRESS_MAP_RCE_HSP2_SS_3_BASE 0x0bf80000
+#define NV_ADDRESS_MAP_RCE_HSP2_SS_3_LIMIT 0x0bf8ffff
+#define NV_ADDRESS_MAP_RCE_HSP2_SS_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RCE_HSP2_SS_3_HEADER
+
+#define NV_ADDRESS_MAP_AON_ATCM_CFG_EVP_BASE 0x0c000000
+#define NV_ADDRESS_MAP_AON_ATCM_CFG_EVP_LIMIT 0x0c00ffff
+#define NV_ADDRESS_MAP_AON_ATCM_CFG_EVP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_ATCM_CFG_EVP_HEADER
+
+#define NV_ADDRESS_MAP_AON_VIC_0_BASE 0x0c020000
+#define NV_ADDRESS_MAP_AON_VIC_0_LIMIT 0x0c02ffff
+#define NV_ADDRESS_MAP_AON_VIC_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_VIC_0_HEADER araps_vic.h
+
+#define NV_ADDRESS_MAP_AON_VIC_1_BASE 0x0c030000
+#define NV_ADDRESS_MAP_AON_VIC_1_LIMIT 0x0c03ffff
+#define NV_ADDRESS_MAP_AON_VIC_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_VIC_1_HEADER araps_vic.h
+
+#define NV_ADDRESS_MAP_AON_AST_0_BASE 0x0c040000
+#define NV_ADDRESS_MAP_AON_AST_0_LIMIT 0x0c04ffff
+#define NV_ADDRESS_MAP_AON_AST_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_AST_0_HEADER araps_ast.h;araps_ast_scr.h
+
+#define NV_ADDRESS_MAP_AON_AST_1_BASE 0x0c050000
+#define NV_ADDRESS_MAP_AON_AST_1_LIMIT 0x0c05ffff
+#define NV_ADDRESS_MAP_AON_AST_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_AST_1_HEADER araps_ast.h;araps_ast_scr.h
+
+#define NV_ADDRESS_MAP_AON_DMA_COMMON_BASE 0x0c060000
+#define NV_ADDRESS_MAP_AON_DMA_COMMON_LIMIT 0x0c06ffff
+#define NV_ADDRESS_MAP_AON_DMA_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_DMA_COMMON_HEADER
+
+#define NV_ADDRESS_MAP_AON_DMA_CH_0_BASE 0x0c070000
+#define NV_ADDRESS_MAP_AON_DMA_CH_0_LIMIT 0x0c07ffff
+#define NV_ADDRESS_MAP_AON_DMA_CH_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_DMA_CH_0_HEADER
+
+#define NV_ADDRESS_MAP_AON_DMA_CH_1_BASE 0x0c080000
+#define NV_ADDRESS_MAP_AON_DMA_CH_1_LIMIT 0x0c08ffff
+#define NV_ADDRESS_MAP_AON_DMA_CH_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_DMA_CH_1_HEADER
+
+#define NV_ADDRESS_MAP_AON_DMA_CH_2_BASE 0x0c090000
+#define NV_ADDRESS_MAP_AON_DMA_CH_2_LIMIT 0x0c09ffff
+#define NV_ADDRESS_MAP_AON_DMA_CH_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_DMA_CH_2_HEADER
+
+#define NV_ADDRESS_MAP_AON_DMA_CH_3_BASE 0x0c0a0000
+#define NV_ADDRESS_MAP_AON_DMA_CH_3_LIMIT 0x0c0affff
+#define NV_ADDRESS_MAP_AON_DMA_CH_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_DMA_CH_3_HEADER
+
+#define NV_ADDRESS_MAP_AON_DMA_CH_4_BASE 0x0c0b0000
+#define NV_ADDRESS_MAP_AON_DMA_CH_4_LIMIT 0x0c0bffff
+#define NV_ADDRESS_MAP_AON_DMA_CH_4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_DMA_CH_4_HEADER
+
+#define NV_ADDRESS_MAP_AON_DMA_CH_5_BASE 0x0c0c0000
+#define NV_ADDRESS_MAP_AON_DMA_CH_5_LIMIT 0x0c0cffff
+#define NV_ADDRESS_MAP_AON_DMA_CH_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_DMA_CH_5_HEADER
+
+#define NV_ADDRESS_MAP_AON_DMA_CH_6_BASE 0x0c0d0000
+#define NV_ADDRESS_MAP_AON_DMA_CH_6_LIMIT 0x0c0dffff
+#define NV_ADDRESS_MAP_AON_DMA_CH_6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_DMA_CH_6_HEADER
+
+#define NV_ADDRESS_MAP_AON_DMA_CH_7_BASE 0x0c0e0000
+#define NV_ADDRESS_MAP_AON_DMA_CH_7_LIMIT 0x0c0effff
+#define NV_ADDRESS_MAP_AON_DMA_CH_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_DMA_CH_7_HEADER
+
+#define NV_ADDRESS_MAP_AON_TKE_SHARED_BASE 0x0c0f0000
+#define NV_ADDRESS_MAP_AON_TKE_SHARED_LIMIT 0x0c0fffff
+#define NV_ADDRESS_MAP_AON_TKE_SHARED_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_TKE_SHARED_HEADER
+
+#define NV_ADDRESS_MAP_AON_TKE_TMR_0_BASE 0x0c100000
+#define NV_ADDRESS_MAP_AON_TKE_TMR_0_LIMIT 0x0c10ffff
+#define NV_ADDRESS_MAP_AON_TKE_TMR_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_TKE_TMR_0_HEADER
+
+#define NV_ADDRESS_MAP_AON_TKE_TMR_1_BASE 0x0c110000
+#define NV_ADDRESS_MAP_AON_TKE_TMR_1_LIMIT 0x0c11ffff
+#define NV_ADDRESS_MAP_AON_TKE_TMR_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_TKE_TMR_1_HEADER
+
+#define NV_ADDRESS_MAP_AON_TKE_TMR_2_BASE 0x0c120000
+#define NV_ADDRESS_MAP_AON_TKE_TMR_2_LIMIT 0x0c12ffff
+#define NV_ADDRESS_MAP_AON_TKE_TMR_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_TKE_TMR_2_HEADER
+
+#define NV_ADDRESS_MAP_AON_TKE_TMR_3_BASE 0x0c130000
+#define NV_ADDRESS_MAP_AON_TKE_TMR_3_LIMIT 0x0c13ffff
+#define NV_ADDRESS_MAP_AON_TKE_TMR_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_TKE_TMR_3_HEADER
+
+#define NV_ADDRESS_MAP_AON_TKE_WDT_0_BASE 0x0c140000
+#define NV_ADDRESS_MAP_AON_TKE_WDT_0_LIMIT 0x0c14ffff
+#define NV_ADDRESS_MAP_AON_TKE_WDT_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_TKE_WDT_0_HEADER
+
+#define NV_ADDRESS_MAP_AON_HSP_COMMON_BASE 0x0c150000
+#define NV_ADDRESS_MAP_AON_HSP_COMMON_LIMIT 0x0c15ffff
+#define NV_ADDRESS_MAP_AON_HSP_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_HSP_COMMON_HEADER arhsp_int_aon.h;arhsp_int_aon_scr.h
+
+#define NV_ADDRESS_MAP_AON_HSP_SM_0_1_BASE 0x0c160000
+#define NV_ADDRESS_MAP_AON_HSP_SM_0_1_LIMIT 0x0c16ffff
+#define NV_ADDRESS_MAP_AON_HSP_SM_0_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_HSP_SM_0_1_HEADER
+
+#define NV_ADDRESS_MAP_AON_HSP_SM_2_3_BASE 0x0c170000
+#define NV_ADDRESS_MAP_AON_HSP_SM_2_3_LIMIT 0x0c17ffff
+#define NV_ADDRESS_MAP_AON_HSP_SM_2_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_HSP_SM_2_3_HEADER
+
+#define NV_ADDRESS_MAP_AON_HSP_SM_4_5_BASE 0x0c180000
+#define NV_ADDRESS_MAP_AON_HSP_SM_4_5_LIMIT 0x0c18ffff
+#define NV_ADDRESS_MAP_AON_HSP_SM_4_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_HSP_SM_4_5_HEADER
+
+#define NV_ADDRESS_MAP_AON_HSP_SM_6_7_BASE 0x0c190000
+#define NV_ADDRESS_MAP_AON_HSP_SM_6_7_LIMIT 0x0c19ffff
+#define NV_ADDRESS_MAP_AON_HSP_SM_6_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_HSP_SM_6_7_HEADER
+
+#define NV_ADDRESS_MAP_AON_HSP_SS_0_BASE 0x0c1a0000
+#define NV_ADDRESS_MAP_AON_HSP_SS_0_LIMIT 0x0c1affff
+#define NV_ADDRESS_MAP_AON_HSP_SS_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_HSP_SS_0_HEADER
+
+#define NV_ADDRESS_MAP_AON_HSP_SS_1_BASE 0x0c1b0000
+#define NV_ADDRESS_MAP_AON_HSP_SS_1_LIMIT 0x0c1bffff
+#define NV_ADDRESS_MAP_AON_HSP_SS_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_HSP_SS_1_HEADER
+
+#define NV_ADDRESS_MAP_AON_HSP_SS_2_BASE 0x0c1c0000
+#define NV_ADDRESS_MAP_AON_HSP_SS_2_LIMIT 0x0c1cffff
+#define NV_ADDRESS_MAP_AON_HSP_SS_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_HSP_SS_2_HEADER
+
+#define NV_ADDRESS_MAP_AON_HSP_SS_3_BASE 0x0c1d0000
+#define NV_ADDRESS_MAP_AON_HSP_SS_3_LIMIT 0x0c1dffff
+#define NV_ADDRESS_MAP_AON_HSP_SS_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_HSP_SS_3_HEADER
+
+#define NV_ADDRESS_MAP_AON_GTE_BASE 0x0c1e0000
+#define NV_ADDRESS_MAP_AON_GTE_LIMIT 0x0c1effff
+#define NV_ADDRESS_MAP_AON_GTE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_GTE_HEADER argte_gpio.h;argte_gpio_scr.h
+
+#define NV_ADDRESS_MAP_AON_PM_IMPL_BASE 0x0c1f0000
+#define NV_ADDRESS_MAP_AON_PM_IMPL_LIMIT 0x0c1fffff
+#define NV_ADDRESS_MAP_AON_PM_IMPL_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_PM_IMPL_HEADER araopm.h;araopm_scr.h
+
+#define NV_ADDRESS_MAP_AON_ACTMON_BASE 0x0c200000
+#define NV_ADDRESS_MAP_AON_ACTMON_LIMIT 0x0c20ffff
+#define NV_ADDRESS_MAP_AON_ACTMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_ACTMON_HEADER arunit_actmon.h
+
+#define NV_ADDRESS_MAP_AON_CAN_RAM_CTL_BASE 0x0c210000
+#define NV_ADDRESS_MAP_AON_CAN_RAM_CTL_LIMIT 0x0c21ffff
+#define NV_ADDRESS_MAP_AON_CAN_RAM_CTL_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_CAN_RAM_CTL_HEADER no_headers
+
+#define NV_ADDRESS_MAP_I2C2_BASE 0x0c240000
+#define NV_ADDRESS_MAP_I2C2_LIMIT 0x0c24ffff
+#define NV_ADDRESS_MAP_I2C2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_I2C2_HEADER ari2c.h
+
+#define NV_ADDRESS_MAP_I2C8_BASE 0x0c250000
+#define NV_ADDRESS_MAP_I2C8_LIMIT 0x0c25ffff
+#define NV_ADDRESS_MAP_I2C8_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_I2C8_HEADER ari2c.h
+
+#define NV_ADDRESS_MAP_SPI2_BASE 0x0c260000
+#define NV_ADDRESS_MAP_SPI2_LIMIT 0x0c26ffff
+#define NV_ADDRESS_MAP_SPI2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SPI2_HEADER arspi.h
+
+#define NV_ADDRESS_MAP_UARTJ_BASE 0x0c270000
+#define NV_ADDRESS_MAP_UARTJ_LIMIT 0x0c27ffff
+#define NV_ADDRESS_MAP_UARTJ_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UARTJ_HEADER arsbsa_uart.h
+
+#define NV_ADDRESS_MAP_UARTC_BASE 0x0c280000
+#define NV_ADDRESS_MAP_UARTC_LIMIT 0x0c28ffff
+#define NV_ADDRESS_MAP_UARTC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_UARTC_HEADER aruart.h
+
+#define NV_ADDRESS_MAP_RTC_BASE 0x0c2a0000
+#define NV_ADDRESS_MAP_RTC_LIMIT 0x0c2affff
+#define NV_ADDRESS_MAP_RTC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RTC_HEADER arrtc2.h;arrtc2_scr.h
+
+#define NV_ADDRESS_MAP_AON_GPIO_0_BASE 0x0c2f0000
+#define NV_ADDRESS_MAP_AON_GPIO_0_LIMIT 0x0c2fffff
+#define NV_ADDRESS_MAP_AON_GPIO_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_GPIO_0_HEADER argpio_common_aon.h;argpio_aon.h
+
+#define NV_ADDRESS_MAP_PADCTL_A12_BASE 0x0c301000
+#define NV_ADDRESS_MAP_PADCTL_A12_LIMIT 0x0c301fff
+#define NV_ADDRESS_MAP_PADCTL_A12_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A12_HEADER arpadctl_SYS.h;arpadctl_SYS_scr.h
+
+#define NV_ADDRESS_MAP_PADCTL_A14_BASE 0x0c302000
+#define NV_ADDRESS_MAP_PADCTL_A14_LIMIT 0x0c302fff
+#define NV_ADDRESS_MAP_PADCTL_A14_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A14_HEADER arpadctl_AO.h;arpadctl_AO_scr.h
+
+#define NV_ADDRESS_MAP_PADCTL_A15_BASE 0x0c303000
+#define NV_ADDRESS_MAP_PADCTL_A15_LIMIT 0x0c303fff
+#define NV_ADDRESS_MAP_PADCTL_A15_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PADCTL_A15_HEADER arpadctl_AO_HV.h;arpadctl_AO_HV_scr.h
+
+#define NV_ADDRESS_MAP_CAN1_BASE 0x0c310000
+#define NV_ADDRESS_MAP_CAN1_LIMIT 0x0c31ffff
+#define NV_ADDRESS_MAP_CAN1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CAN1_HEADER arm_ttcan.h;arm_ttcan_core.h
+
+#define NV_ADDRESS_MAP_CAN2_BASE 0x0c320000
+#define NV_ADDRESS_MAP_CAN2_LIMIT 0x0c32ffff
+#define NV_ADDRESS_MAP_CAN2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CAN2_HEADER arm_ttcan.h;arm_ttcan_core.h
+
+#define NV_ADDRESS_MAP_DMIC5_BASE 0x0c330000
+#define NV_ADDRESS_MAP_DMIC5_LIMIT 0x0c33ffff
+#define NV_ADDRESS_MAP_DMIC5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DMIC5_HEADER araodmic.h
+
+#define NV_ADDRESS_MAP_PWM4_BASE 0x0c340000
+#define NV_ADDRESS_MAP_PWM4_LIMIT 0x0c34ffff
+#define NV_ADDRESS_MAP_PWM4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PWM4_HEADER arpwm.h
+
+#define NV_ADDRESS_MAP_AON_MSS_BASE 0x0c350000
+#define NV_ADDRESS_MAP_AON_MSS_LIMIT 0x0c35ffff
+#define NV_ADDRESS_MAP_AON_MSS_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_MSS_HEADER armss_aon_cfg.h;armss_aon_cfg_scr.h;armss_aon_scratch_scr.h
+
+#define NV_ADDRESS_MAP_PMC_IMPL_BASE 0x0c360000
+#define NV_ADDRESS_MAP_PMC_IMPL_LIMIT 0x0c36ffff
+#define NV_ADDRESS_MAP_PMC_IMPL_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PMC_IMPL_HEADER arpmc_impl.h;arpmc_impl_scr.h
+
+#define NV_ADDRESS_MAP_WAKE_BASE 0x0c370000
+#define NV_ADDRESS_MAP_WAKE_LIMIT 0x0c37ffff
+#define NV_ADDRESS_MAP_WAKE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_WAKE_HEADER arwake.h;arwake_scr.h
+
+#define NV_ADDRESS_MAP_SCRATCH_BASE 0x0c390000
+#define NV_ADDRESS_MAP_SCRATCH_LIMIT 0x0c39ffff
+#define NV_ADDRESS_MAP_SCRATCH_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SCRATCH_HEADER arscratch.h;arscratch_scr.h
+
+#define NV_ADDRESS_MAP_PMC_MISC_BASE 0x0c3a0000
+#define NV_ADDRESS_MAP_PMC_MISC_LIMIT 0x0c3affff
+#define NV_ADDRESS_MAP_PMC_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PMC_MISC_HEADER arpmc_misc.h;arpmc_misc_scr.h
+
+#define NV_ADDRESS_MAP_AON_CEC_BASE 0x0c3e0000
+#define NV_ADDRESS_MAP_AON_CEC_LIMIT 0x0c3effff
+#define NV_ADDRESS_MAP_AON_CEC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_CEC_HEADER arcec.h
+
+#define NV_ADDRESS_MAP_AON_ATCM_EVP_EXT_BASE 0x0c400000
+#define NV_ADDRESS_MAP_AON_ATCM_EVP_EXT_LIMIT 0x0c40ffff
+#define NV_ADDRESS_MAP_AON_ATCM_EVP_EXT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_ATCM_EVP_EXT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_AON_BTCM_BASE 0x0c480000
+#define NV_ADDRESS_MAP_AON_BTCM_LIMIT 0x0c4bffff
+#define NV_ADDRESS_MAP_AON_BTCM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_BTCM_HEADER no_headers
+
+#define NV_ADDRESS_MAP_AON_ICACHE_ACCESS_PORT_BASE 0x0c500000
+#define NV_ADDRESS_MAP_AON_ICACHE_ACCESS_PORT_LIMIT 0x0c57ffff
+#define NV_ADDRESS_MAP_AON_ICACHE_ACCESS_PORT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_ICACHE_ACCESS_PORT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_AON_DCACHE_ACCESS_PORT_BASE 0x0c580000
+#define NV_ADDRESS_MAP_AON_DCACHE_ACCESS_PORT_LIMIT 0x0c5fffff
+#define NV_ADDRESS_MAP_AON_DCACHE_ACCESS_PORT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_DCACHE_ACCESS_PORT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_AON_SN_AXI2APB_1_BASE 0x0c600000
+#define NV_ADDRESS_MAP_AON_SN_AXI2APB_1_LIMIT 0x0c600fff
+#define NV_ADDRESS_MAP_AON_SN_AXI2APB_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_SN_AXI2APB_1_HEADER
+
+#define NV_ADDRESS_MAP_AON_MN_CPU_P_I_BASE 0x0c610000
+#define NV_ADDRESS_MAP_AON_MN_CPU_P_I_LIMIT 0x0c610fff
+#define NV_ADDRESS_MAP_AON_MN_CPU_P_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_MN_CPU_P_I_HEADER
+
+#define NV_ADDRESS_MAP_AON_MN_DMA_P_I_BASE 0x0c611000
+#define NV_ADDRESS_MAP_AON_MN_DMA_P_I_LIMIT 0x0c611fff
+#define NV_ADDRESS_MAP_AON_MN_DMA_P_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_MN_DMA_P_I_HEADER
+
+#define NV_ADDRESS_MAP_AON_MN_CBB_I_BASE 0x0c612000
+#define NV_ADDRESS_MAP_AON_MN_CBB_I_LIMIT 0x0c612fff
+#define NV_ADDRESS_MAP_AON_MN_CBB_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_MN_CBB_I_HEADER
+
+#define NV_ADDRESS_MAP_AON_MN_DMA_M_I_BASE 0x0c613000
+#define NV_ADDRESS_MAP_AON_MN_DMA_M_I_LIMIT 0x0c613fff
+#define NV_ADDRESS_MAP_AON_MN_DMA_M_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_MN_DMA_M_I_HEADER
+
+#define NV_ADDRESS_MAP_AON_SN_AST1_T_BASE 0x0c614000
+#define NV_ADDRESS_MAP_AON_SN_AST1_T_LIMIT 0x0c614fff
+#define NV_ADDRESS_MAP_AON_SN_AST1_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_SN_AST1_T_HEADER
+
+#define NV_ADDRESS_MAP_AON_SN_CBB_T_BASE 0x0c615000
+#define NV_ADDRESS_MAP_AON_SN_CBB_T_LIMIT 0x0c615fff
+#define NV_ADDRESS_MAP_AON_SN_CBB_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_SN_CBB_T_HEADER
+
+#define NV_ADDRESS_MAP_AON_SN_CPU_T_BASE 0x0c616000
+#define NV_ADDRESS_MAP_AON_SN_CPU_T_LIMIT 0x0c616fff
+#define NV_ADDRESS_MAP_AON_SN_CPU_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_SN_CPU_T_HEADER
+
+#define NV_ADDRESS_MAP_AON_EN_CFG_BASE 0x0c617000
+#define NV_ADDRESS_MAP_AON_EN_CFG_LIMIT 0x0c617fff
+#define NV_ADDRESS_MAP_AON_EN_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_EN_CFG_HEADER
+
+#define NV_ADDRESS_MAP_AON_FABRIC_NPG_ERR_COLLATOR_BASE 0x0c620000
+#define NV_ADDRESS_MAP_AON_FABRIC_NPG_ERR_COLLATOR_LIMIT 0x0c620fff
+#define NV_ADDRESS_MAP_AON_FABRIC_NPG_ERR_COLLATOR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_FABRIC_NPG_ERR_COLLATOR_HEADER
+
+#define NV_ADDRESS_MAP_AON_FABRIC_PG_ERR_COLLATOR_BASE 0x0c621000
+#define NV_ADDRESS_MAP_AON_FABRIC_PG_ERR_COLLATOR_LIMIT 0x0c621fff
+#define NV_ADDRESS_MAP_AON_FABRIC_PG_ERR_COLLATOR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_FABRIC_PG_ERR_COLLATOR_HEADER
+
+#define NV_ADDRESS_MAP_AON_ERR_COLLATOR_BASE 0x0c650000
+#define NV_ADDRESS_MAP_AON_ERR_COLLATOR_LIMIT 0x0c65ffff
+#define NV_ADDRESS_MAP_AON_ERR_COLLATOR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_ERR_COLLATOR_HEADER araoncluster_error_collator.h;araoncluster_error_collator_scr.h
+
+#define NV_ADDRESS_MAP_AON_MISC_BASE 0x0c660000
+#define NV_ADDRESS_MAP_AON_MISC_LIMIT 0x0c66ffff
+#define NV_ADDRESS_MAP_AON_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_MISC_HEADER araon_misc.h;araon_misc_scr.h
+
+#define NV_ADDRESS_MAP_SYSCTR0_BASE 0x0c670000
+#define NV_ADDRESS_MAP_SYSCTR0_LIMIT 0x0c67ffff
+#define NV_ADDRESS_MAP_SYSCTR0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SYSCTR0_HEADER artsc_sysctr0.h
+
+#define NV_ADDRESS_MAP_SYSCTR1_BASE 0x0c680000
+#define NV_ADDRESS_MAP_SYSCTR1_LIMIT 0x0c68ffff
+#define NV_ADDRESS_MAP_SYSCTR1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SYSCTR1_HEADER artsc_sysctr1.h
+
+#define NV_ADDRESS_MAP_SYSCTR2_BASE 0x0c690000
+#define NV_ADDRESS_MAP_SYSCTR2_LIMIT 0x0c69ffff
+#define NV_ADDRESS_MAP_SYSCTR2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SYSCTR2_HEADER artsc_sysctr2.h
+
+#define NV_ADDRESS_MAP_TSC_IMPL_BASE 0x0c6a0000
+#define NV_ADDRESS_MAP_TSC_IMPL_LIMIT 0x0c6affff
+#define NV_ADDRESS_MAP_TSC_IMPL_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSC_IMPL_HEADER artsc.h;artsc_scr.h
+
+#define NV_ADDRESS_MAP_TSCUS_BASE 0x0c6b0000
+#define NV_ADDRESS_MAP_TSCUS_LIMIT 0x0c6bffff
+#define NV_ADDRESS_MAP_TSCUS_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_TSCUS_HEADER arusec_cntr.h;arusec_cntr_scr.h
+
+#define NV_ADDRESS_MAP_BPMP_ATCM_CFG_EVP_BASE 0x0d000000
+#define NV_ADDRESS_MAP_BPMP_ATCM_CFG_EVP_LIMIT 0x0d00ffff
+#define NV_ADDRESS_MAP_BPMP_ATCM_CFG_EVP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_ATCM_CFG_EVP_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_IPATCH_BASE 0x0d010000
+#define NV_ADDRESS_MAP_BPMP_IPATCH_LIMIT 0x0d01ffff
+#define NV_ADDRESS_MAP_BPMP_IPATCH_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_IPATCH_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_VIC_0_BASE 0x0d020000
+#define NV_ADDRESS_MAP_BPMP_VIC_0_LIMIT 0x0d02ffff
+#define NV_ADDRESS_MAP_BPMP_VIC_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_VIC_0_HEADER araps_vic.h
+
+#define NV_ADDRESS_MAP_BPMP_VIC_1_BASE 0x0d030000
+#define NV_ADDRESS_MAP_BPMP_VIC_1_LIMIT 0x0d03ffff
+#define NV_ADDRESS_MAP_BPMP_VIC_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_VIC_1_HEADER araps_vic.h
+
+#define NV_ADDRESS_MAP_BPMP_AST_0_BASE 0x0d040000
+#define NV_ADDRESS_MAP_BPMP_AST_0_LIMIT 0x0d04ffff
+#define NV_ADDRESS_MAP_BPMP_AST_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_AST_0_HEADER araps_ast.h;araps_ast_scr.h
+
+#define NV_ADDRESS_MAP_BPMP_AST_1_BASE 0x0d050000
+#define NV_ADDRESS_MAP_BPMP_AST_1_LIMIT 0x0d05ffff
+#define NV_ADDRESS_MAP_BPMP_AST_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_AST_1_HEADER araps_ast.h;araps_ast_scr.h
+
+#define NV_ADDRESS_MAP_BPMP_DMA_COMMON_BASE 0x0d060000
+#define NV_ADDRESS_MAP_BPMP_DMA_COMMON_LIMIT 0x0d06ffff
+#define NV_ADDRESS_MAP_BPMP_DMA_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_DMA_COMMON_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_DMA_CH_0_BASE 0x0d070000
+#define NV_ADDRESS_MAP_BPMP_DMA_CH_0_LIMIT 0x0d07ffff
+#define NV_ADDRESS_MAP_BPMP_DMA_CH_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_DMA_CH_0_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_DMA_CH_1_BASE 0x0d080000
+#define NV_ADDRESS_MAP_BPMP_DMA_CH_1_LIMIT 0x0d08ffff
+#define NV_ADDRESS_MAP_BPMP_DMA_CH_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_DMA_CH_1_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_DMA_CH_2_BASE 0x0d090000
+#define NV_ADDRESS_MAP_BPMP_DMA_CH_2_LIMIT 0x0d09ffff
+#define NV_ADDRESS_MAP_BPMP_DMA_CH_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_DMA_CH_2_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_DMA_CH_3_BASE 0x0d0a0000
+#define NV_ADDRESS_MAP_BPMP_DMA_CH_3_LIMIT 0x0d0affff
+#define NV_ADDRESS_MAP_BPMP_DMA_CH_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_DMA_CH_3_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_TKE_SHARED_BASE 0x0d0f0000
+#define NV_ADDRESS_MAP_BPMP_TKE_SHARED_LIMIT 0x0d0fffff
+#define NV_ADDRESS_MAP_BPMP_TKE_SHARED_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_TKE_SHARED_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_TKE_TMR_0_BASE 0x0d100000
+#define NV_ADDRESS_MAP_BPMP_TKE_TMR_0_LIMIT 0x0d10ffff
+#define NV_ADDRESS_MAP_BPMP_TKE_TMR_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_TKE_TMR_0_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_TKE_TMR_1_BASE 0x0d110000
+#define NV_ADDRESS_MAP_BPMP_TKE_TMR_1_LIMIT 0x0d11ffff
+#define NV_ADDRESS_MAP_BPMP_TKE_TMR_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_TKE_TMR_1_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_TKE_TMR_2_BASE 0x0d120000
+#define NV_ADDRESS_MAP_BPMP_TKE_TMR_2_LIMIT 0x0d12ffff
+#define NV_ADDRESS_MAP_BPMP_TKE_TMR_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_TKE_TMR_2_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_TKE_TMR_3_BASE 0x0d130000
+#define NV_ADDRESS_MAP_BPMP_TKE_TMR_3_LIMIT 0x0d13ffff
+#define NV_ADDRESS_MAP_BPMP_TKE_TMR_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_TKE_TMR_3_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_TKE_WDT_0_BASE 0x0d140000
+#define NV_ADDRESS_MAP_BPMP_TKE_WDT_0_LIMIT 0x0d14ffff
+#define NV_ADDRESS_MAP_BPMP_TKE_WDT_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_TKE_WDT_0_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_HSP_COMMON_BASE 0x0d150000
+#define NV_ADDRESS_MAP_BPMP_HSP_COMMON_LIMIT 0x0d15ffff
+#define NV_ADDRESS_MAP_BPMP_HSP_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_HSP_COMMON_HEADER arhsp_int.h;arhsp_int_scr.h
+
+#define NV_ADDRESS_MAP_BPMP_HSP_SM_0_1_BASE 0x0d160000
+#define NV_ADDRESS_MAP_BPMP_HSP_SM_0_1_LIMIT 0x0d16ffff
+#define NV_ADDRESS_MAP_BPMP_HSP_SM_0_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_HSP_SM_0_1_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_HSP_SM_2_3_BASE 0x0d170000
+#define NV_ADDRESS_MAP_BPMP_HSP_SM_2_3_LIMIT 0x0d17ffff
+#define NV_ADDRESS_MAP_BPMP_HSP_SM_2_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_HSP_SM_2_3_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_HSP_SM_4_5_BASE 0x0d180000
+#define NV_ADDRESS_MAP_BPMP_HSP_SM_4_5_LIMIT 0x0d18ffff
+#define NV_ADDRESS_MAP_BPMP_HSP_SM_4_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_HSP_SM_4_5_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_HSP_SM_6_7_BASE 0x0d190000
+#define NV_ADDRESS_MAP_BPMP_HSP_SM_6_7_LIMIT 0x0d19ffff
+#define NV_ADDRESS_MAP_BPMP_HSP_SM_6_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_HSP_SM_6_7_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_HSP_SS_0_BASE 0x0d1a0000
+#define NV_ADDRESS_MAP_BPMP_HSP_SS_0_LIMIT 0x0d1affff
+#define NV_ADDRESS_MAP_BPMP_HSP_SS_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_HSP_SS_0_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_HSP_SS_1_BASE 0x0d1b0000
+#define NV_ADDRESS_MAP_BPMP_HSP_SS_1_LIMIT 0x0d1bffff
+#define NV_ADDRESS_MAP_BPMP_HSP_SS_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_HSP_SS_1_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_HSP_SS_2_BASE 0x0d1c0000
+#define NV_ADDRESS_MAP_BPMP_HSP_SS_2_LIMIT 0x0d1cffff
+#define NV_ADDRESS_MAP_BPMP_HSP_SS_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_HSP_SS_2_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_HSP_SS_3_BASE 0x0d1d0000
+#define NV_ADDRESS_MAP_BPMP_HSP_SS_3_LIMIT 0x0d1dffff
+#define NV_ADDRESS_MAP_BPMP_HSP_SS_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_HSP_SS_3_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_GTE_BASE 0x0d1e0000
+#define NV_ADDRESS_MAP_BPMP_GTE_LIMIT 0x0d1effff
+#define NV_ADDRESS_MAP_BPMP_GTE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_GTE_HEADER argte_aps.h;argte_aps_scr.h
+
+#define NV_ADDRESS_MAP_BPMP_PM_IMPL_BASE 0x0d1f0000
+#define NV_ADDRESS_MAP_BPMP_PM_IMPL_LIMIT 0x0d1fffff
+#define NV_ADDRESS_MAP_BPMP_PM_IMPL_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_PM_IMPL_HEADER arbpmppm.h;arbpmppm_scr.h
+
+#define NV_ADDRESS_MAP_BPMP_ACTMON_BASE 0x0d200000
+#define NV_ADDRESS_MAP_BPMP_ACTMON_LIMIT 0x0d20ffff
+#define NV_ADDRESS_MAP_BPMP_ACTMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_ACTMON_HEADER arunit_actmon.h
+
+#define NV_ADDRESS_MAP_SECURE_BOOT_BASE 0x0d210000
+#define NV_ADDRESS_MAP_SECURE_BOOT_LIMIT 0x0d21ffff
+#define NV_ADDRESS_MAP_SECURE_BOOT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SECURE_BOOT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_ACTMON_BASE 0x0d230000
+#define NV_ADDRESS_MAP_ACTMON_LIMIT 0x0d23ffff
+#define NV_ADDRESS_MAP_ACTMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_ACTMON_HEADER aractmon.h
+
+#define NV_ADDRESS_MAP_SOC_THERM_BASE 0x0d280000
+#define NV_ADDRESS_MAP_SOC_THERM_LIMIT 0x0d28ffff
+#define NV_ADDRESS_MAP_SOC_THERM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SOC_THERM_HEADER arsoc_therm.h;arsoc_therm_scr.h
+
+#define NV_ADDRESS_MAP_CENTRAL_VTG_CTLR_BASE 0x0d290000
+#define NV_ADDRESS_MAP_CENTRAL_VTG_CTLR_LIMIT 0x0d29ffff
+#define NV_ADDRESS_MAP_CENTRAL_VTG_CTLR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CENTRAL_VTG_CTLR_HEADER arbpmpcvc.h;arbpmpcvc_scr.h
+
+#define NV_ADDRESS_MAP_CENTRAL_PWR_MGR_BASE 0x0d2a0000
+#define NV_ADDRESS_MAP_CENTRAL_PWR_MGR_LIMIT 0x0d2affff
+#define NV_ADDRESS_MAP_CENTRAL_PWR_MGR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CENTRAL_PWR_MGR_HEADER no_headers
+
+#define NV_ADDRESS_MAP_BPMP_CFG_BASE 0x0d2c0000
+#define NV_ADDRESS_MAP_BPMP_CFG_LIMIT 0x0d2cffff
+#define NV_ADDRESS_MAP_BPMP_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_CFG_HEADER araps_proc_cfg.h
+
+#define NV_ADDRESS_MAP_BPMP_ATCM_EVP_EXT_BASE 0x0d400000
+#define NV_ADDRESS_MAP_BPMP_ATCM_EVP_EXT_LIMIT 0x0d40ffff
+#define NV_ADDRESS_MAP_BPMP_ATCM_EVP_EXT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_ATCM_EVP_EXT_HEADER arbpmp_evp.h
+
+#define NV_ADDRESS_MAP_BPMP_BOOTROM_EXT_BASE 0x0d410000
+#define NV_ADDRESS_MAP_BPMP_BOOTROM_EXT_LIMIT 0x0d43ffff
+#define NV_ADDRESS_MAP_BPMP_BOOTROM_EXT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_BOOTROM_EXT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_BPMP_BTCM_BASE 0x0d480000
+#define NV_ADDRESS_MAP_BPMP_BTCM_LIMIT 0x0d49ffff
+#define NV_ADDRESS_MAP_BPMP_BTCM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_BTCM_HEADER no_headers
+
+#define NV_ADDRESS_MAP_BPMP_ICACHE_ACCESS_PORT_BASE 0x0d500000
+#define NV_ADDRESS_MAP_BPMP_ICACHE_ACCESS_PORT_LIMIT 0x0d57ffff
+#define NV_ADDRESS_MAP_BPMP_ICACHE_ACCESS_PORT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_ICACHE_ACCESS_PORT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_BPMP_DCACHE_ACCESS_PORT_BASE 0x0d580000
+#define NV_ADDRESS_MAP_BPMP_DCACHE_ACCESS_PORT_LIMIT 0x0d5fffff
+#define NV_ADDRESS_MAP_BPMP_DCACHE_ACCESS_PORT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_DCACHE_ACCESS_PORT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_BPMP_SN_AXI2APB_1_BASE 0x0d600000
+#define NV_ADDRESS_MAP_BPMP_SN_AXI2APB_1_LIMIT 0x0d600fff
+#define NV_ADDRESS_MAP_BPMP_SN_AXI2APB_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_SN_AXI2APB_1_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_MN_CPU_M_I_BASE 0x0d610000
+#define NV_ADDRESS_MAP_BPMP_MN_CPU_M_I_LIMIT 0x0d610fff
+#define NV_ADDRESS_MAP_BPMP_MN_CPU_M_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_MN_CPU_M_I_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_MN_CBB_I_BASE 0x0d611000
+#define NV_ADDRESS_MAP_BPMP_MN_CBB_I_LIMIT 0x0d611fff
+#define NV_ADDRESS_MAP_BPMP_MN_CBB_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_MN_CBB_I_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_MN_CPU_P_I_BASE 0x0d612000
+#define NV_ADDRESS_MAP_BPMP_MN_CPU_P_I_LIMIT 0x0d612fff
+#define NV_ADDRESS_MAP_BPMP_MN_CPU_P_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_MN_CPU_P_I_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_MN_DMA_P_I_BASE 0x0d613000
+#define NV_ADDRESS_MAP_BPMP_MN_DMA_P_I_LIMIT 0x0d613fff
+#define NV_ADDRESS_MAP_BPMP_MN_DMA_P_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_MN_DMA_P_I_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_MN_DMA_M_I_BASE 0x0d614000
+#define NV_ADDRESS_MAP_BPMP_MN_DMA_M_I_LIMIT 0x0d614fff
+#define NV_ADDRESS_MAP_BPMP_MN_DMA_M_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_MN_DMA_M_I_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_SN_AST0_T_BASE 0x0d615000
+#define NV_ADDRESS_MAP_BPMP_SN_AST0_T_LIMIT 0x0d615fff
+#define NV_ADDRESS_MAP_BPMP_SN_AST0_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_SN_AST0_T_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_SN_AST1_T_BASE 0x0d616000
+#define NV_ADDRESS_MAP_BPMP_SN_AST1_T_LIMIT 0x0d616fff
+#define NV_ADDRESS_MAP_BPMP_SN_AST1_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_SN_AST1_T_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_SN_CBB_T_BASE 0x0d617000
+#define NV_ADDRESS_MAP_BPMP_SN_CBB_T_LIMIT 0x0d617fff
+#define NV_ADDRESS_MAP_BPMP_SN_CBB_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_SN_CBB_T_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_SN_CPU_T_BASE 0x0d618000
+#define NV_ADDRESS_MAP_BPMP_SN_CPU_T_LIMIT 0x0d618fff
+#define NV_ADDRESS_MAP_BPMP_SN_CPU_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_SN_CPU_T_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_EN_CFG_BASE 0x0d619000
+#define NV_ADDRESS_MAP_BPMP_EN_CFG_LIMIT 0x0d619fff
+#define NV_ADDRESS_MAP_BPMP_EN_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_EN_CFG_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_FABRIC_ERR_COLLATOR_BASE 0x0d620000
+#define NV_ADDRESS_MAP_BPMP_FABRIC_ERR_COLLATOR_LIMIT 0x0d620fff
+#define NV_ADDRESS_MAP_BPMP_FABRIC_ERR_COLLATOR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_FABRIC_ERR_COLLATOR_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_ERR_COLLATOR_BASE 0x0d650000
+#define NV_ADDRESS_MAP_BPMP_ERR_COLLATOR_LIMIT 0x0d65ffff
+#define NV_ADDRESS_MAP_BPMP_ERR_COLLATOR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_ERR_COLLATOR_HEADER arbpmp_error_collator.h;arbpmp_error_collator_scr.h
+
+#define NV_ADDRESS_MAP_BPMP_MISC_CFG_BASE 0x0d660000
+#define NV_ADDRESS_MAP_BPMP_MISC_CFG_LIMIT 0x0d66efff
+#define NV_ADDRESS_MAP_BPMP_MISC_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_MISC_CFG_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_SCPM_BASE 0x0d66f000
+#define NV_ADDRESS_MAP_BPMP_SCPM_LIMIT 0x0d66ffff
+#define NV_ADDRESS_MAP_BPMP_SCPM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_SCPM_HEADER
+
+#define NV_ADDRESS_MAP_DCE_ATCM_CFG_EVP_BASE 0x0d800000
+#define NV_ADDRESS_MAP_DCE_ATCM_CFG_EVP_LIMIT 0x0d80ffff
+#define NV_ADDRESS_MAP_DCE_ATCM_CFG_EVP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_ATCM_CFG_EVP_HEADER
+
+#define NV_ADDRESS_MAP_DCE_VIC_0_BASE 0x0d820000
+#define NV_ADDRESS_MAP_DCE_VIC_0_LIMIT 0x0d82ffff
+#define NV_ADDRESS_MAP_DCE_VIC_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_VIC_0_HEADER araps_vic.h
+
+#define NV_ADDRESS_MAP_DCE_VIC_1_BASE 0x0d830000
+#define NV_ADDRESS_MAP_DCE_VIC_1_LIMIT 0x0d83ffff
+#define NV_ADDRESS_MAP_DCE_VIC_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_VIC_1_HEADER araps_vic.h
+
+#define NV_ADDRESS_MAP_DCE_AST_0_BASE 0x0d840000
+#define NV_ADDRESS_MAP_DCE_AST_0_LIMIT 0x0d84ffff
+#define NV_ADDRESS_MAP_DCE_AST_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_AST_0_HEADER araps_ast.h;araps_ast_scr.h
+
+#define NV_ADDRESS_MAP_DCE_AST_1_BASE 0x0d850000
+#define NV_ADDRESS_MAP_DCE_AST_1_LIMIT 0x0d85ffff
+#define NV_ADDRESS_MAP_DCE_AST_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_AST_1_HEADER araps_ast.h;araps_ast_scr.h
+
+#define NV_ADDRESS_MAP_DCE_DMA_COMMON_BASE 0x0d860000
+#define NV_ADDRESS_MAP_DCE_DMA_COMMON_LIMIT 0x0d86ffff
+#define NV_ADDRESS_MAP_DCE_DMA_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_DMA_COMMON_HEADER
+
+#define NV_ADDRESS_MAP_DCE_DMA_CH_0_BASE 0x0d870000
+#define NV_ADDRESS_MAP_DCE_DMA_CH_0_LIMIT 0x0d87ffff
+#define NV_ADDRESS_MAP_DCE_DMA_CH_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_DMA_CH_0_HEADER
+
+#define NV_ADDRESS_MAP_DCE_DMA_CH_1_BASE 0x0d880000
+#define NV_ADDRESS_MAP_DCE_DMA_CH_1_LIMIT 0x0d88ffff
+#define NV_ADDRESS_MAP_DCE_DMA_CH_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_DMA_CH_1_HEADER
+
+#define NV_ADDRESS_MAP_DCE_DMA_CH_2_BASE 0x0d890000
+#define NV_ADDRESS_MAP_DCE_DMA_CH_2_LIMIT 0x0d89ffff
+#define NV_ADDRESS_MAP_DCE_DMA_CH_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_DMA_CH_2_HEADER
+
+#define NV_ADDRESS_MAP_DCE_DMA_CH_3_BASE 0x0d8a0000
+#define NV_ADDRESS_MAP_DCE_DMA_CH_3_LIMIT 0x0d8affff
+#define NV_ADDRESS_MAP_DCE_DMA_CH_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_DMA_CH_3_HEADER
+
+#define NV_ADDRESS_MAP_DCE_DMA_CH_4_BASE 0x0d8b0000
+#define NV_ADDRESS_MAP_DCE_DMA_CH_4_LIMIT 0x0d8bffff
+#define NV_ADDRESS_MAP_DCE_DMA_CH_4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_DMA_CH_4_HEADER
+
+#define NV_ADDRESS_MAP_DCE_DMA_CH_5_BASE 0x0d8c0000
+#define NV_ADDRESS_MAP_DCE_DMA_CH_5_LIMIT 0x0d8cffff
+#define NV_ADDRESS_MAP_DCE_DMA_CH_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_DMA_CH_5_HEADER
+
+#define NV_ADDRESS_MAP_DCE_DMA_CH_6_BASE 0x0d8d0000
+#define NV_ADDRESS_MAP_DCE_DMA_CH_6_LIMIT 0x0d8dffff
+#define NV_ADDRESS_MAP_DCE_DMA_CH_6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_DMA_CH_6_HEADER
+
+#define NV_ADDRESS_MAP_DCE_DMA_CH_7_BASE 0x0d8e0000
+#define NV_ADDRESS_MAP_DCE_DMA_CH_7_LIMIT 0x0d8effff
+#define NV_ADDRESS_MAP_DCE_DMA_CH_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_DMA_CH_7_HEADER
+
+#define NV_ADDRESS_MAP_DCE_TKE_SHARED_BASE 0x0d8f0000
+#define NV_ADDRESS_MAP_DCE_TKE_SHARED_LIMIT 0x0d8fffff
+#define NV_ADDRESS_MAP_DCE_TKE_SHARED_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_TKE_SHARED_HEADER
+
+#define NV_ADDRESS_MAP_DCE_TKE_TMR_0_BASE 0x0d900000
+#define NV_ADDRESS_MAP_DCE_TKE_TMR_0_LIMIT 0x0d90ffff
+#define NV_ADDRESS_MAP_DCE_TKE_TMR_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_TKE_TMR_0_HEADER
+
+#define NV_ADDRESS_MAP_DCE_TKE_TMR_1_BASE 0x0d910000
+#define NV_ADDRESS_MAP_DCE_TKE_TMR_1_LIMIT 0x0d91ffff
+#define NV_ADDRESS_MAP_DCE_TKE_TMR_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_TKE_TMR_1_HEADER
+
+#define NV_ADDRESS_MAP_DCE_TKE_TMR_2_BASE 0x0d920000
+#define NV_ADDRESS_MAP_DCE_TKE_TMR_2_LIMIT 0x0d92ffff
+#define NV_ADDRESS_MAP_DCE_TKE_TMR_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_TKE_TMR_2_HEADER
+
+#define NV_ADDRESS_MAP_DCE_TKE_TMR_3_BASE 0x0d930000
+#define NV_ADDRESS_MAP_DCE_TKE_TMR_3_LIMIT 0x0d93ffff
+#define NV_ADDRESS_MAP_DCE_TKE_TMR_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_TKE_TMR_3_HEADER
+
+#define NV_ADDRESS_MAP_DCE_TKE_WDT_0_BASE 0x0d940000
+#define NV_ADDRESS_MAP_DCE_TKE_WDT_0_LIMIT 0x0d94ffff
+#define NV_ADDRESS_MAP_DCE_TKE_WDT_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_TKE_WDT_0_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP_COMMON_BASE 0x0d950000
+#define NV_ADDRESS_MAP_DCE_HSP_COMMON_LIMIT 0x0d95ffff
+#define NV_ADDRESS_MAP_DCE_HSP_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP_COMMON_HEADER arhsp_int.h;arhsp_int_scr.h
+
+#define NV_ADDRESS_MAP_DCE_HSP_SM_0_1_BASE 0x0d960000
+#define NV_ADDRESS_MAP_DCE_HSP_SM_0_1_LIMIT 0x0d96ffff
+#define NV_ADDRESS_MAP_DCE_HSP_SM_0_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP_SM_0_1_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP_SM_2_3_BASE 0x0d970000
+#define NV_ADDRESS_MAP_DCE_HSP_SM_2_3_LIMIT 0x0d97ffff
+#define NV_ADDRESS_MAP_DCE_HSP_SM_2_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP_SM_2_3_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP_SM_4_5_BASE 0x0d980000
+#define NV_ADDRESS_MAP_DCE_HSP_SM_4_5_LIMIT 0x0d98ffff
+#define NV_ADDRESS_MAP_DCE_HSP_SM_4_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP_SM_4_5_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP_SM_6_7_BASE 0x0d990000
+#define NV_ADDRESS_MAP_DCE_HSP_SM_6_7_LIMIT 0x0d99ffff
+#define NV_ADDRESS_MAP_DCE_HSP_SM_6_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP_SM_6_7_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP_SS_0_BASE 0x0d9a0000
+#define NV_ADDRESS_MAP_DCE_HSP_SS_0_LIMIT 0x0d9affff
+#define NV_ADDRESS_MAP_DCE_HSP_SS_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP_SS_0_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP_SS_1_BASE 0x0d9b0000
+#define NV_ADDRESS_MAP_DCE_HSP_SS_1_LIMIT 0x0d9bffff
+#define NV_ADDRESS_MAP_DCE_HSP_SS_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP_SS_1_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP_SS_2_BASE 0x0d9c0000
+#define NV_ADDRESS_MAP_DCE_HSP_SS_2_LIMIT 0x0d9cffff
+#define NV_ADDRESS_MAP_DCE_HSP_SS_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP_SS_2_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP_SS_3_BASE 0x0d9d0000
+#define NV_ADDRESS_MAP_DCE_HSP_SS_3_LIMIT 0x0d9dffff
+#define NV_ADDRESS_MAP_DCE_HSP_SS_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP_SS_3_HEADER
+
+#define NV_ADDRESS_MAP_DCE_GTE_BASE 0x0d9e0000
+#define NV_ADDRESS_MAP_DCE_GTE_LIMIT 0x0d9effff
+#define NV_ADDRESS_MAP_DCE_GTE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_GTE_HEADER argte_aps.h;argte_aps_scr.h
+
+#define NV_ADDRESS_MAP_DCE_PM_IMPL_BASE 0x0d9f0000
+#define NV_ADDRESS_MAP_DCE_PM_IMPL_LIMIT 0x0d9fffff
+#define NV_ADDRESS_MAP_DCE_PM_IMPL_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_PM_IMPL_HEADER arscepm.h;arscepm_scr.h
+
+#define NV_ADDRESS_MAP_DCE_ACTMON_BASE 0x0da00000
+#define NV_ADDRESS_MAP_DCE_ACTMON_LIMIT 0x0da0ffff
+#define NV_ADDRESS_MAP_DCE_ACTMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_ACTMON_HEADER arunit_actmon.h
+
+#define NV_ADDRESS_MAP_DCE_CFG_BASE 0x0da30000
+#define NV_ADDRESS_MAP_DCE_CFG_LIMIT 0x0da3ffff
+#define NV_ADDRESS_MAP_DCE_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_CFG_HEADER araps_proc_cfg.h
+
+#define NV_ADDRESS_MAP_DCE_HSM_BASE 0x0da40000
+#define NV_ADDRESS_MAP_DCE_HSM_LIMIT 0x0da4ffff
+#define NV_ADDRESS_MAP_DCE_HSM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSM_HEADER arsce_hsm.h
+
+#define NV_ADDRESS_MAP_DCE_ATCM_EVP_EXT_BASE 0x0dc00000
+#define NV_ADDRESS_MAP_DCE_ATCM_EVP_EXT_LIMIT 0x0dc0ffff
+#define NV_ADDRESS_MAP_DCE_ATCM_EVP_EXT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_ATCM_EVP_EXT_HEADER ardce_evp.h
+
+#define NV_ADDRESS_MAP_DCE_BTCM_BASE 0x0dc80000
+#define NV_ADDRESS_MAP_DCE_BTCM_LIMIT 0x0dcdffff
+#define NV_ADDRESS_MAP_DCE_BTCM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_BTCM_HEADER no_headers
+
+#define NV_ADDRESS_MAP_DCE_ICACHE_ACCESS_PORT_BASE 0x0dd00000
+#define NV_ADDRESS_MAP_DCE_ICACHE_ACCESS_PORT_LIMIT 0x0dd7ffff
+#define NV_ADDRESS_MAP_DCE_ICACHE_ACCESS_PORT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_ICACHE_ACCESS_PORT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_DCE_DCACHE_ACCESS_PORT_BASE 0x0dd80000
+#define NV_ADDRESS_MAP_DCE_DCACHE_ACCESS_PORT_LIMIT 0x0ddfffff
+#define NV_ADDRESS_MAP_DCE_DCACHE_ACCESS_PORT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_DCACHE_ACCESS_PORT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_DCE_SN_AXI2APB_1_BASE 0x0de00000
+#define NV_ADDRESS_MAP_DCE_SN_AXI2APB_1_LIMIT 0x0de00fff
+#define NV_ADDRESS_MAP_DCE_SN_AXI2APB_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_SN_AXI2APB_1_HEADER
+
+#define NV_ADDRESS_MAP_DCE_MN_CPU_M_I_BASE 0x0de10000
+#define NV_ADDRESS_MAP_DCE_MN_CPU_M_I_LIMIT 0x0de10fff
+#define NV_ADDRESS_MAP_DCE_MN_CPU_M_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_MN_CPU_M_I_HEADER
+
+#define NV_ADDRESS_MAP_DCE_MN_CBB_I_BASE 0x0de11000
+#define NV_ADDRESS_MAP_DCE_MN_CBB_I_LIMIT 0x0de11fff
+#define NV_ADDRESS_MAP_DCE_MN_CBB_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_MN_CBB_I_HEADER
+
+#define NV_ADDRESS_MAP_DCE_MN_CPU_P_I_BASE 0x0de12000
+#define NV_ADDRESS_MAP_DCE_MN_CPU_P_I_LIMIT 0x0de12fff
+#define NV_ADDRESS_MAP_DCE_MN_CPU_P_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_MN_CPU_P_I_HEADER
+
+#define NV_ADDRESS_MAP_DCE_MN_DMA_M_I_BASE 0x0de13000
+#define NV_ADDRESS_MAP_DCE_MN_DMA_M_I_LIMIT 0x0de13fff
+#define NV_ADDRESS_MAP_DCE_MN_DMA_M_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_MN_DMA_M_I_HEADER
+
+#define NV_ADDRESS_MAP_DCE_MN_DMA_P_I_BASE 0x0de14000
+#define NV_ADDRESS_MAP_DCE_MN_DMA_P_I_LIMIT 0x0de14fff
+#define NV_ADDRESS_MAP_DCE_MN_DMA_P_I_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_MN_DMA_P_I_HEADER
+
+#define NV_ADDRESS_MAP_DCE_SN_AST0_T_BASE 0x0de15000
+#define NV_ADDRESS_MAP_DCE_SN_AST0_T_LIMIT 0x0de15fff
+#define NV_ADDRESS_MAP_DCE_SN_AST0_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_SN_AST0_T_HEADER
+
+#define NV_ADDRESS_MAP_DCE_SN_AST1_T_BASE 0x0de16000
+#define NV_ADDRESS_MAP_DCE_SN_AST1_T_LIMIT 0x0de16fff
+#define NV_ADDRESS_MAP_DCE_SN_AST1_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_SN_AST1_T_HEADER
+
+#define NV_ADDRESS_MAP_DCE_SN_CBB_T_BASE 0x0de17000
+#define NV_ADDRESS_MAP_DCE_SN_CBB_T_LIMIT 0x0de17fff
+#define NV_ADDRESS_MAP_DCE_SN_CBB_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_SN_CBB_T_HEADER
+
+#define NV_ADDRESS_MAP_DCE_SN_CPU_T_BASE 0x0de18000
+#define NV_ADDRESS_MAP_DCE_SN_CPU_T_LIMIT 0x0de18fff
+#define NV_ADDRESS_MAP_DCE_SN_CPU_T_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_SN_CPU_T_HEADER
+
+#define NV_ADDRESS_MAP_DCE_EN_CFG_BASE 0x0de19000
+#define NV_ADDRESS_MAP_DCE_EN_CFG_LIMIT 0x0de19fff
+#define NV_ADDRESS_MAP_DCE_EN_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_EN_CFG_HEADER
+
+#define NV_ADDRESS_MAP_DCE_FABRIC_ERR_COLLATOR_BASE 0x0de20000
+#define NV_ADDRESS_MAP_DCE_FABRIC_ERR_COLLATOR_LIMIT 0x0de20fff
+#define NV_ADDRESS_MAP_DCE_FABRIC_ERR_COLLATOR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_FABRIC_ERR_COLLATOR_HEADER
+
+#define NV_ADDRESS_MAP_DCE_ERR_COLLATOR_BASE 0x0de50000
+#define NV_ADDRESS_MAP_DCE_ERR_COLLATOR_LIMIT 0x0de5ffff
+#define NV_ADDRESS_MAP_DCE_ERR_COLLATOR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_ERR_COLLATOR_HEADER arsce_ec.h;arsce_ec_scr.h
+
+#define NV_ADDRESS_MAP_DCE_MISC_BASE 0x0de60000
+#define NV_ADDRESS_MAP_DCE_MISC_LIMIT 0x0de6ffff
+#define NV_ADDRESS_MAP_DCE_MISC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_MISC_HEADER arsce_misc.h;arsce_misc_scr.h
+
+#define NV_ADDRESS_MAP_DCE_HSP1_COMMON_BASE 0x0de70000
+#define NV_ADDRESS_MAP_DCE_HSP1_COMMON_LIMIT 0x0de7ffff
+#define NV_ADDRESS_MAP_DCE_HSP1_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP1_COMMON_HEADER arhsp_int.h;arhsp_int_scr.h
+
+#define NV_ADDRESS_MAP_DCE_HSP1_SM_0_1_BASE 0x0de80000
+#define NV_ADDRESS_MAP_DCE_HSP1_SM_0_1_LIMIT 0x0de8ffff
+#define NV_ADDRESS_MAP_DCE_HSP1_SM_0_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP1_SM_0_1_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP1_SM_2_3_BASE 0x0de90000
+#define NV_ADDRESS_MAP_DCE_HSP1_SM_2_3_LIMIT 0x0de9ffff
+#define NV_ADDRESS_MAP_DCE_HSP1_SM_2_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP1_SM_2_3_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP1_SM_4_5_BASE 0x0dea0000
+#define NV_ADDRESS_MAP_DCE_HSP1_SM_4_5_LIMIT 0x0deaffff
+#define NV_ADDRESS_MAP_DCE_HSP1_SM_4_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP1_SM_4_5_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP1_SM_6_7_BASE 0x0deb0000
+#define NV_ADDRESS_MAP_DCE_HSP1_SM_6_7_LIMIT 0x0debffff
+#define NV_ADDRESS_MAP_DCE_HSP1_SM_6_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP1_SM_6_7_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP1_SS_0_BASE 0x0dec0000
+#define NV_ADDRESS_MAP_DCE_HSP1_SS_0_LIMIT 0x0decffff
+#define NV_ADDRESS_MAP_DCE_HSP1_SS_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP1_SS_0_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP1_SS_1_BASE 0x0ded0000
+#define NV_ADDRESS_MAP_DCE_HSP1_SS_1_LIMIT 0x0dedffff
+#define NV_ADDRESS_MAP_DCE_HSP1_SS_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP1_SS_1_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP1_SS_2_BASE 0x0dee0000
+#define NV_ADDRESS_MAP_DCE_HSP1_SS_2_LIMIT 0x0deeffff
+#define NV_ADDRESS_MAP_DCE_HSP1_SS_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP1_SS_2_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP1_SS_3_BASE 0x0def0000
+#define NV_ADDRESS_MAP_DCE_HSP1_SS_3_LIMIT 0x0defffff
+#define NV_ADDRESS_MAP_DCE_HSP1_SS_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP1_SS_3_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP2_COMMON_BASE 0x0df00000
+#define NV_ADDRESS_MAP_DCE_HSP2_COMMON_LIMIT 0x0df0ffff
+#define NV_ADDRESS_MAP_DCE_HSP2_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP2_COMMON_HEADER arhsp_int.h;arhsp_int_scr.h
+
+#define NV_ADDRESS_MAP_DCE_HSP2_SM_0_1_BASE 0x0df10000
+#define NV_ADDRESS_MAP_DCE_HSP2_SM_0_1_LIMIT 0x0df1ffff
+#define NV_ADDRESS_MAP_DCE_HSP2_SM_0_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP2_SM_0_1_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP2_SM_2_3_BASE 0x0df20000
+#define NV_ADDRESS_MAP_DCE_HSP2_SM_2_3_LIMIT 0x0df2ffff
+#define NV_ADDRESS_MAP_DCE_HSP2_SM_2_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP2_SM_2_3_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP2_SM_4_5_BASE 0x0df30000
+#define NV_ADDRESS_MAP_DCE_HSP2_SM_4_5_LIMIT 0x0df3ffff
+#define NV_ADDRESS_MAP_DCE_HSP2_SM_4_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP2_SM_4_5_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP2_SM_6_7_BASE 0x0df40000
+#define NV_ADDRESS_MAP_DCE_HSP2_SM_6_7_LIMIT 0x0df4ffff
+#define NV_ADDRESS_MAP_DCE_HSP2_SM_6_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP2_SM_6_7_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP2_SS_0_BASE 0x0df50000
+#define NV_ADDRESS_MAP_DCE_HSP2_SS_0_LIMIT 0x0df5ffff
+#define NV_ADDRESS_MAP_DCE_HSP2_SS_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP2_SS_0_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP2_SS_1_BASE 0x0df60000
+#define NV_ADDRESS_MAP_DCE_HSP2_SS_1_LIMIT 0x0df6ffff
+#define NV_ADDRESS_MAP_DCE_HSP2_SS_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP2_SS_1_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP2_SS_2_BASE 0x0df70000
+#define NV_ADDRESS_MAP_DCE_HSP2_SS_2_LIMIT 0x0df7ffff
+#define NV_ADDRESS_MAP_DCE_HSP2_SS_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP2_SS_2_HEADER
+
+#define NV_ADDRESS_MAP_DCE_HSP2_SS_3_BASE 0x0df80000
+#define NV_ADDRESS_MAP_DCE_HSP2_SS_3_LIMIT 0x0df8ffff
+#define NV_ADDRESS_MAP_DCE_HSP2_SS_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DCE_HSP2_SS_3_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_MMCRAB_ARM_BASE 0x0e000000
+#define NV_ADDRESS_MAP_CCPLEX_MMCRAB_ARM_LIMIT 0x0e3fffff
+#define NV_ADDRESS_MAP_CCPLEX_MMCRAB_ARM_ADDR_LOCALITY CCPLEX
+#define NV_ADDRESS_MAP_CCPLEX_MMCRAB_ARM_HEADER no_headers
+
+#define NV_ADDRESS_MAP_AXIS_NIC_0_BASE 0x0f000000
+#define NV_ADDRESS_MAP_AXIS_NIC_0_LIMIT 0x0f0fffff
+#define NV_ADDRESS_MAP_AXIS_NIC_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AXIS_NIC_0_HEADER no_headers
+
+#define NV_ADDRESS_MAP_RPG_PM_VI0_BASE 0x0f100000
+#define NV_ADDRESS_MAP_RPG_PM_VI0_LIMIT 0x0f100fff
+#define NV_ADDRESS_MAP_RPG_PM_VI0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_VI0_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_VI1_BASE 0x0f101000
+#define NV_ADDRESS_MAP_RPG_PM_VI1_LIMIT 0x0f101fff
+#define NV_ADDRESS_MAP_RPG_PM_VI1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_VI1_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_ISP0_BASE 0x0f102000
+#define NV_ADDRESS_MAP_RPG_PM_ISP0_LIMIT 0x0f102fff
+#define NV_ADDRESS_MAP_RPG_PM_ISP0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_ISP0_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_VIC_BASE 0x0f103000
+#define NV_ADDRESS_MAP_RPG_PM_VIC_LIMIT 0x0f103fff
+#define NV_ADDRESS_MAP_RPG_PM_VIC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_VIC_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_PVA0_0_BASE 0x0f105000
+#define NV_ADDRESS_MAP_RPG_PM_PVA0_0_LIMIT 0x0f105fff
+#define NV_ADDRESS_MAP_RPG_PM_PVA0_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_PVA0_0_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_PVA0_1_BASE 0x0f106000
+#define NV_ADDRESS_MAP_RPG_PM_PVA0_1_LIMIT 0x0f106fff
+#define NV_ADDRESS_MAP_RPG_PM_PVA0_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_PVA0_1_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_PVA0_2_BASE 0x0f107000
+#define NV_ADDRESS_MAP_RPG_PM_PVA0_2_LIMIT 0x0f107fff
+#define NV_ADDRESS_MAP_RPG_PM_PVA0_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_PVA0_2_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_NVDLA0_BASE 0x0f108000
+#define NV_ADDRESS_MAP_RPG_PM_NVDLA0_LIMIT 0x0f108fff
+#define NV_ADDRESS_MAP_RPG_PM_NVDLA0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_NVDLA0_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_NVDLA1_BASE 0x0f109000
+#define NV_ADDRESS_MAP_RPG_PM_NVDLA1_LIMIT 0x0f109fff
+#define NV_ADDRESS_MAP_RPG_PM_NVDLA1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_NVDLA1_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_DISPLAY_BASE 0x0f10a000
+#define NV_ADDRESS_MAP_RPG_PM_DISPLAY_LIMIT 0x0f10afff
+#define NV_ADDRESS_MAP_RPG_PM_DISPLAY_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_DISPLAY_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_PMA_BASE 0x0f10b000
+#define NV_ADDRESS_MAP_RPG_PM_PMA_LIMIT 0x0f10bfff
+#define NV_ADDRESS_MAP_RPG_PM_PMA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_PMA_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MGBE0_BASE 0x0f10c000
+#define NV_ADDRESS_MAP_RPG_PM_MGBE0_LIMIT 0x0f10cfff
+#define NV_ADDRESS_MAP_RPG_PM_MGBE0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MGBE0_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MGBE1_BASE 0x0f10d000
+#define NV_ADDRESS_MAP_RPG_PM_MGBE1_LIMIT 0x0f10dfff
+#define NV_ADDRESS_MAP_RPG_PM_MGBE1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MGBE1_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MGBE2_BASE 0x0f10e000
+#define NV_ADDRESS_MAP_RPG_PM_MGBE2_LIMIT 0x0f10efff
+#define NV_ADDRESS_MAP_RPG_PM_MGBE2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MGBE2_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MGBE3_BASE 0x0f10f000
+#define NV_ADDRESS_MAP_RPG_PM_MGBE3_LIMIT 0x0f10ffff
+#define NV_ADDRESS_MAP_RPG_PM_MGBE3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MGBE3_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_SCF_BASE 0x0f110000
+#define NV_ADDRESS_MAP_RPG_PM_SCF_LIMIT 0x0f110fff
+#define NV_ADDRESS_MAP_RPG_PM_SCF_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_SCF_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_NVDEC0_BASE 0x0f111000
+#define NV_ADDRESS_MAP_RPG_PM_NVDEC0_LIMIT 0x0f111fff
+#define NV_ADDRESS_MAP_RPG_PM_NVDEC0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_NVDEC0_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_NVENC0_BASE 0x0f112000
+#define NV_ADDRESS_MAP_RPG_PM_NVENC0_LIMIT 0x0f112fff
+#define NV_ADDRESS_MAP_RPG_PM_NVENC0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_NVENC0_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSSNVL_BASE 0x0f113000
+#define NV_ADDRESS_MAP_RPG_PM_MSSNVL_LIMIT 0x0f113fff
+#define NV_ADDRESS_MAP_RPG_PM_MSSNVL_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSSNVL_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C0_BASE 0x0f114000
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C0_LIMIT 0x0f114fff
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C0_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C1_BASE 0x0f115000
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C1_LIMIT 0x0f115fff
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C1_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C2_BASE 0x0f116000
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C2_LIMIT 0x0f116fff
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C2_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C3_BASE 0x0f117000
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C3_LIMIT 0x0f117fff
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C3_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C4_BASE 0x0f118000
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C4_LIMIT 0x0f118fff
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C4_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C5_BASE 0x0f119000
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C5_LIMIT 0x0f119fff
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C5_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C6_BASE 0x0f11a000
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C6_LIMIT 0x0f11afff
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C6_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C7_BASE 0x0f11b000
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C7_LIMIT 0x0f11bfff
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C7_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C8_BASE 0x0f11c000
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C8_LIMIT 0x0f11cfff
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C8_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C8_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C9_BASE 0x0f11d000
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C9_LIMIT 0x0f11dfff
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C9_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C9_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C10_BASE 0x0f11e000
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C10_LIMIT 0x0f11efff
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C10_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_PCIE_C10_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSS0_BASE 0x0f11f000
+#define NV_ADDRESS_MAP_RPG_PM_MSS0_LIMIT 0x0f11ffff
+#define NV_ADDRESS_MAP_RPG_PM_MSS0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSS0_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSS1_BASE 0x0f120000
+#define NV_ADDRESS_MAP_RPG_PM_MSS1_LIMIT 0x0f120fff
+#define NV_ADDRESS_MAP_RPG_PM_MSS1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSS1_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSS2_BASE 0x0f121000
+#define NV_ADDRESS_MAP_RPG_PM_MSS2_LIMIT 0x0f121fff
+#define NV_ADDRESS_MAP_RPG_PM_MSS2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSS2_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSS3_BASE 0x0f122000
+#define NV_ADDRESS_MAP_RPG_PM_MSS3_LIMIT 0x0f122fff
+#define NV_ADDRESS_MAP_RPG_PM_MSS3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSS3_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSS4_BASE 0x0f123000
+#define NV_ADDRESS_MAP_RPG_PM_MSS4_LIMIT 0x0f123fff
+#define NV_ADDRESS_MAP_RPG_PM_MSS4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSS4_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSS5_BASE 0x0f124000
+#define NV_ADDRESS_MAP_RPG_PM_MSS5_LIMIT 0x0f124fff
+#define NV_ADDRESS_MAP_RPG_PM_MSS5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSS5_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSS6_BASE 0x0f125000
+#define NV_ADDRESS_MAP_RPG_PM_MSS6_LIMIT 0x0f125fff
+#define NV_ADDRESS_MAP_RPG_PM_MSS6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSS6_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSS7_BASE 0x0f126000
+#define NV_ADDRESS_MAP_RPG_PM_MSS7_LIMIT 0x0f126fff
+#define NV_ADDRESS_MAP_RPG_PM_MSS7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSS7_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSS8_BASE 0x0f127000
+#define NV_ADDRESS_MAP_RPG_PM_MSS8_LIMIT 0x0f127fff
+#define NV_ADDRESS_MAP_RPG_PM_MSS8_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSS8_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSS9_BASE 0x0f128000
+#define NV_ADDRESS_MAP_RPG_PM_MSS9_LIMIT 0x0f128fff
+#define NV_ADDRESS_MAP_RPG_PM_MSS9_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSS9_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSS10_BASE 0x0f129000
+#define NV_ADDRESS_MAP_RPG_PM_MSS10_LIMIT 0x0f129fff
+#define NV_ADDRESS_MAP_RPG_PM_MSS10_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSS10_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSS11_BASE 0x0f12a000
+#define NV_ADDRESS_MAP_RPG_PM_MSS11_LIMIT 0x0f12afff
+#define NV_ADDRESS_MAP_RPG_PM_MSS11_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSS11_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSS12_BASE 0x0f12b000
+#define NV_ADDRESS_MAP_RPG_PM_MSS12_LIMIT 0x0f12bfff
+#define NV_ADDRESS_MAP_RPG_PM_MSS12_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSS12_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSS13_BASE 0x0f12c000
+#define NV_ADDRESS_MAP_RPG_PM_MSS13_LIMIT 0x0f12cfff
+#define NV_ADDRESS_MAP_RPG_PM_MSS13_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSS13_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSS14_BASE 0x0f12d000
+#define NV_ADDRESS_MAP_RPG_PM_MSS14_LIMIT 0x0f12dfff
+#define NV_ADDRESS_MAP_RPG_PM_MSS14_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSS14_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSS15_BASE 0x0f12e000
+#define NV_ADDRESS_MAP_RPG_PM_MSS15_LIMIT 0x0f12efff
+#define NV_ADDRESS_MAP_RPG_PM_MSS15_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSS15_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSSHUB0_BASE 0x0f12f000
+#define NV_ADDRESS_MAP_RPG_PM_MSSHUB0_LIMIT 0x0f12ffff
+#define NV_ADDRESS_MAP_RPG_PM_MSSHUB0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSSHUB0_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MSSHUB1_BASE 0x0f130000
+#define NV_ADDRESS_MAP_RPG_PM_MSSHUB1_LIMIT 0x0f130fff
+#define NV_ADDRESS_MAP_RPG_PM_MSSHUB1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MSSHUB1_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MCF0_BASE 0x0f131000
+#define NV_ADDRESS_MAP_RPG_PM_MCF0_LIMIT 0x0f131fff
+#define NV_ADDRESS_MAP_RPG_PM_MCF0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MCF0_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MCF1_BASE 0x0f132000
+#define NV_ADDRESS_MAP_RPG_PM_MCF1_LIMIT 0x0f132fff
+#define NV_ADDRESS_MAP_RPG_PM_MCF1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MCF1_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_RPG_PM_MCF2_BASE 0x0f133000
+#define NV_ADDRESS_MAP_RPG_PM_MCF2_LIMIT 0x0f133fff
+#define NV_ADDRESS_MAP_RPG_PM_MCF2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RPG_PM_MCF2_HEADER pri_perf_pmm_perfmon.h
+
+#define NV_ADDRESS_MAP_PMA_CFG_BASE 0x0f14a000
+#define NV_ADDRESS_MAP_PMA_CFG_LIMIT 0x0f14afff
+#define NV_ADDRESS_MAP_PMA_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PMA_CFG_HEADER
+
+#define NV_ADDRESS_MAP_RTR_BASE 0x0f14d000
+#define NV_ADDRESS_MAP_RTR_LIMIT 0x0f14dfff
+#define NV_ADDRESS_MAP_RTR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_RTR_HEADER pri_perf_pmm_rtr.h
+
+#define NV_ADDRESS_MAP_CCPLEX_GICD_BASE 0x0f400000
+#define NV_ADDRESS_MAP_CCPLEX_GICD_LIMIT 0x0f40ffff
+#define NV_ADDRESS_MAP_CCPLEX_GICD_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICD_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICA_BASE 0x0f410000
+#define NV_ADDRESS_MAP_CCPLEX_GICA_LIMIT 0x0f41ffff
+#define NV_ADDRESS_MAP_CCPLEX_GICA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICA_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICT_BASE 0x0f420000
+#define NV_ADDRESS_MAP_CCPLEX_GICT_LIMIT 0x0f42ffff
+#define NV_ADDRESS_MAP_CCPLEX_GICT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICT_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICP_BASE 0x0f430000
+#define NV_ADDRESS_MAP_CCPLEX_GICP_LIMIT 0x0f43ffff
+#define NV_ADDRESS_MAP_CCPLEX_GICP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICP_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICR0_BASE 0x0f440000
+#define NV_ADDRESS_MAP_CCPLEX_GICR0_LIMIT 0x0f45ffff
+#define NV_ADDRESS_MAP_CCPLEX_GICR0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICR0_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICR1_BASE 0x0f460000
+#define NV_ADDRESS_MAP_CCPLEX_GICR1_LIMIT 0x0f47ffff
+#define NV_ADDRESS_MAP_CCPLEX_GICR1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICR1_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICR2_BASE 0x0f480000
+#define NV_ADDRESS_MAP_CCPLEX_GICR2_LIMIT 0x0f49ffff
+#define NV_ADDRESS_MAP_CCPLEX_GICR2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICR2_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICR3_BASE 0x0f4a0000
+#define NV_ADDRESS_MAP_CCPLEX_GICR3_LIMIT 0x0f4bffff
+#define NV_ADDRESS_MAP_CCPLEX_GICR3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICR3_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICR4_BASE 0x0f4c0000
+#define NV_ADDRESS_MAP_CCPLEX_GICR4_LIMIT 0x0f4dffff
+#define NV_ADDRESS_MAP_CCPLEX_GICR4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICR4_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICR5_BASE 0x0f4e0000
+#define NV_ADDRESS_MAP_CCPLEX_GICR5_LIMIT 0x0f4fffff
+#define NV_ADDRESS_MAP_CCPLEX_GICR5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICR5_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICR6_BASE 0x0f500000
+#define NV_ADDRESS_MAP_CCPLEX_GICR6_LIMIT 0x0f51ffff
+#define NV_ADDRESS_MAP_CCPLEX_GICR6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICR6_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICR7_BASE 0x0f520000
+#define NV_ADDRESS_MAP_CCPLEX_GICR7_LIMIT 0x0f53ffff
+#define NV_ADDRESS_MAP_CCPLEX_GICR7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICR7_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICR8_BASE 0x0f540000
+#define NV_ADDRESS_MAP_CCPLEX_GICR8_LIMIT 0x0f55ffff
+#define NV_ADDRESS_MAP_CCPLEX_GICR8_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICR8_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICR9_BASE 0x0f560000
+#define NV_ADDRESS_MAP_CCPLEX_GICR9_LIMIT 0x0f57ffff
+#define NV_ADDRESS_MAP_CCPLEX_GICR9_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICR9_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICR10_BASE 0x0f580000
+#define NV_ADDRESS_MAP_CCPLEX_GICR10_LIMIT 0x0f59ffff
+#define NV_ADDRESS_MAP_CCPLEX_GICR10_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICR10_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICR11_BASE 0x0f5a0000
+#define NV_ADDRESS_MAP_CCPLEX_GICR11_LIMIT 0x0f5bffff
+#define NV_ADDRESS_MAP_CCPLEX_GICR11_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICR11_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICR12_BASE 0x0f5c0000
+#define NV_ADDRESS_MAP_CCPLEX_GICR12_LIMIT 0x0f5dffff
+#define NV_ADDRESS_MAP_CCPLEX_GICR12_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICR12_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICR13_BASE 0x0f5e0000
+#define NV_ADDRESS_MAP_CCPLEX_GICR13_LIMIT 0x0f5fffff
+#define NV_ADDRESS_MAP_CCPLEX_GICR13_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICR13_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICR14_BASE 0x0f600000
+#define NV_ADDRESS_MAP_CCPLEX_GICR14_LIMIT 0x0f61ffff
+#define NV_ADDRESS_MAP_CCPLEX_GICR14_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICR14_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICR15_BASE 0x0f620000
+#define NV_ADDRESS_MAP_CCPLEX_GICR15_LIMIT 0x0f63ffff
+#define NV_ADDRESS_MAP_CCPLEX_GICR15_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICR15_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICDA_BASE 0x0f640000
+#define NV_ADDRESS_MAP_CCPLEX_GICDA_LIMIT 0x0f64ffff
+#define NV_ADDRESS_MAP_CCPLEX_GICDA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICDA_HEADER
+
+#define NV_ADDRESS_MAP_CCPLEX_GICFMU_BASE 0x0f7f0000
+#define NV_ADDRESS_MAP_CCPLEX_GICFMU_LIMIT 0x0f7fffff
+#define NV_ADDRESS_MAP_CCPLEX_GICFMU_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CCPLEX_GICFMU_HEADER
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_GR0_BASE 0x10000000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_GR0_LIMIT 0x1000ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_GR0_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_GR0_HEADER arm_smmu_500_global.h;arm_smmu_500_global_sec.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_GR0_BASE 0x10000000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_GR0_LIMIT 0x10000fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_GR0_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_GR0_HEADER arm_smmu_500_global.h;arm_smmu_500_global_sec.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_GR1_BASE 0x10001000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_GR1_LIMIT 0x10001fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_GR1_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_GR1_HEADER arm_smmu_500_global_1.h;arm_smmu_500_global_sec_1.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_GID_BASE 0x10002000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_GID_LIMIT 0x10002fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_GID_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_GID_HEADER arm_smmu_500_integ_sec.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_PM_BASE 0x10003000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_PM_LIMIT 0x10003fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_PM_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_PM_HEADER arm_smmu_500_perf_mon.h;arm_smmu_500_perf_mon_sec.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_GR1_BASE 0x10010000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_GR1_LIMIT 0x1001ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_GR1_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_GR1_HEADER arm_smmu_500_global_1.h;arm_smmu_500_global_sec_1.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_GID_BASE 0x10020000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_GID_LIMIT 0x1002ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_GID_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_GID_HEADER arm_smmu_500_integ_sec.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_PM_BASE 0x10030000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_PM_LIMIT 0x1003ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_PM_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_PM_HEADER arm_smmu_500_perf_mon.h;arm_smmu_500_perf_mon_sec.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB0_BASE 0x10080000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB0_LIMIT 0x10080fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB0_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB0_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB1_BASE 0x10081000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB1_LIMIT 0x10081fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB1_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB1_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB2_BASE 0x10082000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB2_LIMIT 0x10082fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB2_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB2_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB3_BASE 0x10083000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB3_LIMIT 0x10083fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB3_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB3_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB4_BASE 0x10084000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB4_LIMIT 0x10084fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB4_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB4_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB5_BASE 0x10085000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB5_LIMIT 0x10085fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB5_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB5_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB6_BASE 0x10086000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB6_LIMIT 0x10086fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB6_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB6_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB7_BASE 0x10087000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB7_LIMIT 0x10087fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB7_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB7_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB8_BASE 0x10088000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB8_LIMIT 0x10088fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB8_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB8_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB9_BASE 0x10089000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB9_LIMIT 0x10089fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB9_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB9_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB10_BASE 0x1008a000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB10_LIMIT 0x1008afff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB10_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB10_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB11_BASE 0x1008b000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB11_LIMIT 0x1008bfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB11_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB11_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB12_BASE 0x1008c000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB12_LIMIT 0x1008cfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB12_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB12_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB13_BASE 0x1008d000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB13_LIMIT 0x1008dfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB13_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB13_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB14_BASE 0x1008e000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB14_LIMIT 0x1008efff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB14_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB14_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB15_BASE 0x1008f000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB15_LIMIT 0x1008ffff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB15_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB15_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB16_BASE 0x10090000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB16_LIMIT 0x10090fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB16_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB16_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB17_BASE 0x10091000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB17_LIMIT 0x10091fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB17_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB17_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB18_BASE 0x10092000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB18_LIMIT 0x10092fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB18_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB18_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB19_BASE 0x10093000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB19_LIMIT 0x10093fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB19_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB19_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB20_BASE 0x10094000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB20_LIMIT 0x10094fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB20_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB20_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB21_BASE 0x10095000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB21_LIMIT 0x10095fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB21_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB21_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB22_BASE 0x10096000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB22_LIMIT 0x10096fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB22_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB22_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB23_BASE 0x10097000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB23_LIMIT 0x10097fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB23_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB23_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB24_BASE 0x10098000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB24_LIMIT 0x10098fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB24_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB24_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB25_BASE 0x10099000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB25_LIMIT 0x10099fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB25_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB25_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB26_BASE 0x1009a000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB26_LIMIT 0x1009afff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB26_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB26_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB27_BASE 0x1009b000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB27_LIMIT 0x1009bfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB27_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB27_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB28_BASE 0x1009c000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB28_LIMIT 0x1009cfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB28_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB28_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB29_BASE 0x1009d000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB29_LIMIT 0x1009dfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB29_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB29_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB30_BASE 0x1009e000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB30_LIMIT 0x1009efff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB30_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB30_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB31_BASE 0x1009f000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB31_LIMIT 0x1009ffff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB31_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB31_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB32_BASE 0x100a0000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB32_LIMIT 0x100a0fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB32_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB32_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB33_BASE 0x100a1000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB33_LIMIT 0x100a1fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB33_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB33_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB34_BASE 0x100a2000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB34_LIMIT 0x100a2fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB34_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB34_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB35_BASE 0x100a3000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB35_LIMIT 0x100a3fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB35_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB35_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB36_BASE 0x100a4000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB36_LIMIT 0x100a4fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB36_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB36_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB37_BASE 0x100a5000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB37_LIMIT 0x100a5fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB37_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB37_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB38_BASE 0x100a6000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB38_LIMIT 0x100a6fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB38_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB38_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB39_BASE 0x100a7000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB39_LIMIT 0x100a7fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB39_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB39_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB40_BASE 0x100a8000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB40_LIMIT 0x100a8fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB40_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB40_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB41_BASE 0x100a9000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB41_LIMIT 0x100a9fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB41_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB41_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB42_BASE 0x100aa000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB42_LIMIT 0x100aafff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB42_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB42_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB43_BASE 0x100ab000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB43_LIMIT 0x100abfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB43_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB43_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB44_BASE 0x100ac000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB44_LIMIT 0x100acfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB44_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB44_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB45_BASE 0x100ad000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB45_LIMIT 0x100adfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB45_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB45_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB46_BASE 0x100ae000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB46_LIMIT 0x100aefff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB46_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB46_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB47_BASE 0x100af000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB47_LIMIT 0x100affff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB47_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB47_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB48_BASE 0x100b0000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB48_LIMIT 0x100b0fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB48_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB48_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB49_BASE 0x100b1000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB49_LIMIT 0x100b1fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB49_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB49_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB50_BASE 0x100b2000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB50_LIMIT 0x100b2fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB50_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB50_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB51_BASE 0x100b3000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB51_LIMIT 0x100b3fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB51_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB51_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB52_BASE 0x100b4000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB52_LIMIT 0x100b4fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB52_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB52_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB53_BASE 0x100b5000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB53_LIMIT 0x100b5fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB53_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB53_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB54_BASE 0x100b6000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB54_LIMIT 0x100b6fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB54_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB54_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB55_BASE 0x100b7000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB55_LIMIT 0x100b7fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB55_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB55_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB56_BASE 0x100b8000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB56_LIMIT 0x100b8fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB56_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB56_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB57_BASE 0x100b9000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB57_LIMIT 0x100b9fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB57_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB57_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB58_BASE 0x100ba000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB58_LIMIT 0x100bafff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB58_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB58_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB59_BASE 0x100bb000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB59_LIMIT 0x100bbfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB59_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB59_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB60_BASE 0x100bc000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB60_LIMIT 0x100bcfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB60_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB60_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB61_BASE 0x100bd000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB61_LIMIT 0x100bdfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB61_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB61_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB62_BASE 0x100be000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB62_LIMIT 0x100befff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB62_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB62_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB63_BASE 0x100bf000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB63_LIMIT 0x100bffff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB63_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB63_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB64_BASE 0x100c0000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB64_LIMIT 0x100c0fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB64_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB64_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB65_BASE 0x100c1000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB65_LIMIT 0x100c1fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB65_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB65_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB66_BASE 0x100c2000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB66_LIMIT 0x100c2fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB66_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB66_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB67_BASE 0x100c3000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB67_LIMIT 0x100c3fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB67_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB67_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB68_BASE 0x100c4000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB68_LIMIT 0x100c4fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB68_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB68_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB69_BASE 0x100c5000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB69_LIMIT 0x100c5fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB69_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB69_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB70_BASE 0x100c6000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB70_LIMIT 0x100c6fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB70_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB70_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB71_BASE 0x100c7000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB71_LIMIT 0x100c7fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB71_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB71_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB72_BASE 0x100c8000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB72_LIMIT 0x100c8fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB72_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB72_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB73_BASE 0x100c9000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB73_LIMIT 0x100c9fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB73_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB73_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB74_BASE 0x100ca000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB74_LIMIT 0x100cafff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB74_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB74_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB75_BASE 0x100cb000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB75_LIMIT 0x100cbfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB75_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB75_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB76_BASE 0x100cc000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB76_LIMIT 0x100ccfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB76_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB76_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB77_BASE 0x100cd000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB77_LIMIT 0x100cdfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB77_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB77_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB78_BASE 0x100ce000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB78_LIMIT 0x100cefff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB78_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB78_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB79_BASE 0x100cf000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB79_LIMIT 0x100cffff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB79_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB79_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB80_BASE 0x100d0000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB80_LIMIT 0x100d0fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB80_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB80_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB81_BASE 0x100d1000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB81_LIMIT 0x100d1fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB81_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB81_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB82_BASE 0x100d2000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB82_LIMIT 0x100d2fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB82_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB82_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB83_BASE 0x100d3000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB83_LIMIT 0x100d3fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB83_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB83_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB84_BASE 0x100d4000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB84_LIMIT 0x100d4fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB84_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB84_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB85_BASE 0x100d5000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB85_LIMIT 0x100d5fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB85_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB85_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB86_BASE 0x100d6000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB86_LIMIT 0x100d6fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB86_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB86_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB87_BASE 0x100d7000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB87_LIMIT 0x100d7fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB87_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB87_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB88_BASE 0x100d8000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB88_LIMIT 0x100d8fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB88_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB88_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB89_BASE 0x100d9000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB89_LIMIT 0x100d9fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB89_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB89_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB90_BASE 0x100da000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB90_LIMIT 0x100dafff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB90_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB90_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB91_BASE 0x100db000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB91_LIMIT 0x100dbfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB91_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB91_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB92_BASE 0x100dc000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB92_LIMIT 0x100dcfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB92_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB92_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB93_BASE 0x100dd000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB93_LIMIT 0x100ddfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB93_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB93_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB94_BASE 0x100de000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB94_LIMIT 0x100defff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB94_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB94_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB95_BASE 0x100df000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB95_LIMIT 0x100dffff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB95_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB95_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB96_BASE 0x100e0000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB96_LIMIT 0x100e0fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB96_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB96_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB97_BASE 0x100e1000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB97_LIMIT 0x100e1fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB97_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB97_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB98_BASE 0x100e2000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB98_LIMIT 0x100e2fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB98_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB98_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB99_BASE 0x100e3000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB99_LIMIT 0x100e3fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB99_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB99_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB100_BASE 0x100e4000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB100_LIMIT 0x100e4fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB100_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB100_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB101_BASE 0x100e5000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB101_LIMIT 0x100e5fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB101_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB101_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB102_BASE 0x100e6000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB102_LIMIT 0x100e6fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB102_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB102_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB103_BASE 0x100e7000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB103_LIMIT 0x100e7fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB103_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB103_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB104_BASE 0x100e8000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB104_LIMIT 0x100e8fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB104_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB104_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB105_BASE 0x100e9000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB105_LIMIT 0x100e9fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB105_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB105_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB106_BASE 0x100ea000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB106_LIMIT 0x100eafff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB106_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB106_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB107_BASE 0x100eb000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB107_LIMIT 0x100ebfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB107_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB107_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB108_BASE 0x100ec000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB108_LIMIT 0x100ecfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB108_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB108_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB109_BASE 0x100ed000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB109_LIMIT 0x100edfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB109_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB109_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB110_BASE 0x100ee000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB110_LIMIT 0x100eefff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB110_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB110_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB111_BASE 0x100ef000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB111_LIMIT 0x100effff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB111_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB111_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB112_BASE 0x100f0000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB112_LIMIT 0x100f0fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB112_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB112_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB113_BASE 0x100f1000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB113_LIMIT 0x100f1fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB113_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB113_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB114_BASE 0x100f2000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB114_LIMIT 0x100f2fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB114_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB114_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB115_BASE 0x100f3000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB115_LIMIT 0x100f3fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB115_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB115_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB116_BASE 0x100f4000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB116_LIMIT 0x100f4fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB116_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB116_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB117_BASE 0x100f5000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB117_LIMIT 0x100f5fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB117_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB117_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB118_BASE 0x100f6000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB118_LIMIT 0x100f6fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB118_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB118_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB119_BASE 0x100f7000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB119_LIMIT 0x100f7fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB119_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB119_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB120_BASE 0x100f8000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB120_LIMIT 0x100f8fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB120_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB120_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB121_BASE 0x100f9000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB121_LIMIT 0x100f9fff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB121_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB121_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB122_BASE 0x100fa000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB122_LIMIT 0x100fafff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB122_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB122_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB123_BASE 0x100fb000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB123_LIMIT 0x100fbfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB123_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB123_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB124_BASE 0x100fc000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB124_LIMIT 0x100fcfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB124_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB124_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB125_BASE 0x100fd000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB125_LIMIT 0x100fdfff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB125_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB125_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB126_BASE 0x100fe000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB126_LIMIT 0x100fefff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB126_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB126_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB127_BASE 0x100ff000
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB127_LIMIT 0x100fffff
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB127_ADDR_LOCALITY SYSTEM_CFG.SMMU2_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU2_4KB_PAGESIZE_CB127_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB0_BASE 0x10800000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB0_LIMIT 0x1080ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB0_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB0_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB1_BASE 0x10810000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB1_LIMIT 0x1081ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB1_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB1_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB2_BASE 0x10820000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB2_LIMIT 0x1082ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB2_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB2_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB3_BASE 0x10830000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB3_LIMIT 0x1083ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB3_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB3_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB4_BASE 0x10840000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB4_LIMIT 0x1084ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB4_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB4_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB5_BASE 0x10850000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB5_LIMIT 0x1085ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB5_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB5_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB6_BASE 0x10860000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB6_LIMIT 0x1086ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB6_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB6_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB7_BASE 0x10870000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB7_LIMIT 0x1087ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB7_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB7_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB8_BASE 0x10880000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB8_LIMIT 0x1088ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB8_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB8_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB9_BASE 0x10890000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB9_LIMIT 0x1089ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB9_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB9_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB10_BASE 0x108a0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB10_LIMIT 0x108affff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB10_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB10_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB11_BASE 0x108b0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB11_LIMIT 0x108bffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB11_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB11_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB12_BASE 0x108c0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB12_LIMIT 0x108cffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB12_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB12_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB13_BASE 0x108d0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB13_LIMIT 0x108dffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB13_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB13_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB14_BASE 0x108e0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB14_LIMIT 0x108effff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB14_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB14_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB15_BASE 0x108f0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB15_LIMIT 0x108fffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB15_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB15_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB16_BASE 0x10900000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB16_LIMIT 0x1090ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB16_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB16_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB17_BASE 0x10910000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB17_LIMIT 0x1091ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB17_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB17_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB18_BASE 0x10920000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB18_LIMIT 0x1092ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB18_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB18_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB19_BASE 0x10930000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB19_LIMIT 0x1093ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB19_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB19_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB20_BASE 0x10940000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB20_LIMIT 0x1094ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB20_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB20_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB21_BASE 0x10950000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB21_LIMIT 0x1095ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB21_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB21_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB22_BASE 0x10960000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB22_LIMIT 0x1096ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB22_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB22_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB23_BASE 0x10970000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB23_LIMIT 0x1097ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB23_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB23_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB24_BASE 0x10980000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB24_LIMIT 0x1098ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB24_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB24_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB25_BASE 0x10990000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB25_LIMIT 0x1099ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB25_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB25_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB26_BASE 0x109a0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB26_LIMIT 0x109affff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB26_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB26_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB27_BASE 0x109b0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB27_LIMIT 0x109bffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB27_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB27_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB28_BASE 0x109c0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB28_LIMIT 0x109cffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB28_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB28_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB29_BASE 0x109d0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB29_LIMIT 0x109dffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB29_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB29_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB30_BASE 0x109e0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB30_LIMIT 0x109effff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB30_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB30_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB31_BASE 0x109f0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB31_LIMIT 0x109fffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB31_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB31_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB32_BASE 0x10a00000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB32_LIMIT 0x10a0ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB32_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB32_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB33_BASE 0x10a10000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB33_LIMIT 0x10a1ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB33_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB33_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB34_BASE 0x10a20000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB34_LIMIT 0x10a2ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB34_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB34_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB35_BASE 0x10a30000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB35_LIMIT 0x10a3ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB35_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB35_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB36_BASE 0x10a40000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB36_LIMIT 0x10a4ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB36_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB36_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB37_BASE 0x10a50000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB37_LIMIT 0x10a5ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB37_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB37_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB38_BASE 0x10a60000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB38_LIMIT 0x10a6ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB38_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB38_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB39_BASE 0x10a70000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB39_LIMIT 0x10a7ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB39_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB39_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB40_BASE 0x10a80000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB40_LIMIT 0x10a8ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB40_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB40_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB41_BASE 0x10a90000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB41_LIMIT 0x10a9ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB41_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB41_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB42_BASE 0x10aa0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB42_LIMIT 0x10aaffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB42_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB42_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB43_BASE 0x10ab0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB43_LIMIT 0x10abffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB43_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB43_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB44_BASE 0x10ac0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB44_LIMIT 0x10acffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB44_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB44_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB45_BASE 0x10ad0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB45_LIMIT 0x10adffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB45_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB45_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB46_BASE 0x10ae0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB46_LIMIT 0x10aeffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB46_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB46_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB47_BASE 0x10af0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB47_LIMIT 0x10afffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB47_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB47_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB48_BASE 0x10b00000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB48_LIMIT 0x10b0ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB48_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB48_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB49_BASE 0x10b10000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB49_LIMIT 0x10b1ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB49_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB49_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB50_BASE 0x10b20000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB50_LIMIT 0x10b2ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB50_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB50_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB51_BASE 0x10b30000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB51_LIMIT 0x10b3ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB51_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB51_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB52_BASE 0x10b40000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB52_LIMIT 0x10b4ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB52_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB52_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB53_BASE 0x10b50000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB53_LIMIT 0x10b5ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB53_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB53_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB54_BASE 0x10b60000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB54_LIMIT 0x10b6ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB54_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB54_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB55_BASE 0x10b70000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB55_LIMIT 0x10b7ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB55_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB55_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB56_BASE 0x10b80000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB56_LIMIT 0x10b8ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB56_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB56_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB57_BASE 0x10b90000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB57_LIMIT 0x10b9ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB57_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB57_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB58_BASE 0x10ba0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB58_LIMIT 0x10baffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB58_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB58_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB59_BASE 0x10bb0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB59_LIMIT 0x10bbffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB59_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB59_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB60_BASE 0x10bc0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB60_LIMIT 0x10bcffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB60_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB60_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB61_BASE 0x10bd0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB61_LIMIT 0x10bdffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB61_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB61_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB62_BASE 0x10be0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB62_LIMIT 0x10beffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB62_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB62_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB63_BASE 0x10bf0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB63_LIMIT 0x10bfffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB63_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB63_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB64_BASE 0x10c00000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB64_LIMIT 0x10c0ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB64_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB64_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB65_BASE 0x10c10000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB65_LIMIT 0x10c1ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB65_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB65_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB66_BASE 0x10c20000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB66_LIMIT 0x10c2ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB66_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB66_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB67_BASE 0x10c30000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB67_LIMIT 0x10c3ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB67_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB67_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB68_BASE 0x10c40000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB68_LIMIT 0x10c4ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB68_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB68_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB69_BASE 0x10c50000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB69_LIMIT 0x10c5ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB69_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB69_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB70_BASE 0x10c60000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB70_LIMIT 0x10c6ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB70_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB70_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB71_BASE 0x10c70000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB71_LIMIT 0x10c7ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB71_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB71_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB72_BASE 0x10c80000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB72_LIMIT 0x10c8ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB72_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB72_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB73_BASE 0x10c90000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB73_LIMIT 0x10c9ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB73_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB73_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB74_BASE 0x10ca0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB74_LIMIT 0x10caffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB74_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB74_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB75_BASE 0x10cb0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB75_LIMIT 0x10cbffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB75_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB75_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB76_BASE 0x10cc0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB76_LIMIT 0x10ccffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB76_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB76_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB77_BASE 0x10cd0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB77_LIMIT 0x10cdffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB77_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB77_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB78_BASE 0x10ce0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB78_LIMIT 0x10ceffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB78_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB78_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB79_BASE 0x10cf0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB79_LIMIT 0x10cfffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB79_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB79_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB80_BASE 0x10d00000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB80_LIMIT 0x10d0ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB80_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB80_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB81_BASE 0x10d10000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB81_LIMIT 0x10d1ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB81_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB81_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB82_BASE 0x10d20000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB82_LIMIT 0x10d2ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB82_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB82_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB83_BASE 0x10d30000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB83_LIMIT 0x10d3ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB83_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB83_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB84_BASE 0x10d40000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB84_LIMIT 0x10d4ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB84_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB84_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB85_BASE 0x10d50000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB85_LIMIT 0x10d5ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB85_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB85_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB86_BASE 0x10d60000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB86_LIMIT 0x10d6ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB86_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB86_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB87_BASE 0x10d70000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB87_LIMIT 0x10d7ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB87_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB87_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB88_BASE 0x10d80000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB88_LIMIT 0x10d8ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB88_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB88_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB89_BASE 0x10d90000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB89_LIMIT 0x10d9ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB89_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB89_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB90_BASE 0x10da0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB90_LIMIT 0x10daffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB90_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB90_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB91_BASE 0x10db0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB91_LIMIT 0x10dbffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB91_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB91_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB92_BASE 0x10dc0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB92_LIMIT 0x10dcffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB92_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB92_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB93_BASE 0x10dd0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB93_LIMIT 0x10ddffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB93_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB93_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB94_BASE 0x10de0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB94_LIMIT 0x10deffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB94_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB94_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB95_BASE 0x10df0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB95_LIMIT 0x10dfffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB95_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB95_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB96_BASE 0x10e00000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB96_LIMIT 0x10e0ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB96_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB96_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB97_BASE 0x10e10000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB97_LIMIT 0x10e1ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB97_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB97_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB98_BASE 0x10e20000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB98_LIMIT 0x10e2ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB98_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB98_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB99_BASE 0x10e30000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB99_LIMIT 0x10e3ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB99_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB99_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB100_BASE 0x10e40000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB100_LIMIT 0x10e4ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB100_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB100_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB101_BASE 0x10e50000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB101_LIMIT 0x10e5ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB101_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB101_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB102_BASE 0x10e60000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB102_LIMIT 0x10e6ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB102_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB102_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB103_BASE 0x10e70000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB103_LIMIT 0x10e7ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB103_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB103_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB104_BASE 0x10e80000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB104_LIMIT 0x10e8ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB104_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB104_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB105_BASE 0x10e90000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB105_LIMIT 0x10e9ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB105_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB105_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB106_BASE 0x10ea0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB106_LIMIT 0x10eaffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB106_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB106_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB107_BASE 0x10eb0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB107_LIMIT 0x10ebffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB107_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB107_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB108_BASE 0x10ec0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB108_LIMIT 0x10ecffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB108_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB108_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB109_BASE 0x10ed0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB109_LIMIT 0x10edffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB109_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB109_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB110_BASE 0x10ee0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB110_LIMIT 0x10eeffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB110_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB110_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB111_BASE 0x10ef0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB111_LIMIT 0x10efffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB111_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB111_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB112_BASE 0x10f00000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB112_LIMIT 0x10f0ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB112_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB112_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB113_BASE 0x10f10000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB113_LIMIT 0x10f1ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB113_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB113_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB114_BASE 0x10f20000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB114_LIMIT 0x10f2ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB114_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB114_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB115_BASE 0x10f30000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB115_LIMIT 0x10f3ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB115_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB115_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB116_BASE 0x10f40000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB116_LIMIT 0x10f4ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB116_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB116_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB117_BASE 0x10f50000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB117_LIMIT 0x10f5ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB117_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB117_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB118_BASE 0x10f60000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB118_LIMIT 0x10f6ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB118_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB118_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB119_BASE 0x10f70000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB119_LIMIT 0x10f7ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB119_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB119_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB120_BASE 0x10f80000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB120_LIMIT 0x10f8ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB120_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB120_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB121_BASE 0x10f90000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB121_LIMIT 0x10f9ffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB121_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB121_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB122_BASE 0x10fa0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB122_LIMIT 0x10faffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB122_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB122_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB123_BASE 0x10fb0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB123_LIMIT 0x10fbffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB123_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB123_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB124_BASE 0x10fc0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB124_LIMIT 0x10fcffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB124_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB124_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB125_BASE 0x10fd0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB125_LIMIT 0x10fdffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB125_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB125_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB126_BASE 0x10fe0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB126_LIMIT 0x10feffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB126_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB126_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB127_BASE 0x10ff0000
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB127_LIMIT 0x10ffffff
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB127_ADDR_LOCALITY SYSTEM_CFG.SMMU2_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU2_64KB_PAGESIZE_CB127_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_GR0_BASE 0x11000000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_GR0_LIMIT 0x1100ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_GR0_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_GR0_HEADER arm_smmu_500_global.h;arm_smmu_500_global_sec.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_GR0_BASE 0x11000000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_GR0_LIMIT 0x11000fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_GR0_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_GR0_HEADER arm_smmu_500_global.h;arm_smmu_500_global_sec.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_GR1_BASE 0x11001000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_GR1_LIMIT 0x11001fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_GR1_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_GR1_HEADER arm_smmu_500_global_1.h;arm_smmu_500_global_sec_1.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_GID_BASE 0x11002000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_GID_LIMIT 0x11002fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_GID_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_GID_HEADER arm_smmu_500_integ_sec.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_PM_BASE 0x11003000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_PM_LIMIT 0x11003fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_PM_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_PM_HEADER arm_smmu_500_perf_mon.h;arm_smmu_500_perf_mon_sec.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_GR1_BASE 0x11010000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_GR1_LIMIT 0x1101ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_GR1_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_GR1_HEADER arm_smmu_500_global_1.h;arm_smmu_500_global_sec_1.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_GID_BASE 0x11020000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_GID_LIMIT 0x1102ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_GID_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_GID_HEADER arm_smmu_500_integ_sec.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_PM_BASE 0x11030000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_PM_LIMIT 0x1103ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_PM_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_PM_HEADER arm_smmu_500_perf_mon.h;arm_smmu_500_perf_mon_sec.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB0_BASE 0x11080000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB0_LIMIT 0x11080fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB0_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB0_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB1_BASE 0x11081000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB1_LIMIT 0x11081fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB1_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB1_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB2_BASE 0x11082000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB2_LIMIT 0x11082fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB2_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB2_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB3_BASE 0x11083000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB3_LIMIT 0x11083fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB3_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB3_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB4_BASE 0x11084000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB4_LIMIT 0x11084fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB4_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB4_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB5_BASE 0x11085000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB5_LIMIT 0x11085fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB5_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB5_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB6_BASE 0x11086000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB6_LIMIT 0x11086fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB6_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB6_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB7_BASE 0x11087000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB7_LIMIT 0x11087fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB7_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB7_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB8_BASE 0x11088000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB8_LIMIT 0x11088fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB8_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB8_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB9_BASE 0x11089000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB9_LIMIT 0x11089fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB9_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB9_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB10_BASE 0x1108a000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB10_LIMIT 0x1108afff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB10_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB10_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB11_BASE 0x1108b000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB11_LIMIT 0x1108bfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB11_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB11_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB12_BASE 0x1108c000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB12_LIMIT 0x1108cfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB12_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB12_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB13_BASE 0x1108d000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB13_LIMIT 0x1108dfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB13_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB13_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB14_BASE 0x1108e000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB14_LIMIT 0x1108efff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB14_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB14_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB15_BASE 0x1108f000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB15_LIMIT 0x1108ffff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB15_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB15_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB16_BASE 0x11090000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB16_LIMIT 0x11090fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB16_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB16_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB17_BASE 0x11091000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB17_LIMIT 0x11091fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB17_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB17_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB18_BASE 0x11092000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB18_LIMIT 0x11092fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB18_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB18_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB19_BASE 0x11093000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB19_LIMIT 0x11093fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB19_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB19_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB20_BASE 0x11094000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB20_LIMIT 0x11094fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB20_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB20_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB21_BASE 0x11095000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB21_LIMIT 0x11095fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB21_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB21_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB22_BASE 0x11096000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB22_LIMIT 0x11096fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB22_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB22_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB23_BASE 0x11097000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB23_LIMIT 0x11097fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB23_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB23_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB24_BASE 0x11098000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB24_LIMIT 0x11098fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB24_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB24_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB25_BASE 0x11099000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB25_LIMIT 0x11099fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB25_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB25_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB26_BASE 0x1109a000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB26_LIMIT 0x1109afff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB26_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB26_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB27_BASE 0x1109b000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB27_LIMIT 0x1109bfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB27_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB27_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB28_BASE 0x1109c000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB28_LIMIT 0x1109cfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB28_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB28_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB29_BASE 0x1109d000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB29_LIMIT 0x1109dfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB29_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB29_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB30_BASE 0x1109e000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB30_LIMIT 0x1109efff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB30_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB30_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB31_BASE 0x1109f000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB31_LIMIT 0x1109ffff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB31_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB31_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB32_BASE 0x110a0000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB32_LIMIT 0x110a0fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB32_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB32_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB33_BASE 0x110a1000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB33_LIMIT 0x110a1fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB33_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB33_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB34_BASE 0x110a2000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB34_LIMIT 0x110a2fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB34_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB34_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB35_BASE 0x110a3000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB35_LIMIT 0x110a3fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB35_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB35_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB36_BASE 0x110a4000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB36_LIMIT 0x110a4fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB36_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB36_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB37_BASE 0x110a5000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB37_LIMIT 0x110a5fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB37_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB37_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB38_BASE 0x110a6000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB38_LIMIT 0x110a6fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB38_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB38_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB39_BASE 0x110a7000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB39_LIMIT 0x110a7fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB39_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB39_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB40_BASE 0x110a8000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB40_LIMIT 0x110a8fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB40_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB40_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB41_BASE 0x110a9000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB41_LIMIT 0x110a9fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB41_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB41_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB42_BASE 0x110aa000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB42_LIMIT 0x110aafff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB42_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB42_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB43_BASE 0x110ab000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB43_LIMIT 0x110abfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB43_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB43_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB44_BASE 0x110ac000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB44_LIMIT 0x110acfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB44_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB44_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB45_BASE 0x110ad000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB45_LIMIT 0x110adfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB45_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB45_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB46_BASE 0x110ae000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB46_LIMIT 0x110aefff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB46_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB46_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB47_BASE 0x110af000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB47_LIMIT 0x110affff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB47_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB47_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB48_BASE 0x110b0000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB48_LIMIT 0x110b0fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB48_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB48_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB49_BASE 0x110b1000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB49_LIMIT 0x110b1fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB49_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB49_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB50_BASE 0x110b2000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB50_LIMIT 0x110b2fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB50_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB50_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB51_BASE 0x110b3000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB51_LIMIT 0x110b3fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB51_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB51_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB52_BASE 0x110b4000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB52_LIMIT 0x110b4fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB52_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB52_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB53_BASE 0x110b5000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB53_LIMIT 0x110b5fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB53_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB53_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB54_BASE 0x110b6000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB54_LIMIT 0x110b6fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB54_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB54_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB55_BASE 0x110b7000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB55_LIMIT 0x110b7fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB55_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB55_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB56_BASE 0x110b8000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB56_LIMIT 0x110b8fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB56_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB56_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB57_BASE 0x110b9000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB57_LIMIT 0x110b9fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB57_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB57_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB58_BASE 0x110ba000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB58_LIMIT 0x110bafff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB58_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB58_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB59_BASE 0x110bb000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB59_LIMIT 0x110bbfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB59_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB59_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB60_BASE 0x110bc000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB60_LIMIT 0x110bcfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB60_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB60_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB61_BASE 0x110bd000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB61_LIMIT 0x110bdfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB61_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB61_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB62_BASE 0x110be000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB62_LIMIT 0x110befff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB62_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB62_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB63_BASE 0x110bf000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB63_LIMIT 0x110bffff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB63_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB63_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB64_BASE 0x110c0000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB64_LIMIT 0x110c0fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB64_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB64_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB65_BASE 0x110c1000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB65_LIMIT 0x110c1fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB65_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB65_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB66_BASE 0x110c2000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB66_LIMIT 0x110c2fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB66_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB66_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB67_BASE 0x110c3000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB67_LIMIT 0x110c3fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB67_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB67_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB68_BASE 0x110c4000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB68_LIMIT 0x110c4fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB68_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB68_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB69_BASE 0x110c5000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB69_LIMIT 0x110c5fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB69_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB69_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB70_BASE 0x110c6000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB70_LIMIT 0x110c6fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB70_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB70_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB71_BASE 0x110c7000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB71_LIMIT 0x110c7fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB71_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB71_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB72_BASE 0x110c8000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB72_LIMIT 0x110c8fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB72_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB72_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB73_BASE 0x110c9000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB73_LIMIT 0x110c9fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB73_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB73_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB74_BASE 0x110ca000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB74_LIMIT 0x110cafff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB74_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB74_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB75_BASE 0x110cb000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB75_LIMIT 0x110cbfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB75_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB75_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB76_BASE 0x110cc000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB76_LIMIT 0x110ccfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB76_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB76_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB77_BASE 0x110cd000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB77_LIMIT 0x110cdfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB77_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB77_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB78_BASE 0x110ce000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB78_LIMIT 0x110cefff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB78_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB78_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB79_BASE 0x110cf000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB79_LIMIT 0x110cffff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB79_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB79_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB80_BASE 0x110d0000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB80_LIMIT 0x110d0fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB80_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB80_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB81_BASE 0x110d1000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB81_LIMIT 0x110d1fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB81_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB81_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB82_BASE 0x110d2000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB82_LIMIT 0x110d2fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB82_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB82_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB83_BASE 0x110d3000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB83_LIMIT 0x110d3fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB83_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB83_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB84_BASE 0x110d4000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB84_LIMIT 0x110d4fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB84_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB84_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB85_BASE 0x110d5000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB85_LIMIT 0x110d5fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB85_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB85_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB86_BASE 0x110d6000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB86_LIMIT 0x110d6fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB86_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB86_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB87_BASE 0x110d7000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB87_LIMIT 0x110d7fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB87_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB87_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB88_BASE 0x110d8000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB88_LIMIT 0x110d8fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB88_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB88_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB89_BASE 0x110d9000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB89_LIMIT 0x110d9fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB89_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB89_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB90_BASE 0x110da000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB90_LIMIT 0x110dafff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB90_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB90_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB91_BASE 0x110db000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB91_LIMIT 0x110dbfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB91_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB91_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB92_BASE 0x110dc000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB92_LIMIT 0x110dcfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB92_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB92_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB93_BASE 0x110dd000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB93_LIMIT 0x110ddfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB93_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB93_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB94_BASE 0x110de000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB94_LIMIT 0x110defff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB94_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB94_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB95_BASE 0x110df000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB95_LIMIT 0x110dffff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB95_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB95_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB96_BASE 0x110e0000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB96_LIMIT 0x110e0fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB96_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB96_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB97_BASE 0x110e1000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB97_LIMIT 0x110e1fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB97_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB97_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB98_BASE 0x110e2000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB98_LIMIT 0x110e2fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB98_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB98_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB99_BASE 0x110e3000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB99_LIMIT 0x110e3fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB99_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB99_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB100_BASE 0x110e4000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB100_LIMIT 0x110e4fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB100_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB100_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB101_BASE 0x110e5000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB101_LIMIT 0x110e5fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB101_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB101_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB102_BASE 0x110e6000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB102_LIMIT 0x110e6fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB102_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB102_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB103_BASE 0x110e7000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB103_LIMIT 0x110e7fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB103_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB103_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB104_BASE 0x110e8000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB104_LIMIT 0x110e8fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB104_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB104_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB105_BASE 0x110e9000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB105_LIMIT 0x110e9fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB105_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB105_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB106_BASE 0x110ea000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB106_LIMIT 0x110eafff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB106_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB106_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB107_BASE 0x110eb000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB107_LIMIT 0x110ebfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB107_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB107_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB108_BASE 0x110ec000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB108_LIMIT 0x110ecfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB108_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB108_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB109_BASE 0x110ed000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB109_LIMIT 0x110edfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB109_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB109_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB110_BASE 0x110ee000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB110_LIMIT 0x110eefff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB110_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB110_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB111_BASE 0x110ef000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB111_LIMIT 0x110effff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB111_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB111_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB112_BASE 0x110f0000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB112_LIMIT 0x110f0fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB112_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB112_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB113_BASE 0x110f1000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB113_LIMIT 0x110f1fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB113_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB113_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB114_BASE 0x110f2000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB114_LIMIT 0x110f2fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB114_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB114_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB115_BASE 0x110f3000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB115_LIMIT 0x110f3fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB115_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB115_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB116_BASE 0x110f4000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB116_LIMIT 0x110f4fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB116_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB116_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB117_BASE 0x110f5000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB117_LIMIT 0x110f5fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB117_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB117_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB118_BASE 0x110f6000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB118_LIMIT 0x110f6fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB118_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB118_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB119_BASE 0x110f7000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB119_LIMIT 0x110f7fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB119_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB119_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB120_BASE 0x110f8000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB120_LIMIT 0x110f8fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB120_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB120_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB121_BASE 0x110f9000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB121_LIMIT 0x110f9fff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB121_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB121_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB122_BASE 0x110fa000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB122_LIMIT 0x110fafff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB122_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB122_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB123_BASE 0x110fb000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB123_LIMIT 0x110fbfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB123_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB123_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB124_BASE 0x110fc000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB124_LIMIT 0x110fcfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB124_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB124_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB125_BASE 0x110fd000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB125_LIMIT 0x110fdfff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB125_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB125_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB126_BASE 0x110fe000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB126_LIMIT 0x110fefff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB126_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB126_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB127_BASE 0x110ff000
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB127_LIMIT 0x110fffff
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB127_ADDR_LOCALITY SYSTEM_CFG.SMMU1_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU1_4KB_PAGESIZE_CB127_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB0_BASE 0x11800000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB0_LIMIT 0x1180ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB0_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB0_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB1_BASE 0x11810000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB1_LIMIT 0x1181ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB1_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB1_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB2_BASE 0x11820000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB2_LIMIT 0x1182ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB2_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB2_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB3_BASE 0x11830000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB3_LIMIT 0x1183ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB3_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB3_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB4_BASE 0x11840000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB4_LIMIT 0x1184ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB4_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB4_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB5_BASE 0x11850000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB5_LIMIT 0x1185ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB5_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB5_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB6_BASE 0x11860000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB6_LIMIT 0x1186ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB6_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB6_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB7_BASE 0x11870000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB7_LIMIT 0x1187ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB7_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB7_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB8_BASE 0x11880000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB8_LIMIT 0x1188ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB8_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB8_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB9_BASE 0x11890000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB9_LIMIT 0x1189ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB9_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB9_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB10_BASE 0x118a0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB10_LIMIT 0x118affff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB10_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB10_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB11_BASE 0x118b0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB11_LIMIT 0x118bffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB11_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB11_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB12_BASE 0x118c0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB12_LIMIT 0x118cffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB12_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB12_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB13_BASE 0x118d0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB13_LIMIT 0x118dffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB13_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB13_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB14_BASE 0x118e0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB14_LIMIT 0x118effff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB14_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB14_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB15_BASE 0x118f0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB15_LIMIT 0x118fffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB15_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB15_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB16_BASE 0x11900000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB16_LIMIT 0x1190ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB16_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB16_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB17_BASE 0x11910000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB17_LIMIT 0x1191ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB17_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB17_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB18_BASE 0x11920000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB18_LIMIT 0x1192ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB18_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB18_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB19_BASE 0x11930000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB19_LIMIT 0x1193ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB19_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB19_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB20_BASE 0x11940000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB20_LIMIT 0x1194ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB20_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB20_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB21_BASE 0x11950000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB21_LIMIT 0x1195ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB21_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB21_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB22_BASE 0x11960000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB22_LIMIT 0x1196ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB22_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB22_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB23_BASE 0x11970000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB23_LIMIT 0x1197ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB23_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB23_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB24_BASE 0x11980000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB24_LIMIT 0x1198ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB24_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB24_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB25_BASE 0x11990000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB25_LIMIT 0x1199ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB25_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB25_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB26_BASE 0x119a0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB26_LIMIT 0x119affff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB26_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB26_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB27_BASE 0x119b0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB27_LIMIT 0x119bffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB27_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB27_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB28_BASE 0x119c0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB28_LIMIT 0x119cffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB28_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB28_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB29_BASE 0x119d0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB29_LIMIT 0x119dffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB29_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB29_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB30_BASE 0x119e0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB30_LIMIT 0x119effff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB30_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB30_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB31_BASE 0x119f0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB31_LIMIT 0x119fffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB31_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB31_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB32_BASE 0x11a00000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB32_LIMIT 0x11a0ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB32_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB32_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB33_BASE 0x11a10000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB33_LIMIT 0x11a1ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB33_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB33_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB34_BASE 0x11a20000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB34_LIMIT 0x11a2ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB34_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB34_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB35_BASE 0x11a30000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB35_LIMIT 0x11a3ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB35_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB35_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB36_BASE 0x11a40000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB36_LIMIT 0x11a4ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB36_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB36_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB37_BASE 0x11a50000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB37_LIMIT 0x11a5ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB37_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB37_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB38_BASE 0x11a60000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB38_LIMIT 0x11a6ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB38_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB38_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB39_BASE 0x11a70000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB39_LIMIT 0x11a7ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB39_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB39_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB40_BASE 0x11a80000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB40_LIMIT 0x11a8ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB40_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB40_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB41_BASE 0x11a90000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB41_LIMIT 0x11a9ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB41_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB41_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB42_BASE 0x11aa0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB42_LIMIT 0x11aaffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB42_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB42_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB43_BASE 0x11ab0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB43_LIMIT 0x11abffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB43_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB43_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB44_BASE 0x11ac0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB44_LIMIT 0x11acffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB44_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB44_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB45_BASE 0x11ad0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB45_LIMIT 0x11adffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB45_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB45_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB46_BASE 0x11ae0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB46_LIMIT 0x11aeffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB46_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB46_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB47_BASE 0x11af0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB47_LIMIT 0x11afffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB47_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB47_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB48_BASE 0x11b00000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB48_LIMIT 0x11b0ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB48_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB48_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB49_BASE 0x11b10000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB49_LIMIT 0x11b1ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB49_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB49_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB50_BASE 0x11b20000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB50_LIMIT 0x11b2ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB50_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB50_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB51_BASE 0x11b30000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB51_LIMIT 0x11b3ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB51_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB51_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB52_BASE 0x11b40000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB52_LIMIT 0x11b4ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB52_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB52_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB53_BASE 0x11b50000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB53_LIMIT 0x11b5ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB53_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB53_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB54_BASE 0x11b60000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB54_LIMIT 0x11b6ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB54_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB54_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB55_BASE 0x11b70000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB55_LIMIT 0x11b7ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB55_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB55_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB56_BASE 0x11b80000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB56_LIMIT 0x11b8ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB56_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB56_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB57_BASE 0x11b90000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB57_LIMIT 0x11b9ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB57_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB57_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB58_BASE 0x11ba0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB58_LIMIT 0x11baffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB58_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB58_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB59_BASE 0x11bb0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB59_LIMIT 0x11bbffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB59_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB59_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB60_BASE 0x11bc0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB60_LIMIT 0x11bcffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB60_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB60_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB61_BASE 0x11bd0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB61_LIMIT 0x11bdffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB61_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB61_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB62_BASE 0x11be0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB62_LIMIT 0x11beffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB62_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB62_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB63_BASE 0x11bf0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB63_LIMIT 0x11bfffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB63_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB63_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB64_BASE 0x11c00000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB64_LIMIT 0x11c0ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB64_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB64_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB65_BASE 0x11c10000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB65_LIMIT 0x11c1ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB65_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB65_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB66_BASE 0x11c20000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB66_LIMIT 0x11c2ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB66_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB66_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB67_BASE 0x11c30000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB67_LIMIT 0x11c3ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB67_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB67_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB68_BASE 0x11c40000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB68_LIMIT 0x11c4ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB68_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB68_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB69_BASE 0x11c50000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB69_LIMIT 0x11c5ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB69_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB69_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB70_BASE 0x11c60000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB70_LIMIT 0x11c6ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB70_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB70_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB71_BASE 0x11c70000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB71_LIMIT 0x11c7ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB71_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB71_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB72_BASE 0x11c80000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB72_LIMIT 0x11c8ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB72_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB72_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB73_BASE 0x11c90000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB73_LIMIT 0x11c9ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB73_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB73_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB74_BASE 0x11ca0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB74_LIMIT 0x11caffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB74_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB74_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB75_BASE 0x11cb0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB75_LIMIT 0x11cbffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB75_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB75_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB76_BASE 0x11cc0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB76_LIMIT 0x11ccffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB76_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB76_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB77_BASE 0x11cd0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB77_LIMIT 0x11cdffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB77_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB77_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB78_BASE 0x11ce0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB78_LIMIT 0x11ceffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB78_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB78_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB79_BASE 0x11cf0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB79_LIMIT 0x11cfffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB79_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB79_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB80_BASE 0x11d00000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB80_LIMIT 0x11d0ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB80_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB80_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB81_BASE 0x11d10000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB81_LIMIT 0x11d1ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB81_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB81_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB82_BASE 0x11d20000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB82_LIMIT 0x11d2ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB82_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB82_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB83_BASE 0x11d30000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB83_LIMIT 0x11d3ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB83_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB83_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB84_BASE 0x11d40000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB84_LIMIT 0x11d4ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB84_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB84_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB85_BASE 0x11d50000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB85_LIMIT 0x11d5ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB85_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB85_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB86_BASE 0x11d60000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB86_LIMIT 0x11d6ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB86_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB86_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB87_BASE 0x11d70000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB87_LIMIT 0x11d7ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB87_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB87_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB88_BASE 0x11d80000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB88_LIMIT 0x11d8ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB88_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB88_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB89_BASE 0x11d90000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB89_LIMIT 0x11d9ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB89_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB89_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB90_BASE 0x11da0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB90_LIMIT 0x11daffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB90_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB90_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB91_BASE 0x11db0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB91_LIMIT 0x11dbffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB91_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB91_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB92_BASE 0x11dc0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB92_LIMIT 0x11dcffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB92_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB92_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB93_BASE 0x11dd0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB93_LIMIT 0x11ddffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB93_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB93_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB94_BASE 0x11de0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB94_LIMIT 0x11deffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB94_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB94_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB95_BASE 0x11df0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB95_LIMIT 0x11dfffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB95_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB95_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB96_BASE 0x11e00000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB96_LIMIT 0x11e0ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB96_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB96_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB97_BASE 0x11e10000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB97_LIMIT 0x11e1ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB97_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB97_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB98_BASE 0x11e20000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB98_LIMIT 0x11e2ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB98_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB98_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB99_BASE 0x11e30000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB99_LIMIT 0x11e3ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB99_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB99_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB100_BASE 0x11e40000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB100_LIMIT 0x11e4ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB100_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB100_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB101_BASE 0x11e50000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB101_LIMIT 0x11e5ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB101_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB101_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB102_BASE 0x11e60000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB102_LIMIT 0x11e6ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB102_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB102_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB103_BASE 0x11e70000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB103_LIMIT 0x11e7ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB103_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB103_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB104_BASE 0x11e80000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB104_LIMIT 0x11e8ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB104_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB104_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB105_BASE 0x11e90000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB105_LIMIT 0x11e9ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB105_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB105_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB106_BASE 0x11ea0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB106_LIMIT 0x11eaffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB106_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB106_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB107_BASE 0x11eb0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB107_LIMIT 0x11ebffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB107_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB107_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB108_BASE 0x11ec0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB108_LIMIT 0x11ecffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB108_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB108_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB109_BASE 0x11ed0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB109_LIMIT 0x11edffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB109_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB109_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB110_BASE 0x11ee0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB110_LIMIT 0x11eeffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB110_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB110_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB111_BASE 0x11ef0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB111_LIMIT 0x11efffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB111_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB111_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB112_BASE 0x11f00000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB112_LIMIT 0x11f0ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB112_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB112_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB113_BASE 0x11f10000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB113_LIMIT 0x11f1ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB113_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB113_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB114_BASE 0x11f20000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB114_LIMIT 0x11f2ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB114_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB114_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB115_BASE 0x11f30000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB115_LIMIT 0x11f3ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB115_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB115_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB116_BASE 0x11f40000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB116_LIMIT 0x11f4ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB116_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB116_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB117_BASE 0x11f50000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB117_LIMIT 0x11f5ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB117_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB117_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB118_BASE 0x11f60000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB118_LIMIT 0x11f6ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB118_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB118_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB119_BASE 0x11f70000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB119_LIMIT 0x11f7ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB119_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB119_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB120_BASE 0x11f80000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB120_LIMIT 0x11f8ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB120_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB120_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB121_BASE 0x11f90000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB121_LIMIT 0x11f9ffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB121_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB121_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB122_BASE 0x11fa0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB122_LIMIT 0x11faffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB122_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB122_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB123_BASE 0x11fb0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB123_LIMIT 0x11fbffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB123_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB123_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB124_BASE 0x11fc0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB124_LIMIT 0x11fcffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB124_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB124_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB125_BASE 0x11fd0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB125_LIMIT 0x11fdffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB125_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB125_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB126_BASE 0x11fe0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB126_LIMIT 0x11feffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB126_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB126_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB127_BASE 0x11ff0000
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB127_LIMIT 0x11ffffff
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB127_ADDR_LOCALITY SYSTEM_CFG.SMMU1_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU1_64KB_PAGESIZE_CB127_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_GR0_BASE 0x12000000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_GR0_LIMIT 0x1200ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_GR0_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_GR0_HEADER arm_smmu_500_global.h;arm_smmu_500_global_sec.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_GR0_BASE 0x12000000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_GR0_LIMIT 0x12000fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_GR0_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_GR0_HEADER arm_smmu_500_global.h;arm_smmu_500_global_sec.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_GR1_BASE 0x12001000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_GR1_LIMIT 0x12001fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_GR1_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_GR1_HEADER arm_smmu_500_global_1.h;arm_smmu_500_global_sec_1.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_GID_BASE 0x12002000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_GID_LIMIT 0x12002fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_GID_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_GID_HEADER arm_smmu_500_integ_sec.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_PM_BASE 0x12003000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_PM_LIMIT 0x12003fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_PM_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_PM_HEADER arm_smmu_500_perf_mon.h;arm_smmu_500_perf_mon_sec.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_GR1_BASE 0x12010000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_GR1_LIMIT 0x1201ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_GR1_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_GR1_HEADER arm_smmu_500_global_1.h;arm_smmu_500_global_sec_1.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_GID_BASE 0x12020000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_GID_LIMIT 0x1202ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_GID_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_GID_HEADER arm_smmu_500_integ_sec.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_PM_BASE 0x12030000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_PM_LIMIT 0x1203ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_PM_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_PM_HEADER arm_smmu_500_perf_mon.h;arm_smmu_500_perf_mon_sec.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB0_BASE 0x12080000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB0_LIMIT 0x12080fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB0_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB0_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB1_BASE 0x12081000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB1_LIMIT 0x12081fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB1_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB1_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB2_BASE 0x12082000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB2_LIMIT 0x12082fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB2_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB2_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB3_BASE 0x12083000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB3_LIMIT 0x12083fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB3_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB3_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB4_BASE 0x12084000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB4_LIMIT 0x12084fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB4_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB4_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB5_BASE 0x12085000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB5_LIMIT 0x12085fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB5_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB5_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB6_BASE 0x12086000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB6_LIMIT 0x12086fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB6_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB6_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB7_BASE 0x12087000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB7_LIMIT 0x12087fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB7_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB7_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB8_BASE 0x12088000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB8_LIMIT 0x12088fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB8_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB8_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB9_BASE 0x12089000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB9_LIMIT 0x12089fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB9_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB9_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB10_BASE 0x1208a000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB10_LIMIT 0x1208afff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB10_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB10_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB11_BASE 0x1208b000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB11_LIMIT 0x1208bfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB11_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB11_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB12_BASE 0x1208c000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB12_LIMIT 0x1208cfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB12_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB12_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB13_BASE 0x1208d000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB13_LIMIT 0x1208dfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB13_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB13_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB14_BASE 0x1208e000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB14_LIMIT 0x1208efff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB14_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB14_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB15_BASE 0x1208f000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB15_LIMIT 0x1208ffff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB15_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB15_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB16_BASE 0x12090000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB16_LIMIT 0x12090fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB16_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB16_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB17_BASE 0x12091000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB17_LIMIT 0x12091fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB17_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB17_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB18_BASE 0x12092000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB18_LIMIT 0x12092fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB18_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB18_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB19_BASE 0x12093000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB19_LIMIT 0x12093fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB19_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB19_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB20_BASE 0x12094000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB20_LIMIT 0x12094fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB20_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB20_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB21_BASE 0x12095000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB21_LIMIT 0x12095fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB21_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB21_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB22_BASE 0x12096000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB22_LIMIT 0x12096fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB22_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB22_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB23_BASE 0x12097000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB23_LIMIT 0x12097fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB23_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB23_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB24_BASE 0x12098000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB24_LIMIT 0x12098fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB24_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB24_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB25_BASE 0x12099000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB25_LIMIT 0x12099fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB25_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB25_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB26_BASE 0x1209a000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB26_LIMIT 0x1209afff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB26_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB26_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB27_BASE 0x1209b000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB27_LIMIT 0x1209bfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB27_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB27_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB28_BASE 0x1209c000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB28_LIMIT 0x1209cfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB28_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB28_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB29_BASE 0x1209d000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB29_LIMIT 0x1209dfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB29_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB29_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB30_BASE 0x1209e000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB30_LIMIT 0x1209efff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB30_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB30_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB31_BASE 0x1209f000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB31_LIMIT 0x1209ffff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB31_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB31_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB32_BASE 0x120a0000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB32_LIMIT 0x120a0fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB32_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB32_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB33_BASE 0x120a1000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB33_LIMIT 0x120a1fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB33_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB33_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB34_BASE 0x120a2000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB34_LIMIT 0x120a2fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB34_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB34_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB35_BASE 0x120a3000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB35_LIMIT 0x120a3fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB35_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB35_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB36_BASE 0x120a4000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB36_LIMIT 0x120a4fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB36_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB36_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB37_BASE 0x120a5000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB37_LIMIT 0x120a5fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB37_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB37_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB38_BASE 0x120a6000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB38_LIMIT 0x120a6fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB38_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB38_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB39_BASE 0x120a7000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB39_LIMIT 0x120a7fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB39_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB39_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB40_BASE 0x120a8000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB40_LIMIT 0x120a8fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB40_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB40_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB41_BASE 0x120a9000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB41_LIMIT 0x120a9fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB41_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB41_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB42_BASE 0x120aa000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB42_LIMIT 0x120aafff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB42_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB42_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB43_BASE 0x120ab000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB43_LIMIT 0x120abfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB43_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB43_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB44_BASE 0x120ac000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB44_LIMIT 0x120acfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB44_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB44_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB45_BASE 0x120ad000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB45_LIMIT 0x120adfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB45_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB45_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB46_BASE 0x120ae000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB46_LIMIT 0x120aefff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB46_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB46_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB47_BASE 0x120af000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB47_LIMIT 0x120affff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB47_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB47_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB48_BASE 0x120b0000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB48_LIMIT 0x120b0fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB48_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB48_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB49_BASE 0x120b1000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB49_LIMIT 0x120b1fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB49_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB49_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB50_BASE 0x120b2000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB50_LIMIT 0x120b2fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB50_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB50_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB51_BASE 0x120b3000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB51_LIMIT 0x120b3fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB51_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB51_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB52_BASE 0x120b4000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB52_LIMIT 0x120b4fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB52_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB52_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB53_BASE 0x120b5000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB53_LIMIT 0x120b5fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB53_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB53_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB54_BASE 0x120b6000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB54_LIMIT 0x120b6fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB54_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB54_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB55_BASE 0x120b7000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB55_LIMIT 0x120b7fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB55_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB55_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB56_BASE 0x120b8000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB56_LIMIT 0x120b8fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB56_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB56_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB57_BASE 0x120b9000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB57_LIMIT 0x120b9fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB57_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB57_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB58_BASE 0x120ba000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB58_LIMIT 0x120bafff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB58_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB58_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB59_BASE 0x120bb000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB59_LIMIT 0x120bbfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB59_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB59_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB60_BASE 0x120bc000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB60_LIMIT 0x120bcfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB60_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB60_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB61_BASE 0x120bd000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB61_LIMIT 0x120bdfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB61_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB61_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB62_BASE 0x120be000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB62_LIMIT 0x120befff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB62_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB62_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB63_BASE 0x120bf000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB63_LIMIT 0x120bffff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB63_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB63_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB64_BASE 0x120c0000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB64_LIMIT 0x120c0fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB64_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB64_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB65_BASE 0x120c1000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB65_LIMIT 0x120c1fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB65_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB65_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB66_BASE 0x120c2000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB66_LIMIT 0x120c2fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB66_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB66_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB67_BASE 0x120c3000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB67_LIMIT 0x120c3fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB67_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB67_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB68_BASE 0x120c4000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB68_LIMIT 0x120c4fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB68_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB68_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB69_BASE 0x120c5000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB69_LIMIT 0x120c5fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB69_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB69_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB70_BASE 0x120c6000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB70_LIMIT 0x120c6fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB70_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB70_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB71_BASE 0x120c7000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB71_LIMIT 0x120c7fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB71_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB71_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB72_BASE 0x120c8000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB72_LIMIT 0x120c8fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB72_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB72_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB73_BASE 0x120c9000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB73_LIMIT 0x120c9fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB73_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB73_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB74_BASE 0x120ca000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB74_LIMIT 0x120cafff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB74_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB74_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB75_BASE 0x120cb000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB75_LIMIT 0x120cbfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB75_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB75_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB76_BASE 0x120cc000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB76_LIMIT 0x120ccfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB76_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB76_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB77_BASE 0x120cd000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB77_LIMIT 0x120cdfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB77_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB77_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB78_BASE 0x120ce000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB78_LIMIT 0x120cefff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB78_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB78_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB79_BASE 0x120cf000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB79_LIMIT 0x120cffff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB79_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB79_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB80_BASE 0x120d0000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB80_LIMIT 0x120d0fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB80_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB80_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB81_BASE 0x120d1000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB81_LIMIT 0x120d1fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB81_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB81_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB82_BASE 0x120d2000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB82_LIMIT 0x120d2fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB82_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB82_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB83_BASE 0x120d3000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB83_LIMIT 0x120d3fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB83_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB83_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB84_BASE 0x120d4000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB84_LIMIT 0x120d4fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB84_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB84_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB85_BASE 0x120d5000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB85_LIMIT 0x120d5fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB85_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB85_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB86_BASE 0x120d6000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB86_LIMIT 0x120d6fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB86_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB86_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB87_BASE 0x120d7000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB87_LIMIT 0x120d7fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB87_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB87_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB88_BASE 0x120d8000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB88_LIMIT 0x120d8fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB88_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB88_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB89_BASE 0x120d9000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB89_LIMIT 0x120d9fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB89_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB89_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB90_BASE 0x120da000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB90_LIMIT 0x120dafff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB90_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB90_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB91_BASE 0x120db000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB91_LIMIT 0x120dbfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB91_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB91_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB92_BASE 0x120dc000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB92_LIMIT 0x120dcfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB92_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB92_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB93_BASE 0x120dd000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB93_LIMIT 0x120ddfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB93_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB93_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB94_BASE 0x120de000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB94_LIMIT 0x120defff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB94_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB94_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB95_BASE 0x120df000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB95_LIMIT 0x120dffff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB95_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB95_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB96_BASE 0x120e0000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB96_LIMIT 0x120e0fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB96_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB96_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB97_BASE 0x120e1000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB97_LIMIT 0x120e1fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB97_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB97_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB98_BASE 0x120e2000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB98_LIMIT 0x120e2fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB98_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB98_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB99_BASE 0x120e3000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB99_LIMIT 0x120e3fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB99_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB99_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB100_BASE 0x120e4000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB100_LIMIT 0x120e4fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB100_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB100_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB101_BASE 0x120e5000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB101_LIMIT 0x120e5fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB101_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB101_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB102_BASE 0x120e6000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB102_LIMIT 0x120e6fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB102_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB102_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB103_BASE 0x120e7000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB103_LIMIT 0x120e7fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB103_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB103_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB104_BASE 0x120e8000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB104_LIMIT 0x120e8fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB104_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB104_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB105_BASE 0x120e9000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB105_LIMIT 0x120e9fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB105_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB105_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB106_BASE 0x120ea000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB106_LIMIT 0x120eafff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB106_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB106_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB107_BASE 0x120eb000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB107_LIMIT 0x120ebfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB107_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB107_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB108_BASE 0x120ec000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB108_LIMIT 0x120ecfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB108_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB108_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB109_BASE 0x120ed000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB109_LIMIT 0x120edfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB109_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB109_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB110_BASE 0x120ee000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB110_LIMIT 0x120eefff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB110_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB110_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB111_BASE 0x120ef000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB111_LIMIT 0x120effff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB111_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB111_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB112_BASE 0x120f0000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB112_LIMIT 0x120f0fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB112_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB112_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB113_BASE 0x120f1000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB113_LIMIT 0x120f1fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB113_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB113_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB114_BASE 0x120f2000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB114_LIMIT 0x120f2fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB114_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB114_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB115_BASE 0x120f3000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB115_LIMIT 0x120f3fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB115_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB115_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB116_BASE 0x120f4000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB116_LIMIT 0x120f4fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB116_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB116_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB117_BASE 0x120f5000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB117_LIMIT 0x120f5fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB117_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB117_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB118_BASE 0x120f6000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB118_LIMIT 0x120f6fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB118_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB118_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB119_BASE 0x120f7000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB119_LIMIT 0x120f7fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB119_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB119_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB120_BASE 0x120f8000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB120_LIMIT 0x120f8fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB120_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB120_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB121_BASE 0x120f9000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB121_LIMIT 0x120f9fff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB121_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB121_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB122_BASE 0x120fa000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB122_LIMIT 0x120fafff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB122_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB122_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB123_BASE 0x120fb000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB123_LIMIT 0x120fbfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB123_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB123_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB124_BASE 0x120fc000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB124_LIMIT 0x120fcfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB124_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB124_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB125_BASE 0x120fd000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB125_LIMIT 0x120fdfff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB125_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB125_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB126_BASE 0x120fe000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB126_LIMIT 0x120fefff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB126_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB126_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB127_BASE 0x120ff000
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB127_LIMIT 0x120fffff
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB127_ADDR_LOCALITY SYSTEM_CFG.SMMU0_4KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.0
+#define NV_ADDRESS_MAP_SMMU0_4KB_PAGESIZE_CB127_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB0_BASE 0x12800000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB0_LIMIT 0x1280ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB0_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB0_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB1_BASE 0x12810000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB1_LIMIT 0x1281ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB1_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB1_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB2_BASE 0x12820000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB2_LIMIT 0x1282ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB2_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB2_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB3_BASE 0x12830000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB3_LIMIT 0x1283ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB3_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB3_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB4_BASE 0x12840000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB4_LIMIT 0x1284ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB4_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB4_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB5_BASE 0x12850000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB5_LIMIT 0x1285ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB5_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB5_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB6_BASE 0x12860000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB6_LIMIT 0x1286ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB6_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB6_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB7_BASE 0x12870000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB7_LIMIT 0x1287ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB7_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB7_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB8_BASE 0x12880000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB8_LIMIT 0x1288ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB8_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB8_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB9_BASE 0x12890000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB9_LIMIT 0x1289ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB9_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB9_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB10_BASE 0x128a0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB10_LIMIT 0x128affff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB10_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB10_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB11_BASE 0x128b0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB11_LIMIT 0x128bffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB11_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB11_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB12_BASE 0x128c0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB12_LIMIT 0x128cffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB12_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB12_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB13_BASE 0x128d0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB13_LIMIT 0x128dffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB13_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB13_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB14_BASE 0x128e0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB14_LIMIT 0x128effff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB14_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB14_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB15_BASE 0x128f0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB15_LIMIT 0x128fffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB15_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB15_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB16_BASE 0x12900000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB16_LIMIT 0x1290ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB16_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB16_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB17_BASE 0x12910000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB17_LIMIT 0x1291ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB17_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB17_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB18_BASE 0x12920000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB18_LIMIT 0x1292ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB18_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB18_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB19_BASE 0x12930000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB19_LIMIT 0x1293ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB19_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB19_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB20_BASE 0x12940000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB20_LIMIT 0x1294ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB20_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB20_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB21_BASE 0x12950000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB21_LIMIT 0x1295ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB21_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB21_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB22_BASE 0x12960000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB22_LIMIT 0x1296ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB22_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB22_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB23_BASE 0x12970000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB23_LIMIT 0x1297ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB23_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB23_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB24_BASE 0x12980000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB24_LIMIT 0x1298ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB24_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB24_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB25_BASE 0x12990000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB25_LIMIT 0x1299ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB25_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB25_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB26_BASE 0x129a0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB26_LIMIT 0x129affff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB26_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB26_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB27_BASE 0x129b0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB27_LIMIT 0x129bffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB27_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB27_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB28_BASE 0x129c0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB28_LIMIT 0x129cffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB28_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB28_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB29_BASE 0x129d0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB29_LIMIT 0x129dffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB29_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB29_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB30_BASE 0x129e0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB30_LIMIT 0x129effff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB30_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB30_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB31_BASE 0x129f0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB31_LIMIT 0x129fffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB31_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB31_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB32_BASE 0x12a00000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB32_LIMIT 0x12a0ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB32_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB32_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB33_BASE 0x12a10000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB33_LIMIT 0x12a1ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB33_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB33_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB34_BASE 0x12a20000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB34_LIMIT 0x12a2ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB34_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB34_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB35_BASE 0x12a30000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB35_LIMIT 0x12a3ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB35_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB35_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB36_BASE 0x12a40000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB36_LIMIT 0x12a4ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB36_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB36_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB37_BASE 0x12a50000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB37_LIMIT 0x12a5ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB37_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB37_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB38_BASE 0x12a60000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB38_LIMIT 0x12a6ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB38_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB38_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB39_BASE 0x12a70000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB39_LIMIT 0x12a7ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB39_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB39_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB40_BASE 0x12a80000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB40_LIMIT 0x12a8ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB40_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB40_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB41_BASE 0x12a90000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB41_LIMIT 0x12a9ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB41_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB41_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB42_BASE 0x12aa0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB42_LIMIT 0x12aaffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB42_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB42_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB43_BASE 0x12ab0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB43_LIMIT 0x12abffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB43_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB43_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB44_BASE 0x12ac0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB44_LIMIT 0x12acffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB44_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB44_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB45_BASE 0x12ad0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB45_LIMIT 0x12adffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB45_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB45_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB46_BASE 0x12ae0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB46_LIMIT 0x12aeffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB46_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB46_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB47_BASE 0x12af0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB47_LIMIT 0x12afffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB47_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB47_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB48_BASE 0x12b00000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB48_LIMIT 0x12b0ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB48_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB48_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB49_BASE 0x12b10000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB49_LIMIT 0x12b1ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB49_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB49_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB50_BASE 0x12b20000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB50_LIMIT 0x12b2ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB50_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB50_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB51_BASE 0x12b30000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB51_LIMIT 0x12b3ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB51_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB51_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB52_BASE 0x12b40000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB52_LIMIT 0x12b4ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB52_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB52_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB53_BASE 0x12b50000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB53_LIMIT 0x12b5ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB53_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB53_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB54_BASE 0x12b60000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB54_LIMIT 0x12b6ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB54_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB54_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB55_BASE 0x12b70000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB55_LIMIT 0x12b7ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB55_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB55_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB56_BASE 0x12b80000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB56_LIMIT 0x12b8ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB56_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB56_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB57_BASE 0x12b90000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB57_LIMIT 0x12b9ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB57_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB57_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB58_BASE 0x12ba0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB58_LIMIT 0x12baffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB58_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB58_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB59_BASE 0x12bb0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB59_LIMIT 0x12bbffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB59_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB59_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB60_BASE 0x12bc0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB60_LIMIT 0x12bcffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB60_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB60_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB61_BASE 0x12bd0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB61_LIMIT 0x12bdffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB61_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB61_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB62_BASE 0x12be0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB62_LIMIT 0x12beffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB62_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB62_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB63_BASE 0x12bf0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB63_LIMIT 0x12bfffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB63_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB63_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB64_BASE 0x12c00000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB64_LIMIT 0x12c0ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB64_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB64_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB65_BASE 0x12c10000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB65_LIMIT 0x12c1ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB65_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB65_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB66_BASE 0x12c20000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB66_LIMIT 0x12c2ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB66_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB66_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB67_BASE 0x12c30000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB67_LIMIT 0x12c3ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB67_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB67_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB68_BASE 0x12c40000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB68_LIMIT 0x12c4ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB68_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB68_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB69_BASE 0x12c50000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB69_LIMIT 0x12c5ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB69_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB69_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB70_BASE 0x12c60000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB70_LIMIT 0x12c6ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB70_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB70_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB71_BASE 0x12c70000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB71_LIMIT 0x12c7ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB71_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB71_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB72_BASE 0x12c80000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB72_LIMIT 0x12c8ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB72_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB72_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB73_BASE 0x12c90000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB73_LIMIT 0x12c9ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB73_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB73_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB74_BASE 0x12ca0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB74_LIMIT 0x12caffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB74_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB74_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB75_BASE 0x12cb0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB75_LIMIT 0x12cbffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB75_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB75_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB76_BASE 0x12cc0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB76_LIMIT 0x12ccffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB76_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB76_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB77_BASE 0x12cd0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB77_LIMIT 0x12cdffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB77_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB77_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB78_BASE 0x12ce0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB78_LIMIT 0x12ceffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB78_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB78_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB79_BASE 0x12cf0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB79_LIMIT 0x12cfffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB79_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB79_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB80_BASE 0x12d00000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB80_LIMIT 0x12d0ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB80_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB80_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB81_BASE 0x12d10000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB81_LIMIT 0x12d1ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB81_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB81_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB82_BASE 0x12d20000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB82_LIMIT 0x12d2ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB82_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB82_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB83_BASE 0x12d30000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB83_LIMIT 0x12d3ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB83_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB83_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB84_BASE 0x12d40000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB84_LIMIT 0x12d4ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB84_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB84_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB85_BASE 0x12d50000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB85_LIMIT 0x12d5ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB85_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB85_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB86_BASE 0x12d60000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB86_LIMIT 0x12d6ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB86_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB86_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB87_BASE 0x12d70000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB87_LIMIT 0x12d7ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB87_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB87_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB88_BASE 0x12d80000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB88_LIMIT 0x12d8ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB88_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB88_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB89_BASE 0x12d90000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB89_LIMIT 0x12d9ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB89_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB89_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB90_BASE 0x12da0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB90_LIMIT 0x12daffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB90_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB90_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB91_BASE 0x12db0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB91_LIMIT 0x12dbffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB91_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB91_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB92_BASE 0x12dc0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB92_LIMIT 0x12dcffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB92_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB92_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB93_BASE 0x12dd0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB93_LIMIT 0x12ddffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB93_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB93_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB94_BASE 0x12de0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB94_LIMIT 0x12deffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB94_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB94_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB95_BASE 0x12df0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB95_LIMIT 0x12dfffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB95_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB95_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB96_BASE 0x12e00000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB96_LIMIT 0x12e0ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB96_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB96_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB97_BASE 0x12e10000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB97_LIMIT 0x12e1ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB97_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB97_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB98_BASE 0x12e20000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB98_LIMIT 0x12e2ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB98_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB98_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB99_BASE 0x12e30000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB99_LIMIT 0x12e3ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB99_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB99_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB100_BASE 0x12e40000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB100_LIMIT 0x12e4ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB100_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB100_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB101_BASE 0x12e50000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB101_LIMIT 0x12e5ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB101_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB101_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB102_BASE 0x12e60000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB102_LIMIT 0x12e6ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB102_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB102_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB103_BASE 0x12e70000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB103_LIMIT 0x12e7ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB103_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB103_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB104_BASE 0x12e80000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB104_LIMIT 0x12e8ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB104_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB104_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB105_BASE 0x12e90000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB105_LIMIT 0x12e9ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB105_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB105_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB106_BASE 0x12ea0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB106_LIMIT 0x12eaffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB106_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB106_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB107_BASE 0x12eb0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB107_LIMIT 0x12ebffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB107_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB107_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB108_BASE 0x12ec0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB108_LIMIT 0x12ecffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB108_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB108_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB109_BASE 0x12ed0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB109_LIMIT 0x12edffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB109_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB109_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB110_BASE 0x12ee0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB110_LIMIT 0x12eeffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB110_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB110_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB111_BASE 0x12ef0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB111_LIMIT 0x12efffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB111_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB111_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB112_BASE 0x12f00000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB112_LIMIT 0x12f0ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB112_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB112_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB113_BASE 0x12f10000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB113_LIMIT 0x12f1ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB113_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB113_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB114_BASE 0x12f20000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB114_LIMIT 0x12f2ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB114_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB114_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB115_BASE 0x12f30000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB115_LIMIT 0x12f3ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB115_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB115_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB116_BASE 0x12f40000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB116_LIMIT 0x12f4ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB116_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB116_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB117_BASE 0x12f50000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB117_LIMIT 0x12f5ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB117_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB117_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB118_BASE 0x12f60000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB118_LIMIT 0x12f6ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB118_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB118_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB119_BASE 0x12f70000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB119_LIMIT 0x12f7ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB119_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB119_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB120_BASE 0x12f80000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB120_LIMIT 0x12f8ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB120_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB120_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB121_BASE 0x12f90000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB121_LIMIT 0x12f9ffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB121_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB121_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB122_BASE 0x12fa0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB122_LIMIT 0x12faffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB122_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB122_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB123_BASE 0x12fb0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB123_LIMIT 0x12fbffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB123_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB123_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB124_BASE 0x12fc0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB124_LIMIT 0x12fcffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB124_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB124_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB125_BASE 0x12fd0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB125_LIMIT 0x12fdffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB125_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB125_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB126_BASE 0x12fe0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB126_LIMIT 0x12feffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB126_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB126_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB127_BASE 0x12ff0000
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB127_LIMIT 0x12ffffff
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB127_ADDR_LOCALITY SYSTEM_CFG.SMMU0_64KB_PAGESIZE_GR0.ARM_SMMU_GSR0_SACR_0.PAGESIZE.1
+#define NV_ADDRESS_MAP_SMMU0_64KB_PAGESIZE_CB127_HEADER arm_smmu_500_context.h
+
+#define NV_ADDRESS_MAP_DISP_CORE_1_BASE 0x13800000
+#define NV_ADDRESS_MAP_DISP_CORE_1_LIMIT 0x1383ffff
+#define NV_ADDRESS_MAP_DISP_CORE_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DISP_CORE_1_HEADER
+
+#define NV_ADDRESS_MAP_DISP_EC_BASE 0x13840000
+#define NV_ADDRESS_MAP_DISP_EC_LIMIT 0x13840fff
+#define NV_ADDRESS_MAP_DISP_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DISP_EC_HEADER
+
+#define NV_ADDRESS_MAP_DISP_CORE_2_BASE 0x13841000
+#define NV_ADDRESS_MAP_DISP_CORE_2_LIMIT 0x138effff
+#define NV_ADDRESS_MAP_DISP_CORE_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DISP_CORE_2_HEADER
+
+#define NV_ADDRESS_MAP_CBB_CENTRAL_CBB_PROG_AMAP_BASE 0x13a00000
+#define NV_ADDRESS_MAP_CBB_CENTRAL_CBB_PROG_AMAP_LIMIT 0x13a0ffff
+#define NV_ADDRESS_MAP_CBB_CENTRAL_CBB_PROG_AMAP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_CENTRAL_CBB_PROG_AMAP_HEADER
+
+#define NV_ADDRESS_MAP_CBB_MN_AON_BASE 0x13a30000
+#define NV_ADDRESS_MAP_CBB_MN_AON_LIMIT 0x13a30fff
+#define NV_ADDRESS_MAP_CBB_MN_AON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_MN_AON_HEADER
+
+#define NV_ADDRESS_MAP_CBB_MN_APE_BASE 0x13a31000
+#define NV_ADDRESS_MAP_CBB_MN_APE_LIMIT 0x13a31fff
+#define NV_ADDRESS_MAP_CBB_MN_APE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_MN_APE_HEADER
+
+#define NV_ADDRESS_MAP_CBB_MN_BPMP_BASE 0x13a32000
+#define NV_ADDRESS_MAP_CBB_MN_BPMP_LIMIT 0x13a32fff
+#define NV_ADDRESS_MAP_CBB_MN_BPMP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_MN_BPMP_HEADER
+
+#define NV_ADDRESS_MAP_CBB_MN_CBB_CENTRAL_BASE 0x13a34000
+#define NV_ADDRESS_MAP_CBB_MN_CBB_CENTRAL_LIMIT 0x13a34fff
+#define NV_ADDRESS_MAP_CBB_MN_CBB_CENTRAL_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_MN_CBB_CENTRAL_HEADER
+
+#define NV_ADDRESS_MAP_CBB_MN_CORESIGHT_BASE 0x13a35000
+#define NV_ADDRESS_MAP_CBB_MN_CORESIGHT_LIMIT 0x13a35fff
+#define NV_ADDRESS_MAP_CBB_MN_CORESIGHT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_MN_CORESIGHT_HEADER
+
+#define NV_ADDRESS_MAP_CBB_MN_GPCDMA_MMIO_BASE 0x13a36000
+#define NV_ADDRESS_MAP_CBB_MN_GPCDMA_MMIO_LIMIT 0x13a36fff
+#define NV_ADDRESS_MAP_CBB_MN_GPCDMA_MMIO_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_MN_GPCDMA_MMIO_HEADER
+
+#define NV_ADDRESS_MAP_CBB_MN_JTAG_BASE 0x13a37000
+#define NV_ADDRESS_MAP_CBB_MN_JTAG_LIMIT 0x13a37fff
+#define NV_ADDRESS_MAP_CBB_MN_JTAG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_MN_JTAG_HEADER
+
+#define NV_ADDRESS_MAP_CBB_MN_CCPLEX_BASE 0x13a3a000
+#define NV_ADDRESS_MAP_CBB_MN_CCPLEX_LIMIT 0x13a3afff
+#define NV_ADDRESS_MAP_CBB_MN_CCPLEX_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_MN_CCPLEX_HEADER
+
+#define NV_ADDRESS_MAP_CBB_MN_NVDEC_BASE 0x13a3b000
+#define NV_ADDRESS_MAP_CBB_MN_NVDEC_LIMIT 0x13a3bfff
+#define NV_ADDRESS_MAP_CBB_MN_NVDEC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_MN_NVDEC_HEADER
+
+#define NV_ADDRESS_MAP_CBB_MN_DCE_BASE 0x13a3c000
+#define NV_ADDRESS_MAP_CBB_MN_DCE_LIMIT 0x13a3cfff
+#define NV_ADDRESS_MAP_CBB_MN_DCE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_MN_DCE_HEADER
+
+#define NV_ADDRESS_MAP_CBB_MN_RCE_BASE 0x13a3d000
+#define NV_ADDRESS_MAP_CBB_MN_RCE_LIMIT 0x13a3dfff
+#define NV_ADDRESS_MAP_CBB_MN_RCE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_MN_RCE_HEADER
+
+#define NV_ADDRESS_MAP_CBB_MN_SCE_BASE 0x13a3e000
+#define NV_ADDRESS_MAP_CBB_MN_SCE_LIMIT 0x13a3efff
+#define NV_ADDRESS_MAP_CBB_MN_SCE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_MN_SCE_HEADER
+
+#define NV_ADDRESS_MAP_CBB_MN_CBB_CENTRAL_1_BASE 0x13a3f000
+#define NV_ADDRESS_MAP_CBB_MN_CBB_CENTRAL_1_LIMIT 0x13a3ffff
+#define NV_ADDRESS_MAP_CBB_MN_CBB_CENTRAL_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_MN_CBB_CENTRAL_1_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AON_SLAVE_BASE 0x13a40000
+#define NV_ADDRESS_MAP_CBB_SN_AON_SLAVE_LIMIT 0x13a40fff
+#define NV_ADDRESS_MAP_CBB_SN_AON_SLAVE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AON_SLAVE_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_BPMP_SLAVE_BASE 0x13a41000
+#define NV_ADDRESS_MAP_CBB_SN_BPMP_SLAVE_LIMIT 0x13a41fff
+#define NV_ADDRESS_MAP_CBB_SN_BPMP_SLAVE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_BPMP_SLAVE_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_CBB_CENTRAL_BASE 0x13a42000
+#define NV_ADDRESS_MAP_CBB_SN_CBB_CENTRAL_LIMIT 0x13a42fff
+#define NV_ADDRESS_MAP_CBB_SN_CBB_CENTRAL_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_CBB_CENTRAL_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_HOST1X_BASE 0x13a43000
+#define NV_ADDRESS_MAP_CBB_SN_HOST1X_LIMIT 0x13a43fff
+#define NV_ADDRESS_MAP_CBB_SN_HOST1X_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_HOST1X_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_STM_BASE 0x13a44000
+#define NV_ADDRESS_MAP_CBB_SN_STM_LIMIT 0x13a44fff
+#define NV_ADDRESS_MAP_CBB_SN_STM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_STM_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C1_BASE 0x13a47000
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C1_LIMIT 0x13a47fff
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C1_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C2_BASE 0x13a48000
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C2_LIMIT 0x13a48fff
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C2_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C3_BASE 0x13a49000
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C3_LIMIT 0x13a49fff
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C3_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C0_BASE 0x13a4a000
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C0_LIMIT 0x13a4afff
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C0_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C4_BASE 0x13a4b000
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C4_LIMIT 0x13a4bfff
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C4_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_GPU_BASE 0x13a4c000
+#define NV_ADDRESS_MAP_CBB_SN_GPU_LIMIT 0x13a4cfff
+#define NV_ADDRESS_MAP_CBB_SN_GPU_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_GPU_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_SMMU0_BASE 0x13a4d000
+#define NV_ADDRESS_MAP_CBB_SN_SMMU0_LIMIT 0x13a4dfff
+#define NV_ADDRESS_MAP_CBB_SN_SMMU0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_SMMU0_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_SMMU1_BASE 0x13a4e000
+#define NV_ADDRESS_MAP_CBB_SN_SMMU1_LIMIT 0x13a4efff
+#define NV_ADDRESS_MAP_CBB_SN_SMMU1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_SMMU1_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_SMMU2_BASE 0x13a4f000
+#define NV_ADDRESS_MAP_CBB_SN_SMMU2_LIMIT 0x13a4ffff
+#define NV_ADDRESS_MAP_CBB_SN_SMMU2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_SMMU2_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_SMMU3_BASE 0x13a50000
+#define NV_ADDRESS_MAP_CBB_SN_SMMU3_LIMIT 0x13a50fff
+#define NV_ADDRESS_MAP_CBB_SN_SMMU3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_SMMU3_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_SMMU4_BASE 0x13a51000
+#define NV_ADDRESS_MAP_CBB_SN_SMMU4_LIMIT 0x13a51fff
+#define NV_ADDRESS_MAP_CBB_SN_SMMU4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_SMMU4_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C10_BASE 0x13a52000
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C10_LIMIT 0x13a52fff
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C10_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C10_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C7_BASE 0x13a53000
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C7_LIMIT 0x13a53fff
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C7_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C8_BASE 0x13a54000
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C8_LIMIT 0x13a54fff
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C8_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C8_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C9_BASE 0x13a55000
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C9_LIMIT 0x13a55fff
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C9_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C9_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C5_BASE 0x13a56000
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C5_LIMIT 0x13a56fff
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C5_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C6_BASE 0x13a57000
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C6_LIMIT 0x13a57fff
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_PCIE_C6_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_DCE_SLAVE_BASE 0x13a58000
+#define NV_ADDRESS_MAP_CBB_SN_DCE_SLAVE_LIMIT 0x13a58fff
+#define NV_ADDRESS_MAP_CBB_SN_DCE_SLAVE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_DCE_SLAVE_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_RCE_SLAVE_BASE 0x13a59000
+#define NV_ADDRESS_MAP_CBB_SN_RCE_SLAVE_LIMIT 0x13a59fff
+#define NV_ADDRESS_MAP_CBB_SN_RCE_SLAVE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_RCE_SLAVE_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_SCE_SLAVE_BASE 0x13a5a000
+#define NV_ADDRESS_MAP_CBB_SN_SCE_SLAVE_LIMIT 0x13a5afff
+#define NV_ADDRESS_MAP_CBB_SN_SCE_SLAVE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_SCE_SLAVE_HEADER
+
+#define NV_ADDRESS_MAP_CBB_EN_CFG_BASE 0x13a60000
+#define NV_ADDRESS_MAP_CBB_EN_CFG_LIMIT 0x13a60fff
+#define NV_ADDRESS_MAP_CBB_EN_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_EN_CFG_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_1_BASE 0x13a70000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_1_LIMIT 0x13a70fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_1_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_10_BASE 0x13a71000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_10_LIMIT 0x13a71fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_10_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_10_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_11_BASE 0x13a72000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_11_LIMIT 0x13a72fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_11_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_11_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_12_BASE 0x13a73000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_12_LIMIT 0x13a73fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_12_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_12_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_13_BASE 0x13a74000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_13_LIMIT 0x13a74fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_13_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_13_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_14_BASE 0x13a75000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_14_LIMIT 0x13a75fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_14_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_14_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_15_BASE 0x13a76000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_15_LIMIT 0x13a76fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_15_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_15_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_16_BASE 0x13a77000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_16_LIMIT 0x13a77fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_16_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_16_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_17_BASE 0x13a78000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_17_LIMIT 0x13a78fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_17_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_17_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_18_BASE 0x13a79000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_18_LIMIT 0x13a79fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_18_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_18_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_19_BASE 0x13a7a000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_19_LIMIT 0x13a7afff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_19_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_19_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_2_BASE 0x13a7b000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_2_LIMIT 0x13a7bfff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_2_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_20_BASE 0x13a7c000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_20_LIMIT 0x13a7cfff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_20_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_20_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_21_BASE 0x13a7d000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_21_LIMIT 0x13a7dfff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_21_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_21_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_22_BASE 0x13a7e000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_22_LIMIT 0x13a7efff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_22_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_22_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_23_BASE 0x13a7f000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_23_LIMIT 0x13a7ffff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_23_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_23_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_25_BASE 0x13a80000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_25_LIMIT 0x13a80fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_25_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_25_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_26_BASE 0x13a81000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_26_LIMIT 0x13a81fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_26_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_26_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_27_BASE 0x13a82000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_27_LIMIT 0x13a82fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_27_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_27_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_28_BASE 0x13a83000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_28_LIMIT 0x13a83fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_28_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_28_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_29_BASE 0x13a84000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_29_LIMIT 0x13a84fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_29_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_29_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_30_BASE 0x13a85000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_30_LIMIT 0x13a85fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_30_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_30_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_31_BASE 0x13a86000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_31_LIMIT 0x13a86fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_31_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_31_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_32_BASE 0x13a87000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_32_LIMIT 0x13a87fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_32_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_32_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_33_BASE 0x13a88000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_33_LIMIT 0x13a88fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_33_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_33_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_34_BASE 0x13a89000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_34_LIMIT 0x13a89fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_34_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_34_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_4_BASE 0x13a8b000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_4_LIMIT 0x13a8bfff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_4_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_5_BASE 0x13a8c000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_5_LIMIT 0x13a8cfff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_5_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_6_BASE 0x13a8d000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_6_LIMIT 0x13a8dfff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_6_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_7_BASE 0x13a8e000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_7_LIMIT 0x13a8efff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_7_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_8_BASE 0x13a8f000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_8_LIMIT 0x13a8ffff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_8_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_8_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_9_BASE 0x13a90000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_9_LIMIT 0x13a90fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_9_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_9_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_3_BASE 0x13a91000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_3_LIMIT 0x13a91fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_3_HEADER
+
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_35_BASE 0x13a92000
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_35_LIMIT 0x13a92fff
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_35_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_SN_AXI2APB_35_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_0_BASE 0x13aa0000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_0_LIMIT 0x13aa0fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_0_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_1_BASE 0x13aa1000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_1_LIMIT 0x13aa1fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_1_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_2_BASE 0x13aa2000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_2_LIMIT 0x13aa2fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_2_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_3_BASE 0x13aa3000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_3_LIMIT 0x13aa3fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_3_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_4_BASE 0x13aa4000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_4_LIMIT 0x13aa4fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_4_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_5_BASE 0x13aa5000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_5_LIMIT 0x13aa5fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_5_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_6_BASE 0x13aa6000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_6_LIMIT 0x13aa6fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_6_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_7_BASE 0x13aa7000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_7_LIMIT 0x13aa7fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_7_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_8_BASE 0x13aa8000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_8_LIMIT 0x13aa8fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_8_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_8_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_9_BASE 0x13aa9000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_9_LIMIT 0x13aa9fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_9_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_9_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_10_BASE 0x13aaa000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_10_LIMIT 0x13aaafff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_10_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_10_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_11_BASE 0x13aab000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_11_LIMIT 0x13aabfff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_11_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_11_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_12_BASE 0x13aac000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_12_LIMIT 0x13aacfff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_12_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_12_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_13_BASE 0x13aad000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_13_LIMIT 0x13aadfff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_13_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_13_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_14_BASE 0x13aae000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_14_LIMIT 0x13aaefff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_14_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_14_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_15_BASE 0x13aaf000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_15_LIMIT 0x13aaffff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_15_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_15_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_16_BASE 0x13ab0000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_16_LIMIT 0x13ab0fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_16_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_16_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_17_BASE 0x13ab1000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_17_LIMIT 0x13ab1fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_17_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_17_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_18_BASE 0x13ab2000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_18_LIMIT 0x13ab2fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_18_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_18_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_19_BASE 0x13ab3000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_19_LIMIT 0x13ab3fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_19_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_19_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_20_BASE 0x13ab4000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_20_LIMIT 0x13ab4fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_20_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_20_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_21_BASE 0x13ab5000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_21_LIMIT 0x13ab5fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_21_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_21_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_22_BASE 0x13ab6000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_22_LIMIT 0x13ab6fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_22_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_22_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_23_BASE 0x13ab7000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_23_LIMIT 0x13ab7fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_23_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_23_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_24_BASE 0x13ab8000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_24_LIMIT 0x13ab8fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_24_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_24_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_25_BASE 0x13ab9000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_25_LIMIT 0x13ab9fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_25_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_25_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_26_BASE 0x13aba000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_26_LIMIT 0x13abafff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_26_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_26_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_27_BASE 0x13abb000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_27_LIMIT 0x13abbfff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_27_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_27_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_28_BASE 0x13abc000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_28_LIMIT 0x13abcfff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_28_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_28_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_29_BASE 0x13abd000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_29_LIMIT 0x13abdfff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_29_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_29_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_30_BASE 0x13abe000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_30_LIMIT 0x13abefff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_30_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_30_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_31_BASE 0x13abf000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_31_LIMIT 0x13abffff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_31_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_31_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_32_BASE 0x13ac0000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_32_LIMIT 0x13ac0fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_32_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_32_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_33_BASE 0x13ac1000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_33_LIMIT 0x13ac1fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_33_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_33_HEADER
+
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_34_BASE 0x13ac2000
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_34_LIMIT 0x13ac2fff
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_34_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CBB_ERR_COLLATOR_34_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_COMMON_BASE 0x13e00000
+#define NV_ADDRESS_MAP_HOST1X_COMMON_LIMIT 0x13e0ffff
+#define NV_ADDRESS_MAP_HOST1X_COMMON_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_COMMON_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_HYPERVISOR_BASE 0x13e10000
+#define NV_ADDRESS_MAP_HOST1X_HYPERVISOR_LIMIT 0x13e1ffff
+#define NV_ADDRESS_MAP_HOST1X_HYPERVISOR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_HYPERVISOR_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_R5_CLUSTER_BASE 0x13e20000
+#define NV_ADDRESS_MAP_HOST1X_R5_CLUSTER_LIMIT 0x13e2ffff
+#define NV_ADDRESS_MAP_HOST1X_R5_CLUSTER_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_R5_CLUSTER_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_HSM_BASE 0x13e30000
+#define NV_ADDRESS_MAP_HOST1X_HSM_LIMIT 0x13e3ffff
+#define NV_ADDRESS_MAP_HOST1X_HSM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_HSM_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_0_BASE 0x13e40000
+#define NV_ADDRESS_MAP_HOST1X_0_LIMIT 0x13e4ffff
+#define NV_ADDRESS_MAP_HOST1X_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_0_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_1_BASE 0x13e50000
+#define NV_ADDRESS_MAP_HOST1X_1_LIMIT 0x13e5ffff
+#define NV_ADDRESS_MAP_HOST1X_1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_1_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_2_BASE 0x13e60000
+#define NV_ADDRESS_MAP_HOST1X_2_LIMIT 0x13e6ffff
+#define NV_ADDRESS_MAP_HOST1X_2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_2_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_3_BASE 0x13e70000
+#define NV_ADDRESS_MAP_HOST1X_3_LIMIT 0x13e7ffff
+#define NV_ADDRESS_MAP_HOST1X_3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_3_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_4_BASE 0x13e80000
+#define NV_ADDRESS_MAP_HOST1X_4_LIMIT 0x13e8ffff
+#define NV_ADDRESS_MAP_HOST1X_4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_4_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_5_BASE 0x13e90000
+#define NV_ADDRESS_MAP_HOST1X_5_LIMIT 0x13e9ffff
+#define NV_ADDRESS_MAP_HOST1X_5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_5_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_6_BASE 0x13ea0000
+#define NV_ADDRESS_MAP_HOST1X_6_LIMIT 0x13eaffff
+#define NV_ADDRESS_MAP_HOST1X_6_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_6_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_7_BASE 0x13eb0000
+#define NV_ADDRESS_MAP_HOST1X_7_LIMIT 0x13ebffff
+#define NV_ADDRESS_MAP_HOST1X_7_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_7_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_ACTMON0_BASE 0x13ef0000
+#define NV_ADDRESS_MAP_HOST1X_ACTMON0_LIMIT 0x13efffff
+#define NV_ADDRESS_MAP_HOST1X_ACTMON0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_ACTMON0_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_ACTMON1_BASE 0x13f00000
+#define NV_ADDRESS_MAP_HOST1X_ACTMON1_LIMIT 0x13f0ffff
+#define NV_ADDRESS_MAP_HOST1X_ACTMON1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_ACTMON1_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_ACTMON2_BASE 0x13f10000
+#define NV_ADDRESS_MAP_HOST1X_ACTMON2_LIMIT 0x13f1ffff
+#define NV_ADDRESS_MAP_HOST1X_ACTMON2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_ACTMON2_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_ACTMON3_BASE 0x13f20000
+#define NV_ADDRESS_MAP_HOST1X_ACTMON3_LIMIT 0x13f2ffff
+#define NV_ADDRESS_MAP_HOST1X_ACTMON3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_ACTMON3_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_ACTMON4_BASE 0x13f30000
+#define NV_ADDRESS_MAP_HOST1X_ACTMON4_LIMIT 0x13f3ffff
+#define NV_ADDRESS_MAP_HOST1X_ACTMON4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_ACTMON4_HEADER
+
+#define NV_ADDRESS_MAP_HOST1X_ACTMON5_BASE 0x13f40000
+#define NV_ADDRESS_MAP_HOST1X_ACTMON5_LIMIT 0x13f4ffff
+#define NV_ADDRESS_MAP_HOST1X_ACTMON5_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_HOST1X_ACTMON5_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C8_CTL_NONSECURE_BASE 0x140a0000
+#define NV_ADDRESS_MAP_PCIE_C8_CTL_NONSECURE_LIMIT 0x140affff
+#define NV_ADDRESS_MAP_PCIE_C8_CTL_NONSECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C8_CTL_NONSECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C8_CTL_SECURE_BASE 0x140b0000
+#define NV_ADDRESS_MAP_PCIE_C8_CTL_SECURE_LIMIT 0x140bffff
+#define NV_ADDRESS_MAP_PCIE_C8_CTL_SECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C8_CTL_SECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C9_CTL_NONSECURE_BASE 0x140c0000
+#define NV_ADDRESS_MAP_PCIE_C9_CTL_NONSECURE_LIMIT 0x140cffff
+#define NV_ADDRESS_MAP_PCIE_C9_CTL_NONSECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C9_CTL_NONSECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C9_CTL_SECURE_BASE 0x140d0000
+#define NV_ADDRESS_MAP_PCIE_C9_CTL_SECURE_LIMIT 0x140dffff
+#define NV_ADDRESS_MAP_PCIE_C9_CTL_SECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C9_CTL_SECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C10_CTL_NONSECURE_BASE 0x140e0000
+#define NV_ADDRESS_MAP_PCIE_C10_CTL_NONSECURE_LIMIT 0x140effff
+#define NV_ADDRESS_MAP_PCIE_C10_CTL_NONSECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C10_CTL_NONSECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C10_CTL_SECURE_BASE 0x140f0000
+#define NV_ADDRESS_MAP_PCIE_C10_CTL_SECURE_LIMIT 0x140fffff
+#define NV_ADDRESS_MAP_PCIE_C10_CTL_SECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C10_CTL_SECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C1_CTL_NONSECURE_BASE 0x14100000
+#define NV_ADDRESS_MAP_PCIE_C1_CTL_NONSECURE_LIMIT 0x1410ffff
+#define NV_ADDRESS_MAP_PCIE_C1_CTL_NONSECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C1_CTL_NONSECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C1_CTL_SECURE_BASE 0x14110000
+#define NV_ADDRESS_MAP_PCIE_C1_CTL_SECURE_LIMIT 0x1411ffff
+#define NV_ADDRESS_MAP_PCIE_C1_CTL_SECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C1_CTL_SECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C2_CTL_NONSECURE_BASE 0x14120000
+#define NV_ADDRESS_MAP_PCIE_C2_CTL_NONSECURE_LIMIT 0x1412ffff
+#define NV_ADDRESS_MAP_PCIE_C2_CTL_NONSECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C2_CTL_NONSECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C2_CTL_SECURE_BASE 0x14130000
+#define NV_ADDRESS_MAP_PCIE_C2_CTL_SECURE_LIMIT 0x1413ffff
+#define NV_ADDRESS_MAP_PCIE_C2_CTL_SECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C2_CTL_SECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C3_CTL_NONSECURE_BASE 0x14140000
+#define NV_ADDRESS_MAP_PCIE_C3_CTL_NONSECURE_LIMIT 0x1414ffff
+#define NV_ADDRESS_MAP_PCIE_C3_CTL_NONSECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C3_CTL_NONSECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C3_CTL_SECURE_BASE 0x14150000
+#define NV_ADDRESS_MAP_PCIE_C3_CTL_SECURE_LIMIT 0x1415ffff
+#define NV_ADDRESS_MAP_PCIE_C3_CTL_SECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C3_CTL_SECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C4_CTL_NONSECURE_BASE 0x14160000
+#define NV_ADDRESS_MAP_PCIE_C4_CTL_NONSECURE_LIMIT 0x1416ffff
+#define NV_ADDRESS_MAP_PCIE_C4_CTL_NONSECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C4_CTL_NONSECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C4_CTL_SECURE_BASE 0x14170000
+#define NV_ADDRESS_MAP_PCIE_C4_CTL_SECURE_LIMIT 0x1417ffff
+#define NV_ADDRESS_MAP_PCIE_C4_CTL_SECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C4_CTL_SECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C0_CTL_NONSECURE_BASE 0x14180000
+#define NV_ADDRESS_MAP_PCIE_C0_CTL_NONSECURE_LIMIT 0x1418ffff
+#define NV_ADDRESS_MAP_PCIE_C0_CTL_NONSECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C0_CTL_NONSECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C0_CTL_SECURE_BASE 0x14190000
+#define NV_ADDRESS_MAP_PCIE_C0_CTL_SECURE_LIMIT 0x1419ffff
+#define NV_ADDRESS_MAP_PCIE_C0_CTL_SECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C0_CTL_SECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C5_CTL_NONSECURE_BASE 0x141a0000
+#define NV_ADDRESS_MAP_PCIE_C5_CTL_NONSECURE_LIMIT 0x141affff
+#define NV_ADDRESS_MAP_PCIE_C5_CTL_NONSECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C5_CTL_NONSECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C5_CTL_SECURE_BASE 0x141b0000
+#define NV_ADDRESS_MAP_PCIE_C5_CTL_SECURE_LIMIT 0x141bffff
+#define NV_ADDRESS_MAP_PCIE_C5_CTL_SECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C5_CTL_SECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C6_CTL_NONSECURE_BASE 0x141c0000
+#define NV_ADDRESS_MAP_PCIE_C6_CTL_NONSECURE_LIMIT 0x141cffff
+#define NV_ADDRESS_MAP_PCIE_C6_CTL_NONSECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C6_CTL_NONSECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C6_CTL_SECURE_BASE 0x141d0000
+#define NV_ADDRESS_MAP_PCIE_C6_CTL_SECURE_LIMIT 0x141dffff
+#define NV_ADDRESS_MAP_PCIE_C6_CTL_SECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C6_CTL_SECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C7_CTL_NONSECURE_BASE 0x141e0000
+#define NV_ADDRESS_MAP_PCIE_C7_CTL_NONSECURE_LIMIT 0x141effff
+#define NV_ADDRESS_MAP_PCIE_C7_CTL_NONSECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C7_CTL_NONSECURE_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C7_CTL_SECURE_BASE 0x141f0000
+#define NV_ADDRESS_MAP_PCIE_C7_CTL_SECURE_LIMIT 0x141fffff
+#define NV_ADDRESS_MAP_PCIE_C7_CTL_SECURE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C7_CTL_SECURE_HEADER
+
+#define NV_ADDRESS_MAP_ISP_BASE 0x14800000
+#define NV_ADDRESS_MAP_ISP_LIMIT 0x14afffff
+#define NV_ADDRESS_MAP_ISP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_ISP_HEADER arisp_hostshim.h
+
+#define NV_ADDRESS_MAP_ISP_THI_CPU_BASE 0x14b00000
+#define NV_ADDRESS_MAP_ISP_THI_CPU_LIMIT 0x14b07fff
+#define NV_ADDRESS_MAP_ISP_THI_CPU_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_ISP_THI_CPU_HEADER
+
+#define NV_ADDRESS_MAP_ISP_THI_EC_BASE 0x14b08000
+#define NV_ADDRESS_MAP_ISP_THI_EC_LIMIT 0x14b08fff
+#define NV_ADDRESS_MAP_ISP_THI_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_ISP_THI_EC_HEADER
+
+#define NV_ADDRESS_MAP_ISP_THI_ENGINE_BASE 0x14b09000
+#define NV_ADDRESS_MAP_ISP_THI_ENGINE_LIMIT 0x14bfffff
+#define NV_ADDRESS_MAP_ISP_THI_ENGINE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_ISP_THI_ENGINE_HEADER
+
+#define NV_ADDRESS_MAP_VI2_BASE 0x14c00000
+#define NV_ADDRESS_MAP_VI2_LIMIT 0x14efffff
+#define NV_ADDRESS_MAP_VI2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_VI2_HEADER arvi_fw.h
+
+#define NV_ADDRESS_MAP_VI2_THI_CPU_BASE 0x14f00000
+#define NV_ADDRESS_MAP_VI2_THI_CPU_LIMIT 0x14f03fff
+#define NV_ADDRESS_MAP_VI2_THI_CPU_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_VI2_THI_CPU_HEADER
+
+#define NV_ADDRESS_MAP_VI2_THI_EC_BASE 0x14f04000
+#define NV_ADDRESS_MAP_VI2_THI_EC_LIMIT 0x14f04fff
+#define NV_ADDRESS_MAP_VI2_THI_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_VI2_THI_EC_HEADER
+
+#define NV_ADDRESS_MAP_VI2_THI_ENGINE_BASE 0x14f05000
+#define NV_ADDRESS_MAP_VI2_THI_ENGINE_LIMIT 0x14ffffff
+#define NV_ADDRESS_MAP_VI2_THI_ENGINE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_VI2_THI_ENGINE_HEADER
+
+#define NV_ADDRESS_MAP_VIC_EC_BASE 0x1534f000
+#define NV_ADDRESS_MAP_VIC_EC_LIMIT 0x1534ffff
+#define NV_ADDRESS_MAP_VIC_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_VIC_EC_HEADER arvic_ec_pri.h
+
+#define NV_ADDRESS_MAP_NVJPG_BASE 0x15380000
+#define NV_ADDRESS_MAP_NVJPG_LIMIT 0x153bffff
+#define NV_ADDRESS_MAP_NVJPG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVJPG_HEADER arnvjpg.h;dev_nvjpg_pri.h
+
+#define NV_ADDRESS_MAP_NVDEC_BASE 0x15480000
+#define NV_ADDRESS_MAP_NVDEC_LIMIT 0x154bffff
+#define NV_ADDRESS_MAP_NVDEC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVDEC_HEADER arnvdec.h;nv_ref_dev_nvdec_pri.h;nv_ref_dev_nvdec_pri_PROD.h;dev_nvdec_pri.h
+
+#define NV_ADDRESS_MAP_NVENC_EC_BASE 0x154cf000
+#define NV_ADDRESS_MAP_NVENC_EC_LIMIT 0x154cffff
+#define NV_ADDRESS_MAP_NVENC_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVENC_EC_HEADER
+
+#define NV_ADDRESS_MAP_NVJPG1_BASE 0x15540000
+#define NV_ADDRESS_MAP_NVJPG1_LIMIT 0x1557ffff
+#define NV_ADDRESS_MAP_NVJPG1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVJPG1_HEADER arnvjpg.h;dev_nvjpg_pri.h
+
+#define NV_ADDRESS_MAP_DPAUX_BASE 0x155c0000
+#define NV_ADDRESS_MAP_DPAUX_LIMIT 0x155cffff
+#define NV_ADDRESS_MAP_DPAUX_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_DPAUX_HEADER ardpaux.h
+
+#define NV_ADDRESS_MAP_NVDLA0_ENGINE_BASE 0x15880000
+#define NV_ADDRESS_MAP_NVDLA0_ENGINE_LIMIT 0x158befff
+#define NV_ADDRESS_MAP_NVDLA0_ENGINE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVDLA0_ENGINE_HEADER
+
+#define NV_ADDRESS_MAP_NVDLA0_EC_BASE 0x158bf000
+#define NV_ADDRESS_MAP_NVDLA0_EC_LIMIT 0x158bffff
+#define NV_ADDRESS_MAP_NVDLA0_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVDLA0_EC_HEADER
+
+#define NV_ADDRESS_MAP_NVDLA1_ENGINE_BASE 0x158c0000
+#define NV_ADDRESS_MAP_NVDLA1_ENGINE_LIMIT 0x158fefff
+#define NV_ADDRESS_MAP_NVDLA1_ENGINE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVDLA1_ENGINE_HEADER
+
+#define NV_ADDRESS_MAP_NVDLA1_EC_BASE 0x158ff000
+#define NV_ADDRESS_MAP_NVDLA1_EC_LIMIT 0x158fffff
+#define NV_ADDRESS_MAP_NVDLA1_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVDLA1_EC_HEADER
+
+#define NV_ADDRESS_MAP_NVCSI_ENGINE_BASE 0x15a00000
+#define NV_ADDRESS_MAP_NVCSI_ENGINE_LIMIT 0x15a4afff
+#define NV_ADDRESS_MAP_NVCSI_ENGINE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVCSI_ENGINE_HEADER
+
+#define NV_ADDRESS_MAP_NVCSI_EC_BASE 0x15a4b000
+#define NV_ADDRESS_MAP_NVCSI_EC_LIMIT 0x15a4ffff
+#define NV_ADDRESS_MAP_NVCSI_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_NVCSI_EC_HEADER
+
+#define NV_ADDRESS_MAP_VI_BASE 0x15c00000
+#define NV_ADDRESS_MAP_VI_LIMIT 0x15efffff
+#define NV_ADDRESS_MAP_VI_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_VI_HEADER arvi_fw.h
+
+#define NV_ADDRESS_MAP_VI_THI_CPU_BASE 0x15f00000
+#define NV_ADDRESS_MAP_VI_THI_CPU_LIMIT 0x15f03fff
+#define NV_ADDRESS_MAP_VI_THI_CPU_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_VI_THI_CPU_HEADER
+
+#define NV_ADDRESS_MAP_VI_THI_EC_BASE 0x15f04000
+#define NV_ADDRESS_MAP_VI_THI_EC_LIMIT 0x15f04fff
+#define NV_ADDRESS_MAP_VI_THI_EC_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_VI_THI_EC_HEADER
+
+#define NV_ADDRESS_MAP_VI_THI_ENGINE_BASE 0x15f05000
+#define NV_ADDRESS_MAP_VI_THI_ENGINE_LIMIT 0x15ffffff
+#define NV_ADDRESS_MAP_VI_THI_ENGINE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_VI_THI_ENGINE_HEADER
+
+#define NV_ADDRESS_MAP_PVA0_CLUSTER_BASE 0x16000000
+#define NV_ADDRESS_MAP_PVA0_CLUSTER_LIMIT 0x167fffff
+#define NV_ADDRESS_MAP_PVA0_CLUSTER_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PVA0_CLUSTER_HEADER
+
+#define NV_ADDRESS_MAP_GPU_BASE 0x17000000
+#define NV_ADDRESS_MAP_GPU_LIMIT 0x1fffffff
+#define NV_ADDRESS_MAP_GPU_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GPU_HEADER argpu_comb.h
+
+#define NV_ADDRESS_MAP_BPMP_SPARE_BASE 0x20ae0000
+#define NV_ADDRESS_MAP_BPMP_SPARE_LIMIT 0x20aeefff
+#define NV_ADDRESS_MAP_BPMP_SPARE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_SPARE_HEADER
+
+#define NV_ADDRESS_MAP_BPMP_SCR_BASE 0x20aef000
+#define NV_ADDRESS_MAP_BPMP_SCR_LIMIT 0x20aeffff
+#define NV_ADDRESS_MAP_BPMP_SCR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_BPMP_SCR_HEADER
+
+#define NV_ADDRESS_MAP_AON_SPARE_BASE 0x20cb0000
+#define NV_ADDRESS_MAP_AON_SPARE_LIMIT 0x20cdefff
+#define NV_ADDRESS_MAP_AON_SPARE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_SPARE_HEADER
+
+#define NV_ADDRESS_MAP_AON_SCR_BASE 0x20cdf000
+#define NV_ADDRESS_MAP_AON_SCR_LIMIT 0x20cdffff
+#define NV_ADDRESS_MAP_AON_SCR_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_SCR_HEADER
+
+#define NV_ADDRESS_MAP_CSITE_MISC0_BASE 0x24000000
+#define NV_ADDRESS_MAP_CSITE_MISC0_LIMIT 0x2401ffff
+#define NV_ADDRESS_MAP_CSITE_MISC0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CSITE_MISC0_HEADER
+
+#define NV_ADDRESS_MAP_CSITE_CFG_BASE 0x24020000
+#define NV_ADDRESS_MAP_CSITE_CFG_LIMIT 0x2403ffff
+#define NV_ADDRESS_MAP_CSITE_CFG_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CSITE_CFG_HEADER
+
+#define NV_ADDRESS_MAP_CSITE_MISC1_BASE 0x24040000
+#define NV_ADDRESS_MAP_CSITE_MISC1_LIMIT 0x2440ffff
+#define NV_ADDRESS_MAP_CSITE_MISC1_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CSITE_MISC1_HEADER
+
+#define NV_ADDRESS_MAP_LA_BASE 0x24410000
+#define NV_ADDRESS_MAP_LA_LIMIT 0x2441ffff
+#define NV_ADDRESS_MAP_LA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_LA_HEADER dev_t_la.ref;ardfd_obs.h
+
+#define NV_ADDRESS_MAP_CSITE_MISC2_BASE 0x24420000
+#define NV_ADDRESS_MAP_CSITE_MISC2_LIMIT 0x2443ffff
+#define NV_ADDRESS_MAP_CSITE_MISC2_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CSITE_MISC2_HEADER
+
+#define NV_ADDRESS_MAP_CSITE_BPMP_BASE 0x24440000
+#define NV_ADDRESS_MAP_CSITE_BPMP_LIMIT 0x2445ffff
+#define NV_ADDRESS_MAP_CSITE_BPMP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CSITE_BPMP_HEADER
+
+#define NV_ADDRESS_MAP_CSITE_MISC3_BASE 0x24480000
+#define NV_ADDRESS_MAP_CSITE_MISC3_LIMIT 0x2473ffff
+#define NV_ADDRESS_MAP_CSITE_MISC3_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CSITE_MISC3_HEADER
+
+#define NV_ADDRESS_MAP_CSITE_PVA0VPU_BASE 0x24740000
+#define NV_ADDRESS_MAP_CSITE_PVA0VPU_LIMIT 0x2477ffff
+#define NV_ADDRESS_MAP_CSITE_PVA0VPU_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CSITE_PVA0VPU_HEADER
+
+#define NV_ADDRESS_MAP_CSITE_MISC4_BASE 0x24780000
+#define NV_ADDRESS_MAP_CSITE_MISC4_LIMIT 0x247fffff
+#define NV_ADDRESS_MAP_CSITE_MISC4_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CSITE_MISC4_HEADER
+
+#define NV_ADDRESS_MAP_STM_BASE 0x25000000
+#define NV_ADDRESS_MAP_STM_LIMIT 0x25ffffff
+#define NV_ADDRESS_MAP_STM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_STM_HEADER
+
+#define NV_ADDRESS_MAP_CSITE_CCPLEX_BASE 0x26000000
+#define NV_ADDRESS_MAP_CSITE_CCPLEX_LIMIT 0x27ffffff
+#define NV_ADDRESS_MAP_CSITE_CCPLEX_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_CSITE_CCPLEX_HEADER
+
+#define NV_ADDRESS_MAP_PCIE_C7_32BIT_EP_BASE 0x28000000
+#define NV_ADDRESS_MAP_PCIE_C7_32BIT_EP_LIMIT 0x28001fff
+#define NV_ADDRESS_MAP_PCIE_C7_32BIT_EP_ADDR_LOCALITY SYSTEM_CFG.PCIE_C7_CTL.PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.END_POINT
+#define NV_ADDRESS_MAP_PCIE_C7_32BIT_EP_HEADER arpcie_x8_ep_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C7_32BIT_RP_BASE 0x28000000
+#define NV_ADDRESS_MAP_PCIE_C7_32BIT_RP_LIMIT 0x28001fff
+#define NV_ADDRESS_MAP_PCIE_C7_32BIT_RP_ADDR_LOCALITY SYSTEM_CFG.PCIE_C7_CTL.PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.ROOT_PORT
+#define NV_ADDRESS_MAP_PCIE_C7_32BIT_RP_HEADER arpcie_x8_rc_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C7_32BIT_DMA_BASE 0x28040000
+#define NV_ADDRESS_MAP_PCIE_C7_32BIT_DMA_LIMIT 0x2807ffff
+#define NV_ADDRESS_MAP_PCIE_C7_32BIT_DMA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C7_32BIT_DMA_HEADER arpcie_iatu_dma.h
+
+#define NV_ADDRESS_MAP_PCIE_C8_32BIT_EP_BASE 0x2a000000
+#define NV_ADDRESS_MAP_PCIE_C8_32BIT_EP_LIMIT 0x2a001fff
+#define NV_ADDRESS_MAP_PCIE_C8_32BIT_EP_ADDR_LOCALITY SYSTEM_CFG.PCIE_C8_CTL.PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.END_POINT
+#define NV_ADDRESS_MAP_PCIE_C8_32BIT_EP_HEADER arpcie_x4_ep_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C8_32BIT_RP_BASE 0x2a000000
+#define NV_ADDRESS_MAP_PCIE_C8_32BIT_RP_LIMIT 0x2a001fff
+#define NV_ADDRESS_MAP_PCIE_C8_32BIT_RP_ADDR_LOCALITY SYSTEM_CFG.PCIE_C8_CTL.PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.ROOT_PORT
+#define NV_ADDRESS_MAP_PCIE_C8_32BIT_RP_HEADER arpcie_x4_rc_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C8_32BIT_DMA_BASE 0x2a040000
+#define NV_ADDRESS_MAP_PCIE_C8_32BIT_DMA_LIMIT 0x2a07ffff
+#define NV_ADDRESS_MAP_PCIE_C8_32BIT_DMA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C8_32BIT_DMA_HEADER arpcie_iatu_dma.h
+
+#define NV_ADDRESS_MAP_PCIE_C9_32BIT_EP_BASE 0x2c000000
+#define NV_ADDRESS_MAP_PCIE_C9_32BIT_EP_LIMIT 0x2c001fff
+#define NV_ADDRESS_MAP_PCIE_C9_32BIT_EP_ADDR_LOCALITY SYSTEM_CFG.PCIE_C9_CTL.PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.END_POINT
+#define NV_ADDRESS_MAP_PCIE_C9_32BIT_EP_HEADER arpcie_x4_ep_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C9_32BIT_RP_BASE 0x2c000000
+#define NV_ADDRESS_MAP_PCIE_C9_32BIT_RP_LIMIT 0x2c001fff
+#define NV_ADDRESS_MAP_PCIE_C9_32BIT_RP_ADDR_LOCALITY SYSTEM_CFG.PCIE_C9_CTL.PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.ROOT_PORT
+#define NV_ADDRESS_MAP_PCIE_C9_32BIT_RP_HEADER arpcie_x4_rc_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C9_32BIT_DMA_BASE 0x2c040000
+#define NV_ADDRESS_MAP_PCIE_C9_32BIT_DMA_LIMIT 0x2c07ffff
+#define NV_ADDRESS_MAP_PCIE_C9_32BIT_DMA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C9_32BIT_DMA_HEADER arpcie_iatu_dma.h
+
+#define NV_ADDRESS_MAP_PCIE_C10_32BIT_EP_BASE 0x2e000000
+#define NV_ADDRESS_MAP_PCIE_C10_32BIT_EP_LIMIT 0x2e001fff
+#define NV_ADDRESS_MAP_PCIE_C10_32BIT_EP_ADDR_LOCALITY SYSTEM_CFG.PCIE_C10_CTL.PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.END_POINT
+#define NV_ADDRESS_MAP_PCIE_C10_32BIT_EP_HEADER arpcie_x4_ep_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C10_32BIT_RP_BASE 0x2e000000
+#define NV_ADDRESS_MAP_PCIE_C10_32BIT_RP_LIMIT 0x2e001fff
+#define NV_ADDRESS_MAP_PCIE_C10_32BIT_RP_ADDR_LOCALITY SYSTEM_CFG.PCIE_C10_CTL.PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.ROOT_PORT
+#define NV_ADDRESS_MAP_PCIE_C10_32BIT_RP_HEADER arpcie_x4_rc_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C10_32BIT_DMA_BASE 0x2e040000
+#define NV_ADDRESS_MAP_PCIE_C10_32BIT_DMA_LIMIT 0x2e07ffff
+#define NV_ADDRESS_MAP_PCIE_C10_32BIT_DMA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C10_32BIT_DMA_HEADER arpcie_iatu_dma.h
+
+#define NV_ADDRESS_MAP_PCIE_C1_32BIT_RP_BASE 0x30000000
+#define NV_ADDRESS_MAP_PCIE_C1_32BIT_RP_LIMIT 0x30001fff
+#define NV_ADDRESS_MAP_PCIE_C1_32BIT_RP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C1_32BIT_RP_HEADER arpcie_x1_rc_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C1_32BIT_DMA_BASE 0x30040000
+#define NV_ADDRESS_MAP_PCIE_C1_32BIT_DMA_LIMIT 0x3007ffff
+#define NV_ADDRESS_MAP_PCIE_C1_32BIT_DMA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C1_32BIT_DMA_HEADER arpcie_iatu_dma.h
+
+#define NV_ADDRESS_MAP_PCIE_C2_32BIT_RP_BASE 0x32000000
+#define NV_ADDRESS_MAP_PCIE_C2_32BIT_RP_LIMIT 0x32001fff
+#define NV_ADDRESS_MAP_PCIE_C2_32BIT_RP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C2_32BIT_RP_HEADER arpcie_x1_rc_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C2_32BIT_DMA_BASE 0x32040000
+#define NV_ADDRESS_MAP_PCIE_C2_32BIT_DMA_LIMIT 0x3207ffff
+#define NV_ADDRESS_MAP_PCIE_C2_32BIT_DMA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C2_32BIT_DMA_HEADER arpcie_iatu_dma.h
+
+#define NV_ADDRESS_MAP_PCIE_C3_32BIT_RP_BASE 0x34000000
+#define NV_ADDRESS_MAP_PCIE_C3_32BIT_RP_LIMIT 0x34001fff
+#define NV_ADDRESS_MAP_PCIE_C3_32BIT_RP_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C3_32BIT_RP_HEADER arpcie_x1_rc_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C3_32BIT_DMA_BASE 0x34040000
+#define NV_ADDRESS_MAP_PCIE_C3_32BIT_DMA_LIMIT 0x3407ffff
+#define NV_ADDRESS_MAP_PCIE_C3_32BIT_DMA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C3_32BIT_DMA_HEADER arpcie_iatu_dma.h
+
+#define NV_ADDRESS_MAP_PCIE_C4_32BIT_EP_BASE 0x36000000
+#define NV_ADDRESS_MAP_PCIE_C4_32BIT_EP_LIMIT 0x36001fff
+#define NV_ADDRESS_MAP_PCIE_C4_32BIT_EP_ADDR_LOCALITY SYSTEM_CFG.PCIE_C4_CTL.PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.END_POINT
+#define NV_ADDRESS_MAP_PCIE_C4_32BIT_EP_HEADER arpcie_x4_ep_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C4_32BIT_RP_BASE 0x36000000
+#define NV_ADDRESS_MAP_PCIE_C4_32BIT_RP_LIMIT 0x36001fff
+#define NV_ADDRESS_MAP_PCIE_C4_32BIT_RP_ADDR_LOCALITY SYSTEM_CFG.PCIE_C4_CTL.PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.ROOT_PORT
+#define NV_ADDRESS_MAP_PCIE_C4_32BIT_RP_HEADER arpcie_x4_rc_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C4_32BIT_DMA_BASE 0x36040000
+#define NV_ADDRESS_MAP_PCIE_C4_32BIT_DMA_LIMIT 0x3607ffff
+#define NV_ADDRESS_MAP_PCIE_C4_32BIT_DMA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C4_32BIT_DMA_HEADER arpcie_iatu_dma.h
+
+#define NV_ADDRESS_MAP_PCIE_C0_32BIT_EP_BASE 0x38000000
+#define NV_ADDRESS_MAP_PCIE_C0_32BIT_EP_LIMIT 0x38001fff
+#define NV_ADDRESS_MAP_PCIE_C0_32BIT_EP_ADDR_LOCALITY SYSTEM_CFG.PCIE_C0_CTL.PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.END_POINT
+#define NV_ADDRESS_MAP_PCIE_C0_32BIT_EP_HEADER arpcie_x4_ep_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C0_32BIT_RP_BASE 0x38000000
+#define NV_ADDRESS_MAP_PCIE_C0_32BIT_RP_LIMIT 0x38001fff
+#define NV_ADDRESS_MAP_PCIE_C0_32BIT_RP_ADDR_LOCALITY SYSTEM_CFG.PCIE_C0_CTL.PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.ROOT_PORT
+#define NV_ADDRESS_MAP_PCIE_C0_32BIT_RP_HEADER arpcie_x4_rc_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C0_32BIT_DMA_BASE 0x38040000
+#define NV_ADDRESS_MAP_PCIE_C0_32BIT_DMA_LIMIT 0x3807ffff
+#define NV_ADDRESS_MAP_PCIE_C0_32BIT_DMA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C0_32BIT_DMA_HEADER arpcie_iatu_dma.h
+
+#define NV_ADDRESS_MAP_PCIE_C5_32BIT_EP_BASE 0x3a000000
+#define NV_ADDRESS_MAP_PCIE_C5_32BIT_EP_LIMIT 0x3a001fff
+#define NV_ADDRESS_MAP_PCIE_C5_32BIT_EP_ADDR_LOCALITY SYSTEM_CFG.PCIE_C5_CTL.PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.END_POINT
+#define NV_ADDRESS_MAP_PCIE_C5_32BIT_EP_HEADER arpcie_x8_ep_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C5_32BIT_RP_BASE 0x3a000000
+#define NV_ADDRESS_MAP_PCIE_C5_32BIT_RP_LIMIT 0x3a001fff
+#define NV_ADDRESS_MAP_PCIE_C5_32BIT_RP_ADDR_LOCALITY SYSTEM_CFG.PCIE_C5_CTL.PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.ROOT_PORT
+#define NV_ADDRESS_MAP_PCIE_C5_32BIT_RP_HEADER arpcie_x8_rc_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C5_32BIT_DMA_BASE 0x3a040000
+#define NV_ADDRESS_MAP_PCIE_C5_32BIT_DMA_LIMIT 0x3a07ffff
+#define NV_ADDRESS_MAP_PCIE_C5_32BIT_DMA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C5_32BIT_DMA_HEADER arpcie_iatu_dma.h
+
+#define NV_ADDRESS_MAP_PCIE_C6_32BIT_EP_BASE 0x3c000000
+#define NV_ADDRESS_MAP_PCIE_C6_32BIT_EP_LIMIT 0x3c001fff
+#define NV_ADDRESS_MAP_PCIE_C6_32BIT_EP_ADDR_LOCALITY SYSTEM_CFG.PCIE_C6_CTL.PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.END_POINT
+#define NV_ADDRESS_MAP_PCIE_C6_32BIT_EP_HEADER arpcie_x4_ep_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C6_32BIT_RP_BASE 0x3c000000
+#define NV_ADDRESS_MAP_PCIE_C6_32BIT_RP_LIMIT 0x3c001fff
+#define NV_ADDRESS_MAP_PCIE_C6_32BIT_RP_ADDR_LOCALITY SYSTEM_CFG.PCIE_C6_CTL.PCIE_RP_APPL_DM_TYPE_0.DEVICE_TYPE.ROOT_PORT
+#define NV_ADDRESS_MAP_PCIE_C6_32BIT_RP_HEADER arpcie_x4_rc_dbi.h
+
+#define NV_ADDRESS_MAP_PCIE_C6_32BIT_DMA_BASE 0x3c040000
+#define NV_ADDRESS_MAP_PCIE_C6_32BIT_DMA_LIMIT 0x3c07ffff
+#define NV_ADDRESS_MAP_PCIE_C6_32BIT_DMA_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C6_32BIT_DMA_HEADER arpcie_iatu_dma.h
+
+#define NV_ADDRESS_MAP_SYSRAM_0_IMPL_BASE 0x40000000
+#define NV_ADDRESS_MAP_SYSRAM_0_IMPL_LIMIT 0x4007ffff
+#define NV_ADDRESS_MAP_SYSRAM_0_IMPL_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SYSRAM_0_IMPL_HEADER no_headers
+
+#define NV_ADDRESS_MAP_AON_TZRAM_BASE 0x50000000
+#define NV_ADDRESS_MAP_AON_TZRAM_LIMIT 0x5007ffff
+#define NV_ADDRESS_MAP_AON_TZRAM_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_AON_TZRAM_HEADER no_headers
+
+#define NV_ADDRESS_MAP_GIC_MSI_BASE 0x54000000
+#define NV_ADDRESS_MAP_GIC_MSI_LIMIT 0x57ffffff
+#define NV_ADDRESS_MAP_GIC_MSI_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_GIC_MSI_HEADER no_headers
+
+#define NV_ADDRESS_MAP_SYNCPOINT_0_BASE 0x60000000
+#define NV_ADDRESS_MAP_SYNCPOINT_0_LIMIT 0x63ffffff
+#define NV_ADDRESS_MAP_SYNCPOINT_0_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_SYNCPOINT_0_HEADER no_headers
+
+#define NV_ADDRESS_MAP_EMEM_32BIT_BASE 0x80000000
+#define NV_ADDRESS_MAP_EMEM_32BIT_LIMIT 0xffffffff
+#define NV_ADDRESS_MAP_EMEM_32BIT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_EMEM_32BIT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_PCIE_C1_64BIT_BASE 0x2080000000
+#define NV_ADDRESS_MAP_PCIE_C1_64BIT_LIMIT 0x20bfffffff
+#define NV_ADDRESS_MAP_PCIE_C1_64BIT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C1_64BIT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_PCIE_C2_64BIT_BASE 0x20c0000000
+#define NV_ADDRESS_MAP_PCIE_C2_64BIT_LIMIT 0x20ffffffff
+#define NV_ADDRESS_MAP_PCIE_C2_64BIT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C2_64BIT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_PCIE_C3_64BIT_BASE 0x2100000000
+#define NV_ADDRESS_MAP_PCIE_C3_64BIT_LIMIT 0x213fffffff
+#define NV_ADDRESS_MAP_PCIE_C3_64BIT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C3_64BIT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_PCIE_C6_64BIT_BASE 0x2140000000
+#define NV_ADDRESS_MAP_PCIE_C6_64BIT_LIMIT 0x217fffffff
+#define NV_ADDRESS_MAP_PCIE_C6_64BIT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C6_64BIT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_PCIE_C7_64BIT_BASE 0x2180000000
+#define NV_ADDRESS_MAP_PCIE_C7_64BIT_LIMIT 0x21bfffffff
+#define NV_ADDRESS_MAP_PCIE_C7_64BIT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C7_64BIT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_PCIE_C8_64BIT_BASE 0x21c0000000
+#define NV_ADDRESS_MAP_PCIE_C8_64BIT_LIMIT 0x21ffffffff
+#define NV_ADDRESS_MAP_PCIE_C8_64BIT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C8_64BIT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_PCIE_C9_64BIT_BASE 0x2200000000
+#define NV_ADDRESS_MAP_PCIE_C9_64BIT_LIMIT 0x223fffffff
+#define NV_ADDRESS_MAP_PCIE_C9_64BIT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C9_64BIT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_PCIE_C10_64BIT_BASE 0x2240000000
+#define NV_ADDRESS_MAP_PCIE_C10_64BIT_LIMIT 0x227fffffff
+#define NV_ADDRESS_MAP_PCIE_C10_64BIT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C10_64BIT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_PCIE_C4_64BIT_BASE 0x2280000000
+#define NV_ADDRESS_MAP_PCIE_C4_64BIT_LIMIT 0x267fffffff
+#define NV_ADDRESS_MAP_PCIE_C4_64BIT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C4_64BIT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_PCIE_C0_64BIT_BASE 0x2680000000
+#define NV_ADDRESS_MAP_PCIE_C0_64BIT_LIMIT 0x2a7fffffff
+#define NV_ADDRESS_MAP_PCIE_C0_64BIT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C0_64BIT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_PCIE_C5_64BIT_BASE 0x2a80000000
+#define NV_ADDRESS_MAP_PCIE_C5_64BIT_LIMIT 0x2e7fffffff
+#define NV_ADDRESS_MAP_PCIE_C5_64BIT_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_PCIE_C5_64BIT_HEADER no_headers
+
+#define NV_ADDRESS_MAP_MSSNVLINK0_SLAVE_BASE 0x4000000000
+#define NV_ADDRESS_MAP_MSSNVLINK0_SLAVE_LIMIT 0x7fffffffff
+#define NV_ADDRESS_MAP_MSSNVLINK0_SLAVE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MSSNVLINK0_SLAVE_HEADER no_headers
+
+#define NV_ADDRESS_MAP_MSSNVLINK1_SLAVE_BASE 0x8000000000
+#define NV_ADDRESS_MAP_MSSNVLINK1_SLAVE_LIMIT 0xbfffffffff
+#define NV_ADDRESS_MAP_MSSNVLINK1_SLAVE_ADDR_LOCALITY SYSTEM
+#define NV_ADDRESS_MAP_MSSNVLINK1_SLAVE_HEADER no_headers
+
+#define NV_ADDRESS_MAP_CAR_BASE 0x20000000
+#define NV_ADDRESS_MAP_AON_TKE_BASE 0x0c0f0000
+#define NV_ADDRESS_MAP_TOP0_HSP_BASE 0x03c00000
+#define NV_ADDRESS_MAP_BPMP_HSP_BASE 0x0d150000
+#define NV_ADDRESS_MAP_AON_HSP_BASE 0x0c150000
+#define NV_ADDRESS_MAP_SCE_HSP_BASE 0x0b150000
+#define NV_ADDRESS_MAP_AON_PM_BASE 0x0c1f0000
+#define NV_ADDRESS_MAP_TOP0_HSP_COMMON_SIZEi 0x00010000
+#define NV_ADDRESS_MAP_FUSE_BASE 0x03810000
+#define NV_ADDRESS_MAP_TOP0_HSP_COMMON_SIZE 0x00010000
+#define NV_ADDRESS_MAP_TOP1_HSP_BASE 0x03d00000
+#define NV_ADDRESS_MAP_FSI_HSP_BASE  0x09300000
+#define NV_ADDRESS_MAP_AON_BTCM_SIZE 0x00040000
+#define NV_ADDRESS_MAP_AON_DMA_BASE  0x0c060000
+#define NV_ADDRESS_MAP_GPIO_CTL_BASE 0x02200000
+#define NV_ADDRESS_MAP_TOP_HSP1_SHARED_4_INTR_ID 0x84
+#define NV_ADDRESS_MAP_LIC_BASE	0x03000000
+#define NV_ADDRESS_MAP_FUSE_CONTROLLER_SIZE	0x00020000
+
+#endif  //ADDRESS_MAP_NEW_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/araodmic.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/araodmic.h
new file mode 100644
index 0000000..74a706b
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/araodmic.h
@@ -0,0 +1,996 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARAODMIC_H_INC
+#define ARAODMIC_H_INC
+#define NV_MOBILE_ARAODMIC_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARAODMIC_H_SCRREG_NOMENCLATURE INFERRED
+
+
+// Register AODMIC_APB_FIFO_CTRL_0
+#define AODMIC_APB_FIFO_CTRL_0                  MK_ADDR_CONST(0x0)
+#define AODMIC_APB_FIFO_CTRL_0_SECURE                   0x0
+#define AODMIC_APB_FIFO_CTRL_0_DUAL                     0x0
+#define AODMIC_APB_FIFO_CTRL_0_SCR                      0
+#define AODMIC_APB_FIFO_CTRL_0_SCRREG                   0
+#define AODMIC_APB_FIFO_CTRL_0_WORD_COUNT                       0x1
+#define AODMIC_APB_FIFO_CTRL_0_RESET_VAL                        MK_MASK_CONST(0x1000)
+#define AODMIC_APB_FIFO_CTRL_0_RESET_MASK                       MK_MASK_CONST(0x3f00)
+#define AODMIC_APB_FIFO_CTRL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_CTRL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_CTRL_0_READ_MASK                        MK_MASK_CONST(0x3f00)
+#define AODMIC_APB_FIFO_CTRL_0_WRITE_MASK                       MK_MASK_CONST(0x3f00)
+#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_SHIFT                  MK_SHIFT_CONST(8)
+#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_FIELD                  MK_FIELD_CONST(0x3f, AODMIC_APB_FIFO_CTRL_0_THRESHOLD_SHIFT)
+#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_RANGE                  13:8
+#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_MSB                    MK_SHIFT_CONST(13)
+#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_LSB                    MK_SHIFT_CONST(8)
+#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_WOFFSET                        0x0
+#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_DEFAULT                        MK_MASK_CONST(0x10)
+#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_DEFAULT_MASK                   MK_MASK_CONST(0x3f)
+#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_CTRL_0_THRESHOLD_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register AODMIC_APB_FIFO_CTRL_RD_DATA_0
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0                  MK_ADDR_CONST(0x4)
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_SECURE                   0x0
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DUAL                     0x0
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_SCR                      0
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_SCRREG                   0
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_WORD_COUNT                       0x1
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_SHIFT)
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_RANGE                       31:0
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_WOFFSET                     0x0
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_CTRL_RD_DATA_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register AODMIC_APB_FIFO_STATUS_0
+#define AODMIC_APB_FIFO_STATUS_0                        MK_ADDR_CONST(0x8)
+#define AODMIC_APB_FIFO_STATUS_0_SECURE                         0x0
+#define AODMIC_APB_FIFO_STATUS_0_DUAL                   0x0
+#define AODMIC_APB_FIFO_STATUS_0_SCR                    0
+#define AODMIC_APB_FIFO_STATUS_0_SCRREG                         0
+#define AODMIC_APB_FIFO_STATUS_0_WORD_COUNT                     0x1
+#define AODMIC_APB_FIFO_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x40)
+#define AODMIC_APB_FIFO_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x1ff)
+#define AODMIC_APB_FIFO_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_READ_MASK                      MK_MASK_CONST(0x1ff)
+#define AODMIC_APB_FIFO_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_SHIFT                   MK_SHIFT_CONST(8)
+#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_FIELD                   MK_FIELD_CONST(0x1, AODMIC_APB_FIFO_STATUS_0_RX_REQ_SHIFT)
+#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_RANGE                   8:8
+#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_MSB                     MK_SHIFT_CONST(8)
+#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_LSB                     MK_SHIFT_CONST(8)
+#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_WOFFSET                 0x0
+#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_INIT_ENUM                       FALSE
+#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_FALSE                   MK_ENUM_CONST(0)
+#define AODMIC_APB_FIFO_STATUS_0_RX_REQ_TRUE                    MK_ENUM_CONST(1)
+
+#define AODMIC_APB_FIFO_STATUS_0_FULL_SHIFT                     MK_SHIFT_CONST(7)
+#define AODMIC_APB_FIFO_STATUS_0_FULL_FIELD                     MK_FIELD_CONST(0x1, AODMIC_APB_FIFO_STATUS_0_FULL_SHIFT)
+#define AODMIC_APB_FIFO_STATUS_0_FULL_RANGE                     7:7
+#define AODMIC_APB_FIFO_STATUS_0_FULL_MSB                       MK_SHIFT_CONST(7)
+#define AODMIC_APB_FIFO_STATUS_0_FULL_LSB                       MK_SHIFT_CONST(7)
+#define AODMIC_APB_FIFO_STATUS_0_FULL_WOFFSET                   0x0
+#define AODMIC_APB_FIFO_STATUS_0_FULL_DEFAULT                   MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_FULL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AODMIC_APB_FIFO_STATUS_0_FULL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_FULL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_FULL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_FULL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AODMIC_APB_FIFO_STATUS_0_FULL_INIT_ENUM                 FALSE
+#define AODMIC_APB_FIFO_STATUS_0_FULL_FALSE                     MK_ENUM_CONST(0)
+#define AODMIC_APB_FIFO_STATUS_0_FULL_TRUE                      MK_ENUM_CONST(1)
+
+#define AODMIC_APB_FIFO_STATUS_0_EMPTY_SHIFT                    MK_SHIFT_CONST(6)
+#define AODMIC_APB_FIFO_STATUS_0_EMPTY_FIELD                    MK_FIELD_CONST(0x1, AODMIC_APB_FIFO_STATUS_0_EMPTY_SHIFT)
+#define AODMIC_APB_FIFO_STATUS_0_EMPTY_RANGE                    6:6
+#define AODMIC_APB_FIFO_STATUS_0_EMPTY_MSB                      MK_SHIFT_CONST(6)
+#define AODMIC_APB_FIFO_STATUS_0_EMPTY_LSB                      MK_SHIFT_CONST(6)
+#define AODMIC_APB_FIFO_STATUS_0_EMPTY_WOFFSET                  0x0
+#define AODMIC_APB_FIFO_STATUS_0_EMPTY_DEFAULT                  MK_MASK_CONST(0x1)
+#define AODMIC_APB_FIFO_STATUS_0_EMPTY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AODMIC_APB_FIFO_STATUS_0_EMPTY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_EMPTY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_EMPTY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_EMPTY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AODMIC_APB_FIFO_STATUS_0_EMPTY_INIT_ENUM                        TRUE
+#define AODMIC_APB_FIFO_STATUS_0_EMPTY_FALSE                    MK_ENUM_CONST(0)
+#define AODMIC_APB_FIFO_STATUS_0_EMPTY_TRUE                     MK_ENUM_CONST(1)
+
+#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_FIELD                       MK_FIELD_CONST(0x3f, AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_SHIFT)
+#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_RANGE                       5:0
+#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_MSB                 MK_SHIFT_CONST(5)
+#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_WOFFSET                     0x0
+#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AODMIC_APB_FIFO_STATUS_0_DATA_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register AODMIC_APB_RX_INT_STATUS_0
+#define AODMIC_APB_RX_INT_STATUS_0                      MK_ADDR_CONST(0xc)
+#define AODMIC_APB_RX_INT_STATUS_0_SECURE                       0x0
+#define AODMIC_APB_RX_INT_STATUS_0_DUAL                         0x0
+#define AODMIC_APB_RX_INT_STATUS_0_SCR                  0
+#define AODMIC_APB_RX_INT_STATUS_0_SCRREG                       0
+#define AODMIC_APB_RX_INT_STATUS_0_WORD_COUNT                   0x1
+#define AODMIC_APB_RX_INT_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x101)
+#define AODMIC_APB_RX_INT_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_STATUS_0_READ_MASK                    MK_MASK_CONST(0x101)
+#define AODMIC_APB_RX_INT_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_SHIFT                     MK_SHIFT_CONST(8)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_FIELD                     MK_FIELD_CONST(0x1, AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_SHIFT)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_RANGE                     8:8
+#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_MSB                       MK_SHIFT_CONST(8)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_LSB                       MK_SHIFT_CONST(8)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_WOFFSET                   0x0
+#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_DEFAULT                   MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_INIT_ENUM                 CLEAR
+#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_CLEAR                     MK_ENUM_CONST(0)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_OVERRUN_SET                       MK_ENUM_CONST(1)
+
+#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_SHIFT                        MK_SHIFT_CONST(0)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_FIELD                        MK_FIELD_CONST(0x1, AODMIC_APB_RX_INT_STATUS_0_RX_DONE_SHIFT)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_RANGE                        0:0
+#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_MSB                  MK_SHIFT_CONST(0)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_LSB                  MK_SHIFT_CONST(0)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_WOFFSET                      0x0
+#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_DEFAULT                      MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_INIT_ENUM                    CLEAR
+#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_CLEAR                        MK_ENUM_CONST(0)
+#define AODMIC_APB_RX_INT_STATUS_0_RX_DONE_SET                  MK_ENUM_CONST(1)
+
+
+// Register AODMIC_APB_RX_INT_MASK_0
+#define AODMIC_APB_RX_INT_MASK_0                        MK_ADDR_CONST(0x10)
+#define AODMIC_APB_RX_INT_MASK_0_SECURE                         0x0
+#define AODMIC_APB_RX_INT_MASK_0_DUAL                   0x0
+#define AODMIC_APB_RX_INT_MASK_0_SCR                    0
+#define AODMIC_APB_RX_INT_MASK_0_SCRREG                         0
+#define AODMIC_APB_RX_INT_MASK_0_WORD_COUNT                     0x1
+#define AODMIC_APB_RX_INT_MASK_0_RESET_VAL                      MK_MASK_CONST(0x101)
+#define AODMIC_APB_RX_INT_MASK_0_RESET_MASK                     MK_MASK_CONST(0x101)
+#define AODMIC_APB_RX_INT_MASK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_MASK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_MASK_0_READ_MASK                      MK_MASK_CONST(0x101)
+#define AODMIC_APB_RX_INT_MASK_0_WRITE_MASK                     MK_MASK_CONST(0x101)
+#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_SHIFT                       MK_SHIFT_CONST(8)
+#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_FIELD                       MK_FIELD_CONST(0x1, AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_SHIFT)
+#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_RANGE                       8:8
+#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_MSB                 MK_SHIFT_CONST(8)
+#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_LSB                 MK_SHIFT_CONST(8)
+#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_WOFFSET                     0x0
+#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_DEFAULT                     MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_INIT_ENUM                   MASK
+#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_UNMASK                      MK_ENUM_CONST(0)
+#define AODMIC_APB_RX_INT_MASK_0_RX_OVERRUN_MASK                        MK_ENUM_CONST(1)
+
+#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_SHIFT                  MK_SHIFT_CONST(0)
+#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_FIELD                  MK_FIELD_CONST(0x1, AODMIC_APB_RX_INT_MASK_0_RX_DONE_SHIFT)
+#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_RANGE                  0:0
+#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_MSB                    MK_SHIFT_CONST(0)
+#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_LSB                    MK_SHIFT_CONST(0)
+#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_WOFFSET                        0x0
+#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_DEFAULT                        MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_INIT_ENUM                      MASK
+#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_UNMASK                 MK_ENUM_CONST(0)
+#define AODMIC_APB_RX_INT_MASK_0_RX_DONE_MASK                   MK_ENUM_CONST(1)
+
+
+// Register AODMIC_APB_RX_INT_SET_0
+#define AODMIC_APB_RX_INT_SET_0                 MK_ADDR_CONST(0x14)
+#define AODMIC_APB_RX_INT_SET_0_SECURE                  0x0
+#define AODMIC_APB_RX_INT_SET_0_DUAL                    0x0
+#define AODMIC_APB_RX_INT_SET_0_SCR                     0
+#define AODMIC_APB_RX_INT_SET_0_SCRREG                  0
+#define AODMIC_APB_RX_INT_SET_0_WORD_COUNT                      0x1
+#define AODMIC_APB_RX_INT_SET_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_SET_0_RESET_MASK                      MK_MASK_CONST(0x101)
+#define AODMIC_APB_RX_INT_SET_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_SET_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_SET_0_READ_MASK                       MK_MASK_CONST(0x101)
+#define AODMIC_APB_RX_INT_SET_0_WRITE_MASK                      MK_MASK_CONST(0x101)
+#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_SHIFT                        MK_SHIFT_CONST(8)
+#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_FIELD                        MK_FIELD_CONST(0x1, AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_SHIFT)
+#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_RANGE                        8:8
+#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_MSB                  MK_SHIFT_CONST(8)
+#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_LSB                  MK_SHIFT_CONST(8)
+#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_WOFFSET                      0x0
+#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_DEFAULT                      MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_INIT_ENUM                    CLEAR
+#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_CLEAR                        MK_ENUM_CONST(0)
+#define AODMIC_APB_RX_INT_SET_0_RX_OVERRUN_SET                  MK_ENUM_CONST(1)
+
+#define AODMIC_APB_RX_INT_SET_0_RX_DONE_SHIFT                   MK_SHIFT_CONST(0)
+#define AODMIC_APB_RX_INT_SET_0_RX_DONE_FIELD                   MK_FIELD_CONST(0x1, AODMIC_APB_RX_INT_SET_0_RX_DONE_SHIFT)
+#define AODMIC_APB_RX_INT_SET_0_RX_DONE_RANGE                   0:0
+#define AODMIC_APB_RX_INT_SET_0_RX_DONE_MSB                     MK_SHIFT_CONST(0)
+#define AODMIC_APB_RX_INT_SET_0_RX_DONE_LSB                     MK_SHIFT_CONST(0)
+#define AODMIC_APB_RX_INT_SET_0_RX_DONE_WOFFSET                 0x0
+#define AODMIC_APB_RX_INT_SET_0_RX_DONE_DEFAULT                 MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_SET_0_RX_DONE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_SET_0_RX_DONE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_SET_0_RX_DONE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_SET_0_RX_DONE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_SET_0_RX_DONE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_SET_0_RX_DONE_INIT_ENUM                       CLEAR
+#define AODMIC_APB_RX_INT_SET_0_RX_DONE_CLEAR                   MK_ENUM_CONST(0)
+#define AODMIC_APB_RX_INT_SET_0_RX_DONE_SET                     MK_ENUM_CONST(1)
+
+
+// Register AODMIC_APB_RX_INT_CLEAR_0
+#define AODMIC_APB_RX_INT_CLEAR_0                       MK_ADDR_CONST(0x18)
+#define AODMIC_APB_RX_INT_CLEAR_0_SECURE                        0x0
+#define AODMIC_APB_RX_INT_CLEAR_0_DUAL                  0x0
+#define AODMIC_APB_RX_INT_CLEAR_0_SCR                   0
+#define AODMIC_APB_RX_INT_CLEAR_0_SCRREG                        0
+#define AODMIC_APB_RX_INT_CLEAR_0_WORD_COUNT                    0x1
+#define AODMIC_APB_RX_INT_CLEAR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_CLEAR_0_RESET_MASK                    MK_MASK_CONST(0x101)
+#define AODMIC_APB_RX_INT_CLEAR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_CLEAR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_CLEAR_0_READ_MASK                     MK_MASK_CONST(0x101)
+#define AODMIC_APB_RX_INT_CLEAR_0_WRITE_MASK                    MK_MASK_CONST(0x101)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_SHIFT                      MK_SHIFT_CONST(8)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_FIELD                      MK_FIELD_CONST(0x1, AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_SHIFT)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_RANGE                      8:8
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_MSB                        MK_SHIFT_CONST(8)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_LSB                        MK_SHIFT_CONST(8)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_WOFFSET                    0x0
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_DEFAULT                    MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_INIT_ENUM                  CLEAR
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_CLEAR                      MK_ENUM_CONST(0)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_OVERRUN_SET                        MK_ENUM_CONST(1)
+
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_SHIFT                 MK_SHIFT_CONST(0)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_FIELD                 MK_FIELD_CONST(0x1, AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_SHIFT)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_RANGE                 0:0
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_MSB                   MK_SHIFT_CONST(0)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_LSB                   MK_SHIFT_CONST(0)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_WOFFSET                       0x0
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_DEFAULT                       MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_INIT_ENUM                     CLEAR
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_CLEAR                 MK_ENUM_CONST(0)
+#define AODMIC_APB_RX_INT_CLEAR_0_RX_DONE_SET                   MK_ENUM_CONST(1)
+
+
+// Register AODMIC_ENABLE_0
+#define AODMIC_ENABLE_0                 MK_ADDR_CONST(0x40)
+#define AODMIC_ENABLE_0_SECURE                  0x0
+#define AODMIC_ENABLE_0_DUAL                    0x0
+#define AODMIC_ENABLE_0_SCR                     0
+#define AODMIC_ENABLE_0_SCRREG                  0
+#define AODMIC_ENABLE_0_WORD_COUNT                      0x1
+#define AODMIC_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define AODMIC_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define AODMIC_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define AODMIC_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define AODMIC_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define AODMIC_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define AODMIC_ENABLE_0_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define AODMIC_ENABLE_0_ENABLE_FIELD                    MK_FIELD_CONST(0x1, AODMIC_ENABLE_0_ENABLE_SHIFT)
+#define AODMIC_ENABLE_0_ENABLE_RANGE                    0:0
+#define AODMIC_ENABLE_0_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define AODMIC_ENABLE_0_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define AODMIC_ENABLE_0_ENABLE_WOFFSET                  0x0
+#define AODMIC_ENABLE_0_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define AODMIC_ENABLE_0_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AODMIC_ENABLE_0_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AODMIC_ENABLE_0_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AODMIC_ENABLE_0_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AODMIC_ENABLE_0_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AODMIC_ENABLE_0_ENABLE_INIT_ENUM                        FALSE
+#define AODMIC_ENABLE_0_ENABLE_FALSE                    MK_ENUM_CONST(0)
+#define AODMIC_ENABLE_0_ENABLE_TRUE                     MK_ENUM_CONST(1)
+
+
+// Register AODMIC_SOFT_RESET_0
+#define AODMIC_SOFT_RESET_0                     MK_ADDR_CONST(0x44)
+#define AODMIC_SOFT_RESET_0_SECURE                      0x0
+#define AODMIC_SOFT_RESET_0_DUAL                        0x0
+#define AODMIC_SOFT_RESET_0_SCR                         0
+#define AODMIC_SOFT_RESET_0_SCRREG                      0
+#define AODMIC_SOFT_RESET_0_WORD_COUNT                  0x1
+#define AODMIC_SOFT_RESET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define AODMIC_SOFT_RESET_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define AODMIC_SOFT_RESET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define AODMIC_SOFT_RESET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AODMIC_SOFT_RESET_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define AODMIC_SOFT_RESET_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define AODMIC_SOFT_RESET_0_SOFT_RESET_SHIFT                    MK_SHIFT_CONST(0)
+#define AODMIC_SOFT_RESET_0_SOFT_RESET_FIELD                    MK_FIELD_CONST(0x1, AODMIC_SOFT_RESET_0_SOFT_RESET_SHIFT)
+#define AODMIC_SOFT_RESET_0_SOFT_RESET_RANGE                    0:0
+#define AODMIC_SOFT_RESET_0_SOFT_RESET_MSB                      MK_SHIFT_CONST(0)
+#define AODMIC_SOFT_RESET_0_SOFT_RESET_LSB                      MK_SHIFT_CONST(0)
+#define AODMIC_SOFT_RESET_0_SOFT_RESET_WOFFSET                  0x0
+#define AODMIC_SOFT_RESET_0_SOFT_RESET_DEFAULT                  MK_MASK_CONST(0x0)
+#define AODMIC_SOFT_RESET_0_SOFT_RESET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AODMIC_SOFT_RESET_0_SOFT_RESET_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AODMIC_SOFT_RESET_0_SOFT_RESET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AODMIC_SOFT_RESET_0_SOFT_RESET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AODMIC_SOFT_RESET_0_SOFT_RESET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AODMIC_SOFT_RESET_0_SOFT_RESET_INIT_ENUM                        FALSE
+#define AODMIC_SOFT_RESET_0_SOFT_RESET_FALSE                    MK_ENUM_CONST(0)
+#define AODMIC_SOFT_RESET_0_SOFT_RESET_TRUE                     MK_ENUM_CONST(1)
+
+
+// Register AODMIC_CG_0
+#define AODMIC_CG_0                     MK_ADDR_CONST(0x48)
+#define AODMIC_CG_0_SECURE                      0x0
+#define AODMIC_CG_0_DUAL                        0x0
+#define AODMIC_CG_0_SCR                         0
+#define AODMIC_CG_0_SCRREG                      0
+#define AODMIC_CG_0_WORD_COUNT                  0x1
+#define AODMIC_CG_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define AODMIC_CG_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define AODMIC_CG_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define AODMIC_CG_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AODMIC_CG_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define AODMIC_CG_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define AODMIC_CG_0_SLCG_EN_SHIFT                       MK_SHIFT_CONST(0)
+#define AODMIC_CG_0_SLCG_EN_FIELD                       MK_FIELD_CONST(0x1, AODMIC_CG_0_SLCG_EN_SHIFT)
+#define AODMIC_CG_0_SLCG_EN_RANGE                       0:0
+#define AODMIC_CG_0_SLCG_EN_MSB                 MK_SHIFT_CONST(0)
+#define AODMIC_CG_0_SLCG_EN_LSB                 MK_SHIFT_CONST(0)
+#define AODMIC_CG_0_SLCG_EN_WOFFSET                     0x0
+#define AODMIC_CG_0_SLCG_EN_DEFAULT                     MK_MASK_CONST(0x1)
+#define AODMIC_CG_0_SLCG_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AODMIC_CG_0_SLCG_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AODMIC_CG_0_SLCG_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AODMIC_CG_0_SLCG_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AODMIC_CG_0_SLCG_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AODMIC_CG_0_SLCG_EN_INIT_ENUM                   TRUE
+#define AODMIC_CG_0_SLCG_EN_FALSE                       MK_ENUM_CONST(0)
+#define AODMIC_CG_0_SLCG_EN_TRUE                        MK_ENUM_CONST(1)
+
+
+// Register AODMIC_STATUS_0
+#define AODMIC_STATUS_0                 MK_ADDR_CONST(0x4c)
+#define AODMIC_STATUS_0_SECURE                  0x0
+#define AODMIC_STATUS_0_DUAL                    0x0
+#define AODMIC_STATUS_0_SCR                     0
+#define AODMIC_STATUS_0_SCRREG                  0
+#define AODMIC_STATUS_0_WORD_COUNT                      0x1
+#define AODMIC_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x10)
+#define AODMIC_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x80000131)
+#define AODMIC_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_READ_MASK                       MK_MASK_CONST(0x80000131)
+#define AODMIC_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_CNFG_ERR_SHIFT                  MK_SHIFT_CONST(31)
+#define AODMIC_STATUS_0_CNFG_ERR_FIELD                  MK_FIELD_CONST(0x1, AODMIC_STATUS_0_CNFG_ERR_SHIFT)
+#define AODMIC_STATUS_0_CNFG_ERR_RANGE                  31:31
+#define AODMIC_STATUS_0_CNFG_ERR_MSB                    MK_SHIFT_CONST(31)
+#define AODMIC_STATUS_0_CNFG_ERR_LSB                    MK_SHIFT_CONST(31)
+#define AODMIC_STATUS_0_CNFG_ERR_WOFFSET                        0x0
+#define AODMIC_STATUS_0_CNFG_ERR_DEFAULT                        MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_CNFG_ERR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AODMIC_STATUS_0_CNFG_ERR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_CNFG_ERR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_CNFG_ERR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_CNFG_ERR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AODMIC_STATUS_0_CNFG_ERR_INIT_ENUM                      FALSE
+#define AODMIC_STATUS_0_CNFG_ERR_FALSE                  MK_ENUM_CONST(0)
+#define AODMIC_STATUS_0_CNFG_ERR_TRUE                   MK_ENUM_CONST(1)
+
+#define AODMIC_STATUS_0_SLCG_CLKEN_SHIFT                        MK_SHIFT_CONST(8)
+#define AODMIC_STATUS_0_SLCG_CLKEN_FIELD                        MK_FIELD_CONST(0x1, AODMIC_STATUS_0_SLCG_CLKEN_SHIFT)
+#define AODMIC_STATUS_0_SLCG_CLKEN_RANGE                        8:8
+#define AODMIC_STATUS_0_SLCG_CLKEN_MSB                  MK_SHIFT_CONST(8)
+#define AODMIC_STATUS_0_SLCG_CLKEN_LSB                  MK_SHIFT_CONST(8)
+#define AODMIC_STATUS_0_SLCG_CLKEN_WOFFSET                      0x0
+#define AODMIC_STATUS_0_SLCG_CLKEN_DEFAULT                      MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_SLCG_CLKEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AODMIC_STATUS_0_SLCG_CLKEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_SLCG_CLKEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_SLCG_CLKEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_SLCG_CLKEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AODMIC_STATUS_0_SLCG_CLKEN_INIT_ENUM                    FALSE
+#define AODMIC_STATUS_0_SLCG_CLKEN_FALSE                        MK_ENUM_CONST(0)
+#define AODMIC_STATUS_0_SLCG_CLKEN_TRUE                 MK_ENUM_CONST(1)
+
+#define AODMIC_STATUS_0_FIFO_FULL_SHIFT                 MK_SHIFT_CONST(5)
+#define AODMIC_STATUS_0_FIFO_FULL_FIELD                 MK_FIELD_CONST(0x1, AODMIC_STATUS_0_FIFO_FULL_SHIFT)
+#define AODMIC_STATUS_0_FIFO_FULL_RANGE                 5:5
+#define AODMIC_STATUS_0_FIFO_FULL_MSB                   MK_SHIFT_CONST(5)
+#define AODMIC_STATUS_0_FIFO_FULL_LSB                   MK_SHIFT_CONST(5)
+#define AODMIC_STATUS_0_FIFO_FULL_WOFFSET                       0x0
+#define AODMIC_STATUS_0_FIFO_FULL_DEFAULT                       MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_FIFO_FULL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AODMIC_STATUS_0_FIFO_FULL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_FIFO_FULL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_FIFO_FULL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_FIFO_FULL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AODMIC_STATUS_0_FIFO_FULL_INIT_ENUM                     FALSE
+#define AODMIC_STATUS_0_FIFO_FULL_FALSE                 MK_ENUM_CONST(0)
+#define AODMIC_STATUS_0_FIFO_FULL_TRUE                  MK_ENUM_CONST(1)
+
+#define AODMIC_STATUS_0_FIFO_EMPTY_SHIFT                        MK_SHIFT_CONST(4)
+#define AODMIC_STATUS_0_FIFO_EMPTY_FIELD                        MK_FIELD_CONST(0x1, AODMIC_STATUS_0_FIFO_EMPTY_SHIFT)
+#define AODMIC_STATUS_0_FIFO_EMPTY_RANGE                        4:4
+#define AODMIC_STATUS_0_FIFO_EMPTY_MSB                  MK_SHIFT_CONST(4)
+#define AODMIC_STATUS_0_FIFO_EMPTY_LSB                  MK_SHIFT_CONST(4)
+#define AODMIC_STATUS_0_FIFO_EMPTY_WOFFSET                      0x0
+#define AODMIC_STATUS_0_FIFO_EMPTY_DEFAULT                      MK_MASK_CONST(0x1)
+#define AODMIC_STATUS_0_FIFO_EMPTY_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AODMIC_STATUS_0_FIFO_EMPTY_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_FIFO_EMPTY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_FIFO_EMPTY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_FIFO_EMPTY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AODMIC_STATUS_0_FIFO_EMPTY_INIT_ENUM                    TRUE
+#define AODMIC_STATUS_0_FIFO_EMPTY_FALSE                        MK_ENUM_CONST(0)
+#define AODMIC_STATUS_0_FIFO_EMPTY_TRUE                 MK_ENUM_CONST(1)
+
+#define AODMIC_STATUS_0_ENABLE_STATUS_SHIFT                     MK_SHIFT_CONST(0)
+#define AODMIC_STATUS_0_ENABLE_STATUS_FIELD                     MK_FIELD_CONST(0x1, AODMIC_STATUS_0_ENABLE_STATUS_SHIFT)
+#define AODMIC_STATUS_0_ENABLE_STATUS_RANGE                     0:0
+#define AODMIC_STATUS_0_ENABLE_STATUS_MSB                       MK_SHIFT_CONST(0)
+#define AODMIC_STATUS_0_ENABLE_STATUS_LSB                       MK_SHIFT_CONST(0)
+#define AODMIC_STATUS_0_ENABLE_STATUS_WOFFSET                   0x0
+#define AODMIC_STATUS_0_ENABLE_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_ENABLE_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AODMIC_STATUS_0_ENABLE_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_ENABLE_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_ENABLE_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AODMIC_STATUS_0_ENABLE_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AODMIC_STATUS_0_ENABLE_STATUS_INIT_ENUM                 FALSE
+#define AODMIC_STATUS_0_ENABLE_STATUS_FALSE                     MK_ENUM_CONST(0)
+#define AODMIC_STATUS_0_ENABLE_STATUS_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register AODMIC_INT_STATUS_0
+#define AODMIC_INT_STATUS_0                     MK_ADDR_CONST(0x50)
+#define AODMIC_INT_STATUS_0_SECURE                      0x0
+#define AODMIC_INT_STATUS_0_DUAL                        0x0
+#define AODMIC_INT_STATUS_0_SCR                         0
+#define AODMIC_INT_STATUS_0_SCRREG                      0
+#define AODMIC_INT_STATUS_0_WORD_COUNT                  0x1
+#define AODMIC_INT_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define AODMIC_INT_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x101)
+#define AODMIC_INT_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define AODMIC_INT_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AODMIC_INT_STATUS_0_READ_MASK                   MK_MASK_CONST(0x101)
+#define AODMIC_INT_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define AODMIC_INT_STATUS_0_RX_OVERRUN_SHIFT                    MK_SHIFT_CONST(8)
+#define AODMIC_INT_STATUS_0_RX_OVERRUN_FIELD                    MK_FIELD_CONST(0x1, AODMIC_INT_STATUS_0_RX_OVERRUN_SHIFT)
+#define AODMIC_INT_STATUS_0_RX_OVERRUN_RANGE                    8:8
+#define AODMIC_INT_STATUS_0_RX_OVERRUN_MSB                      MK_SHIFT_CONST(8)
+#define AODMIC_INT_STATUS_0_RX_OVERRUN_LSB                      MK_SHIFT_CONST(8)
+#define AODMIC_INT_STATUS_0_RX_OVERRUN_WOFFSET                  0x0
+#define AODMIC_INT_STATUS_0_RX_OVERRUN_DEFAULT                  MK_MASK_CONST(0x0)
+#define AODMIC_INT_STATUS_0_RX_OVERRUN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AODMIC_INT_STATUS_0_RX_OVERRUN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AODMIC_INT_STATUS_0_RX_OVERRUN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AODMIC_INT_STATUS_0_RX_OVERRUN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AODMIC_INT_STATUS_0_RX_OVERRUN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AODMIC_INT_STATUS_0_RX_OVERRUN_INIT_ENUM                        CLEAR
+#define AODMIC_INT_STATUS_0_RX_OVERRUN_CLEAR                    MK_ENUM_CONST(0)
+#define AODMIC_INT_STATUS_0_RX_OVERRUN_SET                      MK_ENUM_CONST(1)
+
+#define AODMIC_INT_STATUS_0_RX_DONE_SHIFT                       MK_SHIFT_CONST(0)
+#define AODMIC_INT_STATUS_0_RX_DONE_FIELD                       MK_FIELD_CONST(0x1, AODMIC_INT_STATUS_0_RX_DONE_SHIFT)
+#define AODMIC_INT_STATUS_0_RX_DONE_RANGE                       0:0
+#define AODMIC_INT_STATUS_0_RX_DONE_MSB                 MK_SHIFT_CONST(0)
+#define AODMIC_INT_STATUS_0_RX_DONE_LSB                 MK_SHIFT_CONST(0)
+#define AODMIC_INT_STATUS_0_RX_DONE_WOFFSET                     0x0
+#define AODMIC_INT_STATUS_0_RX_DONE_DEFAULT                     MK_MASK_CONST(0x0)
+#define AODMIC_INT_STATUS_0_RX_DONE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AODMIC_INT_STATUS_0_RX_DONE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AODMIC_INT_STATUS_0_RX_DONE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AODMIC_INT_STATUS_0_RX_DONE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AODMIC_INT_STATUS_0_RX_DONE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AODMIC_INT_STATUS_0_RX_DONE_INIT_ENUM                   CLEAR
+#define AODMIC_INT_STATUS_0_RX_DONE_CLEAR                       MK_ENUM_CONST(0)
+#define AODMIC_INT_STATUS_0_RX_DONE_SET                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x54
+
+// Reserved address 0x58
+
+// Reserved address 0x5c
+
+// Reserved address 0x60
+
+// Register AODMIC_CTRL_0
+#define AODMIC_CTRL_0                   MK_ADDR_CONST(0x64)
+#define AODMIC_CTRL_0_SECURE                    0x0
+#define AODMIC_CTRL_0_DUAL                      0x0
+#define AODMIC_CTRL_0_SCR                       0
+#define AODMIC_CTRL_0_SCRREG                    0
+#define AODMIC_CTRL_0_WORD_COUNT                        0x1
+#define AODMIC_CTRL_0_RESET_VAL                         MK_MASK_CONST(0x300)
+#define AODMIC_CTRL_0_RESET_MASK                        MK_MASK_CONST(0x313)
+#define AODMIC_CTRL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define AODMIC_CTRL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AODMIC_CTRL_0_READ_MASK                         MK_MASK_CONST(0x313)
+#define AODMIC_CTRL_0_WRITE_MASK                        MK_MASK_CONST(0x313)
+#define AODMIC_CTRL_0_CHANNEL_SELECT_SHIFT                      MK_SHIFT_CONST(8)
+#define AODMIC_CTRL_0_CHANNEL_SELECT_FIELD                      MK_FIELD_CONST(0x3, AODMIC_CTRL_0_CHANNEL_SELECT_SHIFT)
+#define AODMIC_CTRL_0_CHANNEL_SELECT_RANGE                      9:8
+#define AODMIC_CTRL_0_CHANNEL_SELECT_MSB                        MK_SHIFT_CONST(9)
+#define AODMIC_CTRL_0_CHANNEL_SELECT_LSB                        MK_SHIFT_CONST(8)
+#define AODMIC_CTRL_0_CHANNEL_SELECT_WOFFSET                    0x0
+#define AODMIC_CTRL_0_CHANNEL_SELECT_DEFAULT                    MK_MASK_CONST(0x3)
+#define AODMIC_CTRL_0_CHANNEL_SELECT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define AODMIC_CTRL_0_CHANNEL_SELECT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AODMIC_CTRL_0_CHANNEL_SELECT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AODMIC_CTRL_0_CHANNEL_SELECT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AODMIC_CTRL_0_CHANNEL_SELECT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AODMIC_CTRL_0_CHANNEL_SELECT_INIT_ENUM                  STEREO
+#define AODMIC_CTRL_0_CHANNEL_SELECT_NONE                       MK_ENUM_CONST(0)
+#define AODMIC_CTRL_0_CHANNEL_SELECT_LEFT                       MK_ENUM_CONST(1)
+#define AODMIC_CTRL_0_CHANNEL_SELECT_RIGHT                      MK_ENUM_CONST(2)
+#define AODMIC_CTRL_0_CHANNEL_SELECT_STEREO                     MK_ENUM_CONST(3)
+
+#define AODMIC_CTRL_0_LRSEL_POLARITY_SHIFT                      MK_SHIFT_CONST(4)
+#define AODMIC_CTRL_0_LRSEL_POLARITY_FIELD                      MK_FIELD_CONST(0x1, AODMIC_CTRL_0_LRSEL_POLARITY_SHIFT)
+#define AODMIC_CTRL_0_LRSEL_POLARITY_RANGE                      4:4
+#define AODMIC_CTRL_0_LRSEL_POLARITY_MSB                        MK_SHIFT_CONST(4)
+#define AODMIC_CTRL_0_LRSEL_POLARITY_LSB                        MK_SHIFT_CONST(4)
+#define AODMIC_CTRL_0_LRSEL_POLARITY_WOFFSET                    0x0
+#define AODMIC_CTRL_0_LRSEL_POLARITY_DEFAULT                    MK_MASK_CONST(0x0)
+#define AODMIC_CTRL_0_LRSEL_POLARITY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AODMIC_CTRL_0_LRSEL_POLARITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AODMIC_CTRL_0_LRSEL_POLARITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AODMIC_CTRL_0_LRSEL_POLARITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AODMIC_CTRL_0_LRSEL_POLARITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AODMIC_CTRL_0_LRSEL_POLARITY_INIT_ENUM                  LEFT
+#define AODMIC_CTRL_0_LRSEL_POLARITY_LEFT                       MK_ENUM_CONST(0)
+#define AODMIC_CTRL_0_LRSEL_POLARITY_RIGHT                      MK_ENUM_CONST(1)
+
+#define AODMIC_CTRL_0_OSR_SHIFT                 MK_SHIFT_CONST(0)
+#define AODMIC_CTRL_0_OSR_FIELD                 MK_FIELD_CONST(0x3, AODMIC_CTRL_0_OSR_SHIFT)
+#define AODMIC_CTRL_0_OSR_RANGE                 1:0
+#define AODMIC_CTRL_0_OSR_MSB                   MK_SHIFT_CONST(1)
+#define AODMIC_CTRL_0_OSR_LSB                   MK_SHIFT_CONST(0)
+#define AODMIC_CTRL_0_OSR_WOFFSET                       0x0
+#define AODMIC_CTRL_0_OSR_DEFAULT                       MK_MASK_CONST(0x0)
+#define AODMIC_CTRL_0_OSR_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define AODMIC_CTRL_0_OSR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AODMIC_CTRL_0_OSR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AODMIC_CTRL_0_OSR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AODMIC_CTRL_0_OSR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AODMIC_CTRL_0_OSR_INIT_ENUM                     OSR64
+#define AODMIC_CTRL_0_OSR_OSR64                 MK_ENUM_CONST(0)
+#define AODMIC_CTRL_0_OSR_OSR128                        MK_ENUM_CONST(1)
+#define AODMIC_CTRL_0_OSR_OSR256                        MK_ENUM_CONST(2)
+
+
+// Register AODMIC_CYA_0
+#define AODMIC_CYA_0                    MK_ADDR_CONST(0x68)
+#define AODMIC_CYA_0_SECURE                     0x0
+#define AODMIC_CYA_0_DUAL                       0x0
+#define AODMIC_CYA_0_SCR                        0
+#define AODMIC_CYA_0_SCRREG                     0
+#define AODMIC_CYA_0_WORD_COUNT                         0x1
+#define AODMIC_CYA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define AODMIC_CYA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define AODMIC_CYA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define AODMIC_CYA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AODMIC_CYA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define AODMIC_CYA_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define AODMIC_CYA_0_CYA_SHIFT                  MK_SHIFT_CONST(0)
+#define AODMIC_CYA_0_CYA_FIELD                  MK_FIELD_CONST(0xffffffff, AODMIC_CYA_0_CYA_SHIFT)
+#define AODMIC_CYA_0_CYA_RANGE                  31:0
+#define AODMIC_CYA_0_CYA_MSB                    MK_SHIFT_CONST(31)
+#define AODMIC_CYA_0_CYA_LSB                    MK_SHIFT_CONST(0)
+#define AODMIC_CYA_0_CYA_WOFFSET                        0x0
+#define AODMIC_CYA_0_CYA_DEFAULT                        MK_MASK_CONST(0x0)
+#define AODMIC_CYA_0_CYA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define AODMIC_CYA_0_CYA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AODMIC_CYA_0_CYA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AODMIC_CYA_0_CYA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AODMIC_CYA_0_CYA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register AODMIC_CYA
+#define AODMIC_CYA                      MK_ADDR_CONST(0x68)
+#define AODMIC_CYA_SECURE                       0x0
+#define AODMIC_CYA_DUAL                         0x0
+#define AODMIC_CYA_SCR                  0
+#define AODMIC_CYA_SCRREG                       0
+#define AODMIC_CYA_WORD_COUNT                   0x1
+#define AODMIC_CYA_RESET_VAL                    MK_MASK_CONST(0x0)
+#define AODMIC_CYA_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define AODMIC_CYA_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define AODMIC_CYA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AODMIC_CYA_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define AODMIC_CYA_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define AODMIC_CYA_CYA_SHIFT                    MK_SHIFT_CONST(0)
+#define AODMIC_CYA_CYA_FIELD                    MK_FIELD_CONST(0xffffffff, AODMIC_CYA_CYA_SHIFT)
+#define AODMIC_CYA_CYA_RANGE                    31:0
+#define AODMIC_CYA_CYA_MSB                      MK_SHIFT_CONST(31)
+#define AODMIC_CYA_CYA_LSB                      MK_SHIFT_CONST(0)
+#define AODMIC_CYA_CYA_WOFFSET                  0x0
+#define AODMIC_CYA_CYA_DEFAULT                  MK_MASK_CONST(0x0)
+#define AODMIC_CYA_CYA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define AODMIC_CYA_CYA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AODMIC_CYA_CYA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AODMIC_CYA_CYA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AODMIC_CYA_CYA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register AODMIC_CYA_1
+#define AODMIC_CYA_1                    MK_ADDR_CONST(0x6c)
+#define AODMIC_CYA_1_SECURE                     0x0
+#define AODMIC_CYA_1_DUAL                       0x0
+#define AODMIC_CYA_1_SCR                        0
+#define AODMIC_CYA_1_SCRREG                     0
+#define AODMIC_CYA_1_WORD_COUNT                         0x1
+#define AODMIC_CYA_1_RESET_VAL                  MK_MASK_CONST(0x0)
+#define AODMIC_CYA_1_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define AODMIC_CYA_1_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define AODMIC_CYA_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AODMIC_CYA_1_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define AODMIC_CYA_1_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define AODMIC_CYA_1_CYA_SHIFT                  MK_SHIFT_CONST(0)
+#define AODMIC_CYA_1_CYA_FIELD                  MK_FIELD_CONST(0xffffffff, AODMIC_CYA_1_CYA_SHIFT)
+#define AODMIC_CYA_1_CYA_RANGE                  31:0
+#define AODMIC_CYA_1_CYA_MSB                    MK_SHIFT_CONST(31)
+#define AODMIC_CYA_1_CYA_LSB                    MK_SHIFT_CONST(0)
+#define AODMIC_CYA_1_CYA_WOFFSET                        0x0
+#define AODMIC_CYA_1_CYA_DEFAULT                        MK_MASK_CONST(0x0)
+#define AODMIC_CYA_1_CYA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define AODMIC_CYA_1_CYA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AODMIC_CYA_1_CYA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AODMIC_CYA_1_CYA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AODMIC_CYA_1_CYA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register AODMIC_DBG_CTRL_0
+#define AODMIC_DBG_CTRL_0                       MK_ADDR_CONST(0x70)
+#define AODMIC_DBG_CTRL_0_SECURE                        0x0
+#define AODMIC_DBG_CTRL_0_DUAL                  0x0
+#define AODMIC_DBG_CTRL_0_SCR                   0
+#define AODMIC_DBG_CTRL_0_SCRREG                        0
+#define AODMIC_DBG_CTRL_0_WORD_COUNT                    0x1
+#define AODMIC_DBG_CTRL_0_RESET_VAL                     MK_MASK_CONST(0x2)
+#define AODMIC_DBG_CTRL_0_RESET_MASK                    MK_MASK_CONST(0xf)
+#define AODMIC_DBG_CTRL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define AODMIC_DBG_CTRL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AODMIC_DBG_CTRL_0_READ_MASK                     MK_MASK_CONST(0xf)
+#define AODMIC_DBG_CTRL_0_WRITE_MASK                    MK_MASK_CONST(0xf)
+#define AODMIC_DBG_CTRL_0_DCR_ENABLE_SHIFT                      MK_SHIFT_CONST(3)
+#define AODMIC_DBG_CTRL_0_DCR_ENABLE_FIELD                      MK_FIELD_CONST(0x1, AODMIC_DBG_CTRL_0_DCR_ENABLE_SHIFT)
+#define AODMIC_DBG_CTRL_0_DCR_ENABLE_RANGE                      3:3
+#define AODMIC_DBG_CTRL_0_DCR_ENABLE_MSB                        MK_SHIFT_CONST(3)
+#define AODMIC_DBG_CTRL_0_DCR_ENABLE_LSB                        MK_SHIFT_CONST(3)
+#define AODMIC_DBG_CTRL_0_DCR_ENABLE_WOFFSET                    0x0
+#define AODMIC_DBG_CTRL_0_DCR_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
+#define AODMIC_DBG_CTRL_0_DCR_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AODMIC_DBG_CTRL_0_DCR_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AODMIC_DBG_CTRL_0_DCR_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AODMIC_DBG_CTRL_0_DCR_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AODMIC_DBG_CTRL_0_DCR_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AODMIC_DBG_CTRL_0_DCR_ENABLE_INIT_ENUM                  DISABLE
+#define AODMIC_DBG_CTRL_0_DCR_ENABLE_DISABLE                    MK_ENUM_CONST(0)
+#define AODMIC_DBG_CTRL_0_DCR_ENABLE_ENABLE                     MK_ENUM_CONST(1)
+
+#define AODMIC_DBG_CTRL_0_LP_ENABLE_SHIFT                       MK_SHIFT_CONST(2)
+#define AODMIC_DBG_CTRL_0_LP_ENABLE_FIELD                       MK_FIELD_CONST(0x1, AODMIC_DBG_CTRL_0_LP_ENABLE_SHIFT)
+#define AODMIC_DBG_CTRL_0_LP_ENABLE_RANGE                       2:2
+#define AODMIC_DBG_CTRL_0_LP_ENABLE_MSB                 MK_SHIFT_CONST(2)
+#define AODMIC_DBG_CTRL_0_LP_ENABLE_LSB                 MK_SHIFT_CONST(2)
+#define AODMIC_DBG_CTRL_0_LP_ENABLE_WOFFSET                     0x0
+#define AODMIC_DBG_CTRL_0_LP_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
+#define AODMIC_DBG_CTRL_0_LP_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AODMIC_DBG_CTRL_0_LP_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AODMIC_DBG_CTRL_0_LP_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AODMIC_DBG_CTRL_0_LP_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AODMIC_DBG_CTRL_0_LP_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AODMIC_DBG_CTRL_0_LP_ENABLE_INIT_ENUM                   DISABLE
+#define AODMIC_DBG_CTRL_0_LP_ENABLE_DISABLE                     MK_ENUM_CONST(0)
+#define AODMIC_DBG_CTRL_0_LP_ENABLE_ENABLE                      MK_ENUM_CONST(1)
+
+#define AODMIC_DBG_CTRL_0_SC_ENABLE_SHIFT                       MK_SHIFT_CONST(1)
+#define AODMIC_DBG_CTRL_0_SC_ENABLE_FIELD                       MK_FIELD_CONST(0x1, AODMIC_DBG_CTRL_0_SC_ENABLE_SHIFT)
+#define AODMIC_DBG_CTRL_0_SC_ENABLE_RANGE                       1:1
+#define AODMIC_DBG_CTRL_0_SC_ENABLE_MSB                 MK_SHIFT_CONST(1)
+#define AODMIC_DBG_CTRL_0_SC_ENABLE_LSB                 MK_SHIFT_CONST(1)
+#define AODMIC_DBG_CTRL_0_SC_ENABLE_WOFFSET                     0x0
+#define AODMIC_DBG_CTRL_0_SC_ENABLE_DEFAULT                     MK_MASK_CONST(0x1)
+#define AODMIC_DBG_CTRL_0_SC_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AODMIC_DBG_CTRL_0_SC_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AODMIC_DBG_CTRL_0_SC_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AODMIC_DBG_CTRL_0_SC_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AODMIC_DBG_CTRL_0_SC_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AODMIC_DBG_CTRL_0_SC_ENABLE_INIT_ENUM                   ENABLE
+#define AODMIC_DBG_CTRL_0_SC_ENABLE_DISABLE                     MK_ENUM_CONST(0)
+#define AODMIC_DBG_CTRL_0_SC_ENABLE_ENABLE                      MK_ENUM_CONST(1)
+
+#define AODMIC_DBG_CTRL_0_BYPASS_SHIFT                  MK_SHIFT_CONST(0)
+#define AODMIC_DBG_CTRL_0_BYPASS_FIELD                  MK_FIELD_CONST(0x1, AODMIC_DBG_CTRL_0_BYPASS_SHIFT)
+#define AODMIC_DBG_CTRL_0_BYPASS_RANGE                  0:0
+#define AODMIC_DBG_CTRL_0_BYPASS_MSB                    MK_SHIFT_CONST(0)
+#define AODMIC_DBG_CTRL_0_BYPASS_LSB                    MK_SHIFT_CONST(0)
+#define AODMIC_DBG_CTRL_0_BYPASS_WOFFSET                        0x0
+#define AODMIC_DBG_CTRL_0_BYPASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define AODMIC_DBG_CTRL_0_BYPASS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AODMIC_DBG_CTRL_0_BYPASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AODMIC_DBG_CTRL_0_BYPASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AODMIC_DBG_CTRL_0_BYPASS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AODMIC_DBG_CTRL_0_BYPASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AODMIC_DBG_CTRL_0_BYPASS_INIT_ENUM                      DISABLE
+#define AODMIC_DBG_CTRL_0_BYPASS_DISABLE                        MK_ENUM_CONST(0)
+#define AODMIC_DBG_CTRL_0_BYPASS_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register AODMIC_DCR_FILTER_GAIN_0
+#define AODMIC_DCR_FILTER_GAIN_0                        MK_ADDR_CONST(0x74)
+#define AODMIC_DCR_FILTER_GAIN_0_SECURE                         0x0
+#define AODMIC_DCR_FILTER_GAIN_0_DUAL                   0x0
+#define AODMIC_DCR_FILTER_GAIN_0_SCR                    0
+#define AODMIC_DCR_FILTER_GAIN_0_SCRREG                         0
+#define AODMIC_DCR_FILTER_GAIN_0_WORD_COUNT                     0x1
+#define AODMIC_DCR_FILTER_GAIN_0_RESET_VAL                      MK_MASK_CONST(0x800000)
+#define AODMIC_DCR_FILTER_GAIN_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define AODMIC_DCR_FILTER_GAIN_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define AODMIC_DCR_FILTER_GAIN_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AODMIC_DCR_FILTER_GAIN_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define AODMIC_DCR_FILTER_GAIN_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_SHIFT                   MK_SHIFT_CONST(0)
+#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_FIELD                   MK_FIELD_CONST(0xffffffff, AODMIC_DCR_FILTER_GAIN_0_GAIN_0_SHIFT)
+#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_RANGE                   31:0
+#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_MSB                     MK_SHIFT_CONST(31)
+#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_LSB                     MK_SHIFT_CONST(0)
+#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_WOFFSET                 0x0
+#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_DEFAULT                 MK_MASK_CONST(0x800000)
+#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AODMIC_DCR_FILTER_GAIN_0_GAIN_0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register AODMIC_LP_FILTER_GAIN_0
+#define AODMIC_LP_FILTER_GAIN_0                 MK_ADDR_CONST(0x8c)
+#define AODMIC_LP_FILTER_GAIN_0_SECURE                  0x0
+#define AODMIC_LP_FILTER_GAIN_0_DUAL                    0x0
+#define AODMIC_LP_FILTER_GAIN_0_SCR                     0
+#define AODMIC_LP_FILTER_GAIN_0_SCRREG                  0
+#define AODMIC_LP_FILTER_GAIN_0_WORD_COUNT                      0x1
+#define AODMIC_LP_FILTER_GAIN_0_RESET_VAL                       MK_MASK_CONST(0x4c255a)
+#define AODMIC_LP_FILTER_GAIN_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define AODMIC_LP_FILTER_GAIN_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define AODMIC_LP_FILTER_GAIN_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define AODMIC_LP_FILTER_GAIN_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define AODMIC_LP_FILTER_GAIN_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_SHIFT                    MK_SHIFT_CONST(0)
+#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_FIELD                    MK_FIELD_CONST(0xffffffff, AODMIC_LP_FILTER_GAIN_0_GAIN_0_SHIFT)
+#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_RANGE                    31:0
+#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_MSB                      MK_SHIFT_CONST(31)
+#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_LSB                      MK_SHIFT_CONST(0)
+#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_WOFFSET                  0x0
+#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_DEFAULT                  MK_MASK_CONST(0x4c255a)
+#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AODMIC_LP_FILTER_GAIN_0_GAIN_0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register AODMIC_CORRECTION_FILTER_GAIN_0
+#define AODMIC_CORRECTION_FILTER_GAIN_0                 MK_ADDR_CONST(0xb8)
+#define AODMIC_CORRECTION_FILTER_GAIN_0_SECURE                  0x0
+#define AODMIC_CORRECTION_FILTER_GAIN_0_DUAL                    0x0
+#define AODMIC_CORRECTION_FILTER_GAIN_0_SCR                     0
+#define AODMIC_CORRECTION_FILTER_GAIN_0_SCRREG                  0
+#define AODMIC_CORRECTION_FILTER_GAIN_0_WORD_COUNT                      0x1
+#define AODMIC_CORRECTION_FILTER_GAIN_0_RESET_VAL                       MK_MASK_CONST(0x10628f6)
+#define AODMIC_CORRECTION_FILTER_GAIN_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define AODMIC_CORRECTION_FILTER_GAIN_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define AODMIC_CORRECTION_FILTER_GAIN_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define AODMIC_CORRECTION_FILTER_GAIN_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define AODMIC_CORRECTION_FILTER_GAIN_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_SHIFT                    MK_SHIFT_CONST(0)
+#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_FIELD                    MK_FIELD_CONST(0xffffffff, AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_SHIFT)
+#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_RANGE                    31:0
+#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_MSB                      MK_SHIFT_CONST(31)
+#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_LSB                      MK_SHIFT_CONST(0)
+#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_WOFFSET                  0x0
+#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_DEFAULT                  MK_MASK_CONST(0x10628f6)
+#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AODMIC_CORRECTION_FILTER_GAIN_0_GAIN_0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+#define NV_AODMIC_INT4  4
+#define NV_AODMIC_INT6  6
+#define NV_AODMIC_INT8  8
+#define NV_AODMIC_INT16 16
+#define NV_AODMIC_INT24 24
+#define NV_AODMIC_INT32 32
+#define NV_AODMIC_INT40 40
+#define NV_AODMIC_INT43 43
+#define NV_AODMIC_INT48 48
+#define NV_AODMIC_INT64 64
+#define NV_AODMIC_INT128        128
+#define NV_AODMIC_INT256        256
+#define NV_AODMIC_INT512        512
+#define NV_AODMIC_INT1024       1024
+#define NV_AODMIC_INT1280       1280
+#define NV_AODMIC_MAX_OSR       64
+#define NV_AODMIC_MAX_SYNCDECIMATION_ORDER      5
+#define NV_AODMIC_MIN_OSR       64
+#define NV_AODMIC_DIFF_OUTPUT_WIDTH     16
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAODMIC_REGS(_op_) \
+_op_(AODMIC_APB_FIFO_CTRL_0) \
+_op_(AODMIC_APB_FIFO_CTRL_RD_DATA_0) \
+_op_(AODMIC_APB_FIFO_STATUS_0) \
+_op_(AODMIC_APB_RX_INT_STATUS_0) \
+_op_(AODMIC_APB_RX_INT_MASK_0) \
+_op_(AODMIC_APB_RX_INT_SET_0) \
+_op_(AODMIC_APB_RX_INT_CLEAR_0) \
+_op_(AODMIC_ENABLE_0) \
+_op_(AODMIC_SOFT_RESET_0) \
+_op_(AODMIC_CG_0) \
+_op_(AODMIC_STATUS_0) \
+_op_(AODMIC_INT_STATUS_0) \
+_op_(AODMIC_CTRL_0) \
+_op_(AODMIC_CYA_0) \
+_op_(AODMIC_CYA) \
+_op_(AODMIC_CYA_1) \
+_op_(AODMIC_DBG_CTRL_0) \
+_op_(AODMIC_DCR_FILTER_GAIN_0) \
+_op_(AODMIC_LP_FILTER_GAIN_0) \
+_op_(AODMIC_CORRECTION_FILTER_GAIN_0) \
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_AODMIC_APB 0x00000000
+#define BASE_ADDRESS_AODMIC     0x00000040
+
+//
+// ARAODMIC REGISTER BANKS
+//
+
+#define AODMIC_APB0_FIRST_REG 0x0000 // AODMIC_APB_FIFO_CTRL_0
+#define AODMIC_APB0_LAST_REG 0x0018 // AODMIC_APB_RX_INT_CLEAR_0
+#define AODMIC0_FIRST_REG 0x0040 // AODMIC_ENABLE_0
+#define AODMIC0_LAST_REG 0x0050 // AODMIC_INT_STATUS_0
+#define AODMIC1_FIRST_REG 0x0064 // AODMIC_CTRL_0
+#define AODMIC1_LAST_REG 0x00e0 // AODMIC_CORRECTION_BIQUAD_1_COEF_4_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARAODMIC_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/araoncluster_evp.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/araoncluster_evp.h
new file mode 100644
index 0000000..b1b4ef9
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/araoncluster_evp.h
@@ -0,0 +1,543 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARAONCLUSTER_EVP_H_INC
+#define ARAONCLUSTER_EVP_H_INC
+#define NV_MOBILE_ARAONCLUSTER_EVP_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARAONCLUSTER_EVP_H_SCRREG_NOMENCLATURE INFERRED
+
+
+// Register AONCLUSTER_EVP_RESET_VEC_0
+#define AONCLUSTER_EVP_RESET_VEC_0                      MK_ADDR_CONST(0x0)
+#define AONCLUSTER_EVP_RESET_VEC_0_SECURE                       0x0
+#define AONCLUSTER_EVP_RESET_VEC_0_DUAL                         0x0
+#define AONCLUSTER_EVP_RESET_VEC_0_SCR                  0
+#define AONCLUSTER_EVP_RESET_VEC_0_SCRREG                       0
+#define AONCLUSTER_EVP_RESET_VEC_0_WORD_COUNT                   0x1
+#define AONCLUSTER_EVP_RESET_VEC_0_RESET_VAL                    MK_MASK_CONST(0xe59ff018)
+#define AONCLUSTER_EVP_RESET_VEC_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_RESET_VEC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RESET_VEC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RESET_VEC_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_RESET_VEC_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_SHIFT                 MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_FIELD                 MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_RESET_VEC_0_VECTOR_SHIFT)
+#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_RANGE                 31:0
+#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_MSB                   MK_SHIFT_CONST(31)
+#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_LSB                   MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_WOFFSET                       0x0
+#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_DEFAULT                       MK_MASK_CONST(0xe59ff018)
+#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RESET_VEC_0_VECTOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register AONCLUSTER_EVP_UNDEF_VEC_0
+#define AONCLUSTER_EVP_UNDEF_VEC_0                      MK_ADDR_CONST(0x4)
+#define AONCLUSTER_EVP_UNDEF_VEC_0_SECURE                       0x0
+#define AONCLUSTER_EVP_UNDEF_VEC_0_DUAL                         0x0
+#define AONCLUSTER_EVP_UNDEF_VEC_0_SCR                  0
+#define AONCLUSTER_EVP_UNDEF_VEC_0_SCRREG                       0
+#define AONCLUSTER_EVP_UNDEF_VEC_0_WORD_COUNT                   0x1
+#define AONCLUSTER_EVP_UNDEF_VEC_0_RESET_VAL                    MK_MASK_CONST(0xe59ff018)
+#define AONCLUSTER_EVP_UNDEF_VEC_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_UNDEF_VEC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_UNDEF_VEC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_UNDEF_VEC_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_UNDEF_VEC_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_SHIFT                 MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_FIELD                 MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_SHIFT)
+#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_RANGE                 31:0
+#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_MSB                   MK_SHIFT_CONST(31)
+#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_LSB                   MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_WOFFSET                       0x0
+#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_DEFAULT                       MK_MASK_CONST(0xe59ff018)
+#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_UNDEF_VEC_0_VECTOR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register AONCLUSTER_EVP_SWI_VEC_0
+#define AONCLUSTER_EVP_SWI_VEC_0                        MK_ADDR_CONST(0x8)
+#define AONCLUSTER_EVP_SWI_VEC_0_SECURE                         0x0
+#define AONCLUSTER_EVP_SWI_VEC_0_DUAL                   0x0
+#define AONCLUSTER_EVP_SWI_VEC_0_SCR                    0
+#define AONCLUSTER_EVP_SWI_VEC_0_SCRREG                         0
+#define AONCLUSTER_EVP_SWI_VEC_0_WORD_COUNT                     0x1
+#define AONCLUSTER_EVP_SWI_VEC_0_RESET_VAL                      MK_MASK_CONST(0xe59ff018)
+#define AONCLUSTER_EVP_SWI_VEC_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_SWI_VEC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_SWI_VEC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_SWI_VEC_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_SWI_VEC_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_SHIFT                   MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_FIELD                   MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_SWI_VEC_0_VECTOR_SHIFT)
+#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_RANGE                   31:0
+#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_MSB                     MK_SHIFT_CONST(31)
+#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_LSB                     MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_WOFFSET                 0x0
+#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_DEFAULT                 MK_MASK_CONST(0xe59ff018)
+#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_SWI_VEC_0_VECTOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0                     MK_ADDR_CONST(0xc)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_SECURE                      0x0
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_DUAL                        0x0
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_SCR                         0
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_SCRREG                      0
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_WORD_COUNT                  0x1
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_RESET_VAL                   MK_MASK_CONST(0xe59ff018)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_SHIFT                        MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_FIELD                        MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_SHIFT)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_RANGE                        31:0
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_MSB                  MK_SHIFT_CONST(31)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_LSB                  MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_WOFFSET                      0x0
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_DEFAULT                      MK_MASK_CONST(0xe59ff018)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0_VECTOR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register AONCLUSTER_EVP_DATA_ABORT_VEC_0
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0                 MK_ADDR_CONST(0x10)
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_SECURE                  0x0
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_DUAL                    0x0
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_SCR                     0
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_SCRREG                  0
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_WORD_COUNT                      0x1
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_RESET_VAL                       MK_MASK_CONST(0xe59ff018)
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_SHIFT                    MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_FIELD                    MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_SHIFT)
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_RANGE                    31:0
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_MSB                      MK_SHIFT_CONST(31)
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_LSB                      MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_WOFFSET                  0x0
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_DEFAULT                  MK_MASK_CONST(0xe59ff018)
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_DATA_ABORT_VEC_0_VECTOR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register AONCLUSTER_EVP_RSVD_VEC_0
+#define AONCLUSTER_EVP_RSVD_VEC_0                       MK_ADDR_CONST(0x14)
+#define AONCLUSTER_EVP_RSVD_VEC_0_SECURE                        0x0
+#define AONCLUSTER_EVP_RSVD_VEC_0_DUAL                  0x0
+#define AONCLUSTER_EVP_RSVD_VEC_0_SCR                   0
+#define AONCLUSTER_EVP_RSVD_VEC_0_SCRREG                        0
+#define AONCLUSTER_EVP_RSVD_VEC_0_WORD_COUNT                    0x1
+#define AONCLUSTER_EVP_RSVD_VEC_0_RESET_VAL                     MK_MASK_CONST(0xe59ff018)
+#define AONCLUSTER_EVP_RSVD_VEC_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_RSVD_VEC_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RSVD_VEC_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RSVD_VEC_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_RSVD_VEC_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_SHIFT                  MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_FIELD                  MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_SHIFT)
+#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_RANGE                  31:0
+#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_MSB                    MK_SHIFT_CONST(31)
+#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_LSB                    MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_WOFFSET                        0x0
+#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_DEFAULT                        MK_MASK_CONST(0xe59ff018)
+#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RSVD_VEC_0_VECTOR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register AONCLUSTER_EVP_IRQ_VEC_0
+#define AONCLUSTER_EVP_IRQ_VEC_0                        MK_ADDR_CONST(0x18)
+#define AONCLUSTER_EVP_IRQ_VEC_0_SECURE                         0x0
+#define AONCLUSTER_EVP_IRQ_VEC_0_DUAL                   0x0
+#define AONCLUSTER_EVP_IRQ_VEC_0_SCR                    0
+#define AONCLUSTER_EVP_IRQ_VEC_0_SCRREG                         0
+#define AONCLUSTER_EVP_IRQ_VEC_0_WORD_COUNT                     0x1
+#define AONCLUSTER_EVP_IRQ_VEC_0_RESET_VAL                      MK_MASK_CONST(0xe59ff018)
+#define AONCLUSTER_EVP_IRQ_VEC_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_IRQ_VEC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_IRQ_VEC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_IRQ_VEC_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_IRQ_VEC_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_SHIFT                   MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_FIELD                   MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_SHIFT)
+#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_RANGE                   31:0
+#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_MSB                     MK_SHIFT_CONST(31)
+#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_LSB                     MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_WOFFSET                 0x0
+#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_DEFAULT                 MK_MASK_CONST(0xe59ff018)
+#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_IRQ_VEC_0_VECTOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register AONCLUSTER_EVP_FIQ_VEC_0
+#define AONCLUSTER_EVP_FIQ_VEC_0                        MK_ADDR_CONST(0x1c)
+#define AONCLUSTER_EVP_FIQ_VEC_0_SECURE                         0x0
+#define AONCLUSTER_EVP_FIQ_VEC_0_DUAL                   0x0
+#define AONCLUSTER_EVP_FIQ_VEC_0_SCR                    0
+#define AONCLUSTER_EVP_FIQ_VEC_0_SCRREG                         0
+#define AONCLUSTER_EVP_FIQ_VEC_0_WORD_COUNT                     0x1
+#define AONCLUSTER_EVP_FIQ_VEC_0_RESET_VAL                      MK_MASK_CONST(0xe59ff018)
+#define AONCLUSTER_EVP_FIQ_VEC_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_FIQ_VEC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_FIQ_VEC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_FIQ_VEC_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_FIQ_VEC_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_SHIFT                   MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_FIELD                   MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_SHIFT)
+#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_RANGE                   31:0
+#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_MSB                     MK_SHIFT_CONST(31)
+#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_LSB                     MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_WOFFSET                 0x0
+#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_DEFAULT                 MK_MASK_CONST(0xe59ff018)
+#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_FIQ_VEC_0_VECTOR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register AONCLUSTER_EVP_RESET_ADDR_0
+#define AONCLUSTER_EVP_RESET_ADDR_0                     MK_ADDR_CONST(0x20)
+#define AONCLUSTER_EVP_RESET_ADDR_0_SECURE                      0x0
+#define AONCLUSTER_EVP_RESET_ADDR_0_DUAL                        0x0
+#define AONCLUSTER_EVP_RESET_ADDR_0_SCR                         0
+#define AONCLUSTER_EVP_RESET_ADDR_0_SCRREG                      0
+#define AONCLUSTER_EVP_RESET_ADDR_0_WORD_COUNT                  0x1
+#define AONCLUSTER_EVP_RESET_ADDR_0_RESET_VAL                   MK_MASK_CONST(0xc480000)
+#define AONCLUSTER_EVP_RESET_ADDR_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_RESET_ADDR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RESET_ADDR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RESET_ADDR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_RESET_ADDR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_SHIFT                  MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_FIELD                  MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_RESET_ADDR_0_ADDR_SHIFT)
+#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_RANGE                  31:0
+#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_MSB                    MK_SHIFT_CONST(31)
+#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_LSB                    MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_WOFFSET                        0x0
+#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_DEFAULT                        MK_MASK_CONST(0xc480000)
+#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RESET_ADDR_0_ADDR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register AONCLUSTER_EVP_UNDEF_ADDR_0
+#define AONCLUSTER_EVP_UNDEF_ADDR_0                     MK_ADDR_CONST(0x24)
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_SECURE                      0x0
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_DUAL                        0x0
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_SCR                         0
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_SCRREG                      0
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_WORD_COUNT                  0x1
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_RESET_VAL                   MK_MASK_CONST(0xc480004)
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_SHIFT                  MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_FIELD                  MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_SHIFT)
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_RANGE                  31:0
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_MSB                    MK_SHIFT_CONST(31)
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_LSB                    MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_WOFFSET                        0x0
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_DEFAULT                        MK_MASK_CONST(0xc480004)
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_UNDEF_ADDR_0_ADDR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register AONCLUSTER_EVP_SWI_ADDR_0
+#define AONCLUSTER_EVP_SWI_ADDR_0                       MK_ADDR_CONST(0x28)
+#define AONCLUSTER_EVP_SWI_ADDR_0_SECURE                        0x0
+#define AONCLUSTER_EVP_SWI_ADDR_0_DUAL                  0x0
+#define AONCLUSTER_EVP_SWI_ADDR_0_SCR                   0
+#define AONCLUSTER_EVP_SWI_ADDR_0_SCRREG                        0
+#define AONCLUSTER_EVP_SWI_ADDR_0_WORD_COUNT                    0x1
+#define AONCLUSTER_EVP_SWI_ADDR_0_RESET_VAL                     MK_MASK_CONST(0xc480008)
+#define AONCLUSTER_EVP_SWI_ADDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_SWI_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_SWI_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_SWI_ADDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_SWI_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_SHIFT                    MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_FIELD                    MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_SWI_ADDR_0_ADDR_SHIFT)
+#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_RANGE                    31:0
+#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_LSB                      MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_WOFFSET                  0x0
+#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_DEFAULT                  MK_MASK_CONST(0xc480008)
+#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_SWI_ADDR_0_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0                    MK_ADDR_CONST(0x2c)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_SECURE                     0x0
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_DUAL                       0x0
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_SCR                        0
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_SCRREG                     0
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_WORD_COUNT                         0x1
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_RESET_VAL                  MK_MASK_CONST(0xc48000c)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_SHIFT                 MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_FIELD                 MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_SHIFT)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_RANGE                 31:0
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_MSB                   MK_SHIFT_CONST(31)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_LSB                   MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_WOFFSET                       0x0
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_DEFAULT                       MK_MASK_CONST(0xc48000c)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0_ADDR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register AONCLUSTER_EVP_DATA_ABORT_ADDR_0
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0                        MK_ADDR_CONST(0x30)
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_SECURE                         0x0
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_DUAL                   0x0
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_SCR                    0
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_SCRREG                         0
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_WORD_COUNT                     0x1
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_RESET_VAL                      MK_MASK_CONST(0xc480010)
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_SHIFT                     MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_FIELD                     MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_SHIFT)
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_RANGE                     31:0
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_LSB                       MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_WOFFSET                   0x0
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_DEFAULT                   MK_MASK_CONST(0xc480010)
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_DATA_ABORT_ADDR_0_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register AONCLUSTER_EVP_RSVD_ADDR_0
+#define AONCLUSTER_EVP_RSVD_ADDR_0                      MK_ADDR_CONST(0x34)
+#define AONCLUSTER_EVP_RSVD_ADDR_0_SECURE                       0x0
+#define AONCLUSTER_EVP_RSVD_ADDR_0_DUAL                         0x0
+#define AONCLUSTER_EVP_RSVD_ADDR_0_SCR                  0
+#define AONCLUSTER_EVP_RSVD_ADDR_0_SCRREG                       0
+#define AONCLUSTER_EVP_RSVD_ADDR_0_WORD_COUNT                   0x1
+#define AONCLUSTER_EVP_RSVD_ADDR_0_RESET_VAL                    MK_MASK_CONST(0xc480014)
+#define AONCLUSTER_EVP_RSVD_ADDR_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_RSVD_ADDR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RSVD_ADDR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RSVD_ADDR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_RSVD_ADDR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_SHIFT                   MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_FIELD                   MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_SHIFT)
+#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_RANGE                   31:0
+#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_MSB                     MK_SHIFT_CONST(31)
+#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_LSB                     MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_WOFFSET                 0x0
+#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_DEFAULT                 MK_MASK_CONST(0xc480014)
+#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_RSVD_ADDR_0_ADDR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register AONCLUSTER_EVP_IRQ_ADDR_0
+#define AONCLUSTER_EVP_IRQ_ADDR_0                       MK_ADDR_CONST(0x38)
+#define AONCLUSTER_EVP_IRQ_ADDR_0_SECURE                        0x0
+#define AONCLUSTER_EVP_IRQ_ADDR_0_DUAL                  0x0
+#define AONCLUSTER_EVP_IRQ_ADDR_0_SCR                   0
+#define AONCLUSTER_EVP_IRQ_ADDR_0_SCRREG                        0
+#define AONCLUSTER_EVP_IRQ_ADDR_0_WORD_COUNT                    0x1
+#define AONCLUSTER_EVP_IRQ_ADDR_0_RESET_VAL                     MK_MASK_CONST(0xc480018)
+#define AONCLUSTER_EVP_IRQ_ADDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_IRQ_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_IRQ_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_IRQ_ADDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_IRQ_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_SHIFT                    MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_FIELD                    MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_SHIFT)
+#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_RANGE                    31:0
+#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_LSB                      MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_WOFFSET                  0x0
+#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_DEFAULT                  MK_MASK_CONST(0xc480018)
+#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_IRQ_ADDR_0_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register AONCLUSTER_EVP_FIQ_ADDR_0
+#define AONCLUSTER_EVP_FIQ_ADDR_0                       MK_ADDR_CONST(0x3c)
+#define AONCLUSTER_EVP_FIQ_ADDR_0_SECURE                        0x0
+#define AONCLUSTER_EVP_FIQ_ADDR_0_DUAL                  0x0
+#define AONCLUSTER_EVP_FIQ_ADDR_0_SCR                   0
+#define AONCLUSTER_EVP_FIQ_ADDR_0_SCRREG                        0
+#define AONCLUSTER_EVP_FIQ_ADDR_0_WORD_COUNT                    0x1
+#define AONCLUSTER_EVP_FIQ_ADDR_0_RESET_VAL                     MK_MASK_CONST(0xc48001c)
+#define AONCLUSTER_EVP_FIQ_ADDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_FIQ_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_FIQ_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_FIQ_ADDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_FIQ_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_SHIFT                    MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_FIELD                    MK_FIELD_CONST(0xffffffff, AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_SHIFT)
+#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_RANGE                    31:0
+#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_LSB                      MK_SHIFT_CONST(0)
+#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_WOFFSET                  0x0
+#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_DEFAULT                  MK_MASK_CONST(0xc48001c)
+#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AONCLUSTER_EVP_FIQ_ADDR_0_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAONCLUSTER_EVP_REGS(_op_) \
+_op_(AONCLUSTER_EVP_RESET_VEC_0) \
+_op_(AONCLUSTER_EVP_UNDEF_VEC_0) \
+_op_(AONCLUSTER_EVP_SWI_VEC_0) \
+_op_(AONCLUSTER_EVP_PREFETCH_ABORT_VEC_0) \
+_op_(AONCLUSTER_EVP_DATA_ABORT_VEC_0) \
+_op_(AONCLUSTER_EVP_RSVD_VEC_0) \
+_op_(AONCLUSTER_EVP_IRQ_VEC_0) \
+_op_(AONCLUSTER_EVP_FIQ_VEC_0) \
+_op_(AONCLUSTER_EVP_RESET_ADDR_0) \
+_op_(AONCLUSTER_EVP_UNDEF_ADDR_0) \
+_op_(AONCLUSTER_EVP_SWI_ADDR_0) \
+_op_(AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0) \
+_op_(AONCLUSTER_EVP_DATA_ABORT_ADDR_0) \
+_op_(AONCLUSTER_EVP_RSVD_ADDR_0) \
+_op_(AONCLUSTER_EVP_IRQ_ADDR_0) \
+_op_(AONCLUSTER_EVP_FIQ_ADDR_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_AONCLUSTER_EVP     0x00000000
+
+//
+// ARAONCLUSTER_EVP REGISTER BANKS
+//
+
+#define AONCLUSTER_EVP0_FIRST_REG 0x0000 // AONCLUSTER_EVP_RESET_VEC_0
+#define AONCLUSTER_EVP0_LAST_REG 0x003c // AONCLUSTER_EVP_FIQ_ADDR_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARAONCLUSTER_EVP_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/araopm.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/araopm.h
new file mode 100644
index 0000000..d9522da
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/araopm.h
@@ -0,0 +1,3853 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARAOPM_H_INC
+#define ARAOPM_H_INC
+#define NV_MOBILE_ARAOPM_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARAOPM_H_SCRREG_NOMENCLATURE INFERRED
+
+
+// Register AOPM_SOFT_RESET_0
+#define AOPM_SOFT_RESET_0                       MK_ADDR_CONST(0x0)
+#define AOPM_SOFT_RESET_0_SECURE                        0x0
+#define AOPM_SOFT_RESET_0_DUAL                  0x0
+#define AOPM_SOFT_RESET_0_SCR                   SCR_PRIVATE_0
+#define AOPM_SOFT_RESET_0_SCRREG                        AOPM_SCR_SCR_PRIVATE_0
+#define AOPM_SOFT_RESET_0_WORD_COUNT                    0x1
+#define AOPM_SOFT_RESET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define AOPM_SOFT_RESET_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_SOFT_RESET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define AOPM_SOFT_RESET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_SOFT_RESET_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_SOFT_RESET_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_SOFT_RESET_0_SOFT_RESET_SHIFT                      MK_SHIFT_CONST(0)
+#define AOPM_SOFT_RESET_0_SOFT_RESET_FIELD                      MK_FIELD_CONST(0x1, AOPM_SOFT_RESET_0_SOFT_RESET_SHIFT)
+#define AOPM_SOFT_RESET_0_SOFT_RESET_RANGE                      0:0
+#define AOPM_SOFT_RESET_0_SOFT_RESET_MSB                        MK_SHIFT_CONST(0)
+#define AOPM_SOFT_RESET_0_SOFT_RESET_LSB                        MK_SHIFT_CONST(0)
+#define AOPM_SOFT_RESET_0_SOFT_RESET_WOFFSET                    0x0
+#define AOPM_SOFT_RESET_0_SOFT_RESET_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_SOFT_RESET_0_SOFT_RESET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_SOFT_RESET_0_SOFT_RESET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_SOFT_RESET_0_SOFT_RESET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_SOFT_RESET_0_SOFT_RESET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_SOFT_RESET_0_SOFT_RESET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_SOFT_RESET_0_SOFT_RESET_INIT_ENUM                  FALSE
+#define AOPM_SOFT_RESET_0_SOFT_RESET_FALSE                      MK_ENUM_CONST(0)
+#define AOPM_SOFT_RESET_0_SOFT_RESET_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register AOPM_SLCG_CTRL_0
+#define AOPM_SLCG_CTRL_0                        MK_ADDR_CONST(0x4)
+#define AOPM_SLCG_CTRL_0_SECURE                         0x0
+#define AOPM_SLCG_CTRL_0_DUAL                   0x0
+#define AOPM_SLCG_CTRL_0_SCR                    SCR_PRIVATE_0
+#define AOPM_SLCG_CTRL_0_SCRREG                         AOPM_SCR_SCR_PRIVATE_0
+#define AOPM_SLCG_CTRL_0_WORD_COUNT                     0x1
+#define AOPM_SLCG_CTRL_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define AOPM_SLCG_CTRL_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define AOPM_SLCG_CTRL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define AOPM_SLCG_CTRL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_SLCG_CTRL_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define AOPM_SLCG_CTRL_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_FIELD                      MK_FIELD_CONST(0x1, AOPM_SLCG_CTRL_0_APB_SLCG_EN_SHIFT)
+#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_RANGE                      0:0
+#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_MSB                        MK_SHIFT_CONST(0)
+#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_LSB                        MK_SHIFT_CONST(0)
+#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_WOFFSET                    0x0
+#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_INIT_ENUM                  DISABLE
+#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_DISABLE                    MK_ENUM_CONST(0)
+#define AOPM_SLCG_CTRL_0_APB_SLCG_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_SHIFT                       MK_SHIFT_CONST(1)
+#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_FIELD                       MK_FIELD_CONST(0x1, AOPM_SLCG_CTRL_0_PM_SLCG_EN_SHIFT)
+#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_RANGE                       1:1
+#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_MSB                 MK_SHIFT_CONST(1)
+#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_LSB                 MK_SHIFT_CONST(1)
+#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_WOFFSET                     0x0
+#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_INIT_ENUM                   DISABLE
+#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_DISABLE                     MK_ENUM_CONST(0)
+#define AOPM_SLCG_CTRL_0_PM_SLCG_EN_ENABLE                      MK_ENUM_CONST(1)
+
+
+// Register AOPM_TGT_PWR_STATE_0
+#define AOPM_TGT_PWR_STATE_0                    MK_ADDR_CONST(0x8)
+#define AOPM_TGT_PWR_STATE_0_SECURE                     0x0
+#define AOPM_TGT_PWR_STATE_0_DUAL                       0x0
+#define AOPM_TGT_PWR_STATE_0_SCR                        SCR_SHARED_0
+#define AOPM_TGT_PWR_STATE_0_SCRREG                     AOPM_SCR_SCR_SHARED_0
+#define AOPM_TGT_PWR_STATE_0_WORD_COUNT                         0x1
+#define AOPM_TGT_PWR_STATE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define AOPM_TGT_PWR_STATE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define AOPM_TGT_PWR_STATE_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define AOPM_TGT_PWR_STATE_0_STATE_SHIFT                        MK_SHIFT_CONST(0)
+#define AOPM_TGT_PWR_STATE_0_STATE_FIELD                        MK_FIELD_CONST(0xf, AOPM_TGT_PWR_STATE_0_STATE_SHIFT)
+#define AOPM_TGT_PWR_STATE_0_STATE_RANGE                        3:0
+#define AOPM_TGT_PWR_STATE_0_STATE_MSB                  MK_SHIFT_CONST(3)
+#define AOPM_TGT_PWR_STATE_0_STATE_LSB                  MK_SHIFT_CONST(0)
+#define AOPM_TGT_PWR_STATE_0_STATE_WOFFSET                      0x0
+#define AOPM_TGT_PWR_STATE_0_STATE_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_STATE_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define AOPM_TGT_PWR_STATE_0_STATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_STATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_STATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_STATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_STATE_0_STATE_INIT_ENUM                    ACTIVE
+#define AOPM_TGT_PWR_STATE_0_STATE_ACTIVE                       MK_ENUM_CONST(0)
+#define AOPM_TGT_PWR_STATE_0_STATE_IDLE                 MK_ENUM_CONST(1)
+#define AOPM_TGT_PWR_STATE_0_STATE_STANDBY                      MK_ENUM_CONST(2)
+#define AOPM_TGT_PWR_STATE_0_STATE_DORMANT                      MK_ENUM_CONST(3)
+
+#define AOPM_TGT_PWR_STATE_0_RAM_PPG_SHIFT                      MK_SHIFT_CONST(4)
+#define AOPM_TGT_PWR_STATE_0_RAM_PPG_FIELD                      MK_FIELD_CONST(0x1, AOPM_TGT_PWR_STATE_0_RAM_PPG_SHIFT)
+#define AOPM_TGT_PWR_STATE_0_RAM_PPG_RANGE                      4:4
+#define AOPM_TGT_PWR_STATE_0_RAM_PPG_MSB                        MK_SHIFT_CONST(4)
+#define AOPM_TGT_PWR_STATE_0_RAM_PPG_LSB                        MK_SHIFT_CONST(4)
+#define AOPM_TGT_PWR_STATE_0_RAM_PPG_WOFFSET                    0x0
+#define AOPM_TGT_PWR_STATE_0_RAM_PPG_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_RAM_PPG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_STATE_0_RAM_PPG_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_RAM_PPG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_RAM_PPG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_RAM_PPG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_STATE_0_RAM_PPG_INIT_ENUM                  DISABLE
+#define AOPM_TGT_PWR_STATE_0_RAM_PPG_DISABLE                    MK_ENUM_CONST(0)
+#define AOPM_TGT_PWR_STATE_0_RAM_PPG_ENABLE                     MK_ENUM_CONST(1)
+
+#define AOPM_TGT_PWR_STATE_0_RAM_RET_SHIFT                      MK_SHIFT_CONST(5)
+#define AOPM_TGT_PWR_STATE_0_RAM_RET_FIELD                      MK_FIELD_CONST(0x1, AOPM_TGT_PWR_STATE_0_RAM_RET_SHIFT)
+#define AOPM_TGT_PWR_STATE_0_RAM_RET_RANGE                      5:5
+#define AOPM_TGT_PWR_STATE_0_RAM_RET_MSB                        MK_SHIFT_CONST(5)
+#define AOPM_TGT_PWR_STATE_0_RAM_RET_LSB                        MK_SHIFT_CONST(5)
+#define AOPM_TGT_PWR_STATE_0_RAM_RET_WOFFSET                    0x0
+#define AOPM_TGT_PWR_STATE_0_RAM_RET_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_RAM_RET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_STATE_0_RAM_RET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_RAM_RET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_RAM_RET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_RAM_RET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_STATE_0_RAM_RET_INIT_ENUM                  DISABLE
+#define AOPM_TGT_PWR_STATE_0_RAM_RET_DISABLE                    MK_ENUM_CONST(0)
+#define AOPM_TGT_PWR_STATE_0_RAM_RET_ENABLE                     MK_ENUM_CONST(1)
+
+#define AOPM_TGT_PWR_STATE_0_RAIL_RET_SHIFT                     MK_SHIFT_CONST(6)
+#define AOPM_TGT_PWR_STATE_0_RAIL_RET_FIELD                     MK_FIELD_CONST(0x1, AOPM_TGT_PWR_STATE_0_RAIL_RET_SHIFT)
+#define AOPM_TGT_PWR_STATE_0_RAIL_RET_RANGE                     6:6
+#define AOPM_TGT_PWR_STATE_0_RAIL_RET_MSB                       MK_SHIFT_CONST(6)
+#define AOPM_TGT_PWR_STATE_0_RAIL_RET_LSB                       MK_SHIFT_CONST(6)
+#define AOPM_TGT_PWR_STATE_0_RAIL_RET_WOFFSET                   0x0
+#define AOPM_TGT_PWR_STATE_0_RAIL_RET_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_RAIL_RET_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_STATE_0_RAIL_RET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_RAIL_RET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_RAIL_RET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_RAIL_RET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_STATE_0_RAIL_RET_INIT_ENUM                 DISABLE
+#define AOPM_TGT_PWR_STATE_0_RAIL_RET_DISABLE                   MK_ENUM_CONST(0)
+#define AOPM_TGT_PWR_STATE_0_RAIL_RET_ENABLE                    MK_ENUM_CONST(1)
+
+#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_SHIFT                       MK_SHIFT_CONST(7)
+#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_FIELD                       MK_FIELD_CONST(0x1, AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_SHIFT)
+#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_RANGE                       7:7
+#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_MSB                 MK_SHIFT_CONST(7)
+#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_LSB                 MK_SHIFT_CONST(7)
+#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_WOFFSET                     0x0
+#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_INIT_ENUM                   DISABLE
+#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_DISABLE                     MK_ENUM_CONST(0)
+#define AOPM_TGT_PWR_STATE_0_BYPASS_TWOSTEP_ENABLE                      MK_ENUM_CONST(1)
+
+
+// Register AOPM_TCM_RET_TIMER_0
+#define AOPM_TCM_RET_TIMER_0                    MK_ADDR_CONST(0xc)
+#define AOPM_TCM_RET_TIMER_0_SECURE                     0x0
+#define AOPM_TCM_RET_TIMER_0_DUAL                       0x0
+#define AOPM_TCM_RET_TIMER_0_SCR                        SCR_SHARED_0
+#define AOPM_TCM_RET_TIMER_0_SCRREG                     AOPM_SCR_SCR_SHARED_0
+#define AOPM_TCM_RET_TIMER_0_WORD_COUNT                         0x1
+#define AOPM_TCM_RET_TIMER_0_RESET_VAL                  MK_MASK_CONST(0x10)
+#define AOPM_TCM_RET_TIMER_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define AOPM_TCM_RET_TIMER_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define AOPM_TCM_RET_TIMER_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_TCM_RET_TIMER_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define AOPM_TCM_RET_TIMER_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define AOPM_TCM_RET_TIMER_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define AOPM_TCM_RET_TIMER_0_VAL_FIELD                  MK_FIELD_CONST(0xffffffff, AOPM_TCM_RET_TIMER_0_VAL_SHIFT)
+#define AOPM_TCM_RET_TIMER_0_VAL_RANGE                  31:0
+#define AOPM_TCM_RET_TIMER_0_VAL_MSB                    MK_SHIFT_CONST(31)
+#define AOPM_TCM_RET_TIMER_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define AOPM_TCM_RET_TIMER_0_VAL_WOFFSET                        0x0
+#define AOPM_TCM_RET_TIMER_0_VAL_DEFAULT                        MK_MASK_CONST(0x10)
+#define AOPM_TCM_RET_TIMER_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define AOPM_TCM_RET_TIMER_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_TCM_RET_TIMER_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_TCM_RET_TIMER_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_TCM_RET_TIMER_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register AOPM_DBG_TIMER_0
+#define AOPM_DBG_TIMER_0                        MK_ADDR_CONST(0x10)
+#define AOPM_DBG_TIMER_0_SECURE                         0x0
+#define AOPM_DBG_TIMER_0_DUAL                   0x0
+#define AOPM_DBG_TIMER_0_SCR                    SCR_SHARED_0
+#define AOPM_DBG_TIMER_0_SCRREG                         AOPM_SCR_SCR_SHARED_0
+#define AOPM_DBG_TIMER_0_WORD_COUNT                     0x1
+#define AOPM_DBG_TIMER_0_RESET_VAL                      MK_MASK_CONST(0x10)
+#define AOPM_DBG_TIMER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define AOPM_DBG_TIMER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define AOPM_DBG_TIMER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_DBG_TIMER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define AOPM_DBG_TIMER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define AOPM_DBG_TIMER_0_VAL_SHIFT                      MK_SHIFT_CONST(0)
+#define AOPM_DBG_TIMER_0_VAL_FIELD                      MK_FIELD_CONST(0xffffffff, AOPM_DBG_TIMER_0_VAL_SHIFT)
+#define AOPM_DBG_TIMER_0_VAL_RANGE                      31:0
+#define AOPM_DBG_TIMER_0_VAL_MSB                        MK_SHIFT_CONST(31)
+#define AOPM_DBG_TIMER_0_VAL_LSB                        MK_SHIFT_CONST(0)
+#define AOPM_DBG_TIMER_0_VAL_WOFFSET                    0x0
+#define AOPM_DBG_TIMER_0_VAL_DEFAULT                    MK_MASK_CONST(0x10)
+#define AOPM_DBG_TIMER_0_VAL_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define AOPM_DBG_TIMER_0_VAL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_DBG_TIMER_0_VAL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_DBG_TIMER_0_VAL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_DBG_TIMER_0_VAL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register AOPM_LP_EXIT_0
+#define AOPM_LP_EXIT_0                  MK_ADDR_CONST(0x14)
+#define AOPM_LP_EXIT_0_SECURE                   0x0
+#define AOPM_LP_EXIT_0_DUAL                     0x0
+#define AOPM_LP_EXIT_0_SCR                      SCR_SHARED_0
+#define AOPM_LP_EXIT_0_SCRREG                   AOPM_SCR_SCR_SHARED_0
+#define AOPM_LP_EXIT_0_WORD_COUNT                       0x1
+#define AOPM_LP_EXIT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define AOPM_LP_EXIT_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_LP_EXIT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define AOPM_LP_EXIT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_LP_EXIT_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define AOPM_LP_EXIT_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_LP_EXIT_0_EXIT_SHIFT                       MK_SHIFT_CONST(0)
+#define AOPM_LP_EXIT_0_EXIT_FIELD                       MK_FIELD_CONST(0x1, AOPM_LP_EXIT_0_EXIT_SHIFT)
+#define AOPM_LP_EXIT_0_EXIT_RANGE                       0:0
+#define AOPM_LP_EXIT_0_EXIT_MSB                 MK_SHIFT_CONST(0)
+#define AOPM_LP_EXIT_0_EXIT_LSB                 MK_SHIFT_CONST(0)
+#define AOPM_LP_EXIT_0_EXIT_WOFFSET                     0x0
+#define AOPM_LP_EXIT_0_EXIT_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_LP_EXIT_0_EXIT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AOPM_LP_EXIT_0_EXIT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_LP_EXIT_0_EXIT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_LP_EXIT_0_EXIT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AOPM_LP_EXIT_0_EXIT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AOPM_LP_EXIT_0_EXIT_DONE                        MK_ENUM_CONST(0)
+#define AOPM_LP_EXIT_0_EXIT_PENDING                     MK_ENUM_CONST(1)
+
+
+// Register AOPM_POWER_CFG_MASK_0
+#define AOPM_POWER_CFG_MASK_0                   MK_ADDR_CONST(0x18)
+#define AOPM_POWER_CFG_MASK_0_SECURE                    0x0
+#define AOPM_POWER_CFG_MASK_0_DUAL                      0x0
+#define AOPM_POWER_CFG_MASK_0_SCR                       SCR_PRIVATE_0
+#define AOPM_POWER_CFG_MASK_0_SCRREG                    AOPM_SCR_SCR_PRIVATE_0
+#define AOPM_POWER_CFG_MASK_0_WORD_COUNT                        0x1
+#define AOPM_POWER_CFG_MASK_0_RESET_VAL                         MK_MASK_CONST(0x400070)
+#define AOPM_POWER_CFG_MASK_0_RESET_MASK                        MK_MASK_CONST(0x7f0777)
+#define AOPM_POWER_CFG_MASK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_READ_MASK                         MK_MASK_CONST(0x7f0777)
+#define AOPM_POWER_CFG_MASK_0_WRITE_MASK                        MK_MASK_CONST(0x7f0777)
+#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_SHIFT                    MK_SHIFT_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_FIELD                    MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_WFI_IDLE_SHIFT)
+#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_RANGE                    0:0
+#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_MSB                      MK_SHIFT_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_LSB                      MK_SHIFT_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_WOFFSET                  0x0
+#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_INIT_ENUM                        UNMASK
+#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_UNMASK                   MK_ENUM_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_WFI_IDLE_MASK                     MK_ENUM_CONST(1)
+
+#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_SHIFT                 MK_SHIFT_CONST(1)
+#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_FIELD                 MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_WFI_STANDBY_SHIFT)
+#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_RANGE                 1:1
+#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_MSB                   MK_SHIFT_CONST(1)
+#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_LSB                   MK_SHIFT_CONST(1)
+#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_WOFFSET                       0x0
+#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_INIT_ENUM                     UNMASK
+#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_UNMASK                        MK_ENUM_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_WFI_STANDBY_MASK                  MK_ENUM_CONST(1)
+
+#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_SHIFT                 MK_SHIFT_CONST(2)
+#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_FIELD                 MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_WFI_DORMANT_SHIFT)
+#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_RANGE                 2:2
+#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_MSB                   MK_SHIFT_CONST(2)
+#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_LSB                   MK_SHIFT_CONST(2)
+#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_WOFFSET                       0x0
+#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_INIT_ENUM                     UNMASK
+#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_UNMASK                        MK_ENUM_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_WFI_DORMANT_MASK                  MK_ENUM_CONST(1)
+
+#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_SHIFT                    MK_SHIFT_CONST(4)
+#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_FIELD                    MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_WFE_IDLE_SHIFT)
+#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_RANGE                    4:4
+#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_MSB                      MK_SHIFT_CONST(4)
+#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_LSB                      MK_SHIFT_CONST(4)
+#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_WOFFSET                  0x0
+#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_DEFAULT                  MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_INIT_ENUM                        MASK
+#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_UNMASK                   MK_ENUM_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_WFE_IDLE_MASK                     MK_ENUM_CONST(1)
+
+#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_SHIFT                 MK_SHIFT_CONST(5)
+#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_FIELD                 MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_WFE_STANDBY_SHIFT)
+#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_RANGE                 5:5
+#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_MSB                   MK_SHIFT_CONST(5)
+#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_LSB                   MK_SHIFT_CONST(5)
+#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_WOFFSET                       0x0
+#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_DEFAULT                       MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_INIT_ENUM                     MASK
+#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_UNMASK                        MK_ENUM_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_WFE_STANDBY_MASK                  MK_ENUM_CONST(1)
+
+#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_SHIFT                 MK_SHIFT_CONST(6)
+#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_FIELD                 MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_WFE_DORMANT_SHIFT)
+#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_RANGE                 6:6
+#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_MSB                   MK_SHIFT_CONST(6)
+#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_LSB                   MK_SHIFT_CONST(6)
+#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_WOFFSET                       0x0
+#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_DEFAULT                       MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_INIT_ENUM                     MASK
+#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_UNMASK                        MK_ENUM_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_WFE_DORMANT_MASK                  MK_ENUM_CONST(1)
+
+#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_SHIFT                    MK_SHIFT_CONST(8)
+#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_FIELD                    MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_TGT_IDLE_SHIFT)
+#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_RANGE                    8:8
+#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_MSB                      MK_SHIFT_CONST(8)
+#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_LSB                      MK_SHIFT_CONST(8)
+#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_WOFFSET                  0x0
+#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_INIT_ENUM                        UNMASK
+#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_UNMASK                   MK_ENUM_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_TGT_IDLE_MASK                     MK_ENUM_CONST(1)
+
+#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_SHIFT                 MK_SHIFT_CONST(9)
+#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_FIELD                 MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_TGT_STANDBY_SHIFT)
+#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_RANGE                 9:9
+#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_MSB                   MK_SHIFT_CONST(9)
+#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_LSB                   MK_SHIFT_CONST(9)
+#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_WOFFSET                       0x0
+#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_INIT_ENUM                     UNMASK
+#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_UNMASK                        MK_ENUM_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_TGT_STANDBY_MASK                  MK_ENUM_CONST(1)
+
+#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_SHIFT                 MK_SHIFT_CONST(10)
+#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_FIELD                 MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_TGT_DORMANT_SHIFT)
+#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_RANGE                 10:10
+#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_MSB                   MK_SHIFT_CONST(10)
+#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_LSB                   MK_SHIFT_CONST(10)
+#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_WOFFSET                       0x0
+#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_INIT_ENUM                     UNMASK
+#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_UNMASK                        MK_ENUM_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_TGT_DORMANT_MASK                  MK_ENUM_CONST(1)
+
+#define AOPM_POWER_CFG_MASK_0_RAM_PPG_SHIFT                     MK_SHIFT_CONST(16)
+#define AOPM_POWER_CFG_MASK_0_RAM_PPG_FIELD                     MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_RAM_PPG_SHIFT)
+#define AOPM_POWER_CFG_MASK_0_RAM_PPG_RANGE                     16:16
+#define AOPM_POWER_CFG_MASK_0_RAM_PPG_MSB                       MK_SHIFT_CONST(16)
+#define AOPM_POWER_CFG_MASK_0_RAM_PPG_LSB                       MK_SHIFT_CONST(16)
+#define AOPM_POWER_CFG_MASK_0_RAM_PPG_WOFFSET                   0x0
+#define AOPM_POWER_CFG_MASK_0_RAM_PPG_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_RAM_PPG_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_RAM_PPG_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_RAM_PPG_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_RAM_PPG_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_RAM_PPG_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_RAM_PPG_INIT_ENUM                 UNMASK
+#define AOPM_POWER_CFG_MASK_0_RAM_PPG_UNMASK                    MK_ENUM_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_RAM_PPG_MASK                      MK_ENUM_CONST(1)
+
+#define AOPM_POWER_CFG_MASK_0_RAM_RET_SHIFT                     MK_SHIFT_CONST(17)
+#define AOPM_POWER_CFG_MASK_0_RAM_RET_FIELD                     MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_RAM_RET_SHIFT)
+#define AOPM_POWER_CFG_MASK_0_RAM_RET_RANGE                     17:17
+#define AOPM_POWER_CFG_MASK_0_RAM_RET_MSB                       MK_SHIFT_CONST(17)
+#define AOPM_POWER_CFG_MASK_0_RAM_RET_LSB                       MK_SHIFT_CONST(17)
+#define AOPM_POWER_CFG_MASK_0_RAM_RET_WOFFSET                   0x0
+#define AOPM_POWER_CFG_MASK_0_RAM_RET_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_RAM_RET_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_RAM_RET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_RAM_RET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_RAM_RET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_RAM_RET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_RAM_RET_INIT_ENUM                 UNMASK
+#define AOPM_POWER_CFG_MASK_0_RAM_RET_UNMASK                    MK_ENUM_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_RAM_RET_MASK                      MK_ENUM_CONST(1)
+
+#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_SHIFT                 MK_SHIFT_CONST(18)
+#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_FIELD                 MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_SHIFT)
+#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_RANGE                 18:18
+#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_MSB                   MK_SHIFT_CONST(18)
+#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_LSB                   MK_SHIFT_CONST(18)
+#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_WOFFSET                       0x0
+#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_INIT_ENUM                     ENABLE
+#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_DISABLE                       MK_ENUM_CONST(1)
+#define AOPM_POWER_CFG_MASK_0_PWRGATE_DIS_ENABLE                        MK_ENUM_CONST(0)
+
+#define AOPM_POWER_CFG_MASK_0_RAIL_RET_SHIFT                    MK_SHIFT_CONST(19)
+#define AOPM_POWER_CFG_MASK_0_RAIL_RET_FIELD                    MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_RAIL_RET_SHIFT)
+#define AOPM_POWER_CFG_MASK_0_RAIL_RET_RANGE                    19:19
+#define AOPM_POWER_CFG_MASK_0_RAIL_RET_MSB                      MK_SHIFT_CONST(19)
+#define AOPM_POWER_CFG_MASK_0_RAIL_RET_LSB                      MK_SHIFT_CONST(19)
+#define AOPM_POWER_CFG_MASK_0_RAIL_RET_WOFFSET                  0x0
+#define AOPM_POWER_CFG_MASK_0_RAIL_RET_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_RAIL_RET_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_RAIL_RET_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_RAIL_RET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_RAIL_RET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_RAIL_RET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_RAIL_RET_INIT_ENUM                        UNMASK
+#define AOPM_POWER_CFG_MASK_0_RAIL_RET_UNMASK                   MK_ENUM_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_RAIL_RET_MASK                     MK_ENUM_CONST(1)
+
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_SHIFT                        MK_SHIFT_CONST(20)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_FIELD                        MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_SHIFT)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_RANGE                        20:20
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_MSB                  MK_SHIFT_CONST(20)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_LSB                  MK_SHIFT_CONST(20)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_WOFFSET                      0x0
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_INIT_ENUM                    OFF
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_OFF                  MK_ENUM_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_I_ON                   MK_ENUM_CONST(1)
+
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_SHIFT                        MK_SHIFT_CONST(21)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_FIELD                        MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_SHIFT)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_RANGE                        21:21
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_MSB                  MK_SHIFT_CONST(21)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_LSB                  MK_SHIFT_CONST(21)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_WOFFSET                      0x0
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_INIT_ENUM                    OFF
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_OFF                  MK_ENUM_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_S_ON                   MK_ENUM_CONST(1)
+
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_SHIFT                        MK_SHIFT_CONST(22)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_FIELD                        MK_FIELD_CONST(0x1, AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_SHIFT)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_RANGE                        22:22
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_MSB                  MK_SHIFT_CONST(22)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_LSB                  MK_SHIFT_CONST(22)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_WOFFSET                      0x0
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_DEFAULT                      MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_INIT_ENUM                    ON
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_OFF                  MK_ENUM_CONST(0)
+#define AOPM_POWER_CFG_MASK_0_ALLOW_DEEP_D_ON                   MK_ENUM_CONST(1)
+
+
+// Register AOPM_TGT_PWR_CFG_ORIDE_0
+#define AOPM_TGT_PWR_CFG_ORIDE_0                        MK_ADDR_CONST(0x1c)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_SECURE                         0x0
+#define AOPM_TGT_PWR_CFG_ORIDE_0_DUAL                   0x0
+#define AOPM_TGT_PWR_CFG_ORIDE_0_SCR                    SCR_PRIVATE_0
+#define AOPM_TGT_PWR_CFG_ORIDE_0_SCRREG                         AOPM_SCR_SCR_PRIVATE_0
+#define AOPM_TGT_PWR_CFG_ORIDE_0_WORD_COUNT                     0x1
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RESET_MASK                     MK_MASK_CONST(0x800000ff)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_READ_MASK                      MK_MASK_CONST(0x800000ff)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_WRITE_MASK                     MK_MASK_CONST(0x800000ff)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_SHIFT                    MK_SHIFT_CONST(0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_FIELD                    MK_FIELD_CONST(0xf, AOPM_TGT_PWR_CFG_ORIDE_0_STATE_SHIFT)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_RANGE                    3:0
+#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_MSB                      MK_SHIFT_CONST(3)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_LSB                      MK_SHIFT_CONST(0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_WOFFSET                  0x0
+#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_DEFAULT_MASK                     MK_MASK_CONST(0xf)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_INIT_ENUM                        ACTIVE
+#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_ACTIVE                   MK_ENUM_CONST(0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_IDLE                     MK_ENUM_CONST(1)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_STANDBY                  MK_ENUM_CONST(2)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_STATE_DORMANT                  MK_ENUM_CONST(3)
+
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_SHIFT                  MK_SHIFT_CONST(4)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_FIELD                  MK_FIELD_CONST(0x1, AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_SHIFT)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_RANGE                  4:4
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_MSB                    MK_SHIFT_CONST(4)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_LSB                    MK_SHIFT_CONST(4)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_WOFFSET                        0x0
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_INIT_ENUM                      DISABLE
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_DISABLE                        MK_ENUM_CONST(0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_PPG_ENABLE                 MK_ENUM_CONST(1)
+
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_SHIFT                  MK_SHIFT_CONST(5)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_FIELD                  MK_FIELD_CONST(0x1, AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_SHIFT)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_RANGE                  5:5
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_MSB                    MK_SHIFT_CONST(5)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_LSB                    MK_SHIFT_CONST(5)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_WOFFSET                        0x0
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_INIT_ENUM                      DISABLE
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_DISABLE                        MK_ENUM_CONST(0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAM_RET_ENABLE                 MK_ENUM_CONST(1)
+
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_SHIFT                 MK_SHIFT_CONST(6)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_FIELD                 MK_FIELD_CONST(0x1, AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_SHIFT)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_RANGE                 6:6
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_MSB                   MK_SHIFT_CONST(6)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_LSB                   MK_SHIFT_CONST(6)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_WOFFSET                       0x0
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_INIT_ENUM                     DISABLE
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_DISABLE                       MK_ENUM_CONST(0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_RAIL_RET_ENABLE                        MK_ENUM_CONST(1)
+
+#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_SHIFT                   MK_SHIFT_CONST(7)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_FIELD                   MK_FIELD_CONST(0x1, AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_SHIFT)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_RANGE                   7:7
+#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_MSB                     MK_SHIFT_CONST(7)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_LSB                     MK_SHIFT_CONST(7)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_WOFFSET                 0x0
+#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_INIT_ENUM                       DISABLE
+#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_DISABLE                 MK_ENUM_CONST(0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_BYPASS_TWOSTEP_ENABLE                  MK_ENUM_CONST(1)
+
+#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_SHIFT                 MK_SHIFT_CONST(31)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_FIELD                 MK_FIELD_CONST(0x1, AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_SHIFT)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_RANGE                 31:31
+#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_MSB                   MK_SHIFT_CONST(31)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_LSB                   MK_SHIFT_CONST(31)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_WOFFSET                       0x0
+#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_INIT_ENUM                     DISABLE
+#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_DISABLE                       MK_ENUM_CONST(0)
+#define AOPM_TGT_PWR_CFG_ORIDE_0_ORIDE_EN_ENABLE                        MK_ENUM_CONST(1)
+
+
+// Register AOPM_PWR_STATUS_0
+#define AOPM_PWR_STATUS_0                       MK_ADDR_CONST(0x20)
+#define AOPM_PWR_STATUS_0_SECURE                        0x0
+#define AOPM_PWR_STATUS_0_DUAL                  0x0
+#define AOPM_PWR_STATUS_0_SCR                   0
+#define AOPM_PWR_STATUS_0_SCRREG                        0
+#define AOPM_PWR_STATUS_0_WORD_COUNT                    0x1
+#define AOPM_PWR_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x4600000)
+#define AOPM_PWR_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7ffffc0)
+#define AOPM_PWR_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7ffffc0)
+#define AOPM_PWR_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_TCM_RET_SHIFT                 MK_SHIFT_CONST(6)
+#define AOPM_PWR_STATUS_0_TCM_RET_FIELD                 MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_TCM_RET_SHIFT)
+#define AOPM_PWR_STATUS_0_TCM_RET_RANGE                 6:6
+#define AOPM_PWR_STATUS_0_TCM_RET_MSB                   MK_SHIFT_CONST(6)
+#define AOPM_PWR_STATUS_0_TCM_RET_LSB                   MK_SHIFT_CONST(6)
+#define AOPM_PWR_STATUS_0_TCM_RET_WOFFSET                       0x0
+#define AOPM_PWR_STATUS_0_TCM_RET_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_TCM_RET_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_TCM_RET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_TCM_RET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_TCM_RET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_TCM_RET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_TCM_RET_INIT_ENUM                     ACTIVE
+#define AOPM_PWR_STATUS_0_TCM_RET_ACTIVE                        MK_ENUM_CONST(0)
+#define AOPM_PWR_STATUS_0_TCM_RET_RET                   MK_ENUM_CONST(1)
+
+#define AOPM_PWR_STATUS_0_RAIL_SHIFT                    MK_SHIFT_CONST(7)
+#define AOPM_PWR_STATUS_0_RAIL_FIELD                    MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_RAIL_SHIFT)
+#define AOPM_PWR_STATUS_0_RAIL_RANGE                    7:7
+#define AOPM_PWR_STATUS_0_RAIL_MSB                      MK_SHIFT_CONST(7)
+#define AOPM_PWR_STATUS_0_RAIL_LSB                      MK_SHIFT_CONST(7)
+#define AOPM_PWR_STATUS_0_RAIL_WOFFSET                  0x0
+#define AOPM_PWR_STATUS_0_RAIL_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_RAIL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_RAIL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_RAIL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_RAIL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_RAIL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_RAIL_INIT_ENUM                        ACTIVE
+#define AOPM_PWR_STATUS_0_RAIL_ACTIVE                   MK_ENUM_CONST(0)
+#define AOPM_PWR_STATUS_0_RAIL_RET                      MK_ENUM_CONST(1)
+
+#define AOPM_PWR_STATUS_0_STATE_SHIFT                   MK_SHIFT_CONST(8)
+#define AOPM_PWR_STATUS_0_STATE_FIELD                   MK_FIELD_CONST(0xf, AOPM_PWR_STATUS_0_STATE_SHIFT)
+#define AOPM_PWR_STATUS_0_STATE_RANGE                   11:8
+#define AOPM_PWR_STATUS_0_STATE_MSB                     MK_SHIFT_CONST(11)
+#define AOPM_PWR_STATUS_0_STATE_LSB                     MK_SHIFT_CONST(8)
+#define AOPM_PWR_STATUS_0_STATE_WOFFSET                 0x0
+#define AOPM_PWR_STATUS_0_STATE_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_STATE_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define AOPM_PWR_STATUS_0_STATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_STATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_STATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_STATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_STATE_INIT_ENUM                       ACTIVE
+#define AOPM_PWR_STATUS_0_STATE_ACTIVE                  MK_ENUM_CONST(0)
+#define AOPM_PWR_STATUS_0_STATE_IDLE_SHALLOW                    MK_ENUM_CONST(1)
+#define AOPM_PWR_STATUS_0_STATE_IDLE_DEEP                       MK_ENUM_CONST(2)
+#define AOPM_PWR_STATUS_0_STATE_STANDBY_SHALLOW                 MK_ENUM_CONST(3)
+#define AOPM_PWR_STATUS_0_STATE_STANDBY_DEEP                    MK_ENUM_CONST(4)
+#define AOPM_PWR_STATUS_0_STATE_DORMANT_SHALLOW                 MK_ENUM_CONST(5)
+#define AOPM_PWR_STATUS_0_STATE_DORMANT_DEEP                    MK_ENUM_CONST(6)
+
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_SHIFT                      MK_SHIFT_CONST(12)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_FIELD                      MK_FIELD_CONST(0xf, AOPM_PWR_STATUS_0_EXIT_CAUSE_SHIFT)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_RANGE                      15:12
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_MSB                        MK_SHIFT_CONST(15)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_LSB                        MK_SHIFT_CONST(12)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_WOFFSET                    0x0
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_DEFAULT_MASK                       MK_MASK_CONST(0xf)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_INIT_ENUM                  NONE
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_NONE                       MK_ENUM_CONST(0)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_SWTRIG                     MK_ENUM_CONST(1)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_DMA_ACTIVE                 MK_ENUM_CONST(2)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_IRQ                        MK_ENUM_CONST(3)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_FIQ                        MK_ENUM_CONST(4)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_WAKE                       MK_ENUM_CONST(5)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_RTC_ALARM                  MK_ENUM_CONST(6)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_DBG_TIMEOUT                        MK_ENUM_CONST(7)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_WFI                        MK_ENUM_CONST(8)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_WFE                        MK_ENUM_CONST(9)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_CLKSTOPPED                 MK_ENUM_CONST(10)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_SC7                        MK_ENUM_CONST(11)
+#define AOPM_PWR_STATUS_0_EXIT_CAUSE_AXIP                       MK_ENUM_CONST(12)
+
+#define AOPM_PWR_STATUS_0_LAST_LP_STATE_SHIFT                   MK_SHIFT_CONST(16)
+#define AOPM_PWR_STATUS_0_LAST_LP_STATE_FIELD                   MK_FIELD_CONST(0x3, AOPM_PWR_STATUS_0_LAST_LP_STATE_SHIFT)
+#define AOPM_PWR_STATUS_0_LAST_LP_STATE_RANGE                   17:16
+#define AOPM_PWR_STATUS_0_LAST_LP_STATE_MSB                     MK_SHIFT_CONST(17)
+#define AOPM_PWR_STATUS_0_LAST_LP_STATE_LSB                     MK_SHIFT_CONST(16)
+#define AOPM_PWR_STATUS_0_LAST_LP_STATE_WOFFSET                 0x0
+#define AOPM_PWR_STATUS_0_LAST_LP_STATE_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_LAST_LP_STATE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define AOPM_PWR_STATUS_0_LAST_LP_STATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_LAST_LP_STATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_LAST_LP_STATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_LAST_LP_STATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_LAST_LP_STATE_INIT_ENUM                       NONE
+#define AOPM_PWR_STATUS_0_LAST_LP_STATE_NONE                    MK_ENUM_CONST(0)
+#define AOPM_PWR_STATUS_0_LAST_LP_STATE_IDLE                    MK_ENUM_CONST(1)
+#define AOPM_PWR_STATUS_0_LAST_LP_STATE_STANDBY                 MK_ENUM_CONST(2)
+#define AOPM_PWR_STATUS_0_LAST_LP_STATE_DORMANT                 MK_ENUM_CONST(3)
+
+#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_SHIFT                     MK_SHIFT_CONST(18)
+#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_FIELD                     MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_SHIFT)
+#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_RANGE                     18:18
+#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_MSB                       MK_SHIFT_CONST(18)
+#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_LSB                       MK_SHIFT_CONST(18)
+#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_WOFFSET                   0x0
+#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_INIT_ENUM                 FALSE
+#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_FALSE                     MK_ENUM_CONST(0)
+#define AOPM_PWR_STATUS_0_LAST_EXIT_FROM_DEEP_TRUE                      MK_ENUM_CONST(1)
+
+#define AOPM_PWR_STATUS_0_EXIT_STATUS_SHIFT                     MK_SHIFT_CONST(19)
+#define AOPM_PWR_STATUS_0_EXIT_STATUS_FIELD                     MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_EXIT_STATUS_SHIFT)
+#define AOPM_PWR_STATUS_0_EXIT_STATUS_RANGE                     19:19
+#define AOPM_PWR_STATUS_0_EXIT_STATUS_MSB                       MK_SHIFT_CONST(19)
+#define AOPM_PWR_STATUS_0_EXIT_STATUS_LSB                       MK_SHIFT_CONST(19)
+#define AOPM_PWR_STATUS_0_EXIT_STATUS_WOFFSET                   0x0
+#define AOPM_PWR_STATUS_0_EXIT_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_EXIT_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_EXIT_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_EXIT_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_EXIT_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_EXIT_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_EXIT_STATUS_INIT_ENUM                 DONE
+#define AOPM_PWR_STATUS_0_EXIT_STATUS_DONE                      MK_ENUM_CONST(0)
+#define AOPM_PWR_STATUS_0_EXIT_STATUS_EXITING                   MK_ENUM_CONST(1)
+
+#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_SHIFT                     MK_SHIFT_CONST(20)
+#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_FIELD                     MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_ACTIVE_TYPE_SHIFT)
+#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_RANGE                     20:20
+#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_MSB                       MK_SHIFT_CONST(20)
+#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_LSB                       MK_SHIFT_CONST(20)
+#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_WOFFSET                   0x0
+#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_INIT_ENUM                 ACTIVE
+#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_ACTIVE                    MK_ENUM_CONST(0)
+#define AOPM_PWR_STATUS_0_ACTIVE_TYPE_ACTIVE_IRQFIQ                     MK_ENUM_CONST(1)
+
+#define AOPM_PWR_STATUS_0_nWFI_SHIFT                    MK_SHIFT_CONST(21)
+#define AOPM_PWR_STATUS_0_nWFI_FIELD                    MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_nWFI_SHIFT)
+#define AOPM_PWR_STATUS_0_nWFI_RANGE                    21:21
+#define AOPM_PWR_STATUS_0_nWFI_MSB                      MK_SHIFT_CONST(21)
+#define AOPM_PWR_STATUS_0_nWFI_LSB                      MK_SHIFT_CONST(21)
+#define AOPM_PWR_STATUS_0_nWFI_WOFFSET                  0x0
+#define AOPM_PWR_STATUS_0_nWFI_DEFAULT                  MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_nWFI_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_nWFI_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_nWFI_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_nWFI_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_nWFI_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define AOPM_PWR_STATUS_0_nWFE_SHIFT                    MK_SHIFT_CONST(22)
+#define AOPM_PWR_STATUS_0_nWFE_FIELD                    MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_nWFE_SHIFT)
+#define AOPM_PWR_STATUS_0_nWFE_RANGE                    22:22
+#define AOPM_PWR_STATUS_0_nWFE_MSB                      MK_SHIFT_CONST(22)
+#define AOPM_PWR_STATUS_0_nWFE_LSB                      MK_SHIFT_CONST(22)
+#define AOPM_PWR_STATUS_0_nWFE_WOFFSET                  0x0
+#define AOPM_PWR_STATUS_0_nWFE_DEFAULT                  MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_nWFE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_nWFE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_nWFE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_nWFE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_nWFE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_SHIFT                        MK_SHIFT_CONST(23)
+#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_FIELD                        MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_SKIPPING_RAILRET_SHIFT)
+#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_RANGE                        23:23
+#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_MSB                  MK_SHIFT_CONST(23)
+#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_LSB                  MK_SHIFT_CONST(23)
+#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_WOFFSET                      0x0
+#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_INIT_ENUM                    FALSE
+#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_FALSE                        MK_ENUM_CONST(0)
+#define AOPM_PWR_STATUS_0_SKIPPING_RAILRET_TRUE                 MK_ENUM_CONST(1)
+
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_SHIFT                  MK_SHIFT_CONST(24)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_FIELD                  MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_LAST_LP_DID_PG_SHIFT)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_RANGE                  24:24
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_MSB                    MK_SHIFT_CONST(24)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_LSB                    MK_SHIFT_CONST(24)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_WOFFSET                        0x0
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_INIT_ENUM                      FALSE
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_FALSE                  MK_ENUM_CONST(0)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_PG_TRUE                   MK_ENUM_CONST(1)
+
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_SHIFT                 MK_SHIFT_CONST(25)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_FIELD                 MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_LAST_LP_DID_RST_SHIFT)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_RANGE                 25:25
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_MSB                   MK_SHIFT_CONST(25)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_LSB                   MK_SHIFT_CONST(25)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_WOFFSET                       0x0
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_INIT_ENUM                     FALSE
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_FALSE                 MK_ENUM_CONST(0)
+#define AOPM_PWR_STATUS_0_LAST_LP_DID_RST_TRUE                  MK_ENUM_CONST(1)
+
+#define AOPM_PWR_STATUS_0_nCLKSTOPPED_SHIFT                     MK_SHIFT_CONST(26)
+#define AOPM_PWR_STATUS_0_nCLKSTOPPED_FIELD                     MK_FIELD_CONST(0x1, AOPM_PWR_STATUS_0_nCLKSTOPPED_SHIFT)
+#define AOPM_PWR_STATUS_0_nCLKSTOPPED_RANGE                     26:26
+#define AOPM_PWR_STATUS_0_nCLKSTOPPED_MSB                       MK_SHIFT_CONST(26)
+#define AOPM_PWR_STATUS_0_nCLKSTOPPED_LSB                       MK_SHIFT_CONST(26)
+#define AOPM_PWR_STATUS_0_nCLKSTOPPED_WOFFSET                   0x0
+#define AOPM_PWR_STATUS_0_nCLKSTOPPED_DEFAULT                   MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_nCLKSTOPPED_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_PWR_STATUS_0_nCLKSTOPPED_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_nCLKSTOPPED_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_nCLKSTOPPED_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_PWR_STATUS_0_nCLKSTOPPED_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register AOPM_DBG_STATUS_0
+#define AOPM_DBG_STATUS_0                       MK_ADDR_CONST(0x24)
+#define AOPM_DBG_STATUS_0_SECURE                        0x0
+#define AOPM_DBG_STATUS_0_DUAL                  0x0
+#define AOPM_DBG_STATUS_0_SCR                   0
+#define AOPM_DBG_STATUS_0_SCRREG                        0
+#define AOPM_DBG_STATUS_0_WORD_COUNT                    0x1
+#define AOPM_DBG_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x1ffff3)
+#define AOPM_DBG_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_READ_MASK                     MK_MASK_CONST(0x1ffff3)
+#define AOPM_DBG_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_SHIFT                 MK_SHIFT_CONST(0)
+#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_FIELD                 MK_FIELD_CONST(0x3, AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_SHIFT)
+#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_RANGE                 1:0
+#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_MSB                   MK_SHIFT_CONST(1)
+#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_LSB                   MK_SHIFT_CONST(0)
+#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_WOFFSET                       0x0
+#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_INIT_ENUM                     NONE
+#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_NONE                  MK_ENUM_CONST(0)
+#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_IDLE                  MK_ENUM_CONST(1)
+#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_STANDBY                       MK_ENUM_CONST(2)
+#define AOPM_DBG_STATUS_0_FSM_IN_PROGRESS_DORMANT                       MK_ENUM_CONST(3)
+
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_SHIFT                 MK_SHIFT_CONST(4)
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_FIELD                 MK_FIELD_CONST(0xf, AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_SHIFT)
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_RANGE                 7:4
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_MSB                   MK_SHIFT_CONST(7)
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_LSB                   MK_SHIFT_CONST(4)
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_WOFFSET                       0x0
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_INIT_ENUM                     PMI_ACTIVE
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_PMI_ACTIVE                    MK_ENUM_CONST(0)
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_PMI_CARREQ_H                  MK_ENUM_CONST(1)
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_PMI_CARREQ_L                  MK_ENUM_CONST(2)
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_PMI_IDLE_SHALLOW                      MK_ENUM_CONST(3)
+#define AOPM_DBG_STATUS_0_CSTATE_IDLE_FSM_PMI_IDLE_DEEP                 MK_ENUM_CONST(4)
+
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_SHIFT                      MK_SHIFT_CONST(8)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_FIELD                      MK_FIELD_CONST(0xf, AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_SHIFT)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_RANGE                      11:8
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_MSB                        MK_SHIFT_CONST(11)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_LSB                        MK_SHIFT_CONST(8)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_WOFFSET                    0x0
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_DEFAULT_MASK                       MK_MASK_CONST(0xf)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_INIT_ENUM                  PMS_ACTIVE
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_ACTIVE                 MK_ENUM_CONST(0)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_CARREQ_H                       MK_ENUM_CONST(1)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_CARREQ_L                       MK_ENUM_CONST(2)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_RET_WAIT                       MK_ENUM_CONST(3)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_RAMRET_IN                      MK_ENUM_CONST(4)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_RAMRET_OUT                     MK_ENUM_CONST(5)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_RAILRET                        MK_ENUM_CONST(6)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_STANDBY_SHALLOW                        MK_ENUM_CONST(7)
+#define AOPM_DBG_STATUS_0_CSTATE_STANDBY_FSM_PMS_STANDBY_DEEP                   MK_ENUM_CONST(8)
+
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_SHIFT                      MK_SHIFT_CONST(12)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_FIELD                      MK_FIELD_CONST(0x1f, AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_SHIFT)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_RANGE                      16:12
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_MSB                        MK_SHIFT_CONST(16)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_LSB                        MK_SHIFT_CONST(12)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_WOFFSET                    0x0
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_DEFAULT_MASK                       MK_MASK_CONST(0x1f)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_INIT_ENUM                  PMD_ACTIVE
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_ACTIVE                 MK_ENUM_CONST(0)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_CARREQ_H                       MK_ENUM_CONST(1)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_CARREQ_L                       MK_ENUM_CONST(2)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_RAMRET_IN                      MK_ENUM_CONST(4)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_RAILRET                        MK_ENUM_CONST(5)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_RST_ASRT                       MK_ENUM_CONST(6)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_PG                     MK_ENUM_CONST(7)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_OSCOFF                 MK_ENUM_CONST(8)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_OSCON                  MK_ENUM_CONST(9)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_UPG                    MK_ENUM_CONST(10)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_RST_DEASRT                     MK_ENUM_CONST(11)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_RAMRET_OUT                     MK_ENUM_CONST(12)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_DORMANT_S                      MK_ENUM_CONST(13)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_DORMANT_D                      MK_ENUM_CONST(14)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_NOC_IDLE_ACK_H                 MK_ENUM_CONST(15)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_NOC_IDLE_H                     MK_ENUM_CONST(16)
+#define AOPM_DBG_STATUS_0_CSTATE_DORMANT_FSM_PMD_NOC_IDLE_ACK_L                 MK_ENUM_CONST(17)
+
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_SHIFT                       MK_SHIFT_CONST(17)
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_FIELD                       MK_FIELD_CONST(0xf, AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_SHIFT)
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_RANGE                       20:17
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_MSB                 MK_SHIFT_CONST(20)
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_LSB                 MK_SHIFT_CONST(17)
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_WOFFSET                     0x0
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_INIT_ENUM                   PMA_ACTIVE
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_PMA_ACTIVE                  MK_ENUM_CONST(0)
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_PMA_CARREQ_H                        MK_ENUM_CONST(1)
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_PMA_CARREQ_L                        MK_ENUM_CONST(2)
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_PMA_WAIT_LP                 MK_ENUM_CONST(3)
+#define AOPM_DBG_STATUS_0_CSTATE_IRQFIQ_FSM_PMA_ACT_IRQFIQ                      MK_ENUM_CONST(4)
+
+
+// Register AOPM_DBG_FEATURES_0
+#define AOPM_DBG_FEATURES_0                     MK_ADDR_CONST(0x28)
+#define AOPM_DBG_FEATURES_0_SECURE                      0x0
+#define AOPM_DBG_FEATURES_0_DUAL                        0x0
+#define AOPM_DBG_FEATURES_0_SCR                         SCR_PRIVATE_0
+#define AOPM_DBG_FEATURES_0_SCRREG                      AOPM_SCR_SCR_PRIVATE_0
+#define AOPM_DBG_FEATURES_0_WORD_COUNT                  0x1
+#define AOPM_DBG_FEATURES_0_RESET_VAL                   MK_MASK_CONST(0x1c4)
+#define AOPM_DBG_FEATURES_0_RESET_MASK                  MK_MASK_CONST(0x3ff)
+#define AOPM_DBG_FEATURES_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_READ_MASK                   MK_MASK_CONST(0x3ff)
+#define AOPM_DBG_FEATURES_0_WRITE_MASK                  MK_MASK_CONST(0x3ff)
+#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_SHIFT                     MK_SHIFT_CONST(0)
+#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_FIELD                     MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_SHIFT)
+#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_RANGE                     0:0
+#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_MSB                       MK_SHIFT_CONST(0)
+#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_LSB                       MK_SHIFT_CONST(0)
+#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_WOFFSET                   0x0
+#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_SKIP_DDORMANT_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define AOPM_DBG_FEATURES_0_FORCE_START_SHIFT                   MK_SHIFT_CONST(1)
+#define AOPM_DBG_FEATURES_0_FORCE_START_FIELD                   MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_FORCE_START_SHIFT)
+#define AOPM_DBG_FEATURES_0_FORCE_START_RANGE                   1:1
+#define AOPM_DBG_FEATURES_0_FORCE_START_MSB                     MK_SHIFT_CONST(1)
+#define AOPM_DBG_FEATURES_0_FORCE_START_LSB                     MK_SHIFT_CONST(1)
+#define AOPM_DBG_FEATURES_0_FORCE_START_WOFFSET                 0x0
+#define AOPM_DBG_FEATURES_0_FORCE_START_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_FORCE_START_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_FORCE_START_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_FORCE_START_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_FORCE_START_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_FORCE_START_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_SHIFT                    MK_SHIFT_CONST(2)
+#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_FIELD                    MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_SHIFT)
+#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_RANGE                    2:2
+#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_MSB                      MK_SHIFT_CONST(2)
+#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_LSB                      MK_SHIFT_CONST(2)
+#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_WOFFSET                  0x0
+#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_DEFAULT                  MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_INIT_ENUM                        ENABLE
+#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_DISABLE                  MK_ENUM_CONST(0)
+#define AOPM_DBG_FEATURES_0_NOC_PG_UPG_IN_PATH_ENABLE                   MK_ENUM_CONST(1)
+
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_SHIFT                        MK_SHIFT_CONST(3)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_FIELD                        MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_SHIFT)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_RANGE                        3:3
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_MSB                  MK_SHIFT_CONST(3)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_LSB                  MK_SHIFT_CONST(3)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_WOFFSET                      0x0
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_INIT_ENUM                    DISABLE
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_DISABLE                      MK_ENUM_CONST(0)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_H_ENABLE                       MK_ENUM_CONST(1)
+
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_SHIFT                        MK_SHIFT_CONST(4)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_FIELD                        MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_SHIFT)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_RANGE                        4:4
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_MSB                  MK_SHIFT_CONST(4)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_LSB                  MK_SHIFT_CONST(4)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_WOFFSET                      0x0
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_INIT_ENUM                    DISABLE
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_DISABLE                      MK_ENUM_CONST(0)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_ACK_L_ENABLE                       MK_ENUM_CONST(1)
+
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_SHIFT                    MK_SHIFT_CONST(5)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_FIELD                    MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_SHIFT)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_RANGE                    5:5
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_MSB                      MK_SHIFT_CONST(5)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_LSB                      MK_SHIFT_CONST(5)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_WOFFSET                  0x0
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_INIT_ENUM                        DISABLE
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_DISABLE                  MK_ENUM_CONST(0)
+#define AOPM_DBG_FEATURES_0_FAKE_NOC2PM_IDLE_H_ENABLE                   MK_ENUM_CONST(1)
+
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_SHIFT                     MK_SHIFT_CONST(6)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_FIELD                     MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_SHIFT)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_RANGE                     6:6
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_MSB                       MK_SHIFT_CONST(6)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_LSB                       MK_SHIFT_CONST(6)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_WOFFSET                   0x0
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_DEFAULT                   MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_INIT_ENUM                 INCLUDE
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_EXCLUDE                   MK_ENUM_CONST(0)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_H_INCLUDE                   MK_ENUM_CONST(1)
+
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_SHIFT                     MK_SHIFT_CONST(7)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_FIELD                     MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_SHIFT)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_RANGE                     7:7
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_MSB                       MK_SHIFT_CONST(7)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_LSB                       MK_SHIFT_CONST(7)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_WOFFSET                   0x0
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_DEFAULT                   MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_INIT_ENUM                 INCLUDE
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_EXCLUDE                   MK_ENUM_CONST(0)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_ACK_L_INCLUDE                   MK_ENUM_CONST(1)
+
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_SHIFT                 MK_SHIFT_CONST(8)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_FIELD                 MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_SHIFT)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_RANGE                 8:8
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_MSB                   MK_SHIFT_CONST(8)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_LSB                   MK_SHIFT_CONST(8)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_WOFFSET                       0x0
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_DEFAULT                       MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_INIT_ENUM                     INCLUDE
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_EXCLUDE                       MK_ENUM_CONST(0)
+#define AOPM_DBG_FEATURES_0_CS_NOC_IDLE_H_INCLUDE                       MK_ENUM_CONST(1)
+
+#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_SHIFT                        MK_SHIFT_CONST(9)
+#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_FIELD                        MK_FIELD_CONST(0x1, AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_SHIFT)
+#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_RANGE                        9:9
+#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_MSB                  MK_SHIFT_CONST(9)
+#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_LSB                  MK_SHIFT_CONST(9)
+#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_WOFFSET                      0x0
+#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_DBG_FEATURES_0_PMC2PM_RET_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register AOPM_EXIT_MASK_0
+#define AOPM_EXIT_MASK_0                        MK_ADDR_CONST(0x2c)
+#define AOPM_EXIT_MASK_0_SECURE                         0x0
+#define AOPM_EXIT_MASK_0_DUAL                   0x0
+#define AOPM_EXIT_MASK_0_SCR                    SCR_SHARED_0
+#define AOPM_EXIT_MASK_0_SCRREG                         AOPM_SCR_SCR_SHARED_0
+#define AOPM_EXIT_MASK_0_WORD_COUNT                     0x1
+#define AOPM_EXIT_MASK_0_RESET_VAL                      MK_MASK_CONST(0xa0)
+#define AOPM_EXIT_MASK_0_RESET_MASK                     MK_MASK_CONST(0x3ff)
+#define AOPM_EXIT_MASK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_READ_MASK                      MK_MASK_CONST(0x3ff)
+#define AOPM_EXIT_MASK_0_WRITE_MASK                     MK_MASK_CONST(0x3ff)
+#define AOPM_EXIT_MASK_0_DMA_ACTIVE_SHIFT                       MK_SHIFT_CONST(0)
+#define AOPM_EXIT_MASK_0_DMA_ACTIVE_FIELD                       MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_DMA_ACTIVE_SHIFT)
+#define AOPM_EXIT_MASK_0_DMA_ACTIVE_RANGE                       0:0
+#define AOPM_EXIT_MASK_0_DMA_ACTIVE_MSB                 MK_SHIFT_CONST(0)
+#define AOPM_EXIT_MASK_0_DMA_ACTIVE_LSB                 MK_SHIFT_CONST(0)
+#define AOPM_EXIT_MASK_0_DMA_ACTIVE_WOFFSET                     0x0
+#define AOPM_EXIT_MASK_0_DMA_ACTIVE_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_DMA_ACTIVE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_DMA_ACTIVE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_DMA_ACTIVE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_DMA_ACTIVE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_DMA_ACTIVE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_DMA_ACTIVE_INIT_ENUM                   UNMASK
+#define AOPM_EXIT_MASK_0_DMA_ACTIVE_UNMASK                      MK_ENUM_CONST(0)
+#define AOPM_EXIT_MASK_0_DMA_ACTIVE_MASK                        MK_ENUM_CONST(1)
+
+#define AOPM_EXIT_MASK_0_IRQ_SHIFT                      MK_SHIFT_CONST(1)
+#define AOPM_EXIT_MASK_0_IRQ_FIELD                      MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_IRQ_SHIFT)
+#define AOPM_EXIT_MASK_0_IRQ_RANGE                      1:1
+#define AOPM_EXIT_MASK_0_IRQ_MSB                        MK_SHIFT_CONST(1)
+#define AOPM_EXIT_MASK_0_IRQ_LSB                        MK_SHIFT_CONST(1)
+#define AOPM_EXIT_MASK_0_IRQ_WOFFSET                    0x0
+#define AOPM_EXIT_MASK_0_IRQ_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_IRQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_IRQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_IRQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_IRQ_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_IRQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_IRQ_INIT_ENUM                  UNMASK
+#define AOPM_EXIT_MASK_0_IRQ_UNMASK                     MK_ENUM_CONST(0)
+#define AOPM_EXIT_MASK_0_IRQ_MASK                       MK_ENUM_CONST(1)
+
+#define AOPM_EXIT_MASK_0_FIQ_SHIFT                      MK_SHIFT_CONST(2)
+#define AOPM_EXIT_MASK_0_FIQ_FIELD                      MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_FIQ_SHIFT)
+#define AOPM_EXIT_MASK_0_FIQ_RANGE                      2:2
+#define AOPM_EXIT_MASK_0_FIQ_MSB                        MK_SHIFT_CONST(2)
+#define AOPM_EXIT_MASK_0_FIQ_LSB                        MK_SHIFT_CONST(2)
+#define AOPM_EXIT_MASK_0_FIQ_WOFFSET                    0x0
+#define AOPM_EXIT_MASK_0_FIQ_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_FIQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_FIQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_FIQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_FIQ_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_FIQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_FIQ_INIT_ENUM                  UNMASK
+#define AOPM_EXIT_MASK_0_FIQ_UNMASK                     MK_ENUM_CONST(0)
+#define AOPM_EXIT_MASK_0_FIQ_MASK                       MK_ENUM_CONST(1)
+
+#define AOPM_EXIT_MASK_0_T0_WAKE_SHIFT                  MK_SHIFT_CONST(3)
+#define AOPM_EXIT_MASK_0_T0_WAKE_FIELD                  MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_T0_WAKE_SHIFT)
+#define AOPM_EXIT_MASK_0_T0_WAKE_RANGE                  3:3
+#define AOPM_EXIT_MASK_0_T0_WAKE_MSB                    MK_SHIFT_CONST(3)
+#define AOPM_EXIT_MASK_0_T0_WAKE_LSB                    MK_SHIFT_CONST(3)
+#define AOPM_EXIT_MASK_0_T0_WAKE_WOFFSET                        0x0
+#define AOPM_EXIT_MASK_0_T0_WAKE_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_T0_WAKE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_T0_WAKE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_T0_WAKE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_T0_WAKE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_T0_WAKE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_T0_WAKE_INIT_ENUM                      UNMASK
+#define AOPM_EXIT_MASK_0_T0_WAKE_UNMASK                 MK_ENUM_CONST(0)
+#define AOPM_EXIT_MASK_0_T0_WAKE_MASK                   MK_ENUM_CONST(1)
+
+#define AOPM_EXIT_MASK_0_RTC_ALARM_SHIFT                        MK_SHIFT_CONST(4)
+#define AOPM_EXIT_MASK_0_RTC_ALARM_FIELD                        MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_RTC_ALARM_SHIFT)
+#define AOPM_EXIT_MASK_0_RTC_ALARM_RANGE                        4:4
+#define AOPM_EXIT_MASK_0_RTC_ALARM_MSB                  MK_SHIFT_CONST(4)
+#define AOPM_EXIT_MASK_0_RTC_ALARM_LSB                  MK_SHIFT_CONST(4)
+#define AOPM_EXIT_MASK_0_RTC_ALARM_WOFFSET                      0x0
+#define AOPM_EXIT_MASK_0_RTC_ALARM_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_RTC_ALARM_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_RTC_ALARM_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_RTC_ALARM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_RTC_ALARM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_RTC_ALARM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_RTC_ALARM_INIT_ENUM                    UNMASK
+#define AOPM_EXIT_MASK_0_RTC_ALARM_UNMASK                       MK_ENUM_CONST(0)
+#define AOPM_EXIT_MASK_0_RTC_ALARM_MASK                 MK_ENUM_CONST(1)
+
+#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_SHIFT                      MK_SHIFT_CONST(5)
+#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_FIELD                      MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_DBG_TIMEOUT_SHIFT)
+#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_RANGE                      5:5
+#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_MSB                        MK_SHIFT_CONST(5)
+#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_LSB                        MK_SHIFT_CONST(5)
+#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_WOFFSET                    0x0
+#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_DEFAULT                    MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_INIT_ENUM                  MASK
+#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_UNMASK                     MK_ENUM_CONST(0)
+#define AOPM_EXIT_MASK_0_DBG_TIMEOUT_MASK                       MK_ENUM_CONST(1)
+
+#define AOPM_EXIT_MASK_0_WFI_SHIFT                      MK_SHIFT_CONST(6)
+#define AOPM_EXIT_MASK_0_WFI_FIELD                      MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_WFI_SHIFT)
+#define AOPM_EXIT_MASK_0_WFI_RANGE                      6:6
+#define AOPM_EXIT_MASK_0_WFI_MSB                        MK_SHIFT_CONST(6)
+#define AOPM_EXIT_MASK_0_WFI_LSB                        MK_SHIFT_CONST(6)
+#define AOPM_EXIT_MASK_0_WFI_WOFFSET                    0x0
+#define AOPM_EXIT_MASK_0_WFI_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_WFI_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_WFI_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_WFI_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_WFI_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_WFI_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_WFI_INIT_ENUM                  UNMASK
+#define AOPM_EXIT_MASK_0_WFI_UNMASK                     MK_ENUM_CONST(0)
+#define AOPM_EXIT_MASK_0_WFI_MASK                       MK_ENUM_CONST(1)
+
+#define AOPM_EXIT_MASK_0_WFE_SHIFT                      MK_SHIFT_CONST(7)
+#define AOPM_EXIT_MASK_0_WFE_FIELD                      MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_WFE_SHIFT)
+#define AOPM_EXIT_MASK_0_WFE_RANGE                      7:7
+#define AOPM_EXIT_MASK_0_WFE_MSB                        MK_SHIFT_CONST(7)
+#define AOPM_EXIT_MASK_0_WFE_LSB                        MK_SHIFT_CONST(7)
+#define AOPM_EXIT_MASK_0_WFE_WOFFSET                    0x0
+#define AOPM_EXIT_MASK_0_WFE_DEFAULT                    MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_WFE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_WFE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_WFE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_WFE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_WFE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_WFE_INIT_ENUM                  MASK
+#define AOPM_EXIT_MASK_0_WFE_UNMASK                     MK_ENUM_CONST(0)
+#define AOPM_EXIT_MASK_0_WFE_MASK                       MK_ENUM_CONST(1)
+
+#define AOPM_EXIT_MASK_0_CLKSTOPPED_SHIFT                       MK_SHIFT_CONST(8)
+#define AOPM_EXIT_MASK_0_CLKSTOPPED_FIELD                       MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_CLKSTOPPED_SHIFT)
+#define AOPM_EXIT_MASK_0_CLKSTOPPED_RANGE                       8:8
+#define AOPM_EXIT_MASK_0_CLKSTOPPED_MSB                 MK_SHIFT_CONST(8)
+#define AOPM_EXIT_MASK_0_CLKSTOPPED_LSB                 MK_SHIFT_CONST(8)
+#define AOPM_EXIT_MASK_0_CLKSTOPPED_WOFFSET                     0x0
+#define AOPM_EXIT_MASK_0_CLKSTOPPED_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_CLKSTOPPED_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_CLKSTOPPED_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_CLKSTOPPED_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_CLKSTOPPED_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_CLKSTOPPED_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_CLKSTOPPED_INIT_ENUM                   UNMASK
+#define AOPM_EXIT_MASK_0_CLKSTOPPED_UNMASK                      MK_ENUM_CONST(0)
+#define AOPM_EXIT_MASK_0_CLKSTOPPED_MASK                        MK_ENUM_CONST(1)
+
+#define AOPM_EXIT_MASK_0_AXIP_SHIFT                     MK_SHIFT_CONST(9)
+#define AOPM_EXIT_MASK_0_AXIP_FIELD                     MK_FIELD_CONST(0x1, AOPM_EXIT_MASK_0_AXIP_SHIFT)
+#define AOPM_EXIT_MASK_0_AXIP_RANGE                     9:9
+#define AOPM_EXIT_MASK_0_AXIP_MSB                       MK_SHIFT_CONST(9)
+#define AOPM_EXIT_MASK_0_AXIP_LSB                       MK_SHIFT_CONST(9)
+#define AOPM_EXIT_MASK_0_AXIP_WOFFSET                   0x0
+#define AOPM_EXIT_MASK_0_AXIP_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_AXIP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_AXIP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_AXIP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_AXIP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_EXIT_MASK_0_AXIP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_EXIT_MASK_0_AXIP_INIT_ENUM                 UNMASK
+#define AOPM_EXIT_MASK_0_AXIP_UNMASK                    MK_ENUM_CONST(0)
+#define AOPM_EXIT_MASK_0_AXIP_MASK                      MK_ENUM_CONST(1)
+
+
+// Register AOPM_BURST_CLK_0
+#define AOPM_BURST_CLK_0                        MK_ADDR_CONST(0x30)
+#define AOPM_BURST_CLK_0_SECURE                         0x0
+#define AOPM_BURST_CLK_0_DUAL                   0x0
+#define AOPM_BURST_CLK_0_SCR                    SCR_SHARED_0
+#define AOPM_BURST_CLK_0_SCRREG                         AOPM_SCR_SCR_SHARED_0
+#define AOPM_BURST_CLK_0_WORD_COUNT                     0x1
+#define AOPM_BURST_CLK_0_RESET_VAL                      MK_MASK_CONST(0x2)
+#define AOPM_BURST_CLK_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define AOPM_BURST_CLK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define AOPM_BURST_CLK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_BURST_CLK_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define AOPM_BURST_CLK_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define AOPM_BURST_CLK_0_BURST_CLK_EN_SHIFT                     MK_SHIFT_CONST(0)
+#define AOPM_BURST_CLK_0_BURST_CLK_EN_FIELD                     MK_FIELD_CONST(0x1, AOPM_BURST_CLK_0_BURST_CLK_EN_SHIFT)
+#define AOPM_BURST_CLK_0_BURST_CLK_EN_RANGE                     0:0
+#define AOPM_BURST_CLK_0_BURST_CLK_EN_MSB                       MK_SHIFT_CONST(0)
+#define AOPM_BURST_CLK_0_BURST_CLK_EN_LSB                       MK_SHIFT_CONST(0)
+#define AOPM_BURST_CLK_0_BURST_CLK_EN_WOFFSET                   0x0
+#define AOPM_BURST_CLK_0_BURST_CLK_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_BURST_CLK_0_BURST_CLK_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_BURST_CLK_0_BURST_CLK_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_BURST_CLK_0_BURST_CLK_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_BURST_CLK_0_BURST_CLK_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_BURST_CLK_0_BURST_CLK_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_BURST_CLK_0_BURST_CLK_EN_INIT_ENUM                 DISABLE
+#define AOPM_BURST_CLK_0_BURST_CLK_EN_DISABLE                   MK_ENUM_CONST(0)
+#define AOPM_BURST_CLK_0_BURST_CLK_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define AOPM_BURST_CLK_0_BURST_LP_EN_SHIFT                      MK_SHIFT_CONST(1)
+#define AOPM_BURST_CLK_0_BURST_LP_EN_FIELD                      MK_FIELD_CONST(0x1, AOPM_BURST_CLK_0_BURST_LP_EN_SHIFT)
+#define AOPM_BURST_CLK_0_BURST_LP_EN_RANGE                      1:1
+#define AOPM_BURST_CLK_0_BURST_LP_EN_MSB                        MK_SHIFT_CONST(1)
+#define AOPM_BURST_CLK_0_BURST_LP_EN_LSB                        MK_SHIFT_CONST(1)
+#define AOPM_BURST_CLK_0_BURST_LP_EN_WOFFSET                    0x0
+#define AOPM_BURST_CLK_0_BURST_LP_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define AOPM_BURST_CLK_0_BURST_LP_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_BURST_CLK_0_BURST_LP_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_BURST_CLK_0_BURST_LP_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_BURST_CLK_0_BURST_LP_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_BURST_CLK_0_BURST_LP_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_BURST_CLK_0_BURST_LP_EN_INIT_ENUM                  ENABLE
+#define AOPM_BURST_CLK_0_BURST_LP_EN_DISABLE                    MK_ENUM_CONST(0)
+#define AOPM_BURST_CLK_0_BURST_LP_EN_ENABLE                     MK_ENUM_CONST(1)
+
+
+// Register AOPM_ACTIRQFIQ_TO_ACT_0
+#define AOPM_ACTIRQFIQ_TO_ACT_0                 MK_ADDR_CONST(0x34)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_SECURE                  0x0
+#define AOPM_ACTIRQFIQ_TO_ACT_0_DUAL                    0x0
+#define AOPM_ACTIRQFIQ_TO_ACT_0_SCR                     SCR_SHARED_0
+#define AOPM_ACTIRQFIQ_TO_ACT_0_SCRREG                  AOPM_SCR_SCR_SHARED_0
+#define AOPM_ACTIRQFIQ_TO_ACT_0_WORD_COUNT                      0x1
+#define AOPM_ACTIRQFIQ_TO_ACT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_SHIFT                        MK_SHIFT_CONST(0)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_FIELD                        MK_FIELD_CONST(0x1, AOPM_ACTIRQFIQ_TO_ACT_0_EN_SHIFT)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_RANGE                        0:0
+#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_MSB                  MK_SHIFT_CONST(0)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_LSB                  MK_SHIFT_CONST(0)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_WOFFSET                      0x0
+#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_DONE                 MK_ENUM_CONST(0)
+#define AOPM_ACTIRQFIQ_TO_ACT_0_EN_PENDING                      MK_ENUM_CONST(1)
+
+
+// Register AOPM_CSITE_CFG_0
+#define AOPM_CSITE_CFG_0                        MK_ADDR_CONST(0x38)
+#define AOPM_CSITE_CFG_0_SECURE                         0x0
+#define AOPM_CSITE_CFG_0_DUAL                   0x0
+#define AOPM_CSITE_CFG_0_SCR                    SCR_PRIVATE_0
+#define AOPM_CSITE_CFG_0_SCRREG                         AOPM_SCR_SCR_PRIVATE_0
+#define AOPM_CSITE_CFG_0_WORD_COUNT                     0x1
+#define AOPM_CSITE_CFG_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define AOPM_CSITE_CFG_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_CSITE_CFG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define AOPM_CSITE_CFG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_CSITE_CFG_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_CSITE_CFG_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_SHIFT                   MK_SHIFT_CONST(0)
+#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_FIELD                   MK_FIELD_CONST(0x1, AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_SHIFT)
+#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_RANGE                   0:0
+#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_MSB                     MK_SHIFT_CONST(0)
+#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_LSB                     MK_SHIFT_CONST(0)
+#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_WOFFSET                 0x0
+#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_INIT_ENUM                       FALSE
+#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_FALSE                   MK_ENUM_CONST(0)
+#define AOPM_CSITE_CFG_0_CSITE_CFG_DBGNOCLKSTOP_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register AOPM_R5_CFG_0
+#define AOPM_R5_CFG_0                   MK_ADDR_CONST(0x3c)
+#define AOPM_R5_CFG_0_SECURE                    0x0
+#define AOPM_R5_CFG_0_DUAL                      0x0
+#define AOPM_R5_CFG_0_SCR                       SCR_PRIVATE_0
+#define AOPM_R5_CFG_0_SCRREG                    AOPM_SCR_SCR_PRIVATE_0
+#define AOPM_R5_CFG_0_WORD_COUNT                        0x1
+#define AOPM_R5_CFG_0_RESET_VAL                         MK_MASK_CONST(0xa88)
+#define AOPM_R5_CFG_0_RESET_MASK                        MK_MASK_CONST(0xffffff8a)
+#define AOPM_R5_CFG_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define AOPM_R5_CFG_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_R5_CFG_0_READ_MASK                         MK_MASK_CONST(0xffffff8a)
+#define AOPM_R5_CFG_0_WRITE_MASK                        MK_MASK_CONST(0xffffff8a)
+#define AOPM_R5_CFG_0_TEINIT_SHIFT                      MK_SHIFT_CONST(1)
+#define AOPM_R5_CFG_0_TEINIT_FIELD                      MK_FIELD_CONST(0x1, AOPM_R5_CFG_0_TEINIT_SHIFT)
+#define AOPM_R5_CFG_0_TEINIT_RANGE                      1:1
+#define AOPM_R5_CFG_0_TEINIT_MSB                        MK_SHIFT_CONST(1)
+#define AOPM_R5_CFG_0_TEINIT_LSB                        MK_SHIFT_CONST(1)
+#define AOPM_R5_CFG_0_TEINIT_WOFFSET                    0x0
+#define AOPM_R5_CFG_0_TEINIT_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_R5_CFG_0_TEINIT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_R5_CFG_0_TEINIT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_R5_CFG_0_TEINIT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_R5_CFG_0_TEINIT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_R5_CFG_0_TEINIT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_R5_CFG_0_TEINIT_INIT_ENUM                  ARM
+#define AOPM_R5_CFG_0_TEINIT_ARM                        MK_ENUM_CONST(0)
+#define AOPM_R5_CFG_0_TEINIT_THUMB                      MK_ENUM_CONST(1)
+
+#define AOPM_R5_CFG_0_INITPPX_SHIFT                     MK_SHIFT_CONST(3)
+#define AOPM_R5_CFG_0_INITPPX_FIELD                     MK_FIELD_CONST(0x1, AOPM_R5_CFG_0_INITPPX_SHIFT)
+#define AOPM_R5_CFG_0_INITPPX_RANGE                     3:3
+#define AOPM_R5_CFG_0_INITPPX_MSB                       MK_SHIFT_CONST(3)
+#define AOPM_R5_CFG_0_INITPPX_LSB                       MK_SHIFT_CONST(3)
+#define AOPM_R5_CFG_0_INITPPX_WOFFSET                   0x0
+#define AOPM_R5_CFG_0_INITPPX_DEFAULT                   MK_MASK_CONST(0x1)
+#define AOPM_R5_CFG_0_INITPPX_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_R5_CFG_0_INITPPX_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_R5_CFG_0_INITPPX_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_R5_CFG_0_INITPPX_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_R5_CFG_0_INITPPX_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_R5_CFG_0_INITPPX_INIT_ENUM                 ENABLE
+#define AOPM_R5_CFG_0_INITPPX_DISABLE                   MK_ENUM_CONST(0)
+#define AOPM_R5_CFG_0_INITPPX_ENABLE                    MK_ENUM_CONST(1)
+
+#define AOPM_R5_CFG_0_PPXSIZE_SHIFT                     MK_SHIFT_CONST(7)
+#define AOPM_R5_CFG_0_PPXSIZE_FIELD                     MK_FIELD_CONST(0x1f, AOPM_R5_CFG_0_PPXSIZE_SHIFT)
+#define AOPM_R5_CFG_0_PPXSIZE_RANGE                     11:7
+#define AOPM_R5_CFG_0_PPXSIZE_MSB                       MK_SHIFT_CONST(11)
+#define AOPM_R5_CFG_0_PPXSIZE_LSB                       MK_SHIFT_CONST(7)
+#define AOPM_R5_CFG_0_PPXSIZE_WOFFSET                   0x0
+#define AOPM_R5_CFG_0_PPXSIZE_DEFAULT                   MK_MASK_CONST(0x15)
+#define AOPM_R5_CFG_0_PPXSIZE_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
+#define AOPM_R5_CFG_0_PPXSIZE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_R5_CFG_0_PPXSIZE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_R5_CFG_0_PPXSIZE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_R5_CFG_0_PPXSIZE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define AOPM_R5_CFG_0_PPXBASE_SHIFT                     MK_SHIFT_CONST(12)
+#define AOPM_R5_CFG_0_PPXBASE_FIELD                     MK_FIELD_CONST(0xfffff, AOPM_R5_CFG_0_PPXBASE_SHIFT)
+#define AOPM_R5_CFG_0_PPXBASE_RANGE                     31:12
+#define AOPM_R5_CFG_0_PPXBASE_MSB                       MK_SHIFT_CONST(31)
+#define AOPM_R5_CFG_0_PPXBASE_LSB                       MK_SHIFT_CONST(12)
+#define AOPM_R5_CFG_0_PPXBASE_WOFFSET                   0x0
+#define AOPM_R5_CFG_0_PPXBASE_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_R5_CFG_0_PPXBASE_DEFAULT_MASK                      MK_MASK_CONST(0xfffff)
+#define AOPM_R5_CFG_0_PPXBASE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_R5_CFG_0_PPXBASE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_R5_CFG_0_PPXBASE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_R5_CFG_0_PPXBASE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register AOPM_R5_CTRL_0
+#define AOPM_R5_CTRL_0                  MK_ADDR_CONST(0x40)
+#define AOPM_R5_CTRL_0_SECURE                   0x0
+#define AOPM_R5_CTRL_0_DUAL                     0x0
+#define AOPM_R5_CTRL_0_SCR                      SCR_PRIVATE_0
+#define AOPM_R5_CTRL_0_SCRREG                   AOPM_SCR_SCR_PRIVATE_0
+#define AOPM_R5_CTRL_0_WORD_COUNT                       0x1
+#define AOPM_R5_CTRL_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define AOPM_R5_CTRL_0_RESET_MASK                       MK_MASK_CONST(0x3)
+#define AOPM_R5_CTRL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define AOPM_R5_CTRL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_R5_CTRL_0_READ_MASK                        MK_MASK_CONST(0x3)
+#define AOPM_R5_CTRL_0_WRITE_MASK                       MK_MASK_CONST(0x3)
+#define AOPM_R5_CTRL_0_FWLOADDONE_SHIFT                 MK_SHIFT_CONST(1)
+#define AOPM_R5_CTRL_0_FWLOADDONE_FIELD                 MK_FIELD_CONST(0x1, AOPM_R5_CTRL_0_FWLOADDONE_SHIFT)
+#define AOPM_R5_CTRL_0_FWLOADDONE_RANGE                 1:1
+#define AOPM_R5_CTRL_0_FWLOADDONE_MSB                   MK_SHIFT_CONST(1)
+#define AOPM_R5_CTRL_0_FWLOADDONE_LSB                   MK_SHIFT_CONST(1)
+#define AOPM_R5_CTRL_0_FWLOADDONE_WOFFSET                       0x0
+#define AOPM_R5_CTRL_0_FWLOADDONE_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_R5_CTRL_0_FWLOADDONE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_R5_CTRL_0_FWLOADDONE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_R5_CTRL_0_FWLOADDONE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_R5_CTRL_0_FWLOADDONE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_R5_CTRL_0_FWLOADDONE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_R5_CTRL_0_FWLOADDONE_INIT_ENUM                     HALTED
+#define AOPM_R5_CTRL_0_FWLOADDONE_HALTED                        MK_ENUM_CONST(0)
+#define AOPM_R5_CTRL_0_FWLOADDONE_DONE                  MK_ENUM_CONST(1)
+
+#define AOPM_R5_CTRL_0_LOCK_SHIFT                       MK_SHIFT_CONST(0)
+#define AOPM_R5_CTRL_0_LOCK_FIELD                       MK_FIELD_CONST(0x1, AOPM_R5_CTRL_0_LOCK_SHIFT)
+#define AOPM_R5_CTRL_0_LOCK_RANGE                       0:0
+#define AOPM_R5_CTRL_0_LOCK_MSB                 MK_SHIFT_CONST(0)
+#define AOPM_R5_CTRL_0_LOCK_LSB                 MK_SHIFT_CONST(0)
+#define AOPM_R5_CTRL_0_LOCK_WOFFSET                     0x0
+#define AOPM_R5_CTRL_0_LOCK_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_R5_CTRL_0_LOCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AOPM_R5_CTRL_0_LOCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_R5_CTRL_0_LOCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_R5_CTRL_0_LOCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AOPM_R5_CTRL_0_LOCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AOPM_R5_CTRL_0_LOCK_INIT_ENUM                   UNLOCKED
+#define AOPM_R5_CTRL_0_LOCK_UNLOCKED                    MK_ENUM_CONST(0)
+#define AOPM_R5_CTRL_0_LOCK_LOCKED                      MK_ENUM_CONST(1)
+
+
+// Register AOPM_TCM_SEL_0
+#define AOPM_TCM_SEL_0                  MK_ADDR_CONST(0x44)
+#define AOPM_TCM_SEL_0_SECURE                   0x0
+#define AOPM_TCM_SEL_0_DUAL                     0x0
+#define AOPM_TCM_SEL_0_SCR                      SCR_SHARED_0
+#define AOPM_TCM_SEL_0_SCRREG                   AOPM_SCR_SCR_SHARED_0
+#define AOPM_TCM_SEL_0_WORD_COUNT                       0x1
+#define AOPM_TCM_SEL_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define AOPM_TCM_SEL_0_RESET_MASK                       MK_MASK_CONST(0x3c)
+#define AOPM_TCM_SEL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define AOPM_TCM_SEL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_TCM_SEL_0_READ_MASK                        MK_MASK_CONST(0x3c)
+#define AOPM_TCM_SEL_0_WRITE_MASK                       MK_MASK_CONST(0x3c)
+#define AOPM_TCM_SEL_0_AXI_ADDR_SHIFT                   MK_SHIFT_CONST(2)
+#define AOPM_TCM_SEL_0_AXI_ADDR_FIELD                   MK_FIELD_CONST(0xf, AOPM_TCM_SEL_0_AXI_ADDR_SHIFT)
+#define AOPM_TCM_SEL_0_AXI_ADDR_RANGE                   5:2
+#define AOPM_TCM_SEL_0_AXI_ADDR_MSB                     MK_SHIFT_CONST(5)
+#define AOPM_TCM_SEL_0_AXI_ADDR_LSB                     MK_SHIFT_CONST(2)
+#define AOPM_TCM_SEL_0_AXI_ADDR_WOFFSET                 0x0
+#define AOPM_TCM_SEL_0_AXI_ADDR_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_TCM_SEL_0_AXI_ADDR_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define AOPM_TCM_SEL_0_AXI_ADDR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_TCM_SEL_0_AXI_ADDR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_TCM_SEL_0_AXI_ADDR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_TCM_SEL_0_AXI_ADDR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register AOPM_TCM_SLCG_0
+#define AOPM_TCM_SLCG_0                 MK_ADDR_CONST(0x48)
+#define AOPM_TCM_SLCG_0_SECURE                  0x0
+#define AOPM_TCM_SLCG_0_DUAL                    0x0
+#define AOPM_TCM_SLCG_0_SCR                     SCR_SHARED_0
+#define AOPM_TCM_SLCG_0_SCRREG                  AOPM_SCR_SCR_SHARED_0
+#define AOPM_TCM_SLCG_0_WORD_COUNT                      0x1
+#define AOPM_TCM_SLCG_0_RESET_VAL                       MK_MASK_CONST(0x3)
+#define AOPM_TCM_SLCG_0_RESET_MASK                      MK_MASK_CONST(0x3)
+#define AOPM_TCM_SLCG_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define AOPM_TCM_SLCG_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define AOPM_TCM_SLCG_0_READ_MASK                       MK_MASK_CONST(0x3)
+#define AOPM_TCM_SLCG_0_WRITE_MASK                      MK_MASK_CONST(0x3)
+#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_FIELD                      MK_FIELD_CONST(0x1, AOPM_TCM_SLCG_0_ATCM_SLCG_EN_SHIFT)
+#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_RANGE                      0:0
+#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_MSB                        MK_SHIFT_CONST(0)
+#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_LSB                        MK_SHIFT_CONST(0)
+#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_WOFFSET                    0x0
+#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_INIT_ENUM                  ENABLE
+#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_DISABLE                    MK_ENUM_CONST(0)
+#define AOPM_TCM_SLCG_0_ATCM_SLCG_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_SHIFT                      MK_SHIFT_CONST(1)
+#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_FIELD                      MK_FIELD_CONST(0x1, AOPM_TCM_SLCG_0_BTCM_SLCG_EN_SHIFT)
+#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_RANGE                      1:1
+#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_MSB                        MK_SHIFT_CONST(1)
+#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_LSB                        MK_SHIFT_CONST(1)
+#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_WOFFSET                    0x0
+#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_INIT_ENUM                  ENABLE
+#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_DISABLE                    MK_ENUM_CONST(0)
+#define AOPM_TCM_SLCG_0_BTCM_SLCG_EN_ENABLE                     MK_ENUM_CONST(1)
+
+
+// Register AOPM_ACTMON_0
+#define AOPM_ACTMON_0                   MK_ADDR_CONST(0x4c)
+#define AOPM_ACTMON_0_SECURE                    0x0
+#define AOPM_ACTMON_0_DUAL                      0x0
+#define AOPM_ACTMON_0_SCR                       SCR_SHARED_0
+#define AOPM_ACTMON_0_SCRREG                    AOPM_SCR_SCR_SHARED_0
+#define AOPM_ACTMON_0_WORD_COUNT                        0x1
+#define AOPM_ACTMON_0_RESET_VAL                         MK_MASK_CONST(0xff0000)
+#define AOPM_ACTMON_0_RESET_MASK                        MK_MASK_CONST(0x80ff00f7)
+#define AOPM_ACTMON_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_READ_MASK                         MK_MASK_CONST(0x80ff00f7)
+#define AOPM_ACTMON_0_WRITE_MASK                        MK_MASK_CONST(0x80ff00f7)
+#define AOPM_ACTMON_0_MASK_NCLK_SHIFT                   MK_SHIFT_CONST(0)
+#define AOPM_ACTMON_0_MASK_NCLK_FIELD                   MK_FIELD_CONST(0x1, AOPM_ACTMON_0_MASK_NCLK_SHIFT)
+#define AOPM_ACTMON_0_MASK_NCLK_RANGE                   0:0
+#define AOPM_ACTMON_0_MASK_NCLK_MSB                     MK_SHIFT_CONST(0)
+#define AOPM_ACTMON_0_MASK_NCLK_LSB                     MK_SHIFT_CONST(0)
+#define AOPM_ACTMON_0_MASK_NCLK_WOFFSET                 0x0
+#define AOPM_ACTMON_0_MASK_NCLK_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_NCLK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_ACTMON_0_MASK_NCLK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_NCLK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_NCLK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_NCLK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_ACTMON_0_MASK_NCLK_INIT_ENUM                       UNMASK
+#define AOPM_ACTMON_0_MASK_NCLK_UNMASK                  MK_ENUM_CONST(0)
+#define AOPM_ACTMON_0_MASK_NCLK_MASK                    MK_ENUM_CONST(1)
+
+#define AOPM_ACTMON_0_MASK_NWFI_SHIFT                   MK_SHIFT_CONST(1)
+#define AOPM_ACTMON_0_MASK_NWFI_FIELD                   MK_FIELD_CONST(0x1, AOPM_ACTMON_0_MASK_NWFI_SHIFT)
+#define AOPM_ACTMON_0_MASK_NWFI_RANGE                   1:1
+#define AOPM_ACTMON_0_MASK_NWFI_MSB                     MK_SHIFT_CONST(1)
+#define AOPM_ACTMON_0_MASK_NWFI_LSB                     MK_SHIFT_CONST(1)
+#define AOPM_ACTMON_0_MASK_NWFI_WOFFSET                 0x0
+#define AOPM_ACTMON_0_MASK_NWFI_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_NWFI_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_ACTMON_0_MASK_NWFI_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_NWFI_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_NWFI_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_NWFI_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_ACTMON_0_MASK_NWFI_INIT_ENUM                       UNMASK
+#define AOPM_ACTMON_0_MASK_NWFI_UNMASK                  MK_ENUM_CONST(0)
+#define AOPM_ACTMON_0_MASK_NWFI_MASK                    MK_ENUM_CONST(1)
+
+#define AOPM_ACTMON_0_MASK_NWFE_SHIFT                   MK_SHIFT_CONST(2)
+#define AOPM_ACTMON_0_MASK_NWFE_FIELD                   MK_FIELD_CONST(0x1, AOPM_ACTMON_0_MASK_NWFE_SHIFT)
+#define AOPM_ACTMON_0_MASK_NWFE_RANGE                   2:2
+#define AOPM_ACTMON_0_MASK_NWFE_MSB                     MK_SHIFT_CONST(2)
+#define AOPM_ACTMON_0_MASK_NWFE_LSB                     MK_SHIFT_CONST(2)
+#define AOPM_ACTMON_0_MASK_NWFE_WOFFSET                 0x0
+#define AOPM_ACTMON_0_MASK_NWFE_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_NWFE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_ACTMON_0_MASK_NWFE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_NWFE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_NWFE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_NWFE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_ACTMON_0_MASK_NWFE_INIT_ENUM                       UNMASK
+#define AOPM_ACTMON_0_MASK_NWFE_UNMASK                  MK_ENUM_CONST(0)
+#define AOPM_ACTMON_0_MASK_NWFE_MASK                    MK_ENUM_CONST(1)
+
+#define AOPM_ACTMON_0_MASK_EB5_SHIFT                    MK_SHIFT_CONST(4)
+#define AOPM_ACTMON_0_MASK_EB5_FIELD                    MK_FIELD_CONST(0x1, AOPM_ACTMON_0_MASK_EB5_SHIFT)
+#define AOPM_ACTMON_0_MASK_EB5_RANGE                    4:4
+#define AOPM_ACTMON_0_MASK_EB5_MSB                      MK_SHIFT_CONST(4)
+#define AOPM_ACTMON_0_MASK_EB5_LSB                      MK_SHIFT_CONST(4)
+#define AOPM_ACTMON_0_MASK_EB5_WOFFSET                  0x0
+#define AOPM_ACTMON_0_MASK_EB5_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_EB5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_ACTMON_0_MASK_EB5_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_EB5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_EB5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_EB5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_ACTMON_0_MASK_EB5_INIT_ENUM                        UNMASK
+#define AOPM_ACTMON_0_MASK_EB5_UNMASK                   MK_ENUM_CONST(0)
+#define AOPM_ACTMON_0_MASK_EB5_MASK                     MK_ENUM_CONST(1)
+
+#define AOPM_ACTMON_0_MASK_EB16_SHIFT                   MK_SHIFT_CONST(5)
+#define AOPM_ACTMON_0_MASK_EB16_FIELD                   MK_FIELD_CONST(0x1, AOPM_ACTMON_0_MASK_EB16_SHIFT)
+#define AOPM_ACTMON_0_MASK_EB16_RANGE                   5:5
+#define AOPM_ACTMON_0_MASK_EB16_MSB                     MK_SHIFT_CONST(5)
+#define AOPM_ACTMON_0_MASK_EB16_LSB                     MK_SHIFT_CONST(5)
+#define AOPM_ACTMON_0_MASK_EB16_WOFFSET                 0x0
+#define AOPM_ACTMON_0_MASK_EB16_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_EB16_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_ACTMON_0_MASK_EB16_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_EB16_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_EB16_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_EB16_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_ACTMON_0_MASK_EB16_INIT_ENUM                       UNMASK
+#define AOPM_ACTMON_0_MASK_EB16_UNMASK                  MK_ENUM_CONST(0)
+#define AOPM_ACTMON_0_MASK_EB16_MASK                    MK_ENUM_CONST(1)
+
+#define AOPM_ACTMON_0_MASK_EB19_SHIFT                   MK_SHIFT_CONST(6)
+#define AOPM_ACTMON_0_MASK_EB19_FIELD                   MK_FIELD_CONST(0x1, AOPM_ACTMON_0_MASK_EB19_SHIFT)
+#define AOPM_ACTMON_0_MASK_EB19_RANGE                   6:6
+#define AOPM_ACTMON_0_MASK_EB19_MSB                     MK_SHIFT_CONST(6)
+#define AOPM_ACTMON_0_MASK_EB19_LSB                     MK_SHIFT_CONST(6)
+#define AOPM_ACTMON_0_MASK_EB19_WOFFSET                 0x0
+#define AOPM_ACTMON_0_MASK_EB19_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_EB19_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_ACTMON_0_MASK_EB19_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_EB19_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_EB19_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_EB19_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_ACTMON_0_MASK_EB19_INIT_ENUM                       UNMASK
+#define AOPM_ACTMON_0_MASK_EB19_UNMASK                  MK_ENUM_CONST(0)
+#define AOPM_ACTMON_0_MASK_EB19_MASK                    MK_ENUM_CONST(1)
+
+#define AOPM_ACTMON_0_MASK_EB20_SHIFT                   MK_SHIFT_CONST(7)
+#define AOPM_ACTMON_0_MASK_EB20_FIELD                   MK_FIELD_CONST(0x1, AOPM_ACTMON_0_MASK_EB20_SHIFT)
+#define AOPM_ACTMON_0_MASK_EB20_RANGE                   7:7
+#define AOPM_ACTMON_0_MASK_EB20_MSB                     MK_SHIFT_CONST(7)
+#define AOPM_ACTMON_0_MASK_EB20_LSB                     MK_SHIFT_CONST(7)
+#define AOPM_ACTMON_0_MASK_EB20_WOFFSET                 0x0
+#define AOPM_ACTMON_0_MASK_EB20_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_EB20_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_ACTMON_0_MASK_EB20_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_EB20_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_EB20_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_MASK_EB20_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_ACTMON_0_MASK_EB20_INIT_ENUM                       UNMASK
+#define AOPM_ACTMON_0_MASK_EB20_UNMASK                  MK_ENUM_CONST(0)
+#define AOPM_ACTMON_0_MASK_EB20_MASK                    MK_ENUM_CONST(1)
+
+#define AOPM_ACTMON_0_COUNT_TGT_SHIFT                   MK_SHIFT_CONST(16)
+#define AOPM_ACTMON_0_COUNT_TGT_FIELD                   MK_FIELD_CONST(0xff, AOPM_ACTMON_0_COUNT_TGT_SHIFT)
+#define AOPM_ACTMON_0_COUNT_TGT_RANGE                   23:16
+#define AOPM_ACTMON_0_COUNT_TGT_MSB                     MK_SHIFT_CONST(23)
+#define AOPM_ACTMON_0_COUNT_TGT_LSB                     MK_SHIFT_CONST(16)
+#define AOPM_ACTMON_0_COUNT_TGT_WOFFSET                 0x0
+#define AOPM_ACTMON_0_COUNT_TGT_DEFAULT                 MK_MASK_CONST(0xff)
+#define AOPM_ACTMON_0_COUNT_TGT_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define AOPM_ACTMON_0_COUNT_TGT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_COUNT_TGT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_COUNT_TGT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_COUNT_TGT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define AOPM_ACTMON_0_ENB_CNTR_SHIFT                    MK_SHIFT_CONST(31)
+#define AOPM_ACTMON_0_ENB_CNTR_FIELD                    MK_FIELD_CONST(0x1, AOPM_ACTMON_0_ENB_CNTR_SHIFT)
+#define AOPM_ACTMON_0_ENB_CNTR_RANGE                    31:31
+#define AOPM_ACTMON_0_ENB_CNTR_MSB                      MK_SHIFT_CONST(31)
+#define AOPM_ACTMON_0_ENB_CNTR_LSB                      MK_SHIFT_CONST(31)
+#define AOPM_ACTMON_0_ENB_CNTR_WOFFSET                  0x0
+#define AOPM_ACTMON_0_ENB_CNTR_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_ENB_CNTR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_ACTMON_0_ENB_CNTR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_ENB_CNTR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_ENB_CNTR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_ACTMON_0_ENB_CNTR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_ACTMON_0_ENB_CNTR_INIT_ENUM                        DISABLE
+#define AOPM_ACTMON_0_ENB_CNTR_DISABLE                  MK_ENUM_CONST(0)
+#define AOPM_ACTMON_0_ENB_CNTR_ENABLE                   MK_ENUM_CONST(1)
+
+
+// Register AOPM_R5_INTR_STATUS_0
+#define AOPM_R5_INTR_STATUS_0                   MK_ADDR_CONST(0x50)
+#define AOPM_R5_INTR_STATUS_0_SECURE                    0x0
+#define AOPM_R5_INTR_STATUS_0_DUAL                      0x0
+#define AOPM_R5_INTR_STATUS_0_SCR                       SCR_SHARED_0
+#define AOPM_R5_INTR_STATUS_0_SCRREG                    AOPM_SCR_SCR_SHARED_0
+#define AOPM_R5_INTR_STATUS_0_WORD_COUNT                        0x1
+#define AOPM_R5_INTR_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x1ff)
+#define AOPM_R5_INTR_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_READ_MASK                         MK_MASK_CONST(0x1ff)
+#define AOPM_R5_INTR_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_SHIFT                   MK_SHIFT_CONST(0)
+#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_FIELD                   MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_RTC_ALARM_SHIFT)
+#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_RANGE                   0:0
+#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_MSB                     MK_SHIFT_CONST(0)
+#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_LSB                     MK_SHIFT_CONST(0)
+#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_WOFFSET                 0x0
+#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_INIT_ENUM                       CLEAR
+#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_CLEAR                   MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_STATUS_0_RTC_ALARM_SET                     MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_SHIFT                  MK_SHIFT_CONST(1)
+#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_FIELD                  MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_SHIFT)
+#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_RANGE                  1:1
+#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_MSB                    MK_SHIFT_CONST(1)
+#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_LSB                    MK_SHIFT_CONST(1)
+#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_WOFFSET                        0x0
+#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_INIT_ENUM                      CLEAR
+#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_CLEAR                  MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_STATUS_0_NO_CAR_ACK_SET                    MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_SHIFT                  MK_SHIFT_CONST(2)
+#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_FIELD                  MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_SHIFT)
+#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_RANGE                  2:2
+#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_MSB                    MK_SHIFT_CONST(2)
+#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_LSB                    MK_SHIFT_CONST(2)
+#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_WOFFSET                        0x0
+#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_INIT_ENUM                      CLEAR
+#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_CLEAR                  MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_STATUS_0_NO_DVS_ACK_SET                    MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_SHIFT                  MK_SHIFT_CONST(3)
+#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_FIELD                  MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_SHIFT)
+#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_RANGE                  3:3
+#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_MSB                    MK_SHIFT_CONST(3)
+#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_LSB                    MK_SHIFT_CONST(3)
+#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_WOFFSET                        0x0
+#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_INIT_ENUM                      CLEAR
+#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_CLEAR                  MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_STATUS_0_NO_OSC_ACK_SET                    MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_STATUS_0_LP_EXIT_SHIFT                     MK_SHIFT_CONST(4)
+#define AOPM_R5_INTR_STATUS_0_LP_EXIT_FIELD                     MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_LP_EXIT_SHIFT)
+#define AOPM_R5_INTR_STATUS_0_LP_EXIT_RANGE                     4:4
+#define AOPM_R5_INTR_STATUS_0_LP_EXIT_MSB                       MK_SHIFT_CONST(4)
+#define AOPM_R5_INTR_STATUS_0_LP_EXIT_LSB                       MK_SHIFT_CONST(4)
+#define AOPM_R5_INTR_STATUS_0_LP_EXIT_WOFFSET                   0x0
+#define AOPM_R5_INTR_STATUS_0_LP_EXIT_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_LP_EXIT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_LP_EXIT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_LP_EXIT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_LP_EXIT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_LP_EXIT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_LP_EXIT_INIT_ENUM                 CLEAR
+#define AOPM_R5_INTR_STATUS_0_LP_EXIT_CLEAR                     MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_STATUS_0_LP_EXIT_SET                       MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_STATUS_0_DBG_TO_SHIFT                      MK_SHIFT_CONST(5)
+#define AOPM_R5_INTR_STATUS_0_DBG_TO_FIELD                      MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_DBG_TO_SHIFT)
+#define AOPM_R5_INTR_STATUS_0_DBG_TO_RANGE                      5:5
+#define AOPM_R5_INTR_STATUS_0_DBG_TO_MSB                        MK_SHIFT_CONST(5)
+#define AOPM_R5_INTR_STATUS_0_DBG_TO_LSB                        MK_SHIFT_CONST(5)
+#define AOPM_R5_INTR_STATUS_0_DBG_TO_WOFFSET                    0x0
+#define AOPM_R5_INTR_STATUS_0_DBG_TO_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_DBG_TO_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_DBG_TO_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_DBG_TO_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_DBG_TO_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_DBG_TO_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_DBG_TO_INIT_ENUM                  CLEAR
+#define AOPM_R5_INTR_STATUS_0_DBG_TO_CLEAR                      MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_STATUS_0_DBG_TO_SET                        MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_SHIFT                  MK_SHIFT_CONST(6)
+#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_FIELD                  MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_NO_RET_ACK_SHIFT)
+#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_RANGE                  6:6
+#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_MSB                    MK_SHIFT_CONST(6)
+#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_LSB                    MK_SHIFT_CONST(6)
+#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_WOFFSET                        0x0
+#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_INIT_ENUM                      CLEAR
+#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_CLEAR                  MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_STATUS_0_NO_RET_ACK_SET                    MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_SHIFT                     MK_SHIFT_CONST(7)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_FIELD                     MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_SHIFT)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_RANGE                     7:7
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_MSB                       MK_SHIFT_CONST(7)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_LSB                       MK_SHIFT_CONST(7)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_WOFFSET                   0x0
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_INIT_ENUM                 CLEAR
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_CLEAR                     MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_ACK_SET                       MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_SHIFT                 MK_SHIFT_CONST(8)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_FIELD                 MK_FIELD_CONST(0x1, AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_SHIFT)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_RANGE                 8:8
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_MSB                   MK_SHIFT_CONST(8)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_LSB                   MK_SHIFT_CONST(8)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_WOFFSET                       0x0
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_INIT_ENUM                     CLEAR
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_CLEAR                 MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_STATUS_0_NO_NOC_IDLE_SET                   MK_ENUM_CONST(1)
+
+
+// Register AOPM_R5_INTR_MASK_0
+#define AOPM_R5_INTR_MASK_0                     MK_ADDR_CONST(0x54)
+#define AOPM_R5_INTR_MASK_0_SECURE                      0x0
+#define AOPM_R5_INTR_MASK_0_DUAL                        0x0
+#define AOPM_R5_INTR_MASK_0_SCR                         SCR_SHARED_0
+#define AOPM_R5_INTR_MASK_0_SCRREG                      AOPM_SCR_SCR_SHARED_0
+#define AOPM_R5_INTR_MASK_0_WORD_COUNT                  0x1
+#define AOPM_R5_INTR_MASK_0_RESET_VAL                   MK_MASK_CONST(0x1ff)
+#define AOPM_R5_INTR_MASK_0_RESET_MASK                  MK_MASK_CONST(0x1ff)
+#define AOPM_R5_INTR_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_READ_MASK                   MK_MASK_CONST(0x1ff)
+#define AOPM_R5_INTR_MASK_0_WRITE_MASK                  MK_MASK_CONST(0x1ff)
+#define AOPM_R5_INTR_MASK_0_RTC_ALARM_SHIFT                     MK_SHIFT_CONST(0)
+#define AOPM_R5_INTR_MASK_0_RTC_ALARM_FIELD                     MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_RTC_ALARM_SHIFT)
+#define AOPM_R5_INTR_MASK_0_RTC_ALARM_RANGE                     0:0
+#define AOPM_R5_INTR_MASK_0_RTC_ALARM_MSB                       MK_SHIFT_CONST(0)
+#define AOPM_R5_INTR_MASK_0_RTC_ALARM_LSB                       MK_SHIFT_CONST(0)
+#define AOPM_R5_INTR_MASK_0_RTC_ALARM_WOFFSET                   0x0
+#define AOPM_R5_INTR_MASK_0_RTC_ALARM_DEFAULT                   MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_RTC_ALARM_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_RTC_ALARM_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_RTC_ALARM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_RTC_ALARM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_RTC_ALARM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_RTC_ALARM_INIT_ENUM                 MASK
+#define AOPM_R5_INTR_MASK_0_RTC_ALARM_UNMASK                    MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_MASK_0_RTC_ALARM_MASK                      MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_SHIFT                    MK_SHIFT_CONST(1)
+#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_FIELD                    MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_NO_CAR_ACK_SHIFT)
+#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_RANGE                    1:1
+#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_MSB                      MK_SHIFT_CONST(1)
+#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_LSB                      MK_SHIFT_CONST(1)
+#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_WOFFSET                  0x0
+#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_DEFAULT                  MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_INIT_ENUM                        MASK
+#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_UNMASK                   MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_MASK_0_NO_CAR_ACK_MASK                     MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_SHIFT                    MK_SHIFT_CONST(2)
+#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_FIELD                    MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_NO_DVS_ACK_SHIFT)
+#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_RANGE                    2:2
+#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_MSB                      MK_SHIFT_CONST(2)
+#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_LSB                      MK_SHIFT_CONST(2)
+#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_WOFFSET                  0x0
+#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_DEFAULT                  MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_INIT_ENUM                        MASK
+#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_UNMASK                   MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_MASK_0_NO_DVS_ACK_MASK                     MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_SHIFT                    MK_SHIFT_CONST(3)
+#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_FIELD                    MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_NO_OSC_ACK_SHIFT)
+#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_RANGE                    3:3
+#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_MSB                      MK_SHIFT_CONST(3)
+#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_LSB                      MK_SHIFT_CONST(3)
+#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_WOFFSET                  0x0
+#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_DEFAULT                  MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_INIT_ENUM                        MASK
+#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_UNMASK                   MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_MASK_0_NO_OSC_ACK_MASK                     MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_MASK_0_LP_EXIT_SHIFT                       MK_SHIFT_CONST(4)
+#define AOPM_R5_INTR_MASK_0_LP_EXIT_FIELD                       MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_LP_EXIT_SHIFT)
+#define AOPM_R5_INTR_MASK_0_LP_EXIT_RANGE                       4:4
+#define AOPM_R5_INTR_MASK_0_LP_EXIT_MSB                 MK_SHIFT_CONST(4)
+#define AOPM_R5_INTR_MASK_0_LP_EXIT_LSB                 MK_SHIFT_CONST(4)
+#define AOPM_R5_INTR_MASK_0_LP_EXIT_WOFFSET                     0x0
+#define AOPM_R5_INTR_MASK_0_LP_EXIT_DEFAULT                     MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_LP_EXIT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_LP_EXIT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_LP_EXIT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_LP_EXIT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_LP_EXIT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_LP_EXIT_INIT_ENUM                   MASK
+#define AOPM_R5_INTR_MASK_0_LP_EXIT_UNMASK                      MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_MASK_0_LP_EXIT_MASK                        MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_MASK_0_DBG_TO_SHIFT                        MK_SHIFT_CONST(5)
+#define AOPM_R5_INTR_MASK_0_DBG_TO_FIELD                        MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_DBG_TO_SHIFT)
+#define AOPM_R5_INTR_MASK_0_DBG_TO_RANGE                        5:5
+#define AOPM_R5_INTR_MASK_0_DBG_TO_MSB                  MK_SHIFT_CONST(5)
+#define AOPM_R5_INTR_MASK_0_DBG_TO_LSB                  MK_SHIFT_CONST(5)
+#define AOPM_R5_INTR_MASK_0_DBG_TO_WOFFSET                      0x0
+#define AOPM_R5_INTR_MASK_0_DBG_TO_DEFAULT                      MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_DBG_TO_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_DBG_TO_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_DBG_TO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_DBG_TO_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_DBG_TO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_DBG_TO_INIT_ENUM                    MASK
+#define AOPM_R5_INTR_MASK_0_DBG_TO_UNMASK                       MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_MASK_0_DBG_TO_MASK                 MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_SHIFT                    MK_SHIFT_CONST(6)
+#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_FIELD                    MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_NO_RET_ACK_SHIFT)
+#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_RANGE                    6:6
+#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_MSB                      MK_SHIFT_CONST(6)
+#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_LSB                      MK_SHIFT_CONST(6)
+#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_WOFFSET                  0x0
+#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_DEFAULT                  MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_INIT_ENUM                        MASK
+#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_UNMASK                   MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_MASK_0_NO_RET_ACK_MASK                     MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_SHIFT                       MK_SHIFT_CONST(7)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_FIELD                       MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_SHIFT)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_RANGE                       7:7
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_MSB                 MK_SHIFT_CONST(7)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_LSB                 MK_SHIFT_CONST(7)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_WOFFSET                     0x0
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_DEFAULT                     MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_INIT_ENUM                   MASK
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_UNMASK                      MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_ACK_MASK                        MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_SHIFT                   MK_SHIFT_CONST(8)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_FIELD                   MK_FIELD_CONST(0x1, AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_SHIFT)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_RANGE                   8:8
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_MSB                     MK_SHIFT_CONST(8)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_LSB                     MK_SHIFT_CONST(8)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_WOFFSET                 0x0
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_DEFAULT                 MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_INIT_ENUM                       MASK
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_UNMASK                  MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_MASK_0_NO_NOC_IDLE_MASK                    MK_ENUM_CONST(1)
+
+
+// Register AOPM_R5_INTR_SET_0
+#define AOPM_R5_INTR_SET_0                      MK_ADDR_CONST(0x58)
+#define AOPM_R5_INTR_SET_0_SECURE                       0x0
+#define AOPM_R5_INTR_SET_0_DUAL                         0x0
+#define AOPM_R5_INTR_SET_0_SCR                  SCR_SHARED_0
+#define AOPM_R5_INTR_SET_0_SCRREG                       AOPM_SCR_SCR_SHARED_0
+#define AOPM_R5_INTR_SET_0_WORD_COUNT                   0x1
+#define AOPM_R5_INTR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
+#define AOPM_R5_INTR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_READ_MASK                    MK_MASK_CONST(0x1ff)
+#define AOPM_R5_INTR_SET_0_WRITE_MASK                   MK_MASK_CONST(0x1ff)
+#define AOPM_R5_INTR_SET_0_RTC_ALARM_SHIFT                      MK_SHIFT_CONST(0)
+#define AOPM_R5_INTR_SET_0_RTC_ALARM_FIELD                      MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_RTC_ALARM_SHIFT)
+#define AOPM_R5_INTR_SET_0_RTC_ALARM_RANGE                      0:0
+#define AOPM_R5_INTR_SET_0_RTC_ALARM_MSB                        MK_SHIFT_CONST(0)
+#define AOPM_R5_INTR_SET_0_RTC_ALARM_LSB                        MK_SHIFT_CONST(0)
+#define AOPM_R5_INTR_SET_0_RTC_ALARM_WOFFSET                    0x0
+#define AOPM_R5_INTR_SET_0_RTC_ALARM_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_RTC_ALARM_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_RTC_ALARM_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_RTC_ALARM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_RTC_ALARM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_RTC_ALARM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_RTC_ALARM_INIT_ENUM                  CLEAR
+#define AOPM_R5_INTR_SET_0_RTC_ALARM_CLEAR                      MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_SET_0_RTC_ALARM_SET                        MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_SHIFT                     MK_SHIFT_CONST(1)
+#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_FIELD                     MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_NO_CAR_ACK_SHIFT)
+#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_RANGE                     1:1
+#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_MSB                       MK_SHIFT_CONST(1)
+#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_LSB                       MK_SHIFT_CONST(1)
+#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_WOFFSET                   0x0
+#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_INIT_ENUM                 CLEAR
+#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_CLEAR                     MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_SET_0_NO_CAR_ACK_SET                       MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_SHIFT                     MK_SHIFT_CONST(2)
+#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_FIELD                     MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_NO_DVS_ACK_SHIFT)
+#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_RANGE                     2:2
+#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_MSB                       MK_SHIFT_CONST(2)
+#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_LSB                       MK_SHIFT_CONST(2)
+#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_WOFFSET                   0x0
+#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_INIT_ENUM                 CLEAR
+#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_CLEAR                     MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_SET_0_NO_DVS_ACK_SET                       MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_SHIFT                     MK_SHIFT_CONST(3)
+#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_FIELD                     MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_NO_OSC_ACK_SHIFT)
+#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_RANGE                     3:3
+#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_MSB                       MK_SHIFT_CONST(3)
+#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_LSB                       MK_SHIFT_CONST(3)
+#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_WOFFSET                   0x0
+#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_INIT_ENUM                 CLEAR
+#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_CLEAR                     MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_SET_0_NO_OSC_ACK_SET                       MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_SET_0_LP_EXIT_SHIFT                        MK_SHIFT_CONST(4)
+#define AOPM_R5_INTR_SET_0_LP_EXIT_FIELD                        MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_LP_EXIT_SHIFT)
+#define AOPM_R5_INTR_SET_0_LP_EXIT_RANGE                        4:4
+#define AOPM_R5_INTR_SET_0_LP_EXIT_MSB                  MK_SHIFT_CONST(4)
+#define AOPM_R5_INTR_SET_0_LP_EXIT_LSB                  MK_SHIFT_CONST(4)
+#define AOPM_R5_INTR_SET_0_LP_EXIT_WOFFSET                      0x0
+#define AOPM_R5_INTR_SET_0_LP_EXIT_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_LP_EXIT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_LP_EXIT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_LP_EXIT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_LP_EXIT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_LP_EXIT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_LP_EXIT_INIT_ENUM                    CLEAR
+#define AOPM_R5_INTR_SET_0_LP_EXIT_CLEAR                        MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_SET_0_LP_EXIT_SET                  MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_SET_0_DBG_TO_SHIFT                 MK_SHIFT_CONST(5)
+#define AOPM_R5_INTR_SET_0_DBG_TO_FIELD                 MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_DBG_TO_SHIFT)
+#define AOPM_R5_INTR_SET_0_DBG_TO_RANGE                 5:5
+#define AOPM_R5_INTR_SET_0_DBG_TO_MSB                   MK_SHIFT_CONST(5)
+#define AOPM_R5_INTR_SET_0_DBG_TO_LSB                   MK_SHIFT_CONST(5)
+#define AOPM_R5_INTR_SET_0_DBG_TO_WOFFSET                       0x0
+#define AOPM_R5_INTR_SET_0_DBG_TO_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_DBG_TO_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_DBG_TO_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_DBG_TO_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_DBG_TO_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_DBG_TO_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_DBG_TO_INIT_ENUM                     CLEAR
+#define AOPM_R5_INTR_SET_0_DBG_TO_CLEAR                 MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_SET_0_DBG_TO_SET                   MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_SET_0_NO_RET_ACK_SHIFT                     MK_SHIFT_CONST(6)
+#define AOPM_R5_INTR_SET_0_NO_RET_ACK_FIELD                     MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_NO_RET_ACK_SHIFT)
+#define AOPM_R5_INTR_SET_0_NO_RET_ACK_RANGE                     6:6
+#define AOPM_R5_INTR_SET_0_NO_RET_ACK_MSB                       MK_SHIFT_CONST(6)
+#define AOPM_R5_INTR_SET_0_NO_RET_ACK_LSB                       MK_SHIFT_CONST(6)
+#define AOPM_R5_INTR_SET_0_NO_RET_ACK_WOFFSET                   0x0
+#define AOPM_R5_INTR_SET_0_NO_RET_ACK_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_RET_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_NO_RET_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_RET_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_RET_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_RET_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_NO_RET_ACK_INIT_ENUM                 CLEAR
+#define AOPM_R5_INTR_SET_0_NO_RET_ACK_CLEAR                     MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_SET_0_NO_RET_ACK_SET                       MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_SHIFT                        MK_SHIFT_CONST(7)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_FIELD                        MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_SHIFT)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_RANGE                        7:7
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_MSB                  MK_SHIFT_CONST(7)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_LSB                  MK_SHIFT_CONST(7)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_WOFFSET                      0x0
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_INIT_ENUM                    CLEAR
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_CLEAR                        MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_ACK_SET                  MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_SHIFT                    MK_SHIFT_CONST(8)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_FIELD                    MK_FIELD_CONST(0x1, AOPM_R5_INTR_SET_0_NO_NOC_IDLE_SHIFT)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_RANGE                    8:8
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_MSB                      MK_SHIFT_CONST(8)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_LSB                      MK_SHIFT_CONST(8)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_WOFFSET                  0x0
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_INIT_ENUM                        CLEAR
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_CLEAR                    MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_SET_0_NO_NOC_IDLE_SET                      MK_ENUM_CONST(1)
+
+
+// Register AOPM_R5_INTR_CLEAR_0
+#define AOPM_R5_INTR_CLEAR_0                    MK_ADDR_CONST(0x5c)
+#define AOPM_R5_INTR_CLEAR_0_SECURE                     0x0
+#define AOPM_R5_INTR_CLEAR_0_DUAL                       0x0
+#define AOPM_R5_INTR_CLEAR_0_SCR                        SCR_SHARED_0
+#define AOPM_R5_INTR_CLEAR_0_SCRREG                     AOPM_SCR_SCR_SHARED_0
+#define AOPM_R5_INTR_CLEAR_0_WORD_COUNT                         0x1
+#define AOPM_R5_INTR_CLEAR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_RESET_MASK                         MK_MASK_CONST(0x1ff)
+#define AOPM_R5_INTR_CLEAR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_READ_MASK                  MK_MASK_CONST(0x1ff)
+#define AOPM_R5_INTR_CLEAR_0_WRITE_MASK                         MK_MASK_CONST(0x1ff)
+#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_SHIFT                    MK_SHIFT_CONST(0)
+#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_FIELD                    MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_RTC_ALARM_SHIFT)
+#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_RANGE                    0:0
+#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_MSB                      MK_SHIFT_CONST(0)
+#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_LSB                      MK_SHIFT_CONST(0)
+#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_WOFFSET                  0x0
+#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_INIT_ENUM                        DISABLE
+#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_DISABLE                  MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_CLEAR_0_RTC_ALARM_ENABLE                   MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_SHIFT                   MK_SHIFT_CONST(1)
+#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_FIELD                   MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_SHIFT)
+#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_RANGE                   1:1
+#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_MSB                     MK_SHIFT_CONST(1)
+#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_LSB                     MK_SHIFT_CONST(1)
+#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_WOFFSET                 0x0
+#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_INIT_ENUM                       DISABLE
+#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_DISABLE                 MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_CLEAR_0_NO_CAR_ACK_ENABLE                  MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_SHIFT                   MK_SHIFT_CONST(2)
+#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_FIELD                   MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_SHIFT)
+#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_RANGE                   2:2
+#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_MSB                     MK_SHIFT_CONST(2)
+#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_LSB                     MK_SHIFT_CONST(2)
+#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_WOFFSET                 0x0
+#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_INIT_ENUM                       DISABLE
+#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_DISABLE                 MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_CLEAR_0_NO_DVS_ACK_ENABLE                  MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_SHIFT                   MK_SHIFT_CONST(3)
+#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_FIELD                   MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_SHIFT)
+#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_RANGE                   3:3
+#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_MSB                     MK_SHIFT_CONST(3)
+#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_LSB                     MK_SHIFT_CONST(3)
+#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_WOFFSET                 0x0
+#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_INIT_ENUM                       DISABLE
+#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_DISABLE                 MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_CLEAR_0_NO_OSC_ACK_ENABLE                  MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_SHIFT                      MK_SHIFT_CONST(4)
+#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_FIELD                      MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_LP_EXIT_SHIFT)
+#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_RANGE                      4:4
+#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_MSB                        MK_SHIFT_CONST(4)
+#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_LSB                        MK_SHIFT_CONST(4)
+#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_WOFFSET                    0x0
+#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_INIT_ENUM                  DISABLE
+#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_DISABLE                    MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_CLEAR_0_LP_EXIT_ENABLE                     MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_CLEAR_0_DBG_TO_SHIFT                       MK_SHIFT_CONST(5)
+#define AOPM_R5_INTR_CLEAR_0_DBG_TO_FIELD                       MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_DBG_TO_SHIFT)
+#define AOPM_R5_INTR_CLEAR_0_DBG_TO_RANGE                       5:5
+#define AOPM_R5_INTR_CLEAR_0_DBG_TO_MSB                 MK_SHIFT_CONST(5)
+#define AOPM_R5_INTR_CLEAR_0_DBG_TO_LSB                 MK_SHIFT_CONST(5)
+#define AOPM_R5_INTR_CLEAR_0_DBG_TO_WOFFSET                     0x0
+#define AOPM_R5_INTR_CLEAR_0_DBG_TO_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_DBG_TO_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_DBG_TO_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_DBG_TO_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_DBG_TO_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_DBG_TO_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_DBG_TO_INIT_ENUM                   DISABLE
+#define AOPM_R5_INTR_CLEAR_0_DBG_TO_DISABLE                     MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_CLEAR_0_DBG_TO_ENABLE                      MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_SHIFT                   MK_SHIFT_CONST(6)
+#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_FIELD                   MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_SHIFT)
+#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_RANGE                   6:6
+#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_MSB                     MK_SHIFT_CONST(6)
+#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_LSB                     MK_SHIFT_CONST(6)
+#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_WOFFSET                 0x0
+#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_INIT_ENUM                       DISABLE
+#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_DISABLE                 MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_CLEAR_0_NO_RET_ACK_ENABLE                  MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_SHIFT                      MK_SHIFT_CONST(7)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_FIELD                      MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_SHIFT)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_RANGE                      7:7
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_MSB                        MK_SHIFT_CONST(7)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_LSB                        MK_SHIFT_CONST(7)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_WOFFSET                    0x0
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_INIT_ENUM                  DISABLE
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_DISABLE                    MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ACK_ENABLE                     MK_ENUM_CONST(1)
+
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_SHIFT                  MK_SHIFT_CONST(8)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_FIELD                  MK_FIELD_CONST(0x1, AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_SHIFT)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_RANGE                  8:8
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_MSB                    MK_SHIFT_CONST(8)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_LSB                    MK_SHIFT_CONST(8)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_WOFFSET                        0x0
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_INIT_ENUM                      DISABLE
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_DISABLE                        MK_ENUM_CONST(0)
+#define AOPM_R5_INTR_CLEAR_0_NO_NOC_IDLE_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register AOPM_EXT_INTR_STATUS_0
+#define AOPM_EXT_INTR_STATUS_0                  MK_ADDR_CONST(0x60)
+#define AOPM_EXT_INTR_STATUS_0_SECURE                   0x0
+#define AOPM_EXT_INTR_STATUS_0_DUAL                     0x0
+#define AOPM_EXT_INTR_STATUS_0_SCR                      SCR_SHARED_0
+#define AOPM_EXT_INTR_STATUS_0_SCRREG                   AOPM_SCR_SCR_SHARED_0
+#define AOPM_EXT_INTR_STATUS_0_WORD_COUNT                       0x1
+#define AOPM_EXT_INTR_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x1ff)
+#define AOPM_EXT_INTR_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_READ_MASK                        MK_MASK_CONST(0x1ff)
+#define AOPM_EXT_INTR_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_SHIFT                  MK_SHIFT_CONST(0)
+#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_FIELD                  MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_RTC_ALARM_SHIFT)
+#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_RANGE                  0:0
+#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_MSB                    MK_SHIFT_CONST(0)
+#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_LSB                    MK_SHIFT_CONST(0)
+#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_WOFFSET                        0x0
+#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_INIT_ENUM                      CLEAR
+#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_CLEAR                  MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_STATUS_0_RTC_ALARM_SET                    MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_SHIFT                 MK_SHIFT_CONST(1)
+#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_FIELD                 MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_SHIFT)
+#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_RANGE                 1:1
+#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_MSB                   MK_SHIFT_CONST(1)
+#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_LSB                   MK_SHIFT_CONST(1)
+#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_WOFFSET                       0x0
+#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_INIT_ENUM                     CLEAR
+#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_CLEAR                 MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_STATUS_0_NO_CAR_ACK_SET                   MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_SHIFT                 MK_SHIFT_CONST(2)
+#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_FIELD                 MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_SHIFT)
+#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_RANGE                 2:2
+#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_MSB                   MK_SHIFT_CONST(2)
+#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_LSB                   MK_SHIFT_CONST(2)
+#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_WOFFSET                       0x0
+#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_INIT_ENUM                     CLEAR
+#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_CLEAR                 MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_STATUS_0_NO_DVS_ACK_SET                   MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_SHIFT                 MK_SHIFT_CONST(3)
+#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_FIELD                 MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_SHIFT)
+#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_RANGE                 3:3
+#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_MSB                   MK_SHIFT_CONST(3)
+#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_LSB                   MK_SHIFT_CONST(3)
+#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_WOFFSET                       0x0
+#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_INIT_ENUM                     CLEAR
+#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_CLEAR                 MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_STATUS_0_NO_OSC_ACK_SET                   MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_SHIFT                    MK_SHIFT_CONST(4)
+#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_FIELD                    MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_LP_EXIT_SHIFT)
+#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_RANGE                    4:4
+#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_MSB                      MK_SHIFT_CONST(4)
+#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_LSB                      MK_SHIFT_CONST(4)
+#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_WOFFSET                  0x0
+#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_INIT_ENUM                        CLEAR
+#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_CLEAR                    MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_STATUS_0_LP_EXIT_SET                      MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_STATUS_0_DBG_TO_SHIFT                     MK_SHIFT_CONST(5)
+#define AOPM_EXT_INTR_STATUS_0_DBG_TO_FIELD                     MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_DBG_TO_SHIFT)
+#define AOPM_EXT_INTR_STATUS_0_DBG_TO_RANGE                     5:5
+#define AOPM_EXT_INTR_STATUS_0_DBG_TO_MSB                       MK_SHIFT_CONST(5)
+#define AOPM_EXT_INTR_STATUS_0_DBG_TO_LSB                       MK_SHIFT_CONST(5)
+#define AOPM_EXT_INTR_STATUS_0_DBG_TO_WOFFSET                   0x0
+#define AOPM_EXT_INTR_STATUS_0_DBG_TO_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_DBG_TO_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_DBG_TO_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_DBG_TO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_DBG_TO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_DBG_TO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_DBG_TO_INIT_ENUM                 CLEAR
+#define AOPM_EXT_INTR_STATUS_0_DBG_TO_CLEAR                     MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_STATUS_0_DBG_TO_SET                       MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_SHIFT                 MK_SHIFT_CONST(6)
+#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_FIELD                 MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_SHIFT)
+#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_RANGE                 6:6
+#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_MSB                   MK_SHIFT_CONST(6)
+#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_LSB                   MK_SHIFT_CONST(6)
+#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_WOFFSET                       0x0
+#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_INIT_ENUM                     CLEAR
+#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_CLEAR                 MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_STATUS_0_NO_RET_ACK_SET                   MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_SHIFT                    MK_SHIFT_CONST(7)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_FIELD                    MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_SHIFT)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_RANGE                    7:7
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_MSB                      MK_SHIFT_CONST(7)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_LSB                      MK_SHIFT_CONST(7)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_WOFFSET                  0x0
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_INIT_ENUM                        CLEAR
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_CLEAR                    MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_ACK_SET                      MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_SHIFT                        MK_SHIFT_CONST(8)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_FIELD                        MK_FIELD_CONST(0x1, AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_SHIFT)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_RANGE                        8:8
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_MSB                  MK_SHIFT_CONST(8)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_LSB                  MK_SHIFT_CONST(8)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_WOFFSET                      0x0
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_INIT_ENUM                    CLEAR
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_CLEAR                        MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_STATUS_0_NO_NOC_IDLE_SET                  MK_ENUM_CONST(1)
+
+
+// Register AOPM_EXT_INTR_MASK_0
+#define AOPM_EXT_INTR_MASK_0                    MK_ADDR_CONST(0x64)
+#define AOPM_EXT_INTR_MASK_0_SECURE                     0x0
+#define AOPM_EXT_INTR_MASK_0_DUAL                       0x0
+#define AOPM_EXT_INTR_MASK_0_SCR                        SCR_PRIVATE_0
+#define AOPM_EXT_INTR_MASK_0_SCRREG                     AOPM_SCR_SCR_PRIVATE_0
+#define AOPM_EXT_INTR_MASK_0_WORD_COUNT                         0x1
+#define AOPM_EXT_INTR_MASK_0_RESET_VAL                  MK_MASK_CONST(0x1ff)
+#define AOPM_EXT_INTR_MASK_0_RESET_MASK                         MK_MASK_CONST(0x1ff)
+#define AOPM_EXT_INTR_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_READ_MASK                  MK_MASK_CONST(0x1ff)
+#define AOPM_EXT_INTR_MASK_0_WRITE_MASK                         MK_MASK_CONST(0x1ff)
+#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_SHIFT                    MK_SHIFT_CONST(0)
+#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_FIELD                    MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_RTC_ALARM_SHIFT)
+#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_RANGE                    0:0
+#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_MSB                      MK_SHIFT_CONST(0)
+#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_LSB                      MK_SHIFT_CONST(0)
+#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_WOFFSET                  0x0
+#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_DEFAULT                  MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_INIT_ENUM                        MASK
+#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_UNMASK                   MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_MASK_0_RTC_ALARM_MASK                     MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_SHIFT                   MK_SHIFT_CONST(1)
+#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_FIELD                   MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_SHIFT)
+#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_RANGE                   1:1
+#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_MSB                     MK_SHIFT_CONST(1)
+#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_LSB                     MK_SHIFT_CONST(1)
+#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_WOFFSET                 0x0
+#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_INIT_ENUM                       MASK
+#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_UNMASK                  MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_MASK_0_NO_CAR_ACK_MASK                    MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_SHIFT                   MK_SHIFT_CONST(2)
+#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_FIELD                   MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_SHIFT)
+#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_RANGE                   2:2
+#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_MSB                     MK_SHIFT_CONST(2)
+#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_LSB                     MK_SHIFT_CONST(2)
+#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_WOFFSET                 0x0
+#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_INIT_ENUM                       MASK
+#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_UNMASK                  MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_MASK_0_NO_DVS_ACK_MASK                    MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_SHIFT                   MK_SHIFT_CONST(3)
+#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_FIELD                   MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_SHIFT)
+#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_RANGE                   3:3
+#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_MSB                     MK_SHIFT_CONST(3)
+#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_LSB                     MK_SHIFT_CONST(3)
+#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_WOFFSET                 0x0
+#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_INIT_ENUM                       MASK
+#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_UNMASK                  MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_MASK_0_NO_OSC_ACK_MASK                    MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_MASK_0_LP_EXIT_SHIFT                      MK_SHIFT_CONST(4)
+#define AOPM_EXT_INTR_MASK_0_LP_EXIT_FIELD                      MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_LP_EXIT_SHIFT)
+#define AOPM_EXT_INTR_MASK_0_LP_EXIT_RANGE                      4:4
+#define AOPM_EXT_INTR_MASK_0_LP_EXIT_MSB                        MK_SHIFT_CONST(4)
+#define AOPM_EXT_INTR_MASK_0_LP_EXIT_LSB                        MK_SHIFT_CONST(4)
+#define AOPM_EXT_INTR_MASK_0_LP_EXIT_WOFFSET                    0x0
+#define AOPM_EXT_INTR_MASK_0_LP_EXIT_DEFAULT                    MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_LP_EXIT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_LP_EXIT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_LP_EXIT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_LP_EXIT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_LP_EXIT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_LP_EXIT_INIT_ENUM                  MASK
+#define AOPM_EXT_INTR_MASK_0_LP_EXIT_UNMASK                     MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_MASK_0_LP_EXIT_MASK                       MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_MASK_0_DBG_TO_SHIFT                       MK_SHIFT_CONST(5)
+#define AOPM_EXT_INTR_MASK_0_DBG_TO_FIELD                       MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_DBG_TO_SHIFT)
+#define AOPM_EXT_INTR_MASK_0_DBG_TO_RANGE                       5:5
+#define AOPM_EXT_INTR_MASK_0_DBG_TO_MSB                 MK_SHIFT_CONST(5)
+#define AOPM_EXT_INTR_MASK_0_DBG_TO_LSB                 MK_SHIFT_CONST(5)
+#define AOPM_EXT_INTR_MASK_0_DBG_TO_WOFFSET                     0x0
+#define AOPM_EXT_INTR_MASK_0_DBG_TO_DEFAULT                     MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_DBG_TO_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_DBG_TO_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_DBG_TO_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_DBG_TO_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_DBG_TO_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_DBG_TO_INIT_ENUM                   MASK
+#define AOPM_EXT_INTR_MASK_0_DBG_TO_UNMASK                      MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_MASK_0_DBG_TO_MASK                        MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_SHIFT                   MK_SHIFT_CONST(6)
+#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_FIELD                   MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_NO_RET_ACK_SHIFT)
+#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_RANGE                   6:6
+#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_MSB                     MK_SHIFT_CONST(6)
+#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_LSB                     MK_SHIFT_CONST(6)
+#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_WOFFSET                 0x0
+#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_INIT_ENUM                       MASK
+#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_UNMASK                  MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_MASK_0_NO_RET_ACK_MASK                    MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_SHIFT                      MK_SHIFT_CONST(7)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_FIELD                      MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_SHIFT)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_RANGE                      7:7
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_MSB                        MK_SHIFT_CONST(7)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_LSB                        MK_SHIFT_CONST(7)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_WOFFSET                    0x0
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_DEFAULT                    MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_INIT_ENUM                  MASK
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_UNMASK                     MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_ACK_MASK                       MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_SHIFT                  MK_SHIFT_CONST(8)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_FIELD                  MK_FIELD_CONST(0x1, AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_SHIFT)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_RANGE                  8:8
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_MSB                    MK_SHIFT_CONST(8)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_LSB                    MK_SHIFT_CONST(8)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_WOFFSET                        0x0
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_DEFAULT                        MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_INIT_ENUM                      MASK
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_UNMASK                 MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_MASK_0_NO_NOC_IDLE_MASK                   MK_ENUM_CONST(1)
+
+
+// Register AOPM_EXT_INTR_SET_0
+#define AOPM_EXT_INTR_SET_0                     MK_ADDR_CONST(0x68)
+#define AOPM_EXT_INTR_SET_0_SECURE                      0x0
+#define AOPM_EXT_INTR_SET_0_DUAL                        0x0
+#define AOPM_EXT_INTR_SET_0_SCR                         SCR_PRIVATE_0
+#define AOPM_EXT_INTR_SET_0_SCRREG                      AOPM_SCR_SCR_PRIVATE_0
+#define AOPM_EXT_INTR_SET_0_WORD_COUNT                  0x1
+#define AOPM_EXT_INTR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_RESET_MASK                  MK_MASK_CONST(0x1ff)
+#define AOPM_EXT_INTR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_READ_MASK                   MK_MASK_CONST(0x1ff)
+#define AOPM_EXT_INTR_SET_0_WRITE_MASK                  MK_MASK_CONST(0x1ff)
+#define AOPM_EXT_INTR_SET_0_RTC_ALARM_SHIFT                     MK_SHIFT_CONST(0)
+#define AOPM_EXT_INTR_SET_0_RTC_ALARM_FIELD                     MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_RTC_ALARM_SHIFT)
+#define AOPM_EXT_INTR_SET_0_RTC_ALARM_RANGE                     0:0
+#define AOPM_EXT_INTR_SET_0_RTC_ALARM_MSB                       MK_SHIFT_CONST(0)
+#define AOPM_EXT_INTR_SET_0_RTC_ALARM_LSB                       MK_SHIFT_CONST(0)
+#define AOPM_EXT_INTR_SET_0_RTC_ALARM_WOFFSET                   0x0
+#define AOPM_EXT_INTR_SET_0_RTC_ALARM_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_RTC_ALARM_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_RTC_ALARM_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_RTC_ALARM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_RTC_ALARM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_RTC_ALARM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_RTC_ALARM_INIT_ENUM                 CLEAR
+#define AOPM_EXT_INTR_SET_0_RTC_ALARM_CLEAR                     MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_SET_0_RTC_ALARM_SET                       MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_SHIFT                    MK_SHIFT_CONST(1)
+#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_FIELD                    MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_NO_CAR_ACK_SHIFT)
+#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_RANGE                    1:1
+#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_MSB                      MK_SHIFT_CONST(1)
+#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_LSB                      MK_SHIFT_CONST(1)
+#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_WOFFSET                  0x0
+#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_INIT_ENUM                        CLEAR
+#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_CLEAR                    MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_SET_0_NO_CAR_ACK_SET                      MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_SHIFT                    MK_SHIFT_CONST(2)
+#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_FIELD                    MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_NO_DVS_ACK_SHIFT)
+#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_RANGE                    2:2
+#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_MSB                      MK_SHIFT_CONST(2)
+#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_LSB                      MK_SHIFT_CONST(2)
+#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_WOFFSET                  0x0
+#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_INIT_ENUM                        CLEAR
+#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_CLEAR                    MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_SET_0_NO_DVS_ACK_SET                      MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_SHIFT                    MK_SHIFT_CONST(3)
+#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_FIELD                    MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_NO_OSC_ACK_SHIFT)
+#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_RANGE                    3:3
+#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_MSB                      MK_SHIFT_CONST(3)
+#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_LSB                      MK_SHIFT_CONST(3)
+#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_WOFFSET                  0x0
+#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_INIT_ENUM                        CLEAR
+#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_CLEAR                    MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_SET_0_NO_OSC_ACK_SET                      MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_SET_0_LP_EXIT_SHIFT                       MK_SHIFT_CONST(4)
+#define AOPM_EXT_INTR_SET_0_LP_EXIT_FIELD                       MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_LP_EXIT_SHIFT)
+#define AOPM_EXT_INTR_SET_0_LP_EXIT_RANGE                       4:4
+#define AOPM_EXT_INTR_SET_0_LP_EXIT_MSB                 MK_SHIFT_CONST(4)
+#define AOPM_EXT_INTR_SET_0_LP_EXIT_LSB                 MK_SHIFT_CONST(4)
+#define AOPM_EXT_INTR_SET_0_LP_EXIT_WOFFSET                     0x0
+#define AOPM_EXT_INTR_SET_0_LP_EXIT_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_LP_EXIT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_LP_EXIT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_LP_EXIT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_LP_EXIT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_LP_EXIT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_LP_EXIT_INIT_ENUM                   CLEAR
+#define AOPM_EXT_INTR_SET_0_LP_EXIT_CLEAR                       MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_SET_0_LP_EXIT_SET                 MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_SET_0_DBG_TO_SHIFT                        MK_SHIFT_CONST(5)
+#define AOPM_EXT_INTR_SET_0_DBG_TO_FIELD                        MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_DBG_TO_SHIFT)
+#define AOPM_EXT_INTR_SET_0_DBG_TO_RANGE                        5:5
+#define AOPM_EXT_INTR_SET_0_DBG_TO_MSB                  MK_SHIFT_CONST(5)
+#define AOPM_EXT_INTR_SET_0_DBG_TO_LSB                  MK_SHIFT_CONST(5)
+#define AOPM_EXT_INTR_SET_0_DBG_TO_WOFFSET                      0x0
+#define AOPM_EXT_INTR_SET_0_DBG_TO_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_DBG_TO_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_DBG_TO_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_DBG_TO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_DBG_TO_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_DBG_TO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_DBG_TO_INIT_ENUM                    CLEAR
+#define AOPM_EXT_INTR_SET_0_DBG_TO_CLEAR                        MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_SET_0_DBG_TO_SET                  MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_SHIFT                    MK_SHIFT_CONST(6)
+#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_FIELD                    MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_NO_RET_ACK_SHIFT)
+#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_RANGE                    6:6
+#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_MSB                      MK_SHIFT_CONST(6)
+#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_LSB                      MK_SHIFT_CONST(6)
+#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_WOFFSET                  0x0
+#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_INIT_ENUM                        CLEAR
+#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_CLEAR                    MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_SET_0_NO_RET_ACK_SET                      MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_SHIFT                       MK_SHIFT_CONST(7)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_FIELD                       MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_SHIFT)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_RANGE                       7:7
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_MSB                 MK_SHIFT_CONST(7)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_LSB                 MK_SHIFT_CONST(7)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_WOFFSET                     0x0
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_INIT_ENUM                   CLEAR
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_CLEAR                       MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_ACK_SET                 MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_SHIFT                   MK_SHIFT_CONST(8)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_FIELD                   MK_FIELD_CONST(0x1, AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_SHIFT)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_RANGE                   8:8
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_MSB                     MK_SHIFT_CONST(8)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_LSB                     MK_SHIFT_CONST(8)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_WOFFSET                 0x0
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_INIT_ENUM                       CLEAR
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_CLEAR                   MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_SET_0_NO_NOC_IDLE_SET                     MK_ENUM_CONST(1)
+
+
+// Register AOPM_EXT_INTR_CLEAR_0
+#define AOPM_EXT_INTR_CLEAR_0                   MK_ADDR_CONST(0x6c)
+#define AOPM_EXT_INTR_CLEAR_0_SECURE                    0x0
+#define AOPM_EXT_INTR_CLEAR_0_DUAL                      0x0
+#define AOPM_EXT_INTR_CLEAR_0_SCR                       SCR_PRIVATE_0
+#define AOPM_EXT_INTR_CLEAR_0_SCRREG                    AOPM_SCR_SCR_PRIVATE_0
+#define AOPM_EXT_INTR_CLEAR_0_WORD_COUNT                        0x1
+#define AOPM_EXT_INTR_CLEAR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_RESET_MASK                        MK_MASK_CONST(0x1ff)
+#define AOPM_EXT_INTR_CLEAR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_READ_MASK                         MK_MASK_CONST(0x1ff)
+#define AOPM_EXT_INTR_CLEAR_0_WRITE_MASK                        MK_MASK_CONST(0x1ff)
+#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_SHIFT                   MK_SHIFT_CONST(0)
+#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_FIELD                   MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_SHIFT)
+#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_RANGE                   0:0
+#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_MSB                     MK_SHIFT_CONST(0)
+#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_LSB                     MK_SHIFT_CONST(0)
+#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_WOFFSET                 0x0
+#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_INIT_ENUM                       DISABLE
+#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_DISABLE                 MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_CLEAR_0_RTC_ALARM_ENABLE                  MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_SHIFT                  MK_SHIFT_CONST(1)
+#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_FIELD                  MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_SHIFT)
+#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_RANGE                  1:1
+#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_MSB                    MK_SHIFT_CONST(1)
+#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_LSB                    MK_SHIFT_CONST(1)
+#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_WOFFSET                        0x0
+#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_INIT_ENUM                      DISABLE
+#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_DISABLE                        MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_CAR_ACK_ENABLE                 MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_SHIFT                  MK_SHIFT_CONST(2)
+#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_FIELD                  MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_SHIFT)
+#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_RANGE                  2:2
+#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_MSB                    MK_SHIFT_CONST(2)
+#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_LSB                    MK_SHIFT_CONST(2)
+#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_WOFFSET                        0x0
+#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_INIT_ENUM                      DISABLE
+#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_DISABLE                        MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_DVS_ACK_ENABLE                 MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_SHIFT                  MK_SHIFT_CONST(3)
+#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_FIELD                  MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_SHIFT)
+#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_RANGE                  3:3
+#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_MSB                    MK_SHIFT_CONST(3)
+#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_LSB                    MK_SHIFT_CONST(3)
+#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_WOFFSET                        0x0
+#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_INIT_ENUM                      DISABLE
+#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_DISABLE                        MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_OSC_ACK_ENABLE                 MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_SHIFT                     MK_SHIFT_CONST(4)
+#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_FIELD                     MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_LP_EXIT_SHIFT)
+#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_RANGE                     4:4
+#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_MSB                       MK_SHIFT_CONST(4)
+#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_LSB                       MK_SHIFT_CONST(4)
+#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_WOFFSET                   0x0
+#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_INIT_ENUM                 DISABLE
+#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_DISABLE                   MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_CLEAR_0_LP_EXIT_ENABLE                    MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_SHIFT                      MK_SHIFT_CONST(5)
+#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_FIELD                      MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_DBG_TO_SHIFT)
+#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_RANGE                      5:5
+#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_MSB                        MK_SHIFT_CONST(5)
+#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_LSB                        MK_SHIFT_CONST(5)
+#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_WOFFSET                    0x0
+#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_INIT_ENUM                  DISABLE
+#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_DISABLE                    MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_CLEAR_0_DBG_TO_ENABLE                     MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_SHIFT                  MK_SHIFT_CONST(6)
+#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_FIELD                  MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_SHIFT)
+#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_RANGE                  6:6
+#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_MSB                    MK_SHIFT_CONST(6)
+#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_LSB                    MK_SHIFT_CONST(6)
+#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_WOFFSET                        0x0
+#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_INIT_ENUM                      DISABLE
+#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_DISABLE                        MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_RET_ACK_ENABLE                 MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_SHIFT                     MK_SHIFT_CONST(7)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_FIELD                     MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_SHIFT)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_RANGE                     7:7
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_MSB                       MK_SHIFT_CONST(7)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_LSB                       MK_SHIFT_CONST(7)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_WOFFSET                   0x0
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_INIT_ENUM                 DISABLE
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_DISABLE                   MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ACK_ENABLE                    MK_ENUM_CONST(1)
+
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_SHIFT                 MK_SHIFT_CONST(8)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_FIELD                 MK_FIELD_CONST(0x1, AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_SHIFT)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_RANGE                 8:8
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_MSB                   MK_SHIFT_CONST(8)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_LSB                   MK_SHIFT_CONST(8)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_WOFFSET                       0x0
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_INIT_ENUM                     DISABLE
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_DISABLE                       MK_ENUM_CONST(0)
+#define AOPM_EXT_INTR_CLEAR_0_NO_NOC_IDLE_ENABLE                        MK_ENUM_CONST(1)
+
+
+// Register AOPM_PM_STATUS_NUM_IDLE_0
+#define AOPM_PM_STATUS_NUM_IDLE_0                       MK_ADDR_CONST(0x70)
+#define AOPM_PM_STATUS_NUM_IDLE_0_SECURE                        0x0
+#define AOPM_PM_STATUS_NUM_IDLE_0_DUAL                  0x0
+#define AOPM_PM_STATUS_NUM_IDLE_0_SCR                   SCR_SHARED_0
+#define AOPM_PM_STATUS_NUM_IDLE_0_SCRREG                        AOPM_SCR_SCR_SHARED_0
+#define AOPM_PM_STATUS_NUM_IDLE_0_WORD_COUNT                    0x1
+#define AOPM_PM_STATUS_NUM_IDLE_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_IDLE_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define AOPM_PM_STATUS_NUM_IDLE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_IDLE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_IDLE_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define AOPM_PM_STATUS_NUM_IDLE_0_WRITE_MASK                    MK_MASK_CONST(0x80000000)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_SHIFT                      MK_SHIFT_CONST(0)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_FIELD                      MK_FIELD_CONST(0x7fffffff, AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_SHIFT)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_RANGE                      30:0
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_MSB                        MK_SHIFT_CONST(30)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_LSB                        MK_SHIFT_CONST(0)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_WOFFSET                    0x0
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_DEFAULT_MASK                       MK_MASK_CONST(0x7fffffff)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_SHIFT                  MK_SHIFT_CONST(31)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_FIELD                  MK_FIELD_CONST(0x1, AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_SHIFT)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_RANGE                  31:31
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_MSB                    MK_SHIFT_CONST(31)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_LSB                    MK_SHIFT_CONST(31)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_WOFFSET                        0x0
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_IDLE_0_PM_STATUS_NUM_IDLE_CLR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register AOPM_PM_STATUS_NUM_STANDBY_0
+#define AOPM_PM_STATUS_NUM_STANDBY_0                    MK_ADDR_CONST(0x74)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_SECURE                     0x0
+#define AOPM_PM_STATUS_NUM_STANDBY_0_DUAL                       0x0
+#define AOPM_PM_STATUS_NUM_STANDBY_0_SCR                        SCR_SHARED_0
+#define AOPM_PM_STATUS_NUM_STANDBY_0_SCRREG                     AOPM_SCR_SCR_SHARED_0
+#define AOPM_PM_STATUS_NUM_STANDBY_0_WORD_COUNT                         0x1
+#define AOPM_PM_STATUS_NUM_STANDBY_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_WRITE_MASK                         MK_MASK_CONST(0x80000000)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_SHIFT                        MK_SHIFT_CONST(0)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_FIELD                        MK_FIELD_CONST(0x7fffffff, AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_SHIFT)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_RANGE                        30:0
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_MSB                  MK_SHIFT_CONST(30)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_LSB                  MK_SHIFT_CONST(0)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_WOFFSET                      0x0
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_DEFAULT_MASK                 MK_MASK_CONST(0x7fffffff)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_SHIFT                    MK_SHIFT_CONST(31)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_FIELD                    MK_FIELD_CONST(0x1, AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_SHIFT)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_RANGE                    31:31
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_MSB                      MK_SHIFT_CONST(31)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_LSB                      MK_SHIFT_CONST(31)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_WOFFSET                  0x0
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_STANDBY_0_PM_STATUS_NUM_STANDBY_CLR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register AOPM_PM_STATUS_NUM_DORMANT_0
+#define AOPM_PM_STATUS_NUM_DORMANT_0                    MK_ADDR_CONST(0x78)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_SECURE                     0x0
+#define AOPM_PM_STATUS_NUM_DORMANT_0_DUAL                       0x0
+#define AOPM_PM_STATUS_NUM_DORMANT_0_SCR                        SCR_SHARED_0
+#define AOPM_PM_STATUS_NUM_DORMANT_0_SCRREG                     AOPM_SCR_SCR_SHARED_0
+#define AOPM_PM_STATUS_NUM_DORMANT_0_WORD_COUNT                         0x1
+#define AOPM_PM_STATUS_NUM_DORMANT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_WRITE_MASK                         MK_MASK_CONST(0x80000000)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_SHIFT                        MK_SHIFT_CONST(0)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_FIELD                        MK_FIELD_CONST(0x7fffffff, AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_SHIFT)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_RANGE                        30:0
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_MSB                  MK_SHIFT_CONST(30)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_LSB                  MK_SHIFT_CONST(0)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_WOFFSET                      0x0
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_DEFAULT_MASK                 MK_MASK_CONST(0x7fffffff)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_SHIFT                    MK_SHIFT_CONST(31)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_FIELD                    MK_FIELD_CONST(0x1, AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_SHIFT)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_RANGE                    31:31
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_MSB                      MK_SHIFT_CONST(31)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_LSB                      MK_SHIFT_CONST(31)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_WOFFSET                  0x0
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_PM_STATUS_NUM_DORMANT_0_PM_STATUS_NUM_DORMANT_CLR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x7c
+
+// Reserved address 0x80
+
+// Reserved address 0x84
+
+// Reserved address 0x88
+
+// Reserved address 0x8c
+
+// Register AOPM_CYA_0
+#define AOPM_CYA_0                      MK_ADDR_CONST(0x90)
+#define AOPM_CYA_0_SECURE                       0x0
+#define AOPM_CYA_0_DUAL                         0x0
+#define AOPM_CYA_0_SCR                  0
+#define AOPM_CYA_0_SCRREG                       0
+#define AOPM_CYA_0_WORD_COUNT                   0x1
+#define AOPM_CYA_0_RESET_VAL                    MK_MASK_CONST(0xfab)
+#define AOPM_CYA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define AOPM_CYA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define AOPM_CYA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_CYA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define AOPM_CYA_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define AOPM_CYA_0_CYA_SHIFT                    MK_SHIFT_CONST(0)
+#define AOPM_CYA_0_CYA_FIELD                    MK_FIELD_CONST(0xffffffff, AOPM_CYA_0_CYA_SHIFT)
+#define AOPM_CYA_0_CYA_RANGE                    31:0
+#define AOPM_CYA_0_CYA_MSB                      MK_SHIFT_CONST(31)
+#define AOPM_CYA_0_CYA_LSB                      MK_SHIFT_CONST(0)
+#define AOPM_CYA_0_CYA_WOFFSET                  0x0
+#define AOPM_CYA_0_CYA_DEFAULT                  MK_MASK_CONST(0xfab)
+#define AOPM_CYA_0_CYA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define AOPM_CYA_0_CYA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_CYA_0_CYA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_CYA_0_CYA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_CYA_0_CYA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register AOPM_CYA
+#define AOPM_CYA                        MK_ADDR_CONST(0x90)
+#define AOPM_CYA_SECURE                         0x0
+#define AOPM_CYA_DUAL                   0x0
+#define AOPM_CYA_SCR                    0
+#define AOPM_CYA_SCRREG                         0
+#define AOPM_CYA_WORD_COUNT                     0x1
+#define AOPM_CYA_RESET_VAL                      MK_MASK_CONST(0xfab)
+#define AOPM_CYA_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define AOPM_CYA_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define AOPM_CYA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_CYA_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define AOPM_CYA_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define AOPM_CYA_CYA_SHIFT                      MK_SHIFT_CONST(0)
+#define AOPM_CYA_CYA_FIELD                      MK_FIELD_CONST(0xffffffff, AOPM_CYA_CYA_SHIFT)
+#define AOPM_CYA_CYA_RANGE                      31:0
+#define AOPM_CYA_CYA_MSB                        MK_SHIFT_CONST(31)
+#define AOPM_CYA_CYA_LSB                        MK_SHIFT_CONST(0)
+#define AOPM_CYA_CYA_WOFFSET                    0x0
+#define AOPM_CYA_CYA_DEFAULT                    MK_MASK_CONST(0xfab)
+#define AOPM_CYA_CYA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define AOPM_CYA_CYA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_CYA_CYA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_CYA_CYA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_CYA_CYA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register AOPM_CYA_1
+#define AOPM_CYA_1                      MK_ADDR_CONST(0x94)
+#define AOPM_CYA_1_SECURE                       0x0
+#define AOPM_CYA_1_DUAL                         0x0
+#define AOPM_CYA_1_SCR                  0
+#define AOPM_CYA_1_SCRREG                       0
+#define AOPM_CYA_1_WORD_COUNT                   0x1
+#define AOPM_CYA_1_RESET_VAL                    MK_MASK_CONST(0xfab)
+#define AOPM_CYA_1_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define AOPM_CYA_1_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define AOPM_CYA_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_CYA_1_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define AOPM_CYA_1_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define AOPM_CYA_1_CYA_SHIFT                    MK_SHIFT_CONST(0)
+#define AOPM_CYA_1_CYA_FIELD                    MK_FIELD_CONST(0xffffffff, AOPM_CYA_1_CYA_SHIFT)
+#define AOPM_CYA_1_CYA_RANGE                    31:0
+#define AOPM_CYA_1_CYA_MSB                      MK_SHIFT_CONST(31)
+#define AOPM_CYA_1_CYA_LSB                      MK_SHIFT_CONST(0)
+#define AOPM_CYA_1_CYA_WOFFSET                  0x0
+#define AOPM_CYA_1_CYA_DEFAULT                  MK_MASK_CONST(0xfab)
+#define AOPM_CYA_1_CYA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define AOPM_CYA_1_CYA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_CYA_1_CYA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_CYA_1_CYA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define AOPM_CYA_1_CYA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register AOPM_RAIL_RET_TIMER_0
+#define AOPM_RAIL_RET_TIMER_0                   MK_ADDR_CONST(0x98)
+#define AOPM_RAIL_RET_TIMER_0_SECURE                    0x0
+#define AOPM_RAIL_RET_TIMER_0_DUAL                      0x0
+#define AOPM_RAIL_RET_TIMER_0_SCR                       SCR_PRIVATE_0
+#define AOPM_RAIL_RET_TIMER_0_SCRREG                    AOPM_SCR_SCR_PRIVATE_0
+#define AOPM_RAIL_RET_TIMER_0_WORD_COUNT                        0x1
+#define AOPM_RAIL_RET_TIMER_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define AOPM_RAIL_RET_TIMER_0_RESET_MASK                        MK_MASK_CONST(0xffff)
+#define AOPM_RAIL_RET_TIMER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define AOPM_RAIL_RET_TIMER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_RAIL_RET_TIMER_0_READ_MASK                         MK_MASK_CONST(0xffff)
+#define AOPM_RAIL_RET_TIMER_0_WRITE_MASK                        MK_MASK_CONST(0xffff)
+#define AOPM_RAIL_RET_TIMER_0_VAL_SHIFT                 MK_SHIFT_CONST(0)
+#define AOPM_RAIL_RET_TIMER_0_VAL_FIELD                 MK_FIELD_CONST(0xffff, AOPM_RAIL_RET_TIMER_0_VAL_SHIFT)
+#define AOPM_RAIL_RET_TIMER_0_VAL_RANGE                 15:0
+#define AOPM_RAIL_RET_TIMER_0_VAL_MSB                   MK_SHIFT_CONST(15)
+#define AOPM_RAIL_RET_TIMER_0_VAL_LSB                   MK_SHIFT_CONST(0)
+#define AOPM_RAIL_RET_TIMER_0_VAL_WOFFSET                       0x0
+#define AOPM_RAIL_RET_TIMER_0_VAL_DEFAULT                       MK_MASK_CONST(0x0)
+#define AOPM_RAIL_RET_TIMER_0_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define AOPM_RAIL_RET_TIMER_0_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_RAIL_RET_TIMER_0_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_RAIL_RET_TIMER_0_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_RAIL_RET_TIMER_0_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register AOPM_EXT_SLCG_0
+#define AOPM_EXT_SLCG_0                 MK_ADDR_CONST(0x9c)
+#define AOPM_EXT_SLCG_0_SECURE                  0x0
+#define AOPM_EXT_SLCG_0_DUAL                    0x0
+#define AOPM_EXT_SLCG_0_SCR                     SCR_PRIVATE_0
+#define AOPM_EXT_SLCG_0_SCRREG                  AOPM_SCR_SCR_PRIVATE_0
+#define AOPM_EXT_SLCG_0_WORD_COUNT                      0x1
+#define AOPM_EXT_SLCG_0_RESET_VAL                       MK_MASK_CONST(0x1)
+#define AOPM_EXT_SLCG_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_EXT_SLCG_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define AOPM_EXT_SLCG_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define AOPM_EXT_SLCG_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_EXT_SLCG_0_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_SHIFT                   MK_SHIFT_CONST(0)
+#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_FIELD                   MK_FIELD_CONST(0x1, AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_SHIFT)
+#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_RANGE                   0:0
+#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_MSB                     MK_SHIFT_CONST(0)
+#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_LSB                     MK_SHIFT_CONST(0)
+#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_WOFFSET                 0x0
+#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_DEFAULT                 MK_MASK_CONST(0x1)
+#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_EXT_SLCG_0_NIC_SLCG_OVR_ON_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register AOPM_SPARE_0
+#define AOPM_SPARE_0                    MK_ADDR_CONST(0xa0)
+#define AOPM_SPARE_0_SECURE                     0x0
+#define AOPM_SPARE_0_DUAL                       0x0
+#define AOPM_SPARE_0_SCR                        0
+#define AOPM_SPARE_0_SCRREG                     0
+#define AOPM_SPARE_0_WORD_COUNT                         0x1
+#define AOPM_SPARE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define AOPM_SPARE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define AOPM_SPARE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define AOPM_SPARE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_SPARE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define AOPM_SPARE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define AOPM_SPARE_0_SPARE_SHIFT                        MK_SHIFT_CONST(0)
+#define AOPM_SPARE_0_SPARE_FIELD                        MK_FIELD_CONST(0xffffffff, AOPM_SPARE_0_SPARE_SHIFT)
+#define AOPM_SPARE_0_SPARE_RANGE                        31:0
+#define AOPM_SPARE_0_SPARE_MSB                  MK_SHIFT_CONST(31)
+#define AOPM_SPARE_0_SPARE_LSB                  MK_SHIFT_CONST(0)
+#define AOPM_SPARE_0_SPARE_WOFFSET                      0x0
+#define AOPM_SPARE_0_SPARE_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_SPARE_0_SPARE_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define AOPM_SPARE_0_SPARE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_SPARE_0_SPARE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_SPARE_0_SPARE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_SPARE_0_SPARE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register AOPM_SPARE
+#define AOPM_SPARE                      MK_ADDR_CONST(0xa0)
+#define AOPM_SPARE_SECURE                       0x0
+#define AOPM_SPARE_DUAL                         0x0
+#define AOPM_SPARE_SCR                  0
+#define AOPM_SPARE_SCRREG                       0
+#define AOPM_SPARE_WORD_COUNT                   0x1
+#define AOPM_SPARE_RESET_VAL                    MK_MASK_CONST(0x0)
+#define AOPM_SPARE_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define AOPM_SPARE_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define AOPM_SPARE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_SPARE_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define AOPM_SPARE_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define AOPM_SPARE_SPARE_SHIFT                  MK_SHIFT_CONST(0)
+#define AOPM_SPARE_SPARE_FIELD                  MK_FIELD_CONST(0xffffffff, AOPM_SPARE_SPARE_SHIFT)
+#define AOPM_SPARE_SPARE_RANGE                  31:0
+#define AOPM_SPARE_SPARE_MSB                    MK_SHIFT_CONST(31)
+#define AOPM_SPARE_SPARE_LSB                    MK_SHIFT_CONST(0)
+#define AOPM_SPARE_SPARE_WOFFSET                        0x0
+#define AOPM_SPARE_SPARE_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_SPARE_SPARE_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define AOPM_SPARE_SPARE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_SPARE_SPARE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_SPARE_SPARE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_SPARE_SPARE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register AOPM_SPARE_1
+#define AOPM_SPARE_1                    MK_ADDR_CONST(0xa4)
+#define AOPM_SPARE_1_SECURE                     0x0
+#define AOPM_SPARE_1_DUAL                       0x0
+#define AOPM_SPARE_1_SCR                        0
+#define AOPM_SPARE_1_SCRREG                     0
+#define AOPM_SPARE_1_WORD_COUNT                         0x1
+#define AOPM_SPARE_1_RESET_VAL                  MK_MASK_CONST(0x0)
+#define AOPM_SPARE_1_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define AOPM_SPARE_1_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define AOPM_SPARE_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_SPARE_1_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define AOPM_SPARE_1_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define AOPM_SPARE_1_SPARE_SHIFT                        MK_SHIFT_CONST(0)
+#define AOPM_SPARE_1_SPARE_FIELD                        MK_FIELD_CONST(0xffffffff, AOPM_SPARE_1_SPARE_SHIFT)
+#define AOPM_SPARE_1_SPARE_RANGE                        31:0
+#define AOPM_SPARE_1_SPARE_MSB                  MK_SHIFT_CONST(31)
+#define AOPM_SPARE_1_SPARE_LSB                  MK_SHIFT_CONST(0)
+#define AOPM_SPARE_1_SPARE_WOFFSET                      0x0
+#define AOPM_SPARE_1_SPARE_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_SPARE_1_SPARE_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define AOPM_SPARE_1_SPARE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_SPARE_1_SPARE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_SPARE_1_SPARE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_SPARE_1_SPARE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register AOPM_SPARE_2
+#define AOPM_SPARE_2                    MK_ADDR_CONST(0xa8)
+#define AOPM_SPARE_2_SECURE                     0x0
+#define AOPM_SPARE_2_DUAL                       0x0
+#define AOPM_SPARE_2_SCR                        0
+#define AOPM_SPARE_2_SCRREG                     0
+#define AOPM_SPARE_2_WORD_COUNT                         0x1
+#define AOPM_SPARE_2_RESET_VAL                  MK_MASK_CONST(0x0)
+#define AOPM_SPARE_2_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define AOPM_SPARE_2_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define AOPM_SPARE_2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_SPARE_2_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define AOPM_SPARE_2_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define AOPM_SPARE_2_SPARE_SHIFT                        MK_SHIFT_CONST(0)
+#define AOPM_SPARE_2_SPARE_FIELD                        MK_FIELD_CONST(0xffffffff, AOPM_SPARE_2_SPARE_SHIFT)
+#define AOPM_SPARE_2_SPARE_RANGE                        31:0
+#define AOPM_SPARE_2_SPARE_MSB                  MK_SHIFT_CONST(31)
+#define AOPM_SPARE_2_SPARE_LSB                  MK_SHIFT_CONST(0)
+#define AOPM_SPARE_2_SPARE_WOFFSET                      0x0
+#define AOPM_SPARE_2_SPARE_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_SPARE_2_SPARE_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define AOPM_SPARE_2_SPARE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_SPARE_2_SPARE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_SPARE_2_SPARE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_SPARE_2_SPARE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xac
+
+// Reserved address 0xb0
+
+// Register AOPM_SEC_LATCH_0
+#define AOPM_SEC_LATCH_0                        MK_ADDR_CONST(0xb4)
+#define AOPM_SEC_LATCH_0_SECURE                         0x0
+#define AOPM_SEC_LATCH_0_DUAL                   0x0
+#define AOPM_SEC_LATCH_0_SCR                    SCR_PRIVATE_0
+#define AOPM_SEC_LATCH_0_SCRREG                         AOPM_SCR_SCR_PRIVATE_0
+#define AOPM_SEC_LATCH_0_WORD_COUNT                     0x1
+#define AOPM_SEC_LATCH_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_SEC_LATCH_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_SEC_LATCH_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define AOPM_SEC_LATCH_0_UPD_SHIFT                      MK_SHIFT_CONST(0)
+#define AOPM_SEC_LATCH_0_UPD_FIELD                      MK_FIELD_CONST(0x1, AOPM_SEC_LATCH_0_UPD_SHIFT)
+#define AOPM_SEC_LATCH_0_UPD_RANGE                      0:0
+#define AOPM_SEC_LATCH_0_UPD_MSB                        MK_SHIFT_CONST(0)
+#define AOPM_SEC_LATCH_0_UPD_LSB                        MK_SHIFT_CONST(0)
+#define AOPM_SEC_LATCH_0_UPD_WOFFSET                    0x0
+#define AOPM_SEC_LATCH_0_UPD_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_0_UPD_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_SEC_LATCH_0_UPD_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_0_UPD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_0_UPD_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_0_UPD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define AOPM_SEC_LATCH_0_UPD_INIT_ENUM                  DISABLE
+#define AOPM_SEC_LATCH_0_UPD_DISABLE                    MK_ENUM_CONST(0)
+#define AOPM_SEC_LATCH_0_UPD_ENABLE                     MK_ENUM_CONST(1)
+
+
+// Register AOPM_AON_BLOCK_0
+#define AOPM_AON_BLOCK_0                        MK_ADDR_CONST(0xb8)
+#define AOPM_AON_BLOCK_0_SECURE                         0x0
+#define AOPM_AON_BLOCK_0_DUAL                   0x0
+#define AOPM_AON_BLOCK_0_SCR                    AXI_BLOCK_SCR_0
+#define AOPM_AON_BLOCK_0_SCRREG                         AOPM_SCR_AXI_BLOCK_SCR_0
+#define AOPM_AON_BLOCK_0_WORD_COUNT                     0x1
+#define AOPM_AON_BLOCK_0_RESET_VAL                      MK_MASK_CONST(0x5)
+#define AOPM_AON_BLOCK_0_RESET_MASK                     MK_MASK_CONST(0x7)
+#define AOPM_AON_BLOCK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define AOPM_AON_BLOCK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_AON_BLOCK_0_READ_MASK                      MK_MASK_CONST(0x7)
+#define AOPM_AON_BLOCK_0_WRITE_MASK                     MK_MASK_CONST(0x7)
+#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_SHIFT                     MK_SHIFT_CONST(0)
+#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_FIELD                     MK_FIELD_CONST(0x1, AOPM_AON_BLOCK_0_AON2SNIC_REQ_SHIFT)
+#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_RANGE                     0:0
+#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_MSB                       MK_SHIFT_CONST(0)
+#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_LSB                       MK_SHIFT_CONST(0)
+#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_WOFFSET                   0x0
+#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_DEFAULT                   MK_MASK_CONST(0x1)
+#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_INIT_ENUM                 ENABLE
+#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_DISABLE                   MK_ENUM_CONST(0)
+#define AOPM_AON_BLOCK_0_AON2SNIC_REQ_ENABLE                    MK_ENUM_CONST(1)
+
+#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_SHIFT                  MK_SHIFT_CONST(1)
+#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_FIELD                  MK_FIELD_CONST(0x1, AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_SHIFT)
+#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_RANGE                  1:1
+#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_MSB                    MK_SHIFT_CONST(1)
+#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_LSB                    MK_SHIFT_CONST(1)
+#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_WOFFSET                        0x0
+#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_INIT_ENUM                      DISABLE
+#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_DISABLE                        MK_ENUM_CONST(0)
+#define AOPM_AON_BLOCK_0_WAKE_ON_TXN_REQ_ENABLE                 MK_ENUM_CONST(1)
+
+#define AOPM_AON_BLOCK_0_AON2MC_REQ_SHIFT                       MK_SHIFT_CONST(2)
+#define AOPM_AON_BLOCK_0_AON2MC_REQ_FIELD                       MK_FIELD_CONST(0x1, AOPM_AON_BLOCK_0_AON2MC_REQ_SHIFT)
+#define AOPM_AON_BLOCK_0_AON2MC_REQ_RANGE                       2:2
+#define AOPM_AON_BLOCK_0_AON2MC_REQ_MSB                 MK_SHIFT_CONST(2)
+#define AOPM_AON_BLOCK_0_AON2MC_REQ_LSB                 MK_SHIFT_CONST(2)
+#define AOPM_AON_BLOCK_0_AON2MC_REQ_WOFFSET                     0x0
+#define AOPM_AON_BLOCK_0_AON2MC_REQ_DEFAULT                     MK_MASK_CONST(0x1)
+#define AOPM_AON_BLOCK_0_AON2MC_REQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define AOPM_AON_BLOCK_0_AON2MC_REQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define AOPM_AON_BLOCK_0_AON2MC_REQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_AON_BLOCK_0_AON2MC_REQ_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define AOPM_AON_BLOCK_0_AON2MC_REQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define AOPM_AON_BLOCK_0_AON2MC_REQ_INIT_ENUM                   ENABLE
+#define AOPM_AON_BLOCK_0_AON2MC_REQ_DISABLE                     MK_ENUM_CONST(0)
+#define AOPM_AON_BLOCK_0_AON2MC_REQ_ENABLE                      MK_ENUM_CONST(1)
+
+
+// Register AOPM_DVS_VOLT_INDEX_0
+#define AOPM_DVS_VOLT_INDEX_0                   MK_ADDR_CONST(0xbc)
+#define AOPM_DVS_VOLT_INDEX_0_SECURE                    0x0
+#define AOPM_DVS_VOLT_INDEX_0_DUAL                      0x0
+#define AOPM_DVS_VOLT_INDEX_0_SCR                       SCR_PRIVATE_0
+#define AOPM_DVS_VOLT_INDEX_0_SCRREG                    AOPM_SCR_SCR_PRIVATE_0
+#define AOPM_DVS_VOLT_INDEX_0_WORD_COUNT                        0x1
+#define AOPM_DVS_VOLT_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define AOPM_DVS_VOLT_INDEX_0_RESET_MASK                        MK_MASK_CONST(0x3f3f)
+#define AOPM_DVS_VOLT_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define AOPM_DVS_VOLT_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_DVS_VOLT_INDEX_0_READ_MASK                         MK_MASK_CONST(0x3f3f)
+#define AOPM_DVS_VOLT_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0x3f3f)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_SHIFT                      MK_SHIFT_CONST(0)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_FIELD                      MK_FIELD_CONST(0x3f, AOPM_DVS_VOLT_INDEX_0_IDX_IN_SHIFT)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_RANGE                      5:0
+#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_MSB                        MK_SHIFT_CONST(5)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_LSB                        MK_SHIFT_CONST(0)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_WOFFSET                    0x0
+#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_DEFAULT_MASK                       MK_MASK_CONST(0x3f)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_IN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_SHIFT                     MK_SHIFT_CONST(8)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_FIELD                     MK_FIELD_CONST(0x3f, AOPM_DVS_VOLT_INDEX_0_IDX_OUT_SHIFT)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_RANGE                     13:8
+#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_MSB                       MK_SHIFT_CONST(13)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_LSB                       MK_SHIFT_CONST(8)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_WOFFSET                   0x0
+#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_DEFAULT_MASK                      MK_MASK_CONST(0x3f)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define AOPM_DVS_VOLT_INDEX_0_IDX_OUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register AOPM_RTC_ALARM_TIMER_0
+#define AOPM_RTC_ALARM_TIMER_0                  MK_ADDR_CONST(0xc0)
+#define AOPM_RTC_ALARM_TIMER_0_SECURE                   0x0
+#define AOPM_RTC_ALARM_TIMER_0_DUAL                     0x0
+#define AOPM_RTC_ALARM_TIMER_0_SCR                      SCR_SHARED_0
+#define AOPM_RTC_ALARM_TIMER_0_SCRREG                   AOPM_SCR_SCR_SHARED_0
+#define AOPM_RTC_ALARM_TIMER_0_WORD_COUNT                       0x1
+#define AOPM_RTC_ALARM_TIMER_0_RESET_VAL                        MK_MASK_CONST(0x10)
+#define AOPM_RTC_ALARM_TIMER_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define AOPM_RTC_ALARM_TIMER_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define AOPM_RTC_ALARM_TIMER_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define AOPM_RTC_ALARM_TIMER_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define AOPM_RTC_ALARM_TIMER_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define AOPM_RTC_ALARM_TIMER_0_VAL_SHIFT                        MK_SHIFT_CONST(0)
+#define AOPM_RTC_ALARM_TIMER_0_VAL_FIELD                        MK_FIELD_CONST(0xffffffff, AOPM_RTC_ALARM_TIMER_0_VAL_SHIFT)
+#define AOPM_RTC_ALARM_TIMER_0_VAL_RANGE                        31:0
+#define AOPM_RTC_ALARM_TIMER_0_VAL_MSB                  MK_SHIFT_CONST(31)
+#define AOPM_RTC_ALARM_TIMER_0_VAL_LSB                  MK_SHIFT_CONST(0)
+#define AOPM_RTC_ALARM_TIMER_0_VAL_WOFFSET                      0x0
+#define AOPM_RTC_ALARM_TIMER_0_VAL_DEFAULT                      MK_MASK_CONST(0x10)
+#define AOPM_RTC_ALARM_TIMER_0_VAL_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define AOPM_RTC_ALARM_TIMER_0_VAL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define AOPM_RTC_ALARM_TIMER_0_VAL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_RTC_ALARM_TIMER_0_VAL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define AOPM_RTC_ALARM_TIMER_0_VAL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register AOPM_RTC_ALARM_MSEC_TIMER_0
+#define AOPM_RTC_ALARM_MSEC_TIMER_0                     MK_ADDR_CONST(0xc4)
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_SECURE                      0x0
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_DUAL                        0x0
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_SCR                         SCR_SHARED_0
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_SCRREG                      AOPM_SCR_SCR_SHARED_0
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_WORD_COUNT                  0x1
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_RESET_MASK                  MK_MASK_CONST(0x3ff)
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_READ_MASK                   MK_MASK_CONST(0x3ff)
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_WRITE_MASK                  MK_MASK_CONST(0x3ff)
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_FIELD                   MK_FIELD_CONST(0x3ff, AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_SHIFT)
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_RANGE                   9:0
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_MSB                     MK_SHIFT_CONST(9)
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_WOFFSET                 0x0
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3ff)
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_RTC_ALARM_MSEC_TIMER_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xc8
+
+// Register AOPM_SEC_LATCH_STATUS_0
+#define AOPM_SEC_LATCH_STATUS_0                 MK_ADDR_CONST(0xcc)
+#define AOPM_SEC_LATCH_STATUS_0_SECURE                  0x0
+#define AOPM_SEC_LATCH_STATUS_0_DUAL                    0x0
+#define AOPM_SEC_LATCH_STATUS_0_SCR                     SCR_PRIVATE_0
+#define AOPM_SEC_LATCH_STATUS_0_SCRREG                  AOPM_SCR_SCR_PRIVATE_0
+#define AOPM_SEC_LATCH_STATUS_0_WORD_COUNT                      0x1
+#define AOPM_SEC_LATCH_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x1fffe)
+#define AOPM_SEC_LATCH_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x1ffff)
+#define AOPM_SEC_LATCH_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_READ_MASK                       MK_MASK_CONST(0x1ffff)
+#define AOPM_SEC_LATCH_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_LOCK_SHIFT                      MK_SHIFT_CONST(0)
+#define AOPM_SEC_LATCH_STATUS_0_LOCK_FIELD                      MK_FIELD_CONST(0x1, AOPM_SEC_LATCH_STATUS_0_LOCK_SHIFT)
+#define AOPM_SEC_LATCH_STATUS_0_LOCK_RANGE                      0:0
+#define AOPM_SEC_LATCH_STATUS_0_LOCK_MSB                        MK_SHIFT_CONST(0)
+#define AOPM_SEC_LATCH_STATUS_0_LOCK_LSB                        MK_SHIFT_CONST(0)
+#define AOPM_SEC_LATCH_STATUS_0_LOCK_WOFFSET                    0x0
+#define AOPM_SEC_LATCH_STATUS_0_LOCK_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_LOCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define AOPM_SEC_LATCH_STATUS_0_LOCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_LOCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_LOCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_LOCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_SHIFT                   MK_SHIFT_CONST(1)
+#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_FIELD                   MK_FIELD_CONST(0x1, AOPM_SEC_LATCH_STATUS_0_AWPROT1_SHIFT)
+#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_RANGE                   1:1
+#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_MSB                     MK_SHIFT_CONST(1)
+#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_LSB                     MK_SHIFT_CONST(1)
+#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_WOFFSET                 0x0
+#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_DEFAULT                 MK_MASK_CONST(0x1)
+#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_AWPROT1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_SHIFT                   MK_SHIFT_CONST(2)
+#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_FIELD                   MK_FIELD_CONST(0x1, AOPM_SEC_LATCH_STATUS_0_ARPROT1_SHIFT)
+#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_RANGE                   2:2
+#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_MSB                     MK_SHIFT_CONST(2)
+#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_LSB                     MK_SHIFT_CONST(2)
+#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_WOFFSET                 0x0
+#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_DEFAULT                 MK_MASK_CONST(0x1)
+#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_ARPROT1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_SHIFT                 MK_SHIFT_CONST(3)
+#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_FIELD                 MK_FIELD_CONST(0x7f, AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_SHIFT)
+#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_RANGE                 9:3
+#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_MSB                   MK_SHIFT_CONST(9)
+#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_LSB                   MK_SHIFT_CONST(3)
+#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_WOFFSET                       0x0
+#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_DEFAULT                       MK_MASK_CONST(0x7f)
+#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_DEFAULT_MASK                  MK_MASK_CONST(0x7f)
+#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_AWUSER_NS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_SHIFT                 MK_SHIFT_CONST(10)
+#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_FIELD                 MK_FIELD_CONST(0x7f, AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_SHIFT)
+#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_RANGE                 16:10
+#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_MSB                   MK_SHIFT_CONST(16)
+#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_LSB                   MK_SHIFT_CONST(10)
+#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_WOFFSET                       0x0
+#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_DEFAULT                       MK_MASK_CONST(0x7f)
+#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_DEFAULT_MASK                  MK_MASK_CONST(0x7f)
+#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define AOPM_SEC_LATCH_STATUS_0_ARUSER_NS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAOPM_REGS(_op_) \
+_op_(AOPM_SOFT_RESET_0) \
+_op_(AOPM_SLCG_CTRL_0) \
+_op_(AOPM_TGT_PWR_STATE_0) \
+_op_(AOPM_TCM_RET_TIMER_0) \
+_op_(AOPM_DBG_TIMER_0) \
+_op_(AOPM_LP_EXIT_0) \
+_op_(AOPM_POWER_CFG_MASK_0) \
+_op_(AOPM_TGT_PWR_CFG_ORIDE_0) \
+_op_(AOPM_PWR_STATUS_0) \
+_op_(AOPM_DBG_STATUS_0) \
+_op_(AOPM_DBG_FEATURES_0) \
+_op_(AOPM_EXIT_MASK_0) \
+_op_(AOPM_BURST_CLK_0) \
+_op_(AOPM_ACTIRQFIQ_TO_ACT_0) \
+_op_(AOPM_CSITE_CFG_0) \
+_op_(AOPM_R5_CFG_0) \
+_op_(AOPM_R5_CTRL_0) \
+_op_(AOPM_TCM_SEL_0) \
+_op_(AOPM_TCM_SLCG_0) \
+_op_(AOPM_ACTMON_0) \
+_op_(AOPM_R5_INTR_STATUS_0) \
+_op_(AOPM_R5_INTR_MASK_0) \
+_op_(AOPM_R5_INTR_SET_0) \
+_op_(AOPM_R5_INTR_CLEAR_0) \
+_op_(AOPM_EXT_INTR_STATUS_0) \
+_op_(AOPM_EXT_INTR_MASK_0) \
+_op_(AOPM_EXT_INTR_SET_0) \
+_op_(AOPM_EXT_INTR_CLEAR_0) \
+_op_(AOPM_PM_STATUS_NUM_IDLE_0) \
+_op_(AOPM_PM_STATUS_NUM_STANDBY_0) \
+_op_(AOPM_PM_STATUS_NUM_DORMANT_0) \
+_op_(AOPM_CYA_0) \
+_op_(AOPM_CYA) \
+_op_(AOPM_CYA_1) \
+_op_(AOPM_RAIL_RET_TIMER_0) \
+_op_(AOPM_EXT_SLCG_0) \
+_op_(AOPM_SPARE_0) \
+_op_(AOPM_SPARE) \
+_op_(AOPM_SPARE_1) \
+_op_(AOPM_SPARE_2) \
+_op_(AOPM_SEC_LATCH_0) \
+_op_(AOPM_AON_BLOCK_0) \
+_op_(AOPM_DVS_VOLT_INDEX_0) \
+_op_(AOPM_RTC_ALARM_TIMER_0) \
+_op_(AOPM_RTC_ALARM_MSEC_TIMER_0) \
+_op_(AOPM_SEC_LATCH_STATUS_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_AOPM       0x00000000
+
+//
+// ARAOPM REGISTER BANKS
+//
+
+#define AOPM0_FIRST_REG 0x0000 // AOPM_SOFT_RESET_0
+#define AOPM0_LAST_REG 0x0078 // AOPM_PM_STATUS_NUM_DORMANT_0
+#define AOPM1_FIRST_REG 0x0090 // AOPM_CYA_0
+#define AOPM1_LAST_REG 0x00a8 // AOPM_SPARE_2
+#define AOPM2_FIRST_REG 0x00b4 // AOPM_SEC_LATCH_0
+#define AOPM2_LAST_REG 0x00c4 // AOPM_RTC_ALARM_MSEC_TIMER_0
+#define AOPM3_FIRST_REG 0x00cc // AOPM_SEC_LATCH_STATUS_0
+#define AOPM3_LAST_REG 0x00cc // AOPM_SEC_LATCH_STATUS_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARAOPM_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/araps_ast.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/araps_ast.h
new file mode 100644
index 0000000..fdafe09
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/araps_ast.h
@@ -0,0 +1,3286 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARAPS_AST_H_INC
+#define ARAPS_AST_H_INC
+#define NV_MOBILE_ARAPS_AST_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARAPS_AST_H_SCRREG_NOMENCLATURE INFERRED
+
+
+// Register APS_AST_CONTROL_0
+#define APS_AST_CONTROL_0                       MK_ADDR_CONST(0x0)
+#define APS_AST_CONTROL_0_SECURE                        0x0
+#define APS_AST_CONTROL_0_DUAL                  0x0
+#define APS_AST_CONTROL_0_SCR                   AST_GBL_SEC_CONTROL_0
+#define APS_AST_CONTROL_0_SCRREG                        APS_AST_SCR_AST_GBL_SEC_CONTROL_0
+#define APS_AST_CONTROL_0_WORD_COUNT                    0x1
+#define APS_AST_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1fc80000)
+#define APS_AST_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0xffdf83e7)
+#define APS_AST_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_READ_MASK                     MK_MASK_CONST(0xffdf83e7)
+#define APS_AST_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0xffdf83e7)
+#define APS_AST_CONTROL_0_ApbOvrOn_SHIFT                        MK_SHIFT_CONST(31)
+#define APS_AST_CONTROL_0_ApbOvrOn_FIELD                        MK_FIELD_CONST(0x1, APS_AST_CONTROL_0_ApbOvrOn_SHIFT)
+#define APS_AST_CONTROL_0_ApbOvrOn_RANGE                        31:31
+#define APS_AST_CONTROL_0_ApbOvrOn_MSB                  MK_SHIFT_CONST(31)
+#define APS_AST_CONTROL_0_ApbOvrOn_LSB                  MK_SHIFT_CONST(31)
+#define APS_AST_CONTROL_0_ApbOvrOn_WOFFSET                      0x0
+#define APS_AST_CONTROL_0_ApbOvrOn_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_ApbOvrOn_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define APS_AST_CONTROL_0_ApbOvrOn_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_ApbOvrOn_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_ApbOvrOn_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_ApbOvrOn_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define APS_AST_CONTROL_0_NicOvrOn_SHIFT                        MK_SHIFT_CONST(30)
+#define APS_AST_CONTROL_0_NicOvrOn_FIELD                        MK_FIELD_CONST(0x1, APS_AST_CONTROL_0_NicOvrOn_SHIFT)
+#define APS_AST_CONTROL_0_NicOvrOn_RANGE                        30:30
+#define APS_AST_CONTROL_0_NicOvrOn_MSB                  MK_SHIFT_CONST(30)
+#define APS_AST_CONTROL_0_NicOvrOn_LSB                  MK_SHIFT_CONST(30)
+#define APS_AST_CONTROL_0_NicOvrOn_WOFFSET                      0x0
+#define APS_AST_CONTROL_0_NicOvrOn_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_NicOvrOn_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define APS_AST_CONTROL_0_NicOvrOn_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_NicOvrOn_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_NicOvrOn_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_NicOvrOn_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define APS_AST_CONTROL_0_CarveOutLock_SHIFT                    MK_SHIFT_CONST(20)
+#define APS_AST_CONTROL_0_CarveOutLock_FIELD                    MK_FIELD_CONST(0x1, APS_AST_CONTROL_0_CarveOutLock_SHIFT)
+#define APS_AST_CONTROL_0_CarveOutLock_RANGE                    20:20
+#define APS_AST_CONTROL_0_CarveOutLock_MSB                      MK_SHIFT_CONST(20)
+#define APS_AST_CONTROL_0_CarveOutLock_LSB                      MK_SHIFT_CONST(20)
+#define APS_AST_CONTROL_0_CarveOutLock_WOFFSET                  0x0
+#define APS_AST_CONTROL_0_CarveOutLock_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_CarveOutLock_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define APS_AST_CONTROL_0_CarveOutLock_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_CarveOutLock_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_CarveOutLock_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_CarveOutLock_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define APS_AST_CONTROL_0_CarveOutLock_FALSE                    MK_ENUM_CONST(0)
+#define APS_AST_CONTROL_0_CarveOutLock_TRUE                     MK_ENUM_CONST(1)
+
+#define APS_AST_CONTROL_0_DefPhysical_SHIFT                     MK_SHIFT_CONST(19)
+#define APS_AST_CONTROL_0_DefPhysical_FIELD                     MK_FIELD_CONST(0x1, APS_AST_CONTROL_0_DefPhysical_SHIFT)
+#define APS_AST_CONTROL_0_DefPhysical_RANGE                     19:19
+#define APS_AST_CONTROL_0_DefPhysical_MSB                       MK_SHIFT_CONST(19)
+#define APS_AST_CONTROL_0_DefPhysical_LSB                       MK_SHIFT_CONST(19)
+#define APS_AST_CONTROL_0_DefPhysical_WOFFSET                   0x0
+#define APS_AST_CONTROL_0_DefPhysical_DEFAULT                   MK_MASK_CONST(0x1)
+#define APS_AST_CONTROL_0_DefPhysical_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define APS_AST_CONTROL_0_DefPhysical_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_DefPhysical_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_DefPhysical_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_DefPhysical_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define APS_AST_CONTROL_0_DefVMIndex_SHIFT                      MK_SHIFT_CONST(15)
+#define APS_AST_CONTROL_0_DefVMIndex_FIELD                      MK_FIELD_CONST(0xf, APS_AST_CONTROL_0_DefVMIndex_SHIFT)
+#define APS_AST_CONTROL_0_DefVMIndex_RANGE                      18:15
+#define APS_AST_CONTROL_0_DefVMIndex_MSB                        MK_SHIFT_CONST(18)
+#define APS_AST_CONTROL_0_DefVMIndex_LSB                        MK_SHIFT_CONST(15)
+#define APS_AST_CONTROL_0_DefVMIndex_WOFFSET                    0x0
+#define APS_AST_CONTROL_0_DefVMIndex_DEFAULT                    MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_DefVMIndex_DEFAULT_MASK                       MK_MASK_CONST(0xf)
+#define APS_AST_CONTROL_0_DefVMIndex_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_DefVMIndex_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_DefVMIndex_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_DefVMIndex_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define APS_AST_CONTROL_0_DefCarveOutID_SHIFT                   MK_SHIFT_CONST(5)
+#define APS_AST_CONTROL_0_DefCarveOutID_FIELD                   MK_FIELD_CONST(0x1f, APS_AST_CONTROL_0_DefCarveOutID_SHIFT)
+#define APS_AST_CONTROL_0_DefCarveOutID_RANGE                   9:5
+#define APS_AST_CONTROL_0_DefCarveOutID_MSB                     MK_SHIFT_CONST(9)
+#define APS_AST_CONTROL_0_DefCarveOutID_LSB                     MK_SHIFT_CONST(5)
+#define APS_AST_CONTROL_0_DefCarveOutID_WOFFSET                 0x0
+#define APS_AST_CONTROL_0_DefCarveOutID_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_DefCarveOutID_DEFAULT_MASK                    MK_MASK_CONST(0x1f)
+#define APS_AST_CONTROL_0_DefCarveOutID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_DefCarveOutID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_DefCarveOutID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_DefCarveOutID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define APS_AST_CONTROL_0_DefSnoop_SHIFT                        MK_SHIFT_CONST(2)
+#define APS_AST_CONTROL_0_DefSnoop_FIELD                        MK_FIELD_CONST(0x1, APS_AST_CONTROL_0_DefSnoop_SHIFT)
+#define APS_AST_CONTROL_0_DefSnoop_RANGE                        2:2
+#define APS_AST_CONTROL_0_DefSnoop_MSB                  MK_SHIFT_CONST(2)
+#define APS_AST_CONTROL_0_DefSnoop_LSB                  MK_SHIFT_CONST(2)
+#define APS_AST_CONTROL_0_DefSnoop_WOFFSET                      0x0
+#define APS_AST_CONTROL_0_DefSnoop_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_DefSnoop_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define APS_AST_CONTROL_0_DefSnoop_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_DefSnoop_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_DefSnoop_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_DefSnoop_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define APS_AST_CONTROL_0_DefSnoop_DISABLE                      MK_ENUM_CONST(0)
+#define APS_AST_CONTROL_0_DefSnoop_ENABLE                       MK_ENUM_CONST(1)
+
+#define APS_AST_CONTROL_0_MatchErrCtl_SHIFT                     MK_SHIFT_CONST(1)
+#define APS_AST_CONTROL_0_MatchErrCtl_FIELD                     MK_FIELD_CONST(0x1, APS_AST_CONTROL_0_MatchErrCtl_SHIFT)
+#define APS_AST_CONTROL_0_MatchErrCtl_RANGE                     1:1
+#define APS_AST_CONTROL_0_MatchErrCtl_MSB                       MK_SHIFT_CONST(1)
+#define APS_AST_CONTROL_0_MatchErrCtl_LSB                       MK_SHIFT_CONST(1)
+#define APS_AST_CONTROL_0_MatchErrCtl_WOFFSET                   0x0
+#define APS_AST_CONTROL_0_MatchErrCtl_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_MatchErrCtl_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define APS_AST_CONTROL_0_MatchErrCtl_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_MatchErrCtl_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_MatchErrCtl_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_MatchErrCtl_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define APS_AST_CONTROL_0_MatchErrCtl_NO_DECERR                 MK_ENUM_CONST(0)
+#define APS_AST_CONTROL_0_MatchErrCtl_DECERR                    MK_ENUM_CONST(1)
+
+#define APS_AST_CONTROL_0_Lock_SHIFT                    MK_SHIFT_CONST(0)
+#define APS_AST_CONTROL_0_Lock_FIELD                    MK_FIELD_CONST(0x1, APS_AST_CONTROL_0_Lock_SHIFT)
+#define APS_AST_CONTROL_0_Lock_RANGE                    0:0
+#define APS_AST_CONTROL_0_Lock_MSB                      MK_SHIFT_CONST(0)
+#define APS_AST_CONTROL_0_Lock_LSB                      MK_SHIFT_CONST(0)
+#define APS_AST_CONTROL_0_Lock_WOFFSET                  0x0
+#define APS_AST_CONTROL_0_Lock_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_Lock_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define APS_AST_CONTROL_0_Lock_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_Lock_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_Lock_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define APS_AST_CONTROL_0_Lock_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define APS_AST_CONTROL_0_Lock_FALSE                    MK_ENUM_CONST(0)
+#define APS_AST_CONTROL_0_Lock_TRUE                     MK_ENUM_CONST(1)
+
+
+// Register APS_AST_ERROR_STATUS_0
+#define APS_AST_ERROR_STATUS_0                  MK_ADDR_CONST(0x4)
+#define APS_AST_ERROR_STATUS_0_SECURE                   0x0
+#define APS_AST_ERROR_STATUS_0_DUAL                     0x0
+#define APS_AST_ERROR_STATUS_0_SCR                      AST_GBL_SEC_CONTROL_0
+#define APS_AST_ERROR_STATUS_0_SCRREG                   APS_AST_SCR_AST_GBL_SEC_CONTROL_0
+#define APS_AST_ERROR_STATUS_0_WORD_COUNT                       0x1
+#define APS_AST_ERROR_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x7)
+#define APS_AST_ERROR_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_STATUS_0_READ_MASK                        MK_MASK_CONST(0x7)
+#define APS_AST_ERROR_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define APS_AST_ERROR_STATUS_0_Overflow_SHIFT                   MK_SHIFT_CONST(2)
+#define APS_AST_ERROR_STATUS_0_Overflow_FIELD                   MK_FIELD_CONST(0x1, APS_AST_ERROR_STATUS_0_Overflow_SHIFT)
+#define APS_AST_ERROR_STATUS_0_Overflow_RANGE                   2:2
+#define APS_AST_ERROR_STATUS_0_Overflow_MSB                     MK_SHIFT_CONST(2)
+#define APS_AST_ERROR_STATUS_0_Overflow_LSB                     MK_SHIFT_CONST(2)
+#define APS_AST_ERROR_STATUS_0_Overflow_WOFFSET                 0x0
+#define APS_AST_ERROR_STATUS_0_Overflow_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_STATUS_0_Overflow_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_AST_ERROR_STATUS_0_Overflow_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_STATUS_0_Overflow_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_STATUS_0_Overflow_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_STATUS_0_Overflow_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define APS_AST_ERROR_STATUS_0_VMIndxErr_SHIFT                  MK_SHIFT_CONST(1)
+#define APS_AST_ERROR_STATUS_0_VMIndxErr_FIELD                  MK_FIELD_CONST(0x1, APS_AST_ERROR_STATUS_0_VMIndxErr_SHIFT)
+#define APS_AST_ERROR_STATUS_0_VMIndxErr_RANGE                  1:1
+#define APS_AST_ERROR_STATUS_0_VMIndxErr_MSB                    MK_SHIFT_CONST(1)
+#define APS_AST_ERROR_STATUS_0_VMIndxErr_LSB                    MK_SHIFT_CONST(1)
+#define APS_AST_ERROR_STATUS_0_VMIndxErr_WOFFSET                        0x0
+#define APS_AST_ERROR_STATUS_0_VMIndxErr_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_STATUS_0_VMIndxErr_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define APS_AST_ERROR_STATUS_0_VMIndxErr_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_STATUS_0_VMIndxErr_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_STATUS_0_VMIndxErr_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_STATUS_0_VMIndxErr_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define APS_AST_ERROR_STATUS_0_Valid_SHIFT                      MK_SHIFT_CONST(0)
+#define APS_AST_ERROR_STATUS_0_Valid_FIELD                      MK_FIELD_CONST(0x1, APS_AST_ERROR_STATUS_0_Valid_SHIFT)
+#define APS_AST_ERROR_STATUS_0_Valid_RANGE                      0:0
+#define APS_AST_ERROR_STATUS_0_Valid_MSB                        MK_SHIFT_CONST(0)
+#define APS_AST_ERROR_STATUS_0_Valid_LSB                        MK_SHIFT_CONST(0)
+#define APS_AST_ERROR_STATUS_0_Valid_WOFFSET                    0x0
+#define APS_AST_ERROR_STATUS_0_Valid_DEFAULT                    MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_STATUS_0_Valid_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define APS_AST_ERROR_STATUS_0_Valid_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_STATUS_0_Valid_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_STATUS_0_Valid_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_STATUS_0_Valid_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_ERROR_ADDR_LO_0
+#define APS_AST_ERROR_ADDR_LO_0                 MK_ADDR_CONST(0x8)
+#define APS_AST_ERROR_ADDR_LO_0_SECURE                  0x0
+#define APS_AST_ERROR_ADDR_LO_0_DUAL                    0x0
+#define APS_AST_ERROR_ADDR_LO_0_SCR                     AST_GBL_SEC_CONTROL_0
+#define APS_AST_ERROR_ADDR_LO_0_SCRREG                  APS_AST_SCR_AST_GBL_SEC_CONTROL_0
+#define APS_AST_ERROR_ADDR_LO_0_WORD_COUNT                      0x1
+#define APS_AST_ERROR_ADDR_LO_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_ADDR_LO_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_AST_ERROR_ADDR_LO_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_ADDR_LO_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_ADDR_LO_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_AST_ERROR_ADDR_LO_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_SHIFT                 MK_SHIFT_CONST(0)
+#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_FIELD                 MK_FIELD_CONST(0xffffffff, APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_SHIFT)
+#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_RANGE                 31:0
+#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_MSB                   MK_SHIFT_CONST(31)
+#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_LSB                   MK_SHIFT_CONST(0)
+#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_WOFFSET                       0x0
+#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_DEFAULT                       MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_ADDR_LO_0_ErrAddrLo_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_ERROR_ADDR_HI_0
+#define APS_AST_ERROR_ADDR_HI_0                 MK_ADDR_CONST(0xc)
+#define APS_AST_ERROR_ADDR_HI_0_SECURE                  0x0
+#define APS_AST_ERROR_ADDR_HI_0_DUAL                    0x0
+#define APS_AST_ERROR_ADDR_HI_0_SCR                     AST_GBL_SEC_CONTROL_0
+#define APS_AST_ERROR_ADDR_HI_0_SCRREG                  APS_AST_SCR_AST_GBL_SEC_CONTROL_0
+#define APS_AST_ERROR_ADDR_HI_0_WORD_COUNT                      0x1
+#define APS_AST_ERROR_ADDR_HI_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_ADDR_HI_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_AST_ERROR_ADDR_HI_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_ADDR_HI_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_ADDR_HI_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_AST_ERROR_ADDR_HI_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_SHIFT                 MK_SHIFT_CONST(0)
+#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_FIELD                 MK_FIELD_CONST(0xffffffff, APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_SHIFT)
+#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_RANGE                 31:0
+#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_MSB                   MK_SHIFT_CONST(31)
+#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_LSB                   MK_SHIFT_CONST(0)
+#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_WOFFSET                       0x0
+#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_DEFAULT                       MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define APS_AST_ERROR_ADDR_HI_0_ErrAddrHi_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_STREAMID_CTL_0
+#define APS_AST_STREAMID_CTL_0                  MK_ADDR_CONST(0x20)
+#define APS_AST_STREAMID_CTL_0_SECURE                   0x0
+#define APS_AST_STREAMID_CTL_0_DUAL                     0x0
+#define APS_AST_STREAMID_CTL_0_SCR                      AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_0_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_0_WORD_COUNT                       0x1
+#define APS_AST_STREAMID_CTL_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_0_RESET_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_0_READ_MASK                        MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_0_WRITE_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_0_StreamID_SHIFT                   MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_0_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_0_StreamID_SHIFT)
+#define APS_AST_STREAMID_CTL_0_StreamID_RANGE                   15:8
+#define APS_AST_STREAMID_CTL_0_StreamID_MSB                     MK_SHIFT_CONST(15)
+#define APS_AST_STREAMID_CTL_0_StreamID_LSB                     MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_0_StreamID_WOFFSET                 0x0
+#define APS_AST_STREAMID_CTL_0_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_0_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define APS_AST_STREAMID_CTL_0_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_0_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_0_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_0_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define APS_AST_STREAMID_CTL_0_Enable_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_0_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_0_Enable_SHIFT)
+#define APS_AST_STREAMID_CTL_0_Enable_RANGE                     0:0
+#define APS_AST_STREAMID_CTL_0_Enable_MSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_0_Enable_LSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_0_Enable_WOFFSET                   0x0
+#define APS_AST_STREAMID_CTL_0_Enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_0_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_0_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_0_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_0_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_0_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_0_Enable_DISABLE                   MK_ENUM_CONST(0)
+#define APS_AST_STREAMID_CTL_0_Enable_ENABLE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_STREAMID_CTL
+#define APS_AST_STREAMID_CTL                    MK_ADDR_CONST(0x20)
+#define APS_AST_STREAMID_CTL_SECURE                     0x0
+#define APS_AST_STREAMID_CTL_DUAL                       0x0
+#define APS_AST_STREAMID_CTL_SCR                        AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_SCRREG                     APS_AST_SCR_AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_WORD_COUNT                         0x1
+#define APS_AST_STREAMID_CTL_RESET_VAL                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_RESET_MASK                         MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_READ_MASK                  MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_WRITE_MASK                         MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_StreamID_SHIFT                     MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_StreamID_FIELD                     MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_StreamID_SHIFT)
+#define APS_AST_STREAMID_CTL_StreamID_RANGE                     15:8
+#define APS_AST_STREAMID_CTL_StreamID_MSB                       MK_SHIFT_CONST(15)
+#define APS_AST_STREAMID_CTL_StreamID_LSB                       MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_StreamID_WOFFSET                   0x0
+#define APS_AST_STREAMID_CTL_StreamID_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_StreamID_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define APS_AST_STREAMID_CTL_StreamID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_StreamID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_StreamID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_StreamID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define APS_AST_STREAMID_CTL_Enable_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_Enable_FIELD                       MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_Enable_SHIFT)
+#define APS_AST_STREAMID_CTL_Enable_RANGE                       0:0
+#define APS_AST_STREAMID_CTL_Enable_MSB                 MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_Enable_LSB                 MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_Enable_WOFFSET                     0x0
+#define APS_AST_STREAMID_CTL_Enable_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_Enable_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_Enable_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_Enable_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_Enable_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_Enable_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_Enable_DISABLE                     MK_ENUM_CONST(0)
+#define APS_AST_STREAMID_CTL_Enable_ENABLE                      MK_ENUM_CONST(1)
+
+
+// Register APS_AST_STREAMID_CTL_1
+#define APS_AST_STREAMID_CTL_1                  MK_ADDR_CONST(0x24)
+#define APS_AST_STREAMID_CTL_1_SECURE                   0x0
+#define APS_AST_STREAMID_CTL_1_DUAL                     0x0
+#define APS_AST_STREAMID_CTL_1_SCR                      AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_1_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_1_WORD_COUNT                       0x1
+#define APS_AST_STREAMID_CTL_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_1_RESET_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_1_READ_MASK                        MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_1_WRITE_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_1_StreamID_SHIFT                   MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_1_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_1_StreamID_SHIFT)
+#define APS_AST_STREAMID_CTL_1_StreamID_RANGE                   15:8
+#define APS_AST_STREAMID_CTL_1_StreamID_MSB                     MK_SHIFT_CONST(15)
+#define APS_AST_STREAMID_CTL_1_StreamID_LSB                     MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_1_StreamID_WOFFSET                 0x0
+#define APS_AST_STREAMID_CTL_1_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_1_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define APS_AST_STREAMID_CTL_1_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_1_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_1_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_1_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define APS_AST_STREAMID_CTL_1_Enable_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_1_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_1_Enable_SHIFT)
+#define APS_AST_STREAMID_CTL_1_Enable_RANGE                     0:0
+#define APS_AST_STREAMID_CTL_1_Enable_MSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_1_Enable_LSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_1_Enable_WOFFSET                   0x0
+#define APS_AST_STREAMID_CTL_1_Enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_1_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_1_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_1_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_1_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_1_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_1_Enable_DISABLE                   MK_ENUM_CONST(0)
+#define APS_AST_STREAMID_CTL_1_Enable_ENABLE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_STREAMID_CTL_2
+#define APS_AST_STREAMID_CTL_2                  MK_ADDR_CONST(0x28)
+#define APS_AST_STREAMID_CTL_2_SECURE                   0x0
+#define APS_AST_STREAMID_CTL_2_DUAL                     0x0
+#define APS_AST_STREAMID_CTL_2_SCR                      AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_2_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_2_WORD_COUNT                       0x1
+#define APS_AST_STREAMID_CTL_2_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_2_RESET_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_2_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_2_READ_MASK                        MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_2_WRITE_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_2_StreamID_SHIFT                   MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_2_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_2_StreamID_SHIFT)
+#define APS_AST_STREAMID_CTL_2_StreamID_RANGE                   15:8
+#define APS_AST_STREAMID_CTL_2_StreamID_MSB                     MK_SHIFT_CONST(15)
+#define APS_AST_STREAMID_CTL_2_StreamID_LSB                     MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_2_StreamID_WOFFSET                 0x0
+#define APS_AST_STREAMID_CTL_2_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_2_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define APS_AST_STREAMID_CTL_2_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_2_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_2_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_2_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define APS_AST_STREAMID_CTL_2_Enable_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_2_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_2_Enable_SHIFT)
+#define APS_AST_STREAMID_CTL_2_Enable_RANGE                     0:0
+#define APS_AST_STREAMID_CTL_2_Enable_MSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_2_Enable_LSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_2_Enable_WOFFSET                   0x0
+#define APS_AST_STREAMID_CTL_2_Enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_2_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_2_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_2_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_2_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_2_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_2_Enable_DISABLE                   MK_ENUM_CONST(0)
+#define APS_AST_STREAMID_CTL_2_Enable_ENABLE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_STREAMID_CTL_3
+#define APS_AST_STREAMID_CTL_3                  MK_ADDR_CONST(0x2c)
+#define APS_AST_STREAMID_CTL_3_SECURE                   0x0
+#define APS_AST_STREAMID_CTL_3_DUAL                     0x0
+#define APS_AST_STREAMID_CTL_3_SCR                      AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_3_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_3_WORD_COUNT                       0x1
+#define APS_AST_STREAMID_CTL_3_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_3_RESET_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_3_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_3_READ_MASK                        MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_3_WRITE_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_3_StreamID_SHIFT                   MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_3_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_3_StreamID_SHIFT)
+#define APS_AST_STREAMID_CTL_3_StreamID_RANGE                   15:8
+#define APS_AST_STREAMID_CTL_3_StreamID_MSB                     MK_SHIFT_CONST(15)
+#define APS_AST_STREAMID_CTL_3_StreamID_LSB                     MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_3_StreamID_WOFFSET                 0x0
+#define APS_AST_STREAMID_CTL_3_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_3_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define APS_AST_STREAMID_CTL_3_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_3_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_3_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_3_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define APS_AST_STREAMID_CTL_3_Enable_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_3_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_3_Enable_SHIFT)
+#define APS_AST_STREAMID_CTL_3_Enable_RANGE                     0:0
+#define APS_AST_STREAMID_CTL_3_Enable_MSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_3_Enable_LSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_3_Enable_WOFFSET                   0x0
+#define APS_AST_STREAMID_CTL_3_Enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_3_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_3_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_3_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_3_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_3_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_3_Enable_DISABLE                   MK_ENUM_CONST(0)
+#define APS_AST_STREAMID_CTL_3_Enable_ENABLE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_STREAMID_CTL_4
+#define APS_AST_STREAMID_CTL_4                  MK_ADDR_CONST(0x30)
+#define APS_AST_STREAMID_CTL_4_SECURE                   0x0
+#define APS_AST_STREAMID_CTL_4_DUAL                     0x0
+#define APS_AST_STREAMID_CTL_4_SCR                      AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_4_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_4_WORD_COUNT                       0x1
+#define APS_AST_STREAMID_CTL_4_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_4_RESET_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_4_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_4_READ_MASK                        MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_4_WRITE_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_4_StreamID_SHIFT                   MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_4_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_4_StreamID_SHIFT)
+#define APS_AST_STREAMID_CTL_4_StreamID_RANGE                   15:8
+#define APS_AST_STREAMID_CTL_4_StreamID_MSB                     MK_SHIFT_CONST(15)
+#define APS_AST_STREAMID_CTL_4_StreamID_LSB                     MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_4_StreamID_WOFFSET                 0x0
+#define APS_AST_STREAMID_CTL_4_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_4_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define APS_AST_STREAMID_CTL_4_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_4_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_4_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_4_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define APS_AST_STREAMID_CTL_4_Enable_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_4_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_4_Enable_SHIFT)
+#define APS_AST_STREAMID_CTL_4_Enable_RANGE                     0:0
+#define APS_AST_STREAMID_CTL_4_Enable_MSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_4_Enable_LSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_4_Enable_WOFFSET                   0x0
+#define APS_AST_STREAMID_CTL_4_Enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_4_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_4_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_4_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_4_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_4_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_4_Enable_DISABLE                   MK_ENUM_CONST(0)
+#define APS_AST_STREAMID_CTL_4_Enable_ENABLE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_STREAMID_CTL_5
+#define APS_AST_STREAMID_CTL_5                  MK_ADDR_CONST(0x34)
+#define APS_AST_STREAMID_CTL_5_SECURE                   0x0
+#define APS_AST_STREAMID_CTL_5_DUAL                     0x0
+#define APS_AST_STREAMID_CTL_5_SCR                      AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_5_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_5_WORD_COUNT                       0x1
+#define APS_AST_STREAMID_CTL_5_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_5_RESET_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_5_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_5_READ_MASK                        MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_5_WRITE_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_5_StreamID_SHIFT                   MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_5_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_5_StreamID_SHIFT)
+#define APS_AST_STREAMID_CTL_5_StreamID_RANGE                   15:8
+#define APS_AST_STREAMID_CTL_5_StreamID_MSB                     MK_SHIFT_CONST(15)
+#define APS_AST_STREAMID_CTL_5_StreamID_LSB                     MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_5_StreamID_WOFFSET                 0x0
+#define APS_AST_STREAMID_CTL_5_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_5_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define APS_AST_STREAMID_CTL_5_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_5_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_5_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_5_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define APS_AST_STREAMID_CTL_5_Enable_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_5_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_5_Enable_SHIFT)
+#define APS_AST_STREAMID_CTL_5_Enable_RANGE                     0:0
+#define APS_AST_STREAMID_CTL_5_Enable_MSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_5_Enable_LSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_5_Enable_WOFFSET                   0x0
+#define APS_AST_STREAMID_CTL_5_Enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_5_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_5_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_5_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_5_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_5_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_5_Enable_DISABLE                   MK_ENUM_CONST(0)
+#define APS_AST_STREAMID_CTL_5_Enable_ENABLE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_STREAMID_CTL_6
+#define APS_AST_STREAMID_CTL_6                  MK_ADDR_CONST(0x38)
+#define APS_AST_STREAMID_CTL_6_SECURE                   0x0
+#define APS_AST_STREAMID_CTL_6_DUAL                     0x0
+#define APS_AST_STREAMID_CTL_6_SCR                      AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_6_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_6_WORD_COUNT                       0x1
+#define APS_AST_STREAMID_CTL_6_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_6_RESET_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_6_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_6_READ_MASK                        MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_6_WRITE_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_6_StreamID_SHIFT                   MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_6_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_6_StreamID_SHIFT)
+#define APS_AST_STREAMID_CTL_6_StreamID_RANGE                   15:8
+#define APS_AST_STREAMID_CTL_6_StreamID_MSB                     MK_SHIFT_CONST(15)
+#define APS_AST_STREAMID_CTL_6_StreamID_LSB                     MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_6_StreamID_WOFFSET                 0x0
+#define APS_AST_STREAMID_CTL_6_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_6_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define APS_AST_STREAMID_CTL_6_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_6_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_6_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_6_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define APS_AST_STREAMID_CTL_6_Enable_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_6_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_6_Enable_SHIFT)
+#define APS_AST_STREAMID_CTL_6_Enable_RANGE                     0:0
+#define APS_AST_STREAMID_CTL_6_Enable_MSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_6_Enable_LSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_6_Enable_WOFFSET                   0x0
+#define APS_AST_STREAMID_CTL_6_Enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_6_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_6_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_6_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_6_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_6_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_6_Enable_DISABLE                   MK_ENUM_CONST(0)
+#define APS_AST_STREAMID_CTL_6_Enable_ENABLE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_STREAMID_CTL_7
+#define APS_AST_STREAMID_CTL_7                  MK_ADDR_CONST(0x3c)
+#define APS_AST_STREAMID_CTL_7_SECURE                   0x0
+#define APS_AST_STREAMID_CTL_7_DUAL                     0x0
+#define APS_AST_STREAMID_CTL_7_SCR                      AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_7_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_7_WORD_COUNT                       0x1
+#define APS_AST_STREAMID_CTL_7_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_7_RESET_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_7_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_7_READ_MASK                        MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_7_WRITE_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_7_StreamID_SHIFT                   MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_7_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_7_StreamID_SHIFT)
+#define APS_AST_STREAMID_CTL_7_StreamID_RANGE                   15:8
+#define APS_AST_STREAMID_CTL_7_StreamID_MSB                     MK_SHIFT_CONST(15)
+#define APS_AST_STREAMID_CTL_7_StreamID_LSB                     MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_7_StreamID_WOFFSET                 0x0
+#define APS_AST_STREAMID_CTL_7_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_7_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define APS_AST_STREAMID_CTL_7_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_7_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_7_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_7_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define APS_AST_STREAMID_CTL_7_Enable_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_7_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_7_Enable_SHIFT)
+#define APS_AST_STREAMID_CTL_7_Enable_RANGE                     0:0
+#define APS_AST_STREAMID_CTL_7_Enable_MSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_7_Enable_LSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_7_Enable_WOFFSET                   0x0
+#define APS_AST_STREAMID_CTL_7_Enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_7_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_7_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_7_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_7_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_7_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_7_Enable_DISABLE                   MK_ENUM_CONST(0)
+#define APS_AST_STREAMID_CTL_7_Enable_ENABLE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_STREAMID_CTL_8
+#define APS_AST_STREAMID_CTL_8                  MK_ADDR_CONST(0x40)
+#define APS_AST_STREAMID_CTL_8_SECURE                   0x0
+#define APS_AST_STREAMID_CTL_8_DUAL                     0x0
+#define APS_AST_STREAMID_CTL_8_SCR                      AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_8_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_8_WORD_COUNT                       0x1
+#define APS_AST_STREAMID_CTL_8_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_8_RESET_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_8_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_8_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_8_READ_MASK                        MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_8_WRITE_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_8_StreamID_SHIFT                   MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_8_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_8_StreamID_SHIFT)
+#define APS_AST_STREAMID_CTL_8_StreamID_RANGE                   15:8
+#define APS_AST_STREAMID_CTL_8_StreamID_MSB                     MK_SHIFT_CONST(15)
+#define APS_AST_STREAMID_CTL_8_StreamID_LSB                     MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_8_StreamID_WOFFSET                 0x0
+#define APS_AST_STREAMID_CTL_8_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_8_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define APS_AST_STREAMID_CTL_8_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_8_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_8_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_8_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define APS_AST_STREAMID_CTL_8_Enable_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_8_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_8_Enable_SHIFT)
+#define APS_AST_STREAMID_CTL_8_Enable_RANGE                     0:0
+#define APS_AST_STREAMID_CTL_8_Enable_MSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_8_Enable_LSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_8_Enable_WOFFSET                   0x0
+#define APS_AST_STREAMID_CTL_8_Enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_8_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_8_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_8_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_8_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_8_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_8_Enable_DISABLE                   MK_ENUM_CONST(0)
+#define APS_AST_STREAMID_CTL_8_Enable_ENABLE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_STREAMID_CTL_9
+#define APS_AST_STREAMID_CTL_9                  MK_ADDR_CONST(0x44)
+#define APS_AST_STREAMID_CTL_9_SECURE                   0x0
+#define APS_AST_STREAMID_CTL_9_DUAL                     0x0
+#define APS_AST_STREAMID_CTL_9_SCR                      AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_9_SCRREG                   APS_AST_SCR_AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_9_WORD_COUNT                       0x1
+#define APS_AST_STREAMID_CTL_9_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_9_RESET_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_9_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_9_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_9_READ_MASK                        MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_9_WRITE_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_9_StreamID_SHIFT                   MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_9_StreamID_FIELD                   MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_9_StreamID_SHIFT)
+#define APS_AST_STREAMID_CTL_9_StreamID_RANGE                   15:8
+#define APS_AST_STREAMID_CTL_9_StreamID_MSB                     MK_SHIFT_CONST(15)
+#define APS_AST_STREAMID_CTL_9_StreamID_LSB                     MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_9_StreamID_WOFFSET                 0x0
+#define APS_AST_STREAMID_CTL_9_StreamID_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_9_StreamID_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define APS_AST_STREAMID_CTL_9_StreamID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_9_StreamID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_9_StreamID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_9_StreamID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define APS_AST_STREAMID_CTL_9_Enable_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_9_Enable_FIELD                     MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_9_Enable_SHIFT)
+#define APS_AST_STREAMID_CTL_9_Enable_RANGE                     0:0
+#define APS_AST_STREAMID_CTL_9_Enable_MSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_9_Enable_LSB                       MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_9_Enable_WOFFSET                   0x0
+#define APS_AST_STREAMID_CTL_9_Enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_9_Enable_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_9_Enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_9_Enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_9_Enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_9_Enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_9_Enable_DISABLE                   MK_ENUM_CONST(0)
+#define APS_AST_STREAMID_CTL_9_Enable_ENABLE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_STREAMID_CTL_10
+#define APS_AST_STREAMID_CTL_10                 MK_ADDR_CONST(0x48)
+#define APS_AST_STREAMID_CTL_10_SECURE                  0x0
+#define APS_AST_STREAMID_CTL_10_DUAL                    0x0
+#define APS_AST_STREAMID_CTL_10_SCR                     AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_10_SCRREG                  APS_AST_SCR_AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_10_WORD_COUNT                      0x1
+#define APS_AST_STREAMID_CTL_10_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_10_RESET_MASK                      MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_10_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_10_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_10_READ_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_10_WRITE_MASK                      MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_10_StreamID_SHIFT                  MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_10_StreamID_FIELD                  MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_10_StreamID_SHIFT)
+#define APS_AST_STREAMID_CTL_10_StreamID_RANGE                  15:8
+#define APS_AST_STREAMID_CTL_10_StreamID_MSB                    MK_SHIFT_CONST(15)
+#define APS_AST_STREAMID_CTL_10_StreamID_LSB                    MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_10_StreamID_WOFFSET                        0x0
+#define APS_AST_STREAMID_CTL_10_StreamID_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_10_StreamID_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define APS_AST_STREAMID_CTL_10_StreamID_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_10_StreamID_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_10_StreamID_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_10_StreamID_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define APS_AST_STREAMID_CTL_10_Enable_SHIFT                    MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_10_Enable_FIELD                    MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_10_Enable_SHIFT)
+#define APS_AST_STREAMID_CTL_10_Enable_RANGE                    0:0
+#define APS_AST_STREAMID_CTL_10_Enable_MSB                      MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_10_Enable_LSB                      MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_10_Enable_WOFFSET                  0x0
+#define APS_AST_STREAMID_CTL_10_Enable_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_10_Enable_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_10_Enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_10_Enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_10_Enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_10_Enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_10_Enable_DISABLE                  MK_ENUM_CONST(0)
+#define APS_AST_STREAMID_CTL_10_Enable_ENABLE                   MK_ENUM_CONST(1)
+
+
+// Register APS_AST_STREAMID_CTL_11
+#define APS_AST_STREAMID_CTL_11                 MK_ADDR_CONST(0x4c)
+#define APS_AST_STREAMID_CTL_11_SECURE                  0x0
+#define APS_AST_STREAMID_CTL_11_DUAL                    0x0
+#define APS_AST_STREAMID_CTL_11_SCR                     AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_11_SCRREG                  APS_AST_SCR_AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_11_WORD_COUNT                      0x1
+#define APS_AST_STREAMID_CTL_11_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_11_RESET_MASK                      MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_11_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_11_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_11_READ_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_11_WRITE_MASK                      MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_11_StreamID_SHIFT                  MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_11_StreamID_FIELD                  MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_11_StreamID_SHIFT)
+#define APS_AST_STREAMID_CTL_11_StreamID_RANGE                  15:8
+#define APS_AST_STREAMID_CTL_11_StreamID_MSB                    MK_SHIFT_CONST(15)
+#define APS_AST_STREAMID_CTL_11_StreamID_LSB                    MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_11_StreamID_WOFFSET                        0x0
+#define APS_AST_STREAMID_CTL_11_StreamID_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_11_StreamID_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define APS_AST_STREAMID_CTL_11_StreamID_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_11_StreamID_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_11_StreamID_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_11_StreamID_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define APS_AST_STREAMID_CTL_11_Enable_SHIFT                    MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_11_Enable_FIELD                    MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_11_Enable_SHIFT)
+#define APS_AST_STREAMID_CTL_11_Enable_RANGE                    0:0
+#define APS_AST_STREAMID_CTL_11_Enable_MSB                      MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_11_Enable_LSB                      MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_11_Enable_WOFFSET                  0x0
+#define APS_AST_STREAMID_CTL_11_Enable_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_11_Enable_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_11_Enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_11_Enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_11_Enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_11_Enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_11_Enable_DISABLE                  MK_ENUM_CONST(0)
+#define APS_AST_STREAMID_CTL_11_Enable_ENABLE                   MK_ENUM_CONST(1)
+
+
+// Register APS_AST_STREAMID_CTL_12
+#define APS_AST_STREAMID_CTL_12                 MK_ADDR_CONST(0x50)
+#define APS_AST_STREAMID_CTL_12_SECURE                  0x0
+#define APS_AST_STREAMID_CTL_12_DUAL                    0x0
+#define APS_AST_STREAMID_CTL_12_SCR                     AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_12_SCRREG                  APS_AST_SCR_AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_12_WORD_COUNT                      0x1
+#define APS_AST_STREAMID_CTL_12_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_12_RESET_MASK                      MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_12_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_12_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_12_READ_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_12_WRITE_MASK                      MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_12_StreamID_SHIFT                  MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_12_StreamID_FIELD                  MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_12_StreamID_SHIFT)
+#define APS_AST_STREAMID_CTL_12_StreamID_RANGE                  15:8
+#define APS_AST_STREAMID_CTL_12_StreamID_MSB                    MK_SHIFT_CONST(15)
+#define APS_AST_STREAMID_CTL_12_StreamID_LSB                    MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_12_StreamID_WOFFSET                        0x0
+#define APS_AST_STREAMID_CTL_12_StreamID_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_12_StreamID_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define APS_AST_STREAMID_CTL_12_StreamID_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_12_StreamID_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_12_StreamID_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_12_StreamID_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define APS_AST_STREAMID_CTL_12_Enable_SHIFT                    MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_12_Enable_FIELD                    MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_12_Enable_SHIFT)
+#define APS_AST_STREAMID_CTL_12_Enable_RANGE                    0:0
+#define APS_AST_STREAMID_CTL_12_Enable_MSB                      MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_12_Enable_LSB                      MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_12_Enable_WOFFSET                  0x0
+#define APS_AST_STREAMID_CTL_12_Enable_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_12_Enable_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_12_Enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_12_Enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_12_Enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_12_Enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_12_Enable_DISABLE                  MK_ENUM_CONST(0)
+#define APS_AST_STREAMID_CTL_12_Enable_ENABLE                   MK_ENUM_CONST(1)
+
+
+// Register APS_AST_STREAMID_CTL_13
+#define APS_AST_STREAMID_CTL_13                 MK_ADDR_CONST(0x54)
+#define APS_AST_STREAMID_CTL_13_SECURE                  0x0
+#define APS_AST_STREAMID_CTL_13_DUAL                    0x0
+#define APS_AST_STREAMID_CTL_13_SCR                     AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_13_SCRREG                  APS_AST_SCR_AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_13_WORD_COUNT                      0x1
+#define APS_AST_STREAMID_CTL_13_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_13_RESET_MASK                      MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_13_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_13_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_13_READ_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_13_WRITE_MASK                      MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_13_StreamID_SHIFT                  MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_13_StreamID_FIELD                  MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_13_StreamID_SHIFT)
+#define APS_AST_STREAMID_CTL_13_StreamID_RANGE                  15:8
+#define APS_AST_STREAMID_CTL_13_StreamID_MSB                    MK_SHIFT_CONST(15)
+#define APS_AST_STREAMID_CTL_13_StreamID_LSB                    MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_13_StreamID_WOFFSET                        0x0
+#define APS_AST_STREAMID_CTL_13_StreamID_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_13_StreamID_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define APS_AST_STREAMID_CTL_13_StreamID_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_13_StreamID_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_13_StreamID_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_13_StreamID_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define APS_AST_STREAMID_CTL_13_Enable_SHIFT                    MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_13_Enable_FIELD                    MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_13_Enable_SHIFT)
+#define APS_AST_STREAMID_CTL_13_Enable_RANGE                    0:0
+#define APS_AST_STREAMID_CTL_13_Enable_MSB                      MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_13_Enable_LSB                      MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_13_Enable_WOFFSET                  0x0
+#define APS_AST_STREAMID_CTL_13_Enable_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_13_Enable_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_13_Enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_13_Enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_13_Enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_13_Enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_13_Enable_DISABLE                  MK_ENUM_CONST(0)
+#define APS_AST_STREAMID_CTL_13_Enable_ENABLE                   MK_ENUM_CONST(1)
+
+
+// Register APS_AST_STREAMID_CTL_14
+#define APS_AST_STREAMID_CTL_14                 MK_ADDR_CONST(0x58)
+#define APS_AST_STREAMID_CTL_14_SECURE                  0x0
+#define APS_AST_STREAMID_CTL_14_DUAL                    0x0
+#define APS_AST_STREAMID_CTL_14_SCR                     AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_14_SCRREG                  APS_AST_SCR_AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_14_WORD_COUNT                      0x1
+#define APS_AST_STREAMID_CTL_14_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_14_RESET_MASK                      MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_14_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_14_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_14_READ_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_14_WRITE_MASK                      MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_14_StreamID_SHIFT                  MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_14_StreamID_FIELD                  MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_14_StreamID_SHIFT)
+#define APS_AST_STREAMID_CTL_14_StreamID_RANGE                  15:8
+#define APS_AST_STREAMID_CTL_14_StreamID_MSB                    MK_SHIFT_CONST(15)
+#define APS_AST_STREAMID_CTL_14_StreamID_LSB                    MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_14_StreamID_WOFFSET                        0x0
+#define APS_AST_STREAMID_CTL_14_StreamID_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_14_StreamID_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define APS_AST_STREAMID_CTL_14_StreamID_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_14_StreamID_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_14_StreamID_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_14_StreamID_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define APS_AST_STREAMID_CTL_14_Enable_SHIFT                    MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_14_Enable_FIELD                    MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_14_Enable_SHIFT)
+#define APS_AST_STREAMID_CTL_14_Enable_RANGE                    0:0
+#define APS_AST_STREAMID_CTL_14_Enable_MSB                      MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_14_Enable_LSB                      MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_14_Enable_WOFFSET                  0x0
+#define APS_AST_STREAMID_CTL_14_Enable_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_14_Enable_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_14_Enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_14_Enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_14_Enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_14_Enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_14_Enable_DISABLE                  MK_ENUM_CONST(0)
+#define APS_AST_STREAMID_CTL_14_Enable_ENABLE                   MK_ENUM_CONST(1)
+
+
+// Register APS_AST_STREAMID_CTL_15
+#define APS_AST_STREAMID_CTL_15                 MK_ADDR_CONST(0x5c)
+#define APS_AST_STREAMID_CTL_15_SECURE                  0x0
+#define APS_AST_STREAMID_CTL_15_DUAL                    0x0
+#define APS_AST_STREAMID_CTL_15_SCR                     AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_15_SCRREG                  APS_AST_SCR_AST_HYP_SEC_CONTROL_0
+#define APS_AST_STREAMID_CTL_15_WORD_COUNT                      0x1
+#define APS_AST_STREAMID_CTL_15_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_15_RESET_MASK                      MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_15_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_15_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_15_READ_MASK                       MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_15_WRITE_MASK                      MK_MASK_CONST(0xff01)
+#define APS_AST_STREAMID_CTL_15_StreamID_SHIFT                  MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_15_StreamID_FIELD                  MK_FIELD_CONST(0xff, APS_AST_STREAMID_CTL_15_StreamID_SHIFT)
+#define APS_AST_STREAMID_CTL_15_StreamID_RANGE                  15:8
+#define APS_AST_STREAMID_CTL_15_StreamID_MSB                    MK_SHIFT_CONST(15)
+#define APS_AST_STREAMID_CTL_15_StreamID_LSB                    MK_SHIFT_CONST(8)
+#define APS_AST_STREAMID_CTL_15_StreamID_WOFFSET                        0x0
+#define APS_AST_STREAMID_CTL_15_StreamID_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_15_StreamID_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define APS_AST_STREAMID_CTL_15_StreamID_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_15_StreamID_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_15_StreamID_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_15_StreamID_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define APS_AST_STREAMID_CTL_15_Enable_SHIFT                    MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_15_Enable_FIELD                    MK_FIELD_CONST(0x1, APS_AST_STREAMID_CTL_15_Enable_SHIFT)
+#define APS_AST_STREAMID_CTL_15_Enable_RANGE                    0:0
+#define APS_AST_STREAMID_CTL_15_Enable_MSB                      MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_15_Enable_LSB                      MK_SHIFT_CONST(0)
+#define APS_AST_STREAMID_CTL_15_Enable_WOFFSET                  0x0
+#define APS_AST_STREAMID_CTL_15_Enable_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_15_Enable_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_15_Enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_15_Enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_15_Enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define APS_AST_STREAMID_CTL_15_Enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define APS_AST_STREAMID_CTL_15_Enable_DISABLE                  MK_ENUM_CONST(0)
+#define APS_AST_STREAMID_CTL_15_Enable_ENABLE                   MK_ENUM_CONST(1)
+
+
+// Register APS_AST_WRITE_BLOCK_STATUS_0
+#define APS_AST_WRITE_BLOCK_STATUS_0                    MK_ADDR_CONST(0x60)
+#define APS_AST_WRITE_BLOCK_STATUS_0_SECURE                     0x0
+#define APS_AST_WRITE_BLOCK_STATUS_0_DUAL                       0x0
+#define APS_AST_WRITE_BLOCK_STATUS_0_SCR                        AST_GBL_SEC_CONTROL_0
+#define APS_AST_WRITE_BLOCK_STATUS_0_SCRREG                     APS_AST_SCR_AST_GBL_SEC_CONTROL_0
+#define APS_AST_WRITE_BLOCK_STATUS_0_WORD_COUNT                         0x1
+#define APS_AST_WRITE_BLOCK_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define APS_AST_WRITE_BLOCK_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define APS_AST_WRITE_BLOCK_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_WRITE_BLOCK_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define APS_AST_WRITE_BLOCK_STATUS_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_SHIFT)
+#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_RANGE                   31:0
+#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_MSB                     MK_SHIFT_CONST(31)
+#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_WOFFSET                 0x0
+#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_WRITE_BLOCK_STATUS_0_WRITE_BLOCK_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_READ_BLOCK_STATUS_0
+#define APS_AST_READ_BLOCK_STATUS_0                     MK_ADDR_CONST(0x64)
+#define APS_AST_READ_BLOCK_STATUS_0_SECURE                      0x0
+#define APS_AST_READ_BLOCK_STATUS_0_DUAL                        0x0
+#define APS_AST_READ_BLOCK_STATUS_0_SCR                         AST_GBL_SEC_CONTROL_0
+#define APS_AST_READ_BLOCK_STATUS_0_SCRREG                      APS_AST_SCR_AST_GBL_SEC_CONTROL_0
+#define APS_AST_READ_BLOCK_STATUS_0_WORD_COUNT                  0x1
+#define APS_AST_READ_BLOCK_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define APS_AST_READ_BLOCK_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_READ_BLOCK_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_AST_READ_BLOCK_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_AST_READ_BLOCK_STATUS_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_READ_BLOCK_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_FIELD                     MK_FIELD_CONST(0xffffffff, APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_SHIFT)
+#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_RANGE                     31:0
+#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_MSB                       MK_SHIFT_CONST(31)
+#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_LSB                       MK_SHIFT_CONST(0)
+#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_WOFFSET                   0x0
+#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_READ_BLOCK_STATUS_0_READ_BLOCK_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_0_SLAVE_BASE_LO_0
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0                        MK_ADDR_CONST(0x100)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SECURE                         0x0
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_DUAL                   0x0
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SCR                    AST_REG_0_SEC_CONTROL_0
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SCRREG                         APS_AST_SCR_AST_REG_0_SEC_CONTROL_0
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_WORD_COUNT                     0x1
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_RESET_MASK                     MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_READ_MASK                      MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_WRITE_MASK                     MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_SHIFT                  MK_SHIFT_CONST(12)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_FIELD                  MK_FIELD_CONST(0xfffff, APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_SHIFT)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_RANGE                  31:12
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_LSB                    MK_SHIFT_CONST(12)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_WOFFSET                        0x0
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_SHIFT)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_RANGE                   0:0
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_MSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_WOFFSET                 0x0
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_FALSE                   MK_ENUM_CONST(0)
+#define APS_AST_REGION_0_SLAVE_BASE_LO_0_Enable_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_REGION_0_SLAVE_BASE_HI_0
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0                        MK_ADDR_CONST(0x104)
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SECURE                         0x0
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_DUAL                   0x0
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SCR                    AST_REG_0_SEC_CONTROL_0
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SCRREG                         APS_AST_SCR_AST_REG_0_SEC_CONTROL_0
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_WORD_COUNT                     0x1
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_SHIFT                  MK_SHIFT_CONST(0)
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_FIELD                  MK_FIELD_CONST(0xffffffff, APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_SHIFT)
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_RANGE                  31:0
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_LSB                    MK_SHIFT_CONST(0)
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_WOFFSET                        0x0
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_SLAVE_BASE_HI_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_0_MASK_LO_0
+#define APS_AST_REGION_0_MASK_LO_0                      MK_ADDR_CONST(0x108)
+#define APS_AST_REGION_0_MASK_LO_0_SECURE                       0x0
+#define APS_AST_REGION_0_MASK_LO_0_DUAL                         0x0
+#define APS_AST_REGION_0_MASK_LO_0_SCR                  AST_REG_0_SEC_CONTROL_0
+#define APS_AST_REGION_0_MASK_LO_0_SCRREG                       APS_AST_SCR_AST_REG_0_SEC_CONTROL_0
+#define APS_AST_REGION_0_MASK_LO_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_0_MASK_LO_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASK_LO_0_RESET_MASK                   MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_0_MASK_LO_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASK_LO_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASK_LO_0_READ_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_0_MASK_LO_0_WRITE_MASK                   MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_0_MASK_LO_0_Mask_SHIFT                   MK_SHIFT_CONST(12)
+#define APS_AST_REGION_0_MASK_LO_0_Mask_FIELD                   MK_FIELD_CONST(0xfffff, APS_AST_REGION_0_MASK_LO_0_Mask_SHIFT)
+#define APS_AST_REGION_0_MASK_LO_0_Mask_RANGE                   31:12
+#define APS_AST_REGION_0_MASK_LO_0_Mask_MSB                     MK_SHIFT_CONST(31)
+#define APS_AST_REGION_0_MASK_LO_0_Mask_LSB                     MK_SHIFT_CONST(12)
+#define APS_AST_REGION_0_MASK_LO_0_Mask_WOFFSET                 0x0
+#define APS_AST_REGION_0_MASK_LO_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASK_LO_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_0_MASK_LO_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASK_LO_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASK_LO_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASK_LO_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_0_MASK_HI_0
+#define APS_AST_REGION_0_MASK_HI_0                      MK_ADDR_CONST(0x10c)
+#define APS_AST_REGION_0_MASK_HI_0_SECURE                       0x0
+#define APS_AST_REGION_0_MASK_HI_0_DUAL                         0x0
+#define APS_AST_REGION_0_MASK_HI_0_SCR                  AST_REG_0_SEC_CONTROL_0
+#define APS_AST_REGION_0_MASK_HI_0_SCRREG                       APS_AST_SCR_AST_REG_0_SEC_CONTROL_0
+#define APS_AST_REGION_0_MASK_HI_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_0_MASK_HI_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASK_HI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_0_MASK_HI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASK_HI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASK_HI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_0_MASK_HI_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_0_MASK_HI_0_Mask_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_0_MASK_HI_0_Mask_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_REGION_0_MASK_HI_0_Mask_SHIFT)
+#define APS_AST_REGION_0_MASK_HI_0_Mask_RANGE                   31:0
+#define APS_AST_REGION_0_MASK_HI_0_Mask_MSB                     MK_SHIFT_CONST(31)
+#define APS_AST_REGION_0_MASK_HI_0_Mask_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_0_MASK_HI_0_Mask_WOFFSET                 0x0
+#define APS_AST_REGION_0_MASK_HI_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASK_HI_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_0_MASK_HI_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASK_HI_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASK_HI_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASK_HI_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_0_MASTER_BASE_LO_0
+#define APS_AST_REGION_0_MASTER_BASE_LO_0                       MK_ADDR_CONST(0x110)
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_SECURE                        0x0
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_DUAL                  0x0
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_SCR                   AST_REG_0_SEC_CONTROL_0
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_SCRREG                        APS_AST_SCR_AST_REG_0_SEC_CONTROL_0
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_WORD_COUNT                    0x1
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_RESET_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_READ_MASK                     MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_WRITE_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_SHIFT                        MK_SHIFT_CONST(12)
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_FIELD                        MK_FIELD_CONST(0xfffff, APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_SHIFT)
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_RANGE                        31:12
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_MSB                  MK_SHIFT_CONST(31)
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_LSB                  MK_SHIFT_CONST(12)
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_WOFFSET                      0x0
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASTER_BASE_LO_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_0_MASTER_BASE_HI_0
+#define APS_AST_REGION_0_MASTER_BASE_HI_0                       MK_ADDR_CONST(0x114)
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_SECURE                        0x0
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_DUAL                  0x0
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_SCR                   AST_REG_0_SEC_CONTROL_0
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_SCRREG                        APS_AST_SCR_AST_REG_0_SEC_CONTROL_0
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_WORD_COUNT                    0x1
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_SHIFT                        MK_SHIFT_CONST(0)
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_FIELD                        MK_FIELD_CONST(0xffffffff, APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_SHIFT)
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_RANGE                        31:0
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_MSB                  MK_SHIFT_CONST(31)
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_LSB                  MK_SHIFT_CONST(0)
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_WOFFSET                      0x0
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_MASTER_BASE_HI_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_0_CONTROL_0
+#define APS_AST_REGION_0_CONTROL_0                      MK_ADDR_CONST(0x118)
+#define APS_AST_REGION_0_CONTROL_0_SECURE                       0x0
+#define APS_AST_REGION_0_CONTROL_0_DUAL                         0x0
+#define APS_AST_REGION_0_CONTROL_0_SCR                  AST_REG_0_SEC_CONTROL_0
+#define APS_AST_REGION_0_CONTROL_0_SCRREG                       APS_AST_SCR_AST_REG_0_SEC_CONTROL_0
+#define APS_AST_REGION_0_CONTROL_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_0_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_0_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_READ_MASK                    MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_0_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_0_CONTROL_0_Physical_SHIFT                       MK_SHIFT_CONST(19)
+#define APS_AST_REGION_0_CONTROL_0_Physical_FIELD                       MK_FIELD_CONST(0x1, APS_AST_REGION_0_CONTROL_0_Physical_SHIFT)
+#define APS_AST_REGION_0_CONTROL_0_Physical_RANGE                       19:19
+#define APS_AST_REGION_0_CONTROL_0_Physical_MSB                 MK_SHIFT_CONST(19)
+#define APS_AST_REGION_0_CONTROL_0_Physical_LSB                 MK_SHIFT_CONST(19)
+#define APS_AST_REGION_0_CONTROL_0_Physical_WOFFSET                     0x0
+#define APS_AST_REGION_0_CONTROL_0_Physical_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_Physical_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define APS_AST_REGION_0_CONTROL_0_Physical_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_Physical_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_Physical_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_Physical_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_0_CONTROL_0_VMIndex_SHIFT                        MK_SHIFT_CONST(15)
+#define APS_AST_REGION_0_CONTROL_0_VMIndex_FIELD                        MK_FIELD_CONST(0xf, APS_AST_REGION_0_CONTROL_0_VMIndex_SHIFT)
+#define APS_AST_REGION_0_CONTROL_0_VMIndex_RANGE                        18:15
+#define APS_AST_REGION_0_CONTROL_0_VMIndex_MSB                  MK_SHIFT_CONST(18)
+#define APS_AST_REGION_0_CONTROL_0_VMIndex_LSB                  MK_SHIFT_CONST(15)
+#define APS_AST_REGION_0_CONTROL_0_VMIndex_WOFFSET                      0x0
+#define APS_AST_REGION_0_CONTROL_0_VMIndex_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_VMIndex_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define APS_AST_REGION_0_CONTROL_0_VMIndex_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_VMIndex_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_VMIndex_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_VMIndex_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_0_CONTROL_0_CarveOutID_SHIFT                     MK_SHIFT_CONST(5)
+#define APS_AST_REGION_0_CONTROL_0_CarveOutID_FIELD                     MK_FIELD_CONST(0x1f, APS_AST_REGION_0_CONTROL_0_CarveOutID_SHIFT)
+#define APS_AST_REGION_0_CONTROL_0_CarveOutID_RANGE                     9:5
+#define APS_AST_REGION_0_CONTROL_0_CarveOutID_MSB                       MK_SHIFT_CONST(9)
+#define APS_AST_REGION_0_CONTROL_0_CarveOutID_LSB                       MK_SHIFT_CONST(5)
+#define APS_AST_REGION_0_CONTROL_0_CarveOutID_WOFFSET                   0x0
+#define APS_AST_REGION_0_CONTROL_0_CarveOutID_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_CarveOutID_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
+#define APS_AST_REGION_0_CONTROL_0_CarveOutID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_CarveOutID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_CarveOutID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_CarveOutID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_0_CONTROL_0_Snoop_SHIFT                  MK_SHIFT_CONST(2)
+#define APS_AST_REGION_0_CONTROL_0_Snoop_FIELD                  MK_FIELD_CONST(0x1, APS_AST_REGION_0_CONTROL_0_Snoop_SHIFT)
+#define APS_AST_REGION_0_CONTROL_0_Snoop_RANGE                  2:2
+#define APS_AST_REGION_0_CONTROL_0_Snoop_MSB                    MK_SHIFT_CONST(2)
+#define APS_AST_REGION_0_CONTROL_0_Snoop_LSB                    MK_SHIFT_CONST(2)
+#define APS_AST_REGION_0_CONTROL_0_Snoop_WOFFSET                        0x0
+#define APS_AST_REGION_0_CONTROL_0_Snoop_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_Snoop_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define APS_AST_REGION_0_CONTROL_0_Snoop_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_Snoop_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_Snoop_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_Snoop_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define APS_AST_REGION_0_CONTROL_0_Snoop_DISABLE                        MK_ENUM_CONST(0)
+#define APS_AST_REGION_0_CONTROL_0_Snoop_ENABLE                 MK_ENUM_CONST(1)
+
+#define APS_AST_REGION_0_CONTROL_0_Lock_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_0_CONTROL_0_Lock_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_0_CONTROL_0_Lock_SHIFT)
+#define APS_AST_REGION_0_CONTROL_0_Lock_RANGE                   0:0
+#define APS_AST_REGION_0_CONTROL_0_Lock_MSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_0_CONTROL_0_Lock_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_0_CONTROL_0_Lock_WOFFSET                 0x0
+#define APS_AST_REGION_0_CONTROL_0_Lock_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_Lock_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_AST_REGION_0_CONTROL_0_Lock_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_Lock_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_Lock_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_0_CONTROL_0_Lock_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define APS_AST_REGION_0_CONTROL_0_Lock_FALSE                   MK_ENUM_CONST(0)
+#define APS_AST_REGION_0_CONTROL_0_Lock_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_REGION_1_SLAVE_BASE_LO_0
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0                        MK_ADDR_CONST(0x120)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SECURE                         0x0
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_DUAL                   0x0
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SCR                    AST_REG_1_SEC_CONTROL_0
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SCRREG                         APS_AST_SCR_AST_REG_1_SEC_CONTROL_0
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_WORD_COUNT                     0x1
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_RESET_MASK                     MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_READ_MASK                      MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_WRITE_MASK                     MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_SHIFT                  MK_SHIFT_CONST(12)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_FIELD                  MK_FIELD_CONST(0xfffff, APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_SHIFT)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_RANGE                  31:12
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_LSB                    MK_SHIFT_CONST(12)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_WOFFSET                        0x0
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_SHIFT)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_RANGE                   0:0
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_MSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_WOFFSET                 0x0
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_FALSE                   MK_ENUM_CONST(0)
+#define APS_AST_REGION_1_SLAVE_BASE_LO_0_Enable_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_REGION_1_SLAVE_BASE_HI_0
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0                        MK_ADDR_CONST(0x124)
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SECURE                         0x0
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_DUAL                   0x0
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SCR                    AST_REG_1_SEC_CONTROL_0
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SCRREG                         APS_AST_SCR_AST_REG_1_SEC_CONTROL_0
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_WORD_COUNT                     0x1
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_SHIFT                  MK_SHIFT_CONST(0)
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_FIELD                  MK_FIELD_CONST(0xffffffff, APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_SHIFT)
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_RANGE                  31:0
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_LSB                    MK_SHIFT_CONST(0)
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_WOFFSET                        0x0
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_SLAVE_BASE_HI_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_1_MASK_LO_0
+#define APS_AST_REGION_1_MASK_LO_0                      MK_ADDR_CONST(0x128)
+#define APS_AST_REGION_1_MASK_LO_0_SECURE                       0x0
+#define APS_AST_REGION_1_MASK_LO_0_DUAL                         0x0
+#define APS_AST_REGION_1_MASK_LO_0_SCR                  AST_REG_1_SEC_CONTROL_0
+#define APS_AST_REGION_1_MASK_LO_0_SCRREG                       APS_AST_SCR_AST_REG_1_SEC_CONTROL_0
+#define APS_AST_REGION_1_MASK_LO_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_1_MASK_LO_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASK_LO_0_RESET_MASK                   MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_1_MASK_LO_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASK_LO_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASK_LO_0_READ_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_1_MASK_LO_0_WRITE_MASK                   MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_1_MASK_LO_0_Mask_SHIFT                   MK_SHIFT_CONST(12)
+#define APS_AST_REGION_1_MASK_LO_0_Mask_FIELD                   MK_FIELD_CONST(0xfffff, APS_AST_REGION_1_MASK_LO_0_Mask_SHIFT)
+#define APS_AST_REGION_1_MASK_LO_0_Mask_RANGE                   31:12
+#define APS_AST_REGION_1_MASK_LO_0_Mask_MSB                     MK_SHIFT_CONST(31)
+#define APS_AST_REGION_1_MASK_LO_0_Mask_LSB                     MK_SHIFT_CONST(12)
+#define APS_AST_REGION_1_MASK_LO_0_Mask_WOFFSET                 0x0
+#define APS_AST_REGION_1_MASK_LO_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASK_LO_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_1_MASK_LO_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASK_LO_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASK_LO_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASK_LO_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_1_MASK_HI_0
+#define APS_AST_REGION_1_MASK_HI_0                      MK_ADDR_CONST(0x12c)
+#define APS_AST_REGION_1_MASK_HI_0_SECURE                       0x0
+#define APS_AST_REGION_1_MASK_HI_0_DUAL                         0x0
+#define APS_AST_REGION_1_MASK_HI_0_SCR                  AST_REG_1_SEC_CONTROL_0
+#define APS_AST_REGION_1_MASK_HI_0_SCRREG                       APS_AST_SCR_AST_REG_1_SEC_CONTROL_0
+#define APS_AST_REGION_1_MASK_HI_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_1_MASK_HI_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASK_HI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_1_MASK_HI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASK_HI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASK_HI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_1_MASK_HI_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_1_MASK_HI_0_Mask_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_1_MASK_HI_0_Mask_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_REGION_1_MASK_HI_0_Mask_SHIFT)
+#define APS_AST_REGION_1_MASK_HI_0_Mask_RANGE                   31:0
+#define APS_AST_REGION_1_MASK_HI_0_Mask_MSB                     MK_SHIFT_CONST(31)
+#define APS_AST_REGION_1_MASK_HI_0_Mask_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_1_MASK_HI_0_Mask_WOFFSET                 0x0
+#define APS_AST_REGION_1_MASK_HI_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASK_HI_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_1_MASK_HI_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASK_HI_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASK_HI_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASK_HI_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_1_MASTER_BASE_LO_0
+#define APS_AST_REGION_1_MASTER_BASE_LO_0                       MK_ADDR_CONST(0x130)
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_SECURE                        0x0
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_DUAL                  0x0
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_SCR                   AST_REG_1_SEC_CONTROL_0
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_SCRREG                        APS_AST_SCR_AST_REG_1_SEC_CONTROL_0
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_WORD_COUNT                    0x1
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_RESET_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_READ_MASK                     MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_WRITE_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_SHIFT                        MK_SHIFT_CONST(12)
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_FIELD                        MK_FIELD_CONST(0xfffff, APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_SHIFT)
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_RANGE                        31:12
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_MSB                  MK_SHIFT_CONST(31)
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_LSB                  MK_SHIFT_CONST(12)
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_WOFFSET                      0x0
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASTER_BASE_LO_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_1_MASTER_BASE_HI_0
+#define APS_AST_REGION_1_MASTER_BASE_HI_0                       MK_ADDR_CONST(0x134)
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_SECURE                        0x0
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_DUAL                  0x0
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_SCR                   AST_REG_1_SEC_CONTROL_0
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_SCRREG                        APS_AST_SCR_AST_REG_1_SEC_CONTROL_0
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_WORD_COUNT                    0x1
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_SHIFT                        MK_SHIFT_CONST(0)
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_FIELD                        MK_FIELD_CONST(0xffffffff, APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_SHIFT)
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_RANGE                        31:0
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_MSB                  MK_SHIFT_CONST(31)
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_LSB                  MK_SHIFT_CONST(0)
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_WOFFSET                      0x0
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_MASTER_BASE_HI_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_1_CONTROL_0
+#define APS_AST_REGION_1_CONTROL_0                      MK_ADDR_CONST(0x138)
+#define APS_AST_REGION_1_CONTROL_0_SECURE                       0x0
+#define APS_AST_REGION_1_CONTROL_0_DUAL                         0x0
+#define APS_AST_REGION_1_CONTROL_0_SCR                  AST_REG_1_SEC_CONTROL_0
+#define APS_AST_REGION_1_CONTROL_0_SCRREG                       APS_AST_SCR_AST_REG_1_SEC_CONTROL_0
+#define APS_AST_REGION_1_CONTROL_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_1_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_1_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_READ_MASK                    MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_1_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_1_CONTROL_0_Physical_SHIFT                       MK_SHIFT_CONST(19)
+#define APS_AST_REGION_1_CONTROL_0_Physical_FIELD                       MK_FIELD_CONST(0x1, APS_AST_REGION_1_CONTROL_0_Physical_SHIFT)
+#define APS_AST_REGION_1_CONTROL_0_Physical_RANGE                       19:19
+#define APS_AST_REGION_1_CONTROL_0_Physical_MSB                 MK_SHIFT_CONST(19)
+#define APS_AST_REGION_1_CONTROL_0_Physical_LSB                 MK_SHIFT_CONST(19)
+#define APS_AST_REGION_1_CONTROL_0_Physical_WOFFSET                     0x0
+#define APS_AST_REGION_1_CONTROL_0_Physical_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_Physical_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define APS_AST_REGION_1_CONTROL_0_Physical_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_Physical_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_Physical_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_Physical_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_1_CONTROL_0_VMIndex_SHIFT                        MK_SHIFT_CONST(15)
+#define APS_AST_REGION_1_CONTROL_0_VMIndex_FIELD                        MK_FIELD_CONST(0xf, APS_AST_REGION_1_CONTROL_0_VMIndex_SHIFT)
+#define APS_AST_REGION_1_CONTROL_0_VMIndex_RANGE                        18:15
+#define APS_AST_REGION_1_CONTROL_0_VMIndex_MSB                  MK_SHIFT_CONST(18)
+#define APS_AST_REGION_1_CONTROL_0_VMIndex_LSB                  MK_SHIFT_CONST(15)
+#define APS_AST_REGION_1_CONTROL_0_VMIndex_WOFFSET                      0x0
+#define APS_AST_REGION_1_CONTROL_0_VMIndex_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_VMIndex_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define APS_AST_REGION_1_CONTROL_0_VMIndex_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_VMIndex_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_VMIndex_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_VMIndex_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_1_CONTROL_0_CarveOutID_SHIFT                     MK_SHIFT_CONST(5)
+#define APS_AST_REGION_1_CONTROL_0_CarveOutID_FIELD                     MK_FIELD_CONST(0x1f, APS_AST_REGION_1_CONTROL_0_CarveOutID_SHIFT)
+#define APS_AST_REGION_1_CONTROL_0_CarveOutID_RANGE                     9:5
+#define APS_AST_REGION_1_CONTROL_0_CarveOutID_MSB                       MK_SHIFT_CONST(9)
+#define APS_AST_REGION_1_CONTROL_0_CarveOutID_LSB                       MK_SHIFT_CONST(5)
+#define APS_AST_REGION_1_CONTROL_0_CarveOutID_WOFFSET                   0x0
+#define APS_AST_REGION_1_CONTROL_0_CarveOutID_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_CarveOutID_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
+#define APS_AST_REGION_1_CONTROL_0_CarveOutID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_CarveOutID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_CarveOutID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_CarveOutID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_1_CONTROL_0_Snoop_SHIFT                  MK_SHIFT_CONST(2)
+#define APS_AST_REGION_1_CONTROL_0_Snoop_FIELD                  MK_FIELD_CONST(0x1, APS_AST_REGION_1_CONTROL_0_Snoop_SHIFT)
+#define APS_AST_REGION_1_CONTROL_0_Snoop_RANGE                  2:2
+#define APS_AST_REGION_1_CONTROL_0_Snoop_MSB                    MK_SHIFT_CONST(2)
+#define APS_AST_REGION_1_CONTROL_0_Snoop_LSB                    MK_SHIFT_CONST(2)
+#define APS_AST_REGION_1_CONTROL_0_Snoop_WOFFSET                        0x0
+#define APS_AST_REGION_1_CONTROL_0_Snoop_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_Snoop_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define APS_AST_REGION_1_CONTROL_0_Snoop_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_Snoop_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_Snoop_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_Snoop_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define APS_AST_REGION_1_CONTROL_0_Snoop_DISABLE                        MK_ENUM_CONST(0)
+#define APS_AST_REGION_1_CONTROL_0_Snoop_ENABLE                 MK_ENUM_CONST(1)
+
+#define APS_AST_REGION_1_CONTROL_0_Lock_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_1_CONTROL_0_Lock_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_1_CONTROL_0_Lock_SHIFT)
+#define APS_AST_REGION_1_CONTROL_0_Lock_RANGE                   0:0
+#define APS_AST_REGION_1_CONTROL_0_Lock_MSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_1_CONTROL_0_Lock_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_1_CONTROL_0_Lock_WOFFSET                 0x0
+#define APS_AST_REGION_1_CONTROL_0_Lock_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_Lock_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_AST_REGION_1_CONTROL_0_Lock_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_Lock_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_Lock_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_1_CONTROL_0_Lock_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define APS_AST_REGION_1_CONTROL_0_Lock_FALSE                   MK_ENUM_CONST(0)
+#define APS_AST_REGION_1_CONTROL_0_Lock_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_REGION_2_SLAVE_BASE_LO_0
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0                        MK_ADDR_CONST(0x140)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SECURE                         0x0
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_DUAL                   0x0
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SCR                    AST_REG_2_SEC_CONTROL_0
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SCRREG                         APS_AST_SCR_AST_REG_2_SEC_CONTROL_0
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_WORD_COUNT                     0x1
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_RESET_MASK                     MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_READ_MASK                      MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_WRITE_MASK                     MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_SHIFT                  MK_SHIFT_CONST(12)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_FIELD                  MK_FIELD_CONST(0xfffff, APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_SHIFT)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_RANGE                  31:12
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_LSB                    MK_SHIFT_CONST(12)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_WOFFSET                        0x0
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_SHIFT)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_RANGE                   0:0
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_MSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_WOFFSET                 0x0
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_FALSE                   MK_ENUM_CONST(0)
+#define APS_AST_REGION_2_SLAVE_BASE_LO_0_Enable_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_REGION_2_SLAVE_BASE_HI_0
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0                        MK_ADDR_CONST(0x144)
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SECURE                         0x0
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_DUAL                   0x0
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SCR                    AST_REG_2_SEC_CONTROL_0
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SCRREG                         APS_AST_SCR_AST_REG_2_SEC_CONTROL_0
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_WORD_COUNT                     0x1
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_SHIFT                  MK_SHIFT_CONST(0)
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_FIELD                  MK_FIELD_CONST(0xffffffff, APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_SHIFT)
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_RANGE                  31:0
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_LSB                    MK_SHIFT_CONST(0)
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_WOFFSET                        0x0
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_SLAVE_BASE_HI_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_2_MASK_LO_0
+#define APS_AST_REGION_2_MASK_LO_0                      MK_ADDR_CONST(0x148)
+#define APS_AST_REGION_2_MASK_LO_0_SECURE                       0x0
+#define APS_AST_REGION_2_MASK_LO_0_DUAL                         0x0
+#define APS_AST_REGION_2_MASK_LO_0_SCR                  AST_REG_2_SEC_CONTROL_0
+#define APS_AST_REGION_2_MASK_LO_0_SCRREG                       APS_AST_SCR_AST_REG_2_SEC_CONTROL_0
+#define APS_AST_REGION_2_MASK_LO_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_2_MASK_LO_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASK_LO_0_RESET_MASK                   MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_2_MASK_LO_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASK_LO_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASK_LO_0_READ_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_2_MASK_LO_0_WRITE_MASK                   MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_2_MASK_LO_0_Mask_SHIFT                   MK_SHIFT_CONST(12)
+#define APS_AST_REGION_2_MASK_LO_0_Mask_FIELD                   MK_FIELD_CONST(0xfffff, APS_AST_REGION_2_MASK_LO_0_Mask_SHIFT)
+#define APS_AST_REGION_2_MASK_LO_0_Mask_RANGE                   31:12
+#define APS_AST_REGION_2_MASK_LO_0_Mask_MSB                     MK_SHIFT_CONST(31)
+#define APS_AST_REGION_2_MASK_LO_0_Mask_LSB                     MK_SHIFT_CONST(12)
+#define APS_AST_REGION_2_MASK_LO_0_Mask_WOFFSET                 0x0
+#define APS_AST_REGION_2_MASK_LO_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASK_LO_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_2_MASK_LO_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASK_LO_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASK_LO_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASK_LO_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_2_MASK_HI_0
+#define APS_AST_REGION_2_MASK_HI_0                      MK_ADDR_CONST(0x14c)
+#define APS_AST_REGION_2_MASK_HI_0_SECURE                       0x0
+#define APS_AST_REGION_2_MASK_HI_0_DUAL                         0x0
+#define APS_AST_REGION_2_MASK_HI_0_SCR                  AST_REG_2_SEC_CONTROL_0
+#define APS_AST_REGION_2_MASK_HI_0_SCRREG                       APS_AST_SCR_AST_REG_2_SEC_CONTROL_0
+#define APS_AST_REGION_2_MASK_HI_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_2_MASK_HI_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASK_HI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_2_MASK_HI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASK_HI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASK_HI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_2_MASK_HI_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_2_MASK_HI_0_Mask_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_2_MASK_HI_0_Mask_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_REGION_2_MASK_HI_0_Mask_SHIFT)
+#define APS_AST_REGION_2_MASK_HI_0_Mask_RANGE                   31:0
+#define APS_AST_REGION_2_MASK_HI_0_Mask_MSB                     MK_SHIFT_CONST(31)
+#define APS_AST_REGION_2_MASK_HI_0_Mask_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_2_MASK_HI_0_Mask_WOFFSET                 0x0
+#define APS_AST_REGION_2_MASK_HI_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASK_HI_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_2_MASK_HI_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASK_HI_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASK_HI_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASK_HI_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_2_MASTER_BASE_LO_0
+#define APS_AST_REGION_2_MASTER_BASE_LO_0                       MK_ADDR_CONST(0x150)
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_SECURE                        0x0
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_DUAL                  0x0
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_SCR                   AST_REG_2_SEC_CONTROL_0
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_SCRREG                        APS_AST_SCR_AST_REG_2_SEC_CONTROL_0
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_WORD_COUNT                    0x1
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_RESET_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_READ_MASK                     MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_WRITE_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_SHIFT                        MK_SHIFT_CONST(12)
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_FIELD                        MK_FIELD_CONST(0xfffff, APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_SHIFT)
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_RANGE                        31:12
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_MSB                  MK_SHIFT_CONST(31)
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_LSB                  MK_SHIFT_CONST(12)
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_WOFFSET                      0x0
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASTER_BASE_LO_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_2_MASTER_BASE_HI_0
+#define APS_AST_REGION_2_MASTER_BASE_HI_0                       MK_ADDR_CONST(0x154)
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_SECURE                        0x0
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_DUAL                  0x0
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_SCR                   AST_REG_2_SEC_CONTROL_0
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_SCRREG                        APS_AST_SCR_AST_REG_2_SEC_CONTROL_0
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_WORD_COUNT                    0x1
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_SHIFT                        MK_SHIFT_CONST(0)
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_FIELD                        MK_FIELD_CONST(0xffffffff, APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_SHIFT)
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_RANGE                        31:0
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_MSB                  MK_SHIFT_CONST(31)
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_LSB                  MK_SHIFT_CONST(0)
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_WOFFSET                      0x0
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_MASTER_BASE_HI_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_2_CONTROL_0
+#define APS_AST_REGION_2_CONTROL_0                      MK_ADDR_CONST(0x158)
+#define APS_AST_REGION_2_CONTROL_0_SECURE                       0x0
+#define APS_AST_REGION_2_CONTROL_0_DUAL                         0x0
+#define APS_AST_REGION_2_CONTROL_0_SCR                  AST_REG_2_SEC_CONTROL_0
+#define APS_AST_REGION_2_CONTROL_0_SCRREG                       APS_AST_SCR_AST_REG_2_SEC_CONTROL_0
+#define APS_AST_REGION_2_CONTROL_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_2_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_2_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_READ_MASK                    MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_2_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_2_CONTROL_0_Physical_SHIFT                       MK_SHIFT_CONST(19)
+#define APS_AST_REGION_2_CONTROL_0_Physical_FIELD                       MK_FIELD_CONST(0x1, APS_AST_REGION_2_CONTROL_0_Physical_SHIFT)
+#define APS_AST_REGION_2_CONTROL_0_Physical_RANGE                       19:19
+#define APS_AST_REGION_2_CONTROL_0_Physical_MSB                 MK_SHIFT_CONST(19)
+#define APS_AST_REGION_2_CONTROL_0_Physical_LSB                 MK_SHIFT_CONST(19)
+#define APS_AST_REGION_2_CONTROL_0_Physical_WOFFSET                     0x0
+#define APS_AST_REGION_2_CONTROL_0_Physical_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_Physical_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define APS_AST_REGION_2_CONTROL_0_Physical_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_Physical_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_Physical_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_Physical_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_2_CONTROL_0_VMIndex_SHIFT                        MK_SHIFT_CONST(15)
+#define APS_AST_REGION_2_CONTROL_0_VMIndex_FIELD                        MK_FIELD_CONST(0xf, APS_AST_REGION_2_CONTROL_0_VMIndex_SHIFT)
+#define APS_AST_REGION_2_CONTROL_0_VMIndex_RANGE                        18:15
+#define APS_AST_REGION_2_CONTROL_0_VMIndex_MSB                  MK_SHIFT_CONST(18)
+#define APS_AST_REGION_2_CONTROL_0_VMIndex_LSB                  MK_SHIFT_CONST(15)
+#define APS_AST_REGION_2_CONTROL_0_VMIndex_WOFFSET                      0x0
+#define APS_AST_REGION_2_CONTROL_0_VMIndex_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_VMIndex_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define APS_AST_REGION_2_CONTROL_0_VMIndex_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_VMIndex_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_VMIndex_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_VMIndex_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_2_CONTROL_0_CarveOutID_SHIFT                     MK_SHIFT_CONST(5)
+#define APS_AST_REGION_2_CONTROL_0_CarveOutID_FIELD                     MK_FIELD_CONST(0x1f, APS_AST_REGION_2_CONTROL_0_CarveOutID_SHIFT)
+#define APS_AST_REGION_2_CONTROL_0_CarveOutID_RANGE                     9:5
+#define APS_AST_REGION_2_CONTROL_0_CarveOutID_MSB                       MK_SHIFT_CONST(9)
+#define APS_AST_REGION_2_CONTROL_0_CarveOutID_LSB                       MK_SHIFT_CONST(5)
+#define APS_AST_REGION_2_CONTROL_0_CarveOutID_WOFFSET                   0x0
+#define APS_AST_REGION_2_CONTROL_0_CarveOutID_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_CarveOutID_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
+#define APS_AST_REGION_2_CONTROL_0_CarveOutID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_CarveOutID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_CarveOutID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_CarveOutID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_2_CONTROL_0_Snoop_SHIFT                  MK_SHIFT_CONST(2)
+#define APS_AST_REGION_2_CONTROL_0_Snoop_FIELD                  MK_FIELD_CONST(0x1, APS_AST_REGION_2_CONTROL_0_Snoop_SHIFT)
+#define APS_AST_REGION_2_CONTROL_0_Snoop_RANGE                  2:2
+#define APS_AST_REGION_2_CONTROL_0_Snoop_MSB                    MK_SHIFT_CONST(2)
+#define APS_AST_REGION_2_CONTROL_0_Snoop_LSB                    MK_SHIFT_CONST(2)
+#define APS_AST_REGION_2_CONTROL_0_Snoop_WOFFSET                        0x0
+#define APS_AST_REGION_2_CONTROL_0_Snoop_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_Snoop_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define APS_AST_REGION_2_CONTROL_0_Snoop_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_Snoop_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_Snoop_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_Snoop_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define APS_AST_REGION_2_CONTROL_0_Snoop_DISABLE                        MK_ENUM_CONST(0)
+#define APS_AST_REGION_2_CONTROL_0_Snoop_ENABLE                 MK_ENUM_CONST(1)
+
+#define APS_AST_REGION_2_CONTROL_0_Lock_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_2_CONTROL_0_Lock_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_2_CONTROL_0_Lock_SHIFT)
+#define APS_AST_REGION_2_CONTROL_0_Lock_RANGE                   0:0
+#define APS_AST_REGION_2_CONTROL_0_Lock_MSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_2_CONTROL_0_Lock_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_2_CONTROL_0_Lock_WOFFSET                 0x0
+#define APS_AST_REGION_2_CONTROL_0_Lock_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_Lock_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_AST_REGION_2_CONTROL_0_Lock_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_Lock_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_Lock_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_2_CONTROL_0_Lock_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define APS_AST_REGION_2_CONTROL_0_Lock_FALSE                   MK_ENUM_CONST(0)
+#define APS_AST_REGION_2_CONTROL_0_Lock_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_REGION_3_SLAVE_BASE_LO_0
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0                        MK_ADDR_CONST(0x160)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SECURE                         0x0
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_DUAL                   0x0
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SCR                    AST_REG_3_SEC_CONTROL_0
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SCRREG                         APS_AST_SCR_AST_REG_3_SEC_CONTROL_0
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_WORD_COUNT                     0x1
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_RESET_MASK                     MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_READ_MASK                      MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_WRITE_MASK                     MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_SHIFT                  MK_SHIFT_CONST(12)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_FIELD                  MK_FIELD_CONST(0xfffff, APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_SHIFT)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_RANGE                  31:12
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_LSB                    MK_SHIFT_CONST(12)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_WOFFSET                        0x0
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_SHIFT)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_RANGE                   0:0
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_MSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_WOFFSET                 0x0
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_FALSE                   MK_ENUM_CONST(0)
+#define APS_AST_REGION_3_SLAVE_BASE_LO_0_Enable_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_REGION_3_SLAVE_BASE_HI_0
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0                        MK_ADDR_CONST(0x164)
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SECURE                         0x0
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_DUAL                   0x0
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SCR                    AST_REG_3_SEC_CONTROL_0
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SCRREG                         APS_AST_SCR_AST_REG_3_SEC_CONTROL_0
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_WORD_COUNT                     0x1
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_SHIFT                  MK_SHIFT_CONST(0)
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_FIELD                  MK_FIELD_CONST(0xffffffff, APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_SHIFT)
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_RANGE                  31:0
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_LSB                    MK_SHIFT_CONST(0)
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_WOFFSET                        0x0
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_SLAVE_BASE_HI_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_3_MASK_LO_0
+#define APS_AST_REGION_3_MASK_LO_0                      MK_ADDR_CONST(0x168)
+#define APS_AST_REGION_3_MASK_LO_0_SECURE                       0x0
+#define APS_AST_REGION_3_MASK_LO_0_DUAL                         0x0
+#define APS_AST_REGION_3_MASK_LO_0_SCR                  AST_REG_3_SEC_CONTROL_0
+#define APS_AST_REGION_3_MASK_LO_0_SCRREG                       APS_AST_SCR_AST_REG_3_SEC_CONTROL_0
+#define APS_AST_REGION_3_MASK_LO_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_3_MASK_LO_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASK_LO_0_RESET_MASK                   MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_3_MASK_LO_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASK_LO_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASK_LO_0_READ_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_3_MASK_LO_0_WRITE_MASK                   MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_3_MASK_LO_0_Mask_SHIFT                   MK_SHIFT_CONST(12)
+#define APS_AST_REGION_3_MASK_LO_0_Mask_FIELD                   MK_FIELD_CONST(0xfffff, APS_AST_REGION_3_MASK_LO_0_Mask_SHIFT)
+#define APS_AST_REGION_3_MASK_LO_0_Mask_RANGE                   31:12
+#define APS_AST_REGION_3_MASK_LO_0_Mask_MSB                     MK_SHIFT_CONST(31)
+#define APS_AST_REGION_3_MASK_LO_0_Mask_LSB                     MK_SHIFT_CONST(12)
+#define APS_AST_REGION_3_MASK_LO_0_Mask_WOFFSET                 0x0
+#define APS_AST_REGION_3_MASK_LO_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASK_LO_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_3_MASK_LO_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASK_LO_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASK_LO_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASK_LO_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_3_MASK_HI_0
+#define APS_AST_REGION_3_MASK_HI_0                      MK_ADDR_CONST(0x16c)
+#define APS_AST_REGION_3_MASK_HI_0_SECURE                       0x0
+#define APS_AST_REGION_3_MASK_HI_0_DUAL                         0x0
+#define APS_AST_REGION_3_MASK_HI_0_SCR                  AST_REG_3_SEC_CONTROL_0
+#define APS_AST_REGION_3_MASK_HI_0_SCRREG                       APS_AST_SCR_AST_REG_3_SEC_CONTROL_0
+#define APS_AST_REGION_3_MASK_HI_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_3_MASK_HI_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASK_HI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_3_MASK_HI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASK_HI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASK_HI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_3_MASK_HI_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_3_MASK_HI_0_Mask_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_3_MASK_HI_0_Mask_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_REGION_3_MASK_HI_0_Mask_SHIFT)
+#define APS_AST_REGION_3_MASK_HI_0_Mask_RANGE                   31:0
+#define APS_AST_REGION_3_MASK_HI_0_Mask_MSB                     MK_SHIFT_CONST(31)
+#define APS_AST_REGION_3_MASK_HI_0_Mask_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_3_MASK_HI_0_Mask_WOFFSET                 0x0
+#define APS_AST_REGION_3_MASK_HI_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASK_HI_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_3_MASK_HI_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASK_HI_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASK_HI_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASK_HI_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_3_MASTER_BASE_LO_0
+#define APS_AST_REGION_3_MASTER_BASE_LO_0                       MK_ADDR_CONST(0x170)
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_SECURE                        0x0
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_DUAL                  0x0
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_SCR                   AST_REG_3_SEC_CONTROL_0
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_SCRREG                        APS_AST_SCR_AST_REG_3_SEC_CONTROL_0
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_WORD_COUNT                    0x1
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_RESET_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_READ_MASK                     MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_WRITE_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_SHIFT                        MK_SHIFT_CONST(12)
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_FIELD                        MK_FIELD_CONST(0xfffff, APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_SHIFT)
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_RANGE                        31:12
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_MSB                  MK_SHIFT_CONST(31)
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_LSB                  MK_SHIFT_CONST(12)
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_WOFFSET                      0x0
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASTER_BASE_LO_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_3_MASTER_BASE_HI_0
+#define APS_AST_REGION_3_MASTER_BASE_HI_0                       MK_ADDR_CONST(0x174)
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_SECURE                        0x0
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_DUAL                  0x0
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_SCR                   AST_REG_3_SEC_CONTROL_0
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_SCRREG                        APS_AST_SCR_AST_REG_3_SEC_CONTROL_0
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_WORD_COUNT                    0x1
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_SHIFT                        MK_SHIFT_CONST(0)
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_FIELD                        MK_FIELD_CONST(0xffffffff, APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_SHIFT)
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_RANGE                        31:0
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_MSB                  MK_SHIFT_CONST(31)
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_LSB                  MK_SHIFT_CONST(0)
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_WOFFSET                      0x0
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_MASTER_BASE_HI_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_3_CONTROL_0
+#define APS_AST_REGION_3_CONTROL_0                      MK_ADDR_CONST(0x178)
+#define APS_AST_REGION_3_CONTROL_0_SECURE                       0x0
+#define APS_AST_REGION_3_CONTROL_0_DUAL                         0x0
+#define APS_AST_REGION_3_CONTROL_0_SCR                  AST_REG_3_SEC_CONTROL_0
+#define APS_AST_REGION_3_CONTROL_0_SCRREG                       APS_AST_SCR_AST_REG_3_SEC_CONTROL_0
+#define APS_AST_REGION_3_CONTROL_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_3_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_3_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_READ_MASK                    MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_3_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_3_CONTROL_0_Physical_SHIFT                       MK_SHIFT_CONST(19)
+#define APS_AST_REGION_3_CONTROL_0_Physical_FIELD                       MK_FIELD_CONST(0x1, APS_AST_REGION_3_CONTROL_0_Physical_SHIFT)
+#define APS_AST_REGION_3_CONTROL_0_Physical_RANGE                       19:19
+#define APS_AST_REGION_3_CONTROL_0_Physical_MSB                 MK_SHIFT_CONST(19)
+#define APS_AST_REGION_3_CONTROL_0_Physical_LSB                 MK_SHIFT_CONST(19)
+#define APS_AST_REGION_3_CONTROL_0_Physical_WOFFSET                     0x0
+#define APS_AST_REGION_3_CONTROL_0_Physical_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_Physical_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define APS_AST_REGION_3_CONTROL_0_Physical_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_Physical_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_Physical_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_Physical_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_3_CONTROL_0_VMIndex_SHIFT                        MK_SHIFT_CONST(15)
+#define APS_AST_REGION_3_CONTROL_0_VMIndex_FIELD                        MK_FIELD_CONST(0xf, APS_AST_REGION_3_CONTROL_0_VMIndex_SHIFT)
+#define APS_AST_REGION_3_CONTROL_0_VMIndex_RANGE                        18:15
+#define APS_AST_REGION_3_CONTROL_0_VMIndex_MSB                  MK_SHIFT_CONST(18)
+#define APS_AST_REGION_3_CONTROL_0_VMIndex_LSB                  MK_SHIFT_CONST(15)
+#define APS_AST_REGION_3_CONTROL_0_VMIndex_WOFFSET                      0x0
+#define APS_AST_REGION_3_CONTROL_0_VMIndex_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_VMIndex_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define APS_AST_REGION_3_CONTROL_0_VMIndex_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_VMIndex_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_VMIndex_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_VMIndex_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_3_CONTROL_0_CarveOutID_SHIFT                     MK_SHIFT_CONST(5)
+#define APS_AST_REGION_3_CONTROL_0_CarveOutID_FIELD                     MK_FIELD_CONST(0x1f, APS_AST_REGION_3_CONTROL_0_CarveOutID_SHIFT)
+#define APS_AST_REGION_3_CONTROL_0_CarveOutID_RANGE                     9:5
+#define APS_AST_REGION_3_CONTROL_0_CarveOutID_MSB                       MK_SHIFT_CONST(9)
+#define APS_AST_REGION_3_CONTROL_0_CarveOutID_LSB                       MK_SHIFT_CONST(5)
+#define APS_AST_REGION_3_CONTROL_0_CarveOutID_WOFFSET                   0x0
+#define APS_AST_REGION_3_CONTROL_0_CarveOutID_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_CarveOutID_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
+#define APS_AST_REGION_3_CONTROL_0_CarveOutID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_CarveOutID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_CarveOutID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_CarveOutID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_3_CONTROL_0_Snoop_SHIFT                  MK_SHIFT_CONST(2)
+#define APS_AST_REGION_3_CONTROL_0_Snoop_FIELD                  MK_FIELD_CONST(0x1, APS_AST_REGION_3_CONTROL_0_Snoop_SHIFT)
+#define APS_AST_REGION_3_CONTROL_0_Snoop_RANGE                  2:2
+#define APS_AST_REGION_3_CONTROL_0_Snoop_MSB                    MK_SHIFT_CONST(2)
+#define APS_AST_REGION_3_CONTROL_0_Snoop_LSB                    MK_SHIFT_CONST(2)
+#define APS_AST_REGION_3_CONTROL_0_Snoop_WOFFSET                        0x0
+#define APS_AST_REGION_3_CONTROL_0_Snoop_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_Snoop_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define APS_AST_REGION_3_CONTROL_0_Snoop_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_Snoop_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_Snoop_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_Snoop_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define APS_AST_REGION_3_CONTROL_0_Snoop_DISABLE                        MK_ENUM_CONST(0)
+#define APS_AST_REGION_3_CONTROL_0_Snoop_ENABLE                 MK_ENUM_CONST(1)
+
+#define APS_AST_REGION_3_CONTROL_0_Lock_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_3_CONTROL_0_Lock_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_3_CONTROL_0_Lock_SHIFT)
+#define APS_AST_REGION_3_CONTROL_0_Lock_RANGE                   0:0
+#define APS_AST_REGION_3_CONTROL_0_Lock_MSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_3_CONTROL_0_Lock_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_3_CONTROL_0_Lock_WOFFSET                 0x0
+#define APS_AST_REGION_3_CONTROL_0_Lock_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_Lock_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_AST_REGION_3_CONTROL_0_Lock_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_Lock_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_Lock_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_3_CONTROL_0_Lock_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define APS_AST_REGION_3_CONTROL_0_Lock_FALSE                   MK_ENUM_CONST(0)
+#define APS_AST_REGION_3_CONTROL_0_Lock_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_REGION_4_SLAVE_BASE_LO_0
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0                        MK_ADDR_CONST(0x180)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SECURE                         0x0
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_DUAL                   0x0
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SCR                    AST_REG_4_SEC_CONTROL_0
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SCRREG                         APS_AST_SCR_AST_REG_4_SEC_CONTROL_0
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_WORD_COUNT                     0x1
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_RESET_MASK                     MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_READ_MASK                      MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_WRITE_MASK                     MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_SHIFT                  MK_SHIFT_CONST(12)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_FIELD                  MK_FIELD_CONST(0xfffff, APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_SHIFT)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_RANGE                  31:12
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_LSB                    MK_SHIFT_CONST(12)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_WOFFSET                        0x0
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_SHIFT)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_RANGE                   0:0
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_MSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_WOFFSET                 0x0
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_FALSE                   MK_ENUM_CONST(0)
+#define APS_AST_REGION_4_SLAVE_BASE_LO_0_Enable_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_REGION_4_SLAVE_BASE_HI_0
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0                        MK_ADDR_CONST(0x184)
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SECURE                         0x0
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_DUAL                   0x0
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SCR                    AST_REG_4_SEC_CONTROL_0
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SCRREG                         APS_AST_SCR_AST_REG_4_SEC_CONTROL_0
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_WORD_COUNT                     0x1
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_SHIFT                  MK_SHIFT_CONST(0)
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_FIELD                  MK_FIELD_CONST(0xffffffff, APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_SHIFT)
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_RANGE                  31:0
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_LSB                    MK_SHIFT_CONST(0)
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_WOFFSET                        0x0
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_SLAVE_BASE_HI_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_4_MASK_LO_0
+#define APS_AST_REGION_4_MASK_LO_0                      MK_ADDR_CONST(0x188)
+#define APS_AST_REGION_4_MASK_LO_0_SECURE                       0x0
+#define APS_AST_REGION_4_MASK_LO_0_DUAL                         0x0
+#define APS_AST_REGION_4_MASK_LO_0_SCR                  AST_REG_4_SEC_CONTROL_0
+#define APS_AST_REGION_4_MASK_LO_0_SCRREG                       APS_AST_SCR_AST_REG_4_SEC_CONTROL_0
+#define APS_AST_REGION_4_MASK_LO_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_4_MASK_LO_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASK_LO_0_RESET_MASK                   MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_4_MASK_LO_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASK_LO_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASK_LO_0_READ_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_4_MASK_LO_0_WRITE_MASK                   MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_4_MASK_LO_0_Mask_SHIFT                   MK_SHIFT_CONST(12)
+#define APS_AST_REGION_4_MASK_LO_0_Mask_FIELD                   MK_FIELD_CONST(0xfffff, APS_AST_REGION_4_MASK_LO_0_Mask_SHIFT)
+#define APS_AST_REGION_4_MASK_LO_0_Mask_RANGE                   31:12
+#define APS_AST_REGION_4_MASK_LO_0_Mask_MSB                     MK_SHIFT_CONST(31)
+#define APS_AST_REGION_4_MASK_LO_0_Mask_LSB                     MK_SHIFT_CONST(12)
+#define APS_AST_REGION_4_MASK_LO_0_Mask_WOFFSET                 0x0
+#define APS_AST_REGION_4_MASK_LO_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASK_LO_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_4_MASK_LO_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASK_LO_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASK_LO_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASK_LO_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_4_MASK_HI_0
+#define APS_AST_REGION_4_MASK_HI_0                      MK_ADDR_CONST(0x18c)
+#define APS_AST_REGION_4_MASK_HI_0_SECURE                       0x0
+#define APS_AST_REGION_4_MASK_HI_0_DUAL                         0x0
+#define APS_AST_REGION_4_MASK_HI_0_SCR                  AST_REG_4_SEC_CONTROL_0
+#define APS_AST_REGION_4_MASK_HI_0_SCRREG                       APS_AST_SCR_AST_REG_4_SEC_CONTROL_0
+#define APS_AST_REGION_4_MASK_HI_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_4_MASK_HI_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASK_HI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_4_MASK_HI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASK_HI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASK_HI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_4_MASK_HI_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_4_MASK_HI_0_Mask_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_4_MASK_HI_0_Mask_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_REGION_4_MASK_HI_0_Mask_SHIFT)
+#define APS_AST_REGION_4_MASK_HI_0_Mask_RANGE                   31:0
+#define APS_AST_REGION_4_MASK_HI_0_Mask_MSB                     MK_SHIFT_CONST(31)
+#define APS_AST_REGION_4_MASK_HI_0_Mask_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_4_MASK_HI_0_Mask_WOFFSET                 0x0
+#define APS_AST_REGION_4_MASK_HI_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASK_HI_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_4_MASK_HI_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASK_HI_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASK_HI_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASK_HI_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_4_MASTER_BASE_LO_0
+#define APS_AST_REGION_4_MASTER_BASE_LO_0                       MK_ADDR_CONST(0x190)
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_SECURE                        0x0
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_DUAL                  0x0
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_SCR                   AST_REG_4_SEC_CONTROL_0
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_SCRREG                        APS_AST_SCR_AST_REG_4_SEC_CONTROL_0
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_WORD_COUNT                    0x1
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_RESET_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_READ_MASK                     MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_WRITE_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_SHIFT                        MK_SHIFT_CONST(12)
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_FIELD                        MK_FIELD_CONST(0xfffff, APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_SHIFT)
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_RANGE                        31:12
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_MSB                  MK_SHIFT_CONST(31)
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_LSB                  MK_SHIFT_CONST(12)
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_WOFFSET                      0x0
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASTER_BASE_LO_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_4_MASTER_BASE_HI_0
+#define APS_AST_REGION_4_MASTER_BASE_HI_0                       MK_ADDR_CONST(0x194)
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_SECURE                        0x0
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_DUAL                  0x0
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_SCR                   AST_REG_4_SEC_CONTROL_0
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_SCRREG                        APS_AST_SCR_AST_REG_4_SEC_CONTROL_0
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_WORD_COUNT                    0x1
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_SHIFT                        MK_SHIFT_CONST(0)
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_FIELD                        MK_FIELD_CONST(0xffffffff, APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_SHIFT)
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_RANGE                        31:0
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_MSB                  MK_SHIFT_CONST(31)
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_LSB                  MK_SHIFT_CONST(0)
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_WOFFSET                      0x0
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_MASTER_BASE_HI_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_4_CONTROL_0
+#define APS_AST_REGION_4_CONTROL_0                      MK_ADDR_CONST(0x198)
+#define APS_AST_REGION_4_CONTROL_0_SECURE                       0x0
+#define APS_AST_REGION_4_CONTROL_0_DUAL                         0x0
+#define APS_AST_REGION_4_CONTROL_0_SCR                  AST_REG_4_SEC_CONTROL_0
+#define APS_AST_REGION_4_CONTROL_0_SCRREG                       APS_AST_SCR_AST_REG_4_SEC_CONTROL_0
+#define APS_AST_REGION_4_CONTROL_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_4_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_4_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_READ_MASK                    MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_4_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_4_CONTROL_0_Physical_SHIFT                       MK_SHIFT_CONST(19)
+#define APS_AST_REGION_4_CONTROL_0_Physical_FIELD                       MK_FIELD_CONST(0x1, APS_AST_REGION_4_CONTROL_0_Physical_SHIFT)
+#define APS_AST_REGION_4_CONTROL_0_Physical_RANGE                       19:19
+#define APS_AST_REGION_4_CONTROL_0_Physical_MSB                 MK_SHIFT_CONST(19)
+#define APS_AST_REGION_4_CONTROL_0_Physical_LSB                 MK_SHIFT_CONST(19)
+#define APS_AST_REGION_4_CONTROL_0_Physical_WOFFSET                     0x0
+#define APS_AST_REGION_4_CONTROL_0_Physical_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_Physical_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define APS_AST_REGION_4_CONTROL_0_Physical_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_Physical_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_Physical_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_Physical_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_4_CONTROL_0_VMIndex_SHIFT                        MK_SHIFT_CONST(15)
+#define APS_AST_REGION_4_CONTROL_0_VMIndex_FIELD                        MK_FIELD_CONST(0xf, APS_AST_REGION_4_CONTROL_0_VMIndex_SHIFT)
+#define APS_AST_REGION_4_CONTROL_0_VMIndex_RANGE                        18:15
+#define APS_AST_REGION_4_CONTROL_0_VMIndex_MSB                  MK_SHIFT_CONST(18)
+#define APS_AST_REGION_4_CONTROL_0_VMIndex_LSB                  MK_SHIFT_CONST(15)
+#define APS_AST_REGION_4_CONTROL_0_VMIndex_WOFFSET                      0x0
+#define APS_AST_REGION_4_CONTROL_0_VMIndex_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_VMIndex_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define APS_AST_REGION_4_CONTROL_0_VMIndex_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_VMIndex_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_VMIndex_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_VMIndex_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_4_CONTROL_0_CarveOutID_SHIFT                     MK_SHIFT_CONST(5)
+#define APS_AST_REGION_4_CONTROL_0_CarveOutID_FIELD                     MK_FIELD_CONST(0x1f, APS_AST_REGION_4_CONTROL_0_CarveOutID_SHIFT)
+#define APS_AST_REGION_4_CONTROL_0_CarveOutID_RANGE                     9:5
+#define APS_AST_REGION_4_CONTROL_0_CarveOutID_MSB                       MK_SHIFT_CONST(9)
+#define APS_AST_REGION_4_CONTROL_0_CarveOutID_LSB                       MK_SHIFT_CONST(5)
+#define APS_AST_REGION_4_CONTROL_0_CarveOutID_WOFFSET                   0x0
+#define APS_AST_REGION_4_CONTROL_0_CarveOutID_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_CarveOutID_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
+#define APS_AST_REGION_4_CONTROL_0_CarveOutID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_CarveOutID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_CarveOutID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_CarveOutID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_4_CONTROL_0_Snoop_SHIFT                  MK_SHIFT_CONST(2)
+#define APS_AST_REGION_4_CONTROL_0_Snoop_FIELD                  MK_FIELD_CONST(0x1, APS_AST_REGION_4_CONTROL_0_Snoop_SHIFT)
+#define APS_AST_REGION_4_CONTROL_0_Snoop_RANGE                  2:2
+#define APS_AST_REGION_4_CONTROL_0_Snoop_MSB                    MK_SHIFT_CONST(2)
+#define APS_AST_REGION_4_CONTROL_0_Snoop_LSB                    MK_SHIFT_CONST(2)
+#define APS_AST_REGION_4_CONTROL_0_Snoop_WOFFSET                        0x0
+#define APS_AST_REGION_4_CONTROL_0_Snoop_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_Snoop_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define APS_AST_REGION_4_CONTROL_0_Snoop_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_Snoop_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_Snoop_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_Snoop_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define APS_AST_REGION_4_CONTROL_0_Snoop_DISABLE                        MK_ENUM_CONST(0)
+#define APS_AST_REGION_4_CONTROL_0_Snoop_ENABLE                 MK_ENUM_CONST(1)
+
+#define APS_AST_REGION_4_CONTROL_0_Lock_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_4_CONTROL_0_Lock_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_4_CONTROL_0_Lock_SHIFT)
+#define APS_AST_REGION_4_CONTROL_0_Lock_RANGE                   0:0
+#define APS_AST_REGION_4_CONTROL_0_Lock_MSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_4_CONTROL_0_Lock_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_4_CONTROL_0_Lock_WOFFSET                 0x0
+#define APS_AST_REGION_4_CONTROL_0_Lock_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_Lock_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_AST_REGION_4_CONTROL_0_Lock_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_Lock_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_Lock_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_4_CONTROL_0_Lock_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define APS_AST_REGION_4_CONTROL_0_Lock_FALSE                   MK_ENUM_CONST(0)
+#define APS_AST_REGION_4_CONTROL_0_Lock_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_REGION_5_SLAVE_BASE_LO_0
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0                        MK_ADDR_CONST(0x1a0)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SECURE                         0x0
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_DUAL                   0x0
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SCR                    AST_REG_5_SEC_CONTROL_0
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SCRREG                         APS_AST_SCR_AST_REG_5_SEC_CONTROL_0
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_WORD_COUNT                     0x1
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_RESET_MASK                     MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_READ_MASK                      MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_WRITE_MASK                     MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_SHIFT                  MK_SHIFT_CONST(12)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_FIELD                  MK_FIELD_CONST(0xfffff, APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_SHIFT)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_RANGE                  31:12
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_LSB                    MK_SHIFT_CONST(12)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_WOFFSET                        0x0
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_SHIFT)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_RANGE                   0:0
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_MSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_WOFFSET                 0x0
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_FALSE                   MK_ENUM_CONST(0)
+#define APS_AST_REGION_5_SLAVE_BASE_LO_0_Enable_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_REGION_5_SLAVE_BASE_HI_0
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0                        MK_ADDR_CONST(0x1a4)
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SECURE                         0x0
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_DUAL                   0x0
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SCR                    AST_REG_5_SEC_CONTROL_0
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SCRREG                         APS_AST_SCR_AST_REG_5_SEC_CONTROL_0
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_WORD_COUNT                     0x1
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_SHIFT                  MK_SHIFT_CONST(0)
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_FIELD                  MK_FIELD_CONST(0xffffffff, APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_SHIFT)
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_RANGE                  31:0
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_LSB                    MK_SHIFT_CONST(0)
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_WOFFSET                        0x0
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_SLAVE_BASE_HI_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_5_MASK_LO_0
+#define APS_AST_REGION_5_MASK_LO_0                      MK_ADDR_CONST(0x1a8)
+#define APS_AST_REGION_5_MASK_LO_0_SECURE                       0x0
+#define APS_AST_REGION_5_MASK_LO_0_DUAL                         0x0
+#define APS_AST_REGION_5_MASK_LO_0_SCR                  AST_REG_5_SEC_CONTROL_0
+#define APS_AST_REGION_5_MASK_LO_0_SCRREG                       APS_AST_SCR_AST_REG_5_SEC_CONTROL_0
+#define APS_AST_REGION_5_MASK_LO_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_5_MASK_LO_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASK_LO_0_RESET_MASK                   MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_5_MASK_LO_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASK_LO_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASK_LO_0_READ_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_5_MASK_LO_0_WRITE_MASK                   MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_5_MASK_LO_0_Mask_SHIFT                   MK_SHIFT_CONST(12)
+#define APS_AST_REGION_5_MASK_LO_0_Mask_FIELD                   MK_FIELD_CONST(0xfffff, APS_AST_REGION_5_MASK_LO_0_Mask_SHIFT)
+#define APS_AST_REGION_5_MASK_LO_0_Mask_RANGE                   31:12
+#define APS_AST_REGION_5_MASK_LO_0_Mask_MSB                     MK_SHIFT_CONST(31)
+#define APS_AST_REGION_5_MASK_LO_0_Mask_LSB                     MK_SHIFT_CONST(12)
+#define APS_AST_REGION_5_MASK_LO_0_Mask_WOFFSET                 0x0
+#define APS_AST_REGION_5_MASK_LO_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASK_LO_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_5_MASK_LO_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASK_LO_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASK_LO_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASK_LO_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_5_MASK_HI_0
+#define APS_AST_REGION_5_MASK_HI_0                      MK_ADDR_CONST(0x1ac)
+#define APS_AST_REGION_5_MASK_HI_0_SECURE                       0x0
+#define APS_AST_REGION_5_MASK_HI_0_DUAL                         0x0
+#define APS_AST_REGION_5_MASK_HI_0_SCR                  AST_REG_5_SEC_CONTROL_0
+#define APS_AST_REGION_5_MASK_HI_0_SCRREG                       APS_AST_SCR_AST_REG_5_SEC_CONTROL_0
+#define APS_AST_REGION_5_MASK_HI_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_5_MASK_HI_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASK_HI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_5_MASK_HI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASK_HI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASK_HI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_5_MASK_HI_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_5_MASK_HI_0_Mask_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_5_MASK_HI_0_Mask_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_REGION_5_MASK_HI_0_Mask_SHIFT)
+#define APS_AST_REGION_5_MASK_HI_0_Mask_RANGE                   31:0
+#define APS_AST_REGION_5_MASK_HI_0_Mask_MSB                     MK_SHIFT_CONST(31)
+#define APS_AST_REGION_5_MASK_HI_0_Mask_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_5_MASK_HI_0_Mask_WOFFSET                 0x0
+#define APS_AST_REGION_5_MASK_HI_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASK_HI_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_5_MASK_HI_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASK_HI_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASK_HI_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASK_HI_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_5_MASTER_BASE_LO_0
+#define APS_AST_REGION_5_MASTER_BASE_LO_0                       MK_ADDR_CONST(0x1b0)
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_SECURE                        0x0
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_DUAL                  0x0
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_SCR                   AST_REG_5_SEC_CONTROL_0
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_SCRREG                        APS_AST_SCR_AST_REG_5_SEC_CONTROL_0
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_WORD_COUNT                    0x1
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_RESET_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_READ_MASK                     MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_WRITE_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_SHIFT                        MK_SHIFT_CONST(12)
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_FIELD                        MK_FIELD_CONST(0xfffff, APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_SHIFT)
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_RANGE                        31:12
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_MSB                  MK_SHIFT_CONST(31)
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_LSB                  MK_SHIFT_CONST(12)
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_WOFFSET                      0x0
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASTER_BASE_LO_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_5_MASTER_BASE_HI_0
+#define APS_AST_REGION_5_MASTER_BASE_HI_0                       MK_ADDR_CONST(0x1b4)
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_SECURE                        0x0
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_DUAL                  0x0
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_SCR                   AST_REG_5_SEC_CONTROL_0
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_SCRREG                        APS_AST_SCR_AST_REG_5_SEC_CONTROL_0
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_WORD_COUNT                    0x1
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_SHIFT                        MK_SHIFT_CONST(0)
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_FIELD                        MK_FIELD_CONST(0xffffffff, APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_SHIFT)
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_RANGE                        31:0
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_MSB                  MK_SHIFT_CONST(31)
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_LSB                  MK_SHIFT_CONST(0)
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_WOFFSET                      0x0
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_MASTER_BASE_HI_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_5_CONTROL_0
+#define APS_AST_REGION_5_CONTROL_0                      MK_ADDR_CONST(0x1b8)
+#define APS_AST_REGION_5_CONTROL_0_SECURE                       0x0
+#define APS_AST_REGION_5_CONTROL_0_DUAL                         0x0
+#define APS_AST_REGION_5_CONTROL_0_SCR                  AST_REG_5_SEC_CONTROL_0
+#define APS_AST_REGION_5_CONTROL_0_SCRREG                       APS_AST_SCR_AST_REG_5_SEC_CONTROL_0
+#define APS_AST_REGION_5_CONTROL_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_5_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_5_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_READ_MASK                    MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_5_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_5_CONTROL_0_Physical_SHIFT                       MK_SHIFT_CONST(19)
+#define APS_AST_REGION_5_CONTROL_0_Physical_FIELD                       MK_FIELD_CONST(0x1, APS_AST_REGION_5_CONTROL_0_Physical_SHIFT)
+#define APS_AST_REGION_5_CONTROL_0_Physical_RANGE                       19:19
+#define APS_AST_REGION_5_CONTROL_0_Physical_MSB                 MK_SHIFT_CONST(19)
+#define APS_AST_REGION_5_CONTROL_0_Physical_LSB                 MK_SHIFT_CONST(19)
+#define APS_AST_REGION_5_CONTROL_0_Physical_WOFFSET                     0x0
+#define APS_AST_REGION_5_CONTROL_0_Physical_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_Physical_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define APS_AST_REGION_5_CONTROL_0_Physical_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_Physical_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_Physical_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_Physical_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_5_CONTROL_0_VMIndex_SHIFT                        MK_SHIFT_CONST(15)
+#define APS_AST_REGION_5_CONTROL_0_VMIndex_FIELD                        MK_FIELD_CONST(0xf, APS_AST_REGION_5_CONTROL_0_VMIndex_SHIFT)
+#define APS_AST_REGION_5_CONTROL_0_VMIndex_RANGE                        18:15
+#define APS_AST_REGION_5_CONTROL_0_VMIndex_MSB                  MK_SHIFT_CONST(18)
+#define APS_AST_REGION_5_CONTROL_0_VMIndex_LSB                  MK_SHIFT_CONST(15)
+#define APS_AST_REGION_5_CONTROL_0_VMIndex_WOFFSET                      0x0
+#define APS_AST_REGION_5_CONTROL_0_VMIndex_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_VMIndex_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define APS_AST_REGION_5_CONTROL_0_VMIndex_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_VMIndex_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_VMIndex_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_VMIndex_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_5_CONTROL_0_CarveOutID_SHIFT                     MK_SHIFT_CONST(5)
+#define APS_AST_REGION_5_CONTROL_0_CarveOutID_FIELD                     MK_FIELD_CONST(0x1f, APS_AST_REGION_5_CONTROL_0_CarveOutID_SHIFT)
+#define APS_AST_REGION_5_CONTROL_0_CarveOutID_RANGE                     9:5
+#define APS_AST_REGION_5_CONTROL_0_CarveOutID_MSB                       MK_SHIFT_CONST(9)
+#define APS_AST_REGION_5_CONTROL_0_CarveOutID_LSB                       MK_SHIFT_CONST(5)
+#define APS_AST_REGION_5_CONTROL_0_CarveOutID_WOFFSET                   0x0
+#define APS_AST_REGION_5_CONTROL_0_CarveOutID_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_CarveOutID_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
+#define APS_AST_REGION_5_CONTROL_0_CarveOutID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_CarveOutID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_CarveOutID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_CarveOutID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_5_CONTROL_0_Snoop_SHIFT                  MK_SHIFT_CONST(2)
+#define APS_AST_REGION_5_CONTROL_0_Snoop_FIELD                  MK_FIELD_CONST(0x1, APS_AST_REGION_5_CONTROL_0_Snoop_SHIFT)
+#define APS_AST_REGION_5_CONTROL_0_Snoop_RANGE                  2:2
+#define APS_AST_REGION_5_CONTROL_0_Snoop_MSB                    MK_SHIFT_CONST(2)
+#define APS_AST_REGION_5_CONTROL_0_Snoop_LSB                    MK_SHIFT_CONST(2)
+#define APS_AST_REGION_5_CONTROL_0_Snoop_WOFFSET                        0x0
+#define APS_AST_REGION_5_CONTROL_0_Snoop_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_Snoop_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define APS_AST_REGION_5_CONTROL_0_Snoop_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_Snoop_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_Snoop_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_Snoop_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define APS_AST_REGION_5_CONTROL_0_Snoop_DISABLE                        MK_ENUM_CONST(0)
+#define APS_AST_REGION_5_CONTROL_0_Snoop_ENABLE                 MK_ENUM_CONST(1)
+
+#define APS_AST_REGION_5_CONTROL_0_Lock_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_5_CONTROL_0_Lock_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_5_CONTROL_0_Lock_SHIFT)
+#define APS_AST_REGION_5_CONTROL_0_Lock_RANGE                   0:0
+#define APS_AST_REGION_5_CONTROL_0_Lock_MSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_5_CONTROL_0_Lock_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_5_CONTROL_0_Lock_WOFFSET                 0x0
+#define APS_AST_REGION_5_CONTROL_0_Lock_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_Lock_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_AST_REGION_5_CONTROL_0_Lock_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_Lock_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_Lock_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_5_CONTROL_0_Lock_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define APS_AST_REGION_5_CONTROL_0_Lock_FALSE                   MK_ENUM_CONST(0)
+#define APS_AST_REGION_5_CONTROL_0_Lock_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_REGION_6_SLAVE_BASE_LO_0
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0                        MK_ADDR_CONST(0x1c0)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SECURE                         0x0
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_DUAL                   0x0
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SCR                    AST_REG_6_SEC_CONTROL_0
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SCRREG                         APS_AST_SCR_AST_REG_6_SEC_CONTROL_0
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_WORD_COUNT                     0x1
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_RESET_MASK                     MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_READ_MASK                      MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_WRITE_MASK                     MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_SHIFT                  MK_SHIFT_CONST(12)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_FIELD                  MK_FIELD_CONST(0xfffff, APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_SHIFT)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_RANGE                  31:12
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_LSB                    MK_SHIFT_CONST(12)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_WOFFSET                        0x0
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_SHIFT)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_RANGE                   0:0
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_MSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_WOFFSET                 0x0
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_FALSE                   MK_ENUM_CONST(0)
+#define APS_AST_REGION_6_SLAVE_BASE_LO_0_Enable_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_REGION_6_SLAVE_BASE_HI_0
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0                        MK_ADDR_CONST(0x1c4)
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SECURE                         0x0
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_DUAL                   0x0
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SCR                    AST_REG_6_SEC_CONTROL_0
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SCRREG                         APS_AST_SCR_AST_REG_6_SEC_CONTROL_0
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_WORD_COUNT                     0x1
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_SHIFT                  MK_SHIFT_CONST(0)
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_FIELD                  MK_FIELD_CONST(0xffffffff, APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_SHIFT)
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_RANGE                  31:0
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_LSB                    MK_SHIFT_CONST(0)
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_WOFFSET                        0x0
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_SLAVE_BASE_HI_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_6_MASK_LO_0
+#define APS_AST_REGION_6_MASK_LO_0                      MK_ADDR_CONST(0x1c8)
+#define APS_AST_REGION_6_MASK_LO_0_SECURE                       0x0
+#define APS_AST_REGION_6_MASK_LO_0_DUAL                         0x0
+#define APS_AST_REGION_6_MASK_LO_0_SCR                  AST_REG_6_SEC_CONTROL_0
+#define APS_AST_REGION_6_MASK_LO_0_SCRREG                       APS_AST_SCR_AST_REG_6_SEC_CONTROL_0
+#define APS_AST_REGION_6_MASK_LO_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_6_MASK_LO_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASK_LO_0_RESET_MASK                   MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_6_MASK_LO_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASK_LO_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASK_LO_0_READ_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_6_MASK_LO_0_WRITE_MASK                   MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_6_MASK_LO_0_Mask_SHIFT                   MK_SHIFT_CONST(12)
+#define APS_AST_REGION_6_MASK_LO_0_Mask_FIELD                   MK_FIELD_CONST(0xfffff, APS_AST_REGION_6_MASK_LO_0_Mask_SHIFT)
+#define APS_AST_REGION_6_MASK_LO_0_Mask_RANGE                   31:12
+#define APS_AST_REGION_6_MASK_LO_0_Mask_MSB                     MK_SHIFT_CONST(31)
+#define APS_AST_REGION_6_MASK_LO_0_Mask_LSB                     MK_SHIFT_CONST(12)
+#define APS_AST_REGION_6_MASK_LO_0_Mask_WOFFSET                 0x0
+#define APS_AST_REGION_6_MASK_LO_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASK_LO_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_6_MASK_LO_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASK_LO_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASK_LO_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASK_LO_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_6_MASK_HI_0
+#define APS_AST_REGION_6_MASK_HI_0                      MK_ADDR_CONST(0x1cc)
+#define APS_AST_REGION_6_MASK_HI_0_SECURE                       0x0
+#define APS_AST_REGION_6_MASK_HI_0_DUAL                         0x0
+#define APS_AST_REGION_6_MASK_HI_0_SCR                  AST_REG_6_SEC_CONTROL_0
+#define APS_AST_REGION_6_MASK_HI_0_SCRREG                       APS_AST_SCR_AST_REG_6_SEC_CONTROL_0
+#define APS_AST_REGION_6_MASK_HI_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_6_MASK_HI_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASK_HI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_6_MASK_HI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASK_HI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASK_HI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_6_MASK_HI_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_6_MASK_HI_0_Mask_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_6_MASK_HI_0_Mask_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_REGION_6_MASK_HI_0_Mask_SHIFT)
+#define APS_AST_REGION_6_MASK_HI_0_Mask_RANGE                   31:0
+#define APS_AST_REGION_6_MASK_HI_0_Mask_MSB                     MK_SHIFT_CONST(31)
+#define APS_AST_REGION_6_MASK_HI_0_Mask_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_6_MASK_HI_0_Mask_WOFFSET                 0x0
+#define APS_AST_REGION_6_MASK_HI_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASK_HI_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_6_MASK_HI_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASK_HI_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASK_HI_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASK_HI_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_6_MASTER_BASE_LO_0
+#define APS_AST_REGION_6_MASTER_BASE_LO_0                       MK_ADDR_CONST(0x1d0)
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_SECURE                        0x0
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_DUAL                  0x0
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_SCR                   AST_REG_6_SEC_CONTROL_0
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_SCRREG                        APS_AST_SCR_AST_REG_6_SEC_CONTROL_0
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_WORD_COUNT                    0x1
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_RESET_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_READ_MASK                     MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_WRITE_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_SHIFT                        MK_SHIFT_CONST(12)
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_FIELD                        MK_FIELD_CONST(0xfffff, APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_SHIFT)
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_RANGE                        31:12
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_MSB                  MK_SHIFT_CONST(31)
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_LSB                  MK_SHIFT_CONST(12)
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_WOFFSET                      0x0
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASTER_BASE_LO_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_6_MASTER_BASE_HI_0
+#define APS_AST_REGION_6_MASTER_BASE_HI_0                       MK_ADDR_CONST(0x1d4)
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_SECURE                        0x0
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_DUAL                  0x0
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_SCR                   AST_REG_6_SEC_CONTROL_0
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_SCRREG                        APS_AST_SCR_AST_REG_6_SEC_CONTROL_0
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_WORD_COUNT                    0x1
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_SHIFT                        MK_SHIFT_CONST(0)
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_FIELD                        MK_FIELD_CONST(0xffffffff, APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_SHIFT)
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_RANGE                        31:0
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_MSB                  MK_SHIFT_CONST(31)
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_LSB                  MK_SHIFT_CONST(0)
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_WOFFSET                      0x0
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_MASTER_BASE_HI_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_6_CONTROL_0
+#define APS_AST_REGION_6_CONTROL_0                      MK_ADDR_CONST(0x1d8)
+#define APS_AST_REGION_6_CONTROL_0_SECURE                       0x0
+#define APS_AST_REGION_6_CONTROL_0_DUAL                         0x0
+#define APS_AST_REGION_6_CONTROL_0_SCR                  AST_REG_6_SEC_CONTROL_0
+#define APS_AST_REGION_6_CONTROL_0_SCRREG                       APS_AST_SCR_AST_REG_6_SEC_CONTROL_0
+#define APS_AST_REGION_6_CONTROL_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_6_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_6_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_READ_MASK                    MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_6_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_6_CONTROL_0_Physical_SHIFT                       MK_SHIFT_CONST(19)
+#define APS_AST_REGION_6_CONTROL_0_Physical_FIELD                       MK_FIELD_CONST(0x1, APS_AST_REGION_6_CONTROL_0_Physical_SHIFT)
+#define APS_AST_REGION_6_CONTROL_0_Physical_RANGE                       19:19
+#define APS_AST_REGION_6_CONTROL_0_Physical_MSB                 MK_SHIFT_CONST(19)
+#define APS_AST_REGION_6_CONTROL_0_Physical_LSB                 MK_SHIFT_CONST(19)
+#define APS_AST_REGION_6_CONTROL_0_Physical_WOFFSET                     0x0
+#define APS_AST_REGION_6_CONTROL_0_Physical_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_Physical_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define APS_AST_REGION_6_CONTROL_0_Physical_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_Physical_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_Physical_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_Physical_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_6_CONTROL_0_VMIndex_SHIFT                        MK_SHIFT_CONST(15)
+#define APS_AST_REGION_6_CONTROL_0_VMIndex_FIELD                        MK_FIELD_CONST(0xf, APS_AST_REGION_6_CONTROL_0_VMIndex_SHIFT)
+#define APS_AST_REGION_6_CONTROL_0_VMIndex_RANGE                        18:15
+#define APS_AST_REGION_6_CONTROL_0_VMIndex_MSB                  MK_SHIFT_CONST(18)
+#define APS_AST_REGION_6_CONTROL_0_VMIndex_LSB                  MK_SHIFT_CONST(15)
+#define APS_AST_REGION_6_CONTROL_0_VMIndex_WOFFSET                      0x0
+#define APS_AST_REGION_6_CONTROL_0_VMIndex_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_VMIndex_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define APS_AST_REGION_6_CONTROL_0_VMIndex_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_VMIndex_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_VMIndex_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_VMIndex_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_6_CONTROL_0_CarveOutID_SHIFT                     MK_SHIFT_CONST(5)
+#define APS_AST_REGION_6_CONTROL_0_CarveOutID_FIELD                     MK_FIELD_CONST(0x1f, APS_AST_REGION_6_CONTROL_0_CarveOutID_SHIFT)
+#define APS_AST_REGION_6_CONTROL_0_CarveOutID_RANGE                     9:5
+#define APS_AST_REGION_6_CONTROL_0_CarveOutID_MSB                       MK_SHIFT_CONST(9)
+#define APS_AST_REGION_6_CONTROL_0_CarveOutID_LSB                       MK_SHIFT_CONST(5)
+#define APS_AST_REGION_6_CONTROL_0_CarveOutID_WOFFSET                   0x0
+#define APS_AST_REGION_6_CONTROL_0_CarveOutID_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_CarveOutID_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
+#define APS_AST_REGION_6_CONTROL_0_CarveOutID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_CarveOutID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_CarveOutID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_CarveOutID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_6_CONTROL_0_Snoop_SHIFT                  MK_SHIFT_CONST(2)
+#define APS_AST_REGION_6_CONTROL_0_Snoop_FIELD                  MK_FIELD_CONST(0x1, APS_AST_REGION_6_CONTROL_0_Snoop_SHIFT)
+#define APS_AST_REGION_6_CONTROL_0_Snoop_RANGE                  2:2
+#define APS_AST_REGION_6_CONTROL_0_Snoop_MSB                    MK_SHIFT_CONST(2)
+#define APS_AST_REGION_6_CONTROL_0_Snoop_LSB                    MK_SHIFT_CONST(2)
+#define APS_AST_REGION_6_CONTROL_0_Snoop_WOFFSET                        0x0
+#define APS_AST_REGION_6_CONTROL_0_Snoop_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_Snoop_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define APS_AST_REGION_6_CONTROL_0_Snoop_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_Snoop_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_Snoop_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_Snoop_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define APS_AST_REGION_6_CONTROL_0_Snoop_DISABLE                        MK_ENUM_CONST(0)
+#define APS_AST_REGION_6_CONTROL_0_Snoop_ENABLE                 MK_ENUM_CONST(1)
+
+#define APS_AST_REGION_6_CONTROL_0_Lock_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_6_CONTROL_0_Lock_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_6_CONTROL_0_Lock_SHIFT)
+#define APS_AST_REGION_6_CONTROL_0_Lock_RANGE                   0:0
+#define APS_AST_REGION_6_CONTROL_0_Lock_MSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_6_CONTROL_0_Lock_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_6_CONTROL_0_Lock_WOFFSET                 0x0
+#define APS_AST_REGION_6_CONTROL_0_Lock_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_Lock_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_AST_REGION_6_CONTROL_0_Lock_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_Lock_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_Lock_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_6_CONTROL_0_Lock_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define APS_AST_REGION_6_CONTROL_0_Lock_FALSE                   MK_ENUM_CONST(0)
+#define APS_AST_REGION_6_CONTROL_0_Lock_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_REGION_7_SLAVE_BASE_LO_0
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0                        MK_ADDR_CONST(0x1e0)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SECURE                         0x0
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_DUAL                   0x0
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SCR                    AST_REG_7_SEC_CONTROL_0
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SCRREG                         APS_AST_SCR_AST_REG_7_SEC_CONTROL_0
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_WORD_COUNT                     0x1
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_RESET_MASK                     MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_READ_MASK                      MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_WRITE_MASK                     MK_MASK_CONST(0xfffff001)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_SHIFT                  MK_SHIFT_CONST(12)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_FIELD                  MK_FIELD_CONST(0xfffff, APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_SHIFT)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_RANGE                  31:12
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_LSB                    MK_SHIFT_CONST(12)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_WOFFSET                        0x0
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_SHIFT)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_RANGE                   0:0
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_MSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_WOFFSET                 0x0
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_FALSE                   MK_ENUM_CONST(0)
+#define APS_AST_REGION_7_SLAVE_BASE_LO_0_Enable_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register APS_AST_REGION_7_SLAVE_BASE_HI_0
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0                        MK_ADDR_CONST(0x1e4)
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SECURE                         0x0
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_DUAL                   0x0
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SCR                    AST_REG_7_SEC_CONTROL_0
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SCRREG                         APS_AST_SCR_AST_REG_7_SEC_CONTROL_0
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_WORD_COUNT                     0x1
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_SHIFT                  MK_SHIFT_CONST(0)
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_FIELD                  MK_FIELD_CONST(0xffffffff, APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_SHIFT)
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_RANGE                  31:0
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_MSB                    MK_SHIFT_CONST(31)
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_LSB                    MK_SHIFT_CONST(0)
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_WOFFSET                        0x0
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_SLAVE_BASE_HI_0_SlvBase_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_7_MASK_LO_0
+#define APS_AST_REGION_7_MASK_LO_0                      MK_ADDR_CONST(0x1e8)
+#define APS_AST_REGION_7_MASK_LO_0_SECURE                       0x0
+#define APS_AST_REGION_7_MASK_LO_0_DUAL                         0x0
+#define APS_AST_REGION_7_MASK_LO_0_SCR                  AST_REG_7_SEC_CONTROL_0
+#define APS_AST_REGION_7_MASK_LO_0_SCRREG                       APS_AST_SCR_AST_REG_7_SEC_CONTROL_0
+#define APS_AST_REGION_7_MASK_LO_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_7_MASK_LO_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASK_LO_0_RESET_MASK                   MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_7_MASK_LO_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASK_LO_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASK_LO_0_READ_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_7_MASK_LO_0_WRITE_MASK                   MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_7_MASK_LO_0_Mask_SHIFT                   MK_SHIFT_CONST(12)
+#define APS_AST_REGION_7_MASK_LO_0_Mask_FIELD                   MK_FIELD_CONST(0xfffff, APS_AST_REGION_7_MASK_LO_0_Mask_SHIFT)
+#define APS_AST_REGION_7_MASK_LO_0_Mask_RANGE                   31:12
+#define APS_AST_REGION_7_MASK_LO_0_Mask_MSB                     MK_SHIFT_CONST(31)
+#define APS_AST_REGION_7_MASK_LO_0_Mask_LSB                     MK_SHIFT_CONST(12)
+#define APS_AST_REGION_7_MASK_LO_0_Mask_WOFFSET                 0x0
+#define APS_AST_REGION_7_MASK_LO_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASK_LO_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_7_MASK_LO_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASK_LO_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASK_LO_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASK_LO_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_7_MASK_HI_0
+#define APS_AST_REGION_7_MASK_HI_0                      MK_ADDR_CONST(0x1ec)
+#define APS_AST_REGION_7_MASK_HI_0_SECURE                       0x0
+#define APS_AST_REGION_7_MASK_HI_0_DUAL                         0x0
+#define APS_AST_REGION_7_MASK_HI_0_SCR                  AST_REG_7_SEC_CONTROL_0
+#define APS_AST_REGION_7_MASK_HI_0_SCRREG                       APS_AST_SCR_AST_REG_7_SEC_CONTROL_0
+#define APS_AST_REGION_7_MASK_HI_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_7_MASK_HI_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASK_HI_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_7_MASK_HI_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASK_HI_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASK_HI_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_7_MASK_HI_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_7_MASK_HI_0_Mask_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_7_MASK_HI_0_Mask_FIELD                   MK_FIELD_CONST(0xffffffff, APS_AST_REGION_7_MASK_HI_0_Mask_SHIFT)
+#define APS_AST_REGION_7_MASK_HI_0_Mask_RANGE                   31:0
+#define APS_AST_REGION_7_MASK_HI_0_Mask_MSB                     MK_SHIFT_CONST(31)
+#define APS_AST_REGION_7_MASK_HI_0_Mask_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_7_MASK_HI_0_Mask_WOFFSET                 0x0
+#define APS_AST_REGION_7_MASK_HI_0_Mask_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASK_HI_0_Mask_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_7_MASK_HI_0_Mask_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASK_HI_0_Mask_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASK_HI_0_Mask_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASK_HI_0_Mask_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_7_MASTER_BASE_LO_0
+#define APS_AST_REGION_7_MASTER_BASE_LO_0                       MK_ADDR_CONST(0x1f0)
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_SECURE                        0x0
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_DUAL                  0x0
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_SCR                   AST_REG_7_SEC_CONTROL_0
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_SCRREG                        APS_AST_SCR_AST_REG_7_SEC_CONTROL_0
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_WORD_COUNT                    0x1
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_RESET_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_READ_MASK                     MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_WRITE_MASK                    MK_MASK_CONST(0xfffff000)
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_SHIFT                        MK_SHIFT_CONST(12)
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_FIELD                        MK_FIELD_CONST(0xfffff, APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_SHIFT)
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_RANGE                        31:12
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_MSB                  MK_SHIFT_CONST(31)
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_LSB                  MK_SHIFT_CONST(12)
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_WOFFSET                      0x0
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xfffff)
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASTER_BASE_LO_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_7_MASTER_BASE_HI_0
+#define APS_AST_REGION_7_MASTER_BASE_HI_0                       MK_ADDR_CONST(0x1f4)
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_SECURE                        0x0
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_DUAL                  0x0
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_SCR                   AST_REG_7_SEC_CONTROL_0
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_SCRREG                        APS_AST_SCR_AST_REG_7_SEC_CONTROL_0
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_WORD_COUNT                    0x1
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_SHIFT                        MK_SHIFT_CONST(0)
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_FIELD                        MK_FIELD_CONST(0xffffffff, APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_SHIFT)
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_RANGE                        31:0
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_MSB                  MK_SHIFT_CONST(31)
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_LSB                  MK_SHIFT_CONST(0)
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_WOFFSET                      0x0
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_MASTER_BASE_HI_0_MastBase_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register APS_AST_REGION_7_CONTROL_0
+#define APS_AST_REGION_7_CONTROL_0                      MK_ADDR_CONST(0x1f8)
+#define APS_AST_REGION_7_CONTROL_0_SECURE                       0x0
+#define APS_AST_REGION_7_CONTROL_0_DUAL                         0x0
+#define APS_AST_REGION_7_CONTROL_0_SCR                  AST_REG_7_SEC_CONTROL_0
+#define APS_AST_REGION_7_CONTROL_0_SCRREG                       APS_AST_SCR_AST_REG_7_SEC_CONTROL_0
+#define APS_AST_REGION_7_CONTROL_0_WORD_COUNT                   0x1
+#define APS_AST_REGION_7_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_7_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_READ_MASK                    MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_7_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0xf83e5)
+#define APS_AST_REGION_7_CONTROL_0_Physical_SHIFT                       MK_SHIFT_CONST(19)
+#define APS_AST_REGION_7_CONTROL_0_Physical_FIELD                       MK_FIELD_CONST(0x1, APS_AST_REGION_7_CONTROL_0_Physical_SHIFT)
+#define APS_AST_REGION_7_CONTROL_0_Physical_RANGE                       19:19
+#define APS_AST_REGION_7_CONTROL_0_Physical_MSB                 MK_SHIFT_CONST(19)
+#define APS_AST_REGION_7_CONTROL_0_Physical_LSB                 MK_SHIFT_CONST(19)
+#define APS_AST_REGION_7_CONTROL_0_Physical_WOFFSET                     0x0
+#define APS_AST_REGION_7_CONTROL_0_Physical_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_Physical_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define APS_AST_REGION_7_CONTROL_0_Physical_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_Physical_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_Physical_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_Physical_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_7_CONTROL_0_VMIndex_SHIFT                        MK_SHIFT_CONST(15)
+#define APS_AST_REGION_7_CONTROL_0_VMIndex_FIELD                        MK_FIELD_CONST(0xf, APS_AST_REGION_7_CONTROL_0_VMIndex_SHIFT)
+#define APS_AST_REGION_7_CONTROL_0_VMIndex_RANGE                        18:15
+#define APS_AST_REGION_7_CONTROL_0_VMIndex_MSB                  MK_SHIFT_CONST(18)
+#define APS_AST_REGION_7_CONTROL_0_VMIndex_LSB                  MK_SHIFT_CONST(15)
+#define APS_AST_REGION_7_CONTROL_0_VMIndex_WOFFSET                      0x0
+#define APS_AST_REGION_7_CONTROL_0_VMIndex_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_VMIndex_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define APS_AST_REGION_7_CONTROL_0_VMIndex_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_VMIndex_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_VMIndex_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_VMIndex_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_7_CONTROL_0_CarveOutID_SHIFT                     MK_SHIFT_CONST(5)
+#define APS_AST_REGION_7_CONTROL_0_CarveOutID_FIELD                     MK_FIELD_CONST(0x1f, APS_AST_REGION_7_CONTROL_0_CarveOutID_SHIFT)
+#define APS_AST_REGION_7_CONTROL_0_CarveOutID_RANGE                     9:5
+#define APS_AST_REGION_7_CONTROL_0_CarveOutID_MSB                       MK_SHIFT_CONST(9)
+#define APS_AST_REGION_7_CONTROL_0_CarveOutID_LSB                       MK_SHIFT_CONST(5)
+#define APS_AST_REGION_7_CONTROL_0_CarveOutID_WOFFSET                   0x0
+#define APS_AST_REGION_7_CONTROL_0_CarveOutID_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_CarveOutID_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
+#define APS_AST_REGION_7_CONTROL_0_CarveOutID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_CarveOutID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_CarveOutID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_CarveOutID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define APS_AST_REGION_7_CONTROL_0_Snoop_SHIFT                  MK_SHIFT_CONST(2)
+#define APS_AST_REGION_7_CONTROL_0_Snoop_FIELD                  MK_FIELD_CONST(0x1, APS_AST_REGION_7_CONTROL_0_Snoop_SHIFT)
+#define APS_AST_REGION_7_CONTROL_0_Snoop_RANGE                  2:2
+#define APS_AST_REGION_7_CONTROL_0_Snoop_MSB                    MK_SHIFT_CONST(2)
+#define APS_AST_REGION_7_CONTROL_0_Snoop_LSB                    MK_SHIFT_CONST(2)
+#define APS_AST_REGION_7_CONTROL_0_Snoop_WOFFSET                        0x0
+#define APS_AST_REGION_7_CONTROL_0_Snoop_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_Snoop_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define APS_AST_REGION_7_CONTROL_0_Snoop_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_Snoop_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_Snoop_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_Snoop_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define APS_AST_REGION_7_CONTROL_0_Snoop_DISABLE                        MK_ENUM_CONST(0)
+#define APS_AST_REGION_7_CONTROL_0_Snoop_ENABLE                 MK_ENUM_CONST(1)
+
+#define APS_AST_REGION_7_CONTROL_0_Lock_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_AST_REGION_7_CONTROL_0_Lock_FIELD                   MK_FIELD_CONST(0x1, APS_AST_REGION_7_CONTROL_0_Lock_SHIFT)
+#define APS_AST_REGION_7_CONTROL_0_Lock_RANGE                   0:0
+#define APS_AST_REGION_7_CONTROL_0_Lock_MSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_7_CONTROL_0_Lock_LSB                     MK_SHIFT_CONST(0)
+#define APS_AST_REGION_7_CONTROL_0_Lock_WOFFSET                 0x0
+#define APS_AST_REGION_7_CONTROL_0_Lock_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_Lock_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_AST_REGION_7_CONTROL_0_Lock_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_Lock_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_Lock_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_AST_REGION_7_CONTROL_0_Lock_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define APS_AST_REGION_7_CONTROL_0_Lock_FALSE                   MK_ENUM_CONST(0)
+#define APS_AST_REGION_7_CONTROL_0_Lock_TRUE                    MK_ENUM_CONST(1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPS_AST_REGS(_op_) \
+_op_(APS_AST_CONTROL_0) \
+_op_(APS_AST_ERROR_STATUS_0) \
+_op_(APS_AST_ERROR_ADDR_LO_0) \
+_op_(APS_AST_ERROR_ADDR_HI_0) \
+_op_(APS_AST_STREAMID_CTL_0) \
+_op_(APS_AST_STREAMID_CTL) \
+_op_(APS_AST_STREAMID_CTL_1) \
+_op_(APS_AST_STREAMID_CTL_2) \
+_op_(APS_AST_STREAMID_CTL_3) \
+_op_(APS_AST_STREAMID_CTL_4) \
+_op_(APS_AST_STREAMID_CTL_5) \
+_op_(APS_AST_STREAMID_CTL_6) \
+_op_(APS_AST_STREAMID_CTL_7) \
+_op_(APS_AST_STREAMID_CTL_8) \
+_op_(APS_AST_STREAMID_CTL_9) \
+_op_(APS_AST_STREAMID_CTL_10) \
+_op_(APS_AST_STREAMID_CTL_11) \
+_op_(APS_AST_STREAMID_CTL_12) \
+_op_(APS_AST_STREAMID_CTL_13) \
+_op_(APS_AST_STREAMID_CTL_14) \
+_op_(APS_AST_STREAMID_CTL_15) \
+_op_(APS_AST_WRITE_BLOCK_STATUS_0) \
+_op_(APS_AST_READ_BLOCK_STATUS_0) \
+_op_(APS_AST_REGION_0_SLAVE_BASE_LO_0) \
+_op_(APS_AST_REGION_0_SLAVE_BASE_HI_0) \
+_op_(APS_AST_REGION_0_MASK_LO_0) \
+_op_(APS_AST_REGION_0_MASK_HI_0) \
+_op_(APS_AST_REGION_0_MASTER_BASE_LO_0) \
+_op_(APS_AST_REGION_0_MASTER_BASE_HI_0) \
+_op_(APS_AST_REGION_0_CONTROL_0) \
+_op_(APS_AST_REGION_1_SLAVE_BASE_LO_0) \
+_op_(APS_AST_REGION_1_SLAVE_BASE_HI_0) \
+_op_(APS_AST_REGION_1_MASK_LO_0) \
+_op_(APS_AST_REGION_1_MASK_HI_0) \
+_op_(APS_AST_REGION_1_MASTER_BASE_LO_0) \
+_op_(APS_AST_REGION_1_MASTER_BASE_HI_0) \
+_op_(APS_AST_REGION_1_CONTROL_0) \
+_op_(APS_AST_REGION_2_SLAVE_BASE_LO_0) \
+_op_(APS_AST_REGION_2_SLAVE_BASE_HI_0) \
+_op_(APS_AST_REGION_2_MASK_LO_0) \
+_op_(APS_AST_REGION_2_MASK_HI_0) \
+_op_(APS_AST_REGION_2_MASTER_BASE_LO_0) \
+_op_(APS_AST_REGION_2_MASTER_BASE_HI_0) \
+_op_(APS_AST_REGION_2_CONTROL_0) \
+_op_(APS_AST_REGION_3_SLAVE_BASE_LO_0) \
+_op_(APS_AST_REGION_3_SLAVE_BASE_HI_0) \
+_op_(APS_AST_REGION_3_MASK_LO_0) \
+_op_(APS_AST_REGION_3_MASK_HI_0) \
+_op_(APS_AST_REGION_3_MASTER_BASE_LO_0) \
+_op_(APS_AST_REGION_3_MASTER_BASE_HI_0) \
+_op_(APS_AST_REGION_3_CONTROL_0) \
+_op_(APS_AST_REGION_4_SLAVE_BASE_LO_0) \
+_op_(APS_AST_REGION_4_SLAVE_BASE_HI_0) \
+_op_(APS_AST_REGION_4_MASK_LO_0) \
+_op_(APS_AST_REGION_4_MASK_HI_0) \
+_op_(APS_AST_REGION_4_MASTER_BASE_LO_0) \
+_op_(APS_AST_REGION_4_MASTER_BASE_HI_0) \
+_op_(APS_AST_REGION_4_CONTROL_0) \
+_op_(APS_AST_REGION_5_SLAVE_BASE_LO_0) \
+_op_(APS_AST_REGION_5_SLAVE_BASE_HI_0) \
+_op_(APS_AST_REGION_5_MASK_LO_0) \
+_op_(APS_AST_REGION_5_MASK_HI_0) \
+_op_(APS_AST_REGION_5_MASTER_BASE_LO_0) \
+_op_(APS_AST_REGION_5_MASTER_BASE_HI_0) \
+_op_(APS_AST_REGION_5_CONTROL_0) \
+_op_(APS_AST_REGION_6_SLAVE_BASE_LO_0) \
+_op_(APS_AST_REGION_6_SLAVE_BASE_HI_0) \
+_op_(APS_AST_REGION_6_MASK_LO_0) \
+_op_(APS_AST_REGION_6_MASK_HI_0) \
+_op_(APS_AST_REGION_6_MASTER_BASE_LO_0) \
+_op_(APS_AST_REGION_6_MASTER_BASE_HI_0) \
+_op_(APS_AST_REGION_6_CONTROL_0) \
+_op_(APS_AST_REGION_7_SLAVE_BASE_LO_0) \
+_op_(APS_AST_REGION_7_SLAVE_BASE_HI_0) \
+_op_(APS_AST_REGION_7_MASK_LO_0) \
+_op_(APS_AST_REGION_7_MASK_HI_0) \
+_op_(APS_AST_REGION_7_MASTER_BASE_LO_0) \
+_op_(APS_AST_REGION_7_MASTER_BASE_HI_0) \
+_op_(APS_AST_REGION_7_CONTROL_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APS_AST    0x00000000
+
+//
+// ARAPS_AST REGISTER BANKS
+//
+
+#define APS_AST0_FIRST_REG 0x0000 // APS_AST_CONTROL_0
+#define APS_AST0_LAST_REG 0x000c // APS_AST_ERROR_ADDR_HI_0
+#define APS_AST1_FIRST_REG 0x0020 // APS_AST_STREAMID_CTL_0
+#define APS_AST1_LAST_REG 0x0064 // APS_AST_READ_BLOCK_STATUS_0
+#define APS_AST2_FIRST_REG 0x0100 // APS_AST_REGION_0_SLAVE_BASE_LO_0
+#define APS_AST2_LAST_REG 0x0118 // APS_AST_REGION_0_CONTROL_0
+#define APS_AST3_FIRST_REG 0x0120 // APS_AST_REGION_1_SLAVE_BASE_LO_0
+#define APS_AST3_LAST_REG 0x0138 // APS_AST_REGION_1_CONTROL_0
+#define APS_AST4_FIRST_REG 0x0140 // APS_AST_REGION_2_SLAVE_BASE_LO_0
+#define APS_AST4_LAST_REG 0x0158 // APS_AST_REGION_2_CONTROL_0
+#define APS_AST5_FIRST_REG 0x0160 // APS_AST_REGION_3_SLAVE_BASE_LO_0
+#define APS_AST5_LAST_REG 0x0178 // APS_AST_REGION_3_CONTROL_0
+#define APS_AST6_FIRST_REG 0x0180 // APS_AST_REGION_4_SLAVE_BASE_LO_0
+#define APS_AST6_LAST_REG 0x0198 // APS_AST_REGION_4_CONTROL_0
+#define APS_AST7_FIRST_REG 0x01a0 // APS_AST_REGION_5_SLAVE_BASE_LO_0
+#define APS_AST7_LAST_REG 0x01b8 // APS_AST_REGION_5_CONTROL_0
+#define APS_AST8_FIRST_REG 0x01c0 // APS_AST_REGION_6_SLAVE_BASE_LO_0
+#define APS_AST8_LAST_REG 0x01d8 // APS_AST_REGION_6_CONTROL_0
+#define APS_AST9_FIRST_REG 0x01e0 // APS_AST_REGION_7_SLAVE_BASE_LO_0
+#define APS_AST9_LAST_REG 0x01f8 // APS_AST_REGION_7_CONTROL_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARAPS_AST_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/araps_vic.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/araps_vic.h
new file mode 100644
index 0000000..4458a02
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/araps_vic.h
@@ -0,0 +1,4624 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARAPS_VIC_H_INC
+#define ARAPS_VIC_H_INC
+#define NV_MOBILE_ARAPS_VIC_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARAPS_VIC_H_SCRREG_NOMENCLATURE INFERRED
+
+
+// Register APS_VIC_VICIRQSTATUS_0
+#define APS_VIC_VICIRQSTATUS_0                  MK_ADDR_CONST(0x0)
+#define APS_VIC_VICIRQSTATUS_0_SECURE                   0x0
+#define APS_VIC_VICIRQSTATUS_0_DUAL                     0x0
+#define APS_VIC_VICIRQSTATUS_0_SCR                      0
+#define APS_VIC_VICIRQSTATUS_0_SCRREG                   0
+#define APS_VIC_VICIRQSTATUS_0_WORD_COUNT                       0x1
+#define APS_VIC_VICIRQSTATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICIRQSTATUS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICIRQSTATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICIRQSTATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICIRQSTATUS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICIRQSTATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_SHIFT)
+#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_RANGE                       31:0
+#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_MSB                 MK_SHIFT_CONST(31)
+#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_WOFFSET                     0x0
+#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICIRQSTATUS_0_VICIRQSTATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICFIQSTATUS_0
+#define APS_VIC_VICFIQSTATUS_0                  MK_ADDR_CONST(0x4)
+#define APS_VIC_VICFIQSTATUS_0_SECURE                   0x0
+#define APS_VIC_VICFIQSTATUS_0_DUAL                     0x0
+#define APS_VIC_VICFIQSTATUS_0_SCR                      0
+#define APS_VIC_VICFIQSTATUS_0_SCRREG                   0
+#define APS_VIC_VICFIQSTATUS_0_WORD_COUNT                       0x1
+#define APS_VIC_VICFIQSTATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICFIQSTATUS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICFIQSTATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICFIQSTATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICFIQSTATUS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICFIQSTATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_SHIFT)
+#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_RANGE                       31:0
+#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_MSB                 MK_SHIFT_CONST(31)
+#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_WOFFSET                     0x0
+#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICFIQSTATUS_0_VICFIQSTATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICRAWINTR_0
+#define APS_VIC_VICRAWINTR_0                    MK_ADDR_CONST(0x8)
+#define APS_VIC_VICRAWINTR_0_SECURE                     0x0
+#define APS_VIC_VICRAWINTR_0_DUAL                       0x0
+#define APS_VIC_VICRAWINTR_0_SCR                        0
+#define APS_VIC_VICRAWINTR_0_SCRREG                     0
+#define APS_VIC_VICRAWINTR_0_WORD_COUNT                         0x1
+#define APS_VIC_VICRAWINTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICRAWINTR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICRAWINTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICRAWINTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICRAWINTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICRAWINTR_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICRAWINTR_0_VICRAWINTR_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_VIC_VICRAWINTR_0_VICRAWINTR_FIELD                   MK_FIELD_CONST(0xffffffff, APS_VIC_VICRAWINTR_0_VICRAWINTR_SHIFT)
+#define APS_VIC_VICRAWINTR_0_VICRAWINTR_RANGE                   31:0
+#define APS_VIC_VICRAWINTR_0_VICRAWINTR_MSB                     MK_SHIFT_CONST(31)
+#define APS_VIC_VICRAWINTR_0_VICRAWINTR_LSB                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICRAWINTR_0_VICRAWINTR_WOFFSET                 0x0
+#define APS_VIC_VICRAWINTR_0_VICRAWINTR_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICRAWINTR_0_VICRAWINTR_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICRAWINTR_0_VICRAWINTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICRAWINTR_0_VICRAWINTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICRAWINTR_0_VICRAWINTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICRAWINTR_0_VICRAWINTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICINTSELECT_0
+#define APS_VIC_VICINTSELECT_0                  MK_ADDR_CONST(0xc)
+#define APS_VIC_VICINTSELECT_0_SECURE                   0x0
+#define APS_VIC_VICINTSELECT_0_DUAL                     0x0
+#define APS_VIC_VICINTSELECT_0_SCR                      0
+#define APS_VIC_VICINTSELECT_0_SCRREG                   0
+#define APS_VIC_VICINTSELECT_0_WORD_COUNT                       0x1
+#define APS_VIC_VICINTSELECT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSELECT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICINTSELECT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSELECT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSELECT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICINTSELECT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICINTSELECT_0_VICINTSELECT_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICINTSELECT_0_VICINTSELECT_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICINTSELECT_0_VICINTSELECT_SHIFT)
+#define APS_VIC_VICINTSELECT_0_VICINTSELECT_RANGE                       31:0
+#define APS_VIC_VICINTSELECT_0_VICINTSELECT_MSB                 MK_SHIFT_CONST(31)
+#define APS_VIC_VICINTSELECT_0_VICINTSELECT_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICINTSELECT_0_VICINTSELECT_WOFFSET                     0x0
+#define APS_VIC_VICINTSELECT_0_VICINTSELECT_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSELECT_0_VICINTSELECT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICINTSELECT_0_VICINTSELECT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSELECT_0_VICINTSELECT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSELECT_0_VICINTSELECT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSELECT_0_VICINTSELECT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICINTENABLE_0
+#define APS_VIC_VICINTENABLE_0                  MK_ADDR_CONST(0x10)
+#define APS_VIC_VICINTENABLE_0_SECURE                   0x0
+#define APS_VIC_VICINTENABLE_0_DUAL                     0x0
+#define APS_VIC_VICINTENABLE_0_SCR                      0
+#define APS_VIC_VICINTENABLE_0_SCRREG                   0
+#define APS_VIC_VICINTENABLE_0_WORD_COUNT                       0x1
+#define APS_VIC_VICINTENABLE_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTENABLE_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICINTENABLE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTENABLE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTENABLE_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICINTENABLE_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICINTENABLE_0_VICINTENABLE_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICINTENABLE_0_VICINTENABLE_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICINTENABLE_0_VICINTENABLE_SHIFT)
+#define APS_VIC_VICINTENABLE_0_VICINTENABLE_RANGE                       31:0
+#define APS_VIC_VICINTENABLE_0_VICINTENABLE_MSB                 MK_SHIFT_CONST(31)
+#define APS_VIC_VICINTENABLE_0_VICINTENABLE_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICINTENABLE_0_VICINTENABLE_WOFFSET                     0x0
+#define APS_VIC_VICINTENABLE_0_VICINTENABLE_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTENABLE_0_VICINTENABLE_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICINTENABLE_0_VICINTENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTENABLE_0_VICINTENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTENABLE_0_VICINTENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTENABLE_0_VICINTENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICINTENCLEAR_0
+#define APS_VIC_VICINTENCLEAR_0                 MK_ADDR_CONST(0x14)
+#define APS_VIC_VICINTENCLEAR_0_SECURE                  0x0
+#define APS_VIC_VICINTENCLEAR_0_DUAL                    0x0
+#define APS_VIC_VICINTENCLEAR_0_SCR                     0
+#define APS_VIC_VICINTENCLEAR_0_SCRREG                  0
+#define APS_VIC_VICINTENCLEAR_0_WORD_COUNT                      0x1
+#define APS_VIC_VICINTENCLEAR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTENCLEAR_0_RESET_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTENCLEAR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTENCLEAR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTENCLEAR_0_READ_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTENCLEAR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_SHIFT)
+#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_RANGE                     31:0
+#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_WOFFSET                   0x0
+#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTENCLEAR_0_VICINTENCLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICSOFTINT_0
+#define APS_VIC_VICSOFTINT_0                    MK_ADDR_CONST(0x18)
+#define APS_VIC_VICSOFTINT_0_SECURE                     0x0
+#define APS_VIC_VICSOFTINT_0_DUAL                       0x0
+#define APS_VIC_VICSOFTINT_0_SCR                        0
+#define APS_VIC_VICSOFTINT_0_SCRREG                     0
+#define APS_VIC_VICSOFTINT_0_WORD_COUNT                         0x1
+#define APS_VIC_VICSOFTINT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICSOFTINT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICSOFTINT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICSOFTINT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICSOFTINT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICSOFTINT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICSOFTINT_0_VICSOFTINT_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_VIC_VICSOFTINT_0_VICSOFTINT_FIELD                   MK_FIELD_CONST(0xffffffff, APS_VIC_VICSOFTINT_0_VICSOFTINT_SHIFT)
+#define APS_VIC_VICSOFTINT_0_VICSOFTINT_RANGE                   31:0
+#define APS_VIC_VICSOFTINT_0_VICSOFTINT_MSB                     MK_SHIFT_CONST(31)
+#define APS_VIC_VICSOFTINT_0_VICSOFTINT_LSB                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICSOFTINT_0_VICSOFTINT_WOFFSET                 0x0
+#define APS_VIC_VICSOFTINT_0_VICSOFTINT_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICSOFTINT_0_VICSOFTINT_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICSOFTINT_0_VICSOFTINT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICSOFTINT_0_VICSOFTINT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICSOFTINT_0_VICSOFTINT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICSOFTINT_0_VICSOFTINT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICSOFTINTCLEAR_0
+#define APS_VIC_VICSOFTINTCLEAR_0                       MK_ADDR_CONST(0x1c)
+#define APS_VIC_VICSOFTINTCLEAR_0_SECURE                        0x0
+#define APS_VIC_VICSOFTINTCLEAR_0_DUAL                  0x0
+#define APS_VIC_VICSOFTINTCLEAR_0_SCR                   0
+#define APS_VIC_VICSOFTINTCLEAR_0_SCRREG                        0
+#define APS_VIC_VICSOFTINTCLEAR_0_WORD_COUNT                    0x1
+#define APS_VIC_VICSOFTINTCLEAR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICSOFTINTCLEAR_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICSOFTINTCLEAR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICSOFTINTCLEAR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICSOFTINTCLEAR_0_READ_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICSOFTINTCLEAR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_FIELD                 MK_FIELD_CONST(0xffffffff, APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_SHIFT)
+#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_RANGE                 31:0
+#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_MSB                   MK_SHIFT_CONST(31)
+#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_LSB                   MK_SHIFT_CONST(0)
+#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_WOFFSET                       0x0
+#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICSOFTINTCLEAR_0_VICSOFTINTCLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICPROTECTION_0
+#define APS_VIC_VICPROTECTION_0                 MK_ADDR_CONST(0x20)
+#define APS_VIC_VICPROTECTION_0_SECURE                  0x0
+#define APS_VIC_VICPROTECTION_0_DUAL                    0x0
+#define APS_VIC_VICPROTECTION_0_SCR                     0
+#define APS_VIC_VICPROTECTION_0_SCRREG                  0
+#define APS_VIC_VICPROTECTION_0_WORD_COUNT                      0x1
+#define APS_VIC_VICPROTECTION_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICPROTECTION_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define APS_VIC_VICPROTECTION_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICPROTECTION_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICPROTECTION_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define APS_VIC_VICPROTECTION_0_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define APS_VIC_VICPROTECTION_0_VICPROTECTION_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICPROTECTION_0_VICPROTECTION_FIELD                     MK_FIELD_CONST(0x1, APS_VIC_VICPROTECTION_0_VICPROTECTION_SHIFT)
+#define APS_VIC_VICPROTECTION_0_VICPROTECTION_RANGE                     0:0
+#define APS_VIC_VICPROTECTION_0_VICPROTECTION_MSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICPROTECTION_0_VICPROTECTION_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICPROTECTION_0_VICPROTECTION_WOFFSET                   0x0
+#define APS_VIC_VICPROTECTION_0_VICPROTECTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICPROTECTION_0_VICPROTECTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define APS_VIC_VICPROTECTION_0_VICPROTECTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICPROTECTION_0_VICPROTECTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICPROTECTION_0_VICPROTECTION_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICPROTECTION_0_VICPROTECTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define APS_VIC_VICPROTECTION_0_VICPROTECTION__PROD                     MK_ENUM_CONST(1)
+
+
+// Register APS_VIC_VICSWPRIORITY_0
+#define APS_VIC_VICSWPRIORITY_0                 MK_ADDR_CONST(0x24)
+#define APS_VIC_VICSWPRIORITY_0_SECURE                  0x0
+#define APS_VIC_VICSWPRIORITY_0_DUAL                    0x0
+#define APS_VIC_VICSWPRIORITY_0_SCR                     0
+#define APS_VIC_VICSWPRIORITY_0_SCRREG                  0
+#define APS_VIC_VICSWPRIORITY_0_WORD_COUNT                      0x1
+#define APS_VIC_VICSWPRIORITY_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define APS_VIC_VICSWPRIORITY_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define APS_VIC_VICSWPRIORITY_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICSWPRIORITY_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICSWPRIORITY_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define APS_VIC_VICSWPRIORITY_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_FIELD                     MK_FIELD_CONST(0xffff, APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_SHIFT)
+#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_RANGE                     15:0
+#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_MSB                       MK_SHIFT_CONST(15)
+#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_WOFFSET                   0x0
+#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_DEFAULT                   MK_MASK_CONST(0xffff)
+#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICSWPRIORITY_0_VICSWPRIORITY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICPRIORITYDAISY_0
+#define APS_VIC_VICPRIORITYDAISY_0                      MK_ADDR_CONST(0x28)
+#define APS_VIC_VICPRIORITYDAISY_0_SECURE                       0x0
+#define APS_VIC_VICPRIORITYDAISY_0_DUAL                         0x0
+#define APS_VIC_VICPRIORITYDAISY_0_SCR                  0
+#define APS_VIC_VICPRIORITYDAISY_0_SCRREG                       0
+#define APS_VIC_VICPRIORITYDAISY_0_WORD_COUNT                   0x1
+#define APS_VIC_VICPRIORITYDAISY_0_RESET_VAL                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICPRIORITYDAISY_0_RESET_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICPRIORITYDAISY_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICPRIORITYDAISY_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICPRIORITYDAISY_0_READ_MASK                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICPRIORITYDAISY_0_WRITE_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_SHIFT)
+#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_RANGE                       3:0
+#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_MSB                 MK_SHIFT_CONST(3)
+#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_WOFFSET                     0x0
+#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_DEFAULT                     MK_MASK_CONST(0xf)
+#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICPRIORITYDAISY_0_VICPRIORITYDAISY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x2c
+
+// Reserved address 0x30
+
+// Reserved address 0x34
+
+// Reserved address 0x38
+
+// Reserved address 0x3c
+
+// Reserved address 0x40
+
+// Reserved address 0x44
+
+// Reserved address 0x48
+
+// Reserved address 0x4c
+
+// Reserved address 0x50
+
+// Reserved address 0x54
+
+// Reserved address 0x58
+
+// Reserved address 0x5c
+
+// Reserved address 0x60
+
+// Reserved address 0x64
+
+// Reserved address 0x68
+
+// Reserved address 0x6c
+
+// Reserved address 0x70
+
+// Reserved address 0x74
+
+// Reserved address 0x78
+
+// Reserved address 0x7c
+
+// Reserved address 0x80
+
+// Reserved address 0x84
+
+// Reserved address 0x88
+
+// Reserved address 0x8c
+
+// Reserved address 0x90
+
+// Reserved address 0x94
+
+// Reserved address 0x98
+
+// Reserved address 0x9c
+
+// Reserved address 0xa0
+
+// Reserved address 0xa4
+
+// Reserved address 0xa8
+
+// Reserved address 0xac
+
+// Reserved address 0xb0
+
+// Reserved address 0xb4
+
+// Reserved address 0xb8
+
+// Reserved address 0xbc
+
+// Reserved address 0xc0
+
+// Reserved address 0xc4
+
+// Reserved address 0xc8
+
+// Reserved address 0xcc
+
+// Reserved address 0xd0
+
+// Reserved address 0xd4
+
+// Reserved address 0xd8
+
+// Reserved address 0xdc
+
+// Reserved address 0xe0
+
+// Reserved address 0xe4
+
+// Reserved address 0xe8
+
+// Reserved address 0xec
+
+// Reserved address 0xf0
+
+// Reserved address 0xf4
+
+// Reserved address 0xf8
+
+// Reserved address 0xfc
+
+// Register APS_VIC_VICVECTADDR0_0
+#define APS_VIC_VICVECTADDR0_0                  MK_ADDR_CONST(0x100)
+#define APS_VIC_VICVECTADDR0_0_SECURE                   0x0
+#define APS_VIC_VICVECTADDR0_0_DUAL                     0x0
+#define APS_VIC_VICVECTADDR0_0_SCR                      0
+#define APS_VIC_VICVECTADDR0_0_SCRREG                   0
+#define APS_VIC_VICVECTADDR0_0_WORD_COUNT                       0x1
+#define APS_VIC_VICVECTADDR0_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR0_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR0_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR0_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR0_0_VICVECTADDR0_SHIFT)
+#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_RANGE                       31:0
+#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_MSB                 MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_WOFFSET                     0x0
+#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR0_0_VICVECTADDR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR1_0
+#define APS_VIC_VICVECTADDR1_0                  MK_ADDR_CONST(0x104)
+#define APS_VIC_VICVECTADDR1_0_SECURE                   0x0
+#define APS_VIC_VICVECTADDR1_0_DUAL                     0x0
+#define APS_VIC_VICVECTADDR1_0_SCR                      0
+#define APS_VIC_VICVECTADDR1_0_SCRREG                   0
+#define APS_VIC_VICVECTADDR1_0_WORD_COUNT                       0x1
+#define APS_VIC_VICVECTADDR1_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR1_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR1_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR1_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR1_0_VICVECTADDR1_SHIFT)
+#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_RANGE                       31:0
+#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_MSB                 MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_WOFFSET                     0x0
+#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR1_0_VICVECTADDR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR2_0
+#define APS_VIC_VICVECTADDR2_0                  MK_ADDR_CONST(0x108)
+#define APS_VIC_VICVECTADDR2_0_SECURE                   0x0
+#define APS_VIC_VICVECTADDR2_0_DUAL                     0x0
+#define APS_VIC_VICVECTADDR2_0_SCR                      0
+#define APS_VIC_VICVECTADDR2_0_SCRREG                   0
+#define APS_VIC_VICVECTADDR2_0_WORD_COUNT                       0x1
+#define APS_VIC_VICVECTADDR2_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR2_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR2_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR2_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR2_0_VICVECTADDR2_SHIFT)
+#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_RANGE                       31:0
+#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_MSB                 MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_WOFFSET                     0x0
+#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR2_0_VICVECTADDR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR3_0
+#define APS_VIC_VICVECTADDR3_0                  MK_ADDR_CONST(0x10c)
+#define APS_VIC_VICVECTADDR3_0_SECURE                   0x0
+#define APS_VIC_VICVECTADDR3_0_DUAL                     0x0
+#define APS_VIC_VICVECTADDR3_0_SCR                      0
+#define APS_VIC_VICVECTADDR3_0_SCRREG                   0
+#define APS_VIC_VICVECTADDR3_0_WORD_COUNT                       0x1
+#define APS_VIC_VICVECTADDR3_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR3_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR3_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR3_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR3_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR3_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR3_0_VICVECTADDR3_SHIFT)
+#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_RANGE                       31:0
+#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_MSB                 MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_WOFFSET                     0x0
+#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR3_0_VICVECTADDR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR4_0
+#define APS_VIC_VICVECTADDR4_0                  MK_ADDR_CONST(0x110)
+#define APS_VIC_VICVECTADDR4_0_SECURE                   0x0
+#define APS_VIC_VICVECTADDR4_0_DUAL                     0x0
+#define APS_VIC_VICVECTADDR4_0_SCR                      0
+#define APS_VIC_VICVECTADDR4_0_SCRREG                   0
+#define APS_VIC_VICVECTADDR4_0_WORD_COUNT                       0x1
+#define APS_VIC_VICVECTADDR4_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR4_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR4_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR4_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR4_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR4_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR4_0_VICVECTADDR4_SHIFT)
+#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_RANGE                       31:0
+#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_MSB                 MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_WOFFSET                     0x0
+#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR4_0_VICVECTADDR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR5_0
+#define APS_VIC_VICVECTADDR5_0                  MK_ADDR_CONST(0x114)
+#define APS_VIC_VICVECTADDR5_0_SECURE                   0x0
+#define APS_VIC_VICVECTADDR5_0_DUAL                     0x0
+#define APS_VIC_VICVECTADDR5_0_SCR                      0
+#define APS_VIC_VICVECTADDR5_0_SCRREG                   0
+#define APS_VIC_VICVECTADDR5_0_WORD_COUNT                       0x1
+#define APS_VIC_VICVECTADDR5_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR5_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR5_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR5_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR5_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR5_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR5_0_VICVECTADDR5_SHIFT)
+#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_RANGE                       31:0
+#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_MSB                 MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_WOFFSET                     0x0
+#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR5_0_VICVECTADDR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR6_0
+#define APS_VIC_VICVECTADDR6_0                  MK_ADDR_CONST(0x118)
+#define APS_VIC_VICVECTADDR6_0_SECURE                   0x0
+#define APS_VIC_VICVECTADDR6_0_DUAL                     0x0
+#define APS_VIC_VICVECTADDR6_0_SCR                      0
+#define APS_VIC_VICVECTADDR6_0_SCRREG                   0
+#define APS_VIC_VICVECTADDR6_0_WORD_COUNT                       0x1
+#define APS_VIC_VICVECTADDR6_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR6_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR6_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR6_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR6_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR6_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR6_0_VICVECTADDR6_SHIFT)
+#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_RANGE                       31:0
+#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_MSB                 MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_WOFFSET                     0x0
+#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR6_0_VICVECTADDR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR7_0
+#define APS_VIC_VICVECTADDR7_0                  MK_ADDR_CONST(0x11c)
+#define APS_VIC_VICVECTADDR7_0_SECURE                   0x0
+#define APS_VIC_VICVECTADDR7_0_DUAL                     0x0
+#define APS_VIC_VICVECTADDR7_0_SCR                      0
+#define APS_VIC_VICVECTADDR7_0_SCRREG                   0
+#define APS_VIC_VICVECTADDR7_0_WORD_COUNT                       0x1
+#define APS_VIC_VICVECTADDR7_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR7_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR7_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR7_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR7_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR7_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR7_0_VICVECTADDR7_SHIFT)
+#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_RANGE                       31:0
+#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_MSB                 MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_WOFFSET                     0x0
+#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR7_0_VICVECTADDR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR8_0
+#define APS_VIC_VICVECTADDR8_0                  MK_ADDR_CONST(0x120)
+#define APS_VIC_VICVECTADDR8_0_SECURE                   0x0
+#define APS_VIC_VICVECTADDR8_0_DUAL                     0x0
+#define APS_VIC_VICVECTADDR8_0_SCR                      0
+#define APS_VIC_VICVECTADDR8_0_SCRREG                   0
+#define APS_VIC_VICVECTADDR8_0_WORD_COUNT                       0x1
+#define APS_VIC_VICVECTADDR8_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR8_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR8_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR8_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR8_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR8_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR8_0_VICVECTADDR8_SHIFT)
+#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_RANGE                       31:0
+#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_MSB                 MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_WOFFSET                     0x0
+#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR8_0_VICVECTADDR8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR9_0
+#define APS_VIC_VICVECTADDR9_0                  MK_ADDR_CONST(0x124)
+#define APS_VIC_VICVECTADDR9_0_SECURE                   0x0
+#define APS_VIC_VICVECTADDR9_0_DUAL                     0x0
+#define APS_VIC_VICVECTADDR9_0_SCR                      0
+#define APS_VIC_VICVECTADDR9_0_SCRREG                   0
+#define APS_VIC_VICVECTADDR9_0_WORD_COUNT                       0x1
+#define APS_VIC_VICVECTADDR9_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR9_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR9_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR9_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR9_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR9_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_FIELD                       MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR9_0_VICVECTADDR9_SHIFT)
+#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_RANGE                       31:0
+#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_MSB                 MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_WOFFSET                     0x0
+#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR9_0_VICVECTADDR9_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR10_0
+#define APS_VIC_VICVECTADDR10_0                 MK_ADDR_CONST(0x128)
+#define APS_VIC_VICVECTADDR10_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR10_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR10_0_SCR                     0
+#define APS_VIC_VICVECTADDR10_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR10_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR10_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR10_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR10_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR10_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR10_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR10_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR10_0_VICVECTADDR10_SHIFT)
+#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_RANGE                     31:0
+#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR10_0_VICVECTADDR10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR11_0
+#define APS_VIC_VICVECTADDR11_0                 MK_ADDR_CONST(0x12c)
+#define APS_VIC_VICVECTADDR11_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR11_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR11_0_SCR                     0
+#define APS_VIC_VICVECTADDR11_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR11_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR11_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR11_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR11_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR11_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR11_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR11_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR11_0_VICVECTADDR11_SHIFT)
+#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_RANGE                     31:0
+#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR11_0_VICVECTADDR11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR12_0
+#define APS_VIC_VICVECTADDR12_0                 MK_ADDR_CONST(0x130)
+#define APS_VIC_VICVECTADDR12_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR12_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR12_0_SCR                     0
+#define APS_VIC_VICVECTADDR12_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR12_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR12_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR12_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR12_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR12_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR12_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR12_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR12_0_VICVECTADDR12_SHIFT)
+#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_RANGE                     31:0
+#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR12_0_VICVECTADDR12_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR13_0
+#define APS_VIC_VICVECTADDR13_0                 MK_ADDR_CONST(0x134)
+#define APS_VIC_VICVECTADDR13_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR13_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR13_0_SCR                     0
+#define APS_VIC_VICVECTADDR13_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR13_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR13_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR13_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR13_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR13_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR13_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR13_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR13_0_VICVECTADDR13_SHIFT)
+#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_RANGE                     31:0
+#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR13_0_VICVECTADDR13_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR14_0
+#define APS_VIC_VICVECTADDR14_0                 MK_ADDR_CONST(0x138)
+#define APS_VIC_VICVECTADDR14_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR14_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR14_0_SCR                     0
+#define APS_VIC_VICVECTADDR14_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR14_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR14_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR14_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR14_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR14_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR14_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR14_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR14_0_VICVECTADDR14_SHIFT)
+#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_RANGE                     31:0
+#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR14_0_VICVECTADDR14_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR15_0
+#define APS_VIC_VICVECTADDR15_0                 MK_ADDR_CONST(0x13c)
+#define APS_VIC_VICVECTADDR15_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR15_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR15_0_SCR                     0
+#define APS_VIC_VICVECTADDR15_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR15_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR15_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR15_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR15_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR15_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR15_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR15_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR15_0_VICVECTADDR15_SHIFT)
+#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_RANGE                     31:0
+#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR15_0_VICVECTADDR15_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR16_0
+#define APS_VIC_VICVECTADDR16_0                 MK_ADDR_CONST(0x140)
+#define APS_VIC_VICVECTADDR16_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR16_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR16_0_SCR                     0
+#define APS_VIC_VICVECTADDR16_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR16_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR16_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR16_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR16_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR16_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR16_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR16_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR16_0_VICVECTADDR16_SHIFT)
+#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_RANGE                     31:0
+#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR16_0_VICVECTADDR16_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR17_0
+#define APS_VIC_VICVECTADDR17_0                 MK_ADDR_CONST(0x144)
+#define APS_VIC_VICVECTADDR17_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR17_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR17_0_SCR                     0
+#define APS_VIC_VICVECTADDR17_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR17_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR17_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR17_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR17_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR17_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR17_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR17_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR17_0_VICVECTADDR17_SHIFT)
+#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_RANGE                     31:0
+#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR17_0_VICVECTADDR17_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR18_0
+#define APS_VIC_VICVECTADDR18_0                 MK_ADDR_CONST(0x148)
+#define APS_VIC_VICVECTADDR18_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR18_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR18_0_SCR                     0
+#define APS_VIC_VICVECTADDR18_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR18_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR18_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR18_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR18_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR18_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR18_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR18_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR18_0_VICVECTADDR18_SHIFT)
+#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_RANGE                     31:0
+#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR18_0_VICVECTADDR18_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR19_0
+#define APS_VIC_VICVECTADDR19_0                 MK_ADDR_CONST(0x14c)
+#define APS_VIC_VICVECTADDR19_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR19_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR19_0_SCR                     0
+#define APS_VIC_VICVECTADDR19_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR19_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR19_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR19_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR19_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR19_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR19_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR19_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR19_0_VICVECTADDR19_SHIFT)
+#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_RANGE                     31:0
+#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR19_0_VICVECTADDR19_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR20_0
+#define APS_VIC_VICVECTADDR20_0                 MK_ADDR_CONST(0x150)
+#define APS_VIC_VICVECTADDR20_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR20_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR20_0_SCR                     0
+#define APS_VIC_VICVECTADDR20_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR20_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR20_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR20_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR20_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR20_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR20_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR20_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR20_0_VICVECTADDR20_SHIFT)
+#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_RANGE                     31:0
+#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR20_0_VICVECTADDR20_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR21_0
+#define APS_VIC_VICVECTADDR21_0                 MK_ADDR_CONST(0x154)
+#define APS_VIC_VICVECTADDR21_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR21_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR21_0_SCR                     0
+#define APS_VIC_VICVECTADDR21_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR21_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR21_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR21_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR21_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR21_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR21_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR21_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR21_0_VICVECTADDR21_SHIFT)
+#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_RANGE                     31:0
+#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR21_0_VICVECTADDR21_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR22_0
+#define APS_VIC_VICVECTADDR22_0                 MK_ADDR_CONST(0x158)
+#define APS_VIC_VICVECTADDR22_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR22_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR22_0_SCR                     0
+#define APS_VIC_VICVECTADDR22_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR22_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR22_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR22_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR22_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR22_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR22_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR22_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR22_0_VICVECTADDR22_SHIFT)
+#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_RANGE                     31:0
+#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR22_0_VICVECTADDR22_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR23_0
+#define APS_VIC_VICVECTADDR23_0                 MK_ADDR_CONST(0x15c)
+#define APS_VIC_VICVECTADDR23_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR23_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR23_0_SCR                     0
+#define APS_VIC_VICVECTADDR23_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR23_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR23_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR23_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR23_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR23_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR23_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR23_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR23_0_VICVECTADDR23_SHIFT)
+#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_RANGE                     31:0
+#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR23_0_VICVECTADDR23_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR24_0
+#define APS_VIC_VICVECTADDR24_0                 MK_ADDR_CONST(0x160)
+#define APS_VIC_VICVECTADDR24_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR24_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR24_0_SCR                     0
+#define APS_VIC_VICVECTADDR24_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR24_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR24_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR24_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR24_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR24_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR24_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR24_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR24_0_VICVECTADDR24_SHIFT)
+#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_RANGE                     31:0
+#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR24_0_VICVECTADDR24_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR25_0
+#define APS_VIC_VICVECTADDR25_0                 MK_ADDR_CONST(0x164)
+#define APS_VIC_VICVECTADDR25_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR25_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR25_0_SCR                     0
+#define APS_VIC_VICVECTADDR25_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR25_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR25_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR25_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR25_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR25_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR25_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR25_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR25_0_VICVECTADDR25_SHIFT)
+#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_RANGE                     31:0
+#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR25_0_VICVECTADDR25_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR26_0
+#define APS_VIC_VICVECTADDR26_0                 MK_ADDR_CONST(0x168)
+#define APS_VIC_VICVECTADDR26_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR26_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR26_0_SCR                     0
+#define APS_VIC_VICVECTADDR26_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR26_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR26_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR26_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR26_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR26_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR26_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR26_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR26_0_VICVECTADDR26_SHIFT)
+#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_RANGE                     31:0
+#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR26_0_VICVECTADDR26_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR27_0
+#define APS_VIC_VICVECTADDR27_0                 MK_ADDR_CONST(0x16c)
+#define APS_VIC_VICVECTADDR27_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR27_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR27_0_SCR                     0
+#define APS_VIC_VICVECTADDR27_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR27_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR27_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR27_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR27_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR27_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR27_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR27_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR27_0_VICVECTADDR27_SHIFT)
+#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_RANGE                     31:0
+#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR27_0_VICVECTADDR27_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR28_0
+#define APS_VIC_VICVECTADDR28_0                 MK_ADDR_CONST(0x170)
+#define APS_VIC_VICVECTADDR28_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR28_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR28_0_SCR                     0
+#define APS_VIC_VICVECTADDR28_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR28_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR28_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR28_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR28_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR28_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR28_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR28_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR28_0_VICVECTADDR28_SHIFT)
+#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_RANGE                     31:0
+#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR28_0_VICVECTADDR28_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR29_0
+#define APS_VIC_VICVECTADDR29_0                 MK_ADDR_CONST(0x174)
+#define APS_VIC_VICVECTADDR29_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR29_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR29_0_SCR                     0
+#define APS_VIC_VICVECTADDR29_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR29_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR29_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR29_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR29_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR29_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR29_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR29_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR29_0_VICVECTADDR29_SHIFT)
+#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_RANGE                     31:0
+#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR29_0_VICVECTADDR29_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR30_0
+#define APS_VIC_VICVECTADDR30_0                 MK_ADDR_CONST(0x178)
+#define APS_VIC_VICVECTADDR30_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR30_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR30_0_SCR                     0
+#define APS_VIC_VICVECTADDR30_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR30_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR30_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR30_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR30_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR30_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR30_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR30_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR30_0_VICVECTADDR30_SHIFT)
+#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_RANGE                     31:0
+#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR30_0_VICVECTADDR30_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTADDR31_0
+#define APS_VIC_VICVECTADDR31_0                 MK_ADDR_CONST(0x17c)
+#define APS_VIC_VICVECTADDR31_0_SECURE                  0x0
+#define APS_VIC_VICVECTADDR31_0_DUAL                    0x0
+#define APS_VIC_VICVECTADDR31_0_SCR                     0
+#define APS_VIC_VICVECTADDR31_0_SCRREG                  0
+#define APS_VIC_VICVECTADDR31_0_WORD_COUNT                      0x1
+#define APS_VIC_VICVECTADDR31_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR31_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR31_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR31_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR31_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR31_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_FIELD                     MK_FIELD_CONST(0xffffffff, APS_VIC_VICVECTADDR31_0_VICVECTADDR31_SHIFT)
+#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_RANGE                     31:0
+#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_MSB                       MK_SHIFT_CONST(31)
+#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_WOFFSET                   0x0
+#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTADDR31_0_VICVECTADDR31_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x180
+
+// Reserved address 0x184
+
+// Reserved address 0x188
+
+// Reserved address 0x18c
+
+// Reserved address 0x190
+
+// Reserved address 0x194
+
+// Reserved address 0x198
+
+// Reserved address 0x19c
+
+// Reserved address 0x1a0
+
+// Reserved address 0x1a4
+
+// Reserved address 0x1a8
+
+// Reserved address 0x1ac
+
+// Reserved address 0x1b0
+
+// Reserved address 0x1b4
+
+// Reserved address 0x1b8
+
+// Reserved address 0x1bc
+
+// Reserved address 0x1c0
+
+// Reserved address 0x1c4
+
+// Reserved address 0x1c8
+
+// Reserved address 0x1cc
+
+// Reserved address 0x1d0
+
+// Reserved address 0x1d4
+
+// Reserved address 0x1d8
+
+// Reserved address 0x1dc
+
+// Reserved address 0x1e0
+
+// Reserved address 0x1e4
+
+// Reserved address 0x1e8
+
+// Reserved address 0x1ec
+
+// Reserved address 0x1f0
+
+// Reserved address 0x1f4
+
+// Reserved address 0x1f8
+
+// Reserved address 0x1fc
+
+// Register APS_VIC_VICVECTPRIORITY0_0
+#define APS_VIC_VICVECTPRIORITY0_0                      MK_ADDR_CONST(0x200)
+#define APS_VIC_VICVECTPRIORITY0_0_SECURE                       0x0
+#define APS_VIC_VICVECTPRIORITY0_0_DUAL                         0x0
+#define APS_VIC_VICVECTPRIORITY0_0_SCR                  0
+#define APS_VIC_VICVECTPRIORITY0_0_SCRREG                       0
+#define APS_VIC_VICVECTPRIORITY0_0_WORD_COUNT                   0x1
+#define APS_VIC_VICVECTPRIORITY0_0_RESET_VAL                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY0_0_RESET_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY0_0_READ_MASK                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY0_0_WRITE_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_SHIFT)
+#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_RANGE                       3:0
+#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_MSB                 MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_WOFFSET                     0x0
+#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_DEFAULT                     MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY0_0_VICVECTPRIORITY0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY1_0
+#define APS_VIC_VICVECTPRIORITY1_0                      MK_ADDR_CONST(0x204)
+#define APS_VIC_VICVECTPRIORITY1_0_SECURE                       0x0
+#define APS_VIC_VICVECTPRIORITY1_0_DUAL                         0x0
+#define APS_VIC_VICVECTPRIORITY1_0_SCR                  0
+#define APS_VIC_VICVECTPRIORITY1_0_SCRREG                       0
+#define APS_VIC_VICVECTPRIORITY1_0_WORD_COUNT                   0x1
+#define APS_VIC_VICVECTPRIORITY1_0_RESET_VAL                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY1_0_RESET_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY1_0_READ_MASK                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY1_0_WRITE_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_SHIFT)
+#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_RANGE                       3:0
+#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_MSB                 MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_WOFFSET                     0x0
+#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_DEFAULT                     MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY1_0_VICVECTPRIORITY1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY2_0
+#define APS_VIC_VICVECTPRIORITY2_0                      MK_ADDR_CONST(0x208)
+#define APS_VIC_VICVECTPRIORITY2_0_SECURE                       0x0
+#define APS_VIC_VICVECTPRIORITY2_0_DUAL                         0x0
+#define APS_VIC_VICVECTPRIORITY2_0_SCR                  0
+#define APS_VIC_VICVECTPRIORITY2_0_SCRREG                       0
+#define APS_VIC_VICVECTPRIORITY2_0_WORD_COUNT                   0x1
+#define APS_VIC_VICVECTPRIORITY2_0_RESET_VAL                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY2_0_RESET_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY2_0_READ_MASK                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY2_0_WRITE_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_SHIFT)
+#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_RANGE                       3:0
+#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_MSB                 MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_WOFFSET                     0x0
+#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_DEFAULT                     MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY2_0_VICVECTPRIORITY2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY3_0
+#define APS_VIC_VICVECTPRIORITY3_0                      MK_ADDR_CONST(0x20c)
+#define APS_VIC_VICVECTPRIORITY3_0_SECURE                       0x0
+#define APS_VIC_VICVECTPRIORITY3_0_DUAL                         0x0
+#define APS_VIC_VICVECTPRIORITY3_0_SCR                  0
+#define APS_VIC_VICVECTPRIORITY3_0_SCRREG                       0
+#define APS_VIC_VICVECTPRIORITY3_0_WORD_COUNT                   0x1
+#define APS_VIC_VICVECTPRIORITY3_0_RESET_VAL                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY3_0_RESET_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY3_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY3_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY3_0_READ_MASK                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY3_0_WRITE_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_SHIFT)
+#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_RANGE                       3:0
+#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_MSB                 MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_WOFFSET                     0x0
+#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_DEFAULT                     MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY3_0_VICVECTPRIORITY3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY4_0
+#define APS_VIC_VICVECTPRIORITY4_0                      MK_ADDR_CONST(0x210)
+#define APS_VIC_VICVECTPRIORITY4_0_SECURE                       0x0
+#define APS_VIC_VICVECTPRIORITY4_0_DUAL                         0x0
+#define APS_VIC_VICVECTPRIORITY4_0_SCR                  0
+#define APS_VIC_VICVECTPRIORITY4_0_SCRREG                       0
+#define APS_VIC_VICVECTPRIORITY4_0_WORD_COUNT                   0x1
+#define APS_VIC_VICVECTPRIORITY4_0_RESET_VAL                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY4_0_RESET_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY4_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY4_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY4_0_READ_MASK                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY4_0_WRITE_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_SHIFT)
+#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_RANGE                       3:0
+#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_MSB                 MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_WOFFSET                     0x0
+#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_DEFAULT                     MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY4_0_VICVECTPRIORITY4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY5_0
+#define APS_VIC_VICVECTPRIORITY5_0                      MK_ADDR_CONST(0x214)
+#define APS_VIC_VICVECTPRIORITY5_0_SECURE                       0x0
+#define APS_VIC_VICVECTPRIORITY5_0_DUAL                         0x0
+#define APS_VIC_VICVECTPRIORITY5_0_SCR                  0
+#define APS_VIC_VICVECTPRIORITY5_0_SCRREG                       0
+#define APS_VIC_VICVECTPRIORITY5_0_WORD_COUNT                   0x1
+#define APS_VIC_VICVECTPRIORITY5_0_RESET_VAL                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY5_0_RESET_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY5_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY5_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY5_0_READ_MASK                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY5_0_WRITE_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_SHIFT)
+#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_RANGE                       3:0
+#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_MSB                 MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_WOFFSET                     0x0
+#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_DEFAULT                     MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY5_0_VICVECTPRIORITY5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY6_0
+#define APS_VIC_VICVECTPRIORITY6_0                      MK_ADDR_CONST(0x218)
+#define APS_VIC_VICVECTPRIORITY6_0_SECURE                       0x0
+#define APS_VIC_VICVECTPRIORITY6_0_DUAL                         0x0
+#define APS_VIC_VICVECTPRIORITY6_0_SCR                  0
+#define APS_VIC_VICVECTPRIORITY6_0_SCRREG                       0
+#define APS_VIC_VICVECTPRIORITY6_0_WORD_COUNT                   0x1
+#define APS_VIC_VICVECTPRIORITY6_0_RESET_VAL                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY6_0_RESET_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY6_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY6_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY6_0_READ_MASK                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY6_0_WRITE_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_SHIFT)
+#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_RANGE                       3:0
+#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_MSB                 MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_WOFFSET                     0x0
+#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_DEFAULT                     MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY6_0_VICVECTPRIORITY6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY7_0
+#define APS_VIC_VICVECTPRIORITY7_0                      MK_ADDR_CONST(0x21c)
+#define APS_VIC_VICVECTPRIORITY7_0_SECURE                       0x0
+#define APS_VIC_VICVECTPRIORITY7_0_DUAL                         0x0
+#define APS_VIC_VICVECTPRIORITY7_0_SCR                  0
+#define APS_VIC_VICVECTPRIORITY7_0_SCRREG                       0
+#define APS_VIC_VICVECTPRIORITY7_0_WORD_COUNT                   0x1
+#define APS_VIC_VICVECTPRIORITY7_0_RESET_VAL                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY7_0_RESET_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY7_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY7_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY7_0_READ_MASK                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY7_0_WRITE_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_SHIFT)
+#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_RANGE                       3:0
+#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_MSB                 MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_WOFFSET                     0x0
+#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_DEFAULT                     MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY7_0_VICVECTPRIORITY7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY8_0
+#define APS_VIC_VICVECTPRIORITY8_0                      MK_ADDR_CONST(0x220)
+#define APS_VIC_VICVECTPRIORITY8_0_SECURE                       0x0
+#define APS_VIC_VICVECTPRIORITY8_0_DUAL                         0x0
+#define APS_VIC_VICVECTPRIORITY8_0_SCR                  0
+#define APS_VIC_VICVECTPRIORITY8_0_SCRREG                       0
+#define APS_VIC_VICVECTPRIORITY8_0_WORD_COUNT                   0x1
+#define APS_VIC_VICVECTPRIORITY8_0_RESET_VAL                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY8_0_RESET_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY8_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY8_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY8_0_READ_MASK                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY8_0_WRITE_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_SHIFT)
+#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_RANGE                       3:0
+#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_MSB                 MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_WOFFSET                     0x0
+#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_DEFAULT                     MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY8_0_VICVECTPRIORITY8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY9_0
+#define APS_VIC_VICVECTPRIORITY9_0                      MK_ADDR_CONST(0x224)
+#define APS_VIC_VICVECTPRIORITY9_0_SECURE                       0x0
+#define APS_VIC_VICVECTPRIORITY9_0_DUAL                         0x0
+#define APS_VIC_VICVECTPRIORITY9_0_SCR                  0
+#define APS_VIC_VICVECTPRIORITY9_0_SCRREG                       0
+#define APS_VIC_VICVECTPRIORITY9_0_WORD_COUNT                   0x1
+#define APS_VIC_VICVECTPRIORITY9_0_RESET_VAL                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY9_0_RESET_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY9_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY9_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY9_0_READ_MASK                    MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY9_0_WRITE_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_FIELD                       MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_SHIFT)
+#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_RANGE                       3:0
+#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_MSB                 MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_WOFFSET                     0x0
+#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_DEFAULT                     MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY9_0_VICVECTPRIORITY9_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY10_0
+#define APS_VIC_VICVECTPRIORITY10_0                     MK_ADDR_CONST(0x228)
+#define APS_VIC_VICVECTPRIORITY10_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY10_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY10_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY10_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY10_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY10_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY10_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY10_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY10_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY10_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY10_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_SHIFT)
+#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY10_0_VICVECTPRIORITY10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY11_0
+#define APS_VIC_VICVECTPRIORITY11_0                     MK_ADDR_CONST(0x22c)
+#define APS_VIC_VICVECTPRIORITY11_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY11_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY11_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY11_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY11_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY11_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY11_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY11_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY11_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY11_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY11_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_SHIFT)
+#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY11_0_VICVECTPRIORITY11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY12_0
+#define APS_VIC_VICVECTPRIORITY12_0                     MK_ADDR_CONST(0x230)
+#define APS_VIC_VICVECTPRIORITY12_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY12_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY12_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY12_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY12_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY12_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY12_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY12_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY12_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY12_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY12_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_SHIFT)
+#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY12_0_VICVECTPRIORITY12_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY13_0
+#define APS_VIC_VICVECTPRIORITY13_0                     MK_ADDR_CONST(0x234)
+#define APS_VIC_VICVECTPRIORITY13_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY13_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY13_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY13_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY13_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY13_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY13_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY13_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY13_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY13_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY13_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_SHIFT)
+#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY13_0_VICVECTPRIORITY13_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY14_0
+#define APS_VIC_VICVECTPRIORITY14_0                     MK_ADDR_CONST(0x238)
+#define APS_VIC_VICVECTPRIORITY14_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY14_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY14_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY14_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY14_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY14_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY14_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY14_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY14_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY14_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY14_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_SHIFT)
+#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY14_0_VICVECTPRIORITY14_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY15_0
+#define APS_VIC_VICVECTPRIORITY15_0                     MK_ADDR_CONST(0x23c)
+#define APS_VIC_VICVECTPRIORITY15_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY15_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY15_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY15_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY15_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY15_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY15_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY15_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY15_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY15_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY15_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_SHIFT)
+#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY15_0_VICVECTPRIORITY15_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY16_0
+#define APS_VIC_VICVECTPRIORITY16_0                     MK_ADDR_CONST(0x240)
+#define APS_VIC_VICVECTPRIORITY16_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY16_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY16_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY16_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY16_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY16_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY16_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY16_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY16_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY16_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY16_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_SHIFT)
+#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY16_0_VICVECTPRIORITY16_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY17_0
+#define APS_VIC_VICVECTPRIORITY17_0                     MK_ADDR_CONST(0x244)
+#define APS_VIC_VICVECTPRIORITY17_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY17_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY17_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY17_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY17_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY17_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY17_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY17_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY17_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY17_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY17_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_SHIFT)
+#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY17_0_VICVECTPRIORITY17_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY18_0
+#define APS_VIC_VICVECTPRIORITY18_0                     MK_ADDR_CONST(0x248)
+#define APS_VIC_VICVECTPRIORITY18_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY18_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY18_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY18_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY18_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY18_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY18_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY18_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY18_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY18_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY18_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_SHIFT)
+#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY18_0_VICVECTPRIORITY18_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY19_0
+#define APS_VIC_VICVECTPRIORITY19_0                     MK_ADDR_CONST(0x24c)
+#define APS_VIC_VICVECTPRIORITY19_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY19_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY19_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY19_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY19_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY19_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY19_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY19_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY19_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY19_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY19_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_SHIFT)
+#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY19_0_VICVECTPRIORITY19_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY20_0
+#define APS_VIC_VICVECTPRIORITY20_0                     MK_ADDR_CONST(0x250)
+#define APS_VIC_VICVECTPRIORITY20_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY20_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY20_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY20_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY20_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY20_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY20_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY20_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY20_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY20_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY20_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_SHIFT)
+#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY20_0_VICVECTPRIORITY20_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY21_0
+#define APS_VIC_VICVECTPRIORITY21_0                     MK_ADDR_CONST(0x254)
+#define APS_VIC_VICVECTPRIORITY21_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY21_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY21_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY21_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY21_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY21_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY21_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY21_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY21_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY21_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY21_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_SHIFT)
+#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY21_0_VICVECTPRIORITY21_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY22_0
+#define APS_VIC_VICVECTPRIORITY22_0                     MK_ADDR_CONST(0x258)
+#define APS_VIC_VICVECTPRIORITY22_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY22_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY22_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY22_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY22_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY22_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY22_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY22_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY22_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY22_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY22_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_SHIFT)
+#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY22_0_VICVECTPRIORITY22_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY23_0
+#define APS_VIC_VICVECTPRIORITY23_0                     MK_ADDR_CONST(0x25c)
+#define APS_VIC_VICVECTPRIORITY23_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY23_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY23_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY23_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY23_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY23_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY23_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY23_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY23_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY23_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY23_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_SHIFT)
+#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY23_0_VICVECTPRIORITY23_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY24_0
+#define APS_VIC_VICVECTPRIORITY24_0                     MK_ADDR_CONST(0x260)
+#define APS_VIC_VICVECTPRIORITY24_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY24_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY24_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY24_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY24_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY24_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY24_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY24_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY24_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY24_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY24_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_SHIFT)
+#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY24_0_VICVECTPRIORITY24_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY25_0
+#define APS_VIC_VICVECTPRIORITY25_0                     MK_ADDR_CONST(0x264)
+#define APS_VIC_VICVECTPRIORITY25_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY25_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY25_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY25_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY25_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY25_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY25_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY25_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY25_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY25_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY25_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_SHIFT)
+#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY25_0_VICVECTPRIORITY25_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY26_0
+#define APS_VIC_VICVECTPRIORITY26_0                     MK_ADDR_CONST(0x268)
+#define APS_VIC_VICVECTPRIORITY26_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY26_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY26_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY26_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY26_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY26_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY26_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY26_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY26_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY26_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY26_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_SHIFT)
+#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY26_0_VICVECTPRIORITY26_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY27_0
+#define APS_VIC_VICVECTPRIORITY27_0                     MK_ADDR_CONST(0x26c)
+#define APS_VIC_VICVECTPRIORITY27_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY27_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY27_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY27_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY27_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY27_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY27_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY27_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY27_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY27_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY27_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_SHIFT)
+#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY27_0_VICVECTPRIORITY27_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY28_0
+#define APS_VIC_VICVECTPRIORITY28_0                     MK_ADDR_CONST(0x270)
+#define APS_VIC_VICVECTPRIORITY28_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY28_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY28_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY28_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY28_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY28_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY28_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY28_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY28_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY28_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY28_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_SHIFT)
+#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY28_0_VICVECTPRIORITY28_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY29_0
+#define APS_VIC_VICVECTPRIORITY29_0                     MK_ADDR_CONST(0x274)
+#define APS_VIC_VICVECTPRIORITY29_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY29_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY29_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY29_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY29_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY29_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY29_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY29_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY29_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY29_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY29_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_SHIFT)
+#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY29_0_VICVECTPRIORITY29_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY30_0
+#define APS_VIC_VICVECTPRIORITY30_0                     MK_ADDR_CONST(0x278)
+#define APS_VIC_VICVECTPRIORITY30_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY30_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY30_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY30_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY30_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY30_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY30_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY30_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY30_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY30_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY30_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_SHIFT)
+#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY30_0_VICVECTPRIORITY30_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICVECTPRIORITY31_0
+#define APS_VIC_VICVECTPRIORITY31_0                     MK_ADDR_CONST(0x27c)
+#define APS_VIC_VICVECTPRIORITY31_0_SECURE                      0x0
+#define APS_VIC_VICVECTPRIORITY31_0_DUAL                        0x0
+#define APS_VIC_VICVECTPRIORITY31_0_SCR                         0
+#define APS_VIC_VICVECTPRIORITY31_0_SCRREG                      0
+#define APS_VIC_VICVECTPRIORITY31_0_WORD_COUNT                  0x1
+#define APS_VIC_VICVECTPRIORITY31_0_RESET_VAL                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY31_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY31_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY31_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY31_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY31_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_SHIFT                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_FIELD                     MK_FIELD_CONST(0xf, APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_SHIFT)
+#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_RANGE                     3:0
+#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_MSB                       MK_SHIFT_CONST(3)
+#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_LSB                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_WOFFSET                   0x0
+#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_DEFAULT                   MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICVECTPRIORITY31_0_VICVECTPRIORITY31_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x280
+
+// Reserved address 0x284
+
+// Reserved address 0x288
+
+// Reserved address 0x28c
+
+// Reserved address 0x290
+
+// Reserved address 0x294
+
+// Reserved address 0x298
+
+// Reserved address 0x29c
+
+// Reserved address 0x2a0
+
+// Reserved address 0x2a4
+
+// Reserved address 0x2a8
+
+// Reserved address 0x2ac
+
+// Reserved address 0x2b0
+
+// Reserved address 0x2b4
+
+// Reserved address 0x2b8
+
+// Reserved address 0x2bc
+
+// Reserved address 0x2c0
+
+// Reserved address 0x2c4
+
+// Reserved address 0x2c8
+
+// Reserved address 0x2cc
+
+// Reserved address 0x2d0
+
+// Reserved address 0x2d4
+
+// Reserved address 0x2d8
+
+// Reserved address 0x2dc
+
+// Reserved address 0x2e0
+
+// Reserved address 0x2e4
+
+// Reserved address 0x2e8
+
+// Reserved address 0x2ec
+
+// Reserved address 0x2f0
+
+// Reserved address 0x2f4
+
+// Reserved address 0x2f8
+
+// Reserved address 0x2fc
+
+// Register APS_VIC_VICITCR_0
+#define APS_VIC_VICITCR_0                       MK_ADDR_CONST(0x300)
+#define APS_VIC_VICITCR_0_SECURE                        0x0
+#define APS_VIC_VICITCR_0_DUAL                  0x0
+#define APS_VIC_VICITCR_0_SCR                   0
+#define APS_VIC_VICITCR_0_SCRREG                        0
+#define APS_VIC_VICITCR_0_WORD_COUNT                    0x1
+#define APS_VIC_VICITCR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICITCR_0_RESET_MASK                    MK_MASK_CONST(0x3)
+#define APS_VIC_VICITCR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICITCR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITCR_0_READ_MASK                     MK_MASK_CONST(0x3)
+#define APS_VIC_VICITCR_0_WRITE_MASK                    MK_MASK_CONST(0x3)
+#define APS_VIC_VICITCR_0_ISS_SHIFT                     MK_SHIFT_CONST(1)
+#define APS_VIC_VICITCR_0_ISS_FIELD                     MK_FIELD_CONST(0x1, APS_VIC_VICITCR_0_ISS_SHIFT)
+#define APS_VIC_VICITCR_0_ISS_RANGE                     1:1
+#define APS_VIC_VICITCR_0_ISS_MSB                       MK_SHIFT_CONST(1)
+#define APS_VIC_VICITCR_0_ISS_LSB                       MK_SHIFT_CONST(1)
+#define APS_VIC_VICITCR_0_ISS_WOFFSET                   0x0
+#define APS_VIC_VICITCR_0_ISS_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICITCR_0_ISS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define APS_VIC_VICITCR_0_ISS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICITCR_0_ISS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICITCR_0_ISS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICITCR_0_ISS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define APS_VIC_VICITCR_0_ITEN_SHIFT                    MK_SHIFT_CONST(0)
+#define APS_VIC_VICITCR_0_ITEN_FIELD                    MK_FIELD_CONST(0x1, APS_VIC_VICITCR_0_ITEN_SHIFT)
+#define APS_VIC_VICITCR_0_ITEN_RANGE                    0:0
+#define APS_VIC_VICITCR_0_ITEN_MSB                      MK_SHIFT_CONST(0)
+#define APS_VIC_VICITCR_0_ITEN_LSB                      MK_SHIFT_CONST(0)
+#define APS_VIC_VICITCR_0_ITEN_WOFFSET                  0x0
+#define APS_VIC_VICITCR_0_ITEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICITCR_0_ITEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define APS_VIC_VICITCR_0_ITEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITCR_0_ITEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICITCR_0_ITEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICITCR_0_ITEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICITIP1_0
+#define APS_VIC_VICITIP1_0                      MK_ADDR_CONST(0x304)
+#define APS_VIC_VICITIP1_0_SECURE                       0x0
+#define APS_VIC_VICITIP1_0_DUAL                         0x0
+#define APS_VIC_VICITIP1_0_SCR                  0
+#define APS_VIC_VICITIP1_0_SCRREG                       0
+#define APS_VIC_VICITIP1_0_WORD_COUNT                   0x1
+#define APS_VIC_VICITIP1_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_READ_MASK                    MK_MASK_CONST(0x7c0)
+#define APS_VIC_VICITIP1_0_WRITE_MASK                   MK_MASK_CONST(0x1c0)
+#define APS_VIC_VICITIP1_0_VICFIQINREG_SHIFT                    MK_SHIFT_CONST(10)
+#define APS_VIC_VICITIP1_0_VICFIQINREG_FIELD                    MK_FIELD_CONST(0x1, APS_VIC_VICITIP1_0_VICFIQINREG_SHIFT)
+#define APS_VIC_VICITIP1_0_VICFIQINREG_RANGE                    10:10
+#define APS_VIC_VICITIP1_0_VICFIQINREG_MSB                      MK_SHIFT_CONST(10)
+#define APS_VIC_VICITIP1_0_VICFIQINREG_LSB                      MK_SHIFT_CONST(10)
+#define APS_VIC_VICITIP1_0_VICFIQINREG_WOFFSET                  0x0
+#define APS_VIC_VICITIP1_0_VICFIQINREG_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_VICFIQINREG_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_VICFIQINREG_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_VICFIQINREG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_VICFIQINREG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_VICFIQINREG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define APS_VIC_VICITIP1_0_VICIRQINREG_SHIFT                    MK_SHIFT_CONST(9)
+#define APS_VIC_VICITIP1_0_VICIRQINREG_FIELD                    MK_FIELD_CONST(0x1, APS_VIC_VICITIP1_0_VICIRQINREG_SHIFT)
+#define APS_VIC_VICITIP1_0_VICIRQINREG_RANGE                    9:9
+#define APS_VIC_VICITIP1_0_VICIRQINREG_MSB                      MK_SHIFT_CONST(9)
+#define APS_VIC_VICITIP1_0_VICIRQINREG_LSB                      MK_SHIFT_CONST(9)
+#define APS_VIC_VICITIP1_0_VICIRQINREG_WOFFSET                  0x0
+#define APS_VIC_VICITIP1_0_VICIRQINREG_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_VICIRQINREG_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_VICIRQINREG_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_VICIRQINREG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_VICIRQINREG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_VICIRQINREG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define APS_VIC_VICITIP1_0_VICIRQACK_SHIFT                      MK_SHIFT_CONST(8)
+#define APS_VIC_VICITIP1_0_VICIRQACK_FIELD                      MK_FIELD_CONST(0x1, APS_VIC_VICITIP1_0_VICIRQACK_SHIFT)
+#define APS_VIC_VICITIP1_0_VICIRQACK_RANGE                      8:8
+#define APS_VIC_VICITIP1_0_VICIRQACK_MSB                        MK_SHIFT_CONST(8)
+#define APS_VIC_VICITIP1_0_VICIRQACK_LSB                        MK_SHIFT_CONST(8)
+#define APS_VIC_VICITIP1_0_VICIRQACK_WOFFSET                    0x0
+#define APS_VIC_VICITIP1_0_VICIRQACK_DEFAULT                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_VICIRQACK_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_VICIRQACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_VICIRQACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_VICIRQACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_VICIRQACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define APS_VIC_VICITIP1_0_NVICIRQIN_SHIFT                      MK_SHIFT_CONST(7)
+#define APS_VIC_VICITIP1_0_NVICIRQIN_FIELD                      MK_FIELD_CONST(0x1, APS_VIC_VICITIP1_0_NVICIRQIN_SHIFT)
+#define APS_VIC_VICITIP1_0_NVICIRQIN_RANGE                      7:7
+#define APS_VIC_VICITIP1_0_NVICIRQIN_MSB                        MK_SHIFT_CONST(7)
+#define APS_VIC_VICITIP1_0_NVICIRQIN_LSB                        MK_SHIFT_CONST(7)
+#define APS_VIC_VICITIP1_0_NVICIRQIN_WOFFSET                    0x0
+#define APS_VIC_VICITIP1_0_NVICIRQIN_DEFAULT                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_NVICIRQIN_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_NVICIRQIN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_NVICIRQIN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_NVICIRQIN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_NVICIRQIN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define APS_VIC_VICITIP1_0_NVICFIQIN_SHIFT                      MK_SHIFT_CONST(6)
+#define APS_VIC_VICITIP1_0_NVICFIQIN_FIELD                      MK_FIELD_CONST(0x1, APS_VIC_VICITIP1_0_NVICFIQIN_SHIFT)
+#define APS_VIC_VICITIP1_0_NVICFIQIN_RANGE                      6:6
+#define APS_VIC_VICITIP1_0_NVICFIQIN_MSB                        MK_SHIFT_CONST(6)
+#define APS_VIC_VICITIP1_0_NVICFIQIN_LSB                        MK_SHIFT_CONST(6)
+#define APS_VIC_VICITIP1_0_NVICFIQIN_WOFFSET                    0x0
+#define APS_VIC_VICITIP1_0_NVICFIQIN_DEFAULT                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_NVICFIQIN_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_NVICFIQIN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_NVICFIQIN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_NVICFIQIN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP1_0_NVICFIQIN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICITIP2_0
+#define APS_VIC_VICITIP2_0                      MK_ADDR_CONST(0x308)
+#define APS_VIC_VICITIP2_0_SECURE                       0x0
+#define APS_VIC_VICITIP2_0_DUAL                         0x0
+#define APS_VIC_VICITIP2_0_SCR                  0
+#define APS_VIC_VICITIP2_0_SCRREG                       0
+#define APS_VIC_VICITIP2_0_WORD_COUNT                   0x1
+#define APS_VIC_VICITIP2_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP2_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP2_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICITIP2_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICITIP2_0_VICVECTADDRIN_SHIFT                  MK_SHIFT_CONST(0)
+#define APS_VIC_VICITIP2_0_VICVECTADDRIN_FIELD                  MK_FIELD_CONST(0xffffffff, APS_VIC_VICITIP2_0_VICVECTADDRIN_SHIFT)
+#define APS_VIC_VICITIP2_0_VICVECTADDRIN_RANGE                  31:0
+#define APS_VIC_VICITIP2_0_VICVECTADDRIN_MSB                    MK_SHIFT_CONST(31)
+#define APS_VIC_VICITIP2_0_VICVECTADDRIN_LSB                    MK_SHIFT_CONST(0)
+#define APS_VIC_VICITIP2_0_VICVECTADDRIN_WOFFSET                        0x0
+#define APS_VIC_VICITIP2_0_VICVECTADDRIN_DEFAULT                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP2_0_VICVECTADDRIN_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP2_0_VICVECTADDRIN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP2_0_VICVECTADDRIN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP2_0_VICVECTADDRIN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICITIP2_0_VICVECTADDRIN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICITOP1_0
+#define APS_VIC_VICITOP1_0                      MK_ADDR_CONST(0x30c)
+#define APS_VIC_VICITOP1_0_SECURE                       0x0
+#define APS_VIC_VICITOP1_0_DUAL                         0x0
+#define APS_VIC_VICITOP1_0_SCR                  0
+#define APS_VIC_VICITOP1_0_SCRREG                       0
+#define APS_VIC_VICITOP1_0_WORD_COUNT                   0x1
+#define APS_VIC_VICITOP1_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_RESET_MASK                   MK_MASK_CONST(0x3c0)
+#define APS_VIC_VICITOP1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_READ_MASK                    MK_MASK_CONST(0x3c0)
+#define APS_VIC_VICITOP1_0_WRITE_MASK                   MK_MASK_CONST(0x3c0)
+#define APS_VIC_VICITOP1_0_VICIRQACKOUT_SHIFT                   MK_SHIFT_CONST(9)
+#define APS_VIC_VICITOP1_0_VICIRQACKOUT_FIELD                   MK_FIELD_CONST(0x1, APS_VIC_VICITOP1_0_VICIRQACKOUT_SHIFT)
+#define APS_VIC_VICITOP1_0_VICIRQACKOUT_RANGE                   9:9
+#define APS_VIC_VICITOP1_0_VICIRQACKOUT_MSB                     MK_SHIFT_CONST(9)
+#define APS_VIC_VICITOP1_0_VICIRQACKOUT_LSB                     MK_SHIFT_CONST(9)
+#define APS_VIC_VICITOP1_0_VICIRQACKOUT_WOFFSET                 0x0
+#define APS_VIC_VICITOP1_0_VICIRQACKOUT_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_VICIRQACKOUT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_VIC_VICITOP1_0_VICIRQACKOUT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_VICIRQACKOUT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_VICIRQACKOUT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_VICIRQACKOUT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define APS_VIC_VICITOP1_0_VICVECTADDRV_SHIFT                   MK_SHIFT_CONST(8)
+#define APS_VIC_VICITOP1_0_VICVECTADDRV_FIELD                   MK_FIELD_CONST(0x1, APS_VIC_VICITOP1_0_VICVECTADDRV_SHIFT)
+#define APS_VIC_VICITOP1_0_VICVECTADDRV_RANGE                   8:8
+#define APS_VIC_VICITOP1_0_VICVECTADDRV_MSB                     MK_SHIFT_CONST(8)
+#define APS_VIC_VICITOP1_0_VICVECTADDRV_LSB                     MK_SHIFT_CONST(8)
+#define APS_VIC_VICITOP1_0_VICVECTADDRV_WOFFSET                 0x0
+#define APS_VIC_VICITOP1_0_VICVECTADDRV_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_VICVECTADDRV_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define APS_VIC_VICITOP1_0_VICVECTADDRV_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_VICVECTADDRV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_VICVECTADDRV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_VICVECTADDRV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define APS_VIC_VICITOP1_0_VICIRQ_SHIFT                 MK_SHIFT_CONST(7)
+#define APS_VIC_VICITOP1_0_VICIRQ_FIELD                 MK_FIELD_CONST(0x1, APS_VIC_VICITOP1_0_VICIRQ_SHIFT)
+#define APS_VIC_VICITOP1_0_VICIRQ_RANGE                 7:7
+#define APS_VIC_VICITOP1_0_VICIRQ_MSB                   MK_SHIFT_CONST(7)
+#define APS_VIC_VICITOP1_0_VICIRQ_LSB                   MK_SHIFT_CONST(7)
+#define APS_VIC_VICITOP1_0_VICIRQ_WOFFSET                       0x0
+#define APS_VIC_VICITOP1_0_VICIRQ_DEFAULT                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_VICIRQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define APS_VIC_VICITOP1_0_VICIRQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_VICIRQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_VICIRQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_VICIRQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define APS_VIC_VICITOP1_0_VICFIQ_SHIFT                 MK_SHIFT_CONST(6)
+#define APS_VIC_VICITOP1_0_VICFIQ_FIELD                 MK_FIELD_CONST(0x1, APS_VIC_VICITOP1_0_VICFIQ_SHIFT)
+#define APS_VIC_VICITOP1_0_VICFIQ_RANGE                 6:6
+#define APS_VIC_VICITOP1_0_VICFIQ_MSB                   MK_SHIFT_CONST(6)
+#define APS_VIC_VICITOP1_0_VICFIQ_LSB                   MK_SHIFT_CONST(6)
+#define APS_VIC_VICITOP1_0_VICFIQ_WOFFSET                       0x0
+#define APS_VIC_VICITOP1_0_VICFIQ_DEFAULT                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_VICFIQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define APS_VIC_VICITOP1_0_VICFIQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_VICFIQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_VICFIQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP1_0_VICFIQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICITOP2_0
+#define APS_VIC_VICITOP2_0                      MK_ADDR_CONST(0x310)
+#define APS_VIC_VICITOP2_0_SECURE                       0x0
+#define APS_VIC_VICITOP2_0_DUAL                         0x0
+#define APS_VIC_VICITOP2_0_SCR                  0
+#define APS_VIC_VICITOP2_0_SCRREG                       0
+#define APS_VIC_VICITOP2_0_WORD_COUNT                   0x1
+#define APS_VIC_VICITOP2_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP2_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICITOP2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP2_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICITOP2_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICITOP2_0_VICVECTADDROUT_SHIFT                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICITOP2_0_VICVECTADDROUT_FIELD                 MK_FIELD_CONST(0xffffffff, APS_VIC_VICITOP2_0_VICVECTADDROUT_SHIFT)
+#define APS_VIC_VICITOP2_0_VICVECTADDROUT_RANGE                 31:0
+#define APS_VIC_VICITOP2_0_VICVECTADDROUT_MSB                   MK_SHIFT_CONST(31)
+#define APS_VIC_VICITOP2_0_VICVECTADDROUT_LSB                   MK_SHIFT_CONST(0)
+#define APS_VIC_VICITOP2_0_VICVECTADDROUT_WOFFSET                       0x0
+#define APS_VIC_VICITOP2_0_VICVECTADDROUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP2_0_VICVECTADDROUT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICITOP2_0_VICVECTADDROUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP2_0_VICVECTADDROUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP2_0_VICVECTADDROUT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICITOP2_0_VICVECTADDROUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICINTSSTATUS_0
+#define APS_VIC_VICINTSSTATUS_0                 MK_ADDR_CONST(0x314)
+#define APS_VIC_VICINTSSTATUS_0_SECURE                  0x0
+#define APS_VIC_VICINTSSTATUS_0_DUAL                    0x0
+#define APS_VIC_VICINTSSTATUS_0_SCR                     0
+#define APS_VIC_VICINTSSTATUS_0_SCRREG                  0
+#define APS_VIC_VICINTSSTATUS_0_WORD_COUNT                      0x1
+#define APS_VIC_VICINTSSTATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICINTSSTATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICINTSSTATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_FIELD                        MK_FIELD_CONST(0xffffffff, APS_VIC_VICINTSSTATUS_0_INTSSTATUS_SHIFT)
+#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_RANGE                        31:0
+#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_MSB                  MK_SHIFT_CONST(31)
+#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_LSB                  MK_SHIFT_CONST(0)
+#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_WOFFSET                      0x0
+#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUS_0_INTSSTATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICINTSSTATUSCLEAR_0
+#define APS_VIC_VICINTSSTATUSCLEAR_0                    MK_ADDR_CONST(0x318)
+#define APS_VIC_VICINTSSTATUSCLEAR_0_SECURE                     0x0
+#define APS_VIC_VICINTSSTATUSCLEAR_0_DUAL                       0x0
+#define APS_VIC_VICINTSSTATUSCLEAR_0_SCR                        0
+#define APS_VIC_VICINTSSTATUSCLEAR_0_SCRREG                     0
+#define APS_VIC_VICINTSSTATUSCLEAR_0_WORD_COUNT                         0x1
+#define APS_VIC_VICINTSSTATUSCLEAR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUSCLEAR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUSCLEAR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUSCLEAR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUSCLEAR_0_READ_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUSCLEAR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_FIELD                   MK_FIELD_CONST(0xffffffff, APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_SHIFT)
+#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_RANGE                   31:0
+#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_MSB                     MK_SHIFT_CONST(31)
+#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_LSB                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_WOFFSET                 0x0
+#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICINTSSTATUSCLEAR_0_INTSSTATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x31c
+
+// Reserved address 0x320
+
+// Reserved address 0x324
+
+// Reserved address 0x328
+
+// Reserved address 0x32c
+
+// Reserved address 0x330
+
+// Reserved address 0x334
+
+// Reserved address 0x338
+
+// Reserved address 0x33c
+
+// Reserved address 0x340
+
+// Reserved address 0x344
+
+// Reserved address 0x348
+
+// Reserved address 0x34c
+
+// Reserved address 0x350
+
+// Reserved address 0x354
+
+// Reserved address 0x358
+
+// Reserved address 0x35c
+
+// Reserved address 0x360
+
+// Reserved address 0x364
+
+// Reserved address 0x368
+
+// Reserved address 0x36c
+
+// Reserved address 0x370
+
+// Reserved address 0x374
+
+// Reserved address 0x378
+
+// Reserved address 0x37c
+
+// Reserved address 0x380
+
+// Reserved address 0x384
+
+// Reserved address 0x388
+
+// Reserved address 0x38c
+
+// Reserved address 0x390
+
+// Reserved address 0x394
+
+// Reserved address 0x398
+
+// Reserved address 0x39c
+
+// Reserved address 0x3a0
+
+// Reserved address 0x3a4
+
+// Reserved address 0x3a8
+
+// Reserved address 0x3ac
+
+// Reserved address 0x3b0
+
+// Reserved address 0x3b4
+
+// Reserved address 0x3b8
+
+// Reserved address 0x3bc
+
+// Reserved address 0x3c0
+
+// Reserved address 0x3c4
+
+// Reserved address 0x3c8
+
+// Reserved address 0x3cc
+
+// Reserved address 0x3d0
+
+// Reserved address 0x3d4
+
+// Reserved address 0x3d8
+
+// Reserved address 0x3dc
+
+// Reserved address 0x3e0
+
+// Reserved address 0x3e4
+
+// Reserved address 0x3e8
+
+// Reserved address 0x3ec
+
+// Reserved address 0x3f0
+
+// Reserved address 0x3f4
+
+// Reserved address 0x3f8
+
+// Reserved address 0x3fc
+
+// Reserved address 0x400
+
+// Reserved address 0x404
+
+// Reserved address 0x408
+
+// Reserved address 0x40c
+
+// Reserved address 0x410
+
+// Reserved address 0x414
+
+// Reserved address 0x418
+
+// Reserved address 0x41c
+
+// Reserved address 0x420
+
+// Reserved address 0x424
+
+// Reserved address 0x428
+
+// Reserved address 0x42c
+
+// Reserved address 0x430
+
+// Reserved address 0x434
+
+// Reserved address 0x438
+
+// Reserved address 0x43c
+
+// Reserved address 0x440
+
+// Reserved address 0x444
+
+// Reserved address 0x448
+
+// Reserved address 0x44c
+
+// Reserved address 0x450
+
+// Reserved address 0x454
+
+// Reserved address 0x458
+
+// Reserved address 0x45c
+
+// Reserved address 0x460
+
+// Reserved address 0x464
+
+// Reserved address 0x468
+
+// Reserved address 0x46c
+
+// Reserved address 0x470
+
+// Reserved address 0x474
+
+// Reserved address 0x478
+
+// Reserved address 0x47c
+
+// Reserved address 0x480
+
+// Reserved address 0x484
+
+// Reserved address 0x488
+
+// Reserved address 0x48c
+
+// Reserved address 0x490
+
+// Reserved address 0x494
+
+// Reserved address 0x498
+
+// Reserved address 0x49c
+
+// Reserved address 0x4a0
+
+// Reserved address 0x4a4
+
+// Reserved address 0x4a8
+
+// Reserved address 0x4ac
+
+// Reserved address 0x4b0
+
+// Reserved address 0x4b4
+
+// Reserved address 0x4b8
+
+// Reserved address 0x4bc
+
+// Reserved address 0x4c0
+
+// Reserved address 0x4c4
+
+// Reserved address 0x4c8
+
+// Reserved address 0x4cc
+
+// Reserved address 0x4d0
+
+// Reserved address 0x4d4
+
+// Reserved address 0x4d8
+
+// Reserved address 0x4dc
+
+// Reserved address 0x4e0
+
+// Reserved address 0x4e4
+
+// Reserved address 0x4e8
+
+// Reserved address 0x4ec
+
+// Reserved address 0x4f0
+
+// Reserved address 0x4f4
+
+// Reserved address 0x4f8
+
+// Reserved address 0x4fc
+
+// Reserved address 0x500
+
+// Reserved address 0x504
+
+// Reserved address 0x508
+
+// Reserved address 0x50c
+
+// Reserved address 0x510
+
+// Reserved address 0x514
+
+// Reserved address 0x518
+
+// Reserved address 0x51c
+
+// Reserved address 0x520
+
+// Reserved address 0x524
+
+// Reserved address 0x528
+
+// Reserved address 0x52c
+
+// Reserved address 0x530
+
+// Reserved address 0x534
+
+// Reserved address 0x538
+
+// Reserved address 0x53c
+
+// Reserved address 0x540
+
+// Reserved address 0x544
+
+// Reserved address 0x548
+
+// Reserved address 0x54c
+
+// Reserved address 0x550
+
+// Reserved address 0x554
+
+// Reserved address 0x558
+
+// Reserved address 0x55c
+
+// Reserved address 0x560
+
+// Reserved address 0x564
+
+// Reserved address 0x568
+
+// Reserved address 0x56c
+
+// Reserved address 0x570
+
+// Reserved address 0x574
+
+// Reserved address 0x578
+
+// Reserved address 0x57c
+
+// Reserved address 0x580
+
+// Reserved address 0x584
+
+// Reserved address 0x588
+
+// Reserved address 0x58c
+
+// Reserved address 0x590
+
+// Reserved address 0x594
+
+// Reserved address 0x598
+
+// Reserved address 0x59c
+
+// Reserved address 0x5a0
+
+// Reserved address 0x5a4
+
+// Reserved address 0x5a8
+
+// Reserved address 0x5ac
+
+// Reserved address 0x5b0
+
+// Reserved address 0x5b4
+
+// Reserved address 0x5b8
+
+// Reserved address 0x5bc
+
+// Reserved address 0x5c0
+
+// Reserved address 0x5c4
+
+// Reserved address 0x5c8
+
+// Reserved address 0x5cc
+
+// Reserved address 0x5d0
+
+// Reserved address 0x5d4
+
+// Reserved address 0x5d8
+
+// Reserved address 0x5dc
+
+// Reserved address 0x5e0
+
+// Reserved address 0x5e4
+
+// Reserved address 0x5e8
+
+// Reserved address 0x5ec
+
+// Reserved address 0x5f0
+
+// Reserved address 0x5f4
+
+// Reserved address 0x5f8
+
+// Reserved address 0x5fc
+
+// Reserved address 0x600
+
+// Reserved address 0x604
+
+// Reserved address 0x608
+
+// Reserved address 0x60c
+
+// Reserved address 0x610
+
+// Reserved address 0x614
+
+// Reserved address 0x618
+
+// Reserved address 0x61c
+
+// Reserved address 0x620
+
+// Reserved address 0x624
+
+// Reserved address 0x628
+
+// Reserved address 0x62c
+
+// Reserved address 0x630
+
+// Reserved address 0x634
+
+// Reserved address 0x638
+
+// Reserved address 0x63c
+
+// Reserved address 0x640
+
+// Reserved address 0x644
+
+// Reserved address 0x648
+
+// Reserved address 0x64c
+
+// Reserved address 0x650
+
+// Reserved address 0x654
+
+// Reserved address 0x658
+
+// Reserved address 0x65c
+
+// Reserved address 0x660
+
+// Reserved address 0x664
+
+// Reserved address 0x668
+
+// Reserved address 0x66c
+
+// Reserved address 0x670
+
+// Reserved address 0x674
+
+// Reserved address 0x678
+
+// Reserved address 0x67c
+
+// Reserved address 0x680
+
+// Reserved address 0x684
+
+// Reserved address 0x688
+
+// Reserved address 0x68c
+
+// Reserved address 0x690
+
+// Reserved address 0x694
+
+// Reserved address 0x698
+
+// Reserved address 0x69c
+
+// Reserved address 0x6a0
+
+// Reserved address 0x6a4
+
+// Reserved address 0x6a8
+
+// Reserved address 0x6ac
+
+// Reserved address 0x6b0
+
+// Reserved address 0x6b4
+
+// Reserved address 0x6b8
+
+// Reserved address 0x6bc
+
+// Reserved address 0x6c0
+
+// Reserved address 0x6c4
+
+// Reserved address 0x6c8
+
+// Reserved address 0x6cc
+
+// Reserved address 0x6d0
+
+// Reserved address 0x6d4
+
+// Reserved address 0x6d8
+
+// Reserved address 0x6dc
+
+// Reserved address 0x6e0
+
+// Reserved address 0x6e4
+
+// Reserved address 0x6e8
+
+// Reserved address 0x6ec
+
+// Reserved address 0x6f0
+
+// Reserved address 0x6f4
+
+// Reserved address 0x6f8
+
+// Reserved address 0x6fc
+
+// Reserved address 0x700
+
+// Reserved address 0x704
+
+// Reserved address 0x708
+
+// Reserved address 0x70c
+
+// Reserved address 0x710
+
+// Reserved address 0x714
+
+// Reserved address 0x718
+
+// Reserved address 0x71c
+
+// Reserved address 0x720
+
+// Reserved address 0x724
+
+// Reserved address 0x728
+
+// Reserved address 0x72c
+
+// Reserved address 0x730
+
+// Reserved address 0x734
+
+// Reserved address 0x738
+
+// Reserved address 0x73c
+
+// Reserved address 0x740
+
+// Reserved address 0x744
+
+// Reserved address 0x748
+
+// Reserved address 0x74c
+
+// Reserved address 0x750
+
+// Reserved address 0x754
+
+// Reserved address 0x758
+
+// Reserved address 0x75c
+
+// Reserved address 0x760
+
+// Reserved address 0x764
+
+// Reserved address 0x768
+
+// Reserved address 0x76c
+
+// Reserved address 0x770
+
+// Reserved address 0x774
+
+// Reserved address 0x778
+
+// Reserved address 0x77c
+
+// Reserved address 0x780
+
+// Reserved address 0x784
+
+// Reserved address 0x788
+
+// Reserved address 0x78c
+
+// Reserved address 0x790
+
+// Reserved address 0x794
+
+// Reserved address 0x798
+
+// Reserved address 0x79c
+
+// Reserved address 0x7a0
+
+// Reserved address 0x7a4
+
+// Reserved address 0x7a8
+
+// Reserved address 0x7ac
+
+// Reserved address 0x7b0
+
+// Reserved address 0x7b4
+
+// Reserved address 0x7b8
+
+// Reserved address 0x7bc
+
+// Reserved address 0x7c0
+
+// Reserved address 0x7c4
+
+// Reserved address 0x7c8
+
+// Reserved address 0x7cc
+
+// Reserved address 0x7d0
+
+// Reserved address 0x7d4
+
+// Reserved address 0x7d8
+
+// Reserved address 0x7dc
+
+// Reserved address 0x7e0
+
+// Reserved address 0x7e4
+
+// Reserved address 0x7e8
+
+// Reserved address 0x7ec
+
+// Reserved address 0x7f0
+
+// Reserved address 0x7f4
+
+// Reserved address 0x7f8
+
+// Reserved address 0x7fc
+
+// Reserved address 0x800
+
+// Reserved address 0x804
+
+// Reserved address 0x808
+
+// Reserved address 0x80c
+
+// Reserved address 0x810
+
+// Reserved address 0x814
+
+// Reserved address 0x818
+
+// Reserved address 0x81c
+
+// Reserved address 0x820
+
+// Reserved address 0x824
+
+// Reserved address 0x828
+
+// Reserved address 0x82c
+
+// Reserved address 0x830
+
+// Reserved address 0x834
+
+// Reserved address 0x838
+
+// Reserved address 0x83c
+
+// Reserved address 0x840
+
+// Reserved address 0x844
+
+// Reserved address 0x848
+
+// Reserved address 0x84c
+
+// Reserved address 0x850
+
+// Reserved address 0x854
+
+// Reserved address 0x858
+
+// Reserved address 0x85c
+
+// Reserved address 0x860
+
+// Reserved address 0x864
+
+// Reserved address 0x868
+
+// Reserved address 0x86c
+
+// Reserved address 0x870
+
+// Reserved address 0x874
+
+// Reserved address 0x878
+
+// Reserved address 0x87c
+
+// Reserved address 0x880
+
+// Reserved address 0x884
+
+// Reserved address 0x888
+
+// Reserved address 0x88c
+
+// Reserved address 0x890
+
+// Reserved address 0x894
+
+// Reserved address 0x898
+
+// Reserved address 0x89c
+
+// Reserved address 0x8a0
+
+// Reserved address 0x8a4
+
+// Reserved address 0x8a8
+
+// Reserved address 0x8ac
+
+// Reserved address 0x8b0
+
+// Reserved address 0x8b4
+
+// Reserved address 0x8b8
+
+// Reserved address 0x8bc
+
+// Reserved address 0x8c0
+
+// Reserved address 0x8c4
+
+// Reserved address 0x8c8
+
+// Reserved address 0x8cc
+
+// Reserved address 0x8d0
+
+// Reserved address 0x8d4
+
+// Reserved address 0x8d8
+
+// Reserved address 0x8dc
+
+// Reserved address 0x8e0
+
+// Reserved address 0x8e4
+
+// Reserved address 0x8e8
+
+// Reserved address 0x8ec
+
+// Reserved address 0x8f0
+
+// Reserved address 0x8f4
+
+// Reserved address 0x8f8
+
+// Reserved address 0x8fc
+
+// Reserved address 0x900
+
+// Reserved address 0x904
+
+// Reserved address 0x908
+
+// Reserved address 0x90c
+
+// Reserved address 0x910
+
+// Reserved address 0x914
+
+// Reserved address 0x918
+
+// Reserved address 0x91c
+
+// Reserved address 0x920
+
+// Reserved address 0x924
+
+// Reserved address 0x928
+
+// Reserved address 0x92c
+
+// Reserved address 0x930
+
+// Reserved address 0x934
+
+// Reserved address 0x938
+
+// Reserved address 0x93c
+
+// Reserved address 0x940
+
+// Reserved address 0x944
+
+// Reserved address 0x948
+
+// Reserved address 0x94c
+
+// Reserved address 0x950
+
+// Reserved address 0x954
+
+// Reserved address 0x958
+
+// Reserved address 0x95c
+
+// Reserved address 0x960
+
+// Reserved address 0x964
+
+// Reserved address 0x968
+
+// Reserved address 0x96c
+
+// Reserved address 0x970
+
+// Reserved address 0x974
+
+// Reserved address 0x978
+
+// Reserved address 0x97c
+
+// Reserved address 0x980
+
+// Reserved address 0x984
+
+// Reserved address 0x988
+
+// Reserved address 0x98c
+
+// Reserved address 0x990
+
+// Reserved address 0x994
+
+// Reserved address 0x998
+
+// Reserved address 0x99c
+
+// Reserved address 0x9a0
+
+// Reserved address 0x9a4
+
+// Reserved address 0x9a8
+
+// Reserved address 0x9ac
+
+// Reserved address 0x9b0
+
+// Reserved address 0x9b4
+
+// Reserved address 0x9b8
+
+// Reserved address 0x9bc
+
+// Reserved address 0x9c0
+
+// Reserved address 0x9c4
+
+// Reserved address 0x9c8
+
+// Reserved address 0x9cc
+
+// Reserved address 0x9d0
+
+// Reserved address 0x9d4
+
+// Reserved address 0x9d8
+
+// Reserved address 0x9dc
+
+// Reserved address 0x9e0
+
+// Reserved address 0x9e4
+
+// Reserved address 0x9e8
+
+// Reserved address 0x9ec
+
+// Reserved address 0x9f0
+
+// Reserved address 0x9f4
+
+// Reserved address 0x9f8
+
+// Reserved address 0x9fc
+
+// Reserved address 0xa00
+
+// Reserved address 0xa04
+
+// Reserved address 0xa08
+
+// Reserved address 0xa0c
+
+// Reserved address 0xa10
+
+// Reserved address 0xa14
+
+// Reserved address 0xa18
+
+// Reserved address 0xa1c
+
+// Reserved address 0xa20
+
+// Reserved address 0xa24
+
+// Reserved address 0xa28
+
+// Reserved address 0xa2c
+
+// Reserved address 0xa30
+
+// Reserved address 0xa34
+
+// Reserved address 0xa38
+
+// Reserved address 0xa3c
+
+// Reserved address 0xa40
+
+// Reserved address 0xa44
+
+// Reserved address 0xa48
+
+// Reserved address 0xa4c
+
+// Reserved address 0xa50
+
+// Reserved address 0xa54
+
+// Reserved address 0xa58
+
+// Reserved address 0xa5c
+
+// Reserved address 0xa60
+
+// Reserved address 0xa64
+
+// Reserved address 0xa68
+
+// Reserved address 0xa6c
+
+// Reserved address 0xa70
+
+// Reserved address 0xa74
+
+// Reserved address 0xa78
+
+// Reserved address 0xa7c
+
+// Reserved address 0xa80
+
+// Reserved address 0xa84
+
+// Reserved address 0xa88
+
+// Reserved address 0xa8c
+
+// Reserved address 0xa90
+
+// Reserved address 0xa94
+
+// Reserved address 0xa98
+
+// Reserved address 0xa9c
+
+// Reserved address 0xaa0
+
+// Reserved address 0xaa4
+
+// Reserved address 0xaa8
+
+// Reserved address 0xaac
+
+// Reserved address 0xab0
+
+// Reserved address 0xab4
+
+// Reserved address 0xab8
+
+// Reserved address 0xabc
+
+// Reserved address 0xac0
+
+// Reserved address 0xac4
+
+// Reserved address 0xac8
+
+// Reserved address 0xacc
+
+// Reserved address 0xad0
+
+// Reserved address 0xad4
+
+// Reserved address 0xad8
+
+// Reserved address 0xadc
+
+// Reserved address 0xae0
+
+// Reserved address 0xae4
+
+// Reserved address 0xae8
+
+// Reserved address 0xaec
+
+// Reserved address 0xaf0
+
+// Reserved address 0xaf4
+
+// Reserved address 0xaf8
+
+// Reserved address 0xafc
+
+// Reserved address 0xb00
+
+// Reserved address 0xb04
+
+// Reserved address 0xb08
+
+// Reserved address 0xb0c
+
+// Reserved address 0xb10
+
+// Reserved address 0xb14
+
+// Reserved address 0xb18
+
+// Reserved address 0xb1c
+
+// Reserved address 0xb20
+
+// Reserved address 0xb24
+
+// Reserved address 0xb28
+
+// Reserved address 0xb2c
+
+// Reserved address 0xb30
+
+// Reserved address 0xb34
+
+// Reserved address 0xb38
+
+// Reserved address 0xb3c
+
+// Reserved address 0xb40
+
+// Reserved address 0xb44
+
+// Reserved address 0xb48
+
+// Reserved address 0xb4c
+
+// Reserved address 0xb50
+
+// Reserved address 0xb54
+
+// Reserved address 0xb58
+
+// Reserved address 0xb5c
+
+// Reserved address 0xb60
+
+// Reserved address 0xb64
+
+// Reserved address 0xb68
+
+// Reserved address 0xb6c
+
+// Reserved address 0xb70
+
+// Reserved address 0xb74
+
+// Reserved address 0xb78
+
+// Reserved address 0xb7c
+
+// Reserved address 0xb80
+
+// Reserved address 0xb84
+
+// Reserved address 0xb88
+
+// Reserved address 0xb8c
+
+// Reserved address 0xb90
+
+// Reserved address 0xb94
+
+// Reserved address 0xb98
+
+// Reserved address 0xb9c
+
+// Reserved address 0xba0
+
+// Reserved address 0xba4
+
+// Reserved address 0xba8
+
+// Reserved address 0xbac
+
+// Reserved address 0xbb0
+
+// Reserved address 0xbb4
+
+// Reserved address 0xbb8
+
+// Reserved address 0xbbc
+
+// Reserved address 0xbc0
+
+// Reserved address 0xbc4
+
+// Reserved address 0xbc8
+
+// Reserved address 0xbcc
+
+// Reserved address 0xbd0
+
+// Reserved address 0xbd4
+
+// Reserved address 0xbd8
+
+// Reserved address 0xbdc
+
+// Reserved address 0xbe0
+
+// Reserved address 0xbe4
+
+// Reserved address 0xbe8
+
+// Reserved address 0xbec
+
+// Reserved address 0xbf0
+
+// Reserved address 0xbf4
+
+// Reserved address 0xbf8
+
+// Reserved address 0xbfc
+
+// Reserved address 0xc00
+
+// Reserved address 0xc04
+
+// Reserved address 0xc08
+
+// Reserved address 0xc0c
+
+// Reserved address 0xc10
+
+// Reserved address 0xc14
+
+// Reserved address 0xc18
+
+// Reserved address 0xc1c
+
+// Reserved address 0xc20
+
+// Reserved address 0xc24
+
+// Reserved address 0xc28
+
+// Reserved address 0xc2c
+
+// Reserved address 0xc30
+
+// Reserved address 0xc34
+
+// Reserved address 0xc38
+
+// Reserved address 0xc3c
+
+// Reserved address 0xc40
+
+// Reserved address 0xc44
+
+// Reserved address 0xc48
+
+// Reserved address 0xc4c
+
+// Reserved address 0xc50
+
+// Reserved address 0xc54
+
+// Reserved address 0xc58
+
+// Reserved address 0xc5c
+
+// Reserved address 0xc60
+
+// Reserved address 0xc64
+
+// Reserved address 0xc68
+
+// Reserved address 0xc6c
+
+// Reserved address 0xc70
+
+// Reserved address 0xc74
+
+// Reserved address 0xc78
+
+// Reserved address 0xc7c
+
+// Reserved address 0xc80
+
+// Reserved address 0xc84
+
+// Reserved address 0xc88
+
+// Reserved address 0xc8c
+
+// Reserved address 0xc90
+
+// Reserved address 0xc94
+
+// Reserved address 0xc98
+
+// Reserved address 0xc9c
+
+// Reserved address 0xca0
+
+// Reserved address 0xca4
+
+// Reserved address 0xca8
+
+// Reserved address 0xcac
+
+// Reserved address 0xcb0
+
+// Reserved address 0xcb4
+
+// Reserved address 0xcb8
+
+// Reserved address 0xcbc
+
+// Reserved address 0xcc0
+
+// Reserved address 0xcc4
+
+// Reserved address 0xcc8
+
+// Reserved address 0xccc
+
+// Reserved address 0xcd0
+
+// Reserved address 0xcd4
+
+// Reserved address 0xcd8
+
+// Reserved address 0xcdc
+
+// Reserved address 0xce0
+
+// Reserved address 0xce4
+
+// Reserved address 0xce8
+
+// Reserved address 0xcec
+
+// Reserved address 0xcf0
+
+// Reserved address 0xcf4
+
+// Reserved address 0xcf8
+
+// Reserved address 0xcfc
+
+// Reserved address 0xd00
+
+// Reserved address 0xd04
+
+// Reserved address 0xd08
+
+// Reserved address 0xd0c
+
+// Reserved address 0xd10
+
+// Reserved address 0xd14
+
+// Reserved address 0xd18
+
+// Reserved address 0xd1c
+
+// Reserved address 0xd20
+
+// Reserved address 0xd24
+
+// Reserved address 0xd28
+
+// Reserved address 0xd2c
+
+// Reserved address 0xd30
+
+// Reserved address 0xd34
+
+// Reserved address 0xd38
+
+// Reserved address 0xd3c
+
+// Reserved address 0xd40
+
+// Reserved address 0xd44
+
+// Reserved address 0xd48
+
+// Reserved address 0xd4c
+
+// Reserved address 0xd50
+
+// Reserved address 0xd54
+
+// Reserved address 0xd58
+
+// Reserved address 0xd5c
+
+// Reserved address 0xd60
+
+// Reserved address 0xd64
+
+// Reserved address 0xd68
+
+// Reserved address 0xd6c
+
+// Reserved address 0xd70
+
+// Reserved address 0xd74
+
+// Reserved address 0xd78
+
+// Reserved address 0xd7c
+
+// Reserved address 0xd80
+
+// Reserved address 0xd84
+
+// Reserved address 0xd88
+
+// Reserved address 0xd8c
+
+// Reserved address 0xd90
+
+// Reserved address 0xd94
+
+// Reserved address 0xd98
+
+// Reserved address 0xd9c
+
+// Reserved address 0xda0
+
+// Reserved address 0xda4
+
+// Reserved address 0xda8
+
+// Reserved address 0xdac
+
+// Reserved address 0xdb0
+
+// Reserved address 0xdb4
+
+// Reserved address 0xdb8
+
+// Reserved address 0xdbc
+
+// Reserved address 0xdc0
+
+// Reserved address 0xdc4
+
+// Reserved address 0xdc8
+
+// Reserved address 0xdcc
+
+// Reserved address 0xdd0
+
+// Reserved address 0xdd4
+
+// Reserved address 0xdd8
+
+// Reserved address 0xddc
+
+// Reserved address 0xde0
+
+// Reserved address 0xde4
+
+// Reserved address 0xde8
+
+// Reserved address 0xdec
+
+// Reserved address 0xdf0
+
+// Reserved address 0xdf4
+
+// Reserved address 0xdf8
+
+// Reserved address 0xdfc
+
+// Reserved address 0xe00
+
+// Reserved address 0xe04
+
+// Reserved address 0xe08
+
+// Reserved address 0xe0c
+
+// Reserved address 0xe10
+
+// Reserved address 0xe14
+
+// Reserved address 0xe18
+
+// Reserved address 0xe1c
+
+// Reserved address 0xe20
+
+// Reserved address 0xe24
+
+// Reserved address 0xe28
+
+// Reserved address 0xe2c
+
+// Reserved address 0xe30
+
+// Reserved address 0xe34
+
+// Reserved address 0xe38
+
+// Reserved address 0xe3c
+
+// Reserved address 0xe40
+
+// Reserved address 0xe44
+
+// Reserved address 0xe48
+
+// Reserved address 0xe4c
+
+// Reserved address 0xe50
+
+// Reserved address 0xe54
+
+// Reserved address 0xe58
+
+// Reserved address 0xe5c
+
+// Reserved address 0xe60
+
+// Reserved address 0xe64
+
+// Reserved address 0xe68
+
+// Reserved address 0xe6c
+
+// Reserved address 0xe70
+
+// Reserved address 0xe74
+
+// Reserved address 0xe78
+
+// Reserved address 0xe7c
+
+// Reserved address 0xe80
+
+// Reserved address 0xe84
+
+// Reserved address 0xe88
+
+// Reserved address 0xe8c
+
+// Reserved address 0xe90
+
+// Reserved address 0xe94
+
+// Reserved address 0xe98
+
+// Reserved address 0xe9c
+
+// Reserved address 0xea0
+
+// Reserved address 0xea4
+
+// Reserved address 0xea8
+
+// Reserved address 0xeac
+
+// Reserved address 0xeb0
+
+// Reserved address 0xeb4
+
+// Reserved address 0xeb8
+
+// Reserved address 0xebc
+
+// Reserved address 0xec0
+
+// Reserved address 0xec4
+
+// Reserved address 0xec8
+
+// Reserved address 0xecc
+
+// Reserved address 0xed0
+
+// Reserved address 0xed4
+
+// Reserved address 0xed8
+
+// Reserved address 0xedc
+
+// Reserved address 0xee0
+
+// Reserved address 0xee4
+
+// Reserved address 0xee8
+
+// Reserved address 0xeec
+
+// Reserved address 0xef0
+
+// Reserved address 0xef4
+
+// Reserved address 0xef8
+
+// Reserved address 0xefc
+
+// Register APS_VIC_VICADDRESS_0
+#define APS_VIC_VICADDRESS_0                    MK_ADDR_CONST(0xf00)
+#define APS_VIC_VICADDRESS_0_SECURE                     0x0
+#define APS_VIC_VICADDRESS_0_DUAL                       0x0
+#define APS_VIC_VICADDRESS_0_SCR                        0
+#define APS_VIC_VICADDRESS_0_SCRREG                     0
+#define APS_VIC_VICADDRESS_0_WORD_COUNT                         0x1
+#define APS_VIC_VICADDRESS_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICADDRESS_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICADDRESS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICADDRESS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICADDRESS_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICADDRESS_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICADDRESS_0_VICADDRESS_SHIFT                   MK_SHIFT_CONST(0)
+#define APS_VIC_VICADDRESS_0_VICADDRESS_FIELD                   MK_FIELD_CONST(0xffffffff, APS_VIC_VICADDRESS_0_VICADDRESS_SHIFT)
+#define APS_VIC_VICADDRESS_0_VICADDRESS_RANGE                   31:0
+#define APS_VIC_VICADDRESS_0_VICADDRESS_MSB                     MK_SHIFT_CONST(31)
+#define APS_VIC_VICADDRESS_0_VICADDRESS_LSB                     MK_SHIFT_CONST(0)
+#define APS_VIC_VICADDRESS_0_VICADDRESS_WOFFSET                 0x0
+#define APS_VIC_VICADDRESS_0_VICADDRESS_DEFAULT                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICADDRESS_0_VICADDRESS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define APS_VIC_VICADDRESS_0_VICADDRESS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define APS_VIC_VICADDRESS_0_VICADDRESS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define APS_VIC_VICADDRESS_0_VICADDRESS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICADDRESS_0_VICADDRESS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xf04
+
+// Reserved address 0xf08
+
+// Reserved address 0xf0c
+
+// Reserved address 0xf10
+
+// Reserved address 0xf14
+
+// Reserved address 0xf18
+
+// Reserved address 0xf1c
+
+// Reserved address 0xf20
+
+// Reserved address 0xf24
+
+// Reserved address 0xf28
+
+// Reserved address 0xf2c
+
+// Reserved address 0xf30
+
+// Reserved address 0xf34
+
+// Reserved address 0xf38
+
+// Reserved address 0xf3c
+
+// Reserved address 0xf40
+
+// Reserved address 0xf44
+
+// Reserved address 0xf48
+
+// Reserved address 0xf4c
+
+// Reserved address 0xf50
+
+// Reserved address 0xf54
+
+// Reserved address 0xf58
+
+// Reserved address 0xf5c
+
+// Reserved address 0xf60
+
+// Reserved address 0xf64
+
+// Reserved address 0xf68
+
+// Reserved address 0xf6c
+
+// Reserved address 0xf70
+
+// Reserved address 0xf74
+
+// Reserved address 0xf78
+
+// Reserved address 0xf7c
+
+// Reserved address 0xf80
+
+// Reserved address 0xf84
+
+// Reserved address 0xf88
+
+// Reserved address 0xf8c
+
+// Reserved address 0xf90
+
+// Reserved address 0xf94
+
+// Reserved address 0xf98
+
+// Reserved address 0xf9c
+
+// Reserved address 0xfa0
+
+// Reserved address 0xfa4
+
+// Reserved address 0xfa8
+
+// Reserved address 0xfac
+
+// Reserved address 0xfb0
+
+// Reserved address 0xfb4
+
+// Reserved address 0xfb8
+
+// Reserved address 0xfbc
+
+// Reserved address 0xfc0
+
+// Reserved address 0xfc4
+
+// Reserved address 0xfc8
+
+// Reserved address 0xfcc
+
+// Reserved address 0xfd0
+
+// Reserved address 0xfd4
+
+// Reserved address 0xfd8
+
+// Reserved address 0xfdc
+
+// Register APS_VIC_VICPERIPHID0_0
+#define APS_VIC_VICPERIPHID0_0                  MK_ADDR_CONST(0xfe0)
+#define APS_VIC_VICPERIPHID0_0_SECURE                   0x0
+#define APS_VIC_VICPERIPHID0_0_DUAL                     0x0
+#define APS_VIC_VICPERIPHID0_0_SCR                      0
+#define APS_VIC_VICPERIPHID0_0_SCRREG                   0
+#define APS_VIC_VICPERIPHID0_0_WORD_COUNT                       0x1
+#define APS_VIC_VICPERIPHID0_0_RESET_VAL                        MK_MASK_CONST(0x92)
+#define APS_VIC_VICPERIPHID0_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define APS_VIC_VICPERIPHID0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID0_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define APS_VIC_VICPERIPHID0_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_FIELD                       MK_FIELD_CONST(0xff, APS_VIC_VICPERIPHID0_0_VICPERIPHID0_SHIFT)
+#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_RANGE                       7:0
+#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_MSB                 MK_SHIFT_CONST(7)
+#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_WOFFSET                     0x0
+#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_DEFAULT                     MK_MASK_CONST(0x92)
+#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID0_0_VICPERIPHID0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICPERIPHID1_0
+#define APS_VIC_VICPERIPHID1_0                  MK_ADDR_CONST(0xfe4)
+#define APS_VIC_VICPERIPHID1_0_SECURE                   0x0
+#define APS_VIC_VICPERIPHID1_0_DUAL                     0x0
+#define APS_VIC_VICPERIPHID1_0_SCR                      0
+#define APS_VIC_VICPERIPHID1_0_SCRREG                   0
+#define APS_VIC_VICPERIPHID1_0_WORD_COUNT                       0x1
+#define APS_VIC_VICPERIPHID1_0_RESET_VAL                        MK_MASK_CONST(0x11)
+#define APS_VIC_VICPERIPHID1_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define APS_VIC_VICPERIPHID1_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID1_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID1_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define APS_VIC_VICPERIPHID1_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_FIELD                       MK_FIELD_CONST(0xff, APS_VIC_VICPERIPHID1_0_VICPERIPHID1_SHIFT)
+#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_RANGE                       7:0
+#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_MSB                 MK_SHIFT_CONST(7)
+#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_WOFFSET                     0x0
+#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_DEFAULT                     MK_MASK_CONST(0x11)
+#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID1_0_VICPERIPHID1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICPERIPHID2_0
+#define APS_VIC_VICPERIPHID2_0                  MK_ADDR_CONST(0xfe8)
+#define APS_VIC_VICPERIPHID2_0_SECURE                   0x0
+#define APS_VIC_VICPERIPHID2_0_DUAL                     0x0
+#define APS_VIC_VICPERIPHID2_0_SCR                      0
+#define APS_VIC_VICPERIPHID2_0_SCRREG                   0
+#define APS_VIC_VICPERIPHID2_0_WORD_COUNT                       0x1
+#define APS_VIC_VICPERIPHID2_0_RESET_VAL                        MK_MASK_CONST(0x4)
+#define APS_VIC_VICPERIPHID2_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define APS_VIC_VICPERIPHID2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID2_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define APS_VIC_VICPERIPHID2_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_FIELD                       MK_FIELD_CONST(0xff, APS_VIC_VICPERIPHID2_0_VICPERIPHID2_SHIFT)
+#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_RANGE                       7:0
+#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_MSB                 MK_SHIFT_CONST(7)
+#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_WOFFSET                     0x0
+#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_DEFAULT                     MK_MASK_CONST(0x4)
+#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID2_0_VICPERIPHID2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICPERIPHID3_0
+#define APS_VIC_VICPERIPHID3_0                  MK_ADDR_CONST(0xfec)
+#define APS_VIC_VICPERIPHID3_0_SECURE                   0x0
+#define APS_VIC_VICPERIPHID3_0_DUAL                     0x0
+#define APS_VIC_VICPERIPHID3_0_SCR                      0
+#define APS_VIC_VICPERIPHID3_0_SCRREG                   0
+#define APS_VIC_VICPERIPHID3_0_WORD_COUNT                       0x1
+#define APS_VIC_VICPERIPHID3_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID3_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define APS_VIC_VICPERIPHID3_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID3_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID3_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define APS_VIC_VICPERIPHID3_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_SHIFT                       MK_SHIFT_CONST(0)
+#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_FIELD                       MK_FIELD_CONST(0xff, APS_VIC_VICPERIPHID3_0_VICPERIPHID3_SHIFT)
+#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_RANGE                       7:0
+#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_MSB                 MK_SHIFT_CONST(7)
+#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_LSB                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_WOFFSET                     0x0
+#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_DEFAULT                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICPERIPHID3_0_VICPERIPHID3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICPCELLID0_0
+#define APS_VIC_VICPCELLID0_0                   MK_ADDR_CONST(0xff0)
+#define APS_VIC_VICPCELLID0_0_SECURE                    0x0
+#define APS_VIC_VICPCELLID0_0_DUAL                      0x0
+#define APS_VIC_VICPCELLID0_0_SCR                       0
+#define APS_VIC_VICPCELLID0_0_SCRREG                    0
+#define APS_VIC_VICPCELLID0_0_WORD_COUNT                        0x1
+#define APS_VIC_VICPCELLID0_0_RESET_VAL                         MK_MASK_CONST(0xd)
+#define APS_VIC_VICPCELLID0_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define APS_VIC_VICPCELLID0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID0_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define APS_VIC_VICPCELLID0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID0_0_VICPCELLID0_SHIFT                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICPCELLID0_0_VICPCELLID0_FIELD                 MK_FIELD_CONST(0xff, APS_VIC_VICPCELLID0_0_VICPCELLID0_SHIFT)
+#define APS_VIC_VICPCELLID0_0_VICPCELLID0_RANGE                 7:0
+#define APS_VIC_VICPCELLID0_0_VICPCELLID0_MSB                   MK_SHIFT_CONST(7)
+#define APS_VIC_VICPCELLID0_0_VICPCELLID0_LSB                   MK_SHIFT_CONST(0)
+#define APS_VIC_VICPCELLID0_0_VICPCELLID0_WOFFSET                       0x0
+#define APS_VIC_VICPCELLID0_0_VICPCELLID0_DEFAULT                       MK_MASK_CONST(0xd)
+#define APS_VIC_VICPCELLID0_0_VICPCELLID0_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define APS_VIC_VICPCELLID0_0_VICPCELLID0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID0_0_VICPCELLID0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID0_0_VICPCELLID0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID0_0_VICPCELLID0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICPCELLID1_0
+#define APS_VIC_VICPCELLID1_0                   MK_ADDR_CONST(0xff4)
+#define APS_VIC_VICPCELLID1_0_SECURE                    0x0
+#define APS_VIC_VICPCELLID1_0_DUAL                      0x0
+#define APS_VIC_VICPCELLID1_0_SCR                       0
+#define APS_VIC_VICPCELLID1_0_SCRREG                    0
+#define APS_VIC_VICPCELLID1_0_WORD_COUNT                        0x1
+#define APS_VIC_VICPCELLID1_0_RESET_VAL                         MK_MASK_CONST(0xf0)
+#define APS_VIC_VICPCELLID1_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define APS_VIC_VICPCELLID1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID1_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define APS_VIC_VICPCELLID1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID1_0_VICPCELLID1_SHIFT                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICPCELLID1_0_VICPCELLID1_FIELD                 MK_FIELD_CONST(0xff, APS_VIC_VICPCELLID1_0_VICPCELLID1_SHIFT)
+#define APS_VIC_VICPCELLID1_0_VICPCELLID1_RANGE                 7:0
+#define APS_VIC_VICPCELLID1_0_VICPCELLID1_MSB                   MK_SHIFT_CONST(7)
+#define APS_VIC_VICPCELLID1_0_VICPCELLID1_LSB                   MK_SHIFT_CONST(0)
+#define APS_VIC_VICPCELLID1_0_VICPCELLID1_WOFFSET                       0x0
+#define APS_VIC_VICPCELLID1_0_VICPCELLID1_DEFAULT                       MK_MASK_CONST(0xf0)
+#define APS_VIC_VICPCELLID1_0_VICPCELLID1_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define APS_VIC_VICPCELLID1_0_VICPCELLID1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID1_0_VICPCELLID1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID1_0_VICPCELLID1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID1_0_VICPCELLID1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICPCELLID2_0
+#define APS_VIC_VICPCELLID2_0                   MK_ADDR_CONST(0xff8)
+#define APS_VIC_VICPCELLID2_0_SECURE                    0x0
+#define APS_VIC_VICPCELLID2_0_DUAL                      0x0
+#define APS_VIC_VICPCELLID2_0_SCR                       0
+#define APS_VIC_VICPCELLID2_0_SCRREG                    0
+#define APS_VIC_VICPCELLID2_0_WORD_COUNT                        0x1
+#define APS_VIC_VICPCELLID2_0_RESET_VAL                         MK_MASK_CONST(0x5)
+#define APS_VIC_VICPCELLID2_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define APS_VIC_VICPCELLID2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID2_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define APS_VIC_VICPCELLID2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID2_0_VICPCELLID2_SHIFT                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICPCELLID2_0_VICPCELLID2_FIELD                 MK_FIELD_CONST(0xff, APS_VIC_VICPCELLID2_0_VICPCELLID2_SHIFT)
+#define APS_VIC_VICPCELLID2_0_VICPCELLID2_RANGE                 7:0
+#define APS_VIC_VICPCELLID2_0_VICPCELLID2_MSB                   MK_SHIFT_CONST(7)
+#define APS_VIC_VICPCELLID2_0_VICPCELLID2_LSB                   MK_SHIFT_CONST(0)
+#define APS_VIC_VICPCELLID2_0_VICPCELLID2_WOFFSET                       0x0
+#define APS_VIC_VICPCELLID2_0_VICPCELLID2_DEFAULT                       MK_MASK_CONST(0x5)
+#define APS_VIC_VICPCELLID2_0_VICPCELLID2_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define APS_VIC_VICPCELLID2_0_VICPCELLID2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID2_0_VICPCELLID2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID2_0_VICPCELLID2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID2_0_VICPCELLID2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register APS_VIC_VICPCELLID3_0
+#define APS_VIC_VICPCELLID3_0                   MK_ADDR_CONST(0xffc)
+#define APS_VIC_VICPCELLID3_0_SECURE                    0x0
+#define APS_VIC_VICPCELLID3_0_DUAL                      0x0
+#define APS_VIC_VICPCELLID3_0_SCR                       0
+#define APS_VIC_VICPCELLID3_0_SCRREG                    0
+#define APS_VIC_VICPCELLID3_0_WORD_COUNT                        0x1
+#define APS_VIC_VICPCELLID3_0_RESET_VAL                         MK_MASK_CONST(0xb1)
+#define APS_VIC_VICPCELLID3_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define APS_VIC_VICPCELLID3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID3_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define APS_VIC_VICPCELLID3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID3_0_VICPCELLID3_SHIFT                 MK_SHIFT_CONST(0)
+#define APS_VIC_VICPCELLID3_0_VICPCELLID3_FIELD                 MK_FIELD_CONST(0xff, APS_VIC_VICPCELLID3_0_VICPCELLID3_SHIFT)
+#define APS_VIC_VICPCELLID3_0_VICPCELLID3_RANGE                 7:0
+#define APS_VIC_VICPCELLID3_0_VICPCELLID3_MSB                   MK_SHIFT_CONST(7)
+#define APS_VIC_VICPCELLID3_0_VICPCELLID3_LSB                   MK_SHIFT_CONST(0)
+#define APS_VIC_VICPCELLID3_0_VICPCELLID3_WOFFSET                       0x0
+#define APS_VIC_VICPCELLID3_0_VICPCELLID3_DEFAULT                       MK_MASK_CONST(0xb1)
+#define APS_VIC_VICPCELLID3_0_VICPCELLID3_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define APS_VIC_VICPCELLID3_0_VICPCELLID3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID3_0_VICPCELLID3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID3_0_VICPCELLID3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define APS_VIC_VICPCELLID3_0_VICPCELLID3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARAPS_VIC_REGS(_op_) \
+_op_(APS_VIC_VICIRQSTATUS_0) \
+_op_(APS_VIC_VICFIQSTATUS_0) \
+_op_(APS_VIC_VICRAWINTR_0) \
+_op_(APS_VIC_VICINTSELECT_0) \
+_op_(APS_VIC_VICINTENABLE_0) \
+_op_(APS_VIC_VICINTENCLEAR_0) \
+_op_(APS_VIC_VICSOFTINT_0) \
+_op_(APS_VIC_VICSOFTINTCLEAR_0) \
+_op_(APS_VIC_VICPROTECTION_0) \
+_op_(APS_VIC_VICSWPRIORITY_0) \
+_op_(APS_VIC_VICPRIORITYDAISY_0) \
+_op_(APS_VIC_VICVECTADDR0_0) \
+_op_(APS_VIC_VICVECTADDR1_0) \
+_op_(APS_VIC_VICVECTADDR2_0) \
+_op_(APS_VIC_VICVECTADDR3_0) \
+_op_(APS_VIC_VICVECTADDR4_0) \
+_op_(APS_VIC_VICVECTADDR5_0) \
+_op_(APS_VIC_VICVECTADDR6_0) \
+_op_(APS_VIC_VICVECTADDR7_0) \
+_op_(APS_VIC_VICVECTADDR8_0) \
+_op_(APS_VIC_VICVECTADDR9_0) \
+_op_(APS_VIC_VICVECTADDR10_0) \
+_op_(APS_VIC_VICVECTADDR11_0) \
+_op_(APS_VIC_VICVECTADDR12_0) \
+_op_(APS_VIC_VICVECTADDR13_0) \
+_op_(APS_VIC_VICVECTADDR14_0) \
+_op_(APS_VIC_VICVECTADDR15_0) \
+_op_(APS_VIC_VICVECTADDR16_0) \
+_op_(APS_VIC_VICVECTADDR17_0) \
+_op_(APS_VIC_VICVECTADDR18_0) \
+_op_(APS_VIC_VICVECTADDR19_0) \
+_op_(APS_VIC_VICVECTADDR20_0) \
+_op_(APS_VIC_VICVECTADDR21_0) \
+_op_(APS_VIC_VICVECTADDR22_0) \
+_op_(APS_VIC_VICVECTADDR23_0) \
+_op_(APS_VIC_VICVECTADDR24_0) \
+_op_(APS_VIC_VICVECTADDR25_0) \
+_op_(APS_VIC_VICVECTADDR26_0) \
+_op_(APS_VIC_VICVECTADDR27_0) \
+_op_(APS_VIC_VICVECTADDR28_0) \
+_op_(APS_VIC_VICVECTADDR29_0) \
+_op_(APS_VIC_VICVECTADDR30_0) \
+_op_(APS_VIC_VICVECTADDR31_0) \
+_op_(APS_VIC_VICVECTPRIORITY0_0) \
+_op_(APS_VIC_VICVECTPRIORITY1_0) \
+_op_(APS_VIC_VICVECTPRIORITY2_0) \
+_op_(APS_VIC_VICVECTPRIORITY3_0) \
+_op_(APS_VIC_VICVECTPRIORITY4_0) \
+_op_(APS_VIC_VICVECTPRIORITY5_0) \
+_op_(APS_VIC_VICVECTPRIORITY6_0) \
+_op_(APS_VIC_VICVECTPRIORITY7_0) \
+_op_(APS_VIC_VICVECTPRIORITY8_0) \
+_op_(APS_VIC_VICVECTPRIORITY9_0) \
+_op_(APS_VIC_VICVECTPRIORITY10_0) \
+_op_(APS_VIC_VICVECTPRIORITY11_0) \
+_op_(APS_VIC_VICVECTPRIORITY12_0) \
+_op_(APS_VIC_VICVECTPRIORITY13_0) \
+_op_(APS_VIC_VICVECTPRIORITY14_0) \
+_op_(APS_VIC_VICVECTPRIORITY15_0) \
+_op_(APS_VIC_VICVECTPRIORITY16_0) \
+_op_(APS_VIC_VICVECTPRIORITY17_0) \
+_op_(APS_VIC_VICVECTPRIORITY18_0) \
+_op_(APS_VIC_VICVECTPRIORITY19_0) \
+_op_(APS_VIC_VICVECTPRIORITY20_0) \
+_op_(APS_VIC_VICVECTPRIORITY21_0) \
+_op_(APS_VIC_VICVECTPRIORITY22_0) \
+_op_(APS_VIC_VICVECTPRIORITY23_0) \
+_op_(APS_VIC_VICVECTPRIORITY24_0) \
+_op_(APS_VIC_VICVECTPRIORITY25_0) \
+_op_(APS_VIC_VICVECTPRIORITY26_0) \
+_op_(APS_VIC_VICVECTPRIORITY27_0) \
+_op_(APS_VIC_VICVECTPRIORITY28_0) \
+_op_(APS_VIC_VICVECTPRIORITY29_0) \
+_op_(APS_VIC_VICVECTPRIORITY30_0) \
+_op_(APS_VIC_VICVECTPRIORITY31_0) \
+_op_(APS_VIC_VICITCR_0) \
+_op_(APS_VIC_VICITIP1_0) \
+_op_(APS_VIC_VICITIP2_0) \
+_op_(APS_VIC_VICITOP1_0) \
+_op_(APS_VIC_VICITOP2_0) \
+_op_(APS_VIC_VICINTSSTATUS_0) \
+_op_(APS_VIC_VICINTSSTATUSCLEAR_0) \
+_op_(APS_VIC_VICADDRESS_0) \
+_op_(APS_VIC_VICPERIPHID0_0) \
+_op_(APS_VIC_VICPERIPHID1_0) \
+_op_(APS_VIC_VICPERIPHID2_0) \
+_op_(APS_VIC_VICPERIPHID3_0) \
+_op_(APS_VIC_VICPCELLID0_0) \
+_op_(APS_VIC_VICPCELLID1_0) \
+_op_(APS_VIC_VICPCELLID2_0) \
+_op_(APS_VIC_VICPCELLID3_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_APS_VIC    0x00000000
+
+//
+// ARAPS_VIC REGISTER BANKS
+//
+
+#define APS_VIC0_FIRST_REG 0x0000 // APS_VIC_VICIRQSTATUS_0
+#define APS_VIC0_LAST_REG 0x0028 // APS_VIC_VICPRIORITYDAISY_0
+#define APS_VIC1_FIRST_REG 0x0100 // APS_VIC_VICVECTADDR0_0
+#define APS_VIC1_LAST_REG 0x017c // APS_VIC_VICVECTADDR31_0
+#define APS_VIC2_FIRST_REG 0x0200 // APS_VIC_VICVECTPRIORITY0_0
+#define APS_VIC2_LAST_REG 0x027c // APS_VIC_VICVECTPRIORITY31_0
+#define APS_VIC3_FIRST_REG 0x0300 // APS_VIC_VICITCR_0
+#define APS_VIC3_LAST_REG 0x0318 // APS_VIC_VICINTSSTATUSCLEAR_0
+#define APS_VIC4_FIRST_REG 0x0f00 // APS_VIC_VICADDRESS_0
+#define APS_VIC4_LAST_REG 0x0f00 // APS_VIC_VICADDRESS_0
+#define APS_VIC5_FIRST_REG 0x0fe0 // APS_VIC_VICPERIPHID0_0
+#define APS_VIC5_LAST_REG 0x0ffc // APS_VIC_VICPCELLID3_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARAPS_VIC_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arclk_rst.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arclk_rst.h
new file mode 100644
index 0000000..18ed041
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arclk_rst.h
@@ -0,0 +1,385 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+
+#ifndef ARCLK_RST_H
+#define ARCLK_RST_H
+
+#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0                                          MK_ADDR_CONST(0xb40004)
+#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_ENABLE                 MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0                                      MK_ADDR_CONST(0xb41004)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_LSB                MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_SET_0_SET_CLK_ENB_UARTC_ENABLE             MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0                                           MK_ADDR_CONST(0xb43000)
+#define CLK_RST_CONTROLLER_RST_DEV_UARTC_SET_0_SET_SWR_UARTC_RST_LSB                    MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_ENABLE                 MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0_CLR_SWR_UARTC_RST_LSB                    MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEV_UARTC_CLR_0                                          MK_ADDR_CONST(0xb40008)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_MSB                         MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_SRC_OSC_UNDIV                   MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_MSB                         MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_LSB                         MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC_0_UARTC_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0                                                MK_ADDR_CONST(0xbe0000)
+#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0                                              MK_ADDR_CONST(0xbe0008)
+#define CLK_RST_CONTROLLER_PLLP_BASE_0                                                  MK_ADDR_CONST(0x7000c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_pllAON_out      MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_LSB             MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_PLLP_OUT0       MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_OSC_UNDIV       MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_CLK_S           MK_ENUM_CONST(6)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0                          MK_ADDR_CONST(0xc30060)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0                   MK_ADDR_CONST(0xc30064)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0                    MK_ADDR_CONST(0xc30068)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0                       MK_ADDR_CONST(0xc3006c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0                    MK_ADDR_CONST(0xc30070)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0                       MK_ADDR_CONST(0xc30074)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0                 MK_ADDR_CONST(0xc30078)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0                    MK_ADDR_CONST(0xc3007c)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0                              MK_ADDR_CONST(0xc300a0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0                       MK_ADDR_CONST(0xc300a4)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0                        MK_ADDR_CONST(0xc300a8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0                           MK_ADDR_CONST(0xc300ac)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0                        MK_ADDR_CONST(0xc300b0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0                           MK_ADDR_CONST(0xc300b4)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0                     MK_ADDR_CONST(0xc300b8)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0                        MK_ADDR_CONST(0xc300bc)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0                                     MK_ADDR_CONST(0xb03000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0                                         MK_ADDR_CONST(0xb32000)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_LSB                                MK_SHIFT_CONST(20)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVP_MSB                                MK_SHIFT_CONST(25)
+#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_LSB                              MK_SHIFT_CONST(16)
+#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_MSB                              MK_SHIFT_CONST(23)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_LSB                                MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_LSB                                MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVM_MSB                                MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_LSB                         MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_DIVN_FRAC_MSB                         MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0                                                   MK_ADDR_CONST(0xbf0000)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_LSB                                      MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_MSB                                      MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC12                                    MK_ENUM_CONST(8)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC13                                    MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC16P8                                  MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC19P2                                  MK_ENUM_CONST(4)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC26                                    MK_ENUM_CONST(12)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC38P4                                  MK_ENUM_CONST(5)
+#define CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC48                                    MK_ENUM_CONST(9)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_MSB         MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_DIVISOR_LSB         MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0                                   MK_ADDR_CONST(0xc300c0)
+#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_LSB                MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_ACK_MSB                MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_MSB              MK_SHIFT_CONST(2)
+#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_STATE_LSB              MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_MSB                MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0_AON_SW_TGT_REQ_LSB                MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_SHIFT                         MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_SHIFT                              MK_SHIFT_CONST(26)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_MSB                              MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_LSB                              MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_DISABLE                          MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_MSB                              MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_LSB                              MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_ON                               MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_MSB                              MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_LSB                              MK_SHIFT_CONST(27)
+#define CLK_RST_CONTROLLER_PLLAON_MISC_1_0_PLLAON_IDDQ_OFF                              MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_MSB                              MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_LSB                              MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_ENABLE_ENABLE                           MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_MSB                     MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_LSB                     MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_PLLP_OUT0               MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_MSB                 MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_DIVISOR_LSB                 MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_pllAON_out              MK_ENUM_CONST(2)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0_AON_APB_CLK_SRC_OSC_UNDIV               MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0_AON_CPU_NIC_CLK_SRC_MSB             MK_SHIFT_CONST(31)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_LSB                                MK_SHIFT_CONST(10)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_DIVN_MSB                                MK_SHIFT_CONST(17)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0                                     MK_ADDR_CONST(0xc30080)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_SHIFT       MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_FIELD       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_SHIFT     MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_FIELD     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_MSB         MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_IDDQ_LSB         MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_MSB       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_0_AON_PLL_ACTIVE_PLL_ENABLE_LSB       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0                              MK_ADDR_CONST(0xc30084)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0                                  MK_ADDR_CONST(0xc3008c)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0                               MK_ADDR_CONST(0xc30090)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0                                  MK_ADDR_CONST(0xc30094)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0                               MK_ADDR_CONST(0xc30088)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0                            MK_ADDR_CONST(0xc30098)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0                               MK_ADDR_CONST(0xc3009c)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT       MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_FIELD       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT     MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_FIELD     MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_MSB         MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_IDDQ_LSB         MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_MSB       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_ACTIVE_IRQFIQ_0_AON_PLL_ACTIVE_IRQFIQ_PLL_ENABLE_LSB       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT         MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_FIELD         MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_FIELD       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_MSB           MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_MSB           MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_MSB         MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_ENABLE_LSB         MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_SHIFT               MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_FIELD               MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_SHIFT             MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_FIELD             MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_MSB                 MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_LSB                 MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_IDDQ_LSB                 MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_MSB               MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_DEEP_0_AON_PLL_IDLE_DEEP_PLL_ENABLE_LSB               MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT         MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_FIELD         MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT         MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_FIELD         MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_MSB           MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_IDDQ_LSB           MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_MSB         MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_LSB         MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_SHIFT               MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_FIELD               MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_SHIFT             MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_FIELD             MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_MSB                 MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_IDDQ_LSB                 MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_MSB               MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_DEEP_0_AON_PLL_STBY_DEEP_PLL_ENABLE_LSB               MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT   MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_FIELD   MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_FIELD MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_MSB     MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_IDDQ_LSB     MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_MSB   MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_SHIFT         MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_FIELD         MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_SHIFT       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_FIELD       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_MSB           MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_LSB           MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_IDDQ_LSB           MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_MSB         MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_DEEP_0_AON_PLL_DORMANT_DEEP_PLL_ENABLE_LSB         MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_IDLE_SHALLOW_0_AON_PLL_IDLE_SHALLOW_PLL_IDDQ_LSB           MK_SHIFT_CONST(1)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_FIELD       MK_FIELD_CONST(0x1, CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_STBY_SHALLOW_0_AON_PLL_STBY_SHALLOW_PLL_ENABLE_SHIFT)
+#define CLK_RST_CONTROLLER_PLL_CFG_AON_TGT_DORMANT_SHALLOW_0_AON_PLL_DORMANT_SHALLOW_PLL_ENABLE_LSB   MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0                                              MK_ADDR_CONST(0xbe0004)
+#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_MSB                             MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLAON_MISC_0_0_PLLAON_RESET_LSB                             MK_SHIFT_CONST(30)
+#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0                                              MK_ADDR_CONST(0xbe0014)
+#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_MSB                          MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_PLLAON_MISC_4_0_PLLAON_SEL_IREF_LSB                          MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_MSB                            MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_OVERRIDE_LSB                            MK_SHIFT_CONST(28)
+#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_MSB                   MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_SWDIV_SEQUENCER_EN_LSB                   MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_MSB                     MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0_AON_PLL_SEQUENCER_EN_LSB                     MK_SHIFT_CONST(6)
+#define CLK_RST_CONTROLLER_AON_SEQ_CTL_0_0                                              MK_ADDR_CONST(0xc300c4)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTA_0                                          MK_ADDR_CONST(0x1c1000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0                                           MK_ADDR_CONST(0x1c3000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_DIV_ENB_LSB                         MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA_0_UARTA_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_UARTA_0                                              MK_ADDR_CONST(0x1c0000)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTB_0                                          MK_ADDR_CONST(0x1d1000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0                                           MK_ADDR_CONST(0x1d3000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_DIV_ENB_LSB                         MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB_0_UARTB_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_UARTB_0                                              MK_ADDR_CONST(0x1d0000)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0                                          MK_ADDR_CONST(0xb41000)
+#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0                                              MK_ADDR_CONST(0xb40000)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTF_0                                          MK_ADDR_CONST(0x9e1000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0                                           MK_ADDR_CONST(0x9e3000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_DIV_ENB_LSB                         MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTF_0_UARTF_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_UARTF_0                                              MK_ADDR_CONST(0x9e0000)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTG_0                                          MK_ADDR_CONST(0xb51000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0                                           MK_ADDR_CONST(0xb53000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_OSC_UNDIV                   MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_DIV_ENB_LSB                         MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTG_0_UARTG_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_UARTG_0                                              MK_ADDR_CONST(0xb50000)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTH_0                                          MK_ADDR_CONST(0x1281000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0                                           MK_ADDR_CONST(0x1283000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_DIV_ENB_LSB                         MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTH_0_UARTH_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_UARTH_0                                              MK_ADDR_CONST(0x1280000)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_AON_I2C_SLOW_0                                   MK_ADDR_CONST(0xba0000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0                                    MK_ADDR_CONST(0xba2000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_LSB       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_DIVISOR_MSB       MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_PLLP_OUT0     MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW_0_AON_I2C_SLOW_CLK_SRC_LSB           MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C_SLOW_0                                       MK_ADDR_CONST(0x390000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0                                        MK_ADDR_CONST(0x392000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_LSB               MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_DIVISOR_MSB               MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_PLLP_OUT0             MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW_0_I2C_SLOW_CLK_SRC_LSB                   MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C1_0                                           MK_ADDR_CONST(0x121000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0                                            MK_ADDR_CONST(0x123000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1_0_I2C1_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_I2C1_0                                               MK_ADDR_CONST(0x120000)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C2_0                                           MK_ADDR_CONST(0xb71000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0                                            MK_ADDR_CONST(0xb73000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C2_0_I2C2_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_I2C2_0                                               MK_ADDR_CONST(0xb70000)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C3_0                                           MK_ADDR_CONST(0x241000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0                                            MK_ADDR_CONST(0x243000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C3_0_I2C3_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_I2C3_0                                               MK_ADDR_CONST(0x240000)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C8_0                                           MK_ADDR_CONST(0xb81000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0                                            MK_ADDR_CONST(0xb83000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C8_0_I2C8_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_I2C8_0                                               MK_ADDR_CONST(0xb80000)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C10_0                                          MK_ADDR_CONST(0xb91000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0                                           MK_ADDR_CONST(0xb93000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_PLLP_OUT0                   MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C10_0_I2C10_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_I2C10_0                                              MK_ADDR_CONST(0xb90000)
+#define CLK_RST_CONTROLLER_RST_DEV_AON_DMA_0                                            MK_ADDR_CONST(0xb00030)
+#define CLK_RST_CONTROLLER_RST_DEV_SCE_DMA_0                                            MK_ADDR_CONST(0xd00024)
+#define CLK_RST_CONTROLLER_RST_DEV_RCE_DMA_0                                            MK_ADDR_CONST(0x1000024)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_DMIC5_0                                          MK_ADDR_CONST(0xbc1000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0                                           MK_ADDR_CONST(0xbc3000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_OSC_UNDIV                   MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5_0_DMIC5_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_DMIC5_0                                              MK_ADDR_CONST(0xbc0000)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI1_0                                           MK_ADDR_CONST(0x141000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0                                            MK_ADDR_CONST(0x143000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI1_0_SPI1_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_SPI1_0                                               MK_ADDR_CONST(0x140000)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI2_0                                           MK_ADDR_CONST(0xbb1000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0                                            MK_ADDR_CONST(0xbb3000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI2_0_SPI2_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_SPI2_0                                               MK_ADDR_CONST(0xbb0000)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_SPI3_0                                           MK_ADDR_CONST(0x111000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0                                            MK_ADDR_CONST(0x113000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SPI3_0_SPI3_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_SPI3_0                                               MK_ADDR_CONST(0x110000)
+#define CLK_RST_CONTROLLER_RST_DEV_CAN1_0                                               MK_ADDR_CONST(0xb10000)
+#define CLK_RST_CONTROLLER_RST_DEV_CAN2_0                                               MK_ADDR_CONST(0xb20000)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTJ_0                                          MK_ADDR_CONST(0xc41000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ_0                                           MK_ADDR_CONST(0xc43000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ_0_UARTJ_CLK_DIVISOR_LSB                     MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ_0_UARTJ_CLK_DIVISOR_MSB                     MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ_0_UARTJ_DIV_ENB_ENABLE                      MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ_0_UARTJ_DIV_ENB_LSB                         MK_SHIFT_CONST(24)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ_0_UARTJ_CLK_SRC_OSC_UNDIV                   MK_ENUM_CONST(7)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTJ_0_UARTJ_CLK_SRC_LSB                         MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_UARTJ_0                                              MK_ADDR_CONST(0xc40000)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C4_0                                           MK_ADDR_CONST(0x321000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0                                            MK_ADDR_CONST(0x323000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C4_0_I2C4_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_I2C4_0                                               MK_ADDR_CONST(0x320000)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C6_0                                           MK_ADDR_CONST(0x531000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0                                            MK_ADDR_CONST(0x533000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C6_0_I2C6_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_I2C6_0                                               MK_ADDR_CONST(0x530000)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_I2C7_0                                           MK_ADDR_CONST(0x8f1000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0                                            MK_ADDR_CONST(0x8f3000)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_LSB                       MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_DIVISOR_MSB                       MK_SHIFT_CONST(15)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_PLLP_OUT0                     MK_ENUM_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C7_0_I2C7_CLK_SRC_LSB                           MK_SHIFT_CONST(29)
+#define CLK_RST_CONTROLLER_RST_DEV_I2C7_0                                               MK_ADDR_CONST(0x8f0000)
+#define CLK_RST_CONTROLLER_RST_DEV_DCE_DMA_0                                            MK_ADDR_CONST(0x1700024)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_LSB                        MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_MSB                        MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_CLK_OUT_ENB_UARTC_0_CLK_ENB_UARTC_ENABLE                     MK_ENUM_CONST(1)
+#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_LSB                            MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_MSB                            MK_SHIFT_CONST(0)
+#define CLK_RST_CONTROLLER_RST_DEV_UARTC_0_SWR_UARTC_RST_DISABLE                        MK_ENUM_CONST(0)
+
+#endif /* ARCLK_RST_H */
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arfuse.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arfuse.h
new file mode 100644
index 0000000..91699eb
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arfuse.h
@@ -0,0 +1,99 @@
+/*
+ * SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef ARFUSE_H_INC
+#define ARFUSE_H_INC
+
+// Register FUSE_OPT_FSI_DISABLE_0
+#define FUSE_OPT_FSI_DISABLE_0                  MK_ADDR_CONST(0x9c8)
+#define FUSE_OPT_FSI_DISABLE_0_SECURE                   0x0
+#define FUSE_OPT_FSI_DISABLE_0_DUAL                     0x0
+#define FUSE_OPT_FSI_DISABLE_0_SCR                      0
+#define FUSE_OPT_FSI_DISABLE_0_SCRREG                   0
+#define FUSE_OPT_FSI_DISABLE_0_WORD_COUNT                       0x1
+#define FUSE_OPT_FSI_DISABLE_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define FUSE_OPT_FSI_DISABLE_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define FUSE_OPT_FSI_DISABLE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define FUSE_OPT_FSI_DISABLE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define FUSE_OPT_FSI_DISABLE_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define FUSE_OPT_FSI_DISABLE_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_FIELD                    MK_FIELD_CONST(0x1, FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_SHIFT)
+#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_RANGE                    0:0
+#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_MSB                      MK_SHIFT_CONST(0)
+#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_LSB                      MK_SHIFT_CONST(0)
+#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_WOFFSET                  0x0
+#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define FUSE_OPT_FSI_DISABLE_0_OPT_FSI_DISABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+//
+// REGISTER LIST
+//
+#define LIST_ARFUSE_REGS(_op_) \
+_op_(FUSE_OPT_FSI_DISABLE_0) \
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARFUSE_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argpcdma_ao.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argpcdma_ao.h
new file mode 100644
index 0000000..7ca4fc8
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argpcdma_ao.h
@@ -0,0 +1,14484 @@
+//
+// Copyright (c) 2023 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARGPCDMA_AO_H_INC
+#define ARGPCDMA_AO_H_INC
+#define NV_MOBILE_ARGPCDMA_AO_H_UNIT_OF_OFFSET 1B
+
+
+// Register GPCDMA_AO_COMMON_DMA_CHAN_STA_0
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0                 MK_ADDR_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_SECURE                  0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_DUAL                    0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_SCR                     SCR_DMA_RO_0
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH0_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH0_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH0_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH0_RANGE                       0:0
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH0_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH0_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH0_WOFFSET                     0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH1_SHIFT                       MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH1_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH1_RANGE                       1:1
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH1_MSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH1_LSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH1_WOFFSET                     0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH2_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH2_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH2_RANGE                       2:2
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH2_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH2_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH2_WOFFSET                     0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH3_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH3_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH3_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH3_RANGE                       3:3
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH3_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH3_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH3_WOFFSET                     0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH4_SHIFT                       MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH4_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH4_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH4_RANGE                       4:4
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH4_MSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH4_LSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH4_WOFFSET                     0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH5_SHIFT                       MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH5_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH5_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH5_RANGE                       5:5
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH5_MSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH5_LSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH5_WOFFSET                     0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH6_SHIFT                       MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH6_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH6_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH6_RANGE                       6:6
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH6_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH6_LSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH6_WOFFSET                     0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH7_SHIFT                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH7_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH7_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH7_RANGE                       7:7
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH7_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH7_LSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH7_WOFFSET                     0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_STA_0_CH7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_REQUESTORS_TX_0
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0                        MK_ADDR_CONST(0x4)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_SECURE                         0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_DUAL                   0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_SCR                    SCR_DMA_RO_0
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_WORD_COUNT                     0x1
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_RESET_MASK                     MK_MASK_CONST(0x33f)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_READ_MASK                      MK_MASK_CONST(0x33f)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C1_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C1_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C1_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C1_RANGE                     0:0
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C1_MSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C1_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C1_WOFFSET                   0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C1_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C2_SHIFT                     MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C2_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C2_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C2_RANGE                     1:1
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C2_MSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C2_LSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C2_WOFFSET                   0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C2_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C2_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C3_SHIFT                     MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C3_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C3_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C3_RANGE                     2:2
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C3_MSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C3_LSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C3_WOFFSET                   0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C3_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C3_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_I2C3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_SPI_SHIFT                      MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_SPI_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_TX_0_SPI_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_SPI_RANGE                      3:3
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_SPI_MSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_SPI_LSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_SPI_WOFFSET                    0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_SPI_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_SPI_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_SPI_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_SPI_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_SPI_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_SPI_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART1_SHIFT                    MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART1_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART1_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART1_RANGE                    4:4
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART1_MSB                      MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART1_LSB                      MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART1_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART2_SHIFT                    MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART2_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART2_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART2_RANGE                    5:5
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART2_MSB                      MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART2_LSB                      MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART2_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART2_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART6_SHIFT                    MK_SHIFT_CONST(8)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART6_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART6_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART6_RANGE                    8:8
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART6_MSB                      MK_SHIFT_CONST(8)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART6_LSB                      MK_SHIFT_CONST(8)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART6_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART6_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART6_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART8_SHIFT                    MK_SHIFT_CONST(9)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART8_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART8_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART8_RANGE                    9:9
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART8_MSB                      MK_SHIFT_CONST(9)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART8_LSB                      MK_SHIFT_CONST(9)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART8_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART8_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART8_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART8_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART8_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART8_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_TX_0_UART8_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_REQUESTORS_RX_0
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0                        MK_ADDR_CONST(0x8)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_SECURE                         0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_DUAL                   0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_SCR                    SCR_DMA_RO_0
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_WORD_COUNT                     0x1
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_RESET_MASK                     MK_MASK_CONST(0x3ff)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_READ_MASK                      MK_MASK_CONST(0x3ff)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C1_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C1_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C1_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C1_RANGE                     0:0
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C1_MSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C1_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C1_WOFFSET                   0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C1_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C2_SHIFT                     MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C2_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C2_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C2_RANGE                     1:1
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C2_MSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C2_LSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C2_WOFFSET                   0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C2_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C2_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C3_SHIFT                     MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C3_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C3_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C3_RANGE                     2:2
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C3_MSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C3_LSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C3_WOFFSET                   0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C3_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C3_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_I2C3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_SPI_SHIFT                      MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_SPI_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_RX_0_SPI_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_SPI_RANGE                      3:3
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_SPI_MSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_SPI_LSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_SPI_WOFFSET                    0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_SPI_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_SPI_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_SPI_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_SPI_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_SPI_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_SPI_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART1_SHIFT                    MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART1_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART1_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART1_RANGE                    4:4
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART1_MSB                      MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART1_LSB                      MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART1_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART2_SHIFT                    MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART2_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART2_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART2_RANGE                    5:5
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART2_MSB                      MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART2_LSB                      MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART2_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART2_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_DMIC_SHIFT                     MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_DMIC_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_RX_0_DMIC_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_DMIC_RANGE                     6:6
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_DMIC_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_DMIC_LSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_DMIC_WOFFSET                   0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_DMIC_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_DMIC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_DMIC_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_DMIC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_DMIC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_DMIC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_GTE_SHIFT                      MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_GTE_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_RX_0_GTE_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_GTE_RANGE                      7:7
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_GTE_MSB                        MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_GTE_LSB                        MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_GTE_WOFFSET                    0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_GTE_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_GTE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_GTE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_GTE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_GTE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_GTE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART6_SHIFT                    MK_SHIFT_CONST(8)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART6_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART6_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART6_RANGE                    8:8
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART6_MSB                      MK_SHIFT_CONST(8)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART6_LSB                      MK_SHIFT_CONST(8)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART6_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART6_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART6_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART8_SHIFT                    MK_SHIFT_CONST(9)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART8_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART8_SHIFT)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART8_RANGE                    9:9
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART8_MSB                      MK_SHIFT_CONST(9)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART8_LSB                      MK_SHIFT_CONST(9)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART8_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART8_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART8_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART8_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART8_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART8_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_REQUESTORS_RX_0_UART8_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_COMMON_ERROR_STA_0
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0                     MK_ADDR_CONST(0xc)
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_SECURE                      0x0
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_DUAL                        0x0
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_SCR                         SCR_HYPER_0
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_RANGE                  31:0
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_WOFFSET                        0x0
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0                    MK_ADDR_CONST(0x10)
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_SECURE                     0x0
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_DUAL                       0x0
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_SCR                        SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_RANGE                 31:0
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_WOFFSET                       0x0
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x14
+
+// Register GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0                     MK_ADDR_CONST(0x18)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_SECURE                      0x0
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_DUAL                        0x0
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_SCR                         SCR_DMA_RO_0
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH0_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH0_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH0_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH0_RANGE                   0:0
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH0_MSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH0_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH0_WOFFSET                 0x0
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH0_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH0_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH1_SHIFT                   MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH1_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH1_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH1_RANGE                   1:1
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH1_MSB                     MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH1_LSB                     MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH1_WOFFSET                 0x0
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH1_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH1_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH2_SHIFT                   MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH2_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH2_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH2_RANGE                   2:2
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH2_MSB                     MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH2_LSB                     MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH2_WOFFSET                 0x0
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH2_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH2_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH3_SHIFT                   MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH3_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH3_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH3_RANGE                   3:3
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH3_MSB                     MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH3_LSB                     MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH3_WOFFSET                 0x0
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH3_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH3_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH4_SHIFT                   MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH4_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH4_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH4_RANGE                   4:4
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH4_MSB                     MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH4_LSB                     MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH4_WOFFSET                 0x0
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH4_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH4_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH5_SHIFT                   MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH5_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH5_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH5_RANGE                   5:5
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH5_MSB                     MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH5_LSB                     MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH5_WOFFSET                 0x0
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH5_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH5_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH6_SHIFT                   MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH6_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH6_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH6_RANGE                   6:6
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH6_MSB                     MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH6_LSB                     MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH6_WOFFSET                 0x0
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH6_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH6_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH7_SHIFT                   MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH7_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH7_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH7_RANGE                   7:7
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH7_MSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH7_LSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH7_WOFFSET                 0x0
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH7_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH7_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0_CH7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_MASKED_INTR_REG_0
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0                      MK_ADDR_CONST(0x1c)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_SECURE                       0x0
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_DUAL                         0x0
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_SCR                  SCR_DMA_RO_0
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_RESET_VAL                    MK_MASK_CONST(0xff)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH0_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH0_SHIFT)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH0_RANGE                    0:0
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH0_MSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH0_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH0_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH1_SHIFT                    MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH1_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH1_SHIFT)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH1_RANGE                    1:1
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH1_MSB                      MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH1_LSB                      MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH1_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH1_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH2_SHIFT                    MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH2_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH2_SHIFT)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH2_RANGE                    2:2
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH2_MSB                      MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH2_LSB                      MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH2_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH2_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH3_SHIFT                    MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH3_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH3_SHIFT)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH3_RANGE                    3:3
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH3_MSB                      MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH3_LSB                      MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH3_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH3_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH3_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH4_SHIFT                    MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH4_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH4_SHIFT)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH4_RANGE                    4:4
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH4_MSB                      MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH4_LSB                      MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH4_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH4_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH4_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH5_SHIFT                    MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH5_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH5_SHIFT)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH5_RANGE                    5:5
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH5_MSB                      MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH5_LSB                      MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH5_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH5_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH5_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH6_SHIFT                    MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH6_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH6_SHIFT)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH6_RANGE                    6:6
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH6_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH6_LSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH6_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH6_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH6_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH7_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH7_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH7_SHIFT)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH7_RANGE                    7:7
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH7_MSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH7_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH7_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH7_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH7_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_MASKED_INTR_REG_0_CH7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0                     MK_ADDR_CONST(0x20)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_SECURE                      0x0
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_DUAL                        0x0
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_SCR                         SCR_DMA_RO_0
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH0_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH0_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH0_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH0_RANGE                   0:0
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH0_MSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH0_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH0_WOFFSET                 0x0
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH0_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH0_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH1_SHIFT                   MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH1_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH1_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH1_RANGE                   1:1
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH1_MSB                     MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH1_LSB                     MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH1_WOFFSET                 0x0
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH1_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH1_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH2_SHIFT                   MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH2_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH2_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH2_RANGE                   2:2
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH2_MSB                     MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH2_LSB                     MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH2_WOFFSET                 0x0
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH2_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH2_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH3_SHIFT                   MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH3_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH3_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH3_RANGE                   3:3
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH3_MSB                     MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH3_LSB                     MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH3_WOFFSET                 0x0
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH3_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH3_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH4_SHIFT                   MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH4_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH4_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH4_RANGE                   4:4
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH4_MSB                     MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH4_LSB                     MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH4_WOFFSET                 0x0
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH4_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH4_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH5_SHIFT                   MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH5_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH5_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH5_RANGE                   5:5
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH5_MSB                     MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH5_LSB                     MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH5_WOFFSET                 0x0
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH5_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH5_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH6_SHIFT                   MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH6_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH6_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH6_RANGE                   6:6
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH6_MSB                     MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH6_LSB                     MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH6_WOFFSET                 0x0
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH6_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH6_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH7_SHIFT                   MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH7_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH7_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH7_RANGE                   7:7
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH7_MSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH7_LSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH7_WOFFSET                 0x0
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH7_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH7_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0_CH7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_COMMON_INTR_0
+#define GPCDMA_AO_COMMON_COMMON_INTR_0                  MK_ADDR_CONST(0x24)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_RESET_MASK                       MK_MASK_CONST(0x1f)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_READ_MASK                        MK_MASK_CONST(0x1f)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_WRITE_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_SHIFT                    MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_SHIFT)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_RANGE                    4:4
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_MSB                      MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_LSB                      MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_SHIFT                    MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_SHIFT)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_RANGE                    3:3
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_MSB                      MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_LSB                      MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IS_EOC_SHIFT                     MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IS_EOC_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_COMMON_INTR_0_IS_EOC_SHIFT)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IS_EOC_RANGE                     2:2
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IS_EOC_MSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IS_EOC_LSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IS_EOC_WOFFSET                   0x0
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IS_EOC_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IS_EOC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IS_EOC_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IS_EOC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IS_EOC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IS_EOC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_INTR_MASK_SHIFT                  MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_INTR_MASK_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_COMMON_INTR_0_INTR_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_INTR_MASK_RANGE                  1:1
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_INTR_MASK_MSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_INTR_MASK_LSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_INTR_MASK_WOFFSET                        0x0
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_INTR_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_INTR_MASK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_INTR_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_INTR_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_INTR_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_INTR_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IE_EOC_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IE_EOC_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_COMMON_INTR_0_IE_EOC_SHIFT)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IE_EOC_RANGE                     0:0
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IE_EOC_MSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IE_EOC_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IE_EOC_WOFFSET                   0x0
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IE_EOC_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IE_EOC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IE_EOC_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IE_EOC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IE_EOC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_COMMON_INTR_0_IE_EOC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0                     MK_ADDR_CONST(0x28)
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_SECURE                      0x0
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_DUAL                        0x0
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_SHIFT)
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_RANGE                       31:0
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_WOFFSET                     0x0
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0                     MK_ADDR_CONST(0x80)
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_SECURE                      0x0
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_DUAL                        0x0
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_RANGE                      31:0
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_WOFFSET                    0x0
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0                     MK_ADDR_CONST(0x84)
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_SECURE                      0x0
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_DUAL                        0x0
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_RANGE                      31:0
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_WOFFSET                    0x0
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0                     MK_ADDR_CONST(0x88)
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_SECURE                      0x0
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_DUAL                        0x0
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_RANGE                      31:0
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_WOFFSET                    0x0
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0                     MK_ADDR_CONST(0x8c)
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_SECURE                      0x0
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_DUAL                        0x0
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_RANGE                      31:0
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_WOFFSET                    0x0
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0                     MK_ADDR_CONST(0x90)
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_SECURE                      0x0
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_DUAL                        0x0
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_RANGE                      31:0
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_WOFFSET                    0x0
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0                     MK_ADDR_CONST(0x94)
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_SECURE                      0x0
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_DUAL                        0x0
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_RANGE                      31:0
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_WOFFSET                    0x0
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0                     MK_ADDR_CONST(0x98)
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_SECURE                      0x0
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_DUAL                        0x0
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_RANGE                      31:0
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_WOFFSET                    0x0
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0                     MK_ADDR_CONST(0x9c)
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_SECURE                      0x0
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_DUAL                        0x0
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_RANGE                      31:0
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_WOFFSET                    0x0
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_PER0_PERI_ADDR_0
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0                       MK_ADDR_CONST(0x100)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_SECURE                        0x0
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_DUAL                  0x0
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_SCR                   SCR_HYPER_0
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_FIELD                    MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_SHIFT)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_RANGE                    31:16
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_FIELD                        MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_SHIFT)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_RANGE                        15:0
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_PER1_PERI_ADDR_0
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0                       MK_ADDR_CONST(0x104)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_SECURE                        0x0
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_DUAL                  0x0
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_SCR                   SCR_HYPER_0
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_FIELD                    MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_SHIFT)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_RANGE                    31:16
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_FIELD                        MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_SHIFT)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_RANGE                        15:0
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_PER2_PERI_ADDR_0
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0                       MK_ADDR_CONST(0x108)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_SECURE                        0x0
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_DUAL                  0x0
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_SCR                   SCR_HYPER_0
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_FIELD                    MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_SHIFT)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_RANGE                    31:16
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_FIELD                        MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_SHIFT)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_RANGE                        15:0
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_PER3_PERI_ADDR_0
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0                       MK_ADDR_CONST(0x10c)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_SECURE                        0x0
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_DUAL                  0x0
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_SCR                   SCR_HYPER_0
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_FIELD                    MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_SHIFT)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_RANGE                    31:16
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_FIELD                        MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_SHIFT)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_RANGE                        15:0
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_PER4_PERI_ADDR_0
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0                       MK_ADDR_CONST(0x110)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_SECURE                        0x0
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_DUAL                  0x0
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_SCR                   SCR_HYPER_0
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_FIELD                    MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_SHIFT)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_RANGE                    31:16
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_FIELD                        MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_SHIFT)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_RANGE                        15:0
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_PER5_PERI_ADDR_0
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0                       MK_ADDR_CONST(0x114)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_SECURE                        0x0
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_DUAL                  0x0
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_SCR                   SCR_HYPER_0
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_FIELD                    MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_SHIFT)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_RANGE                    31:16
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_FIELD                        MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_SHIFT)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_RANGE                        15:0
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_PER6_PERI_ADDR_0
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0                       MK_ADDR_CONST(0x118)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_SECURE                        0x0
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_DUAL                  0x0
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_SCR                   SCR_HYPER_0
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_FIELD                    MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_SHIFT)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_RANGE                    31:16
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_FIELD                        MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_SHIFT)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_RANGE                        15:0
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_PER7_PERI_ADDR_0
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0                       MK_ADDR_CONST(0x11c)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_SECURE                        0x0
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_DUAL                  0x0
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_SCR                   SCR_HYPER_0
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_FIELD                    MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_SHIFT)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_RANGE                    31:16
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_FIELD                        MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_SHIFT)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_RANGE                        15:0
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_PER8_PERI_ADDR_0
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0                       MK_ADDR_CONST(0x120)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_SECURE                        0x0
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_DUAL                  0x0
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_SCR                   SCR_HYPER_0
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_FIELD                    MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_SHIFT)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_RANGE                    31:16
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_FIELD                        MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_SHIFT)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_RANGE                        15:0
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_PER9_PERI_ADDR_0
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0                       MK_ADDR_CONST(0x124)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_SECURE                        0x0
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_DUAL                  0x0
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_SCR                   SCR_HYPER_0
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_FIELD                    MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_SHIFT)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_RANGE                    31:16
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_FIELD                        MK_FIELD_CONST(0xffff, GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_SHIFT)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_RANGE                        15:0
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0                  MK_ADDR_CONST(0x180)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0                  MK_ADDR_CONST(0x184)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0                  MK_ADDR_CONST(0x188)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0                  MK_ADDR_CONST(0x18c)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0                  MK_ADDR_CONST(0x190)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0                  MK_ADDR_CONST(0x194)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0                  MK_ADDR_CONST(0x198)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0                  MK_ADDR_CONST(0x19c)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0                  MK_ADDR_CONST(0x200)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0                  MK_ADDR_CONST(0x204)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0                  MK_ADDR_CONST(0x208)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0                  MK_ADDR_CONST(0x20c)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0                  MK_ADDR_CONST(0x210)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0                  MK_ADDR_CONST(0x214)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0                  MK_ADDR_CONST(0x218)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0                  MK_ADDR_CONST(0x21c)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0                  MK_ADDR_CONST(0x280)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0                  MK_ADDR_CONST(0x284)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0                  MK_ADDR_CONST(0x288)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0                  MK_ADDR_CONST(0x28c)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0                  MK_ADDR_CONST(0x290)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0                  MK_ADDR_CONST(0x294)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0                  MK_ADDR_CONST(0x298)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0                  MK_ADDR_CONST(0x29c)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0                  MK_ADDR_CONST(0x300)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0                  MK_ADDR_CONST(0x304)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0                  MK_ADDR_CONST(0x308)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0                  MK_ADDR_CONST(0x30c)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0                  MK_ADDR_CONST(0x310)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0                  MK_ADDR_CONST(0x314)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0                  MK_ADDR_CONST(0x318)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0                  MK_ADDR_CONST(0x31c)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_SCR                      SCR_HYPER_0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_RANGE                        31:0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0                       MK_ADDR_CONST(0x380)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_SECURE                        0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_DUAL                  0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_SCR                   SCR_HYPER_0
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_RESET_VAL                     MK_MASK_CONST(0xff)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_RANGE                     0:0
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_MSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_WOFFSET                   0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_SHIFT                     MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_RANGE                     1:1
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_MSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_LSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_WOFFSET                   0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_SHIFT                     MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_RANGE                     2:2
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_MSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_LSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_WOFFSET                   0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_SHIFT                     MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_RANGE                     3:3
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_MSB                       MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_LSB                       MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_WOFFSET                   0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_SHIFT                     MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_RANGE                     4:4
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_MSB                       MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_LSB                       MK_SHIFT_CONST(4)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_WOFFSET                   0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_SHIFT                     MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_RANGE                     5:5
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_MSB                       MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_LSB                       MK_SHIFT_CONST(5)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_WOFFSET                   0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_SHIFT                     MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_RANGE                     6:6
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_LSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_WOFFSET                   0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_SHIFT                     MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_RANGE                     7:7
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_MSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_LSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_WOFFSET                   0x0
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0                  MK_ADDR_CONST(0x384)
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_SECURE                   0x0
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_DUAL                     0x0
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_SCR                      0
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_RANGE                        0:0
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_MSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_WOFFSET                      0x0
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_COMMON_DMA_ACTIVE_0
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0                   MK_ADDR_CONST(0x388)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_SECURE                    0x0
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DUAL                      0x0
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_SCR                       0
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_WORD_COUNT                        0x1
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_RANGE                  0:0
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_MSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_WOFFSET                        0x0
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_SHIFT                    MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_RANGE                    1:1
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_MSB                      MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_LSB                      MK_SHIFT_CONST(1)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_WOFFSET                  0x0
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_RANGE                       2:2
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_WOFFSET                     0x0
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_SHIFT)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_RANGE                       3:3
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_WOFFSET                     0x0
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x390
+
+// Register GPCDMA_AO_SCR_SCR_CH0_0
+#define GPCDMA_AO_SCR_SCR_CH0_0                 MK_ADDR_CONST(0xf00)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SECURE                  0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_DUAL                    0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_SCR                     0
+#define GPCDMA_AO_SCR_SCR_CH0_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_SCR_SCR_CH0_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH0_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_SEC_LCK_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_LCK_RANGE                   29:29
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_LCK_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_SEC_WEN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_WEN_RANGE                   28:28
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_WEN_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_SEC_REN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_REN_RANGE                   27:27
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_REN_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_AO_SCR_SCR_CH0_0_SEC_OWNER_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_OWNER_RANGE                 26:24
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_OWNER_WOFFSET                       0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_PR7_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR7_RANGE                       23:23
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR7_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_PR6_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR6_RANGE                       22:22
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR6_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_PR5_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR5_RANGE                       21:21
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR5_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_PR4_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR4_RANGE                       20:20
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR4_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_PR3_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR3_RANGE                       19:19
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR3_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_PR2_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR2_RANGE                       18:18
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR2_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_PR1_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR1_RANGE                       17:17
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR1_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_PR0_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR0_RANGE                       16:16
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR0_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_G7W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7W_RANGE                       15:15
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_G6W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6W_RANGE                       14:14
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_G5W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5W_RANGE                       13:13
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_G4W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4W_RANGE                       12:12
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_G3W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3W_RANGE                       11:11
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_G2W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2W_RANGE                       10:10
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_G1W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1W_RANGE                       9:9
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_G0W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0W_RANGE                       8:8
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_G7R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7R_RANGE                       7:7
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_G6R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6R_RANGE                       6:6
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_G5R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5R_RANGE                       5:5
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_G4R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4R_RANGE                       4:4
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_G3R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3R_RANGE                       3:3
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_G2R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2R_RANGE                       2:2
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_G1R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1R_RANGE                       1:1
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH0_0_G0R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0R_RANGE                       0:0
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH0_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_SCR_SCR_CH1_0
+#define GPCDMA_AO_SCR_SCR_CH1_0                 MK_ADDR_CONST(0xf04)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SECURE                  0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_DUAL                    0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_SCR                     0
+#define GPCDMA_AO_SCR_SCR_CH1_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_SCR_SCR_CH1_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH1_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_SEC_LCK_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_LCK_RANGE                   29:29
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_LCK_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_SEC_WEN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_WEN_RANGE                   28:28
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_WEN_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_SEC_REN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_REN_RANGE                   27:27
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_REN_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_AO_SCR_SCR_CH1_0_SEC_OWNER_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_OWNER_RANGE                 26:24
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_OWNER_WOFFSET                       0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_PR7_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR7_RANGE                       23:23
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR7_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_PR6_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR6_RANGE                       22:22
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR6_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_PR5_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR5_RANGE                       21:21
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR5_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_PR4_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR4_RANGE                       20:20
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR4_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_PR3_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR3_RANGE                       19:19
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR3_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_PR2_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR2_RANGE                       18:18
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR2_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_PR1_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR1_RANGE                       17:17
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR1_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_PR0_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR0_RANGE                       16:16
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR0_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_G7W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7W_RANGE                       15:15
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_G6W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6W_RANGE                       14:14
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_G5W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5W_RANGE                       13:13
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_G4W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4W_RANGE                       12:12
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_G3W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3W_RANGE                       11:11
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_G2W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2W_RANGE                       10:10
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_G1W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1W_RANGE                       9:9
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_G0W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0W_RANGE                       8:8
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_G7R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7R_RANGE                       7:7
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_G6R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6R_RANGE                       6:6
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_G5R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5R_RANGE                       5:5
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_G4R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4R_RANGE                       4:4
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_G3R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3R_RANGE                       3:3
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_G2R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2R_RANGE                       2:2
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_G1R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1R_RANGE                       1:1
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH1_0_G0R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0R_RANGE                       0:0
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH1_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_SCR_SCR_CH2_0
+#define GPCDMA_AO_SCR_SCR_CH2_0                 MK_ADDR_CONST(0xf08)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SECURE                  0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_DUAL                    0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_SCR                     0
+#define GPCDMA_AO_SCR_SCR_CH2_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_SCR_SCR_CH2_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH2_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_SEC_LCK_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_LCK_RANGE                   29:29
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_LCK_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_SEC_WEN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_WEN_RANGE                   28:28
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_WEN_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_SEC_REN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_REN_RANGE                   27:27
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_REN_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_AO_SCR_SCR_CH2_0_SEC_OWNER_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_OWNER_RANGE                 26:24
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_OWNER_WOFFSET                       0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_PR7_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR7_RANGE                       23:23
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR7_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_PR6_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR6_RANGE                       22:22
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR6_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_PR5_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR5_RANGE                       21:21
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR5_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_PR4_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR4_RANGE                       20:20
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR4_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_PR3_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR3_RANGE                       19:19
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR3_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_PR2_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR2_RANGE                       18:18
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR2_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_PR1_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR1_RANGE                       17:17
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR1_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_PR0_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR0_RANGE                       16:16
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR0_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_G7W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7W_RANGE                       15:15
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_G6W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6W_RANGE                       14:14
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_G5W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5W_RANGE                       13:13
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_G4W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4W_RANGE                       12:12
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_G3W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3W_RANGE                       11:11
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_G2W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2W_RANGE                       10:10
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_G1W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1W_RANGE                       9:9
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_G0W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0W_RANGE                       8:8
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_G7R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7R_RANGE                       7:7
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_G6R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6R_RANGE                       6:6
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_G5R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5R_RANGE                       5:5
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_G4R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4R_RANGE                       4:4
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_G3R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3R_RANGE                       3:3
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_G2R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2R_RANGE                       2:2
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_G1R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1R_RANGE                       1:1
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH2_0_G0R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0R_RANGE                       0:0
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH2_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_SCR_SCR_CH3_0
+#define GPCDMA_AO_SCR_SCR_CH3_0                 MK_ADDR_CONST(0xf0c)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SECURE                  0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_DUAL                    0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_SCR                     0
+#define GPCDMA_AO_SCR_SCR_CH3_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_SCR_SCR_CH3_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH3_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_SEC_LCK_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_LCK_RANGE                   29:29
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_LCK_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_SEC_WEN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_WEN_RANGE                   28:28
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_WEN_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_SEC_REN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_REN_RANGE                   27:27
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_REN_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_AO_SCR_SCR_CH3_0_SEC_OWNER_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_OWNER_RANGE                 26:24
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_OWNER_WOFFSET                       0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_PR7_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR7_RANGE                       23:23
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR7_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_PR6_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR6_RANGE                       22:22
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR6_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_PR5_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR5_RANGE                       21:21
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR5_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_PR4_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR4_RANGE                       20:20
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR4_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_PR3_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR3_RANGE                       19:19
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR3_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_PR2_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR2_RANGE                       18:18
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR2_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_PR1_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR1_RANGE                       17:17
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR1_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_PR0_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR0_RANGE                       16:16
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR0_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_G7W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7W_RANGE                       15:15
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_G6W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6W_RANGE                       14:14
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_G5W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5W_RANGE                       13:13
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_G4W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4W_RANGE                       12:12
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_G3W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3W_RANGE                       11:11
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_G2W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2W_RANGE                       10:10
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_G1W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1W_RANGE                       9:9
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_G0W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0W_RANGE                       8:8
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_G7R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7R_RANGE                       7:7
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_G6R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6R_RANGE                       6:6
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_G5R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5R_RANGE                       5:5
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_G4R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4R_RANGE                       4:4
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_G3R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3R_RANGE                       3:3
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_G2R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2R_RANGE                       2:2
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_G1R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1R_RANGE                       1:1
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH3_0_G0R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0R_RANGE                       0:0
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH3_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_SCR_SCR_CH4_0
+#define GPCDMA_AO_SCR_SCR_CH4_0                 MK_ADDR_CONST(0xf10)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SECURE                  0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_DUAL                    0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_SCR                     0
+#define GPCDMA_AO_SCR_SCR_CH4_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_SCR_SCR_CH4_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH4_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_SEC_LCK_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_LCK_RANGE                   29:29
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_LCK_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_SEC_WEN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_WEN_RANGE                   28:28
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_WEN_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_SEC_REN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_REN_RANGE                   27:27
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_REN_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_AO_SCR_SCR_CH4_0_SEC_OWNER_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_OWNER_RANGE                 26:24
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_OWNER_WOFFSET                       0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_PR7_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR7_RANGE                       23:23
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR7_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_PR6_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR6_RANGE                       22:22
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR6_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_PR5_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR5_RANGE                       21:21
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR5_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_PR4_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR4_RANGE                       20:20
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR4_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_PR3_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR3_RANGE                       19:19
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR3_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_PR2_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR2_RANGE                       18:18
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR2_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_PR1_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR1_RANGE                       17:17
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR1_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_PR0_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR0_RANGE                       16:16
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR0_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_G7W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7W_RANGE                       15:15
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_G6W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6W_RANGE                       14:14
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_G5W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5W_RANGE                       13:13
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_G4W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4W_RANGE                       12:12
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_G3W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3W_RANGE                       11:11
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_G2W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2W_RANGE                       10:10
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_G1W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1W_RANGE                       9:9
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_G0W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0W_RANGE                       8:8
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_G7R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7R_RANGE                       7:7
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_G6R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6R_RANGE                       6:6
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_G5R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5R_RANGE                       5:5
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_G4R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4R_RANGE                       4:4
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_G3R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3R_RANGE                       3:3
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_G2R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2R_RANGE                       2:2
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_G1R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1R_RANGE                       1:1
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH4_0_G0R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0R_RANGE                       0:0
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH4_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_SCR_SCR_CH5_0
+#define GPCDMA_AO_SCR_SCR_CH5_0                 MK_ADDR_CONST(0xf14)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SECURE                  0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_DUAL                    0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_SCR                     0
+#define GPCDMA_AO_SCR_SCR_CH5_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_SCR_SCR_CH5_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH5_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_SEC_LCK_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_LCK_RANGE                   29:29
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_LCK_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_SEC_WEN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_WEN_RANGE                   28:28
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_WEN_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_SEC_REN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_REN_RANGE                   27:27
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_REN_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_AO_SCR_SCR_CH5_0_SEC_OWNER_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_OWNER_RANGE                 26:24
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_OWNER_WOFFSET                       0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_PR7_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR7_RANGE                       23:23
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR7_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_PR6_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR6_RANGE                       22:22
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR6_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_PR5_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR5_RANGE                       21:21
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR5_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_PR4_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR4_RANGE                       20:20
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR4_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_PR3_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR3_RANGE                       19:19
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR3_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_PR2_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR2_RANGE                       18:18
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR2_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_PR1_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR1_RANGE                       17:17
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR1_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_PR0_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR0_RANGE                       16:16
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR0_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_G7W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7W_RANGE                       15:15
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_G6W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6W_RANGE                       14:14
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_G5W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5W_RANGE                       13:13
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_G4W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4W_RANGE                       12:12
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_G3W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3W_RANGE                       11:11
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_G2W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2W_RANGE                       10:10
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_G1W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1W_RANGE                       9:9
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_G0W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0W_RANGE                       8:8
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_G7R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7R_RANGE                       7:7
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_G6R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6R_RANGE                       6:6
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_G5R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5R_RANGE                       5:5
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_G4R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4R_RANGE                       4:4
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_G3R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3R_RANGE                       3:3
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_G2R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2R_RANGE                       2:2
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_G1R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1R_RANGE                       1:1
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH5_0_G0R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0R_RANGE                       0:0
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH5_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_SCR_SCR_CH6_0
+#define GPCDMA_AO_SCR_SCR_CH6_0                 MK_ADDR_CONST(0xf18)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SECURE                  0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_DUAL                    0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_SCR                     0
+#define GPCDMA_AO_SCR_SCR_CH6_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_SCR_SCR_CH6_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH6_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_SEC_LCK_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_LCK_RANGE                   29:29
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_LCK_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_SEC_WEN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_WEN_RANGE                   28:28
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_WEN_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_SEC_REN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_REN_RANGE                   27:27
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_REN_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_AO_SCR_SCR_CH6_0_SEC_OWNER_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_OWNER_RANGE                 26:24
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_OWNER_WOFFSET                       0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_PR7_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR7_RANGE                       23:23
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR7_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_PR6_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR6_RANGE                       22:22
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR6_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_PR5_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR5_RANGE                       21:21
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR5_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_PR4_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR4_RANGE                       20:20
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR4_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_PR3_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR3_RANGE                       19:19
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR3_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_PR2_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR2_RANGE                       18:18
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR2_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_PR1_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR1_RANGE                       17:17
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR1_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_PR0_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR0_RANGE                       16:16
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR0_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_G7W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7W_RANGE                       15:15
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_G6W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6W_RANGE                       14:14
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_G5W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5W_RANGE                       13:13
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_G4W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4W_RANGE                       12:12
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_G3W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3W_RANGE                       11:11
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_G2W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2W_RANGE                       10:10
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_G1W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1W_RANGE                       9:9
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_G0W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0W_RANGE                       8:8
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_G7R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7R_RANGE                       7:7
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_G6R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6R_RANGE                       6:6
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_G5R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5R_RANGE                       5:5
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_G4R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4R_RANGE                       4:4
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_G3R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3R_RANGE                       3:3
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_G2R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2R_RANGE                       2:2
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_G1R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1R_RANGE                       1:1
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH6_0_G0R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0R_RANGE                       0:0
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH6_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_SCR_SCR_CH7_0
+#define GPCDMA_AO_SCR_SCR_CH7_0                 MK_ADDR_CONST(0xf1c)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SECURE                  0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_DUAL                    0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_SCR                     0
+#define GPCDMA_AO_SCR_SCR_CH7_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_SCR_SCR_CH7_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH7_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_SEC_LCK_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_LCK_RANGE                   29:29
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_LCK_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_SEC_WEN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_WEN_RANGE                   28:28
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_WEN_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_SEC_REN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_REN_RANGE                   27:27
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_REN_WOFFSET                 0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_AO_SCR_SCR_CH7_0_SEC_OWNER_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_OWNER_RANGE                 26:24
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_OWNER_WOFFSET                       0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_PR7_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR7_RANGE                       23:23
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR7_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_PR6_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR6_RANGE                       22:22
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR6_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_PR5_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR5_RANGE                       21:21
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR5_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_PR4_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR4_RANGE                       20:20
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR4_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_PR3_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR3_RANGE                       19:19
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR3_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_PR2_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR2_RANGE                       18:18
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR2_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_PR1_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR1_RANGE                       17:17
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR1_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_PR0_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR0_RANGE                       16:16
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR0_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_G7W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7W_RANGE                       15:15
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_G6W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6W_RANGE                       14:14
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_G5W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5W_RANGE                       13:13
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_G4W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4W_RANGE                       12:12
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_G3W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3W_RANGE                       11:11
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_G2W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2W_RANGE                       10:10
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_G1W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1W_RANGE                       9:9
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_G0W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0W_RANGE                       8:8
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0W_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_G7R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7R_RANGE                       7:7
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_G6R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6R_RANGE                       6:6
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_G5R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5R_RANGE                       5:5
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_G4R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4R_RANGE                       4:4
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_G3R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3R_RANGE                       3:3
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_G2R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2R_RANGE                       2:2
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_G1R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1R_RANGE                       1:1
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_CH7_0_G0R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0R_RANGE                       0:0
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0R_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_CH7_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xf20
+
+// Reserved address 0xf24
+
+// Reserved address 0xf28
+
+// Reserved address 0xf2c
+
+// Reserved address 0xf30
+
+// Reserved address 0xf34
+
+// Reserved address 0xf38
+
+// Reserved address 0xf3c
+
+// Reserved address 0xf40
+
+// Reserved address 0xf44
+
+// Reserved address 0xf48
+
+// Reserved address 0xf4c
+
+// Reserved address 0xf50
+
+// Reserved address 0xf54
+
+// Reserved address 0xf58
+
+// Reserved address 0xf5c
+
+// Reserved address 0xf60
+
+// Reserved address 0xf64
+
+// Reserved address 0xf68
+
+// Reserved address 0xf6c
+
+// Reserved address 0xf70
+
+// Reserved address 0xf74
+
+// Reserved address 0xf78
+
+// Reserved address 0xf7c
+
+// Register GPCDMA_AO_SCR_SCR_TZ_0
+#define GPCDMA_AO_SCR_SCR_TZ_0                  MK_ADDR_CONST(0xf80)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SECURE                   0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_DUAL                     0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_SCR                      0
+#define GPCDMA_AO_SCR_SCR_TZ_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_SCR_SCR_TZ_0_RESET_VAL                        MK_MASK_CONST(0x38000101)
+#define GPCDMA_AO_SCR_SCR_TZ_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_TZ_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_SEC_LCK_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_LCK_RANGE                    29:29
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_LCK_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_SEC_WEN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_WEN_RANGE                    28:28
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_WEN_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_SEC_REN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_REN_RANGE                    27:27
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_REN_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, GPCDMA_AO_SCR_SCR_TZ_0_SEC_OWNER_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_OWNER_RANGE                  26:24
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_OWNER_WOFFSET                        0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR7_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_PR7_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR7_RANGE                        23:23
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR7_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR6_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_PR6_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR6_RANGE                        22:22
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR6_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR5_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_PR5_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR5_RANGE                        21:21
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR5_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR4_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_PR4_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR4_RANGE                        20:20
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR4_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR3_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_PR3_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR3_RANGE                        19:19
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR3_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR2_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_PR2_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR2_RANGE                        18:18
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR2_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_PR1_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR1_RANGE                        17:17
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR1_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR0_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_PR0_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR0_RANGE                        16:16
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR0_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7W_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_G7W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7W_RANGE                        15:15
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7W_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6W_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_G6W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6W_RANGE                        14:14
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6W_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5W_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_G5W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5W_RANGE                        13:13
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5W_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4W_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_G4W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4W_RANGE                        12:12
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4W_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3W_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_G3W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3W_RANGE                        11:11
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3W_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2W_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_G2W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2W_RANGE                        10:10
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2W_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1W_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_G1W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1W_RANGE                        9:9
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1W_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0W_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_G0W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0W_RANGE                        8:8
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0W_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0W_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7R_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_G7R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7R_RANGE                        7:7
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7R_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6R_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_G6R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6R_RANGE                        6:6
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6R_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5R_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_G5R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5R_RANGE                        5:5
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5R_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4R_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_G4R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4R_RANGE                        4:4
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4R_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3R_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_G3R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3R_RANGE                        3:3
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3R_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2R_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_G2R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2R_RANGE                        2:2
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2R_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1R_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_G1R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1R_RANGE                        1:1
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1R_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0R_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_TZ_0_G0R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0R_RANGE                        0:0
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0R_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0R_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_TZ_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_SCR_SCR_DMA_RO_0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0                      MK_ADDR_CONST(0xf84)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SECURE                       0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_DUAL                         0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SCR                  0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_LCK_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_LCK_RANGE                        29:29
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_LCK_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_WEN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_WEN_RANGE                        28:28
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_WEN_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_REN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_REN_RANGE                        27:27
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_REN_WOFFSET                      0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_OWNER_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_OWNER_RANGE                      26:24
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_OWNER_WOFFSET                    0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR7_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_PR7_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR7_RANGE                    23:23
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR7_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR7_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR7_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR6_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_PR6_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR6_RANGE                    22:22
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR6_MSB                      MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR6_LSB                      MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR6_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR5_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_PR5_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR5_RANGE                    21:21
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR5_MSB                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR5_LSB                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR5_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR4_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_PR4_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR4_RANGE                    20:20
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR4_MSB                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR4_LSB                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR4_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR3_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_PR3_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR3_RANGE                    19:19
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR3_MSB                      MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR3_LSB                      MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR3_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR2_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_PR2_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR2_RANGE                    18:18
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR2_MSB                      MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR2_LSB                      MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR2_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR1_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_PR1_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR1_RANGE                    17:17
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR1_MSB                      MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR1_LSB                      MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR1_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR0_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_PR0_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR0_RANGE                    16:16
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR0_MSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR0_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR0_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7W_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_G7W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7W_RANGE                    15:15
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7W_MSB                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7W_LSB                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7W_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6W_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_G6W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6W_RANGE                    14:14
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6W_MSB                      MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6W_LSB                      MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6W_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5W_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_G5W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5W_RANGE                    13:13
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5W_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5W_LSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5W_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4W_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_G4W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4W_RANGE                    12:12
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4W_MSB                      MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4W_LSB                      MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4W_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3W_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_G3W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3W_RANGE                    11:11
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3W_MSB                      MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3W_LSB                      MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3W_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2W_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_G2W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2W_RANGE                    10:10
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2W_MSB                      MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2W_LSB                      MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2W_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1W_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_G1W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1W_RANGE                    9:9
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1W_MSB                      MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1W_LSB                      MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1W_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0W_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_G0W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0W_RANGE                    8:8
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0W_MSB                      MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0W_LSB                      MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0W_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7R_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_G7R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7R_RANGE                    7:7
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7R_MSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7R_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7R_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6R_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_G6R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6R_RANGE                    6:6
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6R_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6R_LSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6R_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5R_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_G5R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5R_RANGE                    5:5
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5R_MSB                      MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5R_LSB                      MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5R_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4R_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_G4R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4R_RANGE                    4:4
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4R_MSB                      MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4R_LSB                      MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4R_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3R_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_G3R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3R_RANGE                    3:3
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3R_MSB                      MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3R_LSB                      MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3R_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2R_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_G2R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2R_RANGE                    2:2
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2R_MSB                      MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2R_LSB                      MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2R_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1R_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_G1R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1R_RANGE                    1:1
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1R_MSB                      MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1R_LSB                      MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1R_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0R_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_DMA_RO_0_G0R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0R_RANGE                    0:0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0R_MSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0R_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0R_WOFFSET                  0x0
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_DMA_RO_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_SCR_SCR_HYPER_0
+#define GPCDMA_AO_SCR_SCR_HYPER_0                       MK_ADDR_CONST(0xf88)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SECURE                        0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_DUAL                  0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SCR                   0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_SCR_SCR_HYPER_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_SEC_LCK_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_LCK_RANGE                 29:29
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_LCK_WOFFSET                       0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_SEC_WEN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_WEN_RANGE                 28:28
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_WEN_WOFFSET                       0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_SEC_REN_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_REN_RANGE                 27:27
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_REN_WOFFSET                       0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, GPCDMA_AO_SCR_SCR_HYPER_0_SEC_OWNER_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_OWNER_RANGE                       26:24
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_OWNER_WOFFSET                     0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR7_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_PR7_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR7_RANGE                     23:23
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR7_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR7_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR7_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR6_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_PR6_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR6_RANGE                     22:22
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR6_MSB                       MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR6_LSB                       MK_SHIFT_CONST(22)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR6_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR5_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_PR5_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR5_RANGE                     21:21
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR5_MSB                       MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR5_LSB                       MK_SHIFT_CONST(21)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR5_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR4_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_PR4_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR4_RANGE                     20:20
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR4_MSB                       MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR4_LSB                       MK_SHIFT_CONST(20)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR4_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR3_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_PR3_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR3_RANGE                     19:19
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR3_MSB                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR3_LSB                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR3_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR2_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_PR2_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR2_RANGE                     18:18
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR2_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR2_LSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR2_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR1_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_PR1_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR1_RANGE                     17:17
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR1_MSB                       MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR1_LSB                       MK_SHIFT_CONST(17)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR1_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR0_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_PR0_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR0_RANGE                     16:16
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR0_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR0_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR0_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7W_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_G7W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7W_RANGE                     15:15
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7W_MSB                       MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7W_LSB                       MK_SHIFT_CONST(15)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7W_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6W_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_G6W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6W_RANGE                     14:14
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6W_MSB                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6W_LSB                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6W_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5W_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_G5W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5W_RANGE                     13:13
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5W_MSB                       MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5W_LSB                       MK_SHIFT_CONST(13)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5W_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4W_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_G4W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4W_RANGE                     12:12
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4W_MSB                       MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4W_LSB                       MK_SHIFT_CONST(12)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4W_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3W_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_G3W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3W_RANGE                     11:11
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3W_MSB                       MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3W_LSB                       MK_SHIFT_CONST(11)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3W_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2W_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_G2W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2W_RANGE                     10:10
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2W_MSB                       MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2W_LSB                       MK_SHIFT_CONST(10)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2W_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1W_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_G1W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1W_RANGE                     9:9
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1W_MSB                       MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1W_LSB                       MK_SHIFT_CONST(9)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1W_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0W_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_G0W_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0W_RANGE                     8:8
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0W_MSB                       MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0W_LSB                       MK_SHIFT_CONST(8)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0W_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7R_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_G7R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7R_RANGE                     7:7
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7R_MSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7R_LSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7R_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6R_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_G6R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6R_RANGE                     6:6
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6R_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6R_LSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6R_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5R_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_G5R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5R_RANGE                     5:5
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5R_MSB                       MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5R_LSB                       MK_SHIFT_CONST(5)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5R_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4R_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_G4R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4R_RANGE                     4:4
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4R_MSB                       MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4R_LSB                       MK_SHIFT_CONST(4)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4R_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3R_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_G3R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3R_RANGE                     3:3
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3R_MSB                       MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3R_LSB                       MK_SHIFT_CONST(3)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3R_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2R_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_G2R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2R_RANGE                     2:2
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2R_MSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2R_LSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2R_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1R_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_G1R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1R_RANGE                     1:1
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1R_MSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1R_LSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1R_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0R_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_AO_SCR_SCR_HYPER_0_G0R_SHIFT)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0R_RANGE                     0:0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0R_MSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0R_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0R_WOFFSET                   0x0
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_SCR_SCR_HYPER_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH0_CSR_0
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0                     MK_ADDR_CONST(0x10000)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_SECURE                      0x0
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DUAL                        0x0
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_SCR                         SCR_CH0_0
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_RESET_VAL                   MK_MASK_CONST(0x8008400)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_RESET_MASK                  MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_READ_MASK                   MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_WRITE_MASK                  MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ENB_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ENB_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_CSR_0_ENB_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ENB_RANGE                   31:31
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ENB_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ENB_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ENB_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ENB_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ENB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ENB_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ENB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ENB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ENB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ENB_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ENB_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IE_EOC_SHIFT                        MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IE_EOC_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IE_EOC_RANGE                        30:30
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IE_EOC_MSB                  MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IE_EOC_LSB                  MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IE_EOC_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IE_EOC_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IE_EOC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IE_EOC_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IE_EOC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IE_EOC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IE_EOC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IE_EOC_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IE_EOC_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ONCE_SHIFT                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ONCE_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_CSR_0_ONCE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ONCE_RANGE                  27:27
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ONCE_MSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ONCE_LSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ONCE_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ONCE_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ONCE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ONCE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ONCE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ONCE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ONCE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ONCE_CYCLIC_MODE                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_ONCE_SINGLE_BLOCK                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_FC_MODE_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_FC_MODE_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH0_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_FC_MODE_RANGE                       25:24
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_FC_MODE_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_FC_MODE_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_FC_MODE_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_FC_MODE_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_FC_MODE_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_FC_MODE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_FC_MODE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_FC_MODE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_FC_MODE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_FC_MODE_NO_MMIO                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_FC_MODE_ONE_MMIO                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_FC_MODE_TWO_MMIO                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_FC_MODE_FOUR_MMIO                   MK_ENUM_CONST(3)
+
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_RANGE                      23:21
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_MSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_IO2MEM_NO_FC                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_IO2MEM_FC                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_MEM2IO_NO_FC                       MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_MEM2IO_FC                  MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_MEM2MEM                    MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_RSVD                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_DMA_MODE_FIXED_PAT                  MK_ENUM_CONST(6)
+
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_FIELD                       MK_FIELD_CONST(0x1f, GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_RANGE                       20:16
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_I2C1                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_I2C2                        MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_I2C3                        MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_SPI                 MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_UART1                       MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_UART2                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_DMIC                        MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_GTE                 MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_UART6                       MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_UART8                       MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_REQ_SEL_RSVD                        MK_ENUM_CONST(29)
+
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IRQ_MASK_SHIFT                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IRQ_MASK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IRQ_MASK_RANGE                      15:15
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IRQ_MASK_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IRQ_MASK_LSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IRQ_MASK_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IRQ_MASK_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IRQ_MASK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IRQ_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IRQ_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IRQ_MASK_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_IRQ_MASK_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_WEIGHT_SHIFT                        MK_SHIFT_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_WEIGHT_FIELD                        MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH0_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_WEIGHT_RANGE                        13:10
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_WEIGHT_MSB                  MK_SHIFT_CONST(13)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_WEIGHT_LSB                  MK_SHIFT_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_WEIGHT_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_WEIGHT_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_WEIGHT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_WEIGHT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_WEIGHT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_WEIGHT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSR_0_WEIGHT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH0_STA_0
+#define GPCDMA_AO_CHANNEL_CH0_STA_0                     MK_ADDR_CONST(0x10004)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_SECURE                      0x0
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_DUAL                        0x0
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_SCR                         SCR_CH0_0
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_RESET_MASK                  MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_READ_MASK                   MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_BSY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_BSY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_STA_0_BSY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_BSY_RANGE                   31:31
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_BSY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_BSY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_BSY_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_BSY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_BSY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_BSY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_BSY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_BSY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_BSY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_BSY_WAIT                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_BSY_ACTIVE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_ISE_EOC_SHIFT                       MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_ISE_EOC_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_ISE_EOC_RANGE                       30:30
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_ISE_EOC_MSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_ISE_EOC_LSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_ISE_EOC_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_ISE_EOC_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_ISE_EOC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_ISE_EOC_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_ISE_EOC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_ISE_EOC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_ISE_EOC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_ISE_EOC_NO_INTR                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_ISE_EOC_INTR                        MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_PING_PONG_STA_SHIFT                 MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_PING_PONG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_PING_PONG_STA_RANGE                 28:28
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_PING_PONG_STA_MSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_PING_PONG_STA_LSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_PING_PONG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_PING_PONG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_PING_PONG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_PING_PONG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_PING_PONG_STA_PING_INTR_STA                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_PING_PONG_STA_PONG_INTR_STA                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_DMA_ACTIVITY_SHIFT                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_DMA_ACTIVITY_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_DMA_ACTIVITY_RANGE                  27:27
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_DMA_ACTIVITY_MSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_DMA_ACTIVITY_LSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_DMA_ACTIVITY_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_DMA_ACTIVITY_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_DMA_ACTIVITY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_DMA_ACTIVITY_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_DMA_ACTIVITY_IDLE                   MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_DMA_ACTIVITY_BUSY                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_SHIFT                 MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_RANGE                 26:26
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_LSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_RESUME                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_PAUSE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_RX_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_RX_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_RX_RANGE                    25:25
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_RX_MSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_RX_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_RX_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_RX_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_RX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_RX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_RX_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_RX_NOT_ACTIVE                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_RX_ACTIVE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_TX_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_TX_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_TX_RANGE                    24:24
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_TX_MSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_TX_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_TX_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_TX_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_TX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_TX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_TX_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_TX_NOT_ACTIVE                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_CHANNEL_TX_ACTIVE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_IRQ_INTR_STA_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_IRQ_INTR_STA_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_IRQ_INTR_STA_RANGE                  23:23
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_IRQ_INTR_STA_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_IRQ_INTR_STA_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_IRQ_INTR_STA_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_IRQ_INTR_STA_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_IRQ_INTR_STA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_IRQ_INTR_STA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_IRQ_INTR_STA_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_IRQ_INTR_STA_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_TRIG_STA_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_TRIG_STA_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_TRIG_STA_RANGE                      21:21
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_TRIG_STA_MSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_TRIG_STA_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_TRIG_STA_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_TRIG_STA_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_TRIG_STA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_TRIG_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_TRIG_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_TRIG_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_TRIG_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_TRIG_STA_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_TRIG_STA_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_INTR_STA_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_INTR_STA_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_INTR_STA_RANGE                      20:20
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_INTR_STA_MSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_INTR_STA_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_INTR_STA_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_INTR_STA_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_INTR_STA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_INTR_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_INTR_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_INTR_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_INTR_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_INTR_STA_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_STA_0_INTR_STA_ACTIVE                     MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH0_CSRE_0
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0                    MK_ADDR_CONST(0x10008)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_SCR                        SCR_CH0_0
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_RESET_MASK                         MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_READ_MASK                  MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_WRITE_MASK                         MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_RANGE                 31:31
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_RESUME                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_PAUSE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_SHIFT                     MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_FIELD                     MK_FIELD_CONST(0x3f, GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_RANGE                     19:14
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_MSB                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_LSB                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x3f)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_SMP_24                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_SMP_25                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_SMP_26                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH0                       MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH1                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH2                       MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH3                       MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH4                       MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH5                       MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH6                       MK_ENUM_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH7                       MK_ENUM_CONST(11)
+#define GPCDMA_AO_CHANNEL_CH0_CSRE_0_TRIG_SEL_RSVD                      MK_ENUM_CONST(0)
+
+
+// Register GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0                 MK_ADDR_CONST(0x1000c)
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_SCR                     SCR_CH0_0
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH0_DST_PTR_0
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0                 MK_ADDR_CONST(0x10010)
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_SCR                     SCR_CH0_0
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_DST_PTR_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_DST_PTR_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_DST_PTR_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_DST_PTR_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_DST_PTR_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_DST_PTR_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_DST_PTR_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_DST_PTR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_DST_PTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_DST_PTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0                      MK_ADDR_CONST(0x10014)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_SECURE                       0x0
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_DUAL                         0x0
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_SCR                  SCR_CH0_0
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_RESET_MASK                   MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_READ_MASK                    MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_WRITE_MASK                   MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_FIELD                     MK_FIELD_CONST(0xff, GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_RANGE                     23:16
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                     MK_FIELD_CONST(0xff, GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                     7:0
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_MSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0                  MK_ADDR_CONST(0x10018)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_SECURE                   0x0
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_DUAL                     0x0
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_SCR                      SCR_CH0_0
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x3800000)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_SHIFT                       MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_RANGE                       31:31
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_LSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_DISABLE                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_SHIFT                 MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_FIELD                 MK_FIELD_CONST(0x3f, GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_RANGE                 30:25
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_LSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_BURST_SHIFT                   MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_BURST_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_BURST_RANGE                   24:23
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_BURST_MSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_BURST_LSB                     MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_BURST_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_BURST_DEFAULT                 MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_BURST_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_BURST_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                       MK_ENUM_CONST(3)
+
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                      22:20
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_MSB                        MK_SHIFT_CONST(22)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                   MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                   MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                  MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                  MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                      MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                      19:17
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_MSB                        MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_LSB                        MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                   MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                   MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                  MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                  MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_RANGE                   16:16
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_MSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_PROT_SHIFT                    MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_PROT_FIELD                    MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_PROT_RANGE                    15:14
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_PROT_MSB                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_PROT_LSB                      MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_PROT_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_PROT_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_PROT_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_PROT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID1_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID1_FIELD                  MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID1_RANGE                  13:7
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID1_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID1_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID1_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID1_DEFAULT_MASK                   MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID0_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID0_FIELD                  MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID0_RANGE                  6:0
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID0_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID0_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID0_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID0_DEFAULT_MASK                   MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0                        MK_ADDR_CONST(0x1001c)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_SECURE                         0x0
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_DUAL                   0x0
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_SCR                    SCR_CH0_0
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_WORD_COUNT                     0x1
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_RESET_VAL                      MK_MASK_CONST(0x2381007f)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_RESET_MASK                     MK_MASK_CONST(0xffff01ff)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_READ_MASK                      MK_MASK_CONST(0xffff01ff)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_WRITE_MASK                     MK_MASK_CONST(0xff870180)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_RANGE                  31:31
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                   30:28
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                 MK_MASK_CONST(0x2)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                    MK_ENUM_CONST(2)
+
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                   27:27
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_FIELD                       MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_RANGE                       26:23
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_MSB                 MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DEFAULT                     MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                    MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                   MK_ENUM_CONST(15)
+
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_SHIFT                   MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_RANGE                   22:19
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_MSB                     MK_SHIFT_CONST(22)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_LSB                     MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_RSVD                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_CCPLEX                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_CCPLEX_DPMU                     MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_BPMP                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_SPE                     MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_SCE                     MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_DMA_PER                 MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_TSECA                   MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_TSECB                   MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_JTAGM                   MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_CSITE                   MK_ENUM_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_MASTER_ID_APE                     MK_ENUM_CONST(11)
+
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                   18:16
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                     MK_SHIFT_CONST(18)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                  MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                  MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                  MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                 MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                 MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                 MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_SHIFT                        MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_FIELD                        MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_RANGE                        8:7
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_MSB                  MK_SHIFT_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_LSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                    6:0
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                  MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH0_BCOUNT_0
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0                  MK_ADDR_CONST(0x10020)
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_SECURE                   0x0
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_DUAL                     0x0
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_SCR                      SCR_CH0_0
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_BCOUNT_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_BCOUNT_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_BCOUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_BCOUNT_RANGE                     31:0
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_BCOUNT_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_BCOUNT_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_BCOUNT_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_BCOUNT_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_BCOUNT_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_BCOUNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_BCOUNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_BCOUNT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_BCOUNT_0_BCOUNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0                    MK_ADDR_CONST(0x10024)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_SCR                        SCR_CH0_0
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_TRANSFER_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_TRANSFER_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_TRANSFER_COUNT_RANGE                       31:0
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_TRANSFER_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_TRANSFER_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_TRANSFER_COUNT_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_TRANSFER_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_TRANSFER_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0                    MK_ADDR_CONST(0x10028)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_SCR                        SCR_CH0_0
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_DMA_COUNT_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_DMA_COUNT_FIELD                    MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_DMA_COUNT_RANGE                    31:0
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_DMA_COUNT_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_DMA_COUNT_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_DMA_COUNT_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_DMA_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_DMA_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_DMA_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_DMA_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_DMA_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x1002c
+
+// Register GPCDMA_AO_CHANNEL_CH0_ERR_STA_0
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0                 MK_ADDR_CONST(0x10030)
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_SCR                     SCR_CH0_0
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_RANGE                      31:0
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0                       MK_ADDR_CONST(0x10034)
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_SECURE                        0x0
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_DUAL                  0x0
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_SCR                   SCR_CH0_0
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH0_TZ_0
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0                      MK_ADDR_CONST(0x10038)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_SECURE                       0x0
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_DUAL                         0x0
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_SCR                  SCR_TZ_0
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_RESET_VAL                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_RESET_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_READ_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_WRITE_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MC_PROT_1_SHIFT                      MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MC_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MC_PROT_1_RANGE                      1:1
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MC_PROT_1_MSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MC_PROT_1_LSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MC_PROT_1_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MC_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MC_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MC_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MC_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MMIO_PROT_1_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MMIO_PROT_1_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH0_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MMIO_PROT_1_RANGE                    0:0
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MMIO_PROT_1_MSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MMIO_PROT_1_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MMIO_PROT_1_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MMIO_PROT_1_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MMIO_PROT_1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MMIO_PROT_1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH0_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH1_CSR_0
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0                     MK_ADDR_CONST(0x20000)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_SECURE                      0x0
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DUAL                        0x0
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_SCR                         SCR_CH1_0
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_RESET_VAL                   MK_MASK_CONST(0x8008400)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_RESET_MASK                  MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_READ_MASK                   MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_WRITE_MASK                  MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ENB_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ENB_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_CSR_0_ENB_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ENB_RANGE                   31:31
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ENB_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ENB_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ENB_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ENB_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ENB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ENB_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ENB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ENB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ENB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ENB_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ENB_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IE_EOC_SHIFT                        MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IE_EOC_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IE_EOC_RANGE                        30:30
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IE_EOC_MSB                  MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IE_EOC_LSB                  MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IE_EOC_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IE_EOC_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IE_EOC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IE_EOC_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IE_EOC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IE_EOC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IE_EOC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IE_EOC_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IE_EOC_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ONCE_SHIFT                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ONCE_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_CSR_0_ONCE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ONCE_RANGE                  27:27
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ONCE_MSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ONCE_LSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ONCE_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ONCE_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ONCE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ONCE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ONCE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ONCE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ONCE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ONCE_CYCLIC_MODE                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_ONCE_SINGLE_BLOCK                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_FC_MODE_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_FC_MODE_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH1_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_FC_MODE_RANGE                       25:24
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_FC_MODE_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_FC_MODE_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_FC_MODE_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_FC_MODE_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_FC_MODE_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_FC_MODE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_FC_MODE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_FC_MODE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_FC_MODE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_FC_MODE_NO_MMIO                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_FC_MODE_ONE_MMIO                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_FC_MODE_TWO_MMIO                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_FC_MODE_FOUR_MMIO                   MK_ENUM_CONST(3)
+
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_RANGE                      23:21
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_MSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_IO2MEM_NO_FC                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_IO2MEM_FC                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_MEM2IO_NO_FC                       MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_MEM2IO_FC                  MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_MEM2MEM                    MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_RSVD                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_DMA_MODE_FIXED_PAT                  MK_ENUM_CONST(6)
+
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_FIELD                       MK_FIELD_CONST(0x1f, GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_RANGE                       20:16
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_I2C1                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_I2C2                        MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_I2C3                        MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_SPI                 MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_UART1                       MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_UART2                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_DMIC                        MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_GTE                 MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_UART6                       MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_UART8                       MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_REQ_SEL_RSVD                        MK_ENUM_CONST(29)
+
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IRQ_MASK_SHIFT                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IRQ_MASK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IRQ_MASK_RANGE                      15:15
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IRQ_MASK_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IRQ_MASK_LSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IRQ_MASK_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IRQ_MASK_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IRQ_MASK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IRQ_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IRQ_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IRQ_MASK_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_IRQ_MASK_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_WEIGHT_SHIFT                        MK_SHIFT_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_WEIGHT_FIELD                        MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH1_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_WEIGHT_RANGE                        13:10
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_WEIGHT_MSB                  MK_SHIFT_CONST(13)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_WEIGHT_LSB                  MK_SHIFT_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_WEIGHT_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_WEIGHT_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_WEIGHT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_WEIGHT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_WEIGHT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_WEIGHT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSR_0_WEIGHT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH1_STA_0
+#define GPCDMA_AO_CHANNEL_CH1_STA_0                     MK_ADDR_CONST(0x20004)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_SECURE                      0x0
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_DUAL                        0x0
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_SCR                         SCR_CH1_0
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_RESET_MASK                  MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_READ_MASK                   MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_BSY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_BSY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_STA_0_BSY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_BSY_RANGE                   31:31
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_BSY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_BSY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_BSY_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_BSY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_BSY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_BSY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_BSY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_BSY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_BSY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_BSY_WAIT                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_BSY_ACTIVE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_ISE_EOC_SHIFT                       MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_ISE_EOC_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_ISE_EOC_RANGE                       30:30
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_ISE_EOC_MSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_ISE_EOC_LSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_ISE_EOC_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_ISE_EOC_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_ISE_EOC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_ISE_EOC_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_ISE_EOC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_ISE_EOC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_ISE_EOC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_ISE_EOC_NO_INTR                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_ISE_EOC_INTR                        MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_PING_PONG_STA_SHIFT                 MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_PING_PONG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_PING_PONG_STA_RANGE                 28:28
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_PING_PONG_STA_MSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_PING_PONG_STA_LSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_PING_PONG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_PING_PONG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_PING_PONG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_PING_PONG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_PING_PONG_STA_PING_INTR_STA                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_PING_PONG_STA_PONG_INTR_STA                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_DMA_ACTIVITY_SHIFT                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_DMA_ACTIVITY_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_DMA_ACTIVITY_RANGE                  27:27
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_DMA_ACTIVITY_MSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_DMA_ACTIVITY_LSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_DMA_ACTIVITY_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_DMA_ACTIVITY_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_DMA_ACTIVITY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_DMA_ACTIVITY_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_DMA_ACTIVITY_IDLE                   MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_DMA_ACTIVITY_BUSY                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_SHIFT                 MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_RANGE                 26:26
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_LSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_RESUME                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_PAUSE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_RX_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_RX_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_RX_RANGE                    25:25
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_RX_MSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_RX_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_RX_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_RX_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_RX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_RX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_RX_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_RX_NOT_ACTIVE                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_RX_ACTIVE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_TX_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_TX_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_TX_RANGE                    24:24
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_TX_MSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_TX_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_TX_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_TX_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_TX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_TX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_TX_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_TX_NOT_ACTIVE                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_CHANNEL_TX_ACTIVE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_IRQ_INTR_STA_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_IRQ_INTR_STA_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_IRQ_INTR_STA_RANGE                  23:23
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_IRQ_INTR_STA_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_IRQ_INTR_STA_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_IRQ_INTR_STA_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_IRQ_INTR_STA_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_IRQ_INTR_STA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_IRQ_INTR_STA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_IRQ_INTR_STA_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_IRQ_INTR_STA_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_TRIG_STA_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_TRIG_STA_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_TRIG_STA_RANGE                      21:21
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_TRIG_STA_MSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_TRIG_STA_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_TRIG_STA_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_TRIG_STA_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_TRIG_STA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_TRIG_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_TRIG_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_TRIG_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_TRIG_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_TRIG_STA_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_TRIG_STA_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_INTR_STA_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_INTR_STA_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_INTR_STA_RANGE                      20:20
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_INTR_STA_MSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_INTR_STA_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_INTR_STA_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_INTR_STA_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_INTR_STA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_INTR_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_INTR_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_INTR_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_INTR_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_INTR_STA_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_STA_0_INTR_STA_ACTIVE                     MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH1_CSRE_0
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0                    MK_ADDR_CONST(0x20008)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_SCR                        SCR_CH1_0
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_RESET_MASK                         MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_READ_MASK                  MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_WRITE_MASK                         MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_RANGE                 31:31
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_RESUME                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_PAUSE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_SHIFT                     MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_FIELD                     MK_FIELD_CONST(0x3f, GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_RANGE                     19:14
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_MSB                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_LSB                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x3f)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_SMP_24                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_SMP_25                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_SMP_26                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH0                       MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH1                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH2                       MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH3                       MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH4                       MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH5                       MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH6                       MK_ENUM_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH7                       MK_ENUM_CONST(11)
+#define GPCDMA_AO_CHANNEL_CH1_CSRE_0_TRIG_SEL_RSVD                      MK_ENUM_CONST(0)
+
+
+// Register GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0                 MK_ADDR_CONST(0x2000c)
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_SCR                     SCR_CH1_0
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH1_DST_PTR_0
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0                 MK_ADDR_CONST(0x20010)
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_SCR                     SCR_CH1_0
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_DST_PTR_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_DST_PTR_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_DST_PTR_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_DST_PTR_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_DST_PTR_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_DST_PTR_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_DST_PTR_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_DST_PTR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_DST_PTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_DST_PTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0                      MK_ADDR_CONST(0x20014)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_SECURE                       0x0
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_DUAL                         0x0
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_SCR                  SCR_CH1_0
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_RESET_MASK                   MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_READ_MASK                    MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_WRITE_MASK                   MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_FIELD                     MK_FIELD_CONST(0xff, GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_RANGE                     23:16
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                     MK_FIELD_CONST(0xff, GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                     7:0
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_MSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0                  MK_ADDR_CONST(0x20018)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_SECURE                   0x0
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_DUAL                     0x0
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_SCR                      SCR_CH1_0
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x3800000)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_SHIFT                       MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_RANGE                       31:31
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_LSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_DISABLE                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_SHIFT                 MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_FIELD                 MK_FIELD_CONST(0x3f, GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_RANGE                 30:25
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_LSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_BURST_SHIFT                   MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_BURST_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_BURST_RANGE                   24:23
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_BURST_MSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_BURST_LSB                     MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_BURST_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_BURST_DEFAULT                 MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_BURST_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_BURST_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                       MK_ENUM_CONST(3)
+
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                      22:20
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_MSB                        MK_SHIFT_CONST(22)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                   MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                   MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                  MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                  MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                      MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                      19:17
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_MSB                        MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_LSB                        MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                   MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                   MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                  MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                  MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_RANGE                   16:16
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_MSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_PROT_SHIFT                    MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_PROT_FIELD                    MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_PROT_RANGE                    15:14
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_PROT_MSB                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_PROT_LSB                      MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_PROT_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_PROT_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_PROT_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_PROT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID1_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID1_FIELD                  MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID1_RANGE                  13:7
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID1_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID1_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID1_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID1_DEFAULT_MASK                   MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID0_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID0_FIELD                  MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID0_RANGE                  6:0
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID0_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID0_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID0_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID0_DEFAULT_MASK                   MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0                        MK_ADDR_CONST(0x2001c)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_SECURE                         0x0
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_DUAL                   0x0
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_SCR                    SCR_CH1_0
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_WORD_COUNT                     0x1
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_RESET_VAL                      MK_MASK_CONST(0x2381007f)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_RESET_MASK                     MK_MASK_CONST(0xffff01ff)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_READ_MASK                      MK_MASK_CONST(0xffff01ff)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_WRITE_MASK                     MK_MASK_CONST(0xff870180)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_RANGE                  31:31
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                   30:28
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                 MK_MASK_CONST(0x2)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                    MK_ENUM_CONST(2)
+
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                   27:27
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_FIELD                       MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_RANGE                       26:23
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_MSB                 MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DEFAULT                     MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                    MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                   MK_ENUM_CONST(15)
+
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_SHIFT                   MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_RANGE                   22:19
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_MSB                     MK_SHIFT_CONST(22)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_LSB                     MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_RSVD                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_CCPLEX                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_CCPLEX_DPMU                     MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_BPMP                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_SPE                     MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_SCE                     MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_DMA_PER                 MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_TSECA                   MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_TSECB                   MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_JTAGM                   MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_CSITE                   MK_ENUM_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_MASTER_ID_APE                     MK_ENUM_CONST(11)
+
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                   18:16
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                     MK_SHIFT_CONST(18)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                  MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                  MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                  MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                 MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                 MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                 MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_SHIFT                        MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_FIELD                        MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_RANGE                        8:7
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_MSB                  MK_SHIFT_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_LSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                    6:0
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                  MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH1_BCOUNT_0
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0                  MK_ADDR_CONST(0x20020)
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_SECURE                   0x0
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_DUAL                     0x0
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_SCR                      SCR_CH1_0
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_BCOUNT_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_BCOUNT_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_BCOUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_BCOUNT_RANGE                     31:0
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_BCOUNT_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_BCOUNT_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_BCOUNT_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_BCOUNT_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_BCOUNT_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_BCOUNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_BCOUNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_BCOUNT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_BCOUNT_0_BCOUNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0                    MK_ADDR_CONST(0x20024)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_SCR                        SCR_CH1_0
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_TRANSFER_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_TRANSFER_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_TRANSFER_COUNT_RANGE                       31:0
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_TRANSFER_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_TRANSFER_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_TRANSFER_COUNT_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_TRANSFER_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_TRANSFER_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0                    MK_ADDR_CONST(0x20028)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_SCR                        SCR_CH1_0
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_DMA_COUNT_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_DMA_COUNT_FIELD                    MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_DMA_COUNT_RANGE                    31:0
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_DMA_COUNT_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_DMA_COUNT_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_DMA_COUNT_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_DMA_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_DMA_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_DMA_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_DMA_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_DMA_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x2002c
+
+// Register GPCDMA_AO_CHANNEL_CH1_ERR_STA_0
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0                 MK_ADDR_CONST(0x20030)
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_SCR                     SCR_CH1_0
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_RANGE                      31:0
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0                       MK_ADDR_CONST(0x20034)
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_SECURE                        0x0
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_DUAL                  0x0
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_SCR                   SCR_CH1_0
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH1_TZ_0
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0                      MK_ADDR_CONST(0x20038)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_SECURE                       0x0
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_DUAL                         0x0
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_SCR                  SCR_TZ_0
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_RESET_VAL                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_RESET_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_READ_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_WRITE_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MC_PROT_1_SHIFT                      MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MC_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MC_PROT_1_RANGE                      1:1
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MC_PROT_1_MSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MC_PROT_1_LSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MC_PROT_1_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MC_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MC_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MC_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MC_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MMIO_PROT_1_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MMIO_PROT_1_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH1_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MMIO_PROT_1_RANGE                    0:0
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MMIO_PROT_1_MSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MMIO_PROT_1_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MMIO_PROT_1_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MMIO_PROT_1_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MMIO_PROT_1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MMIO_PROT_1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH1_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH2_CSR_0
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0                     MK_ADDR_CONST(0x30000)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_SECURE                      0x0
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DUAL                        0x0
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_SCR                         SCR_CH2_0
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_RESET_VAL                   MK_MASK_CONST(0x8008400)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_RESET_MASK                  MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_READ_MASK                   MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_WRITE_MASK                  MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ENB_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ENB_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_CSR_0_ENB_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ENB_RANGE                   31:31
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ENB_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ENB_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ENB_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ENB_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ENB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ENB_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ENB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ENB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ENB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ENB_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ENB_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IE_EOC_SHIFT                        MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IE_EOC_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IE_EOC_RANGE                        30:30
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IE_EOC_MSB                  MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IE_EOC_LSB                  MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IE_EOC_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IE_EOC_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IE_EOC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IE_EOC_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IE_EOC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IE_EOC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IE_EOC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IE_EOC_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IE_EOC_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ONCE_SHIFT                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ONCE_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_CSR_0_ONCE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ONCE_RANGE                  27:27
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ONCE_MSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ONCE_LSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ONCE_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ONCE_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ONCE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ONCE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ONCE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ONCE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ONCE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ONCE_CYCLIC_MODE                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_ONCE_SINGLE_BLOCK                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_FC_MODE_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_FC_MODE_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH2_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_FC_MODE_RANGE                       25:24
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_FC_MODE_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_FC_MODE_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_FC_MODE_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_FC_MODE_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_FC_MODE_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_FC_MODE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_FC_MODE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_FC_MODE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_FC_MODE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_FC_MODE_NO_MMIO                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_FC_MODE_ONE_MMIO                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_FC_MODE_TWO_MMIO                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_FC_MODE_FOUR_MMIO                   MK_ENUM_CONST(3)
+
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_RANGE                      23:21
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_MSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_IO2MEM_NO_FC                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_IO2MEM_FC                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_MEM2IO_NO_FC                       MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_MEM2IO_FC                  MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_MEM2MEM                    MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_RSVD                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_DMA_MODE_FIXED_PAT                  MK_ENUM_CONST(6)
+
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_FIELD                       MK_FIELD_CONST(0x1f, GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_RANGE                       20:16
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_I2C1                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_I2C2                        MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_I2C3                        MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_SPI                 MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_UART1                       MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_UART2                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_DMIC                        MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_GTE                 MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_UART6                       MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_UART8                       MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_REQ_SEL_RSVD                        MK_ENUM_CONST(29)
+
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IRQ_MASK_SHIFT                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IRQ_MASK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IRQ_MASK_RANGE                      15:15
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IRQ_MASK_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IRQ_MASK_LSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IRQ_MASK_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IRQ_MASK_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IRQ_MASK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IRQ_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IRQ_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IRQ_MASK_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_IRQ_MASK_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_WEIGHT_SHIFT                        MK_SHIFT_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_WEIGHT_FIELD                        MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH2_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_WEIGHT_RANGE                        13:10
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_WEIGHT_MSB                  MK_SHIFT_CONST(13)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_WEIGHT_LSB                  MK_SHIFT_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_WEIGHT_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_WEIGHT_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_WEIGHT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_WEIGHT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_WEIGHT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_WEIGHT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSR_0_WEIGHT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH2_STA_0
+#define GPCDMA_AO_CHANNEL_CH2_STA_0                     MK_ADDR_CONST(0x30004)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_SECURE                      0x0
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_DUAL                        0x0
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_SCR                         SCR_CH2_0
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_RESET_MASK                  MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_READ_MASK                   MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_BSY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_BSY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_STA_0_BSY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_BSY_RANGE                   31:31
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_BSY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_BSY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_BSY_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_BSY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_BSY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_BSY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_BSY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_BSY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_BSY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_BSY_WAIT                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_BSY_ACTIVE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_ISE_EOC_SHIFT                       MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_ISE_EOC_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_ISE_EOC_RANGE                       30:30
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_ISE_EOC_MSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_ISE_EOC_LSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_ISE_EOC_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_ISE_EOC_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_ISE_EOC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_ISE_EOC_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_ISE_EOC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_ISE_EOC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_ISE_EOC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_ISE_EOC_NO_INTR                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_ISE_EOC_INTR                        MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_PING_PONG_STA_SHIFT                 MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_PING_PONG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_PING_PONG_STA_RANGE                 28:28
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_PING_PONG_STA_MSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_PING_PONG_STA_LSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_PING_PONG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_PING_PONG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_PING_PONG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_PING_PONG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_PING_PONG_STA_PING_INTR_STA                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_PING_PONG_STA_PONG_INTR_STA                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_DMA_ACTIVITY_SHIFT                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_DMA_ACTIVITY_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_DMA_ACTIVITY_RANGE                  27:27
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_DMA_ACTIVITY_MSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_DMA_ACTIVITY_LSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_DMA_ACTIVITY_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_DMA_ACTIVITY_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_DMA_ACTIVITY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_DMA_ACTIVITY_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_DMA_ACTIVITY_IDLE                   MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_DMA_ACTIVITY_BUSY                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_SHIFT                 MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_RANGE                 26:26
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_LSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_RESUME                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_PAUSE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_RX_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_RX_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_RX_RANGE                    25:25
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_RX_MSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_RX_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_RX_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_RX_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_RX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_RX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_RX_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_RX_NOT_ACTIVE                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_RX_ACTIVE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_TX_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_TX_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_TX_RANGE                    24:24
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_TX_MSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_TX_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_TX_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_TX_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_TX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_TX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_TX_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_TX_NOT_ACTIVE                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_CHANNEL_TX_ACTIVE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_IRQ_INTR_STA_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_IRQ_INTR_STA_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_IRQ_INTR_STA_RANGE                  23:23
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_IRQ_INTR_STA_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_IRQ_INTR_STA_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_IRQ_INTR_STA_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_IRQ_INTR_STA_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_IRQ_INTR_STA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_IRQ_INTR_STA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_IRQ_INTR_STA_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_IRQ_INTR_STA_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_TRIG_STA_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_TRIG_STA_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_TRIG_STA_RANGE                      21:21
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_TRIG_STA_MSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_TRIG_STA_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_TRIG_STA_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_TRIG_STA_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_TRIG_STA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_TRIG_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_TRIG_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_TRIG_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_TRIG_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_TRIG_STA_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_TRIG_STA_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_INTR_STA_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_INTR_STA_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_INTR_STA_RANGE                      20:20
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_INTR_STA_MSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_INTR_STA_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_INTR_STA_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_INTR_STA_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_INTR_STA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_INTR_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_INTR_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_INTR_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_INTR_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_INTR_STA_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_STA_0_INTR_STA_ACTIVE                     MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH2_CSRE_0
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0                    MK_ADDR_CONST(0x30008)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_SCR                        SCR_CH2_0
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_RESET_MASK                         MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_READ_MASK                  MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_WRITE_MASK                         MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_RANGE                 31:31
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_RESUME                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_PAUSE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_SHIFT                     MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_FIELD                     MK_FIELD_CONST(0x3f, GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_RANGE                     19:14
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_MSB                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_LSB                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x3f)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_SMP_24                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_SMP_25                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_SMP_26                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH0                       MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH1                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH2                       MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH3                       MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH4                       MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH5                       MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH6                       MK_ENUM_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH7                       MK_ENUM_CONST(11)
+#define GPCDMA_AO_CHANNEL_CH2_CSRE_0_TRIG_SEL_RSVD                      MK_ENUM_CONST(0)
+
+
+// Register GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0                 MK_ADDR_CONST(0x3000c)
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_SCR                     SCR_CH2_0
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH2_DST_PTR_0
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0                 MK_ADDR_CONST(0x30010)
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_SCR                     SCR_CH2_0
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_DST_PTR_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_DST_PTR_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_DST_PTR_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_DST_PTR_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_DST_PTR_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_DST_PTR_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_DST_PTR_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_DST_PTR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_DST_PTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_DST_PTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0                      MK_ADDR_CONST(0x30014)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_SECURE                       0x0
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_DUAL                         0x0
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_SCR                  SCR_CH2_0
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_RESET_MASK                   MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_READ_MASK                    MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_WRITE_MASK                   MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_FIELD                     MK_FIELD_CONST(0xff, GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_RANGE                     23:16
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                     MK_FIELD_CONST(0xff, GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                     7:0
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_MSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0                  MK_ADDR_CONST(0x30018)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_SECURE                   0x0
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_DUAL                     0x0
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_SCR                      SCR_CH2_0
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x3800000)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_SHIFT                       MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_RANGE                       31:31
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_LSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_DISABLE                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_SHIFT                 MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_FIELD                 MK_FIELD_CONST(0x3f, GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_RANGE                 30:25
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_LSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_BURST_SHIFT                   MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_BURST_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_BURST_RANGE                   24:23
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_BURST_MSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_BURST_LSB                     MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_BURST_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_BURST_DEFAULT                 MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_BURST_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_BURST_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                       MK_ENUM_CONST(3)
+
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                      22:20
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_MSB                        MK_SHIFT_CONST(22)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                   MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                   MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                  MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                  MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                      MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                      19:17
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_MSB                        MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_LSB                        MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                   MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                   MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                  MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                  MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_RANGE                   16:16
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_MSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_PROT_SHIFT                    MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_PROT_FIELD                    MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_PROT_RANGE                    15:14
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_PROT_MSB                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_PROT_LSB                      MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_PROT_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_PROT_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_PROT_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_PROT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID1_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID1_FIELD                  MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID1_RANGE                  13:7
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID1_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID1_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID1_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID1_DEFAULT_MASK                   MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID0_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID0_FIELD                  MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID0_RANGE                  6:0
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID0_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID0_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID0_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID0_DEFAULT_MASK                   MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0                        MK_ADDR_CONST(0x3001c)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_SECURE                         0x0
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_DUAL                   0x0
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_SCR                    SCR_CH2_0
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_WORD_COUNT                     0x1
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_RESET_VAL                      MK_MASK_CONST(0x2381007f)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_RESET_MASK                     MK_MASK_CONST(0xffff01ff)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_READ_MASK                      MK_MASK_CONST(0xffff01ff)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_WRITE_MASK                     MK_MASK_CONST(0xff870180)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_RANGE                  31:31
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                   30:28
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                 MK_MASK_CONST(0x2)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                    MK_ENUM_CONST(2)
+
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                   27:27
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_FIELD                       MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_RANGE                       26:23
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_MSB                 MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DEFAULT                     MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                    MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                   MK_ENUM_CONST(15)
+
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_SHIFT                   MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_RANGE                   22:19
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_MSB                     MK_SHIFT_CONST(22)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_LSB                     MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_RSVD                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_CCPLEX                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_CCPLEX_DPMU                     MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_BPMP                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_SPE                     MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_SCE                     MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_DMA_PER                 MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_TSECA                   MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_TSECB                   MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_JTAGM                   MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_CSITE                   MK_ENUM_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_MASTER_ID_APE                     MK_ENUM_CONST(11)
+
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                   18:16
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                     MK_SHIFT_CONST(18)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                  MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                  MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                  MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                 MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                 MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                 MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_SHIFT                        MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_FIELD                        MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_RANGE                        8:7
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_MSB                  MK_SHIFT_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_LSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                    6:0
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                  MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH2_BCOUNT_0
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0                  MK_ADDR_CONST(0x30020)
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_SECURE                   0x0
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_DUAL                     0x0
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_SCR                      SCR_CH2_0
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_BCOUNT_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_BCOUNT_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_BCOUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_BCOUNT_RANGE                     31:0
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_BCOUNT_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_BCOUNT_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_BCOUNT_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_BCOUNT_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_BCOUNT_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_BCOUNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_BCOUNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_BCOUNT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_BCOUNT_0_BCOUNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0                    MK_ADDR_CONST(0x30024)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_SCR                        SCR_CH2_0
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_TRANSFER_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_TRANSFER_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_TRANSFER_COUNT_RANGE                       31:0
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_TRANSFER_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_TRANSFER_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_TRANSFER_COUNT_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_TRANSFER_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_TRANSFER_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0                    MK_ADDR_CONST(0x30028)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_SCR                        SCR_CH2_0
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_DMA_COUNT_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_DMA_COUNT_FIELD                    MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_DMA_COUNT_RANGE                    31:0
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_DMA_COUNT_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_DMA_COUNT_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_DMA_COUNT_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_DMA_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_DMA_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_DMA_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_DMA_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_DMA_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x3002c
+
+// Register GPCDMA_AO_CHANNEL_CH2_ERR_STA_0
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0                 MK_ADDR_CONST(0x30030)
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_SCR                     SCR_CH2_0
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_RANGE                      31:0
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0                       MK_ADDR_CONST(0x30034)
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_SECURE                        0x0
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_DUAL                  0x0
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_SCR                   SCR_CH2_0
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH2_TZ_0
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0                      MK_ADDR_CONST(0x30038)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_SECURE                       0x0
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_DUAL                         0x0
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_SCR                  SCR_TZ_0
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_RESET_VAL                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_RESET_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_READ_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_WRITE_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MC_PROT_1_SHIFT                      MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MC_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MC_PROT_1_RANGE                      1:1
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MC_PROT_1_MSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MC_PROT_1_LSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MC_PROT_1_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MC_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MC_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MC_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MC_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MMIO_PROT_1_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MMIO_PROT_1_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH2_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MMIO_PROT_1_RANGE                    0:0
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MMIO_PROT_1_MSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MMIO_PROT_1_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MMIO_PROT_1_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MMIO_PROT_1_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MMIO_PROT_1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MMIO_PROT_1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH2_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH3_CSR_0
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0                     MK_ADDR_CONST(0x40000)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_SECURE                      0x0
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DUAL                        0x0
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_SCR                         SCR_CH3_0
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_RESET_VAL                   MK_MASK_CONST(0x8008400)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_RESET_MASK                  MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_READ_MASK                   MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_WRITE_MASK                  MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ENB_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ENB_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_CSR_0_ENB_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ENB_RANGE                   31:31
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ENB_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ENB_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ENB_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ENB_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ENB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ENB_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ENB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ENB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ENB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ENB_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ENB_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IE_EOC_SHIFT                        MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IE_EOC_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IE_EOC_RANGE                        30:30
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IE_EOC_MSB                  MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IE_EOC_LSB                  MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IE_EOC_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IE_EOC_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IE_EOC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IE_EOC_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IE_EOC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IE_EOC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IE_EOC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IE_EOC_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IE_EOC_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ONCE_SHIFT                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ONCE_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_CSR_0_ONCE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ONCE_RANGE                  27:27
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ONCE_MSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ONCE_LSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ONCE_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ONCE_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ONCE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ONCE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ONCE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ONCE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ONCE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ONCE_CYCLIC_MODE                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_ONCE_SINGLE_BLOCK                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_FC_MODE_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_FC_MODE_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH3_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_FC_MODE_RANGE                       25:24
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_FC_MODE_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_FC_MODE_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_FC_MODE_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_FC_MODE_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_FC_MODE_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_FC_MODE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_FC_MODE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_FC_MODE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_FC_MODE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_FC_MODE_NO_MMIO                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_FC_MODE_ONE_MMIO                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_FC_MODE_TWO_MMIO                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_FC_MODE_FOUR_MMIO                   MK_ENUM_CONST(3)
+
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_RANGE                      23:21
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_MSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_IO2MEM_NO_FC                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_IO2MEM_FC                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_MEM2IO_NO_FC                       MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_MEM2IO_FC                  MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_MEM2MEM                    MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_RSVD                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_DMA_MODE_FIXED_PAT                  MK_ENUM_CONST(6)
+
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_FIELD                       MK_FIELD_CONST(0x1f, GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_RANGE                       20:16
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_I2C1                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_I2C2                        MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_I2C3                        MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_SPI                 MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_UART1                       MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_UART2                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_DMIC                        MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_GTE                 MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_UART6                       MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_UART8                       MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_REQ_SEL_RSVD                        MK_ENUM_CONST(29)
+
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IRQ_MASK_SHIFT                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IRQ_MASK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IRQ_MASK_RANGE                      15:15
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IRQ_MASK_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IRQ_MASK_LSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IRQ_MASK_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IRQ_MASK_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IRQ_MASK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IRQ_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IRQ_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IRQ_MASK_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_IRQ_MASK_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_WEIGHT_SHIFT                        MK_SHIFT_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_WEIGHT_FIELD                        MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH3_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_WEIGHT_RANGE                        13:10
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_WEIGHT_MSB                  MK_SHIFT_CONST(13)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_WEIGHT_LSB                  MK_SHIFT_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_WEIGHT_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_WEIGHT_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_WEIGHT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_WEIGHT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_WEIGHT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_WEIGHT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSR_0_WEIGHT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH3_STA_0
+#define GPCDMA_AO_CHANNEL_CH3_STA_0                     MK_ADDR_CONST(0x40004)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_SECURE                      0x0
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_DUAL                        0x0
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_SCR                         SCR_CH3_0
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_RESET_MASK                  MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_READ_MASK                   MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_BSY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_BSY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_STA_0_BSY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_BSY_RANGE                   31:31
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_BSY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_BSY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_BSY_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_BSY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_BSY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_BSY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_BSY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_BSY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_BSY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_BSY_WAIT                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_BSY_ACTIVE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_ISE_EOC_SHIFT                       MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_ISE_EOC_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_ISE_EOC_RANGE                       30:30
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_ISE_EOC_MSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_ISE_EOC_LSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_ISE_EOC_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_ISE_EOC_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_ISE_EOC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_ISE_EOC_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_ISE_EOC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_ISE_EOC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_ISE_EOC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_ISE_EOC_NO_INTR                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_ISE_EOC_INTR                        MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_PING_PONG_STA_SHIFT                 MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_PING_PONG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_PING_PONG_STA_RANGE                 28:28
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_PING_PONG_STA_MSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_PING_PONG_STA_LSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_PING_PONG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_PING_PONG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_PING_PONG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_PING_PONG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_PING_PONG_STA_PING_INTR_STA                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_PING_PONG_STA_PONG_INTR_STA                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_DMA_ACTIVITY_SHIFT                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_DMA_ACTIVITY_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_DMA_ACTIVITY_RANGE                  27:27
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_DMA_ACTIVITY_MSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_DMA_ACTIVITY_LSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_DMA_ACTIVITY_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_DMA_ACTIVITY_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_DMA_ACTIVITY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_DMA_ACTIVITY_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_DMA_ACTIVITY_IDLE                   MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_DMA_ACTIVITY_BUSY                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_SHIFT                 MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_RANGE                 26:26
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_LSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_RESUME                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_PAUSE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_RX_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_RX_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_RX_RANGE                    25:25
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_RX_MSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_RX_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_RX_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_RX_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_RX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_RX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_RX_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_RX_NOT_ACTIVE                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_RX_ACTIVE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_TX_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_TX_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_TX_RANGE                    24:24
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_TX_MSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_TX_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_TX_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_TX_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_TX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_TX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_TX_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_TX_NOT_ACTIVE                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_CHANNEL_TX_ACTIVE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_IRQ_INTR_STA_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_IRQ_INTR_STA_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_IRQ_INTR_STA_RANGE                  23:23
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_IRQ_INTR_STA_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_IRQ_INTR_STA_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_IRQ_INTR_STA_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_IRQ_INTR_STA_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_IRQ_INTR_STA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_IRQ_INTR_STA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_IRQ_INTR_STA_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_IRQ_INTR_STA_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_TRIG_STA_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_TRIG_STA_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_TRIG_STA_RANGE                      21:21
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_TRIG_STA_MSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_TRIG_STA_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_TRIG_STA_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_TRIG_STA_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_TRIG_STA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_TRIG_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_TRIG_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_TRIG_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_TRIG_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_TRIG_STA_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_TRIG_STA_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_INTR_STA_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_INTR_STA_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_INTR_STA_RANGE                      20:20
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_INTR_STA_MSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_INTR_STA_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_INTR_STA_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_INTR_STA_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_INTR_STA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_INTR_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_INTR_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_INTR_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_INTR_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_INTR_STA_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_STA_0_INTR_STA_ACTIVE                     MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH3_CSRE_0
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0                    MK_ADDR_CONST(0x40008)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_SCR                        SCR_CH3_0
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_RESET_MASK                         MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_READ_MASK                  MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_WRITE_MASK                         MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_RANGE                 31:31
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_RESUME                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_PAUSE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_SHIFT                     MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_FIELD                     MK_FIELD_CONST(0x3f, GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_RANGE                     19:14
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_MSB                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_LSB                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x3f)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_SMP_24                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_SMP_25                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_SMP_26                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH0                       MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH1                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH2                       MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH3                       MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH4                       MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH5                       MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH6                       MK_ENUM_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH7                       MK_ENUM_CONST(11)
+#define GPCDMA_AO_CHANNEL_CH3_CSRE_0_TRIG_SEL_RSVD                      MK_ENUM_CONST(0)
+
+
+// Register GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0                 MK_ADDR_CONST(0x4000c)
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_SCR                     SCR_CH3_0
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH3_DST_PTR_0
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0                 MK_ADDR_CONST(0x40010)
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_SCR                     SCR_CH3_0
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_DST_PTR_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_DST_PTR_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_DST_PTR_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_DST_PTR_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_DST_PTR_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_DST_PTR_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_DST_PTR_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_DST_PTR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_DST_PTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_DST_PTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0                      MK_ADDR_CONST(0x40014)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_SECURE                       0x0
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_DUAL                         0x0
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_SCR                  SCR_CH3_0
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_RESET_MASK                   MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_READ_MASK                    MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_WRITE_MASK                   MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_FIELD                     MK_FIELD_CONST(0xff, GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_RANGE                     23:16
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                     MK_FIELD_CONST(0xff, GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                     7:0
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_MSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0                  MK_ADDR_CONST(0x40018)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_SECURE                   0x0
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_DUAL                     0x0
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_SCR                      SCR_CH3_0
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x3800000)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_SHIFT                       MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_RANGE                       31:31
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_LSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_DISABLE                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_SHIFT                 MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_FIELD                 MK_FIELD_CONST(0x3f, GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_RANGE                 30:25
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_LSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_BURST_SHIFT                   MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_BURST_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_BURST_RANGE                   24:23
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_BURST_MSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_BURST_LSB                     MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_BURST_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_BURST_DEFAULT                 MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_BURST_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_BURST_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                       MK_ENUM_CONST(3)
+
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                      22:20
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_MSB                        MK_SHIFT_CONST(22)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                   MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                   MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                  MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                  MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                      MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                      19:17
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_MSB                        MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_LSB                        MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                   MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                   MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                  MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                  MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_RANGE                   16:16
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_MSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_PROT_SHIFT                    MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_PROT_FIELD                    MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_PROT_RANGE                    15:14
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_PROT_MSB                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_PROT_LSB                      MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_PROT_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_PROT_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_PROT_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_PROT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID1_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID1_FIELD                  MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID1_RANGE                  13:7
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID1_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID1_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID1_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID1_DEFAULT_MASK                   MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID0_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID0_FIELD                  MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID0_RANGE                  6:0
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID0_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID0_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID0_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID0_DEFAULT_MASK                   MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0                        MK_ADDR_CONST(0x4001c)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_SECURE                         0x0
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_DUAL                   0x0
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_SCR                    SCR_CH3_0
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_WORD_COUNT                     0x1
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_RESET_VAL                      MK_MASK_CONST(0x2381007f)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_RESET_MASK                     MK_MASK_CONST(0xffff01ff)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_READ_MASK                      MK_MASK_CONST(0xffff01ff)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_WRITE_MASK                     MK_MASK_CONST(0xff870180)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_RANGE                  31:31
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                   30:28
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                 MK_MASK_CONST(0x2)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                    MK_ENUM_CONST(2)
+
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                   27:27
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_FIELD                       MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_RANGE                       26:23
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_MSB                 MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DEFAULT                     MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                    MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                   MK_ENUM_CONST(15)
+
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_SHIFT                   MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_RANGE                   22:19
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_MSB                     MK_SHIFT_CONST(22)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_LSB                     MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_RSVD                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_CCPLEX                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_CCPLEX_DPMU                     MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_BPMP                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_SPE                     MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_SCE                     MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_DMA_PER                 MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_TSECA                   MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_TSECB                   MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_JTAGM                   MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_CSITE                   MK_ENUM_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_MASTER_ID_APE                     MK_ENUM_CONST(11)
+
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                   18:16
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                     MK_SHIFT_CONST(18)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                  MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                  MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                  MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                 MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                 MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                 MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_SHIFT                        MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_FIELD                        MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_RANGE                        8:7
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_MSB                  MK_SHIFT_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_LSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                    6:0
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                  MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH3_BCOUNT_0
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0                  MK_ADDR_CONST(0x40020)
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_SECURE                   0x0
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_DUAL                     0x0
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_SCR                      SCR_CH3_0
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_BCOUNT_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_BCOUNT_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_BCOUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_BCOUNT_RANGE                     31:0
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_BCOUNT_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_BCOUNT_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_BCOUNT_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_BCOUNT_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_BCOUNT_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_BCOUNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_BCOUNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_BCOUNT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_BCOUNT_0_BCOUNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0                    MK_ADDR_CONST(0x40024)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_SCR                        SCR_CH3_0
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_TRANSFER_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_TRANSFER_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_TRANSFER_COUNT_RANGE                       31:0
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_TRANSFER_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_TRANSFER_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_TRANSFER_COUNT_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_TRANSFER_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_TRANSFER_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0                    MK_ADDR_CONST(0x40028)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_SCR                        SCR_CH3_0
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_DMA_COUNT_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_DMA_COUNT_FIELD                    MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_DMA_COUNT_RANGE                    31:0
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_DMA_COUNT_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_DMA_COUNT_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_DMA_COUNT_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_DMA_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_DMA_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_DMA_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_DMA_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_DMA_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x4002c
+
+// Register GPCDMA_AO_CHANNEL_CH3_ERR_STA_0
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0                 MK_ADDR_CONST(0x40030)
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_SCR                     SCR_CH3_0
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_RANGE                      31:0
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0                       MK_ADDR_CONST(0x40034)
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_SECURE                        0x0
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_DUAL                  0x0
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_SCR                   SCR_CH3_0
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH3_TZ_0
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0                      MK_ADDR_CONST(0x40038)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_SECURE                       0x0
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_DUAL                         0x0
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_SCR                  SCR_TZ_0
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_RESET_VAL                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_RESET_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_READ_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_WRITE_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MC_PROT_1_SHIFT                      MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MC_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MC_PROT_1_RANGE                      1:1
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MC_PROT_1_MSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MC_PROT_1_LSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MC_PROT_1_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MC_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MC_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MC_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MC_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MMIO_PROT_1_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MMIO_PROT_1_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH3_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MMIO_PROT_1_RANGE                    0:0
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MMIO_PROT_1_MSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MMIO_PROT_1_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MMIO_PROT_1_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MMIO_PROT_1_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MMIO_PROT_1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MMIO_PROT_1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH3_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH4_CSR_0
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0                     MK_ADDR_CONST(0x50000)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_SECURE                      0x0
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DUAL                        0x0
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_SCR                         SCR_CH4_0
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_RESET_VAL                   MK_MASK_CONST(0x8008400)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_RESET_MASK                  MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_READ_MASK                   MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_WRITE_MASK                  MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ENB_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ENB_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_CSR_0_ENB_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ENB_RANGE                   31:31
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ENB_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ENB_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ENB_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ENB_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ENB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ENB_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ENB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ENB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ENB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ENB_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ENB_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IE_EOC_SHIFT                        MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IE_EOC_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IE_EOC_RANGE                        30:30
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IE_EOC_MSB                  MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IE_EOC_LSB                  MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IE_EOC_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IE_EOC_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IE_EOC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IE_EOC_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IE_EOC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IE_EOC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IE_EOC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IE_EOC_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IE_EOC_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ONCE_SHIFT                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ONCE_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_CSR_0_ONCE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ONCE_RANGE                  27:27
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ONCE_MSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ONCE_LSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ONCE_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ONCE_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ONCE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ONCE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ONCE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ONCE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ONCE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ONCE_CYCLIC_MODE                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_ONCE_SINGLE_BLOCK                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_FC_MODE_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_FC_MODE_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH4_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_FC_MODE_RANGE                       25:24
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_FC_MODE_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_FC_MODE_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_FC_MODE_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_FC_MODE_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_FC_MODE_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_FC_MODE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_FC_MODE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_FC_MODE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_FC_MODE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_FC_MODE_NO_MMIO                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_FC_MODE_ONE_MMIO                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_FC_MODE_TWO_MMIO                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_FC_MODE_FOUR_MMIO                   MK_ENUM_CONST(3)
+
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_RANGE                      23:21
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_MSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_IO2MEM_NO_FC                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_IO2MEM_FC                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_MEM2IO_NO_FC                       MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_MEM2IO_FC                  MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_MEM2MEM                    MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_RSVD                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_DMA_MODE_FIXED_PAT                  MK_ENUM_CONST(6)
+
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_FIELD                       MK_FIELD_CONST(0x1f, GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_RANGE                       20:16
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_I2C1                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_I2C2                        MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_I2C3                        MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_SPI                 MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_UART1                       MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_UART2                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_DMIC                        MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_GTE                 MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_UART6                       MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_UART8                       MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_REQ_SEL_RSVD                        MK_ENUM_CONST(29)
+
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IRQ_MASK_SHIFT                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IRQ_MASK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IRQ_MASK_RANGE                      15:15
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IRQ_MASK_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IRQ_MASK_LSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IRQ_MASK_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IRQ_MASK_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IRQ_MASK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IRQ_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IRQ_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IRQ_MASK_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_IRQ_MASK_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_WEIGHT_SHIFT                        MK_SHIFT_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_WEIGHT_FIELD                        MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH4_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_WEIGHT_RANGE                        13:10
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_WEIGHT_MSB                  MK_SHIFT_CONST(13)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_WEIGHT_LSB                  MK_SHIFT_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_WEIGHT_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_WEIGHT_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_WEIGHT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_WEIGHT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_WEIGHT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_WEIGHT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSR_0_WEIGHT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH4_STA_0
+#define GPCDMA_AO_CHANNEL_CH4_STA_0                     MK_ADDR_CONST(0x50004)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_SECURE                      0x0
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_DUAL                        0x0
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_SCR                         SCR_CH4_0
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_RESET_MASK                  MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_READ_MASK                   MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_BSY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_BSY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_STA_0_BSY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_BSY_RANGE                   31:31
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_BSY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_BSY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_BSY_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_BSY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_BSY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_BSY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_BSY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_BSY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_BSY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_BSY_WAIT                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_BSY_ACTIVE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_ISE_EOC_SHIFT                       MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_ISE_EOC_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_ISE_EOC_RANGE                       30:30
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_ISE_EOC_MSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_ISE_EOC_LSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_ISE_EOC_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_ISE_EOC_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_ISE_EOC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_ISE_EOC_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_ISE_EOC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_ISE_EOC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_ISE_EOC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_ISE_EOC_NO_INTR                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_ISE_EOC_INTR                        MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_PING_PONG_STA_SHIFT                 MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_PING_PONG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_PING_PONG_STA_RANGE                 28:28
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_PING_PONG_STA_MSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_PING_PONG_STA_LSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_PING_PONG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_PING_PONG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_PING_PONG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_PING_PONG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_PING_PONG_STA_PING_INTR_STA                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_PING_PONG_STA_PONG_INTR_STA                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_DMA_ACTIVITY_SHIFT                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_DMA_ACTIVITY_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_DMA_ACTIVITY_RANGE                  27:27
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_DMA_ACTIVITY_MSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_DMA_ACTIVITY_LSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_DMA_ACTIVITY_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_DMA_ACTIVITY_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_DMA_ACTIVITY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_DMA_ACTIVITY_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_DMA_ACTIVITY_IDLE                   MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_DMA_ACTIVITY_BUSY                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_SHIFT                 MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_RANGE                 26:26
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_LSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_RESUME                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_PAUSE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_RX_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_RX_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_RX_RANGE                    25:25
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_RX_MSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_RX_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_RX_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_RX_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_RX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_RX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_RX_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_RX_NOT_ACTIVE                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_RX_ACTIVE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_TX_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_TX_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_TX_RANGE                    24:24
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_TX_MSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_TX_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_TX_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_TX_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_TX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_TX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_TX_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_TX_NOT_ACTIVE                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_CHANNEL_TX_ACTIVE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_IRQ_INTR_STA_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_IRQ_INTR_STA_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_IRQ_INTR_STA_RANGE                  23:23
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_IRQ_INTR_STA_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_IRQ_INTR_STA_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_IRQ_INTR_STA_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_IRQ_INTR_STA_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_IRQ_INTR_STA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_IRQ_INTR_STA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_IRQ_INTR_STA_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_IRQ_INTR_STA_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_TRIG_STA_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_TRIG_STA_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_TRIG_STA_RANGE                      21:21
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_TRIG_STA_MSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_TRIG_STA_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_TRIG_STA_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_TRIG_STA_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_TRIG_STA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_TRIG_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_TRIG_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_TRIG_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_TRIG_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_TRIG_STA_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_TRIG_STA_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_INTR_STA_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_INTR_STA_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_INTR_STA_RANGE                      20:20
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_INTR_STA_MSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_INTR_STA_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_INTR_STA_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_INTR_STA_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_INTR_STA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_INTR_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_INTR_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_INTR_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_INTR_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_INTR_STA_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_STA_0_INTR_STA_ACTIVE                     MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH4_CSRE_0
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0                    MK_ADDR_CONST(0x50008)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_SCR                        SCR_CH4_0
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_RESET_MASK                         MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_READ_MASK                  MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_WRITE_MASK                         MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_RANGE                 31:31
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_RESUME                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_PAUSE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_SHIFT                     MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_FIELD                     MK_FIELD_CONST(0x3f, GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_RANGE                     19:14
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_MSB                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_LSB                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x3f)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_SMP_24                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_SMP_25                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_SMP_26                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH0                       MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH1                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH2                       MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH3                       MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH4                       MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH5                       MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH6                       MK_ENUM_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH7                       MK_ENUM_CONST(11)
+#define GPCDMA_AO_CHANNEL_CH4_CSRE_0_TRIG_SEL_RSVD                      MK_ENUM_CONST(0)
+
+
+// Register GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0                 MK_ADDR_CONST(0x5000c)
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_SCR                     SCR_CH4_0
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH4_DST_PTR_0
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0                 MK_ADDR_CONST(0x50010)
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_SCR                     SCR_CH4_0
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_DST_PTR_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_DST_PTR_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_DST_PTR_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_DST_PTR_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_DST_PTR_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_DST_PTR_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_DST_PTR_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_DST_PTR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_DST_PTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_DST_PTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0                      MK_ADDR_CONST(0x50014)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_SECURE                       0x0
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_DUAL                         0x0
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_SCR                  SCR_CH4_0
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_RESET_MASK                   MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_READ_MASK                    MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_WRITE_MASK                   MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_FIELD                     MK_FIELD_CONST(0xff, GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_RANGE                     23:16
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                     MK_FIELD_CONST(0xff, GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                     7:0
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_MSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0                  MK_ADDR_CONST(0x50018)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_SECURE                   0x0
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_DUAL                     0x0
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_SCR                      SCR_CH4_0
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x3800000)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_SHIFT                       MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_RANGE                       31:31
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_LSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_DISABLE                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_SHIFT                 MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_FIELD                 MK_FIELD_CONST(0x3f, GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_RANGE                 30:25
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_LSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_BURST_SHIFT                   MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_BURST_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_BURST_RANGE                   24:23
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_BURST_MSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_BURST_LSB                     MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_BURST_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_BURST_DEFAULT                 MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_BURST_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_BURST_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                       MK_ENUM_CONST(3)
+
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                      22:20
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_MSB                        MK_SHIFT_CONST(22)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                   MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                   MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                  MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                  MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                      MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                      19:17
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_MSB                        MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_LSB                        MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                   MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                   MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                  MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                  MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_RANGE                   16:16
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_MSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_PROT_SHIFT                    MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_PROT_FIELD                    MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_PROT_RANGE                    15:14
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_PROT_MSB                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_PROT_LSB                      MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_PROT_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_PROT_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_PROT_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_PROT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID1_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID1_FIELD                  MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID1_RANGE                  13:7
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID1_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID1_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID1_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID1_DEFAULT_MASK                   MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID0_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID0_FIELD                  MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID0_RANGE                  6:0
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID0_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID0_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID0_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID0_DEFAULT_MASK                   MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0                        MK_ADDR_CONST(0x5001c)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_SECURE                         0x0
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_DUAL                   0x0
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_SCR                    SCR_CH4_0
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_WORD_COUNT                     0x1
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_RESET_VAL                      MK_MASK_CONST(0x2381007f)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_RESET_MASK                     MK_MASK_CONST(0xffff01ff)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_READ_MASK                      MK_MASK_CONST(0xffff01ff)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_WRITE_MASK                     MK_MASK_CONST(0xff870180)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_RANGE                  31:31
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                   30:28
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                 MK_MASK_CONST(0x2)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                    MK_ENUM_CONST(2)
+
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                   27:27
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_FIELD                       MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_RANGE                       26:23
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_MSB                 MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DEFAULT                     MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                    MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                   MK_ENUM_CONST(15)
+
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_SHIFT                   MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_RANGE                   22:19
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_MSB                     MK_SHIFT_CONST(22)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_LSB                     MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_RSVD                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_CCPLEX                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_CCPLEX_DPMU                     MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_BPMP                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_SPE                     MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_SCE                     MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_DMA_PER                 MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_TSECA                   MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_TSECB                   MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_JTAGM                   MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_CSITE                   MK_ENUM_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_MASTER_ID_APE                     MK_ENUM_CONST(11)
+
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                   18:16
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                     MK_SHIFT_CONST(18)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                  MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                  MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                  MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                 MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                 MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                 MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_SHIFT                        MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_FIELD                        MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_RANGE                        8:7
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_MSB                  MK_SHIFT_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_LSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                    6:0
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                  MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH4_BCOUNT_0
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0                  MK_ADDR_CONST(0x50020)
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_SECURE                   0x0
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_DUAL                     0x0
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_SCR                      SCR_CH4_0
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_BCOUNT_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_BCOUNT_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_BCOUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_BCOUNT_RANGE                     31:0
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_BCOUNT_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_BCOUNT_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_BCOUNT_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_BCOUNT_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_BCOUNT_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_BCOUNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_BCOUNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_BCOUNT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_BCOUNT_0_BCOUNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0                    MK_ADDR_CONST(0x50024)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_SCR                        SCR_CH4_0
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_TRANSFER_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_TRANSFER_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_TRANSFER_COUNT_RANGE                       31:0
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_TRANSFER_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_TRANSFER_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_TRANSFER_COUNT_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_TRANSFER_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_TRANSFER_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0                    MK_ADDR_CONST(0x50028)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_SCR                        SCR_CH4_0
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_DMA_COUNT_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_DMA_COUNT_FIELD                    MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_DMA_COUNT_RANGE                    31:0
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_DMA_COUNT_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_DMA_COUNT_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_DMA_COUNT_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_DMA_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_DMA_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_DMA_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_DMA_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_DMA_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x5002c
+
+// Register GPCDMA_AO_CHANNEL_CH4_ERR_STA_0
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0                 MK_ADDR_CONST(0x50030)
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_SCR                     SCR_CH4_0
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_RANGE                      31:0
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0                       MK_ADDR_CONST(0x50034)
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_SECURE                        0x0
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_DUAL                  0x0
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_SCR                   SCR_CH4_0
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH4_TZ_0
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0                      MK_ADDR_CONST(0x50038)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_SECURE                       0x0
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_DUAL                         0x0
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_SCR                  SCR_TZ_0
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_RESET_VAL                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_RESET_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_READ_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_WRITE_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MC_PROT_1_SHIFT                      MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MC_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MC_PROT_1_RANGE                      1:1
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MC_PROT_1_MSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MC_PROT_1_LSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MC_PROT_1_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MC_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MC_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MC_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MC_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MMIO_PROT_1_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MMIO_PROT_1_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MMIO_PROT_1_RANGE                    0:0
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MMIO_PROT_1_MSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MMIO_PROT_1_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MMIO_PROT_1_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MMIO_PROT_1_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MMIO_PROT_1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MMIO_PROT_1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH4_SPARE_0
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0                   MK_ADDR_CONST(0x50040)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SECURE                    0x0
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_DUAL                      0x0
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SCR                       SCR_CH4_0
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_WORD_COUNT                        0x1
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_RESET_VAL                         MK_MASK_CONST(0xffff0000)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_HI_SHIFT                    MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_HI_FIELD                    MK_FIELD_CONST(0x7fff, GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_HI_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_HI_RANGE                    31:17
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_HI_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_HI_LSB                      MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_HI_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_HI_DEFAULT                  MK_MASK_CONST(0x7fff)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_HI_DEFAULT_MASK                     MK_MASK_CONST(0x7fff)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_HI_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_HI_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_HI_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_HI_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_ENABLE_LEGACY_FC_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_ENABLE_LEGACY_FC_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH4_SPARE_0_ENABLE_LEGACY_FC_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_ENABLE_LEGACY_FC_RANGE                    16:16
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_ENABLE_LEGACY_FC_MSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_ENABLE_LEGACY_FC_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_ENABLE_LEGACY_FC_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_ENABLE_LEGACY_FC_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_ENABLE_LEGACY_FC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_ENABLE_LEGACY_FC_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_ENABLE_LEGACY_FC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_ENABLE_LEGACY_FC_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_ENABLE_LEGACY_FC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_LO_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_LO_FIELD                    MK_FIELD_CONST(0xffff, GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_LO_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_LO_RANGE                    15:0
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_LO_MSB                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_LO_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_LO_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_LO_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_LO_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_LO_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_LO_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_LO_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH4_SPARE_0_SPARE_LO_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH5_CSR_0
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0                     MK_ADDR_CONST(0x60000)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_SECURE                      0x0
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DUAL                        0x0
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_SCR                         SCR_CH5_0
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_RESET_VAL                   MK_MASK_CONST(0x8008400)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_RESET_MASK                  MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_READ_MASK                   MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_WRITE_MASK                  MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ENB_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ENB_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_CSR_0_ENB_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ENB_RANGE                   31:31
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ENB_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ENB_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ENB_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ENB_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ENB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ENB_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ENB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ENB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ENB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ENB_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ENB_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IE_EOC_SHIFT                        MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IE_EOC_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IE_EOC_RANGE                        30:30
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IE_EOC_MSB                  MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IE_EOC_LSB                  MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IE_EOC_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IE_EOC_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IE_EOC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IE_EOC_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IE_EOC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IE_EOC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IE_EOC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IE_EOC_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IE_EOC_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ONCE_SHIFT                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ONCE_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_CSR_0_ONCE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ONCE_RANGE                  27:27
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ONCE_MSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ONCE_LSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ONCE_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ONCE_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ONCE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ONCE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ONCE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ONCE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ONCE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ONCE_CYCLIC_MODE                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_ONCE_SINGLE_BLOCK                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_FC_MODE_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_FC_MODE_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH5_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_FC_MODE_RANGE                       25:24
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_FC_MODE_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_FC_MODE_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_FC_MODE_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_FC_MODE_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_FC_MODE_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_FC_MODE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_FC_MODE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_FC_MODE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_FC_MODE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_FC_MODE_NO_MMIO                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_FC_MODE_ONE_MMIO                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_FC_MODE_TWO_MMIO                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_FC_MODE_FOUR_MMIO                   MK_ENUM_CONST(3)
+
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_RANGE                      23:21
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_MSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_IO2MEM_NO_FC                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_IO2MEM_FC                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_MEM2IO_NO_FC                       MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_MEM2IO_FC                  MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_MEM2MEM                    MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_RSVD                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_DMA_MODE_FIXED_PAT                  MK_ENUM_CONST(6)
+
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_FIELD                       MK_FIELD_CONST(0x1f, GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_RANGE                       20:16
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_I2C1                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_I2C2                        MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_I2C3                        MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_SPI                 MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_UART1                       MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_UART2                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_DMIC                        MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_GTE                 MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_UART6                       MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_UART8                       MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_REQ_SEL_RSVD                        MK_ENUM_CONST(29)
+
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IRQ_MASK_SHIFT                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IRQ_MASK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IRQ_MASK_RANGE                      15:15
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IRQ_MASK_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IRQ_MASK_LSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IRQ_MASK_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IRQ_MASK_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IRQ_MASK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IRQ_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IRQ_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IRQ_MASK_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_IRQ_MASK_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_WEIGHT_SHIFT                        MK_SHIFT_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_WEIGHT_FIELD                        MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH5_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_WEIGHT_RANGE                        13:10
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_WEIGHT_MSB                  MK_SHIFT_CONST(13)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_WEIGHT_LSB                  MK_SHIFT_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_WEIGHT_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_WEIGHT_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_WEIGHT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_WEIGHT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_WEIGHT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_WEIGHT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSR_0_WEIGHT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH5_STA_0
+#define GPCDMA_AO_CHANNEL_CH5_STA_0                     MK_ADDR_CONST(0x60004)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_SECURE                      0x0
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_DUAL                        0x0
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_SCR                         SCR_CH5_0
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_RESET_MASK                  MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_READ_MASK                   MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_BSY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_BSY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_STA_0_BSY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_BSY_RANGE                   31:31
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_BSY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_BSY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_BSY_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_BSY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_BSY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_BSY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_BSY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_BSY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_BSY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_BSY_WAIT                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_BSY_ACTIVE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_ISE_EOC_SHIFT                       MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_ISE_EOC_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_ISE_EOC_RANGE                       30:30
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_ISE_EOC_MSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_ISE_EOC_LSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_ISE_EOC_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_ISE_EOC_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_ISE_EOC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_ISE_EOC_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_ISE_EOC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_ISE_EOC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_ISE_EOC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_ISE_EOC_NO_INTR                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_ISE_EOC_INTR                        MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_PING_PONG_STA_SHIFT                 MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_PING_PONG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_PING_PONG_STA_RANGE                 28:28
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_PING_PONG_STA_MSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_PING_PONG_STA_LSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_PING_PONG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_PING_PONG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_PING_PONG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_PING_PONG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_PING_PONG_STA_PING_INTR_STA                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_PING_PONG_STA_PONG_INTR_STA                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_DMA_ACTIVITY_SHIFT                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_DMA_ACTIVITY_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_DMA_ACTIVITY_RANGE                  27:27
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_DMA_ACTIVITY_MSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_DMA_ACTIVITY_LSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_DMA_ACTIVITY_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_DMA_ACTIVITY_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_DMA_ACTIVITY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_DMA_ACTIVITY_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_DMA_ACTIVITY_IDLE                   MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_DMA_ACTIVITY_BUSY                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_SHIFT                 MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_RANGE                 26:26
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_LSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_RESUME                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_PAUSE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_RX_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_RX_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_RX_RANGE                    25:25
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_RX_MSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_RX_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_RX_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_RX_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_RX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_RX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_RX_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_RX_NOT_ACTIVE                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_RX_ACTIVE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_TX_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_TX_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_TX_RANGE                    24:24
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_TX_MSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_TX_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_TX_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_TX_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_TX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_TX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_TX_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_TX_NOT_ACTIVE                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_CHANNEL_TX_ACTIVE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_IRQ_INTR_STA_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_IRQ_INTR_STA_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_IRQ_INTR_STA_RANGE                  23:23
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_IRQ_INTR_STA_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_IRQ_INTR_STA_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_IRQ_INTR_STA_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_IRQ_INTR_STA_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_IRQ_INTR_STA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_IRQ_INTR_STA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_IRQ_INTR_STA_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_IRQ_INTR_STA_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_TRIG_STA_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_TRIG_STA_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_TRIG_STA_RANGE                      21:21
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_TRIG_STA_MSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_TRIG_STA_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_TRIG_STA_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_TRIG_STA_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_TRIG_STA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_TRIG_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_TRIG_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_TRIG_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_TRIG_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_TRIG_STA_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_TRIG_STA_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_INTR_STA_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_INTR_STA_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_INTR_STA_RANGE                      20:20
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_INTR_STA_MSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_INTR_STA_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_INTR_STA_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_INTR_STA_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_INTR_STA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_INTR_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_INTR_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_INTR_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_INTR_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_INTR_STA_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_STA_0_INTR_STA_ACTIVE                     MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH5_CSRE_0
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0                    MK_ADDR_CONST(0x60008)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_SCR                        SCR_CH5_0
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_RESET_MASK                         MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_READ_MASK                  MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_WRITE_MASK                         MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_RANGE                 31:31
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_RESUME                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_PAUSE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_SHIFT                     MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_FIELD                     MK_FIELD_CONST(0x3f, GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_RANGE                     19:14
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_MSB                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_LSB                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x3f)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_SMP_24                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_SMP_25                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_SMP_26                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH0                       MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH1                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH2                       MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH3                       MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH4                       MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH5                       MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH6                       MK_ENUM_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH7                       MK_ENUM_CONST(11)
+#define GPCDMA_AO_CHANNEL_CH5_CSRE_0_TRIG_SEL_RSVD                      MK_ENUM_CONST(0)
+
+
+// Register GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0                 MK_ADDR_CONST(0x6000c)
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_SCR                     SCR_CH5_0
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH5_DST_PTR_0
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0                 MK_ADDR_CONST(0x60010)
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_SCR                     SCR_CH5_0
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_DST_PTR_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_DST_PTR_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_DST_PTR_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_DST_PTR_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_DST_PTR_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_DST_PTR_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_DST_PTR_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_DST_PTR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_DST_PTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_DST_PTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0                      MK_ADDR_CONST(0x60014)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_SECURE                       0x0
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_DUAL                         0x0
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_SCR                  SCR_CH5_0
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_RESET_MASK                   MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_READ_MASK                    MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_WRITE_MASK                   MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_FIELD                     MK_FIELD_CONST(0xff, GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_RANGE                     23:16
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                     MK_FIELD_CONST(0xff, GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                     7:0
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_MSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0                  MK_ADDR_CONST(0x60018)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_SECURE                   0x0
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_DUAL                     0x0
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_SCR                      SCR_CH5_0
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x3800000)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_SHIFT                       MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_RANGE                       31:31
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_LSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_DISABLE                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_SHIFT                 MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_FIELD                 MK_FIELD_CONST(0x3f, GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_RANGE                 30:25
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_LSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_BURST_SHIFT                   MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_BURST_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_BURST_RANGE                   24:23
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_BURST_MSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_BURST_LSB                     MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_BURST_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_BURST_DEFAULT                 MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_BURST_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_BURST_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                       MK_ENUM_CONST(3)
+
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                      22:20
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_MSB                        MK_SHIFT_CONST(22)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                   MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                   MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                  MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                  MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                      MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                      19:17
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_MSB                        MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_LSB                        MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                   MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                   MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                  MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                  MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_RANGE                   16:16
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_MSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_PROT_SHIFT                    MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_PROT_FIELD                    MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_PROT_RANGE                    15:14
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_PROT_MSB                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_PROT_LSB                      MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_PROT_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_PROT_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_PROT_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_PROT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID1_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID1_FIELD                  MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID1_RANGE                  13:7
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID1_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID1_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID1_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID1_DEFAULT_MASK                   MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID0_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID0_FIELD                  MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID0_RANGE                  6:0
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID0_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID0_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID0_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID0_DEFAULT_MASK                   MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0                        MK_ADDR_CONST(0x6001c)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_SECURE                         0x0
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_DUAL                   0x0
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_SCR                    SCR_CH5_0
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_WORD_COUNT                     0x1
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_RESET_VAL                      MK_MASK_CONST(0x2381007f)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_RESET_MASK                     MK_MASK_CONST(0xffff01ff)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_READ_MASK                      MK_MASK_CONST(0xffff01ff)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_WRITE_MASK                     MK_MASK_CONST(0xff870180)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_RANGE                  31:31
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                   30:28
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                 MK_MASK_CONST(0x2)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                    MK_ENUM_CONST(2)
+
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                   27:27
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_FIELD                       MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_RANGE                       26:23
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_MSB                 MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DEFAULT                     MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                    MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                   MK_ENUM_CONST(15)
+
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_SHIFT                   MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_RANGE                   22:19
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_MSB                     MK_SHIFT_CONST(22)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_LSB                     MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_RSVD                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_CCPLEX                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_CCPLEX_DPMU                     MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_BPMP                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_SPE                     MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_SCE                     MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_DMA_PER                 MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_TSECA                   MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_TSECB                   MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_JTAGM                   MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_CSITE                   MK_ENUM_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_MASTER_ID_APE                     MK_ENUM_CONST(11)
+
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                   18:16
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                     MK_SHIFT_CONST(18)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                  MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                  MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                  MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                 MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                 MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                 MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_SHIFT                        MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_FIELD                        MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_RANGE                        8:7
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_MSB                  MK_SHIFT_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_LSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                    6:0
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                  MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH5_BCOUNT_0
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0                  MK_ADDR_CONST(0x60020)
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_SECURE                   0x0
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_DUAL                     0x0
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_SCR                      SCR_CH5_0
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_BCOUNT_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_BCOUNT_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_BCOUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_BCOUNT_RANGE                     31:0
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_BCOUNT_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_BCOUNT_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_BCOUNT_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_BCOUNT_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_BCOUNT_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_BCOUNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_BCOUNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_BCOUNT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_BCOUNT_0_BCOUNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0                    MK_ADDR_CONST(0x60024)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_SCR                        SCR_CH5_0
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_TRANSFER_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_TRANSFER_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_TRANSFER_COUNT_RANGE                       31:0
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_TRANSFER_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_TRANSFER_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_TRANSFER_COUNT_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_TRANSFER_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_TRANSFER_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0                    MK_ADDR_CONST(0x60028)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_SCR                        SCR_CH5_0
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_DMA_COUNT_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_DMA_COUNT_FIELD                    MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_DMA_COUNT_RANGE                    31:0
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_DMA_COUNT_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_DMA_COUNT_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_DMA_COUNT_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_DMA_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_DMA_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_DMA_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_DMA_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_DMA_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x6002c
+
+// Register GPCDMA_AO_CHANNEL_CH5_ERR_STA_0
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0                 MK_ADDR_CONST(0x60030)
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_SCR                     SCR_CH5_0
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_RANGE                      31:0
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0                       MK_ADDR_CONST(0x60034)
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_SECURE                        0x0
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_DUAL                  0x0
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_SCR                   SCR_CH5_0
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH5_TZ_0
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0                      MK_ADDR_CONST(0x60038)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_SECURE                       0x0
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_DUAL                         0x0
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_SCR                  SCR_TZ_0
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_RESET_VAL                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_RESET_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_READ_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_WRITE_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MC_PROT_1_SHIFT                      MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MC_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MC_PROT_1_RANGE                      1:1
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MC_PROT_1_MSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MC_PROT_1_LSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MC_PROT_1_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MC_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MC_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MC_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MC_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MMIO_PROT_1_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MMIO_PROT_1_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH5_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MMIO_PROT_1_RANGE                    0:0
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MMIO_PROT_1_MSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MMIO_PROT_1_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MMIO_PROT_1_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MMIO_PROT_1_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MMIO_PROT_1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MMIO_PROT_1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH5_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH6_CSR_0
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0                     MK_ADDR_CONST(0x70000)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_SECURE                      0x0
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DUAL                        0x0
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_SCR                         SCR_CH6_0
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_RESET_VAL                   MK_MASK_CONST(0x8008400)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_RESET_MASK                  MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_READ_MASK                   MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_WRITE_MASK                  MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ENB_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ENB_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_CSR_0_ENB_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ENB_RANGE                   31:31
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ENB_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ENB_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ENB_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ENB_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ENB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ENB_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ENB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ENB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ENB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ENB_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ENB_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IE_EOC_SHIFT                        MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IE_EOC_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IE_EOC_RANGE                        30:30
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IE_EOC_MSB                  MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IE_EOC_LSB                  MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IE_EOC_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IE_EOC_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IE_EOC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IE_EOC_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IE_EOC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IE_EOC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IE_EOC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IE_EOC_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IE_EOC_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ONCE_SHIFT                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ONCE_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_CSR_0_ONCE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ONCE_RANGE                  27:27
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ONCE_MSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ONCE_LSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ONCE_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ONCE_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ONCE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ONCE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ONCE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ONCE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ONCE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ONCE_CYCLIC_MODE                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_ONCE_SINGLE_BLOCK                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_FC_MODE_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_FC_MODE_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH6_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_FC_MODE_RANGE                       25:24
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_FC_MODE_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_FC_MODE_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_FC_MODE_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_FC_MODE_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_FC_MODE_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_FC_MODE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_FC_MODE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_FC_MODE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_FC_MODE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_FC_MODE_NO_MMIO                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_FC_MODE_ONE_MMIO                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_FC_MODE_TWO_MMIO                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_FC_MODE_FOUR_MMIO                   MK_ENUM_CONST(3)
+
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_RANGE                      23:21
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_MSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_IO2MEM_NO_FC                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_IO2MEM_FC                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_MEM2IO_NO_FC                       MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_MEM2IO_FC                  MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_MEM2MEM                    MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_RSVD                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_DMA_MODE_FIXED_PAT                  MK_ENUM_CONST(6)
+
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_FIELD                       MK_FIELD_CONST(0x1f, GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_RANGE                       20:16
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_I2C1                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_I2C2                        MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_I2C3                        MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_SPI                 MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_UART1                       MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_UART2                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_DMIC                        MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_GTE                 MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_UART6                       MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_UART8                       MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_REQ_SEL_RSVD                        MK_ENUM_CONST(29)
+
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IRQ_MASK_SHIFT                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IRQ_MASK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IRQ_MASK_RANGE                      15:15
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IRQ_MASK_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IRQ_MASK_LSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IRQ_MASK_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IRQ_MASK_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IRQ_MASK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IRQ_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IRQ_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IRQ_MASK_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_IRQ_MASK_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_WEIGHT_SHIFT                        MK_SHIFT_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_WEIGHT_FIELD                        MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH6_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_WEIGHT_RANGE                        13:10
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_WEIGHT_MSB                  MK_SHIFT_CONST(13)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_WEIGHT_LSB                  MK_SHIFT_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_WEIGHT_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_WEIGHT_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_WEIGHT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_WEIGHT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_WEIGHT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_WEIGHT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSR_0_WEIGHT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH6_STA_0
+#define GPCDMA_AO_CHANNEL_CH6_STA_0                     MK_ADDR_CONST(0x70004)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_SECURE                      0x0
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_DUAL                        0x0
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_SCR                         SCR_CH6_0
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_RESET_MASK                  MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_READ_MASK                   MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_BSY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_BSY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_STA_0_BSY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_BSY_RANGE                   31:31
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_BSY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_BSY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_BSY_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_BSY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_BSY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_BSY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_BSY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_BSY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_BSY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_BSY_WAIT                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_BSY_ACTIVE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_ISE_EOC_SHIFT                       MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_ISE_EOC_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_ISE_EOC_RANGE                       30:30
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_ISE_EOC_MSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_ISE_EOC_LSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_ISE_EOC_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_ISE_EOC_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_ISE_EOC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_ISE_EOC_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_ISE_EOC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_ISE_EOC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_ISE_EOC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_ISE_EOC_NO_INTR                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_ISE_EOC_INTR                        MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_PING_PONG_STA_SHIFT                 MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_PING_PONG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_PING_PONG_STA_RANGE                 28:28
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_PING_PONG_STA_MSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_PING_PONG_STA_LSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_PING_PONG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_PING_PONG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_PING_PONG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_PING_PONG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_PING_PONG_STA_PING_INTR_STA                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_PING_PONG_STA_PONG_INTR_STA                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_DMA_ACTIVITY_SHIFT                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_DMA_ACTIVITY_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_DMA_ACTIVITY_RANGE                  27:27
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_DMA_ACTIVITY_MSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_DMA_ACTIVITY_LSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_DMA_ACTIVITY_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_DMA_ACTIVITY_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_DMA_ACTIVITY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_DMA_ACTIVITY_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_DMA_ACTIVITY_IDLE                   MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_DMA_ACTIVITY_BUSY                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_SHIFT                 MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_RANGE                 26:26
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_LSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_RESUME                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_PAUSE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_RX_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_RX_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_RX_RANGE                    25:25
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_RX_MSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_RX_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_RX_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_RX_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_RX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_RX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_RX_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_RX_NOT_ACTIVE                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_RX_ACTIVE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_TX_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_TX_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_TX_RANGE                    24:24
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_TX_MSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_TX_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_TX_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_TX_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_TX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_TX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_TX_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_TX_NOT_ACTIVE                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_CHANNEL_TX_ACTIVE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_IRQ_INTR_STA_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_IRQ_INTR_STA_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_IRQ_INTR_STA_RANGE                  23:23
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_IRQ_INTR_STA_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_IRQ_INTR_STA_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_IRQ_INTR_STA_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_IRQ_INTR_STA_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_IRQ_INTR_STA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_IRQ_INTR_STA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_IRQ_INTR_STA_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_IRQ_INTR_STA_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_TRIG_STA_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_TRIG_STA_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_TRIG_STA_RANGE                      21:21
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_TRIG_STA_MSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_TRIG_STA_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_TRIG_STA_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_TRIG_STA_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_TRIG_STA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_TRIG_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_TRIG_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_TRIG_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_TRIG_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_TRIG_STA_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_TRIG_STA_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_INTR_STA_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_INTR_STA_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_INTR_STA_RANGE                      20:20
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_INTR_STA_MSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_INTR_STA_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_INTR_STA_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_INTR_STA_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_INTR_STA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_INTR_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_INTR_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_INTR_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_INTR_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_INTR_STA_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_STA_0_INTR_STA_ACTIVE                     MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH6_CSRE_0
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0                    MK_ADDR_CONST(0x70008)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_SCR                        SCR_CH6_0
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_RESET_MASK                         MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_READ_MASK                  MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_WRITE_MASK                         MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_RANGE                 31:31
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_RESUME                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_PAUSE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_SHIFT                     MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_FIELD                     MK_FIELD_CONST(0x3f, GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_RANGE                     19:14
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_MSB                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_LSB                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x3f)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_SMP_24                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_SMP_25                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_SMP_26                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH0                       MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH1                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH2                       MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH3                       MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH4                       MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH5                       MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH6                       MK_ENUM_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH7                       MK_ENUM_CONST(11)
+#define GPCDMA_AO_CHANNEL_CH6_CSRE_0_TRIG_SEL_RSVD                      MK_ENUM_CONST(0)
+
+
+// Register GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0                 MK_ADDR_CONST(0x7000c)
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_SCR                     SCR_CH6_0
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH6_DST_PTR_0
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0                 MK_ADDR_CONST(0x70010)
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_SCR                     SCR_CH6_0
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_DST_PTR_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_DST_PTR_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_DST_PTR_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_DST_PTR_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_DST_PTR_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_DST_PTR_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_DST_PTR_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_DST_PTR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_DST_PTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_DST_PTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0                      MK_ADDR_CONST(0x70014)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_SECURE                       0x0
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_DUAL                         0x0
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_SCR                  SCR_CH6_0
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_RESET_MASK                   MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_READ_MASK                    MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_WRITE_MASK                   MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_FIELD                     MK_FIELD_CONST(0xff, GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_RANGE                     23:16
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                     MK_FIELD_CONST(0xff, GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                     7:0
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_MSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0                  MK_ADDR_CONST(0x70018)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_SECURE                   0x0
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_DUAL                     0x0
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_SCR                      SCR_CH6_0
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x3800000)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_SHIFT                       MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_RANGE                       31:31
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_LSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_DISABLE                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_SHIFT                 MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_FIELD                 MK_FIELD_CONST(0x3f, GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_RANGE                 30:25
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_LSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_BURST_SHIFT                   MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_BURST_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_BURST_RANGE                   24:23
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_BURST_MSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_BURST_LSB                     MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_BURST_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_BURST_DEFAULT                 MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_BURST_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_BURST_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                       MK_ENUM_CONST(3)
+
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                      22:20
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_MSB                        MK_SHIFT_CONST(22)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                   MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                   MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                  MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                  MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                      MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                      19:17
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_MSB                        MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_LSB                        MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                   MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                   MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                  MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                  MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_RANGE                   16:16
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_MSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_PROT_SHIFT                    MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_PROT_FIELD                    MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_PROT_RANGE                    15:14
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_PROT_MSB                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_PROT_LSB                      MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_PROT_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_PROT_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_PROT_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_PROT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID1_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID1_FIELD                  MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID1_RANGE                  13:7
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID1_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID1_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID1_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID1_DEFAULT_MASK                   MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID0_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID0_FIELD                  MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID0_RANGE                  6:0
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID0_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID0_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID0_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID0_DEFAULT_MASK                   MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0                        MK_ADDR_CONST(0x7001c)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_SECURE                         0x0
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_DUAL                   0x0
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_SCR                    SCR_CH6_0
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_WORD_COUNT                     0x1
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_RESET_VAL                      MK_MASK_CONST(0x2381007f)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_RESET_MASK                     MK_MASK_CONST(0xffff01ff)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_READ_MASK                      MK_MASK_CONST(0xffff01ff)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_WRITE_MASK                     MK_MASK_CONST(0xff870180)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_RANGE                  31:31
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                   30:28
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                 MK_MASK_CONST(0x2)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                    MK_ENUM_CONST(2)
+
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                   27:27
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_FIELD                       MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_RANGE                       26:23
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_MSB                 MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DEFAULT                     MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                    MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                   MK_ENUM_CONST(15)
+
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_SHIFT                   MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_RANGE                   22:19
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_MSB                     MK_SHIFT_CONST(22)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_LSB                     MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_RSVD                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_CCPLEX                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_CCPLEX_DPMU                     MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_BPMP                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_SPE                     MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_SCE                     MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_DMA_PER                 MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_TSECA                   MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_TSECB                   MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_JTAGM                   MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_CSITE                   MK_ENUM_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_MASTER_ID_APE                     MK_ENUM_CONST(11)
+
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                   18:16
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                     MK_SHIFT_CONST(18)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                  MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                  MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                  MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                 MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                 MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                 MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_SHIFT                        MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_FIELD                        MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_RANGE                        8:7
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_MSB                  MK_SHIFT_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_LSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                    6:0
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                  MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH6_BCOUNT_0
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0                  MK_ADDR_CONST(0x70020)
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_SECURE                   0x0
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_DUAL                     0x0
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_SCR                      SCR_CH6_0
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_BCOUNT_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_BCOUNT_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_BCOUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_BCOUNT_RANGE                     31:0
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_BCOUNT_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_BCOUNT_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_BCOUNT_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_BCOUNT_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_BCOUNT_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_BCOUNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_BCOUNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_BCOUNT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_BCOUNT_0_BCOUNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0                    MK_ADDR_CONST(0x70024)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_SCR                        SCR_CH6_0
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_TRANSFER_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_TRANSFER_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_TRANSFER_COUNT_RANGE                       31:0
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_TRANSFER_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_TRANSFER_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_TRANSFER_COUNT_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_TRANSFER_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_TRANSFER_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0                    MK_ADDR_CONST(0x70028)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_SCR                        SCR_CH6_0
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_DMA_COUNT_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_DMA_COUNT_FIELD                    MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_DMA_COUNT_RANGE                    31:0
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_DMA_COUNT_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_DMA_COUNT_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_DMA_COUNT_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_DMA_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_DMA_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_DMA_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_DMA_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_DMA_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x7002c
+
+// Register GPCDMA_AO_CHANNEL_CH6_ERR_STA_0
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0                 MK_ADDR_CONST(0x70030)
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_SCR                     SCR_CH6_0
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_RANGE                      31:0
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0                       MK_ADDR_CONST(0x70034)
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_SECURE                        0x0
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_DUAL                  0x0
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_SCR                   SCR_CH6_0
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH6_TZ_0
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0                      MK_ADDR_CONST(0x70038)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_SECURE                       0x0
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_DUAL                         0x0
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_SCR                  SCR_TZ_0
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_RESET_VAL                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_RESET_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_READ_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_WRITE_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MC_PROT_1_SHIFT                      MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MC_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MC_PROT_1_RANGE                      1:1
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MC_PROT_1_MSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MC_PROT_1_LSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MC_PROT_1_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MC_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MC_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MC_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MC_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MMIO_PROT_1_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MMIO_PROT_1_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH6_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MMIO_PROT_1_RANGE                    0:0
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MMIO_PROT_1_MSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MMIO_PROT_1_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MMIO_PROT_1_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MMIO_PROT_1_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MMIO_PROT_1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MMIO_PROT_1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH6_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH7_CSR_0
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0                     MK_ADDR_CONST(0x80000)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_SECURE                      0x0
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DUAL                        0x0
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_SCR                         SCR_CH7_0
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_RESET_VAL                   MK_MASK_CONST(0x8008400)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_RESET_MASK                  MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_READ_MASK                   MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_WRITE_MASK                  MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ENB_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ENB_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_CSR_0_ENB_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ENB_RANGE                   31:31
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ENB_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ENB_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ENB_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ENB_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ENB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ENB_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ENB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ENB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ENB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ENB_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ENB_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IE_EOC_SHIFT                        MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IE_EOC_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IE_EOC_RANGE                        30:30
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IE_EOC_MSB                  MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IE_EOC_LSB                  MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IE_EOC_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IE_EOC_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IE_EOC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IE_EOC_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IE_EOC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IE_EOC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IE_EOC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IE_EOC_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IE_EOC_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ONCE_SHIFT                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ONCE_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_CSR_0_ONCE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ONCE_RANGE                  27:27
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ONCE_MSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ONCE_LSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ONCE_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ONCE_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ONCE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ONCE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ONCE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ONCE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ONCE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ONCE_CYCLIC_MODE                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_ONCE_SINGLE_BLOCK                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_FC_MODE_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_FC_MODE_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH7_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_FC_MODE_RANGE                       25:24
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_FC_MODE_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_FC_MODE_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_FC_MODE_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_FC_MODE_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_FC_MODE_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_FC_MODE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_FC_MODE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_FC_MODE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_FC_MODE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_FC_MODE_NO_MMIO                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_FC_MODE_ONE_MMIO                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_FC_MODE_TWO_MMIO                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_FC_MODE_FOUR_MMIO                   MK_ENUM_CONST(3)
+
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_RANGE                      23:21
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_MSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_IO2MEM_NO_FC                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_IO2MEM_FC                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_MEM2IO_NO_FC                       MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_MEM2IO_FC                  MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_MEM2MEM                    MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_RSVD                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_DMA_MODE_FIXED_PAT                  MK_ENUM_CONST(6)
+
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_FIELD                       MK_FIELD_CONST(0x1f, GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_RANGE                       20:16
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_I2C1                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_I2C2                        MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_I2C3                        MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_SPI                 MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_UART1                       MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_UART2                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_DMIC                        MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_GTE                 MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_UART6                       MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_UART8                       MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_REQ_SEL_RSVD                        MK_ENUM_CONST(29)
+
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IRQ_MASK_SHIFT                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IRQ_MASK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IRQ_MASK_RANGE                      15:15
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IRQ_MASK_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IRQ_MASK_LSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IRQ_MASK_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IRQ_MASK_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IRQ_MASK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IRQ_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IRQ_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IRQ_MASK_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_IRQ_MASK_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_WEIGHT_SHIFT                        MK_SHIFT_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_WEIGHT_FIELD                        MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH7_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_WEIGHT_RANGE                        13:10
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_WEIGHT_MSB                  MK_SHIFT_CONST(13)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_WEIGHT_LSB                  MK_SHIFT_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_WEIGHT_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_WEIGHT_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_WEIGHT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_WEIGHT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_WEIGHT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_WEIGHT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSR_0_WEIGHT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH7_STA_0
+#define GPCDMA_AO_CHANNEL_CH7_STA_0                     MK_ADDR_CONST(0x80004)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_SECURE                      0x0
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_DUAL                        0x0
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_SCR                         SCR_CH7_0
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_WORD_COUNT                  0x1
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_RESET_MASK                  MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_READ_MASK                   MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_BSY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_BSY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_STA_0_BSY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_BSY_RANGE                   31:31
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_BSY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_BSY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_BSY_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_BSY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_BSY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_BSY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_BSY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_BSY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_BSY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_BSY_WAIT                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_BSY_ACTIVE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_ISE_EOC_SHIFT                       MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_ISE_EOC_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_ISE_EOC_RANGE                       30:30
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_ISE_EOC_MSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_ISE_EOC_LSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_ISE_EOC_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_ISE_EOC_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_ISE_EOC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_ISE_EOC_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_ISE_EOC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_ISE_EOC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_ISE_EOC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_ISE_EOC_NO_INTR                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_ISE_EOC_INTR                        MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_PING_PONG_STA_SHIFT                 MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_PING_PONG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_PING_PONG_STA_RANGE                 28:28
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_PING_PONG_STA_MSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_PING_PONG_STA_LSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_PING_PONG_STA_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_PING_PONG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_PING_PONG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_PING_PONG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_PING_PONG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_PING_PONG_STA_PING_INTR_STA                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_PING_PONG_STA_PONG_INTR_STA                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_DMA_ACTIVITY_SHIFT                  MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_DMA_ACTIVITY_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_DMA_ACTIVITY_RANGE                  27:27
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_DMA_ACTIVITY_MSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_DMA_ACTIVITY_LSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_DMA_ACTIVITY_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_DMA_ACTIVITY_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_DMA_ACTIVITY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_DMA_ACTIVITY_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_DMA_ACTIVITY_IDLE                   MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_DMA_ACTIVITY_BUSY                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_SHIFT                 MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_RANGE                 26:26
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_LSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_RESUME                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_PAUSE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_RX_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_RX_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_RX_RANGE                    25:25
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_RX_MSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_RX_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_RX_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_RX_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_RX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_RX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_RX_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_RX_NOT_ACTIVE                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_RX_ACTIVE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_TX_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_TX_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_TX_RANGE                    24:24
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_TX_MSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_TX_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_TX_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_TX_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_TX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_TX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_TX_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_TX_NOT_ACTIVE                       MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_CHANNEL_TX_ACTIVE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_IRQ_INTR_STA_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_IRQ_INTR_STA_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_IRQ_INTR_STA_RANGE                  23:23
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_IRQ_INTR_STA_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_IRQ_INTR_STA_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_IRQ_INTR_STA_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_IRQ_INTR_STA_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_IRQ_INTR_STA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_IRQ_INTR_STA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_IRQ_INTR_STA_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_IRQ_INTR_STA_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_TRIG_STA_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_TRIG_STA_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_TRIG_STA_RANGE                      21:21
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_TRIG_STA_MSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_TRIG_STA_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_TRIG_STA_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_TRIG_STA_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_TRIG_STA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_TRIG_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_TRIG_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_TRIG_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_TRIG_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_TRIG_STA_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_TRIG_STA_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_INTR_STA_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_INTR_STA_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_INTR_STA_RANGE                      20:20
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_INTR_STA_MSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_INTR_STA_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_INTR_STA_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_INTR_STA_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_INTR_STA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_INTR_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_INTR_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_INTR_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_INTR_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_INTR_STA_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_STA_0_INTR_STA_ACTIVE                     MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH7_CSRE_0
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0                    MK_ADDR_CONST(0x80008)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_SCR                        SCR_CH7_0
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_RESET_MASK                         MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_READ_MASK                  MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_WRITE_MASK                         MK_MASK_CONST(0x800fc000)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_RANGE                 31:31
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_RESUME                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_PAUSE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_SHIFT                     MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_FIELD                     MK_FIELD_CONST(0x3f, GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_RANGE                     19:14
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_MSB                       MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_LSB                       MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x3f)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_SMP_24                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_SMP_25                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_SMP_26                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH0                       MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH1                       MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH2                       MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH3                       MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH4                       MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH5                       MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH6                       MK_ENUM_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH7                       MK_ENUM_CONST(11)
+#define GPCDMA_AO_CHANNEL_CH7_CSRE_0_TRIG_SEL_RSVD                      MK_ENUM_CONST(0)
+
+
+// Register GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0                 MK_ADDR_CONST(0x8000c)
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_SCR                     SCR_CH7_0
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH7_DST_PTR_0
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0                 MK_ADDR_CONST(0x80010)
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_SCR                     SCR_CH7_0
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_DST_PTR_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_DST_PTR_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_DST_PTR_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_DST_PTR_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_DST_PTR_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_DST_PTR_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_DST_PTR_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_DST_PTR_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_DST_PTR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_DST_PTR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0                      MK_ADDR_CONST(0x80014)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_SECURE                       0x0
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_DUAL                         0x0
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_SCR                  SCR_CH7_0
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_RESET_MASK                   MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_READ_MASK                    MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_WRITE_MASK                   MK_MASK_CONST(0xff00ff)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_FIELD                     MK_FIELD_CONST(0xff, GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_RANGE                     23:16
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                     MK_FIELD_CONST(0xff, GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                     7:0
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_MSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0                  MK_ADDR_CONST(0x80018)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_SECURE                   0x0
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_DUAL                     0x0
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_SCR                      SCR_CH7_0
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x3800000)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_SHIFT                       MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_RANGE                       31:31
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_LSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_DISABLE                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_SHIFT                 MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_FIELD                 MK_FIELD_CONST(0x3f, GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_RANGE                 30:25
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_LSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_WOFFSET                       0x0
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_BURST_SHIFT                   MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_BURST_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_BURST_RANGE                   24:23
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_BURST_MSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_BURST_LSB                     MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_BURST_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_BURST_DEFAULT                 MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_BURST_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_BURST_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                       MK_ENUM_CONST(3)
+
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                      22:20
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_MSB                        MK_SHIFT_CONST(22)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                   MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                   MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                  MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                  MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                      MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                      19:17
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_MSB                        MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_LSB                        MK_SHIFT_CONST(17)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                   MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                   MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                  MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                  MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_RANGE                   16:16
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_MSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_PROT_SHIFT                    MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_PROT_FIELD                    MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_PROT_RANGE                    15:14
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_PROT_MSB                      MK_SHIFT_CONST(15)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_PROT_LSB                      MK_SHIFT_CONST(14)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_PROT_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_PROT_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_PROT_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_PROT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID1_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID1_FIELD                  MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID1_RANGE                  13:7
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID1_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID1_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID1_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID1_DEFAULT_MASK                   MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID0_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID0_FIELD                  MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID0_RANGE                  6:0
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID0_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID0_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID0_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID0_DEFAULT_MASK                   MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0                        MK_ADDR_CONST(0x8001c)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_SECURE                         0x0
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_DUAL                   0x0
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_SCR                    SCR_CH7_0
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_WORD_COUNT                     0x1
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_RESET_VAL                      MK_MASK_CONST(0x2381007f)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_RESET_MASK                     MK_MASK_CONST(0xffff01ff)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_READ_MASK                      MK_MASK_CONST(0xffff01ff)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_WRITE_MASK                     MK_MASK_CONST(0xff870180)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_RANGE                  31:31
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_WOFFSET                        0x0
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                   30:28
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                 MK_MASK_CONST(0x2)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                     MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                    MK_ENUM_CONST(2)
+
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                   27:27
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_FIELD                       MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_RANGE                       26:23
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_MSB                 MK_SHIFT_CONST(26)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DEFAULT                     MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                    MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                   MK_ENUM_CONST(15)
+
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_SHIFT                   MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_RANGE                   22:19
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_MSB                     MK_SHIFT_CONST(22)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_LSB                     MK_SHIFT_CONST(19)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_RSVD                    MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_CCPLEX                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_CCPLEX_DPMU                     MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_BPMP                    MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_SPE                     MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_SCE                     MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_DMA_PER                 MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_TSECA                   MK_ENUM_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_TSECB                   MK_ENUM_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_JTAGM                   MK_ENUM_CONST(9)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_CSITE                   MK_ENUM_CONST(10)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_MASTER_ID_APE                     MK_ENUM_CONST(11)
+
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                   18:16
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                     MK_SHIFT_CONST(18)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                 MK_ENUM_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                  MK_ENUM_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                  MK_ENUM_CONST(2)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                  MK_ENUM_CONST(3)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                  MK_ENUM_CONST(4)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                 MK_ENUM_CONST(5)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                 MK_ENUM_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                 MK_ENUM_CONST(7)
+
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_SHIFT                        MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_FIELD                        MK_FIELD_CONST(0x3, GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_RANGE                        8:7
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_MSB                  MK_SHIFT_CONST(8)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_LSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_WOFFSET                      0x0
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                    6:0
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                  MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH7_BCOUNT_0
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0                  MK_ADDR_CONST(0x80020)
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_SECURE                   0x0
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_DUAL                     0x0
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_SCR                      SCR_CH7_0
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_WORD_COUNT                       0x1
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_BCOUNT_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_BCOUNT_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_BCOUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_BCOUNT_RANGE                     31:0
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_BCOUNT_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_BCOUNT_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_BCOUNT_WOFFSET                   0x0
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_BCOUNT_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_BCOUNT_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_BCOUNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_BCOUNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_BCOUNT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_BCOUNT_0_BCOUNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0                    MK_ADDR_CONST(0x80024)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_SCR                        SCR_CH7_0
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_TRANSFER_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_TRANSFER_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_TRANSFER_COUNT_RANGE                       31:0
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_TRANSFER_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_TRANSFER_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_TRANSFER_COUNT_WOFFSET                     0x0
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_TRANSFER_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_TRANSFER_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0                    MK_ADDR_CONST(0x80028)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_SECURE                     0x0
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_DUAL                       0x0
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_SCR                        SCR_CH7_0
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_DMA_COUNT_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_DMA_COUNT_FIELD                    MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_DMA_COUNT_RANGE                    31:0
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_DMA_COUNT_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_DMA_COUNT_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_DMA_COUNT_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_DMA_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_DMA_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_DMA_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_DMA_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_DMA_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x8002c
+
+// Register GPCDMA_AO_CHANNEL_CH7_ERR_STA_0
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0                 MK_ADDR_CONST(0x80030)
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_SECURE                  0x0
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_DUAL                    0x0
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_SCR                     SCR_CH7_0
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_WORD_COUNT                      0x1
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_RANGE                      31:0
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0                       MK_ADDR_CONST(0x80034)
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_SECURE                        0x0
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_DUAL                  0x0
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_SCR                   SCR_CH7_0
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_WORD_COUNT                    0x1
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_RANGE                   31:0
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                 0x0
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_AO_CHANNEL_CH7_TZ_0
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0                      MK_ADDR_CONST(0x80038)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_SECURE                       0x0
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_DUAL                         0x0
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_SCR                  SCR_TZ_0
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_WORD_COUNT                   0x1
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_RESET_VAL                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_RESET_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_READ_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_WRITE_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MC_PROT_1_SHIFT                      MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MC_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MC_PROT_1_RANGE                      1:1
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MC_PROT_1_MSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MC_PROT_1_LSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MC_PROT_1_WOFFSET                    0x0
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MC_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MC_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MC_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MC_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MMIO_PROT_1_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MMIO_PROT_1_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_AO_CHANNEL_CH7_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MMIO_PROT_1_RANGE                    0:0
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MMIO_PROT_1_MSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MMIO_PROT_1_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MMIO_PROT_1_WOFFSET                  0x0
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MMIO_PROT_1_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MMIO_PROT_1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MMIO_PROT_1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_AO_CHANNEL_CH7_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARGPCDMA_AO_REGS(_op_) \
+_op_(GPCDMA_AO_COMMON_DMA_CHAN_STA_0) \
+_op_(GPCDMA_AO_COMMON_REQUESTORS_TX_0) \
+_op_(GPCDMA_AO_COMMON_REQUESTORS_RX_0) \
+_op_(GPCDMA_AO_COMMON_COMMON_ERROR_STA_0) \
+_op_(GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0) \
+_op_(GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0) \
+_op_(GPCDMA_AO_COMMON_MASKED_INTR_REG_0) \
+_op_(GPCDMA_AO_COMMON_CHANNEL_INTR_STA_0) \
+_op_(GPCDMA_AO_COMMON_COMMON_INTR_0) \
+_op_(GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0) \
+_op_(GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH1_PERI_ID_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH2_PERI_ID_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH3_PERI_ID_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH4_PERI_ID_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH5_PERI_ID_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH6_PERI_ID_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0) \
+_op_(GPCDMA_AO_COMMON_PER0_PERI_ADDR_0) \
+_op_(GPCDMA_AO_COMMON_PER1_PERI_ADDR_0) \
+_op_(GPCDMA_AO_COMMON_PER2_PERI_ADDR_0) \
+_op_(GPCDMA_AO_COMMON_PER3_PERI_ADDR_0) \
+_op_(GPCDMA_AO_COMMON_PER4_PERI_ADDR_0) \
+_op_(GPCDMA_AO_COMMON_PER5_PERI_ADDR_0) \
+_op_(GPCDMA_AO_COMMON_PER6_PERI_ADDR_0) \
+_op_(GPCDMA_AO_COMMON_PER7_PERI_ADDR_0) \
+_op_(GPCDMA_AO_COMMON_PER8_PERI_ADDR_0) \
+_op_(GPCDMA_AO_COMMON_PER9_PERI_ADDR_0) \
+_op_(GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH1_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH2_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH3_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH4_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH5_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH6_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH1_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH2_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH3_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH4_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH5_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH6_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH1_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH2_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH3_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH4_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH5_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH6_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH1_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH2_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH3_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH4_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH5_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH6_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0) \
+_op_(GPCDMA_AO_COMMON_DMA_ICG_EN_OVERRIDE_0) \
+_op_(GPCDMA_AO_COMMON_DMA_ACTIVE_0) \
+_op_(GPCDMA_AO_SCR_SCR_CH0_0) \
+_op_(GPCDMA_AO_SCR_SCR_CH1_0) \
+_op_(GPCDMA_AO_SCR_SCR_CH2_0) \
+_op_(GPCDMA_AO_SCR_SCR_CH3_0) \
+_op_(GPCDMA_AO_SCR_SCR_CH4_0) \
+_op_(GPCDMA_AO_SCR_SCR_CH5_0) \
+_op_(GPCDMA_AO_SCR_SCR_CH6_0) \
+_op_(GPCDMA_AO_SCR_SCR_CH7_0) \
+_op_(GPCDMA_AO_SCR_SCR_TZ_0) \
+_op_(GPCDMA_AO_SCR_SCR_DMA_RO_0) \
+_op_(GPCDMA_AO_SCR_SCR_HYPER_0) \
+_op_(GPCDMA_AO_CHANNEL_CH0_CSR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH0_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH0_CSRE_0) \
+_op_(GPCDMA_AO_CHANNEL_CH0_SRC_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH0_DST_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH0_HI_ADR_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH0_MC_SEQ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH0_MMIO_SEQ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH0_BCOUNT_0) \
+_op_(GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_TRA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH0_ERR_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH0_FIXED_PAT_0) \
+_op_(GPCDMA_AO_CHANNEL_CH0_TZ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH1_CSR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH1_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH1_CSRE_0) \
+_op_(GPCDMA_AO_CHANNEL_CH1_SRC_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH1_DST_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH1_HI_ADR_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH1_MC_SEQ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH1_MMIO_SEQ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH1_BCOUNT_0) \
+_op_(GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_TRA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH1_ERR_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH1_FIXED_PAT_0) \
+_op_(GPCDMA_AO_CHANNEL_CH1_TZ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH2_CSR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH2_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH2_CSRE_0) \
+_op_(GPCDMA_AO_CHANNEL_CH2_SRC_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH2_DST_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH2_HI_ADR_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH2_MC_SEQ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH2_MMIO_SEQ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH2_BCOUNT_0) \
+_op_(GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_TRA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH2_ERR_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH2_FIXED_PAT_0) \
+_op_(GPCDMA_AO_CHANNEL_CH2_TZ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH3_CSR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH3_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH3_CSRE_0) \
+_op_(GPCDMA_AO_CHANNEL_CH3_SRC_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH3_DST_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH3_HI_ADR_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH3_MC_SEQ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH3_MMIO_SEQ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH3_BCOUNT_0) \
+_op_(GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_TRA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH3_ERR_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH3_FIXED_PAT_0) \
+_op_(GPCDMA_AO_CHANNEL_CH3_TZ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH4_CSR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH4_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH4_CSRE_0) \
+_op_(GPCDMA_AO_CHANNEL_CH4_SRC_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH4_DST_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH4_HI_ADR_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH4_MC_SEQ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH4_MMIO_SEQ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH4_BCOUNT_0) \
+_op_(GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_TRA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH4_ERR_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH4_FIXED_PAT_0) \
+_op_(GPCDMA_AO_CHANNEL_CH4_TZ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH4_SPARE_0) \
+_op_(GPCDMA_AO_CHANNEL_CH5_CSR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH5_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH5_CSRE_0) \
+_op_(GPCDMA_AO_CHANNEL_CH5_SRC_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH5_DST_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH5_HI_ADR_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH5_MC_SEQ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH5_MMIO_SEQ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH5_BCOUNT_0) \
+_op_(GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_TRA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH5_ERR_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH5_FIXED_PAT_0) \
+_op_(GPCDMA_AO_CHANNEL_CH5_TZ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH6_CSR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH6_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH6_CSRE_0) \
+_op_(GPCDMA_AO_CHANNEL_CH6_SRC_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH6_DST_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH6_HI_ADR_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH6_MC_SEQ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH6_MMIO_SEQ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH6_BCOUNT_0) \
+_op_(GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_TRA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH6_ERR_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH6_FIXED_PAT_0) \
+_op_(GPCDMA_AO_CHANNEL_CH6_TZ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH7_CSR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH7_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH7_CSRE_0) \
+_op_(GPCDMA_AO_CHANNEL_CH7_SRC_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH7_DST_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH7_HI_ADR_PTR_0) \
+_op_(GPCDMA_AO_CHANNEL_CH7_MC_SEQ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH7_MMIO_SEQ_0) \
+_op_(GPCDMA_AO_CHANNEL_CH7_BCOUNT_0) \
+_op_(GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_TRA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH7_ERR_STA_0) \
+_op_(GPCDMA_AO_CHANNEL_CH7_FIXED_PAT_0) \
+_op_(GPCDMA_AO_CHANNEL_CH7_TZ_0) \
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_GPCDMA_AO_COMMON   0x00000000
+#define BASE_ADDRESS_GPCDMA_AO_SCR      0x00000f00
+#define BASE_ADDRESS_GPCDMA_AO_CHANNEL  0x00010000
+
+//
+// ARGPCDMA_AO REGISTER BANKS
+//
+
+#define GPCDMA_AO_COMMON0_FIRST_REG 0x0000 // GPCDMA_AO_COMMON_DMA_CHAN_STA_0
+#define GPCDMA_AO_COMMON0_LAST_REG 0x0010 // GPCDMA_AO_COMMON_CHANNEL_ERROR_STA_0
+#define GPCDMA_AO_COMMON1_FIRST_REG 0x0018 // GPCDMA_AO_COMMON_CHANNEL_TRIG_REG_0
+#define GPCDMA_AO_COMMON1_LAST_REG 0x0028 // GPCDMA_AO_COMMON_CHANNEL_REG_LOCK_0
+#define GPCDMA_AO_COMMON2_FIRST_REG 0x0080 // GPCDMA_AO_COMMON_CH0_PERI_ID_MASK_0
+#define GPCDMA_AO_COMMON2_LAST_REG 0x009c // GPCDMA_AO_COMMON_CH7_PERI_ID_MASK_0
+#define GPCDMA_AO_COMMON3_FIRST_REG 0x0100 // GPCDMA_AO_COMMON_PER0_PERI_ADDR_0
+#define GPCDMA_AO_COMMON3_LAST_REG 0x0124 // GPCDMA_AO_COMMON_PER9_PERI_ADDR_0
+#define GPCDMA_AO_COMMON4_FIRST_REG 0x0180 // GPCDMA_AO_COMMON_CH0_STREAM_ID0_MASK_0
+#define GPCDMA_AO_COMMON4_LAST_REG 0x019c // GPCDMA_AO_COMMON_CH7_STREAM_ID0_MASK_0
+#define GPCDMA_AO_COMMON5_FIRST_REG 0x0200 // GPCDMA_AO_COMMON_CH0_STREAM_ID1_MASK_0
+#define GPCDMA_AO_COMMON5_LAST_REG 0x021c // GPCDMA_AO_COMMON_CH7_STREAM_ID1_MASK_0
+#define GPCDMA_AO_COMMON6_FIRST_REG 0x0280 // GPCDMA_AO_COMMON_CH0_STREAM_ID2_MASK_0
+#define GPCDMA_AO_COMMON6_LAST_REG 0x029c // GPCDMA_AO_COMMON_CH7_STREAM_ID2_MASK_0
+#define GPCDMA_AO_COMMON7_FIRST_REG 0x0300 // GPCDMA_AO_COMMON_CH0_STREAM_ID3_MASK_0
+#define GPCDMA_AO_COMMON7_LAST_REG 0x031c // GPCDMA_AO_COMMON_CH7_STREAM_ID3_MASK_0
+#define GPCDMA_AO_COMMON8_FIRST_REG 0x0380 // GPCDMA_AO_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0
+#define GPCDMA_AO_COMMON8_LAST_REG 0x038c // GPCDMA_AO_COMMON_COMMON_SPARE_0
+#define GPCDMA_AO_SCR0_FIRST_REG 0x0f00 // GPCDMA_AO_SCR_SCR_CH0_0
+#define GPCDMA_AO_SCR0_LAST_REG 0x0f1c // GPCDMA_AO_SCR_SCR_CH7_0
+#define GPCDMA_AO_SCR1_FIRST_REG 0x0f80 // GPCDMA_AO_SCR_SCR_TZ_0
+#define GPCDMA_AO_SCR1_LAST_REG 0x0f88 // GPCDMA_AO_SCR_SCR_HYPER_0
+#define GPCDMA_AO_CHANNEL0_FIRST_REG 0x10000 // GPCDMA_AO_CHANNEL_CH0_CSR_0
+#define GPCDMA_AO_CHANNEL0_LAST_REG 0x10028 // GPCDMA_AO_CHANNEL_CH0_DMA_BYTE_STA_0
+#define GPCDMA_AO_CHANNEL1_FIRST_REG 0x10030 // GPCDMA_AO_CHANNEL_CH0_ERR_STA_0
+#define GPCDMA_AO_CHANNEL1_LAST_REG 0x10040 // GPCDMA_AO_CHANNEL_CH0_SPARE_0
+#define GPCDMA_AO_CHANNEL2_FIRST_REG 0x20000 // GPCDMA_AO_CHANNEL_CH1_CSR_0
+#define GPCDMA_AO_CHANNEL2_LAST_REG 0x20028 // GPCDMA_AO_CHANNEL_CH1_DMA_BYTE_STA_0
+#define GPCDMA_AO_CHANNEL3_FIRST_REG 0x20030 // GPCDMA_AO_CHANNEL_CH1_ERR_STA_0
+#define GPCDMA_AO_CHANNEL3_LAST_REG 0x20040 // GPCDMA_AO_CHANNEL_CH1_SPARE_0
+#define GPCDMA_AO_CHANNEL4_FIRST_REG 0x30000 // GPCDMA_AO_CHANNEL_CH2_CSR_0
+#define GPCDMA_AO_CHANNEL4_LAST_REG 0x30028 // GPCDMA_AO_CHANNEL_CH2_DMA_BYTE_STA_0
+#define GPCDMA_AO_CHANNEL5_FIRST_REG 0x30030 // GPCDMA_AO_CHANNEL_CH2_ERR_STA_0
+#define GPCDMA_AO_CHANNEL5_LAST_REG 0x30040 // GPCDMA_AO_CHANNEL_CH2_SPARE_0
+#define GPCDMA_AO_CHANNEL6_FIRST_REG 0x40000 // GPCDMA_AO_CHANNEL_CH3_CSR_0
+#define GPCDMA_AO_CHANNEL6_LAST_REG 0x40028 // GPCDMA_AO_CHANNEL_CH3_DMA_BYTE_STA_0
+#define GPCDMA_AO_CHANNEL7_FIRST_REG 0x40030 // GPCDMA_AO_CHANNEL_CH3_ERR_STA_0
+#define GPCDMA_AO_CHANNEL7_LAST_REG 0x40040 // GPCDMA_AO_CHANNEL_CH3_SPARE_0
+#define GPCDMA_AO_CHANNEL8_FIRST_REG 0x50000 // GPCDMA_AO_CHANNEL_CH4_CSR_0
+#define GPCDMA_AO_CHANNEL8_LAST_REG 0x50028 // GPCDMA_AO_CHANNEL_CH4_DMA_BYTE_STA_0
+#define GPCDMA_AO_CHANNEL9_FIRST_REG 0x50030 // GPCDMA_AO_CHANNEL_CH4_ERR_STA_0
+#define GPCDMA_AO_CHANNEL9_LAST_REG 0x50040 // GPCDMA_AO_CHANNEL_CH4_SPARE_0
+#define GPCDMA_AO_CHANNEL10_FIRST_REG 0x60000 // GPCDMA_AO_CHANNEL_CH5_CSR_0
+#define GPCDMA_AO_CHANNEL10_LAST_REG 0x60028 // GPCDMA_AO_CHANNEL_CH5_DMA_BYTE_STA_0
+#define GPCDMA_AO_CHANNEL11_FIRST_REG 0x60030 // GPCDMA_AO_CHANNEL_CH5_ERR_STA_0
+#define GPCDMA_AO_CHANNEL11_LAST_REG 0x60040 // GPCDMA_AO_CHANNEL_CH5_SPARE_0
+#define GPCDMA_AO_CHANNEL12_FIRST_REG 0x70000 // GPCDMA_AO_CHANNEL_CH6_CSR_0
+#define GPCDMA_AO_CHANNEL12_LAST_REG 0x70028 // GPCDMA_AO_CHANNEL_CH6_DMA_BYTE_STA_0
+#define GPCDMA_AO_CHANNEL13_FIRST_REG 0x70030 // GPCDMA_AO_CHANNEL_CH6_ERR_STA_0
+#define GPCDMA_AO_CHANNEL13_LAST_REG 0x70040 // GPCDMA_AO_CHANNEL_CH6_SPARE_0
+#define GPCDMA_AO_CHANNEL14_FIRST_REG 0x80000 // GPCDMA_AO_CHANNEL_CH7_CSR_0
+#define GPCDMA_AO_CHANNEL14_LAST_REG 0x80028 // GPCDMA_AO_CHANNEL_CH7_DMA_BYTE_STA_0
+#define GPCDMA_AO_CHANNEL15_FIRST_REG 0x80030 // GPCDMA_AO_CHANNEL_CH7_ERR_STA_0
+#define GPCDMA_AO_CHANNEL15_LAST_REG 0x80040 // GPCDMA_AO_CHANNEL_CH7_SPARE_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARGPCDMA_AO_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argpcdma_flv_32ch.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argpcdma_flv_32ch.h
new file mode 100644
index 0000000..65b796d
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argpcdma_flv_32ch.h
@@ -0,0 +1,56261 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARGPCDMA_FLV_32CH_H_INC
+#define ARGPCDMA_FLV_32CH_H_INC
+#define NV_MOBILE_ARGPCDMA_FLV_32CH_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARGPCDMA_FLV_32CH_H_SCRREG_NOMENCLATURE EXACT
+
+
+// Register GPCDMA_COMMON_DMA_CHAN_STA_0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0                    MK_ADDR_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_SECURE                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_DUAL                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_SCR                        SCR_DMA_RO_0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_SCRREG                     GPCDMA_SCR_SCR_DMA_RO_0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH0_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH0_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH0_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH0_RANGE                  0:0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH0_MSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH0_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH0_WOFFSET                        0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH1_SHIFT                  MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH1_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH1_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH1_RANGE                  1:1
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH1_MSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH1_LSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH1_WOFFSET                        0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH2_SHIFT                  MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH2_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH2_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH2_RANGE                  2:2
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH2_MSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH2_LSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH2_WOFFSET                        0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH2_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH2_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH2_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH3_SHIFT                  MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH3_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH3_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH3_RANGE                  3:3
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH3_MSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH3_LSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH3_WOFFSET                        0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH3_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH3_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH3_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH4_SHIFT                  MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH4_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH4_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH4_RANGE                  4:4
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH4_MSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH4_LSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH4_WOFFSET                        0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH4_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH4_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH4_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH5_SHIFT                  MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH5_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH5_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH5_RANGE                  5:5
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH5_MSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH5_LSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH5_WOFFSET                        0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH5_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH5_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH5_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH6_SHIFT                  MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH6_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH6_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH6_RANGE                  6:6
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH6_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH6_LSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH6_WOFFSET                        0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH6_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH6_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH6_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH7_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH7_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH7_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH7_RANGE                  7:7
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH7_MSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH7_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH7_WOFFSET                        0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH7_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH7_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH7_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH8_SHIFT                  MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH8_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH8_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH8_RANGE                  8:8
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH8_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH8_LSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH8_WOFFSET                        0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH8_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH8_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH8_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH8_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH8_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH8_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH9_SHIFT                  MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH9_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH9_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH9_RANGE                  9:9
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH9_MSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH9_LSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH9_WOFFSET                        0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH9_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH9_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH9_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH9_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH9_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH9_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH10_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH10_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH10_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH10_RANGE                 10:10
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH10_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH10_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH10_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH10_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH10_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH10_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH10_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH10_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH10_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH11_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH11_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH11_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH11_RANGE                 11:11
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH11_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH11_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH11_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH11_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH11_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH11_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH11_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH11_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH11_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH12_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH12_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH12_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH12_RANGE                 12:12
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH12_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH12_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH12_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH12_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH12_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH12_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH12_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH12_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH12_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH13_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH13_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH13_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH13_RANGE                 13:13
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH13_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH13_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH13_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH13_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH13_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH13_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH13_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH13_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH13_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH14_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH14_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH14_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH14_RANGE                 14:14
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH14_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH14_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH14_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH14_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH14_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH14_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH14_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH14_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH14_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH15_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH15_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH15_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH15_RANGE                 15:15
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH15_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH15_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH15_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH15_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH15_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH15_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH15_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH15_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH15_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH16_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH16_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH16_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH16_RANGE                 16:16
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH16_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH16_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH16_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH16_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH16_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH16_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH16_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH16_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH16_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH17_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH17_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH17_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH17_RANGE                 17:17
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH17_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH17_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH17_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH17_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH17_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH17_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH17_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH17_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH17_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH18_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH18_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH18_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH18_RANGE                 18:18
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH18_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH18_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH18_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH18_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH18_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH18_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH18_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH18_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH18_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH19_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH19_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH19_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH19_RANGE                 19:19
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH19_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH19_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH19_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH19_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH19_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH19_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH19_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH19_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH19_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH20_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH20_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH20_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH20_RANGE                 20:20
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH20_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH20_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH20_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH20_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH20_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH20_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH20_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH20_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH20_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH21_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH21_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH21_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH21_RANGE                 21:21
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH21_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH21_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH21_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH21_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH21_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH21_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH21_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH21_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH21_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH22_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH22_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH22_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH22_RANGE                 22:22
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH22_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH22_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH22_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH22_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH22_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH22_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH22_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH22_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH22_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH23_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH23_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH23_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH23_RANGE                 23:23
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH23_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH23_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH23_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH23_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH23_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH23_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH23_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH23_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH23_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH24_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH24_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH24_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH24_RANGE                 24:24
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH24_MSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH24_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH24_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH24_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH24_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH24_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH24_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH24_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH24_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH25_SHIFT                 MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH25_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH25_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH25_RANGE                 25:25
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH25_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH25_LSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH25_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH25_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH25_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH25_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH25_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH25_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH25_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH26_SHIFT                 MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH26_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH26_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH26_RANGE                 26:26
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH26_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH26_LSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH26_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH26_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH26_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH26_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH26_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH26_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH26_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH27_SHIFT                 MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH27_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH27_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH27_RANGE                 27:27
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH27_MSB                   MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH27_LSB                   MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH27_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH27_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH27_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH27_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH27_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH27_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH27_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH28_SHIFT                 MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH28_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH28_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH28_RANGE                 28:28
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH28_MSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH28_LSB                   MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH28_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH28_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH28_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH28_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH28_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH28_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH28_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH29_SHIFT                 MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH29_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH29_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH29_RANGE                 29:29
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH29_MSB                   MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH29_LSB                   MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH29_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH29_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH29_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH29_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH29_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH29_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH29_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH30_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH30_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH30_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH30_RANGE                 30:30
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH30_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH30_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH30_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH30_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH30_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH30_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH30_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH30_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH30_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH31_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH31_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_STA_0_CH31_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH31_RANGE                 31:31
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH31_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH31_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH31_WOFFSET                       0x0
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH31_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH31_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH31_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH31_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH31_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_STA_0_CH31_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_REQUESTORS_TX_0
+#define GPCDMA_COMMON_REQUESTORS_TX_0                   MK_ADDR_CONST(0x4)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_SECURE                    0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_DUAL                      0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_SCR                       SCR_DMA_RO_0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_SCRREG                    GPCDMA_SCR_SCR_DMA_RO_0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_WORD_COUNT                        0x1
+#define GPCDMA_COMMON_REQUESTORS_TX_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_0_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_0_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_0_RANGE                    0:0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_0_MSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_0_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_1_SHIFT                    MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_1_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_1_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_1_RANGE                    1:1
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_1_MSB                      MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_1_LSB                      MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_1_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_2_SHIFT                    MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_2_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_2_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_2_RANGE                    2:2
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_2_MSB                      MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_2_LSB                      MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_2_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_2_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_3_SHIFT                    MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_3_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_3_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_3_RANGE                    3:3
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_3_MSB                      MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_3_LSB                      MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_3_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_3_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_3_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_4_SHIFT                    MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_4_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_4_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_4_RANGE                    4:4
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_4_MSB                      MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_4_LSB                      MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_4_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_4_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_4_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_5_SHIFT                    MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_5_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_5_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_5_RANGE                    5:5
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_5_MSB                      MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_5_LSB                      MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_5_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_5_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_5_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_6_SHIFT                    MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_6_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_6_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_6_RANGE                    6:6
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_6_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_6_LSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_6_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_6_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_6_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_7_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_7_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_7_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_7_RANGE                    7:7
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_7_MSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_7_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_7_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_7_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_7_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_8_SHIFT                    MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_8_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_8_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_8_RANGE                    8:8
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_8_MSB                      MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_8_LSB                      MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_8_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_8_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_8_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_8_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_8_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_8_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_8_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_9_SHIFT                    MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_9_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_9_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_9_RANGE                    9:9
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_9_MSB                      MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_9_LSB                      MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_9_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_9_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_9_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_9_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_9_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_9_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_9_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_10_SHIFT                   MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_10_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_10_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_10_RANGE                   10:10
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_10_MSB                     MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_10_LSB                     MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_10_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_10_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_10_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_10_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_10_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_10_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_10_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_11_SHIFT                   MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_11_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_11_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_11_RANGE                   11:11
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_11_MSB                     MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_11_LSB                     MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_11_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_11_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_11_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_11_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_11_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_11_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_11_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_12_SHIFT                   MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_12_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_12_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_12_RANGE                   12:12
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_12_MSB                     MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_12_LSB                     MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_12_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_12_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_12_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_12_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_12_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_12_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_12_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_13_SHIFT                   MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_13_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_13_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_13_RANGE                   13:13
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_13_MSB                     MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_13_LSB                     MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_13_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_13_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_13_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_13_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_13_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_13_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_13_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_14_SHIFT                   MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_14_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_14_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_14_RANGE                   14:14
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_14_MSB                     MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_14_LSB                     MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_14_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_14_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_14_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_14_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_14_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_14_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_14_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_15_SHIFT                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_15_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_15_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_15_RANGE                   15:15
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_15_MSB                     MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_15_LSB                     MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_15_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_15_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_15_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_15_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_15_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_15_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_15_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_16_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_16_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_16_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_16_RANGE                   16:16
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_16_MSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_16_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_16_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_16_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_16_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_16_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_16_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_16_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_16_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_17_SHIFT                   MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_17_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_17_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_17_RANGE                   17:17
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_17_MSB                     MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_17_LSB                     MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_17_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_17_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_17_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_17_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_17_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_17_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_17_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_18_SHIFT                   MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_18_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_18_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_18_RANGE                   18:18
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_18_MSB                     MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_18_LSB                     MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_18_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_18_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_18_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_18_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_18_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_18_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_18_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_19_SHIFT                   MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_19_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_19_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_19_RANGE                   19:19
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_19_MSB                     MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_19_LSB                     MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_19_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_19_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_19_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_19_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_19_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_19_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_19_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_20_SHIFT                   MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_20_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_20_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_20_RANGE                   20:20
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_20_MSB                     MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_20_LSB                     MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_20_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_20_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_20_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_20_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_20_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_20_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_20_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_21_SHIFT                   MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_21_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_21_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_21_RANGE                   21:21
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_21_MSB                     MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_21_LSB                     MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_21_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_21_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_21_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_21_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_21_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_21_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_21_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_22_SHIFT                   MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_22_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_22_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_22_RANGE                   22:22
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_22_MSB                     MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_22_LSB                     MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_22_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_22_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_22_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_22_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_22_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_22_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_22_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_23_SHIFT                   MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_23_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_23_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_23_RANGE                   23:23
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_23_MSB                     MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_23_LSB                     MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_23_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_23_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_23_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_23_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_23_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_23_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_23_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_24_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_24_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_24_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_24_RANGE                   24:24
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_24_MSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_24_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_24_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_24_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_24_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_24_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_24_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_24_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_24_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_25_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_25_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_25_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_25_RANGE                   25:25
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_25_MSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_25_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_25_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_25_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_25_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_25_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_25_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_25_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_25_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_26_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_26_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_26_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_26_RANGE                   26:26
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_26_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_26_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_26_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_26_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_26_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_26_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_26_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_26_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_26_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_27_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_27_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_27_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_27_RANGE                   27:27
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_27_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_27_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_27_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_27_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_27_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_27_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_27_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_27_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_27_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_28_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_28_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_28_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_28_RANGE                   28:28
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_28_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_28_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_28_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_28_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_28_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_28_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_28_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_28_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_28_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_29_SHIFT                   MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_29_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_29_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_29_RANGE                   29:29
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_29_MSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_29_LSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_29_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_29_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_29_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_29_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_29_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_29_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_29_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_30_SHIFT                   MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_30_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_30_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_30_RANGE                   30:30
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_30_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_30_LSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_30_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_30_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_30_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_30_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_30_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_30_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_30_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_31_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_31_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_31_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_31_RANGE                   31:31
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_31_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_31_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_31_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_31_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_31_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_31_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_31_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_31_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_TX_0_CLIENT_31_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_REQUESTORS_RX_0
+#define GPCDMA_COMMON_REQUESTORS_RX_0                   MK_ADDR_CONST(0x8)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_SECURE                    0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_DUAL                      0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_SCR                       SCR_DMA_RO_0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_SCRREG                    GPCDMA_SCR_SCR_DMA_RO_0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_WORD_COUNT                        0x1
+#define GPCDMA_COMMON_REQUESTORS_RX_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_0_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_0_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_0_RANGE                    0:0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_0_MSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_0_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_1_SHIFT                    MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_1_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_1_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_1_RANGE                    1:1
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_1_MSB                      MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_1_LSB                      MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_1_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_2_SHIFT                    MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_2_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_2_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_2_RANGE                    2:2
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_2_MSB                      MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_2_LSB                      MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_2_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_2_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_3_SHIFT                    MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_3_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_3_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_3_RANGE                    3:3
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_3_MSB                      MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_3_LSB                      MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_3_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_3_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_3_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_4_SHIFT                    MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_4_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_4_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_4_RANGE                    4:4
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_4_MSB                      MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_4_LSB                      MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_4_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_4_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_4_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_5_SHIFT                    MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_5_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_5_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_5_RANGE                    5:5
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_5_MSB                      MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_5_LSB                      MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_5_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_5_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_5_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_6_SHIFT                    MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_6_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_6_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_6_RANGE                    6:6
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_6_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_6_LSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_6_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_6_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_6_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_7_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_7_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_7_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_7_RANGE                    7:7
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_7_MSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_7_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_7_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_7_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_7_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_8_SHIFT                    MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_8_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_8_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_8_RANGE                    8:8
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_8_MSB                      MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_8_LSB                      MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_8_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_8_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_8_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_8_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_8_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_8_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_8_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_9_SHIFT                    MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_9_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_9_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_9_RANGE                    9:9
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_9_MSB                      MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_9_LSB                      MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_9_WOFFSET                  0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_9_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_9_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_9_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_9_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_9_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_9_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_10_SHIFT                   MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_10_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_10_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_10_RANGE                   10:10
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_10_MSB                     MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_10_LSB                     MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_10_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_10_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_10_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_10_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_10_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_10_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_10_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_11_SHIFT                   MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_11_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_11_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_11_RANGE                   11:11
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_11_MSB                     MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_11_LSB                     MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_11_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_11_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_11_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_11_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_11_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_11_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_11_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_12_SHIFT                   MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_12_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_12_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_12_RANGE                   12:12
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_12_MSB                     MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_12_LSB                     MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_12_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_12_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_12_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_12_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_12_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_12_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_12_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_13_SHIFT                   MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_13_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_13_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_13_RANGE                   13:13
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_13_MSB                     MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_13_LSB                     MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_13_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_13_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_13_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_13_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_13_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_13_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_13_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_14_SHIFT                   MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_14_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_14_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_14_RANGE                   14:14
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_14_MSB                     MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_14_LSB                     MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_14_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_14_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_14_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_14_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_14_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_14_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_14_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_15_SHIFT                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_15_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_15_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_15_RANGE                   15:15
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_15_MSB                     MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_15_LSB                     MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_15_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_15_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_15_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_15_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_15_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_15_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_15_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_16_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_16_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_16_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_16_RANGE                   16:16
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_16_MSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_16_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_16_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_16_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_16_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_16_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_16_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_16_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_16_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_17_SHIFT                   MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_17_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_17_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_17_RANGE                   17:17
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_17_MSB                     MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_17_LSB                     MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_17_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_17_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_17_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_17_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_17_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_17_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_17_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_18_SHIFT                   MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_18_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_18_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_18_RANGE                   18:18
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_18_MSB                     MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_18_LSB                     MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_18_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_18_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_18_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_18_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_18_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_18_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_18_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_19_SHIFT                   MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_19_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_19_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_19_RANGE                   19:19
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_19_MSB                     MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_19_LSB                     MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_19_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_19_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_19_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_19_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_19_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_19_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_19_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_20_SHIFT                   MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_20_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_20_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_20_RANGE                   20:20
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_20_MSB                     MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_20_LSB                     MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_20_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_20_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_20_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_20_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_20_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_20_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_20_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_21_SHIFT                   MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_21_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_21_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_21_RANGE                   21:21
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_21_MSB                     MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_21_LSB                     MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_21_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_21_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_21_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_21_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_21_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_21_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_21_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_22_SHIFT                   MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_22_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_22_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_22_RANGE                   22:22
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_22_MSB                     MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_22_LSB                     MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_22_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_22_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_22_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_22_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_22_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_22_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_22_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_23_SHIFT                   MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_23_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_23_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_23_RANGE                   23:23
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_23_MSB                     MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_23_LSB                     MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_23_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_23_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_23_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_23_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_23_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_23_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_23_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_24_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_24_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_24_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_24_RANGE                   24:24
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_24_MSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_24_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_24_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_24_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_24_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_24_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_24_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_24_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_24_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_25_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_25_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_25_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_25_RANGE                   25:25
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_25_MSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_25_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_25_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_25_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_25_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_25_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_25_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_25_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_25_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_26_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_26_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_26_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_26_RANGE                   26:26
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_26_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_26_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_26_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_26_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_26_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_26_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_26_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_26_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_26_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_27_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_27_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_27_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_27_RANGE                   27:27
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_27_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_27_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_27_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_27_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_27_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_27_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_27_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_27_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_27_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_28_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_28_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_28_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_28_RANGE                   28:28
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_28_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_28_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_28_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_28_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_28_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_28_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_28_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_28_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_28_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_29_SHIFT                   MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_29_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_29_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_29_RANGE                   29:29
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_29_MSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_29_LSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_29_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_29_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_29_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_29_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_29_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_29_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_29_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_30_SHIFT                   MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_30_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_30_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_30_RANGE                   30:30
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_30_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_30_LSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_30_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_30_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_30_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_30_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_30_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_30_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_30_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_31_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_31_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_31_SHIFT)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_31_RANGE                   31:31
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_31_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_31_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_31_WOFFSET                 0x0
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_31_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_31_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_31_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_31_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_31_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_REQUESTORS_RX_0_CLIENT_31_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_COMMON_ERROR_STA_0
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0                        MK_ADDR_CONST(0xc)
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_SECURE                         0x0
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_DUAL                   0x0
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_SCR                    SCR_HYPER_0
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_SCRREG                         GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_WORD_COUNT                     0x1
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_RANGE                     31:0
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_WOFFSET                   0x0
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CHANNEL_ERROR_STA_0
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0                       MK_ADDR_CONST(0x10)
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_SECURE                        0x0
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_DUAL                  0x0
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_FIELD                    MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_RANGE                    31:0
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_WOFFSET                  0x0
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x14
+
+// Register GPCDMA_COMMON_CHANNEL_TRIG_REG_0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0                        MK_ADDR_CONST(0x18)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_SECURE                         0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_DUAL                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_SCR                    SCR_DMA_RO_0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_SCRREG                         GPCDMA_SCR_SCR_DMA_RO_0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_WORD_COUNT                     0x1
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH0_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH0_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH0_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH0_RANGE                      0:0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH0_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH0_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH0_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH1_SHIFT                      MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH1_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH1_RANGE                      1:1
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH1_MSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH1_LSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH1_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH2_SHIFT                      MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH2_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH2_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH2_RANGE                      2:2
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH2_MSB                        MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH2_LSB                        MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH2_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH3_SHIFT                      MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH3_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH3_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH3_RANGE                      3:3
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH3_MSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH3_LSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH3_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH4_SHIFT                      MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH4_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH4_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH4_RANGE                      4:4
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH4_MSB                        MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH4_LSB                        MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH4_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH5_SHIFT                      MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH5_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH5_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH5_RANGE                      5:5
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH5_MSB                        MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH5_LSB                        MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH5_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH6_SHIFT                      MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH6_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH6_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH6_RANGE                      6:6
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH6_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH6_LSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH6_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH7_SHIFT                      MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH7_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH7_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH7_RANGE                      7:7
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH7_MSB                        MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH7_LSB                        MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH7_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH8_SHIFT                      MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH8_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH8_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH8_RANGE                      8:8
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH8_MSB                        MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH8_LSB                        MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH8_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH8_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH8_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH8_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH8_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH8_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH8_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH9_SHIFT                      MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH9_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH9_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH9_RANGE                      9:9
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH9_MSB                        MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH9_LSB                        MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH9_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH9_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH9_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH9_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH9_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH9_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH9_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH10_SHIFT                     MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH10_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH10_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH10_RANGE                     10:10
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH10_MSB                       MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH10_LSB                       MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH10_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH10_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH10_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH10_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH10_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH11_SHIFT                     MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH11_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH11_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH11_RANGE                     11:11
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH11_MSB                       MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH11_LSB                       MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH11_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH11_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH11_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH11_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH11_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH12_SHIFT                     MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH12_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH12_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH12_RANGE                     12:12
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH12_MSB                       MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH12_LSB                       MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH12_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH12_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH12_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH12_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH12_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH12_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH13_SHIFT                     MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH13_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH13_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH13_RANGE                     13:13
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH13_MSB                       MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH13_LSB                       MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH13_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH13_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH13_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH13_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH13_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH13_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH13_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH14_SHIFT                     MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH14_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH14_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH14_RANGE                     14:14
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH14_MSB                       MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH14_LSB                       MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH14_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH14_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH14_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH14_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH14_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH14_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH14_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH15_SHIFT                     MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH15_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH15_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH15_RANGE                     15:15
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH15_MSB                       MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH15_LSB                       MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH15_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH15_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH15_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH15_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH15_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH15_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH15_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH16_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH16_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH16_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH16_RANGE                     16:16
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH16_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH16_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH16_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH16_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH16_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH16_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH16_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH16_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH16_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH17_SHIFT                     MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH17_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH17_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH17_RANGE                     17:17
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH17_MSB                       MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH17_LSB                       MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH17_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH17_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH17_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH17_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH17_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH17_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH17_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH18_SHIFT                     MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH18_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH18_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH18_RANGE                     18:18
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH18_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH18_LSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH18_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH18_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH18_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH18_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH18_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH18_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH18_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH19_SHIFT                     MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH19_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH19_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH19_RANGE                     19:19
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH19_MSB                       MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH19_LSB                       MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH19_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH19_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH19_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH19_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH19_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH19_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH19_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH20_SHIFT                     MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH20_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH20_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH20_RANGE                     20:20
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH20_MSB                       MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH20_LSB                       MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH20_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH20_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH20_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH20_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH20_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH20_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH20_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH21_SHIFT                     MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH21_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH21_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH21_RANGE                     21:21
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH21_MSB                       MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH21_LSB                       MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH21_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH21_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH21_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH21_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH21_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH21_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH21_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH22_SHIFT                     MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH22_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH22_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH22_RANGE                     22:22
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH22_MSB                       MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH22_LSB                       MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH22_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH22_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH22_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH22_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH22_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH22_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH22_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH23_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH23_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH23_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH23_RANGE                     23:23
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH23_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH23_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH23_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH23_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH23_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH23_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH23_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH23_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH23_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH24_SHIFT                     MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH24_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH24_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH24_RANGE                     24:24
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH24_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH24_LSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH24_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH24_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH24_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH24_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH24_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH24_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH24_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH25_SHIFT                     MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH25_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH25_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH25_RANGE                     25:25
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH25_MSB                       MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH25_LSB                       MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH25_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH25_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH25_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH25_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH25_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH25_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH25_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH26_SHIFT                     MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH26_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH26_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH26_RANGE                     26:26
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH26_MSB                       MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH26_LSB                       MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH26_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH26_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH26_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH26_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH26_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH26_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH26_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH27_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH27_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH27_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH27_RANGE                     27:27
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH27_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH27_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH27_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH27_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH27_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH27_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH27_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH27_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH27_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH28_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH28_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH28_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH28_RANGE                     28:28
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH28_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH28_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH28_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH28_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH28_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH28_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH28_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH28_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH28_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH29_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH29_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH29_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH29_RANGE                     29:29
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH29_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH29_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH29_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH29_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH29_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH29_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH29_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH29_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH29_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH30_SHIFT                     MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH30_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH30_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH30_RANGE                     30:30
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH30_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH30_LSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH30_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH30_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH30_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH30_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH30_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH30_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH30_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH31_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH31_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH31_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH31_RANGE                     31:31
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH31_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH31_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH31_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH31_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH31_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH31_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH31_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH31_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_TRIG_REG_0_CH31_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_MASKED_INTR_REG_0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0                 MK_ADDR_CONST(0x1c)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_SECURE                  0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_DUAL                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_SCR                     SCR_DMA_RO_0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_SCRREG                  GPCDMA_SCR_SCR_DMA_RO_0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_RESET_VAL                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH0_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH0_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH0_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH0_RANGE                       0:0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH0_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH0_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH0_WOFFSET                     0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH0_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH1_SHIFT                       MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH1_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH1_RANGE                       1:1
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH1_MSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH1_LSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH1_WOFFSET                     0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH1_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH2_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH2_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH2_RANGE                       2:2
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH2_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH2_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH2_WOFFSET                     0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH2_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH3_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH3_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH3_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH3_RANGE                       3:3
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH3_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH3_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH3_WOFFSET                     0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH3_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH4_SHIFT                       MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH4_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH4_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH4_RANGE                       4:4
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH4_MSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH4_LSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH4_WOFFSET                     0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH4_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH5_SHIFT                       MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH5_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH5_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH5_RANGE                       5:5
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH5_MSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH5_LSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH5_WOFFSET                     0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH5_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH6_SHIFT                       MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH6_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH6_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH6_RANGE                       6:6
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH6_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH6_LSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH6_WOFFSET                     0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH6_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH7_SHIFT                       MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH7_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH7_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH7_RANGE                       7:7
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH7_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH7_LSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH7_WOFFSET                     0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH7_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH8_SHIFT                       MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH8_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH8_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH8_RANGE                       8:8
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH8_MSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH8_LSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH8_WOFFSET                     0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH8_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH8_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH9_SHIFT                       MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH9_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH9_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH9_RANGE                       9:9
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH9_MSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH9_LSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH9_WOFFSET                     0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH9_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH9_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH9_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH9_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH9_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH9_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH10_SHIFT                      MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH10_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH10_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH10_RANGE                      10:10
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH10_MSB                        MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH10_LSB                        MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH10_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH10_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH10_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH10_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH10_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH10_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH10_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH11_SHIFT                      MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH11_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH11_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH11_RANGE                      11:11
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH11_MSB                        MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH11_LSB                        MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH11_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH11_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH11_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH11_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH11_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH11_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH11_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH12_SHIFT                      MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH12_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH12_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH12_RANGE                      12:12
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH12_MSB                        MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH12_LSB                        MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH12_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH12_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH12_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH12_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH12_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH12_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH12_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH13_SHIFT                      MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH13_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH13_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH13_RANGE                      13:13
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH13_MSB                        MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH13_LSB                        MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH13_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH13_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH13_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH13_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH13_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH13_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH13_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH14_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH14_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH14_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH14_RANGE                      14:14
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH14_MSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH14_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH14_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH14_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH14_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH14_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH14_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH14_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH14_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH15_SHIFT                      MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH15_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH15_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH15_RANGE                      15:15
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH15_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH15_LSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH15_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH15_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH15_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH15_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH15_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH15_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH15_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH16_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH16_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH16_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH16_RANGE                      16:16
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH16_MSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH16_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH16_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH16_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH16_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH16_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH16_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH16_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH16_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH17_SHIFT                      MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH17_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH17_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH17_RANGE                      17:17
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH17_MSB                        MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH17_LSB                        MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH17_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH17_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH17_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH17_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH17_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH17_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH17_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH18_SHIFT                      MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH18_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH18_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH18_RANGE                      18:18
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH18_MSB                        MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH18_LSB                        MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH18_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH18_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH18_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH18_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH18_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH18_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH18_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH19_SHIFT                      MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH19_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH19_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH19_RANGE                      19:19
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH19_MSB                        MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH19_LSB                        MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH19_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH19_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH19_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH19_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH19_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH19_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH19_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH20_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH20_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH20_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH20_RANGE                      20:20
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH20_MSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH20_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH20_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH20_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH20_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH20_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH20_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH20_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH20_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH21_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH21_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH21_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH21_RANGE                      21:21
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH21_MSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH21_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH21_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH21_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH21_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH21_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH21_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH21_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH21_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH22_SHIFT                      MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH22_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH22_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH22_RANGE                      22:22
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH22_MSB                        MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH22_LSB                        MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH22_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH22_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH22_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH22_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH22_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH22_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH22_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH23_SHIFT                      MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH23_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH23_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH23_RANGE                      23:23
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH23_MSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH23_LSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH23_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH23_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH23_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH23_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH23_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH23_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH23_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH24_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH24_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH24_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH24_RANGE                      24:24
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH24_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH24_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH24_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH24_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH24_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH24_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH24_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH24_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH24_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH25_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH25_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH25_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH25_RANGE                      25:25
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH25_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH25_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH25_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH25_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH25_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH25_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH25_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH25_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH25_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH26_SHIFT                      MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH26_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH26_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH26_RANGE                      26:26
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH26_MSB                        MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH26_LSB                        MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH26_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH26_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH26_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH26_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH26_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH26_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH26_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH27_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH27_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH27_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH27_RANGE                      27:27
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH27_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH27_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH27_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH27_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH27_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH27_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH27_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH27_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH27_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH28_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH28_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH28_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH28_RANGE                      28:28
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH28_MSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH28_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH28_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH28_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH28_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH28_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH28_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH28_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH28_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH29_SHIFT                      MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH29_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH29_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH29_RANGE                      29:29
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH29_MSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH29_LSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH29_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH29_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH29_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH29_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH29_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH29_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH29_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH30_SHIFT                      MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH30_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH30_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH30_RANGE                      30:30
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH30_MSB                        MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH30_LSB                        MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH30_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH30_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH30_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH30_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH30_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH30_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH30_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH31_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH31_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_MASKED_INTR_REG_0_CH31_SHIFT)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH31_RANGE                      31:31
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH31_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH31_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH31_WOFFSET                    0x0
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH31_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH31_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH31_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH31_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH31_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_MASKED_INTR_REG_0_CH31_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CHANNEL_INTR_STA_0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0                        MK_ADDR_CONST(0x20)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_SECURE                         0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_DUAL                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_SCR                    SCR_DMA_RO_0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_SCRREG                         GPCDMA_SCR_SCR_DMA_RO_0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_WORD_COUNT                     0x1
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH0_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH0_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH0_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH0_RANGE                      0:0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH0_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH0_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH0_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH1_SHIFT                      MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH1_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH1_RANGE                      1:1
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH1_MSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH1_LSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH1_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH2_SHIFT                      MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH2_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH2_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH2_RANGE                      2:2
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH2_MSB                        MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH2_LSB                        MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH2_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH3_SHIFT                      MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH3_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH3_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH3_RANGE                      3:3
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH3_MSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH3_LSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH3_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH4_SHIFT                      MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH4_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH4_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH4_RANGE                      4:4
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH4_MSB                        MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH4_LSB                        MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH4_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH5_SHIFT                      MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH5_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH5_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH5_RANGE                      5:5
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH5_MSB                        MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH5_LSB                        MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH5_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH6_SHIFT                      MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH6_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH6_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH6_RANGE                      6:6
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH6_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH6_LSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH6_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH7_SHIFT                      MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH7_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH7_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH7_RANGE                      7:7
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH7_MSB                        MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH7_LSB                        MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH7_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH8_SHIFT                      MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH8_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH8_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH8_RANGE                      8:8
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH8_MSB                        MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH8_LSB                        MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH8_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH8_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH8_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH8_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH8_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH8_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH8_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH9_SHIFT                      MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH9_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH9_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH9_RANGE                      9:9
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH9_MSB                        MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH9_LSB                        MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH9_WOFFSET                    0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH9_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH9_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH9_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH9_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH9_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH9_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH10_SHIFT                     MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH10_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH10_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH10_RANGE                     10:10
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH10_MSB                       MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH10_LSB                       MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH10_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH10_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH10_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH10_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH10_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH11_SHIFT                     MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH11_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH11_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH11_RANGE                     11:11
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH11_MSB                       MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH11_LSB                       MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH11_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH11_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH11_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH11_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH11_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH12_SHIFT                     MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH12_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH12_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH12_RANGE                     12:12
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH12_MSB                       MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH12_LSB                       MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH12_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH12_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH12_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH12_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH12_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH12_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH13_SHIFT                     MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH13_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH13_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH13_RANGE                     13:13
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH13_MSB                       MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH13_LSB                       MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH13_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH13_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH13_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH13_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH13_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH13_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH13_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH14_SHIFT                     MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH14_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH14_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH14_RANGE                     14:14
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH14_MSB                       MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH14_LSB                       MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH14_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH14_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH14_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH14_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH14_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH14_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH14_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH15_SHIFT                     MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH15_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH15_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH15_RANGE                     15:15
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH15_MSB                       MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH15_LSB                       MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH15_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH15_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH15_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH15_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH15_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH15_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH15_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH16_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH16_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH16_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH16_RANGE                     16:16
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH16_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH16_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH16_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH16_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH16_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH16_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH16_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH16_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH16_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH17_SHIFT                     MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH17_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH17_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH17_RANGE                     17:17
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH17_MSB                       MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH17_LSB                       MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH17_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH17_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH17_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH17_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH17_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH17_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH17_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH18_SHIFT                     MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH18_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH18_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH18_RANGE                     18:18
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH18_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH18_LSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH18_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH18_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH18_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH18_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH18_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH18_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH18_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH19_SHIFT                     MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH19_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH19_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH19_RANGE                     19:19
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH19_MSB                       MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH19_LSB                       MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH19_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH19_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH19_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH19_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH19_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH19_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH19_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH20_SHIFT                     MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH20_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH20_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH20_RANGE                     20:20
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH20_MSB                       MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH20_LSB                       MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH20_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH20_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH20_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH20_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH20_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH20_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH20_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH21_SHIFT                     MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH21_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH21_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH21_RANGE                     21:21
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH21_MSB                       MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH21_LSB                       MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH21_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH21_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH21_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH21_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH21_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH21_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH21_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH22_SHIFT                     MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH22_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH22_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH22_RANGE                     22:22
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH22_MSB                       MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH22_LSB                       MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH22_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH22_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH22_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH22_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH22_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH22_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH22_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH23_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH23_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH23_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH23_RANGE                     23:23
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH23_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH23_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH23_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH23_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH23_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH23_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH23_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH23_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH23_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH24_SHIFT                     MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH24_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH24_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH24_RANGE                     24:24
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH24_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH24_LSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH24_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH24_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH24_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH24_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH24_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH24_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH24_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH25_SHIFT                     MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH25_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH25_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH25_RANGE                     25:25
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH25_MSB                       MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH25_LSB                       MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH25_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH25_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH25_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH25_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH25_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH25_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH25_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH26_SHIFT                     MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH26_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH26_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH26_RANGE                     26:26
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH26_MSB                       MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH26_LSB                       MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH26_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH26_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH26_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH26_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH26_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH26_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH26_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH27_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH27_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH27_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH27_RANGE                     27:27
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH27_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH27_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH27_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH27_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH27_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH27_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH27_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH27_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH27_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH28_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH28_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH28_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH28_RANGE                     28:28
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH28_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH28_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH28_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH28_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH28_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH28_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH28_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH28_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH28_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH29_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH29_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH29_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH29_RANGE                     29:29
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH29_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH29_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH29_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH29_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH29_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH29_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH29_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH29_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH29_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH30_SHIFT                     MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH30_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH30_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH30_RANGE                     30:30
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH30_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH30_LSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH30_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH30_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH30_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH30_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH30_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH30_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH30_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH31_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH31_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH31_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH31_RANGE                     31:31
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH31_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH31_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH31_WOFFSET                   0x0
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH31_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH31_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH31_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH31_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH31_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_INTR_STA_0_CH31_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_COMMON_INTR_0
+#define GPCDMA_COMMON_COMMON_INTR_0                     MK_ADDR_CONST(0x24)
+#define GPCDMA_COMMON_COMMON_INTR_0_SECURE                      0x0
+#define GPCDMA_COMMON_COMMON_INTR_0_DUAL                        0x0
+#define GPCDMA_COMMON_COMMON_INTR_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_COMMON_INTR_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_COMMON_INTR_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_COMMON_INTR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_RESET_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_COMMON_COMMON_INTR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_READ_MASK                   MK_MASK_CONST(0x1f)
+#define GPCDMA_COMMON_COMMON_INTR_0_WRITE_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_SHIFT                       MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_SHIFT)
+#define GPCDMA_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_RANGE                       4:4
+#define GPCDMA_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_MSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_LSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_WOFFSET                     0x0
+#define GPCDMA_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_SHIFT)
+#define GPCDMA_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_RANGE                       3:3
+#define GPCDMA_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_WOFFSET                     0x0
+#define GPCDMA_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_COMMON_INTR_0_IS_EOC_SHIFT                        MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_COMMON_INTR_0_IS_EOC_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_COMMON_COMMON_INTR_0_IS_EOC_SHIFT)
+#define GPCDMA_COMMON_COMMON_INTR_0_IS_EOC_RANGE                        2:2
+#define GPCDMA_COMMON_COMMON_INTR_0_IS_EOC_MSB                  MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_COMMON_INTR_0_IS_EOC_LSB                  MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_COMMON_INTR_0_IS_EOC_WOFFSET                      0x0
+#define GPCDMA_COMMON_COMMON_INTR_0_IS_EOC_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_IS_EOC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_COMMON_INTR_0_IS_EOC_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_IS_EOC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_IS_EOC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_IS_EOC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_COMMON_INTR_0_INTR_MASK_SHIFT                     MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_COMMON_INTR_0_INTR_MASK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_COMMON_INTR_0_INTR_MASK_SHIFT)
+#define GPCDMA_COMMON_COMMON_INTR_0_INTR_MASK_RANGE                     1:1
+#define GPCDMA_COMMON_COMMON_INTR_0_INTR_MASK_MSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_COMMON_INTR_0_INTR_MASK_LSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_COMMON_INTR_0_INTR_MASK_WOFFSET                   0x0
+#define GPCDMA_COMMON_COMMON_INTR_0_INTR_MASK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_INTR_MASK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_COMMON_INTR_0_INTR_MASK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_INTR_MASK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_INTR_MASK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_INTR_MASK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_COMMON_INTR_0_IE_EOC_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_COMMON_INTR_0_IE_EOC_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_COMMON_COMMON_INTR_0_IE_EOC_SHIFT)
+#define GPCDMA_COMMON_COMMON_INTR_0_IE_EOC_RANGE                        0:0
+#define GPCDMA_COMMON_COMMON_INTR_0_IE_EOC_MSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_COMMON_INTR_0_IE_EOC_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_COMMON_INTR_0_IE_EOC_WOFFSET                      0x0
+#define GPCDMA_COMMON_COMMON_INTR_0_IE_EOC_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_IE_EOC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_COMMON_INTR_0_IE_EOC_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_IE_EOC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_IE_EOC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_COMMON_INTR_0_IE_EOC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CHANNEL_REG_LOCK_0
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0                        MK_ADDR_CONST(0x28)
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_SECURE                         0x0
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_DUAL                   0x0
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_SCR                    SCR_HYPER_0
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_SCRREG                         GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_WORD_COUNT                     0x1
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_SHIFT)
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_RANGE                  31:0
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_WOFFSET                        0x0
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH0_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0                        MK_ADDR_CONST(0x80)
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_SECURE                         0x0
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_DUAL                   0x0
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_SCR                    SCR_HYPER_0
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_SCRREG                         GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_WORD_COUNT                     0x1
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH1_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0                        MK_ADDR_CONST(0x84)
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_SECURE                         0x0
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_DUAL                   0x0
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_SCR                    SCR_HYPER_0
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_SCRREG                         GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_WORD_COUNT                     0x1
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH2_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0                        MK_ADDR_CONST(0x88)
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_SECURE                         0x0
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_DUAL                   0x0
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_SCR                    SCR_HYPER_0
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_SCRREG                         GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_WORD_COUNT                     0x1
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH3_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0                        MK_ADDR_CONST(0x8c)
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_SECURE                         0x0
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_DUAL                   0x0
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_SCR                    SCR_HYPER_0
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_SCRREG                         GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_WORD_COUNT                     0x1
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH4_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0                        MK_ADDR_CONST(0x90)
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_SECURE                         0x0
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_DUAL                   0x0
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_SCR                    SCR_HYPER_0
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_SCRREG                         GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_WORD_COUNT                     0x1
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH5_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0                        MK_ADDR_CONST(0x94)
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_SECURE                         0x0
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_DUAL                   0x0
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_SCR                    SCR_HYPER_0
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_SCRREG                         GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_WORD_COUNT                     0x1
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH6_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0                        MK_ADDR_CONST(0x98)
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_SECURE                         0x0
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_DUAL                   0x0
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_SCR                    SCR_HYPER_0
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_SCRREG                         GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_WORD_COUNT                     0x1
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH7_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0                        MK_ADDR_CONST(0x9c)
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_SECURE                         0x0
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_DUAL                   0x0
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_SCR                    SCR_HYPER_0
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_SCRREG                         GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_WORD_COUNT                     0x1
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH8_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0                        MK_ADDR_CONST(0xa0)
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_SECURE                         0x0
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_DUAL                   0x0
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_SCR                    SCR_HYPER_0
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_SCRREG                         GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_WORD_COUNT                     0x1
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_CH8_PERI_ID_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_CH8_PERI_ID_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH8_PERI_ID_MASK_0_CH8_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_CH8_PERI_ID_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_CH8_PERI_ID_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_CH8_PERI_ID_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_CH8_PERI_ID_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_CH8_PERI_ID_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_CH8_PERI_ID_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_CH8_PERI_ID_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_CH8_PERI_ID_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_CH8_PERI_ID_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_PERI_ID_MASK_0_CH8_PERI_ID_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH9_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0                        MK_ADDR_CONST(0xa4)
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_SECURE                         0x0
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_DUAL                   0x0
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_SCR                    SCR_HYPER_0
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_SCRREG                         GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_WORD_COUNT                     0x1
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_CH9_PERI_ID_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_CH9_PERI_ID_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH9_PERI_ID_MASK_0_CH9_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_CH9_PERI_ID_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_CH9_PERI_ID_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_CH9_PERI_ID_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_CH9_PERI_ID_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_CH9_PERI_ID_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_CH9_PERI_ID_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_CH9_PERI_ID_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_CH9_PERI_ID_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_CH9_PERI_ID_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_PERI_ID_MASK_0_CH9_PERI_ID_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH10_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0                       MK_ADDR_CONST(0xa8)
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_CH10_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_CH10_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH10_PERI_ID_MASK_0_CH10_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_CH10_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_CH10_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_CH10_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_CH10_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_CH10_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_CH10_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_CH10_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_CH10_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_CH10_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_PERI_ID_MASK_0_CH10_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH11_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0                       MK_ADDR_CONST(0xac)
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_CH11_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_CH11_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH11_PERI_ID_MASK_0_CH11_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_CH11_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_CH11_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_CH11_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_CH11_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_CH11_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_CH11_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_CH11_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_CH11_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_CH11_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_PERI_ID_MASK_0_CH11_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH12_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0                       MK_ADDR_CONST(0xb0)
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_CH12_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_CH12_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH12_PERI_ID_MASK_0_CH12_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_CH12_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_CH12_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_CH12_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_CH12_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_CH12_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_CH12_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_CH12_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_CH12_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_CH12_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_PERI_ID_MASK_0_CH12_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH13_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0                       MK_ADDR_CONST(0xb4)
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_CH13_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_CH13_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH13_PERI_ID_MASK_0_CH13_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_CH13_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_CH13_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_CH13_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_CH13_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_CH13_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_CH13_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_CH13_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_CH13_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_CH13_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_PERI_ID_MASK_0_CH13_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH14_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0                       MK_ADDR_CONST(0xb8)
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_CH14_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_CH14_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH14_PERI_ID_MASK_0_CH14_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_CH14_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_CH14_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_CH14_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_CH14_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_CH14_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_CH14_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_CH14_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_CH14_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_CH14_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_PERI_ID_MASK_0_CH14_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH15_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0                       MK_ADDR_CONST(0xbc)
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_CH15_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_CH15_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH15_PERI_ID_MASK_0_CH15_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_CH15_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_CH15_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_CH15_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_CH15_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_CH15_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_CH15_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_CH15_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_CH15_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_CH15_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_PERI_ID_MASK_0_CH15_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH16_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0                       MK_ADDR_CONST(0xc0)
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_CH16_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_CH16_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH16_PERI_ID_MASK_0_CH16_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_CH16_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_CH16_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_CH16_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_CH16_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_CH16_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_CH16_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_CH16_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_CH16_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_CH16_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_PERI_ID_MASK_0_CH16_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH17_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0                       MK_ADDR_CONST(0xc4)
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_CH17_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_CH17_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH17_PERI_ID_MASK_0_CH17_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_CH17_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_CH17_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_CH17_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_CH17_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_CH17_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_CH17_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_CH17_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_CH17_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_CH17_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_PERI_ID_MASK_0_CH17_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH18_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0                       MK_ADDR_CONST(0xc8)
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_CH18_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_CH18_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH18_PERI_ID_MASK_0_CH18_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_CH18_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_CH18_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_CH18_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_CH18_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_CH18_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_CH18_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_CH18_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_CH18_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_CH18_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_PERI_ID_MASK_0_CH18_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH19_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0                       MK_ADDR_CONST(0xcc)
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_CH19_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_CH19_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH19_PERI_ID_MASK_0_CH19_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_CH19_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_CH19_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_CH19_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_CH19_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_CH19_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_CH19_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_CH19_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_CH19_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_CH19_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_PERI_ID_MASK_0_CH19_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH20_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0                       MK_ADDR_CONST(0xd0)
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_CH20_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_CH20_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH20_PERI_ID_MASK_0_CH20_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_CH20_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_CH20_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_CH20_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_CH20_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_CH20_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_CH20_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_CH20_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_CH20_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_CH20_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_PERI_ID_MASK_0_CH20_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH21_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0                       MK_ADDR_CONST(0xd4)
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_CH21_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_CH21_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH21_PERI_ID_MASK_0_CH21_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_CH21_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_CH21_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_CH21_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_CH21_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_CH21_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_CH21_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_CH21_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_CH21_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_CH21_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_PERI_ID_MASK_0_CH21_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH22_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0                       MK_ADDR_CONST(0xd8)
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_CH22_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_CH22_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH22_PERI_ID_MASK_0_CH22_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_CH22_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_CH22_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_CH22_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_CH22_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_CH22_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_CH22_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_CH22_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_CH22_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_CH22_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_PERI_ID_MASK_0_CH22_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH23_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0                       MK_ADDR_CONST(0xdc)
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_CH23_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_CH23_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH23_PERI_ID_MASK_0_CH23_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_CH23_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_CH23_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_CH23_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_CH23_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_CH23_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_CH23_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_CH23_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_CH23_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_CH23_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_PERI_ID_MASK_0_CH23_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH24_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0                       MK_ADDR_CONST(0xe0)
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_CH24_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_CH24_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH24_PERI_ID_MASK_0_CH24_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_CH24_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_CH24_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_CH24_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_CH24_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_CH24_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_CH24_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_CH24_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_CH24_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_CH24_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_PERI_ID_MASK_0_CH24_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH25_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0                       MK_ADDR_CONST(0xe4)
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_CH25_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_CH25_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH25_PERI_ID_MASK_0_CH25_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_CH25_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_CH25_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_CH25_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_CH25_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_CH25_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_CH25_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_CH25_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_CH25_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_CH25_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_PERI_ID_MASK_0_CH25_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH26_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0                       MK_ADDR_CONST(0xe8)
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_CH26_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_CH26_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH26_PERI_ID_MASK_0_CH26_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_CH26_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_CH26_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_CH26_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_CH26_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_CH26_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_CH26_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_CH26_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_CH26_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_CH26_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_PERI_ID_MASK_0_CH26_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH27_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0                       MK_ADDR_CONST(0xec)
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_CH27_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_CH27_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH27_PERI_ID_MASK_0_CH27_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_CH27_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_CH27_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_CH27_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_CH27_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_CH27_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_CH27_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_CH27_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_CH27_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_CH27_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_PERI_ID_MASK_0_CH27_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH28_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0                       MK_ADDR_CONST(0xf0)
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_CH28_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_CH28_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH28_PERI_ID_MASK_0_CH28_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_CH28_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_CH28_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_CH28_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_CH28_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_CH28_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_CH28_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_CH28_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_CH28_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_CH28_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_PERI_ID_MASK_0_CH28_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH29_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0                       MK_ADDR_CONST(0xf4)
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_CH29_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_CH29_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH29_PERI_ID_MASK_0_CH29_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_CH29_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_CH29_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_CH29_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_CH29_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_CH29_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_CH29_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_CH29_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_CH29_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_CH29_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_PERI_ID_MASK_0_CH29_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH30_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0                       MK_ADDR_CONST(0xf8)
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_CH30_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_CH30_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH30_PERI_ID_MASK_0_CH30_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_CH30_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_CH30_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_CH30_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_CH30_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_CH30_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_CH30_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_CH30_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_CH30_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_CH30_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_PERI_ID_MASK_0_CH30_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH31_PERI_ID_MASK_0
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0                       MK_ADDR_CONST(0xfc)
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_SCRREG                        GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_CH31_PERI_ID_MASK_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_CH31_PERI_ID_MASK_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH31_PERI_ID_MASK_0_CH31_PERI_ID_MASK_SHIFT)
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_CH31_PERI_ID_MASK_RANGE                       31:0
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_CH31_PERI_ID_MASK_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_CH31_PERI_ID_MASK_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_CH31_PERI_ID_MASK_WOFFSET                     0x0
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_CH31_PERI_ID_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_CH31_PERI_ID_MASK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_CH31_PERI_ID_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_CH31_PERI_ID_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_CH31_PERI_ID_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_PERI_ID_MASK_0_CH31_PERI_ID_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER0_PERI_ADDR_0
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0                  MK_ADDR_CONST(0x100)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_SECURE                   0x0
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_DUAL                     0x0
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_SCR                      SCR_HYPER_0
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_SCRREG                   GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_WORD_COUNT                       0x1
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_FIELD                       MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_RANGE                       31:16
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_WOFFSET                     0x0
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_FIELD                   MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_RANGE                   15:0
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_MSB                     MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_WOFFSET                 0x0
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER1_PERI_ADDR_0
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0                  MK_ADDR_CONST(0x104)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_SECURE                   0x0
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_DUAL                     0x0
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_SCR                      SCR_HYPER_0
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_SCRREG                   GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_WORD_COUNT                       0x1
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_FIELD                       MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_RANGE                       31:16
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_WOFFSET                     0x0
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_FIELD                   MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_RANGE                   15:0
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_MSB                     MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_WOFFSET                 0x0
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER2_PERI_ADDR_0
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0                  MK_ADDR_CONST(0x108)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_SECURE                   0x0
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_DUAL                     0x0
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_SCR                      SCR_HYPER_0
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_SCRREG                   GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_WORD_COUNT                       0x1
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_FIELD                       MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_RANGE                       31:16
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_WOFFSET                     0x0
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_FIELD                   MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_RANGE                   15:0
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_MSB                     MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_WOFFSET                 0x0
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER3_PERI_ADDR_0
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0                  MK_ADDR_CONST(0x10c)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_SECURE                   0x0
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_DUAL                     0x0
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_SCR                      SCR_HYPER_0
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_SCRREG                   GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_WORD_COUNT                       0x1
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_FIELD                       MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_RANGE                       31:16
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_WOFFSET                     0x0
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_FIELD                   MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_RANGE                   15:0
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_MSB                     MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_WOFFSET                 0x0
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER4_PERI_ADDR_0
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0                  MK_ADDR_CONST(0x110)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_SECURE                   0x0
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_DUAL                     0x0
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_SCR                      SCR_HYPER_0
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_SCRREG                   GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_WORD_COUNT                       0x1
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_FIELD                       MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_RANGE                       31:16
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_WOFFSET                     0x0
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_FIELD                   MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_RANGE                   15:0
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_MSB                     MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_WOFFSET                 0x0
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER5_PERI_ADDR_0
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0                  MK_ADDR_CONST(0x114)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_SECURE                   0x0
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_DUAL                     0x0
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_SCR                      SCR_HYPER_0
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_SCRREG                   GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_WORD_COUNT                       0x1
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_FIELD                       MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_RANGE                       31:16
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_WOFFSET                     0x0
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_FIELD                   MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_RANGE                   15:0
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_MSB                     MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_WOFFSET                 0x0
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER6_PERI_ADDR_0
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0                  MK_ADDR_CONST(0x118)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_SECURE                   0x0
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_DUAL                     0x0
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_SCR                      SCR_HYPER_0
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_SCRREG                   GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_WORD_COUNT                       0x1
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_FIELD                       MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_RANGE                       31:16
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_WOFFSET                     0x0
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_FIELD                   MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_RANGE                   15:0
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_MSB                     MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_WOFFSET                 0x0
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER7_PERI_ADDR_0
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0                  MK_ADDR_CONST(0x11c)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_SECURE                   0x0
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_DUAL                     0x0
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_SCR                      SCR_HYPER_0
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_SCRREG                   GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_WORD_COUNT                       0x1
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_FIELD                       MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_RANGE                       31:16
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_WOFFSET                     0x0
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_FIELD                   MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_RANGE                   15:0
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_MSB                     MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_WOFFSET                 0x0
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER8_PERI_ADDR_0
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0                  MK_ADDR_CONST(0x120)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_SECURE                   0x0
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_DUAL                     0x0
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_SCR                      SCR_HYPER_0
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_SCRREG                   GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_WORD_COUNT                       0x1
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_FIELD                       MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_RANGE                       31:16
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_WOFFSET                     0x0
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_FIELD                   MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_RANGE                   15:0
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_MSB                     MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_WOFFSET                 0x0
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER9_PERI_ADDR_0
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0                  MK_ADDR_CONST(0x124)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_SECURE                   0x0
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_DUAL                     0x0
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_SCR                      SCR_HYPER_0
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_SCRREG                   GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_WORD_COUNT                       0x1
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_FIELD                       MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_RANGE                       31:16
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_WOFFSET                     0x0
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_FIELD                   MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_RANGE                   15:0
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_MSB                     MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_WOFFSET                 0x0
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER10_PERI_ADDR_0
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0                 MK_ADDR_CONST(0x128)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER11_PERI_ADDR_0
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0                 MK_ADDR_CONST(0x12c)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER12_PERI_ADDR_0
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0                 MK_ADDR_CONST(0x130)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER13_PERI_ADDR_0
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0                 MK_ADDR_CONST(0x134)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER14_PERI_ADDR_0
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0                 MK_ADDR_CONST(0x138)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER15_PERI_ADDR_0
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0                 MK_ADDR_CONST(0x13c)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER16_PERI_ADDR_0
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0                 MK_ADDR_CONST(0x140)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER16_PERI_ADDR_0_PER16_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER17_PERI_ADDR_0
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0                 MK_ADDR_CONST(0x144)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER17_PERI_ADDR_0_PER17_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER18_PERI_ADDR_0
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0                 MK_ADDR_CONST(0x148)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER18_PERI_ADDR_0_PER18_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER19_PERI_ADDR_0
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0                 MK_ADDR_CONST(0x14c)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER19_PERI_ADDR_0_PER19_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER20_PERI_ADDR_0
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0                 MK_ADDR_CONST(0x150)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER20_PERI_ADDR_0_PER20_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER21_PERI_ADDR_0
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0                 MK_ADDR_CONST(0x154)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER21_PERI_ADDR_0_PER21_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER22_PERI_ADDR_0
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0                 MK_ADDR_CONST(0x158)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER22_PERI_ADDR_0_PER22_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER23_PERI_ADDR_0
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0                 MK_ADDR_CONST(0x15c)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER23_PERI_ADDR_0_PER23_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER24_PERI_ADDR_0
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0                 MK_ADDR_CONST(0x160)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER24_PERI_ADDR_0_PER24_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER25_PERI_ADDR_0
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0                 MK_ADDR_CONST(0x164)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER25_PERI_ADDR_0_PER25_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER26_PERI_ADDR_0
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0                 MK_ADDR_CONST(0x168)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER26_PERI_ADDR_0_PER26_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER27_PERI_ADDR_0
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0                 MK_ADDR_CONST(0x16c)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER27_PERI_ADDR_0_PER27_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER28_PERI_ADDR_0
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0                 MK_ADDR_CONST(0x170)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER28_PERI_ADDR_0_PER28_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER29_PERI_ADDR_0
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0                 MK_ADDR_CONST(0x174)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER29_PERI_ADDR_0_PER29_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER30_PERI_ADDR_0
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0                 MK_ADDR_CONST(0x178)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER30_PERI_ADDR_0_PER30_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_PER31_PERI_ADDR_0
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0                 MK_ADDR_CONST(0x17c)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_SCRREG                  GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_START_ADDR_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_START_ADDR_FIELD                     MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_START_ADDR_SHIFT)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_START_ADDR_RANGE                     31:16
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_START_ADDR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_START_ADDR_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_START_ADDR_WOFFSET                   0x0
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_START_ADDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_START_ADDR_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_START_ADDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_START_ADDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_START_ADDR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_START_ADDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_OFFSET_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_OFFSET_FIELD                 MK_FIELD_CONST(0xffff, GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_OFFSET_SHIFT)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_OFFSET_RANGE                 15:0
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_OFFSET_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_OFFSET_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_OFFSET_WOFFSET                       0x0
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_OFFSET_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_OFFSET_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_OFFSET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_OFFSET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_OFFSET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_PER31_PERI_ADDR_0_PER31_PERI_OFFSET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0                     MK_ADDR_CONST(0x180)
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0                     MK_ADDR_CONST(0x184)
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0                     MK_ADDR_CONST(0x188)
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0                     MK_ADDR_CONST(0x18c)
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0                     MK_ADDR_CONST(0x190)
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0                     MK_ADDR_CONST(0x194)
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0                     MK_ADDR_CONST(0x198)
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0                     MK_ADDR_CONST(0x19c)
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0                     MK_ADDR_CONST(0x1a0)
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_CH8_STREAM_ID0_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_CH8_STREAM_ID0_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_CH8_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_CH8_STREAM_ID0_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_CH8_STREAM_ID0_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_CH8_STREAM_ID0_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_CH8_STREAM_ID0_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_CH8_STREAM_ID0_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_CH8_STREAM_ID0_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_CH8_STREAM_ID0_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_CH8_STREAM_ID0_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_CH8_STREAM_ID0_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0_CH8_STREAM_ID0_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0                     MK_ADDR_CONST(0x1a4)
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_CH9_STREAM_ID0_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_CH9_STREAM_ID0_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_CH9_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_CH9_STREAM_ID0_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_CH9_STREAM_ID0_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_CH9_STREAM_ID0_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_CH9_STREAM_ID0_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_CH9_STREAM_ID0_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_CH9_STREAM_ID0_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_CH9_STREAM_ID0_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_CH9_STREAM_ID0_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_CH9_STREAM_ID0_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0_CH9_STREAM_ID0_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1a8)
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_CH10_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_CH10_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_CH10_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_CH10_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_CH10_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_CH10_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_CH10_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_CH10_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_CH10_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_CH10_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_CH10_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_CH10_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0_CH10_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1ac)
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_CH11_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_CH11_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_CH11_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_CH11_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_CH11_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_CH11_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_CH11_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_CH11_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_CH11_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_CH11_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_CH11_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_CH11_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0_CH11_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1b0)
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_CH12_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_CH12_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_CH12_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_CH12_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_CH12_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_CH12_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_CH12_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_CH12_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_CH12_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_CH12_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_CH12_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_CH12_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0_CH12_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1b4)
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_CH13_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_CH13_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_CH13_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_CH13_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_CH13_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_CH13_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_CH13_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_CH13_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_CH13_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_CH13_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_CH13_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_CH13_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0_CH13_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1b8)
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_CH14_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_CH14_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_CH14_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_CH14_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_CH14_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_CH14_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_CH14_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_CH14_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_CH14_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_CH14_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_CH14_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_CH14_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0_CH14_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1bc)
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_CH15_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_CH15_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_CH15_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_CH15_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_CH15_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_CH15_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_CH15_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_CH15_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_CH15_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_CH15_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_CH15_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_CH15_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0_CH15_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1c0)
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_CH16_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_CH16_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_CH16_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_CH16_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_CH16_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_CH16_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_CH16_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_CH16_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_CH16_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_CH16_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_CH16_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_CH16_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0_CH16_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1c4)
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_CH17_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_CH17_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_CH17_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_CH17_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_CH17_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_CH17_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_CH17_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_CH17_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_CH17_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_CH17_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_CH17_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_CH17_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0_CH17_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1c8)
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_CH18_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_CH18_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_CH18_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_CH18_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_CH18_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_CH18_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_CH18_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_CH18_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_CH18_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_CH18_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_CH18_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_CH18_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0_CH18_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1cc)
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_CH19_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_CH19_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_CH19_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_CH19_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_CH19_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_CH19_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_CH19_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_CH19_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_CH19_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_CH19_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_CH19_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_CH19_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0_CH19_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1d0)
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_CH20_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_CH20_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_CH20_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_CH20_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_CH20_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_CH20_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_CH20_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_CH20_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_CH20_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_CH20_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_CH20_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_CH20_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0_CH20_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1d4)
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_CH21_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_CH21_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_CH21_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_CH21_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_CH21_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_CH21_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_CH21_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_CH21_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_CH21_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_CH21_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_CH21_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_CH21_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0_CH21_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1d8)
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_CH22_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_CH22_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_CH22_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_CH22_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_CH22_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_CH22_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_CH22_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_CH22_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_CH22_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_CH22_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_CH22_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_CH22_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0_CH22_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1dc)
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_CH23_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_CH23_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_CH23_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_CH23_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_CH23_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_CH23_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_CH23_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_CH23_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_CH23_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_CH23_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_CH23_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_CH23_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0_CH23_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1e0)
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_CH24_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_CH24_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_CH24_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_CH24_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_CH24_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_CH24_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_CH24_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_CH24_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_CH24_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_CH24_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_CH24_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_CH24_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0_CH24_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1e4)
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_CH25_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_CH25_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_CH25_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_CH25_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_CH25_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_CH25_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_CH25_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_CH25_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_CH25_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_CH25_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_CH25_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_CH25_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0_CH25_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1e8)
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_CH26_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_CH26_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_CH26_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_CH26_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_CH26_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_CH26_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_CH26_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_CH26_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_CH26_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_CH26_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_CH26_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_CH26_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0_CH26_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1ec)
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_CH27_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_CH27_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_CH27_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_CH27_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_CH27_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_CH27_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_CH27_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_CH27_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_CH27_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_CH27_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_CH27_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_CH27_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0_CH27_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1f0)
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_CH28_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_CH28_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_CH28_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_CH28_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_CH28_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_CH28_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_CH28_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_CH28_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_CH28_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_CH28_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_CH28_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_CH28_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0_CH28_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1f4)
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_CH29_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_CH29_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_CH29_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_CH29_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_CH29_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_CH29_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_CH29_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_CH29_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_CH29_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_CH29_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_CH29_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_CH29_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0_CH29_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1f8)
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_CH30_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_CH30_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_CH30_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_CH30_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_CH30_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_CH30_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_CH30_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_CH30_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_CH30_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_CH30_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_CH30_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_CH30_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0_CH30_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x1fc)
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_CH31_STREAM_ID0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_CH31_STREAM_ID0_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_CH31_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_CH31_STREAM_ID0_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_CH31_STREAM_ID0_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_CH31_STREAM_ID0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_CH31_STREAM_ID0_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_CH31_STREAM_ID0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_CH31_STREAM_ID0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_CH31_STREAM_ID0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_CH31_STREAM_ID0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_CH31_STREAM_ID0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0_CH31_STREAM_ID0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0                     MK_ADDR_CONST(0x200)
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0                     MK_ADDR_CONST(0x204)
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0                     MK_ADDR_CONST(0x208)
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0                     MK_ADDR_CONST(0x20c)
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0                     MK_ADDR_CONST(0x210)
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0                     MK_ADDR_CONST(0x214)
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0                     MK_ADDR_CONST(0x218)
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0                     MK_ADDR_CONST(0x21c)
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0                     MK_ADDR_CONST(0x220)
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_CH8_STREAM_ID1_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_CH8_STREAM_ID1_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_CH8_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_CH8_STREAM_ID1_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_CH8_STREAM_ID1_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_CH8_STREAM_ID1_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_CH8_STREAM_ID1_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_CH8_STREAM_ID1_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_CH8_STREAM_ID1_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_CH8_STREAM_ID1_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_CH8_STREAM_ID1_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_CH8_STREAM_ID1_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0_CH8_STREAM_ID1_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0                     MK_ADDR_CONST(0x224)
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_CH9_STREAM_ID1_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_CH9_STREAM_ID1_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_CH9_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_CH9_STREAM_ID1_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_CH9_STREAM_ID1_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_CH9_STREAM_ID1_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_CH9_STREAM_ID1_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_CH9_STREAM_ID1_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_CH9_STREAM_ID1_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_CH9_STREAM_ID1_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_CH9_STREAM_ID1_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_CH9_STREAM_ID1_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0_CH9_STREAM_ID1_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x228)
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_CH10_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_CH10_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_CH10_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_CH10_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_CH10_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_CH10_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_CH10_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_CH10_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_CH10_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_CH10_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_CH10_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_CH10_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0_CH10_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x22c)
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_CH11_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_CH11_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_CH11_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_CH11_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_CH11_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_CH11_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_CH11_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_CH11_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_CH11_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_CH11_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_CH11_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_CH11_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0_CH11_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x230)
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_CH12_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_CH12_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_CH12_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_CH12_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_CH12_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_CH12_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_CH12_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_CH12_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_CH12_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_CH12_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_CH12_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_CH12_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0_CH12_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x234)
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_CH13_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_CH13_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_CH13_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_CH13_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_CH13_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_CH13_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_CH13_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_CH13_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_CH13_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_CH13_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_CH13_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_CH13_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0_CH13_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x238)
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_CH14_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_CH14_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_CH14_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_CH14_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_CH14_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_CH14_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_CH14_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_CH14_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_CH14_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_CH14_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_CH14_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_CH14_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0_CH14_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x23c)
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_CH15_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_CH15_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_CH15_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_CH15_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_CH15_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_CH15_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_CH15_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_CH15_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_CH15_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_CH15_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_CH15_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_CH15_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0_CH15_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x240)
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_CH16_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_CH16_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_CH16_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_CH16_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_CH16_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_CH16_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_CH16_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_CH16_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_CH16_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_CH16_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_CH16_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_CH16_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0_CH16_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x244)
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_CH17_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_CH17_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_CH17_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_CH17_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_CH17_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_CH17_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_CH17_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_CH17_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_CH17_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_CH17_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_CH17_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_CH17_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0_CH17_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x248)
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_CH18_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_CH18_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_CH18_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_CH18_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_CH18_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_CH18_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_CH18_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_CH18_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_CH18_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_CH18_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_CH18_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_CH18_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0_CH18_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x24c)
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_CH19_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_CH19_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_CH19_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_CH19_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_CH19_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_CH19_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_CH19_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_CH19_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_CH19_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_CH19_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_CH19_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_CH19_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0_CH19_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x250)
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_CH20_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_CH20_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_CH20_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_CH20_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_CH20_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_CH20_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_CH20_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_CH20_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_CH20_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_CH20_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_CH20_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_CH20_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0_CH20_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x254)
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_CH21_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_CH21_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_CH21_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_CH21_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_CH21_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_CH21_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_CH21_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_CH21_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_CH21_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_CH21_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_CH21_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_CH21_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0_CH21_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x258)
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_CH22_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_CH22_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_CH22_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_CH22_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_CH22_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_CH22_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_CH22_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_CH22_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_CH22_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_CH22_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_CH22_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_CH22_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0_CH22_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x25c)
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_CH23_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_CH23_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_CH23_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_CH23_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_CH23_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_CH23_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_CH23_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_CH23_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_CH23_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_CH23_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_CH23_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_CH23_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0_CH23_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x260)
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_CH24_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_CH24_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_CH24_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_CH24_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_CH24_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_CH24_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_CH24_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_CH24_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_CH24_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_CH24_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_CH24_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_CH24_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0_CH24_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x264)
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_CH25_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_CH25_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_CH25_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_CH25_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_CH25_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_CH25_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_CH25_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_CH25_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_CH25_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_CH25_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_CH25_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_CH25_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0_CH25_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x268)
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_CH26_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_CH26_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_CH26_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_CH26_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_CH26_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_CH26_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_CH26_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_CH26_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_CH26_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_CH26_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_CH26_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_CH26_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0_CH26_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x26c)
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_CH27_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_CH27_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_CH27_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_CH27_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_CH27_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_CH27_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_CH27_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_CH27_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_CH27_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_CH27_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_CH27_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_CH27_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0_CH27_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x270)
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_CH28_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_CH28_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_CH28_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_CH28_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_CH28_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_CH28_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_CH28_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_CH28_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_CH28_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_CH28_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_CH28_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_CH28_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0_CH28_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x274)
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_CH29_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_CH29_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_CH29_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_CH29_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_CH29_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_CH29_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_CH29_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_CH29_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_CH29_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_CH29_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_CH29_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_CH29_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0_CH29_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x278)
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_CH30_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_CH30_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_CH30_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_CH30_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_CH30_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_CH30_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_CH30_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_CH30_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_CH30_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_CH30_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_CH30_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_CH30_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0_CH30_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x27c)
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_CH31_STREAM_ID1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_CH31_STREAM_ID1_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_CH31_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_CH31_STREAM_ID1_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_CH31_STREAM_ID1_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_CH31_STREAM_ID1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_CH31_STREAM_ID1_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_CH31_STREAM_ID1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_CH31_STREAM_ID1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_CH31_STREAM_ID1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_CH31_STREAM_ID1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_CH31_STREAM_ID1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0_CH31_STREAM_ID1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0                     MK_ADDR_CONST(0x280)
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0                     MK_ADDR_CONST(0x284)
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0                     MK_ADDR_CONST(0x288)
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0                     MK_ADDR_CONST(0x28c)
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0                     MK_ADDR_CONST(0x290)
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0                     MK_ADDR_CONST(0x294)
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0                     MK_ADDR_CONST(0x298)
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0                     MK_ADDR_CONST(0x29c)
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0                     MK_ADDR_CONST(0x2a0)
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_CH8_STREAM_ID2_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_CH8_STREAM_ID2_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_CH8_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_CH8_STREAM_ID2_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_CH8_STREAM_ID2_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_CH8_STREAM_ID2_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_CH8_STREAM_ID2_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_CH8_STREAM_ID2_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_CH8_STREAM_ID2_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_CH8_STREAM_ID2_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_CH8_STREAM_ID2_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_CH8_STREAM_ID2_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0_CH8_STREAM_ID2_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0                     MK_ADDR_CONST(0x2a4)
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_CH9_STREAM_ID2_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_CH9_STREAM_ID2_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_CH9_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_CH9_STREAM_ID2_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_CH9_STREAM_ID2_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_CH9_STREAM_ID2_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_CH9_STREAM_ID2_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_CH9_STREAM_ID2_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_CH9_STREAM_ID2_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_CH9_STREAM_ID2_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_CH9_STREAM_ID2_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_CH9_STREAM_ID2_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0_CH9_STREAM_ID2_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2a8)
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_CH10_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_CH10_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_CH10_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_CH10_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_CH10_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_CH10_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_CH10_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_CH10_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_CH10_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_CH10_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_CH10_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_CH10_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0_CH10_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2ac)
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_CH11_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_CH11_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_CH11_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_CH11_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_CH11_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_CH11_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_CH11_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_CH11_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_CH11_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_CH11_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_CH11_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_CH11_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0_CH11_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2b0)
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_CH12_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_CH12_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_CH12_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_CH12_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_CH12_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_CH12_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_CH12_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_CH12_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_CH12_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_CH12_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_CH12_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_CH12_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0_CH12_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2b4)
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_CH13_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_CH13_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_CH13_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_CH13_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_CH13_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_CH13_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_CH13_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_CH13_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_CH13_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_CH13_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_CH13_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_CH13_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0_CH13_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2b8)
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_CH14_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_CH14_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_CH14_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_CH14_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_CH14_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_CH14_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_CH14_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_CH14_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_CH14_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_CH14_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_CH14_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_CH14_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0_CH14_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2bc)
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_CH15_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_CH15_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_CH15_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_CH15_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_CH15_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_CH15_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_CH15_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_CH15_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_CH15_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_CH15_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_CH15_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_CH15_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0_CH15_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2c0)
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_CH16_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_CH16_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_CH16_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_CH16_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_CH16_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_CH16_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_CH16_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_CH16_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_CH16_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_CH16_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_CH16_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_CH16_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0_CH16_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2c4)
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_CH17_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_CH17_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_CH17_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_CH17_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_CH17_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_CH17_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_CH17_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_CH17_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_CH17_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_CH17_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_CH17_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_CH17_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0_CH17_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2c8)
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_CH18_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_CH18_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_CH18_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_CH18_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_CH18_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_CH18_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_CH18_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_CH18_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_CH18_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_CH18_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_CH18_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_CH18_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0_CH18_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2cc)
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_CH19_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_CH19_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_CH19_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_CH19_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_CH19_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_CH19_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_CH19_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_CH19_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_CH19_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_CH19_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_CH19_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_CH19_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0_CH19_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2d0)
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_CH20_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_CH20_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_CH20_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_CH20_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_CH20_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_CH20_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_CH20_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_CH20_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_CH20_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_CH20_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_CH20_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_CH20_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0_CH20_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2d4)
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_CH21_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_CH21_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_CH21_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_CH21_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_CH21_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_CH21_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_CH21_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_CH21_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_CH21_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_CH21_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_CH21_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_CH21_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0_CH21_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2d8)
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_CH22_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_CH22_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_CH22_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_CH22_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_CH22_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_CH22_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_CH22_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_CH22_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_CH22_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_CH22_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_CH22_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_CH22_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0_CH22_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2dc)
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_CH23_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_CH23_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_CH23_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_CH23_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_CH23_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_CH23_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_CH23_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_CH23_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_CH23_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_CH23_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_CH23_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_CH23_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0_CH23_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2e0)
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_CH24_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_CH24_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_CH24_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_CH24_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_CH24_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_CH24_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_CH24_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_CH24_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_CH24_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_CH24_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_CH24_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_CH24_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0_CH24_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2e4)
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_CH25_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_CH25_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_CH25_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_CH25_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_CH25_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_CH25_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_CH25_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_CH25_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_CH25_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_CH25_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_CH25_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_CH25_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0_CH25_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2e8)
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_CH26_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_CH26_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_CH26_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_CH26_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_CH26_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_CH26_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_CH26_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_CH26_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_CH26_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_CH26_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_CH26_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_CH26_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0_CH26_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2ec)
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_CH27_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_CH27_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_CH27_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_CH27_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_CH27_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_CH27_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_CH27_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_CH27_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_CH27_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_CH27_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_CH27_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_CH27_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0_CH27_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2f0)
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_CH28_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_CH28_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_CH28_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_CH28_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_CH28_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_CH28_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_CH28_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_CH28_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_CH28_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_CH28_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_CH28_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_CH28_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0_CH28_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2f4)
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_CH29_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_CH29_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_CH29_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_CH29_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_CH29_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_CH29_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_CH29_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_CH29_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_CH29_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_CH29_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_CH29_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_CH29_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0_CH29_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2f8)
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_CH30_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_CH30_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_CH30_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_CH30_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_CH30_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_CH30_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_CH30_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_CH30_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_CH30_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_CH30_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_CH30_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_CH30_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0_CH30_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x2fc)
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_CH31_STREAM_ID2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_CH31_STREAM_ID2_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_CH31_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_CH31_STREAM_ID2_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_CH31_STREAM_ID2_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_CH31_STREAM_ID2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_CH31_STREAM_ID2_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_CH31_STREAM_ID2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_CH31_STREAM_ID2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_CH31_STREAM_ID2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_CH31_STREAM_ID2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_CH31_STREAM_ID2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0_CH31_STREAM_ID2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0                     MK_ADDR_CONST(0x300)
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0                     MK_ADDR_CONST(0x304)
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0                     MK_ADDR_CONST(0x308)
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0                     MK_ADDR_CONST(0x30c)
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0                     MK_ADDR_CONST(0x310)
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0                     MK_ADDR_CONST(0x314)
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0                     MK_ADDR_CONST(0x318)
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0                     MK_ADDR_CONST(0x31c)
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0                     MK_ADDR_CONST(0x320)
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_CH8_STREAM_ID3_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_CH8_STREAM_ID3_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_CH8_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_CH8_STREAM_ID3_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_CH8_STREAM_ID3_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_CH8_STREAM_ID3_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_CH8_STREAM_ID3_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_CH8_STREAM_ID3_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_CH8_STREAM_ID3_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_CH8_STREAM_ID3_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_CH8_STREAM_ID3_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_CH8_STREAM_ID3_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0_CH8_STREAM_ID3_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0                     MK_ADDR_CONST(0x324)
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_SECURE                      0x0
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_DUAL                        0x0
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_SCR                         SCR_HYPER_0
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_SCRREG                      GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_CH9_STREAM_ID3_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_CH9_STREAM_ID3_MASK_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_CH9_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_CH9_STREAM_ID3_MASK_RANGE                   31:0
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_CH9_STREAM_ID3_MASK_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_CH9_STREAM_ID3_MASK_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_CH9_STREAM_ID3_MASK_WOFFSET                 0x0
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_CH9_STREAM_ID3_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_CH9_STREAM_ID3_MASK_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_CH9_STREAM_ID3_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_CH9_STREAM_ID3_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_CH9_STREAM_ID3_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0_CH9_STREAM_ID3_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x328)
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_CH10_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_CH10_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_CH10_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_CH10_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_CH10_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_CH10_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_CH10_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_CH10_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_CH10_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_CH10_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_CH10_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_CH10_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0_CH10_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x32c)
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_CH11_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_CH11_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_CH11_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_CH11_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_CH11_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_CH11_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_CH11_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_CH11_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_CH11_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_CH11_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_CH11_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_CH11_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0_CH11_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x330)
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_CH12_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_CH12_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_CH12_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_CH12_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_CH12_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_CH12_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_CH12_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_CH12_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_CH12_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_CH12_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_CH12_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_CH12_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0_CH12_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x334)
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_CH13_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_CH13_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_CH13_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_CH13_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_CH13_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_CH13_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_CH13_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_CH13_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_CH13_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_CH13_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_CH13_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_CH13_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0_CH13_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x338)
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_CH14_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_CH14_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_CH14_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_CH14_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_CH14_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_CH14_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_CH14_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_CH14_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_CH14_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_CH14_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_CH14_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_CH14_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0_CH14_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x33c)
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_CH15_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_CH15_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_CH15_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_CH15_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_CH15_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_CH15_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_CH15_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_CH15_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_CH15_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_CH15_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_CH15_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_CH15_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0_CH15_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x340)
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_CH16_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_CH16_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_CH16_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_CH16_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_CH16_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_CH16_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_CH16_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_CH16_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_CH16_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_CH16_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_CH16_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_CH16_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0_CH16_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x344)
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_CH17_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_CH17_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_CH17_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_CH17_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_CH17_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_CH17_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_CH17_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_CH17_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_CH17_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_CH17_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_CH17_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_CH17_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0_CH17_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x348)
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_CH18_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_CH18_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_CH18_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_CH18_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_CH18_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_CH18_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_CH18_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_CH18_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_CH18_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_CH18_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_CH18_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_CH18_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0_CH18_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x34c)
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_CH19_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_CH19_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_CH19_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_CH19_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_CH19_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_CH19_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_CH19_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_CH19_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_CH19_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_CH19_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_CH19_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_CH19_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0_CH19_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x350)
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_CH20_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_CH20_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_CH20_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_CH20_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_CH20_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_CH20_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_CH20_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_CH20_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_CH20_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_CH20_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_CH20_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_CH20_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0_CH20_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x354)
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_CH21_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_CH21_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_CH21_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_CH21_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_CH21_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_CH21_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_CH21_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_CH21_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_CH21_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_CH21_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_CH21_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_CH21_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0_CH21_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x358)
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_CH22_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_CH22_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_CH22_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_CH22_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_CH22_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_CH22_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_CH22_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_CH22_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_CH22_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_CH22_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_CH22_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_CH22_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0_CH22_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x35c)
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_CH23_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_CH23_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_CH23_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_CH23_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_CH23_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_CH23_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_CH23_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_CH23_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_CH23_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_CH23_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_CH23_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_CH23_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0_CH23_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x360)
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_CH24_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_CH24_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_CH24_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_CH24_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_CH24_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_CH24_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_CH24_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_CH24_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_CH24_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_CH24_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_CH24_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_CH24_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0_CH24_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x364)
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_CH25_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_CH25_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_CH25_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_CH25_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_CH25_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_CH25_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_CH25_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_CH25_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_CH25_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_CH25_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_CH25_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_CH25_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0_CH25_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x368)
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_CH26_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_CH26_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_CH26_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_CH26_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_CH26_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_CH26_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_CH26_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_CH26_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_CH26_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_CH26_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_CH26_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_CH26_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0_CH26_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x36c)
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_CH27_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_CH27_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_CH27_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_CH27_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_CH27_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_CH27_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_CH27_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_CH27_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_CH27_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_CH27_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_CH27_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_CH27_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0_CH27_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x370)
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_CH28_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_CH28_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_CH28_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_CH28_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_CH28_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_CH28_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_CH28_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_CH28_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_CH28_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_CH28_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_CH28_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_CH28_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0_CH28_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x374)
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_CH29_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_CH29_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_CH29_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_CH29_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_CH29_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_CH29_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_CH29_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_CH29_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_CH29_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_CH29_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_CH29_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_CH29_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0_CH29_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x378)
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_CH30_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_CH30_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_CH30_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_CH30_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_CH30_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_CH30_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_CH30_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_CH30_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_CH30_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_CH30_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_CH30_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_CH30_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0_CH30_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x37c)
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_CH31_STREAM_ID3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_CH31_STREAM_ID3_MASK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_CH31_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_CH31_STREAM_ID3_MASK_RANGE                 31:0
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_CH31_STREAM_ID3_MASK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_CH31_STREAM_ID3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_CH31_STREAM_ID3_MASK_WOFFSET                       0x0
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_CH31_STREAM_ID3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_CH31_STREAM_ID3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_CH31_STREAM_ID3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_CH31_STREAM_ID3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_CH31_STREAM_ID3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0_CH31_STREAM_ID3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0                  MK_ADDR_CONST(0x380)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_SECURE                   0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_DUAL                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_SCR                      SCR_HYPER_0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_SCRREG                   GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_WORD_COUNT                       0x1
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_RANGE                        0:0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_MSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_WOFFSET                      0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_RANGE                        1:1
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_WOFFSET                      0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_RANGE                        2:2
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_MSB                  MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_LSB                  MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_WOFFSET                      0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_SHIFT                        MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_RANGE                        3:3
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_MSB                  MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_LSB                  MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_WOFFSET                      0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_SHIFT                        MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_RANGE                        4:4
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_MSB                  MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_LSB                  MK_SHIFT_CONST(4)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_WOFFSET                      0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_SHIFT                        MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_RANGE                        5:5
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_MSB                  MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_LSB                  MK_SHIFT_CONST(5)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_WOFFSET                      0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_SHIFT                        MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_RANGE                        6:6
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_MSB                  MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_LSB                  MK_SHIFT_CONST(6)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_WOFFSET                      0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_SHIFT                        MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_RANGE                        7:7
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_MSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_LSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_WOFFSET                      0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH8_SHIFT                        MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH8_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH8_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH8_RANGE                        8:8
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH8_MSB                  MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH8_LSB                  MK_SHIFT_CONST(8)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH8_WOFFSET                      0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH8_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH8_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH9_SHIFT                        MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH9_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH9_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH9_RANGE                        9:9
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH9_MSB                  MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH9_LSB                  MK_SHIFT_CONST(9)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH9_WOFFSET                      0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH9_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH9_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH9_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH9_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH9_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH9_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH10_SHIFT                       MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH10_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH10_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH10_RANGE                       10:10
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH10_MSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH10_LSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH10_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH10_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH10_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH10_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH10_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH10_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH10_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH11_SHIFT                       MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH11_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH11_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH11_RANGE                       11:11
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH11_MSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH11_LSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH11_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH11_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH11_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH11_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH11_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH11_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH11_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH12_SHIFT                       MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH12_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH12_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH12_RANGE                       12:12
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH12_MSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH12_LSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH12_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH12_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH12_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH12_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH12_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH12_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH12_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH13_SHIFT                       MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH13_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH13_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH13_RANGE                       13:13
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH13_MSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH13_LSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH13_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH13_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH13_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH13_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH13_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH13_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH13_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH14_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH14_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH14_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH14_RANGE                       14:14
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH14_MSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH14_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH14_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH14_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH14_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH14_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH14_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH14_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH14_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH15_SHIFT                       MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH15_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH15_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH15_RANGE                       15:15
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH15_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH15_LSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH15_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH15_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH15_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH15_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH15_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH15_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH15_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH16_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH16_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH16_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH16_RANGE                       16:16
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH16_MSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH16_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH16_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH16_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH16_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH16_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH16_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH16_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH16_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH17_SHIFT                       MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH17_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH17_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH17_RANGE                       17:17
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH17_MSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH17_LSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH17_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH17_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH17_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH17_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH17_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH17_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH17_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH18_SHIFT                       MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH18_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH18_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH18_RANGE                       18:18
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH18_MSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH18_LSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH18_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH18_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH18_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH18_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH18_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH18_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH18_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH19_SHIFT                       MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH19_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH19_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH19_RANGE                       19:19
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH19_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH19_LSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH19_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH19_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH19_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH19_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH19_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH19_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH19_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH20_SHIFT                       MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH20_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH20_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH20_RANGE                       20:20
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH20_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH20_LSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH20_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH20_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH20_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH20_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH20_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH20_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH20_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH21_SHIFT                       MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH21_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH21_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH21_RANGE                       21:21
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH21_MSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH21_LSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH21_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH21_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH21_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH21_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH21_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH21_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH21_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH22_SHIFT                       MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH22_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH22_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH22_RANGE                       22:22
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH22_MSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH22_LSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH22_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH22_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH22_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH22_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH22_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH22_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH22_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH23_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH23_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH23_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH23_RANGE                       23:23
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH23_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH23_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH23_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH23_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH23_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH23_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH23_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH23_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH23_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH24_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH24_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH24_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH24_RANGE                       24:24
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH24_MSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH24_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH24_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH24_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH24_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH24_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH24_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH24_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH24_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH25_SHIFT                       MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH25_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH25_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH25_RANGE                       25:25
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH25_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH25_LSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH25_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH25_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH25_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH25_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH25_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH25_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH25_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH26_SHIFT                       MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH26_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH26_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH26_RANGE                       26:26
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH26_MSB                 MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH26_LSB                 MK_SHIFT_CONST(26)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH26_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH26_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH26_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH26_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH26_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH26_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH26_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH27_SHIFT                       MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH27_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH27_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH27_RANGE                       27:27
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH27_MSB                 MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH27_LSB                 MK_SHIFT_CONST(27)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH27_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH27_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH27_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH27_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH27_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH27_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH27_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH28_SHIFT                       MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH28_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH28_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH28_RANGE                       28:28
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH28_MSB                 MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH28_LSB                 MK_SHIFT_CONST(28)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH28_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH28_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH28_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH28_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH28_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH28_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH28_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH29_SHIFT                       MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH29_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH29_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH29_RANGE                       29:29
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH29_MSB                 MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH29_LSB                 MK_SHIFT_CONST(29)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH29_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH29_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH29_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH29_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH29_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH29_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH29_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH30_SHIFT                       MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH30_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH30_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH30_RANGE                       30:30
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH30_MSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH30_LSB                 MK_SHIFT_CONST(30)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH30_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH30_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH30_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH30_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH30_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH30_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH30_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH31_SHIFT                       MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH31_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH31_SHIFT)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH31_RANGE                       31:31
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH31_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH31_LSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH31_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH31_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH31_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH31_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH31_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH31_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH31_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0                     MK_ADDR_CONST(0x384)
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_SECURE                      0x0
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_DUAL                        0x0
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_SCR                         0
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_SCRREG                      0
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_SHIFT)
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_RANGE                   0:0
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_MSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_WOFFSET                 0x0
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_DMA_ACTIVE_0
+#define GPCDMA_COMMON_DMA_ACTIVE_0                      MK_ADDR_CONST(0x388)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_SECURE                       0x0
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DUAL                         0x0
+#define GPCDMA_COMMON_DMA_ACTIVE_0_SCR                  0
+#define GPCDMA_COMMON_DMA_ACTIVE_0_SCRREG                       0
+#define GPCDMA_COMMON_DMA_ACTIVE_0_WORD_COUNT                   0x1
+#define GPCDMA_COMMON_DMA_ACTIVE_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_RESET_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_READ_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_SHIFT)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_RANGE                     0:0
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_MSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_WOFFSET                   0x0
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_SHIFT                       MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_SHIFT)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_RANGE                       1:1
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_MSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_LSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_WOFFSET                     0x0
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_SHIFT                  MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_SHIFT)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_RANGE                  2:2
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_MSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_LSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_WOFFSET                        0x0
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_SHIFT                  MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_SHIFT)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_RANGE                  3:3
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_MSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_LSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_WOFFSET                        0x0
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0                        MK_ADDR_CONST(0x390)
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SECURE                         0x0
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_DUAL                   0x0
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SCR                    SCR_SAFETY_0
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SCRREG                         GPCDMA_SCR_SCR_SAFETY_0
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_WORD_COUNT                     0x1
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_RESET_VAL                      MK_MASK_CONST(0x2)
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SAFETY_LOGIC_CLK_DISABLE_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SAFETY_LOGIC_CLK_DISABLE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SAFETY_LOGIC_CLK_DISABLE_SHIFT)
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SAFETY_LOGIC_CLK_DISABLE_RANGE                 1:0
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SAFETY_LOGIC_CLK_DISABLE_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SAFETY_LOGIC_CLK_DISABLE_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SAFETY_LOGIC_CLK_DISABLE_WOFFSET                       0x0
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SAFETY_LOGIC_CLK_DISABLE_DEFAULT                       MK_MASK_CONST(0x2)
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SAFETY_LOGIC_CLK_DISABLE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SAFETY_LOGIC_CLK_DISABLE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SAFETY_LOGIC_CLK_DISABLE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SAFETY_LOGIC_CLK_DISABLE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0_SAFETY_LOGIC_CLK_DISABLE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH0_0
+#define GPCDMA_SCR_SCR_CH0_0                    MK_ADDR_CONST(0xf00)
+#define GPCDMA_SCR_SCR_CH0_0_SECURE                     0x0
+#define GPCDMA_SCR_SCR_CH0_0_DUAL                       0x0
+#define GPCDMA_SCR_SCR_CH0_0_SCR                        0
+#define GPCDMA_SCR_SCR_CH0_0_SCRREG                     0
+#define GPCDMA_SCR_SCR_CH0_0_WORD_COUNT                         0x1
+#define GPCDMA_SCR_SCR_CH0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH0_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_LCK_RANGE                      29:29
+#define GPCDMA_SCR_SCR_CH0_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_LCK_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH0_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_WEN_RANGE                      28:28
+#define GPCDMA_SCR_SCR_CH0_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_WEN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH0_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_REN_RANGE                      27:27
+#define GPCDMA_SCR_SCR_CH0_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_REN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH0_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH0_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_OWNER_RANGE                    26:24
+#define GPCDMA_SCR_SCR_CH0_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_OWNER_WOFFSET                  0x0
+#define GPCDMA_SCR_SCR_CH0_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH0_0_PR7_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_PR7_RANGE                  23:23
+#define GPCDMA_SCR_SCR_CH0_0_PR7_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH0_0_PR7_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH0_0_PR7_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH0_0_PR6_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_PR6_RANGE                  22:22
+#define GPCDMA_SCR_SCR_CH0_0_PR6_MSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH0_0_PR6_LSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH0_0_PR6_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH0_0_PR5_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_PR5_RANGE                  21:21
+#define GPCDMA_SCR_SCR_CH0_0_PR5_MSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH0_0_PR5_LSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH0_0_PR5_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH0_0_PR4_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_PR4_RANGE                  20:20
+#define GPCDMA_SCR_SCR_CH0_0_PR4_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH0_0_PR4_LSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH0_0_PR4_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH0_0_PR3_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_PR3_RANGE                  19:19
+#define GPCDMA_SCR_SCR_CH0_0_PR3_MSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH0_0_PR3_LSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH0_0_PR3_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH0_0_PR2_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_PR2_RANGE                  18:18
+#define GPCDMA_SCR_SCR_CH0_0_PR2_MSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH0_0_PR2_LSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH0_0_PR2_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH0_0_PR1_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_PR1_RANGE                  17:17
+#define GPCDMA_SCR_SCR_CH0_0_PR1_MSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH0_0_PR1_LSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH0_0_PR1_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH0_0_PR0_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_PR0_RANGE                  16:16
+#define GPCDMA_SCR_SCR_CH0_0_PR0_MSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH0_0_PR0_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH0_0_PR0_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH0_0_G7W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_G7W_RANGE                  15:15
+#define GPCDMA_SCR_SCR_CH0_0_G7W_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH0_0_G7W_LSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH0_0_G7W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH0_0_G6W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_G6W_RANGE                  14:14
+#define GPCDMA_SCR_SCR_CH0_0_G6W_MSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH0_0_G6W_LSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH0_0_G6W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH0_0_G5W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_G5W_RANGE                  13:13
+#define GPCDMA_SCR_SCR_CH0_0_G5W_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH0_0_G5W_LSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH0_0_G5W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH0_0_G4W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_G4W_RANGE                  12:12
+#define GPCDMA_SCR_SCR_CH0_0_G4W_MSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH0_0_G4W_LSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH0_0_G4W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH0_0_G3W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_G3W_RANGE                  11:11
+#define GPCDMA_SCR_SCR_CH0_0_G3W_MSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH0_0_G3W_LSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH0_0_G3W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH0_0_G2W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_G2W_RANGE                  10:10
+#define GPCDMA_SCR_SCR_CH0_0_G2W_MSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH0_0_G2W_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH0_0_G2W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH0_0_G1W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_G1W_RANGE                  9:9
+#define GPCDMA_SCR_SCR_CH0_0_G1W_MSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH0_0_G1W_LSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH0_0_G1W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH0_0_G0W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_G0W_RANGE                  8:8
+#define GPCDMA_SCR_SCR_CH0_0_G0W_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH0_0_G0W_LSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH0_0_G0W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH0_0_G7R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_G7R_RANGE                  7:7
+#define GPCDMA_SCR_SCR_CH0_0_G7R_MSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH0_0_G7R_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH0_0_G7R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH0_0_G6R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_G6R_RANGE                  6:6
+#define GPCDMA_SCR_SCR_CH0_0_G6R_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH0_0_G6R_LSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH0_0_G6R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH0_0_G5R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_G5R_RANGE                  5:5
+#define GPCDMA_SCR_SCR_CH0_0_G5R_MSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH0_0_G5R_LSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH0_0_G5R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH0_0_G4R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_G4R_RANGE                  4:4
+#define GPCDMA_SCR_SCR_CH0_0_G4R_MSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH0_0_G4R_LSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH0_0_G4R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH0_0_G3R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_G3R_RANGE                  3:3
+#define GPCDMA_SCR_SCR_CH0_0_G3R_MSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH0_0_G3R_LSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH0_0_G3R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH0_0_G2R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_G2R_RANGE                  2:2
+#define GPCDMA_SCR_SCR_CH0_0_G2R_MSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH0_0_G2R_LSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH0_0_G2R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH0_0_G1R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_G1R_RANGE                  1:1
+#define GPCDMA_SCR_SCR_CH0_0_G1R_MSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH0_0_G1R_LSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH0_0_G1R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH0_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH0_0_G0R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH0_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH0_0_G0R_RANGE                  0:0
+#define GPCDMA_SCR_SCR_CH0_0_G0R_MSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH0_0_G0R_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH0_0_G0R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH0_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH0_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH0_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH1_0
+#define GPCDMA_SCR_SCR_CH1_0                    MK_ADDR_CONST(0xf04)
+#define GPCDMA_SCR_SCR_CH1_0_SECURE                     0x0
+#define GPCDMA_SCR_SCR_CH1_0_DUAL                       0x0
+#define GPCDMA_SCR_SCR_CH1_0_SCR                        0
+#define GPCDMA_SCR_SCR_CH1_0_SCRREG                     0
+#define GPCDMA_SCR_SCR_CH1_0_WORD_COUNT                         0x1
+#define GPCDMA_SCR_SCR_CH1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH1_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_LCK_RANGE                      29:29
+#define GPCDMA_SCR_SCR_CH1_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_LCK_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH1_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_WEN_RANGE                      28:28
+#define GPCDMA_SCR_SCR_CH1_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_WEN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH1_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_REN_RANGE                      27:27
+#define GPCDMA_SCR_SCR_CH1_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_REN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH1_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH1_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_OWNER_RANGE                    26:24
+#define GPCDMA_SCR_SCR_CH1_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_OWNER_WOFFSET                  0x0
+#define GPCDMA_SCR_SCR_CH1_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH1_0_PR7_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_PR7_RANGE                  23:23
+#define GPCDMA_SCR_SCR_CH1_0_PR7_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH1_0_PR7_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH1_0_PR7_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH1_0_PR6_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_PR6_RANGE                  22:22
+#define GPCDMA_SCR_SCR_CH1_0_PR6_MSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH1_0_PR6_LSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH1_0_PR6_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH1_0_PR5_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_PR5_RANGE                  21:21
+#define GPCDMA_SCR_SCR_CH1_0_PR5_MSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH1_0_PR5_LSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH1_0_PR5_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH1_0_PR4_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_PR4_RANGE                  20:20
+#define GPCDMA_SCR_SCR_CH1_0_PR4_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH1_0_PR4_LSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH1_0_PR4_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH1_0_PR3_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_PR3_RANGE                  19:19
+#define GPCDMA_SCR_SCR_CH1_0_PR3_MSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH1_0_PR3_LSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH1_0_PR3_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH1_0_PR2_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_PR2_RANGE                  18:18
+#define GPCDMA_SCR_SCR_CH1_0_PR2_MSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH1_0_PR2_LSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH1_0_PR2_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH1_0_PR1_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_PR1_RANGE                  17:17
+#define GPCDMA_SCR_SCR_CH1_0_PR1_MSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH1_0_PR1_LSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH1_0_PR1_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH1_0_PR0_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_PR0_RANGE                  16:16
+#define GPCDMA_SCR_SCR_CH1_0_PR0_MSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH1_0_PR0_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH1_0_PR0_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH1_0_G7W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_G7W_RANGE                  15:15
+#define GPCDMA_SCR_SCR_CH1_0_G7W_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH1_0_G7W_LSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH1_0_G7W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH1_0_G6W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_G6W_RANGE                  14:14
+#define GPCDMA_SCR_SCR_CH1_0_G6W_MSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH1_0_G6W_LSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH1_0_G6W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH1_0_G5W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_G5W_RANGE                  13:13
+#define GPCDMA_SCR_SCR_CH1_0_G5W_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH1_0_G5W_LSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH1_0_G5W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH1_0_G4W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_G4W_RANGE                  12:12
+#define GPCDMA_SCR_SCR_CH1_0_G4W_MSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH1_0_G4W_LSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH1_0_G4W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH1_0_G3W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_G3W_RANGE                  11:11
+#define GPCDMA_SCR_SCR_CH1_0_G3W_MSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH1_0_G3W_LSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH1_0_G3W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH1_0_G2W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_G2W_RANGE                  10:10
+#define GPCDMA_SCR_SCR_CH1_0_G2W_MSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH1_0_G2W_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH1_0_G2W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH1_0_G1W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_G1W_RANGE                  9:9
+#define GPCDMA_SCR_SCR_CH1_0_G1W_MSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH1_0_G1W_LSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH1_0_G1W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH1_0_G0W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_G0W_RANGE                  8:8
+#define GPCDMA_SCR_SCR_CH1_0_G0W_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH1_0_G0W_LSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH1_0_G0W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH1_0_G7R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_G7R_RANGE                  7:7
+#define GPCDMA_SCR_SCR_CH1_0_G7R_MSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH1_0_G7R_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH1_0_G7R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH1_0_G6R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_G6R_RANGE                  6:6
+#define GPCDMA_SCR_SCR_CH1_0_G6R_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH1_0_G6R_LSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH1_0_G6R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH1_0_G5R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_G5R_RANGE                  5:5
+#define GPCDMA_SCR_SCR_CH1_0_G5R_MSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH1_0_G5R_LSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH1_0_G5R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH1_0_G4R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_G4R_RANGE                  4:4
+#define GPCDMA_SCR_SCR_CH1_0_G4R_MSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH1_0_G4R_LSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH1_0_G4R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH1_0_G3R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_G3R_RANGE                  3:3
+#define GPCDMA_SCR_SCR_CH1_0_G3R_MSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH1_0_G3R_LSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH1_0_G3R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH1_0_G2R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_G2R_RANGE                  2:2
+#define GPCDMA_SCR_SCR_CH1_0_G2R_MSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH1_0_G2R_LSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH1_0_G2R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH1_0_G1R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_G1R_RANGE                  1:1
+#define GPCDMA_SCR_SCR_CH1_0_G1R_MSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH1_0_G1R_LSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH1_0_G1R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH1_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH1_0_G0R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH1_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH1_0_G0R_RANGE                  0:0
+#define GPCDMA_SCR_SCR_CH1_0_G0R_MSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH1_0_G0R_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH1_0_G0R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH1_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH1_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH1_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH2_0
+#define GPCDMA_SCR_SCR_CH2_0                    MK_ADDR_CONST(0xf08)
+#define GPCDMA_SCR_SCR_CH2_0_SECURE                     0x0
+#define GPCDMA_SCR_SCR_CH2_0_DUAL                       0x0
+#define GPCDMA_SCR_SCR_CH2_0_SCR                        0
+#define GPCDMA_SCR_SCR_CH2_0_SCRREG                     0
+#define GPCDMA_SCR_SCR_CH2_0_WORD_COUNT                         0x1
+#define GPCDMA_SCR_SCR_CH2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH2_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_LCK_RANGE                      29:29
+#define GPCDMA_SCR_SCR_CH2_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_LCK_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH2_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_WEN_RANGE                      28:28
+#define GPCDMA_SCR_SCR_CH2_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_WEN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH2_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_REN_RANGE                      27:27
+#define GPCDMA_SCR_SCR_CH2_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_REN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH2_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH2_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_OWNER_RANGE                    26:24
+#define GPCDMA_SCR_SCR_CH2_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_OWNER_WOFFSET                  0x0
+#define GPCDMA_SCR_SCR_CH2_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH2_0_PR7_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_PR7_RANGE                  23:23
+#define GPCDMA_SCR_SCR_CH2_0_PR7_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH2_0_PR7_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH2_0_PR7_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH2_0_PR6_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_PR6_RANGE                  22:22
+#define GPCDMA_SCR_SCR_CH2_0_PR6_MSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH2_0_PR6_LSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH2_0_PR6_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH2_0_PR5_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_PR5_RANGE                  21:21
+#define GPCDMA_SCR_SCR_CH2_0_PR5_MSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH2_0_PR5_LSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH2_0_PR5_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH2_0_PR4_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_PR4_RANGE                  20:20
+#define GPCDMA_SCR_SCR_CH2_0_PR4_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH2_0_PR4_LSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH2_0_PR4_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH2_0_PR3_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_PR3_RANGE                  19:19
+#define GPCDMA_SCR_SCR_CH2_0_PR3_MSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH2_0_PR3_LSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH2_0_PR3_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH2_0_PR2_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_PR2_RANGE                  18:18
+#define GPCDMA_SCR_SCR_CH2_0_PR2_MSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH2_0_PR2_LSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH2_0_PR2_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH2_0_PR1_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_PR1_RANGE                  17:17
+#define GPCDMA_SCR_SCR_CH2_0_PR1_MSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH2_0_PR1_LSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH2_0_PR1_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH2_0_PR0_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_PR0_RANGE                  16:16
+#define GPCDMA_SCR_SCR_CH2_0_PR0_MSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH2_0_PR0_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH2_0_PR0_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH2_0_G7W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_G7W_RANGE                  15:15
+#define GPCDMA_SCR_SCR_CH2_0_G7W_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH2_0_G7W_LSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH2_0_G7W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH2_0_G6W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_G6W_RANGE                  14:14
+#define GPCDMA_SCR_SCR_CH2_0_G6W_MSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH2_0_G6W_LSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH2_0_G6W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH2_0_G5W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_G5W_RANGE                  13:13
+#define GPCDMA_SCR_SCR_CH2_0_G5W_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH2_0_G5W_LSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH2_0_G5W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH2_0_G4W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_G4W_RANGE                  12:12
+#define GPCDMA_SCR_SCR_CH2_0_G4W_MSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH2_0_G4W_LSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH2_0_G4W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH2_0_G3W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_G3W_RANGE                  11:11
+#define GPCDMA_SCR_SCR_CH2_0_G3W_MSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH2_0_G3W_LSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH2_0_G3W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH2_0_G2W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_G2W_RANGE                  10:10
+#define GPCDMA_SCR_SCR_CH2_0_G2W_MSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH2_0_G2W_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH2_0_G2W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH2_0_G1W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_G1W_RANGE                  9:9
+#define GPCDMA_SCR_SCR_CH2_0_G1W_MSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH2_0_G1W_LSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH2_0_G1W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH2_0_G0W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_G0W_RANGE                  8:8
+#define GPCDMA_SCR_SCR_CH2_0_G0W_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH2_0_G0W_LSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH2_0_G0W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH2_0_G7R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_G7R_RANGE                  7:7
+#define GPCDMA_SCR_SCR_CH2_0_G7R_MSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH2_0_G7R_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH2_0_G7R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH2_0_G6R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_G6R_RANGE                  6:6
+#define GPCDMA_SCR_SCR_CH2_0_G6R_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH2_0_G6R_LSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH2_0_G6R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH2_0_G5R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_G5R_RANGE                  5:5
+#define GPCDMA_SCR_SCR_CH2_0_G5R_MSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH2_0_G5R_LSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH2_0_G5R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH2_0_G4R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_G4R_RANGE                  4:4
+#define GPCDMA_SCR_SCR_CH2_0_G4R_MSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH2_0_G4R_LSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH2_0_G4R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH2_0_G3R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_G3R_RANGE                  3:3
+#define GPCDMA_SCR_SCR_CH2_0_G3R_MSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH2_0_G3R_LSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH2_0_G3R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH2_0_G2R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_G2R_RANGE                  2:2
+#define GPCDMA_SCR_SCR_CH2_0_G2R_MSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH2_0_G2R_LSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH2_0_G2R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH2_0_G1R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_G1R_RANGE                  1:1
+#define GPCDMA_SCR_SCR_CH2_0_G1R_MSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH2_0_G1R_LSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH2_0_G1R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH2_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH2_0_G0R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH2_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH2_0_G0R_RANGE                  0:0
+#define GPCDMA_SCR_SCR_CH2_0_G0R_MSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH2_0_G0R_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH2_0_G0R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH2_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH2_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH2_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH3_0
+#define GPCDMA_SCR_SCR_CH3_0                    MK_ADDR_CONST(0xf0c)
+#define GPCDMA_SCR_SCR_CH3_0_SECURE                     0x0
+#define GPCDMA_SCR_SCR_CH3_0_DUAL                       0x0
+#define GPCDMA_SCR_SCR_CH3_0_SCR                        0
+#define GPCDMA_SCR_SCR_CH3_0_SCRREG                     0
+#define GPCDMA_SCR_SCR_CH3_0_WORD_COUNT                         0x1
+#define GPCDMA_SCR_SCR_CH3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH3_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_LCK_RANGE                      29:29
+#define GPCDMA_SCR_SCR_CH3_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_LCK_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH3_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_WEN_RANGE                      28:28
+#define GPCDMA_SCR_SCR_CH3_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_WEN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH3_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_REN_RANGE                      27:27
+#define GPCDMA_SCR_SCR_CH3_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_REN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH3_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH3_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_OWNER_RANGE                    26:24
+#define GPCDMA_SCR_SCR_CH3_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_OWNER_WOFFSET                  0x0
+#define GPCDMA_SCR_SCR_CH3_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH3_0_PR7_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_PR7_RANGE                  23:23
+#define GPCDMA_SCR_SCR_CH3_0_PR7_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH3_0_PR7_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH3_0_PR7_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH3_0_PR6_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_PR6_RANGE                  22:22
+#define GPCDMA_SCR_SCR_CH3_0_PR6_MSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH3_0_PR6_LSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH3_0_PR6_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH3_0_PR5_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_PR5_RANGE                  21:21
+#define GPCDMA_SCR_SCR_CH3_0_PR5_MSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH3_0_PR5_LSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH3_0_PR5_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH3_0_PR4_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_PR4_RANGE                  20:20
+#define GPCDMA_SCR_SCR_CH3_0_PR4_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH3_0_PR4_LSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH3_0_PR4_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH3_0_PR3_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_PR3_RANGE                  19:19
+#define GPCDMA_SCR_SCR_CH3_0_PR3_MSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH3_0_PR3_LSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH3_0_PR3_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH3_0_PR2_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_PR2_RANGE                  18:18
+#define GPCDMA_SCR_SCR_CH3_0_PR2_MSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH3_0_PR2_LSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH3_0_PR2_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH3_0_PR1_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_PR1_RANGE                  17:17
+#define GPCDMA_SCR_SCR_CH3_0_PR1_MSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH3_0_PR1_LSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH3_0_PR1_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH3_0_PR0_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_PR0_RANGE                  16:16
+#define GPCDMA_SCR_SCR_CH3_0_PR0_MSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH3_0_PR0_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH3_0_PR0_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH3_0_G7W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_G7W_RANGE                  15:15
+#define GPCDMA_SCR_SCR_CH3_0_G7W_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH3_0_G7W_LSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH3_0_G7W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH3_0_G6W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_G6W_RANGE                  14:14
+#define GPCDMA_SCR_SCR_CH3_0_G6W_MSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH3_0_G6W_LSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH3_0_G6W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH3_0_G5W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_G5W_RANGE                  13:13
+#define GPCDMA_SCR_SCR_CH3_0_G5W_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH3_0_G5W_LSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH3_0_G5W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH3_0_G4W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_G4W_RANGE                  12:12
+#define GPCDMA_SCR_SCR_CH3_0_G4W_MSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH3_0_G4W_LSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH3_0_G4W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH3_0_G3W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_G3W_RANGE                  11:11
+#define GPCDMA_SCR_SCR_CH3_0_G3W_MSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH3_0_G3W_LSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH3_0_G3W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH3_0_G2W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_G2W_RANGE                  10:10
+#define GPCDMA_SCR_SCR_CH3_0_G2W_MSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH3_0_G2W_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH3_0_G2W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH3_0_G1W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_G1W_RANGE                  9:9
+#define GPCDMA_SCR_SCR_CH3_0_G1W_MSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH3_0_G1W_LSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH3_0_G1W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH3_0_G0W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_G0W_RANGE                  8:8
+#define GPCDMA_SCR_SCR_CH3_0_G0W_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH3_0_G0W_LSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH3_0_G0W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH3_0_G7R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_G7R_RANGE                  7:7
+#define GPCDMA_SCR_SCR_CH3_0_G7R_MSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH3_0_G7R_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH3_0_G7R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH3_0_G6R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_G6R_RANGE                  6:6
+#define GPCDMA_SCR_SCR_CH3_0_G6R_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH3_0_G6R_LSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH3_0_G6R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH3_0_G5R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_G5R_RANGE                  5:5
+#define GPCDMA_SCR_SCR_CH3_0_G5R_MSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH3_0_G5R_LSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH3_0_G5R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH3_0_G4R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_G4R_RANGE                  4:4
+#define GPCDMA_SCR_SCR_CH3_0_G4R_MSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH3_0_G4R_LSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH3_0_G4R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH3_0_G3R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_G3R_RANGE                  3:3
+#define GPCDMA_SCR_SCR_CH3_0_G3R_MSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH3_0_G3R_LSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH3_0_G3R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH3_0_G2R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_G2R_RANGE                  2:2
+#define GPCDMA_SCR_SCR_CH3_0_G2R_MSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH3_0_G2R_LSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH3_0_G2R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH3_0_G1R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_G1R_RANGE                  1:1
+#define GPCDMA_SCR_SCR_CH3_0_G1R_MSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH3_0_G1R_LSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH3_0_G1R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH3_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH3_0_G0R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH3_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH3_0_G0R_RANGE                  0:0
+#define GPCDMA_SCR_SCR_CH3_0_G0R_MSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH3_0_G0R_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH3_0_G0R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH3_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH3_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH3_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH4_0
+#define GPCDMA_SCR_SCR_CH4_0                    MK_ADDR_CONST(0xf10)
+#define GPCDMA_SCR_SCR_CH4_0_SECURE                     0x0
+#define GPCDMA_SCR_SCR_CH4_0_DUAL                       0x0
+#define GPCDMA_SCR_SCR_CH4_0_SCR                        0
+#define GPCDMA_SCR_SCR_CH4_0_SCRREG                     0
+#define GPCDMA_SCR_SCR_CH4_0_WORD_COUNT                         0x1
+#define GPCDMA_SCR_SCR_CH4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH4_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_LCK_RANGE                      29:29
+#define GPCDMA_SCR_SCR_CH4_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_LCK_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH4_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_WEN_RANGE                      28:28
+#define GPCDMA_SCR_SCR_CH4_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_WEN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH4_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_REN_RANGE                      27:27
+#define GPCDMA_SCR_SCR_CH4_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_REN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH4_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH4_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_OWNER_RANGE                    26:24
+#define GPCDMA_SCR_SCR_CH4_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_OWNER_WOFFSET                  0x0
+#define GPCDMA_SCR_SCR_CH4_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH4_0_PR7_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_PR7_RANGE                  23:23
+#define GPCDMA_SCR_SCR_CH4_0_PR7_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH4_0_PR7_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH4_0_PR7_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH4_0_PR6_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_PR6_RANGE                  22:22
+#define GPCDMA_SCR_SCR_CH4_0_PR6_MSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH4_0_PR6_LSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH4_0_PR6_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH4_0_PR5_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_PR5_RANGE                  21:21
+#define GPCDMA_SCR_SCR_CH4_0_PR5_MSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH4_0_PR5_LSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH4_0_PR5_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH4_0_PR4_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_PR4_RANGE                  20:20
+#define GPCDMA_SCR_SCR_CH4_0_PR4_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH4_0_PR4_LSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH4_0_PR4_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH4_0_PR3_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_PR3_RANGE                  19:19
+#define GPCDMA_SCR_SCR_CH4_0_PR3_MSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH4_0_PR3_LSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH4_0_PR3_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH4_0_PR2_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_PR2_RANGE                  18:18
+#define GPCDMA_SCR_SCR_CH4_0_PR2_MSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH4_0_PR2_LSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH4_0_PR2_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH4_0_PR1_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_PR1_RANGE                  17:17
+#define GPCDMA_SCR_SCR_CH4_0_PR1_MSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH4_0_PR1_LSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH4_0_PR1_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH4_0_PR0_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_PR0_RANGE                  16:16
+#define GPCDMA_SCR_SCR_CH4_0_PR0_MSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH4_0_PR0_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH4_0_PR0_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH4_0_G7W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_G7W_RANGE                  15:15
+#define GPCDMA_SCR_SCR_CH4_0_G7W_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH4_0_G7W_LSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH4_0_G7W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH4_0_G6W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_G6W_RANGE                  14:14
+#define GPCDMA_SCR_SCR_CH4_0_G6W_MSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH4_0_G6W_LSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH4_0_G6W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH4_0_G5W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_G5W_RANGE                  13:13
+#define GPCDMA_SCR_SCR_CH4_0_G5W_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH4_0_G5W_LSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH4_0_G5W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH4_0_G4W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_G4W_RANGE                  12:12
+#define GPCDMA_SCR_SCR_CH4_0_G4W_MSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH4_0_G4W_LSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH4_0_G4W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH4_0_G3W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_G3W_RANGE                  11:11
+#define GPCDMA_SCR_SCR_CH4_0_G3W_MSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH4_0_G3W_LSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH4_0_G3W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH4_0_G2W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_G2W_RANGE                  10:10
+#define GPCDMA_SCR_SCR_CH4_0_G2W_MSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH4_0_G2W_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH4_0_G2W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH4_0_G1W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_G1W_RANGE                  9:9
+#define GPCDMA_SCR_SCR_CH4_0_G1W_MSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH4_0_G1W_LSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH4_0_G1W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH4_0_G0W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_G0W_RANGE                  8:8
+#define GPCDMA_SCR_SCR_CH4_0_G0W_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH4_0_G0W_LSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH4_0_G0W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH4_0_G7R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_G7R_RANGE                  7:7
+#define GPCDMA_SCR_SCR_CH4_0_G7R_MSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH4_0_G7R_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH4_0_G7R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH4_0_G6R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_G6R_RANGE                  6:6
+#define GPCDMA_SCR_SCR_CH4_0_G6R_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH4_0_G6R_LSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH4_0_G6R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH4_0_G5R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_G5R_RANGE                  5:5
+#define GPCDMA_SCR_SCR_CH4_0_G5R_MSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH4_0_G5R_LSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH4_0_G5R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH4_0_G4R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_G4R_RANGE                  4:4
+#define GPCDMA_SCR_SCR_CH4_0_G4R_MSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH4_0_G4R_LSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH4_0_G4R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH4_0_G3R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_G3R_RANGE                  3:3
+#define GPCDMA_SCR_SCR_CH4_0_G3R_MSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH4_0_G3R_LSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH4_0_G3R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH4_0_G2R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_G2R_RANGE                  2:2
+#define GPCDMA_SCR_SCR_CH4_0_G2R_MSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH4_0_G2R_LSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH4_0_G2R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH4_0_G1R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_G1R_RANGE                  1:1
+#define GPCDMA_SCR_SCR_CH4_0_G1R_MSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH4_0_G1R_LSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH4_0_G1R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH4_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH4_0_G0R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH4_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH4_0_G0R_RANGE                  0:0
+#define GPCDMA_SCR_SCR_CH4_0_G0R_MSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH4_0_G0R_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH4_0_G0R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH4_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH4_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH4_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH5_0
+#define GPCDMA_SCR_SCR_CH5_0                    MK_ADDR_CONST(0xf14)
+#define GPCDMA_SCR_SCR_CH5_0_SECURE                     0x0
+#define GPCDMA_SCR_SCR_CH5_0_DUAL                       0x0
+#define GPCDMA_SCR_SCR_CH5_0_SCR                        0
+#define GPCDMA_SCR_SCR_CH5_0_SCRREG                     0
+#define GPCDMA_SCR_SCR_CH5_0_WORD_COUNT                         0x1
+#define GPCDMA_SCR_SCR_CH5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH5_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_LCK_RANGE                      29:29
+#define GPCDMA_SCR_SCR_CH5_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_LCK_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH5_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_WEN_RANGE                      28:28
+#define GPCDMA_SCR_SCR_CH5_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_WEN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH5_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_REN_RANGE                      27:27
+#define GPCDMA_SCR_SCR_CH5_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_REN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH5_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH5_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_OWNER_RANGE                    26:24
+#define GPCDMA_SCR_SCR_CH5_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_OWNER_WOFFSET                  0x0
+#define GPCDMA_SCR_SCR_CH5_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH5_0_PR7_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_PR7_RANGE                  23:23
+#define GPCDMA_SCR_SCR_CH5_0_PR7_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH5_0_PR7_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH5_0_PR7_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH5_0_PR6_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_PR6_RANGE                  22:22
+#define GPCDMA_SCR_SCR_CH5_0_PR6_MSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH5_0_PR6_LSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH5_0_PR6_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH5_0_PR5_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_PR5_RANGE                  21:21
+#define GPCDMA_SCR_SCR_CH5_0_PR5_MSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH5_0_PR5_LSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH5_0_PR5_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH5_0_PR4_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_PR4_RANGE                  20:20
+#define GPCDMA_SCR_SCR_CH5_0_PR4_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH5_0_PR4_LSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH5_0_PR4_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH5_0_PR3_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_PR3_RANGE                  19:19
+#define GPCDMA_SCR_SCR_CH5_0_PR3_MSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH5_0_PR3_LSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH5_0_PR3_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH5_0_PR2_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_PR2_RANGE                  18:18
+#define GPCDMA_SCR_SCR_CH5_0_PR2_MSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH5_0_PR2_LSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH5_0_PR2_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH5_0_PR1_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_PR1_RANGE                  17:17
+#define GPCDMA_SCR_SCR_CH5_0_PR1_MSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH5_0_PR1_LSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH5_0_PR1_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH5_0_PR0_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_PR0_RANGE                  16:16
+#define GPCDMA_SCR_SCR_CH5_0_PR0_MSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH5_0_PR0_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH5_0_PR0_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH5_0_G7W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_G7W_RANGE                  15:15
+#define GPCDMA_SCR_SCR_CH5_0_G7W_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH5_0_G7W_LSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH5_0_G7W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH5_0_G6W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_G6W_RANGE                  14:14
+#define GPCDMA_SCR_SCR_CH5_0_G6W_MSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH5_0_G6W_LSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH5_0_G6W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH5_0_G5W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_G5W_RANGE                  13:13
+#define GPCDMA_SCR_SCR_CH5_0_G5W_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH5_0_G5W_LSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH5_0_G5W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH5_0_G4W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_G4W_RANGE                  12:12
+#define GPCDMA_SCR_SCR_CH5_0_G4W_MSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH5_0_G4W_LSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH5_0_G4W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH5_0_G3W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_G3W_RANGE                  11:11
+#define GPCDMA_SCR_SCR_CH5_0_G3W_MSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH5_0_G3W_LSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH5_0_G3W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH5_0_G2W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_G2W_RANGE                  10:10
+#define GPCDMA_SCR_SCR_CH5_0_G2W_MSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH5_0_G2W_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH5_0_G2W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH5_0_G1W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_G1W_RANGE                  9:9
+#define GPCDMA_SCR_SCR_CH5_0_G1W_MSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH5_0_G1W_LSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH5_0_G1W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH5_0_G0W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_G0W_RANGE                  8:8
+#define GPCDMA_SCR_SCR_CH5_0_G0W_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH5_0_G0W_LSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH5_0_G0W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH5_0_G7R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_G7R_RANGE                  7:7
+#define GPCDMA_SCR_SCR_CH5_0_G7R_MSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH5_0_G7R_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH5_0_G7R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH5_0_G6R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_G6R_RANGE                  6:6
+#define GPCDMA_SCR_SCR_CH5_0_G6R_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH5_0_G6R_LSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH5_0_G6R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH5_0_G5R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_G5R_RANGE                  5:5
+#define GPCDMA_SCR_SCR_CH5_0_G5R_MSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH5_0_G5R_LSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH5_0_G5R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH5_0_G4R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_G4R_RANGE                  4:4
+#define GPCDMA_SCR_SCR_CH5_0_G4R_MSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH5_0_G4R_LSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH5_0_G4R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH5_0_G3R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_G3R_RANGE                  3:3
+#define GPCDMA_SCR_SCR_CH5_0_G3R_MSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH5_0_G3R_LSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH5_0_G3R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH5_0_G2R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_G2R_RANGE                  2:2
+#define GPCDMA_SCR_SCR_CH5_0_G2R_MSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH5_0_G2R_LSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH5_0_G2R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH5_0_G1R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_G1R_RANGE                  1:1
+#define GPCDMA_SCR_SCR_CH5_0_G1R_MSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH5_0_G1R_LSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH5_0_G1R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH5_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH5_0_G0R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH5_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH5_0_G0R_RANGE                  0:0
+#define GPCDMA_SCR_SCR_CH5_0_G0R_MSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH5_0_G0R_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH5_0_G0R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH5_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH5_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH5_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH6_0
+#define GPCDMA_SCR_SCR_CH6_0                    MK_ADDR_CONST(0xf18)
+#define GPCDMA_SCR_SCR_CH6_0_SECURE                     0x0
+#define GPCDMA_SCR_SCR_CH6_0_DUAL                       0x0
+#define GPCDMA_SCR_SCR_CH6_0_SCR                        0
+#define GPCDMA_SCR_SCR_CH6_0_SCRREG                     0
+#define GPCDMA_SCR_SCR_CH6_0_WORD_COUNT                         0x1
+#define GPCDMA_SCR_SCR_CH6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH6_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_LCK_RANGE                      29:29
+#define GPCDMA_SCR_SCR_CH6_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_LCK_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH6_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_WEN_RANGE                      28:28
+#define GPCDMA_SCR_SCR_CH6_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_WEN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH6_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_REN_RANGE                      27:27
+#define GPCDMA_SCR_SCR_CH6_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_REN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH6_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH6_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_OWNER_RANGE                    26:24
+#define GPCDMA_SCR_SCR_CH6_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_OWNER_WOFFSET                  0x0
+#define GPCDMA_SCR_SCR_CH6_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH6_0_PR7_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_PR7_RANGE                  23:23
+#define GPCDMA_SCR_SCR_CH6_0_PR7_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH6_0_PR7_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH6_0_PR7_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH6_0_PR6_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_PR6_RANGE                  22:22
+#define GPCDMA_SCR_SCR_CH6_0_PR6_MSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH6_0_PR6_LSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH6_0_PR6_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH6_0_PR5_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_PR5_RANGE                  21:21
+#define GPCDMA_SCR_SCR_CH6_0_PR5_MSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH6_0_PR5_LSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH6_0_PR5_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH6_0_PR4_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_PR4_RANGE                  20:20
+#define GPCDMA_SCR_SCR_CH6_0_PR4_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH6_0_PR4_LSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH6_0_PR4_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH6_0_PR3_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_PR3_RANGE                  19:19
+#define GPCDMA_SCR_SCR_CH6_0_PR3_MSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH6_0_PR3_LSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH6_0_PR3_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH6_0_PR2_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_PR2_RANGE                  18:18
+#define GPCDMA_SCR_SCR_CH6_0_PR2_MSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH6_0_PR2_LSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH6_0_PR2_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH6_0_PR1_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_PR1_RANGE                  17:17
+#define GPCDMA_SCR_SCR_CH6_0_PR1_MSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH6_0_PR1_LSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH6_0_PR1_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH6_0_PR0_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_PR0_RANGE                  16:16
+#define GPCDMA_SCR_SCR_CH6_0_PR0_MSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH6_0_PR0_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH6_0_PR0_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH6_0_G7W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_G7W_RANGE                  15:15
+#define GPCDMA_SCR_SCR_CH6_0_G7W_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH6_0_G7W_LSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH6_0_G7W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH6_0_G6W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_G6W_RANGE                  14:14
+#define GPCDMA_SCR_SCR_CH6_0_G6W_MSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH6_0_G6W_LSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH6_0_G6W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH6_0_G5W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_G5W_RANGE                  13:13
+#define GPCDMA_SCR_SCR_CH6_0_G5W_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH6_0_G5W_LSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH6_0_G5W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH6_0_G4W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_G4W_RANGE                  12:12
+#define GPCDMA_SCR_SCR_CH6_0_G4W_MSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH6_0_G4W_LSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH6_0_G4W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH6_0_G3W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_G3W_RANGE                  11:11
+#define GPCDMA_SCR_SCR_CH6_0_G3W_MSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH6_0_G3W_LSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH6_0_G3W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH6_0_G2W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_G2W_RANGE                  10:10
+#define GPCDMA_SCR_SCR_CH6_0_G2W_MSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH6_0_G2W_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH6_0_G2W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH6_0_G1W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_G1W_RANGE                  9:9
+#define GPCDMA_SCR_SCR_CH6_0_G1W_MSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH6_0_G1W_LSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH6_0_G1W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH6_0_G0W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_G0W_RANGE                  8:8
+#define GPCDMA_SCR_SCR_CH6_0_G0W_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH6_0_G0W_LSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH6_0_G0W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH6_0_G7R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_G7R_RANGE                  7:7
+#define GPCDMA_SCR_SCR_CH6_0_G7R_MSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH6_0_G7R_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH6_0_G7R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH6_0_G6R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_G6R_RANGE                  6:6
+#define GPCDMA_SCR_SCR_CH6_0_G6R_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH6_0_G6R_LSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH6_0_G6R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH6_0_G5R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_G5R_RANGE                  5:5
+#define GPCDMA_SCR_SCR_CH6_0_G5R_MSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH6_0_G5R_LSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH6_0_G5R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH6_0_G4R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_G4R_RANGE                  4:4
+#define GPCDMA_SCR_SCR_CH6_0_G4R_MSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH6_0_G4R_LSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH6_0_G4R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH6_0_G3R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_G3R_RANGE                  3:3
+#define GPCDMA_SCR_SCR_CH6_0_G3R_MSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH6_0_G3R_LSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH6_0_G3R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH6_0_G2R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_G2R_RANGE                  2:2
+#define GPCDMA_SCR_SCR_CH6_0_G2R_MSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH6_0_G2R_LSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH6_0_G2R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH6_0_G1R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_G1R_RANGE                  1:1
+#define GPCDMA_SCR_SCR_CH6_0_G1R_MSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH6_0_G1R_LSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH6_0_G1R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH6_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH6_0_G0R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH6_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH6_0_G0R_RANGE                  0:0
+#define GPCDMA_SCR_SCR_CH6_0_G0R_MSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH6_0_G0R_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH6_0_G0R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH6_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH6_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH6_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH7_0
+#define GPCDMA_SCR_SCR_CH7_0                    MK_ADDR_CONST(0xf1c)
+#define GPCDMA_SCR_SCR_CH7_0_SECURE                     0x0
+#define GPCDMA_SCR_SCR_CH7_0_DUAL                       0x0
+#define GPCDMA_SCR_SCR_CH7_0_SCR                        0
+#define GPCDMA_SCR_SCR_CH7_0_SCRREG                     0
+#define GPCDMA_SCR_SCR_CH7_0_WORD_COUNT                         0x1
+#define GPCDMA_SCR_SCR_CH7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH7_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_LCK_RANGE                      29:29
+#define GPCDMA_SCR_SCR_CH7_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_LCK_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH7_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_WEN_RANGE                      28:28
+#define GPCDMA_SCR_SCR_CH7_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_WEN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH7_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_REN_RANGE                      27:27
+#define GPCDMA_SCR_SCR_CH7_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_REN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH7_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH7_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_OWNER_RANGE                    26:24
+#define GPCDMA_SCR_SCR_CH7_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_OWNER_WOFFSET                  0x0
+#define GPCDMA_SCR_SCR_CH7_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH7_0_PR7_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_PR7_RANGE                  23:23
+#define GPCDMA_SCR_SCR_CH7_0_PR7_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH7_0_PR7_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH7_0_PR7_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH7_0_PR6_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_PR6_RANGE                  22:22
+#define GPCDMA_SCR_SCR_CH7_0_PR6_MSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH7_0_PR6_LSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH7_0_PR6_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH7_0_PR5_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_PR5_RANGE                  21:21
+#define GPCDMA_SCR_SCR_CH7_0_PR5_MSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH7_0_PR5_LSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH7_0_PR5_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH7_0_PR4_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_PR4_RANGE                  20:20
+#define GPCDMA_SCR_SCR_CH7_0_PR4_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH7_0_PR4_LSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH7_0_PR4_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH7_0_PR3_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_PR3_RANGE                  19:19
+#define GPCDMA_SCR_SCR_CH7_0_PR3_MSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH7_0_PR3_LSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH7_0_PR3_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH7_0_PR2_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_PR2_RANGE                  18:18
+#define GPCDMA_SCR_SCR_CH7_0_PR2_MSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH7_0_PR2_LSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH7_0_PR2_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH7_0_PR1_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_PR1_RANGE                  17:17
+#define GPCDMA_SCR_SCR_CH7_0_PR1_MSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH7_0_PR1_LSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH7_0_PR1_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH7_0_PR0_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_PR0_RANGE                  16:16
+#define GPCDMA_SCR_SCR_CH7_0_PR0_MSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH7_0_PR0_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH7_0_PR0_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH7_0_G7W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_G7W_RANGE                  15:15
+#define GPCDMA_SCR_SCR_CH7_0_G7W_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH7_0_G7W_LSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH7_0_G7W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH7_0_G6W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_G6W_RANGE                  14:14
+#define GPCDMA_SCR_SCR_CH7_0_G6W_MSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH7_0_G6W_LSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH7_0_G6W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH7_0_G5W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_G5W_RANGE                  13:13
+#define GPCDMA_SCR_SCR_CH7_0_G5W_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH7_0_G5W_LSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH7_0_G5W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH7_0_G4W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_G4W_RANGE                  12:12
+#define GPCDMA_SCR_SCR_CH7_0_G4W_MSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH7_0_G4W_LSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH7_0_G4W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH7_0_G3W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_G3W_RANGE                  11:11
+#define GPCDMA_SCR_SCR_CH7_0_G3W_MSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH7_0_G3W_LSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH7_0_G3W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH7_0_G2W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_G2W_RANGE                  10:10
+#define GPCDMA_SCR_SCR_CH7_0_G2W_MSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH7_0_G2W_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH7_0_G2W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH7_0_G1W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_G1W_RANGE                  9:9
+#define GPCDMA_SCR_SCR_CH7_0_G1W_MSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH7_0_G1W_LSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH7_0_G1W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH7_0_G0W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_G0W_RANGE                  8:8
+#define GPCDMA_SCR_SCR_CH7_0_G0W_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH7_0_G0W_LSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH7_0_G0W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH7_0_G7R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_G7R_RANGE                  7:7
+#define GPCDMA_SCR_SCR_CH7_0_G7R_MSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH7_0_G7R_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH7_0_G7R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH7_0_G6R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_G6R_RANGE                  6:6
+#define GPCDMA_SCR_SCR_CH7_0_G6R_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH7_0_G6R_LSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH7_0_G6R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH7_0_G5R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_G5R_RANGE                  5:5
+#define GPCDMA_SCR_SCR_CH7_0_G5R_MSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH7_0_G5R_LSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH7_0_G5R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH7_0_G4R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_G4R_RANGE                  4:4
+#define GPCDMA_SCR_SCR_CH7_0_G4R_MSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH7_0_G4R_LSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH7_0_G4R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH7_0_G3R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_G3R_RANGE                  3:3
+#define GPCDMA_SCR_SCR_CH7_0_G3R_MSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH7_0_G3R_LSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH7_0_G3R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH7_0_G2R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_G2R_RANGE                  2:2
+#define GPCDMA_SCR_SCR_CH7_0_G2R_MSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH7_0_G2R_LSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH7_0_G2R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH7_0_G1R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_G1R_RANGE                  1:1
+#define GPCDMA_SCR_SCR_CH7_0_G1R_MSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH7_0_G1R_LSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH7_0_G1R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH7_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH7_0_G0R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH7_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH7_0_G0R_RANGE                  0:0
+#define GPCDMA_SCR_SCR_CH7_0_G0R_MSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH7_0_G0R_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH7_0_G0R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH7_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH7_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH7_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH8_0
+#define GPCDMA_SCR_SCR_CH8_0                    MK_ADDR_CONST(0xf20)
+#define GPCDMA_SCR_SCR_CH8_0_SECURE                     0x0
+#define GPCDMA_SCR_SCR_CH8_0_DUAL                       0x0
+#define GPCDMA_SCR_SCR_CH8_0_SCR                        0
+#define GPCDMA_SCR_SCR_CH8_0_SCRREG                     0
+#define GPCDMA_SCR_SCR_CH8_0_WORD_COUNT                         0x1
+#define GPCDMA_SCR_SCR_CH8_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH8_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH8_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_LCK_RANGE                      29:29
+#define GPCDMA_SCR_SCR_CH8_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_LCK_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH8_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_WEN_RANGE                      28:28
+#define GPCDMA_SCR_SCR_CH8_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_WEN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH8_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_REN_RANGE                      27:27
+#define GPCDMA_SCR_SCR_CH8_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_REN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH8_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH8_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_OWNER_RANGE                    26:24
+#define GPCDMA_SCR_SCR_CH8_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_OWNER_WOFFSET                  0x0
+#define GPCDMA_SCR_SCR_CH8_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH8_0_PR7_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_PR7_RANGE                  23:23
+#define GPCDMA_SCR_SCR_CH8_0_PR7_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH8_0_PR7_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH8_0_PR7_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH8_0_PR6_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_PR6_RANGE                  22:22
+#define GPCDMA_SCR_SCR_CH8_0_PR6_MSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH8_0_PR6_LSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH8_0_PR6_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH8_0_PR5_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_PR5_RANGE                  21:21
+#define GPCDMA_SCR_SCR_CH8_0_PR5_MSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH8_0_PR5_LSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH8_0_PR5_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH8_0_PR4_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_PR4_RANGE                  20:20
+#define GPCDMA_SCR_SCR_CH8_0_PR4_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH8_0_PR4_LSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH8_0_PR4_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH8_0_PR3_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_PR3_RANGE                  19:19
+#define GPCDMA_SCR_SCR_CH8_0_PR3_MSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH8_0_PR3_LSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH8_0_PR3_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH8_0_PR2_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_PR2_RANGE                  18:18
+#define GPCDMA_SCR_SCR_CH8_0_PR2_MSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH8_0_PR2_LSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH8_0_PR2_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH8_0_PR1_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_PR1_RANGE                  17:17
+#define GPCDMA_SCR_SCR_CH8_0_PR1_MSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH8_0_PR1_LSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH8_0_PR1_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH8_0_PR0_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_PR0_RANGE                  16:16
+#define GPCDMA_SCR_SCR_CH8_0_PR0_MSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH8_0_PR0_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH8_0_PR0_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH8_0_G7W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_G7W_RANGE                  15:15
+#define GPCDMA_SCR_SCR_CH8_0_G7W_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH8_0_G7W_LSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH8_0_G7W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH8_0_G6W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_G6W_RANGE                  14:14
+#define GPCDMA_SCR_SCR_CH8_0_G6W_MSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH8_0_G6W_LSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH8_0_G6W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH8_0_G5W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_G5W_RANGE                  13:13
+#define GPCDMA_SCR_SCR_CH8_0_G5W_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH8_0_G5W_LSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH8_0_G5W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH8_0_G4W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_G4W_RANGE                  12:12
+#define GPCDMA_SCR_SCR_CH8_0_G4W_MSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH8_0_G4W_LSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH8_0_G4W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH8_0_G3W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_G3W_RANGE                  11:11
+#define GPCDMA_SCR_SCR_CH8_0_G3W_MSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH8_0_G3W_LSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH8_0_G3W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH8_0_G2W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_G2W_RANGE                  10:10
+#define GPCDMA_SCR_SCR_CH8_0_G2W_MSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH8_0_G2W_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH8_0_G2W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH8_0_G1W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_G1W_RANGE                  9:9
+#define GPCDMA_SCR_SCR_CH8_0_G1W_MSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH8_0_G1W_LSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH8_0_G1W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH8_0_G0W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_G0W_RANGE                  8:8
+#define GPCDMA_SCR_SCR_CH8_0_G0W_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH8_0_G0W_LSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH8_0_G0W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH8_0_G7R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_G7R_RANGE                  7:7
+#define GPCDMA_SCR_SCR_CH8_0_G7R_MSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH8_0_G7R_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH8_0_G7R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH8_0_G6R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_G6R_RANGE                  6:6
+#define GPCDMA_SCR_SCR_CH8_0_G6R_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH8_0_G6R_LSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH8_0_G6R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH8_0_G5R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_G5R_RANGE                  5:5
+#define GPCDMA_SCR_SCR_CH8_0_G5R_MSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH8_0_G5R_LSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH8_0_G5R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH8_0_G4R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_G4R_RANGE                  4:4
+#define GPCDMA_SCR_SCR_CH8_0_G4R_MSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH8_0_G4R_LSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH8_0_G4R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH8_0_G3R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_G3R_RANGE                  3:3
+#define GPCDMA_SCR_SCR_CH8_0_G3R_MSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH8_0_G3R_LSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH8_0_G3R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH8_0_G2R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_G2R_RANGE                  2:2
+#define GPCDMA_SCR_SCR_CH8_0_G2R_MSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH8_0_G2R_LSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH8_0_G2R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH8_0_G1R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_G1R_RANGE                  1:1
+#define GPCDMA_SCR_SCR_CH8_0_G1R_MSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH8_0_G1R_LSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH8_0_G1R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH8_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH8_0_G0R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH8_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH8_0_G0R_RANGE                  0:0
+#define GPCDMA_SCR_SCR_CH8_0_G0R_MSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH8_0_G0R_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH8_0_G0R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH8_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH8_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH8_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH9_0
+#define GPCDMA_SCR_SCR_CH9_0                    MK_ADDR_CONST(0xf24)
+#define GPCDMA_SCR_SCR_CH9_0_SECURE                     0x0
+#define GPCDMA_SCR_SCR_CH9_0_DUAL                       0x0
+#define GPCDMA_SCR_SCR_CH9_0_SCR                        0
+#define GPCDMA_SCR_SCR_CH9_0_SCRREG                     0
+#define GPCDMA_SCR_SCR_CH9_0_WORD_COUNT                         0x1
+#define GPCDMA_SCR_SCR_CH9_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH9_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH9_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_LCK_RANGE                      29:29
+#define GPCDMA_SCR_SCR_CH9_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_LCK_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH9_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_WEN_RANGE                      28:28
+#define GPCDMA_SCR_SCR_CH9_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_WEN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH9_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_REN_RANGE                      27:27
+#define GPCDMA_SCR_SCR_CH9_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_REN_WOFFSET                    0x0
+#define GPCDMA_SCR_SCR_CH9_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH9_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_OWNER_RANGE                    26:24
+#define GPCDMA_SCR_SCR_CH9_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_OWNER_WOFFSET                  0x0
+#define GPCDMA_SCR_SCR_CH9_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH9_0_PR7_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_PR7_RANGE                  23:23
+#define GPCDMA_SCR_SCR_CH9_0_PR7_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH9_0_PR7_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH9_0_PR7_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH9_0_PR6_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_PR6_RANGE                  22:22
+#define GPCDMA_SCR_SCR_CH9_0_PR6_MSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH9_0_PR6_LSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH9_0_PR6_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH9_0_PR5_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_PR5_RANGE                  21:21
+#define GPCDMA_SCR_SCR_CH9_0_PR5_MSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH9_0_PR5_LSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH9_0_PR5_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH9_0_PR4_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_PR4_RANGE                  20:20
+#define GPCDMA_SCR_SCR_CH9_0_PR4_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH9_0_PR4_LSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH9_0_PR4_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH9_0_PR3_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_PR3_RANGE                  19:19
+#define GPCDMA_SCR_SCR_CH9_0_PR3_MSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH9_0_PR3_LSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH9_0_PR3_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH9_0_PR2_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_PR2_RANGE                  18:18
+#define GPCDMA_SCR_SCR_CH9_0_PR2_MSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH9_0_PR2_LSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH9_0_PR2_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH9_0_PR1_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_PR1_RANGE                  17:17
+#define GPCDMA_SCR_SCR_CH9_0_PR1_MSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH9_0_PR1_LSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH9_0_PR1_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH9_0_PR0_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_PR0_RANGE                  16:16
+#define GPCDMA_SCR_SCR_CH9_0_PR0_MSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH9_0_PR0_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH9_0_PR0_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH9_0_G7W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_G7W_RANGE                  15:15
+#define GPCDMA_SCR_SCR_CH9_0_G7W_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH9_0_G7W_LSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH9_0_G7W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH9_0_G6W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_G6W_RANGE                  14:14
+#define GPCDMA_SCR_SCR_CH9_0_G6W_MSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH9_0_G6W_LSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH9_0_G6W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH9_0_G5W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_G5W_RANGE                  13:13
+#define GPCDMA_SCR_SCR_CH9_0_G5W_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH9_0_G5W_LSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH9_0_G5W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH9_0_G4W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_G4W_RANGE                  12:12
+#define GPCDMA_SCR_SCR_CH9_0_G4W_MSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH9_0_G4W_LSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH9_0_G4W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH9_0_G3W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_G3W_RANGE                  11:11
+#define GPCDMA_SCR_SCR_CH9_0_G3W_MSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH9_0_G3W_LSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH9_0_G3W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH9_0_G2W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_G2W_RANGE                  10:10
+#define GPCDMA_SCR_SCR_CH9_0_G2W_MSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH9_0_G2W_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH9_0_G2W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH9_0_G1W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_G1W_RANGE                  9:9
+#define GPCDMA_SCR_SCR_CH9_0_G1W_MSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH9_0_G1W_LSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH9_0_G1W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH9_0_G0W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_G0W_RANGE                  8:8
+#define GPCDMA_SCR_SCR_CH9_0_G0W_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH9_0_G0W_LSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH9_0_G0W_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_G0W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH9_0_G7R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_G7R_RANGE                  7:7
+#define GPCDMA_SCR_SCR_CH9_0_G7R_MSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH9_0_G7R_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH9_0_G7R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH9_0_G6R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_G6R_RANGE                  6:6
+#define GPCDMA_SCR_SCR_CH9_0_G6R_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH9_0_G6R_LSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH9_0_G6R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH9_0_G5R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_G5R_RANGE                  5:5
+#define GPCDMA_SCR_SCR_CH9_0_G5R_MSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH9_0_G5R_LSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH9_0_G5R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH9_0_G4R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_G4R_RANGE                  4:4
+#define GPCDMA_SCR_SCR_CH9_0_G4R_MSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH9_0_G4R_LSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH9_0_G4R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH9_0_G3R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_G3R_RANGE                  3:3
+#define GPCDMA_SCR_SCR_CH9_0_G3R_MSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH9_0_G3R_LSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH9_0_G3R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH9_0_G2R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_G2R_RANGE                  2:2
+#define GPCDMA_SCR_SCR_CH9_0_G2R_MSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH9_0_G2R_LSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH9_0_G2R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH9_0_G1R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_G1R_RANGE                  1:1
+#define GPCDMA_SCR_SCR_CH9_0_G1R_MSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH9_0_G1R_LSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH9_0_G1R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH9_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH9_0_G0R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH9_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH9_0_G0R_RANGE                  0:0
+#define GPCDMA_SCR_SCR_CH9_0_G0R_MSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH9_0_G0R_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH9_0_G0R_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_CH9_0_G0R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH9_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH9_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH10_0
+#define GPCDMA_SCR_SCR_CH10_0                   MK_ADDR_CONST(0xf28)
+#define GPCDMA_SCR_SCR_CH10_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH10_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH10_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH10_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH10_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH10_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH10_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH10_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH10_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH10_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH10_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH10_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH10_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH10_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH10_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH10_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH10_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH10_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH10_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH10_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH10_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH10_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH10_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH10_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH10_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH10_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH10_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH10_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH10_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH10_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH10_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH10_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH10_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH10_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH10_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH10_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH10_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH10_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH10_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH10_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH10_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH10_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH10_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH10_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH10_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH10_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH10_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH10_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH10_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH10_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH10_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH10_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH10_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH10_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH10_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH10_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH10_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH10_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH10_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH10_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH10_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH10_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH10_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH10_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH10_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH10_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH10_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH10_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH10_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH10_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH10_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH10_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH10_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH10_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH10_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH10_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH10_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH10_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH10_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH10_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH10_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH10_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH10_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH10_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH10_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH10_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH10_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH10_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH10_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH10_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH10_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH10_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH10_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH10_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH10_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH10_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH10_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH10_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH10_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH10_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH10_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH10_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH10_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH10_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH10_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH10_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH10_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH10_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH10_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH10_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH10_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH10_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH10_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH10_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH10_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH10_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH10_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH10_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH10_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH11_0
+#define GPCDMA_SCR_SCR_CH11_0                   MK_ADDR_CONST(0xf2c)
+#define GPCDMA_SCR_SCR_CH11_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH11_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH11_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH11_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH11_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH11_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH11_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH11_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH11_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH11_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH11_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH11_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH11_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH11_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH11_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH11_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH11_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH11_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH11_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH11_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH11_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH11_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH11_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH11_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH11_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH11_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH11_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH11_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH11_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH11_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH11_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH11_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH11_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH11_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH11_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH11_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH11_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH11_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH11_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH11_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH11_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH11_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH11_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH11_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH11_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH11_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH11_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH11_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH11_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH11_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH11_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH11_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH11_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH11_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH11_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH11_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH11_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH11_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH11_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH11_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH11_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH11_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH11_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH11_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH11_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH11_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH11_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH11_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH11_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH11_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH11_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH11_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH11_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH11_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH11_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH11_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH11_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH11_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH11_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH11_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH11_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH11_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH11_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH11_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH11_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH11_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH11_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH11_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH11_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH11_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH11_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH11_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH11_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH11_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH11_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH11_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH11_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH11_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH11_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH11_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH11_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH11_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH11_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH11_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH11_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH11_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH11_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH11_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH11_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH11_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH11_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH11_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH11_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH11_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH11_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH11_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH11_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH11_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH11_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH12_0
+#define GPCDMA_SCR_SCR_CH12_0                   MK_ADDR_CONST(0xf30)
+#define GPCDMA_SCR_SCR_CH12_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH12_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH12_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH12_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH12_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH12_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH12_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH12_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH12_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH12_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH12_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH12_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH12_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH12_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH12_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH12_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH12_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH12_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH12_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH12_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH12_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH12_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH12_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH12_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH12_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH12_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH12_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH12_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH12_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH12_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH12_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH12_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH12_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH12_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH12_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH12_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH12_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH12_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH12_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH12_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH12_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH12_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH12_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH12_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH12_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH12_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH12_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH12_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH12_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH12_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH12_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH12_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH12_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH12_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH12_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH12_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH12_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH12_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH12_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH12_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH12_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH12_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH12_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH12_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH12_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH12_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH12_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH12_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH12_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH12_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH12_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH12_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH12_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH12_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH12_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH12_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH12_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH12_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH12_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH12_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH12_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH12_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH12_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH12_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH12_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH12_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH12_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH12_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH12_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH12_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH12_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH12_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH12_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH12_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH12_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH12_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH12_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH12_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH12_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH12_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH12_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH12_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH12_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH12_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH12_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH12_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH12_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH12_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH12_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH12_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH12_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH12_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH12_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH12_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH12_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH12_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH12_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH12_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH12_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH13_0
+#define GPCDMA_SCR_SCR_CH13_0                   MK_ADDR_CONST(0xf34)
+#define GPCDMA_SCR_SCR_CH13_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH13_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH13_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH13_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH13_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH13_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH13_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH13_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH13_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH13_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH13_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH13_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH13_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH13_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH13_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH13_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH13_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH13_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH13_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH13_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH13_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH13_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH13_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH13_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH13_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH13_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH13_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH13_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH13_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH13_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH13_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH13_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH13_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH13_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH13_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH13_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH13_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH13_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH13_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH13_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH13_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH13_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH13_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH13_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH13_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH13_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH13_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH13_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH13_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH13_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH13_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH13_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH13_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH13_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH13_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH13_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH13_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH13_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH13_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH13_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH13_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH13_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH13_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH13_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH13_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH13_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH13_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH13_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH13_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH13_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH13_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH13_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH13_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH13_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH13_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH13_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH13_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH13_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH13_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH13_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH13_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH13_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH13_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH13_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH13_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH13_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH13_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH13_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH13_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH13_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH13_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH13_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH13_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH13_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH13_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH13_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH13_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH13_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH13_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH13_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH13_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH13_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH13_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH13_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH13_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH13_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH13_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH13_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH13_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH13_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH13_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH13_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH13_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH13_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH13_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH13_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH13_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH13_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH13_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH14_0
+#define GPCDMA_SCR_SCR_CH14_0                   MK_ADDR_CONST(0xf38)
+#define GPCDMA_SCR_SCR_CH14_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH14_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH14_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH14_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH14_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH14_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH14_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH14_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH14_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH14_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH14_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH14_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH14_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH14_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH14_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH14_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH14_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH14_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH14_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH14_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH14_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH14_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH14_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH14_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH14_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH14_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH14_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH14_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH14_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH14_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH14_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH14_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH14_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH14_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH14_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH14_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH14_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH14_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH14_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH14_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH14_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH14_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH14_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH14_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH14_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH14_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH14_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH14_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH14_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH14_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH14_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH14_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH14_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH14_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH14_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH14_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH14_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH14_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH14_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH14_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH14_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH14_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH14_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH14_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH14_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH14_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH14_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH14_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH14_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH14_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH14_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH14_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH14_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH14_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH14_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH14_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH14_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH14_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH14_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH14_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH14_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH14_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH14_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH14_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH14_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH14_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH14_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH14_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH14_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH14_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH14_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH14_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH14_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH14_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH14_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH14_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH14_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH14_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH14_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH14_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH14_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH14_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH14_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH14_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH14_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH14_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH14_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH14_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH14_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH14_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH14_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH14_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH14_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH14_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH14_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH14_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH14_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH14_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH14_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH15_0
+#define GPCDMA_SCR_SCR_CH15_0                   MK_ADDR_CONST(0xf3c)
+#define GPCDMA_SCR_SCR_CH15_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH15_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH15_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH15_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH15_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH15_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH15_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH15_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH15_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH15_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH15_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH15_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH15_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH15_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH15_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH15_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH15_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH15_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH15_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH15_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH15_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH15_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH15_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH15_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH15_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH15_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH15_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH15_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH15_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH15_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH15_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH15_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH15_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH15_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH15_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH15_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH15_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH15_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH15_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH15_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH15_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH15_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH15_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH15_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH15_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH15_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH15_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH15_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH15_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH15_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH15_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH15_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH15_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH15_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH15_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH15_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH15_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH15_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH15_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH15_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH15_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH15_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH15_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH15_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH15_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH15_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH15_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH15_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH15_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH15_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH15_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH15_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH15_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH15_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH15_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH15_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH15_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH15_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH15_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH15_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH15_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH15_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH15_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH15_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH15_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH15_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH15_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH15_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH15_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH15_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH15_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH15_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH15_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH15_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH15_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH15_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH15_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH15_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH15_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH15_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH15_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH15_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH15_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH15_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH15_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH15_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH15_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH15_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH15_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH15_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH15_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH15_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH15_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH15_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH15_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH15_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH15_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH15_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH15_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH16_0
+#define GPCDMA_SCR_SCR_CH16_0                   MK_ADDR_CONST(0xf40)
+#define GPCDMA_SCR_SCR_CH16_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH16_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH16_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH16_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH16_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH16_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH16_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH16_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH16_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH16_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH16_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH16_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH16_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH16_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH16_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH16_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH16_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH16_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH16_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH16_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH16_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH16_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH16_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH16_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH16_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH16_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH16_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH16_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH16_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH16_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH16_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH16_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH16_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH16_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH16_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH16_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH16_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH16_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH16_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH16_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH16_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH16_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH16_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH16_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH16_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH16_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH16_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH16_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH16_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH16_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH16_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH16_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH16_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH16_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH16_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH16_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH16_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH16_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH16_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH16_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH16_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH16_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH16_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH16_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH16_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH16_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH16_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH16_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH16_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH16_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH16_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH16_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH16_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH16_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH16_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH16_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH16_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH16_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH16_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH16_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH16_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH16_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH16_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH16_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH16_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH16_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH16_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH16_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH16_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH16_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH16_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH16_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH16_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH16_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH16_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH16_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH16_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH16_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH16_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH16_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH16_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH16_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH16_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH16_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH16_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH16_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH16_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH16_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH16_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH16_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH16_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH16_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH16_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH16_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH16_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH16_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH16_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH16_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH16_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH17_0
+#define GPCDMA_SCR_SCR_CH17_0                   MK_ADDR_CONST(0xf44)
+#define GPCDMA_SCR_SCR_CH17_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH17_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH17_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH17_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH17_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH17_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH17_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH17_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH17_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH17_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH17_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH17_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH17_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH17_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH17_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH17_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH17_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH17_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH17_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH17_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH17_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH17_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH17_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH17_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH17_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH17_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH17_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH17_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH17_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH17_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH17_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH17_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH17_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH17_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH17_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH17_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH17_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH17_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH17_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH17_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH17_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH17_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH17_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH17_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH17_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH17_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH17_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH17_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH17_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH17_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH17_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH17_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH17_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH17_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH17_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH17_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH17_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH17_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH17_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH17_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH17_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH17_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH17_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH17_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH17_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH17_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH17_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH17_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH17_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH17_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH17_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH17_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH17_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH17_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH17_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH17_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH17_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH17_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH17_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH17_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH17_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH17_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH17_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH17_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH17_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH17_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH17_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH17_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH17_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH17_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH17_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH17_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH17_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH17_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH17_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH17_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH17_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH17_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH17_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH17_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH17_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH17_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH17_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH17_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH17_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH17_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH17_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH17_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH17_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH17_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH17_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH17_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH17_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH17_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH17_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH17_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH17_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH17_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH17_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH18_0
+#define GPCDMA_SCR_SCR_CH18_0                   MK_ADDR_CONST(0xf48)
+#define GPCDMA_SCR_SCR_CH18_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH18_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH18_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH18_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH18_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH18_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH18_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH18_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH18_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH18_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH18_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH18_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH18_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH18_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH18_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH18_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH18_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH18_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH18_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH18_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH18_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH18_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH18_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH18_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH18_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH18_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH18_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH18_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH18_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH18_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH18_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH18_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH18_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH18_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH18_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH18_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH18_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH18_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH18_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH18_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH18_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH18_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH18_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH18_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH18_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH18_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH18_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH18_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH18_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH18_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH18_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH18_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH18_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH18_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH18_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH18_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH18_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH18_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH18_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH18_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH18_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH18_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH18_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH18_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH18_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH18_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH18_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH18_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH18_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH18_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH18_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH18_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH18_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH18_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH18_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH18_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH18_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH18_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH18_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH18_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH18_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH18_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH18_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH18_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH18_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH18_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH18_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH18_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH18_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH18_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH18_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH18_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH18_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH18_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH18_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH18_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH18_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH18_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH18_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH18_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH18_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH18_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH18_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH18_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH18_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH18_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH18_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH18_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH18_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH18_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH18_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH18_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH18_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH18_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH18_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH18_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH18_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH18_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH18_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH19_0
+#define GPCDMA_SCR_SCR_CH19_0                   MK_ADDR_CONST(0xf4c)
+#define GPCDMA_SCR_SCR_CH19_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH19_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH19_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH19_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH19_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH19_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH19_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH19_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH19_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH19_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH19_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH19_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH19_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH19_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH19_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH19_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH19_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH19_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH19_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH19_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH19_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH19_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH19_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH19_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH19_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH19_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH19_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH19_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH19_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH19_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH19_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH19_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH19_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH19_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH19_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH19_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH19_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH19_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH19_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH19_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH19_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH19_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH19_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH19_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH19_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH19_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH19_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH19_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH19_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH19_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH19_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH19_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH19_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH19_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH19_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH19_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH19_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH19_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH19_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH19_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH19_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH19_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH19_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH19_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH19_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH19_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH19_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH19_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH19_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH19_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH19_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH19_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH19_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH19_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH19_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH19_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH19_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH19_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH19_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH19_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH19_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH19_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH19_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH19_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH19_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH19_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH19_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH19_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH19_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH19_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH19_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH19_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH19_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH19_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH19_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH19_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH19_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH19_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH19_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH19_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH19_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH19_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH19_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH19_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH19_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH19_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH19_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH19_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH19_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH19_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH19_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH19_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH19_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH19_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH19_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH19_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH19_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH19_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH19_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH20_0
+#define GPCDMA_SCR_SCR_CH20_0                   MK_ADDR_CONST(0xf50)
+#define GPCDMA_SCR_SCR_CH20_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH20_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH20_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH20_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH20_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH20_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH20_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH20_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH20_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH20_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH20_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH20_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH20_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH20_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH20_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH20_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH20_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH20_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH20_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH20_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH20_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH20_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH20_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH20_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH20_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH20_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH20_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH20_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH20_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH20_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH20_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH20_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH20_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH20_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH20_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH20_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH20_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH20_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH20_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH20_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH20_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH20_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH20_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH20_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH20_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH20_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH20_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH20_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH20_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH20_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH20_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH20_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH20_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH20_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH20_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH20_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH20_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH20_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH20_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH20_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH20_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH20_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH20_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH20_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH20_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH20_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH20_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH20_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH20_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH20_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH20_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH20_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH20_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH20_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH20_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH20_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH20_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH20_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH20_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH20_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH20_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH20_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH20_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH20_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH20_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH20_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH20_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH20_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH20_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH20_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH20_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH20_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH20_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH20_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH20_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH20_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH20_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH20_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH20_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH20_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH20_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH20_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH20_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH20_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH20_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH20_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH20_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH20_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH20_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH20_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH20_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH20_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH20_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH20_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH20_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH20_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH20_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH20_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH20_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH21_0
+#define GPCDMA_SCR_SCR_CH21_0                   MK_ADDR_CONST(0xf54)
+#define GPCDMA_SCR_SCR_CH21_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH21_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH21_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH21_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH21_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH21_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH21_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH21_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH21_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH21_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH21_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH21_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH21_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH21_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH21_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH21_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH21_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH21_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH21_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH21_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH21_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH21_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH21_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH21_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH21_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH21_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH21_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH21_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH21_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH21_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH21_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH21_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH21_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH21_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH21_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH21_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH21_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH21_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH21_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH21_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH21_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH21_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH21_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH21_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH21_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH21_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH21_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH21_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH21_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH21_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH21_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH21_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH21_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH21_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH21_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH21_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH21_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH21_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH21_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH21_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH21_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH21_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH21_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH21_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH21_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH21_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH21_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH21_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH21_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH21_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH21_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH21_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH21_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH21_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH21_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH21_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH21_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH21_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH21_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH21_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH21_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH21_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH21_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH21_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH21_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH21_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH21_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH21_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH21_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH21_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH21_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH21_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH21_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH21_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH21_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH21_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH21_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH21_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH21_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH21_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH21_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH21_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH21_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH21_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH21_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH21_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH21_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH21_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH21_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH21_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH21_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH21_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH21_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH21_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH21_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH21_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH21_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH21_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH21_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH22_0
+#define GPCDMA_SCR_SCR_CH22_0                   MK_ADDR_CONST(0xf58)
+#define GPCDMA_SCR_SCR_CH22_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH22_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH22_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH22_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH22_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH22_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH22_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH22_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH22_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH22_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH22_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH22_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH22_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH22_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH22_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH22_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH22_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH22_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH22_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH22_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH22_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH22_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH22_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH22_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH22_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH22_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH22_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH22_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH22_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH22_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH22_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH22_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH22_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH22_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH22_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH22_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH22_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH22_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH22_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH22_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH22_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH22_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH22_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH22_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH22_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH22_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH22_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH22_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH22_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH22_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH22_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH22_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH22_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH22_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH22_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH22_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH22_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH22_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH22_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH22_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH22_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH22_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH22_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH22_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH22_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH22_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH22_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH22_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH22_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH22_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH22_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH22_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH22_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH22_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH22_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH22_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH22_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH22_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH22_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH22_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH22_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH22_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH22_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH22_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH22_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH22_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH22_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH22_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH22_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH22_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH22_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH22_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH22_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH22_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH22_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH22_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH22_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH22_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH22_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH22_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH22_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH22_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH22_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH22_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH22_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH22_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH22_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH22_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH22_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH22_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH22_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH22_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH22_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH22_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH22_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH22_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH22_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH22_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH22_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH23_0
+#define GPCDMA_SCR_SCR_CH23_0                   MK_ADDR_CONST(0xf5c)
+#define GPCDMA_SCR_SCR_CH23_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH23_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH23_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH23_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH23_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH23_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH23_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH23_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH23_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH23_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH23_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH23_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH23_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH23_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH23_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH23_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH23_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH23_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH23_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH23_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH23_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH23_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH23_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH23_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH23_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH23_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH23_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH23_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH23_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH23_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH23_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH23_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH23_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH23_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH23_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH23_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH23_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH23_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH23_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH23_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH23_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH23_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH23_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH23_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH23_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH23_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH23_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH23_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH23_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH23_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH23_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH23_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH23_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH23_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH23_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH23_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH23_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH23_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH23_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH23_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH23_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH23_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH23_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH23_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH23_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH23_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH23_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH23_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH23_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH23_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH23_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH23_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH23_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH23_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH23_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH23_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH23_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH23_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH23_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH23_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH23_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH23_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH23_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH23_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH23_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH23_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH23_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH23_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH23_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH23_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH23_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH23_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH23_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH23_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH23_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH23_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH23_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH23_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH23_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH23_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH23_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH23_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH23_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH23_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH23_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH23_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH23_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH23_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH23_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH23_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH23_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH23_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH23_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH23_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH23_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH23_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH23_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH23_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH23_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH24_0
+#define GPCDMA_SCR_SCR_CH24_0                   MK_ADDR_CONST(0xf60)
+#define GPCDMA_SCR_SCR_CH24_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH24_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH24_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH24_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH24_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH24_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH24_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH24_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH24_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH24_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH24_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH24_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH24_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH24_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH24_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH24_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH24_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH24_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH24_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH24_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH24_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH24_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH24_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH24_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH24_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH24_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH24_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH24_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH24_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH24_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH24_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH24_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH24_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH24_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH24_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH24_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH24_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH24_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH24_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH24_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH24_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH24_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH24_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH24_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH24_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH24_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH24_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH24_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH24_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH24_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH24_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH24_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH24_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH24_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH24_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH24_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH24_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH24_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH24_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH24_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH24_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH24_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH24_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH24_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH24_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH24_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH24_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH24_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH24_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH24_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH24_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH24_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH24_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH24_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH24_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH24_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH24_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH24_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH24_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH24_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH24_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH24_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH24_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH24_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH24_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH24_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH24_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH24_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH24_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH24_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH24_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH24_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH24_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH24_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH24_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH24_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH24_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH24_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH24_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH24_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH24_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH24_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH24_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH24_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH24_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH24_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH24_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH24_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH24_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH24_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH24_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH24_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH24_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH24_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH24_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH24_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH24_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH24_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH24_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH25_0
+#define GPCDMA_SCR_SCR_CH25_0                   MK_ADDR_CONST(0xf64)
+#define GPCDMA_SCR_SCR_CH25_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH25_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH25_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH25_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH25_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH25_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH25_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH25_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH25_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH25_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH25_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH25_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH25_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH25_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH25_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH25_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH25_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH25_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH25_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH25_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH25_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH25_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH25_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH25_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH25_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH25_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH25_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH25_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH25_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH25_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH25_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH25_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH25_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH25_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH25_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH25_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH25_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH25_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH25_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH25_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH25_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH25_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH25_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH25_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH25_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH25_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH25_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH25_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH25_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH25_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH25_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH25_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH25_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH25_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH25_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH25_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH25_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH25_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH25_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH25_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH25_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH25_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH25_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH25_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH25_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH25_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH25_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH25_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH25_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH25_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH25_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH25_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH25_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH25_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH25_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH25_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH25_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH25_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH25_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH25_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH25_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH25_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH25_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH25_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH25_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH25_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH25_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH25_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH25_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH25_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH25_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH25_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH25_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH25_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH25_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH25_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH25_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH25_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH25_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH25_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH25_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH25_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH25_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH25_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH25_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH25_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH25_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH25_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH25_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH25_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH25_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH25_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH25_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH25_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH25_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH25_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH25_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH25_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH25_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH26_0
+#define GPCDMA_SCR_SCR_CH26_0                   MK_ADDR_CONST(0xf68)
+#define GPCDMA_SCR_SCR_CH26_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH26_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH26_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH26_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH26_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH26_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH26_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH26_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH26_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH26_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH26_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH26_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH26_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH26_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH26_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH26_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH26_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH26_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH26_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH26_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH26_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH26_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH26_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH26_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH26_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH26_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH26_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH26_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH26_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH26_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH26_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH26_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH26_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH26_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH26_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH26_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH26_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH26_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH26_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH26_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH26_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH26_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH26_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH26_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH26_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH26_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH26_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH26_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH26_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH26_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH26_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH26_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH26_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH26_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH26_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH26_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH26_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH26_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH26_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH26_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH26_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH26_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH26_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH26_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH26_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH26_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH26_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH26_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH26_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH26_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH26_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH26_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH26_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH26_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH26_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH26_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH26_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH26_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH26_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH26_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH26_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH26_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH26_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH26_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH26_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH26_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH26_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH26_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH26_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH26_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH26_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH26_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH26_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH26_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH26_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH26_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH26_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH26_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH26_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH26_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH26_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH26_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH26_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH26_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH26_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH26_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH26_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH26_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH26_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH26_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH26_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH26_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH26_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH26_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH26_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH26_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH26_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH26_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH26_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH27_0
+#define GPCDMA_SCR_SCR_CH27_0                   MK_ADDR_CONST(0xf6c)
+#define GPCDMA_SCR_SCR_CH27_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH27_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH27_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH27_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH27_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH27_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH27_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH27_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH27_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH27_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH27_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH27_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH27_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH27_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH27_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH27_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH27_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH27_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH27_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH27_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH27_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH27_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH27_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH27_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH27_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH27_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH27_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH27_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH27_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH27_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH27_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH27_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH27_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH27_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH27_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH27_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH27_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH27_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH27_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH27_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH27_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH27_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH27_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH27_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH27_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH27_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH27_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH27_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH27_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH27_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH27_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH27_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH27_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH27_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH27_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH27_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH27_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH27_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH27_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH27_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH27_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH27_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH27_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH27_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH27_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH27_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH27_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH27_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH27_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH27_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH27_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH27_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH27_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH27_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH27_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH27_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH27_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH27_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH27_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH27_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH27_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH27_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH27_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH27_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH27_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH27_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH27_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH27_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH27_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH27_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH27_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH27_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH27_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH27_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH27_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH27_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH27_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH27_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH27_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH27_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH27_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH27_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH27_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH27_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH27_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH27_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH27_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH27_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH27_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH27_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH27_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH27_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH27_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH27_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH27_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH27_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH27_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH27_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH27_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH28_0
+#define GPCDMA_SCR_SCR_CH28_0                   MK_ADDR_CONST(0xf70)
+#define GPCDMA_SCR_SCR_CH28_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH28_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH28_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH28_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH28_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH28_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH28_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH28_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH28_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH28_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH28_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH28_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH28_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH28_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH28_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH28_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH28_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH28_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH28_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH28_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH28_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH28_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH28_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH28_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH28_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH28_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH28_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH28_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH28_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH28_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH28_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH28_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH28_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH28_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH28_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH28_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH28_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH28_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH28_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH28_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH28_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH28_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH28_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH28_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH28_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH28_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH28_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH28_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH28_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH28_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH28_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH28_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH28_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH28_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH28_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH28_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH28_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH28_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH28_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH28_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH28_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH28_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH28_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH28_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH28_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH28_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH28_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH28_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH28_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH28_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH28_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH28_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH28_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH28_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH28_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH28_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH28_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH28_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH28_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH28_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH28_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH28_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH28_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH28_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH28_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH28_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH28_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH28_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH28_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH28_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH28_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH28_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH28_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH28_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH28_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH28_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH28_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH28_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH28_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH28_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH28_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH28_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH28_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH28_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH28_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH28_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH28_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH28_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH28_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH28_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH28_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH28_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH28_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH28_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH28_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH28_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH28_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH28_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH28_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH29_0
+#define GPCDMA_SCR_SCR_CH29_0                   MK_ADDR_CONST(0xf74)
+#define GPCDMA_SCR_SCR_CH29_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH29_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH29_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH29_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH29_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH29_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH29_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH29_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH29_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH29_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH29_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH29_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH29_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH29_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH29_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH29_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH29_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH29_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH29_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH29_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH29_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH29_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH29_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH29_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH29_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH29_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH29_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH29_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH29_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH29_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH29_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH29_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH29_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH29_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH29_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH29_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH29_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH29_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH29_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH29_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH29_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH29_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH29_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH29_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH29_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH29_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH29_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH29_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH29_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH29_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH29_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH29_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH29_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH29_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH29_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH29_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH29_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH29_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH29_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH29_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH29_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH29_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH29_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH29_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH29_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH29_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH29_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH29_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH29_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH29_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH29_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH29_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH29_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH29_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH29_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH29_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH29_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH29_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH29_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH29_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH29_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH29_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH29_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH29_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH29_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH29_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH29_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH29_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH29_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH29_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH29_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH29_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH29_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH29_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH29_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH29_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH29_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH29_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH29_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH29_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH29_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH29_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH29_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH29_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH29_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH29_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH29_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH29_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH29_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH29_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH29_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH29_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH29_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH29_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH29_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH29_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH29_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH29_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH29_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH30_0
+#define GPCDMA_SCR_SCR_CH30_0                   MK_ADDR_CONST(0xf78)
+#define GPCDMA_SCR_SCR_CH30_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH30_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH30_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH30_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH30_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH30_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH30_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH30_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH30_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH30_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH30_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH30_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH30_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH30_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH30_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH30_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH30_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH30_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH30_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH30_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH30_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH30_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH30_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH30_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH30_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH30_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH30_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH30_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH30_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH30_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH30_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH30_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH30_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH30_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH30_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH30_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH30_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH30_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH30_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH30_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH30_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH30_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH30_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH30_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH30_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH30_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH30_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH30_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH30_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH30_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH30_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH30_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH30_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH30_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH30_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH30_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH30_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH30_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH30_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH30_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH30_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH30_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH30_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH30_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH30_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH30_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH30_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH30_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH30_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH30_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH30_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH30_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH30_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH30_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH30_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH30_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH30_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH30_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH30_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH30_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH30_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH30_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH30_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH30_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH30_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH30_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH30_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH30_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH30_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH30_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH30_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH30_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH30_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH30_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH30_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH30_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH30_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH30_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH30_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH30_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH30_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH30_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH30_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH30_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH30_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH30_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH30_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH30_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH30_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH30_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH30_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH30_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH30_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH30_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH30_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH30_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH30_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH30_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH30_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_CH31_0
+#define GPCDMA_SCR_SCR_CH31_0                   MK_ADDR_CONST(0xf7c)
+#define GPCDMA_SCR_SCR_CH31_0_SECURE                    0x0
+#define GPCDMA_SCR_SCR_CH31_0_DUAL                      0x0
+#define GPCDMA_SCR_SCR_CH31_0_SCR                       0
+#define GPCDMA_SCR_SCR_CH31_0_SCRREG                    0
+#define GPCDMA_SCR_SCR_CH31_0_WORD_COUNT                        0x1
+#define GPCDMA_SCR_SCR_CH31_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH31_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH31_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_SCR_SCR_CH31_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH31_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_SCR_SCR_CH31_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH31_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_SCR_SCR_CH31_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_CH31_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_CH31_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_SCR_SCR_CH31_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_CH31_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH31_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_PR7_RANGE                 23:23
+#define GPCDMA_SCR_SCR_CH31_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH31_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_CH31_0_PR7_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH31_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_PR6_RANGE                 22:22
+#define GPCDMA_SCR_SCR_CH31_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH31_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_CH31_0_PR6_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH31_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_PR5_RANGE                 21:21
+#define GPCDMA_SCR_SCR_CH31_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH31_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_CH31_0_PR5_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH31_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_PR4_RANGE                 20:20
+#define GPCDMA_SCR_SCR_CH31_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH31_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_CH31_0_PR4_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH31_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_PR3_RANGE                 19:19
+#define GPCDMA_SCR_SCR_CH31_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH31_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_CH31_0_PR3_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH31_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_PR2_RANGE                 18:18
+#define GPCDMA_SCR_SCR_CH31_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH31_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_CH31_0_PR2_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH31_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_PR1_RANGE                 17:17
+#define GPCDMA_SCR_SCR_CH31_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH31_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_CH31_0_PR1_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH31_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_PR0_RANGE                 16:16
+#define GPCDMA_SCR_SCR_CH31_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH31_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_CH31_0_PR0_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH31_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_G7W_RANGE                 15:15
+#define GPCDMA_SCR_SCR_CH31_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH31_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_CH31_0_G7W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH31_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_G6W_RANGE                 14:14
+#define GPCDMA_SCR_SCR_CH31_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH31_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_CH31_0_G6W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH31_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_G5W_RANGE                 13:13
+#define GPCDMA_SCR_SCR_CH31_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH31_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_CH31_0_G5W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH31_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_G4W_RANGE                 12:12
+#define GPCDMA_SCR_SCR_CH31_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH31_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_CH31_0_G4W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH31_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_G3W_RANGE                 11:11
+#define GPCDMA_SCR_SCR_CH31_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH31_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_CH31_0_G3W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH31_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_G2W_RANGE                 10:10
+#define GPCDMA_SCR_SCR_CH31_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH31_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_CH31_0_G2W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH31_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_G1W_RANGE                 9:9
+#define GPCDMA_SCR_SCR_CH31_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH31_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_CH31_0_G1W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH31_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_G0W_RANGE                 8:8
+#define GPCDMA_SCR_SCR_CH31_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH31_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_CH31_0_G0W_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH31_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_G7R_RANGE                 7:7
+#define GPCDMA_SCR_SCR_CH31_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH31_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_CH31_0_G7R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH31_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_G6R_RANGE                 6:6
+#define GPCDMA_SCR_SCR_CH31_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH31_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_CH31_0_G6R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH31_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_G5R_RANGE                 5:5
+#define GPCDMA_SCR_SCR_CH31_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH31_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_CH31_0_G5R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH31_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_G4R_RANGE                 4:4
+#define GPCDMA_SCR_SCR_CH31_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH31_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_CH31_0_G4R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH31_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_G3R_RANGE                 3:3
+#define GPCDMA_SCR_SCR_CH31_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH31_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_CH31_0_G3R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH31_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_G2R_RANGE                 2:2
+#define GPCDMA_SCR_SCR_CH31_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH31_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_CH31_0_G2R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH31_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_G1R_RANGE                 1:1
+#define GPCDMA_SCR_SCR_CH31_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH31_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_CH31_0_G1R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_CH31_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH31_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_CH31_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_CH31_0_G0R_RANGE                 0:0
+#define GPCDMA_SCR_SCR_CH31_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH31_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_CH31_0_G0R_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_CH31_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_CH31_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_CH31_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_SCR_SCR_TZ_0                     MK_ADDR_CONST(0xf80)
+#define GPCDMA_SCR_SCR_TZ_0_SECURE                      0x0
+#define GPCDMA_SCR_SCR_TZ_0_DUAL                        0x0
+#define GPCDMA_SCR_SCR_TZ_0_SCR                         0
+#define GPCDMA_SCR_SCR_TZ_0_SCRREG                      0
+#define GPCDMA_SCR_SCR_TZ_0_WORD_COUNT                  0x1
+#define GPCDMA_SCR_SCR_TZ_0_RESET_VAL                   MK_MASK_CONST(0x38000101)
+#define GPCDMA_SCR_SCR_TZ_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_TZ_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_TZ_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_LCK_RANGE                       29:29
+#define GPCDMA_SCR_SCR_TZ_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_LCK_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_TZ_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_WEN_RANGE                       28:28
+#define GPCDMA_SCR_SCR_TZ_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_WEN_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_TZ_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_REN_RANGE                       27:27
+#define GPCDMA_SCR_SCR_TZ_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_REN_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_TZ_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_TZ_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_OWNER_RANGE                     26:24
+#define GPCDMA_SCR_SCR_TZ_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_OWNER_WOFFSET                   0x0
+#define GPCDMA_SCR_SCR_TZ_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_TZ_0_PR7_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_PR7_RANGE                   23:23
+#define GPCDMA_SCR_SCR_TZ_0_PR7_MSB                     MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_TZ_0_PR7_LSB                     MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_TZ_0_PR7_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_TZ_0_PR6_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_PR6_RANGE                   22:22
+#define GPCDMA_SCR_SCR_TZ_0_PR6_MSB                     MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_TZ_0_PR6_LSB                     MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_TZ_0_PR6_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_TZ_0_PR5_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_PR5_RANGE                   21:21
+#define GPCDMA_SCR_SCR_TZ_0_PR5_MSB                     MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_TZ_0_PR5_LSB                     MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_TZ_0_PR5_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_TZ_0_PR4_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_PR4_RANGE                   20:20
+#define GPCDMA_SCR_SCR_TZ_0_PR4_MSB                     MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_TZ_0_PR4_LSB                     MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_TZ_0_PR4_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_TZ_0_PR3_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_PR3_RANGE                   19:19
+#define GPCDMA_SCR_SCR_TZ_0_PR3_MSB                     MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_TZ_0_PR3_LSB                     MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_TZ_0_PR3_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_TZ_0_PR2_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_PR2_RANGE                   18:18
+#define GPCDMA_SCR_SCR_TZ_0_PR2_MSB                     MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_TZ_0_PR2_LSB                     MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_TZ_0_PR2_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_TZ_0_PR1_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_PR1_RANGE                   17:17
+#define GPCDMA_SCR_SCR_TZ_0_PR1_MSB                     MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_TZ_0_PR1_LSB                     MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_TZ_0_PR1_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_TZ_0_PR0_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_PR0_RANGE                   16:16
+#define GPCDMA_SCR_SCR_TZ_0_PR0_MSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_TZ_0_PR0_LSB                     MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_TZ_0_PR0_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_TZ_0_G7W_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_G7W_RANGE                   15:15
+#define GPCDMA_SCR_SCR_TZ_0_G7W_MSB                     MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_TZ_0_G7W_LSB                     MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_TZ_0_G7W_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_TZ_0_G6W_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_G6W_RANGE                   14:14
+#define GPCDMA_SCR_SCR_TZ_0_G6W_MSB                     MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_TZ_0_G6W_LSB                     MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_TZ_0_G6W_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_TZ_0_G5W_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_G5W_RANGE                   13:13
+#define GPCDMA_SCR_SCR_TZ_0_G5W_MSB                     MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_TZ_0_G5W_LSB                     MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_TZ_0_G5W_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_TZ_0_G4W_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_G4W_RANGE                   12:12
+#define GPCDMA_SCR_SCR_TZ_0_G4W_MSB                     MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_TZ_0_G4W_LSB                     MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_TZ_0_G4W_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_TZ_0_G3W_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_G3W_RANGE                   11:11
+#define GPCDMA_SCR_SCR_TZ_0_G3W_MSB                     MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_TZ_0_G3W_LSB                     MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_TZ_0_G3W_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_TZ_0_G2W_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_G2W_RANGE                   10:10
+#define GPCDMA_SCR_SCR_TZ_0_G2W_MSB                     MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_TZ_0_G2W_LSB                     MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_TZ_0_G2W_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_TZ_0_G1W_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_G1W_RANGE                   9:9
+#define GPCDMA_SCR_SCR_TZ_0_G1W_MSB                     MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_TZ_0_G1W_LSB                     MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_TZ_0_G1W_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_TZ_0_G0W_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_G0W_RANGE                   8:8
+#define GPCDMA_SCR_SCR_TZ_0_G0W_MSB                     MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_TZ_0_G0W_LSB                     MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_TZ_0_G0W_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_G0W_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_TZ_0_G7R_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_G7R_RANGE                   7:7
+#define GPCDMA_SCR_SCR_TZ_0_G7R_MSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_TZ_0_G7R_LSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_TZ_0_G7R_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_TZ_0_G6R_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_G6R_RANGE                   6:6
+#define GPCDMA_SCR_SCR_TZ_0_G6R_MSB                     MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_TZ_0_G6R_LSB                     MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_TZ_0_G6R_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_TZ_0_G5R_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_G5R_RANGE                   5:5
+#define GPCDMA_SCR_SCR_TZ_0_G5R_MSB                     MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_TZ_0_G5R_LSB                     MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_TZ_0_G5R_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_TZ_0_G4R_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_G4R_RANGE                   4:4
+#define GPCDMA_SCR_SCR_TZ_0_G4R_MSB                     MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_TZ_0_G4R_LSB                     MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_TZ_0_G4R_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_TZ_0_G3R_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_G3R_RANGE                   3:3
+#define GPCDMA_SCR_SCR_TZ_0_G3R_MSB                     MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_TZ_0_G3R_LSB                     MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_TZ_0_G3R_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_TZ_0_G2R_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_G2R_RANGE                   2:2
+#define GPCDMA_SCR_SCR_TZ_0_G2R_MSB                     MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_TZ_0_G2R_LSB                     MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_TZ_0_G2R_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_TZ_0_G1R_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_G1R_RANGE                   1:1
+#define GPCDMA_SCR_SCR_TZ_0_G1R_MSB                     MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_TZ_0_G1R_LSB                     MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_TZ_0_G1R_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_TZ_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_TZ_0_G0R_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_TZ_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_TZ_0_G0R_RANGE                   0:0
+#define GPCDMA_SCR_SCR_TZ_0_G0R_MSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_TZ_0_G0R_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_TZ_0_G0R_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_TZ_0_G0R_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_TZ_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_TZ_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_DMA_RO_0
+#define GPCDMA_SCR_SCR_DMA_RO_0                 MK_ADDR_CONST(0xf84)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SECURE                  0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_DUAL                    0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_SCR                     0
+#define GPCDMA_SCR_SCR_DMA_RO_0_SCRREG                  0
+#define GPCDMA_SCR_SCR_DMA_RO_0_WORD_COUNT                      0x1
+#define GPCDMA_SCR_SCR_DMA_RO_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_DMA_RO_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_LCK_RANGE                   29:29
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_LCK_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_WEN_RANGE                   28:28
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_WEN_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_REN_RANGE                   27:27
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_REN_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_DMA_RO_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_OWNER_RANGE                 26:24
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_OWNER_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR7_RANGE                       23:23
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR7_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR6_RANGE                       22:22
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR6_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR5_RANGE                       21:21
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR5_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR4_RANGE                       20:20
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR4_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR3_RANGE                       19:19
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR3_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR2_RANGE                       18:18
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR2_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR1_RANGE                       17:17
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR1_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR0_RANGE                       16:16
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR0_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7W_RANGE                       15:15
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7W_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6W_RANGE                       14:14
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6W_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5W_RANGE                       13:13
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5W_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4W_RANGE                       12:12
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4W_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3W_RANGE                       11:11
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3W_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2W_RANGE                       10:10
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2W_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1W_RANGE                       9:9
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1W_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0W_RANGE                       8:8
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0W_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7R_RANGE                       7:7
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7R_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6R_RANGE                       6:6
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6R_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5R_RANGE                       5:5
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5R_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4R_RANGE                       4:4
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4R_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3R_RANGE                       3:3
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3R_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2R_RANGE                       2:2
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2R_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1R_RANGE                       1:1
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1R_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_DMA_RO_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0R_RANGE                       0:0
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0R_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_DMA_RO_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_HYPER_0
+#define GPCDMA_SCR_SCR_HYPER_0                  MK_ADDR_CONST(0xf88)
+#define GPCDMA_SCR_SCR_HYPER_0_SECURE                   0x0
+#define GPCDMA_SCR_SCR_HYPER_0_DUAL                     0x0
+#define GPCDMA_SCR_SCR_HYPER_0_SCR                      0
+#define GPCDMA_SCR_SCR_HYPER_0_SCRREG                   0
+#define GPCDMA_SCR_SCR_HYPER_0_WORD_COUNT                       0x1
+#define GPCDMA_SCR_SCR_HYPER_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_HYPER_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_HYPER_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_LCK_RANGE                    29:29
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_LCK_WOFFSET                  0x0
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_WEN_RANGE                    28:28
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_WEN_WOFFSET                  0x0
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_REN_RANGE                    27:27
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_REN_WOFFSET                  0x0
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_HYPER_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_OWNER_RANGE                  26:24
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_OWNER_WOFFSET                        0x0
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_HYPER_0_PR7_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_PR7_RANGE                        23:23
+#define GPCDMA_SCR_SCR_HYPER_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_HYPER_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_HYPER_0_PR7_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_HYPER_0_PR6_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_PR6_RANGE                        22:22
+#define GPCDMA_SCR_SCR_HYPER_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_HYPER_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_HYPER_0_PR6_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_HYPER_0_PR5_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_PR5_RANGE                        21:21
+#define GPCDMA_SCR_SCR_HYPER_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_HYPER_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_HYPER_0_PR5_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_HYPER_0_PR4_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_PR4_RANGE                        20:20
+#define GPCDMA_SCR_SCR_HYPER_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_HYPER_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_HYPER_0_PR4_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_HYPER_0_PR3_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_PR3_RANGE                        19:19
+#define GPCDMA_SCR_SCR_HYPER_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_HYPER_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_HYPER_0_PR3_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_HYPER_0_PR2_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_PR2_RANGE                        18:18
+#define GPCDMA_SCR_SCR_HYPER_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_HYPER_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_HYPER_0_PR2_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_HYPER_0_PR1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_PR1_RANGE                        17:17
+#define GPCDMA_SCR_SCR_HYPER_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_HYPER_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_HYPER_0_PR1_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_HYPER_0_PR0_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_PR0_RANGE                        16:16
+#define GPCDMA_SCR_SCR_HYPER_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_HYPER_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_HYPER_0_PR0_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_HYPER_0_G7W_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_G7W_RANGE                        15:15
+#define GPCDMA_SCR_SCR_HYPER_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_HYPER_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_HYPER_0_G7W_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_HYPER_0_G6W_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_G6W_RANGE                        14:14
+#define GPCDMA_SCR_SCR_HYPER_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_HYPER_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_HYPER_0_G6W_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_HYPER_0_G5W_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_G5W_RANGE                        13:13
+#define GPCDMA_SCR_SCR_HYPER_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_HYPER_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_HYPER_0_G5W_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_HYPER_0_G4W_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_G4W_RANGE                        12:12
+#define GPCDMA_SCR_SCR_HYPER_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_HYPER_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_HYPER_0_G4W_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_HYPER_0_G3W_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_G3W_RANGE                        11:11
+#define GPCDMA_SCR_SCR_HYPER_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_HYPER_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_HYPER_0_G3W_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_HYPER_0_G2W_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_G2W_RANGE                        10:10
+#define GPCDMA_SCR_SCR_HYPER_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_HYPER_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_HYPER_0_G2W_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_HYPER_0_G1W_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_G1W_RANGE                        9:9
+#define GPCDMA_SCR_SCR_HYPER_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_HYPER_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_HYPER_0_G1W_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_HYPER_0_G0W_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_G0W_RANGE                        8:8
+#define GPCDMA_SCR_SCR_HYPER_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_HYPER_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_HYPER_0_G0W_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_HYPER_0_G7R_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_G7R_RANGE                        7:7
+#define GPCDMA_SCR_SCR_HYPER_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_HYPER_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_HYPER_0_G7R_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_HYPER_0_G6R_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_G6R_RANGE                        6:6
+#define GPCDMA_SCR_SCR_HYPER_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_HYPER_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_HYPER_0_G6R_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_HYPER_0_G5R_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_G5R_RANGE                        5:5
+#define GPCDMA_SCR_SCR_HYPER_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_HYPER_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_HYPER_0_G5R_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_HYPER_0_G4R_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_G4R_RANGE                        4:4
+#define GPCDMA_SCR_SCR_HYPER_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_HYPER_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_HYPER_0_G4R_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_HYPER_0_G3R_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_G3R_RANGE                        3:3
+#define GPCDMA_SCR_SCR_HYPER_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_HYPER_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_HYPER_0_G3R_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_HYPER_0_G2R_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_G2R_RANGE                        2:2
+#define GPCDMA_SCR_SCR_HYPER_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_HYPER_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_HYPER_0_G2R_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_HYPER_0_G1R_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_G1R_RANGE                        1:1
+#define GPCDMA_SCR_SCR_HYPER_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_HYPER_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_HYPER_0_G1R_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_HYPER_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_HYPER_0_G0R_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_HYPER_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_HYPER_0_G0R_RANGE                        0:0
+#define GPCDMA_SCR_SCR_HYPER_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_HYPER_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_HYPER_0_G0R_WOFFSET                      0x0
+#define GPCDMA_SCR_SCR_HYPER_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_HYPER_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_HYPER_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_SCR_SCR_SAFETY_0
+#define GPCDMA_SCR_SCR_SAFETY_0                 MK_ADDR_CONST(0xf8c)
+#define GPCDMA_SCR_SCR_SAFETY_0_SECURE                  0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_DUAL                    0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_SCR                     0
+#define GPCDMA_SCR_SCR_SAFETY_0_SCRREG                  0
+#define GPCDMA_SCR_SCR_SAFETY_0_WORD_COUNT                      0x1
+#define GPCDMA_SCR_SCR_SAFETY_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_SAFETY_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_SAFETY_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_SEC_LCK_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_LCK_RANGE                   29:29
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_LCK_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_SEC_WEN_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_WEN_RANGE                   28:28
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_WEN_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_SEC_REN_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_REN_RANGE                   27:27
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_REN_WOFFSET                 0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_SCR_SCR_SAFETY_0_SEC_OWNER_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_OWNER_RANGE                 26:24
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_OWNER_WOFFSET                       0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_PR7_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR7_RANGE                       23:23
+#define GPCDMA_SCR_SCR_SAFETY_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR7_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_PR6_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR6_RANGE                       22:22
+#define GPCDMA_SCR_SCR_SAFETY_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR6_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_PR5_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR5_RANGE                       21:21
+#define GPCDMA_SCR_SCR_SAFETY_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR5_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_PR4_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR4_RANGE                       20:20
+#define GPCDMA_SCR_SCR_SAFETY_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR4_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_PR3_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR3_RANGE                       19:19
+#define GPCDMA_SCR_SCR_SAFETY_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR3_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_PR2_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR2_RANGE                       18:18
+#define GPCDMA_SCR_SCR_SAFETY_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR2_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_PR1_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR1_RANGE                       17:17
+#define GPCDMA_SCR_SCR_SAFETY_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR1_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_PR0_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR0_RANGE                       16:16
+#define GPCDMA_SCR_SCR_SAFETY_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR0_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_G7W_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7W_RANGE                       15:15
+#define GPCDMA_SCR_SCR_SAFETY_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7W_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_G6W_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6W_RANGE                       14:14
+#define GPCDMA_SCR_SCR_SAFETY_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6W_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_G5W_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5W_RANGE                       13:13
+#define GPCDMA_SCR_SCR_SAFETY_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5W_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_G4W_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4W_RANGE                       12:12
+#define GPCDMA_SCR_SCR_SAFETY_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4W_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_G3W_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3W_RANGE                       11:11
+#define GPCDMA_SCR_SCR_SAFETY_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3W_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_G2W_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2W_RANGE                       10:10
+#define GPCDMA_SCR_SCR_SAFETY_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2W_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_G1W_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1W_RANGE                       9:9
+#define GPCDMA_SCR_SCR_SAFETY_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1W_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_G0W_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0W_RANGE                       8:8
+#define GPCDMA_SCR_SCR_SAFETY_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0W_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_G7R_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7R_RANGE                       7:7
+#define GPCDMA_SCR_SCR_SAFETY_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7R_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_G6R_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6R_RANGE                       6:6
+#define GPCDMA_SCR_SCR_SAFETY_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6R_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_G5R_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5R_RANGE                       5:5
+#define GPCDMA_SCR_SCR_SAFETY_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5R_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_G4R_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4R_RANGE                       4:4
+#define GPCDMA_SCR_SCR_SAFETY_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4R_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_G3R_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3R_RANGE                       3:3
+#define GPCDMA_SCR_SCR_SAFETY_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3R_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_G2R_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2R_RANGE                       2:2
+#define GPCDMA_SCR_SCR_SAFETY_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2R_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_G1R_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1R_RANGE                       1:1
+#define GPCDMA_SCR_SCR_SAFETY_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1R_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_SCR_SCR_SAFETY_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_SCR_SCR_SAFETY_0_G0R_SHIFT)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0R_RANGE                       0:0
+#define GPCDMA_SCR_SCR_SAFETY_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0R_WOFFSET                     0x0
+#define GPCDMA_SCR_SCR_SAFETY_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_SCR_SCR_SAFETY_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0                 MK_ADDR_CONST(0xf000)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SECURE                  0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_DUAL                    0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SCR                     0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SCRREG                  0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_WORD_COUNT                      0x1
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_LCK_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_LCK_RANGE                   29:29
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_LCK_WOFFSET                 0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_WEN_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_WEN_RANGE                   28:28
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_WEN_WOFFSET                 0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_REN_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_REN_RANGE                   27:27
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_REN_WOFFSET                 0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_OWNER_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_OWNER_RANGE                 26:24
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_OWNER_WOFFSET                       0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR7_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR7_RANGE                       23:23
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR7_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR6_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR6_RANGE                       22:22
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR6_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR5_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR5_RANGE                       21:21
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR5_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR4_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR4_RANGE                       20:20
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR4_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR3_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR3_RANGE                       19:19
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR3_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR2_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR2_RANGE                       18:18
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR2_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR1_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR1_RANGE                       17:17
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR1_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR0_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR0_RANGE                       16:16
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR0_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7W_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7W_RANGE                       15:15
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7W_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6W_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6W_RANGE                       14:14
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6W_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5W_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5W_RANGE                       13:13
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5W_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4W_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4W_RANGE                       12:12
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4W_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3W_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3W_RANGE                       11:11
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3W_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2W_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2W_RANGE                       10:10
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2W_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1W_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1W_RANGE                       9:9
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1W_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0W_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0W_RANGE                       8:8
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0W_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7R_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7R_RANGE                       7:7
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7R_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6R_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6R_RANGE                       6:6
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6R_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5R_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5R_RANGE                       5:5
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5R_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4R_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4R_RANGE                       4:4
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4R_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3R_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3R_RANGE                       3:3
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3R_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2R_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2R_RANGE                       2:2
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2R_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1R_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1R_RANGE                       1:1
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1R_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0R_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0R_RANGE                       0:0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0R_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_ERRCOLLATOR_FEATURE_0
+#define GPCDMA_ERRCOLLATOR_FEATURE_0                    MK_ADDR_CONST(0xff00)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_SECURE                     0x0
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_DUAL                       0x0
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_SCR                        EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_SCRREG                     GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_WORD_COUNT                         0x1
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_RESET_VAL                  MK_MASK_CONST(0xc0001)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_RESET_MASK                         MK_MASK_CONST(0xffff003f)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_READ_MASK                  MK_MASK_CONST(0xffff003f)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_FIELD                      MK_FIELD_CONST(0xffff, GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_SHIFT)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_RANGE                      31:16
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_DEFAULT                    MK_MASK_CONST(0xc)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_SLICES_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_SLICES_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_SLICES_SHIFT)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_SLICES_RANGE                       5:0
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_SLICES_MSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_SLICES_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_SLICES_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_SLICES_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_SLICES_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_SLICES_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_SLICES_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_FEATURE_0_NUM_ERR_SLICES_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_ERRCOLLATOR_SWRESET_0
+#define GPCDMA_ERRCOLLATOR_SWRESET_0                    MK_ADDR_CONST(0xff04)
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_SECURE                     0x0
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_DUAL                       0x0
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_SCR                        EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_SCRREG                     GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_WORD_COUNT                         0x1
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_READ_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_SWRST_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_SWRST_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_SWRESET_0_SWRST_SHIFT)
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_SWRST_RANGE                        0:0
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_SWRST_MSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_SWRST_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_SWRST_WOFFSET                      0x0
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_SWRST_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_SWRST_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_SWRST_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_SWRST_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_SWRST_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_SWRESET_0_SWRST_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0                    MK_ADDR_CONST(0xff08)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_SECURE                     0x0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_DUAL                       0x0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_SCR                        EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_SCRREG                     GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_WORD_COUNT                         0x1
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_RESET_VAL                  MK_MASK_CONST(0x5)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_CODE_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_CODE_FIELD                 MK_FIELD_CONST(0x3f, GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_CODE_SHIFT)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_CODE_RANGE                 5:0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_CODE_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_CODE_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_CODE_WOFFSET                       0x0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_CODE_DEFAULT                       MK_MASK_CONST(0x5)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_CODE_DEFAULT_MASK                  MK_MASK_CONST(0x3f)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_CODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_CODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_CODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0_CODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0                      MK_ADDR_CONST(0xff0c)
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_SECURE                       0x0
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_DUAL                         0x0
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_SCR                  EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_SCRREG                       GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_WORD_COUNT                   0x1
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_RESET_MASK                   MK_MASK_CONST(0x1ff)
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_READ_MASK                    MK_MASK_CONST(0x1ff)
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_VALUE_FIELD                  MK_FIELD_CONST(0x1ff, GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_VALUE_SHIFT)
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_VALUE_RANGE                  8:0
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_VALUE_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_VALUE_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_VALUE_WOFFSET                        0x0
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_VALUE_DEFAULT_MASK                   MK_MASK_CONST(0x1ff)
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_VALUE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_VALUE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0_VALUE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xff10
+
+// Register GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0                   MK_ADDR_CONST(0xff14)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_SECURE                    0x0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_DUAL                      0x0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_SCR                       EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_SCRREG                    GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_WORD_COUNT                        0x1
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_WRITE_MASK                        MK_MASK_CONST(0xf)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_IDX_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_IDX_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_IDX_SHIFT)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_IDX_RANGE                 3:0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_IDX_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_IDX_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_IDX_WOFFSET                       0x0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_IDX_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_IDX_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_IDX_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_IDX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_IDX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0_IDX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0                      MK_ADDR_CONST(0xff18)
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_SECURE                       0x0
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_DUAL                         0x0
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_SCR                  EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_SCRREG                       GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_WORD_COUNT                   0x1
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_COUNT_FIELD                  MK_FIELD_CONST(0xff, GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_COUNT_SHIFT)
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_COUNT_RANGE                  7:0
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_COUNT_MSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_COUNT_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_COUNT_WOFFSET                        0x0
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0                   MK_ADDR_CONST(0xff1c)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_SECURE                    0x0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_DUAL                      0x0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_SCR                       EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_SCRREG                    GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_WORD_COUNT                        0x1
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_WRITE_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_VALUE_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_VALUE_SHIFT)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_VALUE_RANGE                       7:0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_VALUE_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_VALUE_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_VALUE_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_VALUE_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_VALUE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_VALUE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_VALUE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_VALUE_LOCK                        MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0_VALUE_UNLOCK                      MK_ENUM_CONST(225)
+
+
+// Reserved address 0xff20
+
+// Reserved address 0xff24
+
+// Reserved address 0xff28
+
+// Reserved address 0xff2c
+
+// Register GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0                        MK_ADDR_CONST(0xff30)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_SECURE                         0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_DUAL                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_SCR                    EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_SCRREG                         GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_WORD_COUNT                     0x1
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_VAL                      MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_RESET_MASK                     MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_READ_MASK                      MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_WRITE_MASK                     MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SHIFT                    MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_RANGE                    12:12
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_MSB                      MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_LSB                      MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_WOFFSET                  0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR12_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT                    MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_RANGE                    11:11
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_MSB                      MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_LSB                      MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_WOFFSET                  0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR11_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT                    MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_RANGE                    10:10
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_MSB                      MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_LSB                      MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_WOFFSET                  0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR10_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT                     MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_RANGE                     9:9
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_MSB                       MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_LSB                       MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR9_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT                     MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_RANGE                     8:8
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_MSB                       MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_LSB                       MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR8_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT                     MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_RANGE                     7:7
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_MSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_LSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR7_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_RANGE                     6:6
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_LSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR6_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_RANGE                     5:5
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_MSB                       MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_LSB                       MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR5_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_RANGE                     4:4
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_MSB                       MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_LSB                       MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR4_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_RANGE                     3:3
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_MSB                       MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_LSB                       MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR3_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_RANGE                     2:2
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_MSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_LSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR2_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_RANGE                     1:1
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_MSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_LSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR1_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_RANGE                     0:0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_MSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0_ERR0_ENABLE                    MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0                 MK_ADDR_CONST(0xff34)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_SECURE                  0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_DUAL                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_SCR                     EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_SCRREG                  GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_WORD_COUNT                      0x1
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_RESET_MASK                      MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_READ_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_WRITE_MASK                      MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SHIFT                     MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_RANGE                     12:12
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_MSB                       MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_LSB                       MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_NOFORCE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR12_FORCE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT                     MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_RANGE                     11:11
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_MSB                       MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_LSB                       MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_NOFORCE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR11_FORCE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT                     MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_RANGE                     10:10
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_MSB                       MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_LSB                       MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_NOFORCE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR10_FORCE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT                      MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_RANGE                      9:9
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_MSB                        MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_LSB                        MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_NOFORCE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR9_FORCE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT                      MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_RANGE                      8:8
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_MSB                        MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_LSB                        MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_NOFORCE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR8_FORCE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT                      MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_RANGE                      7:7
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_MSB                        MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_LSB                        MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_NOFORCE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR7_FORCE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_RANGE                      6:6
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_LSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_NOFORCE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR6_FORCE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_RANGE                      5:5
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_NOFORCE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR5_FORCE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_RANGE                      4:4
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_NOFORCE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR4_FORCE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_RANGE                      3:3
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_NOFORCE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR3_FORCE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_RANGE                      2:2
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_NOFORCE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR2_FORCE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_RANGE                      1:1
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_NOFORCE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR1_FORCE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_RANGE                      0:0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_NOFORCE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0_ERR0_FORCE                      MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0                        MK_ADDR_CONST(0xff38)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_SECURE                         0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_DUAL                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_SCR                    EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_SCRREG                         GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_WORD_COUNT                     0x1
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_READ_MASK                      MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SHIFT                    MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_RANGE                    12:12
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_MSB                      MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_LSB                      MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_WOFFSET                  0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR12_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT                    MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_RANGE                    11:11
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_MSB                      MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_LSB                      MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_WOFFSET                  0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR11_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT                    MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_RANGE                    10:10
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_MSB                      MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_LSB                      MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_WOFFSET                  0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR10_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT                     MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_RANGE                     9:9
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_MSB                       MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_LSB                       MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR9_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT                     MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_RANGE                     8:8
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_MSB                       MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_LSB                       MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR8_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT                     MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_RANGE                     7:7
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_MSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_LSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_RANGE                     6:6
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_LSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_RANGE                     5:5
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_MSB                       MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_LSB                       MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_RANGE                     4:4
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_MSB                       MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_LSB                       MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_RANGE                     3:3
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_MSB                       MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_LSB                       MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_RANGE                     2:2
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_MSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_LSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_RANGE                     1:1
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_MSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_LSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_RANGE                     0:0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_MSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0                        MK_ADDR_CONST(0xff3c)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_SECURE                         0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_DUAL                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_SCR                    EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_SCRREG                         GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_WORD_COUNT                     0x1
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_RESET_MASK                     MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_READ_MASK                      MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_WRITE_MASK                     MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_SHIFT                    MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_RANGE                    12:12
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_MSB                      MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_LSB                      MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_WOFFSET                  0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR12_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_SHIFT                    MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_RANGE                    11:11
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_MSB                      MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_LSB                      MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_WOFFSET                  0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR11_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_SHIFT                    MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_RANGE                    10:10
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_MSB                      MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_LSB                      MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_WOFFSET                  0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR10_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_SHIFT                     MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_RANGE                     9:9
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_MSB                       MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_LSB                       MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR9_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SHIFT                     MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_RANGE                     8:8
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_MSB                       MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_LSB                       MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR8_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT                     MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_RANGE                     7:7
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_MSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_LSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR7_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT                     MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_RANGE                     6:6
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_LSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR6_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT                     MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_RANGE                     5:5
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_MSB                       MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_LSB                       MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR5_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT                     MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_RANGE                     4:4
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_MSB                       MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_LSB                       MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR4_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT                     MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_RANGE                     3:3
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_MSB                       MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_LSB                       MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR3_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT                     MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_RANGE                     2:2
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_MSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_LSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR2_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT                     MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_RANGE                     1:1
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_MSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_LSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR1_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_RANGE                     0:0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_MSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0_ERR0_ENABLE                    MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0                 MK_ADDR_CONST(0xff40)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_SECURE                  0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_DUAL                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_SCR                     EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_SCRREG                  GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_WORD_COUNT                      0x1
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_READ_MASK                       MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SHIFT                     MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_RANGE                     12:12
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_MSB                       MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_LSB                       MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR12_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT                     MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_RANGE                     11:11
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_MSB                       MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_LSB                       MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR11_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT                     MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_RANGE                     10:10
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_MSB                       MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_LSB                       MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR10_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT                      MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_RANGE                      9:9
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_MSB                        MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_LSB                        MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR9_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT                      MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_RANGE                      8:8
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_MSB                        MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_LSB                        MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR8_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT                      MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_RANGE                      7:7
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_MSB                        MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_LSB                        MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR7_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_RANGE                      6:6
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_LSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR6_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_RANGE                      5:5
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_MSB                        MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_LSB                        MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR5_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_RANGE                      4:4
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_MSB                        MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_LSB                        MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR4_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_RANGE                      3:3
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_MSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_LSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR3_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_RANGE                      2:2
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_MSB                        MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_LSB                        MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR2_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_RANGE                      1:1
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_MSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_LSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR1_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_RANGE                      0:0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0_ERR0_ENABLE                     MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0                  MK_ADDR_CONST(0xff44)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_SECURE                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_DUAL                     0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_SCR                      EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_SCRREG                   GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_WORD_COUNT                       0x1
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_RESET_MASK                       MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_READ_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_WRITE_MASK                       MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SHIFT                      MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR12_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR12_RANGE                      12:12
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR12_MSB                        MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR12_LSB                        MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR12_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR12_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR12_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR12_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR12_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR12_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR12_NOFORCE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR12_FORCE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT                      MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR11_RANGE                      11:11
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR11_MSB                        MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR11_LSB                        MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR11_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR11_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR11_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR11_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR11_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR11_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR11_NOFORCE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR11_FORCE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT                      MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR10_RANGE                      10:10
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR10_MSB                        MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR10_LSB                        MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR10_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR10_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR10_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR10_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR10_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR10_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR10_NOFORCE                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR10_FORCE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT                       MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR9_RANGE                       9:9
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR9_MSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR9_LSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR9_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR9_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR9_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR9_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR9_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR9_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR9_NOFORCE                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR9_FORCE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT                       MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR8_RANGE                       8:8
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR8_MSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR8_LSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR8_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR8_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR8_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR8_NOFORCE                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR8_FORCE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT                       MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR7_RANGE                       7:7
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR7_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR7_LSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR7_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR7_NOFORCE                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR7_FORCE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT                       MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR6_RANGE                       6:6
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR6_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR6_LSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR6_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR6_NOFORCE                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR6_FORCE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT                       MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR5_RANGE                       5:5
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR5_MSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR5_LSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR5_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR5_NOFORCE                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR5_FORCE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT                       MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR4_RANGE                       4:4
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR4_MSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR4_LSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR4_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR4_NOFORCE                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR4_FORCE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR3_RANGE                       3:3
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR3_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR3_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR3_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR3_NOFORCE                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR3_FORCE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR2_RANGE                       2:2
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR2_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR2_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR2_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR2_NOFORCE                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR2_FORCE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT                       MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR1_RANGE                       1:1
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR1_MSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR1_LSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR1_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR1_NOFORCE                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR1_FORCE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR0_RANGE                       0:0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR0_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR0_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR0_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR0_NOFORCE                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0_ERR0_FORCE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0                 MK_ADDR_CONST(0xff48)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_SECURE                  0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_DUAL                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_SCR                     EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_SCRREG                  GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_WORD_COUNT                      0x1
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_READ_MASK                       MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SHIFT                     MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR12_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR12_RANGE                     12:12
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR12_MSB                       MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR12_LSB                       MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR12_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR12_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR12_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR12_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR12_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT                     MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR11_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR11_RANGE                     11:11
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR11_MSB                       MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR11_LSB                       MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR11_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR11_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR11_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR11_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR11_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT                     MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR10_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR10_RANGE                     10:10
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR10_MSB                       MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR10_LSB                       MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR10_WOFFSET                   0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR10_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR10_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR10_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR10_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT                      MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR9_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR9_RANGE                      9:9
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR9_MSB                        MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR9_LSB                        MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR9_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR9_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR9_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR9_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR9_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR9_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT                      MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR8_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR8_RANGE                      8:8
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR8_MSB                        MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR8_LSB                        MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR8_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR8_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR8_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR8_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR8_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR8_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT                      MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR7_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR7_RANGE                      7:7
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR7_MSB                        MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR7_LSB                        MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR7_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR7_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT                      MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR6_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR6_RANGE                      6:6
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR6_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR6_LSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR6_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT                      MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR5_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR5_RANGE                      5:5
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR5_MSB                        MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR5_LSB                        MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR5_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT                      MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR4_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR4_RANGE                      4:4
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR4_MSB                        MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR4_LSB                        MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR4_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT                      MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR3_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR3_RANGE                      3:3
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR3_MSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR3_LSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR3_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT                      MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR2_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR2_RANGE                      2:2
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR2_MSB                        MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR2_LSB                        MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR2_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT                      MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR1_RANGE                      1:1
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR1_MSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR1_LSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR1_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR0_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR0_RANGE                      0:0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR0_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR0_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR0_WOFFSET                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0_ERR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xff4c
+
+// Register GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0                   MK_ADDR_CONST(0xff50)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_SECURE                    0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_DUAL                      0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_SCR                       EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_SCRREG                    GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_WORD_COUNT                        0x1
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_RESET_MASK                        MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_READ_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_WRITE_MASK                        MK_MASK_CONST(0x1fff)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SHIFT                       MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR12_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR12_RANGE                       12:12
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR12_MSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR12_LSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR12_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR12_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR12_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR12_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR12_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR12_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR12_NORELOAD                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR12_RELOAD                      MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT                       MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR11_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR11_RANGE                       11:11
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR11_MSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR11_LSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR11_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR11_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR11_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR11_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR11_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR11_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR11_NORELOAD                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR11_RELOAD                      MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT                       MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR10_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR10_RANGE                       10:10
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR10_MSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR10_LSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR10_WOFFSET                     0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR10_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR10_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR10_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR10_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR10_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR10_NORELOAD                    MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR10_RELOAD                      MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT                        MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR9_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR9_RANGE                        9:9
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR9_MSB                  MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR9_LSB                  MK_SHIFT_CONST(9)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR9_WOFFSET                      0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR9_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR9_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR9_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR9_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR9_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR9_NORELOAD                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR9_RELOAD                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT                        MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR8_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR8_RANGE                        8:8
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR8_MSB                  MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR8_LSB                  MK_SHIFT_CONST(8)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR8_WOFFSET                      0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR8_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR8_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR8_NORELOAD                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR8_RELOAD                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT                        MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR7_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR7_RANGE                        7:7
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR7_MSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR7_LSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR7_WOFFSET                      0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR7_NORELOAD                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR7_RELOAD                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT                        MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR6_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RANGE                        6:6
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR6_MSB                  MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR6_LSB                  MK_SHIFT_CONST(6)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR6_WOFFSET                      0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR6_NORELOAD                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR6_RELOAD                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT                        MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR5_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RANGE                        5:5
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR5_MSB                  MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR5_LSB                  MK_SHIFT_CONST(5)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR5_WOFFSET                      0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR5_NORELOAD                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR5_RELOAD                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT                        MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR4_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RANGE                        4:4
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR4_MSB                  MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR4_LSB                  MK_SHIFT_CONST(4)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR4_WOFFSET                      0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR4_NORELOAD                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR4_RELOAD                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT                        MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR3_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RANGE                        3:3
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR3_MSB                  MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR3_LSB                  MK_SHIFT_CONST(3)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR3_WOFFSET                      0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR3_NORELOAD                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR3_RELOAD                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR2_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RANGE                        2:2
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR2_MSB                  MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR2_LSB                  MK_SHIFT_CONST(2)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR2_WOFFSET                      0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR2_NORELOAD                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR2_RELOAD                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RANGE                        1:1
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR1_WOFFSET                      0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR1_NORELOAD                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR1_RELOAD                       MK_ENUM_CONST(1)
+
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR0_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SHIFT)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RANGE                        0:0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR0_MSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR0_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR0_WOFFSET                      0x0
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR0_NORELOAD                     MK_ENUM_CONST(0)
+#define GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0_ERR0_RELOAD                       MK_ENUM_CONST(1)
+
+
+// Reserved address 0xff54
+
+// Reserved address 0xff58
+
+// Reserved address 0xff5c
+
+// Register GPCDMA_CHANNEL_CH0_CSR_0
+#define GPCDMA_CHANNEL_CH0_CSR_0                        MK_ADDR_CONST(0x10000)
+#define GPCDMA_CHANNEL_CH0_CSR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH0_CSR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH0_CSR_0_SCR                    SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_CSR_0_SCRREG                         GPCDMA_SCR_SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_CSR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH0_CSR_0_RESET_VAL                      MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH0_CSR_0_RESET_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH0_CSR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_READ_MASK                      MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH0_CSR_0_WRITE_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ENB_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ENB_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ENB_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH0_CSR_0_ENB_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ENB_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ENB_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH0_CSR_0_ENB_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ENB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ENB_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ENB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ENB_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ENB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ENB_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ENB_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH0_CSR_0_IE_EOC_SHIFT                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IE_EOC_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IE_EOC_RANGE                   30:30
+#define GPCDMA_CHANNEL_CH0_CSR_0_IE_EOC_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IE_EOC_LSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IE_EOC_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH0_CSR_0_IE_EOC_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IE_EOC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IE_EOC_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IE_EOC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IE_EOC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IE_EOC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IE_EOC_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IE_EOC_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH0_CSR_0_ONCE_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ONCE_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ONCE_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH0_CSR_0_ONCE_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ONCE_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ONCE_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH0_CSR_0_ONCE_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ONCE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ONCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ONCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ONCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ONCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ONCE_CYCLIC_MODE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_ONCE_SINGLE_BLOCK                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH0_CSR_0_FC_MODE_SHIFT                  MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH0_CSR_0_FC_MODE_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH0_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH0_CSR_0_FC_MODE_RANGE                  25:24
+#define GPCDMA_CHANNEL_CH0_CSR_0_FC_MODE_MSB                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH0_CSR_0_FC_MODE_LSB                    MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH0_CSR_0_FC_MODE_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH0_CSR_0_FC_MODE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_FC_MODE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH0_CSR_0_FC_MODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_FC_MODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_FC_MODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_FC_MODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_CSR_0_FC_MODE_NO_MMIO                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_FC_MODE_ONE_MMIO                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH0_CSR_0_FC_MODE_TWO_MMIO                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH0_CSR_0_FC_MODE_FOUR_MMIO                      MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_RANGE                 23:21
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_IO2MEM_NO_FC                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_IO2MEM_FC                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_MEM2IO_NO_FC                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_MEM2IO_FC                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_MEM2MEM                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_RSVD                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH0_CSR_0_DMA_MODE_FIXED_PAT                     MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_FIELD                  MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_RANGE                  20:16
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_0                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_1                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_2                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_3                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_4                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_5                       MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_6                       MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_7                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_8                       MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_9                       MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_10                      MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_11                      MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_12                      MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_13                      MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_14                      MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_15                      MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_16                      MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_17                      MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_18                      MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_19                      MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_20                      MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_21                      MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_22                      MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_23                      MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_24                      MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_25                      MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_26                      MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_27                      MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_28                      MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_29_RSVD                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_30                      MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_31                      MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH0_CSR_0_REQ_SEL_RSVD                   MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH0_CSR_0_IRQ_MASK_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IRQ_MASK_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IRQ_MASK_RANGE                 15:15
+#define GPCDMA_CHANNEL_CH0_CSR_0_IRQ_MASK_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IRQ_MASK_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IRQ_MASK_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH0_CSR_0_IRQ_MASK_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IRQ_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IRQ_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IRQ_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IRQ_MASK_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_IRQ_MASK_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH0_CSR_0_WEIGHT_SHIFT                   MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH0_CSR_0_WEIGHT_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH0_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH0_CSR_0_WEIGHT_RANGE                   13:10
+#define GPCDMA_CHANNEL_CH0_CSR_0_WEIGHT_MSB                     MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH0_CSR_0_WEIGHT_LSB                     MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH0_CSR_0_WEIGHT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH0_CSR_0_WEIGHT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_CSR_0_WEIGHT_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH0_CSR_0_WEIGHT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_WEIGHT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_WEIGHT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSR_0_WEIGHT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH0_STA_0
+#define GPCDMA_CHANNEL_CH0_STA_0                        MK_ADDR_CONST(0x10004)
+#define GPCDMA_CHANNEL_CH0_STA_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH0_STA_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH0_STA_0_SCR                    SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_STA_0_SCRREG                         GPCDMA_SCR_SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_STA_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH0_STA_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_RESET_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH0_STA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_READ_MASK                      MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH0_STA_0_WRITE_MASK                     MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH0_STA_0_BSY_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_STA_0_BSY_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH0_STA_0_BSY_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH0_STA_0_BSY_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_STA_0_BSY_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_STA_0_BSY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH0_STA_0_BSY_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_BSY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_BSY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_BSY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_BSY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_BSY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_BSY_WAIT                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_STA_0_BSY_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH0_STA_0_ISE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH0_STA_0_ISE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH0_STA_0_ISE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH0_STA_0_ISE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH0_STA_0_ISE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH0_STA_0_ISE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH0_STA_0_ISE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_ISE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_ISE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_ISE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_ISE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_ISE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_ISE_EOC_NO_INTR                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_STA_0_ISE_EOC_INTR                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH0_STA_0_PING_PONG_STA_SHIFT                    MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH0_STA_0_PING_PONG_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH0_STA_0_PING_PONG_STA_RANGE                    28:28
+#define GPCDMA_CHANNEL_CH0_STA_0_PING_PONG_STA_MSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH0_STA_0_PING_PONG_STA_LSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH0_STA_0_PING_PONG_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH0_STA_0_PING_PONG_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_PING_PONG_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_PING_PONG_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_PING_PONG_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_PING_PONG_STA_PING_INTR_STA                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_STA_0_PING_PONG_STA_PONG_INTR_STA                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH0_STA_0_DMA_ACTIVITY_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH0_STA_0_DMA_ACTIVITY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH0_STA_0_DMA_ACTIVITY_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH0_STA_0_DMA_ACTIVITY_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH0_STA_0_DMA_ACTIVITY_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH0_STA_0_DMA_ACTIVITY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH0_STA_0_DMA_ACTIVITY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_DMA_ACTIVITY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_DMA_ACTIVITY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_DMA_ACTIVITY_IDLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_STA_0_DMA_ACTIVITY_BUSY                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_SHIFT                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_RANGE                    26:26
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_LSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_RX_SHIFT                       MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_RX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_RX_RANGE                       25:25
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_RX_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_RX_LSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_RX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_RX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_RX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_RX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_RX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_RX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_RX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_TX_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_TX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_TX_RANGE                       24:24
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_TX_MSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_TX_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_TX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_TX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_TX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_TX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_TX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_TX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_STA_0_CHANNEL_TX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH0_STA_0_IRQ_INTR_STA_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH0_STA_0_IRQ_INTR_STA_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH0_STA_0_IRQ_INTR_STA_RANGE                     23:23
+#define GPCDMA_CHANNEL_CH0_STA_0_IRQ_INTR_STA_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH0_STA_0_IRQ_INTR_STA_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH0_STA_0_IRQ_INTR_STA_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH0_STA_0_IRQ_INTR_STA_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_IRQ_INTR_STA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_IRQ_INTR_STA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_IRQ_INTR_STA_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_STA_0_IRQ_INTR_STA_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH0_STA_0_TRIG_STA_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH0_STA_0_TRIG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH0_STA_0_TRIG_STA_RANGE                 21:21
+#define GPCDMA_CHANNEL_CH0_STA_0_TRIG_STA_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH0_STA_0_TRIG_STA_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH0_STA_0_TRIG_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH0_STA_0_TRIG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_TRIG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_TRIG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_TRIG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_TRIG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_TRIG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_TRIG_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_STA_0_TRIG_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH0_STA_0_INTR_STA_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH0_STA_0_INTR_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH0_STA_0_INTR_STA_RANGE                 20:20
+#define GPCDMA_CHANNEL_CH0_STA_0_INTR_STA_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH0_STA_0_INTR_STA_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH0_STA_0_INTR_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH0_STA_0_INTR_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_INTR_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_INTR_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_INTR_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_INTR_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_STA_0_INTR_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_STA_0_INTR_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_STA_0_INTR_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH0_CSRE_0
+#define GPCDMA_CHANNEL_CH0_CSRE_0                       MK_ADDR_CONST(0x10008)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH0_CSRE_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH0_CSRE_0_SCR                   SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_CSRE_0_SCRREG                        GPCDMA_SCR_SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_CSRE_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH0_CSRE_0_RESET_VAL                     MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_RESET_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_READ_MASK                     MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_WRITE_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_SHIFT                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_FIELD                        MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_RANGE                        19:14
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_LSB                  MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_DEFAULT                      MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH0                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH1                  MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH2                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH3                  MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH4                  MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH5                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH6                  MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH7                  MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH8                  MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH9                  MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH10                 MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH11                 MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH12                 MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH13                 MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH14                 MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH15                 MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH16                 MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH17                 MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH18                 MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH19                 MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH20                 MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH21                 MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH22                 MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH23                 MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH24                 MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH25                 MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH26                 MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH27                 MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH28                 MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH29                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH30                 MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH31                 MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH0_CSRE_0_TRIG_SEL_RSVD                 MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH0_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0                    MK_ADDR_CONST(0x1000c)
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_SCR                        SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH0_DST_PTR_0
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0                    MK_ADDR_CONST(0x10010)
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_SCR                        SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_DST_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_DST_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH0_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_DST_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_DST_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_DST_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_DST_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_DST_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_DST_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_DST_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_DST_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0                 MK_ADDR_CONST(0x10014)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_SCR                     SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_SCRREG                  GPCDMA_SCR_SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_RESET_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_READ_MASK                       MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_RANGE                        23:16
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_LSB                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                        7:0
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_MSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH0_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0                     MK_ADDR_CONST(0x10018)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_SCR                         SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_SCRREG                      GPCDMA_SCR_SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_RESET_VAL                   MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_RANGE                  31:31
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_FIELD                    MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_RANGE                    30:25
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_MSB                      MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                     MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_BURST_SHIFT                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_BURST_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_BURST_RANGE                      24:23
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_BURST_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_BURST_LSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_BURST_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_BURST_DEFAULT                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_BURST_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_BURST_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                  MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                 22:20
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                 19:17
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_RANGE                      16:16
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_MSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_PROT_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_PROT_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_PROT_RANGE                       15:14
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_PROT_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_PROT_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_PROT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_PROT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_PROT_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_PROT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID1_SHIFT                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID1_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID1_RANGE                     13:7
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID1_MSB                       MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID1_LSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID1_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID1_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID1_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID0_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID0_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID0_RANGE                     6:0
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID0_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID0_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID0_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID0_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID0_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH0_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0                   MK_ADDR_CONST(0x1001c)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_SCR                       SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_SCRREG                    GPCDMA_SCR_SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_RESET_VAL                         MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_RESET_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_READ_MASK                         MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_WRITE_MASK                        MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                      30:28
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                        MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                    MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                       MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                      27:27
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_RANGE                  26:23
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_MSB                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DEFAULT                        MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                      MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                      18:16
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                        MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                     MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                    MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_SHIFT                   MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_RANGE                   8:7
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_MSB                     MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_LSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                       MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                       6:0
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH0_WCOUNT_0
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0                     MK_ADDR_CONST(0x10020)
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_SCR                         SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_SCRREG                      GPCDMA_SCR_SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_WCOUNT_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_WCOUNT_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH0_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_WCOUNT_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_WCOUNT_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_WCOUNT_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_WCOUNT_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_WCOUNT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_WCOUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_WCOUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_WCOUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0                       MK_ADDR_CONST(0x10024)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_SCR                   SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_SCRREG                        GPCDMA_SCR_SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                  31:0
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0                       MK_ADDR_CONST(0x10028)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_SCR                   SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x1002c
+
+// Register GPCDMA_CHANNEL_CH0_ERR_STA_0
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0                    MK_ADDR_CONST(0x10030)
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_SCR                        SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_SCRREG                     GPCDMA_SCR_SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH0_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0                  MK_ADDR_CONST(0x10034)
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_SCR                      SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_SCRREG                   GPCDMA_SCR_SCR_CH0_0
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH0_TZ_0
+#define GPCDMA_CHANNEL_CH0_TZ_0                 MK_ADDR_CONST(0x10038)
+#define GPCDMA_CHANNEL_CH0_TZ_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH0_TZ_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH0_TZ_0_SCR                     SCR_TZ_0
+#define GPCDMA_CHANNEL_CH0_TZ_0_SCRREG                  GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH0_TZ_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH0_TZ_0_RESET_VAL                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH0_TZ_0_RESET_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH0_TZ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_TZ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_TZ_0_READ_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH0_TZ_0_WRITE_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MC_PROT_1_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MC_PROT_1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MC_PROT_1_RANGE                 1:1
+#define GPCDMA_CHANNEL_CH0_TZ_0_MC_PROT_1_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MC_PROT_1_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MC_PROT_1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH0_TZ_0_MC_PROT_1_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MC_PROT_1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MC_PROT_1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MC_PROT_1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH0_TZ_0_MMIO_PROT_1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MMIO_PROT_1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH0_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MMIO_PROT_1_RANGE                       0:0
+#define GPCDMA_CHANNEL_CH0_TZ_0_MMIO_PROT_1_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MMIO_PROT_1_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MMIO_PROT_1_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH0_TZ_0_MMIO_PROT_1_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MMIO_PROT_1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MMIO_PROT_1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH0_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH1_CSR_0
+#define GPCDMA_CHANNEL_CH1_CSR_0                        MK_ADDR_CONST(0x20000)
+#define GPCDMA_CHANNEL_CH1_CSR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH1_CSR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH1_CSR_0_SCR                    SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_CSR_0_SCRREG                         GPCDMA_SCR_SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_CSR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH1_CSR_0_RESET_VAL                      MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH1_CSR_0_RESET_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH1_CSR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_READ_MASK                      MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH1_CSR_0_WRITE_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ENB_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ENB_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ENB_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH1_CSR_0_ENB_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ENB_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ENB_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH1_CSR_0_ENB_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ENB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ENB_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ENB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ENB_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ENB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ENB_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ENB_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH1_CSR_0_IE_EOC_SHIFT                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IE_EOC_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IE_EOC_RANGE                   30:30
+#define GPCDMA_CHANNEL_CH1_CSR_0_IE_EOC_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IE_EOC_LSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IE_EOC_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH1_CSR_0_IE_EOC_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IE_EOC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IE_EOC_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IE_EOC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IE_EOC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IE_EOC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IE_EOC_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IE_EOC_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH1_CSR_0_ONCE_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ONCE_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ONCE_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH1_CSR_0_ONCE_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ONCE_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ONCE_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH1_CSR_0_ONCE_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ONCE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ONCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ONCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ONCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ONCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ONCE_CYCLIC_MODE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_ONCE_SINGLE_BLOCK                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH1_CSR_0_FC_MODE_SHIFT                  MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH1_CSR_0_FC_MODE_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH1_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH1_CSR_0_FC_MODE_RANGE                  25:24
+#define GPCDMA_CHANNEL_CH1_CSR_0_FC_MODE_MSB                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH1_CSR_0_FC_MODE_LSB                    MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH1_CSR_0_FC_MODE_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH1_CSR_0_FC_MODE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_FC_MODE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH1_CSR_0_FC_MODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_FC_MODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_FC_MODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_FC_MODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_CSR_0_FC_MODE_NO_MMIO                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_FC_MODE_ONE_MMIO                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH1_CSR_0_FC_MODE_TWO_MMIO                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH1_CSR_0_FC_MODE_FOUR_MMIO                      MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_RANGE                 23:21
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_IO2MEM_NO_FC                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_IO2MEM_FC                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_MEM2IO_NO_FC                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_MEM2IO_FC                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_MEM2MEM                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_RSVD                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH1_CSR_0_DMA_MODE_FIXED_PAT                     MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_FIELD                  MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_RANGE                  20:16
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_0                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_1                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_2                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_3                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_4                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_5                       MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_6                       MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_7                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_8                       MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_9                       MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_10                      MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_11                      MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_12                      MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_13                      MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_14                      MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_15                      MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_16                      MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_17                      MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_18                      MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_19                      MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_20                      MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_21                      MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_22                      MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_23                      MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_24                      MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_25                      MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_26                      MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_27                      MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_28                      MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_29_RSVD                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_30                      MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_31                      MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH1_CSR_0_REQ_SEL_RSVD                   MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH1_CSR_0_IRQ_MASK_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IRQ_MASK_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IRQ_MASK_RANGE                 15:15
+#define GPCDMA_CHANNEL_CH1_CSR_0_IRQ_MASK_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IRQ_MASK_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IRQ_MASK_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH1_CSR_0_IRQ_MASK_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IRQ_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IRQ_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IRQ_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IRQ_MASK_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_IRQ_MASK_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH1_CSR_0_WEIGHT_SHIFT                   MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH1_CSR_0_WEIGHT_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH1_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH1_CSR_0_WEIGHT_RANGE                   13:10
+#define GPCDMA_CHANNEL_CH1_CSR_0_WEIGHT_MSB                     MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH1_CSR_0_WEIGHT_LSB                     MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH1_CSR_0_WEIGHT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH1_CSR_0_WEIGHT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_CSR_0_WEIGHT_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH1_CSR_0_WEIGHT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_WEIGHT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_WEIGHT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSR_0_WEIGHT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH1_STA_0
+#define GPCDMA_CHANNEL_CH1_STA_0                        MK_ADDR_CONST(0x20004)
+#define GPCDMA_CHANNEL_CH1_STA_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH1_STA_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH1_STA_0_SCR                    SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_STA_0_SCRREG                         GPCDMA_SCR_SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_STA_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH1_STA_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_RESET_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH1_STA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_READ_MASK                      MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH1_STA_0_WRITE_MASK                     MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH1_STA_0_BSY_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_STA_0_BSY_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH1_STA_0_BSY_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH1_STA_0_BSY_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_STA_0_BSY_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_STA_0_BSY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH1_STA_0_BSY_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_BSY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_BSY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_BSY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_BSY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_BSY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_BSY_WAIT                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_STA_0_BSY_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH1_STA_0_ISE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH1_STA_0_ISE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH1_STA_0_ISE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH1_STA_0_ISE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH1_STA_0_ISE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH1_STA_0_ISE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH1_STA_0_ISE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_ISE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_ISE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_ISE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_ISE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_ISE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_ISE_EOC_NO_INTR                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_STA_0_ISE_EOC_INTR                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH1_STA_0_PING_PONG_STA_SHIFT                    MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH1_STA_0_PING_PONG_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH1_STA_0_PING_PONG_STA_RANGE                    28:28
+#define GPCDMA_CHANNEL_CH1_STA_0_PING_PONG_STA_MSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH1_STA_0_PING_PONG_STA_LSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH1_STA_0_PING_PONG_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH1_STA_0_PING_PONG_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_PING_PONG_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_PING_PONG_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_PING_PONG_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_PING_PONG_STA_PING_INTR_STA                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_STA_0_PING_PONG_STA_PONG_INTR_STA                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH1_STA_0_DMA_ACTIVITY_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH1_STA_0_DMA_ACTIVITY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH1_STA_0_DMA_ACTIVITY_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH1_STA_0_DMA_ACTIVITY_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH1_STA_0_DMA_ACTIVITY_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH1_STA_0_DMA_ACTIVITY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH1_STA_0_DMA_ACTIVITY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_DMA_ACTIVITY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_DMA_ACTIVITY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_DMA_ACTIVITY_IDLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_STA_0_DMA_ACTIVITY_BUSY                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_SHIFT                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_RANGE                    26:26
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_LSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_RX_SHIFT                       MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_RX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_RX_RANGE                       25:25
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_RX_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_RX_LSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_RX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_RX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_RX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_RX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_RX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_RX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_RX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_TX_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_TX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_TX_RANGE                       24:24
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_TX_MSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_TX_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_TX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_TX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_TX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_TX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_TX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_TX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_STA_0_CHANNEL_TX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH1_STA_0_IRQ_INTR_STA_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH1_STA_0_IRQ_INTR_STA_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH1_STA_0_IRQ_INTR_STA_RANGE                     23:23
+#define GPCDMA_CHANNEL_CH1_STA_0_IRQ_INTR_STA_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH1_STA_0_IRQ_INTR_STA_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH1_STA_0_IRQ_INTR_STA_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH1_STA_0_IRQ_INTR_STA_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_IRQ_INTR_STA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_IRQ_INTR_STA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_IRQ_INTR_STA_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_STA_0_IRQ_INTR_STA_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH1_STA_0_TRIG_STA_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH1_STA_0_TRIG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH1_STA_0_TRIG_STA_RANGE                 21:21
+#define GPCDMA_CHANNEL_CH1_STA_0_TRIG_STA_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH1_STA_0_TRIG_STA_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH1_STA_0_TRIG_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH1_STA_0_TRIG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_TRIG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_TRIG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_TRIG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_TRIG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_TRIG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_TRIG_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_STA_0_TRIG_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH1_STA_0_INTR_STA_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH1_STA_0_INTR_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH1_STA_0_INTR_STA_RANGE                 20:20
+#define GPCDMA_CHANNEL_CH1_STA_0_INTR_STA_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH1_STA_0_INTR_STA_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH1_STA_0_INTR_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH1_STA_0_INTR_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_INTR_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_INTR_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_INTR_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_INTR_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_STA_0_INTR_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_STA_0_INTR_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_STA_0_INTR_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH1_CSRE_0
+#define GPCDMA_CHANNEL_CH1_CSRE_0                       MK_ADDR_CONST(0x20008)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH1_CSRE_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH1_CSRE_0_SCR                   SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_CSRE_0_SCRREG                        GPCDMA_SCR_SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_CSRE_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH1_CSRE_0_RESET_VAL                     MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_RESET_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_READ_MASK                     MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_WRITE_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_SHIFT                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_FIELD                        MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_RANGE                        19:14
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_LSB                  MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_DEFAULT                      MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH0                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH1                  MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH2                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH3                  MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH4                  MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH5                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH6                  MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH7                  MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH8                  MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH9                  MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH10                 MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH11                 MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH12                 MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH13                 MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH14                 MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH15                 MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH16                 MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH17                 MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH18                 MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH19                 MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH20                 MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH21                 MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH22                 MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH23                 MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH24                 MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH25                 MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH26                 MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH27                 MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH28                 MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH29                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH30                 MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH31                 MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH1_CSRE_0_TRIG_SEL_RSVD                 MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH1_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0                    MK_ADDR_CONST(0x2000c)
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_SCR                        SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH1_DST_PTR_0
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0                    MK_ADDR_CONST(0x20010)
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_SCR                        SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_DST_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_DST_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH1_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_DST_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_DST_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_DST_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_DST_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_DST_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_DST_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_DST_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_DST_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0                 MK_ADDR_CONST(0x20014)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_SCR                     SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_SCRREG                  GPCDMA_SCR_SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_RESET_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_READ_MASK                       MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_RANGE                        23:16
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_LSB                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                        7:0
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_MSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH1_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0                     MK_ADDR_CONST(0x20018)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_SCR                         SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_SCRREG                      GPCDMA_SCR_SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_RESET_VAL                   MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_RANGE                  31:31
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_FIELD                    MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_RANGE                    30:25
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_MSB                      MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                     MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_BURST_SHIFT                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_BURST_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_BURST_RANGE                      24:23
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_BURST_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_BURST_LSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_BURST_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_BURST_DEFAULT                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_BURST_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_BURST_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                  MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                 22:20
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                 19:17
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_RANGE                      16:16
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_MSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_PROT_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_PROT_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_PROT_RANGE                       15:14
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_PROT_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_PROT_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_PROT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_PROT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_PROT_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_PROT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID1_SHIFT                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID1_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID1_RANGE                     13:7
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID1_MSB                       MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID1_LSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID1_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID1_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID1_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID0_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID0_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID0_RANGE                     6:0
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID0_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID0_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID0_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID0_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID0_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH1_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0                   MK_ADDR_CONST(0x2001c)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_SCR                       SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_SCRREG                    GPCDMA_SCR_SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_RESET_VAL                         MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_RESET_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_READ_MASK                         MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_WRITE_MASK                        MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                      30:28
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                        MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                    MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                       MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                      27:27
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_RANGE                  26:23
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_MSB                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DEFAULT                        MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                      MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                      18:16
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                        MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                     MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                    MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_SHIFT                   MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_RANGE                   8:7
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_MSB                     MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_LSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                       MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                       6:0
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH1_WCOUNT_0
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0                     MK_ADDR_CONST(0x20020)
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_SCR                         SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_SCRREG                      GPCDMA_SCR_SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_WCOUNT_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_WCOUNT_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH1_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_WCOUNT_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_WCOUNT_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_WCOUNT_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_WCOUNT_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_WCOUNT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_WCOUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_WCOUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_WCOUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0                       MK_ADDR_CONST(0x20024)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_SCR                   SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_SCRREG                        GPCDMA_SCR_SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                  31:0
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0                       MK_ADDR_CONST(0x20028)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_SCR                   SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x2002c
+
+// Register GPCDMA_CHANNEL_CH1_ERR_STA_0
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0                    MK_ADDR_CONST(0x20030)
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_SCR                        SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_SCRREG                     GPCDMA_SCR_SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH1_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0                  MK_ADDR_CONST(0x20034)
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_SCR                      SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_SCRREG                   GPCDMA_SCR_SCR_CH1_0
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH1_TZ_0
+#define GPCDMA_CHANNEL_CH1_TZ_0                 MK_ADDR_CONST(0x20038)
+#define GPCDMA_CHANNEL_CH1_TZ_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH1_TZ_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH1_TZ_0_SCR                     SCR_TZ_0
+#define GPCDMA_CHANNEL_CH1_TZ_0_SCRREG                  GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH1_TZ_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH1_TZ_0_RESET_VAL                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH1_TZ_0_RESET_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH1_TZ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_TZ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_TZ_0_READ_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH1_TZ_0_WRITE_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MC_PROT_1_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MC_PROT_1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MC_PROT_1_RANGE                 1:1
+#define GPCDMA_CHANNEL_CH1_TZ_0_MC_PROT_1_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MC_PROT_1_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MC_PROT_1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH1_TZ_0_MC_PROT_1_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MC_PROT_1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MC_PROT_1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MC_PROT_1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH1_TZ_0_MMIO_PROT_1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MMIO_PROT_1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH1_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MMIO_PROT_1_RANGE                       0:0
+#define GPCDMA_CHANNEL_CH1_TZ_0_MMIO_PROT_1_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MMIO_PROT_1_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MMIO_PROT_1_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH1_TZ_0_MMIO_PROT_1_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MMIO_PROT_1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MMIO_PROT_1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH1_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH2_CSR_0
+#define GPCDMA_CHANNEL_CH2_CSR_0                        MK_ADDR_CONST(0x30000)
+#define GPCDMA_CHANNEL_CH2_CSR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH2_CSR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH2_CSR_0_SCR                    SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_CSR_0_SCRREG                         GPCDMA_SCR_SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_CSR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH2_CSR_0_RESET_VAL                      MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH2_CSR_0_RESET_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH2_CSR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_READ_MASK                      MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH2_CSR_0_WRITE_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ENB_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ENB_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ENB_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH2_CSR_0_ENB_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ENB_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ENB_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH2_CSR_0_ENB_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ENB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ENB_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ENB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ENB_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ENB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ENB_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ENB_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH2_CSR_0_IE_EOC_SHIFT                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IE_EOC_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IE_EOC_RANGE                   30:30
+#define GPCDMA_CHANNEL_CH2_CSR_0_IE_EOC_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IE_EOC_LSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IE_EOC_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH2_CSR_0_IE_EOC_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IE_EOC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IE_EOC_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IE_EOC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IE_EOC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IE_EOC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IE_EOC_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IE_EOC_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH2_CSR_0_ONCE_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ONCE_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ONCE_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH2_CSR_0_ONCE_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ONCE_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ONCE_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH2_CSR_0_ONCE_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ONCE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ONCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ONCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ONCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ONCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ONCE_CYCLIC_MODE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_ONCE_SINGLE_BLOCK                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH2_CSR_0_FC_MODE_SHIFT                  MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH2_CSR_0_FC_MODE_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH2_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH2_CSR_0_FC_MODE_RANGE                  25:24
+#define GPCDMA_CHANNEL_CH2_CSR_0_FC_MODE_MSB                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH2_CSR_0_FC_MODE_LSB                    MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH2_CSR_0_FC_MODE_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH2_CSR_0_FC_MODE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_FC_MODE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH2_CSR_0_FC_MODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_FC_MODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_FC_MODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_FC_MODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_CSR_0_FC_MODE_NO_MMIO                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_FC_MODE_ONE_MMIO                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH2_CSR_0_FC_MODE_TWO_MMIO                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH2_CSR_0_FC_MODE_FOUR_MMIO                      MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_RANGE                 23:21
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_IO2MEM_NO_FC                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_IO2MEM_FC                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_MEM2IO_NO_FC                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_MEM2IO_FC                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_MEM2MEM                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_RSVD                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH2_CSR_0_DMA_MODE_FIXED_PAT                     MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_FIELD                  MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_RANGE                  20:16
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_0                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_1                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_2                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_3                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_4                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_5                       MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_6                       MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_7                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_8                       MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_9                       MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_10                      MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_11                      MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_12                      MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_13                      MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_14                      MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_15                      MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_16                      MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_17                      MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_18                      MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_19                      MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_20                      MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_21                      MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_22                      MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_23                      MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_24                      MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_25                      MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_26                      MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_27                      MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_28                      MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_29_RSVD                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_30                      MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_31                      MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH2_CSR_0_REQ_SEL_RSVD                   MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH2_CSR_0_IRQ_MASK_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IRQ_MASK_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IRQ_MASK_RANGE                 15:15
+#define GPCDMA_CHANNEL_CH2_CSR_0_IRQ_MASK_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IRQ_MASK_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IRQ_MASK_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH2_CSR_0_IRQ_MASK_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IRQ_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IRQ_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IRQ_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IRQ_MASK_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_IRQ_MASK_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH2_CSR_0_WEIGHT_SHIFT                   MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH2_CSR_0_WEIGHT_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH2_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH2_CSR_0_WEIGHT_RANGE                   13:10
+#define GPCDMA_CHANNEL_CH2_CSR_0_WEIGHT_MSB                     MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH2_CSR_0_WEIGHT_LSB                     MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH2_CSR_0_WEIGHT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH2_CSR_0_WEIGHT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_CSR_0_WEIGHT_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH2_CSR_0_WEIGHT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_WEIGHT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_WEIGHT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSR_0_WEIGHT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH2_STA_0
+#define GPCDMA_CHANNEL_CH2_STA_0                        MK_ADDR_CONST(0x30004)
+#define GPCDMA_CHANNEL_CH2_STA_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH2_STA_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH2_STA_0_SCR                    SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_STA_0_SCRREG                         GPCDMA_SCR_SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_STA_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH2_STA_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_RESET_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH2_STA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_READ_MASK                      MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH2_STA_0_WRITE_MASK                     MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH2_STA_0_BSY_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_STA_0_BSY_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH2_STA_0_BSY_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH2_STA_0_BSY_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_STA_0_BSY_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_STA_0_BSY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH2_STA_0_BSY_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_BSY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_BSY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_BSY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_BSY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_BSY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_BSY_WAIT                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_STA_0_BSY_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH2_STA_0_ISE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH2_STA_0_ISE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH2_STA_0_ISE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH2_STA_0_ISE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH2_STA_0_ISE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH2_STA_0_ISE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH2_STA_0_ISE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_ISE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_ISE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_ISE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_ISE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_ISE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_ISE_EOC_NO_INTR                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_STA_0_ISE_EOC_INTR                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH2_STA_0_PING_PONG_STA_SHIFT                    MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH2_STA_0_PING_PONG_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH2_STA_0_PING_PONG_STA_RANGE                    28:28
+#define GPCDMA_CHANNEL_CH2_STA_0_PING_PONG_STA_MSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH2_STA_0_PING_PONG_STA_LSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH2_STA_0_PING_PONG_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH2_STA_0_PING_PONG_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_PING_PONG_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_PING_PONG_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_PING_PONG_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_PING_PONG_STA_PING_INTR_STA                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_STA_0_PING_PONG_STA_PONG_INTR_STA                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH2_STA_0_DMA_ACTIVITY_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH2_STA_0_DMA_ACTIVITY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH2_STA_0_DMA_ACTIVITY_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH2_STA_0_DMA_ACTIVITY_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH2_STA_0_DMA_ACTIVITY_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH2_STA_0_DMA_ACTIVITY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH2_STA_0_DMA_ACTIVITY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_DMA_ACTIVITY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_DMA_ACTIVITY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_DMA_ACTIVITY_IDLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_STA_0_DMA_ACTIVITY_BUSY                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_SHIFT                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_RANGE                    26:26
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_LSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_RX_SHIFT                       MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_RX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_RX_RANGE                       25:25
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_RX_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_RX_LSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_RX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_RX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_RX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_RX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_RX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_RX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_RX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_TX_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_TX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_TX_RANGE                       24:24
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_TX_MSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_TX_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_TX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_TX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_TX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_TX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_TX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_TX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_STA_0_CHANNEL_TX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH2_STA_0_IRQ_INTR_STA_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH2_STA_0_IRQ_INTR_STA_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH2_STA_0_IRQ_INTR_STA_RANGE                     23:23
+#define GPCDMA_CHANNEL_CH2_STA_0_IRQ_INTR_STA_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH2_STA_0_IRQ_INTR_STA_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH2_STA_0_IRQ_INTR_STA_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH2_STA_0_IRQ_INTR_STA_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_IRQ_INTR_STA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_IRQ_INTR_STA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_IRQ_INTR_STA_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_STA_0_IRQ_INTR_STA_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH2_STA_0_TRIG_STA_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH2_STA_0_TRIG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH2_STA_0_TRIG_STA_RANGE                 21:21
+#define GPCDMA_CHANNEL_CH2_STA_0_TRIG_STA_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH2_STA_0_TRIG_STA_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH2_STA_0_TRIG_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH2_STA_0_TRIG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_TRIG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_TRIG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_TRIG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_TRIG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_TRIG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_TRIG_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_STA_0_TRIG_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH2_STA_0_INTR_STA_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH2_STA_0_INTR_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH2_STA_0_INTR_STA_RANGE                 20:20
+#define GPCDMA_CHANNEL_CH2_STA_0_INTR_STA_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH2_STA_0_INTR_STA_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH2_STA_0_INTR_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH2_STA_0_INTR_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_INTR_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_INTR_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_INTR_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_INTR_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_STA_0_INTR_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_STA_0_INTR_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_STA_0_INTR_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH2_CSRE_0
+#define GPCDMA_CHANNEL_CH2_CSRE_0                       MK_ADDR_CONST(0x30008)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH2_CSRE_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH2_CSRE_0_SCR                   SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_CSRE_0_SCRREG                        GPCDMA_SCR_SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_CSRE_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH2_CSRE_0_RESET_VAL                     MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_RESET_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_READ_MASK                     MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_WRITE_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_SHIFT                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_FIELD                        MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_RANGE                        19:14
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_LSB                  MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_DEFAULT                      MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH0                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH1                  MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH2                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH3                  MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH4                  MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH5                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH6                  MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH7                  MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH8                  MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH9                  MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH10                 MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH11                 MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH12                 MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH13                 MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH14                 MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH15                 MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH16                 MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH17                 MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH18                 MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH19                 MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH20                 MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH21                 MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH22                 MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH23                 MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH24                 MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH25                 MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH26                 MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH27                 MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH28                 MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH29                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH30                 MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH31                 MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH2_CSRE_0_TRIG_SEL_RSVD                 MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH2_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0                    MK_ADDR_CONST(0x3000c)
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_SCR                        SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH2_DST_PTR_0
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0                    MK_ADDR_CONST(0x30010)
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_SCR                        SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_DST_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_DST_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH2_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_DST_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_DST_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_DST_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_DST_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_DST_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_DST_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_DST_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_DST_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0                 MK_ADDR_CONST(0x30014)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_SCR                     SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_SCRREG                  GPCDMA_SCR_SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_RESET_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_READ_MASK                       MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_RANGE                        23:16
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_LSB                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                        7:0
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_MSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH2_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0                     MK_ADDR_CONST(0x30018)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_SCR                         SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_SCRREG                      GPCDMA_SCR_SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_RESET_VAL                   MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_RANGE                  31:31
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_FIELD                    MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_RANGE                    30:25
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_MSB                      MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                     MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_BURST_SHIFT                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_BURST_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_BURST_RANGE                      24:23
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_BURST_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_BURST_LSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_BURST_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_BURST_DEFAULT                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_BURST_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_BURST_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                  MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                 22:20
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                 19:17
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_RANGE                      16:16
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_MSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_PROT_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_PROT_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_PROT_RANGE                       15:14
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_PROT_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_PROT_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_PROT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_PROT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_PROT_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_PROT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID1_SHIFT                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID1_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID1_RANGE                     13:7
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID1_MSB                       MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID1_LSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID1_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID1_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID1_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID0_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID0_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID0_RANGE                     6:0
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID0_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID0_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID0_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID0_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID0_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH2_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0                   MK_ADDR_CONST(0x3001c)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_SCR                       SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_SCRREG                    GPCDMA_SCR_SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_RESET_VAL                         MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_RESET_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_READ_MASK                         MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_WRITE_MASK                        MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                      30:28
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                        MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                    MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                       MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                      27:27
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_RANGE                  26:23
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_MSB                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DEFAULT                        MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                      MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                      18:16
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                        MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                     MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                    MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_SHIFT                   MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_RANGE                   8:7
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_MSB                     MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_LSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                       MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                       6:0
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH2_WCOUNT_0
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0                     MK_ADDR_CONST(0x30020)
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_SCR                         SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_SCRREG                      GPCDMA_SCR_SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_WCOUNT_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_WCOUNT_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH2_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_WCOUNT_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_WCOUNT_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_WCOUNT_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_WCOUNT_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_WCOUNT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_WCOUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_WCOUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_WCOUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0                       MK_ADDR_CONST(0x30024)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_SCR                   SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_SCRREG                        GPCDMA_SCR_SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                  31:0
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0                       MK_ADDR_CONST(0x30028)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_SCR                   SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x3002c
+
+// Register GPCDMA_CHANNEL_CH2_ERR_STA_0
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0                    MK_ADDR_CONST(0x30030)
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_SCR                        SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_SCRREG                     GPCDMA_SCR_SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH2_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0                  MK_ADDR_CONST(0x30034)
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_SCR                      SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_SCRREG                   GPCDMA_SCR_SCR_CH2_0
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH2_TZ_0
+#define GPCDMA_CHANNEL_CH2_TZ_0                 MK_ADDR_CONST(0x30038)
+#define GPCDMA_CHANNEL_CH2_TZ_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH2_TZ_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH2_TZ_0_SCR                     SCR_TZ_0
+#define GPCDMA_CHANNEL_CH2_TZ_0_SCRREG                  GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH2_TZ_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH2_TZ_0_RESET_VAL                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH2_TZ_0_RESET_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH2_TZ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_TZ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_TZ_0_READ_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH2_TZ_0_WRITE_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MC_PROT_1_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MC_PROT_1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MC_PROT_1_RANGE                 1:1
+#define GPCDMA_CHANNEL_CH2_TZ_0_MC_PROT_1_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MC_PROT_1_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MC_PROT_1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH2_TZ_0_MC_PROT_1_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MC_PROT_1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MC_PROT_1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MC_PROT_1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH2_TZ_0_MMIO_PROT_1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MMIO_PROT_1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH2_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MMIO_PROT_1_RANGE                       0:0
+#define GPCDMA_CHANNEL_CH2_TZ_0_MMIO_PROT_1_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MMIO_PROT_1_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MMIO_PROT_1_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH2_TZ_0_MMIO_PROT_1_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MMIO_PROT_1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MMIO_PROT_1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH2_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH3_CSR_0
+#define GPCDMA_CHANNEL_CH3_CSR_0                        MK_ADDR_CONST(0x40000)
+#define GPCDMA_CHANNEL_CH3_CSR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH3_CSR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH3_CSR_0_SCR                    SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_CSR_0_SCRREG                         GPCDMA_SCR_SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_CSR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH3_CSR_0_RESET_VAL                      MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH3_CSR_0_RESET_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH3_CSR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_READ_MASK                      MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH3_CSR_0_WRITE_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ENB_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ENB_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ENB_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH3_CSR_0_ENB_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ENB_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ENB_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH3_CSR_0_ENB_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ENB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ENB_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ENB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ENB_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ENB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ENB_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ENB_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH3_CSR_0_IE_EOC_SHIFT                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IE_EOC_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IE_EOC_RANGE                   30:30
+#define GPCDMA_CHANNEL_CH3_CSR_0_IE_EOC_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IE_EOC_LSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IE_EOC_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH3_CSR_0_IE_EOC_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IE_EOC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IE_EOC_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IE_EOC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IE_EOC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IE_EOC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IE_EOC_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IE_EOC_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH3_CSR_0_ONCE_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ONCE_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ONCE_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH3_CSR_0_ONCE_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ONCE_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ONCE_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH3_CSR_0_ONCE_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ONCE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ONCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ONCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ONCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ONCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ONCE_CYCLIC_MODE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_ONCE_SINGLE_BLOCK                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH3_CSR_0_FC_MODE_SHIFT                  MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH3_CSR_0_FC_MODE_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH3_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH3_CSR_0_FC_MODE_RANGE                  25:24
+#define GPCDMA_CHANNEL_CH3_CSR_0_FC_MODE_MSB                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH3_CSR_0_FC_MODE_LSB                    MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH3_CSR_0_FC_MODE_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH3_CSR_0_FC_MODE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_FC_MODE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH3_CSR_0_FC_MODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_FC_MODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_FC_MODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_FC_MODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_CSR_0_FC_MODE_NO_MMIO                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_FC_MODE_ONE_MMIO                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH3_CSR_0_FC_MODE_TWO_MMIO                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH3_CSR_0_FC_MODE_FOUR_MMIO                      MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_RANGE                 23:21
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_IO2MEM_NO_FC                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_IO2MEM_FC                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_MEM2IO_NO_FC                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_MEM2IO_FC                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_MEM2MEM                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_RSVD                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH3_CSR_0_DMA_MODE_FIXED_PAT                     MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_FIELD                  MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_RANGE                  20:16
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_0                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_1                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_2                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_3                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_4                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_5                       MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_6                       MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_7                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_8                       MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_9                       MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_10                      MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_11                      MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_12                      MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_13                      MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_14                      MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_15                      MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_16                      MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_17                      MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_18                      MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_19                      MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_20                      MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_21                      MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_22                      MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_23                      MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_24                      MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_25                      MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_26                      MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_27                      MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_28                      MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_29_RSVD                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_30                      MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_31                      MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH3_CSR_0_REQ_SEL_RSVD                   MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH3_CSR_0_IRQ_MASK_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IRQ_MASK_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IRQ_MASK_RANGE                 15:15
+#define GPCDMA_CHANNEL_CH3_CSR_0_IRQ_MASK_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IRQ_MASK_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IRQ_MASK_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH3_CSR_0_IRQ_MASK_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IRQ_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IRQ_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IRQ_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IRQ_MASK_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_IRQ_MASK_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH3_CSR_0_WEIGHT_SHIFT                   MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH3_CSR_0_WEIGHT_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH3_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH3_CSR_0_WEIGHT_RANGE                   13:10
+#define GPCDMA_CHANNEL_CH3_CSR_0_WEIGHT_MSB                     MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH3_CSR_0_WEIGHT_LSB                     MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH3_CSR_0_WEIGHT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH3_CSR_0_WEIGHT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_CSR_0_WEIGHT_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH3_CSR_0_WEIGHT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_WEIGHT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_WEIGHT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSR_0_WEIGHT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH3_STA_0
+#define GPCDMA_CHANNEL_CH3_STA_0                        MK_ADDR_CONST(0x40004)
+#define GPCDMA_CHANNEL_CH3_STA_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH3_STA_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH3_STA_0_SCR                    SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_STA_0_SCRREG                         GPCDMA_SCR_SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_STA_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH3_STA_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_RESET_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH3_STA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_READ_MASK                      MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH3_STA_0_WRITE_MASK                     MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH3_STA_0_BSY_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_STA_0_BSY_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH3_STA_0_BSY_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH3_STA_0_BSY_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_STA_0_BSY_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_STA_0_BSY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH3_STA_0_BSY_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_BSY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_BSY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_BSY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_BSY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_BSY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_BSY_WAIT                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_STA_0_BSY_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH3_STA_0_ISE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH3_STA_0_ISE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH3_STA_0_ISE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH3_STA_0_ISE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH3_STA_0_ISE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH3_STA_0_ISE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH3_STA_0_ISE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_ISE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_ISE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_ISE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_ISE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_ISE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_ISE_EOC_NO_INTR                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_STA_0_ISE_EOC_INTR                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH3_STA_0_PING_PONG_STA_SHIFT                    MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH3_STA_0_PING_PONG_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH3_STA_0_PING_PONG_STA_RANGE                    28:28
+#define GPCDMA_CHANNEL_CH3_STA_0_PING_PONG_STA_MSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH3_STA_0_PING_PONG_STA_LSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH3_STA_0_PING_PONG_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH3_STA_0_PING_PONG_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_PING_PONG_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_PING_PONG_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_PING_PONG_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_PING_PONG_STA_PING_INTR_STA                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_STA_0_PING_PONG_STA_PONG_INTR_STA                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH3_STA_0_DMA_ACTIVITY_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH3_STA_0_DMA_ACTIVITY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH3_STA_0_DMA_ACTIVITY_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH3_STA_0_DMA_ACTIVITY_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH3_STA_0_DMA_ACTIVITY_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH3_STA_0_DMA_ACTIVITY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH3_STA_0_DMA_ACTIVITY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_DMA_ACTIVITY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_DMA_ACTIVITY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_DMA_ACTIVITY_IDLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_STA_0_DMA_ACTIVITY_BUSY                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_SHIFT                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_RANGE                    26:26
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_LSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_RX_SHIFT                       MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_RX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_RX_RANGE                       25:25
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_RX_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_RX_LSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_RX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_RX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_RX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_RX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_RX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_RX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_RX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_TX_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_TX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_TX_RANGE                       24:24
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_TX_MSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_TX_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_TX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_TX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_TX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_TX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_TX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_TX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_STA_0_CHANNEL_TX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH3_STA_0_IRQ_INTR_STA_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH3_STA_0_IRQ_INTR_STA_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH3_STA_0_IRQ_INTR_STA_RANGE                     23:23
+#define GPCDMA_CHANNEL_CH3_STA_0_IRQ_INTR_STA_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH3_STA_0_IRQ_INTR_STA_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH3_STA_0_IRQ_INTR_STA_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH3_STA_0_IRQ_INTR_STA_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_IRQ_INTR_STA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_IRQ_INTR_STA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_IRQ_INTR_STA_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_STA_0_IRQ_INTR_STA_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH3_STA_0_TRIG_STA_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH3_STA_0_TRIG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH3_STA_0_TRIG_STA_RANGE                 21:21
+#define GPCDMA_CHANNEL_CH3_STA_0_TRIG_STA_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH3_STA_0_TRIG_STA_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH3_STA_0_TRIG_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH3_STA_0_TRIG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_TRIG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_TRIG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_TRIG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_TRIG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_TRIG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_TRIG_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_STA_0_TRIG_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH3_STA_0_INTR_STA_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH3_STA_0_INTR_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH3_STA_0_INTR_STA_RANGE                 20:20
+#define GPCDMA_CHANNEL_CH3_STA_0_INTR_STA_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH3_STA_0_INTR_STA_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH3_STA_0_INTR_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH3_STA_0_INTR_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_INTR_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_INTR_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_INTR_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_INTR_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_STA_0_INTR_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_STA_0_INTR_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_STA_0_INTR_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH3_CSRE_0
+#define GPCDMA_CHANNEL_CH3_CSRE_0                       MK_ADDR_CONST(0x40008)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH3_CSRE_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH3_CSRE_0_SCR                   SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_CSRE_0_SCRREG                        GPCDMA_SCR_SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_CSRE_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH3_CSRE_0_RESET_VAL                     MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_RESET_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_READ_MASK                     MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_WRITE_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_SHIFT                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_FIELD                        MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_RANGE                        19:14
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_LSB                  MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_DEFAULT                      MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH0                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH1                  MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH2                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH3                  MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH4                  MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH5                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH6                  MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH7                  MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH8                  MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH9                  MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH10                 MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH11                 MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH12                 MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH13                 MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH14                 MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH15                 MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH16                 MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH17                 MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH18                 MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH19                 MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH20                 MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH21                 MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH22                 MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH23                 MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH24                 MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH25                 MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH26                 MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH27                 MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH28                 MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH29                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH30                 MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH31                 MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH3_CSRE_0_TRIG_SEL_RSVD                 MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH3_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0                    MK_ADDR_CONST(0x4000c)
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_SCR                        SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH3_DST_PTR_0
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0                    MK_ADDR_CONST(0x40010)
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_SCR                        SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_DST_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_DST_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH3_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_DST_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_DST_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_DST_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_DST_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_DST_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_DST_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_DST_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_DST_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0                 MK_ADDR_CONST(0x40014)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_SCR                     SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_SCRREG                  GPCDMA_SCR_SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_RESET_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_READ_MASK                       MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_RANGE                        23:16
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_LSB                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                        7:0
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_MSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH3_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0                     MK_ADDR_CONST(0x40018)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_SCR                         SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_SCRREG                      GPCDMA_SCR_SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_RESET_VAL                   MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_RANGE                  31:31
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_FIELD                    MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_RANGE                    30:25
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_MSB                      MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                     MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_BURST_SHIFT                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_BURST_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_BURST_RANGE                      24:23
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_BURST_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_BURST_LSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_BURST_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_BURST_DEFAULT                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_BURST_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_BURST_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                  MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                 22:20
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                 19:17
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_RANGE                      16:16
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_MSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_PROT_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_PROT_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_PROT_RANGE                       15:14
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_PROT_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_PROT_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_PROT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_PROT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_PROT_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_PROT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID1_SHIFT                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID1_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID1_RANGE                     13:7
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID1_MSB                       MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID1_LSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID1_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID1_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID1_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID0_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID0_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID0_RANGE                     6:0
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID0_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID0_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID0_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID0_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID0_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH3_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0                   MK_ADDR_CONST(0x4001c)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_SCR                       SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_SCRREG                    GPCDMA_SCR_SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_RESET_VAL                         MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_RESET_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_READ_MASK                         MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_WRITE_MASK                        MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                      30:28
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                        MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                    MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                       MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                      27:27
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_RANGE                  26:23
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_MSB                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DEFAULT                        MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                      MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                      18:16
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                        MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                     MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                    MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_SHIFT                   MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_RANGE                   8:7
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_MSB                     MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_LSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                       MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                       6:0
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH3_WCOUNT_0
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0                     MK_ADDR_CONST(0x40020)
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_SCR                         SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_SCRREG                      GPCDMA_SCR_SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_WCOUNT_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_WCOUNT_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH3_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_WCOUNT_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_WCOUNT_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_WCOUNT_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_WCOUNT_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_WCOUNT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_WCOUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_WCOUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_WCOUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0                       MK_ADDR_CONST(0x40024)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_SCR                   SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_SCRREG                        GPCDMA_SCR_SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                  31:0
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0                       MK_ADDR_CONST(0x40028)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_SCR                   SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x4002c
+
+// Register GPCDMA_CHANNEL_CH3_ERR_STA_0
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0                    MK_ADDR_CONST(0x40030)
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_SCR                        SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_SCRREG                     GPCDMA_SCR_SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH3_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0                  MK_ADDR_CONST(0x40034)
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_SCR                      SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_SCRREG                   GPCDMA_SCR_SCR_CH3_0
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH3_TZ_0
+#define GPCDMA_CHANNEL_CH3_TZ_0                 MK_ADDR_CONST(0x40038)
+#define GPCDMA_CHANNEL_CH3_TZ_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH3_TZ_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH3_TZ_0_SCR                     SCR_TZ_0
+#define GPCDMA_CHANNEL_CH3_TZ_0_SCRREG                  GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH3_TZ_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH3_TZ_0_RESET_VAL                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH3_TZ_0_RESET_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH3_TZ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_TZ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_TZ_0_READ_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH3_TZ_0_WRITE_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MC_PROT_1_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MC_PROT_1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MC_PROT_1_RANGE                 1:1
+#define GPCDMA_CHANNEL_CH3_TZ_0_MC_PROT_1_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MC_PROT_1_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MC_PROT_1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH3_TZ_0_MC_PROT_1_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MC_PROT_1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MC_PROT_1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MC_PROT_1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH3_TZ_0_MMIO_PROT_1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MMIO_PROT_1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH3_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MMIO_PROT_1_RANGE                       0:0
+#define GPCDMA_CHANNEL_CH3_TZ_0_MMIO_PROT_1_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MMIO_PROT_1_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MMIO_PROT_1_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH3_TZ_0_MMIO_PROT_1_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MMIO_PROT_1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MMIO_PROT_1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH3_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH4_CSR_0
+#define GPCDMA_CHANNEL_CH4_CSR_0                        MK_ADDR_CONST(0x50000)
+#define GPCDMA_CHANNEL_CH4_CSR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH4_CSR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH4_CSR_0_SCR                    SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_CSR_0_SCRREG                         GPCDMA_SCR_SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_CSR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH4_CSR_0_RESET_VAL                      MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH4_CSR_0_RESET_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH4_CSR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_READ_MASK                      MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH4_CSR_0_WRITE_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ENB_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ENB_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ENB_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH4_CSR_0_ENB_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ENB_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ENB_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH4_CSR_0_ENB_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ENB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ENB_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ENB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ENB_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ENB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ENB_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ENB_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH4_CSR_0_IE_EOC_SHIFT                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IE_EOC_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IE_EOC_RANGE                   30:30
+#define GPCDMA_CHANNEL_CH4_CSR_0_IE_EOC_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IE_EOC_LSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IE_EOC_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH4_CSR_0_IE_EOC_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IE_EOC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IE_EOC_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IE_EOC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IE_EOC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IE_EOC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IE_EOC_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IE_EOC_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH4_CSR_0_ONCE_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ONCE_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ONCE_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH4_CSR_0_ONCE_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ONCE_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ONCE_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH4_CSR_0_ONCE_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ONCE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ONCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ONCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ONCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ONCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ONCE_CYCLIC_MODE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_ONCE_SINGLE_BLOCK                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH4_CSR_0_FC_MODE_SHIFT                  MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH4_CSR_0_FC_MODE_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH4_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH4_CSR_0_FC_MODE_RANGE                  25:24
+#define GPCDMA_CHANNEL_CH4_CSR_0_FC_MODE_MSB                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH4_CSR_0_FC_MODE_LSB                    MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH4_CSR_0_FC_MODE_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH4_CSR_0_FC_MODE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_FC_MODE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH4_CSR_0_FC_MODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_FC_MODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_FC_MODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_FC_MODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_CSR_0_FC_MODE_NO_MMIO                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_FC_MODE_ONE_MMIO                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH4_CSR_0_FC_MODE_TWO_MMIO                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH4_CSR_0_FC_MODE_FOUR_MMIO                      MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_RANGE                 23:21
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_IO2MEM_NO_FC                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_IO2MEM_FC                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_MEM2IO_NO_FC                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_MEM2IO_FC                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_MEM2MEM                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_RSVD                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH4_CSR_0_DMA_MODE_FIXED_PAT                     MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_FIELD                  MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_RANGE                  20:16
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_0                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_1                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_2                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_3                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_4                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_5                       MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_6                       MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_7                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_8                       MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_9                       MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_10                      MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_11                      MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_12                      MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_13                      MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_14                      MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_15                      MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_16                      MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_17                      MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_18                      MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_19                      MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_20                      MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_21                      MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_22                      MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_23                      MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_24                      MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_25                      MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_26                      MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_27                      MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_28                      MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_29_RSVD                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_30                      MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_31                      MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH4_CSR_0_REQ_SEL_RSVD                   MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH4_CSR_0_IRQ_MASK_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IRQ_MASK_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IRQ_MASK_RANGE                 15:15
+#define GPCDMA_CHANNEL_CH4_CSR_0_IRQ_MASK_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IRQ_MASK_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IRQ_MASK_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH4_CSR_0_IRQ_MASK_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IRQ_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IRQ_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IRQ_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IRQ_MASK_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_IRQ_MASK_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH4_CSR_0_WEIGHT_SHIFT                   MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH4_CSR_0_WEIGHT_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH4_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH4_CSR_0_WEIGHT_RANGE                   13:10
+#define GPCDMA_CHANNEL_CH4_CSR_0_WEIGHT_MSB                     MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH4_CSR_0_WEIGHT_LSB                     MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH4_CSR_0_WEIGHT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH4_CSR_0_WEIGHT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_CSR_0_WEIGHT_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH4_CSR_0_WEIGHT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_WEIGHT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_WEIGHT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSR_0_WEIGHT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH4_STA_0
+#define GPCDMA_CHANNEL_CH4_STA_0                        MK_ADDR_CONST(0x50004)
+#define GPCDMA_CHANNEL_CH4_STA_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH4_STA_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH4_STA_0_SCR                    SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_STA_0_SCRREG                         GPCDMA_SCR_SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_STA_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH4_STA_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_RESET_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH4_STA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_READ_MASK                      MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH4_STA_0_WRITE_MASK                     MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH4_STA_0_BSY_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_STA_0_BSY_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH4_STA_0_BSY_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH4_STA_0_BSY_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_STA_0_BSY_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_STA_0_BSY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH4_STA_0_BSY_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_BSY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_BSY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_BSY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_BSY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_BSY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_BSY_WAIT                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_STA_0_BSY_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH4_STA_0_ISE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH4_STA_0_ISE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH4_STA_0_ISE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH4_STA_0_ISE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH4_STA_0_ISE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH4_STA_0_ISE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH4_STA_0_ISE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_ISE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_ISE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_ISE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_ISE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_ISE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_ISE_EOC_NO_INTR                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_STA_0_ISE_EOC_INTR                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH4_STA_0_PING_PONG_STA_SHIFT                    MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH4_STA_0_PING_PONG_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH4_STA_0_PING_PONG_STA_RANGE                    28:28
+#define GPCDMA_CHANNEL_CH4_STA_0_PING_PONG_STA_MSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH4_STA_0_PING_PONG_STA_LSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH4_STA_0_PING_PONG_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH4_STA_0_PING_PONG_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_PING_PONG_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_PING_PONG_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_PING_PONG_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_PING_PONG_STA_PING_INTR_STA                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_STA_0_PING_PONG_STA_PONG_INTR_STA                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH4_STA_0_DMA_ACTIVITY_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH4_STA_0_DMA_ACTIVITY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH4_STA_0_DMA_ACTIVITY_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH4_STA_0_DMA_ACTIVITY_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH4_STA_0_DMA_ACTIVITY_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH4_STA_0_DMA_ACTIVITY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH4_STA_0_DMA_ACTIVITY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_DMA_ACTIVITY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_DMA_ACTIVITY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_DMA_ACTIVITY_IDLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_STA_0_DMA_ACTIVITY_BUSY                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_SHIFT                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_RANGE                    26:26
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_LSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_RX_SHIFT                       MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_RX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_RX_RANGE                       25:25
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_RX_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_RX_LSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_RX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_RX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_RX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_RX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_RX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_RX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_RX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_TX_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_TX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_TX_RANGE                       24:24
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_TX_MSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_TX_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_TX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_TX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_TX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_TX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_TX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_TX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_STA_0_CHANNEL_TX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH4_STA_0_IRQ_INTR_STA_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH4_STA_0_IRQ_INTR_STA_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH4_STA_0_IRQ_INTR_STA_RANGE                     23:23
+#define GPCDMA_CHANNEL_CH4_STA_0_IRQ_INTR_STA_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH4_STA_0_IRQ_INTR_STA_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH4_STA_0_IRQ_INTR_STA_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH4_STA_0_IRQ_INTR_STA_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_IRQ_INTR_STA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_IRQ_INTR_STA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_IRQ_INTR_STA_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_STA_0_IRQ_INTR_STA_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH4_STA_0_TRIG_STA_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH4_STA_0_TRIG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH4_STA_0_TRIG_STA_RANGE                 21:21
+#define GPCDMA_CHANNEL_CH4_STA_0_TRIG_STA_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH4_STA_0_TRIG_STA_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH4_STA_0_TRIG_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH4_STA_0_TRIG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_TRIG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_TRIG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_TRIG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_TRIG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_TRIG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_TRIG_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_STA_0_TRIG_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH4_STA_0_INTR_STA_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH4_STA_0_INTR_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH4_STA_0_INTR_STA_RANGE                 20:20
+#define GPCDMA_CHANNEL_CH4_STA_0_INTR_STA_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH4_STA_0_INTR_STA_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH4_STA_0_INTR_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH4_STA_0_INTR_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_INTR_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_INTR_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_INTR_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_INTR_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_STA_0_INTR_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_STA_0_INTR_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_STA_0_INTR_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH4_CSRE_0
+#define GPCDMA_CHANNEL_CH4_CSRE_0                       MK_ADDR_CONST(0x50008)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH4_CSRE_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH4_CSRE_0_SCR                   SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_CSRE_0_SCRREG                        GPCDMA_SCR_SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_CSRE_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH4_CSRE_0_RESET_VAL                     MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_RESET_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_READ_MASK                     MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_WRITE_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_SHIFT                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_FIELD                        MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_RANGE                        19:14
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_LSB                  MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_DEFAULT                      MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH0                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH1                  MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH2                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH3                  MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH4                  MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH5                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH6                  MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH7                  MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH8                  MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH9                  MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH10                 MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH11                 MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH12                 MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH13                 MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH14                 MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH15                 MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH16                 MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH17                 MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH18                 MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH19                 MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH20                 MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH21                 MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH22                 MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH23                 MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH24                 MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH25                 MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH26                 MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH27                 MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH28                 MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH29                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH30                 MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH31                 MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH4_CSRE_0_TRIG_SEL_RSVD                 MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH4_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0                    MK_ADDR_CONST(0x5000c)
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_SCR                        SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH4_DST_PTR_0
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0                    MK_ADDR_CONST(0x50010)
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_SCR                        SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_DST_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_DST_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH4_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_DST_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_DST_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_DST_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_DST_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_DST_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_DST_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_DST_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_DST_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0                 MK_ADDR_CONST(0x50014)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_SCR                     SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_SCRREG                  GPCDMA_SCR_SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_RESET_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_READ_MASK                       MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_RANGE                        23:16
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_LSB                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                        7:0
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_MSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH4_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0                     MK_ADDR_CONST(0x50018)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_SCR                         SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_SCRREG                      GPCDMA_SCR_SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_RESET_VAL                   MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_RANGE                  31:31
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_FIELD                    MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_RANGE                    30:25
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_MSB                      MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                     MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_BURST_SHIFT                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_BURST_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_BURST_RANGE                      24:23
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_BURST_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_BURST_LSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_BURST_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_BURST_DEFAULT                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_BURST_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_BURST_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                  MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                 22:20
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                 19:17
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_RANGE                      16:16
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_MSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_PROT_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_PROT_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_PROT_RANGE                       15:14
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_PROT_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_PROT_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_PROT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_PROT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_PROT_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_PROT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID1_SHIFT                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID1_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID1_RANGE                     13:7
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID1_MSB                       MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID1_LSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID1_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID1_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID1_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID0_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID0_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID0_RANGE                     6:0
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID0_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID0_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID0_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID0_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID0_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH4_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0                   MK_ADDR_CONST(0x5001c)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_SCR                       SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_SCRREG                    GPCDMA_SCR_SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_RESET_VAL                         MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_RESET_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_READ_MASK                         MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_WRITE_MASK                        MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                      30:28
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                        MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                    MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                       MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                      27:27
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_RANGE                  26:23
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_MSB                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DEFAULT                        MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                      MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                      18:16
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                        MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                     MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                    MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_SHIFT                   MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_RANGE                   8:7
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_MSB                     MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_LSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                       MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                       6:0
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH4_WCOUNT_0
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0                     MK_ADDR_CONST(0x50020)
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_SCR                         SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_SCRREG                      GPCDMA_SCR_SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_WCOUNT_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_WCOUNT_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH4_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_WCOUNT_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_WCOUNT_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_WCOUNT_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_WCOUNT_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_WCOUNT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_WCOUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_WCOUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_WCOUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0                       MK_ADDR_CONST(0x50024)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_SCR                   SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_SCRREG                        GPCDMA_SCR_SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                  31:0
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0                       MK_ADDR_CONST(0x50028)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_SCR                   SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x5002c
+
+// Register GPCDMA_CHANNEL_CH4_ERR_STA_0
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0                    MK_ADDR_CONST(0x50030)
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_SCR                        SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_SCRREG                     GPCDMA_SCR_SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH4_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0                  MK_ADDR_CONST(0x50034)
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_SCR                      SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_SCRREG                   GPCDMA_SCR_SCR_CH4_0
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH4_TZ_0
+#define GPCDMA_CHANNEL_CH4_TZ_0                 MK_ADDR_CONST(0x50038)
+#define GPCDMA_CHANNEL_CH4_TZ_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH4_TZ_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH4_TZ_0_SCR                     SCR_TZ_0
+#define GPCDMA_CHANNEL_CH4_TZ_0_SCRREG                  GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH4_TZ_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH4_TZ_0_RESET_VAL                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH4_TZ_0_RESET_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH4_TZ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_TZ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_TZ_0_READ_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH4_TZ_0_WRITE_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MC_PROT_1_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MC_PROT_1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MC_PROT_1_RANGE                 1:1
+#define GPCDMA_CHANNEL_CH4_TZ_0_MC_PROT_1_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MC_PROT_1_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MC_PROT_1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH4_TZ_0_MC_PROT_1_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MC_PROT_1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MC_PROT_1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MC_PROT_1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH4_TZ_0_MMIO_PROT_1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MMIO_PROT_1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH4_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MMIO_PROT_1_RANGE                       0:0
+#define GPCDMA_CHANNEL_CH4_TZ_0_MMIO_PROT_1_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MMIO_PROT_1_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MMIO_PROT_1_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH4_TZ_0_MMIO_PROT_1_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MMIO_PROT_1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MMIO_PROT_1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH4_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH5_CSR_0
+#define GPCDMA_CHANNEL_CH5_CSR_0                        MK_ADDR_CONST(0x60000)
+#define GPCDMA_CHANNEL_CH5_CSR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH5_CSR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH5_CSR_0_SCR                    SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_CSR_0_SCRREG                         GPCDMA_SCR_SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_CSR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH5_CSR_0_RESET_VAL                      MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH5_CSR_0_RESET_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH5_CSR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_READ_MASK                      MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH5_CSR_0_WRITE_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ENB_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ENB_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ENB_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH5_CSR_0_ENB_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ENB_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ENB_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH5_CSR_0_ENB_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ENB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ENB_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ENB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ENB_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ENB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ENB_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ENB_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH5_CSR_0_IE_EOC_SHIFT                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IE_EOC_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IE_EOC_RANGE                   30:30
+#define GPCDMA_CHANNEL_CH5_CSR_0_IE_EOC_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IE_EOC_LSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IE_EOC_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH5_CSR_0_IE_EOC_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IE_EOC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IE_EOC_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IE_EOC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IE_EOC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IE_EOC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IE_EOC_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IE_EOC_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH5_CSR_0_ONCE_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ONCE_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ONCE_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH5_CSR_0_ONCE_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ONCE_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ONCE_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH5_CSR_0_ONCE_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ONCE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ONCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ONCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ONCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ONCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ONCE_CYCLIC_MODE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_ONCE_SINGLE_BLOCK                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH5_CSR_0_FC_MODE_SHIFT                  MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH5_CSR_0_FC_MODE_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH5_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH5_CSR_0_FC_MODE_RANGE                  25:24
+#define GPCDMA_CHANNEL_CH5_CSR_0_FC_MODE_MSB                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH5_CSR_0_FC_MODE_LSB                    MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH5_CSR_0_FC_MODE_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH5_CSR_0_FC_MODE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_FC_MODE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH5_CSR_0_FC_MODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_FC_MODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_FC_MODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_FC_MODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_CSR_0_FC_MODE_NO_MMIO                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_FC_MODE_ONE_MMIO                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH5_CSR_0_FC_MODE_TWO_MMIO                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH5_CSR_0_FC_MODE_FOUR_MMIO                      MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_RANGE                 23:21
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_IO2MEM_NO_FC                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_IO2MEM_FC                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_MEM2IO_NO_FC                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_MEM2IO_FC                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_MEM2MEM                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_RSVD                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH5_CSR_0_DMA_MODE_FIXED_PAT                     MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_FIELD                  MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_RANGE                  20:16
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_0                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_1                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_2                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_3                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_4                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_5                       MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_6                       MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_7                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_8                       MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_9                       MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_10                      MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_11                      MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_12                      MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_13                      MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_14                      MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_15                      MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_16                      MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_17                      MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_18                      MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_19                      MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_20                      MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_21                      MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_22                      MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_23                      MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_24                      MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_25                      MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_26                      MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_27                      MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_28                      MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_29_RSVD                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_30                      MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_31                      MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH5_CSR_0_REQ_SEL_RSVD                   MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH5_CSR_0_IRQ_MASK_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IRQ_MASK_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IRQ_MASK_RANGE                 15:15
+#define GPCDMA_CHANNEL_CH5_CSR_0_IRQ_MASK_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IRQ_MASK_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IRQ_MASK_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH5_CSR_0_IRQ_MASK_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IRQ_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IRQ_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IRQ_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IRQ_MASK_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_IRQ_MASK_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH5_CSR_0_WEIGHT_SHIFT                   MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH5_CSR_0_WEIGHT_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH5_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH5_CSR_0_WEIGHT_RANGE                   13:10
+#define GPCDMA_CHANNEL_CH5_CSR_0_WEIGHT_MSB                     MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH5_CSR_0_WEIGHT_LSB                     MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH5_CSR_0_WEIGHT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH5_CSR_0_WEIGHT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_CSR_0_WEIGHT_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH5_CSR_0_WEIGHT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_WEIGHT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_WEIGHT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSR_0_WEIGHT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH5_STA_0
+#define GPCDMA_CHANNEL_CH5_STA_0                        MK_ADDR_CONST(0x60004)
+#define GPCDMA_CHANNEL_CH5_STA_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH5_STA_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH5_STA_0_SCR                    SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_STA_0_SCRREG                         GPCDMA_SCR_SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_STA_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH5_STA_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_RESET_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH5_STA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_READ_MASK                      MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH5_STA_0_WRITE_MASK                     MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH5_STA_0_BSY_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_STA_0_BSY_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH5_STA_0_BSY_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH5_STA_0_BSY_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_STA_0_BSY_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_STA_0_BSY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH5_STA_0_BSY_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_BSY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_BSY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_BSY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_BSY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_BSY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_BSY_WAIT                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_STA_0_BSY_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH5_STA_0_ISE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH5_STA_0_ISE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH5_STA_0_ISE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH5_STA_0_ISE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH5_STA_0_ISE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH5_STA_0_ISE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH5_STA_0_ISE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_ISE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_ISE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_ISE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_ISE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_ISE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_ISE_EOC_NO_INTR                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_STA_0_ISE_EOC_INTR                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH5_STA_0_PING_PONG_STA_SHIFT                    MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH5_STA_0_PING_PONG_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH5_STA_0_PING_PONG_STA_RANGE                    28:28
+#define GPCDMA_CHANNEL_CH5_STA_0_PING_PONG_STA_MSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH5_STA_0_PING_PONG_STA_LSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH5_STA_0_PING_PONG_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH5_STA_0_PING_PONG_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_PING_PONG_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_PING_PONG_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_PING_PONG_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_PING_PONG_STA_PING_INTR_STA                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_STA_0_PING_PONG_STA_PONG_INTR_STA                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH5_STA_0_DMA_ACTIVITY_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH5_STA_0_DMA_ACTIVITY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH5_STA_0_DMA_ACTIVITY_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH5_STA_0_DMA_ACTIVITY_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH5_STA_0_DMA_ACTIVITY_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH5_STA_0_DMA_ACTIVITY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH5_STA_0_DMA_ACTIVITY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_DMA_ACTIVITY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_DMA_ACTIVITY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_DMA_ACTIVITY_IDLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_STA_0_DMA_ACTIVITY_BUSY                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_SHIFT                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_RANGE                    26:26
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_LSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_RX_SHIFT                       MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_RX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_RX_RANGE                       25:25
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_RX_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_RX_LSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_RX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_RX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_RX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_RX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_RX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_RX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_RX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_TX_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_TX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_TX_RANGE                       24:24
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_TX_MSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_TX_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_TX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_TX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_TX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_TX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_TX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_TX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_STA_0_CHANNEL_TX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH5_STA_0_IRQ_INTR_STA_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH5_STA_0_IRQ_INTR_STA_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH5_STA_0_IRQ_INTR_STA_RANGE                     23:23
+#define GPCDMA_CHANNEL_CH5_STA_0_IRQ_INTR_STA_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH5_STA_0_IRQ_INTR_STA_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH5_STA_0_IRQ_INTR_STA_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH5_STA_0_IRQ_INTR_STA_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_IRQ_INTR_STA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_IRQ_INTR_STA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_IRQ_INTR_STA_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_STA_0_IRQ_INTR_STA_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH5_STA_0_TRIG_STA_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH5_STA_0_TRIG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH5_STA_0_TRIG_STA_RANGE                 21:21
+#define GPCDMA_CHANNEL_CH5_STA_0_TRIG_STA_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH5_STA_0_TRIG_STA_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH5_STA_0_TRIG_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH5_STA_0_TRIG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_TRIG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_TRIG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_TRIG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_TRIG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_TRIG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_TRIG_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_STA_0_TRIG_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH5_STA_0_INTR_STA_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH5_STA_0_INTR_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH5_STA_0_INTR_STA_RANGE                 20:20
+#define GPCDMA_CHANNEL_CH5_STA_0_INTR_STA_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH5_STA_0_INTR_STA_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH5_STA_0_INTR_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH5_STA_0_INTR_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_INTR_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_INTR_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_INTR_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_INTR_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_STA_0_INTR_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_STA_0_INTR_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_STA_0_INTR_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH5_CSRE_0
+#define GPCDMA_CHANNEL_CH5_CSRE_0                       MK_ADDR_CONST(0x60008)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH5_CSRE_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH5_CSRE_0_SCR                   SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_CSRE_0_SCRREG                        GPCDMA_SCR_SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_CSRE_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH5_CSRE_0_RESET_VAL                     MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_RESET_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_READ_MASK                     MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_WRITE_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_SHIFT                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_FIELD                        MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_RANGE                        19:14
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_LSB                  MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_DEFAULT                      MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH0                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH1                  MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH2                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH3                  MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH4                  MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH5                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH6                  MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH7                  MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH8                  MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH9                  MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH10                 MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH11                 MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH12                 MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH13                 MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH14                 MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH15                 MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH16                 MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH17                 MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH18                 MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH19                 MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH20                 MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH21                 MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH22                 MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH23                 MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH24                 MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH25                 MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH26                 MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH27                 MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH28                 MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH29                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH30                 MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH31                 MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH5_CSRE_0_TRIG_SEL_RSVD                 MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH5_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0                    MK_ADDR_CONST(0x6000c)
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_SCR                        SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH5_DST_PTR_0
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0                    MK_ADDR_CONST(0x60010)
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_SCR                        SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_DST_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_DST_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH5_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_DST_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_DST_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_DST_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_DST_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_DST_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_DST_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_DST_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_DST_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0                 MK_ADDR_CONST(0x60014)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_SCR                     SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_SCRREG                  GPCDMA_SCR_SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_RESET_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_READ_MASK                       MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_RANGE                        23:16
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_LSB                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                        7:0
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_MSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH5_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0                     MK_ADDR_CONST(0x60018)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_SCR                         SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_SCRREG                      GPCDMA_SCR_SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_RESET_VAL                   MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_RANGE                  31:31
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_FIELD                    MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_RANGE                    30:25
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_MSB                      MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                     MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_BURST_SHIFT                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_BURST_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_BURST_RANGE                      24:23
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_BURST_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_BURST_LSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_BURST_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_BURST_DEFAULT                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_BURST_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_BURST_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                  MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                 22:20
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                 19:17
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_RANGE                      16:16
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_MSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_PROT_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_PROT_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_PROT_RANGE                       15:14
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_PROT_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_PROT_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_PROT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_PROT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_PROT_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_PROT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID1_SHIFT                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID1_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID1_RANGE                     13:7
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID1_MSB                       MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID1_LSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID1_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID1_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID1_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID0_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID0_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID0_RANGE                     6:0
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID0_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID0_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID0_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID0_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID0_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH5_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0                   MK_ADDR_CONST(0x6001c)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_SCR                       SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_SCRREG                    GPCDMA_SCR_SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_RESET_VAL                         MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_RESET_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_READ_MASK                         MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_WRITE_MASK                        MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                      30:28
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                        MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                    MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                       MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                      27:27
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_RANGE                  26:23
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_MSB                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DEFAULT                        MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                      MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                      18:16
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                        MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                     MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                    MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_SHIFT                   MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_RANGE                   8:7
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_MSB                     MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_LSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                       MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                       6:0
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH5_WCOUNT_0
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0                     MK_ADDR_CONST(0x60020)
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_SCR                         SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_SCRREG                      GPCDMA_SCR_SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_WCOUNT_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_WCOUNT_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH5_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_WCOUNT_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_WCOUNT_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_WCOUNT_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_WCOUNT_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_WCOUNT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_WCOUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_WCOUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_WCOUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0                       MK_ADDR_CONST(0x60024)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_SCR                   SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_SCRREG                        GPCDMA_SCR_SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                  31:0
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0                       MK_ADDR_CONST(0x60028)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_SCR                   SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x6002c
+
+// Register GPCDMA_CHANNEL_CH5_ERR_STA_0
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0                    MK_ADDR_CONST(0x60030)
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_SCR                        SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_SCRREG                     GPCDMA_SCR_SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH5_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0                  MK_ADDR_CONST(0x60034)
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_SCR                      SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_SCRREG                   GPCDMA_SCR_SCR_CH5_0
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH5_TZ_0
+#define GPCDMA_CHANNEL_CH5_TZ_0                 MK_ADDR_CONST(0x60038)
+#define GPCDMA_CHANNEL_CH5_TZ_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH5_TZ_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH5_TZ_0_SCR                     SCR_TZ_0
+#define GPCDMA_CHANNEL_CH5_TZ_0_SCRREG                  GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH5_TZ_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH5_TZ_0_RESET_VAL                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH5_TZ_0_RESET_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH5_TZ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_TZ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_TZ_0_READ_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH5_TZ_0_WRITE_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MC_PROT_1_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MC_PROT_1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MC_PROT_1_RANGE                 1:1
+#define GPCDMA_CHANNEL_CH5_TZ_0_MC_PROT_1_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MC_PROT_1_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MC_PROT_1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH5_TZ_0_MC_PROT_1_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MC_PROT_1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MC_PROT_1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MC_PROT_1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH5_TZ_0_MMIO_PROT_1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MMIO_PROT_1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH5_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MMIO_PROT_1_RANGE                       0:0
+#define GPCDMA_CHANNEL_CH5_TZ_0_MMIO_PROT_1_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MMIO_PROT_1_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MMIO_PROT_1_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH5_TZ_0_MMIO_PROT_1_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MMIO_PROT_1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MMIO_PROT_1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH5_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH6_CSR_0
+#define GPCDMA_CHANNEL_CH6_CSR_0                        MK_ADDR_CONST(0x70000)
+#define GPCDMA_CHANNEL_CH6_CSR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH6_CSR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH6_CSR_0_SCR                    SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_CSR_0_SCRREG                         GPCDMA_SCR_SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_CSR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH6_CSR_0_RESET_VAL                      MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH6_CSR_0_RESET_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH6_CSR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_READ_MASK                      MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH6_CSR_0_WRITE_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ENB_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ENB_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ENB_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH6_CSR_0_ENB_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ENB_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ENB_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH6_CSR_0_ENB_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ENB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ENB_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ENB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ENB_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ENB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ENB_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ENB_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH6_CSR_0_IE_EOC_SHIFT                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IE_EOC_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IE_EOC_RANGE                   30:30
+#define GPCDMA_CHANNEL_CH6_CSR_0_IE_EOC_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IE_EOC_LSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IE_EOC_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH6_CSR_0_IE_EOC_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IE_EOC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IE_EOC_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IE_EOC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IE_EOC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IE_EOC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IE_EOC_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IE_EOC_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH6_CSR_0_ONCE_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ONCE_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ONCE_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH6_CSR_0_ONCE_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ONCE_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ONCE_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH6_CSR_0_ONCE_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ONCE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ONCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ONCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ONCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ONCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ONCE_CYCLIC_MODE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_ONCE_SINGLE_BLOCK                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH6_CSR_0_FC_MODE_SHIFT                  MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH6_CSR_0_FC_MODE_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH6_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH6_CSR_0_FC_MODE_RANGE                  25:24
+#define GPCDMA_CHANNEL_CH6_CSR_0_FC_MODE_MSB                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH6_CSR_0_FC_MODE_LSB                    MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH6_CSR_0_FC_MODE_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH6_CSR_0_FC_MODE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_FC_MODE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH6_CSR_0_FC_MODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_FC_MODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_FC_MODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_FC_MODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_CSR_0_FC_MODE_NO_MMIO                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_FC_MODE_ONE_MMIO                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH6_CSR_0_FC_MODE_TWO_MMIO                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH6_CSR_0_FC_MODE_FOUR_MMIO                      MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_RANGE                 23:21
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_IO2MEM_NO_FC                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_IO2MEM_FC                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_MEM2IO_NO_FC                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_MEM2IO_FC                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_MEM2MEM                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_RSVD                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH6_CSR_0_DMA_MODE_FIXED_PAT                     MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_FIELD                  MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_RANGE                  20:16
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_0                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_1                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_2                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_3                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_4                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_5                       MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_6                       MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_7                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_8                       MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_9                       MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_10                      MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_11                      MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_12                      MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_13                      MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_14                      MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_15                      MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_16                      MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_17                      MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_18                      MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_19                      MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_20                      MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_21                      MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_22                      MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_23                      MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_24                      MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_25                      MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_26                      MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_27                      MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_28                      MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_29_RSVD                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_30                      MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_31                      MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH6_CSR_0_REQ_SEL_RSVD                   MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH6_CSR_0_IRQ_MASK_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IRQ_MASK_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IRQ_MASK_RANGE                 15:15
+#define GPCDMA_CHANNEL_CH6_CSR_0_IRQ_MASK_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IRQ_MASK_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IRQ_MASK_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH6_CSR_0_IRQ_MASK_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IRQ_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IRQ_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IRQ_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IRQ_MASK_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_IRQ_MASK_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH6_CSR_0_WEIGHT_SHIFT                   MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH6_CSR_0_WEIGHT_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH6_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH6_CSR_0_WEIGHT_RANGE                   13:10
+#define GPCDMA_CHANNEL_CH6_CSR_0_WEIGHT_MSB                     MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH6_CSR_0_WEIGHT_LSB                     MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH6_CSR_0_WEIGHT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH6_CSR_0_WEIGHT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_CSR_0_WEIGHT_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH6_CSR_0_WEIGHT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_WEIGHT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_WEIGHT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSR_0_WEIGHT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH6_STA_0
+#define GPCDMA_CHANNEL_CH6_STA_0                        MK_ADDR_CONST(0x70004)
+#define GPCDMA_CHANNEL_CH6_STA_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH6_STA_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH6_STA_0_SCR                    SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_STA_0_SCRREG                         GPCDMA_SCR_SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_STA_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH6_STA_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_RESET_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH6_STA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_READ_MASK                      MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH6_STA_0_WRITE_MASK                     MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH6_STA_0_BSY_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_STA_0_BSY_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH6_STA_0_BSY_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH6_STA_0_BSY_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_STA_0_BSY_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_STA_0_BSY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH6_STA_0_BSY_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_BSY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_BSY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_BSY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_BSY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_BSY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_BSY_WAIT                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_STA_0_BSY_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH6_STA_0_ISE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH6_STA_0_ISE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH6_STA_0_ISE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH6_STA_0_ISE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH6_STA_0_ISE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH6_STA_0_ISE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH6_STA_0_ISE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_ISE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_ISE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_ISE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_ISE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_ISE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_ISE_EOC_NO_INTR                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_STA_0_ISE_EOC_INTR                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH6_STA_0_PING_PONG_STA_SHIFT                    MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH6_STA_0_PING_PONG_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH6_STA_0_PING_PONG_STA_RANGE                    28:28
+#define GPCDMA_CHANNEL_CH6_STA_0_PING_PONG_STA_MSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH6_STA_0_PING_PONG_STA_LSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH6_STA_0_PING_PONG_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH6_STA_0_PING_PONG_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_PING_PONG_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_PING_PONG_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_PING_PONG_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_PING_PONG_STA_PING_INTR_STA                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_STA_0_PING_PONG_STA_PONG_INTR_STA                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH6_STA_0_DMA_ACTIVITY_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH6_STA_0_DMA_ACTIVITY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH6_STA_0_DMA_ACTIVITY_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH6_STA_0_DMA_ACTIVITY_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH6_STA_0_DMA_ACTIVITY_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH6_STA_0_DMA_ACTIVITY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH6_STA_0_DMA_ACTIVITY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_DMA_ACTIVITY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_DMA_ACTIVITY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_DMA_ACTIVITY_IDLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_STA_0_DMA_ACTIVITY_BUSY                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_SHIFT                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_RANGE                    26:26
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_LSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_RX_SHIFT                       MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_RX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_RX_RANGE                       25:25
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_RX_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_RX_LSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_RX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_RX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_RX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_RX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_RX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_RX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_RX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_TX_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_TX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_TX_RANGE                       24:24
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_TX_MSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_TX_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_TX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_TX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_TX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_TX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_TX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_TX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_STA_0_CHANNEL_TX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH6_STA_0_IRQ_INTR_STA_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH6_STA_0_IRQ_INTR_STA_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH6_STA_0_IRQ_INTR_STA_RANGE                     23:23
+#define GPCDMA_CHANNEL_CH6_STA_0_IRQ_INTR_STA_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH6_STA_0_IRQ_INTR_STA_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH6_STA_0_IRQ_INTR_STA_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH6_STA_0_IRQ_INTR_STA_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_IRQ_INTR_STA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_IRQ_INTR_STA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_IRQ_INTR_STA_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_STA_0_IRQ_INTR_STA_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH6_STA_0_TRIG_STA_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH6_STA_0_TRIG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH6_STA_0_TRIG_STA_RANGE                 21:21
+#define GPCDMA_CHANNEL_CH6_STA_0_TRIG_STA_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH6_STA_0_TRIG_STA_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH6_STA_0_TRIG_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH6_STA_0_TRIG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_TRIG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_TRIG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_TRIG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_TRIG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_TRIG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_TRIG_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_STA_0_TRIG_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH6_STA_0_INTR_STA_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH6_STA_0_INTR_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH6_STA_0_INTR_STA_RANGE                 20:20
+#define GPCDMA_CHANNEL_CH6_STA_0_INTR_STA_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH6_STA_0_INTR_STA_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH6_STA_0_INTR_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH6_STA_0_INTR_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_INTR_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_INTR_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_INTR_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_INTR_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_STA_0_INTR_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_STA_0_INTR_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_STA_0_INTR_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH6_CSRE_0
+#define GPCDMA_CHANNEL_CH6_CSRE_0                       MK_ADDR_CONST(0x70008)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH6_CSRE_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH6_CSRE_0_SCR                   SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_CSRE_0_SCRREG                        GPCDMA_SCR_SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_CSRE_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH6_CSRE_0_RESET_VAL                     MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_RESET_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_READ_MASK                     MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_WRITE_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_SHIFT                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_FIELD                        MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_RANGE                        19:14
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_LSB                  MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_DEFAULT                      MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH0                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH1                  MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH2                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH3                  MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH4                  MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH5                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH6                  MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH7                  MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH8                  MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH9                  MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH10                 MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH11                 MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH12                 MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH13                 MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH14                 MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH15                 MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH16                 MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH17                 MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH18                 MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH19                 MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH20                 MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH21                 MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH22                 MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH23                 MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH24                 MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH25                 MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH26                 MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH27                 MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH28                 MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH29                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH30                 MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH31                 MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH6_CSRE_0_TRIG_SEL_RSVD                 MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH6_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0                    MK_ADDR_CONST(0x7000c)
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_SCR                        SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH6_DST_PTR_0
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0                    MK_ADDR_CONST(0x70010)
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_SCR                        SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_DST_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_DST_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH6_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_DST_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_DST_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_DST_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_DST_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_DST_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_DST_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_DST_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_DST_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0                 MK_ADDR_CONST(0x70014)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_SCR                     SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_SCRREG                  GPCDMA_SCR_SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_RESET_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_READ_MASK                       MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_RANGE                        23:16
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_LSB                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                        7:0
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_MSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH6_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0                     MK_ADDR_CONST(0x70018)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_SCR                         SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_SCRREG                      GPCDMA_SCR_SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_RESET_VAL                   MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_RANGE                  31:31
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_FIELD                    MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_RANGE                    30:25
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_MSB                      MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                     MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_BURST_SHIFT                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_BURST_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_BURST_RANGE                      24:23
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_BURST_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_BURST_LSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_BURST_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_BURST_DEFAULT                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_BURST_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_BURST_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                  MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                 22:20
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                 19:17
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_RANGE                      16:16
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_MSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_PROT_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_PROT_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_PROT_RANGE                       15:14
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_PROT_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_PROT_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_PROT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_PROT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_PROT_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_PROT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID1_SHIFT                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID1_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID1_RANGE                     13:7
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID1_MSB                       MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID1_LSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID1_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID1_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID1_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID0_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID0_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID0_RANGE                     6:0
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID0_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID0_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID0_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID0_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID0_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH6_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0                   MK_ADDR_CONST(0x7001c)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_SCR                       SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_SCRREG                    GPCDMA_SCR_SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_RESET_VAL                         MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_RESET_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_READ_MASK                         MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_WRITE_MASK                        MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                      30:28
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                        MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                    MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                       MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                      27:27
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_RANGE                  26:23
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_MSB                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DEFAULT                        MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                      MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                      18:16
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                        MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                     MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                    MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_SHIFT                   MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_RANGE                   8:7
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_MSB                     MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_LSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                       MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                       6:0
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH6_WCOUNT_0
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0                     MK_ADDR_CONST(0x70020)
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_SCR                         SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_SCRREG                      GPCDMA_SCR_SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_WCOUNT_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_WCOUNT_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH6_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_WCOUNT_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_WCOUNT_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_WCOUNT_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_WCOUNT_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_WCOUNT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_WCOUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_WCOUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_WCOUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0                       MK_ADDR_CONST(0x70024)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_SCR                   SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_SCRREG                        GPCDMA_SCR_SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                  31:0
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0                       MK_ADDR_CONST(0x70028)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_SCR                   SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x7002c
+
+// Register GPCDMA_CHANNEL_CH6_ERR_STA_0
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0                    MK_ADDR_CONST(0x70030)
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_SCR                        SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_SCRREG                     GPCDMA_SCR_SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH6_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0                  MK_ADDR_CONST(0x70034)
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_SCR                      SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_SCRREG                   GPCDMA_SCR_SCR_CH6_0
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH6_TZ_0
+#define GPCDMA_CHANNEL_CH6_TZ_0                 MK_ADDR_CONST(0x70038)
+#define GPCDMA_CHANNEL_CH6_TZ_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH6_TZ_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH6_TZ_0_SCR                     SCR_TZ_0
+#define GPCDMA_CHANNEL_CH6_TZ_0_SCRREG                  GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH6_TZ_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH6_TZ_0_RESET_VAL                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH6_TZ_0_RESET_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH6_TZ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_TZ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_TZ_0_READ_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH6_TZ_0_WRITE_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MC_PROT_1_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MC_PROT_1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MC_PROT_1_RANGE                 1:1
+#define GPCDMA_CHANNEL_CH6_TZ_0_MC_PROT_1_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MC_PROT_1_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MC_PROT_1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH6_TZ_0_MC_PROT_1_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MC_PROT_1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MC_PROT_1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MC_PROT_1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH6_TZ_0_MMIO_PROT_1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MMIO_PROT_1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH6_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MMIO_PROT_1_RANGE                       0:0
+#define GPCDMA_CHANNEL_CH6_TZ_0_MMIO_PROT_1_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MMIO_PROT_1_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MMIO_PROT_1_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH6_TZ_0_MMIO_PROT_1_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MMIO_PROT_1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MMIO_PROT_1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH6_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH7_CSR_0
+#define GPCDMA_CHANNEL_CH7_CSR_0                        MK_ADDR_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH7_CSR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH7_CSR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH7_CSR_0_SCR                    SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_CSR_0_SCRREG                         GPCDMA_SCR_SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_CSR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH7_CSR_0_RESET_VAL                      MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH7_CSR_0_RESET_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH7_CSR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_READ_MASK                      MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH7_CSR_0_WRITE_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ENB_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ENB_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ENB_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH7_CSR_0_ENB_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ENB_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ENB_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH7_CSR_0_ENB_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ENB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ENB_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ENB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ENB_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ENB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ENB_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ENB_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH7_CSR_0_IE_EOC_SHIFT                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IE_EOC_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IE_EOC_RANGE                   30:30
+#define GPCDMA_CHANNEL_CH7_CSR_0_IE_EOC_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IE_EOC_LSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IE_EOC_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH7_CSR_0_IE_EOC_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IE_EOC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IE_EOC_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IE_EOC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IE_EOC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IE_EOC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IE_EOC_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IE_EOC_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH7_CSR_0_ONCE_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ONCE_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ONCE_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH7_CSR_0_ONCE_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ONCE_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ONCE_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH7_CSR_0_ONCE_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ONCE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ONCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ONCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ONCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ONCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ONCE_CYCLIC_MODE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_ONCE_SINGLE_BLOCK                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH7_CSR_0_FC_MODE_SHIFT                  MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH7_CSR_0_FC_MODE_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH7_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH7_CSR_0_FC_MODE_RANGE                  25:24
+#define GPCDMA_CHANNEL_CH7_CSR_0_FC_MODE_MSB                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH7_CSR_0_FC_MODE_LSB                    MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH7_CSR_0_FC_MODE_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH7_CSR_0_FC_MODE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_FC_MODE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH7_CSR_0_FC_MODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_FC_MODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_FC_MODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_FC_MODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_CSR_0_FC_MODE_NO_MMIO                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_FC_MODE_ONE_MMIO                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH7_CSR_0_FC_MODE_TWO_MMIO                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH7_CSR_0_FC_MODE_FOUR_MMIO                      MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_RANGE                 23:21
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_IO2MEM_NO_FC                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_IO2MEM_FC                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_MEM2IO_NO_FC                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_MEM2IO_FC                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_MEM2MEM                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_RSVD                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH7_CSR_0_DMA_MODE_FIXED_PAT                     MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_FIELD                  MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_RANGE                  20:16
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_0                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_1                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_2                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_3                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_4                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_5                       MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_6                       MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_7                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_8                       MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_9                       MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_10                      MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_11                      MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_12                      MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_13                      MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_14                      MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_15                      MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_16                      MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_17                      MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_18                      MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_19                      MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_20                      MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_21                      MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_22                      MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_23                      MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_24                      MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_25                      MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_26                      MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_27                      MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_28                      MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_29_RSVD                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_30                      MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_31                      MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH7_CSR_0_REQ_SEL_RSVD                   MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH7_CSR_0_IRQ_MASK_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IRQ_MASK_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IRQ_MASK_RANGE                 15:15
+#define GPCDMA_CHANNEL_CH7_CSR_0_IRQ_MASK_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IRQ_MASK_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IRQ_MASK_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH7_CSR_0_IRQ_MASK_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IRQ_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IRQ_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IRQ_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IRQ_MASK_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_IRQ_MASK_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH7_CSR_0_WEIGHT_SHIFT                   MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH7_CSR_0_WEIGHT_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH7_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH7_CSR_0_WEIGHT_RANGE                   13:10
+#define GPCDMA_CHANNEL_CH7_CSR_0_WEIGHT_MSB                     MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH7_CSR_0_WEIGHT_LSB                     MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH7_CSR_0_WEIGHT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH7_CSR_0_WEIGHT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_CSR_0_WEIGHT_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH7_CSR_0_WEIGHT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_WEIGHT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_WEIGHT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSR_0_WEIGHT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH7_STA_0
+#define GPCDMA_CHANNEL_CH7_STA_0                        MK_ADDR_CONST(0x80004)
+#define GPCDMA_CHANNEL_CH7_STA_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH7_STA_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH7_STA_0_SCR                    SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_STA_0_SCRREG                         GPCDMA_SCR_SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_STA_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH7_STA_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_RESET_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH7_STA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_READ_MASK                      MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH7_STA_0_WRITE_MASK                     MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH7_STA_0_BSY_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_STA_0_BSY_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH7_STA_0_BSY_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH7_STA_0_BSY_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_STA_0_BSY_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_STA_0_BSY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH7_STA_0_BSY_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_BSY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_BSY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_BSY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_BSY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_BSY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_BSY_WAIT                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_STA_0_BSY_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH7_STA_0_ISE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH7_STA_0_ISE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH7_STA_0_ISE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH7_STA_0_ISE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH7_STA_0_ISE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH7_STA_0_ISE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH7_STA_0_ISE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_ISE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_ISE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_ISE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_ISE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_ISE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_ISE_EOC_NO_INTR                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_STA_0_ISE_EOC_INTR                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH7_STA_0_PING_PONG_STA_SHIFT                    MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH7_STA_0_PING_PONG_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH7_STA_0_PING_PONG_STA_RANGE                    28:28
+#define GPCDMA_CHANNEL_CH7_STA_0_PING_PONG_STA_MSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH7_STA_0_PING_PONG_STA_LSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH7_STA_0_PING_PONG_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH7_STA_0_PING_PONG_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_PING_PONG_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_PING_PONG_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_PING_PONG_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_PING_PONG_STA_PING_INTR_STA                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_STA_0_PING_PONG_STA_PONG_INTR_STA                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH7_STA_0_DMA_ACTIVITY_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH7_STA_0_DMA_ACTIVITY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH7_STA_0_DMA_ACTIVITY_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH7_STA_0_DMA_ACTIVITY_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH7_STA_0_DMA_ACTIVITY_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH7_STA_0_DMA_ACTIVITY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH7_STA_0_DMA_ACTIVITY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_DMA_ACTIVITY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_DMA_ACTIVITY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_DMA_ACTIVITY_IDLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_STA_0_DMA_ACTIVITY_BUSY                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_SHIFT                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_RANGE                    26:26
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_LSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_RX_SHIFT                       MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_RX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_RX_RANGE                       25:25
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_RX_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_RX_LSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_RX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_RX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_RX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_RX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_RX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_RX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_RX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_TX_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_TX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_TX_RANGE                       24:24
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_TX_MSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_TX_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_TX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_TX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_TX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_TX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_TX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_TX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_STA_0_CHANNEL_TX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH7_STA_0_IRQ_INTR_STA_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH7_STA_0_IRQ_INTR_STA_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH7_STA_0_IRQ_INTR_STA_RANGE                     23:23
+#define GPCDMA_CHANNEL_CH7_STA_0_IRQ_INTR_STA_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH7_STA_0_IRQ_INTR_STA_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH7_STA_0_IRQ_INTR_STA_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH7_STA_0_IRQ_INTR_STA_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_IRQ_INTR_STA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_IRQ_INTR_STA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_IRQ_INTR_STA_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_STA_0_IRQ_INTR_STA_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH7_STA_0_TRIG_STA_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH7_STA_0_TRIG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH7_STA_0_TRIG_STA_RANGE                 21:21
+#define GPCDMA_CHANNEL_CH7_STA_0_TRIG_STA_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH7_STA_0_TRIG_STA_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH7_STA_0_TRIG_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH7_STA_0_TRIG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_TRIG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_TRIG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_TRIG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_TRIG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_TRIG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_TRIG_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_STA_0_TRIG_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH7_STA_0_INTR_STA_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH7_STA_0_INTR_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH7_STA_0_INTR_STA_RANGE                 20:20
+#define GPCDMA_CHANNEL_CH7_STA_0_INTR_STA_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH7_STA_0_INTR_STA_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH7_STA_0_INTR_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH7_STA_0_INTR_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_INTR_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_INTR_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_INTR_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_INTR_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_STA_0_INTR_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_STA_0_INTR_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_STA_0_INTR_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH7_CSRE_0
+#define GPCDMA_CHANNEL_CH7_CSRE_0                       MK_ADDR_CONST(0x80008)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH7_CSRE_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH7_CSRE_0_SCR                   SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_CSRE_0_SCRREG                        GPCDMA_SCR_SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_CSRE_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH7_CSRE_0_RESET_VAL                     MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_RESET_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_READ_MASK                     MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_WRITE_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_SHIFT                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_FIELD                        MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_RANGE                        19:14
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_LSB                  MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_DEFAULT                      MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH0                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH1                  MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH2                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH3                  MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH4                  MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH5                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH6                  MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH7                  MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH8                  MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH9                  MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH10                 MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH11                 MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH12                 MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH13                 MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH14                 MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH15                 MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH16                 MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH17                 MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH18                 MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH19                 MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH20                 MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH21                 MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH22                 MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH23                 MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH24                 MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH25                 MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH26                 MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH27                 MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH28                 MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH29                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH30                 MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH31                 MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH7_CSRE_0_TRIG_SEL_RSVD                 MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH7_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0                    MK_ADDR_CONST(0x8000c)
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_SCR                        SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH7_DST_PTR_0
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0                    MK_ADDR_CONST(0x80010)
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_SCR                        SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_DST_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_DST_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH7_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_DST_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_DST_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_DST_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_DST_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_DST_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_DST_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_DST_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_DST_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0                 MK_ADDR_CONST(0x80014)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_SCR                     SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_SCRREG                  GPCDMA_SCR_SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_RESET_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_READ_MASK                       MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_RANGE                        23:16
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_LSB                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                        7:0
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_MSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH7_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0                     MK_ADDR_CONST(0x80018)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_SCR                         SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_SCRREG                      GPCDMA_SCR_SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_RESET_VAL                   MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_RANGE                  31:31
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_FIELD                    MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_RANGE                    30:25
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_MSB                      MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                     MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_BURST_SHIFT                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_BURST_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_BURST_RANGE                      24:23
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_BURST_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_BURST_LSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_BURST_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_BURST_DEFAULT                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_BURST_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_BURST_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                  MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                 22:20
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                 19:17
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_RANGE                      16:16
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_MSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_PROT_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_PROT_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_PROT_RANGE                       15:14
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_PROT_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_PROT_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_PROT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_PROT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_PROT_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_PROT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID1_SHIFT                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID1_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID1_RANGE                     13:7
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID1_MSB                       MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID1_LSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID1_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID1_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID1_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID0_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID0_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID0_RANGE                     6:0
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID0_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID0_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID0_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID0_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID0_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH7_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0                   MK_ADDR_CONST(0x8001c)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_SCR                       SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_SCRREG                    GPCDMA_SCR_SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_RESET_VAL                         MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_RESET_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_READ_MASK                         MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_WRITE_MASK                        MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                      30:28
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                        MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                    MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                       MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                      27:27
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_RANGE                  26:23
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_MSB                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DEFAULT                        MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                      MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                      18:16
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                        MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                     MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                    MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_SHIFT                   MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_RANGE                   8:7
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_MSB                     MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_LSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                       MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                       6:0
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH7_WCOUNT_0
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0                     MK_ADDR_CONST(0x80020)
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_SCR                         SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_SCRREG                      GPCDMA_SCR_SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_WCOUNT_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_WCOUNT_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH7_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_WCOUNT_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_WCOUNT_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_WCOUNT_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_WCOUNT_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_WCOUNT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_WCOUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_WCOUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_WCOUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0                       MK_ADDR_CONST(0x80024)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_SCR                   SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_SCRREG                        GPCDMA_SCR_SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                  31:0
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0                       MK_ADDR_CONST(0x80028)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_SCR                   SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x8002c
+
+// Register GPCDMA_CHANNEL_CH7_ERR_STA_0
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0                    MK_ADDR_CONST(0x80030)
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_SCR                        SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_SCRREG                     GPCDMA_SCR_SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH7_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0                  MK_ADDR_CONST(0x80034)
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_SCR                      SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_SCRREG                   GPCDMA_SCR_SCR_CH7_0
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH7_TZ_0
+#define GPCDMA_CHANNEL_CH7_TZ_0                 MK_ADDR_CONST(0x80038)
+#define GPCDMA_CHANNEL_CH7_TZ_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH7_TZ_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH7_TZ_0_SCR                     SCR_TZ_0
+#define GPCDMA_CHANNEL_CH7_TZ_0_SCRREG                  GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH7_TZ_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH7_TZ_0_RESET_VAL                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH7_TZ_0_RESET_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH7_TZ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_TZ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_TZ_0_READ_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH7_TZ_0_WRITE_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MC_PROT_1_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MC_PROT_1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MC_PROT_1_RANGE                 1:1
+#define GPCDMA_CHANNEL_CH7_TZ_0_MC_PROT_1_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MC_PROT_1_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MC_PROT_1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH7_TZ_0_MC_PROT_1_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MC_PROT_1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MC_PROT_1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MC_PROT_1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH7_TZ_0_MMIO_PROT_1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MMIO_PROT_1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH7_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MMIO_PROT_1_RANGE                       0:0
+#define GPCDMA_CHANNEL_CH7_TZ_0_MMIO_PROT_1_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MMIO_PROT_1_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MMIO_PROT_1_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH7_TZ_0_MMIO_PROT_1_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MMIO_PROT_1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MMIO_PROT_1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH7_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH8_CSR_0
+#define GPCDMA_CHANNEL_CH8_CSR_0                        MK_ADDR_CONST(0x90000)
+#define GPCDMA_CHANNEL_CH8_CSR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH8_CSR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH8_CSR_0_SCR                    SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_CSR_0_SCRREG                         GPCDMA_SCR_SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_CSR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH8_CSR_0_RESET_VAL                      MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH8_CSR_0_RESET_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH8_CSR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_READ_MASK                      MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH8_CSR_0_WRITE_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ENB_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ENB_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ENB_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH8_CSR_0_ENB_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ENB_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ENB_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH8_CSR_0_ENB_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ENB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ENB_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ENB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ENB_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ENB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ENB_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ENB_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH8_CSR_0_IE_EOC_SHIFT                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IE_EOC_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IE_EOC_RANGE                   30:30
+#define GPCDMA_CHANNEL_CH8_CSR_0_IE_EOC_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IE_EOC_LSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IE_EOC_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH8_CSR_0_IE_EOC_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IE_EOC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IE_EOC_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IE_EOC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IE_EOC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IE_EOC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IE_EOC_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IE_EOC_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH8_CSR_0_ONCE_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ONCE_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ONCE_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH8_CSR_0_ONCE_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ONCE_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ONCE_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH8_CSR_0_ONCE_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ONCE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ONCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ONCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ONCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ONCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ONCE_CYCLIC_MODE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_ONCE_SINGLE_BLOCK                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH8_CSR_0_FC_MODE_SHIFT                  MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH8_CSR_0_FC_MODE_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH8_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH8_CSR_0_FC_MODE_RANGE                  25:24
+#define GPCDMA_CHANNEL_CH8_CSR_0_FC_MODE_MSB                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH8_CSR_0_FC_MODE_LSB                    MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH8_CSR_0_FC_MODE_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH8_CSR_0_FC_MODE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_FC_MODE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH8_CSR_0_FC_MODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_FC_MODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_FC_MODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_FC_MODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_CSR_0_FC_MODE_NO_MMIO                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_FC_MODE_ONE_MMIO                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH8_CSR_0_FC_MODE_TWO_MMIO                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH8_CSR_0_FC_MODE_FOUR_MMIO                      MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_RANGE                 23:21
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_IO2MEM_NO_FC                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_IO2MEM_FC                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_MEM2IO_NO_FC                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_MEM2IO_FC                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_MEM2MEM                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_RSVD                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH8_CSR_0_DMA_MODE_FIXED_PAT                     MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_FIELD                  MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_RANGE                  20:16
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_0                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_1                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_2                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_3                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_4                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_5                       MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_6                       MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_7                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_8                       MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_9                       MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_10                      MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_11                      MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_12                      MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_13                      MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_14                      MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_15                      MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_16                      MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_17                      MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_18                      MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_19                      MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_20                      MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_21                      MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_22                      MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_23                      MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_24                      MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_25                      MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_26                      MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_27                      MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_28                      MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_29_RSVD                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_30                      MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_CLIENT_31                      MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH8_CSR_0_REQ_SEL_RSVD                   MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH8_CSR_0_IRQ_MASK_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IRQ_MASK_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IRQ_MASK_RANGE                 15:15
+#define GPCDMA_CHANNEL_CH8_CSR_0_IRQ_MASK_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IRQ_MASK_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IRQ_MASK_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH8_CSR_0_IRQ_MASK_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IRQ_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IRQ_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IRQ_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IRQ_MASK_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_IRQ_MASK_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH8_CSR_0_WEIGHT_SHIFT                   MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH8_CSR_0_WEIGHT_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH8_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH8_CSR_0_WEIGHT_RANGE                   13:10
+#define GPCDMA_CHANNEL_CH8_CSR_0_WEIGHT_MSB                     MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH8_CSR_0_WEIGHT_LSB                     MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH8_CSR_0_WEIGHT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH8_CSR_0_WEIGHT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_CSR_0_WEIGHT_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH8_CSR_0_WEIGHT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_WEIGHT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_WEIGHT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSR_0_WEIGHT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH8_STA_0
+#define GPCDMA_CHANNEL_CH8_STA_0                        MK_ADDR_CONST(0x90004)
+#define GPCDMA_CHANNEL_CH8_STA_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH8_STA_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH8_STA_0_SCR                    SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_STA_0_SCRREG                         GPCDMA_SCR_SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_STA_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH8_STA_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_RESET_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH8_STA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_READ_MASK                      MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH8_STA_0_WRITE_MASK                     MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH8_STA_0_BSY_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_STA_0_BSY_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH8_STA_0_BSY_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH8_STA_0_BSY_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_STA_0_BSY_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_STA_0_BSY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH8_STA_0_BSY_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_BSY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_BSY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_BSY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_BSY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_BSY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_BSY_WAIT                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_STA_0_BSY_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH8_STA_0_ISE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH8_STA_0_ISE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH8_STA_0_ISE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH8_STA_0_ISE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH8_STA_0_ISE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH8_STA_0_ISE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH8_STA_0_ISE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_ISE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_ISE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_ISE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_ISE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_ISE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_ISE_EOC_NO_INTR                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_STA_0_ISE_EOC_INTR                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH8_STA_0_PING_PONG_STA_SHIFT                    MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH8_STA_0_PING_PONG_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH8_STA_0_PING_PONG_STA_RANGE                    28:28
+#define GPCDMA_CHANNEL_CH8_STA_0_PING_PONG_STA_MSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH8_STA_0_PING_PONG_STA_LSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH8_STA_0_PING_PONG_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH8_STA_0_PING_PONG_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_PING_PONG_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_PING_PONG_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_PING_PONG_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_PING_PONG_STA_PING_INTR_STA                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_STA_0_PING_PONG_STA_PONG_INTR_STA                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH8_STA_0_DMA_ACTIVITY_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH8_STA_0_DMA_ACTIVITY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH8_STA_0_DMA_ACTIVITY_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH8_STA_0_DMA_ACTIVITY_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH8_STA_0_DMA_ACTIVITY_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH8_STA_0_DMA_ACTIVITY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH8_STA_0_DMA_ACTIVITY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_DMA_ACTIVITY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_DMA_ACTIVITY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_DMA_ACTIVITY_IDLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_STA_0_DMA_ACTIVITY_BUSY                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_PAUSE_SHIFT                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_PAUSE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_PAUSE_RANGE                    26:26
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_PAUSE_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_PAUSE_LSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_PAUSE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_PAUSE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_PAUSE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_PAUSE_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_PAUSE_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_RX_SHIFT                       MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_RX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_RX_RANGE                       25:25
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_RX_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_RX_LSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_RX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_RX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_RX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_RX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_RX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_RX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_RX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_TX_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_TX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_TX_RANGE                       24:24
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_TX_MSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_TX_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_TX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_TX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_TX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_TX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_TX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_TX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_STA_0_CHANNEL_TX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH8_STA_0_IRQ_INTR_STA_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH8_STA_0_IRQ_INTR_STA_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH8_STA_0_IRQ_INTR_STA_RANGE                     23:23
+#define GPCDMA_CHANNEL_CH8_STA_0_IRQ_INTR_STA_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH8_STA_0_IRQ_INTR_STA_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH8_STA_0_IRQ_INTR_STA_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH8_STA_0_IRQ_INTR_STA_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_IRQ_INTR_STA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_IRQ_INTR_STA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_IRQ_INTR_STA_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_STA_0_IRQ_INTR_STA_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH8_STA_0_TRIG_STA_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH8_STA_0_TRIG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH8_STA_0_TRIG_STA_RANGE                 21:21
+#define GPCDMA_CHANNEL_CH8_STA_0_TRIG_STA_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH8_STA_0_TRIG_STA_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH8_STA_0_TRIG_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH8_STA_0_TRIG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_TRIG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_TRIG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_TRIG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_TRIG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_TRIG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_TRIG_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_STA_0_TRIG_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH8_STA_0_INTR_STA_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH8_STA_0_INTR_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH8_STA_0_INTR_STA_RANGE                 20:20
+#define GPCDMA_CHANNEL_CH8_STA_0_INTR_STA_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH8_STA_0_INTR_STA_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH8_STA_0_INTR_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH8_STA_0_INTR_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_INTR_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_INTR_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_INTR_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_INTR_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_STA_0_INTR_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_STA_0_INTR_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_STA_0_INTR_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH8_CSRE_0
+#define GPCDMA_CHANNEL_CH8_CSRE_0                       MK_ADDR_CONST(0x90008)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH8_CSRE_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH8_CSRE_0_SCR                   SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_CSRE_0_SCRREG                        GPCDMA_SCR_SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_CSRE_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH8_CSRE_0_RESET_VAL                     MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_RESET_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_READ_MASK                     MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_WRITE_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_DMA_ACTIVITY_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH8_CSRE_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH8_CSRE_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_DMA_ACTIVITY_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_DMA_ACTIVITY_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_SHIFT                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_FIELD                        MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_RANGE                        19:14
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_LSB                  MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_DEFAULT                      MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH0                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH1                  MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH2                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH3                  MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH4                  MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH5                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH6                  MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH7                  MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH8                  MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH9                  MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH10                 MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH11                 MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH12                 MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH13                 MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH14                 MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH15                 MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH16                 MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH17                 MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH18                 MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH19                 MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH20                 MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH21                 MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH22                 MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH23                 MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH24                 MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH25                 MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH26                 MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH27                 MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH28                 MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH29                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH30                 MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_CH31                 MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH8_CSRE_0_TRIG_SEL_RSVD                 MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH8_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0                    MK_ADDR_CONST(0x9000c)
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_SCR                        SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_SRC_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_SRC_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH8_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_SRC_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_SRC_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_SRC_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_SRC_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_SRC_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_SRC_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH8_DST_PTR_0
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0                    MK_ADDR_CONST(0x90010)
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_SCR                        SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_DST_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_DST_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH8_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_DST_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_DST_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_DST_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_DST_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_DST_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_DST_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_DST_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_DST_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0                 MK_ADDR_CONST(0x90014)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_SCR                     SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_SCRREG                  GPCDMA_SCR_SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_RESET_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_READ_MASK                       MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_DST_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_DST_PTR_RANGE                        23:16
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_DST_PTR_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_DST_PTR_LSB                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                        7:0
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_SRC_PTR_MSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_SRC_PTR_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH8_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0                     MK_ADDR_CONST(0x90018)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_SCR                         SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_SCRREG                      GPCDMA_SCR_SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_RESET_VAL                   MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_DATA_SWAP_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_DATA_SWAP_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_DATA_SWAP_RANGE                  31:31
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_DATA_SWAP_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_DATA_SWAP_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_DATA_SWAP_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_DATA_SWAP_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_REQ_CNT_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_REQ_CNT_FIELD                    MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_REQ_CNT_RANGE                    30:25
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_REQ_CNT_MSB                      MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_REQ_CNT_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_REQ_CNT_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_REQ_CNT_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                     MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_BURST_SHIFT                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_BURST_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_BURST_RANGE                      24:23
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_BURST_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_BURST_LSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_BURST_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_BURST_DEFAULT                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_BURST_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_BURST_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                  MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                 22:20
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                 19:17
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_AXIID_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_AXIID_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_AXIID_RANGE                      16:16
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_AXIID_MSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_AXIID_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_AXIID_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_AXIID_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_AXIID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_PROT_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_PROT_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_PROT_RANGE                       15:14
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_PROT_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_PROT_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_PROT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_PROT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_PROT_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_PROT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID1_SHIFT                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID1_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID1_RANGE                     13:7
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID1_MSB                       MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID1_LSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID1_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID1_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID1_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID0_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID0_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID0_RANGE                     6:0
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID0_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID0_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID0_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID0_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID0_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH8_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0                   MK_ADDR_CONST(0x9001c)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_SCR                       SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_SCRREG                    GPCDMA_SCR_SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_RESET_VAL                         MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_RESET_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_READ_MASK                         MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_WRITE_MASK                        MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_DBL_BUF_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_DBL_BUF_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_DBL_BUF_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_DBL_BUF_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_DBL_BUF_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_DBL_BUF_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_DBL_BUF_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_DBL_BUF_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_DBL_BUF_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                      30:28
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                        MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                    MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                       MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                      27:27
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_RANGE                  26:23
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_MSB                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_DEFAULT                        MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                      MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                      18:16
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                        MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                     MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                    MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_PROT_SHIFT                   MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_PROT_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_PROT_RANGE                   8:7
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_PROT_MSB                     MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_PROT_LSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_PROT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_PROT_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                       MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                       6:0
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH8_WCOUNT_0
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0                     MK_ADDR_CONST(0x90020)
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_SCR                         SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_SCRREG                      GPCDMA_SCR_SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_WCOUNT_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_WCOUNT_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH8_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_WCOUNT_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_WCOUNT_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_WCOUNT_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_WCOUNT_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_WCOUNT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_WCOUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_WCOUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_WCOUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0                       MK_ADDR_CONST(0x90024)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_SCR                   SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_SCRREG                        GPCDMA_SCR_SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                  31:0
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0                       MK_ADDR_CONST(0x90028)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_SCR                   SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_DMA_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_DMA_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_DMA_COUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_DMA_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_DMA_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x9002c
+
+// Register GPCDMA_CHANNEL_CH8_ERR_STA_0
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0                    MK_ADDR_CONST(0x90030)
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_SCR                        SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_SCRREG                     GPCDMA_SCR_SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_ERROR_STATUS_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_ERROR_STATUS_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH8_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_ERROR_STATUS_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_ERROR_STATUS_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_ERROR_STATUS_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_ERROR_STATUS_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_ERROR_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH8_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0                  MK_ADDR_CONST(0x90034)
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_SCR                      SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_SCRREG                   GPCDMA_SCR_SCR_CH8_0
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_FIXED_PATTERN_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_FIXED_PATTERN_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH8_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_FIXED_PATTERN_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_FIXED_PATTERN_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_FIXED_PATTERN_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH8_TZ_0
+#define GPCDMA_CHANNEL_CH8_TZ_0                 MK_ADDR_CONST(0x90038)
+#define GPCDMA_CHANNEL_CH8_TZ_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH8_TZ_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH8_TZ_0_SCR                     SCR_TZ_0
+#define GPCDMA_CHANNEL_CH8_TZ_0_SCRREG                  GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH8_TZ_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH8_TZ_0_RESET_VAL                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH8_TZ_0_RESET_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH8_TZ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_TZ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_TZ_0_READ_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH8_TZ_0_WRITE_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MC_PROT_1_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MC_PROT_1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MC_PROT_1_RANGE                 1:1
+#define GPCDMA_CHANNEL_CH8_TZ_0_MC_PROT_1_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MC_PROT_1_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MC_PROT_1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH8_TZ_0_MC_PROT_1_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MC_PROT_1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MC_PROT_1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MC_PROT_1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH8_TZ_0_MMIO_PROT_1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MMIO_PROT_1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH8_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MMIO_PROT_1_RANGE                       0:0
+#define GPCDMA_CHANNEL_CH8_TZ_0_MMIO_PROT_1_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MMIO_PROT_1_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MMIO_PROT_1_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH8_TZ_0_MMIO_PROT_1_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MMIO_PROT_1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MMIO_PROT_1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH8_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH9_CSR_0
+#define GPCDMA_CHANNEL_CH9_CSR_0                        MK_ADDR_CONST(0xa0000)
+#define GPCDMA_CHANNEL_CH9_CSR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH9_CSR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH9_CSR_0_SCR                    SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_CSR_0_SCRREG                         GPCDMA_SCR_SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_CSR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH9_CSR_0_RESET_VAL                      MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH9_CSR_0_RESET_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH9_CSR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_READ_MASK                      MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH9_CSR_0_WRITE_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ENB_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ENB_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ENB_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH9_CSR_0_ENB_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ENB_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ENB_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH9_CSR_0_ENB_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ENB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ENB_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ENB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ENB_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ENB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ENB_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ENB_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH9_CSR_0_IE_EOC_SHIFT                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IE_EOC_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IE_EOC_RANGE                   30:30
+#define GPCDMA_CHANNEL_CH9_CSR_0_IE_EOC_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IE_EOC_LSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IE_EOC_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH9_CSR_0_IE_EOC_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IE_EOC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IE_EOC_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IE_EOC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IE_EOC_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IE_EOC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IE_EOC_DISABLE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IE_EOC_ENABLE                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH9_CSR_0_ONCE_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ONCE_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ONCE_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH9_CSR_0_ONCE_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ONCE_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ONCE_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH9_CSR_0_ONCE_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ONCE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ONCE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ONCE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ONCE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ONCE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ONCE_CYCLIC_MODE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_ONCE_SINGLE_BLOCK                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH9_CSR_0_FC_MODE_SHIFT                  MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH9_CSR_0_FC_MODE_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH9_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH9_CSR_0_FC_MODE_RANGE                  25:24
+#define GPCDMA_CHANNEL_CH9_CSR_0_FC_MODE_MSB                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH9_CSR_0_FC_MODE_LSB                    MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH9_CSR_0_FC_MODE_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH9_CSR_0_FC_MODE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_FC_MODE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH9_CSR_0_FC_MODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_FC_MODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_FC_MODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_FC_MODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_CSR_0_FC_MODE_NO_MMIO                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_FC_MODE_ONE_MMIO                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH9_CSR_0_FC_MODE_TWO_MMIO                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH9_CSR_0_FC_MODE_FOUR_MMIO                      MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_RANGE                 23:21
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_IO2MEM_NO_FC                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_IO2MEM_FC                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_MEM2IO_NO_FC                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_MEM2IO_FC                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_MEM2MEM                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_RSVD                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH9_CSR_0_DMA_MODE_FIXED_PAT                     MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_FIELD                  MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_RANGE                  20:16
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_0                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_1                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_2                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_3                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_4                       MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_5                       MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_6                       MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_7                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_8                       MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_9                       MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_10                      MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_11                      MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_12                      MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_13                      MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_14                      MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_15                      MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_16                      MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_17                      MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_18                      MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_19                      MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_20                      MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_21                      MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_22                      MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_23                      MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_24                      MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_25                      MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_26                      MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_27                      MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_28                      MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_29_RSVD                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_30                      MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_CLIENT_31                      MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH9_CSR_0_REQ_SEL_RSVD                   MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH9_CSR_0_IRQ_MASK_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IRQ_MASK_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IRQ_MASK_RANGE                 15:15
+#define GPCDMA_CHANNEL_CH9_CSR_0_IRQ_MASK_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IRQ_MASK_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IRQ_MASK_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH9_CSR_0_IRQ_MASK_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IRQ_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IRQ_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IRQ_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IRQ_MASK_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_IRQ_MASK_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH9_CSR_0_WEIGHT_SHIFT                   MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH9_CSR_0_WEIGHT_FIELD                   MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH9_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH9_CSR_0_WEIGHT_RANGE                   13:10
+#define GPCDMA_CHANNEL_CH9_CSR_0_WEIGHT_MSB                     MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH9_CSR_0_WEIGHT_LSB                     MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH9_CSR_0_WEIGHT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH9_CSR_0_WEIGHT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_CSR_0_WEIGHT_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH9_CSR_0_WEIGHT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_WEIGHT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_WEIGHT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSR_0_WEIGHT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH9_STA_0
+#define GPCDMA_CHANNEL_CH9_STA_0                        MK_ADDR_CONST(0xa0004)
+#define GPCDMA_CHANNEL_CH9_STA_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH9_STA_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH9_STA_0_SCR                    SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_STA_0_SCRREG                         GPCDMA_SCR_SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_STA_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH9_STA_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_RESET_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH9_STA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_READ_MASK                      MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH9_STA_0_WRITE_MASK                     MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH9_STA_0_BSY_SHIFT                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_STA_0_BSY_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH9_STA_0_BSY_RANGE                      31:31
+#define GPCDMA_CHANNEL_CH9_STA_0_BSY_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_STA_0_BSY_LSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_STA_0_BSY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH9_STA_0_BSY_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_BSY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_BSY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_BSY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_BSY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_BSY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_BSY_WAIT                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_STA_0_BSY_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH9_STA_0_ISE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH9_STA_0_ISE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH9_STA_0_ISE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH9_STA_0_ISE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH9_STA_0_ISE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH9_STA_0_ISE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH9_STA_0_ISE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_ISE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_ISE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_ISE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_ISE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_ISE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_ISE_EOC_NO_INTR                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_STA_0_ISE_EOC_INTR                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH9_STA_0_PING_PONG_STA_SHIFT                    MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH9_STA_0_PING_PONG_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH9_STA_0_PING_PONG_STA_RANGE                    28:28
+#define GPCDMA_CHANNEL_CH9_STA_0_PING_PONG_STA_MSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH9_STA_0_PING_PONG_STA_LSB                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH9_STA_0_PING_PONG_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH9_STA_0_PING_PONG_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_PING_PONG_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_PING_PONG_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_PING_PONG_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_PING_PONG_STA_PING_INTR_STA                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_STA_0_PING_PONG_STA_PONG_INTR_STA                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH9_STA_0_DMA_ACTIVITY_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH9_STA_0_DMA_ACTIVITY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH9_STA_0_DMA_ACTIVITY_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH9_STA_0_DMA_ACTIVITY_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH9_STA_0_DMA_ACTIVITY_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH9_STA_0_DMA_ACTIVITY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH9_STA_0_DMA_ACTIVITY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_DMA_ACTIVITY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_DMA_ACTIVITY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_DMA_ACTIVITY_IDLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_STA_0_DMA_ACTIVITY_BUSY                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_PAUSE_SHIFT                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_PAUSE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_PAUSE_RANGE                    26:26
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_PAUSE_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_PAUSE_LSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_PAUSE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_PAUSE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_PAUSE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_PAUSE_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_PAUSE_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_RX_SHIFT                       MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_RX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_RX_RANGE                       25:25
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_RX_MSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_RX_LSB                 MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_RX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_RX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_RX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_RX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_RX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_RX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_RX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_TX_SHIFT                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_TX_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_TX_RANGE                       24:24
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_TX_MSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_TX_LSB                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_TX_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_TX_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_TX_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_TX_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_TX_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_TX_NOT_ACTIVE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_STA_0_CHANNEL_TX_ACTIVE                      MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH9_STA_0_IRQ_INTR_STA_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH9_STA_0_IRQ_INTR_STA_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH9_STA_0_IRQ_INTR_STA_RANGE                     23:23
+#define GPCDMA_CHANNEL_CH9_STA_0_IRQ_INTR_STA_MSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH9_STA_0_IRQ_INTR_STA_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH9_STA_0_IRQ_INTR_STA_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH9_STA_0_IRQ_INTR_STA_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_IRQ_INTR_STA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_IRQ_INTR_STA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_IRQ_INTR_STA_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_STA_0_IRQ_INTR_STA_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH9_STA_0_TRIG_STA_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH9_STA_0_TRIG_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH9_STA_0_TRIG_STA_RANGE                 21:21
+#define GPCDMA_CHANNEL_CH9_STA_0_TRIG_STA_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH9_STA_0_TRIG_STA_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH9_STA_0_TRIG_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH9_STA_0_TRIG_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_TRIG_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_TRIG_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_TRIG_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_TRIG_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_TRIG_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_TRIG_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_STA_0_TRIG_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH9_STA_0_INTR_STA_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH9_STA_0_INTR_STA_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH9_STA_0_INTR_STA_RANGE                 20:20
+#define GPCDMA_CHANNEL_CH9_STA_0_INTR_STA_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH9_STA_0_INTR_STA_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH9_STA_0_INTR_STA_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH9_STA_0_INTR_STA_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_INTR_STA_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_INTR_STA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_INTR_STA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_INTR_STA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_STA_0_INTR_STA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_STA_0_INTR_STA_NOT_ACTIVE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_STA_0_INTR_STA_ACTIVE                        MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH9_CSRE_0
+#define GPCDMA_CHANNEL_CH9_CSRE_0                       MK_ADDR_CONST(0xa0008)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH9_CSRE_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH9_CSRE_0_SCR                   SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_CSRE_0_SCRREG                        GPCDMA_SCR_SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_CSRE_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH9_CSRE_0_RESET_VAL                     MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_RESET_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_READ_MASK                     MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_WRITE_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_DMA_ACTIVITY_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH9_CSRE_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH9_CSRE_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_DMA_ACTIVITY_RESUME                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_DMA_ACTIVITY_PAUSE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_SHIFT                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_FIELD                        MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_RANGE                        19:14
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_LSB                  MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_DEFAULT                      MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH0                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH1                  MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH2                  MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH3                  MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH4                  MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH5                  MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH6                  MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH7                  MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH8                  MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH9                  MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH10                 MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH11                 MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH12                 MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH13                 MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH14                 MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH15                 MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH16                 MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH17                 MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH18                 MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH19                 MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH20                 MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH21                 MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH22                 MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH23                 MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH24                 MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH25                 MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH26                 MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH27                 MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH28                 MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH29                 MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH30                 MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_CH31                 MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH9_CSRE_0_TRIG_SEL_RSVD                 MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH9_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0                    MK_ADDR_CONST(0xa000c)
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_SCR                        SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_SRC_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_SRC_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH9_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_SRC_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_SRC_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_SRC_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_SRC_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_SRC_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_SRC_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH9_DST_PTR_0
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0                    MK_ADDR_CONST(0xa0010)
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_SCR                        SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_SCRREG                     GPCDMA_SCR_SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_DST_PTR_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_DST_PTR_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH9_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_DST_PTR_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_DST_PTR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_DST_PTR_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_DST_PTR_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_DST_PTR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_DST_PTR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_DST_PTR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_DST_PTR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0                 MK_ADDR_CONST(0xa0014)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_SCR                     SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_SCRREG                  GPCDMA_SCR_SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_RESET_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_READ_MASK                       MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_WRITE_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_DST_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_DST_PTR_RANGE                        23:16
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_DST_PTR_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_DST_PTR_LSB                  MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                        MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                        7:0
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_SRC_PTR_MSB                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_SRC_PTR_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH9_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0                     MK_ADDR_CONST(0xa0018)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_SCR                         SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_SCRREG                      GPCDMA_SCR_SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_RESET_VAL                   MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_DATA_SWAP_SHIFT                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_DATA_SWAP_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_DATA_SWAP_RANGE                  31:31
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_DATA_SWAP_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_DATA_SWAP_LSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_DATA_SWAP_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_DATA_SWAP_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_REQ_CNT_SHIFT                    MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_REQ_CNT_FIELD                    MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_REQ_CNT_RANGE                    30:25
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_REQ_CNT_MSB                      MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_REQ_CNT_LSB                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_REQ_CNT_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_REQ_CNT_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                     MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_BURST_SHIFT                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_BURST_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_BURST_RANGE                      24:23
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_BURST_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_BURST_LSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_BURST_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_BURST_DEFAULT                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_BURST_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_BURST_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                  MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                 22:20
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                 19:17
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                       MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                     MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                     MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_AXIID_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_AXIID_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_AXIID_RANGE                      16:16
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_AXIID_MSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_AXIID_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_AXIID_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_AXIID_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_AXIID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_PROT_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_PROT_FIELD                       MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_PROT_RANGE                       15:14
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_PROT_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_PROT_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_PROT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_PROT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_PROT_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_PROT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID1_SHIFT                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID1_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID1_RANGE                     13:7
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID1_MSB                       MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID1_LSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID1_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID1_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID1_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID0_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID0_FIELD                     MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID0_RANGE                     6:0
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID0_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID0_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID0_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID0_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID0_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH9_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0                   MK_ADDR_CONST(0xa001c)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_SCR                       SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_SCRREG                    GPCDMA_SCR_SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_RESET_VAL                         MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_RESET_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_READ_MASK                         MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_WRITE_MASK                        MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_DBL_BUF_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_DBL_BUF_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_DBL_BUF_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_DBL_BUF_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_DBL_BUF_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_DBL_BUF_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_DBL_BUF_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_DBL_BUF_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_DBL_BUF_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                      30:28
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                        MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                    MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                       MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                      27:27
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_RANGE                  26:23
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_MSB                    MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_DEFAULT                        MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                       MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                       MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                       MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                      MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                      MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                      18:16
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                        MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                    MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                     MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                     MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                    MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_PROT_SHIFT                   MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_PROT_FIELD                   MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_PROT_RANGE                   8:7
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_PROT_MSB                     MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_PROT_LSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_PROT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_PROT_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                       MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                       6:0
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH9_WCOUNT_0
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0                     MK_ADDR_CONST(0xa0020)
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_SECURE                      0x0
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_DUAL                        0x0
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_SCR                         SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_SCRREG                      GPCDMA_SCR_SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_WORD_COUNT                  0x1
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_WCOUNT_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_WCOUNT_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH9_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_WCOUNT_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_WCOUNT_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_WCOUNT_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_WCOUNT_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_WCOUNT_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_WCOUNT_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_WCOUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_WCOUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0                       MK_ADDR_CONST(0xa0024)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_SCR                   SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_SCRREG                        GPCDMA_SCR_SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                  31:0
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0                       MK_ADDR_CONST(0xa0028)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_SCR                   SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_DMA_COUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_DMA_COUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_DMA_COUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_DMA_COUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_DMA_COUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xa002c
+
+// Register GPCDMA_CHANNEL_CH9_ERR_STA_0
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0                    MK_ADDR_CONST(0xa0030)
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_SCR                        SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_SCRREG                     GPCDMA_SCR_SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_ERROR_STATUS_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_ERROR_STATUS_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH9_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_ERROR_STATUS_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_ERROR_STATUS_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_ERROR_STATUS_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_ERROR_STATUS_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_ERROR_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH9_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0                  MK_ADDR_CONST(0xa0034)
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_SCR                      SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_SCRREG                   GPCDMA_SCR_SCR_CH9_0
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_FIXED_PATTERN_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_FIXED_PATTERN_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH9_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_FIXED_PATTERN_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_FIXED_PATTERN_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_FIXED_PATTERN_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH9_TZ_0
+#define GPCDMA_CHANNEL_CH9_TZ_0                 MK_ADDR_CONST(0xa0038)
+#define GPCDMA_CHANNEL_CH9_TZ_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH9_TZ_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH9_TZ_0_SCR                     SCR_TZ_0
+#define GPCDMA_CHANNEL_CH9_TZ_0_SCRREG                  GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH9_TZ_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH9_TZ_0_RESET_VAL                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH9_TZ_0_RESET_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH9_TZ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_TZ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_TZ_0_READ_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH9_TZ_0_WRITE_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MC_PROT_1_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MC_PROT_1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MC_PROT_1_RANGE                 1:1
+#define GPCDMA_CHANNEL_CH9_TZ_0_MC_PROT_1_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MC_PROT_1_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MC_PROT_1_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH9_TZ_0_MC_PROT_1_DEFAULT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MC_PROT_1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MC_PROT_1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MC_PROT_1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH9_TZ_0_MMIO_PROT_1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MMIO_PROT_1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH9_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MMIO_PROT_1_RANGE                       0:0
+#define GPCDMA_CHANNEL_CH9_TZ_0_MMIO_PROT_1_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MMIO_PROT_1_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MMIO_PROT_1_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH9_TZ_0_MMIO_PROT_1_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MMIO_PROT_1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MMIO_PROT_1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH9_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH10_CSR_0
+#define GPCDMA_CHANNEL_CH10_CSR_0                       MK_ADDR_CONST(0xb0000)
+#define GPCDMA_CHANNEL_CH10_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH10_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH10_CSR_0_SCR                   SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH10_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH10_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH10_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH10_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH10_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH10_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH10_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH10_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH10_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH10_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH10_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH10_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH10_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH10_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH10_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH10_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH10_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH10_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH10_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH10_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH10_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH10_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH10_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH10_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH10_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH10_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH10_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH10_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH10_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH10_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH10_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH10_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH10_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH10_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH10_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH10_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH10_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH10_STA_0
+#define GPCDMA_CHANNEL_CH10_STA_0                       MK_ADDR_CONST(0xb0004)
+#define GPCDMA_CHANNEL_CH10_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH10_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH10_STA_0_SCR                   SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH10_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH10_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH10_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH10_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH10_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH10_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH10_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH10_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH10_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH10_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH10_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH10_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH10_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH10_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH10_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH10_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH10_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH10_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH10_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH10_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH10_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH10_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH10_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH10_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH10_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH10_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH10_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH10_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH10_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH10_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH10_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH10_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH10_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH10_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH10_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH10_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH10_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH10_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH10_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH10_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH10_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH10_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH10_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH10_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH10_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH10_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH10_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH10_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH10_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH10_CSRE_0
+#define GPCDMA_CHANNEL_CH10_CSRE_0                      MK_ADDR_CONST(0xb0008)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH10_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH10_CSRE_0_SCR                  SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH10_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH10_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH10_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH10_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH10_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0                   MK_ADDR_CONST(0xb000c)
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_SCR                       SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH10_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH10_DST_PTR_0
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0                   MK_ADDR_CONST(0xb0010)
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_SCR                       SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH10_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0                        MK_ADDR_CONST(0xb0014)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_SCR                    SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH10_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0                    MK_ADDR_CONST(0xb0018)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_SCR                        SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH10_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0                  MK_ADDR_CONST(0xb001c)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_SCR                      SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH10_WCOUNT_0
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0                    MK_ADDR_CONST(0xb0020)
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_SCR                        SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH10_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0                      MK_ADDR_CONST(0xb0024)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_SCR                  SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0                      MK_ADDR_CONST(0xb0028)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_SCR                  SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xb002c
+
+// Register GPCDMA_CHANNEL_CH10_ERR_STA_0
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0                   MK_ADDR_CONST(0xb0030)
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_SCR                       SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH10_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH10_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0                 MK_ADDR_CONST(0xb0034)
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_SCR                     SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH10_0
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH10_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH10_TZ_0
+#define GPCDMA_CHANNEL_CH10_TZ_0                        MK_ADDR_CONST(0xb0038)
+#define GPCDMA_CHANNEL_CH10_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH10_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH10_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH10_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH10_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH10_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH10_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH10_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH10_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH10_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH10_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH10_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH10_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH10_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH10_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH10_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH11_CSR_0
+#define GPCDMA_CHANNEL_CH11_CSR_0                       MK_ADDR_CONST(0xc0000)
+#define GPCDMA_CHANNEL_CH11_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH11_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH11_CSR_0_SCR                   SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH11_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH11_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH11_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH11_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH11_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH11_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH11_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH11_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH11_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH11_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH11_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH11_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH11_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH11_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH11_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH11_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH11_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH11_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH11_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH11_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH11_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH11_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH11_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH11_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH11_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH11_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH11_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH11_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH11_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH11_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH11_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH11_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH11_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH11_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH11_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH11_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH11_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH11_STA_0
+#define GPCDMA_CHANNEL_CH11_STA_0                       MK_ADDR_CONST(0xc0004)
+#define GPCDMA_CHANNEL_CH11_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH11_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH11_STA_0_SCR                   SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH11_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH11_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH11_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH11_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH11_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH11_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH11_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH11_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH11_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH11_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH11_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH11_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH11_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH11_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH11_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH11_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH11_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH11_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH11_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH11_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH11_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH11_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH11_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH11_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH11_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH11_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH11_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH11_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH11_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH11_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH11_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH11_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH11_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH11_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH11_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH11_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH11_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH11_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH11_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH11_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH11_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH11_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH11_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH11_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH11_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH11_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH11_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH11_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH11_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH11_CSRE_0
+#define GPCDMA_CHANNEL_CH11_CSRE_0                      MK_ADDR_CONST(0xc0008)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH11_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH11_CSRE_0_SCR                  SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH11_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH11_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH11_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH11_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH11_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0                   MK_ADDR_CONST(0xc000c)
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_SCR                       SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH11_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH11_DST_PTR_0
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0                   MK_ADDR_CONST(0xc0010)
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_SCR                       SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH11_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0                        MK_ADDR_CONST(0xc0014)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_SCR                    SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH11_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0                    MK_ADDR_CONST(0xc0018)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_SCR                        SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH11_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0                  MK_ADDR_CONST(0xc001c)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_SCR                      SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH11_WCOUNT_0
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0                    MK_ADDR_CONST(0xc0020)
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_SCR                        SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH11_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0                      MK_ADDR_CONST(0xc0024)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_SCR                  SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0                      MK_ADDR_CONST(0xc0028)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_SCR                  SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xc002c
+
+// Register GPCDMA_CHANNEL_CH11_ERR_STA_0
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0                   MK_ADDR_CONST(0xc0030)
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_SCR                       SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH11_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH11_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0                 MK_ADDR_CONST(0xc0034)
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_SCR                     SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH11_0
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH11_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH11_TZ_0
+#define GPCDMA_CHANNEL_CH11_TZ_0                        MK_ADDR_CONST(0xc0038)
+#define GPCDMA_CHANNEL_CH11_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH11_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH11_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH11_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH11_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH11_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH11_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH11_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH11_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH11_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH11_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH11_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH11_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH11_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH11_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH11_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH12_CSR_0
+#define GPCDMA_CHANNEL_CH12_CSR_0                       MK_ADDR_CONST(0xd0000)
+#define GPCDMA_CHANNEL_CH12_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH12_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH12_CSR_0_SCR                   SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH12_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH12_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH12_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH12_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH12_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH12_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH12_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH12_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH12_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH12_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH12_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH12_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH12_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH12_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH12_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH12_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH12_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH12_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH12_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH12_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH12_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH12_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH12_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH12_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH12_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH12_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH12_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH12_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH12_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH12_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH12_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH12_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH12_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH12_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH12_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH12_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH12_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH12_STA_0
+#define GPCDMA_CHANNEL_CH12_STA_0                       MK_ADDR_CONST(0xd0004)
+#define GPCDMA_CHANNEL_CH12_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH12_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH12_STA_0_SCR                   SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH12_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH12_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH12_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH12_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH12_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH12_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH12_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH12_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH12_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH12_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH12_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH12_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH12_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH12_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH12_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH12_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH12_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH12_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH12_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH12_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH12_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH12_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH12_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH12_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH12_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH12_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH12_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH12_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH12_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH12_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH12_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH12_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH12_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH12_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH12_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH12_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH12_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH12_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH12_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH12_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH12_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH12_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH12_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH12_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH12_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH12_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH12_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH12_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH12_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH12_CSRE_0
+#define GPCDMA_CHANNEL_CH12_CSRE_0                      MK_ADDR_CONST(0xd0008)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH12_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH12_CSRE_0_SCR                  SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH12_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH12_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH12_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH12_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH12_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0                   MK_ADDR_CONST(0xd000c)
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_SCR                       SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH12_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH12_DST_PTR_0
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0                   MK_ADDR_CONST(0xd0010)
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_SCR                       SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH12_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0                        MK_ADDR_CONST(0xd0014)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_SCR                    SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH12_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0                    MK_ADDR_CONST(0xd0018)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_SCR                        SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH12_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0                  MK_ADDR_CONST(0xd001c)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_SCR                      SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH12_WCOUNT_0
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0                    MK_ADDR_CONST(0xd0020)
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_SCR                        SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH12_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0                      MK_ADDR_CONST(0xd0024)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_SCR                  SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0                      MK_ADDR_CONST(0xd0028)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_SCR                  SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xd002c
+
+// Register GPCDMA_CHANNEL_CH12_ERR_STA_0
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0                   MK_ADDR_CONST(0xd0030)
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_SCR                       SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH12_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH12_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0                 MK_ADDR_CONST(0xd0034)
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_SCR                     SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH12_0
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH12_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH12_TZ_0
+#define GPCDMA_CHANNEL_CH12_TZ_0                        MK_ADDR_CONST(0xd0038)
+#define GPCDMA_CHANNEL_CH12_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH12_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH12_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH12_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH12_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH12_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH12_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH12_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH12_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH12_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH12_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH12_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH12_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH12_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH12_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH12_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH13_CSR_0
+#define GPCDMA_CHANNEL_CH13_CSR_0                       MK_ADDR_CONST(0xe0000)
+#define GPCDMA_CHANNEL_CH13_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH13_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH13_CSR_0_SCR                   SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH13_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH13_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH13_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH13_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH13_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH13_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH13_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH13_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH13_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH13_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH13_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH13_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH13_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH13_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH13_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH13_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH13_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH13_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH13_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH13_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH13_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH13_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH13_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH13_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH13_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH13_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH13_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH13_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH13_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH13_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH13_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH13_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH13_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH13_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH13_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH13_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH13_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH13_STA_0
+#define GPCDMA_CHANNEL_CH13_STA_0                       MK_ADDR_CONST(0xe0004)
+#define GPCDMA_CHANNEL_CH13_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH13_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH13_STA_0_SCR                   SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH13_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH13_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH13_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH13_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH13_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH13_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH13_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH13_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH13_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH13_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH13_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH13_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH13_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH13_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH13_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH13_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH13_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH13_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH13_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH13_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH13_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH13_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH13_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH13_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH13_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH13_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH13_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH13_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH13_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH13_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH13_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH13_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH13_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH13_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH13_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH13_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH13_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH13_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH13_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH13_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH13_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH13_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH13_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH13_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH13_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH13_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH13_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH13_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH13_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH13_CSRE_0
+#define GPCDMA_CHANNEL_CH13_CSRE_0                      MK_ADDR_CONST(0xe0008)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH13_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH13_CSRE_0_SCR                  SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH13_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH13_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH13_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH13_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH13_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0                   MK_ADDR_CONST(0xe000c)
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_SCR                       SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH13_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH13_DST_PTR_0
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0                   MK_ADDR_CONST(0xe0010)
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_SCR                       SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH13_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0                        MK_ADDR_CONST(0xe0014)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_SCR                    SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH13_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0                    MK_ADDR_CONST(0xe0018)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_SCR                        SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH13_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0                  MK_ADDR_CONST(0xe001c)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_SCR                      SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH13_WCOUNT_0
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0                    MK_ADDR_CONST(0xe0020)
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_SCR                        SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH13_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0                      MK_ADDR_CONST(0xe0024)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_SCR                  SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0                      MK_ADDR_CONST(0xe0028)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_SCR                  SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xe002c
+
+// Register GPCDMA_CHANNEL_CH13_ERR_STA_0
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0                   MK_ADDR_CONST(0xe0030)
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_SCR                       SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH13_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH13_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0                 MK_ADDR_CONST(0xe0034)
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_SCR                     SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH13_0
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH13_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH13_TZ_0
+#define GPCDMA_CHANNEL_CH13_TZ_0                        MK_ADDR_CONST(0xe0038)
+#define GPCDMA_CHANNEL_CH13_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH13_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH13_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH13_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH13_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH13_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH13_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH13_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH13_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH13_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH13_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH13_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH13_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH13_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH13_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH13_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH14_CSR_0
+#define GPCDMA_CHANNEL_CH14_CSR_0                       MK_ADDR_CONST(0xf0000)
+#define GPCDMA_CHANNEL_CH14_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH14_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH14_CSR_0_SCR                   SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH14_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH14_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH14_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH14_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH14_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH14_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH14_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH14_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH14_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH14_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH14_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH14_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH14_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH14_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH14_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH14_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH14_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH14_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH14_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH14_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH14_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH14_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH14_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH14_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH14_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH14_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH14_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH14_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH14_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH14_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH14_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH14_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH14_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH14_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH14_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH14_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH14_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH14_STA_0
+#define GPCDMA_CHANNEL_CH14_STA_0                       MK_ADDR_CONST(0xf0004)
+#define GPCDMA_CHANNEL_CH14_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH14_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH14_STA_0_SCR                   SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH14_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH14_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH14_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH14_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH14_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH14_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH14_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH14_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH14_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH14_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH14_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH14_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH14_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH14_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH14_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH14_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH14_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH14_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH14_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH14_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH14_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH14_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH14_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH14_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH14_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH14_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH14_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH14_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH14_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH14_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH14_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH14_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH14_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH14_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH14_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH14_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH14_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH14_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH14_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH14_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH14_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH14_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH14_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH14_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH14_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH14_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH14_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH14_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH14_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH14_CSRE_0
+#define GPCDMA_CHANNEL_CH14_CSRE_0                      MK_ADDR_CONST(0xf0008)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH14_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH14_CSRE_0_SCR                  SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH14_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH14_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH14_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH14_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH14_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0                   MK_ADDR_CONST(0xf000c)
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_SCR                       SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH14_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH14_DST_PTR_0
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0                   MK_ADDR_CONST(0xf0010)
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_SCR                       SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH14_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0                        MK_ADDR_CONST(0xf0014)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_SCR                    SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH14_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0                    MK_ADDR_CONST(0xf0018)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_SCR                        SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH14_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0                  MK_ADDR_CONST(0xf001c)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_SCR                      SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH14_WCOUNT_0
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0                    MK_ADDR_CONST(0xf0020)
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_SCR                        SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH14_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0                      MK_ADDR_CONST(0xf0024)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_SCR                  SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0                      MK_ADDR_CONST(0xf0028)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_SCR                  SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xf002c
+
+// Register GPCDMA_CHANNEL_CH14_ERR_STA_0
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0                   MK_ADDR_CONST(0xf0030)
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_SCR                       SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH14_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH14_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0                 MK_ADDR_CONST(0xf0034)
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_SCR                     SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH14_0
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH14_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH14_TZ_0
+#define GPCDMA_CHANNEL_CH14_TZ_0                        MK_ADDR_CONST(0xf0038)
+#define GPCDMA_CHANNEL_CH14_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH14_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH14_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH14_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH14_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH14_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH14_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH14_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH14_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH14_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH14_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH14_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH14_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH14_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH14_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH14_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH15_CSR_0
+#define GPCDMA_CHANNEL_CH15_CSR_0                       MK_ADDR_CONST(0x100000)
+#define GPCDMA_CHANNEL_CH15_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH15_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH15_CSR_0_SCR                   SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH15_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH15_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH15_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH15_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH15_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH15_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH15_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH15_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH15_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH15_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH15_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH15_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH15_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH15_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH15_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH15_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH15_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH15_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH15_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH15_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH15_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH15_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH15_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH15_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH15_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH15_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH15_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH15_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH15_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH15_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH15_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH15_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH15_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH15_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH15_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH15_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH15_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH15_STA_0
+#define GPCDMA_CHANNEL_CH15_STA_0                       MK_ADDR_CONST(0x100004)
+#define GPCDMA_CHANNEL_CH15_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH15_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH15_STA_0_SCR                   SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH15_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH15_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH15_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH15_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH15_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH15_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH15_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH15_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH15_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH15_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH15_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH15_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH15_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH15_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH15_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH15_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH15_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH15_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH15_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH15_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH15_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH15_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH15_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH15_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH15_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH15_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH15_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH15_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH15_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH15_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH15_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH15_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH15_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH15_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH15_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH15_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH15_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH15_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH15_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH15_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH15_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH15_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH15_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH15_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH15_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH15_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH15_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH15_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH15_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH15_CSRE_0
+#define GPCDMA_CHANNEL_CH15_CSRE_0                      MK_ADDR_CONST(0x100008)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH15_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH15_CSRE_0_SCR                  SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH15_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH15_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH15_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH15_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH15_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0                   MK_ADDR_CONST(0x10000c)
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_SCR                       SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH15_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH15_DST_PTR_0
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0                   MK_ADDR_CONST(0x100010)
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_SCR                       SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH15_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0                        MK_ADDR_CONST(0x100014)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_SCR                    SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH15_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0                    MK_ADDR_CONST(0x100018)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_SCR                        SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH15_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0                  MK_ADDR_CONST(0x10001c)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_SCR                      SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH15_WCOUNT_0
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0                    MK_ADDR_CONST(0x100020)
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_SCR                        SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH15_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x100024)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_SCR                  SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0                      MK_ADDR_CONST(0x100028)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_SCR                  SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x10002c
+
+// Register GPCDMA_CHANNEL_CH15_ERR_STA_0
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0                   MK_ADDR_CONST(0x100030)
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_SCR                       SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH15_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH15_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0                 MK_ADDR_CONST(0x100034)
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_SCR                     SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH15_0
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH15_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH15_TZ_0
+#define GPCDMA_CHANNEL_CH15_TZ_0                        MK_ADDR_CONST(0x100038)
+#define GPCDMA_CHANNEL_CH15_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH15_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH15_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH15_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH15_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH15_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH15_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH15_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH15_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH15_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH15_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH15_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH15_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH15_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH15_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH15_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH16_CSR_0
+#define GPCDMA_CHANNEL_CH16_CSR_0                       MK_ADDR_CONST(0x110000)
+#define GPCDMA_CHANNEL_CH16_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH16_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH16_CSR_0_SCR                   SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH16_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH16_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH16_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH16_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH16_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH16_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH16_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH16_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH16_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH16_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH16_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH16_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH16_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH16_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH16_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH16_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH16_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH16_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH16_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH16_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH16_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH16_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH16_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH16_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH16_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH16_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH16_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH16_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH16_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH16_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH16_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH16_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH16_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH16_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH16_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH16_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH16_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH16_STA_0
+#define GPCDMA_CHANNEL_CH16_STA_0                       MK_ADDR_CONST(0x110004)
+#define GPCDMA_CHANNEL_CH16_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH16_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH16_STA_0_SCR                   SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH16_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH16_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH16_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH16_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH16_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH16_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH16_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH16_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH16_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH16_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH16_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH16_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH16_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH16_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH16_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH16_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH16_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH16_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH16_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH16_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH16_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH16_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH16_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH16_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH16_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH16_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH16_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH16_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH16_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH16_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH16_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH16_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH16_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH16_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH16_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH16_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH16_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH16_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH16_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH16_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH16_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH16_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH16_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH16_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH16_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH16_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH16_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH16_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH16_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH16_CSRE_0
+#define GPCDMA_CHANNEL_CH16_CSRE_0                      MK_ADDR_CONST(0x110008)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH16_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH16_CSRE_0_SCR                  SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH16_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH16_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH16_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH16_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH16_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0                   MK_ADDR_CONST(0x11000c)
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_SCR                       SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH16_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH16_DST_PTR_0
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0                   MK_ADDR_CONST(0x110010)
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_SCR                       SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH16_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0                        MK_ADDR_CONST(0x110014)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_SCR                    SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH16_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0                    MK_ADDR_CONST(0x110018)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_SCR                        SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH16_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0                  MK_ADDR_CONST(0x11001c)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_SCR                      SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH16_WCOUNT_0
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0                    MK_ADDR_CONST(0x110020)
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_SCR                        SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH16_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x110024)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_SCR                  SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0                      MK_ADDR_CONST(0x110028)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_SCR                  SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x11002c
+
+// Register GPCDMA_CHANNEL_CH16_ERR_STA_0
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0                   MK_ADDR_CONST(0x110030)
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_SCR                       SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH16_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH16_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0                 MK_ADDR_CONST(0x110034)
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_SCR                     SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH16_0
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH16_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH16_TZ_0
+#define GPCDMA_CHANNEL_CH16_TZ_0                        MK_ADDR_CONST(0x110038)
+#define GPCDMA_CHANNEL_CH16_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH16_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH16_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH16_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH16_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH16_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH16_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH16_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH16_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH16_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH16_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH16_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH16_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH16_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH16_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH16_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH17_CSR_0
+#define GPCDMA_CHANNEL_CH17_CSR_0                       MK_ADDR_CONST(0x120000)
+#define GPCDMA_CHANNEL_CH17_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH17_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH17_CSR_0_SCR                   SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH17_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH17_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH17_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH17_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH17_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH17_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH17_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH17_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH17_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH17_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH17_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH17_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH17_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH17_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH17_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH17_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH17_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH17_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH17_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH17_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH17_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH17_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH17_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH17_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH17_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH17_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH17_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH17_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH17_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH17_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH17_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH17_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH17_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH17_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH17_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH17_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH17_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH17_STA_0
+#define GPCDMA_CHANNEL_CH17_STA_0                       MK_ADDR_CONST(0x120004)
+#define GPCDMA_CHANNEL_CH17_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH17_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH17_STA_0_SCR                   SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH17_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH17_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH17_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH17_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH17_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH17_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH17_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH17_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH17_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH17_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH17_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH17_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH17_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH17_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH17_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH17_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH17_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH17_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH17_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH17_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH17_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH17_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH17_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH17_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH17_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH17_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH17_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH17_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH17_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH17_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH17_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH17_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH17_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH17_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH17_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH17_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH17_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH17_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH17_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH17_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH17_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH17_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH17_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH17_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH17_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH17_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH17_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH17_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH17_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH17_CSRE_0
+#define GPCDMA_CHANNEL_CH17_CSRE_0                      MK_ADDR_CONST(0x120008)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH17_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH17_CSRE_0_SCR                  SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH17_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH17_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH17_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH17_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH17_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0                   MK_ADDR_CONST(0x12000c)
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_SCR                       SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH17_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH17_DST_PTR_0
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0                   MK_ADDR_CONST(0x120010)
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_SCR                       SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH17_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0                        MK_ADDR_CONST(0x120014)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_SCR                    SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH17_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0                    MK_ADDR_CONST(0x120018)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_SCR                        SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH17_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0                  MK_ADDR_CONST(0x12001c)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_SCR                      SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH17_WCOUNT_0
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0                    MK_ADDR_CONST(0x120020)
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_SCR                        SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH17_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x120024)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_SCR                  SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0                      MK_ADDR_CONST(0x120028)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_SCR                  SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x12002c
+
+// Register GPCDMA_CHANNEL_CH17_ERR_STA_0
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0                   MK_ADDR_CONST(0x120030)
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_SCR                       SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH17_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH17_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0                 MK_ADDR_CONST(0x120034)
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_SCR                     SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH17_0
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH17_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH17_TZ_0
+#define GPCDMA_CHANNEL_CH17_TZ_0                        MK_ADDR_CONST(0x120038)
+#define GPCDMA_CHANNEL_CH17_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH17_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH17_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH17_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH17_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH17_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH17_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH17_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH17_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH17_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH17_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH17_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH17_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH17_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH17_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH17_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH18_CSR_0
+#define GPCDMA_CHANNEL_CH18_CSR_0                       MK_ADDR_CONST(0x130000)
+#define GPCDMA_CHANNEL_CH18_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH18_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH18_CSR_0_SCR                   SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH18_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH18_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH18_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH18_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH18_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH18_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH18_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH18_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH18_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH18_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH18_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH18_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH18_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH18_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH18_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH18_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH18_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH18_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH18_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH18_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH18_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH18_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH18_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH18_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH18_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH18_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH18_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH18_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH18_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH18_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH18_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH18_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH18_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH18_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH18_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH18_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH18_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH18_STA_0
+#define GPCDMA_CHANNEL_CH18_STA_0                       MK_ADDR_CONST(0x130004)
+#define GPCDMA_CHANNEL_CH18_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH18_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH18_STA_0_SCR                   SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH18_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH18_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH18_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH18_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH18_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH18_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH18_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH18_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH18_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH18_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH18_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH18_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH18_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH18_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH18_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH18_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH18_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH18_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH18_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH18_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH18_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH18_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH18_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH18_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH18_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH18_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH18_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH18_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH18_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH18_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH18_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH18_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH18_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH18_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH18_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH18_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH18_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH18_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH18_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH18_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH18_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH18_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH18_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH18_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH18_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH18_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH18_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH18_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH18_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH18_CSRE_0
+#define GPCDMA_CHANNEL_CH18_CSRE_0                      MK_ADDR_CONST(0x130008)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH18_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH18_CSRE_0_SCR                  SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH18_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH18_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH18_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH18_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH18_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0                   MK_ADDR_CONST(0x13000c)
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_SCR                       SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH18_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH18_DST_PTR_0
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0                   MK_ADDR_CONST(0x130010)
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_SCR                       SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH18_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0                        MK_ADDR_CONST(0x130014)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_SCR                    SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH18_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0                    MK_ADDR_CONST(0x130018)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_SCR                        SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH18_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0                  MK_ADDR_CONST(0x13001c)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_SCR                      SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH18_WCOUNT_0
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0                    MK_ADDR_CONST(0x130020)
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_SCR                        SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH18_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x130024)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_SCR                  SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0                      MK_ADDR_CONST(0x130028)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_SCR                  SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x13002c
+
+// Register GPCDMA_CHANNEL_CH18_ERR_STA_0
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0                   MK_ADDR_CONST(0x130030)
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_SCR                       SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH18_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH18_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0                 MK_ADDR_CONST(0x130034)
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_SCR                     SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH18_0
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH18_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH18_TZ_0
+#define GPCDMA_CHANNEL_CH18_TZ_0                        MK_ADDR_CONST(0x130038)
+#define GPCDMA_CHANNEL_CH18_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH18_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH18_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH18_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH18_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH18_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH18_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH18_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH18_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH18_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH18_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH18_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH18_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH18_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH18_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH18_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH19_CSR_0
+#define GPCDMA_CHANNEL_CH19_CSR_0                       MK_ADDR_CONST(0x140000)
+#define GPCDMA_CHANNEL_CH19_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH19_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH19_CSR_0_SCR                   SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH19_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH19_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH19_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH19_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH19_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH19_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH19_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH19_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH19_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH19_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH19_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH19_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH19_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH19_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH19_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH19_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH19_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH19_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH19_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH19_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH19_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH19_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH19_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH19_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH19_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH19_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH19_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH19_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH19_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH19_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH19_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH19_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH19_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH19_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH19_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH19_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH19_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH19_STA_0
+#define GPCDMA_CHANNEL_CH19_STA_0                       MK_ADDR_CONST(0x140004)
+#define GPCDMA_CHANNEL_CH19_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH19_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH19_STA_0_SCR                   SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH19_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH19_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH19_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH19_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH19_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH19_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH19_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH19_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH19_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH19_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH19_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH19_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH19_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH19_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH19_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH19_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH19_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH19_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH19_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH19_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH19_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH19_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH19_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH19_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH19_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH19_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH19_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH19_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH19_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH19_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH19_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH19_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH19_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH19_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH19_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH19_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH19_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH19_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH19_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH19_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH19_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH19_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH19_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH19_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH19_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH19_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH19_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH19_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH19_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH19_CSRE_0
+#define GPCDMA_CHANNEL_CH19_CSRE_0                      MK_ADDR_CONST(0x140008)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH19_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH19_CSRE_0_SCR                  SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH19_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH19_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH19_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH19_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH19_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0                   MK_ADDR_CONST(0x14000c)
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_SCR                       SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH19_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH19_DST_PTR_0
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0                   MK_ADDR_CONST(0x140010)
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_SCR                       SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH19_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0                        MK_ADDR_CONST(0x140014)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_SCR                    SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH19_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0                    MK_ADDR_CONST(0x140018)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_SCR                        SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH19_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0                  MK_ADDR_CONST(0x14001c)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_SCR                      SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH19_WCOUNT_0
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0                    MK_ADDR_CONST(0x140020)
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_SCR                        SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH19_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x140024)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_SCR                  SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0                      MK_ADDR_CONST(0x140028)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_SCR                  SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x14002c
+
+// Register GPCDMA_CHANNEL_CH19_ERR_STA_0
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0                   MK_ADDR_CONST(0x140030)
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_SCR                       SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH19_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH19_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0                 MK_ADDR_CONST(0x140034)
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_SCR                     SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH19_0
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH19_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH19_TZ_0
+#define GPCDMA_CHANNEL_CH19_TZ_0                        MK_ADDR_CONST(0x140038)
+#define GPCDMA_CHANNEL_CH19_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH19_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH19_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH19_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH19_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH19_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH19_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH19_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH19_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH19_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH19_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH19_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH19_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH19_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH19_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH19_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH20_CSR_0
+#define GPCDMA_CHANNEL_CH20_CSR_0                       MK_ADDR_CONST(0x150000)
+#define GPCDMA_CHANNEL_CH20_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH20_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH20_CSR_0_SCR                   SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH20_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH20_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH20_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH20_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH20_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH20_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH20_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH20_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH20_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH20_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH20_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH20_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH20_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH20_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH20_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH20_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH20_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH20_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH20_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH20_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH20_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH20_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH20_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH20_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH20_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH20_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH20_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH20_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH20_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH20_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH20_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH20_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH20_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH20_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH20_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH20_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH20_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH20_STA_0
+#define GPCDMA_CHANNEL_CH20_STA_0                       MK_ADDR_CONST(0x150004)
+#define GPCDMA_CHANNEL_CH20_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH20_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH20_STA_0_SCR                   SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH20_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH20_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH20_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH20_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH20_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH20_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH20_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH20_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH20_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH20_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH20_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH20_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH20_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH20_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH20_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH20_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH20_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH20_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH20_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH20_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH20_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH20_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH20_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH20_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH20_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH20_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH20_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH20_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH20_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH20_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH20_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH20_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH20_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH20_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH20_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH20_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH20_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH20_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH20_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH20_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH20_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH20_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH20_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH20_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH20_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH20_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH20_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH20_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH20_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH20_CSRE_0
+#define GPCDMA_CHANNEL_CH20_CSRE_0                      MK_ADDR_CONST(0x150008)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH20_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH20_CSRE_0_SCR                  SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH20_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH20_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH20_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH20_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH20_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0                   MK_ADDR_CONST(0x15000c)
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_SCR                       SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH20_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH20_DST_PTR_0
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0                   MK_ADDR_CONST(0x150010)
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_SCR                       SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH20_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0                        MK_ADDR_CONST(0x150014)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_SCR                    SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH20_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0                    MK_ADDR_CONST(0x150018)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_SCR                        SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH20_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0                  MK_ADDR_CONST(0x15001c)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_SCR                      SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH20_WCOUNT_0
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0                    MK_ADDR_CONST(0x150020)
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_SCR                        SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH20_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x150024)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_SCR                  SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0                      MK_ADDR_CONST(0x150028)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_SCR                  SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x15002c
+
+// Register GPCDMA_CHANNEL_CH20_ERR_STA_0
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0                   MK_ADDR_CONST(0x150030)
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_SCR                       SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH20_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH20_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0                 MK_ADDR_CONST(0x150034)
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_SCR                     SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH20_0
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH20_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH20_TZ_0
+#define GPCDMA_CHANNEL_CH20_TZ_0                        MK_ADDR_CONST(0x150038)
+#define GPCDMA_CHANNEL_CH20_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH20_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH20_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH20_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH20_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH20_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH20_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH20_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH20_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH20_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH20_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH20_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH20_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH20_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH20_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH20_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH21_CSR_0
+#define GPCDMA_CHANNEL_CH21_CSR_0                       MK_ADDR_CONST(0x160000)
+#define GPCDMA_CHANNEL_CH21_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH21_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH21_CSR_0_SCR                   SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH21_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH21_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH21_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH21_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH21_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH21_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH21_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH21_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH21_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH21_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH21_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH21_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH21_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH21_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH21_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH21_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH21_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH21_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH21_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH21_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH21_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH21_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH21_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH21_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH21_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH21_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH21_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH21_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH21_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH21_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH21_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH21_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH21_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH21_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH21_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH21_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH21_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH21_STA_0
+#define GPCDMA_CHANNEL_CH21_STA_0                       MK_ADDR_CONST(0x160004)
+#define GPCDMA_CHANNEL_CH21_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH21_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH21_STA_0_SCR                   SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH21_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH21_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH21_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH21_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH21_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH21_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH21_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH21_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH21_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH21_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH21_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH21_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH21_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH21_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH21_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH21_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH21_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH21_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH21_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH21_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH21_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH21_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH21_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH21_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH21_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH21_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH21_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH21_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH21_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH21_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH21_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH21_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH21_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH21_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH21_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH21_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH21_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH21_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH21_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH21_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH21_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH21_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH21_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH21_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH21_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH21_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH21_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH21_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH21_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH21_CSRE_0
+#define GPCDMA_CHANNEL_CH21_CSRE_0                      MK_ADDR_CONST(0x160008)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH21_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH21_CSRE_0_SCR                  SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH21_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH21_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH21_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH21_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH21_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0                   MK_ADDR_CONST(0x16000c)
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_SCR                       SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH21_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH21_DST_PTR_0
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0                   MK_ADDR_CONST(0x160010)
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_SCR                       SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH21_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0                        MK_ADDR_CONST(0x160014)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_SCR                    SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH21_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0                    MK_ADDR_CONST(0x160018)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_SCR                        SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH21_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0                  MK_ADDR_CONST(0x16001c)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_SCR                      SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH21_WCOUNT_0
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0                    MK_ADDR_CONST(0x160020)
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_SCR                        SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH21_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x160024)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_SCR                  SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0                      MK_ADDR_CONST(0x160028)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_SCR                  SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x16002c
+
+// Register GPCDMA_CHANNEL_CH21_ERR_STA_0
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0                   MK_ADDR_CONST(0x160030)
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_SCR                       SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH21_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH21_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0                 MK_ADDR_CONST(0x160034)
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_SCR                     SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH21_0
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH21_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH21_TZ_0
+#define GPCDMA_CHANNEL_CH21_TZ_0                        MK_ADDR_CONST(0x160038)
+#define GPCDMA_CHANNEL_CH21_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH21_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH21_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH21_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH21_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH21_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH21_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH21_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH21_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH21_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH21_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH21_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH21_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH21_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH21_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH21_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH22_CSR_0
+#define GPCDMA_CHANNEL_CH22_CSR_0                       MK_ADDR_CONST(0x170000)
+#define GPCDMA_CHANNEL_CH22_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH22_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH22_CSR_0_SCR                   SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH22_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH22_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH22_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH22_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH22_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH22_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH22_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH22_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH22_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH22_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH22_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH22_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH22_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH22_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH22_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH22_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH22_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH22_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH22_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH22_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH22_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH22_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH22_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH22_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH22_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH22_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH22_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH22_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH22_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH22_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH22_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH22_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH22_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH22_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH22_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH22_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH22_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH22_STA_0
+#define GPCDMA_CHANNEL_CH22_STA_0                       MK_ADDR_CONST(0x170004)
+#define GPCDMA_CHANNEL_CH22_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH22_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH22_STA_0_SCR                   SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH22_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH22_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH22_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH22_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH22_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH22_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH22_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH22_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH22_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH22_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH22_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH22_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH22_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH22_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH22_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH22_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH22_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH22_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH22_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH22_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH22_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH22_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH22_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH22_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH22_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH22_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH22_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH22_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH22_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH22_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH22_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH22_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH22_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH22_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH22_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH22_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH22_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH22_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH22_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH22_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH22_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH22_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH22_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH22_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH22_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH22_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH22_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH22_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH22_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH22_CSRE_0
+#define GPCDMA_CHANNEL_CH22_CSRE_0                      MK_ADDR_CONST(0x170008)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH22_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH22_CSRE_0_SCR                  SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH22_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH22_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH22_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH22_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH22_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0                   MK_ADDR_CONST(0x17000c)
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_SCR                       SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH22_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH22_DST_PTR_0
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0                   MK_ADDR_CONST(0x170010)
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_SCR                       SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH22_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0                        MK_ADDR_CONST(0x170014)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_SCR                    SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH22_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0                    MK_ADDR_CONST(0x170018)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_SCR                        SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH22_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0                  MK_ADDR_CONST(0x17001c)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_SCR                      SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH22_WCOUNT_0
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0                    MK_ADDR_CONST(0x170020)
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_SCR                        SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH22_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x170024)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_SCR                  SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0                      MK_ADDR_CONST(0x170028)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_SCR                  SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x17002c
+
+// Register GPCDMA_CHANNEL_CH22_ERR_STA_0
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0                   MK_ADDR_CONST(0x170030)
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_SCR                       SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH22_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH22_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0                 MK_ADDR_CONST(0x170034)
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_SCR                     SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH22_0
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH22_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH22_TZ_0
+#define GPCDMA_CHANNEL_CH22_TZ_0                        MK_ADDR_CONST(0x170038)
+#define GPCDMA_CHANNEL_CH22_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH22_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH22_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH22_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH22_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH22_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH22_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH22_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH22_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH22_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH22_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH22_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH22_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH22_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH22_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH22_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH23_CSR_0
+#define GPCDMA_CHANNEL_CH23_CSR_0                       MK_ADDR_CONST(0x180000)
+#define GPCDMA_CHANNEL_CH23_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH23_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH23_CSR_0_SCR                   SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH23_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH23_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH23_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH23_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH23_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH23_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH23_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH23_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH23_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH23_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH23_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH23_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH23_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH23_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH23_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH23_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH23_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH23_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH23_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH23_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH23_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH23_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH23_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH23_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH23_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH23_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH23_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH23_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH23_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH23_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH23_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH23_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH23_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH23_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH23_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH23_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH23_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH23_STA_0
+#define GPCDMA_CHANNEL_CH23_STA_0                       MK_ADDR_CONST(0x180004)
+#define GPCDMA_CHANNEL_CH23_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH23_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH23_STA_0_SCR                   SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH23_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH23_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH23_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH23_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH23_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH23_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH23_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH23_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH23_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH23_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH23_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH23_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH23_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH23_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH23_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH23_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH23_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH23_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH23_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH23_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH23_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH23_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH23_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH23_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH23_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH23_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH23_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH23_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH23_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH23_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH23_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH23_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH23_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH23_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH23_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH23_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH23_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH23_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH23_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH23_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH23_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH23_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH23_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH23_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH23_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH23_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH23_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH23_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH23_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH23_CSRE_0
+#define GPCDMA_CHANNEL_CH23_CSRE_0                      MK_ADDR_CONST(0x180008)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH23_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH23_CSRE_0_SCR                  SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH23_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH23_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH23_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH23_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH23_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0                   MK_ADDR_CONST(0x18000c)
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_SCR                       SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH23_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH23_DST_PTR_0
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0                   MK_ADDR_CONST(0x180010)
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_SCR                       SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH23_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0                        MK_ADDR_CONST(0x180014)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_SCR                    SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH23_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0                    MK_ADDR_CONST(0x180018)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_SCR                        SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH23_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0                  MK_ADDR_CONST(0x18001c)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_SCR                      SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH23_WCOUNT_0
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0                    MK_ADDR_CONST(0x180020)
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_SCR                        SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH23_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x180024)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_SCR                  SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0                      MK_ADDR_CONST(0x180028)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_SCR                  SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x18002c
+
+// Register GPCDMA_CHANNEL_CH23_ERR_STA_0
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0                   MK_ADDR_CONST(0x180030)
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_SCR                       SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH23_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH23_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0                 MK_ADDR_CONST(0x180034)
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_SCR                     SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH23_0
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH23_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH23_TZ_0
+#define GPCDMA_CHANNEL_CH23_TZ_0                        MK_ADDR_CONST(0x180038)
+#define GPCDMA_CHANNEL_CH23_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH23_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH23_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH23_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH23_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH23_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH23_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH23_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH23_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH23_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH23_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH23_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH23_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH23_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH23_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH23_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH24_CSR_0
+#define GPCDMA_CHANNEL_CH24_CSR_0                       MK_ADDR_CONST(0x190000)
+#define GPCDMA_CHANNEL_CH24_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH24_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH24_CSR_0_SCR                   SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH24_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH24_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH24_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH24_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH24_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH24_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH24_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH24_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH24_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH24_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH24_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH24_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH24_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH24_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH24_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH24_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH24_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH24_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH24_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH24_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH24_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH24_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH24_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH24_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH24_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH24_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH24_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH24_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH24_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH24_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH24_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH24_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH24_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH24_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH24_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH24_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH24_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH24_STA_0
+#define GPCDMA_CHANNEL_CH24_STA_0                       MK_ADDR_CONST(0x190004)
+#define GPCDMA_CHANNEL_CH24_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH24_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH24_STA_0_SCR                   SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH24_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH24_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH24_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH24_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH24_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH24_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH24_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH24_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH24_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH24_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH24_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH24_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH24_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH24_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH24_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH24_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH24_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH24_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH24_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH24_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH24_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH24_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH24_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH24_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH24_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH24_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH24_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH24_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH24_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH24_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH24_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH24_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH24_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH24_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH24_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH24_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH24_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH24_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH24_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH24_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH24_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH24_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH24_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH24_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH24_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH24_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH24_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH24_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH24_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH24_CSRE_0
+#define GPCDMA_CHANNEL_CH24_CSRE_0                      MK_ADDR_CONST(0x190008)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH24_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH24_CSRE_0_SCR                  SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH24_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH24_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH24_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH24_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH24_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0                   MK_ADDR_CONST(0x19000c)
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_SCR                       SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH24_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH24_DST_PTR_0
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0                   MK_ADDR_CONST(0x190010)
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_SCR                       SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH24_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0                        MK_ADDR_CONST(0x190014)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_SCR                    SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH24_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0                    MK_ADDR_CONST(0x190018)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_SCR                        SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH24_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0                  MK_ADDR_CONST(0x19001c)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_SCR                      SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH24_WCOUNT_0
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0                    MK_ADDR_CONST(0x190020)
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_SCR                        SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH24_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x190024)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_SCR                  SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0                      MK_ADDR_CONST(0x190028)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_SCR                  SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x19002c
+
+// Register GPCDMA_CHANNEL_CH24_ERR_STA_0
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0                   MK_ADDR_CONST(0x190030)
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_SCR                       SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH24_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH24_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0                 MK_ADDR_CONST(0x190034)
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_SCR                     SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH24_0
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH24_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH24_TZ_0
+#define GPCDMA_CHANNEL_CH24_TZ_0                        MK_ADDR_CONST(0x190038)
+#define GPCDMA_CHANNEL_CH24_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH24_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH24_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH24_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH24_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH24_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH24_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH24_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH24_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH24_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH24_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH24_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH24_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH24_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH24_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH24_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH25_CSR_0
+#define GPCDMA_CHANNEL_CH25_CSR_0                       MK_ADDR_CONST(0x1a0000)
+#define GPCDMA_CHANNEL_CH25_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH25_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH25_CSR_0_SCR                   SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH25_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH25_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH25_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH25_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH25_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH25_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH25_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH25_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH25_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH25_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH25_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH25_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH25_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH25_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH25_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH25_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH25_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH25_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH25_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH25_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH25_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH25_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH25_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH25_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH25_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH25_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH25_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH25_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH25_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH25_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH25_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH25_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH25_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH25_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH25_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH25_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH25_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH25_STA_0
+#define GPCDMA_CHANNEL_CH25_STA_0                       MK_ADDR_CONST(0x1a0004)
+#define GPCDMA_CHANNEL_CH25_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH25_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH25_STA_0_SCR                   SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH25_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH25_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH25_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH25_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH25_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH25_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH25_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH25_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH25_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH25_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH25_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH25_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH25_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH25_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH25_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH25_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH25_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH25_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH25_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH25_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH25_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH25_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH25_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH25_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH25_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH25_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH25_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH25_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH25_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH25_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH25_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH25_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH25_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH25_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH25_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH25_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH25_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH25_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH25_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH25_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH25_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH25_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH25_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH25_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH25_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH25_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH25_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH25_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH25_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH25_CSRE_0
+#define GPCDMA_CHANNEL_CH25_CSRE_0                      MK_ADDR_CONST(0x1a0008)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH25_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH25_CSRE_0_SCR                  SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH25_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH25_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH25_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH25_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH25_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0                   MK_ADDR_CONST(0x1a000c)
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_SCR                       SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH25_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH25_DST_PTR_0
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0                   MK_ADDR_CONST(0x1a0010)
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_SCR                       SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH25_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0                        MK_ADDR_CONST(0x1a0014)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_SCR                    SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH25_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0                    MK_ADDR_CONST(0x1a0018)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_SCR                        SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH25_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0                  MK_ADDR_CONST(0x1a001c)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_SCR                      SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH25_WCOUNT_0
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0                    MK_ADDR_CONST(0x1a0020)
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_SCR                        SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH25_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x1a0024)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_SCR                  SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0                      MK_ADDR_CONST(0x1a0028)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_SCR                  SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x1a002c
+
+// Register GPCDMA_CHANNEL_CH25_ERR_STA_0
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0                   MK_ADDR_CONST(0x1a0030)
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_SCR                       SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH25_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH25_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0                 MK_ADDR_CONST(0x1a0034)
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_SCR                     SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH25_0
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH25_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH25_TZ_0
+#define GPCDMA_CHANNEL_CH25_TZ_0                        MK_ADDR_CONST(0x1a0038)
+#define GPCDMA_CHANNEL_CH25_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH25_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH25_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH25_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH25_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH25_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH25_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH25_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH25_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH25_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH25_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH25_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH25_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH25_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH25_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH25_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH26_CSR_0
+#define GPCDMA_CHANNEL_CH26_CSR_0                       MK_ADDR_CONST(0x1b0000)
+#define GPCDMA_CHANNEL_CH26_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH26_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH26_CSR_0_SCR                   SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH26_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH26_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH26_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH26_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH26_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH26_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH26_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH26_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH26_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH26_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH26_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH26_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH26_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH26_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH26_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH26_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH26_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH26_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH26_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH26_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH26_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH26_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH26_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH26_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH26_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH26_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH26_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH26_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH26_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH26_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH26_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH26_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH26_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH26_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH26_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH26_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH26_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH26_STA_0
+#define GPCDMA_CHANNEL_CH26_STA_0                       MK_ADDR_CONST(0x1b0004)
+#define GPCDMA_CHANNEL_CH26_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH26_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH26_STA_0_SCR                   SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH26_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH26_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH26_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH26_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH26_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH26_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH26_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH26_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH26_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH26_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH26_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH26_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH26_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH26_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH26_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH26_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH26_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH26_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH26_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH26_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH26_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH26_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH26_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH26_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH26_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH26_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH26_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH26_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH26_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH26_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH26_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH26_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH26_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH26_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH26_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH26_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH26_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH26_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH26_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH26_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH26_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH26_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH26_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH26_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH26_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH26_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH26_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH26_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH26_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH26_CSRE_0
+#define GPCDMA_CHANNEL_CH26_CSRE_0                      MK_ADDR_CONST(0x1b0008)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH26_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH26_CSRE_0_SCR                  SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH26_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH26_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH26_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH26_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH26_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0                   MK_ADDR_CONST(0x1b000c)
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_SCR                       SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH26_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH26_DST_PTR_0
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0                   MK_ADDR_CONST(0x1b0010)
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_SCR                       SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH26_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0                        MK_ADDR_CONST(0x1b0014)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_SCR                    SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH26_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0                    MK_ADDR_CONST(0x1b0018)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_SCR                        SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH26_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0                  MK_ADDR_CONST(0x1b001c)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_SCR                      SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH26_WCOUNT_0
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0                    MK_ADDR_CONST(0x1b0020)
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_SCR                        SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH26_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x1b0024)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_SCR                  SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0                      MK_ADDR_CONST(0x1b0028)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_SCR                  SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x1b002c
+
+// Register GPCDMA_CHANNEL_CH26_ERR_STA_0
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0                   MK_ADDR_CONST(0x1b0030)
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_SCR                       SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH26_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH26_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0                 MK_ADDR_CONST(0x1b0034)
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_SCR                     SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH26_0
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH26_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH26_TZ_0
+#define GPCDMA_CHANNEL_CH26_TZ_0                        MK_ADDR_CONST(0x1b0038)
+#define GPCDMA_CHANNEL_CH26_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH26_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH26_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH26_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH26_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH26_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH26_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH26_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH26_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH26_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH26_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH26_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH26_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH26_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH26_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH26_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH27_CSR_0
+#define GPCDMA_CHANNEL_CH27_CSR_0                       MK_ADDR_CONST(0x1c0000)
+#define GPCDMA_CHANNEL_CH27_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH27_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH27_CSR_0_SCR                   SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH27_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH27_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH27_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH27_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH27_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH27_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH27_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH27_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH27_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH27_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH27_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH27_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH27_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH27_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH27_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH27_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH27_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH27_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH27_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH27_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH27_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH27_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH27_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH27_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH27_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH27_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH27_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH27_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH27_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH27_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH27_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH27_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH27_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH27_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH27_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH27_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH27_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH27_STA_0
+#define GPCDMA_CHANNEL_CH27_STA_0                       MK_ADDR_CONST(0x1c0004)
+#define GPCDMA_CHANNEL_CH27_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH27_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH27_STA_0_SCR                   SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH27_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH27_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH27_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH27_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH27_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH27_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH27_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH27_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH27_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH27_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH27_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH27_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH27_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH27_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH27_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH27_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH27_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH27_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH27_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH27_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH27_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH27_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH27_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH27_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH27_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH27_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH27_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH27_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH27_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH27_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH27_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH27_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH27_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH27_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH27_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH27_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH27_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH27_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH27_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH27_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH27_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH27_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH27_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH27_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH27_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH27_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH27_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH27_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH27_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH27_CSRE_0
+#define GPCDMA_CHANNEL_CH27_CSRE_0                      MK_ADDR_CONST(0x1c0008)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH27_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH27_CSRE_0_SCR                  SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH27_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH27_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH27_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH27_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH27_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0                   MK_ADDR_CONST(0x1c000c)
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_SCR                       SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH27_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH27_DST_PTR_0
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0                   MK_ADDR_CONST(0x1c0010)
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_SCR                       SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH27_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0                        MK_ADDR_CONST(0x1c0014)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_SCR                    SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH27_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0                    MK_ADDR_CONST(0x1c0018)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_SCR                        SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH27_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0                  MK_ADDR_CONST(0x1c001c)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_SCR                      SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH27_WCOUNT_0
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0                    MK_ADDR_CONST(0x1c0020)
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_SCR                        SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH27_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x1c0024)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_SCR                  SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0                      MK_ADDR_CONST(0x1c0028)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_SCR                  SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x1c002c
+
+// Register GPCDMA_CHANNEL_CH27_ERR_STA_0
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0                   MK_ADDR_CONST(0x1c0030)
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_SCR                       SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH27_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH27_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0                 MK_ADDR_CONST(0x1c0034)
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_SCR                     SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH27_0
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH27_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH27_TZ_0
+#define GPCDMA_CHANNEL_CH27_TZ_0                        MK_ADDR_CONST(0x1c0038)
+#define GPCDMA_CHANNEL_CH27_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH27_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH27_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH27_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH27_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH27_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH27_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH27_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH27_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH27_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH27_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH27_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH27_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH27_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH27_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH27_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH28_CSR_0
+#define GPCDMA_CHANNEL_CH28_CSR_0                       MK_ADDR_CONST(0x1d0000)
+#define GPCDMA_CHANNEL_CH28_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH28_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH28_CSR_0_SCR                   SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH28_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH28_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH28_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH28_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH28_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH28_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH28_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH28_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH28_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH28_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH28_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH28_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH28_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH28_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH28_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH28_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH28_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH28_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH28_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH28_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH28_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH28_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH28_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH28_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH28_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH28_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH28_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH28_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH28_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH28_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH28_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH28_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH28_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH28_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH28_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH28_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH28_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH28_STA_0
+#define GPCDMA_CHANNEL_CH28_STA_0                       MK_ADDR_CONST(0x1d0004)
+#define GPCDMA_CHANNEL_CH28_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH28_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH28_STA_0_SCR                   SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH28_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH28_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH28_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH28_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH28_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH28_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH28_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH28_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH28_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH28_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH28_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH28_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH28_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH28_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH28_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH28_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH28_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH28_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH28_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH28_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH28_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH28_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH28_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH28_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH28_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH28_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH28_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH28_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH28_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH28_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH28_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH28_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH28_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH28_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH28_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH28_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH28_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH28_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH28_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH28_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH28_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH28_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH28_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH28_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH28_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH28_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH28_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH28_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH28_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH28_CSRE_0
+#define GPCDMA_CHANNEL_CH28_CSRE_0                      MK_ADDR_CONST(0x1d0008)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH28_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH28_CSRE_0_SCR                  SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH28_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH28_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH28_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH28_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH28_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0                   MK_ADDR_CONST(0x1d000c)
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_SCR                       SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH28_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH28_DST_PTR_0
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0                   MK_ADDR_CONST(0x1d0010)
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_SCR                       SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH28_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0                        MK_ADDR_CONST(0x1d0014)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_SCR                    SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH28_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0                    MK_ADDR_CONST(0x1d0018)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_SCR                        SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH28_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0                  MK_ADDR_CONST(0x1d001c)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_SCR                      SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH28_WCOUNT_0
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0                    MK_ADDR_CONST(0x1d0020)
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_SCR                        SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH28_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x1d0024)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_SCR                  SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0                      MK_ADDR_CONST(0x1d0028)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_SCR                  SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x1d002c
+
+// Register GPCDMA_CHANNEL_CH28_ERR_STA_0
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0                   MK_ADDR_CONST(0x1d0030)
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_SCR                       SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH28_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH28_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0                 MK_ADDR_CONST(0x1d0034)
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_SCR                     SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH28_0
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH28_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH28_TZ_0
+#define GPCDMA_CHANNEL_CH28_TZ_0                        MK_ADDR_CONST(0x1d0038)
+#define GPCDMA_CHANNEL_CH28_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH28_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH28_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH28_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH28_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH28_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH28_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH28_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH28_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH28_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH28_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH28_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH28_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH28_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH28_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH28_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH29_CSR_0
+#define GPCDMA_CHANNEL_CH29_CSR_0                       MK_ADDR_CONST(0x1e0000)
+#define GPCDMA_CHANNEL_CH29_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH29_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH29_CSR_0_SCR                   SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH29_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH29_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH29_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH29_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH29_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH29_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH29_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH29_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH29_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH29_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH29_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH29_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH29_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH29_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH29_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH29_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH29_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH29_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH29_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH29_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH29_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH29_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH29_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH29_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH29_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH29_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH29_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH29_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH29_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH29_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH29_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH29_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH29_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH29_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH29_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH29_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH29_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH29_STA_0
+#define GPCDMA_CHANNEL_CH29_STA_0                       MK_ADDR_CONST(0x1e0004)
+#define GPCDMA_CHANNEL_CH29_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH29_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH29_STA_0_SCR                   SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH29_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH29_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH29_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH29_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH29_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH29_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH29_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH29_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH29_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH29_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH29_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH29_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH29_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH29_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH29_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH29_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH29_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH29_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH29_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH29_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH29_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH29_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH29_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH29_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH29_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH29_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH29_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH29_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH29_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH29_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH29_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH29_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH29_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH29_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH29_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH29_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH29_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH29_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH29_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH29_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH29_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH29_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH29_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH29_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH29_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH29_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH29_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH29_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH29_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH29_CSRE_0
+#define GPCDMA_CHANNEL_CH29_CSRE_0                      MK_ADDR_CONST(0x1e0008)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH29_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH29_CSRE_0_SCR                  SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH29_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH29_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH29_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH29_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH29_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0                   MK_ADDR_CONST(0x1e000c)
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_SCR                       SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH29_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH29_DST_PTR_0
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0                   MK_ADDR_CONST(0x1e0010)
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_SCR                       SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH29_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0                        MK_ADDR_CONST(0x1e0014)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_SCR                    SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH29_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0                    MK_ADDR_CONST(0x1e0018)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_SCR                        SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH29_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0                  MK_ADDR_CONST(0x1e001c)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_SCR                      SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH29_WCOUNT_0
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0                    MK_ADDR_CONST(0x1e0020)
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_SCR                        SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH29_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x1e0024)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_SCR                  SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0                      MK_ADDR_CONST(0x1e0028)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_SCR                  SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x1e002c
+
+// Register GPCDMA_CHANNEL_CH29_ERR_STA_0
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0                   MK_ADDR_CONST(0x1e0030)
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_SCR                       SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH29_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH29_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0                 MK_ADDR_CONST(0x1e0034)
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_SCR                     SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH29_0
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH29_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH29_TZ_0
+#define GPCDMA_CHANNEL_CH29_TZ_0                        MK_ADDR_CONST(0x1e0038)
+#define GPCDMA_CHANNEL_CH29_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH29_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH29_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH29_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH29_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH29_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH29_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH29_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH29_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH29_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH29_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH29_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH29_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH29_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH29_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH29_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH30_CSR_0
+#define GPCDMA_CHANNEL_CH30_CSR_0                       MK_ADDR_CONST(0x1f0000)
+#define GPCDMA_CHANNEL_CH30_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH30_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH30_CSR_0_SCR                   SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH30_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH30_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH30_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH30_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH30_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH30_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH30_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH30_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH30_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH30_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH30_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH30_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH30_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH30_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH30_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH30_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH30_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH30_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH30_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH30_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH30_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH30_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH30_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH30_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH30_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH30_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH30_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH30_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH30_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH30_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH30_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH30_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH30_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH30_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH30_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH30_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH30_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH30_STA_0
+#define GPCDMA_CHANNEL_CH30_STA_0                       MK_ADDR_CONST(0x1f0004)
+#define GPCDMA_CHANNEL_CH30_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH30_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH30_STA_0_SCR                   SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH30_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH30_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH30_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH30_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH30_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH30_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH30_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH30_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH30_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH30_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH30_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH30_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH30_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH30_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH30_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH30_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH30_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH30_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH30_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH30_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH30_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH30_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH30_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH30_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH30_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH30_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH30_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH30_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH30_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH30_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH30_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH30_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH30_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH30_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH30_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH30_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH30_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH30_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH30_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH30_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH30_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH30_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH30_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH30_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH30_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH30_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH30_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH30_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH30_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH30_CSRE_0
+#define GPCDMA_CHANNEL_CH30_CSRE_0                      MK_ADDR_CONST(0x1f0008)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH30_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH30_CSRE_0_SCR                  SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH30_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH30_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH30_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH30_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH30_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0                   MK_ADDR_CONST(0x1f000c)
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_SCR                       SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH30_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH30_DST_PTR_0
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0                   MK_ADDR_CONST(0x1f0010)
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_SCR                       SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH30_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0                        MK_ADDR_CONST(0x1f0014)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_SCR                    SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH30_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0                    MK_ADDR_CONST(0x1f0018)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_SCR                        SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH30_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0                  MK_ADDR_CONST(0x1f001c)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_SCR                      SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH30_WCOUNT_0
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0                    MK_ADDR_CONST(0x1f0020)
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_SCR                        SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH30_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x1f0024)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_SCR                  SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0                      MK_ADDR_CONST(0x1f0028)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_SCR                  SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x1f002c
+
+// Register GPCDMA_CHANNEL_CH30_ERR_STA_0
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0                   MK_ADDR_CONST(0x1f0030)
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_SCR                       SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH30_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH30_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0                 MK_ADDR_CONST(0x1f0034)
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_SCR                     SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH30_0
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH30_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH30_TZ_0
+#define GPCDMA_CHANNEL_CH30_TZ_0                        MK_ADDR_CONST(0x1f0038)
+#define GPCDMA_CHANNEL_CH30_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH30_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH30_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH30_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH30_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH30_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH30_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH30_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH30_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH30_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH30_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH30_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH30_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH30_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH30_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH30_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH31_CSR_0
+#define GPCDMA_CHANNEL_CH31_CSR_0                       MK_ADDR_CONST(0x200000)
+#define GPCDMA_CHANNEL_CH31_CSR_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH31_CSR_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH31_CSR_0_SCR                   SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_CSR_0_SCRREG                        GPCDMA_SCR_SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH31_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_CHANNEL_CH31_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH31_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH31_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_CSR_0_ENB_SHIFT)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH31_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH31_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH31_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_CHANNEL_CH31_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH31_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH31_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_CSR_0_ONCE_SHIFT)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH31_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH31_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH31_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH31_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH31_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH31_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_CHANNEL_CH31_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH31_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH31_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH31_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH31_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH31_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH31_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH31_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_16                     MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_17                     MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_18                     MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_19                     MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_20                     MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_21                     MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_22                     MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_23                     MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_24                     MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_25                     MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_26                     MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_27                     MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_28                     MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_29_RSVD                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_30                     MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_CLIENT_31                     MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH31_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_CHANNEL_CH31_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_CHANNEL_CH31_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH31_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH31_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH31_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH31_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_CHANNEL_CH31_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_CHANNEL_CH31_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH31_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_CHANNEL_CH31_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH31_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH31_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH31_STA_0
+#define GPCDMA_CHANNEL_CH31_STA_0                       MK_ADDR_CONST(0x200004)
+#define GPCDMA_CHANNEL_CH31_STA_0_SECURE                        0x0
+#define GPCDMA_CHANNEL_CH31_STA_0_DUAL                  0x0
+#define GPCDMA_CHANNEL_CH31_STA_0_SCR                   SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_STA_0_SCRREG                        GPCDMA_SCR_SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_CHANNEL_CH31_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH31_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_CHANNEL_CH31_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_CHANNEL_CH31_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_STA_0_BSY_SHIFT)
+#define GPCDMA_CHANNEL_CH31_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_CHANNEL_CH31_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH31_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH31_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH31_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_CHANNEL_CH31_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_CHANNEL_CH31_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH31_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH31_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH31_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH31_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH31_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH31_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_CHANNEL_CH31_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH31_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH31_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH31_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH31_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH31_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH31_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_CHANNEL_CH31_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH31_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH31_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH31_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH31_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH31_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH31_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_CHANNEL_CH31_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH31_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH31_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH31_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH31_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH31_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH31_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_CHANNEL_CH31_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH31_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_CHANNEL_CH31_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH31_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH31_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH31_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_CHANNEL_CH31_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_CHANNEL_CH31_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH31_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH31_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH31_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_CHANNEL_CH31_CSRE_0
+#define GPCDMA_CHANNEL_CH31_CSRE_0                      MK_ADDR_CONST(0x200008)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH31_CSRE_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH31_CSRE_0_SCR                  SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_CSRE_0_SCRREG                       GPCDMA_SCR_SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH31_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_CHANNEL_CH31_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH31_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH8                 MK_ENUM_CONST(8)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH9                 MK_ENUM_CONST(9)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH10                        MK_ENUM_CONST(10)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH11                        MK_ENUM_CONST(11)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH12                        MK_ENUM_CONST(12)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH13                        MK_ENUM_CONST(13)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH14                        MK_ENUM_CONST(14)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH15                        MK_ENUM_CONST(15)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH16                        MK_ENUM_CONST(16)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH17                        MK_ENUM_CONST(17)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH18                        MK_ENUM_CONST(18)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH19                        MK_ENUM_CONST(19)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH20                        MK_ENUM_CONST(20)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH21                        MK_ENUM_CONST(21)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH22                        MK_ENUM_CONST(22)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH23                        MK_ENUM_CONST(23)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH24                        MK_ENUM_CONST(24)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH25                        MK_ENUM_CONST(25)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH26                        MK_ENUM_CONST(26)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH27                        MK_ENUM_CONST(27)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH28                        MK_ENUM_CONST(28)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH29                        MK_ENUM_CONST(29)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH30                        MK_ENUM_CONST(30)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_CH31                        MK_ENUM_CONST(31)
+#define GPCDMA_CHANNEL_CH31_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_CHANNEL_CH31_SRC_PTR_0
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0                   MK_ADDR_CONST(0x20000c)
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_SCR                       SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH31_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH31_DST_PTR_0
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0                   MK_ADDR_CONST(0x200010)
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_SCR                       SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_SCRREG                    GPCDMA_SCR_SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH31_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0                        MK_ADDR_CONST(0x200014)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_SCR                    SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_SCRREG                         GPCDMA_SCR_SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH31_MC_SEQ_0
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0                    MK_ADDR_CONST(0x200018)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_SCR                        SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_SCRREG                     GPCDMA_SCR_SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH31_MMIO_SEQ_0
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0                  MK_ADDR_CONST(0x20001c)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_SCR                      SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_SCRREG                   GPCDMA_SCR_SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH31_WCOUNT_0
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0                    MK_ADDR_CONST(0x200020)
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_SCR                        SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_SCRREG                     GPCDMA_SCR_SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH31_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x200024)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_SCR                  SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_SCRREG                       GPCDMA_SCR_SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0                      MK_ADDR_CONST(0x200028)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_SCR                  SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_SCRREG                       GPCDMA_SCR_SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x20002c
+
+// Register GPCDMA_CHANNEL_CH31_ERR_STA_0
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0                   MK_ADDR_CONST(0x200030)
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_SCR                       SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_SCRREG                    GPCDMA_SCR_SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH31_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH31_FIXED_PAT_0
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0                 MK_ADDR_CONST(0x200034)
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_SCR                     SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_SCRREG                  GPCDMA_SCR_SCR_CH31_0
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_CHANNEL_CH31_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_CHANNEL_CH31_TZ_0
+#define GPCDMA_CHANNEL_CH31_TZ_0                        MK_ADDR_CONST(0x200038)
+#define GPCDMA_CHANNEL_CH31_TZ_0_SECURE                         0x0
+#define GPCDMA_CHANNEL_CH31_TZ_0_DUAL                   0x0
+#define GPCDMA_CHANNEL_CH31_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_CHANNEL_CH31_TZ_0_SCRREG                         GPCDMA_SCR_SCR_TZ_0
+#define GPCDMA_CHANNEL_CH31_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_CHANNEL_CH31_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH31_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH31_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH31_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_CHANNEL_CH31_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_CHANNEL_CH31_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_CHANNEL_CH31_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_CHANNEL_CH31_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_CHANNEL_CH31_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_CHANNEL_CH31_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_CHANNEL_CH31_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARGPCDMA_FLV_32CH_REGS(_op_) \
+_op_(GPCDMA_COMMON_DMA_CHAN_STA_0) \
+_op_(GPCDMA_COMMON_REQUESTORS_TX_0) \
+_op_(GPCDMA_COMMON_REQUESTORS_RX_0) \
+_op_(GPCDMA_COMMON_COMMON_ERROR_STA_0) \
+_op_(GPCDMA_COMMON_CHANNEL_ERROR_STA_0) \
+_op_(GPCDMA_COMMON_CHANNEL_TRIG_REG_0) \
+_op_(GPCDMA_COMMON_MASKED_INTR_REG_0) \
+_op_(GPCDMA_COMMON_CHANNEL_INTR_STA_0) \
+_op_(GPCDMA_COMMON_COMMON_INTR_0) \
+_op_(GPCDMA_COMMON_CHANNEL_REG_LOCK_0) \
+_op_(GPCDMA_COMMON_CH0_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH1_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH2_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH3_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH4_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH5_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH6_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH7_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH8_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH9_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH10_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH11_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH12_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH13_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH14_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH15_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH16_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH17_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH18_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH19_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH20_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH21_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH22_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH23_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH24_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH25_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH26_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH27_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH28_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH29_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH30_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_CH31_PERI_ID_MASK_0) \
+_op_(GPCDMA_COMMON_PER0_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER1_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER2_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER3_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER4_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER5_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER6_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER7_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER8_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER9_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER10_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER11_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER12_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER13_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER14_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER15_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER16_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER17_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER18_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER19_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER20_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER21_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER22_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER23_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER24_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER25_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER26_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER27_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER28_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER29_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER30_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_PER31_PERI_ADDR_0) \
+_op_(GPCDMA_COMMON_CH0_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH1_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH2_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH3_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH4_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH5_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH6_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH7_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH8_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH9_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH10_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH11_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH12_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH13_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH14_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH15_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH16_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH17_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH18_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH19_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH20_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH21_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH22_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH23_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH24_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH25_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH26_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH27_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH28_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH29_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH30_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH31_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_COMMON_CH0_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH1_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH2_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH3_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH4_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH5_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH6_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH7_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH8_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH9_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH10_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH11_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH12_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH13_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH14_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH15_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH16_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH17_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH18_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH19_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH20_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH21_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH22_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH23_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH24_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH25_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH26_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH27_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH28_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH29_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH30_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH31_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_COMMON_CH0_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH1_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH2_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH3_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH4_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH5_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH6_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH7_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH8_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH9_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH10_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH11_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH12_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH13_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH14_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH15_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH16_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH17_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH18_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH19_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH20_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH21_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH22_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH23_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH24_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH25_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH26_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH27_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH28_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH29_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH30_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH31_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_COMMON_CH0_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH1_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH2_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH3_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH4_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH5_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH6_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH7_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH8_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH9_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH10_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH11_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH12_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH13_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH14_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH15_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH16_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH17_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH18_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH19_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH20_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH21_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH22_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH23_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH24_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH25_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH26_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH27_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH28_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH29_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH30_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_CH31_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0) \
+_op_(GPCDMA_COMMON_DMA_ICG_EN_OVERRIDE_0) \
+_op_(GPCDMA_COMMON_DMA_ACTIVE_0) \
+_op_(GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0) \
+_op_(GPCDMA_SCR_SCR_CH0_0) \
+_op_(GPCDMA_SCR_SCR_CH1_0) \
+_op_(GPCDMA_SCR_SCR_CH2_0) \
+_op_(GPCDMA_SCR_SCR_CH3_0) \
+_op_(GPCDMA_SCR_SCR_CH4_0) \
+_op_(GPCDMA_SCR_SCR_CH5_0) \
+_op_(GPCDMA_SCR_SCR_CH6_0) \
+_op_(GPCDMA_SCR_SCR_CH7_0) \
+_op_(GPCDMA_SCR_SCR_CH8_0) \
+_op_(GPCDMA_SCR_SCR_CH9_0) \
+_op_(GPCDMA_SCR_SCR_CH10_0) \
+_op_(GPCDMA_SCR_SCR_CH11_0) \
+_op_(GPCDMA_SCR_SCR_CH12_0) \
+_op_(GPCDMA_SCR_SCR_CH13_0) \
+_op_(GPCDMA_SCR_SCR_CH14_0) \
+_op_(GPCDMA_SCR_SCR_CH15_0) \
+_op_(GPCDMA_SCR_SCR_CH16_0) \
+_op_(GPCDMA_SCR_SCR_CH17_0) \
+_op_(GPCDMA_SCR_SCR_CH18_0) \
+_op_(GPCDMA_SCR_SCR_CH19_0) \
+_op_(GPCDMA_SCR_SCR_CH20_0) \
+_op_(GPCDMA_SCR_SCR_CH21_0) \
+_op_(GPCDMA_SCR_SCR_CH22_0) \
+_op_(GPCDMA_SCR_SCR_CH23_0) \
+_op_(GPCDMA_SCR_SCR_CH24_0) \
+_op_(GPCDMA_SCR_SCR_CH25_0) \
+_op_(GPCDMA_SCR_SCR_CH26_0) \
+_op_(GPCDMA_SCR_SCR_CH27_0) \
+_op_(GPCDMA_SCR_SCR_CH28_0) \
+_op_(GPCDMA_SCR_SCR_CH29_0) \
+_op_(GPCDMA_SCR_SCR_CH30_0) \
+_op_(GPCDMA_SCR_SCR_CH31_0) \
+_op_(GPCDMA_SCR_SCR_TZ_0) \
+_op_(GPCDMA_SCR_SCR_DMA_RO_0) \
+_op_(GPCDMA_SCR_SCR_HYPER_0) \
+_op_(GPCDMA_SCR_SCR_SAFETY_0) \
+_op_(GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0) \
+_op_(GPCDMA_ERRCOLLATOR_FEATURE_0) \
+_op_(GPCDMA_ERRCOLLATOR_SWRESET_0) \
+_op_(GPCDMA_ERRCOLLATOR_MISSIONERR_TYPE_0) \
+_op_(GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0) \
+_op_(GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0) \
+_op_(GPCDMA_ERRCOLLATOR_CORRECTABLE_THRESHOLD_0) \
+_op_(GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0) \
+_op_(GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0) \
+_op_(GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_FORCE_0) \
+_op_(GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_STATUS_0) \
+_op_(GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_INJECT_0) \
+_op_(GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_ENABLE_0) \
+_op_(GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_FORCE_0) \
+_op_(GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0) \
+_op_(GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0) \
+_op_(GPCDMA_CHANNEL_CH0_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH0_STA_0) \
+_op_(GPCDMA_CHANNEL_CH0_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH0_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH0_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH0_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH0_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH0_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH0_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH0_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH0_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH0_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH0_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH1_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH1_STA_0) \
+_op_(GPCDMA_CHANNEL_CH1_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH1_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH1_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH1_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH1_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH1_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH1_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH1_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH1_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH1_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH1_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH2_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH2_STA_0) \
+_op_(GPCDMA_CHANNEL_CH2_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH2_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH2_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH2_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH2_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH2_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH2_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH2_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH2_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH2_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH2_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH3_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH3_STA_0) \
+_op_(GPCDMA_CHANNEL_CH3_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH3_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH3_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH3_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH3_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH3_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH3_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH3_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH3_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH3_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH3_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH4_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH4_STA_0) \
+_op_(GPCDMA_CHANNEL_CH4_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH4_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH4_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH4_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH4_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH4_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH4_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH4_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH4_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH4_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH4_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH5_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH5_STA_0) \
+_op_(GPCDMA_CHANNEL_CH5_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH5_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH5_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH5_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH5_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH5_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH5_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH5_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH5_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH5_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH5_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH6_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH6_STA_0) \
+_op_(GPCDMA_CHANNEL_CH6_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH6_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH6_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH6_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH6_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH6_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH6_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH6_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH6_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH6_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH6_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH7_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH7_STA_0) \
+_op_(GPCDMA_CHANNEL_CH7_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH7_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH7_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH7_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH7_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH7_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH7_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH7_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH7_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH7_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH7_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH8_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH8_STA_0) \
+_op_(GPCDMA_CHANNEL_CH8_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH8_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH8_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH8_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH8_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH8_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH8_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH8_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH8_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH8_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH8_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH9_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH9_STA_0) \
+_op_(GPCDMA_CHANNEL_CH9_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH9_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH9_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH9_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH9_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH9_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH9_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH9_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH9_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH9_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH9_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH10_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH10_STA_0) \
+_op_(GPCDMA_CHANNEL_CH10_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH10_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH10_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH10_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH10_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH10_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH10_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH10_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH10_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH10_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH10_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH11_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH11_STA_0) \
+_op_(GPCDMA_CHANNEL_CH11_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH11_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH11_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH11_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH11_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH11_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH11_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH11_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH11_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH11_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH11_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH12_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH12_STA_0) \
+_op_(GPCDMA_CHANNEL_CH12_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH12_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH12_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH12_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH12_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH12_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH12_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH12_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH12_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH12_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH12_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH13_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH13_STA_0) \
+_op_(GPCDMA_CHANNEL_CH13_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH13_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH13_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH13_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH13_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH13_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH13_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH13_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH13_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH13_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH13_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH14_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH14_STA_0) \
+_op_(GPCDMA_CHANNEL_CH14_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH14_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH14_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH14_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH14_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH14_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH14_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH14_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH14_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH14_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH14_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH15_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH15_STA_0) \
+_op_(GPCDMA_CHANNEL_CH15_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH15_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH15_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH15_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH15_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH15_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH15_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH15_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH15_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH15_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH15_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH16_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH16_STA_0) \
+_op_(GPCDMA_CHANNEL_CH16_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH16_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH16_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH16_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH16_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH16_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH16_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH16_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH16_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH16_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH16_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH17_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH17_STA_0) \
+_op_(GPCDMA_CHANNEL_CH17_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH17_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH17_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH17_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH17_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH17_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH17_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH17_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH17_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH17_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH17_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH18_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH18_STA_0) \
+_op_(GPCDMA_CHANNEL_CH18_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH18_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH18_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH18_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH18_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH18_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH18_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH18_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH18_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH18_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH18_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH19_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH19_STA_0) \
+_op_(GPCDMA_CHANNEL_CH19_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH19_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH19_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH19_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH19_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH19_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH19_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH19_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH19_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH19_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH19_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH20_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH20_STA_0) \
+_op_(GPCDMA_CHANNEL_CH20_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH20_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH20_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH20_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH20_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH20_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH20_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH20_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH20_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH20_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH20_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH21_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH21_STA_0) \
+_op_(GPCDMA_CHANNEL_CH21_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH21_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH21_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH21_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH21_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH21_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH21_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH21_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH21_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH21_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH21_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH22_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH22_STA_0) \
+_op_(GPCDMA_CHANNEL_CH22_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH22_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH22_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH22_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH22_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH22_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH22_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH22_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH22_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH22_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH22_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH23_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH23_STA_0) \
+_op_(GPCDMA_CHANNEL_CH23_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH23_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH23_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH23_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH23_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH23_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH23_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH23_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH23_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH23_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH23_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH24_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH24_STA_0) \
+_op_(GPCDMA_CHANNEL_CH24_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH24_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH24_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH24_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH24_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH24_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH24_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH24_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH24_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH24_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH24_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH25_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH25_STA_0) \
+_op_(GPCDMA_CHANNEL_CH25_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH25_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH25_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH25_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH25_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH25_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH25_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH25_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH25_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH25_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH25_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH26_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH26_STA_0) \
+_op_(GPCDMA_CHANNEL_CH26_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH26_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH26_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH26_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH26_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH26_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH26_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH26_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH26_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH26_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH26_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH27_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH27_STA_0) \
+_op_(GPCDMA_CHANNEL_CH27_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH27_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH27_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH27_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH27_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH27_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH27_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH27_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH27_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH27_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH27_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH28_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH28_STA_0) \
+_op_(GPCDMA_CHANNEL_CH28_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH28_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH28_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH28_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH28_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH28_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH28_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH28_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH28_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH28_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH28_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH29_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH29_STA_0) \
+_op_(GPCDMA_CHANNEL_CH29_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH29_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH29_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH29_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH29_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH29_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH29_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH29_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH29_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH29_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH29_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH30_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH30_STA_0) \
+_op_(GPCDMA_CHANNEL_CH30_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH30_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH30_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH30_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH30_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH30_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH30_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH30_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH30_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH30_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH30_TZ_0) \
+_op_(GPCDMA_CHANNEL_CH31_CSR_0) \
+_op_(GPCDMA_CHANNEL_CH31_STA_0) \
+_op_(GPCDMA_CHANNEL_CH31_CSRE_0) \
+_op_(GPCDMA_CHANNEL_CH31_SRC_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH31_DST_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH31_HI_ADR_PTR_0) \
+_op_(GPCDMA_CHANNEL_CH31_MC_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH31_MMIO_SEQ_0) \
+_op_(GPCDMA_CHANNEL_CH31_WCOUNT_0) \
+_op_(GPCDMA_CHANNEL_CH31_DMA_WORD_TRA_0) \
+_op_(GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0) \
+_op_(GPCDMA_CHANNEL_CH31_ERR_STA_0) \
+_op_(GPCDMA_CHANNEL_CH31_FIXED_PAT_0) \
+_op_(GPCDMA_CHANNEL_CH31_TZ_0) \
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_GPCDMA_COMMON      0x00000000
+#define BASE_ADDRESS_GPCDMA_SCR 0x00000f00
+#define BASE_ADDRESS_GPCDMA_ERRCOLLATOR_SCR     0x0000f000
+#define BASE_ADDRESS_GPCDMA_ERRCOLLATOR 0x0000ff00
+#define BASE_ADDRESS_GPCDMA_CHANNEL     0x00010000
+
+//
+// ARGPCDMA_FLV_32CH REGISTER BANKS
+//
+
+#define GPCDMA_COMMON0_FIRST_REG 0x0000 // GPCDMA_COMMON_DMA_CHAN_STA_0
+#define GPCDMA_COMMON0_LAST_REG 0x0010 // GPCDMA_COMMON_CHANNEL_ERROR_STA_0
+#define GPCDMA_COMMON1_FIRST_REG 0x0018 // GPCDMA_COMMON_CHANNEL_TRIG_REG_0
+#define GPCDMA_COMMON1_LAST_REG 0x0028 // GPCDMA_COMMON_CHANNEL_REG_LOCK_0
+#define GPCDMA_COMMON2_FIRST_REG 0x0080 // GPCDMA_COMMON_CH0_PERI_ID_MASK_0
+#define GPCDMA_COMMON2_LAST_REG 0x0390 // GPCDMA_COMMON_SAFETY_LOGIC_CLK_DISABLE_0
+#define GPCDMA_SCR0_FIRST_REG 0x0f00 // GPCDMA_SCR_SCR_CH0_0
+#define GPCDMA_SCR0_LAST_REG 0x0f8c // GPCDMA_SCR_SCR_SAFETY_0
+#define GPCDMA_ERRCOLLATOR_SCR0_FIRST_REG 0xf000 // GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR_SCR0_LAST_REG 0xf000 // GPCDMA_ERRCOLLATOR_SCR_EC_SCR_0
+#define GPCDMA_ERRCOLLATOR0_FIRST_REG 0xff00 // GPCDMA_ERRCOLLATOR_FEATURE_0
+#define GPCDMA_ERRCOLLATOR0_LAST_REG 0xff0c // GPCDMA_ERRCOLLATOR_CURRENT_COUNTER_VALUE_0
+#define GPCDMA_ERRCOLLATOR1_FIRST_REG 0xff14 // GPCDMA_ERRCOLLATOR_MISSIONERR_INDEX_0
+#define GPCDMA_ERRCOLLATOR1_LAST_REG 0xff1c // GPCDMA_ERRCOLLATOR_MISSIONERR_INJECT_UNLOCK_0
+#define GPCDMA_ERRCOLLATOR2_FIRST_REG 0xff30 // GPCDMA_ERRCOLLATOR_ERRSLICE0_MISSIONERR_ENABLE_0
+#define GPCDMA_ERRCOLLATOR2_LAST_REG 0xff48 // GPCDMA_ERRCOLLATOR_ERRSLICE0_LATENTERR_STATUS_0
+#define GPCDMA_ERRCOLLATOR3_FIRST_REG 0xff50 // GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0
+#define GPCDMA_ERRCOLLATOR3_LAST_REG 0xff50 // GPCDMA_ERRCOLLATOR_ERRSLICE0_COUNTER_RELOAD_0
+#define GPCDMA_CHANNEL0_FIRST_REG 0x10000 // GPCDMA_CHANNEL_CH0_CSR_0
+#define GPCDMA_CHANNEL0_LAST_REG 0x10028 // GPCDMA_CHANNEL_CH0_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL1_FIRST_REG 0x10030 // GPCDMA_CHANNEL_CH0_ERR_STA_0
+#define GPCDMA_CHANNEL1_LAST_REG 0x10040 // GPCDMA_CHANNEL_CH0_SPARE_0
+#define GPCDMA_CHANNEL2_FIRST_REG 0x20000 // GPCDMA_CHANNEL_CH1_CSR_0
+#define GPCDMA_CHANNEL2_LAST_REG 0x20028 // GPCDMA_CHANNEL_CH1_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL3_FIRST_REG 0x20030 // GPCDMA_CHANNEL_CH1_ERR_STA_0
+#define GPCDMA_CHANNEL3_LAST_REG 0x20040 // GPCDMA_CHANNEL_CH1_SPARE_0
+#define GPCDMA_CHANNEL4_FIRST_REG 0x30000 // GPCDMA_CHANNEL_CH2_CSR_0
+#define GPCDMA_CHANNEL4_LAST_REG 0x30028 // GPCDMA_CHANNEL_CH2_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL5_FIRST_REG 0x30030 // GPCDMA_CHANNEL_CH2_ERR_STA_0
+#define GPCDMA_CHANNEL5_LAST_REG 0x30040 // GPCDMA_CHANNEL_CH2_SPARE_0
+#define GPCDMA_CHANNEL6_FIRST_REG 0x40000 // GPCDMA_CHANNEL_CH3_CSR_0
+#define GPCDMA_CHANNEL6_LAST_REG 0x40028 // GPCDMA_CHANNEL_CH3_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL7_FIRST_REG 0x40030 // GPCDMA_CHANNEL_CH3_ERR_STA_0
+#define GPCDMA_CHANNEL7_LAST_REG 0x40040 // GPCDMA_CHANNEL_CH3_SPARE_0
+#define GPCDMA_CHANNEL8_FIRST_REG 0x50000 // GPCDMA_CHANNEL_CH4_CSR_0
+#define GPCDMA_CHANNEL8_LAST_REG 0x50028 // GPCDMA_CHANNEL_CH4_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL9_FIRST_REG 0x50030 // GPCDMA_CHANNEL_CH4_ERR_STA_0
+#define GPCDMA_CHANNEL9_LAST_REG 0x50040 // GPCDMA_CHANNEL_CH4_SPARE_0
+#define GPCDMA_CHANNEL10_FIRST_REG 0x60000 // GPCDMA_CHANNEL_CH5_CSR_0
+#define GPCDMA_CHANNEL10_LAST_REG 0x60028 // GPCDMA_CHANNEL_CH5_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL11_FIRST_REG 0x60030 // GPCDMA_CHANNEL_CH5_ERR_STA_0
+#define GPCDMA_CHANNEL11_LAST_REG 0x60040 // GPCDMA_CHANNEL_CH5_SPARE_0
+#define GPCDMA_CHANNEL12_FIRST_REG 0x70000 // GPCDMA_CHANNEL_CH6_CSR_0
+#define GPCDMA_CHANNEL12_LAST_REG 0x70028 // GPCDMA_CHANNEL_CH6_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL13_FIRST_REG 0x70030 // GPCDMA_CHANNEL_CH6_ERR_STA_0
+#define GPCDMA_CHANNEL13_LAST_REG 0x70040 // GPCDMA_CHANNEL_CH6_SPARE_0
+#define GPCDMA_CHANNEL14_FIRST_REG 0x80000 // GPCDMA_CHANNEL_CH7_CSR_0
+#define GPCDMA_CHANNEL14_LAST_REG 0x80028 // GPCDMA_CHANNEL_CH7_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL15_FIRST_REG 0x80030 // GPCDMA_CHANNEL_CH7_ERR_STA_0
+#define GPCDMA_CHANNEL15_LAST_REG 0x80040 // GPCDMA_CHANNEL_CH7_SPARE_0
+#define GPCDMA_CHANNEL16_FIRST_REG 0x90000 // GPCDMA_CHANNEL_CH8_CSR_0
+#define GPCDMA_CHANNEL16_LAST_REG 0x90028 // GPCDMA_CHANNEL_CH8_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL17_FIRST_REG 0x90030 // GPCDMA_CHANNEL_CH8_ERR_STA_0
+#define GPCDMA_CHANNEL17_LAST_REG 0x90040 // GPCDMA_CHANNEL_CH8_SPARE_0
+#define GPCDMA_CHANNEL18_FIRST_REG 0xa0000 // GPCDMA_CHANNEL_CH9_CSR_0
+#define GPCDMA_CHANNEL18_LAST_REG 0xa0028 // GPCDMA_CHANNEL_CH9_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL19_FIRST_REG 0xa0030 // GPCDMA_CHANNEL_CH9_ERR_STA_0
+#define GPCDMA_CHANNEL19_LAST_REG 0xa0040 // GPCDMA_CHANNEL_CH9_SPARE_0
+#define GPCDMA_CHANNEL20_FIRST_REG 0xb0000 // GPCDMA_CHANNEL_CH10_CSR_0
+#define GPCDMA_CHANNEL20_LAST_REG 0xb0028 // GPCDMA_CHANNEL_CH10_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL21_FIRST_REG 0xb0030 // GPCDMA_CHANNEL_CH10_ERR_STA_0
+#define GPCDMA_CHANNEL21_LAST_REG 0xb0040 // GPCDMA_CHANNEL_CH10_SPARE_0
+#define GPCDMA_CHANNEL22_FIRST_REG 0xc0000 // GPCDMA_CHANNEL_CH11_CSR_0
+#define GPCDMA_CHANNEL22_LAST_REG 0xc0028 // GPCDMA_CHANNEL_CH11_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL23_FIRST_REG 0xc0030 // GPCDMA_CHANNEL_CH11_ERR_STA_0
+#define GPCDMA_CHANNEL23_LAST_REG 0xc0040 // GPCDMA_CHANNEL_CH11_SPARE_0
+#define GPCDMA_CHANNEL24_FIRST_REG 0xd0000 // GPCDMA_CHANNEL_CH12_CSR_0
+#define GPCDMA_CHANNEL24_LAST_REG 0xd0028 // GPCDMA_CHANNEL_CH12_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL25_FIRST_REG 0xd0030 // GPCDMA_CHANNEL_CH12_ERR_STA_0
+#define GPCDMA_CHANNEL25_LAST_REG 0xd0040 // GPCDMA_CHANNEL_CH12_SPARE_0
+#define GPCDMA_CHANNEL26_FIRST_REG 0xe0000 // GPCDMA_CHANNEL_CH13_CSR_0
+#define GPCDMA_CHANNEL26_LAST_REG 0xe0028 // GPCDMA_CHANNEL_CH13_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL27_FIRST_REG 0xe0030 // GPCDMA_CHANNEL_CH13_ERR_STA_0
+#define GPCDMA_CHANNEL27_LAST_REG 0xe0040 // GPCDMA_CHANNEL_CH13_SPARE_0
+#define GPCDMA_CHANNEL28_FIRST_REG 0xf0000 // GPCDMA_CHANNEL_CH14_CSR_0
+#define GPCDMA_CHANNEL28_LAST_REG 0xf0028 // GPCDMA_CHANNEL_CH14_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL29_FIRST_REG 0xf0030 // GPCDMA_CHANNEL_CH14_ERR_STA_0
+#define GPCDMA_CHANNEL29_LAST_REG 0xf0040 // GPCDMA_CHANNEL_CH14_SPARE_0
+#define GPCDMA_CHANNEL30_FIRST_REG 0x100000 // GPCDMA_CHANNEL_CH15_CSR_0
+#define GPCDMA_CHANNEL30_LAST_REG 0x100028 // GPCDMA_CHANNEL_CH15_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL31_FIRST_REG 0x100030 // GPCDMA_CHANNEL_CH15_ERR_STA_0
+#define GPCDMA_CHANNEL31_LAST_REG 0x100040 // GPCDMA_CHANNEL_CH15_SPARE_0
+#define GPCDMA_CHANNEL32_FIRST_REG 0x110000 // GPCDMA_CHANNEL_CH16_CSR_0
+#define GPCDMA_CHANNEL32_LAST_REG 0x110028 // GPCDMA_CHANNEL_CH16_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL33_FIRST_REG 0x110030 // GPCDMA_CHANNEL_CH16_ERR_STA_0
+#define GPCDMA_CHANNEL33_LAST_REG 0x110040 // GPCDMA_CHANNEL_CH16_SPARE_0
+#define GPCDMA_CHANNEL34_FIRST_REG 0x120000 // GPCDMA_CHANNEL_CH17_CSR_0
+#define GPCDMA_CHANNEL34_LAST_REG 0x120028 // GPCDMA_CHANNEL_CH17_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL35_FIRST_REG 0x120030 // GPCDMA_CHANNEL_CH17_ERR_STA_0
+#define GPCDMA_CHANNEL35_LAST_REG 0x120040 // GPCDMA_CHANNEL_CH17_SPARE_0
+#define GPCDMA_CHANNEL36_FIRST_REG 0x130000 // GPCDMA_CHANNEL_CH18_CSR_0
+#define GPCDMA_CHANNEL36_LAST_REG 0x130028 // GPCDMA_CHANNEL_CH18_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL37_FIRST_REG 0x130030 // GPCDMA_CHANNEL_CH18_ERR_STA_0
+#define GPCDMA_CHANNEL37_LAST_REG 0x130040 // GPCDMA_CHANNEL_CH18_SPARE_0
+#define GPCDMA_CHANNEL38_FIRST_REG 0x140000 // GPCDMA_CHANNEL_CH19_CSR_0
+#define GPCDMA_CHANNEL38_LAST_REG 0x140028 // GPCDMA_CHANNEL_CH19_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL39_FIRST_REG 0x140030 // GPCDMA_CHANNEL_CH19_ERR_STA_0
+#define GPCDMA_CHANNEL39_LAST_REG 0x140040 // GPCDMA_CHANNEL_CH19_SPARE_0
+#define GPCDMA_CHANNEL40_FIRST_REG 0x150000 // GPCDMA_CHANNEL_CH20_CSR_0
+#define GPCDMA_CHANNEL40_LAST_REG 0x150028 // GPCDMA_CHANNEL_CH20_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL41_FIRST_REG 0x150030 // GPCDMA_CHANNEL_CH20_ERR_STA_0
+#define GPCDMA_CHANNEL41_LAST_REG 0x150040 // GPCDMA_CHANNEL_CH20_SPARE_0
+#define GPCDMA_CHANNEL42_FIRST_REG 0x160000 // GPCDMA_CHANNEL_CH21_CSR_0
+#define GPCDMA_CHANNEL42_LAST_REG 0x160028 // GPCDMA_CHANNEL_CH21_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL43_FIRST_REG 0x160030 // GPCDMA_CHANNEL_CH21_ERR_STA_0
+#define GPCDMA_CHANNEL43_LAST_REG 0x160040 // GPCDMA_CHANNEL_CH21_SPARE_0
+#define GPCDMA_CHANNEL44_FIRST_REG 0x170000 // GPCDMA_CHANNEL_CH22_CSR_0
+#define GPCDMA_CHANNEL44_LAST_REG 0x170028 // GPCDMA_CHANNEL_CH22_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL45_FIRST_REG 0x170030 // GPCDMA_CHANNEL_CH22_ERR_STA_0
+#define GPCDMA_CHANNEL45_LAST_REG 0x170040 // GPCDMA_CHANNEL_CH22_SPARE_0
+#define GPCDMA_CHANNEL46_FIRST_REG 0x180000 // GPCDMA_CHANNEL_CH23_CSR_0
+#define GPCDMA_CHANNEL46_LAST_REG 0x180028 // GPCDMA_CHANNEL_CH23_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL47_FIRST_REG 0x180030 // GPCDMA_CHANNEL_CH23_ERR_STA_0
+#define GPCDMA_CHANNEL47_LAST_REG 0x180040 // GPCDMA_CHANNEL_CH23_SPARE_0
+#define GPCDMA_CHANNEL48_FIRST_REG 0x190000 // GPCDMA_CHANNEL_CH24_CSR_0
+#define GPCDMA_CHANNEL48_LAST_REG 0x190028 // GPCDMA_CHANNEL_CH24_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL49_FIRST_REG 0x190030 // GPCDMA_CHANNEL_CH24_ERR_STA_0
+#define GPCDMA_CHANNEL49_LAST_REG 0x190040 // GPCDMA_CHANNEL_CH24_SPARE_0
+#define GPCDMA_CHANNEL50_FIRST_REG 0x1a0000 // GPCDMA_CHANNEL_CH25_CSR_0
+#define GPCDMA_CHANNEL50_LAST_REG 0x1a0028 // GPCDMA_CHANNEL_CH25_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL51_FIRST_REG 0x1a0030 // GPCDMA_CHANNEL_CH25_ERR_STA_0
+#define GPCDMA_CHANNEL51_LAST_REG 0x1a0040 // GPCDMA_CHANNEL_CH25_SPARE_0
+#define GPCDMA_CHANNEL52_FIRST_REG 0x1b0000 // GPCDMA_CHANNEL_CH26_CSR_0
+#define GPCDMA_CHANNEL52_LAST_REG 0x1b0028 // GPCDMA_CHANNEL_CH26_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL53_FIRST_REG 0x1b0030 // GPCDMA_CHANNEL_CH26_ERR_STA_0
+#define GPCDMA_CHANNEL53_LAST_REG 0x1b0040 // GPCDMA_CHANNEL_CH26_SPARE_0
+#define GPCDMA_CHANNEL54_FIRST_REG 0x1c0000 // GPCDMA_CHANNEL_CH27_CSR_0
+#define GPCDMA_CHANNEL54_LAST_REG 0x1c0028 // GPCDMA_CHANNEL_CH27_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL55_FIRST_REG 0x1c0030 // GPCDMA_CHANNEL_CH27_ERR_STA_0
+#define GPCDMA_CHANNEL55_LAST_REG 0x1c0040 // GPCDMA_CHANNEL_CH27_SPARE_0
+#define GPCDMA_CHANNEL56_FIRST_REG 0x1d0000 // GPCDMA_CHANNEL_CH28_CSR_0
+#define GPCDMA_CHANNEL56_LAST_REG 0x1d0028 // GPCDMA_CHANNEL_CH28_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL57_FIRST_REG 0x1d0030 // GPCDMA_CHANNEL_CH28_ERR_STA_0
+#define GPCDMA_CHANNEL57_LAST_REG 0x1d0040 // GPCDMA_CHANNEL_CH28_SPARE_0
+#define GPCDMA_CHANNEL58_FIRST_REG 0x1e0000 // GPCDMA_CHANNEL_CH29_CSR_0
+#define GPCDMA_CHANNEL58_LAST_REG 0x1e0028 // GPCDMA_CHANNEL_CH29_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL59_FIRST_REG 0x1e0030 // GPCDMA_CHANNEL_CH29_ERR_STA_0
+#define GPCDMA_CHANNEL59_LAST_REG 0x1e0040 // GPCDMA_CHANNEL_CH29_SPARE_0
+#define GPCDMA_CHANNEL60_FIRST_REG 0x1f0000 // GPCDMA_CHANNEL_CH30_CSR_0
+#define GPCDMA_CHANNEL60_LAST_REG 0x1f0028 // GPCDMA_CHANNEL_CH30_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL61_FIRST_REG 0x1f0030 // GPCDMA_CHANNEL_CH30_ERR_STA_0
+#define GPCDMA_CHANNEL61_LAST_REG 0x1f0040 // GPCDMA_CHANNEL_CH30_SPARE_0
+#define GPCDMA_CHANNEL62_FIRST_REG 0x200000 // GPCDMA_CHANNEL_CH31_CSR_0
+#define GPCDMA_CHANNEL62_LAST_REG 0x200028 // GPCDMA_CHANNEL_CH31_DMA_WORD_STA_0
+#define GPCDMA_CHANNEL63_FIRST_REG 0x200030 // GPCDMA_CHANNEL_CH31_ERR_STA_0
+#define GPCDMA_CHANNEL63_LAST_REG 0x200040 // GPCDMA_CHANNEL_CH31_SPARE_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARGPCDMA_FLV_32CH_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argpcdma_flv_8ch_non_safe.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argpcdma_flv_8ch_non_safe.h
new file mode 100644
index 0000000..21b6514
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argpcdma_flv_8ch_non_safe.h
@@ -0,0 +1,14900 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARGPCDMA_FLV_8CH_NON_SAFE_H_INC
+#define ARGPCDMA_FLV_8CH_NON_SAFE_H_INC
+#define NV_MOBILE_ARGPCDMA_FLV_8CH_NON_SAFE_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARGPCDMA_FLV_8CH_NON_SAFE_H_SCRREG_NOMENCLATURE EXACT
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0                   MK_ADDR_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_SCR                       SCR_DMA_RO_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH0_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH0_RANGE                 0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH0_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH0_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH0_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH1_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH1_RANGE                 1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH1_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH1_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH1_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH2_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH2_RANGE                 2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH2_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH2_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH2_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH3_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH3_RANGE                 3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH3_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH3_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH3_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH4_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH4_RANGE                 4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH4_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH4_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH4_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH5_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH5_RANGE                 5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH5_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH5_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH5_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH6_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH6_RANGE                 6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH6_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH6_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH6_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH7_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH7_RANGE                 7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH7_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH7_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH7_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0_CH7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0                  MK_ADDR_CONST(0x4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_SECURE                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_DUAL                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_SCR                      SCR_DMA_RO_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_SCRREG                   GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_WORD_COUNT                       0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_0_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_0_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_0_RANGE                   0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_0_MSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_0_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_0_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_0_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_0_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_1_SHIFT                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_1_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_1_RANGE                   1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_1_MSB                     MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_1_LSB                     MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_1_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_1_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_1_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_2_SHIFT                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_2_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_2_RANGE                   2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_2_MSB                     MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_2_LSB                     MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_2_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_2_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_2_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_3_SHIFT                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_3_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_3_RANGE                   3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_3_MSB                     MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_3_LSB                     MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_3_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_3_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_3_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_4_SHIFT                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_4_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_4_RANGE                   4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_4_MSB                     MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_4_LSB                     MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_4_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_4_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_4_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_5_SHIFT                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_5_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_5_RANGE                   5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_5_MSB                     MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_5_LSB                     MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_5_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_5_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_5_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_6_SHIFT                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_6_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_6_RANGE                   6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_6_MSB                     MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_6_LSB                     MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_6_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_6_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_6_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_7_SHIFT                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_7_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_7_RANGE                   7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_7_MSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_7_LSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_7_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_7_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_7_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_8_SHIFT                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_8_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_8_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_8_RANGE                   8:8
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_8_MSB                     MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_8_LSB                     MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_8_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_8_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_8_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_8_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_8_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_8_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_8_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_9_SHIFT                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_9_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_9_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_9_RANGE                   9:9
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_9_MSB                     MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_9_LSB                     MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_9_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_9_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_9_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_9_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_9_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_9_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_9_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_10_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_10_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_10_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_10_RANGE                  10:10
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_10_MSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_10_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_10_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_10_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_10_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_10_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_10_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_10_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_10_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_11_SHIFT                  MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_11_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_11_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_11_RANGE                  11:11
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_11_MSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_11_LSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_11_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_11_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_11_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_11_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_11_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_11_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_11_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_12_SHIFT                  MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_12_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_12_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_12_RANGE                  12:12
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_12_MSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_12_LSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_12_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_12_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_12_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_12_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_12_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_12_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_12_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_13_SHIFT                  MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_13_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_13_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_13_RANGE                  13:13
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_13_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_13_LSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_13_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_13_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_13_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_13_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_13_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_13_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_13_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_14_SHIFT                  MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_14_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_14_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_14_RANGE                  14:14
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_14_MSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_14_LSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_14_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_14_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_14_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_14_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_14_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_14_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_14_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_15_SHIFT                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_15_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_15_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_15_RANGE                  15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_15_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_15_LSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_15_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_15_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_15_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_15_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_15_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_15_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0_CLIENT_15_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0                  MK_ADDR_CONST(0x8)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_SECURE                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_DUAL                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_SCR                      SCR_DMA_RO_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_SCRREG                   GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_WORD_COUNT                       0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_0_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_0_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_0_RANGE                   0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_0_MSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_0_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_0_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_0_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_0_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_1_SHIFT                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_1_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_1_RANGE                   1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_1_MSB                     MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_1_LSB                     MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_1_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_1_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_1_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_2_SHIFT                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_2_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_2_RANGE                   2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_2_MSB                     MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_2_LSB                     MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_2_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_2_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_2_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_3_SHIFT                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_3_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_3_RANGE                   3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_3_MSB                     MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_3_LSB                     MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_3_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_3_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_3_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_4_SHIFT                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_4_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_4_RANGE                   4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_4_MSB                     MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_4_LSB                     MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_4_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_4_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_4_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_5_SHIFT                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_5_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_5_RANGE                   5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_5_MSB                     MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_5_LSB                     MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_5_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_5_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_5_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_6_SHIFT                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_6_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_6_RANGE                   6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_6_MSB                     MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_6_LSB                     MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_6_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_6_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_6_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_7_SHIFT                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_7_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_7_RANGE                   7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_7_MSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_7_LSB                     MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_7_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_7_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_7_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_8_SHIFT                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_8_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_8_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_8_RANGE                   8:8
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_8_MSB                     MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_8_LSB                     MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_8_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_8_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_8_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_8_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_8_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_8_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_8_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_9_SHIFT                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_9_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_9_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_9_RANGE                   9:9
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_9_MSB                     MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_9_LSB                     MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_9_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_9_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_9_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_9_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_9_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_9_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_9_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_10_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_10_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_10_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_10_RANGE                  10:10
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_10_MSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_10_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_10_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_10_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_10_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_10_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_10_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_10_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_10_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_11_SHIFT                  MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_11_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_11_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_11_RANGE                  11:11
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_11_MSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_11_LSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_11_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_11_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_11_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_11_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_11_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_11_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_11_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_12_SHIFT                  MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_12_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_12_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_12_RANGE                  12:12
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_12_MSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_12_LSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_12_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_12_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_12_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_12_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_12_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_12_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_12_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_13_SHIFT                  MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_13_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_13_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_13_RANGE                  13:13
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_13_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_13_LSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_13_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_13_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_13_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_13_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_13_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_13_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_13_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_14_SHIFT                  MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_14_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_14_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_14_RANGE                  14:14
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_14_MSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_14_LSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_14_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_14_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_14_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_14_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_14_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_14_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_14_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_15_SHIFT                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_15_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_15_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_15_RANGE                  15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_15_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_15_LSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_15_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_15_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_15_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_15_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_15_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_15_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0_CLIENT_15_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0                       MK_ADDR_CONST(0xc)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_SCR                   SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_FIELD                    MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_RANGE                    31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0                      MK_ADDR_CONST(0x10)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_SCR                  SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_SHIFT                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_FIELD                   MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_RANGE                   31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_LSB                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x14
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0                       MK_ADDR_CONST(0x18)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_SCR                   SCR_DMA_RO_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH0_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH0_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH0_RANGE                     0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH0_MSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH0_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH0_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH0_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH1_SHIFT                     MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH1_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH1_RANGE                     1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH1_MSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH1_LSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH1_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH1_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH2_SHIFT                     MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH2_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH2_RANGE                     2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH2_MSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH2_LSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH2_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH2_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH2_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH3_SHIFT                     MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH3_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH3_RANGE                     3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH3_MSB                       MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH3_LSB                       MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH3_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH3_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH3_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH4_SHIFT                     MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH4_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH4_RANGE                     4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH4_MSB                       MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH4_LSB                       MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH4_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH4_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH4_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH5_SHIFT                     MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH5_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH5_RANGE                     5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH5_MSB                       MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH5_LSB                       MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH5_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH5_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH5_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH6_SHIFT                     MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH6_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH6_RANGE                     6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH6_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH6_LSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH6_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH6_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH6_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH7_SHIFT                     MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH7_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH7_RANGE                     7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH7_MSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH7_LSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH7_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH7_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH7_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH7_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0_CH7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0                        MK_ADDR_CONST(0x1c)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_SCR                    SCR_DMA_RO_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_RESET_VAL                      MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_RESET_MASK                     MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_READ_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH0_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH0_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH0_RANGE                      0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH0_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH0_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH0_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH0_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH1_SHIFT                      MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH1_RANGE                      1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH1_MSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH1_LSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH1_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH2_SHIFT                      MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH2_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH2_RANGE                      2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH2_MSB                        MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH2_LSB                        MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH2_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH2_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH3_SHIFT                      MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH3_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH3_RANGE                      3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH3_MSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH3_LSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH3_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH3_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH4_SHIFT                      MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH4_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH4_RANGE                      4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH4_MSB                        MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH4_LSB                        MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH4_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH4_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH5_SHIFT                      MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH5_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH5_RANGE                      5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH5_MSB                        MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH5_LSB                        MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH5_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH5_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH6_SHIFT                      MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH6_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH6_RANGE                      6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH6_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH6_LSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH6_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH6_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH7_SHIFT                      MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH7_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH7_RANGE                      7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH7_MSB                        MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH7_LSB                        MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH7_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH7_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0_CH7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0                       MK_ADDR_CONST(0x20)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_SCR                   SCR_DMA_RO_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH0_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH0_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH0_RANGE                     0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH0_MSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH0_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH0_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH0_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH1_SHIFT                     MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH1_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH1_RANGE                     1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH1_MSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH1_LSB                       MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH1_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH1_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH2_SHIFT                     MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH2_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH2_RANGE                     2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH2_MSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH2_LSB                       MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH2_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH2_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH2_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH3_SHIFT                     MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH3_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH3_RANGE                     3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH3_MSB                       MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH3_LSB                       MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH3_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH3_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH3_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH4_SHIFT                     MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH4_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH4_RANGE                     4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH4_MSB                       MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH4_LSB                       MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH4_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH4_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH4_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH5_SHIFT                     MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH5_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH5_RANGE                     5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH5_MSB                       MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH5_LSB                       MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH5_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH5_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH5_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH6_SHIFT                     MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH6_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH6_RANGE                     6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH6_MSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH6_LSB                       MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH6_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH6_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH6_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH7_SHIFT                     MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH7_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH7_RANGE                     7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH7_MSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH7_LSB                       MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH7_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH7_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH7_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH7_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0_CH7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0                    MK_ADDR_CONST(0x24)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_RESET_MASK                         MK_MASK_CONST(0x1f)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_READ_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_WRITE_MASK                         MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_SHIFT                      MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_RANGE                      4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_MSB                        MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_LSB                        MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_RAW_INTR_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_SHIFT                      MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_RANGE                      3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_MSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_LSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IRQ_INTR_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IS_EOC_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IS_EOC_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IS_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IS_EOC_RANGE                       2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IS_EOC_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IS_EOC_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IS_EOC_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IS_EOC_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IS_EOC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IS_EOC_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IS_EOC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IS_EOC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IS_EOC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_INTR_MASK_SHIFT                    MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_INTR_MASK_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_INTR_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_INTR_MASK_RANGE                    1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_INTR_MASK_MSB                      MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_INTR_MASK_LSB                      MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_INTR_MASK_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_INTR_MASK_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_INTR_MASK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_INTR_MASK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_INTR_MASK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_INTR_MASK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_INTR_MASK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IE_EOC_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IE_EOC_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IE_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IE_EOC_RANGE                       0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IE_EOC_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IE_EOC_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IE_EOC_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IE_EOC_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IE_EOC_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IE_EOC_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IE_EOC_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IE_EOC_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0_IE_EOC_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0                       MK_ADDR_CONST(0x28)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_RANGE                 31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0_REGLOCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0                       MK_ADDR_CONST(0x80)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_RANGE                        31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0_CH0_PERI_ID_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0                       MK_ADDR_CONST(0x84)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_RANGE                        31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0_CH1_PERI_ID_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0                       MK_ADDR_CONST(0x88)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_RANGE                        31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0_CH2_PERI_ID_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0                       MK_ADDR_CONST(0x8c)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_RANGE                        31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0_CH3_PERI_ID_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0                       MK_ADDR_CONST(0x90)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_RANGE                        31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0_CH4_PERI_ID_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0                       MK_ADDR_CONST(0x94)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_RANGE                        31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0_CH5_PERI_ID_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0                       MK_ADDR_CONST(0x98)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_RANGE                        31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0_CH6_PERI_ID_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0                       MK_ADDR_CONST(0x9c)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_SCR                   SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_RANGE                        31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0_CH7_PERI_ID_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0                 MK_ADDR_CONST(0x100)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_FIELD                      MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_RANGE                      31:16
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_START_ADDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_FIELD                  MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_RANGE                  15:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0_PER0_PERI_OFFSET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0                 MK_ADDR_CONST(0x104)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_FIELD                      MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_RANGE                      31:16
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_START_ADDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_FIELD                  MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_RANGE                  15:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0_PER1_PERI_OFFSET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0                 MK_ADDR_CONST(0x108)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_FIELD                      MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_RANGE                      31:16
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_START_ADDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_FIELD                  MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_RANGE                  15:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0_PER2_PERI_OFFSET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0                 MK_ADDR_CONST(0x10c)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_FIELD                      MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_RANGE                      31:16
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_START_ADDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_FIELD                  MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_RANGE                  15:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0_PER3_PERI_OFFSET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0                 MK_ADDR_CONST(0x110)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_FIELD                      MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_RANGE                      31:16
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_START_ADDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_FIELD                  MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_RANGE                  15:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0_PER4_PERI_OFFSET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0                 MK_ADDR_CONST(0x114)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_FIELD                      MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_RANGE                      31:16
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_START_ADDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_FIELD                  MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_RANGE                  15:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0_PER5_PERI_OFFSET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0                 MK_ADDR_CONST(0x118)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_FIELD                      MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_RANGE                      31:16
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_START_ADDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_FIELD                  MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_RANGE                  15:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0_PER6_PERI_OFFSET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0                 MK_ADDR_CONST(0x11c)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_FIELD                      MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_RANGE                      31:16
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_START_ADDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_FIELD                  MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_RANGE                  15:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0_PER7_PERI_OFFSET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0                 MK_ADDR_CONST(0x120)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_FIELD                      MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_RANGE                      31:16
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_START_ADDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_FIELD                  MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_RANGE                  15:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0_PER8_PERI_OFFSET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0                 MK_ADDR_CONST(0x124)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_SCR                     SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_FIELD                      MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_RANGE                      31:16
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_START_ADDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_FIELD                  MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_RANGE                  15:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0_PER9_PERI_OFFSET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0                        MK_ADDR_CONST(0x128)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_SCR                    SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_FIELD                    MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_RANGE                    31:16
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_START_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_FIELD                        MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_RANGE                        15:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0_PER10_PERI_OFFSET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0                        MK_ADDR_CONST(0x12c)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_SCR                    SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_FIELD                    MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_RANGE                    31:16
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_START_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_FIELD                        MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_RANGE                        15:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0_PER11_PERI_OFFSET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0                        MK_ADDR_CONST(0x130)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_SCR                    SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_FIELD                    MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_RANGE                    31:16
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_START_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_FIELD                        MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_RANGE                        15:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0_PER12_PERI_OFFSET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0                        MK_ADDR_CONST(0x134)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_SCR                    SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_FIELD                    MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_RANGE                    31:16
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_START_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_FIELD                        MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_RANGE                        15:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0_PER13_PERI_OFFSET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0                        MK_ADDR_CONST(0x138)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_SCR                    SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_FIELD                    MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_RANGE                    31:16
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_START_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_FIELD                        MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_RANGE                        15:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0_PER14_PERI_OFFSET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0                        MK_ADDR_CONST(0x13c)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_SCR                    SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_SHIFT                    MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_FIELD                    MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_RANGE                    31:16
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_LSB                      MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_START_ADDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_FIELD                        MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_RANGE                        15:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0_PER15_PERI_OFFSET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x180)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0_CH0_STREAM_ID0_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x184)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0_CH1_STREAM_ID0_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x188)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0_CH2_STREAM_ID0_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x18c)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0_CH3_STREAM_ID0_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x190)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0_CH4_STREAM_ID0_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x194)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0_CH5_STREAM_ID0_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x198)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0_CH6_STREAM_ID0_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0                    MK_ADDR_CONST(0x19c)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0_CH7_STREAM_ID0_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x200)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0_CH0_STREAM_ID1_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x204)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0_CH1_STREAM_ID1_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x208)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0_CH2_STREAM_ID1_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x20c)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0_CH3_STREAM_ID1_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x210)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0_CH4_STREAM_ID1_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x214)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0_CH5_STREAM_ID1_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x218)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0_CH6_STREAM_ID1_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0                    MK_ADDR_CONST(0x21c)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0_CH7_STREAM_ID1_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x280)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0_CH0_STREAM_ID2_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x284)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0_CH1_STREAM_ID2_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x288)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0_CH2_STREAM_ID2_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x28c)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0_CH3_STREAM_ID2_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x290)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0_CH4_STREAM_ID2_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x294)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0_CH5_STREAM_ID2_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x298)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0_CH6_STREAM_ID2_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0                    MK_ADDR_CONST(0x29c)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0_CH7_STREAM_ID2_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x300)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0_CH0_STREAM_ID3_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x304)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0_CH1_STREAM_ID3_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x308)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0_CH2_STREAM_ID3_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x30c)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0_CH3_STREAM_ID3_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x310)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0_CH4_STREAM_ID3_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x314)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0_CH5_STREAM_ID3_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x318)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0_CH6_STREAM_ID3_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0                    MK_ADDR_CONST(0x31c)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_SCR                        SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_FIELD                  MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_RANGE                  31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_MSB                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0_CH7_STREAM_ID3_MASK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0                 MK_ADDR_CONST(0x380)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_SCR                     SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_RANGE                       0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_SHIFT                       MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_RANGE                       1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_MSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_LSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_RANGE                       2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_RANGE                       3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_SHIFT                       MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_RANGE                       4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_MSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_LSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_SHIFT                       MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_RANGE                       5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_MSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_LSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_SHIFT                       MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_RANGE                       6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_LSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_SHIFT                       MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_RANGE                       7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_LSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0_CH7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0                    MK_ADDR_CONST(0x384)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_SCR                        0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_SCRREG                     0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_RANGE                  0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_MSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0_DMA_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0                     MK_ADDR_CONST(0x388)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_SECURE                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DUAL                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_SCR                         0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_SCRREG                      0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_WORD_COUNT                  0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_RANGE                    0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_MSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_ACTIVE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_SHIFT                      MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_RANGE                      1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_MSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_LSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_MC_ACTIVE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_RANGE                 2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_MC_ACTIVE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_RANGE                 3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0_DMA_IO_ACTIVE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x390
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0                   MK_ADDR_CONST(0xf00)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SCR                       0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SCRREG                    0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_LCK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_WEN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_REN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_OWNER_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR7_RANGE                 23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR7_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR6_RANGE                 22:22
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR6_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR5_RANGE                 21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR5_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR4_RANGE                 20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR4_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR3_RANGE                 19:19
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR3_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR2_RANGE                 18:18
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR2_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR1_RANGE                 17:17
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR1_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR0_RANGE                 16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR0_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7W_RANGE                 15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6W_RANGE                 14:14
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5W_RANGE                 13:13
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4W_RANGE                 12:12
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3W_RANGE                 11:11
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2W_RANGE                 10:10
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1W_RANGE                 9:9
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0W_RANGE                 8:8
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7R_RANGE                 7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6R_RANGE                 6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5R_RANGE                 5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4R_RANGE                 4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3R_RANGE                 3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2R_RANGE                 2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1R_RANGE                 1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0R_RANGE                 0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0                   MK_ADDR_CONST(0xf04)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SCR                       0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SCRREG                    0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_LCK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_WEN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_REN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_OWNER_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR7_RANGE                 23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR7_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR6_RANGE                 22:22
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR6_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR5_RANGE                 21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR5_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR4_RANGE                 20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR4_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR3_RANGE                 19:19
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR3_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR2_RANGE                 18:18
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR2_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR1_RANGE                 17:17
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR1_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR0_RANGE                 16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR0_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7W_RANGE                 15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6W_RANGE                 14:14
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5W_RANGE                 13:13
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4W_RANGE                 12:12
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3W_RANGE                 11:11
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2W_RANGE                 10:10
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1W_RANGE                 9:9
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0W_RANGE                 8:8
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7R_RANGE                 7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6R_RANGE                 6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5R_RANGE                 5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4R_RANGE                 4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3R_RANGE                 3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2R_RANGE                 2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1R_RANGE                 1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0R_RANGE                 0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0                   MK_ADDR_CONST(0xf08)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SCR                       0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SCRREG                    0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_LCK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_WEN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_REN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_OWNER_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR7_RANGE                 23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR7_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR6_RANGE                 22:22
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR6_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR5_RANGE                 21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR5_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR4_RANGE                 20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR4_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR3_RANGE                 19:19
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR3_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR2_RANGE                 18:18
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR2_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR1_RANGE                 17:17
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR1_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR0_RANGE                 16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR0_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7W_RANGE                 15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6W_RANGE                 14:14
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5W_RANGE                 13:13
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4W_RANGE                 12:12
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3W_RANGE                 11:11
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2W_RANGE                 10:10
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1W_RANGE                 9:9
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0W_RANGE                 8:8
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7R_RANGE                 7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6R_RANGE                 6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5R_RANGE                 5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4R_RANGE                 4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3R_RANGE                 3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2R_RANGE                 2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1R_RANGE                 1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0R_RANGE                 0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0                   MK_ADDR_CONST(0xf0c)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SCR                       0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SCRREG                    0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_LCK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_WEN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_REN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_OWNER_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR7_RANGE                 23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR7_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR6_RANGE                 22:22
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR6_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR5_RANGE                 21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR5_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR4_RANGE                 20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR4_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR3_RANGE                 19:19
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR3_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR2_RANGE                 18:18
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR2_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR1_RANGE                 17:17
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR1_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR0_RANGE                 16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR0_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7W_RANGE                 15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6W_RANGE                 14:14
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5W_RANGE                 13:13
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4W_RANGE                 12:12
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3W_RANGE                 11:11
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2W_RANGE                 10:10
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1W_RANGE                 9:9
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0W_RANGE                 8:8
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7R_RANGE                 7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6R_RANGE                 6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5R_RANGE                 5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4R_RANGE                 4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3R_RANGE                 3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2R_RANGE                 2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1R_RANGE                 1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0R_RANGE                 0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0                   MK_ADDR_CONST(0xf10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SCR                       0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SCRREG                    0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_LCK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_WEN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_REN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_OWNER_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR7_RANGE                 23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR7_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR6_RANGE                 22:22
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR6_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR5_RANGE                 21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR5_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR4_RANGE                 20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR4_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR3_RANGE                 19:19
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR3_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR2_RANGE                 18:18
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR2_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR1_RANGE                 17:17
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR1_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR0_RANGE                 16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR0_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7W_RANGE                 15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6W_RANGE                 14:14
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5W_RANGE                 13:13
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4W_RANGE                 12:12
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3W_RANGE                 11:11
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2W_RANGE                 10:10
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1W_RANGE                 9:9
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0W_RANGE                 8:8
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7R_RANGE                 7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6R_RANGE                 6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5R_RANGE                 5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4R_RANGE                 4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3R_RANGE                 3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2R_RANGE                 2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1R_RANGE                 1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0R_RANGE                 0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0                   MK_ADDR_CONST(0xf14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SCR                       0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SCRREG                    0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_LCK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_WEN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_REN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_OWNER_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR7_RANGE                 23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR7_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR6_RANGE                 22:22
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR6_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR5_RANGE                 21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR5_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR4_RANGE                 20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR4_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR3_RANGE                 19:19
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR3_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR2_RANGE                 18:18
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR2_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR1_RANGE                 17:17
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR1_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR0_RANGE                 16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR0_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7W_RANGE                 15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6W_RANGE                 14:14
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5W_RANGE                 13:13
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4W_RANGE                 12:12
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3W_RANGE                 11:11
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2W_RANGE                 10:10
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1W_RANGE                 9:9
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0W_RANGE                 8:8
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7R_RANGE                 7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6R_RANGE                 6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5R_RANGE                 5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4R_RANGE                 4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3R_RANGE                 3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2R_RANGE                 2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1R_RANGE                 1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0R_RANGE                 0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0                   MK_ADDR_CONST(0xf18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SCR                       0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SCRREG                    0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_LCK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_WEN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_REN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_OWNER_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR7_RANGE                 23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR7_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR6_RANGE                 22:22
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR6_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR5_RANGE                 21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR5_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR4_RANGE                 20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR4_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR3_RANGE                 19:19
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR3_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR2_RANGE                 18:18
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR2_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR1_RANGE                 17:17
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR1_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR0_RANGE                 16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR0_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7W_RANGE                 15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6W_RANGE                 14:14
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5W_RANGE                 13:13
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4W_RANGE                 12:12
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3W_RANGE                 11:11
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2W_RANGE                 10:10
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1W_RANGE                 9:9
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0W_RANGE                 8:8
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7R_RANGE                 7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6R_RANGE                 6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5R_RANGE                 5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4R_RANGE                 4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3R_RANGE                 3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2R_RANGE                 2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1R_RANGE                 1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0R_RANGE                 0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0                   MK_ADDR_CONST(0xf1c)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SCR                       0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SCRREG                    0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_WRITE_MASK                        MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_LCK_SHIFT                     MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_LCK_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_LCK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_LCK_RANGE                     29:29
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_LCK_MSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_LCK_LSB                       MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_LCK_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_LCK_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_LCK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_LCK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_LCK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_LCK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_LCK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_WEN_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_WEN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_WEN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_WEN_RANGE                     28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_WEN_MSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_WEN_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_WEN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_WEN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_WEN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_WEN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_WEN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_WEN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_WEN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_REN_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_REN_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_REN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_REN_RANGE                     27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_REN_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_REN_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_REN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_REN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_REN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_REN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_REN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_REN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_REN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_OWNER_SHIFT                   MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_OWNER_FIELD                   MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_OWNER_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_OWNER_RANGE                   26:24
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_OWNER_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_OWNER_LSB                     MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_OWNER_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_OWNER_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_OWNER_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_OWNER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_OWNER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_OWNER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_SEC_OWNER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR7_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR7_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR7_RANGE                 23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR7_MSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR7_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR7_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR7_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR7_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR6_SHIFT                 MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR6_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR6_RANGE                 22:22
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR6_MSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR6_LSB                   MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR6_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR6_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR6_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR5_SHIFT                 MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR5_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR5_RANGE                 21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR5_MSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR5_LSB                   MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR5_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR5_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR4_SHIFT                 MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR4_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR4_RANGE                 20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR4_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR4_LSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR4_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR4_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR4_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR3_SHIFT                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR3_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR3_RANGE                 19:19
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR3_MSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR3_LSB                   MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR3_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR3_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR2_SHIFT                 MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR2_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR2_RANGE                 18:18
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR2_MSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR2_LSB                   MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR2_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR2_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR1_SHIFT                 MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR1_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR1_RANGE                 17:17
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR1_MSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR1_LSB                   MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR1_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR0_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR0_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR0_RANGE                 16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR0_MSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR0_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR0_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_PR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7W_SHIFT                 MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7W_RANGE                 15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7W_MSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7W_LSB                   MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6W_SHIFT                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6W_RANGE                 14:14
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6W_MSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6W_LSB                   MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5W_SHIFT                 MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5W_RANGE                 13:13
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5W_MSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5W_LSB                   MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4W_SHIFT                 MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4W_RANGE                 12:12
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4W_MSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4W_LSB                   MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3W_SHIFT                 MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3W_RANGE                 11:11
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3W_MSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3W_LSB                   MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2W_SHIFT                 MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2W_RANGE                 10:10
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2W_MSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2W_LSB                   MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1W_SHIFT                 MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1W_RANGE                 9:9
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1W_MSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1W_LSB                   MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0W_SHIFT                 MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0W_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0W_RANGE                 8:8
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0W_MSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0W_LSB                   MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0W_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0W_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0W_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0W_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0W_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0W_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0W_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7R_SHIFT                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7R_RANGE                 7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7R_MSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7R_LSB                   MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G7R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6R_SHIFT                 MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6R_RANGE                 6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6R_MSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6R_LSB                   MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G6R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5R_SHIFT                 MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5R_RANGE                 5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5R_MSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5R_LSB                   MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G5R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4R_SHIFT                 MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4R_RANGE                 4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4R_MSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4R_LSB                   MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G4R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3R_SHIFT                 MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3R_RANGE                 3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3R_MSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3R_LSB                   MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G3R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2R_SHIFT                 MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2R_RANGE                 2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2R_MSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2R_LSB                   MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G2R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1R_SHIFT                 MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1R_RANGE                 1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1R_MSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1R_LSB                   MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G1R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0R_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0R_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0R_RANGE                 0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0R_MSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0R_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0R_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0R_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0R_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0R_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0R_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0R_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0_G0R_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xf20
+
+// Reserved address 0xf24
+
+// Reserved address 0xf28
+
+// Reserved address 0xf2c
+
+// Reserved address 0xf30
+
+// Reserved address 0xf34
+
+// Reserved address 0xf38
+
+// Reserved address 0xf3c
+
+// Reserved address 0xf40
+
+// Reserved address 0xf44
+
+// Reserved address 0xf48
+
+// Reserved address 0xf4c
+
+// Reserved address 0xf50
+
+// Reserved address 0xf54
+
+// Reserved address 0xf58
+
+// Reserved address 0xf5c
+
+// Reserved address 0xf60
+
+// Reserved address 0xf64
+
+// Reserved address 0xf68
+
+// Reserved address 0xf6c
+
+// Reserved address 0xf70
+
+// Reserved address 0xf74
+
+// Reserved address 0xf78
+
+// Reserved address 0xf7c
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0                    MK_ADDR_CONST(0xf80)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SCR                        0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SCRREG                     0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_RESET_VAL                  MK_MASK_CONST(0x38000101)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_LCK_SHIFT                      MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_LCK_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_LCK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_LCK_RANGE                      29:29
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_LCK_MSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_LCK_LSB                        MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_LCK_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_LCK_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_LCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_LCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_LCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_LCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_LCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_WEN_SHIFT                      MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_WEN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_WEN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_WEN_RANGE                      28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_WEN_MSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_WEN_LSB                        MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_WEN_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_WEN_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_WEN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_WEN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_WEN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_WEN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_WEN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_REN_SHIFT                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_REN_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_REN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_REN_RANGE                      27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_REN_MSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_REN_LSB                        MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_REN_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_REN_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_REN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_REN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_REN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_REN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_REN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_OWNER_SHIFT                    MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_OWNER_FIELD                    MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_OWNER_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_OWNER_RANGE                    26:24
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_OWNER_MSB                      MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_OWNER_LSB                      MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_OWNER_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_OWNER_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_OWNER_DEFAULT_MASK                     MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_OWNER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_OWNER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_OWNER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_SEC_OWNER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR7_SHIFT                  MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR7_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR7_RANGE                  23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR7_MSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR7_LSB                    MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR7_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR7_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR7_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR7_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR6_SHIFT                  MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR6_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR6_RANGE                  22:22
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR6_MSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR6_LSB                    MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR6_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR6_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR6_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR6_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR5_SHIFT                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR5_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR5_RANGE                  21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR5_MSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR5_LSB                    MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR5_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR5_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR5_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR5_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR4_SHIFT                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR4_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR4_RANGE                  20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR4_MSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR4_LSB                    MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR4_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR4_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR4_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR4_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR3_SHIFT                  MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR3_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR3_RANGE                  19:19
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR3_MSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR3_LSB                    MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR3_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR3_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR3_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR3_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR2_SHIFT                  MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR2_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR2_RANGE                  18:18
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR2_MSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR2_LSB                    MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR2_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR2_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR2_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR2_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR1_SHIFT                  MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR1_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR1_RANGE                  17:17
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR1_MSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR1_LSB                    MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR1_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR1_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR0_SHIFT                  MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR0_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR0_RANGE                  16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR0_MSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR0_LSB                    MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR0_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR0_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_PR0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7W_SHIFT                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7W_RANGE                  15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7W_MSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7W_LSB                    MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7W_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6W_SHIFT                  MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6W_RANGE                  14:14
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6W_MSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6W_LSB                    MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6W_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5W_SHIFT                  MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5W_RANGE                  13:13
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5W_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5W_LSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5W_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4W_SHIFT                  MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4W_RANGE                  12:12
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4W_MSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4W_LSB                    MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4W_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3W_SHIFT                  MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3W_RANGE                  11:11
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3W_MSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3W_LSB                    MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3W_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2W_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2W_RANGE                  10:10
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2W_MSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2W_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2W_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1W_SHIFT                  MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1W_RANGE                  9:9
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1W_MSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1W_LSB                    MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1W_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1W_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0W_SHIFT                  MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0W_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0W_RANGE                  8:8
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0W_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0W_LSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0W_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0W_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0W_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0W_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0W_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0W_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0W_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7R_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7R_RANGE                  7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7R_MSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7R_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7R_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G7R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6R_SHIFT                  MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6R_RANGE                  6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6R_MSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6R_LSB                    MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6R_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G6R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5R_SHIFT                  MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5R_RANGE                  5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5R_MSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5R_LSB                    MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5R_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G5R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4R_SHIFT                  MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4R_RANGE                  4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4R_MSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4R_LSB                    MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4R_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G4R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3R_SHIFT                  MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3R_RANGE                  3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3R_MSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3R_LSB                    MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3R_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G3R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2R_SHIFT                  MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2R_RANGE                  2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2R_MSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2R_LSB                    MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2R_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G2R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1R_SHIFT                  MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1R_RANGE                  1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1R_MSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1R_LSB                    MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1R_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1R_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G1R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0R_SHIFT                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0R_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0R_RANGE                  0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0R_MSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0R_LSB                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0R_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0R_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0R_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0R_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0R_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0R_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0_G0R_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0                        MK_ADDR_CONST(0xf84)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SCR                    0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SCRREG                         0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_LCK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_LCK_RANGE                  29:29
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_LCK_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_WEN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_WEN_RANGE                  28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_WEN_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_REN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_REN_RANGE                  27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_REN_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_OWNER_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_OWNER_RANGE                        26:24
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_OWNER_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR7_RANGE                      23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR7_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR6_RANGE                      22:22
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR6_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR5_RANGE                      21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR5_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR4_RANGE                      20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR4_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR3_RANGE                      19:19
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR3_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR2_RANGE                      18:18
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR2_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR1_RANGE                      17:17
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR1_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR0_RANGE                      16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR0_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7W_RANGE                      15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7W_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6W_RANGE                      14:14
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6W_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5W_RANGE                      13:13
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5W_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4W_RANGE                      12:12
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4W_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3W_RANGE                      11:11
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3W_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2W_RANGE                      10:10
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2W_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1W_RANGE                      9:9
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1W_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0W_RANGE                      8:8
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0W_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7R_RANGE                      7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7R_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6R_RANGE                      6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6R_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5R_RANGE                      5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5R_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4R_RANGE                      4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4R_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3R_RANGE                      3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3R_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2R_RANGE                      2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2R_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1R_RANGE                      1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1R_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0R_RANGE                      0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0R_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0                 MK_ADDR_CONST(0xf88)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SCR                     0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SCRREG                  0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_LCK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_LCK_RANGE                   29:29
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_LCK_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_WEN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_WEN_RANGE                   28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_WEN_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_REN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_REN_RANGE                   27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_REN_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_OWNER_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_OWNER_RANGE                 26:24
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_OWNER_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR7_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR7_RANGE                       23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR7_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR6_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR6_RANGE                       22:22
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR6_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR5_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR5_RANGE                       21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR5_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR4_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR4_RANGE                       20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR4_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR3_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR3_RANGE                       19:19
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR3_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR2_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR2_RANGE                       18:18
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR2_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR1_RANGE                       17:17
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR1_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR0_RANGE                       16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR0_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7W_RANGE                       15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7W_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6W_RANGE                       14:14
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6W_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5W_RANGE                       13:13
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5W_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4W_RANGE                       12:12
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4W_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3W_RANGE                       11:11
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3W_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2W_RANGE                       10:10
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2W_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1W_RANGE                       9:9
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1W_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0W_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0W_RANGE                       8:8
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0W_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7R_RANGE                       7:7
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7R_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6R_RANGE                       6:6
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6R_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5R_RANGE                       5:5
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5R_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4R_RANGE                       4:4
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4R_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3R_RANGE                       3:3
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3R_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2R_RANGE                       2:2
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2R_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1R_RANGE                       1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1R_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0R_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0R_RANGE                       0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0R_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0                       MK_ADDR_CONST(0x10000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_SCR                   SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ENB_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ONCE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0                       MK_ADDR_CONST(0x10004)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_SCR                   SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_BSY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0                      MK_ADDR_CONST(0x10008)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_SCR                  SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0                   MK_ADDR_CONST(0x1000c)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SCR                       SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0                   MK_ADDR_CONST(0x10010)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_SCR                       SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0                        MK_ADDR_CONST(0x10014)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_SCR                    SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0                    MK_ADDR_CONST(0x10018)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_SCR                        SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0                  MK_ADDR_CONST(0x1001c)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_SCR                      SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_SCRREG                   GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0                    MK_ADDR_CONST(0x10020)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_SCR                        SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x10024)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_SCR                  SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0                      MK_ADDR_CONST(0x10028)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_SCR                  SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x1002c
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0                   MK_ADDR_CONST(0x10030)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_SCR                       SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0                 MK_ADDR_CONST(0x10034)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_SCR                     SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0                        MK_ADDR_CONST(0x10038)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0                       MK_ADDR_CONST(0x20000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_SCR                   SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ENB_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ONCE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0                       MK_ADDR_CONST(0x20004)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_SCR                   SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_BSY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0                      MK_ADDR_CONST(0x20008)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_SCR                  SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0                   MK_ADDR_CONST(0x2000c)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SCR                       SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0                   MK_ADDR_CONST(0x20010)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_SCR                       SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0                        MK_ADDR_CONST(0x20014)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_SCR                    SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0                    MK_ADDR_CONST(0x20018)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_SCR                        SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0                  MK_ADDR_CONST(0x2001c)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_SCR                      SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_SCRREG                   GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0                    MK_ADDR_CONST(0x20020)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_SCR                        SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x20024)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_SCR                  SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0                      MK_ADDR_CONST(0x20028)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_SCR                  SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x2002c
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0                   MK_ADDR_CONST(0x20030)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_SCR                       SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0                 MK_ADDR_CONST(0x20034)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_SCR                     SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0                        MK_ADDR_CONST(0x20038)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0                       MK_ADDR_CONST(0x30000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_SCR                   SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ENB_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ONCE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0                       MK_ADDR_CONST(0x30004)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_SCR                   SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_BSY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0                      MK_ADDR_CONST(0x30008)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_SCR                  SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0                   MK_ADDR_CONST(0x3000c)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SCR                       SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0                   MK_ADDR_CONST(0x30010)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_SCR                       SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0                        MK_ADDR_CONST(0x30014)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_SCR                    SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0                    MK_ADDR_CONST(0x30018)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_SCR                        SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0                  MK_ADDR_CONST(0x3001c)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_SCR                      SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_SCRREG                   GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0                    MK_ADDR_CONST(0x30020)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_SCR                        SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x30024)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_SCR                  SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0                      MK_ADDR_CONST(0x30028)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_SCR                  SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x3002c
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0                   MK_ADDR_CONST(0x30030)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_SCR                       SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0                 MK_ADDR_CONST(0x30034)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_SCR                     SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0                        MK_ADDR_CONST(0x30038)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0                       MK_ADDR_CONST(0x40000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_SCR                   SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ENB_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ONCE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0                       MK_ADDR_CONST(0x40004)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_SCR                   SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_BSY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0                      MK_ADDR_CONST(0x40008)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_SCR                  SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0                   MK_ADDR_CONST(0x4000c)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SCR                       SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0                   MK_ADDR_CONST(0x40010)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_SCR                       SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0                        MK_ADDR_CONST(0x40014)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_SCR                    SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0                    MK_ADDR_CONST(0x40018)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_SCR                        SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0                  MK_ADDR_CONST(0x4001c)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_SCR                      SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_SCRREG                   GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0                    MK_ADDR_CONST(0x40020)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_SCR                        SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x40024)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_SCR                  SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0                      MK_ADDR_CONST(0x40028)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_SCR                  SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x4002c
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0                   MK_ADDR_CONST(0x40030)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_SCR                       SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0                 MK_ADDR_CONST(0x40034)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_SCR                     SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0                        MK_ADDR_CONST(0x40038)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0                       MK_ADDR_CONST(0x50000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_SCR                   SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ENB_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ONCE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0                       MK_ADDR_CONST(0x50004)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_SCR                   SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_BSY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0                      MK_ADDR_CONST(0x50008)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_SCR                  SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0                   MK_ADDR_CONST(0x5000c)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SCR                       SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0                   MK_ADDR_CONST(0x50010)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_SCR                       SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0                        MK_ADDR_CONST(0x50014)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_SCR                    SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0                    MK_ADDR_CONST(0x50018)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_SCR                        SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0                  MK_ADDR_CONST(0x5001c)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_SCR                      SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_SCRREG                   GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0                    MK_ADDR_CONST(0x50020)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_SCR                        SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x50024)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_SCR                  SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0                      MK_ADDR_CONST(0x50028)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_SCR                  SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x5002c
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0                   MK_ADDR_CONST(0x50030)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_SCR                       SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0                 MK_ADDR_CONST(0x50034)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_SCR                     SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0                        MK_ADDR_CONST(0x50038)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0                       MK_ADDR_CONST(0x60000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_SCR                   SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ENB_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ONCE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0                       MK_ADDR_CONST(0x60004)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_SCR                   SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_BSY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0                      MK_ADDR_CONST(0x60008)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_SCR                  SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0                   MK_ADDR_CONST(0x6000c)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SCR                       SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0                   MK_ADDR_CONST(0x60010)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_SCR                       SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0                        MK_ADDR_CONST(0x60014)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_SCR                    SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0                    MK_ADDR_CONST(0x60018)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_SCR                        SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0                  MK_ADDR_CONST(0x6001c)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_SCR                      SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_SCRREG                   GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0                    MK_ADDR_CONST(0x60020)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_SCR                        SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x60024)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_SCR                  SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0                      MK_ADDR_CONST(0x60028)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_SCR                  SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x6002c
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0                   MK_ADDR_CONST(0x60030)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_SCR                       SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0                 MK_ADDR_CONST(0x60034)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_SCR                     SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0                        MK_ADDR_CONST(0x60038)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SPARE_0_SPARE_LO_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SPARE_0_SPARE_LO_FIELD                      MK_FIELD_CONST(0xffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SPARE_0_SPARE_LO_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SPARE_0_SPARE_LO_RANGE                      15:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SPARE_0_SPARE_LO_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SPARE_0_SPARE_LO_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SPARE_0_SPARE_LO_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SPARE_0_SPARE_LO_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SPARE_0_SPARE_LO_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SPARE_0_SPARE_LO_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SPARE_0_SPARE_LO_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SPARE_0_SPARE_LO_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SPARE_0_SPARE_LO_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0                       MK_ADDR_CONST(0x70000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_SCR                   SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ENB_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ONCE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0                       MK_ADDR_CONST(0x70004)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_SCR                   SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_BSY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0                      MK_ADDR_CONST(0x70008)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_SCR                  SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0                   MK_ADDR_CONST(0x7000c)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SCR                       SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0                   MK_ADDR_CONST(0x70010)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_SCR                       SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0                        MK_ADDR_CONST(0x70014)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_SCR                    SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0                    MK_ADDR_CONST(0x70018)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_SCR                        SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0                  MK_ADDR_CONST(0x7001c)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_SCR                      SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_SCRREG                   GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0                    MK_ADDR_CONST(0x70020)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_SCR                        SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x70024)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_SCR                  SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0                      MK_ADDR_CONST(0x70028)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_SCR                  SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x7002c
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0                   MK_ADDR_CONST(0x70030)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_SCR                       SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0                 MK_ADDR_CONST(0x70034)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_SCR                     SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0                        MK_ADDR_CONST(0x70038)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0                       MK_ADDR_CONST(0x80000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_SCR                   SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_RESET_VAL                     MK_MASK_CONST(0x8008400)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_RESET_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_READ_MASK                     MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_WRITE_MASK                    MK_MASK_CONST(0xcbffbc00)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ENB_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ENB_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ENB_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ENB_RANGE                     31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ENB_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ENB_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ENB_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ENB_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ENB_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ENB_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ENB_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ENB_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ENB_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ENB_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ENB_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IE_EOC_SHIFT                  MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IE_EOC_FIELD                  MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IE_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IE_EOC_RANGE                  30:30
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IE_EOC_MSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IE_EOC_LSB                    MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IE_EOC_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IE_EOC_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IE_EOC_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IE_EOC_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IE_EOC_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IE_EOC_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IE_EOC_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IE_EOC_DISABLE                        MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IE_EOC_ENABLE                 MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ONCE_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ONCE_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ONCE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ONCE_RANGE                    27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ONCE_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ONCE_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ONCE_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ONCE_DEFAULT                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ONCE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ONCE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ONCE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ONCE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ONCE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ONCE_CYCLIC_MODE                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_ONCE_SINGLE_BLOCK                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_FC_MODE_SHIFT                 MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_FC_MODE_FIELD                 MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_FC_MODE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_FC_MODE_RANGE                 25:24
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_FC_MODE_MSB                   MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_FC_MODE_LSB                   MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_FC_MODE_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_FC_MODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_FC_MODE_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_FC_MODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_FC_MODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_FC_MODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_FC_MODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_FC_MODE_NO_MMIO                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_FC_MODE_ONE_MMIO                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_FC_MODE_TWO_MMIO                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_FC_MODE_FOUR_MMIO                     MK_ENUM_CONST(3)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_RANGE                        23:21
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_MSB                  MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_IO2MEM_NO_FC                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_IO2MEM_FC                    MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_MEM2IO_NO_FC                 MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_MEM2IO_FC                    MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_MEM2MEM                      MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_RSVD                 MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_DMA_MODE_FIXED_PAT                    MK_ENUM_CONST(6)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_SHIFT                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_FIELD                 MK_FIELD_CONST(0x1f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_RANGE                 20:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_MSB                   MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_LSB                   MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_0                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_1                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_2                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_3                      MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_4                      MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_5                      MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_6                      MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_7                      MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_8                      MK_ENUM_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_9                      MK_ENUM_CONST(9)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_10                     MK_ENUM_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_11                     MK_ENUM_CONST(11)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_12                     MK_ENUM_CONST(12)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_13                     MK_ENUM_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_14                     MK_ENUM_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_CLIENT_15                     MK_ENUM_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_REQ_SEL_RSVD                  MK_ENUM_CONST(29)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IRQ_MASK_SHIFT                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IRQ_MASK_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IRQ_MASK_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IRQ_MASK_RANGE                        15:15
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IRQ_MASK_MSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IRQ_MASK_LSB                  MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IRQ_MASK_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IRQ_MASK_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IRQ_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IRQ_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IRQ_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IRQ_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IRQ_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IRQ_MASK_DISABLE                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_IRQ_MASK_ENABLE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_WEIGHT_SHIFT                  MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_WEIGHT_FIELD                  MK_FIELD_CONST(0xf, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_WEIGHT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_WEIGHT_RANGE                  13:10
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_WEIGHT_MSB                    MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_WEIGHT_LSB                    MK_SHIFT_CONST(10)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_WEIGHT_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_WEIGHT_DEFAULT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_WEIGHT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_WEIGHT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_WEIGHT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_WEIGHT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0_WEIGHT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0                       MK_ADDR_CONST(0x80004)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_SECURE                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_DUAL                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_SCR                   SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_SCRREG                        GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_WORD_COUNT                    0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_RESET_MASK                    MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_READ_MASK                     MK_MASK_CONST(0xdfb00000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_WRITE_MASK                    MK_MASK_CONST(0x40000000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_BSY_SHIFT                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_BSY_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_BSY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_BSY_RANGE                     31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_BSY_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_BSY_LSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_BSY_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_BSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_BSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_BSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_BSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_BSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_BSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_BSY_WAIT                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_BSY_ACTIVE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_ISE_EOC_SHIFT                 MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_ISE_EOC_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_ISE_EOC_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_ISE_EOC_RANGE                 30:30
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_ISE_EOC_MSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_ISE_EOC_LSB                   MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_ISE_EOC_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_ISE_EOC_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_ISE_EOC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_ISE_EOC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_ISE_EOC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_ISE_EOC_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_ISE_EOC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_ISE_EOC_NO_INTR                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_ISE_EOC_INTR                  MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_PING_PONG_STA_SHIFT                   MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_PING_PONG_STA_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_PING_PONG_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_PING_PONG_STA_RANGE                   28:28
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_PING_PONG_STA_MSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_PING_PONG_STA_LSB                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_PING_PONG_STA_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_PING_PONG_STA_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_PING_PONG_STA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_PING_PONG_STA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_PING_PONG_STA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_PING_PONG_STA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_PING_PONG_STA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_PING_PONG_STA_PING_INTR_STA                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_PING_PONG_STA_PONG_INTR_STA                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_DMA_ACTIVITY_SHIFT                    MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_DMA_ACTIVITY_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_DMA_ACTIVITY_RANGE                    27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_DMA_ACTIVITY_MSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_DMA_ACTIVITY_LSB                      MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_DMA_ACTIVITY_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_DMA_ACTIVITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_DMA_ACTIVITY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_DMA_ACTIVITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_DMA_ACTIVITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_DMA_ACTIVITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_DMA_ACTIVITY_IDLE                     MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_DMA_ACTIVITY_BUSY                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_SHIFT                   MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_RANGE                   26:26
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_MSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_LSB                     MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_PAUSE_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_RX_SHIFT                      MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_RX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_RX_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_RX_RANGE                      25:25
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_RX_MSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_RX_LSB                        MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_RX_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_RX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_RX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_TX_SHIFT                      MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_TX_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_TX_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_TX_RANGE                      24:24
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_TX_MSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_TX_LSB                        MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_TX_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_TX_NOT_ACTIVE                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_CHANNEL_TX_ACTIVE                     MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_IRQ_INTR_STA_SHIFT                    MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_IRQ_INTR_STA_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_IRQ_INTR_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_IRQ_INTR_STA_RANGE                    23:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_IRQ_INTR_STA_MSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_IRQ_INTR_STA_LSB                      MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_IRQ_INTR_STA_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_IRQ_INTR_STA_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_IRQ_INTR_STA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_IRQ_INTR_STA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_IRQ_INTR_STA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_IRQ_INTR_STA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_IRQ_INTR_STA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_IRQ_INTR_STA_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_IRQ_INTR_STA_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_TRIG_STA_SHIFT                        MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_TRIG_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_TRIG_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_TRIG_STA_RANGE                        21:21
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_TRIG_STA_MSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_TRIG_STA_LSB                  MK_SHIFT_CONST(21)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_TRIG_STA_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_TRIG_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_TRIG_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_TRIG_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_TRIG_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_TRIG_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_TRIG_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_TRIG_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_TRIG_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_INTR_STA_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_INTR_STA_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_INTR_STA_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_INTR_STA_RANGE                        20:20
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_INTR_STA_MSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_INTR_STA_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_INTR_STA_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_INTR_STA_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_INTR_STA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_INTR_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_INTR_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_INTR_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_INTR_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_INTR_STA_NOT_ACTIVE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0_INTR_STA_ACTIVE                       MK_ENUM_CONST(1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0                      MK_ADDR_CONST(0x80008)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_SCR                  SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_RESET_VAL                    MK_MASK_CONST(0x80000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_RESET_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_READ_MASK                    MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_WRITE_MASK                   MK_MASK_CONST(0x800fc000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_SHIFT                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_FIELD                   MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_RANGE                   31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_MSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_LSB                     MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_RESUME                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_DMA_ACTIVITY_PAUSE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_SHIFT                       MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_FIELD                       MK_FIELD_CONST(0x3f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_RANGE                       19:14
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_MSB                 MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_LSB                 MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_DEFAULT                     MK_MASK_CONST(0x20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_DEFAULT_MASK                        MK_MASK_CONST(0x3f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH0                 MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH1                 MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH2                 MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH3                 MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH4                 MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH5                 MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH6                 MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_CH7                 MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0_TRIG_SEL_RSVD                        MK_ENUM_CONST(32)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0                   MK_ADDR_CONST(0x8000c)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SCR                       SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0_SRC_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0                   MK_ADDR_CONST(0x80010)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_SCR                       SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_DST_PTR_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_DST_PTR_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_DST_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_DST_PTR_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_DST_PTR_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_DST_PTR_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_DST_PTR_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_DST_PTR_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_DST_PTR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_DST_PTR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_DST_PTR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_DST_PTR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0_DST_PTR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0                        MK_ADDR_CONST(0x80014)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_SCR                    SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_RESET_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_READ_MASK                      MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_WRITE_MASK                     MK_MASK_CONST(0xff00ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_SHIFT                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_RANGE                       23:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_MSB                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_LSB                 MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_DST_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_FIELD                       MK_FIELD_CONST(0xff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_RANGE                       7:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_MSB                 MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0_HI_SRC_PTR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0                    MK_ADDR_CONST(0x80018)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_SCR                        SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_RESET_VAL                  MK_MASK_CONST(0x3800000)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_SHIFT                 MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_FIELD                 MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_RANGE                 31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_LSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_DISABLE                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_DATA_SWAP_ENABLE                        MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_SHIFT                   MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_FIELD                   MK_FIELD_CONST(0x3f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_RANGE                   30:25
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_MSB                     MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_LSB                     MK_SHIFT_CONST(25)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_WOFFSET                 0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_DEFAULT                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_REQ_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_BURST_SHIFT                     MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_BURST_FIELD                     MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_BURST_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_BURST_RANGE                     24:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_BURST_MSB                       MK_SHIFT_CONST(24)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_BURST_LSB                       MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_BURST_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_BURST_DEFAULT                   MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_BURST_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_BURST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_BURST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_BURST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_BURST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_BURST_DMA_BURST_2WORDS                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_BURST_DMA_BURST_16WORDS                 MK_ENUM_CONST(3)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT                        MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_RANGE                        22:20
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_MSB                  MK_SHIFT_CONST(22)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_LSB                  MK_SHIFT_CONST(20)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP1_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT                        MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_FIELD                        MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_RANGE                        19:17
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_MSB                  MK_SHIFT_CONST(19)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_LSB                  MK_SHIFT_CONST(17)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_NO_WRAP                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_0N_32WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_64WORDS                      MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_128WORDS                     MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_256WORDS                     MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_512WORDS                     MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_1024WORDS                    MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_ADDR_WRAP0_WRAP_ON_2048WORDS                    MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_RANGE                     16:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_MSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_AXIID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_PROT_SHIFT                      MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_PROT_FIELD                      MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_PROT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_PROT_RANGE                      15:14
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_PROT_MSB                        MK_SHIFT_CONST(15)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_PROT_LSB                        MK_SHIFT_CONST(14)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_PROT_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_PROT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_PROT_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_PROT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_PROT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_PROT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_MC_PROT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID1_SHIFT                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID1_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID1_RANGE                    13:7
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID1_MSB                      MK_SHIFT_CONST(13)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID1_LSB                      MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID1_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID1_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID0_SHIFT                    MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID0_FIELD                    MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID0_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID0_RANGE                    6:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID0_MSB                      MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID0_LSB                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID0_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID0_DEFAULT_MASK                     MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0_STREAMID0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0                  MK_ADDR_CONST(0x8001c)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_SECURE                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_DUAL                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_SCR                      SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_SCRREG                   GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_WORD_COUNT                       0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_RESET_VAL                        MK_MASK_CONST(0x2381007f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_RESET_MASK                       MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_READ_MASK                        MK_MASK_CONST(0xff8701ff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_WRITE_MASK                       MK_MASK_CONST(0xff870180)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_SHIFT                    MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_FIELD                    MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_RANGE                    31:31
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_MSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_LSB                      MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_WOFFSET                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_DISABLE                  MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_DBL_BUF_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT                     MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_RANGE                     30:28
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_MSB                       MK_SHIFT_CONST(30)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_LSB                       MK_SHIFT_CONST(28)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT                   MK_MASK_CONST(0x2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_8                       MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_16                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BUS_WIDTH_BUS_WIDTH_32                      MK_ENUM_CONST(2)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT                     MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_FIELD                     MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_RANGE                     27:27
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_MSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_LSB                       MK_SHIFT_CONST(27)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_DISABLE                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_DATA_SWAP_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_SHIFT                 MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_FIELD                 MK_FIELD_CONST(0xf, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_RANGE                 26:23
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_MSB                   MK_SHIFT_CONST(26)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_LSB                   MK_SHIFT_CONST(23)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DEFAULT                       MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DEFAULT_MASK                  MK_MASK_CONST(0xf)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_1WORDS                      MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_2WORDS                      MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_4WORDS                      MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_8WORDS                      MK_ENUM_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_BURST_DMA_BURST_16WORDS                     MK_ENUM_CONST(15)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT                     MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_FIELD                     MK_FIELD_CONST(0x7, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_RANGE                     18:16
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_MSB                       MK_SHIFT_CONST(18)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_LSB                       MK_SHIFT_CONST(16)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT                   MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_NO_WRAP                   MK_ENUM_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_0N_1WORDS                    MK_ENUM_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_2WORDS                    MK_ENUM_CONST(2)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_4WORDS                    MK_ENUM_CONST(3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_8WORDS                    MK_ENUM_CONST(4)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_16WORDS                   MK_ENUM_CONST(5)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_32WORDS                   MK_ENUM_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_ADDR_WRAP_WRAP_ON_64WORDS                   MK_ENUM_CONST(7)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_SHIFT                  MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_FIELD                  MK_FIELD_CONST(0x3, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_RANGE                  8:7
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_MSB                    MK_SHIFT_CONST(8)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_LSB                    MK_SHIFT_CONST(7)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_WOFFSET                        0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_PROT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_FIELD                      MK_FIELD_CONST(0x7f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_RANGE                      6:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_MSB                        MK_SHIFT_CONST(6)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT                    MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0_MMIO_CHANNEL_SECURITY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0                    MK_ADDR_CONST(0x80020)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_SECURE                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_DUAL                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_SCR                        SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_SCRREG                     GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_WORD_COUNT                         0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_WCOUNT_SHIFT                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_WCOUNT_FIELD                       MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_WCOUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_WCOUNT_RANGE                       31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_WCOUNT_MSB                 MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_WCOUNT_LSB                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_WCOUNT_WOFFSET                     0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_WCOUNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_WCOUNT_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_WCOUNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_WCOUNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_WCOUNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0_WCOUNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0                      MK_ADDR_CONST(0x80024)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_SCR                  SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT                 MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_FIELD                 MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_RANGE                 31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_MSB                   MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_LSB                   MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_WOFFSET                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0_TRANSFER_COUNT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0                      MK_ADDR_CONST(0x80028)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_SECURE                       0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_DUAL                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_SCR                  SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_SCRREG                       GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_WORD_COUNT                   0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_FIELD                      MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_RANGE                      31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_MSB                        MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0_DMA_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x8002c
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0                   MK_ADDR_CONST(0x80030)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_SECURE                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_DUAL                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_SCR                       SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_SCRREG                    GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_WORD_COUNT                        0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_RANGE                        31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0_ERROR_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0                 MK_ADDR_CONST(0x80034)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_SECURE                  0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_DUAL                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_SCR                     SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_SCRREG                  GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_WORD_COUNT                      0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_SHIFT                     MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_FIELD                     MK_FIELD_CONST(0xffffffff, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_RANGE                     31:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_MSB                       MK_SHIFT_CONST(31)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_LSB                       MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_WOFFSET                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0_FIXED_PATTERN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0                        MK_ADDR_CONST(0x80038)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_SECURE                         0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_DUAL                   0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_SCR                    SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_SCRREG                         GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_WORD_COUNT                     0x1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_RESET_VAL                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_WRITE_MASK                     MK_MASK_CONST(0x3)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MC_PROT_1_SHIFT                        MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MC_PROT_1_FIELD                        MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MC_PROT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MC_PROT_1_RANGE                        1:1
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MC_PROT_1_MSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MC_PROT_1_LSB                  MK_SHIFT_CONST(1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MC_PROT_1_WOFFSET                      0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MC_PROT_1_DEFAULT                      MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MC_PROT_1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MC_PROT_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MC_PROT_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MC_PROT_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MC_PROT_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MMIO_PROT_1_SHIFT                      MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MMIO_PROT_1_FIELD                      MK_FIELD_CONST(0x1, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MMIO_PROT_1_SHIFT)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MMIO_PROT_1_RANGE                      0:0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MMIO_PROT_1_MSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MMIO_PROT_1_LSB                        MK_SHIFT_CONST(0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MMIO_PROT_1_WOFFSET                    0x0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MMIO_PROT_1_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MMIO_PROT_1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MMIO_PROT_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MMIO_PROT_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MMIO_PROT_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0_MMIO_PROT_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARGPCDMA_FLV_8CH_NON_SAFE_REGS(_op_) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_TX_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_REQUESTORS_RX_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_ERROR_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_MASKED_INTR_REG_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_INTR_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_INTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_PERI_ID_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_PERI_ID_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_PERI_ID_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_PERI_ID_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_PERI_ID_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_PERI_ID_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER1_PERI_ADDR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER2_PERI_ADDR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER3_PERI_ADDR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER4_PERI_ADDR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER5_PERI_ADDR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER6_PERI_ADDR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER7_PERI_ADDR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER8_PERI_ADDR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER9_PERI_ADDR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER10_PERI_ADDR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER11_PERI_ADDR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER12_PERI_ADDR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER13_PERI_ADDR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER14_PERI_ADDR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH1_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH2_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH3_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH4_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH5_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH6_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ICG_EN_OVERRIDE_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_ACTIVE_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH1_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH2_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH3_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH4_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH5_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH6_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_DMA_RO_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSRE_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SRC_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DST_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_HI_ADR_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MC_SEQ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_MMIO_SEQ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_WCOUNT_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_TRA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_FIXED_PAT_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_TZ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSRE_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SRC_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DST_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_HI_ADR_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MC_SEQ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_MMIO_SEQ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_WCOUNT_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_TRA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_FIXED_PAT_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_TZ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSRE_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SRC_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DST_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_HI_ADR_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MC_SEQ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_MMIO_SEQ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_WCOUNT_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_TRA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_FIXED_PAT_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_TZ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSRE_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SRC_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DST_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_HI_ADR_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MC_SEQ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_MMIO_SEQ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_WCOUNT_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_TRA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_FIXED_PAT_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_TZ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSRE_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SRC_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DST_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_HI_ADR_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MC_SEQ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_MMIO_SEQ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_WCOUNT_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_TRA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_FIXED_PAT_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_TZ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSRE_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SRC_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DST_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_HI_ADR_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MC_SEQ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_MMIO_SEQ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_WCOUNT_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_TRA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_FIXED_PAT_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_TZ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSRE_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SRC_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DST_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_HI_ADR_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MC_SEQ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_MMIO_SEQ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_WCOUNT_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_TRA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_FIXED_PAT_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_TZ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSRE_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SRC_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DST_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_HI_ADR_PTR_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MC_SEQ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_MMIO_SEQ_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_WCOUNT_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_TRA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_FIXED_PAT_0) \
+_op_(GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_TZ_0) \
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_GPCDMA_FLV_8CH_NON_SAFE_COMMON     0x00000000
+#define BASE_ADDRESS_GPCDMA_FLV_8CH_NON_SAFE_SCR        0x00000f00
+#define BASE_ADDRESS_GPCDMA_FLV_8CH_NON_SAFE_CHANNEL    0x00010000
+
+//
+// ARGPCDMA_FLV_8CH_NON_SAFE REGISTER BANKS
+//
+
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON0_FIRST_REG 0x0000 // GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON0_LAST_REG 0x0010 // GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_ERROR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON1_FIRST_REG 0x0018 // GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_TRIG_REG_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON1_LAST_REG 0x0028 // GPCDMA_FLV_8CH_NON_SAFE_COMMON_CHANNEL_REG_LOCK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON2_FIRST_REG 0x0080 // GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_PERI_ID_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON2_LAST_REG 0x009c // GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_PERI_ID_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON3_FIRST_REG 0x0100 // GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER0_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON3_LAST_REG 0x013c // GPCDMA_FLV_8CH_NON_SAFE_COMMON_PER15_PERI_ADDR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON4_FIRST_REG 0x0180 // GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID0_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON4_LAST_REG 0x019c // GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID0_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON5_FIRST_REG 0x0200 // GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID1_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON5_LAST_REG 0x021c // GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID1_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON6_FIRST_REG 0x0280 // GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID2_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON6_LAST_REG 0x029c // GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID2_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON7_FIRST_REG 0x0300 // GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH0_STREAM_ID3_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON7_LAST_REG 0x031c // GPCDMA_FLV_8CH_NON_SAFE_COMMON_CH7_STREAM_ID3_MASK_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON8_FIRST_REG 0x0380 // GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_COMMON8_LAST_REG 0x038c // GPCDMA_FLV_8CH_NON_SAFE_COMMON_COMMON_SPARE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR0_FIRST_REG 0x0f00 // GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH0_0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR0_LAST_REG 0x0f1c // GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_CH7_0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR1_FIRST_REG 0x0f80 // GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_TZ_0
+#define GPCDMA_FLV_8CH_NON_SAFE_SCR1_LAST_REG 0x0f88 // GPCDMA_FLV_8CH_NON_SAFE_SCR_SCR_HYPER_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL0_FIRST_REG 0x10000 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL0_LAST_REG 0x10028 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_DMA_WORD_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL1_FIRST_REG 0x10030 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ERR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL1_LAST_REG 0x10040 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_SPARE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL2_FIRST_REG 0x20000 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_CSR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL2_LAST_REG 0x20028 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_DMA_WORD_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL3_FIRST_REG 0x20030 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_ERR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL3_LAST_REG 0x20040 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH1_SPARE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL4_FIRST_REG 0x30000 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_CSR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL4_LAST_REG 0x30028 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_DMA_WORD_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL5_FIRST_REG 0x30030 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_ERR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL5_LAST_REG 0x30040 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH2_SPARE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL6_FIRST_REG 0x40000 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_CSR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL6_LAST_REG 0x40028 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_DMA_WORD_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL7_FIRST_REG 0x40030 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_ERR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL7_LAST_REG 0x40040 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH3_SPARE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL8_FIRST_REG 0x50000 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_CSR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL8_LAST_REG 0x50028 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_DMA_WORD_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL9_FIRST_REG 0x50030 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_ERR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL9_LAST_REG 0x50040 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH4_SPARE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL10_FIRST_REG 0x60000 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_CSR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL10_LAST_REG 0x60028 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_DMA_WORD_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL11_FIRST_REG 0x60030 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_ERR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL11_LAST_REG 0x60040 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH5_SPARE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL12_FIRST_REG 0x70000 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_CSR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL12_LAST_REG 0x70028 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_DMA_WORD_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL13_FIRST_REG 0x70030 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_ERR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL13_LAST_REG 0x70040 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH6_SPARE_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL14_FIRST_REG 0x80000 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_CSR_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL14_LAST_REG 0x80028 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_DMA_WORD_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL15_FIRST_REG 0x80030 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_ERR_STA_0
+#define GPCDMA_FLV_8CH_NON_SAFE_CHANNEL15_LAST_REG 0x80040 // GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH7_SPARE_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARGPCDMA_FLV_8CH_NON_SAFE_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argpio_aon_sw.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argpio_aon_sw.h
new file mode 100644
index 0000000..58fe038
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argpio_aon_sw.h
@@ -0,0 +1,11081 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARGPIO_AON_H_INC
+#define ARGPIO_AON_H_INC
+#define NV_MOBILE_ARGPIO_AON_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARGPIO_AON_H_SCRREG_NOMENCLATURE EXACT
+
+
+// Register GPIO_EE_ENABLE_CONFIG_00_0
+#define GPIO_EE_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x1000)
+#define GPIO_EE_ENABLE_CONFIG_00_0_SECURE                       0x0
+#define GPIO_EE_ENABLE_CONFIG_00_0_DUAL                         0x0
+#define GPIO_EE_ENABLE_CONFIG_00_0_SCR                  GPIO_EE_SCR_00_0
+#define GPIO_EE_ENABLE_CONFIG_00_0_SCRREG                       GPIO_EE_SCR_00_0
+#define GPIO_EE_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
+#define GPIO_EE_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
+#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_EE_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x1004)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_EE_SCR_00_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_EE_SCR_00_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INPUT_00_0
+#define GPIO_EE_INPUT_00_0                      MK_ADDR_CONST(0x1008)
+#define GPIO_EE_INPUT_00_0_SECURE                       0x0
+#define GPIO_EE_INPUT_00_0_DUAL                         0x0
+#define GPIO_EE_INPUT_00_0_SCR                  GPIO_EE_SCR_00_0
+#define GPIO_EE_INPUT_00_0_SCRREG                       GPIO_EE_SCR_00_0
+#define GPIO_EE_INPUT_00_0_WORD_COUNT                   0x1
+#define GPIO_EE_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_EE_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_EE_INPUT_00_0_GPIO_IN_RANGE                        0:0
+#define GPIO_EE_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_EE_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_OUTPUT_CONTROL_00_0
+#define GPIO_EE_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x100c)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_SECURE                      0x0
+#define GPIO_EE_OUTPUT_CONTROL_00_0_DUAL                        0x0
+#define GPIO_EE_OUTPUT_CONTROL_00_0_SCR                         GPIO_EE_SCR_00_0
+#define GPIO_EE_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_EE_SCR_00_0
+#define GPIO_EE_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
+#define GPIO_EE_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_EE_OUTPUT_VALUE_00_0
+#define GPIO_EE_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x1010)
+#define GPIO_EE_OUTPUT_VALUE_00_0_SECURE                        0x0
+#define GPIO_EE_OUTPUT_VALUE_00_0_DUAL                  0x0
+#define GPIO_EE_OUTPUT_VALUE_00_0_SCR                   GPIO_EE_SCR_00_0
+#define GPIO_EE_OUTPUT_VALUE_00_0_SCRREG                        GPIO_EE_SCR_00_0
+#define GPIO_EE_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
+#define GPIO_EE_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INTERRUPT_CLEAR_00_0
+#define GPIO_EE_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x1014)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_SECURE                     0x0
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_DUAL                       0x0
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_SCR                        GPIO_EE_SCR_00_0
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_EE_SCR_00_0
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1018
+
+// Reserved address 0x101c
+
+// Register GPIO_EE_ENABLE_CONFIG_01_0
+#define GPIO_EE_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x1020)
+#define GPIO_EE_ENABLE_CONFIG_01_0_SECURE                       0x0
+#define GPIO_EE_ENABLE_CONFIG_01_0_DUAL                         0x0
+#define GPIO_EE_ENABLE_CONFIG_01_0_SCR                  GPIO_EE_SCR_01_0
+#define GPIO_EE_ENABLE_CONFIG_01_0_SCRREG                       GPIO_EE_SCR_01_0
+#define GPIO_EE_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
+#define GPIO_EE_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
+#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_EE_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x1024)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_EE_SCR_01_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_EE_SCR_01_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INPUT_01_0
+#define GPIO_EE_INPUT_01_0                      MK_ADDR_CONST(0x1028)
+#define GPIO_EE_INPUT_01_0_SECURE                       0x0
+#define GPIO_EE_INPUT_01_0_DUAL                         0x0
+#define GPIO_EE_INPUT_01_0_SCR                  GPIO_EE_SCR_01_0
+#define GPIO_EE_INPUT_01_0_SCRREG                       GPIO_EE_SCR_01_0
+#define GPIO_EE_INPUT_01_0_WORD_COUNT                   0x1
+#define GPIO_EE_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_EE_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_EE_INPUT_01_0_GPIO_IN_RANGE                        0:0
+#define GPIO_EE_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_EE_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_OUTPUT_CONTROL_01_0
+#define GPIO_EE_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x102c)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_SECURE                      0x0
+#define GPIO_EE_OUTPUT_CONTROL_01_0_DUAL                        0x0
+#define GPIO_EE_OUTPUT_CONTROL_01_0_SCR                         GPIO_EE_SCR_01_0
+#define GPIO_EE_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_EE_SCR_01_0
+#define GPIO_EE_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
+#define GPIO_EE_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_EE_OUTPUT_VALUE_01_0
+#define GPIO_EE_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x1030)
+#define GPIO_EE_OUTPUT_VALUE_01_0_SECURE                        0x0
+#define GPIO_EE_OUTPUT_VALUE_01_0_DUAL                  0x0
+#define GPIO_EE_OUTPUT_VALUE_01_0_SCR                   GPIO_EE_SCR_01_0
+#define GPIO_EE_OUTPUT_VALUE_01_0_SCRREG                        GPIO_EE_SCR_01_0
+#define GPIO_EE_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
+#define GPIO_EE_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INTERRUPT_CLEAR_01_0
+#define GPIO_EE_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x1034)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_SECURE                     0x0
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_DUAL                       0x0
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_SCR                        GPIO_EE_SCR_01_0
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_EE_SCR_01_0
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1038
+
+// Reserved address 0x103c
+
+// Register GPIO_EE_ENABLE_CONFIG_02_0
+#define GPIO_EE_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x1040)
+#define GPIO_EE_ENABLE_CONFIG_02_0_SECURE                       0x0
+#define GPIO_EE_ENABLE_CONFIG_02_0_DUAL                         0x0
+#define GPIO_EE_ENABLE_CONFIG_02_0_SCR                  GPIO_EE_SCR_02_0
+#define GPIO_EE_ENABLE_CONFIG_02_0_SCRREG                       GPIO_EE_SCR_02_0
+#define GPIO_EE_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
+#define GPIO_EE_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
+#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_EE_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x1044)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_EE_SCR_02_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_EE_SCR_02_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INPUT_02_0
+#define GPIO_EE_INPUT_02_0                      MK_ADDR_CONST(0x1048)
+#define GPIO_EE_INPUT_02_0_SECURE                       0x0
+#define GPIO_EE_INPUT_02_0_DUAL                         0x0
+#define GPIO_EE_INPUT_02_0_SCR                  GPIO_EE_SCR_02_0
+#define GPIO_EE_INPUT_02_0_SCRREG                       GPIO_EE_SCR_02_0
+#define GPIO_EE_INPUT_02_0_WORD_COUNT                   0x1
+#define GPIO_EE_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_EE_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_EE_INPUT_02_0_GPIO_IN_RANGE                        0:0
+#define GPIO_EE_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_EE_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_OUTPUT_CONTROL_02_0
+#define GPIO_EE_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x104c)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_SECURE                      0x0
+#define GPIO_EE_OUTPUT_CONTROL_02_0_DUAL                        0x0
+#define GPIO_EE_OUTPUT_CONTROL_02_0_SCR                         GPIO_EE_SCR_02_0
+#define GPIO_EE_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_EE_SCR_02_0
+#define GPIO_EE_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
+#define GPIO_EE_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_EE_OUTPUT_VALUE_02_0
+#define GPIO_EE_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x1050)
+#define GPIO_EE_OUTPUT_VALUE_02_0_SECURE                        0x0
+#define GPIO_EE_OUTPUT_VALUE_02_0_DUAL                  0x0
+#define GPIO_EE_OUTPUT_VALUE_02_0_SCR                   GPIO_EE_SCR_02_0
+#define GPIO_EE_OUTPUT_VALUE_02_0_SCRREG                        GPIO_EE_SCR_02_0
+#define GPIO_EE_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
+#define GPIO_EE_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INTERRUPT_CLEAR_02_0
+#define GPIO_EE_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x1054)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_SECURE                     0x0
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_DUAL                       0x0
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_SCR                        GPIO_EE_SCR_02_0
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_EE_SCR_02_0
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1058
+
+// Reserved address 0x105c
+
+// Register GPIO_EE_ENABLE_CONFIG_03_0
+#define GPIO_EE_ENABLE_CONFIG_03_0                      MK_ADDR_CONST(0x1060)
+#define GPIO_EE_ENABLE_CONFIG_03_0_SECURE                       0x0
+#define GPIO_EE_ENABLE_CONFIG_03_0_DUAL                         0x0
+#define GPIO_EE_ENABLE_CONFIG_03_0_SCR                  GPIO_EE_SCR_03_0
+#define GPIO_EE_ENABLE_CONFIG_03_0_SCRREG                       GPIO_EE_SCR_03_0
+#define GPIO_EE_ENABLE_CONFIG_03_0_WORD_COUNT                   0x1
+#define GPIO_EE_ENABLE_CONFIG_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_03_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_RANGE                 1:1
+#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_EE_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0                 MK_ADDR_CONST(0x1064)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_SECURE                  0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DUAL                    0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_SCR                     GPIO_EE_SCR_03_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_SCRREG                  GPIO_EE_SCR_03_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                      0x1
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INPUT_03_0
+#define GPIO_EE_INPUT_03_0                      MK_ADDR_CONST(0x1068)
+#define GPIO_EE_INPUT_03_0_SECURE                       0x0
+#define GPIO_EE_INPUT_03_0_DUAL                         0x0
+#define GPIO_EE_INPUT_03_0_SCR                  GPIO_EE_SCR_03_0
+#define GPIO_EE_INPUT_03_0_SCRREG                       GPIO_EE_SCR_03_0
+#define GPIO_EE_INPUT_03_0_WORD_COUNT                   0x1
+#define GPIO_EE_INPUT_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_03_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_INPUT_03_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_03_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_03_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_EE_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_EE_INPUT_03_0_GPIO_IN_RANGE                        0:0
+#define GPIO_EE_INPUT_03_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_03_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_03_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_EE_INPUT_03_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_03_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_03_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_OUTPUT_CONTROL_03_0
+#define GPIO_EE_OUTPUT_CONTROL_03_0                     MK_ADDR_CONST(0x106c)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_SECURE                      0x0
+#define GPIO_EE_OUTPUT_CONTROL_03_0_DUAL                        0x0
+#define GPIO_EE_OUTPUT_CONTROL_03_0_SCR                         GPIO_EE_SCR_03_0
+#define GPIO_EE_OUTPUT_CONTROL_03_0_SCRREG                      GPIO_EE_SCR_03_0
+#define GPIO_EE_OUTPUT_CONTROL_03_0_WORD_COUNT                  0x1
+#define GPIO_EE_OUTPUT_CONTROL_03_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_EE_OUTPUT_VALUE_03_0
+#define GPIO_EE_OUTPUT_VALUE_03_0                       MK_ADDR_CONST(0x1070)
+#define GPIO_EE_OUTPUT_VALUE_03_0_SECURE                        0x0
+#define GPIO_EE_OUTPUT_VALUE_03_0_DUAL                  0x0
+#define GPIO_EE_OUTPUT_VALUE_03_0_SCR                   GPIO_EE_SCR_03_0
+#define GPIO_EE_OUTPUT_VALUE_03_0_SCRREG                        GPIO_EE_SCR_03_0
+#define GPIO_EE_OUTPUT_VALUE_03_0_WORD_COUNT                    0x1
+#define GPIO_EE_OUTPUT_VALUE_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_03_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_03_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INTERRUPT_CLEAR_03_0
+#define GPIO_EE_INTERRUPT_CLEAR_03_0                    MK_ADDR_CONST(0x1074)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_SECURE                     0x0
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_DUAL                       0x0
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_SCR                        GPIO_EE_SCR_03_0
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_SCRREG                     GPIO_EE_SCR_03_0
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_WORD_COUNT                         0x1
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1078
+
+// Reserved address 0x107c
+
+// Register GPIO_EE_ENABLE_CONFIG_04_0
+#define GPIO_EE_ENABLE_CONFIG_04_0                      MK_ADDR_CONST(0x1080)
+#define GPIO_EE_ENABLE_CONFIG_04_0_SECURE                       0x0
+#define GPIO_EE_ENABLE_CONFIG_04_0_DUAL                         0x0
+#define GPIO_EE_ENABLE_CONFIG_04_0_SCR                  GPIO_EE_SCR_04_0
+#define GPIO_EE_ENABLE_CONFIG_04_0_SCRREG                       GPIO_EE_SCR_04_0
+#define GPIO_EE_ENABLE_CONFIG_04_0_WORD_COUNT                   0x1
+#define GPIO_EE_ENABLE_CONFIG_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_04_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_RANGE                 1:1
+#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_EE_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0                 MK_ADDR_CONST(0x1084)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_SECURE                  0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DUAL                    0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_SCR                     GPIO_EE_SCR_04_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_SCRREG                  GPIO_EE_SCR_04_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                      0x1
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INPUT_04_0
+#define GPIO_EE_INPUT_04_0                      MK_ADDR_CONST(0x1088)
+#define GPIO_EE_INPUT_04_0_SECURE                       0x0
+#define GPIO_EE_INPUT_04_0_DUAL                         0x0
+#define GPIO_EE_INPUT_04_0_SCR                  GPIO_EE_SCR_04_0
+#define GPIO_EE_INPUT_04_0_SCRREG                       GPIO_EE_SCR_04_0
+#define GPIO_EE_INPUT_04_0_WORD_COUNT                   0x1
+#define GPIO_EE_INPUT_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_04_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_INPUT_04_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_04_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_04_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_EE_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_EE_INPUT_04_0_GPIO_IN_RANGE                        0:0
+#define GPIO_EE_INPUT_04_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_04_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_04_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_EE_INPUT_04_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_04_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_04_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_OUTPUT_CONTROL_04_0
+#define GPIO_EE_OUTPUT_CONTROL_04_0                     MK_ADDR_CONST(0x108c)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_SECURE                      0x0
+#define GPIO_EE_OUTPUT_CONTROL_04_0_DUAL                        0x0
+#define GPIO_EE_OUTPUT_CONTROL_04_0_SCR                         GPIO_EE_SCR_04_0
+#define GPIO_EE_OUTPUT_CONTROL_04_0_SCRREG                      GPIO_EE_SCR_04_0
+#define GPIO_EE_OUTPUT_CONTROL_04_0_WORD_COUNT                  0x1
+#define GPIO_EE_OUTPUT_CONTROL_04_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_EE_OUTPUT_VALUE_04_0
+#define GPIO_EE_OUTPUT_VALUE_04_0                       MK_ADDR_CONST(0x1090)
+#define GPIO_EE_OUTPUT_VALUE_04_0_SECURE                        0x0
+#define GPIO_EE_OUTPUT_VALUE_04_0_DUAL                  0x0
+#define GPIO_EE_OUTPUT_VALUE_04_0_SCR                   GPIO_EE_SCR_04_0
+#define GPIO_EE_OUTPUT_VALUE_04_0_SCRREG                        GPIO_EE_SCR_04_0
+#define GPIO_EE_OUTPUT_VALUE_04_0_WORD_COUNT                    0x1
+#define GPIO_EE_OUTPUT_VALUE_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_04_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_04_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INTERRUPT_CLEAR_04_0
+#define GPIO_EE_INTERRUPT_CLEAR_04_0                    MK_ADDR_CONST(0x1094)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_SECURE                     0x0
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_DUAL                       0x0
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_SCR                        GPIO_EE_SCR_04_0
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_SCRREG                     GPIO_EE_SCR_04_0
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_WORD_COUNT                         0x1
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1098
+
+// Reserved address 0x109c
+
+// Register GPIO_EE_ENABLE_CONFIG_05_0
+#define GPIO_EE_ENABLE_CONFIG_05_0                      MK_ADDR_CONST(0x10a0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_SECURE                       0x0
+#define GPIO_EE_ENABLE_CONFIG_05_0_DUAL                         0x0
+#define GPIO_EE_ENABLE_CONFIG_05_0_SCR                  GPIO_EE_SCR_05_0
+#define GPIO_EE_ENABLE_CONFIG_05_0_SCRREG                       GPIO_EE_SCR_05_0
+#define GPIO_EE_ENABLE_CONFIG_05_0_WORD_COUNT                   0x1
+#define GPIO_EE_ENABLE_CONFIG_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_05_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_RANGE                 1:1
+#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_EE_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0                 MK_ADDR_CONST(0x10a4)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_SECURE                  0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DUAL                    0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_SCR                     GPIO_EE_SCR_05_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_SCRREG                  GPIO_EE_SCR_05_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                      0x1
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INPUT_05_0
+#define GPIO_EE_INPUT_05_0                      MK_ADDR_CONST(0x10a8)
+#define GPIO_EE_INPUT_05_0_SECURE                       0x0
+#define GPIO_EE_INPUT_05_0_DUAL                         0x0
+#define GPIO_EE_INPUT_05_0_SCR                  GPIO_EE_SCR_05_0
+#define GPIO_EE_INPUT_05_0_SCRREG                       GPIO_EE_SCR_05_0
+#define GPIO_EE_INPUT_05_0_WORD_COUNT                   0x1
+#define GPIO_EE_INPUT_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_05_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_INPUT_05_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_05_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_05_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_EE_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_EE_INPUT_05_0_GPIO_IN_RANGE                        0:0
+#define GPIO_EE_INPUT_05_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_05_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_05_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_EE_INPUT_05_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_05_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_05_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_OUTPUT_CONTROL_05_0
+#define GPIO_EE_OUTPUT_CONTROL_05_0                     MK_ADDR_CONST(0x10ac)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_SECURE                      0x0
+#define GPIO_EE_OUTPUT_CONTROL_05_0_DUAL                        0x0
+#define GPIO_EE_OUTPUT_CONTROL_05_0_SCR                         GPIO_EE_SCR_05_0
+#define GPIO_EE_OUTPUT_CONTROL_05_0_SCRREG                      GPIO_EE_SCR_05_0
+#define GPIO_EE_OUTPUT_CONTROL_05_0_WORD_COUNT                  0x1
+#define GPIO_EE_OUTPUT_CONTROL_05_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_EE_OUTPUT_VALUE_05_0
+#define GPIO_EE_OUTPUT_VALUE_05_0                       MK_ADDR_CONST(0x10b0)
+#define GPIO_EE_OUTPUT_VALUE_05_0_SECURE                        0x0
+#define GPIO_EE_OUTPUT_VALUE_05_0_DUAL                  0x0
+#define GPIO_EE_OUTPUT_VALUE_05_0_SCR                   GPIO_EE_SCR_05_0
+#define GPIO_EE_OUTPUT_VALUE_05_0_SCRREG                        GPIO_EE_SCR_05_0
+#define GPIO_EE_OUTPUT_VALUE_05_0_WORD_COUNT                    0x1
+#define GPIO_EE_OUTPUT_VALUE_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_05_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_05_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INTERRUPT_CLEAR_05_0
+#define GPIO_EE_INTERRUPT_CLEAR_05_0                    MK_ADDR_CONST(0x10b4)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_SECURE                     0x0
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_DUAL                       0x0
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_SCR                        GPIO_EE_SCR_05_0
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_SCRREG                     GPIO_EE_SCR_05_0
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_WORD_COUNT                         0x1
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10b8
+
+// Reserved address 0x10bc
+
+// Register GPIO_EE_ENABLE_CONFIG_06_0
+#define GPIO_EE_ENABLE_CONFIG_06_0                      MK_ADDR_CONST(0x10c0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_SECURE                       0x0
+#define GPIO_EE_ENABLE_CONFIG_06_0_DUAL                         0x0
+#define GPIO_EE_ENABLE_CONFIG_06_0_SCR                  GPIO_EE_SCR_06_0
+#define GPIO_EE_ENABLE_CONFIG_06_0_SCRREG                       GPIO_EE_SCR_06_0
+#define GPIO_EE_ENABLE_CONFIG_06_0_WORD_COUNT                   0x1
+#define GPIO_EE_ENABLE_CONFIG_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_06_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_RANGE                 1:1
+#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_EE_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0                 MK_ADDR_CONST(0x10c4)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_SECURE                  0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DUAL                    0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_SCR                     GPIO_EE_SCR_06_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_SCRREG                  GPIO_EE_SCR_06_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                      0x1
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INPUT_06_0
+#define GPIO_EE_INPUT_06_0                      MK_ADDR_CONST(0x10c8)
+#define GPIO_EE_INPUT_06_0_SECURE                       0x0
+#define GPIO_EE_INPUT_06_0_DUAL                         0x0
+#define GPIO_EE_INPUT_06_0_SCR                  GPIO_EE_SCR_06_0
+#define GPIO_EE_INPUT_06_0_SCRREG                       GPIO_EE_SCR_06_0
+#define GPIO_EE_INPUT_06_0_WORD_COUNT                   0x1
+#define GPIO_EE_INPUT_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_06_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_INPUT_06_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_06_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_06_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_EE_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_EE_INPUT_06_0_GPIO_IN_RANGE                        0:0
+#define GPIO_EE_INPUT_06_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_06_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_06_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_EE_INPUT_06_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_06_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_06_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_OUTPUT_CONTROL_06_0
+#define GPIO_EE_OUTPUT_CONTROL_06_0                     MK_ADDR_CONST(0x10cc)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_SECURE                      0x0
+#define GPIO_EE_OUTPUT_CONTROL_06_0_DUAL                        0x0
+#define GPIO_EE_OUTPUT_CONTROL_06_0_SCR                         GPIO_EE_SCR_06_0
+#define GPIO_EE_OUTPUT_CONTROL_06_0_SCRREG                      GPIO_EE_SCR_06_0
+#define GPIO_EE_OUTPUT_CONTROL_06_0_WORD_COUNT                  0x1
+#define GPIO_EE_OUTPUT_CONTROL_06_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_EE_OUTPUT_VALUE_06_0
+#define GPIO_EE_OUTPUT_VALUE_06_0                       MK_ADDR_CONST(0x10d0)
+#define GPIO_EE_OUTPUT_VALUE_06_0_SECURE                        0x0
+#define GPIO_EE_OUTPUT_VALUE_06_0_DUAL                  0x0
+#define GPIO_EE_OUTPUT_VALUE_06_0_SCR                   GPIO_EE_SCR_06_0
+#define GPIO_EE_OUTPUT_VALUE_06_0_SCRREG                        GPIO_EE_SCR_06_0
+#define GPIO_EE_OUTPUT_VALUE_06_0_WORD_COUNT                    0x1
+#define GPIO_EE_OUTPUT_VALUE_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_06_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_06_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INTERRUPT_CLEAR_06_0
+#define GPIO_EE_INTERRUPT_CLEAR_06_0                    MK_ADDR_CONST(0x10d4)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_SECURE                     0x0
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_DUAL                       0x0
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_SCR                        GPIO_EE_SCR_06_0
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_SCRREG                     GPIO_EE_SCR_06_0
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_WORD_COUNT                         0x1
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10d8
+
+// Reserved address 0x10dc
+
+// Register GPIO_EE_ENABLE_CONFIG_07_0
+#define GPIO_EE_ENABLE_CONFIG_07_0                      MK_ADDR_CONST(0x10e0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_SECURE                       0x0
+#define GPIO_EE_ENABLE_CONFIG_07_0_DUAL                         0x0
+#define GPIO_EE_ENABLE_CONFIG_07_0_SCR                  GPIO_EE_SCR_07_0
+#define GPIO_EE_ENABLE_CONFIG_07_0_SCRREG                       GPIO_EE_SCR_07_0
+#define GPIO_EE_ENABLE_CONFIG_07_0_WORD_COUNT                   0x1
+#define GPIO_EE_ENABLE_CONFIG_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_07_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_RANGE                 1:1
+#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_EE_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_EE_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0                 MK_ADDR_CONST(0x10e4)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_SECURE                  0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DUAL                    0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_SCR                     GPIO_EE_SCR_07_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_SCRREG                  GPIO_EE_SCR_07_0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                      0x1
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_EE_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INPUT_07_0
+#define GPIO_EE_INPUT_07_0                      MK_ADDR_CONST(0x10e8)
+#define GPIO_EE_INPUT_07_0_SECURE                       0x0
+#define GPIO_EE_INPUT_07_0_DUAL                         0x0
+#define GPIO_EE_INPUT_07_0_SCR                  GPIO_EE_SCR_07_0
+#define GPIO_EE_INPUT_07_0_SCRREG                       GPIO_EE_SCR_07_0
+#define GPIO_EE_INPUT_07_0_WORD_COUNT                   0x1
+#define GPIO_EE_INPUT_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_07_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_INPUT_07_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_07_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_07_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_EE_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_EE_INPUT_07_0_GPIO_IN_RANGE                        0:0
+#define GPIO_EE_INPUT_07_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_07_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_EE_INPUT_07_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_EE_INPUT_07_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_07_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_07_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_OUTPUT_CONTROL_07_0
+#define GPIO_EE_OUTPUT_CONTROL_07_0                     MK_ADDR_CONST(0x10ec)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_SECURE                      0x0
+#define GPIO_EE_OUTPUT_CONTROL_07_0_DUAL                        0x0
+#define GPIO_EE_OUTPUT_CONTROL_07_0_SCR                         GPIO_EE_SCR_07_0
+#define GPIO_EE_OUTPUT_CONTROL_07_0_SCRREG                      GPIO_EE_SCR_07_0
+#define GPIO_EE_OUTPUT_CONTROL_07_0_WORD_COUNT                  0x1
+#define GPIO_EE_OUTPUT_CONTROL_07_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_EE_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_EE_OUTPUT_VALUE_07_0
+#define GPIO_EE_OUTPUT_VALUE_07_0                       MK_ADDR_CONST(0x10f0)
+#define GPIO_EE_OUTPUT_VALUE_07_0_SECURE                        0x0
+#define GPIO_EE_OUTPUT_VALUE_07_0_DUAL                  0x0
+#define GPIO_EE_OUTPUT_VALUE_07_0_SCR                   GPIO_EE_SCR_07_0
+#define GPIO_EE_OUTPUT_VALUE_07_0_SCRREG                        GPIO_EE_SCR_07_0
+#define GPIO_EE_OUTPUT_VALUE_07_0_WORD_COUNT                    0x1
+#define GPIO_EE_OUTPUT_VALUE_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_07_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_07_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_EE_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INTERRUPT_CLEAR_07_0
+#define GPIO_EE_INTERRUPT_CLEAR_07_0                    MK_ADDR_CONST(0x10f4)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_SECURE                     0x0
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_DUAL                       0x0
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_SCR                        GPIO_EE_SCR_07_0
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_SCRREG                     GPIO_EE_SCR_07_0
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_WORD_COUNT                         0x1
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_EE_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10f8
+
+// Reserved address 0x10fc
+
+// Register GPIO_EE_INTERRUPT_STATUS_G0_0
+#define GPIO_EE_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x1100)
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_SECURE                    0x0
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_DUAL                      0x0
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_SCR                       0
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_SCRREG                    0
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INTERRUPT_STATUS_G1_0
+#define GPIO_EE_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x1104)
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_SECURE                    0x0
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_DUAL                      0x0
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_SCR                       0
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_SCRREG                    0
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INTERRUPT_STATUS_G2_0
+#define GPIO_EE_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x1108)
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_SECURE                    0x0
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_DUAL                      0x0
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_SCR                       0
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_SCRREG                    0
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INTERRUPT_STATUS_G3_0
+#define GPIO_EE_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x110c)
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_SECURE                    0x0
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_DUAL                      0x0
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_SCR                       0
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_SCRREG                    0
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INTERRUPT_STATUS_G4_0
+#define GPIO_EE_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x1110)
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_SECURE                    0x0
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_DUAL                      0x0
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_SCR                       0
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_SCRREG                    0
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INTERRUPT_STATUS_G5_0
+#define GPIO_EE_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x1114)
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_SECURE                    0x0
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_DUAL                      0x0
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_SCR                       0
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_SCRREG                    0
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INTERRUPT_STATUS_G6_0
+#define GPIO_EE_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x1118)
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_SECURE                    0x0
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_DUAL                      0x0
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_SCR                       0
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_SCRREG                    0
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_EE_INTERRUPT_STATUS_G7_0
+#define GPIO_EE_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x111c)
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_SECURE                    0x0
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_DUAL                      0x0
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_SCR                       0
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_SCRREG                    0
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_EE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x1120
+
+// Reserved address 0x1124
+
+// Reserved address 0x1128
+
+// Reserved address 0x112c
+
+// Reserved address 0x1130
+
+// Reserved address 0x1134
+
+// Reserved address 0x1138
+
+// Reserved address 0x113c
+
+// Reserved address 0x1140
+
+// Reserved address 0x1144
+
+// Reserved address 0x1148
+
+// Reserved address 0x114c
+
+// Reserved address 0x1150
+
+// Reserved address 0x1154
+
+// Reserved address 0x1158
+
+// Reserved address 0x115c
+
+// Reserved address 0x1160
+
+// Reserved address 0x1164
+
+// Reserved address 0x1168
+
+// Reserved address 0x116c
+
+// Reserved address 0x1170
+
+// Reserved address 0x1174
+
+// Reserved address 0x1178
+
+// Reserved address 0x117c
+
+// Reserved address 0x1180
+
+// Reserved address 0x1184
+
+// Reserved address 0x1188
+
+// Reserved address 0x118c
+
+// Reserved address 0x1190
+
+// Reserved address 0x1194
+
+// Reserved address 0x1198
+
+// Reserved address 0x119c
+
+// Reserved address 0x11a0
+
+// Reserved address 0x11a4
+
+// Reserved address 0x11a8
+
+// Reserved address 0x11ac
+
+// Reserved address 0x11b0
+
+// Reserved address 0x11b4
+
+// Reserved address 0x11b8
+
+// Reserved address 0x11bc
+
+// Reserved address 0x11c0
+
+// Reserved address 0x11c4
+
+// Reserved address 0x11c8
+
+// Reserved address 0x11cc
+
+// Reserved address 0x11d0
+
+// Reserved address 0x11d4
+
+// Reserved address 0x11d8
+
+// Reserved address 0x11dc
+
+// Reserved address 0x11e0
+
+// Reserved address 0x11e4
+
+// Reserved address 0x11e8
+
+// Reserved address 0x11ec
+
+// Reserved address 0x11f0
+
+// Reserved address 0x11f4
+
+// Reserved address 0x11f8
+
+// Reserved address 0x11fc
+
+// Register GPIO_GG_ENABLE_CONFIG_00_0
+#define GPIO_GG_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x1200)
+#define GPIO_GG_ENABLE_CONFIG_00_0_SECURE                       0x0
+#define GPIO_GG_ENABLE_CONFIG_00_0_DUAL                         0x0
+#define GPIO_GG_ENABLE_CONFIG_00_0_SCR                  GPIO_GG_SCR_00_0
+#define GPIO_GG_ENABLE_CONFIG_00_0_SCRREG                       GPIO_GG_SCR_00_0
+#define GPIO_GG_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
+#define GPIO_GG_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_GG_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_GG_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
+#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_GG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_GG_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x1204)
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_GG_SCR_00_0
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_GG_SCR_00_0
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_GG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_GG_INPUT_00_0
+#define GPIO_GG_INPUT_00_0                      MK_ADDR_CONST(0x1208)
+#define GPIO_GG_INPUT_00_0_SECURE                       0x0
+#define GPIO_GG_INPUT_00_0_DUAL                         0x0
+#define GPIO_GG_INPUT_00_0_SCR                  GPIO_GG_SCR_00_0
+#define GPIO_GG_INPUT_00_0_SCRREG                       GPIO_GG_SCR_00_0
+#define GPIO_GG_INPUT_00_0_WORD_COUNT                   0x1
+#define GPIO_GG_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_GG_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_GG_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_GG_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_GG_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_GG_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_GG_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_GG_INPUT_00_0_GPIO_IN_RANGE                        0:0
+#define GPIO_GG_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_GG_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_GG_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_GG_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_GG_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_GG_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_GG_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_GG_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_GG_OUTPUT_CONTROL_00_0
+#define GPIO_GG_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x120c)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_SECURE                      0x0
+#define GPIO_GG_OUTPUT_CONTROL_00_0_DUAL                        0x0
+#define GPIO_GG_OUTPUT_CONTROL_00_0_SCR                         GPIO_GG_SCR_00_0
+#define GPIO_GG_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_GG_SCR_00_0
+#define GPIO_GG_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
+#define GPIO_GG_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_GG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_GG_OUTPUT_VALUE_00_0
+#define GPIO_GG_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x1210)
+#define GPIO_GG_OUTPUT_VALUE_00_0_SECURE                        0x0
+#define GPIO_GG_OUTPUT_VALUE_00_0_DUAL                  0x0
+#define GPIO_GG_OUTPUT_VALUE_00_0_SCR                   GPIO_GG_SCR_00_0
+#define GPIO_GG_OUTPUT_VALUE_00_0_SCRREG                        GPIO_GG_SCR_00_0
+#define GPIO_GG_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
+#define GPIO_GG_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_GG_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_GG_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_GG_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_GG_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_GG_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_GG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_GG_INTERRUPT_CLEAR_00_0
+#define GPIO_GG_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x1214)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_SECURE                     0x0
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_DUAL                       0x0
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_SCR                        GPIO_GG_SCR_00_0
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_GG_SCR_00_0
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_GG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1218
+
+// Reserved address 0x121c
+
+// Reserved address 0x1220
+
+// Reserved address 0x1224
+
+// Reserved address 0x1228
+
+// Reserved address 0x122c
+
+// Reserved address 0x1230
+
+// Reserved address 0x1234
+
+// Reserved address 0x1238
+
+// Reserved address 0x123c
+
+// Reserved address 0x1240
+
+// Reserved address 0x1244
+
+// Reserved address 0x1248
+
+// Reserved address 0x124c
+
+// Reserved address 0x1250
+
+// Reserved address 0x1254
+
+// Reserved address 0x1258
+
+// Reserved address 0x125c
+
+// Reserved address 0x1260
+
+// Reserved address 0x1264
+
+// Reserved address 0x1268
+
+// Reserved address 0x126c
+
+// Reserved address 0x1270
+
+// Reserved address 0x1274
+
+// Reserved address 0x1278
+
+// Reserved address 0x127c
+
+// Reserved address 0x1280
+
+// Reserved address 0x1284
+
+// Reserved address 0x1288
+
+// Reserved address 0x128c
+
+// Reserved address 0x1290
+
+// Reserved address 0x1294
+
+// Reserved address 0x1298
+
+// Reserved address 0x129c
+
+// Reserved address 0x12a0
+
+// Reserved address 0x12a4
+
+// Reserved address 0x12a8
+
+// Reserved address 0x12ac
+
+// Reserved address 0x12b0
+
+// Reserved address 0x12b4
+
+// Reserved address 0x12b8
+
+// Reserved address 0x12bc
+
+// Reserved address 0x12c0
+
+// Reserved address 0x12c4
+
+// Reserved address 0x12c8
+
+// Reserved address 0x12cc
+
+// Reserved address 0x12d0
+
+// Reserved address 0x12d4
+
+// Reserved address 0x12d8
+
+// Reserved address 0x12dc
+
+// Reserved address 0x12e0
+
+// Reserved address 0x12e4
+
+// Reserved address 0x12e8
+
+// Reserved address 0x12ec
+
+// Reserved address 0x12f0
+
+// Reserved address 0x12f4
+
+// Reserved address 0x12f8
+
+// Reserved address 0x12fc
+
+// Register GPIO_GG_INTERRUPT_STATUS_G0_0
+#define GPIO_GG_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x1300)
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_SECURE                    0x0
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_DUAL                      0x0
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_SCR                       0
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_SCRREG                    0
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       0:0
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_GG_INTERRUPT_STATUS_G1_0
+#define GPIO_GG_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x1304)
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_SECURE                    0x0
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_DUAL                      0x0
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_SCR                       0
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_SCRREG                    0
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       0:0
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_GG_INTERRUPT_STATUS_G2_0
+#define GPIO_GG_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x1308)
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_SECURE                    0x0
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_DUAL                      0x0
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_SCR                       0
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_SCRREG                    0
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       0:0
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_GG_INTERRUPT_STATUS_G3_0
+#define GPIO_GG_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x130c)
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_SECURE                    0x0
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_DUAL                      0x0
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_SCR                       0
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_SCRREG                    0
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       0:0
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_GG_INTERRUPT_STATUS_G4_0
+#define GPIO_GG_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x1310)
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_SECURE                    0x0
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_DUAL                      0x0
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_SCR                       0
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_SCRREG                    0
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       0:0
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_GG_INTERRUPT_STATUS_G5_0
+#define GPIO_GG_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x1314)
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_SECURE                    0x0
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_DUAL                      0x0
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_SCR                       0
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_SCRREG                    0
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       0:0
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_GG_INTERRUPT_STATUS_G6_0
+#define GPIO_GG_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x1318)
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_SECURE                    0x0
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_DUAL                      0x0
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_SCR                       0
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_SCRREG                    0
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       0:0
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_GG_INTERRUPT_STATUS_G7_0
+#define GPIO_GG_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x131c)
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_SECURE                    0x0
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_DUAL                      0x0
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_SCR                       0
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_SCRREG                    0
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x1, GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       0:0
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_GG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x1320
+
+// Reserved address 0x1324
+
+// Reserved address 0x1328
+
+// Reserved address 0x132c
+
+// Reserved address 0x1330
+
+// Reserved address 0x1334
+
+// Reserved address 0x1338
+
+// Reserved address 0x133c
+
+// Reserved address 0x1340
+
+// Reserved address 0x1344
+
+// Reserved address 0x1348
+
+// Reserved address 0x134c
+
+// Reserved address 0x1350
+
+// Reserved address 0x1354
+
+// Reserved address 0x1358
+
+// Reserved address 0x135c
+
+// Reserved address 0x1360
+
+// Reserved address 0x1364
+
+// Reserved address 0x1368
+
+// Reserved address 0x136c
+
+// Reserved address 0x1370
+
+// Reserved address 0x1374
+
+// Reserved address 0x1378
+
+// Reserved address 0x137c
+
+// Reserved address 0x1380
+
+// Reserved address 0x1384
+
+// Reserved address 0x1388
+
+// Reserved address 0x138c
+
+// Reserved address 0x1390
+
+// Reserved address 0x1394
+
+// Reserved address 0x1398
+
+// Reserved address 0x139c
+
+// Reserved address 0x13a0
+
+// Reserved address 0x13a4
+
+// Reserved address 0x13a8
+
+// Reserved address 0x13ac
+
+// Reserved address 0x13b0
+
+// Reserved address 0x13b4
+
+// Reserved address 0x13b8
+
+// Reserved address 0x13bc
+
+// Reserved address 0x13c0
+
+// Reserved address 0x13c4
+
+// Reserved address 0x13c8
+
+// Reserved address 0x13cc
+
+// Reserved address 0x13d0
+
+// Reserved address 0x13d4
+
+// Reserved address 0x13d8
+
+// Reserved address 0x13dc
+
+// Reserved address 0x13e0
+
+// Reserved address 0x13e4
+
+// Reserved address 0x13e8
+
+// Reserved address 0x13ec
+
+// Reserved address 0x13f0
+
+// Reserved address 0x13f4
+
+// Reserved address 0x13f8
+
+// Reserved address 0x13fc
+
+// Register GPIO_CC_ENABLE_CONFIG_00_0
+#define GPIO_CC_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x1400)
+#define GPIO_CC_ENABLE_CONFIG_00_0_SECURE                       0x0
+#define GPIO_CC_ENABLE_CONFIG_00_0_DUAL                         0x0
+#define GPIO_CC_ENABLE_CONFIG_00_0_SCR                  GPIO_CC_SCR_00_0
+#define GPIO_CC_ENABLE_CONFIG_00_0_SCRREG                       GPIO_CC_SCR_00_0
+#define GPIO_CC_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
+#define GPIO_CC_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
+#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_CC_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x1404)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_CC_SCR_00_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_CC_SCR_00_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INPUT_00_0
+#define GPIO_CC_INPUT_00_0                      MK_ADDR_CONST(0x1408)
+#define GPIO_CC_INPUT_00_0_SECURE                       0x0
+#define GPIO_CC_INPUT_00_0_DUAL                         0x0
+#define GPIO_CC_INPUT_00_0_SCR                  GPIO_CC_SCR_00_0
+#define GPIO_CC_INPUT_00_0_SCRREG                       GPIO_CC_SCR_00_0
+#define GPIO_CC_INPUT_00_0_WORD_COUNT                   0x1
+#define GPIO_CC_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CC_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_CC_INPUT_00_0_GPIO_IN_RANGE                        0:0
+#define GPIO_CC_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_CC_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_OUTPUT_CONTROL_00_0
+#define GPIO_CC_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x140c)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_SECURE                      0x0
+#define GPIO_CC_OUTPUT_CONTROL_00_0_DUAL                        0x0
+#define GPIO_CC_OUTPUT_CONTROL_00_0_SCR                         GPIO_CC_SCR_00_0
+#define GPIO_CC_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_CC_SCR_00_0
+#define GPIO_CC_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
+#define GPIO_CC_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_CC_OUTPUT_VALUE_00_0
+#define GPIO_CC_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x1410)
+#define GPIO_CC_OUTPUT_VALUE_00_0_SECURE                        0x0
+#define GPIO_CC_OUTPUT_VALUE_00_0_DUAL                  0x0
+#define GPIO_CC_OUTPUT_VALUE_00_0_SCR                   GPIO_CC_SCR_00_0
+#define GPIO_CC_OUTPUT_VALUE_00_0_SCRREG                        GPIO_CC_SCR_00_0
+#define GPIO_CC_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
+#define GPIO_CC_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INTERRUPT_CLEAR_00_0
+#define GPIO_CC_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x1414)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_SECURE                     0x0
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_DUAL                       0x0
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_SCR                        GPIO_CC_SCR_00_0
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_CC_SCR_00_0
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1418
+
+// Reserved address 0x141c
+
+// Register GPIO_CC_ENABLE_CONFIG_01_0
+#define GPIO_CC_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x1420)
+#define GPIO_CC_ENABLE_CONFIG_01_0_SECURE                       0x0
+#define GPIO_CC_ENABLE_CONFIG_01_0_DUAL                         0x0
+#define GPIO_CC_ENABLE_CONFIG_01_0_SCR                  GPIO_CC_SCR_01_0
+#define GPIO_CC_ENABLE_CONFIG_01_0_SCRREG                       GPIO_CC_SCR_01_0
+#define GPIO_CC_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
+#define GPIO_CC_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
+#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_CC_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x1424)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_CC_SCR_01_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_CC_SCR_01_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INPUT_01_0
+#define GPIO_CC_INPUT_01_0                      MK_ADDR_CONST(0x1428)
+#define GPIO_CC_INPUT_01_0_SECURE                       0x0
+#define GPIO_CC_INPUT_01_0_DUAL                         0x0
+#define GPIO_CC_INPUT_01_0_SCR                  GPIO_CC_SCR_01_0
+#define GPIO_CC_INPUT_01_0_SCRREG                       GPIO_CC_SCR_01_0
+#define GPIO_CC_INPUT_01_0_WORD_COUNT                   0x1
+#define GPIO_CC_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CC_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_CC_INPUT_01_0_GPIO_IN_RANGE                        0:0
+#define GPIO_CC_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_CC_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_OUTPUT_CONTROL_01_0
+#define GPIO_CC_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x142c)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_SECURE                      0x0
+#define GPIO_CC_OUTPUT_CONTROL_01_0_DUAL                        0x0
+#define GPIO_CC_OUTPUT_CONTROL_01_0_SCR                         GPIO_CC_SCR_01_0
+#define GPIO_CC_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_CC_SCR_01_0
+#define GPIO_CC_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
+#define GPIO_CC_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_CC_OUTPUT_VALUE_01_0
+#define GPIO_CC_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x1430)
+#define GPIO_CC_OUTPUT_VALUE_01_0_SECURE                        0x0
+#define GPIO_CC_OUTPUT_VALUE_01_0_DUAL                  0x0
+#define GPIO_CC_OUTPUT_VALUE_01_0_SCR                   GPIO_CC_SCR_01_0
+#define GPIO_CC_OUTPUT_VALUE_01_0_SCRREG                        GPIO_CC_SCR_01_0
+#define GPIO_CC_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
+#define GPIO_CC_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INTERRUPT_CLEAR_01_0
+#define GPIO_CC_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x1434)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_SECURE                     0x0
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_DUAL                       0x0
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_SCR                        GPIO_CC_SCR_01_0
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_CC_SCR_01_0
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1438
+
+// Reserved address 0x143c
+
+// Register GPIO_CC_ENABLE_CONFIG_02_0
+#define GPIO_CC_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x1440)
+#define GPIO_CC_ENABLE_CONFIG_02_0_SECURE                       0x0
+#define GPIO_CC_ENABLE_CONFIG_02_0_DUAL                         0x0
+#define GPIO_CC_ENABLE_CONFIG_02_0_SCR                  GPIO_CC_SCR_02_0
+#define GPIO_CC_ENABLE_CONFIG_02_0_SCRREG                       GPIO_CC_SCR_02_0
+#define GPIO_CC_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
+#define GPIO_CC_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
+#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_CC_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x1444)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_CC_SCR_02_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_CC_SCR_02_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INPUT_02_0
+#define GPIO_CC_INPUT_02_0                      MK_ADDR_CONST(0x1448)
+#define GPIO_CC_INPUT_02_0_SECURE                       0x0
+#define GPIO_CC_INPUT_02_0_DUAL                         0x0
+#define GPIO_CC_INPUT_02_0_SCR                  GPIO_CC_SCR_02_0
+#define GPIO_CC_INPUT_02_0_SCRREG                       GPIO_CC_SCR_02_0
+#define GPIO_CC_INPUT_02_0_WORD_COUNT                   0x1
+#define GPIO_CC_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CC_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_CC_INPUT_02_0_GPIO_IN_RANGE                        0:0
+#define GPIO_CC_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_CC_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_OUTPUT_CONTROL_02_0
+#define GPIO_CC_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x144c)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_SECURE                      0x0
+#define GPIO_CC_OUTPUT_CONTROL_02_0_DUAL                        0x0
+#define GPIO_CC_OUTPUT_CONTROL_02_0_SCR                         GPIO_CC_SCR_02_0
+#define GPIO_CC_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_CC_SCR_02_0
+#define GPIO_CC_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
+#define GPIO_CC_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_CC_OUTPUT_VALUE_02_0
+#define GPIO_CC_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x1450)
+#define GPIO_CC_OUTPUT_VALUE_02_0_SECURE                        0x0
+#define GPIO_CC_OUTPUT_VALUE_02_0_DUAL                  0x0
+#define GPIO_CC_OUTPUT_VALUE_02_0_SCR                   GPIO_CC_SCR_02_0
+#define GPIO_CC_OUTPUT_VALUE_02_0_SCRREG                        GPIO_CC_SCR_02_0
+#define GPIO_CC_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
+#define GPIO_CC_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INTERRUPT_CLEAR_02_0
+#define GPIO_CC_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x1454)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_SECURE                     0x0
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_DUAL                       0x0
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_SCR                        GPIO_CC_SCR_02_0
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_CC_SCR_02_0
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1458
+
+// Reserved address 0x145c
+
+// Register GPIO_CC_ENABLE_CONFIG_03_0
+#define GPIO_CC_ENABLE_CONFIG_03_0                      MK_ADDR_CONST(0x1460)
+#define GPIO_CC_ENABLE_CONFIG_03_0_SECURE                       0x0
+#define GPIO_CC_ENABLE_CONFIG_03_0_DUAL                         0x0
+#define GPIO_CC_ENABLE_CONFIG_03_0_SCR                  GPIO_CC_SCR_03_0
+#define GPIO_CC_ENABLE_CONFIG_03_0_SCRREG                       GPIO_CC_SCR_03_0
+#define GPIO_CC_ENABLE_CONFIG_03_0_WORD_COUNT                   0x1
+#define GPIO_CC_ENABLE_CONFIG_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_03_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_RANGE                 1:1
+#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_CC_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0                 MK_ADDR_CONST(0x1464)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_SECURE                  0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DUAL                    0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_SCR                     GPIO_CC_SCR_03_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_SCRREG                  GPIO_CC_SCR_03_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                      0x1
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INPUT_03_0
+#define GPIO_CC_INPUT_03_0                      MK_ADDR_CONST(0x1468)
+#define GPIO_CC_INPUT_03_0_SECURE                       0x0
+#define GPIO_CC_INPUT_03_0_DUAL                         0x0
+#define GPIO_CC_INPUT_03_0_SCR                  GPIO_CC_SCR_03_0
+#define GPIO_CC_INPUT_03_0_SCRREG                       GPIO_CC_SCR_03_0
+#define GPIO_CC_INPUT_03_0_WORD_COUNT                   0x1
+#define GPIO_CC_INPUT_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_03_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_INPUT_03_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_03_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_03_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CC_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_CC_INPUT_03_0_GPIO_IN_RANGE                        0:0
+#define GPIO_CC_INPUT_03_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_03_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_03_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_CC_INPUT_03_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_03_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_03_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_OUTPUT_CONTROL_03_0
+#define GPIO_CC_OUTPUT_CONTROL_03_0                     MK_ADDR_CONST(0x146c)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_SECURE                      0x0
+#define GPIO_CC_OUTPUT_CONTROL_03_0_DUAL                        0x0
+#define GPIO_CC_OUTPUT_CONTROL_03_0_SCR                         GPIO_CC_SCR_03_0
+#define GPIO_CC_OUTPUT_CONTROL_03_0_SCRREG                      GPIO_CC_SCR_03_0
+#define GPIO_CC_OUTPUT_CONTROL_03_0_WORD_COUNT                  0x1
+#define GPIO_CC_OUTPUT_CONTROL_03_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_CC_OUTPUT_VALUE_03_0
+#define GPIO_CC_OUTPUT_VALUE_03_0                       MK_ADDR_CONST(0x1470)
+#define GPIO_CC_OUTPUT_VALUE_03_0_SECURE                        0x0
+#define GPIO_CC_OUTPUT_VALUE_03_0_DUAL                  0x0
+#define GPIO_CC_OUTPUT_VALUE_03_0_SCR                   GPIO_CC_SCR_03_0
+#define GPIO_CC_OUTPUT_VALUE_03_0_SCRREG                        GPIO_CC_SCR_03_0
+#define GPIO_CC_OUTPUT_VALUE_03_0_WORD_COUNT                    0x1
+#define GPIO_CC_OUTPUT_VALUE_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_03_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_03_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INTERRUPT_CLEAR_03_0
+#define GPIO_CC_INTERRUPT_CLEAR_03_0                    MK_ADDR_CONST(0x1474)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_SECURE                     0x0
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_DUAL                       0x0
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_SCR                        GPIO_CC_SCR_03_0
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_SCRREG                     GPIO_CC_SCR_03_0
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_WORD_COUNT                         0x1
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1478
+
+// Reserved address 0x147c
+
+// Register GPIO_CC_ENABLE_CONFIG_04_0
+#define GPIO_CC_ENABLE_CONFIG_04_0                      MK_ADDR_CONST(0x1480)
+#define GPIO_CC_ENABLE_CONFIG_04_0_SECURE                       0x0
+#define GPIO_CC_ENABLE_CONFIG_04_0_DUAL                         0x0
+#define GPIO_CC_ENABLE_CONFIG_04_0_SCR                  GPIO_CC_SCR_04_0
+#define GPIO_CC_ENABLE_CONFIG_04_0_SCRREG                       GPIO_CC_SCR_04_0
+#define GPIO_CC_ENABLE_CONFIG_04_0_WORD_COUNT                   0x1
+#define GPIO_CC_ENABLE_CONFIG_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_04_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_RANGE                 1:1
+#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_CC_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0                 MK_ADDR_CONST(0x1484)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_SECURE                  0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DUAL                    0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_SCR                     GPIO_CC_SCR_04_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_SCRREG                  GPIO_CC_SCR_04_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                      0x1
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INPUT_04_0
+#define GPIO_CC_INPUT_04_0                      MK_ADDR_CONST(0x1488)
+#define GPIO_CC_INPUT_04_0_SECURE                       0x0
+#define GPIO_CC_INPUT_04_0_DUAL                         0x0
+#define GPIO_CC_INPUT_04_0_SCR                  GPIO_CC_SCR_04_0
+#define GPIO_CC_INPUT_04_0_SCRREG                       GPIO_CC_SCR_04_0
+#define GPIO_CC_INPUT_04_0_WORD_COUNT                   0x1
+#define GPIO_CC_INPUT_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_04_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_INPUT_04_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_04_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_04_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CC_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_CC_INPUT_04_0_GPIO_IN_RANGE                        0:0
+#define GPIO_CC_INPUT_04_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_04_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_04_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_CC_INPUT_04_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_04_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_04_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_OUTPUT_CONTROL_04_0
+#define GPIO_CC_OUTPUT_CONTROL_04_0                     MK_ADDR_CONST(0x148c)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_SECURE                      0x0
+#define GPIO_CC_OUTPUT_CONTROL_04_0_DUAL                        0x0
+#define GPIO_CC_OUTPUT_CONTROL_04_0_SCR                         GPIO_CC_SCR_04_0
+#define GPIO_CC_OUTPUT_CONTROL_04_0_SCRREG                      GPIO_CC_SCR_04_0
+#define GPIO_CC_OUTPUT_CONTROL_04_0_WORD_COUNT                  0x1
+#define GPIO_CC_OUTPUT_CONTROL_04_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_CC_OUTPUT_VALUE_04_0
+#define GPIO_CC_OUTPUT_VALUE_04_0                       MK_ADDR_CONST(0x1490)
+#define GPIO_CC_OUTPUT_VALUE_04_0_SECURE                        0x0
+#define GPIO_CC_OUTPUT_VALUE_04_0_DUAL                  0x0
+#define GPIO_CC_OUTPUT_VALUE_04_0_SCR                   GPIO_CC_SCR_04_0
+#define GPIO_CC_OUTPUT_VALUE_04_0_SCRREG                        GPIO_CC_SCR_04_0
+#define GPIO_CC_OUTPUT_VALUE_04_0_WORD_COUNT                    0x1
+#define GPIO_CC_OUTPUT_VALUE_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_04_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_04_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INTERRUPT_CLEAR_04_0
+#define GPIO_CC_INTERRUPT_CLEAR_04_0                    MK_ADDR_CONST(0x1494)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_SECURE                     0x0
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_DUAL                       0x0
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_SCR                        GPIO_CC_SCR_04_0
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_SCRREG                     GPIO_CC_SCR_04_0
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_WORD_COUNT                         0x1
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1498
+
+// Reserved address 0x149c
+
+// Register GPIO_CC_ENABLE_CONFIG_05_0
+#define GPIO_CC_ENABLE_CONFIG_05_0                      MK_ADDR_CONST(0x14a0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_SECURE                       0x0
+#define GPIO_CC_ENABLE_CONFIG_05_0_DUAL                         0x0
+#define GPIO_CC_ENABLE_CONFIG_05_0_SCR                  GPIO_CC_SCR_05_0
+#define GPIO_CC_ENABLE_CONFIG_05_0_SCRREG                       GPIO_CC_SCR_05_0
+#define GPIO_CC_ENABLE_CONFIG_05_0_WORD_COUNT                   0x1
+#define GPIO_CC_ENABLE_CONFIG_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_05_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_RANGE                 1:1
+#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_CC_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0                 MK_ADDR_CONST(0x14a4)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_SECURE                  0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DUAL                    0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_SCR                     GPIO_CC_SCR_05_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_SCRREG                  GPIO_CC_SCR_05_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                      0x1
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INPUT_05_0
+#define GPIO_CC_INPUT_05_0                      MK_ADDR_CONST(0x14a8)
+#define GPIO_CC_INPUT_05_0_SECURE                       0x0
+#define GPIO_CC_INPUT_05_0_DUAL                         0x0
+#define GPIO_CC_INPUT_05_0_SCR                  GPIO_CC_SCR_05_0
+#define GPIO_CC_INPUT_05_0_SCRREG                       GPIO_CC_SCR_05_0
+#define GPIO_CC_INPUT_05_0_WORD_COUNT                   0x1
+#define GPIO_CC_INPUT_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_05_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_INPUT_05_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_05_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_05_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CC_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_CC_INPUT_05_0_GPIO_IN_RANGE                        0:0
+#define GPIO_CC_INPUT_05_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_05_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_05_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_CC_INPUT_05_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_05_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_05_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_OUTPUT_CONTROL_05_0
+#define GPIO_CC_OUTPUT_CONTROL_05_0                     MK_ADDR_CONST(0x14ac)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_SECURE                      0x0
+#define GPIO_CC_OUTPUT_CONTROL_05_0_DUAL                        0x0
+#define GPIO_CC_OUTPUT_CONTROL_05_0_SCR                         GPIO_CC_SCR_05_0
+#define GPIO_CC_OUTPUT_CONTROL_05_0_SCRREG                      GPIO_CC_SCR_05_0
+#define GPIO_CC_OUTPUT_CONTROL_05_0_WORD_COUNT                  0x1
+#define GPIO_CC_OUTPUT_CONTROL_05_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_CC_OUTPUT_VALUE_05_0
+#define GPIO_CC_OUTPUT_VALUE_05_0                       MK_ADDR_CONST(0x14b0)
+#define GPIO_CC_OUTPUT_VALUE_05_0_SECURE                        0x0
+#define GPIO_CC_OUTPUT_VALUE_05_0_DUAL                  0x0
+#define GPIO_CC_OUTPUT_VALUE_05_0_SCR                   GPIO_CC_SCR_05_0
+#define GPIO_CC_OUTPUT_VALUE_05_0_SCRREG                        GPIO_CC_SCR_05_0
+#define GPIO_CC_OUTPUT_VALUE_05_0_WORD_COUNT                    0x1
+#define GPIO_CC_OUTPUT_VALUE_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_05_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_05_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INTERRUPT_CLEAR_05_0
+#define GPIO_CC_INTERRUPT_CLEAR_05_0                    MK_ADDR_CONST(0x14b4)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_SECURE                     0x0
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_DUAL                       0x0
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_SCR                        GPIO_CC_SCR_05_0
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_SCRREG                     GPIO_CC_SCR_05_0
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_WORD_COUNT                         0x1
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14b8
+
+// Reserved address 0x14bc
+
+// Register GPIO_CC_ENABLE_CONFIG_06_0
+#define GPIO_CC_ENABLE_CONFIG_06_0                      MK_ADDR_CONST(0x14c0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_SECURE                       0x0
+#define GPIO_CC_ENABLE_CONFIG_06_0_DUAL                         0x0
+#define GPIO_CC_ENABLE_CONFIG_06_0_SCR                  GPIO_CC_SCR_06_0
+#define GPIO_CC_ENABLE_CONFIG_06_0_SCRREG                       GPIO_CC_SCR_06_0
+#define GPIO_CC_ENABLE_CONFIG_06_0_WORD_COUNT                   0x1
+#define GPIO_CC_ENABLE_CONFIG_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_06_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_RANGE                 1:1
+#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_CC_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0                 MK_ADDR_CONST(0x14c4)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_SECURE                  0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DUAL                    0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_SCR                     GPIO_CC_SCR_06_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_SCRREG                  GPIO_CC_SCR_06_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                      0x1
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INPUT_06_0
+#define GPIO_CC_INPUT_06_0                      MK_ADDR_CONST(0x14c8)
+#define GPIO_CC_INPUT_06_0_SECURE                       0x0
+#define GPIO_CC_INPUT_06_0_DUAL                         0x0
+#define GPIO_CC_INPUT_06_0_SCR                  GPIO_CC_SCR_06_0
+#define GPIO_CC_INPUT_06_0_SCRREG                       GPIO_CC_SCR_06_0
+#define GPIO_CC_INPUT_06_0_WORD_COUNT                   0x1
+#define GPIO_CC_INPUT_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_06_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_INPUT_06_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_06_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_06_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CC_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_CC_INPUT_06_0_GPIO_IN_RANGE                        0:0
+#define GPIO_CC_INPUT_06_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_06_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_06_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_CC_INPUT_06_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_06_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_06_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_OUTPUT_CONTROL_06_0
+#define GPIO_CC_OUTPUT_CONTROL_06_0                     MK_ADDR_CONST(0x14cc)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_SECURE                      0x0
+#define GPIO_CC_OUTPUT_CONTROL_06_0_DUAL                        0x0
+#define GPIO_CC_OUTPUT_CONTROL_06_0_SCR                         GPIO_CC_SCR_06_0
+#define GPIO_CC_OUTPUT_CONTROL_06_0_SCRREG                      GPIO_CC_SCR_06_0
+#define GPIO_CC_OUTPUT_CONTROL_06_0_WORD_COUNT                  0x1
+#define GPIO_CC_OUTPUT_CONTROL_06_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_CC_OUTPUT_VALUE_06_0
+#define GPIO_CC_OUTPUT_VALUE_06_0                       MK_ADDR_CONST(0x14d0)
+#define GPIO_CC_OUTPUT_VALUE_06_0_SECURE                        0x0
+#define GPIO_CC_OUTPUT_VALUE_06_0_DUAL                  0x0
+#define GPIO_CC_OUTPUT_VALUE_06_0_SCR                   GPIO_CC_SCR_06_0
+#define GPIO_CC_OUTPUT_VALUE_06_0_SCRREG                        GPIO_CC_SCR_06_0
+#define GPIO_CC_OUTPUT_VALUE_06_0_WORD_COUNT                    0x1
+#define GPIO_CC_OUTPUT_VALUE_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_06_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_06_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INTERRUPT_CLEAR_06_0
+#define GPIO_CC_INTERRUPT_CLEAR_06_0                    MK_ADDR_CONST(0x14d4)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_SECURE                     0x0
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_DUAL                       0x0
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_SCR                        GPIO_CC_SCR_06_0
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_SCRREG                     GPIO_CC_SCR_06_0
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_WORD_COUNT                         0x1
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14d8
+
+// Reserved address 0x14dc
+
+// Register GPIO_CC_ENABLE_CONFIG_07_0
+#define GPIO_CC_ENABLE_CONFIG_07_0                      MK_ADDR_CONST(0x14e0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_SECURE                       0x0
+#define GPIO_CC_ENABLE_CONFIG_07_0_DUAL                         0x0
+#define GPIO_CC_ENABLE_CONFIG_07_0_SCR                  GPIO_CC_SCR_07_0
+#define GPIO_CC_ENABLE_CONFIG_07_0_SCRREG                       GPIO_CC_SCR_07_0
+#define GPIO_CC_ENABLE_CONFIG_07_0_WORD_COUNT                   0x1
+#define GPIO_CC_ENABLE_CONFIG_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_07_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_RANGE                 1:1
+#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_CC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_CC_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0                 MK_ADDR_CONST(0x14e4)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_SECURE                  0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DUAL                    0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_SCR                     GPIO_CC_SCR_07_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_SCRREG                  GPIO_CC_SCR_07_0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                      0x1
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_CC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INPUT_07_0
+#define GPIO_CC_INPUT_07_0                      MK_ADDR_CONST(0x14e8)
+#define GPIO_CC_INPUT_07_0_SECURE                       0x0
+#define GPIO_CC_INPUT_07_0_DUAL                         0x0
+#define GPIO_CC_INPUT_07_0_SCR                  GPIO_CC_SCR_07_0
+#define GPIO_CC_INPUT_07_0_SCRREG                       GPIO_CC_SCR_07_0
+#define GPIO_CC_INPUT_07_0_WORD_COUNT                   0x1
+#define GPIO_CC_INPUT_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_07_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_INPUT_07_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_07_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_07_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CC_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_CC_INPUT_07_0_GPIO_IN_RANGE                        0:0
+#define GPIO_CC_INPUT_07_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_07_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_CC_INPUT_07_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_CC_INPUT_07_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_07_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_07_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_OUTPUT_CONTROL_07_0
+#define GPIO_CC_OUTPUT_CONTROL_07_0                     MK_ADDR_CONST(0x14ec)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_SECURE                      0x0
+#define GPIO_CC_OUTPUT_CONTROL_07_0_DUAL                        0x0
+#define GPIO_CC_OUTPUT_CONTROL_07_0_SCR                         GPIO_CC_SCR_07_0
+#define GPIO_CC_OUTPUT_CONTROL_07_0_SCRREG                      GPIO_CC_SCR_07_0
+#define GPIO_CC_OUTPUT_CONTROL_07_0_WORD_COUNT                  0x1
+#define GPIO_CC_OUTPUT_CONTROL_07_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_CC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_CC_OUTPUT_VALUE_07_0
+#define GPIO_CC_OUTPUT_VALUE_07_0                       MK_ADDR_CONST(0x14f0)
+#define GPIO_CC_OUTPUT_VALUE_07_0_SECURE                        0x0
+#define GPIO_CC_OUTPUT_VALUE_07_0_DUAL                  0x0
+#define GPIO_CC_OUTPUT_VALUE_07_0_SCR                   GPIO_CC_SCR_07_0
+#define GPIO_CC_OUTPUT_VALUE_07_0_SCRREG                        GPIO_CC_SCR_07_0
+#define GPIO_CC_OUTPUT_VALUE_07_0_WORD_COUNT                    0x1
+#define GPIO_CC_OUTPUT_VALUE_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_07_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_07_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_CC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INTERRUPT_CLEAR_07_0
+#define GPIO_CC_INTERRUPT_CLEAR_07_0                    MK_ADDR_CONST(0x14f4)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_SECURE                     0x0
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_DUAL                       0x0
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_SCR                        GPIO_CC_SCR_07_0
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_SCRREG                     GPIO_CC_SCR_07_0
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_WORD_COUNT                         0x1
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_CC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14f8
+
+// Reserved address 0x14fc
+
+// Register GPIO_CC_INTERRUPT_STATUS_G0_0
+#define GPIO_CC_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x1500)
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_SECURE                    0x0
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_DUAL                      0x0
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_SCR                       0
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_SCRREG                    0
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INTERRUPT_STATUS_G1_0
+#define GPIO_CC_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x1504)
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_SECURE                    0x0
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_DUAL                      0x0
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_SCR                       0
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_SCRREG                    0
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INTERRUPT_STATUS_G2_0
+#define GPIO_CC_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x1508)
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_SECURE                    0x0
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_DUAL                      0x0
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_SCR                       0
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_SCRREG                    0
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INTERRUPT_STATUS_G3_0
+#define GPIO_CC_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x150c)
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_SECURE                    0x0
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_DUAL                      0x0
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_SCR                       0
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_SCRREG                    0
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INTERRUPT_STATUS_G4_0
+#define GPIO_CC_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x1510)
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_SECURE                    0x0
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_DUAL                      0x0
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_SCR                       0
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_SCRREG                    0
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INTERRUPT_STATUS_G5_0
+#define GPIO_CC_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x1514)
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_SECURE                    0x0
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_DUAL                      0x0
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_SCR                       0
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_SCRREG                    0
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INTERRUPT_STATUS_G6_0
+#define GPIO_CC_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x1518)
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_SECURE                    0x0
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_DUAL                      0x0
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_SCR                       0
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_SCRREG                    0
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CC_INTERRUPT_STATUS_G7_0
+#define GPIO_CC_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x151c)
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_SECURE                    0x0
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_DUAL                      0x0
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_SCR                       0
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_SCRREG                    0
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x1520
+
+// Reserved address 0x1524
+
+// Reserved address 0x1528
+
+// Reserved address 0x152c
+
+// Reserved address 0x1530
+
+// Reserved address 0x1534
+
+// Reserved address 0x1538
+
+// Reserved address 0x153c
+
+// Reserved address 0x1540
+
+// Reserved address 0x1544
+
+// Reserved address 0x1548
+
+// Reserved address 0x154c
+
+// Reserved address 0x1550
+
+// Reserved address 0x1554
+
+// Reserved address 0x1558
+
+// Reserved address 0x155c
+
+// Reserved address 0x1560
+
+// Reserved address 0x1564
+
+// Reserved address 0x1568
+
+// Reserved address 0x156c
+
+// Reserved address 0x1570
+
+// Reserved address 0x1574
+
+// Reserved address 0x1578
+
+// Reserved address 0x157c
+
+// Reserved address 0x1580
+
+// Reserved address 0x1584
+
+// Reserved address 0x1588
+
+// Reserved address 0x158c
+
+// Reserved address 0x1590
+
+// Reserved address 0x1594
+
+// Reserved address 0x1598
+
+// Reserved address 0x159c
+
+// Reserved address 0x15a0
+
+// Reserved address 0x15a4
+
+// Reserved address 0x15a8
+
+// Reserved address 0x15ac
+
+// Reserved address 0x15b0
+
+// Reserved address 0x15b4
+
+// Reserved address 0x15b8
+
+// Reserved address 0x15bc
+
+// Reserved address 0x15c0
+
+// Reserved address 0x15c4
+
+// Reserved address 0x15c8
+
+// Reserved address 0x15cc
+
+// Reserved address 0x15d0
+
+// Reserved address 0x15d4
+
+// Reserved address 0x15d8
+
+// Reserved address 0x15dc
+
+// Reserved address 0x15e0
+
+// Reserved address 0x15e4
+
+// Reserved address 0x15e8
+
+// Reserved address 0x15ec
+
+// Reserved address 0x15f0
+
+// Reserved address 0x15f4
+
+// Reserved address 0x15f8
+
+// Reserved address 0x15fc
+
+// Register GPIO_DD_ENABLE_CONFIG_00_0
+#define GPIO_DD_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x1600)
+#define GPIO_DD_ENABLE_CONFIG_00_0_SECURE                       0x0
+#define GPIO_DD_ENABLE_CONFIG_00_0_DUAL                         0x0
+#define GPIO_DD_ENABLE_CONFIG_00_0_SCR                  GPIO_DD_SCR_00_0
+#define GPIO_DD_ENABLE_CONFIG_00_0_SCRREG                       GPIO_DD_SCR_00_0
+#define GPIO_DD_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
+#define GPIO_DD_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_DD_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_DD_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
+#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_DD_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x1604)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_DD_SCR_00_0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_DD_SCR_00_0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_DD_INPUT_00_0
+#define GPIO_DD_INPUT_00_0                      MK_ADDR_CONST(0x1608)
+#define GPIO_DD_INPUT_00_0_SECURE                       0x0
+#define GPIO_DD_INPUT_00_0_DUAL                         0x0
+#define GPIO_DD_INPUT_00_0_SCR                  GPIO_DD_SCR_00_0
+#define GPIO_DD_INPUT_00_0_SCRREG                       GPIO_DD_SCR_00_0
+#define GPIO_DD_INPUT_00_0_WORD_COUNT                   0x1
+#define GPIO_DD_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_DD_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_DD_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_DD_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_DD_INPUT_00_0_GPIO_IN_RANGE                        0:0
+#define GPIO_DD_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_DD_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_DD_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_DD_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_DD_OUTPUT_CONTROL_00_0
+#define GPIO_DD_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x160c)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_SECURE                      0x0
+#define GPIO_DD_OUTPUT_CONTROL_00_0_DUAL                        0x0
+#define GPIO_DD_OUTPUT_CONTROL_00_0_SCR                         GPIO_DD_SCR_00_0
+#define GPIO_DD_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_DD_SCR_00_0
+#define GPIO_DD_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
+#define GPIO_DD_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_DD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_DD_OUTPUT_VALUE_00_0
+#define GPIO_DD_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x1610)
+#define GPIO_DD_OUTPUT_VALUE_00_0_SECURE                        0x0
+#define GPIO_DD_OUTPUT_VALUE_00_0_DUAL                  0x0
+#define GPIO_DD_OUTPUT_VALUE_00_0_SCR                   GPIO_DD_SCR_00_0
+#define GPIO_DD_OUTPUT_VALUE_00_0_SCRREG                        GPIO_DD_SCR_00_0
+#define GPIO_DD_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
+#define GPIO_DD_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_DD_INTERRUPT_CLEAR_00_0
+#define GPIO_DD_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x1614)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_SECURE                     0x0
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_DUAL                       0x0
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_SCR                        GPIO_DD_SCR_00_0
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_DD_SCR_00_0
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_DD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1618
+
+// Reserved address 0x161c
+
+// Register GPIO_DD_ENABLE_CONFIG_01_0
+#define GPIO_DD_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x1620)
+#define GPIO_DD_ENABLE_CONFIG_01_0_SECURE                       0x0
+#define GPIO_DD_ENABLE_CONFIG_01_0_DUAL                         0x0
+#define GPIO_DD_ENABLE_CONFIG_01_0_SCR                  GPIO_DD_SCR_01_0
+#define GPIO_DD_ENABLE_CONFIG_01_0_SCRREG                       GPIO_DD_SCR_01_0
+#define GPIO_DD_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
+#define GPIO_DD_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_DD_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_DD_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
+#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_DD_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x1624)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_DD_SCR_01_0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_DD_SCR_01_0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_DD_INPUT_01_0
+#define GPIO_DD_INPUT_01_0                      MK_ADDR_CONST(0x1628)
+#define GPIO_DD_INPUT_01_0_SECURE                       0x0
+#define GPIO_DD_INPUT_01_0_DUAL                         0x0
+#define GPIO_DD_INPUT_01_0_SCR                  GPIO_DD_SCR_01_0
+#define GPIO_DD_INPUT_01_0_SCRREG                       GPIO_DD_SCR_01_0
+#define GPIO_DD_INPUT_01_0_WORD_COUNT                   0x1
+#define GPIO_DD_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_DD_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_DD_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_DD_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_DD_INPUT_01_0_GPIO_IN_RANGE                        0:0
+#define GPIO_DD_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_DD_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_DD_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_DD_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_DD_OUTPUT_CONTROL_01_0
+#define GPIO_DD_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x162c)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_SECURE                      0x0
+#define GPIO_DD_OUTPUT_CONTROL_01_0_DUAL                        0x0
+#define GPIO_DD_OUTPUT_CONTROL_01_0_SCR                         GPIO_DD_SCR_01_0
+#define GPIO_DD_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_DD_SCR_01_0
+#define GPIO_DD_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
+#define GPIO_DD_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_DD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_DD_OUTPUT_VALUE_01_0
+#define GPIO_DD_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x1630)
+#define GPIO_DD_OUTPUT_VALUE_01_0_SECURE                        0x0
+#define GPIO_DD_OUTPUT_VALUE_01_0_DUAL                  0x0
+#define GPIO_DD_OUTPUT_VALUE_01_0_SCR                   GPIO_DD_SCR_01_0
+#define GPIO_DD_OUTPUT_VALUE_01_0_SCRREG                        GPIO_DD_SCR_01_0
+#define GPIO_DD_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
+#define GPIO_DD_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_DD_INTERRUPT_CLEAR_01_0
+#define GPIO_DD_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x1634)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_SECURE                     0x0
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_DUAL                       0x0
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_SCR                        GPIO_DD_SCR_01_0
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_DD_SCR_01_0
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_DD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1638
+
+// Reserved address 0x163c
+
+// Register GPIO_DD_ENABLE_CONFIG_02_0
+#define GPIO_DD_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x1640)
+#define GPIO_DD_ENABLE_CONFIG_02_0_SECURE                       0x0
+#define GPIO_DD_ENABLE_CONFIG_02_0_DUAL                         0x0
+#define GPIO_DD_ENABLE_CONFIG_02_0_SCR                  GPIO_DD_SCR_02_0
+#define GPIO_DD_ENABLE_CONFIG_02_0_SCRREG                       GPIO_DD_SCR_02_0
+#define GPIO_DD_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
+#define GPIO_DD_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_DD_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_DD_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
+#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_DD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_DD_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x1644)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_DD_SCR_02_0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_DD_SCR_02_0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_DD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_DD_INPUT_02_0
+#define GPIO_DD_INPUT_02_0                      MK_ADDR_CONST(0x1648)
+#define GPIO_DD_INPUT_02_0_SECURE                       0x0
+#define GPIO_DD_INPUT_02_0_DUAL                         0x0
+#define GPIO_DD_INPUT_02_0_SCR                  GPIO_DD_SCR_02_0
+#define GPIO_DD_INPUT_02_0_SCRREG                       GPIO_DD_SCR_02_0
+#define GPIO_DD_INPUT_02_0_WORD_COUNT                   0x1
+#define GPIO_DD_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_DD_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_DD_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_DD_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_DD_INPUT_02_0_GPIO_IN_RANGE                        0:0
+#define GPIO_DD_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_DD_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_DD_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_DD_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_DD_OUTPUT_CONTROL_02_0
+#define GPIO_DD_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x164c)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_SECURE                      0x0
+#define GPIO_DD_OUTPUT_CONTROL_02_0_DUAL                        0x0
+#define GPIO_DD_OUTPUT_CONTROL_02_0_SCR                         GPIO_DD_SCR_02_0
+#define GPIO_DD_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_DD_SCR_02_0
+#define GPIO_DD_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
+#define GPIO_DD_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_DD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_DD_OUTPUT_VALUE_02_0
+#define GPIO_DD_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x1650)
+#define GPIO_DD_OUTPUT_VALUE_02_0_SECURE                        0x0
+#define GPIO_DD_OUTPUT_VALUE_02_0_DUAL                  0x0
+#define GPIO_DD_OUTPUT_VALUE_02_0_SCR                   GPIO_DD_SCR_02_0
+#define GPIO_DD_OUTPUT_VALUE_02_0_SCRREG                        GPIO_DD_SCR_02_0
+#define GPIO_DD_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
+#define GPIO_DD_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_DD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_DD_INTERRUPT_CLEAR_02_0
+#define GPIO_DD_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x1654)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_SECURE                     0x0
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_DUAL                       0x0
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_SCR                        GPIO_DD_SCR_02_0
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_DD_SCR_02_0
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_DD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1658
+
+// Reserved address 0x165c
+
+// Reserved address 0x1660
+
+// Reserved address 0x1664
+
+// Reserved address 0x1668
+
+// Reserved address 0x166c
+
+// Reserved address 0x1670
+
+// Reserved address 0x1674
+
+// Reserved address 0x1678
+
+// Reserved address 0x167c
+
+// Reserved address 0x1680
+
+// Reserved address 0x1684
+
+// Reserved address 0x1688
+
+// Reserved address 0x168c
+
+// Reserved address 0x1690
+
+// Reserved address 0x1694
+
+// Reserved address 0x1698
+
+// Reserved address 0x169c
+
+// Reserved address 0x16a0
+
+// Reserved address 0x16a4
+
+// Reserved address 0x16a8
+
+// Reserved address 0x16ac
+
+// Reserved address 0x16b0
+
+// Reserved address 0x16b4
+
+// Reserved address 0x16b8
+
+// Reserved address 0x16bc
+
+// Reserved address 0x16c0
+
+// Reserved address 0x16c4
+
+// Reserved address 0x16c8
+
+// Reserved address 0x16cc
+
+// Reserved address 0x16d0
+
+// Reserved address 0x16d4
+
+// Reserved address 0x16d8
+
+// Reserved address 0x16dc
+
+// Reserved address 0x16e0
+
+// Reserved address 0x16e4
+
+// Reserved address 0x16e8
+
+// Reserved address 0x16ec
+
+// Reserved address 0x16f0
+
+// Reserved address 0x16f4
+
+// Reserved address 0x16f8
+
+// Reserved address 0x16fc
+
+// Register GPIO_DD_INTERRUPT_STATUS_G0_0
+#define GPIO_DD_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x1700)
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_SECURE                    0x0
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_DUAL                      0x0
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_SCR                       0
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_SCRREG                    0
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x7, GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       2:0
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_DD_INTERRUPT_STATUS_G1_0
+#define GPIO_DD_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x1704)
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_SECURE                    0x0
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_DUAL                      0x0
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_SCR                       0
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_SCRREG                    0
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x7, GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       2:0
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_DD_INTERRUPT_STATUS_G2_0
+#define GPIO_DD_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x1708)
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_SECURE                    0x0
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_DUAL                      0x0
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_SCR                       0
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_SCRREG                    0
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x7, GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       2:0
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_DD_INTERRUPT_STATUS_G3_0
+#define GPIO_DD_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x170c)
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_SECURE                    0x0
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_DUAL                      0x0
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_SCR                       0
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_SCRREG                    0
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x7, GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       2:0
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_DD_INTERRUPT_STATUS_G4_0
+#define GPIO_DD_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x1710)
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_SECURE                    0x0
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_DUAL                      0x0
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_SCR                       0
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_SCRREG                    0
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x7, GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       2:0
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_DD_INTERRUPT_STATUS_G5_0
+#define GPIO_DD_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x1714)
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_SECURE                    0x0
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_DUAL                      0x0
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_SCR                       0
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_SCRREG                    0
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x7, GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       2:0
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_DD_INTERRUPT_STATUS_G6_0
+#define GPIO_DD_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x1718)
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_SECURE                    0x0
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_DUAL                      0x0
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_SCR                       0
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_SCRREG                    0
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x7, GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       2:0
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_DD_INTERRUPT_STATUS_G7_0
+#define GPIO_DD_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x171c)
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_SECURE                    0x0
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_DUAL                      0x0
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_SCR                       0
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_SCRREG                    0
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x7, GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       2:0
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_DD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x1720
+
+// Reserved address 0x1724
+
+// Reserved address 0x1728
+
+// Reserved address 0x172c
+
+// Reserved address 0x1730
+
+// Reserved address 0x1734
+
+// Reserved address 0x1738
+
+// Reserved address 0x173c
+
+// Reserved address 0x1740
+
+// Reserved address 0x1744
+
+// Reserved address 0x1748
+
+// Reserved address 0x174c
+
+// Reserved address 0x1750
+
+// Reserved address 0x1754
+
+// Reserved address 0x1758
+
+// Reserved address 0x175c
+
+// Reserved address 0x1760
+
+// Reserved address 0x1764
+
+// Reserved address 0x1768
+
+// Reserved address 0x176c
+
+// Reserved address 0x1770
+
+// Reserved address 0x1774
+
+// Reserved address 0x1778
+
+// Reserved address 0x177c
+
+// Reserved address 0x1780
+
+// Reserved address 0x1784
+
+// Reserved address 0x1788
+
+// Reserved address 0x178c
+
+// Reserved address 0x1790
+
+// Reserved address 0x1794
+
+// Reserved address 0x1798
+
+// Reserved address 0x179c
+
+// Reserved address 0x17a0
+
+// Reserved address 0x17a4
+
+// Reserved address 0x17a8
+
+// Reserved address 0x17ac
+
+// Reserved address 0x17b0
+
+// Reserved address 0x17b4
+
+// Reserved address 0x17b8
+
+// Reserved address 0x17bc
+
+// Reserved address 0x17c0
+
+// Reserved address 0x17c4
+
+// Reserved address 0x17c8
+
+// Reserved address 0x17cc
+
+// Reserved address 0x17d0
+
+// Reserved address 0x17d4
+
+// Reserved address 0x17d8
+
+// Reserved address 0x17dc
+
+// Reserved address 0x17e0
+
+// Reserved address 0x17e4
+
+// Reserved address 0x17e8
+
+// Reserved address 0x17ec
+
+// Reserved address 0x17f0
+
+// Reserved address 0x17f4
+
+// Reserved address 0x17f8
+
+// Reserved address 0x17fc
+
+// Register GPIO_AA_ENABLE_CONFIG_00_0
+#define GPIO_AA_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x1800)
+#define GPIO_AA_ENABLE_CONFIG_00_0_SECURE                       0x0
+#define GPIO_AA_ENABLE_CONFIG_00_0_DUAL                         0x0
+#define GPIO_AA_ENABLE_CONFIG_00_0_SCR                  GPIO_AA_SCR_00_0
+#define GPIO_AA_ENABLE_CONFIG_00_0_SCRREG                       GPIO_AA_SCR_00_0
+#define GPIO_AA_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
+#define GPIO_AA_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
+#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AA_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x1804)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_AA_SCR_00_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_AA_SCR_00_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INPUT_00_0
+#define GPIO_AA_INPUT_00_0                      MK_ADDR_CONST(0x1808)
+#define GPIO_AA_INPUT_00_0_SECURE                       0x0
+#define GPIO_AA_INPUT_00_0_DUAL                         0x0
+#define GPIO_AA_INPUT_00_0_SCR                  GPIO_AA_SCR_00_0
+#define GPIO_AA_INPUT_00_0_SCRREG                       GPIO_AA_SCR_00_0
+#define GPIO_AA_INPUT_00_0_WORD_COUNT                   0x1
+#define GPIO_AA_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AA_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_AA_INPUT_00_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AA_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AA_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_OUTPUT_CONTROL_00_0
+#define GPIO_AA_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x180c)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_SECURE                      0x0
+#define GPIO_AA_OUTPUT_CONTROL_00_0_DUAL                        0x0
+#define GPIO_AA_OUTPUT_CONTROL_00_0_SCR                         GPIO_AA_SCR_00_0
+#define GPIO_AA_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_AA_SCR_00_0
+#define GPIO_AA_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
+#define GPIO_AA_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AA_OUTPUT_VALUE_00_0
+#define GPIO_AA_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x1810)
+#define GPIO_AA_OUTPUT_VALUE_00_0_SECURE                        0x0
+#define GPIO_AA_OUTPUT_VALUE_00_0_DUAL                  0x0
+#define GPIO_AA_OUTPUT_VALUE_00_0_SCR                   GPIO_AA_SCR_00_0
+#define GPIO_AA_OUTPUT_VALUE_00_0_SCRREG                        GPIO_AA_SCR_00_0
+#define GPIO_AA_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
+#define GPIO_AA_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INTERRUPT_CLEAR_00_0
+#define GPIO_AA_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x1814)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_SECURE                     0x0
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_DUAL                       0x0
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_SCR                        GPIO_AA_SCR_00_0
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_AA_SCR_00_0
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1818
+
+// Reserved address 0x181c
+
+// Register GPIO_AA_ENABLE_CONFIG_01_0
+#define GPIO_AA_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x1820)
+#define GPIO_AA_ENABLE_CONFIG_01_0_SECURE                       0x0
+#define GPIO_AA_ENABLE_CONFIG_01_0_DUAL                         0x0
+#define GPIO_AA_ENABLE_CONFIG_01_0_SCR                  GPIO_AA_SCR_01_0
+#define GPIO_AA_ENABLE_CONFIG_01_0_SCRREG                       GPIO_AA_SCR_01_0
+#define GPIO_AA_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
+#define GPIO_AA_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
+#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AA_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x1824)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_AA_SCR_01_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_AA_SCR_01_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INPUT_01_0
+#define GPIO_AA_INPUT_01_0                      MK_ADDR_CONST(0x1828)
+#define GPIO_AA_INPUT_01_0_SECURE                       0x0
+#define GPIO_AA_INPUT_01_0_DUAL                         0x0
+#define GPIO_AA_INPUT_01_0_SCR                  GPIO_AA_SCR_01_0
+#define GPIO_AA_INPUT_01_0_SCRREG                       GPIO_AA_SCR_01_0
+#define GPIO_AA_INPUT_01_0_WORD_COUNT                   0x1
+#define GPIO_AA_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AA_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_AA_INPUT_01_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AA_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AA_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_OUTPUT_CONTROL_01_0
+#define GPIO_AA_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x182c)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_SECURE                      0x0
+#define GPIO_AA_OUTPUT_CONTROL_01_0_DUAL                        0x0
+#define GPIO_AA_OUTPUT_CONTROL_01_0_SCR                         GPIO_AA_SCR_01_0
+#define GPIO_AA_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_AA_SCR_01_0
+#define GPIO_AA_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
+#define GPIO_AA_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AA_OUTPUT_VALUE_01_0
+#define GPIO_AA_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x1830)
+#define GPIO_AA_OUTPUT_VALUE_01_0_SECURE                        0x0
+#define GPIO_AA_OUTPUT_VALUE_01_0_DUAL                  0x0
+#define GPIO_AA_OUTPUT_VALUE_01_0_SCR                   GPIO_AA_SCR_01_0
+#define GPIO_AA_OUTPUT_VALUE_01_0_SCRREG                        GPIO_AA_SCR_01_0
+#define GPIO_AA_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
+#define GPIO_AA_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INTERRUPT_CLEAR_01_0
+#define GPIO_AA_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x1834)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_SECURE                     0x0
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_DUAL                       0x0
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_SCR                        GPIO_AA_SCR_01_0
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_AA_SCR_01_0
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1838
+
+// Reserved address 0x183c
+
+// Register GPIO_AA_ENABLE_CONFIG_02_0
+#define GPIO_AA_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x1840)
+#define GPIO_AA_ENABLE_CONFIG_02_0_SECURE                       0x0
+#define GPIO_AA_ENABLE_CONFIG_02_0_DUAL                         0x0
+#define GPIO_AA_ENABLE_CONFIG_02_0_SCR                  GPIO_AA_SCR_02_0
+#define GPIO_AA_ENABLE_CONFIG_02_0_SCRREG                       GPIO_AA_SCR_02_0
+#define GPIO_AA_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
+#define GPIO_AA_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
+#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AA_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x1844)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_AA_SCR_02_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_AA_SCR_02_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INPUT_02_0
+#define GPIO_AA_INPUT_02_0                      MK_ADDR_CONST(0x1848)
+#define GPIO_AA_INPUT_02_0_SECURE                       0x0
+#define GPIO_AA_INPUT_02_0_DUAL                         0x0
+#define GPIO_AA_INPUT_02_0_SCR                  GPIO_AA_SCR_02_0
+#define GPIO_AA_INPUT_02_0_SCRREG                       GPIO_AA_SCR_02_0
+#define GPIO_AA_INPUT_02_0_WORD_COUNT                   0x1
+#define GPIO_AA_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AA_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_AA_INPUT_02_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AA_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AA_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_OUTPUT_CONTROL_02_0
+#define GPIO_AA_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x184c)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_SECURE                      0x0
+#define GPIO_AA_OUTPUT_CONTROL_02_0_DUAL                        0x0
+#define GPIO_AA_OUTPUT_CONTROL_02_0_SCR                         GPIO_AA_SCR_02_0
+#define GPIO_AA_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_AA_SCR_02_0
+#define GPIO_AA_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
+#define GPIO_AA_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AA_OUTPUT_VALUE_02_0
+#define GPIO_AA_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x1850)
+#define GPIO_AA_OUTPUT_VALUE_02_0_SECURE                        0x0
+#define GPIO_AA_OUTPUT_VALUE_02_0_DUAL                  0x0
+#define GPIO_AA_OUTPUT_VALUE_02_0_SCR                   GPIO_AA_SCR_02_0
+#define GPIO_AA_OUTPUT_VALUE_02_0_SCRREG                        GPIO_AA_SCR_02_0
+#define GPIO_AA_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
+#define GPIO_AA_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INTERRUPT_CLEAR_02_0
+#define GPIO_AA_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x1854)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_SECURE                     0x0
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_DUAL                       0x0
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_SCR                        GPIO_AA_SCR_02_0
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_AA_SCR_02_0
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1858
+
+// Reserved address 0x185c
+
+// Register GPIO_AA_ENABLE_CONFIG_03_0
+#define GPIO_AA_ENABLE_CONFIG_03_0                      MK_ADDR_CONST(0x1860)
+#define GPIO_AA_ENABLE_CONFIG_03_0_SECURE                       0x0
+#define GPIO_AA_ENABLE_CONFIG_03_0_DUAL                         0x0
+#define GPIO_AA_ENABLE_CONFIG_03_0_SCR                  GPIO_AA_SCR_03_0
+#define GPIO_AA_ENABLE_CONFIG_03_0_SCRREG                       GPIO_AA_SCR_03_0
+#define GPIO_AA_ENABLE_CONFIG_03_0_WORD_COUNT                   0x1
+#define GPIO_AA_ENABLE_CONFIG_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_03_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_RANGE                 1:1
+#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AA_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0                 MK_ADDR_CONST(0x1864)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_SECURE                  0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DUAL                    0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_SCR                     GPIO_AA_SCR_03_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_SCRREG                  GPIO_AA_SCR_03_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                      0x1
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INPUT_03_0
+#define GPIO_AA_INPUT_03_0                      MK_ADDR_CONST(0x1868)
+#define GPIO_AA_INPUT_03_0_SECURE                       0x0
+#define GPIO_AA_INPUT_03_0_DUAL                         0x0
+#define GPIO_AA_INPUT_03_0_SCR                  GPIO_AA_SCR_03_0
+#define GPIO_AA_INPUT_03_0_SCRREG                       GPIO_AA_SCR_03_0
+#define GPIO_AA_INPUT_03_0_WORD_COUNT                   0x1
+#define GPIO_AA_INPUT_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_03_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_INPUT_03_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_03_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_03_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AA_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_AA_INPUT_03_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AA_INPUT_03_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_03_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_03_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AA_INPUT_03_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_03_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_03_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_OUTPUT_CONTROL_03_0
+#define GPIO_AA_OUTPUT_CONTROL_03_0                     MK_ADDR_CONST(0x186c)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_SECURE                      0x0
+#define GPIO_AA_OUTPUT_CONTROL_03_0_DUAL                        0x0
+#define GPIO_AA_OUTPUT_CONTROL_03_0_SCR                         GPIO_AA_SCR_03_0
+#define GPIO_AA_OUTPUT_CONTROL_03_0_SCRREG                      GPIO_AA_SCR_03_0
+#define GPIO_AA_OUTPUT_CONTROL_03_0_WORD_COUNT                  0x1
+#define GPIO_AA_OUTPUT_CONTROL_03_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AA_OUTPUT_VALUE_03_0
+#define GPIO_AA_OUTPUT_VALUE_03_0                       MK_ADDR_CONST(0x1870)
+#define GPIO_AA_OUTPUT_VALUE_03_0_SECURE                        0x0
+#define GPIO_AA_OUTPUT_VALUE_03_0_DUAL                  0x0
+#define GPIO_AA_OUTPUT_VALUE_03_0_SCR                   GPIO_AA_SCR_03_0
+#define GPIO_AA_OUTPUT_VALUE_03_0_SCRREG                        GPIO_AA_SCR_03_0
+#define GPIO_AA_OUTPUT_VALUE_03_0_WORD_COUNT                    0x1
+#define GPIO_AA_OUTPUT_VALUE_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_03_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_03_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INTERRUPT_CLEAR_03_0
+#define GPIO_AA_INTERRUPT_CLEAR_03_0                    MK_ADDR_CONST(0x1874)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_SECURE                     0x0
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_DUAL                       0x0
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_SCR                        GPIO_AA_SCR_03_0
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_SCRREG                     GPIO_AA_SCR_03_0
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_WORD_COUNT                         0x1
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1878
+
+// Reserved address 0x187c
+
+// Register GPIO_AA_ENABLE_CONFIG_04_0
+#define GPIO_AA_ENABLE_CONFIG_04_0                      MK_ADDR_CONST(0x1880)
+#define GPIO_AA_ENABLE_CONFIG_04_0_SECURE                       0x0
+#define GPIO_AA_ENABLE_CONFIG_04_0_DUAL                         0x0
+#define GPIO_AA_ENABLE_CONFIG_04_0_SCR                  GPIO_AA_SCR_04_0
+#define GPIO_AA_ENABLE_CONFIG_04_0_SCRREG                       GPIO_AA_SCR_04_0
+#define GPIO_AA_ENABLE_CONFIG_04_0_WORD_COUNT                   0x1
+#define GPIO_AA_ENABLE_CONFIG_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_04_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_RANGE                 1:1
+#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AA_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0                 MK_ADDR_CONST(0x1884)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_SECURE                  0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DUAL                    0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_SCR                     GPIO_AA_SCR_04_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_SCRREG                  GPIO_AA_SCR_04_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                      0x1
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INPUT_04_0
+#define GPIO_AA_INPUT_04_0                      MK_ADDR_CONST(0x1888)
+#define GPIO_AA_INPUT_04_0_SECURE                       0x0
+#define GPIO_AA_INPUT_04_0_DUAL                         0x0
+#define GPIO_AA_INPUT_04_0_SCR                  GPIO_AA_SCR_04_0
+#define GPIO_AA_INPUT_04_0_SCRREG                       GPIO_AA_SCR_04_0
+#define GPIO_AA_INPUT_04_0_WORD_COUNT                   0x1
+#define GPIO_AA_INPUT_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_04_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_INPUT_04_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_04_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_04_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AA_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_AA_INPUT_04_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AA_INPUT_04_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_04_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_04_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AA_INPUT_04_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_04_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_04_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_OUTPUT_CONTROL_04_0
+#define GPIO_AA_OUTPUT_CONTROL_04_0                     MK_ADDR_CONST(0x188c)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_SECURE                      0x0
+#define GPIO_AA_OUTPUT_CONTROL_04_0_DUAL                        0x0
+#define GPIO_AA_OUTPUT_CONTROL_04_0_SCR                         GPIO_AA_SCR_04_0
+#define GPIO_AA_OUTPUT_CONTROL_04_0_SCRREG                      GPIO_AA_SCR_04_0
+#define GPIO_AA_OUTPUT_CONTROL_04_0_WORD_COUNT                  0x1
+#define GPIO_AA_OUTPUT_CONTROL_04_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AA_OUTPUT_VALUE_04_0
+#define GPIO_AA_OUTPUT_VALUE_04_0                       MK_ADDR_CONST(0x1890)
+#define GPIO_AA_OUTPUT_VALUE_04_0_SECURE                        0x0
+#define GPIO_AA_OUTPUT_VALUE_04_0_DUAL                  0x0
+#define GPIO_AA_OUTPUT_VALUE_04_0_SCR                   GPIO_AA_SCR_04_0
+#define GPIO_AA_OUTPUT_VALUE_04_0_SCRREG                        GPIO_AA_SCR_04_0
+#define GPIO_AA_OUTPUT_VALUE_04_0_WORD_COUNT                    0x1
+#define GPIO_AA_OUTPUT_VALUE_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_04_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_04_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INTERRUPT_CLEAR_04_0
+#define GPIO_AA_INTERRUPT_CLEAR_04_0                    MK_ADDR_CONST(0x1894)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_SECURE                     0x0
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_DUAL                       0x0
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_SCR                        GPIO_AA_SCR_04_0
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_SCRREG                     GPIO_AA_SCR_04_0
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_WORD_COUNT                         0x1
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1898
+
+// Reserved address 0x189c
+
+// Register GPIO_AA_ENABLE_CONFIG_05_0
+#define GPIO_AA_ENABLE_CONFIG_05_0                      MK_ADDR_CONST(0x18a0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_SECURE                       0x0
+#define GPIO_AA_ENABLE_CONFIG_05_0_DUAL                         0x0
+#define GPIO_AA_ENABLE_CONFIG_05_0_SCR                  GPIO_AA_SCR_05_0
+#define GPIO_AA_ENABLE_CONFIG_05_0_SCRREG                       GPIO_AA_SCR_05_0
+#define GPIO_AA_ENABLE_CONFIG_05_0_WORD_COUNT                   0x1
+#define GPIO_AA_ENABLE_CONFIG_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_05_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_RANGE                 1:1
+#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AA_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0                 MK_ADDR_CONST(0x18a4)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_SECURE                  0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DUAL                    0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_SCR                     GPIO_AA_SCR_05_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_SCRREG                  GPIO_AA_SCR_05_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                      0x1
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INPUT_05_0
+#define GPIO_AA_INPUT_05_0                      MK_ADDR_CONST(0x18a8)
+#define GPIO_AA_INPUT_05_0_SECURE                       0x0
+#define GPIO_AA_INPUT_05_0_DUAL                         0x0
+#define GPIO_AA_INPUT_05_0_SCR                  GPIO_AA_SCR_05_0
+#define GPIO_AA_INPUT_05_0_SCRREG                       GPIO_AA_SCR_05_0
+#define GPIO_AA_INPUT_05_0_WORD_COUNT                   0x1
+#define GPIO_AA_INPUT_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_05_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_INPUT_05_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_05_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_05_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AA_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_AA_INPUT_05_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AA_INPUT_05_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_05_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_05_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AA_INPUT_05_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_05_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_05_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_OUTPUT_CONTROL_05_0
+#define GPIO_AA_OUTPUT_CONTROL_05_0                     MK_ADDR_CONST(0x18ac)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_SECURE                      0x0
+#define GPIO_AA_OUTPUT_CONTROL_05_0_DUAL                        0x0
+#define GPIO_AA_OUTPUT_CONTROL_05_0_SCR                         GPIO_AA_SCR_05_0
+#define GPIO_AA_OUTPUT_CONTROL_05_0_SCRREG                      GPIO_AA_SCR_05_0
+#define GPIO_AA_OUTPUT_CONTROL_05_0_WORD_COUNT                  0x1
+#define GPIO_AA_OUTPUT_CONTROL_05_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AA_OUTPUT_VALUE_05_0
+#define GPIO_AA_OUTPUT_VALUE_05_0                       MK_ADDR_CONST(0x18b0)
+#define GPIO_AA_OUTPUT_VALUE_05_0_SECURE                        0x0
+#define GPIO_AA_OUTPUT_VALUE_05_0_DUAL                  0x0
+#define GPIO_AA_OUTPUT_VALUE_05_0_SCR                   GPIO_AA_SCR_05_0
+#define GPIO_AA_OUTPUT_VALUE_05_0_SCRREG                        GPIO_AA_SCR_05_0
+#define GPIO_AA_OUTPUT_VALUE_05_0_WORD_COUNT                    0x1
+#define GPIO_AA_OUTPUT_VALUE_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_05_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_05_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INTERRUPT_CLEAR_05_0
+#define GPIO_AA_INTERRUPT_CLEAR_05_0                    MK_ADDR_CONST(0x18b4)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_SECURE                     0x0
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_DUAL                       0x0
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_SCR                        GPIO_AA_SCR_05_0
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_SCRREG                     GPIO_AA_SCR_05_0
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_WORD_COUNT                         0x1
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x18b8
+
+// Reserved address 0x18bc
+
+// Register GPIO_AA_ENABLE_CONFIG_06_0
+#define GPIO_AA_ENABLE_CONFIG_06_0                      MK_ADDR_CONST(0x18c0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_SECURE                       0x0
+#define GPIO_AA_ENABLE_CONFIG_06_0_DUAL                         0x0
+#define GPIO_AA_ENABLE_CONFIG_06_0_SCR                  GPIO_AA_SCR_06_0
+#define GPIO_AA_ENABLE_CONFIG_06_0_SCRREG                       GPIO_AA_SCR_06_0
+#define GPIO_AA_ENABLE_CONFIG_06_0_WORD_COUNT                   0x1
+#define GPIO_AA_ENABLE_CONFIG_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_06_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_RANGE                 1:1
+#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AA_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0                 MK_ADDR_CONST(0x18c4)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_SECURE                  0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DUAL                    0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_SCR                     GPIO_AA_SCR_06_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_SCRREG                  GPIO_AA_SCR_06_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                      0x1
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INPUT_06_0
+#define GPIO_AA_INPUT_06_0                      MK_ADDR_CONST(0x18c8)
+#define GPIO_AA_INPUT_06_0_SECURE                       0x0
+#define GPIO_AA_INPUT_06_0_DUAL                         0x0
+#define GPIO_AA_INPUT_06_0_SCR                  GPIO_AA_SCR_06_0
+#define GPIO_AA_INPUT_06_0_SCRREG                       GPIO_AA_SCR_06_0
+#define GPIO_AA_INPUT_06_0_WORD_COUNT                   0x1
+#define GPIO_AA_INPUT_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_06_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_INPUT_06_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_06_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_06_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AA_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_AA_INPUT_06_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AA_INPUT_06_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_06_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_06_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AA_INPUT_06_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_06_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_06_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_OUTPUT_CONTROL_06_0
+#define GPIO_AA_OUTPUT_CONTROL_06_0                     MK_ADDR_CONST(0x18cc)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_SECURE                      0x0
+#define GPIO_AA_OUTPUT_CONTROL_06_0_DUAL                        0x0
+#define GPIO_AA_OUTPUT_CONTROL_06_0_SCR                         GPIO_AA_SCR_06_0
+#define GPIO_AA_OUTPUT_CONTROL_06_0_SCRREG                      GPIO_AA_SCR_06_0
+#define GPIO_AA_OUTPUT_CONTROL_06_0_WORD_COUNT                  0x1
+#define GPIO_AA_OUTPUT_CONTROL_06_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AA_OUTPUT_VALUE_06_0
+#define GPIO_AA_OUTPUT_VALUE_06_0                       MK_ADDR_CONST(0x18d0)
+#define GPIO_AA_OUTPUT_VALUE_06_0_SECURE                        0x0
+#define GPIO_AA_OUTPUT_VALUE_06_0_DUAL                  0x0
+#define GPIO_AA_OUTPUT_VALUE_06_0_SCR                   GPIO_AA_SCR_06_0
+#define GPIO_AA_OUTPUT_VALUE_06_0_SCRREG                        GPIO_AA_SCR_06_0
+#define GPIO_AA_OUTPUT_VALUE_06_0_WORD_COUNT                    0x1
+#define GPIO_AA_OUTPUT_VALUE_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_06_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_06_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INTERRUPT_CLEAR_06_0
+#define GPIO_AA_INTERRUPT_CLEAR_06_0                    MK_ADDR_CONST(0x18d4)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_SECURE                     0x0
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_DUAL                       0x0
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_SCR                        GPIO_AA_SCR_06_0
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_SCRREG                     GPIO_AA_SCR_06_0
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_WORD_COUNT                         0x1
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x18d8
+
+// Reserved address 0x18dc
+
+// Register GPIO_AA_ENABLE_CONFIG_07_0
+#define GPIO_AA_ENABLE_CONFIG_07_0                      MK_ADDR_CONST(0x18e0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_SECURE                       0x0
+#define GPIO_AA_ENABLE_CONFIG_07_0_DUAL                         0x0
+#define GPIO_AA_ENABLE_CONFIG_07_0_SCR                  GPIO_AA_SCR_07_0
+#define GPIO_AA_ENABLE_CONFIG_07_0_SCRREG                       GPIO_AA_SCR_07_0
+#define GPIO_AA_ENABLE_CONFIG_07_0_WORD_COUNT                   0x1
+#define GPIO_AA_ENABLE_CONFIG_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_07_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_RANGE                 1:1
+#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AA_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AA_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0                 MK_ADDR_CONST(0x18e4)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_SECURE                  0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DUAL                    0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_SCR                     GPIO_AA_SCR_07_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_SCRREG                  GPIO_AA_SCR_07_0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                      0x1
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AA_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INPUT_07_0
+#define GPIO_AA_INPUT_07_0                      MK_ADDR_CONST(0x18e8)
+#define GPIO_AA_INPUT_07_0_SECURE                       0x0
+#define GPIO_AA_INPUT_07_0_DUAL                         0x0
+#define GPIO_AA_INPUT_07_0_SCR                  GPIO_AA_SCR_07_0
+#define GPIO_AA_INPUT_07_0_SCRREG                       GPIO_AA_SCR_07_0
+#define GPIO_AA_INPUT_07_0_WORD_COUNT                   0x1
+#define GPIO_AA_INPUT_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_07_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_INPUT_07_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_07_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_07_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AA_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_AA_INPUT_07_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AA_INPUT_07_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_07_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AA_INPUT_07_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AA_INPUT_07_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_07_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_07_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_OUTPUT_CONTROL_07_0
+#define GPIO_AA_OUTPUT_CONTROL_07_0                     MK_ADDR_CONST(0x18ec)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_SECURE                      0x0
+#define GPIO_AA_OUTPUT_CONTROL_07_0_DUAL                        0x0
+#define GPIO_AA_OUTPUT_CONTROL_07_0_SCR                         GPIO_AA_SCR_07_0
+#define GPIO_AA_OUTPUT_CONTROL_07_0_SCRREG                      GPIO_AA_SCR_07_0
+#define GPIO_AA_OUTPUT_CONTROL_07_0_WORD_COUNT                  0x1
+#define GPIO_AA_OUTPUT_CONTROL_07_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AA_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AA_OUTPUT_VALUE_07_0
+#define GPIO_AA_OUTPUT_VALUE_07_0                       MK_ADDR_CONST(0x18f0)
+#define GPIO_AA_OUTPUT_VALUE_07_0_SECURE                        0x0
+#define GPIO_AA_OUTPUT_VALUE_07_0_DUAL                  0x0
+#define GPIO_AA_OUTPUT_VALUE_07_0_SCR                   GPIO_AA_SCR_07_0
+#define GPIO_AA_OUTPUT_VALUE_07_0_SCRREG                        GPIO_AA_SCR_07_0
+#define GPIO_AA_OUTPUT_VALUE_07_0_WORD_COUNT                    0x1
+#define GPIO_AA_OUTPUT_VALUE_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_07_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_07_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AA_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INTERRUPT_CLEAR_07_0
+#define GPIO_AA_INTERRUPT_CLEAR_07_0                    MK_ADDR_CONST(0x18f4)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_SECURE                     0x0
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_DUAL                       0x0
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_SCR                        GPIO_AA_SCR_07_0
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_SCRREG                     GPIO_AA_SCR_07_0
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_WORD_COUNT                         0x1
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AA_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x18f8
+
+// Reserved address 0x18fc
+
+// Register GPIO_AA_INTERRUPT_STATUS_G0_0
+#define GPIO_AA_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x1900)
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_SECURE                    0x0
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_DUAL                      0x0
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_SCR                       0
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_SCRREG                    0
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INTERRUPT_STATUS_G1_0
+#define GPIO_AA_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x1904)
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_SECURE                    0x0
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_DUAL                      0x0
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_SCR                       0
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_SCRREG                    0
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INTERRUPT_STATUS_G2_0
+#define GPIO_AA_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x1908)
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_SECURE                    0x0
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_DUAL                      0x0
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_SCR                       0
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_SCRREG                    0
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INTERRUPT_STATUS_G3_0
+#define GPIO_AA_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x190c)
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_SECURE                    0x0
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_DUAL                      0x0
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_SCR                       0
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_SCRREG                    0
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INTERRUPT_STATUS_G4_0
+#define GPIO_AA_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x1910)
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_SECURE                    0x0
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_DUAL                      0x0
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_SCR                       0
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_SCRREG                    0
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INTERRUPT_STATUS_G5_0
+#define GPIO_AA_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x1914)
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_SECURE                    0x0
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_DUAL                      0x0
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_SCR                       0
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_SCRREG                    0
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INTERRUPT_STATUS_G6_0
+#define GPIO_AA_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x1918)
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_SECURE                    0x0
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_DUAL                      0x0
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_SCR                       0
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_SCRREG                    0
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AA_INTERRUPT_STATUS_G7_0
+#define GPIO_AA_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x191c)
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_SECURE                    0x0
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_DUAL                      0x0
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_SCR                       0
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_SCRREG                    0
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AA_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x1920
+
+// Reserved address 0x1924
+
+// Reserved address 0x1928
+
+// Reserved address 0x192c
+
+// Reserved address 0x1930
+
+// Reserved address 0x1934
+
+// Reserved address 0x1938
+
+// Reserved address 0x193c
+
+// Reserved address 0x1940
+
+// Reserved address 0x1944
+
+// Reserved address 0x1948
+
+// Reserved address 0x194c
+
+// Reserved address 0x1950
+
+// Reserved address 0x1954
+
+// Reserved address 0x1958
+
+// Reserved address 0x195c
+
+// Reserved address 0x1960
+
+// Reserved address 0x1964
+
+// Reserved address 0x1968
+
+// Reserved address 0x196c
+
+// Reserved address 0x1970
+
+// Reserved address 0x1974
+
+// Reserved address 0x1978
+
+// Reserved address 0x197c
+
+// Reserved address 0x1980
+
+// Reserved address 0x1984
+
+// Reserved address 0x1988
+
+// Reserved address 0x198c
+
+// Reserved address 0x1990
+
+// Reserved address 0x1994
+
+// Reserved address 0x1998
+
+// Reserved address 0x199c
+
+// Reserved address 0x19a0
+
+// Reserved address 0x19a4
+
+// Reserved address 0x19a8
+
+// Reserved address 0x19ac
+
+// Reserved address 0x19b0
+
+// Reserved address 0x19b4
+
+// Reserved address 0x19b8
+
+// Reserved address 0x19bc
+
+// Reserved address 0x19c0
+
+// Reserved address 0x19c4
+
+// Reserved address 0x19c8
+
+// Reserved address 0x19cc
+
+// Reserved address 0x19d0
+
+// Reserved address 0x19d4
+
+// Reserved address 0x19d8
+
+// Reserved address 0x19dc
+
+// Reserved address 0x19e0
+
+// Reserved address 0x19e4
+
+// Reserved address 0x19e8
+
+// Reserved address 0x19ec
+
+// Reserved address 0x19f0
+
+// Reserved address 0x19f4
+
+// Reserved address 0x19f8
+
+// Reserved address 0x19fc
+
+// Register GPIO_BB_ENABLE_CONFIG_00_0
+#define GPIO_BB_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x1a00)
+#define GPIO_BB_ENABLE_CONFIG_00_0_SECURE                       0x0
+#define GPIO_BB_ENABLE_CONFIG_00_0_DUAL                         0x0
+#define GPIO_BB_ENABLE_CONFIG_00_0_SCR                  GPIO_BB_SCR_00_0
+#define GPIO_BB_ENABLE_CONFIG_00_0_SCRREG                       GPIO_BB_SCR_00_0
+#define GPIO_BB_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
+#define GPIO_BB_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_BB_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_BB_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
+#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_BB_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x1a04)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_BB_SCR_00_0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_BB_SCR_00_0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_INPUT_00_0
+#define GPIO_BB_INPUT_00_0                      MK_ADDR_CONST(0x1a08)
+#define GPIO_BB_INPUT_00_0_SECURE                       0x0
+#define GPIO_BB_INPUT_00_0_DUAL                         0x0
+#define GPIO_BB_INPUT_00_0_SCR                  GPIO_BB_SCR_00_0
+#define GPIO_BB_INPUT_00_0_SCRREG                       GPIO_BB_SCR_00_0
+#define GPIO_BB_INPUT_00_0_WORD_COUNT                   0x1
+#define GPIO_BB_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_BB_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_BB_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_BB_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_BB_INPUT_00_0_GPIO_IN_RANGE                        0:0
+#define GPIO_BB_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_BB_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_BB_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_BB_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_OUTPUT_CONTROL_00_0
+#define GPIO_BB_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x1a0c)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_SECURE                      0x0
+#define GPIO_BB_OUTPUT_CONTROL_00_0_DUAL                        0x0
+#define GPIO_BB_OUTPUT_CONTROL_00_0_SCR                         GPIO_BB_SCR_00_0
+#define GPIO_BB_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_BB_SCR_00_0
+#define GPIO_BB_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
+#define GPIO_BB_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_BB_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_BB_OUTPUT_VALUE_00_0
+#define GPIO_BB_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x1a10)
+#define GPIO_BB_OUTPUT_VALUE_00_0_SECURE                        0x0
+#define GPIO_BB_OUTPUT_VALUE_00_0_DUAL                  0x0
+#define GPIO_BB_OUTPUT_VALUE_00_0_SCR                   GPIO_BB_SCR_00_0
+#define GPIO_BB_OUTPUT_VALUE_00_0_SCRREG                        GPIO_BB_SCR_00_0
+#define GPIO_BB_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
+#define GPIO_BB_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_INTERRUPT_CLEAR_00_0
+#define GPIO_BB_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x1a14)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_SECURE                     0x0
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_DUAL                       0x0
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_SCR                        GPIO_BB_SCR_00_0
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_BB_SCR_00_0
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_BB_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1a18
+
+// Reserved address 0x1a1c
+
+// Register GPIO_BB_ENABLE_CONFIG_01_0
+#define GPIO_BB_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x1a20)
+#define GPIO_BB_ENABLE_CONFIG_01_0_SECURE                       0x0
+#define GPIO_BB_ENABLE_CONFIG_01_0_DUAL                         0x0
+#define GPIO_BB_ENABLE_CONFIG_01_0_SCR                  GPIO_BB_SCR_01_0
+#define GPIO_BB_ENABLE_CONFIG_01_0_SCRREG                       GPIO_BB_SCR_01_0
+#define GPIO_BB_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
+#define GPIO_BB_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_BB_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_BB_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
+#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_BB_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x1a24)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_BB_SCR_01_0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_BB_SCR_01_0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_INPUT_01_0
+#define GPIO_BB_INPUT_01_0                      MK_ADDR_CONST(0x1a28)
+#define GPIO_BB_INPUT_01_0_SECURE                       0x0
+#define GPIO_BB_INPUT_01_0_DUAL                         0x0
+#define GPIO_BB_INPUT_01_0_SCR                  GPIO_BB_SCR_01_0
+#define GPIO_BB_INPUT_01_0_SCRREG                       GPIO_BB_SCR_01_0
+#define GPIO_BB_INPUT_01_0_WORD_COUNT                   0x1
+#define GPIO_BB_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_BB_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_BB_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_BB_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_BB_INPUT_01_0_GPIO_IN_RANGE                        0:0
+#define GPIO_BB_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_BB_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_BB_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_BB_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_OUTPUT_CONTROL_01_0
+#define GPIO_BB_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x1a2c)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_SECURE                      0x0
+#define GPIO_BB_OUTPUT_CONTROL_01_0_DUAL                        0x0
+#define GPIO_BB_OUTPUT_CONTROL_01_0_SCR                         GPIO_BB_SCR_01_0
+#define GPIO_BB_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_BB_SCR_01_0
+#define GPIO_BB_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
+#define GPIO_BB_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_BB_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_BB_OUTPUT_VALUE_01_0
+#define GPIO_BB_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x1a30)
+#define GPIO_BB_OUTPUT_VALUE_01_0_SECURE                        0x0
+#define GPIO_BB_OUTPUT_VALUE_01_0_DUAL                  0x0
+#define GPIO_BB_OUTPUT_VALUE_01_0_SCR                   GPIO_BB_SCR_01_0
+#define GPIO_BB_OUTPUT_VALUE_01_0_SCRREG                        GPIO_BB_SCR_01_0
+#define GPIO_BB_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
+#define GPIO_BB_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_INTERRUPT_CLEAR_01_0
+#define GPIO_BB_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x1a34)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_SECURE                     0x0
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_DUAL                       0x0
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_SCR                        GPIO_BB_SCR_01_0
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_BB_SCR_01_0
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_BB_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1a38
+
+// Reserved address 0x1a3c
+
+// Register GPIO_BB_ENABLE_CONFIG_02_0
+#define GPIO_BB_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x1a40)
+#define GPIO_BB_ENABLE_CONFIG_02_0_SECURE                       0x0
+#define GPIO_BB_ENABLE_CONFIG_02_0_DUAL                         0x0
+#define GPIO_BB_ENABLE_CONFIG_02_0_SCR                  GPIO_BB_SCR_02_0
+#define GPIO_BB_ENABLE_CONFIG_02_0_SCRREG                       GPIO_BB_SCR_02_0
+#define GPIO_BB_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
+#define GPIO_BB_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_BB_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_BB_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
+#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_BB_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x1a44)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_BB_SCR_02_0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_BB_SCR_02_0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_INPUT_02_0
+#define GPIO_BB_INPUT_02_0                      MK_ADDR_CONST(0x1a48)
+#define GPIO_BB_INPUT_02_0_SECURE                       0x0
+#define GPIO_BB_INPUT_02_0_DUAL                         0x0
+#define GPIO_BB_INPUT_02_0_SCR                  GPIO_BB_SCR_02_0
+#define GPIO_BB_INPUT_02_0_SCRREG                       GPIO_BB_SCR_02_0
+#define GPIO_BB_INPUT_02_0_WORD_COUNT                   0x1
+#define GPIO_BB_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_BB_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_BB_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_BB_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_BB_INPUT_02_0_GPIO_IN_RANGE                        0:0
+#define GPIO_BB_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_BB_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_BB_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_BB_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_OUTPUT_CONTROL_02_0
+#define GPIO_BB_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x1a4c)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_SECURE                      0x0
+#define GPIO_BB_OUTPUT_CONTROL_02_0_DUAL                        0x0
+#define GPIO_BB_OUTPUT_CONTROL_02_0_SCR                         GPIO_BB_SCR_02_0
+#define GPIO_BB_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_BB_SCR_02_0
+#define GPIO_BB_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
+#define GPIO_BB_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_BB_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_BB_OUTPUT_VALUE_02_0
+#define GPIO_BB_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x1a50)
+#define GPIO_BB_OUTPUT_VALUE_02_0_SECURE                        0x0
+#define GPIO_BB_OUTPUT_VALUE_02_0_DUAL                  0x0
+#define GPIO_BB_OUTPUT_VALUE_02_0_SCR                   GPIO_BB_SCR_02_0
+#define GPIO_BB_OUTPUT_VALUE_02_0_SCRREG                        GPIO_BB_SCR_02_0
+#define GPIO_BB_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
+#define GPIO_BB_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_INTERRUPT_CLEAR_02_0
+#define GPIO_BB_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x1a54)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_SECURE                     0x0
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_DUAL                       0x0
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_SCR                        GPIO_BB_SCR_02_0
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_BB_SCR_02_0
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_BB_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1a58
+
+// Reserved address 0x1a5c
+
+// Register GPIO_BB_ENABLE_CONFIG_03_0
+#define GPIO_BB_ENABLE_CONFIG_03_0                      MK_ADDR_CONST(0x1a60)
+#define GPIO_BB_ENABLE_CONFIG_03_0_SECURE                       0x0
+#define GPIO_BB_ENABLE_CONFIG_03_0_DUAL                         0x0
+#define GPIO_BB_ENABLE_CONFIG_03_0_SCR                  GPIO_BB_SCR_03_0
+#define GPIO_BB_ENABLE_CONFIG_03_0_SCRREG                       GPIO_BB_SCR_03_0
+#define GPIO_BB_ENABLE_CONFIG_03_0_WORD_COUNT                   0x1
+#define GPIO_BB_ENABLE_CONFIG_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_BB_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_BB_ENABLE_CONFIG_03_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_RANGE                 1:1
+#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_BB_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_BB_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0                 MK_ADDR_CONST(0x1a64)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_SECURE                  0x0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DUAL                    0x0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_SCR                     GPIO_BB_SCR_03_0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_SCRREG                  GPIO_BB_SCR_03_0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                      0x1
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_BB_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_INPUT_03_0
+#define GPIO_BB_INPUT_03_0                      MK_ADDR_CONST(0x1a68)
+#define GPIO_BB_INPUT_03_0_SECURE                       0x0
+#define GPIO_BB_INPUT_03_0_DUAL                         0x0
+#define GPIO_BB_INPUT_03_0_SCR                  GPIO_BB_SCR_03_0
+#define GPIO_BB_INPUT_03_0_SCRREG                       GPIO_BB_SCR_03_0
+#define GPIO_BB_INPUT_03_0_WORD_COUNT                   0x1
+#define GPIO_BB_INPUT_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_03_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_BB_INPUT_03_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_03_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_BB_INPUT_03_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_BB_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_BB_INPUT_03_0_GPIO_IN_RANGE                        0:0
+#define GPIO_BB_INPUT_03_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_BB_INPUT_03_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_BB_INPUT_03_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_BB_INPUT_03_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_03_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_03_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_OUTPUT_CONTROL_03_0
+#define GPIO_BB_OUTPUT_CONTROL_03_0                     MK_ADDR_CONST(0x1a6c)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_SECURE                      0x0
+#define GPIO_BB_OUTPUT_CONTROL_03_0_DUAL                        0x0
+#define GPIO_BB_OUTPUT_CONTROL_03_0_SCR                         GPIO_BB_SCR_03_0
+#define GPIO_BB_OUTPUT_CONTROL_03_0_SCRREG                      GPIO_BB_SCR_03_0
+#define GPIO_BB_OUTPUT_CONTROL_03_0_WORD_COUNT                  0x1
+#define GPIO_BB_OUTPUT_CONTROL_03_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_BB_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_BB_OUTPUT_VALUE_03_0
+#define GPIO_BB_OUTPUT_VALUE_03_0                       MK_ADDR_CONST(0x1a70)
+#define GPIO_BB_OUTPUT_VALUE_03_0_SECURE                        0x0
+#define GPIO_BB_OUTPUT_VALUE_03_0_DUAL                  0x0
+#define GPIO_BB_OUTPUT_VALUE_03_0_SCR                   GPIO_BB_SCR_03_0
+#define GPIO_BB_OUTPUT_VALUE_03_0_SCRREG                        GPIO_BB_SCR_03_0
+#define GPIO_BB_OUTPUT_VALUE_03_0_WORD_COUNT                    0x1
+#define GPIO_BB_OUTPUT_VALUE_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_03_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_03_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_BB_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_INTERRUPT_CLEAR_03_0
+#define GPIO_BB_INTERRUPT_CLEAR_03_0                    MK_ADDR_CONST(0x1a74)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_SECURE                     0x0
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_DUAL                       0x0
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_SCR                        GPIO_BB_SCR_03_0
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_SCRREG                     GPIO_BB_SCR_03_0
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_WORD_COUNT                         0x1
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_BB_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1a78
+
+// Reserved address 0x1a7c
+
+// Reserved address 0x1a80
+
+// Reserved address 0x1a84
+
+// Reserved address 0x1a88
+
+// Reserved address 0x1a8c
+
+// Reserved address 0x1a90
+
+// Reserved address 0x1a94
+
+// Reserved address 0x1a98
+
+// Reserved address 0x1a9c
+
+// Reserved address 0x1aa0
+
+// Reserved address 0x1aa4
+
+// Reserved address 0x1aa8
+
+// Reserved address 0x1aac
+
+// Reserved address 0x1ab0
+
+// Reserved address 0x1ab4
+
+// Reserved address 0x1ab8
+
+// Reserved address 0x1abc
+
+// Reserved address 0x1ac0
+
+// Reserved address 0x1ac4
+
+// Reserved address 0x1ac8
+
+// Reserved address 0x1acc
+
+// Reserved address 0x1ad0
+
+// Reserved address 0x1ad4
+
+// Reserved address 0x1ad8
+
+// Reserved address 0x1adc
+
+// Reserved address 0x1ae0
+
+// Reserved address 0x1ae4
+
+// Reserved address 0x1ae8
+
+// Reserved address 0x1aec
+
+// Reserved address 0x1af0
+
+// Reserved address 0x1af4
+
+// Reserved address 0x1af8
+
+// Reserved address 0x1afc
+
+// Register GPIO_BB_INTERRUPT_STATUS_G0_0
+#define GPIO_BB_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x1b00)
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_SECURE                    0x0
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_DUAL                      0x0
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_SCR                       0
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_SCRREG                    0
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_INTERRUPT_STATUS_G1_0
+#define GPIO_BB_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x1b04)
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_SECURE                    0x0
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_DUAL                      0x0
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_SCR                       0
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_SCRREG                    0
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_INTERRUPT_STATUS_G2_0
+#define GPIO_BB_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x1b08)
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_SECURE                    0x0
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_DUAL                      0x0
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_SCR                       0
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_SCRREG                    0
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_INTERRUPT_STATUS_G3_0
+#define GPIO_BB_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x1b0c)
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_SECURE                    0x0
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_DUAL                      0x0
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_SCR                       0
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_SCRREG                    0
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_INTERRUPT_STATUS_G4_0
+#define GPIO_BB_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x1b10)
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_SECURE                    0x0
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_DUAL                      0x0
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_SCR                       0
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_SCRREG                    0
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_INTERRUPT_STATUS_G5_0
+#define GPIO_BB_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x1b14)
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_SECURE                    0x0
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_DUAL                      0x0
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_SCR                       0
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_SCRREG                    0
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_INTERRUPT_STATUS_G6_0
+#define GPIO_BB_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x1b18)
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_SECURE                    0x0
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_DUAL                      0x0
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_SCR                       0
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_SCRREG                    0
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_BB_INTERRUPT_STATUS_G7_0
+#define GPIO_BB_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x1b1c)
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_SECURE                    0x0
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_DUAL                      0x0
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_SCR                       0
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_SCRREG                    0
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_BB_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x1b20
+
+// Reserved address 0x1b24
+
+// Reserved address 0x1b28
+
+// Reserved address 0x1b2c
+
+// Reserved address 0x1b30
+
+// Reserved address 0x1b34
+
+// Reserved address 0x1b38
+
+// Reserved address 0x1b3c
+
+// Reserved address 0x1b40
+
+// Reserved address 0x1b44
+
+// Reserved address 0x1b48
+
+// Reserved address 0x1b4c
+
+// Reserved address 0x1b50
+
+// Reserved address 0x1b54
+
+// Reserved address 0x1b58
+
+// Reserved address 0x1b5c
+
+// Reserved address 0x1b60
+
+// Reserved address 0x1b64
+
+// Reserved address 0x1b68
+
+// Reserved address 0x1b6c
+
+// Reserved address 0x1b70
+
+// Reserved address 0x1b74
+
+// Reserved address 0x1b78
+
+// Reserved address 0x1b7c
+
+// Reserved address 0x1b80
+
+// Reserved address 0x1b84
+
+// Reserved address 0x1b88
+
+// Reserved address 0x1b8c
+
+// Reserved address 0x1b90
+
+// Reserved address 0x1b94
+
+// Reserved address 0x1b98
+
+// Reserved address 0x1b9c
+
+// Reserved address 0x1ba0
+
+// Reserved address 0x1ba4
+
+// Reserved address 0x1ba8
+
+// Reserved address 0x1bac
+
+// Reserved address 0x1bb0
+
+// Reserved address 0x1bb4
+
+// Reserved address 0x1bb8
+
+// Reserved address 0x1bbc
+
+// Reserved address 0x1bc0
+
+// Reserved address 0x1bc4
+
+// Reserved address 0x1bc8
+
+// Reserved address 0x1bcc
+
+// Reserved address 0x1bd0
+
+// Reserved address 0x1bd4
+
+// Reserved address 0x1bd8
+
+// Reserved address 0x1bdc
+
+// Reserved address 0x1be0
+
+// Reserved address 0x1be4
+
+// Reserved address 0x1be8
+
+// Reserved address 0x1bec
+
+// Reserved address 0x1bf0
+
+// Reserved address 0x1bf4
+
+// Reserved address 0x1bf8
+
+// Reserved address 0x1bfc
+
+//
+// REGISTER LIST
+//
+#define LIST_ARGPIO_AON_REGS(_op_) \
+_op_(GPIO_EE_ENABLE_CONFIG_00_0) \
+_op_(GPIO_EE_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_EE_INPUT_00_0) \
+_op_(GPIO_EE_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_EE_OUTPUT_VALUE_00_0) \
+_op_(GPIO_EE_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_EE_ENABLE_CONFIG_01_0) \
+_op_(GPIO_EE_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_EE_INPUT_01_0) \
+_op_(GPIO_EE_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_EE_OUTPUT_VALUE_01_0) \
+_op_(GPIO_EE_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_EE_ENABLE_CONFIG_02_0) \
+_op_(GPIO_EE_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_EE_INPUT_02_0) \
+_op_(GPIO_EE_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_EE_OUTPUT_VALUE_02_0) \
+_op_(GPIO_EE_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_EE_ENABLE_CONFIG_03_0) \
+_op_(GPIO_EE_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_EE_INPUT_03_0) \
+_op_(GPIO_EE_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_EE_OUTPUT_VALUE_03_0) \
+_op_(GPIO_EE_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_EE_ENABLE_CONFIG_04_0) \
+_op_(GPIO_EE_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_EE_INPUT_04_0) \
+_op_(GPIO_EE_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_EE_OUTPUT_VALUE_04_0) \
+_op_(GPIO_EE_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_EE_ENABLE_CONFIG_05_0) \
+_op_(GPIO_EE_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_EE_INPUT_05_0) \
+_op_(GPIO_EE_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_EE_OUTPUT_VALUE_05_0) \
+_op_(GPIO_EE_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_EE_ENABLE_CONFIG_06_0) \
+_op_(GPIO_EE_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_EE_INPUT_06_0) \
+_op_(GPIO_EE_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_EE_OUTPUT_VALUE_06_0) \
+_op_(GPIO_EE_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_EE_ENABLE_CONFIG_07_0) \
+_op_(GPIO_EE_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_EE_INPUT_07_0) \
+_op_(GPIO_EE_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_EE_OUTPUT_VALUE_07_0) \
+_op_(GPIO_EE_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_EE_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_EE_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_EE_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_EE_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_EE_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_EE_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_EE_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_EE_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_GG_ENABLE_CONFIG_00_0) \
+_op_(GPIO_GG_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_GG_INPUT_00_0) \
+_op_(GPIO_GG_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_GG_OUTPUT_VALUE_00_0) \
+_op_(GPIO_GG_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_GG_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_GG_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_GG_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_GG_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_GG_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_GG_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_GG_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_GG_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_CC_ENABLE_CONFIG_00_0) \
+_op_(GPIO_CC_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_CC_INPUT_00_0) \
+_op_(GPIO_CC_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_CC_OUTPUT_VALUE_00_0) \
+_op_(GPIO_CC_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_CC_ENABLE_CONFIG_01_0) \
+_op_(GPIO_CC_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_CC_INPUT_01_0) \
+_op_(GPIO_CC_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_CC_OUTPUT_VALUE_01_0) \
+_op_(GPIO_CC_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_CC_ENABLE_CONFIG_02_0) \
+_op_(GPIO_CC_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_CC_INPUT_02_0) \
+_op_(GPIO_CC_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_CC_OUTPUT_VALUE_02_0) \
+_op_(GPIO_CC_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_CC_ENABLE_CONFIG_03_0) \
+_op_(GPIO_CC_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_CC_INPUT_03_0) \
+_op_(GPIO_CC_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_CC_OUTPUT_VALUE_03_0) \
+_op_(GPIO_CC_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_CC_ENABLE_CONFIG_04_0) \
+_op_(GPIO_CC_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_CC_INPUT_04_0) \
+_op_(GPIO_CC_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_CC_OUTPUT_VALUE_04_0) \
+_op_(GPIO_CC_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_CC_ENABLE_CONFIG_05_0) \
+_op_(GPIO_CC_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_CC_INPUT_05_0) \
+_op_(GPIO_CC_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_CC_OUTPUT_VALUE_05_0) \
+_op_(GPIO_CC_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_CC_ENABLE_CONFIG_06_0) \
+_op_(GPIO_CC_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_CC_INPUT_06_0) \
+_op_(GPIO_CC_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_CC_OUTPUT_VALUE_06_0) \
+_op_(GPIO_CC_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_CC_ENABLE_CONFIG_07_0) \
+_op_(GPIO_CC_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_CC_INPUT_07_0) \
+_op_(GPIO_CC_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_CC_OUTPUT_VALUE_07_0) \
+_op_(GPIO_CC_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_CC_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_CC_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_CC_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_CC_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_CC_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_CC_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_CC_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_CC_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_DD_ENABLE_CONFIG_00_0) \
+_op_(GPIO_DD_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_DD_INPUT_00_0) \
+_op_(GPIO_DD_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_DD_OUTPUT_VALUE_00_0) \
+_op_(GPIO_DD_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_DD_ENABLE_CONFIG_01_0) \
+_op_(GPIO_DD_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_DD_INPUT_01_0) \
+_op_(GPIO_DD_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_DD_OUTPUT_VALUE_01_0) \
+_op_(GPIO_DD_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_DD_ENABLE_CONFIG_02_0) \
+_op_(GPIO_DD_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_DD_INPUT_02_0) \
+_op_(GPIO_DD_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_DD_OUTPUT_VALUE_02_0) \
+_op_(GPIO_DD_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_DD_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_DD_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_DD_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_DD_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_DD_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_DD_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_DD_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_DD_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_AA_ENABLE_CONFIG_00_0) \
+_op_(GPIO_AA_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_AA_INPUT_00_0) \
+_op_(GPIO_AA_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_AA_OUTPUT_VALUE_00_0) \
+_op_(GPIO_AA_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_AA_ENABLE_CONFIG_01_0) \
+_op_(GPIO_AA_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_AA_INPUT_01_0) \
+_op_(GPIO_AA_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_AA_OUTPUT_VALUE_01_0) \
+_op_(GPIO_AA_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_AA_ENABLE_CONFIG_02_0) \
+_op_(GPIO_AA_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_AA_INPUT_02_0) \
+_op_(GPIO_AA_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_AA_OUTPUT_VALUE_02_0) \
+_op_(GPIO_AA_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_AA_ENABLE_CONFIG_03_0) \
+_op_(GPIO_AA_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_AA_INPUT_03_0) \
+_op_(GPIO_AA_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_AA_OUTPUT_VALUE_03_0) \
+_op_(GPIO_AA_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_AA_ENABLE_CONFIG_04_0) \
+_op_(GPIO_AA_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_AA_INPUT_04_0) \
+_op_(GPIO_AA_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_AA_OUTPUT_VALUE_04_0) \
+_op_(GPIO_AA_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_AA_ENABLE_CONFIG_05_0) \
+_op_(GPIO_AA_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_AA_INPUT_05_0) \
+_op_(GPIO_AA_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_AA_OUTPUT_VALUE_05_0) \
+_op_(GPIO_AA_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_AA_ENABLE_CONFIG_06_0) \
+_op_(GPIO_AA_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_AA_INPUT_06_0) \
+_op_(GPIO_AA_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_AA_OUTPUT_VALUE_06_0) \
+_op_(GPIO_AA_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_AA_ENABLE_CONFIG_07_0) \
+_op_(GPIO_AA_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_AA_INPUT_07_0) \
+_op_(GPIO_AA_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_AA_OUTPUT_VALUE_07_0) \
+_op_(GPIO_AA_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_AA_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_AA_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_AA_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_AA_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_AA_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_AA_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_AA_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_AA_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_BB_ENABLE_CONFIG_00_0) \
+_op_(GPIO_BB_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_BB_INPUT_00_0) \
+_op_(GPIO_BB_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_BB_OUTPUT_VALUE_00_0) \
+_op_(GPIO_BB_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_BB_ENABLE_CONFIG_01_0) \
+_op_(GPIO_BB_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_BB_INPUT_01_0) \
+_op_(GPIO_BB_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_BB_OUTPUT_VALUE_01_0) \
+_op_(GPIO_BB_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_BB_ENABLE_CONFIG_02_0) \
+_op_(GPIO_BB_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_BB_INPUT_02_0) \
+_op_(GPIO_BB_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_BB_OUTPUT_VALUE_02_0) \
+_op_(GPIO_BB_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_BB_ENABLE_CONFIG_03_0) \
+_op_(GPIO_BB_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_BB_INPUT_03_0) \
+_op_(GPIO_BB_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_BB_OUTPUT_VALUE_03_0) \
+_op_(GPIO_BB_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_BB_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_BB_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_BB_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_BB_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_BB_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_BB_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_BB_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_BB_INTERRUPT_STATUS_G7_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_GPIO       0x00001000
+
+//
+// ARGPIO_AON REGISTER BANKS
+//
+
+#define GPIO0_FIRST_REG 0x1000 // GPIO_EE_ENABLE_CONFIG_00_0
+#define GPIO0_LAST_REG 0x1014 // GPIO_EE_INTERRUPT_CLEAR_00_0
+#define GPIO1_FIRST_REG 0x1020 // GPIO_EE_ENABLE_CONFIG_01_0
+#define GPIO1_LAST_REG 0x1034 // GPIO_EE_INTERRUPT_CLEAR_01_0
+#define GPIO2_FIRST_REG 0x1040 // GPIO_EE_ENABLE_CONFIG_02_0
+#define GPIO2_LAST_REG 0x1054 // GPIO_EE_INTERRUPT_CLEAR_02_0
+#define GPIO3_FIRST_REG 0x1060 // GPIO_EE_ENABLE_CONFIG_03_0
+#define GPIO3_LAST_REG 0x1074 // GPIO_EE_INTERRUPT_CLEAR_03_0
+#define GPIO4_FIRST_REG 0x1080 // GPIO_EE_ENABLE_CONFIG_04_0
+#define GPIO4_LAST_REG 0x1094 // GPIO_EE_INTERRUPT_CLEAR_04_0
+#define GPIO5_FIRST_REG 0x10a0 // GPIO_EE_ENABLE_CONFIG_05_0
+#define GPIO5_LAST_REG 0x10b4 // GPIO_EE_INTERRUPT_CLEAR_05_0
+#define GPIO6_FIRST_REG 0x10c0 // GPIO_EE_ENABLE_CONFIG_06_0
+#define GPIO6_LAST_REG 0x10d4 // GPIO_EE_INTERRUPT_CLEAR_06_0
+#define GPIO7_FIRST_REG 0x10e0 // GPIO_EE_ENABLE_CONFIG_07_0
+#define GPIO7_LAST_REG 0x10f4 // GPIO_EE_INTERRUPT_CLEAR_07_0
+#define GPIO8_FIRST_REG 0x1100 // GPIO_EE_INTERRUPT_STATUS_G0_0
+#define GPIO8_LAST_REG 0x111c // GPIO_EE_INTERRUPT_STATUS_G7_0
+#define GPIO9_FIRST_REG 0x1200 // GPIO_GG_ENABLE_CONFIG_00_0
+#define GPIO9_LAST_REG 0x1214 // GPIO_GG_INTERRUPT_CLEAR_00_0
+#define GPIO10_FIRST_REG 0x1300 // GPIO_GG_INTERRUPT_STATUS_G0_0
+#define GPIO10_LAST_REG 0x131c // GPIO_GG_INTERRUPT_STATUS_G7_0
+#define GPIO11_FIRST_REG 0x1400 // GPIO_CC_ENABLE_CONFIG_00_0
+#define GPIO11_LAST_REG 0x1414 // GPIO_CC_INTERRUPT_CLEAR_00_0
+#define GPIO12_FIRST_REG 0x1420 // GPIO_CC_ENABLE_CONFIG_01_0
+#define GPIO12_LAST_REG 0x1434 // GPIO_CC_INTERRUPT_CLEAR_01_0
+#define GPIO13_FIRST_REG 0x1440 // GPIO_CC_ENABLE_CONFIG_02_0
+#define GPIO13_LAST_REG 0x1454 // GPIO_CC_INTERRUPT_CLEAR_02_0
+#define GPIO14_FIRST_REG 0x1460 // GPIO_CC_ENABLE_CONFIG_03_0
+#define GPIO14_LAST_REG 0x1474 // GPIO_CC_INTERRUPT_CLEAR_03_0
+#define GPIO15_FIRST_REG 0x1480 // GPIO_CC_ENABLE_CONFIG_04_0
+#define GPIO15_LAST_REG 0x1494 // GPIO_CC_INTERRUPT_CLEAR_04_0
+#define GPIO16_FIRST_REG 0x14a0 // GPIO_CC_ENABLE_CONFIG_05_0
+#define GPIO16_LAST_REG 0x14b4 // GPIO_CC_INTERRUPT_CLEAR_05_0
+#define GPIO17_FIRST_REG 0x14c0 // GPIO_CC_ENABLE_CONFIG_06_0
+#define GPIO17_LAST_REG 0x14d4 // GPIO_CC_INTERRUPT_CLEAR_06_0
+#define GPIO18_FIRST_REG 0x14e0 // GPIO_CC_ENABLE_CONFIG_07_0
+#define GPIO18_LAST_REG 0x14f4 // GPIO_CC_INTERRUPT_CLEAR_07_0
+#define GPIO19_FIRST_REG 0x1500 // GPIO_CC_INTERRUPT_STATUS_G0_0
+#define GPIO19_LAST_REG 0x151c // GPIO_CC_INTERRUPT_STATUS_G7_0
+#define GPIO20_FIRST_REG 0x1600 // GPIO_DD_ENABLE_CONFIG_00_0
+#define GPIO20_LAST_REG 0x1614 // GPIO_DD_INTERRUPT_CLEAR_00_0
+#define GPIO21_FIRST_REG 0x1620 // GPIO_DD_ENABLE_CONFIG_01_0
+#define GPIO21_LAST_REG 0x1634 // GPIO_DD_INTERRUPT_CLEAR_01_0
+#define GPIO22_FIRST_REG 0x1640 // GPIO_DD_ENABLE_CONFIG_02_0
+#define GPIO22_LAST_REG 0x1654 // GPIO_DD_INTERRUPT_CLEAR_02_0
+#define GPIO23_FIRST_REG 0x1700 // GPIO_DD_INTERRUPT_STATUS_G0_0
+#define GPIO23_LAST_REG 0x171c // GPIO_DD_INTERRUPT_STATUS_G7_0
+#define GPIO24_FIRST_REG 0x1800 // GPIO_AA_ENABLE_CONFIG_00_0
+#define GPIO24_LAST_REG 0x1814 // GPIO_AA_INTERRUPT_CLEAR_00_0
+#define GPIO25_FIRST_REG 0x1820 // GPIO_AA_ENABLE_CONFIG_01_0
+#define GPIO25_LAST_REG 0x1834 // GPIO_AA_INTERRUPT_CLEAR_01_0
+#define GPIO26_FIRST_REG 0x1840 // GPIO_AA_ENABLE_CONFIG_02_0
+#define GPIO26_LAST_REG 0x1854 // GPIO_AA_INTERRUPT_CLEAR_02_0
+#define GPIO27_FIRST_REG 0x1860 // GPIO_AA_ENABLE_CONFIG_03_0
+#define GPIO27_LAST_REG 0x1874 // GPIO_AA_INTERRUPT_CLEAR_03_0
+#define GPIO28_FIRST_REG 0x1880 // GPIO_AA_ENABLE_CONFIG_04_0
+#define GPIO28_LAST_REG 0x1894 // GPIO_AA_INTERRUPT_CLEAR_04_0
+#define GPIO29_FIRST_REG 0x18a0 // GPIO_AA_ENABLE_CONFIG_05_0
+#define GPIO29_LAST_REG 0x18b4 // GPIO_AA_INTERRUPT_CLEAR_05_0
+#define GPIO30_FIRST_REG 0x18c0 // GPIO_AA_ENABLE_CONFIG_06_0
+#define GPIO30_LAST_REG 0x18d4 // GPIO_AA_INTERRUPT_CLEAR_06_0
+#define GPIO31_FIRST_REG 0x18e0 // GPIO_AA_ENABLE_CONFIG_07_0
+#define GPIO31_LAST_REG 0x18f4 // GPIO_AA_INTERRUPT_CLEAR_07_0
+#define GPIO32_FIRST_REG 0x1900 // GPIO_AA_INTERRUPT_STATUS_G0_0
+#define GPIO32_LAST_REG 0x191c // GPIO_AA_INTERRUPT_STATUS_G7_0
+#define GPIO33_FIRST_REG 0x1a00 // GPIO_BB_ENABLE_CONFIG_00_0
+#define GPIO33_LAST_REG 0x1a14 // GPIO_BB_INTERRUPT_CLEAR_00_0
+#define GPIO34_FIRST_REG 0x1a20 // GPIO_BB_ENABLE_CONFIG_01_0
+#define GPIO34_LAST_REG 0x1a34 // GPIO_BB_INTERRUPT_CLEAR_01_0
+#define GPIO35_FIRST_REG 0x1a40 // GPIO_BB_ENABLE_CONFIG_02_0
+#define GPIO35_LAST_REG 0x1a54 // GPIO_BB_INTERRUPT_CLEAR_02_0
+#define GPIO36_FIRST_REG 0x1a60 // GPIO_BB_ENABLE_CONFIG_03_0
+#define GPIO36_LAST_REG 0x1a74 // GPIO_BB_INTERRUPT_CLEAR_03_0
+#define GPIO37_FIRST_REG 0x1b00 // GPIO_BB_INTERRUPT_STATUS_G0_0
+#define GPIO37_LAST_REG 0x1b1c // GPIO_BB_INTERRUPT_STATUS_G7_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARGPIO_AON_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argpio_sw.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argpio_sw.h
new file mode 100644
index 0000000..4af846b
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argpio_sw.h
@@ -0,0 +1,148503 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARGPIO_H_INC
+#define ARGPIO_H_INC
+#define NV_MOBILE_ARGPIO_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARGPIO_H_SCRREG_NOMENCLATURE EXACT
+
+
+// Register GPIO_A_VM_00_0
+#define GPIO_A_VM_00_0                  MK_ADDR_CONST(0x0)
+#define GPIO_A_VM_00_0_SECURE                   0x0
+#define GPIO_A_VM_00_0_DUAL                     0x0
+#define GPIO_A_VM_00_0_SCR                      GPIO_CTL0_VM_SCR_0
+#define GPIO_A_VM_00_0_SCRREG                   GPIO_CTL0_VM_SCR_0
+#define GPIO_A_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_A_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_A_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM1_SHIFT)
+#define GPIO_A_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_A_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_A_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_A_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_A_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_A_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM2_SHIFT)
+#define GPIO_A_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_A_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_A_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_A_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_A_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_A_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM3_SHIFT)
+#define GPIO_A_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_A_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_A_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_A_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_A_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_A_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM4_SHIFT)
+#define GPIO_A_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_A_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_A_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_A_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_A_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_A_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM5_SHIFT)
+#define GPIO_A_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_A_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_A_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_A_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_A_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_A_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM6_SHIFT)
+#define GPIO_A_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_A_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_A_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_A_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_A_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_A_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM7_SHIFT)
+#define GPIO_A_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_A_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_A_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_A_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_A_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_A_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_00_0_VM8_SHIFT)
+#define GPIO_A_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_A_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_A_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_A_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_A_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_SCR_00_0
+#define GPIO_A_SCR_00_0                 MK_ADDR_CONST(0x4)
+#define GPIO_A_SCR_00_0_SECURE                  0x0
+#define GPIO_A_SCR_00_0_DUAL                    0x0
+#define GPIO_A_SCR_00_0_SCR                     0
+#define GPIO_A_SCR_00_0_SCRREG                  0
+#define GPIO_A_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_A_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_A_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_A_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_A_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_A_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_A_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_A_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_A_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_A_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_A_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_A_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_A_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_A_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_A_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_A_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_A_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_A_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_A_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR7_SHIFT)
+#define GPIO_A_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_A_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR6_SHIFT)
+#define GPIO_A_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_A_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR5_SHIFT)
+#define GPIO_A_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_A_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR4_SHIFT)
+#define GPIO_A_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_A_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR3_SHIFT)
+#define GPIO_A_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_A_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR2_SHIFT)
+#define GPIO_A_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_A_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR1_SHIFT)
+#define GPIO_A_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_A_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_PR0_SHIFT)
+#define GPIO_A_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_A_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G7W_SHIFT)
+#define GPIO_A_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_A_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G6W_SHIFT)
+#define GPIO_A_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_A_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G5W_SHIFT)
+#define GPIO_A_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_A_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G4W_SHIFT)
+#define GPIO_A_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_A_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G3W_SHIFT)
+#define GPIO_A_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_A_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G2W_SHIFT)
+#define GPIO_A_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_A_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G1W_SHIFT)
+#define GPIO_A_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_A_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G0W_SHIFT)
+#define GPIO_A_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_A_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G7R_SHIFT)
+#define GPIO_A_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_A_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G6R_SHIFT)
+#define GPIO_A_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_A_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G5R_SHIFT)
+#define GPIO_A_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_A_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G4R_SHIFT)
+#define GPIO_A_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_A_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G3R_SHIFT)
+#define GPIO_A_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_A_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G2R_SHIFT)
+#define GPIO_A_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_A_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G1R_SHIFT)
+#define GPIO_A_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_A_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_00_0_G0R_SHIFT)
+#define GPIO_A_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_A_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_A_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_VM_01_0
+#define GPIO_A_VM_01_0                  MK_ADDR_CONST(0x8)
+#define GPIO_A_VM_01_0_SECURE                   0x0
+#define GPIO_A_VM_01_0_DUAL                     0x0
+#define GPIO_A_VM_01_0_SCR                      GPIO_CTL0_VM_SCR_0
+#define GPIO_A_VM_01_0_SCRREG                   GPIO_CTL0_VM_SCR_0
+#define GPIO_A_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_A_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_A_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM1_SHIFT)
+#define GPIO_A_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_A_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_A_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_A_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_A_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_A_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM2_SHIFT)
+#define GPIO_A_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_A_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_A_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_A_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_A_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_A_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM3_SHIFT)
+#define GPIO_A_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_A_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_A_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_A_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_A_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_A_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM4_SHIFT)
+#define GPIO_A_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_A_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_A_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_A_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_A_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_A_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM5_SHIFT)
+#define GPIO_A_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_A_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_A_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_A_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_A_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_A_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM6_SHIFT)
+#define GPIO_A_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_A_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_A_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_A_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_A_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_A_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM7_SHIFT)
+#define GPIO_A_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_A_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_A_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_A_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_A_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_A_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_01_0_VM8_SHIFT)
+#define GPIO_A_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_A_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_A_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_A_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_A_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_SCR_01_0
+#define GPIO_A_SCR_01_0                 MK_ADDR_CONST(0xc)
+#define GPIO_A_SCR_01_0_SECURE                  0x0
+#define GPIO_A_SCR_01_0_DUAL                    0x0
+#define GPIO_A_SCR_01_0_SCR                     0
+#define GPIO_A_SCR_01_0_SCRREG                  0
+#define GPIO_A_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_A_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_A_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_A_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_A_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_A_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_A_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_A_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_A_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_A_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_A_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_A_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_A_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_A_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_A_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_A_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_A_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_A_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_A_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR7_SHIFT)
+#define GPIO_A_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_A_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR6_SHIFT)
+#define GPIO_A_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_A_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR5_SHIFT)
+#define GPIO_A_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_A_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR4_SHIFT)
+#define GPIO_A_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_A_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR3_SHIFT)
+#define GPIO_A_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_A_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR2_SHIFT)
+#define GPIO_A_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_A_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR1_SHIFT)
+#define GPIO_A_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_A_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_PR0_SHIFT)
+#define GPIO_A_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_A_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G7W_SHIFT)
+#define GPIO_A_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_A_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G6W_SHIFT)
+#define GPIO_A_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_A_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G5W_SHIFT)
+#define GPIO_A_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_A_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G4W_SHIFT)
+#define GPIO_A_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_A_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G3W_SHIFT)
+#define GPIO_A_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_A_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G2W_SHIFT)
+#define GPIO_A_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_A_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G1W_SHIFT)
+#define GPIO_A_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_A_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G0W_SHIFT)
+#define GPIO_A_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_A_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G7R_SHIFT)
+#define GPIO_A_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_A_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G6R_SHIFT)
+#define GPIO_A_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_A_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G5R_SHIFT)
+#define GPIO_A_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_A_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G4R_SHIFT)
+#define GPIO_A_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_A_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G3R_SHIFT)
+#define GPIO_A_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_A_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G2R_SHIFT)
+#define GPIO_A_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_A_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G1R_SHIFT)
+#define GPIO_A_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_A_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_01_0_G0R_SHIFT)
+#define GPIO_A_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_A_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_A_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_VM_02_0
+#define GPIO_A_VM_02_0                  MK_ADDR_CONST(0x10)
+#define GPIO_A_VM_02_0_SECURE                   0x0
+#define GPIO_A_VM_02_0_DUAL                     0x0
+#define GPIO_A_VM_02_0_SCR                      GPIO_CTL0_VM_SCR_0
+#define GPIO_A_VM_02_0_SCRREG                   GPIO_CTL0_VM_SCR_0
+#define GPIO_A_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_A_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_A_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM1_SHIFT)
+#define GPIO_A_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_A_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_A_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_A_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_A_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_A_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM2_SHIFT)
+#define GPIO_A_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_A_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_A_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_A_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_A_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_A_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM3_SHIFT)
+#define GPIO_A_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_A_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_A_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_A_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_A_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_A_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM4_SHIFT)
+#define GPIO_A_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_A_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_A_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_A_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_A_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_A_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM5_SHIFT)
+#define GPIO_A_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_A_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_A_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_A_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_A_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_A_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM6_SHIFT)
+#define GPIO_A_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_A_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_A_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_A_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_A_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_A_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM7_SHIFT)
+#define GPIO_A_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_A_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_A_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_A_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_A_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_A_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_02_0_VM8_SHIFT)
+#define GPIO_A_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_A_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_A_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_A_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_A_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_SCR_02_0
+#define GPIO_A_SCR_02_0                 MK_ADDR_CONST(0x14)
+#define GPIO_A_SCR_02_0_SECURE                  0x0
+#define GPIO_A_SCR_02_0_DUAL                    0x0
+#define GPIO_A_SCR_02_0_SCR                     0
+#define GPIO_A_SCR_02_0_SCRREG                  0
+#define GPIO_A_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_A_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_A_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_A_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_A_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_A_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_A_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_A_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_A_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_A_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_A_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_A_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_A_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_A_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_A_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_A_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_A_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_A_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_A_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR7_SHIFT)
+#define GPIO_A_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_A_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR6_SHIFT)
+#define GPIO_A_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_A_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR5_SHIFT)
+#define GPIO_A_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_A_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR4_SHIFT)
+#define GPIO_A_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_A_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR3_SHIFT)
+#define GPIO_A_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_A_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR2_SHIFT)
+#define GPIO_A_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_A_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR1_SHIFT)
+#define GPIO_A_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_A_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_PR0_SHIFT)
+#define GPIO_A_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_A_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G7W_SHIFT)
+#define GPIO_A_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_A_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G6W_SHIFT)
+#define GPIO_A_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_A_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G5W_SHIFT)
+#define GPIO_A_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_A_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G4W_SHIFT)
+#define GPIO_A_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_A_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G3W_SHIFT)
+#define GPIO_A_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_A_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G2W_SHIFT)
+#define GPIO_A_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_A_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G1W_SHIFT)
+#define GPIO_A_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_A_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G0W_SHIFT)
+#define GPIO_A_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_A_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G7R_SHIFT)
+#define GPIO_A_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_A_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G6R_SHIFT)
+#define GPIO_A_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_A_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G5R_SHIFT)
+#define GPIO_A_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_A_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G4R_SHIFT)
+#define GPIO_A_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_A_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G3R_SHIFT)
+#define GPIO_A_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_A_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G2R_SHIFT)
+#define GPIO_A_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_A_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G1R_SHIFT)
+#define GPIO_A_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_A_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_02_0_G0R_SHIFT)
+#define GPIO_A_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_A_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_A_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_VM_03_0
+#define GPIO_A_VM_03_0                  MK_ADDR_CONST(0x18)
+#define GPIO_A_VM_03_0_SECURE                   0x0
+#define GPIO_A_VM_03_0_DUAL                     0x0
+#define GPIO_A_VM_03_0_SCR                      GPIO_CTL0_VM_SCR_0
+#define GPIO_A_VM_03_0_SCRREG                   GPIO_CTL0_VM_SCR_0
+#define GPIO_A_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_A_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_A_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM1_SHIFT)
+#define GPIO_A_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_A_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_A_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_A_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_A_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_A_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM2_SHIFT)
+#define GPIO_A_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_A_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_A_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_A_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_A_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_A_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM3_SHIFT)
+#define GPIO_A_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_A_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_A_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_A_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_A_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_A_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM4_SHIFT)
+#define GPIO_A_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_A_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_A_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_A_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_A_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_A_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM5_SHIFT)
+#define GPIO_A_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_A_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_A_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_A_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_A_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_A_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM6_SHIFT)
+#define GPIO_A_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_A_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_A_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_A_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_A_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_A_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM7_SHIFT)
+#define GPIO_A_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_A_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_A_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_A_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_A_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_A_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_03_0_VM8_SHIFT)
+#define GPIO_A_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_A_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_A_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_A_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_A_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_SCR_03_0
+#define GPIO_A_SCR_03_0                 MK_ADDR_CONST(0x1c)
+#define GPIO_A_SCR_03_0_SECURE                  0x0
+#define GPIO_A_SCR_03_0_DUAL                    0x0
+#define GPIO_A_SCR_03_0_SCR                     0
+#define GPIO_A_SCR_03_0_SCRREG                  0
+#define GPIO_A_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_A_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_A_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_A_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_A_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_A_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_A_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_A_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_A_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_A_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_A_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_A_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_A_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_A_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_A_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_A_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_A_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_A_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_A_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR7_SHIFT)
+#define GPIO_A_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_A_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR6_SHIFT)
+#define GPIO_A_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_A_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR5_SHIFT)
+#define GPIO_A_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_A_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR4_SHIFT)
+#define GPIO_A_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_A_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR3_SHIFT)
+#define GPIO_A_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_A_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR2_SHIFT)
+#define GPIO_A_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_A_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR1_SHIFT)
+#define GPIO_A_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_A_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_PR0_SHIFT)
+#define GPIO_A_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_A_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G7W_SHIFT)
+#define GPIO_A_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_A_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G6W_SHIFT)
+#define GPIO_A_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_A_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G5W_SHIFT)
+#define GPIO_A_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_A_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G4W_SHIFT)
+#define GPIO_A_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_A_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G3W_SHIFT)
+#define GPIO_A_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_A_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G2W_SHIFT)
+#define GPIO_A_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_A_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G1W_SHIFT)
+#define GPIO_A_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_A_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G0W_SHIFT)
+#define GPIO_A_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_A_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G7R_SHIFT)
+#define GPIO_A_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_A_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G6R_SHIFT)
+#define GPIO_A_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_A_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G5R_SHIFT)
+#define GPIO_A_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_A_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G4R_SHIFT)
+#define GPIO_A_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_A_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G3R_SHIFT)
+#define GPIO_A_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_A_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G2R_SHIFT)
+#define GPIO_A_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_A_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G1R_SHIFT)
+#define GPIO_A_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_A_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_03_0_G0R_SHIFT)
+#define GPIO_A_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_A_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_A_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_VM_04_0
+#define GPIO_A_VM_04_0                  MK_ADDR_CONST(0x20)
+#define GPIO_A_VM_04_0_SECURE                   0x0
+#define GPIO_A_VM_04_0_DUAL                     0x0
+#define GPIO_A_VM_04_0_SCR                      GPIO_CTL0_VM_SCR_0
+#define GPIO_A_VM_04_0_SCRREG                   GPIO_CTL0_VM_SCR_0
+#define GPIO_A_VM_04_0_WORD_COUNT                       0x1
+#define GPIO_A_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_A_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM1_SHIFT)
+#define GPIO_A_VM_04_0_VM1_RANGE                        1:0
+#define GPIO_A_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_A_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_A_VM_04_0_VM1_WOFFSET                      0x0
+#define GPIO_A_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_A_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM2_SHIFT)
+#define GPIO_A_VM_04_0_VM2_RANGE                        3:2
+#define GPIO_A_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_A_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_A_VM_04_0_VM2_WOFFSET                      0x0
+#define GPIO_A_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_A_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM3_SHIFT)
+#define GPIO_A_VM_04_0_VM3_RANGE                        5:4
+#define GPIO_A_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_A_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_A_VM_04_0_VM3_WOFFSET                      0x0
+#define GPIO_A_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_A_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM4_SHIFT)
+#define GPIO_A_VM_04_0_VM4_RANGE                        7:6
+#define GPIO_A_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_A_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_A_VM_04_0_VM4_WOFFSET                      0x0
+#define GPIO_A_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_A_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM5_SHIFT)
+#define GPIO_A_VM_04_0_VM5_RANGE                        9:8
+#define GPIO_A_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_A_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_A_VM_04_0_VM5_WOFFSET                      0x0
+#define GPIO_A_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_A_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM6_SHIFT)
+#define GPIO_A_VM_04_0_VM6_RANGE                        11:10
+#define GPIO_A_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_A_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_A_VM_04_0_VM6_WOFFSET                      0x0
+#define GPIO_A_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_A_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM7_SHIFT)
+#define GPIO_A_VM_04_0_VM7_RANGE                        13:12
+#define GPIO_A_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_A_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_A_VM_04_0_VM7_WOFFSET                      0x0
+#define GPIO_A_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_A_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_04_0_VM8_SHIFT)
+#define GPIO_A_VM_04_0_VM8_RANGE                        15:14
+#define GPIO_A_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_A_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_A_VM_04_0_VM8_WOFFSET                      0x0
+#define GPIO_A_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_SCR_04_0
+#define GPIO_A_SCR_04_0                 MK_ADDR_CONST(0x24)
+#define GPIO_A_SCR_04_0_SECURE                  0x0
+#define GPIO_A_SCR_04_0_DUAL                    0x0
+#define GPIO_A_SCR_04_0_SCR                     0
+#define GPIO_A_SCR_04_0_SCRREG                  0
+#define GPIO_A_SCR_04_0_WORD_COUNT                      0x1
+#define GPIO_A_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_A_SCR_04_0_SEC_LCK_RANGE                   29:29
+#define GPIO_A_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_04_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_A_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_A_SCR_04_0_SEC_WEN_RANGE                   28:28
+#define GPIO_A_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_04_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_A_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_A_SCR_04_0_SEC_REN_RANGE                   27:27
+#define GPIO_A_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_04_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_A_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_A_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_A_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_A_SCR_04_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_A_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_A_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_A_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_A_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_A_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR7_SHIFT)
+#define GPIO_A_SCR_04_0_PR7_RANGE                       23:23
+#define GPIO_A_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_04_0_PR7_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR6_SHIFT)
+#define GPIO_A_SCR_04_0_PR6_RANGE                       22:22
+#define GPIO_A_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_04_0_PR6_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR5_SHIFT)
+#define GPIO_A_SCR_04_0_PR5_RANGE                       21:21
+#define GPIO_A_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_04_0_PR5_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR4_SHIFT)
+#define GPIO_A_SCR_04_0_PR4_RANGE                       20:20
+#define GPIO_A_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_04_0_PR4_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR3_SHIFT)
+#define GPIO_A_SCR_04_0_PR3_RANGE                       19:19
+#define GPIO_A_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_04_0_PR3_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR2_SHIFT)
+#define GPIO_A_SCR_04_0_PR2_RANGE                       18:18
+#define GPIO_A_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_04_0_PR2_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR1_SHIFT)
+#define GPIO_A_SCR_04_0_PR1_RANGE                       17:17
+#define GPIO_A_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_04_0_PR1_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_PR0_SHIFT)
+#define GPIO_A_SCR_04_0_PR0_RANGE                       16:16
+#define GPIO_A_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_04_0_PR0_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G7W_SHIFT)
+#define GPIO_A_SCR_04_0_G7W_RANGE                       15:15
+#define GPIO_A_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_04_0_G7W_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G6W_SHIFT)
+#define GPIO_A_SCR_04_0_G6W_RANGE                       14:14
+#define GPIO_A_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_04_0_G6W_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G5W_SHIFT)
+#define GPIO_A_SCR_04_0_G5W_RANGE                       13:13
+#define GPIO_A_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_04_0_G5W_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G4W_SHIFT)
+#define GPIO_A_SCR_04_0_G4W_RANGE                       12:12
+#define GPIO_A_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_04_0_G4W_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G3W_SHIFT)
+#define GPIO_A_SCR_04_0_G3W_RANGE                       11:11
+#define GPIO_A_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_04_0_G3W_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G2W_SHIFT)
+#define GPIO_A_SCR_04_0_G2W_RANGE                       10:10
+#define GPIO_A_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_04_0_G2W_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G1W_SHIFT)
+#define GPIO_A_SCR_04_0_G1W_RANGE                       9:9
+#define GPIO_A_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_04_0_G1W_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G0W_SHIFT)
+#define GPIO_A_SCR_04_0_G0W_RANGE                       8:8
+#define GPIO_A_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_04_0_G0W_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G7R_SHIFT)
+#define GPIO_A_SCR_04_0_G7R_RANGE                       7:7
+#define GPIO_A_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_04_0_G7R_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G6R_SHIFT)
+#define GPIO_A_SCR_04_0_G6R_RANGE                       6:6
+#define GPIO_A_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_04_0_G6R_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G5R_SHIFT)
+#define GPIO_A_SCR_04_0_G5R_RANGE                       5:5
+#define GPIO_A_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_04_0_G5R_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G4R_SHIFT)
+#define GPIO_A_SCR_04_0_G4R_RANGE                       4:4
+#define GPIO_A_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_04_0_G4R_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G3R_SHIFT)
+#define GPIO_A_SCR_04_0_G3R_RANGE                       3:3
+#define GPIO_A_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_04_0_G3R_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G2R_SHIFT)
+#define GPIO_A_SCR_04_0_G2R_RANGE                       2:2
+#define GPIO_A_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_04_0_G2R_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G1R_SHIFT)
+#define GPIO_A_SCR_04_0_G1R_RANGE                       1:1
+#define GPIO_A_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_04_0_G1R_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_04_0_G0R_SHIFT)
+#define GPIO_A_SCR_04_0_G0R_RANGE                       0:0
+#define GPIO_A_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_04_0_G0R_WOFFSET                     0x0
+#define GPIO_A_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_VM_05_0
+#define GPIO_A_VM_05_0                  MK_ADDR_CONST(0x28)
+#define GPIO_A_VM_05_0_SECURE                   0x0
+#define GPIO_A_VM_05_0_DUAL                     0x0
+#define GPIO_A_VM_05_0_SCR                      GPIO_CTL0_VM_SCR_0
+#define GPIO_A_VM_05_0_SCRREG                   GPIO_CTL0_VM_SCR_0
+#define GPIO_A_VM_05_0_WORD_COUNT                       0x1
+#define GPIO_A_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_A_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM1_SHIFT)
+#define GPIO_A_VM_05_0_VM1_RANGE                        1:0
+#define GPIO_A_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_A_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_A_VM_05_0_VM1_WOFFSET                      0x0
+#define GPIO_A_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_A_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM2_SHIFT)
+#define GPIO_A_VM_05_0_VM2_RANGE                        3:2
+#define GPIO_A_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_A_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_A_VM_05_0_VM2_WOFFSET                      0x0
+#define GPIO_A_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_A_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM3_SHIFT)
+#define GPIO_A_VM_05_0_VM3_RANGE                        5:4
+#define GPIO_A_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_A_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_A_VM_05_0_VM3_WOFFSET                      0x0
+#define GPIO_A_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_A_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM4_SHIFT)
+#define GPIO_A_VM_05_0_VM4_RANGE                        7:6
+#define GPIO_A_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_A_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_A_VM_05_0_VM4_WOFFSET                      0x0
+#define GPIO_A_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_A_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM5_SHIFT)
+#define GPIO_A_VM_05_0_VM5_RANGE                        9:8
+#define GPIO_A_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_A_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_A_VM_05_0_VM5_WOFFSET                      0x0
+#define GPIO_A_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_A_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM6_SHIFT)
+#define GPIO_A_VM_05_0_VM6_RANGE                        11:10
+#define GPIO_A_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_A_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_A_VM_05_0_VM6_WOFFSET                      0x0
+#define GPIO_A_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_A_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM7_SHIFT)
+#define GPIO_A_VM_05_0_VM7_RANGE                        13:12
+#define GPIO_A_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_A_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_A_VM_05_0_VM7_WOFFSET                      0x0
+#define GPIO_A_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_A_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_05_0_VM8_SHIFT)
+#define GPIO_A_VM_05_0_VM8_RANGE                        15:14
+#define GPIO_A_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_A_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_A_VM_05_0_VM8_WOFFSET                      0x0
+#define GPIO_A_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_SCR_05_0
+#define GPIO_A_SCR_05_0                 MK_ADDR_CONST(0x2c)
+#define GPIO_A_SCR_05_0_SECURE                  0x0
+#define GPIO_A_SCR_05_0_DUAL                    0x0
+#define GPIO_A_SCR_05_0_SCR                     0
+#define GPIO_A_SCR_05_0_SCRREG                  0
+#define GPIO_A_SCR_05_0_WORD_COUNT                      0x1
+#define GPIO_A_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_A_SCR_05_0_SEC_LCK_RANGE                   29:29
+#define GPIO_A_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_05_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_A_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_A_SCR_05_0_SEC_WEN_RANGE                   28:28
+#define GPIO_A_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_05_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_A_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_A_SCR_05_0_SEC_REN_RANGE                   27:27
+#define GPIO_A_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_05_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_A_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_A_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_A_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_A_SCR_05_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_A_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_A_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_A_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_A_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_A_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR7_SHIFT)
+#define GPIO_A_SCR_05_0_PR7_RANGE                       23:23
+#define GPIO_A_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_05_0_PR7_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR6_SHIFT)
+#define GPIO_A_SCR_05_0_PR6_RANGE                       22:22
+#define GPIO_A_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_05_0_PR6_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR5_SHIFT)
+#define GPIO_A_SCR_05_0_PR5_RANGE                       21:21
+#define GPIO_A_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_05_0_PR5_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR4_SHIFT)
+#define GPIO_A_SCR_05_0_PR4_RANGE                       20:20
+#define GPIO_A_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_05_0_PR4_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR3_SHIFT)
+#define GPIO_A_SCR_05_0_PR3_RANGE                       19:19
+#define GPIO_A_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_05_0_PR3_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR2_SHIFT)
+#define GPIO_A_SCR_05_0_PR2_RANGE                       18:18
+#define GPIO_A_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_05_0_PR2_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR1_SHIFT)
+#define GPIO_A_SCR_05_0_PR1_RANGE                       17:17
+#define GPIO_A_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_05_0_PR1_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_PR0_SHIFT)
+#define GPIO_A_SCR_05_0_PR0_RANGE                       16:16
+#define GPIO_A_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_05_0_PR0_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G7W_SHIFT)
+#define GPIO_A_SCR_05_0_G7W_RANGE                       15:15
+#define GPIO_A_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_05_0_G7W_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G6W_SHIFT)
+#define GPIO_A_SCR_05_0_G6W_RANGE                       14:14
+#define GPIO_A_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_05_0_G6W_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G5W_SHIFT)
+#define GPIO_A_SCR_05_0_G5W_RANGE                       13:13
+#define GPIO_A_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_05_0_G5W_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G4W_SHIFT)
+#define GPIO_A_SCR_05_0_G4W_RANGE                       12:12
+#define GPIO_A_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_05_0_G4W_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G3W_SHIFT)
+#define GPIO_A_SCR_05_0_G3W_RANGE                       11:11
+#define GPIO_A_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_05_0_G3W_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G2W_SHIFT)
+#define GPIO_A_SCR_05_0_G2W_RANGE                       10:10
+#define GPIO_A_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_05_0_G2W_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G1W_SHIFT)
+#define GPIO_A_SCR_05_0_G1W_RANGE                       9:9
+#define GPIO_A_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_05_0_G1W_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G0W_SHIFT)
+#define GPIO_A_SCR_05_0_G0W_RANGE                       8:8
+#define GPIO_A_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_05_0_G0W_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G7R_SHIFT)
+#define GPIO_A_SCR_05_0_G7R_RANGE                       7:7
+#define GPIO_A_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_05_0_G7R_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G6R_SHIFT)
+#define GPIO_A_SCR_05_0_G6R_RANGE                       6:6
+#define GPIO_A_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_05_0_G6R_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G5R_SHIFT)
+#define GPIO_A_SCR_05_0_G5R_RANGE                       5:5
+#define GPIO_A_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_05_0_G5R_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G4R_SHIFT)
+#define GPIO_A_SCR_05_0_G4R_RANGE                       4:4
+#define GPIO_A_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_05_0_G4R_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G3R_SHIFT)
+#define GPIO_A_SCR_05_0_G3R_RANGE                       3:3
+#define GPIO_A_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_05_0_G3R_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G2R_SHIFT)
+#define GPIO_A_SCR_05_0_G2R_RANGE                       2:2
+#define GPIO_A_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_05_0_G2R_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G1R_SHIFT)
+#define GPIO_A_SCR_05_0_G1R_RANGE                       1:1
+#define GPIO_A_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_05_0_G1R_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_05_0_G0R_SHIFT)
+#define GPIO_A_SCR_05_0_G0R_RANGE                       0:0
+#define GPIO_A_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_05_0_G0R_WOFFSET                     0x0
+#define GPIO_A_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_VM_06_0
+#define GPIO_A_VM_06_0                  MK_ADDR_CONST(0x30)
+#define GPIO_A_VM_06_0_SECURE                   0x0
+#define GPIO_A_VM_06_0_DUAL                     0x0
+#define GPIO_A_VM_06_0_SCR                      GPIO_CTL0_VM_SCR_0
+#define GPIO_A_VM_06_0_SCRREG                   GPIO_CTL0_VM_SCR_0
+#define GPIO_A_VM_06_0_WORD_COUNT                       0x1
+#define GPIO_A_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_A_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM1_SHIFT)
+#define GPIO_A_VM_06_0_VM1_RANGE                        1:0
+#define GPIO_A_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_A_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_A_VM_06_0_VM1_WOFFSET                      0x0
+#define GPIO_A_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_A_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM2_SHIFT)
+#define GPIO_A_VM_06_0_VM2_RANGE                        3:2
+#define GPIO_A_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_A_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_A_VM_06_0_VM2_WOFFSET                      0x0
+#define GPIO_A_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_A_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM3_SHIFT)
+#define GPIO_A_VM_06_0_VM3_RANGE                        5:4
+#define GPIO_A_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_A_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_A_VM_06_0_VM3_WOFFSET                      0x0
+#define GPIO_A_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_A_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM4_SHIFT)
+#define GPIO_A_VM_06_0_VM4_RANGE                        7:6
+#define GPIO_A_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_A_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_A_VM_06_0_VM4_WOFFSET                      0x0
+#define GPIO_A_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_A_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM5_SHIFT)
+#define GPIO_A_VM_06_0_VM5_RANGE                        9:8
+#define GPIO_A_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_A_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_A_VM_06_0_VM5_WOFFSET                      0x0
+#define GPIO_A_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_A_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM6_SHIFT)
+#define GPIO_A_VM_06_0_VM6_RANGE                        11:10
+#define GPIO_A_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_A_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_A_VM_06_0_VM6_WOFFSET                      0x0
+#define GPIO_A_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_A_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM7_SHIFT)
+#define GPIO_A_VM_06_0_VM7_RANGE                        13:12
+#define GPIO_A_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_A_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_A_VM_06_0_VM7_WOFFSET                      0x0
+#define GPIO_A_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_A_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_06_0_VM8_SHIFT)
+#define GPIO_A_VM_06_0_VM8_RANGE                        15:14
+#define GPIO_A_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_A_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_A_VM_06_0_VM8_WOFFSET                      0x0
+#define GPIO_A_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_SCR_06_0
+#define GPIO_A_SCR_06_0                 MK_ADDR_CONST(0x34)
+#define GPIO_A_SCR_06_0_SECURE                  0x0
+#define GPIO_A_SCR_06_0_DUAL                    0x0
+#define GPIO_A_SCR_06_0_SCR                     0
+#define GPIO_A_SCR_06_0_SCRREG                  0
+#define GPIO_A_SCR_06_0_WORD_COUNT                      0x1
+#define GPIO_A_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_SEC_LCK_SHIFT)
+#define GPIO_A_SCR_06_0_SEC_LCK_RANGE                   29:29
+#define GPIO_A_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_06_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_A_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_SEC_WEN_SHIFT)
+#define GPIO_A_SCR_06_0_SEC_WEN_RANGE                   28:28
+#define GPIO_A_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_06_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_A_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_SEC_REN_SHIFT)
+#define GPIO_A_SCR_06_0_SEC_REN_RANGE                   27:27
+#define GPIO_A_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_06_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_A_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_A_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_A_SCR_06_0_SEC_OWNER_SHIFT)
+#define GPIO_A_SCR_06_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_A_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_A_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_A_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_A_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_A_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR7_SHIFT)
+#define GPIO_A_SCR_06_0_PR7_RANGE                       23:23
+#define GPIO_A_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_06_0_PR7_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR6_SHIFT)
+#define GPIO_A_SCR_06_0_PR6_RANGE                       22:22
+#define GPIO_A_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_06_0_PR6_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR5_SHIFT)
+#define GPIO_A_SCR_06_0_PR5_RANGE                       21:21
+#define GPIO_A_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_06_0_PR5_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR4_SHIFT)
+#define GPIO_A_SCR_06_0_PR4_RANGE                       20:20
+#define GPIO_A_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_06_0_PR4_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR3_SHIFT)
+#define GPIO_A_SCR_06_0_PR3_RANGE                       19:19
+#define GPIO_A_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_06_0_PR3_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR2_SHIFT)
+#define GPIO_A_SCR_06_0_PR2_RANGE                       18:18
+#define GPIO_A_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_06_0_PR2_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR1_SHIFT)
+#define GPIO_A_SCR_06_0_PR1_RANGE                       17:17
+#define GPIO_A_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_06_0_PR1_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_PR0_SHIFT)
+#define GPIO_A_SCR_06_0_PR0_RANGE                       16:16
+#define GPIO_A_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_06_0_PR0_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G7W_SHIFT)
+#define GPIO_A_SCR_06_0_G7W_RANGE                       15:15
+#define GPIO_A_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_06_0_G7W_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G6W_SHIFT)
+#define GPIO_A_SCR_06_0_G6W_RANGE                       14:14
+#define GPIO_A_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_06_0_G6W_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G5W_SHIFT)
+#define GPIO_A_SCR_06_0_G5W_RANGE                       13:13
+#define GPIO_A_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_06_0_G5W_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G4W_SHIFT)
+#define GPIO_A_SCR_06_0_G4W_RANGE                       12:12
+#define GPIO_A_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_06_0_G4W_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G3W_SHIFT)
+#define GPIO_A_SCR_06_0_G3W_RANGE                       11:11
+#define GPIO_A_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_06_0_G3W_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G2W_SHIFT)
+#define GPIO_A_SCR_06_0_G2W_RANGE                       10:10
+#define GPIO_A_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_06_0_G2W_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G1W_SHIFT)
+#define GPIO_A_SCR_06_0_G1W_RANGE                       9:9
+#define GPIO_A_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_06_0_G1W_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G0W_SHIFT)
+#define GPIO_A_SCR_06_0_G0W_RANGE                       8:8
+#define GPIO_A_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_06_0_G0W_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G7R_SHIFT)
+#define GPIO_A_SCR_06_0_G7R_RANGE                       7:7
+#define GPIO_A_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_06_0_G7R_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G6R_SHIFT)
+#define GPIO_A_SCR_06_0_G6R_RANGE                       6:6
+#define GPIO_A_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_06_0_G6R_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G5R_SHIFT)
+#define GPIO_A_SCR_06_0_G5R_RANGE                       5:5
+#define GPIO_A_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_06_0_G5R_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G4R_SHIFT)
+#define GPIO_A_SCR_06_0_G4R_RANGE                       4:4
+#define GPIO_A_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_06_0_G4R_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G3R_SHIFT)
+#define GPIO_A_SCR_06_0_G3R_RANGE                       3:3
+#define GPIO_A_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_06_0_G3R_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G2R_SHIFT)
+#define GPIO_A_SCR_06_0_G2R_RANGE                       2:2
+#define GPIO_A_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_06_0_G2R_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G1R_SHIFT)
+#define GPIO_A_SCR_06_0_G1R_RANGE                       1:1
+#define GPIO_A_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_06_0_G1R_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_06_0_G0R_SHIFT)
+#define GPIO_A_SCR_06_0_G0R_RANGE                       0:0
+#define GPIO_A_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_06_0_G0R_WOFFSET                     0x0
+#define GPIO_A_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_VM_07_0
+#define GPIO_A_VM_07_0                  MK_ADDR_CONST(0x38)
+#define GPIO_A_VM_07_0_SECURE                   0x0
+#define GPIO_A_VM_07_0_DUAL                     0x0
+#define GPIO_A_VM_07_0_SCR                      GPIO_CTL0_VM_SCR_0
+#define GPIO_A_VM_07_0_SCRREG                   GPIO_CTL0_VM_SCR_0
+#define GPIO_A_VM_07_0_WORD_COUNT                       0x1
+#define GPIO_A_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_A_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_A_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM1_SHIFT)
+#define GPIO_A_VM_07_0_VM1_RANGE                        1:0
+#define GPIO_A_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_A_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_A_VM_07_0_VM1_WOFFSET                      0x0
+#define GPIO_A_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_A_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM2_SHIFT)
+#define GPIO_A_VM_07_0_VM2_RANGE                        3:2
+#define GPIO_A_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_A_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_A_VM_07_0_VM2_WOFFSET                      0x0
+#define GPIO_A_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_A_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM3_SHIFT)
+#define GPIO_A_VM_07_0_VM3_RANGE                        5:4
+#define GPIO_A_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_A_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_A_VM_07_0_VM3_WOFFSET                      0x0
+#define GPIO_A_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_A_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM4_SHIFT)
+#define GPIO_A_VM_07_0_VM4_RANGE                        7:6
+#define GPIO_A_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_A_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_A_VM_07_0_VM4_WOFFSET                      0x0
+#define GPIO_A_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_A_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM5_SHIFT)
+#define GPIO_A_VM_07_0_VM5_RANGE                        9:8
+#define GPIO_A_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_A_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_A_VM_07_0_VM5_WOFFSET                      0x0
+#define GPIO_A_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_A_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM6_SHIFT)
+#define GPIO_A_VM_07_0_VM6_RANGE                        11:10
+#define GPIO_A_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_A_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_A_VM_07_0_VM6_WOFFSET                      0x0
+#define GPIO_A_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_A_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM7_SHIFT)
+#define GPIO_A_VM_07_0_VM7_RANGE                        13:12
+#define GPIO_A_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_A_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_A_VM_07_0_VM7_WOFFSET                      0x0
+#define GPIO_A_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_A_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_A_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_A_VM_07_0_VM8_SHIFT)
+#define GPIO_A_VM_07_0_VM8_RANGE                        15:14
+#define GPIO_A_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_A_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_A_VM_07_0_VM8_WOFFSET                      0x0
+#define GPIO_A_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_A_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_A_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_SCR_07_0
+#define GPIO_A_SCR_07_0                 MK_ADDR_CONST(0x3c)
+#define GPIO_A_SCR_07_0_SECURE                  0x0
+#define GPIO_A_SCR_07_0_DUAL                    0x0
+#define GPIO_A_SCR_07_0_SCR                     0
+#define GPIO_A_SCR_07_0_SCRREG                  0
+#define GPIO_A_SCR_07_0_WORD_COUNT                      0x1
+#define GPIO_A_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_A_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_SEC_LCK_SHIFT)
+#define GPIO_A_SCR_07_0_SEC_LCK_RANGE                   29:29
+#define GPIO_A_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_A_SCR_07_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_A_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_SEC_WEN_SHIFT)
+#define GPIO_A_SCR_07_0_SEC_WEN_RANGE                   28:28
+#define GPIO_A_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_A_SCR_07_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_A_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_SEC_REN_SHIFT)
+#define GPIO_A_SCR_07_0_SEC_REN_RANGE                   27:27
+#define GPIO_A_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_A_SCR_07_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_A_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_A_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_A_SCR_07_0_SEC_OWNER_SHIFT)
+#define GPIO_A_SCR_07_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_A_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_A_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_A_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_A_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_A_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR7_SHIFT)
+#define GPIO_A_SCR_07_0_PR7_RANGE                       23:23
+#define GPIO_A_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_A_SCR_07_0_PR7_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR6_SHIFT)
+#define GPIO_A_SCR_07_0_PR6_RANGE                       22:22
+#define GPIO_A_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_A_SCR_07_0_PR6_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR5_SHIFT)
+#define GPIO_A_SCR_07_0_PR5_RANGE                       21:21
+#define GPIO_A_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_A_SCR_07_0_PR5_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR4_SHIFT)
+#define GPIO_A_SCR_07_0_PR4_RANGE                       20:20
+#define GPIO_A_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_A_SCR_07_0_PR4_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR3_SHIFT)
+#define GPIO_A_SCR_07_0_PR3_RANGE                       19:19
+#define GPIO_A_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_A_SCR_07_0_PR3_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR2_SHIFT)
+#define GPIO_A_SCR_07_0_PR2_RANGE                       18:18
+#define GPIO_A_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_A_SCR_07_0_PR2_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR1_SHIFT)
+#define GPIO_A_SCR_07_0_PR1_RANGE                       17:17
+#define GPIO_A_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_A_SCR_07_0_PR1_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_PR0_SHIFT)
+#define GPIO_A_SCR_07_0_PR0_RANGE                       16:16
+#define GPIO_A_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_A_SCR_07_0_PR0_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G7W_SHIFT)
+#define GPIO_A_SCR_07_0_G7W_RANGE                       15:15
+#define GPIO_A_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_A_SCR_07_0_G7W_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G6W_SHIFT)
+#define GPIO_A_SCR_07_0_G6W_RANGE                       14:14
+#define GPIO_A_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_A_SCR_07_0_G6W_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G5W_SHIFT)
+#define GPIO_A_SCR_07_0_G5W_RANGE                       13:13
+#define GPIO_A_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_A_SCR_07_0_G5W_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G4W_SHIFT)
+#define GPIO_A_SCR_07_0_G4W_RANGE                       12:12
+#define GPIO_A_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_A_SCR_07_0_G4W_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G3W_SHIFT)
+#define GPIO_A_SCR_07_0_G3W_RANGE                       11:11
+#define GPIO_A_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_A_SCR_07_0_G3W_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G2W_SHIFT)
+#define GPIO_A_SCR_07_0_G2W_RANGE                       10:10
+#define GPIO_A_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_A_SCR_07_0_G2W_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G1W_SHIFT)
+#define GPIO_A_SCR_07_0_G1W_RANGE                       9:9
+#define GPIO_A_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_A_SCR_07_0_G1W_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G0W_SHIFT)
+#define GPIO_A_SCR_07_0_G0W_RANGE                       8:8
+#define GPIO_A_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_A_SCR_07_0_G0W_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G7R_SHIFT)
+#define GPIO_A_SCR_07_0_G7R_RANGE                       7:7
+#define GPIO_A_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_A_SCR_07_0_G7R_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G6R_SHIFT)
+#define GPIO_A_SCR_07_0_G6R_RANGE                       6:6
+#define GPIO_A_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_A_SCR_07_0_G6R_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G5R_SHIFT)
+#define GPIO_A_SCR_07_0_G5R_RANGE                       5:5
+#define GPIO_A_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_SCR_07_0_G5R_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G4R_SHIFT)
+#define GPIO_A_SCR_07_0_G4R_RANGE                       4:4
+#define GPIO_A_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_A_SCR_07_0_G4R_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G3R_SHIFT)
+#define GPIO_A_SCR_07_0_G3R_RANGE                       3:3
+#define GPIO_A_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_A_SCR_07_0_G3R_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G2R_SHIFT)
+#define GPIO_A_SCR_07_0_G2R_RANGE                       2:2
+#define GPIO_A_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_A_SCR_07_0_G2R_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G1R_SHIFT)
+#define GPIO_A_SCR_07_0_G1R_RANGE                       1:1
+#define GPIO_A_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_A_SCR_07_0_G1R_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_A_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_SCR_07_0_G0R_SHIFT)
+#define GPIO_A_SCR_07_0_G0R_RANGE                       0:0
+#define GPIO_A_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_SCR_07_0_G0R_WOFFSET                     0x0
+#define GPIO_A_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_A_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_VM_00_0
+#define GPIO_AC_VM_00_0                 MK_ADDR_CONST(0x40)
+#define GPIO_AC_VM_00_0_SECURE                  0x0
+#define GPIO_AC_VM_00_0_DUAL                    0x0
+#define GPIO_AC_VM_00_0_SCR                     GPIO_CTL0_VM_SCR_0
+#define GPIO_AC_VM_00_0_SCRREG                  GPIO_CTL0_VM_SCR_0
+#define GPIO_AC_VM_00_0_WORD_COUNT                      0x1
+#define GPIO_AC_VM_00_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_00_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_00_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_00_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AC_VM_00_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_00_0_VM1_SHIFT)
+#define GPIO_AC_VM_00_0_VM1_RANGE                       1:0
+#define GPIO_AC_VM_00_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AC_VM_00_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AC_VM_00_0_VM1_WOFFSET                     0x0
+#define GPIO_AC_VM_00_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_00_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_00_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_00_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AC_VM_00_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_00_0_VM2_SHIFT)
+#define GPIO_AC_VM_00_0_VM2_RANGE                       3:2
+#define GPIO_AC_VM_00_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AC_VM_00_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AC_VM_00_0_VM2_WOFFSET                     0x0
+#define GPIO_AC_VM_00_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_00_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_00_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_00_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AC_VM_00_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_00_0_VM3_SHIFT)
+#define GPIO_AC_VM_00_0_VM3_RANGE                       5:4
+#define GPIO_AC_VM_00_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AC_VM_00_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AC_VM_00_0_VM3_WOFFSET                     0x0
+#define GPIO_AC_VM_00_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_00_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_00_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_00_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AC_VM_00_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_00_0_VM4_SHIFT)
+#define GPIO_AC_VM_00_0_VM4_RANGE                       7:6
+#define GPIO_AC_VM_00_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AC_VM_00_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AC_VM_00_0_VM4_WOFFSET                     0x0
+#define GPIO_AC_VM_00_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_00_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_00_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_00_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AC_VM_00_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_00_0_VM5_SHIFT)
+#define GPIO_AC_VM_00_0_VM5_RANGE                       9:8
+#define GPIO_AC_VM_00_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AC_VM_00_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AC_VM_00_0_VM5_WOFFSET                     0x0
+#define GPIO_AC_VM_00_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_00_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_00_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_00_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AC_VM_00_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_00_0_VM6_SHIFT)
+#define GPIO_AC_VM_00_0_VM6_RANGE                       11:10
+#define GPIO_AC_VM_00_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AC_VM_00_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AC_VM_00_0_VM6_WOFFSET                     0x0
+#define GPIO_AC_VM_00_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_00_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_00_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_00_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AC_VM_00_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_00_0_VM7_SHIFT)
+#define GPIO_AC_VM_00_0_VM7_RANGE                       13:12
+#define GPIO_AC_VM_00_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AC_VM_00_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AC_VM_00_0_VM7_WOFFSET                     0x0
+#define GPIO_AC_VM_00_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_00_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_00_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_00_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AC_VM_00_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_00_0_VM8_SHIFT)
+#define GPIO_AC_VM_00_0_VM8_RANGE                       15:14
+#define GPIO_AC_VM_00_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AC_VM_00_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AC_VM_00_0_VM8_WOFFSET                     0x0
+#define GPIO_AC_VM_00_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_00_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_00_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_00_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_SCR_00_0
+#define GPIO_AC_SCR_00_0                        MK_ADDR_CONST(0x44)
+#define GPIO_AC_SCR_00_0_SECURE                         0x0
+#define GPIO_AC_SCR_00_0_DUAL                   0x0
+#define GPIO_AC_SCR_00_0_SCR                    0
+#define GPIO_AC_SCR_00_0_SCRREG                         0
+#define GPIO_AC_SCR_00_0_WORD_COUNT                     0x1
+#define GPIO_AC_SCR_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_00_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_00_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_00_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_AC_SCR_00_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AC_SCR_00_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_00_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_00_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AC_SCR_00_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_00_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_AC_SCR_00_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AC_SCR_00_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_00_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_00_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AC_SCR_00_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_00_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_AC_SCR_00_0_SEC_REN_RANGE                  27:27
+#define GPIO_AC_SCR_00_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_00_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_00_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AC_SCR_00_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AC_SCR_00_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AC_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_AC_SCR_00_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AC_SCR_00_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AC_SCR_00_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AC_SCR_00_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AC_SCR_00_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AC_SCR_00_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_00_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_PR7_SHIFT)
+#define GPIO_AC_SCR_00_0_PR7_RANGE                      23:23
+#define GPIO_AC_SCR_00_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_00_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_00_0_PR7_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_00_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_PR6_SHIFT)
+#define GPIO_AC_SCR_00_0_PR6_RANGE                      22:22
+#define GPIO_AC_SCR_00_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_00_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_00_0_PR6_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_00_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_PR5_SHIFT)
+#define GPIO_AC_SCR_00_0_PR5_RANGE                      21:21
+#define GPIO_AC_SCR_00_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_00_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_00_0_PR5_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_00_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_PR4_SHIFT)
+#define GPIO_AC_SCR_00_0_PR4_RANGE                      20:20
+#define GPIO_AC_SCR_00_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_00_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_00_0_PR4_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_00_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_PR3_SHIFT)
+#define GPIO_AC_SCR_00_0_PR3_RANGE                      19:19
+#define GPIO_AC_SCR_00_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_00_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_00_0_PR3_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_00_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_PR2_SHIFT)
+#define GPIO_AC_SCR_00_0_PR2_RANGE                      18:18
+#define GPIO_AC_SCR_00_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_00_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_00_0_PR2_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_00_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_PR1_SHIFT)
+#define GPIO_AC_SCR_00_0_PR1_RANGE                      17:17
+#define GPIO_AC_SCR_00_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_00_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_00_0_PR1_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_00_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_PR0_SHIFT)
+#define GPIO_AC_SCR_00_0_PR0_RANGE                      16:16
+#define GPIO_AC_SCR_00_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_00_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_00_0_PR0_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_00_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G7W_SHIFT)
+#define GPIO_AC_SCR_00_0_G7W_RANGE                      15:15
+#define GPIO_AC_SCR_00_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_00_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_00_0_G7W_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_00_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G6W_SHIFT)
+#define GPIO_AC_SCR_00_0_G6W_RANGE                      14:14
+#define GPIO_AC_SCR_00_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_00_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_00_0_G6W_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_00_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G5W_SHIFT)
+#define GPIO_AC_SCR_00_0_G5W_RANGE                      13:13
+#define GPIO_AC_SCR_00_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_00_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_00_0_G5W_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_00_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G4W_SHIFT)
+#define GPIO_AC_SCR_00_0_G4W_RANGE                      12:12
+#define GPIO_AC_SCR_00_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_00_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_00_0_G4W_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_00_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G3W_SHIFT)
+#define GPIO_AC_SCR_00_0_G3W_RANGE                      11:11
+#define GPIO_AC_SCR_00_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_00_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_00_0_G3W_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_00_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G2W_SHIFT)
+#define GPIO_AC_SCR_00_0_G2W_RANGE                      10:10
+#define GPIO_AC_SCR_00_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_00_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_00_0_G2W_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_00_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G1W_SHIFT)
+#define GPIO_AC_SCR_00_0_G1W_RANGE                      9:9
+#define GPIO_AC_SCR_00_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_00_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_00_0_G1W_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_00_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G0W_SHIFT)
+#define GPIO_AC_SCR_00_0_G0W_RANGE                      8:8
+#define GPIO_AC_SCR_00_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_00_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_00_0_G0W_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_00_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G7R_SHIFT)
+#define GPIO_AC_SCR_00_0_G7R_RANGE                      7:7
+#define GPIO_AC_SCR_00_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_00_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_00_0_G7R_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_00_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G6R_SHIFT)
+#define GPIO_AC_SCR_00_0_G6R_RANGE                      6:6
+#define GPIO_AC_SCR_00_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_00_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_00_0_G6R_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_00_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G5R_SHIFT)
+#define GPIO_AC_SCR_00_0_G5R_RANGE                      5:5
+#define GPIO_AC_SCR_00_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_00_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_00_0_G5R_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_00_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G4R_SHIFT)
+#define GPIO_AC_SCR_00_0_G4R_RANGE                      4:4
+#define GPIO_AC_SCR_00_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_00_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_00_0_G4R_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_00_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G3R_SHIFT)
+#define GPIO_AC_SCR_00_0_G3R_RANGE                      3:3
+#define GPIO_AC_SCR_00_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_00_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_00_0_G3R_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_00_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G2R_SHIFT)
+#define GPIO_AC_SCR_00_0_G2R_RANGE                      2:2
+#define GPIO_AC_SCR_00_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_00_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_00_0_G2R_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_00_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G1R_SHIFT)
+#define GPIO_AC_SCR_00_0_G1R_RANGE                      1:1
+#define GPIO_AC_SCR_00_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_00_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_00_0_G1R_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_00_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_00_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_00_0_G0R_SHIFT)
+#define GPIO_AC_SCR_00_0_G0R_RANGE                      0:0
+#define GPIO_AC_SCR_00_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_00_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_00_0_G0R_WOFFSET                    0x0
+#define GPIO_AC_SCR_00_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_00_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_00_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_VM_01_0
+#define GPIO_AC_VM_01_0                 MK_ADDR_CONST(0x48)
+#define GPIO_AC_VM_01_0_SECURE                  0x0
+#define GPIO_AC_VM_01_0_DUAL                    0x0
+#define GPIO_AC_VM_01_0_SCR                     GPIO_CTL0_VM_SCR_0
+#define GPIO_AC_VM_01_0_SCRREG                  GPIO_CTL0_VM_SCR_0
+#define GPIO_AC_VM_01_0_WORD_COUNT                      0x1
+#define GPIO_AC_VM_01_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_01_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_01_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_01_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AC_VM_01_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_01_0_VM1_SHIFT)
+#define GPIO_AC_VM_01_0_VM1_RANGE                       1:0
+#define GPIO_AC_VM_01_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AC_VM_01_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AC_VM_01_0_VM1_WOFFSET                     0x0
+#define GPIO_AC_VM_01_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_01_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_01_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_01_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AC_VM_01_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_01_0_VM2_SHIFT)
+#define GPIO_AC_VM_01_0_VM2_RANGE                       3:2
+#define GPIO_AC_VM_01_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AC_VM_01_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AC_VM_01_0_VM2_WOFFSET                     0x0
+#define GPIO_AC_VM_01_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_01_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_01_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_01_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AC_VM_01_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_01_0_VM3_SHIFT)
+#define GPIO_AC_VM_01_0_VM3_RANGE                       5:4
+#define GPIO_AC_VM_01_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AC_VM_01_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AC_VM_01_0_VM3_WOFFSET                     0x0
+#define GPIO_AC_VM_01_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_01_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_01_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_01_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AC_VM_01_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_01_0_VM4_SHIFT)
+#define GPIO_AC_VM_01_0_VM4_RANGE                       7:6
+#define GPIO_AC_VM_01_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AC_VM_01_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AC_VM_01_0_VM4_WOFFSET                     0x0
+#define GPIO_AC_VM_01_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_01_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_01_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_01_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AC_VM_01_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_01_0_VM5_SHIFT)
+#define GPIO_AC_VM_01_0_VM5_RANGE                       9:8
+#define GPIO_AC_VM_01_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AC_VM_01_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AC_VM_01_0_VM5_WOFFSET                     0x0
+#define GPIO_AC_VM_01_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_01_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_01_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_01_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AC_VM_01_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_01_0_VM6_SHIFT)
+#define GPIO_AC_VM_01_0_VM6_RANGE                       11:10
+#define GPIO_AC_VM_01_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AC_VM_01_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AC_VM_01_0_VM6_WOFFSET                     0x0
+#define GPIO_AC_VM_01_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_01_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_01_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_01_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AC_VM_01_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_01_0_VM7_SHIFT)
+#define GPIO_AC_VM_01_0_VM7_RANGE                       13:12
+#define GPIO_AC_VM_01_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AC_VM_01_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AC_VM_01_0_VM7_WOFFSET                     0x0
+#define GPIO_AC_VM_01_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_01_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_01_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_01_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AC_VM_01_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_01_0_VM8_SHIFT)
+#define GPIO_AC_VM_01_0_VM8_RANGE                       15:14
+#define GPIO_AC_VM_01_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AC_VM_01_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AC_VM_01_0_VM8_WOFFSET                     0x0
+#define GPIO_AC_VM_01_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_01_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_01_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_01_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_SCR_01_0
+#define GPIO_AC_SCR_01_0                        MK_ADDR_CONST(0x4c)
+#define GPIO_AC_SCR_01_0_SECURE                         0x0
+#define GPIO_AC_SCR_01_0_DUAL                   0x0
+#define GPIO_AC_SCR_01_0_SCR                    0
+#define GPIO_AC_SCR_01_0_SCRREG                         0
+#define GPIO_AC_SCR_01_0_WORD_COUNT                     0x1
+#define GPIO_AC_SCR_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_01_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_01_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_01_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_AC_SCR_01_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AC_SCR_01_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_01_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_01_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AC_SCR_01_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_01_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_AC_SCR_01_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AC_SCR_01_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_01_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_01_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AC_SCR_01_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_01_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_AC_SCR_01_0_SEC_REN_RANGE                  27:27
+#define GPIO_AC_SCR_01_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_01_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_01_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AC_SCR_01_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AC_SCR_01_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AC_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_AC_SCR_01_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AC_SCR_01_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AC_SCR_01_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AC_SCR_01_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AC_SCR_01_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AC_SCR_01_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_01_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_PR7_SHIFT)
+#define GPIO_AC_SCR_01_0_PR7_RANGE                      23:23
+#define GPIO_AC_SCR_01_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_01_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_01_0_PR7_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_01_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_PR6_SHIFT)
+#define GPIO_AC_SCR_01_0_PR6_RANGE                      22:22
+#define GPIO_AC_SCR_01_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_01_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_01_0_PR6_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_01_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_PR5_SHIFT)
+#define GPIO_AC_SCR_01_0_PR5_RANGE                      21:21
+#define GPIO_AC_SCR_01_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_01_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_01_0_PR5_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_01_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_PR4_SHIFT)
+#define GPIO_AC_SCR_01_0_PR4_RANGE                      20:20
+#define GPIO_AC_SCR_01_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_01_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_01_0_PR4_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_01_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_PR3_SHIFT)
+#define GPIO_AC_SCR_01_0_PR3_RANGE                      19:19
+#define GPIO_AC_SCR_01_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_01_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_01_0_PR3_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_01_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_PR2_SHIFT)
+#define GPIO_AC_SCR_01_0_PR2_RANGE                      18:18
+#define GPIO_AC_SCR_01_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_01_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_01_0_PR2_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_01_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_PR1_SHIFT)
+#define GPIO_AC_SCR_01_0_PR1_RANGE                      17:17
+#define GPIO_AC_SCR_01_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_01_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_01_0_PR1_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_01_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_PR0_SHIFT)
+#define GPIO_AC_SCR_01_0_PR0_RANGE                      16:16
+#define GPIO_AC_SCR_01_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_01_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_01_0_PR0_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_01_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G7W_SHIFT)
+#define GPIO_AC_SCR_01_0_G7W_RANGE                      15:15
+#define GPIO_AC_SCR_01_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_01_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_01_0_G7W_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_01_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G6W_SHIFT)
+#define GPIO_AC_SCR_01_0_G6W_RANGE                      14:14
+#define GPIO_AC_SCR_01_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_01_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_01_0_G6W_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_01_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G5W_SHIFT)
+#define GPIO_AC_SCR_01_0_G5W_RANGE                      13:13
+#define GPIO_AC_SCR_01_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_01_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_01_0_G5W_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_01_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G4W_SHIFT)
+#define GPIO_AC_SCR_01_0_G4W_RANGE                      12:12
+#define GPIO_AC_SCR_01_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_01_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_01_0_G4W_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_01_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G3W_SHIFT)
+#define GPIO_AC_SCR_01_0_G3W_RANGE                      11:11
+#define GPIO_AC_SCR_01_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_01_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_01_0_G3W_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_01_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G2W_SHIFT)
+#define GPIO_AC_SCR_01_0_G2W_RANGE                      10:10
+#define GPIO_AC_SCR_01_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_01_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_01_0_G2W_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_01_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G1W_SHIFT)
+#define GPIO_AC_SCR_01_0_G1W_RANGE                      9:9
+#define GPIO_AC_SCR_01_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_01_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_01_0_G1W_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_01_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G0W_SHIFT)
+#define GPIO_AC_SCR_01_0_G0W_RANGE                      8:8
+#define GPIO_AC_SCR_01_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_01_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_01_0_G0W_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_01_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G7R_SHIFT)
+#define GPIO_AC_SCR_01_0_G7R_RANGE                      7:7
+#define GPIO_AC_SCR_01_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_01_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_01_0_G7R_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_01_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G6R_SHIFT)
+#define GPIO_AC_SCR_01_0_G6R_RANGE                      6:6
+#define GPIO_AC_SCR_01_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_01_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_01_0_G6R_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_01_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G5R_SHIFT)
+#define GPIO_AC_SCR_01_0_G5R_RANGE                      5:5
+#define GPIO_AC_SCR_01_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_01_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_01_0_G5R_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_01_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G4R_SHIFT)
+#define GPIO_AC_SCR_01_0_G4R_RANGE                      4:4
+#define GPIO_AC_SCR_01_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_01_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_01_0_G4R_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_01_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G3R_SHIFT)
+#define GPIO_AC_SCR_01_0_G3R_RANGE                      3:3
+#define GPIO_AC_SCR_01_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_01_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_01_0_G3R_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_01_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G2R_SHIFT)
+#define GPIO_AC_SCR_01_0_G2R_RANGE                      2:2
+#define GPIO_AC_SCR_01_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_01_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_01_0_G2R_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_01_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G1R_SHIFT)
+#define GPIO_AC_SCR_01_0_G1R_RANGE                      1:1
+#define GPIO_AC_SCR_01_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_01_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_01_0_G1R_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_01_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_01_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_01_0_G0R_SHIFT)
+#define GPIO_AC_SCR_01_0_G0R_RANGE                      0:0
+#define GPIO_AC_SCR_01_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_01_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_01_0_G0R_WOFFSET                    0x0
+#define GPIO_AC_SCR_01_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_01_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_01_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_VM_02_0
+#define GPIO_AC_VM_02_0                 MK_ADDR_CONST(0x50)
+#define GPIO_AC_VM_02_0_SECURE                  0x0
+#define GPIO_AC_VM_02_0_DUAL                    0x0
+#define GPIO_AC_VM_02_0_SCR                     GPIO_CTL0_VM_SCR_0
+#define GPIO_AC_VM_02_0_SCRREG                  GPIO_CTL0_VM_SCR_0
+#define GPIO_AC_VM_02_0_WORD_COUNT                      0x1
+#define GPIO_AC_VM_02_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_02_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_02_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_02_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AC_VM_02_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_02_0_VM1_SHIFT)
+#define GPIO_AC_VM_02_0_VM1_RANGE                       1:0
+#define GPIO_AC_VM_02_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AC_VM_02_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AC_VM_02_0_VM1_WOFFSET                     0x0
+#define GPIO_AC_VM_02_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_02_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_02_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_02_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AC_VM_02_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_02_0_VM2_SHIFT)
+#define GPIO_AC_VM_02_0_VM2_RANGE                       3:2
+#define GPIO_AC_VM_02_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AC_VM_02_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AC_VM_02_0_VM2_WOFFSET                     0x0
+#define GPIO_AC_VM_02_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_02_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_02_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_02_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AC_VM_02_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_02_0_VM3_SHIFT)
+#define GPIO_AC_VM_02_0_VM3_RANGE                       5:4
+#define GPIO_AC_VM_02_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AC_VM_02_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AC_VM_02_0_VM3_WOFFSET                     0x0
+#define GPIO_AC_VM_02_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_02_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_02_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_02_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AC_VM_02_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_02_0_VM4_SHIFT)
+#define GPIO_AC_VM_02_0_VM4_RANGE                       7:6
+#define GPIO_AC_VM_02_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AC_VM_02_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AC_VM_02_0_VM4_WOFFSET                     0x0
+#define GPIO_AC_VM_02_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_02_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_02_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_02_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AC_VM_02_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_02_0_VM5_SHIFT)
+#define GPIO_AC_VM_02_0_VM5_RANGE                       9:8
+#define GPIO_AC_VM_02_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AC_VM_02_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AC_VM_02_0_VM5_WOFFSET                     0x0
+#define GPIO_AC_VM_02_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_02_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_02_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_02_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AC_VM_02_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_02_0_VM6_SHIFT)
+#define GPIO_AC_VM_02_0_VM6_RANGE                       11:10
+#define GPIO_AC_VM_02_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AC_VM_02_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AC_VM_02_0_VM6_WOFFSET                     0x0
+#define GPIO_AC_VM_02_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_02_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_02_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_02_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AC_VM_02_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_02_0_VM7_SHIFT)
+#define GPIO_AC_VM_02_0_VM7_RANGE                       13:12
+#define GPIO_AC_VM_02_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AC_VM_02_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AC_VM_02_0_VM7_WOFFSET                     0x0
+#define GPIO_AC_VM_02_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_02_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_02_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_02_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AC_VM_02_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_02_0_VM8_SHIFT)
+#define GPIO_AC_VM_02_0_VM8_RANGE                       15:14
+#define GPIO_AC_VM_02_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AC_VM_02_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AC_VM_02_0_VM8_WOFFSET                     0x0
+#define GPIO_AC_VM_02_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_02_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_02_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_02_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_SCR_02_0
+#define GPIO_AC_SCR_02_0                        MK_ADDR_CONST(0x54)
+#define GPIO_AC_SCR_02_0_SECURE                         0x0
+#define GPIO_AC_SCR_02_0_DUAL                   0x0
+#define GPIO_AC_SCR_02_0_SCR                    0
+#define GPIO_AC_SCR_02_0_SCRREG                         0
+#define GPIO_AC_SCR_02_0_WORD_COUNT                     0x1
+#define GPIO_AC_SCR_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_02_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_02_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_02_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_AC_SCR_02_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AC_SCR_02_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_02_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_02_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AC_SCR_02_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_02_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_AC_SCR_02_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AC_SCR_02_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_02_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_02_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AC_SCR_02_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_02_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_AC_SCR_02_0_SEC_REN_RANGE                  27:27
+#define GPIO_AC_SCR_02_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_02_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_02_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AC_SCR_02_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AC_SCR_02_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AC_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_AC_SCR_02_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AC_SCR_02_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AC_SCR_02_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AC_SCR_02_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AC_SCR_02_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AC_SCR_02_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_02_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_PR7_SHIFT)
+#define GPIO_AC_SCR_02_0_PR7_RANGE                      23:23
+#define GPIO_AC_SCR_02_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_02_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_02_0_PR7_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_02_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_PR6_SHIFT)
+#define GPIO_AC_SCR_02_0_PR6_RANGE                      22:22
+#define GPIO_AC_SCR_02_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_02_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_02_0_PR6_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_02_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_PR5_SHIFT)
+#define GPIO_AC_SCR_02_0_PR5_RANGE                      21:21
+#define GPIO_AC_SCR_02_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_02_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_02_0_PR5_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_02_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_PR4_SHIFT)
+#define GPIO_AC_SCR_02_0_PR4_RANGE                      20:20
+#define GPIO_AC_SCR_02_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_02_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_02_0_PR4_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_02_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_PR3_SHIFT)
+#define GPIO_AC_SCR_02_0_PR3_RANGE                      19:19
+#define GPIO_AC_SCR_02_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_02_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_02_0_PR3_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_02_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_PR2_SHIFT)
+#define GPIO_AC_SCR_02_0_PR2_RANGE                      18:18
+#define GPIO_AC_SCR_02_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_02_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_02_0_PR2_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_02_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_PR1_SHIFT)
+#define GPIO_AC_SCR_02_0_PR1_RANGE                      17:17
+#define GPIO_AC_SCR_02_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_02_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_02_0_PR1_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_02_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_PR0_SHIFT)
+#define GPIO_AC_SCR_02_0_PR0_RANGE                      16:16
+#define GPIO_AC_SCR_02_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_02_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_02_0_PR0_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_02_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G7W_SHIFT)
+#define GPIO_AC_SCR_02_0_G7W_RANGE                      15:15
+#define GPIO_AC_SCR_02_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_02_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_02_0_G7W_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_02_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G6W_SHIFT)
+#define GPIO_AC_SCR_02_0_G6W_RANGE                      14:14
+#define GPIO_AC_SCR_02_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_02_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_02_0_G6W_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_02_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G5W_SHIFT)
+#define GPIO_AC_SCR_02_0_G5W_RANGE                      13:13
+#define GPIO_AC_SCR_02_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_02_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_02_0_G5W_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_02_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G4W_SHIFT)
+#define GPIO_AC_SCR_02_0_G4W_RANGE                      12:12
+#define GPIO_AC_SCR_02_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_02_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_02_0_G4W_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_02_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G3W_SHIFT)
+#define GPIO_AC_SCR_02_0_G3W_RANGE                      11:11
+#define GPIO_AC_SCR_02_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_02_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_02_0_G3W_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_02_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G2W_SHIFT)
+#define GPIO_AC_SCR_02_0_G2W_RANGE                      10:10
+#define GPIO_AC_SCR_02_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_02_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_02_0_G2W_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_02_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G1W_SHIFT)
+#define GPIO_AC_SCR_02_0_G1W_RANGE                      9:9
+#define GPIO_AC_SCR_02_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_02_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_02_0_G1W_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_02_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G0W_SHIFT)
+#define GPIO_AC_SCR_02_0_G0W_RANGE                      8:8
+#define GPIO_AC_SCR_02_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_02_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_02_0_G0W_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_02_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G7R_SHIFT)
+#define GPIO_AC_SCR_02_0_G7R_RANGE                      7:7
+#define GPIO_AC_SCR_02_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_02_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_02_0_G7R_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_02_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G6R_SHIFT)
+#define GPIO_AC_SCR_02_0_G6R_RANGE                      6:6
+#define GPIO_AC_SCR_02_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_02_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_02_0_G6R_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_02_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G5R_SHIFT)
+#define GPIO_AC_SCR_02_0_G5R_RANGE                      5:5
+#define GPIO_AC_SCR_02_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_02_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_02_0_G5R_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_02_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G4R_SHIFT)
+#define GPIO_AC_SCR_02_0_G4R_RANGE                      4:4
+#define GPIO_AC_SCR_02_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_02_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_02_0_G4R_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_02_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G3R_SHIFT)
+#define GPIO_AC_SCR_02_0_G3R_RANGE                      3:3
+#define GPIO_AC_SCR_02_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_02_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_02_0_G3R_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_02_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G2R_SHIFT)
+#define GPIO_AC_SCR_02_0_G2R_RANGE                      2:2
+#define GPIO_AC_SCR_02_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_02_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_02_0_G2R_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_02_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G1R_SHIFT)
+#define GPIO_AC_SCR_02_0_G1R_RANGE                      1:1
+#define GPIO_AC_SCR_02_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_02_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_02_0_G1R_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_02_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_02_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_02_0_G0R_SHIFT)
+#define GPIO_AC_SCR_02_0_G0R_RANGE                      0:0
+#define GPIO_AC_SCR_02_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_02_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_02_0_G0R_WOFFSET                    0x0
+#define GPIO_AC_SCR_02_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_02_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_02_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_VM_03_0
+#define GPIO_AC_VM_03_0                 MK_ADDR_CONST(0x58)
+#define GPIO_AC_VM_03_0_SECURE                  0x0
+#define GPIO_AC_VM_03_0_DUAL                    0x0
+#define GPIO_AC_VM_03_0_SCR                     GPIO_CTL0_VM_SCR_0
+#define GPIO_AC_VM_03_0_SCRREG                  GPIO_CTL0_VM_SCR_0
+#define GPIO_AC_VM_03_0_WORD_COUNT                      0x1
+#define GPIO_AC_VM_03_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_03_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_03_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_03_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AC_VM_03_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_03_0_VM1_SHIFT)
+#define GPIO_AC_VM_03_0_VM1_RANGE                       1:0
+#define GPIO_AC_VM_03_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AC_VM_03_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AC_VM_03_0_VM1_WOFFSET                     0x0
+#define GPIO_AC_VM_03_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_03_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_03_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_03_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AC_VM_03_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_03_0_VM2_SHIFT)
+#define GPIO_AC_VM_03_0_VM2_RANGE                       3:2
+#define GPIO_AC_VM_03_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AC_VM_03_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AC_VM_03_0_VM2_WOFFSET                     0x0
+#define GPIO_AC_VM_03_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_03_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_03_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_03_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AC_VM_03_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_03_0_VM3_SHIFT)
+#define GPIO_AC_VM_03_0_VM3_RANGE                       5:4
+#define GPIO_AC_VM_03_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AC_VM_03_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AC_VM_03_0_VM3_WOFFSET                     0x0
+#define GPIO_AC_VM_03_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_03_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_03_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_03_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AC_VM_03_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_03_0_VM4_SHIFT)
+#define GPIO_AC_VM_03_0_VM4_RANGE                       7:6
+#define GPIO_AC_VM_03_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AC_VM_03_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AC_VM_03_0_VM4_WOFFSET                     0x0
+#define GPIO_AC_VM_03_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_03_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_03_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_03_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AC_VM_03_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_03_0_VM5_SHIFT)
+#define GPIO_AC_VM_03_0_VM5_RANGE                       9:8
+#define GPIO_AC_VM_03_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AC_VM_03_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AC_VM_03_0_VM5_WOFFSET                     0x0
+#define GPIO_AC_VM_03_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_03_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_03_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_03_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AC_VM_03_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_03_0_VM6_SHIFT)
+#define GPIO_AC_VM_03_0_VM6_RANGE                       11:10
+#define GPIO_AC_VM_03_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AC_VM_03_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AC_VM_03_0_VM6_WOFFSET                     0x0
+#define GPIO_AC_VM_03_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_03_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_03_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_03_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AC_VM_03_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_03_0_VM7_SHIFT)
+#define GPIO_AC_VM_03_0_VM7_RANGE                       13:12
+#define GPIO_AC_VM_03_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AC_VM_03_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AC_VM_03_0_VM7_WOFFSET                     0x0
+#define GPIO_AC_VM_03_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_03_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_03_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_03_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AC_VM_03_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_03_0_VM8_SHIFT)
+#define GPIO_AC_VM_03_0_VM8_RANGE                       15:14
+#define GPIO_AC_VM_03_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AC_VM_03_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AC_VM_03_0_VM8_WOFFSET                     0x0
+#define GPIO_AC_VM_03_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_03_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_03_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_03_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_SCR_03_0
+#define GPIO_AC_SCR_03_0                        MK_ADDR_CONST(0x5c)
+#define GPIO_AC_SCR_03_0_SECURE                         0x0
+#define GPIO_AC_SCR_03_0_DUAL                   0x0
+#define GPIO_AC_SCR_03_0_SCR                    0
+#define GPIO_AC_SCR_03_0_SCRREG                         0
+#define GPIO_AC_SCR_03_0_WORD_COUNT                     0x1
+#define GPIO_AC_SCR_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_03_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_03_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_03_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_AC_SCR_03_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AC_SCR_03_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_03_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_03_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AC_SCR_03_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_03_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_AC_SCR_03_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AC_SCR_03_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_03_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_03_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AC_SCR_03_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_03_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_AC_SCR_03_0_SEC_REN_RANGE                  27:27
+#define GPIO_AC_SCR_03_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_03_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_03_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AC_SCR_03_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AC_SCR_03_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AC_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_AC_SCR_03_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AC_SCR_03_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AC_SCR_03_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AC_SCR_03_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AC_SCR_03_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AC_SCR_03_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_03_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_PR7_SHIFT)
+#define GPIO_AC_SCR_03_0_PR7_RANGE                      23:23
+#define GPIO_AC_SCR_03_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_03_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_03_0_PR7_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_03_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_PR6_SHIFT)
+#define GPIO_AC_SCR_03_0_PR6_RANGE                      22:22
+#define GPIO_AC_SCR_03_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_03_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_03_0_PR6_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_03_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_PR5_SHIFT)
+#define GPIO_AC_SCR_03_0_PR5_RANGE                      21:21
+#define GPIO_AC_SCR_03_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_03_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_03_0_PR5_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_03_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_PR4_SHIFT)
+#define GPIO_AC_SCR_03_0_PR4_RANGE                      20:20
+#define GPIO_AC_SCR_03_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_03_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_03_0_PR4_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_03_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_PR3_SHIFT)
+#define GPIO_AC_SCR_03_0_PR3_RANGE                      19:19
+#define GPIO_AC_SCR_03_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_03_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_03_0_PR3_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_03_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_PR2_SHIFT)
+#define GPIO_AC_SCR_03_0_PR2_RANGE                      18:18
+#define GPIO_AC_SCR_03_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_03_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_03_0_PR2_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_03_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_PR1_SHIFT)
+#define GPIO_AC_SCR_03_0_PR1_RANGE                      17:17
+#define GPIO_AC_SCR_03_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_03_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_03_0_PR1_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_03_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_PR0_SHIFT)
+#define GPIO_AC_SCR_03_0_PR0_RANGE                      16:16
+#define GPIO_AC_SCR_03_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_03_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_03_0_PR0_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_03_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G7W_SHIFT)
+#define GPIO_AC_SCR_03_0_G7W_RANGE                      15:15
+#define GPIO_AC_SCR_03_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_03_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_03_0_G7W_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_03_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G6W_SHIFT)
+#define GPIO_AC_SCR_03_0_G6W_RANGE                      14:14
+#define GPIO_AC_SCR_03_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_03_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_03_0_G6W_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_03_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G5W_SHIFT)
+#define GPIO_AC_SCR_03_0_G5W_RANGE                      13:13
+#define GPIO_AC_SCR_03_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_03_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_03_0_G5W_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_03_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G4W_SHIFT)
+#define GPIO_AC_SCR_03_0_G4W_RANGE                      12:12
+#define GPIO_AC_SCR_03_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_03_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_03_0_G4W_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_03_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G3W_SHIFT)
+#define GPIO_AC_SCR_03_0_G3W_RANGE                      11:11
+#define GPIO_AC_SCR_03_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_03_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_03_0_G3W_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_03_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G2W_SHIFT)
+#define GPIO_AC_SCR_03_0_G2W_RANGE                      10:10
+#define GPIO_AC_SCR_03_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_03_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_03_0_G2W_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_03_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G1W_SHIFT)
+#define GPIO_AC_SCR_03_0_G1W_RANGE                      9:9
+#define GPIO_AC_SCR_03_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_03_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_03_0_G1W_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_03_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G0W_SHIFT)
+#define GPIO_AC_SCR_03_0_G0W_RANGE                      8:8
+#define GPIO_AC_SCR_03_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_03_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_03_0_G0W_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_03_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G7R_SHIFT)
+#define GPIO_AC_SCR_03_0_G7R_RANGE                      7:7
+#define GPIO_AC_SCR_03_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_03_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_03_0_G7R_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_03_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G6R_SHIFT)
+#define GPIO_AC_SCR_03_0_G6R_RANGE                      6:6
+#define GPIO_AC_SCR_03_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_03_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_03_0_G6R_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_03_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G5R_SHIFT)
+#define GPIO_AC_SCR_03_0_G5R_RANGE                      5:5
+#define GPIO_AC_SCR_03_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_03_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_03_0_G5R_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_03_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G4R_SHIFT)
+#define GPIO_AC_SCR_03_0_G4R_RANGE                      4:4
+#define GPIO_AC_SCR_03_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_03_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_03_0_G4R_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_03_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G3R_SHIFT)
+#define GPIO_AC_SCR_03_0_G3R_RANGE                      3:3
+#define GPIO_AC_SCR_03_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_03_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_03_0_G3R_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_03_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G2R_SHIFT)
+#define GPIO_AC_SCR_03_0_G2R_RANGE                      2:2
+#define GPIO_AC_SCR_03_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_03_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_03_0_G2R_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_03_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G1R_SHIFT)
+#define GPIO_AC_SCR_03_0_G1R_RANGE                      1:1
+#define GPIO_AC_SCR_03_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_03_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_03_0_G1R_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_03_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_03_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_03_0_G0R_SHIFT)
+#define GPIO_AC_SCR_03_0_G0R_RANGE                      0:0
+#define GPIO_AC_SCR_03_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_03_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_03_0_G0R_WOFFSET                    0x0
+#define GPIO_AC_SCR_03_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_03_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_03_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_VM_04_0
+#define GPIO_AC_VM_04_0                 MK_ADDR_CONST(0x60)
+#define GPIO_AC_VM_04_0_SECURE                  0x0
+#define GPIO_AC_VM_04_0_DUAL                    0x0
+#define GPIO_AC_VM_04_0_SCR                     GPIO_CTL0_VM_SCR_0
+#define GPIO_AC_VM_04_0_SCRREG                  GPIO_CTL0_VM_SCR_0
+#define GPIO_AC_VM_04_0_WORD_COUNT                      0x1
+#define GPIO_AC_VM_04_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_04_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_04_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_04_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AC_VM_04_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_04_0_VM1_SHIFT)
+#define GPIO_AC_VM_04_0_VM1_RANGE                       1:0
+#define GPIO_AC_VM_04_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AC_VM_04_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AC_VM_04_0_VM1_WOFFSET                     0x0
+#define GPIO_AC_VM_04_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_04_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_04_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_04_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AC_VM_04_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_04_0_VM2_SHIFT)
+#define GPIO_AC_VM_04_0_VM2_RANGE                       3:2
+#define GPIO_AC_VM_04_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AC_VM_04_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AC_VM_04_0_VM2_WOFFSET                     0x0
+#define GPIO_AC_VM_04_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_04_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_04_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_04_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AC_VM_04_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_04_0_VM3_SHIFT)
+#define GPIO_AC_VM_04_0_VM3_RANGE                       5:4
+#define GPIO_AC_VM_04_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AC_VM_04_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AC_VM_04_0_VM3_WOFFSET                     0x0
+#define GPIO_AC_VM_04_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_04_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_04_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_04_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AC_VM_04_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_04_0_VM4_SHIFT)
+#define GPIO_AC_VM_04_0_VM4_RANGE                       7:6
+#define GPIO_AC_VM_04_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AC_VM_04_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AC_VM_04_0_VM4_WOFFSET                     0x0
+#define GPIO_AC_VM_04_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_04_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_04_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_04_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AC_VM_04_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_04_0_VM5_SHIFT)
+#define GPIO_AC_VM_04_0_VM5_RANGE                       9:8
+#define GPIO_AC_VM_04_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AC_VM_04_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AC_VM_04_0_VM5_WOFFSET                     0x0
+#define GPIO_AC_VM_04_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_04_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_04_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_04_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AC_VM_04_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_04_0_VM6_SHIFT)
+#define GPIO_AC_VM_04_0_VM6_RANGE                       11:10
+#define GPIO_AC_VM_04_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AC_VM_04_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AC_VM_04_0_VM6_WOFFSET                     0x0
+#define GPIO_AC_VM_04_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_04_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_04_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_04_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AC_VM_04_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_04_0_VM7_SHIFT)
+#define GPIO_AC_VM_04_0_VM7_RANGE                       13:12
+#define GPIO_AC_VM_04_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AC_VM_04_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AC_VM_04_0_VM7_WOFFSET                     0x0
+#define GPIO_AC_VM_04_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_04_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_04_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_04_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AC_VM_04_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_04_0_VM8_SHIFT)
+#define GPIO_AC_VM_04_0_VM8_RANGE                       15:14
+#define GPIO_AC_VM_04_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AC_VM_04_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AC_VM_04_0_VM8_WOFFSET                     0x0
+#define GPIO_AC_VM_04_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_04_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_04_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_04_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_SCR_04_0
+#define GPIO_AC_SCR_04_0                        MK_ADDR_CONST(0x64)
+#define GPIO_AC_SCR_04_0_SECURE                         0x0
+#define GPIO_AC_SCR_04_0_DUAL                   0x0
+#define GPIO_AC_SCR_04_0_SCR                    0
+#define GPIO_AC_SCR_04_0_SCRREG                         0
+#define GPIO_AC_SCR_04_0_WORD_COUNT                     0x1
+#define GPIO_AC_SCR_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_04_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_04_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_04_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_AC_SCR_04_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AC_SCR_04_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_04_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_04_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AC_SCR_04_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_04_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_AC_SCR_04_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AC_SCR_04_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_04_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_04_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AC_SCR_04_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_04_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_AC_SCR_04_0_SEC_REN_RANGE                  27:27
+#define GPIO_AC_SCR_04_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_04_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_04_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AC_SCR_04_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AC_SCR_04_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AC_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_AC_SCR_04_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AC_SCR_04_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AC_SCR_04_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AC_SCR_04_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AC_SCR_04_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AC_SCR_04_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_04_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_PR7_SHIFT)
+#define GPIO_AC_SCR_04_0_PR7_RANGE                      23:23
+#define GPIO_AC_SCR_04_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_04_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_04_0_PR7_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_04_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_PR6_SHIFT)
+#define GPIO_AC_SCR_04_0_PR6_RANGE                      22:22
+#define GPIO_AC_SCR_04_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_04_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_04_0_PR6_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_04_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_PR5_SHIFT)
+#define GPIO_AC_SCR_04_0_PR5_RANGE                      21:21
+#define GPIO_AC_SCR_04_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_04_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_04_0_PR5_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_04_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_PR4_SHIFT)
+#define GPIO_AC_SCR_04_0_PR4_RANGE                      20:20
+#define GPIO_AC_SCR_04_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_04_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_04_0_PR4_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_04_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_PR3_SHIFT)
+#define GPIO_AC_SCR_04_0_PR3_RANGE                      19:19
+#define GPIO_AC_SCR_04_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_04_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_04_0_PR3_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_04_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_PR2_SHIFT)
+#define GPIO_AC_SCR_04_0_PR2_RANGE                      18:18
+#define GPIO_AC_SCR_04_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_04_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_04_0_PR2_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_04_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_PR1_SHIFT)
+#define GPIO_AC_SCR_04_0_PR1_RANGE                      17:17
+#define GPIO_AC_SCR_04_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_04_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_04_0_PR1_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_04_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_PR0_SHIFT)
+#define GPIO_AC_SCR_04_0_PR0_RANGE                      16:16
+#define GPIO_AC_SCR_04_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_04_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_04_0_PR0_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_04_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G7W_SHIFT)
+#define GPIO_AC_SCR_04_0_G7W_RANGE                      15:15
+#define GPIO_AC_SCR_04_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_04_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_04_0_G7W_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_04_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G6W_SHIFT)
+#define GPIO_AC_SCR_04_0_G6W_RANGE                      14:14
+#define GPIO_AC_SCR_04_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_04_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_04_0_G6W_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_04_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G5W_SHIFT)
+#define GPIO_AC_SCR_04_0_G5W_RANGE                      13:13
+#define GPIO_AC_SCR_04_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_04_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_04_0_G5W_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_04_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G4W_SHIFT)
+#define GPIO_AC_SCR_04_0_G4W_RANGE                      12:12
+#define GPIO_AC_SCR_04_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_04_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_04_0_G4W_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_04_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G3W_SHIFT)
+#define GPIO_AC_SCR_04_0_G3W_RANGE                      11:11
+#define GPIO_AC_SCR_04_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_04_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_04_0_G3W_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_04_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G2W_SHIFT)
+#define GPIO_AC_SCR_04_0_G2W_RANGE                      10:10
+#define GPIO_AC_SCR_04_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_04_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_04_0_G2W_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_04_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G1W_SHIFT)
+#define GPIO_AC_SCR_04_0_G1W_RANGE                      9:9
+#define GPIO_AC_SCR_04_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_04_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_04_0_G1W_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_04_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G0W_SHIFT)
+#define GPIO_AC_SCR_04_0_G0W_RANGE                      8:8
+#define GPIO_AC_SCR_04_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_04_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_04_0_G0W_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_04_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G7R_SHIFT)
+#define GPIO_AC_SCR_04_0_G7R_RANGE                      7:7
+#define GPIO_AC_SCR_04_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_04_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_04_0_G7R_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_04_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G6R_SHIFT)
+#define GPIO_AC_SCR_04_0_G6R_RANGE                      6:6
+#define GPIO_AC_SCR_04_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_04_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_04_0_G6R_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_04_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G5R_SHIFT)
+#define GPIO_AC_SCR_04_0_G5R_RANGE                      5:5
+#define GPIO_AC_SCR_04_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_04_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_04_0_G5R_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_04_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G4R_SHIFT)
+#define GPIO_AC_SCR_04_0_G4R_RANGE                      4:4
+#define GPIO_AC_SCR_04_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_04_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_04_0_G4R_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_04_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G3R_SHIFT)
+#define GPIO_AC_SCR_04_0_G3R_RANGE                      3:3
+#define GPIO_AC_SCR_04_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_04_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_04_0_G3R_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_04_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G2R_SHIFT)
+#define GPIO_AC_SCR_04_0_G2R_RANGE                      2:2
+#define GPIO_AC_SCR_04_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_04_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_04_0_G2R_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_04_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G1R_SHIFT)
+#define GPIO_AC_SCR_04_0_G1R_RANGE                      1:1
+#define GPIO_AC_SCR_04_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_04_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_04_0_G1R_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_04_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_04_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_04_0_G0R_SHIFT)
+#define GPIO_AC_SCR_04_0_G0R_RANGE                      0:0
+#define GPIO_AC_SCR_04_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_04_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_04_0_G0R_WOFFSET                    0x0
+#define GPIO_AC_SCR_04_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_04_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_04_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_VM_05_0
+#define GPIO_AC_VM_05_0                 MK_ADDR_CONST(0x68)
+#define GPIO_AC_VM_05_0_SECURE                  0x0
+#define GPIO_AC_VM_05_0_DUAL                    0x0
+#define GPIO_AC_VM_05_0_SCR                     GPIO_CTL0_VM_SCR_0
+#define GPIO_AC_VM_05_0_SCRREG                  GPIO_CTL0_VM_SCR_0
+#define GPIO_AC_VM_05_0_WORD_COUNT                      0x1
+#define GPIO_AC_VM_05_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_05_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_05_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_05_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AC_VM_05_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_05_0_VM1_SHIFT)
+#define GPIO_AC_VM_05_0_VM1_RANGE                       1:0
+#define GPIO_AC_VM_05_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AC_VM_05_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AC_VM_05_0_VM1_WOFFSET                     0x0
+#define GPIO_AC_VM_05_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_05_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_05_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_05_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AC_VM_05_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_05_0_VM2_SHIFT)
+#define GPIO_AC_VM_05_0_VM2_RANGE                       3:2
+#define GPIO_AC_VM_05_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AC_VM_05_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AC_VM_05_0_VM2_WOFFSET                     0x0
+#define GPIO_AC_VM_05_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_05_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_05_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_05_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AC_VM_05_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_05_0_VM3_SHIFT)
+#define GPIO_AC_VM_05_0_VM3_RANGE                       5:4
+#define GPIO_AC_VM_05_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AC_VM_05_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AC_VM_05_0_VM3_WOFFSET                     0x0
+#define GPIO_AC_VM_05_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_05_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_05_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_05_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AC_VM_05_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_05_0_VM4_SHIFT)
+#define GPIO_AC_VM_05_0_VM4_RANGE                       7:6
+#define GPIO_AC_VM_05_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AC_VM_05_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AC_VM_05_0_VM4_WOFFSET                     0x0
+#define GPIO_AC_VM_05_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_05_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_05_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_05_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AC_VM_05_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_05_0_VM5_SHIFT)
+#define GPIO_AC_VM_05_0_VM5_RANGE                       9:8
+#define GPIO_AC_VM_05_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AC_VM_05_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AC_VM_05_0_VM5_WOFFSET                     0x0
+#define GPIO_AC_VM_05_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_05_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_05_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_05_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AC_VM_05_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_05_0_VM6_SHIFT)
+#define GPIO_AC_VM_05_0_VM6_RANGE                       11:10
+#define GPIO_AC_VM_05_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AC_VM_05_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AC_VM_05_0_VM6_WOFFSET                     0x0
+#define GPIO_AC_VM_05_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_05_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_05_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_05_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AC_VM_05_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_05_0_VM7_SHIFT)
+#define GPIO_AC_VM_05_0_VM7_RANGE                       13:12
+#define GPIO_AC_VM_05_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AC_VM_05_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AC_VM_05_0_VM7_WOFFSET                     0x0
+#define GPIO_AC_VM_05_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_05_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_05_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_05_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AC_VM_05_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_05_0_VM8_SHIFT)
+#define GPIO_AC_VM_05_0_VM8_RANGE                       15:14
+#define GPIO_AC_VM_05_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AC_VM_05_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AC_VM_05_0_VM8_WOFFSET                     0x0
+#define GPIO_AC_VM_05_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_05_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_05_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_05_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_SCR_05_0
+#define GPIO_AC_SCR_05_0                        MK_ADDR_CONST(0x6c)
+#define GPIO_AC_SCR_05_0_SECURE                         0x0
+#define GPIO_AC_SCR_05_0_DUAL                   0x0
+#define GPIO_AC_SCR_05_0_SCR                    0
+#define GPIO_AC_SCR_05_0_SCRREG                         0
+#define GPIO_AC_SCR_05_0_WORD_COUNT                     0x1
+#define GPIO_AC_SCR_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_05_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_05_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_05_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_AC_SCR_05_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AC_SCR_05_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_05_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_05_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AC_SCR_05_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_05_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_AC_SCR_05_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AC_SCR_05_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_05_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_05_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AC_SCR_05_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_05_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_AC_SCR_05_0_SEC_REN_RANGE                  27:27
+#define GPIO_AC_SCR_05_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_05_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_05_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AC_SCR_05_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AC_SCR_05_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AC_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_AC_SCR_05_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AC_SCR_05_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AC_SCR_05_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AC_SCR_05_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AC_SCR_05_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AC_SCR_05_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_05_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_PR7_SHIFT)
+#define GPIO_AC_SCR_05_0_PR7_RANGE                      23:23
+#define GPIO_AC_SCR_05_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_05_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_05_0_PR7_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_05_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_PR6_SHIFT)
+#define GPIO_AC_SCR_05_0_PR6_RANGE                      22:22
+#define GPIO_AC_SCR_05_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_05_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_05_0_PR6_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_05_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_PR5_SHIFT)
+#define GPIO_AC_SCR_05_0_PR5_RANGE                      21:21
+#define GPIO_AC_SCR_05_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_05_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_05_0_PR5_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_05_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_PR4_SHIFT)
+#define GPIO_AC_SCR_05_0_PR4_RANGE                      20:20
+#define GPIO_AC_SCR_05_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_05_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_05_0_PR4_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_05_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_PR3_SHIFT)
+#define GPIO_AC_SCR_05_0_PR3_RANGE                      19:19
+#define GPIO_AC_SCR_05_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_05_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_05_0_PR3_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_05_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_PR2_SHIFT)
+#define GPIO_AC_SCR_05_0_PR2_RANGE                      18:18
+#define GPIO_AC_SCR_05_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_05_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_05_0_PR2_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_05_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_PR1_SHIFT)
+#define GPIO_AC_SCR_05_0_PR1_RANGE                      17:17
+#define GPIO_AC_SCR_05_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_05_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_05_0_PR1_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_05_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_PR0_SHIFT)
+#define GPIO_AC_SCR_05_0_PR0_RANGE                      16:16
+#define GPIO_AC_SCR_05_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_05_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_05_0_PR0_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_05_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G7W_SHIFT)
+#define GPIO_AC_SCR_05_0_G7W_RANGE                      15:15
+#define GPIO_AC_SCR_05_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_05_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_05_0_G7W_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_05_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G6W_SHIFT)
+#define GPIO_AC_SCR_05_0_G6W_RANGE                      14:14
+#define GPIO_AC_SCR_05_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_05_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_05_0_G6W_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_05_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G5W_SHIFT)
+#define GPIO_AC_SCR_05_0_G5W_RANGE                      13:13
+#define GPIO_AC_SCR_05_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_05_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_05_0_G5W_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_05_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G4W_SHIFT)
+#define GPIO_AC_SCR_05_0_G4W_RANGE                      12:12
+#define GPIO_AC_SCR_05_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_05_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_05_0_G4W_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_05_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G3W_SHIFT)
+#define GPIO_AC_SCR_05_0_G3W_RANGE                      11:11
+#define GPIO_AC_SCR_05_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_05_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_05_0_G3W_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_05_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G2W_SHIFT)
+#define GPIO_AC_SCR_05_0_G2W_RANGE                      10:10
+#define GPIO_AC_SCR_05_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_05_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_05_0_G2W_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_05_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G1W_SHIFT)
+#define GPIO_AC_SCR_05_0_G1W_RANGE                      9:9
+#define GPIO_AC_SCR_05_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_05_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_05_0_G1W_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_05_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G0W_SHIFT)
+#define GPIO_AC_SCR_05_0_G0W_RANGE                      8:8
+#define GPIO_AC_SCR_05_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_05_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_05_0_G0W_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_05_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G7R_SHIFT)
+#define GPIO_AC_SCR_05_0_G7R_RANGE                      7:7
+#define GPIO_AC_SCR_05_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_05_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_05_0_G7R_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_05_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G6R_SHIFT)
+#define GPIO_AC_SCR_05_0_G6R_RANGE                      6:6
+#define GPIO_AC_SCR_05_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_05_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_05_0_G6R_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_05_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G5R_SHIFT)
+#define GPIO_AC_SCR_05_0_G5R_RANGE                      5:5
+#define GPIO_AC_SCR_05_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_05_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_05_0_G5R_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_05_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G4R_SHIFT)
+#define GPIO_AC_SCR_05_0_G4R_RANGE                      4:4
+#define GPIO_AC_SCR_05_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_05_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_05_0_G4R_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_05_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G3R_SHIFT)
+#define GPIO_AC_SCR_05_0_G3R_RANGE                      3:3
+#define GPIO_AC_SCR_05_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_05_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_05_0_G3R_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_05_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G2R_SHIFT)
+#define GPIO_AC_SCR_05_0_G2R_RANGE                      2:2
+#define GPIO_AC_SCR_05_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_05_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_05_0_G2R_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_05_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G1R_SHIFT)
+#define GPIO_AC_SCR_05_0_G1R_RANGE                      1:1
+#define GPIO_AC_SCR_05_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_05_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_05_0_G1R_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_05_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_05_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_05_0_G0R_SHIFT)
+#define GPIO_AC_SCR_05_0_G0R_RANGE                      0:0
+#define GPIO_AC_SCR_05_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_05_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_05_0_G0R_WOFFSET                    0x0
+#define GPIO_AC_SCR_05_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_05_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_05_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_VM_06_0
+#define GPIO_AC_VM_06_0                 MK_ADDR_CONST(0x70)
+#define GPIO_AC_VM_06_0_SECURE                  0x0
+#define GPIO_AC_VM_06_0_DUAL                    0x0
+#define GPIO_AC_VM_06_0_SCR                     GPIO_CTL0_VM_SCR_0
+#define GPIO_AC_VM_06_0_SCRREG                  GPIO_CTL0_VM_SCR_0
+#define GPIO_AC_VM_06_0_WORD_COUNT                      0x1
+#define GPIO_AC_VM_06_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_06_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_06_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_06_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AC_VM_06_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_06_0_VM1_SHIFT)
+#define GPIO_AC_VM_06_0_VM1_RANGE                       1:0
+#define GPIO_AC_VM_06_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AC_VM_06_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AC_VM_06_0_VM1_WOFFSET                     0x0
+#define GPIO_AC_VM_06_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_06_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_06_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_06_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AC_VM_06_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_06_0_VM2_SHIFT)
+#define GPIO_AC_VM_06_0_VM2_RANGE                       3:2
+#define GPIO_AC_VM_06_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AC_VM_06_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AC_VM_06_0_VM2_WOFFSET                     0x0
+#define GPIO_AC_VM_06_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_06_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_06_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_06_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AC_VM_06_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_06_0_VM3_SHIFT)
+#define GPIO_AC_VM_06_0_VM3_RANGE                       5:4
+#define GPIO_AC_VM_06_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AC_VM_06_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AC_VM_06_0_VM3_WOFFSET                     0x0
+#define GPIO_AC_VM_06_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_06_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_06_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_06_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AC_VM_06_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_06_0_VM4_SHIFT)
+#define GPIO_AC_VM_06_0_VM4_RANGE                       7:6
+#define GPIO_AC_VM_06_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AC_VM_06_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AC_VM_06_0_VM4_WOFFSET                     0x0
+#define GPIO_AC_VM_06_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_06_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_06_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_06_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AC_VM_06_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_06_0_VM5_SHIFT)
+#define GPIO_AC_VM_06_0_VM5_RANGE                       9:8
+#define GPIO_AC_VM_06_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AC_VM_06_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AC_VM_06_0_VM5_WOFFSET                     0x0
+#define GPIO_AC_VM_06_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_06_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_06_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_06_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AC_VM_06_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_06_0_VM6_SHIFT)
+#define GPIO_AC_VM_06_0_VM6_RANGE                       11:10
+#define GPIO_AC_VM_06_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AC_VM_06_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AC_VM_06_0_VM6_WOFFSET                     0x0
+#define GPIO_AC_VM_06_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_06_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_06_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_06_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AC_VM_06_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_06_0_VM7_SHIFT)
+#define GPIO_AC_VM_06_0_VM7_RANGE                       13:12
+#define GPIO_AC_VM_06_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AC_VM_06_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AC_VM_06_0_VM7_WOFFSET                     0x0
+#define GPIO_AC_VM_06_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_06_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_06_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_06_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AC_VM_06_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_06_0_VM8_SHIFT)
+#define GPIO_AC_VM_06_0_VM8_RANGE                       15:14
+#define GPIO_AC_VM_06_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AC_VM_06_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AC_VM_06_0_VM8_WOFFSET                     0x0
+#define GPIO_AC_VM_06_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_06_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_06_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_06_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_SCR_06_0
+#define GPIO_AC_SCR_06_0                        MK_ADDR_CONST(0x74)
+#define GPIO_AC_SCR_06_0_SECURE                         0x0
+#define GPIO_AC_SCR_06_0_DUAL                   0x0
+#define GPIO_AC_SCR_06_0_SCR                    0
+#define GPIO_AC_SCR_06_0_SCRREG                         0
+#define GPIO_AC_SCR_06_0_WORD_COUNT                     0x1
+#define GPIO_AC_SCR_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_06_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_06_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_06_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_SEC_LCK_SHIFT)
+#define GPIO_AC_SCR_06_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AC_SCR_06_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_06_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_06_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AC_SCR_06_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_06_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_SEC_WEN_SHIFT)
+#define GPIO_AC_SCR_06_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AC_SCR_06_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_06_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_06_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AC_SCR_06_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_06_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_SEC_REN_SHIFT)
+#define GPIO_AC_SCR_06_0_SEC_REN_RANGE                  27:27
+#define GPIO_AC_SCR_06_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_06_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_06_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AC_SCR_06_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AC_SCR_06_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AC_SCR_06_0_SEC_OWNER_SHIFT)
+#define GPIO_AC_SCR_06_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AC_SCR_06_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AC_SCR_06_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AC_SCR_06_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AC_SCR_06_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AC_SCR_06_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_06_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_PR7_SHIFT)
+#define GPIO_AC_SCR_06_0_PR7_RANGE                      23:23
+#define GPIO_AC_SCR_06_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_06_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_06_0_PR7_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_06_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_PR6_SHIFT)
+#define GPIO_AC_SCR_06_0_PR6_RANGE                      22:22
+#define GPIO_AC_SCR_06_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_06_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_06_0_PR6_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_06_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_PR5_SHIFT)
+#define GPIO_AC_SCR_06_0_PR5_RANGE                      21:21
+#define GPIO_AC_SCR_06_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_06_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_06_0_PR5_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_06_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_PR4_SHIFT)
+#define GPIO_AC_SCR_06_0_PR4_RANGE                      20:20
+#define GPIO_AC_SCR_06_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_06_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_06_0_PR4_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_06_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_PR3_SHIFT)
+#define GPIO_AC_SCR_06_0_PR3_RANGE                      19:19
+#define GPIO_AC_SCR_06_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_06_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_06_0_PR3_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_06_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_PR2_SHIFT)
+#define GPIO_AC_SCR_06_0_PR2_RANGE                      18:18
+#define GPIO_AC_SCR_06_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_06_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_06_0_PR2_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_06_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_PR1_SHIFT)
+#define GPIO_AC_SCR_06_0_PR1_RANGE                      17:17
+#define GPIO_AC_SCR_06_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_06_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_06_0_PR1_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_06_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_PR0_SHIFT)
+#define GPIO_AC_SCR_06_0_PR0_RANGE                      16:16
+#define GPIO_AC_SCR_06_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_06_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_06_0_PR0_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_06_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G7W_SHIFT)
+#define GPIO_AC_SCR_06_0_G7W_RANGE                      15:15
+#define GPIO_AC_SCR_06_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_06_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_06_0_G7W_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_06_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G6W_SHIFT)
+#define GPIO_AC_SCR_06_0_G6W_RANGE                      14:14
+#define GPIO_AC_SCR_06_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_06_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_06_0_G6W_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_06_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G5W_SHIFT)
+#define GPIO_AC_SCR_06_0_G5W_RANGE                      13:13
+#define GPIO_AC_SCR_06_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_06_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_06_0_G5W_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_06_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G4W_SHIFT)
+#define GPIO_AC_SCR_06_0_G4W_RANGE                      12:12
+#define GPIO_AC_SCR_06_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_06_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_06_0_G4W_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_06_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G3W_SHIFT)
+#define GPIO_AC_SCR_06_0_G3W_RANGE                      11:11
+#define GPIO_AC_SCR_06_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_06_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_06_0_G3W_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_06_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G2W_SHIFT)
+#define GPIO_AC_SCR_06_0_G2W_RANGE                      10:10
+#define GPIO_AC_SCR_06_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_06_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_06_0_G2W_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_06_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G1W_SHIFT)
+#define GPIO_AC_SCR_06_0_G1W_RANGE                      9:9
+#define GPIO_AC_SCR_06_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_06_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_06_0_G1W_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_06_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G0W_SHIFT)
+#define GPIO_AC_SCR_06_0_G0W_RANGE                      8:8
+#define GPIO_AC_SCR_06_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_06_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_06_0_G0W_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_06_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G7R_SHIFT)
+#define GPIO_AC_SCR_06_0_G7R_RANGE                      7:7
+#define GPIO_AC_SCR_06_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_06_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_06_0_G7R_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_06_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G6R_SHIFT)
+#define GPIO_AC_SCR_06_0_G6R_RANGE                      6:6
+#define GPIO_AC_SCR_06_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_06_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_06_0_G6R_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_06_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G5R_SHIFT)
+#define GPIO_AC_SCR_06_0_G5R_RANGE                      5:5
+#define GPIO_AC_SCR_06_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_06_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_06_0_G5R_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_06_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G4R_SHIFT)
+#define GPIO_AC_SCR_06_0_G4R_RANGE                      4:4
+#define GPIO_AC_SCR_06_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_06_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_06_0_G4R_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_06_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G3R_SHIFT)
+#define GPIO_AC_SCR_06_0_G3R_RANGE                      3:3
+#define GPIO_AC_SCR_06_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_06_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_06_0_G3R_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_06_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G2R_SHIFT)
+#define GPIO_AC_SCR_06_0_G2R_RANGE                      2:2
+#define GPIO_AC_SCR_06_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_06_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_06_0_G2R_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_06_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G1R_SHIFT)
+#define GPIO_AC_SCR_06_0_G1R_RANGE                      1:1
+#define GPIO_AC_SCR_06_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_06_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_06_0_G1R_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_06_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_06_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_06_0_G0R_SHIFT)
+#define GPIO_AC_SCR_06_0_G0R_RANGE                      0:0
+#define GPIO_AC_SCR_06_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_06_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_06_0_G0R_WOFFSET                    0x0
+#define GPIO_AC_SCR_06_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_06_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_06_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_VM_07_0
+#define GPIO_AC_VM_07_0                 MK_ADDR_CONST(0x78)
+#define GPIO_AC_VM_07_0_SECURE                  0x0
+#define GPIO_AC_VM_07_0_DUAL                    0x0
+#define GPIO_AC_VM_07_0_SCR                     GPIO_CTL0_VM_SCR_0
+#define GPIO_AC_VM_07_0_SCRREG                  GPIO_CTL0_VM_SCR_0
+#define GPIO_AC_VM_07_0_WORD_COUNT                      0x1
+#define GPIO_AC_VM_07_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_07_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_07_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AC_VM_07_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AC_VM_07_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_07_0_VM1_SHIFT)
+#define GPIO_AC_VM_07_0_VM1_RANGE                       1:0
+#define GPIO_AC_VM_07_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AC_VM_07_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AC_VM_07_0_VM1_WOFFSET                     0x0
+#define GPIO_AC_VM_07_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_07_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_07_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_07_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AC_VM_07_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_07_0_VM2_SHIFT)
+#define GPIO_AC_VM_07_0_VM2_RANGE                       3:2
+#define GPIO_AC_VM_07_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AC_VM_07_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AC_VM_07_0_VM2_WOFFSET                     0x0
+#define GPIO_AC_VM_07_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_07_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_07_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_07_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AC_VM_07_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_07_0_VM3_SHIFT)
+#define GPIO_AC_VM_07_0_VM3_RANGE                       5:4
+#define GPIO_AC_VM_07_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AC_VM_07_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AC_VM_07_0_VM3_WOFFSET                     0x0
+#define GPIO_AC_VM_07_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_07_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_07_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_07_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AC_VM_07_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_07_0_VM4_SHIFT)
+#define GPIO_AC_VM_07_0_VM4_RANGE                       7:6
+#define GPIO_AC_VM_07_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AC_VM_07_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AC_VM_07_0_VM4_WOFFSET                     0x0
+#define GPIO_AC_VM_07_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_07_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_07_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_07_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AC_VM_07_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_07_0_VM5_SHIFT)
+#define GPIO_AC_VM_07_0_VM5_RANGE                       9:8
+#define GPIO_AC_VM_07_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AC_VM_07_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AC_VM_07_0_VM5_WOFFSET                     0x0
+#define GPIO_AC_VM_07_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_07_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_07_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_07_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AC_VM_07_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_07_0_VM6_SHIFT)
+#define GPIO_AC_VM_07_0_VM6_RANGE                       11:10
+#define GPIO_AC_VM_07_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AC_VM_07_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AC_VM_07_0_VM6_WOFFSET                     0x0
+#define GPIO_AC_VM_07_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_07_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_07_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_07_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AC_VM_07_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_07_0_VM7_SHIFT)
+#define GPIO_AC_VM_07_0_VM7_RANGE                       13:12
+#define GPIO_AC_VM_07_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AC_VM_07_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AC_VM_07_0_VM7_WOFFSET                     0x0
+#define GPIO_AC_VM_07_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_07_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_07_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AC_VM_07_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AC_VM_07_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AC_VM_07_0_VM8_SHIFT)
+#define GPIO_AC_VM_07_0_VM8_RANGE                       15:14
+#define GPIO_AC_VM_07_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AC_VM_07_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AC_VM_07_0_VM8_WOFFSET                     0x0
+#define GPIO_AC_VM_07_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_07_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AC_VM_07_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_VM_07_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_SCR_07_0
+#define GPIO_AC_SCR_07_0                        MK_ADDR_CONST(0x7c)
+#define GPIO_AC_SCR_07_0_SECURE                         0x0
+#define GPIO_AC_SCR_07_0_DUAL                   0x0
+#define GPIO_AC_SCR_07_0_SCR                    0
+#define GPIO_AC_SCR_07_0_SCRREG                         0
+#define GPIO_AC_SCR_07_0_WORD_COUNT                     0x1
+#define GPIO_AC_SCR_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_07_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AC_SCR_07_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_07_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_SEC_LCK_SHIFT)
+#define GPIO_AC_SCR_07_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AC_SCR_07_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_07_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AC_SCR_07_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AC_SCR_07_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_07_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_SEC_WEN_SHIFT)
+#define GPIO_AC_SCR_07_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AC_SCR_07_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_07_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AC_SCR_07_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AC_SCR_07_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_07_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_SEC_REN_SHIFT)
+#define GPIO_AC_SCR_07_0_SEC_REN_RANGE                  27:27
+#define GPIO_AC_SCR_07_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_07_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AC_SCR_07_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AC_SCR_07_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AC_SCR_07_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AC_SCR_07_0_SEC_OWNER_SHIFT)
+#define GPIO_AC_SCR_07_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AC_SCR_07_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AC_SCR_07_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AC_SCR_07_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AC_SCR_07_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AC_SCR_07_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_07_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_PR7_SHIFT)
+#define GPIO_AC_SCR_07_0_PR7_RANGE                      23:23
+#define GPIO_AC_SCR_07_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_07_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AC_SCR_07_0_PR7_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_07_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_PR6_SHIFT)
+#define GPIO_AC_SCR_07_0_PR6_RANGE                      22:22
+#define GPIO_AC_SCR_07_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_07_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AC_SCR_07_0_PR6_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_07_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_PR5_SHIFT)
+#define GPIO_AC_SCR_07_0_PR5_RANGE                      21:21
+#define GPIO_AC_SCR_07_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_07_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AC_SCR_07_0_PR5_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_07_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_PR4_SHIFT)
+#define GPIO_AC_SCR_07_0_PR4_RANGE                      20:20
+#define GPIO_AC_SCR_07_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_07_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AC_SCR_07_0_PR4_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_07_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_PR3_SHIFT)
+#define GPIO_AC_SCR_07_0_PR3_RANGE                      19:19
+#define GPIO_AC_SCR_07_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_07_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AC_SCR_07_0_PR3_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_07_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_PR2_SHIFT)
+#define GPIO_AC_SCR_07_0_PR2_RANGE                      18:18
+#define GPIO_AC_SCR_07_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_07_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AC_SCR_07_0_PR2_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_07_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_PR1_SHIFT)
+#define GPIO_AC_SCR_07_0_PR1_RANGE                      17:17
+#define GPIO_AC_SCR_07_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_07_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AC_SCR_07_0_PR1_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_07_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_PR0_SHIFT)
+#define GPIO_AC_SCR_07_0_PR0_RANGE                      16:16
+#define GPIO_AC_SCR_07_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_07_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AC_SCR_07_0_PR0_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_07_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G7W_SHIFT)
+#define GPIO_AC_SCR_07_0_G7W_RANGE                      15:15
+#define GPIO_AC_SCR_07_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_07_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AC_SCR_07_0_G7W_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_07_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G6W_SHIFT)
+#define GPIO_AC_SCR_07_0_G6W_RANGE                      14:14
+#define GPIO_AC_SCR_07_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_07_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AC_SCR_07_0_G6W_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_07_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G5W_SHIFT)
+#define GPIO_AC_SCR_07_0_G5W_RANGE                      13:13
+#define GPIO_AC_SCR_07_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_07_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AC_SCR_07_0_G5W_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_07_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G4W_SHIFT)
+#define GPIO_AC_SCR_07_0_G4W_RANGE                      12:12
+#define GPIO_AC_SCR_07_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_07_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AC_SCR_07_0_G4W_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_07_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G3W_SHIFT)
+#define GPIO_AC_SCR_07_0_G3W_RANGE                      11:11
+#define GPIO_AC_SCR_07_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_07_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AC_SCR_07_0_G3W_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_07_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G2W_SHIFT)
+#define GPIO_AC_SCR_07_0_G2W_RANGE                      10:10
+#define GPIO_AC_SCR_07_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_07_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AC_SCR_07_0_G2W_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_07_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G1W_SHIFT)
+#define GPIO_AC_SCR_07_0_G1W_RANGE                      9:9
+#define GPIO_AC_SCR_07_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_07_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AC_SCR_07_0_G1W_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_07_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G0W_SHIFT)
+#define GPIO_AC_SCR_07_0_G0W_RANGE                      8:8
+#define GPIO_AC_SCR_07_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_07_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AC_SCR_07_0_G0W_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_07_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G7R_SHIFT)
+#define GPIO_AC_SCR_07_0_G7R_RANGE                      7:7
+#define GPIO_AC_SCR_07_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_07_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AC_SCR_07_0_G7R_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_07_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G6R_SHIFT)
+#define GPIO_AC_SCR_07_0_G6R_RANGE                      6:6
+#define GPIO_AC_SCR_07_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_07_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AC_SCR_07_0_G6R_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_07_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G5R_SHIFT)
+#define GPIO_AC_SCR_07_0_G5R_RANGE                      5:5
+#define GPIO_AC_SCR_07_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_07_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_SCR_07_0_G5R_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_07_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G4R_SHIFT)
+#define GPIO_AC_SCR_07_0_G4R_RANGE                      4:4
+#define GPIO_AC_SCR_07_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_07_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AC_SCR_07_0_G4R_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_07_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G3R_SHIFT)
+#define GPIO_AC_SCR_07_0_G3R_RANGE                      3:3
+#define GPIO_AC_SCR_07_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_07_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AC_SCR_07_0_G3R_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_07_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G2R_SHIFT)
+#define GPIO_AC_SCR_07_0_G2R_RANGE                      2:2
+#define GPIO_AC_SCR_07_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_07_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AC_SCR_07_0_G2R_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_07_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G1R_SHIFT)
+#define GPIO_AC_SCR_07_0_G1R_RANGE                      1:1
+#define GPIO_AC_SCR_07_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_07_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AC_SCR_07_0_G1R_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AC_SCR_07_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_07_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_SCR_07_0_G0R_SHIFT)
+#define GPIO_AC_SCR_07_0_G0R_RANGE                      0:0
+#define GPIO_AC_SCR_07_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_07_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_SCR_07_0_G0R_WOFFSET                    0x0
+#define GPIO_AC_SCR_07_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_SCR_07_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AC_SCR_07_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_VM_00_0
+#define GPIO_AD_VM_00_0                 MK_ADDR_CONST(0x80)
+#define GPIO_AD_VM_00_0_SECURE                  0x0
+#define GPIO_AD_VM_00_0_DUAL                    0x0
+#define GPIO_AD_VM_00_0_SCR                     GPIO_CTL0_VM_SCR_0
+#define GPIO_AD_VM_00_0_SCRREG                  GPIO_CTL0_VM_SCR_0
+#define GPIO_AD_VM_00_0_WORD_COUNT                      0x1
+#define GPIO_AD_VM_00_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AD_VM_00_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AD_VM_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AD_VM_00_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AD_VM_00_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AD_VM_00_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_00_0_VM1_SHIFT)
+#define GPIO_AD_VM_00_0_VM1_RANGE                       1:0
+#define GPIO_AD_VM_00_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AD_VM_00_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AD_VM_00_0_VM1_WOFFSET                     0x0
+#define GPIO_AD_VM_00_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_00_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_00_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_00_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AD_VM_00_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_00_0_VM2_SHIFT)
+#define GPIO_AD_VM_00_0_VM2_RANGE                       3:2
+#define GPIO_AD_VM_00_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AD_VM_00_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AD_VM_00_0_VM2_WOFFSET                     0x0
+#define GPIO_AD_VM_00_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_00_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_00_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_00_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AD_VM_00_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_00_0_VM3_SHIFT)
+#define GPIO_AD_VM_00_0_VM3_RANGE                       5:4
+#define GPIO_AD_VM_00_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AD_VM_00_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AD_VM_00_0_VM3_WOFFSET                     0x0
+#define GPIO_AD_VM_00_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_00_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_00_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_00_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AD_VM_00_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_00_0_VM4_SHIFT)
+#define GPIO_AD_VM_00_0_VM4_RANGE                       7:6
+#define GPIO_AD_VM_00_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AD_VM_00_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AD_VM_00_0_VM4_WOFFSET                     0x0
+#define GPIO_AD_VM_00_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_00_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_00_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_00_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AD_VM_00_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_00_0_VM5_SHIFT)
+#define GPIO_AD_VM_00_0_VM5_RANGE                       9:8
+#define GPIO_AD_VM_00_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AD_VM_00_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AD_VM_00_0_VM5_WOFFSET                     0x0
+#define GPIO_AD_VM_00_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_00_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_00_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_00_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AD_VM_00_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_00_0_VM6_SHIFT)
+#define GPIO_AD_VM_00_0_VM6_RANGE                       11:10
+#define GPIO_AD_VM_00_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AD_VM_00_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AD_VM_00_0_VM6_WOFFSET                     0x0
+#define GPIO_AD_VM_00_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_00_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_00_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_00_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AD_VM_00_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_00_0_VM7_SHIFT)
+#define GPIO_AD_VM_00_0_VM7_RANGE                       13:12
+#define GPIO_AD_VM_00_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AD_VM_00_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AD_VM_00_0_VM7_WOFFSET                     0x0
+#define GPIO_AD_VM_00_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_00_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_00_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_00_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AD_VM_00_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_00_0_VM8_SHIFT)
+#define GPIO_AD_VM_00_0_VM8_RANGE                       15:14
+#define GPIO_AD_VM_00_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AD_VM_00_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AD_VM_00_0_VM8_WOFFSET                     0x0
+#define GPIO_AD_VM_00_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_00_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_00_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_00_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_SCR_00_0
+#define GPIO_AD_SCR_00_0                        MK_ADDR_CONST(0x84)
+#define GPIO_AD_SCR_00_0_SECURE                         0x0
+#define GPIO_AD_SCR_00_0_DUAL                   0x0
+#define GPIO_AD_SCR_00_0_SCR                    0
+#define GPIO_AD_SCR_00_0_SCRREG                         0
+#define GPIO_AD_SCR_00_0_WORD_COUNT                     0x1
+#define GPIO_AD_SCR_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AD_SCR_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AD_SCR_00_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AD_SCR_00_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AD_SCR_00_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_AD_SCR_00_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AD_SCR_00_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AD_SCR_00_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AD_SCR_00_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AD_SCR_00_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AD_SCR_00_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_AD_SCR_00_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AD_SCR_00_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AD_SCR_00_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AD_SCR_00_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AD_SCR_00_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AD_SCR_00_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_AD_SCR_00_0_SEC_REN_RANGE                  27:27
+#define GPIO_AD_SCR_00_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AD_SCR_00_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AD_SCR_00_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AD_SCR_00_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AD_SCR_00_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AD_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_AD_SCR_00_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AD_SCR_00_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AD_SCR_00_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AD_SCR_00_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AD_SCR_00_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AD_SCR_00_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AD_SCR_00_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_PR7_SHIFT)
+#define GPIO_AD_SCR_00_0_PR7_RANGE                      23:23
+#define GPIO_AD_SCR_00_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AD_SCR_00_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AD_SCR_00_0_PR7_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AD_SCR_00_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_PR6_SHIFT)
+#define GPIO_AD_SCR_00_0_PR6_RANGE                      22:22
+#define GPIO_AD_SCR_00_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AD_SCR_00_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AD_SCR_00_0_PR6_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AD_SCR_00_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_PR5_SHIFT)
+#define GPIO_AD_SCR_00_0_PR5_RANGE                      21:21
+#define GPIO_AD_SCR_00_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AD_SCR_00_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AD_SCR_00_0_PR5_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AD_SCR_00_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_PR4_SHIFT)
+#define GPIO_AD_SCR_00_0_PR4_RANGE                      20:20
+#define GPIO_AD_SCR_00_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AD_SCR_00_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AD_SCR_00_0_PR4_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AD_SCR_00_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_PR3_SHIFT)
+#define GPIO_AD_SCR_00_0_PR3_RANGE                      19:19
+#define GPIO_AD_SCR_00_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AD_SCR_00_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AD_SCR_00_0_PR3_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AD_SCR_00_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_PR2_SHIFT)
+#define GPIO_AD_SCR_00_0_PR2_RANGE                      18:18
+#define GPIO_AD_SCR_00_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AD_SCR_00_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AD_SCR_00_0_PR2_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AD_SCR_00_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_PR1_SHIFT)
+#define GPIO_AD_SCR_00_0_PR1_RANGE                      17:17
+#define GPIO_AD_SCR_00_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AD_SCR_00_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AD_SCR_00_0_PR1_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AD_SCR_00_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_PR0_SHIFT)
+#define GPIO_AD_SCR_00_0_PR0_RANGE                      16:16
+#define GPIO_AD_SCR_00_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AD_SCR_00_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AD_SCR_00_0_PR0_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AD_SCR_00_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G7W_SHIFT)
+#define GPIO_AD_SCR_00_0_G7W_RANGE                      15:15
+#define GPIO_AD_SCR_00_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AD_SCR_00_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AD_SCR_00_0_G7W_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AD_SCR_00_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G6W_SHIFT)
+#define GPIO_AD_SCR_00_0_G6W_RANGE                      14:14
+#define GPIO_AD_SCR_00_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AD_SCR_00_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AD_SCR_00_0_G6W_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AD_SCR_00_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G5W_SHIFT)
+#define GPIO_AD_SCR_00_0_G5W_RANGE                      13:13
+#define GPIO_AD_SCR_00_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AD_SCR_00_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AD_SCR_00_0_G5W_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AD_SCR_00_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G4W_SHIFT)
+#define GPIO_AD_SCR_00_0_G4W_RANGE                      12:12
+#define GPIO_AD_SCR_00_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AD_SCR_00_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AD_SCR_00_0_G4W_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AD_SCR_00_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G3W_SHIFT)
+#define GPIO_AD_SCR_00_0_G3W_RANGE                      11:11
+#define GPIO_AD_SCR_00_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AD_SCR_00_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AD_SCR_00_0_G3W_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AD_SCR_00_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G2W_SHIFT)
+#define GPIO_AD_SCR_00_0_G2W_RANGE                      10:10
+#define GPIO_AD_SCR_00_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AD_SCR_00_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AD_SCR_00_0_G2W_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AD_SCR_00_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G1W_SHIFT)
+#define GPIO_AD_SCR_00_0_G1W_RANGE                      9:9
+#define GPIO_AD_SCR_00_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AD_SCR_00_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AD_SCR_00_0_G1W_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AD_SCR_00_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G0W_SHIFT)
+#define GPIO_AD_SCR_00_0_G0W_RANGE                      8:8
+#define GPIO_AD_SCR_00_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AD_SCR_00_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AD_SCR_00_0_G0W_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AD_SCR_00_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G7R_SHIFT)
+#define GPIO_AD_SCR_00_0_G7R_RANGE                      7:7
+#define GPIO_AD_SCR_00_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AD_SCR_00_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AD_SCR_00_0_G7R_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AD_SCR_00_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G6R_SHIFT)
+#define GPIO_AD_SCR_00_0_G6R_RANGE                      6:6
+#define GPIO_AD_SCR_00_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AD_SCR_00_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AD_SCR_00_0_G6R_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AD_SCR_00_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G5R_SHIFT)
+#define GPIO_AD_SCR_00_0_G5R_RANGE                      5:5
+#define GPIO_AD_SCR_00_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AD_SCR_00_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AD_SCR_00_0_G5R_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AD_SCR_00_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G4R_SHIFT)
+#define GPIO_AD_SCR_00_0_G4R_RANGE                      4:4
+#define GPIO_AD_SCR_00_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AD_SCR_00_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AD_SCR_00_0_G4R_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AD_SCR_00_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G3R_SHIFT)
+#define GPIO_AD_SCR_00_0_G3R_RANGE                      3:3
+#define GPIO_AD_SCR_00_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AD_SCR_00_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AD_SCR_00_0_G3R_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AD_SCR_00_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G2R_SHIFT)
+#define GPIO_AD_SCR_00_0_G2R_RANGE                      2:2
+#define GPIO_AD_SCR_00_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AD_SCR_00_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AD_SCR_00_0_G2R_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AD_SCR_00_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G1R_SHIFT)
+#define GPIO_AD_SCR_00_0_G1R_RANGE                      1:1
+#define GPIO_AD_SCR_00_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AD_SCR_00_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AD_SCR_00_0_G1R_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_00_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AD_SCR_00_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_00_0_G0R_SHIFT)
+#define GPIO_AD_SCR_00_0_G0R_RANGE                      0:0
+#define GPIO_AD_SCR_00_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AD_SCR_00_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AD_SCR_00_0_G0R_WOFFSET                    0x0
+#define GPIO_AD_SCR_00_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_00_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_00_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_VM_01_0
+#define GPIO_AD_VM_01_0                 MK_ADDR_CONST(0x88)
+#define GPIO_AD_VM_01_0_SECURE                  0x0
+#define GPIO_AD_VM_01_0_DUAL                    0x0
+#define GPIO_AD_VM_01_0_SCR                     GPIO_CTL0_VM_SCR_0
+#define GPIO_AD_VM_01_0_SCRREG                  GPIO_CTL0_VM_SCR_0
+#define GPIO_AD_VM_01_0_WORD_COUNT                      0x1
+#define GPIO_AD_VM_01_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AD_VM_01_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AD_VM_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AD_VM_01_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AD_VM_01_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AD_VM_01_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_01_0_VM1_SHIFT)
+#define GPIO_AD_VM_01_0_VM1_RANGE                       1:0
+#define GPIO_AD_VM_01_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AD_VM_01_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AD_VM_01_0_VM1_WOFFSET                     0x0
+#define GPIO_AD_VM_01_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_01_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_01_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_01_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AD_VM_01_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_01_0_VM2_SHIFT)
+#define GPIO_AD_VM_01_0_VM2_RANGE                       3:2
+#define GPIO_AD_VM_01_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AD_VM_01_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AD_VM_01_0_VM2_WOFFSET                     0x0
+#define GPIO_AD_VM_01_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_01_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_01_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_01_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AD_VM_01_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_01_0_VM3_SHIFT)
+#define GPIO_AD_VM_01_0_VM3_RANGE                       5:4
+#define GPIO_AD_VM_01_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AD_VM_01_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AD_VM_01_0_VM3_WOFFSET                     0x0
+#define GPIO_AD_VM_01_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_01_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_01_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_01_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AD_VM_01_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_01_0_VM4_SHIFT)
+#define GPIO_AD_VM_01_0_VM4_RANGE                       7:6
+#define GPIO_AD_VM_01_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AD_VM_01_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AD_VM_01_0_VM4_WOFFSET                     0x0
+#define GPIO_AD_VM_01_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_01_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_01_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_01_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AD_VM_01_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_01_0_VM5_SHIFT)
+#define GPIO_AD_VM_01_0_VM5_RANGE                       9:8
+#define GPIO_AD_VM_01_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AD_VM_01_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AD_VM_01_0_VM5_WOFFSET                     0x0
+#define GPIO_AD_VM_01_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_01_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_01_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_01_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AD_VM_01_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_01_0_VM6_SHIFT)
+#define GPIO_AD_VM_01_0_VM6_RANGE                       11:10
+#define GPIO_AD_VM_01_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AD_VM_01_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AD_VM_01_0_VM6_WOFFSET                     0x0
+#define GPIO_AD_VM_01_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_01_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_01_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_01_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AD_VM_01_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_01_0_VM7_SHIFT)
+#define GPIO_AD_VM_01_0_VM7_RANGE                       13:12
+#define GPIO_AD_VM_01_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AD_VM_01_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AD_VM_01_0_VM7_WOFFSET                     0x0
+#define GPIO_AD_VM_01_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_01_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_01_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_01_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AD_VM_01_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_01_0_VM8_SHIFT)
+#define GPIO_AD_VM_01_0_VM8_RANGE                       15:14
+#define GPIO_AD_VM_01_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AD_VM_01_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AD_VM_01_0_VM8_WOFFSET                     0x0
+#define GPIO_AD_VM_01_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_01_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_01_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_01_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_SCR_01_0
+#define GPIO_AD_SCR_01_0                        MK_ADDR_CONST(0x8c)
+#define GPIO_AD_SCR_01_0_SECURE                         0x0
+#define GPIO_AD_SCR_01_0_DUAL                   0x0
+#define GPIO_AD_SCR_01_0_SCR                    0
+#define GPIO_AD_SCR_01_0_SCRREG                         0
+#define GPIO_AD_SCR_01_0_WORD_COUNT                     0x1
+#define GPIO_AD_SCR_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AD_SCR_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AD_SCR_01_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AD_SCR_01_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AD_SCR_01_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_AD_SCR_01_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AD_SCR_01_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AD_SCR_01_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AD_SCR_01_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AD_SCR_01_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AD_SCR_01_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_AD_SCR_01_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AD_SCR_01_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AD_SCR_01_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AD_SCR_01_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AD_SCR_01_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AD_SCR_01_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_AD_SCR_01_0_SEC_REN_RANGE                  27:27
+#define GPIO_AD_SCR_01_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AD_SCR_01_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AD_SCR_01_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AD_SCR_01_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AD_SCR_01_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AD_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_AD_SCR_01_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AD_SCR_01_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AD_SCR_01_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AD_SCR_01_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AD_SCR_01_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AD_SCR_01_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AD_SCR_01_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_PR7_SHIFT)
+#define GPIO_AD_SCR_01_0_PR7_RANGE                      23:23
+#define GPIO_AD_SCR_01_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AD_SCR_01_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AD_SCR_01_0_PR7_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AD_SCR_01_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_PR6_SHIFT)
+#define GPIO_AD_SCR_01_0_PR6_RANGE                      22:22
+#define GPIO_AD_SCR_01_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AD_SCR_01_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AD_SCR_01_0_PR6_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AD_SCR_01_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_PR5_SHIFT)
+#define GPIO_AD_SCR_01_0_PR5_RANGE                      21:21
+#define GPIO_AD_SCR_01_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AD_SCR_01_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AD_SCR_01_0_PR5_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AD_SCR_01_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_PR4_SHIFT)
+#define GPIO_AD_SCR_01_0_PR4_RANGE                      20:20
+#define GPIO_AD_SCR_01_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AD_SCR_01_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AD_SCR_01_0_PR4_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AD_SCR_01_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_PR3_SHIFT)
+#define GPIO_AD_SCR_01_0_PR3_RANGE                      19:19
+#define GPIO_AD_SCR_01_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AD_SCR_01_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AD_SCR_01_0_PR3_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AD_SCR_01_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_PR2_SHIFT)
+#define GPIO_AD_SCR_01_0_PR2_RANGE                      18:18
+#define GPIO_AD_SCR_01_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AD_SCR_01_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AD_SCR_01_0_PR2_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AD_SCR_01_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_PR1_SHIFT)
+#define GPIO_AD_SCR_01_0_PR1_RANGE                      17:17
+#define GPIO_AD_SCR_01_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AD_SCR_01_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AD_SCR_01_0_PR1_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AD_SCR_01_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_PR0_SHIFT)
+#define GPIO_AD_SCR_01_0_PR0_RANGE                      16:16
+#define GPIO_AD_SCR_01_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AD_SCR_01_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AD_SCR_01_0_PR0_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AD_SCR_01_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G7W_SHIFT)
+#define GPIO_AD_SCR_01_0_G7W_RANGE                      15:15
+#define GPIO_AD_SCR_01_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AD_SCR_01_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AD_SCR_01_0_G7W_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AD_SCR_01_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G6W_SHIFT)
+#define GPIO_AD_SCR_01_0_G6W_RANGE                      14:14
+#define GPIO_AD_SCR_01_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AD_SCR_01_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AD_SCR_01_0_G6W_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AD_SCR_01_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G5W_SHIFT)
+#define GPIO_AD_SCR_01_0_G5W_RANGE                      13:13
+#define GPIO_AD_SCR_01_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AD_SCR_01_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AD_SCR_01_0_G5W_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AD_SCR_01_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G4W_SHIFT)
+#define GPIO_AD_SCR_01_0_G4W_RANGE                      12:12
+#define GPIO_AD_SCR_01_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AD_SCR_01_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AD_SCR_01_0_G4W_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AD_SCR_01_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G3W_SHIFT)
+#define GPIO_AD_SCR_01_0_G3W_RANGE                      11:11
+#define GPIO_AD_SCR_01_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AD_SCR_01_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AD_SCR_01_0_G3W_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AD_SCR_01_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G2W_SHIFT)
+#define GPIO_AD_SCR_01_0_G2W_RANGE                      10:10
+#define GPIO_AD_SCR_01_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AD_SCR_01_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AD_SCR_01_0_G2W_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AD_SCR_01_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G1W_SHIFT)
+#define GPIO_AD_SCR_01_0_G1W_RANGE                      9:9
+#define GPIO_AD_SCR_01_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AD_SCR_01_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AD_SCR_01_0_G1W_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AD_SCR_01_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G0W_SHIFT)
+#define GPIO_AD_SCR_01_0_G0W_RANGE                      8:8
+#define GPIO_AD_SCR_01_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AD_SCR_01_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AD_SCR_01_0_G0W_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AD_SCR_01_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G7R_SHIFT)
+#define GPIO_AD_SCR_01_0_G7R_RANGE                      7:7
+#define GPIO_AD_SCR_01_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AD_SCR_01_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AD_SCR_01_0_G7R_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AD_SCR_01_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G6R_SHIFT)
+#define GPIO_AD_SCR_01_0_G6R_RANGE                      6:6
+#define GPIO_AD_SCR_01_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AD_SCR_01_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AD_SCR_01_0_G6R_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AD_SCR_01_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G5R_SHIFT)
+#define GPIO_AD_SCR_01_0_G5R_RANGE                      5:5
+#define GPIO_AD_SCR_01_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AD_SCR_01_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AD_SCR_01_0_G5R_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AD_SCR_01_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G4R_SHIFT)
+#define GPIO_AD_SCR_01_0_G4R_RANGE                      4:4
+#define GPIO_AD_SCR_01_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AD_SCR_01_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AD_SCR_01_0_G4R_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AD_SCR_01_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G3R_SHIFT)
+#define GPIO_AD_SCR_01_0_G3R_RANGE                      3:3
+#define GPIO_AD_SCR_01_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AD_SCR_01_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AD_SCR_01_0_G3R_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AD_SCR_01_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G2R_SHIFT)
+#define GPIO_AD_SCR_01_0_G2R_RANGE                      2:2
+#define GPIO_AD_SCR_01_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AD_SCR_01_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AD_SCR_01_0_G2R_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AD_SCR_01_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G1R_SHIFT)
+#define GPIO_AD_SCR_01_0_G1R_RANGE                      1:1
+#define GPIO_AD_SCR_01_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AD_SCR_01_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AD_SCR_01_0_G1R_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_01_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AD_SCR_01_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_01_0_G0R_SHIFT)
+#define GPIO_AD_SCR_01_0_G0R_RANGE                      0:0
+#define GPIO_AD_SCR_01_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AD_SCR_01_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AD_SCR_01_0_G0R_WOFFSET                    0x0
+#define GPIO_AD_SCR_01_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_01_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_01_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_VM_02_0
+#define GPIO_AD_VM_02_0                 MK_ADDR_CONST(0x90)
+#define GPIO_AD_VM_02_0_SECURE                  0x0
+#define GPIO_AD_VM_02_0_DUAL                    0x0
+#define GPIO_AD_VM_02_0_SCR                     GPIO_CTL0_VM_SCR_0
+#define GPIO_AD_VM_02_0_SCRREG                  GPIO_CTL0_VM_SCR_0
+#define GPIO_AD_VM_02_0_WORD_COUNT                      0x1
+#define GPIO_AD_VM_02_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AD_VM_02_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AD_VM_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AD_VM_02_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AD_VM_02_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AD_VM_02_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_02_0_VM1_SHIFT)
+#define GPIO_AD_VM_02_0_VM1_RANGE                       1:0
+#define GPIO_AD_VM_02_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AD_VM_02_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AD_VM_02_0_VM1_WOFFSET                     0x0
+#define GPIO_AD_VM_02_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_02_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_02_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_02_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AD_VM_02_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_02_0_VM2_SHIFT)
+#define GPIO_AD_VM_02_0_VM2_RANGE                       3:2
+#define GPIO_AD_VM_02_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AD_VM_02_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AD_VM_02_0_VM2_WOFFSET                     0x0
+#define GPIO_AD_VM_02_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_02_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_02_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_02_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AD_VM_02_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_02_0_VM3_SHIFT)
+#define GPIO_AD_VM_02_0_VM3_RANGE                       5:4
+#define GPIO_AD_VM_02_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AD_VM_02_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AD_VM_02_0_VM3_WOFFSET                     0x0
+#define GPIO_AD_VM_02_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_02_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_02_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_02_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AD_VM_02_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_02_0_VM4_SHIFT)
+#define GPIO_AD_VM_02_0_VM4_RANGE                       7:6
+#define GPIO_AD_VM_02_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AD_VM_02_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AD_VM_02_0_VM4_WOFFSET                     0x0
+#define GPIO_AD_VM_02_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_02_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_02_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_02_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AD_VM_02_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_02_0_VM5_SHIFT)
+#define GPIO_AD_VM_02_0_VM5_RANGE                       9:8
+#define GPIO_AD_VM_02_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AD_VM_02_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AD_VM_02_0_VM5_WOFFSET                     0x0
+#define GPIO_AD_VM_02_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_02_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_02_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_02_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AD_VM_02_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_02_0_VM6_SHIFT)
+#define GPIO_AD_VM_02_0_VM6_RANGE                       11:10
+#define GPIO_AD_VM_02_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AD_VM_02_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AD_VM_02_0_VM6_WOFFSET                     0x0
+#define GPIO_AD_VM_02_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_02_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_02_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_02_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AD_VM_02_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_02_0_VM7_SHIFT)
+#define GPIO_AD_VM_02_0_VM7_RANGE                       13:12
+#define GPIO_AD_VM_02_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AD_VM_02_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AD_VM_02_0_VM7_WOFFSET                     0x0
+#define GPIO_AD_VM_02_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_02_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_02_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_02_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AD_VM_02_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_02_0_VM8_SHIFT)
+#define GPIO_AD_VM_02_0_VM8_RANGE                       15:14
+#define GPIO_AD_VM_02_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AD_VM_02_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AD_VM_02_0_VM8_WOFFSET                     0x0
+#define GPIO_AD_VM_02_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_02_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_02_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_02_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_SCR_02_0
+#define GPIO_AD_SCR_02_0                        MK_ADDR_CONST(0x94)
+#define GPIO_AD_SCR_02_0_SECURE                         0x0
+#define GPIO_AD_SCR_02_0_DUAL                   0x0
+#define GPIO_AD_SCR_02_0_SCR                    0
+#define GPIO_AD_SCR_02_0_SCRREG                         0
+#define GPIO_AD_SCR_02_0_WORD_COUNT                     0x1
+#define GPIO_AD_SCR_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AD_SCR_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AD_SCR_02_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AD_SCR_02_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AD_SCR_02_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_AD_SCR_02_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AD_SCR_02_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AD_SCR_02_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AD_SCR_02_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AD_SCR_02_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AD_SCR_02_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_AD_SCR_02_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AD_SCR_02_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AD_SCR_02_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AD_SCR_02_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AD_SCR_02_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AD_SCR_02_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_AD_SCR_02_0_SEC_REN_RANGE                  27:27
+#define GPIO_AD_SCR_02_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AD_SCR_02_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AD_SCR_02_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AD_SCR_02_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AD_SCR_02_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AD_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_AD_SCR_02_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AD_SCR_02_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AD_SCR_02_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AD_SCR_02_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AD_SCR_02_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AD_SCR_02_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AD_SCR_02_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_PR7_SHIFT)
+#define GPIO_AD_SCR_02_0_PR7_RANGE                      23:23
+#define GPIO_AD_SCR_02_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AD_SCR_02_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AD_SCR_02_0_PR7_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AD_SCR_02_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_PR6_SHIFT)
+#define GPIO_AD_SCR_02_0_PR6_RANGE                      22:22
+#define GPIO_AD_SCR_02_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AD_SCR_02_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AD_SCR_02_0_PR6_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AD_SCR_02_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_PR5_SHIFT)
+#define GPIO_AD_SCR_02_0_PR5_RANGE                      21:21
+#define GPIO_AD_SCR_02_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AD_SCR_02_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AD_SCR_02_0_PR5_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AD_SCR_02_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_PR4_SHIFT)
+#define GPIO_AD_SCR_02_0_PR4_RANGE                      20:20
+#define GPIO_AD_SCR_02_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AD_SCR_02_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AD_SCR_02_0_PR4_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AD_SCR_02_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_PR3_SHIFT)
+#define GPIO_AD_SCR_02_0_PR3_RANGE                      19:19
+#define GPIO_AD_SCR_02_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AD_SCR_02_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AD_SCR_02_0_PR3_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AD_SCR_02_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_PR2_SHIFT)
+#define GPIO_AD_SCR_02_0_PR2_RANGE                      18:18
+#define GPIO_AD_SCR_02_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AD_SCR_02_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AD_SCR_02_0_PR2_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AD_SCR_02_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_PR1_SHIFT)
+#define GPIO_AD_SCR_02_0_PR1_RANGE                      17:17
+#define GPIO_AD_SCR_02_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AD_SCR_02_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AD_SCR_02_0_PR1_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AD_SCR_02_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_PR0_SHIFT)
+#define GPIO_AD_SCR_02_0_PR0_RANGE                      16:16
+#define GPIO_AD_SCR_02_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AD_SCR_02_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AD_SCR_02_0_PR0_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AD_SCR_02_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G7W_SHIFT)
+#define GPIO_AD_SCR_02_0_G7W_RANGE                      15:15
+#define GPIO_AD_SCR_02_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AD_SCR_02_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AD_SCR_02_0_G7W_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AD_SCR_02_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G6W_SHIFT)
+#define GPIO_AD_SCR_02_0_G6W_RANGE                      14:14
+#define GPIO_AD_SCR_02_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AD_SCR_02_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AD_SCR_02_0_G6W_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AD_SCR_02_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G5W_SHIFT)
+#define GPIO_AD_SCR_02_0_G5W_RANGE                      13:13
+#define GPIO_AD_SCR_02_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AD_SCR_02_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AD_SCR_02_0_G5W_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AD_SCR_02_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G4W_SHIFT)
+#define GPIO_AD_SCR_02_0_G4W_RANGE                      12:12
+#define GPIO_AD_SCR_02_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AD_SCR_02_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AD_SCR_02_0_G4W_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AD_SCR_02_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G3W_SHIFT)
+#define GPIO_AD_SCR_02_0_G3W_RANGE                      11:11
+#define GPIO_AD_SCR_02_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AD_SCR_02_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AD_SCR_02_0_G3W_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AD_SCR_02_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G2W_SHIFT)
+#define GPIO_AD_SCR_02_0_G2W_RANGE                      10:10
+#define GPIO_AD_SCR_02_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AD_SCR_02_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AD_SCR_02_0_G2W_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AD_SCR_02_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G1W_SHIFT)
+#define GPIO_AD_SCR_02_0_G1W_RANGE                      9:9
+#define GPIO_AD_SCR_02_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AD_SCR_02_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AD_SCR_02_0_G1W_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AD_SCR_02_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G0W_SHIFT)
+#define GPIO_AD_SCR_02_0_G0W_RANGE                      8:8
+#define GPIO_AD_SCR_02_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AD_SCR_02_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AD_SCR_02_0_G0W_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AD_SCR_02_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G7R_SHIFT)
+#define GPIO_AD_SCR_02_0_G7R_RANGE                      7:7
+#define GPIO_AD_SCR_02_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AD_SCR_02_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AD_SCR_02_0_G7R_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AD_SCR_02_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G6R_SHIFT)
+#define GPIO_AD_SCR_02_0_G6R_RANGE                      6:6
+#define GPIO_AD_SCR_02_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AD_SCR_02_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AD_SCR_02_0_G6R_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AD_SCR_02_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G5R_SHIFT)
+#define GPIO_AD_SCR_02_0_G5R_RANGE                      5:5
+#define GPIO_AD_SCR_02_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AD_SCR_02_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AD_SCR_02_0_G5R_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AD_SCR_02_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G4R_SHIFT)
+#define GPIO_AD_SCR_02_0_G4R_RANGE                      4:4
+#define GPIO_AD_SCR_02_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AD_SCR_02_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AD_SCR_02_0_G4R_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AD_SCR_02_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G3R_SHIFT)
+#define GPIO_AD_SCR_02_0_G3R_RANGE                      3:3
+#define GPIO_AD_SCR_02_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AD_SCR_02_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AD_SCR_02_0_G3R_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AD_SCR_02_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G2R_SHIFT)
+#define GPIO_AD_SCR_02_0_G2R_RANGE                      2:2
+#define GPIO_AD_SCR_02_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AD_SCR_02_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AD_SCR_02_0_G2R_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AD_SCR_02_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G1R_SHIFT)
+#define GPIO_AD_SCR_02_0_G1R_RANGE                      1:1
+#define GPIO_AD_SCR_02_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AD_SCR_02_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AD_SCR_02_0_G1R_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_02_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AD_SCR_02_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_02_0_G0R_SHIFT)
+#define GPIO_AD_SCR_02_0_G0R_RANGE                      0:0
+#define GPIO_AD_SCR_02_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AD_SCR_02_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AD_SCR_02_0_G0R_WOFFSET                    0x0
+#define GPIO_AD_SCR_02_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_02_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_02_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_VM_03_0
+#define GPIO_AD_VM_03_0                 MK_ADDR_CONST(0x98)
+#define GPIO_AD_VM_03_0_SECURE                  0x0
+#define GPIO_AD_VM_03_0_DUAL                    0x0
+#define GPIO_AD_VM_03_0_SCR                     GPIO_CTL0_VM_SCR_0
+#define GPIO_AD_VM_03_0_SCRREG                  GPIO_CTL0_VM_SCR_0
+#define GPIO_AD_VM_03_0_WORD_COUNT                      0x1
+#define GPIO_AD_VM_03_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AD_VM_03_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AD_VM_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AD_VM_03_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AD_VM_03_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AD_VM_03_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_03_0_VM1_SHIFT)
+#define GPIO_AD_VM_03_0_VM1_RANGE                       1:0
+#define GPIO_AD_VM_03_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AD_VM_03_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AD_VM_03_0_VM1_WOFFSET                     0x0
+#define GPIO_AD_VM_03_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_03_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_03_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_03_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AD_VM_03_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_03_0_VM2_SHIFT)
+#define GPIO_AD_VM_03_0_VM2_RANGE                       3:2
+#define GPIO_AD_VM_03_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AD_VM_03_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AD_VM_03_0_VM2_WOFFSET                     0x0
+#define GPIO_AD_VM_03_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_03_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_03_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_03_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AD_VM_03_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_03_0_VM3_SHIFT)
+#define GPIO_AD_VM_03_0_VM3_RANGE                       5:4
+#define GPIO_AD_VM_03_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AD_VM_03_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AD_VM_03_0_VM3_WOFFSET                     0x0
+#define GPIO_AD_VM_03_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_03_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_03_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_03_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AD_VM_03_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_03_0_VM4_SHIFT)
+#define GPIO_AD_VM_03_0_VM4_RANGE                       7:6
+#define GPIO_AD_VM_03_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AD_VM_03_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AD_VM_03_0_VM4_WOFFSET                     0x0
+#define GPIO_AD_VM_03_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_03_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_03_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_03_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AD_VM_03_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_03_0_VM5_SHIFT)
+#define GPIO_AD_VM_03_0_VM5_RANGE                       9:8
+#define GPIO_AD_VM_03_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AD_VM_03_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AD_VM_03_0_VM5_WOFFSET                     0x0
+#define GPIO_AD_VM_03_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_03_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_03_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_03_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AD_VM_03_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_03_0_VM6_SHIFT)
+#define GPIO_AD_VM_03_0_VM6_RANGE                       11:10
+#define GPIO_AD_VM_03_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AD_VM_03_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AD_VM_03_0_VM6_WOFFSET                     0x0
+#define GPIO_AD_VM_03_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_03_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_03_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_03_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AD_VM_03_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_03_0_VM7_SHIFT)
+#define GPIO_AD_VM_03_0_VM7_RANGE                       13:12
+#define GPIO_AD_VM_03_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AD_VM_03_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AD_VM_03_0_VM7_WOFFSET                     0x0
+#define GPIO_AD_VM_03_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_03_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_03_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AD_VM_03_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AD_VM_03_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AD_VM_03_0_VM8_SHIFT)
+#define GPIO_AD_VM_03_0_VM8_RANGE                       15:14
+#define GPIO_AD_VM_03_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AD_VM_03_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AD_VM_03_0_VM8_WOFFSET                     0x0
+#define GPIO_AD_VM_03_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_03_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AD_VM_03_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_VM_03_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_SCR_03_0
+#define GPIO_AD_SCR_03_0                        MK_ADDR_CONST(0x9c)
+#define GPIO_AD_SCR_03_0_SECURE                         0x0
+#define GPIO_AD_SCR_03_0_DUAL                   0x0
+#define GPIO_AD_SCR_03_0_SCR                    0
+#define GPIO_AD_SCR_03_0_SCRREG                         0
+#define GPIO_AD_SCR_03_0_WORD_COUNT                     0x1
+#define GPIO_AD_SCR_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AD_SCR_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AD_SCR_03_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AD_SCR_03_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AD_SCR_03_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_AD_SCR_03_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AD_SCR_03_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AD_SCR_03_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AD_SCR_03_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AD_SCR_03_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AD_SCR_03_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_AD_SCR_03_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AD_SCR_03_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AD_SCR_03_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AD_SCR_03_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AD_SCR_03_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AD_SCR_03_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_AD_SCR_03_0_SEC_REN_RANGE                  27:27
+#define GPIO_AD_SCR_03_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AD_SCR_03_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AD_SCR_03_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AD_SCR_03_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AD_SCR_03_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AD_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_AD_SCR_03_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AD_SCR_03_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AD_SCR_03_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AD_SCR_03_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AD_SCR_03_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AD_SCR_03_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AD_SCR_03_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_PR7_SHIFT)
+#define GPIO_AD_SCR_03_0_PR7_RANGE                      23:23
+#define GPIO_AD_SCR_03_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AD_SCR_03_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AD_SCR_03_0_PR7_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AD_SCR_03_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_PR6_SHIFT)
+#define GPIO_AD_SCR_03_0_PR6_RANGE                      22:22
+#define GPIO_AD_SCR_03_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AD_SCR_03_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AD_SCR_03_0_PR6_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AD_SCR_03_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_PR5_SHIFT)
+#define GPIO_AD_SCR_03_0_PR5_RANGE                      21:21
+#define GPIO_AD_SCR_03_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AD_SCR_03_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AD_SCR_03_0_PR5_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AD_SCR_03_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_PR4_SHIFT)
+#define GPIO_AD_SCR_03_0_PR4_RANGE                      20:20
+#define GPIO_AD_SCR_03_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AD_SCR_03_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AD_SCR_03_0_PR4_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AD_SCR_03_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_PR3_SHIFT)
+#define GPIO_AD_SCR_03_0_PR3_RANGE                      19:19
+#define GPIO_AD_SCR_03_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AD_SCR_03_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AD_SCR_03_0_PR3_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AD_SCR_03_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_PR2_SHIFT)
+#define GPIO_AD_SCR_03_0_PR2_RANGE                      18:18
+#define GPIO_AD_SCR_03_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AD_SCR_03_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AD_SCR_03_0_PR2_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AD_SCR_03_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_PR1_SHIFT)
+#define GPIO_AD_SCR_03_0_PR1_RANGE                      17:17
+#define GPIO_AD_SCR_03_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AD_SCR_03_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AD_SCR_03_0_PR1_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AD_SCR_03_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_PR0_SHIFT)
+#define GPIO_AD_SCR_03_0_PR0_RANGE                      16:16
+#define GPIO_AD_SCR_03_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AD_SCR_03_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AD_SCR_03_0_PR0_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AD_SCR_03_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G7W_SHIFT)
+#define GPIO_AD_SCR_03_0_G7W_RANGE                      15:15
+#define GPIO_AD_SCR_03_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AD_SCR_03_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AD_SCR_03_0_G7W_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AD_SCR_03_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G6W_SHIFT)
+#define GPIO_AD_SCR_03_0_G6W_RANGE                      14:14
+#define GPIO_AD_SCR_03_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AD_SCR_03_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AD_SCR_03_0_G6W_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AD_SCR_03_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G5W_SHIFT)
+#define GPIO_AD_SCR_03_0_G5W_RANGE                      13:13
+#define GPIO_AD_SCR_03_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AD_SCR_03_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AD_SCR_03_0_G5W_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AD_SCR_03_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G4W_SHIFT)
+#define GPIO_AD_SCR_03_0_G4W_RANGE                      12:12
+#define GPIO_AD_SCR_03_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AD_SCR_03_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AD_SCR_03_0_G4W_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AD_SCR_03_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G3W_SHIFT)
+#define GPIO_AD_SCR_03_0_G3W_RANGE                      11:11
+#define GPIO_AD_SCR_03_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AD_SCR_03_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AD_SCR_03_0_G3W_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AD_SCR_03_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G2W_SHIFT)
+#define GPIO_AD_SCR_03_0_G2W_RANGE                      10:10
+#define GPIO_AD_SCR_03_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AD_SCR_03_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AD_SCR_03_0_G2W_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AD_SCR_03_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G1W_SHIFT)
+#define GPIO_AD_SCR_03_0_G1W_RANGE                      9:9
+#define GPIO_AD_SCR_03_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AD_SCR_03_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AD_SCR_03_0_G1W_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AD_SCR_03_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G0W_SHIFT)
+#define GPIO_AD_SCR_03_0_G0W_RANGE                      8:8
+#define GPIO_AD_SCR_03_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AD_SCR_03_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AD_SCR_03_0_G0W_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AD_SCR_03_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G7R_SHIFT)
+#define GPIO_AD_SCR_03_0_G7R_RANGE                      7:7
+#define GPIO_AD_SCR_03_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AD_SCR_03_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AD_SCR_03_0_G7R_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AD_SCR_03_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G6R_SHIFT)
+#define GPIO_AD_SCR_03_0_G6R_RANGE                      6:6
+#define GPIO_AD_SCR_03_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AD_SCR_03_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AD_SCR_03_0_G6R_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AD_SCR_03_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G5R_SHIFT)
+#define GPIO_AD_SCR_03_0_G5R_RANGE                      5:5
+#define GPIO_AD_SCR_03_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AD_SCR_03_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AD_SCR_03_0_G5R_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AD_SCR_03_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G4R_SHIFT)
+#define GPIO_AD_SCR_03_0_G4R_RANGE                      4:4
+#define GPIO_AD_SCR_03_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AD_SCR_03_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AD_SCR_03_0_G4R_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AD_SCR_03_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G3R_SHIFT)
+#define GPIO_AD_SCR_03_0_G3R_RANGE                      3:3
+#define GPIO_AD_SCR_03_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AD_SCR_03_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AD_SCR_03_0_G3R_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AD_SCR_03_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G2R_SHIFT)
+#define GPIO_AD_SCR_03_0_G2R_RANGE                      2:2
+#define GPIO_AD_SCR_03_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AD_SCR_03_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AD_SCR_03_0_G2R_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AD_SCR_03_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G1R_SHIFT)
+#define GPIO_AD_SCR_03_0_G1R_RANGE                      1:1
+#define GPIO_AD_SCR_03_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AD_SCR_03_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AD_SCR_03_0_G1R_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AD_SCR_03_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AD_SCR_03_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_SCR_03_0_G0R_SHIFT)
+#define GPIO_AD_SCR_03_0_G0R_RANGE                      0:0
+#define GPIO_AD_SCR_03_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AD_SCR_03_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AD_SCR_03_0_G0R_WOFFSET                    0x0
+#define GPIO_AD_SCR_03_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_SCR_03_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AD_SCR_03_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xa0
+
+// Reserved address 0xa4
+
+// Reserved address 0xa8
+
+// Reserved address 0xac
+
+// Reserved address 0xb0
+
+// Reserved address 0xb4
+
+// Reserved address 0xb8
+
+// Reserved address 0xbc
+
+// Register GPIO_B_VM_00_0
+#define GPIO_B_VM_00_0                  MK_ADDR_CONST(0xc0)
+#define GPIO_B_VM_00_0_SECURE                   0x0
+#define GPIO_B_VM_00_0_DUAL                     0x0
+#define GPIO_B_VM_00_0_SCR                      GPIO_CTL0_VM_SCR_0
+#define GPIO_B_VM_00_0_SCRREG                   GPIO_CTL0_VM_SCR_0
+#define GPIO_B_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_B_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_B_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_B_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_B_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_B_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_B_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM1_SHIFT)
+#define GPIO_B_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_B_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_B_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_B_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_B_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_B_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_B_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_B_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_B_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM2_SHIFT)
+#define GPIO_B_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_B_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_B_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_B_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_B_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_B_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_B_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_B_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_B_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM3_SHIFT)
+#define GPIO_B_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_B_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_B_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_B_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_B_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_B_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_B_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_B_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_B_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM4_SHIFT)
+#define GPIO_B_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_B_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_B_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_B_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_B_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_B_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_B_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_B_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_B_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM5_SHIFT)
+#define GPIO_B_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_B_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_B_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_B_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_B_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_B_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_B_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_B_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_B_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM6_SHIFT)
+#define GPIO_B_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_B_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_B_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_B_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_B_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_B_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_B_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_B_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_B_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM7_SHIFT)
+#define GPIO_B_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_B_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_B_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_B_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_B_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_B_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_B_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_B_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_B_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_B_VM_00_0_VM8_SHIFT)
+#define GPIO_B_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_B_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_B_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_B_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_B_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_B_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_B_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_B_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_SCR_00_0
+#define GPIO_B_SCR_00_0                 MK_ADDR_CONST(0xc4)
+#define GPIO_B_SCR_00_0_SECURE                  0x0
+#define GPIO_B_SCR_00_0_DUAL                    0x0
+#define GPIO_B_SCR_00_0_SCR                     0
+#define GPIO_B_SCR_00_0_SCRREG                  0
+#define GPIO_B_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_B_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_B_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_B_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_B_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_B_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_B_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_B_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_B_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_B_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_B_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_B_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_B_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_B_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_B_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_B_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_B_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_B_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_B_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_B_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_B_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_B_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_B_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_B_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_B_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_B_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_B_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_B_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_B_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_B_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_B_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_B_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR7_SHIFT)
+#define GPIO_B_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_B_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_B_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_B_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_B_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR6_SHIFT)
+#define GPIO_B_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_B_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_B_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_B_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_B_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR5_SHIFT)
+#define GPIO_B_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_B_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_B_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_B_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_B_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR4_SHIFT)
+#define GPIO_B_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_B_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_B_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_B_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_B_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR3_SHIFT)
+#define GPIO_B_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_B_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_B_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_B_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_B_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR2_SHIFT)
+#define GPIO_B_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_B_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_B_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_B_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_B_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR1_SHIFT)
+#define GPIO_B_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_B_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_B_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_B_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_B_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_PR0_SHIFT)
+#define GPIO_B_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_B_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_B_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_B_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_B_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G7W_SHIFT)
+#define GPIO_B_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_B_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_B_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_B_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_B_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G6W_SHIFT)
+#define GPIO_B_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_B_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_B_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_B_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_B_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G5W_SHIFT)
+#define GPIO_B_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_B_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_B_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_B_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_B_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G4W_SHIFT)
+#define GPIO_B_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_B_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_B_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_B_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_B_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G3W_SHIFT)
+#define GPIO_B_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_B_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_B_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_B_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_B_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G2W_SHIFT)
+#define GPIO_B_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_B_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_B_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_B_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_B_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G1W_SHIFT)
+#define GPIO_B_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_B_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_B_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_B_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_B_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G0W_SHIFT)
+#define GPIO_B_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_B_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_B_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_B_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_B_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G7R_SHIFT)
+#define GPIO_B_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_B_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_B_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_B_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_B_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G6R_SHIFT)
+#define GPIO_B_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_B_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_B_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_B_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_B_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G5R_SHIFT)
+#define GPIO_B_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_B_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_B_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_B_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_B_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G4R_SHIFT)
+#define GPIO_B_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_B_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_B_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_B_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_B_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G3R_SHIFT)
+#define GPIO_B_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_B_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_B_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_B_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_B_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G2R_SHIFT)
+#define GPIO_B_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_B_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_B_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_B_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_B_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G1R_SHIFT)
+#define GPIO_B_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_B_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_B_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_B_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_B_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_B_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_SCR_00_0_G0R_SHIFT)
+#define GPIO_B_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_B_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_B_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_B_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_B_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_B_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xc8
+
+// Reserved address 0xcc
+
+// Reserved address 0xd0
+
+// Reserved address 0xd4
+
+// Reserved address 0xd8
+
+// Reserved address 0xdc
+
+// Reserved address 0xe0
+
+// Reserved address 0xe4
+
+// Reserved address 0xe8
+
+// Reserved address 0xec
+
+// Reserved address 0xf0
+
+// Reserved address 0xf4
+
+// Reserved address 0xf8
+
+// Reserved address 0xfc
+
+// Register GPIO_CTL0_VM_SCR_0
+#define GPIO_CTL0_VM_SCR_0                      MK_ADDR_CONST(0x800)
+#define GPIO_CTL0_VM_SCR_0_SECURE                       0x0
+#define GPIO_CTL0_VM_SCR_0_DUAL                         0x0
+#define GPIO_CTL0_VM_SCR_0_SCR                  0
+#define GPIO_CTL0_VM_SCR_0_SCRREG                       0
+#define GPIO_CTL0_VM_SCR_0_WORD_COUNT                   0x1
+#define GPIO_CTL0_VM_SCR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL0_VM_SCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL0_VM_SCR_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL0_VM_SCR_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
+#define GPIO_CTL0_VM_SCR_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_SEC_LCK_RANGE                        29:29
+#define GPIO_CTL0_VM_SCR_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
+#define GPIO_CTL0_VM_SCR_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
+#define GPIO_CTL0_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
+#define GPIO_CTL0_VM_SCR_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
+#define GPIO_CTL0_VM_SCR_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_SEC_WEN_RANGE                        28:28
+#define GPIO_CTL0_VM_SCR_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
+#define GPIO_CTL0_VM_SCR_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
+#define GPIO_CTL0_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
+#define GPIO_CTL0_VM_SCR_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
+#define GPIO_CTL0_VM_SCR_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_SEC_REN_RANGE                        27:27
+#define GPIO_CTL0_VM_SCR_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
+#define GPIO_CTL0_VM_SCR_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
+#define GPIO_CTL0_VM_SCR_0_SEC_REN_WOFFSET                      0x0
+#define GPIO_CTL0_VM_SCR_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
+#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, GPIO_CTL0_VM_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_RANGE                      26:24
+#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
+#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
+#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
+#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
+#define GPIO_CTL0_VM_SCR_0_PR7_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR7_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_PR7_RANGE                    23:23
+#define GPIO_CTL0_VM_SCR_0_PR7_MSB                      MK_SHIFT_CONST(23)
+#define GPIO_CTL0_VM_SCR_0_PR7_LSB                      MK_SHIFT_CONST(23)
+#define GPIO_CTL0_VM_SCR_0_PR7_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
+#define GPIO_CTL0_VM_SCR_0_PR6_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR6_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_PR6_RANGE                    22:22
+#define GPIO_CTL0_VM_SCR_0_PR6_MSB                      MK_SHIFT_CONST(22)
+#define GPIO_CTL0_VM_SCR_0_PR6_LSB                      MK_SHIFT_CONST(22)
+#define GPIO_CTL0_VM_SCR_0_PR6_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
+#define GPIO_CTL0_VM_SCR_0_PR5_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR5_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_PR5_RANGE                    21:21
+#define GPIO_CTL0_VM_SCR_0_PR5_MSB                      MK_SHIFT_CONST(21)
+#define GPIO_CTL0_VM_SCR_0_PR5_LSB                      MK_SHIFT_CONST(21)
+#define GPIO_CTL0_VM_SCR_0_PR5_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
+#define GPIO_CTL0_VM_SCR_0_PR4_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR4_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_PR4_RANGE                    20:20
+#define GPIO_CTL0_VM_SCR_0_PR4_MSB                      MK_SHIFT_CONST(20)
+#define GPIO_CTL0_VM_SCR_0_PR4_LSB                      MK_SHIFT_CONST(20)
+#define GPIO_CTL0_VM_SCR_0_PR4_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
+#define GPIO_CTL0_VM_SCR_0_PR3_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR3_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_PR3_RANGE                    19:19
+#define GPIO_CTL0_VM_SCR_0_PR3_MSB                      MK_SHIFT_CONST(19)
+#define GPIO_CTL0_VM_SCR_0_PR3_LSB                      MK_SHIFT_CONST(19)
+#define GPIO_CTL0_VM_SCR_0_PR3_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
+#define GPIO_CTL0_VM_SCR_0_PR2_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR2_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_PR2_RANGE                    18:18
+#define GPIO_CTL0_VM_SCR_0_PR2_MSB                      MK_SHIFT_CONST(18)
+#define GPIO_CTL0_VM_SCR_0_PR2_LSB                      MK_SHIFT_CONST(18)
+#define GPIO_CTL0_VM_SCR_0_PR2_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
+#define GPIO_CTL0_VM_SCR_0_PR1_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR1_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_PR1_RANGE                    17:17
+#define GPIO_CTL0_VM_SCR_0_PR1_MSB                      MK_SHIFT_CONST(17)
+#define GPIO_CTL0_VM_SCR_0_PR1_LSB                      MK_SHIFT_CONST(17)
+#define GPIO_CTL0_VM_SCR_0_PR1_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
+#define GPIO_CTL0_VM_SCR_0_PR0_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_PR0_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_PR0_RANGE                    16:16
+#define GPIO_CTL0_VM_SCR_0_PR0_MSB                      MK_SHIFT_CONST(16)
+#define GPIO_CTL0_VM_SCR_0_PR0_LSB                      MK_SHIFT_CONST(16)
+#define GPIO_CTL0_VM_SCR_0_PR0_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
+#define GPIO_CTL0_VM_SCR_0_G7W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G7W_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_G7W_RANGE                    15:15
+#define GPIO_CTL0_VM_SCR_0_G7W_MSB                      MK_SHIFT_CONST(15)
+#define GPIO_CTL0_VM_SCR_0_G7W_LSB                      MK_SHIFT_CONST(15)
+#define GPIO_CTL0_VM_SCR_0_G7W_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
+#define GPIO_CTL0_VM_SCR_0_G6W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G6W_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_G6W_RANGE                    14:14
+#define GPIO_CTL0_VM_SCR_0_G6W_MSB                      MK_SHIFT_CONST(14)
+#define GPIO_CTL0_VM_SCR_0_G6W_LSB                      MK_SHIFT_CONST(14)
+#define GPIO_CTL0_VM_SCR_0_G6W_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
+#define GPIO_CTL0_VM_SCR_0_G5W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G5W_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_G5W_RANGE                    13:13
+#define GPIO_CTL0_VM_SCR_0_G5W_MSB                      MK_SHIFT_CONST(13)
+#define GPIO_CTL0_VM_SCR_0_G5W_LSB                      MK_SHIFT_CONST(13)
+#define GPIO_CTL0_VM_SCR_0_G5W_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
+#define GPIO_CTL0_VM_SCR_0_G4W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G4W_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_G4W_RANGE                    12:12
+#define GPIO_CTL0_VM_SCR_0_G4W_MSB                      MK_SHIFT_CONST(12)
+#define GPIO_CTL0_VM_SCR_0_G4W_LSB                      MK_SHIFT_CONST(12)
+#define GPIO_CTL0_VM_SCR_0_G4W_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
+#define GPIO_CTL0_VM_SCR_0_G3W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G3W_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_G3W_RANGE                    11:11
+#define GPIO_CTL0_VM_SCR_0_G3W_MSB                      MK_SHIFT_CONST(11)
+#define GPIO_CTL0_VM_SCR_0_G3W_LSB                      MK_SHIFT_CONST(11)
+#define GPIO_CTL0_VM_SCR_0_G3W_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
+#define GPIO_CTL0_VM_SCR_0_G2W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G2W_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_G2W_RANGE                    10:10
+#define GPIO_CTL0_VM_SCR_0_G2W_MSB                      MK_SHIFT_CONST(10)
+#define GPIO_CTL0_VM_SCR_0_G2W_LSB                      MK_SHIFT_CONST(10)
+#define GPIO_CTL0_VM_SCR_0_G2W_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
+#define GPIO_CTL0_VM_SCR_0_G1W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G1W_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_G1W_RANGE                    9:9
+#define GPIO_CTL0_VM_SCR_0_G1W_MSB                      MK_SHIFT_CONST(9)
+#define GPIO_CTL0_VM_SCR_0_G1W_LSB                      MK_SHIFT_CONST(9)
+#define GPIO_CTL0_VM_SCR_0_G1W_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
+#define GPIO_CTL0_VM_SCR_0_G0W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G0W_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_G0W_RANGE                    8:8
+#define GPIO_CTL0_VM_SCR_0_G0W_MSB                      MK_SHIFT_CONST(8)
+#define GPIO_CTL0_VM_SCR_0_G0W_LSB                      MK_SHIFT_CONST(8)
+#define GPIO_CTL0_VM_SCR_0_G0W_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
+#define GPIO_CTL0_VM_SCR_0_G7R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G7R_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_G7R_RANGE                    7:7
+#define GPIO_CTL0_VM_SCR_0_G7R_MSB                      MK_SHIFT_CONST(7)
+#define GPIO_CTL0_VM_SCR_0_G7R_LSB                      MK_SHIFT_CONST(7)
+#define GPIO_CTL0_VM_SCR_0_G7R_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
+#define GPIO_CTL0_VM_SCR_0_G6R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G6R_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_G6R_RANGE                    6:6
+#define GPIO_CTL0_VM_SCR_0_G6R_MSB                      MK_SHIFT_CONST(6)
+#define GPIO_CTL0_VM_SCR_0_G6R_LSB                      MK_SHIFT_CONST(6)
+#define GPIO_CTL0_VM_SCR_0_G6R_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
+#define GPIO_CTL0_VM_SCR_0_G5R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G5R_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_G5R_RANGE                    5:5
+#define GPIO_CTL0_VM_SCR_0_G5R_MSB                      MK_SHIFT_CONST(5)
+#define GPIO_CTL0_VM_SCR_0_G5R_LSB                      MK_SHIFT_CONST(5)
+#define GPIO_CTL0_VM_SCR_0_G5R_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
+#define GPIO_CTL0_VM_SCR_0_G4R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G4R_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_G4R_RANGE                    4:4
+#define GPIO_CTL0_VM_SCR_0_G4R_MSB                      MK_SHIFT_CONST(4)
+#define GPIO_CTL0_VM_SCR_0_G4R_LSB                      MK_SHIFT_CONST(4)
+#define GPIO_CTL0_VM_SCR_0_G4R_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
+#define GPIO_CTL0_VM_SCR_0_G3R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G3R_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_G3R_RANGE                    3:3
+#define GPIO_CTL0_VM_SCR_0_G3R_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_CTL0_VM_SCR_0_G3R_LSB                      MK_SHIFT_CONST(3)
+#define GPIO_CTL0_VM_SCR_0_G3R_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_CTL0_VM_SCR_0_G2R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G2R_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_G2R_RANGE                    2:2
+#define GPIO_CTL0_VM_SCR_0_G2R_MSB                      MK_SHIFT_CONST(2)
+#define GPIO_CTL0_VM_SCR_0_G2R_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_CTL0_VM_SCR_0_G2R_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
+#define GPIO_CTL0_VM_SCR_0_G1R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G1R_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_G1R_RANGE                    1:1
+#define GPIO_CTL0_VM_SCR_0_G1R_MSB                      MK_SHIFT_CONST(1)
+#define GPIO_CTL0_VM_SCR_0_G1R_LSB                      MK_SHIFT_CONST(1)
+#define GPIO_CTL0_VM_SCR_0_G1R_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_VM_SCR_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CTL0_VM_SCR_0_G0R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL0_VM_SCR_0_G0R_SHIFT)
+#define GPIO_CTL0_VM_SCR_0_G0R_RANGE                    0:0
+#define GPIO_CTL0_VM_SCR_0_G0R_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CTL0_VM_SCR_0_G0R_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CTL0_VM_SCR_0_G0R_WOFFSET                  0x0
+#define GPIO_CTL0_VM_SCR_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL0_VM_SCR_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0                     MK_ADDR_CONST(0x804)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SCRREG                      0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_MSB                     MK_SHIFT_CONST(23)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_LSB                     MK_SHIFT_CONST(23)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_MSB                     MK_SHIFT_CONST(22)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_LSB                     MK_SHIFT_CONST(22)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_MSB                     MK_SHIFT_CONST(21)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_LSB                     MK_SHIFT_CONST(21)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_MSB                     MK_SHIFT_CONST(20)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_LSB                     MK_SHIFT_CONST(20)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_MSB                     MK_SHIFT_CONST(19)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_LSB                     MK_SHIFT_CONST(19)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_MSB                     MK_SHIFT_CONST(18)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_LSB                     MK_SHIFT_CONST(18)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_MSB                     MK_SHIFT_CONST(17)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_LSB                     MK_SHIFT_CONST(17)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_MSB                     MK_SHIFT_CONST(16)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_LSB                     MK_SHIFT_CONST(16)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_MSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_LSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_MSB                     MK_SHIFT_CONST(14)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_LSB                     MK_SHIFT_CONST(14)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_MSB                     MK_SHIFT_CONST(13)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_LSB                     MK_SHIFT_CONST(13)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_MSB                     MK_SHIFT_CONST(12)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_LSB                     MK_SHIFT_CONST(12)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_MSB                     MK_SHIFT_CONST(11)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_LSB                     MK_SHIFT_CONST(11)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_MSB                     MK_SHIFT_CONST(10)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_LSB                     MK_SHIFT_CONST(10)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_MSB                     MK_SHIFT_CONST(9)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_LSB                     MK_SHIFT_CONST(9)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_MSB                     MK_SHIFT_CONST(8)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_LSB                     MK_SHIFT_CONST(8)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_MSB                     MK_SHIFT_CONST(6)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_LSB                     MK_SHIFT_CONST(6)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_LSB                     MK_SHIFT_CONST(5)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_LSB                     MK_SHIFT_CONST(3)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_MSB                     MK_SHIFT_CONST(2)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_MSB                     MK_SHIFT_CONST(1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_LSB                     MK_SHIFT_CONST(1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_MSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL0_INTERRUPT_STATUS_VM_0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0                 MK_ADDR_CONST(0x808)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SECURE                  0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_DUAL                    0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SCRREG                  GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  MK_FIELD_CONST(0xff, GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL0_SCR_0
+#define GPIO_CTL0_SCR_0                 MK_ADDR_CONST(0x80c)
+#define GPIO_CTL0_SCR_0_SECURE                  0x0
+#define GPIO_CTL0_SCR_0_DUAL                    0x0
+#define GPIO_CTL0_SCR_0_SCR                     0
+#define GPIO_CTL0_SCR_0_SCRREG                  0
+#define GPIO_CTL0_SCR_0_WORD_COUNT                      0x1
+#define GPIO_CTL0_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL0_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL0_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL0_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_CTL0_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL0_SCR_0_SEC_LCK_RANGE                   29:29
+#define GPIO_CTL0_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_CTL0_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_CTL0_SCR_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_CTL0_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_CTL0_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL0_SCR_0_SEC_WEN_RANGE                   28:28
+#define GPIO_CTL0_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_CTL0_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_CTL0_SCR_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_CTL0_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_CTL0_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL0_SCR_0_SEC_REN_RANGE                   27:27
+#define GPIO_CTL0_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_CTL0_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_CTL0_SCR_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_CTL0_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_CTL0_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_CTL0_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL0_SCR_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_CTL0_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_CTL0_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_CTL0_SCR_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_CTL0_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_CTL0_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_CTL0_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR7_SHIFT)
+#define GPIO_CTL0_SCR_0_PR7_RANGE                       23:23
+#define GPIO_CTL0_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_CTL0_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_CTL0_SCR_0_PR7_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_CTL0_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR6_SHIFT)
+#define GPIO_CTL0_SCR_0_PR6_RANGE                       22:22
+#define GPIO_CTL0_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_CTL0_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_CTL0_SCR_0_PR6_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_CTL0_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR5_SHIFT)
+#define GPIO_CTL0_SCR_0_PR5_RANGE                       21:21
+#define GPIO_CTL0_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_CTL0_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_CTL0_SCR_0_PR5_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_CTL0_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR4_SHIFT)
+#define GPIO_CTL0_SCR_0_PR4_RANGE                       20:20
+#define GPIO_CTL0_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_CTL0_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_CTL0_SCR_0_PR4_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_CTL0_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR3_SHIFT)
+#define GPIO_CTL0_SCR_0_PR3_RANGE                       19:19
+#define GPIO_CTL0_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_CTL0_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_CTL0_SCR_0_PR3_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_CTL0_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR2_SHIFT)
+#define GPIO_CTL0_SCR_0_PR2_RANGE                       18:18
+#define GPIO_CTL0_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_CTL0_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_CTL0_SCR_0_PR2_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_CTL0_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR1_SHIFT)
+#define GPIO_CTL0_SCR_0_PR1_RANGE                       17:17
+#define GPIO_CTL0_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_CTL0_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_CTL0_SCR_0_PR1_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_CTL0_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_PR0_SHIFT)
+#define GPIO_CTL0_SCR_0_PR0_RANGE                       16:16
+#define GPIO_CTL0_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_CTL0_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_CTL0_SCR_0_PR0_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_CTL0_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G7W_SHIFT)
+#define GPIO_CTL0_SCR_0_G7W_RANGE                       15:15
+#define GPIO_CTL0_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_CTL0_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_CTL0_SCR_0_G7W_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_CTL0_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G6W_SHIFT)
+#define GPIO_CTL0_SCR_0_G6W_RANGE                       14:14
+#define GPIO_CTL0_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_CTL0_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_CTL0_SCR_0_G6W_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_CTL0_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G5W_SHIFT)
+#define GPIO_CTL0_SCR_0_G5W_RANGE                       13:13
+#define GPIO_CTL0_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_CTL0_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_CTL0_SCR_0_G5W_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_CTL0_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G4W_SHIFT)
+#define GPIO_CTL0_SCR_0_G4W_RANGE                       12:12
+#define GPIO_CTL0_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_CTL0_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_CTL0_SCR_0_G4W_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_CTL0_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G3W_SHIFT)
+#define GPIO_CTL0_SCR_0_G3W_RANGE                       11:11
+#define GPIO_CTL0_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_CTL0_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_CTL0_SCR_0_G3W_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_CTL0_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G2W_SHIFT)
+#define GPIO_CTL0_SCR_0_G2W_RANGE                       10:10
+#define GPIO_CTL0_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_CTL0_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_CTL0_SCR_0_G2W_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_CTL0_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G1W_SHIFT)
+#define GPIO_CTL0_SCR_0_G1W_RANGE                       9:9
+#define GPIO_CTL0_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_CTL0_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_CTL0_SCR_0_G1W_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_CTL0_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G0W_SHIFT)
+#define GPIO_CTL0_SCR_0_G0W_RANGE                       8:8
+#define GPIO_CTL0_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_CTL0_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_CTL0_SCR_0_G0W_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_CTL0_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G7R_SHIFT)
+#define GPIO_CTL0_SCR_0_G7R_RANGE                       7:7
+#define GPIO_CTL0_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_CTL0_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_CTL0_SCR_0_G7R_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_CTL0_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G6R_SHIFT)
+#define GPIO_CTL0_SCR_0_G6R_RANGE                       6:6
+#define GPIO_CTL0_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_CTL0_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_CTL0_SCR_0_G6R_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_CTL0_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G5R_SHIFT)
+#define GPIO_CTL0_SCR_0_G5R_RANGE                       5:5
+#define GPIO_CTL0_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_CTL0_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_CTL0_SCR_0_G5R_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_CTL0_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G4R_SHIFT)
+#define GPIO_CTL0_SCR_0_G4R_RANGE                       4:4
+#define GPIO_CTL0_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_CTL0_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_CTL0_SCR_0_G4R_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_CTL0_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G3R_SHIFT)
+#define GPIO_CTL0_SCR_0_G3R_RANGE                       3:3
+#define GPIO_CTL0_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_CTL0_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_CTL0_SCR_0_G3R_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_CTL0_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G2R_SHIFT)
+#define GPIO_CTL0_SCR_0_G2R_RANGE                       2:2
+#define GPIO_CTL0_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_CTL0_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_CTL0_SCR_0_G2R_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_CTL0_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G1R_SHIFT)
+#define GPIO_CTL0_SCR_0_G1R_RANGE                       1:1
+#define GPIO_CTL0_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_CTL0_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_CTL0_SCR_0_G1R_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL0_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_CTL0_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL0_SCR_0_G0R_SHIFT)
+#define GPIO_CTL0_SCR_0_G0R_RANGE                       0:0
+#define GPIO_CTL0_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_CTL0_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_CTL0_SCR_0_G0R_WOFFSET                     0x0
+#define GPIO_CTL0_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL0_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL0_ICG_EN_OVERRIDE_0
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0                     MK_ADDR_CONST(0x810)
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SECURE                      0x0
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_DUAL                        0x0
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL0_SCR_0
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SCRREG                      GPIO_CTL0_SCR_0
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CTL0_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INT0_ROUTE_MAPPING_0
+#define GPIO_A_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x814)
+#define GPIO_A_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_A_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_A_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
+#define GPIO_A_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
+#define GPIO_A_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_A_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_A_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_A_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INT1_ROUTE_MAPPING_0
+#define GPIO_A_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x818)
+#define GPIO_A_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_A_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_A_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
+#define GPIO_A_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
+#define GPIO_A_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_A_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_A_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_A_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INT2_ROUTE_MAPPING_0
+#define GPIO_A_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x81c)
+#define GPIO_A_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_A_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_A_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
+#define GPIO_A_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
+#define GPIO_A_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_A_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_A_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_A_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INT3_ROUTE_MAPPING_0
+#define GPIO_A_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x820)
+#define GPIO_A_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_A_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_A_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
+#define GPIO_A_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
+#define GPIO_A_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_A_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_A_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_A_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INT4_ROUTE_MAPPING_0
+#define GPIO_A_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x824)
+#define GPIO_A_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_A_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_A_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
+#define GPIO_A_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
+#define GPIO_A_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_A_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_A_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_A_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INT5_ROUTE_MAPPING_0
+#define GPIO_A_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x828)
+#define GPIO_A_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_A_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_A_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
+#define GPIO_A_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
+#define GPIO_A_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_A_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_A_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_A_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INT6_ROUTE_MAPPING_0
+#define GPIO_A_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x82c)
+#define GPIO_A_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_A_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_A_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
+#define GPIO_A_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
+#define GPIO_A_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_A_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_A_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_A_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INT7_ROUTE_MAPPING_0
+#define GPIO_A_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x830)
+#define GPIO_A_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_A_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_A_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
+#define GPIO_A_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
+#define GPIO_A_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_A_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_A_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_A_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INT0_ROUTE_MAPPING_0
+#define GPIO_AC_INT0_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x834)
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_RANGE                  7:0
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INT1_ROUTE_MAPPING_0
+#define GPIO_AC_INT1_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x838)
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_RANGE                  7:0
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INT2_ROUTE_MAPPING_0
+#define GPIO_AC_INT2_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x83c)
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_RANGE                  7:0
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INT3_ROUTE_MAPPING_0
+#define GPIO_AC_INT3_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x840)
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_RANGE                  7:0
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INT4_ROUTE_MAPPING_0
+#define GPIO_AC_INT4_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x844)
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_RANGE                  7:0
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INT5_ROUTE_MAPPING_0
+#define GPIO_AC_INT5_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x848)
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_RANGE                  7:0
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INT6_ROUTE_MAPPING_0
+#define GPIO_AC_INT6_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x84c)
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_RANGE                  7:0
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INT7_ROUTE_MAPPING_0
+#define GPIO_AC_INT7_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x850)
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_RANGE                  7:0
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INT0_ROUTE_MAPPING_0
+#define GPIO_AD_INT0_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x854)
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_RANGE                  3:0
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AD_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INT1_ROUTE_MAPPING_0
+#define GPIO_AD_INT1_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x858)
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_RANGE                  3:0
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AD_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INT2_ROUTE_MAPPING_0
+#define GPIO_AD_INT2_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x85c)
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_RANGE                  3:0
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AD_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INT3_ROUTE_MAPPING_0
+#define GPIO_AD_INT3_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x860)
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_RANGE                  3:0
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AD_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INT4_ROUTE_MAPPING_0
+#define GPIO_AD_INT4_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x864)
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_RANGE                  3:0
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AD_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INT5_ROUTE_MAPPING_0
+#define GPIO_AD_INT5_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x868)
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_RANGE                  3:0
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AD_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INT6_ROUTE_MAPPING_0
+#define GPIO_AD_INT6_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x86c)
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_RANGE                  3:0
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AD_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INT7_ROUTE_MAPPING_0
+#define GPIO_AD_INT7_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x870)
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_SCR                        GPIO_CTL0_SCR_0
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL0_SCR_0
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_RANGE                  3:0
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AD_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_INT0_ROUTE_MAPPING_0
+#define GPIO_B_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x874)
+#define GPIO_B_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_B_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_B_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
+#define GPIO_B_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
+#define GPIO_B_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_B_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_B_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_B_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_B_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_RANGE                   0:0
+#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(0)
+#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_B_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_INT1_ROUTE_MAPPING_0
+#define GPIO_B_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x878)
+#define GPIO_B_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_B_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_B_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
+#define GPIO_B_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
+#define GPIO_B_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_B_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_B_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_B_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_B_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_RANGE                   0:0
+#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(0)
+#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_B_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_INT2_ROUTE_MAPPING_0
+#define GPIO_B_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x87c)
+#define GPIO_B_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_B_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_B_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
+#define GPIO_B_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
+#define GPIO_B_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_B_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_B_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_B_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_B_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_RANGE                   0:0
+#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(0)
+#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_B_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_INT3_ROUTE_MAPPING_0
+#define GPIO_B_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x880)
+#define GPIO_B_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_B_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_B_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
+#define GPIO_B_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
+#define GPIO_B_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_B_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_B_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_B_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_B_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_RANGE                   0:0
+#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(0)
+#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_B_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_INT4_ROUTE_MAPPING_0
+#define GPIO_B_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x884)
+#define GPIO_B_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_B_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_B_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
+#define GPIO_B_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
+#define GPIO_B_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_B_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_B_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_B_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_B_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_RANGE                   0:0
+#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(0)
+#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_B_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_INT5_ROUTE_MAPPING_0
+#define GPIO_B_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x888)
+#define GPIO_B_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_B_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_B_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
+#define GPIO_B_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
+#define GPIO_B_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_B_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_B_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_B_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_B_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_RANGE                   0:0
+#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(0)
+#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_B_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_INT6_ROUTE_MAPPING_0
+#define GPIO_B_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x88c)
+#define GPIO_B_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_B_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_B_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
+#define GPIO_B_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
+#define GPIO_B_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_B_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_B_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_B_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_B_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_RANGE                   0:0
+#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(0)
+#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_B_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_INT7_ROUTE_MAPPING_0
+#define GPIO_B_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x890)
+#define GPIO_B_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_B_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_B_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL0_SCR_0
+#define GPIO_B_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL0_SCR_0
+#define GPIO_B_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_B_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_B_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_B_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_B_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_RANGE                   0:0
+#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(0)
+#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_B_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL0_SPARE_0
+#define GPIO_CTL0_SPARE_0                       MK_ADDR_CONST(0x894)
+#define GPIO_CTL0_SPARE_0_SECURE                        0x0
+#define GPIO_CTL0_SPARE_0_DUAL                  0x0
+#define GPIO_CTL0_SPARE_0_SCR                   0
+#define GPIO_CTL0_SPARE_0_SCRREG                        0
+#define GPIO_CTL0_SPARE_0_WORD_COUNT                    0x1
+#define GPIO_CTL0_SPARE_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SPARE_0_RESET_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL0_SPARE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SPARE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SPARE_0_READ_MASK                     MK_MASK_CONST(0xffff)
+#define GPIO_CTL0_SPARE_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL0_SPARE_0_SPARE_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_CTL0_SPARE_0_SPARE_FIELD                   MK_FIELD_CONST(0xffff, GPIO_CTL0_SPARE_0_SPARE_SHIFT)
+#define GPIO_CTL0_SPARE_0_SPARE_RANGE                   15:0
+#define GPIO_CTL0_SPARE_0_SPARE_MSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL0_SPARE_0_SPARE_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL0_SPARE_0_SPARE_WOFFSET                 0x0
+#define GPIO_CTL0_SPARE_0_SPARE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SPARE_0_SPARE_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL0_SPARE_0_SPARE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SPARE_0_SPARE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SPARE_0_SPARE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL0_SPARE_0_SPARE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_VM_00_0
+#define GPIO_X_VM_00_0                  MK_ADDR_CONST(0x1000)
+#define GPIO_X_VM_00_0_SECURE                   0x0
+#define GPIO_X_VM_00_0_DUAL                     0x0
+#define GPIO_X_VM_00_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_X_VM_00_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_X_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_X_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_X_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM1_SHIFT)
+#define GPIO_X_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_X_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_X_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_X_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_X_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_X_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM2_SHIFT)
+#define GPIO_X_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_X_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_X_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_X_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_X_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_X_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM3_SHIFT)
+#define GPIO_X_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_X_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_X_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_X_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_X_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_X_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM4_SHIFT)
+#define GPIO_X_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_X_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_X_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_X_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_X_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_X_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM5_SHIFT)
+#define GPIO_X_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_X_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_X_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_X_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_X_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_X_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM6_SHIFT)
+#define GPIO_X_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_X_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_X_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_X_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_X_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_X_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM7_SHIFT)
+#define GPIO_X_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_X_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_X_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_X_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_X_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_X_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_00_0_VM8_SHIFT)
+#define GPIO_X_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_X_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_X_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_X_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_X_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_SCR_00_0
+#define GPIO_X_SCR_00_0                 MK_ADDR_CONST(0x1004)
+#define GPIO_X_SCR_00_0_SECURE                  0x0
+#define GPIO_X_SCR_00_0_DUAL                    0x0
+#define GPIO_X_SCR_00_0_SCR                     0
+#define GPIO_X_SCR_00_0_SCRREG                  0
+#define GPIO_X_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_X_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_X_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_X_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_X_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_X_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_X_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_X_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_X_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_X_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_X_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_X_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_X_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_X_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_X_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_X_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_X_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_X_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_X_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR7_SHIFT)
+#define GPIO_X_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_X_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR6_SHIFT)
+#define GPIO_X_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_X_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR5_SHIFT)
+#define GPIO_X_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_X_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR4_SHIFT)
+#define GPIO_X_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_X_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR3_SHIFT)
+#define GPIO_X_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_X_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR2_SHIFT)
+#define GPIO_X_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_X_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR1_SHIFT)
+#define GPIO_X_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_X_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_PR0_SHIFT)
+#define GPIO_X_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_X_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G7W_SHIFT)
+#define GPIO_X_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_X_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G6W_SHIFT)
+#define GPIO_X_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_X_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G5W_SHIFT)
+#define GPIO_X_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_X_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G4W_SHIFT)
+#define GPIO_X_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_X_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G3W_SHIFT)
+#define GPIO_X_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_X_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G2W_SHIFT)
+#define GPIO_X_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_X_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G1W_SHIFT)
+#define GPIO_X_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_X_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G0W_SHIFT)
+#define GPIO_X_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_X_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G7R_SHIFT)
+#define GPIO_X_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_X_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G6R_SHIFT)
+#define GPIO_X_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_X_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G5R_SHIFT)
+#define GPIO_X_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_X_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G4R_SHIFT)
+#define GPIO_X_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_X_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G3R_SHIFT)
+#define GPIO_X_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_X_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G2R_SHIFT)
+#define GPIO_X_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_X_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G1R_SHIFT)
+#define GPIO_X_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_X_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_00_0_G0R_SHIFT)
+#define GPIO_X_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_X_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_X_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_VM_01_0
+#define GPIO_X_VM_01_0                  MK_ADDR_CONST(0x1008)
+#define GPIO_X_VM_01_0_SECURE                   0x0
+#define GPIO_X_VM_01_0_DUAL                     0x0
+#define GPIO_X_VM_01_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_X_VM_01_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_X_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_X_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_X_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM1_SHIFT)
+#define GPIO_X_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_X_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_X_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_X_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_X_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_X_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM2_SHIFT)
+#define GPIO_X_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_X_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_X_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_X_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_X_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_X_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM3_SHIFT)
+#define GPIO_X_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_X_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_X_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_X_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_X_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_X_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM4_SHIFT)
+#define GPIO_X_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_X_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_X_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_X_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_X_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_X_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM5_SHIFT)
+#define GPIO_X_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_X_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_X_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_X_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_X_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_X_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM6_SHIFT)
+#define GPIO_X_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_X_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_X_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_X_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_X_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_X_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM7_SHIFT)
+#define GPIO_X_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_X_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_X_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_X_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_X_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_X_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_01_0_VM8_SHIFT)
+#define GPIO_X_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_X_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_X_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_X_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_X_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_SCR_01_0
+#define GPIO_X_SCR_01_0                 MK_ADDR_CONST(0x100c)
+#define GPIO_X_SCR_01_0_SECURE                  0x0
+#define GPIO_X_SCR_01_0_DUAL                    0x0
+#define GPIO_X_SCR_01_0_SCR                     0
+#define GPIO_X_SCR_01_0_SCRREG                  0
+#define GPIO_X_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_X_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_X_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_X_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_X_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_X_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_X_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_X_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_X_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_X_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_X_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_X_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_X_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_X_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_X_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_X_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_X_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_X_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_X_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR7_SHIFT)
+#define GPIO_X_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_X_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR6_SHIFT)
+#define GPIO_X_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_X_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR5_SHIFT)
+#define GPIO_X_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_X_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR4_SHIFT)
+#define GPIO_X_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_X_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR3_SHIFT)
+#define GPIO_X_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_X_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR2_SHIFT)
+#define GPIO_X_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_X_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR1_SHIFT)
+#define GPIO_X_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_X_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_PR0_SHIFT)
+#define GPIO_X_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_X_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G7W_SHIFT)
+#define GPIO_X_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_X_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G6W_SHIFT)
+#define GPIO_X_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_X_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G5W_SHIFT)
+#define GPIO_X_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_X_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G4W_SHIFT)
+#define GPIO_X_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_X_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G3W_SHIFT)
+#define GPIO_X_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_X_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G2W_SHIFT)
+#define GPIO_X_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_X_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G1W_SHIFT)
+#define GPIO_X_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_X_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G0W_SHIFT)
+#define GPIO_X_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_X_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G7R_SHIFT)
+#define GPIO_X_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_X_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G6R_SHIFT)
+#define GPIO_X_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_X_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G5R_SHIFT)
+#define GPIO_X_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_X_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G4R_SHIFT)
+#define GPIO_X_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_X_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G3R_SHIFT)
+#define GPIO_X_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_X_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G2R_SHIFT)
+#define GPIO_X_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_X_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G1R_SHIFT)
+#define GPIO_X_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_X_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_01_0_G0R_SHIFT)
+#define GPIO_X_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_X_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_X_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_VM_02_0
+#define GPIO_X_VM_02_0                  MK_ADDR_CONST(0x1010)
+#define GPIO_X_VM_02_0_SECURE                   0x0
+#define GPIO_X_VM_02_0_DUAL                     0x0
+#define GPIO_X_VM_02_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_X_VM_02_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_X_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_X_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_X_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM1_SHIFT)
+#define GPIO_X_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_X_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_X_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_X_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_X_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_X_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM2_SHIFT)
+#define GPIO_X_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_X_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_X_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_X_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_X_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_X_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM3_SHIFT)
+#define GPIO_X_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_X_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_X_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_X_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_X_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_X_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM4_SHIFT)
+#define GPIO_X_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_X_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_X_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_X_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_X_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_X_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM5_SHIFT)
+#define GPIO_X_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_X_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_X_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_X_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_X_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_X_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM6_SHIFT)
+#define GPIO_X_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_X_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_X_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_X_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_X_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_X_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM7_SHIFT)
+#define GPIO_X_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_X_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_X_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_X_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_X_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_X_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_02_0_VM8_SHIFT)
+#define GPIO_X_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_X_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_X_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_X_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_X_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_SCR_02_0
+#define GPIO_X_SCR_02_0                 MK_ADDR_CONST(0x1014)
+#define GPIO_X_SCR_02_0_SECURE                  0x0
+#define GPIO_X_SCR_02_0_DUAL                    0x0
+#define GPIO_X_SCR_02_0_SCR                     0
+#define GPIO_X_SCR_02_0_SCRREG                  0
+#define GPIO_X_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_X_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_X_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_X_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_X_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_X_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_X_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_X_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_X_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_X_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_X_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_X_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_X_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_X_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_X_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_X_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_X_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_X_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_X_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR7_SHIFT)
+#define GPIO_X_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_X_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR6_SHIFT)
+#define GPIO_X_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_X_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR5_SHIFT)
+#define GPIO_X_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_X_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR4_SHIFT)
+#define GPIO_X_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_X_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR3_SHIFT)
+#define GPIO_X_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_X_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR2_SHIFT)
+#define GPIO_X_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_X_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR1_SHIFT)
+#define GPIO_X_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_X_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_PR0_SHIFT)
+#define GPIO_X_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_X_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G7W_SHIFT)
+#define GPIO_X_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_X_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G6W_SHIFT)
+#define GPIO_X_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_X_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G5W_SHIFT)
+#define GPIO_X_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_X_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G4W_SHIFT)
+#define GPIO_X_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_X_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G3W_SHIFT)
+#define GPIO_X_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_X_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G2W_SHIFT)
+#define GPIO_X_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_X_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G1W_SHIFT)
+#define GPIO_X_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_X_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G0W_SHIFT)
+#define GPIO_X_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_X_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G7R_SHIFT)
+#define GPIO_X_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_X_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G6R_SHIFT)
+#define GPIO_X_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_X_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G5R_SHIFT)
+#define GPIO_X_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_X_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G4R_SHIFT)
+#define GPIO_X_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_X_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G3R_SHIFT)
+#define GPIO_X_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_X_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G2R_SHIFT)
+#define GPIO_X_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_X_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G1R_SHIFT)
+#define GPIO_X_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_X_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_02_0_G0R_SHIFT)
+#define GPIO_X_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_X_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_X_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_VM_03_0
+#define GPIO_X_VM_03_0                  MK_ADDR_CONST(0x1018)
+#define GPIO_X_VM_03_0_SECURE                   0x0
+#define GPIO_X_VM_03_0_DUAL                     0x0
+#define GPIO_X_VM_03_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_X_VM_03_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_X_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_X_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_X_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM1_SHIFT)
+#define GPIO_X_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_X_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_X_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_X_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_X_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_X_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM2_SHIFT)
+#define GPIO_X_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_X_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_X_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_X_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_X_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_X_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM3_SHIFT)
+#define GPIO_X_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_X_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_X_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_X_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_X_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_X_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM4_SHIFT)
+#define GPIO_X_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_X_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_X_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_X_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_X_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_X_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM5_SHIFT)
+#define GPIO_X_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_X_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_X_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_X_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_X_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_X_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM6_SHIFT)
+#define GPIO_X_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_X_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_X_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_X_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_X_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_X_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM7_SHIFT)
+#define GPIO_X_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_X_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_X_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_X_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_X_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_X_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_03_0_VM8_SHIFT)
+#define GPIO_X_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_X_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_X_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_X_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_X_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_SCR_03_0
+#define GPIO_X_SCR_03_0                 MK_ADDR_CONST(0x101c)
+#define GPIO_X_SCR_03_0_SECURE                  0x0
+#define GPIO_X_SCR_03_0_DUAL                    0x0
+#define GPIO_X_SCR_03_0_SCR                     0
+#define GPIO_X_SCR_03_0_SCRREG                  0
+#define GPIO_X_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_X_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_X_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_X_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_X_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_X_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_X_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_X_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_X_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_X_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_X_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_X_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_X_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_X_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_X_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_X_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_X_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_X_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_X_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR7_SHIFT)
+#define GPIO_X_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_X_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR6_SHIFT)
+#define GPIO_X_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_X_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR5_SHIFT)
+#define GPIO_X_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_X_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR4_SHIFT)
+#define GPIO_X_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_X_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR3_SHIFT)
+#define GPIO_X_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_X_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR2_SHIFT)
+#define GPIO_X_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_X_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR1_SHIFT)
+#define GPIO_X_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_X_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_PR0_SHIFT)
+#define GPIO_X_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_X_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G7W_SHIFT)
+#define GPIO_X_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_X_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G6W_SHIFT)
+#define GPIO_X_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_X_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G5W_SHIFT)
+#define GPIO_X_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_X_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G4W_SHIFT)
+#define GPIO_X_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_X_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G3W_SHIFT)
+#define GPIO_X_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_X_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G2W_SHIFT)
+#define GPIO_X_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_X_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G1W_SHIFT)
+#define GPIO_X_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_X_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G0W_SHIFT)
+#define GPIO_X_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_X_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G7R_SHIFT)
+#define GPIO_X_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_X_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G6R_SHIFT)
+#define GPIO_X_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_X_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G5R_SHIFT)
+#define GPIO_X_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_X_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G4R_SHIFT)
+#define GPIO_X_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_X_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G3R_SHIFT)
+#define GPIO_X_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_X_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G2R_SHIFT)
+#define GPIO_X_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_X_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G1R_SHIFT)
+#define GPIO_X_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_X_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_03_0_G0R_SHIFT)
+#define GPIO_X_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_X_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_X_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_VM_04_0
+#define GPIO_X_VM_04_0                  MK_ADDR_CONST(0x1020)
+#define GPIO_X_VM_04_0_SECURE                   0x0
+#define GPIO_X_VM_04_0_DUAL                     0x0
+#define GPIO_X_VM_04_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_X_VM_04_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_X_VM_04_0_WORD_COUNT                       0x1
+#define GPIO_X_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_X_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM1_SHIFT)
+#define GPIO_X_VM_04_0_VM1_RANGE                        1:0
+#define GPIO_X_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_X_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_X_VM_04_0_VM1_WOFFSET                      0x0
+#define GPIO_X_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_X_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM2_SHIFT)
+#define GPIO_X_VM_04_0_VM2_RANGE                        3:2
+#define GPIO_X_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_X_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_X_VM_04_0_VM2_WOFFSET                      0x0
+#define GPIO_X_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_X_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM3_SHIFT)
+#define GPIO_X_VM_04_0_VM3_RANGE                        5:4
+#define GPIO_X_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_X_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_X_VM_04_0_VM3_WOFFSET                      0x0
+#define GPIO_X_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_X_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM4_SHIFT)
+#define GPIO_X_VM_04_0_VM4_RANGE                        7:6
+#define GPIO_X_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_X_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_X_VM_04_0_VM4_WOFFSET                      0x0
+#define GPIO_X_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_X_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM5_SHIFT)
+#define GPIO_X_VM_04_0_VM5_RANGE                        9:8
+#define GPIO_X_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_X_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_X_VM_04_0_VM5_WOFFSET                      0x0
+#define GPIO_X_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_X_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM6_SHIFT)
+#define GPIO_X_VM_04_0_VM6_RANGE                        11:10
+#define GPIO_X_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_X_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_X_VM_04_0_VM6_WOFFSET                      0x0
+#define GPIO_X_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_X_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM7_SHIFT)
+#define GPIO_X_VM_04_0_VM7_RANGE                        13:12
+#define GPIO_X_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_X_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_X_VM_04_0_VM7_WOFFSET                      0x0
+#define GPIO_X_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_X_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_04_0_VM8_SHIFT)
+#define GPIO_X_VM_04_0_VM8_RANGE                        15:14
+#define GPIO_X_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_X_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_X_VM_04_0_VM8_WOFFSET                      0x0
+#define GPIO_X_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_SCR_04_0
+#define GPIO_X_SCR_04_0                 MK_ADDR_CONST(0x1024)
+#define GPIO_X_SCR_04_0_SECURE                  0x0
+#define GPIO_X_SCR_04_0_DUAL                    0x0
+#define GPIO_X_SCR_04_0_SCR                     0
+#define GPIO_X_SCR_04_0_SCRREG                  0
+#define GPIO_X_SCR_04_0_WORD_COUNT                      0x1
+#define GPIO_X_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_X_SCR_04_0_SEC_LCK_RANGE                   29:29
+#define GPIO_X_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_04_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_X_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_X_SCR_04_0_SEC_WEN_RANGE                   28:28
+#define GPIO_X_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_04_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_X_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_X_SCR_04_0_SEC_REN_RANGE                   27:27
+#define GPIO_X_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_04_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_X_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_X_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_X_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_X_SCR_04_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_X_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_X_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_X_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_X_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_X_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR7_SHIFT)
+#define GPIO_X_SCR_04_0_PR7_RANGE                       23:23
+#define GPIO_X_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_04_0_PR7_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR6_SHIFT)
+#define GPIO_X_SCR_04_0_PR6_RANGE                       22:22
+#define GPIO_X_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_04_0_PR6_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR5_SHIFT)
+#define GPIO_X_SCR_04_0_PR5_RANGE                       21:21
+#define GPIO_X_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_04_0_PR5_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR4_SHIFT)
+#define GPIO_X_SCR_04_0_PR4_RANGE                       20:20
+#define GPIO_X_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_04_0_PR4_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR3_SHIFT)
+#define GPIO_X_SCR_04_0_PR3_RANGE                       19:19
+#define GPIO_X_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_04_0_PR3_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR2_SHIFT)
+#define GPIO_X_SCR_04_0_PR2_RANGE                       18:18
+#define GPIO_X_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_04_0_PR2_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR1_SHIFT)
+#define GPIO_X_SCR_04_0_PR1_RANGE                       17:17
+#define GPIO_X_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_04_0_PR1_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_PR0_SHIFT)
+#define GPIO_X_SCR_04_0_PR0_RANGE                       16:16
+#define GPIO_X_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_04_0_PR0_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G7W_SHIFT)
+#define GPIO_X_SCR_04_0_G7W_RANGE                       15:15
+#define GPIO_X_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_04_0_G7W_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G6W_SHIFT)
+#define GPIO_X_SCR_04_0_G6W_RANGE                       14:14
+#define GPIO_X_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_04_0_G6W_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G5W_SHIFT)
+#define GPIO_X_SCR_04_0_G5W_RANGE                       13:13
+#define GPIO_X_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_04_0_G5W_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G4W_SHIFT)
+#define GPIO_X_SCR_04_0_G4W_RANGE                       12:12
+#define GPIO_X_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_04_0_G4W_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G3W_SHIFT)
+#define GPIO_X_SCR_04_0_G3W_RANGE                       11:11
+#define GPIO_X_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_04_0_G3W_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G2W_SHIFT)
+#define GPIO_X_SCR_04_0_G2W_RANGE                       10:10
+#define GPIO_X_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_04_0_G2W_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G1W_SHIFT)
+#define GPIO_X_SCR_04_0_G1W_RANGE                       9:9
+#define GPIO_X_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_04_0_G1W_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G0W_SHIFT)
+#define GPIO_X_SCR_04_0_G0W_RANGE                       8:8
+#define GPIO_X_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_04_0_G0W_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G7R_SHIFT)
+#define GPIO_X_SCR_04_0_G7R_RANGE                       7:7
+#define GPIO_X_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_04_0_G7R_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G6R_SHIFT)
+#define GPIO_X_SCR_04_0_G6R_RANGE                       6:6
+#define GPIO_X_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_04_0_G6R_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G5R_SHIFT)
+#define GPIO_X_SCR_04_0_G5R_RANGE                       5:5
+#define GPIO_X_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_04_0_G5R_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G4R_SHIFT)
+#define GPIO_X_SCR_04_0_G4R_RANGE                       4:4
+#define GPIO_X_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_04_0_G4R_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G3R_SHIFT)
+#define GPIO_X_SCR_04_0_G3R_RANGE                       3:3
+#define GPIO_X_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_04_0_G3R_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G2R_SHIFT)
+#define GPIO_X_SCR_04_0_G2R_RANGE                       2:2
+#define GPIO_X_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_04_0_G2R_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G1R_SHIFT)
+#define GPIO_X_SCR_04_0_G1R_RANGE                       1:1
+#define GPIO_X_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_04_0_G1R_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_04_0_G0R_SHIFT)
+#define GPIO_X_SCR_04_0_G0R_RANGE                       0:0
+#define GPIO_X_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_04_0_G0R_WOFFSET                     0x0
+#define GPIO_X_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_VM_05_0
+#define GPIO_X_VM_05_0                  MK_ADDR_CONST(0x1028)
+#define GPIO_X_VM_05_0_SECURE                   0x0
+#define GPIO_X_VM_05_0_DUAL                     0x0
+#define GPIO_X_VM_05_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_X_VM_05_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_X_VM_05_0_WORD_COUNT                       0x1
+#define GPIO_X_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_X_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM1_SHIFT)
+#define GPIO_X_VM_05_0_VM1_RANGE                        1:0
+#define GPIO_X_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_X_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_X_VM_05_0_VM1_WOFFSET                      0x0
+#define GPIO_X_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_X_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM2_SHIFT)
+#define GPIO_X_VM_05_0_VM2_RANGE                        3:2
+#define GPIO_X_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_X_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_X_VM_05_0_VM2_WOFFSET                      0x0
+#define GPIO_X_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_X_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM3_SHIFT)
+#define GPIO_X_VM_05_0_VM3_RANGE                        5:4
+#define GPIO_X_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_X_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_X_VM_05_0_VM3_WOFFSET                      0x0
+#define GPIO_X_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_X_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM4_SHIFT)
+#define GPIO_X_VM_05_0_VM4_RANGE                        7:6
+#define GPIO_X_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_X_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_X_VM_05_0_VM4_WOFFSET                      0x0
+#define GPIO_X_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_X_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM5_SHIFT)
+#define GPIO_X_VM_05_0_VM5_RANGE                        9:8
+#define GPIO_X_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_X_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_X_VM_05_0_VM5_WOFFSET                      0x0
+#define GPIO_X_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_X_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM6_SHIFT)
+#define GPIO_X_VM_05_0_VM6_RANGE                        11:10
+#define GPIO_X_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_X_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_X_VM_05_0_VM6_WOFFSET                      0x0
+#define GPIO_X_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_X_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM7_SHIFT)
+#define GPIO_X_VM_05_0_VM7_RANGE                        13:12
+#define GPIO_X_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_X_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_X_VM_05_0_VM7_WOFFSET                      0x0
+#define GPIO_X_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_X_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_05_0_VM8_SHIFT)
+#define GPIO_X_VM_05_0_VM8_RANGE                        15:14
+#define GPIO_X_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_X_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_X_VM_05_0_VM8_WOFFSET                      0x0
+#define GPIO_X_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_SCR_05_0
+#define GPIO_X_SCR_05_0                 MK_ADDR_CONST(0x102c)
+#define GPIO_X_SCR_05_0_SECURE                  0x0
+#define GPIO_X_SCR_05_0_DUAL                    0x0
+#define GPIO_X_SCR_05_0_SCR                     0
+#define GPIO_X_SCR_05_0_SCRREG                  0
+#define GPIO_X_SCR_05_0_WORD_COUNT                      0x1
+#define GPIO_X_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_X_SCR_05_0_SEC_LCK_RANGE                   29:29
+#define GPIO_X_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_05_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_X_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_X_SCR_05_0_SEC_WEN_RANGE                   28:28
+#define GPIO_X_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_05_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_X_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_X_SCR_05_0_SEC_REN_RANGE                   27:27
+#define GPIO_X_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_05_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_X_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_X_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_X_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_X_SCR_05_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_X_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_X_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_X_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_X_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_X_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR7_SHIFT)
+#define GPIO_X_SCR_05_0_PR7_RANGE                       23:23
+#define GPIO_X_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_05_0_PR7_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR6_SHIFT)
+#define GPIO_X_SCR_05_0_PR6_RANGE                       22:22
+#define GPIO_X_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_05_0_PR6_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR5_SHIFT)
+#define GPIO_X_SCR_05_0_PR5_RANGE                       21:21
+#define GPIO_X_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_05_0_PR5_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR4_SHIFT)
+#define GPIO_X_SCR_05_0_PR4_RANGE                       20:20
+#define GPIO_X_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_05_0_PR4_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR3_SHIFT)
+#define GPIO_X_SCR_05_0_PR3_RANGE                       19:19
+#define GPIO_X_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_05_0_PR3_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR2_SHIFT)
+#define GPIO_X_SCR_05_0_PR2_RANGE                       18:18
+#define GPIO_X_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_05_0_PR2_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR1_SHIFT)
+#define GPIO_X_SCR_05_0_PR1_RANGE                       17:17
+#define GPIO_X_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_05_0_PR1_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_PR0_SHIFT)
+#define GPIO_X_SCR_05_0_PR0_RANGE                       16:16
+#define GPIO_X_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_05_0_PR0_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G7W_SHIFT)
+#define GPIO_X_SCR_05_0_G7W_RANGE                       15:15
+#define GPIO_X_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_05_0_G7W_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G6W_SHIFT)
+#define GPIO_X_SCR_05_0_G6W_RANGE                       14:14
+#define GPIO_X_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_05_0_G6W_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G5W_SHIFT)
+#define GPIO_X_SCR_05_0_G5W_RANGE                       13:13
+#define GPIO_X_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_05_0_G5W_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G4W_SHIFT)
+#define GPIO_X_SCR_05_0_G4W_RANGE                       12:12
+#define GPIO_X_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_05_0_G4W_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G3W_SHIFT)
+#define GPIO_X_SCR_05_0_G3W_RANGE                       11:11
+#define GPIO_X_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_05_0_G3W_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G2W_SHIFT)
+#define GPIO_X_SCR_05_0_G2W_RANGE                       10:10
+#define GPIO_X_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_05_0_G2W_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G1W_SHIFT)
+#define GPIO_X_SCR_05_0_G1W_RANGE                       9:9
+#define GPIO_X_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_05_0_G1W_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G0W_SHIFT)
+#define GPIO_X_SCR_05_0_G0W_RANGE                       8:8
+#define GPIO_X_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_05_0_G0W_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G7R_SHIFT)
+#define GPIO_X_SCR_05_0_G7R_RANGE                       7:7
+#define GPIO_X_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_05_0_G7R_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G6R_SHIFT)
+#define GPIO_X_SCR_05_0_G6R_RANGE                       6:6
+#define GPIO_X_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_05_0_G6R_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G5R_SHIFT)
+#define GPIO_X_SCR_05_0_G5R_RANGE                       5:5
+#define GPIO_X_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_05_0_G5R_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G4R_SHIFT)
+#define GPIO_X_SCR_05_0_G4R_RANGE                       4:4
+#define GPIO_X_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_05_0_G4R_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G3R_SHIFT)
+#define GPIO_X_SCR_05_0_G3R_RANGE                       3:3
+#define GPIO_X_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_05_0_G3R_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G2R_SHIFT)
+#define GPIO_X_SCR_05_0_G2R_RANGE                       2:2
+#define GPIO_X_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_05_0_G2R_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G1R_SHIFT)
+#define GPIO_X_SCR_05_0_G1R_RANGE                       1:1
+#define GPIO_X_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_05_0_G1R_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_05_0_G0R_SHIFT)
+#define GPIO_X_SCR_05_0_G0R_RANGE                       0:0
+#define GPIO_X_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_05_0_G0R_WOFFSET                     0x0
+#define GPIO_X_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_VM_06_0
+#define GPIO_X_VM_06_0                  MK_ADDR_CONST(0x1030)
+#define GPIO_X_VM_06_0_SECURE                   0x0
+#define GPIO_X_VM_06_0_DUAL                     0x0
+#define GPIO_X_VM_06_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_X_VM_06_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_X_VM_06_0_WORD_COUNT                       0x1
+#define GPIO_X_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_X_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM1_SHIFT)
+#define GPIO_X_VM_06_0_VM1_RANGE                        1:0
+#define GPIO_X_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_X_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_X_VM_06_0_VM1_WOFFSET                      0x0
+#define GPIO_X_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_X_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM2_SHIFT)
+#define GPIO_X_VM_06_0_VM2_RANGE                        3:2
+#define GPIO_X_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_X_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_X_VM_06_0_VM2_WOFFSET                      0x0
+#define GPIO_X_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_X_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM3_SHIFT)
+#define GPIO_X_VM_06_0_VM3_RANGE                        5:4
+#define GPIO_X_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_X_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_X_VM_06_0_VM3_WOFFSET                      0x0
+#define GPIO_X_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_X_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM4_SHIFT)
+#define GPIO_X_VM_06_0_VM4_RANGE                        7:6
+#define GPIO_X_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_X_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_X_VM_06_0_VM4_WOFFSET                      0x0
+#define GPIO_X_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_X_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM5_SHIFT)
+#define GPIO_X_VM_06_0_VM5_RANGE                        9:8
+#define GPIO_X_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_X_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_X_VM_06_0_VM5_WOFFSET                      0x0
+#define GPIO_X_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_X_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM6_SHIFT)
+#define GPIO_X_VM_06_0_VM6_RANGE                        11:10
+#define GPIO_X_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_X_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_X_VM_06_0_VM6_WOFFSET                      0x0
+#define GPIO_X_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_X_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM7_SHIFT)
+#define GPIO_X_VM_06_0_VM7_RANGE                        13:12
+#define GPIO_X_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_X_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_X_VM_06_0_VM7_WOFFSET                      0x0
+#define GPIO_X_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_X_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_06_0_VM8_SHIFT)
+#define GPIO_X_VM_06_0_VM8_RANGE                        15:14
+#define GPIO_X_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_X_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_X_VM_06_0_VM8_WOFFSET                      0x0
+#define GPIO_X_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_SCR_06_0
+#define GPIO_X_SCR_06_0                 MK_ADDR_CONST(0x1034)
+#define GPIO_X_SCR_06_0_SECURE                  0x0
+#define GPIO_X_SCR_06_0_DUAL                    0x0
+#define GPIO_X_SCR_06_0_SCR                     0
+#define GPIO_X_SCR_06_0_SCRREG                  0
+#define GPIO_X_SCR_06_0_WORD_COUNT                      0x1
+#define GPIO_X_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_SEC_LCK_SHIFT)
+#define GPIO_X_SCR_06_0_SEC_LCK_RANGE                   29:29
+#define GPIO_X_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_06_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_X_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_SEC_WEN_SHIFT)
+#define GPIO_X_SCR_06_0_SEC_WEN_RANGE                   28:28
+#define GPIO_X_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_06_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_X_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_SEC_REN_SHIFT)
+#define GPIO_X_SCR_06_0_SEC_REN_RANGE                   27:27
+#define GPIO_X_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_06_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_X_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_X_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_X_SCR_06_0_SEC_OWNER_SHIFT)
+#define GPIO_X_SCR_06_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_X_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_X_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_X_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_X_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_X_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR7_SHIFT)
+#define GPIO_X_SCR_06_0_PR7_RANGE                       23:23
+#define GPIO_X_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_06_0_PR7_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR6_SHIFT)
+#define GPIO_X_SCR_06_0_PR6_RANGE                       22:22
+#define GPIO_X_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_06_0_PR6_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR5_SHIFT)
+#define GPIO_X_SCR_06_0_PR5_RANGE                       21:21
+#define GPIO_X_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_06_0_PR5_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR4_SHIFT)
+#define GPIO_X_SCR_06_0_PR4_RANGE                       20:20
+#define GPIO_X_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_06_0_PR4_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR3_SHIFT)
+#define GPIO_X_SCR_06_0_PR3_RANGE                       19:19
+#define GPIO_X_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_06_0_PR3_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR2_SHIFT)
+#define GPIO_X_SCR_06_0_PR2_RANGE                       18:18
+#define GPIO_X_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_06_0_PR2_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR1_SHIFT)
+#define GPIO_X_SCR_06_0_PR1_RANGE                       17:17
+#define GPIO_X_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_06_0_PR1_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_PR0_SHIFT)
+#define GPIO_X_SCR_06_0_PR0_RANGE                       16:16
+#define GPIO_X_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_06_0_PR0_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G7W_SHIFT)
+#define GPIO_X_SCR_06_0_G7W_RANGE                       15:15
+#define GPIO_X_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_06_0_G7W_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G6W_SHIFT)
+#define GPIO_X_SCR_06_0_G6W_RANGE                       14:14
+#define GPIO_X_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_06_0_G6W_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G5W_SHIFT)
+#define GPIO_X_SCR_06_0_G5W_RANGE                       13:13
+#define GPIO_X_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_06_0_G5W_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G4W_SHIFT)
+#define GPIO_X_SCR_06_0_G4W_RANGE                       12:12
+#define GPIO_X_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_06_0_G4W_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G3W_SHIFT)
+#define GPIO_X_SCR_06_0_G3W_RANGE                       11:11
+#define GPIO_X_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_06_0_G3W_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G2W_SHIFT)
+#define GPIO_X_SCR_06_0_G2W_RANGE                       10:10
+#define GPIO_X_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_06_0_G2W_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G1W_SHIFT)
+#define GPIO_X_SCR_06_0_G1W_RANGE                       9:9
+#define GPIO_X_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_06_0_G1W_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G0W_SHIFT)
+#define GPIO_X_SCR_06_0_G0W_RANGE                       8:8
+#define GPIO_X_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_06_0_G0W_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G7R_SHIFT)
+#define GPIO_X_SCR_06_0_G7R_RANGE                       7:7
+#define GPIO_X_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_06_0_G7R_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G6R_SHIFT)
+#define GPIO_X_SCR_06_0_G6R_RANGE                       6:6
+#define GPIO_X_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_06_0_G6R_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G5R_SHIFT)
+#define GPIO_X_SCR_06_0_G5R_RANGE                       5:5
+#define GPIO_X_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_06_0_G5R_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G4R_SHIFT)
+#define GPIO_X_SCR_06_0_G4R_RANGE                       4:4
+#define GPIO_X_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_06_0_G4R_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G3R_SHIFT)
+#define GPIO_X_SCR_06_0_G3R_RANGE                       3:3
+#define GPIO_X_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_06_0_G3R_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G2R_SHIFT)
+#define GPIO_X_SCR_06_0_G2R_RANGE                       2:2
+#define GPIO_X_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_06_0_G2R_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G1R_SHIFT)
+#define GPIO_X_SCR_06_0_G1R_RANGE                       1:1
+#define GPIO_X_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_06_0_G1R_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_06_0_G0R_SHIFT)
+#define GPIO_X_SCR_06_0_G0R_RANGE                       0:0
+#define GPIO_X_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_06_0_G0R_WOFFSET                     0x0
+#define GPIO_X_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_VM_07_0
+#define GPIO_X_VM_07_0                  MK_ADDR_CONST(0x1038)
+#define GPIO_X_VM_07_0_SECURE                   0x0
+#define GPIO_X_VM_07_0_DUAL                     0x0
+#define GPIO_X_VM_07_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_X_VM_07_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_X_VM_07_0_WORD_COUNT                       0x1
+#define GPIO_X_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_X_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_X_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM1_SHIFT)
+#define GPIO_X_VM_07_0_VM1_RANGE                        1:0
+#define GPIO_X_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_X_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_X_VM_07_0_VM1_WOFFSET                      0x0
+#define GPIO_X_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_X_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM2_SHIFT)
+#define GPIO_X_VM_07_0_VM2_RANGE                        3:2
+#define GPIO_X_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_X_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_X_VM_07_0_VM2_WOFFSET                      0x0
+#define GPIO_X_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_X_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM3_SHIFT)
+#define GPIO_X_VM_07_0_VM3_RANGE                        5:4
+#define GPIO_X_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_X_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_X_VM_07_0_VM3_WOFFSET                      0x0
+#define GPIO_X_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_X_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM4_SHIFT)
+#define GPIO_X_VM_07_0_VM4_RANGE                        7:6
+#define GPIO_X_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_X_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_X_VM_07_0_VM4_WOFFSET                      0x0
+#define GPIO_X_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_X_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM5_SHIFT)
+#define GPIO_X_VM_07_0_VM5_RANGE                        9:8
+#define GPIO_X_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_X_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_X_VM_07_0_VM5_WOFFSET                      0x0
+#define GPIO_X_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_X_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM6_SHIFT)
+#define GPIO_X_VM_07_0_VM6_RANGE                        11:10
+#define GPIO_X_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_X_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_X_VM_07_0_VM6_WOFFSET                      0x0
+#define GPIO_X_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_X_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM7_SHIFT)
+#define GPIO_X_VM_07_0_VM7_RANGE                        13:12
+#define GPIO_X_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_X_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_X_VM_07_0_VM7_WOFFSET                      0x0
+#define GPIO_X_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_X_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_X_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_X_VM_07_0_VM8_SHIFT)
+#define GPIO_X_VM_07_0_VM8_RANGE                        15:14
+#define GPIO_X_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_X_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_X_VM_07_0_VM8_WOFFSET                      0x0
+#define GPIO_X_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_X_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_X_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_SCR_07_0
+#define GPIO_X_SCR_07_0                 MK_ADDR_CONST(0x103c)
+#define GPIO_X_SCR_07_0_SECURE                  0x0
+#define GPIO_X_SCR_07_0_DUAL                    0x0
+#define GPIO_X_SCR_07_0_SCR                     0
+#define GPIO_X_SCR_07_0_SCRREG                  0
+#define GPIO_X_SCR_07_0_WORD_COUNT                      0x1
+#define GPIO_X_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_X_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_SEC_LCK_SHIFT)
+#define GPIO_X_SCR_07_0_SEC_LCK_RANGE                   29:29
+#define GPIO_X_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_X_SCR_07_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_X_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_SEC_WEN_SHIFT)
+#define GPIO_X_SCR_07_0_SEC_WEN_RANGE                   28:28
+#define GPIO_X_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_X_SCR_07_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_X_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_SEC_REN_SHIFT)
+#define GPIO_X_SCR_07_0_SEC_REN_RANGE                   27:27
+#define GPIO_X_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_X_SCR_07_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_X_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_X_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_X_SCR_07_0_SEC_OWNER_SHIFT)
+#define GPIO_X_SCR_07_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_X_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_X_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_X_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_X_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_X_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR7_SHIFT)
+#define GPIO_X_SCR_07_0_PR7_RANGE                       23:23
+#define GPIO_X_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_X_SCR_07_0_PR7_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR6_SHIFT)
+#define GPIO_X_SCR_07_0_PR6_RANGE                       22:22
+#define GPIO_X_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_X_SCR_07_0_PR6_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR5_SHIFT)
+#define GPIO_X_SCR_07_0_PR5_RANGE                       21:21
+#define GPIO_X_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_X_SCR_07_0_PR5_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR4_SHIFT)
+#define GPIO_X_SCR_07_0_PR4_RANGE                       20:20
+#define GPIO_X_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_X_SCR_07_0_PR4_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR3_SHIFT)
+#define GPIO_X_SCR_07_0_PR3_RANGE                       19:19
+#define GPIO_X_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_X_SCR_07_0_PR3_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR2_SHIFT)
+#define GPIO_X_SCR_07_0_PR2_RANGE                       18:18
+#define GPIO_X_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_X_SCR_07_0_PR2_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR1_SHIFT)
+#define GPIO_X_SCR_07_0_PR1_RANGE                       17:17
+#define GPIO_X_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_X_SCR_07_0_PR1_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_PR0_SHIFT)
+#define GPIO_X_SCR_07_0_PR0_RANGE                       16:16
+#define GPIO_X_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_X_SCR_07_0_PR0_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G7W_SHIFT)
+#define GPIO_X_SCR_07_0_G7W_RANGE                       15:15
+#define GPIO_X_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_X_SCR_07_0_G7W_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G6W_SHIFT)
+#define GPIO_X_SCR_07_0_G6W_RANGE                       14:14
+#define GPIO_X_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_X_SCR_07_0_G6W_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G5W_SHIFT)
+#define GPIO_X_SCR_07_0_G5W_RANGE                       13:13
+#define GPIO_X_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_X_SCR_07_0_G5W_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G4W_SHIFT)
+#define GPIO_X_SCR_07_0_G4W_RANGE                       12:12
+#define GPIO_X_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_X_SCR_07_0_G4W_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G3W_SHIFT)
+#define GPIO_X_SCR_07_0_G3W_RANGE                       11:11
+#define GPIO_X_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_X_SCR_07_0_G3W_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G2W_SHIFT)
+#define GPIO_X_SCR_07_0_G2W_RANGE                       10:10
+#define GPIO_X_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_X_SCR_07_0_G2W_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G1W_SHIFT)
+#define GPIO_X_SCR_07_0_G1W_RANGE                       9:9
+#define GPIO_X_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_X_SCR_07_0_G1W_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G0W_SHIFT)
+#define GPIO_X_SCR_07_0_G0W_RANGE                       8:8
+#define GPIO_X_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_X_SCR_07_0_G0W_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G7R_SHIFT)
+#define GPIO_X_SCR_07_0_G7R_RANGE                       7:7
+#define GPIO_X_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_X_SCR_07_0_G7R_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G6R_SHIFT)
+#define GPIO_X_SCR_07_0_G6R_RANGE                       6:6
+#define GPIO_X_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_X_SCR_07_0_G6R_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G5R_SHIFT)
+#define GPIO_X_SCR_07_0_G5R_RANGE                       5:5
+#define GPIO_X_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_SCR_07_0_G5R_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G4R_SHIFT)
+#define GPIO_X_SCR_07_0_G4R_RANGE                       4:4
+#define GPIO_X_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_X_SCR_07_0_G4R_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G3R_SHIFT)
+#define GPIO_X_SCR_07_0_G3R_RANGE                       3:3
+#define GPIO_X_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_X_SCR_07_0_G3R_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G2R_SHIFT)
+#define GPIO_X_SCR_07_0_G2R_RANGE                       2:2
+#define GPIO_X_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_X_SCR_07_0_G2R_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G1R_SHIFT)
+#define GPIO_X_SCR_07_0_G1R_RANGE                       1:1
+#define GPIO_X_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_X_SCR_07_0_G1R_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_X_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_SCR_07_0_G0R_SHIFT)
+#define GPIO_X_SCR_07_0_G0R_RANGE                       0:0
+#define GPIO_X_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_SCR_07_0_G0R_WOFFSET                     0x0
+#define GPIO_X_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_X_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_VM_00_0
+#define GPIO_Y_VM_00_0                  MK_ADDR_CONST(0x1040)
+#define GPIO_Y_VM_00_0_SECURE                   0x0
+#define GPIO_Y_VM_00_0_DUAL                     0x0
+#define GPIO_Y_VM_00_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_Y_VM_00_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_Y_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_Y_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Y_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM1_SHIFT)
+#define GPIO_Y_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_Y_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Y_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Y_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_Y_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Y_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM2_SHIFT)
+#define GPIO_Y_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_Y_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Y_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Y_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_Y_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Y_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM3_SHIFT)
+#define GPIO_Y_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_Y_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Y_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Y_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_Y_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Y_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM4_SHIFT)
+#define GPIO_Y_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_Y_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Y_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Y_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_Y_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Y_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM5_SHIFT)
+#define GPIO_Y_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_Y_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Y_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Y_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_Y_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Y_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM6_SHIFT)
+#define GPIO_Y_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_Y_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Y_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Y_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_Y_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Y_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM7_SHIFT)
+#define GPIO_Y_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_Y_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Y_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Y_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_Y_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Y_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_00_0_VM8_SHIFT)
+#define GPIO_Y_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_Y_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Y_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Y_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_Y_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_SCR_00_0
+#define GPIO_Y_SCR_00_0                 MK_ADDR_CONST(0x1044)
+#define GPIO_Y_SCR_00_0_SECURE                  0x0
+#define GPIO_Y_SCR_00_0_DUAL                    0x0
+#define GPIO_Y_SCR_00_0_SCR                     0
+#define GPIO_Y_SCR_00_0_SCRREG                  0
+#define GPIO_Y_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_Y_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_Y_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Y_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Y_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_Y_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Y_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Y_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_Y_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_Y_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Y_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Y_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Y_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_Y_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Y_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Y_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Y_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Y_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Y_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR7_SHIFT)
+#define GPIO_Y_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_Y_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR6_SHIFT)
+#define GPIO_Y_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_Y_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR5_SHIFT)
+#define GPIO_Y_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_Y_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR4_SHIFT)
+#define GPIO_Y_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_Y_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR3_SHIFT)
+#define GPIO_Y_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_Y_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR2_SHIFT)
+#define GPIO_Y_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_Y_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR1_SHIFT)
+#define GPIO_Y_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_Y_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_PR0_SHIFT)
+#define GPIO_Y_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_Y_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G7W_SHIFT)
+#define GPIO_Y_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_Y_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G6W_SHIFT)
+#define GPIO_Y_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_Y_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G5W_SHIFT)
+#define GPIO_Y_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_Y_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G4W_SHIFT)
+#define GPIO_Y_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_Y_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G3W_SHIFT)
+#define GPIO_Y_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_Y_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G2W_SHIFT)
+#define GPIO_Y_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_Y_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G1W_SHIFT)
+#define GPIO_Y_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_Y_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G0W_SHIFT)
+#define GPIO_Y_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_Y_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G7R_SHIFT)
+#define GPIO_Y_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_Y_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G6R_SHIFT)
+#define GPIO_Y_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_Y_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G5R_SHIFT)
+#define GPIO_Y_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_Y_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G4R_SHIFT)
+#define GPIO_Y_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_Y_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G3R_SHIFT)
+#define GPIO_Y_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_Y_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G2R_SHIFT)
+#define GPIO_Y_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_Y_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G1R_SHIFT)
+#define GPIO_Y_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_Y_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_00_0_G0R_SHIFT)
+#define GPIO_Y_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_Y_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_Y_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_VM_01_0
+#define GPIO_Y_VM_01_0                  MK_ADDR_CONST(0x1048)
+#define GPIO_Y_VM_01_0_SECURE                   0x0
+#define GPIO_Y_VM_01_0_DUAL                     0x0
+#define GPIO_Y_VM_01_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_Y_VM_01_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_Y_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_Y_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Y_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM1_SHIFT)
+#define GPIO_Y_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_Y_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Y_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Y_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_Y_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Y_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM2_SHIFT)
+#define GPIO_Y_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_Y_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Y_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Y_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_Y_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Y_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM3_SHIFT)
+#define GPIO_Y_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_Y_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Y_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Y_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_Y_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Y_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM4_SHIFT)
+#define GPIO_Y_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_Y_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Y_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Y_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_Y_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Y_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM5_SHIFT)
+#define GPIO_Y_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_Y_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Y_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Y_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_Y_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Y_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM6_SHIFT)
+#define GPIO_Y_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_Y_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Y_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Y_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_Y_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Y_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM7_SHIFT)
+#define GPIO_Y_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_Y_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Y_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Y_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_Y_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Y_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_01_0_VM8_SHIFT)
+#define GPIO_Y_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_Y_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Y_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Y_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_Y_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_SCR_01_0
+#define GPIO_Y_SCR_01_0                 MK_ADDR_CONST(0x104c)
+#define GPIO_Y_SCR_01_0_SECURE                  0x0
+#define GPIO_Y_SCR_01_0_DUAL                    0x0
+#define GPIO_Y_SCR_01_0_SCR                     0
+#define GPIO_Y_SCR_01_0_SCRREG                  0
+#define GPIO_Y_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_Y_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_Y_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Y_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Y_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_Y_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Y_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Y_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_Y_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_Y_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Y_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Y_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Y_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_Y_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Y_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Y_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Y_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Y_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Y_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR7_SHIFT)
+#define GPIO_Y_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_Y_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR6_SHIFT)
+#define GPIO_Y_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_Y_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR5_SHIFT)
+#define GPIO_Y_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_Y_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR4_SHIFT)
+#define GPIO_Y_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_Y_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR3_SHIFT)
+#define GPIO_Y_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_Y_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR2_SHIFT)
+#define GPIO_Y_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_Y_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR1_SHIFT)
+#define GPIO_Y_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_Y_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_PR0_SHIFT)
+#define GPIO_Y_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_Y_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G7W_SHIFT)
+#define GPIO_Y_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_Y_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G6W_SHIFT)
+#define GPIO_Y_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_Y_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G5W_SHIFT)
+#define GPIO_Y_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_Y_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G4W_SHIFT)
+#define GPIO_Y_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_Y_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G3W_SHIFT)
+#define GPIO_Y_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_Y_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G2W_SHIFT)
+#define GPIO_Y_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_Y_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G1W_SHIFT)
+#define GPIO_Y_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_Y_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G0W_SHIFT)
+#define GPIO_Y_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_Y_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G7R_SHIFT)
+#define GPIO_Y_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_Y_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G6R_SHIFT)
+#define GPIO_Y_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_Y_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G5R_SHIFT)
+#define GPIO_Y_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_Y_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G4R_SHIFT)
+#define GPIO_Y_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_Y_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G3R_SHIFT)
+#define GPIO_Y_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_Y_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G2R_SHIFT)
+#define GPIO_Y_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_Y_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G1R_SHIFT)
+#define GPIO_Y_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_Y_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_01_0_G0R_SHIFT)
+#define GPIO_Y_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_Y_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_Y_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_VM_02_0
+#define GPIO_Y_VM_02_0                  MK_ADDR_CONST(0x1050)
+#define GPIO_Y_VM_02_0_SECURE                   0x0
+#define GPIO_Y_VM_02_0_DUAL                     0x0
+#define GPIO_Y_VM_02_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_Y_VM_02_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_Y_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_Y_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Y_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM1_SHIFT)
+#define GPIO_Y_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_Y_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Y_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Y_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_Y_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Y_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM2_SHIFT)
+#define GPIO_Y_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_Y_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Y_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Y_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_Y_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Y_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM3_SHIFT)
+#define GPIO_Y_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_Y_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Y_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Y_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_Y_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Y_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM4_SHIFT)
+#define GPIO_Y_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_Y_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Y_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Y_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_Y_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Y_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM5_SHIFT)
+#define GPIO_Y_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_Y_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Y_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Y_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_Y_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Y_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM6_SHIFT)
+#define GPIO_Y_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_Y_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Y_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Y_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_Y_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Y_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM7_SHIFT)
+#define GPIO_Y_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_Y_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Y_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Y_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_Y_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Y_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_02_0_VM8_SHIFT)
+#define GPIO_Y_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_Y_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Y_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Y_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_Y_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_SCR_02_0
+#define GPIO_Y_SCR_02_0                 MK_ADDR_CONST(0x1054)
+#define GPIO_Y_SCR_02_0_SECURE                  0x0
+#define GPIO_Y_SCR_02_0_DUAL                    0x0
+#define GPIO_Y_SCR_02_0_SCR                     0
+#define GPIO_Y_SCR_02_0_SCRREG                  0
+#define GPIO_Y_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_Y_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_Y_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Y_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Y_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_Y_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Y_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Y_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_Y_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_Y_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Y_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Y_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Y_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_Y_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Y_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Y_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Y_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Y_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Y_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR7_SHIFT)
+#define GPIO_Y_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_Y_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR6_SHIFT)
+#define GPIO_Y_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_Y_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR5_SHIFT)
+#define GPIO_Y_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_Y_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR4_SHIFT)
+#define GPIO_Y_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_Y_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR3_SHIFT)
+#define GPIO_Y_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_Y_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR2_SHIFT)
+#define GPIO_Y_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_Y_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR1_SHIFT)
+#define GPIO_Y_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_Y_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_PR0_SHIFT)
+#define GPIO_Y_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_Y_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G7W_SHIFT)
+#define GPIO_Y_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_Y_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G6W_SHIFT)
+#define GPIO_Y_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_Y_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G5W_SHIFT)
+#define GPIO_Y_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_Y_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G4W_SHIFT)
+#define GPIO_Y_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_Y_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G3W_SHIFT)
+#define GPIO_Y_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_Y_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G2W_SHIFT)
+#define GPIO_Y_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_Y_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G1W_SHIFT)
+#define GPIO_Y_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_Y_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G0W_SHIFT)
+#define GPIO_Y_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_Y_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G7R_SHIFT)
+#define GPIO_Y_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_Y_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G6R_SHIFT)
+#define GPIO_Y_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_Y_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G5R_SHIFT)
+#define GPIO_Y_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_Y_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G4R_SHIFT)
+#define GPIO_Y_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_Y_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G3R_SHIFT)
+#define GPIO_Y_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_Y_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G2R_SHIFT)
+#define GPIO_Y_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_Y_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G1R_SHIFT)
+#define GPIO_Y_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_Y_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_02_0_G0R_SHIFT)
+#define GPIO_Y_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_Y_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_Y_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_VM_03_0
+#define GPIO_Y_VM_03_0                  MK_ADDR_CONST(0x1058)
+#define GPIO_Y_VM_03_0_SECURE                   0x0
+#define GPIO_Y_VM_03_0_DUAL                     0x0
+#define GPIO_Y_VM_03_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_Y_VM_03_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_Y_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_Y_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Y_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM1_SHIFT)
+#define GPIO_Y_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_Y_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Y_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Y_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_Y_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Y_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM2_SHIFT)
+#define GPIO_Y_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_Y_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Y_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Y_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_Y_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Y_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM3_SHIFT)
+#define GPIO_Y_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_Y_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Y_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Y_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_Y_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Y_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM4_SHIFT)
+#define GPIO_Y_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_Y_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Y_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Y_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_Y_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Y_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM5_SHIFT)
+#define GPIO_Y_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_Y_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Y_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Y_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_Y_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Y_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM6_SHIFT)
+#define GPIO_Y_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_Y_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Y_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Y_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_Y_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Y_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM7_SHIFT)
+#define GPIO_Y_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_Y_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Y_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Y_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_Y_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Y_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_03_0_VM8_SHIFT)
+#define GPIO_Y_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_Y_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Y_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Y_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_Y_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_SCR_03_0
+#define GPIO_Y_SCR_03_0                 MK_ADDR_CONST(0x105c)
+#define GPIO_Y_SCR_03_0_SECURE                  0x0
+#define GPIO_Y_SCR_03_0_DUAL                    0x0
+#define GPIO_Y_SCR_03_0_SCR                     0
+#define GPIO_Y_SCR_03_0_SCRREG                  0
+#define GPIO_Y_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_Y_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_Y_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Y_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Y_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_Y_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Y_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Y_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_Y_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_Y_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Y_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Y_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Y_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_Y_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Y_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Y_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Y_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Y_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Y_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR7_SHIFT)
+#define GPIO_Y_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_Y_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR6_SHIFT)
+#define GPIO_Y_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_Y_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR5_SHIFT)
+#define GPIO_Y_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_Y_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR4_SHIFT)
+#define GPIO_Y_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_Y_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR3_SHIFT)
+#define GPIO_Y_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_Y_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR2_SHIFT)
+#define GPIO_Y_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_Y_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR1_SHIFT)
+#define GPIO_Y_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_Y_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_PR0_SHIFT)
+#define GPIO_Y_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_Y_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G7W_SHIFT)
+#define GPIO_Y_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_Y_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G6W_SHIFT)
+#define GPIO_Y_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_Y_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G5W_SHIFT)
+#define GPIO_Y_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_Y_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G4W_SHIFT)
+#define GPIO_Y_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_Y_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G3W_SHIFT)
+#define GPIO_Y_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_Y_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G2W_SHIFT)
+#define GPIO_Y_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_Y_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G1W_SHIFT)
+#define GPIO_Y_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_Y_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G0W_SHIFT)
+#define GPIO_Y_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_Y_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G7R_SHIFT)
+#define GPIO_Y_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_Y_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G6R_SHIFT)
+#define GPIO_Y_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_Y_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G5R_SHIFT)
+#define GPIO_Y_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_Y_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G4R_SHIFT)
+#define GPIO_Y_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_Y_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G3R_SHIFT)
+#define GPIO_Y_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_Y_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G2R_SHIFT)
+#define GPIO_Y_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_Y_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G1R_SHIFT)
+#define GPIO_Y_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_Y_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_03_0_G0R_SHIFT)
+#define GPIO_Y_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_Y_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_Y_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_VM_04_0
+#define GPIO_Y_VM_04_0                  MK_ADDR_CONST(0x1060)
+#define GPIO_Y_VM_04_0_SECURE                   0x0
+#define GPIO_Y_VM_04_0_DUAL                     0x0
+#define GPIO_Y_VM_04_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_Y_VM_04_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_Y_VM_04_0_WORD_COUNT                       0x1
+#define GPIO_Y_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Y_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM1_SHIFT)
+#define GPIO_Y_VM_04_0_VM1_RANGE                        1:0
+#define GPIO_Y_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Y_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Y_VM_04_0_VM1_WOFFSET                      0x0
+#define GPIO_Y_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Y_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM2_SHIFT)
+#define GPIO_Y_VM_04_0_VM2_RANGE                        3:2
+#define GPIO_Y_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Y_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Y_VM_04_0_VM2_WOFFSET                      0x0
+#define GPIO_Y_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Y_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM3_SHIFT)
+#define GPIO_Y_VM_04_0_VM3_RANGE                        5:4
+#define GPIO_Y_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Y_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Y_VM_04_0_VM3_WOFFSET                      0x0
+#define GPIO_Y_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Y_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM4_SHIFT)
+#define GPIO_Y_VM_04_0_VM4_RANGE                        7:6
+#define GPIO_Y_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Y_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Y_VM_04_0_VM4_WOFFSET                      0x0
+#define GPIO_Y_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Y_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM5_SHIFT)
+#define GPIO_Y_VM_04_0_VM5_RANGE                        9:8
+#define GPIO_Y_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Y_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Y_VM_04_0_VM5_WOFFSET                      0x0
+#define GPIO_Y_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Y_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM6_SHIFT)
+#define GPIO_Y_VM_04_0_VM6_RANGE                        11:10
+#define GPIO_Y_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Y_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Y_VM_04_0_VM6_WOFFSET                      0x0
+#define GPIO_Y_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Y_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM7_SHIFT)
+#define GPIO_Y_VM_04_0_VM7_RANGE                        13:12
+#define GPIO_Y_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Y_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Y_VM_04_0_VM7_WOFFSET                      0x0
+#define GPIO_Y_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Y_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_04_0_VM8_SHIFT)
+#define GPIO_Y_VM_04_0_VM8_RANGE                        15:14
+#define GPIO_Y_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Y_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Y_VM_04_0_VM8_WOFFSET                      0x0
+#define GPIO_Y_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_SCR_04_0
+#define GPIO_Y_SCR_04_0                 MK_ADDR_CONST(0x1064)
+#define GPIO_Y_SCR_04_0_SECURE                  0x0
+#define GPIO_Y_SCR_04_0_DUAL                    0x0
+#define GPIO_Y_SCR_04_0_SCR                     0
+#define GPIO_Y_SCR_04_0_SCRREG                  0
+#define GPIO_Y_SCR_04_0_WORD_COUNT                      0x1
+#define GPIO_Y_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_Y_SCR_04_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Y_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_04_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Y_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_Y_SCR_04_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Y_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_04_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Y_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_Y_SCR_04_0_SEC_REN_RANGE                   27:27
+#define GPIO_Y_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_04_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Y_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Y_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Y_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_Y_SCR_04_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Y_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Y_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Y_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Y_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Y_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR7_SHIFT)
+#define GPIO_Y_SCR_04_0_PR7_RANGE                       23:23
+#define GPIO_Y_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_04_0_PR7_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR6_SHIFT)
+#define GPIO_Y_SCR_04_0_PR6_RANGE                       22:22
+#define GPIO_Y_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_04_0_PR6_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR5_SHIFT)
+#define GPIO_Y_SCR_04_0_PR5_RANGE                       21:21
+#define GPIO_Y_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_04_0_PR5_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR4_SHIFT)
+#define GPIO_Y_SCR_04_0_PR4_RANGE                       20:20
+#define GPIO_Y_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_04_0_PR4_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR3_SHIFT)
+#define GPIO_Y_SCR_04_0_PR3_RANGE                       19:19
+#define GPIO_Y_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_04_0_PR3_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR2_SHIFT)
+#define GPIO_Y_SCR_04_0_PR2_RANGE                       18:18
+#define GPIO_Y_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_04_0_PR2_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR1_SHIFT)
+#define GPIO_Y_SCR_04_0_PR1_RANGE                       17:17
+#define GPIO_Y_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_04_0_PR1_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_PR0_SHIFT)
+#define GPIO_Y_SCR_04_0_PR0_RANGE                       16:16
+#define GPIO_Y_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_04_0_PR0_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G7W_SHIFT)
+#define GPIO_Y_SCR_04_0_G7W_RANGE                       15:15
+#define GPIO_Y_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_04_0_G7W_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G6W_SHIFT)
+#define GPIO_Y_SCR_04_0_G6W_RANGE                       14:14
+#define GPIO_Y_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_04_0_G6W_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G5W_SHIFT)
+#define GPIO_Y_SCR_04_0_G5W_RANGE                       13:13
+#define GPIO_Y_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_04_0_G5W_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G4W_SHIFT)
+#define GPIO_Y_SCR_04_0_G4W_RANGE                       12:12
+#define GPIO_Y_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_04_0_G4W_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G3W_SHIFT)
+#define GPIO_Y_SCR_04_0_G3W_RANGE                       11:11
+#define GPIO_Y_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_04_0_G3W_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G2W_SHIFT)
+#define GPIO_Y_SCR_04_0_G2W_RANGE                       10:10
+#define GPIO_Y_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_04_0_G2W_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G1W_SHIFT)
+#define GPIO_Y_SCR_04_0_G1W_RANGE                       9:9
+#define GPIO_Y_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_04_0_G1W_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G0W_SHIFT)
+#define GPIO_Y_SCR_04_0_G0W_RANGE                       8:8
+#define GPIO_Y_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_04_0_G0W_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G7R_SHIFT)
+#define GPIO_Y_SCR_04_0_G7R_RANGE                       7:7
+#define GPIO_Y_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_04_0_G7R_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G6R_SHIFT)
+#define GPIO_Y_SCR_04_0_G6R_RANGE                       6:6
+#define GPIO_Y_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_04_0_G6R_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G5R_SHIFT)
+#define GPIO_Y_SCR_04_0_G5R_RANGE                       5:5
+#define GPIO_Y_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_04_0_G5R_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G4R_SHIFT)
+#define GPIO_Y_SCR_04_0_G4R_RANGE                       4:4
+#define GPIO_Y_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_04_0_G4R_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G3R_SHIFT)
+#define GPIO_Y_SCR_04_0_G3R_RANGE                       3:3
+#define GPIO_Y_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_04_0_G3R_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G2R_SHIFT)
+#define GPIO_Y_SCR_04_0_G2R_RANGE                       2:2
+#define GPIO_Y_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_04_0_G2R_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G1R_SHIFT)
+#define GPIO_Y_SCR_04_0_G1R_RANGE                       1:1
+#define GPIO_Y_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_04_0_G1R_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_04_0_G0R_SHIFT)
+#define GPIO_Y_SCR_04_0_G0R_RANGE                       0:0
+#define GPIO_Y_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_04_0_G0R_WOFFSET                     0x0
+#define GPIO_Y_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_VM_05_0
+#define GPIO_Y_VM_05_0                  MK_ADDR_CONST(0x1068)
+#define GPIO_Y_VM_05_0_SECURE                   0x0
+#define GPIO_Y_VM_05_0_DUAL                     0x0
+#define GPIO_Y_VM_05_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_Y_VM_05_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_Y_VM_05_0_WORD_COUNT                       0x1
+#define GPIO_Y_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Y_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM1_SHIFT)
+#define GPIO_Y_VM_05_0_VM1_RANGE                        1:0
+#define GPIO_Y_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Y_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Y_VM_05_0_VM1_WOFFSET                      0x0
+#define GPIO_Y_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Y_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM2_SHIFT)
+#define GPIO_Y_VM_05_0_VM2_RANGE                        3:2
+#define GPIO_Y_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Y_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Y_VM_05_0_VM2_WOFFSET                      0x0
+#define GPIO_Y_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Y_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM3_SHIFT)
+#define GPIO_Y_VM_05_0_VM3_RANGE                        5:4
+#define GPIO_Y_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Y_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Y_VM_05_0_VM3_WOFFSET                      0x0
+#define GPIO_Y_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Y_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM4_SHIFT)
+#define GPIO_Y_VM_05_0_VM4_RANGE                        7:6
+#define GPIO_Y_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Y_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Y_VM_05_0_VM4_WOFFSET                      0x0
+#define GPIO_Y_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Y_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM5_SHIFT)
+#define GPIO_Y_VM_05_0_VM5_RANGE                        9:8
+#define GPIO_Y_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Y_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Y_VM_05_0_VM5_WOFFSET                      0x0
+#define GPIO_Y_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Y_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM6_SHIFT)
+#define GPIO_Y_VM_05_0_VM6_RANGE                        11:10
+#define GPIO_Y_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Y_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Y_VM_05_0_VM6_WOFFSET                      0x0
+#define GPIO_Y_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Y_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM7_SHIFT)
+#define GPIO_Y_VM_05_0_VM7_RANGE                        13:12
+#define GPIO_Y_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Y_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Y_VM_05_0_VM7_WOFFSET                      0x0
+#define GPIO_Y_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Y_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_05_0_VM8_SHIFT)
+#define GPIO_Y_VM_05_0_VM8_RANGE                        15:14
+#define GPIO_Y_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Y_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Y_VM_05_0_VM8_WOFFSET                      0x0
+#define GPIO_Y_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_SCR_05_0
+#define GPIO_Y_SCR_05_0                 MK_ADDR_CONST(0x106c)
+#define GPIO_Y_SCR_05_0_SECURE                  0x0
+#define GPIO_Y_SCR_05_0_DUAL                    0x0
+#define GPIO_Y_SCR_05_0_SCR                     0
+#define GPIO_Y_SCR_05_0_SCRREG                  0
+#define GPIO_Y_SCR_05_0_WORD_COUNT                      0x1
+#define GPIO_Y_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_Y_SCR_05_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Y_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_05_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Y_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_Y_SCR_05_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Y_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_05_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Y_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_Y_SCR_05_0_SEC_REN_RANGE                   27:27
+#define GPIO_Y_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_05_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Y_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Y_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Y_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_Y_SCR_05_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Y_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Y_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Y_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Y_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Y_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR7_SHIFT)
+#define GPIO_Y_SCR_05_0_PR7_RANGE                       23:23
+#define GPIO_Y_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_05_0_PR7_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR6_SHIFT)
+#define GPIO_Y_SCR_05_0_PR6_RANGE                       22:22
+#define GPIO_Y_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_05_0_PR6_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR5_SHIFT)
+#define GPIO_Y_SCR_05_0_PR5_RANGE                       21:21
+#define GPIO_Y_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_05_0_PR5_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR4_SHIFT)
+#define GPIO_Y_SCR_05_0_PR4_RANGE                       20:20
+#define GPIO_Y_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_05_0_PR4_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR3_SHIFT)
+#define GPIO_Y_SCR_05_0_PR3_RANGE                       19:19
+#define GPIO_Y_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_05_0_PR3_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR2_SHIFT)
+#define GPIO_Y_SCR_05_0_PR2_RANGE                       18:18
+#define GPIO_Y_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_05_0_PR2_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR1_SHIFT)
+#define GPIO_Y_SCR_05_0_PR1_RANGE                       17:17
+#define GPIO_Y_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_05_0_PR1_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_PR0_SHIFT)
+#define GPIO_Y_SCR_05_0_PR0_RANGE                       16:16
+#define GPIO_Y_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_05_0_PR0_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G7W_SHIFT)
+#define GPIO_Y_SCR_05_0_G7W_RANGE                       15:15
+#define GPIO_Y_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_05_0_G7W_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G6W_SHIFT)
+#define GPIO_Y_SCR_05_0_G6W_RANGE                       14:14
+#define GPIO_Y_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_05_0_G6W_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G5W_SHIFT)
+#define GPIO_Y_SCR_05_0_G5W_RANGE                       13:13
+#define GPIO_Y_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_05_0_G5W_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G4W_SHIFT)
+#define GPIO_Y_SCR_05_0_G4W_RANGE                       12:12
+#define GPIO_Y_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_05_0_G4W_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G3W_SHIFT)
+#define GPIO_Y_SCR_05_0_G3W_RANGE                       11:11
+#define GPIO_Y_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_05_0_G3W_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G2W_SHIFT)
+#define GPIO_Y_SCR_05_0_G2W_RANGE                       10:10
+#define GPIO_Y_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_05_0_G2W_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G1W_SHIFT)
+#define GPIO_Y_SCR_05_0_G1W_RANGE                       9:9
+#define GPIO_Y_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_05_0_G1W_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G0W_SHIFT)
+#define GPIO_Y_SCR_05_0_G0W_RANGE                       8:8
+#define GPIO_Y_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_05_0_G0W_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G7R_SHIFT)
+#define GPIO_Y_SCR_05_0_G7R_RANGE                       7:7
+#define GPIO_Y_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_05_0_G7R_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G6R_SHIFT)
+#define GPIO_Y_SCR_05_0_G6R_RANGE                       6:6
+#define GPIO_Y_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_05_0_G6R_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G5R_SHIFT)
+#define GPIO_Y_SCR_05_0_G5R_RANGE                       5:5
+#define GPIO_Y_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_05_0_G5R_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G4R_SHIFT)
+#define GPIO_Y_SCR_05_0_G4R_RANGE                       4:4
+#define GPIO_Y_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_05_0_G4R_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G3R_SHIFT)
+#define GPIO_Y_SCR_05_0_G3R_RANGE                       3:3
+#define GPIO_Y_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_05_0_G3R_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G2R_SHIFT)
+#define GPIO_Y_SCR_05_0_G2R_RANGE                       2:2
+#define GPIO_Y_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_05_0_G2R_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G1R_SHIFT)
+#define GPIO_Y_SCR_05_0_G1R_RANGE                       1:1
+#define GPIO_Y_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_05_0_G1R_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_05_0_G0R_SHIFT)
+#define GPIO_Y_SCR_05_0_G0R_RANGE                       0:0
+#define GPIO_Y_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_05_0_G0R_WOFFSET                     0x0
+#define GPIO_Y_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_VM_06_0
+#define GPIO_Y_VM_06_0                  MK_ADDR_CONST(0x1070)
+#define GPIO_Y_VM_06_0_SECURE                   0x0
+#define GPIO_Y_VM_06_0_DUAL                     0x0
+#define GPIO_Y_VM_06_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_Y_VM_06_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_Y_VM_06_0_WORD_COUNT                       0x1
+#define GPIO_Y_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Y_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM1_SHIFT)
+#define GPIO_Y_VM_06_0_VM1_RANGE                        1:0
+#define GPIO_Y_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Y_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Y_VM_06_0_VM1_WOFFSET                      0x0
+#define GPIO_Y_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Y_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM2_SHIFT)
+#define GPIO_Y_VM_06_0_VM2_RANGE                        3:2
+#define GPIO_Y_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Y_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Y_VM_06_0_VM2_WOFFSET                      0x0
+#define GPIO_Y_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Y_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM3_SHIFT)
+#define GPIO_Y_VM_06_0_VM3_RANGE                        5:4
+#define GPIO_Y_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Y_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Y_VM_06_0_VM3_WOFFSET                      0x0
+#define GPIO_Y_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Y_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM4_SHIFT)
+#define GPIO_Y_VM_06_0_VM4_RANGE                        7:6
+#define GPIO_Y_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Y_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Y_VM_06_0_VM4_WOFFSET                      0x0
+#define GPIO_Y_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Y_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM5_SHIFT)
+#define GPIO_Y_VM_06_0_VM5_RANGE                        9:8
+#define GPIO_Y_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Y_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Y_VM_06_0_VM5_WOFFSET                      0x0
+#define GPIO_Y_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Y_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM6_SHIFT)
+#define GPIO_Y_VM_06_0_VM6_RANGE                        11:10
+#define GPIO_Y_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Y_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Y_VM_06_0_VM6_WOFFSET                      0x0
+#define GPIO_Y_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Y_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM7_SHIFT)
+#define GPIO_Y_VM_06_0_VM7_RANGE                        13:12
+#define GPIO_Y_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Y_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Y_VM_06_0_VM7_WOFFSET                      0x0
+#define GPIO_Y_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Y_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_06_0_VM8_SHIFT)
+#define GPIO_Y_VM_06_0_VM8_RANGE                        15:14
+#define GPIO_Y_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Y_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Y_VM_06_0_VM8_WOFFSET                      0x0
+#define GPIO_Y_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_SCR_06_0
+#define GPIO_Y_SCR_06_0                 MK_ADDR_CONST(0x1074)
+#define GPIO_Y_SCR_06_0_SECURE                  0x0
+#define GPIO_Y_SCR_06_0_DUAL                    0x0
+#define GPIO_Y_SCR_06_0_SCR                     0
+#define GPIO_Y_SCR_06_0_SCRREG                  0
+#define GPIO_Y_SCR_06_0_WORD_COUNT                      0x1
+#define GPIO_Y_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_SEC_LCK_SHIFT)
+#define GPIO_Y_SCR_06_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Y_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_06_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Y_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_SEC_WEN_SHIFT)
+#define GPIO_Y_SCR_06_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Y_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_06_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Y_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_SEC_REN_SHIFT)
+#define GPIO_Y_SCR_06_0_SEC_REN_RANGE                   27:27
+#define GPIO_Y_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_06_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Y_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Y_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Y_SCR_06_0_SEC_OWNER_SHIFT)
+#define GPIO_Y_SCR_06_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Y_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Y_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Y_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Y_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Y_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR7_SHIFT)
+#define GPIO_Y_SCR_06_0_PR7_RANGE                       23:23
+#define GPIO_Y_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_06_0_PR7_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR6_SHIFT)
+#define GPIO_Y_SCR_06_0_PR6_RANGE                       22:22
+#define GPIO_Y_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_06_0_PR6_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR5_SHIFT)
+#define GPIO_Y_SCR_06_0_PR5_RANGE                       21:21
+#define GPIO_Y_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_06_0_PR5_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR4_SHIFT)
+#define GPIO_Y_SCR_06_0_PR4_RANGE                       20:20
+#define GPIO_Y_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_06_0_PR4_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR3_SHIFT)
+#define GPIO_Y_SCR_06_0_PR3_RANGE                       19:19
+#define GPIO_Y_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_06_0_PR3_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR2_SHIFT)
+#define GPIO_Y_SCR_06_0_PR2_RANGE                       18:18
+#define GPIO_Y_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_06_0_PR2_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR1_SHIFT)
+#define GPIO_Y_SCR_06_0_PR1_RANGE                       17:17
+#define GPIO_Y_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_06_0_PR1_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_PR0_SHIFT)
+#define GPIO_Y_SCR_06_0_PR0_RANGE                       16:16
+#define GPIO_Y_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_06_0_PR0_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G7W_SHIFT)
+#define GPIO_Y_SCR_06_0_G7W_RANGE                       15:15
+#define GPIO_Y_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_06_0_G7W_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G6W_SHIFT)
+#define GPIO_Y_SCR_06_0_G6W_RANGE                       14:14
+#define GPIO_Y_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_06_0_G6W_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G5W_SHIFT)
+#define GPIO_Y_SCR_06_0_G5W_RANGE                       13:13
+#define GPIO_Y_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_06_0_G5W_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G4W_SHIFT)
+#define GPIO_Y_SCR_06_0_G4W_RANGE                       12:12
+#define GPIO_Y_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_06_0_G4W_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G3W_SHIFT)
+#define GPIO_Y_SCR_06_0_G3W_RANGE                       11:11
+#define GPIO_Y_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_06_0_G3W_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G2W_SHIFT)
+#define GPIO_Y_SCR_06_0_G2W_RANGE                       10:10
+#define GPIO_Y_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_06_0_G2W_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G1W_SHIFT)
+#define GPIO_Y_SCR_06_0_G1W_RANGE                       9:9
+#define GPIO_Y_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_06_0_G1W_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G0W_SHIFT)
+#define GPIO_Y_SCR_06_0_G0W_RANGE                       8:8
+#define GPIO_Y_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_06_0_G0W_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G7R_SHIFT)
+#define GPIO_Y_SCR_06_0_G7R_RANGE                       7:7
+#define GPIO_Y_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_06_0_G7R_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G6R_SHIFT)
+#define GPIO_Y_SCR_06_0_G6R_RANGE                       6:6
+#define GPIO_Y_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_06_0_G6R_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G5R_SHIFT)
+#define GPIO_Y_SCR_06_0_G5R_RANGE                       5:5
+#define GPIO_Y_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_06_0_G5R_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G4R_SHIFT)
+#define GPIO_Y_SCR_06_0_G4R_RANGE                       4:4
+#define GPIO_Y_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_06_0_G4R_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G3R_SHIFT)
+#define GPIO_Y_SCR_06_0_G3R_RANGE                       3:3
+#define GPIO_Y_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_06_0_G3R_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G2R_SHIFT)
+#define GPIO_Y_SCR_06_0_G2R_RANGE                       2:2
+#define GPIO_Y_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_06_0_G2R_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G1R_SHIFT)
+#define GPIO_Y_SCR_06_0_G1R_RANGE                       1:1
+#define GPIO_Y_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_06_0_G1R_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_06_0_G0R_SHIFT)
+#define GPIO_Y_SCR_06_0_G0R_RANGE                       0:0
+#define GPIO_Y_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_06_0_G0R_WOFFSET                     0x0
+#define GPIO_Y_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_VM_07_0
+#define GPIO_Y_VM_07_0                  MK_ADDR_CONST(0x1078)
+#define GPIO_Y_VM_07_0_SECURE                   0x0
+#define GPIO_Y_VM_07_0_DUAL                     0x0
+#define GPIO_Y_VM_07_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_Y_VM_07_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_Y_VM_07_0_WORD_COUNT                       0x1
+#define GPIO_Y_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Y_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Y_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM1_SHIFT)
+#define GPIO_Y_VM_07_0_VM1_RANGE                        1:0
+#define GPIO_Y_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Y_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Y_VM_07_0_VM1_WOFFSET                      0x0
+#define GPIO_Y_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Y_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM2_SHIFT)
+#define GPIO_Y_VM_07_0_VM2_RANGE                        3:2
+#define GPIO_Y_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Y_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Y_VM_07_0_VM2_WOFFSET                      0x0
+#define GPIO_Y_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Y_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM3_SHIFT)
+#define GPIO_Y_VM_07_0_VM3_RANGE                        5:4
+#define GPIO_Y_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Y_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Y_VM_07_0_VM3_WOFFSET                      0x0
+#define GPIO_Y_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Y_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM4_SHIFT)
+#define GPIO_Y_VM_07_0_VM4_RANGE                        7:6
+#define GPIO_Y_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Y_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Y_VM_07_0_VM4_WOFFSET                      0x0
+#define GPIO_Y_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Y_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM5_SHIFT)
+#define GPIO_Y_VM_07_0_VM5_RANGE                        9:8
+#define GPIO_Y_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Y_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Y_VM_07_0_VM5_WOFFSET                      0x0
+#define GPIO_Y_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Y_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM6_SHIFT)
+#define GPIO_Y_VM_07_0_VM6_RANGE                        11:10
+#define GPIO_Y_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Y_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Y_VM_07_0_VM6_WOFFSET                      0x0
+#define GPIO_Y_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Y_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM7_SHIFT)
+#define GPIO_Y_VM_07_0_VM7_RANGE                        13:12
+#define GPIO_Y_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Y_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Y_VM_07_0_VM7_WOFFSET                      0x0
+#define GPIO_Y_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Y_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Y_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Y_VM_07_0_VM8_SHIFT)
+#define GPIO_Y_VM_07_0_VM8_RANGE                        15:14
+#define GPIO_Y_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Y_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Y_VM_07_0_VM8_WOFFSET                      0x0
+#define GPIO_Y_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Y_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_SCR_07_0
+#define GPIO_Y_SCR_07_0                 MK_ADDR_CONST(0x107c)
+#define GPIO_Y_SCR_07_0_SECURE                  0x0
+#define GPIO_Y_SCR_07_0_DUAL                    0x0
+#define GPIO_Y_SCR_07_0_SCR                     0
+#define GPIO_Y_SCR_07_0_SCRREG                  0
+#define GPIO_Y_SCR_07_0_WORD_COUNT                      0x1
+#define GPIO_Y_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Y_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_SEC_LCK_SHIFT)
+#define GPIO_Y_SCR_07_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Y_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Y_SCR_07_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Y_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_SEC_WEN_SHIFT)
+#define GPIO_Y_SCR_07_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Y_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Y_SCR_07_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Y_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_SEC_REN_SHIFT)
+#define GPIO_Y_SCR_07_0_SEC_REN_RANGE                   27:27
+#define GPIO_Y_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Y_SCR_07_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Y_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Y_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Y_SCR_07_0_SEC_OWNER_SHIFT)
+#define GPIO_Y_SCR_07_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Y_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Y_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Y_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Y_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Y_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR7_SHIFT)
+#define GPIO_Y_SCR_07_0_PR7_RANGE                       23:23
+#define GPIO_Y_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Y_SCR_07_0_PR7_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR6_SHIFT)
+#define GPIO_Y_SCR_07_0_PR6_RANGE                       22:22
+#define GPIO_Y_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Y_SCR_07_0_PR6_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR5_SHIFT)
+#define GPIO_Y_SCR_07_0_PR5_RANGE                       21:21
+#define GPIO_Y_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Y_SCR_07_0_PR5_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR4_SHIFT)
+#define GPIO_Y_SCR_07_0_PR4_RANGE                       20:20
+#define GPIO_Y_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Y_SCR_07_0_PR4_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR3_SHIFT)
+#define GPIO_Y_SCR_07_0_PR3_RANGE                       19:19
+#define GPIO_Y_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Y_SCR_07_0_PR3_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR2_SHIFT)
+#define GPIO_Y_SCR_07_0_PR2_RANGE                       18:18
+#define GPIO_Y_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Y_SCR_07_0_PR2_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR1_SHIFT)
+#define GPIO_Y_SCR_07_0_PR1_RANGE                       17:17
+#define GPIO_Y_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Y_SCR_07_0_PR1_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_PR0_SHIFT)
+#define GPIO_Y_SCR_07_0_PR0_RANGE                       16:16
+#define GPIO_Y_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Y_SCR_07_0_PR0_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G7W_SHIFT)
+#define GPIO_Y_SCR_07_0_G7W_RANGE                       15:15
+#define GPIO_Y_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Y_SCR_07_0_G7W_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G6W_SHIFT)
+#define GPIO_Y_SCR_07_0_G6W_RANGE                       14:14
+#define GPIO_Y_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Y_SCR_07_0_G6W_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G5W_SHIFT)
+#define GPIO_Y_SCR_07_0_G5W_RANGE                       13:13
+#define GPIO_Y_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Y_SCR_07_0_G5W_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G4W_SHIFT)
+#define GPIO_Y_SCR_07_0_G4W_RANGE                       12:12
+#define GPIO_Y_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Y_SCR_07_0_G4W_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G3W_SHIFT)
+#define GPIO_Y_SCR_07_0_G3W_RANGE                       11:11
+#define GPIO_Y_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Y_SCR_07_0_G3W_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G2W_SHIFT)
+#define GPIO_Y_SCR_07_0_G2W_RANGE                       10:10
+#define GPIO_Y_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Y_SCR_07_0_G2W_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G1W_SHIFT)
+#define GPIO_Y_SCR_07_0_G1W_RANGE                       9:9
+#define GPIO_Y_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Y_SCR_07_0_G1W_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G0W_SHIFT)
+#define GPIO_Y_SCR_07_0_G0W_RANGE                       8:8
+#define GPIO_Y_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Y_SCR_07_0_G0W_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G7R_SHIFT)
+#define GPIO_Y_SCR_07_0_G7R_RANGE                       7:7
+#define GPIO_Y_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Y_SCR_07_0_G7R_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G6R_SHIFT)
+#define GPIO_Y_SCR_07_0_G6R_RANGE                       6:6
+#define GPIO_Y_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Y_SCR_07_0_G6R_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G5R_SHIFT)
+#define GPIO_Y_SCR_07_0_G5R_RANGE                       5:5
+#define GPIO_Y_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_SCR_07_0_G5R_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G4R_SHIFT)
+#define GPIO_Y_SCR_07_0_G4R_RANGE                       4:4
+#define GPIO_Y_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Y_SCR_07_0_G4R_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G3R_SHIFT)
+#define GPIO_Y_SCR_07_0_G3R_RANGE                       3:3
+#define GPIO_Y_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Y_SCR_07_0_G3R_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G2R_SHIFT)
+#define GPIO_Y_SCR_07_0_G2R_RANGE                       2:2
+#define GPIO_Y_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Y_SCR_07_0_G2R_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G1R_SHIFT)
+#define GPIO_Y_SCR_07_0_G1R_RANGE                       1:1
+#define GPIO_Y_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Y_SCR_07_0_G1R_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Y_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_SCR_07_0_G0R_SHIFT)
+#define GPIO_Y_SCR_07_0_G0R_RANGE                       0:0
+#define GPIO_Y_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_SCR_07_0_G0R_WOFFSET                     0x0
+#define GPIO_Y_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Y_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_VM_00_0
+#define GPIO_Z_VM_00_0                  MK_ADDR_CONST(0x1080)
+#define GPIO_Z_VM_00_0_SECURE                   0x0
+#define GPIO_Z_VM_00_0_DUAL                     0x0
+#define GPIO_Z_VM_00_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_Z_VM_00_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_Z_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_Z_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Z_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM1_SHIFT)
+#define GPIO_Z_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_Z_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Z_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Z_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_Z_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Z_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM2_SHIFT)
+#define GPIO_Z_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_Z_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Z_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Z_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_Z_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Z_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM3_SHIFT)
+#define GPIO_Z_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_Z_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Z_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Z_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_Z_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Z_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM4_SHIFT)
+#define GPIO_Z_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_Z_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Z_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Z_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_Z_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Z_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM5_SHIFT)
+#define GPIO_Z_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_Z_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Z_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Z_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_Z_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Z_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM6_SHIFT)
+#define GPIO_Z_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_Z_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Z_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Z_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_Z_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Z_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM7_SHIFT)
+#define GPIO_Z_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_Z_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Z_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Z_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_Z_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Z_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_00_0_VM8_SHIFT)
+#define GPIO_Z_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_Z_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Z_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Z_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_Z_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_SCR_00_0
+#define GPIO_Z_SCR_00_0                 MK_ADDR_CONST(0x1084)
+#define GPIO_Z_SCR_00_0_SECURE                  0x0
+#define GPIO_Z_SCR_00_0_DUAL                    0x0
+#define GPIO_Z_SCR_00_0_SCR                     0
+#define GPIO_Z_SCR_00_0_SCRREG                  0
+#define GPIO_Z_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_Z_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_Z_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Z_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Z_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_Z_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Z_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Z_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_Z_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_Z_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Z_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Z_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Z_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_Z_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Z_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Z_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Z_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Z_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Z_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR7_SHIFT)
+#define GPIO_Z_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_Z_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR6_SHIFT)
+#define GPIO_Z_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_Z_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR5_SHIFT)
+#define GPIO_Z_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_Z_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR4_SHIFT)
+#define GPIO_Z_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_Z_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR3_SHIFT)
+#define GPIO_Z_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_Z_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR2_SHIFT)
+#define GPIO_Z_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_Z_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR1_SHIFT)
+#define GPIO_Z_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_Z_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_PR0_SHIFT)
+#define GPIO_Z_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_Z_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G7W_SHIFT)
+#define GPIO_Z_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_Z_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G6W_SHIFT)
+#define GPIO_Z_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_Z_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G5W_SHIFT)
+#define GPIO_Z_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_Z_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G4W_SHIFT)
+#define GPIO_Z_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_Z_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G3W_SHIFT)
+#define GPIO_Z_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_Z_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G2W_SHIFT)
+#define GPIO_Z_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_Z_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G1W_SHIFT)
+#define GPIO_Z_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_Z_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G0W_SHIFT)
+#define GPIO_Z_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_Z_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G7R_SHIFT)
+#define GPIO_Z_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_Z_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G6R_SHIFT)
+#define GPIO_Z_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_Z_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G5R_SHIFT)
+#define GPIO_Z_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_Z_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G4R_SHIFT)
+#define GPIO_Z_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_Z_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G3R_SHIFT)
+#define GPIO_Z_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_Z_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G2R_SHIFT)
+#define GPIO_Z_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_Z_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G1R_SHIFT)
+#define GPIO_Z_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_Z_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_00_0_G0R_SHIFT)
+#define GPIO_Z_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_Z_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_Z_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_VM_01_0
+#define GPIO_Z_VM_01_0                  MK_ADDR_CONST(0x1088)
+#define GPIO_Z_VM_01_0_SECURE                   0x0
+#define GPIO_Z_VM_01_0_DUAL                     0x0
+#define GPIO_Z_VM_01_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_Z_VM_01_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_Z_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_Z_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Z_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM1_SHIFT)
+#define GPIO_Z_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_Z_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Z_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Z_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_Z_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Z_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM2_SHIFT)
+#define GPIO_Z_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_Z_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Z_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Z_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_Z_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Z_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM3_SHIFT)
+#define GPIO_Z_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_Z_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Z_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Z_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_Z_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Z_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM4_SHIFT)
+#define GPIO_Z_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_Z_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Z_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Z_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_Z_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Z_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM5_SHIFT)
+#define GPIO_Z_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_Z_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Z_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Z_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_Z_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Z_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM6_SHIFT)
+#define GPIO_Z_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_Z_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Z_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Z_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_Z_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Z_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM7_SHIFT)
+#define GPIO_Z_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_Z_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Z_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Z_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_Z_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Z_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_01_0_VM8_SHIFT)
+#define GPIO_Z_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_Z_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Z_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Z_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_Z_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_SCR_01_0
+#define GPIO_Z_SCR_01_0                 MK_ADDR_CONST(0x108c)
+#define GPIO_Z_SCR_01_0_SECURE                  0x0
+#define GPIO_Z_SCR_01_0_DUAL                    0x0
+#define GPIO_Z_SCR_01_0_SCR                     0
+#define GPIO_Z_SCR_01_0_SCRREG                  0
+#define GPIO_Z_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_Z_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_Z_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Z_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Z_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_Z_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Z_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Z_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_Z_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_Z_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Z_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Z_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Z_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_Z_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Z_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Z_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Z_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Z_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Z_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR7_SHIFT)
+#define GPIO_Z_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_Z_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR6_SHIFT)
+#define GPIO_Z_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_Z_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR5_SHIFT)
+#define GPIO_Z_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_Z_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR4_SHIFT)
+#define GPIO_Z_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_Z_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR3_SHIFT)
+#define GPIO_Z_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_Z_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR2_SHIFT)
+#define GPIO_Z_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_Z_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR1_SHIFT)
+#define GPIO_Z_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_Z_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_PR0_SHIFT)
+#define GPIO_Z_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_Z_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G7W_SHIFT)
+#define GPIO_Z_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_Z_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G6W_SHIFT)
+#define GPIO_Z_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_Z_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G5W_SHIFT)
+#define GPIO_Z_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_Z_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G4W_SHIFT)
+#define GPIO_Z_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_Z_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G3W_SHIFT)
+#define GPIO_Z_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_Z_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G2W_SHIFT)
+#define GPIO_Z_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_Z_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G1W_SHIFT)
+#define GPIO_Z_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_Z_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G0W_SHIFT)
+#define GPIO_Z_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_Z_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G7R_SHIFT)
+#define GPIO_Z_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_Z_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G6R_SHIFT)
+#define GPIO_Z_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_Z_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G5R_SHIFT)
+#define GPIO_Z_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_Z_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G4R_SHIFT)
+#define GPIO_Z_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_Z_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G3R_SHIFT)
+#define GPIO_Z_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_Z_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G2R_SHIFT)
+#define GPIO_Z_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_Z_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G1R_SHIFT)
+#define GPIO_Z_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_Z_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_01_0_G0R_SHIFT)
+#define GPIO_Z_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_Z_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_Z_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_VM_02_0
+#define GPIO_Z_VM_02_0                  MK_ADDR_CONST(0x1090)
+#define GPIO_Z_VM_02_0_SECURE                   0x0
+#define GPIO_Z_VM_02_0_DUAL                     0x0
+#define GPIO_Z_VM_02_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_Z_VM_02_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_Z_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_Z_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Z_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM1_SHIFT)
+#define GPIO_Z_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_Z_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Z_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Z_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_Z_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Z_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM2_SHIFT)
+#define GPIO_Z_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_Z_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Z_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Z_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_Z_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Z_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM3_SHIFT)
+#define GPIO_Z_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_Z_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Z_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Z_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_Z_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Z_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM4_SHIFT)
+#define GPIO_Z_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_Z_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Z_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Z_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_Z_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Z_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM5_SHIFT)
+#define GPIO_Z_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_Z_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Z_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Z_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_Z_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Z_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM6_SHIFT)
+#define GPIO_Z_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_Z_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Z_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Z_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_Z_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Z_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM7_SHIFT)
+#define GPIO_Z_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_Z_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Z_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Z_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_Z_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Z_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_02_0_VM8_SHIFT)
+#define GPIO_Z_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_Z_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Z_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Z_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_Z_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_SCR_02_0
+#define GPIO_Z_SCR_02_0                 MK_ADDR_CONST(0x1094)
+#define GPIO_Z_SCR_02_0_SECURE                  0x0
+#define GPIO_Z_SCR_02_0_DUAL                    0x0
+#define GPIO_Z_SCR_02_0_SCR                     0
+#define GPIO_Z_SCR_02_0_SCRREG                  0
+#define GPIO_Z_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_Z_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_Z_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Z_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Z_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_Z_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Z_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Z_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_Z_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_Z_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Z_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Z_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Z_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_Z_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Z_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Z_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Z_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Z_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Z_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR7_SHIFT)
+#define GPIO_Z_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_Z_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR6_SHIFT)
+#define GPIO_Z_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_Z_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR5_SHIFT)
+#define GPIO_Z_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_Z_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR4_SHIFT)
+#define GPIO_Z_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_Z_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR3_SHIFT)
+#define GPIO_Z_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_Z_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR2_SHIFT)
+#define GPIO_Z_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_Z_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR1_SHIFT)
+#define GPIO_Z_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_Z_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_PR0_SHIFT)
+#define GPIO_Z_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_Z_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G7W_SHIFT)
+#define GPIO_Z_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_Z_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G6W_SHIFT)
+#define GPIO_Z_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_Z_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G5W_SHIFT)
+#define GPIO_Z_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_Z_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G4W_SHIFT)
+#define GPIO_Z_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_Z_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G3W_SHIFT)
+#define GPIO_Z_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_Z_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G2W_SHIFT)
+#define GPIO_Z_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_Z_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G1W_SHIFT)
+#define GPIO_Z_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_Z_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G0W_SHIFT)
+#define GPIO_Z_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_Z_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G7R_SHIFT)
+#define GPIO_Z_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_Z_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G6R_SHIFT)
+#define GPIO_Z_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_Z_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G5R_SHIFT)
+#define GPIO_Z_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_Z_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G4R_SHIFT)
+#define GPIO_Z_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_Z_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G3R_SHIFT)
+#define GPIO_Z_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_Z_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G2R_SHIFT)
+#define GPIO_Z_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_Z_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G1R_SHIFT)
+#define GPIO_Z_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_Z_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_02_0_G0R_SHIFT)
+#define GPIO_Z_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_Z_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_Z_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_VM_03_0
+#define GPIO_Z_VM_03_0                  MK_ADDR_CONST(0x1098)
+#define GPIO_Z_VM_03_0_SECURE                   0x0
+#define GPIO_Z_VM_03_0_DUAL                     0x0
+#define GPIO_Z_VM_03_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_Z_VM_03_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_Z_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_Z_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Z_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM1_SHIFT)
+#define GPIO_Z_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_Z_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Z_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Z_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_Z_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Z_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM2_SHIFT)
+#define GPIO_Z_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_Z_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Z_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Z_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_Z_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Z_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM3_SHIFT)
+#define GPIO_Z_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_Z_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Z_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Z_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_Z_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Z_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM4_SHIFT)
+#define GPIO_Z_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_Z_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Z_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Z_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_Z_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Z_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM5_SHIFT)
+#define GPIO_Z_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_Z_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Z_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Z_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_Z_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Z_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM6_SHIFT)
+#define GPIO_Z_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_Z_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Z_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Z_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_Z_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Z_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM7_SHIFT)
+#define GPIO_Z_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_Z_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Z_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Z_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_Z_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Z_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_03_0_VM8_SHIFT)
+#define GPIO_Z_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_Z_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Z_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Z_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_Z_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_SCR_03_0
+#define GPIO_Z_SCR_03_0                 MK_ADDR_CONST(0x109c)
+#define GPIO_Z_SCR_03_0_SECURE                  0x0
+#define GPIO_Z_SCR_03_0_DUAL                    0x0
+#define GPIO_Z_SCR_03_0_SCR                     0
+#define GPIO_Z_SCR_03_0_SCRREG                  0
+#define GPIO_Z_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_Z_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_Z_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Z_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Z_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_Z_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Z_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Z_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_Z_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_Z_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Z_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Z_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Z_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_Z_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Z_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Z_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Z_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Z_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Z_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR7_SHIFT)
+#define GPIO_Z_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_Z_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR6_SHIFT)
+#define GPIO_Z_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_Z_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR5_SHIFT)
+#define GPIO_Z_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_Z_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR4_SHIFT)
+#define GPIO_Z_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_Z_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR3_SHIFT)
+#define GPIO_Z_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_Z_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR2_SHIFT)
+#define GPIO_Z_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_Z_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR1_SHIFT)
+#define GPIO_Z_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_Z_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_PR0_SHIFT)
+#define GPIO_Z_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_Z_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G7W_SHIFT)
+#define GPIO_Z_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_Z_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G6W_SHIFT)
+#define GPIO_Z_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_Z_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G5W_SHIFT)
+#define GPIO_Z_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_Z_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G4W_SHIFT)
+#define GPIO_Z_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_Z_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G3W_SHIFT)
+#define GPIO_Z_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_Z_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G2W_SHIFT)
+#define GPIO_Z_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_Z_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G1W_SHIFT)
+#define GPIO_Z_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_Z_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G0W_SHIFT)
+#define GPIO_Z_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_Z_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G7R_SHIFT)
+#define GPIO_Z_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_Z_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G6R_SHIFT)
+#define GPIO_Z_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_Z_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G5R_SHIFT)
+#define GPIO_Z_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_Z_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G4R_SHIFT)
+#define GPIO_Z_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_Z_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G3R_SHIFT)
+#define GPIO_Z_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_Z_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G2R_SHIFT)
+#define GPIO_Z_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_Z_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G1R_SHIFT)
+#define GPIO_Z_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_Z_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_03_0_G0R_SHIFT)
+#define GPIO_Z_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_Z_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_Z_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_VM_04_0
+#define GPIO_Z_VM_04_0                  MK_ADDR_CONST(0x10a0)
+#define GPIO_Z_VM_04_0_SECURE                   0x0
+#define GPIO_Z_VM_04_0_DUAL                     0x0
+#define GPIO_Z_VM_04_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_Z_VM_04_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_Z_VM_04_0_WORD_COUNT                       0x1
+#define GPIO_Z_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Z_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM1_SHIFT)
+#define GPIO_Z_VM_04_0_VM1_RANGE                        1:0
+#define GPIO_Z_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Z_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Z_VM_04_0_VM1_WOFFSET                      0x0
+#define GPIO_Z_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Z_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM2_SHIFT)
+#define GPIO_Z_VM_04_0_VM2_RANGE                        3:2
+#define GPIO_Z_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Z_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Z_VM_04_0_VM2_WOFFSET                      0x0
+#define GPIO_Z_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Z_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM3_SHIFT)
+#define GPIO_Z_VM_04_0_VM3_RANGE                        5:4
+#define GPIO_Z_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Z_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Z_VM_04_0_VM3_WOFFSET                      0x0
+#define GPIO_Z_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Z_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM4_SHIFT)
+#define GPIO_Z_VM_04_0_VM4_RANGE                        7:6
+#define GPIO_Z_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Z_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Z_VM_04_0_VM4_WOFFSET                      0x0
+#define GPIO_Z_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Z_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM5_SHIFT)
+#define GPIO_Z_VM_04_0_VM5_RANGE                        9:8
+#define GPIO_Z_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Z_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Z_VM_04_0_VM5_WOFFSET                      0x0
+#define GPIO_Z_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Z_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM6_SHIFT)
+#define GPIO_Z_VM_04_0_VM6_RANGE                        11:10
+#define GPIO_Z_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Z_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Z_VM_04_0_VM6_WOFFSET                      0x0
+#define GPIO_Z_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Z_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM7_SHIFT)
+#define GPIO_Z_VM_04_0_VM7_RANGE                        13:12
+#define GPIO_Z_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Z_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Z_VM_04_0_VM7_WOFFSET                      0x0
+#define GPIO_Z_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Z_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_04_0_VM8_SHIFT)
+#define GPIO_Z_VM_04_0_VM8_RANGE                        15:14
+#define GPIO_Z_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Z_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Z_VM_04_0_VM8_WOFFSET                      0x0
+#define GPIO_Z_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_SCR_04_0
+#define GPIO_Z_SCR_04_0                 MK_ADDR_CONST(0x10a4)
+#define GPIO_Z_SCR_04_0_SECURE                  0x0
+#define GPIO_Z_SCR_04_0_DUAL                    0x0
+#define GPIO_Z_SCR_04_0_SCR                     0
+#define GPIO_Z_SCR_04_0_SCRREG                  0
+#define GPIO_Z_SCR_04_0_WORD_COUNT                      0x1
+#define GPIO_Z_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_Z_SCR_04_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Z_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_04_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Z_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_Z_SCR_04_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Z_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_04_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Z_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_Z_SCR_04_0_SEC_REN_RANGE                   27:27
+#define GPIO_Z_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_04_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Z_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Z_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Z_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_Z_SCR_04_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Z_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Z_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Z_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Z_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Z_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR7_SHIFT)
+#define GPIO_Z_SCR_04_0_PR7_RANGE                       23:23
+#define GPIO_Z_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_04_0_PR7_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR6_SHIFT)
+#define GPIO_Z_SCR_04_0_PR6_RANGE                       22:22
+#define GPIO_Z_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_04_0_PR6_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR5_SHIFT)
+#define GPIO_Z_SCR_04_0_PR5_RANGE                       21:21
+#define GPIO_Z_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_04_0_PR5_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR4_SHIFT)
+#define GPIO_Z_SCR_04_0_PR4_RANGE                       20:20
+#define GPIO_Z_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_04_0_PR4_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR3_SHIFT)
+#define GPIO_Z_SCR_04_0_PR3_RANGE                       19:19
+#define GPIO_Z_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_04_0_PR3_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR2_SHIFT)
+#define GPIO_Z_SCR_04_0_PR2_RANGE                       18:18
+#define GPIO_Z_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_04_0_PR2_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR1_SHIFT)
+#define GPIO_Z_SCR_04_0_PR1_RANGE                       17:17
+#define GPIO_Z_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_04_0_PR1_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_PR0_SHIFT)
+#define GPIO_Z_SCR_04_0_PR0_RANGE                       16:16
+#define GPIO_Z_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_04_0_PR0_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G7W_SHIFT)
+#define GPIO_Z_SCR_04_0_G7W_RANGE                       15:15
+#define GPIO_Z_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_04_0_G7W_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G6W_SHIFT)
+#define GPIO_Z_SCR_04_0_G6W_RANGE                       14:14
+#define GPIO_Z_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_04_0_G6W_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G5W_SHIFT)
+#define GPIO_Z_SCR_04_0_G5W_RANGE                       13:13
+#define GPIO_Z_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_04_0_G5W_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G4W_SHIFT)
+#define GPIO_Z_SCR_04_0_G4W_RANGE                       12:12
+#define GPIO_Z_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_04_0_G4W_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G3W_SHIFT)
+#define GPIO_Z_SCR_04_0_G3W_RANGE                       11:11
+#define GPIO_Z_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_04_0_G3W_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G2W_SHIFT)
+#define GPIO_Z_SCR_04_0_G2W_RANGE                       10:10
+#define GPIO_Z_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_04_0_G2W_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G1W_SHIFT)
+#define GPIO_Z_SCR_04_0_G1W_RANGE                       9:9
+#define GPIO_Z_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_04_0_G1W_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G0W_SHIFT)
+#define GPIO_Z_SCR_04_0_G0W_RANGE                       8:8
+#define GPIO_Z_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_04_0_G0W_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G7R_SHIFT)
+#define GPIO_Z_SCR_04_0_G7R_RANGE                       7:7
+#define GPIO_Z_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_04_0_G7R_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G6R_SHIFT)
+#define GPIO_Z_SCR_04_0_G6R_RANGE                       6:6
+#define GPIO_Z_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_04_0_G6R_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G5R_SHIFT)
+#define GPIO_Z_SCR_04_0_G5R_RANGE                       5:5
+#define GPIO_Z_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_04_0_G5R_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G4R_SHIFT)
+#define GPIO_Z_SCR_04_0_G4R_RANGE                       4:4
+#define GPIO_Z_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_04_0_G4R_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G3R_SHIFT)
+#define GPIO_Z_SCR_04_0_G3R_RANGE                       3:3
+#define GPIO_Z_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_04_0_G3R_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G2R_SHIFT)
+#define GPIO_Z_SCR_04_0_G2R_RANGE                       2:2
+#define GPIO_Z_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_04_0_G2R_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G1R_SHIFT)
+#define GPIO_Z_SCR_04_0_G1R_RANGE                       1:1
+#define GPIO_Z_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_04_0_G1R_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_04_0_G0R_SHIFT)
+#define GPIO_Z_SCR_04_0_G0R_RANGE                       0:0
+#define GPIO_Z_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_04_0_G0R_WOFFSET                     0x0
+#define GPIO_Z_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_VM_05_0
+#define GPIO_Z_VM_05_0                  MK_ADDR_CONST(0x10a8)
+#define GPIO_Z_VM_05_0_SECURE                   0x0
+#define GPIO_Z_VM_05_0_DUAL                     0x0
+#define GPIO_Z_VM_05_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_Z_VM_05_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_Z_VM_05_0_WORD_COUNT                       0x1
+#define GPIO_Z_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Z_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM1_SHIFT)
+#define GPIO_Z_VM_05_0_VM1_RANGE                        1:0
+#define GPIO_Z_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Z_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Z_VM_05_0_VM1_WOFFSET                      0x0
+#define GPIO_Z_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Z_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM2_SHIFT)
+#define GPIO_Z_VM_05_0_VM2_RANGE                        3:2
+#define GPIO_Z_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Z_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Z_VM_05_0_VM2_WOFFSET                      0x0
+#define GPIO_Z_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Z_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM3_SHIFT)
+#define GPIO_Z_VM_05_0_VM3_RANGE                        5:4
+#define GPIO_Z_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Z_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Z_VM_05_0_VM3_WOFFSET                      0x0
+#define GPIO_Z_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Z_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM4_SHIFT)
+#define GPIO_Z_VM_05_0_VM4_RANGE                        7:6
+#define GPIO_Z_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Z_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Z_VM_05_0_VM4_WOFFSET                      0x0
+#define GPIO_Z_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Z_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM5_SHIFT)
+#define GPIO_Z_VM_05_0_VM5_RANGE                        9:8
+#define GPIO_Z_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Z_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Z_VM_05_0_VM5_WOFFSET                      0x0
+#define GPIO_Z_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Z_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM6_SHIFT)
+#define GPIO_Z_VM_05_0_VM6_RANGE                        11:10
+#define GPIO_Z_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Z_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Z_VM_05_0_VM6_WOFFSET                      0x0
+#define GPIO_Z_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Z_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM7_SHIFT)
+#define GPIO_Z_VM_05_0_VM7_RANGE                        13:12
+#define GPIO_Z_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Z_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Z_VM_05_0_VM7_WOFFSET                      0x0
+#define GPIO_Z_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Z_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_05_0_VM8_SHIFT)
+#define GPIO_Z_VM_05_0_VM8_RANGE                        15:14
+#define GPIO_Z_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Z_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Z_VM_05_0_VM8_WOFFSET                      0x0
+#define GPIO_Z_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_SCR_05_0
+#define GPIO_Z_SCR_05_0                 MK_ADDR_CONST(0x10ac)
+#define GPIO_Z_SCR_05_0_SECURE                  0x0
+#define GPIO_Z_SCR_05_0_DUAL                    0x0
+#define GPIO_Z_SCR_05_0_SCR                     0
+#define GPIO_Z_SCR_05_0_SCRREG                  0
+#define GPIO_Z_SCR_05_0_WORD_COUNT                      0x1
+#define GPIO_Z_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_Z_SCR_05_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Z_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_05_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Z_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_Z_SCR_05_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Z_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_05_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Z_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_Z_SCR_05_0_SEC_REN_RANGE                   27:27
+#define GPIO_Z_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_05_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Z_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Z_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Z_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_Z_SCR_05_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Z_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Z_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Z_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Z_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Z_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR7_SHIFT)
+#define GPIO_Z_SCR_05_0_PR7_RANGE                       23:23
+#define GPIO_Z_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_05_0_PR7_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR6_SHIFT)
+#define GPIO_Z_SCR_05_0_PR6_RANGE                       22:22
+#define GPIO_Z_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_05_0_PR6_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR5_SHIFT)
+#define GPIO_Z_SCR_05_0_PR5_RANGE                       21:21
+#define GPIO_Z_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_05_0_PR5_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR4_SHIFT)
+#define GPIO_Z_SCR_05_0_PR4_RANGE                       20:20
+#define GPIO_Z_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_05_0_PR4_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR3_SHIFT)
+#define GPIO_Z_SCR_05_0_PR3_RANGE                       19:19
+#define GPIO_Z_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_05_0_PR3_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR2_SHIFT)
+#define GPIO_Z_SCR_05_0_PR2_RANGE                       18:18
+#define GPIO_Z_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_05_0_PR2_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR1_SHIFT)
+#define GPIO_Z_SCR_05_0_PR1_RANGE                       17:17
+#define GPIO_Z_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_05_0_PR1_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_PR0_SHIFT)
+#define GPIO_Z_SCR_05_0_PR0_RANGE                       16:16
+#define GPIO_Z_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_05_0_PR0_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G7W_SHIFT)
+#define GPIO_Z_SCR_05_0_G7W_RANGE                       15:15
+#define GPIO_Z_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_05_0_G7W_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G6W_SHIFT)
+#define GPIO_Z_SCR_05_0_G6W_RANGE                       14:14
+#define GPIO_Z_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_05_0_G6W_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G5W_SHIFT)
+#define GPIO_Z_SCR_05_0_G5W_RANGE                       13:13
+#define GPIO_Z_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_05_0_G5W_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G4W_SHIFT)
+#define GPIO_Z_SCR_05_0_G4W_RANGE                       12:12
+#define GPIO_Z_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_05_0_G4W_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G3W_SHIFT)
+#define GPIO_Z_SCR_05_0_G3W_RANGE                       11:11
+#define GPIO_Z_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_05_0_G3W_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G2W_SHIFT)
+#define GPIO_Z_SCR_05_0_G2W_RANGE                       10:10
+#define GPIO_Z_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_05_0_G2W_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G1W_SHIFT)
+#define GPIO_Z_SCR_05_0_G1W_RANGE                       9:9
+#define GPIO_Z_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_05_0_G1W_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G0W_SHIFT)
+#define GPIO_Z_SCR_05_0_G0W_RANGE                       8:8
+#define GPIO_Z_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_05_0_G0W_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G7R_SHIFT)
+#define GPIO_Z_SCR_05_0_G7R_RANGE                       7:7
+#define GPIO_Z_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_05_0_G7R_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G6R_SHIFT)
+#define GPIO_Z_SCR_05_0_G6R_RANGE                       6:6
+#define GPIO_Z_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_05_0_G6R_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G5R_SHIFT)
+#define GPIO_Z_SCR_05_0_G5R_RANGE                       5:5
+#define GPIO_Z_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_05_0_G5R_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G4R_SHIFT)
+#define GPIO_Z_SCR_05_0_G4R_RANGE                       4:4
+#define GPIO_Z_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_05_0_G4R_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G3R_SHIFT)
+#define GPIO_Z_SCR_05_0_G3R_RANGE                       3:3
+#define GPIO_Z_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_05_0_G3R_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G2R_SHIFT)
+#define GPIO_Z_SCR_05_0_G2R_RANGE                       2:2
+#define GPIO_Z_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_05_0_G2R_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G1R_SHIFT)
+#define GPIO_Z_SCR_05_0_G1R_RANGE                       1:1
+#define GPIO_Z_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_05_0_G1R_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_05_0_G0R_SHIFT)
+#define GPIO_Z_SCR_05_0_G0R_RANGE                       0:0
+#define GPIO_Z_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_05_0_G0R_WOFFSET                     0x0
+#define GPIO_Z_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_VM_06_0
+#define GPIO_Z_VM_06_0                  MK_ADDR_CONST(0x10b0)
+#define GPIO_Z_VM_06_0_SECURE                   0x0
+#define GPIO_Z_VM_06_0_DUAL                     0x0
+#define GPIO_Z_VM_06_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_Z_VM_06_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_Z_VM_06_0_WORD_COUNT                       0x1
+#define GPIO_Z_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Z_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM1_SHIFT)
+#define GPIO_Z_VM_06_0_VM1_RANGE                        1:0
+#define GPIO_Z_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Z_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Z_VM_06_0_VM1_WOFFSET                      0x0
+#define GPIO_Z_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Z_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM2_SHIFT)
+#define GPIO_Z_VM_06_0_VM2_RANGE                        3:2
+#define GPIO_Z_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Z_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Z_VM_06_0_VM2_WOFFSET                      0x0
+#define GPIO_Z_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Z_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM3_SHIFT)
+#define GPIO_Z_VM_06_0_VM3_RANGE                        5:4
+#define GPIO_Z_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Z_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Z_VM_06_0_VM3_WOFFSET                      0x0
+#define GPIO_Z_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Z_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM4_SHIFT)
+#define GPIO_Z_VM_06_0_VM4_RANGE                        7:6
+#define GPIO_Z_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Z_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Z_VM_06_0_VM4_WOFFSET                      0x0
+#define GPIO_Z_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Z_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM5_SHIFT)
+#define GPIO_Z_VM_06_0_VM5_RANGE                        9:8
+#define GPIO_Z_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Z_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Z_VM_06_0_VM5_WOFFSET                      0x0
+#define GPIO_Z_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Z_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM6_SHIFT)
+#define GPIO_Z_VM_06_0_VM6_RANGE                        11:10
+#define GPIO_Z_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Z_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Z_VM_06_0_VM6_WOFFSET                      0x0
+#define GPIO_Z_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Z_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM7_SHIFT)
+#define GPIO_Z_VM_06_0_VM7_RANGE                        13:12
+#define GPIO_Z_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Z_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Z_VM_06_0_VM7_WOFFSET                      0x0
+#define GPIO_Z_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Z_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_06_0_VM8_SHIFT)
+#define GPIO_Z_VM_06_0_VM8_RANGE                        15:14
+#define GPIO_Z_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Z_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Z_VM_06_0_VM8_WOFFSET                      0x0
+#define GPIO_Z_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_SCR_06_0
+#define GPIO_Z_SCR_06_0                 MK_ADDR_CONST(0x10b4)
+#define GPIO_Z_SCR_06_0_SECURE                  0x0
+#define GPIO_Z_SCR_06_0_DUAL                    0x0
+#define GPIO_Z_SCR_06_0_SCR                     0
+#define GPIO_Z_SCR_06_0_SCRREG                  0
+#define GPIO_Z_SCR_06_0_WORD_COUNT                      0x1
+#define GPIO_Z_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_SEC_LCK_SHIFT)
+#define GPIO_Z_SCR_06_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Z_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_06_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Z_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_SEC_WEN_SHIFT)
+#define GPIO_Z_SCR_06_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Z_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_06_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Z_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_SEC_REN_SHIFT)
+#define GPIO_Z_SCR_06_0_SEC_REN_RANGE                   27:27
+#define GPIO_Z_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_06_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Z_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Z_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Z_SCR_06_0_SEC_OWNER_SHIFT)
+#define GPIO_Z_SCR_06_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Z_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Z_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Z_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Z_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Z_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR7_SHIFT)
+#define GPIO_Z_SCR_06_0_PR7_RANGE                       23:23
+#define GPIO_Z_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_06_0_PR7_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR6_SHIFT)
+#define GPIO_Z_SCR_06_0_PR6_RANGE                       22:22
+#define GPIO_Z_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_06_0_PR6_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR5_SHIFT)
+#define GPIO_Z_SCR_06_0_PR5_RANGE                       21:21
+#define GPIO_Z_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_06_0_PR5_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR4_SHIFT)
+#define GPIO_Z_SCR_06_0_PR4_RANGE                       20:20
+#define GPIO_Z_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_06_0_PR4_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR3_SHIFT)
+#define GPIO_Z_SCR_06_0_PR3_RANGE                       19:19
+#define GPIO_Z_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_06_0_PR3_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR2_SHIFT)
+#define GPIO_Z_SCR_06_0_PR2_RANGE                       18:18
+#define GPIO_Z_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_06_0_PR2_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR1_SHIFT)
+#define GPIO_Z_SCR_06_0_PR1_RANGE                       17:17
+#define GPIO_Z_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_06_0_PR1_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_PR0_SHIFT)
+#define GPIO_Z_SCR_06_0_PR0_RANGE                       16:16
+#define GPIO_Z_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_06_0_PR0_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G7W_SHIFT)
+#define GPIO_Z_SCR_06_0_G7W_RANGE                       15:15
+#define GPIO_Z_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_06_0_G7W_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G6W_SHIFT)
+#define GPIO_Z_SCR_06_0_G6W_RANGE                       14:14
+#define GPIO_Z_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_06_0_G6W_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G5W_SHIFT)
+#define GPIO_Z_SCR_06_0_G5W_RANGE                       13:13
+#define GPIO_Z_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_06_0_G5W_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G4W_SHIFT)
+#define GPIO_Z_SCR_06_0_G4W_RANGE                       12:12
+#define GPIO_Z_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_06_0_G4W_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G3W_SHIFT)
+#define GPIO_Z_SCR_06_0_G3W_RANGE                       11:11
+#define GPIO_Z_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_06_0_G3W_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G2W_SHIFT)
+#define GPIO_Z_SCR_06_0_G2W_RANGE                       10:10
+#define GPIO_Z_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_06_0_G2W_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G1W_SHIFT)
+#define GPIO_Z_SCR_06_0_G1W_RANGE                       9:9
+#define GPIO_Z_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_06_0_G1W_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G0W_SHIFT)
+#define GPIO_Z_SCR_06_0_G0W_RANGE                       8:8
+#define GPIO_Z_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_06_0_G0W_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G7R_SHIFT)
+#define GPIO_Z_SCR_06_0_G7R_RANGE                       7:7
+#define GPIO_Z_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_06_0_G7R_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G6R_SHIFT)
+#define GPIO_Z_SCR_06_0_G6R_RANGE                       6:6
+#define GPIO_Z_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_06_0_G6R_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G5R_SHIFT)
+#define GPIO_Z_SCR_06_0_G5R_RANGE                       5:5
+#define GPIO_Z_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_06_0_G5R_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G4R_SHIFT)
+#define GPIO_Z_SCR_06_0_G4R_RANGE                       4:4
+#define GPIO_Z_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_06_0_G4R_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G3R_SHIFT)
+#define GPIO_Z_SCR_06_0_G3R_RANGE                       3:3
+#define GPIO_Z_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_06_0_G3R_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G2R_SHIFT)
+#define GPIO_Z_SCR_06_0_G2R_RANGE                       2:2
+#define GPIO_Z_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_06_0_G2R_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G1R_SHIFT)
+#define GPIO_Z_SCR_06_0_G1R_RANGE                       1:1
+#define GPIO_Z_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_06_0_G1R_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_06_0_G0R_SHIFT)
+#define GPIO_Z_SCR_06_0_G0R_RANGE                       0:0
+#define GPIO_Z_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_06_0_G0R_WOFFSET                     0x0
+#define GPIO_Z_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_VM_07_0
+#define GPIO_Z_VM_07_0                  MK_ADDR_CONST(0x10b8)
+#define GPIO_Z_VM_07_0_SECURE                   0x0
+#define GPIO_Z_VM_07_0_DUAL                     0x0
+#define GPIO_Z_VM_07_0_SCR                      GPIO_CTL1_VM_SCR_0
+#define GPIO_Z_VM_07_0_SCRREG                   GPIO_CTL1_VM_SCR_0
+#define GPIO_Z_VM_07_0_WORD_COUNT                       0x1
+#define GPIO_Z_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Z_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Z_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM1_SHIFT)
+#define GPIO_Z_VM_07_0_VM1_RANGE                        1:0
+#define GPIO_Z_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Z_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Z_VM_07_0_VM1_WOFFSET                      0x0
+#define GPIO_Z_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Z_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM2_SHIFT)
+#define GPIO_Z_VM_07_0_VM2_RANGE                        3:2
+#define GPIO_Z_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Z_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Z_VM_07_0_VM2_WOFFSET                      0x0
+#define GPIO_Z_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Z_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM3_SHIFT)
+#define GPIO_Z_VM_07_0_VM3_RANGE                        5:4
+#define GPIO_Z_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Z_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Z_VM_07_0_VM3_WOFFSET                      0x0
+#define GPIO_Z_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Z_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM4_SHIFT)
+#define GPIO_Z_VM_07_0_VM4_RANGE                        7:6
+#define GPIO_Z_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Z_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Z_VM_07_0_VM4_WOFFSET                      0x0
+#define GPIO_Z_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Z_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM5_SHIFT)
+#define GPIO_Z_VM_07_0_VM5_RANGE                        9:8
+#define GPIO_Z_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Z_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Z_VM_07_0_VM5_WOFFSET                      0x0
+#define GPIO_Z_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Z_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM6_SHIFT)
+#define GPIO_Z_VM_07_0_VM6_RANGE                        11:10
+#define GPIO_Z_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Z_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Z_VM_07_0_VM6_WOFFSET                      0x0
+#define GPIO_Z_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Z_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM7_SHIFT)
+#define GPIO_Z_VM_07_0_VM7_RANGE                        13:12
+#define GPIO_Z_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Z_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Z_VM_07_0_VM7_WOFFSET                      0x0
+#define GPIO_Z_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Z_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Z_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Z_VM_07_0_VM8_SHIFT)
+#define GPIO_Z_VM_07_0_VM8_RANGE                        15:14
+#define GPIO_Z_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Z_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Z_VM_07_0_VM8_WOFFSET                      0x0
+#define GPIO_Z_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Z_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_SCR_07_0
+#define GPIO_Z_SCR_07_0                 MK_ADDR_CONST(0x10bc)
+#define GPIO_Z_SCR_07_0_SECURE                  0x0
+#define GPIO_Z_SCR_07_0_DUAL                    0x0
+#define GPIO_Z_SCR_07_0_SCR                     0
+#define GPIO_Z_SCR_07_0_SCRREG                  0
+#define GPIO_Z_SCR_07_0_WORD_COUNT                      0x1
+#define GPIO_Z_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Z_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_SEC_LCK_SHIFT)
+#define GPIO_Z_SCR_07_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Z_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Z_SCR_07_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Z_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_SEC_WEN_SHIFT)
+#define GPIO_Z_SCR_07_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Z_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Z_SCR_07_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Z_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_SEC_REN_SHIFT)
+#define GPIO_Z_SCR_07_0_SEC_REN_RANGE                   27:27
+#define GPIO_Z_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Z_SCR_07_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Z_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Z_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Z_SCR_07_0_SEC_OWNER_SHIFT)
+#define GPIO_Z_SCR_07_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Z_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Z_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Z_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Z_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Z_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR7_SHIFT)
+#define GPIO_Z_SCR_07_0_PR7_RANGE                       23:23
+#define GPIO_Z_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Z_SCR_07_0_PR7_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR6_SHIFT)
+#define GPIO_Z_SCR_07_0_PR6_RANGE                       22:22
+#define GPIO_Z_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Z_SCR_07_0_PR6_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR5_SHIFT)
+#define GPIO_Z_SCR_07_0_PR5_RANGE                       21:21
+#define GPIO_Z_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Z_SCR_07_0_PR5_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR4_SHIFT)
+#define GPIO_Z_SCR_07_0_PR4_RANGE                       20:20
+#define GPIO_Z_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Z_SCR_07_0_PR4_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR3_SHIFT)
+#define GPIO_Z_SCR_07_0_PR3_RANGE                       19:19
+#define GPIO_Z_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Z_SCR_07_0_PR3_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR2_SHIFT)
+#define GPIO_Z_SCR_07_0_PR2_RANGE                       18:18
+#define GPIO_Z_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Z_SCR_07_0_PR2_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR1_SHIFT)
+#define GPIO_Z_SCR_07_0_PR1_RANGE                       17:17
+#define GPIO_Z_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Z_SCR_07_0_PR1_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_PR0_SHIFT)
+#define GPIO_Z_SCR_07_0_PR0_RANGE                       16:16
+#define GPIO_Z_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Z_SCR_07_0_PR0_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G7W_SHIFT)
+#define GPIO_Z_SCR_07_0_G7W_RANGE                       15:15
+#define GPIO_Z_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Z_SCR_07_0_G7W_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G6W_SHIFT)
+#define GPIO_Z_SCR_07_0_G6W_RANGE                       14:14
+#define GPIO_Z_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Z_SCR_07_0_G6W_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G5W_SHIFT)
+#define GPIO_Z_SCR_07_0_G5W_RANGE                       13:13
+#define GPIO_Z_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Z_SCR_07_0_G5W_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G4W_SHIFT)
+#define GPIO_Z_SCR_07_0_G4W_RANGE                       12:12
+#define GPIO_Z_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Z_SCR_07_0_G4W_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G3W_SHIFT)
+#define GPIO_Z_SCR_07_0_G3W_RANGE                       11:11
+#define GPIO_Z_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Z_SCR_07_0_G3W_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G2W_SHIFT)
+#define GPIO_Z_SCR_07_0_G2W_RANGE                       10:10
+#define GPIO_Z_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Z_SCR_07_0_G2W_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G1W_SHIFT)
+#define GPIO_Z_SCR_07_0_G1W_RANGE                       9:9
+#define GPIO_Z_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Z_SCR_07_0_G1W_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G0W_SHIFT)
+#define GPIO_Z_SCR_07_0_G0W_RANGE                       8:8
+#define GPIO_Z_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Z_SCR_07_0_G0W_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G7R_SHIFT)
+#define GPIO_Z_SCR_07_0_G7R_RANGE                       7:7
+#define GPIO_Z_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Z_SCR_07_0_G7R_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G6R_SHIFT)
+#define GPIO_Z_SCR_07_0_G6R_RANGE                       6:6
+#define GPIO_Z_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Z_SCR_07_0_G6R_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G5R_SHIFT)
+#define GPIO_Z_SCR_07_0_G5R_RANGE                       5:5
+#define GPIO_Z_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_SCR_07_0_G5R_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G4R_SHIFT)
+#define GPIO_Z_SCR_07_0_G4R_RANGE                       4:4
+#define GPIO_Z_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Z_SCR_07_0_G4R_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G3R_SHIFT)
+#define GPIO_Z_SCR_07_0_G3R_RANGE                       3:3
+#define GPIO_Z_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Z_SCR_07_0_G3R_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G2R_SHIFT)
+#define GPIO_Z_SCR_07_0_G2R_RANGE                       2:2
+#define GPIO_Z_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Z_SCR_07_0_G2R_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G1R_SHIFT)
+#define GPIO_Z_SCR_07_0_G1R_RANGE                       1:1
+#define GPIO_Z_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Z_SCR_07_0_G1R_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Z_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_SCR_07_0_G0R_SHIFT)
+#define GPIO_Z_SCR_07_0_G0R_RANGE                       0:0
+#define GPIO_Z_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_SCR_07_0_G0R_WOFFSET                     0x0
+#define GPIO_Z_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Z_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL1_VM_SCR_0
+#define GPIO_CTL1_VM_SCR_0                      MK_ADDR_CONST(0x1800)
+#define GPIO_CTL1_VM_SCR_0_SECURE                       0x0
+#define GPIO_CTL1_VM_SCR_0_DUAL                         0x0
+#define GPIO_CTL1_VM_SCR_0_SCR                  0
+#define GPIO_CTL1_VM_SCR_0_SCRREG                       0
+#define GPIO_CTL1_VM_SCR_0_WORD_COUNT                   0x1
+#define GPIO_CTL1_VM_SCR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL1_VM_SCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL1_VM_SCR_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL1_VM_SCR_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
+#define GPIO_CTL1_VM_SCR_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_SEC_LCK_RANGE                        29:29
+#define GPIO_CTL1_VM_SCR_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
+#define GPIO_CTL1_VM_SCR_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
+#define GPIO_CTL1_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
+#define GPIO_CTL1_VM_SCR_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
+#define GPIO_CTL1_VM_SCR_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_SEC_WEN_RANGE                        28:28
+#define GPIO_CTL1_VM_SCR_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
+#define GPIO_CTL1_VM_SCR_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
+#define GPIO_CTL1_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
+#define GPIO_CTL1_VM_SCR_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
+#define GPIO_CTL1_VM_SCR_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_SEC_REN_RANGE                        27:27
+#define GPIO_CTL1_VM_SCR_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
+#define GPIO_CTL1_VM_SCR_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
+#define GPIO_CTL1_VM_SCR_0_SEC_REN_WOFFSET                      0x0
+#define GPIO_CTL1_VM_SCR_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
+#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, GPIO_CTL1_VM_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_RANGE                      26:24
+#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
+#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
+#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
+#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
+#define GPIO_CTL1_VM_SCR_0_PR7_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR7_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_PR7_RANGE                    23:23
+#define GPIO_CTL1_VM_SCR_0_PR7_MSB                      MK_SHIFT_CONST(23)
+#define GPIO_CTL1_VM_SCR_0_PR7_LSB                      MK_SHIFT_CONST(23)
+#define GPIO_CTL1_VM_SCR_0_PR7_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
+#define GPIO_CTL1_VM_SCR_0_PR6_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR6_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_PR6_RANGE                    22:22
+#define GPIO_CTL1_VM_SCR_0_PR6_MSB                      MK_SHIFT_CONST(22)
+#define GPIO_CTL1_VM_SCR_0_PR6_LSB                      MK_SHIFT_CONST(22)
+#define GPIO_CTL1_VM_SCR_0_PR6_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
+#define GPIO_CTL1_VM_SCR_0_PR5_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR5_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_PR5_RANGE                    21:21
+#define GPIO_CTL1_VM_SCR_0_PR5_MSB                      MK_SHIFT_CONST(21)
+#define GPIO_CTL1_VM_SCR_0_PR5_LSB                      MK_SHIFT_CONST(21)
+#define GPIO_CTL1_VM_SCR_0_PR5_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
+#define GPIO_CTL1_VM_SCR_0_PR4_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR4_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_PR4_RANGE                    20:20
+#define GPIO_CTL1_VM_SCR_0_PR4_MSB                      MK_SHIFT_CONST(20)
+#define GPIO_CTL1_VM_SCR_0_PR4_LSB                      MK_SHIFT_CONST(20)
+#define GPIO_CTL1_VM_SCR_0_PR4_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
+#define GPIO_CTL1_VM_SCR_0_PR3_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR3_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_PR3_RANGE                    19:19
+#define GPIO_CTL1_VM_SCR_0_PR3_MSB                      MK_SHIFT_CONST(19)
+#define GPIO_CTL1_VM_SCR_0_PR3_LSB                      MK_SHIFT_CONST(19)
+#define GPIO_CTL1_VM_SCR_0_PR3_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
+#define GPIO_CTL1_VM_SCR_0_PR2_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR2_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_PR2_RANGE                    18:18
+#define GPIO_CTL1_VM_SCR_0_PR2_MSB                      MK_SHIFT_CONST(18)
+#define GPIO_CTL1_VM_SCR_0_PR2_LSB                      MK_SHIFT_CONST(18)
+#define GPIO_CTL1_VM_SCR_0_PR2_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
+#define GPIO_CTL1_VM_SCR_0_PR1_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR1_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_PR1_RANGE                    17:17
+#define GPIO_CTL1_VM_SCR_0_PR1_MSB                      MK_SHIFT_CONST(17)
+#define GPIO_CTL1_VM_SCR_0_PR1_LSB                      MK_SHIFT_CONST(17)
+#define GPIO_CTL1_VM_SCR_0_PR1_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
+#define GPIO_CTL1_VM_SCR_0_PR0_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_PR0_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_PR0_RANGE                    16:16
+#define GPIO_CTL1_VM_SCR_0_PR0_MSB                      MK_SHIFT_CONST(16)
+#define GPIO_CTL1_VM_SCR_0_PR0_LSB                      MK_SHIFT_CONST(16)
+#define GPIO_CTL1_VM_SCR_0_PR0_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
+#define GPIO_CTL1_VM_SCR_0_G7W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G7W_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_G7W_RANGE                    15:15
+#define GPIO_CTL1_VM_SCR_0_G7W_MSB                      MK_SHIFT_CONST(15)
+#define GPIO_CTL1_VM_SCR_0_G7W_LSB                      MK_SHIFT_CONST(15)
+#define GPIO_CTL1_VM_SCR_0_G7W_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
+#define GPIO_CTL1_VM_SCR_0_G6W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G6W_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_G6W_RANGE                    14:14
+#define GPIO_CTL1_VM_SCR_0_G6W_MSB                      MK_SHIFT_CONST(14)
+#define GPIO_CTL1_VM_SCR_0_G6W_LSB                      MK_SHIFT_CONST(14)
+#define GPIO_CTL1_VM_SCR_0_G6W_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
+#define GPIO_CTL1_VM_SCR_0_G5W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G5W_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_G5W_RANGE                    13:13
+#define GPIO_CTL1_VM_SCR_0_G5W_MSB                      MK_SHIFT_CONST(13)
+#define GPIO_CTL1_VM_SCR_0_G5W_LSB                      MK_SHIFT_CONST(13)
+#define GPIO_CTL1_VM_SCR_0_G5W_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
+#define GPIO_CTL1_VM_SCR_0_G4W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G4W_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_G4W_RANGE                    12:12
+#define GPIO_CTL1_VM_SCR_0_G4W_MSB                      MK_SHIFT_CONST(12)
+#define GPIO_CTL1_VM_SCR_0_G4W_LSB                      MK_SHIFT_CONST(12)
+#define GPIO_CTL1_VM_SCR_0_G4W_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
+#define GPIO_CTL1_VM_SCR_0_G3W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G3W_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_G3W_RANGE                    11:11
+#define GPIO_CTL1_VM_SCR_0_G3W_MSB                      MK_SHIFT_CONST(11)
+#define GPIO_CTL1_VM_SCR_0_G3W_LSB                      MK_SHIFT_CONST(11)
+#define GPIO_CTL1_VM_SCR_0_G3W_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
+#define GPIO_CTL1_VM_SCR_0_G2W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G2W_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_G2W_RANGE                    10:10
+#define GPIO_CTL1_VM_SCR_0_G2W_MSB                      MK_SHIFT_CONST(10)
+#define GPIO_CTL1_VM_SCR_0_G2W_LSB                      MK_SHIFT_CONST(10)
+#define GPIO_CTL1_VM_SCR_0_G2W_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
+#define GPIO_CTL1_VM_SCR_0_G1W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G1W_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_G1W_RANGE                    9:9
+#define GPIO_CTL1_VM_SCR_0_G1W_MSB                      MK_SHIFT_CONST(9)
+#define GPIO_CTL1_VM_SCR_0_G1W_LSB                      MK_SHIFT_CONST(9)
+#define GPIO_CTL1_VM_SCR_0_G1W_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
+#define GPIO_CTL1_VM_SCR_0_G0W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G0W_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_G0W_RANGE                    8:8
+#define GPIO_CTL1_VM_SCR_0_G0W_MSB                      MK_SHIFT_CONST(8)
+#define GPIO_CTL1_VM_SCR_0_G0W_LSB                      MK_SHIFT_CONST(8)
+#define GPIO_CTL1_VM_SCR_0_G0W_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
+#define GPIO_CTL1_VM_SCR_0_G7R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G7R_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_G7R_RANGE                    7:7
+#define GPIO_CTL1_VM_SCR_0_G7R_MSB                      MK_SHIFT_CONST(7)
+#define GPIO_CTL1_VM_SCR_0_G7R_LSB                      MK_SHIFT_CONST(7)
+#define GPIO_CTL1_VM_SCR_0_G7R_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
+#define GPIO_CTL1_VM_SCR_0_G6R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G6R_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_G6R_RANGE                    6:6
+#define GPIO_CTL1_VM_SCR_0_G6R_MSB                      MK_SHIFT_CONST(6)
+#define GPIO_CTL1_VM_SCR_0_G6R_LSB                      MK_SHIFT_CONST(6)
+#define GPIO_CTL1_VM_SCR_0_G6R_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
+#define GPIO_CTL1_VM_SCR_0_G5R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G5R_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_G5R_RANGE                    5:5
+#define GPIO_CTL1_VM_SCR_0_G5R_MSB                      MK_SHIFT_CONST(5)
+#define GPIO_CTL1_VM_SCR_0_G5R_LSB                      MK_SHIFT_CONST(5)
+#define GPIO_CTL1_VM_SCR_0_G5R_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
+#define GPIO_CTL1_VM_SCR_0_G4R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G4R_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_G4R_RANGE                    4:4
+#define GPIO_CTL1_VM_SCR_0_G4R_MSB                      MK_SHIFT_CONST(4)
+#define GPIO_CTL1_VM_SCR_0_G4R_LSB                      MK_SHIFT_CONST(4)
+#define GPIO_CTL1_VM_SCR_0_G4R_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
+#define GPIO_CTL1_VM_SCR_0_G3R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G3R_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_G3R_RANGE                    3:3
+#define GPIO_CTL1_VM_SCR_0_G3R_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_CTL1_VM_SCR_0_G3R_LSB                      MK_SHIFT_CONST(3)
+#define GPIO_CTL1_VM_SCR_0_G3R_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_CTL1_VM_SCR_0_G2R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G2R_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_G2R_RANGE                    2:2
+#define GPIO_CTL1_VM_SCR_0_G2R_MSB                      MK_SHIFT_CONST(2)
+#define GPIO_CTL1_VM_SCR_0_G2R_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_CTL1_VM_SCR_0_G2R_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
+#define GPIO_CTL1_VM_SCR_0_G1R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G1R_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_G1R_RANGE                    1:1
+#define GPIO_CTL1_VM_SCR_0_G1R_MSB                      MK_SHIFT_CONST(1)
+#define GPIO_CTL1_VM_SCR_0_G1R_LSB                      MK_SHIFT_CONST(1)
+#define GPIO_CTL1_VM_SCR_0_G1R_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_VM_SCR_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CTL1_VM_SCR_0_G0R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL1_VM_SCR_0_G0R_SHIFT)
+#define GPIO_CTL1_VM_SCR_0_G0R_RANGE                    0:0
+#define GPIO_CTL1_VM_SCR_0_G0R_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CTL1_VM_SCR_0_G0R_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CTL1_VM_SCR_0_G0R_WOFFSET                  0x0
+#define GPIO_CTL1_VM_SCR_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL1_VM_SCR_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0                     MK_ADDR_CONST(0x1804)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SCRREG                      0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_MSB                     MK_SHIFT_CONST(23)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_LSB                     MK_SHIFT_CONST(23)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_MSB                     MK_SHIFT_CONST(22)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_LSB                     MK_SHIFT_CONST(22)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_MSB                     MK_SHIFT_CONST(21)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_LSB                     MK_SHIFT_CONST(21)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_MSB                     MK_SHIFT_CONST(20)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_LSB                     MK_SHIFT_CONST(20)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_MSB                     MK_SHIFT_CONST(19)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_LSB                     MK_SHIFT_CONST(19)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_MSB                     MK_SHIFT_CONST(18)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_LSB                     MK_SHIFT_CONST(18)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_MSB                     MK_SHIFT_CONST(17)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_LSB                     MK_SHIFT_CONST(17)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_MSB                     MK_SHIFT_CONST(16)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_LSB                     MK_SHIFT_CONST(16)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_MSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_LSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_MSB                     MK_SHIFT_CONST(14)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_LSB                     MK_SHIFT_CONST(14)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_MSB                     MK_SHIFT_CONST(13)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_LSB                     MK_SHIFT_CONST(13)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_MSB                     MK_SHIFT_CONST(12)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_LSB                     MK_SHIFT_CONST(12)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_MSB                     MK_SHIFT_CONST(11)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_LSB                     MK_SHIFT_CONST(11)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_MSB                     MK_SHIFT_CONST(10)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_LSB                     MK_SHIFT_CONST(10)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_MSB                     MK_SHIFT_CONST(9)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_LSB                     MK_SHIFT_CONST(9)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_MSB                     MK_SHIFT_CONST(8)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_LSB                     MK_SHIFT_CONST(8)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_MSB                     MK_SHIFT_CONST(6)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_LSB                     MK_SHIFT_CONST(6)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_LSB                     MK_SHIFT_CONST(5)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_LSB                     MK_SHIFT_CONST(3)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_MSB                     MK_SHIFT_CONST(2)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_MSB                     MK_SHIFT_CONST(1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_LSB                     MK_SHIFT_CONST(1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_MSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL1_INTERRUPT_STATUS_VM_0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0                 MK_ADDR_CONST(0x1808)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SECURE                  0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_DUAL                    0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SCRREG                  GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  MK_FIELD_CONST(0xff, GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL1_SCR_0
+#define GPIO_CTL1_SCR_0                 MK_ADDR_CONST(0x180c)
+#define GPIO_CTL1_SCR_0_SECURE                  0x0
+#define GPIO_CTL1_SCR_0_DUAL                    0x0
+#define GPIO_CTL1_SCR_0_SCR                     0
+#define GPIO_CTL1_SCR_0_SCRREG                  0
+#define GPIO_CTL1_SCR_0_WORD_COUNT                      0x1
+#define GPIO_CTL1_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL1_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL1_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL1_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_CTL1_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL1_SCR_0_SEC_LCK_RANGE                   29:29
+#define GPIO_CTL1_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_CTL1_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_CTL1_SCR_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_CTL1_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_CTL1_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL1_SCR_0_SEC_WEN_RANGE                   28:28
+#define GPIO_CTL1_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_CTL1_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_CTL1_SCR_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_CTL1_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_CTL1_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL1_SCR_0_SEC_REN_RANGE                   27:27
+#define GPIO_CTL1_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_CTL1_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_CTL1_SCR_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_CTL1_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_CTL1_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_CTL1_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL1_SCR_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_CTL1_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_CTL1_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_CTL1_SCR_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_CTL1_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_CTL1_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_CTL1_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR7_SHIFT)
+#define GPIO_CTL1_SCR_0_PR7_RANGE                       23:23
+#define GPIO_CTL1_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_CTL1_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_CTL1_SCR_0_PR7_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_CTL1_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR6_SHIFT)
+#define GPIO_CTL1_SCR_0_PR6_RANGE                       22:22
+#define GPIO_CTL1_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_CTL1_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_CTL1_SCR_0_PR6_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_CTL1_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR5_SHIFT)
+#define GPIO_CTL1_SCR_0_PR5_RANGE                       21:21
+#define GPIO_CTL1_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_CTL1_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_CTL1_SCR_0_PR5_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_CTL1_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR4_SHIFT)
+#define GPIO_CTL1_SCR_0_PR4_RANGE                       20:20
+#define GPIO_CTL1_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_CTL1_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_CTL1_SCR_0_PR4_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_CTL1_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR3_SHIFT)
+#define GPIO_CTL1_SCR_0_PR3_RANGE                       19:19
+#define GPIO_CTL1_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_CTL1_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_CTL1_SCR_0_PR3_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_CTL1_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR2_SHIFT)
+#define GPIO_CTL1_SCR_0_PR2_RANGE                       18:18
+#define GPIO_CTL1_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_CTL1_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_CTL1_SCR_0_PR2_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_CTL1_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR1_SHIFT)
+#define GPIO_CTL1_SCR_0_PR1_RANGE                       17:17
+#define GPIO_CTL1_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_CTL1_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_CTL1_SCR_0_PR1_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_CTL1_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_PR0_SHIFT)
+#define GPIO_CTL1_SCR_0_PR0_RANGE                       16:16
+#define GPIO_CTL1_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_CTL1_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_CTL1_SCR_0_PR0_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_CTL1_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G7W_SHIFT)
+#define GPIO_CTL1_SCR_0_G7W_RANGE                       15:15
+#define GPIO_CTL1_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_CTL1_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_CTL1_SCR_0_G7W_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_CTL1_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G6W_SHIFT)
+#define GPIO_CTL1_SCR_0_G6W_RANGE                       14:14
+#define GPIO_CTL1_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_CTL1_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_CTL1_SCR_0_G6W_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_CTL1_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G5W_SHIFT)
+#define GPIO_CTL1_SCR_0_G5W_RANGE                       13:13
+#define GPIO_CTL1_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_CTL1_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_CTL1_SCR_0_G5W_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_CTL1_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G4W_SHIFT)
+#define GPIO_CTL1_SCR_0_G4W_RANGE                       12:12
+#define GPIO_CTL1_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_CTL1_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_CTL1_SCR_0_G4W_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_CTL1_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G3W_SHIFT)
+#define GPIO_CTL1_SCR_0_G3W_RANGE                       11:11
+#define GPIO_CTL1_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_CTL1_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_CTL1_SCR_0_G3W_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_CTL1_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G2W_SHIFT)
+#define GPIO_CTL1_SCR_0_G2W_RANGE                       10:10
+#define GPIO_CTL1_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_CTL1_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_CTL1_SCR_0_G2W_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_CTL1_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G1W_SHIFT)
+#define GPIO_CTL1_SCR_0_G1W_RANGE                       9:9
+#define GPIO_CTL1_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_CTL1_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_CTL1_SCR_0_G1W_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_CTL1_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G0W_SHIFT)
+#define GPIO_CTL1_SCR_0_G0W_RANGE                       8:8
+#define GPIO_CTL1_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_CTL1_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_CTL1_SCR_0_G0W_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_CTL1_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G7R_SHIFT)
+#define GPIO_CTL1_SCR_0_G7R_RANGE                       7:7
+#define GPIO_CTL1_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_CTL1_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_CTL1_SCR_0_G7R_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_CTL1_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G6R_SHIFT)
+#define GPIO_CTL1_SCR_0_G6R_RANGE                       6:6
+#define GPIO_CTL1_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_CTL1_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_CTL1_SCR_0_G6R_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_CTL1_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G5R_SHIFT)
+#define GPIO_CTL1_SCR_0_G5R_RANGE                       5:5
+#define GPIO_CTL1_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_CTL1_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_CTL1_SCR_0_G5R_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_CTL1_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G4R_SHIFT)
+#define GPIO_CTL1_SCR_0_G4R_RANGE                       4:4
+#define GPIO_CTL1_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_CTL1_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_CTL1_SCR_0_G4R_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_CTL1_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G3R_SHIFT)
+#define GPIO_CTL1_SCR_0_G3R_RANGE                       3:3
+#define GPIO_CTL1_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_CTL1_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_CTL1_SCR_0_G3R_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_CTL1_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G2R_SHIFT)
+#define GPIO_CTL1_SCR_0_G2R_RANGE                       2:2
+#define GPIO_CTL1_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_CTL1_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_CTL1_SCR_0_G2R_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_CTL1_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G1R_SHIFT)
+#define GPIO_CTL1_SCR_0_G1R_RANGE                       1:1
+#define GPIO_CTL1_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_CTL1_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_CTL1_SCR_0_G1R_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL1_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_CTL1_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL1_SCR_0_G0R_SHIFT)
+#define GPIO_CTL1_SCR_0_G0R_RANGE                       0:0
+#define GPIO_CTL1_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_CTL1_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_CTL1_SCR_0_G0R_WOFFSET                     0x0
+#define GPIO_CTL1_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL1_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL1_ICG_EN_OVERRIDE_0
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0                     MK_ADDR_CONST(0x1810)
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SECURE                      0x0
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_DUAL                        0x0
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CTL1_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INT0_ROUTE_MAPPING_0
+#define GPIO_X_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1814)
+#define GPIO_X_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_X_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_X_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_X_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_X_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_X_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_X_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_X_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INT1_ROUTE_MAPPING_0
+#define GPIO_X_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1818)
+#define GPIO_X_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_X_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_X_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_X_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_X_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_X_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_X_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_X_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INT2_ROUTE_MAPPING_0
+#define GPIO_X_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x181c)
+#define GPIO_X_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_X_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_X_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_X_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_X_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_X_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_X_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_X_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INT3_ROUTE_MAPPING_0
+#define GPIO_X_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1820)
+#define GPIO_X_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_X_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_X_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_X_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_X_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_X_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_X_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_X_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INT4_ROUTE_MAPPING_0
+#define GPIO_X_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1824)
+#define GPIO_X_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_X_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_X_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_X_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_X_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_X_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_X_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_X_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INT5_ROUTE_MAPPING_0
+#define GPIO_X_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1828)
+#define GPIO_X_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_X_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_X_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_X_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_X_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_X_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_X_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_X_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INT6_ROUTE_MAPPING_0
+#define GPIO_X_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x182c)
+#define GPIO_X_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_X_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_X_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_X_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_X_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_X_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_X_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_X_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INT7_ROUTE_MAPPING_0
+#define GPIO_X_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1830)
+#define GPIO_X_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_X_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_X_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_X_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_X_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_X_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_X_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_X_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INT0_ROUTE_MAPPING_0
+#define GPIO_Y_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1834)
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INT1_ROUTE_MAPPING_0
+#define GPIO_Y_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1838)
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INT2_ROUTE_MAPPING_0
+#define GPIO_Y_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x183c)
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INT3_ROUTE_MAPPING_0
+#define GPIO_Y_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1840)
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INT4_ROUTE_MAPPING_0
+#define GPIO_Y_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1844)
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INT5_ROUTE_MAPPING_0
+#define GPIO_Y_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1848)
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INT6_ROUTE_MAPPING_0
+#define GPIO_Y_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x184c)
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INT7_ROUTE_MAPPING_0
+#define GPIO_Y_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1850)
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INT0_ROUTE_MAPPING_0
+#define GPIO_Z_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1854)
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INT1_ROUTE_MAPPING_0
+#define GPIO_Z_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1858)
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INT2_ROUTE_MAPPING_0
+#define GPIO_Z_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x185c)
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INT3_ROUTE_MAPPING_0
+#define GPIO_Z_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1860)
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INT4_ROUTE_MAPPING_0
+#define GPIO_Z_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1864)
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INT5_ROUTE_MAPPING_0
+#define GPIO_Z_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1868)
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INT6_ROUTE_MAPPING_0
+#define GPIO_Z_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x186c)
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INT7_ROUTE_MAPPING_0
+#define GPIO_Z_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x1870)
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL1_SCR_0
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL1_SCR_0
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL1_SPARE_0
+#define GPIO_CTL1_SPARE_0                       MK_ADDR_CONST(0x1874)
+#define GPIO_CTL1_SPARE_0_SECURE                        0x0
+#define GPIO_CTL1_SPARE_0_DUAL                  0x0
+#define GPIO_CTL1_SPARE_0_SCR                   0
+#define GPIO_CTL1_SPARE_0_SCRREG                        0
+#define GPIO_CTL1_SPARE_0_WORD_COUNT                    0x1
+#define GPIO_CTL1_SPARE_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SPARE_0_RESET_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL1_SPARE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SPARE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SPARE_0_READ_MASK                     MK_MASK_CONST(0xffff)
+#define GPIO_CTL1_SPARE_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL1_SPARE_0_SPARE_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_CTL1_SPARE_0_SPARE_FIELD                   MK_FIELD_CONST(0xffff, GPIO_CTL1_SPARE_0_SPARE_SHIFT)
+#define GPIO_CTL1_SPARE_0_SPARE_RANGE                   15:0
+#define GPIO_CTL1_SPARE_0_SPARE_MSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL1_SPARE_0_SPARE_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL1_SPARE_0_SPARE_WOFFSET                 0x0
+#define GPIO_CTL1_SPARE_0_SPARE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SPARE_0_SPARE_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL1_SPARE_0_SPARE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SPARE_0_SPARE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SPARE_0_SPARE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL1_SPARE_0_SPARE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_VM_00_0
+#define GPIO_M_VM_00_0                  MK_ADDR_CONST(0x2000)
+#define GPIO_M_VM_00_0_SECURE                   0x0
+#define GPIO_M_VM_00_0_DUAL                     0x0
+#define GPIO_M_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_M_VM_00_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_M_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_M_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_M_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM1_SHIFT)
+#define GPIO_M_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_M_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_M_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_M_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_M_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_M_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM2_SHIFT)
+#define GPIO_M_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_M_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_M_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_M_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_M_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_M_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM3_SHIFT)
+#define GPIO_M_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_M_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_M_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_M_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_M_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_M_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM4_SHIFT)
+#define GPIO_M_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_M_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_M_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_M_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_M_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_M_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM5_SHIFT)
+#define GPIO_M_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_M_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_M_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_M_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_M_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_M_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM6_SHIFT)
+#define GPIO_M_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_M_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_M_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_M_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_M_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_M_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM7_SHIFT)
+#define GPIO_M_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_M_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_M_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_M_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_M_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_M_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_00_0_VM8_SHIFT)
+#define GPIO_M_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_M_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_M_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_M_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_M_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_SCR_00_0
+#define GPIO_M_SCR_00_0                 MK_ADDR_CONST(0x2004)
+#define GPIO_M_SCR_00_0_SECURE                  0x0
+#define GPIO_M_SCR_00_0_DUAL                    0x0
+#define GPIO_M_SCR_00_0_SCR                     0
+#define GPIO_M_SCR_00_0_SCRREG                  0
+#define GPIO_M_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_M_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_M_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_M_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_M_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_M_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_M_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_M_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_M_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_M_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_M_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_M_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_M_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_M_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_M_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_M_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_M_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_M_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_M_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR7_SHIFT)
+#define GPIO_M_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_M_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR6_SHIFT)
+#define GPIO_M_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_M_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR5_SHIFT)
+#define GPIO_M_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_M_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR4_SHIFT)
+#define GPIO_M_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_M_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR3_SHIFT)
+#define GPIO_M_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_M_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR2_SHIFT)
+#define GPIO_M_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_M_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR1_SHIFT)
+#define GPIO_M_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_M_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_PR0_SHIFT)
+#define GPIO_M_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_M_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G7W_SHIFT)
+#define GPIO_M_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_M_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G6W_SHIFT)
+#define GPIO_M_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_M_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G5W_SHIFT)
+#define GPIO_M_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_M_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G4W_SHIFT)
+#define GPIO_M_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_M_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G3W_SHIFT)
+#define GPIO_M_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_M_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G2W_SHIFT)
+#define GPIO_M_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_M_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G1W_SHIFT)
+#define GPIO_M_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_M_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G0W_SHIFT)
+#define GPIO_M_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_M_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G7R_SHIFT)
+#define GPIO_M_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_M_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G6R_SHIFT)
+#define GPIO_M_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_M_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G5R_SHIFT)
+#define GPIO_M_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_M_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G4R_SHIFT)
+#define GPIO_M_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_M_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G3R_SHIFT)
+#define GPIO_M_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_M_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G2R_SHIFT)
+#define GPIO_M_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_M_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G1R_SHIFT)
+#define GPIO_M_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_M_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_00_0_G0R_SHIFT)
+#define GPIO_M_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_M_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_M_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_VM_01_0
+#define GPIO_M_VM_01_0                  MK_ADDR_CONST(0x2008)
+#define GPIO_M_VM_01_0_SECURE                   0x0
+#define GPIO_M_VM_01_0_DUAL                     0x0
+#define GPIO_M_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_M_VM_01_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_M_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_M_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_M_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM1_SHIFT)
+#define GPIO_M_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_M_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_M_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_M_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_M_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_M_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM2_SHIFT)
+#define GPIO_M_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_M_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_M_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_M_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_M_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_M_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM3_SHIFT)
+#define GPIO_M_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_M_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_M_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_M_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_M_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_M_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM4_SHIFT)
+#define GPIO_M_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_M_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_M_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_M_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_M_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_M_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM5_SHIFT)
+#define GPIO_M_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_M_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_M_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_M_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_M_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_M_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM6_SHIFT)
+#define GPIO_M_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_M_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_M_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_M_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_M_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_M_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM7_SHIFT)
+#define GPIO_M_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_M_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_M_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_M_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_M_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_M_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_01_0_VM8_SHIFT)
+#define GPIO_M_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_M_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_M_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_M_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_M_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_SCR_01_0
+#define GPIO_M_SCR_01_0                 MK_ADDR_CONST(0x200c)
+#define GPIO_M_SCR_01_0_SECURE                  0x0
+#define GPIO_M_SCR_01_0_DUAL                    0x0
+#define GPIO_M_SCR_01_0_SCR                     0
+#define GPIO_M_SCR_01_0_SCRREG                  0
+#define GPIO_M_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_M_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_M_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_M_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_M_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_M_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_M_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_M_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_M_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_M_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_M_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_M_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_M_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_M_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_M_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_M_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_M_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_M_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_M_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR7_SHIFT)
+#define GPIO_M_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_M_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR6_SHIFT)
+#define GPIO_M_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_M_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR5_SHIFT)
+#define GPIO_M_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_M_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR4_SHIFT)
+#define GPIO_M_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_M_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR3_SHIFT)
+#define GPIO_M_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_M_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR2_SHIFT)
+#define GPIO_M_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_M_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR1_SHIFT)
+#define GPIO_M_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_M_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_PR0_SHIFT)
+#define GPIO_M_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_M_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G7W_SHIFT)
+#define GPIO_M_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_M_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G6W_SHIFT)
+#define GPIO_M_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_M_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G5W_SHIFT)
+#define GPIO_M_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_M_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G4W_SHIFT)
+#define GPIO_M_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_M_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G3W_SHIFT)
+#define GPIO_M_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_M_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G2W_SHIFT)
+#define GPIO_M_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_M_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G1W_SHIFT)
+#define GPIO_M_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_M_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G0W_SHIFT)
+#define GPIO_M_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_M_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G7R_SHIFT)
+#define GPIO_M_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_M_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G6R_SHIFT)
+#define GPIO_M_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_M_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G5R_SHIFT)
+#define GPIO_M_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_M_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G4R_SHIFT)
+#define GPIO_M_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_M_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G3R_SHIFT)
+#define GPIO_M_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_M_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G2R_SHIFT)
+#define GPIO_M_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_M_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G1R_SHIFT)
+#define GPIO_M_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_M_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_01_0_G0R_SHIFT)
+#define GPIO_M_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_M_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_M_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_VM_02_0
+#define GPIO_M_VM_02_0                  MK_ADDR_CONST(0x2010)
+#define GPIO_M_VM_02_0_SECURE                   0x0
+#define GPIO_M_VM_02_0_DUAL                     0x0
+#define GPIO_M_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_M_VM_02_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_M_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_M_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_M_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM1_SHIFT)
+#define GPIO_M_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_M_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_M_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_M_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_M_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_M_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM2_SHIFT)
+#define GPIO_M_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_M_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_M_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_M_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_M_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_M_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM3_SHIFT)
+#define GPIO_M_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_M_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_M_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_M_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_M_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_M_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM4_SHIFT)
+#define GPIO_M_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_M_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_M_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_M_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_M_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_M_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM5_SHIFT)
+#define GPIO_M_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_M_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_M_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_M_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_M_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_M_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM6_SHIFT)
+#define GPIO_M_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_M_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_M_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_M_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_M_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_M_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM7_SHIFT)
+#define GPIO_M_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_M_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_M_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_M_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_M_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_M_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_02_0_VM8_SHIFT)
+#define GPIO_M_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_M_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_M_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_M_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_M_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_SCR_02_0
+#define GPIO_M_SCR_02_0                 MK_ADDR_CONST(0x2014)
+#define GPIO_M_SCR_02_0_SECURE                  0x0
+#define GPIO_M_SCR_02_0_DUAL                    0x0
+#define GPIO_M_SCR_02_0_SCR                     0
+#define GPIO_M_SCR_02_0_SCRREG                  0
+#define GPIO_M_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_M_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_M_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_M_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_M_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_M_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_M_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_M_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_M_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_M_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_M_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_M_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_M_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_M_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_M_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_M_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_M_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_M_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_M_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR7_SHIFT)
+#define GPIO_M_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_M_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR6_SHIFT)
+#define GPIO_M_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_M_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR5_SHIFT)
+#define GPIO_M_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_M_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR4_SHIFT)
+#define GPIO_M_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_M_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR3_SHIFT)
+#define GPIO_M_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_M_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR2_SHIFT)
+#define GPIO_M_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_M_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR1_SHIFT)
+#define GPIO_M_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_M_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_PR0_SHIFT)
+#define GPIO_M_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_M_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G7W_SHIFT)
+#define GPIO_M_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_M_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G6W_SHIFT)
+#define GPIO_M_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_M_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G5W_SHIFT)
+#define GPIO_M_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_M_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G4W_SHIFT)
+#define GPIO_M_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_M_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G3W_SHIFT)
+#define GPIO_M_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_M_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G2W_SHIFT)
+#define GPIO_M_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_M_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G1W_SHIFT)
+#define GPIO_M_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_M_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G0W_SHIFT)
+#define GPIO_M_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_M_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G7R_SHIFT)
+#define GPIO_M_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_M_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G6R_SHIFT)
+#define GPIO_M_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_M_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G5R_SHIFT)
+#define GPIO_M_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_M_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G4R_SHIFT)
+#define GPIO_M_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_M_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G3R_SHIFT)
+#define GPIO_M_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_M_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G2R_SHIFT)
+#define GPIO_M_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_M_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G1R_SHIFT)
+#define GPIO_M_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_M_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_02_0_G0R_SHIFT)
+#define GPIO_M_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_M_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_M_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_VM_03_0
+#define GPIO_M_VM_03_0                  MK_ADDR_CONST(0x2018)
+#define GPIO_M_VM_03_0_SECURE                   0x0
+#define GPIO_M_VM_03_0_DUAL                     0x0
+#define GPIO_M_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_M_VM_03_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_M_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_M_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_M_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM1_SHIFT)
+#define GPIO_M_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_M_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_M_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_M_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_M_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_M_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM2_SHIFT)
+#define GPIO_M_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_M_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_M_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_M_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_M_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_M_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM3_SHIFT)
+#define GPIO_M_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_M_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_M_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_M_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_M_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_M_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM4_SHIFT)
+#define GPIO_M_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_M_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_M_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_M_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_M_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_M_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM5_SHIFT)
+#define GPIO_M_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_M_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_M_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_M_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_M_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_M_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM6_SHIFT)
+#define GPIO_M_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_M_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_M_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_M_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_M_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_M_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM7_SHIFT)
+#define GPIO_M_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_M_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_M_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_M_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_M_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_M_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_03_0_VM8_SHIFT)
+#define GPIO_M_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_M_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_M_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_M_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_M_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_SCR_03_0
+#define GPIO_M_SCR_03_0                 MK_ADDR_CONST(0x201c)
+#define GPIO_M_SCR_03_0_SECURE                  0x0
+#define GPIO_M_SCR_03_0_DUAL                    0x0
+#define GPIO_M_SCR_03_0_SCR                     0
+#define GPIO_M_SCR_03_0_SCRREG                  0
+#define GPIO_M_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_M_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_M_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_M_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_M_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_M_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_M_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_M_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_M_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_M_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_M_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_M_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_M_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_M_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_M_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_M_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_M_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_M_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_M_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR7_SHIFT)
+#define GPIO_M_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_M_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR6_SHIFT)
+#define GPIO_M_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_M_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR5_SHIFT)
+#define GPIO_M_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_M_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR4_SHIFT)
+#define GPIO_M_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_M_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR3_SHIFT)
+#define GPIO_M_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_M_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR2_SHIFT)
+#define GPIO_M_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_M_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR1_SHIFT)
+#define GPIO_M_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_M_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_PR0_SHIFT)
+#define GPIO_M_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_M_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G7W_SHIFT)
+#define GPIO_M_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_M_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G6W_SHIFT)
+#define GPIO_M_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_M_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G5W_SHIFT)
+#define GPIO_M_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_M_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G4W_SHIFT)
+#define GPIO_M_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_M_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G3W_SHIFT)
+#define GPIO_M_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_M_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G2W_SHIFT)
+#define GPIO_M_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_M_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G1W_SHIFT)
+#define GPIO_M_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_M_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G0W_SHIFT)
+#define GPIO_M_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_M_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G7R_SHIFT)
+#define GPIO_M_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_M_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G6R_SHIFT)
+#define GPIO_M_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_M_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G5R_SHIFT)
+#define GPIO_M_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_M_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G4R_SHIFT)
+#define GPIO_M_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_M_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G3R_SHIFT)
+#define GPIO_M_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_M_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G2R_SHIFT)
+#define GPIO_M_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_M_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G1R_SHIFT)
+#define GPIO_M_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_M_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_03_0_G0R_SHIFT)
+#define GPIO_M_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_M_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_M_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_VM_04_0
+#define GPIO_M_VM_04_0                  MK_ADDR_CONST(0x2020)
+#define GPIO_M_VM_04_0_SECURE                   0x0
+#define GPIO_M_VM_04_0_DUAL                     0x0
+#define GPIO_M_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_M_VM_04_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_M_VM_04_0_WORD_COUNT                       0x1
+#define GPIO_M_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_M_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM1_SHIFT)
+#define GPIO_M_VM_04_0_VM1_RANGE                        1:0
+#define GPIO_M_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_M_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_M_VM_04_0_VM1_WOFFSET                      0x0
+#define GPIO_M_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_M_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM2_SHIFT)
+#define GPIO_M_VM_04_0_VM2_RANGE                        3:2
+#define GPIO_M_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_M_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_M_VM_04_0_VM2_WOFFSET                      0x0
+#define GPIO_M_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_M_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM3_SHIFT)
+#define GPIO_M_VM_04_0_VM3_RANGE                        5:4
+#define GPIO_M_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_M_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_M_VM_04_0_VM3_WOFFSET                      0x0
+#define GPIO_M_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_M_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM4_SHIFT)
+#define GPIO_M_VM_04_0_VM4_RANGE                        7:6
+#define GPIO_M_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_M_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_M_VM_04_0_VM4_WOFFSET                      0x0
+#define GPIO_M_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_M_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM5_SHIFT)
+#define GPIO_M_VM_04_0_VM5_RANGE                        9:8
+#define GPIO_M_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_M_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_M_VM_04_0_VM5_WOFFSET                      0x0
+#define GPIO_M_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_M_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM6_SHIFT)
+#define GPIO_M_VM_04_0_VM6_RANGE                        11:10
+#define GPIO_M_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_M_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_M_VM_04_0_VM6_WOFFSET                      0x0
+#define GPIO_M_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_M_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM7_SHIFT)
+#define GPIO_M_VM_04_0_VM7_RANGE                        13:12
+#define GPIO_M_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_M_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_M_VM_04_0_VM7_WOFFSET                      0x0
+#define GPIO_M_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_M_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_04_0_VM8_SHIFT)
+#define GPIO_M_VM_04_0_VM8_RANGE                        15:14
+#define GPIO_M_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_M_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_M_VM_04_0_VM8_WOFFSET                      0x0
+#define GPIO_M_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_SCR_04_0
+#define GPIO_M_SCR_04_0                 MK_ADDR_CONST(0x2024)
+#define GPIO_M_SCR_04_0_SECURE                  0x0
+#define GPIO_M_SCR_04_0_DUAL                    0x0
+#define GPIO_M_SCR_04_0_SCR                     0
+#define GPIO_M_SCR_04_0_SCRREG                  0
+#define GPIO_M_SCR_04_0_WORD_COUNT                      0x1
+#define GPIO_M_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_M_SCR_04_0_SEC_LCK_RANGE                   29:29
+#define GPIO_M_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_04_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_M_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_M_SCR_04_0_SEC_WEN_RANGE                   28:28
+#define GPIO_M_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_04_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_M_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_M_SCR_04_0_SEC_REN_RANGE                   27:27
+#define GPIO_M_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_04_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_M_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_M_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_M_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_M_SCR_04_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_M_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_M_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_M_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_M_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_M_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR7_SHIFT)
+#define GPIO_M_SCR_04_0_PR7_RANGE                       23:23
+#define GPIO_M_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_04_0_PR7_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR6_SHIFT)
+#define GPIO_M_SCR_04_0_PR6_RANGE                       22:22
+#define GPIO_M_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_04_0_PR6_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR5_SHIFT)
+#define GPIO_M_SCR_04_0_PR5_RANGE                       21:21
+#define GPIO_M_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_04_0_PR5_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR4_SHIFT)
+#define GPIO_M_SCR_04_0_PR4_RANGE                       20:20
+#define GPIO_M_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_04_0_PR4_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR3_SHIFT)
+#define GPIO_M_SCR_04_0_PR3_RANGE                       19:19
+#define GPIO_M_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_04_0_PR3_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR2_SHIFT)
+#define GPIO_M_SCR_04_0_PR2_RANGE                       18:18
+#define GPIO_M_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_04_0_PR2_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR1_SHIFT)
+#define GPIO_M_SCR_04_0_PR1_RANGE                       17:17
+#define GPIO_M_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_04_0_PR1_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_PR0_SHIFT)
+#define GPIO_M_SCR_04_0_PR0_RANGE                       16:16
+#define GPIO_M_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_04_0_PR0_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G7W_SHIFT)
+#define GPIO_M_SCR_04_0_G7W_RANGE                       15:15
+#define GPIO_M_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_04_0_G7W_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G6W_SHIFT)
+#define GPIO_M_SCR_04_0_G6W_RANGE                       14:14
+#define GPIO_M_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_04_0_G6W_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G5W_SHIFT)
+#define GPIO_M_SCR_04_0_G5W_RANGE                       13:13
+#define GPIO_M_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_04_0_G5W_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G4W_SHIFT)
+#define GPIO_M_SCR_04_0_G4W_RANGE                       12:12
+#define GPIO_M_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_04_0_G4W_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G3W_SHIFT)
+#define GPIO_M_SCR_04_0_G3W_RANGE                       11:11
+#define GPIO_M_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_04_0_G3W_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G2W_SHIFT)
+#define GPIO_M_SCR_04_0_G2W_RANGE                       10:10
+#define GPIO_M_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_04_0_G2W_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G1W_SHIFT)
+#define GPIO_M_SCR_04_0_G1W_RANGE                       9:9
+#define GPIO_M_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_04_0_G1W_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G0W_SHIFT)
+#define GPIO_M_SCR_04_0_G0W_RANGE                       8:8
+#define GPIO_M_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_04_0_G0W_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G7R_SHIFT)
+#define GPIO_M_SCR_04_0_G7R_RANGE                       7:7
+#define GPIO_M_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_04_0_G7R_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G6R_SHIFT)
+#define GPIO_M_SCR_04_0_G6R_RANGE                       6:6
+#define GPIO_M_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_04_0_G6R_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G5R_SHIFT)
+#define GPIO_M_SCR_04_0_G5R_RANGE                       5:5
+#define GPIO_M_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_04_0_G5R_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G4R_SHIFT)
+#define GPIO_M_SCR_04_0_G4R_RANGE                       4:4
+#define GPIO_M_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_04_0_G4R_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G3R_SHIFT)
+#define GPIO_M_SCR_04_0_G3R_RANGE                       3:3
+#define GPIO_M_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_04_0_G3R_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G2R_SHIFT)
+#define GPIO_M_SCR_04_0_G2R_RANGE                       2:2
+#define GPIO_M_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_04_0_G2R_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G1R_SHIFT)
+#define GPIO_M_SCR_04_0_G1R_RANGE                       1:1
+#define GPIO_M_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_04_0_G1R_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_04_0_G0R_SHIFT)
+#define GPIO_M_SCR_04_0_G0R_RANGE                       0:0
+#define GPIO_M_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_04_0_G0R_WOFFSET                     0x0
+#define GPIO_M_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_VM_05_0
+#define GPIO_M_VM_05_0                  MK_ADDR_CONST(0x2028)
+#define GPIO_M_VM_05_0_SECURE                   0x0
+#define GPIO_M_VM_05_0_DUAL                     0x0
+#define GPIO_M_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_M_VM_05_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_M_VM_05_0_WORD_COUNT                       0x1
+#define GPIO_M_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_M_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM1_SHIFT)
+#define GPIO_M_VM_05_0_VM1_RANGE                        1:0
+#define GPIO_M_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_M_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_M_VM_05_0_VM1_WOFFSET                      0x0
+#define GPIO_M_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_M_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM2_SHIFT)
+#define GPIO_M_VM_05_0_VM2_RANGE                        3:2
+#define GPIO_M_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_M_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_M_VM_05_0_VM2_WOFFSET                      0x0
+#define GPIO_M_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_M_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM3_SHIFT)
+#define GPIO_M_VM_05_0_VM3_RANGE                        5:4
+#define GPIO_M_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_M_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_M_VM_05_0_VM3_WOFFSET                      0x0
+#define GPIO_M_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_M_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM4_SHIFT)
+#define GPIO_M_VM_05_0_VM4_RANGE                        7:6
+#define GPIO_M_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_M_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_M_VM_05_0_VM4_WOFFSET                      0x0
+#define GPIO_M_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_M_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM5_SHIFT)
+#define GPIO_M_VM_05_0_VM5_RANGE                        9:8
+#define GPIO_M_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_M_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_M_VM_05_0_VM5_WOFFSET                      0x0
+#define GPIO_M_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_M_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM6_SHIFT)
+#define GPIO_M_VM_05_0_VM6_RANGE                        11:10
+#define GPIO_M_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_M_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_M_VM_05_0_VM6_WOFFSET                      0x0
+#define GPIO_M_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_M_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM7_SHIFT)
+#define GPIO_M_VM_05_0_VM7_RANGE                        13:12
+#define GPIO_M_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_M_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_M_VM_05_0_VM7_WOFFSET                      0x0
+#define GPIO_M_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_M_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_05_0_VM8_SHIFT)
+#define GPIO_M_VM_05_0_VM8_RANGE                        15:14
+#define GPIO_M_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_M_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_M_VM_05_0_VM8_WOFFSET                      0x0
+#define GPIO_M_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_SCR_05_0
+#define GPIO_M_SCR_05_0                 MK_ADDR_CONST(0x202c)
+#define GPIO_M_SCR_05_0_SECURE                  0x0
+#define GPIO_M_SCR_05_0_DUAL                    0x0
+#define GPIO_M_SCR_05_0_SCR                     0
+#define GPIO_M_SCR_05_0_SCRREG                  0
+#define GPIO_M_SCR_05_0_WORD_COUNT                      0x1
+#define GPIO_M_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_M_SCR_05_0_SEC_LCK_RANGE                   29:29
+#define GPIO_M_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_05_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_M_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_M_SCR_05_0_SEC_WEN_RANGE                   28:28
+#define GPIO_M_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_05_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_M_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_M_SCR_05_0_SEC_REN_RANGE                   27:27
+#define GPIO_M_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_05_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_M_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_M_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_M_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_M_SCR_05_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_M_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_M_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_M_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_M_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_M_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR7_SHIFT)
+#define GPIO_M_SCR_05_0_PR7_RANGE                       23:23
+#define GPIO_M_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_05_0_PR7_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR6_SHIFT)
+#define GPIO_M_SCR_05_0_PR6_RANGE                       22:22
+#define GPIO_M_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_05_0_PR6_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR5_SHIFT)
+#define GPIO_M_SCR_05_0_PR5_RANGE                       21:21
+#define GPIO_M_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_05_0_PR5_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR4_SHIFT)
+#define GPIO_M_SCR_05_0_PR4_RANGE                       20:20
+#define GPIO_M_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_05_0_PR4_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR3_SHIFT)
+#define GPIO_M_SCR_05_0_PR3_RANGE                       19:19
+#define GPIO_M_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_05_0_PR3_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR2_SHIFT)
+#define GPIO_M_SCR_05_0_PR2_RANGE                       18:18
+#define GPIO_M_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_05_0_PR2_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR1_SHIFT)
+#define GPIO_M_SCR_05_0_PR1_RANGE                       17:17
+#define GPIO_M_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_05_0_PR1_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_PR0_SHIFT)
+#define GPIO_M_SCR_05_0_PR0_RANGE                       16:16
+#define GPIO_M_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_05_0_PR0_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G7W_SHIFT)
+#define GPIO_M_SCR_05_0_G7W_RANGE                       15:15
+#define GPIO_M_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_05_0_G7W_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G6W_SHIFT)
+#define GPIO_M_SCR_05_0_G6W_RANGE                       14:14
+#define GPIO_M_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_05_0_G6W_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G5W_SHIFT)
+#define GPIO_M_SCR_05_0_G5W_RANGE                       13:13
+#define GPIO_M_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_05_0_G5W_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G4W_SHIFT)
+#define GPIO_M_SCR_05_0_G4W_RANGE                       12:12
+#define GPIO_M_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_05_0_G4W_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G3W_SHIFT)
+#define GPIO_M_SCR_05_0_G3W_RANGE                       11:11
+#define GPIO_M_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_05_0_G3W_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G2W_SHIFT)
+#define GPIO_M_SCR_05_0_G2W_RANGE                       10:10
+#define GPIO_M_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_05_0_G2W_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G1W_SHIFT)
+#define GPIO_M_SCR_05_0_G1W_RANGE                       9:9
+#define GPIO_M_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_05_0_G1W_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G0W_SHIFT)
+#define GPIO_M_SCR_05_0_G0W_RANGE                       8:8
+#define GPIO_M_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_05_0_G0W_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G7R_SHIFT)
+#define GPIO_M_SCR_05_0_G7R_RANGE                       7:7
+#define GPIO_M_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_05_0_G7R_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G6R_SHIFT)
+#define GPIO_M_SCR_05_0_G6R_RANGE                       6:6
+#define GPIO_M_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_05_0_G6R_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G5R_SHIFT)
+#define GPIO_M_SCR_05_0_G5R_RANGE                       5:5
+#define GPIO_M_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_05_0_G5R_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G4R_SHIFT)
+#define GPIO_M_SCR_05_0_G4R_RANGE                       4:4
+#define GPIO_M_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_05_0_G4R_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G3R_SHIFT)
+#define GPIO_M_SCR_05_0_G3R_RANGE                       3:3
+#define GPIO_M_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_05_0_G3R_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G2R_SHIFT)
+#define GPIO_M_SCR_05_0_G2R_RANGE                       2:2
+#define GPIO_M_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_05_0_G2R_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G1R_SHIFT)
+#define GPIO_M_SCR_05_0_G1R_RANGE                       1:1
+#define GPIO_M_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_05_0_G1R_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_05_0_G0R_SHIFT)
+#define GPIO_M_SCR_05_0_G0R_RANGE                       0:0
+#define GPIO_M_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_05_0_G0R_WOFFSET                     0x0
+#define GPIO_M_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_VM_06_0
+#define GPIO_M_VM_06_0                  MK_ADDR_CONST(0x2030)
+#define GPIO_M_VM_06_0_SECURE                   0x0
+#define GPIO_M_VM_06_0_DUAL                     0x0
+#define GPIO_M_VM_06_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_M_VM_06_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_M_VM_06_0_WORD_COUNT                       0x1
+#define GPIO_M_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_M_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM1_SHIFT)
+#define GPIO_M_VM_06_0_VM1_RANGE                        1:0
+#define GPIO_M_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_M_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_M_VM_06_0_VM1_WOFFSET                      0x0
+#define GPIO_M_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_M_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM2_SHIFT)
+#define GPIO_M_VM_06_0_VM2_RANGE                        3:2
+#define GPIO_M_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_M_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_M_VM_06_0_VM2_WOFFSET                      0x0
+#define GPIO_M_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_M_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM3_SHIFT)
+#define GPIO_M_VM_06_0_VM3_RANGE                        5:4
+#define GPIO_M_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_M_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_M_VM_06_0_VM3_WOFFSET                      0x0
+#define GPIO_M_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_M_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM4_SHIFT)
+#define GPIO_M_VM_06_0_VM4_RANGE                        7:6
+#define GPIO_M_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_M_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_M_VM_06_0_VM4_WOFFSET                      0x0
+#define GPIO_M_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_M_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM5_SHIFT)
+#define GPIO_M_VM_06_0_VM5_RANGE                        9:8
+#define GPIO_M_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_M_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_M_VM_06_0_VM5_WOFFSET                      0x0
+#define GPIO_M_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_M_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM6_SHIFT)
+#define GPIO_M_VM_06_0_VM6_RANGE                        11:10
+#define GPIO_M_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_M_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_M_VM_06_0_VM6_WOFFSET                      0x0
+#define GPIO_M_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_M_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM7_SHIFT)
+#define GPIO_M_VM_06_0_VM7_RANGE                        13:12
+#define GPIO_M_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_M_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_M_VM_06_0_VM7_WOFFSET                      0x0
+#define GPIO_M_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_M_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_06_0_VM8_SHIFT)
+#define GPIO_M_VM_06_0_VM8_RANGE                        15:14
+#define GPIO_M_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_M_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_M_VM_06_0_VM8_WOFFSET                      0x0
+#define GPIO_M_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_SCR_06_0
+#define GPIO_M_SCR_06_0                 MK_ADDR_CONST(0x2034)
+#define GPIO_M_SCR_06_0_SECURE                  0x0
+#define GPIO_M_SCR_06_0_DUAL                    0x0
+#define GPIO_M_SCR_06_0_SCR                     0
+#define GPIO_M_SCR_06_0_SCRREG                  0
+#define GPIO_M_SCR_06_0_WORD_COUNT                      0x1
+#define GPIO_M_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_SEC_LCK_SHIFT)
+#define GPIO_M_SCR_06_0_SEC_LCK_RANGE                   29:29
+#define GPIO_M_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_06_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_M_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_SEC_WEN_SHIFT)
+#define GPIO_M_SCR_06_0_SEC_WEN_RANGE                   28:28
+#define GPIO_M_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_06_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_M_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_SEC_REN_SHIFT)
+#define GPIO_M_SCR_06_0_SEC_REN_RANGE                   27:27
+#define GPIO_M_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_06_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_M_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_M_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_M_SCR_06_0_SEC_OWNER_SHIFT)
+#define GPIO_M_SCR_06_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_M_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_M_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_M_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_M_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_M_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR7_SHIFT)
+#define GPIO_M_SCR_06_0_PR7_RANGE                       23:23
+#define GPIO_M_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_06_0_PR7_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR6_SHIFT)
+#define GPIO_M_SCR_06_0_PR6_RANGE                       22:22
+#define GPIO_M_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_06_0_PR6_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR5_SHIFT)
+#define GPIO_M_SCR_06_0_PR5_RANGE                       21:21
+#define GPIO_M_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_06_0_PR5_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR4_SHIFT)
+#define GPIO_M_SCR_06_0_PR4_RANGE                       20:20
+#define GPIO_M_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_06_0_PR4_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR3_SHIFT)
+#define GPIO_M_SCR_06_0_PR3_RANGE                       19:19
+#define GPIO_M_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_06_0_PR3_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR2_SHIFT)
+#define GPIO_M_SCR_06_0_PR2_RANGE                       18:18
+#define GPIO_M_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_06_0_PR2_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR1_SHIFT)
+#define GPIO_M_SCR_06_0_PR1_RANGE                       17:17
+#define GPIO_M_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_06_0_PR1_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_PR0_SHIFT)
+#define GPIO_M_SCR_06_0_PR0_RANGE                       16:16
+#define GPIO_M_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_06_0_PR0_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G7W_SHIFT)
+#define GPIO_M_SCR_06_0_G7W_RANGE                       15:15
+#define GPIO_M_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_06_0_G7W_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G6W_SHIFT)
+#define GPIO_M_SCR_06_0_G6W_RANGE                       14:14
+#define GPIO_M_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_06_0_G6W_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G5W_SHIFT)
+#define GPIO_M_SCR_06_0_G5W_RANGE                       13:13
+#define GPIO_M_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_06_0_G5W_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G4W_SHIFT)
+#define GPIO_M_SCR_06_0_G4W_RANGE                       12:12
+#define GPIO_M_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_06_0_G4W_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G3W_SHIFT)
+#define GPIO_M_SCR_06_0_G3W_RANGE                       11:11
+#define GPIO_M_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_06_0_G3W_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G2W_SHIFT)
+#define GPIO_M_SCR_06_0_G2W_RANGE                       10:10
+#define GPIO_M_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_06_0_G2W_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G1W_SHIFT)
+#define GPIO_M_SCR_06_0_G1W_RANGE                       9:9
+#define GPIO_M_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_06_0_G1W_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G0W_SHIFT)
+#define GPIO_M_SCR_06_0_G0W_RANGE                       8:8
+#define GPIO_M_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_06_0_G0W_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G7R_SHIFT)
+#define GPIO_M_SCR_06_0_G7R_RANGE                       7:7
+#define GPIO_M_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_06_0_G7R_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G6R_SHIFT)
+#define GPIO_M_SCR_06_0_G6R_RANGE                       6:6
+#define GPIO_M_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_06_0_G6R_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G5R_SHIFT)
+#define GPIO_M_SCR_06_0_G5R_RANGE                       5:5
+#define GPIO_M_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_06_0_G5R_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G4R_SHIFT)
+#define GPIO_M_SCR_06_0_G4R_RANGE                       4:4
+#define GPIO_M_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_06_0_G4R_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G3R_SHIFT)
+#define GPIO_M_SCR_06_0_G3R_RANGE                       3:3
+#define GPIO_M_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_06_0_G3R_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G2R_SHIFT)
+#define GPIO_M_SCR_06_0_G2R_RANGE                       2:2
+#define GPIO_M_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_06_0_G2R_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G1R_SHIFT)
+#define GPIO_M_SCR_06_0_G1R_RANGE                       1:1
+#define GPIO_M_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_06_0_G1R_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_06_0_G0R_SHIFT)
+#define GPIO_M_SCR_06_0_G0R_RANGE                       0:0
+#define GPIO_M_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_06_0_G0R_WOFFSET                     0x0
+#define GPIO_M_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_VM_07_0
+#define GPIO_M_VM_07_0                  MK_ADDR_CONST(0x2038)
+#define GPIO_M_VM_07_0_SECURE                   0x0
+#define GPIO_M_VM_07_0_DUAL                     0x0
+#define GPIO_M_VM_07_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_M_VM_07_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_M_VM_07_0_WORD_COUNT                       0x1
+#define GPIO_M_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_M_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_M_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM1_SHIFT)
+#define GPIO_M_VM_07_0_VM1_RANGE                        1:0
+#define GPIO_M_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_M_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_M_VM_07_0_VM1_WOFFSET                      0x0
+#define GPIO_M_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_M_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM2_SHIFT)
+#define GPIO_M_VM_07_0_VM2_RANGE                        3:2
+#define GPIO_M_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_M_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_M_VM_07_0_VM2_WOFFSET                      0x0
+#define GPIO_M_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_M_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM3_SHIFT)
+#define GPIO_M_VM_07_0_VM3_RANGE                        5:4
+#define GPIO_M_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_M_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_M_VM_07_0_VM3_WOFFSET                      0x0
+#define GPIO_M_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_M_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM4_SHIFT)
+#define GPIO_M_VM_07_0_VM4_RANGE                        7:6
+#define GPIO_M_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_M_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_M_VM_07_0_VM4_WOFFSET                      0x0
+#define GPIO_M_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_M_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM5_SHIFT)
+#define GPIO_M_VM_07_0_VM5_RANGE                        9:8
+#define GPIO_M_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_M_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_M_VM_07_0_VM5_WOFFSET                      0x0
+#define GPIO_M_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_M_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM6_SHIFT)
+#define GPIO_M_VM_07_0_VM6_RANGE                        11:10
+#define GPIO_M_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_M_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_M_VM_07_0_VM6_WOFFSET                      0x0
+#define GPIO_M_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_M_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM7_SHIFT)
+#define GPIO_M_VM_07_0_VM7_RANGE                        13:12
+#define GPIO_M_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_M_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_M_VM_07_0_VM7_WOFFSET                      0x0
+#define GPIO_M_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_M_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_M_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_M_VM_07_0_VM8_SHIFT)
+#define GPIO_M_VM_07_0_VM8_RANGE                        15:14
+#define GPIO_M_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_M_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_M_VM_07_0_VM8_WOFFSET                      0x0
+#define GPIO_M_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_M_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_M_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_SCR_07_0
+#define GPIO_M_SCR_07_0                 MK_ADDR_CONST(0x203c)
+#define GPIO_M_SCR_07_0_SECURE                  0x0
+#define GPIO_M_SCR_07_0_DUAL                    0x0
+#define GPIO_M_SCR_07_0_SCR                     0
+#define GPIO_M_SCR_07_0_SCRREG                  0
+#define GPIO_M_SCR_07_0_WORD_COUNT                      0x1
+#define GPIO_M_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_M_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_SEC_LCK_SHIFT)
+#define GPIO_M_SCR_07_0_SEC_LCK_RANGE                   29:29
+#define GPIO_M_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_M_SCR_07_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_M_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_SEC_WEN_SHIFT)
+#define GPIO_M_SCR_07_0_SEC_WEN_RANGE                   28:28
+#define GPIO_M_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_M_SCR_07_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_M_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_SEC_REN_SHIFT)
+#define GPIO_M_SCR_07_0_SEC_REN_RANGE                   27:27
+#define GPIO_M_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_M_SCR_07_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_M_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_M_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_M_SCR_07_0_SEC_OWNER_SHIFT)
+#define GPIO_M_SCR_07_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_M_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_M_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_M_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_M_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_M_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR7_SHIFT)
+#define GPIO_M_SCR_07_0_PR7_RANGE                       23:23
+#define GPIO_M_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_M_SCR_07_0_PR7_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR6_SHIFT)
+#define GPIO_M_SCR_07_0_PR6_RANGE                       22:22
+#define GPIO_M_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_M_SCR_07_0_PR6_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR5_SHIFT)
+#define GPIO_M_SCR_07_0_PR5_RANGE                       21:21
+#define GPIO_M_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_M_SCR_07_0_PR5_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR4_SHIFT)
+#define GPIO_M_SCR_07_0_PR4_RANGE                       20:20
+#define GPIO_M_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_M_SCR_07_0_PR4_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR3_SHIFT)
+#define GPIO_M_SCR_07_0_PR3_RANGE                       19:19
+#define GPIO_M_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_M_SCR_07_0_PR3_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR2_SHIFT)
+#define GPIO_M_SCR_07_0_PR2_RANGE                       18:18
+#define GPIO_M_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_M_SCR_07_0_PR2_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR1_SHIFT)
+#define GPIO_M_SCR_07_0_PR1_RANGE                       17:17
+#define GPIO_M_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_M_SCR_07_0_PR1_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_PR0_SHIFT)
+#define GPIO_M_SCR_07_0_PR0_RANGE                       16:16
+#define GPIO_M_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_M_SCR_07_0_PR0_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G7W_SHIFT)
+#define GPIO_M_SCR_07_0_G7W_RANGE                       15:15
+#define GPIO_M_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_M_SCR_07_0_G7W_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G6W_SHIFT)
+#define GPIO_M_SCR_07_0_G6W_RANGE                       14:14
+#define GPIO_M_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_M_SCR_07_0_G6W_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G5W_SHIFT)
+#define GPIO_M_SCR_07_0_G5W_RANGE                       13:13
+#define GPIO_M_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_M_SCR_07_0_G5W_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G4W_SHIFT)
+#define GPIO_M_SCR_07_0_G4W_RANGE                       12:12
+#define GPIO_M_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_M_SCR_07_0_G4W_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G3W_SHIFT)
+#define GPIO_M_SCR_07_0_G3W_RANGE                       11:11
+#define GPIO_M_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_M_SCR_07_0_G3W_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G2W_SHIFT)
+#define GPIO_M_SCR_07_0_G2W_RANGE                       10:10
+#define GPIO_M_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_M_SCR_07_0_G2W_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G1W_SHIFT)
+#define GPIO_M_SCR_07_0_G1W_RANGE                       9:9
+#define GPIO_M_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_M_SCR_07_0_G1W_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G0W_SHIFT)
+#define GPIO_M_SCR_07_0_G0W_RANGE                       8:8
+#define GPIO_M_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_M_SCR_07_0_G0W_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G7R_SHIFT)
+#define GPIO_M_SCR_07_0_G7R_RANGE                       7:7
+#define GPIO_M_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_M_SCR_07_0_G7R_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G6R_SHIFT)
+#define GPIO_M_SCR_07_0_G6R_RANGE                       6:6
+#define GPIO_M_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_M_SCR_07_0_G6R_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G5R_SHIFT)
+#define GPIO_M_SCR_07_0_G5R_RANGE                       5:5
+#define GPIO_M_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_SCR_07_0_G5R_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G4R_SHIFT)
+#define GPIO_M_SCR_07_0_G4R_RANGE                       4:4
+#define GPIO_M_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_M_SCR_07_0_G4R_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G3R_SHIFT)
+#define GPIO_M_SCR_07_0_G3R_RANGE                       3:3
+#define GPIO_M_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_M_SCR_07_0_G3R_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G2R_SHIFT)
+#define GPIO_M_SCR_07_0_G2R_RANGE                       2:2
+#define GPIO_M_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_M_SCR_07_0_G2R_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G1R_SHIFT)
+#define GPIO_M_SCR_07_0_G1R_RANGE                       1:1
+#define GPIO_M_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_M_SCR_07_0_G1R_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_M_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_SCR_07_0_G0R_SHIFT)
+#define GPIO_M_SCR_07_0_G0R_RANGE                       0:0
+#define GPIO_M_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_SCR_07_0_G0R_WOFFSET                     0x0
+#define GPIO_M_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_M_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_VM_00_0
+#define GPIO_N_VM_00_0                  MK_ADDR_CONST(0x2040)
+#define GPIO_N_VM_00_0_SECURE                   0x0
+#define GPIO_N_VM_00_0_DUAL                     0x0
+#define GPIO_N_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_N_VM_00_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_N_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_N_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_N_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM1_SHIFT)
+#define GPIO_N_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_N_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_N_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_N_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_N_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_N_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM2_SHIFT)
+#define GPIO_N_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_N_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_N_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_N_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_N_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_N_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM3_SHIFT)
+#define GPIO_N_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_N_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_N_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_N_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_N_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_N_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM4_SHIFT)
+#define GPIO_N_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_N_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_N_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_N_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_N_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_N_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM5_SHIFT)
+#define GPIO_N_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_N_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_N_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_N_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_N_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_N_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM6_SHIFT)
+#define GPIO_N_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_N_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_N_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_N_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_N_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_N_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM7_SHIFT)
+#define GPIO_N_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_N_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_N_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_N_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_N_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_N_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_00_0_VM8_SHIFT)
+#define GPIO_N_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_N_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_N_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_N_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_N_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_SCR_00_0
+#define GPIO_N_SCR_00_0                 MK_ADDR_CONST(0x2044)
+#define GPIO_N_SCR_00_0_SECURE                  0x0
+#define GPIO_N_SCR_00_0_DUAL                    0x0
+#define GPIO_N_SCR_00_0_SCR                     0
+#define GPIO_N_SCR_00_0_SCRREG                  0
+#define GPIO_N_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_N_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_N_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_N_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_N_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_N_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_N_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_N_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_N_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_N_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_N_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_N_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_N_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_N_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_N_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_N_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_N_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_N_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_N_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR7_SHIFT)
+#define GPIO_N_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_N_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR6_SHIFT)
+#define GPIO_N_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_N_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR5_SHIFT)
+#define GPIO_N_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_N_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR4_SHIFT)
+#define GPIO_N_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_N_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR3_SHIFT)
+#define GPIO_N_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_N_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR2_SHIFT)
+#define GPIO_N_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_N_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR1_SHIFT)
+#define GPIO_N_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_N_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_PR0_SHIFT)
+#define GPIO_N_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_N_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G7W_SHIFT)
+#define GPIO_N_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_N_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G6W_SHIFT)
+#define GPIO_N_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_N_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G5W_SHIFT)
+#define GPIO_N_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_N_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G4W_SHIFT)
+#define GPIO_N_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_N_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G3W_SHIFT)
+#define GPIO_N_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_N_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G2W_SHIFT)
+#define GPIO_N_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_N_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G1W_SHIFT)
+#define GPIO_N_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_N_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G0W_SHIFT)
+#define GPIO_N_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_N_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G7R_SHIFT)
+#define GPIO_N_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_N_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G6R_SHIFT)
+#define GPIO_N_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_N_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G5R_SHIFT)
+#define GPIO_N_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_N_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G4R_SHIFT)
+#define GPIO_N_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_N_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G3R_SHIFT)
+#define GPIO_N_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_N_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G2R_SHIFT)
+#define GPIO_N_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_N_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G1R_SHIFT)
+#define GPIO_N_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_N_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_00_0_G0R_SHIFT)
+#define GPIO_N_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_N_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_N_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_VM_01_0
+#define GPIO_N_VM_01_0                  MK_ADDR_CONST(0x2048)
+#define GPIO_N_VM_01_0_SECURE                   0x0
+#define GPIO_N_VM_01_0_DUAL                     0x0
+#define GPIO_N_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_N_VM_01_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_N_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_N_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_N_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM1_SHIFT)
+#define GPIO_N_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_N_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_N_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_N_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_N_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_N_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM2_SHIFT)
+#define GPIO_N_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_N_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_N_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_N_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_N_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_N_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM3_SHIFT)
+#define GPIO_N_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_N_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_N_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_N_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_N_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_N_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM4_SHIFT)
+#define GPIO_N_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_N_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_N_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_N_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_N_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_N_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM5_SHIFT)
+#define GPIO_N_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_N_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_N_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_N_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_N_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_N_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM6_SHIFT)
+#define GPIO_N_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_N_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_N_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_N_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_N_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_N_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM7_SHIFT)
+#define GPIO_N_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_N_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_N_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_N_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_N_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_N_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_01_0_VM8_SHIFT)
+#define GPIO_N_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_N_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_N_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_N_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_N_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_SCR_01_0
+#define GPIO_N_SCR_01_0                 MK_ADDR_CONST(0x204c)
+#define GPIO_N_SCR_01_0_SECURE                  0x0
+#define GPIO_N_SCR_01_0_DUAL                    0x0
+#define GPIO_N_SCR_01_0_SCR                     0
+#define GPIO_N_SCR_01_0_SCRREG                  0
+#define GPIO_N_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_N_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_N_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_N_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_N_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_N_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_N_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_N_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_N_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_N_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_N_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_N_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_N_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_N_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_N_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_N_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_N_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_N_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_N_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR7_SHIFT)
+#define GPIO_N_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_N_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR6_SHIFT)
+#define GPIO_N_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_N_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR5_SHIFT)
+#define GPIO_N_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_N_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR4_SHIFT)
+#define GPIO_N_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_N_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR3_SHIFT)
+#define GPIO_N_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_N_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR2_SHIFT)
+#define GPIO_N_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_N_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR1_SHIFT)
+#define GPIO_N_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_N_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_PR0_SHIFT)
+#define GPIO_N_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_N_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G7W_SHIFT)
+#define GPIO_N_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_N_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G6W_SHIFT)
+#define GPIO_N_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_N_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G5W_SHIFT)
+#define GPIO_N_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_N_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G4W_SHIFT)
+#define GPIO_N_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_N_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G3W_SHIFT)
+#define GPIO_N_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_N_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G2W_SHIFT)
+#define GPIO_N_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_N_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G1W_SHIFT)
+#define GPIO_N_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_N_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G0W_SHIFT)
+#define GPIO_N_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_N_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G7R_SHIFT)
+#define GPIO_N_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_N_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G6R_SHIFT)
+#define GPIO_N_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_N_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G5R_SHIFT)
+#define GPIO_N_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_N_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G4R_SHIFT)
+#define GPIO_N_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_N_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G3R_SHIFT)
+#define GPIO_N_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_N_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G2R_SHIFT)
+#define GPIO_N_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_N_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G1R_SHIFT)
+#define GPIO_N_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_N_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_01_0_G0R_SHIFT)
+#define GPIO_N_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_N_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_N_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_VM_02_0
+#define GPIO_N_VM_02_0                  MK_ADDR_CONST(0x2050)
+#define GPIO_N_VM_02_0_SECURE                   0x0
+#define GPIO_N_VM_02_0_DUAL                     0x0
+#define GPIO_N_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_N_VM_02_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_N_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_N_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_N_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM1_SHIFT)
+#define GPIO_N_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_N_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_N_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_N_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_N_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_N_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM2_SHIFT)
+#define GPIO_N_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_N_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_N_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_N_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_N_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_N_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM3_SHIFT)
+#define GPIO_N_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_N_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_N_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_N_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_N_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_N_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM4_SHIFT)
+#define GPIO_N_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_N_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_N_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_N_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_N_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_N_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM5_SHIFT)
+#define GPIO_N_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_N_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_N_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_N_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_N_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_N_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM6_SHIFT)
+#define GPIO_N_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_N_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_N_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_N_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_N_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_N_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM7_SHIFT)
+#define GPIO_N_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_N_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_N_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_N_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_N_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_N_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_02_0_VM8_SHIFT)
+#define GPIO_N_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_N_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_N_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_N_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_N_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_SCR_02_0
+#define GPIO_N_SCR_02_0                 MK_ADDR_CONST(0x2054)
+#define GPIO_N_SCR_02_0_SECURE                  0x0
+#define GPIO_N_SCR_02_0_DUAL                    0x0
+#define GPIO_N_SCR_02_0_SCR                     0
+#define GPIO_N_SCR_02_0_SCRREG                  0
+#define GPIO_N_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_N_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_N_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_N_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_N_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_N_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_N_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_N_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_N_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_N_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_N_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_N_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_N_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_N_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_N_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_N_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_N_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_N_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_N_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR7_SHIFT)
+#define GPIO_N_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_N_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR6_SHIFT)
+#define GPIO_N_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_N_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR5_SHIFT)
+#define GPIO_N_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_N_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR4_SHIFT)
+#define GPIO_N_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_N_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR3_SHIFT)
+#define GPIO_N_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_N_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR2_SHIFT)
+#define GPIO_N_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_N_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR1_SHIFT)
+#define GPIO_N_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_N_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_PR0_SHIFT)
+#define GPIO_N_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_N_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G7W_SHIFT)
+#define GPIO_N_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_N_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G6W_SHIFT)
+#define GPIO_N_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_N_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G5W_SHIFT)
+#define GPIO_N_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_N_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G4W_SHIFT)
+#define GPIO_N_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_N_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G3W_SHIFT)
+#define GPIO_N_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_N_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G2W_SHIFT)
+#define GPIO_N_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_N_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G1W_SHIFT)
+#define GPIO_N_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_N_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G0W_SHIFT)
+#define GPIO_N_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_N_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G7R_SHIFT)
+#define GPIO_N_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_N_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G6R_SHIFT)
+#define GPIO_N_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_N_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G5R_SHIFT)
+#define GPIO_N_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_N_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G4R_SHIFT)
+#define GPIO_N_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_N_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G3R_SHIFT)
+#define GPIO_N_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_N_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G2R_SHIFT)
+#define GPIO_N_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_N_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G1R_SHIFT)
+#define GPIO_N_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_N_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_02_0_G0R_SHIFT)
+#define GPIO_N_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_N_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_N_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_VM_03_0
+#define GPIO_N_VM_03_0                  MK_ADDR_CONST(0x2058)
+#define GPIO_N_VM_03_0_SECURE                   0x0
+#define GPIO_N_VM_03_0_DUAL                     0x0
+#define GPIO_N_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_N_VM_03_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_N_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_N_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_N_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM1_SHIFT)
+#define GPIO_N_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_N_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_N_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_N_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_N_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_N_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM2_SHIFT)
+#define GPIO_N_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_N_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_N_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_N_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_N_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_N_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM3_SHIFT)
+#define GPIO_N_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_N_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_N_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_N_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_N_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_N_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM4_SHIFT)
+#define GPIO_N_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_N_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_N_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_N_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_N_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_N_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM5_SHIFT)
+#define GPIO_N_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_N_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_N_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_N_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_N_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_N_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM6_SHIFT)
+#define GPIO_N_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_N_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_N_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_N_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_N_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_N_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM7_SHIFT)
+#define GPIO_N_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_N_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_N_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_N_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_N_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_N_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_03_0_VM8_SHIFT)
+#define GPIO_N_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_N_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_N_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_N_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_N_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_SCR_03_0
+#define GPIO_N_SCR_03_0                 MK_ADDR_CONST(0x205c)
+#define GPIO_N_SCR_03_0_SECURE                  0x0
+#define GPIO_N_SCR_03_0_DUAL                    0x0
+#define GPIO_N_SCR_03_0_SCR                     0
+#define GPIO_N_SCR_03_0_SCRREG                  0
+#define GPIO_N_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_N_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_N_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_N_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_N_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_N_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_N_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_N_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_N_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_N_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_N_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_N_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_N_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_N_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_N_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_N_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_N_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_N_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_N_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR7_SHIFT)
+#define GPIO_N_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_N_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR6_SHIFT)
+#define GPIO_N_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_N_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR5_SHIFT)
+#define GPIO_N_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_N_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR4_SHIFT)
+#define GPIO_N_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_N_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR3_SHIFT)
+#define GPIO_N_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_N_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR2_SHIFT)
+#define GPIO_N_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_N_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR1_SHIFT)
+#define GPIO_N_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_N_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_PR0_SHIFT)
+#define GPIO_N_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_N_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G7W_SHIFT)
+#define GPIO_N_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_N_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G6W_SHIFT)
+#define GPIO_N_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_N_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G5W_SHIFT)
+#define GPIO_N_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_N_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G4W_SHIFT)
+#define GPIO_N_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_N_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G3W_SHIFT)
+#define GPIO_N_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_N_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G2W_SHIFT)
+#define GPIO_N_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_N_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G1W_SHIFT)
+#define GPIO_N_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_N_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G0W_SHIFT)
+#define GPIO_N_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_N_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G7R_SHIFT)
+#define GPIO_N_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_N_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G6R_SHIFT)
+#define GPIO_N_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_N_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G5R_SHIFT)
+#define GPIO_N_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_N_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G4R_SHIFT)
+#define GPIO_N_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_N_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G3R_SHIFT)
+#define GPIO_N_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_N_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G2R_SHIFT)
+#define GPIO_N_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_N_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G1R_SHIFT)
+#define GPIO_N_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_N_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_03_0_G0R_SHIFT)
+#define GPIO_N_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_N_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_N_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_VM_04_0
+#define GPIO_N_VM_04_0                  MK_ADDR_CONST(0x2060)
+#define GPIO_N_VM_04_0_SECURE                   0x0
+#define GPIO_N_VM_04_0_DUAL                     0x0
+#define GPIO_N_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_N_VM_04_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_N_VM_04_0_WORD_COUNT                       0x1
+#define GPIO_N_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_N_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM1_SHIFT)
+#define GPIO_N_VM_04_0_VM1_RANGE                        1:0
+#define GPIO_N_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_N_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_N_VM_04_0_VM1_WOFFSET                      0x0
+#define GPIO_N_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_N_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM2_SHIFT)
+#define GPIO_N_VM_04_0_VM2_RANGE                        3:2
+#define GPIO_N_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_N_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_N_VM_04_0_VM2_WOFFSET                      0x0
+#define GPIO_N_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_N_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM3_SHIFT)
+#define GPIO_N_VM_04_0_VM3_RANGE                        5:4
+#define GPIO_N_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_N_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_N_VM_04_0_VM3_WOFFSET                      0x0
+#define GPIO_N_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_N_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM4_SHIFT)
+#define GPIO_N_VM_04_0_VM4_RANGE                        7:6
+#define GPIO_N_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_N_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_N_VM_04_0_VM4_WOFFSET                      0x0
+#define GPIO_N_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_N_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM5_SHIFT)
+#define GPIO_N_VM_04_0_VM5_RANGE                        9:8
+#define GPIO_N_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_N_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_N_VM_04_0_VM5_WOFFSET                      0x0
+#define GPIO_N_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_N_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM6_SHIFT)
+#define GPIO_N_VM_04_0_VM6_RANGE                        11:10
+#define GPIO_N_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_N_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_N_VM_04_0_VM6_WOFFSET                      0x0
+#define GPIO_N_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_N_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM7_SHIFT)
+#define GPIO_N_VM_04_0_VM7_RANGE                        13:12
+#define GPIO_N_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_N_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_N_VM_04_0_VM7_WOFFSET                      0x0
+#define GPIO_N_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_N_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_04_0_VM8_SHIFT)
+#define GPIO_N_VM_04_0_VM8_RANGE                        15:14
+#define GPIO_N_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_N_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_N_VM_04_0_VM8_WOFFSET                      0x0
+#define GPIO_N_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_SCR_04_0
+#define GPIO_N_SCR_04_0                 MK_ADDR_CONST(0x2064)
+#define GPIO_N_SCR_04_0_SECURE                  0x0
+#define GPIO_N_SCR_04_0_DUAL                    0x0
+#define GPIO_N_SCR_04_0_SCR                     0
+#define GPIO_N_SCR_04_0_SCRREG                  0
+#define GPIO_N_SCR_04_0_WORD_COUNT                      0x1
+#define GPIO_N_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_N_SCR_04_0_SEC_LCK_RANGE                   29:29
+#define GPIO_N_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_04_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_N_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_N_SCR_04_0_SEC_WEN_RANGE                   28:28
+#define GPIO_N_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_04_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_N_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_N_SCR_04_0_SEC_REN_RANGE                   27:27
+#define GPIO_N_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_04_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_N_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_N_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_N_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_N_SCR_04_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_N_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_N_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_N_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_N_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_N_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR7_SHIFT)
+#define GPIO_N_SCR_04_0_PR7_RANGE                       23:23
+#define GPIO_N_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_04_0_PR7_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR6_SHIFT)
+#define GPIO_N_SCR_04_0_PR6_RANGE                       22:22
+#define GPIO_N_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_04_0_PR6_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR5_SHIFT)
+#define GPIO_N_SCR_04_0_PR5_RANGE                       21:21
+#define GPIO_N_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_04_0_PR5_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR4_SHIFT)
+#define GPIO_N_SCR_04_0_PR4_RANGE                       20:20
+#define GPIO_N_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_04_0_PR4_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR3_SHIFT)
+#define GPIO_N_SCR_04_0_PR3_RANGE                       19:19
+#define GPIO_N_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_04_0_PR3_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR2_SHIFT)
+#define GPIO_N_SCR_04_0_PR2_RANGE                       18:18
+#define GPIO_N_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_04_0_PR2_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR1_SHIFT)
+#define GPIO_N_SCR_04_0_PR1_RANGE                       17:17
+#define GPIO_N_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_04_0_PR1_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_PR0_SHIFT)
+#define GPIO_N_SCR_04_0_PR0_RANGE                       16:16
+#define GPIO_N_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_04_0_PR0_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G7W_SHIFT)
+#define GPIO_N_SCR_04_0_G7W_RANGE                       15:15
+#define GPIO_N_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_04_0_G7W_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G6W_SHIFT)
+#define GPIO_N_SCR_04_0_G6W_RANGE                       14:14
+#define GPIO_N_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_04_0_G6W_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G5W_SHIFT)
+#define GPIO_N_SCR_04_0_G5W_RANGE                       13:13
+#define GPIO_N_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_04_0_G5W_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G4W_SHIFT)
+#define GPIO_N_SCR_04_0_G4W_RANGE                       12:12
+#define GPIO_N_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_04_0_G4W_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G3W_SHIFT)
+#define GPIO_N_SCR_04_0_G3W_RANGE                       11:11
+#define GPIO_N_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_04_0_G3W_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G2W_SHIFT)
+#define GPIO_N_SCR_04_0_G2W_RANGE                       10:10
+#define GPIO_N_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_04_0_G2W_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G1W_SHIFT)
+#define GPIO_N_SCR_04_0_G1W_RANGE                       9:9
+#define GPIO_N_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_04_0_G1W_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G0W_SHIFT)
+#define GPIO_N_SCR_04_0_G0W_RANGE                       8:8
+#define GPIO_N_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_04_0_G0W_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G7R_SHIFT)
+#define GPIO_N_SCR_04_0_G7R_RANGE                       7:7
+#define GPIO_N_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_04_0_G7R_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G6R_SHIFT)
+#define GPIO_N_SCR_04_0_G6R_RANGE                       6:6
+#define GPIO_N_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_04_0_G6R_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G5R_SHIFT)
+#define GPIO_N_SCR_04_0_G5R_RANGE                       5:5
+#define GPIO_N_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_04_0_G5R_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G4R_SHIFT)
+#define GPIO_N_SCR_04_0_G4R_RANGE                       4:4
+#define GPIO_N_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_04_0_G4R_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G3R_SHIFT)
+#define GPIO_N_SCR_04_0_G3R_RANGE                       3:3
+#define GPIO_N_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_04_0_G3R_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G2R_SHIFT)
+#define GPIO_N_SCR_04_0_G2R_RANGE                       2:2
+#define GPIO_N_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_04_0_G2R_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G1R_SHIFT)
+#define GPIO_N_SCR_04_0_G1R_RANGE                       1:1
+#define GPIO_N_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_04_0_G1R_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_04_0_G0R_SHIFT)
+#define GPIO_N_SCR_04_0_G0R_RANGE                       0:0
+#define GPIO_N_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_04_0_G0R_WOFFSET                     0x0
+#define GPIO_N_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_VM_05_0
+#define GPIO_N_VM_05_0                  MK_ADDR_CONST(0x2068)
+#define GPIO_N_VM_05_0_SECURE                   0x0
+#define GPIO_N_VM_05_0_DUAL                     0x0
+#define GPIO_N_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_N_VM_05_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_N_VM_05_0_WORD_COUNT                       0x1
+#define GPIO_N_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_N_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM1_SHIFT)
+#define GPIO_N_VM_05_0_VM1_RANGE                        1:0
+#define GPIO_N_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_N_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_N_VM_05_0_VM1_WOFFSET                      0x0
+#define GPIO_N_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_N_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM2_SHIFT)
+#define GPIO_N_VM_05_0_VM2_RANGE                        3:2
+#define GPIO_N_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_N_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_N_VM_05_0_VM2_WOFFSET                      0x0
+#define GPIO_N_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_N_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM3_SHIFT)
+#define GPIO_N_VM_05_0_VM3_RANGE                        5:4
+#define GPIO_N_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_N_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_N_VM_05_0_VM3_WOFFSET                      0x0
+#define GPIO_N_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_N_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM4_SHIFT)
+#define GPIO_N_VM_05_0_VM4_RANGE                        7:6
+#define GPIO_N_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_N_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_N_VM_05_0_VM4_WOFFSET                      0x0
+#define GPIO_N_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_N_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM5_SHIFT)
+#define GPIO_N_VM_05_0_VM5_RANGE                        9:8
+#define GPIO_N_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_N_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_N_VM_05_0_VM5_WOFFSET                      0x0
+#define GPIO_N_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_N_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM6_SHIFT)
+#define GPIO_N_VM_05_0_VM6_RANGE                        11:10
+#define GPIO_N_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_N_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_N_VM_05_0_VM6_WOFFSET                      0x0
+#define GPIO_N_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_N_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM7_SHIFT)
+#define GPIO_N_VM_05_0_VM7_RANGE                        13:12
+#define GPIO_N_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_N_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_N_VM_05_0_VM7_WOFFSET                      0x0
+#define GPIO_N_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_N_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_05_0_VM8_SHIFT)
+#define GPIO_N_VM_05_0_VM8_RANGE                        15:14
+#define GPIO_N_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_N_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_N_VM_05_0_VM8_WOFFSET                      0x0
+#define GPIO_N_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_SCR_05_0
+#define GPIO_N_SCR_05_0                 MK_ADDR_CONST(0x206c)
+#define GPIO_N_SCR_05_0_SECURE                  0x0
+#define GPIO_N_SCR_05_0_DUAL                    0x0
+#define GPIO_N_SCR_05_0_SCR                     0
+#define GPIO_N_SCR_05_0_SCRREG                  0
+#define GPIO_N_SCR_05_0_WORD_COUNT                      0x1
+#define GPIO_N_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_N_SCR_05_0_SEC_LCK_RANGE                   29:29
+#define GPIO_N_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_05_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_N_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_N_SCR_05_0_SEC_WEN_RANGE                   28:28
+#define GPIO_N_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_05_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_N_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_N_SCR_05_0_SEC_REN_RANGE                   27:27
+#define GPIO_N_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_05_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_N_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_N_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_N_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_N_SCR_05_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_N_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_N_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_N_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_N_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_N_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR7_SHIFT)
+#define GPIO_N_SCR_05_0_PR7_RANGE                       23:23
+#define GPIO_N_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_05_0_PR7_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR6_SHIFT)
+#define GPIO_N_SCR_05_0_PR6_RANGE                       22:22
+#define GPIO_N_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_05_0_PR6_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR5_SHIFT)
+#define GPIO_N_SCR_05_0_PR5_RANGE                       21:21
+#define GPIO_N_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_05_0_PR5_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR4_SHIFT)
+#define GPIO_N_SCR_05_0_PR4_RANGE                       20:20
+#define GPIO_N_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_05_0_PR4_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR3_SHIFT)
+#define GPIO_N_SCR_05_0_PR3_RANGE                       19:19
+#define GPIO_N_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_05_0_PR3_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR2_SHIFT)
+#define GPIO_N_SCR_05_0_PR2_RANGE                       18:18
+#define GPIO_N_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_05_0_PR2_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR1_SHIFT)
+#define GPIO_N_SCR_05_0_PR1_RANGE                       17:17
+#define GPIO_N_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_05_0_PR1_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_PR0_SHIFT)
+#define GPIO_N_SCR_05_0_PR0_RANGE                       16:16
+#define GPIO_N_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_05_0_PR0_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G7W_SHIFT)
+#define GPIO_N_SCR_05_0_G7W_RANGE                       15:15
+#define GPIO_N_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_05_0_G7W_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G6W_SHIFT)
+#define GPIO_N_SCR_05_0_G6W_RANGE                       14:14
+#define GPIO_N_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_05_0_G6W_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G5W_SHIFT)
+#define GPIO_N_SCR_05_0_G5W_RANGE                       13:13
+#define GPIO_N_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_05_0_G5W_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G4W_SHIFT)
+#define GPIO_N_SCR_05_0_G4W_RANGE                       12:12
+#define GPIO_N_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_05_0_G4W_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G3W_SHIFT)
+#define GPIO_N_SCR_05_0_G3W_RANGE                       11:11
+#define GPIO_N_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_05_0_G3W_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G2W_SHIFT)
+#define GPIO_N_SCR_05_0_G2W_RANGE                       10:10
+#define GPIO_N_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_05_0_G2W_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G1W_SHIFT)
+#define GPIO_N_SCR_05_0_G1W_RANGE                       9:9
+#define GPIO_N_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_05_0_G1W_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G0W_SHIFT)
+#define GPIO_N_SCR_05_0_G0W_RANGE                       8:8
+#define GPIO_N_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_05_0_G0W_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G7R_SHIFT)
+#define GPIO_N_SCR_05_0_G7R_RANGE                       7:7
+#define GPIO_N_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_05_0_G7R_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G6R_SHIFT)
+#define GPIO_N_SCR_05_0_G6R_RANGE                       6:6
+#define GPIO_N_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_05_0_G6R_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G5R_SHIFT)
+#define GPIO_N_SCR_05_0_G5R_RANGE                       5:5
+#define GPIO_N_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_05_0_G5R_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G4R_SHIFT)
+#define GPIO_N_SCR_05_0_G4R_RANGE                       4:4
+#define GPIO_N_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_05_0_G4R_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G3R_SHIFT)
+#define GPIO_N_SCR_05_0_G3R_RANGE                       3:3
+#define GPIO_N_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_05_0_G3R_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G2R_SHIFT)
+#define GPIO_N_SCR_05_0_G2R_RANGE                       2:2
+#define GPIO_N_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_05_0_G2R_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G1R_SHIFT)
+#define GPIO_N_SCR_05_0_G1R_RANGE                       1:1
+#define GPIO_N_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_05_0_G1R_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_05_0_G0R_SHIFT)
+#define GPIO_N_SCR_05_0_G0R_RANGE                       0:0
+#define GPIO_N_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_05_0_G0R_WOFFSET                     0x0
+#define GPIO_N_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_VM_06_0
+#define GPIO_N_VM_06_0                  MK_ADDR_CONST(0x2070)
+#define GPIO_N_VM_06_0_SECURE                   0x0
+#define GPIO_N_VM_06_0_DUAL                     0x0
+#define GPIO_N_VM_06_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_N_VM_06_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_N_VM_06_0_WORD_COUNT                       0x1
+#define GPIO_N_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_N_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM1_SHIFT)
+#define GPIO_N_VM_06_0_VM1_RANGE                        1:0
+#define GPIO_N_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_N_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_N_VM_06_0_VM1_WOFFSET                      0x0
+#define GPIO_N_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_N_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM2_SHIFT)
+#define GPIO_N_VM_06_0_VM2_RANGE                        3:2
+#define GPIO_N_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_N_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_N_VM_06_0_VM2_WOFFSET                      0x0
+#define GPIO_N_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_N_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM3_SHIFT)
+#define GPIO_N_VM_06_0_VM3_RANGE                        5:4
+#define GPIO_N_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_N_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_N_VM_06_0_VM3_WOFFSET                      0x0
+#define GPIO_N_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_N_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM4_SHIFT)
+#define GPIO_N_VM_06_0_VM4_RANGE                        7:6
+#define GPIO_N_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_N_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_N_VM_06_0_VM4_WOFFSET                      0x0
+#define GPIO_N_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_N_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM5_SHIFT)
+#define GPIO_N_VM_06_0_VM5_RANGE                        9:8
+#define GPIO_N_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_N_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_N_VM_06_0_VM5_WOFFSET                      0x0
+#define GPIO_N_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_N_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM6_SHIFT)
+#define GPIO_N_VM_06_0_VM6_RANGE                        11:10
+#define GPIO_N_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_N_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_N_VM_06_0_VM6_WOFFSET                      0x0
+#define GPIO_N_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_N_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM7_SHIFT)
+#define GPIO_N_VM_06_0_VM7_RANGE                        13:12
+#define GPIO_N_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_N_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_N_VM_06_0_VM7_WOFFSET                      0x0
+#define GPIO_N_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_N_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_06_0_VM8_SHIFT)
+#define GPIO_N_VM_06_0_VM8_RANGE                        15:14
+#define GPIO_N_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_N_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_N_VM_06_0_VM8_WOFFSET                      0x0
+#define GPIO_N_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_SCR_06_0
+#define GPIO_N_SCR_06_0                 MK_ADDR_CONST(0x2074)
+#define GPIO_N_SCR_06_0_SECURE                  0x0
+#define GPIO_N_SCR_06_0_DUAL                    0x0
+#define GPIO_N_SCR_06_0_SCR                     0
+#define GPIO_N_SCR_06_0_SCRREG                  0
+#define GPIO_N_SCR_06_0_WORD_COUNT                      0x1
+#define GPIO_N_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_SEC_LCK_SHIFT)
+#define GPIO_N_SCR_06_0_SEC_LCK_RANGE                   29:29
+#define GPIO_N_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_06_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_N_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_SEC_WEN_SHIFT)
+#define GPIO_N_SCR_06_0_SEC_WEN_RANGE                   28:28
+#define GPIO_N_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_06_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_N_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_SEC_REN_SHIFT)
+#define GPIO_N_SCR_06_0_SEC_REN_RANGE                   27:27
+#define GPIO_N_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_06_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_N_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_N_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_N_SCR_06_0_SEC_OWNER_SHIFT)
+#define GPIO_N_SCR_06_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_N_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_N_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_N_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_N_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_N_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR7_SHIFT)
+#define GPIO_N_SCR_06_0_PR7_RANGE                       23:23
+#define GPIO_N_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_06_0_PR7_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR6_SHIFT)
+#define GPIO_N_SCR_06_0_PR6_RANGE                       22:22
+#define GPIO_N_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_06_0_PR6_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR5_SHIFT)
+#define GPIO_N_SCR_06_0_PR5_RANGE                       21:21
+#define GPIO_N_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_06_0_PR5_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR4_SHIFT)
+#define GPIO_N_SCR_06_0_PR4_RANGE                       20:20
+#define GPIO_N_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_06_0_PR4_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR3_SHIFT)
+#define GPIO_N_SCR_06_0_PR3_RANGE                       19:19
+#define GPIO_N_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_06_0_PR3_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR2_SHIFT)
+#define GPIO_N_SCR_06_0_PR2_RANGE                       18:18
+#define GPIO_N_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_06_0_PR2_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR1_SHIFT)
+#define GPIO_N_SCR_06_0_PR1_RANGE                       17:17
+#define GPIO_N_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_06_0_PR1_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_PR0_SHIFT)
+#define GPIO_N_SCR_06_0_PR0_RANGE                       16:16
+#define GPIO_N_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_06_0_PR0_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G7W_SHIFT)
+#define GPIO_N_SCR_06_0_G7W_RANGE                       15:15
+#define GPIO_N_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_06_0_G7W_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G6W_SHIFT)
+#define GPIO_N_SCR_06_0_G6W_RANGE                       14:14
+#define GPIO_N_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_06_0_G6W_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G5W_SHIFT)
+#define GPIO_N_SCR_06_0_G5W_RANGE                       13:13
+#define GPIO_N_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_06_0_G5W_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G4W_SHIFT)
+#define GPIO_N_SCR_06_0_G4W_RANGE                       12:12
+#define GPIO_N_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_06_0_G4W_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G3W_SHIFT)
+#define GPIO_N_SCR_06_0_G3W_RANGE                       11:11
+#define GPIO_N_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_06_0_G3W_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G2W_SHIFT)
+#define GPIO_N_SCR_06_0_G2W_RANGE                       10:10
+#define GPIO_N_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_06_0_G2W_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G1W_SHIFT)
+#define GPIO_N_SCR_06_0_G1W_RANGE                       9:9
+#define GPIO_N_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_06_0_G1W_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G0W_SHIFT)
+#define GPIO_N_SCR_06_0_G0W_RANGE                       8:8
+#define GPIO_N_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_06_0_G0W_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G7R_SHIFT)
+#define GPIO_N_SCR_06_0_G7R_RANGE                       7:7
+#define GPIO_N_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_06_0_G7R_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G6R_SHIFT)
+#define GPIO_N_SCR_06_0_G6R_RANGE                       6:6
+#define GPIO_N_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_06_0_G6R_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G5R_SHIFT)
+#define GPIO_N_SCR_06_0_G5R_RANGE                       5:5
+#define GPIO_N_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_06_0_G5R_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G4R_SHIFT)
+#define GPIO_N_SCR_06_0_G4R_RANGE                       4:4
+#define GPIO_N_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_06_0_G4R_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G3R_SHIFT)
+#define GPIO_N_SCR_06_0_G3R_RANGE                       3:3
+#define GPIO_N_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_06_0_G3R_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G2R_SHIFT)
+#define GPIO_N_SCR_06_0_G2R_RANGE                       2:2
+#define GPIO_N_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_06_0_G2R_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G1R_SHIFT)
+#define GPIO_N_SCR_06_0_G1R_RANGE                       1:1
+#define GPIO_N_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_06_0_G1R_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_06_0_G0R_SHIFT)
+#define GPIO_N_SCR_06_0_G0R_RANGE                       0:0
+#define GPIO_N_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_06_0_G0R_WOFFSET                     0x0
+#define GPIO_N_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_VM_07_0
+#define GPIO_N_VM_07_0                  MK_ADDR_CONST(0x2078)
+#define GPIO_N_VM_07_0_SECURE                   0x0
+#define GPIO_N_VM_07_0_DUAL                     0x0
+#define GPIO_N_VM_07_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_N_VM_07_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_N_VM_07_0_WORD_COUNT                       0x1
+#define GPIO_N_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_N_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_N_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_07_0_VM1_SHIFT)
+#define GPIO_N_VM_07_0_VM1_RANGE                        1:0
+#define GPIO_N_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_N_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_N_VM_07_0_VM1_WOFFSET                      0x0
+#define GPIO_N_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_N_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_07_0_VM2_SHIFT)
+#define GPIO_N_VM_07_0_VM2_RANGE                        3:2
+#define GPIO_N_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_N_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_N_VM_07_0_VM2_WOFFSET                      0x0
+#define GPIO_N_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_N_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_07_0_VM3_SHIFT)
+#define GPIO_N_VM_07_0_VM3_RANGE                        5:4
+#define GPIO_N_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_N_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_N_VM_07_0_VM3_WOFFSET                      0x0
+#define GPIO_N_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_N_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_07_0_VM4_SHIFT)
+#define GPIO_N_VM_07_0_VM4_RANGE                        7:6
+#define GPIO_N_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_N_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_N_VM_07_0_VM4_WOFFSET                      0x0
+#define GPIO_N_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_N_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_07_0_VM5_SHIFT)
+#define GPIO_N_VM_07_0_VM5_RANGE                        9:8
+#define GPIO_N_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_N_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_N_VM_07_0_VM5_WOFFSET                      0x0
+#define GPIO_N_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_N_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_07_0_VM6_SHIFT)
+#define GPIO_N_VM_07_0_VM6_RANGE                        11:10
+#define GPIO_N_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_N_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_N_VM_07_0_VM6_WOFFSET                      0x0
+#define GPIO_N_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_N_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_07_0_VM7_SHIFT)
+#define GPIO_N_VM_07_0_VM7_RANGE                        13:12
+#define GPIO_N_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_N_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_N_VM_07_0_VM7_WOFFSET                      0x0
+#define GPIO_N_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_N_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_N_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_N_VM_07_0_VM8_SHIFT)
+#define GPIO_N_VM_07_0_VM8_RANGE                        15:14
+#define GPIO_N_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_N_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_N_VM_07_0_VM8_WOFFSET                      0x0
+#define GPIO_N_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_N_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_N_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_SCR_07_0
+#define GPIO_N_SCR_07_0                 MK_ADDR_CONST(0x207c)
+#define GPIO_N_SCR_07_0_SECURE                  0x0
+#define GPIO_N_SCR_07_0_DUAL                    0x0
+#define GPIO_N_SCR_07_0_SCR                     0
+#define GPIO_N_SCR_07_0_SCRREG                  0
+#define GPIO_N_SCR_07_0_WORD_COUNT                      0x1
+#define GPIO_N_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_N_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_SEC_LCK_SHIFT)
+#define GPIO_N_SCR_07_0_SEC_LCK_RANGE                   29:29
+#define GPIO_N_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_N_SCR_07_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_N_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_SEC_WEN_SHIFT)
+#define GPIO_N_SCR_07_0_SEC_WEN_RANGE                   28:28
+#define GPIO_N_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_N_SCR_07_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_N_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_SEC_REN_SHIFT)
+#define GPIO_N_SCR_07_0_SEC_REN_RANGE                   27:27
+#define GPIO_N_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_N_SCR_07_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_N_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_N_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_N_SCR_07_0_SEC_OWNER_SHIFT)
+#define GPIO_N_SCR_07_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_N_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_N_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_N_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_N_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_N_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_PR7_SHIFT)
+#define GPIO_N_SCR_07_0_PR7_RANGE                       23:23
+#define GPIO_N_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_N_SCR_07_0_PR7_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_PR6_SHIFT)
+#define GPIO_N_SCR_07_0_PR6_RANGE                       22:22
+#define GPIO_N_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_N_SCR_07_0_PR6_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_PR5_SHIFT)
+#define GPIO_N_SCR_07_0_PR5_RANGE                       21:21
+#define GPIO_N_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_N_SCR_07_0_PR5_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_PR4_SHIFT)
+#define GPIO_N_SCR_07_0_PR4_RANGE                       20:20
+#define GPIO_N_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_N_SCR_07_0_PR4_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_PR3_SHIFT)
+#define GPIO_N_SCR_07_0_PR3_RANGE                       19:19
+#define GPIO_N_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_N_SCR_07_0_PR3_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_PR2_SHIFT)
+#define GPIO_N_SCR_07_0_PR2_RANGE                       18:18
+#define GPIO_N_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_N_SCR_07_0_PR2_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_PR1_SHIFT)
+#define GPIO_N_SCR_07_0_PR1_RANGE                       17:17
+#define GPIO_N_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_N_SCR_07_0_PR1_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_PR0_SHIFT)
+#define GPIO_N_SCR_07_0_PR0_RANGE                       16:16
+#define GPIO_N_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_N_SCR_07_0_PR0_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G7W_SHIFT)
+#define GPIO_N_SCR_07_0_G7W_RANGE                       15:15
+#define GPIO_N_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_N_SCR_07_0_G7W_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G6W_SHIFT)
+#define GPIO_N_SCR_07_0_G6W_RANGE                       14:14
+#define GPIO_N_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_N_SCR_07_0_G6W_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G5W_SHIFT)
+#define GPIO_N_SCR_07_0_G5W_RANGE                       13:13
+#define GPIO_N_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_N_SCR_07_0_G5W_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G4W_SHIFT)
+#define GPIO_N_SCR_07_0_G4W_RANGE                       12:12
+#define GPIO_N_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_N_SCR_07_0_G4W_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G3W_SHIFT)
+#define GPIO_N_SCR_07_0_G3W_RANGE                       11:11
+#define GPIO_N_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_N_SCR_07_0_G3W_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G2W_SHIFT)
+#define GPIO_N_SCR_07_0_G2W_RANGE                       10:10
+#define GPIO_N_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_N_SCR_07_0_G2W_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G1W_SHIFT)
+#define GPIO_N_SCR_07_0_G1W_RANGE                       9:9
+#define GPIO_N_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_N_SCR_07_0_G1W_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G0W_SHIFT)
+#define GPIO_N_SCR_07_0_G0W_RANGE                       8:8
+#define GPIO_N_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_N_SCR_07_0_G0W_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G7R_SHIFT)
+#define GPIO_N_SCR_07_0_G7R_RANGE                       7:7
+#define GPIO_N_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_N_SCR_07_0_G7R_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G6R_SHIFT)
+#define GPIO_N_SCR_07_0_G6R_RANGE                       6:6
+#define GPIO_N_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_N_SCR_07_0_G6R_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G5R_SHIFT)
+#define GPIO_N_SCR_07_0_G5R_RANGE                       5:5
+#define GPIO_N_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_SCR_07_0_G5R_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G4R_SHIFT)
+#define GPIO_N_SCR_07_0_G4R_RANGE                       4:4
+#define GPIO_N_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_N_SCR_07_0_G4R_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G3R_SHIFT)
+#define GPIO_N_SCR_07_0_G3R_RANGE                       3:3
+#define GPIO_N_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_N_SCR_07_0_G3R_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G2R_SHIFT)
+#define GPIO_N_SCR_07_0_G2R_RANGE                       2:2
+#define GPIO_N_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_N_SCR_07_0_G2R_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G1R_SHIFT)
+#define GPIO_N_SCR_07_0_G1R_RANGE                       1:1
+#define GPIO_N_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_N_SCR_07_0_G1R_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_N_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_SCR_07_0_G0R_SHIFT)
+#define GPIO_N_SCR_07_0_G0R_RANGE                       0:0
+#define GPIO_N_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_SCR_07_0_G0R_WOFFSET                     0x0
+#define GPIO_N_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_N_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_VM_00_0
+#define GPIO_P_VM_00_0                  MK_ADDR_CONST(0x2080)
+#define GPIO_P_VM_00_0_SECURE                   0x0
+#define GPIO_P_VM_00_0_DUAL                     0x0
+#define GPIO_P_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_P_VM_00_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_P_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_P_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_P_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM1_SHIFT)
+#define GPIO_P_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_P_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_P_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_P_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_P_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_P_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM2_SHIFT)
+#define GPIO_P_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_P_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_P_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_P_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_P_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_P_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM3_SHIFT)
+#define GPIO_P_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_P_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_P_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_P_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_P_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_P_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM4_SHIFT)
+#define GPIO_P_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_P_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_P_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_P_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_P_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_P_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM5_SHIFT)
+#define GPIO_P_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_P_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_P_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_P_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_P_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_P_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM6_SHIFT)
+#define GPIO_P_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_P_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_P_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_P_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_P_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_P_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM7_SHIFT)
+#define GPIO_P_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_P_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_P_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_P_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_P_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_P_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_00_0_VM8_SHIFT)
+#define GPIO_P_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_P_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_P_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_P_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_P_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_SCR_00_0
+#define GPIO_P_SCR_00_0                 MK_ADDR_CONST(0x2084)
+#define GPIO_P_SCR_00_0_SECURE                  0x0
+#define GPIO_P_SCR_00_0_DUAL                    0x0
+#define GPIO_P_SCR_00_0_SCR                     0
+#define GPIO_P_SCR_00_0_SCRREG                  0
+#define GPIO_P_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_P_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_P_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_P_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_P_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_P_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_P_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_P_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_P_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_P_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_P_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_P_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_P_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_P_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_P_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_P_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_P_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_P_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_P_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR7_SHIFT)
+#define GPIO_P_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_P_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR6_SHIFT)
+#define GPIO_P_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_P_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR5_SHIFT)
+#define GPIO_P_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_P_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR4_SHIFT)
+#define GPIO_P_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_P_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR3_SHIFT)
+#define GPIO_P_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_P_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR2_SHIFT)
+#define GPIO_P_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_P_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR1_SHIFT)
+#define GPIO_P_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_P_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_PR0_SHIFT)
+#define GPIO_P_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_P_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G7W_SHIFT)
+#define GPIO_P_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_P_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G6W_SHIFT)
+#define GPIO_P_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_P_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G5W_SHIFT)
+#define GPIO_P_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_P_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G4W_SHIFT)
+#define GPIO_P_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_P_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G3W_SHIFT)
+#define GPIO_P_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_P_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G2W_SHIFT)
+#define GPIO_P_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_P_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G1W_SHIFT)
+#define GPIO_P_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_P_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G0W_SHIFT)
+#define GPIO_P_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_P_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G7R_SHIFT)
+#define GPIO_P_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_P_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G6R_SHIFT)
+#define GPIO_P_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_P_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G5R_SHIFT)
+#define GPIO_P_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_P_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G4R_SHIFT)
+#define GPIO_P_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_P_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G3R_SHIFT)
+#define GPIO_P_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_P_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G2R_SHIFT)
+#define GPIO_P_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_P_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G1R_SHIFT)
+#define GPIO_P_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_P_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_00_0_G0R_SHIFT)
+#define GPIO_P_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_P_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_P_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_VM_01_0
+#define GPIO_P_VM_01_0                  MK_ADDR_CONST(0x2088)
+#define GPIO_P_VM_01_0_SECURE                   0x0
+#define GPIO_P_VM_01_0_DUAL                     0x0
+#define GPIO_P_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_P_VM_01_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_P_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_P_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_P_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM1_SHIFT)
+#define GPIO_P_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_P_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_P_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_P_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_P_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_P_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM2_SHIFT)
+#define GPIO_P_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_P_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_P_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_P_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_P_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_P_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM3_SHIFT)
+#define GPIO_P_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_P_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_P_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_P_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_P_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_P_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM4_SHIFT)
+#define GPIO_P_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_P_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_P_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_P_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_P_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_P_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM5_SHIFT)
+#define GPIO_P_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_P_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_P_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_P_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_P_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_P_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM6_SHIFT)
+#define GPIO_P_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_P_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_P_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_P_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_P_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_P_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM7_SHIFT)
+#define GPIO_P_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_P_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_P_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_P_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_P_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_P_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_01_0_VM8_SHIFT)
+#define GPIO_P_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_P_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_P_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_P_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_P_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_SCR_01_0
+#define GPIO_P_SCR_01_0                 MK_ADDR_CONST(0x208c)
+#define GPIO_P_SCR_01_0_SECURE                  0x0
+#define GPIO_P_SCR_01_0_DUAL                    0x0
+#define GPIO_P_SCR_01_0_SCR                     0
+#define GPIO_P_SCR_01_0_SCRREG                  0
+#define GPIO_P_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_P_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_P_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_P_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_P_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_P_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_P_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_P_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_P_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_P_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_P_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_P_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_P_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_P_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_P_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_P_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_P_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_P_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_P_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR7_SHIFT)
+#define GPIO_P_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_P_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR6_SHIFT)
+#define GPIO_P_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_P_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR5_SHIFT)
+#define GPIO_P_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_P_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR4_SHIFT)
+#define GPIO_P_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_P_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR3_SHIFT)
+#define GPIO_P_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_P_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR2_SHIFT)
+#define GPIO_P_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_P_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR1_SHIFT)
+#define GPIO_P_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_P_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_PR0_SHIFT)
+#define GPIO_P_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_P_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G7W_SHIFT)
+#define GPIO_P_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_P_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G6W_SHIFT)
+#define GPIO_P_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_P_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G5W_SHIFT)
+#define GPIO_P_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_P_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G4W_SHIFT)
+#define GPIO_P_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_P_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G3W_SHIFT)
+#define GPIO_P_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_P_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G2W_SHIFT)
+#define GPIO_P_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_P_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G1W_SHIFT)
+#define GPIO_P_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_P_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G0W_SHIFT)
+#define GPIO_P_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_P_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G7R_SHIFT)
+#define GPIO_P_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_P_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G6R_SHIFT)
+#define GPIO_P_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_P_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G5R_SHIFT)
+#define GPIO_P_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_P_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G4R_SHIFT)
+#define GPIO_P_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_P_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G3R_SHIFT)
+#define GPIO_P_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_P_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G2R_SHIFT)
+#define GPIO_P_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_P_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G1R_SHIFT)
+#define GPIO_P_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_P_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_01_0_G0R_SHIFT)
+#define GPIO_P_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_P_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_P_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_VM_02_0
+#define GPIO_P_VM_02_0                  MK_ADDR_CONST(0x2090)
+#define GPIO_P_VM_02_0_SECURE                   0x0
+#define GPIO_P_VM_02_0_DUAL                     0x0
+#define GPIO_P_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_P_VM_02_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_P_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_P_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_P_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM1_SHIFT)
+#define GPIO_P_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_P_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_P_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_P_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_P_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_P_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM2_SHIFT)
+#define GPIO_P_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_P_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_P_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_P_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_P_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_P_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM3_SHIFT)
+#define GPIO_P_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_P_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_P_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_P_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_P_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_P_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM4_SHIFT)
+#define GPIO_P_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_P_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_P_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_P_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_P_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_P_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM5_SHIFT)
+#define GPIO_P_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_P_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_P_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_P_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_P_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_P_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM6_SHIFT)
+#define GPIO_P_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_P_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_P_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_P_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_P_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_P_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM7_SHIFT)
+#define GPIO_P_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_P_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_P_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_P_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_P_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_P_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_02_0_VM8_SHIFT)
+#define GPIO_P_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_P_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_P_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_P_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_P_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_SCR_02_0
+#define GPIO_P_SCR_02_0                 MK_ADDR_CONST(0x2094)
+#define GPIO_P_SCR_02_0_SECURE                  0x0
+#define GPIO_P_SCR_02_0_DUAL                    0x0
+#define GPIO_P_SCR_02_0_SCR                     0
+#define GPIO_P_SCR_02_0_SCRREG                  0
+#define GPIO_P_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_P_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_P_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_P_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_P_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_P_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_P_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_P_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_P_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_P_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_P_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_P_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_P_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_P_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_P_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_P_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_P_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_P_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_P_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR7_SHIFT)
+#define GPIO_P_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_P_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR6_SHIFT)
+#define GPIO_P_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_P_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR5_SHIFT)
+#define GPIO_P_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_P_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR4_SHIFT)
+#define GPIO_P_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_P_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR3_SHIFT)
+#define GPIO_P_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_P_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR2_SHIFT)
+#define GPIO_P_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_P_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR1_SHIFT)
+#define GPIO_P_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_P_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_PR0_SHIFT)
+#define GPIO_P_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_P_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G7W_SHIFT)
+#define GPIO_P_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_P_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G6W_SHIFT)
+#define GPIO_P_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_P_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G5W_SHIFT)
+#define GPIO_P_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_P_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G4W_SHIFT)
+#define GPIO_P_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_P_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G3W_SHIFT)
+#define GPIO_P_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_P_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G2W_SHIFT)
+#define GPIO_P_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_P_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G1W_SHIFT)
+#define GPIO_P_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_P_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G0W_SHIFT)
+#define GPIO_P_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_P_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G7R_SHIFT)
+#define GPIO_P_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_P_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G6R_SHIFT)
+#define GPIO_P_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_P_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G5R_SHIFT)
+#define GPIO_P_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_P_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G4R_SHIFT)
+#define GPIO_P_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_P_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G3R_SHIFT)
+#define GPIO_P_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_P_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G2R_SHIFT)
+#define GPIO_P_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_P_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G1R_SHIFT)
+#define GPIO_P_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_P_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_02_0_G0R_SHIFT)
+#define GPIO_P_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_P_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_P_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_VM_03_0
+#define GPIO_P_VM_03_0                  MK_ADDR_CONST(0x2098)
+#define GPIO_P_VM_03_0_SECURE                   0x0
+#define GPIO_P_VM_03_0_DUAL                     0x0
+#define GPIO_P_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_P_VM_03_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_P_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_P_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_P_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM1_SHIFT)
+#define GPIO_P_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_P_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_P_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_P_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_P_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_P_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM2_SHIFT)
+#define GPIO_P_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_P_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_P_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_P_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_P_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_P_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM3_SHIFT)
+#define GPIO_P_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_P_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_P_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_P_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_P_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_P_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM4_SHIFT)
+#define GPIO_P_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_P_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_P_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_P_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_P_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_P_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM5_SHIFT)
+#define GPIO_P_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_P_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_P_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_P_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_P_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_P_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM6_SHIFT)
+#define GPIO_P_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_P_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_P_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_P_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_P_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_P_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM7_SHIFT)
+#define GPIO_P_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_P_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_P_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_P_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_P_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_P_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_03_0_VM8_SHIFT)
+#define GPIO_P_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_P_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_P_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_P_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_P_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_SCR_03_0
+#define GPIO_P_SCR_03_0                 MK_ADDR_CONST(0x209c)
+#define GPIO_P_SCR_03_0_SECURE                  0x0
+#define GPIO_P_SCR_03_0_DUAL                    0x0
+#define GPIO_P_SCR_03_0_SCR                     0
+#define GPIO_P_SCR_03_0_SCRREG                  0
+#define GPIO_P_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_P_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_P_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_P_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_P_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_P_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_P_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_P_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_P_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_P_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_P_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_P_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_P_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_P_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_P_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_P_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_P_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_P_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_P_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR7_SHIFT)
+#define GPIO_P_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_P_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR6_SHIFT)
+#define GPIO_P_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_P_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR5_SHIFT)
+#define GPIO_P_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_P_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR4_SHIFT)
+#define GPIO_P_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_P_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR3_SHIFT)
+#define GPIO_P_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_P_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR2_SHIFT)
+#define GPIO_P_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_P_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR1_SHIFT)
+#define GPIO_P_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_P_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_PR0_SHIFT)
+#define GPIO_P_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_P_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G7W_SHIFT)
+#define GPIO_P_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_P_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G6W_SHIFT)
+#define GPIO_P_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_P_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G5W_SHIFT)
+#define GPIO_P_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_P_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G4W_SHIFT)
+#define GPIO_P_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_P_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G3W_SHIFT)
+#define GPIO_P_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_P_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G2W_SHIFT)
+#define GPIO_P_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_P_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G1W_SHIFT)
+#define GPIO_P_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_P_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G0W_SHIFT)
+#define GPIO_P_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_P_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G7R_SHIFT)
+#define GPIO_P_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_P_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G6R_SHIFT)
+#define GPIO_P_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_P_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G5R_SHIFT)
+#define GPIO_P_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_P_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G4R_SHIFT)
+#define GPIO_P_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_P_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G3R_SHIFT)
+#define GPIO_P_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_P_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G2R_SHIFT)
+#define GPIO_P_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_P_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G1R_SHIFT)
+#define GPIO_P_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_P_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_03_0_G0R_SHIFT)
+#define GPIO_P_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_P_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_P_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_VM_04_0
+#define GPIO_P_VM_04_0                  MK_ADDR_CONST(0x20a0)
+#define GPIO_P_VM_04_0_SECURE                   0x0
+#define GPIO_P_VM_04_0_DUAL                     0x0
+#define GPIO_P_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_P_VM_04_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_P_VM_04_0_WORD_COUNT                       0x1
+#define GPIO_P_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_P_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM1_SHIFT)
+#define GPIO_P_VM_04_0_VM1_RANGE                        1:0
+#define GPIO_P_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_P_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_P_VM_04_0_VM1_WOFFSET                      0x0
+#define GPIO_P_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_P_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM2_SHIFT)
+#define GPIO_P_VM_04_0_VM2_RANGE                        3:2
+#define GPIO_P_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_P_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_P_VM_04_0_VM2_WOFFSET                      0x0
+#define GPIO_P_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_P_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM3_SHIFT)
+#define GPIO_P_VM_04_0_VM3_RANGE                        5:4
+#define GPIO_P_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_P_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_P_VM_04_0_VM3_WOFFSET                      0x0
+#define GPIO_P_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_P_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM4_SHIFT)
+#define GPIO_P_VM_04_0_VM4_RANGE                        7:6
+#define GPIO_P_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_P_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_P_VM_04_0_VM4_WOFFSET                      0x0
+#define GPIO_P_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_P_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM5_SHIFT)
+#define GPIO_P_VM_04_0_VM5_RANGE                        9:8
+#define GPIO_P_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_P_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_P_VM_04_0_VM5_WOFFSET                      0x0
+#define GPIO_P_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_P_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM6_SHIFT)
+#define GPIO_P_VM_04_0_VM6_RANGE                        11:10
+#define GPIO_P_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_P_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_P_VM_04_0_VM6_WOFFSET                      0x0
+#define GPIO_P_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_P_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM7_SHIFT)
+#define GPIO_P_VM_04_0_VM7_RANGE                        13:12
+#define GPIO_P_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_P_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_P_VM_04_0_VM7_WOFFSET                      0x0
+#define GPIO_P_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_P_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_04_0_VM8_SHIFT)
+#define GPIO_P_VM_04_0_VM8_RANGE                        15:14
+#define GPIO_P_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_P_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_P_VM_04_0_VM8_WOFFSET                      0x0
+#define GPIO_P_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_SCR_04_0
+#define GPIO_P_SCR_04_0                 MK_ADDR_CONST(0x20a4)
+#define GPIO_P_SCR_04_0_SECURE                  0x0
+#define GPIO_P_SCR_04_0_DUAL                    0x0
+#define GPIO_P_SCR_04_0_SCR                     0
+#define GPIO_P_SCR_04_0_SCRREG                  0
+#define GPIO_P_SCR_04_0_WORD_COUNT                      0x1
+#define GPIO_P_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_P_SCR_04_0_SEC_LCK_RANGE                   29:29
+#define GPIO_P_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_04_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_P_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_P_SCR_04_0_SEC_WEN_RANGE                   28:28
+#define GPIO_P_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_04_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_P_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_P_SCR_04_0_SEC_REN_RANGE                   27:27
+#define GPIO_P_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_04_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_P_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_P_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_P_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_P_SCR_04_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_P_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_P_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_P_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_P_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_P_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR7_SHIFT)
+#define GPIO_P_SCR_04_0_PR7_RANGE                       23:23
+#define GPIO_P_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_04_0_PR7_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR6_SHIFT)
+#define GPIO_P_SCR_04_0_PR6_RANGE                       22:22
+#define GPIO_P_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_04_0_PR6_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR5_SHIFT)
+#define GPIO_P_SCR_04_0_PR5_RANGE                       21:21
+#define GPIO_P_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_04_0_PR5_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR4_SHIFT)
+#define GPIO_P_SCR_04_0_PR4_RANGE                       20:20
+#define GPIO_P_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_04_0_PR4_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR3_SHIFT)
+#define GPIO_P_SCR_04_0_PR3_RANGE                       19:19
+#define GPIO_P_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_04_0_PR3_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR2_SHIFT)
+#define GPIO_P_SCR_04_0_PR2_RANGE                       18:18
+#define GPIO_P_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_04_0_PR2_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR1_SHIFT)
+#define GPIO_P_SCR_04_0_PR1_RANGE                       17:17
+#define GPIO_P_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_04_0_PR1_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_PR0_SHIFT)
+#define GPIO_P_SCR_04_0_PR0_RANGE                       16:16
+#define GPIO_P_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_04_0_PR0_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G7W_SHIFT)
+#define GPIO_P_SCR_04_0_G7W_RANGE                       15:15
+#define GPIO_P_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_04_0_G7W_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G6W_SHIFT)
+#define GPIO_P_SCR_04_0_G6W_RANGE                       14:14
+#define GPIO_P_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_04_0_G6W_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G5W_SHIFT)
+#define GPIO_P_SCR_04_0_G5W_RANGE                       13:13
+#define GPIO_P_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_04_0_G5W_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G4W_SHIFT)
+#define GPIO_P_SCR_04_0_G4W_RANGE                       12:12
+#define GPIO_P_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_04_0_G4W_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G3W_SHIFT)
+#define GPIO_P_SCR_04_0_G3W_RANGE                       11:11
+#define GPIO_P_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_04_0_G3W_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G2W_SHIFT)
+#define GPIO_P_SCR_04_0_G2W_RANGE                       10:10
+#define GPIO_P_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_04_0_G2W_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G1W_SHIFT)
+#define GPIO_P_SCR_04_0_G1W_RANGE                       9:9
+#define GPIO_P_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_04_0_G1W_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G0W_SHIFT)
+#define GPIO_P_SCR_04_0_G0W_RANGE                       8:8
+#define GPIO_P_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_04_0_G0W_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G7R_SHIFT)
+#define GPIO_P_SCR_04_0_G7R_RANGE                       7:7
+#define GPIO_P_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_04_0_G7R_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G6R_SHIFT)
+#define GPIO_P_SCR_04_0_G6R_RANGE                       6:6
+#define GPIO_P_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_04_0_G6R_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G5R_SHIFT)
+#define GPIO_P_SCR_04_0_G5R_RANGE                       5:5
+#define GPIO_P_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_04_0_G5R_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G4R_SHIFT)
+#define GPIO_P_SCR_04_0_G4R_RANGE                       4:4
+#define GPIO_P_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_04_0_G4R_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G3R_SHIFT)
+#define GPIO_P_SCR_04_0_G3R_RANGE                       3:3
+#define GPIO_P_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_04_0_G3R_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G2R_SHIFT)
+#define GPIO_P_SCR_04_0_G2R_RANGE                       2:2
+#define GPIO_P_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_04_0_G2R_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G1R_SHIFT)
+#define GPIO_P_SCR_04_0_G1R_RANGE                       1:1
+#define GPIO_P_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_04_0_G1R_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_04_0_G0R_SHIFT)
+#define GPIO_P_SCR_04_0_G0R_RANGE                       0:0
+#define GPIO_P_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_04_0_G0R_WOFFSET                     0x0
+#define GPIO_P_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_VM_05_0
+#define GPIO_P_VM_05_0                  MK_ADDR_CONST(0x20a8)
+#define GPIO_P_VM_05_0_SECURE                   0x0
+#define GPIO_P_VM_05_0_DUAL                     0x0
+#define GPIO_P_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_P_VM_05_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_P_VM_05_0_WORD_COUNT                       0x1
+#define GPIO_P_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_P_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM1_SHIFT)
+#define GPIO_P_VM_05_0_VM1_RANGE                        1:0
+#define GPIO_P_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_P_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_P_VM_05_0_VM1_WOFFSET                      0x0
+#define GPIO_P_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_P_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM2_SHIFT)
+#define GPIO_P_VM_05_0_VM2_RANGE                        3:2
+#define GPIO_P_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_P_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_P_VM_05_0_VM2_WOFFSET                      0x0
+#define GPIO_P_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_P_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM3_SHIFT)
+#define GPIO_P_VM_05_0_VM3_RANGE                        5:4
+#define GPIO_P_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_P_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_P_VM_05_0_VM3_WOFFSET                      0x0
+#define GPIO_P_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_P_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM4_SHIFT)
+#define GPIO_P_VM_05_0_VM4_RANGE                        7:6
+#define GPIO_P_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_P_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_P_VM_05_0_VM4_WOFFSET                      0x0
+#define GPIO_P_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_P_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM5_SHIFT)
+#define GPIO_P_VM_05_0_VM5_RANGE                        9:8
+#define GPIO_P_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_P_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_P_VM_05_0_VM5_WOFFSET                      0x0
+#define GPIO_P_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_P_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM6_SHIFT)
+#define GPIO_P_VM_05_0_VM6_RANGE                        11:10
+#define GPIO_P_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_P_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_P_VM_05_0_VM6_WOFFSET                      0x0
+#define GPIO_P_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_P_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM7_SHIFT)
+#define GPIO_P_VM_05_0_VM7_RANGE                        13:12
+#define GPIO_P_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_P_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_P_VM_05_0_VM7_WOFFSET                      0x0
+#define GPIO_P_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_P_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_05_0_VM8_SHIFT)
+#define GPIO_P_VM_05_0_VM8_RANGE                        15:14
+#define GPIO_P_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_P_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_P_VM_05_0_VM8_WOFFSET                      0x0
+#define GPIO_P_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_SCR_05_0
+#define GPIO_P_SCR_05_0                 MK_ADDR_CONST(0x20ac)
+#define GPIO_P_SCR_05_0_SECURE                  0x0
+#define GPIO_P_SCR_05_0_DUAL                    0x0
+#define GPIO_P_SCR_05_0_SCR                     0
+#define GPIO_P_SCR_05_0_SCRREG                  0
+#define GPIO_P_SCR_05_0_WORD_COUNT                      0x1
+#define GPIO_P_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_P_SCR_05_0_SEC_LCK_RANGE                   29:29
+#define GPIO_P_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_05_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_P_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_P_SCR_05_0_SEC_WEN_RANGE                   28:28
+#define GPIO_P_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_05_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_P_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_P_SCR_05_0_SEC_REN_RANGE                   27:27
+#define GPIO_P_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_05_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_P_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_P_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_P_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_P_SCR_05_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_P_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_P_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_P_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_P_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_P_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR7_SHIFT)
+#define GPIO_P_SCR_05_0_PR7_RANGE                       23:23
+#define GPIO_P_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_05_0_PR7_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR6_SHIFT)
+#define GPIO_P_SCR_05_0_PR6_RANGE                       22:22
+#define GPIO_P_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_05_0_PR6_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR5_SHIFT)
+#define GPIO_P_SCR_05_0_PR5_RANGE                       21:21
+#define GPIO_P_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_05_0_PR5_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR4_SHIFT)
+#define GPIO_P_SCR_05_0_PR4_RANGE                       20:20
+#define GPIO_P_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_05_0_PR4_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR3_SHIFT)
+#define GPIO_P_SCR_05_0_PR3_RANGE                       19:19
+#define GPIO_P_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_05_0_PR3_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR2_SHIFT)
+#define GPIO_P_SCR_05_0_PR2_RANGE                       18:18
+#define GPIO_P_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_05_0_PR2_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR1_SHIFT)
+#define GPIO_P_SCR_05_0_PR1_RANGE                       17:17
+#define GPIO_P_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_05_0_PR1_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_PR0_SHIFT)
+#define GPIO_P_SCR_05_0_PR0_RANGE                       16:16
+#define GPIO_P_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_05_0_PR0_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G7W_SHIFT)
+#define GPIO_P_SCR_05_0_G7W_RANGE                       15:15
+#define GPIO_P_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_05_0_G7W_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G6W_SHIFT)
+#define GPIO_P_SCR_05_0_G6W_RANGE                       14:14
+#define GPIO_P_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_05_0_G6W_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G5W_SHIFT)
+#define GPIO_P_SCR_05_0_G5W_RANGE                       13:13
+#define GPIO_P_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_05_0_G5W_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G4W_SHIFT)
+#define GPIO_P_SCR_05_0_G4W_RANGE                       12:12
+#define GPIO_P_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_05_0_G4W_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G3W_SHIFT)
+#define GPIO_P_SCR_05_0_G3W_RANGE                       11:11
+#define GPIO_P_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_05_0_G3W_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G2W_SHIFT)
+#define GPIO_P_SCR_05_0_G2W_RANGE                       10:10
+#define GPIO_P_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_05_0_G2W_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G1W_SHIFT)
+#define GPIO_P_SCR_05_0_G1W_RANGE                       9:9
+#define GPIO_P_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_05_0_G1W_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G0W_SHIFT)
+#define GPIO_P_SCR_05_0_G0W_RANGE                       8:8
+#define GPIO_P_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_05_0_G0W_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G7R_SHIFT)
+#define GPIO_P_SCR_05_0_G7R_RANGE                       7:7
+#define GPIO_P_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_05_0_G7R_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G6R_SHIFT)
+#define GPIO_P_SCR_05_0_G6R_RANGE                       6:6
+#define GPIO_P_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_05_0_G6R_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G5R_SHIFT)
+#define GPIO_P_SCR_05_0_G5R_RANGE                       5:5
+#define GPIO_P_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_05_0_G5R_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G4R_SHIFT)
+#define GPIO_P_SCR_05_0_G4R_RANGE                       4:4
+#define GPIO_P_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_05_0_G4R_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G3R_SHIFT)
+#define GPIO_P_SCR_05_0_G3R_RANGE                       3:3
+#define GPIO_P_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_05_0_G3R_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G2R_SHIFT)
+#define GPIO_P_SCR_05_0_G2R_RANGE                       2:2
+#define GPIO_P_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_05_0_G2R_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G1R_SHIFT)
+#define GPIO_P_SCR_05_0_G1R_RANGE                       1:1
+#define GPIO_P_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_05_0_G1R_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_05_0_G0R_SHIFT)
+#define GPIO_P_SCR_05_0_G0R_RANGE                       0:0
+#define GPIO_P_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_05_0_G0R_WOFFSET                     0x0
+#define GPIO_P_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_VM_06_0
+#define GPIO_P_VM_06_0                  MK_ADDR_CONST(0x20b0)
+#define GPIO_P_VM_06_0_SECURE                   0x0
+#define GPIO_P_VM_06_0_DUAL                     0x0
+#define GPIO_P_VM_06_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_P_VM_06_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_P_VM_06_0_WORD_COUNT                       0x1
+#define GPIO_P_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_P_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM1_SHIFT)
+#define GPIO_P_VM_06_0_VM1_RANGE                        1:0
+#define GPIO_P_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_P_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_P_VM_06_0_VM1_WOFFSET                      0x0
+#define GPIO_P_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_P_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM2_SHIFT)
+#define GPIO_P_VM_06_0_VM2_RANGE                        3:2
+#define GPIO_P_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_P_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_P_VM_06_0_VM2_WOFFSET                      0x0
+#define GPIO_P_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_P_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM3_SHIFT)
+#define GPIO_P_VM_06_0_VM3_RANGE                        5:4
+#define GPIO_P_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_P_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_P_VM_06_0_VM3_WOFFSET                      0x0
+#define GPIO_P_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_P_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM4_SHIFT)
+#define GPIO_P_VM_06_0_VM4_RANGE                        7:6
+#define GPIO_P_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_P_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_P_VM_06_0_VM4_WOFFSET                      0x0
+#define GPIO_P_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_P_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM5_SHIFT)
+#define GPIO_P_VM_06_0_VM5_RANGE                        9:8
+#define GPIO_P_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_P_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_P_VM_06_0_VM5_WOFFSET                      0x0
+#define GPIO_P_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_P_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM6_SHIFT)
+#define GPIO_P_VM_06_0_VM6_RANGE                        11:10
+#define GPIO_P_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_P_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_P_VM_06_0_VM6_WOFFSET                      0x0
+#define GPIO_P_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_P_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM7_SHIFT)
+#define GPIO_P_VM_06_0_VM7_RANGE                        13:12
+#define GPIO_P_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_P_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_P_VM_06_0_VM7_WOFFSET                      0x0
+#define GPIO_P_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_P_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_06_0_VM8_SHIFT)
+#define GPIO_P_VM_06_0_VM8_RANGE                        15:14
+#define GPIO_P_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_P_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_P_VM_06_0_VM8_WOFFSET                      0x0
+#define GPIO_P_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_SCR_06_0
+#define GPIO_P_SCR_06_0                 MK_ADDR_CONST(0x20b4)
+#define GPIO_P_SCR_06_0_SECURE                  0x0
+#define GPIO_P_SCR_06_0_DUAL                    0x0
+#define GPIO_P_SCR_06_0_SCR                     0
+#define GPIO_P_SCR_06_0_SCRREG                  0
+#define GPIO_P_SCR_06_0_WORD_COUNT                      0x1
+#define GPIO_P_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_SEC_LCK_SHIFT)
+#define GPIO_P_SCR_06_0_SEC_LCK_RANGE                   29:29
+#define GPIO_P_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_06_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_P_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_SEC_WEN_SHIFT)
+#define GPIO_P_SCR_06_0_SEC_WEN_RANGE                   28:28
+#define GPIO_P_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_06_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_P_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_SEC_REN_SHIFT)
+#define GPIO_P_SCR_06_0_SEC_REN_RANGE                   27:27
+#define GPIO_P_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_06_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_P_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_P_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_P_SCR_06_0_SEC_OWNER_SHIFT)
+#define GPIO_P_SCR_06_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_P_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_P_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_P_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_P_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_P_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR7_SHIFT)
+#define GPIO_P_SCR_06_0_PR7_RANGE                       23:23
+#define GPIO_P_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_06_0_PR7_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR6_SHIFT)
+#define GPIO_P_SCR_06_0_PR6_RANGE                       22:22
+#define GPIO_P_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_06_0_PR6_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR5_SHIFT)
+#define GPIO_P_SCR_06_0_PR5_RANGE                       21:21
+#define GPIO_P_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_06_0_PR5_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR4_SHIFT)
+#define GPIO_P_SCR_06_0_PR4_RANGE                       20:20
+#define GPIO_P_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_06_0_PR4_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR3_SHIFT)
+#define GPIO_P_SCR_06_0_PR3_RANGE                       19:19
+#define GPIO_P_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_06_0_PR3_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR2_SHIFT)
+#define GPIO_P_SCR_06_0_PR2_RANGE                       18:18
+#define GPIO_P_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_06_0_PR2_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR1_SHIFT)
+#define GPIO_P_SCR_06_0_PR1_RANGE                       17:17
+#define GPIO_P_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_06_0_PR1_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_PR0_SHIFT)
+#define GPIO_P_SCR_06_0_PR0_RANGE                       16:16
+#define GPIO_P_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_06_0_PR0_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G7W_SHIFT)
+#define GPIO_P_SCR_06_0_G7W_RANGE                       15:15
+#define GPIO_P_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_06_0_G7W_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G6W_SHIFT)
+#define GPIO_P_SCR_06_0_G6W_RANGE                       14:14
+#define GPIO_P_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_06_0_G6W_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G5W_SHIFT)
+#define GPIO_P_SCR_06_0_G5W_RANGE                       13:13
+#define GPIO_P_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_06_0_G5W_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G4W_SHIFT)
+#define GPIO_P_SCR_06_0_G4W_RANGE                       12:12
+#define GPIO_P_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_06_0_G4W_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G3W_SHIFT)
+#define GPIO_P_SCR_06_0_G3W_RANGE                       11:11
+#define GPIO_P_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_06_0_G3W_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G2W_SHIFT)
+#define GPIO_P_SCR_06_0_G2W_RANGE                       10:10
+#define GPIO_P_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_06_0_G2W_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G1W_SHIFT)
+#define GPIO_P_SCR_06_0_G1W_RANGE                       9:9
+#define GPIO_P_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_06_0_G1W_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G0W_SHIFT)
+#define GPIO_P_SCR_06_0_G0W_RANGE                       8:8
+#define GPIO_P_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_06_0_G0W_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G7R_SHIFT)
+#define GPIO_P_SCR_06_0_G7R_RANGE                       7:7
+#define GPIO_P_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_06_0_G7R_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G6R_SHIFT)
+#define GPIO_P_SCR_06_0_G6R_RANGE                       6:6
+#define GPIO_P_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_06_0_G6R_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G5R_SHIFT)
+#define GPIO_P_SCR_06_0_G5R_RANGE                       5:5
+#define GPIO_P_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_06_0_G5R_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G4R_SHIFT)
+#define GPIO_P_SCR_06_0_G4R_RANGE                       4:4
+#define GPIO_P_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_06_0_G4R_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G3R_SHIFT)
+#define GPIO_P_SCR_06_0_G3R_RANGE                       3:3
+#define GPIO_P_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_06_0_G3R_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G2R_SHIFT)
+#define GPIO_P_SCR_06_0_G2R_RANGE                       2:2
+#define GPIO_P_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_06_0_G2R_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G1R_SHIFT)
+#define GPIO_P_SCR_06_0_G1R_RANGE                       1:1
+#define GPIO_P_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_06_0_G1R_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_06_0_G0R_SHIFT)
+#define GPIO_P_SCR_06_0_G0R_RANGE                       0:0
+#define GPIO_P_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_06_0_G0R_WOFFSET                     0x0
+#define GPIO_P_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_VM_07_0
+#define GPIO_P_VM_07_0                  MK_ADDR_CONST(0x20b8)
+#define GPIO_P_VM_07_0_SECURE                   0x0
+#define GPIO_P_VM_07_0_DUAL                     0x0
+#define GPIO_P_VM_07_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_P_VM_07_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_P_VM_07_0_WORD_COUNT                       0x1
+#define GPIO_P_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_P_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_P_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM1_SHIFT)
+#define GPIO_P_VM_07_0_VM1_RANGE                        1:0
+#define GPIO_P_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_P_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_P_VM_07_0_VM1_WOFFSET                      0x0
+#define GPIO_P_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_P_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM2_SHIFT)
+#define GPIO_P_VM_07_0_VM2_RANGE                        3:2
+#define GPIO_P_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_P_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_P_VM_07_0_VM2_WOFFSET                      0x0
+#define GPIO_P_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_P_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM3_SHIFT)
+#define GPIO_P_VM_07_0_VM3_RANGE                        5:4
+#define GPIO_P_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_P_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_P_VM_07_0_VM3_WOFFSET                      0x0
+#define GPIO_P_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_P_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM4_SHIFT)
+#define GPIO_P_VM_07_0_VM4_RANGE                        7:6
+#define GPIO_P_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_P_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_P_VM_07_0_VM4_WOFFSET                      0x0
+#define GPIO_P_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_P_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM5_SHIFT)
+#define GPIO_P_VM_07_0_VM5_RANGE                        9:8
+#define GPIO_P_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_P_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_P_VM_07_0_VM5_WOFFSET                      0x0
+#define GPIO_P_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_P_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM6_SHIFT)
+#define GPIO_P_VM_07_0_VM6_RANGE                        11:10
+#define GPIO_P_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_P_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_P_VM_07_0_VM6_WOFFSET                      0x0
+#define GPIO_P_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_P_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM7_SHIFT)
+#define GPIO_P_VM_07_0_VM7_RANGE                        13:12
+#define GPIO_P_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_P_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_P_VM_07_0_VM7_WOFFSET                      0x0
+#define GPIO_P_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_P_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_P_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_P_VM_07_0_VM8_SHIFT)
+#define GPIO_P_VM_07_0_VM8_RANGE                        15:14
+#define GPIO_P_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_P_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_P_VM_07_0_VM8_WOFFSET                      0x0
+#define GPIO_P_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_P_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_P_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_SCR_07_0
+#define GPIO_P_SCR_07_0                 MK_ADDR_CONST(0x20bc)
+#define GPIO_P_SCR_07_0_SECURE                  0x0
+#define GPIO_P_SCR_07_0_DUAL                    0x0
+#define GPIO_P_SCR_07_0_SCR                     0
+#define GPIO_P_SCR_07_0_SCRREG                  0
+#define GPIO_P_SCR_07_0_WORD_COUNT                      0x1
+#define GPIO_P_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_P_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_SEC_LCK_SHIFT)
+#define GPIO_P_SCR_07_0_SEC_LCK_RANGE                   29:29
+#define GPIO_P_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_P_SCR_07_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_P_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_SEC_WEN_SHIFT)
+#define GPIO_P_SCR_07_0_SEC_WEN_RANGE                   28:28
+#define GPIO_P_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_P_SCR_07_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_P_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_SEC_REN_SHIFT)
+#define GPIO_P_SCR_07_0_SEC_REN_RANGE                   27:27
+#define GPIO_P_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_P_SCR_07_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_P_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_P_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_P_SCR_07_0_SEC_OWNER_SHIFT)
+#define GPIO_P_SCR_07_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_P_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_P_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_P_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_P_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_P_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR7_SHIFT)
+#define GPIO_P_SCR_07_0_PR7_RANGE                       23:23
+#define GPIO_P_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_P_SCR_07_0_PR7_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR6_SHIFT)
+#define GPIO_P_SCR_07_0_PR6_RANGE                       22:22
+#define GPIO_P_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_P_SCR_07_0_PR6_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR5_SHIFT)
+#define GPIO_P_SCR_07_0_PR5_RANGE                       21:21
+#define GPIO_P_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_P_SCR_07_0_PR5_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR4_SHIFT)
+#define GPIO_P_SCR_07_0_PR4_RANGE                       20:20
+#define GPIO_P_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_P_SCR_07_0_PR4_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR3_SHIFT)
+#define GPIO_P_SCR_07_0_PR3_RANGE                       19:19
+#define GPIO_P_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_P_SCR_07_0_PR3_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR2_SHIFT)
+#define GPIO_P_SCR_07_0_PR2_RANGE                       18:18
+#define GPIO_P_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_P_SCR_07_0_PR2_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR1_SHIFT)
+#define GPIO_P_SCR_07_0_PR1_RANGE                       17:17
+#define GPIO_P_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_P_SCR_07_0_PR1_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_PR0_SHIFT)
+#define GPIO_P_SCR_07_0_PR0_RANGE                       16:16
+#define GPIO_P_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_P_SCR_07_0_PR0_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G7W_SHIFT)
+#define GPIO_P_SCR_07_0_G7W_RANGE                       15:15
+#define GPIO_P_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_P_SCR_07_0_G7W_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G6W_SHIFT)
+#define GPIO_P_SCR_07_0_G6W_RANGE                       14:14
+#define GPIO_P_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_P_SCR_07_0_G6W_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G5W_SHIFT)
+#define GPIO_P_SCR_07_0_G5W_RANGE                       13:13
+#define GPIO_P_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_P_SCR_07_0_G5W_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G4W_SHIFT)
+#define GPIO_P_SCR_07_0_G4W_RANGE                       12:12
+#define GPIO_P_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_P_SCR_07_0_G4W_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G3W_SHIFT)
+#define GPIO_P_SCR_07_0_G3W_RANGE                       11:11
+#define GPIO_P_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_P_SCR_07_0_G3W_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G2W_SHIFT)
+#define GPIO_P_SCR_07_0_G2W_RANGE                       10:10
+#define GPIO_P_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_P_SCR_07_0_G2W_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G1W_SHIFT)
+#define GPIO_P_SCR_07_0_G1W_RANGE                       9:9
+#define GPIO_P_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_P_SCR_07_0_G1W_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G0W_SHIFT)
+#define GPIO_P_SCR_07_0_G0W_RANGE                       8:8
+#define GPIO_P_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_P_SCR_07_0_G0W_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G7R_SHIFT)
+#define GPIO_P_SCR_07_0_G7R_RANGE                       7:7
+#define GPIO_P_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_P_SCR_07_0_G7R_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G6R_SHIFT)
+#define GPIO_P_SCR_07_0_G6R_RANGE                       6:6
+#define GPIO_P_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_P_SCR_07_0_G6R_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G5R_SHIFT)
+#define GPIO_P_SCR_07_0_G5R_RANGE                       5:5
+#define GPIO_P_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_SCR_07_0_G5R_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G4R_SHIFT)
+#define GPIO_P_SCR_07_0_G4R_RANGE                       4:4
+#define GPIO_P_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_P_SCR_07_0_G4R_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G3R_SHIFT)
+#define GPIO_P_SCR_07_0_G3R_RANGE                       3:3
+#define GPIO_P_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_P_SCR_07_0_G3R_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G2R_SHIFT)
+#define GPIO_P_SCR_07_0_G2R_RANGE                       2:2
+#define GPIO_P_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_P_SCR_07_0_G2R_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G1R_SHIFT)
+#define GPIO_P_SCR_07_0_G1R_RANGE                       1:1
+#define GPIO_P_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_P_SCR_07_0_G1R_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_P_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_SCR_07_0_G0R_SHIFT)
+#define GPIO_P_SCR_07_0_G0R_RANGE                       0:0
+#define GPIO_P_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_SCR_07_0_G0R_WOFFSET                     0x0
+#define GPIO_P_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_P_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_VM_00_0
+#define GPIO_Q_VM_00_0                  MK_ADDR_CONST(0x20c0)
+#define GPIO_Q_VM_00_0_SECURE                   0x0
+#define GPIO_Q_VM_00_0_DUAL                     0x0
+#define GPIO_Q_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_Q_VM_00_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_Q_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_Q_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Q_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM1_SHIFT)
+#define GPIO_Q_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_Q_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Q_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Q_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_Q_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Q_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM2_SHIFT)
+#define GPIO_Q_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_Q_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Q_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Q_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_Q_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Q_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM3_SHIFT)
+#define GPIO_Q_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_Q_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Q_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Q_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_Q_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Q_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM4_SHIFT)
+#define GPIO_Q_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_Q_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Q_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Q_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_Q_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Q_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM5_SHIFT)
+#define GPIO_Q_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_Q_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Q_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Q_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_Q_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Q_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM6_SHIFT)
+#define GPIO_Q_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_Q_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Q_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Q_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_Q_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Q_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM7_SHIFT)
+#define GPIO_Q_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_Q_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Q_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Q_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_Q_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Q_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_00_0_VM8_SHIFT)
+#define GPIO_Q_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_Q_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Q_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Q_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_Q_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_SCR_00_0
+#define GPIO_Q_SCR_00_0                 MK_ADDR_CONST(0x20c4)
+#define GPIO_Q_SCR_00_0_SECURE                  0x0
+#define GPIO_Q_SCR_00_0_DUAL                    0x0
+#define GPIO_Q_SCR_00_0_SCR                     0
+#define GPIO_Q_SCR_00_0_SCRREG                  0
+#define GPIO_Q_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_Q_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_Q_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Q_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Q_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_Q_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Q_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Q_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_Q_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_Q_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Q_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Q_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Q_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_Q_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Q_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Q_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Q_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Q_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Q_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR7_SHIFT)
+#define GPIO_Q_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_Q_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR6_SHIFT)
+#define GPIO_Q_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_Q_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR5_SHIFT)
+#define GPIO_Q_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_Q_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR4_SHIFT)
+#define GPIO_Q_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_Q_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR3_SHIFT)
+#define GPIO_Q_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_Q_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR2_SHIFT)
+#define GPIO_Q_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_Q_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR1_SHIFT)
+#define GPIO_Q_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_Q_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_PR0_SHIFT)
+#define GPIO_Q_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_Q_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G7W_SHIFT)
+#define GPIO_Q_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_Q_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G6W_SHIFT)
+#define GPIO_Q_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_Q_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G5W_SHIFT)
+#define GPIO_Q_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_Q_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G4W_SHIFT)
+#define GPIO_Q_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_Q_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G3W_SHIFT)
+#define GPIO_Q_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_Q_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G2W_SHIFT)
+#define GPIO_Q_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_Q_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G1W_SHIFT)
+#define GPIO_Q_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_Q_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G0W_SHIFT)
+#define GPIO_Q_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_Q_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G7R_SHIFT)
+#define GPIO_Q_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_Q_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G6R_SHIFT)
+#define GPIO_Q_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_Q_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G5R_SHIFT)
+#define GPIO_Q_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_Q_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G4R_SHIFT)
+#define GPIO_Q_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_Q_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G3R_SHIFT)
+#define GPIO_Q_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_Q_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G2R_SHIFT)
+#define GPIO_Q_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_Q_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G1R_SHIFT)
+#define GPIO_Q_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_Q_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_00_0_G0R_SHIFT)
+#define GPIO_Q_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_Q_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_Q_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_VM_01_0
+#define GPIO_Q_VM_01_0                  MK_ADDR_CONST(0x20c8)
+#define GPIO_Q_VM_01_0_SECURE                   0x0
+#define GPIO_Q_VM_01_0_DUAL                     0x0
+#define GPIO_Q_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_Q_VM_01_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_Q_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_Q_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Q_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM1_SHIFT)
+#define GPIO_Q_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_Q_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Q_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Q_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_Q_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Q_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM2_SHIFT)
+#define GPIO_Q_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_Q_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Q_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Q_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_Q_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Q_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM3_SHIFT)
+#define GPIO_Q_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_Q_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Q_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Q_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_Q_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Q_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM4_SHIFT)
+#define GPIO_Q_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_Q_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Q_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Q_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_Q_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Q_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM5_SHIFT)
+#define GPIO_Q_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_Q_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Q_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Q_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_Q_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Q_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM6_SHIFT)
+#define GPIO_Q_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_Q_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Q_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Q_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_Q_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Q_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM7_SHIFT)
+#define GPIO_Q_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_Q_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Q_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Q_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_Q_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Q_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_01_0_VM8_SHIFT)
+#define GPIO_Q_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_Q_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Q_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Q_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_Q_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_SCR_01_0
+#define GPIO_Q_SCR_01_0                 MK_ADDR_CONST(0x20cc)
+#define GPIO_Q_SCR_01_0_SECURE                  0x0
+#define GPIO_Q_SCR_01_0_DUAL                    0x0
+#define GPIO_Q_SCR_01_0_SCR                     0
+#define GPIO_Q_SCR_01_0_SCRREG                  0
+#define GPIO_Q_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_Q_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_Q_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Q_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Q_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_Q_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Q_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Q_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_Q_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_Q_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Q_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Q_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Q_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_Q_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Q_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Q_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Q_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Q_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Q_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR7_SHIFT)
+#define GPIO_Q_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_Q_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR6_SHIFT)
+#define GPIO_Q_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_Q_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR5_SHIFT)
+#define GPIO_Q_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_Q_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR4_SHIFT)
+#define GPIO_Q_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_Q_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR3_SHIFT)
+#define GPIO_Q_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_Q_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR2_SHIFT)
+#define GPIO_Q_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_Q_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR1_SHIFT)
+#define GPIO_Q_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_Q_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_PR0_SHIFT)
+#define GPIO_Q_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_Q_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G7W_SHIFT)
+#define GPIO_Q_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_Q_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G6W_SHIFT)
+#define GPIO_Q_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_Q_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G5W_SHIFT)
+#define GPIO_Q_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_Q_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G4W_SHIFT)
+#define GPIO_Q_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_Q_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G3W_SHIFT)
+#define GPIO_Q_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_Q_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G2W_SHIFT)
+#define GPIO_Q_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_Q_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G1W_SHIFT)
+#define GPIO_Q_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_Q_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G0W_SHIFT)
+#define GPIO_Q_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_Q_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G7R_SHIFT)
+#define GPIO_Q_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_Q_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G6R_SHIFT)
+#define GPIO_Q_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_Q_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G5R_SHIFT)
+#define GPIO_Q_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_Q_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G4R_SHIFT)
+#define GPIO_Q_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_Q_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G3R_SHIFT)
+#define GPIO_Q_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_Q_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G2R_SHIFT)
+#define GPIO_Q_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_Q_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G1R_SHIFT)
+#define GPIO_Q_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_Q_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_01_0_G0R_SHIFT)
+#define GPIO_Q_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_Q_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_Q_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_VM_02_0
+#define GPIO_Q_VM_02_0                  MK_ADDR_CONST(0x20d0)
+#define GPIO_Q_VM_02_0_SECURE                   0x0
+#define GPIO_Q_VM_02_0_DUAL                     0x0
+#define GPIO_Q_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_Q_VM_02_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_Q_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_Q_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Q_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM1_SHIFT)
+#define GPIO_Q_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_Q_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Q_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Q_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_Q_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Q_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM2_SHIFT)
+#define GPIO_Q_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_Q_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Q_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Q_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_Q_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Q_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM3_SHIFT)
+#define GPIO_Q_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_Q_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Q_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Q_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_Q_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Q_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM4_SHIFT)
+#define GPIO_Q_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_Q_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Q_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Q_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_Q_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Q_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM5_SHIFT)
+#define GPIO_Q_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_Q_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Q_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Q_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_Q_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Q_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM6_SHIFT)
+#define GPIO_Q_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_Q_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Q_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Q_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_Q_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Q_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM7_SHIFT)
+#define GPIO_Q_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_Q_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Q_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Q_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_Q_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Q_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_02_0_VM8_SHIFT)
+#define GPIO_Q_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_Q_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Q_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Q_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_Q_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_SCR_02_0
+#define GPIO_Q_SCR_02_0                 MK_ADDR_CONST(0x20d4)
+#define GPIO_Q_SCR_02_0_SECURE                  0x0
+#define GPIO_Q_SCR_02_0_DUAL                    0x0
+#define GPIO_Q_SCR_02_0_SCR                     0
+#define GPIO_Q_SCR_02_0_SCRREG                  0
+#define GPIO_Q_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_Q_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_Q_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Q_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Q_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_Q_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Q_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Q_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_Q_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_Q_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Q_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Q_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Q_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_Q_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Q_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Q_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Q_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Q_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Q_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR7_SHIFT)
+#define GPIO_Q_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_Q_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR6_SHIFT)
+#define GPIO_Q_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_Q_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR5_SHIFT)
+#define GPIO_Q_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_Q_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR4_SHIFT)
+#define GPIO_Q_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_Q_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR3_SHIFT)
+#define GPIO_Q_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_Q_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR2_SHIFT)
+#define GPIO_Q_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_Q_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR1_SHIFT)
+#define GPIO_Q_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_Q_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_PR0_SHIFT)
+#define GPIO_Q_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_Q_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G7W_SHIFT)
+#define GPIO_Q_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_Q_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G6W_SHIFT)
+#define GPIO_Q_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_Q_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G5W_SHIFT)
+#define GPIO_Q_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_Q_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G4W_SHIFT)
+#define GPIO_Q_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_Q_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G3W_SHIFT)
+#define GPIO_Q_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_Q_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G2W_SHIFT)
+#define GPIO_Q_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_Q_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G1W_SHIFT)
+#define GPIO_Q_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_Q_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G0W_SHIFT)
+#define GPIO_Q_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_Q_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G7R_SHIFT)
+#define GPIO_Q_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_Q_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G6R_SHIFT)
+#define GPIO_Q_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_Q_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G5R_SHIFT)
+#define GPIO_Q_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_Q_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G4R_SHIFT)
+#define GPIO_Q_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_Q_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G3R_SHIFT)
+#define GPIO_Q_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_Q_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G2R_SHIFT)
+#define GPIO_Q_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_Q_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G1R_SHIFT)
+#define GPIO_Q_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_Q_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_02_0_G0R_SHIFT)
+#define GPIO_Q_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_Q_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_Q_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_VM_03_0
+#define GPIO_Q_VM_03_0                  MK_ADDR_CONST(0x20d8)
+#define GPIO_Q_VM_03_0_SECURE                   0x0
+#define GPIO_Q_VM_03_0_DUAL                     0x0
+#define GPIO_Q_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_Q_VM_03_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_Q_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_Q_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Q_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM1_SHIFT)
+#define GPIO_Q_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_Q_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Q_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Q_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_Q_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Q_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM2_SHIFT)
+#define GPIO_Q_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_Q_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Q_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Q_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_Q_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Q_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM3_SHIFT)
+#define GPIO_Q_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_Q_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Q_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Q_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_Q_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Q_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM4_SHIFT)
+#define GPIO_Q_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_Q_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Q_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Q_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_Q_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Q_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM5_SHIFT)
+#define GPIO_Q_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_Q_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Q_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Q_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_Q_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Q_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM6_SHIFT)
+#define GPIO_Q_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_Q_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Q_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Q_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_Q_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Q_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM7_SHIFT)
+#define GPIO_Q_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_Q_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Q_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Q_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_Q_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Q_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_03_0_VM8_SHIFT)
+#define GPIO_Q_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_Q_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Q_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Q_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_Q_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_SCR_03_0
+#define GPIO_Q_SCR_03_0                 MK_ADDR_CONST(0x20dc)
+#define GPIO_Q_SCR_03_0_SECURE                  0x0
+#define GPIO_Q_SCR_03_0_DUAL                    0x0
+#define GPIO_Q_SCR_03_0_SCR                     0
+#define GPIO_Q_SCR_03_0_SCRREG                  0
+#define GPIO_Q_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_Q_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_Q_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Q_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Q_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_Q_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Q_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Q_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_Q_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_Q_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Q_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Q_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Q_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_Q_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Q_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Q_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Q_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Q_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Q_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR7_SHIFT)
+#define GPIO_Q_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_Q_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR6_SHIFT)
+#define GPIO_Q_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_Q_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR5_SHIFT)
+#define GPIO_Q_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_Q_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR4_SHIFT)
+#define GPIO_Q_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_Q_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR3_SHIFT)
+#define GPIO_Q_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_Q_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR2_SHIFT)
+#define GPIO_Q_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_Q_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR1_SHIFT)
+#define GPIO_Q_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_Q_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_PR0_SHIFT)
+#define GPIO_Q_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_Q_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G7W_SHIFT)
+#define GPIO_Q_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_Q_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G6W_SHIFT)
+#define GPIO_Q_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_Q_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G5W_SHIFT)
+#define GPIO_Q_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_Q_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G4W_SHIFT)
+#define GPIO_Q_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_Q_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G3W_SHIFT)
+#define GPIO_Q_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_Q_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G2W_SHIFT)
+#define GPIO_Q_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_Q_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G1W_SHIFT)
+#define GPIO_Q_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_Q_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G0W_SHIFT)
+#define GPIO_Q_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_Q_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G7R_SHIFT)
+#define GPIO_Q_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_Q_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G6R_SHIFT)
+#define GPIO_Q_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_Q_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G5R_SHIFT)
+#define GPIO_Q_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_Q_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G4R_SHIFT)
+#define GPIO_Q_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_Q_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G3R_SHIFT)
+#define GPIO_Q_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_Q_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G2R_SHIFT)
+#define GPIO_Q_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_Q_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G1R_SHIFT)
+#define GPIO_Q_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_Q_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_03_0_G0R_SHIFT)
+#define GPIO_Q_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_Q_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_Q_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_VM_04_0
+#define GPIO_Q_VM_04_0                  MK_ADDR_CONST(0x20e0)
+#define GPIO_Q_VM_04_0_SECURE                   0x0
+#define GPIO_Q_VM_04_0_DUAL                     0x0
+#define GPIO_Q_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_Q_VM_04_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_Q_VM_04_0_WORD_COUNT                       0x1
+#define GPIO_Q_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Q_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM1_SHIFT)
+#define GPIO_Q_VM_04_0_VM1_RANGE                        1:0
+#define GPIO_Q_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Q_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Q_VM_04_0_VM1_WOFFSET                      0x0
+#define GPIO_Q_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Q_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM2_SHIFT)
+#define GPIO_Q_VM_04_0_VM2_RANGE                        3:2
+#define GPIO_Q_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Q_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Q_VM_04_0_VM2_WOFFSET                      0x0
+#define GPIO_Q_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Q_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM3_SHIFT)
+#define GPIO_Q_VM_04_0_VM3_RANGE                        5:4
+#define GPIO_Q_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Q_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Q_VM_04_0_VM3_WOFFSET                      0x0
+#define GPIO_Q_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Q_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM4_SHIFT)
+#define GPIO_Q_VM_04_0_VM4_RANGE                        7:6
+#define GPIO_Q_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Q_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Q_VM_04_0_VM4_WOFFSET                      0x0
+#define GPIO_Q_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Q_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM5_SHIFT)
+#define GPIO_Q_VM_04_0_VM5_RANGE                        9:8
+#define GPIO_Q_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Q_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Q_VM_04_0_VM5_WOFFSET                      0x0
+#define GPIO_Q_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Q_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM6_SHIFT)
+#define GPIO_Q_VM_04_0_VM6_RANGE                        11:10
+#define GPIO_Q_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Q_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Q_VM_04_0_VM6_WOFFSET                      0x0
+#define GPIO_Q_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Q_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM7_SHIFT)
+#define GPIO_Q_VM_04_0_VM7_RANGE                        13:12
+#define GPIO_Q_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Q_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Q_VM_04_0_VM7_WOFFSET                      0x0
+#define GPIO_Q_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Q_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_04_0_VM8_SHIFT)
+#define GPIO_Q_VM_04_0_VM8_RANGE                        15:14
+#define GPIO_Q_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Q_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Q_VM_04_0_VM8_WOFFSET                      0x0
+#define GPIO_Q_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_SCR_04_0
+#define GPIO_Q_SCR_04_0                 MK_ADDR_CONST(0x20e4)
+#define GPIO_Q_SCR_04_0_SECURE                  0x0
+#define GPIO_Q_SCR_04_0_DUAL                    0x0
+#define GPIO_Q_SCR_04_0_SCR                     0
+#define GPIO_Q_SCR_04_0_SCRREG                  0
+#define GPIO_Q_SCR_04_0_WORD_COUNT                      0x1
+#define GPIO_Q_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_Q_SCR_04_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Q_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_04_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Q_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_Q_SCR_04_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Q_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_04_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Q_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_Q_SCR_04_0_SEC_REN_RANGE                   27:27
+#define GPIO_Q_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_04_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Q_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Q_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Q_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_Q_SCR_04_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Q_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Q_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Q_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Q_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Q_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR7_SHIFT)
+#define GPIO_Q_SCR_04_0_PR7_RANGE                       23:23
+#define GPIO_Q_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_04_0_PR7_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR6_SHIFT)
+#define GPIO_Q_SCR_04_0_PR6_RANGE                       22:22
+#define GPIO_Q_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_04_0_PR6_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR5_SHIFT)
+#define GPIO_Q_SCR_04_0_PR5_RANGE                       21:21
+#define GPIO_Q_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_04_0_PR5_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR4_SHIFT)
+#define GPIO_Q_SCR_04_0_PR4_RANGE                       20:20
+#define GPIO_Q_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_04_0_PR4_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR3_SHIFT)
+#define GPIO_Q_SCR_04_0_PR3_RANGE                       19:19
+#define GPIO_Q_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_04_0_PR3_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR2_SHIFT)
+#define GPIO_Q_SCR_04_0_PR2_RANGE                       18:18
+#define GPIO_Q_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_04_0_PR2_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR1_SHIFT)
+#define GPIO_Q_SCR_04_0_PR1_RANGE                       17:17
+#define GPIO_Q_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_04_0_PR1_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_PR0_SHIFT)
+#define GPIO_Q_SCR_04_0_PR0_RANGE                       16:16
+#define GPIO_Q_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_04_0_PR0_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G7W_SHIFT)
+#define GPIO_Q_SCR_04_0_G7W_RANGE                       15:15
+#define GPIO_Q_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_04_0_G7W_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G6W_SHIFT)
+#define GPIO_Q_SCR_04_0_G6W_RANGE                       14:14
+#define GPIO_Q_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_04_0_G6W_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G5W_SHIFT)
+#define GPIO_Q_SCR_04_0_G5W_RANGE                       13:13
+#define GPIO_Q_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_04_0_G5W_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G4W_SHIFT)
+#define GPIO_Q_SCR_04_0_G4W_RANGE                       12:12
+#define GPIO_Q_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_04_0_G4W_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G3W_SHIFT)
+#define GPIO_Q_SCR_04_0_G3W_RANGE                       11:11
+#define GPIO_Q_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_04_0_G3W_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G2W_SHIFT)
+#define GPIO_Q_SCR_04_0_G2W_RANGE                       10:10
+#define GPIO_Q_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_04_0_G2W_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G1W_SHIFT)
+#define GPIO_Q_SCR_04_0_G1W_RANGE                       9:9
+#define GPIO_Q_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_04_0_G1W_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G0W_SHIFT)
+#define GPIO_Q_SCR_04_0_G0W_RANGE                       8:8
+#define GPIO_Q_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_04_0_G0W_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G7R_SHIFT)
+#define GPIO_Q_SCR_04_0_G7R_RANGE                       7:7
+#define GPIO_Q_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_04_0_G7R_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G6R_SHIFT)
+#define GPIO_Q_SCR_04_0_G6R_RANGE                       6:6
+#define GPIO_Q_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_04_0_G6R_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G5R_SHIFT)
+#define GPIO_Q_SCR_04_0_G5R_RANGE                       5:5
+#define GPIO_Q_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_04_0_G5R_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G4R_SHIFT)
+#define GPIO_Q_SCR_04_0_G4R_RANGE                       4:4
+#define GPIO_Q_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_04_0_G4R_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G3R_SHIFT)
+#define GPIO_Q_SCR_04_0_G3R_RANGE                       3:3
+#define GPIO_Q_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_04_0_G3R_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G2R_SHIFT)
+#define GPIO_Q_SCR_04_0_G2R_RANGE                       2:2
+#define GPIO_Q_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_04_0_G2R_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G1R_SHIFT)
+#define GPIO_Q_SCR_04_0_G1R_RANGE                       1:1
+#define GPIO_Q_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_04_0_G1R_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_04_0_G0R_SHIFT)
+#define GPIO_Q_SCR_04_0_G0R_RANGE                       0:0
+#define GPIO_Q_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_04_0_G0R_WOFFSET                     0x0
+#define GPIO_Q_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_VM_05_0
+#define GPIO_Q_VM_05_0                  MK_ADDR_CONST(0x20e8)
+#define GPIO_Q_VM_05_0_SECURE                   0x0
+#define GPIO_Q_VM_05_0_DUAL                     0x0
+#define GPIO_Q_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_Q_VM_05_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_Q_VM_05_0_WORD_COUNT                       0x1
+#define GPIO_Q_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Q_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM1_SHIFT)
+#define GPIO_Q_VM_05_0_VM1_RANGE                        1:0
+#define GPIO_Q_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Q_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Q_VM_05_0_VM1_WOFFSET                      0x0
+#define GPIO_Q_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Q_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM2_SHIFT)
+#define GPIO_Q_VM_05_0_VM2_RANGE                        3:2
+#define GPIO_Q_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Q_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Q_VM_05_0_VM2_WOFFSET                      0x0
+#define GPIO_Q_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Q_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM3_SHIFT)
+#define GPIO_Q_VM_05_0_VM3_RANGE                        5:4
+#define GPIO_Q_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Q_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Q_VM_05_0_VM3_WOFFSET                      0x0
+#define GPIO_Q_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Q_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM4_SHIFT)
+#define GPIO_Q_VM_05_0_VM4_RANGE                        7:6
+#define GPIO_Q_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Q_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Q_VM_05_0_VM4_WOFFSET                      0x0
+#define GPIO_Q_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Q_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM5_SHIFT)
+#define GPIO_Q_VM_05_0_VM5_RANGE                        9:8
+#define GPIO_Q_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Q_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Q_VM_05_0_VM5_WOFFSET                      0x0
+#define GPIO_Q_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Q_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM6_SHIFT)
+#define GPIO_Q_VM_05_0_VM6_RANGE                        11:10
+#define GPIO_Q_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Q_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Q_VM_05_0_VM6_WOFFSET                      0x0
+#define GPIO_Q_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Q_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM7_SHIFT)
+#define GPIO_Q_VM_05_0_VM7_RANGE                        13:12
+#define GPIO_Q_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Q_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Q_VM_05_0_VM7_WOFFSET                      0x0
+#define GPIO_Q_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Q_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_05_0_VM8_SHIFT)
+#define GPIO_Q_VM_05_0_VM8_RANGE                        15:14
+#define GPIO_Q_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Q_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Q_VM_05_0_VM8_WOFFSET                      0x0
+#define GPIO_Q_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_SCR_05_0
+#define GPIO_Q_SCR_05_0                 MK_ADDR_CONST(0x20ec)
+#define GPIO_Q_SCR_05_0_SECURE                  0x0
+#define GPIO_Q_SCR_05_0_DUAL                    0x0
+#define GPIO_Q_SCR_05_0_SCR                     0
+#define GPIO_Q_SCR_05_0_SCRREG                  0
+#define GPIO_Q_SCR_05_0_WORD_COUNT                      0x1
+#define GPIO_Q_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_Q_SCR_05_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Q_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_05_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Q_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_Q_SCR_05_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Q_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_05_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Q_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_Q_SCR_05_0_SEC_REN_RANGE                   27:27
+#define GPIO_Q_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_05_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Q_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Q_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Q_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_Q_SCR_05_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Q_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Q_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Q_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Q_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Q_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR7_SHIFT)
+#define GPIO_Q_SCR_05_0_PR7_RANGE                       23:23
+#define GPIO_Q_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_05_0_PR7_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR6_SHIFT)
+#define GPIO_Q_SCR_05_0_PR6_RANGE                       22:22
+#define GPIO_Q_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_05_0_PR6_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR5_SHIFT)
+#define GPIO_Q_SCR_05_0_PR5_RANGE                       21:21
+#define GPIO_Q_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_05_0_PR5_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR4_SHIFT)
+#define GPIO_Q_SCR_05_0_PR4_RANGE                       20:20
+#define GPIO_Q_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_05_0_PR4_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR3_SHIFT)
+#define GPIO_Q_SCR_05_0_PR3_RANGE                       19:19
+#define GPIO_Q_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_05_0_PR3_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR2_SHIFT)
+#define GPIO_Q_SCR_05_0_PR2_RANGE                       18:18
+#define GPIO_Q_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_05_0_PR2_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR1_SHIFT)
+#define GPIO_Q_SCR_05_0_PR1_RANGE                       17:17
+#define GPIO_Q_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_05_0_PR1_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_PR0_SHIFT)
+#define GPIO_Q_SCR_05_0_PR0_RANGE                       16:16
+#define GPIO_Q_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_05_0_PR0_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G7W_SHIFT)
+#define GPIO_Q_SCR_05_0_G7W_RANGE                       15:15
+#define GPIO_Q_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_05_0_G7W_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G6W_SHIFT)
+#define GPIO_Q_SCR_05_0_G6W_RANGE                       14:14
+#define GPIO_Q_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_05_0_G6W_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G5W_SHIFT)
+#define GPIO_Q_SCR_05_0_G5W_RANGE                       13:13
+#define GPIO_Q_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_05_0_G5W_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G4W_SHIFT)
+#define GPIO_Q_SCR_05_0_G4W_RANGE                       12:12
+#define GPIO_Q_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_05_0_G4W_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G3W_SHIFT)
+#define GPIO_Q_SCR_05_0_G3W_RANGE                       11:11
+#define GPIO_Q_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_05_0_G3W_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G2W_SHIFT)
+#define GPIO_Q_SCR_05_0_G2W_RANGE                       10:10
+#define GPIO_Q_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_05_0_G2W_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G1W_SHIFT)
+#define GPIO_Q_SCR_05_0_G1W_RANGE                       9:9
+#define GPIO_Q_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_05_0_G1W_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G0W_SHIFT)
+#define GPIO_Q_SCR_05_0_G0W_RANGE                       8:8
+#define GPIO_Q_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_05_0_G0W_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G7R_SHIFT)
+#define GPIO_Q_SCR_05_0_G7R_RANGE                       7:7
+#define GPIO_Q_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_05_0_G7R_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G6R_SHIFT)
+#define GPIO_Q_SCR_05_0_G6R_RANGE                       6:6
+#define GPIO_Q_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_05_0_G6R_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G5R_SHIFT)
+#define GPIO_Q_SCR_05_0_G5R_RANGE                       5:5
+#define GPIO_Q_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_05_0_G5R_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G4R_SHIFT)
+#define GPIO_Q_SCR_05_0_G4R_RANGE                       4:4
+#define GPIO_Q_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_05_0_G4R_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G3R_SHIFT)
+#define GPIO_Q_SCR_05_0_G3R_RANGE                       3:3
+#define GPIO_Q_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_05_0_G3R_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G2R_SHIFT)
+#define GPIO_Q_SCR_05_0_G2R_RANGE                       2:2
+#define GPIO_Q_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_05_0_G2R_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G1R_SHIFT)
+#define GPIO_Q_SCR_05_0_G1R_RANGE                       1:1
+#define GPIO_Q_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_05_0_G1R_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_05_0_G0R_SHIFT)
+#define GPIO_Q_SCR_05_0_G0R_RANGE                       0:0
+#define GPIO_Q_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_05_0_G0R_WOFFSET                     0x0
+#define GPIO_Q_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_VM_06_0
+#define GPIO_Q_VM_06_0                  MK_ADDR_CONST(0x20f0)
+#define GPIO_Q_VM_06_0_SECURE                   0x0
+#define GPIO_Q_VM_06_0_DUAL                     0x0
+#define GPIO_Q_VM_06_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_Q_VM_06_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_Q_VM_06_0_WORD_COUNT                       0x1
+#define GPIO_Q_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Q_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM1_SHIFT)
+#define GPIO_Q_VM_06_0_VM1_RANGE                        1:0
+#define GPIO_Q_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Q_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Q_VM_06_0_VM1_WOFFSET                      0x0
+#define GPIO_Q_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Q_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM2_SHIFT)
+#define GPIO_Q_VM_06_0_VM2_RANGE                        3:2
+#define GPIO_Q_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Q_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Q_VM_06_0_VM2_WOFFSET                      0x0
+#define GPIO_Q_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Q_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM3_SHIFT)
+#define GPIO_Q_VM_06_0_VM3_RANGE                        5:4
+#define GPIO_Q_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Q_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Q_VM_06_0_VM3_WOFFSET                      0x0
+#define GPIO_Q_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Q_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM4_SHIFT)
+#define GPIO_Q_VM_06_0_VM4_RANGE                        7:6
+#define GPIO_Q_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Q_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Q_VM_06_0_VM4_WOFFSET                      0x0
+#define GPIO_Q_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Q_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM5_SHIFT)
+#define GPIO_Q_VM_06_0_VM5_RANGE                        9:8
+#define GPIO_Q_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Q_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Q_VM_06_0_VM5_WOFFSET                      0x0
+#define GPIO_Q_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Q_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM6_SHIFT)
+#define GPIO_Q_VM_06_0_VM6_RANGE                        11:10
+#define GPIO_Q_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Q_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Q_VM_06_0_VM6_WOFFSET                      0x0
+#define GPIO_Q_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Q_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM7_SHIFT)
+#define GPIO_Q_VM_06_0_VM7_RANGE                        13:12
+#define GPIO_Q_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Q_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Q_VM_06_0_VM7_WOFFSET                      0x0
+#define GPIO_Q_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Q_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_06_0_VM8_SHIFT)
+#define GPIO_Q_VM_06_0_VM8_RANGE                        15:14
+#define GPIO_Q_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Q_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Q_VM_06_0_VM8_WOFFSET                      0x0
+#define GPIO_Q_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_SCR_06_0
+#define GPIO_Q_SCR_06_0                 MK_ADDR_CONST(0x20f4)
+#define GPIO_Q_SCR_06_0_SECURE                  0x0
+#define GPIO_Q_SCR_06_0_DUAL                    0x0
+#define GPIO_Q_SCR_06_0_SCR                     0
+#define GPIO_Q_SCR_06_0_SCRREG                  0
+#define GPIO_Q_SCR_06_0_WORD_COUNT                      0x1
+#define GPIO_Q_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_SEC_LCK_SHIFT)
+#define GPIO_Q_SCR_06_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Q_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_06_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Q_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_SEC_WEN_SHIFT)
+#define GPIO_Q_SCR_06_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Q_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_06_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Q_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_SEC_REN_SHIFT)
+#define GPIO_Q_SCR_06_0_SEC_REN_RANGE                   27:27
+#define GPIO_Q_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_06_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Q_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Q_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Q_SCR_06_0_SEC_OWNER_SHIFT)
+#define GPIO_Q_SCR_06_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Q_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Q_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Q_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Q_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Q_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR7_SHIFT)
+#define GPIO_Q_SCR_06_0_PR7_RANGE                       23:23
+#define GPIO_Q_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_06_0_PR7_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR6_SHIFT)
+#define GPIO_Q_SCR_06_0_PR6_RANGE                       22:22
+#define GPIO_Q_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_06_0_PR6_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR5_SHIFT)
+#define GPIO_Q_SCR_06_0_PR5_RANGE                       21:21
+#define GPIO_Q_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_06_0_PR5_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR4_SHIFT)
+#define GPIO_Q_SCR_06_0_PR4_RANGE                       20:20
+#define GPIO_Q_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_06_0_PR4_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR3_SHIFT)
+#define GPIO_Q_SCR_06_0_PR3_RANGE                       19:19
+#define GPIO_Q_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_06_0_PR3_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR2_SHIFT)
+#define GPIO_Q_SCR_06_0_PR2_RANGE                       18:18
+#define GPIO_Q_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_06_0_PR2_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR1_SHIFT)
+#define GPIO_Q_SCR_06_0_PR1_RANGE                       17:17
+#define GPIO_Q_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_06_0_PR1_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_PR0_SHIFT)
+#define GPIO_Q_SCR_06_0_PR0_RANGE                       16:16
+#define GPIO_Q_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_06_0_PR0_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G7W_SHIFT)
+#define GPIO_Q_SCR_06_0_G7W_RANGE                       15:15
+#define GPIO_Q_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_06_0_G7W_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G6W_SHIFT)
+#define GPIO_Q_SCR_06_0_G6W_RANGE                       14:14
+#define GPIO_Q_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_06_0_G6W_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G5W_SHIFT)
+#define GPIO_Q_SCR_06_0_G5W_RANGE                       13:13
+#define GPIO_Q_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_06_0_G5W_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G4W_SHIFT)
+#define GPIO_Q_SCR_06_0_G4W_RANGE                       12:12
+#define GPIO_Q_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_06_0_G4W_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G3W_SHIFT)
+#define GPIO_Q_SCR_06_0_G3W_RANGE                       11:11
+#define GPIO_Q_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_06_0_G3W_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G2W_SHIFT)
+#define GPIO_Q_SCR_06_0_G2W_RANGE                       10:10
+#define GPIO_Q_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_06_0_G2W_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G1W_SHIFT)
+#define GPIO_Q_SCR_06_0_G1W_RANGE                       9:9
+#define GPIO_Q_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_06_0_G1W_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G0W_SHIFT)
+#define GPIO_Q_SCR_06_0_G0W_RANGE                       8:8
+#define GPIO_Q_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_06_0_G0W_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G7R_SHIFT)
+#define GPIO_Q_SCR_06_0_G7R_RANGE                       7:7
+#define GPIO_Q_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_06_0_G7R_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G6R_SHIFT)
+#define GPIO_Q_SCR_06_0_G6R_RANGE                       6:6
+#define GPIO_Q_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_06_0_G6R_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G5R_SHIFT)
+#define GPIO_Q_SCR_06_0_G5R_RANGE                       5:5
+#define GPIO_Q_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_06_0_G5R_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G4R_SHIFT)
+#define GPIO_Q_SCR_06_0_G4R_RANGE                       4:4
+#define GPIO_Q_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_06_0_G4R_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G3R_SHIFT)
+#define GPIO_Q_SCR_06_0_G3R_RANGE                       3:3
+#define GPIO_Q_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_06_0_G3R_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G2R_SHIFT)
+#define GPIO_Q_SCR_06_0_G2R_RANGE                       2:2
+#define GPIO_Q_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_06_0_G2R_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G1R_SHIFT)
+#define GPIO_Q_SCR_06_0_G1R_RANGE                       1:1
+#define GPIO_Q_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_06_0_G1R_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_06_0_G0R_SHIFT)
+#define GPIO_Q_SCR_06_0_G0R_RANGE                       0:0
+#define GPIO_Q_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_06_0_G0R_WOFFSET                     0x0
+#define GPIO_Q_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_VM_07_0
+#define GPIO_Q_VM_07_0                  MK_ADDR_CONST(0x20f8)
+#define GPIO_Q_VM_07_0_SECURE                   0x0
+#define GPIO_Q_VM_07_0_DUAL                     0x0
+#define GPIO_Q_VM_07_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_Q_VM_07_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_Q_VM_07_0_WORD_COUNT                       0x1
+#define GPIO_Q_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_Q_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Q_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM1_SHIFT)
+#define GPIO_Q_VM_07_0_VM1_RANGE                        1:0
+#define GPIO_Q_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_Q_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Q_VM_07_0_VM1_WOFFSET                      0x0
+#define GPIO_Q_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_Q_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM2_SHIFT)
+#define GPIO_Q_VM_07_0_VM2_RANGE                        3:2
+#define GPIO_Q_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_Q_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_Q_VM_07_0_VM2_WOFFSET                      0x0
+#define GPIO_Q_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_Q_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM3_SHIFT)
+#define GPIO_Q_VM_07_0_VM3_RANGE                        5:4
+#define GPIO_Q_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_Q_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_Q_VM_07_0_VM3_WOFFSET                      0x0
+#define GPIO_Q_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_Q_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM4_SHIFT)
+#define GPIO_Q_VM_07_0_VM4_RANGE                        7:6
+#define GPIO_Q_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Q_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_Q_VM_07_0_VM4_WOFFSET                      0x0
+#define GPIO_Q_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_Q_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM5_SHIFT)
+#define GPIO_Q_VM_07_0_VM5_RANGE                        9:8
+#define GPIO_Q_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_Q_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_Q_VM_07_0_VM5_WOFFSET                      0x0
+#define GPIO_Q_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_Q_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM6_SHIFT)
+#define GPIO_Q_VM_07_0_VM6_RANGE                        11:10
+#define GPIO_Q_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_Q_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_Q_VM_07_0_VM6_WOFFSET                      0x0
+#define GPIO_Q_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_Q_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM7_SHIFT)
+#define GPIO_Q_VM_07_0_VM7_RANGE                        13:12
+#define GPIO_Q_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_Q_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_Q_VM_07_0_VM7_WOFFSET                      0x0
+#define GPIO_Q_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_Q_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_Q_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_Q_VM_07_0_VM8_SHIFT)
+#define GPIO_Q_VM_07_0_VM8_RANGE                        15:14
+#define GPIO_Q_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_Q_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_Q_VM_07_0_VM8_WOFFSET                      0x0
+#define GPIO_Q_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_Q_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_SCR_07_0
+#define GPIO_Q_SCR_07_0                 MK_ADDR_CONST(0x20fc)
+#define GPIO_Q_SCR_07_0_SECURE                  0x0
+#define GPIO_Q_SCR_07_0_DUAL                    0x0
+#define GPIO_Q_SCR_07_0_SCR                     0
+#define GPIO_Q_SCR_07_0_SCRREG                  0
+#define GPIO_Q_SCR_07_0_WORD_COUNT                      0x1
+#define GPIO_Q_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_Q_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_SEC_LCK_SHIFT)
+#define GPIO_Q_SCR_07_0_SEC_LCK_RANGE                   29:29
+#define GPIO_Q_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_Q_SCR_07_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_Q_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_SEC_WEN_SHIFT)
+#define GPIO_Q_SCR_07_0_SEC_WEN_RANGE                   28:28
+#define GPIO_Q_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_Q_SCR_07_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_Q_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_SEC_REN_SHIFT)
+#define GPIO_Q_SCR_07_0_SEC_REN_RANGE                   27:27
+#define GPIO_Q_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_Q_SCR_07_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_Q_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_Q_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_Q_SCR_07_0_SEC_OWNER_SHIFT)
+#define GPIO_Q_SCR_07_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_Q_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_Q_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_Q_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_Q_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_Q_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR7_SHIFT)
+#define GPIO_Q_SCR_07_0_PR7_RANGE                       23:23
+#define GPIO_Q_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_Q_SCR_07_0_PR7_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR6_SHIFT)
+#define GPIO_Q_SCR_07_0_PR6_RANGE                       22:22
+#define GPIO_Q_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_Q_SCR_07_0_PR6_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR5_SHIFT)
+#define GPIO_Q_SCR_07_0_PR5_RANGE                       21:21
+#define GPIO_Q_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_Q_SCR_07_0_PR5_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR4_SHIFT)
+#define GPIO_Q_SCR_07_0_PR4_RANGE                       20:20
+#define GPIO_Q_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_Q_SCR_07_0_PR4_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR3_SHIFT)
+#define GPIO_Q_SCR_07_0_PR3_RANGE                       19:19
+#define GPIO_Q_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_Q_SCR_07_0_PR3_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR2_SHIFT)
+#define GPIO_Q_SCR_07_0_PR2_RANGE                       18:18
+#define GPIO_Q_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_Q_SCR_07_0_PR2_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR1_SHIFT)
+#define GPIO_Q_SCR_07_0_PR1_RANGE                       17:17
+#define GPIO_Q_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_Q_SCR_07_0_PR1_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_PR0_SHIFT)
+#define GPIO_Q_SCR_07_0_PR0_RANGE                       16:16
+#define GPIO_Q_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_Q_SCR_07_0_PR0_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G7W_SHIFT)
+#define GPIO_Q_SCR_07_0_G7W_RANGE                       15:15
+#define GPIO_Q_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_Q_SCR_07_0_G7W_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G6W_SHIFT)
+#define GPIO_Q_SCR_07_0_G6W_RANGE                       14:14
+#define GPIO_Q_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_Q_SCR_07_0_G6W_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G5W_SHIFT)
+#define GPIO_Q_SCR_07_0_G5W_RANGE                       13:13
+#define GPIO_Q_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_Q_SCR_07_0_G5W_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G4W_SHIFT)
+#define GPIO_Q_SCR_07_0_G4W_RANGE                       12:12
+#define GPIO_Q_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_Q_SCR_07_0_G4W_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G3W_SHIFT)
+#define GPIO_Q_SCR_07_0_G3W_RANGE                       11:11
+#define GPIO_Q_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_Q_SCR_07_0_G3W_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G2W_SHIFT)
+#define GPIO_Q_SCR_07_0_G2W_RANGE                       10:10
+#define GPIO_Q_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_Q_SCR_07_0_G2W_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G1W_SHIFT)
+#define GPIO_Q_SCR_07_0_G1W_RANGE                       9:9
+#define GPIO_Q_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_Q_SCR_07_0_G1W_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G0W_SHIFT)
+#define GPIO_Q_SCR_07_0_G0W_RANGE                       8:8
+#define GPIO_Q_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_Q_SCR_07_0_G0W_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G7R_SHIFT)
+#define GPIO_Q_SCR_07_0_G7R_RANGE                       7:7
+#define GPIO_Q_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_Q_SCR_07_0_G7R_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G6R_SHIFT)
+#define GPIO_Q_SCR_07_0_G6R_RANGE                       6:6
+#define GPIO_Q_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_Q_SCR_07_0_G6R_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G5R_SHIFT)
+#define GPIO_Q_SCR_07_0_G5R_RANGE                       5:5
+#define GPIO_Q_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_SCR_07_0_G5R_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G4R_SHIFT)
+#define GPIO_Q_SCR_07_0_G4R_RANGE                       4:4
+#define GPIO_Q_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_Q_SCR_07_0_G4R_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G3R_SHIFT)
+#define GPIO_Q_SCR_07_0_G3R_RANGE                       3:3
+#define GPIO_Q_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_Q_SCR_07_0_G3R_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G2R_SHIFT)
+#define GPIO_Q_SCR_07_0_G2R_RANGE                       2:2
+#define GPIO_Q_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_Q_SCR_07_0_G2R_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G1R_SHIFT)
+#define GPIO_Q_SCR_07_0_G1R_RANGE                       1:1
+#define GPIO_Q_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_Q_SCR_07_0_G1R_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_Q_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_SCR_07_0_G0R_SHIFT)
+#define GPIO_Q_SCR_07_0_G0R_RANGE                       0:0
+#define GPIO_Q_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_SCR_07_0_G0R_WOFFSET                     0x0
+#define GPIO_Q_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_Q_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_VM_00_0
+#define GPIO_R_VM_00_0                  MK_ADDR_CONST(0x2100)
+#define GPIO_R_VM_00_0_SECURE                   0x0
+#define GPIO_R_VM_00_0_DUAL                     0x0
+#define GPIO_R_VM_00_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_R_VM_00_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_R_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_R_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_R_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM1_SHIFT)
+#define GPIO_R_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_R_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_R_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_R_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_R_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_R_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM2_SHIFT)
+#define GPIO_R_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_R_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_R_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_R_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_R_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_R_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM3_SHIFT)
+#define GPIO_R_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_R_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_R_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_R_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_R_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_R_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM4_SHIFT)
+#define GPIO_R_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_R_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_R_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_R_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_R_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_R_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM5_SHIFT)
+#define GPIO_R_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_R_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_R_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_R_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_R_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_R_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM6_SHIFT)
+#define GPIO_R_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_R_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_R_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_R_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_R_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_R_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM7_SHIFT)
+#define GPIO_R_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_R_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_R_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_R_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_R_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_R_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_00_0_VM8_SHIFT)
+#define GPIO_R_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_R_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_R_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_R_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_R_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_SCR_00_0
+#define GPIO_R_SCR_00_0                 MK_ADDR_CONST(0x2104)
+#define GPIO_R_SCR_00_0_SECURE                  0x0
+#define GPIO_R_SCR_00_0_DUAL                    0x0
+#define GPIO_R_SCR_00_0_SCR                     0
+#define GPIO_R_SCR_00_0_SCRREG                  0
+#define GPIO_R_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_R_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_R_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_R_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_R_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_R_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_R_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_R_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_R_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_R_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_R_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_R_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_R_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_R_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_R_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_R_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_R_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_R_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_R_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR7_SHIFT)
+#define GPIO_R_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_R_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR6_SHIFT)
+#define GPIO_R_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_R_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR5_SHIFT)
+#define GPIO_R_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_R_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR4_SHIFT)
+#define GPIO_R_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_R_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR3_SHIFT)
+#define GPIO_R_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_R_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR2_SHIFT)
+#define GPIO_R_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_R_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR1_SHIFT)
+#define GPIO_R_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_R_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_PR0_SHIFT)
+#define GPIO_R_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_R_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G7W_SHIFT)
+#define GPIO_R_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_R_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G6W_SHIFT)
+#define GPIO_R_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_R_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G5W_SHIFT)
+#define GPIO_R_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_R_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G4W_SHIFT)
+#define GPIO_R_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_R_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G3W_SHIFT)
+#define GPIO_R_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_R_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G2W_SHIFT)
+#define GPIO_R_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_R_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G1W_SHIFT)
+#define GPIO_R_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_R_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G0W_SHIFT)
+#define GPIO_R_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_R_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G7R_SHIFT)
+#define GPIO_R_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_R_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G6R_SHIFT)
+#define GPIO_R_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_R_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G5R_SHIFT)
+#define GPIO_R_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_R_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G4R_SHIFT)
+#define GPIO_R_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_R_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G3R_SHIFT)
+#define GPIO_R_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_R_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G2R_SHIFT)
+#define GPIO_R_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_R_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G1R_SHIFT)
+#define GPIO_R_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_R_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_00_0_G0R_SHIFT)
+#define GPIO_R_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_R_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_R_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_VM_01_0
+#define GPIO_R_VM_01_0                  MK_ADDR_CONST(0x2108)
+#define GPIO_R_VM_01_0_SECURE                   0x0
+#define GPIO_R_VM_01_0_DUAL                     0x0
+#define GPIO_R_VM_01_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_R_VM_01_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_R_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_R_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_R_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM1_SHIFT)
+#define GPIO_R_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_R_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_R_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_R_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_R_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_R_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM2_SHIFT)
+#define GPIO_R_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_R_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_R_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_R_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_R_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_R_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM3_SHIFT)
+#define GPIO_R_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_R_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_R_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_R_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_R_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_R_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM4_SHIFT)
+#define GPIO_R_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_R_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_R_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_R_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_R_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_R_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM5_SHIFT)
+#define GPIO_R_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_R_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_R_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_R_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_R_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_R_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM6_SHIFT)
+#define GPIO_R_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_R_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_R_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_R_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_R_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_R_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM7_SHIFT)
+#define GPIO_R_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_R_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_R_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_R_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_R_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_R_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_01_0_VM8_SHIFT)
+#define GPIO_R_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_R_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_R_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_R_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_R_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_SCR_01_0
+#define GPIO_R_SCR_01_0                 MK_ADDR_CONST(0x210c)
+#define GPIO_R_SCR_01_0_SECURE                  0x0
+#define GPIO_R_SCR_01_0_DUAL                    0x0
+#define GPIO_R_SCR_01_0_SCR                     0
+#define GPIO_R_SCR_01_0_SCRREG                  0
+#define GPIO_R_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_R_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_R_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_R_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_R_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_R_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_R_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_R_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_R_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_R_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_R_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_R_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_R_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_R_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_R_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_R_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_R_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_R_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_R_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR7_SHIFT)
+#define GPIO_R_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_R_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR6_SHIFT)
+#define GPIO_R_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_R_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR5_SHIFT)
+#define GPIO_R_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_R_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR4_SHIFT)
+#define GPIO_R_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_R_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR3_SHIFT)
+#define GPIO_R_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_R_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR2_SHIFT)
+#define GPIO_R_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_R_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR1_SHIFT)
+#define GPIO_R_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_R_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_PR0_SHIFT)
+#define GPIO_R_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_R_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G7W_SHIFT)
+#define GPIO_R_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_R_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G6W_SHIFT)
+#define GPIO_R_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_R_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G5W_SHIFT)
+#define GPIO_R_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_R_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G4W_SHIFT)
+#define GPIO_R_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_R_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G3W_SHIFT)
+#define GPIO_R_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_R_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G2W_SHIFT)
+#define GPIO_R_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_R_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G1W_SHIFT)
+#define GPIO_R_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_R_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G0W_SHIFT)
+#define GPIO_R_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_R_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G7R_SHIFT)
+#define GPIO_R_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_R_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G6R_SHIFT)
+#define GPIO_R_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_R_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G5R_SHIFT)
+#define GPIO_R_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_R_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G4R_SHIFT)
+#define GPIO_R_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_R_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G3R_SHIFT)
+#define GPIO_R_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_R_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G2R_SHIFT)
+#define GPIO_R_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_R_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G1R_SHIFT)
+#define GPIO_R_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_R_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_01_0_G0R_SHIFT)
+#define GPIO_R_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_R_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_R_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_VM_02_0
+#define GPIO_R_VM_02_0                  MK_ADDR_CONST(0x2110)
+#define GPIO_R_VM_02_0_SECURE                   0x0
+#define GPIO_R_VM_02_0_DUAL                     0x0
+#define GPIO_R_VM_02_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_R_VM_02_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_R_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_R_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_R_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM1_SHIFT)
+#define GPIO_R_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_R_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_R_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_R_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_R_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_R_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM2_SHIFT)
+#define GPIO_R_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_R_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_R_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_R_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_R_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_R_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM3_SHIFT)
+#define GPIO_R_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_R_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_R_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_R_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_R_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_R_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM4_SHIFT)
+#define GPIO_R_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_R_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_R_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_R_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_R_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_R_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM5_SHIFT)
+#define GPIO_R_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_R_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_R_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_R_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_R_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_R_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM6_SHIFT)
+#define GPIO_R_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_R_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_R_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_R_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_R_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_R_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM7_SHIFT)
+#define GPIO_R_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_R_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_R_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_R_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_R_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_R_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_02_0_VM8_SHIFT)
+#define GPIO_R_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_R_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_R_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_R_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_R_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_SCR_02_0
+#define GPIO_R_SCR_02_0                 MK_ADDR_CONST(0x2114)
+#define GPIO_R_SCR_02_0_SECURE                  0x0
+#define GPIO_R_SCR_02_0_DUAL                    0x0
+#define GPIO_R_SCR_02_0_SCR                     0
+#define GPIO_R_SCR_02_0_SCRREG                  0
+#define GPIO_R_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_R_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_R_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_R_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_R_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_R_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_R_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_R_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_R_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_R_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_R_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_R_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_R_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_R_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_R_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_R_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_R_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_R_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_R_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR7_SHIFT)
+#define GPIO_R_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_R_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR6_SHIFT)
+#define GPIO_R_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_R_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR5_SHIFT)
+#define GPIO_R_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_R_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR4_SHIFT)
+#define GPIO_R_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_R_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR3_SHIFT)
+#define GPIO_R_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_R_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR2_SHIFT)
+#define GPIO_R_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_R_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR1_SHIFT)
+#define GPIO_R_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_R_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_PR0_SHIFT)
+#define GPIO_R_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_R_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G7W_SHIFT)
+#define GPIO_R_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_R_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G6W_SHIFT)
+#define GPIO_R_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_R_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G5W_SHIFT)
+#define GPIO_R_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_R_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G4W_SHIFT)
+#define GPIO_R_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_R_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G3W_SHIFT)
+#define GPIO_R_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_R_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G2W_SHIFT)
+#define GPIO_R_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_R_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G1W_SHIFT)
+#define GPIO_R_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_R_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G0W_SHIFT)
+#define GPIO_R_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_R_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G7R_SHIFT)
+#define GPIO_R_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_R_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G6R_SHIFT)
+#define GPIO_R_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_R_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G5R_SHIFT)
+#define GPIO_R_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_R_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G4R_SHIFT)
+#define GPIO_R_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_R_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G3R_SHIFT)
+#define GPIO_R_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_R_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G2R_SHIFT)
+#define GPIO_R_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_R_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G1R_SHIFT)
+#define GPIO_R_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_R_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_02_0_G0R_SHIFT)
+#define GPIO_R_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_R_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_R_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_VM_03_0
+#define GPIO_R_VM_03_0                  MK_ADDR_CONST(0x2118)
+#define GPIO_R_VM_03_0_SECURE                   0x0
+#define GPIO_R_VM_03_0_DUAL                     0x0
+#define GPIO_R_VM_03_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_R_VM_03_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_R_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_R_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_R_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM1_SHIFT)
+#define GPIO_R_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_R_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_R_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_R_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_R_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_R_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM2_SHIFT)
+#define GPIO_R_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_R_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_R_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_R_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_R_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_R_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM3_SHIFT)
+#define GPIO_R_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_R_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_R_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_R_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_R_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_R_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM4_SHIFT)
+#define GPIO_R_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_R_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_R_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_R_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_R_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_R_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM5_SHIFT)
+#define GPIO_R_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_R_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_R_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_R_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_R_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_R_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM6_SHIFT)
+#define GPIO_R_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_R_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_R_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_R_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_R_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_R_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM7_SHIFT)
+#define GPIO_R_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_R_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_R_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_R_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_R_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_R_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_03_0_VM8_SHIFT)
+#define GPIO_R_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_R_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_R_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_R_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_R_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_SCR_03_0
+#define GPIO_R_SCR_03_0                 MK_ADDR_CONST(0x211c)
+#define GPIO_R_SCR_03_0_SECURE                  0x0
+#define GPIO_R_SCR_03_0_DUAL                    0x0
+#define GPIO_R_SCR_03_0_SCR                     0
+#define GPIO_R_SCR_03_0_SCRREG                  0
+#define GPIO_R_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_R_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_R_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_R_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_R_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_R_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_R_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_R_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_R_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_R_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_R_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_R_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_R_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_R_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_R_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_R_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_R_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_R_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_R_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR7_SHIFT)
+#define GPIO_R_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_R_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR6_SHIFT)
+#define GPIO_R_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_R_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR5_SHIFT)
+#define GPIO_R_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_R_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR4_SHIFT)
+#define GPIO_R_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_R_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR3_SHIFT)
+#define GPIO_R_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_R_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR2_SHIFT)
+#define GPIO_R_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_R_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR1_SHIFT)
+#define GPIO_R_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_R_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_PR0_SHIFT)
+#define GPIO_R_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_R_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G7W_SHIFT)
+#define GPIO_R_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_R_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G6W_SHIFT)
+#define GPIO_R_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_R_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G5W_SHIFT)
+#define GPIO_R_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_R_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G4W_SHIFT)
+#define GPIO_R_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_R_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G3W_SHIFT)
+#define GPIO_R_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_R_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G2W_SHIFT)
+#define GPIO_R_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_R_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G1W_SHIFT)
+#define GPIO_R_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_R_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G0W_SHIFT)
+#define GPIO_R_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_R_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G7R_SHIFT)
+#define GPIO_R_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_R_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G6R_SHIFT)
+#define GPIO_R_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_R_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G5R_SHIFT)
+#define GPIO_R_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_R_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G4R_SHIFT)
+#define GPIO_R_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_R_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G3R_SHIFT)
+#define GPIO_R_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_R_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G2R_SHIFT)
+#define GPIO_R_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_R_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G1R_SHIFT)
+#define GPIO_R_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_R_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_03_0_G0R_SHIFT)
+#define GPIO_R_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_R_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_R_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_VM_04_0
+#define GPIO_R_VM_04_0                  MK_ADDR_CONST(0x2120)
+#define GPIO_R_VM_04_0_SECURE                   0x0
+#define GPIO_R_VM_04_0_DUAL                     0x0
+#define GPIO_R_VM_04_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_R_VM_04_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_R_VM_04_0_WORD_COUNT                       0x1
+#define GPIO_R_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_R_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM1_SHIFT)
+#define GPIO_R_VM_04_0_VM1_RANGE                        1:0
+#define GPIO_R_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_R_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_R_VM_04_0_VM1_WOFFSET                      0x0
+#define GPIO_R_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_R_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM2_SHIFT)
+#define GPIO_R_VM_04_0_VM2_RANGE                        3:2
+#define GPIO_R_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_R_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_R_VM_04_0_VM2_WOFFSET                      0x0
+#define GPIO_R_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_R_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM3_SHIFT)
+#define GPIO_R_VM_04_0_VM3_RANGE                        5:4
+#define GPIO_R_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_R_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_R_VM_04_0_VM3_WOFFSET                      0x0
+#define GPIO_R_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_R_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM4_SHIFT)
+#define GPIO_R_VM_04_0_VM4_RANGE                        7:6
+#define GPIO_R_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_R_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_R_VM_04_0_VM4_WOFFSET                      0x0
+#define GPIO_R_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_R_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM5_SHIFT)
+#define GPIO_R_VM_04_0_VM5_RANGE                        9:8
+#define GPIO_R_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_R_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_R_VM_04_0_VM5_WOFFSET                      0x0
+#define GPIO_R_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_R_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM6_SHIFT)
+#define GPIO_R_VM_04_0_VM6_RANGE                        11:10
+#define GPIO_R_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_R_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_R_VM_04_0_VM6_WOFFSET                      0x0
+#define GPIO_R_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_R_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM7_SHIFT)
+#define GPIO_R_VM_04_0_VM7_RANGE                        13:12
+#define GPIO_R_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_R_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_R_VM_04_0_VM7_WOFFSET                      0x0
+#define GPIO_R_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_R_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_04_0_VM8_SHIFT)
+#define GPIO_R_VM_04_0_VM8_RANGE                        15:14
+#define GPIO_R_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_R_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_R_VM_04_0_VM8_WOFFSET                      0x0
+#define GPIO_R_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_SCR_04_0
+#define GPIO_R_SCR_04_0                 MK_ADDR_CONST(0x2124)
+#define GPIO_R_SCR_04_0_SECURE                  0x0
+#define GPIO_R_SCR_04_0_DUAL                    0x0
+#define GPIO_R_SCR_04_0_SCR                     0
+#define GPIO_R_SCR_04_0_SCRREG                  0
+#define GPIO_R_SCR_04_0_WORD_COUNT                      0x1
+#define GPIO_R_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_R_SCR_04_0_SEC_LCK_RANGE                   29:29
+#define GPIO_R_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_04_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_R_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_R_SCR_04_0_SEC_WEN_RANGE                   28:28
+#define GPIO_R_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_04_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_R_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_R_SCR_04_0_SEC_REN_RANGE                   27:27
+#define GPIO_R_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_04_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_R_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_R_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_R_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_R_SCR_04_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_R_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_R_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_R_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_R_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_R_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR7_SHIFT)
+#define GPIO_R_SCR_04_0_PR7_RANGE                       23:23
+#define GPIO_R_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_04_0_PR7_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR6_SHIFT)
+#define GPIO_R_SCR_04_0_PR6_RANGE                       22:22
+#define GPIO_R_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_04_0_PR6_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR5_SHIFT)
+#define GPIO_R_SCR_04_0_PR5_RANGE                       21:21
+#define GPIO_R_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_04_0_PR5_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR4_SHIFT)
+#define GPIO_R_SCR_04_0_PR4_RANGE                       20:20
+#define GPIO_R_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_04_0_PR4_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR3_SHIFT)
+#define GPIO_R_SCR_04_0_PR3_RANGE                       19:19
+#define GPIO_R_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_04_0_PR3_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR2_SHIFT)
+#define GPIO_R_SCR_04_0_PR2_RANGE                       18:18
+#define GPIO_R_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_04_0_PR2_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR1_SHIFT)
+#define GPIO_R_SCR_04_0_PR1_RANGE                       17:17
+#define GPIO_R_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_04_0_PR1_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_PR0_SHIFT)
+#define GPIO_R_SCR_04_0_PR0_RANGE                       16:16
+#define GPIO_R_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_04_0_PR0_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G7W_SHIFT)
+#define GPIO_R_SCR_04_0_G7W_RANGE                       15:15
+#define GPIO_R_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_04_0_G7W_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G6W_SHIFT)
+#define GPIO_R_SCR_04_0_G6W_RANGE                       14:14
+#define GPIO_R_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_04_0_G6W_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G5W_SHIFT)
+#define GPIO_R_SCR_04_0_G5W_RANGE                       13:13
+#define GPIO_R_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_04_0_G5W_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G4W_SHIFT)
+#define GPIO_R_SCR_04_0_G4W_RANGE                       12:12
+#define GPIO_R_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_04_0_G4W_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G3W_SHIFT)
+#define GPIO_R_SCR_04_0_G3W_RANGE                       11:11
+#define GPIO_R_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_04_0_G3W_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G2W_SHIFT)
+#define GPIO_R_SCR_04_0_G2W_RANGE                       10:10
+#define GPIO_R_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_04_0_G2W_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G1W_SHIFT)
+#define GPIO_R_SCR_04_0_G1W_RANGE                       9:9
+#define GPIO_R_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_04_0_G1W_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G0W_SHIFT)
+#define GPIO_R_SCR_04_0_G0W_RANGE                       8:8
+#define GPIO_R_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_04_0_G0W_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G7R_SHIFT)
+#define GPIO_R_SCR_04_0_G7R_RANGE                       7:7
+#define GPIO_R_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_04_0_G7R_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G6R_SHIFT)
+#define GPIO_R_SCR_04_0_G6R_RANGE                       6:6
+#define GPIO_R_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_04_0_G6R_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G5R_SHIFT)
+#define GPIO_R_SCR_04_0_G5R_RANGE                       5:5
+#define GPIO_R_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_04_0_G5R_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G4R_SHIFT)
+#define GPIO_R_SCR_04_0_G4R_RANGE                       4:4
+#define GPIO_R_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_04_0_G4R_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G3R_SHIFT)
+#define GPIO_R_SCR_04_0_G3R_RANGE                       3:3
+#define GPIO_R_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_04_0_G3R_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G2R_SHIFT)
+#define GPIO_R_SCR_04_0_G2R_RANGE                       2:2
+#define GPIO_R_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_04_0_G2R_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G1R_SHIFT)
+#define GPIO_R_SCR_04_0_G1R_RANGE                       1:1
+#define GPIO_R_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_04_0_G1R_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_04_0_G0R_SHIFT)
+#define GPIO_R_SCR_04_0_G0R_RANGE                       0:0
+#define GPIO_R_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_04_0_G0R_WOFFSET                     0x0
+#define GPIO_R_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_VM_05_0
+#define GPIO_R_VM_05_0                  MK_ADDR_CONST(0x2128)
+#define GPIO_R_VM_05_0_SECURE                   0x0
+#define GPIO_R_VM_05_0_DUAL                     0x0
+#define GPIO_R_VM_05_0_SCR                      GPIO_CTL2_VM_SCR_0
+#define GPIO_R_VM_05_0_SCRREG                   GPIO_CTL2_VM_SCR_0
+#define GPIO_R_VM_05_0_WORD_COUNT                       0x1
+#define GPIO_R_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_R_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_R_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM1_SHIFT)
+#define GPIO_R_VM_05_0_VM1_RANGE                        1:0
+#define GPIO_R_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_R_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_R_VM_05_0_VM1_WOFFSET                      0x0
+#define GPIO_R_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_R_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM2_SHIFT)
+#define GPIO_R_VM_05_0_VM2_RANGE                        3:2
+#define GPIO_R_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_R_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_R_VM_05_0_VM2_WOFFSET                      0x0
+#define GPIO_R_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_R_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM3_SHIFT)
+#define GPIO_R_VM_05_0_VM3_RANGE                        5:4
+#define GPIO_R_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_R_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_R_VM_05_0_VM3_WOFFSET                      0x0
+#define GPIO_R_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_R_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM4_SHIFT)
+#define GPIO_R_VM_05_0_VM4_RANGE                        7:6
+#define GPIO_R_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_R_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_R_VM_05_0_VM4_WOFFSET                      0x0
+#define GPIO_R_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_R_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM5_SHIFT)
+#define GPIO_R_VM_05_0_VM5_RANGE                        9:8
+#define GPIO_R_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_R_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_R_VM_05_0_VM5_WOFFSET                      0x0
+#define GPIO_R_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_R_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM6_SHIFT)
+#define GPIO_R_VM_05_0_VM6_RANGE                        11:10
+#define GPIO_R_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_R_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_R_VM_05_0_VM6_WOFFSET                      0x0
+#define GPIO_R_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_R_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM7_SHIFT)
+#define GPIO_R_VM_05_0_VM7_RANGE                        13:12
+#define GPIO_R_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_R_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_R_VM_05_0_VM7_WOFFSET                      0x0
+#define GPIO_R_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_R_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_R_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_R_VM_05_0_VM8_SHIFT)
+#define GPIO_R_VM_05_0_VM8_RANGE                        15:14
+#define GPIO_R_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_R_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_R_VM_05_0_VM8_WOFFSET                      0x0
+#define GPIO_R_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_R_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_R_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_SCR_05_0
+#define GPIO_R_SCR_05_0                 MK_ADDR_CONST(0x212c)
+#define GPIO_R_SCR_05_0_SECURE                  0x0
+#define GPIO_R_SCR_05_0_DUAL                    0x0
+#define GPIO_R_SCR_05_0_SCR                     0
+#define GPIO_R_SCR_05_0_SCRREG                  0
+#define GPIO_R_SCR_05_0_WORD_COUNT                      0x1
+#define GPIO_R_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_R_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_R_SCR_05_0_SEC_LCK_RANGE                   29:29
+#define GPIO_R_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_R_SCR_05_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_R_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_R_SCR_05_0_SEC_WEN_RANGE                   28:28
+#define GPIO_R_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_R_SCR_05_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_R_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_R_SCR_05_0_SEC_REN_RANGE                   27:27
+#define GPIO_R_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_R_SCR_05_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_R_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_R_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_R_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_R_SCR_05_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_R_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_R_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_R_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_R_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_R_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR7_SHIFT)
+#define GPIO_R_SCR_05_0_PR7_RANGE                       23:23
+#define GPIO_R_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_R_SCR_05_0_PR7_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR6_SHIFT)
+#define GPIO_R_SCR_05_0_PR6_RANGE                       22:22
+#define GPIO_R_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_R_SCR_05_0_PR6_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR5_SHIFT)
+#define GPIO_R_SCR_05_0_PR5_RANGE                       21:21
+#define GPIO_R_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_R_SCR_05_0_PR5_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR4_SHIFT)
+#define GPIO_R_SCR_05_0_PR4_RANGE                       20:20
+#define GPIO_R_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_R_SCR_05_0_PR4_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR3_SHIFT)
+#define GPIO_R_SCR_05_0_PR3_RANGE                       19:19
+#define GPIO_R_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_R_SCR_05_0_PR3_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR2_SHIFT)
+#define GPIO_R_SCR_05_0_PR2_RANGE                       18:18
+#define GPIO_R_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_R_SCR_05_0_PR2_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR1_SHIFT)
+#define GPIO_R_SCR_05_0_PR1_RANGE                       17:17
+#define GPIO_R_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_R_SCR_05_0_PR1_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_PR0_SHIFT)
+#define GPIO_R_SCR_05_0_PR0_RANGE                       16:16
+#define GPIO_R_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_R_SCR_05_0_PR0_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G7W_SHIFT)
+#define GPIO_R_SCR_05_0_G7W_RANGE                       15:15
+#define GPIO_R_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_R_SCR_05_0_G7W_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G6W_SHIFT)
+#define GPIO_R_SCR_05_0_G6W_RANGE                       14:14
+#define GPIO_R_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_R_SCR_05_0_G6W_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G5W_SHIFT)
+#define GPIO_R_SCR_05_0_G5W_RANGE                       13:13
+#define GPIO_R_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_R_SCR_05_0_G5W_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G4W_SHIFT)
+#define GPIO_R_SCR_05_0_G4W_RANGE                       12:12
+#define GPIO_R_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_R_SCR_05_0_G4W_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G3W_SHIFT)
+#define GPIO_R_SCR_05_0_G3W_RANGE                       11:11
+#define GPIO_R_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_R_SCR_05_0_G3W_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G2W_SHIFT)
+#define GPIO_R_SCR_05_0_G2W_RANGE                       10:10
+#define GPIO_R_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_R_SCR_05_0_G2W_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G1W_SHIFT)
+#define GPIO_R_SCR_05_0_G1W_RANGE                       9:9
+#define GPIO_R_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_R_SCR_05_0_G1W_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G0W_SHIFT)
+#define GPIO_R_SCR_05_0_G0W_RANGE                       8:8
+#define GPIO_R_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_R_SCR_05_0_G0W_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G7R_SHIFT)
+#define GPIO_R_SCR_05_0_G7R_RANGE                       7:7
+#define GPIO_R_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_R_SCR_05_0_G7R_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G6R_SHIFT)
+#define GPIO_R_SCR_05_0_G6R_RANGE                       6:6
+#define GPIO_R_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_R_SCR_05_0_G6R_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G5R_SHIFT)
+#define GPIO_R_SCR_05_0_G5R_RANGE                       5:5
+#define GPIO_R_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_SCR_05_0_G5R_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G4R_SHIFT)
+#define GPIO_R_SCR_05_0_G4R_RANGE                       4:4
+#define GPIO_R_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_R_SCR_05_0_G4R_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G3R_SHIFT)
+#define GPIO_R_SCR_05_0_G3R_RANGE                       3:3
+#define GPIO_R_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_R_SCR_05_0_G3R_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G2R_SHIFT)
+#define GPIO_R_SCR_05_0_G2R_RANGE                       2:2
+#define GPIO_R_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_R_SCR_05_0_G2R_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G1R_SHIFT)
+#define GPIO_R_SCR_05_0_G1R_RANGE                       1:1
+#define GPIO_R_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_R_SCR_05_0_G1R_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_R_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_SCR_05_0_G0R_SHIFT)
+#define GPIO_R_SCR_05_0_G0R_RANGE                       0:0
+#define GPIO_R_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_SCR_05_0_G0R_WOFFSET                     0x0
+#define GPIO_R_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_R_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x2130
+
+// Reserved address 0x2134
+
+// Reserved address 0x2138
+
+// Reserved address 0x213c
+
+// Register GPIO_CTL2_VM_SCR_0
+#define GPIO_CTL2_VM_SCR_0                      MK_ADDR_CONST(0x2800)
+#define GPIO_CTL2_VM_SCR_0_SECURE                       0x0
+#define GPIO_CTL2_VM_SCR_0_DUAL                         0x0
+#define GPIO_CTL2_VM_SCR_0_SCR                  0
+#define GPIO_CTL2_VM_SCR_0_SCRREG                       0
+#define GPIO_CTL2_VM_SCR_0_WORD_COUNT                   0x1
+#define GPIO_CTL2_VM_SCR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL2_VM_SCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL2_VM_SCR_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL2_VM_SCR_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
+#define GPIO_CTL2_VM_SCR_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_SEC_LCK_RANGE                        29:29
+#define GPIO_CTL2_VM_SCR_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
+#define GPIO_CTL2_VM_SCR_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
+#define GPIO_CTL2_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
+#define GPIO_CTL2_VM_SCR_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
+#define GPIO_CTL2_VM_SCR_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_SEC_WEN_RANGE                        28:28
+#define GPIO_CTL2_VM_SCR_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
+#define GPIO_CTL2_VM_SCR_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
+#define GPIO_CTL2_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
+#define GPIO_CTL2_VM_SCR_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
+#define GPIO_CTL2_VM_SCR_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_SEC_REN_RANGE                        27:27
+#define GPIO_CTL2_VM_SCR_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
+#define GPIO_CTL2_VM_SCR_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
+#define GPIO_CTL2_VM_SCR_0_SEC_REN_WOFFSET                      0x0
+#define GPIO_CTL2_VM_SCR_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
+#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, GPIO_CTL2_VM_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_RANGE                      26:24
+#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
+#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
+#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
+#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
+#define GPIO_CTL2_VM_SCR_0_PR7_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR7_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_PR7_RANGE                    23:23
+#define GPIO_CTL2_VM_SCR_0_PR7_MSB                      MK_SHIFT_CONST(23)
+#define GPIO_CTL2_VM_SCR_0_PR7_LSB                      MK_SHIFT_CONST(23)
+#define GPIO_CTL2_VM_SCR_0_PR7_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
+#define GPIO_CTL2_VM_SCR_0_PR6_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR6_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_PR6_RANGE                    22:22
+#define GPIO_CTL2_VM_SCR_0_PR6_MSB                      MK_SHIFT_CONST(22)
+#define GPIO_CTL2_VM_SCR_0_PR6_LSB                      MK_SHIFT_CONST(22)
+#define GPIO_CTL2_VM_SCR_0_PR6_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
+#define GPIO_CTL2_VM_SCR_0_PR5_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR5_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_PR5_RANGE                    21:21
+#define GPIO_CTL2_VM_SCR_0_PR5_MSB                      MK_SHIFT_CONST(21)
+#define GPIO_CTL2_VM_SCR_0_PR5_LSB                      MK_SHIFT_CONST(21)
+#define GPIO_CTL2_VM_SCR_0_PR5_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
+#define GPIO_CTL2_VM_SCR_0_PR4_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR4_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_PR4_RANGE                    20:20
+#define GPIO_CTL2_VM_SCR_0_PR4_MSB                      MK_SHIFT_CONST(20)
+#define GPIO_CTL2_VM_SCR_0_PR4_LSB                      MK_SHIFT_CONST(20)
+#define GPIO_CTL2_VM_SCR_0_PR4_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
+#define GPIO_CTL2_VM_SCR_0_PR3_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR3_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_PR3_RANGE                    19:19
+#define GPIO_CTL2_VM_SCR_0_PR3_MSB                      MK_SHIFT_CONST(19)
+#define GPIO_CTL2_VM_SCR_0_PR3_LSB                      MK_SHIFT_CONST(19)
+#define GPIO_CTL2_VM_SCR_0_PR3_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
+#define GPIO_CTL2_VM_SCR_0_PR2_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR2_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_PR2_RANGE                    18:18
+#define GPIO_CTL2_VM_SCR_0_PR2_MSB                      MK_SHIFT_CONST(18)
+#define GPIO_CTL2_VM_SCR_0_PR2_LSB                      MK_SHIFT_CONST(18)
+#define GPIO_CTL2_VM_SCR_0_PR2_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
+#define GPIO_CTL2_VM_SCR_0_PR1_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR1_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_PR1_RANGE                    17:17
+#define GPIO_CTL2_VM_SCR_0_PR1_MSB                      MK_SHIFT_CONST(17)
+#define GPIO_CTL2_VM_SCR_0_PR1_LSB                      MK_SHIFT_CONST(17)
+#define GPIO_CTL2_VM_SCR_0_PR1_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
+#define GPIO_CTL2_VM_SCR_0_PR0_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_PR0_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_PR0_RANGE                    16:16
+#define GPIO_CTL2_VM_SCR_0_PR0_MSB                      MK_SHIFT_CONST(16)
+#define GPIO_CTL2_VM_SCR_0_PR0_LSB                      MK_SHIFT_CONST(16)
+#define GPIO_CTL2_VM_SCR_0_PR0_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
+#define GPIO_CTL2_VM_SCR_0_G7W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G7W_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_G7W_RANGE                    15:15
+#define GPIO_CTL2_VM_SCR_0_G7W_MSB                      MK_SHIFT_CONST(15)
+#define GPIO_CTL2_VM_SCR_0_G7W_LSB                      MK_SHIFT_CONST(15)
+#define GPIO_CTL2_VM_SCR_0_G7W_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
+#define GPIO_CTL2_VM_SCR_0_G6W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G6W_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_G6W_RANGE                    14:14
+#define GPIO_CTL2_VM_SCR_0_G6W_MSB                      MK_SHIFT_CONST(14)
+#define GPIO_CTL2_VM_SCR_0_G6W_LSB                      MK_SHIFT_CONST(14)
+#define GPIO_CTL2_VM_SCR_0_G6W_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
+#define GPIO_CTL2_VM_SCR_0_G5W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G5W_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_G5W_RANGE                    13:13
+#define GPIO_CTL2_VM_SCR_0_G5W_MSB                      MK_SHIFT_CONST(13)
+#define GPIO_CTL2_VM_SCR_0_G5W_LSB                      MK_SHIFT_CONST(13)
+#define GPIO_CTL2_VM_SCR_0_G5W_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
+#define GPIO_CTL2_VM_SCR_0_G4W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G4W_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_G4W_RANGE                    12:12
+#define GPIO_CTL2_VM_SCR_0_G4W_MSB                      MK_SHIFT_CONST(12)
+#define GPIO_CTL2_VM_SCR_0_G4W_LSB                      MK_SHIFT_CONST(12)
+#define GPIO_CTL2_VM_SCR_0_G4W_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
+#define GPIO_CTL2_VM_SCR_0_G3W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G3W_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_G3W_RANGE                    11:11
+#define GPIO_CTL2_VM_SCR_0_G3W_MSB                      MK_SHIFT_CONST(11)
+#define GPIO_CTL2_VM_SCR_0_G3W_LSB                      MK_SHIFT_CONST(11)
+#define GPIO_CTL2_VM_SCR_0_G3W_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
+#define GPIO_CTL2_VM_SCR_0_G2W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G2W_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_G2W_RANGE                    10:10
+#define GPIO_CTL2_VM_SCR_0_G2W_MSB                      MK_SHIFT_CONST(10)
+#define GPIO_CTL2_VM_SCR_0_G2W_LSB                      MK_SHIFT_CONST(10)
+#define GPIO_CTL2_VM_SCR_0_G2W_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
+#define GPIO_CTL2_VM_SCR_0_G1W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G1W_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_G1W_RANGE                    9:9
+#define GPIO_CTL2_VM_SCR_0_G1W_MSB                      MK_SHIFT_CONST(9)
+#define GPIO_CTL2_VM_SCR_0_G1W_LSB                      MK_SHIFT_CONST(9)
+#define GPIO_CTL2_VM_SCR_0_G1W_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
+#define GPIO_CTL2_VM_SCR_0_G0W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G0W_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_G0W_RANGE                    8:8
+#define GPIO_CTL2_VM_SCR_0_G0W_MSB                      MK_SHIFT_CONST(8)
+#define GPIO_CTL2_VM_SCR_0_G0W_LSB                      MK_SHIFT_CONST(8)
+#define GPIO_CTL2_VM_SCR_0_G0W_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
+#define GPIO_CTL2_VM_SCR_0_G7R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G7R_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_G7R_RANGE                    7:7
+#define GPIO_CTL2_VM_SCR_0_G7R_MSB                      MK_SHIFT_CONST(7)
+#define GPIO_CTL2_VM_SCR_0_G7R_LSB                      MK_SHIFT_CONST(7)
+#define GPIO_CTL2_VM_SCR_0_G7R_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
+#define GPIO_CTL2_VM_SCR_0_G6R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G6R_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_G6R_RANGE                    6:6
+#define GPIO_CTL2_VM_SCR_0_G6R_MSB                      MK_SHIFT_CONST(6)
+#define GPIO_CTL2_VM_SCR_0_G6R_LSB                      MK_SHIFT_CONST(6)
+#define GPIO_CTL2_VM_SCR_0_G6R_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
+#define GPIO_CTL2_VM_SCR_0_G5R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G5R_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_G5R_RANGE                    5:5
+#define GPIO_CTL2_VM_SCR_0_G5R_MSB                      MK_SHIFT_CONST(5)
+#define GPIO_CTL2_VM_SCR_0_G5R_LSB                      MK_SHIFT_CONST(5)
+#define GPIO_CTL2_VM_SCR_0_G5R_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
+#define GPIO_CTL2_VM_SCR_0_G4R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G4R_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_G4R_RANGE                    4:4
+#define GPIO_CTL2_VM_SCR_0_G4R_MSB                      MK_SHIFT_CONST(4)
+#define GPIO_CTL2_VM_SCR_0_G4R_LSB                      MK_SHIFT_CONST(4)
+#define GPIO_CTL2_VM_SCR_0_G4R_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
+#define GPIO_CTL2_VM_SCR_0_G3R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G3R_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_G3R_RANGE                    3:3
+#define GPIO_CTL2_VM_SCR_0_G3R_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_CTL2_VM_SCR_0_G3R_LSB                      MK_SHIFT_CONST(3)
+#define GPIO_CTL2_VM_SCR_0_G3R_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_CTL2_VM_SCR_0_G2R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G2R_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_G2R_RANGE                    2:2
+#define GPIO_CTL2_VM_SCR_0_G2R_MSB                      MK_SHIFT_CONST(2)
+#define GPIO_CTL2_VM_SCR_0_G2R_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_CTL2_VM_SCR_0_G2R_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
+#define GPIO_CTL2_VM_SCR_0_G1R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G1R_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_G1R_RANGE                    1:1
+#define GPIO_CTL2_VM_SCR_0_G1R_MSB                      MK_SHIFT_CONST(1)
+#define GPIO_CTL2_VM_SCR_0_G1R_LSB                      MK_SHIFT_CONST(1)
+#define GPIO_CTL2_VM_SCR_0_G1R_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_VM_SCR_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CTL2_VM_SCR_0_G0R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL2_VM_SCR_0_G0R_SHIFT)
+#define GPIO_CTL2_VM_SCR_0_G0R_RANGE                    0:0
+#define GPIO_CTL2_VM_SCR_0_G0R_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CTL2_VM_SCR_0_G0R_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CTL2_VM_SCR_0_G0R_WOFFSET                  0x0
+#define GPIO_CTL2_VM_SCR_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL2_VM_SCR_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0                     MK_ADDR_CONST(0x2804)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SCRREG                      0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_MSB                     MK_SHIFT_CONST(23)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_LSB                     MK_SHIFT_CONST(23)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_MSB                     MK_SHIFT_CONST(22)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_LSB                     MK_SHIFT_CONST(22)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_MSB                     MK_SHIFT_CONST(21)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_LSB                     MK_SHIFT_CONST(21)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_MSB                     MK_SHIFT_CONST(20)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_LSB                     MK_SHIFT_CONST(20)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_MSB                     MK_SHIFT_CONST(19)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_LSB                     MK_SHIFT_CONST(19)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_MSB                     MK_SHIFT_CONST(18)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_LSB                     MK_SHIFT_CONST(18)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_MSB                     MK_SHIFT_CONST(17)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_LSB                     MK_SHIFT_CONST(17)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_MSB                     MK_SHIFT_CONST(16)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_LSB                     MK_SHIFT_CONST(16)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_MSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_LSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_MSB                     MK_SHIFT_CONST(14)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_LSB                     MK_SHIFT_CONST(14)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_MSB                     MK_SHIFT_CONST(13)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_LSB                     MK_SHIFT_CONST(13)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_MSB                     MK_SHIFT_CONST(12)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_LSB                     MK_SHIFT_CONST(12)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_MSB                     MK_SHIFT_CONST(11)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_LSB                     MK_SHIFT_CONST(11)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_MSB                     MK_SHIFT_CONST(10)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_LSB                     MK_SHIFT_CONST(10)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_MSB                     MK_SHIFT_CONST(9)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_LSB                     MK_SHIFT_CONST(9)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_MSB                     MK_SHIFT_CONST(8)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_LSB                     MK_SHIFT_CONST(8)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_MSB                     MK_SHIFT_CONST(6)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_LSB                     MK_SHIFT_CONST(6)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_LSB                     MK_SHIFT_CONST(5)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_LSB                     MK_SHIFT_CONST(3)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_MSB                     MK_SHIFT_CONST(2)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_MSB                     MK_SHIFT_CONST(1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_LSB                     MK_SHIFT_CONST(1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_MSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL2_INTERRUPT_STATUS_VM_0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0                 MK_ADDR_CONST(0x2808)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SECURE                  0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_DUAL                    0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SCRREG                  GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  MK_FIELD_CONST(0xff, GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL2_SCR_0
+#define GPIO_CTL2_SCR_0                 MK_ADDR_CONST(0x280c)
+#define GPIO_CTL2_SCR_0_SECURE                  0x0
+#define GPIO_CTL2_SCR_0_DUAL                    0x0
+#define GPIO_CTL2_SCR_0_SCR                     0
+#define GPIO_CTL2_SCR_0_SCRREG                  0
+#define GPIO_CTL2_SCR_0_WORD_COUNT                      0x1
+#define GPIO_CTL2_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL2_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL2_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL2_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_CTL2_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL2_SCR_0_SEC_LCK_RANGE                   29:29
+#define GPIO_CTL2_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_CTL2_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_CTL2_SCR_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_CTL2_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_CTL2_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL2_SCR_0_SEC_WEN_RANGE                   28:28
+#define GPIO_CTL2_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_CTL2_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_CTL2_SCR_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_CTL2_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_CTL2_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL2_SCR_0_SEC_REN_RANGE                   27:27
+#define GPIO_CTL2_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_CTL2_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_CTL2_SCR_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_CTL2_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_CTL2_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_CTL2_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL2_SCR_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_CTL2_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_CTL2_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_CTL2_SCR_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_CTL2_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_CTL2_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_CTL2_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR7_SHIFT)
+#define GPIO_CTL2_SCR_0_PR7_RANGE                       23:23
+#define GPIO_CTL2_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_CTL2_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_CTL2_SCR_0_PR7_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_CTL2_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR6_SHIFT)
+#define GPIO_CTL2_SCR_0_PR6_RANGE                       22:22
+#define GPIO_CTL2_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_CTL2_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_CTL2_SCR_0_PR6_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_CTL2_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR5_SHIFT)
+#define GPIO_CTL2_SCR_0_PR5_RANGE                       21:21
+#define GPIO_CTL2_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_CTL2_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_CTL2_SCR_0_PR5_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_CTL2_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR4_SHIFT)
+#define GPIO_CTL2_SCR_0_PR4_RANGE                       20:20
+#define GPIO_CTL2_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_CTL2_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_CTL2_SCR_0_PR4_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_CTL2_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR3_SHIFT)
+#define GPIO_CTL2_SCR_0_PR3_RANGE                       19:19
+#define GPIO_CTL2_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_CTL2_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_CTL2_SCR_0_PR3_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_CTL2_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR2_SHIFT)
+#define GPIO_CTL2_SCR_0_PR2_RANGE                       18:18
+#define GPIO_CTL2_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_CTL2_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_CTL2_SCR_0_PR2_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_CTL2_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR1_SHIFT)
+#define GPIO_CTL2_SCR_0_PR1_RANGE                       17:17
+#define GPIO_CTL2_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_CTL2_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_CTL2_SCR_0_PR1_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_CTL2_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_PR0_SHIFT)
+#define GPIO_CTL2_SCR_0_PR0_RANGE                       16:16
+#define GPIO_CTL2_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_CTL2_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_CTL2_SCR_0_PR0_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_CTL2_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G7W_SHIFT)
+#define GPIO_CTL2_SCR_0_G7W_RANGE                       15:15
+#define GPIO_CTL2_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_CTL2_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_CTL2_SCR_0_G7W_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_CTL2_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G6W_SHIFT)
+#define GPIO_CTL2_SCR_0_G6W_RANGE                       14:14
+#define GPIO_CTL2_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_CTL2_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_CTL2_SCR_0_G6W_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_CTL2_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G5W_SHIFT)
+#define GPIO_CTL2_SCR_0_G5W_RANGE                       13:13
+#define GPIO_CTL2_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_CTL2_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_CTL2_SCR_0_G5W_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_CTL2_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G4W_SHIFT)
+#define GPIO_CTL2_SCR_0_G4W_RANGE                       12:12
+#define GPIO_CTL2_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_CTL2_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_CTL2_SCR_0_G4W_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_CTL2_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G3W_SHIFT)
+#define GPIO_CTL2_SCR_0_G3W_RANGE                       11:11
+#define GPIO_CTL2_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_CTL2_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_CTL2_SCR_0_G3W_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_CTL2_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G2W_SHIFT)
+#define GPIO_CTL2_SCR_0_G2W_RANGE                       10:10
+#define GPIO_CTL2_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_CTL2_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_CTL2_SCR_0_G2W_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_CTL2_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G1W_SHIFT)
+#define GPIO_CTL2_SCR_0_G1W_RANGE                       9:9
+#define GPIO_CTL2_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_CTL2_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_CTL2_SCR_0_G1W_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_CTL2_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G0W_SHIFT)
+#define GPIO_CTL2_SCR_0_G0W_RANGE                       8:8
+#define GPIO_CTL2_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_CTL2_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_CTL2_SCR_0_G0W_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_CTL2_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G7R_SHIFT)
+#define GPIO_CTL2_SCR_0_G7R_RANGE                       7:7
+#define GPIO_CTL2_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_CTL2_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_CTL2_SCR_0_G7R_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_CTL2_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G6R_SHIFT)
+#define GPIO_CTL2_SCR_0_G6R_RANGE                       6:6
+#define GPIO_CTL2_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_CTL2_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_CTL2_SCR_0_G6R_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_CTL2_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G5R_SHIFT)
+#define GPIO_CTL2_SCR_0_G5R_RANGE                       5:5
+#define GPIO_CTL2_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_CTL2_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_CTL2_SCR_0_G5R_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_CTL2_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G4R_SHIFT)
+#define GPIO_CTL2_SCR_0_G4R_RANGE                       4:4
+#define GPIO_CTL2_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_CTL2_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_CTL2_SCR_0_G4R_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_CTL2_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G3R_SHIFT)
+#define GPIO_CTL2_SCR_0_G3R_RANGE                       3:3
+#define GPIO_CTL2_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_CTL2_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_CTL2_SCR_0_G3R_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_CTL2_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G2R_SHIFT)
+#define GPIO_CTL2_SCR_0_G2R_RANGE                       2:2
+#define GPIO_CTL2_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_CTL2_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_CTL2_SCR_0_G2R_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_CTL2_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G1R_SHIFT)
+#define GPIO_CTL2_SCR_0_G1R_RANGE                       1:1
+#define GPIO_CTL2_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_CTL2_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_CTL2_SCR_0_G1R_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL2_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_CTL2_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL2_SCR_0_G0R_SHIFT)
+#define GPIO_CTL2_SCR_0_G0R_RANGE                       0:0
+#define GPIO_CTL2_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_CTL2_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_CTL2_SCR_0_G0R_WOFFSET                     0x0
+#define GPIO_CTL2_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL2_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL2_ICG_EN_OVERRIDE_0
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0                     MK_ADDR_CONST(0x2810)
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SECURE                      0x0
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_DUAL                        0x0
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CTL2_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INT0_ROUTE_MAPPING_0
+#define GPIO_M_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2814)
+#define GPIO_M_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_M_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_M_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_M_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_M_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_M_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_M_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_M_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INT1_ROUTE_MAPPING_0
+#define GPIO_M_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2818)
+#define GPIO_M_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_M_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_M_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_M_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_M_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_M_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_M_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_M_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INT2_ROUTE_MAPPING_0
+#define GPIO_M_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x281c)
+#define GPIO_M_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_M_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_M_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_M_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_M_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_M_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_M_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_M_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INT3_ROUTE_MAPPING_0
+#define GPIO_M_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2820)
+#define GPIO_M_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_M_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_M_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_M_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_M_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_M_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_M_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_M_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INT4_ROUTE_MAPPING_0
+#define GPIO_M_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2824)
+#define GPIO_M_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_M_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_M_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_M_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_M_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_M_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_M_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_M_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INT5_ROUTE_MAPPING_0
+#define GPIO_M_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2828)
+#define GPIO_M_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_M_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_M_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_M_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_M_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_M_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_M_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_M_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INT6_ROUTE_MAPPING_0
+#define GPIO_M_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x282c)
+#define GPIO_M_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_M_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_M_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_M_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_M_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_M_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_M_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_M_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INT7_ROUTE_MAPPING_0
+#define GPIO_M_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2830)
+#define GPIO_M_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_M_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_M_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_M_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_M_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_M_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_M_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_M_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INT0_ROUTE_MAPPING_0
+#define GPIO_N_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2834)
+#define GPIO_N_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_N_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_N_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_N_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_N_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_N_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_N_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_N_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INT1_ROUTE_MAPPING_0
+#define GPIO_N_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2838)
+#define GPIO_N_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_N_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_N_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_N_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_N_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_N_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_N_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_N_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INT2_ROUTE_MAPPING_0
+#define GPIO_N_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x283c)
+#define GPIO_N_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_N_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_N_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_N_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_N_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_N_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_N_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_N_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INT3_ROUTE_MAPPING_0
+#define GPIO_N_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2840)
+#define GPIO_N_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_N_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_N_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_N_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_N_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_N_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_N_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_N_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INT4_ROUTE_MAPPING_0
+#define GPIO_N_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2844)
+#define GPIO_N_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_N_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_N_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_N_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_N_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_N_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_N_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_N_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INT5_ROUTE_MAPPING_0
+#define GPIO_N_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2848)
+#define GPIO_N_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_N_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_N_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_N_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_N_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_N_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_N_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_N_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INT6_ROUTE_MAPPING_0
+#define GPIO_N_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x284c)
+#define GPIO_N_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_N_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_N_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_N_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_N_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_N_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_N_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_N_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INT7_ROUTE_MAPPING_0
+#define GPIO_N_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2850)
+#define GPIO_N_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_N_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_N_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_N_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_N_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_N_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_N_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_N_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INT0_ROUTE_MAPPING_0
+#define GPIO_P_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2854)
+#define GPIO_P_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_P_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_P_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_P_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_P_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_P_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_P_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_P_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INT1_ROUTE_MAPPING_0
+#define GPIO_P_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2858)
+#define GPIO_P_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_P_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_P_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_P_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_P_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_P_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_P_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_P_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INT2_ROUTE_MAPPING_0
+#define GPIO_P_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x285c)
+#define GPIO_P_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_P_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_P_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_P_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_P_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_P_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_P_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_P_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INT3_ROUTE_MAPPING_0
+#define GPIO_P_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2860)
+#define GPIO_P_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_P_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_P_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_P_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_P_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_P_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_P_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_P_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INT4_ROUTE_MAPPING_0
+#define GPIO_P_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2864)
+#define GPIO_P_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_P_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_P_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_P_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_P_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_P_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_P_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_P_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INT5_ROUTE_MAPPING_0
+#define GPIO_P_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2868)
+#define GPIO_P_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_P_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_P_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_P_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_P_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_P_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_P_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_P_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INT6_ROUTE_MAPPING_0
+#define GPIO_P_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x286c)
+#define GPIO_P_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_P_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_P_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_P_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_P_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_P_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_P_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_P_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INT7_ROUTE_MAPPING_0
+#define GPIO_P_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2870)
+#define GPIO_P_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_P_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_P_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_P_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_P_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_P_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_P_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_P_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INT0_ROUTE_MAPPING_0
+#define GPIO_Q_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2874)
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INT1_ROUTE_MAPPING_0
+#define GPIO_Q_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2878)
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INT2_ROUTE_MAPPING_0
+#define GPIO_Q_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x287c)
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INT3_ROUTE_MAPPING_0
+#define GPIO_Q_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2880)
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INT4_ROUTE_MAPPING_0
+#define GPIO_Q_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2884)
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INT5_ROUTE_MAPPING_0
+#define GPIO_Q_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2888)
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INT6_ROUTE_MAPPING_0
+#define GPIO_Q_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x288c)
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INT7_ROUTE_MAPPING_0
+#define GPIO_Q_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2890)
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INT0_ROUTE_MAPPING_0
+#define GPIO_R_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2894)
+#define GPIO_R_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_R_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_R_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_R_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_R_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_R_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_R_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_R_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INT1_ROUTE_MAPPING_0
+#define GPIO_R_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x2898)
+#define GPIO_R_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_R_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_R_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_R_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_R_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_R_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_R_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_R_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INT2_ROUTE_MAPPING_0
+#define GPIO_R_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x289c)
+#define GPIO_R_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_R_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_R_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_R_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_R_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_R_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_R_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_R_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INT3_ROUTE_MAPPING_0
+#define GPIO_R_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x28a0)
+#define GPIO_R_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_R_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_R_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_R_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_R_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_R_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_R_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_R_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INT4_ROUTE_MAPPING_0
+#define GPIO_R_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x28a4)
+#define GPIO_R_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_R_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_R_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_R_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_R_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_R_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_R_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_R_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INT5_ROUTE_MAPPING_0
+#define GPIO_R_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x28a8)
+#define GPIO_R_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_R_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_R_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_R_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_R_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_R_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_R_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_R_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INT6_ROUTE_MAPPING_0
+#define GPIO_R_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x28ac)
+#define GPIO_R_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_R_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_R_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_R_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_R_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_R_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_R_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_R_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INT7_ROUTE_MAPPING_0
+#define GPIO_R_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x28b0)
+#define GPIO_R_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_R_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_R_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL2_SCR_0
+#define GPIO_R_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL2_SCR_0
+#define GPIO_R_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_R_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_R_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_R_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL2_SPARE_0
+#define GPIO_CTL2_SPARE_0                       MK_ADDR_CONST(0x28b4)
+#define GPIO_CTL2_SPARE_0_SECURE                        0x0
+#define GPIO_CTL2_SPARE_0_DUAL                  0x0
+#define GPIO_CTL2_SPARE_0_SCR                   0
+#define GPIO_CTL2_SPARE_0_SCRREG                        0
+#define GPIO_CTL2_SPARE_0_WORD_COUNT                    0x1
+#define GPIO_CTL2_SPARE_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SPARE_0_RESET_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL2_SPARE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SPARE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SPARE_0_READ_MASK                     MK_MASK_CONST(0xffff)
+#define GPIO_CTL2_SPARE_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL2_SPARE_0_SPARE_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_CTL2_SPARE_0_SPARE_FIELD                   MK_FIELD_CONST(0xffff, GPIO_CTL2_SPARE_0_SPARE_SHIFT)
+#define GPIO_CTL2_SPARE_0_SPARE_RANGE                   15:0
+#define GPIO_CTL2_SPARE_0_SPARE_MSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL2_SPARE_0_SPARE_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL2_SPARE_0_SPARE_WOFFSET                 0x0
+#define GPIO_CTL2_SPARE_0_SPARE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SPARE_0_SPARE_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL2_SPARE_0_SPARE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SPARE_0_SPARE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SPARE_0_SPARE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL2_SPARE_0_SPARE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_VM_00_0
+#define GPIO_K_VM_00_0                  MK_ADDR_CONST(0x3000)
+#define GPIO_K_VM_00_0_SECURE                   0x0
+#define GPIO_K_VM_00_0_DUAL                     0x0
+#define GPIO_K_VM_00_0_SCR                      GPIO_CTL3_VM_SCR_0
+#define GPIO_K_VM_00_0_SCRREG                   GPIO_CTL3_VM_SCR_0
+#define GPIO_K_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_K_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_K_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM1_SHIFT)
+#define GPIO_K_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_K_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_K_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_K_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_K_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_K_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM2_SHIFT)
+#define GPIO_K_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_K_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_K_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_K_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_K_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_K_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM3_SHIFT)
+#define GPIO_K_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_K_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_K_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_K_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_K_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_K_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM4_SHIFT)
+#define GPIO_K_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_K_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_K_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_K_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_K_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_K_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM5_SHIFT)
+#define GPIO_K_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_K_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_K_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_K_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_K_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_K_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM6_SHIFT)
+#define GPIO_K_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_K_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_K_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_K_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_K_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_K_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM7_SHIFT)
+#define GPIO_K_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_K_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_K_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_K_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_K_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_K_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_00_0_VM8_SHIFT)
+#define GPIO_K_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_K_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_K_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_K_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_K_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_SCR_00_0
+#define GPIO_K_SCR_00_0                 MK_ADDR_CONST(0x3004)
+#define GPIO_K_SCR_00_0_SECURE                  0x0
+#define GPIO_K_SCR_00_0_DUAL                    0x0
+#define GPIO_K_SCR_00_0_SCR                     0
+#define GPIO_K_SCR_00_0_SCRREG                  0
+#define GPIO_K_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_K_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_K_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_K_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_K_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_K_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_K_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_K_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_K_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_K_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_K_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_K_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_K_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_K_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_K_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_K_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_K_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_K_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_K_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR7_SHIFT)
+#define GPIO_K_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_K_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR6_SHIFT)
+#define GPIO_K_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_K_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR5_SHIFT)
+#define GPIO_K_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_K_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR4_SHIFT)
+#define GPIO_K_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_K_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR3_SHIFT)
+#define GPIO_K_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_K_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR2_SHIFT)
+#define GPIO_K_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_K_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR1_SHIFT)
+#define GPIO_K_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_K_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_PR0_SHIFT)
+#define GPIO_K_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_K_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G7W_SHIFT)
+#define GPIO_K_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_K_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G6W_SHIFT)
+#define GPIO_K_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_K_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G5W_SHIFT)
+#define GPIO_K_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_K_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G4W_SHIFT)
+#define GPIO_K_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_K_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G3W_SHIFT)
+#define GPIO_K_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_K_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G2W_SHIFT)
+#define GPIO_K_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_K_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G1W_SHIFT)
+#define GPIO_K_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_K_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G0W_SHIFT)
+#define GPIO_K_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_K_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G7R_SHIFT)
+#define GPIO_K_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_K_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G6R_SHIFT)
+#define GPIO_K_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_K_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G5R_SHIFT)
+#define GPIO_K_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_K_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G4R_SHIFT)
+#define GPIO_K_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_K_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G3R_SHIFT)
+#define GPIO_K_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_K_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G2R_SHIFT)
+#define GPIO_K_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_K_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G1R_SHIFT)
+#define GPIO_K_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_K_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_00_0_G0R_SHIFT)
+#define GPIO_K_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_K_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_K_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_VM_01_0
+#define GPIO_K_VM_01_0                  MK_ADDR_CONST(0x3008)
+#define GPIO_K_VM_01_0_SECURE                   0x0
+#define GPIO_K_VM_01_0_DUAL                     0x0
+#define GPIO_K_VM_01_0_SCR                      GPIO_CTL3_VM_SCR_0
+#define GPIO_K_VM_01_0_SCRREG                   GPIO_CTL3_VM_SCR_0
+#define GPIO_K_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_K_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_K_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM1_SHIFT)
+#define GPIO_K_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_K_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_K_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_K_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_K_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_K_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM2_SHIFT)
+#define GPIO_K_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_K_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_K_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_K_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_K_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_K_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM3_SHIFT)
+#define GPIO_K_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_K_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_K_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_K_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_K_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_K_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM4_SHIFT)
+#define GPIO_K_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_K_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_K_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_K_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_K_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_K_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM5_SHIFT)
+#define GPIO_K_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_K_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_K_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_K_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_K_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_K_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM6_SHIFT)
+#define GPIO_K_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_K_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_K_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_K_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_K_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_K_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM7_SHIFT)
+#define GPIO_K_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_K_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_K_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_K_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_K_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_K_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_01_0_VM8_SHIFT)
+#define GPIO_K_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_K_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_K_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_K_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_K_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_SCR_01_0
+#define GPIO_K_SCR_01_0                 MK_ADDR_CONST(0x300c)
+#define GPIO_K_SCR_01_0_SECURE                  0x0
+#define GPIO_K_SCR_01_0_DUAL                    0x0
+#define GPIO_K_SCR_01_0_SCR                     0
+#define GPIO_K_SCR_01_0_SCRREG                  0
+#define GPIO_K_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_K_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_K_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_K_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_K_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_K_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_K_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_K_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_K_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_K_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_K_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_K_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_K_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_K_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_K_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_K_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_K_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_K_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_K_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR7_SHIFT)
+#define GPIO_K_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_K_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR6_SHIFT)
+#define GPIO_K_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_K_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR5_SHIFT)
+#define GPIO_K_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_K_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR4_SHIFT)
+#define GPIO_K_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_K_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR3_SHIFT)
+#define GPIO_K_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_K_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR2_SHIFT)
+#define GPIO_K_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_K_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR1_SHIFT)
+#define GPIO_K_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_K_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_PR0_SHIFT)
+#define GPIO_K_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_K_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G7W_SHIFT)
+#define GPIO_K_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_K_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G6W_SHIFT)
+#define GPIO_K_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_K_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G5W_SHIFT)
+#define GPIO_K_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_K_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G4W_SHIFT)
+#define GPIO_K_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_K_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G3W_SHIFT)
+#define GPIO_K_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_K_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G2W_SHIFT)
+#define GPIO_K_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_K_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G1W_SHIFT)
+#define GPIO_K_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_K_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G0W_SHIFT)
+#define GPIO_K_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_K_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G7R_SHIFT)
+#define GPIO_K_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_K_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G6R_SHIFT)
+#define GPIO_K_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_K_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G5R_SHIFT)
+#define GPIO_K_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_K_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G4R_SHIFT)
+#define GPIO_K_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_K_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G3R_SHIFT)
+#define GPIO_K_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_K_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G2R_SHIFT)
+#define GPIO_K_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_K_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G1R_SHIFT)
+#define GPIO_K_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_K_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_01_0_G0R_SHIFT)
+#define GPIO_K_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_K_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_K_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_VM_02_0
+#define GPIO_K_VM_02_0                  MK_ADDR_CONST(0x3010)
+#define GPIO_K_VM_02_0_SECURE                   0x0
+#define GPIO_K_VM_02_0_DUAL                     0x0
+#define GPIO_K_VM_02_0_SCR                      GPIO_CTL3_VM_SCR_0
+#define GPIO_K_VM_02_0_SCRREG                   GPIO_CTL3_VM_SCR_0
+#define GPIO_K_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_K_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_K_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM1_SHIFT)
+#define GPIO_K_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_K_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_K_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_K_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_K_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_K_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM2_SHIFT)
+#define GPIO_K_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_K_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_K_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_K_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_K_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_K_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM3_SHIFT)
+#define GPIO_K_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_K_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_K_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_K_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_K_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_K_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM4_SHIFT)
+#define GPIO_K_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_K_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_K_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_K_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_K_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_K_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM5_SHIFT)
+#define GPIO_K_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_K_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_K_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_K_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_K_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_K_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM6_SHIFT)
+#define GPIO_K_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_K_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_K_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_K_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_K_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_K_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM7_SHIFT)
+#define GPIO_K_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_K_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_K_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_K_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_K_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_K_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_02_0_VM8_SHIFT)
+#define GPIO_K_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_K_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_K_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_K_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_K_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_SCR_02_0
+#define GPIO_K_SCR_02_0                 MK_ADDR_CONST(0x3014)
+#define GPIO_K_SCR_02_0_SECURE                  0x0
+#define GPIO_K_SCR_02_0_DUAL                    0x0
+#define GPIO_K_SCR_02_0_SCR                     0
+#define GPIO_K_SCR_02_0_SCRREG                  0
+#define GPIO_K_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_K_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_K_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_K_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_K_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_K_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_K_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_K_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_K_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_K_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_K_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_K_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_K_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_K_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_K_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_K_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_K_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_K_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_K_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR7_SHIFT)
+#define GPIO_K_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_K_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR6_SHIFT)
+#define GPIO_K_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_K_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR5_SHIFT)
+#define GPIO_K_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_K_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR4_SHIFT)
+#define GPIO_K_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_K_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR3_SHIFT)
+#define GPIO_K_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_K_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR2_SHIFT)
+#define GPIO_K_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_K_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR1_SHIFT)
+#define GPIO_K_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_K_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_PR0_SHIFT)
+#define GPIO_K_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_K_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G7W_SHIFT)
+#define GPIO_K_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_K_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G6W_SHIFT)
+#define GPIO_K_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_K_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G5W_SHIFT)
+#define GPIO_K_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_K_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G4W_SHIFT)
+#define GPIO_K_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_K_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G3W_SHIFT)
+#define GPIO_K_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_K_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G2W_SHIFT)
+#define GPIO_K_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_K_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G1W_SHIFT)
+#define GPIO_K_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_K_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G0W_SHIFT)
+#define GPIO_K_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_K_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G7R_SHIFT)
+#define GPIO_K_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_K_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G6R_SHIFT)
+#define GPIO_K_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_K_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G5R_SHIFT)
+#define GPIO_K_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_K_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G4R_SHIFT)
+#define GPIO_K_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_K_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G3R_SHIFT)
+#define GPIO_K_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_K_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G2R_SHIFT)
+#define GPIO_K_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_K_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G1R_SHIFT)
+#define GPIO_K_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_K_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_02_0_G0R_SHIFT)
+#define GPIO_K_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_K_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_K_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_VM_03_0
+#define GPIO_K_VM_03_0                  MK_ADDR_CONST(0x3018)
+#define GPIO_K_VM_03_0_SECURE                   0x0
+#define GPIO_K_VM_03_0_DUAL                     0x0
+#define GPIO_K_VM_03_0_SCR                      GPIO_CTL3_VM_SCR_0
+#define GPIO_K_VM_03_0_SCRREG                   GPIO_CTL3_VM_SCR_0
+#define GPIO_K_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_K_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_K_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM1_SHIFT)
+#define GPIO_K_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_K_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_K_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_K_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_K_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_K_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM2_SHIFT)
+#define GPIO_K_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_K_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_K_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_K_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_K_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_K_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM3_SHIFT)
+#define GPIO_K_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_K_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_K_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_K_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_K_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_K_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM4_SHIFT)
+#define GPIO_K_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_K_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_K_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_K_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_K_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_K_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM5_SHIFT)
+#define GPIO_K_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_K_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_K_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_K_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_K_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_K_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM6_SHIFT)
+#define GPIO_K_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_K_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_K_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_K_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_K_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_K_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM7_SHIFT)
+#define GPIO_K_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_K_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_K_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_K_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_K_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_K_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_03_0_VM8_SHIFT)
+#define GPIO_K_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_K_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_K_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_K_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_K_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_SCR_03_0
+#define GPIO_K_SCR_03_0                 MK_ADDR_CONST(0x301c)
+#define GPIO_K_SCR_03_0_SECURE                  0x0
+#define GPIO_K_SCR_03_0_DUAL                    0x0
+#define GPIO_K_SCR_03_0_SCR                     0
+#define GPIO_K_SCR_03_0_SCRREG                  0
+#define GPIO_K_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_K_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_K_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_K_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_K_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_K_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_K_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_K_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_K_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_K_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_K_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_K_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_K_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_K_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_K_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_K_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_K_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_K_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_K_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR7_SHIFT)
+#define GPIO_K_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_K_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR6_SHIFT)
+#define GPIO_K_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_K_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR5_SHIFT)
+#define GPIO_K_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_K_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR4_SHIFT)
+#define GPIO_K_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_K_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR3_SHIFT)
+#define GPIO_K_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_K_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR2_SHIFT)
+#define GPIO_K_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_K_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR1_SHIFT)
+#define GPIO_K_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_K_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_PR0_SHIFT)
+#define GPIO_K_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_K_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G7W_SHIFT)
+#define GPIO_K_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_K_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G6W_SHIFT)
+#define GPIO_K_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_K_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G5W_SHIFT)
+#define GPIO_K_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_K_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G4W_SHIFT)
+#define GPIO_K_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_K_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G3W_SHIFT)
+#define GPIO_K_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_K_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G2W_SHIFT)
+#define GPIO_K_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_K_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G1W_SHIFT)
+#define GPIO_K_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_K_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G0W_SHIFT)
+#define GPIO_K_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_K_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G7R_SHIFT)
+#define GPIO_K_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_K_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G6R_SHIFT)
+#define GPIO_K_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_K_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G5R_SHIFT)
+#define GPIO_K_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_K_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G4R_SHIFT)
+#define GPIO_K_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_K_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G3R_SHIFT)
+#define GPIO_K_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_K_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G2R_SHIFT)
+#define GPIO_K_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_K_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G1R_SHIFT)
+#define GPIO_K_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_K_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_03_0_G0R_SHIFT)
+#define GPIO_K_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_K_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_K_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_VM_04_0
+#define GPIO_K_VM_04_0                  MK_ADDR_CONST(0x3020)
+#define GPIO_K_VM_04_0_SECURE                   0x0
+#define GPIO_K_VM_04_0_DUAL                     0x0
+#define GPIO_K_VM_04_0_SCR                      GPIO_CTL3_VM_SCR_0
+#define GPIO_K_VM_04_0_SCRREG                   GPIO_CTL3_VM_SCR_0
+#define GPIO_K_VM_04_0_WORD_COUNT                       0x1
+#define GPIO_K_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_K_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM1_SHIFT)
+#define GPIO_K_VM_04_0_VM1_RANGE                        1:0
+#define GPIO_K_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_K_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_K_VM_04_0_VM1_WOFFSET                      0x0
+#define GPIO_K_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_K_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM2_SHIFT)
+#define GPIO_K_VM_04_0_VM2_RANGE                        3:2
+#define GPIO_K_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_K_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_K_VM_04_0_VM2_WOFFSET                      0x0
+#define GPIO_K_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_K_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM3_SHIFT)
+#define GPIO_K_VM_04_0_VM3_RANGE                        5:4
+#define GPIO_K_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_K_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_K_VM_04_0_VM3_WOFFSET                      0x0
+#define GPIO_K_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_K_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM4_SHIFT)
+#define GPIO_K_VM_04_0_VM4_RANGE                        7:6
+#define GPIO_K_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_K_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_K_VM_04_0_VM4_WOFFSET                      0x0
+#define GPIO_K_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_K_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM5_SHIFT)
+#define GPIO_K_VM_04_0_VM5_RANGE                        9:8
+#define GPIO_K_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_K_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_K_VM_04_0_VM5_WOFFSET                      0x0
+#define GPIO_K_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_K_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM6_SHIFT)
+#define GPIO_K_VM_04_0_VM6_RANGE                        11:10
+#define GPIO_K_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_K_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_K_VM_04_0_VM6_WOFFSET                      0x0
+#define GPIO_K_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_K_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM7_SHIFT)
+#define GPIO_K_VM_04_0_VM7_RANGE                        13:12
+#define GPIO_K_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_K_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_K_VM_04_0_VM7_WOFFSET                      0x0
+#define GPIO_K_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_K_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_04_0_VM8_SHIFT)
+#define GPIO_K_VM_04_0_VM8_RANGE                        15:14
+#define GPIO_K_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_K_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_K_VM_04_0_VM8_WOFFSET                      0x0
+#define GPIO_K_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_SCR_04_0
+#define GPIO_K_SCR_04_0                 MK_ADDR_CONST(0x3024)
+#define GPIO_K_SCR_04_0_SECURE                  0x0
+#define GPIO_K_SCR_04_0_DUAL                    0x0
+#define GPIO_K_SCR_04_0_SCR                     0
+#define GPIO_K_SCR_04_0_SCRREG                  0
+#define GPIO_K_SCR_04_0_WORD_COUNT                      0x1
+#define GPIO_K_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_K_SCR_04_0_SEC_LCK_RANGE                   29:29
+#define GPIO_K_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_04_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_K_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_K_SCR_04_0_SEC_WEN_RANGE                   28:28
+#define GPIO_K_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_04_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_K_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_K_SCR_04_0_SEC_REN_RANGE                   27:27
+#define GPIO_K_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_04_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_K_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_K_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_K_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_K_SCR_04_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_K_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_K_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_K_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_K_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_K_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR7_SHIFT)
+#define GPIO_K_SCR_04_0_PR7_RANGE                       23:23
+#define GPIO_K_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_04_0_PR7_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR6_SHIFT)
+#define GPIO_K_SCR_04_0_PR6_RANGE                       22:22
+#define GPIO_K_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_04_0_PR6_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR5_SHIFT)
+#define GPIO_K_SCR_04_0_PR5_RANGE                       21:21
+#define GPIO_K_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_04_0_PR5_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR4_SHIFT)
+#define GPIO_K_SCR_04_0_PR4_RANGE                       20:20
+#define GPIO_K_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_04_0_PR4_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR3_SHIFT)
+#define GPIO_K_SCR_04_0_PR3_RANGE                       19:19
+#define GPIO_K_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_04_0_PR3_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR2_SHIFT)
+#define GPIO_K_SCR_04_0_PR2_RANGE                       18:18
+#define GPIO_K_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_04_0_PR2_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR1_SHIFT)
+#define GPIO_K_SCR_04_0_PR1_RANGE                       17:17
+#define GPIO_K_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_04_0_PR1_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_PR0_SHIFT)
+#define GPIO_K_SCR_04_0_PR0_RANGE                       16:16
+#define GPIO_K_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_04_0_PR0_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G7W_SHIFT)
+#define GPIO_K_SCR_04_0_G7W_RANGE                       15:15
+#define GPIO_K_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_04_0_G7W_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G6W_SHIFT)
+#define GPIO_K_SCR_04_0_G6W_RANGE                       14:14
+#define GPIO_K_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_04_0_G6W_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G5W_SHIFT)
+#define GPIO_K_SCR_04_0_G5W_RANGE                       13:13
+#define GPIO_K_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_04_0_G5W_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G4W_SHIFT)
+#define GPIO_K_SCR_04_0_G4W_RANGE                       12:12
+#define GPIO_K_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_04_0_G4W_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G3W_SHIFT)
+#define GPIO_K_SCR_04_0_G3W_RANGE                       11:11
+#define GPIO_K_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_04_0_G3W_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G2W_SHIFT)
+#define GPIO_K_SCR_04_0_G2W_RANGE                       10:10
+#define GPIO_K_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_04_0_G2W_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G1W_SHIFT)
+#define GPIO_K_SCR_04_0_G1W_RANGE                       9:9
+#define GPIO_K_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_04_0_G1W_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G0W_SHIFT)
+#define GPIO_K_SCR_04_0_G0W_RANGE                       8:8
+#define GPIO_K_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_04_0_G0W_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G7R_SHIFT)
+#define GPIO_K_SCR_04_0_G7R_RANGE                       7:7
+#define GPIO_K_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_04_0_G7R_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G6R_SHIFT)
+#define GPIO_K_SCR_04_0_G6R_RANGE                       6:6
+#define GPIO_K_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_04_0_G6R_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G5R_SHIFT)
+#define GPIO_K_SCR_04_0_G5R_RANGE                       5:5
+#define GPIO_K_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_04_0_G5R_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G4R_SHIFT)
+#define GPIO_K_SCR_04_0_G4R_RANGE                       4:4
+#define GPIO_K_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_04_0_G4R_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G3R_SHIFT)
+#define GPIO_K_SCR_04_0_G3R_RANGE                       3:3
+#define GPIO_K_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_04_0_G3R_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G2R_SHIFT)
+#define GPIO_K_SCR_04_0_G2R_RANGE                       2:2
+#define GPIO_K_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_04_0_G2R_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G1R_SHIFT)
+#define GPIO_K_SCR_04_0_G1R_RANGE                       1:1
+#define GPIO_K_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_04_0_G1R_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_04_0_G0R_SHIFT)
+#define GPIO_K_SCR_04_0_G0R_RANGE                       0:0
+#define GPIO_K_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_04_0_G0R_WOFFSET                     0x0
+#define GPIO_K_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_VM_05_0
+#define GPIO_K_VM_05_0                  MK_ADDR_CONST(0x3028)
+#define GPIO_K_VM_05_0_SECURE                   0x0
+#define GPIO_K_VM_05_0_DUAL                     0x0
+#define GPIO_K_VM_05_0_SCR                      GPIO_CTL3_VM_SCR_0
+#define GPIO_K_VM_05_0_SCRREG                   GPIO_CTL3_VM_SCR_0
+#define GPIO_K_VM_05_0_WORD_COUNT                       0x1
+#define GPIO_K_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_K_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM1_SHIFT)
+#define GPIO_K_VM_05_0_VM1_RANGE                        1:0
+#define GPIO_K_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_K_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_K_VM_05_0_VM1_WOFFSET                      0x0
+#define GPIO_K_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_K_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM2_SHIFT)
+#define GPIO_K_VM_05_0_VM2_RANGE                        3:2
+#define GPIO_K_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_K_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_K_VM_05_0_VM2_WOFFSET                      0x0
+#define GPIO_K_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_K_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM3_SHIFT)
+#define GPIO_K_VM_05_0_VM3_RANGE                        5:4
+#define GPIO_K_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_K_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_K_VM_05_0_VM3_WOFFSET                      0x0
+#define GPIO_K_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_K_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM4_SHIFT)
+#define GPIO_K_VM_05_0_VM4_RANGE                        7:6
+#define GPIO_K_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_K_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_K_VM_05_0_VM4_WOFFSET                      0x0
+#define GPIO_K_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_K_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM5_SHIFT)
+#define GPIO_K_VM_05_0_VM5_RANGE                        9:8
+#define GPIO_K_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_K_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_K_VM_05_0_VM5_WOFFSET                      0x0
+#define GPIO_K_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_K_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM6_SHIFT)
+#define GPIO_K_VM_05_0_VM6_RANGE                        11:10
+#define GPIO_K_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_K_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_K_VM_05_0_VM6_WOFFSET                      0x0
+#define GPIO_K_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_K_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM7_SHIFT)
+#define GPIO_K_VM_05_0_VM7_RANGE                        13:12
+#define GPIO_K_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_K_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_K_VM_05_0_VM7_WOFFSET                      0x0
+#define GPIO_K_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_K_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_05_0_VM8_SHIFT)
+#define GPIO_K_VM_05_0_VM8_RANGE                        15:14
+#define GPIO_K_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_K_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_K_VM_05_0_VM8_WOFFSET                      0x0
+#define GPIO_K_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_SCR_05_0
+#define GPIO_K_SCR_05_0                 MK_ADDR_CONST(0x302c)
+#define GPIO_K_SCR_05_0_SECURE                  0x0
+#define GPIO_K_SCR_05_0_DUAL                    0x0
+#define GPIO_K_SCR_05_0_SCR                     0
+#define GPIO_K_SCR_05_0_SCRREG                  0
+#define GPIO_K_SCR_05_0_WORD_COUNT                      0x1
+#define GPIO_K_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_K_SCR_05_0_SEC_LCK_RANGE                   29:29
+#define GPIO_K_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_05_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_K_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_K_SCR_05_0_SEC_WEN_RANGE                   28:28
+#define GPIO_K_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_05_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_K_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_K_SCR_05_0_SEC_REN_RANGE                   27:27
+#define GPIO_K_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_05_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_K_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_K_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_K_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_K_SCR_05_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_K_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_K_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_K_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_K_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_K_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR7_SHIFT)
+#define GPIO_K_SCR_05_0_PR7_RANGE                       23:23
+#define GPIO_K_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_05_0_PR7_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR6_SHIFT)
+#define GPIO_K_SCR_05_0_PR6_RANGE                       22:22
+#define GPIO_K_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_05_0_PR6_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR5_SHIFT)
+#define GPIO_K_SCR_05_0_PR5_RANGE                       21:21
+#define GPIO_K_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_05_0_PR5_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR4_SHIFT)
+#define GPIO_K_SCR_05_0_PR4_RANGE                       20:20
+#define GPIO_K_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_05_0_PR4_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR3_SHIFT)
+#define GPIO_K_SCR_05_0_PR3_RANGE                       19:19
+#define GPIO_K_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_05_0_PR3_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR2_SHIFT)
+#define GPIO_K_SCR_05_0_PR2_RANGE                       18:18
+#define GPIO_K_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_05_0_PR2_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR1_SHIFT)
+#define GPIO_K_SCR_05_0_PR1_RANGE                       17:17
+#define GPIO_K_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_05_0_PR1_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_PR0_SHIFT)
+#define GPIO_K_SCR_05_0_PR0_RANGE                       16:16
+#define GPIO_K_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_05_0_PR0_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G7W_SHIFT)
+#define GPIO_K_SCR_05_0_G7W_RANGE                       15:15
+#define GPIO_K_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_05_0_G7W_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G6W_SHIFT)
+#define GPIO_K_SCR_05_0_G6W_RANGE                       14:14
+#define GPIO_K_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_05_0_G6W_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G5W_SHIFT)
+#define GPIO_K_SCR_05_0_G5W_RANGE                       13:13
+#define GPIO_K_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_05_0_G5W_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G4W_SHIFT)
+#define GPIO_K_SCR_05_0_G4W_RANGE                       12:12
+#define GPIO_K_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_05_0_G4W_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G3W_SHIFT)
+#define GPIO_K_SCR_05_0_G3W_RANGE                       11:11
+#define GPIO_K_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_05_0_G3W_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G2W_SHIFT)
+#define GPIO_K_SCR_05_0_G2W_RANGE                       10:10
+#define GPIO_K_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_05_0_G2W_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G1W_SHIFT)
+#define GPIO_K_SCR_05_0_G1W_RANGE                       9:9
+#define GPIO_K_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_05_0_G1W_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G0W_SHIFT)
+#define GPIO_K_SCR_05_0_G0W_RANGE                       8:8
+#define GPIO_K_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_05_0_G0W_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G7R_SHIFT)
+#define GPIO_K_SCR_05_0_G7R_RANGE                       7:7
+#define GPIO_K_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_05_0_G7R_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G6R_SHIFT)
+#define GPIO_K_SCR_05_0_G6R_RANGE                       6:6
+#define GPIO_K_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_05_0_G6R_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G5R_SHIFT)
+#define GPIO_K_SCR_05_0_G5R_RANGE                       5:5
+#define GPIO_K_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_05_0_G5R_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G4R_SHIFT)
+#define GPIO_K_SCR_05_0_G4R_RANGE                       4:4
+#define GPIO_K_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_05_0_G4R_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G3R_SHIFT)
+#define GPIO_K_SCR_05_0_G3R_RANGE                       3:3
+#define GPIO_K_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_05_0_G3R_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G2R_SHIFT)
+#define GPIO_K_SCR_05_0_G2R_RANGE                       2:2
+#define GPIO_K_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_05_0_G2R_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G1R_SHIFT)
+#define GPIO_K_SCR_05_0_G1R_RANGE                       1:1
+#define GPIO_K_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_05_0_G1R_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_05_0_G0R_SHIFT)
+#define GPIO_K_SCR_05_0_G0R_RANGE                       0:0
+#define GPIO_K_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_05_0_G0R_WOFFSET                     0x0
+#define GPIO_K_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_VM_06_0
+#define GPIO_K_VM_06_0                  MK_ADDR_CONST(0x3030)
+#define GPIO_K_VM_06_0_SECURE                   0x0
+#define GPIO_K_VM_06_0_DUAL                     0x0
+#define GPIO_K_VM_06_0_SCR                      GPIO_CTL3_VM_SCR_0
+#define GPIO_K_VM_06_0_SCRREG                   GPIO_CTL3_VM_SCR_0
+#define GPIO_K_VM_06_0_WORD_COUNT                       0x1
+#define GPIO_K_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_K_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM1_SHIFT)
+#define GPIO_K_VM_06_0_VM1_RANGE                        1:0
+#define GPIO_K_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_K_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_K_VM_06_0_VM1_WOFFSET                      0x0
+#define GPIO_K_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_K_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM2_SHIFT)
+#define GPIO_K_VM_06_0_VM2_RANGE                        3:2
+#define GPIO_K_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_K_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_K_VM_06_0_VM2_WOFFSET                      0x0
+#define GPIO_K_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_K_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM3_SHIFT)
+#define GPIO_K_VM_06_0_VM3_RANGE                        5:4
+#define GPIO_K_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_K_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_K_VM_06_0_VM3_WOFFSET                      0x0
+#define GPIO_K_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_K_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM4_SHIFT)
+#define GPIO_K_VM_06_0_VM4_RANGE                        7:6
+#define GPIO_K_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_K_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_K_VM_06_0_VM4_WOFFSET                      0x0
+#define GPIO_K_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_K_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM5_SHIFT)
+#define GPIO_K_VM_06_0_VM5_RANGE                        9:8
+#define GPIO_K_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_K_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_K_VM_06_0_VM5_WOFFSET                      0x0
+#define GPIO_K_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_K_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM6_SHIFT)
+#define GPIO_K_VM_06_0_VM6_RANGE                        11:10
+#define GPIO_K_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_K_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_K_VM_06_0_VM6_WOFFSET                      0x0
+#define GPIO_K_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_K_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM7_SHIFT)
+#define GPIO_K_VM_06_0_VM7_RANGE                        13:12
+#define GPIO_K_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_K_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_K_VM_06_0_VM7_WOFFSET                      0x0
+#define GPIO_K_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_K_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_06_0_VM8_SHIFT)
+#define GPIO_K_VM_06_0_VM8_RANGE                        15:14
+#define GPIO_K_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_K_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_K_VM_06_0_VM8_WOFFSET                      0x0
+#define GPIO_K_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_SCR_06_0
+#define GPIO_K_SCR_06_0                 MK_ADDR_CONST(0x3034)
+#define GPIO_K_SCR_06_0_SECURE                  0x0
+#define GPIO_K_SCR_06_0_DUAL                    0x0
+#define GPIO_K_SCR_06_0_SCR                     0
+#define GPIO_K_SCR_06_0_SCRREG                  0
+#define GPIO_K_SCR_06_0_WORD_COUNT                      0x1
+#define GPIO_K_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_SEC_LCK_SHIFT)
+#define GPIO_K_SCR_06_0_SEC_LCK_RANGE                   29:29
+#define GPIO_K_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_06_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_K_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_SEC_WEN_SHIFT)
+#define GPIO_K_SCR_06_0_SEC_WEN_RANGE                   28:28
+#define GPIO_K_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_06_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_K_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_SEC_REN_SHIFT)
+#define GPIO_K_SCR_06_0_SEC_REN_RANGE                   27:27
+#define GPIO_K_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_06_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_K_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_K_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_K_SCR_06_0_SEC_OWNER_SHIFT)
+#define GPIO_K_SCR_06_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_K_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_K_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_K_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_K_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_K_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR7_SHIFT)
+#define GPIO_K_SCR_06_0_PR7_RANGE                       23:23
+#define GPIO_K_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_06_0_PR7_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR6_SHIFT)
+#define GPIO_K_SCR_06_0_PR6_RANGE                       22:22
+#define GPIO_K_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_06_0_PR6_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR5_SHIFT)
+#define GPIO_K_SCR_06_0_PR5_RANGE                       21:21
+#define GPIO_K_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_06_0_PR5_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR4_SHIFT)
+#define GPIO_K_SCR_06_0_PR4_RANGE                       20:20
+#define GPIO_K_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_06_0_PR4_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR3_SHIFT)
+#define GPIO_K_SCR_06_0_PR3_RANGE                       19:19
+#define GPIO_K_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_06_0_PR3_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR2_SHIFT)
+#define GPIO_K_SCR_06_0_PR2_RANGE                       18:18
+#define GPIO_K_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_06_0_PR2_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR1_SHIFT)
+#define GPIO_K_SCR_06_0_PR1_RANGE                       17:17
+#define GPIO_K_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_06_0_PR1_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_PR0_SHIFT)
+#define GPIO_K_SCR_06_0_PR0_RANGE                       16:16
+#define GPIO_K_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_06_0_PR0_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G7W_SHIFT)
+#define GPIO_K_SCR_06_0_G7W_RANGE                       15:15
+#define GPIO_K_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_06_0_G7W_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G6W_SHIFT)
+#define GPIO_K_SCR_06_0_G6W_RANGE                       14:14
+#define GPIO_K_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_06_0_G6W_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G5W_SHIFT)
+#define GPIO_K_SCR_06_0_G5W_RANGE                       13:13
+#define GPIO_K_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_06_0_G5W_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G4W_SHIFT)
+#define GPIO_K_SCR_06_0_G4W_RANGE                       12:12
+#define GPIO_K_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_06_0_G4W_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G3W_SHIFT)
+#define GPIO_K_SCR_06_0_G3W_RANGE                       11:11
+#define GPIO_K_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_06_0_G3W_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G2W_SHIFT)
+#define GPIO_K_SCR_06_0_G2W_RANGE                       10:10
+#define GPIO_K_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_06_0_G2W_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G1W_SHIFT)
+#define GPIO_K_SCR_06_0_G1W_RANGE                       9:9
+#define GPIO_K_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_06_0_G1W_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G0W_SHIFT)
+#define GPIO_K_SCR_06_0_G0W_RANGE                       8:8
+#define GPIO_K_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_06_0_G0W_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G7R_SHIFT)
+#define GPIO_K_SCR_06_0_G7R_RANGE                       7:7
+#define GPIO_K_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_06_0_G7R_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G6R_SHIFT)
+#define GPIO_K_SCR_06_0_G6R_RANGE                       6:6
+#define GPIO_K_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_06_0_G6R_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G5R_SHIFT)
+#define GPIO_K_SCR_06_0_G5R_RANGE                       5:5
+#define GPIO_K_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_06_0_G5R_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G4R_SHIFT)
+#define GPIO_K_SCR_06_0_G4R_RANGE                       4:4
+#define GPIO_K_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_06_0_G4R_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G3R_SHIFT)
+#define GPIO_K_SCR_06_0_G3R_RANGE                       3:3
+#define GPIO_K_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_06_0_G3R_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G2R_SHIFT)
+#define GPIO_K_SCR_06_0_G2R_RANGE                       2:2
+#define GPIO_K_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_06_0_G2R_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G1R_SHIFT)
+#define GPIO_K_SCR_06_0_G1R_RANGE                       1:1
+#define GPIO_K_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_06_0_G1R_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_06_0_G0R_SHIFT)
+#define GPIO_K_SCR_06_0_G0R_RANGE                       0:0
+#define GPIO_K_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_06_0_G0R_WOFFSET                     0x0
+#define GPIO_K_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_VM_07_0
+#define GPIO_K_VM_07_0                  MK_ADDR_CONST(0x3038)
+#define GPIO_K_VM_07_0_SECURE                   0x0
+#define GPIO_K_VM_07_0_DUAL                     0x0
+#define GPIO_K_VM_07_0_SCR                      GPIO_CTL3_VM_SCR_0
+#define GPIO_K_VM_07_0_SCRREG                   GPIO_CTL3_VM_SCR_0
+#define GPIO_K_VM_07_0_WORD_COUNT                       0x1
+#define GPIO_K_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_K_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_K_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM1_SHIFT)
+#define GPIO_K_VM_07_0_VM1_RANGE                        1:0
+#define GPIO_K_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_K_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_K_VM_07_0_VM1_WOFFSET                      0x0
+#define GPIO_K_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_K_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM2_SHIFT)
+#define GPIO_K_VM_07_0_VM2_RANGE                        3:2
+#define GPIO_K_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_K_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_K_VM_07_0_VM2_WOFFSET                      0x0
+#define GPIO_K_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_K_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM3_SHIFT)
+#define GPIO_K_VM_07_0_VM3_RANGE                        5:4
+#define GPIO_K_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_K_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_K_VM_07_0_VM3_WOFFSET                      0x0
+#define GPIO_K_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_K_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM4_SHIFT)
+#define GPIO_K_VM_07_0_VM4_RANGE                        7:6
+#define GPIO_K_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_K_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_K_VM_07_0_VM4_WOFFSET                      0x0
+#define GPIO_K_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_K_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM5_SHIFT)
+#define GPIO_K_VM_07_0_VM5_RANGE                        9:8
+#define GPIO_K_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_K_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_K_VM_07_0_VM5_WOFFSET                      0x0
+#define GPIO_K_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_K_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM6_SHIFT)
+#define GPIO_K_VM_07_0_VM6_RANGE                        11:10
+#define GPIO_K_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_K_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_K_VM_07_0_VM6_WOFFSET                      0x0
+#define GPIO_K_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_K_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM7_SHIFT)
+#define GPIO_K_VM_07_0_VM7_RANGE                        13:12
+#define GPIO_K_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_K_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_K_VM_07_0_VM7_WOFFSET                      0x0
+#define GPIO_K_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_K_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_K_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_K_VM_07_0_VM8_SHIFT)
+#define GPIO_K_VM_07_0_VM8_RANGE                        15:14
+#define GPIO_K_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_K_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_K_VM_07_0_VM8_WOFFSET                      0x0
+#define GPIO_K_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_K_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_K_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_SCR_07_0
+#define GPIO_K_SCR_07_0                 MK_ADDR_CONST(0x303c)
+#define GPIO_K_SCR_07_0_SECURE                  0x0
+#define GPIO_K_SCR_07_0_DUAL                    0x0
+#define GPIO_K_SCR_07_0_SCR                     0
+#define GPIO_K_SCR_07_0_SCRREG                  0
+#define GPIO_K_SCR_07_0_WORD_COUNT                      0x1
+#define GPIO_K_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_K_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_SEC_LCK_SHIFT)
+#define GPIO_K_SCR_07_0_SEC_LCK_RANGE                   29:29
+#define GPIO_K_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_K_SCR_07_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_K_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_SEC_WEN_SHIFT)
+#define GPIO_K_SCR_07_0_SEC_WEN_RANGE                   28:28
+#define GPIO_K_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_K_SCR_07_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_K_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_SEC_REN_SHIFT)
+#define GPIO_K_SCR_07_0_SEC_REN_RANGE                   27:27
+#define GPIO_K_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_K_SCR_07_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_K_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_K_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_K_SCR_07_0_SEC_OWNER_SHIFT)
+#define GPIO_K_SCR_07_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_K_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_K_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_K_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_K_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_K_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR7_SHIFT)
+#define GPIO_K_SCR_07_0_PR7_RANGE                       23:23
+#define GPIO_K_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_K_SCR_07_0_PR7_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR6_SHIFT)
+#define GPIO_K_SCR_07_0_PR6_RANGE                       22:22
+#define GPIO_K_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_K_SCR_07_0_PR6_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR5_SHIFT)
+#define GPIO_K_SCR_07_0_PR5_RANGE                       21:21
+#define GPIO_K_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_K_SCR_07_0_PR5_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR4_SHIFT)
+#define GPIO_K_SCR_07_0_PR4_RANGE                       20:20
+#define GPIO_K_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_K_SCR_07_0_PR4_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR3_SHIFT)
+#define GPIO_K_SCR_07_0_PR3_RANGE                       19:19
+#define GPIO_K_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_K_SCR_07_0_PR3_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR2_SHIFT)
+#define GPIO_K_SCR_07_0_PR2_RANGE                       18:18
+#define GPIO_K_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_K_SCR_07_0_PR2_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR1_SHIFT)
+#define GPIO_K_SCR_07_0_PR1_RANGE                       17:17
+#define GPIO_K_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_K_SCR_07_0_PR1_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_PR0_SHIFT)
+#define GPIO_K_SCR_07_0_PR0_RANGE                       16:16
+#define GPIO_K_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_K_SCR_07_0_PR0_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G7W_SHIFT)
+#define GPIO_K_SCR_07_0_G7W_RANGE                       15:15
+#define GPIO_K_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_K_SCR_07_0_G7W_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G6W_SHIFT)
+#define GPIO_K_SCR_07_0_G6W_RANGE                       14:14
+#define GPIO_K_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_K_SCR_07_0_G6W_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G5W_SHIFT)
+#define GPIO_K_SCR_07_0_G5W_RANGE                       13:13
+#define GPIO_K_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_K_SCR_07_0_G5W_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G4W_SHIFT)
+#define GPIO_K_SCR_07_0_G4W_RANGE                       12:12
+#define GPIO_K_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_K_SCR_07_0_G4W_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G3W_SHIFT)
+#define GPIO_K_SCR_07_0_G3W_RANGE                       11:11
+#define GPIO_K_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_K_SCR_07_0_G3W_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G2W_SHIFT)
+#define GPIO_K_SCR_07_0_G2W_RANGE                       10:10
+#define GPIO_K_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_K_SCR_07_0_G2W_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G1W_SHIFT)
+#define GPIO_K_SCR_07_0_G1W_RANGE                       9:9
+#define GPIO_K_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_K_SCR_07_0_G1W_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G0W_SHIFT)
+#define GPIO_K_SCR_07_0_G0W_RANGE                       8:8
+#define GPIO_K_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_K_SCR_07_0_G0W_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G7R_SHIFT)
+#define GPIO_K_SCR_07_0_G7R_RANGE                       7:7
+#define GPIO_K_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_K_SCR_07_0_G7R_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G6R_SHIFT)
+#define GPIO_K_SCR_07_0_G6R_RANGE                       6:6
+#define GPIO_K_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_K_SCR_07_0_G6R_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G5R_SHIFT)
+#define GPIO_K_SCR_07_0_G5R_RANGE                       5:5
+#define GPIO_K_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_SCR_07_0_G5R_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G4R_SHIFT)
+#define GPIO_K_SCR_07_0_G4R_RANGE                       4:4
+#define GPIO_K_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_K_SCR_07_0_G4R_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G3R_SHIFT)
+#define GPIO_K_SCR_07_0_G3R_RANGE                       3:3
+#define GPIO_K_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_K_SCR_07_0_G3R_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G2R_SHIFT)
+#define GPIO_K_SCR_07_0_G2R_RANGE                       2:2
+#define GPIO_K_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_K_SCR_07_0_G2R_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G1R_SHIFT)
+#define GPIO_K_SCR_07_0_G1R_RANGE                       1:1
+#define GPIO_K_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_K_SCR_07_0_G1R_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_K_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_SCR_07_0_G0R_SHIFT)
+#define GPIO_K_SCR_07_0_G0R_RANGE                       0:0
+#define GPIO_K_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_SCR_07_0_G0R_WOFFSET                     0x0
+#define GPIO_K_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_K_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_VM_00_0
+#define GPIO_L_VM_00_0                  MK_ADDR_CONST(0x3040)
+#define GPIO_L_VM_00_0_SECURE                   0x0
+#define GPIO_L_VM_00_0_DUAL                     0x0
+#define GPIO_L_VM_00_0_SCR                      GPIO_CTL3_VM_SCR_0
+#define GPIO_L_VM_00_0_SCRREG                   GPIO_CTL3_VM_SCR_0
+#define GPIO_L_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_L_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_L_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_L_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_L_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_L_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_L_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM1_SHIFT)
+#define GPIO_L_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_L_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_L_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_L_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_L_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_L_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM2_SHIFT)
+#define GPIO_L_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_L_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_L_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_L_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_L_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_L_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM3_SHIFT)
+#define GPIO_L_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_L_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_L_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_L_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_L_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_L_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM4_SHIFT)
+#define GPIO_L_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_L_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_L_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_L_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_L_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_L_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM5_SHIFT)
+#define GPIO_L_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_L_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_L_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_L_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_L_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_L_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM6_SHIFT)
+#define GPIO_L_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_L_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_L_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_L_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_L_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_L_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM7_SHIFT)
+#define GPIO_L_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_L_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_L_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_L_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_L_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_L_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_00_0_VM8_SHIFT)
+#define GPIO_L_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_L_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_L_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_L_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_L_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_SCR_00_0
+#define GPIO_L_SCR_00_0                 MK_ADDR_CONST(0x3044)
+#define GPIO_L_SCR_00_0_SECURE                  0x0
+#define GPIO_L_SCR_00_0_DUAL                    0x0
+#define GPIO_L_SCR_00_0_SCR                     0
+#define GPIO_L_SCR_00_0_SCRREG                  0
+#define GPIO_L_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_L_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_L_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_L_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_L_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_L_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_L_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_L_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_L_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_L_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_L_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_L_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_L_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_L_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_L_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_L_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_L_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_L_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_L_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_L_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_L_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_L_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_L_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_L_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_L_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_L_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_L_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_L_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_L_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_L_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_L_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_L_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR7_SHIFT)
+#define GPIO_L_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_L_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_L_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_L_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_L_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR6_SHIFT)
+#define GPIO_L_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_L_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_L_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_L_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_L_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR5_SHIFT)
+#define GPIO_L_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_L_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_L_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_L_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_L_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR4_SHIFT)
+#define GPIO_L_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_L_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_L_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_L_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_L_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR3_SHIFT)
+#define GPIO_L_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_L_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_L_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_L_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_L_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR2_SHIFT)
+#define GPIO_L_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_L_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_L_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_L_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_L_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR1_SHIFT)
+#define GPIO_L_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_L_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_L_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_L_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_L_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_PR0_SHIFT)
+#define GPIO_L_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_L_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_L_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_L_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_L_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G7W_SHIFT)
+#define GPIO_L_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_L_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_L_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_L_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_L_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G6W_SHIFT)
+#define GPIO_L_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_L_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_L_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_L_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_L_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G5W_SHIFT)
+#define GPIO_L_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_L_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_L_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_L_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_L_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G4W_SHIFT)
+#define GPIO_L_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_L_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_L_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_L_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_L_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G3W_SHIFT)
+#define GPIO_L_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_L_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_L_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_L_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_L_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G2W_SHIFT)
+#define GPIO_L_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_L_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_L_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_L_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_L_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G1W_SHIFT)
+#define GPIO_L_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_L_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_L_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_L_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_L_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G0W_SHIFT)
+#define GPIO_L_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_L_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_L_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_L_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_L_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G7R_SHIFT)
+#define GPIO_L_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_L_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_L_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_L_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_L_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G6R_SHIFT)
+#define GPIO_L_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_L_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_L_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_L_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_L_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G5R_SHIFT)
+#define GPIO_L_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_L_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_L_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_L_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_L_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G4R_SHIFT)
+#define GPIO_L_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_L_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_L_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_L_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_L_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G3R_SHIFT)
+#define GPIO_L_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_L_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_L_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_L_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_L_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G2R_SHIFT)
+#define GPIO_L_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_L_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_L_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_L_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_L_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G1R_SHIFT)
+#define GPIO_L_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_L_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_L_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_L_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_L_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_00_0_G0R_SHIFT)
+#define GPIO_L_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_L_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_L_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_L_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_L_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_VM_01_0
+#define GPIO_L_VM_01_0                  MK_ADDR_CONST(0x3048)
+#define GPIO_L_VM_01_0_SECURE                   0x0
+#define GPIO_L_VM_01_0_DUAL                     0x0
+#define GPIO_L_VM_01_0_SCR                      GPIO_CTL3_VM_SCR_0
+#define GPIO_L_VM_01_0_SCRREG                   GPIO_CTL3_VM_SCR_0
+#define GPIO_L_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_L_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_L_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_L_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_L_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_L_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_L_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM1_SHIFT)
+#define GPIO_L_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_L_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_L_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_L_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_L_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_L_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM2_SHIFT)
+#define GPIO_L_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_L_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_L_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_L_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_L_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_L_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM3_SHIFT)
+#define GPIO_L_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_L_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_L_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_L_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_L_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_L_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM4_SHIFT)
+#define GPIO_L_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_L_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_L_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_L_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_L_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_L_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM5_SHIFT)
+#define GPIO_L_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_L_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_L_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_L_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_L_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_L_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM6_SHIFT)
+#define GPIO_L_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_L_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_L_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_L_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_L_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_L_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM7_SHIFT)
+#define GPIO_L_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_L_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_L_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_L_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_L_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_L_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_01_0_VM8_SHIFT)
+#define GPIO_L_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_L_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_L_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_L_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_L_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_SCR_01_0
+#define GPIO_L_SCR_01_0                 MK_ADDR_CONST(0x304c)
+#define GPIO_L_SCR_01_0_SECURE                  0x0
+#define GPIO_L_SCR_01_0_DUAL                    0x0
+#define GPIO_L_SCR_01_0_SCR                     0
+#define GPIO_L_SCR_01_0_SCRREG                  0
+#define GPIO_L_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_L_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_L_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_L_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_L_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_L_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_L_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_L_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_L_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_L_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_L_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_L_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_L_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_L_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_L_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_L_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_L_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_L_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_L_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_L_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_L_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_L_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_L_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_L_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_L_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_L_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_L_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_L_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_L_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_L_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_L_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_L_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR7_SHIFT)
+#define GPIO_L_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_L_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_L_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_L_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_L_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR6_SHIFT)
+#define GPIO_L_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_L_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_L_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_L_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_L_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR5_SHIFT)
+#define GPIO_L_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_L_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_L_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_L_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_L_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR4_SHIFT)
+#define GPIO_L_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_L_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_L_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_L_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_L_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR3_SHIFT)
+#define GPIO_L_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_L_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_L_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_L_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_L_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR2_SHIFT)
+#define GPIO_L_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_L_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_L_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_L_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_L_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR1_SHIFT)
+#define GPIO_L_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_L_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_L_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_L_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_L_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_PR0_SHIFT)
+#define GPIO_L_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_L_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_L_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_L_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_L_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G7W_SHIFT)
+#define GPIO_L_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_L_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_L_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_L_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_L_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G6W_SHIFT)
+#define GPIO_L_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_L_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_L_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_L_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_L_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G5W_SHIFT)
+#define GPIO_L_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_L_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_L_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_L_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_L_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G4W_SHIFT)
+#define GPIO_L_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_L_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_L_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_L_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_L_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G3W_SHIFT)
+#define GPIO_L_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_L_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_L_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_L_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_L_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G2W_SHIFT)
+#define GPIO_L_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_L_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_L_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_L_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_L_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G1W_SHIFT)
+#define GPIO_L_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_L_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_L_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_L_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_L_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G0W_SHIFT)
+#define GPIO_L_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_L_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_L_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_L_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_L_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G7R_SHIFT)
+#define GPIO_L_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_L_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_L_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_L_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_L_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G6R_SHIFT)
+#define GPIO_L_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_L_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_L_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_L_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_L_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G5R_SHIFT)
+#define GPIO_L_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_L_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_L_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_L_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_L_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G4R_SHIFT)
+#define GPIO_L_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_L_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_L_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_L_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_L_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G3R_SHIFT)
+#define GPIO_L_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_L_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_L_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_L_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_L_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G2R_SHIFT)
+#define GPIO_L_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_L_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_L_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_L_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_L_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G1R_SHIFT)
+#define GPIO_L_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_L_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_L_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_L_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_L_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_01_0_G0R_SHIFT)
+#define GPIO_L_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_L_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_L_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_L_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_L_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_VM_02_0
+#define GPIO_L_VM_02_0                  MK_ADDR_CONST(0x3050)
+#define GPIO_L_VM_02_0_SECURE                   0x0
+#define GPIO_L_VM_02_0_DUAL                     0x0
+#define GPIO_L_VM_02_0_SCR                      GPIO_CTL3_VM_SCR_0
+#define GPIO_L_VM_02_0_SCRREG                   GPIO_CTL3_VM_SCR_0
+#define GPIO_L_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_L_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_L_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_L_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_L_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_L_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_L_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM1_SHIFT)
+#define GPIO_L_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_L_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_L_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_L_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_L_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_L_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM2_SHIFT)
+#define GPIO_L_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_L_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_L_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_L_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_L_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_L_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM3_SHIFT)
+#define GPIO_L_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_L_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_L_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_L_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_L_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_L_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM4_SHIFT)
+#define GPIO_L_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_L_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_L_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_L_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_L_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_L_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM5_SHIFT)
+#define GPIO_L_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_L_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_L_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_L_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_L_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_L_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM6_SHIFT)
+#define GPIO_L_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_L_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_L_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_L_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_L_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_L_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM7_SHIFT)
+#define GPIO_L_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_L_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_L_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_L_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_L_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_L_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_02_0_VM8_SHIFT)
+#define GPIO_L_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_L_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_L_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_L_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_L_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_SCR_02_0
+#define GPIO_L_SCR_02_0                 MK_ADDR_CONST(0x3054)
+#define GPIO_L_SCR_02_0_SECURE                  0x0
+#define GPIO_L_SCR_02_0_DUAL                    0x0
+#define GPIO_L_SCR_02_0_SCR                     0
+#define GPIO_L_SCR_02_0_SCRREG                  0
+#define GPIO_L_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_L_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_L_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_L_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_L_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_L_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_L_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_L_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_L_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_L_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_L_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_L_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_L_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_L_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_L_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_L_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_L_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_L_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_L_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_L_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_L_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_L_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_L_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_L_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_L_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_L_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_L_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_L_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_L_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_L_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_L_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_L_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR7_SHIFT)
+#define GPIO_L_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_L_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_L_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_L_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_L_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR6_SHIFT)
+#define GPIO_L_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_L_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_L_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_L_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_L_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR5_SHIFT)
+#define GPIO_L_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_L_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_L_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_L_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_L_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR4_SHIFT)
+#define GPIO_L_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_L_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_L_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_L_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_L_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR3_SHIFT)
+#define GPIO_L_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_L_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_L_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_L_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_L_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR2_SHIFT)
+#define GPIO_L_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_L_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_L_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_L_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_L_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR1_SHIFT)
+#define GPIO_L_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_L_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_L_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_L_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_L_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_PR0_SHIFT)
+#define GPIO_L_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_L_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_L_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_L_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_L_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G7W_SHIFT)
+#define GPIO_L_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_L_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_L_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_L_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_L_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G6W_SHIFT)
+#define GPIO_L_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_L_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_L_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_L_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_L_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G5W_SHIFT)
+#define GPIO_L_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_L_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_L_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_L_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_L_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G4W_SHIFT)
+#define GPIO_L_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_L_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_L_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_L_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_L_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G3W_SHIFT)
+#define GPIO_L_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_L_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_L_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_L_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_L_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G2W_SHIFT)
+#define GPIO_L_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_L_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_L_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_L_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_L_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G1W_SHIFT)
+#define GPIO_L_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_L_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_L_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_L_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_L_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G0W_SHIFT)
+#define GPIO_L_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_L_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_L_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_L_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_L_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G7R_SHIFT)
+#define GPIO_L_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_L_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_L_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_L_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_L_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G6R_SHIFT)
+#define GPIO_L_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_L_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_L_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_L_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_L_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G5R_SHIFT)
+#define GPIO_L_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_L_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_L_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_L_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_L_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G4R_SHIFT)
+#define GPIO_L_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_L_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_L_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_L_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_L_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G3R_SHIFT)
+#define GPIO_L_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_L_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_L_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_L_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_L_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G2R_SHIFT)
+#define GPIO_L_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_L_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_L_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_L_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_L_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G1R_SHIFT)
+#define GPIO_L_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_L_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_L_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_L_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_L_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_02_0_G0R_SHIFT)
+#define GPIO_L_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_L_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_L_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_L_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_L_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_VM_03_0
+#define GPIO_L_VM_03_0                  MK_ADDR_CONST(0x3058)
+#define GPIO_L_VM_03_0_SECURE                   0x0
+#define GPIO_L_VM_03_0_DUAL                     0x0
+#define GPIO_L_VM_03_0_SCR                      GPIO_CTL3_VM_SCR_0
+#define GPIO_L_VM_03_0_SCRREG                   GPIO_CTL3_VM_SCR_0
+#define GPIO_L_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_L_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_L_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_L_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_L_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_L_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_L_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM1_SHIFT)
+#define GPIO_L_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_L_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_L_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_L_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_L_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_L_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM2_SHIFT)
+#define GPIO_L_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_L_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_L_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_L_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_L_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_L_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM3_SHIFT)
+#define GPIO_L_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_L_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_L_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_L_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_L_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_L_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM4_SHIFT)
+#define GPIO_L_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_L_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_L_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_L_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_L_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_L_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM5_SHIFT)
+#define GPIO_L_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_L_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_L_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_L_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_L_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_L_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM6_SHIFT)
+#define GPIO_L_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_L_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_L_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_L_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_L_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_L_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM7_SHIFT)
+#define GPIO_L_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_L_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_L_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_L_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_L_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_L_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_L_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_L_VM_03_0_VM8_SHIFT)
+#define GPIO_L_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_L_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_L_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_L_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_L_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_L_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_L_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_SCR_03_0
+#define GPIO_L_SCR_03_0                 MK_ADDR_CONST(0x305c)
+#define GPIO_L_SCR_03_0_SECURE                  0x0
+#define GPIO_L_SCR_03_0_DUAL                    0x0
+#define GPIO_L_SCR_03_0_SCR                     0
+#define GPIO_L_SCR_03_0_SCRREG                  0
+#define GPIO_L_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_L_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_L_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_L_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_L_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_L_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_L_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_L_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_L_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_L_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_L_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_L_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_L_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_L_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_L_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_L_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_L_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_L_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_L_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_L_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_L_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_L_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_L_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_L_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_L_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_L_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_L_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_L_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_L_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_L_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_L_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_L_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR7_SHIFT)
+#define GPIO_L_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_L_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_L_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_L_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_L_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR6_SHIFT)
+#define GPIO_L_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_L_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_L_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_L_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_L_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR5_SHIFT)
+#define GPIO_L_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_L_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_L_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_L_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_L_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR4_SHIFT)
+#define GPIO_L_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_L_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_L_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_L_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_L_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR3_SHIFT)
+#define GPIO_L_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_L_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_L_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_L_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_L_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR2_SHIFT)
+#define GPIO_L_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_L_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_L_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_L_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_L_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR1_SHIFT)
+#define GPIO_L_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_L_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_L_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_L_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_L_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_PR0_SHIFT)
+#define GPIO_L_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_L_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_L_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_L_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_L_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G7W_SHIFT)
+#define GPIO_L_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_L_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_L_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_L_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_L_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G6W_SHIFT)
+#define GPIO_L_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_L_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_L_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_L_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_L_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G5W_SHIFT)
+#define GPIO_L_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_L_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_L_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_L_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_L_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G4W_SHIFT)
+#define GPIO_L_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_L_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_L_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_L_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_L_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G3W_SHIFT)
+#define GPIO_L_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_L_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_L_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_L_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_L_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G2W_SHIFT)
+#define GPIO_L_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_L_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_L_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_L_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_L_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G1W_SHIFT)
+#define GPIO_L_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_L_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_L_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_L_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_L_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G0W_SHIFT)
+#define GPIO_L_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_L_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_L_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_L_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_L_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G7R_SHIFT)
+#define GPIO_L_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_L_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_L_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_L_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_L_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G6R_SHIFT)
+#define GPIO_L_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_L_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_L_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_L_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_L_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G5R_SHIFT)
+#define GPIO_L_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_L_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_L_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_L_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_L_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G4R_SHIFT)
+#define GPIO_L_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_L_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_L_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_L_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_L_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G3R_SHIFT)
+#define GPIO_L_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_L_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_L_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_L_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_L_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G2R_SHIFT)
+#define GPIO_L_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_L_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_L_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_L_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_L_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G1R_SHIFT)
+#define GPIO_L_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_L_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_L_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_L_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_L_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_L_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_SCR_03_0_G0R_SHIFT)
+#define GPIO_L_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_L_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_L_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_L_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_L_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_L_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x3060
+
+// Reserved address 0x3064
+
+// Reserved address 0x3068
+
+// Reserved address 0x306c
+
+// Reserved address 0x3070
+
+// Reserved address 0x3074
+
+// Reserved address 0x3078
+
+// Reserved address 0x307c
+
+// Register GPIO_AG_VM_00_0
+#define GPIO_AG_VM_00_0                 MK_ADDR_CONST(0x3080)
+#define GPIO_AG_VM_00_0_SECURE                  0x0
+#define GPIO_AG_VM_00_0_DUAL                    0x0
+#define GPIO_AG_VM_00_0_SCR                     GPIO_CTL3_VM_SCR_0
+#define GPIO_AG_VM_00_0_SCRREG                  GPIO_CTL3_VM_SCR_0
+#define GPIO_AG_VM_00_0_WORD_COUNT                      0x1
+#define GPIO_AG_VM_00_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_00_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_00_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_00_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AG_VM_00_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_00_0_VM1_SHIFT)
+#define GPIO_AG_VM_00_0_VM1_RANGE                       1:0
+#define GPIO_AG_VM_00_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AG_VM_00_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AG_VM_00_0_VM1_WOFFSET                     0x0
+#define GPIO_AG_VM_00_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_00_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_00_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_00_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AG_VM_00_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_00_0_VM2_SHIFT)
+#define GPIO_AG_VM_00_0_VM2_RANGE                       3:2
+#define GPIO_AG_VM_00_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AG_VM_00_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AG_VM_00_0_VM2_WOFFSET                     0x0
+#define GPIO_AG_VM_00_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_00_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_00_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_00_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AG_VM_00_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_00_0_VM3_SHIFT)
+#define GPIO_AG_VM_00_0_VM3_RANGE                       5:4
+#define GPIO_AG_VM_00_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AG_VM_00_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AG_VM_00_0_VM3_WOFFSET                     0x0
+#define GPIO_AG_VM_00_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_00_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_00_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_00_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AG_VM_00_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_00_0_VM4_SHIFT)
+#define GPIO_AG_VM_00_0_VM4_RANGE                       7:6
+#define GPIO_AG_VM_00_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AG_VM_00_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AG_VM_00_0_VM4_WOFFSET                     0x0
+#define GPIO_AG_VM_00_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_00_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_00_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_00_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AG_VM_00_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_00_0_VM5_SHIFT)
+#define GPIO_AG_VM_00_0_VM5_RANGE                       9:8
+#define GPIO_AG_VM_00_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AG_VM_00_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AG_VM_00_0_VM5_WOFFSET                     0x0
+#define GPIO_AG_VM_00_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_00_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_00_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_00_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AG_VM_00_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_00_0_VM6_SHIFT)
+#define GPIO_AG_VM_00_0_VM6_RANGE                       11:10
+#define GPIO_AG_VM_00_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AG_VM_00_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AG_VM_00_0_VM6_WOFFSET                     0x0
+#define GPIO_AG_VM_00_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_00_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_00_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_00_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AG_VM_00_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_00_0_VM7_SHIFT)
+#define GPIO_AG_VM_00_0_VM7_RANGE                       13:12
+#define GPIO_AG_VM_00_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AG_VM_00_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AG_VM_00_0_VM7_WOFFSET                     0x0
+#define GPIO_AG_VM_00_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_00_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_00_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_00_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AG_VM_00_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_00_0_VM8_SHIFT)
+#define GPIO_AG_VM_00_0_VM8_RANGE                       15:14
+#define GPIO_AG_VM_00_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AG_VM_00_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AG_VM_00_0_VM8_WOFFSET                     0x0
+#define GPIO_AG_VM_00_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_00_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_00_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_00_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_SCR_00_0
+#define GPIO_AG_SCR_00_0                        MK_ADDR_CONST(0x3084)
+#define GPIO_AG_SCR_00_0_SECURE                         0x0
+#define GPIO_AG_SCR_00_0_DUAL                   0x0
+#define GPIO_AG_SCR_00_0_SCR                    0
+#define GPIO_AG_SCR_00_0_SCRREG                         0
+#define GPIO_AG_SCR_00_0_WORD_COUNT                     0x1
+#define GPIO_AG_SCR_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_00_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_00_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_00_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_AG_SCR_00_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AG_SCR_00_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_00_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_00_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AG_SCR_00_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_00_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_AG_SCR_00_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AG_SCR_00_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_00_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_00_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AG_SCR_00_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_00_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_AG_SCR_00_0_SEC_REN_RANGE                  27:27
+#define GPIO_AG_SCR_00_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_00_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_00_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AG_SCR_00_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AG_SCR_00_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AG_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_AG_SCR_00_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AG_SCR_00_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AG_SCR_00_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AG_SCR_00_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AG_SCR_00_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AG_SCR_00_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_00_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_PR7_SHIFT)
+#define GPIO_AG_SCR_00_0_PR7_RANGE                      23:23
+#define GPIO_AG_SCR_00_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_00_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_00_0_PR7_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_00_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_PR6_SHIFT)
+#define GPIO_AG_SCR_00_0_PR6_RANGE                      22:22
+#define GPIO_AG_SCR_00_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_00_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_00_0_PR6_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_00_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_PR5_SHIFT)
+#define GPIO_AG_SCR_00_0_PR5_RANGE                      21:21
+#define GPIO_AG_SCR_00_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_00_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_00_0_PR5_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_00_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_PR4_SHIFT)
+#define GPIO_AG_SCR_00_0_PR4_RANGE                      20:20
+#define GPIO_AG_SCR_00_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_00_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_00_0_PR4_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_00_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_PR3_SHIFT)
+#define GPIO_AG_SCR_00_0_PR3_RANGE                      19:19
+#define GPIO_AG_SCR_00_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_00_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_00_0_PR3_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_00_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_PR2_SHIFT)
+#define GPIO_AG_SCR_00_0_PR2_RANGE                      18:18
+#define GPIO_AG_SCR_00_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_00_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_00_0_PR2_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_00_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_PR1_SHIFT)
+#define GPIO_AG_SCR_00_0_PR1_RANGE                      17:17
+#define GPIO_AG_SCR_00_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_00_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_00_0_PR1_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_00_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_PR0_SHIFT)
+#define GPIO_AG_SCR_00_0_PR0_RANGE                      16:16
+#define GPIO_AG_SCR_00_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_00_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_00_0_PR0_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_00_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G7W_SHIFT)
+#define GPIO_AG_SCR_00_0_G7W_RANGE                      15:15
+#define GPIO_AG_SCR_00_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_00_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_00_0_G7W_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_00_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G6W_SHIFT)
+#define GPIO_AG_SCR_00_0_G6W_RANGE                      14:14
+#define GPIO_AG_SCR_00_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_00_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_00_0_G6W_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_00_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G5W_SHIFT)
+#define GPIO_AG_SCR_00_0_G5W_RANGE                      13:13
+#define GPIO_AG_SCR_00_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_00_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_00_0_G5W_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_00_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G4W_SHIFT)
+#define GPIO_AG_SCR_00_0_G4W_RANGE                      12:12
+#define GPIO_AG_SCR_00_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_00_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_00_0_G4W_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_00_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G3W_SHIFT)
+#define GPIO_AG_SCR_00_0_G3W_RANGE                      11:11
+#define GPIO_AG_SCR_00_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_00_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_00_0_G3W_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_00_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G2W_SHIFT)
+#define GPIO_AG_SCR_00_0_G2W_RANGE                      10:10
+#define GPIO_AG_SCR_00_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_00_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_00_0_G2W_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_00_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G1W_SHIFT)
+#define GPIO_AG_SCR_00_0_G1W_RANGE                      9:9
+#define GPIO_AG_SCR_00_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_00_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_00_0_G1W_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_00_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G0W_SHIFT)
+#define GPIO_AG_SCR_00_0_G0W_RANGE                      8:8
+#define GPIO_AG_SCR_00_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_00_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_00_0_G0W_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_00_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G7R_SHIFT)
+#define GPIO_AG_SCR_00_0_G7R_RANGE                      7:7
+#define GPIO_AG_SCR_00_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_00_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_00_0_G7R_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_00_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G6R_SHIFT)
+#define GPIO_AG_SCR_00_0_G6R_RANGE                      6:6
+#define GPIO_AG_SCR_00_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_00_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_00_0_G6R_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_00_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G5R_SHIFT)
+#define GPIO_AG_SCR_00_0_G5R_RANGE                      5:5
+#define GPIO_AG_SCR_00_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_00_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_00_0_G5R_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_00_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G4R_SHIFT)
+#define GPIO_AG_SCR_00_0_G4R_RANGE                      4:4
+#define GPIO_AG_SCR_00_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_00_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_00_0_G4R_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_00_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G3R_SHIFT)
+#define GPIO_AG_SCR_00_0_G3R_RANGE                      3:3
+#define GPIO_AG_SCR_00_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_00_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_00_0_G3R_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_00_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G2R_SHIFT)
+#define GPIO_AG_SCR_00_0_G2R_RANGE                      2:2
+#define GPIO_AG_SCR_00_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_00_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_00_0_G2R_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_00_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G1R_SHIFT)
+#define GPIO_AG_SCR_00_0_G1R_RANGE                      1:1
+#define GPIO_AG_SCR_00_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_00_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_00_0_G1R_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_00_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_00_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_00_0_G0R_SHIFT)
+#define GPIO_AG_SCR_00_0_G0R_RANGE                      0:0
+#define GPIO_AG_SCR_00_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_00_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_00_0_G0R_WOFFSET                    0x0
+#define GPIO_AG_SCR_00_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_00_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_00_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_VM_01_0
+#define GPIO_AG_VM_01_0                 MK_ADDR_CONST(0x3088)
+#define GPIO_AG_VM_01_0_SECURE                  0x0
+#define GPIO_AG_VM_01_0_DUAL                    0x0
+#define GPIO_AG_VM_01_0_SCR                     GPIO_CTL3_VM_SCR_0
+#define GPIO_AG_VM_01_0_SCRREG                  GPIO_CTL3_VM_SCR_0
+#define GPIO_AG_VM_01_0_WORD_COUNT                      0x1
+#define GPIO_AG_VM_01_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_01_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_01_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_01_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AG_VM_01_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_01_0_VM1_SHIFT)
+#define GPIO_AG_VM_01_0_VM1_RANGE                       1:0
+#define GPIO_AG_VM_01_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AG_VM_01_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AG_VM_01_0_VM1_WOFFSET                     0x0
+#define GPIO_AG_VM_01_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_01_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_01_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_01_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AG_VM_01_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_01_0_VM2_SHIFT)
+#define GPIO_AG_VM_01_0_VM2_RANGE                       3:2
+#define GPIO_AG_VM_01_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AG_VM_01_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AG_VM_01_0_VM2_WOFFSET                     0x0
+#define GPIO_AG_VM_01_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_01_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_01_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_01_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AG_VM_01_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_01_0_VM3_SHIFT)
+#define GPIO_AG_VM_01_0_VM3_RANGE                       5:4
+#define GPIO_AG_VM_01_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AG_VM_01_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AG_VM_01_0_VM3_WOFFSET                     0x0
+#define GPIO_AG_VM_01_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_01_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_01_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_01_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AG_VM_01_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_01_0_VM4_SHIFT)
+#define GPIO_AG_VM_01_0_VM4_RANGE                       7:6
+#define GPIO_AG_VM_01_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AG_VM_01_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AG_VM_01_0_VM4_WOFFSET                     0x0
+#define GPIO_AG_VM_01_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_01_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_01_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_01_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AG_VM_01_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_01_0_VM5_SHIFT)
+#define GPIO_AG_VM_01_0_VM5_RANGE                       9:8
+#define GPIO_AG_VM_01_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AG_VM_01_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AG_VM_01_0_VM5_WOFFSET                     0x0
+#define GPIO_AG_VM_01_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_01_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_01_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_01_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AG_VM_01_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_01_0_VM6_SHIFT)
+#define GPIO_AG_VM_01_0_VM6_RANGE                       11:10
+#define GPIO_AG_VM_01_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AG_VM_01_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AG_VM_01_0_VM6_WOFFSET                     0x0
+#define GPIO_AG_VM_01_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_01_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_01_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_01_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AG_VM_01_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_01_0_VM7_SHIFT)
+#define GPIO_AG_VM_01_0_VM7_RANGE                       13:12
+#define GPIO_AG_VM_01_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AG_VM_01_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AG_VM_01_0_VM7_WOFFSET                     0x0
+#define GPIO_AG_VM_01_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_01_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_01_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_01_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AG_VM_01_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_01_0_VM8_SHIFT)
+#define GPIO_AG_VM_01_0_VM8_RANGE                       15:14
+#define GPIO_AG_VM_01_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AG_VM_01_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AG_VM_01_0_VM8_WOFFSET                     0x0
+#define GPIO_AG_VM_01_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_01_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_01_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_01_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_SCR_01_0
+#define GPIO_AG_SCR_01_0                        MK_ADDR_CONST(0x308c)
+#define GPIO_AG_SCR_01_0_SECURE                         0x0
+#define GPIO_AG_SCR_01_0_DUAL                   0x0
+#define GPIO_AG_SCR_01_0_SCR                    0
+#define GPIO_AG_SCR_01_0_SCRREG                         0
+#define GPIO_AG_SCR_01_0_WORD_COUNT                     0x1
+#define GPIO_AG_SCR_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_01_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_01_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_01_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_AG_SCR_01_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AG_SCR_01_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_01_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_01_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AG_SCR_01_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_01_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_AG_SCR_01_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AG_SCR_01_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_01_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_01_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AG_SCR_01_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_01_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_AG_SCR_01_0_SEC_REN_RANGE                  27:27
+#define GPIO_AG_SCR_01_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_01_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_01_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AG_SCR_01_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AG_SCR_01_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AG_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_AG_SCR_01_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AG_SCR_01_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AG_SCR_01_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AG_SCR_01_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AG_SCR_01_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AG_SCR_01_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_01_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_PR7_SHIFT)
+#define GPIO_AG_SCR_01_0_PR7_RANGE                      23:23
+#define GPIO_AG_SCR_01_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_01_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_01_0_PR7_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_01_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_PR6_SHIFT)
+#define GPIO_AG_SCR_01_0_PR6_RANGE                      22:22
+#define GPIO_AG_SCR_01_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_01_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_01_0_PR6_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_01_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_PR5_SHIFT)
+#define GPIO_AG_SCR_01_0_PR5_RANGE                      21:21
+#define GPIO_AG_SCR_01_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_01_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_01_0_PR5_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_01_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_PR4_SHIFT)
+#define GPIO_AG_SCR_01_0_PR4_RANGE                      20:20
+#define GPIO_AG_SCR_01_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_01_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_01_0_PR4_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_01_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_PR3_SHIFT)
+#define GPIO_AG_SCR_01_0_PR3_RANGE                      19:19
+#define GPIO_AG_SCR_01_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_01_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_01_0_PR3_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_01_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_PR2_SHIFT)
+#define GPIO_AG_SCR_01_0_PR2_RANGE                      18:18
+#define GPIO_AG_SCR_01_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_01_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_01_0_PR2_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_01_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_PR1_SHIFT)
+#define GPIO_AG_SCR_01_0_PR1_RANGE                      17:17
+#define GPIO_AG_SCR_01_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_01_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_01_0_PR1_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_01_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_PR0_SHIFT)
+#define GPIO_AG_SCR_01_0_PR0_RANGE                      16:16
+#define GPIO_AG_SCR_01_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_01_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_01_0_PR0_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_01_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G7W_SHIFT)
+#define GPIO_AG_SCR_01_0_G7W_RANGE                      15:15
+#define GPIO_AG_SCR_01_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_01_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_01_0_G7W_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_01_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G6W_SHIFT)
+#define GPIO_AG_SCR_01_0_G6W_RANGE                      14:14
+#define GPIO_AG_SCR_01_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_01_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_01_0_G6W_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_01_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G5W_SHIFT)
+#define GPIO_AG_SCR_01_0_G5W_RANGE                      13:13
+#define GPIO_AG_SCR_01_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_01_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_01_0_G5W_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_01_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G4W_SHIFT)
+#define GPIO_AG_SCR_01_0_G4W_RANGE                      12:12
+#define GPIO_AG_SCR_01_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_01_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_01_0_G4W_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_01_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G3W_SHIFT)
+#define GPIO_AG_SCR_01_0_G3W_RANGE                      11:11
+#define GPIO_AG_SCR_01_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_01_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_01_0_G3W_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_01_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G2W_SHIFT)
+#define GPIO_AG_SCR_01_0_G2W_RANGE                      10:10
+#define GPIO_AG_SCR_01_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_01_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_01_0_G2W_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_01_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G1W_SHIFT)
+#define GPIO_AG_SCR_01_0_G1W_RANGE                      9:9
+#define GPIO_AG_SCR_01_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_01_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_01_0_G1W_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_01_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G0W_SHIFT)
+#define GPIO_AG_SCR_01_0_G0W_RANGE                      8:8
+#define GPIO_AG_SCR_01_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_01_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_01_0_G0W_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_01_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G7R_SHIFT)
+#define GPIO_AG_SCR_01_0_G7R_RANGE                      7:7
+#define GPIO_AG_SCR_01_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_01_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_01_0_G7R_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_01_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G6R_SHIFT)
+#define GPIO_AG_SCR_01_0_G6R_RANGE                      6:6
+#define GPIO_AG_SCR_01_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_01_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_01_0_G6R_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_01_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G5R_SHIFT)
+#define GPIO_AG_SCR_01_0_G5R_RANGE                      5:5
+#define GPIO_AG_SCR_01_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_01_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_01_0_G5R_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_01_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G4R_SHIFT)
+#define GPIO_AG_SCR_01_0_G4R_RANGE                      4:4
+#define GPIO_AG_SCR_01_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_01_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_01_0_G4R_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_01_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G3R_SHIFT)
+#define GPIO_AG_SCR_01_0_G3R_RANGE                      3:3
+#define GPIO_AG_SCR_01_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_01_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_01_0_G3R_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_01_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G2R_SHIFT)
+#define GPIO_AG_SCR_01_0_G2R_RANGE                      2:2
+#define GPIO_AG_SCR_01_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_01_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_01_0_G2R_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_01_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G1R_SHIFT)
+#define GPIO_AG_SCR_01_0_G1R_RANGE                      1:1
+#define GPIO_AG_SCR_01_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_01_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_01_0_G1R_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_01_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_01_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_01_0_G0R_SHIFT)
+#define GPIO_AG_SCR_01_0_G0R_RANGE                      0:0
+#define GPIO_AG_SCR_01_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_01_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_01_0_G0R_WOFFSET                    0x0
+#define GPIO_AG_SCR_01_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_01_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_01_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_VM_02_0
+#define GPIO_AG_VM_02_0                 MK_ADDR_CONST(0x3090)
+#define GPIO_AG_VM_02_0_SECURE                  0x0
+#define GPIO_AG_VM_02_0_DUAL                    0x0
+#define GPIO_AG_VM_02_0_SCR                     GPIO_CTL3_VM_SCR_0
+#define GPIO_AG_VM_02_0_SCRREG                  GPIO_CTL3_VM_SCR_0
+#define GPIO_AG_VM_02_0_WORD_COUNT                      0x1
+#define GPIO_AG_VM_02_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_02_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_02_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_02_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AG_VM_02_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_02_0_VM1_SHIFT)
+#define GPIO_AG_VM_02_0_VM1_RANGE                       1:0
+#define GPIO_AG_VM_02_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AG_VM_02_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AG_VM_02_0_VM1_WOFFSET                     0x0
+#define GPIO_AG_VM_02_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_02_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_02_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_02_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AG_VM_02_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_02_0_VM2_SHIFT)
+#define GPIO_AG_VM_02_0_VM2_RANGE                       3:2
+#define GPIO_AG_VM_02_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AG_VM_02_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AG_VM_02_0_VM2_WOFFSET                     0x0
+#define GPIO_AG_VM_02_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_02_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_02_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_02_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AG_VM_02_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_02_0_VM3_SHIFT)
+#define GPIO_AG_VM_02_0_VM3_RANGE                       5:4
+#define GPIO_AG_VM_02_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AG_VM_02_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AG_VM_02_0_VM3_WOFFSET                     0x0
+#define GPIO_AG_VM_02_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_02_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_02_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_02_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AG_VM_02_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_02_0_VM4_SHIFT)
+#define GPIO_AG_VM_02_0_VM4_RANGE                       7:6
+#define GPIO_AG_VM_02_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AG_VM_02_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AG_VM_02_0_VM4_WOFFSET                     0x0
+#define GPIO_AG_VM_02_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_02_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_02_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_02_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AG_VM_02_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_02_0_VM5_SHIFT)
+#define GPIO_AG_VM_02_0_VM5_RANGE                       9:8
+#define GPIO_AG_VM_02_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AG_VM_02_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AG_VM_02_0_VM5_WOFFSET                     0x0
+#define GPIO_AG_VM_02_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_02_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_02_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_02_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AG_VM_02_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_02_0_VM6_SHIFT)
+#define GPIO_AG_VM_02_0_VM6_RANGE                       11:10
+#define GPIO_AG_VM_02_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AG_VM_02_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AG_VM_02_0_VM6_WOFFSET                     0x0
+#define GPIO_AG_VM_02_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_02_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_02_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_02_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AG_VM_02_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_02_0_VM7_SHIFT)
+#define GPIO_AG_VM_02_0_VM7_RANGE                       13:12
+#define GPIO_AG_VM_02_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AG_VM_02_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AG_VM_02_0_VM7_WOFFSET                     0x0
+#define GPIO_AG_VM_02_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_02_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_02_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_02_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AG_VM_02_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_02_0_VM8_SHIFT)
+#define GPIO_AG_VM_02_0_VM8_RANGE                       15:14
+#define GPIO_AG_VM_02_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AG_VM_02_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AG_VM_02_0_VM8_WOFFSET                     0x0
+#define GPIO_AG_VM_02_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_02_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_02_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_02_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_SCR_02_0
+#define GPIO_AG_SCR_02_0                        MK_ADDR_CONST(0x3094)
+#define GPIO_AG_SCR_02_0_SECURE                         0x0
+#define GPIO_AG_SCR_02_0_DUAL                   0x0
+#define GPIO_AG_SCR_02_0_SCR                    0
+#define GPIO_AG_SCR_02_0_SCRREG                         0
+#define GPIO_AG_SCR_02_0_WORD_COUNT                     0x1
+#define GPIO_AG_SCR_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_02_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_02_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_02_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_AG_SCR_02_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AG_SCR_02_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_02_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_02_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AG_SCR_02_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_02_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_AG_SCR_02_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AG_SCR_02_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_02_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_02_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AG_SCR_02_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_02_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_AG_SCR_02_0_SEC_REN_RANGE                  27:27
+#define GPIO_AG_SCR_02_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_02_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_02_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AG_SCR_02_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AG_SCR_02_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AG_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_AG_SCR_02_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AG_SCR_02_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AG_SCR_02_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AG_SCR_02_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AG_SCR_02_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AG_SCR_02_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_02_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_PR7_SHIFT)
+#define GPIO_AG_SCR_02_0_PR7_RANGE                      23:23
+#define GPIO_AG_SCR_02_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_02_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_02_0_PR7_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_02_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_PR6_SHIFT)
+#define GPIO_AG_SCR_02_0_PR6_RANGE                      22:22
+#define GPIO_AG_SCR_02_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_02_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_02_0_PR6_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_02_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_PR5_SHIFT)
+#define GPIO_AG_SCR_02_0_PR5_RANGE                      21:21
+#define GPIO_AG_SCR_02_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_02_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_02_0_PR5_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_02_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_PR4_SHIFT)
+#define GPIO_AG_SCR_02_0_PR4_RANGE                      20:20
+#define GPIO_AG_SCR_02_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_02_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_02_0_PR4_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_02_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_PR3_SHIFT)
+#define GPIO_AG_SCR_02_0_PR3_RANGE                      19:19
+#define GPIO_AG_SCR_02_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_02_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_02_0_PR3_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_02_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_PR2_SHIFT)
+#define GPIO_AG_SCR_02_0_PR2_RANGE                      18:18
+#define GPIO_AG_SCR_02_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_02_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_02_0_PR2_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_02_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_PR1_SHIFT)
+#define GPIO_AG_SCR_02_0_PR1_RANGE                      17:17
+#define GPIO_AG_SCR_02_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_02_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_02_0_PR1_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_02_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_PR0_SHIFT)
+#define GPIO_AG_SCR_02_0_PR0_RANGE                      16:16
+#define GPIO_AG_SCR_02_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_02_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_02_0_PR0_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_02_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G7W_SHIFT)
+#define GPIO_AG_SCR_02_0_G7W_RANGE                      15:15
+#define GPIO_AG_SCR_02_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_02_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_02_0_G7W_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_02_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G6W_SHIFT)
+#define GPIO_AG_SCR_02_0_G6W_RANGE                      14:14
+#define GPIO_AG_SCR_02_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_02_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_02_0_G6W_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_02_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G5W_SHIFT)
+#define GPIO_AG_SCR_02_0_G5W_RANGE                      13:13
+#define GPIO_AG_SCR_02_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_02_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_02_0_G5W_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_02_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G4W_SHIFT)
+#define GPIO_AG_SCR_02_0_G4W_RANGE                      12:12
+#define GPIO_AG_SCR_02_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_02_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_02_0_G4W_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_02_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G3W_SHIFT)
+#define GPIO_AG_SCR_02_0_G3W_RANGE                      11:11
+#define GPIO_AG_SCR_02_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_02_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_02_0_G3W_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_02_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G2W_SHIFT)
+#define GPIO_AG_SCR_02_0_G2W_RANGE                      10:10
+#define GPIO_AG_SCR_02_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_02_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_02_0_G2W_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_02_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G1W_SHIFT)
+#define GPIO_AG_SCR_02_0_G1W_RANGE                      9:9
+#define GPIO_AG_SCR_02_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_02_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_02_0_G1W_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_02_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G0W_SHIFT)
+#define GPIO_AG_SCR_02_0_G0W_RANGE                      8:8
+#define GPIO_AG_SCR_02_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_02_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_02_0_G0W_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_02_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G7R_SHIFT)
+#define GPIO_AG_SCR_02_0_G7R_RANGE                      7:7
+#define GPIO_AG_SCR_02_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_02_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_02_0_G7R_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_02_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G6R_SHIFT)
+#define GPIO_AG_SCR_02_0_G6R_RANGE                      6:6
+#define GPIO_AG_SCR_02_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_02_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_02_0_G6R_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_02_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G5R_SHIFT)
+#define GPIO_AG_SCR_02_0_G5R_RANGE                      5:5
+#define GPIO_AG_SCR_02_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_02_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_02_0_G5R_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_02_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G4R_SHIFT)
+#define GPIO_AG_SCR_02_0_G4R_RANGE                      4:4
+#define GPIO_AG_SCR_02_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_02_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_02_0_G4R_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_02_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G3R_SHIFT)
+#define GPIO_AG_SCR_02_0_G3R_RANGE                      3:3
+#define GPIO_AG_SCR_02_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_02_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_02_0_G3R_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_02_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G2R_SHIFT)
+#define GPIO_AG_SCR_02_0_G2R_RANGE                      2:2
+#define GPIO_AG_SCR_02_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_02_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_02_0_G2R_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_02_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G1R_SHIFT)
+#define GPIO_AG_SCR_02_0_G1R_RANGE                      1:1
+#define GPIO_AG_SCR_02_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_02_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_02_0_G1R_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_02_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_02_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_02_0_G0R_SHIFT)
+#define GPIO_AG_SCR_02_0_G0R_RANGE                      0:0
+#define GPIO_AG_SCR_02_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_02_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_02_0_G0R_WOFFSET                    0x0
+#define GPIO_AG_SCR_02_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_02_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_02_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_VM_03_0
+#define GPIO_AG_VM_03_0                 MK_ADDR_CONST(0x3098)
+#define GPIO_AG_VM_03_0_SECURE                  0x0
+#define GPIO_AG_VM_03_0_DUAL                    0x0
+#define GPIO_AG_VM_03_0_SCR                     GPIO_CTL3_VM_SCR_0
+#define GPIO_AG_VM_03_0_SCRREG                  GPIO_CTL3_VM_SCR_0
+#define GPIO_AG_VM_03_0_WORD_COUNT                      0x1
+#define GPIO_AG_VM_03_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_03_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_03_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_03_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AG_VM_03_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_03_0_VM1_SHIFT)
+#define GPIO_AG_VM_03_0_VM1_RANGE                       1:0
+#define GPIO_AG_VM_03_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AG_VM_03_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AG_VM_03_0_VM1_WOFFSET                     0x0
+#define GPIO_AG_VM_03_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_03_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_03_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_03_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AG_VM_03_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_03_0_VM2_SHIFT)
+#define GPIO_AG_VM_03_0_VM2_RANGE                       3:2
+#define GPIO_AG_VM_03_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AG_VM_03_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AG_VM_03_0_VM2_WOFFSET                     0x0
+#define GPIO_AG_VM_03_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_03_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_03_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_03_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AG_VM_03_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_03_0_VM3_SHIFT)
+#define GPIO_AG_VM_03_0_VM3_RANGE                       5:4
+#define GPIO_AG_VM_03_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AG_VM_03_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AG_VM_03_0_VM3_WOFFSET                     0x0
+#define GPIO_AG_VM_03_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_03_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_03_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_03_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AG_VM_03_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_03_0_VM4_SHIFT)
+#define GPIO_AG_VM_03_0_VM4_RANGE                       7:6
+#define GPIO_AG_VM_03_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AG_VM_03_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AG_VM_03_0_VM4_WOFFSET                     0x0
+#define GPIO_AG_VM_03_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_03_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_03_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_03_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AG_VM_03_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_03_0_VM5_SHIFT)
+#define GPIO_AG_VM_03_0_VM5_RANGE                       9:8
+#define GPIO_AG_VM_03_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AG_VM_03_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AG_VM_03_0_VM5_WOFFSET                     0x0
+#define GPIO_AG_VM_03_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_03_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_03_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_03_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AG_VM_03_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_03_0_VM6_SHIFT)
+#define GPIO_AG_VM_03_0_VM6_RANGE                       11:10
+#define GPIO_AG_VM_03_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AG_VM_03_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AG_VM_03_0_VM6_WOFFSET                     0x0
+#define GPIO_AG_VM_03_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_03_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_03_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_03_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AG_VM_03_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_03_0_VM7_SHIFT)
+#define GPIO_AG_VM_03_0_VM7_RANGE                       13:12
+#define GPIO_AG_VM_03_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AG_VM_03_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AG_VM_03_0_VM7_WOFFSET                     0x0
+#define GPIO_AG_VM_03_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_03_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_03_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_03_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AG_VM_03_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_03_0_VM8_SHIFT)
+#define GPIO_AG_VM_03_0_VM8_RANGE                       15:14
+#define GPIO_AG_VM_03_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AG_VM_03_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AG_VM_03_0_VM8_WOFFSET                     0x0
+#define GPIO_AG_VM_03_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_03_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_03_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_03_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_SCR_03_0
+#define GPIO_AG_SCR_03_0                        MK_ADDR_CONST(0x309c)
+#define GPIO_AG_SCR_03_0_SECURE                         0x0
+#define GPIO_AG_SCR_03_0_DUAL                   0x0
+#define GPIO_AG_SCR_03_0_SCR                    0
+#define GPIO_AG_SCR_03_0_SCRREG                         0
+#define GPIO_AG_SCR_03_0_WORD_COUNT                     0x1
+#define GPIO_AG_SCR_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_03_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_03_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_03_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_AG_SCR_03_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AG_SCR_03_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_03_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_03_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AG_SCR_03_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_03_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_AG_SCR_03_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AG_SCR_03_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_03_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_03_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AG_SCR_03_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_03_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_AG_SCR_03_0_SEC_REN_RANGE                  27:27
+#define GPIO_AG_SCR_03_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_03_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_03_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AG_SCR_03_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AG_SCR_03_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AG_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_AG_SCR_03_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AG_SCR_03_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AG_SCR_03_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AG_SCR_03_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AG_SCR_03_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AG_SCR_03_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_03_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_PR7_SHIFT)
+#define GPIO_AG_SCR_03_0_PR7_RANGE                      23:23
+#define GPIO_AG_SCR_03_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_03_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_03_0_PR7_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_03_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_PR6_SHIFT)
+#define GPIO_AG_SCR_03_0_PR6_RANGE                      22:22
+#define GPIO_AG_SCR_03_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_03_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_03_0_PR6_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_03_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_PR5_SHIFT)
+#define GPIO_AG_SCR_03_0_PR5_RANGE                      21:21
+#define GPIO_AG_SCR_03_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_03_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_03_0_PR5_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_03_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_PR4_SHIFT)
+#define GPIO_AG_SCR_03_0_PR4_RANGE                      20:20
+#define GPIO_AG_SCR_03_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_03_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_03_0_PR4_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_03_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_PR3_SHIFT)
+#define GPIO_AG_SCR_03_0_PR3_RANGE                      19:19
+#define GPIO_AG_SCR_03_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_03_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_03_0_PR3_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_03_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_PR2_SHIFT)
+#define GPIO_AG_SCR_03_0_PR2_RANGE                      18:18
+#define GPIO_AG_SCR_03_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_03_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_03_0_PR2_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_03_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_PR1_SHIFT)
+#define GPIO_AG_SCR_03_0_PR1_RANGE                      17:17
+#define GPIO_AG_SCR_03_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_03_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_03_0_PR1_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_03_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_PR0_SHIFT)
+#define GPIO_AG_SCR_03_0_PR0_RANGE                      16:16
+#define GPIO_AG_SCR_03_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_03_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_03_0_PR0_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_03_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G7W_SHIFT)
+#define GPIO_AG_SCR_03_0_G7W_RANGE                      15:15
+#define GPIO_AG_SCR_03_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_03_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_03_0_G7W_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_03_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G6W_SHIFT)
+#define GPIO_AG_SCR_03_0_G6W_RANGE                      14:14
+#define GPIO_AG_SCR_03_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_03_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_03_0_G6W_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_03_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G5W_SHIFT)
+#define GPIO_AG_SCR_03_0_G5W_RANGE                      13:13
+#define GPIO_AG_SCR_03_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_03_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_03_0_G5W_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_03_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G4W_SHIFT)
+#define GPIO_AG_SCR_03_0_G4W_RANGE                      12:12
+#define GPIO_AG_SCR_03_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_03_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_03_0_G4W_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_03_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G3W_SHIFT)
+#define GPIO_AG_SCR_03_0_G3W_RANGE                      11:11
+#define GPIO_AG_SCR_03_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_03_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_03_0_G3W_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_03_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G2W_SHIFT)
+#define GPIO_AG_SCR_03_0_G2W_RANGE                      10:10
+#define GPIO_AG_SCR_03_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_03_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_03_0_G2W_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_03_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G1W_SHIFT)
+#define GPIO_AG_SCR_03_0_G1W_RANGE                      9:9
+#define GPIO_AG_SCR_03_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_03_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_03_0_G1W_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_03_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G0W_SHIFT)
+#define GPIO_AG_SCR_03_0_G0W_RANGE                      8:8
+#define GPIO_AG_SCR_03_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_03_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_03_0_G0W_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_03_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G7R_SHIFT)
+#define GPIO_AG_SCR_03_0_G7R_RANGE                      7:7
+#define GPIO_AG_SCR_03_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_03_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_03_0_G7R_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_03_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G6R_SHIFT)
+#define GPIO_AG_SCR_03_0_G6R_RANGE                      6:6
+#define GPIO_AG_SCR_03_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_03_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_03_0_G6R_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_03_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G5R_SHIFT)
+#define GPIO_AG_SCR_03_0_G5R_RANGE                      5:5
+#define GPIO_AG_SCR_03_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_03_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_03_0_G5R_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_03_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G4R_SHIFT)
+#define GPIO_AG_SCR_03_0_G4R_RANGE                      4:4
+#define GPIO_AG_SCR_03_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_03_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_03_0_G4R_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_03_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G3R_SHIFT)
+#define GPIO_AG_SCR_03_0_G3R_RANGE                      3:3
+#define GPIO_AG_SCR_03_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_03_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_03_0_G3R_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_03_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G2R_SHIFT)
+#define GPIO_AG_SCR_03_0_G2R_RANGE                      2:2
+#define GPIO_AG_SCR_03_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_03_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_03_0_G2R_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_03_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G1R_SHIFT)
+#define GPIO_AG_SCR_03_0_G1R_RANGE                      1:1
+#define GPIO_AG_SCR_03_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_03_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_03_0_G1R_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_03_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_03_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_03_0_G0R_SHIFT)
+#define GPIO_AG_SCR_03_0_G0R_RANGE                      0:0
+#define GPIO_AG_SCR_03_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_03_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_03_0_G0R_WOFFSET                    0x0
+#define GPIO_AG_SCR_03_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_03_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_03_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_VM_04_0
+#define GPIO_AG_VM_04_0                 MK_ADDR_CONST(0x30a0)
+#define GPIO_AG_VM_04_0_SECURE                  0x0
+#define GPIO_AG_VM_04_0_DUAL                    0x0
+#define GPIO_AG_VM_04_0_SCR                     GPIO_CTL3_VM_SCR_0
+#define GPIO_AG_VM_04_0_SCRREG                  GPIO_CTL3_VM_SCR_0
+#define GPIO_AG_VM_04_0_WORD_COUNT                      0x1
+#define GPIO_AG_VM_04_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_04_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_04_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_04_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AG_VM_04_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_04_0_VM1_SHIFT)
+#define GPIO_AG_VM_04_0_VM1_RANGE                       1:0
+#define GPIO_AG_VM_04_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AG_VM_04_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AG_VM_04_0_VM1_WOFFSET                     0x0
+#define GPIO_AG_VM_04_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_04_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_04_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_04_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AG_VM_04_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_04_0_VM2_SHIFT)
+#define GPIO_AG_VM_04_0_VM2_RANGE                       3:2
+#define GPIO_AG_VM_04_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AG_VM_04_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AG_VM_04_0_VM2_WOFFSET                     0x0
+#define GPIO_AG_VM_04_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_04_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_04_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_04_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AG_VM_04_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_04_0_VM3_SHIFT)
+#define GPIO_AG_VM_04_0_VM3_RANGE                       5:4
+#define GPIO_AG_VM_04_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AG_VM_04_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AG_VM_04_0_VM3_WOFFSET                     0x0
+#define GPIO_AG_VM_04_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_04_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_04_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_04_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AG_VM_04_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_04_0_VM4_SHIFT)
+#define GPIO_AG_VM_04_0_VM4_RANGE                       7:6
+#define GPIO_AG_VM_04_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AG_VM_04_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AG_VM_04_0_VM4_WOFFSET                     0x0
+#define GPIO_AG_VM_04_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_04_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_04_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_04_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AG_VM_04_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_04_0_VM5_SHIFT)
+#define GPIO_AG_VM_04_0_VM5_RANGE                       9:8
+#define GPIO_AG_VM_04_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AG_VM_04_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AG_VM_04_0_VM5_WOFFSET                     0x0
+#define GPIO_AG_VM_04_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_04_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_04_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_04_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AG_VM_04_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_04_0_VM6_SHIFT)
+#define GPIO_AG_VM_04_0_VM6_RANGE                       11:10
+#define GPIO_AG_VM_04_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AG_VM_04_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AG_VM_04_0_VM6_WOFFSET                     0x0
+#define GPIO_AG_VM_04_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_04_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_04_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_04_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AG_VM_04_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_04_0_VM7_SHIFT)
+#define GPIO_AG_VM_04_0_VM7_RANGE                       13:12
+#define GPIO_AG_VM_04_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AG_VM_04_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AG_VM_04_0_VM7_WOFFSET                     0x0
+#define GPIO_AG_VM_04_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_04_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_04_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_04_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AG_VM_04_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_04_0_VM8_SHIFT)
+#define GPIO_AG_VM_04_0_VM8_RANGE                       15:14
+#define GPIO_AG_VM_04_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AG_VM_04_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AG_VM_04_0_VM8_WOFFSET                     0x0
+#define GPIO_AG_VM_04_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_04_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_04_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_04_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_SCR_04_0
+#define GPIO_AG_SCR_04_0                        MK_ADDR_CONST(0x30a4)
+#define GPIO_AG_SCR_04_0_SECURE                         0x0
+#define GPIO_AG_SCR_04_0_DUAL                   0x0
+#define GPIO_AG_SCR_04_0_SCR                    0
+#define GPIO_AG_SCR_04_0_SCRREG                         0
+#define GPIO_AG_SCR_04_0_WORD_COUNT                     0x1
+#define GPIO_AG_SCR_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_04_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_04_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_04_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_AG_SCR_04_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AG_SCR_04_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_04_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_04_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AG_SCR_04_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_04_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_AG_SCR_04_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AG_SCR_04_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_04_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_04_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AG_SCR_04_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_04_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_AG_SCR_04_0_SEC_REN_RANGE                  27:27
+#define GPIO_AG_SCR_04_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_04_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_04_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AG_SCR_04_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AG_SCR_04_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AG_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_AG_SCR_04_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AG_SCR_04_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AG_SCR_04_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AG_SCR_04_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AG_SCR_04_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AG_SCR_04_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_04_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_PR7_SHIFT)
+#define GPIO_AG_SCR_04_0_PR7_RANGE                      23:23
+#define GPIO_AG_SCR_04_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_04_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_04_0_PR7_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_04_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_PR6_SHIFT)
+#define GPIO_AG_SCR_04_0_PR6_RANGE                      22:22
+#define GPIO_AG_SCR_04_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_04_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_04_0_PR6_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_04_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_PR5_SHIFT)
+#define GPIO_AG_SCR_04_0_PR5_RANGE                      21:21
+#define GPIO_AG_SCR_04_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_04_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_04_0_PR5_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_04_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_PR4_SHIFT)
+#define GPIO_AG_SCR_04_0_PR4_RANGE                      20:20
+#define GPIO_AG_SCR_04_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_04_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_04_0_PR4_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_04_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_PR3_SHIFT)
+#define GPIO_AG_SCR_04_0_PR3_RANGE                      19:19
+#define GPIO_AG_SCR_04_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_04_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_04_0_PR3_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_04_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_PR2_SHIFT)
+#define GPIO_AG_SCR_04_0_PR2_RANGE                      18:18
+#define GPIO_AG_SCR_04_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_04_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_04_0_PR2_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_04_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_PR1_SHIFT)
+#define GPIO_AG_SCR_04_0_PR1_RANGE                      17:17
+#define GPIO_AG_SCR_04_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_04_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_04_0_PR1_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_04_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_PR0_SHIFT)
+#define GPIO_AG_SCR_04_0_PR0_RANGE                      16:16
+#define GPIO_AG_SCR_04_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_04_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_04_0_PR0_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_04_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G7W_SHIFT)
+#define GPIO_AG_SCR_04_0_G7W_RANGE                      15:15
+#define GPIO_AG_SCR_04_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_04_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_04_0_G7W_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_04_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G6W_SHIFT)
+#define GPIO_AG_SCR_04_0_G6W_RANGE                      14:14
+#define GPIO_AG_SCR_04_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_04_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_04_0_G6W_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_04_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G5W_SHIFT)
+#define GPIO_AG_SCR_04_0_G5W_RANGE                      13:13
+#define GPIO_AG_SCR_04_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_04_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_04_0_G5W_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_04_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G4W_SHIFT)
+#define GPIO_AG_SCR_04_0_G4W_RANGE                      12:12
+#define GPIO_AG_SCR_04_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_04_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_04_0_G4W_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_04_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G3W_SHIFT)
+#define GPIO_AG_SCR_04_0_G3W_RANGE                      11:11
+#define GPIO_AG_SCR_04_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_04_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_04_0_G3W_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_04_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G2W_SHIFT)
+#define GPIO_AG_SCR_04_0_G2W_RANGE                      10:10
+#define GPIO_AG_SCR_04_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_04_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_04_0_G2W_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_04_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G1W_SHIFT)
+#define GPIO_AG_SCR_04_0_G1W_RANGE                      9:9
+#define GPIO_AG_SCR_04_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_04_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_04_0_G1W_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_04_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G0W_SHIFT)
+#define GPIO_AG_SCR_04_0_G0W_RANGE                      8:8
+#define GPIO_AG_SCR_04_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_04_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_04_0_G0W_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_04_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G7R_SHIFT)
+#define GPIO_AG_SCR_04_0_G7R_RANGE                      7:7
+#define GPIO_AG_SCR_04_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_04_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_04_0_G7R_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_04_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G6R_SHIFT)
+#define GPIO_AG_SCR_04_0_G6R_RANGE                      6:6
+#define GPIO_AG_SCR_04_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_04_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_04_0_G6R_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_04_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G5R_SHIFT)
+#define GPIO_AG_SCR_04_0_G5R_RANGE                      5:5
+#define GPIO_AG_SCR_04_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_04_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_04_0_G5R_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_04_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G4R_SHIFT)
+#define GPIO_AG_SCR_04_0_G4R_RANGE                      4:4
+#define GPIO_AG_SCR_04_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_04_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_04_0_G4R_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_04_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G3R_SHIFT)
+#define GPIO_AG_SCR_04_0_G3R_RANGE                      3:3
+#define GPIO_AG_SCR_04_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_04_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_04_0_G3R_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_04_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G2R_SHIFT)
+#define GPIO_AG_SCR_04_0_G2R_RANGE                      2:2
+#define GPIO_AG_SCR_04_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_04_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_04_0_G2R_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_04_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G1R_SHIFT)
+#define GPIO_AG_SCR_04_0_G1R_RANGE                      1:1
+#define GPIO_AG_SCR_04_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_04_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_04_0_G1R_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_04_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_04_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_04_0_G0R_SHIFT)
+#define GPIO_AG_SCR_04_0_G0R_RANGE                      0:0
+#define GPIO_AG_SCR_04_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_04_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_04_0_G0R_WOFFSET                    0x0
+#define GPIO_AG_SCR_04_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_04_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_04_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_VM_05_0
+#define GPIO_AG_VM_05_0                 MK_ADDR_CONST(0x30a8)
+#define GPIO_AG_VM_05_0_SECURE                  0x0
+#define GPIO_AG_VM_05_0_DUAL                    0x0
+#define GPIO_AG_VM_05_0_SCR                     GPIO_CTL3_VM_SCR_0
+#define GPIO_AG_VM_05_0_SCRREG                  GPIO_CTL3_VM_SCR_0
+#define GPIO_AG_VM_05_0_WORD_COUNT                      0x1
+#define GPIO_AG_VM_05_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_05_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_05_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_05_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AG_VM_05_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_05_0_VM1_SHIFT)
+#define GPIO_AG_VM_05_0_VM1_RANGE                       1:0
+#define GPIO_AG_VM_05_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AG_VM_05_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AG_VM_05_0_VM1_WOFFSET                     0x0
+#define GPIO_AG_VM_05_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_05_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_05_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_05_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AG_VM_05_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_05_0_VM2_SHIFT)
+#define GPIO_AG_VM_05_0_VM2_RANGE                       3:2
+#define GPIO_AG_VM_05_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AG_VM_05_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AG_VM_05_0_VM2_WOFFSET                     0x0
+#define GPIO_AG_VM_05_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_05_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_05_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_05_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AG_VM_05_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_05_0_VM3_SHIFT)
+#define GPIO_AG_VM_05_0_VM3_RANGE                       5:4
+#define GPIO_AG_VM_05_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AG_VM_05_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AG_VM_05_0_VM3_WOFFSET                     0x0
+#define GPIO_AG_VM_05_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_05_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_05_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_05_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AG_VM_05_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_05_0_VM4_SHIFT)
+#define GPIO_AG_VM_05_0_VM4_RANGE                       7:6
+#define GPIO_AG_VM_05_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AG_VM_05_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AG_VM_05_0_VM4_WOFFSET                     0x0
+#define GPIO_AG_VM_05_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_05_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_05_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_05_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AG_VM_05_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_05_0_VM5_SHIFT)
+#define GPIO_AG_VM_05_0_VM5_RANGE                       9:8
+#define GPIO_AG_VM_05_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AG_VM_05_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AG_VM_05_0_VM5_WOFFSET                     0x0
+#define GPIO_AG_VM_05_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_05_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_05_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_05_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AG_VM_05_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_05_0_VM6_SHIFT)
+#define GPIO_AG_VM_05_0_VM6_RANGE                       11:10
+#define GPIO_AG_VM_05_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AG_VM_05_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AG_VM_05_0_VM6_WOFFSET                     0x0
+#define GPIO_AG_VM_05_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_05_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_05_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_05_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AG_VM_05_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_05_0_VM7_SHIFT)
+#define GPIO_AG_VM_05_0_VM7_RANGE                       13:12
+#define GPIO_AG_VM_05_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AG_VM_05_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AG_VM_05_0_VM7_WOFFSET                     0x0
+#define GPIO_AG_VM_05_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_05_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_05_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_05_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AG_VM_05_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_05_0_VM8_SHIFT)
+#define GPIO_AG_VM_05_0_VM8_RANGE                       15:14
+#define GPIO_AG_VM_05_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AG_VM_05_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AG_VM_05_0_VM8_WOFFSET                     0x0
+#define GPIO_AG_VM_05_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_05_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_05_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_05_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_SCR_05_0
+#define GPIO_AG_SCR_05_0                        MK_ADDR_CONST(0x30ac)
+#define GPIO_AG_SCR_05_0_SECURE                         0x0
+#define GPIO_AG_SCR_05_0_DUAL                   0x0
+#define GPIO_AG_SCR_05_0_SCR                    0
+#define GPIO_AG_SCR_05_0_SCRREG                         0
+#define GPIO_AG_SCR_05_0_WORD_COUNT                     0x1
+#define GPIO_AG_SCR_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_05_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_05_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_05_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_AG_SCR_05_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AG_SCR_05_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_05_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_05_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AG_SCR_05_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_05_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_AG_SCR_05_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AG_SCR_05_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_05_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_05_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AG_SCR_05_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_05_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_AG_SCR_05_0_SEC_REN_RANGE                  27:27
+#define GPIO_AG_SCR_05_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_05_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_05_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AG_SCR_05_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AG_SCR_05_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AG_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_AG_SCR_05_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AG_SCR_05_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AG_SCR_05_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AG_SCR_05_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AG_SCR_05_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AG_SCR_05_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_05_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_PR7_SHIFT)
+#define GPIO_AG_SCR_05_0_PR7_RANGE                      23:23
+#define GPIO_AG_SCR_05_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_05_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_05_0_PR7_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_05_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_PR6_SHIFT)
+#define GPIO_AG_SCR_05_0_PR6_RANGE                      22:22
+#define GPIO_AG_SCR_05_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_05_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_05_0_PR6_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_05_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_PR5_SHIFT)
+#define GPIO_AG_SCR_05_0_PR5_RANGE                      21:21
+#define GPIO_AG_SCR_05_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_05_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_05_0_PR5_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_05_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_PR4_SHIFT)
+#define GPIO_AG_SCR_05_0_PR4_RANGE                      20:20
+#define GPIO_AG_SCR_05_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_05_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_05_0_PR4_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_05_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_PR3_SHIFT)
+#define GPIO_AG_SCR_05_0_PR3_RANGE                      19:19
+#define GPIO_AG_SCR_05_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_05_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_05_0_PR3_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_05_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_PR2_SHIFT)
+#define GPIO_AG_SCR_05_0_PR2_RANGE                      18:18
+#define GPIO_AG_SCR_05_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_05_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_05_0_PR2_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_05_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_PR1_SHIFT)
+#define GPIO_AG_SCR_05_0_PR1_RANGE                      17:17
+#define GPIO_AG_SCR_05_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_05_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_05_0_PR1_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_05_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_PR0_SHIFT)
+#define GPIO_AG_SCR_05_0_PR0_RANGE                      16:16
+#define GPIO_AG_SCR_05_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_05_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_05_0_PR0_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_05_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G7W_SHIFT)
+#define GPIO_AG_SCR_05_0_G7W_RANGE                      15:15
+#define GPIO_AG_SCR_05_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_05_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_05_0_G7W_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_05_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G6W_SHIFT)
+#define GPIO_AG_SCR_05_0_G6W_RANGE                      14:14
+#define GPIO_AG_SCR_05_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_05_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_05_0_G6W_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_05_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G5W_SHIFT)
+#define GPIO_AG_SCR_05_0_G5W_RANGE                      13:13
+#define GPIO_AG_SCR_05_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_05_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_05_0_G5W_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_05_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G4W_SHIFT)
+#define GPIO_AG_SCR_05_0_G4W_RANGE                      12:12
+#define GPIO_AG_SCR_05_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_05_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_05_0_G4W_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_05_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G3W_SHIFT)
+#define GPIO_AG_SCR_05_0_G3W_RANGE                      11:11
+#define GPIO_AG_SCR_05_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_05_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_05_0_G3W_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_05_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G2W_SHIFT)
+#define GPIO_AG_SCR_05_0_G2W_RANGE                      10:10
+#define GPIO_AG_SCR_05_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_05_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_05_0_G2W_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_05_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G1W_SHIFT)
+#define GPIO_AG_SCR_05_0_G1W_RANGE                      9:9
+#define GPIO_AG_SCR_05_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_05_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_05_0_G1W_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_05_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G0W_SHIFT)
+#define GPIO_AG_SCR_05_0_G0W_RANGE                      8:8
+#define GPIO_AG_SCR_05_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_05_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_05_0_G0W_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_05_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G7R_SHIFT)
+#define GPIO_AG_SCR_05_0_G7R_RANGE                      7:7
+#define GPIO_AG_SCR_05_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_05_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_05_0_G7R_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_05_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G6R_SHIFT)
+#define GPIO_AG_SCR_05_0_G6R_RANGE                      6:6
+#define GPIO_AG_SCR_05_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_05_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_05_0_G6R_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_05_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G5R_SHIFT)
+#define GPIO_AG_SCR_05_0_G5R_RANGE                      5:5
+#define GPIO_AG_SCR_05_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_05_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_05_0_G5R_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_05_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G4R_SHIFT)
+#define GPIO_AG_SCR_05_0_G4R_RANGE                      4:4
+#define GPIO_AG_SCR_05_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_05_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_05_0_G4R_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_05_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G3R_SHIFT)
+#define GPIO_AG_SCR_05_0_G3R_RANGE                      3:3
+#define GPIO_AG_SCR_05_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_05_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_05_0_G3R_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_05_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G2R_SHIFT)
+#define GPIO_AG_SCR_05_0_G2R_RANGE                      2:2
+#define GPIO_AG_SCR_05_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_05_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_05_0_G2R_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_05_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G1R_SHIFT)
+#define GPIO_AG_SCR_05_0_G1R_RANGE                      1:1
+#define GPIO_AG_SCR_05_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_05_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_05_0_G1R_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_05_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_05_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_05_0_G0R_SHIFT)
+#define GPIO_AG_SCR_05_0_G0R_RANGE                      0:0
+#define GPIO_AG_SCR_05_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_05_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_05_0_G0R_WOFFSET                    0x0
+#define GPIO_AG_SCR_05_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_05_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_05_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_VM_06_0
+#define GPIO_AG_VM_06_0                 MK_ADDR_CONST(0x30b0)
+#define GPIO_AG_VM_06_0_SECURE                  0x0
+#define GPIO_AG_VM_06_0_DUAL                    0x0
+#define GPIO_AG_VM_06_0_SCR                     GPIO_CTL3_VM_SCR_0
+#define GPIO_AG_VM_06_0_SCRREG                  GPIO_CTL3_VM_SCR_0
+#define GPIO_AG_VM_06_0_WORD_COUNT                      0x1
+#define GPIO_AG_VM_06_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_06_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_06_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_06_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AG_VM_06_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_06_0_VM1_SHIFT)
+#define GPIO_AG_VM_06_0_VM1_RANGE                       1:0
+#define GPIO_AG_VM_06_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AG_VM_06_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AG_VM_06_0_VM1_WOFFSET                     0x0
+#define GPIO_AG_VM_06_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_06_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_06_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_06_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AG_VM_06_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_06_0_VM2_SHIFT)
+#define GPIO_AG_VM_06_0_VM2_RANGE                       3:2
+#define GPIO_AG_VM_06_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AG_VM_06_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AG_VM_06_0_VM2_WOFFSET                     0x0
+#define GPIO_AG_VM_06_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_06_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_06_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_06_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AG_VM_06_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_06_0_VM3_SHIFT)
+#define GPIO_AG_VM_06_0_VM3_RANGE                       5:4
+#define GPIO_AG_VM_06_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AG_VM_06_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AG_VM_06_0_VM3_WOFFSET                     0x0
+#define GPIO_AG_VM_06_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_06_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_06_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_06_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AG_VM_06_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_06_0_VM4_SHIFT)
+#define GPIO_AG_VM_06_0_VM4_RANGE                       7:6
+#define GPIO_AG_VM_06_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AG_VM_06_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AG_VM_06_0_VM4_WOFFSET                     0x0
+#define GPIO_AG_VM_06_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_06_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_06_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_06_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AG_VM_06_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_06_0_VM5_SHIFT)
+#define GPIO_AG_VM_06_0_VM5_RANGE                       9:8
+#define GPIO_AG_VM_06_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AG_VM_06_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AG_VM_06_0_VM5_WOFFSET                     0x0
+#define GPIO_AG_VM_06_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_06_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_06_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_06_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AG_VM_06_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_06_0_VM6_SHIFT)
+#define GPIO_AG_VM_06_0_VM6_RANGE                       11:10
+#define GPIO_AG_VM_06_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AG_VM_06_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AG_VM_06_0_VM6_WOFFSET                     0x0
+#define GPIO_AG_VM_06_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_06_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_06_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_06_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AG_VM_06_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_06_0_VM7_SHIFT)
+#define GPIO_AG_VM_06_0_VM7_RANGE                       13:12
+#define GPIO_AG_VM_06_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AG_VM_06_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AG_VM_06_0_VM7_WOFFSET                     0x0
+#define GPIO_AG_VM_06_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_06_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_06_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_06_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AG_VM_06_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_06_0_VM8_SHIFT)
+#define GPIO_AG_VM_06_0_VM8_RANGE                       15:14
+#define GPIO_AG_VM_06_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AG_VM_06_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AG_VM_06_0_VM8_WOFFSET                     0x0
+#define GPIO_AG_VM_06_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_06_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_06_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_06_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_SCR_06_0
+#define GPIO_AG_SCR_06_0                        MK_ADDR_CONST(0x30b4)
+#define GPIO_AG_SCR_06_0_SECURE                         0x0
+#define GPIO_AG_SCR_06_0_DUAL                   0x0
+#define GPIO_AG_SCR_06_0_SCR                    0
+#define GPIO_AG_SCR_06_0_SCRREG                         0
+#define GPIO_AG_SCR_06_0_WORD_COUNT                     0x1
+#define GPIO_AG_SCR_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_06_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_06_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_06_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_SEC_LCK_SHIFT)
+#define GPIO_AG_SCR_06_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AG_SCR_06_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_06_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_06_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AG_SCR_06_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_06_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_SEC_WEN_SHIFT)
+#define GPIO_AG_SCR_06_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AG_SCR_06_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_06_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_06_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AG_SCR_06_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_06_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_SEC_REN_SHIFT)
+#define GPIO_AG_SCR_06_0_SEC_REN_RANGE                  27:27
+#define GPIO_AG_SCR_06_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_06_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_06_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AG_SCR_06_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AG_SCR_06_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AG_SCR_06_0_SEC_OWNER_SHIFT)
+#define GPIO_AG_SCR_06_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AG_SCR_06_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AG_SCR_06_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AG_SCR_06_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AG_SCR_06_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AG_SCR_06_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_06_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_PR7_SHIFT)
+#define GPIO_AG_SCR_06_0_PR7_RANGE                      23:23
+#define GPIO_AG_SCR_06_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_06_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_06_0_PR7_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_06_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_PR6_SHIFT)
+#define GPIO_AG_SCR_06_0_PR6_RANGE                      22:22
+#define GPIO_AG_SCR_06_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_06_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_06_0_PR6_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_06_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_PR5_SHIFT)
+#define GPIO_AG_SCR_06_0_PR5_RANGE                      21:21
+#define GPIO_AG_SCR_06_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_06_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_06_0_PR5_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_06_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_PR4_SHIFT)
+#define GPIO_AG_SCR_06_0_PR4_RANGE                      20:20
+#define GPIO_AG_SCR_06_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_06_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_06_0_PR4_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_06_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_PR3_SHIFT)
+#define GPIO_AG_SCR_06_0_PR3_RANGE                      19:19
+#define GPIO_AG_SCR_06_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_06_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_06_0_PR3_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_06_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_PR2_SHIFT)
+#define GPIO_AG_SCR_06_0_PR2_RANGE                      18:18
+#define GPIO_AG_SCR_06_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_06_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_06_0_PR2_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_06_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_PR1_SHIFT)
+#define GPIO_AG_SCR_06_0_PR1_RANGE                      17:17
+#define GPIO_AG_SCR_06_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_06_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_06_0_PR1_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_06_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_PR0_SHIFT)
+#define GPIO_AG_SCR_06_0_PR0_RANGE                      16:16
+#define GPIO_AG_SCR_06_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_06_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_06_0_PR0_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_06_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G7W_SHIFT)
+#define GPIO_AG_SCR_06_0_G7W_RANGE                      15:15
+#define GPIO_AG_SCR_06_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_06_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_06_0_G7W_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_06_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G6W_SHIFT)
+#define GPIO_AG_SCR_06_0_G6W_RANGE                      14:14
+#define GPIO_AG_SCR_06_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_06_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_06_0_G6W_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_06_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G5W_SHIFT)
+#define GPIO_AG_SCR_06_0_G5W_RANGE                      13:13
+#define GPIO_AG_SCR_06_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_06_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_06_0_G5W_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_06_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G4W_SHIFT)
+#define GPIO_AG_SCR_06_0_G4W_RANGE                      12:12
+#define GPIO_AG_SCR_06_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_06_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_06_0_G4W_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_06_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G3W_SHIFT)
+#define GPIO_AG_SCR_06_0_G3W_RANGE                      11:11
+#define GPIO_AG_SCR_06_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_06_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_06_0_G3W_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_06_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G2W_SHIFT)
+#define GPIO_AG_SCR_06_0_G2W_RANGE                      10:10
+#define GPIO_AG_SCR_06_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_06_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_06_0_G2W_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_06_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G1W_SHIFT)
+#define GPIO_AG_SCR_06_0_G1W_RANGE                      9:9
+#define GPIO_AG_SCR_06_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_06_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_06_0_G1W_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_06_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G0W_SHIFT)
+#define GPIO_AG_SCR_06_0_G0W_RANGE                      8:8
+#define GPIO_AG_SCR_06_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_06_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_06_0_G0W_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_06_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G7R_SHIFT)
+#define GPIO_AG_SCR_06_0_G7R_RANGE                      7:7
+#define GPIO_AG_SCR_06_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_06_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_06_0_G7R_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_06_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G6R_SHIFT)
+#define GPIO_AG_SCR_06_0_G6R_RANGE                      6:6
+#define GPIO_AG_SCR_06_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_06_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_06_0_G6R_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_06_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G5R_SHIFT)
+#define GPIO_AG_SCR_06_0_G5R_RANGE                      5:5
+#define GPIO_AG_SCR_06_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_06_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_06_0_G5R_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_06_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G4R_SHIFT)
+#define GPIO_AG_SCR_06_0_G4R_RANGE                      4:4
+#define GPIO_AG_SCR_06_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_06_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_06_0_G4R_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_06_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G3R_SHIFT)
+#define GPIO_AG_SCR_06_0_G3R_RANGE                      3:3
+#define GPIO_AG_SCR_06_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_06_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_06_0_G3R_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_06_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G2R_SHIFT)
+#define GPIO_AG_SCR_06_0_G2R_RANGE                      2:2
+#define GPIO_AG_SCR_06_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_06_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_06_0_G2R_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_06_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G1R_SHIFT)
+#define GPIO_AG_SCR_06_0_G1R_RANGE                      1:1
+#define GPIO_AG_SCR_06_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_06_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_06_0_G1R_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_06_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_06_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_06_0_G0R_SHIFT)
+#define GPIO_AG_SCR_06_0_G0R_RANGE                      0:0
+#define GPIO_AG_SCR_06_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_06_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_06_0_G0R_WOFFSET                    0x0
+#define GPIO_AG_SCR_06_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_06_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_06_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_VM_07_0
+#define GPIO_AG_VM_07_0                 MK_ADDR_CONST(0x30b8)
+#define GPIO_AG_VM_07_0_SECURE                  0x0
+#define GPIO_AG_VM_07_0_DUAL                    0x0
+#define GPIO_AG_VM_07_0_SCR                     GPIO_CTL3_VM_SCR_0
+#define GPIO_AG_VM_07_0_SCRREG                  GPIO_CTL3_VM_SCR_0
+#define GPIO_AG_VM_07_0_WORD_COUNT                      0x1
+#define GPIO_AG_VM_07_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_07_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_07_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AG_VM_07_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AG_VM_07_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_07_0_VM1_SHIFT)
+#define GPIO_AG_VM_07_0_VM1_RANGE                       1:0
+#define GPIO_AG_VM_07_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AG_VM_07_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AG_VM_07_0_VM1_WOFFSET                     0x0
+#define GPIO_AG_VM_07_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_07_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_07_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_07_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AG_VM_07_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_07_0_VM2_SHIFT)
+#define GPIO_AG_VM_07_0_VM2_RANGE                       3:2
+#define GPIO_AG_VM_07_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AG_VM_07_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AG_VM_07_0_VM2_WOFFSET                     0x0
+#define GPIO_AG_VM_07_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_07_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_07_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_07_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AG_VM_07_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_07_0_VM3_SHIFT)
+#define GPIO_AG_VM_07_0_VM3_RANGE                       5:4
+#define GPIO_AG_VM_07_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AG_VM_07_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AG_VM_07_0_VM3_WOFFSET                     0x0
+#define GPIO_AG_VM_07_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_07_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_07_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_07_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AG_VM_07_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_07_0_VM4_SHIFT)
+#define GPIO_AG_VM_07_0_VM4_RANGE                       7:6
+#define GPIO_AG_VM_07_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AG_VM_07_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AG_VM_07_0_VM4_WOFFSET                     0x0
+#define GPIO_AG_VM_07_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_07_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_07_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_07_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AG_VM_07_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_07_0_VM5_SHIFT)
+#define GPIO_AG_VM_07_0_VM5_RANGE                       9:8
+#define GPIO_AG_VM_07_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AG_VM_07_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AG_VM_07_0_VM5_WOFFSET                     0x0
+#define GPIO_AG_VM_07_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_07_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_07_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_07_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AG_VM_07_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_07_0_VM6_SHIFT)
+#define GPIO_AG_VM_07_0_VM6_RANGE                       11:10
+#define GPIO_AG_VM_07_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AG_VM_07_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AG_VM_07_0_VM6_WOFFSET                     0x0
+#define GPIO_AG_VM_07_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_07_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_07_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_07_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AG_VM_07_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_07_0_VM7_SHIFT)
+#define GPIO_AG_VM_07_0_VM7_RANGE                       13:12
+#define GPIO_AG_VM_07_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AG_VM_07_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AG_VM_07_0_VM7_WOFFSET                     0x0
+#define GPIO_AG_VM_07_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_07_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_07_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AG_VM_07_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AG_VM_07_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AG_VM_07_0_VM8_SHIFT)
+#define GPIO_AG_VM_07_0_VM8_RANGE                       15:14
+#define GPIO_AG_VM_07_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AG_VM_07_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AG_VM_07_0_VM8_WOFFSET                     0x0
+#define GPIO_AG_VM_07_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_07_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AG_VM_07_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_VM_07_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_SCR_07_0
+#define GPIO_AG_SCR_07_0                        MK_ADDR_CONST(0x30bc)
+#define GPIO_AG_SCR_07_0_SECURE                         0x0
+#define GPIO_AG_SCR_07_0_DUAL                   0x0
+#define GPIO_AG_SCR_07_0_SCR                    0
+#define GPIO_AG_SCR_07_0_SCRREG                         0
+#define GPIO_AG_SCR_07_0_WORD_COUNT                     0x1
+#define GPIO_AG_SCR_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_07_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AG_SCR_07_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_07_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_SEC_LCK_SHIFT)
+#define GPIO_AG_SCR_07_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AG_SCR_07_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_07_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AG_SCR_07_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AG_SCR_07_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_07_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_SEC_WEN_SHIFT)
+#define GPIO_AG_SCR_07_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AG_SCR_07_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_07_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AG_SCR_07_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AG_SCR_07_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_07_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_SEC_REN_SHIFT)
+#define GPIO_AG_SCR_07_0_SEC_REN_RANGE                  27:27
+#define GPIO_AG_SCR_07_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_07_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AG_SCR_07_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AG_SCR_07_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AG_SCR_07_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AG_SCR_07_0_SEC_OWNER_SHIFT)
+#define GPIO_AG_SCR_07_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AG_SCR_07_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AG_SCR_07_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AG_SCR_07_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AG_SCR_07_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AG_SCR_07_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_07_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_PR7_SHIFT)
+#define GPIO_AG_SCR_07_0_PR7_RANGE                      23:23
+#define GPIO_AG_SCR_07_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_07_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AG_SCR_07_0_PR7_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_07_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_PR6_SHIFT)
+#define GPIO_AG_SCR_07_0_PR6_RANGE                      22:22
+#define GPIO_AG_SCR_07_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_07_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AG_SCR_07_0_PR6_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_07_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_PR5_SHIFT)
+#define GPIO_AG_SCR_07_0_PR5_RANGE                      21:21
+#define GPIO_AG_SCR_07_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_07_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AG_SCR_07_0_PR5_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_07_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_PR4_SHIFT)
+#define GPIO_AG_SCR_07_0_PR4_RANGE                      20:20
+#define GPIO_AG_SCR_07_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_07_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AG_SCR_07_0_PR4_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_07_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_PR3_SHIFT)
+#define GPIO_AG_SCR_07_0_PR3_RANGE                      19:19
+#define GPIO_AG_SCR_07_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_07_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AG_SCR_07_0_PR3_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_07_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_PR2_SHIFT)
+#define GPIO_AG_SCR_07_0_PR2_RANGE                      18:18
+#define GPIO_AG_SCR_07_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_07_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AG_SCR_07_0_PR2_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_07_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_PR1_SHIFT)
+#define GPIO_AG_SCR_07_0_PR1_RANGE                      17:17
+#define GPIO_AG_SCR_07_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_07_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AG_SCR_07_0_PR1_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_07_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_PR0_SHIFT)
+#define GPIO_AG_SCR_07_0_PR0_RANGE                      16:16
+#define GPIO_AG_SCR_07_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_07_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AG_SCR_07_0_PR0_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_07_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G7W_SHIFT)
+#define GPIO_AG_SCR_07_0_G7W_RANGE                      15:15
+#define GPIO_AG_SCR_07_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_07_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AG_SCR_07_0_G7W_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_07_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G6W_SHIFT)
+#define GPIO_AG_SCR_07_0_G6W_RANGE                      14:14
+#define GPIO_AG_SCR_07_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_07_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AG_SCR_07_0_G6W_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_07_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G5W_SHIFT)
+#define GPIO_AG_SCR_07_0_G5W_RANGE                      13:13
+#define GPIO_AG_SCR_07_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_07_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AG_SCR_07_0_G5W_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_07_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G4W_SHIFT)
+#define GPIO_AG_SCR_07_0_G4W_RANGE                      12:12
+#define GPIO_AG_SCR_07_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_07_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AG_SCR_07_0_G4W_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_07_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G3W_SHIFT)
+#define GPIO_AG_SCR_07_0_G3W_RANGE                      11:11
+#define GPIO_AG_SCR_07_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_07_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AG_SCR_07_0_G3W_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_07_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G2W_SHIFT)
+#define GPIO_AG_SCR_07_0_G2W_RANGE                      10:10
+#define GPIO_AG_SCR_07_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_07_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AG_SCR_07_0_G2W_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_07_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G1W_SHIFT)
+#define GPIO_AG_SCR_07_0_G1W_RANGE                      9:9
+#define GPIO_AG_SCR_07_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_07_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AG_SCR_07_0_G1W_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_07_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G0W_SHIFT)
+#define GPIO_AG_SCR_07_0_G0W_RANGE                      8:8
+#define GPIO_AG_SCR_07_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_07_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AG_SCR_07_0_G0W_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_07_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G7R_SHIFT)
+#define GPIO_AG_SCR_07_0_G7R_RANGE                      7:7
+#define GPIO_AG_SCR_07_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_07_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AG_SCR_07_0_G7R_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_07_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G6R_SHIFT)
+#define GPIO_AG_SCR_07_0_G6R_RANGE                      6:6
+#define GPIO_AG_SCR_07_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_07_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AG_SCR_07_0_G6R_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_07_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G5R_SHIFT)
+#define GPIO_AG_SCR_07_0_G5R_RANGE                      5:5
+#define GPIO_AG_SCR_07_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_07_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_SCR_07_0_G5R_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_07_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G4R_SHIFT)
+#define GPIO_AG_SCR_07_0_G4R_RANGE                      4:4
+#define GPIO_AG_SCR_07_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_07_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AG_SCR_07_0_G4R_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_07_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G3R_SHIFT)
+#define GPIO_AG_SCR_07_0_G3R_RANGE                      3:3
+#define GPIO_AG_SCR_07_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_07_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AG_SCR_07_0_G3R_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_07_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G2R_SHIFT)
+#define GPIO_AG_SCR_07_0_G2R_RANGE                      2:2
+#define GPIO_AG_SCR_07_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_07_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AG_SCR_07_0_G2R_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_07_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G1R_SHIFT)
+#define GPIO_AG_SCR_07_0_G1R_RANGE                      1:1
+#define GPIO_AG_SCR_07_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_07_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AG_SCR_07_0_G1R_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AG_SCR_07_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_07_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_SCR_07_0_G0R_SHIFT)
+#define GPIO_AG_SCR_07_0_G0R_RANGE                      0:0
+#define GPIO_AG_SCR_07_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_07_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_SCR_07_0_G0R_WOFFSET                    0x0
+#define GPIO_AG_SCR_07_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_SCR_07_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AG_SCR_07_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_VM_00_0
+#define GPIO_AE_VM_00_0                 MK_ADDR_CONST(0x30c0)
+#define GPIO_AE_VM_00_0_SECURE                  0x0
+#define GPIO_AE_VM_00_0_DUAL                    0x0
+#define GPIO_AE_VM_00_0_SCR                     GPIO_CTL3_VM_SCR_0
+#define GPIO_AE_VM_00_0_SCRREG                  GPIO_CTL3_VM_SCR_0
+#define GPIO_AE_VM_00_0_WORD_COUNT                      0x1
+#define GPIO_AE_VM_00_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AE_VM_00_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AE_VM_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AE_VM_00_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AE_VM_00_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AE_VM_00_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_00_0_VM1_SHIFT)
+#define GPIO_AE_VM_00_0_VM1_RANGE                       1:0
+#define GPIO_AE_VM_00_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AE_VM_00_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AE_VM_00_0_VM1_WOFFSET                     0x0
+#define GPIO_AE_VM_00_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_00_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_00_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AE_VM_00_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AE_VM_00_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_00_0_VM2_SHIFT)
+#define GPIO_AE_VM_00_0_VM2_RANGE                       3:2
+#define GPIO_AE_VM_00_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AE_VM_00_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AE_VM_00_0_VM2_WOFFSET                     0x0
+#define GPIO_AE_VM_00_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_00_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_00_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AE_VM_00_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AE_VM_00_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_00_0_VM3_SHIFT)
+#define GPIO_AE_VM_00_0_VM3_RANGE                       5:4
+#define GPIO_AE_VM_00_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AE_VM_00_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AE_VM_00_0_VM3_WOFFSET                     0x0
+#define GPIO_AE_VM_00_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_00_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_00_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AE_VM_00_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AE_VM_00_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_00_0_VM4_SHIFT)
+#define GPIO_AE_VM_00_0_VM4_RANGE                       7:6
+#define GPIO_AE_VM_00_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AE_VM_00_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AE_VM_00_0_VM4_WOFFSET                     0x0
+#define GPIO_AE_VM_00_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_00_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_00_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AE_VM_00_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AE_VM_00_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_00_0_VM5_SHIFT)
+#define GPIO_AE_VM_00_0_VM5_RANGE                       9:8
+#define GPIO_AE_VM_00_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AE_VM_00_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AE_VM_00_0_VM5_WOFFSET                     0x0
+#define GPIO_AE_VM_00_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_00_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_00_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AE_VM_00_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AE_VM_00_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_00_0_VM6_SHIFT)
+#define GPIO_AE_VM_00_0_VM6_RANGE                       11:10
+#define GPIO_AE_VM_00_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AE_VM_00_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AE_VM_00_0_VM6_WOFFSET                     0x0
+#define GPIO_AE_VM_00_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_00_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_00_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AE_VM_00_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AE_VM_00_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_00_0_VM7_SHIFT)
+#define GPIO_AE_VM_00_0_VM7_RANGE                       13:12
+#define GPIO_AE_VM_00_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AE_VM_00_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AE_VM_00_0_VM7_WOFFSET                     0x0
+#define GPIO_AE_VM_00_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_00_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_00_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AE_VM_00_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AE_VM_00_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_00_0_VM8_SHIFT)
+#define GPIO_AE_VM_00_0_VM8_RANGE                       15:14
+#define GPIO_AE_VM_00_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AE_VM_00_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AE_VM_00_0_VM8_WOFFSET                     0x0
+#define GPIO_AE_VM_00_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_00_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_00_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_00_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_SCR_00_0
+#define GPIO_AE_SCR_00_0                        MK_ADDR_CONST(0x30c4)
+#define GPIO_AE_SCR_00_0_SECURE                         0x0
+#define GPIO_AE_SCR_00_0_DUAL                   0x0
+#define GPIO_AE_SCR_00_0_SCR                    0
+#define GPIO_AE_SCR_00_0_SCRREG                         0
+#define GPIO_AE_SCR_00_0_WORD_COUNT                     0x1
+#define GPIO_AE_SCR_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AE_SCR_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AE_SCR_00_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AE_SCR_00_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AE_SCR_00_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_AE_SCR_00_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AE_SCR_00_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AE_SCR_00_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AE_SCR_00_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AE_SCR_00_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AE_SCR_00_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_AE_SCR_00_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AE_SCR_00_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AE_SCR_00_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AE_SCR_00_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AE_SCR_00_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AE_SCR_00_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_AE_SCR_00_0_SEC_REN_RANGE                  27:27
+#define GPIO_AE_SCR_00_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AE_SCR_00_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AE_SCR_00_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AE_SCR_00_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AE_SCR_00_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AE_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_AE_SCR_00_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AE_SCR_00_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AE_SCR_00_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AE_SCR_00_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AE_SCR_00_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AE_SCR_00_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AE_SCR_00_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_PR7_SHIFT)
+#define GPIO_AE_SCR_00_0_PR7_RANGE                      23:23
+#define GPIO_AE_SCR_00_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AE_SCR_00_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AE_SCR_00_0_PR7_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AE_SCR_00_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_PR6_SHIFT)
+#define GPIO_AE_SCR_00_0_PR6_RANGE                      22:22
+#define GPIO_AE_SCR_00_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AE_SCR_00_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AE_SCR_00_0_PR6_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AE_SCR_00_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_PR5_SHIFT)
+#define GPIO_AE_SCR_00_0_PR5_RANGE                      21:21
+#define GPIO_AE_SCR_00_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AE_SCR_00_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AE_SCR_00_0_PR5_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AE_SCR_00_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_PR4_SHIFT)
+#define GPIO_AE_SCR_00_0_PR4_RANGE                      20:20
+#define GPIO_AE_SCR_00_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AE_SCR_00_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AE_SCR_00_0_PR4_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AE_SCR_00_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_PR3_SHIFT)
+#define GPIO_AE_SCR_00_0_PR3_RANGE                      19:19
+#define GPIO_AE_SCR_00_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AE_SCR_00_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AE_SCR_00_0_PR3_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AE_SCR_00_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_PR2_SHIFT)
+#define GPIO_AE_SCR_00_0_PR2_RANGE                      18:18
+#define GPIO_AE_SCR_00_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AE_SCR_00_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AE_SCR_00_0_PR2_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AE_SCR_00_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_PR1_SHIFT)
+#define GPIO_AE_SCR_00_0_PR1_RANGE                      17:17
+#define GPIO_AE_SCR_00_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AE_SCR_00_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AE_SCR_00_0_PR1_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AE_SCR_00_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_PR0_SHIFT)
+#define GPIO_AE_SCR_00_0_PR0_RANGE                      16:16
+#define GPIO_AE_SCR_00_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AE_SCR_00_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AE_SCR_00_0_PR0_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AE_SCR_00_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G7W_SHIFT)
+#define GPIO_AE_SCR_00_0_G7W_RANGE                      15:15
+#define GPIO_AE_SCR_00_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AE_SCR_00_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AE_SCR_00_0_G7W_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AE_SCR_00_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G6W_SHIFT)
+#define GPIO_AE_SCR_00_0_G6W_RANGE                      14:14
+#define GPIO_AE_SCR_00_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AE_SCR_00_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AE_SCR_00_0_G6W_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AE_SCR_00_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G5W_SHIFT)
+#define GPIO_AE_SCR_00_0_G5W_RANGE                      13:13
+#define GPIO_AE_SCR_00_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AE_SCR_00_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AE_SCR_00_0_G5W_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AE_SCR_00_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G4W_SHIFT)
+#define GPIO_AE_SCR_00_0_G4W_RANGE                      12:12
+#define GPIO_AE_SCR_00_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AE_SCR_00_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AE_SCR_00_0_G4W_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AE_SCR_00_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G3W_SHIFT)
+#define GPIO_AE_SCR_00_0_G3W_RANGE                      11:11
+#define GPIO_AE_SCR_00_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AE_SCR_00_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AE_SCR_00_0_G3W_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AE_SCR_00_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G2W_SHIFT)
+#define GPIO_AE_SCR_00_0_G2W_RANGE                      10:10
+#define GPIO_AE_SCR_00_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AE_SCR_00_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AE_SCR_00_0_G2W_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AE_SCR_00_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G1W_SHIFT)
+#define GPIO_AE_SCR_00_0_G1W_RANGE                      9:9
+#define GPIO_AE_SCR_00_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AE_SCR_00_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AE_SCR_00_0_G1W_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AE_SCR_00_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G0W_SHIFT)
+#define GPIO_AE_SCR_00_0_G0W_RANGE                      8:8
+#define GPIO_AE_SCR_00_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AE_SCR_00_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AE_SCR_00_0_G0W_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AE_SCR_00_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G7R_SHIFT)
+#define GPIO_AE_SCR_00_0_G7R_RANGE                      7:7
+#define GPIO_AE_SCR_00_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AE_SCR_00_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AE_SCR_00_0_G7R_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AE_SCR_00_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G6R_SHIFT)
+#define GPIO_AE_SCR_00_0_G6R_RANGE                      6:6
+#define GPIO_AE_SCR_00_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AE_SCR_00_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AE_SCR_00_0_G6R_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AE_SCR_00_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G5R_SHIFT)
+#define GPIO_AE_SCR_00_0_G5R_RANGE                      5:5
+#define GPIO_AE_SCR_00_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AE_SCR_00_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AE_SCR_00_0_G5R_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AE_SCR_00_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G4R_SHIFT)
+#define GPIO_AE_SCR_00_0_G4R_RANGE                      4:4
+#define GPIO_AE_SCR_00_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AE_SCR_00_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AE_SCR_00_0_G4R_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AE_SCR_00_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G3R_SHIFT)
+#define GPIO_AE_SCR_00_0_G3R_RANGE                      3:3
+#define GPIO_AE_SCR_00_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AE_SCR_00_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AE_SCR_00_0_G3R_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AE_SCR_00_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G2R_SHIFT)
+#define GPIO_AE_SCR_00_0_G2R_RANGE                      2:2
+#define GPIO_AE_SCR_00_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AE_SCR_00_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AE_SCR_00_0_G2R_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AE_SCR_00_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G1R_SHIFT)
+#define GPIO_AE_SCR_00_0_G1R_RANGE                      1:1
+#define GPIO_AE_SCR_00_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AE_SCR_00_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AE_SCR_00_0_G1R_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_00_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AE_SCR_00_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_00_0_G0R_SHIFT)
+#define GPIO_AE_SCR_00_0_G0R_RANGE                      0:0
+#define GPIO_AE_SCR_00_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AE_SCR_00_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AE_SCR_00_0_G0R_WOFFSET                    0x0
+#define GPIO_AE_SCR_00_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_00_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_00_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_VM_01_0
+#define GPIO_AE_VM_01_0                 MK_ADDR_CONST(0x30c8)
+#define GPIO_AE_VM_01_0_SECURE                  0x0
+#define GPIO_AE_VM_01_0_DUAL                    0x0
+#define GPIO_AE_VM_01_0_SCR                     GPIO_CTL3_VM_SCR_0
+#define GPIO_AE_VM_01_0_SCRREG                  GPIO_CTL3_VM_SCR_0
+#define GPIO_AE_VM_01_0_WORD_COUNT                      0x1
+#define GPIO_AE_VM_01_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AE_VM_01_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AE_VM_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AE_VM_01_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AE_VM_01_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AE_VM_01_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_01_0_VM1_SHIFT)
+#define GPIO_AE_VM_01_0_VM1_RANGE                       1:0
+#define GPIO_AE_VM_01_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AE_VM_01_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AE_VM_01_0_VM1_WOFFSET                     0x0
+#define GPIO_AE_VM_01_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_01_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_01_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AE_VM_01_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AE_VM_01_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_01_0_VM2_SHIFT)
+#define GPIO_AE_VM_01_0_VM2_RANGE                       3:2
+#define GPIO_AE_VM_01_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AE_VM_01_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AE_VM_01_0_VM2_WOFFSET                     0x0
+#define GPIO_AE_VM_01_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_01_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_01_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AE_VM_01_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AE_VM_01_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_01_0_VM3_SHIFT)
+#define GPIO_AE_VM_01_0_VM3_RANGE                       5:4
+#define GPIO_AE_VM_01_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AE_VM_01_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AE_VM_01_0_VM3_WOFFSET                     0x0
+#define GPIO_AE_VM_01_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_01_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_01_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AE_VM_01_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AE_VM_01_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_01_0_VM4_SHIFT)
+#define GPIO_AE_VM_01_0_VM4_RANGE                       7:6
+#define GPIO_AE_VM_01_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AE_VM_01_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AE_VM_01_0_VM4_WOFFSET                     0x0
+#define GPIO_AE_VM_01_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_01_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_01_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AE_VM_01_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AE_VM_01_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_01_0_VM5_SHIFT)
+#define GPIO_AE_VM_01_0_VM5_RANGE                       9:8
+#define GPIO_AE_VM_01_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AE_VM_01_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AE_VM_01_0_VM5_WOFFSET                     0x0
+#define GPIO_AE_VM_01_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_01_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_01_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AE_VM_01_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AE_VM_01_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_01_0_VM6_SHIFT)
+#define GPIO_AE_VM_01_0_VM6_RANGE                       11:10
+#define GPIO_AE_VM_01_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AE_VM_01_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AE_VM_01_0_VM6_WOFFSET                     0x0
+#define GPIO_AE_VM_01_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_01_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_01_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AE_VM_01_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AE_VM_01_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_01_0_VM7_SHIFT)
+#define GPIO_AE_VM_01_0_VM7_RANGE                       13:12
+#define GPIO_AE_VM_01_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AE_VM_01_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AE_VM_01_0_VM7_WOFFSET                     0x0
+#define GPIO_AE_VM_01_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_01_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_01_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AE_VM_01_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AE_VM_01_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_VM_01_0_VM8_SHIFT)
+#define GPIO_AE_VM_01_0_VM8_RANGE                       15:14
+#define GPIO_AE_VM_01_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AE_VM_01_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AE_VM_01_0_VM8_WOFFSET                     0x0
+#define GPIO_AE_VM_01_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_01_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_VM_01_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_VM_01_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_SCR_01_0
+#define GPIO_AE_SCR_01_0                        MK_ADDR_CONST(0x30cc)
+#define GPIO_AE_SCR_01_0_SECURE                         0x0
+#define GPIO_AE_SCR_01_0_DUAL                   0x0
+#define GPIO_AE_SCR_01_0_SCR                    0
+#define GPIO_AE_SCR_01_0_SCRREG                         0
+#define GPIO_AE_SCR_01_0_WORD_COUNT                     0x1
+#define GPIO_AE_SCR_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AE_SCR_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AE_SCR_01_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AE_SCR_01_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AE_SCR_01_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_AE_SCR_01_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AE_SCR_01_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AE_SCR_01_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AE_SCR_01_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AE_SCR_01_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AE_SCR_01_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_AE_SCR_01_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AE_SCR_01_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AE_SCR_01_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AE_SCR_01_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AE_SCR_01_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AE_SCR_01_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_AE_SCR_01_0_SEC_REN_RANGE                  27:27
+#define GPIO_AE_SCR_01_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AE_SCR_01_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AE_SCR_01_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AE_SCR_01_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AE_SCR_01_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AE_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_AE_SCR_01_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AE_SCR_01_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AE_SCR_01_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AE_SCR_01_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AE_SCR_01_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AE_SCR_01_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AE_SCR_01_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_PR7_SHIFT)
+#define GPIO_AE_SCR_01_0_PR7_RANGE                      23:23
+#define GPIO_AE_SCR_01_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AE_SCR_01_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AE_SCR_01_0_PR7_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AE_SCR_01_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_PR6_SHIFT)
+#define GPIO_AE_SCR_01_0_PR6_RANGE                      22:22
+#define GPIO_AE_SCR_01_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AE_SCR_01_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AE_SCR_01_0_PR6_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AE_SCR_01_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_PR5_SHIFT)
+#define GPIO_AE_SCR_01_0_PR5_RANGE                      21:21
+#define GPIO_AE_SCR_01_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AE_SCR_01_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AE_SCR_01_0_PR5_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AE_SCR_01_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_PR4_SHIFT)
+#define GPIO_AE_SCR_01_0_PR4_RANGE                      20:20
+#define GPIO_AE_SCR_01_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AE_SCR_01_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AE_SCR_01_0_PR4_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AE_SCR_01_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_PR3_SHIFT)
+#define GPIO_AE_SCR_01_0_PR3_RANGE                      19:19
+#define GPIO_AE_SCR_01_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AE_SCR_01_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AE_SCR_01_0_PR3_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AE_SCR_01_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_PR2_SHIFT)
+#define GPIO_AE_SCR_01_0_PR2_RANGE                      18:18
+#define GPIO_AE_SCR_01_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AE_SCR_01_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AE_SCR_01_0_PR2_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AE_SCR_01_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_PR1_SHIFT)
+#define GPIO_AE_SCR_01_0_PR1_RANGE                      17:17
+#define GPIO_AE_SCR_01_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AE_SCR_01_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AE_SCR_01_0_PR1_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AE_SCR_01_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_PR0_SHIFT)
+#define GPIO_AE_SCR_01_0_PR0_RANGE                      16:16
+#define GPIO_AE_SCR_01_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AE_SCR_01_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AE_SCR_01_0_PR0_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AE_SCR_01_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G7W_SHIFT)
+#define GPIO_AE_SCR_01_0_G7W_RANGE                      15:15
+#define GPIO_AE_SCR_01_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AE_SCR_01_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AE_SCR_01_0_G7W_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AE_SCR_01_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G6W_SHIFT)
+#define GPIO_AE_SCR_01_0_G6W_RANGE                      14:14
+#define GPIO_AE_SCR_01_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AE_SCR_01_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AE_SCR_01_0_G6W_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AE_SCR_01_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G5W_SHIFT)
+#define GPIO_AE_SCR_01_0_G5W_RANGE                      13:13
+#define GPIO_AE_SCR_01_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AE_SCR_01_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AE_SCR_01_0_G5W_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AE_SCR_01_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G4W_SHIFT)
+#define GPIO_AE_SCR_01_0_G4W_RANGE                      12:12
+#define GPIO_AE_SCR_01_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AE_SCR_01_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AE_SCR_01_0_G4W_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AE_SCR_01_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G3W_SHIFT)
+#define GPIO_AE_SCR_01_0_G3W_RANGE                      11:11
+#define GPIO_AE_SCR_01_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AE_SCR_01_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AE_SCR_01_0_G3W_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AE_SCR_01_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G2W_SHIFT)
+#define GPIO_AE_SCR_01_0_G2W_RANGE                      10:10
+#define GPIO_AE_SCR_01_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AE_SCR_01_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AE_SCR_01_0_G2W_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AE_SCR_01_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G1W_SHIFT)
+#define GPIO_AE_SCR_01_0_G1W_RANGE                      9:9
+#define GPIO_AE_SCR_01_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AE_SCR_01_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AE_SCR_01_0_G1W_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AE_SCR_01_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G0W_SHIFT)
+#define GPIO_AE_SCR_01_0_G0W_RANGE                      8:8
+#define GPIO_AE_SCR_01_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AE_SCR_01_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AE_SCR_01_0_G0W_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AE_SCR_01_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G7R_SHIFT)
+#define GPIO_AE_SCR_01_0_G7R_RANGE                      7:7
+#define GPIO_AE_SCR_01_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AE_SCR_01_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AE_SCR_01_0_G7R_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AE_SCR_01_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G6R_SHIFT)
+#define GPIO_AE_SCR_01_0_G6R_RANGE                      6:6
+#define GPIO_AE_SCR_01_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AE_SCR_01_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AE_SCR_01_0_G6R_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AE_SCR_01_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G5R_SHIFT)
+#define GPIO_AE_SCR_01_0_G5R_RANGE                      5:5
+#define GPIO_AE_SCR_01_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AE_SCR_01_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AE_SCR_01_0_G5R_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AE_SCR_01_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G4R_SHIFT)
+#define GPIO_AE_SCR_01_0_G4R_RANGE                      4:4
+#define GPIO_AE_SCR_01_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AE_SCR_01_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AE_SCR_01_0_G4R_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AE_SCR_01_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G3R_SHIFT)
+#define GPIO_AE_SCR_01_0_G3R_RANGE                      3:3
+#define GPIO_AE_SCR_01_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AE_SCR_01_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AE_SCR_01_0_G3R_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AE_SCR_01_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G2R_SHIFT)
+#define GPIO_AE_SCR_01_0_G2R_RANGE                      2:2
+#define GPIO_AE_SCR_01_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AE_SCR_01_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AE_SCR_01_0_G2R_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AE_SCR_01_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G1R_SHIFT)
+#define GPIO_AE_SCR_01_0_G1R_RANGE                      1:1
+#define GPIO_AE_SCR_01_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AE_SCR_01_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AE_SCR_01_0_G1R_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AE_SCR_01_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AE_SCR_01_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_SCR_01_0_G0R_SHIFT)
+#define GPIO_AE_SCR_01_0_G0R_RANGE                      0:0
+#define GPIO_AE_SCR_01_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AE_SCR_01_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AE_SCR_01_0_G0R_WOFFSET                    0x0
+#define GPIO_AE_SCR_01_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_SCR_01_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AE_SCR_01_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x30d0
+
+// Reserved address 0x30d4
+
+// Reserved address 0x30d8
+
+// Reserved address 0x30dc
+
+// Reserved address 0x30e0
+
+// Reserved address 0x30e4
+
+// Reserved address 0x30e8
+
+// Reserved address 0x30ec
+
+// Reserved address 0x30f0
+
+// Reserved address 0x30f4
+
+// Reserved address 0x30f8
+
+// Reserved address 0x30fc
+
+// Register GPIO_AF_VM_00_0
+#define GPIO_AF_VM_00_0                 MK_ADDR_CONST(0x3100)
+#define GPIO_AF_VM_00_0_SECURE                  0x0
+#define GPIO_AF_VM_00_0_DUAL                    0x0
+#define GPIO_AF_VM_00_0_SCR                     GPIO_CTL3_VM_SCR_0
+#define GPIO_AF_VM_00_0_SCRREG                  GPIO_CTL3_VM_SCR_0
+#define GPIO_AF_VM_00_0_WORD_COUNT                      0x1
+#define GPIO_AF_VM_00_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AF_VM_00_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AF_VM_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AF_VM_00_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AF_VM_00_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AF_VM_00_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_00_0_VM1_SHIFT)
+#define GPIO_AF_VM_00_0_VM1_RANGE                       1:0
+#define GPIO_AF_VM_00_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AF_VM_00_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AF_VM_00_0_VM1_WOFFSET                     0x0
+#define GPIO_AF_VM_00_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_00_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_00_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_00_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AF_VM_00_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_00_0_VM2_SHIFT)
+#define GPIO_AF_VM_00_0_VM2_RANGE                       3:2
+#define GPIO_AF_VM_00_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AF_VM_00_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AF_VM_00_0_VM2_WOFFSET                     0x0
+#define GPIO_AF_VM_00_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_00_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_00_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_00_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AF_VM_00_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_00_0_VM3_SHIFT)
+#define GPIO_AF_VM_00_0_VM3_RANGE                       5:4
+#define GPIO_AF_VM_00_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AF_VM_00_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AF_VM_00_0_VM3_WOFFSET                     0x0
+#define GPIO_AF_VM_00_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_00_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_00_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_00_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AF_VM_00_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_00_0_VM4_SHIFT)
+#define GPIO_AF_VM_00_0_VM4_RANGE                       7:6
+#define GPIO_AF_VM_00_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AF_VM_00_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AF_VM_00_0_VM4_WOFFSET                     0x0
+#define GPIO_AF_VM_00_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_00_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_00_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_00_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AF_VM_00_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_00_0_VM5_SHIFT)
+#define GPIO_AF_VM_00_0_VM5_RANGE                       9:8
+#define GPIO_AF_VM_00_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AF_VM_00_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AF_VM_00_0_VM5_WOFFSET                     0x0
+#define GPIO_AF_VM_00_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_00_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_00_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_00_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AF_VM_00_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_00_0_VM6_SHIFT)
+#define GPIO_AF_VM_00_0_VM6_RANGE                       11:10
+#define GPIO_AF_VM_00_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AF_VM_00_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AF_VM_00_0_VM6_WOFFSET                     0x0
+#define GPIO_AF_VM_00_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_00_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_00_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_00_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AF_VM_00_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_00_0_VM7_SHIFT)
+#define GPIO_AF_VM_00_0_VM7_RANGE                       13:12
+#define GPIO_AF_VM_00_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AF_VM_00_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AF_VM_00_0_VM7_WOFFSET                     0x0
+#define GPIO_AF_VM_00_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_00_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_00_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_00_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AF_VM_00_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_00_0_VM8_SHIFT)
+#define GPIO_AF_VM_00_0_VM8_RANGE                       15:14
+#define GPIO_AF_VM_00_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AF_VM_00_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AF_VM_00_0_VM8_WOFFSET                     0x0
+#define GPIO_AF_VM_00_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_00_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_00_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_00_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_SCR_00_0
+#define GPIO_AF_SCR_00_0                        MK_ADDR_CONST(0x3104)
+#define GPIO_AF_SCR_00_0_SECURE                         0x0
+#define GPIO_AF_SCR_00_0_DUAL                   0x0
+#define GPIO_AF_SCR_00_0_SCR                    0
+#define GPIO_AF_SCR_00_0_SCRREG                         0
+#define GPIO_AF_SCR_00_0_WORD_COUNT                     0x1
+#define GPIO_AF_SCR_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AF_SCR_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AF_SCR_00_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AF_SCR_00_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AF_SCR_00_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_AF_SCR_00_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AF_SCR_00_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AF_SCR_00_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AF_SCR_00_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AF_SCR_00_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AF_SCR_00_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_AF_SCR_00_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AF_SCR_00_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AF_SCR_00_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AF_SCR_00_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AF_SCR_00_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AF_SCR_00_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_AF_SCR_00_0_SEC_REN_RANGE                  27:27
+#define GPIO_AF_SCR_00_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AF_SCR_00_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AF_SCR_00_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AF_SCR_00_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AF_SCR_00_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AF_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_AF_SCR_00_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AF_SCR_00_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AF_SCR_00_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AF_SCR_00_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AF_SCR_00_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AF_SCR_00_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AF_SCR_00_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_PR7_SHIFT)
+#define GPIO_AF_SCR_00_0_PR7_RANGE                      23:23
+#define GPIO_AF_SCR_00_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AF_SCR_00_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AF_SCR_00_0_PR7_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AF_SCR_00_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_PR6_SHIFT)
+#define GPIO_AF_SCR_00_0_PR6_RANGE                      22:22
+#define GPIO_AF_SCR_00_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AF_SCR_00_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AF_SCR_00_0_PR6_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AF_SCR_00_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_PR5_SHIFT)
+#define GPIO_AF_SCR_00_0_PR5_RANGE                      21:21
+#define GPIO_AF_SCR_00_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AF_SCR_00_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AF_SCR_00_0_PR5_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AF_SCR_00_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_PR4_SHIFT)
+#define GPIO_AF_SCR_00_0_PR4_RANGE                      20:20
+#define GPIO_AF_SCR_00_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AF_SCR_00_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AF_SCR_00_0_PR4_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AF_SCR_00_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_PR3_SHIFT)
+#define GPIO_AF_SCR_00_0_PR3_RANGE                      19:19
+#define GPIO_AF_SCR_00_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AF_SCR_00_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AF_SCR_00_0_PR3_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AF_SCR_00_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_PR2_SHIFT)
+#define GPIO_AF_SCR_00_0_PR2_RANGE                      18:18
+#define GPIO_AF_SCR_00_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AF_SCR_00_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AF_SCR_00_0_PR2_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AF_SCR_00_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_PR1_SHIFT)
+#define GPIO_AF_SCR_00_0_PR1_RANGE                      17:17
+#define GPIO_AF_SCR_00_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AF_SCR_00_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AF_SCR_00_0_PR1_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AF_SCR_00_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_PR0_SHIFT)
+#define GPIO_AF_SCR_00_0_PR0_RANGE                      16:16
+#define GPIO_AF_SCR_00_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AF_SCR_00_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AF_SCR_00_0_PR0_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AF_SCR_00_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G7W_SHIFT)
+#define GPIO_AF_SCR_00_0_G7W_RANGE                      15:15
+#define GPIO_AF_SCR_00_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AF_SCR_00_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AF_SCR_00_0_G7W_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AF_SCR_00_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G6W_SHIFT)
+#define GPIO_AF_SCR_00_0_G6W_RANGE                      14:14
+#define GPIO_AF_SCR_00_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AF_SCR_00_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AF_SCR_00_0_G6W_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AF_SCR_00_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G5W_SHIFT)
+#define GPIO_AF_SCR_00_0_G5W_RANGE                      13:13
+#define GPIO_AF_SCR_00_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AF_SCR_00_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AF_SCR_00_0_G5W_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AF_SCR_00_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G4W_SHIFT)
+#define GPIO_AF_SCR_00_0_G4W_RANGE                      12:12
+#define GPIO_AF_SCR_00_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AF_SCR_00_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AF_SCR_00_0_G4W_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AF_SCR_00_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G3W_SHIFT)
+#define GPIO_AF_SCR_00_0_G3W_RANGE                      11:11
+#define GPIO_AF_SCR_00_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AF_SCR_00_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AF_SCR_00_0_G3W_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AF_SCR_00_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G2W_SHIFT)
+#define GPIO_AF_SCR_00_0_G2W_RANGE                      10:10
+#define GPIO_AF_SCR_00_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AF_SCR_00_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AF_SCR_00_0_G2W_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AF_SCR_00_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G1W_SHIFT)
+#define GPIO_AF_SCR_00_0_G1W_RANGE                      9:9
+#define GPIO_AF_SCR_00_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AF_SCR_00_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AF_SCR_00_0_G1W_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AF_SCR_00_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G0W_SHIFT)
+#define GPIO_AF_SCR_00_0_G0W_RANGE                      8:8
+#define GPIO_AF_SCR_00_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AF_SCR_00_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AF_SCR_00_0_G0W_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AF_SCR_00_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G7R_SHIFT)
+#define GPIO_AF_SCR_00_0_G7R_RANGE                      7:7
+#define GPIO_AF_SCR_00_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AF_SCR_00_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AF_SCR_00_0_G7R_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AF_SCR_00_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G6R_SHIFT)
+#define GPIO_AF_SCR_00_0_G6R_RANGE                      6:6
+#define GPIO_AF_SCR_00_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AF_SCR_00_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AF_SCR_00_0_G6R_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AF_SCR_00_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G5R_SHIFT)
+#define GPIO_AF_SCR_00_0_G5R_RANGE                      5:5
+#define GPIO_AF_SCR_00_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AF_SCR_00_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AF_SCR_00_0_G5R_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AF_SCR_00_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G4R_SHIFT)
+#define GPIO_AF_SCR_00_0_G4R_RANGE                      4:4
+#define GPIO_AF_SCR_00_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AF_SCR_00_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AF_SCR_00_0_G4R_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AF_SCR_00_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G3R_SHIFT)
+#define GPIO_AF_SCR_00_0_G3R_RANGE                      3:3
+#define GPIO_AF_SCR_00_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AF_SCR_00_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AF_SCR_00_0_G3R_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AF_SCR_00_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G2R_SHIFT)
+#define GPIO_AF_SCR_00_0_G2R_RANGE                      2:2
+#define GPIO_AF_SCR_00_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AF_SCR_00_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AF_SCR_00_0_G2R_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AF_SCR_00_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G1R_SHIFT)
+#define GPIO_AF_SCR_00_0_G1R_RANGE                      1:1
+#define GPIO_AF_SCR_00_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AF_SCR_00_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AF_SCR_00_0_G1R_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_00_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AF_SCR_00_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_00_0_G0R_SHIFT)
+#define GPIO_AF_SCR_00_0_G0R_RANGE                      0:0
+#define GPIO_AF_SCR_00_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AF_SCR_00_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AF_SCR_00_0_G0R_WOFFSET                    0x0
+#define GPIO_AF_SCR_00_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_00_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_00_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_VM_01_0
+#define GPIO_AF_VM_01_0                 MK_ADDR_CONST(0x3108)
+#define GPIO_AF_VM_01_0_SECURE                  0x0
+#define GPIO_AF_VM_01_0_DUAL                    0x0
+#define GPIO_AF_VM_01_0_SCR                     GPIO_CTL3_VM_SCR_0
+#define GPIO_AF_VM_01_0_SCRREG                  GPIO_CTL3_VM_SCR_0
+#define GPIO_AF_VM_01_0_WORD_COUNT                      0x1
+#define GPIO_AF_VM_01_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AF_VM_01_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AF_VM_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AF_VM_01_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AF_VM_01_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AF_VM_01_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_01_0_VM1_SHIFT)
+#define GPIO_AF_VM_01_0_VM1_RANGE                       1:0
+#define GPIO_AF_VM_01_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AF_VM_01_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AF_VM_01_0_VM1_WOFFSET                     0x0
+#define GPIO_AF_VM_01_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_01_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_01_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_01_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AF_VM_01_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_01_0_VM2_SHIFT)
+#define GPIO_AF_VM_01_0_VM2_RANGE                       3:2
+#define GPIO_AF_VM_01_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AF_VM_01_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AF_VM_01_0_VM2_WOFFSET                     0x0
+#define GPIO_AF_VM_01_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_01_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_01_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_01_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AF_VM_01_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_01_0_VM3_SHIFT)
+#define GPIO_AF_VM_01_0_VM3_RANGE                       5:4
+#define GPIO_AF_VM_01_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AF_VM_01_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AF_VM_01_0_VM3_WOFFSET                     0x0
+#define GPIO_AF_VM_01_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_01_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_01_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_01_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AF_VM_01_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_01_0_VM4_SHIFT)
+#define GPIO_AF_VM_01_0_VM4_RANGE                       7:6
+#define GPIO_AF_VM_01_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AF_VM_01_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AF_VM_01_0_VM4_WOFFSET                     0x0
+#define GPIO_AF_VM_01_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_01_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_01_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_01_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AF_VM_01_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_01_0_VM5_SHIFT)
+#define GPIO_AF_VM_01_0_VM5_RANGE                       9:8
+#define GPIO_AF_VM_01_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AF_VM_01_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AF_VM_01_0_VM5_WOFFSET                     0x0
+#define GPIO_AF_VM_01_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_01_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_01_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_01_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AF_VM_01_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_01_0_VM6_SHIFT)
+#define GPIO_AF_VM_01_0_VM6_RANGE                       11:10
+#define GPIO_AF_VM_01_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AF_VM_01_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AF_VM_01_0_VM6_WOFFSET                     0x0
+#define GPIO_AF_VM_01_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_01_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_01_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_01_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AF_VM_01_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_01_0_VM7_SHIFT)
+#define GPIO_AF_VM_01_0_VM7_RANGE                       13:12
+#define GPIO_AF_VM_01_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AF_VM_01_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AF_VM_01_0_VM7_WOFFSET                     0x0
+#define GPIO_AF_VM_01_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_01_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_01_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_01_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AF_VM_01_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_01_0_VM8_SHIFT)
+#define GPIO_AF_VM_01_0_VM8_RANGE                       15:14
+#define GPIO_AF_VM_01_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AF_VM_01_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AF_VM_01_0_VM8_WOFFSET                     0x0
+#define GPIO_AF_VM_01_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_01_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_01_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_01_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_SCR_01_0
+#define GPIO_AF_SCR_01_0                        MK_ADDR_CONST(0x310c)
+#define GPIO_AF_SCR_01_0_SECURE                         0x0
+#define GPIO_AF_SCR_01_0_DUAL                   0x0
+#define GPIO_AF_SCR_01_0_SCR                    0
+#define GPIO_AF_SCR_01_0_SCRREG                         0
+#define GPIO_AF_SCR_01_0_WORD_COUNT                     0x1
+#define GPIO_AF_SCR_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AF_SCR_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AF_SCR_01_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AF_SCR_01_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AF_SCR_01_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_AF_SCR_01_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AF_SCR_01_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AF_SCR_01_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AF_SCR_01_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AF_SCR_01_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AF_SCR_01_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_AF_SCR_01_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AF_SCR_01_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AF_SCR_01_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AF_SCR_01_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AF_SCR_01_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AF_SCR_01_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_AF_SCR_01_0_SEC_REN_RANGE                  27:27
+#define GPIO_AF_SCR_01_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AF_SCR_01_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AF_SCR_01_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AF_SCR_01_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AF_SCR_01_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AF_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_AF_SCR_01_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AF_SCR_01_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AF_SCR_01_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AF_SCR_01_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AF_SCR_01_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AF_SCR_01_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AF_SCR_01_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_PR7_SHIFT)
+#define GPIO_AF_SCR_01_0_PR7_RANGE                      23:23
+#define GPIO_AF_SCR_01_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AF_SCR_01_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AF_SCR_01_0_PR7_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AF_SCR_01_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_PR6_SHIFT)
+#define GPIO_AF_SCR_01_0_PR6_RANGE                      22:22
+#define GPIO_AF_SCR_01_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AF_SCR_01_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AF_SCR_01_0_PR6_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AF_SCR_01_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_PR5_SHIFT)
+#define GPIO_AF_SCR_01_0_PR5_RANGE                      21:21
+#define GPIO_AF_SCR_01_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AF_SCR_01_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AF_SCR_01_0_PR5_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AF_SCR_01_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_PR4_SHIFT)
+#define GPIO_AF_SCR_01_0_PR4_RANGE                      20:20
+#define GPIO_AF_SCR_01_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AF_SCR_01_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AF_SCR_01_0_PR4_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AF_SCR_01_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_PR3_SHIFT)
+#define GPIO_AF_SCR_01_0_PR3_RANGE                      19:19
+#define GPIO_AF_SCR_01_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AF_SCR_01_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AF_SCR_01_0_PR3_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AF_SCR_01_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_PR2_SHIFT)
+#define GPIO_AF_SCR_01_0_PR2_RANGE                      18:18
+#define GPIO_AF_SCR_01_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AF_SCR_01_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AF_SCR_01_0_PR2_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AF_SCR_01_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_PR1_SHIFT)
+#define GPIO_AF_SCR_01_0_PR1_RANGE                      17:17
+#define GPIO_AF_SCR_01_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AF_SCR_01_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AF_SCR_01_0_PR1_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AF_SCR_01_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_PR0_SHIFT)
+#define GPIO_AF_SCR_01_0_PR0_RANGE                      16:16
+#define GPIO_AF_SCR_01_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AF_SCR_01_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AF_SCR_01_0_PR0_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AF_SCR_01_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G7W_SHIFT)
+#define GPIO_AF_SCR_01_0_G7W_RANGE                      15:15
+#define GPIO_AF_SCR_01_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AF_SCR_01_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AF_SCR_01_0_G7W_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AF_SCR_01_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G6W_SHIFT)
+#define GPIO_AF_SCR_01_0_G6W_RANGE                      14:14
+#define GPIO_AF_SCR_01_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AF_SCR_01_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AF_SCR_01_0_G6W_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AF_SCR_01_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G5W_SHIFT)
+#define GPIO_AF_SCR_01_0_G5W_RANGE                      13:13
+#define GPIO_AF_SCR_01_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AF_SCR_01_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AF_SCR_01_0_G5W_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AF_SCR_01_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G4W_SHIFT)
+#define GPIO_AF_SCR_01_0_G4W_RANGE                      12:12
+#define GPIO_AF_SCR_01_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AF_SCR_01_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AF_SCR_01_0_G4W_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AF_SCR_01_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G3W_SHIFT)
+#define GPIO_AF_SCR_01_0_G3W_RANGE                      11:11
+#define GPIO_AF_SCR_01_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AF_SCR_01_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AF_SCR_01_0_G3W_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AF_SCR_01_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G2W_SHIFT)
+#define GPIO_AF_SCR_01_0_G2W_RANGE                      10:10
+#define GPIO_AF_SCR_01_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AF_SCR_01_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AF_SCR_01_0_G2W_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AF_SCR_01_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G1W_SHIFT)
+#define GPIO_AF_SCR_01_0_G1W_RANGE                      9:9
+#define GPIO_AF_SCR_01_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AF_SCR_01_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AF_SCR_01_0_G1W_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AF_SCR_01_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G0W_SHIFT)
+#define GPIO_AF_SCR_01_0_G0W_RANGE                      8:8
+#define GPIO_AF_SCR_01_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AF_SCR_01_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AF_SCR_01_0_G0W_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AF_SCR_01_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G7R_SHIFT)
+#define GPIO_AF_SCR_01_0_G7R_RANGE                      7:7
+#define GPIO_AF_SCR_01_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AF_SCR_01_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AF_SCR_01_0_G7R_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AF_SCR_01_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G6R_SHIFT)
+#define GPIO_AF_SCR_01_0_G6R_RANGE                      6:6
+#define GPIO_AF_SCR_01_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AF_SCR_01_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AF_SCR_01_0_G6R_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AF_SCR_01_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G5R_SHIFT)
+#define GPIO_AF_SCR_01_0_G5R_RANGE                      5:5
+#define GPIO_AF_SCR_01_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AF_SCR_01_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AF_SCR_01_0_G5R_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AF_SCR_01_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G4R_SHIFT)
+#define GPIO_AF_SCR_01_0_G4R_RANGE                      4:4
+#define GPIO_AF_SCR_01_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AF_SCR_01_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AF_SCR_01_0_G4R_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AF_SCR_01_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G3R_SHIFT)
+#define GPIO_AF_SCR_01_0_G3R_RANGE                      3:3
+#define GPIO_AF_SCR_01_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AF_SCR_01_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AF_SCR_01_0_G3R_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AF_SCR_01_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G2R_SHIFT)
+#define GPIO_AF_SCR_01_0_G2R_RANGE                      2:2
+#define GPIO_AF_SCR_01_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AF_SCR_01_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AF_SCR_01_0_G2R_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AF_SCR_01_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G1R_SHIFT)
+#define GPIO_AF_SCR_01_0_G1R_RANGE                      1:1
+#define GPIO_AF_SCR_01_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AF_SCR_01_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AF_SCR_01_0_G1R_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_01_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AF_SCR_01_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_01_0_G0R_SHIFT)
+#define GPIO_AF_SCR_01_0_G0R_RANGE                      0:0
+#define GPIO_AF_SCR_01_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AF_SCR_01_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AF_SCR_01_0_G0R_WOFFSET                    0x0
+#define GPIO_AF_SCR_01_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_01_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_01_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_VM_02_0
+#define GPIO_AF_VM_02_0                 MK_ADDR_CONST(0x3110)
+#define GPIO_AF_VM_02_0_SECURE                  0x0
+#define GPIO_AF_VM_02_0_DUAL                    0x0
+#define GPIO_AF_VM_02_0_SCR                     GPIO_CTL3_VM_SCR_0
+#define GPIO_AF_VM_02_0_SCRREG                  GPIO_CTL3_VM_SCR_0
+#define GPIO_AF_VM_02_0_WORD_COUNT                      0x1
+#define GPIO_AF_VM_02_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AF_VM_02_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AF_VM_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AF_VM_02_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AF_VM_02_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AF_VM_02_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_02_0_VM1_SHIFT)
+#define GPIO_AF_VM_02_0_VM1_RANGE                       1:0
+#define GPIO_AF_VM_02_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AF_VM_02_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AF_VM_02_0_VM1_WOFFSET                     0x0
+#define GPIO_AF_VM_02_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_02_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_02_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_02_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AF_VM_02_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_02_0_VM2_SHIFT)
+#define GPIO_AF_VM_02_0_VM2_RANGE                       3:2
+#define GPIO_AF_VM_02_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AF_VM_02_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AF_VM_02_0_VM2_WOFFSET                     0x0
+#define GPIO_AF_VM_02_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_02_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_02_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_02_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AF_VM_02_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_02_0_VM3_SHIFT)
+#define GPIO_AF_VM_02_0_VM3_RANGE                       5:4
+#define GPIO_AF_VM_02_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AF_VM_02_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AF_VM_02_0_VM3_WOFFSET                     0x0
+#define GPIO_AF_VM_02_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_02_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_02_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_02_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AF_VM_02_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_02_0_VM4_SHIFT)
+#define GPIO_AF_VM_02_0_VM4_RANGE                       7:6
+#define GPIO_AF_VM_02_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AF_VM_02_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AF_VM_02_0_VM4_WOFFSET                     0x0
+#define GPIO_AF_VM_02_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_02_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_02_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_02_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AF_VM_02_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_02_0_VM5_SHIFT)
+#define GPIO_AF_VM_02_0_VM5_RANGE                       9:8
+#define GPIO_AF_VM_02_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AF_VM_02_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AF_VM_02_0_VM5_WOFFSET                     0x0
+#define GPIO_AF_VM_02_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_02_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_02_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_02_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AF_VM_02_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_02_0_VM6_SHIFT)
+#define GPIO_AF_VM_02_0_VM6_RANGE                       11:10
+#define GPIO_AF_VM_02_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AF_VM_02_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AF_VM_02_0_VM6_WOFFSET                     0x0
+#define GPIO_AF_VM_02_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_02_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_02_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_02_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AF_VM_02_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_02_0_VM7_SHIFT)
+#define GPIO_AF_VM_02_0_VM7_RANGE                       13:12
+#define GPIO_AF_VM_02_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AF_VM_02_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AF_VM_02_0_VM7_WOFFSET                     0x0
+#define GPIO_AF_VM_02_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_02_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_02_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_02_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AF_VM_02_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_02_0_VM8_SHIFT)
+#define GPIO_AF_VM_02_0_VM8_RANGE                       15:14
+#define GPIO_AF_VM_02_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AF_VM_02_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AF_VM_02_0_VM8_WOFFSET                     0x0
+#define GPIO_AF_VM_02_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_02_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_02_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_02_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_SCR_02_0
+#define GPIO_AF_SCR_02_0                        MK_ADDR_CONST(0x3114)
+#define GPIO_AF_SCR_02_0_SECURE                         0x0
+#define GPIO_AF_SCR_02_0_DUAL                   0x0
+#define GPIO_AF_SCR_02_0_SCR                    0
+#define GPIO_AF_SCR_02_0_SCRREG                         0
+#define GPIO_AF_SCR_02_0_WORD_COUNT                     0x1
+#define GPIO_AF_SCR_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AF_SCR_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AF_SCR_02_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AF_SCR_02_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AF_SCR_02_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_AF_SCR_02_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AF_SCR_02_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AF_SCR_02_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AF_SCR_02_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AF_SCR_02_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AF_SCR_02_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_AF_SCR_02_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AF_SCR_02_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AF_SCR_02_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AF_SCR_02_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AF_SCR_02_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AF_SCR_02_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_AF_SCR_02_0_SEC_REN_RANGE                  27:27
+#define GPIO_AF_SCR_02_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AF_SCR_02_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AF_SCR_02_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AF_SCR_02_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AF_SCR_02_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AF_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_AF_SCR_02_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AF_SCR_02_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AF_SCR_02_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AF_SCR_02_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AF_SCR_02_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AF_SCR_02_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AF_SCR_02_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_PR7_SHIFT)
+#define GPIO_AF_SCR_02_0_PR7_RANGE                      23:23
+#define GPIO_AF_SCR_02_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AF_SCR_02_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AF_SCR_02_0_PR7_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AF_SCR_02_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_PR6_SHIFT)
+#define GPIO_AF_SCR_02_0_PR6_RANGE                      22:22
+#define GPIO_AF_SCR_02_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AF_SCR_02_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AF_SCR_02_0_PR6_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AF_SCR_02_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_PR5_SHIFT)
+#define GPIO_AF_SCR_02_0_PR5_RANGE                      21:21
+#define GPIO_AF_SCR_02_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AF_SCR_02_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AF_SCR_02_0_PR5_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AF_SCR_02_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_PR4_SHIFT)
+#define GPIO_AF_SCR_02_0_PR4_RANGE                      20:20
+#define GPIO_AF_SCR_02_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AF_SCR_02_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AF_SCR_02_0_PR4_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AF_SCR_02_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_PR3_SHIFT)
+#define GPIO_AF_SCR_02_0_PR3_RANGE                      19:19
+#define GPIO_AF_SCR_02_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AF_SCR_02_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AF_SCR_02_0_PR3_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AF_SCR_02_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_PR2_SHIFT)
+#define GPIO_AF_SCR_02_0_PR2_RANGE                      18:18
+#define GPIO_AF_SCR_02_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AF_SCR_02_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AF_SCR_02_0_PR2_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AF_SCR_02_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_PR1_SHIFT)
+#define GPIO_AF_SCR_02_0_PR1_RANGE                      17:17
+#define GPIO_AF_SCR_02_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AF_SCR_02_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AF_SCR_02_0_PR1_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AF_SCR_02_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_PR0_SHIFT)
+#define GPIO_AF_SCR_02_0_PR0_RANGE                      16:16
+#define GPIO_AF_SCR_02_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AF_SCR_02_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AF_SCR_02_0_PR0_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AF_SCR_02_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G7W_SHIFT)
+#define GPIO_AF_SCR_02_0_G7W_RANGE                      15:15
+#define GPIO_AF_SCR_02_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AF_SCR_02_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AF_SCR_02_0_G7W_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AF_SCR_02_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G6W_SHIFT)
+#define GPIO_AF_SCR_02_0_G6W_RANGE                      14:14
+#define GPIO_AF_SCR_02_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AF_SCR_02_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AF_SCR_02_0_G6W_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AF_SCR_02_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G5W_SHIFT)
+#define GPIO_AF_SCR_02_0_G5W_RANGE                      13:13
+#define GPIO_AF_SCR_02_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AF_SCR_02_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AF_SCR_02_0_G5W_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AF_SCR_02_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G4W_SHIFT)
+#define GPIO_AF_SCR_02_0_G4W_RANGE                      12:12
+#define GPIO_AF_SCR_02_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AF_SCR_02_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AF_SCR_02_0_G4W_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AF_SCR_02_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G3W_SHIFT)
+#define GPIO_AF_SCR_02_0_G3W_RANGE                      11:11
+#define GPIO_AF_SCR_02_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AF_SCR_02_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AF_SCR_02_0_G3W_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AF_SCR_02_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G2W_SHIFT)
+#define GPIO_AF_SCR_02_0_G2W_RANGE                      10:10
+#define GPIO_AF_SCR_02_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AF_SCR_02_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AF_SCR_02_0_G2W_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AF_SCR_02_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G1W_SHIFT)
+#define GPIO_AF_SCR_02_0_G1W_RANGE                      9:9
+#define GPIO_AF_SCR_02_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AF_SCR_02_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AF_SCR_02_0_G1W_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AF_SCR_02_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G0W_SHIFT)
+#define GPIO_AF_SCR_02_0_G0W_RANGE                      8:8
+#define GPIO_AF_SCR_02_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AF_SCR_02_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AF_SCR_02_0_G0W_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AF_SCR_02_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G7R_SHIFT)
+#define GPIO_AF_SCR_02_0_G7R_RANGE                      7:7
+#define GPIO_AF_SCR_02_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AF_SCR_02_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AF_SCR_02_0_G7R_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AF_SCR_02_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G6R_SHIFT)
+#define GPIO_AF_SCR_02_0_G6R_RANGE                      6:6
+#define GPIO_AF_SCR_02_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AF_SCR_02_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AF_SCR_02_0_G6R_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AF_SCR_02_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G5R_SHIFT)
+#define GPIO_AF_SCR_02_0_G5R_RANGE                      5:5
+#define GPIO_AF_SCR_02_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AF_SCR_02_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AF_SCR_02_0_G5R_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AF_SCR_02_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G4R_SHIFT)
+#define GPIO_AF_SCR_02_0_G4R_RANGE                      4:4
+#define GPIO_AF_SCR_02_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AF_SCR_02_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AF_SCR_02_0_G4R_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AF_SCR_02_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G3R_SHIFT)
+#define GPIO_AF_SCR_02_0_G3R_RANGE                      3:3
+#define GPIO_AF_SCR_02_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AF_SCR_02_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AF_SCR_02_0_G3R_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AF_SCR_02_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G2R_SHIFT)
+#define GPIO_AF_SCR_02_0_G2R_RANGE                      2:2
+#define GPIO_AF_SCR_02_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AF_SCR_02_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AF_SCR_02_0_G2R_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AF_SCR_02_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G1R_SHIFT)
+#define GPIO_AF_SCR_02_0_G1R_RANGE                      1:1
+#define GPIO_AF_SCR_02_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AF_SCR_02_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AF_SCR_02_0_G1R_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_02_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AF_SCR_02_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_02_0_G0R_SHIFT)
+#define GPIO_AF_SCR_02_0_G0R_RANGE                      0:0
+#define GPIO_AF_SCR_02_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AF_SCR_02_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AF_SCR_02_0_G0R_WOFFSET                    0x0
+#define GPIO_AF_SCR_02_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_02_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_02_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_VM_03_0
+#define GPIO_AF_VM_03_0                 MK_ADDR_CONST(0x3118)
+#define GPIO_AF_VM_03_0_SECURE                  0x0
+#define GPIO_AF_VM_03_0_DUAL                    0x0
+#define GPIO_AF_VM_03_0_SCR                     GPIO_CTL3_VM_SCR_0
+#define GPIO_AF_VM_03_0_SCRREG                  GPIO_CTL3_VM_SCR_0
+#define GPIO_AF_VM_03_0_WORD_COUNT                      0x1
+#define GPIO_AF_VM_03_0_RESET_VAL                       MK_MASK_CONST(0xffff)
+#define GPIO_AF_VM_03_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AF_VM_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_AF_VM_03_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define GPIO_AF_VM_03_0_VM1_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AF_VM_03_0_VM1_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_03_0_VM1_SHIFT)
+#define GPIO_AF_VM_03_0_VM1_RANGE                       1:0
+#define GPIO_AF_VM_03_0_VM1_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AF_VM_03_0_VM1_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AF_VM_03_0_VM1_WOFFSET                     0x0
+#define GPIO_AF_VM_03_0_VM1_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_03_0_VM1_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_03_0_VM1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_03_0_VM2_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_AF_VM_03_0_VM2_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_03_0_VM2_SHIFT)
+#define GPIO_AF_VM_03_0_VM2_RANGE                       3:2
+#define GPIO_AF_VM_03_0_VM2_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AF_VM_03_0_VM2_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_AF_VM_03_0_VM2_WOFFSET                     0x0
+#define GPIO_AF_VM_03_0_VM2_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_03_0_VM2_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_03_0_VM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_03_0_VM3_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_AF_VM_03_0_VM3_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_03_0_VM3_SHIFT)
+#define GPIO_AF_VM_03_0_VM3_RANGE                       5:4
+#define GPIO_AF_VM_03_0_VM3_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_AF_VM_03_0_VM3_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_AF_VM_03_0_VM3_WOFFSET                     0x0
+#define GPIO_AF_VM_03_0_VM3_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_03_0_VM3_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_03_0_VM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_03_0_VM4_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_AF_VM_03_0_VM4_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_03_0_VM4_SHIFT)
+#define GPIO_AF_VM_03_0_VM4_RANGE                       7:6
+#define GPIO_AF_VM_03_0_VM4_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AF_VM_03_0_VM4_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_AF_VM_03_0_VM4_WOFFSET                     0x0
+#define GPIO_AF_VM_03_0_VM4_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_03_0_VM4_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_03_0_VM4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_03_0_VM5_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_AF_VM_03_0_VM5_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_03_0_VM5_SHIFT)
+#define GPIO_AF_VM_03_0_VM5_RANGE                       9:8
+#define GPIO_AF_VM_03_0_VM5_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_AF_VM_03_0_VM5_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_AF_VM_03_0_VM5_WOFFSET                     0x0
+#define GPIO_AF_VM_03_0_VM5_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_03_0_VM5_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_03_0_VM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_03_0_VM6_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_AF_VM_03_0_VM6_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_03_0_VM6_SHIFT)
+#define GPIO_AF_VM_03_0_VM6_RANGE                       11:10
+#define GPIO_AF_VM_03_0_VM6_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_AF_VM_03_0_VM6_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_AF_VM_03_0_VM6_WOFFSET                     0x0
+#define GPIO_AF_VM_03_0_VM6_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_03_0_VM6_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_03_0_VM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_03_0_VM7_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_AF_VM_03_0_VM7_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_03_0_VM7_SHIFT)
+#define GPIO_AF_VM_03_0_VM7_RANGE                       13:12
+#define GPIO_AF_VM_03_0_VM7_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_AF_VM_03_0_VM7_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_AF_VM_03_0_VM7_WOFFSET                     0x0
+#define GPIO_AF_VM_03_0_VM7_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_03_0_VM7_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_03_0_VM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_AF_VM_03_0_VM8_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_AF_VM_03_0_VM8_FIELD                       MK_FIELD_CONST(0x3, GPIO_AF_VM_03_0_VM8_SHIFT)
+#define GPIO_AF_VM_03_0_VM8_RANGE                       15:14
+#define GPIO_AF_VM_03_0_VM8_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_AF_VM_03_0_VM8_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_AF_VM_03_0_VM8_WOFFSET                     0x0
+#define GPIO_AF_VM_03_0_VM8_DEFAULT                     MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_03_0_VM8_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AF_VM_03_0_VM8_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM8_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_VM_03_0_VM8_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_SCR_03_0
+#define GPIO_AF_SCR_03_0                        MK_ADDR_CONST(0x311c)
+#define GPIO_AF_SCR_03_0_SECURE                         0x0
+#define GPIO_AF_SCR_03_0_DUAL                   0x0
+#define GPIO_AF_SCR_03_0_SCR                    0
+#define GPIO_AF_SCR_03_0_SCRREG                         0
+#define GPIO_AF_SCR_03_0_WORD_COUNT                     0x1
+#define GPIO_AF_SCR_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AF_SCR_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_AF_SCR_03_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define GPIO_AF_SCR_03_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define GPIO_AF_SCR_03_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_AF_SCR_03_0_SEC_LCK_RANGE                  29:29
+#define GPIO_AF_SCR_03_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define GPIO_AF_SCR_03_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define GPIO_AF_SCR_03_0_SEC_LCK_WOFFSET                        0x0
+#define GPIO_AF_SCR_03_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define GPIO_AF_SCR_03_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_AF_SCR_03_0_SEC_WEN_RANGE                  28:28
+#define GPIO_AF_SCR_03_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define GPIO_AF_SCR_03_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define GPIO_AF_SCR_03_0_SEC_WEN_WOFFSET                        0x0
+#define GPIO_AF_SCR_03_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define GPIO_AF_SCR_03_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_AF_SCR_03_0_SEC_REN_RANGE                  27:27
+#define GPIO_AF_SCR_03_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define GPIO_AF_SCR_03_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define GPIO_AF_SCR_03_0_SEC_REN_WOFFSET                        0x0
+#define GPIO_AF_SCR_03_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define GPIO_AF_SCR_03_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, GPIO_AF_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_AF_SCR_03_0_SEC_OWNER_RANGE                        26:24
+#define GPIO_AF_SCR_03_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define GPIO_AF_SCR_03_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define GPIO_AF_SCR_03_0_SEC_OWNER_WOFFSET                      0x0
+#define GPIO_AF_SCR_03_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define GPIO_AF_SCR_03_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define GPIO_AF_SCR_03_0_PR7_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_PR7_SHIFT)
+#define GPIO_AF_SCR_03_0_PR7_RANGE                      23:23
+#define GPIO_AF_SCR_03_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define GPIO_AF_SCR_03_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define GPIO_AF_SCR_03_0_PR7_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define GPIO_AF_SCR_03_0_PR6_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_PR6_SHIFT)
+#define GPIO_AF_SCR_03_0_PR6_RANGE                      22:22
+#define GPIO_AF_SCR_03_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define GPIO_AF_SCR_03_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define GPIO_AF_SCR_03_0_PR6_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define GPIO_AF_SCR_03_0_PR5_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_PR5_SHIFT)
+#define GPIO_AF_SCR_03_0_PR5_RANGE                      21:21
+#define GPIO_AF_SCR_03_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define GPIO_AF_SCR_03_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define GPIO_AF_SCR_03_0_PR5_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define GPIO_AF_SCR_03_0_PR4_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_PR4_SHIFT)
+#define GPIO_AF_SCR_03_0_PR4_RANGE                      20:20
+#define GPIO_AF_SCR_03_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define GPIO_AF_SCR_03_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define GPIO_AF_SCR_03_0_PR4_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define GPIO_AF_SCR_03_0_PR3_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_PR3_SHIFT)
+#define GPIO_AF_SCR_03_0_PR3_RANGE                      19:19
+#define GPIO_AF_SCR_03_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define GPIO_AF_SCR_03_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define GPIO_AF_SCR_03_0_PR3_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define GPIO_AF_SCR_03_0_PR2_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_PR2_SHIFT)
+#define GPIO_AF_SCR_03_0_PR2_RANGE                      18:18
+#define GPIO_AF_SCR_03_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define GPIO_AF_SCR_03_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define GPIO_AF_SCR_03_0_PR2_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define GPIO_AF_SCR_03_0_PR1_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_PR1_SHIFT)
+#define GPIO_AF_SCR_03_0_PR1_RANGE                      17:17
+#define GPIO_AF_SCR_03_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define GPIO_AF_SCR_03_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define GPIO_AF_SCR_03_0_PR1_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define GPIO_AF_SCR_03_0_PR0_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_PR0_SHIFT)
+#define GPIO_AF_SCR_03_0_PR0_RANGE                      16:16
+#define GPIO_AF_SCR_03_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define GPIO_AF_SCR_03_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define GPIO_AF_SCR_03_0_PR0_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define GPIO_AF_SCR_03_0_G7W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G7W_SHIFT)
+#define GPIO_AF_SCR_03_0_G7W_RANGE                      15:15
+#define GPIO_AF_SCR_03_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define GPIO_AF_SCR_03_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define GPIO_AF_SCR_03_0_G7W_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define GPIO_AF_SCR_03_0_G6W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G6W_SHIFT)
+#define GPIO_AF_SCR_03_0_G6W_RANGE                      14:14
+#define GPIO_AF_SCR_03_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define GPIO_AF_SCR_03_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define GPIO_AF_SCR_03_0_G6W_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define GPIO_AF_SCR_03_0_G5W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G5W_SHIFT)
+#define GPIO_AF_SCR_03_0_G5W_RANGE                      13:13
+#define GPIO_AF_SCR_03_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define GPIO_AF_SCR_03_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define GPIO_AF_SCR_03_0_G5W_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define GPIO_AF_SCR_03_0_G4W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G4W_SHIFT)
+#define GPIO_AF_SCR_03_0_G4W_RANGE                      12:12
+#define GPIO_AF_SCR_03_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define GPIO_AF_SCR_03_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define GPIO_AF_SCR_03_0_G4W_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define GPIO_AF_SCR_03_0_G3W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G3W_SHIFT)
+#define GPIO_AF_SCR_03_0_G3W_RANGE                      11:11
+#define GPIO_AF_SCR_03_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define GPIO_AF_SCR_03_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define GPIO_AF_SCR_03_0_G3W_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define GPIO_AF_SCR_03_0_G2W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G2W_SHIFT)
+#define GPIO_AF_SCR_03_0_G2W_RANGE                      10:10
+#define GPIO_AF_SCR_03_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define GPIO_AF_SCR_03_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define GPIO_AF_SCR_03_0_G2W_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define GPIO_AF_SCR_03_0_G1W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G1W_SHIFT)
+#define GPIO_AF_SCR_03_0_G1W_RANGE                      9:9
+#define GPIO_AF_SCR_03_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define GPIO_AF_SCR_03_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define GPIO_AF_SCR_03_0_G1W_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define GPIO_AF_SCR_03_0_G0W_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G0W_SHIFT)
+#define GPIO_AF_SCR_03_0_G0W_RANGE                      8:8
+#define GPIO_AF_SCR_03_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define GPIO_AF_SCR_03_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define GPIO_AF_SCR_03_0_G0W_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define GPIO_AF_SCR_03_0_G7R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G7R_SHIFT)
+#define GPIO_AF_SCR_03_0_G7R_RANGE                      7:7
+#define GPIO_AF_SCR_03_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define GPIO_AF_SCR_03_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define GPIO_AF_SCR_03_0_G7R_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_AF_SCR_03_0_G6R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G6R_SHIFT)
+#define GPIO_AF_SCR_03_0_G6R_RANGE                      6:6
+#define GPIO_AF_SCR_03_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_AF_SCR_03_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_AF_SCR_03_0_G6R_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AF_SCR_03_0_G5R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G5R_SHIFT)
+#define GPIO_AF_SCR_03_0_G5R_RANGE                      5:5
+#define GPIO_AF_SCR_03_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AF_SCR_03_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AF_SCR_03_0_G5R_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define GPIO_AF_SCR_03_0_G4R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G4R_SHIFT)
+#define GPIO_AF_SCR_03_0_G4R_RANGE                      4:4
+#define GPIO_AF_SCR_03_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define GPIO_AF_SCR_03_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define GPIO_AF_SCR_03_0_G4R_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define GPIO_AF_SCR_03_0_G3R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G3R_SHIFT)
+#define GPIO_AF_SCR_03_0_G3R_RANGE                      3:3
+#define GPIO_AF_SCR_03_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define GPIO_AF_SCR_03_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define GPIO_AF_SCR_03_0_G3R_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define GPIO_AF_SCR_03_0_G2R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G2R_SHIFT)
+#define GPIO_AF_SCR_03_0_G2R_RANGE                      2:2
+#define GPIO_AF_SCR_03_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define GPIO_AF_SCR_03_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define GPIO_AF_SCR_03_0_G2R_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define GPIO_AF_SCR_03_0_G1R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G1R_SHIFT)
+#define GPIO_AF_SCR_03_0_G1R_RANGE                      1:1
+#define GPIO_AF_SCR_03_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define GPIO_AF_SCR_03_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define GPIO_AF_SCR_03_0_G1R_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_AF_SCR_03_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AF_SCR_03_0_G0R_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_SCR_03_0_G0R_SHIFT)
+#define GPIO_AF_SCR_03_0_G0R_RANGE                      0:0
+#define GPIO_AF_SCR_03_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AF_SCR_03_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AF_SCR_03_0_G0R_WOFFSET                    0x0
+#define GPIO_AF_SCR_03_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_SCR_03_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_AF_SCR_03_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x3120
+
+// Reserved address 0x3124
+
+// Reserved address 0x3128
+
+// Reserved address 0x312c
+
+// Reserved address 0x3130
+
+// Reserved address 0x3134
+
+// Reserved address 0x3138
+
+// Reserved address 0x313c
+
+// Register GPIO_CTL3_VM_SCR_0
+#define GPIO_CTL3_VM_SCR_0                      MK_ADDR_CONST(0x3800)
+#define GPIO_CTL3_VM_SCR_0_SECURE                       0x0
+#define GPIO_CTL3_VM_SCR_0_DUAL                         0x0
+#define GPIO_CTL3_VM_SCR_0_SCR                  0
+#define GPIO_CTL3_VM_SCR_0_SCRREG                       0
+#define GPIO_CTL3_VM_SCR_0_WORD_COUNT                   0x1
+#define GPIO_CTL3_VM_SCR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL3_VM_SCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL3_VM_SCR_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL3_VM_SCR_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
+#define GPIO_CTL3_VM_SCR_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_SEC_LCK_RANGE                        29:29
+#define GPIO_CTL3_VM_SCR_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
+#define GPIO_CTL3_VM_SCR_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
+#define GPIO_CTL3_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
+#define GPIO_CTL3_VM_SCR_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
+#define GPIO_CTL3_VM_SCR_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_SEC_WEN_RANGE                        28:28
+#define GPIO_CTL3_VM_SCR_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
+#define GPIO_CTL3_VM_SCR_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
+#define GPIO_CTL3_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
+#define GPIO_CTL3_VM_SCR_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
+#define GPIO_CTL3_VM_SCR_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_SEC_REN_RANGE                        27:27
+#define GPIO_CTL3_VM_SCR_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
+#define GPIO_CTL3_VM_SCR_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
+#define GPIO_CTL3_VM_SCR_0_SEC_REN_WOFFSET                      0x0
+#define GPIO_CTL3_VM_SCR_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
+#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, GPIO_CTL3_VM_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_RANGE                      26:24
+#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
+#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
+#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
+#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
+#define GPIO_CTL3_VM_SCR_0_PR7_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR7_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_PR7_RANGE                    23:23
+#define GPIO_CTL3_VM_SCR_0_PR7_MSB                      MK_SHIFT_CONST(23)
+#define GPIO_CTL3_VM_SCR_0_PR7_LSB                      MK_SHIFT_CONST(23)
+#define GPIO_CTL3_VM_SCR_0_PR7_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
+#define GPIO_CTL3_VM_SCR_0_PR6_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR6_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_PR6_RANGE                    22:22
+#define GPIO_CTL3_VM_SCR_0_PR6_MSB                      MK_SHIFT_CONST(22)
+#define GPIO_CTL3_VM_SCR_0_PR6_LSB                      MK_SHIFT_CONST(22)
+#define GPIO_CTL3_VM_SCR_0_PR6_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
+#define GPIO_CTL3_VM_SCR_0_PR5_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR5_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_PR5_RANGE                    21:21
+#define GPIO_CTL3_VM_SCR_0_PR5_MSB                      MK_SHIFT_CONST(21)
+#define GPIO_CTL3_VM_SCR_0_PR5_LSB                      MK_SHIFT_CONST(21)
+#define GPIO_CTL3_VM_SCR_0_PR5_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
+#define GPIO_CTL3_VM_SCR_0_PR4_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR4_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_PR4_RANGE                    20:20
+#define GPIO_CTL3_VM_SCR_0_PR4_MSB                      MK_SHIFT_CONST(20)
+#define GPIO_CTL3_VM_SCR_0_PR4_LSB                      MK_SHIFT_CONST(20)
+#define GPIO_CTL3_VM_SCR_0_PR4_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
+#define GPIO_CTL3_VM_SCR_0_PR3_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR3_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_PR3_RANGE                    19:19
+#define GPIO_CTL3_VM_SCR_0_PR3_MSB                      MK_SHIFT_CONST(19)
+#define GPIO_CTL3_VM_SCR_0_PR3_LSB                      MK_SHIFT_CONST(19)
+#define GPIO_CTL3_VM_SCR_0_PR3_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
+#define GPIO_CTL3_VM_SCR_0_PR2_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR2_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_PR2_RANGE                    18:18
+#define GPIO_CTL3_VM_SCR_0_PR2_MSB                      MK_SHIFT_CONST(18)
+#define GPIO_CTL3_VM_SCR_0_PR2_LSB                      MK_SHIFT_CONST(18)
+#define GPIO_CTL3_VM_SCR_0_PR2_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
+#define GPIO_CTL3_VM_SCR_0_PR1_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR1_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_PR1_RANGE                    17:17
+#define GPIO_CTL3_VM_SCR_0_PR1_MSB                      MK_SHIFT_CONST(17)
+#define GPIO_CTL3_VM_SCR_0_PR1_LSB                      MK_SHIFT_CONST(17)
+#define GPIO_CTL3_VM_SCR_0_PR1_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
+#define GPIO_CTL3_VM_SCR_0_PR0_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_PR0_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_PR0_RANGE                    16:16
+#define GPIO_CTL3_VM_SCR_0_PR0_MSB                      MK_SHIFT_CONST(16)
+#define GPIO_CTL3_VM_SCR_0_PR0_LSB                      MK_SHIFT_CONST(16)
+#define GPIO_CTL3_VM_SCR_0_PR0_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
+#define GPIO_CTL3_VM_SCR_0_G7W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G7W_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_G7W_RANGE                    15:15
+#define GPIO_CTL3_VM_SCR_0_G7W_MSB                      MK_SHIFT_CONST(15)
+#define GPIO_CTL3_VM_SCR_0_G7W_LSB                      MK_SHIFT_CONST(15)
+#define GPIO_CTL3_VM_SCR_0_G7W_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
+#define GPIO_CTL3_VM_SCR_0_G6W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G6W_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_G6W_RANGE                    14:14
+#define GPIO_CTL3_VM_SCR_0_G6W_MSB                      MK_SHIFT_CONST(14)
+#define GPIO_CTL3_VM_SCR_0_G6W_LSB                      MK_SHIFT_CONST(14)
+#define GPIO_CTL3_VM_SCR_0_G6W_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
+#define GPIO_CTL3_VM_SCR_0_G5W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G5W_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_G5W_RANGE                    13:13
+#define GPIO_CTL3_VM_SCR_0_G5W_MSB                      MK_SHIFT_CONST(13)
+#define GPIO_CTL3_VM_SCR_0_G5W_LSB                      MK_SHIFT_CONST(13)
+#define GPIO_CTL3_VM_SCR_0_G5W_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
+#define GPIO_CTL3_VM_SCR_0_G4W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G4W_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_G4W_RANGE                    12:12
+#define GPIO_CTL3_VM_SCR_0_G4W_MSB                      MK_SHIFT_CONST(12)
+#define GPIO_CTL3_VM_SCR_0_G4W_LSB                      MK_SHIFT_CONST(12)
+#define GPIO_CTL3_VM_SCR_0_G4W_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
+#define GPIO_CTL3_VM_SCR_0_G3W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G3W_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_G3W_RANGE                    11:11
+#define GPIO_CTL3_VM_SCR_0_G3W_MSB                      MK_SHIFT_CONST(11)
+#define GPIO_CTL3_VM_SCR_0_G3W_LSB                      MK_SHIFT_CONST(11)
+#define GPIO_CTL3_VM_SCR_0_G3W_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
+#define GPIO_CTL3_VM_SCR_0_G2W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G2W_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_G2W_RANGE                    10:10
+#define GPIO_CTL3_VM_SCR_0_G2W_MSB                      MK_SHIFT_CONST(10)
+#define GPIO_CTL3_VM_SCR_0_G2W_LSB                      MK_SHIFT_CONST(10)
+#define GPIO_CTL3_VM_SCR_0_G2W_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
+#define GPIO_CTL3_VM_SCR_0_G1W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G1W_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_G1W_RANGE                    9:9
+#define GPIO_CTL3_VM_SCR_0_G1W_MSB                      MK_SHIFT_CONST(9)
+#define GPIO_CTL3_VM_SCR_0_G1W_LSB                      MK_SHIFT_CONST(9)
+#define GPIO_CTL3_VM_SCR_0_G1W_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
+#define GPIO_CTL3_VM_SCR_0_G0W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G0W_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_G0W_RANGE                    8:8
+#define GPIO_CTL3_VM_SCR_0_G0W_MSB                      MK_SHIFT_CONST(8)
+#define GPIO_CTL3_VM_SCR_0_G0W_LSB                      MK_SHIFT_CONST(8)
+#define GPIO_CTL3_VM_SCR_0_G0W_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
+#define GPIO_CTL3_VM_SCR_0_G7R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G7R_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_G7R_RANGE                    7:7
+#define GPIO_CTL3_VM_SCR_0_G7R_MSB                      MK_SHIFT_CONST(7)
+#define GPIO_CTL3_VM_SCR_0_G7R_LSB                      MK_SHIFT_CONST(7)
+#define GPIO_CTL3_VM_SCR_0_G7R_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
+#define GPIO_CTL3_VM_SCR_0_G6R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G6R_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_G6R_RANGE                    6:6
+#define GPIO_CTL3_VM_SCR_0_G6R_MSB                      MK_SHIFT_CONST(6)
+#define GPIO_CTL3_VM_SCR_0_G6R_LSB                      MK_SHIFT_CONST(6)
+#define GPIO_CTL3_VM_SCR_0_G6R_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
+#define GPIO_CTL3_VM_SCR_0_G5R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G5R_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_G5R_RANGE                    5:5
+#define GPIO_CTL3_VM_SCR_0_G5R_MSB                      MK_SHIFT_CONST(5)
+#define GPIO_CTL3_VM_SCR_0_G5R_LSB                      MK_SHIFT_CONST(5)
+#define GPIO_CTL3_VM_SCR_0_G5R_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
+#define GPIO_CTL3_VM_SCR_0_G4R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G4R_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_G4R_RANGE                    4:4
+#define GPIO_CTL3_VM_SCR_0_G4R_MSB                      MK_SHIFT_CONST(4)
+#define GPIO_CTL3_VM_SCR_0_G4R_LSB                      MK_SHIFT_CONST(4)
+#define GPIO_CTL3_VM_SCR_0_G4R_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
+#define GPIO_CTL3_VM_SCR_0_G3R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G3R_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_G3R_RANGE                    3:3
+#define GPIO_CTL3_VM_SCR_0_G3R_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_CTL3_VM_SCR_0_G3R_LSB                      MK_SHIFT_CONST(3)
+#define GPIO_CTL3_VM_SCR_0_G3R_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_CTL3_VM_SCR_0_G2R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G2R_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_G2R_RANGE                    2:2
+#define GPIO_CTL3_VM_SCR_0_G2R_MSB                      MK_SHIFT_CONST(2)
+#define GPIO_CTL3_VM_SCR_0_G2R_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_CTL3_VM_SCR_0_G2R_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
+#define GPIO_CTL3_VM_SCR_0_G1R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G1R_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_G1R_RANGE                    1:1
+#define GPIO_CTL3_VM_SCR_0_G1R_MSB                      MK_SHIFT_CONST(1)
+#define GPIO_CTL3_VM_SCR_0_G1R_LSB                      MK_SHIFT_CONST(1)
+#define GPIO_CTL3_VM_SCR_0_G1R_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_VM_SCR_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CTL3_VM_SCR_0_G0R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL3_VM_SCR_0_G0R_SHIFT)
+#define GPIO_CTL3_VM_SCR_0_G0R_RANGE                    0:0
+#define GPIO_CTL3_VM_SCR_0_G0R_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CTL3_VM_SCR_0_G0R_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CTL3_VM_SCR_0_G0R_WOFFSET                  0x0
+#define GPIO_CTL3_VM_SCR_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL3_VM_SCR_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0                     MK_ADDR_CONST(0x3804)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SCRREG                      0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_MSB                     MK_SHIFT_CONST(23)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_LSB                     MK_SHIFT_CONST(23)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_MSB                     MK_SHIFT_CONST(22)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_LSB                     MK_SHIFT_CONST(22)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_MSB                     MK_SHIFT_CONST(21)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_LSB                     MK_SHIFT_CONST(21)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_MSB                     MK_SHIFT_CONST(20)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_LSB                     MK_SHIFT_CONST(20)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_MSB                     MK_SHIFT_CONST(19)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_LSB                     MK_SHIFT_CONST(19)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_MSB                     MK_SHIFT_CONST(18)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_LSB                     MK_SHIFT_CONST(18)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_MSB                     MK_SHIFT_CONST(17)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_LSB                     MK_SHIFT_CONST(17)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_MSB                     MK_SHIFT_CONST(16)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_LSB                     MK_SHIFT_CONST(16)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_MSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_LSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_MSB                     MK_SHIFT_CONST(14)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_LSB                     MK_SHIFT_CONST(14)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_MSB                     MK_SHIFT_CONST(13)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_LSB                     MK_SHIFT_CONST(13)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_MSB                     MK_SHIFT_CONST(12)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_LSB                     MK_SHIFT_CONST(12)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_MSB                     MK_SHIFT_CONST(11)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_LSB                     MK_SHIFT_CONST(11)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_MSB                     MK_SHIFT_CONST(10)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_LSB                     MK_SHIFT_CONST(10)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_MSB                     MK_SHIFT_CONST(9)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_LSB                     MK_SHIFT_CONST(9)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_MSB                     MK_SHIFT_CONST(8)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_LSB                     MK_SHIFT_CONST(8)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_MSB                     MK_SHIFT_CONST(6)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_LSB                     MK_SHIFT_CONST(6)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_LSB                     MK_SHIFT_CONST(5)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_LSB                     MK_SHIFT_CONST(3)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_MSB                     MK_SHIFT_CONST(2)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_MSB                     MK_SHIFT_CONST(1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_LSB                     MK_SHIFT_CONST(1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_MSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL3_INTERRUPT_STATUS_VM_0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0                 MK_ADDR_CONST(0x3808)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SECURE                  0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_DUAL                    0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SCRREG                  GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  MK_FIELD_CONST(0xff, GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL3_SCR_0
+#define GPIO_CTL3_SCR_0                 MK_ADDR_CONST(0x380c)
+#define GPIO_CTL3_SCR_0_SECURE                  0x0
+#define GPIO_CTL3_SCR_0_DUAL                    0x0
+#define GPIO_CTL3_SCR_0_SCR                     0
+#define GPIO_CTL3_SCR_0_SCRREG                  0
+#define GPIO_CTL3_SCR_0_WORD_COUNT                      0x1
+#define GPIO_CTL3_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL3_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL3_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL3_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_CTL3_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL3_SCR_0_SEC_LCK_RANGE                   29:29
+#define GPIO_CTL3_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_CTL3_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_CTL3_SCR_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_CTL3_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_CTL3_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL3_SCR_0_SEC_WEN_RANGE                   28:28
+#define GPIO_CTL3_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_CTL3_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_CTL3_SCR_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_CTL3_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_CTL3_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL3_SCR_0_SEC_REN_RANGE                   27:27
+#define GPIO_CTL3_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_CTL3_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_CTL3_SCR_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_CTL3_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_CTL3_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_CTL3_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL3_SCR_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_CTL3_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_CTL3_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_CTL3_SCR_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_CTL3_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_CTL3_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_CTL3_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR7_SHIFT)
+#define GPIO_CTL3_SCR_0_PR7_RANGE                       23:23
+#define GPIO_CTL3_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_CTL3_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_CTL3_SCR_0_PR7_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_CTL3_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR6_SHIFT)
+#define GPIO_CTL3_SCR_0_PR6_RANGE                       22:22
+#define GPIO_CTL3_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_CTL3_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_CTL3_SCR_0_PR6_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_CTL3_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR5_SHIFT)
+#define GPIO_CTL3_SCR_0_PR5_RANGE                       21:21
+#define GPIO_CTL3_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_CTL3_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_CTL3_SCR_0_PR5_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_CTL3_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR4_SHIFT)
+#define GPIO_CTL3_SCR_0_PR4_RANGE                       20:20
+#define GPIO_CTL3_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_CTL3_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_CTL3_SCR_0_PR4_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_CTL3_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR3_SHIFT)
+#define GPIO_CTL3_SCR_0_PR3_RANGE                       19:19
+#define GPIO_CTL3_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_CTL3_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_CTL3_SCR_0_PR3_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_CTL3_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR2_SHIFT)
+#define GPIO_CTL3_SCR_0_PR2_RANGE                       18:18
+#define GPIO_CTL3_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_CTL3_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_CTL3_SCR_0_PR2_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_CTL3_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR1_SHIFT)
+#define GPIO_CTL3_SCR_0_PR1_RANGE                       17:17
+#define GPIO_CTL3_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_CTL3_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_CTL3_SCR_0_PR1_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_CTL3_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_PR0_SHIFT)
+#define GPIO_CTL3_SCR_0_PR0_RANGE                       16:16
+#define GPIO_CTL3_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_CTL3_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_CTL3_SCR_0_PR0_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_CTL3_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G7W_SHIFT)
+#define GPIO_CTL3_SCR_0_G7W_RANGE                       15:15
+#define GPIO_CTL3_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_CTL3_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_CTL3_SCR_0_G7W_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_CTL3_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G6W_SHIFT)
+#define GPIO_CTL3_SCR_0_G6W_RANGE                       14:14
+#define GPIO_CTL3_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_CTL3_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_CTL3_SCR_0_G6W_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_CTL3_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G5W_SHIFT)
+#define GPIO_CTL3_SCR_0_G5W_RANGE                       13:13
+#define GPIO_CTL3_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_CTL3_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_CTL3_SCR_0_G5W_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_CTL3_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G4W_SHIFT)
+#define GPIO_CTL3_SCR_0_G4W_RANGE                       12:12
+#define GPIO_CTL3_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_CTL3_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_CTL3_SCR_0_G4W_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_CTL3_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G3W_SHIFT)
+#define GPIO_CTL3_SCR_0_G3W_RANGE                       11:11
+#define GPIO_CTL3_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_CTL3_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_CTL3_SCR_0_G3W_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_CTL3_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G2W_SHIFT)
+#define GPIO_CTL3_SCR_0_G2W_RANGE                       10:10
+#define GPIO_CTL3_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_CTL3_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_CTL3_SCR_0_G2W_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_CTL3_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G1W_SHIFT)
+#define GPIO_CTL3_SCR_0_G1W_RANGE                       9:9
+#define GPIO_CTL3_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_CTL3_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_CTL3_SCR_0_G1W_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_CTL3_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G0W_SHIFT)
+#define GPIO_CTL3_SCR_0_G0W_RANGE                       8:8
+#define GPIO_CTL3_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_CTL3_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_CTL3_SCR_0_G0W_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_CTL3_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G7R_SHIFT)
+#define GPIO_CTL3_SCR_0_G7R_RANGE                       7:7
+#define GPIO_CTL3_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_CTL3_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_CTL3_SCR_0_G7R_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_CTL3_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G6R_SHIFT)
+#define GPIO_CTL3_SCR_0_G6R_RANGE                       6:6
+#define GPIO_CTL3_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_CTL3_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_CTL3_SCR_0_G6R_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_CTL3_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G5R_SHIFT)
+#define GPIO_CTL3_SCR_0_G5R_RANGE                       5:5
+#define GPIO_CTL3_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_CTL3_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_CTL3_SCR_0_G5R_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_CTL3_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G4R_SHIFT)
+#define GPIO_CTL3_SCR_0_G4R_RANGE                       4:4
+#define GPIO_CTL3_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_CTL3_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_CTL3_SCR_0_G4R_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_CTL3_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G3R_SHIFT)
+#define GPIO_CTL3_SCR_0_G3R_RANGE                       3:3
+#define GPIO_CTL3_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_CTL3_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_CTL3_SCR_0_G3R_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_CTL3_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G2R_SHIFT)
+#define GPIO_CTL3_SCR_0_G2R_RANGE                       2:2
+#define GPIO_CTL3_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_CTL3_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_CTL3_SCR_0_G2R_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_CTL3_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G1R_SHIFT)
+#define GPIO_CTL3_SCR_0_G1R_RANGE                       1:1
+#define GPIO_CTL3_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_CTL3_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_CTL3_SCR_0_G1R_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL3_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_CTL3_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL3_SCR_0_G0R_SHIFT)
+#define GPIO_CTL3_SCR_0_G0R_RANGE                       0:0
+#define GPIO_CTL3_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_CTL3_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_CTL3_SCR_0_G0R_WOFFSET                     0x0
+#define GPIO_CTL3_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL3_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL3_ICG_EN_OVERRIDE_0
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0                     MK_ADDR_CONST(0x3810)
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SECURE                      0x0
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_DUAL                        0x0
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL3_SCR_0
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SCRREG                      GPIO_CTL3_SCR_0
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CTL3_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INT0_ROUTE_MAPPING_0
+#define GPIO_K_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3814)
+#define GPIO_K_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_K_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_K_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
+#define GPIO_K_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
+#define GPIO_K_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_K_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_K_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_K_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INT1_ROUTE_MAPPING_0
+#define GPIO_K_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3818)
+#define GPIO_K_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_K_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_K_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
+#define GPIO_K_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
+#define GPIO_K_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_K_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_K_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_K_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INT2_ROUTE_MAPPING_0
+#define GPIO_K_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x381c)
+#define GPIO_K_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_K_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_K_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
+#define GPIO_K_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
+#define GPIO_K_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_K_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_K_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_K_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INT3_ROUTE_MAPPING_0
+#define GPIO_K_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3820)
+#define GPIO_K_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_K_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_K_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
+#define GPIO_K_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
+#define GPIO_K_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_K_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_K_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_K_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INT4_ROUTE_MAPPING_0
+#define GPIO_K_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3824)
+#define GPIO_K_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_K_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_K_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
+#define GPIO_K_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
+#define GPIO_K_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_K_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_K_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_K_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INT5_ROUTE_MAPPING_0
+#define GPIO_K_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3828)
+#define GPIO_K_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_K_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_K_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
+#define GPIO_K_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
+#define GPIO_K_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_K_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_K_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_K_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INT6_ROUTE_MAPPING_0
+#define GPIO_K_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x382c)
+#define GPIO_K_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_K_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_K_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
+#define GPIO_K_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
+#define GPIO_K_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_K_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_K_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_K_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INT7_ROUTE_MAPPING_0
+#define GPIO_K_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3830)
+#define GPIO_K_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_K_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_K_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
+#define GPIO_K_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
+#define GPIO_K_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_K_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_K_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_K_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INT0_ROUTE_MAPPING_0
+#define GPIO_L_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3834)
+#define GPIO_L_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_L_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_L_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
+#define GPIO_L_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
+#define GPIO_L_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_L_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_L_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_L_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_L_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_RANGE                   3:0
+#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_L_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INT1_ROUTE_MAPPING_0
+#define GPIO_L_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3838)
+#define GPIO_L_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_L_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_L_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
+#define GPIO_L_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
+#define GPIO_L_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_L_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_L_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_L_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_L_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_RANGE                   3:0
+#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_L_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INT2_ROUTE_MAPPING_0
+#define GPIO_L_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x383c)
+#define GPIO_L_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_L_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_L_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
+#define GPIO_L_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
+#define GPIO_L_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_L_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_L_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_L_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_L_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_RANGE                   3:0
+#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_L_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INT3_ROUTE_MAPPING_0
+#define GPIO_L_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3840)
+#define GPIO_L_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_L_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_L_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
+#define GPIO_L_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
+#define GPIO_L_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_L_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_L_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_L_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_L_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_RANGE                   3:0
+#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_L_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INT4_ROUTE_MAPPING_0
+#define GPIO_L_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3844)
+#define GPIO_L_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_L_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_L_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
+#define GPIO_L_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
+#define GPIO_L_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_L_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_L_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_L_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_L_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_RANGE                   3:0
+#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_L_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INT5_ROUTE_MAPPING_0
+#define GPIO_L_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3848)
+#define GPIO_L_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_L_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_L_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
+#define GPIO_L_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
+#define GPIO_L_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_L_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_L_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_L_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_L_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_RANGE                   3:0
+#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_L_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INT6_ROUTE_MAPPING_0
+#define GPIO_L_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x384c)
+#define GPIO_L_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_L_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_L_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
+#define GPIO_L_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
+#define GPIO_L_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_L_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_L_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_L_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_L_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_RANGE                   3:0
+#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_L_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INT7_ROUTE_MAPPING_0
+#define GPIO_L_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x3850)
+#define GPIO_L_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_L_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_L_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL3_SCR_0
+#define GPIO_L_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL3_SCR_0
+#define GPIO_L_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_L_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_L_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_L_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_L_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_RANGE                   3:0
+#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_L_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INT0_ROUTE_MAPPING_0
+#define GPIO_AG_INT0_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3854)
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_RANGE                  7:0
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INT1_ROUTE_MAPPING_0
+#define GPIO_AG_INT1_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3858)
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_RANGE                  7:0
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INT2_ROUTE_MAPPING_0
+#define GPIO_AG_INT2_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x385c)
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_RANGE                  7:0
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INT3_ROUTE_MAPPING_0
+#define GPIO_AG_INT3_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3860)
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_RANGE                  7:0
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INT4_ROUTE_MAPPING_0
+#define GPIO_AG_INT4_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3864)
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_RANGE                  7:0
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INT5_ROUTE_MAPPING_0
+#define GPIO_AG_INT5_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3868)
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_RANGE                  7:0
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INT6_ROUTE_MAPPING_0
+#define GPIO_AG_INT6_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x386c)
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_RANGE                  7:0
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INT7_ROUTE_MAPPING_0
+#define GPIO_AG_INT7_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3870)
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xff, GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_RANGE                  7:0
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INT0_ROUTE_MAPPING_0
+#define GPIO_AE_INT0_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3874)
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0x3, GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_RANGE                  1:0
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AE_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INT1_ROUTE_MAPPING_0
+#define GPIO_AE_INT1_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3878)
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0x3, GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_RANGE                  1:0
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AE_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INT2_ROUTE_MAPPING_0
+#define GPIO_AE_INT2_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x387c)
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0x3, GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_RANGE                  1:0
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AE_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INT3_ROUTE_MAPPING_0
+#define GPIO_AE_INT3_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3880)
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0x3, GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_RANGE                  1:0
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AE_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INT4_ROUTE_MAPPING_0
+#define GPIO_AE_INT4_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3884)
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0x3, GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_RANGE                  1:0
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AE_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INT5_ROUTE_MAPPING_0
+#define GPIO_AE_INT5_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3888)
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0x3, GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_RANGE                  1:0
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AE_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INT6_ROUTE_MAPPING_0
+#define GPIO_AE_INT6_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x388c)
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0x3, GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_RANGE                  1:0
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AE_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INT7_ROUTE_MAPPING_0
+#define GPIO_AE_INT7_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3890)
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0x3, GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_RANGE                  1:0
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AE_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INT0_ROUTE_MAPPING_0
+#define GPIO_AF_INT0_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3894)
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_RANGE                  3:0
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AF_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INT1_ROUTE_MAPPING_0
+#define GPIO_AF_INT1_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x3898)
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_RANGE                  3:0
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AF_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INT2_ROUTE_MAPPING_0
+#define GPIO_AF_INT2_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x389c)
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_RANGE                  3:0
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AF_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INT3_ROUTE_MAPPING_0
+#define GPIO_AF_INT3_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x38a0)
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_RANGE                  3:0
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AF_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INT4_ROUTE_MAPPING_0
+#define GPIO_AF_INT4_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x38a4)
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_RANGE                  3:0
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AF_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INT5_ROUTE_MAPPING_0
+#define GPIO_AF_INT5_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x38a8)
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_RANGE                  3:0
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AF_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INT6_ROUTE_MAPPING_0
+#define GPIO_AF_INT6_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x38ac)
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_RANGE                  3:0
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AF_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INT7_ROUTE_MAPPING_0
+#define GPIO_AF_INT7_ROUTE_MAPPING_0                    MK_ADDR_CONST(0x38b0)
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_SECURE                     0x0
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_DUAL                       0x0
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_SCR                        GPIO_CTL3_SCR_0
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_SCRREG                     GPIO_CTL3_SCR_0
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_WORD_COUNT                         0x1
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_WRITE_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_FIELD                  MK_FIELD_CONST(0xf, GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_RANGE                  3:0
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_MSB                    MK_SHIFT_CONST(3)
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                        0x0
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AF_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL3_SPARE_0
+#define GPIO_CTL3_SPARE_0                       MK_ADDR_CONST(0x38b4)
+#define GPIO_CTL3_SPARE_0_SECURE                        0x0
+#define GPIO_CTL3_SPARE_0_DUAL                  0x0
+#define GPIO_CTL3_SPARE_0_SCR                   0
+#define GPIO_CTL3_SPARE_0_SCRREG                        0
+#define GPIO_CTL3_SPARE_0_WORD_COUNT                    0x1
+#define GPIO_CTL3_SPARE_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SPARE_0_RESET_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL3_SPARE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SPARE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SPARE_0_READ_MASK                     MK_MASK_CONST(0xffff)
+#define GPIO_CTL3_SPARE_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL3_SPARE_0_SPARE_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_CTL3_SPARE_0_SPARE_FIELD                   MK_FIELD_CONST(0xffff, GPIO_CTL3_SPARE_0_SPARE_SHIFT)
+#define GPIO_CTL3_SPARE_0_SPARE_RANGE                   15:0
+#define GPIO_CTL3_SPARE_0_SPARE_MSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL3_SPARE_0_SPARE_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL3_SPARE_0_SPARE_WOFFSET                 0x0
+#define GPIO_CTL3_SPARE_0_SPARE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SPARE_0_SPARE_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL3_SPARE_0_SPARE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SPARE_0_SPARE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SPARE_0_SPARE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL3_SPARE_0_SPARE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_VM_00_0
+#define GPIO_G_VM_00_0                  MK_ADDR_CONST(0x4000)
+#define GPIO_G_VM_00_0_SECURE                   0x0
+#define GPIO_G_VM_00_0_DUAL                     0x0
+#define GPIO_G_VM_00_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_G_VM_00_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_G_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_G_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_G_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM1_SHIFT)
+#define GPIO_G_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_G_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_G_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_G_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_G_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_G_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM2_SHIFT)
+#define GPIO_G_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_G_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_G_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_G_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_G_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_G_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM3_SHIFT)
+#define GPIO_G_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_G_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_G_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_G_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_G_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_G_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM4_SHIFT)
+#define GPIO_G_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_G_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_G_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_G_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_G_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_G_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM5_SHIFT)
+#define GPIO_G_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_G_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_G_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_G_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_G_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_G_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM6_SHIFT)
+#define GPIO_G_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_G_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_G_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_G_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_G_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_G_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM7_SHIFT)
+#define GPIO_G_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_G_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_G_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_G_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_G_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_G_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_00_0_VM8_SHIFT)
+#define GPIO_G_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_G_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_G_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_G_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_G_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_SCR_00_0
+#define GPIO_G_SCR_00_0                 MK_ADDR_CONST(0x4004)
+#define GPIO_G_SCR_00_0_SECURE                  0x0
+#define GPIO_G_SCR_00_0_DUAL                    0x0
+#define GPIO_G_SCR_00_0_SCR                     0
+#define GPIO_G_SCR_00_0_SCRREG                  0
+#define GPIO_G_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_G_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_G_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_G_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_G_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_G_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_G_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_G_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_G_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_G_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_G_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_G_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_G_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_G_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_G_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_G_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_G_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_G_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_G_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR7_SHIFT)
+#define GPIO_G_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_G_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR6_SHIFT)
+#define GPIO_G_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_G_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR5_SHIFT)
+#define GPIO_G_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_G_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR4_SHIFT)
+#define GPIO_G_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_G_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR3_SHIFT)
+#define GPIO_G_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_G_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR2_SHIFT)
+#define GPIO_G_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_G_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR1_SHIFT)
+#define GPIO_G_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_G_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_PR0_SHIFT)
+#define GPIO_G_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_G_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G7W_SHIFT)
+#define GPIO_G_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_G_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G6W_SHIFT)
+#define GPIO_G_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_G_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G5W_SHIFT)
+#define GPIO_G_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_G_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G4W_SHIFT)
+#define GPIO_G_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_G_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G3W_SHIFT)
+#define GPIO_G_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_G_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G2W_SHIFT)
+#define GPIO_G_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_G_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G1W_SHIFT)
+#define GPIO_G_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_G_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G0W_SHIFT)
+#define GPIO_G_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_G_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G7R_SHIFT)
+#define GPIO_G_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_G_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G6R_SHIFT)
+#define GPIO_G_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_G_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G5R_SHIFT)
+#define GPIO_G_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_G_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G4R_SHIFT)
+#define GPIO_G_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_G_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G3R_SHIFT)
+#define GPIO_G_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_G_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G2R_SHIFT)
+#define GPIO_G_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_G_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G1R_SHIFT)
+#define GPIO_G_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_G_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_00_0_G0R_SHIFT)
+#define GPIO_G_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_G_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_G_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_VM_01_0
+#define GPIO_G_VM_01_0                  MK_ADDR_CONST(0x4008)
+#define GPIO_G_VM_01_0_SECURE                   0x0
+#define GPIO_G_VM_01_0_DUAL                     0x0
+#define GPIO_G_VM_01_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_G_VM_01_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_G_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_G_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_G_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM1_SHIFT)
+#define GPIO_G_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_G_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_G_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_G_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_G_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_G_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM2_SHIFT)
+#define GPIO_G_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_G_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_G_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_G_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_G_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_G_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM3_SHIFT)
+#define GPIO_G_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_G_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_G_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_G_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_G_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_G_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM4_SHIFT)
+#define GPIO_G_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_G_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_G_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_G_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_G_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_G_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM5_SHIFT)
+#define GPIO_G_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_G_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_G_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_G_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_G_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_G_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM6_SHIFT)
+#define GPIO_G_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_G_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_G_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_G_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_G_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_G_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM7_SHIFT)
+#define GPIO_G_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_G_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_G_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_G_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_G_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_G_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_01_0_VM8_SHIFT)
+#define GPIO_G_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_G_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_G_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_G_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_G_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_SCR_01_0
+#define GPIO_G_SCR_01_0                 MK_ADDR_CONST(0x400c)
+#define GPIO_G_SCR_01_0_SECURE                  0x0
+#define GPIO_G_SCR_01_0_DUAL                    0x0
+#define GPIO_G_SCR_01_0_SCR                     0
+#define GPIO_G_SCR_01_0_SCRREG                  0
+#define GPIO_G_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_G_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_G_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_G_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_G_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_G_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_G_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_G_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_G_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_G_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_G_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_G_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_G_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_G_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_G_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_G_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_G_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_G_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_G_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR7_SHIFT)
+#define GPIO_G_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_G_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR6_SHIFT)
+#define GPIO_G_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_G_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR5_SHIFT)
+#define GPIO_G_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_G_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR4_SHIFT)
+#define GPIO_G_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_G_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR3_SHIFT)
+#define GPIO_G_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_G_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR2_SHIFT)
+#define GPIO_G_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_G_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR1_SHIFT)
+#define GPIO_G_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_G_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_PR0_SHIFT)
+#define GPIO_G_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_G_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G7W_SHIFT)
+#define GPIO_G_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_G_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G6W_SHIFT)
+#define GPIO_G_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_G_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G5W_SHIFT)
+#define GPIO_G_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_G_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G4W_SHIFT)
+#define GPIO_G_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_G_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G3W_SHIFT)
+#define GPIO_G_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_G_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G2W_SHIFT)
+#define GPIO_G_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_G_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G1W_SHIFT)
+#define GPIO_G_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_G_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G0W_SHIFT)
+#define GPIO_G_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_G_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G7R_SHIFT)
+#define GPIO_G_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_G_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G6R_SHIFT)
+#define GPIO_G_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_G_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G5R_SHIFT)
+#define GPIO_G_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_G_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G4R_SHIFT)
+#define GPIO_G_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_G_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G3R_SHIFT)
+#define GPIO_G_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_G_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G2R_SHIFT)
+#define GPIO_G_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_G_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G1R_SHIFT)
+#define GPIO_G_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_G_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_01_0_G0R_SHIFT)
+#define GPIO_G_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_G_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_G_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_VM_02_0
+#define GPIO_G_VM_02_0                  MK_ADDR_CONST(0x4010)
+#define GPIO_G_VM_02_0_SECURE                   0x0
+#define GPIO_G_VM_02_0_DUAL                     0x0
+#define GPIO_G_VM_02_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_G_VM_02_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_G_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_G_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_G_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM1_SHIFT)
+#define GPIO_G_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_G_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_G_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_G_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_G_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_G_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM2_SHIFT)
+#define GPIO_G_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_G_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_G_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_G_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_G_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_G_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM3_SHIFT)
+#define GPIO_G_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_G_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_G_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_G_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_G_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_G_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM4_SHIFT)
+#define GPIO_G_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_G_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_G_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_G_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_G_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_G_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM5_SHIFT)
+#define GPIO_G_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_G_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_G_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_G_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_G_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_G_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM6_SHIFT)
+#define GPIO_G_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_G_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_G_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_G_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_G_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_G_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM7_SHIFT)
+#define GPIO_G_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_G_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_G_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_G_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_G_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_G_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_02_0_VM8_SHIFT)
+#define GPIO_G_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_G_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_G_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_G_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_G_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_SCR_02_0
+#define GPIO_G_SCR_02_0                 MK_ADDR_CONST(0x4014)
+#define GPIO_G_SCR_02_0_SECURE                  0x0
+#define GPIO_G_SCR_02_0_DUAL                    0x0
+#define GPIO_G_SCR_02_0_SCR                     0
+#define GPIO_G_SCR_02_0_SCRREG                  0
+#define GPIO_G_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_G_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_G_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_G_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_G_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_G_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_G_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_G_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_G_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_G_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_G_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_G_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_G_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_G_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_G_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_G_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_G_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_G_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_G_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR7_SHIFT)
+#define GPIO_G_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_G_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR6_SHIFT)
+#define GPIO_G_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_G_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR5_SHIFT)
+#define GPIO_G_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_G_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR4_SHIFT)
+#define GPIO_G_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_G_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR3_SHIFT)
+#define GPIO_G_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_G_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR2_SHIFT)
+#define GPIO_G_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_G_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR1_SHIFT)
+#define GPIO_G_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_G_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_PR0_SHIFT)
+#define GPIO_G_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_G_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G7W_SHIFT)
+#define GPIO_G_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_G_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G6W_SHIFT)
+#define GPIO_G_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_G_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G5W_SHIFT)
+#define GPIO_G_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_G_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G4W_SHIFT)
+#define GPIO_G_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_G_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G3W_SHIFT)
+#define GPIO_G_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_G_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G2W_SHIFT)
+#define GPIO_G_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_G_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G1W_SHIFT)
+#define GPIO_G_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_G_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G0W_SHIFT)
+#define GPIO_G_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_G_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G7R_SHIFT)
+#define GPIO_G_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_G_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G6R_SHIFT)
+#define GPIO_G_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_G_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G5R_SHIFT)
+#define GPIO_G_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_G_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G4R_SHIFT)
+#define GPIO_G_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_G_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G3R_SHIFT)
+#define GPIO_G_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_G_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G2R_SHIFT)
+#define GPIO_G_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_G_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G1R_SHIFT)
+#define GPIO_G_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_G_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_02_0_G0R_SHIFT)
+#define GPIO_G_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_G_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_G_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_VM_03_0
+#define GPIO_G_VM_03_0                  MK_ADDR_CONST(0x4018)
+#define GPIO_G_VM_03_0_SECURE                   0x0
+#define GPIO_G_VM_03_0_DUAL                     0x0
+#define GPIO_G_VM_03_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_G_VM_03_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_G_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_G_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_G_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM1_SHIFT)
+#define GPIO_G_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_G_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_G_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_G_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_G_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_G_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM2_SHIFT)
+#define GPIO_G_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_G_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_G_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_G_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_G_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_G_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM3_SHIFT)
+#define GPIO_G_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_G_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_G_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_G_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_G_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_G_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM4_SHIFT)
+#define GPIO_G_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_G_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_G_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_G_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_G_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_G_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM5_SHIFT)
+#define GPIO_G_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_G_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_G_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_G_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_G_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_G_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM6_SHIFT)
+#define GPIO_G_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_G_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_G_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_G_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_G_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_G_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM7_SHIFT)
+#define GPIO_G_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_G_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_G_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_G_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_G_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_G_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_03_0_VM8_SHIFT)
+#define GPIO_G_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_G_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_G_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_G_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_G_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_SCR_03_0
+#define GPIO_G_SCR_03_0                 MK_ADDR_CONST(0x401c)
+#define GPIO_G_SCR_03_0_SECURE                  0x0
+#define GPIO_G_SCR_03_0_DUAL                    0x0
+#define GPIO_G_SCR_03_0_SCR                     0
+#define GPIO_G_SCR_03_0_SCRREG                  0
+#define GPIO_G_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_G_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_G_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_G_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_G_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_G_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_G_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_G_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_G_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_G_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_G_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_G_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_G_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_G_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_G_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_G_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_G_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_G_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_G_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR7_SHIFT)
+#define GPIO_G_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_G_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR6_SHIFT)
+#define GPIO_G_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_G_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR5_SHIFT)
+#define GPIO_G_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_G_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR4_SHIFT)
+#define GPIO_G_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_G_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR3_SHIFT)
+#define GPIO_G_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_G_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR2_SHIFT)
+#define GPIO_G_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_G_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR1_SHIFT)
+#define GPIO_G_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_G_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_PR0_SHIFT)
+#define GPIO_G_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_G_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G7W_SHIFT)
+#define GPIO_G_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_G_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G6W_SHIFT)
+#define GPIO_G_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_G_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G5W_SHIFT)
+#define GPIO_G_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_G_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G4W_SHIFT)
+#define GPIO_G_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_G_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G3W_SHIFT)
+#define GPIO_G_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_G_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G2W_SHIFT)
+#define GPIO_G_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_G_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G1W_SHIFT)
+#define GPIO_G_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_G_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G0W_SHIFT)
+#define GPIO_G_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_G_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G7R_SHIFT)
+#define GPIO_G_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_G_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G6R_SHIFT)
+#define GPIO_G_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_G_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G5R_SHIFT)
+#define GPIO_G_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_G_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G4R_SHIFT)
+#define GPIO_G_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_G_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G3R_SHIFT)
+#define GPIO_G_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_G_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G2R_SHIFT)
+#define GPIO_G_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_G_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G1R_SHIFT)
+#define GPIO_G_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_G_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_03_0_G0R_SHIFT)
+#define GPIO_G_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_G_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_G_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_VM_04_0
+#define GPIO_G_VM_04_0                  MK_ADDR_CONST(0x4020)
+#define GPIO_G_VM_04_0_SECURE                   0x0
+#define GPIO_G_VM_04_0_DUAL                     0x0
+#define GPIO_G_VM_04_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_G_VM_04_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_G_VM_04_0_WORD_COUNT                       0x1
+#define GPIO_G_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_G_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM1_SHIFT)
+#define GPIO_G_VM_04_0_VM1_RANGE                        1:0
+#define GPIO_G_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_G_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_G_VM_04_0_VM1_WOFFSET                      0x0
+#define GPIO_G_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_G_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM2_SHIFT)
+#define GPIO_G_VM_04_0_VM2_RANGE                        3:2
+#define GPIO_G_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_G_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_G_VM_04_0_VM2_WOFFSET                      0x0
+#define GPIO_G_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_G_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM3_SHIFT)
+#define GPIO_G_VM_04_0_VM3_RANGE                        5:4
+#define GPIO_G_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_G_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_G_VM_04_0_VM3_WOFFSET                      0x0
+#define GPIO_G_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_G_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM4_SHIFT)
+#define GPIO_G_VM_04_0_VM4_RANGE                        7:6
+#define GPIO_G_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_G_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_G_VM_04_0_VM4_WOFFSET                      0x0
+#define GPIO_G_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_G_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM5_SHIFT)
+#define GPIO_G_VM_04_0_VM5_RANGE                        9:8
+#define GPIO_G_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_G_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_G_VM_04_0_VM5_WOFFSET                      0x0
+#define GPIO_G_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_G_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM6_SHIFT)
+#define GPIO_G_VM_04_0_VM6_RANGE                        11:10
+#define GPIO_G_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_G_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_G_VM_04_0_VM6_WOFFSET                      0x0
+#define GPIO_G_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_G_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM7_SHIFT)
+#define GPIO_G_VM_04_0_VM7_RANGE                        13:12
+#define GPIO_G_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_G_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_G_VM_04_0_VM7_WOFFSET                      0x0
+#define GPIO_G_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_G_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_04_0_VM8_SHIFT)
+#define GPIO_G_VM_04_0_VM8_RANGE                        15:14
+#define GPIO_G_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_G_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_G_VM_04_0_VM8_WOFFSET                      0x0
+#define GPIO_G_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_SCR_04_0
+#define GPIO_G_SCR_04_0                 MK_ADDR_CONST(0x4024)
+#define GPIO_G_SCR_04_0_SECURE                  0x0
+#define GPIO_G_SCR_04_0_DUAL                    0x0
+#define GPIO_G_SCR_04_0_SCR                     0
+#define GPIO_G_SCR_04_0_SCRREG                  0
+#define GPIO_G_SCR_04_0_WORD_COUNT                      0x1
+#define GPIO_G_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_G_SCR_04_0_SEC_LCK_RANGE                   29:29
+#define GPIO_G_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_04_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_G_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_G_SCR_04_0_SEC_WEN_RANGE                   28:28
+#define GPIO_G_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_04_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_G_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_G_SCR_04_0_SEC_REN_RANGE                   27:27
+#define GPIO_G_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_04_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_G_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_G_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_G_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_G_SCR_04_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_G_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_G_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_G_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_G_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_G_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR7_SHIFT)
+#define GPIO_G_SCR_04_0_PR7_RANGE                       23:23
+#define GPIO_G_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_04_0_PR7_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR6_SHIFT)
+#define GPIO_G_SCR_04_0_PR6_RANGE                       22:22
+#define GPIO_G_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_04_0_PR6_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR5_SHIFT)
+#define GPIO_G_SCR_04_0_PR5_RANGE                       21:21
+#define GPIO_G_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_04_0_PR5_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR4_SHIFT)
+#define GPIO_G_SCR_04_0_PR4_RANGE                       20:20
+#define GPIO_G_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_04_0_PR4_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR3_SHIFT)
+#define GPIO_G_SCR_04_0_PR3_RANGE                       19:19
+#define GPIO_G_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_04_0_PR3_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR2_SHIFT)
+#define GPIO_G_SCR_04_0_PR2_RANGE                       18:18
+#define GPIO_G_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_04_0_PR2_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR1_SHIFT)
+#define GPIO_G_SCR_04_0_PR1_RANGE                       17:17
+#define GPIO_G_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_04_0_PR1_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_PR0_SHIFT)
+#define GPIO_G_SCR_04_0_PR0_RANGE                       16:16
+#define GPIO_G_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_04_0_PR0_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G7W_SHIFT)
+#define GPIO_G_SCR_04_0_G7W_RANGE                       15:15
+#define GPIO_G_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_04_0_G7W_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G6W_SHIFT)
+#define GPIO_G_SCR_04_0_G6W_RANGE                       14:14
+#define GPIO_G_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_04_0_G6W_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G5W_SHIFT)
+#define GPIO_G_SCR_04_0_G5W_RANGE                       13:13
+#define GPIO_G_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_04_0_G5W_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G4W_SHIFT)
+#define GPIO_G_SCR_04_0_G4W_RANGE                       12:12
+#define GPIO_G_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_04_0_G4W_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G3W_SHIFT)
+#define GPIO_G_SCR_04_0_G3W_RANGE                       11:11
+#define GPIO_G_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_04_0_G3W_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G2W_SHIFT)
+#define GPIO_G_SCR_04_0_G2W_RANGE                       10:10
+#define GPIO_G_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_04_0_G2W_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G1W_SHIFT)
+#define GPIO_G_SCR_04_0_G1W_RANGE                       9:9
+#define GPIO_G_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_04_0_G1W_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G0W_SHIFT)
+#define GPIO_G_SCR_04_0_G0W_RANGE                       8:8
+#define GPIO_G_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_04_0_G0W_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G7R_SHIFT)
+#define GPIO_G_SCR_04_0_G7R_RANGE                       7:7
+#define GPIO_G_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_04_0_G7R_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G6R_SHIFT)
+#define GPIO_G_SCR_04_0_G6R_RANGE                       6:6
+#define GPIO_G_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_04_0_G6R_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G5R_SHIFT)
+#define GPIO_G_SCR_04_0_G5R_RANGE                       5:5
+#define GPIO_G_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_04_0_G5R_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G4R_SHIFT)
+#define GPIO_G_SCR_04_0_G4R_RANGE                       4:4
+#define GPIO_G_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_04_0_G4R_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G3R_SHIFT)
+#define GPIO_G_SCR_04_0_G3R_RANGE                       3:3
+#define GPIO_G_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_04_0_G3R_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G2R_SHIFT)
+#define GPIO_G_SCR_04_0_G2R_RANGE                       2:2
+#define GPIO_G_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_04_0_G2R_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G1R_SHIFT)
+#define GPIO_G_SCR_04_0_G1R_RANGE                       1:1
+#define GPIO_G_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_04_0_G1R_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_04_0_G0R_SHIFT)
+#define GPIO_G_SCR_04_0_G0R_RANGE                       0:0
+#define GPIO_G_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_04_0_G0R_WOFFSET                     0x0
+#define GPIO_G_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_VM_05_0
+#define GPIO_G_VM_05_0                  MK_ADDR_CONST(0x4028)
+#define GPIO_G_VM_05_0_SECURE                   0x0
+#define GPIO_G_VM_05_0_DUAL                     0x0
+#define GPIO_G_VM_05_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_G_VM_05_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_G_VM_05_0_WORD_COUNT                       0x1
+#define GPIO_G_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_G_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM1_SHIFT)
+#define GPIO_G_VM_05_0_VM1_RANGE                        1:0
+#define GPIO_G_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_G_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_G_VM_05_0_VM1_WOFFSET                      0x0
+#define GPIO_G_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_G_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM2_SHIFT)
+#define GPIO_G_VM_05_0_VM2_RANGE                        3:2
+#define GPIO_G_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_G_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_G_VM_05_0_VM2_WOFFSET                      0x0
+#define GPIO_G_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_G_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM3_SHIFT)
+#define GPIO_G_VM_05_0_VM3_RANGE                        5:4
+#define GPIO_G_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_G_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_G_VM_05_0_VM3_WOFFSET                      0x0
+#define GPIO_G_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_G_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM4_SHIFT)
+#define GPIO_G_VM_05_0_VM4_RANGE                        7:6
+#define GPIO_G_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_G_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_G_VM_05_0_VM4_WOFFSET                      0x0
+#define GPIO_G_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_G_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM5_SHIFT)
+#define GPIO_G_VM_05_0_VM5_RANGE                        9:8
+#define GPIO_G_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_G_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_G_VM_05_0_VM5_WOFFSET                      0x0
+#define GPIO_G_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_G_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM6_SHIFT)
+#define GPIO_G_VM_05_0_VM6_RANGE                        11:10
+#define GPIO_G_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_G_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_G_VM_05_0_VM6_WOFFSET                      0x0
+#define GPIO_G_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_G_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM7_SHIFT)
+#define GPIO_G_VM_05_0_VM7_RANGE                        13:12
+#define GPIO_G_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_G_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_G_VM_05_0_VM7_WOFFSET                      0x0
+#define GPIO_G_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_G_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_05_0_VM8_SHIFT)
+#define GPIO_G_VM_05_0_VM8_RANGE                        15:14
+#define GPIO_G_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_G_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_G_VM_05_0_VM8_WOFFSET                      0x0
+#define GPIO_G_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_SCR_05_0
+#define GPIO_G_SCR_05_0                 MK_ADDR_CONST(0x402c)
+#define GPIO_G_SCR_05_0_SECURE                  0x0
+#define GPIO_G_SCR_05_0_DUAL                    0x0
+#define GPIO_G_SCR_05_0_SCR                     0
+#define GPIO_G_SCR_05_0_SCRREG                  0
+#define GPIO_G_SCR_05_0_WORD_COUNT                      0x1
+#define GPIO_G_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_G_SCR_05_0_SEC_LCK_RANGE                   29:29
+#define GPIO_G_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_05_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_G_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_G_SCR_05_0_SEC_WEN_RANGE                   28:28
+#define GPIO_G_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_05_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_G_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_G_SCR_05_0_SEC_REN_RANGE                   27:27
+#define GPIO_G_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_05_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_G_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_G_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_G_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_G_SCR_05_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_G_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_G_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_G_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_G_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_G_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR7_SHIFT)
+#define GPIO_G_SCR_05_0_PR7_RANGE                       23:23
+#define GPIO_G_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_05_0_PR7_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR6_SHIFT)
+#define GPIO_G_SCR_05_0_PR6_RANGE                       22:22
+#define GPIO_G_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_05_0_PR6_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR5_SHIFT)
+#define GPIO_G_SCR_05_0_PR5_RANGE                       21:21
+#define GPIO_G_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_05_0_PR5_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR4_SHIFT)
+#define GPIO_G_SCR_05_0_PR4_RANGE                       20:20
+#define GPIO_G_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_05_0_PR4_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR3_SHIFT)
+#define GPIO_G_SCR_05_0_PR3_RANGE                       19:19
+#define GPIO_G_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_05_0_PR3_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR2_SHIFT)
+#define GPIO_G_SCR_05_0_PR2_RANGE                       18:18
+#define GPIO_G_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_05_0_PR2_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR1_SHIFT)
+#define GPIO_G_SCR_05_0_PR1_RANGE                       17:17
+#define GPIO_G_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_05_0_PR1_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_PR0_SHIFT)
+#define GPIO_G_SCR_05_0_PR0_RANGE                       16:16
+#define GPIO_G_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_05_0_PR0_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G7W_SHIFT)
+#define GPIO_G_SCR_05_0_G7W_RANGE                       15:15
+#define GPIO_G_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_05_0_G7W_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G6W_SHIFT)
+#define GPIO_G_SCR_05_0_G6W_RANGE                       14:14
+#define GPIO_G_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_05_0_G6W_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G5W_SHIFT)
+#define GPIO_G_SCR_05_0_G5W_RANGE                       13:13
+#define GPIO_G_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_05_0_G5W_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G4W_SHIFT)
+#define GPIO_G_SCR_05_0_G4W_RANGE                       12:12
+#define GPIO_G_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_05_0_G4W_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G3W_SHIFT)
+#define GPIO_G_SCR_05_0_G3W_RANGE                       11:11
+#define GPIO_G_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_05_0_G3W_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G2W_SHIFT)
+#define GPIO_G_SCR_05_0_G2W_RANGE                       10:10
+#define GPIO_G_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_05_0_G2W_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G1W_SHIFT)
+#define GPIO_G_SCR_05_0_G1W_RANGE                       9:9
+#define GPIO_G_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_05_0_G1W_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G0W_SHIFT)
+#define GPIO_G_SCR_05_0_G0W_RANGE                       8:8
+#define GPIO_G_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_05_0_G0W_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G7R_SHIFT)
+#define GPIO_G_SCR_05_0_G7R_RANGE                       7:7
+#define GPIO_G_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_05_0_G7R_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G6R_SHIFT)
+#define GPIO_G_SCR_05_0_G6R_RANGE                       6:6
+#define GPIO_G_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_05_0_G6R_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G5R_SHIFT)
+#define GPIO_G_SCR_05_0_G5R_RANGE                       5:5
+#define GPIO_G_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_05_0_G5R_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G4R_SHIFT)
+#define GPIO_G_SCR_05_0_G4R_RANGE                       4:4
+#define GPIO_G_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_05_0_G4R_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G3R_SHIFT)
+#define GPIO_G_SCR_05_0_G3R_RANGE                       3:3
+#define GPIO_G_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_05_0_G3R_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G2R_SHIFT)
+#define GPIO_G_SCR_05_0_G2R_RANGE                       2:2
+#define GPIO_G_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_05_0_G2R_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G1R_SHIFT)
+#define GPIO_G_SCR_05_0_G1R_RANGE                       1:1
+#define GPIO_G_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_05_0_G1R_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_05_0_G0R_SHIFT)
+#define GPIO_G_SCR_05_0_G0R_RANGE                       0:0
+#define GPIO_G_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_05_0_G0R_WOFFSET                     0x0
+#define GPIO_G_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_VM_06_0
+#define GPIO_G_VM_06_0                  MK_ADDR_CONST(0x4030)
+#define GPIO_G_VM_06_0_SECURE                   0x0
+#define GPIO_G_VM_06_0_DUAL                     0x0
+#define GPIO_G_VM_06_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_G_VM_06_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_G_VM_06_0_WORD_COUNT                       0x1
+#define GPIO_G_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_G_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM1_SHIFT)
+#define GPIO_G_VM_06_0_VM1_RANGE                        1:0
+#define GPIO_G_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_G_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_G_VM_06_0_VM1_WOFFSET                      0x0
+#define GPIO_G_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_G_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM2_SHIFT)
+#define GPIO_G_VM_06_0_VM2_RANGE                        3:2
+#define GPIO_G_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_G_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_G_VM_06_0_VM2_WOFFSET                      0x0
+#define GPIO_G_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_G_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM3_SHIFT)
+#define GPIO_G_VM_06_0_VM3_RANGE                        5:4
+#define GPIO_G_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_G_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_G_VM_06_0_VM3_WOFFSET                      0x0
+#define GPIO_G_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_G_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM4_SHIFT)
+#define GPIO_G_VM_06_0_VM4_RANGE                        7:6
+#define GPIO_G_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_G_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_G_VM_06_0_VM4_WOFFSET                      0x0
+#define GPIO_G_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_G_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM5_SHIFT)
+#define GPIO_G_VM_06_0_VM5_RANGE                        9:8
+#define GPIO_G_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_G_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_G_VM_06_0_VM5_WOFFSET                      0x0
+#define GPIO_G_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_G_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM6_SHIFT)
+#define GPIO_G_VM_06_0_VM6_RANGE                        11:10
+#define GPIO_G_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_G_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_G_VM_06_0_VM6_WOFFSET                      0x0
+#define GPIO_G_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_G_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM7_SHIFT)
+#define GPIO_G_VM_06_0_VM7_RANGE                        13:12
+#define GPIO_G_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_G_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_G_VM_06_0_VM7_WOFFSET                      0x0
+#define GPIO_G_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_G_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_06_0_VM8_SHIFT)
+#define GPIO_G_VM_06_0_VM8_RANGE                        15:14
+#define GPIO_G_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_G_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_G_VM_06_0_VM8_WOFFSET                      0x0
+#define GPIO_G_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_SCR_06_0
+#define GPIO_G_SCR_06_0                 MK_ADDR_CONST(0x4034)
+#define GPIO_G_SCR_06_0_SECURE                  0x0
+#define GPIO_G_SCR_06_0_DUAL                    0x0
+#define GPIO_G_SCR_06_0_SCR                     0
+#define GPIO_G_SCR_06_0_SCRREG                  0
+#define GPIO_G_SCR_06_0_WORD_COUNT                      0x1
+#define GPIO_G_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_SEC_LCK_SHIFT)
+#define GPIO_G_SCR_06_0_SEC_LCK_RANGE                   29:29
+#define GPIO_G_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_06_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_G_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_SEC_WEN_SHIFT)
+#define GPIO_G_SCR_06_0_SEC_WEN_RANGE                   28:28
+#define GPIO_G_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_06_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_G_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_SEC_REN_SHIFT)
+#define GPIO_G_SCR_06_0_SEC_REN_RANGE                   27:27
+#define GPIO_G_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_06_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_G_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_G_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_G_SCR_06_0_SEC_OWNER_SHIFT)
+#define GPIO_G_SCR_06_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_G_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_G_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_G_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_G_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_G_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR7_SHIFT)
+#define GPIO_G_SCR_06_0_PR7_RANGE                       23:23
+#define GPIO_G_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_06_0_PR7_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR6_SHIFT)
+#define GPIO_G_SCR_06_0_PR6_RANGE                       22:22
+#define GPIO_G_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_06_0_PR6_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR5_SHIFT)
+#define GPIO_G_SCR_06_0_PR5_RANGE                       21:21
+#define GPIO_G_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_06_0_PR5_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR4_SHIFT)
+#define GPIO_G_SCR_06_0_PR4_RANGE                       20:20
+#define GPIO_G_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_06_0_PR4_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR3_SHIFT)
+#define GPIO_G_SCR_06_0_PR3_RANGE                       19:19
+#define GPIO_G_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_06_0_PR3_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR2_SHIFT)
+#define GPIO_G_SCR_06_0_PR2_RANGE                       18:18
+#define GPIO_G_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_06_0_PR2_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR1_SHIFT)
+#define GPIO_G_SCR_06_0_PR1_RANGE                       17:17
+#define GPIO_G_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_06_0_PR1_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_PR0_SHIFT)
+#define GPIO_G_SCR_06_0_PR0_RANGE                       16:16
+#define GPIO_G_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_06_0_PR0_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G7W_SHIFT)
+#define GPIO_G_SCR_06_0_G7W_RANGE                       15:15
+#define GPIO_G_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_06_0_G7W_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G6W_SHIFT)
+#define GPIO_G_SCR_06_0_G6W_RANGE                       14:14
+#define GPIO_G_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_06_0_G6W_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G5W_SHIFT)
+#define GPIO_G_SCR_06_0_G5W_RANGE                       13:13
+#define GPIO_G_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_06_0_G5W_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G4W_SHIFT)
+#define GPIO_G_SCR_06_0_G4W_RANGE                       12:12
+#define GPIO_G_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_06_0_G4W_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G3W_SHIFT)
+#define GPIO_G_SCR_06_0_G3W_RANGE                       11:11
+#define GPIO_G_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_06_0_G3W_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G2W_SHIFT)
+#define GPIO_G_SCR_06_0_G2W_RANGE                       10:10
+#define GPIO_G_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_06_0_G2W_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G1W_SHIFT)
+#define GPIO_G_SCR_06_0_G1W_RANGE                       9:9
+#define GPIO_G_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_06_0_G1W_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G0W_SHIFT)
+#define GPIO_G_SCR_06_0_G0W_RANGE                       8:8
+#define GPIO_G_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_06_0_G0W_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G7R_SHIFT)
+#define GPIO_G_SCR_06_0_G7R_RANGE                       7:7
+#define GPIO_G_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_06_0_G7R_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G6R_SHIFT)
+#define GPIO_G_SCR_06_0_G6R_RANGE                       6:6
+#define GPIO_G_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_06_0_G6R_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G5R_SHIFT)
+#define GPIO_G_SCR_06_0_G5R_RANGE                       5:5
+#define GPIO_G_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_06_0_G5R_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G4R_SHIFT)
+#define GPIO_G_SCR_06_0_G4R_RANGE                       4:4
+#define GPIO_G_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_06_0_G4R_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G3R_SHIFT)
+#define GPIO_G_SCR_06_0_G3R_RANGE                       3:3
+#define GPIO_G_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_06_0_G3R_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G2R_SHIFT)
+#define GPIO_G_SCR_06_0_G2R_RANGE                       2:2
+#define GPIO_G_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_06_0_G2R_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G1R_SHIFT)
+#define GPIO_G_SCR_06_0_G1R_RANGE                       1:1
+#define GPIO_G_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_06_0_G1R_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_06_0_G0R_SHIFT)
+#define GPIO_G_SCR_06_0_G0R_RANGE                       0:0
+#define GPIO_G_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_06_0_G0R_WOFFSET                     0x0
+#define GPIO_G_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_VM_07_0
+#define GPIO_G_VM_07_0                  MK_ADDR_CONST(0x4038)
+#define GPIO_G_VM_07_0_SECURE                   0x0
+#define GPIO_G_VM_07_0_DUAL                     0x0
+#define GPIO_G_VM_07_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_G_VM_07_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_G_VM_07_0_WORD_COUNT                       0x1
+#define GPIO_G_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_G_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_G_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM1_SHIFT)
+#define GPIO_G_VM_07_0_VM1_RANGE                        1:0
+#define GPIO_G_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_G_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_G_VM_07_0_VM1_WOFFSET                      0x0
+#define GPIO_G_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_G_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM2_SHIFT)
+#define GPIO_G_VM_07_0_VM2_RANGE                        3:2
+#define GPIO_G_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_G_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_G_VM_07_0_VM2_WOFFSET                      0x0
+#define GPIO_G_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_G_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM3_SHIFT)
+#define GPIO_G_VM_07_0_VM3_RANGE                        5:4
+#define GPIO_G_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_G_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_G_VM_07_0_VM3_WOFFSET                      0x0
+#define GPIO_G_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_G_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM4_SHIFT)
+#define GPIO_G_VM_07_0_VM4_RANGE                        7:6
+#define GPIO_G_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_G_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_G_VM_07_0_VM4_WOFFSET                      0x0
+#define GPIO_G_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_G_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM5_SHIFT)
+#define GPIO_G_VM_07_0_VM5_RANGE                        9:8
+#define GPIO_G_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_G_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_G_VM_07_0_VM5_WOFFSET                      0x0
+#define GPIO_G_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_G_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM6_SHIFT)
+#define GPIO_G_VM_07_0_VM6_RANGE                        11:10
+#define GPIO_G_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_G_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_G_VM_07_0_VM6_WOFFSET                      0x0
+#define GPIO_G_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_G_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM7_SHIFT)
+#define GPIO_G_VM_07_0_VM7_RANGE                        13:12
+#define GPIO_G_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_G_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_G_VM_07_0_VM7_WOFFSET                      0x0
+#define GPIO_G_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_G_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_G_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_G_VM_07_0_VM8_SHIFT)
+#define GPIO_G_VM_07_0_VM8_RANGE                        15:14
+#define GPIO_G_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_G_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_G_VM_07_0_VM8_WOFFSET                      0x0
+#define GPIO_G_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_G_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_G_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_SCR_07_0
+#define GPIO_G_SCR_07_0                 MK_ADDR_CONST(0x403c)
+#define GPIO_G_SCR_07_0_SECURE                  0x0
+#define GPIO_G_SCR_07_0_DUAL                    0x0
+#define GPIO_G_SCR_07_0_SCR                     0
+#define GPIO_G_SCR_07_0_SCRREG                  0
+#define GPIO_G_SCR_07_0_WORD_COUNT                      0x1
+#define GPIO_G_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_G_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_SEC_LCK_SHIFT)
+#define GPIO_G_SCR_07_0_SEC_LCK_RANGE                   29:29
+#define GPIO_G_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_G_SCR_07_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_G_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_SEC_WEN_SHIFT)
+#define GPIO_G_SCR_07_0_SEC_WEN_RANGE                   28:28
+#define GPIO_G_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_G_SCR_07_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_G_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_SEC_REN_SHIFT)
+#define GPIO_G_SCR_07_0_SEC_REN_RANGE                   27:27
+#define GPIO_G_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_G_SCR_07_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_G_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_G_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_G_SCR_07_0_SEC_OWNER_SHIFT)
+#define GPIO_G_SCR_07_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_G_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_G_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_G_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_G_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_G_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR7_SHIFT)
+#define GPIO_G_SCR_07_0_PR7_RANGE                       23:23
+#define GPIO_G_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_G_SCR_07_0_PR7_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR6_SHIFT)
+#define GPIO_G_SCR_07_0_PR6_RANGE                       22:22
+#define GPIO_G_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_G_SCR_07_0_PR6_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR5_SHIFT)
+#define GPIO_G_SCR_07_0_PR5_RANGE                       21:21
+#define GPIO_G_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_G_SCR_07_0_PR5_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR4_SHIFT)
+#define GPIO_G_SCR_07_0_PR4_RANGE                       20:20
+#define GPIO_G_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_G_SCR_07_0_PR4_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR3_SHIFT)
+#define GPIO_G_SCR_07_0_PR3_RANGE                       19:19
+#define GPIO_G_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_G_SCR_07_0_PR3_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR2_SHIFT)
+#define GPIO_G_SCR_07_0_PR2_RANGE                       18:18
+#define GPIO_G_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_G_SCR_07_0_PR2_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR1_SHIFT)
+#define GPIO_G_SCR_07_0_PR1_RANGE                       17:17
+#define GPIO_G_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_G_SCR_07_0_PR1_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_PR0_SHIFT)
+#define GPIO_G_SCR_07_0_PR0_RANGE                       16:16
+#define GPIO_G_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_G_SCR_07_0_PR0_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G7W_SHIFT)
+#define GPIO_G_SCR_07_0_G7W_RANGE                       15:15
+#define GPIO_G_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_G_SCR_07_0_G7W_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G6W_SHIFT)
+#define GPIO_G_SCR_07_0_G6W_RANGE                       14:14
+#define GPIO_G_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_G_SCR_07_0_G6W_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G5W_SHIFT)
+#define GPIO_G_SCR_07_0_G5W_RANGE                       13:13
+#define GPIO_G_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_G_SCR_07_0_G5W_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G4W_SHIFT)
+#define GPIO_G_SCR_07_0_G4W_RANGE                       12:12
+#define GPIO_G_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_G_SCR_07_0_G4W_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G3W_SHIFT)
+#define GPIO_G_SCR_07_0_G3W_RANGE                       11:11
+#define GPIO_G_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_G_SCR_07_0_G3W_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G2W_SHIFT)
+#define GPIO_G_SCR_07_0_G2W_RANGE                       10:10
+#define GPIO_G_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_G_SCR_07_0_G2W_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G1W_SHIFT)
+#define GPIO_G_SCR_07_0_G1W_RANGE                       9:9
+#define GPIO_G_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_G_SCR_07_0_G1W_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G0W_SHIFT)
+#define GPIO_G_SCR_07_0_G0W_RANGE                       8:8
+#define GPIO_G_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_G_SCR_07_0_G0W_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G7R_SHIFT)
+#define GPIO_G_SCR_07_0_G7R_RANGE                       7:7
+#define GPIO_G_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_G_SCR_07_0_G7R_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G6R_SHIFT)
+#define GPIO_G_SCR_07_0_G6R_RANGE                       6:6
+#define GPIO_G_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_G_SCR_07_0_G6R_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G5R_SHIFT)
+#define GPIO_G_SCR_07_0_G5R_RANGE                       5:5
+#define GPIO_G_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_SCR_07_0_G5R_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G4R_SHIFT)
+#define GPIO_G_SCR_07_0_G4R_RANGE                       4:4
+#define GPIO_G_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_G_SCR_07_0_G4R_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G3R_SHIFT)
+#define GPIO_G_SCR_07_0_G3R_RANGE                       3:3
+#define GPIO_G_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_G_SCR_07_0_G3R_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G2R_SHIFT)
+#define GPIO_G_SCR_07_0_G2R_RANGE                       2:2
+#define GPIO_G_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_G_SCR_07_0_G2R_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G1R_SHIFT)
+#define GPIO_G_SCR_07_0_G1R_RANGE                       1:1
+#define GPIO_G_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_G_SCR_07_0_G1R_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_G_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_SCR_07_0_G0R_SHIFT)
+#define GPIO_G_SCR_07_0_G0R_RANGE                       0:0
+#define GPIO_G_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_SCR_07_0_G0R_WOFFSET                     0x0
+#define GPIO_G_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_G_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_VM_00_0
+#define GPIO_H_VM_00_0                  MK_ADDR_CONST(0x4040)
+#define GPIO_H_VM_00_0_SECURE                   0x0
+#define GPIO_H_VM_00_0_DUAL                     0x0
+#define GPIO_H_VM_00_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_H_VM_00_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_H_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_H_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_H_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM1_SHIFT)
+#define GPIO_H_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_H_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_H_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_H_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_H_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_H_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM2_SHIFT)
+#define GPIO_H_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_H_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_H_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_H_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_H_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_H_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM3_SHIFT)
+#define GPIO_H_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_H_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_H_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_H_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_H_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_H_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM4_SHIFT)
+#define GPIO_H_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_H_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_H_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_H_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_H_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_H_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM5_SHIFT)
+#define GPIO_H_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_H_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_H_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_H_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_H_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_H_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM6_SHIFT)
+#define GPIO_H_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_H_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_H_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_H_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_H_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_H_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM7_SHIFT)
+#define GPIO_H_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_H_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_H_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_H_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_H_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_H_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_00_0_VM8_SHIFT)
+#define GPIO_H_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_H_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_H_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_H_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_H_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_SCR_00_0
+#define GPIO_H_SCR_00_0                 MK_ADDR_CONST(0x4044)
+#define GPIO_H_SCR_00_0_SECURE                  0x0
+#define GPIO_H_SCR_00_0_DUAL                    0x0
+#define GPIO_H_SCR_00_0_SCR                     0
+#define GPIO_H_SCR_00_0_SCRREG                  0
+#define GPIO_H_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_H_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_H_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_H_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_H_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_H_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_H_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_H_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_H_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_H_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_H_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_H_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_H_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_H_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_H_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_H_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_H_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_H_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_H_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR7_SHIFT)
+#define GPIO_H_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_H_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR6_SHIFT)
+#define GPIO_H_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_H_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR5_SHIFT)
+#define GPIO_H_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_H_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR4_SHIFT)
+#define GPIO_H_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_H_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR3_SHIFT)
+#define GPIO_H_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_H_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR2_SHIFT)
+#define GPIO_H_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_H_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR1_SHIFT)
+#define GPIO_H_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_H_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_PR0_SHIFT)
+#define GPIO_H_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_H_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G7W_SHIFT)
+#define GPIO_H_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_H_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G6W_SHIFT)
+#define GPIO_H_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_H_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G5W_SHIFT)
+#define GPIO_H_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_H_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G4W_SHIFT)
+#define GPIO_H_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_H_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G3W_SHIFT)
+#define GPIO_H_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_H_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G2W_SHIFT)
+#define GPIO_H_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_H_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G1W_SHIFT)
+#define GPIO_H_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_H_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G0W_SHIFT)
+#define GPIO_H_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_H_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G7R_SHIFT)
+#define GPIO_H_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_H_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G6R_SHIFT)
+#define GPIO_H_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_H_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G5R_SHIFT)
+#define GPIO_H_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_H_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G4R_SHIFT)
+#define GPIO_H_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_H_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G3R_SHIFT)
+#define GPIO_H_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_H_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G2R_SHIFT)
+#define GPIO_H_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_H_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G1R_SHIFT)
+#define GPIO_H_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_H_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_00_0_G0R_SHIFT)
+#define GPIO_H_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_H_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_H_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_VM_01_0
+#define GPIO_H_VM_01_0                  MK_ADDR_CONST(0x4048)
+#define GPIO_H_VM_01_0_SECURE                   0x0
+#define GPIO_H_VM_01_0_DUAL                     0x0
+#define GPIO_H_VM_01_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_H_VM_01_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_H_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_H_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_H_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM1_SHIFT)
+#define GPIO_H_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_H_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_H_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_H_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_H_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_H_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM2_SHIFT)
+#define GPIO_H_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_H_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_H_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_H_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_H_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_H_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM3_SHIFT)
+#define GPIO_H_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_H_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_H_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_H_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_H_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_H_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM4_SHIFT)
+#define GPIO_H_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_H_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_H_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_H_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_H_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_H_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM5_SHIFT)
+#define GPIO_H_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_H_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_H_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_H_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_H_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_H_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM6_SHIFT)
+#define GPIO_H_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_H_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_H_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_H_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_H_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_H_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM7_SHIFT)
+#define GPIO_H_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_H_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_H_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_H_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_H_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_H_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_01_0_VM8_SHIFT)
+#define GPIO_H_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_H_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_H_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_H_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_H_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_SCR_01_0
+#define GPIO_H_SCR_01_0                 MK_ADDR_CONST(0x404c)
+#define GPIO_H_SCR_01_0_SECURE                  0x0
+#define GPIO_H_SCR_01_0_DUAL                    0x0
+#define GPIO_H_SCR_01_0_SCR                     0
+#define GPIO_H_SCR_01_0_SCRREG                  0
+#define GPIO_H_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_H_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_H_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_H_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_H_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_H_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_H_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_H_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_H_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_H_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_H_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_H_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_H_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_H_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_H_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_H_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_H_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_H_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_H_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR7_SHIFT)
+#define GPIO_H_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_H_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR6_SHIFT)
+#define GPIO_H_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_H_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR5_SHIFT)
+#define GPIO_H_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_H_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR4_SHIFT)
+#define GPIO_H_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_H_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR3_SHIFT)
+#define GPIO_H_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_H_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR2_SHIFT)
+#define GPIO_H_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_H_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR1_SHIFT)
+#define GPIO_H_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_H_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_PR0_SHIFT)
+#define GPIO_H_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_H_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G7W_SHIFT)
+#define GPIO_H_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_H_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G6W_SHIFT)
+#define GPIO_H_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_H_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G5W_SHIFT)
+#define GPIO_H_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_H_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G4W_SHIFT)
+#define GPIO_H_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_H_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G3W_SHIFT)
+#define GPIO_H_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_H_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G2W_SHIFT)
+#define GPIO_H_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_H_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G1W_SHIFT)
+#define GPIO_H_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_H_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G0W_SHIFT)
+#define GPIO_H_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_H_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G7R_SHIFT)
+#define GPIO_H_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_H_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G6R_SHIFT)
+#define GPIO_H_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_H_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G5R_SHIFT)
+#define GPIO_H_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_H_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G4R_SHIFT)
+#define GPIO_H_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_H_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G3R_SHIFT)
+#define GPIO_H_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_H_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G2R_SHIFT)
+#define GPIO_H_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_H_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G1R_SHIFT)
+#define GPIO_H_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_H_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_01_0_G0R_SHIFT)
+#define GPIO_H_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_H_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_H_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_VM_02_0
+#define GPIO_H_VM_02_0                  MK_ADDR_CONST(0x4050)
+#define GPIO_H_VM_02_0_SECURE                   0x0
+#define GPIO_H_VM_02_0_DUAL                     0x0
+#define GPIO_H_VM_02_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_H_VM_02_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_H_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_H_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_H_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM1_SHIFT)
+#define GPIO_H_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_H_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_H_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_H_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_H_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_H_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM2_SHIFT)
+#define GPIO_H_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_H_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_H_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_H_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_H_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_H_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM3_SHIFT)
+#define GPIO_H_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_H_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_H_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_H_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_H_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_H_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM4_SHIFT)
+#define GPIO_H_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_H_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_H_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_H_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_H_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_H_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM5_SHIFT)
+#define GPIO_H_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_H_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_H_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_H_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_H_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_H_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM6_SHIFT)
+#define GPIO_H_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_H_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_H_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_H_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_H_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_H_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM7_SHIFT)
+#define GPIO_H_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_H_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_H_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_H_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_H_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_H_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_02_0_VM8_SHIFT)
+#define GPIO_H_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_H_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_H_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_H_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_H_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_SCR_02_0
+#define GPIO_H_SCR_02_0                 MK_ADDR_CONST(0x4054)
+#define GPIO_H_SCR_02_0_SECURE                  0x0
+#define GPIO_H_SCR_02_0_DUAL                    0x0
+#define GPIO_H_SCR_02_0_SCR                     0
+#define GPIO_H_SCR_02_0_SCRREG                  0
+#define GPIO_H_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_H_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_H_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_H_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_H_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_H_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_H_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_H_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_H_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_H_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_H_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_H_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_H_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_H_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_H_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_H_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_H_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_H_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_H_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR7_SHIFT)
+#define GPIO_H_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_H_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR6_SHIFT)
+#define GPIO_H_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_H_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR5_SHIFT)
+#define GPIO_H_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_H_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR4_SHIFT)
+#define GPIO_H_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_H_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR3_SHIFT)
+#define GPIO_H_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_H_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR2_SHIFT)
+#define GPIO_H_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_H_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR1_SHIFT)
+#define GPIO_H_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_H_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_PR0_SHIFT)
+#define GPIO_H_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_H_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G7W_SHIFT)
+#define GPIO_H_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_H_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G6W_SHIFT)
+#define GPIO_H_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_H_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G5W_SHIFT)
+#define GPIO_H_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_H_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G4W_SHIFT)
+#define GPIO_H_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_H_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G3W_SHIFT)
+#define GPIO_H_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_H_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G2W_SHIFT)
+#define GPIO_H_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_H_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G1W_SHIFT)
+#define GPIO_H_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_H_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G0W_SHIFT)
+#define GPIO_H_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_H_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G7R_SHIFT)
+#define GPIO_H_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_H_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G6R_SHIFT)
+#define GPIO_H_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_H_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G5R_SHIFT)
+#define GPIO_H_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_H_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G4R_SHIFT)
+#define GPIO_H_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_H_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G3R_SHIFT)
+#define GPIO_H_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_H_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G2R_SHIFT)
+#define GPIO_H_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_H_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G1R_SHIFT)
+#define GPIO_H_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_H_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_02_0_G0R_SHIFT)
+#define GPIO_H_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_H_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_H_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_VM_03_0
+#define GPIO_H_VM_03_0                  MK_ADDR_CONST(0x4058)
+#define GPIO_H_VM_03_0_SECURE                   0x0
+#define GPIO_H_VM_03_0_DUAL                     0x0
+#define GPIO_H_VM_03_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_H_VM_03_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_H_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_H_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_H_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM1_SHIFT)
+#define GPIO_H_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_H_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_H_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_H_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_H_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_H_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM2_SHIFT)
+#define GPIO_H_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_H_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_H_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_H_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_H_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_H_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM3_SHIFT)
+#define GPIO_H_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_H_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_H_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_H_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_H_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_H_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM4_SHIFT)
+#define GPIO_H_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_H_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_H_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_H_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_H_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_H_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM5_SHIFT)
+#define GPIO_H_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_H_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_H_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_H_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_H_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_H_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM6_SHIFT)
+#define GPIO_H_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_H_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_H_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_H_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_H_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_H_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM7_SHIFT)
+#define GPIO_H_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_H_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_H_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_H_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_H_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_H_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_03_0_VM8_SHIFT)
+#define GPIO_H_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_H_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_H_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_H_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_H_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_SCR_03_0
+#define GPIO_H_SCR_03_0                 MK_ADDR_CONST(0x405c)
+#define GPIO_H_SCR_03_0_SECURE                  0x0
+#define GPIO_H_SCR_03_0_DUAL                    0x0
+#define GPIO_H_SCR_03_0_SCR                     0
+#define GPIO_H_SCR_03_0_SCRREG                  0
+#define GPIO_H_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_H_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_H_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_H_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_H_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_H_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_H_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_H_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_H_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_H_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_H_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_H_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_H_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_H_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_H_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_H_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_H_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_H_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_H_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR7_SHIFT)
+#define GPIO_H_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_H_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR6_SHIFT)
+#define GPIO_H_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_H_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR5_SHIFT)
+#define GPIO_H_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_H_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR4_SHIFT)
+#define GPIO_H_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_H_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR3_SHIFT)
+#define GPIO_H_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_H_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR2_SHIFT)
+#define GPIO_H_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_H_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR1_SHIFT)
+#define GPIO_H_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_H_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_PR0_SHIFT)
+#define GPIO_H_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_H_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G7W_SHIFT)
+#define GPIO_H_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_H_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G6W_SHIFT)
+#define GPIO_H_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_H_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G5W_SHIFT)
+#define GPIO_H_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_H_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G4W_SHIFT)
+#define GPIO_H_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_H_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G3W_SHIFT)
+#define GPIO_H_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_H_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G2W_SHIFT)
+#define GPIO_H_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_H_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G1W_SHIFT)
+#define GPIO_H_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_H_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G0W_SHIFT)
+#define GPIO_H_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_H_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G7R_SHIFT)
+#define GPIO_H_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_H_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G6R_SHIFT)
+#define GPIO_H_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_H_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G5R_SHIFT)
+#define GPIO_H_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_H_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G4R_SHIFT)
+#define GPIO_H_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_H_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G3R_SHIFT)
+#define GPIO_H_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_H_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G2R_SHIFT)
+#define GPIO_H_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_H_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G1R_SHIFT)
+#define GPIO_H_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_H_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_03_0_G0R_SHIFT)
+#define GPIO_H_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_H_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_H_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_VM_04_0
+#define GPIO_H_VM_04_0                  MK_ADDR_CONST(0x4060)
+#define GPIO_H_VM_04_0_SECURE                   0x0
+#define GPIO_H_VM_04_0_DUAL                     0x0
+#define GPIO_H_VM_04_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_H_VM_04_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_H_VM_04_0_WORD_COUNT                       0x1
+#define GPIO_H_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_H_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM1_SHIFT)
+#define GPIO_H_VM_04_0_VM1_RANGE                        1:0
+#define GPIO_H_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_H_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_H_VM_04_0_VM1_WOFFSET                      0x0
+#define GPIO_H_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_H_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM2_SHIFT)
+#define GPIO_H_VM_04_0_VM2_RANGE                        3:2
+#define GPIO_H_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_H_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_H_VM_04_0_VM2_WOFFSET                      0x0
+#define GPIO_H_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_H_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM3_SHIFT)
+#define GPIO_H_VM_04_0_VM3_RANGE                        5:4
+#define GPIO_H_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_H_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_H_VM_04_0_VM3_WOFFSET                      0x0
+#define GPIO_H_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_H_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM4_SHIFT)
+#define GPIO_H_VM_04_0_VM4_RANGE                        7:6
+#define GPIO_H_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_H_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_H_VM_04_0_VM4_WOFFSET                      0x0
+#define GPIO_H_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_H_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM5_SHIFT)
+#define GPIO_H_VM_04_0_VM5_RANGE                        9:8
+#define GPIO_H_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_H_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_H_VM_04_0_VM5_WOFFSET                      0x0
+#define GPIO_H_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_H_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM6_SHIFT)
+#define GPIO_H_VM_04_0_VM6_RANGE                        11:10
+#define GPIO_H_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_H_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_H_VM_04_0_VM6_WOFFSET                      0x0
+#define GPIO_H_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_H_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM7_SHIFT)
+#define GPIO_H_VM_04_0_VM7_RANGE                        13:12
+#define GPIO_H_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_H_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_H_VM_04_0_VM7_WOFFSET                      0x0
+#define GPIO_H_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_H_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_04_0_VM8_SHIFT)
+#define GPIO_H_VM_04_0_VM8_RANGE                        15:14
+#define GPIO_H_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_H_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_H_VM_04_0_VM8_WOFFSET                      0x0
+#define GPIO_H_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_SCR_04_0
+#define GPIO_H_SCR_04_0                 MK_ADDR_CONST(0x4064)
+#define GPIO_H_SCR_04_0_SECURE                  0x0
+#define GPIO_H_SCR_04_0_DUAL                    0x0
+#define GPIO_H_SCR_04_0_SCR                     0
+#define GPIO_H_SCR_04_0_SCRREG                  0
+#define GPIO_H_SCR_04_0_WORD_COUNT                      0x1
+#define GPIO_H_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_H_SCR_04_0_SEC_LCK_RANGE                   29:29
+#define GPIO_H_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_04_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_H_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_H_SCR_04_0_SEC_WEN_RANGE                   28:28
+#define GPIO_H_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_04_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_H_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_H_SCR_04_0_SEC_REN_RANGE                   27:27
+#define GPIO_H_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_04_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_H_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_H_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_H_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_H_SCR_04_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_H_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_H_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_H_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_H_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_H_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR7_SHIFT)
+#define GPIO_H_SCR_04_0_PR7_RANGE                       23:23
+#define GPIO_H_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_04_0_PR7_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR6_SHIFT)
+#define GPIO_H_SCR_04_0_PR6_RANGE                       22:22
+#define GPIO_H_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_04_0_PR6_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR5_SHIFT)
+#define GPIO_H_SCR_04_0_PR5_RANGE                       21:21
+#define GPIO_H_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_04_0_PR5_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR4_SHIFT)
+#define GPIO_H_SCR_04_0_PR4_RANGE                       20:20
+#define GPIO_H_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_04_0_PR4_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR3_SHIFT)
+#define GPIO_H_SCR_04_0_PR3_RANGE                       19:19
+#define GPIO_H_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_04_0_PR3_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR2_SHIFT)
+#define GPIO_H_SCR_04_0_PR2_RANGE                       18:18
+#define GPIO_H_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_04_0_PR2_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR1_SHIFT)
+#define GPIO_H_SCR_04_0_PR1_RANGE                       17:17
+#define GPIO_H_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_04_0_PR1_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_PR0_SHIFT)
+#define GPIO_H_SCR_04_0_PR0_RANGE                       16:16
+#define GPIO_H_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_04_0_PR0_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G7W_SHIFT)
+#define GPIO_H_SCR_04_0_G7W_RANGE                       15:15
+#define GPIO_H_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_04_0_G7W_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G6W_SHIFT)
+#define GPIO_H_SCR_04_0_G6W_RANGE                       14:14
+#define GPIO_H_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_04_0_G6W_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G5W_SHIFT)
+#define GPIO_H_SCR_04_0_G5W_RANGE                       13:13
+#define GPIO_H_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_04_0_G5W_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G4W_SHIFT)
+#define GPIO_H_SCR_04_0_G4W_RANGE                       12:12
+#define GPIO_H_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_04_0_G4W_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G3W_SHIFT)
+#define GPIO_H_SCR_04_0_G3W_RANGE                       11:11
+#define GPIO_H_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_04_0_G3W_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G2W_SHIFT)
+#define GPIO_H_SCR_04_0_G2W_RANGE                       10:10
+#define GPIO_H_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_04_0_G2W_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G1W_SHIFT)
+#define GPIO_H_SCR_04_0_G1W_RANGE                       9:9
+#define GPIO_H_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_04_0_G1W_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G0W_SHIFT)
+#define GPIO_H_SCR_04_0_G0W_RANGE                       8:8
+#define GPIO_H_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_04_0_G0W_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G7R_SHIFT)
+#define GPIO_H_SCR_04_0_G7R_RANGE                       7:7
+#define GPIO_H_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_04_0_G7R_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G6R_SHIFT)
+#define GPIO_H_SCR_04_0_G6R_RANGE                       6:6
+#define GPIO_H_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_04_0_G6R_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G5R_SHIFT)
+#define GPIO_H_SCR_04_0_G5R_RANGE                       5:5
+#define GPIO_H_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_04_0_G5R_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G4R_SHIFT)
+#define GPIO_H_SCR_04_0_G4R_RANGE                       4:4
+#define GPIO_H_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_04_0_G4R_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G3R_SHIFT)
+#define GPIO_H_SCR_04_0_G3R_RANGE                       3:3
+#define GPIO_H_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_04_0_G3R_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G2R_SHIFT)
+#define GPIO_H_SCR_04_0_G2R_RANGE                       2:2
+#define GPIO_H_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_04_0_G2R_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G1R_SHIFT)
+#define GPIO_H_SCR_04_0_G1R_RANGE                       1:1
+#define GPIO_H_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_04_0_G1R_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_04_0_G0R_SHIFT)
+#define GPIO_H_SCR_04_0_G0R_RANGE                       0:0
+#define GPIO_H_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_04_0_G0R_WOFFSET                     0x0
+#define GPIO_H_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_VM_05_0
+#define GPIO_H_VM_05_0                  MK_ADDR_CONST(0x4068)
+#define GPIO_H_VM_05_0_SECURE                   0x0
+#define GPIO_H_VM_05_0_DUAL                     0x0
+#define GPIO_H_VM_05_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_H_VM_05_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_H_VM_05_0_WORD_COUNT                       0x1
+#define GPIO_H_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_H_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM1_SHIFT)
+#define GPIO_H_VM_05_0_VM1_RANGE                        1:0
+#define GPIO_H_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_H_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_H_VM_05_0_VM1_WOFFSET                      0x0
+#define GPIO_H_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_H_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM2_SHIFT)
+#define GPIO_H_VM_05_0_VM2_RANGE                        3:2
+#define GPIO_H_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_H_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_H_VM_05_0_VM2_WOFFSET                      0x0
+#define GPIO_H_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_H_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM3_SHIFT)
+#define GPIO_H_VM_05_0_VM3_RANGE                        5:4
+#define GPIO_H_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_H_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_H_VM_05_0_VM3_WOFFSET                      0x0
+#define GPIO_H_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_H_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM4_SHIFT)
+#define GPIO_H_VM_05_0_VM4_RANGE                        7:6
+#define GPIO_H_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_H_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_H_VM_05_0_VM4_WOFFSET                      0x0
+#define GPIO_H_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_H_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM5_SHIFT)
+#define GPIO_H_VM_05_0_VM5_RANGE                        9:8
+#define GPIO_H_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_H_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_H_VM_05_0_VM5_WOFFSET                      0x0
+#define GPIO_H_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_H_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM6_SHIFT)
+#define GPIO_H_VM_05_0_VM6_RANGE                        11:10
+#define GPIO_H_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_H_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_H_VM_05_0_VM6_WOFFSET                      0x0
+#define GPIO_H_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_H_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM7_SHIFT)
+#define GPIO_H_VM_05_0_VM7_RANGE                        13:12
+#define GPIO_H_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_H_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_H_VM_05_0_VM7_WOFFSET                      0x0
+#define GPIO_H_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_H_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_05_0_VM8_SHIFT)
+#define GPIO_H_VM_05_0_VM8_RANGE                        15:14
+#define GPIO_H_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_H_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_H_VM_05_0_VM8_WOFFSET                      0x0
+#define GPIO_H_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_SCR_05_0
+#define GPIO_H_SCR_05_0                 MK_ADDR_CONST(0x406c)
+#define GPIO_H_SCR_05_0_SECURE                  0x0
+#define GPIO_H_SCR_05_0_DUAL                    0x0
+#define GPIO_H_SCR_05_0_SCR                     0
+#define GPIO_H_SCR_05_0_SCRREG                  0
+#define GPIO_H_SCR_05_0_WORD_COUNT                      0x1
+#define GPIO_H_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_H_SCR_05_0_SEC_LCK_RANGE                   29:29
+#define GPIO_H_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_05_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_H_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_H_SCR_05_0_SEC_WEN_RANGE                   28:28
+#define GPIO_H_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_05_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_H_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_H_SCR_05_0_SEC_REN_RANGE                   27:27
+#define GPIO_H_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_05_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_H_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_H_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_H_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_H_SCR_05_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_H_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_H_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_H_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_H_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_H_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR7_SHIFT)
+#define GPIO_H_SCR_05_0_PR7_RANGE                       23:23
+#define GPIO_H_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_05_0_PR7_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR6_SHIFT)
+#define GPIO_H_SCR_05_0_PR6_RANGE                       22:22
+#define GPIO_H_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_05_0_PR6_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR5_SHIFT)
+#define GPIO_H_SCR_05_0_PR5_RANGE                       21:21
+#define GPIO_H_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_05_0_PR5_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR4_SHIFT)
+#define GPIO_H_SCR_05_0_PR4_RANGE                       20:20
+#define GPIO_H_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_05_0_PR4_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR3_SHIFT)
+#define GPIO_H_SCR_05_0_PR3_RANGE                       19:19
+#define GPIO_H_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_05_0_PR3_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR2_SHIFT)
+#define GPIO_H_SCR_05_0_PR2_RANGE                       18:18
+#define GPIO_H_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_05_0_PR2_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR1_SHIFT)
+#define GPIO_H_SCR_05_0_PR1_RANGE                       17:17
+#define GPIO_H_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_05_0_PR1_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_PR0_SHIFT)
+#define GPIO_H_SCR_05_0_PR0_RANGE                       16:16
+#define GPIO_H_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_05_0_PR0_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G7W_SHIFT)
+#define GPIO_H_SCR_05_0_G7W_RANGE                       15:15
+#define GPIO_H_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_05_0_G7W_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G6W_SHIFT)
+#define GPIO_H_SCR_05_0_G6W_RANGE                       14:14
+#define GPIO_H_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_05_0_G6W_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G5W_SHIFT)
+#define GPIO_H_SCR_05_0_G5W_RANGE                       13:13
+#define GPIO_H_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_05_0_G5W_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G4W_SHIFT)
+#define GPIO_H_SCR_05_0_G4W_RANGE                       12:12
+#define GPIO_H_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_05_0_G4W_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G3W_SHIFT)
+#define GPIO_H_SCR_05_0_G3W_RANGE                       11:11
+#define GPIO_H_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_05_0_G3W_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G2W_SHIFT)
+#define GPIO_H_SCR_05_0_G2W_RANGE                       10:10
+#define GPIO_H_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_05_0_G2W_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G1W_SHIFT)
+#define GPIO_H_SCR_05_0_G1W_RANGE                       9:9
+#define GPIO_H_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_05_0_G1W_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G0W_SHIFT)
+#define GPIO_H_SCR_05_0_G0W_RANGE                       8:8
+#define GPIO_H_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_05_0_G0W_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G7R_SHIFT)
+#define GPIO_H_SCR_05_0_G7R_RANGE                       7:7
+#define GPIO_H_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_05_0_G7R_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G6R_SHIFT)
+#define GPIO_H_SCR_05_0_G6R_RANGE                       6:6
+#define GPIO_H_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_05_0_G6R_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G5R_SHIFT)
+#define GPIO_H_SCR_05_0_G5R_RANGE                       5:5
+#define GPIO_H_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_05_0_G5R_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G4R_SHIFT)
+#define GPIO_H_SCR_05_0_G4R_RANGE                       4:4
+#define GPIO_H_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_05_0_G4R_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G3R_SHIFT)
+#define GPIO_H_SCR_05_0_G3R_RANGE                       3:3
+#define GPIO_H_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_05_0_G3R_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G2R_SHIFT)
+#define GPIO_H_SCR_05_0_G2R_RANGE                       2:2
+#define GPIO_H_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_05_0_G2R_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G1R_SHIFT)
+#define GPIO_H_SCR_05_0_G1R_RANGE                       1:1
+#define GPIO_H_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_05_0_G1R_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_05_0_G0R_SHIFT)
+#define GPIO_H_SCR_05_0_G0R_RANGE                       0:0
+#define GPIO_H_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_05_0_G0R_WOFFSET                     0x0
+#define GPIO_H_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_VM_06_0
+#define GPIO_H_VM_06_0                  MK_ADDR_CONST(0x4070)
+#define GPIO_H_VM_06_0_SECURE                   0x0
+#define GPIO_H_VM_06_0_DUAL                     0x0
+#define GPIO_H_VM_06_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_H_VM_06_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_H_VM_06_0_WORD_COUNT                       0x1
+#define GPIO_H_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_H_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM1_SHIFT)
+#define GPIO_H_VM_06_0_VM1_RANGE                        1:0
+#define GPIO_H_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_H_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_H_VM_06_0_VM1_WOFFSET                      0x0
+#define GPIO_H_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_H_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM2_SHIFT)
+#define GPIO_H_VM_06_0_VM2_RANGE                        3:2
+#define GPIO_H_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_H_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_H_VM_06_0_VM2_WOFFSET                      0x0
+#define GPIO_H_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_H_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM3_SHIFT)
+#define GPIO_H_VM_06_0_VM3_RANGE                        5:4
+#define GPIO_H_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_H_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_H_VM_06_0_VM3_WOFFSET                      0x0
+#define GPIO_H_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_H_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM4_SHIFT)
+#define GPIO_H_VM_06_0_VM4_RANGE                        7:6
+#define GPIO_H_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_H_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_H_VM_06_0_VM4_WOFFSET                      0x0
+#define GPIO_H_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_H_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM5_SHIFT)
+#define GPIO_H_VM_06_0_VM5_RANGE                        9:8
+#define GPIO_H_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_H_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_H_VM_06_0_VM5_WOFFSET                      0x0
+#define GPIO_H_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_H_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM6_SHIFT)
+#define GPIO_H_VM_06_0_VM6_RANGE                        11:10
+#define GPIO_H_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_H_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_H_VM_06_0_VM6_WOFFSET                      0x0
+#define GPIO_H_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_H_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM7_SHIFT)
+#define GPIO_H_VM_06_0_VM7_RANGE                        13:12
+#define GPIO_H_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_H_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_H_VM_06_0_VM7_WOFFSET                      0x0
+#define GPIO_H_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_H_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_06_0_VM8_SHIFT)
+#define GPIO_H_VM_06_0_VM8_RANGE                        15:14
+#define GPIO_H_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_H_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_H_VM_06_0_VM8_WOFFSET                      0x0
+#define GPIO_H_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_SCR_06_0
+#define GPIO_H_SCR_06_0                 MK_ADDR_CONST(0x4074)
+#define GPIO_H_SCR_06_0_SECURE                  0x0
+#define GPIO_H_SCR_06_0_DUAL                    0x0
+#define GPIO_H_SCR_06_0_SCR                     0
+#define GPIO_H_SCR_06_0_SCRREG                  0
+#define GPIO_H_SCR_06_0_WORD_COUNT                      0x1
+#define GPIO_H_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_SEC_LCK_SHIFT)
+#define GPIO_H_SCR_06_0_SEC_LCK_RANGE                   29:29
+#define GPIO_H_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_06_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_H_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_SEC_WEN_SHIFT)
+#define GPIO_H_SCR_06_0_SEC_WEN_RANGE                   28:28
+#define GPIO_H_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_06_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_H_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_SEC_REN_SHIFT)
+#define GPIO_H_SCR_06_0_SEC_REN_RANGE                   27:27
+#define GPIO_H_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_06_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_H_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_H_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_H_SCR_06_0_SEC_OWNER_SHIFT)
+#define GPIO_H_SCR_06_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_H_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_H_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_H_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_H_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_H_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR7_SHIFT)
+#define GPIO_H_SCR_06_0_PR7_RANGE                       23:23
+#define GPIO_H_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_06_0_PR7_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR6_SHIFT)
+#define GPIO_H_SCR_06_0_PR6_RANGE                       22:22
+#define GPIO_H_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_06_0_PR6_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR5_SHIFT)
+#define GPIO_H_SCR_06_0_PR5_RANGE                       21:21
+#define GPIO_H_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_06_0_PR5_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR4_SHIFT)
+#define GPIO_H_SCR_06_0_PR4_RANGE                       20:20
+#define GPIO_H_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_06_0_PR4_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR3_SHIFT)
+#define GPIO_H_SCR_06_0_PR3_RANGE                       19:19
+#define GPIO_H_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_06_0_PR3_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR2_SHIFT)
+#define GPIO_H_SCR_06_0_PR2_RANGE                       18:18
+#define GPIO_H_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_06_0_PR2_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR1_SHIFT)
+#define GPIO_H_SCR_06_0_PR1_RANGE                       17:17
+#define GPIO_H_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_06_0_PR1_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_PR0_SHIFT)
+#define GPIO_H_SCR_06_0_PR0_RANGE                       16:16
+#define GPIO_H_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_06_0_PR0_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G7W_SHIFT)
+#define GPIO_H_SCR_06_0_G7W_RANGE                       15:15
+#define GPIO_H_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_06_0_G7W_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G6W_SHIFT)
+#define GPIO_H_SCR_06_0_G6W_RANGE                       14:14
+#define GPIO_H_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_06_0_G6W_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G5W_SHIFT)
+#define GPIO_H_SCR_06_0_G5W_RANGE                       13:13
+#define GPIO_H_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_06_0_G5W_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G4W_SHIFT)
+#define GPIO_H_SCR_06_0_G4W_RANGE                       12:12
+#define GPIO_H_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_06_0_G4W_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G3W_SHIFT)
+#define GPIO_H_SCR_06_0_G3W_RANGE                       11:11
+#define GPIO_H_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_06_0_G3W_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G2W_SHIFT)
+#define GPIO_H_SCR_06_0_G2W_RANGE                       10:10
+#define GPIO_H_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_06_0_G2W_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G1W_SHIFT)
+#define GPIO_H_SCR_06_0_G1W_RANGE                       9:9
+#define GPIO_H_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_06_0_G1W_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G0W_SHIFT)
+#define GPIO_H_SCR_06_0_G0W_RANGE                       8:8
+#define GPIO_H_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_06_0_G0W_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G7R_SHIFT)
+#define GPIO_H_SCR_06_0_G7R_RANGE                       7:7
+#define GPIO_H_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_06_0_G7R_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G6R_SHIFT)
+#define GPIO_H_SCR_06_0_G6R_RANGE                       6:6
+#define GPIO_H_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_06_0_G6R_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G5R_SHIFT)
+#define GPIO_H_SCR_06_0_G5R_RANGE                       5:5
+#define GPIO_H_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_06_0_G5R_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G4R_SHIFT)
+#define GPIO_H_SCR_06_0_G4R_RANGE                       4:4
+#define GPIO_H_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_06_0_G4R_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G3R_SHIFT)
+#define GPIO_H_SCR_06_0_G3R_RANGE                       3:3
+#define GPIO_H_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_06_0_G3R_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G2R_SHIFT)
+#define GPIO_H_SCR_06_0_G2R_RANGE                       2:2
+#define GPIO_H_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_06_0_G2R_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G1R_SHIFT)
+#define GPIO_H_SCR_06_0_G1R_RANGE                       1:1
+#define GPIO_H_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_06_0_G1R_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_06_0_G0R_SHIFT)
+#define GPIO_H_SCR_06_0_G0R_RANGE                       0:0
+#define GPIO_H_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_06_0_G0R_WOFFSET                     0x0
+#define GPIO_H_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_VM_07_0
+#define GPIO_H_VM_07_0                  MK_ADDR_CONST(0x4078)
+#define GPIO_H_VM_07_0_SECURE                   0x0
+#define GPIO_H_VM_07_0_DUAL                     0x0
+#define GPIO_H_VM_07_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_H_VM_07_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_H_VM_07_0_WORD_COUNT                       0x1
+#define GPIO_H_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_H_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_H_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM1_SHIFT)
+#define GPIO_H_VM_07_0_VM1_RANGE                        1:0
+#define GPIO_H_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_H_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_H_VM_07_0_VM1_WOFFSET                      0x0
+#define GPIO_H_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_H_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM2_SHIFT)
+#define GPIO_H_VM_07_0_VM2_RANGE                        3:2
+#define GPIO_H_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_H_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_H_VM_07_0_VM2_WOFFSET                      0x0
+#define GPIO_H_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_H_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM3_SHIFT)
+#define GPIO_H_VM_07_0_VM3_RANGE                        5:4
+#define GPIO_H_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_H_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_H_VM_07_0_VM3_WOFFSET                      0x0
+#define GPIO_H_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_H_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM4_SHIFT)
+#define GPIO_H_VM_07_0_VM4_RANGE                        7:6
+#define GPIO_H_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_H_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_H_VM_07_0_VM4_WOFFSET                      0x0
+#define GPIO_H_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_H_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM5_SHIFT)
+#define GPIO_H_VM_07_0_VM5_RANGE                        9:8
+#define GPIO_H_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_H_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_H_VM_07_0_VM5_WOFFSET                      0x0
+#define GPIO_H_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_H_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM6_SHIFT)
+#define GPIO_H_VM_07_0_VM6_RANGE                        11:10
+#define GPIO_H_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_H_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_H_VM_07_0_VM6_WOFFSET                      0x0
+#define GPIO_H_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_H_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM7_SHIFT)
+#define GPIO_H_VM_07_0_VM7_RANGE                        13:12
+#define GPIO_H_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_H_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_H_VM_07_0_VM7_WOFFSET                      0x0
+#define GPIO_H_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_H_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_H_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_H_VM_07_0_VM8_SHIFT)
+#define GPIO_H_VM_07_0_VM8_RANGE                        15:14
+#define GPIO_H_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_H_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_H_VM_07_0_VM8_WOFFSET                      0x0
+#define GPIO_H_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_H_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_H_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_SCR_07_0
+#define GPIO_H_SCR_07_0                 MK_ADDR_CONST(0x407c)
+#define GPIO_H_SCR_07_0_SECURE                  0x0
+#define GPIO_H_SCR_07_0_DUAL                    0x0
+#define GPIO_H_SCR_07_0_SCR                     0
+#define GPIO_H_SCR_07_0_SCRREG                  0
+#define GPIO_H_SCR_07_0_WORD_COUNT                      0x1
+#define GPIO_H_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_H_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_SEC_LCK_SHIFT)
+#define GPIO_H_SCR_07_0_SEC_LCK_RANGE                   29:29
+#define GPIO_H_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_H_SCR_07_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_H_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_SEC_WEN_SHIFT)
+#define GPIO_H_SCR_07_0_SEC_WEN_RANGE                   28:28
+#define GPIO_H_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_H_SCR_07_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_H_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_SEC_REN_SHIFT)
+#define GPIO_H_SCR_07_0_SEC_REN_RANGE                   27:27
+#define GPIO_H_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_H_SCR_07_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_H_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_H_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_H_SCR_07_0_SEC_OWNER_SHIFT)
+#define GPIO_H_SCR_07_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_H_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_H_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_H_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_H_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_H_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR7_SHIFT)
+#define GPIO_H_SCR_07_0_PR7_RANGE                       23:23
+#define GPIO_H_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_H_SCR_07_0_PR7_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR6_SHIFT)
+#define GPIO_H_SCR_07_0_PR6_RANGE                       22:22
+#define GPIO_H_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_H_SCR_07_0_PR6_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR5_SHIFT)
+#define GPIO_H_SCR_07_0_PR5_RANGE                       21:21
+#define GPIO_H_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_H_SCR_07_0_PR5_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR4_SHIFT)
+#define GPIO_H_SCR_07_0_PR4_RANGE                       20:20
+#define GPIO_H_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_H_SCR_07_0_PR4_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR3_SHIFT)
+#define GPIO_H_SCR_07_0_PR3_RANGE                       19:19
+#define GPIO_H_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_H_SCR_07_0_PR3_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR2_SHIFT)
+#define GPIO_H_SCR_07_0_PR2_RANGE                       18:18
+#define GPIO_H_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_H_SCR_07_0_PR2_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR1_SHIFT)
+#define GPIO_H_SCR_07_0_PR1_RANGE                       17:17
+#define GPIO_H_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_H_SCR_07_0_PR1_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_PR0_SHIFT)
+#define GPIO_H_SCR_07_0_PR0_RANGE                       16:16
+#define GPIO_H_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_H_SCR_07_0_PR0_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G7W_SHIFT)
+#define GPIO_H_SCR_07_0_G7W_RANGE                       15:15
+#define GPIO_H_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_H_SCR_07_0_G7W_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G6W_SHIFT)
+#define GPIO_H_SCR_07_0_G6W_RANGE                       14:14
+#define GPIO_H_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_H_SCR_07_0_G6W_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G5W_SHIFT)
+#define GPIO_H_SCR_07_0_G5W_RANGE                       13:13
+#define GPIO_H_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_H_SCR_07_0_G5W_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G4W_SHIFT)
+#define GPIO_H_SCR_07_0_G4W_RANGE                       12:12
+#define GPIO_H_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_H_SCR_07_0_G4W_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G3W_SHIFT)
+#define GPIO_H_SCR_07_0_G3W_RANGE                       11:11
+#define GPIO_H_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_H_SCR_07_0_G3W_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G2W_SHIFT)
+#define GPIO_H_SCR_07_0_G2W_RANGE                       10:10
+#define GPIO_H_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_H_SCR_07_0_G2W_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G1W_SHIFT)
+#define GPIO_H_SCR_07_0_G1W_RANGE                       9:9
+#define GPIO_H_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_H_SCR_07_0_G1W_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G0W_SHIFT)
+#define GPIO_H_SCR_07_0_G0W_RANGE                       8:8
+#define GPIO_H_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_H_SCR_07_0_G0W_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G7R_SHIFT)
+#define GPIO_H_SCR_07_0_G7R_RANGE                       7:7
+#define GPIO_H_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_H_SCR_07_0_G7R_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G6R_SHIFT)
+#define GPIO_H_SCR_07_0_G6R_RANGE                       6:6
+#define GPIO_H_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_H_SCR_07_0_G6R_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G5R_SHIFT)
+#define GPIO_H_SCR_07_0_G5R_RANGE                       5:5
+#define GPIO_H_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_SCR_07_0_G5R_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G4R_SHIFT)
+#define GPIO_H_SCR_07_0_G4R_RANGE                       4:4
+#define GPIO_H_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_H_SCR_07_0_G4R_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G3R_SHIFT)
+#define GPIO_H_SCR_07_0_G3R_RANGE                       3:3
+#define GPIO_H_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_H_SCR_07_0_G3R_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G2R_SHIFT)
+#define GPIO_H_SCR_07_0_G2R_RANGE                       2:2
+#define GPIO_H_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_H_SCR_07_0_G2R_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G1R_SHIFT)
+#define GPIO_H_SCR_07_0_G1R_RANGE                       1:1
+#define GPIO_H_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_H_SCR_07_0_G1R_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_H_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_SCR_07_0_G0R_SHIFT)
+#define GPIO_H_SCR_07_0_G0R_RANGE                       0:0
+#define GPIO_H_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_SCR_07_0_G0R_WOFFSET                     0x0
+#define GPIO_H_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_H_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_VM_00_0
+#define GPIO_I_VM_00_0                  MK_ADDR_CONST(0x4080)
+#define GPIO_I_VM_00_0_SECURE                   0x0
+#define GPIO_I_VM_00_0_DUAL                     0x0
+#define GPIO_I_VM_00_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_I_VM_00_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_I_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_I_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_I_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM1_SHIFT)
+#define GPIO_I_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_I_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_I_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_I_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_I_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_I_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM2_SHIFT)
+#define GPIO_I_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_I_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_I_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_I_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_I_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_I_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM3_SHIFT)
+#define GPIO_I_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_I_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_I_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_I_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_I_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_I_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM4_SHIFT)
+#define GPIO_I_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_I_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_I_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_I_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_I_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_I_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM5_SHIFT)
+#define GPIO_I_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_I_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_I_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_I_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_I_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_I_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM6_SHIFT)
+#define GPIO_I_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_I_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_I_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_I_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_I_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_I_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM7_SHIFT)
+#define GPIO_I_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_I_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_I_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_I_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_I_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_I_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_00_0_VM8_SHIFT)
+#define GPIO_I_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_I_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_I_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_I_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_I_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_SCR_00_0
+#define GPIO_I_SCR_00_0                 MK_ADDR_CONST(0x4084)
+#define GPIO_I_SCR_00_0_SECURE                  0x0
+#define GPIO_I_SCR_00_0_DUAL                    0x0
+#define GPIO_I_SCR_00_0_SCR                     0
+#define GPIO_I_SCR_00_0_SCRREG                  0
+#define GPIO_I_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_I_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_I_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_I_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_I_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_I_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_I_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_I_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_I_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_I_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_I_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_I_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_I_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_I_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_I_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_I_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_I_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_I_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_I_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR7_SHIFT)
+#define GPIO_I_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_I_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR6_SHIFT)
+#define GPIO_I_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_I_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR5_SHIFT)
+#define GPIO_I_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_I_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR4_SHIFT)
+#define GPIO_I_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_I_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR3_SHIFT)
+#define GPIO_I_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_I_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR2_SHIFT)
+#define GPIO_I_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_I_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR1_SHIFT)
+#define GPIO_I_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_I_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_PR0_SHIFT)
+#define GPIO_I_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_I_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G7W_SHIFT)
+#define GPIO_I_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_I_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G6W_SHIFT)
+#define GPIO_I_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_I_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G5W_SHIFT)
+#define GPIO_I_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_I_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G4W_SHIFT)
+#define GPIO_I_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_I_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G3W_SHIFT)
+#define GPIO_I_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_I_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G2W_SHIFT)
+#define GPIO_I_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_I_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G1W_SHIFT)
+#define GPIO_I_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_I_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G0W_SHIFT)
+#define GPIO_I_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_I_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G7R_SHIFT)
+#define GPIO_I_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_I_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G6R_SHIFT)
+#define GPIO_I_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_I_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G5R_SHIFT)
+#define GPIO_I_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_I_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G4R_SHIFT)
+#define GPIO_I_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_I_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G3R_SHIFT)
+#define GPIO_I_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_I_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G2R_SHIFT)
+#define GPIO_I_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_I_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G1R_SHIFT)
+#define GPIO_I_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_I_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_00_0_G0R_SHIFT)
+#define GPIO_I_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_I_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_I_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_VM_01_0
+#define GPIO_I_VM_01_0                  MK_ADDR_CONST(0x4088)
+#define GPIO_I_VM_01_0_SECURE                   0x0
+#define GPIO_I_VM_01_0_DUAL                     0x0
+#define GPIO_I_VM_01_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_I_VM_01_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_I_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_I_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_I_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM1_SHIFT)
+#define GPIO_I_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_I_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_I_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_I_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_I_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_I_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM2_SHIFT)
+#define GPIO_I_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_I_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_I_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_I_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_I_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_I_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM3_SHIFT)
+#define GPIO_I_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_I_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_I_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_I_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_I_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_I_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM4_SHIFT)
+#define GPIO_I_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_I_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_I_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_I_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_I_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_I_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM5_SHIFT)
+#define GPIO_I_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_I_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_I_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_I_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_I_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_I_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM6_SHIFT)
+#define GPIO_I_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_I_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_I_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_I_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_I_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_I_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM7_SHIFT)
+#define GPIO_I_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_I_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_I_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_I_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_I_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_I_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_01_0_VM8_SHIFT)
+#define GPIO_I_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_I_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_I_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_I_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_I_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_SCR_01_0
+#define GPIO_I_SCR_01_0                 MK_ADDR_CONST(0x408c)
+#define GPIO_I_SCR_01_0_SECURE                  0x0
+#define GPIO_I_SCR_01_0_DUAL                    0x0
+#define GPIO_I_SCR_01_0_SCR                     0
+#define GPIO_I_SCR_01_0_SCRREG                  0
+#define GPIO_I_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_I_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_I_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_I_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_I_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_I_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_I_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_I_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_I_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_I_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_I_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_I_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_I_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_I_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_I_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_I_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_I_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_I_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_I_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR7_SHIFT)
+#define GPIO_I_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_I_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR6_SHIFT)
+#define GPIO_I_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_I_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR5_SHIFT)
+#define GPIO_I_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_I_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR4_SHIFT)
+#define GPIO_I_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_I_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR3_SHIFT)
+#define GPIO_I_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_I_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR2_SHIFT)
+#define GPIO_I_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_I_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR1_SHIFT)
+#define GPIO_I_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_I_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_PR0_SHIFT)
+#define GPIO_I_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_I_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G7W_SHIFT)
+#define GPIO_I_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_I_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G6W_SHIFT)
+#define GPIO_I_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_I_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G5W_SHIFT)
+#define GPIO_I_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_I_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G4W_SHIFT)
+#define GPIO_I_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_I_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G3W_SHIFT)
+#define GPIO_I_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_I_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G2W_SHIFT)
+#define GPIO_I_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_I_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G1W_SHIFT)
+#define GPIO_I_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_I_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G0W_SHIFT)
+#define GPIO_I_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_I_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G7R_SHIFT)
+#define GPIO_I_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_I_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G6R_SHIFT)
+#define GPIO_I_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_I_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G5R_SHIFT)
+#define GPIO_I_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_I_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G4R_SHIFT)
+#define GPIO_I_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_I_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G3R_SHIFT)
+#define GPIO_I_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_I_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G2R_SHIFT)
+#define GPIO_I_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_I_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G1R_SHIFT)
+#define GPIO_I_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_I_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_01_0_G0R_SHIFT)
+#define GPIO_I_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_I_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_I_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_VM_02_0
+#define GPIO_I_VM_02_0                  MK_ADDR_CONST(0x4090)
+#define GPIO_I_VM_02_0_SECURE                   0x0
+#define GPIO_I_VM_02_0_DUAL                     0x0
+#define GPIO_I_VM_02_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_I_VM_02_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_I_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_I_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_I_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM1_SHIFT)
+#define GPIO_I_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_I_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_I_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_I_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_I_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_I_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM2_SHIFT)
+#define GPIO_I_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_I_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_I_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_I_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_I_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_I_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM3_SHIFT)
+#define GPIO_I_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_I_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_I_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_I_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_I_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_I_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM4_SHIFT)
+#define GPIO_I_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_I_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_I_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_I_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_I_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_I_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM5_SHIFT)
+#define GPIO_I_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_I_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_I_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_I_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_I_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_I_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM6_SHIFT)
+#define GPIO_I_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_I_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_I_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_I_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_I_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_I_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM7_SHIFT)
+#define GPIO_I_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_I_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_I_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_I_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_I_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_I_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_02_0_VM8_SHIFT)
+#define GPIO_I_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_I_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_I_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_I_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_I_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_SCR_02_0
+#define GPIO_I_SCR_02_0                 MK_ADDR_CONST(0x4094)
+#define GPIO_I_SCR_02_0_SECURE                  0x0
+#define GPIO_I_SCR_02_0_DUAL                    0x0
+#define GPIO_I_SCR_02_0_SCR                     0
+#define GPIO_I_SCR_02_0_SCRREG                  0
+#define GPIO_I_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_I_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_I_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_I_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_I_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_I_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_I_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_I_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_I_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_I_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_I_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_I_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_I_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_I_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_I_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_I_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_I_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_I_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_I_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR7_SHIFT)
+#define GPIO_I_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_I_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR6_SHIFT)
+#define GPIO_I_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_I_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR5_SHIFT)
+#define GPIO_I_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_I_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR4_SHIFT)
+#define GPIO_I_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_I_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR3_SHIFT)
+#define GPIO_I_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_I_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR2_SHIFT)
+#define GPIO_I_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_I_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR1_SHIFT)
+#define GPIO_I_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_I_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_PR0_SHIFT)
+#define GPIO_I_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_I_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G7W_SHIFT)
+#define GPIO_I_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_I_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G6W_SHIFT)
+#define GPIO_I_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_I_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G5W_SHIFT)
+#define GPIO_I_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_I_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G4W_SHIFT)
+#define GPIO_I_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_I_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G3W_SHIFT)
+#define GPIO_I_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_I_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G2W_SHIFT)
+#define GPIO_I_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_I_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G1W_SHIFT)
+#define GPIO_I_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_I_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G0W_SHIFT)
+#define GPIO_I_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_I_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G7R_SHIFT)
+#define GPIO_I_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_I_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G6R_SHIFT)
+#define GPIO_I_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_I_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G5R_SHIFT)
+#define GPIO_I_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_I_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G4R_SHIFT)
+#define GPIO_I_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_I_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G3R_SHIFT)
+#define GPIO_I_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_I_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G2R_SHIFT)
+#define GPIO_I_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_I_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G1R_SHIFT)
+#define GPIO_I_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_I_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_02_0_G0R_SHIFT)
+#define GPIO_I_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_I_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_I_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_VM_03_0
+#define GPIO_I_VM_03_0                  MK_ADDR_CONST(0x4098)
+#define GPIO_I_VM_03_0_SECURE                   0x0
+#define GPIO_I_VM_03_0_DUAL                     0x0
+#define GPIO_I_VM_03_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_I_VM_03_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_I_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_I_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_I_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM1_SHIFT)
+#define GPIO_I_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_I_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_I_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_I_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_I_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_I_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM2_SHIFT)
+#define GPIO_I_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_I_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_I_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_I_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_I_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_I_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM3_SHIFT)
+#define GPIO_I_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_I_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_I_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_I_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_I_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_I_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM4_SHIFT)
+#define GPIO_I_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_I_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_I_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_I_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_I_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_I_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM5_SHIFT)
+#define GPIO_I_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_I_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_I_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_I_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_I_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_I_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM6_SHIFT)
+#define GPIO_I_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_I_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_I_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_I_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_I_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_I_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM7_SHIFT)
+#define GPIO_I_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_I_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_I_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_I_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_I_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_I_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_03_0_VM8_SHIFT)
+#define GPIO_I_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_I_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_I_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_I_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_I_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_SCR_03_0
+#define GPIO_I_SCR_03_0                 MK_ADDR_CONST(0x409c)
+#define GPIO_I_SCR_03_0_SECURE                  0x0
+#define GPIO_I_SCR_03_0_DUAL                    0x0
+#define GPIO_I_SCR_03_0_SCR                     0
+#define GPIO_I_SCR_03_0_SCRREG                  0
+#define GPIO_I_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_I_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_I_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_I_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_I_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_I_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_I_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_I_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_I_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_I_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_I_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_I_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_I_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_I_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_I_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_I_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_I_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_I_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_I_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR7_SHIFT)
+#define GPIO_I_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_I_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR6_SHIFT)
+#define GPIO_I_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_I_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR5_SHIFT)
+#define GPIO_I_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_I_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR4_SHIFT)
+#define GPIO_I_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_I_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR3_SHIFT)
+#define GPIO_I_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_I_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR2_SHIFT)
+#define GPIO_I_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_I_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR1_SHIFT)
+#define GPIO_I_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_I_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_PR0_SHIFT)
+#define GPIO_I_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_I_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G7W_SHIFT)
+#define GPIO_I_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_I_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G6W_SHIFT)
+#define GPIO_I_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_I_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G5W_SHIFT)
+#define GPIO_I_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_I_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G4W_SHIFT)
+#define GPIO_I_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_I_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G3W_SHIFT)
+#define GPIO_I_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_I_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G2W_SHIFT)
+#define GPIO_I_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_I_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G1W_SHIFT)
+#define GPIO_I_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_I_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G0W_SHIFT)
+#define GPIO_I_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_I_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G7R_SHIFT)
+#define GPIO_I_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_I_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G6R_SHIFT)
+#define GPIO_I_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_I_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G5R_SHIFT)
+#define GPIO_I_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_I_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G4R_SHIFT)
+#define GPIO_I_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_I_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G3R_SHIFT)
+#define GPIO_I_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_I_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G2R_SHIFT)
+#define GPIO_I_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_I_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G1R_SHIFT)
+#define GPIO_I_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_I_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_03_0_G0R_SHIFT)
+#define GPIO_I_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_I_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_I_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_VM_04_0
+#define GPIO_I_VM_04_0                  MK_ADDR_CONST(0x40a0)
+#define GPIO_I_VM_04_0_SECURE                   0x0
+#define GPIO_I_VM_04_0_DUAL                     0x0
+#define GPIO_I_VM_04_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_I_VM_04_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_I_VM_04_0_WORD_COUNT                       0x1
+#define GPIO_I_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_I_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM1_SHIFT)
+#define GPIO_I_VM_04_0_VM1_RANGE                        1:0
+#define GPIO_I_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_I_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_I_VM_04_0_VM1_WOFFSET                      0x0
+#define GPIO_I_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_I_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM2_SHIFT)
+#define GPIO_I_VM_04_0_VM2_RANGE                        3:2
+#define GPIO_I_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_I_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_I_VM_04_0_VM2_WOFFSET                      0x0
+#define GPIO_I_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_I_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM3_SHIFT)
+#define GPIO_I_VM_04_0_VM3_RANGE                        5:4
+#define GPIO_I_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_I_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_I_VM_04_0_VM3_WOFFSET                      0x0
+#define GPIO_I_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_I_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM4_SHIFT)
+#define GPIO_I_VM_04_0_VM4_RANGE                        7:6
+#define GPIO_I_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_I_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_I_VM_04_0_VM4_WOFFSET                      0x0
+#define GPIO_I_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_I_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM5_SHIFT)
+#define GPIO_I_VM_04_0_VM5_RANGE                        9:8
+#define GPIO_I_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_I_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_I_VM_04_0_VM5_WOFFSET                      0x0
+#define GPIO_I_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_I_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM6_SHIFT)
+#define GPIO_I_VM_04_0_VM6_RANGE                        11:10
+#define GPIO_I_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_I_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_I_VM_04_0_VM6_WOFFSET                      0x0
+#define GPIO_I_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_I_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM7_SHIFT)
+#define GPIO_I_VM_04_0_VM7_RANGE                        13:12
+#define GPIO_I_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_I_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_I_VM_04_0_VM7_WOFFSET                      0x0
+#define GPIO_I_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_I_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_04_0_VM8_SHIFT)
+#define GPIO_I_VM_04_0_VM8_RANGE                        15:14
+#define GPIO_I_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_I_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_I_VM_04_0_VM8_WOFFSET                      0x0
+#define GPIO_I_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_SCR_04_0
+#define GPIO_I_SCR_04_0                 MK_ADDR_CONST(0x40a4)
+#define GPIO_I_SCR_04_0_SECURE                  0x0
+#define GPIO_I_SCR_04_0_DUAL                    0x0
+#define GPIO_I_SCR_04_0_SCR                     0
+#define GPIO_I_SCR_04_0_SCRREG                  0
+#define GPIO_I_SCR_04_0_WORD_COUNT                      0x1
+#define GPIO_I_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_I_SCR_04_0_SEC_LCK_RANGE                   29:29
+#define GPIO_I_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_04_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_I_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_I_SCR_04_0_SEC_WEN_RANGE                   28:28
+#define GPIO_I_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_04_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_I_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_I_SCR_04_0_SEC_REN_RANGE                   27:27
+#define GPIO_I_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_04_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_I_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_I_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_I_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_I_SCR_04_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_I_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_I_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_I_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_I_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_I_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR7_SHIFT)
+#define GPIO_I_SCR_04_0_PR7_RANGE                       23:23
+#define GPIO_I_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_04_0_PR7_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR6_SHIFT)
+#define GPIO_I_SCR_04_0_PR6_RANGE                       22:22
+#define GPIO_I_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_04_0_PR6_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR5_SHIFT)
+#define GPIO_I_SCR_04_0_PR5_RANGE                       21:21
+#define GPIO_I_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_04_0_PR5_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR4_SHIFT)
+#define GPIO_I_SCR_04_0_PR4_RANGE                       20:20
+#define GPIO_I_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_04_0_PR4_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR3_SHIFT)
+#define GPIO_I_SCR_04_0_PR3_RANGE                       19:19
+#define GPIO_I_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_04_0_PR3_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR2_SHIFT)
+#define GPIO_I_SCR_04_0_PR2_RANGE                       18:18
+#define GPIO_I_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_04_0_PR2_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR1_SHIFT)
+#define GPIO_I_SCR_04_0_PR1_RANGE                       17:17
+#define GPIO_I_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_04_0_PR1_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_PR0_SHIFT)
+#define GPIO_I_SCR_04_0_PR0_RANGE                       16:16
+#define GPIO_I_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_04_0_PR0_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G7W_SHIFT)
+#define GPIO_I_SCR_04_0_G7W_RANGE                       15:15
+#define GPIO_I_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_04_0_G7W_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G6W_SHIFT)
+#define GPIO_I_SCR_04_0_G6W_RANGE                       14:14
+#define GPIO_I_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_04_0_G6W_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G5W_SHIFT)
+#define GPIO_I_SCR_04_0_G5W_RANGE                       13:13
+#define GPIO_I_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_04_0_G5W_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G4W_SHIFT)
+#define GPIO_I_SCR_04_0_G4W_RANGE                       12:12
+#define GPIO_I_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_04_0_G4W_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G3W_SHIFT)
+#define GPIO_I_SCR_04_0_G3W_RANGE                       11:11
+#define GPIO_I_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_04_0_G3W_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G2W_SHIFT)
+#define GPIO_I_SCR_04_0_G2W_RANGE                       10:10
+#define GPIO_I_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_04_0_G2W_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G1W_SHIFT)
+#define GPIO_I_SCR_04_0_G1W_RANGE                       9:9
+#define GPIO_I_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_04_0_G1W_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G0W_SHIFT)
+#define GPIO_I_SCR_04_0_G0W_RANGE                       8:8
+#define GPIO_I_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_04_0_G0W_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G7R_SHIFT)
+#define GPIO_I_SCR_04_0_G7R_RANGE                       7:7
+#define GPIO_I_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_04_0_G7R_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G6R_SHIFT)
+#define GPIO_I_SCR_04_0_G6R_RANGE                       6:6
+#define GPIO_I_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_04_0_G6R_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G5R_SHIFT)
+#define GPIO_I_SCR_04_0_G5R_RANGE                       5:5
+#define GPIO_I_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_04_0_G5R_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G4R_SHIFT)
+#define GPIO_I_SCR_04_0_G4R_RANGE                       4:4
+#define GPIO_I_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_04_0_G4R_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G3R_SHIFT)
+#define GPIO_I_SCR_04_0_G3R_RANGE                       3:3
+#define GPIO_I_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_04_0_G3R_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G2R_SHIFT)
+#define GPIO_I_SCR_04_0_G2R_RANGE                       2:2
+#define GPIO_I_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_04_0_G2R_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G1R_SHIFT)
+#define GPIO_I_SCR_04_0_G1R_RANGE                       1:1
+#define GPIO_I_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_04_0_G1R_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_04_0_G0R_SHIFT)
+#define GPIO_I_SCR_04_0_G0R_RANGE                       0:0
+#define GPIO_I_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_04_0_G0R_WOFFSET                     0x0
+#define GPIO_I_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_VM_05_0
+#define GPIO_I_VM_05_0                  MK_ADDR_CONST(0x40a8)
+#define GPIO_I_VM_05_0_SECURE                   0x0
+#define GPIO_I_VM_05_0_DUAL                     0x0
+#define GPIO_I_VM_05_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_I_VM_05_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_I_VM_05_0_WORD_COUNT                       0x1
+#define GPIO_I_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_I_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM1_SHIFT)
+#define GPIO_I_VM_05_0_VM1_RANGE                        1:0
+#define GPIO_I_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_I_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_I_VM_05_0_VM1_WOFFSET                      0x0
+#define GPIO_I_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_I_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM2_SHIFT)
+#define GPIO_I_VM_05_0_VM2_RANGE                        3:2
+#define GPIO_I_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_I_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_I_VM_05_0_VM2_WOFFSET                      0x0
+#define GPIO_I_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_I_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM3_SHIFT)
+#define GPIO_I_VM_05_0_VM3_RANGE                        5:4
+#define GPIO_I_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_I_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_I_VM_05_0_VM3_WOFFSET                      0x0
+#define GPIO_I_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_I_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM4_SHIFT)
+#define GPIO_I_VM_05_0_VM4_RANGE                        7:6
+#define GPIO_I_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_I_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_I_VM_05_0_VM4_WOFFSET                      0x0
+#define GPIO_I_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_I_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM5_SHIFT)
+#define GPIO_I_VM_05_0_VM5_RANGE                        9:8
+#define GPIO_I_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_I_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_I_VM_05_0_VM5_WOFFSET                      0x0
+#define GPIO_I_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_I_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM6_SHIFT)
+#define GPIO_I_VM_05_0_VM6_RANGE                        11:10
+#define GPIO_I_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_I_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_I_VM_05_0_VM6_WOFFSET                      0x0
+#define GPIO_I_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_I_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM7_SHIFT)
+#define GPIO_I_VM_05_0_VM7_RANGE                        13:12
+#define GPIO_I_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_I_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_I_VM_05_0_VM7_WOFFSET                      0x0
+#define GPIO_I_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_I_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_05_0_VM8_SHIFT)
+#define GPIO_I_VM_05_0_VM8_RANGE                        15:14
+#define GPIO_I_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_I_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_I_VM_05_0_VM8_WOFFSET                      0x0
+#define GPIO_I_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_SCR_05_0
+#define GPIO_I_SCR_05_0                 MK_ADDR_CONST(0x40ac)
+#define GPIO_I_SCR_05_0_SECURE                  0x0
+#define GPIO_I_SCR_05_0_DUAL                    0x0
+#define GPIO_I_SCR_05_0_SCR                     0
+#define GPIO_I_SCR_05_0_SCRREG                  0
+#define GPIO_I_SCR_05_0_WORD_COUNT                      0x1
+#define GPIO_I_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_I_SCR_05_0_SEC_LCK_RANGE                   29:29
+#define GPIO_I_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_05_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_I_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_I_SCR_05_0_SEC_WEN_RANGE                   28:28
+#define GPIO_I_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_05_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_I_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_I_SCR_05_0_SEC_REN_RANGE                   27:27
+#define GPIO_I_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_05_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_I_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_I_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_I_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_I_SCR_05_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_I_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_I_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_I_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_I_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_I_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR7_SHIFT)
+#define GPIO_I_SCR_05_0_PR7_RANGE                       23:23
+#define GPIO_I_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_05_0_PR7_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR6_SHIFT)
+#define GPIO_I_SCR_05_0_PR6_RANGE                       22:22
+#define GPIO_I_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_05_0_PR6_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR5_SHIFT)
+#define GPIO_I_SCR_05_0_PR5_RANGE                       21:21
+#define GPIO_I_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_05_0_PR5_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR4_SHIFT)
+#define GPIO_I_SCR_05_0_PR4_RANGE                       20:20
+#define GPIO_I_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_05_0_PR4_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR3_SHIFT)
+#define GPIO_I_SCR_05_0_PR3_RANGE                       19:19
+#define GPIO_I_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_05_0_PR3_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR2_SHIFT)
+#define GPIO_I_SCR_05_0_PR2_RANGE                       18:18
+#define GPIO_I_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_05_0_PR2_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR1_SHIFT)
+#define GPIO_I_SCR_05_0_PR1_RANGE                       17:17
+#define GPIO_I_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_05_0_PR1_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_PR0_SHIFT)
+#define GPIO_I_SCR_05_0_PR0_RANGE                       16:16
+#define GPIO_I_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_05_0_PR0_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G7W_SHIFT)
+#define GPIO_I_SCR_05_0_G7W_RANGE                       15:15
+#define GPIO_I_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_05_0_G7W_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G6W_SHIFT)
+#define GPIO_I_SCR_05_0_G6W_RANGE                       14:14
+#define GPIO_I_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_05_0_G6W_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G5W_SHIFT)
+#define GPIO_I_SCR_05_0_G5W_RANGE                       13:13
+#define GPIO_I_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_05_0_G5W_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G4W_SHIFT)
+#define GPIO_I_SCR_05_0_G4W_RANGE                       12:12
+#define GPIO_I_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_05_0_G4W_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G3W_SHIFT)
+#define GPIO_I_SCR_05_0_G3W_RANGE                       11:11
+#define GPIO_I_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_05_0_G3W_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G2W_SHIFT)
+#define GPIO_I_SCR_05_0_G2W_RANGE                       10:10
+#define GPIO_I_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_05_0_G2W_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G1W_SHIFT)
+#define GPIO_I_SCR_05_0_G1W_RANGE                       9:9
+#define GPIO_I_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_05_0_G1W_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G0W_SHIFT)
+#define GPIO_I_SCR_05_0_G0W_RANGE                       8:8
+#define GPIO_I_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_05_0_G0W_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G7R_SHIFT)
+#define GPIO_I_SCR_05_0_G7R_RANGE                       7:7
+#define GPIO_I_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_05_0_G7R_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G6R_SHIFT)
+#define GPIO_I_SCR_05_0_G6R_RANGE                       6:6
+#define GPIO_I_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_05_0_G6R_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G5R_SHIFT)
+#define GPIO_I_SCR_05_0_G5R_RANGE                       5:5
+#define GPIO_I_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_05_0_G5R_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G4R_SHIFT)
+#define GPIO_I_SCR_05_0_G4R_RANGE                       4:4
+#define GPIO_I_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_05_0_G4R_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G3R_SHIFT)
+#define GPIO_I_SCR_05_0_G3R_RANGE                       3:3
+#define GPIO_I_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_05_0_G3R_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G2R_SHIFT)
+#define GPIO_I_SCR_05_0_G2R_RANGE                       2:2
+#define GPIO_I_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_05_0_G2R_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G1R_SHIFT)
+#define GPIO_I_SCR_05_0_G1R_RANGE                       1:1
+#define GPIO_I_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_05_0_G1R_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_05_0_G0R_SHIFT)
+#define GPIO_I_SCR_05_0_G0R_RANGE                       0:0
+#define GPIO_I_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_05_0_G0R_WOFFSET                     0x0
+#define GPIO_I_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_VM_06_0
+#define GPIO_I_VM_06_0                  MK_ADDR_CONST(0x40b0)
+#define GPIO_I_VM_06_0_SECURE                   0x0
+#define GPIO_I_VM_06_0_DUAL                     0x0
+#define GPIO_I_VM_06_0_SCR                      GPIO_CTL4_VM_SCR_0
+#define GPIO_I_VM_06_0_SCRREG                   GPIO_CTL4_VM_SCR_0
+#define GPIO_I_VM_06_0_WORD_COUNT                       0x1
+#define GPIO_I_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_I_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_I_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM1_SHIFT)
+#define GPIO_I_VM_06_0_VM1_RANGE                        1:0
+#define GPIO_I_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_I_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_I_VM_06_0_VM1_WOFFSET                      0x0
+#define GPIO_I_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_I_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM2_SHIFT)
+#define GPIO_I_VM_06_0_VM2_RANGE                        3:2
+#define GPIO_I_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_I_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_I_VM_06_0_VM2_WOFFSET                      0x0
+#define GPIO_I_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_I_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM3_SHIFT)
+#define GPIO_I_VM_06_0_VM3_RANGE                        5:4
+#define GPIO_I_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_I_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_I_VM_06_0_VM3_WOFFSET                      0x0
+#define GPIO_I_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_I_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM4_SHIFT)
+#define GPIO_I_VM_06_0_VM4_RANGE                        7:6
+#define GPIO_I_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_I_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_I_VM_06_0_VM4_WOFFSET                      0x0
+#define GPIO_I_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_I_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM5_SHIFT)
+#define GPIO_I_VM_06_0_VM5_RANGE                        9:8
+#define GPIO_I_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_I_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_I_VM_06_0_VM5_WOFFSET                      0x0
+#define GPIO_I_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_I_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM6_SHIFT)
+#define GPIO_I_VM_06_0_VM6_RANGE                        11:10
+#define GPIO_I_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_I_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_I_VM_06_0_VM6_WOFFSET                      0x0
+#define GPIO_I_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_I_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM7_SHIFT)
+#define GPIO_I_VM_06_0_VM7_RANGE                        13:12
+#define GPIO_I_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_I_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_I_VM_06_0_VM7_WOFFSET                      0x0
+#define GPIO_I_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_I_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_I_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_I_VM_06_0_VM8_SHIFT)
+#define GPIO_I_VM_06_0_VM8_RANGE                        15:14
+#define GPIO_I_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_I_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_I_VM_06_0_VM8_WOFFSET                      0x0
+#define GPIO_I_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_I_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_I_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_SCR_06_0
+#define GPIO_I_SCR_06_0                 MK_ADDR_CONST(0x40b4)
+#define GPIO_I_SCR_06_0_SECURE                  0x0
+#define GPIO_I_SCR_06_0_DUAL                    0x0
+#define GPIO_I_SCR_06_0_SCR                     0
+#define GPIO_I_SCR_06_0_SCRREG                  0
+#define GPIO_I_SCR_06_0_WORD_COUNT                      0x1
+#define GPIO_I_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_I_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_SEC_LCK_SHIFT)
+#define GPIO_I_SCR_06_0_SEC_LCK_RANGE                   29:29
+#define GPIO_I_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_I_SCR_06_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_I_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_SEC_WEN_SHIFT)
+#define GPIO_I_SCR_06_0_SEC_WEN_RANGE                   28:28
+#define GPIO_I_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_I_SCR_06_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_I_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_SEC_REN_SHIFT)
+#define GPIO_I_SCR_06_0_SEC_REN_RANGE                   27:27
+#define GPIO_I_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_I_SCR_06_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_I_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_I_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_I_SCR_06_0_SEC_OWNER_SHIFT)
+#define GPIO_I_SCR_06_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_I_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_I_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_I_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_I_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_I_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR7_SHIFT)
+#define GPIO_I_SCR_06_0_PR7_RANGE                       23:23
+#define GPIO_I_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_I_SCR_06_0_PR7_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR6_SHIFT)
+#define GPIO_I_SCR_06_0_PR6_RANGE                       22:22
+#define GPIO_I_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_I_SCR_06_0_PR6_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR5_SHIFT)
+#define GPIO_I_SCR_06_0_PR5_RANGE                       21:21
+#define GPIO_I_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_I_SCR_06_0_PR5_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR4_SHIFT)
+#define GPIO_I_SCR_06_0_PR4_RANGE                       20:20
+#define GPIO_I_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_I_SCR_06_0_PR4_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR3_SHIFT)
+#define GPIO_I_SCR_06_0_PR3_RANGE                       19:19
+#define GPIO_I_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_I_SCR_06_0_PR3_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR2_SHIFT)
+#define GPIO_I_SCR_06_0_PR2_RANGE                       18:18
+#define GPIO_I_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_I_SCR_06_0_PR2_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR1_SHIFT)
+#define GPIO_I_SCR_06_0_PR1_RANGE                       17:17
+#define GPIO_I_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_I_SCR_06_0_PR1_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_PR0_SHIFT)
+#define GPIO_I_SCR_06_0_PR0_RANGE                       16:16
+#define GPIO_I_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_I_SCR_06_0_PR0_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G7W_SHIFT)
+#define GPIO_I_SCR_06_0_G7W_RANGE                       15:15
+#define GPIO_I_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_I_SCR_06_0_G7W_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G6W_SHIFT)
+#define GPIO_I_SCR_06_0_G6W_RANGE                       14:14
+#define GPIO_I_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_I_SCR_06_0_G6W_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G5W_SHIFT)
+#define GPIO_I_SCR_06_0_G5W_RANGE                       13:13
+#define GPIO_I_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_I_SCR_06_0_G5W_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G4W_SHIFT)
+#define GPIO_I_SCR_06_0_G4W_RANGE                       12:12
+#define GPIO_I_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_I_SCR_06_0_G4W_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G3W_SHIFT)
+#define GPIO_I_SCR_06_0_G3W_RANGE                       11:11
+#define GPIO_I_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_I_SCR_06_0_G3W_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G2W_SHIFT)
+#define GPIO_I_SCR_06_0_G2W_RANGE                       10:10
+#define GPIO_I_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_I_SCR_06_0_G2W_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G1W_SHIFT)
+#define GPIO_I_SCR_06_0_G1W_RANGE                       9:9
+#define GPIO_I_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_I_SCR_06_0_G1W_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G0W_SHIFT)
+#define GPIO_I_SCR_06_0_G0W_RANGE                       8:8
+#define GPIO_I_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_I_SCR_06_0_G0W_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G7R_SHIFT)
+#define GPIO_I_SCR_06_0_G7R_RANGE                       7:7
+#define GPIO_I_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_I_SCR_06_0_G7R_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G6R_SHIFT)
+#define GPIO_I_SCR_06_0_G6R_RANGE                       6:6
+#define GPIO_I_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_I_SCR_06_0_G6R_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G5R_SHIFT)
+#define GPIO_I_SCR_06_0_G5R_RANGE                       5:5
+#define GPIO_I_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_SCR_06_0_G5R_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G4R_SHIFT)
+#define GPIO_I_SCR_06_0_G4R_RANGE                       4:4
+#define GPIO_I_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_I_SCR_06_0_G4R_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G3R_SHIFT)
+#define GPIO_I_SCR_06_0_G3R_RANGE                       3:3
+#define GPIO_I_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_I_SCR_06_0_G3R_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G2R_SHIFT)
+#define GPIO_I_SCR_06_0_G2R_RANGE                       2:2
+#define GPIO_I_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_I_SCR_06_0_G2R_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G1R_SHIFT)
+#define GPIO_I_SCR_06_0_G1R_RANGE                       1:1
+#define GPIO_I_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_I_SCR_06_0_G1R_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_I_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_SCR_06_0_G0R_SHIFT)
+#define GPIO_I_SCR_06_0_G0R_RANGE                       0:0
+#define GPIO_I_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_SCR_06_0_G0R_WOFFSET                     0x0
+#define GPIO_I_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_I_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x40b8
+
+// Reserved address 0x40bc
+
+// Register GPIO_CTL4_VM_SCR_0
+#define GPIO_CTL4_VM_SCR_0                      MK_ADDR_CONST(0x4800)
+#define GPIO_CTL4_VM_SCR_0_SECURE                       0x0
+#define GPIO_CTL4_VM_SCR_0_DUAL                         0x0
+#define GPIO_CTL4_VM_SCR_0_SCR                  0
+#define GPIO_CTL4_VM_SCR_0_SCRREG                       0
+#define GPIO_CTL4_VM_SCR_0_WORD_COUNT                   0x1
+#define GPIO_CTL4_VM_SCR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL4_VM_SCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL4_VM_SCR_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL4_VM_SCR_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
+#define GPIO_CTL4_VM_SCR_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_SEC_LCK_RANGE                        29:29
+#define GPIO_CTL4_VM_SCR_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
+#define GPIO_CTL4_VM_SCR_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
+#define GPIO_CTL4_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
+#define GPIO_CTL4_VM_SCR_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
+#define GPIO_CTL4_VM_SCR_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_SEC_WEN_RANGE                        28:28
+#define GPIO_CTL4_VM_SCR_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
+#define GPIO_CTL4_VM_SCR_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
+#define GPIO_CTL4_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
+#define GPIO_CTL4_VM_SCR_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
+#define GPIO_CTL4_VM_SCR_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_SEC_REN_RANGE                        27:27
+#define GPIO_CTL4_VM_SCR_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
+#define GPIO_CTL4_VM_SCR_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
+#define GPIO_CTL4_VM_SCR_0_SEC_REN_WOFFSET                      0x0
+#define GPIO_CTL4_VM_SCR_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
+#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, GPIO_CTL4_VM_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_RANGE                      26:24
+#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
+#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
+#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
+#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
+#define GPIO_CTL4_VM_SCR_0_PR7_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR7_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_PR7_RANGE                    23:23
+#define GPIO_CTL4_VM_SCR_0_PR7_MSB                      MK_SHIFT_CONST(23)
+#define GPIO_CTL4_VM_SCR_0_PR7_LSB                      MK_SHIFT_CONST(23)
+#define GPIO_CTL4_VM_SCR_0_PR7_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
+#define GPIO_CTL4_VM_SCR_0_PR6_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR6_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_PR6_RANGE                    22:22
+#define GPIO_CTL4_VM_SCR_0_PR6_MSB                      MK_SHIFT_CONST(22)
+#define GPIO_CTL4_VM_SCR_0_PR6_LSB                      MK_SHIFT_CONST(22)
+#define GPIO_CTL4_VM_SCR_0_PR6_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
+#define GPIO_CTL4_VM_SCR_0_PR5_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR5_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_PR5_RANGE                    21:21
+#define GPIO_CTL4_VM_SCR_0_PR5_MSB                      MK_SHIFT_CONST(21)
+#define GPIO_CTL4_VM_SCR_0_PR5_LSB                      MK_SHIFT_CONST(21)
+#define GPIO_CTL4_VM_SCR_0_PR5_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
+#define GPIO_CTL4_VM_SCR_0_PR4_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR4_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_PR4_RANGE                    20:20
+#define GPIO_CTL4_VM_SCR_0_PR4_MSB                      MK_SHIFT_CONST(20)
+#define GPIO_CTL4_VM_SCR_0_PR4_LSB                      MK_SHIFT_CONST(20)
+#define GPIO_CTL4_VM_SCR_0_PR4_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
+#define GPIO_CTL4_VM_SCR_0_PR3_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR3_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_PR3_RANGE                    19:19
+#define GPIO_CTL4_VM_SCR_0_PR3_MSB                      MK_SHIFT_CONST(19)
+#define GPIO_CTL4_VM_SCR_0_PR3_LSB                      MK_SHIFT_CONST(19)
+#define GPIO_CTL4_VM_SCR_0_PR3_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
+#define GPIO_CTL4_VM_SCR_0_PR2_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR2_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_PR2_RANGE                    18:18
+#define GPIO_CTL4_VM_SCR_0_PR2_MSB                      MK_SHIFT_CONST(18)
+#define GPIO_CTL4_VM_SCR_0_PR2_LSB                      MK_SHIFT_CONST(18)
+#define GPIO_CTL4_VM_SCR_0_PR2_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
+#define GPIO_CTL4_VM_SCR_0_PR1_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR1_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_PR1_RANGE                    17:17
+#define GPIO_CTL4_VM_SCR_0_PR1_MSB                      MK_SHIFT_CONST(17)
+#define GPIO_CTL4_VM_SCR_0_PR1_LSB                      MK_SHIFT_CONST(17)
+#define GPIO_CTL4_VM_SCR_0_PR1_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
+#define GPIO_CTL4_VM_SCR_0_PR0_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_PR0_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_PR0_RANGE                    16:16
+#define GPIO_CTL4_VM_SCR_0_PR0_MSB                      MK_SHIFT_CONST(16)
+#define GPIO_CTL4_VM_SCR_0_PR0_LSB                      MK_SHIFT_CONST(16)
+#define GPIO_CTL4_VM_SCR_0_PR0_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
+#define GPIO_CTL4_VM_SCR_0_G7W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G7W_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_G7W_RANGE                    15:15
+#define GPIO_CTL4_VM_SCR_0_G7W_MSB                      MK_SHIFT_CONST(15)
+#define GPIO_CTL4_VM_SCR_0_G7W_LSB                      MK_SHIFT_CONST(15)
+#define GPIO_CTL4_VM_SCR_0_G7W_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
+#define GPIO_CTL4_VM_SCR_0_G6W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G6W_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_G6W_RANGE                    14:14
+#define GPIO_CTL4_VM_SCR_0_G6W_MSB                      MK_SHIFT_CONST(14)
+#define GPIO_CTL4_VM_SCR_0_G6W_LSB                      MK_SHIFT_CONST(14)
+#define GPIO_CTL4_VM_SCR_0_G6W_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
+#define GPIO_CTL4_VM_SCR_0_G5W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G5W_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_G5W_RANGE                    13:13
+#define GPIO_CTL4_VM_SCR_0_G5W_MSB                      MK_SHIFT_CONST(13)
+#define GPIO_CTL4_VM_SCR_0_G5W_LSB                      MK_SHIFT_CONST(13)
+#define GPIO_CTL4_VM_SCR_0_G5W_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
+#define GPIO_CTL4_VM_SCR_0_G4W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G4W_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_G4W_RANGE                    12:12
+#define GPIO_CTL4_VM_SCR_0_G4W_MSB                      MK_SHIFT_CONST(12)
+#define GPIO_CTL4_VM_SCR_0_G4W_LSB                      MK_SHIFT_CONST(12)
+#define GPIO_CTL4_VM_SCR_0_G4W_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
+#define GPIO_CTL4_VM_SCR_0_G3W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G3W_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_G3W_RANGE                    11:11
+#define GPIO_CTL4_VM_SCR_0_G3W_MSB                      MK_SHIFT_CONST(11)
+#define GPIO_CTL4_VM_SCR_0_G3W_LSB                      MK_SHIFT_CONST(11)
+#define GPIO_CTL4_VM_SCR_0_G3W_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
+#define GPIO_CTL4_VM_SCR_0_G2W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G2W_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_G2W_RANGE                    10:10
+#define GPIO_CTL4_VM_SCR_0_G2W_MSB                      MK_SHIFT_CONST(10)
+#define GPIO_CTL4_VM_SCR_0_G2W_LSB                      MK_SHIFT_CONST(10)
+#define GPIO_CTL4_VM_SCR_0_G2W_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
+#define GPIO_CTL4_VM_SCR_0_G1W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G1W_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_G1W_RANGE                    9:9
+#define GPIO_CTL4_VM_SCR_0_G1W_MSB                      MK_SHIFT_CONST(9)
+#define GPIO_CTL4_VM_SCR_0_G1W_LSB                      MK_SHIFT_CONST(9)
+#define GPIO_CTL4_VM_SCR_0_G1W_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
+#define GPIO_CTL4_VM_SCR_0_G0W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G0W_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_G0W_RANGE                    8:8
+#define GPIO_CTL4_VM_SCR_0_G0W_MSB                      MK_SHIFT_CONST(8)
+#define GPIO_CTL4_VM_SCR_0_G0W_LSB                      MK_SHIFT_CONST(8)
+#define GPIO_CTL4_VM_SCR_0_G0W_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
+#define GPIO_CTL4_VM_SCR_0_G7R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G7R_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_G7R_RANGE                    7:7
+#define GPIO_CTL4_VM_SCR_0_G7R_MSB                      MK_SHIFT_CONST(7)
+#define GPIO_CTL4_VM_SCR_0_G7R_LSB                      MK_SHIFT_CONST(7)
+#define GPIO_CTL4_VM_SCR_0_G7R_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
+#define GPIO_CTL4_VM_SCR_0_G6R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G6R_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_G6R_RANGE                    6:6
+#define GPIO_CTL4_VM_SCR_0_G6R_MSB                      MK_SHIFT_CONST(6)
+#define GPIO_CTL4_VM_SCR_0_G6R_LSB                      MK_SHIFT_CONST(6)
+#define GPIO_CTL4_VM_SCR_0_G6R_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
+#define GPIO_CTL4_VM_SCR_0_G5R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G5R_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_G5R_RANGE                    5:5
+#define GPIO_CTL4_VM_SCR_0_G5R_MSB                      MK_SHIFT_CONST(5)
+#define GPIO_CTL4_VM_SCR_0_G5R_LSB                      MK_SHIFT_CONST(5)
+#define GPIO_CTL4_VM_SCR_0_G5R_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
+#define GPIO_CTL4_VM_SCR_0_G4R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G4R_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_G4R_RANGE                    4:4
+#define GPIO_CTL4_VM_SCR_0_G4R_MSB                      MK_SHIFT_CONST(4)
+#define GPIO_CTL4_VM_SCR_0_G4R_LSB                      MK_SHIFT_CONST(4)
+#define GPIO_CTL4_VM_SCR_0_G4R_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
+#define GPIO_CTL4_VM_SCR_0_G3R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G3R_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_G3R_RANGE                    3:3
+#define GPIO_CTL4_VM_SCR_0_G3R_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_CTL4_VM_SCR_0_G3R_LSB                      MK_SHIFT_CONST(3)
+#define GPIO_CTL4_VM_SCR_0_G3R_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_CTL4_VM_SCR_0_G2R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G2R_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_G2R_RANGE                    2:2
+#define GPIO_CTL4_VM_SCR_0_G2R_MSB                      MK_SHIFT_CONST(2)
+#define GPIO_CTL4_VM_SCR_0_G2R_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_CTL4_VM_SCR_0_G2R_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
+#define GPIO_CTL4_VM_SCR_0_G1R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G1R_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_G1R_RANGE                    1:1
+#define GPIO_CTL4_VM_SCR_0_G1R_MSB                      MK_SHIFT_CONST(1)
+#define GPIO_CTL4_VM_SCR_0_G1R_LSB                      MK_SHIFT_CONST(1)
+#define GPIO_CTL4_VM_SCR_0_G1R_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_VM_SCR_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CTL4_VM_SCR_0_G0R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL4_VM_SCR_0_G0R_SHIFT)
+#define GPIO_CTL4_VM_SCR_0_G0R_RANGE                    0:0
+#define GPIO_CTL4_VM_SCR_0_G0R_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CTL4_VM_SCR_0_G0R_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CTL4_VM_SCR_0_G0R_WOFFSET                  0x0
+#define GPIO_CTL4_VM_SCR_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL4_VM_SCR_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0                     MK_ADDR_CONST(0x4804)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SCRREG                      0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_MSB                     MK_SHIFT_CONST(23)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_LSB                     MK_SHIFT_CONST(23)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_MSB                     MK_SHIFT_CONST(22)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_LSB                     MK_SHIFT_CONST(22)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_MSB                     MK_SHIFT_CONST(21)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_LSB                     MK_SHIFT_CONST(21)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_MSB                     MK_SHIFT_CONST(20)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_LSB                     MK_SHIFT_CONST(20)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_MSB                     MK_SHIFT_CONST(19)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_LSB                     MK_SHIFT_CONST(19)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_MSB                     MK_SHIFT_CONST(18)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_LSB                     MK_SHIFT_CONST(18)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_MSB                     MK_SHIFT_CONST(17)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_LSB                     MK_SHIFT_CONST(17)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_MSB                     MK_SHIFT_CONST(16)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_LSB                     MK_SHIFT_CONST(16)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_MSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_LSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_MSB                     MK_SHIFT_CONST(14)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_LSB                     MK_SHIFT_CONST(14)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_MSB                     MK_SHIFT_CONST(13)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_LSB                     MK_SHIFT_CONST(13)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_MSB                     MK_SHIFT_CONST(12)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_LSB                     MK_SHIFT_CONST(12)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_MSB                     MK_SHIFT_CONST(11)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_LSB                     MK_SHIFT_CONST(11)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_MSB                     MK_SHIFT_CONST(10)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_LSB                     MK_SHIFT_CONST(10)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_MSB                     MK_SHIFT_CONST(9)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_LSB                     MK_SHIFT_CONST(9)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_MSB                     MK_SHIFT_CONST(8)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_LSB                     MK_SHIFT_CONST(8)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_MSB                     MK_SHIFT_CONST(6)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_LSB                     MK_SHIFT_CONST(6)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_LSB                     MK_SHIFT_CONST(5)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_LSB                     MK_SHIFT_CONST(3)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_MSB                     MK_SHIFT_CONST(2)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_MSB                     MK_SHIFT_CONST(1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_LSB                     MK_SHIFT_CONST(1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_MSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL4_INTERRUPT_STATUS_VM_0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0                 MK_ADDR_CONST(0x4808)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SECURE                  0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_DUAL                    0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SCRREG                  GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  MK_FIELD_CONST(0xff, GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL4_SCR_0
+#define GPIO_CTL4_SCR_0                 MK_ADDR_CONST(0x480c)
+#define GPIO_CTL4_SCR_0_SECURE                  0x0
+#define GPIO_CTL4_SCR_0_DUAL                    0x0
+#define GPIO_CTL4_SCR_0_SCR                     0
+#define GPIO_CTL4_SCR_0_SCRREG                  0
+#define GPIO_CTL4_SCR_0_WORD_COUNT                      0x1
+#define GPIO_CTL4_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL4_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL4_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL4_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_CTL4_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL4_SCR_0_SEC_LCK_RANGE                   29:29
+#define GPIO_CTL4_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_CTL4_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_CTL4_SCR_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_CTL4_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_CTL4_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL4_SCR_0_SEC_WEN_RANGE                   28:28
+#define GPIO_CTL4_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_CTL4_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_CTL4_SCR_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_CTL4_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_CTL4_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL4_SCR_0_SEC_REN_RANGE                   27:27
+#define GPIO_CTL4_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_CTL4_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_CTL4_SCR_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_CTL4_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_CTL4_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_CTL4_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL4_SCR_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_CTL4_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_CTL4_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_CTL4_SCR_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_CTL4_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_CTL4_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_CTL4_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR7_SHIFT)
+#define GPIO_CTL4_SCR_0_PR7_RANGE                       23:23
+#define GPIO_CTL4_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_CTL4_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_CTL4_SCR_0_PR7_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_CTL4_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR6_SHIFT)
+#define GPIO_CTL4_SCR_0_PR6_RANGE                       22:22
+#define GPIO_CTL4_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_CTL4_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_CTL4_SCR_0_PR6_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_CTL4_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR5_SHIFT)
+#define GPIO_CTL4_SCR_0_PR5_RANGE                       21:21
+#define GPIO_CTL4_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_CTL4_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_CTL4_SCR_0_PR5_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_CTL4_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR4_SHIFT)
+#define GPIO_CTL4_SCR_0_PR4_RANGE                       20:20
+#define GPIO_CTL4_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_CTL4_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_CTL4_SCR_0_PR4_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_CTL4_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR3_SHIFT)
+#define GPIO_CTL4_SCR_0_PR3_RANGE                       19:19
+#define GPIO_CTL4_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_CTL4_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_CTL4_SCR_0_PR3_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_CTL4_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR2_SHIFT)
+#define GPIO_CTL4_SCR_0_PR2_RANGE                       18:18
+#define GPIO_CTL4_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_CTL4_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_CTL4_SCR_0_PR2_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_CTL4_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR1_SHIFT)
+#define GPIO_CTL4_SCR_0_PR1_RANGE                       17:17
+#define GPIO_CTL4_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_CTL4_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_CTL4_SCR_0_PR1_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_CTL4_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_PR0_SHIFT)
+#define GPIO_CTL4_SCR_0_PR0_RANGE                       16:16
+#define GPIO_CTL4_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_CTL4_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_CTL4_SCR_0_PR0_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_CTL4_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G7W_SHIFT)
+#define GPIO_CTL4_SCR_0_G7W_RANGE                       15:15
+#define GPIO_CTL4_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_CTL4_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_CTL4_SCR_0_G7W_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_CTL4_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G6W_SHIFT)
+#define GPIO_CTL4_SCR_0_G6W_RANGE                       14:14
+#define GPIO_CTL4_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_CTL4_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_CTL4_SCR_0_G6W_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_CTL4_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G5W_SHIFT)
+#define GPIO_CTL4_SCR_0_G5W_RANGE                       13:13
+#define GPIO_CTL4_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_CTL4_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_CTL4_SCR_0_G5W_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_CTL4_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G4W_SHIFT)
+#define GPIO_CTL4_SCR_0_G4W_RANGE                       12:12
+#define GPIO_CTL4_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_CTL4_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_CTL4_SCR_0_G4W_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_CTL4_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G3W_SHIFT)
+#define GPIO_CTL4_SCR_0_G3W_RANGE                       11:11
+#define GPIO_CTL4_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_CTL4_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_CTL4_SCR_0_G3W_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_CTL4_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G2W_SHIFT)
+#define GPIO_CTL4_SCR_0_G2W_RANGE                       10:10
+#define GPIO_CTL4_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_CTL4_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_CTL4_SCR_0_G2W_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_CTL4_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G1W_SHIFT)
+#define GPIO_CTL4_SCR_0_G1W_RANGE                       9:9
+#define GPIO_CTL4_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_CTL4_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_CTL4_SCR_0_G1W_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_CTL4_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G0W_SHIFT)
+#define GPIO_CTL4_SCR_0_G0W_RANGE                       8:8
+#define GPIO_CTL4_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_CTL4_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_CTL4_SCR_0_G0W_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_CTL4_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G7R_SHIFT)
+#define GPIO_CTL4_SCR_0_G7R_RANGE                       7:7
+#define GPIO_CTL4_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_CTL4_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_CTL4_SCR_0_G7R_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_CTL4_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G6R_SHIFT)
+#define GPIO_CTL4_SCR_0_G6R_RANGE                       6:6
+#define GPIO_CTL4_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_CTL4_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_CTL4_SCR_0_G6R_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_CTL4_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G5R_SHIFT)
+#define GPIO_CTL4_SCR_0_G5R_RANGE                       5:5
+#define GPIO_CTL4_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_CTL4_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_CTL4_SCR_0_G5R_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_CTL4_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G4R_SHIFT)
+#define GPIO_CTL4_SCR_0_G4R_RANGE                       4:4
+#define GPIO_CTL4_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_CTL4_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_CTL4_SCR_0_G4R_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_CTL4_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G3R_SHIFT)
+#define GPIO_CTL4_SCR_0_G3R_RANGE                       3:3
+#define GPIO_CTL4_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_CTL4_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_CTL4_SCR_0_G3R_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_CTL4_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G2R_SHIFT)
+#define GPIO_CTL4_SCR_0_G2R_RANGE                       2:2
+#define GPIO_CTL4_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_CTL4_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_CTL4_SCR_0_G2R_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_CTL4_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G1R_SHIFT)
+#define GPIO_CTL4_SCR_0_G1R_RANGE                       1:1
+#define GPIO_CTL4_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_CTL4_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_CTL4_SCR_0_G1R_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL4_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_CTL4_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL4_SCR_0_G0R_SHIFT)
+#define GPIO_CTL4_SCR_0_G0R_RANGE                       0:0
+#define GPIO_CTL4_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_CTL4_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_CTL4_SCR_0_G0R_WOFFSET                     0x0
+#define GPIO_CTL4_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL4_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL4_ICG_EN_OVERRIDE_0
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0                     MK_ADDR_CONST(0x4810)
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SECURE                      0x0
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_DUAL                        0x0
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CTL4_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INT0_ROUTE_MAPPING_0
+#define GPIO_G_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4814)
+#define GPIO_G_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_G_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_G_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_G_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_G_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_G_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_G_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_G_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INT1_ROUTE_MAPPING_0
+#define GPIO_G_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4818)
+#define GPIO_G_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_G_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_G_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_G_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_G_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_G_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_G_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_G_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INT2_ROUTE_MAPPING_0
+#define GPIO_G_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x481c)
+#define GPIO_G_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_G_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_G_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_G_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_G_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_G_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_G_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_G_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INT3_ROUTE_MAPPING_0
+#define GPIO_G_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4820)
+#define GPIO_G_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_G_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_G_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_G_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_G_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_G_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_G_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_G_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INT4_ROUTE_MAPPING_0
+#define GPIO_G_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4824)
+#define GPIO_G_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_G_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_G_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_G_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_G_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_G_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_G_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_G_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INT5_ROUTE_MAPPING_0
+#define GPIO_G_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4828)
+#define GPIO_G_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_G_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_G_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_G_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_G_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_G_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_G_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_G_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INT6_ROUTE_MAPPING_0
+#define GPIO_G_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x482c)
+#define GPIO_G_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_G_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_G_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_G_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_G_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_G_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_G_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_G_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INT7_ROUTE_MAPPING_0
+#define GPIO_G_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4830)
+#define GPIO_G_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_G_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_G_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_G_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_G_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_G_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_G_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_G_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INT0_ROUTE_MAPPING_0
+#define GPIO_H_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4834)
+#define GPIO_H_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_H_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_H_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_H_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_H_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_H_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_H_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_H_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INT1_ROUTE_MAPPING_0
+#define GPIO_H_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4838)
+#define GPIO_H_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_H_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_H_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_H_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_H_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_H_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_H_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_H_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INT2_ROUTE_MAPPING_0
+#define GPIO_H_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x483c)
+#define GPIO_H_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_H_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_H_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_H_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_H_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_H_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_H_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_H_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INT3_ROUTE_MAPPING_0
+#define GPIO_H_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4840)
+#define GPIO_H_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_H_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_H_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_H_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_H_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_H_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_H_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_H_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INT4_ROUTE_MAPPING_0
+#define GPIO_H_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4844)
+#define GPIO_H_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_H_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_H_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_H_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_H_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_H_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_H_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_H_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INT5_ROUTE_MAPPING_0
+#define GPIO_H_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4848)
+#define GPIO_H_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_H_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_H_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_H_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_H_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_H_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_H_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_H_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INT6_ROUTE_MAPPING_0
+#define GPIO_H_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x484c)
+#define GPIO_H_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_H_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_H_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_H_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_H_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_H_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_H_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_H_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INT7_ROUTE_MAPPING_0
+#define GPIO_H_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4850)
+#define GPIO_H_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_H_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_H_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_H_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_H_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_H_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_H_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_H_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INT0_ROUTE_MAPPING_0
+#define GPIO_I_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4854)
+#define GPIO_I_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_I_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_I_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_I_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_I_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_I_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x7f)
+#define GPIO_I_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x7f, GPIO_I_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_RANGE                   6:0
+#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(6)
+#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
+#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INT1_ROUTE_MAPPING_0
+#define GPIO_I_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4858)
+#define GPIO_I_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_I_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_I_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_I_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_I_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_I_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x7f)
+#define GPIO_I_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x7f, GPIO_I_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_RANGE                   6:0
+#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(6)
+#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
+#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INT2_ROUTE_MAPPING_0
+#define GPIO_I_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x485c)
+#define GPIO_I_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_I_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_I_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_I_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_I_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_I_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x7f)
+#define GPIO_I_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x7f, GPIO_I_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_RANGE                   6:0
+#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(6)
+#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
+#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INT3_ROUTE_MAPPING_0
+#define GPIO_I_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4860)
+#define GPIO_I_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_I_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_I_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_I_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_I_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_I_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x7f)
+#define GPIO_I_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x7f, GPIO_I_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_RANGE                   6:0
+#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(6)
+#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
+#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INT4_ROUTE_MAPPING_0
+#define GPIO_I_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4864)
+#define GPIO_I_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_I_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_I_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_I_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_I_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_I_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x7f)
+#define GPIO_I_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x7f, GPIO_I_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_RANGE                   6:0
+#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(6)
+#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
+#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INT5_ROUTE_MAPPING_0
+#define GPIO_I_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4868)
+#define GPIO_I_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_I_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_I_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_I_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_I_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_I_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x7f)
+#define GPIO_I_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x7f, GPIO_I_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_RANGE                   6:0
+#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(6)
+#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
+#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INT6_ROUTE_MAPPING_0
+#define GPIO_I_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x486c)
+#define GPIO_I_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_I_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_I_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_I_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_I_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_I_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x7f)
+#define GPIO_I_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x7f, GPIO_I_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_RANGE                   6:0
+#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(6)
+#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
+#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INT7_ROUTE_MAPPING_0
+#define GPIO_I_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x4870)
+#define GPIO_I_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_I_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_I_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL4_SCR_0
+#define GPIO_I_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL4_SCR_0
+#define GPIO_I_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_I_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x7f)
+#define GPIO_I_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x7f, GPIO_I_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_RANGE                   6:0
+#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(6)
+#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
+#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL4_SPARE_0
+#define GPIO_CTL4_SPARE_0                       MK_ADDR_CONST(0x4874)
+#define GPIO_CTL4_SPARE_0_SECURE                        0x0
+#define GPIO_CTL4_SPARE_0_DUAL                  0x0
+#define GPIO_CTL4_SPARE_0_SCR                   0
+#define GPIO_CTL4_SPARE_0_SCRREG                        0
+#define GPIO_CTL4_SPARE_0_WORD_COUNT                    0x1
+#define GPIO_CTL4_SPARE_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SPARE_0_RESET_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL4_SPARE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SPARE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SPARE_0_READ_MASK                     MK_MASK_CONST(0xffff)
+#define GPIO_CTL4_SPARE_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL4_SPARE_0_SPARE_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_CTL4_SPARE_0_SPARE_FIELD                   MK_FIELD_CONST(0xffff, GPIO_CTL4_SPARE_0_SPARE_SHIFT)
+#define GPIO_CTL4_SPARE_0_SPARE_RANGE                   15:0
+#define GPIO_CTL4_SPARE_0_SPARE_MSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL4_SPARE_0_SPARE_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL4_SPARE_0_SPARE_WOFFSET                 0x0
+#define GPIO_CTL4_SPARE_0_SPARE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SPARE_0_SPARE_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL4_SPARE_0_SPARE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SPARE_0_SPARE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SPARE_0_SPARE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL4_SPARE_0_SPARE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_VM_00_0
+#define GPIO_J_VM_00_0                  MK_ADDR_CONST(0x5000)
+#define GPIO_J_VM_00_0_SECURE                   0x0
+#define GPIO_J_VM_00_0_DUAL                     0x0
+#define GPIO_J_VM_00_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_J_VM_00_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_J_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_J_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_J_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM1_SHIFT)
+#define GPIO_J_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_J_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_J_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_J_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_J_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_J_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM2_SHIFT)
+#define GPIO_J_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_J_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_J_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_J_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_J_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_J_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM3_SHIFT)
+#define GPIO_J_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_J_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_J_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_J_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_J_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_J_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM4_SHIFT)
+#define GPIO_J_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_J_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_J_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_J_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_J_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_J_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM5_SHIFT)
+#define GPIO_J_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_J_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_J_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_J_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_J_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_J_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM6_SHIFT)
+#define GPIO_J_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_J_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_J_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_J_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_J_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_J_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM7_SHIFT)
+#define GPIO_J_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_J_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_J_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_J_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_J_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_J_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_00_0_VM8_SHIFT)
+#define GPIO_J_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_J_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_J_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_J_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_J_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_SCR_00_0
+#define GPIO_J_SCR_00_0                 MK_ADDR_CONST(0x5004)
+#define GPIO_J_SCR_00_0_SECURE                  0x0
+#define GPIO_J_SCR_00_0_DUAL                    0x0
+#define GPIO_J_SCR_00_0_SCR                     0
+#define GPIO_J_SCR_00_0_SCRREG                  0
+#define GPIO_J_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_J_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_J_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_J_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_J_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_J_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_J_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_J_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_J_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_J_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_J_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_J_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_J_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_J_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_J_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_J_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_J_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_J_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_J_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR7_SHIFT)
+#define GPIO_J_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_J_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR6_SHIFT)
+#define GPIO_J_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_J_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR5_SHIFT)
+#define GPIO_J_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_J_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR4_SHIFT)
+#define GPIO_J_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_J_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR3_SHIFT)
+#define GPIO_J_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_J_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR2_SHIFT)
+#define GPIO_J_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_J_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR1_SHIFT)
+#define GPIO_J_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_J_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_PR0_SHIFT)
+#define GPIO_J_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_J_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G7W_SHIFT)
+#define GPIO_J_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_J_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G6W_SHIFT)
+#define GPIO_J_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_J_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G5W_SHIFT)
+#define GPIO_J_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_J_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G4W_SHIFT)
+#define GPIO_J_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_J_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G3W_SHIFT)
+#define GPIO_J_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_J_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G2W_SHIFT)
+#define GPIO_J_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_J_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G1W_SHIFT)
+#define GPIO_J_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_J_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G0W_SHIFT)
+#define GPIO_J_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_J_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G7R_SHIFT)
+#define GPIO_J_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_J_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G6R_SHIFT)
+#define GPIO_J_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_J_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G5R_SHIFT)
+#define GPIO_J_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_J_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G4R_SHIFT)
+#define GPIO_J_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_J_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G3R_SHIFT)
+#define GPIO_J_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_J_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G2R_SHIFT)
+#define GPIO_J_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_J_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G1R_SHIFT)
+#define GPIO_J_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_J_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_00_0_G0R_SHIFT)
+#define GPIO_J_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_J_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_J_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_VM_01_0
+#define GPIO_J_VM_01_0                  MK_ADDR_CONST(0x5008)
+#define GPIO_J_VM_01_0_SECURE                   0x0
+#define GPIO_J_VM_01_0_DUAL                     0x0
+#define GPIO_J_VM_01_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_J_VM_01_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_J_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_J_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_J_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM1_SHIFT)
+#define GPIO_J_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_J_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_J_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_J_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_J_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_J_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM2_SHIFT)
+#define GPIO_J_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_J_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_J_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_J_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_J_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_J_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM3_SHIFT)
+#define GPIO_J_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_J_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_J_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_J_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_J_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_J_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM4_SHIFT)
+#define GPIO_J_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_J_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_J_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_J_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_J_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_J_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM5_SHIFT)
+#define GPIO_J_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_J_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_J_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_J_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_J_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_J_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM6_SHIFT)
+#define GPIO_J_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_J_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_J_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_J_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_J_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_J_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM7_SHIFT)
+#define GPIO_J_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_J_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_J_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_J_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_J_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_J_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_01_0_VM8_SHIFT)
+#define GPIO_J_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_J_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_J_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_J_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_J_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_SCR_01_0
+#define GPIO_J_SCR_01_0                 MK_ADDR_CONST(0x500c)
+#define GPIO_J_SCR_01_0_SECURE                  0x0
+#define GPIO_J_SCR_01_0_DUAL                    0x0
+#define GPIO_J_SCR_01_0_SCR                     0
+#define GPIO_J_SCR_01_0_SCRREG                  0
+#define GPIO_J_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_J_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_J_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_J_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_J_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_J_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_J_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_J_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_J_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_J_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_J_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_J_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_J_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_J_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_J_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_J_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_J_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_J_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_J_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR7_SHIFT)
+#define GPIO_J_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_J_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR6_SHIFT)
+#define GPIO_J_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_J_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR5_SHIFT)
+#define GPIO_J_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_J_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR4_SHIFT)
+#define GPIO_J_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_J_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR3_SHIFT)
+#define GPIO_J_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_J_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR2_SHIFT)
+#define GPIO_J_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_J_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR1_SHIFT)
+#define GPIO_J_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_J_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_PR0_SHIFT)
+#define GPIO_J_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_J_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G7W_SHIFT)
+#define GPIO_J_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_J_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G6W_SHIFT)
+#define GPIO_J_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_J_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G5W_SHIFT)
+#define GPIO_J_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_J_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G4W_SHIFT)
+#define GPIO_J_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_J_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G3W_SHIFT)
+#define GPIO_J_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_J_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G2W_SHIFT)
+#define GPIO_J_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_J_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G1W_SHIFT)
+#define GPIO_J_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_J_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G0W_SHIFT)
+#define GPIO_J_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_J_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G7R_SHIFT)
+#define GPIO_J_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_J_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G6R_SHIFT)
+#define GPIO_J_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_J_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G5R_SHIFT)
+#define GPIO_J_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_J_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G4R_SHIFT)
+#define GPIO_J_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_J_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G3R_SHIFT)
+#define GPIO_J_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_J_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G2R_SHIFT)
+#define GPIO_J_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_J_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G1R_SHIFT)
+#define GPIO_J_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_J_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_01_0_G0R_SHIFT)
+#define GPIO_J_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_J_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_J_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_VM_02_0
+#define GPIO_J_VM_02_0                  MK_ADDR_CONST(0x5010)
+#define GPIO_J_VM_02_0_SECURE                   0x0
+#define GPIO_J_VM_02_0_DUAL                     0x0
+#define GPIO_J_VM_02_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_J_VM_02_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_J_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_J_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_J_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM1_SHIFT)
+#define GPIO_J_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_J_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_J_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_J_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_J_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_J_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM2_SHIFT)
+#define GPIO_J_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_J_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_J_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_J_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_J_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_J_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM3_SHIFT)
+#define GPIO_J_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_J_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_J_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_J_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_J_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_J_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM4_SHIFT)
+#define GPIO_J_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_J_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_J_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_J_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_J_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_J_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM5_SHIFT)
+#define GPIO_J_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_J_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_J_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_J_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_J_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_J_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM6_SHIFT)
+#define GPIO_J_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_J_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_J_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_J_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_J_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_J_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM7_SHIFT)
+#define GPIO_J_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_J_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_J_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_J_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_J_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_J_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_02_0_VM8_SHIFT)
+#define GPIO_J_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_J_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_J_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_J_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_J_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_SCR_02_0
+#define GPIO_J_SCR_02_0                 MK_ADDR_CONST(0x5014)
+#define GPIO_J_SCR_02_0_SECURE                  0x0
+#define GPIO_J_SCR_02_0_DUAL                    0x0
+#define GPIO_J_SCR_02_0_SCR                     0
+#define GPIO_J_SCR_02_0_SCRREG                  0
+#define GPIO_J_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_J_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_J_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_J_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_J_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_J_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_J_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_J_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_J_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_J_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_J_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_J_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_J_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_J_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_J_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_J_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_J_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_J_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_J_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR7_SHIFT)
+#define GPIO_J_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_J_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR6_SHIFT)
+#define GPIO_J_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_J_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR5_SHIFT)
+#define GPIO_J_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_J_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR4_SHIFT)
+#define GPIO_J_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_J_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR3_SHIFT)
+#define GPIO_J_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_J_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR2_SHIFT)
+#define GPIO_J_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_J_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR1_SHIFT)
+#define GPIO_J_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_J_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_PR0_SHIFT)
+#define GPIO_J_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_J_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G7W_SHIFT)
+#define GPIO_J_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_J_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G6W_SHIFT)
+#define GPIO_J_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_J_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G5W_SHIFT)
+#define GPIO_J_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_J_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G4W_SHIFT)
+#define GPIO_J_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_J_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G3W_SHIFT)
+#define GPIO_J_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_J_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G2W_SHIFT)
+#define GPIO_J_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_J_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G1W_SHIFT)
+#define GPIO_J_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_J_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G0W_SHIFT)
+#define GPIO_J_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_J_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G7R_SHIFT)
+#define GPIO_J_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_J_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G6R_SHIFT)
+#define GPIO_J_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_J_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G5R_SHIFT)
+#define GPIO_J_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_J_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G4R_SHIFT)
+#define GPIO_J_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_J_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G3R_SHIFT)
+#define GPIO_J_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_J_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G2R_SHIFT)
+#define GPIO_J_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_J_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G1R_SHIFT)
+#define GPIO_J_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_J_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_02_0_G0R_SHIFT)
+#define GPIO_J_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_J_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_J_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_VM_03_0
+#define GPIO_J_VM_03_0                  MK_ADDR_CONST(0x5018)
+#define GPIO_J_VM_03_0_SECURE                   0x0
+#define GPIO_J_VM_03_0_DUAL                     0x0
+#define GPIO_J_VM_03_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_J_VM_03_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_J_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_J_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_J_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM1_SHIFT)
+#define GPIO_J_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_J_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_J_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_J_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_J_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_J_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM2_SHIFT)
+#define GPIO_J_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_J_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_J_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_J_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_J_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_J_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM3_SHIFT)
+#define GPIO_J_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_J_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_J_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_J_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_J_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_J_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM4_SHIFT)
+#define GPIO_J_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_J_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_J_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_J_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_J_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_J_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM5_SHIFT)
+#define GPIO_J_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_J_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_J_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_J_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_J_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_J_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM6_SHIFT)
+#define GPIO_J_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_J_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_J_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_J_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_J_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_J_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM7_SHIFT)
+#define GPIO_J_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_J_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_J_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_J_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_J_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_J_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_03_0_VM8_SHIFT)
+#define GPIO_J_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_J_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_J_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_J_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_J_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_SCR_03_0
+#define GPIO_J_SCR_03_0                 MK_ADDR_CONST(0x501c)
+#define GPIO_J_SCR_03_0_SECURE                  0x0
+#define GPIO_J_SCR_03_0_DUAL                    0x0
+#define GPIO_J_SCR_03_0_SCR                     0
+#define GPIO_J_SCR_03_0_SCRREG                  0
+#define GPIO_J_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_J_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_J_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_J_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_J_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_J_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_J_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_J_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_J_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_J_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_J_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_J_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_J_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_J_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_J_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_J_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_J_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_J_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_J_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR7_SHIFT)
+#define GPIO_J_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_J_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR6_SHIFT)
+#define GPIO_J_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_J_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR5_SHIFT)
+#define GPIO_J_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_J_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR4_SHIFT)
+#define GPIO_J_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_J_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR3_SHIFT)
+#define GPIO_J_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_J_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR2_SHIFT)
+#define GPIO_J_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_J_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR1_SHIFT)
+#define GPIO_J_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_J_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_PR0_SHIFT)
+#define GPIO_J_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_J_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G7W_SHIFT)
+#define GPIO_J_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_J_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G6W_SHIFT)
+#define GPIO_J_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_J_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G5W_SHIFT)
+#define GPIO_J_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_J_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G4W_SHIFT)
+#define GPIO_J_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_J_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G3W_SHIFT)
+#define GPIO_J_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_J_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G2W_SHIFT)
+#define GPIO_J_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_J_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G1W_SHIFT)
+#define GPIO_J_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_J_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G0W_SHIFT)
+#define GPIO_J_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_J_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G7R_SHIFT)
+#define GPIO_J_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_J_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G6R_SHIFT)
+#define GPIO_J_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_J_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G5R_SHIFT)
+#define GPIO_J_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_J_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G4R_SHIFT)
+#define GPIO_J_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_J_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G3R_SHIFT)
+#define GPIO_J_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_J_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G2R_SHIFT)
+#define GPIO_J_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_J_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G1R_SHIFT)
+#define GPIO_J_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_J_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_03_0_G0R_SHIFT)
+#define GPIO_J_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_J_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_J_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_VM_04_0
+#define GPIO_J_VM_04_0                  MK_ADDR_CONST(0x5020)
+#define GPIO_J_VM_04_0_SECURE                   0x0
+#define GPIO_J_VM_04_0_DUAL                     0x0
+#define GPIO_J_VM_04_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_J_VM_04_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_J_VM_04_0_WORD_COUNT                       0x1
+#define GPIO_J_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_J_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM1_SHIFT)
+#define GPIO_J_VM_04_0_VM1_RANGE                        1:0
+#define GPIO_J_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_J_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_J_VM_04_0_VM1_WOFFSET                      0x0
+#define GPIO_J_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_J_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM2_SHIFT)
+#define GPIO_J_VM_04_0_VM2_RANGE                        3:2
+#define GPIO_J_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_J_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_J_VM_04_0_VM2_WOFFSET                      0x0
+#define GPIO_J_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_J_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM3_SHIFT)
+#define GPIO_J_VM_04_0_VM3_RANGE                        5:4
+#define GPIO_J_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_J_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_J_VM_04_0_VM3_WOFFSET                      0x0
+#define GPIO_J_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_J_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM4_SHIFT)
+#define GPIO_J_VM_04_0_VM4_RANGE                        7:6
+#define GPIO_J_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_J_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_J_VM_04_0_VM4_WOFFSET                      0x0
+#define GPIO_J_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_J_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM5_SHIFT)
+#define GPIO_J_VM_04_0_VM5_RANGE                        9:8
+#define GPIO_J_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_J_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_J_VM_04_0_VM5_WOFFSET                      0x0
+#define GPIO_J_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_J_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM6_SHIFT)
+#define GPIO_J_VM_04_0_VM6_RANGE                        11:10
+#define GPIO_J_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_J_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_J_VM_04_0_VM6_WOFFSET                      0x0
+#define GPIO_J_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_J_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM7_SHIFT)
+#define GPIO_J_VM_04_0_VM7_RANGE                        13:12
+#define GPIO_J_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_J_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_J_VM_04_0_VM7_WOFFSET                      0x0
+#define GPIO_J_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_J_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_04_0_VM8_SHIFT)
+#define GPIO_J_VM_04_0_VM8_RANGE                        15:14
+#define GPIO_J_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_J_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_J_VM_04_0_VM8_WOFFSET                      0x0
+#define GPIO_J_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_SCR_04_0
+#define GPIO_J_SCR_04_0                 MK_ADDR_CONST(0x5024)
+#define GPIO_J_SCR_04_0_SECURE                  0x0
+#define GPIO_J_SCR_04_0_DUAL                    0x0
+#define GPIO_J_SCR_04_0_SCR                     0
+#define GPIO_J_SCR_04_0_SCRREG                  0
+#define GPIO_J_SCR_04_0_WORD_COUNT                      0x1
+#define GPIO_J_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_J_SCR_04_0_SEC_LCK_RANGE                   29:29
+#define GPIO_J_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_04_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_J_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_J_SCR_04_0_SEC_WEN_RANGE                   28:28
+#define GPIO_J_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_04_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_J_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_J_SCR_04_0_SEC_REN_RANGE                   27:27
+#define GPIO_J_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_04_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_J_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_J_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_J_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_J_SCR_04_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_J_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_J_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_J_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_J_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_J_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR7_SHIFT)
+#define GPIO_J_SCR_04_0_PR7_RANGE                       23:23
+#define GPIO_J_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_04_0_PR7_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR6_SHIFT)
+#define GPIO_J_SCR_04_0_PR6_RANGE                       22:22
+#define GPIO_J_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_04_0_PR6_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR5_SHIFT)
+#define GPIO_J_SCR_04_0_PR5_RANGE                       21:21
+#define GPIO_J_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_04_0_PR5_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR4_SHIFT)
+#define GPIO_J_SCR_04_0_PR4_RANGE                       20:20
+#define GPIO_J_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_04_0_PR4_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR3_SHIFT)
+#define GPIO_J_SCR_04_0_PR3_RANGE                       19:19
+#define GPIO_J_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_04_0_PR3_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR2_SHIFT)
+#define GPIO_J_SCR_04_0_PR2_RANGE                       18:18
+#define GPIO_J_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_04_0_PR2_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR1_SHIFT)
+#define GPIO_J_SCR_04_0_PR1_RANGE                       17:17
+#define GPIO_J_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_04_0_PR1_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_PR0_SHIFT)
+#define GPIO_J_SCR_04_0_PR0_RANGE                       16:16
+#define GPIO_J_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_04_0_PR0_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G7W_SHIFT)
+#define GPIO_J_SCR_04_0_G7W_RANGE                       15:15
+#define GPIO_J_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_04_0_G7W_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G6W_SHIFT)
+#define GPIO_J_SCR_04_0_G6W_RANGE                       14:14
+#define GPIO_J_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_04_0_G6W_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G5W_SHIFT)
+#define GPIO_J_SCR_04_0_G5W_RANGE                       13:13
+#define GPIO_J_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_04_0_G5W_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G4W_SHIFT)
+#define GPIO_J_SCR_04_0_G4W_RANGE                       12:12
+#define GPIO_J_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_04_0_G4W_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G3W_SHIFT)
+#define GPIO_J_SCR_04_0_G3W_RANGE                       11:11
+#define GPIO_J_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_04_0_G3W_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G2W_SHIFT)
+#define GPIO_J_SCR_04_0_G2W_RANGE                       10:10
+#define GPIO_J_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_04_0_G2W_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G1W_SHIFT)
+#define GPIO_J_SCR_04_0_G1W_RANGE                       9:9
+#define GPIO_J_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_04_0_G1W_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G0W_SHIFT)
+#define GPIO_J_SCR_04_0_G0W_RANGE                       8:8
+#define GPIO_J_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_04_0_G0W_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G7R_SHIFT)
+#define GPIO_J_SCR_04_0_G7R_RANGE                       7:7
+#define GPIO_J_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_04_0_G7R_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G6R_SHIFT)
+#define GPIO_J_SCR_04_0_G6R_RANGE                       6:6
+#define GPIO_J_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_04_0_G6R_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G5R_SHIFT)
+#define GPIO_J_SCR_04_0_G5R_RANGE                       5:5
+#define GPIO_J_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_04_0_G5R_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G4R_SHIFT)
+#define GPIO_J_SCR_04_0_G4R_RANGE                       4:4
+#define GPIO_J_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_04_0_G4R_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G3R_SHIFT)
+#define GPIO_J_SCR_04_0_G3R_RANGE                       3:3
+#define GPIO_J_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_04_0_G3R_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G2R_SHIFT)
+#define GPIO_J_SCR_04_0_G2R_RANGE                       2:2
+#define GPIO_J_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_04_0_G2R_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G1R_SHIFT)
+#define GPIO_J_SCR_04_0_G1R_RANGE                       1:1
+#define GPIO_J_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_04_0_G1R_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_04_0_G0R_SHIFT)
+#define GPIO_J_SCR_04_0_G0R_RANGE                       0:0
+#define GPIO_J_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_04_0_G0R_WOFFSET                     0x0
+#define GPIO_J_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_VM_05_0
+#define GPIO_J_VM_05_0                  MK_ADDR_CONST(0x5028)
+#define GPIO_J_VM_05_0_SECURE                   0x0
+#define GPIO_J_VM_05_0_DUAL                     0x0
+#define GPIO_J_VM_05_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_J_VM_05_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_J_VM_05_0_WORD_COUNT                       0x1
+#define GPIO_J_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_J_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_J_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM1_SHIFT)
+#define GPIO_J_VM_05_0_VM1_RANGE                        1:0
+#define GPIO_J_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_J_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_J_VM_05_0_VM1_WOFFSET                      0x0
+#define GPIO_J_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_J_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM2_SHIFT)
+#define GPIO_J_VM_05_0_VM2_RANGE                        3:2
+#define GPIO_J_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_J_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_J_VM_05_0_VM2_WOFFSET                      0x0
+#define GPIO_J_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_J_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM3_SHIFT)
+#define GPIO_J_VM_05_0_VM3_RANGE                        5:4
+#define GPIO_J_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_J_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_J_VM_05_0_VM3_WOFFSET                      0x0
+#define GPIO_J_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_J_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM4_SHIFT)
+#define GPIO_J_VM_05_0_VM4_RANGE                        7:6
+#define GPIO_J_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_J_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_J_VM_05_0_VM4_WOFFSET                      0x0
+#define GPIO_J_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_J_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM5_SHIFT)
+#define GPIO_J_VM_05_0_VM5_RANGE                        9:8
+#define GPIO_J_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_J_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_J_VM_05_0_VM5_WOFFSET                      0x0
+#define GPIO_J_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_J_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM6_SHIFT)
+#define GPIO_J_VM_05_0_VM6_RANGE                        11:10
+#define GPIO_J_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_J_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_J_VM_05_0_VM6_WOFFSET                      0x0
+#define GPIO_J_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_J_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM7_SHIFT)
+#define GPIO_J_VM_05_0_VM7_RANGE                        13:12
+#define GPIO_J_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_J_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_J_VM_05_0_VM7_WOFFSET                      0x0
+#define GPIO_J_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_J_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_J_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_J_VM_05_0_VM8_SHIFT)
+#define GPIO_J_VM_05_0_VM8_RANGE                        15:14
+#define GPIO_J_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_J_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_J_VM_05_0_VM8_WOFFSET                      0x0
+#define GPIO_J_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_J_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_J_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_SCR_05_0
+#define GPIO_J_SCR_05_0                 MK_ADDR_CONST(0x502c)
+#define GPIO_J_SCR_05_0_SECURE                  0x0
+#define GPIO_J_SCR_05_0_DUAL                    0x0
+#define GPIO_J_SCR_05_0_SCR                     0
+#define GPIO_J_SCR_05_0_SCRREG                  0
+#define GPIO_J_SCR_05_0_WORD_COUNT                      0x1
+#define GPIO_J_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_J_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_J_SCR_05_0_SEC_LCK_RANGE                   29:29
+#define GPIO_J_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_J_SCR_05_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_J_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_J_SCR_05_0_SEC_WEN_RANGE                   28:28
+#define GPIO_J_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_J_SCR_05_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_J_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_J_SCR_05_0_SEC_REN_RANGE                   27:27
+#define GPIO_J_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_J_SCR_05_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_J_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_J_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_J_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_J_SCR_05_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_J_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_J_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_J_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_J_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_J_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR7_SHIFT)
+#define GPIO_J_SCR_05_0_PR7_RANGE                       23:23
+#define GPIO_J_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_J_SCR_05_0_PR7_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR6_SHIFT)
+#define GPIO_J_SCR_05_0_PR6_RANGE                       22:22
+#define GPIO_J_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_J_SCR_05_0_PR6_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR5_SHIFT)
+#define GPIO_J_SCR_05_0_PR5_RANGE                       21:21
+#define GPIO_J_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_J_SCR_05_0_PR5_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR4_SHIFT)
+#define GPIO_J_SCR_05_0_PR4_RANGE                       20:20
+#define GPIO_J_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_J_SCR_05_0_PR4_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR3_SHIFT)
+#define GPIO_J_SCR_05_0_PR3_RANGE                       19:19
+#define GPIO_J_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_J_SCR_05_0_PR3_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR2_SHIFT)
+#define GPIO_J_SCR_05_0_PR2_RANGE                       18:18
+#define GPIO_J_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_J_SCR_05_0_PR2_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR1_SHIFT)
+#define GPIO_J_SCR_05_0_PR1_RANGE                       17:17
+#define GPIO_J_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_J_SCR_05_0_PR1_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_PR0_SHIFT)
+#define GPIO_J_SCR_05_0_PR0_RANGE                       16:16
+#define GPIO_J_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_J_SCR_05_0_PR0_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G7W_SHIFT)
+#define GPIO_J_SCR_05_0_G7W_RANGE                       15:15
+#define GPIO_J_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_J_SCR_05_0_G7W_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G6W_SHIFT)
+#define GPIO_J_SCR_05_0_G6W_RANGE                       14:14
+#define GPIO_J_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_J_SCR_05_0_G6W_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G5W_SHIFT)
+#define GPIO_J_SCR_05_0_G5W_RANGE                       13:13
+#define GPIO_J_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_J_SCR_05_0_G5W_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G4W_SHIFT)
+#define GPIO_J_SCR_05_0_G4W_RANGE                       12:12
+#define GPIO_J_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_J_SCR_05_0_G4W_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G3W_SHIFT)
+#define GPIO_J_SCR_05_0_G3W_RANGE                       11:11
+#define GPIO_J_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_J_SCR_05_0_G3W_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G2W_SHIFT)
+#define GPIO_J_SCR_05_0_G2W_RANGE                       10:10
+#define GPIO_J_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_J_SCR_05_0_G2W_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G1W_SHIFT)
+#define GPIO_J_SCR_05_0_G1W_RANGE                       9:9
+#define GPIO_J_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_J_SCR_05_0_G1W_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G0W_SHIFT)
+#define GPIO_J_SCR_05_0_G0W_RANGE                       8:8
+#define GPIO_J_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_J_SCR_05_0_G0W_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G7R_SHIFT)
+#define GPIO_J_SCR_05_0_G7R_RANGE                       7:7
+#define GPIO_J_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_J_SCR_05_0_G7R_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G6R_SHIFT)
+#define GPIO_J_SCR_05_0_G6R_RANGE                       6:6
+#define GPIO_J_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_J_SCR_05_0_G6R_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G5R_SHIFT)
+#define GPIO_J_SCR_05_0_G5R_RANGE                       5:5
+#define GPIO_J_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_SCR_05_0_G5R_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G4R_SHIFT)
+#define GPIO_J_SCR_05_0_G4R_RANGE                       4:4
+#define GPIO_J_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_J_SCR_05_0_G4R_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G3R_SHIFT)
+#define GPIO_J_SCR_05_0_G3R_RANGE                       3:3
+#define GPIO_J_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_J_SCR_05_0_G3R_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G2R_SHIFT)
+#define GPIO_J_SCR_05_0_G2R_RANGE                       2:2
+#define GPIO_J_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_J_SCR_05_0_G2R_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G1R_SHIFT)
+#define GPIO_J_SCR_05_0_G1R_RANGE                       1:1
+#define GPIO_J_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_J_SCR_05_0_G1R_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_J_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_SCR_05_0_G0R_SHIFT)
+#define GPIO_J_SCR_05_0_G0R_RANGE                       0:0
+#define GPIO_J_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_SCR_05_0_G0R_WOFFSET                     0x0
+#define GPIO_J_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_J_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x5030
+
+// Reserved address 0x5034
+
+// Reserved address 0x5038
+
+// Reserved address 0x503c
+
+// Register GPIO_C_VM_00_0
+#define GPIO_C_VM_00_0                  MK_ADDR_CONST(0x5040)
+#define GPIO_C_VM_00_0_SECURE                   0x0
+#define GPIO_C_VM_00_0_DUAL                     0x0
+#define GPIO_C_VM_00_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_C_VM_00_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_C_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_C_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_C_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM1_SHIFT)
+#define GPIO_C_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_C_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_C_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_C_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_C_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_C_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM2_SHIFT)
+#define GPIO_C_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_C_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_C_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_C_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_C_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_C_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM3_SHIFT)
+#define GPIO_C_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_C_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_C_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_C_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_C_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_C_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM4_SHIFT)
+#define GPIO_C_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_C_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_C_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_C_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_C_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_C_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM5_SHIFT)
+#define GPIO_C_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_C_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_C_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_C_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_C_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_C_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM6_SHIFT)
+#define GPIO_C_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_C_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_C_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_C_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_C_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_C_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM7_SHIFT)
+#define GPIO_C_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_C_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_C_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_C_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_C_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_C_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_00_0_VM8_SHIFT)
+#define GPIO_C_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_C_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_C_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_C_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_C_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_SCR_00_0
+#define GPIO_C_SCR_00_0                 MK_ADDR_CONST(0x5044)
+#define GPIO_C_SCR_00_0_SECURE                  0x0
+#define GPIO_C_SCR_00_0_DUAL                    0x0
+#define GPIO_C_SCR_00_0_SCR                     0
+#define GPIO_C_SCR_00_0_SCRREG                  0
+#define GPIO_C_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_C_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_C_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_C_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_C_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_C_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_C_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_C_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_C_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_C_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_C_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_C_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_C_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_C_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_C_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_C_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_C_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_C_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_C_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR7_SHIFT)
+#define GPIO_C_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_C_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR6_SHIFT)
+#define GPIO_C_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_C_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR5_SHIFT)
+#define GPIO_C_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_C_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR4_SHIFT)
+#define GPIO_C_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_C_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR3_SHIFT)
+#define GPIO_C_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_C_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR2_SHIFT)
+#define GPIO_C_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_C_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR1_SHIFT)
+#define GPIO_C_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_C_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_PR0_SHIFT)
+#define GPIO_C_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_C_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G7W_SHIFT)
+#define GPIO_C_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_C_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G6W_SHIFT)
+#define GPIO_C_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_C_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G5W_SHIFT)
+#define GPIO_C_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_C_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G4W_SHIFT)
+#define GPIO_C_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_C_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G3W_SHIFT)
+#define GPIO_C_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_C_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G2W_SHIFT)
+#define GPIO_C_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_C_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G1W_SHIFT)
+#define GPIO_C_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_C_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G0W_SHIFT)
+#define GPIO_C_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_C_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G7R_SHIFT)
+#define GPIO_C_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_C_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G6R_SHIFT)
+#define GPIO_C_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_C_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G5R_SHIFT)
+#define GPIO_C_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_C_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G4R_SHIFT)
+#define GPIO_C_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_C_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G3R_SHIFT)
+#define GPIO_C_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_C_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G2R_SHIFT)
+#define GPIO_C_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_C_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G1R_SHIFT)
+#define GPIO_C_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_C_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_00_0_G0R_SHIFT)
+#define GPIO_C_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_C_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_C_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_VM_01_0
+#define GPIO_C_VM_01_0                  MK_ADDR_CONST(0x5048)
+#define GPIO_C_VM_01_0_SECURE                   0x0
+#define GPIO_C_VM_01_0_DUAL                     0x0
+#define GPIO_C_VM_01_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_C_VM_01_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_C_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_C_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_C_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM1_SHIFT)
+#define GPIO_C_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_C_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_C_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_C_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_C_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_C_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM2_SHIFT)
+#define GPIO_C_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_C_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_C_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_C_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_C_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_C_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM3_SHIFT)
+#define GPIO_C_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_C_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_C_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_C_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_C_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_C_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM4_SHIFT)
+#define GPIO_C_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_C_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_C_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_C_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_C_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_C_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM5_SHIFT)
+#define GPIO_C_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_C_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_C_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_C_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_C_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_C_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM6_SHIFT)
+#define GPIO_C_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_C_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_C_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_C_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_C_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_C_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM7_SHIFT)
+#define GPIO_C_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_C_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_C_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_C_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_C_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_C_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_01_0_VM8_SHIFT)
+#define GPIO_C_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_C_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_C_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_C_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_C_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_SCR_01_0
+#define GPIO_C_SCR_01_0                 MK_ADDR_CONST(0x504c)
+#define GPIO_C_SCR_01_0_SECURE                  0x0
+#define GPIO_C_SCR_01_0_DUAL                    0x0
+#define GPIO_C_SCR_01_0_SCR                     0
+#define GPIO_C_SCR_01_0_SCRREG                  0
+#define GPIO_C_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_C_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_C_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_C_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_C_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_C_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_C_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_C_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_C_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_C_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_C_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_C_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_C_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_C_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_C_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_C_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_C_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_C_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_C_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR7_SHIFT)
+#define GPIO_C_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_C_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR6_SHIFT)
+#define GPIO_C_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_C_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR5_SHIFT)
+#define GPIO_C_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_C_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR4_SHIFT)
+#define GPIO_C_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_C_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR3_SHIFT)
+#define GPIO_C_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_C_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR2_SHIFT)
+#define GPIO_C_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_C_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR1_SHIFT)
+#define GPIO_C_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_C_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_PR0_SHIFT)
+#define GPIO_C_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_C_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G7W_SHIFT)
+#define GPIO_C_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_C_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G6W_SHIFT)
+#define GPIO_C_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_C_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G5W_SHIFT)
+#define GPIO_C_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_C_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G4W_SHIFT)
+#define GPIO_C_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_C_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G3W_SHIFT)
+#define GPIO_C_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_C_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G2W_SHIFT)
+#define GPIO_C_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_C_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G1W_SHIFT)
+#define GPIO_C_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_C_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G0W_SHIFT)
+#define GPIO_C_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_C_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G7R_SHIFT)
+#define GPIO_C_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_C_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G6R_SHIFT)
+#define GPIO_C_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_C_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G5R_SHIFT)
+#define GPIO_C_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_C_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G4R_SHIFT)
+#define GPIO_C_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_C_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G3R_SHIFT)
+#define GPIO_C_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_C_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G2R_SHIFT)
+#define GPIO_C_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_C_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G1R_SHIFT)
+#define GPIO_C_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_C_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_01_0_G0R_SHIFT)
+#define GPIO_C_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_C_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_C_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_VM_02_0
+#define GPIO_C_VM_02_0                  MK_ADDR_CONST(0x5050)
+#define GPIO_C_VM_02_0_SECURE                   0x0
+#define GPIO_C_VM_02_0_DUAL                     0x0
+#define GPIO_C_VM_02_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_C_VM_02_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_C_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_C_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_C_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM1_SHIFT)
+#define GPIO_C_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_C_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_C_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_C_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_C_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_C_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM2_SHIFT)
+#define GPIO_C_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_C_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_C_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_C_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_C_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_C_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM3_SHIFT)
+#define GPIO_C_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_C_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_C_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_C_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_C_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_C_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM4_SHIFT)
+#define GPIO_C_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_C_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_C_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_C_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_C_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_C_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM5_SHIFT)
+#define GPIO_C_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_C_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_C_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_C_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_C_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_C_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM6_SHIFT)
+#define GPIO_C_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_C_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_C_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_C_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_C_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_C_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM7_SHIFT)
+#define GPIO_C_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_C_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_C_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_C_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_C_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_C_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_02_0_VM8_SHIFT)
+#define GPIO_C_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_C_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_C_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_C_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_C_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_SCR_02_0
+#define GPIO_C_SCR_02_0                 MK_ADDR_CONST(0x5054)
+#define GPIO_C_SCR_02_0_SECURE                  0x0
+#define GPIO_C_SCR_02_0_DUAL                    0x0
+#define GPIO_C_SCR_02_0_SCR                     0
+#define GPIO_C_SCR_02_0_SCRREG                  0
+#define GPIO_C_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_C_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_C_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_C_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_C_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_C_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_C_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_C_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_C_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_C_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_C_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_C_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_C_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_C_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_C_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_C_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_C_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_C_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_C_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR7_SHIFT)
+#define GPIO_C_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_C_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR6_SHIFT)
+#define GPIO_C_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_C_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR5_SHIFT)
+#define GPIO_C_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_C_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR4_SHIFT)
+#define GPIO_C_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_C_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR3_SHIFT)
+#define GPIO_C_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_C_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR2_SHIFT)
+#define GPIO_C_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_C_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR1_SHIFT)
+#define GPIO_C_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_C_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_PR0_SHIFT)
+#define GPIO_C_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_C_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G7W_SHIFT)
+#define GPIO_C_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_C_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G6W_SHIFT)
+#define GPIO_C_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_C_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G5W_SHIFT)
+#define GPIO_C_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_C_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G4W_SHIFT)
+#define GPIO_C_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_C_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G3W_SHIFT)
+#define GPIO_C_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_C_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G2W_SHIFT)
+#define GPIO_C_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_C_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G1W_SHIFT)
+#define GPIO_C_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_C_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G0W_SHIFT)
+#define GPIO_C_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_C_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G7R_SHIFT)
+#define GPIO_C_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_C_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G6R_SHIFT)
+#define GPIO_C_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_C_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G5R_SHIFT)
+#define GPIO_C_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_C_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G4R_SHIFT)
+#define GPIO_C_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_C_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G3R_SHIFT)
+#define GPIO_C_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_C_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G2R_SHIFT)
+#define GPIO_C_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_C_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G1R_SHIFT)
+#define GPIO_C_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_C_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_02_0_G0R_SHIFT)
+#define GPIO_C_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_C_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_C_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_VM_03_0
+#define GPIO_C_VM_03_0                  MK_ADDR_CONST(0x5058)
+#define GPIO_C_VM_03_0_SECURE                   0x0
+#define GPIO_C_VM_03_0_DUAL                     0x0
+#define GPIO_C_VM_03_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_C_VM_03_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_C_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_C_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_C_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM1_SHIFT)
+#define GPIO_C_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_C_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_C_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_C_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_C_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_C_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM2_SHIFT)
+#define GPIO_C_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_C_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_C_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_C_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_C_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_C_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM3_SHIFT)
+#define GPIO_C_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_C_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_C_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_C_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_C_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_C_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM4_SHIFT)
+#define GPIO_C_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_C_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_C_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_C_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_C_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_C_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM5_SHIFT)
+#define GPIO_C_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_C_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_C_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_C_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_C_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_C_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM6_SHIFT)
+#define GPIO_C_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_C_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_C_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_C_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_C_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_C_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM7_SHIFT)
+#define GPIO_C_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_C_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_C_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_C_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_C_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_C_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_03_0_VM8_SHIFT)
+#define GPIO_C_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_C_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_C_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_C_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_C_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_SCR_03_0
+#define GPIO_C_SCR_03_0                 MK_ADDR_CONST(0x505c)
+#define GPIO_C_SCR_03_0_SECURE                  0x0
+#define GPIO_C_SCR_03_0_DUAL                    0x0
+#define GPIO_C_SCR_03_0_SCR                     0
+#define GPIO_C_SCR_03_0_SCRREG                  0
+#define GPIO_C_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_C_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_C_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_C_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_C_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_C_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_C_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_C_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_C_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_C_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_C_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_C_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_C_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_C_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_C_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_C_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_C_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_C_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_C_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR7_SHIFT)
+#define GPIO_C_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_C_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR6_SHIFT)
+#define GPIO_C_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_C_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR5_SHIFT)
+#define GPIO_C_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_C_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR4_SHIFT)
+#define GPIO_C_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_C_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR3_SHIFT)
+#define GPIO_C_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_C_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR2_SHIFT)
+#define GPIO_C_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_C_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR1_SHIFT)
+#define GPIO_C_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_C_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_PR0_SHIFT)
+#define GPIO_C_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_C_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G7W_SHIFT)
+#define GPIO_C_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_C_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G6W_SHIFT)
+#define GPIO_C_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_C_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G5W_SHIFT)
+#define GPIO_C_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_C_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G4W_SHIFT)
+#define GPIO_C_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_C_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G3W_SHIFT)
+#define GPIO_C_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_C_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G2W_SHIFT)
+#define GPIO_C_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_C_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G1W_SHIFT)
+#define GPIO_C_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_C_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G0W_SHIFT)
+#define GPIO_C_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_C_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G7R_SHIFT)
+#define GPIO_C_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_C_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G6R_SHIFT)
+#define GPIO_C_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_C_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G5R_SHIFT)
+#define GPIO_C_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_C_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G4R_SHIFT)
+#define GPIO_C_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_C_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G3R_SHIFT)
+#define GPIO_C_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_C_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G2R_SHIFT)
+#define GPIO_C_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_C_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G1R_SHIFT)
+#define GPIO_C_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_C_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_03_0_G0R_SHIFT)
+#define GPIO_C_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_C_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_C_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_VM_04_0
+#define GPIO_C_VM_04_0                  MK_ADDR_CONST(0x5060)
+#define GPIO_C_VM_04_0_SECURE                   0x0
+#define GPIO_C_VM_04_0_DUAL                     0x0
+#define GPIO_C_VM_04_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_C_VM_04_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_C_VM_04_0_WORD_COUNT                       0x1
+#define GPIO_C_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_C_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM1_SHIFT)
+#define GPIO_C_VM_04_0_VM1_RANGE                        1:0
+#define GPIO_C_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_C_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_C_VM_04_0_VM1_WOFFSET                      0x0
+#define GPIO_C_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_C_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM2_SHIFT)
+#define GPIO_C_VM_04_0_VM2_RANGE                        3:2
+#define GPIO_C_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_C_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_C_VM_04_0_VM2_WOFFSET                      0x0
+#define GPIO_C_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_C_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM3_SHIFT)
+#define GPIO_C_VM_04_0_VM3_RANGE                        5:4
+#define GPIO_C_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_C_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_C_VM_04_0_VM3_WOFFSET                      0x0
+#define GPIO_C_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_C_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM4_SHIFT)
+#define GPIO_C_VM_04_0_VM4_RANGE                        7:6
+#define GPIO_C_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_C_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_C_VM_04_0_VM4_WOFFSET                      0x0
+#define GPIO_C_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_C_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM5_SHIFT)
+#define GPIO_C_VM_04_0_VM5_RANGE                        9:8
+#define GPIO_C_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_C_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_C_VM_04_0_VM5_WOFFSET                      0x0
+#define GPIO_C_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_C_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM6_SHIFT)
+#define GPIO_C_VM_04_0_VM6_RANGE                        11:10
+#define GPIO_C_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_C_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_C_VM_04_0_VM6_WOFFSET                      0x0
+#define GPIO_C_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_C_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM7_SHIFT)
+#define GPIO_C_VM_04_0_VM7_RANGE                        13:12
+#define GPIO_C_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_C_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_C_VM_04_0_VM7_WOFFSET                      0x0
+#define GPIO_C_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_C_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_04_0_VM8_SHIFT)
+#define GPIO_C_VM_04_0_VM8_RANGE                        15:14
+#define GPIO_C_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_C_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_C_VM_04_0_VM8_WOFFSET                      0x0
+#define GPIO_C_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_SCR_04_0
+#define GPIO_C_SCR_04_0                 MK_ADDR_CONST(0x5064)
+#define GPIO_C_SCR_04_0_SECURE                  0x0
+#define GPIO_C_SCR_04_0_DUAL                    0x0
+#define GPIO_C_SCR_04_0_SCR                     0
+#define GPIO_C_SCR_04_0_SCRREG                  0
+#define GPIO_C_SCR_04_0_WORD_COUNT                      0x1
+#define GPIO_C_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_C_SCR_04_0_SEC_LCK_RANGE                   29:29
+#define GPIO_C_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_04_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_C_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_C_SCR_04_0_SEC_WEN_RANGE                   28:28
+#define GPIO_C_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_04_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_C_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_C_SCR_04_0_SEC_REN_RANGE                   27:27
+#define GPIO_C_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_04_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_C_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_C_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_C_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_C_SCR_04_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_C_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_C_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_C_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_C_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_C_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR7_SHIFT)
+#define GPIO_C_SCR_04_0_PR7_RANGE                       23:23
+#define GPIO_C_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_04_0_PR7_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR6_SHIFT)
+#define GPIO_C_SCR_04_0_PR6_RANGE                       22:22
+#define GPIO_C_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_04_0_PR6_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR5_SHIFT)
+#define GPIO_C_SCR_04_0_PR5_RANGE                       21:21
+#define GPIO_C_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_04_0_PR5_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR4_SHIFT)
+#define GPIO_C_SCR_04_0_PR4_RANGE                       20:20
+#define GPIO_C_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_04_0_PR4_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR3_SHIFT)
+#define GPIO_C_SCR_04_0_PR3_RANGE                       19:19
+#define GPIO_C_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_04_0_PR3_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR2_SHIFT)
+#define GPIO_C_SCR_04_0_PR2_RANGE                       18:18
+#define GPIO_C_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_04_0_PR2_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR1_SHIFT)
+#define GPIO_C_SCR_04_0_PR1_RANGE                       17:17
+#define GPIO_C_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_04_0_PR1_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_PR0_SHIFT)
+#define GPIO_C_SCR_04_0_PR0_RANGE                       16:16
+#define GPIO_C_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_04_0_PR0_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G7W_SHIFT)
+#define GPIO_C_SCR_04_0_G7W_RANGE                       15:15
+#define GPIO_C_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_04_0_G7W_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G6W_SHIFT)
+#define GPIO_C_SCR_04_0_G6W_RANGE                       14:14
+#define GPIO_C_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_04_0_G6W_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G5W_SHIFT)
+#define GPIO_C_SCR_04_0_G5W_RANGE                       13:13
+#define GPIO_C_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_04_0_G5W_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G4W_SHIFT)
+#define GPIO_C_SCR_04_0_G4W_RANGE                       12:12
+#define GPIO_C_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_04_0_G4W_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G3W_SHIFT)
+#define GPIO_C_SCR_04_0_G3W_RANGE                       11:11
+#define GPIO_C_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_04_0_G3W_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G2W_SHIFT)
+#define GPIO_C_SCR_04_0_G2W_RANGE                       10:10
+#define GPIO_C_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_04_0_G2W_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G1W_SHIFT)
+#define GPIO_C_SCR_04_0_G1W_RANGE                       9:9
+#define GPIO_C_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_04_0_G1W_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G0W_SHIFT)
+#define GPIO_C_SCR_04_0_G0W_RANGE                       8:8
+#define GPIO_C_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_04_0_G0W_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G7R_SHIFT)
+#define GPIO_C_SCR_04_0_G7R_RANGE                       7:7
+#define GPIO_C_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_04_0_G7R_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G6R_SHIFT)
+#define GPIO_C_SCR_04_0_G6R_RANGE                       6:6
+#define GPIO_C_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_04_0_G6R_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G5R_SHIFT)
+#define GPIO_C_SCR_04_0_G5R_RANGE                       5:5
+#define GPIO_C_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_04_0_G5R_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G4R_SHIFT)
+#define GPIO_C_SCR_04_0_G4R_RANGE                       4:4
+#define GPIO_C_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_04_0_G4R_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G3R_SHIFT)
+#define GPIO_C_SCR_04_0_G3R_RANGE                       3:3
+#define GPIO_C_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_04_0_G3R_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G2R_SHIFT)
+#define GPIO_C_SCR_04_0_G2R_RANGE                       2:2
+#define GPIO_C_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_04_0_G2R_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G1R_SHIFT)
+#define GPIO_C_SCR_04_0_G1R_RANGE                       1:1
+#define GPIO_C_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_04_0_G1R_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_04_0_G0R_SHIFT)
+#define GPIO_C_SCR_04_0_G0R_RANGE                       0:0
+#define GPIO_C_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_04_0_G0R_WOFFSET                     0x0
+#define GPIO_C_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_VM_05_0
+#define GPIO_C_VM_05_0                  MK_ADDR_CONST(0x5068)
+#define GPIO_C_VM_05_0_SECURE                   0x0
+#define GPIO_C_VM_05_0_DUAL                     0x0
+#define GPIO_C_VM_05_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_C_VM_05_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_C_VM_05_0_WORD_COUNT                       0x1
+#define GPIO_C_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_C_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM1_SHIFT)
+#define GPIO_C_VM_05_0_VM1_RANGE                        1:0
+#define GPIO_C_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_C_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_C_VM_05_0_VM1_WOFFSET                      0x0
+#define GPIO_C_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_C_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM2_SHIFT)
+#define GPIO_C_VM_05_0_VM2_RANGE                        3:2
+#define GPIO_C_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_C_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_C_VM_05_0_VM2_WOFFSET                      0x0
+#define GPIO_C_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_C_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM3_SHIFT)
+#define GPIO_C_VM_05_0_VM3_RANGE                        5:4
+#define GPIO_C_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_C_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_C_VM_05_0_VM3_WOFFSET                      0x0
+#define GPIO_C_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_C_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM4_SHIFT)
+#define GPIO_C_VM_05_0_VM4_RANGE                        7:6
+#define GPIO_C_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_C_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_C_VM_05_0_VM4_WOFFSET                      0x0
+#define GPIO_C_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_C_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM5_SHIFT)
+#define GPIO_C_VM_05_0_VM5_RANGE                        9:8
+#define GPIO_C_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_C_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_C_VM_05_0_VM5_WOFFSET                      0x0
+#define GPIO_C_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_C_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM6_SHIFT)
+#define GPIO_C_VM_05_0_VM6_RANGE                        11:10
+#define GPIO_C_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_C_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_C_VM_05_0_VM6_WOFFSET                      0x0
+#define GPIO_C_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_C_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM7_SHIFT)
+#define GPIO_C_VM_05_0_VM7_RANGE                        13:12
+#define GPIO_C_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_C_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_C_VM_05_0_VM7_WOFFSET                      0x0
+#define GPIO_C_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_C_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_05_0_VM8_SHIFT)
+#define GPIO_C_VM_05_0_VM8_RANGE                        15:14
+#define GPIO_C_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_C_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_C_VM_05_0_VM8_WOFFSET                      0x0
+#define GPIO_C_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_SCR_05_0
+#define GPIO_C_SCR_05_0                 MK_ADDR_CONST(0x506c)
+#define GPIO_C_SCR_05_0_SECURE                  0x0
+#define GPIO_C_SCR_05_0_DUAL                    0x0
+#define GPIO_C_SCR_05_0_SCR                     0
+#define GPIO_C_SCR_05_0_SCRREG                  0
+#define GPIO_C_SCR_05_0_WORD_COUNT                      0x1
+#define GPIO_C_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_C_SCR_05_0_SEC_LCK_RANGE                   29:29
+#define GPIO_C_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_05_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_C_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_C_SCR_05_0_SEC_WEN_RANGE                   28:28
+#define GPIO_C_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_05_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_C_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_C_SCR_05_0_SEC_REN_RANGE                   27:27
+#define GPIO_C_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_05_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_C_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_C_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_C_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_C_SCR_05_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_C_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_C_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_C_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_C_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_C_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR7_SHIFT)
+#define GPIO_C_SCR_05_0_PR7_RANGE                       23:23
+#define GPIO_C_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_05_0_PR7_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR6_SHIFT)
+#define GPIO_C_SCR_05_0_PR6_RANGE                       22:22
+#define GPIO_C_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_05_0_PR6_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR5_SHIFT)
+#define GPIO_C_SCR_05_0_PR5_RANGE                       21:21
+#define GPIO_C_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_05_0_PR5_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR4_SHIFT)
+#define GPIO_C_SCR_05_0_PR4_RANGE                       20:20
+#define GPIO_C_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_05_0_PR4_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR3_SHIFT)
+#define GPIO_C_SCR_05_0_PR3_RANGE                       19:19
+#define GPIO_C_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_05_0_PR3_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR2_SHIFT)
+#define GPIO_C_SCR_05_0_PR2_RANGE                       18:18
+#define GPIO_C_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_05_0_PR2_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR1_SHIFT)
+#define GPIO_C_SCR_05_0_PR1_RANGE                       17:17
+#define GPIO_C_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_05_0_PR1_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_PR0_SHIFT)
+#define GPIO_C_SCR_05_0_PR0_RANGE                       16:16
+#define GPIO_C_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_05_0_PR0_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G7W_SHIFT)
+#define GPIO_C_SCR_05_0_G7W_RANGE                       15:15
+#define GPIO_C_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_05_0_G7W_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G6W_SHIFT)
+#define GPIO_C_SCR_05_0_G6W_RANGE                       14:14
+#define GPIO_C_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_05_0_G6W_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G5W_SHIFT)
+#define GPIO_C_SCR_05_0_G5W_RANGE                       13:13
+#define GPIO_C_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_05_0_G5W_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G4W_SHIFT)
+#define GPIO_C_SCR_05_0_G4W_RANGE                       12:12
+#define GPIO_C_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_05_0_G4W_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G3W_SHIFT)
+#define GPIO_C_SCR_05_0_G3W_RANGE                       11:11
+#define GPIO_C_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_05_0_G3W_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G2W_SHIFT)
+#define GPIO_C_SCR_05_0_G2W_RANGE                       10:10
+#define GPIO_C_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_05_0_G2W_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G1W_SHIFT)
+#define GPIO_C_SCR_05_0_G1W_RANGE                       9:9
+#define GPIO_C_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_05_0_G1W_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G0W_SHIFT)
+#define GPIO_C_SCR_05_0_G0W_RANGE                       8:8
+#define GPIO_C_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_05_0_G0W_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G7R_SHIFT)
+#define GPIO_C_SCR_05_0_G7R_RANGE                       7:7
+#define GPIO_C_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_05_0_G7R_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G6R_SHIFT)
+#define GPIO_C_SCR_05_0_G6R_RANGE                       6:6
+#define GPIO_C_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_05_0_G6R_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G5R_SHIFT)
+#define GPIO_C_SCR_05_0_G5R_RANGE                       5:5
+#define GPIO_C_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_05_0_G5R_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G4R_SHIFT)
+#define GPIO_C_SCR_05_0_G4R_RANGE                       4:4
+#define GPIO_C_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_05_0_G4R_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G3R_SHIFT)
+#define GPIO_C_SCR_05_0_G3R_RANGE                       3:3
+#define GPIO_C_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_05_0_G3R_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G2R_SHIFT)
+#define GPIO_C_SCR_05_0_G2R_RANGE                       2:2
+#define GPIO_C_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_05_0_G2R_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G1R_SHIFT)
+#define GPIO_C_SCR_05_0_G1R_RANGE                       1:1
+#define GPIO_C_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_05_0_G1R_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_05_0_G0R_SHIFT)
+#define GPIO_C_SCR_05_0_G0R_RANGE                       0:0
+#define GPIO_C_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_05_0_G0R_WOFFSET                     0x0
+#define GPIO_C_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_VM_06_0
+#define GPIO_C_VM_06_0                  MK_ADDR_CONST(0x5070)
+#define GPIO_C_VM_06_0_SECURE                   0x0
+#define GPIO_C_VM_06_0_DUAL                     0x0
+#define GPIO_C_VM_06_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_C_VM_06_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_C_VM_06_0_WORD_COUNT                       0x1
+#define GPIO_C_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_C_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM1_SHIFT)
+#define GPIO_C_VM_06_0_VM1_RANGE                        1:0
+#define GPIO_C_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_C_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_C_VM_06_0_VM1_WOFFSET                      0x0
+#define GPIO_C_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_C_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM2_SHIFT)
+#define GPIO_C_VM_06_0_VM2_RANGE                        3:2
+#define GPIO_C_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_C_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_C_VM_06_0_VM2_WOFFSET                      0x0
+#define GPIO_C_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_C_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM3_SHIFT)
+#define GPIO_C_VM_06_0_VM3_RANGE                        5:4
+#define GPIO_C_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_C_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_C_VM_06_0_VM3_WOFFSET                      0x0
+#define GPIO_C_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_C_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM4_SHIFT)
+#define GPIO_C_VM_06_0_VM4_RANGE                        7:6
+#define GPIO_C_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_C_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_C_VM_06_0_VM4_WOFFSET                      0x0
+#define GPIO_C_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_C_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM5_SHIFT)
+#define GPIO_C_VM_06_0_VM5_RANGE                        9:8
+#define GPIO_C_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_C_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_C_VM_06_0_VM5_WOFFSET                      0x0
+#define GPIO_C_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_C_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM6_SHIFT)
+#define GPIO_C_VM_06_0_VM6_RANGE                        11:10
+#define GPIO_C_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_C_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_C_VM_06_0_VM6_WOFFSET                      0x0
+#define GPIO_C_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_C_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM7_SHIFT)
+#define GPIO_C_VM_06_0_VM7_RANGE                        13:12
+#define GPIO_C_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_C_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_C_VM_06_0_VM7_WOFFSET                      0x0
+#define GPIO_C_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_C_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_06_0_VM8_SHIFT)
+#define GPIO_C_VM_06_0_VM8_RANGE                        15:14
+#define GPIO_C_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_C_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_C_VM_06_0_VM8_WOFFSET                      0x0
+#define GPIO_C_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_SCR_06_0
+#define GPIO_C_SCR_06_0                 MK_ADDR_CONST(0x5074)
+#define GPIO_C_SCR_06_0_SECURE                  0x0
+#define GPIO_C_SCR_06_0_DUAL                    0x0
+#define GPIO_C_SCR_06_0_SCR                     0
+#define GPIO_C_SCR_06_0_SCRREG                  0
+#define GPIO_C_SCR_06_0_WORD_COUNT                      0x1
+#define GPIO_C_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_SEC_LCK_SHIFT)
+#define GPIO_C_SCR_06_0_SEC_LCK_RANGE                   29:29
+#define GPIO_C_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_06_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_C_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_SEC_WEN_SHIFT)
+#define GPIO_C_SCR_06_0_SEC_WEN_RANGE                   28:28
+#define GPIO_C_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_06_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_C_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_SEC_REN_SHIFT)
+#define GPIO_C_SCR_06_0_SEC_REN_RANGE                   27:27
+#define GPIO_C_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_06_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_C_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_C_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_C_SCR_06_0_SEC_OWNER_SHIFT)
+#define GPIO_C_SCR_06_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_C_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_C_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_C_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_C_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_C_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR7_SHIFT)
+#define GPIO_C_SCR_06_0_PR7_RANGE                       23:23
+#define GPIO_C_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_06_0_PR7_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR6_SHIFT)
+#define GPIO_C_SCR_06_0_PR6_RANGE                       22:22
+#define GPIO_C_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_06_0_PR6_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR5_SHIFT)
+#define GPIO_C_SCR_06_0_PR5_RANGE                       21:21
+#define GPIO_C_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_06_0_PR5_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR4_SHIFT)
+#define GPIO_C_SCR_06_0_PR4_RANGE                       20:20
+#define GPIO_C_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_06_0_PR4_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR3_SHIFT)
+#define GPIO_C_SCR_06_0_PR3_RANGE                       19:19
+#define GPIO_C_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_06_0_PR3_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR2_SHIFT)
+#define GPIO_C_SCR_06_0_PR2_RANGE                       18:18
+#define GPIO_C_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_06_0_PR2_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR1_SHIFT)
+#define GPIO_C_SCR_06_0_PR1_RANGE                       17:17
+#define GPIO_C_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_06_0_PR1_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_PR0_SHIFT)
+#define GPIO_C_SCR_06_0_PR0_RANGE                       16:16
+#define GPIO_C_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_06_0_PR0_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G7W_SHIFT)
+#define GPIO_C_SCR_06_0_G7W_RANGE                       15:15
+#define GPIO_C_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_06_0_G7W_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G6W_SHIFT)
+#define GPIO_C_SCR_06_0_G6W_RANGE                       14:14
+#define GPIO_C_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_06_0_G6W_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G5W_SHIFT)
+#define GPIO_C_SCR_06_0_G5W_RANGE                       13:13
+#define GPIO_C_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_06_0_G5W_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G4W_SHIFT)
+#define GPIO_C_SCR_06_0_G4W_RANGE                       12:12
+#define GPIO_C_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_06_0_G4W_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G3W_SHIFT)
+#define GPIO_C_SCR_06_0_G3W_RANGE                       11:11
+#define GPIO_C_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_06_0_G3W_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G2W_SHIFT)
+#define GPIO_C_SCR_06_0_G2W_RANGE                       10:10
+#define GPIO_C_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_06_0_G2W_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G1W_SHIFT)
+#define GPIO_C_SCR_06_0_G1W_RANGE                       9:9
+#define GPIO_C_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_06_0_G1W_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G0W_SHIFT)
+#define GPIO_C_SCR_06_0_G0W_RANGE                       8:8
+#define GPIO_C_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_06_0_G0W_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G7R_SHIFT)
+#define GPIO_C_SCR_06_0_G7R_RANGE                       7:7
+#define GPIO_C_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_06_0_G7R_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G6R_SHIFT)
+#define GPIO_C_SCR_06_0_G6R_RANGE                       6:6
+#define GPIO_C_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_06_0_G6R_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G5R_SHIFT)
+#define GPIO_C_SCR_06_0_G5R_RANGE                       5:5
+#define GPIO_C_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_06_0_G5R_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G4R_SHIFT)
+#define GPIO_C_SCR_06_0_G4R_RANGE                       4:4
+#define GPIO_C_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_06_0_G4R_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G3R_SHIFT)
+#define GPIO_C_SCR_06_0_G3R_RANGE                       3:3
+#define GPIO_C_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_06_0_G3R_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G2R_SHIFT)
+#define GPIO_C_SCR_06_0_G2R_RANGE                       2:2
+#define GPIO_C_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_06_0_G2R_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G1R_SHIFT)
+#define GPIO_C_SCR_06_0_G1R_RANGE                       1:1
+#define GPIO_C_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_06_0_G1R_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_06_0_G0R_SHIFT)
+#define GPIO_C_SCR_06_0_G0R_RANGE                       0:0
+#define GPIO_C_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_06_0_G0R_WOFFSET                     0x0
+#define GPIO_C_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_VM_07_0
+#define GPIO_C_VM_07_0                  MK_ADDR_CONST(0x5078)
+#define GPIO_C_VM_07_0_SECURE                   0x0
+#define GPIO_C_VM_07_0_DUAL                     0x0
+#define GPIO_C_VM_07_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_C_VM_07_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_C_VM_07_0_WORD_COUNT                       0x1
+#define GPIO_C_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_C_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_C_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM1_SHIFT)
+#define GPIO_C_VM_07_0_VM1_RANGE                        1:0
+#define GPIO_C_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_C_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_C_VM_07_0_VM1_WOFFSET                      0x0
+#define GPIO_C_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_C_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM2_SHIFT)
+#define GPIO_C_VM_07_0_VM2_RANGE                        3:2
+#define GPIO_C_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_C_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_C_VM_07_0_VM2_WOFFSET                      0x0
+#define GPIO_C_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_C_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM3_SHIFT)
+#define GPIO_C_VM_07_0_VM3_RANGE                        5:4
+#define GPIO_C_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_C_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_C_VM_07_0_VM3_WOFFSET                      0x0
+#define GPIO_C_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_C_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM4_SHIFT)
+#define GPIO_C_VM_07_0_VM4_RANGE                        7:6
+#define GPIO_C_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_C_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_C_VM_07_0_VM4_WOFFSET                      0x0
+#define GPIO_C_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_C_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM5_SHIFT)
+#define GPIO_C_VM_07_0_VM5_RANGE                        9:8
+#define GPIO_C_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_C_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_C_VM_07_0_VM5_WOFFSET                      0x0
+#define GPIO_C_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_C_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM6_SHIFT)
+#define GPIO_C_VM_07_0_VM6_RANGE                        11:10
+#define GPIO_C_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_C_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_C_VM_07_0_VM6_WOFFSET                      0x0
+#define GPIO_C_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_C_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM7_SHIFT)
+#define GPIO_C_VM_07_0_VM7_RANGE                        13:12
+#define GPIO_C_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_C_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_C_VM_07_0_VM7_WOFFSET                      0x0
+#define GPIO_C_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_C_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_C_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_C_VM_07_0_VM8_SHIFT)
+#define GPIO_C_VM_07_0_VM8_RANGE                        15:14
+#define GPIO_C_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_C_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_C_VM_07_0_VM8_WOFFSET                      0x0
+#define GPIO_C_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_C_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_C_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_SCR_07_0
+#define GPIO_C_SCR_07_0                 MK_ADDR_CONST(0x507c)
+#define GPIO_C_SCR_07_0_SECURE                  0x0
+#define GPIO_C_SCR_07_0_DUAL                    0x0
+#define GPIO_C_SCR_07_0_SCR                     0
+#define GPIO_C_SCR_07_0_SCRREG                  0
+#define GPIO_C_SCR_07_0_WORD_COUNT                      0x1
+#define GPIO_C_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_C_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_SEC_LCK_SHIFT)
+#define GPIO_C_SCR_07_0_SEC_LCK_RANGE                   29:29
+#define GPIO_C_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_C_SCR_07_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_C_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_SEC_WEN_SHIFT)
+#define GPIO_C_SCR_07_0_SEC_WEN_RANGE                   28:28
+#define GPIO_C_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_C_SCR_07_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_C_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_SEC_REN_SHIFT)
+#define GPIO_C_SCR_07_0_SEC_REN_RANGE                   27:27
+#define GPIO_C_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_C_SCR_07_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_C_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_C_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_C_SCR_07_0_SEC_OWNER_SHIFT)
+#define GPIO_C_SCR_07_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_C_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_C_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_C_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_C_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_C_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR7_SHIFT)
+#define GPIO_C_SCR_07_0_PR7_RANGE                       23:23
+#define GPIO_C_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_C_SCR_07_0_PR7_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR6_SHIFT)
+#define GPIO_C_SCR_07_0_PR6_RANGE                       22:22
+#define GPIO_C_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_C_SCR_07_0_PR6_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR5_SHIFT)
+#define GPIO_C_SCR_07_0_PR5_RANGE                       21:21
+#define GPIO_C_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_C_SCR_07_0_PR5_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR4_SHIFT)
+#define GPIO_C_SCR_07_0_PR4_RANGE                       20:20
+#define GPIO_C_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_C_SCR_07_0_PR4_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR3_SHIFT)
+#define GPIO_C_SCR_07_0_PR3_RANGE                       19:19
+#define GPIO_C_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_C_SCR_07_0_PR3_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR2_SHIFT)
+#define GPIO_C_SCR_07_0_PR2_RANGE                       18:18
+#define GPIO_C_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_C_SCR_07_0_PR2_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR1_SHIFT)
+#define GPIO_C_SCR_07_0_PR1_RANGE                       17:17
+#define GPIO_C_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_C_SCR_07_0_PR1_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_PR0_SHIFT)
+#define GPIO_C_SCR_07_0_PR0_RANGE                       16:16
+#define GPIO_C_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_C_SCR_07_0_PR0_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G7W_SHIFT)
+#define GPIO_C_SCR_07_0_G7W_RANGE                       15:15
+#define GPIO_C_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_C_SCR_07_0_G7W_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G6W_SHIFT)
+#define GPIO_C_SCR_07_0_G6W_RANGE                       14:14
+#define GPIO_C_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_C_SCR_07_0_G6W_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G5W_SHIFT)
+#define GPIO_C_SCR_07_0_G5W_RANGE                       13:13
+#define GPIO_C_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_C_SCR_07_0_G5W_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G4W_SHIFT)
+#define GPIO_C_SCR_07_0_G4W_RANGE                       12:12
+#define GPIO_C_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_C_SCR_07_0_G4W_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G3W_SHIFT)
+#define GPIO_C_SCR_07_0_G3W_RANGE                       11:11
+#define GPIO_C_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_C_SCR_07_0_G3W_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G2W_SHIFT)
+#define GPIO_C_SCR_07_0_G2W_RANGE                       10:10
+#define GPIO_C_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_C_SCR_07_0_G2W_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G1W_SHIFT)
+#define GPIO_C_SCR_07_0_G1W_RANGE                       9:9
+#define GPIO_C_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_C_SCR_07_0_G1W_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G0W_SHIFT)
+#define GPIO_C_SCR_07_0_G0W_RANGE                       8:8
+#define GPIO_C_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_C_SCR_07_0_G0W_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G7R_SHIFT)
+#define GPIO_C_SCR_07_0_G7R_RANGE                       7:7
+#define GPIO_C_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_C_SCR_07_0_G7R_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G6R_SHIFT)
+#define GPIO_C_SCR_07_0_G6R_RANGE                       6:6
+#define GPIO_C_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_C_SCR_07_0_G6R_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G5R_SHIFT)
+#define GPIO_C_SCR_07_0_G5R_RANGE                       5:5
+#define GPIO_C_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_SCR_07_0_G5R_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G4R_SHIFT)
+#define GPIO_C_SCR_07_0_G4R_RANGE                       4:4
+#define GPIO_C_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_C_SCR_07_0_G4R_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G3R_SHIFT)
+#define GPIO_C_SCR_07_0_G3R_RANGE                       3:3
+#define GPIO_C_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_C_SCR_07_0_G3R_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G2R_SHIFT)
+#define GPIO_C_SCR_07_0_G2R_RANGE                       2:2
+#define GPIO_C_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_C_SCR_07_0_G2R_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G1R_SHIFT)
+#define GPIO_C_SCR_07_0_G1R_RANGE                       1:1
+#define GPIO_C_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_C_SCR_07_0_G1R_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_C_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_SCR_07_0_G0R_SHIFT)
+#define GPIO_C_SCR_07_0_G0R_RANGE                       0:0
+#define GPIO_C_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_SCR_07_0_G0R_WOFFSET                     0x0
+#define GPIO_C_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_C_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_VM_00_0
+#define GPIO_D_VM_00_0                  MK_ADDR_CONST(0x5080)
+#define GPIO_D_VM_00_0_SECURE                   0x0
+#define GPIO_D_VM_00_0_DUAL                     0x0
+#define GPIO_D_VM_00_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_D_VM_00_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_D_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_D_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_D_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_D_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_D_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_D_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_D_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM1_SHIFT)
+#define GPIO_D_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_D_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_D_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_D_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_D_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_D_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM2_SHIFT)
+#define GPIO_D_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_D_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_D_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_D_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_D_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_D_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM3_SHIFT)
+#define GPIO_D_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_D_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_D_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_D_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_D_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_D_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM4_SHIFT)
+#define GPIO_D_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_D_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_D_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_D_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_D_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_D_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM5_SHIFT)
+#define GPIO_D_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_D_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_D_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_D_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_D_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_D_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM6_SHIFT)
+#define GPIO_D_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_D_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_D_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_D_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_D_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_D_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM7_SHIFT)
+#define GPIO_D_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_D_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_D_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_D_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_D_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_D_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_00_0_VM8_SHIFT)
+#define GPIO_D_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_D_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_D_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_D_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_D_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_SCR_00_0
+#define GPIO_D_SCR_00_0                 MK_ADDR_CONST(0x5084)
+#define GPIO_D_SCR_00_0_SECURE                  0x0
+#define GPIO_D_SCR_00_0_DUAL                    0x0
+#define GPIO_D_SCR_00_0_SCR                     0
+#define GPIO_D_SCR_00_0_SCRREG                  0
+#define GPIO_D_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_D_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_D_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_D_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_D_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_D_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_D_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_D_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_D_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_D_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_D_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_D_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_D_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_D_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_D_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_D_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_D_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_D_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_D_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_D_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_D_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_D_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_D_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_D_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_D_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_D_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_D_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_D_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_D_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_D_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_D_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_D_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR7_SHIFT)
+#define GPIO_D_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_D_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_D_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_D_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_D_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR6_SHIFT)
+#define GPIO_D_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_D_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_D_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_D_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_D_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR5_SHIFT)
+#define GPIO_D_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_D_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_D_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_D_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_D_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR4_SHIFT)
+#define GPIO_D_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_D_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_D_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_D_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_D_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR3_SHIFT)
+#define GPIO_D_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_D_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_D_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_D_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_D_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR2_SHIFT)
+#define GPIO_D_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_D_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_D_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_D_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_D_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR1_SHIFT)
+#define GPIO_D_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_D_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_D_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_D_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_D_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_PR0_SHIFT)
+#define GPIO_D_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_D_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_D_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_D_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_D_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G7W_SHIFT)
+#define GPIO_D_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_D_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_D_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_D_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_D_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G6W_SHIFT)
+#define GPIO_D_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_D_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_D_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_D_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_D_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G5W_SHIFT)
+#define GPIO_D_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_D_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_D_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_D_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_D_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G4W_SHIFT)
+#define GPIO_D_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_D_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_D_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_D_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_D_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G3W_SHIFT)
+#define GPIO_D_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_D_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_D_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_D_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_D_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G2W_SHIFT)
+#define GPIO_D_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_D_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_D_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_D_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_D_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G1W_SHIFT)
+#define GPIO_D_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_D_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_D_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_D_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_D_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G0W_SHIFT)
+#define GPIO_D_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_D_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_D_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_D_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_D_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G7R_SHIFT)
+#define GPIO_D_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_D_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_D_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_D_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_D_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G6R_SHIFT)
+#define GPIO_D_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_D_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_D_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_D_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_D_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G5R_SHIFT)
+#define GPIO_D_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_D_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_D_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_D_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_D_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G4R_SHIFT)
+#define GPIO_D_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_D_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_D_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_D_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_D_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G3R_SHIFT)
+#define GPIO_D_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_D_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_D_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_D_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_D_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G2R_SHIFT)
+#define GPIO_D_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_D_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_D_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_D_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_D_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G1R_SHIFT)
+#define GPIO_D_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_D_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_D_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_D_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_D_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_00_0_G0R_SHIFT)
+#define GPIO_D_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_D_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_D_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_D_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_D_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_VM_01_0
+#define GPIO_D_VM_01_0                  MK_ADDR_CONST(0x5088)
+#define GPIO_D_VM_01_0_SECURE                   0x0
+#define GPIO_D_VM_01_0_DUAL                     0x0
+#define GPIO_D_VM_01_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_D_VM_01_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_D_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_D_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_D_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_D_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_D_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_D_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_D_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM1_SHIFT)
+#define GPIO_D_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_D_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_D_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_D_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_D_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_D_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM2_SHIFT)
+#define GPIO_D_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_D_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_D_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_D_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_D_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_D_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM3_SHIFT)
+#define GPIO_D_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_D_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_D_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_D_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_D_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_D_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM4_SHIFT)
+#define GPIO_D_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_D_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_D_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_D_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_D_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_D_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM5_SHIFT)
+#define GPIO_D_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_D_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_D_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_D_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_D_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_D_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM6_SHIFT)
+#define GPIO_D_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_D_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_D_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_D_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_D_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_D_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM7_SHIFT)
+#define GPIO_D_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_D_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_D_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_D_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_D_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_D_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_01_0_VM8_SHIFT)
+#define GPIO_D_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_D_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_D_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_D_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_D_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_SCR_01_0
+#define GPIO_D_SCR_01_0                 MK_ADDR_CONST(0x508c)
+#define GPIO_D_SCR_01_0_SECURE                  0x0
+#define GPIO_D_SCR_01_0_DUAL                    0x0
+#define GPIO_D_SCR_01_0_SCR                     0
+#define GPIO_D_SCR_01_0_SCRREG                  0
+#define GPIO_D_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_D_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_D_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_D_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_D_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_D_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_D_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_D_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_D_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_D_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_D_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_D_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_D_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_D_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_D_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_D_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_D_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_D_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_D_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_D_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_D_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_D_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_D_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_D_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_D_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_D_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_D_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_D_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_D_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_D_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_D_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_D_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR7_SHIFT)
+#define GPIO_D_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_D_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_D_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_D_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_D_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR6_SHIFT)
+#define GPIO_D_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_D_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_D_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_D_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_D_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR5_SHIFT)
+#define GPIO_D_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_D_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_D_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_D_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_D_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR4_SHIFT)
+#define GPIO_D_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_D_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_D_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_D_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_D_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR3_SHIFT)
+#define GPIO_D_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_D_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_D_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_D_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_D_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR2_SHIFT)
+#define GPIO_D_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_D_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_D_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_D_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_D_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR1_SHIFT)
+#define GPIO_D_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_D_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_D_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_D_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_D_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_PR0_SHIFT)
+#define GPIO_D_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_D_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_D_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_D_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_D_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G7W_SHIFT)
+#define GPIO_D_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_D_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_D_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_D_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_D_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G6W_SHIFT)
+#define GPIO_D_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_D_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_D_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_D_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_D_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G5W_SHIFT)
+#define GPIO_D_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_D_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_D_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_D_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_D_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G4W_SHIFT)
+#define GPIO_D_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_D_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_D_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_D_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_D_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G3W_SHIFT)
+#define GPIO_D_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_D_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_D_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_D_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_D_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G2W_SHIFT)
+#define GPIO_D_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_D_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_D_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_D_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_D_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G1W_SHIFT)
+#define GPIO_D_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_D_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_D_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_D_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_D_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G0W_SHIFT)
+#define GPIO_D_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_D_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_D_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_D_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_D_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G7R_SHIFT)
+#define GPIO_D_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_D_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_D_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_D_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_D_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G6R_SHIFT)
+#define GPIO_D_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_D_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_D_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_D_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_D_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G5R_SHIFT)
+#define GPIO_D_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_D_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_D_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_D_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_D_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G4R_SHIFT)
+#define GPIO_D_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_D_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_D_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_D_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_D_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G3R_SHIFT)
+#define GPIO_D_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_D_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_D_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_D_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_D_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G2R_SHIFT)
+#define GPIO_D_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_D_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_D_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_D_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_D_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G1R_SHIFT)
+#define GPIO_D_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_D_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_D_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_D_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_D_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_01_0_G0R_SHIFT)
+#define GPIO_D_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_D_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_D_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_D_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_D_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_VM_02_0
+#define GPIO_D_VM_02_0                  MK_ADDR_CONST(0x5090)
+#define GPIO_D_VM_02_0_SECURE                   0x0
+#define GPIO_D_VM_02_0_DUAL                     0x0
+#define GPIO_D_VM_02_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_D_VM_02_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_D_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_D_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_D_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_D_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_D_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_D_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_D_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM1_SHIFT)
+#define GPIO_D_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_D_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_D_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_D_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_D_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_D_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM2_SHIFT)
+#define GPIO_D_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_D_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_D_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_D_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_D_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_D_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM3_SHIFT)
+#define GPIO_D_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_D_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_D_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_D_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_D_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_D_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM4_SHIFT)
+#define GPIO_D_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_D_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_D_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_D_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_D_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_D_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM5_SHIFT)
+#define GPIO_D_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_D_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_D_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_D_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_D_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_D_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM6_SHIFT)
+#define GPIO_D_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_D_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_D_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_D_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_D_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_D_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM7_SHIFT)
+#define GPIO_D_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_D_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_D_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_D_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_D_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_D_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_02_0_VM8_SHIFT)
+#define GPIO_D_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_D_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_D_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_D_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_D_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_SCR_02_0
+#define GPIO_D_SCR_02_0                 MK_ADDR_CONST(0x5094)
+#define GPIO_D_SCR_02_0_SECURE                  0x0
+#define GPIO_D_SCR_02_0_DUAL                    0x0
+#define GPIO_D_SCR_02_0_SCR                     0
+#define GPIO_D_SCR_02_0_SCRREG                  0
+#define GPIO_D_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_D_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_D_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_D_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_D_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_D_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_D_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_D_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_D_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_D_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_D_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_D_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_D_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_D_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_D_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_D_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_D_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_D_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_D_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_D_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_D_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_D_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_D_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_D_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_D_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_D_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_D_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_D_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_D_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_D_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_D_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_D_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR7_SHIFT)
+#define GPIO_D_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_D_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_D_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_D_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_D_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR6_SHIFT)
+#define GPIO_D_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_D_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_D_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_D_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_D_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR5_SHIFT)
+#define GPIO_D_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_D_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_D_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_D_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_D_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR4_SHIFT)
+#define GPIO_D_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_D_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_D_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_D_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_D_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR3_SHIFT)
+#define GPIO_D_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_D_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_D_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_D_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_D_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR2_SHIFT)
+#define GPIO_D_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_D_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_D_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_D_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_D_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR1_SHIFT)
+#define GPIO_D_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_D_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_D_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_D_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_D_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_PR0_SHIFT)
+#define GPIO_D_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_D_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_D_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_D_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_D_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G7W_SHIFT)
+#define GPIO_D_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_D_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_D_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_D_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_D_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G6W_SHIFT)
+#define GPIO_D_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_D_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_D_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_D_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_D_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G5W_SHIFT)
+#define GPIO_D_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_D_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_D_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_D_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_D_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G4W_SHIFT)
+#define GPIO_D_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_D_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_D_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_D_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_D_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G3W_SHIFT)
+#define GPIO_D_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_D_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_D_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_D_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_D_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G2W_SHIFT)
+#define GPIO_D_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_D_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_D_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_D_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_D_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G1W_SHIFT)
+#define GPIO_D_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_D_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_D_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_D_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_D_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G0W_SHIFT)
+#define GPIO_D_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_D_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_D_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_D_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_D_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G7R_SHIFT)
+#define GPIO_D_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_D_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_D_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_D_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_D_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G6R_SHIFT)
+#define GPIO_D_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_D_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_D_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_D_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_D_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G5R_SHIFT)
+#define GPIO_D_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_D_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_D_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_D_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_D_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G4R_SHIFT)
+#define GPIO_D_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_D_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_D_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_D_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_D_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G3R_SHIFT)
+#define GPIO_D_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_D_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_D_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_D_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_D_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G2R_SHIFT)
+#define GPIO_D_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_D_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_D_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_D_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_D_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G1R_SHIFT)
+#define GPIO_D_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_D_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_D_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_D_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_D_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_02_0_G0R_SHIFT)
+#define GPIO_D_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_D_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_D_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_D_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_D_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_VM_03_0
+#define GPIO_D_VM_03_0                  MK_ADDR_CONST(0x5098)
+#define GPIO_D_VM_03_0_SECURE                   0x0
+#define GPIO_D_VM_03_0_DUAL                     0x0
+#define GPIO_D_VM_03_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_D_VM_03_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_D_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_D_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_D_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_D_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_D_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_D_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_D_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM1_SHIFT)
+#define GPIO_D_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_D_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_D_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_D_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_D_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_D_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM2_SHIFT)
+#define GPIO_D_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_D_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_D_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_D_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_D_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_D_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM3_SHIFT)
+#define GPIO_D_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_D_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_D_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_D_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_D_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_D_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM4_SHIFT)
+#define GPIO_D_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_D_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_D_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_D_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_D_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_D_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM5_SHIFT)
+#define GPIO_D_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_D_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_D_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_D_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_D_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_D_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM6_SHIFT)
+#define GPIO_D_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_D_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_D_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_D_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_D_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_D_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM7_SHIFT)
+#define GPIO_D_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_D_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_D_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_D_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_D_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_D_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_D_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_D_VM_03_0_VM8_SHIFT)
+#define GPIO_D_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_D_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_D_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_D_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_D_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_D_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_D_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_SCR_03_0
+#define GPIO_D_SCR_03_0                 MK_ADDR_CONST(0x509c)
+#define GPIO_D_SCR_03_0_SECURE                  0x0
+#define GPIO_D_SCR_03_0_DUAL                    0x0
+#define GPIO_D_SCR_03_0_SCR                     0
+#define GPIO_D_SCR_03_0_SCRREG                  0
+#define GPIO_D_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_D_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_D_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_D_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_D_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_D_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_D_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_D_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_D_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_D_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_D_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_D_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_D_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_D_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_D_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_D_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_D_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_D_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_D_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_D_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_D_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_D_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_D_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_D_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_D_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_D_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_D_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_D_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_D_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_D_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_D_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_D_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR7_SHIFT)
+#define GPIO_D_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_D_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_D_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_D_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_D_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR6_SHIFT)
+#define GPIO_D_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_D_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_D_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_D_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_D_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR5_SHIFT)
+#define GPIO_D_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_D_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_D_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_D_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_D_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR4_SHIFT)
+#define GPIO_D_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_D_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_D_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_D_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_D_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR3_SHIFT)
+#define GPIO_D_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_D_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_D_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_D_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_D_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR2_SHIFT)
+#define GPIO_D_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_D_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_D_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_D_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_D_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR1_SHIFT)
+#define GPIO_D_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_D_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_D_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_D_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_D_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_PR0_SHIFT)
+#define GPIO_D_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_D_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_D_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_D_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_D_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G7W_SHIFT)
+#define GPIO_D_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_D_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_D_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_D_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_D_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G6W_SHIFT)
+#define GPIO_D_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_D_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_D_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_D_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_D_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G5W_SHIFT)
+#define GPIO_D_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_D_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_D_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_D_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_D_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G4W_SHIFT)
+#define GPIO_D_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_D_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_D_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_D_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_D_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G3W_SHIFT)
+#define GPIO_D_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_D_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_D_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_D_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_D_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G2W_SHIFT)
+#define GPIO_D_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_D_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_D_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_D_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_D_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G1W_SHIFT)
+#define GPIO_D_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_D_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_D_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_D_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_D_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G0W_SHIFT)
+#define GPIO_D_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_D_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_D_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_D_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_D_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G7R_SHIFT)
+#define GPIO_D_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_D_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_D_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_D_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_D_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G6R_SHIFT)
+#define GPIO_D_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_D_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_D_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_D_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_D_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G5R_SHIFT)
+#define GPIO_D_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_D_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_D_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_D_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_D_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G4R_SHIFT)
+#define GPIO_D_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_D_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_D_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_D_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_D_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G3R_SHIFT)
+#define GPIO_D_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_D_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_D_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_D_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_D_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G2R_SHIFT)
+#define GPIO_D_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_D_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_D_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_D_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_D_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G1R_SHIFT)
+#define GPIO_D_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_D_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_D_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_D_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_D_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_D_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_SCR_03_0_G0R_SHIFT)
+#define GPIO_D_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_D_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_D_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_D_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_D_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_D_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x50a0
+
+// Reserved address 0x50a4
+
+// Reserved address 0x50a8
+
+// Reserved address 0x50ac
+
+// Reserved address 0x50b0
+
+// Reserved address 0x50b4
+
+// Reserved address 0x50b8
+
+// Reserved address 0x50bc
+
+// Register GPIO_E_VM_00_0
+#define GPIO_E_VM_00_0                  MK_ADDR_CONST(0x50c0)
+#define GPIO_E_VM_00_0_SECURE                   0x0
+#define GPIO_E_VM_00_0_DUAL                     0x0
+#define GPIO_E_VM_00_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_E_VM_00_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_E_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_E_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_E_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM1_SHIFT)
+#define GPIO_E_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_E_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_E_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_E_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_E_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_E_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM2_SHIFT)
+#define GPIO_E_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_E_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_E_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_E_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_E_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_E_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM3_SHIFT)
+#define GPIO_E_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_E_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_E_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_E_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_E_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_E_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM4_SHIFT)
+#define GPIO_E_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_E_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_E_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_E_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_E_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_E_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM5_SHIFT)
+#define GPIO_E_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_E_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_E_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_E_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_E_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_E_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM6_SHIFT)
+#define GPIO_E_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_E_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_E_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_E_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_E_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_E_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM7_SHIFT)
+#define GPIO_E_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_E_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_E_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_E_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_E_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_E_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_00_0_VM8_SHIFT)
+#define GPIO_E_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_E_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_E_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_E_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_E_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_SCR_00_0
+#define GPIO_E_SCR_00_0                 MK_ADDR_CONST(0x50c4)
+#define GPIO_E_SCR_00_0_SECURE                  0x0
+#define GPIO_E_SCR_00_0_DUAL                    0x0
+#define GPIO_E_SCR_00_0_SCR                     0
+#define GPIO_E_SCR_00_0_SCRREG                  0
+#define GPIO_E_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_E_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_E_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_E_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_E_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_E_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_E_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_E_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_E_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_E_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_E_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_E_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_E_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_E_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_E_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_E_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_E_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_E_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_E_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR7_SHIFT)
+#define GPIO_E_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_E_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR6_SHIFT)
+#define GPIO_E_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_E_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR5_SHIFT)
+#define GPIO_E_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_E_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR4_SHIFT)
+#define GPIO_E_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_E_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR3_SHIFT)
+#define GPIO_E_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_E_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR2_SHIFT)
+#define GPIO_E_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_E_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR1_SHIFT)
+#define GPIO_E_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_E_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_PR0_SHIFT)
+#define GPIO_E_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_E_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G7W_SHIFT)
+#define GPIO_E_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_E_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G6W_SHIFT)
+#define GPIO_E_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_E_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G5W_SHIFT)
+#define GPIO_E_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_E_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G4W_SHIFT)
+#define GPIO_E_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_E_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G3W_SHIFT)
+#define GPIO_E_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_E_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G2W_SHIFT)
+#define GPIO_E_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_E_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G1W_SHIFT)
+#define GPIO_E_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_E_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G0W_SHIFT)
+#define GPIO_E_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_E_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G7R_SHIFT)
+#define GPIO_E_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_E_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G6R_SHIFT)
+#define GPIO_E_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_E_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G5R_SHIFT)
+#define GPIO_E_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_E_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G4R_SHIFT)
+#define GPIO_E_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_E_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G3R_SHIFT)
+#define GPIO_E_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_E_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G2R_SHIFT)
+#define GPIO_E_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_E_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G1R_SHIFT)
+#define GPIO_E_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_E_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_00_0_G0R_SHIFT)
+#define GPIO_E_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_E_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_E_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_VM_01_0
+#define GPIO_E_VM_01_0                  MK_ADDR_CONST(0x50c8)
+#define GPIO_E_VM_01_0_SECURE                   0x0
+#define GPIO_E_VM_01_0_DUAL                     0x0
+#define GPIO_E_VM_01_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_E_VM_01_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_E_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_E_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_E_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM1_SHIFT)
+#define GPIO_E_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_E_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_E_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_E_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_E_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_E_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM2_SHIFT)
+#define GPIO_E_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_E_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_E_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_E_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_E_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_E_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM3_SHIFT)
+#define GPIO_E_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_E_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_E_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_E_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_E_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_E_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM4_SHIFT)
+#define GPIO_E_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_E_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_E_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_E_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_E_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_E_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM5_SHIFT)
+#define GPIO_E_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_E_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_E_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_E_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_E_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_E_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM6_SHIFT)
+#define GPIO_E_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_E_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_E_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_E_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_E_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_E_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM7_SHIFT)
+#define GPIO_E_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_E_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_E_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_E_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_E_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_E_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_01_0_VM8_SHIFT)
+#define GPIO_E_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_E_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_E_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_E_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_E_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_SCR_01_0
+#define GPIO_E_SCR_01_0                 MK_ADDR_CONST(0x50cc)
+#define GPIO_E_SCR_01_0_SECURE                  0x0
+#define GPIO_E_SCR_01_0_DUAL                    0x0
+#define GPIO_E_SCR_01_0_SCR                     0
+#define GPIO_E_SCR_01_0_SCRREG                  0
+#define GPIO_E_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_E_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_E_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_E_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_E_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_E_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_E_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_E_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_E_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_E_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_E_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_E_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_E_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_E_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_E_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_E_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_E_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_E_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_E_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR7_SHIFT)
+#define GPIO_E_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_E_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR6_SHIFT)
+#define GPIO_E_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_E_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR5_SHIFT)
+#define GPIO_E_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_E_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR4_SHIFT)
+#define GPIO_E_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_E_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR3_SHIFT)
+#define GPIO_E_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_E_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR2_SHIFT)
+#define GPIO_E_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_E_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR1_SHIFT)
+#define GPIO_E_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_E_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_PR0_SHIFT)
+#define GPIO_E_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_E_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G7W_SHIFT)
+#define GPIO_E_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_E_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G6W_SHIFT)
+#define GPIO_E_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_E_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G5W_SHIFT)
+#define GPIO_E_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_E_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G4W_SHIFT)
+#define GPIO_E_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_E_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G3W_SHIFT)
+#define GPIO_E_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_E_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G2W_SHIFT)
+#define GPIO_E_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_E_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G1W_SHIFT)
+#define GPIO_E_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_E_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G0W_SHIFT)
+#define GPIO_E_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_E_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G7R_SHIFT)
+#define GPIO_E_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_E_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G6R_SHIFT)
+#define GPIO_E_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_E_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G5R_SHIFT)
+#define GPIO_E_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_E_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G4R_SHIFT)
+#define GPIO_E_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_E_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G3R_SHIFT)
+#define GPIO_E_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_E_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G2R_SHIFT)
+#define GPIO_E_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_E_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G1R_SHIFT)
+#define GPIO_E_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_E_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_01_0_G0R_SHIFT)
+#define GPIO_E_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_E_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_E_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_VM_02_0
+#define GPIO_E_VM_02_0                  MK_ADDR_CONST(0x50d0)
+#define GPIO_E_VM_02_0_SECURE                   0x0
+#define GPIO_E_VM_02_0_DUAL                     0x0
+#define GPIO_E_VM_02_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_E_VM_02_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_E_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_E_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_E_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM1_SHIFT)
+#define GPIO_E_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_E_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_E_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_E_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_E_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_E_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM2_SHIFT)
+#define GPIO_E_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_E_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_E_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_E_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_E_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_E_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM3_SHIFT)
+#define GPIO_E_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_E_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_E_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_E_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_E_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_E_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM4_SHIFT)
+#define GPIO_E_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_E_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_E_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_E_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_E_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_E_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM5_SHIFT)
+#define GPIO_E_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_E_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_E_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_E_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_E_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_E_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM6_SHIFT)
+#define GPIO_E_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_E_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_E_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_E_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_E_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_E_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM7_SHIFT)
+#define GPIO_E_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_E_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_E_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_E_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_E_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_E_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_02_0_VM8_SHIFT)
+#define GPIO_E_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_E_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_E_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_E_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_E_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_SCR_02_0
+#define GPIO_E_SCR_02_0                 MK_ADDR_CONST(0x50d4)
+#define GPIO_E_SCR_02_0_SECURE                  0x0
+#define GPIO_E_SCR_02_0_DUAL                    0x0
+#define GPIO_E_SCR_02_0_SCR                     0
+#define GPIO_E_SCR_02_0_SCRREG                  0
+#define GPIO_E_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_E_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_E_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_E_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_E_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_E_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_E_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_E_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_E_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_E_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_E_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_E_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_E_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_E_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_E_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_E_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_E_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_E_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_E_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR7_SHIFT)
+#define GPIO_E_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_E_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR6_SHIFT)
+#define GPIO_E_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_E_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR5_SHIFT)
+#define GPIO_E_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_E_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR4_SHIFT)
+#define GPIO_E_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_E_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR3_SHIFT)
+#define GPIO_E_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_E_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR2_SHIFT)
+#define GPIO_E_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_E_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR1_SHIFT)
+#define GPIO_E_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_E_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_PR0_SHIFT)
+#define GPIO_E_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_E_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G7W_SHIFT)
+#define GPIO_E_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_E_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G6W_SHIFT)
+#define GPIO_E_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_E_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G5W_SHIFT)
+#define GPIO_E_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_E_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G4W_SHIFT)
+#define GPIO_E_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_E_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G3W_SHIFT)
+#define GPIO_E_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_E_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G2W_SHIFT)
+#define GPIO_E_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_E_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G1W_SHIFT)
+#define GPIO_E_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_E_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G0W_SHIFT)
+#define GPIO_E_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_E_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G7R_SHIFT)
+#define GPIO_E_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_E_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G6R_SHIFT)
+#define GPIO_E_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_E_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G5R_SHIFT)
+#define GPIO_E_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_E_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G4R_SHIFT)
+#define GPIO_E_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_E_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G3R_SHIFT)
+#define GPIO_E_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_E_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G2R_SHIFT)
+#define GPIO_E_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_E_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G1R_SHIFT)
+#define GPIO_E_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_E_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_02_0_G0R_SHIFT)
+#define GPIO_E_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_E_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_E_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_VM_03_0
+#define GPIO_E_VM_03_0                  MK_ADDR_CONST(0x50d8)
+#define GPIO_E_VM_03_0_SECURE                   0x0
+#define GPIO_E_VM_03_0_DUAL                     0x0
+#define GPIO_E_VM_03_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_E_VM_03_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_E_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_E_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_E_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM1_SHIFT)
+#define GPIO_E_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_E_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_E_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_E_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_E_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_E_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM2_SHIFT)
+#define GPIO_E_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_E_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_E_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_E_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_E_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_E_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM3_SHIFT)
+#define GPIO_E_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_E_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_E_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_E_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_E_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_E_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM4_SHIFT)
+#define GPIO_E_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_E_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_E_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_E_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_E_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_E_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM5_SHIFT)
+#define GPIO_E_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_E_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_E_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_E_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_E_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_E_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM6_SHIFT)
+#define GPIO_E_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_E_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_E_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_E_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_E_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_E_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM7_SHIFT)
+#define GPIO_E_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_E_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_E_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_E_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_E_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_E_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_03_0_VM8_SHIFT)
+#define GPIO_E_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_E_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_E_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_E_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_E_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_SCR_03_0
+#define GPIO_E_SCR_03_0                 MK_ADDR_CONST(0x50dc)
+#define GPIO_E_SCR_03_0_SECURE                  0x0
+#define GPIO_E_SCR_03_0_DUAL                    0x0
+#define GPIO_E_SCR_03_0_SCR                     0
+#define GPIO_E_SCR_03_0_SCRREG                  0
+#define GPIO_E_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_E_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_E_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_E_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_E_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_E_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_E_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_E_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_E_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_E_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_E_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_E_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_E_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_E_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_E_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_E_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_E_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_E_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_E_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR7_SHIFT)
+#define GPIO_E_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_E_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR6_SHIFT)
+#define GPIO_E_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_E_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR5_SHIFT)
+#define GPIO_E_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_E_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR4_SHIFT)
+#define GPIO_E_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_E_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR3_SHIFT)
+#define GPIO_E_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_E_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR2_SHIFT)
+#define GPIO_E_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_E_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR1_SHIFT)
+#define GPIO_E_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_E_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_PR0_SHIFT)
+#define GPIO_E_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_E_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G7W_SHIFT)
+#define GPIO_E_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_E_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G6W_SHIFT)
+#define GPIO_E_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_E_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G5W_SHIFT)
+#define GPIO_E_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_E_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G4W_SHIFT)
+#define GPIO_E_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_E_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G3W_SHIFT)
+#define GPIO_E_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_E_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G2W_SHIFT)
+#define GPIO_E_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_E_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G1W_SHIFT)
+#define GPIO_E_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_E_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G0W_SHIFT)
+#define GPIO_E_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_E_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G7R_SHIFT)
+#define GPIO_E_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_E_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G6R_SHIFT)
+#define GPIO_E_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_E_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G5R_SHIFT)
+#define GPIO_E_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_E_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G4R_SHIFT)
+#define GPIO_E_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_E_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G3R_SHIFT)
+#define GPIO_E_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_E_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G2R_SHIFT)
+#define GPIO_E_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_E_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G1R_SHIFT)
+#define GPIO_E_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_E_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_03_0_G0R_SHIFT)
+#define GPIO_E_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_E_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_E_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_VM_04_0
+#define GPIO_E_VM_04_0                  MK_ADDR_CONST(0x50e0)
+#define GPIO_E_VM_04_0_SECURE                   0x0
+#define GPIO_E_VM_04_0_DUAL                     0x0
+#define GPIO_E_VM_04_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_E_VM_04_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_E_VM_04_0_WORD_COUNT                       0x1
+#define GPIO_E_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_E_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM1_SHIFT)
+#define GPIO_E_VM_04_0_VM1_RANGE                        1:0
+#define GPIO_E_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_E_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_E_VM_04_0_VM1_WOFFSET                      0x0
+#define GPIO_E_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_E_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM2_SHIFT)
+#define GPIO_E_VM_04_0_VM2_RANGE                        3:2
+#define GPIO_E_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_E_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_E_VM_04_0_VM2_WOFFSET                      0x0
+#define GPIO_E_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_E_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM3_SHIFT)
+#define GPIO_E_VM_04_0_VM3_RANGE                        5:4
+#define GPIO_E_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_E_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_E_VM_04_0_VM3_WOFFSET                      0x0
+#define GPIO_E_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_E_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM4_SHIFT)
+#define GPIO_E_VM_04_0_VM4_RANGE                        7:6
+#define GPIO_E_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_E_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_E_VM_04_0_VM4_WOFFSET                      0x0
+#define GPIO_E_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_E_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM5_SHIFT)
+#define GPIO_E_VM_04_0_VM5_RANGE                        9:8
+#define GPIO_E_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_E_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_E_VM_04_0_VM5_WOFFSET                      0x0
+#define GPIO_E_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_E_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM6_SHIFT)
+#define GPIO_E_VM_04_0_VM6_RANGE                        11:10
+#define GPIO_E_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_E_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_E_VM_04_0_VM6_WOFFSET                      0x0
+#define GPIO_E_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_E_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM7_SHIFT)
+#define GPIO_E_VM_04_0_VM7_RANGE                        13:12
+#define GPIO_E_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_E_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_E_VM_04_0_VM7_WOFFSET                      0x0
+#define GPIO_E_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_E_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_04_0_VM8_SHIFT)
+#define GPIO_E_VM_04_0_VM8_RANGE                        15:14
+#define GPIO_E_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_E_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_E_VM_04_0_VM8_WOFFSET                      0x0
+#define GPIO_E_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_SCR_04_0
+#define GPIO_E_SCR_04_0                 MK_ADDR_CONST(0x50e4)
+#define GPIO_E_SCR_04_0_SECURE                  0x0
+#define GPIO_E_SCR_04_0_DUAL                    0x0
+#define GPIO_E_SCR_04_0_SCR                     0
+#define GPIO_E_SCR_04_0_SCRREG                  0
+#define GPIO_E_SCR_04_0_WORD_COUNT                      0x1
+#define GPIO_E_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_E_SCR_04_0_SEC_LCK_RANGE                   29:29
+#define GPIO_E_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_04_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_E_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_E_SCR_04_0_SEC_WEN_RANGE                   28:28
+#define GPIO_E_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_04_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_E_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_E_SCR_04_0_SEC_REN_RANGE                   27:27
+#define GPIO_E_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_04_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_E_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_E_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_E_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_E_SCR_04_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_E_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_E_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_E_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_E_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_E_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR7_SHIFT)
+#define GPIO_E_SCR_04_0_PR7_RANGE                       23:23
+#define GPIO_E_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_04_0_PR7_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR6_SHIFT)
+#define GPIO_E_SCR_04_0_PR6_RANGE                       22:22
+#define GPIO_E_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_04_0_PR6_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR5_SHIFT)
+#define GPIO_E_SCR_04_0_PR5_RANGE                       21:21
+#define GPIO_E_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_04_0_PR5_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR4_SHIFT)
+#define GPIO_E_SCR_04_0_PR4_RANGE                       20:20
+#define GPIO_E_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_04_0_PR4_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR3_SHIFT)
+#define GPIO_E_SCR_04_0_PR3_RANGE                       19:19
+#define GPIO_E_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_04_0_PR3_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR2_SHIFT)
+#define GPIO_E_SCR_04_0_PR2_RANGE                       18:18
+#define GPIO_E_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_04_0_PR2_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR1_SHIFT)
+#define GPIO_E_SCR_04_0_PR1_RANGE                       17:17
+#define GPIO_E_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_04_0_PR1_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_PR0_SHIFT)
+#define GPIO_E_SCR_04_0_PR0_RANGE                       16:16
+#define GPIO_E_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_04_0_PR0_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G7W_SHIFT)
+#define GPIO_E_SCR_04_0_G7W_RANGE                       15:15
+#define GPIO_E_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_04_0_G7W_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G6W_SHIFT)
+#define GPIO_E_SCR_04_0_G6W_RANGE                       14:14
+#define GPIO_E_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_04_0_G6W_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G5W_SHIFT)
+#define GPIO_E_SCR_04_0_G5W_RANGE                       13:13
+#define GPIO_E_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_04_0_G5W_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G4W_SHIFT)
+#define GPIO_E_SCR_04_0_G4W_RANGE                       12:12
+#define GPIO_E_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_04_0_G4W_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G3W_SHIFT)
+#define GPIO_E_SCR_04_0_G3W_RANGE                       11:11
+#define GPIO_E_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_04_0_G3W_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G2W_SHIFT)
+#define GPIO_E_SCR_04_0_G2W_RANGE                       10:10
+#define GPIO_E_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_04_0_G2W_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G1W_SHIFT)
+#define GPIO_E_SCR_04_0_G1W_RANGE                       9:9
+#define GPIO_E_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_04_0_G1W_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G0W_SHIFT)
+#define GPIO_E_SCR_04_0_G0W_RANGE                       8:8
+#define GPIO_E_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_04_0_G0W_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G7R_SHIFT)
+#define GPIO_E_SCR_04_0_G7R_RANGE                       7:7
+#define GPIO_E_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_04_0_G7R_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G6R_SHIFT)
+#define GPIO_E_SCR_04_0_G6R_RANGE                       6:6
+#define GPIO_E_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_04_0_G6R_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G5R_SHIFT)
+#define GPIO_E_SCR_04_0_G5R_RANGE                       5:5
+#define GPIO_E_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_04_0_G5R_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G4R_SHIFT)
+#define GPIO_E_SCR_04_0_G4R_RANGE                       4:4
+#define GPIO_E_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_04_0_G4R_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G3R_SHIFT)
+#define GPIO_E_SCR_04_0_G3R_RANGE                       3:3
+#define GPIO_E_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_04_0_G3R_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G2R_SHIFT)
+#define GPIO_E_SCR_04_0_G2R_RANGE                       2:2
+#define GPIO_E_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_04_0_G2R_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G1R_SHIFT)
+#define GPIO_E_SCR_04_0_G1R_RANGE                       1:1
+#define GPIO_E_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_04_0_G1R_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_04_0_G0R_SHIFT)
+#define GPIO_E_SCR_04_0_G0R_RANGE                       0:0
+#define GPIO_E_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_04_0_G0R_WOFFSET                     0x0
+#define GPIO_E_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_VM_05_0
+#define GPIO_E_VM_05_0                  MK_ADDR_CONST(0x50e8)
+#define GPIO_E_VM_05_0_SECURE                   0x0
+#define GPIO_E_VM_05_0_DUAL                     0x0
+#define GPIO_E_VM_05_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_E_VM_05_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_E_VM_05_0_WORD_COUNT                       0x1
+#define GPIO_E_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_E_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM1_SHIFT)
+#define GPIO_E_VM_05_0_VM1_RANGE                        1:0
+#define GPIO_E_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_E_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_E_VM_05_0_VM1_WOFFSET                      0x0
+#define GPIO_E_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_E_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM2_SHIFT)
+#define GPIO_E_VM_05_0_VM2_RANGE                        3:2
+#define GPIO_E_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_E_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_E_VM_05_0_VM2_WOFFSET                      0x0
+#define GPIO_E_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_E_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM3_SHIFT)
+#define GPIO_E_VM_05_0_VM3_RANGE                        5:4
+#define GPIO_E_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_E_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_E_VM_05_0_VM3_WOFFSET                      0x0
+#define GPIO_E_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_E_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM4_SHIFT)
+#define GPIO_E_VM_05_0_VM4_RANGE                        7:6
+#define GPIO_E_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_E_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_E_VM_05_0_VM4_WOFFSET                      0x0
+#define GPIO_E_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_E_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM5_SHIFT)
+#define GPIO_E_VM_05_0_VM5_RANGE                        9:8
+#define GPIO_E_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_E_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_E_VM_05_0_VM5_WOFFSET                      0x0
+#define GPIO_E_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_E_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM6_SHIFT)
+#define GPIO_E_VM_05_0_VM6_RANGE                        11:10
+#define GPIO_E_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_E_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_E_VM_05_0_VM6_WOFFSET                      0x0
+#define GPIO_E_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_E_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM7_SHIFT)
+#define GPIO_E_VM_05_0_VM7_RANGE                        13:12
+#define GPIO_E_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_E_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_E_VM_05_0_VM7_WOFFSET                      0x0
+#define GPIO_E_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_E_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_05_0_VM8_SHIFT)
+#define GPIO_E_VM_05_0_VM8_RANGE                        15:14
+#define GPIO_E_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_E_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_E_VM_05_0_VM8_WOFFSET                      0x0
+#define GPIO_E_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_SCR_05_0
+#define GPIO_E_SCR_05_0                 MK_ADDR_CONST(0x50ec)
+#define GPIO_E_SCR_05_0_SECURE                  0x0
+#define GPIO_E_SCR_05_0_DUAL                    0x0
+#define GPIO_E_SCR_05_0_SCR                     0
+#define GPIO_E_SCR_05_0_SCRREG                  0
+#define GPIO_E_SCR_05_0_WORD_COUNT                      0x1
+#define GPIO_E_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_E_SCR_05_0_SEC_LCK_RANGE                   29:29
+#define GPIO_E_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_05_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_E_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_E_SCR_05_0_SEC_WEN_RANGE                   28:28
+#define GPIO_E_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_05_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_E_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_E_SCR_05_0_SEC_REN_RANGE                   27:27
+#define GPIO_E_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_05_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_E_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_E_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_E_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_E_SCR_05_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_E_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_E_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_E_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_E_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_E_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR7_SHIFT)
+#define GPIO_E_SCR_05_0_PR7_RANGE                       23:23
+#define GPIO_E_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_05_0_PR7_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR6_SHIFT)
+#define GPIO_E_SCR_05_0_PR6_RANGE                       22:22
+#define GPIO_E_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_05_0_PR6_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR5_SHIFT)
+#define GPIO_E_SCR_05_0_PR5_RANGE                       21:21
+#define GPIO_E_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_05_0_PR5_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR4_SHIFT)
+#define GPIO_E_SCR_05_0_PR4_RANGE                       20:20
+#define GPIO_E_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_05_0_PR4_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR3_SHIFT)
+#define GPIO_E_SCR_05_0_PR3_RANGE                       19:19
+#define GPIO_E_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_05_0_PR3_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR2_SHIFT)
+#define GPIO_E_SCR_05_0_PR2_RANGE                       18:18
+#define GPIO_E_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_05_0_PR2_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR1_SHIFT)
+#define GPIO_E_SCR_05_0_PR1_RANGE                       17:17
+#define GPIO_E_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_05_0_PR1_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_PR0_SHIFT)
+#define GPIO_E_SCR_05_0_PR0_RANGE                       16:16
+#define GPIO_E_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_05_0_PR0_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G7W_SHIFT)
+#define GPIO_E_SCR_05_0_G7W_RANGE                       15:15
+#define GPIO_E_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_05_0_G7W_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G6W_SHIFT)
+#define GPIO_E_SCR_05_0_G6W_RANGE                       14:14
+#define GPIO_E_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_05_0_G6W_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G5W_SHIFT)
+#define GPIO_E_SCR_05_0_G5W_RANGE                       13:13
+#define GPIO_E_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_05_0_G5W_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G4W_SHIFT)
+#define GPIO_E_SCR_05_0_G4W_RANGE                       12:12
+#define GPIO_E_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_05_0_G4W_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G3W_SHIFT)
+#define GPIO_E_SCR_05_0_G3W_RANGE                       11:11
+#define GPIO_E_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_05_0_G3W_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G2W_SHIFT)
+#define GPIO_E_SCR_05_0_G2W_RANGE                       10:10
+#define GPIO_E_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_05_0_G2W_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G1W_SHIFT)
+#define GPIO_E_SCR_05_0_G1W_RANGE                       9:9
+#define GPIO_E_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_05_0_G1W_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G0W_SHIFT)
+#define GPIO_E_SCR_05_0_G0W_RANGE                       8:8
+#define GPIO_E_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_05_0_G0W_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G7R_SHIFT)
+#define GPIO_E_SCR_05_0_G7R_RANGE                       7:7
+#define GPIO_E_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_05_0_G7R_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G6R_SHIFT)
+#define GPIO_E_SCR_05_0_G6R_RANGE                       6:6
+#define GPIO_E_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_05_0_G6R_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G5R_SHIFT)
+#define GPIO_E_SCR_05_0_G5R_RANGE                       5:5
+#define GPIO_E_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_05_0_G5R_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G4R_SHIFT)
+#define GPIO_E_SCR_05_0_G4R_RANGE                       4:4
+#define GPIO_E_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_05_0_G4R_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G3R_SHIFT)
+#define GPIO_E_SCR_05_0_G3R_RANGE                       3:3
+#define GPIO_E_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_05_0_G3R_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G2R_SHIFT)
+#define GPIO_E_SCR_05_0_G2R_RANGE                       2:2
+#define GPIO_E_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_05_0_G2R_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G1R_SHIFT)
+#define GPIO_E_SCR_05_0_G1R_RANGE                       1:1
+#define GPIO_E_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_05_0_G1R_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_05_0_G0R_SHIFT)
+#define GPIO_E_SCR_05_0_G0R_RANGE                       0:0
+#define GPIO_E_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_05_0_G0R_WOFFSET                     0x0
+#define GPIO_E_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_VM_06_0
+#define GPIO_E_VM_06_0                  MK_ADDR_CONST(0x50f0)
+#define GPIO_E_VM_06_0_SECURE                   0x0
+#define GPIO_E_VM_06_0_DUAL                     0x0
+#define GPIO_E_VM_06_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_E_VM_06_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_E_VM_06_0_WORD_COUNT                       0x1
+#define GPIO_E_VM_06_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_06_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_06_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_06_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_E_VM_06_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM1_SHIFT)
+#define GPIO_E_VM_06_0_VM1_RANGE                        1:0
+#define GPIO_E_VM_06_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_E_VM_06_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_E_VM_06_0_VM1_WOFFSET                      0x0
+#define GPIO_E_VM_06_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_06_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_06_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_06_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_E_VM_06_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM2_SHIFT)
+#define GPIO_E_VM_06_0_VM2_RANGE                        3:2
+#define GPIO_E_VM_06_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_E_VM_06_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_E_VM_06_0_VM2_WOFFSET                      0x0
+#define GPIO_E_VM_06_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_06_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_06_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_06_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_E_VM_06_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM3_SHIFT)
+#define GPIO_E_VM_06_0_VM3_RANGE                        5:4
+#define GPIO_E_VM_06_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_E_VM_06_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_E_VM_06_0_VM3_WOFFSET                      0x0
+#define GPIO_E_VM_06_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_06_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_06_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_06_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_E_VM_06_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM4_SHIFT)
+#define GPIO_E_VM_06_0_VM4_RANGE                        7:6
+#define GPIO_E_VM_06_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_E_VM_06_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_E_VM_06_0_VM4_WOFFSET                      0x0
+#define GPIO_E_VM_06_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_06_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_06_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_06_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_E_VM_06_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM5_SHIFT)
+#define GPIO_E_VM_06_0_VM5_RANGE                        9:8
+#define GPIO_E_VM_06_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_E_VM_06_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_E_VM_06_0_VM5_WOFFSET                      0x0
+#define GPIO_E_VM_06_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_06_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_06_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_06_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_E_VM_06_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM6_SHIFT)
+#define GPIO_E_VM_06_0_VM6_RANGE                        11:10
+#define GPIO_E_VM_06_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_E_VM_06_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_E_VM_06_0_VM6_WOFFSET                      0x0
+#define GPIO_E_VM_06_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_06_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_06_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_06_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_E_VM_06_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM7_SHIFT)
+#define GPIO_E_VM_06_0_VM7_RANGE                        13:12
+#define GPIO_E_VM_06_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_E_VM_06_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_E_VM_06_0_VM7_WOFFSET                      0x0
+#define GPIO_E_VM_06_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_06_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_06_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_06_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_E_VM_06_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_06_0_VM8_SHIFT)
+#define GPIO_E_VM_06_0_VM8_RANGE                        15:14
+#define GPIO_E_VM_06_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_E_VM_06_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_E_VM_06_0_VM8_WOFFSET                      0x0
+#define GPIO_E_VM_06_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_06_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_06_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_06_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_SCR_06_0
+#define GPIO_E_SCR_06_0                 MK_ADDR_CONST(0x50f4)
+#define GPIO_E_SCR_06_0_SECURE                  0x0
+#define GPIO_E_SCR_06_0_DUAL                    0x0
+#define GPIO_E_SCR_06_0_SCR                     0
+#define GPIO_E_SCR_06_0_SCRREG                  0
+#define GPIO_E_SCR_06_0_WORD_COUNT                      0x1
+#define GPIO_E_SCR_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_06_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_06_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_06_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_SEC_LCK_SHIFT)
+#define GPIO_E_SCR_06_0_SEC_LCK_RANGE                   29:29
+#define GPIO_E_SCR_06_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_06_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_06_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_E_SCR_06_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_06_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_SEC_WEN_SHIFT)
+#define GPIO_E_SCR_06_0_SEC_WEN_RANGE                   28:28
+#define GPIO_E_SCR_06_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_06_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_06_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_E_SCR_06_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_06_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_SEC_REN_SHIFT)
+#define GPIO_E_SCR_06_0_SEC_REN_RANGE                   27:27
+#define GPIO_E_SCR_06_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_06_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_06_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_E_SCR_06_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_E_SCR_06_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_E_SCR_06_0_SEC_OWNER_SHIFT)
+#define GPIO_E_SCR_06_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_E_SCR_06_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_E_SCR_06_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_E_SCR_06_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_E_SCR_06_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_E_SCR_06_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_06_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR7_SHIFT)
+#define GPIO_E_SCR_06_0_PR7_RANGE                       23:23
+#define GPIO_E_SCR_06_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_06_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_06_0_PR7_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_06_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR6_SHIFT)
+#define GPIO_E_SCR_06_0_PR6_RANGE                       22:22
+#define GPIO_E_SCR_06_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_06_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_06_0_PR6_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_06_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR5_SHIFT)
+#define GPIO_E_SCR_06_0_PR5_RANGE                       21:21
+#define GPIO_E_SCR_06_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_06_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_06_0_PR5_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_06_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR4_SHIFT)
+#define GPIO_E_SCR_06_0_PR4_RANGE                       20:20
+#define GPIO_E_SCR_06_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_06_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_06_0_PR4_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_06_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR3_SHIFT)
+#define GPIO_E_SCR_06_0_PR3_RANGE                       19:19
+#define GPIO_E_SCR_06_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_06_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_06_0_PR3_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_06_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR2_SHIFT)
+#define GPIO_E_SCR_06_0_PR2_RANGE                       18:18
+#define GPIO_E_SCR_06_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_06_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_06_0_PR2_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_06_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR1_SHIFT)
+#define GPIO_E_SCR_06_0_PR1_RANGE                       17:17
+#define GPIO_E_SCR_06_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_06_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_06_0_PR1_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_06_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_PR0_SHIFT)
+#define GPIO_E_SCR_06_0_PR0_RANGE                       16:16
+#define GPIO_E_SCR_06_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_06_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_06_0_PR0_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_06_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G7W_SHIFT)
+#define GPIO_E_SCR_06_0_G7W_RANGE                       15:15
+#define GPIO_E_SCR_06_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_06_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_06_0_G7W_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_06_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G6W_SHIFT)
+#define GPIO_E_SCR_06_0_G6W_RANGE                       14:14
+#define GPIO_E_SCR_06_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_06_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_06_0_G6W_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_06_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G5W_SHIFT)
+#define GPIO_E_SCR_06_0_G5W_RANGE                       13:13
+#define GPIO_E_SCR_06_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_06_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_06_0_G5W_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_06_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G4W_SHIFT)
+#define GPIO_E_SCR_06_0_G4W_RANGE                       12:12
+#define GPIO_E_SCR_06_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_06_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_06_0_G4W_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_06_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G3W_SHIFT)
+#define GPIO_E_SCR_06_0_G3W_RANGE                       11:11
+#define GPIO_E_SCR_06_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_06_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_06_0_G3W_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_06_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G2W_SHIFT)
+#define GPIO_E_SCR_06_0_G2W_RANGE                       10:10
+#define GPIO_E_SCR_06_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_06_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_06_0_G2W_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_06_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G1W_SHIFT)
+#define GPIO_E_SCR_06_0_G1W_RANGE                       9:9
+#define GPIO_E_SCR_06_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_06_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_06_0_G1W_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_06_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G0W_SHIFT)
+#define GPIO_E_SCR_06_0_G0W_RANGE                       8:8
+#define GPIO_E_SCR_06_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_06_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_06_0_G0W_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_06_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G7R_SHIFT)
+#define GPIO_E_SCR_06_0_G7R_RANGE                       7:7
+#define GPIO_E_SCR_06_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_06_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_06_0_G7R_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_06_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G6R_SHIFT)
+#define GPIO_E_SCR_06_0_G6R_RANGE                       6:6
+#define GPIO_E_SCR_06_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_06_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_06_0_G6R_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_06_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G5R_SHIFT)
+#define GPIO_E_SCR_06_0_G5R_RANGE                       5:5
+#define GPIO_E_SCR_06_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_06_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_06_0_G5R_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_06_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G4R_SHIFT)
+#define GPIO_E_SCR_06_0_G4R_RANGE                       4:4
+#define GPIO_E_SCR_06_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_06_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_06_0_G4R_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_06_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G3R_SHIFT)
+#define GPIO_E_SCR_06_0_G3R_RANGE                       3:3
+#define GPIO_E_SCR_06_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_06_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_06_0_G3R_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_06_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G2R_SHIFT)
+#define GPIO_E_SCR_06_0_G2R_RANGE                       2:2
+#define GPIO_E_SCR_06_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_06_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_06_0_G2R_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_06_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G1R_SHIFT)
+#define GPIO_E_SCR_06_0_G1R_RANGE                       1:1
+#define GPIO_E_SCR_06_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_06_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_06_0_G1R_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_06_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_06_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_06_0_G0R_SHIFT)
+#define GPIO_E_SCR_06_0_G0R_RANGE                       0:0
+#define GPIO_E_SCR_06_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_06_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_06_0_G0R_WOFFSET                     0x0
+#define GPIO_E_SCR_06_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_06_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_06_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_VM_07_0
+#define GPIO_E_VM_07_0                  MK_ADDR_CONST(0x50f8)
+#define GPIO_E_VM_07_0_SECURE                   0x0
+#define GPIO_E_VM_07_0_DUAL                     0x0
+#define GPIO_E_VM_07_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_E_VM_07_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_E_VM_07_0_WORD_COUNT                       0x1
+#define GPIO_E_VM_07_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_07_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_07_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_E_VM_07_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_E_VM_07_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM1_SHIFT)
+#define GPIO_E_VM_07_0_VM1_RANGE                        1:0
+#define GPIO_E_VM_07_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_E_VM_07_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_E_VM_07_0_VM1_WOFFSET                      0x0
+#define GPIO_E_VM_07_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_07_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_07_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_07_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_E_VM_07_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM2_SHIFT)
+#define GPIO_E_VM_07_0_VM2_RANGE                        3:2
+#define GPIO_E_VM_07_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_E_VM_07_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_E_VM_07_0_VM2_WOFFSET                      0x0
+#define GPIO_E_VM_07_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_07_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_07_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_07_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_E_VM_07_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM3_SHIFT)
+#define GPIO_E_VM_07_0_VM3_RANGE                        5:4
+#define GPIO_E_VM_07_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_E_VM_07_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_E_VM_07_0_VM3_WOFFSET                      0x0
+#define GPIO_E_VM_07_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_07_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_07_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_07_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_E_VM_07_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM4_SHIFT)
+#define GPIO_E_VM_07_0_VM4_RANGE                        7:6
+#define GPIO_E_VM_07_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_E_VM_07_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_E_VM_07_0_VM4_WOFFSET                      0x0
+#define GPIO_E_VM_07_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_07_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_07_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_07_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_E_VM_07_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM5_SHIFT)
+#define GPIO_E_VM_07_0_VM5_RANGE                        9:8
+#define GPIO_E_VM_07_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_E_VM_07_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_E_VM_07_0_VM5_WOFFSET                      0x0
+#define GPIO_E_VM_07_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_07_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_07_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_07_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_E_VM_07_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM6_SHIFT)
+#define GPIO_E_VM_07_0_VM6_RANGE                        11:10
+#define GPIO_E_VM_07_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_E_VM_07_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_E_VM_07_0_VM6_WOFFSET                      0x0
+#define GPIO_E_VM_07_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_07_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_07_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_07_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_E_VM_07_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM7_SHIFT)
+#define GPIO_E_VM_07_0_VM7_RANGE                        13:12
+#define GPIO_E_VM_07_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_E_VM_07_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_E_VM_07_0_VM7_WOFFSET                      0x0
+#define GPIO_E_VM_07_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_07_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_07_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_E_VM_07_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_E_VM_07_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_E_VM_07_0_VM8_SHIFT)
+#define GPIO_E_VM_07_0_VM8_RANGE                        15:14
+#define GPIO_E_VM_07_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_E_VM_07_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_E_VM_07_0_VM8_WOFFSET                      0x0
+#define GPIO_E_VM_07_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_E_VM_07_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_E_VM_07_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_VM_07_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_SCR_07_0
+#define GPIO_E_SCR_07_0                 MK_ADDR_CONST(0x50fc)
+#define GPIO_E_SCR_07_0_SECURE                  0x0
+#define GPIO_E_SCR_07_0_DUAL                    0x0
+#define GPIO_E_SCR_07_0_SCR                     0
+#define GPIO_E_SCR_07_0_SCRREG                  0
+#define GPIO_E_SCR_07_0_WORD_COUNT                      0x1
+#define GPIO_E_SCR_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_07_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_E_SCR_07_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_07_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_SEC_LCK_SHIFT)
+#define GPIO_E_SCR_07_0_SEC_LCK_RANGE                   29:29
+#define GPIO_E_SCR_07_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_07_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_E_SCR_07_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_E_SCR_07_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_07_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_SEC_WEN_SHIFT)
+#define GPIO_E_SCR_07_0_SEC_WEN_RANGE                   28:28
+#define GPIO_E_SCR_07_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_07_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_E_SCR_07_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_E_SCR_07_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_07_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_SEC_REN_SHIFT)
+#define GPIO_E_SCR_07_0_SEC_REN_RANGE                   27:27
+#define GPIO_E_SCR_07_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_07_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_E_SCR_07_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_E_SCR_07_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_E_SCR_07_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_E_SCR_07_0_SEC_OWNER_SHIFT)
+#define GPIO_E_SCR_07_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_E_SCR_07_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_E_SCR_07_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_E_SCR_07_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_E_SCR_07_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_E_SCR_07_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_07_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR7_SHIFT)
+#define GPIO_E_SCR_07_0_PR7_RANGE                       23:23
+#define GPIO_E_SCR_07_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_07_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_E_SCR_07_0_PR7_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_07_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR6_SHIFT)
+#define GPIO_E_SCR_07_0_PR6_RANGE                       22:22
+#define GPIO_E_SCR_07_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_07_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_E_SCR_07_0_PR6_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_07_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR5_SHIFT)
+#define GPIO_E_SCR_07_0_PR5_RANGE                       21:21
+#define GPIO_E_SCR_07_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_07_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_E_SCR_07_0_PR5_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_07_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR4_SHIFT)
+#define GPIO_E_SCR_07_0_PR4_RANGE                       20:20
+#define GPIO_E_SCR_07_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_07_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_E_SCR_07_0_PR4_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_07_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR3_SHIFT)
+#define GPIO_E_SCR_07_0_PR3_RANGE                       19:19
+#define GPIO_E_SCR_07_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_07_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_E_SCR_07_0_PR3_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_07_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR2_SHIFT)
+#define GPIO_E_SCR_07_0_PR2_RANGE                       18:18
+#define GPIO_E_SCR_07_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_07_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_E_SCR_07_0_PR2_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_07_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR1_SHIFT)
+#define GPIO_E_SCR_07_0_PR1_RANGE                       17:17
+#define GPIO_E_SCR_07_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_07_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_E_SCR_07_0_PR1_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_07_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_PR0_SHIFT)
+#define GPIO_E_SCR_07_0_PR0_RANGE                       16:16
+#define GPIO_E_SCR_07_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_07_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_E_SCR_07_0_PR0_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_07_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G7W_SHIFT)
+#define GPIO_E_SCR_07_0_G7W_RANGE                       15:15
+#define GPIO_E_SCR_07_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_07_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_E_SCR_07_0_G7W_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_07_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G6W_SHIFT)
+#define GPIO_E_SCR_07_0_G6W_RANGE                       14:14
+#define GPIO_E_SCR_07_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_07_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_E_SCR_07_0_G6W_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_07_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G5W_SHIFT)
+#define GPIO_E_SCR_07_0_G5W_RANGE                       13:13
+#define GPIO_E_SCR_07_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_07_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_E_SCR_07_0_G5W_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_07_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G4W_SHIFT)
+#define GPIO_E_SCR_07_0_G4W_RANGE                       12:12
+#define GPIO_E_SCR_07_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_07_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_E_SCR_07_0_G4W_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_07_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G3W_SHIFT)
+#define GPIO_E_SCR_07_0_G3W_RANGE                       11:11
+#define GPIO_E_SCR_07_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_07_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_E_SCR_07_0_G3W_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_07_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G2W_SHIFT)
+#define GPIO_E_SCR_07_0_G2W_RANGE                       10:10
+#define GPIO_E_SCR_07_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_07_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_E_SCR_07_0_G2W_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_07_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G1W_SHIFT)
+#define GPIO_E_SCR_07_0_G1W_RANGE                       9:9
+#define GPIO_E_SCR_07_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_07_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_E_SCR_07_0_G1W_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_07_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G0W_SHIFT)
+#define GPIO_E_SCR_07_0_G0W_RANGE                       8:8
+#define GPIO_E_SCR_07_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_07_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_E_SCR_07_0_G0W_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_07_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G7R_SHIFT)
+#define GPIO_E_SCR_07_0_G7R_RANGE                       7:7
+#define GPIO_E_SCR_07_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_07_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_E_SCR_07_0_G7R_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_07_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G6R_SHIFT)
+#define GPIO_E_SCR_07_0_G6R_RANGE                       6:6
+#define GPIO_E_SCR_07_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_07_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_E_SCR_07_0_G6R_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_07_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G5R_SHIFT)
+#define GPIO_E_SCR_07_0_G5R_RANGE                       5:5
+#define GPIO_E_SCR_07_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_07_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_SCR_07_0_G5R_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_07_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G4R_SHIFT)
+#define GPIO_E_SCR_07_0_G4R_RANGE                       4:4
+#define GPIO_E_SCR_07_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_07_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_E_SCR_07_0_G4R_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_07_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G3R_SHIFT)
+#define GPIO_E_SCR_07_0_G3R_RANGE                       3:3
+#define GPIO_E_SCR_07_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_07_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_E_SCR_07_0_G3R_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_07_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G2R_SHIFT)
+#define GPIO_E_SCR_07_0_G2R_RANGE                       2:2
+#define GPIO_E_SCR_07_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_07_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_E_SCR_07_0_G2R_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_07_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G1R_SHIFT)
+#define GPIO_E_SCR_07_0_G1R_RANGE                       1:1
+#define GPIO_E_SCR_07_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_07_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_E_SCR_07_0_G1R_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_E_SCR_07_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_07_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_SCR_07_0_G0R_SHIFT)
+#define GPIO_E_SCR_07_0_G0R_RANGE                       0:0
+#define GPIO_E_SCR_07_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_07_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_SCR_07_0_G0R_WOFFSET                     0x0
+#define GPIO_E_SCR_07_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_SCR_07_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_E_SCR_07_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_VM_00_0
+#define GPIO_F_VM_00_0                  MK_ADDR_CONST(0x5100)
+#define GPIO_F_VM_00_0_SECURE                   0x0
+#define GPIO_F_VM_00_0_DUAL                     0x0
+#define GPIO_F_VM_00_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_F_VM_00_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_F_VM_00_0_WORD_COUNT                       0x1
+#define GPIO_F_VM_00_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_00_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_00_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_00_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_F_VM_00_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM1_SHIFT)
+#define GPIO_F_VM_00_0_VM1_RANGE                        1:0
+#define GPIO_F_VM_00_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_F_VM_00_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_F_VM_00_0_VM1_WOFFSET                      0x0
+#define GPIO_F_VM_00_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_00_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_00_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_00_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_F_VM_00_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM2_SHIFT)
+#define GPIO_F_VM_00_0_VM2_RANGE                        3:2
+#define GPIO_F_VM_00_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_F_VM_00_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_F_VM_00_0_VM2_WOFFSET                      0x0
+#define GPIO_F_VM_00_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_00_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_00_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_00_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_F_VM_00_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM3_SHIFT)
+#define GPIO_F_VM_00_0_VM3_RANGE                        5:4
+#define GPIO_F_VM_00_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_F_VM_00_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_F_VM_00_0_VM3_WOFFSET                      0x0
+#define GPIO_F_VM_00_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_00_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_00_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_00_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_F_VM_00_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM4_SHIFT)
+#define GPIO_F_VM_00_0_VM4_RANGE                        7:6
+#define GPIO_F_VM_00_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_F_VM_00_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_F_VM_00_0_VM4_WOFFSET                      0x0
+#define GPIO_F_VM_00_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_00_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_00_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_00_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_F_VM_00_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM5_SHIFT)
+#define GPIO_F_VM_00_0_VM5_RANGE                        9:8
+#define GPIO_F_VM_00_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_F_VM_00_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_F_VM_00_0_VM5_WOFFSET                      0x0
+#define GPIO_F_VM_00_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_00_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_00_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_00_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_F_VM_00_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM6_SHIFT)
+#define GPIO_F_VM_00_0_VM6_RANGE                        11:10
+#define GPIO_F_VM_00_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_F_VM_00_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_F_VM_00_0_VM6_WOFFSET                      0x0
+#define GPIO_F_VM_00_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_00_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_00_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_00_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_F_VM_00_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM7_SHIFT)
+#define GPIO_F_VM_00_0_VM7_RANGE                        13:12
+#define GPIO_F_VM_00_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_F_VM_00_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_F_VM_00_0_VM7_WOFFSET                      0x0
+#define GPIO_F_VM_00_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_00_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_00_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_00_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_F_VM_00_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_00_0_VM8_SHIFT)
+#define GPIO_F_VM_00_0_VM8_RANGE                        15:14
+#define GPIO_F_VM_00_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_F_VM_00_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_F_VM_00_0_VM8_WOFFSET                      0x0
+#define GPIO_F_VM_00_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_00_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_00_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_00_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_SCR_00_0
+#define GPIO_F_SCR_00_0                 MK_ADDR_CONST(0x5104)
+#define GPIO_F_SCR_00_0_SECURE                  0x0
+#define GPIO_F_SCR_00_0_DUAL                    0x0
+#define GPIO_F_SCR_00_0_SCR                     0
+#define GPIO_F_SCR_00_0_SCRREG                  0
+#define GPIO_F_SCR_00_0_WORD_COUNT                      0x1
+#define GPIO_F_SCR_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_00_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_00_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_00_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_SEC_LCK_SHIFT)
+#define GPIO_F_SCR_00_0_SEC_LCK_RANGE                   29:29
+#define GPIO_F_SCR_00_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_00_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_00_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_F_SCR_00_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_00_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_SEC_WEN_SHIFT)
+#define GPIO_F_SCR_00_0_SEC_WEN_RANGE                   28:28
+#define GPIO_F_SCR_00_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_00_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_00_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_F_SCR_00_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_00_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_SEC_REN_SHIFT)
+#define GPIO_F_SCR_00_0_SEC_REN_RANGE                   27:27
+#define GPIO_F_SCR_00_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_00_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_00_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_F_SCR_00_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_F_SCR_00_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_F_SCR_00_0_SEC_OWNER_SHIFT)
+#define GPIO_F_SCR_00_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_F_SCR_00_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_F_SCR_00_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_F_SCR_00_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_F_SCR_00_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_F_SCR_00_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_00_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR7_SHIFT)
+#define GPIO_F_SCR_00_0_PR7_RANGE                       23:23
+#define GPIO_F_SCR_00_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_00_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_00_0_PR7_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_00_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR6_SHIFT)
+#define GPIO_F_SCR_00_0_PR6_RANGE                       22:22
+#define GPIO_F_SCR_00_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_00_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_00_0_PR6_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_00_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR5_SHIFT)
+#define GPIO_F_SCR_00_0_PR5_RANGE                       21:21
+#define GPIO_F_SCR_00_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_00_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_00_0_PR5_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_00_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR4_SHIFT)
+#define GPIO_F_SCR_00_0_PR4_RANGE                       20:20
+#define GPIO_F_SCR_00_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_00_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_00_0_PR4_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_00_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR3_SHIFT)
+#define GPIO_F_SCR_00_0_PR3_RANGE                       19:19
+#define GPIO_F_SCR_00_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_00_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_00_0_PR3_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_00_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR2_SHIFT)
+#define GPIO_F_SCR_00_0_PR2_RANGE                       18:18
+#define GPIO_F_SCR_00_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_00_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_00_0_PR2_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_00_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR1_SHIFT)
+#define GPIO_F_SCR_00_0_PR1_RANGE                       17:17
+#define GPIO_F_SCR_00_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_00_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_00_0_PR1_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_00_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_PR0_SHIFT)
+#define GPIO_F_SCR_00_0_PR0_RANGE                       16:16
+#define GPIO_F_SCR_00_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_00_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_00_0_PR0_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_00_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G7W_SHIFT)
+#define GPIO_F_SCR_00_0_G7W_RANGE                       15:15
+#define GPIO_F_SCR_00_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_00_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_00_0_G7W_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_00_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G6W_SHIFT)
+#define GPIO_F_SCR_00_0_G6W_RANGE                       14:14
+#define GPIO_F_SCR_00_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_00_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_00_0_G6W_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_00_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G5W_SHIFT)
+#define GPIO_F_SCR_00_0_G5W_RANGE                       13:13
+#define GPIO_F_SCR_00_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_00_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_00_0_G5W_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_00_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G4W_SHIFT)
+#define GPIO_F_SCR_00_0_G4W_RANGE                       12:12
+#define GPIO_F_SCR_00_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_00_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_00_0_G4W_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_00_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G3W_SHIFT)
+#define GPIO_F_SCR_00_0_G3W_RANGE                       11:11
+#define GPIO_F_SCR_00_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_00_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_00_0_G3W_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_00_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G2W_SHIFT)
+#define GPIO_F_SCR_00_0_G2W_RANGE                       10:10
+#define GPIO_F_SCR_00_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_00_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_00_0_G2W_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_00_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G1W_SHIFT)
+#define GPIO_F_SCR_00_0_G1W_RANGE                       9:9
+#define GPIO_F_SCR_00_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_00_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_00_0_G1W_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_00_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G0W_SHIFT)
+#define GPIO_F_SCR_00_0_G0W_RANGE                       8:8
+#define GPIO_F_SCR_00_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_00_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_00_0_G0W_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_00_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G7R_SHIFT)
+#define GPIO_F_SCR_00_0_G7R_RANGE                       7:7
+#define GPIO_F_SCR_00_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_00_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_00_0_G7R_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_00_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G6R_SHIFT)
+#define GPIO_F_SCR_00_0_G6R_RANGE                       6:6
+#define GPIO_F_SCR_00_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_00_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_00_0_G6R_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_00_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G5R_SHIFT)
+#define GPIO_F_SCR_00_0_G5R_RANGE                       5:5
+#define GPIO_F_SCR_00_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_00_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_00_0_G5R_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_00_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G4R_SHIFT)
+#define GPIO_F_SCR_00_0_G4R_RANGE                       4:4
+#define GPIO_F_SCR_00_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_00_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_00_0_G4R_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_00_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G3R_SHIFT)
+#define GPIO_F_SCR_00_0_G3R_RANGE                       3:3
+#define GPIO_F_SCR_00_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_00_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_00_0_G3R_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_00_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G2R_SHIFT)
+#define GPIO_F_SCR_00_0_G2R_RANGE                       2:2
+#define GPIO_F_SCR_00_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_00_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_00_0_G2R_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_00_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G1R_SHIFT)
+#define GPIO_F_SCR_00_0_G1R_RANGE                       1:1
+#define GPIO_F_SCR_00_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_00_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_00_0_G1R_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_00_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_00_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_00_0_G0R_SHIFT)
+#define GPIO_F_SCR_00_0_G0R_RANGE                       0:0
+#define GPIO_F_SCR_00_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_00_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_00_0_G0R_WOFFSET                     0x0
+#define GPIO_F_SCR_00_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_00_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_00_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_VM_01_0
+#define GPIO_F_VM_01_0                  MK_ADDR_CONST(0x5108)
+#define GPIO_F_VM_01_0_SECURE                   0x0
+#define GPIO_F_VM_01_0_DUAL                     0x0
+#define GPIO_F_VM_01_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_F_VM_01_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_F_VM_01_0_WORD_COUNT                       0x1
+#define GPIO_F_VM_01_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_01_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_01_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_01_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_F_VM_01_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM1_SHIFT)
+#define GPIO_F_VM_01_0_VM1_RANGE                        1:0
+#define GPIO_F_VM_01_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_F_VM_01_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_F_VM_01_0_VM1_WOFFSET                      0x0
+#define GPIO_F_VM_01_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_01_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_01_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_01_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_F_VM_01_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM2_SHIFT)
+#define GPIO_F_VM_01_0_VM2_RANGE                        3:2
+#define GPIO_F_VM_01_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_F_VM_01_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_F_VM_01_0_VM2_WOFFSET                      0x0
+#define GPIO_F_VM_01_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_01_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_01_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_01_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_F_VM_01_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM3_SHIFT)
+#define GPIO_F_VM_01_0_VM3_RANGE                        5:4
+#define GPIO_F_VM_01_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_F_VM_01_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_F_VM_01_0_VM3_WOFFSET                      0x0
+#define GPIO_F_VM_01_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_01_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_01_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_01_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_F_VM_01_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM4_SHIFT)
+#define GPIO_F_VM_01_0_VM4_RANGE                        7:6
+#define GPIO_F_VM_01_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_F_VM_01_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_F_VM_01_0_VM4_WOFFSET                      0x0
+#define GPIO_F_VM_01_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_01_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_01_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_01_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_F_VM_01_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM5_SHIFT)
+#define GPIO_F_VM_01_0_VM5_RANGE                        9:8
+#define GPIO_F_VM_01_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_F_VM_01_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_F_VM_01_0_VM5_WOFFSET                      0x0
+#define GPIO_F_VM_01_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_01_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_01_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_01_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_F_VM_01_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM6_SHIFT)
+#define GPIO_F_VM_01_0_VM6_RANGE                        11:10
+#define GPIO_F_VM_01_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_F_VM_01_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_F_VM_01_0_VM6_WOFFSET                      0x0
+#define GPIO_F_VM_01_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_01_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_01_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_01_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_F_VM_01_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM7_SHIFT)
+#define GPIO_F_VM_01_0_VM7_RANGE                        13:12
+#define GPIO_F_VM_01_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_F_VM_01_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_F_VM_01_0_VM7_WOFFSET                      0x0
+#define GPIO_F_VM_01_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_01_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_01_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_01_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_F_VM_01_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_01_0_VM8_SHIFT)
+#define GPIO_F_VM_01_0_VM8_RANGE                        15:14
+#define GPIO_F_VM_01_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_F_VM_01_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_F_VM_01_0_VM8_WOFFSET                      0x0
+#define GPIO_F_VM_01_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_01_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_01_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_01_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_SCR_01_0
+#define GPIO_F_SCR_01_0                 MK_ADDR_CONST(0x510c)
+#define GPIO_F_SCR_01_0_SECURE                  0x0
+#define GPIO_F_SCR_01_0_DUAL                    0x0
+#define GPIO_F_SCR_01_0_SCR                     0
+#define GPIO_F_SCR_01_0_SCRREG                  0
+#define GPIO_F_SCR_01_0_WORD_COUNT                      0x1
+#define GPIO_F_SCR_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_01_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_01_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_01_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_SEC_LCK_SHIFT)
+#define GPIO_F_SCR_01_0_SEC_LCK_RANGE                   29:29
+#define GPIO_F_SCR_01_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_01_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_01_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_F_SCR_01_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_01_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_SEC_WEN_SHIFT)
+#define GPIO_F_SCR_01_0_SEC_WEN_RANGE                   28:28
+#define GPIO_F_SCR_01_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_01_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_01_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_F_SCR_01_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_01_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_SEC_REN_SHIFT)
+#define GPIO_F_SCR_01_0_SEC_REN_RANGE                   27:27
+#define GPIO_F_SCR_01_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_01_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_01_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_F_SCR_01_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_F_SCR_01_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_F_SCR_01_0_SEC_OWNER_SHIFT)
+#define GPIO_F_SCR_01_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_F_SCR_01_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_F_SCR_01_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_F_SCR_01_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_F_SCR_01_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_F_SCR_01_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_01_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR7_SHIFT)
+#define GPIO_F_SCR_01_0_PR7_RANGE                       23:23
+#define GPIO_F_SCR_01_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_01_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_01_0_PR7_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_01_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR6_SHIFT)
+#define GPIO_F_SCR_01_0_PR6_RANGE                       22:22
+#define GPIO_F_SCR_01_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_01_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_01_0_PR6_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_01_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR5_SHIFT)
+#define GPIO_F_SCR_01_0_PR5_RANGE                       21:21
+#define GPIO_F_SCR_01_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_01_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_01_0_PR5_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_01_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR4_SHIFT)
+#define GPIO_F_SCR_01_0_PR4_RANGE                       20:20
+#define GPIO_F_SCR_01_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_01_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_01_0_PR4_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_01_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR3_SHIFT)
+#define GPIO_F_SCR_01_0_PR3_RANGE                       19:19
+#define GPIO_F_SCR_01_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_01_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_01_0_PR3_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_01_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR2_SHIFT)
+#define GPIO_F_SCR_01_0_PR2_RANGE                       18:18
+#define GPIO_F_SCR_01_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_01_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_01_0_PR2_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_01_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR1_SHIFT)
+#define GPIO_F_SCR_01_0_PR1_RANGE                       17:17
+#define GPIO_F_SCR_01_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_01_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_01_0_PR1_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_01_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_PR0_SHIFT)
+#define GPIO_F_SCR_01_0_PR0_RANGE                       16:16
+#define GPIO_F_SCR_01_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_01_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_01_0_PR0_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_01_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G7W_SHIFT)
+#define GPIO_F_SCR_01_0_G7W_RANGE                       15:15
+#define GPIO_F_SCR_01_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_01_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_01_0_G7W_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_01_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G6W_SHIFT)
+#define GPIO_F_SCR_01_0_G6W_RANGE                       14:14
+#define GPIO_F_SCR_01_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_01_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_01_0_G6W_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_01_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G5W_SHIFT)
+#define GPIO_F_SCR_01_0_G5W_RANGE                       13:13
+#define GPIO_F_SCR_01_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_01_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_01_0_G5W_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_01_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G4W_SHIFT)
+#define GPIO_F_SCR_01_0_G4W_RANGE                       12:12
+#define GPIO_F_SCR_01_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_01_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_01_0_G4W_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_01_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G3W_SHIFT)
+#define GPIO_F_SCR_01_0_G3W_RANGE                       11:11
+#define GPIO_F_SCR_01_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_01_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_01_0_G3W_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_01_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G2W_SHIFT)
+#define GPIO_F_SCR_01_0_G2W_RANGE                       10:10
+#define GPIO_F_SCR_01_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_01_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_01_0_G2W_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_01_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G1W_SHIFT)
+#define GPIO_F_SCR_01_0_G1W_RANGE                       9:9
+#define GPIO_F_SCR_01_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_01_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_01_0_G1W_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_01_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G0W_SHIFT)
+#define GPIO_F_SCR_01_0_G0W_RANGE                       8:8
+#define GPIO_F_SCR_01_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_01_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_01_0_G0W_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_01_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G7R_SHIFT)
+#define GPIO_F_SCR_01_0_G7R_RANGE                       7:7
+#define GPIO_F_SCR_01_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_01_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_01_0_G7R_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_01_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G6R_SHIFT)
+#define GPIO_F_SCR_01_0_G6R_RANGE                       6:6
+#define GPIO_F_SCR_01_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_01_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_01_0_G6R_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_01_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G5R_SHIFT)
+#define GPIO_F_SCR_01_0_G5R_RANGE                       5:5
+#define GPIO_F_SCR_01_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_01_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_01_0_G5R_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_01_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G4R_SHIFT)
+#define GPIO_F_SCR_01_0_G4R_RANGE                       4:4
+#define GPIO_F_SCR_01_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_01_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_01_0_G4R_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_01_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G3R_SHIFT)
+#define GPIO_F_SCR_01_0_G3R_RANGE                       3:3
+#define GPIO_F_SCR_01_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_01_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_01_0_G3R_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_01_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G2R_SHIFT)
+#define GPIO_F_SCR_01_0_G2R_RANGE                       2:2
+#define GPIO_F_SCR_01_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_01_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_01_0_G2R_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_01_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G1R_SHIFT)
+#define GPIO_F_SCR_01_0_G1R_RANGE                       1:1
+#define GPIO_F_SCR_01_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_01_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_01_0_G1R_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_01_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_01_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_01_0_G0R_SHIFT)
+#define GPIO_F_SCR_01_0_G0R_RANGE                       0:0
+#define GPIO_F_SCR_01_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_01_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_01_0_G0R_WOFFSET                     0x0
+#define GPIO_F_SCR_01_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_01_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_01_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_VM_02_0
+#define GPIO_F_VM_02_0                  MK_ADDR_CONST(0x5110)
+#define GPIO_F_VM_02_0_SECURE                   0x0
+#define GPIO_F_VM_02_0_DUAL                     0x0
+#define GPIO_F_VM_02_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_F_VM_02_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_F_VM_02_0_WORD_COUNT                       0x1
+#define GPIO_F_VM_02_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_02_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_02_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_02_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_F_VM_02_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM1_SHIFT)
+#define GPIO_F_VM_02_0_VM1_RANGE                        1:0
+#define GPIO_F_VM_02_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_F_VM_02_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_F_VM_02_0_VM1_WOFFSET                      0x0
+#define GPIO_F_VM_02_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_02_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_02_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_02_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_F_VM_02_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM2_SHIFT)
+#define GPIO_F_VM_02_0_VM2_RANGE                        3:2
+#define GPIO_F_VM_02_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_F_VM_02_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_F_VM_02_0_VM2_WOFFSET                      0x0
+#define GPIO_F_VM_02_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_02_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_02_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_02_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_F_VM_02_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM3_SHIFT)
+#define GPIO_F_VM_02_0_VM3_RANGE                        5:4
+#define GPIO_F_VM_02_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_F_VM_02_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_F_VM_02_0_VM3_WOFFSET                      0x0
+#define GPIO_F_VM_02_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_02_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_02_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_02_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_F_VM_02_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM4_SHIFT)
+#define GPIO_F_VM_02_0_VM4_RANGE                        7:6
+#define GPIO_F_VM_02_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_F_VM_02_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_F_VM_02_0_VM4_WOFFSET                      0x0
+#define GPIO_F_VM_02_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_02_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_02_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_02_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_F_VM_02_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM5_SHIFT)
+#define GPIO_F_VM_02_0_VM5_RANGE                        9:8
+#define GPIO_F_VM_02_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_F_VM_02_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_F_VM_02_0_VM5_WOFFSET                      0x0
+#define GPIO_F_VM_02_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_02_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_02_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_02_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_F_VM_02_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM6_SHIFT)
+#define GPIO_F_VM_02_0_VM6_RANGE                        11:10
+#define GPIO_F_VM_02_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_F_VM_02_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_F_VM_02_0_VM6_WOFFSET                      0x0
+#define GPIO_F_VM_02_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_02_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_02_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_02_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_F_VM_02_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM7_SHIFT)
+#define GPIO_F_VM_02_0_VM7_RANGE                        13:12
+#define GPIO_F_VM_02_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_F_VM_02_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_F_VM_02_0_VM7_WOFFSET                      0x0
+#define GPIO_F_VM_02_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_02_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_02_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_02_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_F_VM_02_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_02_0_VM8_SHIFT)
+#define GPIO_F_VM_02_0_VM8_RANGE                        15:14
+#define GPIO_F_VM_02_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_F_VM_02_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_F_VM_02_0_VM8_WOFFSET                      0x0
+#define GPIO_F_VM_02_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_02_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_02_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_02_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_SCR_02_0
+#define GPIO_F_SCR_02_0                 MK_ADDR_CONST(0x5114)
+#define GPIO_F_SCR_02_0_SECURE                  0x0
+#define GPIO_F_SCR_02_0_DUAL                    0x0
+#define GPIO_F_SCR_02_0_SCR                     0
+#define GPIO_F_SCR_02_0_SCRREG                  0
+#define GPIO_F_SCR_02_0_WORD_COUNT                      0x1
+#define GPIO_F_SCR_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_02_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_02_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_02_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_SEC_LCK_SHIFT)
+#define GPIO_F_SCR_02_0_SEC_LCK_RANGE                   29:29
+#define GPIO_F_SCR_02_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_02_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_02_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_F_SCR_02_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_02_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_SEC_WEN_SHIFT)
+#define GPIO_F_SCR_02_0_SEC_WEN_RANGE                   28:28
+#define GPIO_F_SCR_02_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_02_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_02_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_F_SCR_02_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_02_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_SEC_REN_SHIFT)
+#define GPIO_F_SCR_02_0_SEC_REN_RANGE                   27:27
+#define GPIO_F_SCR_02_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_02_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_02_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_F_SCR_02_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_F_SCR_02_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_F_SCR_02_0_SEC_OWNER_SHIFT)
+#define GPIO_F_SCR_02_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_F_SCR_02_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_F_SCR_02_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_F_SCR_02_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_F_SCR_02_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_F_SCR_02_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_02_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR7_SHIFT)
+#define GPIO_F_SCR_02_0_PR7_RANGE                       23:23
+#define GPIO_F_SCR_02_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_02_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_02_0_PR7_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_02_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR6_SHIFT)
+#define GPIO_F_SCR_02_0_PR6_RANGE                       22:22
+#define GPIO_F_SCR_02_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_02_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_02_0_PR6_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_02_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR5_SHIFT)
+#define GPIO_F_SCR_02_0_PR5_RANGE                       21:21
+#define GPIO_F_SCR_02_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_02_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_02_0_PR5_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_02_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR4_SHIFT)
+#define GPIO_F_SCR_02_0_PR4_RANGE                       20:20
+#define GPIO_F_SCR_02_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_02_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_02_0_PR4_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_02_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR3_SHIFT)
+#define GPIO_F_SCR_02_0_PR3_RANGE                       19:19
+#define GPIO_F_SCR_02_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_02_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_02_0_PR3_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_02_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR2_SHIFT)
+#define GPIO_F_SCR_02_0_PR2_RANGE                       18:18
+#define GPIO_F_SCR_02_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_02_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_02_0_PR2_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_02_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR1_SHIFT)
+#define GPIO_F_SCR_02_0_PR1_RANGE                       17:17
+#define GPIO_F_SCR_02_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_02_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_02_0_PR1_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_02_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_PR0_SHIFT)
+#define GPIO_F_SCR_02_0_PR0_RANGE                       16:16
+#define GPIO_F_SCR_02_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_02_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_02_0_PR0_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_02_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G7W_SHIFT)
+#define GPIO_F_SCR_02_0_G7W_RANGE                       15:15
+#define GPIO_F_SCR_02_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_02_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_02_0_G7W_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_02_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G6W_SHIFT)
+#define GPIO_F_SCR_02_0_G6W_RANGE                       14:14
+#define GPIO_F_SCR_02_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_02_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_02_0_G6W_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_02_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G5W_SHIFT)
+#define GPIO_F_SCR_02_0_G5W_RANGE                       13:13
+#define GPIO_F_SCR_02_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_02_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_02_0_G5W_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_02_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G4W_SHIFT)
+#define GPIO_F_SCR_02_0_G4W_RANGE                       12:12
+#define GPIO_F_SCR_02_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_02_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_02_0_G4W_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_02_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G3W_SHIFT)
+#define GPIO_F_SCR_02_0_G3W_RANGE                       11:11
+#define GPIO_F_SCR_02_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_02_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_02_0_G3W_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_02_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G2W_SHIFT)
+#define GPIO_F_SCR_02_0_G2W_RANGE                       10:10
+#define GPIO_F_SCR_02_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_02_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_02_0_G2W_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_02_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G1W_SHIFT)
+#define GPIO_F_SCR_02_0_G1W_RANGE                       9:9
+#define GPIO_F_SCR_02_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_02_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_02_0_G1W_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_02_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G0W_SHIFT)
+#define GPIO_F_SCR_02_0_G0W_RANGE                       8:8
+#define GPIO_F_SCR_02_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_02_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_02_0_G0W_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_02_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G7R_SHIFT)
+#define GPIO_F_SCR_02_0_G7R_RANGE                       7:7
+#define GPIO_F_SCR_02_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_02_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_02_0_G7R_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_02_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G6R_SHIFT)
+#define GPIO_F_SCR_02_0_G6R_RANGE                       6:6
+#define GPIO_F_SCR_02_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_02_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_02_0_G6R_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_02_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G5R_SHIFT)
+#define GPIO_F_SCR_02_0_G5R_RANGE                       5:5
+#define GPIO_F_SCR_02_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_02_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_02_0_G5R_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_02_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G4R_SHIFT)
+#define GPIO_F_SCR_02_0_G4R_RANGE                       4:4
+#define GPIO_F_SCR_02_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_02_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_02_0_G4R_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_02_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G3R_SHIFT)
+#define GPIO_F_SCR_02_0_G3R_RANGE                       3:3
+#define GPIO_F_SCR_02_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_02_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_02_0_G3R_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_02_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G2R_SHIFT)
+#define GPIO_F_SCR_02_0_G2R_RANGE                       2:2
+#define GPIO_F_SCR_02_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_02_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_02_0_G2R_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_02_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G1R_SHIFT)
+#define GPIO_F_SCR_02_0_G1R_RANGE                       1:1
+#define GPIO_F_SCR_02_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_02_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_02_0_G1R_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_02_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_02_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_02_0_G0R_SHIFT)
+#define GPIO_F_SCR_02_0_G0R_RANGE                       0:0
+#define GPIO_F_SCR_02_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_02_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_02_0_G0R_WOFFSET                     0x0
+#define GPIO_F_SCR_02_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_02_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_02_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_VM_03_0
+#define GPIO_F_VM_03_0                  MK_ADDR_CONST(0x5118)
+#define GPIO_F_VM_03_0_SECURE                   0x0
+#define GPIO_F_VM_03_0_DUAL                     0x0
+#define GPIO_F_VM_03_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_F_VM_03_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_F_VM_03_0_WORD_COUNT                       0x1
+#define GPIO_F_VM_03_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_03_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_03_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_03_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_F_VM_03_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM1_SHIFT)
+#define GPIO_F_VM_03_0_VM1_RANGE                        1:0
+#define GPIO_F_VM_03_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_F_VM_03_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_F_VM_03_0_VM1_WOFFSET                      0x0
+#define GPIO_F_VM_03_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_03_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_03_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_03_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_F_VM_03_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM2_SHIFT)
+#define GPIO_F_VM_03_0_VM2_RANGE                        3:2
+#define GPIO_F_VM_03_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_F_VM_03_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_F_VM_03_0_VM2_WOFFSET                      0x0
+#define GPIO_F_VM_03_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_03_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_03_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_03_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_F_VM_03_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM3_SHIFT)
+#define GPIO_F_VM_03_0_VM3_RANGE                        5:4
+#define GPIO_F_VM_03_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_F_VM_03_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_F_VM_03_0_VM3_WOFFSET                      0x0
+#define GPIO_F_VM_03_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_03_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_03_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_03_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_F_VM_03_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM4_SHIFT)
+#define GPIO_F_VM_03_0_VM4_RANGE                        7:6
+#define GPIO_F_VM_03_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_F_VM_03_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_F_VM_03_0_VM4_WOFFSET                      0x0
+#define GPIO_F_VM_03_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_03_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_03_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_03_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_F_VM_03_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM5_SHIFT)
+#define GPIO_F_VM_03_0_VM5_RANGE                        9:8
+#define GPIO_F_VM_03_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_F_VM_03_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_F_VM_03_0_VM5_WOFFSET                      0x0
+#define GPIO_F_VM_03_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_03_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_03_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_03_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_F_VM_03_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM6_SHIFT)
+#define GPIO_F_VM_03_0_VM6_RANGE                        11:10
+#define GPIO_F_VM_03_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_F_VM_03_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_F_VM_03_0_VM6_WOFFSET                      0x0
+#define GPIO_F_VM_03_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_03_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_03_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_03_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_F_VM_03_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM7_SHIFT)
+#define GPIO_F_VM_03_0_VM7_RANGE                        13:12
+#define GPIO_F_VM_03_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_F_VM_03_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_F_VM_03_0_VM7_WOFFSET                      0x0
+#define GPIO_F_VM_03_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_03_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_03_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_03_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_F_VM_03_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_03_0_VM8_SHIFT)
+#define GPIO_F_VM_03_0_VM8_RANGE                        15:14
+#define GPIO_F_VM_03_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_F_VM_03_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_F_VM_03_0_VM8_WOFFSET                      0x0
+#define GPIO_F_VM_03_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_03_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_03_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_03_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_SCR_03_0
+#define GPIO_F_SCR_03_0                 MK_ADDR_CONST(0x511c)
+#define GPIO_F_SCR_03_0_SECURE                  0x0
+#define GPIO_F_SCR_03_0_DUAL                    0x0
+#define GPIO_F_SCR_03_0_SCR                     0
+#define GPIO_F_SCR_03_0_SCRREG                  0
+#define GPIO_F_SCR_03_0_WORD_COUNT                      0x1
+#define GPIO_F_SCR_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_03_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_03_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_03_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_SEC_LCK_SHIFT)
+#define GPIO_F_SCR_03_0_SEC_LCK_RANGE                   29:29
+#define GPIO_F_SCR_03_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_03_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_03_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_F_SCR_03_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_03_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_SEC_WEN_SHIFT)
+#define GPIO_F_SCR_03_0_SEC_WEN_RANGE                   28:28
+#define GPIO_F_SCR_03_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_03_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_03_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_F_SCR_03_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_03_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_SEC_REN_SHIFT)
+#define GPIO_F_SCR_03_0_SEC_REN_RANGE                   27:27
+#define GPIO_F_SCR_03_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_03_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_03_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_F_SCR_03_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_F_SCR_03_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_F_SCR_03_0_SEC_OWNER_SHIFT)
+#define GPIO_F_SCR_03_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_F_SCR_03_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_F_SCR_03_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_F_SCR_03_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_F_SCR_03_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_F_SCR_03_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_03_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR7_SHIFT)
+#define GPIO_F_SCR_03_0_PR7_RANGE                       23:23
+#define GPIO_F_SCR_03_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_03_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_03_0_PR7_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_03_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR6_SHIFT)
+#define GPIO_F_SCR_03_0_PR6_RANGE                       22:22
+#define GPIO_F_SCR_03_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_03_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_03_0_PR6_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_03_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR5_SHIFT)
+#define GPIO_F_SCR_03_0_PR5_RANGE                       21:21
+#define GPIO_F_SCR_03_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_03_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_03_0_PR5_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_03_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR4_SHIFT)
+#define GPIO_F_SCR_03_0_PR4_RANGE                       20:20
+#define GPIO_F_SCR_03_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_03_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_03_0_PR4_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_03_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR3_SHIFT)
+#define GPIO_F_SCR_03_0_PR3_RANGE                       19:19
+#define GPIO_F_SCR_03_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_03_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_03_0_PR3_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_03_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR2_SHIFT)
+#define GPIO_F_SCR_03_0_PR2_RANGE                       18:18
+#define GPIO_F_SCR_03_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_03_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_03_0_PR2_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_03_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR1_SHIFT)
+#define GPIO_F_SCR_03_0_PR1_RANGE                       17:17
+#define GPIO_F_SCR_03_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_03_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_03_0_PR1_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_03_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_PR0_SHIFT)
+#define GPIO_F_SCR_03_0_PR0_RANGE                       16:16
+#define GPIO_F_SCR_03_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_03_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_03_0_PR0_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_03_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G7W_SHIFT)
+#define GPIO_F_SCR_03_0_G7W_RANGE                       15:15
+#define GPIO_F_SCR_03_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_03_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_03_0_G7W_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_03_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G6W_SHIFT)
+#define GPIO_F_SCR_03_0_G6W_RANGE                       14:14
+#define GPIO_F_SCR_03_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_03_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_03_0_G6W_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_03_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G5W_SHIFT)
+#define GPIO_F_SCR_03_0_G5W_RANGE                       13:13
+#define GPIO_F_SCR_03_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_03_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_03_0_G5W_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_03_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G4W_SHIFT)
+#define GPIO_F_SCR_03_0_G4W_RANGE                       12:12
+#define GPIO_F_SCR_03_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_03_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_03_0_G4W_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_03_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G3W_SHIFT)
+#define GPIO_F_SCR_03_0_G3W_RANGE                       11:11
+#define GPIO_F_SCR_03_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_03_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_03_0_G3W_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_03_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G2W_SHIFT)
+#define GPIO_F_SCR_03_0_G2W_RANGE                       10:10
+#define GPIO_F_SCR_03_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_03_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_03_0_G2W_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_03_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G1W_SHIFT)
+#define GPIO_F_SCR_03_0_G1W_RANGE                       9:9
+#define GPIO_F_SCR_03_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_03_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_03_0_G1W_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_03_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G0W_SHIFT)
+#define GPIO_F_SCR_03_0_G0W_RANGE                       8:8
+#define GPIO_F_SCR_03_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_03_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_03_0_G0W_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_03_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G7R_SHIFT)
+#define GPIO_F_SCR_03_0_G7R_RANGE                       7:7
+#define GPIO_F_SCR_03_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_03_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_03_0_G7R_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_03_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G6R_SHIFT)
+#define GPIO_F_SCR_03_0_G6R_RANGE                       6:6
+#define GPIO_F_SCR_03_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_03_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_03_0_G6R_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_03_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G5R_SHIFT)
+#define GPIO_F_SCR_03_0_G5R_RANGE                       5:5
+#define GPIO_F_SCR_03_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_03_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_03_0_G5R_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_03_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G4R_SHIFT)
+#define GPIO_F_SCR_03_0_G4R_RANGE                       4:4
+#define GPIO_F_SCR_03_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_03_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_03_0_G4R_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_03_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G3R_SHIFT)
+#define GPIO_F_SCR_03_0_G3R_RANGE                       3:3
+#define GPIO_F_SCR_03_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_03_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_03_0_G3R_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_03_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G2R_SHIFT)
+#define GPIO_F_SCR_03_0_G2R_RANGE                       2:2
+#define GPIO_F_SCR_03_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_03_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_03_0_G2R_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_03_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G1R_SHIFT)
+#define GPIO_F_SCR_03_0_G1R_RANGE                       1:1
+#define GPIO_F_SCR_03_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_03_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_03_0_G1R_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_03_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_03_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_03_0_G0R_SHIFT)
+#define GPIO_F_SCR_03_0_G0R_RANGE                       0:0
+#define GPIO_F_SCR_03_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_03_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_03_0_G0R_WOFFSET                     0x0
+#define GPIO_F_SCR_03_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_03_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_03_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_VM_04_0
+#define GPIO_F_VM_04_0                  MK_ADDR_CONST(0x5120)
+#define GPIO_F_VM_04_0_SECURE                   0x0
+#define GPIO_F_VM_04_0_DUAL                     0x0
+#define GPIO_F_VM_04_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_F_VM_04_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_F_VM_04_0_WORD_COUNT                       0x1
+#define GPIO_F_VM_04_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_04_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_04_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_04_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_F_VM_04_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM1_SHIFT)
+#define GPIO_F_VM_04_0_VM1_RANGE                        1:0
+#define GPIO_F_VM_04_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_F_VM_04_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_F_VM_04_0_VM1_WOFFSET                      0x0
+#define GPIO_F_VM_04_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_04_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_04_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_04_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_F_VM_04_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM2_SHIFT)
+#define GPIO_F_VM_04_0_VM2_RANGE                        3:2
+#define GPIO_F_VM_04_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_F_VM_04_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_F_VM_04_0_VM2_WOFFSET                      0x0
+#define GPIO_F_VM_04_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_04_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_04_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_04_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_F_VM_04_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM3_SHIFT)
+#define GPIO_F_VM_04_0_VM3_RANGE                        5:4
+#define GPIO_F_VM_04_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_F_VM_04_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_F_VM_04_0_VM3_WOFFSET                      0x0
+#define GPIO_F_VM_04_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_04_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_04_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_04_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_F_VM_04_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM4_SHIFT)
+#define GPIO_F_VM_04_0_VM4_RANGE                        7:6
+#define GPIO_F_VM_04_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_F_VM_04_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_F_VM_04_0_VM4_WOFFSET                      0x0
+#define GPIO_F_VM_04_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_04_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_04_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_04_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_F_VM_04_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM5_SHIFT)
+#define GPIO_F_VM_04_0_VM5_RANGE                        9:8
+#define GPIO_F_VM_04_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_F_VM_04_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_F_VM_04_0_VM5_WOFFSET                      0x0
+#define GPIO_F_VM_04_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_04_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_04_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_04_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_F_VM_04_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM6_SHIFT)
+#define GPIO_F_VM_04_0_VM6_RANGE                        11:10
+#define GPIO_F_VM_04_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_F_VM_04_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_F_VM_04_0_VM6_WOFFSET                      0x0
+#define GPIO_F_VM_04_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_04_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_04_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_04_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_F_VM_04_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM7_SHIFT)
+#define GPIO_F_VM_04_0_VM7_RANGE                        13:12
+#define GPIO_F_VM_04_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_F_VM_04_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_F_VM_04_0_VM7_WOFFSET                      0x0
+#define GPIO_F_VM_04_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_04_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_04_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_04_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_F_VM_04_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_04_0_VM8_SHIFT)
+#define GPIO_F_VM_04_0_VM8_RANGE                        15:14
+#define GPIO_F_VM_04_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_F_VM_04_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_F_VM_04_0_VM8_WOFFSET                      0x0
+#define GPIO_F_VM_04_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_04_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_04_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_04_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_SCR_04_0
+#define GPIO_F_SCR_04_0                 MK_ADDR_CONST(0x5124)
+#define GPIO_F_SCR_04_0_SECURE                  0x0
+#define GPIO_F_SCR_04_0_DUAL                    0x0
+#define GPIO_F_SCR_04_0_SCR                     0
+#define GPIO_F_SCR_04_0_SCRREG                  0
+#define GPIO_F_SCR_04_0_WORD_COUNT                      0x1
+#define GPIO_F_SCR_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_04_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_04_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_04_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_SEC_LCK_SHIFT)
+#define GPIO_F_SCR_04_0_SEC_LCK_RANGE                   29:29
+#define GPIO_F_SCR_04_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_04_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_04_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_F_SCR_04_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_04_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_SEC_WEN_SHIFT)
+#define GPIO_F_SCR_04_0_SEC_WEN_RANGE                   28:28
+#define GPIO_F_SCR_04_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_04_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_04_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_F_SCR_04_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_04_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_SEC_REN_SHIFT)
+#define GPIO_F_SCR_04_0_SEC_REN_RANGE                   27:27
+#define GPIO_F_SCR_04_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_04_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_04_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_F_SCR_04_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_F_SCR_04_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_F_SCR_04_0_SEC_OWNER_SHIFT)
+#define GPIO_F_SCR_04_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_F_SCR_04_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_F_SCR_04_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_F_SCR_04_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_F_SCR_04_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_F_SCR_04_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_04_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR7_SHIFT)
+#define GPIO_F_SCR_04_0_PR7_RANGE                       23:23
+#define GPIO_F_SCR_04_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_04_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_04_0_PR7_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_04_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR6_SHIFT)
+#define GPIO_F_SCR_04_0_PR6_RANGE                       22:22
+#define GPIO_F_SCR_04_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_04_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_04_0_PR6_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_04_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR5_SHIFT)
+#define GPIO_F_SCR_04_0_PR5_RANGE                       21:21
+#define GPIO_F_SCR_04_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_04_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_04_0_PR5_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_04_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR4_SHIFT)
+#define GPIO_F_SCR_04_0_PR4_RANGE                       20:20
+#define GPIO_F_SCR_04_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_04_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_04_0_PR4_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_04_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR3_SHIFT)
+#define GPIO_F_SCR_04_0_PR3_RANGE                       19:19
+#define GPIO_F_SCR_04_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_04_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_04_0_PR3_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_04_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR2_SHIFT)
+#define GPIO_F_SCR_04_0_PR2_RANGE                       18:18
+#define GPIO_F_SCR_04_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_04_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_04_0_PR2_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_04_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR1_SHIFT)
+#define GPIO_F_SCR_04_0_PR1_RANGE                       17:17
+#define GPIO_F_SCR_04_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_04_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_04_0_PR1_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_04_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_PR0_SHIFT)
+#define GPIO_F_SCR_04_0_PR0_RANGE                       16:16
+#define GPIO_F_SCR_04_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_04_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_04_0_PR0_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_04_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G7W_SHIFT)
+#define GPIO_F_SCR_04_0_G7W_RANGE                       15:15
+#define GPIO_F_SCR_04_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_04_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_04_0_G7W_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_04_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G6W_SHIFT)
+#define GPIO_F_SCR_04_0_G6W_RANGE                       14:14
+#define GPIO_F_SCR_04_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_04_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_04_0_G6W_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_04_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G5W_SHIFT)
+#define GPIO_F_SCR_04_0_G5W_RANGE                       13:13
+#define GPIO_F_SCR_04_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_04_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_04_0_G5W_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_04_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G4W_SHIFT)
+#define GPIO_F_SCR_04_0_G4W_RANGE                       12:12
+#define GPIO_F_SCR_04_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_04_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_04_0_G4W_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_04_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G3W_SHIFT)
+#define GPIO_F_SCR_04_0_G3W_RANGE                       11:11
+#define GPIO_F_SCR_04_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_04_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_04_0_G3W_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_04_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G2W_SHIFT)
+#define GPIO_F_SCR_04_0_G2W_RANGE                       10:10
+#define GPIO_F_SCR_04_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_04_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_04_0_G2W_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_04_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G1W_SHIFT)
+#define GPIO_F_SCR_04_0_G1W_RANGE                       9:9
+#define GPIO_F_SCR_04_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_04_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_04_0_G1W_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_04_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G0W_SHIFT)
+#define GPIO_F_SCR_04_0_G0W_RANGE                       8:8
+#define GPIO_F_SCR_04_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_04_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_04_0_G0W_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_04_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G7R_SHIFT)
+#define GPIO_F_SCR_04_0_G7R_RANGE                       7:7
+#define GPIO_F_SCR_04_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_04_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_04_0_G7R_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_04_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G6R_SHIFT)
+#define GPIO_F_SCR_04_0_G6R_RANGE                       6:6
+#define GPIO_F_SCR_04_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_04_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_04_0_G6R_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_04_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G5R_SHIFT)
+#define GPIO_F_SCR_04_0_G5R_RANGE                       5:5
+#define GPIO_F_SCR_04_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_04_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_04_0_G5R_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_04_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G4R_SHIFT)
+#define GPIO_F_SCR_04_0_G4R_RANGE                       4:4
+#define GPIO_F_SCR_04_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_04_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_04_0_G4R_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_04_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G3R_SHIFT)
+#define GPIO_F_SCR_04_0_G3R_RANGE                       3:3
+#define GPIO_F_SCR_04_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_04_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_04_0_G3R_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_04_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G2R_SHIFT)
+#define GPIO_F_SCR_04_0_G2R_RANGE                       2:2
+#define GPIO_F_SCR_04_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_04_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_04_0_G2R_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_04_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G1R_SHIFT)
+#define GPIO_F_SCR_04_0_G1R_RANGE                       1:1
+#define GPIO_F_SCR_04_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_04_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_04_0_G1R_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_04_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_04_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_04_0_G0R_SHIFT)
+#define GPIO_F_SCR_04_0_G0R_RANGE                       0:0
+#define GPIO_F_SCR_04_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_04_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_04_0_G0R_WOFFSET                     0x0
+#define GPIO_F_SCR_04_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_04_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_04_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_VM_05_0
+#define GPIO_F_VM_05_0                  MK_ADDR_CONST(0x5128)
+#define GPIO_F_VM_05_0_SECURE                   0x0
+#define GPIO_F_VM_05_0_DUAL                     0x0
+#define GPIO_F_VM_05_0_SCR                      GPIO_CTL5_VM_SCR_0
+#define GPIO_F_VM_05_0_SCRREG                   GPIO_CTL5_VM_SCR_0
+#define GPIO_F_VM_05_0_WORD_COUNT                       0x1
+#define GPIO_F_VM_05_0_RESET_VAL                        MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_05_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_05_0_WRITE_MASK                       MK_MASK_CONST(0xffff)
+#define GPIO_F_VM_05_0_VM1_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_F_VM_05_0_VM1_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM1_SHIFT)
+#define GPIO_F_VM_05_0_VM1_RANGE                        1:0
+#define GPIO_F_VM_05_0_VM1_MSB                  MK_SHIFT_CONST(1)
+#define GPIO_F_VM_05_0_VM1_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_F_VM_05_0_VM1_WOFFSET                      0x0
+#define GPIO_F_VM_05_0_VM1_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_05_0_VM1_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_05_0_VM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_05_0_VM2_SHIFT                        MK_SHIFT_CONST(2)
+#define GPIO_F_VM_05_0_VM2_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM2_SHIFT)
+#define GPIO_F_VM_05_0_VM2_RANGE                        3:2
+#define GPIO_F_VM_05_0_VM2_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_F_VM_05_0_VM2_LSB                  MK_SHIFT_CONST(2)
+#define GPIO_F_VM_05_0_VM2_WOFFSET                      0x0
+#define GPIO_F_VM_05_0_VM2_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_05_0_VM2_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_05_0_VM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_05_0_VM3_SHIFT                        MK_SHIFT_CONST(4)
+#define GPIO_F_VM_05_0_VM3_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM3_SHIFT)
+#define GPIO_F_VM_05_0_VM3_RANGE                        5:4
+#define GPIO_F_VM_05_0_VM3_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_F_VM_05_0_VM3_LSB                  MK_SHIFT_CONST(4)
+#define GPIO_F_VM_05_0_VM3_WOFFSET                      0x0
+#define GPIO_F_VM_05_0_VM3_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_05_0_VM3_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_05_0_VM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_05_0_VM4_SHIFT                        MK_SHIFT_CONST(6)
+#define GPIO_F_VM_05_0_VM4_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM4_SHIFT)
+#define GPIO_F_VM_05_0_VM4_RANGE                        7:6
+#define GPIO_F_VM_05_0_VM4_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_F_VM_05_0_VM4_LSB                  MK_SHIFT_CONST(6)
+#define GPIO_F_VM_05_0_VM4_WOFFSET                      0x0
+#define GPIO_F_VM_05_0_VM4_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_05_0_VM4_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_05_0_VM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_05_0_VM5_SHIFT                        MK_SHIFT_CONST(8)
+#define GPIO_F_VM_05_0_VM5_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM5_SHIFT)
+#define GPIO_F_VM_05_0_VM5_RANGE                        9:8
+#define GPIO_F_VM_05_0_VM5_MSB                  MK_SHIFT_CONST(9)
+#define GPIO_F_VM_05_0_VM5_LSB                  MK_SHIFT_CONST(8)
+#define GPIO_F_VM_05_0_VM5_WOFFSET                      0x0
+#define GPIO_F_VM_05_0_VM5_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_05_0_VM5_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_05_0_VM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_05_0_VM6_SHIFT                        MK_SHIFT_CONST(10)
+#define GPIO_F_VM_05_0_VM6_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM6_SHIFT)
+#define GPIO_F_VM_05_0_VM6_RANGE                        11:10
+#define GPIO_F_VM_05_0_VM6_MSB                  MK_SHIFT_CONST(11)
+#define GPIO_F_VM_05_0_VM6_LSB                  MK_SHIFT_CONST(10)
+#define GPIO_F_VM_05_0_VM6_WOFFSET                      0x0
+#define GPIO_F_VM_05_0_VM6_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_05_0_VM6_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_05_0_VM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_05_0_VM7_SHIFT                        MK_SHIFT_CONST(12)
+#define GPIO_F_VM_05_0_VM7_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM7_SHIFT)
+#define GPIO_F_VM_05_0_VM7_RANGE                        13:12
+#define GPIO_F_VM_05_0_VM7_MSB                  MK_SHIFT_CONST(13)
+#define GPIO_F_VM_05_0_VM7_LSB                  MK_SHIFT_CONST(12)
+#define GPIO_F_VM_05_0_VM7_WOFFSET                      0x0
+#define GPIO_F_VM_05_0_VM7_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_05_0_VM7_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_05_0_VM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_F_VM_05_0_VM8_SHIFT                        MK_SHIFT_CONST(14)
+#define GPIO_F_VM_05_0_VM8_FIELD                        MK_FIELD_CONST(0x3, GPIO_F_VM_05_0_VM8_SHIFT)
+#define GPIO_F_VM_05_0_VM8_RANGE                        15:14
+#define GPIO_F_VM_05_0_VM8_MSB                  MK_SHIFT_CONST(15)
+#define GPIO_F_VM_05_0_VM8_LSB                  MK_SHIFT_CONST(14)
+#define GPIO_F_VM_05_0_VM8_WOFFSET                      0x0
+#define GPIO_F_VM_05_0_VM8_DEFAULT                      MK_MASK_CONST(0x3)
+#define GPIO_F_VM_05_0_VM8_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define GPIO_F_VM_05_0_VM8_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM8_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM8_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_VM_05_0_VM8_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_SCR_05_0
+#define GPIO_F_SCR_05_0                 MK_ADDR_CONST(0x512c)
+#define GPIO_F_SCR_05_0_SECURE                  0x0
+#define GPIO_F_SCR_05_0_DUAL                    0x0
+#define GPIO_F_SCR_05_0_SCR                     0
+#define GPIO_F_SCR_05_0_SCRREG                  0
+#define GPIO_F_SCR_05_0_WORD_COUNT                      0x1
+#define GPIO_F_SCR_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_05_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_F_SCR_05_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_05_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_SEC_LCK_SHIFT)
+#define GPIO_F_SCR_05_0_SEC_LCK_RANGE                   29:29
+#define GPIO_F_SCR_05_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_05_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_F_SCR_05_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_F_SCR_05_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_05_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_SEC_WEN_SHIFT)
+#define GPIO_F_SCR_05_0_SEC_WEN_RANGE                   28:28
+#define GPIO_F_SCR_05_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_05_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_F_SCR_05_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_F_SCR_05_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_05_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_SEC_REN_SHIFT)
+#define GPIO_F_SCR_05_0_SEC_REN_RANGE                   27:27
+#define GPIO_F_SCR_05_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_05_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_F_SCR_05_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_F_SCR_05_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_F_SCR_05_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_F_SCR_05_0_SEC_OWNER_SHIFT)
+#define GPIO_F_SCR_05_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_F_SCR_05_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_F_SCR_05_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_F_SCR_05_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_F_SCR_05_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_F_SCR_05_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_05_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR7_SHIFT)
+#define GPIO_F_SCR_05_0_PR7_RANGE                       23:23
+#define GPIO_F_SCR_05_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_05_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_F_SCR_05_0_PR7_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_05_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR6_SHIFT)
+#define GPIO_F_SCR_05_0_PR6_RANGE                       22:22
+#define GPIO_F_SCR_05_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_05_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_F_SCR_05_0_PR6_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_05_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR5_SHIFT)
+#define GPIO_F_SCR_05_0_PR5_RANGE                       21:21
+#define GPIO_F_SCR_05_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_05_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_F_SCR_05_0_PR5_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_05_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR4_SHIFT)
+#define GPIO_F_SCR_05_0_PR4_RANGE                       20:20
+#define GPIO_F_SCR_05_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_05_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_F_SCR_05_0_PR4_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_05_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR3_SHIFT)
+#define GPIO_F_SCR_05_0_PR3_RANGE                       19:19
+#define GPIO_F_SCR_05_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_05_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_F_SCR_05_0_PR3_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_05_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR2_SHIFT)
+#define GPIO_F_SCR_05_0_PR2_RANGE                       18:18
+#define GPIO_F_SCR_05_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_05_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_F_SCR_05_0_PR2_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_05_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR1_SHIFT)
+#define GPIO_F_SCR_05_0_PR1_RANGE                       17:17
+#define GPIO_F_SCR_05_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_05_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_F_SCR_05_0_PR1_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_05_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_PR0_SHIFT)
+#define GPIO_F_SCR_05_0_PR0_RANGE                       16:16
+#define GPIO_F_SCR_05_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_05_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_F_SCR_05_0_PR0_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_05_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G7W_SHIFT)
+#define GPIO_F_SCR_05_0_G7W_RANGE                       15:15
+#define GPIO_F_SCR_05_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_05_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_F_SCR_05_0_G7W_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_05_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G6W_SHIFT)
+#define GPIO_F_SCR_05_0_G6W_RANGE                       14:14
+#define GPIO_F_SCR_05_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_05_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_F_SCR_05_0_G6W_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_05_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G5W_SHIFT)
+#define GPIO_F_SCR_05_0_G5W_RANGE                       13:13
+#define GPIO_F_SCR_05_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_05_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_F_SCR_05_0_G5W_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_05_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G4W_SHIFT)
+#define GPIO_F_SCR_05_0_G4W_RANGE                       12:12
+#define GPIO_F_SCR_05_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_05_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_F_SCR_05_0_G4W_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_05_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G3W_SHIFT)
+#define GPIO_F_SCR_05_0_G3W_RANGE                       11:11
+#define GPIO_F_SCR_05_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_05_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_F_SCR_05_0_G3W_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_05_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G2W_SHIFT)
+#define GPIO_F_SCR_05_0_G2W_RANGE                       10:10
+#define GPIO_F_SCR_05_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_05_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_F_SCR_05_0_G2W_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_05_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G1W_SHIFT)
+#define GPIO_F_SCR_05_0_G1W_RANGE                       9:9
+#define GPIO_F_SCR_05_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_05_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_F_SCR_05_0_G1W_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_05_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G0W_SHIFT)
+#define GPIO_F_SCR_05_0_G0W_RANGE                       8:8
+#define GPIO_F_SCR_05_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_05_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_F_SCR_05_0_G0W_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_05_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G7R_SHIFT)
+#define GPIO_F_SCR_05_0_G7R_RANGE                       7:7
+#define GPIO_F_SCR_05_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_05_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_F_SCR_05_0_G7R_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_05_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G6R_SHIFT)
+#define GPIO_F_SCR_05_0_G6R_RANGE                       6:6
+#define GPIO_F_SCR_05_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_05_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_F_SCR_05_0_G6R_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_05_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G5R_SHIFT)
+#define GPIO_F_SCR_05_0_G5R_RANGE                       5:5
+#define GPIO_F_SCR_05_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_05_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_SCR_05_0_G5R_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_05_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G4R_SHIFT)
+#define GPIO_F_SCR_05_0_G4R_RANGE                       4:4
+#define GPIO_F_SCR_05_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_05_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_F_SCR_05_0_G4R_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_05_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G3R_SHIFT)
+#define GPIO_F_SCR_05_0_G3R_RANGE                       3:3
+#define GPIO_F_SCR_05_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_05_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_F_SCR_05_0_G3R_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_05_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G2R_SHIFT)
+#define GPIO_F_SCR_05_0_G2R_RANGE                       2:2
+#define GPIO_F_SCR_05_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_05_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_F_SCR_05_0_G2R_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_05_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G1R_SHIFT)
+#define GPIO_F_SCR_05_0_G1R_RANGE                       1:1
+#define GPIO_F_SCR_05_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_05_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_F_SCR_05_0_G1R_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_F_SCR_05_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_05_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_SCR_05_0_G0R_SHIFT)
+#define GPIO_F_SCR_05_0_G0R_RANGE                       0:0
+#define GPIO_F_SCR_05_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_05_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_SCR_05_0_G0R_WOFFSET                     0x0
+#define GPIO_F_SCR_05_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_SCR_05_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_F_SCR_05_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x5130
+
+// Reserved address 0x5134
+
+// Reserved address 0x5138
+
+// Reserved address 0x513c
+
+// Register GPIO_CTL5_VM_SCR_0
+#define GPIO_CTL5_VM_SCR_0                      MK_ADDR_CONST(0x5800)
+#define GPIO_CTL5_VM_SCR_0_SECURE                       0x0
+#define GPIO_CTL5_VM_SCR_0_DUAL                         0x0
+#define GPIO_CTL5_VM_SCR_0_SCR                  0
+#define GPIO_CTL5_VM_SCR_0_SCRREG                       0
+#define GPIO_CTL5_VM_SCR_0_WORD_COUNT                   0x1
+#define GPIO_CTL5_VM_SCR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_RESET_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL5_VM_SCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_READ_MASK                    MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL5_VM_SCR_0_WRITE_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL5_VM_SCR_0_SEC_LCK_SHIFT                        MK_SHIFT_CONST(29)
+#define GPIO_CTL5_VM_SCR_0_SEC_LCK_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_SEC_LCK_RANGE                        29:29
+#define GPIO_CTL5_VM_SCR_0_SEC_LCK_MSB                  MK_SHIFT_CONST(29)
+#define GPIO_CTL5_VM_SCR_0_SEC_LCK_LSB                  MK_SHIFT_CONST(29)
+#define GPIO_CTL5_VM_SCR_0_SEC_LCK_WOFFSET                      0x0
+#define GPIO_CTL5_VM_SCR_0_SEC_LCK_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_SEC_LCK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_SEC_LCK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_SEC_WEN_SHIFT                        MK_SHIFT_CONST(28)
+#define GPIO_CTL5_VM_SCR_0_SEC_WEN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_SEC_WEN_RANGE                        28:28
+#define GPIO_CTL5_VM_SCR_0_SEC_WEN_MSB                  MK_SHIFT_CONST(28)
+#define GPIO_CTL5_VM_SCR_0_SEC_WEN_LSB                  MK_SHIFT_CONST(28)
+#define GPIO_CTL5_VM_SCR_0_SEC_WEN_WOFFSET                      0x0
+#define GPIO_CTL5_VM_SCR_0_SEC_WEN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_SEC_WEN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_SEC_WEN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_SEC_REN_SHIFT                        MK_SHIFT_CONST(27)
+#define GPIO_CTL5_VM_SCR_0_SEC_REN_FIELD                        MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_SEC_REN_RANGE                        27:27
+#define GPIO_CTL5_VM_SCR_0_SEC_REN_MSB                  MK_SHIFT_CONST(27)
+#define GPIO_CTL5_VM_SCR_0_SEC_REN_LSB                  MK_SHIFT_CONST(27)
+#define GPIO_CTL5_VM_SCR_0_SEC_REN_WOFFSET                      0x0
+#define GPIO_CTL5_VM_SCR_0_SEC_REN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_SEC_REN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_SEC_REN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_SEC_REN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_SHIFT                      MK_SHIFT_CONST(24)
+#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_FIELD                      MK_FIELD_CONST(0x7, GPIO_CTL5_VM_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_RANGE                      26:24
+#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_MSB                        MK_SHIFT_CONST(26)
+#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_LSB                        MK_SHIFT_CONST(24)
+#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_WOFFSET                    0x0
+#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_PR7_SHIFT                    MK_SHIFT_CONST(23)
+#define GPIO_CTL5_VM_SCR_0_PR7_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR7_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_PR7_RANGE                    23:23
+#define GPIO_CTL5_VM_SCR_0_PR7_MSB                      MK_SHIFT_CONST(23)
+#define GPIO_CTL5_VM_SCR_0_PR7_LSB                      MK_SHIFT_CONST(23)
+#define GPIO_CTL5_VM_SCR_0_PR7_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_PR7_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_PR7_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_PR6_SHIFT                    MK_SHIFT_CONST(22)
+#define GPIO_CTL5_VM_SCR_0_PR6_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR6_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_PR6_RANGE                    22:22
+#define GPIO_CTL5_VM_SCR_0_PR6_MSB                      MK_SHIFT_CONST(22)
+#define GPIO_CTL5_VM_SCR_0_PR6_LSB                      MK_SHIFT_CONST(22)
+#define GPIO_CTL5_VM_SCR_0_PR6_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_PR6_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_PR6_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_PR5_SHIFT                    MK_SHIFT_CONST(21)
+#define GPIO_CTL5_VM_SCR_0_PR5_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR5_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_PR5_RANGE                    21:21
+#define GPIO_CTL5_VM_SCR_0_PR5_MSB                      MK_SHIFT_CONST(21)
+#define GPIO_CTL5_VM_SCR_0_PR5_LSB                      MK_SHIFT_CONST(21)
+#define GPIO_CTL5_VM_SCR_0_PR5_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_PR5_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_PR5_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR5_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_PR4_SHIFT                    MK_SHIFT_CONST(20)
+#define GPIO_CTL5_VM_SCR_0_PR4_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR4_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_PR4_RANGE                    20:20
+#define GPIO_CTL5_VM_SCR_0_PR4_MSB                      MK_SHIFT_CONST(20)
+#define GPIO_CTL5_VM_SCR_0_PR4_LSB                      MK_SHIFT_CONST(20)
+#define GPIO_CTL5_VM_SCR_0_PR4_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_PR4_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_PR4_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_PR3_SHIFT                    MK_SHIFT_CONST(19)
+#define GPIO_CTL5_VM_SCR_0_PR3_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR3_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_PR3_RANGE                    19:19
+#define GPIO_CTL5_VM_SCR_0_PR3_MSB                      MK_SHIFT_CONST(19)
+#define GPIO_CTL5_VM_SCR_0_PR3_LSB                      MK_SHIFT_CONST(19)
+#define GPIO_CTL5_VM_SCR_0_PR3_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_PR3_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_PR3_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_PR2_SHIFT                    MK_SHIFT_CONST(18)
+#define GPIO_CTL5_VM_SCR_0_PR2_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR2_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_PR2_RANGE                    18:18
+#define GPIO_CTL5_VM_SCR_0_PR2_MSB                      MK_SHIFT_CONST(18)
+#define GPIO_CTL5_VM_SCR_0_PR2_LSB                      MK_SHIFT_CONST(18)
+#define GPIO_CTL5_VM_SCR_0_PR2_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_PR2_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_PR2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_PR1_SHIFT                    MK_SHIFT_CONST(17)
+#define GPIO_CTL5_VM_SCR_0_PR1_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR1_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_PR1_RANGE                    17:17
+#define GPIO_CTL5_VM_SCR_0_PR1_MSB                      MK_SHIFT_CONST(17)
+#define GPIO_CTL5_VM_SCR_0_PR1_LSB                      MK_SHIFT_CONST(17)
+#define GPIO_CTL5_VM_SCR_0_PR1_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_PR1_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_PR1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_PR0_SHIFT                    MK_SHIFT_CONST(16)
+#define GPIO_CTL5_VM_SCR_0_PR0_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_PR0_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_PR0_RANGE                    16:16
+#define GPIO_CTL5_VM_SCR_0_PR0_MSB                      MK_SHIFT_CONST(16)
+#define GPIO_CTL5_VM_SCR_0_PR0_LSB                      MK_SHIFT_CONST(16)
+#define GPIO_CTL5_VM_SCR_0_PR0_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_PR0_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_PR0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_PR0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_G7W_SHIFT                    MK_SHIFT_CONST(15)
+#define GPIO_CTL5_VM_SCR_0_G7W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G7W_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_G7W_RANGE                    15:15
+#define GPIO_CTL5_VM_SCR_0_G7W_MSB                      MK_SHIFT_CONST(15)
+#define GPIO_CTL5_VM_SCR_0_G7W_LSB                      MK_SHIFT_CONST(15)
+#define GPIO_CTL5_VM_SCR_0_G7W_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_G7W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G7W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_G7W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G7W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G7W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G7W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_G6W_SHIFT                    MK_SHIFT_CONST(14)
+#define GPIO_CTL5_VM_SCR_0_G6W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G6W_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_G6W_RANGE                    14:14
+#define GPIO_CTL5_VM_SCR_0_G6W_MSB                      MK_SHIFT_CONST(14)
+#define GPIO_CTL5_VM_SCR_0_G6W_LSB                      MK_SHIFT_CONST(14)
+#define GPIO_CTL5_VM_SCR_0_G6W_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_G6W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G6W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_G6W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G6W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G6W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G6W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_G5W_SHIFT                    MK_SHIFT_CONST(13)
+#define GPIO_CTL5_VM_SCR_0_G5W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G5W_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_G5W_RANGE                    13:13
+#define GPIO_CTL5_VM_SCR_0_G5W_MSB                      MK_SHIFT_CONST(13)
+#define GPIO_CTL5_VM_SCR_0_G5W_LSB                      MK_SHIFT_CONST(13)
+#define GPIO_CTL5_VM_SCR_0_G5W_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_G5W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G5W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_G5W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G5W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G5W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G5W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_G4W_SHIFT                    MK_SHIFT_CONST(12)
+#define GPIO_CTL5_VM_SCR_0_G4W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G4W_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_G4W_RANGE                    12:12
+#define GPIO_CTL5_VM_SCR_0_G4W_MSB                      MK_SHIFT_CONST(12)
+#define GPIO_CTL5_VM_SCR_0_G4W_LSB                      MK_SHIFT_CONST(12)
+#define GPIO_CTL5_VM_SCR_0_G4W_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_G4W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G4W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_G4W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G4W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G4W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G4W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_G3W_SHIFT                    MK_SHIFT_CONST(11)
+#define GPIO_CTL5_VM_SCR_0_G3W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G3W_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_G3W_RANGE                    11:11
+#define GPIO_CTL5_VM_SCR_0_G3W_MSB                      MK_SHIFT_CONST(11)
+#define GPIO_CTL5_VM_SCR_0_G3W_LSB                      MK_SHIFT_CONST(11)
+#define GPIO_CTL5_VM_SCR_0_G3W_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_G3W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G3W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_G3W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G3W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G3W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G3W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_G2W_SHIFT                    MK_SHIFT_CONST(10)
+#define GPIO_CTL5_VM_SCR_0_G2W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G2W_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_G2W_RANGE                    10:10
+#define GPIO_CTL5_VM_SCR_0_G2W_MSB                      MK_SHIFT_CONST(10)
+#define GPIO_CTL5_VM_SCR_0_G2W_LSB                      MK_SHIFT_CONST(10)
+#define GPIO_CTL5_VM_SCR_0_G2W_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_G2W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G2W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_G2W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G2W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G2W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G2W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_G1W_SHIFT                    MK_SHIFT_CONST(9)
+#define GPIO_CTL5_VM_SCR_0_G1W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G1W_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_G1W_RANGE                    9:9
+#define GPIO_CTL5_VM_SCR_0_G1W_MSB                      MK_SHIFT_CONST(9)
+#define GPIO_CTL5_VM_SCR_0_G1W_LSB                      MK_SHIFT_CONST(9)
+#define GPIO_CTL5_VM_SCR_0_G1W_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_G1W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G1W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_G1W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G1W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G1W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G1W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_G0W_SHIFT                    MK_SHIFT_CONST(8)
+#define GPIO_CTL5_VM_SCR_0_G0W_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G0W_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_G0W_RANGE                    8:8
+#define GPIO_CTL5_VM_SCR_0_G0W_MSB                      MK_SHIFT_CONST(8)
+#define GPIO_CTL5_VM_SCR_0_G0W_LSB                      MK_SHIFT_CONST(8)
+#define GPIO_CTL5_VM_SCR_0_G0W_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_G0W_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G0W_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_G0W_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G0W_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G0W_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G0W_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_G7R_SHIFT                    MK_SHIFT_CONST(7)
+#define GPIO_CTL5_VM_SCR_0_G7R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G7R_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_G7R_RANGE                    7:7
+#define GPIO_CTL5_VM_SCR_0_G7R_MSB                      MK_SHIFT_CONST(7)
+#define GPIO_CTL5_VM_SCR_0_G7R_LSB                      MK_SHIFT_CONST(7)
+#define GPIO_CTL5_VM_SCR_0_G7R_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_G7R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G7R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_G7R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G7R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G7R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G7R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_G6R_SHIFT                    MK_SHIFT_CONST(6)
+#define GPIO_CTL5_VM_SCR_0_G6R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G6R_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_G6R_RANGE                    6:6
+#define GPIO_CTL5_VM_SCR_0_G6R_MSB                      MK_SHIFT_CONST(6)
+#define GPIO_CTL5_VM_SCR_0_G6R_LSB                      MK_SHIFT_CONST(6)
+#define GPIO_CTL5_VM_SCR_0_G6R_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_G6R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G6R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_G6R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G6R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G6R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G6R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_G5R_SHIFT                    MK_SHIFT_CONST(5)
+#define GPIO_CTL5_VM_SCR_0_G5R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G5R_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_G5R_RANGE                    5:5
+#define GPIO_CTL5_VM_SCR_0_G5R_MSB                      MK_SHIFT_CONST(5)
+#define GPIO_CTL5_VM_SCR_0_G5R_LSB                      MK_SHIFT_CONST(5)
+#define GPIO_CTL5_VM_SCR_0_G5R_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_G5R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G5R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_G5R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G5R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G5R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G5R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_G4R_SHIFT                    MK_SHIFT_CONST(4)
+#define GPIO_CTL5_VM_SCR_0_G4R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G4R_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_G4R_RANGE                    4:4
+#define GPIO_CTL5_VM_SCR_0_G4R_MSB                      MK_SHIFT_CONST(4)
+#define GPIO_CTL5_VM_SCR_0_G4R_LSB                      MK_SHIFT_CONST(4)
+#define GPIO_CTL5_VM_SCR_0_G4R_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_G4R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G4R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_G4R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G4R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G4R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G4R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_G3R_SHIFT                    MK_SHIFT_CONST(3)
+#define GPIO_CTL5_VM_SCR_0_G3R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G3R_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_G3R_RANGE                    3:3
+#define GPIO_CTL5_VM_SCR_0_G3R_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_CTL5_VM_SCR_0_G3R_LSB                      MK_SHIFT_CONST(3)
+#define GPIO_CTL5_VM_SCR_0_G3R_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_G3R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G3R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_G3R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G3R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G3R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G3R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_G2R_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_CTL5_VM_SCR_0_G2R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G2R_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_G2R_RANGE                    2:2
+#define GPIO_CTL5_VM_SCR_0_G2R_MSB                      MK_SHIFT_CONST(2)
+#define GPIO_CTL5_VM_SCR_0_G2R_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_CTL5_VM_SCR_0_G2R_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_G2R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G2R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_G2R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G2R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G2R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G2R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_G1R_SHIFT                    MK_SHIFT_CONST(1)
+#define GPIO_CTL5_VM_SCR_0_G1R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G1R_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_G1R_RANGE                    1:1
+#define GPIO_CTL5_VM_SCR_0_G1R_MSB                      MK_SHIFT_CONST(1)
+#define GPIO_CTL5_VM_SCR_0_G1R_LSB                      MK_SHIFT_CONST(1)
+#define GPIO_CTL5_VM_SCR_0_G1R_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_G1R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G1R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_G1R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G1R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G1R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G1R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_VM_SCR_0_G0R_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_CTL5_VM_SCR_0_G0R_FIELD                    MK_FIELD_CONST(0x1, GPIO_CTL5_VM_SCR_0_G0R_SHIFT)
+#define GPIO_CTL5_VM_SCR_0_G0R_RANGE                    0:0
+#define GPIO_CTL5_VM_SCR_0_G0R_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_CTL5_VM_SCR_0_G0R_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_CTL5_VM_SCR_0_G0R_WOFFSET                  0x0
+#define GPIO_CTL5_VM_SCR_0_G0R_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G0R_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_CTL5_VM_SCR_0_G0R_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G0R_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G0R_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_VM_SCR_0_G0R_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0                     MK_ADDR_CONST(0x5804)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SECURE                      0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_DUAL                        0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SCR                         0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SCRREG                      0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_WORD_COUNT                  0x1
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT                       MK_SHIFT_CONST(29)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_RANGE                       29:29
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_MSB                 MK_SHIFT_CONST(29)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_LSB                 MK_SHIFT_CONST(29)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_WOFFSET                     0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT                       MK_SHIFT_CONST(28)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_RANGE                       28:28
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_MSB                 MK_SHIFT_CONST(28)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_LSB                 MK_SHIFT_CONST(28)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_WOFFSET                     0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT                       MK_SHIFT_CONST(27)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_RANGE                       27:27
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_MSB                 MK_SHIFT_CONST(27)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_LSB                 MK_SHIFT_CONST(27)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_WOFFSET                     0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_REN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT                     MK_SHIFT_CONST(24)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_FIELD                     MK_FIELD_CONST(0x7, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_RANGE                     26:24
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_MSB                       MK_SHIFT_CONST(26)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_LSB                       MK_SHIFT_CONST(24)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_WOFFSET                   0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT                   MK_SHIFT_CONST(23)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_RANGE                   23:23
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_MSB                     MK_SHIFT_CONST(23)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_LSB                     MK_SHIFT_CONST(23)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT                   MK_SHIFT_CONST(22)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_RANGE                   22:22
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_MSB                     MK_SHIFT_CONST(22)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_LSB                     MK_SHIFT_CONST(22)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT                   MK_SHIFT_CONST(21)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_RANGE                   21:21
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_MSB                     MK_SHIFT_CONST(21)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_LSB                     MK_SHIFT_CONST(21)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT                   MK_SHIFT_CONST(20)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_RANGE                   20:20
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_MSB                     MK_SHIFT_CONST(20)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_LSB                     MK_SHIFT_CONST(20)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT                   MK_SHIFT_CONST(19)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_RANGE                   19:19
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_MSB                     MK_SHIFT_CONST(19)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_LSB                     MK_SHIFT_CONST(19)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT                   MK_SHIFT_CONST(18)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_RANGE                   18:18
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_MSB                     MK_SHIFT_CONST(18)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_LSB                     MK_SHIFT_CONST(18)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT                   MK_SHIFT_CONST(17)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_RANGE                   17:17
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_MSB                     MK_SHIFT_CONST(17)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_LSB                     MK_SHIFT_CONST(17)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT                   MK_SHIFT_CONST(16)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_RANGE                   16:16
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_MSB                     MK_SHIFT_CONST(16)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_LSB                     MK_SHIFT_CONST(16)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_PR0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT                   MK_SHIFT_CONST(15)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_RANGE                   15:15
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_MSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_LSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT                   MK_SHIFT_CONST(14)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_RANGE                   14:14
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_MSB                     MK_SHIFT_CONST(14)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_LSB                     MK_SHIFT_CONST(14)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT                   MK_SHIFT_CONST(13)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_RANGE                   13:13
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_MSB                     MK_SHIFT_CONST(13)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_LSB                     MK_SHIFT_CONST(13)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT                   MK_SHIFT_CONST(12)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_RANGE                   12:12
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_MSB                     MK_SHIFT_CONST(12)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_LSB                     MK_SHIFT_CONST(12)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT                   MK_SHIFT_CONST(11)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_RANGE                   11:11
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_MSB                     MK_SHIFT_CONST(11)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_LSB                     MK_SHIFT_CONST(11)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT                   MK_SHIFT_CONST(10)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_RANGE                   10:10
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_MSB                     MK_SHIFT_CONST(10)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_LSB                     MK_SHIFT_CONST(10)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT                   MK_SHIFT_CONST(9)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_RANGE                   9:9
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_MSB                     MK_SHIFT_CONST(9)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_LSB                     MK_SHIFT_CONST(9)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT                   MK_SHIFT_CONST(8)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_RANGE                   8:8
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_MSB                     MK_SHIFT_CONST(8)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_LSB                     MK_SHIFT_CONST(8)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0W_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_RANGE                   7:7
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G7R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT                   MK_SHIFT_CONST(6)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_RANGE                   6:6
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_MSB                     MK_SHIFT_CONST(6)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_LSB                     MK_SHIFT_CONST(6)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G6R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT                   MK_SHIFT_CONST(5)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_RANGE                   5:5
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_LSB                     MK_SHIFT_CONST(5)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G5R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_RANGE                   4:4
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G4R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT                   MK_SHIFT_CONST(3)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_RANGE                   3:3
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_LSB                     MK_SHIFT_CONST(3)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G3R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_RANGE                   2:2
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_MSB                     MK_SHIFT_CONST(2)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G2R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT                   MK_SHIFT_CONST(1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_RANGE                   1:1
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_MSB                     MK_SHIFT_CONST(1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_LSB                     MK_SHIFT_CONST(1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G1R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_RANGE                   0:0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_MSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_WOFFSET                 0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0_G0R_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL5_INTERRUPT_STATUS_VM_0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0                 MK_ADDR_CONST(0x5808)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SECURE                  0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_DUAL                    0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SCR                     GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SCRREG                  GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_WORD_COUNT                      0x1
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_FIELD                  MK_FIELD_CONST(0xff, GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SHIFT)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_RANGE                  7:0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_WOFFSET                        0x0
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_INTERRUPT_STATUS_VM_0_GPIO_INTERRUPT_STATUS_VM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL5_SCR_0
+#define GPIO_CTL5_SCR_0                 MK_ADDR_CONST(0x580c)
+#define GPIO_CTL5_SCR_0_SECURE                  0x0
+#define GPIO_CTL5_SCR_0_DUAL                    0x0
+#define GPIO_CTL5_SCR_0_SCR                     0
+#define GPIO_CTL5_SCR_0_SCRREG                  0
+#define GPIO_CTL5_SCR_0_WORD_COUNT                      0x1
+#define GPIO_CTL5_SCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_RESET_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL5_SCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_READ_MASK                       MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL5_SCR_0_WRITE_MASK                      MK_MASK_CONST(0x3fffffff)
+#define GPIO_CTL5_SCR_0_SEC_LCK_SHIFT                   MK_SHIFT_CONST(29)
+#define GPIO_CTL5_SCR_0_SEC_LCK_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_SEC_LCK_SHIFT)
+#define GPIO_CTL5_SCR_0_SEC_LCK_RANGE                   29:29
+#define GPIO_CTL5_SCR_0_SEC_LCK_MSB                     MK_SHIFT_CONST(29)
+#define GPIO_CTL5_SCR_0_SEC_LCK_LSB                     MK_SHIFT_CONST(29)
+#define GPIO_CTL5_SCR_0_SEC_LCK_WOFFSET                 0x0
+#define GPIO_CTL5_SCR_0_SEC_LCK_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_SEC_LCK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_SEC_LCK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_SEC_LCK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_SEC_LCK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_SEC_LCK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_SEC_WEN_SHIFT                   MK_SHIFT_CONST(28)
+#define GPIO_CTL5_SCR_0_SEC_WEN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_SEC_WEN_SHIFT)
+#define GPIO_CTL5_SCR_0_SEC_WEN_RANGE                   28:28
+#define GPIO_CTL5_SCR_0_SEC_WEN_MSB                     MK_SHIFT_CONST(28)
+#define GPIO_CTL5_SCR_0_SEC_WEN_LSB                     MK_SHIFT_CONST(28)
+#define GPIO_CTL5_SCR_0_SEC_WEN_WOFFSET                 0x0
+#define GPIO_CTL5_SCR_0_SEC_WEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_SEC_WEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_SEC_WEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_SEC_WEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_SEC_WEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_SEC_WEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_SEC_REN_SHIFT                   MK_SHIFT_CONST(27)
+#define GPIO_CTL5_SCR_0_SEC_REN_FIELD                   MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_SEC_REN_SHIFT)
+#define GPIO_CTL5_SCR_0_SEC_REN_RANGE                   27:27
+#define GPIO_CTL5_SCR_0_SEC_REN_MSB                     MK_SHIFT_CONST(27)
+#define GPIO_CTL5_SCR_0_SEC_REN_LSB                     MK_SHIFT_CONST(27)
+#define GPIO_CTL5_SCR_0_SEC_REN_WOFFSET                 0x0
+#define GPIO_CTL5_SCR_0_SEC_REN_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_SEC_REN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_SEC_REN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_SEC_REN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_SEC_REN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_SEC_REN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_SEC_OWNER_SHIFT                 MK_SHIFT_CONST(24)
+#define GPIO_CTL5_SCR_0_SEC_OWNER_FIELD                 MK_FIELD_CONST(0x7, GPIO_CTL5_SCR_0_SEC_OWNER_SHIFT)
+#define GPIO_CTL5_SCR_0_SEC_OWNER_RANGE                 26:24
+#define GPIO_CTL5_SCR_0_SEC_OWNER_MSB                   MK_SHIFT_CONST(26)
+#define GPIO_CTL5_SCR_0_SEC_OWNER_LSB                   MK_SHIFT_CONST(24)
+#define GPIO_CTL5_SCR_0_SEC_OWNER_WOFFSET                       0x0
+#define GPIO_CTL5_SCR_0_SEC_OWNER_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_SEC_OWNER_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define GPIO_CTL5_SCR_0_SEC_OWNER_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_SEC_OWNER_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_SEC_OWNER_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_SEC_OWNER_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_PR7_SHIFT                       MK_SHIFT_CONST(23)
+#define GPIO_CTL5_SCR_0_PR7_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR7_SHIFT)
+#define GPIO_CTL5_SCR_0_PR7_RANGE                       23:23
+#define GPIO_CTL5_SCR_0_PR7_MSB                 MK_SHIFT_CONST(23)
+#define GPIO_CTL5_SCR_0_PR7_LSB                 MK_SHIFT_CONST(23)
+#define GPIO_CTL5_SCR_0_PR7_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_PR7_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_PR7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_PR6_SHIFT                       MK_SHIFT_CONST(22)
+#define GPIO_CTL5_SCR_0_PR6_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR6_SHIFT)
+#define GPIO_CTL5_SCR_0_PR6_RANGE                       22:22
+#define GPIO_CTL5_SCR_0_PR6_MSB                 MK_SHIFT_CONST(22)
+#define GPIO_CTL5_SCR_0_PR6_LSB                 MK_SHIFT_CONST(22)
+#define GPIO_CTL5_SCR_0_PR6_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_PR6_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_PR6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_PR5_SHIFT                       MK_SHIFT_CONST(21)
+#define GPIO_CTL5_SCR_0_PR5_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR5_SHIFT)
+#define GPIO_CTL5_SCR_0_PR5_RANGE                       21:21
+#define GPIO_CTL5_SCR_0_PR5_MSB                 MK_SHIFT_CONST(21)
+#define GPIO_CTL5_SCR_0_PR5_LSB                 MK_SHIFT_CONST(21)
+#define GPIO_CTL5_SCR_0_PR5_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_PR5_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_PR5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_PR4_SHIFT                       MK_SHIFT_CONST(20)
+#define GPIO_CTL5_SCR_0_PR4_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR4_SHIFT)
+#define GPIO_CTL5_SCR_0_PR4_RANGE                       20:20
+#define GPIO_CTL5_SCR_0_PR4_MSB                 MK_SHIFT_CONST(20)
+#define GPIO_CTL5_SCR_0_PR4_LSB                 MK_SHIFT_CONST(20)
+#define GPIO_CTL5_SCR_0_PR4_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_PR4_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_PR4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_PR3_SHIFT                       MK_SHIFT_CONST(19)
+#define GPIO_CTL5_SCR_0_PR3_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR3_SHIFT)
+#define GPIO_CTL5_SCR_0_PR3_RANGE                       19:19
+#define GPIO_CTL5_SCR_0_PR3_MSB                 MK_SHIFT_CONST(19)
+#define GPIO_CTL5_SCR_0_PR3_LSB                 MK_SHIFT_CONST(19)
+#define GPIO_CTL5_SCR_0_PR3_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_PR3_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_PR3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_PR2_SHIFT                       MK_SHIFT_CONST(18)
+#define GPIO_CTL5_SCR_0_PR2_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR2_SHIFT)
+#define GPIO_CTL5_SCR_0_PR2_RANGE                       18:18
+#define GPIO_CTL5_SCR_0_PR2_MSB                 MK_SHIFT_CONST(18)
+#define GPIO_CTL5_SCR_0_PR2_LSB                 MK_SHIFT_CONST(18)
+#define GPIO_CTL5_SCR_0_PR2_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_PR2_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_PR2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_PR1_SHIFT                       MK_SHIFT_CONST(17)
+#define GPIO_CTL5_SCR_0_PR1_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR1_SHIFT)
+#define GPIO_CTL5_SCR_0_PR1_RANGE                       17:17
+#define GPIO_CTL5_SCR_0_PR1_MSB                 MK_SHIFT_CONST(17)
+#define GPIO_CTL5_SCR_0_PR1_LSB                 MK_SHIFT_CONST(17)
+#define GPIO_CTL5_SCR_0_PR1_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_PR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_PR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_PR0_SHIFT                       MK_SHIFT_CONST(16)
+#define GPIO_CTL5_SCR_0_PR0_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_PR0_SHIFT)
+#define GPIO_CTL5_SCR_0_PR0_RANGE                       16:16
+#define GPIO_CTL5_SCR_0_PR0_MSB                 MK_SHIFT_CONST(16)
+#define GPIO_CTL5_SCR_0_PR0_LSB                 MK_SHIFT_CONST(16)
+#define GPIO_CTL5_SCR_0_PR0_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_PR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_PR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_PR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_G7W_SHIFT                       MK_SHIFT_CONST(15)
+#define GPIO_CTL5_SCR_0_G7W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G7W_SHIFT)
+#define GPIO_CTL5_SCR_0_G7W_RANGE                       15:15
+#define GPIO_CTL5_SCR_0_G7W_MSB                 MK_SHIFT_CONST(15)
+#define GPIO_CTL5_SCR_0_G7W_LSB                 MK_SHIFT_CONST(15)
+#define GPIO_CTL5_SCR_0_G7W_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_G7W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G7W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_G7W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G7W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G7W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G7W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_G6W_SHIFT                       MK_SHIFT_CONST(14)
+#define GPIO_CTL5_SCR_0_G6W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G6W_SHIFT)
+#define GPIO_CTL5_SCR_0_G6W_RANGE                       14:14
+#define GPIO_CTL5_SCR_0_G6W_MSB                 MK_SHIFT_CONST(14)
+#define GPIO_CTL5_SCR_0_G6W_LSB                 MK_SHIFT_CONST(14)
+#define GPIO_CTL5_SCR_0_G6W_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_G6W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G6W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_G6W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G6W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G6W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G6W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_G5W_SHIFT                       MK_SHIFT_CONST(13)
+#define GPIO_CTL5_SCR_0_G5W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G5W_SHIFT)
+#define GPIO_CTL5_SCR_0_G5W_RANGE                       13:13
+#define GPIO_CTL5_SCR_0_G5W_MSB                 MK_SHIFT_CONST(13)
+#define GPIO_CTL5_SCR_0_G5W_LSB                 MK_SHIFT_CONST(13)
+#define GPIO_CTL5_SCR_0_G5W_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_G5W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G5W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_G5W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G5W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G5W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G5W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_G4W_SHIFT                       MK_SHIFT_CONST(12)
+#define GPIO_CTL5_SCR_0_G4W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G4W_SHIFT)
+#define GPIO_CTL5_SCR_0_G4W_RANGE                       12:12
+#define GPIO_CTL5_SCR_0_G4W_MSB                 MK_SHIFT_CONST(12)
+#define GPIO_CTL5_SCR_0_G4W_LSB                 MK_SHIFT_CONST(12)
+#define GPIO_CTL5_SCR_0_G4W_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_G4W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G4W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_G4W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G4W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G4W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G4W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_G3W_SHIFT                       MK_SHIFT_CONST(11)
+#define GPIO_CTL5_SCR_0_G3W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G3W_SHIFT)
+#define GPIO_CTL5_SCR_0_G3W_RANGE                       11:11
+#define GPIO_CTL5_SCR_0_G3W_MSB                 MK_SHIFT_CONST(11)
+#define GPIO_CTL5_SCR_0_G3W_LSB                 MK_SHIFT_CONST(11)
+#define GPIO_CTL5_SCR_0_G3W_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_G3W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G3W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_G3W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G3W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G3W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G3W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_G2W_SHIFT                       MK_SHIFT_CONST(10)
+#define GPIO_CTL5_SCR_0_G2W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G2W_SHIFT)
+#define GPIO_CTL5_SCR_0_G2W_RANGE                       10:10
+#define GPIO_CTL5_SCR_0_G2W_MSB                 MK_SHIFT_CONST(10)
+#define GPIO_CTL5_SCR_0_G2W_LSB                 MK_SHIFT_CONST(10)
+#define GPIO_CTL5_SCR_0_G2W_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_G2W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G2W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_G2W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G2W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G2W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G2W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_G1W_SHIFT                       MK_SHIFT_CONST(9)
+#define GPIO_CTL5_SCR_0_G1W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G1W_SHIFT)
+#define GPIO_CTL5_SCR_0_G1W_RANGE                       9:9
+#define GPIO_CTL5_SCR_0_G1W_MSB                 MK_SHIFT_CONST(9)
+#define GPIO_CTL5_SCR_0_G1W_LSB                 MK_SHIFT_CONST(9)
+#define GPIO_CTL5_SCR_0_G1W_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_G1W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G1W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_G1W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G1W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G1W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G1W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_G0W_SHIFT                       MK_SHIFT_CONST(8)
+#define GPIO_CTL5_SCR_0_G0W_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G0W_SHIFT)
+#define GPIO_CTL5_SCR_0_G0W_RANGE                       8:8
+#define GPIO_CTL5_SCR_0_G0W_MSB                 MK_SHIFT_CONST(8)
+#define GPIO_CTL5_SCR_0_G0W_LSB                 MK_SHIFT_CONST(8)
+#define GPIO_CTL5_SCR_0_G0W_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_G0W_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G0W_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_G0W_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G0W_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G0W_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G0W_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_G7R_SHIFT                       MK_SHIFT_CONST(7)
+#define GPIO_CTL5_SCR_0_G7R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G7R_SHIFT)
+#define GPIO_CTL5_SCR_0_G7R_RANGE                       7:7
+#define GPIO_CTL5_SCR_0_G7R_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_CTL5_SCR_0_G7R_LSB                 MK_SHIFT_CONST(7)
+#define GPIO_CTL5_SCR_0_G7R_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_G7R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G7R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_G7R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G7R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G7R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G7R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_G6R_SHIFT                       MK_SHIFT_CONST(6)
+#define GPIO_CTL5_SCR_0_G6R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G6R_SHIFT)
+#define GPIO_CTL5_SCR_0_G6R_RANGE                       6:6
+#define GPIO_CTL5_SCR_0_G6R_MSB                 MK_SHIFT_CONST(6)
+#define GPIO_CTL5_SCR_0_G6R_LSB                 MK_SHIFT_CONST(6)
+#define GPIO_CTL5_SCR_0_G6R_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_G6R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G6R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_G6R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G6R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G6R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G6R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_G5R_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_CTL5_SCR_0_G5R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G5R_SHIFT)
+#define GPIO_CTL5_SCR_0_G5R_RANGE                       5:5
+#define GPIO_CTL5_SCR_0_G5R_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_CTL5_SCR_0_G5R_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_CTL5_SCR_0_G5R_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_G5R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G5R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_G5R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G5R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G5R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G5R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_G4R_SHIFT                       MK_SHIFT_CONST(4)
+#define GPIO_CTL5_SCR_0_G4R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G4R_SHIFT)
+#define GPIO_CTL5_SCR_0_G4R_RANGE                       4:4
+#define GPIO_CTL5_SCR_0_G4R_MSB                 MK_SHIFT_CONST(4)
+#define GPIO_CTL5_SCR_0_G4R_LSB                 MK_SHIFT_CONST(4)
+#define GPIO_CTL5_SCR_0_G4R_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_G4R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G4R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_G4R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G4R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G4R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G4R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_G3R_SHIFT                       MK_SHIFT_CONST(3)
+#define GPIO_CTL5_SCR_0_G3R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G3R_SHIFT)
+#define GPIO_CTL5_SCR_0_G3R_RANGE                       3:3
+#define GPIO_CTL5_SCR_0_G3R_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_CTL5_SCR_0_G3R_LSB                 MK_SHIFT_CONST(3)
+#define GPIO_CTL5_SCR_0_G3R_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_G3R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G3R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_G3R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G3R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G3R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G3R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_G2R_SHIFT                       MK_SHIFT_CONST(2)
+#define GPIO_CTL5_SCR_0_G2R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G2R_SHIFT)
+#define GPIO_CTL5_SCR_0_G2R_RANGE                       2:2
+#define GPIO_CTL5_SCR_0_G2R_MSB                 MK_SHIFT_CONST(2)
+#define GPIO_CTL5_SCR_0_G2R_LSB                 MK_SHIFT_CONST(2)
+#define GPIO_CTL5_SCR_0_G2R_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_G2R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G2R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_G2R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G2R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G2R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G2R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_G1R_SHIFT                       MK_SHIFT_CONST(1)
+#define GPIO_CTL5_SCR_0_G1R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G1R_SHIFT)
+#define GPIO_CTL5_SCR_0_G1R_RANGE                       1:1
+#define GPIO_CTL5_SCR_0_G1R_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_CTL5_SCR_0_G1R_LSB                 MK_SHIFT_CONST(1)
+#define GPIO_CTL5_SCR_0_G1R_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_G1R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G1R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_G1R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G1R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G1R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G1R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GPIO_CTL5_SCR_0_G0R_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_CTL5_SCR_0_G0R_FIELD                       MK_FIELD_CONST(0x1, GPIO_CTL5_SCR_0_G0R_SHIFT)
+#define GPIO_CTL5_SCR_0_G0R_RANGE                       0:0
+#define GPIO_CTL5_SCR_0_G0R_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_CTL5_SCR_0_G0R_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_CTL5_SCR_0_G0R_WOFFSET                     0x0
+#define GPIO_CTL5_SCR_0_G0R_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G0R_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_CTL5_SCR_0_G0R_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G0R_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G0R_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SCR_0_G0R_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL5_ICG_EN_OVERRIDE_0
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0                     MK_ADDR_CONST(0x5810)
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SECURE                      0x0
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_DUAL                        0x0
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_WORD_COUNT                  0x1
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_FIELD                  MK_FIELD_CONST(0x1, GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SHIFT)
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_RANGE                  0:0
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_WOFFSET                        0x0
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_CTL5_ICG_EN_OVERRIDE_0_GPIO_ICG_EN_OVERRIDE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INT0_ROUTE_MAPPING_0
+#define GPIO_J_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5814)
+#define GPIO_J_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_J_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_J_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_J_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_J_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_J_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_J_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_J_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INT1_ROUTE_MAPPING_0
+#define GPIO_J_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5818)
+#define GPIO_J_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_J_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_J_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_J_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_J_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_J_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_J_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_J_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INT2_ROUTE_MAPPING_0
+#define GPIO_J_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x581c)
+#define GPIO_J_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_J_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_J_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_J_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_J_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_J_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_J_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_J_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INT3_ROUTE_MAPPING_0
+#define GPIO_J_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5820)
+#define GPIO_J_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_J_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_J_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_J_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_J_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_J_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_J_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_J_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INT4_ROUTE_MAPPING_0
+#define GPIO_J_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5824)
+#define GPIO_J_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_J_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_J_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_J_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_J_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_J_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_J_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_J_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INT5_ROUTE_MAPPING_0
+#define GPIO_J_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5828)
+#define GPIO_J_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_J_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_J_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_J_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_J_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_J_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_J_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_J_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INT6_ROUTE_MAPPING_0
+#define GPIO_J_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x582c)
+#define GPIO_J_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_J_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_J_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_J_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_J_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_J_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_J_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_J_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INT7_ROUTE_MAPPING_0
+#define GPIO_J_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5830)
+#define GPIO_J_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_J_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_J_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_J_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_J_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_J_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_J_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_J_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INT0_ROUTE_MAPPING_0
+#define GPIO_C_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5834)
+#define GPIO_C_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_C_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_C_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_C_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_C_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_C_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_C_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_C_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INT1_ROUTE_MAPPING_0
+#define GPIO_C_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5838)
+#define GPIO_C_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_C_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_C_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_C_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_C_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_C_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_C_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_C_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INT2_ROUTE_MAPPING_0
+#define GPIO_C_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x583c)
+#define GPIO_C_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_C_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_C_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_C_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_C_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_C_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_C_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_C_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INT3_ROUTE_MAPPING_0
+#define GPIO_C_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5840)
+#define GPIO_C_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_C_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_C_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_C_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_C_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_C_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_C_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_C_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INT4_ROUTE_MAPPING_0
+#define GPIO_C_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5844)
+#define GPIO_C_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_C_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_C_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_C_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_C_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_C_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_C_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_C_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INT5_ROUTE_MAPPING_0
+#define GPIO_C_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5848)
+#define GPIO_C_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_C_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_C_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_C_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_C_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_C_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_C_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_C_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INT6_ROUTE_MAPPING_0
+#define GPIO_C_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x584c)
+#define GPIO_C_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_C_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_C_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_C_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_C_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_C_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_C_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_C_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INT7_ROUTE_MAPPING_0
+#define GPIO_C_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5850)
+#define GPIO_C_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_C_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_C_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_C_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_C_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_C_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_C_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_C_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INT0_ROUTE_MAPPING_0
+#define GPIO_D_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5854)
+#define GPIO_D_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_D_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_D_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_D_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_D_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_D_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_D_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_D_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_D_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_RANGE                   3:0
+#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_D_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INT1_ROUTE_MAPPING_0
+#define GPIO_D_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5858)
+#define GPIO_D_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_D_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_D_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_D_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_D_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_D_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_D_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_D_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_D_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_RANGE                   3:0
+#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_D_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INT2_ROUTE_MAPPING_0
+#define GPIO_D_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x585c)
+#define GPIO_D_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_D_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_D_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_D_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_D_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_D_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_D_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_D_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_D_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_RANGE                   3:0
+#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_D_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INT3_ROUTE_MAPPING_0
+#define GPIO_D_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5860)
+#define GPIO_D_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_D_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_D_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_D_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_D_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_D_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_D_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_D_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_D_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_RANGE                   3:0
+#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_D_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INT4_ROUTE_MAPPING_0
+#define GPIO_D_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5864)
+#define GPIO_D_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_D_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_D_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_D_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_D_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_D_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_D_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_D_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_D_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_RANGE                   3:0
+#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_D_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INT5_ROUTE_MAPPING_0
+#define GPIO_D_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5868)
+#define GPIO_D_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_D_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_D_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_D_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_D_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_D_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_D_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_D_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_D_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_RANGE                   3:0
+#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_D_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INT6_ROUTE_MAPPING_0
+#define GPIO_D_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x586c)
+#define GPIO_D_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_D_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_D_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_D_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_D_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_D_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_D_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_D_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_D_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_RANGE                   3:0
+#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_D_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INT7_ROUTE_MAPPING_0
+#define GPIO_D_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5870)
+#define GPIO_D_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_D_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_D_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_D_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_D_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_D_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_D_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define GPIO_D_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xf, GPIO_D_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_RANGE                   3:0
+#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_D_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INT0_ROUTE_MAPPING_0
+#define GPIO_E_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5874)
+#define GPIO_E_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_E_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_E_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_E_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_E_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_E_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_E_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_E_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INT1_ROUTE_MAPPING_0
+#define GPIO_E_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5878)
+#define GPIO_E_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_E_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_E_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_E_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_E_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_E_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_E_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_E_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INT2_ROUTE_MAPPING_0
+#define GPIO_E_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x587c)
+#define GPIO_E_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_E_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_E_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_E_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_E_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_E_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_E_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_E_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INT3_ROUTE_MAPPING_0
+#define GPIO_E_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5880)
+#define GPIO_E_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_E_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_E_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_E_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_E_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_E_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_E_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_E_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INT4_ROUTE_MAPPING_0
+#define GPIO_E_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5884)
+#define GPIO_E_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_E_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_E_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_E_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_E_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_E_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_E_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_E_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INT5_ROUTE_MAPPING_0
+#define GPIO_E_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5888)
+#define GPIO_E_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_E_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_E_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_E_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_E_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_E_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_E_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_E_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INT6_ROUTE_MAPPING_0
+#define GPIO_E_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x588c)
+#define GPIO_E_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_E_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_E_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_E_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_E_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_E_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_E_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_E_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INT7_ROUTE_MAPPING_0
+#define GPIO_E_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5890)
+#define GPIO_E_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_E_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_E_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_E_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_E_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_E_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_E_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0xff, GPIO_E_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_RANGE                   7:0
+#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INT0_ROUTE_MAPPING_0
+#define GPIO_F_INT0_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5894)
+#define GPIO_F_INT0_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_F_INT0_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_F_INT0_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_F_INT0_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_F_INT0_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_F_INT0_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_INT0_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INT0_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_INT0_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_INT0_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_F_INT0_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_F_INT0_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_INT0_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INT1_ROUTE_MAPPING_0
+#define GPIO_F_INT1_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x5898)
+#define GPIO_F_INT1_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_F_INT1_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_F_INT1_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_F_INT1_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_F_INT1_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_F_INT1_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_INT1_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INT1_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_INT1_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_INT1_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_F_INT1_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_F_INT1_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_INT1_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INT2_ROUTE_MAPPING_0
+#define GPIO_F_INT2_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x589c)
+#define GPIO_F_INT2_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_F_INT2_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_F_INT2_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_F_INT2_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_F_INT2_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_F_INT2_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_INT2_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INT2_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_INT2_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_INT2_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_F_INT2_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_F_INT2_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_INT2_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INT3_ROUTE_MAPPING_0
+#define GPIO_F_INT3_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x58a0)
+#define GPIO_F_INT3_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_F_INT3_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_F_INT3_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_F_INT3_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_F_INT3_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_F_INT3_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_INT3_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INT3_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_INT3_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_INT3_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_F_INT3_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_F_INT3_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_INT3_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INT4_ROUTE_MAPPING_0
+#define GPIO_F_INT4_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x58a4)
+#define GPIO_F_INT4_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_F_INT4_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_F_INT4_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_F_INT4_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_F_INT4_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_F_INT4_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_INT4_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INT4_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_INT4_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_INT4_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_F_INT4_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_F_INT4_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_INT4_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INT5_ROUTE_MAPPING_0
+#define GPIO_F_INT5_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x58a8)
+#define GPIO_F_INT5_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_F_INT5_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_F_INT5_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_F_INT5_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_F_INT5_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_F_INT5_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_INT5_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INT5_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_INT5_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_INT5_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_F_INT5_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_F_INT5_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_INT5_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INT6_ROUTE_MAPPING_0
+#define GPIO_F_INT6_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x58ac)
+#define GPIO_F_INT6_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_F_INT6_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_F_INT6_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_F_INT6_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_F_INT6_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_F_INT6_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_INT6_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INT6_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_INT6_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_INT6_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_F_INT6_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_F_INT6_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_INT6_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INT7_ROUTE_MAPPING_0
+#define GPIO_F_INT7_ROUTE_MAPPING_0                     MK_ADDR_CONST(0x58b0)
+#define GPIO_F_INT7_ROUTE_MAPPING_0_SECURE                      0x0
+#define GPIO_F_INT7_ROUTE_MAPPING_0_DUAL                        0x0
+#define GPIO_F_INT7_ROUTE_MAPPING_0_SCR                         GPIO_CTL5_SCR_0
+#define GPIO_F_INT7_ROUTE_MAPPING_0_SCRREG                      GPIO_CTL5_SCR_0
+#define GPIO_F_INT7_ROUTE_MAPPING_0_WORD_COUNT                  0x1
+#define GPIO_F_INT7_ROUTE_MAPPING_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_INT7_ROUTE_MAPPING_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INT7_ROUTE_MAPPING_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_INT7_ROUTE_MAPPING_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_INT7_ROUTE_MAPPING_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define GPIO_F_INT7_ROUTE_MAPPING_0_WRITE_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_FIELD                   MK_FIELD_CONST(0x3f, GPIO_F_INT7_ROUTE_MAPPING_0_VAL_SHIFT)
+#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_RANGE                   5:0
+#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_MSB                     MK_SHIFT_CONST(5)
+#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_WOFFSET                 0x0
+#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_INT7_ROUTE_MAPPING_0_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_CTL5_SPARE_0
+#define GPIO_CTL5_SPARE_0                       MK_ADDR_CONST(0x58b4)
+#define GPIO_CTL5_SPARE_0_SECURE                        0x0
+#define GPIO_CTL5_SPARE_0_DUAL                  0x0
+#define GPIO_CTL5_SPARE_0_SCR                   0
+#define GPIO_CTL5_SPARE_0_SCRREG                        0
+#define GPIO_CTL5_SPARE_0_WORD_COUNT                    0x1
+#define GPIO_CTL5_SPARE_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SPARE_0_RESET_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL5_SPARE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SPARE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SPARE_0_READ_MASK                     MK_MASK_CONST(0xffff)
+#define GPIO_CTL5_SPARE_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL5_SPARE_0_SPARE_SHIFT                   MK_SHIFT_CONST(0)
+#define GPIO_CTL5_SPARE_0_SPARE_FIELD                   MK_FIELD_CONST(0xffff, GPIO_CTL5_SPARE_0_SPARE_SHIFT)
+#define GPIO_CTL5_SPARE_0_SPARE_RANGE                   15:0
+#define GPIO_CTL5_SPARE_0_SPARE_MSB                     MK_SHIFT_CONST(15)
+#define GPIO_CTL5_SPARE_0_SPARE_LSB                     MK_SHIFT_CONST(0)
+#define GPIO_CTL5_SPARE_0_SPARE_WOFFSET                 0x0
+#define GPIO_CTL5_SPARE_0_SPARE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SPARE_0_SPARE_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define GPIO_CTL5_SPARE_0_SPARE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SPARE_0_SPARE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SPARE_0_SPARE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define GPIO_CTL5_SPARE_0_SPARE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_ENABLE_CONFIG_00_0
+#define GPIO_A_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x10000)
+#define GPIO_A_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_A_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_A_ENABLE_CONFIG_00_0_SCR                   GPIO_A_SCR_00_0
+#define GPIO_A_ENABLE_CONFIG_00_0_SCRREG                        GPIO_A_SCR_00_0
+#define GPIO_A_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_A_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_A_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x10004)
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_A_SCR_00_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_A_SCR_00_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_A_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INPUT_00_0
+#define GPIO_A_INPUT_00_0                       MK_ADDR_CONST(0x10008)
+#define GPIO_A_INPUT_00_0_SECURE                        0x0
+#define GPIO_A_INPUT_00_0_DUAL                  0x0
+#define GPIO_A_INPUT_00_0_SCR                   GPIO_A_SCR_00_0
+#define GPIO_A_INPUT_00_0_SCRREG                        GPIO_A_SCR_00_0
+#define GPIO_A_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_A_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_A_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_A_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_A_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_A_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_OUTPUT_CONTROL_00_0
+#define GPIO_A_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1000c)
+#define GPIO_A_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_A_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_A_OUTPUT_CONTROL_00_0_SCR                  GPIO_A_SCR_00_0
+#define GPIO_A_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_A_SCR_00_0
+#define GPIO_A_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_A_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_A_OUTPUT_VALUE_00_0
+#define GPIO_A_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x10010)
+#define GPIO_A_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_A_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_A_OUTPUT_VALUE_00_0_SCR                    GPIO_A_SCR_00_0
+#define GPIO_A_OUTPUT_VALUE_00_0_SCRREG                         GPIO_A_SCR_00_0
+#define GPIO_A_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_A_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INTERRUPT_CLEAR_00_0
+#define GPIO_A_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x10014)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_A_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_A_INTERRUPT_CLEAR_00_0_SCR                         GPIO_A_SCR_00_0
+#define GPIO_A_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_A_SCR_00_0
+#define GPIO_A_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_A_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10018
+
+// Reserved address 0x1001c
+
+// Register GPIO_A_ENABLE_CONFIG_01_0
+#define GPIO_A_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x10020)
+#define GPIO_A_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_A_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_A_ENABLE_CONFIG_01_0_SCR                   GPIO_A_SCR_01_0
+#define GPIO_A_ENABLE_CONFIG_01_0_SCRREG                        GPIO_A_SCR_01_0
+#define GPIO_A_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_A_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_A_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x10024)
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_A_SCR_01_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_A_SCR_01_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_A_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INPUT_01_0
+#define GPIO_A_INPUT_01_0                       MK_ADDR_CONST(0x10028)
+#define GPIO_A_INPUT_01_0_SECURE                        0x0
+#define GPIO_A_INPUT_01_0_DUAL                  0x0
+#define GPIO_A_INPUT_01_0_SCR                   GPIO_A_SCR_01_0
+#define GPIO_A_INPUT_01_0_SCRREG                        GPIO_A_SCR_01_0
+#define GPIO_A_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_A_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_A_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_A_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_A_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_A_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_OUTPUT_CONTROL_01_0
+#define GPIO_A_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1002c)
+#define GPIO_A_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_A_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_A_OUTPUT_CONTROL_01_0_SCR                  GPIO_A_SCR_01_0
+#define GPIO_A_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_A_SCR_01_0
+#define GPIO_A_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_A_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_A_OUTPUT_VALUE_01_0
+#define GPIO_A_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x10030)
+#define GPIO_A_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_A_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_A_OUTPUT_VALUE_01_0_SCR                    GPIO_A_SCR_01_0
+#define GPIO_A_OUTPUT_VALUE_01_0_SCRREG                         GPIO_A_SCR_01_0
+#define GPIO_A_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_A_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INTERRUPT_CLEAR_01_0
+#define GPIO_A_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x10034)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_A_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_A_INTERRUPT_CLEAR_01_0_SCR                         GPIO_A_SCR_01_0
+#define GPIO_A_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_A_SCR_01_0
+#define GPIO_A_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_A_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10038
+
+// Reserved address 0x1003c
+
+// Register GPIO_A_ENABLE_CONFIG_02_0
+#define GPIO_A_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x10040)
+#define GPIO_A_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_A_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_A_ENABLE_CONFIG_02_0_SCR                   GPIO_A_SCR_02_0
+#define GPIO_A_ENABLE_CONFIG_02_0_SCRREG                        GPIO_A_SCR_02_0
+#define GPIO_A_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_A_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_A_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x10044)
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_A_SCR_02_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_A_SCR_02_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_A_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INPUT_02_0
+#define GPIO_A_INPUT_02_0                       MK_ADDR_CONST(0x10048)
+#define GPIO_A_INPUT_02_0_SECURE                        0x0
+#define GPIO_A_INPUT_02_0_DUAL                  0x0
+#define GPIO_A_INPUT_02_0_SCR                   GPIO_A_SCR_02_0
+#define GPIO_A_INPUT_02_0_SCRREG                        GPIO_A_SCR_02_0
+#define GPIO_A_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_A_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_A_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_A_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_A_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_A_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_OUTPUT_CONTROL_02_0
+#define GPIO_A_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1004c)
+#define GPIO_A_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_A_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_A_OUTPUT_CONTROL_02_0_SCR                  GPIO_A_SCR_02_0
+#define GPIO_A_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_A_SCR_02_0
+#define GPIO_A_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_A_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_A_OUTPUT_VALUE_02_0
+#define GPIO_A_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x10050)
+#define GPIO_A_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_A_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_A_OUTPUT_VALUE_02_0_SCR                    GPIO_A_SCR_02_0
+#define GPIO_A_OUTPUT_VALUE_02_0_SCRREG                         GPIO_A_SCR_02_0
+#define GPIO_A_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_A_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INTERRUPT_CLEAR_02_0
+#define GPIO_A_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x10054)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_A_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_A_INTERRUPT_CLEAR_02_0_SCR                         GPIO_A_SCR_02_0
+#define GPIO_A_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_A_SCR_02_0
+#define GPIO_A_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_A_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10058
+
+// Reserved address 0x1005c
+
+// Register GPIO_A_ENABLE_CONFIG_03_0
+#define GPIO_A_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x10060)
+#define GPIO_A_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_A_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_A_ENABLE_CONFIG_03_0_SCR                   GPIO_A_SCR_03_0
+#define GPIO_A_ENABLE_CONFIG_03_0_SCRREG                        GPIO_A_SCR_03_0
+#define GPIO_A_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_A_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_A_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x10064)
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_A_SCR_03_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_A_SCR_03_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_A_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INPUT_03_0
+#define GPIO_A_INPUT_03_0                       MK_ADDR_CONST(0x10068)
+#define GPIO_A_INPUT_03_0_SECURE                        0x0
+#define GPIO_A_INPUT_03_0_DUAL                  0x0
+#define GPIO_A_INPUT_03_0_SCR                   GPIO_A_SCR_03_0
+#define GPIO_A_INPUT_03_0_SCRREG                        GPIO_A_SCR_03_0
+#define GPIO_A_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_A_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_A_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_A_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_A_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_A_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_OUTPUT_CONTROL_03_0
+#define GPIO_A_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1006c)
+#define GPIO_A_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_A_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_A_OUTPUT_CONTROL_03_0_SCR                  GPIO_A_SCR_03_0
+#define GPIO_A_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_A_SCR_03_0
+#define GPIO_A_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_A_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_A_OUTPUT_VALUE_03_0
+#define GPIO_A_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x10070)
+#define GPIO_A_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_A_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_A_OUTPUT_VALUE_03_0_SCR                    GPIO_A_SCR_03_0
+#define GPIO_A_OUTPUT_VALUE_03_0_SCRREG                         GPIO_A_SCR_03_0
+#define GPIO_A_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_A_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INTERRUPT_CLEAR_03_0
+#define GPIO_A_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x10074)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_A_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_A_INTERRUPT_CLEAR_03_0_SCR                         GPIO_A_SCR_03_0
+#define GPIO_A_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_A_SCR_03_0
+#define GPIO_A_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_A_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10078
+
+// Reserved address 0x1007c
+
+// Register GPIO_A_ENABLE_CONFIG_04_0
+#define GPIO_A_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x10080)
+#define GPIO_A_ENABLE_CONFIG_04_0_SECURE                        0x0
+#define GPIO_A_ENABLE_CONFIG_04_0_DUAL                  0x0
+#define GPIO_A_ENABLE_CONFIG_04_0_SCR                   GPIO_A_SCR_04_0
+#define GPIO_A_ENABLE_CONFIG_04_0_SCRREG                        GPIO_A_SCR_04_0
+#define GPIO_A_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
+#define GPIO_A_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
+#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_A_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x10084)
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_A_SCR_04_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_A_SCR_04_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_A_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INPUT_04_0
+#define GPIO_A_INPUT_04_0                       MK_ADDR_CONST(0x10088)
+#define GPIO_A_INPUT_04_0_SECURE                        0x0
+#define GPIO_A_INPUT_04_0_DUAL                  0x0
+#define GPIO_A_INPUT_04_0_SCR                   GPIO_A_SCR_04_0
+#define GPIO_A_INPUT_04_0_SCRREG                        GPIO_A_SCR_04_0
+#define GPIO_A_INPUT_04_0_WORD_COUNT                    0x1
+#define GPIO_A_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_A_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_A_INPUT_04_0_GPIO_IN_RANGE                 0:0
+#define GPIO_A_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_A_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_OUTPUT_CONTROL_04_0
+#define GPIO_A_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1008c)
+#define GPIO_A_OUTPUT_CONTROL_04_0_SECURE                       0x0
+#define GPIO_A_OUTPUT_CONTROL_04_0_DUAL                         0x0
+#define GPIO_A_OUTPUT_CONTROL_04_0_SCR                  GPIO_A_SCR_04_0
+#define GPIO_A_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_A_SCR_04_0
+#define GPIO_A_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
+#define GPIO_A_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_A_OUTPUT_VALUE_04_0
+#define GPIO_A_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x10090)
+#define GPIO_A_OUTPUT_VALUE_04_0_SECURE                         0x0
+#define GPIO_A_OUTPUT_VALUE_04_0_DUAL                   0x0
+#define GPIO_A_OUTPUT_VALUE_04_0_SCR                    GPIO_A_SCR_04_0
+#define GPIO_A_OUTPUT_VALUE_04_0_SCRREG                         GPIO_A_SCR_04_0
+#define GPIO_A_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
+#define GPIO_A_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INTERRUPT_CLEAR_04_0
+#define GPIO_A_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x10094)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_SECURE                      0x0
+#define GPIO_A_INTERRUPT_CLEAR_04_0_DUAL                        0x0
+#define GPIO_A_INTERRUPT_CLEAR_04_0_SCR                         GPIO_A_SCR_04_0
+#define GPIO_A_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_A_SCR_04_0
+#define GPIO_A_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
+#define GPIO_A_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10098
+
+// Reserved address 0x1009c
+
+// Register GPIO_A_ENABLE_CONFIG_05_0
+#define GPIO_A_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x100a0)
+#define GPIO_A_ENABLE_CONFIG_05_0_SECURE                        0x0
+#define GPIO_A_ENABLE_CONFIG_05_0_DUAL                  0x0
+#define GPIO_A_ENABLE_CONFIG_05_0_SCR                   GPIO_A_SCR_05_0
+#define GPIO_A_ENABLE_CONFIG_05_0_SCRREG                        GPIO_A_SCR_05_0
+#define GPIO_A_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
+#define GPIO_A_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
+#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_A_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x100a4)
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_A_SCR_05_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_A_SCR_05_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_A_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INPUT_05_0
+#define GPIO_A_INPUT_05_0                       MK_ADDR_CONST(0x100a8)
+#define GPIO_A_INPUT_05_0_SECURE                        0x0
+#define GPIO_A_INPUT_05_0_DUAL                  0x0
+#define GPIO_A_INPUT_05_0_SCR                   GPIO_A_SCR_05_0
+#define GPIO_A_INPUT_05_0_SCRREG                        GPIO_A_SCR_05_0
+#define GPIO_A_INPUT_05_0_WORD_COUNT                    0x1
+#define GPIO_A_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_A_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_A_INPUT_05_0_GPIO_IN_RANGE                 0:0
+#define GPIO_A_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_A_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_OUTPUT_CONTROL_05_0
+#define GPIO_A_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x100ac)
+#define GPIO_A_OUTPUT_CONTROL_05_0_SECURE                       0x0
+#define GPIO_A_OUTPUT_CONTROL_05_0_DUAL                         0x0
+#define GPIO_A_OUTPUT_CONTROL_05_0_SCR                  GPIO_A_SCR_05_0
+#define GPIO_A_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_A_SCR_05_0
+#define GPIO_A_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
+#define GPIO_A_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_A_OUTPUT_VALUE_05_0
+#define GPIO_A_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x100b0)
+#define GPIO_A_OUTPUT_VALUE_05_0_SECURE                         0x0
+#define GPIO_A_OUTPUT_VALUE_05_0_DUAL                   0x0
+#define GPIO_A_OUTPUT_VALUE_05_0_SCR                    GPIO_A_SCR_05_0
+#define GPIO_A_OUTPUT_VALUE_05_0_SCRREG                         GPIO_A_SCR_05_0
+#define GPIO_A_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
+#define GPIO_A_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INTERRUPT_CLEAR_05_0
+#define GPIO_A_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x100b4)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_SECURE                      0x0
+#define GPIO_A_INTERRUPT_CLEAR_05_0_DUAL                        0x0
+#define GPIO_A_INTERRUPT_CLEAR_05_0_SCR                         GPIO_A_SCR_05_0
+#define GPIO_A_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_A_SCR_05_0
+#define GPIO_A_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
+#define GPIO_A_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x100b8
+
+// Reserved address 0x100bc
+
+// Register GPIO_A_ENABLE_CONFIG_06_0
+#define GPIO_A_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x100c0)
+#define GPIO_A_ENABLE_CONFIG_06_0_SECURE                        0x0
+#define GPIO_A_ENABLE_CONFIG_06_0_DUAL                  0x0
+#define GPIO_A_ENABLE_CONFIG_06_0_SCR                   GPIO_A_SCR_06_0
+#define GPIO_A_ENABLE_CONFIG_06_0_SCRREG                        GPIO_A_SCR_06_0
+#define GPIO_A_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
+#define GPIO_A_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
+#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_A_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x100c4)
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_A_SCR_06_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_A_SCR_06_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_A_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INPUT_06_0
+#define GPIO_A_INPUT_06_0                       MK_ADDR_CONST(0x100c8)
+#define GPIO_A_INPUT_06_0_SECURE                        0x0
+#define GPIO_A_INPUT_06_0_DUAL                  0x0
+#define GPIO_A_INPUT_06_0_SCR                   GPIO_A_SCR_06_0
+#define GPIO_A_INPUT_06_0_SCRREG                        GPIO_A_SCR_06_0
+#define GPIO_A_INPUT_06_0_WORD_COUNT                    0x1
+#define GPIO_A_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_A_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_A_INPUT_06_0_GPIO_IN_RANGE                 0:0
+#define GPIO_A_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_A_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_OUTPUT_CONTROL_06_0
+#define GPIO_A_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x100cc)
+#define GPIO_A_OUTPUT_CONTROL_06_0_SECURE                       0x0
+#define GPIO_A_OUTPUT_CONTROL_06_0_DUAL                         0x0
+#define GPIO_A_OUTPUT_CONTROL_06_0_SCR                  GPIO_A_SCR_06_0
+#define GPIO_A_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_A_SCR_06_0
+#define GPIO_A_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
+#define GPIO_A_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_A_OUTPUT_VALUE_06_0
+#define GPIO_A_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x100d0)
+#define GPIO_A_OUTPUT_VALUE_06_0_SECURE                         0x0
+#define GPIO_A_OUTPUT_VALUE_06_0_DUAL                   0x0
+#define GPIO_A_OUTPUT_VALUE_06_0_SCR                    GPIO_A_SCR_06_0
+#define GPIO_A_OUTPUT_VALUE_06_0_SCRREG                         GPIO_A_SCR_06_0
+#define GPIO_A_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
+#define GPIO_A_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INTERRUPT_CLEAR_06_0
+#define GPIO_A_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x100d4)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_SECURE                      0x0
+#define GPIO_A_INTERRUPT_CLEAR_06_0_DUAL                        0x0
+#define GPIO_A_INTERRUPT_CLEAR_06_0_SCR                         GPIO_A_SCR_06_0
+#define GPIO_A_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_A_SCR_06_0
+#define GPIO_A_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
+#define GPIO_A_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x100d8
+
+// Reserved address 0x100dc
+
+// Register GPIO_A_ENABLE_CONFIG_07_0
+#define GPIO_A_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x100e0)
+#define GPIO_A_ENABLE_CONFIG_07_0_SECURE                        0x0
+#define GPIO_A_ENABLE_CONFIG_07_0_DUAL                  0x0
+#define GPIO_A_ENABLE_CONFIG_07_0_SCR                   GPIO_A_SCR_07_0
+#define GPIO_A_ENABLE_CONFIG_07_0_SCRREG                        GPIO_A_SCR_07_0
+#define GPIO_A_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
+#define GPIO_A_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
+#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_A_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_A_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x100e4)
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_A_SCR_07_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_A_SCR_07_0
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_A_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INPUT_07_0
+#define GPIO_A_INPUT_07_0                       MK_ADDR_CONST(0x100e8)
+#define GPIO_A_INPUT_07_0_SECURE                        0x0
+#define GPIO_A_INPUT_07_0_DUAL                  0x0
+#define GPIO_A_INPUT_07_0_SCR                   GPIO_A_SCR_07_0
+#define GPIO_A_INPUT_07_0_SCRREG                        GPIO_A_SCR_07_0
+#define GPIO_A_INPUT_07_0_WORD_COUNT                    0x1
+#define GPIO_A_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_A_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_A_INPUT_07_0_GPIO_IN_RANGE                 0:0
+#define GPIO_A_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_A_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_A_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_A_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_OUTPUT_CONTROL_07_0
+#define GPIO_A_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x100ec)
+#define GPIO_A_OUTPUT_CONTROL_07_0_SECURE                       0x0
+#define GPIO_A_OUTPUT_CONTROL_07_0_DUAL                         0x0
+#define GPIO_A_OUTPUT_CONTROL_07_0_SCR                  GPIO_A_SCR_07_0
+#define GPIO_A_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_A_SCR_07_0
+#define GPIO_A_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
+#define GPIO_A_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_A_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_A_OUTPUT_VALUE_07_0
+#define GPIO_A_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x100f0)
+#define GPIO_A_OUTPUT_VALUE_07_0_SECURE                         0x0
+#define GPIO_A_OUTPUT_VALUE_07_0_DUAL                   0x0
+#define GPIO_A_OUTPUT_VALUE_07_0_SCR                    GPIO_A_SCR_07_0
+#define GPIO_A_OUTPUT_VALUE_07_0_SCRREG                         GPIO_A_SCR_07_0
+#define GPIO_A_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
+#define GPIO_A_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_A_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INTERRUPT_CLEAR_07_0
+#define GPIO_A_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x100f4)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_SECURE                      0x0
+#define GPIO_A_INTERRUPT_CLEAR_07_0_DUAL                        0x0
+#define GPIO_A_INTERRUPT_CLEAR_07_0_SCR                         GPIO_A_SCR_07_0
+#define GPIO_A_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_A_SCR_07_0
+#define GPIO_A_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
+#define GPIO_A_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_A_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x100f8
+
+// Reserved address 0x100fc
+
+// Register GPIO_A_INTERRUPT_STATUS_G0_0
+#define GPIO_A_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x10100)
+#define GPIO_A_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_A_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_A_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_A_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_A_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_A_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INTERRUPT_STATUS_G1_0
+#define GPIO_A_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x10104)
+#define GPIO_A_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_A_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_A_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_A_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_A_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_A_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INTERRUPT_STATUS_G2_0
+#define GPIO_A_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x10108)
+#define GPIO_A_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_A_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_A_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_A_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_A_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_A_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INTERRUPT_STATUS_G3_0
+#define GPIO_A_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1010c)
+#define GPIO_A_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_A_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_A_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_A_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_A_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_A_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INTERRUPT_STATUS_G4_0
+#define GPIO_A_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x10110)
+#define GPIO_A_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_A_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_A_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_A_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_A_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_A_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INTERRUPT_STATUS_G5_0
+#define GPIO_A_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x10114)
+#define GPIO_A_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_A_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_A_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_A_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_A_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_A_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INTERRUPT_STATUS_G6_0
+#define GPIO_A_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x10118)
+#define GPIO_A_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_A_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_A_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_A_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_A_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_A_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_A_INTERRUPT_STATUS_G7_0
+#define GPIO_A_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1011c)
+#define GPIO_A_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_A_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_A_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_A_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_A_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_A_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_A_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x10120
+
+// Reserved address 0x10124
+
+// Reserved address 0x10128
+
+// Reserved address 0x1012c
+
+// Reserved address 0x10130
+
+// Reserved address 0x10134
+
+// Reserved address 0x10138
+
+// Reserved address 0x1013c
+
+// Reserved address 0x10140
+
+// Reserved address 0x10144
+
+// Reserved address 0x10148
+
+// Reserved address 0x1014c
+
+// Reserved address 0x10150
+
+// Reserved address 0x10154
+
+// Reserved address 0x10158
+
+// Reserved address 0x1015c
+
+// Reserved address 0x10160
+
+// Reserved address 0x10164
+
+// Reserved address 0x10168
+
+// Reserved address 0x1016c
+
+// Reserved address 0x10170
+
+// Reserved address 0x10174
+
+// Reserved address 0x10178
+
+// Reserved address 0x1017c
+
+// Reserved address 0x10180
+
+// Reserved address 0x10184
+
+// Reserved address 0x10188
+
+// Reserved address 0x1018c
+
+// Reserved address 0x10190
+
+// Reserved address 0x10194
+
+// Reserved address 0x10198
+
+// Reserved address 0x1019c
+
+// Reserved address 0x101a0
+
+// Reserved address 0x101a4
+
+// Reserved address 0x101a8
+
+// Reserved address 0x101ac
+
+// Reserved address 0x101b0
+
+// Reserved address 0x101b4
+
+// Reserved address 0x101b8
+
+// Reserved address 0x101bc
+
+// Reserved address 0x101c0
+
+// Reserved address 0x101c4
+
+// Reserved address 0x101c8
+
+// Reserved address 0x101cc
+
+// Reserved address 0x101d0
+
+// Reserved address 0x101d4
+
+// Reserved address 0x101d8
+
+// Reserved address 0x101dc
+
+// Reserved address 0x101e0
+
+// Reserved address 0x101e4
+
+// Reserved address 0x101e8
+
+// Reserved address 0x101ec
+
+// Reserved address 0x101f0
+
+// Reserved address 0x101f4
+
+// Reserved address 0x101f8
+
+// Reserved address 0x101fc
+
+// Register GPIO_AC_ENABLE_CONFIG_00_0
+#define GPIO_AC_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x10200)
+#define GPIO_AC_ENABLE_CONFIG_00_0_SECURE                       0x0
+#define GPIO_AC_ENABLE_CONFIG_00_0_DUAL                         0x0
+#define GPIO_AC_ENABLE_CONFIG_00_0_SCR                  GPIO_AC_SCR_00_0
+#define GPIO_AC_ENABLE_CONFIG_00_0_SCRREG                       GPIO_AC_SCR_00_0
+#define GPIO_AC_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
+#define GPIO_AC_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
+#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AC_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x10204)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_AC_SCR_00_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_AC_SCR_00_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INPUT_00_0
+#define GPIO_AC_INPUT_00_0                      MK_ADDR_CONST(0x10208)
+#define GPIO_AC_INPUT_00_0_SECURE                       0x0
+#define GPIO_AC_INPUT_00_0_DUAL                         0x0
+#define GPIO_AC_INPUT_00_0_SCR                  GPIO_AC_SCR_00_0
+#define GPIO_AC_INPUT_00_0_SCRREG                       GPIO_AC_SCR_00_0
+#define GPIO_AC_INPUT_00_0_WORD_COUNT                   0x1
+#define GPIO_AC_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AC_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_AC_INPUT_00_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AC_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AC_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_OUTPUT_CONTROL_00_0
+#define GPIO_AC_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x1020c)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_SECURE                      0x0
+#define GPIO_AC_OUTPUT_CONTROL_00_0_DUAL                        0x0
+#define GPIO_AC_OUTPUT_CONTROL_00_0_SCR                         GPIO_AC_SCR_00_0
+#define GPIO_AC_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_AC_SCR_00_0
+#define GPIO_AC_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
+#define GPIO_AC_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AC_OUTPUT_VALUE_00_0
+#define GPIO_AC_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x10210)
+#define GPIO_AC_OUTPUT_VALUE_00_0_SECURE                        0x0
+#define GPIO_AC_OUTPUT_VALUE_00_0_DUAL                  0x0
+#define GPIO_AC_OUTPUT_VALUE_00_0_SCR                   GPIO_AC_SCR_00_0
+#define GPIO_AC_OUTPUT_VALUE_00_0_SCRREG                        GPIO_AC_SCR_00_0
+#define GPIO_AC_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
+#define GPIO_AC_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INTERRUPT_CLEAR_00_0
+#define GPIO_AC_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x10214)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_SECURE                     0x0
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_DUAL                       0x0
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_SCR                        GPIO_AC_SCR_00_0
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_AC_SCR_00_0
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10218
+
+// Reserved address 0x1021c
+
+// Register GPIO_AC_ENABLE_CONFIG_01_0
+#define GPIO_AC_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x10220)
+#define GPIO_AC_ENABLE_CONFIG_01_0_SECURE                       0x0
+#define GPIO_AC_ENABLE_CONFIG_01_0_DUAL                         0x0
+#define GPIO_AC_ENABLE_CONFIG_01_0_SCR                  GPIO_AC_SCR_01_0
+#define GPIO_AC_ENABLE_CONFIG_01_0_SCRREG                       GPIO_AC_SCR_01_0
+#define GPIO_AC_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
+#define GPIO_AC_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
+#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AC_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x10224)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_AC_SCR_01_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_AC_SCR_01_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INPUT_01_0
+#define GPIO_AC_INPUT_01_0                      MK_ADDR_CONST(0x10228)
+#define GPIO_AC_INPUT_01_0_SECURE                       0x0
+#define GPIO_AC_INPUT_01_0_DUAL                         0x0
+#define GPIO_AC_INPUT_01_0_SCR                  GPIO_AC_SCR_01_0
+#define GPIO_AC_INPUT_01_0_SCRREG                       GPIO_AC_SCR_01_0
+#define GPIO_AC_INPUT_01_0_WORD_COUNT                   0x1
+#define GPIO_AC_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AC_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_AC_INPUT_01_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AC_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AC_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_OUTPUT_CONTROL_01_0
+#define GPIO_AC_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x1022c)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_SECURE                      0x0
+#define GPIO_AC_OUTPUT_CONTROL_01_0_DUAL                        0x0
+#define GPIO_AC_OUTPUT_CONTROL_01_0_SCR                         GPIO_AC_SCR_01_0
+#define GPIO_AC_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_AC_SCR_01_0
+#define GPIO_AC_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
+#define GPIO_AC_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AC_OUTPUT_VALUE_01_0
+#define GPIO_AC_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x10230)
+#define GPIO_AC_OUTPUT_VALUE_01_0_SECURE                        0x0
+#define GPIO_AC_OUTPUT_VALUE_01_0_DUAL                  0x0
+#define GPIO_AC_OUTPUT_VALUE_01_0_SCR                   GPIO_AC_SCR_01_0
+#define GPIO_AC_OUTPUT_VALUE_01_0_SCRREG                        GPIO_AC_SCR_01_0
+#define GPIO_AC_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
+#define GPIO_AC_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INTERRUPT_CLEAR_01_0
+#define GPIO_AC_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x10234)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_SECURE                     0x0
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_DUAL                       0x0
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_SCR                        GPIO_AC_SCR_01_0
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_AC_SCR_01_0
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10238
+
+// Reserved address 0x1023c
+
+// Register GPIO_AC_ENABLE_CONFIG_02_0
+#define GPIO_AC_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x10240)
+#define GPIO_AC_ENABLE_CONFIG_02_0_SECURE                       0x0
+#define GPIO_AC_ENABLE_CONFIG_02_0_DUAL                         0x0
+#define GPIO_AC_ENABLE_CONFIG_02_0_SCR                  GPIO_AC_SCR_02_0
+#define GPIO_AC_ENABLE_CONFIG_02_0_SCRREG                       GPIO_AC_SCR_02_0
+#define GPIO_AC_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
+#define GPIO_AC_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
+#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AC_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x10244)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_AC_SCR_02_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_AC_SCR_02_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INPUT_02_0
+#define GPIO_AC_INPUT_02_0                      MK_ADDR_CONST(0x10248)
+#define GPIO_AC_INPUT_02_0_SECURE                       0x0
+#define GPIO_AC_INPUT_02_0_DUAL                         0x0
+#define GPIO_AC_INPUT_02_0_SCR                  GPIO_AC_SCR_02_0
+#define GPIO_AC_INPUT_02_0_SCRREG                       GPIO_AC_SCR_02_0
+#define GPIO_AC_INPUT_02_0_WORD_COUNT                   0x1
+#define GPIO_AC_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AC_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_AC_INPUT_02_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AC_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AC_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_OUTPUT_CONTROL_02_0
+#define GPIO_AC_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x1024c)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_SECURE                      0x0
+#define GPIO_AC_OUTPUT_CONTROL_02_0_DUAL                        0x0
+#define GPIO_AC_OUTPUT_CONTROL_02_0_SCR                         GPIO_AC_SCR_02_0
+#define GPIO_AC_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_AC_SCR_02_0
+#define GPIO_AC_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
+#define GPIO_AC_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AC_OUTPUT_VALUE_02_0
+#define GPIO_AC_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x10250)
+#define GPIO_AC_OUTPUT_VALUE_02_0_SECURE                        0x0
+#define GPIO_AC_OUTPUT_VALUE_02_0_DUAL                  0x0
+#define GPIO_AC_OUTPUT_VALUE_02_0_SCR                   GPIO_AC_SCR_02_0
+#define GPIO_AC_OUTPUT_VALUE_02_0_SCRREG                        GPIO_AC_SCR_02_0
+#define GPIO_AC_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
+#define GPIO_AC_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INTERRUPT_CLEAR_02_0
+#define GPIO_AC_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x10254)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_SECURE                     0x0
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_DUAL                       0x0
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_SCR                        GPIO_AC_SCR_02_0
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_AC_SCR_02_0
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10258
+
+// Reserved address 0x1025c
+
+// Register GPIO_AC_ENABLE_CONFIG_03_0
+#define GPIO_AC_ENABLE_CONFIG_03_0                      MK_ADDR_CONST(0x10260)
+#define GPIO_AC_ENABLE_CONFIG_03_0_SECURE                       0x0
+#define GPIO_AC_ENABLE_CONFIG_03_0_DUAL                         0x0
+#define GPIO_AC_ENABLE_CONFIG_03_0_SCR                  GPIO_AC_SCR_03_0
+#define GPIO_AC_ENABLE_CONFIG_03_0_SCRREG                       GPIO_AC_SCR_03_0
+#define GPIO_AC_ENABLE_CONFIG_03_0_WORD_COUNT                   0x1
+#define GPIO_AC_ENABLE_CONFIG_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_03_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_RANGE                 1:1
+#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AC_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0                 MK_ADDR_CONST(0x10264)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_SECURE                  0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DUAL                    0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_SCR                     GPIO_AC_SCR_03_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_SCRREG                  GPIO_AC_SCR_03_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                      0x1
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INPUT_03_0
+#define GPIO_AC_INPUT_03_0                      MK_ADDR_CONST(0x10268)
+#define GPIO_AC_INPUT_03_0_SECURE                       0x0
+#define GPIO_AC_INPUT_03_0_DUAL                         0x0
+#define GPIO_AC_INPUT_03_0_SCR                  GPIO_AC_SCR_03_0
+#define GPIO_AC_INPUT_03_0_SCRREG                       GPIO_AC_SCR_03_0
+#define GPIO_AC_INPUT_03_0_WORD_COUNT                   0x1
+#define GPIO_AC_INPUT_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_03_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_INPUT_03_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_03_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_03_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AC_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_AC_INPUT_03_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AC_INPUT_03_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_03_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_03_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AC_INPUT_03_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_03_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_03_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_OUTPUT_CONTROL_03_0
+#define GPIO_AC_OUTPUT_CONTROL_03_0                     MK_ADDR_CONST(0x1026c)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_SECURE                      0x0
+#define GPIO_AC_OUTPUT_CONTROL_03_0_DUAL                        0x0
+#define GPIO_AC_OUTPUT_CONTROL_03_0_SCR                         GPIO_AC_SCR_03_0
+#define GPIO_AC_OUTPUT_CONTROL_03_0_SCRREG                      GPIO_AC_SCR_03_0
+#define GPIO_AC_OUTPUT_CONTROL_03_0_WORD_COUNT                  0x1
+#define GPIO_AC_OUTPUT_CONTROL_03_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AC_OUTPUT_VALUE_03_0
+#define GPIO_AC_OUTPUT_VALUE_03_0                       MK_ADDR_CONST(0x10270)
+#define GPIO_AC_OUTPUT_VALUE_03_0_SECURE                        0x0
+#define GPIO_AC_OUTPUT_VALUE_03_0_DUAL                  0x0
+#define GPIO_AC_OUTPUT_VALUE_03_0_SCR                   GPIO_AC_SCR_03_0
+#define GPIO_AC_OUTPUT_VALUE_03_0_SCRREG                        GPIO_AC_SCR_03_0
+#define GPIO_AC_OUTPUT_VALUE_03_0_WORD_COUNT                    0x1
+#define GPIO_AC_OUTPUT_VALUE_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_03_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_03_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INTERRUPT_CLEAR_03_0
+#define GPIO_AC_INTERRUPT_CLEAR_03_0                    MK_ADDR_CONST(0x10274)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_SECURE                     0x0
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_DUAL                       0x0
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_SCR                        GPIO_AC_SCR_03_0
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_SCRREG                     GPIO_AC_SCR_03_0
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_WORD_COUNT                         0x1
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10278
+
+// Reserved address 0x1027c
+
+// Register GPIO_AC_ENABLE_CONFIG_04_0
+#define GPIO_AC_ENABLE_CONFIG_04_0                      MK_ADDR_CONST(0x10280)
+#define GPIO_AC_ENABLE_CONFIG_04_0_SECURE                       0x0
+#define GPIO_AC_ENABLE_CONFIG_04_0_DUAL                         0x0
+#define GPIO_AC_ENABLE_CONFIG_04_0_SCR                  GPIO_AC_SCR_04_0
+#define GPIO_AC_ENABLE_CONFIG_04_0_SCRREG                       GPIO_AC_SCR_04_0
+#define GPIO_AC_ENABLE_CONFIG_04_0_WORD_COUNT                   0x1
+#define GPIO_AC_ENABLE_CONFIG_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_04_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_RANGE                 1:1
+#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AC_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0                 MK_ADDR_CONST(0x10284)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_SECURE                  0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DUAL                    0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_SCR                     GPIO_AC_SCR_04_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_SCRREG                  GPIO_AC_SCR_04_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                      0x1
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INPUT_04_0
+#define GPIO_AC_INPUT_04_0                      MK_ADDR_CONST(0x10288)
+#define GPIO_AC_INPUT_04_0_SECURE                       0x0
+#define GPIO_AC_INPUT_04_0_DUAL                         0x0
+#define GPIO_AC_INPUT_04_0_SCR                  GPIO_AC_SCR_04_0
+#define GPIO_AC_INPUT_04_0_SCRREG                       GPIO_AC_SCR_04_0
+#define GPIO_AC_INPUT_04_0_WORD_COUNT                   0x1
+#define GPIO_AC_INPUT_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_04_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_INPUT_04_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_04_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_04_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AC_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_AC_INPUT_04_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AC_INPUT_04_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_04_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_04_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AC_INPUT_04_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_04_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_04_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_OUTPUT_CONTROL_04_0
+#define GPIO_AC_OUTPUT_CONTROL_04_0                     MK_ADDR_CONST(0x1028c)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_SECURE                      0x0
+#define GPIO_AC_OUTPUT_CONTROL_04_0_DUAL                        0x0
+#define GPIO_AC_OUTPUT_CONTROL_04_0_SCR                         GPIO_AC_SCR_04_0
+#define GPIO_AC_OUTPUT_CONTROL_04_0_SCRREG                      GPIO_AC_SCR_04_0
+#define GPIO_AC_OUTPUT_CONTROL_04_0_WORD_COUNT                  0x1
+#define GPIO_AC_OUTPUT_CONTROL_04_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AC_OUTPUT_VALUE_04_0
+#define GPIO_AC_OUTPUT_VALUE_04_0                       MK_ADDR_CONST(0x10290)
+#define GPIO_AC_OUTPUT_VALUE_04_0_SECURE                        0x0
+#define GPIO_AC_OUTPUT_VALUE_04_0_DUAL                  0x0
+#define GPIO_AC_OUTPUT_VALUE_04_0_SCR                   GPIO_AC_SCR_04_0
+#define GPIO_AC_OUTPUT_VALUE_04_0_SCRREG                        GPIO_AC_SCR_04_0
+#define GPIO_AC_OUTPUT_VALUE_04_0_WORD_COUNT                    0x1
+#define GPIO_AC_OUTPUT_VALUE_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_04_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_04_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INTERRUPT_CLEAR_04_0
+#define GPIO_AC_INTERRUPT_CLEAR_04_0                    MK_ADDR_CONST(0x10294)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_SECURE                     0x0
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_DUAL                       0x0
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_SCR                        GPIO_AC_SCR_04_0
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_SCRREG                     GPIO_AC_SCR_04_0
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_WORD_COUNT                         0x1
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10298
+
+// Reserved address 0x1029c
+
+// Register GPIO_AC_ENABLE_CONFIG_05_0
+#define GPIO_AC_ENABLE_CONFIG_05_0                      MK_ADDR_CONST(0x102a0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_SECURE                       0x0
+#define GPIO_AC_ENABLE_CONFIG_05_0_DUAL                         0x0
+#define GPIO_AC_ENABLE_CONFIG_05_0_SCR                  GPIO_AC_SCR_05_0
+#define GPIO_AC_ENABLE_CONFIG_05_0_SCRREG                       GPIO_AC_SCR_05_0
+#define GPIO_AC_ENABLE_CONFIG_05_0_WORD_COUNT                   0x1
+#define GPIO_AC_ENABLE_CONFIG_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_05_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_RANGE                 1:1
+#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AC_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0                 MK_ADDR_CONST(0x102a4)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_SECURE                  0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DUAL                    0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_SCR                     GPIO_AC_SCR_05_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_SCRREG                  GPIO_AC_SCR_05_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                      0x1
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INPUT_05_0
+#define GPIO_AC_INPUT_05_0                      MK_ADDR_CONST(0x102a8)
+#define GPIO_AC_INPUT_05_0_SECURE                       0x0
+#define GPIO_AC_INPUT_05_0_DUAL                         0x0
+#define GPIO_AC_INPUT_05_0_SCR                  GPIO_AC_SCR_05_0
+#define GPIO_AC_INPUT_05_0_SCRREG                       GPIO_AC_SCR_05_0
+#define GPIO_AC_INPUT_05_0_WORD_COUNT                   0x1
+#define GPIO_AC_INPUT_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_05_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_INPUT_05_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_05_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_05_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AC_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_AC_INPUT_05_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AC_INPUT_05_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_05_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_05_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AC_INPUT_05_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_05_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_05_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_OUTPUT_CONTROL_05_0
+#define GPIO_AC_OUTPUT_CONTROL_05_0                     MK_ADDR_CONST(0x102ac)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_SECURE                      0x0
+#define GPIO_AC_OUTPUT_CONTROL_05_0_DUAL                        0x0
+#define GPIO_AC_OUTPUT_CONTROL_05_0_SCR                         GPIO_AC_SCR_05_0
+#define GPIO_AC_OUTPUT_CONTROL_05_0_SCRREG                      GPIO_AC_SCR_05_0
+#define GPIO_AC_OUTPUT_CONTROL_05_0_WORD_COUNT                  0x1
+#define GPIO_AC_OUTPUT_CONTROL_05_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AC_OUTPUT_VALUE_05_0
+#define GPIO_AC_OUTPUT_VALUE_05_0                       MK_ADDR_CONST(0x102b0)
+#define GPIO_AC_OUTPUT_VALUE_05_0_SECURE                        0x0
+#define GPIO_AC_OUTPUT_VALUE_05_0_DUAL                  0x0
+#define GPIO_AC_OUTPUT_VALUE_05_0_SCR                   GPIO_AC_SCR_05_0
+#define GPIO_AC_OUTPUT_VALUE_05_0_SCRREG                        GPIO_AC_SCR_05_0
+#define GPIO_AC_OUTPUT_VALUE_05_0_WORD_COUNT                    0x1
+#define GPIO_AC_OUTPUT_VALUE_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_05_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_05_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INTERRUPT_CLEAR_05_0
+#define GPIO_AC_INTERRUPT_CLEAR_05_0                    MK_ADDR_CONST(0x102b4)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_SECURE                     0x0
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_DUAL                       0x0
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_SCR                        GPIO_AC_SCR_05_0
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_SCRREG                     GPIO_AC_SCR_05_0
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_WORD_COUNT                         0x1
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x102b8
+
+// Reserved address 0x102bc
+
+// Register GPIO_AC_ENABLE_CONFIG_06_0
+#define GPIO_AC_ENABLE_CONFIG_06_0                      MK_ADDR_CONST(0x102c0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_SECURE                       0x0
+#define GPIO_AC_ENABLE_CONFIG_06_0_DUAL                         0x0
+#define GPIO_AC_ENABLE_CONFIG_06_0_SCR                  GPIO_AC_SCR_06_0
+#define GPIO_AC_ENABLE_CONFIG_06_0_SCRREG                       GPIO_AC_SCR_06_0
+#define GPIO_AC_ENABLE_CONFIG_06_0_WORD_COUNT                   0x1
+#define GPIO_AC_ENABLE_CONFIG_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_06_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_RANGE                 1:1
+#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AC_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0                 MK_ADDR_CONST(0x102c4)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_SECURE                  0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DUAL                    0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_SCR                     GPIO_AC_SCR_06_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_SCRREG                  GPIO_AC_SCR_06_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                      0x1
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INPUT_06_0
+#define GPIO_AC_INPUT_06_0                      MK_ADDR_CONST(0x102c8)
+#define GPIO_AC_INPUT_06_0_SECURE                       0x0
+#define GPIO_AC_INPUT_06_0_DUAL                         0x0
+#define GPIO_AC_INPUT_06_0_SCR                  GPIO_AC_SCR_06_0
+#define GPIO_AC_INPUT_06_0_SCRREG                       GPIO_AC_SCR_06_0
+#define GPIO_AC_INPUT_06_0_WORD_COUNT                   0x1
+#define GPIO_AC_INPUT_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_06_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_INPUT_06_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_06_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_06_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AC_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_AC_INPUT_06_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AC_INPUT_06_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_06_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_06_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AC_INPUT_06_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_06_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_06_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_OUTPUT_CONTROL_06_0
+#define GPIO_AC_OUTPUT_CONTROL_06_0                     MK_ADDR_CONST(0x102cc)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_SECURE                      0x0
+#define GPIO_AC_OUTPUT_CONTROL_06_0_DUAL                        0x0
+#define GPIO_AC_OUTPUT_CONTROL_06_0_SCR                         GPIO_AC_SCR_06_0
+#define GPIO_AC_OUTPUT_CONTROL_06_0_SCRREG                      GPIO_AC_SCR_06_0
+#define GPIO_AC_OUTPUT_CONTROL_06_0_WORD_COUNT                  0x1
+#define GPIO_AC_OUTPUT_CONTROL_06_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AC_OUTPUT_VALUE_06_0
+#define GPIO_AC_OUTPUT_VALUE_06_0                       MK_ADDR_CONST(0x102d0)
+#define GPIO_AC_OUTPUT_VALUE_06_0_SECURE                        0x0
+#define GPIO_AC_OUTPUT_VALUE_06_0_DUAL                  0x0
+#define GPIO_AC_OUTPUT_VALUE_06_0_SCR                   GPIO_AC_SCR_06_0
+#define GPIO_AC_OUTPUT_VALUE_06_0_SCRREG                        GPIO_AC_SCR_06_0
+#define GPIO_AC_OUTPUT_VALUE_06_0_WORD_COUNT                    0x1
+#define GPIO_AC_OUTPUT_VALUE_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_06_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_06_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INTERRUPT_CLEAR_06_0
+#define GPIO_AC_INTERRUPT_CLEAR_06_0                    MK_ADDR_CONST(0x102d4)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_SECURE                     0x0
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_DUAL                       0x0
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_SCR                        GPIO_AC_SCR_06_0
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_SCRREG                     GPIO_AC_SCR_06_0
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_WORD_COUNT                         0x1
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x102d8
+
+// Reserved address 0x102dc
+
+// Register GPIO_AC_ENABLE_CONFIG_07_0
+#define GPIO_AC_ENABLE_CONFIG_07_0                      MK_ADDR_CONST(0x102e0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_SECURE                       0x0
+#define GPIO_AC_ENABLE_CONFIG_07_0_DUAL                         0x0
+#define GPIO_AC_ENABLE_CONFIG_07_0_SCR                  GPIO_AC_SCR_07_0
+#define GPIO_AC_ENABLE_CONFIG_07_0_SCRREG                       GPIO_AC_SCR_07_0
+#define GPIO_AC_ENABLE_CONFIG_07_0_WORD_COUNT                   0x1
+#define GPIO_AC_ENABLE_CONFIG_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_07_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_RANGE                 1:1
+#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AC_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AC_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0                 MK_ADDR_CONST(0x102e4)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_SECURE                  0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DUAL                    0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_SCR                     GPIO_AC_SCR_07_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_SCRREG                  GPIO_AC_SCR_07_0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                      0x1
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AC_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INPUT_07_0
+#define GPIO_AC_INPUT_07_0                      MK_ADDR_CONST(0x102e8)
+#define GPIO_AC_INPUT_07_0_SECURE                       0x0
+#define GPIO_AC_INPUT_07_0_DUAL                         0x0
+#define GPIO_AC_INPUT_07_0_SCR                  GPIO_AC_SCR_07_0
+#define GPIO_AC_INPUT_07_0_SCRREG                       GPIO_AC_SCR_07_0
+#define GPIO_AC_INPUT_07_0_WORD_COUNT                   0x1
+#define GPIO_AC_INPUT_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_07_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_INPUT_07_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_07_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_07_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AC_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_AC_INPUT_07_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AC_INPUT_07_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_07_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AC_INPUT_07_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AC_INPUT_07_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_07_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_07_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_OUTPUT_CONTROL_07_0
+#define GPIO_AC_OUTPUT_CONTROL_07_0                     MK_ADDR_CONST(0x102ec)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_SECURE                      0x0
+#define GPIO_AC_OUTPUT_CONTROL_07_0_DUAL                        0x0
+#define GPIO_AC_OUTPUT_CONTROL_07_0_SCR                         GPIO_AC_SCR_07_0
+#define GPIO_AC_OUTPUT_CONTROL_07_0_SCRREG                      GPIO_AC_SCR_07_0
+#define GPIO_AC_OUTPUT_CONTROL_07_0_WORD_COUNT                  0x1
+#define GPIO_AC_OUTPUT_CONTROL_07_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AC_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AC_OUTPUT_VALUE_07_0
+#define GPIO_AC_OUTPUT_VALUE_07_0                       MK_ADDR_CONST(0x102f0)
+#define GPIO_AC_OUTPUT_VALUE_07_0_SECURE                        0x0
+#define GPIO_AC_OUTPUT_VALUE_07_0_DUAL                  0x0
+#define GPIO_AC_OUTPUT_VALUE_07_0_SCR                   GPIO_AC_SCR_07_0
+#define GPIO_AC_OUTPUT_VALUE_07_0_SCRREG                        GPIO_AC_SCR_07_0
+#define GPIO_AC_OUTPUT_VALUE_07_0_WORD_COUNT                    0x1
+#define GPIO_AC_OUTPUT_VALUE_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_07_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_07_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AC_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INTERRUPT_CLEAR_07_0
+#define GPIO_AC_INTERRUPT_CLEAR_07_0                    MK_ADDR_CONST(0x102f4)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_SECURE                     0x0
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_DUAL                       0x0
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_SCR                        GPIO_AC_SCR_07_0
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_SCRREG                     GPIO_AC_SCR_07_0
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_WORD_COUNT                         0x1
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AC_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x102f8
+
+// Reserved address 0x102fc
+
+// Register GPIO_AC_INTERRUPT_STATUS_G0_0
+#define GPIO_AC_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x10300)
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_SECURE                    0x0
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_DUAL                      0x0
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_SCR                       0
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_SCRREG                    0
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INTERRUPT_STATUS_G1_0
+#define GPIO_AC_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x10304)
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_SECURE                    0x0
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_DUAL                      0x0
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_SCR                       0
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_SCRREG                    0
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INTERRUPT_STATUS_G2_0
+#define GPIO_AC_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x10308)
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_SECURE                    0x0
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_DUAL                      0x0
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_SCR                       0
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_SCRREG                    0
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INTERRUPT_STATUS_G3_0
+#define GPIO_AC_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x1030c)
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_SECURE                    0x0
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_DUAL                      0x0
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_SCR                       0
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_SCRREG                    0
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INTERRUPT_STATUS_G4_0
+#define GPIO_AC_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x10310)
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_SECURE                    0x0
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_DUAL                      0x0
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_SCR                       0
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_SCRREG                    0
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INTERRUPT_STATUS_G5_0
+#define GPIO_AC_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x10314)
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_SECURE                    0x0
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_DUAL                      0x0
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_SCR                       0
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_SCRREG                    0
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INTERRUPT_STATUS_G6_0
+#define GPIO_AC_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x10318)
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_SECURE                    0x0
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_DUAL                      0x0
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_SCR                       0
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_SCRREG                    0
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AC_INTERRUPT_STATUS_G7_0
+#define GPIO_AC_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x1031c)
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_SECURE                    0x0
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_DUAL                      0x0
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_SCR                       0
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_SCRREG                    0
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AC_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x10320
+
+// Reserved address 0x10324
+
+// Reserved address 0x10328
+
+// Reserved address 0x1032c
+
+// Reserved address 0x10330
+
+// Reserved address 0x10334
+
+// Reserved address 0x10338
+
+// Reserved address 0x1033c
+
+// Reserved address 0x10340
+
+// Reserved address 0x10344
+
+// Reserved address 0x10348
+
+// Reserved address 0x1034c
+
+// Reserved address 0x10350
+
+// Reserved address 0x10354
+
+// Reserved address 0x10358
+
+// Reserved address 0x1035c
+
+// Reserved address 0x10360
+
+// Reserved address 0x10364
+
+// Reserved address 0x10368
+
+// Reserved address 0x1036c
+
+// Reserved address 0x10370
+
+// Reserved address 0x10374
+
+// Reserved address 0x10378
+
+// Reserved address 0x1037c
+
+// Reserved address 0x10380
+
+// Reserved address 0x10384
+
+// Reserved address 0x10388
+
+// Reserved address 0x1038c
+
+// Reserved address 0x10390
+
+// Reserved address 0x10394
+
+// Reserved address 0x10398
+
+// Reserved address 0x1039c
+
+// Reserved address 0x103a0
+
+// Reserved address 0x103a4
+
+// Reserved address 0x103a8
+
+// Reserved address 0x103ac
+
+// Reserved address 0x103b0
+
+// Reserved address 0x103b4
+
+// Reserved address 0x103b8
+
+// Reserved address 0x103bc
+
+// Reserved address 0x103c0
+
+// Reserved address 0x103c4
+
+// Reserved address 0x103c8
+
+// Reserved address 0x103cc
+
+// Reserved address 0x103d0
+
+// Reserved address 0x103d4
+
+// Reserved address 0x103d8
+
+// Reserved address 0x103dc
+
+// Reserved address 0x103e0
+
+// Reserved address 0x103e4
+
+// Reserved address 0x103e8
+
+// Reserved address 0x103ec
+
+// Reserved address 0x103f0
+
+// Reserved address 0x103f4
+
+// Reserved address 0x103f8
+
+// Reserved address 0x103fc
+
+// Register GPIO_AD_ENABLE_CONFIG_00_0
+#define GPIO_AD_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x10400)
+#define GPIO_AD_ENABLE_CONFIG_00_0_SECURE                       0x0
+#define GPIO_AD_ENABLE_CONFIG_00_0_DUAL                         0x0
+#define GPIO_AD_ENABLE_CONFIG_00_0_SCR                  GPIO_AD_SCR_00_0
+#define GPIO_AD_ENABLE_CONFIG_00_0_SCRREG                       GPIO_AD_SCR_00_0
+#define GPIO_AD_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
+#define GPIO_AD_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AD_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AD_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
+#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AD_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x10404)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_AD_SCR_00_0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_AD_SCR_00_0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INPUT_00_0
+#define GPIO_AD_INPUT_00_0                      MK_ADDR_CONST(0x10408)
+#define GPIO_AD_INPUT_00_0_SECURE                       0x0
+#define GPIO_AD_INPUT_00_0_DUAL                         0x0
+#define GPIO_AD_INPUT_00_0_SCR                  GPIO_AD_SCR_00_0
+#define GPIO_AD_INPUT_00_0_SCRREG                       GPIO_AD_SCR_00_0
+#define GPIO_AD_INPUT_00_0_WORD_COUNT                   0x1
+#define GPIO_AD_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AD_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AD_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AD_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_AD_INPUT_00_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AD_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AD_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AD_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AD_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_OUTPUT_CONTROL_00_0
+#define GPIO_AD_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x1040c)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_SECURE                      0x0
+#define GPIO_AD_OUTPUT_CONTROL_00_0_DUAL                        0x0
+#define GPIO_AD_OUTPUT_CONTROL_00_0_SCR                         GPIO_AD_SCR_00_0
+#define GPIO_AD_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_AD_SCR_00_0
+#define GPIO_AD_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
+#define GPIO_AD_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AD_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AD_OUTPUT_VALUE_00_0
+#define GPIO_AD_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x10410)
+#define GPIO_AD_OUTPUT_VALUE_00_0_SECURE                        0x0
+#define GPIO_AD_OUTPUT_VALUE_00_0_DUAL                  0x0
+#define GPIO_AD_OUTPUT_VALUE_00_0_SCR                   GPIO_AD_SCR_00_0
+#define GPIO_AD_OUTPUT_VALUE_00_0_SCRREG                        GPIO_AD_SCR_00_0
+#define GPIO_AD_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
+#define GPIO_AD_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INTERRUPT_CLEAR_00_0
+#define GPIO_AD_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x10414)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_SECURE                     0x0
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_DUAL                       0x0
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_SCR                        GPIO_AD_SCR_00_0
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_AD_SCR_00_0
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AD_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10418
+
+// Reserved address 0x1041c
+
+// Register GPIO_AD_ENABLE_CONFIG_01_0
+#define GPIO_AD_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x10420)
+#define GPIO_AD_ENABLE_CONFIG_01_0_SECURE                       0x0
+#define GPIO_AD_ENABLE_CONFIG_01_0_DUAL                         0x0
+#define GPIO_AD_ENABLE_CONFIG_01_0_SCR                  GPIO_AD_SCR_01_0
+#define GPIO_AD_ENABLE_CONFIG_01_0_SCRREG                       GPIO_AD_SCR_01_0
+#define GPIO_AD_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
+#define GPIO_AD_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AD_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AD_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
+#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AD_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x10424)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_AD_SCR_01_0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_AD_SCR_01_0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INPUT_01_0
+#define GPIO_AD_INPUT_01_0                      MK_ADDR_CONST(0x10428)
+#define GPIO_AD_INPUT_01_0_SECURE                       0x0
+#define GPIO_AD_INPUT_01_0_DUAL                         0x0
+#define GPIO_AD_INPUT_01_0_SCR                  GPIO_AD_SCR_01_0
+#define GPIO_AD_INPUT_01_0_SCRREG                       GPIO_AD_SCR_01_0
+#define GPIO_AD_INPUT_01_0_WORD_COUNT                   0x1
+#define GPIO_AD_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AD_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AD_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AD_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_AD_INPUT_01_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AD_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AD_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AD_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AD_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_OUTPUT_CONTROL_01_0
+#define GPIO_AD_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x1042c)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_SECURE                      0x0
+#define GPIO_AD_OUTPUT_CONTROL_01_0_DUAL                        0x0
+#define GPIO_AD_OUTPUT_CONTROL_01_0_SCR                         GPIO_AD_SCR_01_0
+#define GPIO_AD_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_AD_SCR_01_0
+#define GPIO_AD_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
+#define GPIO_AD_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AD_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AD_OUTPUT_VALUE_01_0
+#define GPIO_AD_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x10430)
+#define GPIO_AD_OUTPUT_VALUE_01_0_SECURE                        0x0
+#define GPIO_AD_OUTPUT_VALUE_01_0_DUAL                  0x0
+#define GPIO_AD_OUTPUT_VALUE_01_0_SCR                   GPIO_AD_SCR_01_0
+#define GPIO_AD_OUTPUT_VALUE_01_0_SCRREG                        GPIO_AD_SCR_01_0
+#define GPIO_AD_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
+#define GPIO_AD_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INTERRUPT_CLEAR_01_0
+#define GPIO_AD_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x10434)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_SECURE                     0x0
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_DUAL                       0x0
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_SCR                        GPIO_AD_SCR_01_0
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_AD_SCR_01_0
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AD_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10438
+
+// Reserved address 0x1043c
+
+// Register GPIO_AD_ENABLE_CONFIG_02_0
+#define GPIO_AD_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x10440)
+#define GPIO_AD_ENABLE_CONFIG_02_0_SECURE                       0x0
+#define GPIO_AD_ENABLE_CONFIG_02_0_DUAL                         0x0
+#define GPIO_AD_ENABLE_CONFIG_02_0_SCR                  GPIO_AD_SCR_02_0
+#define GPIO_AD_ENABLE_CONFIG_02_0_SCRREG                       GPIO_AD_SCR_02_0
+#define GPIO_AD_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
+#define GPIO_AD_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AD_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AD_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
+#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AD_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x10444)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_AD_SCR_02_0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_AD_SCR_02_0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INPUT_02_0
+#define GPIO_AD_INPUT_02_0                      MK_ADDR_CONST(0x10448)
+#define GPIO_AD_INPUT_02_0_SECURE                       0x0
+#define GPIO_AD_INPUT_02_0_DUAL                         0x0
+#define GPIO_AD_INPUT_02_0_SCR                  GPIO_AD_SCR_02_0
+#define GPIO_AD_INPUT_02_0_SCRREG                       GPIO_AD_SCR_02_0
+#define GPIO_AD_INPUT_02_0_WORD_COUNT                   0x1
+#define GPIO_AD_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AD_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AD_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AD_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_AD_INPUT_02_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AD_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AD_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AD_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AD_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_OUTPUT_CONTROL_02_0
+#define GPIO_AD_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x1044c)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_SECURE                      0x0
+#define GPIO_AD_OUTPUT_CONTROL_02_0_DUAL                        0x0
+#define GPIO_AD_OUTPUT_CONTROL_02_0_SCR                         GPIO_AD_SCR_02_0
+#define GPIO_AD_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_AD_SCR_02_0
+#define GPIO_AD_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
+#define GPIO_AD_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AD_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AD_OUTPUT_VALUE_02_0
+#define GPIO_AD_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x10450)
+#define GPIO_AD_OUTPUT_VALUE_02_0_SECURE                        0x0
+#define GPIO_AD_OUTPUT_VALUE_02_0_DUAL                  0x0
+#define GPIO_AD_OUTPUT_VALUE_02_0_SCR                   GPIO_AD_SCR_02_0
+#define GPIO_AD_OUTPUT_VALUE_02_0_SCRREG                        GPIO_AD_SCR_02_0
+#define GPIO_AD_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
+#define GPIO_AD_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INTERRUPT_CLEAR_02_0
+#define GPIO_AD_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x10454)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_SECURE                     0x0
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_DUAL                       0x0
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_SCR                        GPIO_AD_SCR_02_0
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_AD_SCR_02_0
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AD_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10458
+
+// Reserved address 0x1045c
+
+// Register GPIO_AD_ENABLE_CONFIG_03_0
+#define GPIO_AD_ENABLE_CONFIG_03_0                      MK_ADDR_CONST(0x10460)
+#define GPIO_AD_ENABLE_CONFIG_03_0_SECURE                       0x0
+#define GPIO_AD_ENABLE_CONFIG_03_0_DUAL                         0x0
+#define GPIO_AD_ENABLE_CONFIG_03_0_SCR                  GPIO_AD_SCR_03_0
+#define GPIO_AD_ENABLE_CONFIG_03_0_SCRREG                       GPIO_AD_SCR_03_0
+#define GPIO_AD_ENABLE_CONFIG_03_0_WORD_COUNT                   0x1
+#define GPIO_AD_ENABLE_CONFIG_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AD_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AD_ENABLE_CONFIG_03_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_RANGE                 1:1
+#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AD_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AD_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0                 MK_ADDR_CONST(0x10464)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_SECURE                  0x0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DUAL                    0x0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_SCR                     GPIO_AD_SCR_03_0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_SCRREG                  GPIO_AD_SCR_03_0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                      0x1
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AD_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INPUT_03_0
+#define GPIO_AD_INPUT_03_0                      MK_ADDR_CONST(0x10468)
+#define GPIO_AD_INPUT_03_0_SECURE                       0x0
+#define GPIO_AD_INPUT_03_0_DUAL                         0x0
+#define GPIO_AD_INPUT_03_0_SCR                  GPIO_AD_SCR_03_0
+#define GPIO_AD_INPUT_03_0_SCRREG                       GPIO_AD_SCR_03_0
+#define GPIO_AD_INPUT_03_0_WORD_COUNT                   0x1
+#define GPIO_AD_INPUT_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_03_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AD_INPUT_03_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_03_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AD_INPUT_03_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AD_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_AD_INPUT_03_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AD_INPUT_03_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AD_INPUT_03_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AD_INPUT_03_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AD_INPUT_03_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_03_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_03_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_OUTPUT_CONTROL_03_0
+#define GPIO_AD_OUTPUT_CONTROL_03_0                     MK_ADDR_CONST(0x1046c)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_SECURE                      0x0
+#define GPIO_AD_OUTPUT_CONTROL_03_0_DUAL                        0x0
+#define GPIO_AD_OUTPUT_CONTROL_03_0_SCR                         GPIO_AD_SCR_03_0
+#define GPIO_AD_OUTPUT_CONTROL_03_0_SCRREG                      GPIO_AD_SCR_03_0
+#define GPIO_AD_OUTPUT_CONTROL_03_0_WORD_COUNT                  0x1
+#define GPIO_AD_OUTPUT_CONTROL_03_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AD_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AD_OUTPUT_VALUE_03_0
+#define GPIO_AD_OUTPUT_VALUE_03_0                       MK_ADDR_CONST(0x10470)
+#define GPIO_AD_OUTPUT_VALUE_03_0_SECURE                        0x0
+#define GPIO_AD_OUTPUT_VALUE_03_0_DUAL                  0x0
+#define GPIO_AD_OUTPUT_VALUE_03_0_SCR                   GPIO_AD_SCR_03_0
+#define GPIO_AD_OUTPUT_VALUE_03_0_SCRREG                        GPIO_AD_SCR_03_0
+#define GPIO_AD_OUTPUT_VALUE_03_0_WORD_COUNT                    0x1
+#define GPIO_AD_OUTPUT_VALUE_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_03_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_03_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AD_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INTERRUPT_CLEAR_03_0
+#define GPIO_AD_INTERRUPT_CLEAR_03_0                    MK_ADDR_CONST(0x10474)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_SECURE                     0x0
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_DUAL                       0x0
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_SCR                        GPIO_AD_SCR_03_0
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_SCRREG                     GPIO_AD_SCR_03_0
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_WORD_COUNT                         0x1
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AD_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10478
+
+// Reserved address 0x1047c
+
+// Reserved address 0x10480
+
+// Reserved address 0x10484
+
+// Reserved address 0x10488
+
+// Reserved address 0x1048c
+
+// Reserved address 0x10490
+
+// Reserved address 0x10494
+
+// Reserved address 0x10498
+
+// Reserved address 0x1049c
+
+// Reserved address 0x104a0
+
+// Reserved address 0x104a4
+
+// Reserved address 0x104a8
+
+// Reserved address 0x104ac
+
+// Reserved address 0x104b0
+
+// Reserved address 0x104b4
+
+// Reserved address 0x104b8
+
+// Reserved address 0x104bc
+
+// Reserved address 0x104c0
+
+// Reserved address 0x104c4
+
+// Reserved address 0x104c8
+
+// Reserved address 0x104cc
+
+// Reserved address 0x104d0
+
+// Reserved address 0x104d4
+
+// Reserved address 0x104d8
+
+// Reserved address 0x104dc
+
+// Reserved address 0x104e0
+
+// Reserved address 0x104e4
+
+// Reserved address 0x104e8
+
+// Reserved address 0x104ec
+
+// Reserved address 0x104f0
+
+// Reserved address 0x104f4
+
+// Reserved address 0x104f8
+
+// Reserved address 0x104fc
+
+// Register GPIO_AD_INTERRUPT_STATUS_G0_0
+#define GPIO_AD_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x10500)
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_SECURE                    0x0
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_DUAL                      0x0
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_SCR                       0
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_SCRREG                    0
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INTERRUPT_STATUS_G1_0
+#define GPIO_AD_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x10504)
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_SECURE                    0x0
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_DUAL                      0x0
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_SCR                       0
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_SCRREG                    0
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INTERRUPT_STATUS_G2_0
+#define GPIO_AD_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x10508)
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_SECURE                    0x0
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_DUAL                      0x0
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_SCR                       0
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_SCRREG                    0
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INTERRUPT_STATUS_G3_0
+#define GPIO_AD_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x1050c)
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_SECURE                    0x0
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_DUAL                      0x0
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_SCR                       0
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_SCRREG                    0
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INTERRUPT_STATUS_G4_0
+#define GPIO_AD_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x10510)
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_SECURE                    0x0
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_DUAL                      0x0
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_SCR                       0
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_SCRREG                    0
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INTERRUPT_STATUS_G5_0
+#define GPIO_AD_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x10514)
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_SECURE                    0x0
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_DUAL                      0x0
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_SCR                       0
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_SCRREG                    0
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INTERRUPT_STATUS_G6_0
+#define GPIO_AD_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x10518)
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_SECURE                    0x0
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_DUAL                      0x0
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_SCR                       0
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_SCRREG                    0
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AD_INTERRUPT_STATUS_G7_0
+#define GPIO_AD_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x1051c)
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_SECURE                    0x0
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_DUAL                      0x0
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_SCR                       0
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_SCRREG                    0
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AD_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x10520
+
+// Reserved address 0x10524
+
+// Reserved address 0x10528
+
+// Reserved address 0x1052c
+
+// Reserved address 0x10530
+
+// Reserved address 0x10534
+
+// Reserved address 0x10538
+
+// Reserved address 0x1053c
+
+// Reserved address 0x10540
+
+// Reserved address 0x10544
+
+// Reserved address 0x10548
+
+// Reserved address 0x1054c
+
+// Reserved address 0x10550
+
+// Reserved address 0x10554
+
+// Reserved address 0x10558
+
+// Reserved address 0x1055c
+
+// Reserved address 0x10560
+
+// Reserved address 0x10564
+
+// Reserved address 0x10568
+
+// Reserved address 0x1056c
+
+// Reserved address 0x10570
+
+// Reserved address 0x10574
+
+// Reserved address 0x10578
+
+// Reserved address 0x1057c
+
+// Reserved address 0x10580
+
+// Reserved address 0x10584
+
+// Reserved address 0x10588
+
+// Reserved address 0x1058c
+
+// Reserved address 0x10590
+
+// Reserved address 0x10594
+
+// Reserved address 0x10598
+
+// Reserved address 0x1059c
+
+// Reserved address 0x105a0
+
+// Reserved address 0x105a4
+
+// Reserved address 0x105a8
+
+// Reserved address 0x105ac
+
+// Reserved address 0x105b0
+
+// Reserved address 0x105b4
+
+// Reserved address 0x105b8
+
+// Reserved address 0x105bc
+
+// Reserved address 0x105c0
+
+// Reserved address 0x105c4
+
+// Reserved address 0x105c8
+
+// Reserved address 0x105cc
+
+// Reserved address 0x105d0
+
+// Reserved address 0x105d4
+
+// Reserved address 0x105d8
+
+// Reserved address 0x105dc
+
+// Reserved address 0x105e0
+
+// Reserved address 0x105e4
+
+// Reserved address 0x105e8
+
+// Reserved address 0x105ec
+
+// Reserved address 0x105f0
+
+// Reserved address 0x105f4
+
+// Reserved address 0x105f8
+
+// Reserved address 0x105fc
+
+// Register GPIO_B_ENABLE_CONFIG_00_0
+#define GPIO_B_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x10600)
+#define GPIO_B_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_B_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_B_ENABLE_CONFIG_00_0_SCR                   GPIO_B_SCR_00_0
+#define GPIO_B_ENABLE_CONFIG_00_0_SCRREG                        GPIO_B_SCR_00_0
+#define GPIO_B_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_B_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_B_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_B_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_B_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_B_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_B_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_B_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_B_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_B_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_B_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x10604)
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_B_SCR_00_0
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_B_SCR_00_0
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_B_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_INPUT_00_0
+#define GPIO_B_INPUT_00_0                       MK_ADDR_CONST(0x10608)
+#define GPIO_B_INPUT_00_0_SECURE                        0x0
+#define GPIO_B_INPUT_00_0_DUAL                  0x0
+#define GPIO_B_INPUT_00_0_SCR                   GPIO_B_SCR_00_0
+#define GPIO_B_INPUT_00_0_SCRREG                        GPIO_B_SCR_00_0
+#define GPIO_B_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_B_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_B_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_B_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_B_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_B_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_B_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_B_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_B_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_B_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_B_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_B_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_B_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_B_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_B_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_B_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_B_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_B_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_B_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_B_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_OUTPUT_CONTROL_00_0
+#define GPIO_B_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1060c)
+#define GPIO_B_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_B_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_B_OUTPUT_CONTROL_00_0_SCR                  GPIO_B_SCR_00_0
+#define GPIO_B_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_B_SCR_00_0
+#define GPIO_B_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_B_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_B_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_B_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_B_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_B_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_B_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_B_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_B_OUTPUT_VALUE_00_0
+#define GPIO_B_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x10610)
+#define GPIO_B_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_B_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_B_OUTPUT_VALUE_00_0_SCR                    GPIO_B_SCR_00_0
+#define GPIO_B_OUTPUT_VALUE_00_0_SCRREG                         GPIO_B_SCR_00_0
+#define GPIO_B_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_B_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_B_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_B_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_B_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_B_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_B_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_B_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_INTERRUPT_CLEAR_00_0
+#define GPIO_B_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x10614)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_B_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_B_INTERRUPT_CLEAR_00_0_SCR                         GPIO_B_SCR_00_0
+#define GPIO_B_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_B_SCR_00_0
+#define GPIO_B_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_B_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_B_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x10618
+
+// Reserved address 0x1061c
+
+// Reserved address 0x10620
+
+// Reserved address 0x10624
+
+// Reserved address 0x10628
+
+// Reserved address 0x1062c
+
+// Reserved address 0x10630
+
+// Reserved address 0x10634
+
+// Reserved address 0x10638
+
+// Reserved address 0x1063c
+
+// Reserved address 0x10640
+
+// Reserved address 0x10644
+
+// Reserved address 0x10648
+
+// Reserved address 0x1064c
+
+// Reserved address 0x10650
+
+// Reserved address 0x10654
+
+// Reserved address 0x10658
+
+// Reserved address 0x1065c
+
+// Reserved address 0x10660
+
+// Reserved address 0x10664
+
+// Reserved address 0x10668
+
+// Reserved address 0x1066c
+
+// Reserved address 0x10670
+
+// Reserved address 0x10674
+
+// Reserved address 0x10678
+
+// Reserved address 0x1067c
+
+// Reserved address 0x10680
+
+// Reserved address 0x10684
+
+// Reserved address 0x10688
+
+// Reserved address 0x1068c
+
+// Reserved address 0x10690
+
+// Reserved address 0x10694
+
+// Reserved address 0x10698
+
+// Reserved address 0x1069c
+
+// Reserved address 0x106a0
+
+// Reserved address 0x106a4
+
+// Reserved address 0x106a8
+
+// Reserved address 0x106ac
+
+// Reserved address 0x106b0
+
+// Reserved address 0x106b4
+
+// Reserved address 0x106b8
+
+// Reserved address 0x106bc
+
+// Reserved address 0x106c0
+
+// Reserved address 0x106c4
+
+// Reserved address 0x106c8
+
+// Reserved address 0x106cc
+
+// Reserved address 0x106d0
+
+// Reserved address 0x106d4
+
+// Reserved address 0x106d8
+
+// Reserved address 0x106dc
+
+// Reserved address 0x106e0
+
+// Reserved address 0x106e4
+
+// Reserved address 0x106e8
+
+// Reserved address 0x106ec
+
+// Reserved address 0x106f0
+
+// Reserved address 0x106f4
+
+// Reserved address 0x106f8
+
+// Reserved address 0x106fc
+
+// Register GPIO_B_INTERRUPT_STATUS_G0_0
+#define GPIO_B_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x10700)
+#define GPIO_B_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_B_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_B_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_B_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_B_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_B_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
+#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_INTERRUPT_STATUS_G1_0
+#define GPIO_B_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x10704)
+#define GPIO_B_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_B_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_B_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_B_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_B_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_B_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
+#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_INTERRUPT_STATUS_G2_0
+#define GPIO_B_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x10708)
+#define GPIO_B_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_B_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_B_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_B_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_B_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_B_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
+#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_INTERRUPT_STATUS_G3_0
+#define GPIO_B_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1070c)
+#define GPIO_B_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_B_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_B_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_B_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_B_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_B_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
+#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_INTERRUPT_STATUS_G4_0
+#define GPIO_B_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x10710)
+#define GPIO_B_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_B_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_B_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_B_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_B_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_B_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
+#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_INTERRUPT_STATUS_G5_0
+#define GPIO_B_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x10714)
+#define GPIO_B_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_B_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_B_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_B_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_B_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_B_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
+#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_INTERRUPT_STATUS_G6_0
+#define GPIO_B_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x10718)
+#define GPIO_B_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_B_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_B_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_B_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_B_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_B_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
+#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_B_INTERRUPT_STATUS_G7_0
+#define GPIO_B_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1071c)
+#define GPIO_B_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_B_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_B_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_B_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_B_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_B_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x1, GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        0:0
+#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_B_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x10720
+
+// Reserved address 0x10724
+
+// Reserved address 0x10728
+
+// Reserved address 0x1072c
+
+// Reserved address 0x10730
+
+// Reserved address 0x10734
+
+// Reserved address 0x10738
+
+// Reserved address 0x1073c
+
+// Reserved address 0x10740
+
+// Reserved address 0x10744
+
+// Reserved address 0x10748
+
+// Reserved address 0x1074c
+
+// Reserved address 0x10750
+
+// Reserved address 0x10754
+
+// Reserved address 0x10758
+
+// Reserved address 0x1075c
+
+// Reserved address 0x10760
+
+// Reserved address 0x10764
+
+// Reserved address 0x10768
+
+// Reserved address 0x1076c
+
+// Reserved address 0x10770
+
+// Reserved address 0x10774
+
+// Reserved address 0x10778
+
+// Reserved address 0x1077c
+
+// Reserved address 0x10780
+
+// Reserved address 0x10784
+
+// Reserved address 0x10788
+
+// Reserved address 0x1078c
+
+// Reserved address 0x10790
+
+// Reserved address 0x10794
+
+// Reserved address 0x10798
+
+// Reserved address 0x1079c
+
+// Reserved address 0x107a0
+
+// Reserved address 0x107a4
+
+// Reserved address 0x107a8
+
+// Reserved address 0x107ac
+
+// Reserved address 0x107b0
+
+// Reserved address 0x107b4
+
+// Reserved address 0x107b8
+
+// Reserved address 0x107bc
+
+// Reserved address 0x107c0
+
+// Reserved address 0x107c4
+
+// Reserved address 0x107c8
+
+// Reserved address 0x107cc
+
+// Reserved address 0x107d0
+
+// Reserved address 0x107d4
+
+// Reserved address 0x107d8
+
+// Reserved address 0x107dc
+
+// Reserved address 0x107e0
+
+// Reserved address 0x107e4
+
+// Reserved address 0x107e8
+
+// Reserved address 0x107ec
+
+// Reserved address 0x107f0
+
+// Reserved address 0x107f4
+
+// Reserved address 0x107f8
+
+// Reserved address 0x107fc
+
+// Register GPIO_X_ENABLE_CONFIG_00_0
+#define GPIO_X_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x11000)
+#define GPIO_X_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_X_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_X_ENABLE_CONFIG_00_0_SCR                   GPIO_X_SCR_00_0
+#define GPIO_X_ENABLE_CONFIG_00_0_SCRREG                        GPIO_X_SCR_00_0
+#define GPIO_X_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_X_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_X_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x11004)
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_X_SCR_00_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_X_SCR_00_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_X_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INPUT_00_0
+#define GPIO_X_INPUT_00_0                       MK_ADDR_CONST(0x11008)
+#define GPIO_X_INPUT_00_0_SECURE                        0x0
+#define GPIO_X_INPUT_00_0_DUAL                  0x0
+#define GPIO_X_INPUT_00_0_SCR                   GPIO_X_SCR_00_0
+#define GPIO_X_INPUT_00_0_SCRREG                        GPIO_X_SCR_00_0
+#define GPIO_X_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_X_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_X_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_X_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_X_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_X_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_OUTPUT_CONTROL_00_0
+#define GPIO_X_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1100c)
+#define GPIO_X_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_X_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_X_OUTPUT_CONTROL_00_0_SCR                  GPIO_X_SCR_00_0
+#define GPIO_X_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_X_SCR_00_0
+#define GPIO_X_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_X_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_X_OUTPUT_VALUE_00_0
+#define GPIO_X_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x11010)
+#define GPIO_X_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_X_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_X_OUTPUT_VALUE_00_0_SCR                    GPIO_X_SCR_00_0
+#define GPIO_X_OUTPUT_VALUE_00_0_SCRREG                         GPIO_X_SCR_00_0
+#define GPIO_X_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_X_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INTERRUPT_CLEAR_00_0
+#define GPIO_X_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x11014)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_X_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_X_INTERRUPT_CLEAR_00_0_SCR                         GPIO_X_SCR_00_0
+#define GPIO_X_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_X_SCR_00_0
+#define GPIO_X_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_X_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x11018
+
+// Reserved address 0x1101c
+
+// Register GPIO_X_ENABLE_CONFIG_01_0
+#define GPIO_X_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x11020)
+#define GPIO_X_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_X_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_X_ENABLE_CONFIG_01_0_SCR                   GPIO_X_SCR_01_0
+#define GPIO_X_ENABLE_CONFIG_01_0_SCRREG                        GPIO_X_SCR_01_0
+#define GPIO_X_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_X_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_X_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x11024)
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_X_SCR_01_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_X_SCR_01_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_X_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INPUT_01_0
+#define GPIO_X_INPUT_01_0                       MK_ADDR_CONST(0x11028)
+#define GPIO_X_INPUT_01_0_SECURE                        0x0
+#define GPIO_X_INPUT_01_0_DUAL                  0x0
+#define GPIO_X_INPUT_01_0_SCR                   GPIO_X_SCR_01_0
+#define GPIO_X_INPUT_01_0_SCRREG                        GPIO_X_SCR_01_0
+#define GPIO_X_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_X_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_X_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_X_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_X_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_X_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_OUTPUT_CONTROL_01_0
+#define GPIO_X_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1102c)
+#define GPIO_X_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_X_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_X_OUTPUT_CONTROL_01_0_SCR                  GPIO_X_SCR_01_0
+#define GPIO_X_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_X_SCR_01_0
+#define GPIO_X_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_X_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_X_OUTPUT_VALUE_01_0
+#define GPIO_X_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x11030)
+#define GPIO_X_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_X_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_X_OUTPUT_VALUE_01_0_SCR                    GPIO_X_SCR_01_0
+#define GPIO_X_OUTPUT_VALUE_01_0_SCRREG                         GPIO_X_SCR_01_0
+#define GPIO_X_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_X_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INTERRUPT_CLEAR_01_0
+#define GPIO_X_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x11034)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_X_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_X_INTERRUPT_CLEAR_01_0_SCR                         GPIO_X_SCR_01_0
+#define GPIO_X_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_X_SCR_01_0
+#define GPIO_X_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_X_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x11038
+
+// Reserved address 0x1103c
+
+// Register GPIO_X_ENABLE_CONFIG_02_0
+#define GPIO_X_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x11040)
+#define GPIO_X_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_X_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_X_ENABLE_CONFIG_02_0_SCR                   GPIO_X_SCR_02_0
+#define GPIO_X_ENABLE_CONFIG_02_0_SCRREG                        GPIO_X_SCR_02_0
+#define GPIO_X_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_X_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_X_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x11044)
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_X_SCR_02_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_X_SCR_02_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_X_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INPUT_02_0
+#define GPIO_X_INPUT_02_0                       MK_ADDR_CONST(0x11048)
+#define GPIO_X_INPUT_02_0_SECURE                        0x0
+#define GPIO_X_INPUT_02_0_DUAL                  0x0
+#define GPIO_X_INPUT_02_0_SCR                   GPIO_X_SCR_02_0
+#define GPIO_X_INPUT_02_0_SCRREG                        GPIO_X_SCR_02_0
+#define GPIO_X_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_X_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_X_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_X_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_X_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_X_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_OUTPUT_CONTROL_02_0
+#define GPIO_X_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1104c)
+#define GPIO_X_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_X_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_X_OUTPUT_CONTROL_02_0_SCR                  GPIO_X_SCR_02_0
+#define GPIO_X_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_X_SCR_02_0
+#define GPIO_X_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_X_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_X_OUTPUT_VALUE_02_0
+#define GPIO_X_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x11050)
+#define GPIO_X_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_X_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_X_OUTPUT_VALUE_02_0_SCR                    GPIO_X_SCR_02_0
+#define GPIO_X_OUTPUT_VALUE_02_0_SCRREG                         GPIO_X_SCR_02_0
+#define GPIO_X_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_X_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INTERRUPT_CLEAR_02_0
+#define GPIO_X_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x11054)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_X_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_X_INTERRUPT_CLEAR_02_0_SCR                         GPIO_X_SCR_02_0
+#define GPIO_X_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_X_SCR_02_0
+#define GPIO_X_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_X_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x11058
+
+// Reserved address 0x1105c
+
+// Register GPIO_X_ENABLE_CONFIG_03_0
+#define GPIO_X_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x11060)
+#define GPIO_X_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_X_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_X_ENABLE_CONFIG_03_0_SCR                   GPIO_X_SCR_03_0
+#define GPIO_X_ENABLE_CONFIG_03_0_SCRREG                        GPIO_X_SCR_03_0
+#define GPIO_X_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_X_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_X_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x11064)
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_X_SCR_03_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_X_SCR_03_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_X_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INPUT_03_0
+#define GPIO_X_INPUT_03_0                       MK_ADDR_CONST(0x11068)
+#define GPIO_X_INPUT_03_0_SECURE                        0x0
+#define GPIO_X_INPUT_03_0_DUAL                  0x0
+#define GPIO_X_INPUT_03_0_SCR                   GPIO_X_SCR_03_0
+#define GPIO_X_INPUT_03_0_SCRREG                        GPIO_X_SCR_03_0
+#define GPIO_X_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_X_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_X_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_X_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_X_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_X_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_OUTPUT_CONTROL_03_0
+#define GPIO_X_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1106c)
+#define GPIO_X_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_X_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_X_OUTPUT_CONTROL_03_0_SCR                  GPIO_X_SCR_03_0
+#define GPIO_X_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_X_SCR_03_0
+#define GPIO_X_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_X_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_X_OUTPUT_VALUE_03_0
+#define GPIO_X_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x11070)
+#define GPIO_X_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_X_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_X_OUTPUT_VALUE_03_0_SCR                    GPIO_X_SCR_03_0
+#define GPIO_X_OUTPUT_VALUE_03_0_SCRREG                         GPIO_X_SCR_03_0
+#define GPIO_X_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_X_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INTERRUPT_CLEAR_03_0
+#define GPIO_X_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x11074)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_X_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_X_INTERRUPT_CLEAR_03_0_SCR                         GPIO_X_SCR_03_0
+#define GPIO_X_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_X_SCR_03_0
+#define GPIO_X_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_X_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x11078
+
+// Reserved address 0x1107c
+
+// Register GPIO_X_ENABLE_CONFIG_04_0
+#define GPIO_X_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x11080)
+#define GPIO_X_ENABLE_CONFIG_04_0_SECURE                        0x0
+#define GPIO_X_ENABLE_CONFIG_04_0_DUAL                  0x0
+#define GPIO_X_ENABLE_CONFIG_04_0_SCR                   GPIO_X_SCR_04_0
+#define GPIO_X_ENABLE_CONFIG_04_0_SCRREG                        GPIO_X_SCR_04_0
+#define GPIO_X_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
+#define GPIO_X_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
+#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_X_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x11084)
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_X_SCR_04_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_X_SCR_04_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_X_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INPUT_04_0
+#define GPIO_X_INPUT_04_0                       MK_ADDR_CONST(0x11088)
+#define GPIO_X_INPUT_04_0_SECURE                        0x0
+#define GPIO_X_INPUT_04_0_DUAL                  0x0
+#define GPIO_X_INPUT_04_0_SCR                   GPIO_X_SCR_04_0
+#define GPIO_X_INPUT_04_0_SCRREG                        GPIO_X_SCR_04_0
+#define GPIO_X_INPUT_04_0_WORD_COUNT                    0x1
+#define GPIO_X_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_X_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_X_INPUT_04_0_GPIO_IN_RANGE                 0:0
+#define GPIO_X_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_X_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_OUTPUT_CONTROL_04_0
+#define GPIO_X_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1108c)
+#define GPIO_X_OUTPUT_CONTROL_04_0_SECURE                       0x0
+#define GPIO_X_OUTPUT_CONTROL_04_0_DUAL                         0x0
+#define GPIO_X_OUTPUT_CONTROL_04_0_SCR                  GPIO_X_SCR_04_0
+#define GPIO_X_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_X_SCR_04_0
+#define GPIO_X_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
+#define GPIO_X_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_X_OUTPUT_VALUE_04_0
+#define GPIO_X_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x11090)
+#define GPIO_X_OUTPUT_VALUE_04_0_SECURE                         0x0
+#define GPIO_X_OUTPUT_VALUE_04_0_DUAL                   0x0
+#define GPIO_X_OUTPUT_VALUE_04_0_SCR                    GPIO_X_SCR_04_0
+#define GPIO_X_OUTPUT_VALUE_04_0_SCRREG                         GPIO_X_SCR_04_0
+#define GPIO_X_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
+#define GPIO_X_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INTERRUPT_CLEAR_04_0
+#define GPIO_X_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x11094)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_SECURE                      0x0
+#define GPIO_X_INTERRUPT_CLEAR_04_0_DUAL                        0x0
+#define GPIO_X_INTERRUPT_CLEAR_04_0_SCR                         GPIO_X_SCR_04_0
+#define GPIO_X_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_X_SCR_04_0
+#define GPIO_X_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
+#define GPIO_X_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x11098
+
+// Reserved address 0x1109c
+
+// Register GPIO_X_ENABLE_CONFIG_05_0
+#define GPIO_X_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x110a0)
+#define GPIO_X_ENABLE_CONFIG_05_0_SECURE                        0x0
+#define GPIO_X_ENABLE_CONFIG_05_0_DUAL                  0x0
+#define GPIO_X_ENABLE_CONFIG_05_0_SCR                   GPIO_X_SCR_05_0
+#define GPIO_X_ENABLE_CONFIG_05_0_SCRREG                        GPIO_X_SCR_05_0
+#define GPIO_X_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
+#define GPIO_X_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
+#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_X_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x110a4)
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_X_SCR_05_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_X_SCR_05_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_X_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INPUT_05_0
+#define GPIO_X_INPUT_05_0                       MK_ADDR_CONST(0x110a8)
+#define GPIO_X_INPUT_05_0_SECURE                        0x0
+#define GPIO_X_INPUT_05_0_DUAL                  0x0
+#define GPIO_X_INPUT_05_0_SCR                   GPIO_X_SCR_05_0
+#define GPIO_X_INPUT_05_0_SCRREG                        GPIO_X_SCR_05_0
+#define GPIO_X_INPUT_05_0_WORD_COUNT                    0x1
+#define GPIO_X_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_X_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_X_INPUT_05_0_GPIO_IN_RANGE                 0:0
+#define GPIO_X_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_X_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_OUTPUT_CONTROL_05_0
+#define GPIO_X_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x110ac)
+#define GPIO_X_OUTPUT_CONTROL_05_0_SECURE                       0x0
+#define GPIO_X_OUTPUT_CONTROL_05_0_DUAL                         0x0
+#define GPIO_X_OUTPUT_CONTROL_05_0_SCR                  GPIO_X_SCR_05_0
+#define GPIO_X_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_X_SCR_05_0
+#define GPIO_X_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
+#define GPIO_X_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_X_OUTPUT_VALUE_05_0
+#define GPIO_X_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x110b0)
+#define GPIO_X_OUTPUT_VALUE_05_0_SECURE                         0x0
+#define GPIO_X_OUTPUT_VALUE_05_0_DUAL                   0x0
+#define GPIO_X_OUTPUT_VALUE_05_0_SCR                    GPIO_X_SCR_05_0
+#define GPIO_X_OUTPUT_VALUE_05_0_SCRREG                         GPIO_X_SCR_05_0
+#define GPIO_X_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
+#define GPIO_X_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INTERRUPT_CLEAR_05_0
+#define GPIO_X_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x110b4)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_SECURE                      0x0
+#define GPIO_X_INTERRUPT_CLEAR_05_0_DUAL                        0x0
+#define GPIO_X_INTERRUPT_CLEAR_05_0_SCR                         GPIO_X_SCR_05_0
+#define GPIO_X_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_X_SCR_05_0
+#define GPIO_X_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
+#define GPIO_X_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x110b8
+
+// Reserved address 0x110bc
+
+// Register GPIO_X_ENABLE_CONFIG_06_0
+#define GPIO_X_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x110c0)
+#define GPIO_X_ENABLE_CONFIG_06_0_SECURE                        0x0
+#define GPIO_X_ENABLE_CONFIG_06_0_DUAL                  0x0
+#define GPIO_X_ENABLE_CONFIG_06_0_SCR                   GPIO_X_SCR_06_0
+#define GPIO_X_ENABLE_CONFIG_06_0_SCRREG                        GPIO_X_SCR_06_0
+#define GPIO_X_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
+#define GPIO_X_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
+#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_X_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x110c4)
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_X_SCR_06_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_X_SCR_06_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_X_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INPUT_06_0
+#define GPIO_X_INPUT_06_0                       MK_ADDR_CONST(0x110c8)
+#define GPIO_X_INPUT_06_0_SECURE                        0x0
+#define GPIO_X_INPUT_06_0_DUAL                  0x0
+#define GPIO_X_INPUT_06_0_SCR                   GPIO_X_SCR_06_0
+#define GPIO_X_INPUT_06_0_SCRREG                        GPIO_X_SCR_06_0
+#define GPIO_X_INPUT_06_0_WORD_COUNT                    0x1
+#define GPIO_X_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_X_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_X_INPUT_06_0_GPIO_IN_RANGE                 0:0
+#define GPIO_X_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_X_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_OUTPUT_CONTROL_06_0
+#define GPIO_X_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x110cc)
+#define GPIO_X_OUTPUT_CONTROL_06_0_SECURE                       0x0
+#define GPIO_X_OUTPUT_CONTROL_06_0_DUAL                         0x0
+#define GPIO_X_OUTPUT_CONTROL_06_0_SCR                  GPIO_X_SCR_06_0
+#define GPIO_X_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_X_SCR_06_0
+#define GPIO_X_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
+#define GPIO_X_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_X_OUTPUT_VALUE_06_0
+#define GPIO_X_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x110d0)
+#define GPIO_X_OUTPUT_VALUE_06_0_SECURE                         0x0
+#define GPIO_X_OUTPUT_VALUE_06_0_DUAL                   0x0
+#define GPIO_X_OUTPUT_VALUE_06_0_SCR                    GPIO_X_SCR_06_0
+#define GPIO_X_OUTPUT_VALUE_06_0_SCRREG                         GPIO_X_SCR_06_0
+#define GPIO_X_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
+#define GPIO_X_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INTERRUPT_CLEAR_06_0
+#define GPIO_X_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x110d4)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_SECURE                      0x0
+#define GPIO_X_INTERRUPT_CLEAR_06_0_DUAL                        0x0
+#define GPIO_X_INTERRUPT_CLEAR_06_0_SCR                         GPIO_X_SCR_06_0
+#define GPIO_X_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_X_SCR_06_0
+#define GPIO_X_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
+#define GPIO_X_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x110d8
+
+// Reserved address 0x110dc
+
+// Register GPIO_X_ENABLE_CONFIG_07_0
+#define GPIO_X_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x110e0)
+#define GPIO_X_ENABLE_CONFIG_07_0_SECURE                        0x0
+#define GPIO_X_ENABLE_CONFIG_07_0_DUAL                  0x0
+#define GPIO_X_ENABLE_CONFIG_07_0_SCR                   GPIO_X_SCR_07_0
+#define GPIO_X_ENABLE_CONFIG_07_0_SCRREG                        GPIO_X_SCR_07_0
+#define GPIO_X_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
+#define GPIO_X_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
+#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_X_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_X_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x110e4)
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_X_SCR_07_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_X_SCR_07_0
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_X_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INPUT_07_0
+#define GPIO_X_INPUT_07_0                       MK_ADDR_CONST(0x110e8)
+#define GPIO_X_INPUT_07_0_SECURE                        0x0
+#define GPIO_X_INPUT_07_0_DUAL                  0x0
+#define GPIO_X_INPUT_07_0_SCR                   GPIO_X_SCR_07_0
+#define GPIO_X_INPUT_07_0_SCRREG                        GPIO_X_SCR_07_0
+#define GPIO_X_INPUT_07_0_WORD_COUNT                    0x1
+#define GPIO_X_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_X_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_X_INPUT_07_0_GPIO_IN_RANGE                 0:0
+#define GPIO_X_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_X_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_X_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_X_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_OUTPUT_CONTROL_07_0
+#define GPIO_X_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x110ec)
+#define GPIO_X_OUTPUT_CONTROL_07_0_SECURE                       0x0
+#define GPIO_X_OUTPUT_CONTROL_07_0_DUAL                         0x0
+#define GPIO_X_OUTPUT_CONTROL_07_0_SCR                  GPIO_X_SCR_07_0
+#define GPIO_X_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_X_SCR_07_0
+#define GPIO_X_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
+#define GPIO_X_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_X_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_X_OUTPUT_VALUE_07_0
+#define GPIO_X_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x110f0)
+#define GPIO_X_OUTPUT_VALUE_07_0_SECURE                         0x0
+#define GPIO_X_OUTPUT_VALUE_07_0_DUAL                   0x0
+#define GPIO_X_OUTPUT_VALUE_07_0_SCR                    GPIO_X_SCR_07_0
+#define GPIO_X_OUTPUT_VALUE_07_0_SCRREG                         GPIO_X_SCR_07_0
+#define GPIO_X_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
+#define GPIO_X_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_X_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INTERRUPT_CLEAR_07_0
+#define GPIO_X_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x110f4)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_SECURE                      0x0
+#define GPIO_X_INTERRUPT_CLEAR_07_0_DUAL                        0x0
+#define GPIO_X_INTERRUPT_CLEAR_07_0_SCR                         GPIO_X_SCR_07_0
+#define GPIO_X_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_X_SCR_07_0
+#define GPIO_X_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
+#define GPIO_X_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_X_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x110f8
+
+// Reserved address 0x110fc
+
+// Register GPIO_X_INTERRUPT_STATUS_G0_0
+#define GPIO_X_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x11100)
+#define GPIO_X_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_X_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_X_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_X_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_X_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_X_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INTERRUPT_STATUS_G1_0
+#define GPIO_X_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x11104)
+#define GPIO_X_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_X_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_X_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_X_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_X_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_X_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INTERRUPT_STATUS_G2_0
+#define GPIO_X_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x11108)
+#define GPIO_X_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_X_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_X_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_X_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_X_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_X_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INTERRUPT_STATUS_G3_0
+#define GPIO_X_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1110c)
+#define GPIO_X_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_X_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_X_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_X_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_X_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_X_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INTERRUPT_STATUS_G4_0
+#define GPIO_X_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x11110)
+#define GPIO_X_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_X_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_X_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_X_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_X_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_X_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INTERRUPT_STATUS_G5_0
+#define GPIO_X_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x11114)
+#define GPIO_X_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_X_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_X_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_X_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_X_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_X_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INTERRUPT_STATUS_G6_0
+#define GPIO_X_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x11118)
+#define GPIO_X_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_X_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_X_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_X_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_X_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_X_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_X_INTERRUPT_STATUS_G7_0
+#define GPIO_X_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1111c)
+#define GPIO_X_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_X_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_X_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_X_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_X_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_X_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_X_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x11120
+
+// Reserved address 0x11124
+
+// Reserved address 0x11128
+
+// Reserved address 0x1112c
+
+// Reserved address 0x11130
+
+// Reserved address 0x11134
+
+// Reserved address 0x11138
+
+// Reserved address 0x1113c
+
+// Reserved address 0x11140
+
+// Reserved address 0x11144
+
+// Reserved address 0x11148
+
+// Reserved address 0x1114c
+
+// Reserved address 0x11150
+
+// Reserved address 0x11154
+
+// Reserved address 0x11158
+
+// Reserved address 0x1115c
+
+// Reserved address 0x11160
+
+// Reserved address 0x11164
+
+// Reserved address 0x11168
+
+// Reserved address 0x1116c
+
+// Reserved address 0x11170
+
+// Reserved address 0x11174
+
+// Reserved address 0x11178
+
+// Reserved address 0x1117c
+
+// Reserved address 0x11180
+
+// Reserved address 0x11184
+
+// Reserved address 0x11188
+
+// Reserved address 0x1118c
+
+// Reserved address 0x11190
+
+// Reserved address 0x11194
+
+// Reserved address 0x11198
+
+// Reserved address 0x1119c
+
+// Reserved address 0x111a0
+
+// Reserved address 0x111a4
+
+// Reserved address 0x111a8
+
+// Reserved address 0x111ac
+
+// Reserved address 0x111b0
+
+// Reserved address 0x111b4
+
+// Reserved address 0x111b8
+
+// Reserved address 0x111bc
+
+// Reserved address 0x111c0
+
+// Reserved address 0x111c4
+
+// Reserved address 0x111c8
+
+// Reserved address 0x111cc
+
+// Reserved address 0x111d0
+
+// Reserved address 0x111d4
+
+// Reserved address 0x111d8
+
+// Reserved address 0x111dc
+
+// Reserved address 0x111e0
+
+// Reserved address 0x111e4
+
+// Reserved address 0x111e8
+
+// Reserved address 0x111ec
+
+// Reserved address 0x111f0
+
+// Reserved address 0x111f4
+
+// Reserved address 0x111f8
+
+// Reserved address 0x111fc
+
+// Register GPIO_Y_ENABLE_CONFIG_00_0
+#define GPIO_Y_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x11200)
+#define GPIO_Y_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_Y_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_Y_ENABLE_CONFIG_00_0_SCR                   GPIO_Y_SCR_00_0
+#define GPIO_Y_ENABLE_CONFIG_00_0_SCRREG                        GPIO_Y_SCR_00_0
+#define GPIO_Y_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_Y_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Y_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x11204)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_Y_SCR_00_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_Y_SCR_00_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INPUT_00_0
+#define GPIO_Y_INPUT_00_0                       MK_ADDR_CONST(0x11208)
+#define GPIO_Y_INPUT_00_0_SECURE                        0x0
+#define GPIO_Y_INPUT_00_0_DUAL                  0x0
+#define GPIO_Y_INPUT_00_0_SCR                   GPIO_Y_SCR_00_0
+#define GPIO_Y_INPUT_00_0_SCRREG                        GPIO_Y_SCR_00_0
+#define GPIO_Y_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_Y_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Y_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_Y_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Y_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Y_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_OUTPUT_CONTROL_00_0
+#define GPIO_Y_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1120c)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_Y_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_Y_OUTPUT_CONTROL_00_0_SCR                  GPIO_Y_SCR_00_0
+#define GPIO_Y_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_Y_SCR_00_0
+#define GPIO_Y_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_Y_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Y_OUTPUT_VALUE_00_0
+#define GPIO_Y_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x11210)
+#define GPIO_Y_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_Y_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_Y_OUTPUT_VALUE_00_0_SCR                    GPIO_Y_SCR_00_0
+#define GPIO_Y_OUTPUT_VALUE_00_0_SCRREG                         GPIO_Y_SCR_00_0
+#define GPIO_Y_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_Y_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INTERRUPT_CLEAR_00_0
+#define GPIO_Y_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x11214)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_SCR                         GPIO_Y_SCR_00_0
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_Y_SCR_00_0
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x11218
+
+// Reserved address 0x1121c
+
+// Register GPIO_Y_ENABLE_CONFIG_01_0
+#define GPIO_Y_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x11220)
+#define GPIO_Y_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_Y_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_Y_ENABLE_CONFIG_01_0_SCR                   GPIO_Y_SCR_01_0
+#define GPIO_Y_ENABLE_CONFIG_01_0_SCRREG                        GPIO_Y_SCR_01_0
+#define GPIO_Y_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_Y_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Y_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x11224)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_Y_SCR_01_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_Y_SCR_01_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INPUT_01_0
+#define GPIO_Y_INPUT_01_0                       MK_ADDR_CONST(0x11228)
+#define GPIO_Y_INPUT_01_0_SECURE                        0x0
+#define GPIO_Y_INPUT_01_0_DUAL                  0x0
+#define GPIO_Y_INPUT_01_0_SCR                   GPIO_Y_SCR_01_0
+#define GPIO_Y_INPUT_01_0_SCRREG                        GPIO_Y_SCR_01_0
+#define GPIO_Y_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_Y_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Y_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_Y_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Y_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Y_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_OUTPUT_CONTROL_01_0
+#define GPIO_Y_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1122c)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_Y_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_Y_OUTPUT_CONTROL_01_0_SCR                  GPIO_Y_SCR_01_0
+#define GPIO_Y_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_Y_SCR_01_0
+#define GPIO_Y_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_Y_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Y_OUTPUT_VALUE_01_0
+#define GPIO_Y_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x11230)
+#define GPIO_Y_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_Y_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_Y_OUTPUT_VALUE_01_0_SCR                    GPIO_Y_SCR_01_0
+#define GPIO_Y_OUTPUT_VALUE_01_0_SCRREG                         GPIO_Y_SCR_01_0
+#define GPIO_Y_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_Y_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INTERRUPT_CLEAR_01_0
+#define GPIO_Y_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x11234)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_SCR                         GPIO_Y_SCR_01_0
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_Y_SCR_01_0
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x11238
+
+// Reserved address 0x1123c
+
+// Register GPIO_Y_ENABLE_CONFIG_02_0
+#define GPIO_Y_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x11240)
+#define GPIO_Y_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_Y_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_Y_ENABLE_CONFIG_02_0_SCR                   GPIO_Y_SCR_02_0
+#define GPIO_Y_ENABLE_CONFIG_02_0_SCRREG                        GPIO_Y_SCR_02_0
+#define GPIO_Y_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_Y_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Y_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x11244)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_Y_SCR_02_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_Y_SCR_02_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INPUT_02_0
+#define GPIO_Y_INPUT_02_0                       MK_ADDR_CONST(0x11248)
+#define GPIO_Y_INPUT_02_0_SECURE                        0x0
+#define GPIO_Y_INPUT_02_0_DUAL                  0x0
+#define GPIO_Y_INPUT_02_0_SCR                   GPIO_Y_SCR_02_0
+#define GPIO_Y_INPUT_02_0_SCRREG                        GPIO_Y_SCR_02_0
+#define GPIO_Y_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_Y_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Y_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_Y_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Y_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Y_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_OUTPUT_CONTROL_02_0
+#define GPIO_Y_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1124c)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_Y_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_Y_OUTPUT_CONTROL_02_0_SCR                  GPIO_Y_SCR_02_0
+#define GPIO_Y_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_Y_SCR_02_0
+#define GPIO_Y_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_Y_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Y_OUTPUT_VALUE_02_0
+#define GPIO_Y_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x11250)
+#define GPIO_Y_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_Y_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_Y_OUTPUT_VALUE_02_0_SCR                    GPIO_Y_SCR_02_0
+#define GPIO_Y_OUTPUT_VALUE_02_0_SCRREG                         GPIO_Y_SCR_02_0
+#define GPIO_Y_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_Y_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INTERRUPT_CLEAR_02_0
+#define GPIO_Y_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x11254)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_SCR                         GPIO_Y_SCR_02_0
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_Y_SCR_02_0
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x11258
+
+// Reserved address 0x1125c
+
+// Register GPIO_Y_ENABLE_CONFIG_03_0
+#define GPIO_Y_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x11260)
+#define GPIO_Y_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_Y_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_Y_ENABLE_CONFIG_03_0_SCR                   GPIO_Y_SCR_03_0
+#define GPIO_Y_ENABLE_CONFIG_03_0_SCRREG                        GPIO_Y_SCR_03_0
+#define GPIO_Y_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_Y_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Y_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x11264)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_Y_SCR_03_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_Y_SCR_03_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INPUT_03_0
+#define GPIO_Y_INPUT_03_0                       MK_ADDR_CONST(0x11268)
+#define GPIO_Y_INPUT_03_0_SECURE                        0x0
+#define GPIO_Y_INPUT_03_0_DUAL                  0x0
+#define GPIO_Y_INPUT_03_0_SCR                   GPIO_Y_SCR_03_0
+#define GPIO_Y_INPUT_03_0_SCRREG                        GPIO_Y_SCR_03_0
+#define GPIO_Y_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_Y_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Y_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_Y_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Y_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Y_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_OUTPUT_CONTROL_03_0
+#define GPIO_Y_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1126c)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_Y_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_Y_OUTPUT_CONTROL_03_0_SCR                  GPIO_Y_SCR_03_0
+#define GPIO_Y_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_Y_SCR_03_0
+#define GPIO_Y_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_Y_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Y_OUTPUT_VALUE_03_0
+#define GPIO_Y_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x11270)
+#define GPIO_Y_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_Y_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_Y_OUTPUT_VALUE_03_0_SCR                    GPIO_Y_SCR_03_0
+#define GPIO_Y_OUTPUT_VALUE_03_0_SCRREG                         GPIO_Y_SCR_03_0
+#define GPIO_Y_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_Y_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INTERRUPT_CLEAR_03_0
+#define GPIO_Y_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x11274)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_SCR                         GPIO_Y_SCR_03_0
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_Y_SCR_03_0
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x11278
+
+// Reserved address 0x1127c
+
+// Register GPIO_Y_ENABLE_CONFIG_04_0
+#define GPIO_Y_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x11280)
+#define GPIO_Y_ENABLE_CONFIG_04_0_SECURE                        0x0
+#define GPIO_Y_ENABLE_CONFIG_04_0_DUAL                  0x0
+#define GPIO_Y_ENABLE_CONFIG_04_0_SCR                   GPIO_Y_SCR_04_0
+#define GPIO_Y_ENABLE_CONFIG_04_0_SCRREG                        GPIO_Y_SCR_04_0
+#define GPIO_Y_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
+#define GPIO_Y_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
+#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Y_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x11284)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_Y_SCR_04_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_Y_SCR_04_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INPUT_04_0
+#define GPIO_Y_INPUT_04_0                       MK_ADDR_CONST(0x11288)
+#define GPIO_Y_INPUT_04_0_SECURE                        0x0
+#define GPIO_Y_INPUT_04_0_DUAL                  0x0
+#define GPIO_Y_INPUT_04_0_SCR                   GPIO_Y_SCR_04_0
+#define GPIO_Y_INPUT_04_0_SCRREG                        GPIO_Y_SCR_04_0
+#define GPIO_Y_INPUT_04_0_WORD_COUNT                    0x1
+#define GPIO_Y_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Y_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_Y_INPUT_04_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Y_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Y_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_OUTPUT_CONTROL_04_0
+#define GPIO_Y_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1128c)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_SECURE                       0x0
+#define GPIO_Y_OUTPUT_CONTROL_04_0_DUAL                         0x0
+#define GPIO_Y_OUTPUT_CONTROL_04_0_SCR                  GPIO_Y_SCR_04_0
+#define GPIO_Y_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_Y_SCR_04_0
+#define GPIO_Y_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
+#define GPIO_Y_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Y_OUTPUT_VALUE_04_0
+#define GPIO_Y_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x11290)
+#define GPIO_Y_OUTPUT_VALUE_04_0_SECURE                         0x0
+#define GPIO_Y_OUTPUT_VALUE_04_0_DUAL                   0x0
+#define GPIO_Y_OUTPUT_VALUE_04_0_SCR                    GPIO_Y_SCR_04_0
+#define GPIO_Y_OUTPUT_VALUE_04_0_SCRREG                         GPIO_Y_SCR_04_0
+#define GPIO_Y_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
+#define GPIO_Y_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INTERRUPT_CLEAR_04_0
+#define GPIO_Y_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x11294)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_SECURE                      0x0
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_DUAL                        0x0
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_SCR                         GPIO_Y_SCR_04_0
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_Y_SCR_04_0
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x11298
+
+// Reserved address 0x1129c
+
+// Register GPIO_Y_ENABLE_CONFIG_05_0
+#define GPIO_Y_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x112a0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_SECURE                        0x0
+#define GPIO_Y_ENABLE_CONFIG_05_0_DUAL                  0x0
+#define GPIO_Y_ENABLE_CONFIG_05_0_SCR                   GPIO_Y_SCR_05_0
+#define GPIO_Y_ENABLE_CONFIG_05_0_SCRREG                        GPIO_Y_SCR_05_0
+#define GPIO_Y_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
+#define GPIO_Y_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
+#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Y_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x112a4)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_Y_SCR_05_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_Y_SCR_05_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INPUT_05_0
+#define GPIO_Y_INPUT_05_0                       MK_ADDR_CONST(0x112a8)
+#define GPIO_Y_INPUT_05_0_SECURE                        0x0
+#define GPIO_Y_INPUT_05_0_DUAL                  0x0
+#define GPIO_Y_INPUT_05_0_SCR                   GPIO_Y_SCR_05_0
+#define GPIO_Y_INPUT_05_0_SCRREG                        GPIO_Y_SCR_05_0
+#define GPIO_Y_INPUT_05_0_WORD_COUNT                    0x1
+#define GPIO_Y_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Y_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_Y_INPUT_05_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Y_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Y_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_OUTPUT_CONTROL_05_0
+#define GPIO_Y_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x112ac)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_SECURE                       0x0
+#define GPIO_Y_OUTPUT_CONTROL_05_0_DUAL                         0x0
+#define GPIO_Y_OUTPUT_CONTROL_05_0_SCR                  GPIO_Y_SCR_05_0
+#define GPIO_Y_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_Y_SCR_05_0
+#define GPIO_Y_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
+#define GPIO_Y_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Y_OUTPUT_VALUE_05_0
+#define GPIO_Y_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x112b0)
+#define GPIO_Y_OUTPUT_VALUE_05_0_SECURE                         0x0
+#define GPIO_Y_OUTPUT_VALUE_05_0_DUAL                   0x0
+#define GPIO_Y_OUTPUT_VALUE_05_0_SCR                    GPIO_Y_SCR_05_0
+#define GPIO_Y_OUTPUT_VALUE_05_0_SCRREG                         GPIO_Y_SCR_05_0
+#define GPIO_Y_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
+#define GPIO_Y_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INTERRUPT_CLEAR_05_0
+#define GPIO_Y_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x112b4)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_SECURE                      0x0
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_DUAL                        0x0
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_SCR                         GPIO_Y_SCR_05_0
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_Y_SCR_05_0
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x112b8
+
+// Reserved address 0x112bc
+
+// Register GPIO_Y_ENABLE_CONFIG_06_0
+#define GPIO_Y_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x112c0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_SECURE                        0x0
+#define GPIO_Y_ENABLE_CONFIG_06_0_DUAL                  0x0
+#define GPIO_Y_ENABLE_CONFIG_06_0_SCR                   GPIO_Y_SCR_06_0
+#define GPIO_Y_ENABLE_CONFIG_06_0_SCRREG                        GPIO_Y_SCR_06_0
+#define GPIO_Y_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
+#define GPIO_Y_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
+#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Y_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x112c4)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_Y_SCR_06_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_Y_SCR_06_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INPUT_06_0
+#define GPIO_Y_INPUT_06_0                       MK_ADDR_CONST(0x112c8)
+#define GPIO_Y_INPUT_06_0_SECURE                        0x0
+#define GPIO_Y_INPUT_06_0_DUAL                  0x0
+#define GPIO_Y_INPUT_06_0_SCR                   GPIO_Y_SCR_06_0
+#define GPIO_Y_INPUT_06_0_SCRREG                        GPIO_Y_SCR_06_0
+#define GPIO_Y_INPUT_06_0_WORD_COUNT                    0x1
+#define GPIO_Y_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Y_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_Y_INPUT_06_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Y_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Y_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_OUTPUT_CONTROL_06_0
+#define GPIO_Y_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x112cc)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_SECURE                       0x0
+#define GPIO_Y_OUTPUT_CONTROL_06_0_DUAL                         0x0
+#define GPIO_Y_OUTPUT_CONTROL_06_0_SCR                  GPIO_Y_SCR_06_0
+#define GPIO_Y_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_Y_SCR_06_0
+#define GPIO_Y_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
+#define GPIO_Y_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Y_OUTPUT_VALUE_06_0
+#define GPIO_Y_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x112d0)
+#define GPIO_Y_OUTPUT_VALUE_06_0_SECURE                         0x0
+#define GPIO_Y_OUTPUT_VALUE_06_0_DUAL                   0x0
+#define GPIO_Y_OUTPUT_VALUE_06_0_SCR                    GPIO_Y_SCR_06_0
+#define GPIO_Y_OUTPUT_VALUE_06_0_SCRREG                         GPIO_Y_SCR_06_0
+#define GPIO_Y_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
+#define GPIO_Y_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INTERRUPT_CLEAR_06_0
+#define GPIO_Y_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x112d4)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_SECURE                      0x0
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_DUAL                        0x0
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_SCR                         GPIO_Y_SCR_06_0
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_Y_SCR_06_0
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x112d8
+
+// Reserved address 0x112dc
+
+// Register GPIO_Y_ENABLE_CONFIG_07_0
+#define GPIO_Y_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x112e0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_SECURE                        0x0
+#define GPIO_Y_ENABLE_CONFIG_07_0_DUAL                  0x0
+#define GPIO_Y_ENABLE_CONFIG_07_0_SCR                   GPIO_Y_SCR_07_0
+#define GPIO_Y_ENABLE_CONFIG_07_0_SCRREG                        GPIO_Y_SCR_07_0
+#define GPIO_Y_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
+#define GPIO_Y_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
+#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Y_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Y_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x112e4)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_Y_SCR_07_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_Y_SCR_07_0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Y_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INPUT_07_0
+#define GPIO_Y_INPUT_07_0                       MK_ADDR_CONST(0x112e8)
+#define GPIO_Y_INPUT_07_0_SECURE                        0x0
+#define GPIO_Y_INPUT_07_0_DUAL                  0x0
+#define GPIO_Y_INPUT_07_0_SCR                   GPIO_Y_SCR_07_0
+#define GPIO_Y_INPUT_07_0_SCRREG                        GPIO_Y_SCR_07_0
+#define GPIO_Y_INPUT_07_0_WORD_COUNT                    0x1
+#define GPIO_Y_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Y_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_Y_INPUT_07_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Y_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Y_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Y_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_OUTPUT_CONTROL_07_0
+#define GPIO_Y_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x112ec)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_SECURE                       0x0
+#define GPIO_Y_OUTPUT_CONTROL_07_0_DUAL                         0x0
+#define GPIO_Y_OUTPUT_CONTROL_07_0_SCR                  GPIO_Y_SCR_07_0
+#define GPIO_Y_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_Y_SCR_07_0
+#define GPIO_Y_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
+#define GPIO_Y_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Y_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Y_OUTPUT_VALUE_07_0
+#define GPIO_Y_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x112f0)
+#define GPIO_Y_OUTPUT_VALUE_07_0_SECURE                         0x0
+#define GPIO_Y_OUTPUT_VALUE_07_0_DUAL                   0x0
+#define GPIO_Y_OUTPUT_VALUE_07_0_SCR                    GPIO_Y_SCR_07_0
+#define GPIO_Y_OUTPUT_VALUE_07_0_SCRREG                         GPIO_Y_SCR_07_0
+#define GPIO_Y_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
+#define GPIO_Y_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Y_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INTERRUPT_CLEAR_07_0
+#define GPIO_Y_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x112f4)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_SECURE                      0x0
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_DUAL                        0x0
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_SCR                         GPIO_Y_SCR_07_0
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_Y_SCR_07_0
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Y_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x112f8
+
+// Reserved address 0x112fc
+
+// Register GPIO_Y_INTERRUPT_STATUS_G0_0
+#define GPIO_Y_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x11300)
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INTERRUPT_STATUS_G1_0
+#define GPIO_Y_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x11304)
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INTERRUPT_STATUS_G2_0
+#define GPIO_Y_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x11308)
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INTERRUPT_STATUS_G3_0
+#define GPIO_Y_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1130c)
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INTERRUPT_STATUS_G4_0
+#define GPIO_Y_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x11310)
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INTERRUPT_STATUS_G5_0
+#define GPIO_Y_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x11314)
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INTERRUPT_STATUS_G6_0
+#define GPIO_Y_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x11318)
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Y_INTERRUPT_STATUS_G7_0
+#define GPIO_Y_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1131c)
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Y_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x11320
+
+// Reserved address 0x11324
+
+// Reserved address 0x11328
+
+// Reserved address 0x1132c
+
+// Reserved address 0x11330
+
+// Reserved address 0x11334
+
+// Reserved address 0x11338
+
+// Reserved address 0x1133c
+
+// Reserved address 0x11340
+
+// Reserved address 0x11344
+
+// Reserved address 0x11348
+
+// Reserved address 0x1134c
+
+// Reserved address 0x11350
+
+// Reserved address 0x11354
+
+// Reserved address 0x11358
+
+// Reserved address 0x1135c
+
+// Reserved address 0x11360
+
+// Reserved address 0x11364
+
+// Reserved address 0x11368
+
+// Reserved address 0x1136c
+
+// Reserved address 0x11370
+
+// Reserved address 0x11374
+
+// Reserved address 0x11378
+
+// Reserved address 0x1137c
+
+// Reserved address 0x11380
+
+// Reserved address 0x11384
+
+// Reserved address 0x11388
+
+// Reserved address 0x1138c
+
+// Reserved address 0x11390
+
+// Reserved address 0x11394
+
+// Reserved address 0x11398
+
+// Reserved address 0x1139c
+
+// Reserved address 0x113a0
+
+// Reserved address 0x113a4
+
+// Reserved address 0x113a8
+
+// Reserved address 0x113ac
+
+// Reserved address 0x113b0
+
+// Reserved address 0x113b4
+
+// Reserved address 0x113b8
+
+// Reserved address 0x113bc
+
+// Reserved address 0x113c0
+
+// Reserved address 0x113c4
+
+// Reserved address 0x113c8
+
+// Reserved address 0x113cc
+
+// Reserved address 0x113d0
+
+// Reserved address 0x113d4
+
+// Reserved address 0x113d8
+
+// Reserved address 0x113dc
+
+// Reserved address 0x113e0
+
+// Reserved address 0x113e4
+
+// Reserved address 0x113e8
+
+// Reserved address 0x113ec
+
+// Reserved address 0x113f0
+
+// Reserved address 0x113f4
+
+// Reserved address 0x113f8
+
+// Reserved address 0x113fc
+
+// Register GPIO_Z_ENABLE_CONFIG_00_0
+#define GPIO_Z_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x11400)
+#define GPIO_Z_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_Z_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_Z_ENABLE_CONFIG_00_0_SCR                   GPIO_Z_SCR_00_0
+#define GPIO_Z_ENABLE_CONFIG_00_0_SCRREG                        GPIO_Z_SCR_00_0
+#define GPIO_Z_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_Z_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Z_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x11404)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_Z_SCR_00_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_Z_SCR_00_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INPUT_00_0
+#define GPIO_Z_INPUT_00_0                       MK_ADDR_CONST(0x11408)
+#define GPIO_Z_INPUT_00_0_SECURE                        0x0
+#define GPIO_Z_INPUT_00_0_DUAL                  0x0
+#define GPIO_Z_INPUT_00_0_SCR                   GPIO_Z_SCR_00_0
+#define GPIO_Z_INPUT_00_0_SCRREG                        GPIO_Z_SCR_00_0
+#define GPIO_Z_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_Z_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Z_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_Z_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Z_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Z_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_OUTPUT_CONTROL_00_0
+#define GPIO_Z_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1140c)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_Z_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_Z_OUTPUT_CONTROL_00_0_SCR                  GPIO_Z_SCR_00_0
+#define GPIO_Z_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_Z_SCR_00_0
+#define GPIO_Z_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_Z_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Z_OUTPUT_VALUE_00_0
+#define GPIO_Z_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x11410)
+#define GPIO_Z_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_Z_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_Z_OUTPUT_VALUE_00_0_SCR                    GPIO_Z_SCR_00_0
+#define GPIO_Z_OUTPUT_VALUE_00_0_SCRREG                         GPIO_Z_SCR_00_0
+#define GPIO_Z_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_Z_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INTERRUPT_CLEAR_00_0
+#define GPIO_Z_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x11414)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_SCR                         GPIO_Z_SCR_00_0
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_Z_SCR_00_0
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x11418
+
+// Reserved address 0x1141c
+
+// Register GPIO_Z_ENABLE_CONFIG_01_0
+#define GPIO_Z_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x11420)
+#define GPIO_Z_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_Z_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_Z_ENABLE_CONFIG_01_0_SCR                   GPIO_Z_SCR_01_0
+#define GPIO_Z_ENABLE_CONFIG_01_0_SCRREG                        GPIO_Z_SCR_01_0
+#define GPIO_Z_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_Z_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Z_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x11424)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_Z_SCR_01_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_Z_SCR_01_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INPUT_01_0
+#define GPIO_Z_INPUT_01_0                       MK_ADDR_CONST(0x11428)
+#define GPIO_Z_INPUT_01_0_SECURE                        0x0
+#define GPIO_Z_INPUT_01_0_DUAL                  0x0
+#define GPIO_Z_INPUT_01_0_SCR                   GPIO_Z_SCR_01_0
+#define GPIO_Z_INPUT_01_0_SCRREG                        GPIO_Z_SCR_01_0
+#define GPIO_Z_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_Z_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Z_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_Z_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Z_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Z_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_OUTPUT_CONTROL_01_0
+#define GPIO_Z_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1142c)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_Z_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_Z_OUTPUT_CONTROL_01_0_SCR                  GPIO_Z_SCR_01_0
+#define GPIO_Z_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_Z_SCR_01_0
+#define GPIO_Z_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_Z_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Z_OUTPUT_VALUE_01_0
+#define GPIO_Z_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x11430)
+#define GPIO_Z_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_Z_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_Z_OUTPUT_VALUE_01_0_SCR                    GPIO_Z_SCR_01_0
+#define GPIO_Z_OUTPUT_VALUE_01_0_SCRREG                         GPIO_Z_SCR_01_0
+#define GPIO_Z_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_Z_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INTERRUPT_CLEAR_01_0
+#define GPIO_Z_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x11434)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_SCR                         GPIO_Z_SCR_01_0
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_Z_SCR_01_0
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x11438
+
+// Reserved address 0x1143c
+
+// Register GPIO_Z_ENABLE_CONFIG_02_0
+#define GPIO_Z_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x11440)
+#define GPIO_Z_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_Z_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_Z_ENABLE_CONFIG_02_0_SCR                   GPIO_Z_SCR_02_0
+#define GPIO_Z_ENABLE_CONFIG_02_0_SCRREG                        GPIO_Z_SCR_02_0
+#define GPIO_Z_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_Z_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Z_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x11444)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_Z_SCR_02_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_Z_SCR_02_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INPUT_02_0
+#define GPIO_Z_INPUT_02_0                       MK_ADDR_CONST(0x11448)
+#define GPIO_Z_INPUT_02_0_SECURE                        0x0
+#define GPIO_Z_INPUT_02_0_DUAL                  0x0
+#define GPIO_Z_INPUT_02_0_SCR                   GPIO_Z_SCR_02_0
+#define GPIO_Z_INPUT_02_0_SCRREG                        GPIO_Z_SCR_02_0
+#define GPIO_Z_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_Z_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Z_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_Z_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Z_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Z_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_OUTPUT_CONTROL_02_0
+#define GPIO_Z_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1144c)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_Z_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_Z_OUTPUT_CONTROL_02_0_SCR                  GPIO_Z_SCR_02_0
+#define GPIO_Z_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_Z_SCR_02_0
+#define GPIO_Z_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_Z_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Z_OUTPUT_VALUE_02_0
+#define GPIO_Z_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x11450)
+#define GPIO_Z_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_Z_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_Z_OUTPUT_VALUE_02_0_SCR                    GPIO_Z_SCR_02_0
+#define GPIO_Z_OUTPUT_VALUE_02_0_SCRREG                         GPIO_Z_SCR_02_0
+#define GPIO_Z_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_Z_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INTERRUPT_CLEAR_02_0
+#define GPIO_Z_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x11454)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_SCR                         GPIO_Z_SCR_02_0
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_Z_SCR_02_0
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x11458
+
+// Reserved address 0x1145c
+
+// Register GPIO_Z_ENABLE_CONFIG_03_0
+#define GPIO_Z_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x11460)
+#define GPIO_Z_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_Z_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_Z_ENABLE_CONFIG_03_0_SCR                   GPIO_Z_SCR_03_0
+#define GPIO_Z_ENABLE_CONFIG_03_0_SCRREG                        GPIO_Z_SCR_03_0
+#define GPIO_Z_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_Z_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Z_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x11464)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_Z_SCR_03_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_Z_SCR_03_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INPUT_03_0
+#define GPIO_Z_INPUT_03_0                       MK_ADDR_CONST(0x11468)
+#define GPIO_Z_INPUT_03_0_SECURE                        0x0
+#define GPIO_Z_INPUT_03_0_DUAL                  0x0
+#define GPIO_Z_INPUT_03_0_SCR                   GPIO_Z_SCR_03_0
+#define GPIO_Z_INPUT_03_0_SCRREG                        GPIO_Z_SCR_03_0
+#define GPIO_Z_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_Z_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Z_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_Z_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Z_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Z_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_OUTPUT_CONTROL_03_0
+#define GPIO_Z_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1146c)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_Z_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_Z_OUTPUT_CONTROL_03_0_SCR                  GPIO_Z_SCR_03_0
+#define GPIO_Z_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_Z_SCR_03_0
+#define GPIO_Z_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_Z_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Z_OUTPUT_VALUE_03_0
+#define GPIO_Z_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x11470)
+#define GPIO_Z_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_Z_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_Z_OUTPUT_VALUE_03_0_SCR                    GPIO_Z_SCR_03_0
+#define GPIO_Z_OUTPUT_VALUE_03_0_SCRREG                         GPIO_Z_SCR_03_0
+#define GPIO_Z_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_Z_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INTERRUPT_CLEAR_03_0
+#define GPIO_Z_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x11474)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_SCR                         GPIO_Z_SCR_03_0
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_Z_SCR_03_0
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x11478
+
+// Reserved address 0x1147c
+
+// Register GPIO_Z_ENABLE_CONFIG_04_0
+#define GPIO_Z_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x11480)
+#define GPIO_Z_ENABLE_CONFIG_04_0_SECURE                        0x0
+#define GPIO_Z_ENABLE_CONFIG_04_0_DUAL                  0x0
+#define GPIO_Z_ENABLE_CONFIG_04_0_SCR                   GPIO_Z_SCR_04_0
+#define GPIO_Z_ENABLE_CONFIG_04_0_SCRREG                        GPIO_Z_SCR_04_0
+#define GPIO_Z_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
+#define GPIO_Z_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
+#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Z_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x11484)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_Z_SCR_04_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_Z_SCR_04_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INPUT_04_0
+#define GPIO_Z_INPUT_04_0                       MK_ADDR_CONST(0x11488)
+#define GPIO_Z_INPUT_04_0_SECURE                        0x0
+#define GPIO_Z_INPUT_04_0_DUAL                  0x0
+#define GPIO_Z_INPUT_04_0_SCR                   GPIO_Z_SCR_04_0
+#define GPIO_Z_INPUT_04_0_SCRREG                        GPIO_Z_SCR_04_0
+#define GPIO_Z_INPUT_04_0_WORD_COUNT                    0x1
+#define GPIO_Z_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Z_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_Z_INPUT_04_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Z_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Z_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_OUTPUT_CONTROL_04_0
+#define GPIO_Z_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1148c)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_SECURE                       0x0
+#define GPIO_Z_OUTPUT_CONTROL_04_0_DUAL                         0x0
+#define GPIO_Z_OUTPUT_CONTROL_04_0_SCR                  GPIO_Z_SCR_04_0
+#define GPIO_Z_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_Z_SCR_04_0
+#define GPIO_Z_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
+#define GPIO_Z_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Z_OUTPUT_VALUE_04_0
+#define GPIO_Z_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x11490)
+#define GPIO_Z_OUTPUT_VALUE_04_0_SECURE                         0x0
+#define GPIO_Z_OUTPUT_VALUE_04_0_DUAL                   0x0
+#define GPIO_Z_OUTPUT_VALUE_04_0_SCR                    GPIO_Z_SCR_04_0
+#define GPIO_Z_OUTPUT_VALUE_04_0_SCRREG                         GPIO_Z_SCR_04_0
+#define GPIO_Z_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
+#define GPIO_Z_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INTERRUPT_CLEAR_04_0
+#define GPIO_Z_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x11494)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_SECURE                      0x0
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_DUAL                        0x0
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_SCR                         GPIO_Z_SCR_04_0
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_Z_SCR_04_0
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x11498
+
+// Reserved address 0x1149c
+
+// Register GPIO_Z_ENABLE_CONFIG_05_0
+#define GPIO_Z_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x114a0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_SECURE                        0x0
+#define GPIO_Z_ENABLE_CONFIG_05_0_DUAL                  0x0
+#define GPIO_Z_ENABLE_CONFIG_05_0_SCR                   GPIO_Z_SCR_05_0
+#define GPIO_Z_ENABLE_CONFIG_05_0_SCRREG                        GPIO_Z_SCR_05_0
+#define GPIO_Z_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
+#define GPIO_Z_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
+#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Z_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x114a4)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_Z_SCR_05_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_Z_SCR_05_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INPUT_05_0
+#define GPIO_Z_INPUT_05_0                       MK_ADDR_CONST(0x114a8)
+#define GPIO_Z_INPUT_05_0_SECURE                        0x0
+#define GPIO_Z_INPUT_05_0_DUAL                  0x0
+#define GPIO_Z_INPUT_05_0_SCR                   GPIO_Z_SCR_05_0
+#define GPIO_Z_INPUT_05_0_SCRREG                        GPIO_Z_SCR_05_0
+#define GPIO_Z_INPUT_05_0_WORD_COUNT                    0x1
+#define GPIO_Z_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Z_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_Z_INPUT_05_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Z_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Z_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_OUTPUT_CONTROL_05_0
+#define GPIO_Z_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x114ac)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_SECURE                       0x0
+#define GPIO_Z_OUTPUT_CONTROL_05_0_DUAL                         0x0
+#define GPIO_Z_OUTPUT_CONTROL_05_0_SCR                  GPIO_Z_SCR_05_0
+#define GPIO_Z_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_Z_SCR_05_0
+#define GPIO_Z_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
+#define GPIO_Z_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Z_OUTPUT_VALUE_05_0
+#define GPIO_Z_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x114b0)
+#define GPIO_Z_OUTPUT_VALUE_05_0_SECURE                         0x0
+#define GPIO_Z_OUTPUT_VALUE_05_0_DUAL                   0x0
+#define GPIO_Z_OUTPUT_VALUE_05_0_SCR                    GPIO_Z_SCR_05_0
+#define GPIO_Z_OUTPUT_VALUE_05_0_SCRREG                         GPIO_Z_SCR_05_0
+#define GPIO_Z_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
+#define GPIO_Z_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INTERRUPT_CLEAR_05_0
+#define GPIO_Z_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x114b4)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_SECURE                      0x0
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_DUAL                        0x0
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_SCR                         GPIO_Z_SCR_05_0
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_Z_SCR_05_0
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x114b8
+
+// Reserved address 0x114bc
+
+// Register GPIO_Z_ENABLE_CONFIG_06_0
+#define GPIO_Z_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x114c0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_SECURE                        0x0
+#define GPIO_Z_ENABLE_CONFIG_06_0_DUAL                  0x0
+#define GPIO_Z_ENABLE_CONFIG_06_0_SCR                   GPIO_Z_SCR_06_0
+#define GPIO_Z_ENABLE_CONFIG_06_0_SCRREG                        GPIO_Z_SCR_06_0
+#define GPIO_Z_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
+#define GPIO_Z_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
+#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Z_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x114c4)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_Z_SCR_06_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_Z_SCR_06_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INPUT_06_0
+#define GPIO_Z_INPUT_06_0                       MK_ADDR_CONST(0x114c8)
+#define GPIO_Z_INPUT_06_0_SECURE                        0x0
+#define GPIO_Z_INPUT_06_0_DUAL                  0x0
+#define GPIO_Z_INPUT_06_0_SCR                   GPIO_Z_SCR_06_0
+#define GPIO_Z_INPUT_06_0_SCRREG                        GPIO_Z_SCR_06_0
+#define GPIO_Z_INPUT_06_0_WORD_COUNT                    0x1
+#define GPIO_Z_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Z_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_Z_INPUT_06_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Z_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Z_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_OUTPUT_CONTROL_06_0
+#define GPIO_Z_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x114cc)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_SECURE                       0x0
+#define GPIO_Z_OUTPUT_CONTROL_06_0_DUAL                         0x0
+#define GPIO_Z_OUTPUT_CONTROL_06_0_SCR                  GPIO_Z_SCR_06_0
+#define GPIO_Z_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_Z_SCR_06_0
+#define GPIO_Z_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
+#define GPIO_Z_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Z_OUTPUT_VALUE_06_0
+#define GPIO_Z_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x114d0)
+#define GPIO_Z_OUTPUT_VALUE_06_0_SECURE                         0x0
+#define GPIO_Z_OUTPUT_VALUE_06_0_DUAL                   0x0
+#define GPIO_Z_OUTPUT_VALUE_06_0_SCR                    GPIO_Z_SCR_06_0
+#define GPIO_Z_OUTPUT_VALUE_06_0_SCRREG                         GPIO_Z_SCR_06_0
+#define GPIO_Z_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
+#define GPIO_Z_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INTERRUPT_CLEAR_06_0
+#define GPIO_Z_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x114d4)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_SECURE                      0x0
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_DUAL                        0x0
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_SCR                         GPIO_Z_SCR_06_0
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_Z_SCR_06_0
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x114d8
+
+// Reserved address 0x114dc
+
+// Register GPIO_Z_ENABLE_CONFIG_07_0
+#define GPIO_Z_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x114e0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_SECURE                        0x0
+#define GPIO_Z_ENABLE_CONFIG_07_0_DUAL                  0x0
+#define GPIO_Z_ENABLE_CONFIG_07_0_SCR                   GPIO_Z_SCR_07_0
+#define GPIO_Z_ENABLE_CONFIG_07_0_SCRREG                        GPIO_Z_SCR_07_0
+#define GPIO_Z_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
+#define GPIO_Z_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
+#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Z_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Z_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x114e4)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_Z_SCR_07_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_Z_SCR_07_0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Z_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INPUT_07_0
+#define GPIO_Z_INPUT_07_0                       MK_ADDR_CONST(0x114e8)
+#define GPIO_Z_INPUT_07_0_SECURE                        0x0
+#define GPIO_Z_INPUT_07_0_DUAL                  0x0
+#define GPIO_Z_INPUT_07_0_SCR                   GPIO_Z_SCR_07_0
+#define GPIO_Z_INPUT_07_0_SCRREG                        GPIO_Z_SCR_07_0
+#define GPIO_Z_INPUT_07_0_WORD_COUNT                    0x1
+#define GPIO_Z_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Z_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_Z_INPUT_07_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Z_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Z_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Z_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_OUTPUT_CONTROL_07_0
+#define GPIO_Z_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x114ec)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_SECURE                       0x0
+#define GPIO_Z_OUTPUT_CONTROL_07_0_DUAL                         0x0
+#define GPIO_Z_OUTPUT_CONTROL_07_0_SCR                  GPIO_Z_SCR_07_0
+#define GPIO_Z_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_Z_SCR_07_0
+#define GPIO_Z_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
+#define GPIO_Z_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Z_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Z_OUTPUT_VALUE_07_0
+#define GPIO_Z_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x114f0)
+#define GPIO_Z_OUTPUT_VALUE_07_0_SECURE                         0x0
+#define GPIO_Z_OUTPUT_VALUE_07_0_DUAL                   0x0
+#define GPIO_Z_OUTPUT_VALUE_07_0_SCR                    GPIO_Z_SCR_07_0
+#define GPIO_Z_OUTPUT_VALUE_07_0_SCRREG                         GPIO_Z_SCR_07_0
+#define GPIO_Z_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
+#define GPIO_Z_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Z_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INTERRUPT_CLEAR_07_0
+#define GPIO_Z_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x114f4)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_SECURE                      0x0
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_DUAL                        0x0
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_SCR                         GPIO_Z_SCR_07_0
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_Z_SCR_07_0
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Z_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x114f8
+
+// Reserved address 0x114fc
+
+// Register GPIO_Z_INTERRUPT_STATUS_G0_0
+#define GPIO_Z_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x11500)
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INTERRUPT_STATUS_G1_0
+#define GPIO_Z_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x11504)
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INTERRUPT_STATUS_G2_0
+#define GPIO_Z_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x11508)
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INTERRUPT_STATUS_G3_0
+#define GPIO_Z_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1150c)
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INTERRUPT_STATUS_G4_0
+#define GPIO_Z_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x11510)
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INTERRUPT_STATUS_G5_0
+#define GPIO_Z_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x11514)
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INTERRUPT_STATUS_G6_0
+#define GPIO_Z_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x11518)
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Z_INTERRUPT_STATUS_G7_0
+#define GPIO_Z_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1151c)
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Z_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x11520
+
+// Reserved address 0x11524
+
+// Reserved address 0x11528
+
+// Reserved address 0x1152c
+
+// Reserved address 0x11530
+
+// Reserved address 0x11534
+
+// Reserved address 0x11538
+
+// Reserved address 0x1153c
+
+// Reserved address 0x11540
+
+// Reserved address 0x11544
+
+// Reserved address 0x11548
+
+// Reserved address 0x1154c
+
+// Reserved address 0x11550
+
+// Reserved address 0x11554
+
+// Reserved address 0x11558
+
+// Reserved address 0x1155c
+
+// Reserved address 0x11560
+
+// Reserved address 0x11564
+
+// Reserved address 0x11568
+
+// Reserved address 0x1156c
+
+// Reserved address 0x11570
+
+// Reserved address 0x11574
+
+// Reserved address 0x11578
+
+// Reserved address 0x1157c
+
+// Reserved address 0x11580
+
+// Reserved address 0x11584
+
+// Reserved address 0x11588
+
+// Reserved address 0x1158c
+
+// Reserved address 0x11590
+
+// Reserved address 0x11594
+
+// Reserved address 0x11598
+
+// Reserved address 0x1159c
+
+// Reserved address 0x115a0
+
+// Reserved address 0x115a4
+
+// Reserved address 0x115a8
+
+// Reserved address 0x115ac
+
+// Reserved address 0x115b0
+
+// Reserved address 0x115b4
+
+// Reserved address 0x115b8
+
+// Reserved address 0x115bc
+
+// Reserved address 0x115c0
+
+// Reserved address 0x115c4
+
+// Reserved address 0x115c8
+
+// Reserved address 0x115cc
+
+// Reserved address 0x115d0
+
+// Reserved address 0x115d4
+
+// Reserved address 0x115d8
+
+// Reserved address 0x115dc
+
+// Reserved address 0x115e0
+
+// Reserved address 0x115e4
+
+// Reserved address 0x115e8
+
+// Reserved address 0x115ec
+
+// Reserved address 0x115f0
+
+// Reserved address 0x115f4
+
+// Reserved address 0x115f8
+
+// Reserved address 0x115fc
+
+// Register GPIO_M_ENABLE_CONFIG_00_0
+#define GPIO_M_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x12000)
+#define GPIO_M_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_M_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_M_ENABLE_CONFIG_00_0_SCR                   GPIO_M_SCR_00_0
+#define GPIO_M_ENABLE_CONFIG_00_0_SCRREG                        GPIO_M_SCR_00_0
+#define GPIO_M_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_M_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_M_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x12004)
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_M_SCR_00_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_M_SCR_00_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_M_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INPUT_00_0
+#define GPIO_M_INPUT_00_0                       MK_ADDR_CONST(0x12008)
+#define GPIO_M_INPUT_00_0_SECURE                        0x0
+#define GPIO_M_INPUT_00_0_DUAL                  0x0
+#define GPIO_M_INPUT_00_0_SCR                   GPIO_M_SCR_00_0
+#define GPIO_M_INPUT_00_0_SCRREG                        GPIO_M_SCR_00_0
+#define GPIO_M_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_M_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_M_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_M_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_M_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_M_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_OUTPUT_CONTROL_00_0
+#define GPIO_M_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1200c)
+#define GPIO_M_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_M_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_M_OUTPUT_CONTROL_00_0_SCR                  GPIO_M_SCR_00_0
+#define GPIO_M_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_M_SCR_00_0
+#define GPIO_M_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_M_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_M_OUTPUT_VALUE_00_0
+#define GPIO_M_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x12010)
+#define GPIO_M_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_M_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_M_OUTPUT_VALUE_00_0_SCR                    GPIO_M_SCR_00_0
+#define GPIO_M_OUTPUT_VALUE_00_0_SCRREG                         GPIO_M_SCR_00_0
+#define GPIO_M_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_M_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INTERRUPT_CLEAR_00_0
+#define GPIO_M_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x12014)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_M_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_M_INTERRUPT_CLEAR_00_0_SCR                         GPIO_M_SCR_00_0
+#define GPIO_M_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_M_SCR_00_0
+#define GPIO_M_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_M_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12018
+
+// Reserved address 0x1201c
+
+// Register GPIO_M_ENABLE_CONFIG_01_0
+#define GPIO_M_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x12020)
+#define GPIO_M_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_M_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_M_ENABLE_CONFIG_01_0_SCR                   GPIO_M_SCR_01_0
+#define GPIO_M_ENABLE_CONFIG_01_0_SCRREG                        GPIO_M_SCR_01_0
+#define GPIO_M_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_M_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_M_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x12024)
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_M_SCR_01_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_M_SCR_01_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_M_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INPUT_01_0
+#define GPIO_M_INPUT_01_0                       MK_ADDR_CONST(0x12028)
+#define GPIO_M_INPUT_01_0_SECURE                        0x0
+#define GPIO_M_INPUT_01_0_DUAL                  0x0
+#define GPIO_M_INPUT_01_0_SCR                   GPIO_M_SCR_01_0
+#define GPIO_M_INPUT_01_0_SCRREG                        GPIO_M_SCR_01_0
+#define GPIO_M_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_M_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_M_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_M_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_M_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_M_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_OUTPUT_CONTROL_01_0
+#define GPIO_M_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1202c)
+#define GPIO_M_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_M_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_M_OUTPUT_CONTROL_01_0_SCR                  GPIO_M_SCR_01_0
+#define GPIO_M_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_M_SCR_01_0
+#define GPIO_M_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_M_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_M_OUTPUT_VALUE_01_0
+#define GPIO_M_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x12030)
+#define GPIO_M_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_M_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_M_OUTPUT_VALUE_01_0_SCR                    GPIO_M_SCR_01_0
+#define GPIO_M_OUTPUT_VALUE_01_0_SCRREG                         GPIO_M_SCR_01_0
+#define GPIO_M_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_M_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INTERRUPT_CLEAR_01_0
+#define GPIO_M_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x12034)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_M_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_M_INTERRUPT_CLEAR_01_0_SCR                         GPIO_M_SCR_01_0
+#define GPIO_M_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_M_SCR_01_0
+#define GPIO_M_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_M_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12038
+
+// Reserved address 0x1203c
+
+// Register GPIO_M_ENABLE_CONFIG_02_0
+#define GPIO_M_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x12040)
+#define GPIO_M_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_M_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_M_ENABLE_CONFIG_02_0_SCR                   GPIO_M_SCR_02_0
+#define GPIO_M_ENABLE_CONFIG_02_0_SCRREG                        GPIO_M_SCR_02_0
+#define GPIO_M_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_M_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_M_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x12044)
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_M_SCR_02_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_M_SCR_02_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_M_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INPUT_02_0
+#define GPIO_M_INPUT_02_0                       MK_ADDR_CONST(0x12048)
+#define GPIO_M_INPUT_02_0_SECURE                        0x0
+#define GPIO_M_INPUT_02_0_DUAL                  0x0
+#define GPIO_M_INPUT_02_0_SCR                   GPIO_M_SCR_02_0
+#define GPIO_M_INPUT_02_0_SCRREG                        GPIO_M_SCR_02_0
+#define GPIO_M_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_M_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_M_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_M_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_M_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_M_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_OUTPUT_CONTROL_02_0
+#define GPIO_M_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1204c)
+#define GPIO_M_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_M_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_M_OUTPUT_CONTROL_02_0_SCR                  GPIO_M_SCR_02_0
+#define GPIO_M_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_M_SCR_02_0
+#define GPIO_M_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_M_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_M_OUTPUT_VALUE_02_0
+#define GPIO_M_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x12050)
+#define GPIO_M_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_M_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_M_OUTPUT_VALUE_02_0_SCR                    GPIO_M_SCR_02_0
+#define GPIO_M_OUTPUT_VALUE_02_0_SCRREG                         GPIO_M_SCR_02_0
+#define GPIO_M_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_M_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INTERRUPT_CLEAR_02_0
+#define GPIO_M_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x12054)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_M_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_M_INTERRUPT_CLEAR_02_0_SCR                         GPIO_M_SCR_02_0
+#define GPIO_M_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_M_SCR_02_0
+#define GPIO_M_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_M_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12058
+
+// Reserved address 0x1205c
+
+// Register GPIO_M_ENABLE_CONFIG_03_0
+#define GPIO_M_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x12060)
+#define GPIO_M_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_M_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_M_ENABLE_CONFIG_03_0_SCR                   GPIO_M_SCR_03_0
+#define GPIO_M_ENABLE_CONFIG_03_0_SCRREG                        GPIO_M_SCR_03_0
+#define GPIO_M_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_M_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_M_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x12064)
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_M_SCR_03_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_M_SCR_03_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_M_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INPUT_03_0
+#define GPIO_M_INPUT_03_0                       MK_ADDR_CONST(0x12068)
+#define GPIO_M_INPUT_03_0_SECURE                        0x0
+#define GPIO_M_INPUT_03_0_DUAL                  0x0
+#define GPIO_M_INPUT_03_0_SCR                   GPIO_M_SCR_03_0
+#define GPIO_M_INPUT_03_0_SCRREG                        GPIO_M_SCR_03_0
+#define GPIO_M_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_M_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_M_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_M_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_M_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_M_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_OUTPUT_CONTROL_03_0
+#define GPIO_M_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1206c)
+#define GPIO_M_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_M_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_M_OUTPUT_CONTROL_03_0_SCR                  GPIO_M_SCR_03_0
+#define GPIO_M_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_M_SCR_03_0
+#define GPIO_M_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_M_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_M_OUTPUT_VALUE_03_0
+#define GPIO_M_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x12070)
+#define GPIO_M_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_M_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_M_OUTPUT_VALUE_03_0_SCR                    GPIO_M_SCR_03_0
+#define GPIO_M_OUTPUT_VALUE_03_0_SCRREG                         GPIO_M_SCR_03_0
+#define GPIO_M_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_M_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INTERRUPT_CLEAR_03_0
+#define GPIO_M_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x12074)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_M_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_M_INTERRUPT_CLEAR_03_0_SCR                         GPIO_M_SCR_03_0
+#define GPIO_M_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_M_SCR_03_0
+#define GPIO_M_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_M_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12078
+
+// Reserved address 0x1207c
+
+// Register GPIO_M_ENABLE_CONFIG_04_0
+#define GPIO_M_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x12080)
+#define GPIO_M_ENABLE_CONFIG_04_0_SECURE                        0x0
+#define GPIO_M_ENABLE_CONFIG_04_0_DUAL                  0x0
+#define GPIO_M_ENABLE_CONFIG_04_0_SCR                   GPIO_M_SCR_04_0
+#define GPIO_M_ENABLE_CONFIG_04_0_SCRREG                        GPIO_M_SCR_04_0
+#define GPIO_M_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
+#define GPIO_M_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
+#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_M_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x12084)
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_M_SCR_04_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_M_SCR_04_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_M_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INPUT_04_0
+#define GPIO_M_INPUT_04_0                       MK_ADDR_CONST(0x12088)
+#define GPIO_M_INPUT_04_0_SECURE                        0x0
+#define GPIO_M_INPUT_04_0_DUAL                  0x0
+#define GPIO_M_INPUT_04_0_SCR                   GPIO_M_SCR_04_0
+#define GPIO_M_INPUT_04_0_SCRREG                        GPIO_M_SCR_04_0
+#define GPIO_M_INPUT_04_0_WORD_COUNT                    0x1
+#define GPIO_M_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_M_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_M_INPUT_04_0_GPIO_IN_RANGE                 0:0
+#define GPIO_M_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_M_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_OUTPUT_CONTROL_04_0
+#define GPIO_M_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1208c)
+#define GPIO_M_OUTPUT_CONTROL_04_0_SECURE                       0x0
+#define GPIO_M_OUTPUT_CONTROL_04_0_DUAL                         0x0
+#define GPIO_M_OUTPUT_CONTROL_04_0_SCR                  GPIO_M_SCR_04_0
+#define GPIO_M_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_M_SCR_04_0
+#define GPIO_M_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
+#define GPIO_M_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_M_OUTPUT_VALUE_04_0
+#define GPIO_M_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x12090)
+#define GPIO_M_OUTPUT_VALUE_04_0_SECURE                         0x0
+#define GPIO_M_OUTPUT_VALUE_04_0_DUAL                   0x0
+#define GPIO_M_OUTPUT_VALUE_04_0_SCR                    GPIO_M_SCR_04_0
+#define GPIO_M_OUTPUT_VALUE_04_0_SCRREG                         GPIO_M_SCR_04_0
+#define GPIO_M_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
+#define GPIO_M_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INTERRUPT_CLEAR_04_0
+#define GPIO_M_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x12094)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_SECURE                      0x0
+#define GPIO_M_INTERRUPT_CLEAR_04_0_DUAL                        0x0
+#define GPIO_M_INTERRUPT_CLEAR_04_0_SCR                         GPIO_M_SCR_04_0
+#define GPIO_M_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_M_SCR_04_0
+#define GPIO_M_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
+#define GPIO_M_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12098
+
+// Reserved address 0x1209c
+
+// Register GPIO_M_ENABLE_CONFIG_05_0
+#define GPIO_M_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x120a0)
+#define GPIO_M_ENABLE_CONFIG_05_0_SECURE                        0x0
+#define GPIO_M_ENABLE_CONFIG_05_0_DUAL                  0x0
+#define GPIO_M_ENABLE_CONFIG_05_0_SCR                   GPIO_M_SCR_05_0
+#define GPIO_M_ENABLE_CONFIG_05_0_SCRREG                        GPIO_M_SCR_05_0
+#define GPIO_M_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
+#define GPIO_M_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
+#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_M_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x120a4)
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_M_SCR_05_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_M_SCR_05_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_M_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INPUT_05_0
+#define GPIO_M_INPUT_05_0                       MK_ADDR_CONST(0x120a8)
+#define GPIO_M_INPUT_05_0_SECURE                        0x0
+#define GPIO_M_INPUT_05_0_DUAL                  0x0
+#define GPIO_M_INPUT_05_0_SCR                   GPIO_M_SCR_05_0
+#define GPIO_M_INPUT_05_0_SCRREG                        GPIO_M_SCR_05_0
+#define GPIO_M_INPUT_05_0_WORD_COUNT                    0x1
+#define GPIO_M_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_M_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_M_INPUT_05_0_GPIO_IN_RANGE                 0:0
+#define GPIO_M_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_M_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_OUTPUT_CONTROL_05_0
+#define GPIO_M_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x120ac)
+#define GPIO_M_OUTPUT_CONTROL_05_0_SECURE                       0x0
+#define GPIO_M_OUTPUT_CONTROL_05_0_DUAL                         0x0
+#define GPIO_M_OUTPUT_CONTROL_05_0_SCR                  GPIO_M_SCR_05_0
+#define GPIO_M_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_M_SCR_05_0
+#define GPIO_M_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
+#define GPIO_M_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_M_OUTPUT_VALUE_05_0
+#define GPIO_M_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x120b0)
+#define GPIO_M_OUTPUT_VALUE_05_0_SECURE                         0x0
+#define GPIO_M_OUTPUT_VALUE_05_0_DUAL                   0x0
+#define GPIO_M_OUTPUT_VALUE_05_0_SCR                    GPIO_M_SCR_05_0
+#define GPIO_M_OUTPUT_VALUE_05_0_SCRREG                         GPIO_M_SCR_05_0
+#define GPIO_M_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
+#define GPIO_M_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INTERRUPT_CLEAR_05_0
+#define GPIO_M_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x120b4)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_SECURE                      0x0
+#define GPIO_M_INTERRUPT_CLEAR_05_0_DUAL                        0x0
+#define GPIO_M_INTERRUPT_CLEAR_05_0_SCR                         GPIO_M_SCR_05_0
+#define GPIO_M_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_M_SCR_05_0
+#define GPIO_M_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
+#define GPIO_M_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x120b8
+
+// Reserved address 0x120bc
+
+// Register GPIO_M_ENABLE_CONFIG_06_0
+#define GPIO_M_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x120c0)
+#define GPIO_M_ENABLE_CONFIG_06_0_SECURE                        0x0
+#define GPIO_M_ENABLE_CONFIG_06_0_DUAL                  0x0
+#define GPIO_M_ENABLE_CONFIG_06_0_SCR                   GPIO_M_SCR_06_0
+#define GPIO_M_ENABLE_CONFIG_06_0_SCRREG                        GPIO_M_SCR_06_0
+#define GPIO_M_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
+#define GPIO_M_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
+#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_M_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x120c4)
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_M_SCR_06_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_M_SCR_06_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_M_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INPUT_06_0
+#define GPIO_M_INPUT_06_0                       MK_ADDR_CONST(0x120c8)
+#define GPIO_M_INPUT_06_0_SECURE                        0x0
+#define GPIO_M_INPUT_06_0_DUAL                  0x0
+#define GPIO_M_INPUT_06_0_SCR                   GPIO_M_SCR_06_0
+#define GPIO_M_INPUT_06_0_SCRREG                        GPIO_M_SCR_06_0
+#define GPIO_M_INPUT_06_0_WORD_COUNT                    0x1
+#define GPIO_M_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_M_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_M_INPUT_06_0_GPIO_IN_RANGE                 0:0
+#define GPIO_M_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_M_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_OUTPUT_CONTROL_06_0
+#define GPIO_M_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x120cc)
+#define GPIO_M_OUTPUT_CONTROL_06_0_SECURE                       0x0
+#define GPIO_M_OUTPUT_CONTROL_06_0_DUAL                         0x0
+#define GPIO_M_OUTPUT_CONTROL_06_0_SCR                  GPIO_M_SCR_06_0
+#define GPIO_M_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_M_SCR_06_0
+#define GPIO_M_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
+#define GPIO_M_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_M_OUTPUT_VALUE_06_0
+#define GPIO_M_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x120d0)
+#define GPIO_M_OUTPUT_VALUE_06_0_SECURE                         0x0
+#define GPIO_M_OUTPUT_VALUE_06_0_DUAL                   0x0
+#define GPIO_M_OUTPUT_VALUE_06_0_SCR                    GPIO_M_SCR_06_0
+#define GPIO_M_OUTPUT_VALUE_06_0_SCRREG                         GPIO_M_SCR_06_0
+#define GPIO_M_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
+#define GPIO_M_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INTERRUPT_CLEAR_06_0
+#define GPIO_M_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x120d4)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_SECURE                      0x0
+#define GPIO_M_INTERRUPT_CLEAR_06_0_DUAL                        0x0
+#define GPIO_M_INTERRUPT_CLEAR_06_0_SCR                         GPIO_M_SCR_06_0
+#define GPIO_M_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_M_SCR_06_0
+#define GPIO_M_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
+#define GPIO_M_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x120d8
+
+// Reserved address 0x120dc
+
+// Register GPIO_M_ENABLE_CONFIG_07_0
+#define GPIO_M_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x120e0)
+#define GPIO_M_ENABLE_CONFIG_07_0_SECURE                        0x0
+#define GPIO_M_ENABLE_CONFIG_07_0_DUAL                  0x0
+#define GPIO_M_ENABLE_CONFIG_07_0_SCR                   GPIO_M_SCR_07_0
+#define GPIO_M_ENABLE_CONFIG_07_0_SCRREG                        GPIO_M_SCR_07_0
+#define GPIO_M_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
+#define GPIO_M_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
+#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_M_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_M_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x120e4)
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_M_SCR_07_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_M_SCR_07_0
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_M_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INPUT_07_0
+#define GPIO_M_INPUT_07_0                       MK_ADDR_CONST(0x120e8)
+#define GPIO_M_INPUT_07_0_SECURE                        0x0
+#define GPIO_M_INPUT_07_0_DUAL                  0x0
+#define GPIO_M_INPUT_07_0_SCR                   GPIO_M_SCR_07_0
+#define GPIO_M_INPUT_07_0_SCRREG                        GPIO_M_SCR_07_0
+#define GPIO_M_INPUT_07_0_WORD_COUNT                    0x1
+#define GPIO_M_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_M_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_M_INPUT_07_0_GPIO_IN_RANGE                 0:0
+#define GPIO_M_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_M_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_M_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_M_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_OUTPUT_CONTROL_07_0
+#define GPIO_M_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x120ec)
+#define GPIO_M_OUTPUT_CONTROL_07_0_SECURE                       0x0
+#define GPIO_M_OUTPUT_CONTROL_07_0_DUAL                         0x0
+#define GPIO_M_OUTPUT_CONTROL_07_0_SCR                  GPIO_M_SCR_07_0
+#define GPIO_M_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_M_SCR_07_0
+#define GPIO_M_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
+#define GPIO_M_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_M_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_M_OUTPUT_VALUE_07_0
+#define GPIO_M_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x120f0)
+#define GPIO_M_OUTPUT_VALUE_07_0_SECURE                         0x0
+#define GPIO_M_OUTPUT_VALUE_07_0_DUAL                   0x0
+#define GPIO_M_OUTPUT_VALUE_07_0_SCR                    GPIO_M_SCR_07_0
+#define GPIO_M_OUTPUT_VALUE_07_0_SCRREG                         GPIO_M_SCR_07_0
+#define GPIO_M_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
+#define GPIO_M_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_M_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INTERRUPT_CLEAR_07_0
+#define GPIO_M_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x120f4)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_SECURE                      0x0
+#define GPIO_M_INTERRUPT_CLEAR_07_0_DUAL                        0x0
+#define GPIO_M_INTERRUPT_CLEAR_07_0_SCR                         GPIO_M_SCR_07_0
+#define GPIO_M_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_M_SCR_07_0
+#define GPIO_M_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
+#define GPIO_M_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_M_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x120f8
+
+// Reserved address 0x120fc
+
+// Register GPIO_M_INTERRUPT_STATUS_G0_0
+#define GPIO_M_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x12100)
+#define GPIO_M_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_M_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_M_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_M_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_M_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_M_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INTERRUPT_STATUS_G1_0
+#define GPIO_M_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x12104)
+#define GPIO_M_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_M_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_M_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_M_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_M_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_M_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INTERRUPT_STATUS_G2_0
+#define GPIO_M_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x12108)
+#define GPIO_M_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_M_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_M_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_M_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_M_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_M_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INTERRUPT_STATUS_G3_0
+#define GPIO_M_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1210c)
+#define GPIO_M_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_M_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_M_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_M_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_M_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_M_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INTERRUPT_STATUS_G4_0
+#define GPIO_M_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x12110)
+#define GPIO_M_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_M_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_M_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_M_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_M_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_M_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INTERRUPT_STATUS_G5_0
+#define GPIO_M_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x12114)
+#define GPIO_M_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_M_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_M_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_M_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_M_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_M_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INTERRUPT_STATUS_G6_0
+#define GPIO_M_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x12118)
+#define GPIO_M_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_M_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_M_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_M_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_M_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_M_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_M_INTERRUPT_STATUS_G7_0
+#define GPIO_M_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1211c)
+#define GPIO_M_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_M_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_M_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_M_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_M_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_M_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_M_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x12120
+
+// Reserved address 0x12124
+
+// Reserved address 0x12128
+
+// Reserved address 0x1212c
+
+// Reserved address 0x12130
+
+// Reserved address 0x12134
+
+// Reserved address 0x12138
+
+// Reserved address 0x1213c
+
+// Reserved address 0x12140
+
+// Reserved address 0x12144
+
+// Reserved address 0x12148
+
+// Reserved address 0x1214c
+
+// Reserved address 0x12150
+
+// Reserved address 0x12154
+
+// Reserved address 0x12158
+
+// Reserved address 0x1215c
+
+// Reserved address 0x12160
+
+// Reserved address 0x12164
+
+// Reserved address 0x12168
+
+// Reserved address 0x1216c
+
+// Reserved address 0x12170
+
+// Reserved address 0x12174
+
+// Reserved address 0x12178
+
+// Reserved address 0x1217c
+
+// Reserved address 0x12180
+
+// Reserved address 0x12184
+
+// Reserved address 0x12188
+
+// Reserved address 0x1218c
+
+// Reserved address 0x12190
+
+// Reserved address 0x12194
+
+// Reserved address 0x12198
+
+// Reserved address 0x1219c
+
+// Reserved address 0x121a0
+
+// Reserved address 0x121a4
+
+// Reserved address 0x121a8
+
+// Reserved address 0x121ac
+
+// Reserved address 0x121b0
+
+// Reserved address 0x121b4
+
+// Reserved address 0x121b8
+
+// Reserved address 0x121bc
+
+// Reserved address 0x121c0
+
+// Reserved address 0x121c4
+
+// Reserved address 0x121c8
+
+// Reserved address 0x121cc
+
+// Reserved address 0x121d0
+
+// Reserved address 0x121d4
+
+// Reserved address 0x121d8
+
+// Reserved address 0x121dc
+
+// Reserved address 0x121e0
+
+// Reserved address 0x121e4
+
+// Reserved address 0x121e8
+
+// Reserved address 0x121ec
+
+// Reserved address 0x121f0
+
+// Reserved address 0x121f4
+
+// Reserved address 0x121f8
+
+// Reserved address 0x121fc
+
+// Register GPIO_N_ENABLE_CONFIG_00_0
+#define GPIO_N_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x12200)
+#define GPIO_N_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_N_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_N_ENABLE_CONFIG_00_0_SCR                   GPIO_N_SCR_00_0
+#define GPIO_N_ENABLE_CONFIG_00_0_SCRREG                        GPIO_N_SCR_00_0
+#define GPIO_N_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_N_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_N_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x12204)
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_N_SCR_00_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_N_SCR_00_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_N_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INPUT_00_0
+#define GPIO_N_INPUT_00_0                       MK_ADDR_CONST(0x12208)
+#define GPIO_N_INPUT_00_0_SECURE                        0x0
+#define GPIO_N_INPUT_00_0_DUAL                  0x0
+#define GPIO_N_INPUT_00_0_SCR                   GPIO_N_SCR_00_0
+#define GPIO_N_INPUT_00_0_SCRREG                        GPIO_N_SCR_00_0
+#define GPIO_N_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_N_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_N_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_N_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_N_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_N_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_OUTPUT_CONTROL_00_0
+#define GPIO_N_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1220c)
+#define GPIO_N_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_N_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_N_OUTPUT_CONTROL_00_0_SCR                  GPIO_N_SCR_00_0
+#define GPIO_N_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_N_SCR_00_0
+#define GPIO_N_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_N_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_N_OUTPUT_VALUE_00_0
+#define GPIO_N_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x12210)
+#define GPIO_N_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_N_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_N_OUTPUT_VALUE_00_0_SCR                    GPIO_N_SCR_00_0
+#define GPIO_N_OUTPUT_VALUE_00_0_SCRREG                         GPIO_N_SCR_00_0
+#define GPIO_N_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_N_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INTERRUPT_CLEAR_00_0
+#define GPIO_N_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x12214)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_N_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_N_INTERRUPT_CLEAR_00_0_SCR                         GPIO_N_SCR_00_0
+#define GPIO_N_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_N_SCR_00_0
+#define GPIO_N_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_N_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12218
+
+// Reserved address 0x1221c
+
+// Register GPIO_N_ENABLE_CONFIG_01_0
+#define GPIO_N_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x12220)
+#define GPIO_N_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_N_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_N_ENABLE_CONFIG_01_0_SCR                   GPIO_N_SCR_01_0
+#define GPIO_N_ENABLE_CONFIG_01_0_SCRREG                        GPIO_N_SCR_01_0
+#define GPIO_N_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_N_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_N_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x12224)
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_N_SCR_01_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_N_SCR_01_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_N_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INPUT_01_0
+#define GPIO_N_INPUT_01_0                       MK_ADDR_CONST(0x12228)
+#define GPIO_N_INPUT_01_0_SECURE                        0x0
+#define GPIO_N_INPUT_01_0_DUAL                  0x0
+#define GPIO_N_INPUT_01_0_SCR                   GPIO_N_SCR_01_0
+#define GPIO_N_INPUT_01_0_SCRREG                        GPIO_N_SCR_01_0
+#define GPIO_N_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_N_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_N_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_N_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_N_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_N_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_OUTPUT_CONTROL_01_0
+#define GPIO_N_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1222c)
+#define GPIO_N_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_N_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_N_OUTPUT_CONTROL_01_0_SCR                  GPIO_N_SCR_01_0
+#define GPIO_N_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_N_SCR_01_0
+#define GPIO_N_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_N_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_N_OUTPUT_VALUE_01_0
+#define GPIO_N_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x12230)
+#define GPIO_N_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_N_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_N_OUTPUT_VALUE_01_0_SCR                    GPIO_N_SCR_01_0
+#define GPIO_N_OUTPUT_VALUE_01_0_SCRREG                         GPIO_N_SCR_01_0
+#define GPIO_N_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_N_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INTERRUPT_CLEAR_01_0
+#define GPIO_N_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x12234)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_N_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_N_INTERRUPT_CLEAR_01_0_SCR                         GPIO_N_SCR_01_0
+#define GPIO_N_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_N_SCR_01_0
+#define GPIO_N_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_N_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12238
+
+// Reserved address 0x1223c
+
+// Register GPIO_N_ENABLE_CONFIG_02_0
+#define GPIO_N_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x12240)
+#define GPIO_N_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_N_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_N_ENABLE_CONFIG_02_0_SCR                   GPIO_N_SCR_02_0
+#define GPIO_N_ENABLE_CONFIG_02_0_SCRREG                        GPIO_N_SCR_02_0
+#define GPIO_N_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_N_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_N_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x12244)
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_N_SCR_02_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_N_SCR_02_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_N_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INPUT_02_0
+#define GPIO_N_INPUT_02_0                       MK_ADDR_CONST(0x12248)
+#define GPIO_N_INPUT_02_0_SECURE                        0x0
+#define GPIO_N_INPUT_02_0_DUAL                  0x0
+#define GPIO_N_INPUT_02_0_SCR                   GPIO_N_SCR_02_0
+#define GPIO_N_INPUT_02_0_SCRREG                        GPIO_N_SCR_02_0
+#define GPIO_N_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_N_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_N_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_N_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_N_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_N_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_OUTPUT_CONTROL_02_0
+#define GPIO_N_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1224c)
+#define GPIO_N_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_N_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_N_OUTPUT_CONTROL_02_0_SCR                  GPIO_N_SCR_02_0
+#define GPIO_N_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_N_SCR_02_0
+#define GPIO_N_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_N_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_N_OUTPUT_VALUE_02_0
+#define GPIO_N_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x12250)
+#define GPIO_N_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_N_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_N_OUTPUT_VALUE_02_0_SCR                    GPIO_N_SCR_02_0
+#define GPIO_N_OUTPUT_VALUE_02_0_SCRREG                         GPIO_N_SCR_02_0
+#define GPIO_N_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_N_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INTERRUPT_CLEAR_02_0
+#define GPIO_N_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x12254)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_N_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_N_INTERRUPT_CLEAR_02_0_SCR                         GPIO_N_SCR_02_0
+#define GPIO_N_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_N_SCR_02_0
+#define GPIO_N_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_N_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12258
+
+// Reserved address 0x1225c
+
+// Register GPIO_N_ENABLE_CONFIG_03_0
+#define GPIO_N_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x12260)
+#define GPIO_N_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_N_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_N_ENABLE_CONFIG_03_0_SCR                   GPIO_N_SCR_03_0
+#define GPIO_N_ENABLE_CONFIG_03_0_SCRREG                        GPIO_N_SCR_03_0
+#define GPIO_N_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_N_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_N_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x12264)
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_N_SCR_03_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_N_SCR_03_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_N_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INPUT_03_0
+#define GPIO_N_INPUT_03_0                       MK_ADDR_CONST(0x12268)
+#define GPIO_N_INPUT_03_0_SECURE                        0x0
+#define GPIO_N_INPUT_03_0_DUAL                  0x0
+#define GPIO_N_INPUT_03_0_SCR                   GPIO_N_SCR_03_0
+#define GPIO_N_INPUT_03_0_SCRREG                        GPIO_N_SCR_03_0
+#define GPIO_N_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_N_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_N_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_N_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_N_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_N_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_OUTPUT_CONTROL_03_0
+#define GPIO_N_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1226c)
+#define GPIO_N_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_N_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_N_OUTPUT_CONTROL_03_0_SCR                  GPIO_N_SCR_03_0
+#define GPIO_N_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_N_SCR_03_0
+#define GPIO_N_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_N_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_N_OUTPUT_VALUE_03_0
+#define GPIO_N_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x12270)
+#define GPIO_N_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_N_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_N_OUTPUT_VALUE_03_0_SCR                    GPIO_N_SCR_03_0
+#define GPIO_N_OUTPUT_VALUE_03_0_SCRREG                         GPIO_N_SCR_03_0
+#define GPIO_N_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_N_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INTERRUPT_CLEAR_03_0
+#define GPIO_N_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x12274)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_N_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_N_INTERRUPT_CLEAR_03_0_SCR                         GPIO_N_SCR_03_0
+#define GPIO_N_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_N_SCR_03_0
+#define GPIO_N_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_N_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12278
+
+// Reserved address 0x1227c
+
+// Register GPIO_N_ENABLE_CONFIG_04_0
+#define GPIO_N_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x12280)
+#define GPIO_N_ENABLE_CONFIG_04_0_SECURE                        0x0
+#define GPIO_N_ENABLE_CONFIG_04_0_DUAL                  0x0
+#define GPIO_N_ENABLE_CONFIG_04_0_SCR                   GPIO_N_SCR_04_0
+#define GPIO_N_ENABLE_CONFIG_04_0_SCRREG                        GPIO_N_SCR_04_0
+#define GPIO_N_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
+#define GPIO_N_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
+#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_N_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x12284)
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_N_SCR_04_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_N_SCR_04_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_N_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INPUT_04_0
+#define GPIO_N_INPUT_04_0                       MK_ADDR_CONST(0x12288)
+#define GPIO_N_INPUT_04_0_SECURE                        0x0
+#define GPIO_N_INPUT_04_0_DUAL                  0x0
+#define GPIO_N_INPUT_04_0_SCR                   GPIO_N_SCR_04_0
+#define GPIO_N_INPUT_04_0_SCRREG                        GPIO_N_SCR_04_0
+#define GPIO_N_INPUT_04_0_WORD_COUNT                    0x1
+#define GPIO_N_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_N_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_N_INPUT_04_0_GPIO_IN_RANGE                 0:0
+#define GPIO_N_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_N_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_OUTPUT_CONTROL_04_0
+#define GPIO_N_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1228c)
+#define GPIO_N_OUTPUT_CONTROL_04_0_SECURE                       0x0
+#define GPIO_N_OUTPUT_CONTROL_04_0_DUAL                         0x0
+#define GPIO_N_OUTPUT_CONTROL_04_0_SCR                  GPIO_N_SCR_04_0
+#define GPIO_N_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_N_SCR_04_0
+#define GPIO_N_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
+#define GPIO_N_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_N_OUTPUT_VALUE_04_0
+#define GPIO_N_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x12290)
+#define GPIO_N_OUTPUT_VALUE_04_0_SECURE                         0x0
+#define GPIO_N_OUTPUT_VALUE_04_0_DUAL                   0x0
+#define GPIO_N_OUTPUT_VALUE_04_0_SCR                    GPIO_N_SCR_04_0
+#define GPIO_N_OUTPUT_VALUE_04_0_SCRREG                         GPIO_N_SCR_04_0
+#define GPIO_N_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
+#define GPIO_N_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INTERRUPT_CLEAR_04_0
+#define GPIO_N_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x12294)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_SECURE                      0x0
+#define GPIO_N_INTERRUPT_CLEAR_04_0_DUAL                        0x0
+#define GPIO_N_INTERRUPT_CLEAR_04_0_SCR                         GPIO_N_SCR_04_0
+#define GPIO_N_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_N_SCR_04_0
+#define GPIO_N_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
+#define GPIO_N_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12298
+
+// Reserved address 0x1229c
+
+// Register GPIO_N_ENABLE_CONFIG_05_0
+#define GPIO_N_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x122a0)
+#define GPIO_N_ENABLE_CONFIG_05_0_SECURE                        0x0
+#define GPIO_N_ENABLE_CONFIG_05_0_DUAL                  0x0
+#define GPIO_N_ENABLE_CONFIG_05_0_SCR                   GPIO_N_SCR_05_0
+#define GPIO_N_ENABLE_CONFIG_05_0_SCRREG                        GPIO_N_SCR_05_0
+#define GPIO_N_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
+#define GPIO_N_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
+#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_N_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x122a4)
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_N_SCR_05_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_N_SCR_05_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_N_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INPUT_05_0
+#define GPIO_N_INPUT_05_0                       MK_ADDR_CONST(0x122a8)
+#define GPIO_N_INPUT_05_0_SECURE                        0x0
+#define GPIO_N_INPUT_05_0_DUAL                  0x0
+#define GPIO_N_INPUT_05_0_SCR                   GPIO_N_SCR_05_0
+#define GPIO_N_INPUT_05_0_SCRREG                        GPIO_N_SCR_05_0
+#define GPIO_N_INPUT_05_0_WORD_COUNT                    0x1
+#define GPIO_N_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_N_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_N_INPUT_05_0_GPIO_IN_RANGE                 0:0
+#define GPIO_N_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_N_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_OUTPUT_CONTROL_05_0
+#define GPIO_N_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x122ac)
+#define GPIO_N_OUTPUT_CONTROL_05_0_SECURE                       0x0
+#define GPIO_N_OUTPUT_CONTROL_05_0_DUAL                         0x0
+#define GPIO_N_OUTPUT_CONTROL_05_0_SCR                  GPIO_N_SCR_05_0
+#define GPIO_N_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_N_SCR_05_0
+#define GPIO_N_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
+#define GPIO_N_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_N_OUTPUT_VALUE_05_0
+#define GPIO_N_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x122b0)
+#define GPIO_N_OUTPUT_VALUE_05_0_SECURE                         0x0
+#define GPIO_N_OUTPUT_VALUE_05_0_DUAL                   0x0
+#define GPIO_N_OUTPUT_VALUE_05_0_SCR                    GPIO_N_SCR_05_0
+#define GPIO_N_OUTPUT_VALUE_05_0_SCRREG                         GPIO_N_SCR_05_0
+#define GPIO_N_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
+#define GPIO_N_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INTERRUPT_CLEAR_05_0
+#define GPIO_N_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x122b4)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_SECURE                      0x0
+#define GPIO_N_INTERRUPT_CLEAR_05_0_DUAL                        0x0
+#define GPIO_N_INTERRUPT_CLEAR_05_0_SCR                         GPIO_N_SCR_05_0
+#define GPIO_N_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_N_SCR_05_0
+#define GPIO_N_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
+#define GPIO_N_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x122b8
+
+// Reserved address 0x122bc
+
+// Register GPIO_N_ENABLE_CONFIG_06_0
+#define GPIO_N_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x122c0)
+#define GPIO_N_ENABLE_CONFIG_06_0_SECURE                        0x0
+#define GPIO_N_ENABLE_CONFIG_06_0_DUAL                  0x0
+#define GPIO_N_ENABLE_CONFIG_06_0_SCR                   GPIO_N_SCR_06_0
+#define GPIO_N_ENABLE_CONFIG_06_0_SCRREG                        GPIO_N_SCR_06_0
+#define GPIO_N_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
+#define GPIO_N_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
+#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_N_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x122c4)
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_N_SCR_06_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_N_SCR_06_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_N_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INPUT_06_0
+#define GPIO_N_INPUT_06_0                       MK_ADDR_CONST(0x122c8)
+#define GPIO_N_INPUT_06_0_SECURE                        0x0
+#define GPIO_N_INPUT_06_0_DUAL                  0x0
+#define GPIO_N_INPUT_06_0_SCR                   GPIO_N_SCR_06_0
+#define GPIO_N_INPUT_06_0_SCRREG                        GPIO_N_SCR_06_0
+#define GPIO_N_INPUT_06_0_WORD_COUNT                    0x1
+#define GPIO_N_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_N_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_N_INPUT_06_0_GPIO_IN_RANGE                 0:0
+#define GPIO_N_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_N_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_OUTPUT_CONTROL_06_0
+#define GPIO_N_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x122cc)
+#define GPIO_N_OUTPUT_CONTROL_06_0_SECURE                       0x0
+#define GPIO_N_OUTPUT_CONTROL_06_0_DUAL                         0x0
+#define GPIO_N_OUTPUT_CONTROL_06_0_SCR                  GPIO_N_SCR_06_0
+#define GPIO_N_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_N_SCR_06_0
+#define GPIO_N_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
+#define GPIO_N_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_N_OUTPUT_VALUE_06_0
+#define GPIO_N_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x122d0)
+#define GPIO_N_OUTPUT_VALUE_06_0_SECURE                         0x0
+#define GPIO_N_OUTPUT_VALUE_06_0_DUAL                   0x0
+#define GPIO_N_OUTPUT_VALUE_06_0_SCR                    GPIO_N_SCR_06_0
+#define GPIO_N_OUTPUT_VALUE_06_0_SCRREG                         GPIO_N_SCR_06_0
+#define GPIO_N_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
+#define GPIO_N_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INTERRUPT_CLEAR_06_0
+#define GPIO_N_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x122d4)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_SECURE                      0x0
+#define GPIO_N_INTERRUPT_CLEAR_06_0_DUAL                        0x0
+#define GPIO_N_INTERRUPT_CLEAR_06_0_SCR                         GPIO_N_SCR_06_0
+#define GPIO_N_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_N_SCR_06_0
+#define GPIO_N_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
+#define GPIO_N_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x122d8
+
+// Reserved address 0x122dc
+
+// Register GPIO_N_ENABLE_CONFIG_07_0
+#define GPIO_N_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x122e0)
+#define GPIO_N_ENABLE_CONFIG_07_0_SECURE                        0x0
+#define GPIO_N_ENABLE_CONFIG_07_0_DUAL                  0x0
+#define GPIO_N_ENABLE_CONFIG_07_0_SCR                   GPIO_N_SCR_07_0
+#define GPIO_N_ENABLE_CONFIG_07_0_SCRREG                        GPIO_N_SCR_07_0
+#define GPIO_N_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
+#define GPIO_N_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
+#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_N_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_N_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x122e4)
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_N_SCR_07_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_N_SCR_07_0
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_N_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INPUT_07_0
+#define GPIO_N_INPUT_07_0                       MK_ADDR_CONST(0x122e8)
+#define GPIO_N_INPUT_07_0_SECURE                        0x0
+#define GPIO_N_INPUT_07_0_DUAL                  0x0
+#define GPIO_N_INPUT_07_0_SCR                   GPIO_N_SCR_07_0
+#define GPIO_N_INPUT_07_0_SCRREG                        GPIO_N_SCR_07_0
+#define GPIO_N_INPUT_07_0_WORD_COUNT                    0x1
+#define GPIO_N_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_N_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_N_INPUT_07_0_GPIO_IN_RANGE                 0:0
+#define GPIO_N_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_N_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_N_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_N_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_OUTPUT_CONTROL_07_0
+#define GPIO_N_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x122ec)
+#define GPIO_N_OUTPUT_CONTROL_07_0_SECURE                       0x0
+#define GPIO_N_OUTPUT_CONTROL_07_0_DUAL                         0x0
+#define GPIO_N_OUTPUT_CONTROL_07_0_SCR                  GPIO_N_SCR_07_0
+#define GPIO_N_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_N_SCR_07_0
+#define GPIO_N_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
+#define GPIO_N_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_N_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_N_OUTPUT_VALUE_07_0
+#define GPIO_N_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x122f0)
+#define GPIO_N_OUTPUT_VALUE_07_0_SECURE                         0x0
+#define GPIO_N_OUTPUT_VALUE_07_0_DUAL                   0x0
+#define GPIO_N_OUTPUT_VALUE_07_0_SCR                    GPIO_N_SCR_07_0
+#define GPIO_N_OUTPUT_VALUE_07_0_SCRREG                         GPIO_N_SCR_07_0
+#define GPIO_N_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
+#define GPIO_N_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_N_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INTERRUPT_CLEAR_07_0
+#define GPIO_N_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x122f4)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_SECURE                      0x0
+#define GPIO_N_INTERRUPT_CLEAR_07_0_DUAL                        0x0
+#define GPIO_N_INTERRUPT_CLEAR_07_0_SCR                         GPIO_N_SCR_07_0
+#define GPIO_N_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_N_SCR_07_0
+#define GPIO_N_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
+#define GPIO_N_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_N_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x122f8
+
+// Reserved address 0x122fc
+
+// Register GPIO_N_INTERRUPT_STATUS_G0_0
+#define GPIO_N_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x12300)
+#define GPIO_N_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_N_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_N_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_N_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_N_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_N_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INTERRUPT_STATUS_G1_0
+#define GPIO_N_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x12304)
+#define GPIO_N_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_N_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_N_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_N_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_N_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_N_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INTERRUPT_STATUS_G2_0
+#define GPIO_N_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x12308)
+#define GPIO_N_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_N_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_N_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_N_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_N_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_N_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INTERRUPT_STATUS_G3_0
+#define GPIO_N_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1230c)
+#define GPIO_N_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_N_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_N_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_N_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_N_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_N_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INTERRUPT_STATUS_G4_0
+#define GPIO_N_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x12310)
+#define GPIO_N_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_N_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_N_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_N_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_N_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_N_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INTERRUPT_STATUS_G5_0
+#define GPIO_N_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x12314)
+#define GPIO_N_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_N_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_N_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_N_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_N_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_N_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INTERRUPT_STATUS_G6_0
+#define GPIO_N_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x12318)
+#define GPIO_N_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_N_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_N_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_N_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_N_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_N_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_N_INTERRUPT_STATUS_G7_0
+#define GPIO_N_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1231c)
+#define GPIO_N_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_N_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_N_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_N_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_N_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_N_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_N_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x12320
+
+// Reserved address 0x12324
+
+// Reserved address 0x12328
+
+// Reserved address 0x1232c
+
+// Reserved address 0x12330
+
+// Reserved address 0x12334
+
+// Reserved address 0x12338
+
+// Reserved address 0x1233c
+
+// Reserved address 0x12340
+
+// Reserved address 0x12344
+
+// Reserved address 0x12348
+
+// Reserved address 0x1234c
+
+// Reserved address 0x12350
+
+// Reserved address 0x12354
+
+// Reserved address 0x12358
+
+// Reserved address 0x1235c
+
+// Reserved address 0x12360
+
+// Reserved address 0x12364
+
+// Reserved address 0x12368
+
+// Reserved address 0x1236c
+
+// Reserved address 0x12370
+
+// Reserved address 0x12374
+
+// Reserved address 0x12378
+
+// Reserved address 0x1237c
+
+// Reserved address 0x12380
+
+// Reserved address 0x12384
+
+// Reserved address 0x12388
+
+// Reserved address 0x1238c
+
+// Reserved address 0x12390
+
+// Reserved address 0x12394
+
+// Reserved address 0x12398
+
+// Reserved address 0x1239c
+
+// Reserved address 0x123a0
+
+// Reserved address 0x123a4
+
+// Reserved address 0x123a8
+
+// Reserved address 0x123ac
+
+// Reserved address 0x123b0
+
+// Reserved address 0x123b4
+
+// Reserved address 0x123b8
+
+// Reserved address 0x123bc
+
+// Reserved address 0x123c0
+
+// Reserved address 0x123c4
+
+// Reserved address 0x123c8
+
+// Reserved address 0x123cc
+
+// Reserved address 0x123d0
+
+// Reserved address 0x123d4
+
+// Reserved address 0x123d8
+
+// Reserved address 0x123dc
+
+// Reserved address 0x123e0
+
+// Reserved address 0x123e4
+
+// Reserved address 0x123e8
+
+// Reserved address 0x123ec
+
+// Reserved address 0x123f0
+
+// Reserved address 0x123f4
+
+// Reserved address 0x123f8
+
+// Reserved address 0x123fc
+
+// Register GPIO_P_ENABLE_CONFIG_00_0
+#define GPIO_P_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x12400)
+#define GPIO_P_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_P_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_P_ENABLE_CONFIG_00_0_SCR                   GPIO_P_SCR_00_0
+#define GPIO_P_ENABLE_CONFIG_00_0_SCRREG                        GPIO_P_SCR_00_0
+#define GPIO_P_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_P_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_P_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x12404)
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_P_SCR_00_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_P_SCR_00_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_P_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INPUT_00_0
+#define GPIO_P_INPUT_00_0                       MK_ADDR_CONST(0x12408)
+#define GPIO_P_INPUT_00_0_SECURE                        0x0
+#define GPIO_P_INPUT_00_0_DUAL                  0x0
+#define GPIO_P_INPUT_00_0_SCR                   GPIO_P_SCR_00_0
+#define GPIO_P_INPUT_00_0_SCRREG                        GPIO_P_SCR_00_0
+#define GPIO_P_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_P_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_P_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_P_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_P_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_P_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_OUTPUT_CONTROL_00_0
+#define GPIO_P_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1240c)
+#define GPIO_P_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_P_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_P_OUTPUT_CONTROL_00_0_SCR                  GPIO_P_SCR_00_0
+#define GPIO_P_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_P_SCR_00_0
+#define GPIO_P_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_P_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_P_OUTPUT_VALUE_00_0
+#define GPIO_P_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x12410)
+#define GPIO_P_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_P_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_P_OUTPUT_VALUE_00_0_SCR                    GPIO_P_SCR_00_0
+#define GPIO_P_OUTPUT_VALUE_00_0_SCRREG                         GPIO_P_SCR_00_0
+#define GPIO_P_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_P_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INTERRUPT_CLEAR_00_0
+#define GPIO_P_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x12414)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_P_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_P_INTERRUPT_CLEAR_00_0_SCR                         GPIO_P_SCR_00_0
+#define GPIO_P_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_P_SCR_00_0
+#define GPIO_P_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_P_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12418
+
+// Reserved address 0x1241c
+
+// Register GPIO_P_ENABLE_CONFIG_01_0
+#define GPIO_P_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x12420)
+#define GPIO_P_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_P_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_P_ENABLE_CONFIG_01_0_SCR                   GPIO_P_SCR_01_0
+#define GPIO_P_ENABLE_CONFIG_01_0_SCRREG                        GPIO_P_SCR_01_0
+#define GPIO_P_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_P_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_P_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x12424)
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_P_SCR_01_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_P_SCR_01_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_P_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INPUT_01_0
+#define GPIO_P_INPUT_01_0                       MK_ADDR_CONST(0x12428)
+#define GPIO_P_INPUT_01_0_SECURE                        0x0
+#define GPIO_P_INPUT_01_0_DUAL                  0x0
+#define GPIO_P_INPUT_01_0_SCR                   GPIO_P_SCR_01_0
+#define GPIO_P_INPUT_01_0_SCRREG                        GPIO_P_SCR_01_0
+#define GPIO_P_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_P_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_P_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_P_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_P_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_P_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_OUTPUT_CONTROL_01_0
+#define GPIO_P_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1242c)
+#define GPIO_P_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_P_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_P_OUTPUT_CONTROL_01_0_SCR                  GPIO_P_SCR_01_0
+#define GPIO_P_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_P_SCR_01_0
+#define GPIO_P_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_P_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_P_OUTPUT_VALUE_01_0
+#define GPIO_P_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x12430)
+#define GPIO_P_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_P_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_P_OUTPUT_VALUE_01_0_SCR                    GPIO_P_SCR_01_0
+#define GPIO_P_OUTPUT_VALUE_01_0_SCRREG                         GPIO_P_SCR_01_0
+#define GPIO_P_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_P_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INTERRUPT_CLEAR_01_0
+#define GPIO_P_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x12434)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_P_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_P_INTERRUPT_CLEAR_01_0_SCR                         GPIO_P_SCR_01_0
+#define GPIO_P_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_P_SCR_01_0
+#define GPIO_P_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_P_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12438
+
+// Reserved address 0x1243c
+
+// Register GPIO_P_ENABLE_CONFIG_02_0
+#define GPIO_P_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x12440)
+#define GPIO_P_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_P_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_P_ENABLE_CONFIG_02_0_SCR                   GPIO_P_SCR_02_0
+#define GPIO_P_ENABLE_CONFIG_02_0_SCRREG                        GPIO_P_SCR_02_0
+#define GPIO_P_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_P_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_P_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x12444)
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_P_SCR_02_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_P_SCR_02_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_P_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INPUT_02_0
+#define GPIO_P_INPUT_02_0                       MK_ADDR_CONST(0x12448)
+#define GPIO_P_INPUT_02_0_SECURE                        0x0
+#define GPIO_P_INPUT_02_0_DUAL                  0x0
+#define GPIO_P_INPUT_02_0_SCR                   GPIO_P_SCR_02_0
+#define GPIO_P_INPUT_02_0_SCRREG                        GPIO_P_SCR_02_0
+#define GPIO_P_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_P_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_P_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_P_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_P_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_P_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_OUTPUT_CONTROL_02_0
+#define GPIO_P_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1244c)
+#define GPIO_P_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_P_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_P_OUTPUT_CONTROL_02_0_SCR                  GPIO_P_SCR_02_0
+#define GPIO_P_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_P_SCR_02_0
+#define GPIO_P_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_P_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_P_OUTPUT_VALUE_02_0
+#define GPIO_P_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x12450)
+#define GPIO_P_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_P_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_P_OUTPUT_VALUE_02_0_SCR                    GPIO_P_SCR_02_0
+#define GPIO_P_OUTPUT_VALUE_02_0_SCRREG                         GPIO_P_SCR_02_0
+#define GPIO_P_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_P_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INTERRUPT_CLEAR_02_0
+#define GPIO_P_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x12454)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_P_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_P_INTERRUPT_CLEAR_02_0_SCR                         GPIO_P_SCR_02_0
+#define GPIO_P_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_P_SCR_02_0
+#define GPIO_P_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_P_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12458
+
+// Reserved address 0x1245c
+
+// Register GPIO_P_ENABLE_CONFIG_03_0
+#define GPIO_P_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x12460)
+#define GPIO_P_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_P_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_P_ENABLE_CONFIG_03_0_SCR                   GPIO_P_SCR_03_0
+#define GPIO_P_ENABLE_CONFIG_03_0_SCRREG                        GPIO_P_SCR_03_0
+#define GPIO_P_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_P_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_P_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x12464)
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_P_SCR_03_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_P_SCR_03_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_P_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INPUT_03_0
+#define GPIO_P_INPUT_03_0                       MK_ADDR_CONST(0x12468)
+#define GPIO_P_INPUT_03_0_SECURE                        0x0
+#define GPIO_P_INPUT_03_0_DUAL                  0x0
+#define GPIO_P_INPUT_03_0_SCR                   GPIO_P_SCR_03_0
+#define GPIO_P_INPUT_03_0_SCRREG                        GPIO_P_SCR_03_0
+#define GPIO_P_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_P_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_P_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_P_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_P_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_P_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_OUTPUT_CONTROL_03_0
+#define GPIO_P_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1246c)
+#define GPIO_P_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_P_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_P_OUTPUT_CONTROL_03_0_SCR                  GPIO_P_SCR_03_0
+#define GPIO_P_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_P_SCR_03_0
+#define GPIO_P_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_P_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_P_OUTPUT_VALUE_03_0
+#define GPIO_P_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x12470)
+#define GPIO_P_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_P_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_P_OUTPUT_VALUE_03_0_SCR                    GPIO_P_SCR_03_0
+#define GPIO_P_OUTPUT_VALUE_03_0_SCRREG                         GPIO_P_SCR_03_0
+#define GPIO_P_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_P_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INTERRUPT_CLEAR_03_0
+#define GPIO_P_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x12474)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_P_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_P_INTERRUPT_CLEAR_03_0_SCR                         GPIO_P_SCR_03_0
+#define GPIO_P_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_P_SCR_03_0
+#define GPIO_P_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_P_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12478
+
+// Reserved address 0x1247c
+
+// Register GPIO_P_ENABLE_CONFIG_04_0
+#define GPIO_P_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x12480)
+#define GPIO_P_ENABLE_CONFIG_04_0_SECURE                        0x0
+#define GPIO_P_ENABLE_CONFIG_04_0_DUAL                  0x0
+#define GPIO_P_ENABLE_CONFIG_04_0_SCR                   GPIO_P_SCR_04_0
+#define GPIO_P_ENABLE_CONFIG_04_0_SCRREG                        GPIO_P_SCR_04_0
+#define GPIO_P_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
+#define GPIO_P_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
+#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_P_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x12484)
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_P_SCR_04_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_P_SCR_04_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_P_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INPUT_04_0
+#define GPIO_P_INPUT_04_0                       MK_ADDR_CONST(0x12488)
+#define GPIO_P_INPUT_04_0_SECURE                        0x0
+#define GPIO_P_INPUT_04_0_DUAL                  0x0
+#define GPIO_P_INPUT_04_0_SCR                   GPIO_P_SCR_04_0
+#define GPIO_P_INPUT_04_0_SCRREG                        GPIO_P_SCR_04_0
+#define GPIO_P_INPUT_04_0_WORD_COUNT                    0x1
+#define GPIO_P_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_P_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_P_INPUT_04_0_GPIO_IN_RANGE                 0:0
+#define GPIO_P_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_P_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_OUTPUT_CONTROL_04_0
+#define GPIO_P_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1248c)
+#define GPIO_P_OUTPUT_CONTROL_04_0_SECURE                       0x0
+#define GPIO_P_OUTPUT_CONTROL_04_0_DUAL                         0x0
+#define GPIO_P_OUTPUT_CONTROL_04_0_SCR                  GPIO_P_SCR_04_0
+#define GPIO_P_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_P_SCR_04_0
+#define GPIO_P_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
+#define GPIO_P_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_P_OUTPUT_VALUE_04_0
+#define GPIO_P_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x12490)
+#define GPIO_P_OUTPUT_VALUE_04_0_SECURE                         0x0
+#define GPIO_P_OUTPUT_VALUE_04_0_DUAL                   0x0
+#define GPIO_P_OUTPUT_VALUE_04_0_SCR                    GPIO_P_SCR_04_0
+#define GPIO_P_OUTPUT_VALUE_04_0_SCRREG                         GPIO_P_SCR_04_0
+#define GPIO_P_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
+#define GPIO_P_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INTERRUPT_CLEAR_04_0
+#define GPIO_P_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x12494)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_SECURE                      0x0
+#define GPIO_P_INTERRUPT_CLEAR_04_0_DUAL                        0x0
+#define GPIO_P_INTERRUPT_CLEAR_04_0_SCR                         GPIO_P_SCR_04_0
+#define GPIO_P_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_P_SCR_04_0
+#define GPIO_P_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
+#define GPIO_P_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12498
+
+// Reserved address 0x1249c
+
+// Register GPIO_P_ENABLE_CONFIG_05_0
+#define GPIO_P_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x124a0)
+#define GPIO_P_ENABLE_CONFIG_05_0_SECURE                        0x0
+#define GPIO_P_ENABLE_CONFIG_05_0_DUAL                  0x0
+#define GPIO_P_ENABLE_CONFIG_05_0_SCR                   GPIO_P_SCR_05_0
+#define GPIO_P_ENABLE_CONFIG_05_0_SCRREG                        GPIO_P_SCR_05_0
+#define GPIO_P_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
+#define GPIO_P_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
+#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_P_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x124a4)
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_P_SCR_05_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_P_SCR_05_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_P_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INPUT_05_0
+#define GPIO_P_INPUT_05_0                       MK_ADDR_CONST(0x124a8)
+#define GPIO_P_INPUT_05_0_SECURE                        0x0
+#define GPIO_P_INPUT_05_0_DUAL                  0x0
+#define GPIO_P_INPUT_05_0_SCR                   GPIO_P_SCR_05_0
+#define GPIO_P_INPUT_05_0_SCRREG                        GPIO_P_SCR_05_0
+#define GPIO_P_INPUT_05_0_WORD_COUNT                    0x1
+#define GPIO_P_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_P_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_P_INPUT_05_0_GPIO_IN_RANGE                 0:0
+#define GPIO_P_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_P_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_OUTPUT_CONTROL_05_0
+#define GPIO_P_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x124ac)
+#define GPIO_P_OUTPUT_CONTROL_05_0_SECURE                       0x0
+#define GPIO_P_OUTPUT_CONTROL_05_0_DUAL                         0x0
+#define GPIO_P_OUTPUT_CONTROL_05_0_SCR                  GPIO_P_SCR_05_0
+#define GPIO_P_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_P_SCR_05_0
+#define GPIO_P_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
+#define GPIO_P_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_P_OUTPUT_VALUE_05_0
+#define GPIO_P_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x124b0)
+#define GPIO_P_OUTPUT_VALUE_05_0_SECURE                         0x0
+#define GPIO_P_OUTPUT_VALUE_05_0_DUAL                   0x0
+#define GPIO_P_OUTPUT_VALUE_05_0_SCR                    GPIO_P_SCR_05_0
+#define GPIO_P_OUTPUT_VALUE_05_0_SCRREG                         GPIO_P_SCR_05_0
+#define GPIO_P_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
+#define GPIO_P_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INTERRUPT_CLEAR_05_0
+#define GPIO_P_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x124b4)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_SECURE                      0x0
+#define GPIO_P_INTERRUPT_CLEAR_05_0_DUAL                        0x0
+#define GPIO_P_INTERRUPT_CLEAR_05_0_SCR                         GPIO_P_SCR_05_0
+#define GPIO_P_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_P_SCR_05_0
+#define GPIO_P_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
+#define GPIO_P_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x124b8
+
+// Reserved address 0x124bc
+
+// Register GPIO_P_ENABLE_CONFIG_06_0
+#define GPIO_P_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x124c0)
+#define GPIO_P_ENABLE_CONFIG_06_0_SECURE                        0x0
+#define GPIO_P_ENABLE_CONFIG_06_0_DUAL                  0x0
+#define GPIO_P_ENABLE_CONFIG_06_0_SCR                   GPIO_P_SCR_06_0
+#define GPIO_P_ENABLE_CONFIG_06_0_SCRREG                        GPIO_P_SCR_06_0
+#define GPIO_P_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
+#define GPIO_P_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
+#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_P_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x124c4)
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_P_SCR_06_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_P_SCR_06_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_P_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INPUT_06_0
+#define GPIO_P_INPUT_06_0                       MK_ADDR_CONST(0x124c8)
+#define GPIO_P_INPUT_06_0_SECURE                        0x0
+#define GPIO_P_INPUT_06_0_DUAL                  0x0
+#define GPIO_P_INPUT_06_0_SCR                   GPIO_P_SCR_06_0
+#define GPIO_P_INPUT_06_0_SCRREG                        GPIO_P_SCR_06_0
+#define GPIO_P_INPUT_06_0_WORD_COUNT                    0x1
+#define GPIO_P_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_P_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_P_INPUT_06_0_GPIO_IN_RANGE                 0:0
+#define GPIO_P_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_P_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_OUTPUT_CONTROL_06_0
+#define GPIO_P_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x124cc)
+#define GPIO_P_OUTPUT_CONTROL_06_0_SECURE                       0x0
+#define GPIO_P_OUTPUT_CONTROL_06_0_DUAL                         0x0
+#define GPIO_P_OUTPUT_CONTROL_06_0_SCR                  GPIO_P_SCR_06_0
+#define GPIO_P_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_P_SCR_06_0
+#define GPIO_P_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
+#define GPIO_P_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_P_OUTPUT_VALUE_06_0
+#define GPIO_P_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x124d0)
+#define GPIO_P_OUTPUT_VALUE_06_0_SECURE                         0x0
+#define GPIO_P_OUTPUT_VALUE_06_0_DUAL                   0x0
+#define GPIO_P_OUTPUT_VALUE_06_0_SCR                    GPIO_P_SCR_06_0
+#define GPIO_P_OUTPUT_VALUE_06_0_SCRREG                         GPIO_P_SCR_06_0
+#define GPIO_P_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
+#define GPIO_P_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INTERRUPT_CLEAR_06_0
+#define GPIO_P_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x124d4)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_SECURE                      0x0
+#define GPIO_P_INTERRUPT_CLEAR_06_0_DUAL                        0x0
+#define GPIO_P_INTERRUPT_CLEAR_06_0_SCR                         GPIO_P_SCR_06_0
+#define GPIO_P_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_P_SCR_06_0
+#define GPIO_P_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
+#define GPIO_P_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x124d8
+
+// Reserved address 0x124dc
+
+// Register GPIO_P_ENABLE_CONFIG_07_0
+#define GPIO_P_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x124e0)
+#define GPIO_P_ENABLE_CONFIG_07_0_SECURE                        0x0
+#define GPIO_P_ENABLE_CONFIG_07_0_DUAL                  0x0
+#define GPIO_P_ENABLE_CONFIG_07_0_SCR                   GPIO_P_SCR_07_0
+#define GPIO_P_ENABLE_CONFIG_07_0_SCRREG                        GPIO_P_SCR_07_0
+#define GPIO_P_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
+#define GPIO_P_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
+#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_P_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_P_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x124e4)
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_P_SCR_07_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_P_SCR_07_0
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_P_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INPUT_07_0
+#define GPIO_P_INPUT_07_0                       MK_ADDR_CONST(0x124e8)
+#define GPIO_P_INPUT_07_0_SECURE                        0x0
+#define GPIO_P_INPUT_07_0_DUAL                  0x0
+#define GPIO_P_INPUT_07_0_SCR                   GPIO_P_SCR_07_0
+#define GPIO_P_INPUT_07_0_SCRREG                        GPIO_P_SCR_07_0
+#define GPIO_P_INPUT_07_0_WORD_COUNT                    0x1
+#define GPIO_P_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_P_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_P_INPUT_07_0_GPIO_IN_RANGE                 0:0
+#define GPIO_P_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_P_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_P_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_P_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_OUTPUT_CONTROL_07_0
+#define GPIO_P_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x124ec)
+#define GPIO_P_OUTPUT_CONTROL_07_0_SECURE                       0x0
+#define GPIO_P_OUTPUT_CONTROL_07_0_DUAL                         0x0
+#define GPIO_P_OUTPUT_CONTROL_07_0_SCR                  GPIO_P_SCR_07_0
+#define GPIO_P_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_P_SCR_07_0
+#define GPIO_P_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
+#define GPIO_P_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_P_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_P_OUTPUT_VALUE_07_0
+#define GPIO_P_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x124f0)
+#define GPIO_P_OUTPUT_VALUE_07_0_SECURE                         0x0
+#define GPIO_P_OUTPUT_VALUE_07_0_DUAL                   0x0
+#define GPIO_P_OUTPUT_VALUE_07_0_SCR                    GPIO_P_SCR_07_0
+#define GPIO_P_OUTPUT_VALUE_07_0_SCRREG                         GPIO_P_SCR_07_0
+#define GPIO_P_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
+#define GPIO_P_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_P_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INTERRUPT_CLEAR_07_0
+#define GPIO_P_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x124f4)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_SECURE                      0x0
+#define GPIO_P_INTERRUPT_CLEAR_07_0_DUAL                        0x0
+#define GPIO_P_INTERRUPT_CLEAR_07_0_SCR                         GPIO_P_SCR_07_0
+#define GPIO_P_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_P_SCR_07_0
+#define GPIO_P_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
+#define GPIO_P_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_P_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x124f8
+
+// Reserved address 0x124fc
+
+// Register GPIO_P_INTERRUPT_STATUS_G0_0
+#define GPIO_P_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x12500)
+#define GPIO_P_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_P_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_P_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_P_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_P_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_P_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INTERRUPT_STATUS_G1_0
+#define GPIO_P_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x12504)
+#define GPIO_P_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_P_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_P_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_P_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_P_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_P_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INTERRUPT_STATUS_G2_0
+#define GPIO_P_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x12508)
+#define GPIO_P_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_P_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_P_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_P_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_P_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_P_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INTERRUPT_STATUS_G3_0
+#define GPIO_P_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1250c)
+#define GPIO_P_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_P_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_P_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_P_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_P_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_P_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INTERRUPT_STATUS_G4_0
+#define GPIO_P_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x12510)
+#define GPIO_P_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_P_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_P_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_P_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_P_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_P_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INTERRUPT_STATUS_G5_0
+#define GPIO_P_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x12514)
+#define GPIO_P_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_P_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_P_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_P_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_P_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_P_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INTERRUPT_STATUS_G6_0
+#define GPIO_P_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x12518)
+#define GPIO_P_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_P_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_P_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_P_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_P_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_P_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_P_INTERRUPT_STATUS_G7_0
+#define GPIO_P_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1251c)
+#define GPIO_P_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_P_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_P_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_P_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_P_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_P_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_P_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x12520
+
+// Reserved address 0x12524
+
+// Reserved address 0x12528
+
+// Reserved address 0x1252c
+
+// Reserved address 0x12530
+
+// Reserved address 0x12534
+
+// Reserved address 0x12538
+
+// Reserved address 0x1253c
+
+// Reserved address 0x12540
+
+// Reserved address 0x12544
+
+// Reserved address 0x12548
+
+// Reserved address 0x1254c
+
+// Reserved address 0x12550
+
+// Reserved address 0x12554
+
+// Reserved address 0x12558
+
+// Reserved address 0x1255c
+
+// Reserved address 0x12560
+
+// Reserved address 0x12564
+
+// Reserved address 0x12568
+
+// Reserved address 0x1256c
+
+// Reserved address 0x12570
+
+// Reserved address 0x12574
+
+// Reserved address 0x12578
+
+// Reserved address 0x1257c
+
+// Reserved address 0x12580
+
+// Reserved address 0x12584
+
+// Reserved address 0x12588
+
+// Reserved address 0x1258c
+
+// Reserved address 0x12590
+
+// Reserved address 0x12594
+
+// Reserved address 0x12598
+
+// Reserved address 0x1259c
+
+// Reserved address 0x125a0
+
+// Reserved address 0x125a4
+
+// Reserved address 0x125a8
+
+// Reserved address 0x125ac
+
+// Reserved address 0x125b0
+
+// Reserved address 0x125b4
+
+// Reserved address 0x125b8
+
+// Reserved address 0x125bc
+
+// Reserved address 0x125c0
+
+// Reserved address 0x125c4
+
+// Reserved address 0x125c8
+
+// Reserved address 0x125cc
+
+// Reserved address 0x125d0
+
+// Reserved address 0x125d4
+
+// Reserved address 0x125d8
+
+// Reserved address 0x125dc
+
+// Reserved address 0x125e0
+
+// Reserved address 0x125e4
+
+// Reserved address 0x125e8
+
+// Reserved address 0x125ec
+
+// Reserved address 0x125f0
+
+// Reserved address 0x125f4
+
+// Reserved address 0x125f8
+
+// Reserved address 0x125fc
+
+// Register GPIO_Q_ENABLE_CONFIG_00_0
+#define GPIO_Q_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x12600)
+#define GPIO_Q_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_Q_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_Q_ENABLE_CONFIG_00_0_SCR                   GPIO_Q_SCR_00_0
+#define GPIO_Q_ENABLE_CONFIG_00_0_SCRREG                        GPIO_Q_SCR_00_0
+#define GPIO_Q_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_Q_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Q_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x12604)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_Q_SCR_00_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_Q_SCR_00_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INPUT_00_0
+#define GPIO_Q_INPUT_00_0                       MK_ADDR_CONST(0x12608)
+#define GPIO_Q_INPUT_00_0_SECURE                        0x0
+#define GPIO_Q_INPUT_00_0_DUAL                  0x0
+#define GPIO_Q_INPUT_00_0_SCR                   GPIO_Q_SCR_00_0
+#define GPIO_Q_INPUT_00_0_SCRREG                        GPIO_Q_SCR_00_0
+#define GPIO_Q_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_Q_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Q_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_Q_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Q_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Q_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_OUTPUT_CONTROL_00_0
+#define GPIO_Q_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1260c)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_Q_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_Q_OUTPUT_CONTROL_00_0_SCR                  GPIO_Q_SCR_00_0
+#define GPIO_Q_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_Q_SCR_00_0
+#define GPIO_Q_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_Q_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Q_OUTPUT_VALUE_00_0
+#define GPIO_Q_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x12610)
+#define GPIO_Q_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_Q_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_Q_OUTPUT_VALUE_00_0_SCR                    GPIO_Q_SCR_00_0
+#define GPIO_Q_OUTPUT_VALUE_00_0_SCRREG                         GPIO_Q_SCR_00_0
+#define GPIO_Q_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_Q_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INTERRUPT_CLEAR_00_0
+#define GPIO_Q_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x12614)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_SCR                         GPIO_Q_SCR_00_0
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_Q_SCR_00_0
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12618
+
+// Reserved address 0x1261c
+
+// Register GPIO_Q_ENABLE_CONFIG_01_0
+#define GPIO_Q_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x12620)
+#define GPIO_Q_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_Q_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_Q_ENABLE_CONFIG_01_0_SCR                   GPIO_Q_SCR_01_0
+#define GPIO_Q_ENABLE_CONFIG_01_0_SCRREG                        GPIO_Q_SCR_01_0
+#define GPIO_Q_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_Q_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Q_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x12624)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_Q_SCR_01_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_Q_SCR_01_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INPUT_01_0
+#define GPIO_Q_INPUT_01_0                       MK_ADDR_CONST(0x12628)
+#define GPIO_Q_INPUT_01_0_SECURE                        0x0
+#define GPIO_Q_INPUT_01_0_DUAL                  0x0
+#define GPIO_Q_INPUT_01_0_SCR                   GPIO_Q_SCR_01_0
+#define GPIO_Q_INPUT_01_0_SCRREG                        GPIO_Q_SCR_01_0
+#define GPIO_Q_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_Q_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Q_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_Q_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Q_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Q_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_OUTPUT_CONTROL_01_0
+#define GPIO_Q_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1262c)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_Q_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_Q_OUTPUT_CONTROL_01_0_SCR                  GPIO_Q_SCR_01_0
+#define GPIO_Q_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_Q_SCR_01_0
+#define GPIO_Q_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_Q_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Q_OUTPUT_VALUE_01_0
+#define GPIO_Q_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x12630)
+#define GPIO_Q_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_Q_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_Q_OUTPUT_VALUE_01_0_SCR                    GPIO_Q_SCR_01_0
+#define GPIO_Q_OUTPUT_VALUE_01_0_SCRREG                         GPIO_Q_SCR_01_0
+#define GPIO_Q_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_Q_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INTERRUPT_CLEAR_01_0
+#define GPIO_Q_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x12634)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_SCR                         GPIO_Q_SCR_01_0
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_Q_SCR_01_0
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12638
+
+// Reserved address 0x1263c
+
+// Register GPIO_Q_ENABLE_CONFIG_02_0
+#define GPIO_Q_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x12640)
+#define GPIO_Q_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_Q_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_Q_ENABLE_CONFIG_02_0_SCR                   GPIO_Q_SCR_02_0
+#define GPIO_Q_ENABLE_CONFIG_02_0_SCRREG                        GPIO_Q_SCR_02_0
+#define GPIO_Q_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_Q_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Q_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x12644)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_Q_SCR_02_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_Q_SCR_02_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INPUT_02_0
+#define GPIO_Q_INPUT_02_0                       MK_ADDR_CONST(0x12648)
+#define GPIO_Q_INPUT_02_0_SECURE                        0x0
+#define GPIO_Q_INPUT_02_0_DUAL                  0x0
+#define GPIO_Q_INPUT_02_0_SCR                   GPIO_Q_SCR_02_0
+#define GPIO_Q_INPUT_02_0_SCRREG                        GPIO_Q_SCR_02_0
+#define GPIO_Q_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_Q_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Q_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_Q_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Q_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Q_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_OUTPUT_CONTROL_02_0
+#define GPIO_Q_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1264c)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_Q_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_Q_OUTPUT_CONTROL_02_0_SCR                  GPIO_Q_SCR_02_0
+#define GPIO_Q_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_Q_SCR_02_0
+#define GPIO_Q_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_Q_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Q_OUTPUT_VALUE_02_0
+#define GPIO_Q_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x12650)
+#define GPIO_Q_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_Q_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_Q_OUTPUT_VALUE_02_0_SCR                    GPIO_Q_SCR_02_0
+#define GPIO_Q_OUTPUT_VALUE_02_0_SCRREG                         GPIO_Q_SCR_02_0
+#define GPIO_Q_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_Q_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INTERRUPT_CLEAR_02_0
+#define GPIO_Q_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x12654)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_SCR                         GPIO_Q_SCR_02_0
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_Q_SCR_02_0
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12658
+
+// Reserved address 0x1265c
+
+// Register GPIO_Q_ENABLE_CONFIG_03_0
+#define GPIO_Q_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x12660)
+#define GPIO_Q_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_Q_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_Q_ENABLE_CONFIG_03_0_SCR                   GPIO_Q_SCR_03_0
+#define GPIO_Q_ENABLE_CONFIG_03_0_SCRREG                        GPIO_Q_SCR_03_0
+#define GPIO_Q_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_Q_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Q_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x12664)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_Q_SCR_03_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_Q_SCR_03_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INPUT_03_0
+#define GPIO_Q_INPUT_03_0                       MK_ADDR_CONST(0x12668)
+#define GPIO_Q_INPUT_03_0_SECURE                        0x0
+#define GPIO_Q_INPUT_03_0_DUAL                  0x0
+#define GPIO_Q_INPUT_03_0_SCR                   GPIO_Q_SCR_03_0
+#define GPIO_Q_INPUT_03_0_SCRREG                        GPIO_Q_SCR_03_0
+#define GPIO_Q_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_Q_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Q_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_Q_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Q_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Q_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_OUTPUT_CONTROL_03_0
+#define GPIO_Q_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1266c)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_Q_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_Q_OUTPUT_CONTROL_03_0_SCR                  GPIO_Q_SCR_03_0
+#define GPIO_Q_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_Q_SCR_03_0
+#define GPIO_Q_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_Q_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Q_OUTPUT_VALUE_03_0
+#define GPIO_Q_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x12670)
+#define GPIO_Q_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_Q_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_Q_OUTPUT_VALUE_03_0_SCR                    GPIO_Q_SCR_03_0
+#define GPIO_Q_OUTPUT_VALUE_03_0_SCRREG                         GPIO_Q_SCR_03_0
+#define GPIO_Q_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_Q_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INTERRUPT_CLEAR_03_0
+#define GPIO_Q_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x12674)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_SCR                         GPIO_Q_SCR_03_0
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_Q_SCR_03_0
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12678
+
+// Reserved address 0x1267c
+
+// Register GPIO_Q_ENABLE_CONFIG_04_0
+#define GPIO_Q_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x12680)
+#define GPIO_Q_ENABLE_CONFIG_04_0_SECURE                        0x0
+#define GPIO_Q_ENABLE_CONFIG_04_0_DUAL                  0x0
+#define GPIO_Q_ENABLE_CONFIG_04_0_SCR                   GPIO_Q_SCR_04_0
+#define GPIO_Q_ENABLE_CONFIG_04_0_SCRREG                        GPIO_Q_SCR_04_0
+#define GPIO_Q_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
+#define GPIO_Q_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
+#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Q_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x12684)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_Q_SCR_04_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_Q_SCR_04_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INPUT_04_0
+#define GPIO_Q_INPUT_04_0                       MK_ADDR_CONST(0x12688)
+#define GPIO_Q_INPUT_04_0_SECURE                        0x0
+#define GPIO_Q_INPUT_04_0_DUAL                  0x0
+#define GPIO_Q_INPUT_04_0_SCR                   GPIO_Q_SCR_04_0
+#define GPIO_Q_INPUT_04_0_SCRREG                        GPIO_Q_SCR_04_0
+#define GPIO_Q_INPUT_04_0_WORD_COUNT                    0x1
+#define GPIO_Q_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Q_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_Q_INPUT_04_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Q_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Q_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_OUTPUT_CONTROL_04_0
+#define GPIO_Q_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1268c)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_SECURE                       0x0
+#define GPIO_Q_OUTPUT_CONTROL_04_0_DUAL                         0x0
+#define GPIO_Q_OUTPUT_CONTROL_04_0_SCR                  GPIO_Q_SCR_04_0
+#define GPIO_Q_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_Q_SCR_04_0
+#define GPIO_Q_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
+#define GPIO_Q_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Q_OUTPUT_VALUE_04_0
+#define GPIO_Q_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x12690)
+#define GPIO_Q_OUTPUT_VALUE_04_0_SECURE                         0x0
+#define GPIO_Q_OUTPUT_VALUE_04_0_DUAL                   0x0
+#define GPIO_Q_OUTPUT_VALUE_04_0_SCR                    GPIO_Q_SCR_04_0
+#define GPIO_Q_OUTPUT_VALUE_04_0_SCRREG                         GPIO_Q_SCR_04_0
+#define GPIO_Q_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
+#define GPIO_Q_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INTERRUPT_CLEAR_04_0
+#define GPIO_Q_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x12694)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_SECURE                      0x0
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_DUAL                        0x0
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_SCR                         GPIO_Q_SCR_04_0
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_Q_SCR_04_0
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12698
+
+// Reserved address 0x1269c
+
+// Register GPIO_Q_ENABLE_CONFIG_05_0
+#define GPIO_Q_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x126a0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_SECURE                        0x0
+#define GPIO_Q_ENABLE_CONFIG_05_0_DUAL                  0x0
+#define GPIO_Q_ENABLE_CONFIG_05_0_SCR                   GPIO_Q_SCR_05_0
+#define GPIO_Q_ENABLE_CONFIG_05_0_SCRREG                        GPIO_Q_SCR_05_0
+#define GPIO_Q_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
+#define GPIO_Q_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
+#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Q_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x126a4)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_Q_SCR_05_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_Q_SCR_05_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INPUT_05_0
+#define GPIO_Q_INPUT_05_0                       MK_ADDR_CONST(0x126a8)
+#define GPIO_Q_INPUT_05_0_SECURE                        0x0
+#define GPIO_Q_INPUT_05_0_DUAL                  0x0
+#define GPIO_Q_INPUT_05_0_SCR                   GPIO_Q_SCR_05_0
+#define GPIO_Q_INPUT_05_0_SCRREG                        GPIO_Q_SCR_05_0
+#define GPIO_Q_INPUT_05_0_WORD_COUNT                    0x1
+#define GPIO_Q_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Q_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_Q_INPUT_05_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Q_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Q_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_OUTPUT_CONTROL_05_0
+#define GPIO_Q_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x126ac)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_SECURE                       0x0
+#define GPIO_Q_OUTPUT_CONTROL_05_0_DUAL                         0x0
+#define GPIO_Q_OUTPUT_CONTROL_05_0_SCR                  GPIO_Q_SCR_05_0
+#define GPIO_Q_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_Q_SCR_05_0
+#define GPIO_Q_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
+#define GPIO_Q_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Q_OUTPUT_VALUE_05_0
+#define GPIO_Q_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x126b0)
+#define GPIO_Q_OUTPUT_VALUE_05_0_SECURE                         0x0
+#define GPIO_Q_OUTPUT_VALUE_05_0_DUAL                   0x0
+#define GPIO_Q_OUTPUT_VALUE_05_0_SCR                    GPIO_Q_SCR_05_0
+#define GPIO_Q_OUTPUT_VALUE_05_0_SCRREG                         GPIO_Q_SCR_05_0
+#define GPIO_Q_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
+#define GPIO_Q_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INTERRUPT_CLEAR_05_0
+#define GPIO_Q_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x126b4)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_SECURE                      0x0
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_DUAL                        0x0
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_SCR                         GPIO_Q_SCR_05_0
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_Q_SCR_05_0
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x126b8
+
+// Reserved address 0x126bc
+
+// Register GPIO_Q_ENABLE_CONFIG_06_0
+#define GPIO_Q_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x126c0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_SECURE                        0x0
+#define GPIO_Q_ENABLE_CONFIG_06_0_DUAL                  0x0
+#define GPIO_Q_ENABLE_CONFIG_06_0_SCR                   GPIO_Q_SCR_06_0
+#define GPIO_Q_ENABLE_CONFIG_06_0_SCRREG                        GPIO_Q_SCR_06_0
+#define GPIO_Q_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
+#define GPIO_Q_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
+#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Q_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x126c4)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_Q_SCR_06_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_Q_SCR_06_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INPUT_06_0
+#define GPIO_Q_INPUT_06_0                       MK_ADDR_CONST(0x126c8)
+#define GPIO_Q_INPUT_06_0_SECURE                        0x0
+#define GPIO_Q_INPUT_06_0_DUAL                  0x0
+#define GPIO_Q_INPUT_06_0_SCR                   GPIO_Q_SCR_06_0
+#define GPIO_Q_INPUT_06_0_SCRREG                        GPIO_Q_SCR_06_0
+#define GPIO_Q_INPUT_06_0_WORD_COUNT                    0x1
+#define GPIO_Q_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Q_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_Q_INPUT_06_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Q_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Q_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_OUTPUT_CONTROL_06_0
+#define GPIO_Q_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x126cc)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_SECURE                       0x0
+#define GPIO_Q_OUTPUT_CONTROL_06_0_DUAL                         0x0
+#define GPIO_Q_OUTPUT_CONTROL_06_0_SCR                  GPIO_Q_SCR_06_0
+#define GPIO_Q_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_Q_SCR_06_0
+#define GPIO_Q_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
+#define GPIO_Q_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Q_OUTPUT_VALUE_06_0
+#define GPIO_Q_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x126d0)
+#define GPIO_Q_OUTPUT_VALUE_06_0_SECURE                         0x0
+#define GPIO_Q_OUTPUT_VALUE_06_0_DUAL                   0x0
+#define GPIO_Q_OUTPUT_VALUE_06_0_SCR                    GPIO_Q_SCR_06_0
+#define GPIO_Q_OUTPUT_VALUE_06_0_SCRREG                         GPIO_Q_SCR_06_0
+#define GPIO_Q_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
+#define GPIO_Q_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INTERRUPT_CLEAR_06_0
+#define GPIO_Q_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x126d4)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_SECURE                      0x0
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_DUAL                        0x0
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_SCR                         GPIO_Q_SCR_06_0
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_Q_SCR_06_0
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x126d8
+
+// Reserved address 0x126dc
+
+// Register GPIO_Q_ENABLE_CONFIG_07_0
+#define GPIO_Q_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x126e0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_SECURE                        0x0
+#define GPIO_Q_ENABLE_CONFIG_07_0_DUAL                  0x0
+#define GPIO_Q_ENABLE_CONFIG_07_0_SCR                   GPIO_Q_SCR_07_0
+#define GPIO_Q_ENABLE_CONFIG_07_0_SCRREG                        GPIO_Q_SCR_07_0
+#define GPIO_Q_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
+#define GPIO_Q_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
+#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_Q_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_Q_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x126e4)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_Q_SCR_07_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_Q_SCR_07_0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_Q_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INPUT_07_0
+#define GPIO_Q_INPUT_07_0                       MK_ADDR_CONST(0x126e8)
+#define GPIO_Q_INPUT_07_0_SECURE                        0x0
+#define GPIO_Q_INPUT_07_0_DUAL                  0x0
+#define GPIO_Q_INPUT_07_0_SCR                   GPIO_Q_SCR_07_0
+#define GPIO_Q_INPUT_07_0_SCRREG                        GPIO_Q_SCR_07_0
+#define GPIO_Q_INPUT_07_0_WORD_COUNT                    0x1
+#define GPIO_Q_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_Q_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_Q_INPUT_07_0_GPIO_IN_RANGE                 0:0
+#define GPIO_Q_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_Q_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_Q_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_OUTPUT_CONTROL_07_0
+#define GPIO_Q_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x126ec)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_SECURE                       0x0
+#define GPIO_Q_OUTPUT_CONTROL_07_0_DUAL                         0x0
+#define GPIO_Q_OUTPUT_CONTROL_07_0_SCR                  GPIO_Q_SCR_07_0
+#define GPIO_Q_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_Q_SCR_07_0
+#define GPIO_Q_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
+#define GPIO_Q_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_Q_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_Q_OUTPUT_VALUE_07_0
+#define GPIO_Q_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x126f0)
+#define GPIO_Q_OUTPUT_VALUE_07_0_SECURE                         0x0
+#define GPIO_Q_OUTPUT_VALUE_07_0_DUAL                   0x0
+#define GPIO_Q_OUTPUT_VALUE_07_0_SCR                    GPIO_Q_SCR_07_0
+#define GPIO_Q_OUTPUT_VALUE_07_0_SCRREG                         GPIO_Q_SCR_07_0
+#define GPIO_Q_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
+#define GPIO_Q_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_Q_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INTERRUPT_CLEAR_07_0
+#define GPIO_Q_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x126f4)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_SECURE                      0x0
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_DUAL                        0x0
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_SCR                         GPIO_Q_SCR_07_0
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_Q_SCR_07_0
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_Q_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x126f8
+
+// Reserved address 0x126fc
+
+// Register GPIO_Q_INTERRUPT_STATUS_G0_0
+#define GPIO_Q_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x12700)
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INTERRUPT_STATUS_G1_0
+#define GPIO_Q_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x12704)
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INTERRUPT_STATUS_G2_0
+#define GPIO_Q_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x12708)
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INTERRUPT_STATUS_G3_0
+#define GPIO_Q_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1270c)
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INTERRUPT_STATUS_G4_0
+#define GPIO_Q_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x12710)
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INTERRUPT_STATUS_G5_0
+#define GPIO_Q_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x12714)
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INTERRUPT_STATUS_G6_0
+#define GPIO_Q_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x12718)
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_Q_INTERRUPT_STATUS_G7_0
+#define GPIO_Q_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1271c)
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_Q_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x12720
+
+// Reserved address 0x12724
+
+// Reserved address 0x12728
+
+// Reserved address 0x1272c
+
+// Reserved address 0x12730
+
+// Reserved address 0x12734
+
+// Reserved address 0x12738
+
+// Reserved address 0x1273c
+
+// Reserved address 0x12740
+
+// Reserved address 0x12744
+
+// Reserved address 0x12748
+
+// Reserved address 0x1274c
+
+// Reserved address 0x12750
+
+// Reserved address 0x12754
+
+// Reserved address 0x12758
+
+// Reserved address 0x1275c
+
+// Reserved address 0x12760
+
+// Reserved address 0x12764
+
+// Reserved address 0x12768
+
+// Reserved address 0x1276c
+
+// Reserved address 0x12770
+
+// Reserved address 0x12774
+
+// Reserved address 0x12778
+
+// Reserved address 0x1277c
+
+// Reserved address 0x12780
+
+// Reserved address 0x12784
+
+// Reserved address 0x12788
+
+// Reserved address 0x1278c
+
+// Reserved address 0x12790
+
+// Reserved address 0x12794
+
+// Reserved address 0x12798
+
+// Reserved address 0x1279c
+
+// Reserved address 0x127a0
+
+// Reserved address 0x127a4
+
+// Reserved address 0x127a8
+
+// Reserved address 0x127ac
+
+// Reserved address 0x127b0
+
+// Reserved address 0x127b4
+
+// Reserved address 0x127b8
+
+// Reserved address 0x127bc
+
+// Reserved address 0x127c0
+
+// Reserved address 0x127c4
+
+// Reserved address 0x127c8
+
+// Reserved address 0x127cc
+
+// Reserved address 0x127d0
+
+// Reserved address 0x127d4
+
+// Reserved address 0x127d8
+
+// Reserved address 0x127dc
+
+// Reserved address 0x127e0
+
+// Reserved address 0x127e4
+
+// Reserved address 0x127e8
+
+// Reserved address 0x127ec
+
+// Reserved address 0x127f0
+
+// Reserved address 0x127f4
+
+// Reserved address 0x127f8
+
+// Reserved address 0x127fc
+
+// Register GPIO_R_ENABLE_CONFIG_00_0
+#define GPIO_R_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x12800)
+#define GPIO_R_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_R_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_R_ENABLE_CONFIG_00_0_SCR                   GPIO_R_SCR_00_0
+#define GPIO_R_ENABLE_CONFIG_00_0_SCRREG                        GPIO_R_SCR_00_0
+#define GPIO_R_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_R_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_R_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x12804)
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_R_SCR_00_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_R_SCR_00_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_R_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INPUT_00_0
+#define GPIO_R_INPUT_00_0                       MK_ADDR_CONST(0x12808)
+#define GPIO_R_INPUT_00_0_SECURE                        0x0
+#define GPIO_R_INPUT_00_0_DUAL                  0x0
+#define GPIO_R_INPUT_00_0_SCR                   GPIO_R_SCR_00_0
+#define GPIO_R_INPUT_00_0_SCRREG                        GPIO_R_SCR_00_0
+#define GPIO_R_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_R_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_R_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_R_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_R_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_R_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_OUTPUT_CONTROL_00_0
+#define GPIO_R_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1280c)
+#define GPIO_R_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_R_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_R_OUTPUT_CONTROL_00_0_SCR                  GPIO_R_SCR_00_0
+#define GPIO_R_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_R_SCR_00_0
+#define GPIO_R_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_R_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_R_OUTPUT_VALUE_00_0
+#define GPIO_R_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x12810)
+#define GPIO_R_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_R_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_R_OUTPUT_VALUE_00_0_SCR                    GPIO_R_SCR_00_0
+#define GPIO_R_OUTPUT_VALUE_00_0_SCRREG                         GPIO_R_SCR_00_0
+#define GPIO_R_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_R_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INTERRUPT_CLEAR_00_0
+#define GPIO_R_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x12814)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_R_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_R_INTERRUPT_CLEAR_00_0_SCR                         GPIO_R_SCR_00_0
+#define GPIO_R_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_R_SCR_00_0
+#define GPIO_R_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_R_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12818
+
+// Reserved address 0x1281c
+
+// Register GPIO_R_ENABLE_CONFIG_01_0
+#define GPIO_R_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x12820)
+#define GPIO_R_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_R_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_R_ENABLE_CONFIG_01_0_SCR                   GPIO_R_SCR_01_0
+#define GPIO_R_ENABLE_CONFIG_01_0_SCRREG                        GPIO_R_SCR_01_0
+#define GPIO_R_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_R_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_R_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x12824)
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_R_SCR_01_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_R_SCR_01_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_R_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INPUT_01_0
+#define GPIO_R_INPUT_01_0                       MK_ADDR_CONST(0x12828)
+#define GPIO_R_INPUT_01_0_SECURE                        0x0
+#define GPIO_R_INPUT_01_0_DUAL                  0x0
+#define GPIO_R_INPUT_01_0_SCR                   GPIO_R_SCR_01_0
+#define GPIO_R_INPUT_01_0_SCRREG                        GPIO_R_SCR_01_0
+#define GPIO_R_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_R_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_R_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_R_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_R_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_R_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_OUTPUT_CONTROL_01_0
+#define GPIO_R_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1282c)
+#define GPIO_R_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_R_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_R_OUTPUT_CONTROL_01_0_SCR                  GPIO_R_SCR_01_0
+#define GPIO_R_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_R_SCR_01_0
+#define GPIO_R_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_R_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_R_OUTPUT_VALUE_01_0
+#define GPIO_R_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x12830)
+#define GPIO_R_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_R_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_R_OUTPUT_VALUE_01_0_SCR                    GPIO_R_SCR_01_0
+#define GPIO_R_OUTPUT_VALUE_01_0_SCRREG                         GPIO_R_SCR_01_0
+#define GPIO_R_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_R_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INTERRUPT_CLEAR_01_0
+#define GPIO_R_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x12834)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_R_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_R_INTERRUPT_CLEAR_01_0_SCR                         GPIO_R_SCR_01_0
+#define GPIO_R_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_R_SCR_01_0
+#define GPIO_R_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_R_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12838
+
+// Reserved address 0x1283c
+
+// Register GPIO_R_ENABLE_CONFIG_02_0
+#define GPIO_R_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x12840)
+#define GPIO_R_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_R_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_R_ENABLE_CONFIG_02_0_SCR                   GPIO_R_SCR_02_0
+#define GPIO_R_ENABLE_CONFIG_02_0_SCRREG                        GPIO_R_SCR_02_0
+#define GPIO_R_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_R_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_R_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x12844)
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_R_SCR_02_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_R_SCR_02_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_R_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INPUT_02_0
+#define GPIO_R_INPUT_02_0                       MK_ADDR_CONST(0x12848)
+#define GPIO_R_INPUT_02_0_SECURE                        0x0
+#define GPIO_R_INPUT_02_0_DUAL                  0x0
+#define GPIO_R_INPUT_02_0_SCR                   GPIO_R_SCR_02_0
+#define GPIO_R_INPUT_02_0_SCRREG                        GPIO_R_SCR_02_0
+#define GPIO_R_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_R_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_R_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_R_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_R_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_R_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_OUTPUT_CONTROL_02_0
+#define GPIO_R_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1284c)
+#define GPIO_R_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_R_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_R_OUTPUT_CONTROL_02_0_SCR                  GPIO_R_SCR_02_0
+#define GPIO_R_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_R_SCR_02_0
+#define GPIO_R_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_R_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_R_OUTPUT_VALUE_02_0
+#define GPIO_R_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x12850)
+#define GPIO_R_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_R_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_R_OUTPUT_VALUE_02_0_SCR                    GPIO_R_SCR_02_0
+#define GPIO_R_OUTPUT_VALUE_02_0_SCRREG                         GPIO_R_SCR_02_0
+#define GPIO_R_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_R_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INTERRUPT_CLEAR_02_0
+#define GPIO_R_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x12854)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_R_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_R_INTERRUPT_CLEAR_02_0_SCR                         GPIO_R_SCR_02_0
+#define GPIO_R_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_R_SCR_02_0
+#define GPIO_R_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_R_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12858
+
+// Reserved address 0x1285c
+
+// Register GPIO_R_ENABLE_CONFIG_03_0
+#define GPIO_R_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x12860)
+#define GPIO_R_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_R_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_R_ENABLE_CONFIG_03_0_SCR                   GPIO_R_SCR_03_0
+#define GPIO_R_ENABLE_CONFIG_03_0_SCRREG                        GPIO_R_SCR_03_0
+#define GPIO_R_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_R_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_R_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x12864)
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_R_SCR_03_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_R_SCR_03_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_R_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INPUT_03_0
+#define GPIO_R_INPUT_03_0                       MK_ADDR_CONST(0x12868)
+#define GPIO_R_INPUT_03_0_SECURE                        0x0
+#define GPIO_R_INPUT_03_0_DUAL                  0x0
+#define GPIO_R_INPUT_03_0_SCR                   GPIO_R_SCR_03_0
+#define GPIO_R_INPUT_03_0_SCRREG                        GPIO_R_SCR_03_0
+#define GPIO_R_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_R_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_R_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_R_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_R_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_R_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_OUTPUT_CONTROL_03_0
+#define GPIO_R_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1286c)
+#define GPIO_R_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_R_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_R_OUTPUT_CONTROL_03_0_SCR                  GPIO_R_SCR_03_0
+#define GPIO_R_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_R_SCR_03_0
+#define GPIO_R_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_R_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_R_OUTPUT_VALUE_03_0
+#define GPIO_R_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x12870)
+#define GPIO_R_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_R_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_R_OUTPUT_VALUE_03_0_SCR                    GPIO_R_SCR_03_0
+#define GPIO_R_OUTPUT_VALUE_03_0_SCRREG                         GPIO_R_SCR_03_0
+#define GPIO_R_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_R_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INTERRUPT_CLEAR_03_0
+#define GPIO_R_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x12874)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_R_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_R_INTERRUPT_CLEAR_03_0_SCR                         GPIO_R_SCR_03_0
+#define GPIO_R_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_R_SCR_03_0
+#define GPIO_R_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_R_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12878
+
+// Reserved address 0x1287c
+
+// Register GPIO_R_ENABLE_CONFIG_04_0
+#define GPIO_R_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x12880)
+#define GPIO_R_ENABLE_CONFIG_04_0_SECURE                        0x0
+#define GPIO_R_ENABLE_CONFIG_04_0_DUAL                  0x0
+#define GPIO_R_ENABLE_CONFIG_04_0_SCR                   GPIO_R_SCR_04_0
+#define GPIO_R_ENABLE_CONFIG_04_0_SCRREG                        GPIO_R_SCR_04_0
+#define GPIO_R_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
+#define GPIO_R_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
+#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_R_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x12884)
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_R_SCR_04_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_R_SCR_04_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_R_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INPUT_04_0
+#define GPIO_R_INPUT_04_0                       MK_ADDR_CONST(0x12888)
+#define GPIO_R_INPUT_04_0_SECURE                        0x0
+#define GPIO_R_INPUT_04_0_DUAL                  0x0
+#define GPIO_R_INPUT_04_0_SCR                   GPIO_R_SCR_04_0
+#define GPIO_R_INPUT_04_0_SCRREG                        GPIO_R_SCR_04_0
+#define GPIO_R_INPUT_04_0_WORD_COUNT                    0x1
+#define GPIO_R_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_R_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_R_INPUT_04_0_GPIO_IN_RANGE                 0:0
+#define GPIO_R_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_R_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_OUTPUT_CONTROL_04_0
+#define GPIO_R_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1288c)
+#define GPIO_R_OUTPUT_CONTROL_04_0_SECURE                       0x0
+#define GPIO_R_OUTPUT_CONTROL_04_0_DUAL                         0x0
+#define GPIO_R_OUTPUT_CONTROL_04_0_SCR                  GPIO_R_SCR_04_0
+#define GPIO_R_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_R_SCR_04_0
+#define GPIO_R_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
+#define GPIO_R_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_R_OUTPUT_VALUE_04_0
+#define GPIO_R_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x12890)
+#define GPIO_R_OUTPUT_VALUE_04_0_SECURE                         0x0
+#define GPIO_R_OUTPUT_VALUE_04_0_DUAL                   0x0
+#define GPIO_R_OUTPUT_VALUE_04_0_SCR                    GPIO_R_SCR_04_0
+#define GPIO_R_OUTPUT_VALUE_04_0_SCRREG                         GPIO_R_SCR_04_0
+#define GPIO_R_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
+#define GPIO_R_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INTERRUPT_CLEAR_04_0
+#define GPIO_R_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x12894)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_SECURE                      0x0
+#define GPIO_R_INTERRUPT_CLEAR_04_0_DUAL                        0x0
+#define GPIO_R_INTERRUPT_CLEAR_04_0_SCR                         GPIO_R_SCR_04_0
+#define GPIO_R_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_R_SCR_04_0
+#define GPIO_R_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
+#define GPIO_R_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x12898
+
+// Reserved address 0x1289c
+
+// Register GPIO_R_ENABLE_CONFIG_05_0
+#define GPIO_R_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x128a0)
+#define GPIO_R_ENABLE_CONFIG_05_0_SECURE                        0x0
+#define GPIO_R_ENABLE_CONFIG_05_0_DUAL                  0x0
+#define GPIO_R_ENABLE_CONFIG_05_0_SCR                   GPIO_R_SCR_05_0
+#define GPIO_R_ENABLE_CONFIG_05_0_SCRREG                        GPIO_R_SCR_05_0
+#define GPIO_R_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
+#define GPIO_R_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
+#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_R_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_R_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x128a4)
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_R_SCR_05_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_R_SCR_05_0
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_R_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INPUT_05_0
+#define GPIO_R_INPUT_05_0                       MK_ADDR_CONST(0x128a8)
+#define GPIO_R_INPUT_05_0_SECURE                        0x0
+#define GPIO_R_INPUT_05_0_DUAL                  0x0
+#define GPIO_R_INPUT_05_0_SCR                   GPIO_R_SCR_05_0
+#define GPIO_R_INPUT_05_0_SCRREG                        GPIO_R_SCR_05_0
+#define GPIO_R_INPUT_05_0_WORD_COUNT                    0x1
+#define GPIO_R_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_R_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_R_INPUT_05_0_GPIO_IN_RANGE                 0:0
+#define GPIO_R_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_R_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_R_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_R_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_OUTPUT_CONTROL_05_0
+#define GPIO_R_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x128ac)
+#define GPIO_R_OUTPUT_CONTROL_05_0_SECURE                       0x0
+#define GPIO_R_OUTPUT_CONTROL_05_0_DUAL                         0x0
+#define GPIO_R_OUTPUT_CONTROL_05_0_SCR                  GPIO_R_SCR_05_0
+#define GPIO_R_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_R_SCR_05_0
+#define GPIO_R_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
+#define GPIO_R_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_R_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_R_OUTPUT_VALUE_05_0
+#define GPIO_R_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x128b0)
+#define GPIO_R_OUTPUT_VALUE_05_0_SECURE                         0x0
+#define GPIO_R_OUTPUT_VALUE_05_0_DUAL                   0x0
+#define GPIO_R_OUTPUT_VALUE_05_0_SCR                    GPIO_R_SCR_05_0
+#define GPIO_R_OUTPUT_VALUE_05_0_SCRREG                         GPIO_R_SCR_05_0
+#define GPIO_R_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
+#define GPIO_R_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_R_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INTERRUPT_CLEAR_05_0
+#define GPIO_R_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x128b4)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_SECURE                      0x0
+#define GPIO_R_INTERRUPT_CLEAR_05_0_DUAL                        0x0
+#define GPIO_R_INTERRUPT_CLEAR_05_0_SCR                         GPIO_R_SCR_05_0
+#define GPIO_R_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_R_SCR_05_0
+#define GPIO_R_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
+#define GPIO_R_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_R_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x128b8
+
+// Reserved address 0x128bc
+
+// Reserved address 0x128c0
+
+// Reserved address 0x128c4
+
+// Reserved address 0x128c8
+
+// Reserved address 0x128cc
+
+// Reserved address 0x128d0
+
+// Reserved address 0x128d4
+
+// Reserved address 0x128d8
+
+// Reserved address 0x128dc
+
+// Reserved address 0x128e0
+
+// Reserved address 0x128e4
+
+// Reserved address 0x128e8
+
+// Reserved address 0x128ec
+
+// Reserved address 0x128f0
+
+// Reserved address 0x128f4
+
+// Reserved address 0x128f8
+
+// Reserved address 0x128fc
+
+// Register GPIO_R_INTERRUPT_STATUS_G0_0
+#define GPIO_R_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x12900)
+#define GPIO_R_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_R_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_R_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_R_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_R_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_R_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INTERRUPT_STATUS_G1_0
+#define GPIO_R_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x12904)
+#define GPIO_R_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_R_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_R_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_R_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_R_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_R_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INTERRUPT_STATUS_G2_0
+#define GPIO_R_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x12908)
+#define GPIO_R_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_R_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_R_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_R_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_R_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_R_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INTERRUPT_STATUS_G3_0
+#define GPIO_R_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1290c)
+#define GPIO_R_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_R_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_R_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_R_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_R_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_R_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INTERRUPT_STATUS_G4_0
+#define GPIO_R_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x12910)
+#define GPIO_R_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_R_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_R_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_R_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_R_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_R_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INTERRUPT_STATUS_G5_0
+#define GPIO_R_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x12914)
+#define GPIO_R_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_R_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_R_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_R_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_R_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_R_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INTERRUPT_STATUS_G6_0
+#define GPIO_R_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x12918)
+#define GPIO_R_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_R_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_R_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_R_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_R_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_R_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_R_INTERRUPT_STATUS_G7_0
+#define GPIO_R_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1291c)
+#define GPIO_R_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_R_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_R_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_R_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_R_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_R_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_R_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x12920
+
+// Reserved address 0x12924
+
+// Reserved address 0x12928
+
+// Reserved address 0x1292c
+
+// Reserved address 0x12930
+
+// Reserved address 0x12934
+
+// Reserved address 0x12938
+
+// Reserved address 0x1293c
+
+// Reserved address 0x12940
+
+// Reserved address 0x12944
+
+// Reserved address 0x12948
+
+// Reserved address 0x1294c
+
+// Reserved address 0x12950
+
+// Reserved address 0x12954
+
+// Reserved address 0x12958
+
+// Reserved address 0x1295c
+
+// Reserved address 0x12960
+
+// Reserved address 0x12964
+
+// Reserved address 0x12968
+
+// Reserved address 0x1296c
+
+// Reserved address 0x12970
+
+// Reserved address 0x12974
+
+// Reserved address 0x12978
+
+// Reserved address 0x1297c
+
+// Reserved address 0x12980
+
+// Reserved address 0x12984
+
+// Reserved address 0x12988
+
+// Reserved address 0x1298c
+
+// Reserved address 0x12990
+
+// Reserved address 0x12994
+
+// Reserved address 0x12998
+
+// Reserved address 0x1299c
+
+// Reserved address 0x129a0
+
+// Reserved address 0x129a4
+
+// Reserved address 0x129a8
+
+// Reserved address 0x129ac
+
+// Reserved address 0x129b0
+
+// Reserved address 0x129b4
+
+// Reserved address 0x129b8
+
+// Reserved address 0x129bc
+
+// Reserved address 0x129c0
+
+// Reserved address 0x129c4
+
+// Reserved address 0x129c8
+
+// Reserved address 0x129cc
+
+// Reserved address 0x129d0
+
+// Reserved address 0x129d4
+
+// Reserved address 0x129d8
+
+// Reserved address 0x129dc
+
+// Reserved address 0x129e0
+
+// Reserved address 0x129e4
+
+// Reserved address 0x129e8
+
+// Reserved address 0x129ec
+
+// Reserved address 0x129f0
+
+// Reserved address 0x129f4
+
+// Reserved address 0x129f8
+
+// Reserved address 0x129fc
+
+// Register GPIO_K_ENABLE_CONFIG_00_0
+#define GPIO_K_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x13000)
+#define GPIO_K_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_K_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_K_ENABLE_CONFIG_00_0_SCR                   GPIO_K_SCR_00_0
+#define GPIO_K_ENABLE_CONFIG_00_0_SCRREG                        GPIO_K_SCR_00_0
+#define GPIO_K_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_K_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_K_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x13004)
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_K_SCR_00_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_K_SCR_00_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_K_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INPUT_00_0
+#define GPIO_K_INPUT_00_0                       MK_ADDR_CONST(0x13008)
+#define GPIO_K_INPUT_00_0_SECURE                        0x0
+#define GPIO_K_INPUT_00_0_DUAL                  0x0
+#define GPIO_K_INPUT_00_0_SCR                   GPIO_K_SCR_00_0
+#define GPIO_K_INPUT_00_0_SCRREG                        GPIO_K_SCR_00_0
+#define GPIO_K_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_K_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_K_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_K_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_K_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_K_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_OUTPUT_CONTROL_00_0
+#define GPIO_K_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1300c)
+#define GPIO_K_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_K_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_K_OUTPUT_CONTROL_00_0_SCR                  GPIO_K_SCR_00_0
+#define GPIO_K_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_K_SCR_00_0
+#define GPIO_K_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_K_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_K_OUTPUT_VALUE_00_0
+#define GPIO_K_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x13010)
+#define GPIO_K_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_K_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_K_OUTPUT_VALUE_00_0_SCR                    GPIO_K_SCR_00_0
+#define GPIO_K_OUTPUT_VALUE_00_0_SCRREG                         GPIO_K_SCR_00_0
+#define GPIO_K_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_K_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INTERRUPT_CLEAR_00_0
+#define GPIO_K_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x13014)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_K_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_K_INTERRUPT_CLEAR_00_0_SCR                         GPIO_K_SCR_00_0
+#define GPIO_K_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_K_SCR_00_0
+#define GPIO_K_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_K_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13018
+
+// Reserved address 0x1301c
+
+// Register GPIO_K_ENABLE_CONFIG_01_0
+#define GPIO_K_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x13020)
+#define GPIO_K_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_K_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_K_ENABLE_CONFIG_01_0_SCR                   GPIO_K_SCR_01_0
+#define GPIO_K_ENABLE_CONFIG_01_0_SCRREG                        GPIO_K_SCR_01_0
+#define GPIO_K_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_K_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_K_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x13024)
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_K_SCR_01_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_K_SCR_01_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_K_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INPUT_01_0
+#define GPIO_K_INPUT_01_0                       MK_ADDR_CONST(0x13028)
+#define GPIO_K_INPUT_01_0_SECURE                        0x0
+#define GPIO_K_INPUT_01_0_DUAL                  0x0
+#define GPIO_K_INPUT_01_0_SCR                   GPIO_K_SCR_01_0
+#define GPIO_K_INPUT_01_0_SCRREG                        GPIO_K_SCR_01_0
+#define GPIO_K_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_K_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_K_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_K_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_K_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_K_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_OUTPUT_CONTROL_01_0
+#define GPIO_K_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1302c)
+#define GPIO_K_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_K_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_K_OUTPUT_CONTROL_01_0_SCR                  GPIO_K_SCR_01_0
+#define GPIO_K_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_K_SCR_01_0
+#define GPIO_K_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_K_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_K_OUTPUT_VALUE_01_0
+#define GPIO_K_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x13030)
+#define GPIO_K_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_K_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_K_OUTPUT_VALUE_01_0_SCR                    GPIO_K_SCR_01_0
+#define GPIO_K_OUTPUT_VALUE_01_0_SCRREG                         GPIO_K_SCR_01_0
+#define GPIO_K_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_K_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INTERRUPT_CLEAR_01_0
+#define GPIO_K_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x13034)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_K_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_K_INTERRUPT_CLEAR_01_0_SCR                         GPIO_K_SCR_01_0
+#define GPIO_K_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_K_SCR_01_0
+#define GPIO_K_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_K_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13038
+
+// Reserved address 0x1303c
+
+// Register GPIO_K_ENABLE_CONFIG_02_0
+#define GPIO_K_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x13040)
+#define GPIO_K_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_K_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_K_ENABLE_CONFIG_02_0_SCR                   GPIO_K_SCR_02_0
+#define GPIO_K_ENABLE_CONFIG_02_0_SCRREG                        GPIO_K_SCR_02_0
+#define GPIO_K_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_K_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_K_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x13044)
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_K_SCR_02_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_K_SCR_02_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_K_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INPUT_02_0
+#define GPIO_K_INPUT_02_0                       MK_ADDR_CONST(0x13048)
+#define GPIO_K_INPUT_02_0_SECURE                        0x0
+#define GPIO_K_INPUT_02_0_DUAL                  0x0
+#define GPIO_K_INPUT_02_0_SCR                   GPIO_K_SCR_02_0
+#define GPIO_K_INPUT_02_0_SCRREG                        GPIO_K_SCR_02_0
+#define GPIO_K_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_K_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_K_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_K_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_K_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_K_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_OUTPUT_CONTROL_02_0
+#define GPIO_K_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1304c)
+#define GPIO_K_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_K_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_K_OUTPUT_CONTROL_02_0_SCR                  GPIO_K_SCR_02_0
+#define GPIO_K_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_K_SCR_02_0
+#define GPIO_K_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_K_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_K_OUTPUT_VALUE_02_0
+#define GPIO_K_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x13050)
+#define GPIO_K_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_K_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_K_OUTPUT_VALUE_02_0_SCR                    GPIO_K_SCR_02_0
+#define GPIO_K_OUTPUT_VALUE_02_0_SCRREG                         GPIO_K_SCR_02_0
+#define GPIO_K_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_K_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INTERRUPT_CLEAR_02_0
+#define GPIO_K_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x13054)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_K_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_K_INTERRUPT_CLEAR_02_0_SCR                         GPIO_K_SCR_02_0
+#define GPIO_K_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_K_SCR_02_0
+#define GPIO_K_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_K_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13058
+
+// Reserved address 0x1305c
+
+// Register GPIO_K_ENABLE_CONFIG_03_0
+#define GPIO_K_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x13060)
+#define GPIO_K_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_K_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_K_ENABLE_CONFIG_03_0_SCR                   GPIO_K_SCR_03_0
+#define GPIO_K_ENABLE_CONFIG_03_0_SCRREG                        GPIO_K_SCR_03_0
+#define GPIO_K_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_K_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_K_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x13064)
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_K_SCR_03_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_K_SCR_03_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_K_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INPUT_03_0
+#define GPIO_K_INPUT_03_0                       MK_ADDR_CONST(0x13068)
+#define GPIO_K_INPUT_03_0_SECURE                        0x0
+#define GPIO_K_INPUT_03_0_DUAL                  0x0
+#define GPIO_K_INPUT_03_0_SCR                   GPIO_K_SCR_03_0
+#define GPIO_K_INPUT_03_0_SCRREG                        GPIO_K_SCR_03_0
+#define GPIO_K_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_K_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_K_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_K_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_K_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_K_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_OUTPUT_CONTROL_03_0
+#define GPIO_K_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1306c)
+#define GPIO_K_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_K_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_K_OUTPUT_CONTROL_03_0_SCR                  GPIO_K_SCR_03_0
+#define GPIO_K_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_K_SCR_03_0
+#define GPIO_K_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_K_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_K_OUTPUT_VALUE_03_0
+#define GPIO_K_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x13070)
+#define GPIO_K_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_K_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_K_OUTPUT_VALUE_03_0_SCR                    GPIO_K_SCR_03_0
+#define GPIO_K_OUTPUT_VALUE_03_0_SCRREG                         GPIO_K_SCR_03_0
+#define GPIO_K_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_K_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INTERRUPT_CLEAR_03_0
+#define GPIO_K_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x13074)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_K_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_K_INTERRUPT_CLEAR_03_0_SCR                         GPIO_K_SCR_03_0
+#define GPIO_K_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_K_SCR_03_0
+#define GPIO_K_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_K_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13078
+
+// Reserved address 0x1307c
+
+// Register GPIO_K_ENABLE_CONFIG_04_0
+#define GPIO_K_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x13080)
+#define GPIO_K_ENABLE_CONFIG_04_0_SECURE                        0x0
+#define GPIO_K_ENABLE_CONFIG_04_0_DUAL                  0x0
+#define GPIO_K_ENABLE_CONFIG_04_0_SCR                   GPIO_K_SCR_04_0
+#define GPIO_K_ENABLE_CONFIG_04_0_SCRREG                        GPIO_K_SCR_04_0
+#define GPIO_K_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
+#define GPIO_K_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
+#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_K_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x13084)
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_K_SCR_04_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_K_SCR_04_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_K_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INPUT_04_0
+#define GPIO_K_INPUT_04_0                       MK_ADDR_CONST(0x13088)
+#define GPIO_K_INPUT_04_0_SECURE                        0x0
+#define GPIO_K_INPUT_04_0_DUAL                  0x0
+#define GPIO_K_INPUT_04_0_SCR                   GPIO_K_SCR_04_0
+#define GPIO_K_INPUT_04_0_SCRREG                        GPIO_K_SCR_04_0
+#define GPIO_K_INPUT_04_0_WORD_COUNT                    0x1
+#define GPIO_K_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_K_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_K_INPUT_04_0_GPIO_IN_RANGE                 0:0
+#define GPIO_K_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_K_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_OUTPUT_CONTROL_04_0
+#define GPIO_K_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1308c)
+#define GPIO_K_OUTPUT_CONTROL_04_0_SECURE                       0x0
+#define GPIO_K_OUTPUT_CONTROL_04_0_DUAL                         0x0
+#define GPIO_K_OUTPUT_CONTROL_04_0_SCR                  GPIO_K_SCR_04_0
+#define GPIO_K_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_K_SCR_04_0
+#define GPIO_K_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
+#define GPIO_K_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_K_OUTPUT_VALUE_04_0
+#define GPIO_K_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x13090)
+#define GPIO_K_OUTPUT_VALUE_04_0_SECURE                         0x0
+#define GPIO_K_OUTPUT_VALUE_04_0_DUAL                   0x0
+#define GPIO_K_OUTPUT_VALUE_04_0_SCR                    GPIO_K_SCR_04_0
+#define GPIO_K_OUTPUT_VALUE_04_0_SCRREG                         GPIO_K_SCR_04_0
+#define GPIO_K_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
+#define GPIO_K_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INTERRUPT_CLEAR_04_0
+#define GPIO_K_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x13094)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_SECURE                      0x0
+#define GPIO_K_INTERRUPT_CLEAR_04_0_DUAL                        0x0
+#define GPIO_K_INTERRUPT_CLEAR_04_0_SCR                         GPIO_K_SCR_04_0
+#define GPIO_K_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_K_SCR_04_0
+#define GPIO_K_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
+#define GPIO_K_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13098
+
+// Reserved address 0x1309c
+
+// Register GPIO_K_ENABLE_CONFIG_05_0
+#define GPIO_K_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x130a0)
+#define GPIO_K_ENABLE_CONFIG_05_0_SECURE                        0x0
+#define GPIO_K_ENABLE_CONFIG_05_0_DUAL                  0x0
+#define GPIO_K_ENABLE_CONFIG_05_0_SCR                   GPIO_K_SCR_05_0
+#define GPIO_K_ENABLE_CONFIG_05_0_SCRREG                        GPIO_K_SCR_05_0
+#define GPIO_K_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
+#define GPIO_K_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
+#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_K_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x130a4)
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_K_SCR_05_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_K_SCR_05_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_K_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INPUT_05_0
+#define GPIO_K_INPUT_05_0                       MK_ADDR_CONST(0x130a8)
+#define GPIO_K_INPUT_05_0_SECURE                        0x0
+#define GPIO_K_INPUT_05_0_DUAL                  0x0
+#define GPIO_K_INPUT_05_0_SCR                   GPIO_K_SCR_05_0
+#define GPIO_K_INPUT_05_0_SCRREG                        GPIO_K_SCR_05_0
+#define GPIO_K_INPUT_05_0_WORD_COUNT                    0x1
+#define GPIO_K_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_K_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_K_INPUT_05_0_GPIO_IN_RANGE                 0:0
+#define GPIO_K_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_K_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_OUTPUT_CONTROL_05_0
+#define GPIO_K_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x130ac)
+#define GPIO_K_OUTPUT_CONTROL_05_0_SECURE                       0x0
+#define GPIO_K_OUTPUT_CONTROL_05_0_DUAL                         0x0
+#define GPIO_K_OUTPUT_CONTROL_05_0_SCR                  GPIO_K_SCR_05_0
+#define GPIO_K_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_K_SCR_05_0
+#define GPIO_K_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
+#define GPIO_K_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_K_OUTPUT_VALUE_05_0
+#define GPIO_K_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x130b0)
+#define GPIO_K_OUTPUT_VALUE_05_0_SECURE                         0x0
+#define GPIO_K_OUTPUT_VALUE_05_0_DUAL                   0x0
+#define GPIO_K_OUTPUT_VALUE_05_0_SCR                    GPIO_K_SCR_05_0
+#define GPIO_K_OUTPUT_VALUE_05_0_SCRREG                         GPIO_K_SCR_05_0
+#define GPIO_K_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
+#define GPIO_K_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INTERRUPT_CLEAR_05_0
+#define GPIO_K_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x130b4)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_SECURE                      0x0
+#define GPIO_K_INTERRUPT_CLEAR_05_0_DUAL                        0x0
+#define GPIO_K_INTERRUPT_CLEAR_05_0_SCR                         GPIO_K_SCR_05_0
+#define GPIO_K_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_K_SCR_05_0
+#define GPIO_K_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
+#define GPIO_K_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x130b8
+
+// Reserved address 0x130bc
+
+// Register GPIO_K_ENABLE_CONFIG_06_0
+#define GPIO_K_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x130c0)
+#define GPIO_K_ENABLE_CONFIG_06_0_SECURE                        0x0
+#define GPIO_K_ENABLE_CONFIG_06_0_DUAL                  0x0
+#define GPIO_K_ENABLE_CONFIG_06_0_SCR                   GPIO_K_SCR_06_0
+#define GPIO_K_ENABLE_CONFIG_06_0_SCRREG                        GPIO_K_SCR_06_0
+#define GPIO_K_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
+#define GPIO_K_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
+#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_K_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x130c4)
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_K_SCR_06_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_K_SCR_06_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_K_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INPUT_06_0
+#define GPIO_K_INPUT_06_0                       MK_ADDR_CONST(0x130c8)
+#define GPIO_K_INPUT_06_0_SECURE                        0x0
+#define GPIO_K_INPUT_06_0_DUAL                  0x0
+#define GPIO_K_INPUT_06_0_SCR                   GPIO_K_SCR_06_0
+#define GPIO_K_INPUT_06_0_SCRREG                        GPIO_K_SCR_06_0
+#define GPIO_K_INPUT_06_0_WORD_COUNT                    0x1
+#define GPIO_K_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_K_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_K_INPUT_06_0_GPIO_IN_RANGE                 0:0
+#define GPIO_K_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_K_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_OUTPUT_CONTROL_06_0
+#define GPIO_K_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x130cc)
+#define GPIO_K_OUTPUT_CONTROL_06_0_SECURE                       0x0
+#define GPIO_K_OUTPUT_CONTROL_06_0_DUAL                         0x0
+#define GPIO_K_OUTPUT_CONTROL_06_0_SCR                  GPIO_K_SCR_06_0
+#define GPIO_K_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_K_SCR_06_0
+#define GPIO_K_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
+#define GPIO_K_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_K_OUTPUT_VALUE_06_0
+#define GPIO_K_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x130d0)
+#define GPIO_K_OUTPUT_VALUE_06_0_SECURE                         0x0
+#define GPIO_K_OUTPUT_VALUE_06_0_DUAL                   0x0
+#define GPIO_K_OUTPUT_VALUE_06_0_SCR                    GPIO_K_SCR_06_0
+#define GPIO_K_OUTPUT_VALUE_06_0_SCRREG                         GPIO_K_SCR_06_0
+#define GPIO_K_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
+#define GPIO_K_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INTERRUPT_CLEAR_06_0
+#define GPIO_K_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x130d4)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_SECURE                      0x0
+#define GPIO_K_INTERRUPT_CLEAR_06_0_DUAL                        0x0
+#define GPIO_K_INTERRUPT_CLEAR_06_0_SCR                         GPIO_K_SCR_06_0
+#define GPIO_K_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_K_SCR_06_0
+#define GPIO_K_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
+#define GPIO_K_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x130d8
+
+// Reserved address 0x130dc
+
+// Register GPIO_K_ENABLE_CONFIG_07_0
+#define GPIO_K_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x130e0)
+#define GPIO_K_ENABLE_CONFIG_07_0_SECURE                        0x0
+#define GPIO_K_ENABLE_CONFIG_07_0_DUAL                  0x0
+#define GPIO_K_ENABLE_CONFIG_07_0_SCR                   GPIO_K_SCR_07_0
+#define GPIO_K_ENABLE_CONFIG_07_0_SCRREG                        GPIO_K_SCR_07_0
+#define GPIO_K_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
+#define GPIO_K_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
+#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_K_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_K_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x130e4)
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_K_SCR_07_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_K_SCR_07_0
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_K_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INPUT_07_0
+#define GPIO_K_INPUT_07_0                       MK_ADDR_CONST(0x130e8)
+#define GPIO_K_INPUT_07_0_SECURE                        0x0
+#define GPIO_K_INPUT_07_0_DUAL                  0x0
+#define GPIO_K_INPUT_07_0_SCR                   GPIO_K_SCR_07_0
+#define GPIO_K_INPUT_07_0_SCRREG                        GPIO_K_SCR_07_0
+#define GPIO_K_INPUT_07_0_WORD_COUNT                    0x1
+#define GPIO_K_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_K_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_K_INPUT_07_0_GPIO_IN_RANGE                 0:0
+#define GPIO_K_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_K_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_K_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_K_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_OUTPUT_CONTROL_07_0
+#define GPIO_K_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x130ec)
+#define GPIO_K_OUTPUT_CONTROL_07_0_SECURE                       0x0
+#define GPIO_K_OUTPUT_CONTROL_07_0_DUAL                         0x0
+#define GPIO_K_OUTPUT_CONTROL_07_0_SCR                  GPIO_K_SCR_07_0
+#define GPIO_K_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_K_SCR_07_0
+#define GPIO_K_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
+#define GPIO_K_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_K_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_K_OUTPUT_VALUE_07_0
+#define GPIO_K_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x130f0)
+#define GPIO_K_OUTPUT_VALUE_07_0_SECURE                         0x0
+#define GPIO_K_OUTPUT_VALUE_07_0_DUAL                   0x0
+#define GPIO_K_OUTPUT_VALUE_07_0_SCR                    GPIO_K_SCR_07_0
+#define GPIO_K_OUTPUT_VALUE_07_0_SCRREG                         GPIO_K_SCR_07_0
+#define GPIO_K_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
+#define GPIO_K_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_K_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INTERRUPT_CLEAR_07_0
+#define GPIO_K_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x130f4)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_SECURE                      0x0
+#define GPIO_K_INTERRUPT_CLEAR_07_0_DUAL                        0x0
+#define GPIO_K_INTERRUPT_CLEAR_07_0_SCR                         GPIO_K_SCR_07_0
+#define GPIO_K_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_K_SCR_07_0
+#define GPIO_K_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
+#define GPIO_K_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_K_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x130f8
+
+// Reserved address 0x130fc
+
+// Register GPIO_K_INTERRUPT_STATUS_G0_0
+#define GPIO_K_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x13100)
+#define GPIO_K_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_K_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_K_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_K_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_K_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_K_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INTERRUPT_STATUS_G1_0
+#define GPIO_K_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x13104)
+#define GPIO_K_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_K_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_K_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_K_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_K_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_K_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INTERRUPT_STATUS_G2_0
+#define GPIO_K_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x13108)
+#define GPIO_K_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_K_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_K_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_K_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_K_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_K_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INTERRUPT_STATUS_G3_0
+#define GPIO_K_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1310c)
+#define GPIO_K_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_K_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_K_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_K_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_K_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_K_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INTERRUPT_STATUS_G4_0
+#define GPIO_K_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x13110)
+#define GPIO_K_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_K_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_K_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_K_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_K_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_K_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INTERRUPT_STATUS_G5_0
+#define GPIO_K_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x13114)
+#define GPIO_K_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_K_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_K_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_K_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_K_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_K_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INTERRUPT_STATUS_G6_0
+#define GPIO_K_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x13118)
+#define GPIO_K_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_K_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_K_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_K_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_K_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_K_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_K_INTERRUPT_STATUS_G7_0
+#define GPIO_K_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1311c)
+#define GPIO_K_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_K_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_K_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_K_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_K_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_K_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_K_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x13120
+
+// Reserved address 0x13124
+
+// Reserved address 0x13128
+
+// Reserved address 0x1312c
+
+// Reserved address 0x13130
+
+// Reserved address 0x13134
+
+// Reserved address 0x13138
+
+// Reserved address 0x1313c
+
+// Reserved address 0x13140
+
+// Reserved address 0x13144
+
+// Reserved address 0x13148
+
+// Reserved address 0x1314c
+
+// Reserved address 0x13150
+
+// Reserved address 0x13154
+
+// Reserved address 0x13158
+
+// Reserved address 0x1315c
+
+// Reserved address 0x13160
+
+// Reserved address 0x13164
+
+// Reserved address 0x13168
+
+// Reserved address 0x1316c
+
+// Reserved address 0x13170
+
+// Reserved address 0x13174
+
+// Reserved address 0x13178
+
+// Reserved address 0x1317c
+
+// Reserved address 0x13180
+
+// Reserved address 0x13184
+
+// Reserved address 0x13188
+
+// Reserved address 0x1318c
+
+// Reserved address 0x13190
+
+// Reserved address 0x13194
+
+// Reserved address 0x13198
+
+// Reserved address 0x1319c
+
+// Reserved address 0x131a0
+
+// Reserved address 0x131a4
+
+// Reserved address 0x131a8
+
+// Reserved address 0x131ac
+
+// Reserved address 0x131b0
+
+// Reserved address 0x131b4
+
+// Reserved address 0x131b8
+
+// Reserved address 0x131bc
+
+// Reserved address 0x131c0
+
+// Reserved address 0x131c4
+
+// Reserved address 0x131c8
+
+// Reserved address 0x131cc
+
+// Reserved address 0x131d0
+
+// Reserved address 0x131d4
+
+// Reserved address 0x131d8
+
+// Reserved address 0x131dc
+
+// Reserved address 0x131e0
+
+// Reserved address 0x131e4
+
+// Reserved address 0x131e8
+
+// Reserved address 0x131ec
+
+// Reserved address 0x131f0
+
+// Reserved address 0x131f4
+
+// Reserved address 0x131f8
+
+// Reserved address 0x131fc
+
+// Register GPIO_L_ENABLE_CONFIG_00_0
+#define GPIO_L_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x13200)
+#define GPIO_L_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_L_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_L_ENABLE_CONFIG_00_0_SCR                   GPIO_L_SCR_00_0
+#define GPIO_L_ENABLE_CONFIG_00_0_SCRREG                        GPIO_L_SCR_00_0
+#define GPIO_L_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_L_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_L_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_L_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_L_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x13204)
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_L_SCR_00_0
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_L_SCR_00_0
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_L_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INPUT_00_0
+#define GPIO_L_INPUT_00_0                       MK_ADDR_CONST(0x13208)
+#define GPIO_L_INPUT_00_0_SECURE                        0x0
+#define GPIO_L_INPUT_00_0_DUAL                  0x0
+#define GPIO_L_INPUT_00_0_SCR                   GPIO_L_SCR_00_0
+#define GPIO_L_INPUT_00_0_SCRREG                        GPIO_L_SCR_00_0
+#define GPIO_L_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_L_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_L_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_L_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_L_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_L_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_L_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_L_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_L_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_L_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_OUTPUT_CONTROL_00_0
+#define GPIO_L_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1320c)
+#define GPIO_L_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_L_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_L_OUTPUT_CONTROL_00_0_SCR                  GPIO_L_SCR_00_0
+#define GPIO_L_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_L_SCR_00_0
+#define GPIO_L_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_L_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_L_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_L_OUTPUT_VALUE_00_0
+#define GPIO_L_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x13210)
+#define GPIO_L_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_L_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_L_OUTPUT_VALUE_00_0_SCR                    GPIO_L_SCR_00_0
+#define GPIO_L_OUTPUT_VALUE_00_0_SCRREG                         GPIO_L_SCR_00_0
+#define GPIO_L_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_L_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INTERRUPT_CLEAR_00_0
+#define GPIO_L_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x13214)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_L_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_L_INTERRUPT_CLEAR_00_0_SCR                         GPIO_L_SCR_00_0
+#define GPIO_L_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_L_SCR_00_0
+#define GPIO_L_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_L_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_L_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13218
+
+// Reserved address 0x1321c
+
+// Register GPIO_L_ENABLE_CONFIG_01_0
+#define GPIO_L_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x13220)
+#define GPIO_L_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_L_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_L_ENABLE_CONFIG_01_0_SCR                   GPIO_L_SCR_01_0
+#define GPIO_L_ENABLE_CONFIG_01_0_SCRREG                        GPIO_L_SCR_01_0
+#define GPIO_L_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_L_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_L_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_L_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_L_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x13224)
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_L_SCR_01_0
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_L_SCR_01_0
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_L_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INPUT_01_0
+#define GPIO_L_INPUT_01_0                       MK_ADDR_CONST(0x13228)
+#define GPIO_L_INPUT_01_0_SECURE                        0x0
+#define GPIO_L_INPUT_01_0_DUAL                  0x0
+#define GPIO_L_INPUT_01_0_SCR                   GPIO_L_SCR_01_0
+#define GPIO_L_INPUT_01_0_SCRREG                        GPIO_L_SCR_01_0
+#define GPIO_L_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_L_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_L_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_L_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_L_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_L_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_L_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_L_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_L_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_L_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_OUTPUT_CONTROL_01_0
+#define GPIO_L_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1322c)
+#define GPIO_L_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_L_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_L_OUTPUT_CONTROL_01_0_SCR                  GPIO_L_SCR_01_0
+#define GPIO_L_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_L_SCR_01_0
+#define GPIO_L_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_L_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_L_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_L_OUTPUT_VALUE_01_0
+#define GPIO_L_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x13230)
+#define GPIO_L_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_L_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_L_OUTPUT_VALUE_01_0_SCR                    GPIO_L_SCR_01_0
+#define GPIO_L_OUTPUT_VALUE_01_0_SCRREG                         GPIO_L_SCR_01_0
+#define GPIO_L_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_L_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INTERRUPT_CLEAR_01_0
+#define GPIO_L_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x13234)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_L_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_L_INTERRUPT_CLEAR_01_0_SCR                         GPIO_L_SCR_01_0
+#define GPIO_L_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_L_SCR_01_0
+#define GPIO_L_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_L_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_L_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13238
+
+// Reserved address 0x1323c
+
+// Register GPIO_L_ENABLE_CONFIG_02_0
+#define GPIO_L_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x13240)
+#define GPIO_L_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_L_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_L_ENABLE_CONFIG_02_0_SCR                   GPIO_L_SCR_02_0
+#define GPIO_L_ENABLE_CONFIG_02_0_SCRREG                        GPIO_L_SCR_02_0
+#define GPIO_L_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_L_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_L_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_L_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_L_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x13244)
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_L_SCR_02_0
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_L_SCR_02_0
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_L_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INPUT_02_0
+#define GPIO_L_INPUT_02_0                       MK_ADDR_CONST(0x13248)
+#define GPIO_L_INPUT_02_0_SECURE                        0x0
+#define GPIO_L_INPUT_02_0_DUAL                  0x0
+#define GPIO_L_INPUT_02_0_SCR                   GPIO_L_SCR_02_0
+#define GPIO_L_INPUT_02_0_SCRREG                        GPIO_L_SCR_02_0
+#define GPIO_L_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_L_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_L_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_L_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_L_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_L_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_L_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_L_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_L_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_L_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_OUTPUT_CONTROL_02_0
+#define GPIO_L_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1324c)
+#define GPIO_L_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_L_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_L_OUTPUT_CONTROL_02_0_SCR                  GPIO_L_SCR_02_0
+#define GPIO_L_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_L_SCR_02_0
+#define GPIO_L_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_L_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_L_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_L_OUTPUT_VALUE_02_0
+#define GPIO_L_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x13250)
+#define GPIO_L_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_L_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_L_OUTPUT_VALUE_02_0_SCR                    GPIO_L_SCR_02_0
+#define GPIO_L_OUTPUT_VALUE_02_0_SCRREG                         GPIO_L_SCR_02_0
+#define GPIO_L_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_L_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INTERRUPT_CLEAR_02_0
+#define GPIO_L_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x13254)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_L_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_L_INTERRUPT_CLEAR_02_0_SCR                         GPIO_L_SCR_02_0
+#define GPIO_L_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_L_SCR_02_0
+#define GPIO_L_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_L_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_L_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13258
+
+// Reserved address 0x1325c
+
+// Register GPIO_L_ENABLE_CONFIG_03_0
+#define GPIO_L_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x13260)
+#define GPIO_L_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_L_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_L_ENABLE_CONFIG_03_0_SCR                   GPIO_L_SCR_03_0
+#define GPIO_L_ENABLE_CONFIG_03_0_SCRREG                        GPIO_L_SCR_03_0
+#define GPIO_L_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_L_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_L_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_L_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_L_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_L_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x13264)
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_L_SCR_03_0
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_L_SCR_03_0
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_L_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INPUT_03_0
+#define GPIO_L_INPUT_03_0                       MK_ADDR_CONST(0x13268)
+#define GPIO_L_INPUT_03_0_SECURE                        0x0
+#define GPIO_L_INPUT_03_0_DUAL                  0x0
+#define GPIO_L_INPUT_03_0_SCR                   GPIO_L_SCR_03_0
+#define GPIO_L_INPUT_03_0_SCRREG                        GPIO_L_SCR_03_0
+#define GPIO_L_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_L_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_L_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_L_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_L_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_L_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_L_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_L_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_L_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_L_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_L_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_OUTPUT_CONTROL_03_0
+#define GPIO_L_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1326c)
+#define GPIO_L_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_L_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_L_OUTPUT_CONTROL_03_0_SCR                  GPIO_L_SCR_03_0
+#define GPIO_L_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_L_SCR_03_0
+#define GPIO_L_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_L_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_L_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_L_OUTPUT_VALUE_03_0
+#define GPIO_L_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x13270)
+#define GPIO_L_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_L_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_L_OUTPUT_VALUE_03_0_SCR                    GPIO_L_SCR_03_0
+#define GPIO_L_OUTPUT_VALUE_03_0_SCRREG                         GPIO_L_SCR_03_0
+#define GPIO_L_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_L_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_L_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INTERRUPT_CLEAR_03_0
+#define GPIO_L_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x13274)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_L_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_L_INTERRUPT_CLEAR_03_0_SCR                         GPIO_L_SCR_03_0
+#define GPIO_L_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_L_SCR_03_0
+#define GPIO_L_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_L_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_L_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13278
+
+// Reserved address 0x1327c
+
+// Reserved address 0x13280
+
+// Reserved address 0x13284
+
+// Reserved address 0x13288
+
+// Reserved address 0x1328c
+
+// Reserved address 0x13290
+
+// Reserved address 0x13294
+
+// Reserved address 0x13298
+
+// Reserved address 0x1329c
+
+// Reserved address 0x132a0
+
+// Reserved address 0x132a4
+
+// Reserved address 0x132a8
+
+// Reserved address 0x132ac
+
+// Reserved address 0x132b0
+
+// Reserved address 0x132b4
+
+// Reserved address 0x132b8
+
+// Reserved address 0x132bc
+
+// Reserved address 0x132c0
+
+// Reserved address 0x132c4
+
+// Reserved address 0x132c8
+
+// Reserved address 0x132cc
+
+// Reserved address 0x132d0
+
+// Reserved address 0x132d4
+
+// Reserved address 0x132d8
+
+// Reserved address 0x132dc
+
+// Reserved address 0x132e0
+
+// Reserved address 0x132e4
+
+// Reserved address 0x132e8
+
+// Reserved address 0x132ec
+
+// Reserved address 0x132f0
+
+// Reserved address 0x132f4
+
+// Reserved address 0x132f8
+
+// Reserved address 0x132fc
+
+// Register GPIO_L_INTERRUPT_STATUS_G0_0
+#define GPIO_L_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x13300)
+#define GPIO_L_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_L_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_L_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_L_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_L_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_L_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
+#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INTERRUPT_STATUS_G1_0
+#define GPIO_L_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x13304)
+#define GPIO_L_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_L_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_L_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_L_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_L_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_L_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
+#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INTERRUPT_STATUS_G2_0
+#define GPIO_L_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x13308)
+#define GPIO_L_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_L_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_L_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_L_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_L_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_L_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
+#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INTERRUPT_STATUS_G3_0
+#define GPIO_L_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1330c)
+#define GPIO_L_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_L_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_L_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_L_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_L_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_L_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
+#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INTERRUPT_STATUS_G4_0
+#define GPIO_L_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x13310)
+#define GPIO_L_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_L_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_L_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_L_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_L_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_L_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
+#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INTERRUPT_STATUS_G5_0
+#define GPIO_L_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x13314)
+#define GPIO_L_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_L_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_L_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_L_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_L_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_L_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
+#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INTERRUPT_STATUS_G6_0
+#define GPIO_L_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x13318)
+#define GPIO_L_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_L_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_L_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_L_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_L_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_L_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
+#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_L_INTERRUPT_STATUS_G7_0
+#define GPIO_L_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1331c)
+#define GPIO_L_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_L_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_L_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_L_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_L_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_L_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
+#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_L_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x13320
+
+// Reserved address 0x13324
+
+// Reserved address 0x13328
+
+// Reserved address 0x1332c
+
+// Reserved address 0x13330
+
+// Reserved address 0x13334
+
+// Reserved address 0x13338
+
+// Reserved address 0x1333c
+
+// Reserved address 0x13340
+
+// Reserved address 0x13344
+
+// Reserved address 0x13348
+
+// Reserved address 0x1334c
+
+// Reserved address 0x13350
+
+// Reserved address 0x13354
+
+// Reserved address 0x13358
+
+// Reserved address 0x1335c
+
+// Reserved address 0x13360
+
+// Reserved address 0x13364
+
+// Reserved address 0x13368
+
+// Reserved address 0x1336c
+
+// Reserved address 0x13370
+
+// Reserved address 0x13374
+
+// Reserved address 0x13378
+
+// Reserved address 0x1337c
+
+// Reserved address 0x13380
+
+// Reserved address 0x13384
+
+// Reserved address 0x13388
+
+// Reserved address 0x1338c
+
+// Reserved address 0x13390
+
+// Reserved address 0x13394
+
+// Reserved address 0x13398
+
+// Reserved address 0x1339c
+
+// Reserved address 0x133a0
+
+// Reserved address 0x133a4
+
+// Reserved address 0x133a8
+
+// Reserved address 0x133ac
+
+// Reserved address 0x133b0
+
+// Reserved address 0x133b4
+
+// Reserved address 0x133b8
+
+// Reserved address 0x133bc
+
+// Reserved address 0x133c0
+
+// Reserved address 0x133c4
+
+// Reserved address 0x133c8
+
+// Reserved address 0x133cc
+
+// Reserved address 0x133d0
+
+// Reserved address 0x133d4
+
+// Reserved address 0x133d8
+
+// Reserved address 0x133dc
+
+// Reserved address 0x133e0
+
+// Reserved address 0x133e4
+
+// Reserved address 0x133e8
+
+// Reserved address 0x133ec
+
+// Reserved address 0x133f0
+
+// Reserved address 0x133f4
+
+// Reserved address 0x133f8
+
+// Reserved address 0x133fc
+
+// Register GPIO_AG_ENABLE_CONFIG_00_0
+#define GPIO_AG_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x13400)
+#define GPIO_AG_ENABLE_CONFIG_00_0_SECURE                       0x0
+#define GPIO_AG_ENABLE_CONFIG_00_0_DUAL                         0x0
+#define GPIO_AG_ENABLE_CONFIG_00_0_SCR                  GPIO_AG_SCR_00_0
+#define GPIO_AG_ENABLE_CONFIG_00_0_SCRREG                       GPIO_AG_SCR_00_0
+#define GPIO_AG_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
+#define GPIO_AG_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
+#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AG_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x13404)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_AG_SCR_00_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_AG_SCR_00_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INPUT_00_0
+#define GPIO_AG_INPUT_00_0                      MK_ADDR_CONST(0x13408)
+#define GPIO_AG_INPUT_00_0_SECURE                       0x0
+#define GPIO_AG_INPUT_00_0_DUAL                         0x0
+#define GPIO_AG_INPUT_00_0_SCR                  GPIO_AG_SCR_00_0
+#define GPIO_AG_INPUT_00_0_SCRREG                       GPIO_AG_SCR_00_0
+#define GPIO_AG_INPUT_00_0_WORD_COUNT                   0x1
+#define GPIO_AG_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AG_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_AG_INPUT_00_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AG_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AG_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_OUTPUT_CONTROL_00_0
+#define GPIO_AG_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x1340c)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_SECURE                      0x0
+#define GPIO_AG_OUTPUT_CONTROL_00_0_DUAL                        0x0
+#define GPIO_AG_OUTPUT_CONTROL_00_0_SCR                         GPIO_AG_SCR_00_0
+#define GPIO_AG_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_AG_SCR_00_0
+#define GPIO_AG_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
+#define GPIO_AG_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AG_OUTPUT_VALUE_00_0
+#define GPIO_AG_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x13410)
+#define GPIO_AG_OUTPUT_VALUE_00_0_SECURE                        0x0
+#define GPIO_AG_OUTPUT_VALUE_00_0_DUAL                  0x0
+#define GPIO_AG_OUTPUT_VALUE_00_0_SCR                   GPIO_AG_SCR_00_0
+#define GPIO_AG_OUTPUT_VALUE_00_0_SCRREG                        GPIO_AG_SCR_00_0
+#define GPIO_AG_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
+#define GPIO_AG_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INTERRUPT_CLEAR_00_0
+#define GPIO_AG_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x13414)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_SECURE                     0x0
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_DUAL                       0x0
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_SCR                        GPIO_AG_SCR_00_0
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_AG_SCR_00_0
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13418
+
+// Reserved address 0x1341c
+
+// Register GPIO_AG_ENABLE_CONFIG_01_0
+#define GPIO_AG_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x13420)
+#define GPIO_AG_ENABLE_CONFIG_01_0_SECURE                       0x0
+#define GPIO_AG_ENABLE_CONFIG_01_0_DUAL                         0x0
+#define GPIO_AG_ENABLE_CONFIG_01_0_SCR                  GPIO_AG_SCR_01_0
+#define GPIO_AG_ENABLE_CONFIG_01_0_SCRREG                       GPIO_AG_SCR_01_0
+#define GPIO_AG_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
+#define GPIO_AG_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
+#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AG_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x13424)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_AG_SCR_01_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_AG_SCR_01_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INPUT_01_0
+#define GPIO_AG_INPUT_01_0                      MK_ADDR_CONST(0x13428)
+#define GPIO_AG_INPUT_01_0_SECURE                       0x0
+#define GPIO_AG_INPUT_01_0_DUAL                         0x0
+#define GPIO_AG_INPUT_01_0_SCR                  GPIO_AG_SCR_01_0
+#define GPIO_AG_INPUT_01_0_SCRREG                       GPIO_AG_SCR_01_0
+#define GPIO_AG_INPUT_01_0_WORD_COUNT                   0x1
+#define GPIO_AG_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AG_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_AG_INPUT_01_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AG_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AG_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_OUTPUT_CONTROL_01_0
+#define GPIO_AG_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x1342c)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_SECURE                      0x0
+#define GPIO_AG_OUTPUT_CONTROL_01_0_DUAL                        0x0
+#define GPIO_AG_OUTPUT_CONTROL_01_0_SCR                         GPIO_AG_SCR_01_0
+#define GPIO_AG_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_AG_SCR_01_0
+#define GPIO_AG_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
+#define GPIO_AG_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AG_OUTPUT_VALUE_01_0
+#define GPIO_AG_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x13430)
+#define GPIO_AG_OUTPUT_VALUE_01_0_SECURE                        0x0
+#define GPIO_AG_OUTPUT_VALUE_01_0_DUAL                  0x0
+#define GPIO_AG_OUTPUT_VALUE_01_0_SCR                   GPIO_AG_SCR_01_0
+#define GPIO_AG_OUTPUT_VALUE_01_0_SCRREG                        GPIO_AG_SCR_01_0
+#define GPIO_AG_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
+#define GPIO_AG_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INTERRUPT_CLEAR_01_0
+#define GPIO_AG_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x13434)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_SECURE                     0x0
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_DUAL                       0x0
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_SCR                        GPIO_AG_SCR_01_0
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_AG_SCR_01_0
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13438
+
+// Reserved address 0x1343c
+
+// Register GPIO_AG_ENABLE_CONFIG_02_0
+#define GPIO_AG_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x13440)
+#define GPIO_AG_ENABLE_CONFIG_02_0_SECURE                       0x0
+#define GPIO_AG_ENABLE_CONFIG_02_0_DUAL                         0x0
+#define GPIO_AG_ENABLE_CONFIG_02_0_SCR                  GPIO_AG_SCR_02_0
+#define GPIO_AG_ENABLE_CONFIG_02_0_SCRREG                       GPIO_AG_SCR_02_0
+#define GPIO_AG_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
+#define GPIO_AG_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
+#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AG_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x13444)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_AG_SCR_02_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_AG_SCR_02_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INPUT_02_0
+#define GPIO_AG_INPUT_02_0                      MK_ADDR_CONST(0x13448)
+#define GPIO_AG_INPUT_02_0_SECURE                       0x0
+#define GPIO_AG_INPUT_02_0_DUAL                         0x0
+#define GPIO_AG_INPUT_02_0_SCR                  GPIO_AG_SCR_02_0
+#define GPIO_AG_INPUT_02_0_SCRREG                       GPIO_AG_SCR_02_0
+#define GPIO_AG_INPUT_02_0_WORD_COUNT                   0x1
+#define GPIO_AG_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AG_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_AG_INPUT_02_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AG_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AG_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_OUTPUT_CONTROL_02_0
+#define GPIO_AG_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x1344c)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_SECURE                      0x0
+#define GPIO_AG_OUTPUT_CONTROL_02_0_DUAL                        0x0
+#define GPIO_AG_OUTPUT_CONTROL_02_0_SCR                         GPIO_AG_SCR_02_0
+#define GPIO_AG_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_AG_SCR_02_0
+#define GPIO_AG_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
+#define GPIO_AG_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AG_OUTPUT_VALUE_02_0
+#define GPIO_AG_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x13450)
+#define GPIO_AG_OUTPUT_VALUE_02_0_SECURE                        0x0
+#define GPIO_AG_OUTPUT_VALUE_02_0_DUAL                  0x0
+#define GPIO_AG_OUTPUT_VALUE_02_0_SCR                   GPIO_AG_SCR_02_0
+#define GPIO_AG_OUTPUT_VALUE_02_0_SCRREG                        GPIO_AG_SCR_02_0
+#define GPIO_AG_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
+#define GPIO_AG_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INTERRUPT_CLEAR_02_0
+#define GPIO_AG_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x13454)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_SECURE                     0x0
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_DUAL                       0x0
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_SCR                        GPIO_AG_SCR_02_0
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_AG_SCR_02_0
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13458
+
+// Reserved address 0x1345c
+
+// Register GPIO_AG_ENABLE_CONFIG_03_0
+#define GPIO_AG_ENABLE_CONFIG_03_0                      MK_ADDR_CONST(0x13460)
+#define GPIO_AG_ENABLE_CONFIG_03_0_SECURE                       0x0
+#define GPIO_AG_ENABLE_CONFIG_03_0_DUAL                         0x0
+#define GPIO_AG_ENABLE_CONFIG_03_0_SCR                  GPIO_AG_SCR_03_0
+#define GPIO_AG_ENABLE_CONFIG_03_0_SCRREG                       GPIO_AG_SCR_03_0
+#define GPIO_AG_ENABLE_CONFIG_03_0_WORD_COUNT                   0x1
+#define GPIO_AG_ENABLE_CONFIG_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_03_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_RANGE                 1:1
+#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AG_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0                 MK_ADDR_CONST(0x13464)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_SECURE                  0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DUAL                    0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_SCR                     GPIO_AG_SCR_03_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_SCRREG                  GPIO_AG_SCR_03_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                      0x1
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INPUT_03_0
+#define GPIO_AG_INPUT_03_0                      MK_ADDR_CONST(0x13468)
+#define GPIO_AG_INPUT_03_0_SECURE                       0x0
+#define GPIO_AG_INPUT_03_0_DUAL                         0x0
+#define GPIO_AG_INPUT_03_0_SCR                  GPIO_AG_SCR_03_0
+#define GPIO_AG_INPUT_03_0_SCRREG                       GPIO_AG_SCR_03_0
+#define GPIO_AG_INPUT_03_0_WORD_COUNT                   0x1
+#define GPIO_AG_INPUT_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_03_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_INPUT_03_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_03_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_03_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AG_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_AG_INPUT_03_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AG_INPUT_03_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_03_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_03_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AG_INPUT_03_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_03_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_03_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_OUTPUT_CONTROL_03_0
+#define GPIO_AG_OUTPUT_CONTROL_03_0                     MK_ADDR_CONST(0x1346c)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_SECURE                      0x0
+#define GPIO_AG_OUTPUT_CONTROL_03_0_DUAL                        0x0
+#define GPIO_AG_OUTPUT_CONTROL_03_0_SCR                         GPIO_AG_SCR_03_0
+#define GPIO_AG_OUTPUT_CONTROL_03_0_SCRREG                      GPIO_AG_SCR_03_0
+#define GPIO_AG_OUTPUT_CONTROL_03_0_WORD_COUNT                  0x1
+#define GPIO_AG_OUTPUT_CONTROL_03_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AG_OUTPUT_VALUE_03_0
+#define GPIO_AG_OUTPUT_VALUE_03_0                       MK_ADDR_CONST(0x13470)
+#define GPIO_AG_OUTPUT_VALUE_03_0_SECURE                        0x0
+#define GPIO_AG_OUTPUT_VALUE_03_0_DUAL                  0x0
+#define GPIO_AG_OUTPUT_VALUE_03_0_SCR                   GPIO_AG_SCR_03_0
+#define GPIO_AG_OUTPUT_VALUE_03_0_SCRREG                        GPIO_AG_SCR_03_0
+#define GPIO_AG_OUTPUT_VALUE_03_0_WORD_COUNT                    0x1
+#define GPIO_AG_OUTPUT_VALUE_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_03_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_03_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INTERRUPT_CLEAR_03_0
+#define GPIO_AG_INTERRUPT_CLEAR_03_0                    MK_ADDR_CONST(0x13474)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_SECURE                     0x0
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_DUAL                       0x0
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_SCR                        GPIO_AG_SCR_03_0
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_SCRREG                     GPIO_AG_SCR_03_0
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_WORD_COUNT                         0x1
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13478
+
+// Reserved address 0x1347c
+
+// Register GPIO_AG_ENABLE_CONFIG_04_0
+#define GPIO_AG_ENABLE_CONFIG_04_0                      MK_ADDR_CONST(0x13480)
+#define GPIO_AG_ENABLE_CONFIG_04_0_SECURE                       0x0
+#define GPIO_AG_ENABLE_CONFIG_04_0_DUAL                         0x0
+#define GPIO_AG_ENABLE_CONFIG_04_0_SCR                  GPIO_AG_SCR_04_0
+#define GPIO_AG_ENABLE_CONFIG_04_0_SCRREG                       GPIO_AG_SCR_04_0
+#define GPIO_AG_ENABLE_CONFIG_04_0_WORD_COUNT                   0x1
+#define GPIO_AG_ENABLE_CONFIG_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_04_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_RANGE                 1:1
+#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AG_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0                 MK_ADDR_CONST(0x13484)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_SECURE                  0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DUAL                    0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_SCR                     GPIO_AG_SCR_04_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_SCRREG                  GPIO_AG_SCR_04_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                      0x1
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INPUT_04_0
+#define GPIO_AG_INPUT_04_0                      MK_ADDR_CONST(0x13488)
+#define GPIO_AG_INPUT_04_0_SECURE                       0x0
+#define GPIO_AG_INPUT_04_0_DUAL                         0x0
+#define GPIO_AG_INPUT_04_0_SCR                  GPIO_AG_SCR_04_0
+#define GPIO_AG_INPUT_04_0_SCRREG                       GPIO_AG_SCR_04_0
+#define GPIO_AG_INPUT_04_0_WORD_COUNT                   0x1
+#define GPIO_AG_INPUT_04_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_04_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_INPUT_04_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_04_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_04_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AG_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_AG_INPUT_04_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AG_INPUT_04_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_04_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_04_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AG_INPUT_04_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_04_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_04_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_OUTPUT_CONTROL_04_0
+#define GPIO_AG_OUTPUT_CONTROL_04_0                     MK_ADDR_CONST(0x1348c)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_SECURE                      0x0
+#define GPIO_AG_OUTPUT_CONTROL_04_0_DUAL                        0x0
+#define GPIO_AG_OUTPUT_CONTROL_04_0_SCR                         GPIO_AG_SCR_04_0
+#define GPIO_AG_OUTPUT_CONTROL_04_0_SCRREG                      GPIO_AG_SCR_04_0
+#define GPIO_AG_OUTPUT_CONTROL_04_0_WORD_COUNT                  0x1
+#define GPIO_AG_OUTPUT_CONTROL_04_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AG_OUTPUT_VALUE_04_0
+#define GPIO_AG_OUTPUT_VALUE_04_0                       MK_ADDR_CONST(0x13490)
+#define GPIO_AG_OUTPUT_VALUE_04_0_SECURE                        0x0
+#define GPIO_AG_OUTPUT_VALUE_04_0_DUAL                  0x0
+#define GPIO_AG_OUTPUT_VALUE_04_0_SCR                   GPIO_AG_SCR_04_0
+#define GPIO_AG_OUTPUT_VALUE_04_0_SCRREG                        GPIO_AG_SCR_04_0
+#define GPIO_AG_OUTPUT_VALUE_04_0_WORD_COUNT                    0x1
+#define GPIO_AG_OUTPUT_VALUE_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_04_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_04_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INTERRUPT_CLEAR_04_0
+#define GPIO_AG_INTERRUPT_CLEAR_04_0                    MK_ADDR_CONST(0x13494)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_SECURE                     0x0
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_DUAL                       0x0
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_SCR                        GPIO_AG_SCR_04_0
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_SCRREG                     GPIO_AG_SCR_04_0
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_WORD_COUNT                         0x1
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13498
+
+// Reserved address 0x1349c
+
+// Register GPIO_AG_ENABLE_CONFIG_05_0
+#define GPIO_AG_ENABLE_CONFIG_05_0                      MK_ADDR_CONST(0x134a0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_SECURE                       0x0
+#define GPIO_AG_ENABLE_CONFIG_05_0_DUAL                         0x0
+#define GPIO_AG_ENABLE_CONFIG_05_0_SCR                  GPIO_AG_SCR_05_0
+#define GPIO_AG_ENABLE_CONFIG_05_0_SCRREG                       GPIO_AG_SCR_05_0
+#define GPIO_AG_ENABLE_CONFIG_05_0_WORD_COUNT                   0x1
+#define GPIO_AG_ENABLE_CONFIG_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_05_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_RANGE                 1:1
+#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AG_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0                 MK_ADDR_CONST(0x134a4)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_SECURE                  0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DUAL                    0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_SCR                     GPIO_AG_SCR_05_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_SCRREG                  GPIO_AG_SCR_05_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                      0x1
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INPUT_05_0
+#define GPIO_AG_INPUT_05_0                      MK_ADDR_CONST(0x134a8)
+#define GPIO_AG_INPUT_05_0_SECURE                       0x0
+#define GPIO_AG_INPUT_05_0_DUAL                         0x0
+#define GPIO_AG_INPUT_05_0_SCR                  GPIO_AG_SCR_05_0
+#define GPIO_AG_INPUT_05_0_SCRREG                       GPIO_AG_SCR_05_0
+#define GPIO_AG_INPUT_05_0_WORD_COUNT                   0x1
+#define GPIO_AG_INPUT_05_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_05_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_INPUT_05_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_05_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_05_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AG_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_AG_INPUT_05_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AG_INPUT_05_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_05_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_05_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AG_INPUT_05_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_05_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_05_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_OUTPUT_CONTROL_05_0
+#define GPIO_AG_OUTPUT_CONTROL_05_0                     MK_ADDR_CONST(0x134ac)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_SECURE                      0x0
+#define GPIO_AG_OUTPUT_CONTROL_05_0_DUAL                        0x0
+#define GPIO_AG_OUTPUT_CONTROL_05_0_SCR                         GPIO_AG_SCR_05_0
+#define GPIO_AG_OUTPUT_CONTROL_05_0_SCRREG                      GPIO_AG_SCR_05_0
+#define GPIO_AG_OUTPUT_CONTROL_05_0_WORD_COUNT                  0x1
+#define GPIO_AG_OUTPUT_CONTROL_05_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AG_OUTPUT_VALUE_05_0
+#define GPIO_AG_OUTPUT_VALUE_05_0                       MK_ADDR_CONST(0x134b0)
+#define GPIO_AG_OUTPUT_VALUE_05_0_SECURE                        0x0
+#define GPIO_AG_OUTPUT_VALUE_05_0_DUAL                  0x0
+#define GPIO_AG_OUTPUT_VALUE_05_0_SCR                   GPIO_AG_SCR_05_0
+#define GPIO_AG_OUTPUT_VALUE_05_0_SCRREG                        GPIO_AG_SCR_05_0
+#define GPIO_AG_OUTPUT_VALUE_05_0_WORD_COUNT                    0x1
+#define GPIO_AG_OUTPUT_VALUE_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_05_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_05_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INTERRUPT_CLEAR_05_0
+#define GPIO_AG_INTERRUPT_CLEAR_05_0                    MK_ADDR_CONST(0x134b4)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_SECURE                     0x0
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_DUAL                       0x0
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_SCR                        GPIO_AG_SCR_05_0
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_SCRREG                     GPIO_AG_SCR_05_0
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_WORD_COUNT                         0x1
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x134b8
+
+// Reserved address 0x134bc
+
+// Register GPIO_AG_ENABLE_CONFIG_06_0
+#define GPIO_AG_ENABLE_CONFIG_06_0                      MK_ADDR_CONST(0x134c0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_SECURE                       0x0
+#define GPIO_AG_ENABLE_CONFIG_06_0_DUAL                         0x0
+#define GPIO_AG_ENABLE_CONFIG_06_0_SCR                  GPIO_AG_SCR_06_0
+#define GPIO_AG_ENABLE_CONFIG_06_0_SCRREG                       GPIO_AG_SCR_06_0
+#define GPIO_AG_ENABLE_CONFIG_06_0_WORD_COUNT                   0x1
+#define GPIO_AG_ENABLE_CONFIG_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_06_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_RANGE                 1:1
+#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AG_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0                 MK_ADDR_CONST(0x134c4)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_SECURE                  0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DUAL                    0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_SCR                     GPIO_AG_SCR_06_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_SCRREG                  GPIO_AG_SCR_06_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                      0x1
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INPUT_06_0
+#define GPIO_AG_INPUT_06_0                      MK_ADDR_CONST(0x134c8)
+#define GPIO_AG_INPUT_06_0_SECURE                       0x0
+#define GPIO_AG_INPUT_06_0_DUAL                         0x0
+#define GPIO_AG_INPUT_06_0_SCR                  GPIO_AG_SCR_06_0
+#define GPIO_AG_INPUT_06_0_SCRREG                       GPIO_AG_SCR_06_0
+#define GPIO_AG_INPUT_06_0_WORD_COUNT                   0x1
+#define GPIO_AG_INPUT_06_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_06_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_INPUT_06_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_06_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_06_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AG_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_AG_INPUT_06_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AG_INPUT_06_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_06_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_06_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AG_INPUT_06_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_06_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_06_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_OUTPUT_CONTROL_06_0
+#define GPIO_AG_OUTPUT_CONTROL_06_0                     MK_ADDR_CONST(0x134cc)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_SECURE                      0x0
+#define GPIO_AG_OUTPUT_CONTROL_06_0_DUAL                        0x0
+#define GPIO_AG_OUTPUT_CONTROL_06_0_SCR                         GPIO_AG_SCR_06_0
+#define GPIO_AG_OUTPUT_CONTROL_06_0_SCRREG                      GPIO_AG_SCR_06_0
+#define GPIO_AG_OUTPUT_CONTROL_06_0_WORD_COUNT                  0x1
+#define GPIO_AG_OUTPUT_CONTROL_06_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AG_OUTPUT_VALUE_06_0
+#define GPIO_AG_OUTPUT_VALUE_06_0                       MK_ADDR_CONST(0x134d0)
+#define GPIO_AG_OUTPUT_VALUE_06_0_SECURE                        0x0
+#define GPIO_AG_OUTPUT_VALUE_06_0_DUAL                  0x0
+#define GPIO_AG_OUTPUT_VALUE_06_0_SCR                   GPIO_AG_SCR_06_0
+#define GPIO_AG_OUTPUT_VALUE_06_0_SCRREG                        GPIO_AG_SCR_06_0
+#define GPIO_AG_OUTPUT_VALUE_06_0_WORD_COUNT                    0x1
+#define GPIO_AG_OUTPUT_VALUE_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_06_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_06_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INTERRUPT_CLEAR_06_0
+#define GPIO_AG_INTERRUPT_CLEAR_06_0                    MK_ADDR_CONST(0x134d4)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_SECURE                     0x0
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_DUAL                       0x0
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_SCR                        GPIO_AG_SCR_06_0
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_SCRREG                     GPIO_AG_SCR_06_0
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_WORD_COUNT                         0x1
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x134d8
+
+// Reserved address 0x134dc
+
+// Register GPIO_AG_ENABLE_CONFIG_07_0
+#define GPIO_AG_ENABLE_CONFIG_07_0                      MK_ADDR_CONST(0x134e0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_SECURE                       0x0
+#define GPIO_AG_ENABLE_CONFIG_07_0_DUAL                         0x0
+#define GPIO_AG_ENABLE_CONFIG_07_0_SCR                  GPIO_AG_SCR_07_0
+#define GPIO_AG_ENABLE_CONFIG_07_0_SCRREG                       GPIO_AG_SCR_07_0
+#define GPIO_AG_ENABLE_CONFIG_07_0_WORD_COUNT                   0x1
+#define GPIO_AG_ENABLE_CONFIG_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_07_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_RANGE                 1:1
+#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AG_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AG_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0                 MK_ADDR_CONST(0x134e4)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_SECURE                  0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DUAL                    0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_SCR                     GPIO_AG_SCR_07_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_SCRREG                  GPIO_AG_SCR_07_0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                      0x1
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AG_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INPUT_07_0
+#define GPIO_AG_INPUT_07_0                      MK_ADDR_CONST(0x134e8)
+#define GPIO_AG_INPUT_07_0_SECURE                       0x0
+#define GPIO_AG_INPUT_07_0_DUAL                         0x0
+#define GPIO_AG_INPUT_07_0_SCR                  GPIO_AG_SCR_07_0
+#define GPIO_AG_INPUT_07_0_SCRREG                       GPIO_AG_SCR_07_0
+#define GPIO_AG_INPUT_07_0_WORD_COUNT                   0x1
+#define GPIO_AG_INPUT_07_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_07_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_INPUT_07_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_07_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_07_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AG_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_AG_INPUT_07_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AG_INPUT_07_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_07_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AG_INPUT_07_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AG_INPUT_07_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_07_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_07_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_OUTPUT_CONTROL_07_0
+#define GPIO_AG_OUTPUT_CONTROL_07_0                     MK_ADDR_CONST(0x134ec)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_SECURE                      0x0
+#define GPIO_AG_OUTPUT_CONTROL_07_0_DUAL                        0x0
+#define GPIO_AG_OUTPUT_CONTROL_07_0_SCR                         GPIO_AG_SCR_07_0
+#define GPIO_AG_OUTPUT_CONTROL_07_0_SCRREG                      GPIO_AG_SCR_07_0
+#define GPIO_AG_OUTPUT_CONTROL_07_0_WORD_COUNT                  0x1
+#define GPIO_AG_OUTPUT_CONTROL_07_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AG_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AG_OUTPUT_VALUE_07_0
+#define GPIO_AG_OUTPUT_VALUE_07_0                       MK_ADDR_CONST(0x134f0)
+#define GPIO_AG_OUTPUT_VALUE_07_0_SECURE                        0x0
+#define GPIO_AG_OUTPUT_VALUE_07_0_DUAL                  0x0
+#define GPIO_AG_OUTPUT_VALUE_07_0_SCR                   GPIO_AG_SCR_07_0
+#define GPIO_AG_OUTPUT_VALUE_07_0_SCRREG                        GPIO_AG_SCR_07_0
+#define GPIO_AG_OUTPUT_VALUE_07_0_WORD_COUNT                    0x1
+#define GPIO_AG_OUTPUT_VALUE_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_07_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_07_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AG_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INTERRUPT_CLEAR_07_0
+#define GPIO_AG_INTERRUPT_CLEAR_07_0                    MK_ADDR_CONST(0x134f4)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_SECURE                     0x0
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_DUAL                       0x0
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_SCR                        GPIO_AG_SCR_07_0
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_SCRREG                     GPIO_AG_SCR_07_0
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_WORD_COUNT                         0x1
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AG_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x134f8
+
+// Reserved address 0x134fc
+
+// Register GPIO_AG_INTERRUPT_STATUS_G0_0
+#define GPIO_AG_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x13500)
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_SECURE                    0x0
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_DUAL                      0x0
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_SCR                       0
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_SCRREG                    0
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INTERRUPT_STATUS_G1_0
+#define GPIO_AG_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x13504)
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_SECURE                    0x0
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_DUAL                      0x0
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_SCR                       0
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_SCRREG                    0
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INTERRUPT_STATUS_G2_0
+#define GPIO_AG_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x13508)
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_SECURE                    0x0
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_DUAL                      0x0
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_SCR                       0
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_SCRREG                    0
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INTERRUPT_STATUS_G3_0
+#define GPIO_AG_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x1350c)
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_SECURE                    0x0
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_DUAL                      0x0
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_SCR                       0
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_SCRREG                    0
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INTERRUPT_STATUS_G4_0
+#define GPIO_AG_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x13510)
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_SECURE                    0x0
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_DUAL                      0x0
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_SCR                       0
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_SCRREG                    0
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INTERRUPT_STATUS_G5_0
+#define GPIO_AG_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x13514)
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_SECURE                    0x0
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_DUAL                      0x0
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_SCR                       0
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_SCRREG                    0
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INTERRUPT_STATUS_G6_0
+#define GPIO_AG_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x13518)
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_SECURE                    0x0
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_DUAL                      0x0
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_SCR                       0
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_SCRREG                    0
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AG_INTERRUPT_STATUS_G7_0
+#define GPIO_AG_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x1351c)
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_SECURE                    0x0
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_DUAL                      0x0
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_SCR                       0
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_SCRREG                    0
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xff, GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       7:0
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(7)
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AG_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x13520
+
+// Reserved address 0x13524
+
+// Reserved address 0x13528
+
+// Reserved address 0x1352c
+
+// Reserved address 0x13530
+
+// Reserved address 0x13534
+
+// Reserved address 0x13538
+
+// Reserved address 0x1353c
+
+// Reserved address 0x13540
+
+// Reserved address 0x13544
+
+// Reserved address 0x13548
+
+// Reserved address 0x1354c
+
+// Reserved address 0x13550
+
+// Reserved address 0x13554
+
+// Reserved address 0x13558
+
+// Reserved address 0x1355c
+
+// Reserved address 0x13560
+
+// Reserved address 0x13564
+
+// Reserved address 0x13568
+
+// Reserved address 0x1356c
+
+// Reserved address 0x13570
+
+// Reserved address 0x13574
+
+// Reserved address 0x13578
+
+// Reserved address 0x1357c
+
+// Reserved address 0x13580
+
+// Reserved address 0x13584
+
+// Reserved address 0x13588
+
+// Reserved address 0x1358c
+
+// Reserved address 0x13590
+
+// Reserved address 0x13594
+
+// Reserved address 0x13598
+
+// Reserved address 0x1359c
+
+// Reserved address 0x135a0
+
+// Reserved address 0x135a4
+
+// Reserved address 0x135a8
+
+// Reserved address 0x135ac
+
+// Reserved address 0x135b0
+
+// Reserved address 0x135b4
+
+// Reserved address 0x135b8
+
+// Reserved address 0x135bc
+
+// Reserved address 0x135c0
+
+// Reserved address 0x135c4
+
+// Reserved address 0x135c8
+
+// Reserved address 0x135cc
+
+// Reserved address 0x135d0
+
+// Reserved address 0x135d4
+
+// Reserved address 0x135d8
+
+// Reserved address 0x135dc
+
+// Reserved address 0x135e0
+
+// Reserved address 0x135e4
+
+// Reserved address 0x135e8
+
+// Reserved address 0x135ec
+
+// Reserved address 0x135f0
+
+// Reserved address 0x135f4
+
+// Reserved address 0x135f8
+
+// Reserved address 0x135fc
+
+// Register GPIO_AE_ENABLE_CONFIG_00_0
+#define GPIO_AE_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x13600)
+#define GPIO_AE_ENABLE_CONFIG_00_0_SECURE                       0x0
+#define GPIO_AE_ENABLE_CONFIG_00_0_DUAL                         0x0
+#define GPIO_AE_ENABLE_CONFIG_00_0_SCR                  GPIO_AE_SCR_00_0
+#define GPIO_AE_ENABLE_CONFIG_00_0_SCRREG                       GPIO_AE_SCR_00_0
+#define GPIO_AE_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
+#define GPIO_AE_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AE_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AE_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
+#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AE_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x13604)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_AE_SCR_00_0
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_AE_SCR_00_0
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INPUT_00_0
+#define GPIO_AE_INPUT_00_0                      MK_ADDR_CONST(0x13608)
+#define GPIO_AE_INPUT_00_0_SECURE                       0x0
+#define GPIO_AE_INPUT_00_0_DUAL                         0x0
+#define GPIO_AE_INPUT_00_0_SCR                  GPIO_AE_SCR_00_0
+#define GPIO_AE_INPUT_00_0_SCRREG                       GPIO_AE_SCR_00_0
+#define GPIO_AE_INPUT_00_0_WORD_COUNT                   0x1
+#define GPIO_AE_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AE_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AE_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AE_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_AE_INPUT_00_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AE_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AE_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AE_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AE_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_OUTPUT_CONTROL_00_0
+#define GPIO_AE_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x1360c)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_SECURE                      0x0
+#define GPIO_AE_OUTPUT_CONTROL_00_0_DUAL                        0x0
+#define GPIO_AE_OUTPUT_CONTROL_00_0_SCR                         GPIO_AE_SCR_00_0
+#define GPIO_AE_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_AE_SCR_00_0
+#define GPIO_AE_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
+#define GPIO_AE_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AE_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AE_OUTPUT_VALUE_00_0
+#define GPIO_AE_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x13610)
+#define GPIO_AE_OUTPUT_VALUE_00_0_SECURE                        0x0
+#define GPIO_AE_OUTPUT_VALUE_00_0_DUAL                  0x0
+#define GPIO_AE_OUTPUT_VALUE_00_0_SCR                   GPIO_AE_SCR_00_0
+#define GPIO_AE_OUTPUT_VALUE_00_0_SCRREG                        GPIO_AE_SCR_00_0
+#define GPIO_AE_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
+#define GPIO_AE_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INTERRUPT_CLEAR_00_0
+#define GPIO_AE_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x13614)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_SECURE                     0x0
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_DUAL                       0x0
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_SCR                        GPIO_AE_SCR_00_0
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_AE_SCR_00_0
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AE_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13618
+
+// Reserved address 0x1361c
+
+// Register GPIO_AE_ENABLE_CONFIG_01_0
+#define GPIO_AE_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x13620)
+#define GPIO_AE_ENABLE_CONFIG_01_0_SECURE                       0x0
+#define GPIO_AE_ENABLE_CONFIG_01_0_DUAL                         0x0
+#define GPIO_AE_ENABLE_CONFIG_01_0_SCR                  GPIO_AE_SCR_01_0
+#define GPIO_AE_ENABLE_CONFIG_01_0_SCRREG                       GPIO_AE_SCR_01_0
+#define GPIO_AE_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
+#define GPIO_AE_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AE_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AE_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
+#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AE_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AE_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x13624)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_AE_SCR_01_0
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_AE_SCR_01_0
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AE_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INPUT_01_0
+#define GPIO_AE_INPUT_01_0                      MK_ADDR_CONST(0x13628)
+#define GPIO_AE_INPUT_01_0_SECURE                       0x0
+#define GPIO_AE_INPUT_01_0_DUAL                         0x0
+#define GPIO_AE_INPUT_01_0_SCR                  GPIO_AE_SCR_01_0
+#define GPIO_AE_INPUT_01_0_SCRREG                       GPIO_AE_SCR_01_0
+#define GPIO_AE_INPUT_01_0_WORD_COUNT                   0x1
+#define GPIO_AE_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AE_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AE_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AE_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_AE_INPUT_01_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AE_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AE_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AE_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AE_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_OUTPUT_CONTROL_01_0
+#define GPIO_AE_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x1362c)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_SECURE                      0x0
+#define GPIO_AE_OUTPUT_CONTROL_01_0_DUAL                        0x0
+#define GPIO_AE_OUTPUT_CONTROL_01_0_SCR                         GPIO_AE_SCR_01_0
+#define GPIO_AE_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_AE_SCR_01_0
+#define GPIO_AE_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
+#define GPIO_AE_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AE_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AE_OUTPUT_VALUE_01_0
+#define GPIO_AE_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x13630)
+#define GPIO_AE_OUTPUT_VALUE_01_0_SECURE                        0x0
+#define GPIO_AE_OUTPUT_VALUE_01_0_DUAL                  0x0
+#define GPIO_AE_OUTPUT_VALUE_01_0_SCR                   GPIO_AE_SCR_01_0
+#define GPIO_AE_OUTPUT_VALUE_01_0_SCRREG                        GPIO_AE_SCR_01_0
+#define GPIO_AE_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
+#define GPIO_AE_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AE_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INTERRUPT_CLEAR_01_0
+#define GPIO_AE_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x13634)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_SECURE                     0x0
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_DUAL                       0x0
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_SCR                        GPIO_AE_SCR_01_0
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_AE_SCR_01_0
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AE_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13638
+
+// Reserved address 0x1363c
+
+// Reserved address 0x13640
+
+// Reserved address 0x13644
+
+// Reserved address 0x13648
+
+// Reserved address 0x1364c
+
+// Reserved address 0x13650
+
+// Reserved address 0x13654
+
+// Reserved address 0x13658
+
+// Reserved address 0x1365c
+
+// Reserved address 0x13660
+
+// Reserved address 0x13664
+
+// Reserved address 0x13668
+
+// Reserved address 0x1366c
+
+// Reserved address 0x13670
+
+// Reserved address 0x13674
+
+// Reserved address 0x13678
+
+// Reserved address 0x1367c
+
+// Reserved address 0x13680
+
+// Reserved address 0x13684
+
+// Reserved address 0x13688
+
+// Reserved address 0x1368c
+
+// Reserved address 0x13690
+
+// Reserved address 0x13694
+
+// Reserved address 0x13698
+
+// Reserved address 0x1369c
+
+// Reserved address 0x136a0
+
+// Reserved address 0x136a4
+
+// Reserved address 0x136a8
+
+// Reserved address 0x136ac
+
+// Reserved address 0x136b0
+
+// Reserved address 0x136b4
+
+// Reserved address 0x136b8
+
+// Reserved address 0x136bc
+
+// Reserved address 0x136c0
+
+// Reserved address 0x136c4
+
+// Reserved address 0x136c8
+
+// Reserved address 0x136cc
+
+// Reserved address 0x136d0
+
+// Reserved address 0x136d4
+
+// Reserved address 0x136d8
+
+// Reserved address 0x136dc
+
+// Reserved address 0x136e0
+
+// Reserved address 0x136e4
+
+// Reserved address 0x136e8
+
+// Reserved address 0x136ec
+
+// Reserved address 0x136f0
+
+// Reserved address 0x136f4
+
+// Reserved address 0x136f8
+
+// Reserved address 0x136fc
+
+// Register GPIO_AE_INTERRUPT_STATUS_G0_0
+#define GPIO_AE_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x13700)
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_SECURE                    0x0
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_DUAL                      0x0
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_SCR                       0
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_SCRREG                    0
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INTERRUPT_STATUS_G1_0
+#define GPIO_AE_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x13704)
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_SECURE                    0x0
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_DUAL                      0x0
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_SCR                       0
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_SCRREG                    0
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INTERRUPT_STATUS_G2_0
+#define GPIO_AE_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x13708)
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_SECURE                    0x0
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_DUAL                      0x0
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_SCR                       0
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_SCRREG                    0
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INTERRUPT_STATUS_G3_0
+#define GPIO_AE_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x1370c)
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_SECURE                    0x0
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_DUAL                      0x0
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_SCR                       0
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_SCRREG                    0
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INTERRUPT_STATUS_G4_0
+#define GPIO_AE_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x13710)
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_SECURE                    0x0
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_DUAL                      0x0
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_SCR                       0
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_SCRREG                    0
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INTERRUPT_STATUS_G5_0
+#define GPIO_AE_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x13714)
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_SECURE                    0x0
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_DUAL                      0x0
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_SCR                       0
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_SCRREG                    0
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INTERRUPT_STATUS_G6_0
+#define GPIO_AE_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x13718)
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_SECURE                    0x0
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_DUAL                      0x0
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_SCR                       0
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_SCRREG                    0
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AE_INTERRUPT_STATUS_G7_0
+#define GPIO_AE_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x1371c)
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_SECURE                    0x0
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_DUAL                      0x0
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_SCR                       0
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_SCRREG                    0
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0x3, GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       1:0
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(1)
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AE_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x13720
+
+// Reserved address 0x13724
+
+// Reserved address 0x13728
+
+// Reserved address 0x1372c
+
+// Reserved address 0x13730
+
+// Reserved address 0x13734
+
+// Reserved address 0x13738
+
+// Reserved address 0x1373c
+
+// Reserved address 0x13740
+
+// Reserved address 0x13744
+
+// Reserved address 0x13748
+
+// Reserved address 0x1374c
+
+// Reserved address 0x13750
+
+// Reserved address 0x13754
+
+// Reserved address 0x13758
+
+// Reserved address 0x1375c
+
+// Reserved address 0x13760
+
+// Reserved address 0x13764
+
+// Reserved address 0x13768
+
+// Reserved address 0x1376c
+
+// Reserved address 0x13770
+
+// Reserved address 0x13774
+
+// Reserved address 0x13778
+
+// Reserved address 0x1377c
+
+// Reserved address 0x13780
+
+// Reserved address 0x13784
+
+// Reserved address 0x13788
+
+// Reserved address 0x1378c
+
+// Reserved address 0x13790
+
+// Reserved address 0x13794
+
+// Reserved address 0x13798
+
+// Reserved address 0x1379c
+
+// Reserved address 0x137a0
+
+// Reserved address 0x137a4
+
+// Reserved address 0x137a8
+
+// Reserved address 0x137ac
+
+// Reserved address 0x137b0
+
+// Reserved address 0x137b4
+
+// Reserved address 0x137b8
+
+// Reserved address 0x137bc
+
+// Reserved address 0x137c0
+
+// Reserved address 0x137c4
+
+// Reserved address 0x137c8
+
+// Reserved address 0x137cc
+
+// Reserved address 0x137d0
+
+// Reserved address 0x137d4
+
+// Reserved address 0x137d8
+
+// Reserved address 0x137dc
+
+// Reserved address 0x137e0
+
+// Reserved address 0x137e4
+
+// Reserved address 0x137e8
+
+// Reserved address 0x137ec
+
+// Reserved address 0x137f0
+
+// Reserved address 0x137f4
+
+// Reserved address 0x137f8
+
+// Reserved address 0x137fc
+
+// Register GPIO_AF_ENABLE_CONFIG_00_0
+#define GPIO_AF_ENABLE_CONFIG_00_0                      MK_ADDR_CONST(0x13800)
+#define GPIO_AF_ENABLE_CONFIG_00_0_SECURE                       0x0
+#define GPIO_AF_ENABLE_CONFIG_00_0_DUAL                         0x0
+#define GPIO_AF_ENABLE_CONFIG_00_0_SCR                  GPIO_AF_SCR_00_0
+#define GPIO_AF_ENABLE_CONFIG_00_0_SCRREG                       GPIO_AF_SCR_00_0
+#define GPIO_AF_ENABLE_CONFIG_00_0_WORD_COUNT                   0x1
+#define GPIO_AF_ENABLE_CONFIG_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AF_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AF_ENABLE_CONFIG_00_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_RANGE                 1:1
+#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AF_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0                 MK_ADDR_CONST(0x13804)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_SECURE                  0x0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DUAL                    0x0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_SCR                     GPIO_AF_SCR_00_0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_SCRREG                  GPIO_AF_SCR_00_0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                      0x1
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INPUT_00_0
+#define GPIO_AF_INPUT_00_0                      MK_ADDR_CONST(0x13808)
+#define GPIO_AF_INPUT_00_0_SECURE                       0x0
+#define GPIO_AF_INPUT_00_0_DUAL                         0x0
+#define GPIO_AF_INPUT_00_0_SCR                  GPIO_AF_SCR_00_0
+#define GPIO_AF_INPUT_00_0_SCRREG                       GPIO_AF_SCR_00_0
+#define GPIO_AF_INPUT_00_0_WORD_COUNT                   0x1
+#define GPIO_AF_INPUT_00_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_00_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AF_INPUT_00_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_00_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AF_INPUT_00_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AF_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_AF_INPUT_00_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AF_INPUT_00_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AF_INPUT_00_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AF_INPUT_00_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AF_INPUT_00_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_00_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_00_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_OUTPUT_CONTROL_00_0
+#define GPIO_AF_OUTPUT_CONTROL_00_0                     MK_ADDR_CONST(0x1380c)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_SECURE                      0x0
+#define GPIO_AF_OUTPUT_CONTROL_00_0_DUAL                        0x0
+#define GPIO_AF_OUTPUT_CONTROL_00_0_SCR                         GPIO_AF_SCR_00_0
+#define GPIO_AF_OUTPUT_CONTROL_00_0_SCRREG                      GPIO_AF_SCR_00_0
+#define GPIO_AF_OUTPUT_CONTROL_00_0_WORD_COUNT                  0x1
+#define GPIO_AF_OUTPUT_CONTROL_00_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AF_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AF_OUTPUT_VALUE_00_0
+#define GPIO_AF_OUTPUT_VALUE_00_0                       MK_ADDR_CONST(0x13810)
+#define GPIO_AF_OUTPUT_VALUE_00_0_SECURE                        0x0
+#define GPIO_AF_OUTPUT_VALUE_00_0_DUAL                  0x0
+#define GPIO_AF_OUTPUT_VALUE_00_0_SCR                   GPIO_AF_SCR_00_0
+#define GPIO_AF_OUTPUT_VALUE_00_0_SCRREG                        GPIO_AF_SCR_00_0
+#define GPIO_AF_OUTPUT_VALUE_00_0_WORD_COUNT                    0x1
+#define GPIO_AF_OUTPUT_VALUE_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_00_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_00_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INTERRUPT_CLEAR_00_0
+#define GPIO_AF_INTERRUPT_CLEAR_00_0                    MK_ADDR_CONST(0x13814)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_SECURE                     0x0
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_DUAL                       0x0
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_SCR                        GPIO_AF_SCR_00_0
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_SCRREG                     GPIO_AF_SCR_00_0
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_WORD_COUNT                         0x1
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AF_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13818
+
+// Reserved address 0x1381c
+
+// Register GPIO_AF_ENABLE_CONFIG_01_0
+#define GPIO_AF_ENABLE_CONFIG_01_0                      MK_ADDR_CONST(0x13820)
+#define GPIO_AF_ENABLE_CONFIG_01_0_SECURE                       0x0
+#define GPIO_AF_ENABLE_CONFIG_01_0_DUAL                         0x0
+#define GPIO_AF_ENABLE_CONFIG_01_0_SCR                  GPIO_AF_SCR_01_0
+#define GPIO_AF_ENABLE_CONFIG_01_0_SCRREG                       GPIO_AF_SCR_01_0
+#define GPIO_AF_ENABLE_CONFIG_01_0_WORD_COUNT                   0x1
+#define GPIO_AF_ENABLE_CONFIG_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AF_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AF_ENABLE_CONFIG_01_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_RANGE                 1:1
+#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AF_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0                 MK_ADDR_CONST(0x13824)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_SECURE                  0x0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DUAL                    0x0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_SCR                     GPIO_AF_SCR_01_0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_SCRREG                  GPIO_AF_SCR_01_0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                      0x1
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INPUT_01_0
+#define GPIO_AF_INPUT_01_0                      MK_ADDR_CONST(0x13828)
+#define GPIO_AF_INPUT_01_0_SECURE                       0x0
+#define GPIO_AF_INPUT_01_0_DUAL                         0x0
+#define GPIO_AF_INPUT_01_0_SCR                  GPIO_AF_SCR_01_0
+#define GPIO_AF_INPUT_01_0_SCRREG                       GPIO_AF_SCR_01_0
+#define GPIO_AF_INPUT_01_0_WORD_COUNT                   0x1
+#define GPIO_AF_INPUT_01_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_01_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AF_INPUT_01_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_01_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AF_INPUT_01_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AF_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_AF_INPUT_01_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AF_INPUT_01_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AF_INPUT_01_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AF_INPUT_01_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AF_INPUT_01_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_01_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_01_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_OUTPUT_CONTROL_01_0
+#define GPIO_AF_OUTPUT_CONTROL_01_0                     MK_ADDR_CONST(0x1382c)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_SECURE                      0x0
+#define GPIO_AF_OUTPUT_CONTROL_01_0_DUAL                        0x0
+#define GPIO_AF_OUTPUT_CONTROL_01_0_SCR                         GPIO_AF_SCR_01_0
+#define GPIO_AF_OUTPUT_CONTROL_01_0_SCRREG                      GPIO_AF_SCR_01_0
+#define GPIO_AF_OUTPUT_CONTROL_01_0_WORD_COUNT                  0x1
+#define GPIO_AF_OUTPUT_CONTROL_01_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AF_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AF_OUTPUT_VALUE_01_0
+#define GPIO_AF_OUTPUT_VALUE_01_0                       MK_ADDR_CONST(0x13830)
+#define GPIO_AF_OUTPUT_VALUE_01_0_SECURE                        0x0
+#define GPIO_AF_OUTPUT_VALUE_01_0_DUAL                  0x0
+#define GPIO_AF_OUTPUT_VALUE_01_0_SCR                   GPIO_AF_SCR_01_0
+#define GPIO_AF_OUTPUT_VALUE_01_0_SCRREG                        GPIO_AF_SCR_01_0
+#define GPIO_AF_OUTPUT_VALUE_01_0_WORD_COUNT                    0x1
+#define GPIO_AF_OUTPUT_VALUE_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_01_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_01_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INTERRUPT_CLEAR_01_0
+#define GPIO_AF_INTERRUPT_CLEAR_01_0                    MK_ADDR_CONST(0x13834)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_SECURE                     0x0
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_DUAL                       0x0
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_SCR                        GPIO_AF_SCR_01_0
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_SCRREG                     GPIO_AF_SCR_01_0
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_WORD_COUNT                         0x1
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AF_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13838
+
+// Reserved address 0x1383c
+
+// Register GPIO_AF_ENABLE_CONFIG_02_0
+#define GPIO_AF_ENABLE_CONFIG_02_0                      MK_ADDR_CONST(0x13840)
+#define GPIO_AF_ENABLE_CONFIG_02_0_SECURE                       0x0
+#define GPIO_AF_ENABLE_CONFIG_02_0_DUAL                         0x0
+#define GPIO_AF_ENABLE_CONFIG_02_0_SCR                  GPIO_AF_SCR_02_0
+#define GPIO_AF_ENABLE_CONFIG_02_0_SCRREG                       GPIO_AF_SCR_02_0
+#define GPIO_AF_ENABLE_CONFIG_02_0_WORD_COUNT                   0x1
+#define GPIO_AF_ENABLE_CONFIG_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AF_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AF_ENABLE_CONFIG_02_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_RANGE                 1:1
+#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AF_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0                 MK_ADDR_CONST(0x13844)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_SECURE                  0x0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DUAL                    0x0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_SCR                     GPIO_AF_SCR_02_0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_SCRREG                  GPIO_AF_SCR_02_0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                      0x1
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INPUT_02_0
+#define GPIO_AF_INPUT_02_0                      MK_ADDR_CONST(0x13848)
+#define GPIO_AF_INPUT_02_0_SECURE                       0x0
+#define GPIO_AF_INPUT_02_0_DUAL                         0x0
+#define GPIO_AF_INPUT_02_0_SCR                  GPIO_AF_SCR_02_0
+#define GPIO_AF_INPUT_02_0_SCRREG                       GPIO_AF_SCR_02_0
+#define GPIO_AF_INPUT_02_0_WORD_COUNT                   0x1
+#define GPIO_AF_INPUT_02_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_02_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AF_INPUT_02_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_02_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AF_INPUT_02_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AF_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_AF_INPUT_02_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AF_INPUT_02_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AF_INPUT_02_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AF_INPUT_02_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AF_INPUT_02_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_02_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_02_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_OUTPUT_CONTROL_02_0
+#define GPIO_AF_OUTPUT_CONTROL_02_0                     MK_ADDR_CONST(0x1384c)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_SECURE                      0x0
+#define GPIO_AF_OUTPUT_CONTROL_02_0_DUAL                        0x0
+#define GPIO_AF_OUTPUT_CONTROL_02_0_SCR                         GPIO_AF_SCR_02_0
+#define GPIO_AF_OUTPUT_CONTROL_02_0_SCRREG                      GPIO_AF_SCR_02_0
+#define GPIO_AF_OUTPUT_CONTROL_02_0_WORD_COUNT                  0x1
+#define GPIO_AF_OUTPUT_CONTROL_02_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AF_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AF_OUTPUT_VALUE_02_0
+#define GPIO_AF_OUTPUT_VALUE_02_0                       MK_ADDR_CONST(0x13850)
+#define GPIO_AF_OUTPUT_VALUE_02_0_SECURE                        0x0
+#define GPIO_AF_OUTPUT_VALUE_02_0_DUAL                  0x0
+#define GPIO_AF_OUTPUT_VALUE_02_0_SCR                   GPIO_AF_SCR_02_0
+#define GPIO_AF_OUTPUT_VALUE_02_0_SCRREG                        GPIO_AF_SCR_02_0
+#define GPIO_AF_OUTPUT_VALUE_02_0_WORD_COUNT                    0x1
+#define GPIO_AF_OUTPUT_VALUE_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_02_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_02_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INTERRUPT_CLEAR_02_0
+#define GPIO_AF_INTERRUPT_CLEAR_02_0                    MK_ADDR_CONST(0x13854)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_SECURE                     0x0
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_DUAL                       0x0
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_SCR                        GPIO_AF_SCR_02_0
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_SCRREG                     GPIO_AF_SCR_02_0
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_WORD_COUNT                         0x1
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AF_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13858
+
+// Reserved address 0x1385c
+
+// Register GPIO_AF_ENABLE_CONFIG_03_0
+#define GPIO_AF_ENABLE_CONFIG_03_0                      MK_ADDR_CONST(0x13860)
+#define GPIO_AF_ENABLE_CONFIG_03_0_SECURE                       0x0
+#define GPIO_AF_ENABLE_CONFIG_03_0_DUAL                         0x0
+#define GPIO_AF_ENABLE_CONFIG_03_0_SCR                  GPIO_AF_SCR_03_0
+#define GPIO_AF_ENABLE_CONFIG_03_0_SCRREG                       GPIO_AF_SCR_03_0
+#define GPIO_AF_ENABLE_CONFIG_03_0_WORD_COUNT                   0x1
+#define GPIO_AF_ENABLE_CONFIG_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AF_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_AF_ENABLE_CONFIG_03_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                    MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                    0:0
+#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                  0x0
+#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                 MK_SHIFT_CONST(1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_FIELD                 MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_RANGE                 1:1
+#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_MSB                   MK_SHIFT_CONST(1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_LSB                   MK_SHIFT_CONST(1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                       0x0
+#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_IN                    MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_IN_OUT_OUT                   MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                   MK_SHIFT_CONST(2)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                   MK_FIELD_CONST(0x3, GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                   3:2
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                     MK_SHIFT_CONST(3)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                     MK_SHIFT_CONST(2)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                 0x0
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                      MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                   MK_ENUM_CONST(1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                     MK_ENUM_CONST(2)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                     MK_ENUM_CONST(3)
+
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                  MK_SHIFT_CONST(4)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                  4:4
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                    MK_SHIFT_CONST(4)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                    MK_SHIFT_CONST(4)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                        0x0
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                        MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                        MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                      MK_SHIFT_CONST(5)
+#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                      5:5
+#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                        MK_SHIFT_CONST(5)
+#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                        MK_SHIFT_CONST(5)
+#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                    0x0
+#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                     MK_SHIFT_CONST(6)
+#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                     MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                     6:6
+#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                       MK_SHIFT_CONST(6)
+#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                       MK_SHIFT_CONST(6)
+#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                   0x0
+#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                  MK_SHIFT_CONST(7)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                  MK_FIELD_CONST(0x1, GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                  7:7
+#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                    MK_SHIFT_CONST(7)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                    MK_SHIFT_CONST(7)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                        0x0
+#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                        MK_ENUM_CONST(0)
+#define GPIO_AF_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GPIO_AF_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0                 MK_ADDR_CONST(0x13864)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_SECURE                  0x0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DUAL                    0x0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_SCR                     GPIO_AF_SCR_03_0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_SCRREG                  GPIO_AF_SCR_03_0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                      0x1
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                        MK_FIELD_CONST(0xff, GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                        7:0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                      0x0
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GPIO_AF_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INPUT_03_0
+#define GPIO_AF_INPUT_03_0                      MK_ADDR_CONST(0x13868)
+#define GPIO_AF_INPUT_03_0_SECURE                       0x0
+#define GPIO_AF_INPUT_03_0_DUAL                         0x0
+#define GPIO_AF_INPUT_03_0_SCR                  GPIO_AF_SCR_03_0
+#define GPIO_AF_INPUT_03_0_SCRREG                       GPIO_AF_SCR_03_0
+#define GPIO_AF_INPUT_03_0_WORD_COUNT                   0x1
+#define GPIO_AF_INPUT_03_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_03_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AF_INPUT_03_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_03_0_GPIO_IN_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_AF_INPUT_03_0_GPIO_IN_FIELD                        MK_FIELD_CONST(0x1, GPIO_AF_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_AF_INPUT_03_0_GPIO_IN_RANGE                        0:0
+#define GPIO_AF_INPUT_03_0_GPIO_IN_MSB                  MK_SHIFT_CONST(0)
+#define GPIO_AF_INPUT_03_0_GPIO_IN_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_AF_INPUT_03_0_GPIO_IN_WOFFSET                      0x0
+#define GPIO_AF_INPUT_03_0_GPIO_IN_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_03_0_GPIO_IN_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_03_0_GPIO_IN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_OUTPUT_CONTROL_03_0
+#define GPIO_AF_OUTPUT_CONTROL_03_0                     MK_ADDR_CONST(0x1386c)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_SECURE                      0x0
+#define GPIO_AF_OUTPUT_CONTROL_03_0_DUAL                        0x0
+#define GPIO_AF_OUTPUT_CONTROL_03_0_SCR                         GPIO_AF_SCR_03_0
+#define GPIO_AF_OUTPUT_CONTROL_03_0_SCRREG                      GPIO_AF_SCR_03_0
+#define GPIO_AF_OUTPUT_CONTROL_03_0_WORD_COUNT                  0x1
+#define GPIO_AF_OUTPUT_CONTROL_03_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                      MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                      MK_FIELD_CONST(0x1, GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                      0:0
+#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                        MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                        MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                    0x0
+#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                    MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                     MK_ENUM_CONST(0)
+#define GPIO_AF_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                    MK_ENUM_CONST(1)
+
+
+// Register GPIO_AF_OUTPUT_VALUE_03_0
+#define GPIO_AF_OUTPUT_VALUE_03_0                       MK_ADDR_CONST(0x13870)
+#define GPIO_AF_OUTPUT_VALUE_03_0_SECURE                        0x0
+#define GPIO_AF_OUTPUT_VALUE_03_0_DUAL                  0x0
+#define GPIO_AF_OUTPUT_VALUE_03_0_SCR                   GPIO_AF_SCR_03_0
+#define GPIO_AF_OUTPUT_VALUE_03_0_SCRREG                        GPIO_AF_SCR_03_0
+#define GPIO_AF_OUTPUT_VALUE_03_0_WORD_COUNT                    0x1
+#define GPIO_AF_OUTPUT_VALUE_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_03_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_03_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                    MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                    MK_FIELD_CONST(0x1, GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                    0:0
+#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                      MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                      MK_SHIFT_CONST(0)
+#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                  0x0
+#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_AF_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INTERRUPT_CLEAR_03_0
+#define GPIO_AF_INTERRUPT_CLEAR_03_0                    MK_ADDR_CONST(0x13874)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_SECURE                     0x0
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_DUAL                       0x0
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_SCR                        GPIO_AF_SCR_03_0
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_SCRREG                     GPIO_AF_SCR_03_0
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_WORD_COUNT                         0x1
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                 MK_FIELD_CONST(0x1, GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                 0:0
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                       0x0
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                     MK_ENUM_CONST(0)
+#define GPIO_AF_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x13878
+
+// Reserved address 0x1387c
+
+// Reserved address 0x13880
+
+// Reserved address 0x13884
+
+// Reserved address 0x13888
+
+// Reserved address 0x1388c
+
+// Reserved address 0x13890
+
+// Reserved address 0x13894
+
+// Reserved address 0x13898
+
+// Reserved address 0x1389c
+
+// Reserved address 0x138a0
+
+// Reserved address 0x138a4
+
+// Reserved address 0x138a8
+
+// Reserved address 0x138ac
+
+// Reserved address 0x138b0
+
+// Reserved address 0x138b4
+
+// Reserved address 0x138b8
+
+// Reserved address 0x138bc
+
+// Reserved address 0x138c0
+
+// Reserved address 0x138c4
+
+// Reserved address 0x138c8
+
+// Reserved address 0x138cc
+
+// Reserved address 0x138d0
+
+// Reserved address 0x138d4
+
+// Reserved address 0x138d8
+
+// Reserved address 0x138dc
+
+// Reserved address 0x138e0
+
+// Reserved address 0x138e4
+
+// Reserved address 0x138e8
+
+// Reserved address 0x138ec
+
+// Reserved address 0x138f0
+
+// Reserved address 0x138f4
+
+// Reserved address 0x138f8
+
+// Reserved address 0x138fc
+
+// Register GPIO_AF_INTERRUPT_STATUS_G0_0
+#define GPIO_AF_INTERRUPT_STATUS_G0_0                   MK_ADDR_CONST(0x13900)
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_SECURE                    0x0
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_DUAL                      0x0
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_SCR                       0
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_SCRREG                    0
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_WORD_COUNT                        0x1
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INTERRUPT_STATUS_G1_0
+#define GPIO_AF_INTERRUPT_STATUS_G1_0                   MK_ADDR_CONST(0x13904)
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_SECURE                    0x0
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_DUAL                      0x0
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_SCR                       0
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_SCRREG                    0
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_WORD_COUNT                        0x1
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INTERRUPT_STATUS_G2_0
+#define GPIO_AF_INTERRUPT_STATUS_G2_0                   MK_ADDR_CONST(0x13908)
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_SECURE                    0x0
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_DUAL                      0x0
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_SCR                       0
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_SCRREG                    0
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_WORD_COUNT                        0x1
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INTERRUPT_STATUS_G3_0
+#define GPIO_AF_INTERRUPT_STATUS_G3_0                   MK_ADDR_CONST(0x1390c)
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_SECURE                    0x0
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_DUAL                      0x0
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_SCR                       0
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_SCRREG                    0
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_WORD_COUNT                        0x1
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INTERRUPT_STATUS_G4_0
+#define GPIO_AF_INTERRUPT_STATUS_G4_0                   MK_ADDR_CONST(0x13910)
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_SECURE                    0x0
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_DUAL                      0x0
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_SCR                       0
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_SCRREG                    0
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_WORD_COUNT                        0x1
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INTERRUPT_STATUS_G5_0
+#define GPIO_AF_INTERRUPT_STATUS_G5_0                   MK_ADDR_CONST(0x13914)
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_SECURE                    0x0
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_DUAL                      0x0
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_SCR                       0
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_SCRREG                    0
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_WORD_COUNT                        0x1
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INTERRUPT_STATUS_G6_0
+#define GPIO_AF_INTERRUPT_STATUS_G6_0                   MK_ADDR_CONST(0x13918)
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_SECURE                    0x0
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_DUAL                      0x0
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_SCR                       0
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_SCRREG                    0
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_WORD_COUNT                        0x1
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GPIO_AF_INTERRUPT_STATUS_G7_0
+#define GPIO_AF_INTERRUPT_STATUS_G7_0                   MK_ADDR_CONST(0x1391c)
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_SECURE                    0x0
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_DUAL                      0x0
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_SCR                       0
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_SCRREG                    0
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_WORD_COUNT                        0x1
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_RESET_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_READ_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                       MK_FIELD_CONST(0xf, GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                       3:0
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                 MK_SHIFT_CONST(3)
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                     0x0
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GPIO_AF_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x13920
+
+// Reserved address 0x13924
+
+// Reserved address 0x13928
+
+// Reserved address 0x1392c
+
+// Reserved address 0x13930
+
+// Reserved address 0x13934
+
+// Reserved address 0x13938
+
+// Reserved address 0x1393c
+
+// Reserved address 0x13940
+
+// Reserved address 0x13944
+
+// Reserved address 0x13948
+
+// Reserved address 0x1394c
+
+// Reserved address 0x13950
+
+// Reserved address 0x13954
+
+// Reserved address 0x13958
+
+// Reserved address 0x1395c
+
+// Reserved address 0x13960
+
+// Reserved address 0x13964
+
+// Reserved address 0x13968
+
+// Reserved address 0x1396c
+
+// Reserved address 0x13970
+
+// Reserved address 0x13974
+
+// Reserved address 0x13978
+
+// Reserved address 0x1397c
+
+// Reserved address 0x13980
+
+// Reserved address 0x13984
+
+// Reserved address 0x13988
+
+// Reserved address 0x1398c
+
+// Reserved address 0x13990
+
+// Reserved address 0x13994
+
+// Reserved address 0x13998
+
+// Reserved address 0x1399c
+
+// Reserved address 0x139a0
+
+// Reserved address 0x139a4
+
+// Reserved address 0x139a8
+
+// Reserved address 0x139ac
+
+// Reserved address 0x139b0
+
+// Reserved address 0x139b4
+
+// Reserved address 0x139b8
+
+// Reserved address 0x139bc
+
+// Reserved address 0x139c0
+
+// Reserved address 0x139c4
+
+// Reserved address 0x139c8
+
+// Reserved address 0x139cc
+
+// Reserved address 0x139d0
+
+// Reserved address 0x139d4
+
+// Reserved address 0x139d8
+
+// Reserved address 0x139dc
+
+// Reserved address 0x139e0
+
+// Reserved address 0x139e4
+
+// Reserved address 0x139e8
+
+// Reserved address 0x139ec
+
+// Reserved address 0x139f0
+
+// Reserved address 0x139f4
+
+// Reserved address 0x139f8
+
+// Reserved address 0x139fc
+
+// Register GPIO_G_ENABLE_CONFIG_00_0
+#define GPIO_G_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x14000)
+#define GPIO_G_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_G_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_G_ENABLE_CONFIG_00_0_SCR                   GPIO_G_SCR_00_0
+#define GPIO_G_ENABLE_CONFIG_00_0_SCRREG                        GPIO_G_SCR_00_0
+#define GPIO_G_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_G_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_G_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x14004)
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_G_SCR_00_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_G_SCR_00_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_G_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INPUT_00_0
+#define GPIO_G_INPUT_00_0                       MK_ADDR_CONST(0x14008)
+#define GPIO_G_INPUT_00_0_SECURE                        0x0
+#define GPIO_G_INPUT_00_0_DUAL                  0x0
+#define GPIO_G_INPUT_00_0_SCR                   GPIO_G_SCR_00_0
+#define GPIO_G_INPUT_00_0_SCRREG                        GPIO_G_SCR_00_0
+#define GPIO_G_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_G_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_G_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_G_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_G_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_G_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_OUTPUT_CONTROL_00_0
+#define GPIO_G_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1400c)
+#define GPIO_G_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_G_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_G_OUTPUT_CONTROL_00_0_SCR                  GPIO_G_SCR_00_0
+#define GPIO_G_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_G_SCR_00_0
+#define GPIO_G_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_G_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_G_OUTPUT_VALUE_00_0
+#define GPIO_G_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x14010)
+#define GPIO_G_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_G_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_G_OUTPUT_VALUE_00_0_SCR                    GPIO_G_SCR_00_0
+#define GPIO_G_OUTPUT_VALUE_00_0_SCRREG                         GPIO_G_SCR_00_0
+#define GPIO_G_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_G_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INTERRUPT_CLEAR_00_0
+#define GPIO_G_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x14014)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_G_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_G_INTERRUPT_CLEAR_00_0_SCR                         GPIO_G_SCR_00_0
+#define GPIO_G_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_G_SCR_00_0
+#define GPIO_G_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_G_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14018
+
+// Reserved address 0x1401c
+
+// Register GPIO_G_ENABLE_CONFIG_01_0
+#define GPIO_G_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x14020)
+#define GPIO_G_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_G_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_G_ENABLE_CONFIG_01_0_SCR                   GPIO_G_SCR_01_0
+#define GPIO_G_ENABLE_CONFIG_01_0_SCRREG                        GPIO_G_SCR_01_0
+#define GPIO_G_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_G_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_G_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x14024)
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_G_SCR_01_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_G_SCR_01_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_G_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INPUT_01_0
+#define GPIO_G_INPUT_01_0                       MK_ADDR_CONST(0x14028)
+#define GPIO_G_INPUT_01_0_SECURE                        0x0
+#define GPIO_G_INPUT_01_0_DUAL                  0x0
+#define GPIO_G_INPUT_01_0_SCR                   GPIO_G_SCR_01_0
+#define GPIO_G_INPUT_01_0_SCRREG                        GPIO_G_SCR_01_0
+#define GPIO_G_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_G_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_G_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_G_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_G_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_G_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_OUTPUT_CONTROL_01_0
+#define GPIO_G_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1402c)
+#define GPIO_G_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_G_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_G_OUTPUT_CONTROL_01_0_SCR                  GPIO_G_SCR_01_0
+#define GPIO_G_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_G_SCR_01_0
+#define GPIO_G_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_G_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_G_OUTPUT_VALUE_01_0
+#define GPIO_G_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x14030)
+#define GPIO_G_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_G_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_G_OUTPUT_VALUE_01_0_SCR                    GPIO_G_SCR_01_0
+#define GPIO_G_OUTPUT_VALUE_01_0_SCRREG                         GPIO_G_SCR_01_0
+#define GPIO_G_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_G_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INTERRUPT_CLEAR_01_0
+#define GPIO_G_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x14034)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_G_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_G_INTERRUPT_CLEAR_01_0_SCR                         GPIO_G_SCR_01_0
+#define GPIO_G_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_G_SCR_01_0
+#define GPIO_G_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_G_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14038
+
+// Reserved address 0x1403c
+
+// Register GPIO_G_ENABLE_CONFIG_02_0
+#define GPIO_G_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x14040)
+#define GPIO_G_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_G_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_G_ENABLE_CONFIG_02_0_SCR                   GPIO_G_SCR_02_0
+#define GPIO_G_ENABLE_CONFIG_02_0_SCRREG                        GPIO_G_SCR_02_0
+#define GPIO_G_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_G_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_G_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x14044)
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_G_SCR_02_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_G_SCR_02_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_G_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INPUT_02_0
+#define GPIO_G_INPUT_02_0                       MK_ADDR_CONST(0x14048)
+#define GPIO_G_INPUT_02_0_SECURE                        0x0
+#define GPIO_G_INPUT_02_0_DUAL                  0x0
+#define GPIO_G_INPUT_02_0_SCR                   GPIO_G_SCR_02_0
+#define GPIO_G_INPUT_02_0_SCRREG                        GPIO_G_SCR_02_0
+#define GPIO_G_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_G_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_G_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_G_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_G_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_G_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_OUTPUT_CONTROL_02_0
+#define GPIO_G_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1404c)
+#define GPIO_G_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_G_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_G_OUTPUT_CONTROL_02_0_SCR                  GPIO_G_SCR_02_0
+#define GPIO_G_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_G_SCR_02_0
+#define GPIO_G_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_G_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_G_OUTPUT_VALUE_02_0
+#define GPIO_G_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x14050)
+#define GPIO_G_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_G_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_G_OUTPUT_VALUE_02_0_SCR                    GPIO_G_SCR_02_0
+#define GPIO_G_OUTPUT_VALUE_02_0_SCRREG                         GPIO_G_SCR_02_0
+#define GPIO_G_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_G_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INTERRUPT_CLEAR_02_0
+#define GPIO_G_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x14054)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_G_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_G_INTERRUPT_CLEAR_02_0_SCR                         GPIO_G_SCR_02_0
+#define GPIO_G_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_G_SCR_02_0
+#define GPIO_G_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_G_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14058
+
+// Reserved address 0x1405c
+
+// Register GPIO_G_ENABLE_CONFIG_03_0
+#define GPIO_G_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x14060)
+#define GPIO_G_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_G_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_G_ENABLE_CONFIG_03_0_SCR                   GPIO_G_SCR_03_0
+#define GPIO_G_ENABLE_CONFIG_03_0_SCRREG                        GPIO_G_SCR_03_0
+#define GPIO_G_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_G_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_G_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x14064)
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_G_SCR_03_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_G_SCR_03_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_G_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INPUT_03_0
+#define GPIO_G_INPUT_03_0                       MK_ADDR_CONST(0x14068)
+#define GPIO_G_INPUT_03_0_SECURE                        0x0
+#define GPIO_G_INPUT_03_0_DUAL                  0x0
+#define GPIO_G_INPUT_03_0_SCR                   GPIO_G_SCR_03_0
+#define GPIO_G_INPUT_03_0_SCRREG                        GPIO_G_SCR_03_0
+#define GPIO_G_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_G_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_G_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_G_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_G_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_G_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_OUTPUT_CONTROL_03_0
+#define GPIO_G_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1406c)
+#define GPIO_G_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_G_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_G_OUTPUT_CONTROL_03_0_SCR                  GPIO_G_SCR_03_0
+#define GPIO_G_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_G_SCR_03_0
+#define GPIO_G_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_G_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_G_OUTPUT_VALUE_03_0
+#define GPIO_G_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x14070)
+#define GPIO_G_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_G_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_G_OUTPUT_VALUE_03_0_SCR                    GPIO_G_SCR_03_0
+#define GPIO_G_OUTPUT_VALUE_03_0_SCRREG                         GPIO_G_SCR_03_0
+#define GPIO_G_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_G_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INTERRUPT_CLEAR_03_0
+#define GPIO_G_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x14074)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_G_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_G_INTERRUPT_CLEAR_03_0_SCR                         GPIO_G_SCR_03_0
+#define GPIO_G_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_G_SCR_03_0
+#define GPIO_G_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_G_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14078
+
+// Reserved address 0x1407c
+
+// Register GPIO_G_ENABLE_CONFIG_04_0
+#define GPIO_G_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x14080)
+#define GPIO_G_ENABLE_CONFIG_04_0_SECURE                        0x0
+#define GPIO_G_ENABLE_CONFIG_04_0_DUAL                  0x0
+#define GPIO_G_ENABLE_CONFIG_04_0_SCR                   GPIO_G_SCR_04_0
+#define GPIO_G_ENABLE_CONFIG_04_0_SCRREG                        GPIO_G_SCR_04_0
+#define GPIO_G_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
+#define GPIO_G_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
+#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_G_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x14084)
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_G_SCR_04_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_G_SCR_04_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_G_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INPUT_04_0
+#define GPIO_G_INPUT_04_0                       MK_ADDR_CONST(0x14088)
+#define GPIO_G_INPUT_04_0_SECURE                        0x0
+#define GPIO_G_INPUT_04_0_DUAL                  0x0
+#define GPIO_G_INPUT_04_0_SCR                   GPIO_G_SCR_04_0
+#define GPIO_G_INPUT_04_0_SCRREG                        GPIO_G_SCR_04_0
+#define GPIO_G_INPUT_04_0_WORD_COUNT                    0x1
+#define GPIO_G_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_G_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_G_INPUT_04_0_GPIO_IN_RANGE                 0:0
+#define GPIO_G_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_G_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_OUTPUT_CONTROL_04_0
+#define GPIO_G_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1408c)
+#define GPIO_G_OUTPUT_CONTROL_04_0_SECURE                       0x0
+#define GPIO_G_OUTPUT_CONTROL_04_0_DUAL                         0x0
+#define GPIO_G_OUTPUT_CONTROL_04_0_SCR                  GPIO_G_SCR_04_0
+#define GPIO_G_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_G_SCR_04_0
+#define GPIO_G_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
+#define GPIO_G_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_G_OUTPUT_VALUE_04_0
+#define GPIO_G_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x14090)
+#define GPIO_G_OUTPUT_VALUE_04_0_SECURE                         0x0
+#define GPIO_G_OUTPUT_VALUE_04_0_DUAL                   0x0
+#define GPIO_G_OUTPUT_VALUE_04_0_SCR                    GPIO_G_SCR_04_0
+#define GPIO_G_OUTPUT_VALUE_04_0_SCRREG                         GPIO_G_SCR_04_0
+#define GPIO_G_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
+#define GPIO_G_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INTERRUPT_CLEAR_04_0
+#define GPIO_G_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x14094)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_SECURE                      0x0
+#define GPIO_G_INTERRUPT_CLEAR_04_0_DUAL                        0x0
+#define GPIO_G_INTERRUPT_CLEAR_04_0_SCR                         GPIO_G_SCR_04_0
+#define GPIO_G_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_G_SCR_04_0
+#define GPIO_G_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
+#define GPIO_G_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14098
+
+// Reserved address 0x1409c
+
+// Register GPIO_G_ENABLE_CONFIG_05_0
+#define GPIO_G_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x140a0)
+#define GPIO_G_ENABLE_CONFIG_05_0_SECURE                        0x0
+#define GPIO_G_ENABLE_CONFIG_05_0_DUAL                  0x0
+#define GPIO_G_ENABLE_CONFIG_05_0_SCR                   GPIO_G_SCR_05_0
+#define GPIO_G_ENABLE_CONFIG_05_0_SCRREG                        GPIO_G_SCR_05_0
+#define GPIO_G_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
+#define GPIO_G_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
+#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_G_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x140a4)
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_G_SCR_05_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_G_SCR_05_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_G_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INPUT_05_0
+#define GPIO_G_INPUT_05_0                       MK_ADDR_CONST(0x140a8)
+#define GPIO_G_INPUT_05_0_SECURE                        0x0
+#define GPIO_G_INPUT_05_0_DUAL                  0x0
+#define GPIO_G_INPUT_05_0_SCR                   GPIO_G_SCR_05_0
+#define GPIO_G_INPUT_05_0_SCRREG                        GPIO_G_SCR_05_0
+#define GPIO_G_INPUT_05_0_WORD_COUNT                    0x1
+#define GPIO_G_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_G_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_G_INPUT_05_0_GPIO_IN_RANGE                 0:0
+#define GPIO_G_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_G_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_OUTPUT_CONTROL_05_0
+#define GPIO_G_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x140ac)
+#define GPIO_G_OUTPUT_CONTROL_05_0_SECURE                       0x0
+#define GPIO_G_OUTPUT_CONTROL_05_0_DUAL                         0x0
+#define GPIO_G_OUTPUT_CONTROL_05_0_SCR                  GPIO_G_SCR_05_0
+#define GPIO_G_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_G_SCR_05_0
+#define GPIO_G_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
+#define GPIO_G_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_G_OUTPUT_VALUE_05_0
+#define GPIO_G_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x140b0)
+#define GPIO_G_OUTPUT_VALUE_05_0_SECURE                         0x0
+#define GPIO_G_OUTPUT_VALUE_05_0_DUAL                   0x0
+#define GPIO_G_OUTPUT_VALUE_05_0_SCR                    GPIO_G_SCR_05_0
+#define GPIO_G_OUTPUT_VALUE_05_0_SCRREG                         GPIO_G_SCR_05_0
+#define GPIO_G_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
+#define GPIO_G_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INTERRUPT_CLEAR_05_0
+#define GPIO_G_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x140b4)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_SECURE                      0x0
+#define GPIO_G_INTERRUPT_CLEAR_05_0_DUAL                        0x0
+#define GPIO_G_INTERRUPT_CLEAR_05_0_SCR                         GPIO_G_SCR_05_0
+#define GPIO_G_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_G_SCR_05_0
+#define GPIO_G_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
+#define GPIO_G_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x140b8
+
+// Reserved address 0x140bc
+
+// Register GPIO_G_ENABLE_CONFIG_06_0
+#define GPIO_G_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x140c0)
+#define GPIO_G_ENABLE_CONFIG_06_0_SECURE                        0x0
+#define GPIO_G_ENABLE_CONFIG_06_0_DUAL                  0x0
+#define GPIO_G_ENABLE_CONFIG_06_0_SCR                   GPIO_G_SCR_06_0
+#define GPIO_G_ENABLE_CONFIG_06_0_SCRREG                        GPIO_G_SCR_06_0
+#define GPIO_G_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
+#define GPIO_G_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
+#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_G_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x140c4)
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_G_SCR_06_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_G_SCR_06_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_G_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INPUT_06_0
+#define GPIO_G_INPUT_06_0                       MK_ADDR_CONST(0x140c8)
+#define GPIO_G_INPUT_06_0_SECURE                        0x0
+#define GPIO_G_INPUT_06_0_DUAL                  0x0
+#define GPIO_G_INPUT_06_0_SCR                   GPIO_G_SCR_06_0
+#define GPIO_G_INPUT_06_0_SCRREG                        GPIO_G_SCR_06_0
+#define GPIO_G_INPUT_06_0_WORD_COUNT                    0x1
+#define GPIO_G_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_G_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_G_INPUT_06_0_GPIO_IN_RANGE                 0:0
+#define GPIO_G_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_G_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_OUTPUT_CONTROL_06_0
+#define GPIO_G_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x140cc)
+#define GPIO_G_OUTPUT_CONTROL_06_0_SECURE                       0x0
+#define GPIO_G_OUTPUT_CONTROL_06_0_DUAL                         0x0
+#define GPIO_G_OUTPUT_CONTROL_06_0_SCR                  GPIO_G_SCR_06_0
+#define GPIO_G_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_G_SCR_06_0
+#define GPIO_G_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
+#define GPIO_G_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_G_OUTPUT_VALUE_06_0
+#define GPIO_G_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x140d0)
+#define GPIO_G_OUTPUT_VALUE_06_0_SECURE                         0x0
+#define GPIO_G_OUTPUT_VALUE_06_0_DUAL                   0x0
+#define GPIO_G_OUTPUT_VALUE_06_0_SCR                    GPIO_G_SCR_06_0
+#define GPIO_G_OUTPUT_VALUE_06_0_SCRREG                         GPIO_G_SCR_06_0
+#define GPIO_G_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
+#define GPIO_G_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INTERRUPT_CLEAR_06_0
+#define GPIO_G_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x140d4)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_SECURE                      0x0
+#define GPIO_G_INTERRUPT_CLEAR_06_0_DUAL                        0x0
+#define GPIO_G_INTERRUPT_CLEAR_06_0_SCR                         GPIO_G_SCR_06_0
+#define GPIO_G_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_G_SCR_06_0
+#define GPIO_G_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
+#define GPIO_G_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x140d8
+
+// Reserved address 0x140dc
+
+// Register GPIO_G_ENABLE_CONFIG_07_0
+#define GPIO_G_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x140e0)
+#define GPIO_G_ENABLE_CONFIG_07_0_SECURE                        0x0
+#define GPIO_G_ENABLE_CONFIG_07_0_DUAL                  0x0
+#define GPIO_G_ENABLE_CONFIG_07_0_SCR                   GPIO_G_SCR_07_0
+#define GPIO_G_ENABLE_CONFIG_07_0_SCRREG                        GPIO_G_SCR_07_0
+#define GPIO_G_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
+#define GPIO_G_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
+#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_G_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_G_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x140e4)
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_G_SCR_07_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_G_SCR_07_0
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_G_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INPUT_07_0
+#define GPIO_G_INPUT_07_0                       MK_ADDR_CONST(0x140e8)
+#define GPIO_G_INPUT_07_0_SECURE                        0x0
+#define GPIO_G_INPUT_07_0_DUAL                  0x0
+#define GPIO_G_INPUT_07_0_SCR                   GPIO_G_SCR_07_0
+#define GPIO_G_INPUT_07_0_SCRREG                        GPIO_G_SCR_07_0
+#define GPIO_G_INPUT_07_0_WORD_COUNT                    0x1
+#define GPIO_G_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_G_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_G_INPUT_07_0_GPIO_IN_RANGE                 0:0
+#define GPIO_G_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_G_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_G_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_G_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_OUTPUT_CONTROL_07_0
+#define GPIO_G_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x140ec)
+#define GPIO_G_OUTPUT_CONTROL_07_0_SECURE                       0x0
+#define GPIO_G_OUTPUT_CONTROL_07_0_DUAL                         0x0
+#define GPIO_G_OUTPUT_CONTROL_07_0_SCR                  GPIO_G_SCR_07_0
+#define GPIO_G_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_G_SCR_07_0
+#define GPIO_G_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
+#define GPIO_G_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_G_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_G_OUTPUT_VALUE_07_0
+#define GPIO_G_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x140f0)
+#define GPIO_G_OUTPUT_VALUE_07_0_SECURE                         0x0
+#define GPIO_G_OUTPUT_VALUE_07_0_DUAL                   0x0
+#define GPIO_G_OUTPUT_VALUE_07_0_SCR                    GPIO_G_SCR_07_0
+#define GPIO_G_OUTPUT_VALUE_07_0_SCRREG                         GPIO_G_SCR_07_0
+#define GPIO_G_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
+#define GPIO_G_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_G_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INTERRUPT_CLEAR_07_0
+#define GPIO_G_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x140f4)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_SECURE                      0x0
+#define GPIO_G_INTERRUPT_CLEAR_07_0_DUAL                        0x0
+#define GPIO_G_INTERRUPT_CLEAR_07_0_SCR                         GPIO_G_SCR_07_0
+#define GPIO_G_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_G_SCR_07_0
+#define GPIO_G_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
+#define GPIO_G_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_G_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x140f8
+
+// Reserved address 0x140fc
+
+// Register GPIO_G_INTERRUPT_STATUS_G0_0
+#define GPIO_G_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x14100)
+#define GPIO_G_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_G_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_G_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_G_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_G_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_G_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INTERRUPT_STATUS_G1_0
+#define GPIO_G_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x14104)
+#define GPIO_G_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_G_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_G_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_G_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_G_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_G_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INTERRUPT_STATUS_G2_0
+#define GPIO_G_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x14108)
+#define GPIO_G_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_G_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_G_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_G_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_G_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_G_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INTERRUPT_STATUS_G3_0
+#define GPIO_G_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1410c)
+#define GPIO_G_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_G_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_G_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_G_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_G_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_G_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INTERRUPT_STATUS_G4_0
+#define GPIO_G_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x14110)
+#define GPIO_G_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_G_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_G_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_G_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_G_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_G_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INTERRUPT_STATUS_G5_0
+#define GPIO_G_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x14114)
+#define GPIO_G_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_G_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_G_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_G_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_G_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_G_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INTERRUPT_STATUS_G6_0
+#define GPIO_G_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x14118)
+#define GPIO_G_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_G_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_G_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_G_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_G_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_G_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_G_INTERRUPT_STATUS_G7_0
+#define GPIO_G_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1411c)
+#define GPIO_G_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_G_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_G_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_G_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_G_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_G_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_G_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x14120
+
+// Reserved address 0x14124
+
+// Reserved address 0x14128
+
+// Reserved address 0x1412c
+
+// Reserved address 0x14130
+
+// Reserved address 0x14134
+
+// Reserved address 0x14138
+
+// Reserved address 0x1413c
+
+// Reserved address 0x14140
+
+// Reserved address 0x14144
+
+// Reserved address 0x14148
+
+// Reserved address 0x1414c
+
+// Reserved address 0x14150
+
+// Reserved address 0x14154
+
+// Reserved address 0x14158
+
+// Reserved address 0x1415c
+
+// Reserved address 0x14160
+
+// Reserved address 0x14164
+
+// Reserved address 0x14168
+
+// Reserved address 0x1416c
+
+// Reserved address 0x14170
+
+// Reserved address 0x14174
+
+// Reserved address 0x14178
+
+// Reserved address 0x1417c
+
+// Reserved address 0x14180
+
+// Reserved address 0x14184
+
+// Reserved address 0x14188
+
+// Reserved address 0x1418c
+
+// Reserved address 0x14190
+
+// Reserved address 0x14194
+
+// Reserved address 0x14198
+
+// Reserved address 0x1419c
+
+// Reserved address 0x141a0
+
+// Reserved address 0x141a4
+
+// Reserved address 0x141a8
+
+// Reserved address 0x141ac
+
+// Reserved address 0x141b0
+
+// Reserved address 0x141b4
+
+// Reserved address 0x141b8
+
+// Reserved address 0x141bc
+
+// Reserved address 0x141c0
+
+// Reserved address 0x141c4
+
+// Reserved address 0x141c8
+
+// Reserved address 0x141cc
+
+// Reserved address 0x141d0
+
+// Reserved address 0x141d4
+
+// Reserved address 0x141d8
+
+// Reserved address 0x141dc
+
+// Reserved address 0x141e0
+
+// Reserved address 0x141e4
+
+// Reserved address 0x141e8
+
+// Reserved address 0x141ec
+
+// Reserved address 0x141f0
+
+// Reserved address 0x141f4
+
+// Reserved address 0x141f8
+
+// Reserved address 0x141fc
+
+// Register GPIO_H_ENABLE_CONFIG_00_0
+#define GPIO_H_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x14200)
+#define GPIO_H_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_H_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_H_ENABLE_CONFIG_00_0_SCR                   GPIO_H_SCR_00_0
+#define GPIO_H_ENABLE_CONFIG_00_0_SCRREG                        GPIO_H_SCR_00_0
+#define GPIO_H_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_H_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_H_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x14204)
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_H_SCR_00_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_H_SCR_00_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_H_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INPUT_00_0
+#define GPIO_H_INPUT_00_0                       MK_ADDR_CONST(0x14208)
+#define GPIO_H_INPUT_00_0_SECURE                        0x0
+#define GPIO_H_INPUT_00_0_DUAL                  0x0
+#define GPIO_H_INPUT_00_0_SCR                   GPIO_H_SCR_00_0
+#define GPIO_H_INPUT_00_0_SCRREG                        GPIO_H_SCR_00_0
+#define GPIO_H_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_H_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_H_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_H_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_H_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_H_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_OUTPUT_CONTROL_00_0
+#define GPIO_H_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1420c)
+#define GPIO_H_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_H_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_H_OUTPUT_CONTROL_00_0_SCR                  GPIO_H_SCR_00_0
+#define GPIO_H_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_H_SCR_00_0
+#define GPIO_H_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_H_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_H_OUTPUT_VALUE_00_0
+#define GPIO_H_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x14210)
+#define GPIO_H_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_H_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_H_OUTPUT_VALUE_00_0_SCR                    GPIO_H_SCR_00_0
+#define GPIO_H_OUTPUT_VALUE_00_0_SCRREG                         GPIO_H_SCR_00_0
+#define GPIO_H_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_H_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INTERRUPT_CLEAR_00_0
+#define GPIO_H_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x14214)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_H_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_H_INTERRUPT_CLEAR_00_0_SCR                         GPIO_H_SCR_00_0
+#define GPIO_H_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_H_SCR_00_0
+#define GPIO_H_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_H_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14218
+
+// Reserved address 0x1421c
+
+// Register GPIO_H_ENABLE_CONFIG_01_0
+#define GPIO_H_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x14220)
+#define GPIO_H_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_H_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_H_ENABLE_CONFIG_01_0_SCR                   GPIO_H_SCR_01_0
+#define GPIO_H_ENABLE_CONFIG_01_0_SCRREG                        GPIO_H_SCR_01_0
+#define GPIO_H_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_H_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_H_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x14224)
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_H_SCR_01_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_H_SCR_01_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_H_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INPUT_01_0
+#define GPIO_H_INPUT_01_0                       MK_ADDR_CONST(0x14228)
+#define GPIO_H_INPUT_01_0_SECURE                        0x0
+#define GPIO_H_INPUT_01_0_DUAL                  0x0
+#define GPIO_H_INPUT_01_0_SCR                   GPIO_H_SCR_01_0
+#define GPIO_H_INPUT_01_0_SCRREG                        GPIO_H_SCR_01_0
+#define GPIO_H_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_H_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_H_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_H_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_H_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_H_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_OUTPUT_CONTROL_01_0
+#define GPIO_H_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1422c)
+#define GPIO_H_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_H_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_H_OUTPUT_CONTROL_01_0_SCR                  GPIO_H_SCR_01_0
+#define GPIO_H_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_H_SCR_01_0
+#define GPIO_H_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_H_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_H_OUTPUT_VALUE_01_0
+#define GPIO_H_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x14230)
+#define GPIO_H_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_H_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_H_OUTPUT_VALUE_01_0_SCR                    GPIO_H_SCR_01_0
+#define GPIO_H_OUTPUT_VALUE_01_0_SCRREG                         GPIO_H_SCR_01_0
+#define GPIO_H_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_H_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INTERRUPT_CLEAR_01_0
+#define GPIO_H_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x14234)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_H_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_H_INTERRUPT_CLEAR_01_0_SCR                         GPIO_H_SCR_01_0
+#define GPIO_H_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_H_SCR_01_0
+#define GPIO_H_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_H_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14238
+
+// Reserved address 0x1423c
+
+// Register GPIO_H_ENABLE_CONFIG_02_0
+#define GPIO_H_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x14240)
+#define GPIO_H_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_H_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_H_ENABLE_CONFIG_02_0_SCR                   GPIO_H_SCR_02_0
+#define GPIO_H_ENABLE_CONFIG_02_0_SCRREG                        GPIO_H_SCR_02_0
+#define GPIO_H_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_H_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_H_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x14244)
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_H_SCR_02_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_H_SCR_02_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_H_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INPUT_02_0
+#define GPIO_H_INPUT_02_0                       MK_ADDR_CONST(0x14248)
+#define GPIO_H_INPUT_02_0_SECURE                        0x0
+#define GPIO_H_INPUT_02_0_DUAL                  0x0
+#define GPIO_H_INPUT_02_0_SCR                   GPIO_H_SCR_02_0
+#define GPIO_H_INPUT_02_0_SCRREG                        GPIO_H_SCR_02_0
+#define GPIO_H_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_H_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_H_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_H_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_H_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_H_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_OUTPUT_CONTROL_02_0
+#define GPIO_H_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1424c)
+#define GPIO_H_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_H_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_H_OUTPUT_CONTROL_02_0_SCR                  GPIO_H_SCR_02_0
+#define GPIO_H_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_H_SCR_02_0
+#define GPIO_H_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_H_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_H_OUTPUT_VALUE_02_0
+#define GPIO_H_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x14250)
+#define GPIO_H_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_H_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_H_OUTPUT_VALUE_02_0_SCR                    GPIO_H_SCR_02_0
+#define GPIO_H_OUTPUT_VALUE_02_0_SCRREG                         GPIO_H_SCR_02_0
+#define GPIO_H_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_H_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INTERRUPT_CLEAR_02_0
+#define GPIO_H_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x14254)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_H_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_H_INTERRUPT_CLEAR_02_0_SCR                         GPIO_H_SCR_02_0
+#define GPIO_H_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_H_SCR_02_0
+#define GPIO_H_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_H_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14258
+
+// Reserved address 0x1425c
+
+// Register GPIO_H_ENABLE_CONFIG_03_0
+#define GPIO_H_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x14260)
+#define GPIO_H_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_H_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_H_ENABLE_CONFIG_03_0_SCR                   GPIO_H_SCR_03_0
+#define GPIO_H_ENABLE_CONFIG_03_0_SCRREG                        GPIO_H_SCR_03_0
+#define GPIO_H_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_H_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_H_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x14264)
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_H_SCR_03_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_H_SCR_03_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_H_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INPUT_03_0
+#define GPIO_H_INPUT_03_0                       MK_ADDR_CONST(0x14268)
+#define GPIO_H_INPUT_03_0_SECURE                        0x0
+#define GPIO_H_INPUT_03_0_DUAL                  0x0
+#define GPIO_H_INPUT_03_0_SCR                   GPIO_H_SCR_03_0
+#define GPIO_H_INPUT_03_0_SCRREG                        GPIO_H_SCR_03_0
+#define GPIO_H_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_H_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_H_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_H_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_H_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_H_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_OUTPUT_CONTROL_03_0
+#define GPIO_H_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1426c)
+#define GPIO_H_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_H_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_H_OUTPUT_CONTROL_03_0_SCR                  GPIO_H_SCR_03_0
+#define GPIO_H_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_H_SCR_03_0
+#define GPIO_H_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_H_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_H_OUTPUT_VALUE_03_0
+#define GPIO_H_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x14270)
+#define GPIO_H_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_H_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_H_OUTPUT_VALUE_03_0_SCR                    GPIO_H_SCR_03_0
+#define GPIO_H_OUTPUT_VALUE_03_0_SCRREG                         GPIO_H_SCR_03_0
+#define GPIO_H_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_H_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INTERRUPT_CLEAR_03_0
+#define GPIO_H_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x14274)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_H_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_H_INTERRUPT_CLEAR_03_0_SCR                         GPIO_H_SCR_03_0
+#define GPIO_H_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_H_SCR_03_0
+#define GPIO_H_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_H_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14278
+
+// Reserved address 0x1427c
+
+// Register GPIO_H_ENABLE_CONFIG_04_0
+#define GPIO_H_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x14280)
+#define GPIO_H_ENABLE_CONFIG_04_0_SECURE                        0x0
+#define GPIO_H_ENABLE_CONFIG_04_0_DUAL                  0x0
+#define GPIO_H_ENABLE_CONFIG_04_0_SCR                   GPIO_H_SCR_04_0
+#define GPIO_H_ENABLE_CONFIG_04_0_SCRREG                        GPIO_H_SCR_04_0
+#define GPIO_H_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
+#define GPIO_H_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
+#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_H_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x14284)
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_H_SCR_04_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_H_SCR_04_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_H_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INPUT_04_0
+#define GPIO_H_INPUT_04_0                       MK_ADDR_CONST(0x14288)
+#define GPIO_H_INPUT_04_0_SECURE                        0x0
+#define GPIO_H_INPUT_04_0_DUAL                  0x0
+#define GPIO_H_INPUT_04_0_SCR                   GPIO_H_SCR_04_0
+#define GPIO_H_INPUT_04_0_SCRREG                        GPIO_H_SCR_04_0
+#define GPIO_H_INPUT_04_0_WORD_COUNT                    0x1
+#define GPIO_H_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_H_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_H_INPUT_04_0_GPIO_IN_RANGE                 0:0
+#define GPIO_H_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_H_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_OUTPUT_CONTROL_04_0
+#define GPIO_H_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1428c)
+#define GPIO_H_OUTPUT_CONTROL_04_0_SECURE                       0x0
+#define GPIO_H_OUTPUT_CONTROL_04_0_DUAL                         0x0
+#define GPIO_H_OUTPUT_CONTROL_04_0_SCR                  GPIO_H_SCR_04_0
+#define GPIO_H_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_H_SCR_04_0
+#define GPIO_H_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
+#define GPIO_H_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_H_OUTPUT_VALUE_04_0
+#define GPIO_H_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x14290)
+#define GPIO_H_OUTPUT_VALUE_04_0_SECURE                         0x0
+#define GPIO_H_OUTPUT_VALUE_04_0_DUAL                   0x0
+#define GPIO_H_OUTPUT_VALUE_04_0_SCR                    GPIO_H_SCR_04_0
+#define GPIO_H_OUTPUT_VALUE_04_0_SCRREG                         GPIO_H_SCR_04_0
+#define GPIO_H_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
+#define GPIO_H_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INTERRUPT_CLEAR_04_0
+#define GPIO_H_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x14294)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_SECURE                      0x0
+#define GPIO_H_INTERRUPT_CLEAR_04_0_DUAL                        0x0
+#define GPIO_H_INTERRUPT_CLEAR_04_0_SCR                         GPIO_H_SCR_04_0
+#define GPIO_H_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_H_SCR_04_0
+#define GPIO_H_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
+#define GPIO_H_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14298
+
+// Reserved address 0x1429c
+
+// Register GPIO_H_ENABLE_CONFIG_05_0
+#define GPIO_H_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x142a0)
+#define GPIO_H_ENABLE_CONFIG_05_0_SECURE                        0x0
+#define GPIO_H_ENABLE_CONFIG_05_0_DUAL                  0x0
+#define GPIO_H_ENABLE_CONFIG_05_0_SCR                   GPIO_H_SCR_05_0
+#define GPIO_H_ENABLE_CONFIG_05_0_SCRREG                        GPIO_H_SCR_05_0
+#define GPIO_H_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
+#define GPIO_H_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
+#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_H_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x142a4)
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_H_SCR_05_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_H_SCR_05_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_H_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INPUT_05_0
+#define GPIO_H_INPUT_05_0                       MK_ADDR_CONST(0x142a8)
+#define GPIO_H_INPUT_05_0_SECURE                        0x0
+#define GPIO_H_INPUT_05_0_DUAL                  0x0
+#define GPIO_H_INPUT_05_0_SCR                   GPIO_H_SCR_05_0
+#define GPIO_H_INPUT_05_0_SCRREG                        GPIO_H_SCR_05_0
+#define GPIO_H_INPUT_05_0_WORD_COUNT                    0x1
+#define GPIO_H_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_H_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_H_INPUT_05_0_GPIO_IN_RANGE                 0:0
+#define GPIO_H_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_H_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_OUTPUT_CONTROL_05_0
+#define GPIO_H_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x142ac)
+#define GPIO_H_OUTPUT_CONTROL_05_0_SECURE                       0x0
+#define GPIO_H_OUTPUT_CONTROL_05_0_DUAL                         0x0
+#define GPIO_H_OUTPUT_CONTROL_05_0_SCR                  GPIO_H_SCR_05_0
+#define GPIO_H_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_H_SCR_05_0
+#define GPIO_H_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
+#define GPIO_H_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_H_OUTPUT_VALUE_05_0
+#define GPIO_H_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x142b0)
+#define GPIO_H_OUTPUT_VALUE_05_0_SECURE                         0x0
+#define GPIO_H_OUTPUT_VALUE_05_0_DUAL                   0x0
+#define GPIO_H_OUTPUT_VALUE_05_0_SCR                    GPIO_H_SCR_05_0
+#define GPIO_H_OUTPUT_VALUE_05_0_SCRREG                         GPIO_H_SCR_05_0
+#define GPIO_H_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
+#define GPIO_H_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INTERRUPT_CLEAR_05_0
+#define GPIO_H_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x142b4)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_SECURE                      0x0
+#define GPIO_H_INTERRUPT_CLEAR_05_0_DUAL                        0x0
+#define GPIO_H_INTERRUPT_CLEAR_05_0_SCR                         GPIO_H_SCR_05_0
+#define GPIO_H_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_H_SCR_05_0
+#define GPIO_H_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
+#define GPIO_H_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x142b8
+
+// Reserved address 0x142bc
+
+// Register GPIO_H_ENABLE_CONFIG_06_0
+#define GPIO_H_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x142c0)
+#define GPIO_H_ENABLE_CONFIG_06_0_SECURE                        0x0
+#define GPIO_H_ENABLE_CONFIG_06_0_DUAL                  0x0
+#define GPIO_H_ENABLE_CONFIG_06_0_SCR                   GPIO_H_SCR_06_0
+#define GPIO_H_ENABLE_CONFIG_06_0_SCRREG                        GPIO_H_SCR_06_0
+#define GPIO_H_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
+#define GPIO_H_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
+#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_H_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x142c4)
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_H_SCR_06_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_H_SCR_06_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_H_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INPUT_06_0
+#define GPIO_H_INPUT_06_0                       MK_ADDR_CONST(0x142c8)
+#define GPIO_H_INPUT_06_0_SECURE                        0x0
+#define GPIO_H_INPUT_06_0_DUAL                  0x0
+#define GPIO_H_INPUT_06_0_SCR                   GPIO_H_SCR_06_0
+#define GPIO_H_INPUT_06_0_SCRREG                        GPIO_H_SCR_06_0
+#define GPIO_H_INPUT_06_0_WORD_COUNT                    0x1
+#define GPIO_H_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_H_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_H_INPUT_06_0_GPIO_IN_RANGE                 0:0
+#define GPIO_H_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_H_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_OUTPUT_CONTROL_06_0
+#define GPIO_H_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x142cc)
+#define GPIO_H_OUTPUT_CONTROL_06_0_SECURE                       0x0
+#define GPIO_H_OUTPUT_CONTROL_06_0_DUAL                         0x0
+#define GPIO_H_OUTPUT_CONTROL_06_0_SCR                  GPIO_H_SCR_06_0
+#define GPIO_H_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_H_SCR_06_0
+#define GPIO_H_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
+#define GPIO_H_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_H_OUTPUT_VALUE_06_0
+#define GPIO_H_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x142d0)
+#define GPIO_H_OUTPUT_VALUE_06_0_SECURE                         0x0
+#define GPIO_H_OUTPUT_VALUE_06_0_DUAL                   0x0
+#define GPIO_H_OUTPUT_VALUE_06_0_SCR                    GPIO_H_SCR_06_0
+#define GPIO_H_OUTPUT_VALUE_06_0_SCRREG                         GPIO_H_SCR_06_0
+#define GPIO_H_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
+#define GPIO_H_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INTERRUPT_CLEAR_06_0
+#define GPIO_H_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x142d4)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_SECURE                      0x0
+#define GPIO_H_INTERRUPT_CLEAR_06_0_DUAL                        0x0
+#define GPIO_H_INTERRUPT_CLEAR_06_0_SCR                         GPIO_H_SCR_06_0
+#define GPIO_H_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_H_SCR_06_0
+#define GPIO_H_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
+#define GPIO_H_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x142d8
+
+// Reserved address 0x142dc
+
+// Register GPIO_H_ENABLE_CONFIG_07_0
+#define GPIO_H_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x142e0)
+#define GPIO_H_ENABLE_CONFIG_07_0_SECURE                        0x0
+#define GPIO_H_ENABLE_CONFIG_07_0_DUAL                  0x0
+#define GPIO_H_ENABLE_CONFIG_07_0_SCR                   GPIO_H_SCR_07_0
+#define GPIO_H_ENABLE_CONFIG_07_0_SCRREG                        GPIO_H_SCR_07_0
+#define GPIO_H_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
+#define GPIO_H_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
+#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_H_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_H_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x142e4)
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_H_SCR_07_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_H_SCR_07_0
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_H_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INPUT_07_0
+#define GPIO_H_INPUT_07_0                       MK_ADDR_CONST(0x142e8)
+#define GPIO_H_INPUT_07_0_SECURE                        0x0
+#define GPIO_H_INPUT_07_0_DUAL                  0x0
+#define GPIO_H_INPUT_07_0_SCR                   GPIO_H_SCR_07_0
+#define GPIO_H_INPUT_07_0_SCRREG                        GPIO_H_SCR_07_0
+#define GPIO_H_INPUT_07_0_WORD_COUNT                    0x1
+#define GPIO_H_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_H_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_H_INPUT_07_0_GPIO_IN_RANGE                 0:0
+#define GPIO_H_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_H_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_H_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_H_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_OUTPUT_CONTROL_07_0
+#define GPIO_H_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x142ec)
+#define GPIO_H_OUTPUT_CONTROL_07_0_SECURE                       0x0
+#define GPIO_H_OUTPUT_CONTROL_07_0_DUAL                         0x0
+#define GPIO_H_OUTPUT_CONTROL_07_0_SCR                  GPIO_H_SCR_07_0
+#define GPIO_H_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_H_SCR_07_0
+#define GPIO_H_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
+#define GPIO_H_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_H_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_H_OUTPUT_VALUE_07_0
+#define GPIO_H_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x142f0)
+#define GPIO_H_OUTPUT_VALUE_07_0_SECURE                         0x0
+#define GPIO_H_OUTPUT_VALUE_07_0_DUAL                   0x0
+#define GPIO_H_OUTPUT_VALUE_07_0_SCR                    GPIO_H_SCR_07_0
+#define GPIO_H_OUTPUT_VALUE_07_0_SCRREG                         GPIO_H_SCR_07_0
+#define GPIO_H_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
+#define GPIO_H_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_H_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INTERRUPT_CLEAR_07_0
+#define GPIO_H_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x142f4)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_SECURE                      0x0
+#define GPIO_H_INTERRUPT_CLEAR_07_0_DUAL                        0x0
+#define GPIO_H_INTERRUPT_CLEAR_07_0_SCR                         GPIO_H_SCR_07_0
+#define GPIO_H_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_H_SCR_07_0
+#define GPIO_H_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
+#define GPIO_H_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_H_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x142f8
+
+// Reserved address 0x142fc
+
+// Register GPIO_H_INTERRUPT_STATUS_G0_0
+#define GPIO_H_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x14300)
+#define GPIO_H_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_H_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_H_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_H_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_H_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_H_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INTERRUPT_STATUS_G1_0
+#define GPIO_H_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x14304)
+#define GPIO_H_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_H_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_H_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_H_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_H_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_H_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INTERRUPT_STATUS_G2_0
+#define GPIO_H_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x14308)
+#define GPIO_H_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_H_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_H_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_H_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_H_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_H_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INTERRUPT_STATUS_G3_0
+#define GPIO_H_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1430c)
+#define GPIO_H_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_H_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_H_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_H_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_H_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_H_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INTERRUPT_STATUS_G4_0
+#define GPIO_H_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x14310)
+#define GPIO_H_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_H_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_H_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_H_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_H_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_H_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INTERRUPT_STATUS_G5_0
+#define GPIO_H_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x14314)
+#define GPIO_H_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_H_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_H_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_H_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_H_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_H_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INTERRUPT_STATUS_G6_0
+#define GPIO_H_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x14318)
+#define GPIO_H_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_H_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_H_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_H_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_H_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_H_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_H_INTERRUPT_STATUS_G7_0
+#define GPIO_H_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1431c)
+#define GPIO_H_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_H_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_H_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_H_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_H_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_H_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_H_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x14320
+
+// Reserved address 0x14324
+
+// Reserved address 0x14328
+
+// Reserved address 0x1432c
+
+// Reserved address 0x14330
+
+// Reserved address 0x14334
+
+// Reserved address 0x14338
+
+// Reserved address 0x1433c
+
+// Reserved address 0x14340
+
+// Reserved address 0x14344
+
+// Reserved address 0x14348
+
+// Reserved address 0x1434c
+
+// Reserved address 0x14350
+
+// Reserved address 0x14354
+
+// Reserved address 0x14358
+
+// Reserved address 0x1435c
+
+// Reserved address 0x14360
+
+// Reserved address 0x14364
+
+// Reserved address 0x14368
+
+// Reserved address 0x1436c
+
+// Reserved address 0x14370
+
+// Reserved address 0x14374
+
+// Reserved address 0x14378
+
+// Reserved address 0x1437c
+
+// Reserved address 0x14380
+
+// Reserved address 0x14384
+
+// Reserved address 0x14388
+
+// Reserved address 0x1438c
+
+// Reserved address 0x14390
+
+// Reserved address 0x14394
+
+// Reserved address 0x14398
+
+// Reserved address 0x1439c
+
+// Reserved address 0x143a0
+
+// Reserved address 0x143a4
+
+// Reserved address 0x143a8
+
+// Reserved address 0x143ac
+
+// Reserved address 0x143b0
+
+// Reserved address 0x143b4
+
+// Reserved address 0x143b8
+
+// Reserved address 0x143bc
+
+// Reserved address 0x143c0
+
+// Reserved address 0x143c4
+
+// Reserved address 0x143c8
+
+// Reserved address 0x143cc
+
+// Reserved address 0x143d0
+
+// Reserved address 0x143d4
+
+// Reserved address 0x143d8
+
+// Reserved address 0x143dc
+
+// Reserved address 0x143e0
+
+// Reserved address 0x143e4
+
+// Reserved address 0x143e8
+
+// Reserved address 0x143ec
+
+// Reserved address 0x143f0
+
+// Reserved address 0x143f4
+
+// Reserved address 0x143f8
+
+// Reserved address 0x143fc
+
+// Register GPIO_I_ENABLE_CONFIG_00_0
+#define GPIO_I_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x14400)
+#define GPIO_I_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_I_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_I_ENABLE_CONFIG_00_0_SCR                   GPIO_I_SCR_00_0
+#define GPIO_I_ENABLE_CONFIG_00_0_SCRREG                        GPIO_I_SCR_00_0
+#define GPIO_I_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_I_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_I_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x14404)
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_I_SCR_00_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_I_SCR_00_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_I_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INPUT_00_0
+#define GPIO_I_INPUT_00_0                       MK_ADDR_CONST(0x14408)
+#define GPIO_I_INPUT_00_0_SECURE                        0x0
+#define GPIO_I_INPUT_00_0_DUAL                  0x0
+#define GPIO_I_INPUT_00_0_SCR                   GPIO_I_SCR_00_0
+#define GPIO_I_INPUT_00_0_SCRREG                        GPIO_I_SCR_00_0
+#define GPIO_I_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_I_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_I_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_I_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_I_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_I_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_OUTPUT_CONTROL_00_0
+#define GPIO_I_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1440c)
+#define GPIO_I_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_I_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_I_OUTPUT_CONTROL_00_0_SCR                  GPIO_I_SCR_00_0
+#define GPIO_I_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_I_SCR_00_0
+#define GPIO_I_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_I_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_I_OUTPUT_VALUE_00_0
+#define GPIO_I_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x14410)
+#define GPIO_I_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_I_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_I_OUTPUT_VALUE_00_0_SCR                    GPIO_I_SCR_00_0
+#define GPIO_I_OUTPUT_VALUE_00_0_SCRREG                         GPIO_I_SCR_00_0
+#define GPIO_I_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_I_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INTERRUPT_CLEAR_00_0
+#define GPIO_I_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x14414)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_I_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_I_INTERRUPT_CLEAR_00_0_SCR                         GPIO_I_SCR_00_0
+#define GPIO_I_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_I_SCR_00_0
+#define GPIO_I_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_I_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14418
+
+// Reserved address 0x1441c
+
+// Register GPIO_I_ENABLE_CONFIG_01_0
+#define GPIO_I_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x14420)
+#define GPIO_I_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_I_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_I_ENABLE_CONFIG_01_0_SCR                   GPIO_I_SCR_01_0
+#define GPIO_I_ENABLE_CONFIG_01_0_SCRREG                        GPIO_I_SCR_01_0
+#define GPIO_I_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_I_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_I_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x14424)
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_I_SCR_01_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_I_SCR_01_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_I_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INPUT_01_0
+#define GPIO_I_INPUT_01_0                       MK_ADDR_CONST(0x14428)
+#define GPIO_I_INPUT_01_0_SECURE                        0x0
+#define GPIO_I_INPUT_01_0_DUAL                  0x0
+#define GPIO_I_INPUT_01_0_SCR                   GPIO_I_SCR_01_0
+#define GPIO_I_INPUT_01_0_SCRREG                        GPIO_I_SCR_01_0
+#define GPIO_I_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_I_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_I_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_I_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_I_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_I_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_OUTPUT_CONTROL_01_0
+#define GPIO_I_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1442c)
+#define GPIO_I_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_I_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_I_OUTPUT_CONTROL_01_0_SCR                  GPIO_I_SCR_01_0
+#define GPIO_I_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_I_SCR_01_0
+#define GPIO_I_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_I_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_I_OUTPUT_VALUE_01_0
+#define GPIO_I_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x14430)
+#define GPIO_I_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_I_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_I_OUTPUT_VALUE_01_0_SCR                    GPIO_I_SCR_01_0
+#define GPIO_I_OUTPUT_VALUE_01_0_SCRREG                         GPIO_I_SCR_01_0
+#define GPIO_I_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_I_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INTERRUPT_CLEAR_01_0
+#define GPIO_I_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x14434)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_I_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_I_INTERRUPT_CLEAR_01_0_SCR                         GPIO_I_SCR_01_0
+#define GPIO_I_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_I_SCR_01_0
+#define GPIO_I_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_I_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14438
+
+// Reserved address 0x1443c
+
+// Register GPIO_I_ENABLE_CONFIG_02_0
+#define GPIO_I_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x14440)
+#define GPIO_I_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_I_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_I_ENABLE_CONFIG_02_0_SCR                   GPIO_I_SCR_02_0
+#define GPIO_I_ENABLE_CONFIG_02_0_SCRREG                        GPIO_I_SCR_02_0
+#define GPIO_I_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_I_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_I_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x14444)
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_I_SCR_02_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_I_SCR_02_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_I_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INPUT_02_0
+#define GPIO_I_INPUT_02_0                       MK_ADDR_CONST(0x14448)
+#define GPIO_I_INPUT_02_0_SECURE                        0x0
+#define GPIO_I_INPUT_02_0_DUAL                  0x0
+#define GPIO_I_INPUT_02_0_SCR                   GPIO_I_SCR_02_0
+#define GPIO_I_INPUT_02_0_SCRREG                        GPIO_I_SCR_02_0
+#define GPIO_I_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_I_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_I_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_I_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_I_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_I_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_OUTPUT_CONTROL_02_0
+#define GPIO_I_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1444c)
+#define GPIO_I_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_I_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_I_OUTPUT_CONTROL_02_0_SCR                  GPIO_I_SCR_02_0
+#define GPIO_I_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_I_SCR_02_0
+#define GPIO_I_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_I_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_I_OUTPUT_VALUE_02_0
+#define GPIO_I_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x14450)
+#define GPIO_I_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_I_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_I_OUTPUT_VALUE_02_0_SCR                    GPIO_I_SCR_02_0
+#define GPIO_I_OUTPUT_VALUE_02_0_SCRREG                         GPIO_I_SCR_02_0
+#define GPIO_I_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_I_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INTERRUPT_CLEAR_02_0
+#define GPIO_I_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x14454)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_I_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_I_INTERRUPT_CLEAR_02_0_SCR                         GPIO_I_SCR_02_0
+#define GPIO_I_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_I_SCR_02_0
+#define GPIO_I_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_I_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14458
+
+// Reserved address 0x1445c
+
+// Register GPIO_I_ENABLE_CONFIG_03_0
+#define GPIO_I_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x14460)
+#define GPIO_I_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_I_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_I_ENABLE_CONFIG_03_0_SCR                   GPIO_I_SCR_03_0
+#define GPIO_I_ENABLE_CONFIG_03_0_SCRREG                        GPIO_I_SCR_03_0
+#define GPIO_I_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_I_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_I_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x14464)
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_I_SCR_03_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_I_SCR_03_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_I_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INPUT_03_0
+#define GPIO_I_INPUT_03_0                       MK_ADDR_CONST(0x14468)
+#define GPIO_I_INPUT_03_0_SECURE                        0x0
+#define GPIO_I_INPUT_03_0_DUAL                  0x0
+#define GPIO_I_INPUT_03_0_SCR                   GPIO_I_SCR_03_0
+#define GPIO_I_INPUT_03_0_SCRREG                        GPIO_I_SCR_03_0
+#define GPIO_I_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_I_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_I_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_I_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_I_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_I_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_OUTPUT_CONTROL_03_0
+#define GPIO_I_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1446c)
+#define GPIO_I_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_I_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_I_OUTPUT_CONTROL_03_0_SCR                  GPIO_I_SCR_03_0
+#define GPIO_I_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_I_SCR_03_0
+#define GPIO_I_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_I_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_I_OUTPUT_VALUE_03_0
+#define GPIO_I_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x14470)
+#define GPIO_I_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_I_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_I_OUTPUT_VALUE_03_0_SCR                    GPIO_I_SCR_03_0
+#define GPIO_I_OUTPUT_VALUE_03_0_SCRREG                         GPIO_I_SCR_03_0
+#define GPIO_I_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_I_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INTERRUPT_CLEAR_03_0
+#define GPIO_I_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x14474)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_I_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_I_INTERRUPT_CLEAR_03_0_SCR                         GPIO_I_SCR_03_0
+#define GPIO_I_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_I_SCR_03_0
+#define GPIO_I_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_I_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14478
+
+// Reserved address 0x1447c
+
+// Register GPIO_I_ENABLE_CONFIG_04_0
+#define GPIO_I_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x14480)
+#define GPIO_I_ENABLE_CONFIG_04_0_SECURE                        0x0
+#define GPIO_I_ENABLE_CONFIG_04_0_DUAL                  0x0
+#define GPIO_I_ENABLE_CONFIG_04_0_SCR                   GPIO_I_SCR_04_0
+#define GPIO_I_ENABLE_CONFIG_04_0_SCRREG                        GPIO_I_SCR_04_0
+#define GPIO_I_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
+#define GPIO_I_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
+#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_I_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x14484)
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_I_SCR_04_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_I_SCR_04_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_I_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INPUT_04_0
+#define GPIO_I_INPUT_04_0                       MK_ADDR_CONST(0x14488)
+#define GPIO_I_INPUT_04_0_SECURE                        0x0
+#define GPIO_I_INPUT_04_0_DUAL                  0x0
+#define GPIO_I_INPUT_04_0_SCR                   GPIO_I_SCR_04_0
+#define GPIO_I_INPUT_04_0_SCRREG                        GPIO_I_SCR_04_0
+#define GPIO_I_INPUT_04_0_WORD_COUNT                    0x1
+#define GPIO_I_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_I_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_I_INPUT_04_0_GPIO_IN_RANGE                 0:0
+#define GPIO_I_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_I_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_OUTPUT_CONTROL_04_0
+#define GPIO_I_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1448c)
+#define GPIO_I_OUTPUT_CONTROL_04_0_SECURE                       0x0
+#define GPIO_I_OUTPUT_CONTROL_04_0_DUAL                         0x0
+#define GPIO_I_OUTPUT_CONTROL_04_0_SCR                  GPIO_I_SCR_04_0
+#define GPIO_I_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_I_SCR_04_0
+#define GPIO_I_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
+#define GPIO_I_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_I_OUTPUT_VALUE_04_0
+#define GPIO_I_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x14490)
+#define GPIO_I_OUTPUT_VALUE_04_0_SECURE                         0x0
+#define GPIO_I_OUTPUT_VALUE_04_0_DUAL                   0x0
+#define GPIO_I_OUTPUT_VALUE_04_0_SCR                    GPIO_I_SCR_04_0
+#define GPIO_I_OUTPUT_VALUE_04_0_SCRREG                         GPIO_I_SCR_04_0
+#define GPIO_I_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
+#define GPIO_I_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INTERRUPT_CLEAR_04_0
+#define GPIO_I_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x14494)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_SECURE                      0x0
+#define GPIO_I_INTERRUPT_CLEAR_04_0_DUAL                        0x0
+#define GPIO_I_INTERRUPT_CLEAR_04_0_SCR                         GPIO_I_SCR_04_0
+#define GPIO_I_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_I_SCR_04_0
+#define GPIO_I_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
+#define GPIO_I_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x14498
+
+// Reserved address 0x1449c
+
+// Register GPIO_I_ENABLE_CONFIG_05_0
+#define GPIO_I_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x144a0)
+#define GPIO_I_ENABLE_CONFIG_05_0_SECURE                        0x0
+#define GPIO_I_ENABLE_CONFIG_05_0_DUAL                  0x0
+#define GPIO_I_ENABLE_CONFIG_05_0_SCR                   GPIO_I_SCR_05_0
+#define GPIO_I_ENABLE_CONFIG_05_0_SCRREG                        GPIO_I_SCR_05_0
+#define GPIO_I_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
+#define GPIO_I_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
+#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_I_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x144a4)
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_I_SCR_05_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_I_SCR_05_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_I_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INPUT_05_0
+#define GPIO_I_INPUT_05_0                       MK_ADDR_CONST(0x144a8)
+#define GPIO_I_INPUT_05_0_SECURE                        0x0
+#define GPIO_I_INPUT_05_0_DUAL                  0x0
+#define GPIO_I_INPUT_05_0_SCR                   GPIO_I_SCR_05_0
+#define GPIO_I_INPUT_05_0_SCRREG                        GPIO_I_SCR_05_0
+#define GPIO_I_INPUT_05_0_WORD_COUNT                    0x1
+#define GPIO_I_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_I_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_I_INPUT_05_0_GPIO_IN_RANGE                 0:0
+#define GPIO_I_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_I_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_OUTPUT_CONTROL_05_0
+#define GPIO_I_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x144ac)
+#define GPIO_I_OUTPUT_CONTROL_05_0_SECURE                       0x0
+#define GPIO_I_OUTPUT_CONTROL_05_0_DUAL                         0x0
+#define GPIO_I_OUTPUT_CONTROL_05_0_SCR                  GPIO_I_SCR_05_0
+#define GPIO_I_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_I_SCR_05_0
+#define GPIO_I_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
+#define GPIO_I_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_I_OUTPUT_VALUE_05_0
+#define GPIO_I_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x144b0)
+#define GPIO_I_OUTPUT_VALUE_05_0_SECURE                         0x0
+#define GPIO_I_OUTPUT_VALUE_05_0_DUAL                   0x0
+#define GPIO_I_OUTPUT_VALUE_05_0_SCR                    GPIO_I_SCR_05_0
+#define GPIO_I_OUTPUT_VALUE_05_0_SCRREG                         GPIO_I_SCR_05_0
+#define GPIO_I_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
+#define GPIO_I_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INTERRUPT_CLEAR_05_0
+#define GPIO_I_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x144b4)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_SECURE                      0x0
+#define GPIO_I_INTERRUPT_CLEAR_05_0_DUAL                        0x0
+#define GPIO_I_INTERRUPT_CLEAR_05_0_SCR                         GPIO_I_SCR_05_0
+#define GPIO_I_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_I_SCR_05_0
+#define GPIO_I_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
+#define GPIO_I_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x144b8
+
+// Reserved address 0x144bc
+
+// Register GPIO_I_ENABLE_CONFIG_06_0
+#define GPIO_I_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x144c0)
+#define GPIO_I_ENABLE_CONFIG_06_0_SECURE                        0x0
+#define GPIO_I_ENABLE_CONFIG_06_0_DUAL                  0x0
+#define GPIO_I_ENABLE_CONFIG_06_0_SCR                   GPIO_I_SCR_06_0
+#define GPIO_I_ENABLE_CONFIG_06_0_SCRREG                        GPIO_I_SCR_06_0
+#define GPIO_I_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
+#define GPIO_I_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
+#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_I_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_I_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x144c4)
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_I_SCR_06_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_I_SCR_06_0
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_I_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INPUT_06_0
+#define GPIO_I_INPUT_06_0                       MK_ADDR_CONST(0x144c8)
+#define GPIO_I_INPUT_06_0_SECURE                        0x0
+#define GPIO_I_INPUT_06_0_DUAL                  0x0
+#define GPIO_I_INPUT_06_0_SCR                   GPIO_I_SCR_06_0
+#define GPIO_I_INPUT_06_0_SCRREG                        GPIO_I_SCR_06_0
+#define GPIO_I_INPUT_06_0_WORD_COUNT                    0x1
+#define GPIO_I_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_I_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_I_INPUT_06_0_GPIO_IN_RANGE                 0:0
+#define GPIO_I_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_I_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_I_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_I_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_OUTPUT_CONTROL_06_0
+#define GPIO_I_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x144cc)
+#define GPIO_I_OUTPUT_CONTROL_06_0_SECURE                       0x0
+#define GPIO_I_OUTPUT_CONTROL_06_0_DUAL                         0x0
+#define GPIO_I_OUTPUT_CONTROL_06_0_SCR                  GPIO_I_SCR_06_0
+#define GPIO_I_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_I_SCR_06_0
+#define GPIO_I_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
+#define GPIO_I_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_I_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_I_OUTPUT_VALUE_06_0
+#define GPIO_I_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x144d0)
+#define GPIO_I_OUTPUT_VALUE_06_0_SECURE                         0x0
+#define GPIO_I_OUTPUT_VALUE_06_0_DUAL                   0x0
+#define GPIO_I_OUTPUT_VALUE_06_0_SCR                    GPIO_I_SCR_06_0
+#define GPIO_I_OUTPUT_VALUE_06_0_SCRREG                         GPIO_I_SCR_06_0
+#define GPIO_I_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
+#define GPIO_I_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_I_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INTERRUPT_CLEAR_06_0
+#define GPIO_I_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x144d4)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_SECURE                      0x0
+#define GPIO_I_INTERRUPT_CLEAR_06_0_DUAL                        0x0
+#define GPIO_I_INTERRUPT_CLEAR_06_0_SCR                         GPIO_I_SCR_06_0
+#define GPIO_I_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_I_SCR_06_0
+#define GPIO_I_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
+#define GPIO_I_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_I_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x144d8
+
+// Reserved address 0x144dc
+
+// Reserved address 0x144e0
+
+// Reserved address 0x144e4
+
+// Reserved address 0x144e8
+
+// Reserved address 0x144ec
+
+// Reserved address 0x144f0
+
+// Reserved address 0x144f4
+
+// Reserved address 0x144f8
+
+// Reserved address 0x144fc
+
+// Register GPIO_I_INTERRUPT_STATUS_G0_0
+#define GPIO_I_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x14500)
+#define GPIO_I_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_I_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_I_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_I_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_I_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_I_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x7f, GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
+#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(6)
+#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INTERRUPT_STATUS_G1_0
+#define GPIO_I_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x14504)
+#define GPIO_I_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_I_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_I_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_I_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_I_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_I_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x7f, GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
+#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(6)
+#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INTERRUPT_STATUS_G2_0
+#define GPIO_I_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x14508)
+#define GPIO_I_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_I_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_I_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_I_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_I_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_I_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x7f, GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
+#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(6)
+#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INTERRUPT_STATUS_G3_0
+#define GPIO_I_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1450c)
+#define GPIO_I_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_I_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_I_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_I_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_I_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_I_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x7f, GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
+#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(6)
+#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INTERRUPT_STATUS_G4_0
+#define GPIO_I_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x14510)
+#define GPIO_I_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_I_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_I_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_I_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_I_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_I_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x7f, GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
+#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(6)
+#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INTERRUPT_STATUS_G5_0
+#define GPIO_I_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x14514)
+#define GPIO_I_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_I_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_I_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_I_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_I_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_I_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x7f, GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
+#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(6)
+#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INTERRUPT_STATUS_G6_0
+#define GPIO_I_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x14518)
+#define GPIO_I_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_I_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_I_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_I_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_I_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_I_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x7f, GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
+#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(6)
+#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_I_INTERRUPT_STATUS_G7_0
+#define GPIO_I_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1451c)
+#define GPIO_I_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_I_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_I_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_I_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_I_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_I_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x7f, GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        6:0
+#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(6)
+#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
+#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_I_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x14520
+
+// Reserved address 0x14524
+
+// Reserved address 0x14528
+
+// Reserved address 0x1452c
+
+// Reserved address 0x14530
+
+// Reserved address 0x14534
+
+// Reserved address 0x14538
+
+// Reserved address 0x1453c
+
+// Reserved address 0x14540
+
+// Reserved address 0x14544
+
+// Reserved address 0x14548
+
+// Reserved address 0x1454c
+
+// Reserved address 0x14550
+
+// Reserved address 0x14554
+
+// Reserved address 0x14558
+
+// Reserved address 0x1455c
+
+// Reserved address 0x14560
+
+// Reserved address 0x14564
+
+// Reserved address 0x14568
+
+// Reserved address 0x1456c
+
+// Reserved address 0x14570
+
+// Reserved address 0x14574
+
+// Reserved address 0x14578
+
+// Reserved address 0x1457c
+
+// Reserved address 0x14580
+
+// Reserved address 0x14584
+
+// Reserved address 0x14588
+
+// Reserved address 0x1458c
+
+// Reserved address 0x14590
+
+// Reserved address 0x14594
+
+// Reserved address 0x14598
+
+// Reserved address 0x1459c
+
+// Reserved address 0x145a0
+
+// Reserved address 0x145a4
+
+// Reserved address 0x145a8
+
+// Reserved address 0x145ac
+
+// Reserved address 0x145b0
+
+// Reserved address 0x145b4
+
+// Reserved address 0x145b8
+
+// Reserved address 0x145bc
+
+// Reserved address 0x145c0
+
+// Reserved address 0x145c4
+
+// Reserved address 0x145c8
+
+// Reserved address 0x145cc
+
+// Reserved address 0x145d0
+
+// Reserved address 0x145d4
+
+// Reserved address 0x145d8
+
+// Reserved address 0x145dc
+
+// Reserved address 0x145e0
+
+// Reserved address 0x145e4
+
+// Reserved address 0x145e8
+
+// Reserved address 0x145ec
+
+// Reserved address 0x145f0
+
+// Reserved address 0x145f4
+
+// Reserved address 0x145f8
+
+// Reserved address 0x145fc
+
+// Register GPIO_J_ENABLE_CONFIG_00_0
+#define GPIO_J_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x15000)
+#define GPIO_J_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_J_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_J_ENABLE_CONFIG_00_0_SCR                   GPIO_J_SCR_00_0
+#define GPIO_J_ENABLE_CONFIG_00_0_SCRREG                        GPIO_J_SCR_00_0
+#define GPIO_J_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_J_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_J_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x15004)
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_J_SCR_00_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_J_SCR_00_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_J_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INPUT_00_0
+#define GPIO_J_INPUT_00_0                       MK_ADDR_CONST(0x15008)
+#define GPIO_J_INPUT_00_0_SECURE                        0x0
+#define GPIO_J_INPUT_00_0_DUAL                  0x0
+#define GPIO_J_INPUT_00_0_SCR                   GPIO_J_SCR_00_0
+#define GPIO_J_INPUT_00_0_SCRREG                        GPIO_J_SCR_00_0
+#define GPIO_J_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_J_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_J_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_J_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_J_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_J_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_OUTPUT_CONTROL_00_0
+#define GPIO_J_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1500c)
+#define GPIO_J_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_J_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_J_OUTPUT_CONTROL_00_0_SCR                  GPIO_J_SCR_00_0
+#define GPIO_J_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_J_SCR_00_0
+#define GPIO_J_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_J_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_J_OUTPUT_VALUE_00_0
+#define GPIO_J_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x15010)
+#define GPIO_J_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_J_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_J_OUTPUT_VALUE_00_0_SCR                    GPIO_J_SCR_00_0
+#define GPIO_J_OUTPUT_VALUE_00_0_SCRREG                         GPIO_J_SCR_00_0
+#define GPIO_J_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_J_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INTERRUPT_CLEAR_00_0
+#define GPIO_J_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x15014)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_J_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_J_INTERRUPT_CLEAR_00_0_SCR                         GPIO_J_SCR_00_0
+#define GPIO_J_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_J_SCR_00_0
+#define GPIO_J_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_J_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15018
+
+// Reserved address 0x1501c
+
+// Register GPIO_J_ENABLE_CONFIG_01_0
+#define GPIO_J_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x15020)
+#define GPIO_J_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_J_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_J_ENABLE_CONFIG_01_0_SCR                   GPIO_J_SCR_01_0
+#define GPIO_J_ENABLE_CONFIG_01_0_SCRREG                        GPIO_J_SCR_01_0
+#define GPIO_J_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_J_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_J_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x15024)
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_J_SCR_01_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_J_SCR_01_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_J_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INPUT_01_0
+#define GPIO_J_INPUT_01_0                       MK_ADDR_CONST(0x15028)
+#define GPIO_J_INPUT_01_0_SECURE                        0x0
+#define GPIO_J_INPUT_01_0_DUAL                  0x0
+#define GPIO_J_INPUT_01_0_SCR                   GPIO_J_SCR_01_0
+#define GPIO_J_INPUT_01_0_SCRREG                        GPIO_J_SCR_01_0
+#define GPIO_J_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_J_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_J_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_J_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_J_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_J_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_OUTPUT_CONTROL_01_0
+#define GPIO_J_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1502c)
+#define GPIO_J_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_J_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_J_OUTPUT_CONTROL_01_0_SCR                  GPIO_J_SCR_01_0
+#define GPIO_J_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_J_SCR_01_0
+#define GPIO_J_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_J_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_J_OUTPUT_VALUE_01_0
+#define GPIO_J_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x15030)
+#define GPIO_J_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_J_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_J_OUTPUT_VALUE_01_0_SCR                    GPIO_J_SCR_01_0
+#define GPIO_J_OUTPUT_VALUE_01_0_SCRREG                         GPIO_J_SCR_01_0
+#define GPIO_J_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_J_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INTERRUPT_CLEAR_01_0
+#define GPIO_J_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x15034)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_J_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_J_INTERRUPT_CLEAR_01_0_SCR                         GPIO_J_SCR_01_0
+#define GPIO_J_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_J_SCR_01_0
+#define GPIO_J_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_J_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15038
+
+// Reserved address 0x1503c
+
+// Register GPIO_J_ENABLE_CONFIG_02_0
+#define GPIO_J_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x15040)
+#define GPIO_J_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_J_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_J_ENABLE_CONFIG_02_0_SCR                   GPIO_J_SCR_02_0
+#define GPIO_J_ENABLE_CONFIG_02_0_SCRREG                        GPIO_J_SCR_02_0
+#define GPIO_J_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_J_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_J_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x15044)
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_J_SCR_02_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_J_SCR_02_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_J_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INPUT_02_0
+#define GPIO_J_INPUT_02_0                       MK_ADDR_CONST(0x15048)
+#define GPIO_J_INPUT_02_0_SECURE                        0x0
+#define GPIO_J_INPUT_02_0_DUAL                  0x0
+#define GPIO_J_INPUT_02_0_SCR                   GPIO_J_SCR_02_0
+#define GPIO_J_INPUT_02_0_SCRREG                        GPIO_J_SCR_02_0
+#define GPIO_J_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_J_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_J_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_J_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_J_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_J_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_OUTPUT_CONTROL_02_0
+#define GPIO_J_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1504c)
+#define GPIO_J_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_J_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_J_OUTPUT_CONTROL_02_0_SCR                  GPIO_J_SCR_02_0
+#define GPIO_J_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_J_SCR_02_0
+#define GPIO_J_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_J_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_J_OUTPUT_VALUE_02_0
+#define GPIO_J_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x15050)
+#define GPIO_J_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_J_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_J_OUTPUT_VALUE_02_0_SCR                    GPIO_J_SCR_02_0
+#define GPIO_J_OUTPUT_VALUE_02_0_SCRREG                         GPIO_J_SCR_02_0
+#define GPIO_J_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_J_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INTERRUPT_CLEAR_02_0
+#define GPIO_J_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x15054)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_J_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_J_INTERRUPT_CLEAR_02_0_SCR                         GPIO_J_SCR_02_0
+#define GPIO_J_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_J_SCR_02_0
+#define GPIO_J_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_J_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15058
+
+// Reserved address 0x1505c
+
+// Register GPIO_J_ENABLE_CONFIG_03_0
+#define GPIO_J_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x15060)
+#define GPIO_J_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_J_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_J_ENABLE_CONFIG_03_0_SCR                   GPIO_J_SCR_03_0
+#define GPIO_J_ENABLE_CONFIG_03_0_SCRREG                        GPIO_J_SCR_03_0
+#define GPIO_J_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_J_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_J_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x15064)
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_J_SCR_03_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_J_SCR_03_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_J_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INPUT_03_0
+#define GPIO_J_INPUT_03_0                       MK_ADDR_CONST(0x15068)
+#define GPIO_J_INPUT_03_0_SECURE                        0x0
+#define GPIO_J_INPUT_03_0_DUAL                  0x0
+#define GPIO_J_INPUT_03_0_SCR                   GPIO_J_SCR_03_0
+#define GPIO_J_INPUT_03_0_SCRREG                        GPIO_J_SCR_03_0
+#define GPIO_J_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_J_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_J_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_J_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_J_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_J_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_OUTPUT_CONTROL_03_0
+#define GPIO_J_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1506c)
+#define GPIO_J_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_J_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_J_OUTPUT_CONTROL_03_0_SCR                  GPIO_J_SCR_03_0
+#define GPIO_J_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_J_SCR_03_0
+#define GPIO_J_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_J_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_J_OUTPUT_VALUE_03_0
+#define GPIO_J_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x15070)
+#define GPIO_J_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_J_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_J_OUTPUT_VALUE_03_0_SCR                    GPIO_J_SCR_03_0
+#define GPIO_J_OUTPUT_VALUE_03_0_SCRREG                         GPIO_J_SCR_03_0
+#define GPIO_J_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_J_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INTERRUPT_CLEAR_03_0
+#define GPIO_J_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x15074)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_J_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_J_INTERRUPT_CLEAR_03_0_SCR                         GPIO_J_SCR_03_0
+#define GPIO_J_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_J_SCR_03_0
+#define GPIO_J_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_J_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15078
+
+// Reserved address 0x1507c
+
+// Register GPIO_J_ENABLE_CONFIG_04_0
+#define GPIO_J_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x15080)
+#define GPIO_J_ENABLE_CONFIG_04_0_SECURE                        0x0
+#define GPIO_J_ENABLE_CONFIG_04_0_DUAL                  0x0
+#define GPIO_J_ENABLE_CONFIG_04_0_SCR                   GPIO_J_SCR_04_0
+#define GPIO_J_ENABLE_CONFIG_04_0_SCRREG                        GPIO_J_SCR_04_0
+#define GPIO_J_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
+#define GPIO_J_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
+#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_J_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x15084)
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_J_SCR_04_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_J_SCR_04_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_J_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INPUT_04_0
+#define GPIO_J_INPUT_04_0                       MK_ADDR_CONST(0x15088)
+#define GPIO_J_INPUT_04_0_SECURE                        0x0
+#define GPIO_J_INPUT_04_0_DUAL                  0x0
+#define GPIO_J_INPUT_04_0_SCR                   GPIO_J_SCR_04_0
+#define GPIO_J_INPUT_04_0_SCRREG                        GPIO_J_SCR_04_0
+#define GPIO_J_INPUT_04_0_WORD_COUNT                    0x1
+#define GPIO_J_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_J_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_J_INPUT_04_0_GPIO_IN_RANGE                 0:0
+#define GPIO_J_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_J_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_OUTPUT_CONTROL_04_0
+#define GPIO_J_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1508c)
+#define GPIO_J_OUTPUT_CONTROL_04_0_SECURE                       0x0
+#define GPIO_J_OUTPUT_CONTROL_04_0_DUAL                         0x0
+#define GPIO_J_OUTPUT_CONTROL_04_0_SCR                  GPIO_J_SCR_04_0
+#define GPIO_J_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_J_SCR_04_0
+#define GPIO_J_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
+#define GPIO_J_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_J_OUTPUT_VALUE_04_0
+#define GPIO_J_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x15090)
+#define GPIO_J_OUTPUT_VALUE_04_0_SECURE                         0x0
+#define GPIO_J_OUTPUT_VALUE_04_0_DUAL                   0x0
+#define GPIO_J_OUTPUT_VALUE_04_0_SCR                    GPIO_J_SCR_04_0
+#define GPIO_J_OUTPUT_VALUE_04_0_SCRREG                         GPIO_J_SCR_04_0
+#define GPIO_J_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
+#define GPIO_J_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INTERRUPT_CLEAR_04_0
+#define GPIO_J_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x15094)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_SECURE                      0x0
+#define GPIO_J_INTERRUPT_CLEAR_04_0_DUAL                        0x0
+#define GPIO_J_INTERRUPT_CLEAR_04_0_SCR                         GPIO_J_SCR_04_0
+#define GPIO_J_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_J_SCR_04_0
+#define GPIO_J_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
+#define GPIO_J_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15098
+
+// Reserved address 0x1509c
+
+// Register GPIO_J_ENABLE_CONFIG_05_0
+#define GPIO_J_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x150a0)
+#define GPIO_J_ENABLE_CONFIG_05_0_SECURE                        0x0
+#define GPIO_J_ENABLE_CONFIG_05_0_DUAL                  0x0
+#define GPIO_J_ENABLE_CONFIG_05_0_SCR                   GPIO_J_SCR_05_0
+#define GPIO_J_ENABLE_CONFIG_05_0_SCRREG                        GPIO_J_SCR_05_0
+#define GPIO_J_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
+#define GPIO_J_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
+#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_J_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_J_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x150a4)
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_J_SCR_05_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_J_SCR_05_0
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_J_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INPUT_05_0
+#define GPIO_J_INPUT_05_0                       MK_ADDR_CONST(0x150a8)
+#define GPIO_J_INPUT_05_0_SECURE                        0x0
+#define GPIO_J_INPUT_05_0_DUAL                  0x0
+#define GPIO_J_INPUT_05_0_SCR                   GPIO_J_SCR_05_0
+#define GPIO_J_INPUT_05_0_SCRREG                        GPIO_J_SCR_05_0
+#define GPIO_J_INPUT_05_0_WORD_COUNT                    0x1
+#define GPIO_J_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_J_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_J_INPUT_05_0_GPIO_IN_RANGE                 0:0
+#define GPIO_J_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_J_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_J_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_J_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_OUTPUT_CONTROL_05_0
+#define GPIO_J_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x150ac)
+#define GPIO_J_OUTPUT_CONTROL_05_0_SECURE                       0x0
+#define GPIO_J_OUTPUT_CONTROL_05_0_DUAL                         0x0
+#define GPIO_J_OUTPUT_CONTROL_05_0_SCR                  GPIO_J_SCR_05_0
+#define GPIO_J_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_J_SCR_05_0
+#define GPIO_J_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
+#define GPIO_J_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_J_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_J_OUTPUT_VALUE_05_0
+#define GPIO_J_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x150b0)
+#define GPIO_J_OUTPUT_VALUE_05_0_SECURE                         0x0
+#define GPIO_J_OUTPUT_VALUE_05_0_DUAL                   0x0
+#define GPIO_J_OUTPUT_VALUE_05_0_SCR                    GPIO_J_SCR_05_0
+#define GPIO_J_OUTPUT_VALUE_05_0_SCRREG                         GPIO_J_SCR_05_0
+#define GPIO_J_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
+#define GPIO_J_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_J_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INTERRUPT_CLEAR_05_0
+#define GPIO_J_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x150b4)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_SECURE                      0x0
+#define GPIO_J_INTERRUPT_CLEAR_05_0_DUAL                        0x0
+#define GPIO_J_INTERRUPT_CLEAR_05_0_SCR                         GPIO_J_SCR_05_0
+#define GPIO_J_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_J_SCR_05_0
+#define GPIO_J_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
+#define GPIO_J_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_J_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x150b8
+
+// Reserved address 0x150bc
+
+// Reserved address 0x150c0
+
+// Reserved address 0x150c4
+
+// Reserved address 0x150c8
+
+// Reserved address 0x150cc
+
+// Reserved address 0x150d0
+
+// Reserved address 0x150d4
+
+// Reserved address 0x150d8
+
+// Reserved address 0x150dc
+
+// Reserved address 0x150e0
+
+// Reserved address 0x150e4
+
+// Reserved address 0x150e8
+
+// Reserved address 0x150ec
+
+// Reserved address 0x150f0
+
+// Reserved address 0x150f4
+
+// Reserved address 0x150f8
+
+// Reserved address 0x150fc
+
+// Register GPIO_J_INTERRUPT_STATUS_G0_0
+#define GPIO_J_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x15100)
+#define GPIO_J_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_J_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_J_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_J_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_J_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_J_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INTERRUPT_STATUS_G1_0
+#define GPIO_J_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x15104)
+#define GPIO_J_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_J_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_J_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_J_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_J_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_J_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INTERRUPT_STATUS_G2_0
+#define GPIO_J_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x15108)
+#define GPIO_J_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_J_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_J_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_J_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_J_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_J_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INTERRUPT_STATUS_G3_0
+#define GPIO_J_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1510c)
+#define GPIO_J_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_J_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_J_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_J_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_J_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_J_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INTERRUPT_STATUS_G4_0
+#define GPIO_J_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x15110)
+#define GPIO_J_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_J_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_J_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_J_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_J_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_J_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INTERRUPT_STATUS_G5_0
+#define GPIO_J_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x15114)
+#define GPIO_J_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_J_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_J_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_J_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_J_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_J_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INTERRUPT_STATUS_G6_0
+#define GPIO_J_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x15118)
+#define GPIO_J_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_J_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_J_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_J_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_J_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_J_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_J_INTERRUPT_STATUS_G7_0
+#define GPIO_J_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1511c)
+#define GPIO_J_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_J_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_J_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_J_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_J_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_J_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_J_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x15120
+
+// Reserved address 0x15124
+
+// Reserved address 0x15128
+
+// Reserved address 0x1512c
+
+// Reserved address 0x15130
+
+// Reserved address 0x15134
+
+// Reserved address 0x15138
+
+// Reserved address 0x1513c
+
+// Reserved address 0x15140
+
+// Reserved address 0x15144
+
+// Reserved address 0x15148
+
+// Reserved address 0x1514c
+
+// Reserved address 0x15150
+
+// Reserved address 0x15154
+
+// Reserved address 0x15158
+
+// Reserved address 0x1515c
+
+// Reserved address 0x15160
+
+// Reserved address 0x15164
+
+// Reserved address 0x15168
+
+// Reserved address 0x1516c
+
+// Reserved address 0x15170
+
+// Reserved address 0x15174
+
+// Reserved address 0x15178
+
+// Reserved address 0x1517c
+
+// Reserved address 0x15180
+
+// Reserved address 0x15184
+
+// Reserved address 0x15188
+
+// Reserved address 0x1518c
+
+// Reserved address 0x15190
+
+// Reserved address 0x15194
+
+// Reserved address 0x15198
+
+// Reserved address 0x1519c
+
+// Reserved address 0x151a0
+
+// Reserved address 0x151a4
+
+// Reserved address 0x151a8
+
+// Reserved address 0x151ac
+
+// Reserved address 0x151b0
+
+// Reserved address 0x151b4
+
+// Reserved address 0x151b8
+
+// Reserved address 0x151bc
+
+// Reserved address 0x151c0
+
+// Reserved address 0x151c4
+
+// Reserved address 0x151c8
+
+// Reserved address 0x151cc
+
+// Reserved address 0x151d0
+
+// Reserved address 0x151d4
+
+// Reserved address 0x151d8
+
+// Reserved address 0x151dc
+
+// Reserved address 0x151e0
+
+// Reserved address 0x151e4
+
+// Reserved address 0x151e8
+
+// Reserved address 0x151ec
+
+// Reserved address 0x151f0
+
+// Reserved address 0x151f4
+
+// Reserved address 0x151f8
+
+// Reserved address 0x151fc
+
+// Register GPIO_C_ENABLE_CONFIG_00_0
+#define GPIO_C_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x15200)
+#define GPIO_C_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_C_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_C_ENABLE_CONFIG_00_0_SCR                   GPIO_C_SCR_00_0
+#define GPIO_C_ENABLE_CONFIG_00_0_SCRREG                        GPIO_C_SCR_00_0
+#define GPIO_C_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_C_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_C_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x15204)
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_C_SCR_00_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_C_SCR_00_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_C_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INPUT_00_0
+#define GPIO_C_INPUT_00_0                       MK_ADDR_CONST(0x15208)
+#define GPIO_C_INPUT_00_0_SECURE                        0x0
+#define GPIO_C_INPUT_00_0_DUAL                  0x0
+#define GPIO_C_INPUT_00_0_SCR                   GPIO_C_SCR_00_0
+#define GPIO_C_INPUT_00_0_SCRREG                        GPIO_C_SCR_00_0
+#define GPIO_C_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_C_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_C_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_C_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_C_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_C_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_OUTPUT_CONTROL_00_0
+#define GPIO_C_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1520c)
+#define GPIO_C_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_C_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_C_OUTPUT_CONTROL_00_0_SCR                  GPIO_C_SCR_00_0
+#define GPIO_C_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_C_SCR_00_0
+#define GPIO_C_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_C_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_C_OUTPUT_VALUE_00_0
+#define GPIO_C_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x15210)
+#define GPIO_C_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_C_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_C_OUTPUT_VALUE_00_0_SCR                    GPIO_C_SCR_00_0
+#define GPIO_C_OUTPUT_VALUE_00_0_SCRREG                         GPIO_C_SCR_00_0
+#define GPIO_C_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_C_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INTERRUPT_CLEAR_00_0
+#define GPIO_C_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x15214)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_C_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_C_INTERRUPT_CLEAR_00_0_SCR                         GPIO_C_SCR_00_0
+#define GPIO_C_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_C_SCR_00_0
+#define GPIO_C_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_C_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15218
+
+// Reserved address 0x1521c
+
+// Register GPIO_C_ENABLE_CONFIG_01_0
+#define GPIO_C_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x15220)
+#define GPIO_C_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_C_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_C_ENABLE_CONFIG_01_0_SCR                   GPIO_C_SCR_01_0
+#define GPIO_C_ENABLE_CONFIG_01_0_SCRREG                        GPIO_C_SCR_01_0
+#define GPIO_C_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_C_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_C_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x15224)
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_C_SCR_01_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_C_SCR_01_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_C_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INPUT_01_0
+#define GPIO_C_INPUT_01_0                       MK_ADDR_CONST(0x15228)
+#define GPIO_C_INPUT_01_0_SECURE                        0x0
+#define GPIO_C_INPUT_01_0_DUAL                  0x0
+#define GPIO_C_INPUT_01_0_SCR                   GPIO_C_SCR_01_0
+#define GPIO_C_INPUT_01_0_SCRREG                        GPIO_C_SCR_01_0
+#define GPIO_C_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_C_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_C_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_C_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_C_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_C_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_OUTPUT_CONTROL_01_0
+#define GPIO_C_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1522c)
+#define GPIO_C_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_C_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_C_OUTPUT_CONTROL_01_0_SCR                  GPIO_C_SCR_01_0
+#define GPIO_C_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_C_SCR_01_0
+#define GPIO_C_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_C_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_C_OUTPUT_VALUE_01_0
+#define GPIO_C_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x15230)
+#define GPIO_C_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_C_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_C_OUTPUT_VALUE_01_0_SCR                    GPIO_C_SCR_01_0
+#define GPIO_C_OUTPUT_VALUE_01_0_SCRREG                         GPIO_C_SCR_01_0
+#define GPIO_C_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_C_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INTERRUPT_CLEAR_01_0
+#define GPIO_C_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x15234)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_C_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_C_INTERRUPT_CLEAR_01_0_SCR                         GPIO_C_SCR_01_0
+#define GPIO_C_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_C_SCR_01_0
+#define GPIO_C_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_C_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15238
+
+// Reserved address 0x1523c
+
+// Register GPIO_C_ENABLE_CONFIG_02_0
+#define GPIO_C_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x15240)
+#define GPIO_C_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_C_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_C_ENABLE_CONFIG_02_0_SCR                   GPIO_C_SCR_02_0
+#define GPIO_C_ENABLE_CONFIG_02_0_SCRREG                        GPIO_C_SCR_02_0
+#define GPIO_C_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_C_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_C_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x15244)
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_C_SCR_02_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_C_SCR_02_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_C_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INPUT_02_0
+#define GPIO_C_INPUT_02_0                       MK_ADDR_CONST(0x15248)
+#define GPIO_C_INPUT_02_0_SECURE                        0x0
+#define GPIO_C_INPUT_02_0_DUAL                  0x0
+#define GPIO_C_INPUT_02_0_SCR                   GPIO_C_SCR_02_0
+#define GPIO_C_INPUT_02_0_SCRREG                        GPIO_C_SCR_02_0
+#define GPIO_C_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_C_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_C_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_C_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_C_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_C_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_OUTPUT_CONTROL_02_0
+#define GPIO_C_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1524c)
+#define GPIO_C_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_C_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_C_OUTPUT_CONTROL_02_0_SCR                  GPIO_C_SCR_02_0
+#define GPIO_C_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_C_SCR_02_0
+#define GPIO_C_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_C_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_C_OUTPUT_VALUE_02_0
+#define GPIO_C_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x15250)
+#define GPIO_C_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_C_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_C_OUTPUT_VALUE_02_0_SCR                    GPIO_C_SCR_02_0
+#define GPIO_C_OUTPUT_VALUE_02_0_SCRREG                         GPIO_C_SCR_02_0
+#define GPIO_C_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_C_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INTERRUPT_CLEAR_02_0
+#define GPIO_C_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x15254)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_C_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_C_INTERRUPT_CLEAR_02_0_SCR                         GPIO_C_SCR_02_0
+#define GPIO_C_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_C_SCR_02_0
+#define GPIO_C_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_C_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15258
+
+// Reserved address 0x1525c
+
+// Register GPIO_C_ENABLE_CONFIG_03_0
+#define GPIO_C_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x15260)
+#define GPIO_C_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_C_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_C_ENABLE_CONFIG_03_0_SCR                   GPIO_C_SCR_03_0
+#define GPIO_C_ENABLE_CONFIG_03_0_SCRREG                        GPIO_C_SCR_03_0
+#define GPIO_C_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_C_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_C_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x15264)
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_C_SCR_03_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_C_SCR_03_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_C_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INPUT_03_0
+#define GPIO_C_INPUT_03_0                       MK_ADDR_CONST(0x15268)
+#define GPIO_C_INPUT_03_0_SECURE                        0x0
+#define GPIO_C_INPUT_03_0_DUAL                  0x0
+#define GPIO_C_INPUT_03_0_SCR                   GPIO_C_SCR_03_0
+#define GPIO_C_INPUT_03_0_SCRREG                        GPIO_C_SCR_03_0
+#define GPIO_C_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_C_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_C_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_C_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_C_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_C_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_OUTPUT_CONTROL_03_0
+#define GPIO_C_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1526c)
+#define GPIO_C_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_C_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_C_OUTPUT_CONTROL_03_0_SCR                  GPIO_C_SCR_03_0
+#define GPIO_C_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_C_SCR_03_0
+#define GPIO_C_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_C_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_C_OUTPUT_VALUE_03_0
+#define GPIO_C_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x15270)
+#define GPIO_C_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_C_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_C_OUTPUT_VALUE_03_0_SCR                    GPIO_C_SCR_03_0
+#define GPIO_C_OUTPUT_VALUE_03_0_SCRREG                         GPIO_C_SCR_03_0
+#define GPIO_C_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_C_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INTERRUPT_CLEAR_03_0
+#define GPIO_C_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x15274)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_C_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_C_INTERRUPT_CLEAR_03_0_SCR                         GPIO_C_SCR_03_0
+#define GPIO_C_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_C_SCR_03_0
+#define GPIO_C_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_C_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15278
+
+// Reserved address 0x1527c
+
+// Register GPIO_C_ENABLE_CONFIG_04_0
+#define GPIO_C_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x15280)
+#define GPIO_C_ENABLE_CONFIG_04_0_SECURE                        0x0
+#define GPIO_C_ENABLE_CONFIG_04_0_DUAL                  0x0
+#define GPIO_C_ENABLE_CONFIG_04_0_SCR                   GPIO_C_SCR_04_0
+#define GPIO_C_ENABLE_CONFIG_04_0_SCRREG                        GPIO_C_SCR_04_0
+#define GPIO_C_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
+#define GPIO_C_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
+#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_C_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x15284)
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_C_SCR_04_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_C_SCR_04_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_C_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INPUT_04_0
+#define GPIO_C_INPUT_04_0                       MK_ADDR_CONST(0x15288)
+#define GPIO_C_INPUT_04_0_SECURE                        0x0
+#define GPIO_C_INPUT_04_0_DUAL                  0x0
+#define GPIO_C_INPUT_04_0_SCR                   GPIO_C_SCR_04_0
+#define GPIO_C_INPUT_04_0_SCRREG                        GPIO_C_SCR_04_0
+#define GPIO_C_INPUT_04_0_WORD_COUNT                    0x1
+#define GPIO_C_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_C_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_C_INPUT_04_0_GPIO_IN_RANGE                 0:0
+#define GPIO_C_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_C_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_OUTPUT_CONTROL_04_0
+#define GPIO_C_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1528c)
+#define GPIO_C_OUTPUT_CONTROL_04_0_SECURE                       0x0
+#define GPIO_C_OUTPUT_CONTROL_04_0_DUAL                         0x0
+#define GPIO_C_OUTPUT_CONTROL_04_0_SCR                  GPIO_C_SCR_04_0
+#define GPIO_C_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_C_SCR_04_0
+#define GPIO_C_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
+#define GPIO_C_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_C_OUTPUT_VALUE_04_0
+#define GPIO_C_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x15290)
+#define GPIO_C_OUTPUT_VALUE_04_0_SECURE                         0x0
+#define GPIO_C_OUTPUT_VALUE_04_0_DUAL                   0x0
+#define GPIO_C_OUTPUT_VALUE_04_0_SCR                    GPIO_C_SCR_04_0
+#define GPIO_C_OUTPUT_VALUE_04_0_SCRREG                         GPIO_C_SCR_04_0
+#define GPIO_C_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
+#define GPIO_C_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INTERRUPT_CLEAR_04_0
+#define GPIO_C_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x15294)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_SECURE                      0x0
+#define GPIO_C_INTERRUPT_CLEAR_04_0_DUAL                        0x0
+#define GPIO_C_INTERRUPT_CLEAR_04_0_SCR                         GPIO_C_SCR_04_0
+#define GPIO_C_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_C_SCR_04_0
+#define GPIO_C_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
+#define GPIO_C_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15298
+
+// Reserved address 0x1529c
+
+// Register GPIO_C_ENABLE_CONFIG_05_0
+#define GPIO_C_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x152a0)
+#define GPIO_C_ENABLE_CONFIG_05_0_SECURE                        0x0
+#define GPIO_C_ENABLE_CONFIG_05_0_DUAL                  0x0
+#define GPIO_C_ENABLE_CONFIG_05_0_SCR                   GPIO_C_SCR_05_0
+#define GPIO_C_ENABLE_CONFIG_05_0_SCRREG                        GPIO_C_SCR_05_0
+#define GPIO_C_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
+#define GPIO_C_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
+#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_C_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x152a4)
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_C_SCR_05_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_C_SCR_05_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_C_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INPUT_05_0
+#define GPIO_C_INPUT_05_0                       MK_ADDR_CONST(0x152a8)
+#define GPIO_C_INPUT_05_0_SECURE                        0x0
+#define GPIO_C_INPUT_05_0_DUAL                  0x0
+#define GPIO_C_INPUT_05_0_SCR                   GPIO_C_SCR_05_0
+#define GPIO_C_INPUT_05_0_SCRREG                        GPIO_C_SCR_05_0
+#define GPIO_C_INPUT_05_0_WORD_COUNT                    0x1
+#define GPIO_C_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_C_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_C_INPUT_05_0_GPIO_IN_RANGE                 0:0
+#define GPIO_C_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_C_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_OUTPUT_CONTROL_05_0
+#define GPIO_C_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x152ac)
+#define GPIO_C_OUTPUT_CONTROL_05_0_SECURE                       0x0
+#define GPIO_C_OUTPUT_CONTROL_05_0_DUAL                         0x0
+#define GPIO_C_OUTPUT_CONTROL_05_0_SCR                  GPIO_C_SCR_05_0
+#define GPIO_C_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_C_SCR_05_0
+#define GPIO_C_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
+#define GPIO_C_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_C_OUTPUT_VALUE_05_0
+#define GPIO_C_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x152b0)
+#define GPIO_C_OUTPUT_VALUE_05_0_SECURE                         0x0
+#define GPIO_C_OUTPUT_VALUE_05_0_DUAL                   0x0
+#define GPIO_C_OUTPUT_VALUE_05_0_SCR                    GPIO_C_SCR_05_0
+#define GPIO_C_OUTPUT_VALUE_05_0_SCRREG                         GPIO_C_SCR_05_0
+#define GPIO_C_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
+#define GPIO_C_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INTERRUPT_CLEAR_05_0
+#define GPIO_C_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x152b4)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_SECURE                      0x0
+#define GPIO_C_INTERRUPT_CLEAR_05_0_DUAL                        0x0
+#define GPIO_C_INTERRUPT_CLEAR_05_0_SCR                         GPIO_C_SCR_05_0
+#define GPIO_C_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_C_SCR_05_0
+#define GPIO_C_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
+#define GPIO_C_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x152b8
+
+// Reserved address 0x152bc
+
+// Register GPIO_C_ENABLE_CONFIG_06_0
+#define GPIO_C_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x152c0)
+#define GPIO_C_ENABLE_CONFIG_06_0_SECURE                        0x0
+#define GPIO_C_ENABLE_CONFIG_06_0_DUAL                  0x0
+#define GPIO_C_ENABLE_CONFIG_06_0_SCR                   GPIO_C_SCR_06_0
+#define GPIO_C_ENABLE_CONFIG_06_0_SCRREG                        GPIO_C_SCR_06_0
+#define GPIO_C_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
+#define GPIO_C_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
+#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_C_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x152c4)
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_C_SCR_06_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_C_SCR_06_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_C_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INPUT_06_0
+#define GPIO_C_INPUT_06_0                       MK_ADDR_CONST(0x152c8)
+#define GPIO_C_INPUT_06_0_SECURE                        0x0
+#define GPIO_C_INPUT_06_0_DUAL                  0x0
+#define GPIO_C_INPUT_06_0_SCR                   GPIO_C_SCR_06_0
+#define GPIO_C_INPUT_06_0_SCRREG                        GPIO_C_SCR_06_0
+#define GPIO_C_INPUT_06_0_WORD_COUNT                    0x1
+#define GPIO_C_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_C_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_C_INPUT_06_0_GPIO_IN_RANGE                 0:0
+#define GPIO_C_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_C_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_OUTPUT_CONTROL_06_0
+#define GPIO_C_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x152cc)
+#define GPIO_C_OUTPUT_CONTROL_06_0_SECURE                       0x0
+#define GPIO_C_OUTPUT_CONTROL_06_0_DUAL                         0x0
+#define GPIO_C_OUTPUT_CONTROL_06_0_SCR                  GPIO_C_SCR_06_0
+#define GPIO_C_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_C_SCR_06_0
+#define GPIO_C_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
+#define GPIO_C_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_C_OUTPUT_VALUE_06_0
+#define GPIO_C_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x152d0)
+#define GPIO_C_OUTPUT_VALUE_06_0_SECURE                         0x0
+#define GPIO_C_OUTPUT_VALUE_06_0_DUAL                   0x0
+#define GPIO_C_OUTPUT_VALUE_06_0_SCR                    GPIO_C_SCR_06_0
+#define GPIO_C_OUTPUT_VALUE_06_0_SCRREG                         GPIO_C_SCR_06_0
+#define GPIO_C_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
+#define GPIO_C_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INTERRUPT_CLEAR_06_0
+#define GPIO_C_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x152d4)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_SECURE                      0x0
+#define GPIO_C_INTERRUPT_CLEAR_06_0_DUAL                        0x0
+#define GPIO_C_INTERRUPT_CLEAR_06_0_SCR                         GPIO_C_SCR_06_0
+#define GPIO_C_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_C_SCR_06_0
+#define GPIO_C_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
+#define GPIO_C_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x152d8
+
+// Reserved address 0x152dc
+
+// Register GPIO_C_ENABLE_CONFIG_07_0
+#define GPIO_C_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x152e0)
+#define GPIO_C_ENABLE_CONFIG_07_0_SECURE                        0x0
+#define GPIO_C_ENABLE_CONFIG_07_0_DUAL                  0x0
+#define GPIO_C_ENABLE_CONFIG_07_0_SCR                   GPIO_C_SCR_07_0
+#define GPIO_C_ENABLE_CONFIG_07_0_SCRREG                        GPIO_C_SCR_07_0
+#define GPIO_C_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
+#define GPIO_C_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
+#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_C_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_C_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x152e4)
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_C_SCR_07_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_C_SCR_07_0
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_C_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INPUT_07_0
+#define GPIO_C_INPUT_07_0                       MK_ADDR_CONST(0x152e8)
+#define GPIO_C_INPUT_07_0_SECURE                        0x0
+#define GPIO_C_INPUT_07_0_DUAL                  0x0
+#define GPIO_C_INPUT_07_0_SCR                   GPIO_C_SCR_07_0
+#define GPIO_C_INPUT_07_0_SCRREG                        GPIO_C_SCR_07_0
+#define GPIO_C_INPUT_07_0_WORD_COUNT                    0x1
+#define GPIO_C_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_C_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_C_INPUT_07_0_GPIO_IN_RANGE                 0:0
+#define GPIO_C_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_C_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_C_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_C_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_OUTPUT_CONTROL_07_0
+#define GPIO_C_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x152ec)
+#define GPIO_C_OUTPUT_CONTROL_07_0_SECURE                       0x0
+#define GPIO_C_OUTPUT_CONTROL_07_0_DUAL                         0x0
+#define GPIO_C_OUTPUT_CONTROL_07_0_SCR                  GPIO_C_SCR_07_0
+#define GPIO_C_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_C_SCR_07_0
+#define GPIO_C_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
+#define GPIO_C_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_C_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_C_OUTPUT_VALUE_07_0
+#define GPIO_C_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x152f0)
+#define GPIO_C_OUTPUT_VALUE_07_0_SECURE                         0x0
+#define GPIO_C_OUTPUT_VALUE_07_0_DUAL                   0x0
+#define GPIO_C_OUTPUT_VALUE_07_0_SCR                    GPIO_C_SCR_07_0
+#define GPIO_C_OUTPUT_VALUE_07_0_SCRREG                         GPIO_C_SCR_07_0
+#define GPIO_C_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
+#define GPIO_C_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_C_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INTERRUPT_CLEAR_07_0
+#define GPIO_C_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x152f4)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_SECURE                      0x0
+#define GPIO_C_INTERRUPT_CLEAR_07_0_DUAL                        0x0
+#define GPIO_C_INTERRUPT_CLEAR_07_0_SCR                         GPIO_C_SCR_07_0
+#define GPIO_C_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_C_SCR_07_0
+#define GPIO_C_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
+#define GPIO_C_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_C_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x152f8
+
+// Reserved address 0x152fc
+
+// Register GPIO_C_INTERRUPT_STATUS_G0_0
+#define GPIO_C_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x15300)
+#define GPIO_C_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_C_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_C_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_C_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_C_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_C_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INTERRUPT_STATUS_G1_0
+#define GPIO_C_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x15304)
+#define GPIO_C_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_C_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_C_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_C_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_C_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_C_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INTERRUPT_STATUS_G2_0
+#define GPIO_C_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x15308)
+#define GPIO_C_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_C_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_C_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_C_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_C_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_C_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INTERRUPT_STATUS_G3_0
+#define GPIO_C_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1530c)
+#define GPIO_C_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_C_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_C_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_C_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_C_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_C_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INTERRUPT_STATUS_G4_0
+#define GPIO_C_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x15310)
+#define GPIO_C_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_C_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_C_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_C_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_C_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_C_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INTERRUPT_STATUS_G5_0
+#define GPIO_C_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x15314)
+#define GPIO_C_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_C_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_C_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_C_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_C_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_C_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INTERRUPT_STATUS_G6_0
+#define GPIO_C_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x15318)
+#define GPIO_C_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_C_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_C_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_C_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_C_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_C_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_C_INTERRUPT_STATUS_G7_0
+#define GPIO_C_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1531c)
+#define GPIO_C_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_C_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_C_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_C_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_C_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_C_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_C_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x15320
+
+// Reserved address 0x15324
+
+// Reserved address 0x15328
+
+// Reserved address 0x1532c
+
+// Reserved address 0x15330
+
+// Reserved address 0x15334
+
+// Reserved address 0x15338
+
+// Reserved address 0x1533c
+
+// Reserved address 0x15340
+
+// Reserved address 0x15344
+
+// Reserved address 0x15348
+
+// Reserved address 0x1534c
+
+// Reserved address 0x15350
+
+// Reserved address 0x15354
+
+// Reserved address 0x15358
+
+// Reserved address 0x1535c
+
+// Reserved address 0x15360
+
+// Reserved address 0x15364
+
+// Reserved address 0x15368
+
+// Reserved address 0x1536c
+
+// Reserved address 0x15370
+
+// Reserved address 0x15374
+
+// Reserved address 0x15378
+
+// Reserved address 0x1537c
+
+// Reserved address 0x15380
+
+// Reserved address 0x15384
+
+// Reserved address 0x15388
+
+// Reserved address 0x1538c
+
+// Reserved address 0x15390
+
+// Reserved address 0x15394
+
+// Reserved address 0x15398
+
+// Reserved address 0x1539c
+
+// Reserved address 0x153a0
+
+// Reserved address 0x153a4
+
+// Reserved address 0x153a8
+
+// Reserved address 0x153ac
+
+// Reserved address 0x153b0
+
+// Reserved address 0x153b4
+
+// Reserved address 0x153b8
+
+// Reserved address 0x153bc
+
+// Reserved address 0x153c0
+
+// Reserved address 0x153c4
+
+// Reserved address 0x153c8
+
+// Reserved address 0x153cc
+
+// Reserved address 0x153d0
+
+// Reserved address 0x153d4
+
+// Reserved address 0x153d8
+
+// Reserved address 0x153dc
+
+// Reserved address 0x153e0
+
+// Reserved address 0x153e4
+
+// Reserved address 0x153e8
+
+// Reserved address 0x153ec
+
+// Reserved address 0x153f0
+
+// Reserved address 0x153f4
+
+// Reserved address 0x153f8
+
+// Reserved address 0x153fc
+
+// Register GPIO_D_ENABLE_CONFIG_00_0
+#define GPIO_D_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x15400)
+#define GPIO_D_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_D_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_D_ENABLE_CONFIG_00_0_SCR                   GPIO_D_SCR_00_0
+#define GPIO_D_ENABLE_CONFIG_00_0_SCRREG                        GPIO_D_SCR_00_0
+#define GPIO_D_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_D_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_D_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_D_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_D_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x15404)
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_D_SCR_00_0
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_D_SCR_00_0
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_D_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INPUT_00_0
+#define GPIO_D_INPUT_00_0                       MK_ADDR_CONST(0x15408)
+#define GPIO_D_INPUT_00_0_SECURE                        0x0
+#define GPIO_D_INPUT_00_0_DUAL                  0x0
+#define GPIO_D_INPUT_00_0_SCR                   GPIO_D_SCR_00_0
+#define GPIO_D_INPUT_00_0_SCRREG                        GPIO_D_SCR_00_0
+#define GPIO_D_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_D_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_D_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_D_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_D_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_D_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_D_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_D_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_D_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_D_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_OUTPUT_CONTROL_00_0
+#define GPIO_D_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1540c)
+#define GPIO_D_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_D_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_D_OUTPUT_CONTROL_00_0_SCR                  GPIO_D_SCR_00_0
+#define GPIO_D_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_D_SCR_00_0
+#define GPIO_D_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_D_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_D_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_D_OUTPUT_VALUE_00_0
+#define GPIO_D_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x15410)
+#define GPIO_D_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_D_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_D_OUTPUT_VALUE_00_0_SCR                    GPIO_D_SCR_00_0
+#define GPIO_D_OUTPUT_VALUE_00_0_SCRREG                         GPIO_D_SCR_00_0
+#define GPIO_D_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_D_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INTERRUPT_CLEAR_00_0
+#define GPIO_D_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x15414)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_D_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_D_INTERRUPT_CLEAR_00_0_SCR                         GPIO_D_SCR_00_0
+#define GPIO_D_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_D_SCR_00_0
+#define GPIO_D_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_D_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_D_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15418
+
+// Reserved address 0x1541c
+
+// Register GPIO_D_ENABLE_CONFIG_01_0
+#define GPIO_D_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x15420)
+#define GPIO_D_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_D_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_D_ENABLE_CONFIG_01_0_SCR                   GPIO_D_SCR_01_0
+#define GPIO_D_ENABLE_CONFIG_01_0_SCRREG                        GPIO_D_SCR_01_0
+#define GPIO_D_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_D_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_D_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_D_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_D_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x15424)
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_D_SCR_01_0
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_D_SCR_01_0
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_D_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INPUT_01_0
+#define GPIO_D_INPUT_01_0                       MK_ADDR_CONST(0x15428)
+#define GPIO_D_INPUT_01_0_SECURE                        0x0
+#define GPIO_D_INPUT_01_0_DUAL                  0x0
+#define GPIO_D_INPUT_01_0_SCR                   GPIO_D_SCR_01_0
+#define GPIO_D_INPUT_01_0_SCRREG                        GPIO_D_SCR_01_0
+#define GPIO_D_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_D_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_D_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_D_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_D_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_D_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_D_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_D_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_D_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_D_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_OUTPUT_CONTROL_01_0
+#define GPIO_D_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1542c)
+#define GPIO_D_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_D_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_D_OUTPUT_CONTROL_01_0_SCR                  GPIO_D_SCR_01_0
+#define GPIO_D_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_D_SCR_01_0
+#define GPIO_D_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_D_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_D_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_D_OUTPUT_VALUE_01_0
+#define GPIO_D_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x15430)
+#define GPIO_D_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_D_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_D_OUTPUT_VALUE_01_0_SCR                    GPIO_D_SCR_01_0
+#define GPIO_D_OUTPUT_VALUE_01_0_SCRREG                         GPIO_D_SCR_01_0
+#define GPIO_D_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_D_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INTERRUPT_CLEAR_01_0
+#define GPIO_D_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x15434)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_D_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_D_INTERRUPT_CLEAR_01_0_SCR                         GPIO_D_SCR_01_0
+#define GPIO_D_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_D_SCR_01_0
+#define GPIO_D_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_D_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_D_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15438
+
+// Reserved address 0x1543c
+
+// Register GPIO_D_ENABLE_CONFIG_02_0
+#define GPIO_D_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x15440)
+#define GPIO_D_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_D_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_D_ENABLE_CONFIG_02_0_SCR                   GPIO_D_SCR_02_0
+#define GPIO_D_ENABLE_CONFIG_02_0_SCRREG                        GPIO_D_SCR_02_0
+#define GPIO_D_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_D_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_D_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_D_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_D_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x15444)
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_D_SCR_02_0
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_D_SCR_02_0
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_D_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INPUT_02_0
+#define GPIO_D_INPUT_02_0                       MK_ADDR_CONST(0x15448)
+#define GPIO_D_INPUT_02_0_SECURE                        0x0
+#define GPIO_D_INPUT_02_0_DUAL                  0x0
+#define GPIO_D_INPUT_02_0_SCR                   GPIO_D_SCR_02_0
+#define GPIO_D_INPUT_02_0_SCRREG                        GPIO_D_SCR_02_0
+#define GPIO_D_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_D_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_D_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_D_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_D_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_D_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_D_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_D_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_D_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_D_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_OUTPUT_CONTROL_02_0
+#define GPIO_D_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1544c)
+#define GPIO_D_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_D_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_D_OUTPUT_CONTROL_02_0_SCR                  GPIO_D_SCR_02_0
+#define GPIO_D_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_D_SCR_02_0
+#define GPIO_D_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_D_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_D_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_D_OUTPUT_VALUE_02_0
+#define GPIO_D_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x15450)
+#define GPIO_D_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_D_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_D_OUTPUT_VALUE_02_0_SCR                    GPIO_D_SCR_02_0
+#define GPIO_D_OUTPUT_VALUE_02_0_SCRREG                         GPIO_D_SCR_02_0
+#define GPIO_D_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_D_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INTERRUPT_CLEAR_02_0
+#define GPIO_D_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x15454)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_D_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_D_INTERRUPT_CLEAR_02_0_SCR                         GPIO_D_SCR_02_0
+#define GPIO_D_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_D_SCR_02_0
+#define GPIO_D_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_D_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_D_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15458
+
+// Reserved address 0x1545c
+
+// Register GPIO_D_ENABLE_CONFIG_03_0
+#define GPIO_D_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x15460)
+#define GPIO_D_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_D_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_D_ENABLE_CONFIG_03_0_SCR                   GPIO_D_SCR_03_0
+#define GPIO_D_ENABLE_CONFIG_03_0_SCRREG                        GPIO_D_SCR_03_0
+#define GPIO_D_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_D_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_D_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_D_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_D_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_D_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x15464)
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_D_SCR_03_0
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_D_SCR_03_0
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_D_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INPUT_03_0
+#define GPIO_D_INPUT_03_0                       MK_ADDR_CONST(0x15468)
+#define GPIO_D_INPUT_03_0_SECURE                        0x0
+#define GPIO_D_INPUT_03_0_DUAL                  0x0
+#define GPIO_D_INPUT_03_0_SCR                   GPIO_D_SCR_03_0
+#define GPIO_D_INPUT_03_0_SCRREG                        GPIO_D_SCR_03_0
+#define GPIO_D_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_D_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_D_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_D_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_D_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_D_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_D_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_D_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_D_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_D_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_D_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_OUTPUT_CONTROL_03_0
+#define GPIO_D_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1546c)
+#define GPIO_D_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_D_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_D_OUTPUT_CONTROL_03_0_SCR                  GPIO_D_SCR_03_0
+#define GPIO_D_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_D_SCR_03_0
+#define GPIO_D_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_D_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_D_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_D_OUTPUT_VALUE_03_0
+#define GPIO_D_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x15470)
+#define GPIO_D_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_D_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_D_OUTPUT_VALUE_03_0_SCR                    GPIO_D_SCR_03_0
+#define GPIO_D_OUTPUT_VALUE_03_0_SCRREG                         GPIO_D_SCR_03_0
+#define GPIO_D_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_D_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_D_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INTERRUPT_CLEAR_03_0
+#define GPIO_D_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x15474)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_D_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_D_INTERRUPT_CLEAR_03_0_SCR                         GPIO_D_SCR_03_0
+#define GPIO_D_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_D_SCR_03_0
+#define GPIO_D_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_D_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_D_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15478
+
+// Reserved address 0x1547c
+
+// Reserved address 0x15480
+
+// Reserved address 0x15484
+
+// Reserved address 0x15488
+
+// Reserved address 0x1548c
+
+// Reserved address 0x15490
+
+// Reserved address 0x15494
+
+// Reserved address 0x15498
+
+// Reserved address 0x1549c
+
+// Reserved address 0x154a0
+
+// Reserved address 0x154a4
+
+// Reserved address 0x154a8
+
+// Reserved address 0x154ac
+
+// Reserved address 0x154b0
+
+// Reserved address 0x154b4
+
+// Reserved address 0x154b8
+
+// Reserved address 0x154bc
+
+// Reserved address 0x154c0
+
+// Reserved address 0x154c4
+
+// Reserved address 0x154c8
+
+// Reserved address 0x154cc
+
+// Reserved address 0x154d0
+
+// Reserved address 0x154d4
+
+// Reserved address 0x154d8
+
+// Reserved address 0x154dc
+
+// Reserved address 0x154e0
+
+// Reserved address 0x154e4
+
+// Reserved address 0x154e8
+
+// Reserved address 0x154ec
+
+// Reserved address 0x154f0
+
+// Reserved address 0x154f4
+
+// Reserved address 0x154f8
+
+// Reserved address 0x154fc
+
+// Register GPIO_D_INTERRUPT_STATUS_G0_0
+#define GPIO_D_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x15500)
+#define GPIO_D_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_D_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_D_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_D_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_D_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_D_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
+#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INTERRUPT_STATUS_G1_0
+#define GPIO_D_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x15504)
+#define GPIO_D_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_D_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_D_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_D_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_D_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_D_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
+#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INTERRUPT_STATUS_G2_0
+#define GPIO_D_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x15508)
+#define GPIO_D_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_D_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_D_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_D_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_D_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_D_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
+#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INTERRUPT_STATUS_G3_0
+#define GPIO_D_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1550c)
+#define GPIO_D_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_D_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_D_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_D_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_D_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_D_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
+#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INTERRUPT_STATUS_G4_0
+#define GPIO_D_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x15510)
+#define GPIO_D_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_D_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_D_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_D_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_D_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_D_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
+#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INTERRUPT_STATUS_G5_0
+#define GPIO_D_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x15514)
+#define GPIO_D_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_D_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_D_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_D_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_D_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_D_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
+#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INTERRUPT_STATUS_G6_0
+#define GPIO_D_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x15518)
+#define GPIO_D_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_D_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_D_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_D_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_D_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_D_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
+#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_D_INTERRUPT_STATUS_G7_0
+#define GPIO_D_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1551c)
+#define GPIO_D_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_D_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_D_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_D_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_D_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_D_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xf, GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        3:0
+#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(3)
+#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_D_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x15520
+
+// Reserved address 0x15524
+
+// Reserved address 0x15528
+
+// Reserved address 0x1552c
+
+// Reserved address 0x15530
+
+// Reserved address 0x15534
+
+// Reserved address 0x15538
+
+// Reserved address 0x1553c
+
+// Reserved address 0x15540
+
+// Reserved address 0x15544
+
+// Reserved address 0x15548
+
+// Reserved address 0x1554c
+
+// Reserved address 0x15550
+
+// Reserved address 0x15554
+
+// Reserved address 0x15558
+
+// Reserved address 0x1555c
+
+// Reserved address 0x15560
+
+// Reserved address 0x15564
+
+// Reserved address 0x15568
+
+// Reserved address 0x1556c
+
+// Reserved address 0x15570
+
+// Reserved address 0x15574
+
+// Reserved address 0x15578
+
+// Reserved address 0x1557c
+
+// Reserved address 0x15580
+
+// Reserved address 0x15584
+
+// Reserved address 0x15588
+
+// Reserved address 0x1558c
+
+// Reserved address 0x15590
+
+// Reserved address 0x15594
+
+// Reserved address 0x15598
+
+// Reserved address 0x1559c
+
+// Reserved address 0x155a0
+
+// Reserved address 0x155a4
+
+// Reserved address 0x155a8
+
+// Reserved address 0x155ac
+
+// Reserved address 0x155b0
+
+// Reserved address 0x155b4
+
+// Reserved address 0x155b8
+
+// Reserved address 0x155bc
+
+// Reserved address 0x155c0
+
+// Reserved address 0x155c4
+
+// Reserved address 0x155c8
+
+// Reserved address 0x155cc
+
+// Reserved address 0x155d0
+
+// Reserved address 0x155d4
+
+// Reserved address 0x155d8
+
+// Reserved address 0x155dc
+
+// Reserved address 0x155e0
+
+// Reserved address 0x155e4
+
+// Reserved address 0x155e8
+
+// Reserved address 0x155ec
+
+// Reserved address 0x155f0
+
+// Reserved address 0x155f4
+
+// Reserved address 0x155f8
+
+// Reserved address 0x155fc
+
+// Register GPIO_E_ENABLE_CONFIG_00_0
+#define GPIO_E_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x15600)
+#define GPIO_E_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_E_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_E_ENABLE_CONFIG_00_0_SCR                   GPIO_E_SCR_00_0
+#define GPIO_E_ENABLE_CONFIG_00_0_SCRREG                        GPIO_E_SCR_00_0
+#define GPIO_E_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_E_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_E_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x15604)
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_E_SCR_00_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_E_SCR_00_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_E_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INPUT_00_0
+#define GPIO_E_INPUT_00_0                       MK_ADDR_CONST(0x15608)
+#define GPIO_E_INPUT_00_0_SECURE                        0x0
+#define GPIO_E_INPUT_00_0_DUAL                  0x0
+#define GPIO_E_INPUT_00_0_SCR                   GPIO_E_SCR_00_0
+#define GPIO_E_INPUT_00_0_SCRREG                        GPIO_E_SCR_00_0
+#define GPIO_E_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_E_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_E_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_E_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_E_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_E_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_OUTPUT_CONTROL_00_0
+#define GPIO_E_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1560c)
+#define GPIO_E_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_E_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_E_OUTPUT_CONTROL_00_0_SCR                  GPIO_E_SCR_00_0
+#define GPIO_E_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_E_SCR_00_0
+#define GPIO_E_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_E_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_E_OUTPUT_VALUE_00_0
+#define GPIO_E_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x15610)
+#define GPIO_E_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_E_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_E_OUTPUT_VALUE_00_0_SCR                    GPIO_E_SCR_00_0
+#define GPIO_E_OUTPUT_VALUE_00_0_SCRREG                         GPIO_E_SCR_00_0
+#define GPIO_E_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_E_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INTERRUPT_CLEAR_00_0
+#define GPIO_E_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x15614)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_E_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_E_INTERRUPT_CLEAR_00_0_SCR                         GPIO_E_SCR_00_0
+#define GPIO_E_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_E_SCR_00_0
+#define GPIO_E_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_E_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15618
+
+// Reserved address 0x1561c
+
+// Register GPIO_E_ENABLE_CONFIG_01_0
+#define GPIO_E_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x15620)
+#define GPIO_E_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_E_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_E_ENABLE_CONFIG_01_0_SCR                   GPIO_E_SCR_01_0
+#define GPIO_E_ENABLE_CONFIG_01_0_SCRREG                        GPIO_E_SCR_01_0
+#define GPIO_E_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_E_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_E_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x15624)
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_E_SCR_01_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_E_SCR_01_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_E_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INPUT_01_0
+#define GPIO_E_INPUT_01_0                       MK_ADDR_CONST(0x15628)
+#define GPIO_E_INPUT_01_0_SECURE                        0x0
+#define GPIO_E_INPUT_01_0_DUAL                  0x0
+#define GPIO_E_INPUT_01_0_SCR                   GPIO_E_SCR_01_0
+#define GPIO_E_INPUT_01_0_SCRREG                        GPIO_E_SCR_01_0
+#define GPIO_E_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_E_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_E_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_E_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_E_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_E_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_OUTPUT_CONTROL_01_0
+#define GPIO_E_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1562c)
+#define GPIO_E_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_E_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_E_OUTPUT_CONTROL_01_0_SCR                  GPIO_E_SCR_01_0
+#define GPIO_E_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_E_SCR_01_0
+#define GPIO_E_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_E_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_E_OUTPUT_VALUE_01_0
+#define GPIO_E_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x15630)
+#define GPIO_E_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_E_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_E_OUTPUT_VALUE_01_0_SCR                    GPIO_E_SCR_01_0
+#define GPIO_E_OUTPUT_VALUE_01_0_SCRREG                         GPIO_E_SCR_01_0
+#define GPIO_E_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_E_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INTERRUPT_CLEAR_01_0
+#define GPIO_E_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x15634)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_E_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_E_INTERRUPT_CLEAR_01_0_SCR                         GPIO_E_SCR_01_0
+#define GPIO_E_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_E_SCR_01_0
+#define GPIO_E_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_E_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15638
+
+// Reserved address 0x1563c
+
+// Register GPIO_E_ENABLE_CONFIG_02_0
+#define GPIO_E_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x15640)
+#define GPIO_E_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_E_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_E_ENABLE_CONFIG_02_0_SCR                   GPIO_E_SCR_02_0
+#define GPIO_E_ENABLE_CONFIG_02_0_SCRREG                        GPIO_E_SCR_02_0
+#define GPIO_E_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_E_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_E_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x15644)
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_E_SCR_02_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_E_SCR_02_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_E_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INPUT_02_0
+#define GPIO_E_INPUT_02_0                       MK_ADDR_CONST(0x15648)
+#define GPIO_E_INPUT_02_0_SECURE                        0x0
+#define GPIO_E_INPUT_02_0_DUAL                  0x0
+#define GPIO_E_INPUT_02_0_SCR                   GPIO_E_SCR_02_0
+#define GPIO_E_INPUT_02_0_SCRREG                        GPIO_E_SCR_02_0
+#define GPIO_E_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_E_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_E_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_E_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_E_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_E_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_OUTPUT_CONTROL_02_0
+#define GPIO_E_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1564c)
+#define GPIO_E_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_E_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_E_OUTPUT_CONTROL_02_0_SCR                  GPIO_E_SCR_02_0
+#define GPIO_E_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_E_SCR_02_0
+#define GPIO_E_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_E_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_E_OUTPUT_VALUE_02_0
+#define GPIO_E_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x15650)
+#define GPIO_E_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_E_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_E_OUTPUT_VALUE_02_0_SCR                    GPIO_E_SCR_02_0
+#define GPIO_E_OUTPUT_VALUE_02_0_SCRREG                         GPIO_E_SCR_02_0
+#define GPIO_E_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_E_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INTERRUPT_CLEAR_02_0
+#define GPIO_E_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x15654)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_E_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_E_INTERRUPT_CLEAR_02_0_SCR                         GPIO_E_SCR_02_0
+#define GPIO_E_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_E_SCR_02_0
+#define GPIO_E_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_E_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15658
+
+// Reserved address 0x1565c
+
+// Register GPIO_E_ENABLE_CONFIG_03_0
+#define GPIO_E_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x15660)
+#define GPIO_E_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_E_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_E_ENABLE_CONFIG_03_0_SCR                   GPIO_E_SCR_03_0
+#define GPIO_E_ENABLE_CONFIG_03_0_SCRREG                        GPIO_E_SCR_03_0
+#define GPIO_E_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_E_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_E_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x15664)
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_E_SCR_03_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_E_SCR_03_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_E_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INPUT_03_0
+#define GPIO_E_INPUT_03_0                       MK_ADDR_CONST(0x15668)
+#define GPIO_E_INPUT_03_0_SECURE                        0x0
+#define GPIO_E_INPUT_03_0_DUAL                  0x0
+#define GPIO_E_INPUT_03_0_SCR                   GPIO_E_SCR_03_0
+#define GPIO_E_INPUT_03_0_SCRREG                        GPIO_E_SCR_03_0
+#define GPIO_E_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_E_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_E_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_E_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_E_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_E_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_OUTPUT_CONTROL_03_0
+#define GPIO_E_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1566c)
+#define GPIO_E_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_E_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_E_OUTPUT_CONTROL_03_0_SCR                  GPIO_E_SCR_03_0
+#define GPIO_E_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_E_SCR_03_0
+#define GPIO_E_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_E_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_E_OUTPUT_VALUE_03_0
+#define GPIO_E_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x15670)
+#define GPIO_E_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_E_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_E_OUTPUT_VALUE_03_0_SCR                    GPIO_E_SCR_03_0
+#define GPIO_E_OUTPUT_VALUE_03_0_SCRREG                         GPIO_E_SCR_03_0
+#define GPIO_E_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_E_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INTERRUPT_CLEAR_03_0
+#define GPIO_E_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x15674)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_E_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_E_INTERRUPT_CLEAR_03_0_SCR                         GPIO_E_SCR_03_0
+#define GPIO_E_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_E_SCR_03_0
+#define GPIO_E_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_E_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15678
+
+// Reserved address 0x1567c
+
+// Register GPIO_E_ENABLE_CONFIG_04_0
+#define GPIO_E_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x15680)
+#define GPIO_E_ENABLE_CONFIG_04_0_SECURE                        0x0
+#define GPIO_E_ENABLE_CONFIG_04_0_DUAL                  0x0
+#define GPIO_E_ENABLE_CONFIG_04_0_SCR                   GPIO_E_SCR_04_0
+#define GPIO_E_ENABLE_CONFIG_04_0_SCRREG                        GPIO_E_SCR_04_0
+#define GPIO_E_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
+#define GPIO_E_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
+#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_E_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x15684)
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_E_SCR_04_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_E_SCR_04_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_E_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INPUT_04_0
+#define GPIO_E_INPUT_04_0                       MK_ADDR_CONST(0x15688)
+#define GPIO_E_INPUT_04_0_SECURE                        0x0
+#define GPIO_E_INPUT_04_0_DUAL                  0x0
+#define GPIO_E_INPUT_04_0_SCR                   GPIO_E_SCR_04_0
+#define GPIO_E_INPUT_04_0_SCRREG                        GPIO_E_SCR_04_0
+#define GPIO_E_INPUT_04_0_WORD_COUNT                    0x1
+#define GPIO_E_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_E_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_E_INPUT_04_0_GPIO_IN_RANGE                 0:0
+#define GPIO_E_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_E_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_OUTPUT_CONTROL_04_0
+#define GPIO_E_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1568c)
+#define GPIO_E_OUTPUT_CONTROL_04_0_SECURE                       0x0
+#define GPIO_E_OUTPUT_CONTROL_04_0_DUAL                         0x0
+#define GPIO_E_OUTPUT_CONTROL_04_0_SCR                  GPIO_E_SCR_04_0
+#define GPIO_E_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_E_SCR_04_0
+#define GPIO_E_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
+#define GPIO_E_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_E_OUTPUT_VALUE_04_0
+#define GPIO_E_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x15690)
+#define GPIO_E_OUTPUT_VALUE_04_0_SECURE                         0x0
+#define GPIO_E_OUTPUT_VALUE_04_0_DUAL                   0x0
+#define GPIO_E_OUTPUT_VALUE_04_0_SCR                    GPIO_E_SCR_04_0
+#define GPIO_E_OUTPUT_VALUE_04_0_SCRREG                         GPIO_E_SCR_04_0
+#define GPIO_E_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
+#define GPIO_E_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INTERRUPT_CLEAR_04_0
+#define GPIO_E_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x15694)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_SECURE                      0x0
+#define GPIO_E_INTERRUPT_CLEAR_04_0_DUAL                        0x0
+#define GPIO_E_INTERRUPT_CLEAR_04_0_SCR                         GPIO_E_SCR_04_0
+#define GPIO_E_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_E_SCR_04_0
+#define GPIO_E_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
+#define GPIO_E_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15698
+
+// Reserved address 0x1569c
+
+// Register GPIO_E_ENABLE_CONFIG_05_0
+#define GPIO_E_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x156a0)
+#define GPIO_E_ENABLE_CONFIG_05_0_SECURE                        0x0
+#define GPIO_E_ENABLE_CONFIG_05_0_DUAL                  0x0
+#define GPIO_E_ENABLE_CONFIG_05_0_SCR                   GPIO_E_SCR_05_0
+#define GPIO_E_ENABLE_CONFIG_05_0_SCRREG                        GPIO_E_SCR_05_0
+#define GPIO_E_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
+#define GPIO_E_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
+#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_E_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x156a4)
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_E_SCR_05_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_E_SCR_05_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_E_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INPUT_05_0
+#define GPIO_E_INPUT_05_0                       MK_ADDR_CONST(0x156a8)
+#define GPIO_E_INPUT_05_0_SECURE                        0x0
+#define GPIO_E_INPUT_05_0_DUAL                  0x0
+#define GPIO_E_INPUT_05_0_SCR                   GPIO_E_SCR_05_0
+#define GPIO_E_INPUT_05_0_SCRREG                        GPIO_E_SCR_05_0
+#define GPIO_E_INPUT_05_0_WORD_COUNT                    0x1
+#define GPIO_E_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_E_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_E_INPUT_05_0_GPIO_IN_RANGE                 0:0
+#define GPIO_E_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_E_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_OUTPUT_CONTROL_05_0
+#define GPIO_E_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x156ac)
+#define GPIO_E_OUTPUT_CONTROL_05_0_SECURE                       0x0
+#define GPIO_E_OUTPUT_CONTROL_05_0_DUAL                         0x0
+#define GPIO_E_OUTPUT_CONTROL_05_0_SCR                  GPIO_E_SCR_05_0
+#define GPIO_E_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_E_SCR_05_0
+#define GPIO_E_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
+#define GPIO_E_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_E_OUTPUT_VALUE_05_0
+#define GPIO_E_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x156b0)
+#define GPIO_E_OUTPUT_VALUE_05_0_SECURE                         0x0
+#define GPIO_E_OUTPUT_VALUE_05_0_DUAL                   0x0
+#define GPIO_E_OUTPUT_VALUE_05_0_SCR                    GPIO_E_SCR_05_0
+#define GPIO_E_OUTPUT_VALUE_05_0_SCRREG                         GPIO_E_SCR_05_0
+#define GPIO_E_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
+#define GPIO_E_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INTERRUPT_CLEAR_05_0
+#define GPIO_E_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x156b4)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_SECURE                      0x0
+#define GPIO_E_INTERRUPT_CLEAR_05_0_DUAL                        0x0
+#define GPIO_E_INTERRUPT_CLEAR_05_0_SCR                         GPIO_E_SCR_05_0
+#define GPIO_E_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_E_SCR_05_0
+#define GPIO_E_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
+#define GPIO_E_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x156b8
+
+// Reserved address 0x156bc
+
+// Register GPIO_E_ENABLE_CONFIG_06_0
+#define GPIO_E_ENABLE_CONFIG_06_0                       MK_ADDR_CONST(0x156c0)
+#define GPIO_E_ENABLE_CONFIG_06_0_SECURE                        0x0
+#define GPIO_E_ENABLE_CONFIG_06_0_DUAL                  0x0
+#define GPIO_E_ENABLE_CONFIG_06_0_SCR                   GPIO_E_SCR_06_0
+#define GPIO_E_ENABLE_CONFIG_06_0_SCRREG                        GPIO_E_SCR_06_0
+#define GPIO_E_ENABLE_CONFIG_06_0_WORD_COUNT                    0x1
+#define GPIO_E_ENABLE_CONFIG_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_06_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_06_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_RANGE                  1:1
+#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_06_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_06_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_06_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_06_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_06_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_E_DEBOUNCE_THRESHOLD_06_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0                  MK_ADDR_CONST(0x156c4)
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SECURE                   0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DUAL                     0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SCR                      GPIO_E_SCR_06_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SCRREG                   GPIO_E_SCR_06_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_WORD_COUNT                       0x1
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_E_DEBOUNCE_THRESHOLD_06_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INPUT_06_0
+#define GPIO_E_INPUT_06_0                       MK_ADDR_CONST(0x156c8)
+#define GPIO_E_INPUT_06_0_SECURE                        0x0
+#define GPIO_E_INPUT_06_0_DUAL                  0x0
+#define GPIO_E_INPUT_06_0_SCR                   GPIO_E_SCR_06_0
+#define GPIO_E_INPUT_06_0_SCRREG                        GPIO_E_SCR_06_0
+#define GPIO_E_INPUT_06_0_WORD_COUNT                    0x1
+#define GPIO_E_INPUT_06_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_06_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_06_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_06_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_06_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_INPUT_06_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_06_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_06_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_E_INPUT_06_0_GPIO_IN_SHIFT)
+#define GPIO_E_INPUT_06_0_GPIO_IN_RANGE                 0:0
+#define GPIO_E_INPUT_06_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_06_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_06_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_E_INPUT_06_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_06_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_06_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_06_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_06_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_06_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_OUTPUT_CONTROL_06_0
+#define GPIO_E_OUTPUT_CONTROL_06_0                      MK_ADDR_CONST(0x156cc)
+#define GPIO_E_OUTPUT_CONTROL_06_0_SECURE                       0x0
+#define GPIO_E_OUTPUT_CONTROL_06_0_DUAL                         0x0
+#define GPIO_E_OUTPUT_CONTROL_06_0_SCR                  GPIO_E_SCR_06_0
+#define GPIO_E_OUTPUT_CONTROL_06_0_SCRREG                       GPIO_E_SCR_06_0
+#define GPIO_E_OUTPUT_CONTROL_06_0_WORD_COUNT                   0x1
+#define GPIO_E_OUTPUT_CONTROL_06_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_06_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_06_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_06_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_06_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_06_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_06_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_E_OUTPUT_VALUE_06_0
+#define GPIO_E_OUTPUT_VALUE_06_0                        MK_ADDR_CONST(0x156d0)
+#define GPIO_E_OUTPUT_VALUE_06_0_SECURE                         0x0
+#define GPIO_E_OUTPUT_VALUE_06_0_DUAL                   0x0
+#define GPIO_E_OUTPUT_VALUE_06_0_SCR                    GPIO_E_SCR_06_0
+#define GPIO_E_OUTPUT_VALUE_06_0_SCRREG                         GPIO_E_SCR_06_0
+#define GPIO_E_OUTPUT_VALUE_06_0_WORD_COUNT                     0x1
+#define GPIO_E_OUTPUT_VALUE_06_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_06_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_06_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_06_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_06_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_06_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_06_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INTERRUPT_CLEAR_06_0
+#define GPIO_E_INTERRUPT_CLEAR_06_0                     MK_ADDR_CONST(0x156d4)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_SECURE                      0x0
+#define GPIO_E_INTERRUPT_CLEAR_06_0_DUAL                        0x0
+#define GPIO_E_INTERRUPT_CLEAR_06_0_SCR                         GPIO_E_SCR_06_0
+#define GPIO_E_INTERRUPT_CLEAR_06_0_SCRREG                      GPIO_E_SCR_06_0
+#define GPIO_E_INTERRUPT_CLEAR_06_0_WORD_COUNT                  0x1
+#define GPIO_E_INTERRUPT_CLEAR_06_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_06_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x156d8
+
+// Reserved address 0x156dc
+
+// Register GPIO_E_ENABLE_CONFIG_07_0
+#define GPIO_E_ENABLE_CONFIG_07_0                       MK_ADDR_CONST(0x156e0)
+#define GPIO_E_ENABLE_CONFIG_07_0_SECURE                        0x0
+#define GPIO_E_ENABLE_CONFIG_07_0_DUAL                  0x0
+#define GPIO_E_ENABLE_CONFIG_07_0_SCR                   GPIO_E_SCR_07_0
+#define GPIO_E_ENABLE_CONFIG_07_0_SCRREG                        GPIO_E_SCR_07_0
+#define GPIO_E_ENABLE_CONFIG_07_0_WORD_COUNT                    0x1
+#define GPIO_E_ENABLE_CONFIG_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_07_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_07_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_RANGE                  1:1
+#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_07_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_07_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_07_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_07_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_E_ENABLE_CONFIG_07_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_E_DEBOUNCE_THRESHOLD_07_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0                  MK_ADDR_CONST(0x156e4)
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SECURE                   0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DUAL                     0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SCR                      GPIO_E_SCR_07_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SCRREG                   GPIO_E_SCR_07_0
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_WORD_COUNT                       0x1
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_E_DEBOUNCE_THRESHOLD_07_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INPUT_07_0
+#define GPIO_E_INPUT_07_0                       MK_ADDR_CONST(0x156e8)
+#define GPIO_E_INPUT_07_0_SECURE                        0x0
+#define GPIO_E_INPUT_07_0_DUAL                  0x0
+#define GPIO_E_INPUT_07_0_SCR                   GPIO_E_SCR_07_0
+#define GPIO_E_INPUT_07_0_SCRREG                        GPIO_E_SCR_07_0
+#define GPIO_E_INPUT_07_0_WORD_COUNT                    0x1
+#define GPIO_E_INPUT_07_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_07_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_07_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_07_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_07_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_INPUT_07_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_07_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_07_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_E_INPUT_07_0_GPIO_IN_SHIFT)
+#define GPIO_E_INPUT_07_0_GPIO_IN_RANGE                 0:0
+#define GPIO_E_INPUT_07_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_07_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_E_INPUT_07_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_E_INPUT_07_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_07_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_07_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_07_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_07_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_E_INPUT_07_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_OUTPUT_CONTROL_07_0
+#define GPIO_E_OUTPUT_CONTROL_07_0                      MK_ADDR_CONST(0x156ec)
+#define GPIO_E_OUTPUT_CONTROL_07_0_SECURE                       0x0
+#define GPIO_E_OUTPUT_CONTROL_07_0_DUAL                         0x0
+#define GPIO_E_OUTPUT_CONTROL_07_0_SCR                  GPIO_E_SCR_07_0
+#define GPIO_E_OUTPUT_CONTROL_07_0_SCRREG                       GPIO_E_SCR_07_0
+#define GPIO_E_OUTPUT_CONTROL_07_0_WORD_COUNT                   0x1
+#define GPIO_E_OUTPUT_CONTROL_07_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_07_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_07_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_07_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_07_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_07_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_E_OUTPUT_CONTROL_07_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_E_OUTPUT_VALUE_07_0
+#define GPIO_E_OUTPUT_VALUE_07_0                        MK_ADDR_CONST(0x156f0)
+#define GPIO_E_OUTPUT_VALUE_07_0_SECURE                         0x0
+#define GPIO_E_OUTPUT_VALUE_07_0_DUAL                   0x0
+#define GPIO_E_OUTPUT_VALUE_07_0_SCR                    GPIO_E_SCR_07_0
+#define GPIO_E_OUTPUT_VALUE_07_0_SCRREG                         GPIO_E_SCR_07_0
+#define GPIO_E_OUTPUT_VALUE_07_0_WORD_COUNT                     0x1
+#define GPIO_E_OUTPUT_VALUE_07_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_07_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_07_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_07_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_07_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_07_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_E_OUTPUT_VALUE_07_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INTERRUPT_CLEAR_07_0
+#define GPIO_E_INTERRUPT_CLEAR_07_0                     MK_ADDR_CONST(0x156f4)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_SECURE                      0x0
+#define GPIO_E_INTERRUPT_CLEAR_07_0_DUAL                        0x0
+#define GPIO_E_INTERRUPT_CLEAR_07_0_SCR                         GPIO_E_SCR_07_0
+#define GPIO_E_INTERRUPT_CLEAR_07_0_SCRREG                      GPIO_E_SCR_07_0
+#define GPIO_E_INTERRUPT_CLEAR_07_0_WORD_COUNT                  0x1
+#define GPIO_E_INTERRUPT_CLEAR_07_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_E_INTERRUPT_CLEAR_07_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x156f8
+
+// Reserved address 0x156fc
+
+// Register GPIO_E_INTERRUPT_STATUS_G0_0
+#define GPIO_E_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x15700)
+#define GPIO_E_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_E_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_E_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_E_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_E_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_E_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INTERRUPT_STATUS_G1_0
+#define GPIO_E_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x15704)
+#define GPIO_E_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_E_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_E_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_E_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_E_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_E_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INTERRUPT_STATUS_G2_0
+#define GPIO_E_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x15708)
+#define GPIO_E_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_E_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_E_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_E_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_E_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_E_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INTERRUPT_STATUS_G3_0
+#define GPIO_E_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1570c)
+#define GPIO_E_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_E_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_E_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_E_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_E_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_E_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INTERRUPT_STATUS_G4_0
+#define GPIO_E_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x15710)
+#define GPIO_E_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_E_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_E_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_E_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_E_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_E_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INTERRUPT_STATUS_G5_0
+#define GPIO_E_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x15714)
+#define GPIO_E_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_E_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_E_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_E_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_E_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_E_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INTERRUPT_STATUS_G6_0
+#define GPIO_E_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x15718)
+#define GPIO_E_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_E_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_E_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_E_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_E_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_E_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_E_INTERRUPT_STATUS_G7_0
+#define GPIO_E_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1571c)
+#define GPIO_E_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_E_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_E_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_E_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_E_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_E_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0xff, GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        7:0
+#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(7)
+#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_E_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x15720
+
+// Reserved address 0x15724
+
+// Reserved address 0x15728
+
+// Reserved address 0x1572c
+
+// Reserved address 0x15730
+
+// Reserved address 0x15734
+
+// Reserved address 0x15738
+
+// Reserved address 0x1573c
+
+// Reserved address 0x15740
+
+// Reserved address 0x15744
+
+// Reserved address 0x15748
+
+// Reserved address 0x1574c
+
+// Reserved address 0x15750
+
+// Reserved address 0x15754
+
+// Reserved address 0x15758
+
+// Reserved address 0x1575c
+
+// Reserved address 0x15760
+
+// Reserved address 0x15764
+
+// Reserved address 0x15768
+
+// Reserved address 0x1576c
+
+// Reserved address 0x15770
+
+// Reserved address 0x15774
+
+// Reserved address 0x15778
+
+// Reserved address 0x1577c
+
+// Reserved address 0x15780
+
+// Reserved address 0x15784
+
+// Reserved address 0x15788
+
+// Reserved address 0x1578c
+
+// Reserved address 0x15790
+
+// Reserved address 0x15794
+
+// Reserved address 0x15798
+
+// Reserved address 0x1579c
+
+// Reserved address 0x157a0
+
+// Reserved address 0x157a4
+
+// Reserved address 0x157a8
+
+// Reserved address 0x157ac
+
+// Reserved address 0x157b0
+
+// Reserved address 0x157b4
+
+// Reserved address 0x157b8
+
+// Reserved address 0x157bc
+
+// Reserved address 0x157c0
+
+// Reserved address 0x157c4
+
+// Reserved address 0x157c8
+
+// Reserved address 0x157cc
+
+// Reserved address 0x157d0
+
+// Reserved address 0x157d4
+
+// Reserved address 0x157d8
+
+// Reserved address 0x157dc
+
+// Reserved address 0x157e0
+
+// Reserved address 0x157e4
+
+// Reserved address 0x157e8
+
+// Reserved address 0x157ec
+
+// Reserved address 0x157f0
+
+// Reserved address 0x157f4
+
+// Reserved address 0x157f8
+
+// Reserved address 0x157fc
+
+// Register GPIO_F_ENABLE_CONFIG_00_0
+#define GPIO_F_ENABLE_CONFIG_00_0                       MK_ADDR_CONST(0x15800)
+#define GPIO_F_ENABLE_CONFIG_00_0_SECURE                        0x0
+#define GPIO_F_ENABLE_CONFIG_00_0_DUAL                  0x0
+#define GPIO_F_ENABLE_CONFIG_00_0_SCR                   GPIO_F_SCR_00_0
+#define GPIO_F_ENABLE_CONFIG_00_0_SCRREG                        GPIO_F_SCR_00_0
+#define GPIO_F_ENABLE_CONFIG_00_0_WORD_COUNT                    0x1
+#define GPIO_F_ENABLE_CONFIG_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_00_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_00_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_RANGE                  1:1
+#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_00_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_00_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_00_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_00_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_00_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_F_DEBOUNCE_THRESHOLD_00_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0                  MK_ADDR_CONST(0x15804)
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SECURE                   0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DUAL                     0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SCR                      GPIO_F_SCR_00_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SCRREG                   GPIO_F_SCR_00_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_WORD_COUNT                       0x1
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_F_DEBOUNCE_THRESHOLD_00_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INPUT_00_0
+#define GPIO_F_INPUT_00_0                       MK_ADDR_CONST(0x15808)
+#define GPIO_F_INPUT_00_0_SECURE                        0x0
+#define GPIO_F_INPUT_00_0_DUAL                  0x0
+#define GPIO_F_INPUT_00_0_SCR                   GPIO_F_SCR_00_0
+#define GPIO_F_INPUT_00_0_SCRREG                        GPIO_F_SCR_00_0
+#define GPIO_F_INPUT_00_0_WORD_COUNT                    0x1
+#define GPIO_F_INPUT_00_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_00_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_00_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_00_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_00_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_INPUT_00_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_00_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_00_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_F_INPUT_00_0_GPIO_IN_SHIFT)
+#define GPIO_F_INPUT_00_0_GPIO_IN_RANGE                 0:0
+#define GPIO_F_INPUT_00_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_00_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_00_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_F_INPUT_00_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_00_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_00_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_00_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_00_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_00_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_OUTPUT_CONTROL_00_0
+#define GPIO_F_OUTPUT_CONTROL_00_0                      MK_ADDR_CONST(0x1580c)
+#define GPIO_F_OUTPUT_CONTROL_00_0_SECURE                       0x0
+#define GPIO_F_OUTPUT_CONTROL_00_0_DUAL                         0x0
+#define GPIO_F_OUTPUT_CONTROL_00_0_SCR                  GPIO_F_SCR_00_0
+#define GPIO_F_OUTPUT_CONTROL_00_0_SCRREG                       GPIO_F_SCR_00_0
+#define GPIO_F_OUTPUT_CONTROL_00_0_WORD_COUNT                   0x1
+#define GPIO_F_OUTPUT_CONTROL_00_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_00_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_00_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_00_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_00_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_00_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_00_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_F_OUTPUT_VALUE_00_0
+#define GPIO_F_OUTPUT_VALUE_00_0                        MK_ADDR_CONST(0x15810)
+#define GPIO_F_OUTPUT_VALUE_00_0_SECURE                         0x0
+#define GPIO_F_OUTPUT_VALUE_00_0_DUAL                   0x0
+#define GPIO_F_OUTPUT_VALUE_00_0_SCR                    GPIO_F_SCR_00_0
+#define GPIO_F_OUTPUT_VALUE_00_0_SCRREG                         GPIO_F_SCR_00_0
+#define GPIO_F_OUTPUT_VALUE_00_0_WORD_COUNT                     0x1
+#define GPIO_F_OUTPUT_VALUE_00_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_00_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_00_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_00_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_00_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_00_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_00_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INTERRUPT_CLEAR_00_0
+#define GPIO_F_INTERRUPT_CLEAR_00_0                     MK_ADDR_CONST(0x15814)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_SECURE                      0x0
+#define GPIO_F_INTERRUPT_CLEAR_00_0_DUAL                        0x0
+#define GPIO_F_INTERRUPT_CLEAR_00_0_SCR                         GPIO_F_SCR_00_0
+#define GPIO_F_INTERRUPT_CLEAR_00_0_SCRREG                      GPIO_F_SCR_00_0
+#define GPIO_F_INTERRUPT_CLEAR_00_0_WORD_COUNT                  0x1
+#define GPIO_F_INTERRUPT_CLEAR_00_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_00_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15818
+
+// Reserved address 0x1581c
+
+// Register GPIO_F_ENABLE_CONFIG_01_0
+#define GPIO_F_ENABLE_CONFIG_01_0                       MK_ADDR_CONST(0x15820)
+#define GPIO_F_ENABLE_CONFIG_01_0_SECURE                        0x0
+#define GPIO_F_ENABLE_CONFIG_01_0_DUAL                  0x0
+#define GPIO_F_ENABLE_CONFIG_01_0_SCR                   GPIO_F_SCR_01_0
+#define GPIO_F_ENABLE_CONFIG_01_0_SCRREG                        GPIO_F_SCR_01_0
+#define GPIO_F_ENABLE_CONFIG_01_0_WORD_COUNT                    0x1
+#define GPIO_F_ENABLE_CONFIG_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_01_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_01_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_RANGE                  1:1
+#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_01_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_01_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_01_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_01_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_01_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_F_DEBOUNCE_THRESHOLD_01_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0                  MK_ADDR_CONST(0x15824)
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SECURE                   0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DUAL                     0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SCR                      GPIO_F_SCR_01_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SCRREG                   GPIO_F_SCR_01_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_WORD_COUNT                       0x1
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_F_DEBOUNCE_THRESHOLD_01_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INPUT_01_0
+#define GPIO_F_INPUT_01_0                       MK_ADDR_CONST(0x15828)
+#define GPIO_F_INPUT_01_0_SECURE                        0x0
+#define GPIO_F_INPUT_01_0_DUAL                  0x0
+#define GPIO_F_INPUT_01_0_SCR                   GPIO_F_SCR_01_0
+#define GPIO_F_INPUT_01_0_SCRREG                        GPIO_F_SCR_01_0
+#define GPIO_F_INPUT_01_0_WORD_COUNT                    0x1
+#define GPIO_F_INPUT_01_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_01_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_01_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_01_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_01_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_INPUT_01_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_01_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_01_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_F_INPUT_01_0_GPIO_IN_SHIFT)
+#define GPIO_F_INPUT_01_0_GPIO_IN_RANGE                 0:0
+#define GPIO_F_INPUT_01_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_01_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_01_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_F_INPUT_01_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_01_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_01_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_01_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_01_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_01_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_OUTPUT_CONTROL_01_0
+#define GPIO_F_OUTPUT_CONTROL_01_0                      MK_ADDR_CONST(0x1582c)
+#define GPIO_F_OUTPUT_CONTROL_01_0_SECURE                       0x0
+#define GPIO_F_OUTPUT_CONTROL_01_0_DUAL                         0x0
+#define GPIO_F_OUTPUT_CONTROL_01_0_SCR                  GPIO_F_SCR_01_0
+#define GPIO_F_OUTPUT_CONTROL_01_0_SCRREG                       GPIO_F_SCR_01_0
+#define GPIO_F_OUTPUT_CONTROL_01_0_WORD_COUNT                   0x1
+#define GPIO_F_OUTPUT_CONTROL_01_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_01_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_01_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_01_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_01_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_01_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_01_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_F_OUTPUT_VALUE_01_0
+#define GPIO_F_OUTPUT_VALUE_01_0                        MK_ADDR_CONST(0x15830)
+#define GPIO_F_OUTPUT_VALUE_01_0_SECURE                         0x0
+#define GPIO_F_OUTPUT_VALUE_01_0_DUAL                   0x0
+#define GPIO_F_OUTPUT_VALUE_01_0_SCR                    GPIO_F_SCR_01_0
+#define GPIO_F_OUTPUT_VALUE_01_0_SCRREG                         GPIO_F_SCR_01_0
+#define GPIO_F_OUTPUT_VALUE_01_0_WORD_COUNT                     0x1
+#define GPIO_F_OUTPUT_VALUE_01_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_01_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_01_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_01_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_01_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_01_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_01_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INTERRUPT_CLEAR_01_0
+#define GPIO_F_INTERRUPT_CLEAR_01_0                     MK_ADDR_CONST(0x15834)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_SECURE                      0x0
+#define GPIO_F_INTERRUPT_CLEAR_01_0_DUAL                        0x0
+#define GPIO_F_INTERRUPT_CLEAR_01_0_SCR                         GPIO_F_SCR_01_0
+#define GPIO_F_INTERRUPT_CLEAR_01_0_SCRREG                      GPIO_F_SCR_01_0
+#define GPIO_F_INTERRUPT_CLEAR_01_0_WORD_COUNT                  0x1
+#define GPIO_F_INTERRUPT_CLEAR_01_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_01_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15838
+
+// Reserved address 0x1583c
+
+// Register GPIO_F_ENABLE_CONFIG_02_0
+#define GPIO_F_ENABLE_CONFIG_02_0                       MK_ADDR_CONST(0x15840)
+#define GPIO_F_ENABLE_CONFIG_02_0_SECURE                        0x0
+#define GPIO_F_ENABLE_CONFIG_02_0_DUAL                  0x0
+#define GPIO_F_ENABLE_CONFIG_02_0_SCR                   GPIO_F_SCR_02_0
+#define GPIO_F_ENABLE_CONFIG_02_0_SCRREG                        GPIO_F_SCR_02_0
+#define GPIO_F_ENABLE_CONFIG_02_0_WORD_COUNT                    0x1
+#define GPIO_F_ENABLE_CONFIG_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_02_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_02_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_RANGE                  1:1
+#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_02_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_02_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_02_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_02_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_02_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_F_DEBOUNCE_THRESHOLD_02_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0                  MK_ADDR_CONST(0x15844)
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SECURE                   0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DUAL                     0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SCR                      GPIO_F_SCR_02_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SCRREG                   GPIO_F_SCR_02_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_WORD_COUNT                       0x1
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_F_DEBOUNCE_THRESHOLD_02_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INPUT_02_0
+#define GPIO_F_INPUT_02_0                       MK_ADDR_CONST(0x15848)
+#define GPIO_F_INPUT_02_0_SECURE                        0x0
+#define GPIO_F_INPUT_02_0_DUAL                  0x0
+#define GPIO_F_INPUT_02_0_SCR                   GPIO_F_SCR_02_0
+#define GPIO_F_INPUT_02_0_SCRREG                        GPIO_F_SCR_02_0
+#define GPIO_F_INPUT_02_0_WORD_COUNT                    0x1
+#define GPIO_F_INPUT_02_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_02_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_02_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_02_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_02_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_INPUT_02_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_02_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_02_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_F_INPUT_02_0_GPIO_IN_SHIFT)
+#define GPIO_F_INPUT_02_0_GPIO_IN_RANGE                 0:0
+#define GPIO_F_INPUT_02_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_02_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_02_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_F_INPUT_02_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_02_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_02_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_02_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_02_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_02_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_OUTPUT_CONTROL_02_0
+#define GPIO_F_OUTPUT_CONTROL_02_0                      MK_ADDR_CONST(0x1584c)
+#define GPIO_F_OUTPUT_CONTROL_02_0_SECURE                       0x0
+#define GPIO_F_OUTPUT_CONTROL_02_0_DUAL                         0x0
+#define GPIO_F_OUTPUT_CONTROL_02_0_SCR                  GPIO_F_SCR_02_0
+#define GPIO_F_OUTPUT_CONTROL_02_0_SCRREG                       GPIO_F_SCR_02_0
+#define GPIO_F_OUTPUT_CONTROL_02_0_WORD_COUNT                   0x1
+#define GPIO_F_OUTPUT_CONTROL_02_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_02_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_02_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_02_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_02_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_02_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_02_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_F_OUTPUT_VALUE_02_0
+#define GPIO_F_OUTPUT_VALUE_02_0                        MK_ADDR_CONST(0x15850)
+#define GPIO_F_OUTPUT_VALUE_02_0_SECURE                         0x0
+#define GPIO_F_OUTPUT_VALUE_02_0_DUAL                   0x0
+#define GPIO_F_OUTPUT_VALUE_02_0_SCR                    GPIO_F_SCR_02_0
+#define GPIO_F_OUTPUT_VALUE_02_0_SCRREG                         GPIO_F_SCR_02_0
+#define GPIO_F_OUTPUT_VALUE_02_0_WORD_COUNT                     0x1
+#define GPIO_F_OUTPUT_VALUE_02_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_02_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_02_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_02_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_02_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_02_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_02_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INTERRUPT_CLEAR_02_0
+#define GPIO_F_INTERRUPT_CLEAR_02_0                     MK_ADDR_CONST(0x15854)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_SECURE                      0x0
+#define GPIO_F_INTERRUPT_CLEAR_02_0_DUAL                        0x0
+#define GPIO_F_INTERRUPT_CLEAR_02_0_SCR                         GPIO_F_SCR_02_0
+#define GPIO_F_INTERRUPT_CLEAR_02_0_SCRREG                      GPIO_F_SCR_02_0
+#define GPIO_F_INTERRUPT_CLEAR_02_0_WORD_COUNT                  0x1
+#define GPIO_F_INTERRUPT_CLEAR_02_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_02_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15858
+
+// Reserved address 0x1585c
+
+// Register GPIO_F_ENABLE_CONFIG_03_0
+#define GPIO_F_ENABLE_CONFIG_03_0                       MK_ADDR_CONST(0x15860)
+#define GPIO_F_ENABLE_CONFIG_03_0_SECURE                        0x0
+#define GPIO_F_ENABLE_CONFIG_03_0_DUAL                  0x0
+#define GPIO_F_ENABLE_CONFIG_03_0_SCR                   GPIO_F_SCR_03_0
+#define GPIO_F_ENABLE_CONFIG_03_0_SCRREG                        GPIO_F_SCR_03_0
+#define GPIO_F_ENABLE_CONFIG_03_0_WORD_COUNT                    0x1
+#define GPIO_F_ENABLE_CONFIG_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_03_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_03_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_RANGE                  1:1
+#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_03_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_03_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_03_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_03_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_03_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_F_DEBOUNCE_THRESHOLD_03_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0                  MK_ADDR_CONST(0x15864)
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SECURE                   0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DUAL                     0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SCR                      GPIO_F_SCR_03_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SCRREG                   GPIO_F_SCR_03_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_WORD_COUNT                       0x1
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_F_DEBOUNCE_THRESHOLD_03_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INPUT_03_0
+#define GPIO_F_INPUT_03_0                       MK_ADDR_CONST(0x15868)
+#define GPIO_F_INPUT_03_0_SECURE                        0x0
+#define GPIO_F_INPUT_03_0_DUAL                  0x0
+#define GPIO_F_INPUT_03_0_SCR                   GPIO_F_SCR_03_0
+#define GPIO_F_INPUT_03_0_SCRREG                        GPIO_F_SCR_03_0
+#define GPIO_F_INPUT_03_0_WORD_COUNT                    0x1
+#define GPIO_F_INPUT_03_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_03_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_03_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_03_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_03_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_INPUT_03_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_03_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_03_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_F_INPUT_03_0_GPIO_IN_SHIFT)
+#define GPIO_F_INPUT_03_0_GPIO_IN_RANGE                 0:0
+#define GPIO_F_INPUT_03_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_03_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_03_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_F_INPUT_03_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_03_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_03_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_03_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_03_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_03_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_OUTPUT_CONTROL_03_0
+#define GPIO_F_OUTPUT_CONTROL_03_0                      MK_ADDR_CONST(0x1586c)
+#define GPIO_F_OUTPUT_CONTROL_03_0_SECURE                       0x0
+#define GPIO_F_OUTPUT_CONTROL_03_0_DUAL                         0x0
+#define GPIO_F_OUTPUT_CONTROL_03_0_SCR                  GPIO_F_SCR_03_0
+#define GPIO_F_OUTPUT_CONTROL_03_0_SCRREG                       GPIO_F_SCR_03_0
+#define GPIO_F_OUTPUT_CONTROL_03_0_WORD_COUNT                   0x1
+#define GPIO_F_OUTPUT_CONTROL_03_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_03_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_03_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_03_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_03_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_03_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_03_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_F_OUTPUT_VALUE_03_0
+#define GPIO_F_OUTPUT_VALUE_03_0                        MK_ADDR_CONST(0x15870)
+#define GPIO_F_OUTPUT_VALUE_03_0_SECURE                         0x0
+#define GPIO_F_OUTPUT_VALUE_03_0_DUAL                   0x0
+#define GPIO_F_OUTPUT_VALUE_03_0_SCR                    GPIO_F_SCR_03_0
+#define GPIO_F_OUTPUT_VALUE_03_0_SCRREG                         GPIO_F_SCR_03_0
+#define GPIO_F_OUTPUT_VALUE_03_0_WORD_COUNT                     0x1
+#define GPIO_F_OUTPUT_VALUE_03_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_03_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_03_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_03_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_03_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_03_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_03_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INTERRUPT_CLEAR_03_0
+#define GPIO_F_INTERRUPT_CLEAR_03_0                     MK_ADDR_CONST(0x15874)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_SECURE                      0x0
+#define GPIO_F_INTERRUPT_CLEAR_03_0_DUAL                        0x0
+#define GPIO_F_INTERRUPT_CLEAR_03_0_SCR                         GPIO_F_SCR_03_0
+#define GPIO_F_INTERRUPT_CLEAR_03_0_SCRREG                      GPIO_F_SCR_03_0
+#define GPIO_F_INTERRUPT_CLEAR_03_0_WORD_COUNT                  0x1
+#define GPIO_F_INTERRUPT_CLEAR_03_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_03_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15878
+
+// Reserved address 0x1587c
+
+// Register GPIO_F_ENABLE_CONFIG_04_0
+#define GPIO_F_ENABLE_CONFIG_04_0                       MK_ADDR_CONST(0x15880)
+#define GPIO_F_ENABLE_CONFIG_04_0_SECURE                        0x0
+#define GPIO_F_ENABLE_CONFIG_04_0_DUAL                  0x0
+#define GPIO_F_ENABLE_CONFIG_04_0_SCR                   GPIO_F_SCR_04_0
+#define GPIO_F_ENABLE_CONFIG_04_0_SCRREG                        GPIO_F_SCR_04_0
+#define GPIO_F_ENABLE_CONFIG_04_0_WORD_COUNT                    0x1
+#define GPIO_F_ENABLE_CONFIG_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_04_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_04_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_RANGE                  1:1
+#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_04_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_04_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_04_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_04_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_04_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_F_DEBOUNCE_THRESHOLD_04_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0                  MK_ADDR_CONST(0x15884)
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SECURE                   0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DUAL                     0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SCR                      GPIO_F_SCR_04_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SCRREG                   GPIO_F_SCR_04_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_WORD_COUNT                       0x1
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_F_DEBOUNCE_THRESHOLD_04_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INPUT_04_0
+#define GPIO_F_INPUT_04_0                       MK_ADDR_CONST(0x15888)
+#define GPIO_F_INPUT_04_0_SECURE                        0x0
+#define GPIO_F_INPUT_04_0_DUAL                  0x0
+#define GPIO_F_INPUT_04_0_SCR                   GPIO_F_SCR_04_0
+#define GPIO_F_INPUT_04_0_SCRREG                        GPIO_F_SCR_04_0
+#define GPIO_F_INPUT_04_0_WORD_COUNT                    0x1
+#define GPIO_F_INPUT_04_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_04_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_04_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_04_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_04_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_INPUT_04_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_04_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_04_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_F_INPUT_04_0_GPIO_IN_SHIFT)
+#define GPIO_F_INPUT_04_0_GPIO_IN_RANGE                 0:0
+#define GPIO_F_INPUT_04_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_04_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_04_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_F_INPUT_04_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_04_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_04_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_04_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_04_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_04_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_OUTPUT_CONTROL_04_0
+#define GPIO_F_OUTPUT_CONTROL_04_0                      MK_ADDR_CONST(0x1588c)
+#define GPIO_F_OUTPUT_CONTROL_04_0_SECURE                       0x0
+#define GPIO_F_OUTPUT_CONTROL_04_0_DUAL                         0x0
+#define GPIO_F_OUTPUT_CONTROL_04_0_SCR                  GPIO_F_SCR_04_0
+#define GPIO_F_OUTPUT_CONTROL_04_0_SCRREG                       GPIO_F_SCR_04_0
+#define GPIO_F_OUTPUT_CONTROL_04_0_WORD_COUNT                   0x1
+#define GPIO_F_OUTPUT_CONTROL_04_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_04_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_04_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_04_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_04_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_04_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_04_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_F_OUTPUT_VALUE_04_0
+#define GPIO_F_OUTPUT_VALUE_04_0                        MK_ADDR_CONST(0x15890)
+#define GPIO_F_OUTPUT_VALUE_04_0_SECURE                         0x0
+#define GPIO_F_OUTPUT_VALUE_04_0_DUAL                   0x0
+#define GPIO_F_OUTPUT_VALUE_04_0_SCR                    GPIO_F_SCR_04_0
+#define GPIO_F_OUTPUT_VALUE_04_0_SCRREG                         GPIO_F_SCR_04_0
+#define GPIO_F_OUTPUT_VALUE_04_0_WORD_COUNT                     0x1
+#define GPIO_F_OUTPUT_VALUE_04_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_04_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_04_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_04_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_04_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_04_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_04_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INTERRUPT_CLEAR_04_0
+#define GPIO_F_INTERRUPT_CLEAR_04_0                     MK_ADDR_CONST(0x15894)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_SECURE                      0x0
+#define GPIO_F_INTERRUPT_CLEAR_04_0_DUAL                        0x0
+#define GPIO_F_INTERRUPT_CLEAR_04_0_SCR                         GPIO_F_SCR_04_0
+#define GPIO_F_INTERRUPT_CLEAR_04_0_SCRREG                      GPIO_F_SCR_04_0
+#define GPIO_F_INTERRUPT_CLEAR_04_0_WORD_COUNT                  0x1
+#define GPIO_F_INTERRUPT_CLEAR_04_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_04_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x15898
+
+// Reserved address 0x1589c
+
+// Register GPIO_F_ENABLE_CONFIG_05_0
+#define GPIO_F_ENABLE_CONFIG_05_0                       MK_ADDR_CONST(0x158a0)
+#define GPIO_F_ENABLE_CONFIG_05_0_SECURE                        0x0
+#define GPIO_F_ENABLE_CONFIG_05_0_DUAL                  0x0
+#define GPIO_F_ENABLE_CONFIG_05_0_SCR                   GPIO_F_SCR_05_0
+#define GPIO_F_ENABLE_CONFIG_05_0_SCRREG                        GPIO_F_SCR_05_0
+#define GPIO_F_ENABLE_CONFIG_05_0_WORD_COUNT                    0x1
+#define GPIO_F_ENABLE_CONFIG_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_05_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_RANGE                     0:0
+#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_WOFFSET                   0x0
+#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_05_0_GPIO_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_SHIFT                  MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_RANGE                  1:1
+#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_MSB                    MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_LSB                    MK_SHIFT_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_WOFFSET                        0x0
+#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_IN                     MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_05_0_IN_OUT_OUT                    MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT                    MK_SHIFT_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_FIELD                    MK_FIELD_CONST(0x3, GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_RANGE                    3:2
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_MSB                      MK_SHIFT_CONST(3)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LSB                      MK_SHIFT_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_WOFFSET                  0x0
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_NO_TRIGGER                       MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_LEVEL                    MK_ENUM_CONST(1)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_SINGLE_EDGE                      MK_ENUM_CONST(2)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_TYPE_DOUBLE_EDGE                      MK_ENUM_CONST(3)
+
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT                   MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_RANGE                   4:4
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_MSB                     MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LSB                     MK_SHIFT_CONST(4)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_WOFFSET                 0x0
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_LOW_LEVEL__FALLING_EDGE                 MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_05_0_TRIGGER_LEVEL_HIGH_LEVEL__RISING_EDGE                 MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT                       MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_RANGE                       5:5
+#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_MSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_LSB                 MK_SHIFT_CONST(5)
+#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_WOFFSET                     0x0
+#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_DISABLE                     MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_05_0_DEBOUNCE_FUNCTION_ENABLE                      MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT                      MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_FIELD                      MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_RANGE                      6:6
+#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_MSB                        MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_LSB                        MK_SHIFT_CONST(6)
+#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_WOFFSET                    0x0
+#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_DISABLE                    MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_05_0_INTERRUPT_FUNCTION_ENABLE                     MK_ENUM_CONST(1)
+
+#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT                   MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_FIELD                   MK_FIELD_CONST(0x1, GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SHIFT)
+#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_RANGE                   7:7
+#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_MSB                     MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_LSB                     MK_SHIFT_CONST(7)
+#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_WOFFSET                 0x0
+#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_DISABLE                 MK_ENUM_CONST(0)
+#define GPIO_F_ENABLE_CONFIG_05_0_TIMESTAMPING_FUNCTION_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register GPIO_F_DEBOUNCE_THRESHOLD_05_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0                  MK_ADDR_CONST(0x158a4)
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SECURE                   0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DUAL                     0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SCR                      GPIO_F_SCR_05_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SCRREG                   GPIO_F_SCR_05_0
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_WORD_COUNT                       0x1
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_READ_MASK                        MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_FIELD                 MK_FIELD_CONST(0xff, GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SHIFT)
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_RANGE                 7:0
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_MSB                   MK_SHIFT_CONST(7)
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_WOFFSET                       0x0
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define GPIO_F_DEBOUNCE_THRESHOLD_05_0_DEBOUNCE_THRESHOLD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INPUT_05_0
+#define GPIO_F_INPUT_05_0                       MK_ADDR_CONST(0x158a8)
+#define GPIO_F_INPUT_05_0_SECURE                        0x0
+#define GPIO_F_INPUT_05_0_DUAL                  0x0
+#define GPIO_F_INPUT_05_0_SCR                   GPIO_F_SCR_05_0
+#define GPIO_F_INPUT_05_0_SCRREG                        GPIO_F_SCR_05_0
+#define GPIO_F_INPUT_05_0_WORD_COUNT                    0x1
+#define GPIO_F_INPUT_05_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_05_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_05_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_05_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_05_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_INPUT_05_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_05_0_GPIO_IN_SHIFT                 MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_05_0_GPIO_IN_FIELD                 MK_FIELD_CONST(0x1, GPIO_F_INPUT_05_0_GPIO_IN_SHIFT)
+#define GPIO_F_INPUT_05_0_GPIO_IN_RANGE                 0:0
+#define GPIO_F_INPUT_05_0_GPIO_IN_MSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_05_0_GPIO_IN_LSB                   MK_SHIFT_CONST(0)
+#define GPIO_F_INPUT_05_0_GPIO_IN_WOFFSET                       0x0
+#define GPIO_F_INPUT_05_0_GPIO_IN_DEFAULT                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_05_0_GPIO_IN_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_05_0_GPIO_IN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_05_0_GPIO_IN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_05_0_GPIO_IN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GPIO_F_INPUT_05_0_GPIO_IN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_OUTPUT_CONTROL_05_0
+#define GPIO_F_OUTPUT_CONTROL_05_0                      MK_ADDR_CONST(0x158ac)
+#define GPIO_F_OUTPUT_CONTROL_05_0_SECURE                       0x0
+#define GPIO_F_OUTPUT_CONTROL_05_0_DUAL                         0x0
+#define GPIO_F_OUTPUT_CONTROL_05_0_SCR                  GPIO_F_SCR_05_0
+#define GPIO_F_OUTPUT_CONTROL_05_0_SCRREG                       GPIO_F_SCR_05_0
+#define GPIO_F_OUTPUT_CONTROL_05_0_WORD_COUNT                   0x1
+#define GPIO_F_OUTPUT_CONTROL_05_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_05_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_05_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_05_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_05_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_05_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FIELD                       MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SHIFT)
+#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_RANGE                       0:0
+#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_MSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_LSB                 MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_WOFFSET                     0x0
+#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_DRIVEN                      MK_ENUM_CONST(0)
+#define GPIO_F_OUTPUT_CONTROL_05_0_GPIO_OUT_CONTROL_FLOATED                     MK_ENUM_CONST(1)
+
+
+// Register GPIO_F_OUTPUT_VALUE_05_0
+#define GPIO_F_OUTPUT_VALUE_05_0                        MK_ADDR_CONST(0x158b0)
+#define GPIO_F_OUTPUT_VALUE_05_0_SECURE                         0x0
+#define GPIO_F_OUTPUT_VALUE_05_0_DUAL                   0x0
+#define GPIO_F_OUTPUT_VALUE_05_0_SCR                    GPIO_F_SCR_05_0
+#define GPIO_F_OUTPUT_VALUE_05_0_SCRREG                         GPIO_F_SCR_05_0
+#define GPIO_F_OUTPUT_VALUE_05_0_WORD_COUNT                     0x1
+#define GPIO_F_OUTPUT_VALUE_05_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_05_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_05_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_05_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_05_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_05_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT                     MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_FIELD                     MK_FIELD_CONST(0x1, GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SHIFT)
+#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_RANGE                     0:0
+#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_MSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_LSB                       MK_SHIFT_CONST(0)
+#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_WOFFSET                   0x0
+#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define GPIO_F_OUTPUT_VALUE_05_0_GPIO_OUT_VAL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INTERRUPT_CLEAR_05_0
+#define GPIO_F_INTERRUPT_CLEAR_05_0                     MK_ADDR_CONST(0x158b4)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_SECURE                      0x0
+#define GPIO_F_INTERRUPT_CLEAR_05_0_DUAL                        0x0
+#define GPIO_F_INTERRUPT_CLEAR_05_0_SCR                         GPIO_F_SCR_05_0
+#define GPIO_F_INTERRUPT_CLEAR_05_0_SCRREG                      GPIO_F_SCR_05_0
+#define GPIO_F_INTERRUPT_CLEAR_05_0_WORD_COUNT                  0x1
+#define GPIO_F_INTERRUPT_CLEAR_05_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT                  MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_FIELD                  MK_FIELD_CONST(0x1, GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SHIFT)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_RANGE                  0:0
+#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_MSB                    MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_LSB                    MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_WOFFSET                        0x0
+#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT                        MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_NOT_CLEAR                      MK_ENUM_CONST(0)
+#define GPIO_F_INTERRUPT_CLEAR_05_0_GPIO_INTERRUPT_CLEAR_CLEAR                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x158b8
+
+// Reserved address 0x158bc
+
+// Reserved address 0x158c0
+
+// Reserved address 0x158c4
+
+// Reserved address 0x158c8
+
+// Reserved address 0x158cc
+
+// Reserved address 0x158d0
+
+// Reserved address 0x158d4
+
+// Reserved address 0x158d8
+
+// Reserved address 0x158dc
+
+// Reserved address 0x158e0
+
+// Reserved address 0x158e4
+
+// Reserved address 0x158e8
+
+// Reserved address 0x158ec
+
+// Reserved address 0x158f0
+
+// Reserved address 0x158f4
+
+// Reserved address 0x158f8
+
+// Reserved address 0x158fc
+
+// Register GPIO_F_INTERRUPT_STATUS_G0_0
+#define GPIO_F_INTERRUPT_STATUS_G0_0                    MK_ADDR_CONST(0x15900)
+#define GPIO_F_INTERRUPT_STATUS_G0_0_SECURE                     0x0
+#define GPIO_F_INTERRUPT_STATUS_G0_0_DUAL                       0x0
+#define GPIO_F_INTERRUPT_STATUS_G0_0_SCR                        0
+#define GPIO_F_INTERRUPT_STATUS_G0_0_SCRREG                     0
+#define GPIO_F_INTERRUPT_STATUS_G0_0_WORD_COUNT                         0x1
+#define GPIO_F_INTERRUPT_STATUS_G0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G0_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G0_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G0_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INTERRUPT_STATUS_G1_0
+#define GPIO_F_INTERRUPT_STATUS_G1_0                    MK_ADDR_CONST(0x15904)
+#define GPIO_F_INTERRUPT_STATUS_G1_0_SECURE                     0x0
+#define GPIO_F_INTERRUPT_STATUS_G1_0_DUAL                       0x0
+#define GPIO_F_INTERRUPT_STATUS_G1_0_SCR                        0
+#define GPIO_F_INTERRUPT_STATUS_G1_0_SCRREG                     0
+#define GPIO_F_INTERRUPT_STATUS_G1_0_WORD_COUNT                         0x1
+#define GPIO_F_INTERRUPT_STATUS_G1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G1_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G1_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G1_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G1_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INTERRUPT_STATUS_G2_0
+#define GPIO_F_INTERRUPT_STATUS_G2_0                    MK_ADDR_CONST(0x15908)
+#define GPIO_F_INTERRUPT_STATUS_G2_0_SECURE                     0x0
+#define GPIO_F_INTERRUPT_STATUS_G2_0_DUAL                       0x0
+#define GPIO_F_INTERRUPT_STATUS_G2_0_SCR                        0
+#define GPIO_F_INTERRUPT_STATUS_G2_0_SCRREG                     0
+#define GPIO_F_INTERRUPT_STATUS_G2_0_WORD_COUNT                         0x1
+#define GPIO_F_INTERRUPT_STATUS_G2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G2_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G2_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G2_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G2_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INTERRUPT_STATUS_G3_0
+#define GPIO_F_INTERRUPT_STATUS_G3_0                    MK_ADDR_CONST(0x1590c)
+#define GPIO_F_INTERRUPT_STATUS_G3_0_SECURE                     0x0
+#define GPIO_F_INTERRUPT_STATUS_G3_0_DUAL                       0x0
+#define GPIO_F_INTERRUPT_STATUS_G3_0_SCR                        0
+#define GPIO_F_INTERRUPT_STATUS_G3_0_SCRREG                     0
+#define GPIO_F_INTERRUPT_STATUS_G3_0_WORD_COUNT                         0x1
+#define GPIO_F_INTERRUPT_STATUS_G3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G3_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G3_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G3_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G3_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INTERRUPT_STATUS_G4_0
+#define GPIO_F_INTERRUPT_STATUS_G4_0                    MK_ADDR_CONST(0x15910)
+#define GPIO_F_INTERRUPT_STATUS_G4_0_SECURE                     0x0
+#define GPIO_F_INTERRUPT_STATUS_G4_0_DUAL                       0x0
+#define GPIO_F_INTERRUPT_STATUS_G4_0_SCR                        0
+#define GPIO_F_INTERRUPT_STATUS_G4_0_SCRREG                     0
+#define GPIO_F_INTERRUPT_STATUS_G4_0_WORD_COUNT                         0x1
+#define GPIO_F_INTERRUPT_STATUS_G4_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G4_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G4_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G4_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G4_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G4_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G4_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INTERRUPT_STATUS_G5_0
+#define GPIO_F_INTERRUPT_STATUS_G5_0                    MK_ADDR_CONST(0x15914)
+#define GPIO_F_INTERRUPT_STATUS_G5_0_SECURE                     0x0
+#define GPIO_F_INTERRUPT_STATUS_G5_0_DUAL                       0x0
+#define GPIO_F_INTERRUPT_STATUS_G5_0_SCR                        0
+#define GPIO_F_INTERRUPT_STATUS_G5_0_SCRREG                     0
+#define GPIO_F_INTERRUPT_STATUS_G5_0_WORD_COUNT                         0x1
+#define GPIO_F_INTERRUPT_STATUS_G5_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G5_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G5_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G5_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G5_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G5_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G5_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INTERRUPT_STATUS_G6_0
+#define GPIO_F_INTERRUPT_STATUS_G6_0                    MK_ADDR_CONST(0x15918)
+#define GPIO_F_INTERRUPT_STATUS_G6_0_SECURE                     0x0
+#define GPIO_F_INTERRUPT_STATUS_G6_0_DUAL                       0x0
+#define GPIO_F_INTERRUPT_STATUS_G6_0_SCR                        0
+#define GPIO_F_INTERRUPT_STATUS_G6_0_SCRREG                     0
+#define GPIO_F_INTERRUPT_STATUS_G6_0_WORD_COUNT                         0x1
+#define GPIO_F_INTERRUPT_STATUS_G6_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G6_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G6_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G6_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G6_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G6_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G6_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GPIO_F_INTERRUPT_STATUS_G7_0
+#define GPIO_F_INTERRUPT_STATUS_G7_0                    MK_ADDR_CONST(0x1591c)
+#define GPIO_F_INTERRUPT_STATUS_G7_0_SECURE                     0x0
+#define GPIO_F_INTERRUPT_STATUS_G7_0_DUAL                       0x0
+#define GPIO_F_INTERRUPT_STATUS_G7_0_SCR                        0
+#define GPIO_F_INTERRUPT_STATUS_G7_0_SCRREG                     0
+#define GPIO_F_INTERRUPT_STATUS_G7_0_WORD_COUNT                         0x1
+#define GPIO_F_INTERRUPT_STATUS_G7_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G7_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G7_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G7_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G7_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G7_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_FIELD                        MK_FIELD_CONST(0x3f, GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SHIFT)
+#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_RANGE                        5:0
+#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_MSB                  MK_SHIFT_CONST(5)
+#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_WOFFSET                      0x0
+#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0x3f)
+#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define GPIO_F_INTERRUPT_STATUS_G7_0_GPIO_INTERRUPT_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x15920
+
+// Reserved address 0x15924
+
+// Reserved address 0x15928
+
+// Reserved address 0x1592c
+
+// Reserved address 0x15930
+
+// Reserved address 0x15934
+
+// Reserved address 0x15938
+
+// Reserved address 0x1593c
+
+// Reserved address 0x15940
+
+// Reserved address 0x15944
+
+// Reserved address 0x15948
+
+// Reserved address 0x1594c
+
+// Reserved address 0x15950
+
+// Reserved address 0x15954
+
+// Reserved address 0x15958
+
+// Reserved address 0x1595c
+
+// Reserved address 0x15960
+
+// Reserved address 0x15964
+
+// Reserved address 0x15968
+
+// Reserved address 0x1596c
+
+// Reserved address 0x15970
+
+// Reserved address 0x15974
+
+// Reserved address 0x15978
+
+// Reserved address 0x1597c
+
+// Reserved address 0x15980
+
+// Reserved address 0x15984
+
+// Reserved address 0x15988
+
+// Reserved address 0x1598c
+
+// Reserved address 0x15990
+
+// Reserved address 0x15994
+
+// Reserved address 0x15998
+
+// Reserved address 0x1599c
+
+// Reserved address 0x159a0
+
+// Reserved address 0x159a4
+
+// Reserved address 0x159a8
+
+// Reserved address 0x159ac
+
+// Reserved address 0x159b0
+
+// Reserved address 0x159b4
+
+// Reserved address 0x159b8
+
+// Reserved address 0x159bc
+
+// Reserved address 0x159c0
+
+// Reserved address 0x159c4
+
+// Reserved address 0x159c8
+
+// Reserved address 0x159cc
+
+// Reserved address 0x159d0
+
+// Reserved address 0x159d4
+
+// Reserved address 0x159d8
+
+// Reserved address 0x159dc
+
+// Reserved address 0x159e0
+
+// Reserved address 0x159e4
+
+// Reserved address 0x159e8
+
+// Reserved address 0x159ec
+
+// Reserved address 0x159f0
+
+// Reserved address 0x159f4
+
+// Reserved address 0x159f8
+
+// Reserved address 0x159fc
+
+//
+// REGISTER LIST
+//
+#define LIST_ARGPIO_REGS(_op_) \
+_op_(GPIO_A_VM_00_0) \
+_op_(GPIO_A_SCR_00_0) \
+_op_(GPIO_A_VM_01_0) \
+_op_(GPIO_A_SCR_01_0) \
+_op_(GPIO_A_VM_02_0) \
+_op_(GPIO_A_SCR_02_0) \
+_op_(GPIO_A_VM_03_0) \
+_op_(GPIO_A_SCR_03_0) \
+_op_(GPIO_A_VM_04_0) \
+_op_(GPIO_A_SCR_04_0) \
+_op_(GPIO_A_VM_05_0) \
+_op_(GPIO_A_SCR_05_0) \
+_op_(GPIO_A_VM_06_0) \
+_op_(GPIO_A_SCR_06_0) \
+_op_(GPIO_A_VM_07_0) \
+_op_(GPIO_A_SCR_07_0) \
+_op_(GPIO_AC_VM_00_0) \
+_op_(GPIO_AC_SCR_00_0) \
+_op_(GPIO_AC_VM_01_0) \
+_op_(GPIO_AC_SCR_01_0) \
+_op_(GPIO_AC_VM_02_0) \
+_op_(GPIO_AC_SCR_02_0) \
+_op_(GPIO_AC_VM_03_0) \
+_op_(GPIO_AC_SCR_03_0) \
+_op_(GPIO_AC_VM_04_0) \
+_op_(GPIO_AC_SCR_04_0) \
+_op_(GPIO_AC_VM_05_0) \
+_op_(GPIO_AC_SCR_05_0) \
+_op_(GPIO_AC_VM_06_0) \
+_op_(GPIO_AC_SCR_06_0) \
+_op_(GPIO_AC_VM_07_0) \
+_op_(GPIO_AC_SCR_07_0) \
+_op_(GPIO_AD_VM_00_0) \
+_op_(GPIO_AD_SCR_00_0) \
+_op_(GPIO_AD_VM_01_0) \
+_op_(GPIO_AD_SCR_01_0) \
+_op_(GPIO_AD_VM_02_0) \
+_op_(GPIO_AD_SCR_02_0) \
+_op_(GPIO_AD_VM_03_0) \
+_op_(GPIO_AD_SCR_03_0) \
+_op_(GPIO_B_VM_00_0) \
+_op_(GPIO_B_SCR_00_0) \
+_op_(GPIO_CTL0_VM_SCR_0) \
+_op_(GPIO_CTL0_INTERRUPT_STATUS_VM_SCR_0) \
+_op_(GPIO_CTL0_INTERRUPT_STATUS_VM_0) \
+_op_(GPIO_CTL0_SCR_0) \
+_op_(GPIO_CTL0_ICG_EN_OVERRIDE_0) \
+_op_(GPIO_A_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_A_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_A_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_A_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_A_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_A_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_A_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_A_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_AC_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_AC_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_AC_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_AC_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_AC_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_AC_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_AC_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_AC_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_AD_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_AD_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_AD_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_AD_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_AD_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_AD_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_AD_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_AD_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_B_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_B_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_B_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_B_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_B_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_B_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_B_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_B_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_CTL0_SPARE_0) \
+_op_(GPIO_X_VM_00_0) \
+_op_(GPIO_X_SCR_00_0) \
+_op_(GPIO_X_VM_01_0) \
+_op_(GPIO_X_SCR_01_0) \
+_op_(GPIO_X_VM_02_0) \
+_op_(GPIO_X_SCR_02_0) \
+_op_(GPIO_X_VM_03_0) \
+_op_(GPIO_X_SCR_03_0) \
+_op_(GPIO_X_VM_04_0) \
+_op_(GPIO_X_SCR_04_0) \
+_op_(GPIO_X_VM_05_0) \
+_op_(GPIO_X_SCR_05_0) \
+_op_(GPIO_X_VM_06_0) \
+_op_(GPIO_X_SCR_06_0) \
+_op_(GPIO_X_VM_07_0) \
+_op_(GPIO_X_SCR_07_0) \
+_op_(GPIO_Y_VM_00_0) \
+_op_(GPIO_Y_SCR_00_0) \
+_op_(GPIO_Y_VM_01_0) \
+_op_(GPIO_Y_SCR_01_0) \
+_op_(GPIO_Y_VM_02_0) \
+_op_(GPIO_Y_SCR_02_0) \
+_op_(GPIO_Y_VM_03_0) \
+_op_(GPIO_Y_SCR_03_0) \
+_op_(GPIO_Y_VM_04_0) \
+_op_(GPIO_Y_SCR_04_0) \
+_op_(GPIO_Y_VM_05_0) \
+_op_(GPIO_Y_SCR_05_0) \
+_op_(GPIO_Y_VM_06_0) \
+_op_(GPIO_Y_SCR_06_0) \
+_op_(GPIO_Y_VM_07_0) \
+_op_(GPIO_Y_SCR_07_0) \
+_op_(GPIO_Z_VM_00_0) \
+_op_(GPIO_Z_SCR_00_0) \
+_op_(GPIO_Z_VM_01_0) \
+_op_(GPIO_Z_SCR_01_0) \
+_op_(GPIO_Z_VM_02_0) \
+_op_(GPIO_Z_SCR_02_0) \
+_op_(GPIO_Z_VM_03_0) \
+_op_(GPIO_Z_SCR_03_0) \
+_op_(GPIO_Z_VM_04_0) \
+_op_(GPIO_Z_SCR_04_0) \
+_op_(GPIO_Z_VM_05_0) \
+_op_(GPIO_Z_SCR_05_0) \
+_op_(GPIO_Z_VM_06_0) \
+_op_(GPIO_Z_SCR_06_0) \
+_op_(GPIO_Z_VM_07_0) \
+_op_(GPIO_Z_SCR_07_0) \
+_op_(GPIO_CTL1_VM_SCR_0) \
+_op_(GPIO_CTL1_INTERRUPT_STATUS_VM_SCR_0) \
+_op_(GPIO_CTL1_INTERRUPT_STATUS_VM_0) \
+_op_(GPIO_CTL1_SCR_0) \
+_op_(GPIO_CTL1_ICG_EN_OVERRIDE_0) \
+_op_(GPIO_X_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_X_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_X_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_X_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_X_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_X_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_X_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_X_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_Y_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_Y_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_Y_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_Y_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_Y_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_Y_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_Y_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_Y_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_Z_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_Z_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_Z_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_Z_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_Z_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_Z_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_Z_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_Z_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_CTL1_SPARE_0) \
+_op_(GPIO_M_VM_00_0) \
+_op_(GPIO_M_SCR_00_0) \
+_op_(GPIO_M_VM_01_0) \
+_op_(GPIO_M_SCR_01_0) \
+_op_(GPIO_M_VM_02_0) \
+_op_(GPIO_M_SCR_02_0) \
+_op_(GPIO_M_VM_03_0) \
+_op_(GPIO_M_SCR_03_0) \
+_op_(GPIO_M_VM_04_0) \
+_op_(GPIO_M_SCR_04_0) \
+_op_(GPIO_M_VM_05_0) \
+_op_(GPIO_M_SCR_05_0) \
+_op_(GPIO_M_VM_06_0) \
+_op_(GPIO_M_SCR_06_0) \
+_op_(GPIO_M_VM_07_0) \
+_op_(GPIO_M_SCR_07_0) \
+_op_(GPIO_N_VM_00_0) \
+_op_(GPIO_N_SCR_00_0) \
+_op_(GPIO_N_VM_01_0) \
+_op_(GPIO_N_SCR_01_0) \
+_op_(GPIO_N_VM_02_0) \
+_op_(GPIO_N_SCR_02_0) \
+_op_(GPIO_N_VM_03_0) \
+_op_(GPIO_N_SCR_03_0) \
+_op_(GPIO_N_VM_04_0) \
+_op_(GPIO_N_SCR_04_0) \
+_op_(GPIO_N_VM_05_0) \
+_op_(GPIO_N_SCR_05_0) \
+_op_(GPIO_N_VM_06_0) \
+_op_(GPIO_N_SCR_06_0) \
+_op_(GPIO_N_VM_07_0) \
+_op_(GPIO_N_SCR_07_0) \
+_op_(GPIO_P_VM_00_0) \
+_op_(GPIO_P_SCR_00_0) \
+_op_(GPIO_P_VM_01_0) \
+_op_(GPIO_P_SCR_01_0) \
+_op_(GPIO_P_VM_02_0) \
+_op_(GPIO_P_SCR_02_0) \
+_op_(GPIO_P_VM_03_0) \
+_op_(GPIO_P_SCR_03_0) \
+_op_(GPIO_P_VM_04_0) \
+_op_(GPIO_P_SCR_04_0) \
+_op_(GPIO_P_VM_05_0) \
+_op_(GPIO_P_SCR_05_0) \
+_op_(GPIO_P_VM_06_0) \
+_op_(GPIO_P_SCR_06_0) \
+_op_(GPIO_P_VM_07_0) \
+_op_(GPIO_P_SCR_07_0) \
+_op_(GPIO_Q_VM_00_0) \
+_op_(GPIO_Q_SCR_00_0) \
+_op_(GPIO_Q_VM_01_0) \
+_op_(GPIO_Q_SCR_01_0) \
+_op_(GPIO_Q_VM_02_0) \
+_op_(GPIO_Q_SCR_02_0) \
+_op_(GPIO_Q_VM_03_0) \
+_op_(GPIO_Q_SCR_03_0) \
+_op_(GPIO_Q_VM_04_0) \
+_op_(GPIO_Q_SCR_04_0) \
+_op_(GPIO_Q_VM_05_0) \
+_op_(GPIO_Q_SCR_05_0) \
+_op_(GPIO_Q_VM_06_0) \
+_op_(GPIO_Q_SCR_06_0) \
+_op_(GPIO_Q_VM_07_0) \
+_op_(GPIO_Q_SCR_07_0) \
+_op_(GPIO_R_VM_00_0) \
+_op_(GPIO_R_SCR_00_0) \
+_op_(GPIO_R_VM_01_0) \
+_op_(GPIO_R_SCR_01_0) \
+_op_(GPIO_R_VM_02_0) \
+_op_(GPIO_R_SCR_02_0) \
+_op_(GPIO_R_VM_03_0) \
+_op_(GPIO_R_SCR_03_0) \
+_op_(GPIO_R_VM_04_0) \
+_op_(GPIO_R_SCR_04_0) \
+_op_(GPIO_R_VM_05_0) \
+_op_(GPIO_R_SCR_05_0) \
+_op_(GPIO_CTL2_VM_SCR_0) \
+_op_(GPIO_CTL2_INTERRUPT_STATUS_VM_SCR_0) \
+_op_(GPIO_CTL2_INTERRUPT_STATUS_VM_0) \
+_op_(GPIO_CTL2_SCR_0) \
+_op_(GPIO_CTL2_ICG_EN_OVERRIDE_0) \
+_op_(GPIO_M_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_M_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_M_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_M_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_M_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_M_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_M_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_M_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_N_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_N_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_N_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_N_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_N_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_N_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_N_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_N_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_P_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_P_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_P_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_P_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_P_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_P_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_P_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_P_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_Q_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_Q_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_Q_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_Q_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_Q_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_Q_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_Q_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_Q_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_R_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_R_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_R_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_R_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_R_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_R_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_R_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_R_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_CTL2_SPARE_0) \
+_op_(GPIO_K_VM_00_0) \
+_op_(GPIO_K_SCR_00_0) \
+_op_(GPIO_K_VM_01_0) \
+_op_(GPIO_K_SCR_01_0) \
+_op_(GPIO_K_VM_02_0) \
+_op_(GPIO_K_SCR_02_0) \
+_op_(GPIO_K_VM_03_0) \
+_op_(GPIO_K_SCR_03_0) \
+_op_(GPIO_K_VM_04_0) \
+_op_(GPIO_K_SCR_04_0) \
+_op_(GPIO_K_VM_05_0) \
+_op_(GPIO_K_SCR_05_0) \
+_op_(GPIO_K_VM_06_0) \
+_op_(GPIO_K_SCR_06_0) \
+_op_(GPIO_K_VM_07_0) \
+_op_(GPIO_K_SCR_07_0) \
+_op_(GPIO_L_VM_00_0) \
+_op_(GPIO_L_SCR_00_0) \
+_op_(GPIO_L_VM_01_0) \
+_op_(GPIO_L_SCR_01_0) \
+_op_(GPIO_L_VM_02_0) \
+_op_(GPIO_L_SCR_02_0) \
+_op_(GPIO_L_VM_03_0) \
+_op_(GPIO_L_SCR_03_0) \
+_op_(GPIO_AG_VM_00_0) \
+_op_(GPIO_AG_SCR_00_0) \
+_op_(GPIO_AG_VM_01_0) \
+_op_(GPIO_AG_SCR_01_0) \
+_op_(GPIO_AG_VM_02_0) \
+_op_(GPIO_AG_SCR_02_0) \
+_op_(GPIO_AG_VM_03_0) \
+_op_(GPIO_AG_SCR_03_0) \
+_op_(GPIO_AG_VM_04_0) \
+_op_(GPIO_AG_SCR_04_0) \
+_op_(GPIO_AG_VM_05_0) \
+_op_(GPIO_AG_SCR_05_0) \
+_op_(GPIO_AG_VM_06_0) \
+_op_(GPIO_AG_SCR_06_0) \
+_op_(GPIO_AG_VM_07_0) \
+_op_(GPIO_AG_SCR_07_0) \
+_op_(GPIO_AE_VM_00_0) \
+_op_(GPIO_AE_SCR_00_0) \
+_op_(GPIO_AE_VM_01_0) \
+_op_(GPIO_AE_SCR_01_0) \
+_op_(GPIO_AF_VM_00_0) \
+_op_(GPIO_AF_SCR_00_0) \
+_op_(GPIO_AF_VM_01_0) \
+_op_(GPIO_AF_SCR_01_0) \
+_op_(GPIO_AF_VM_02_0) \
+_op_(GPIO_AF_SCR_02_0) \
+_op_(GPIO_AF_VM_03_0) \
+_op_(GPIO_AF_SCR_03_0) \
+_op_(GPIO_CTL3_VM_SCR_0) \
+_op_(GPIO_CTL3_INTERRUPT_STATUS_VM_SCR_0) \
+_op_(GPIO_CTL3_INTERRUPT_STATUS_VM_0) \
+_op_(GPIO_CTL3_SCR_0) \
+_op_(GPIO_CTL3_ICG_EN_OVERRIDE_0) \
+_op_(GPIO_K_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_K_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_K_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_K_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_K_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_K_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_K_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_K_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_L_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_L_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_L_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_L_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_L_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_L_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_L_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_L_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_AG_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_AG_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_AG_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_AG_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_AG_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_AG_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_AG_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_AG_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_AE_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_AE_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_AE_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_AE_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_AE_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_AE_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_AE_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_AE_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_AF_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_AF_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_AF_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_AF_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_AF_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_AF_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_AF_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_AF_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_CTL3_SPARE_0) \
+_op_(GPIO_G_VM_00_0) \
+_op_(GPIO_G_SCR_00_0) \
+_op_(GPIO_G_VM_01_0) \
+_op_(GPIO_G_SCR_01_0) \
+_op_(GPIO_G_VM_02_0) \
+_op_(GPIO_G_SCR_02_0) \
+_op_(GPIO_G_VM_03_0) \
+_op_(GPIO_G_SCR_03_0) \
+_op_(GPIO_G_VM_04_0) \
+_op_(GPIO_G_SCR_04_0) \
+_op_(GPIO_G_VM_05_0) \
+_op_(GPIO_G_SCR_05_0) \
+_op_(GPIO_G_VM_06_0) \
+_op_(GPIO_G_SCR_06_0) \
+_op_(GPIO_G_VM_07_0) \
+_op_(GPIO_G_SCR_07_0) \
+_op_(GPIO_H_VM_00_0) \
+_op_(GPIO_H_SCR_00_0) \
+_op_(GPIO_H_VM_01_0) \
+_op_(GPIO_H_SCR_01_0) \
+_op_(GPIO_H_VM_02_0) \
+_op_(GPIO_H_SCR_02_0) \
+_op_(GPIO_H_VM_03_0) \
+_op_(GPIO_H_SCR_03_0) \
+_op_(GPIO_H_VM_04_0) \
+_op_(GPIO_H_SCR_04_0) \
+_op_(GPIO_H_VM_05_0) \
+_op_(GPIO_H_SCR_05_0) \
+_op_(GPIO_H_VM_06_0) \
+_op_(GPIO_H_SCR_06_0) \
+_op_(GPIO_H_VM_07_0) \
+_op_(GPIO_H_SCR_07_0) \
+_op_(GPIO_I_VM_00_0) \
+_op_(GPIO_I_SCR_00_0) \
+_op_(GPIO_I_VM_01_0) \
+_op_(GPIO_I_SCR_01_0) \
+_op_(GPIO_I_VM_02_0) \
+_op_(GPIO_I_SCR_02_0) \
+_op_(GPIO_I_VM_03_0) \
+_op_(GPIO_I_SCR_03_0) \
+_op_(GPIO_I_VM_04_0) \
+_op_(GPIO_I_SCR_04_0) \
+_op_(GPIO_I_VM_05_0) \
+_op_(GPIO_I_SCR_05_0) \
+_op_(GPIO_I_VM_06_0) \
+_op_(GPIO_I_SCR_06_0) \
+_op_(GPIO_CTL4_VM_SCR_0) \
+_op_(GPIO_CTL4_INTERRUPT_STATUS_VM_SCR_0) \
+_op_(GPIO_CTL4_INTERRUPT_STATUS_VM_0) \
+_op_(GPIO_CTL4_SCR_0) \
+_op_(GPIO_CTL4_ICG_EN_OVERRIDE_0) \
+_op_(GPIO_G_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_G_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_G_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_G_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_G_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_G_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_G_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_G_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_H_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_H_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_H_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_H_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_H_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_H_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_H_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_H_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_I_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_I_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_I_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_I_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_I_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_I_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_I_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_I_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_CTL4_SPARE_0) \
+_op_(GPIO_J_VM_00_0) \
+_op_(GPIO_J_SCR_00_0) \
+_op_(GPIO_J_VM_01_0) \
+_op_(GPIO_J_SCR_01_0) \
+_op_(GPIO_J_VM_02_0) \
+_op_(GPIO_J_SCR_02_0) \
+_op_(GPIO_J_VM_03_0) \
+_op_(GPIO_J_SCR_03_0) \
+_op_(GPIO_J_VM_04_0) \
+_op_(GPIO_J_SCR_04_0) \
+_op_(GPIO_J_VM_05_0) \
+_op_(GPIO_J_SCR_05_0) \
+_op_(GPIO_C_VM_00_0) \
+_op_(GPIO_C_SCR_00_0) \
+_op_(GPIO_C_VM_01_0) \
+_op_(GPIO_C_SCR_01_0) \
+_op_(GPIO_C_VM_02_0) \
+_op_(GPIO_C_SCR_02_0) \
+_op_(GPIO_C_VM_03_0) \
+_op_(GPIO_C_SCR_03_0) \
+_op_(GPIO_C_VM_04_0) \
+_op_(GPIO_C_SCR_04_0) \
+_op_(GPIO_C_VM_05_0) \
+_op_(GPIO_C_SCR_05_0) \
+_op_(GPIO_C_VM_06_0) \
+_op_(GPIO_C_SCR_06_0) \
+_op_(GPIO_C_VM_07_0) \
+_op_(GPIO_C_SCR_07_0) \
+_op_(GPIO_D_VM_00_0) \
+_op_(GPIO_D_SCR_00_0) \
+_op_(GPIO_D_VM_01_0) \
+_op_(GPIO_D_SCR_01_0) \
+_op_(GPIO_D_VM_02_0) \
+_op_(GPIO_D_SCR_02_0) \
+_op_(GPIO_D_VM_03_0) \
+_op_(GPIO_D_SCR_03_0) \
+_op_(GPIO_E_VM_00_0) \
+_op_(GPIO_E_SCR_00_0) \
+_op_(GPIO_E_VM_01_0) \
+_op_(GPIO_E_SCR_01_0) \
+_op_(GPIO_E_VM_02_0) \
+_op_(GPIO_E_SCR_02_0) \
+_op_(GPIO_E_VM_03_0) \
+_op_(GPIO_E_SCR_03_0) \
+_op_(GPIO_E_VM_04_0) \
+_op_(GPIO_E_SCR_04_0) \
+_op_(GPIO_E_VM_05_0) \
+_op_(GPIO_E_SCR_05_0) \
+_op_(GPIO_E_VM_06_0) \
+_op_(GPIO_E_SCR_06_0) \
+_op_(GPIO_E_VM_07_0) \
+_op_(GPIO_E_SCR_07_0) \
+_op_(GPIO_F_VM_00_0) \
+_op_(GPIO_F_SCR_00_0) \
+_op_(GPIO_F_VM_01_0) \
+_op_(GPIO_F_SCR_01_0) \
+_op_(GPIO_F_VM_02_0) \
+_op_(GPIO_F_SCR_02_0) \
+_op_(GPIO_F_VM_03_0) \
+_op_(GPIO_F_SCR_03_0) \
+_op_(GPIO_F_VM_04_0) \
+_op_(GPIO_F_SCR_04_0) \
+_op_(GPIO_F_VM_05_0) \
+_op_(GPIO_F_SCR_05_0) \
+_op_(GPIO_CTL5_VM_SCR_0) \
+_op_(GPIO_CTL5_INTERRUPT_STATUS_VM_SCR_0) \
+_op_(GPIO_CTL5_INTERRUPT_STATUS_VM_0) \
+_op_(GPIO_CTL5_SCR_0) \
+_op_(GPIO_CTL5_ICG_EN_OVERRIDE_0) \
+_op_(GPIO_J_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_J_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_J_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_J_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_J_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_J_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_J_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_J_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_C_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_C_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_C_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_C_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_C_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_C_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_C_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_C_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_D_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_D_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_D_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_D_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_D_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_D_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_D_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_D_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_E_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_E_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_E_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_E_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_E_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_E_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_E_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_E_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_F_INT0_ROUTE_MAPPING_0) \
+_op_(GPIO_F_INT1_ROUTE_MAPPING_0) \
+_op_(GPIO_F_INT2_ROUTE_MAPPING_0) \
+_op_(GPIO_F_INT3_ROUTE_MAPPING_0) \
+_op_(GPIO_F_INT4_ROUTE_MAPPING_0) \
+_op_(GPIO_F_INT5_ROUTE_MAPPING_0) \
+_op_(GPIO_F_INT6_ROUTE_MAPPING_0) \
+_op_(GPIO_F_INT7_ROUTE_MAPPING_0) \
+_op_(GPIO_CTL5_SPARE_0) \
+_op_(GPIO_A_ENABLE_CONFIG_00_0) \
+_op_(GPIO_A_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_A_INPUT_00_0) \
+_op_(GPIO_A_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_A_OUTPUT_VALUE_00_0) \
+_op_(GPIO_A_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_A_ENABLE_CONFIG_01_0) \
+_op_(GPIO_A_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_A_INPUT_01_0) \
+_op_(GPIO_A_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_A_OUTPUT_VALUE_01_0) \
+_op_(GPIO_A_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_A_ENABLE_CONFIG_02_0) \
+_op_(GPIO_A_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_A_INPUT_02_0) \
+_op_(GPIO_A_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_A_OUTPUT_VALUE_02_0) \
+_op_(GPIO_A_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_A_ENABLE_CONFIG_03_0) \
+_op_(GPIO_A_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_A_INPUT_03_0) \
+_op_(GPIO_A_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_A_OUTPUT_VALUE_03_0) \
+_op_(GPIO_A_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_A_ENABLE_CONFIG_04_0) \
+_op_(GPIO_A_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_A_INPUT_04_0) \
+_op_(GPIO_A_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_A_OUTPUT_VALUE_04_0) \
+_op_(GPIO_A_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_A_ENABLE_CONFIG_05_0) \
+_op_(GPIO_A_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_A_INPUT_05_0) \
+_op_(GPIO_A_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_A_OUTPUT_VALUE_05_0) \
+_op_(GPIO_A_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_A_ENABLE_CONFIG_06_0) \
+_op_(GPIO_A_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_A_INPUT_06_0) \
+_op_(GPIO_A_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_A_OUTPUT_VALUE_06_0) \
+_op_(GPIO_A_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_A_ENABLE_CONFIG_07_0) \
+_op_(GPIO_A_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_A_INPUT_07_0) \
+_op_(GPIO_A_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_A_OUTPUT_VALUE_07_0) \
+_op_(GPIO_A_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_A_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_A_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_A_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_A_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_A_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_A_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_A_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_A_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_AC_ENABLE_CONFIG_00_0) \
+_op_(GPIO_AC_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_AC_INPUT_00_0) \
+_op_(GPIO_AC_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_AC_OUTPUT_VALUE_00_0) \
+_op_(GPIO_AC_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_AC_ENABLE_CONFIG_01_0) \
+_op_(GPIO_AC_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_AC_INPUT_01_0) \
+_op_(GPIO_AC_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_AC_OUTPUT_VALUE_01_0) \
+_op_(GPIO_AC_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_AC_ENABLE_CONFIG_02_0) \
+_op_(GPIO_AC_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_AC_INPUT_02_0) \
+_op_(GPIO_AC_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_AC_OUTPUT_VALUE_02_0) \
+_op_(GPIO_AC_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_AC_ENABLE_CONFIG_03_0) \
+_op_(GPIO_AC_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_AC_INPUT_03_0) \
+_op_(GPIO_AC_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_AC_OUTPUT_VALUE_03_0) \
+_op_(GPIO_AC_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_AC_ENABLE_CONFIG_04_0) \
+_op_(GPIO_AC_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_AC_INPUT_04_0) \
+_op_(GPIO_AC_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_AC_OUTPUT_VALUE_04_0) \
+_op_(GPIO_AC_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_AC_ENABLE_CONFIG_05_0) \
+_op_(GPIO_AC_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_AC_INPUT_05_0) \
+_op_(GPIO_AC_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_AC_OUTPUT_VALUE_05_0) \
+_op_(GPIO_AC_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_AC_ENABLE_CONFIG_06_0) \
+_op_(GPIO_AC_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_AC_INPUT_06_0) \
+_op_(GPIO_AC_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_AC_OUTPUT_VALUE_06_0) \
+_op_(GPIO_AC_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_AC_ENABLE_CONFIG_07_0) \
+_op_(GPIO_AC_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_AC_INPUT_07_0) \
+_op_(GPIO_AC_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_AC_OUTPUT_VALUE_07_0) \
+_op_(GPIO_AC_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_AC_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_AC_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_AC_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_AC_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_AC_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_AC_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_AC_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_AC_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_AD_ENABLE_CONFIG_00_0) \
+_op_(GPIO_AD_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_AD_INPUT_00_0) \
+_op_(GPIO_AD_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_AD_OUTPUT_VALUE_00_0) \
+_op_(GPIO_AD_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_AD_ENABLE_CONFIG_01_0) \
+_op_(GPIO_AD_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_AD_INPUT_01_0) \
+_op_(GPIO_AD_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_AD_OUTPUT_VALUE_01_0) \
+_op_(GPIO_AD_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_AD_ENABLE_CONFIG_02_0) \
+_op_(GPIO_AD_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_AD_INPUT_02_0) \
+_op_(GPIO_AD_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_AD_OUTPUT_VALUE_02_0) \
+_op_(GPIO_AD_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_AD_ENABLE_CONFIG_03_0) \
+_op_(GPIO_AD_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_AD_INPUT_03_0) \
+_op_(GPIO_AD_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_AD_OUTPUT_VALUE_03_0) \
+_op_(GPIO_AD_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_AD_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_AD_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_AD_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_AD_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_AD_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_AD_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_AD_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_AD_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_B_ENABLE_CONFIG_00_0) \
+_op_(GPIO_B_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_B_INPUT_00_0) \
+_op_(GPIO_B_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_B_OUTPUT_VALUE_00_0) \
+_op_(GPIO_B_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_B_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_B_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_B_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_B_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_B_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_B_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_B_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_B_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_X_ENABLE_CONFIG_00_0) \
+_op_(GPIO_X_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_X_INPUT_00_0) \
+_op_(GPIO_X_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_X_OUTPUT_VALUE_00_0) \
+_op_(GPIO_X_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_X_ENABLE_CONFIG_01_0) \
+_op_(GPIO_X_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_X_INPUT_01_0) \
+_op_(GPIO_X_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_X_OUTPUT_VALUE_01_0) \
+_op_(GPIO_X_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_X_ENABLE_CONFIG_02_0) \
+_op_(GPIO_X_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_X_INPUT_02_0) \
+_op_(GPIO_X_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_X_OUTPUT_VALUE_02_0) \
+_op_(GPIO_X_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_X_ENABLE_CONFIG_03_0) \
+_op_(GPIO_X_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_X_INPUT_03_0) \
+_op_(GPIO_X_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_X_OUTPUT_VALUE_03_0) \
+_op_(GPIO_X_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_X_ENABLE_CONFIG_04_0) \
+_op_(GPIO_X_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_X_INPUT_04_0) \
+_op_(GPIO_X_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_X_OUTPUT_VALUE_04_0) \
+_op_(GPIO_X_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_X_ENABLE_CONFIG_05_0) \
+_op_(GPIO_X_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_X_INPUT_05_0) \
+_op_(GPIO_X_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_X_OUTPUT_VALUE_05_0) \
+_op_(GPIO_X_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_X_ENABLE_CONFIG_06_0) \
+_op_(GPIO_X_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_X_INPUT_06_0) \
+_op_(GPIO_X_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_X_OUTPUT_VALUE_06_0) \
+_op_(GPIO_X_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_X_ENABLE_CONFIG_07_0) \
+_op_(GPIO_X_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_X_INPUT_07_0) \
+_op_(GPIO_X_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_X_OUTPUT_VALUE_07_0) \
+_op_(GPIO_X_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_X_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_X_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_X_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_X_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_X_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_X_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_X_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_X_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_Y_ENABLE_CONFIG_00_0) \
+_op_(GPIO_Y_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_Y_INPUT_00_0) \
+_op_(GPIO_Y_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_Y_OUTPUT_VALUE_00_0) \
+_op_(GPIO_Y_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_Y_ENABLE_CONFIG_01_0) \
+_op_(GPIO_Y_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_Y_INPUT_01_0) \
+_op_(GPIO_Y_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_Y_OUTPUT_VALUE_01_0) \
+_op_(GPIO_Y_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_Y_ENABLE_CONFIG_02_0) \
+_op_(GPIO_Y_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_Y_INPUT_02_0) \
+_op_(GPIO_Y_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_Y_OUTPUT_VALUE_02_0) \
+_op_(GPIO_Y_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_Y_ENABLE_CONFIG_03_0) \
+_op_(GPIO_Y_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_Y_INPUT_03_0) \
+_op_(GPIO_Y_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_Y_OUTPUT_VALUE_03_0) \
+_op_(GPIO_Y_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_Y_ENABLE_CONFIG_04_0) \
+_op_(GPIO_Y_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_Y_INPUT_04_0) \
+_op_(GPIO_Y_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_Y_OUTPUT_VALUE_04_0) \
+_op_(GPIO_Y_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_Y_ENABLE_CONFIG_05_0) \
+_op_(GPIO_Y_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_Y_INPUT_05_0) \
+_op_(GPIO_Y_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_Y_OUTPUT_VALUE_05_0) \
+_op_(GPIO_Y_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_Y_ENABLE_CONFIG_06_0) \
+_op_(GPIO_Y_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_Y_INPUT_06_0) \
+_op_(GPIO_Y_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_Y_OUTPUT_VALUE_06_0) \
+_op_(GPIO_Y_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_Y_ENABLE_CONFIG_07_0) \
+_op_(GPIO_Y_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_Y_INPUT_07_0) \
+_op_(GPIO_Y_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_Y_OUTPUT_VALUE_07_0) \
+_op_(GPIO_Y_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_Y_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_Y_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_Y_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_Y_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_Y_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_Y_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_Y_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_Y_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_Z_ENABLE_CONFIG_00_0) \
+_op_(GPIO_Z_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_Z_INPUT_00_0) \
+_op_(GPIO_Z_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_Z_OUTPUT_VALUE_00_0) \
+_op_(GPIO_Z_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_Z_ENABLE_CONFIG_01_0) \
+_op_(GPIO_Z_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_Z_INPUT_01_0) \
+_op_(GPIO_Z_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_Z_OUTPUT_VALUE_01_0) \
+_op_(GPIO_Z_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_Z_ENABLE_CONFIG_02_0) \
+_op_(GPIO_Z_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_Z_INPUT_02_0) \
+_op_(GPIO_Z_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_Z_OUTPUT_VALUE_02_0) \
+_op_(GPIO_Z_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_Z_ENABLE_CONFIG_03_0) \
+_op_(GPIO_Z_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_Z_INPUT_03_0) \
+_op_(GPIO_Z_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_Z_OUTPUT_VALUE_03_0) \
+_op_(GPIO_Z_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_Z_ENABLE_CONFIG_04_0) \
+_op_(GPIO_Z_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_Z_INPUT_04_0) \
+_op_(GPIO_Z_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_Z_OUTPUT_VALUE_04_0) \
+_op_(GPIO_Z_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_Z_ENABLE_CONFIG_05_0) \
+_op_(GPIO_Z_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_Z_INPUT_05_0) \
+_op_(GPIO_Z_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_Z_OUTPUT_VALUE_05_0) \
+_op_(GPIO_Z_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_Z_ENABLE_CONFIG_06_0) \
+_op_(GPIO_Z_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_Z_INPUT_06_0) \
+_op_(GPIO_Z_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_Z_OUTPUT_VALUE_06_0) \
+_op_(GPIO_Z_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_Z_ENABLE_CONFIG_07_0) \
+_op_(GPIO_Z_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_Z_INPUT_07_0) \
+_op_(GPIO_Z_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_Z_OUTPUT_VALUE_07_0) \
+_op_(GPIO_Z_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_Z_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_Z_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_Z_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_Z_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_Z_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_Z_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_Z_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_Z_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_M_ENABLE_CONFIG_00_0) \
+_op_(GPIO_M_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_M_INPUT_00_0) \
+_op_(GPIO_M_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_M_OUTPUT_VALUE_00_0) \
+_op_(GPIO_M_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_M_ENABLE_CONFIG_01_0) \
+_op_(GPIO_M_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_M_INPUT_01_0) \
+_op_(GPIO_M_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_M_OUTPUT_VALUE_01_0) \
+_op_(GPIO_M_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_M_ENABLE_CONFIG_02_0) \
+_op_(GPIO_M_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_M_INPUT_02_0) \
+_op_(GPIO_M_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_M_OUTPUT_VALUE_02_0) \
+_op_(GPIO_M_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_M_ENABLE_CONFIG_03_0) \
+_op_(GPIO_M_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_M_INPUT_03_0) \
+_op_(GPIO_M_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_M_OUTPUT_VALUE_03_0) \
+_op_(GPIO_M_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_M_ENABLE_CONFIG_04_0) \
+_op_(GPIO_M_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_M_INPUT_04_0) \
+_op_(GPIO_M_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_M_OUTPUT_VALUE_04_0) \
+_op_(GPIO_M_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_M_ENABLE_CONFIG_05_0) \
+_op_(GPIO_M_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_M_INPUT_05_0) \
+_op_(GPIO_M_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_M_OUTPUT_VALUE_05_0) \
+_op_(GPIO_M_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_M_ENABLE_CONFIG_06_0) \
+_op_(GPIO_M_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_M_INPUT_06_0) \
+_op_(GPIO_M_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_M_OUTPUT_VALUE_06_0) \
+_op_(GPIO_M_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_M_ENABLE_CONFIG_07_0) \
+_op_(GPIO_M_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_M_INPUT_07_0) \
+_op_(GPIO_M_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_M_OUTPUT_VALUE_07_0) \
+_op_(GPIO_M_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_M_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_M_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_M_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_M_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_M_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_M_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_M_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_M_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_N_ENABLE_CONFIG_00_0) \
+_op_(GPIO_N_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_N_INPUT_00_0) \
+_op_(GPIO_N_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_N_OUTPUT_VALUE_00_0) \
+_op_(GPIO_N_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_N_ENABLE_CONFIG_01_0) \
+_op_(GPIO_N_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_N_INPUT_01_0) \
+_op_(GPIO_N_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_N_OUTPUT_VALUE_01_0) \
+_op_(GPIO_N_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_N_ENABLE_CONFIG_02_0) \
+_op_(GPIO_N_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_N_INPUT_02_0) \
+_op_(GPIO_N_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_N_OUTPUT_VALUE_02_0) \
+_op_(GPIO_N_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_N_ENABLE_CONFIG_03_0) \
+_op_(GPIO_N_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_N_INPUT_03_0) \
+_op_(GPIO_N_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_N_OUTPUT_VALUE_03_0) \
+_op_(GPIO_N_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_N_ENABLE_CONFIG_04_0) \
+_op_(GPIO_N_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_N_INPUT_04_0) \
+_op_(GPIO_N_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_N_OUTPUT_VALUE_04_0) \
+_op_(GPIO_N_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_N_ENABLE_CONFIG_05_0) \
+_op_(GPIO_N_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_N_INPUT_05_0) \
+_op_(GPIO_N_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_N_OUTPUT_VALUE_05_0) \
+_op_(GPIO_N_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_N_ENABLE_CONFIG_06_0) \
+_op_(GPIO_N_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_N_INPUT_06_0) \
+_op_(GPIO_N_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_N_OUTPUT_VALUE_06_0) \
+_op_(GPIO_N_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_N_ENABLE_CONFIG_07_0) \
+_op_(GPIO_N_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_N_INPUT_07_0) \
+_op_(GPIO_N_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_N_OUTPUT_VALUE_07_0) \
+_op_(GPIO_N_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_N_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_N_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_N_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_N_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_N_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_N_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_N_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_N_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_P_ENABLE_CONFIG_00_0) \
+_op_(GPIO_P_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_P_INPUT_00_0) \
+_op_(GPIO_P_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_P_OUTPUT_VALUE_00_0) \
+_op_(GPIO_P_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_P_ENABLE_CONFIG_01_0) \
+_op_(GPIO_P_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_P_INPUT_01_0) \
+_op_(GPIO_P_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_P_OUTPUT_VALUE_01_0) \
+_op_(GPIO_P_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_P_ENABLE_CONFIG_02_0) \
+_op_(GPIO_P_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_P_INPUT_02_0) \
+_op_(GPIO_P_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_P_OUTPUT_VALUE_02_0) \
+_op_(GPIO_P_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_P_ENABLE_CONFIG_03_0) \
+_op_(GPIO_P_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_P_INPUT_03_0) \
+_op_(GPIO_P_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_P_OUTPUT_VALUE_03_0) \
+_op_(GPIO_P_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_P_ENABLE_CONFIG_04_0) \
+_op_(GPIO_P_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_P_INPUT_04_0) \
+_op_(GPIO_P_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_P_OUTPUT_VALUE_04_0) \
+_op_(GPIO_P_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_P_ENABLE_CONFIG_05_0) \
+_op_(GPIO_P_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_P_INPUT_05_0) \
+_op_(GPIO_P_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_P_OUTPUT_VALUE_05_0) \
+_op_(GPIO_P_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_P_ENABLE_CONFIG_06_0) \
+_op_(GPIO_P_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_P_INPUT_06_0) \
+_op_(GPIO_P_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_P_OUTPUT_VALUE_06_0) \
+_op_(GPIO_P_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_P_ENABLE_CONFIG_07_0) \
+_op_(GPIO_P_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_P_INPUT_07_0) \
+_op_(GPIO_P_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_P_OUTPUT_VALUE_07_0) \
+_op_(GPIO_P_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_P_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_P_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_P_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_P_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_P_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_P_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_P_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_P_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_Q_ENABLE_CONFIG_00_0) \
+_op_(GPIO_Q_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_Q_INPUT_00_0) \
+_op_(GPIO_Q_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_Q_OUTPUT_VALUE_00_0) \
+_op_(GPIO_Q_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_Q_ENABLE_CONFIG_01_0) \
+_op_(GPIO_Q_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_Q_INPUT_01_0) \
+_op_(GPIO_Q_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_Q_OUTPUT_VALUE_01_0) \
+_op_(GPIO_Q_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_Q_ENABLE_CONFIG_02_0) \
+_op_(GPIO_Q_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_Q_INPUT_02_0) \
+_op_(GPIO_Q_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_Q_OUTPUT_VALUE_02_0) \
+_op_(GPIO_Q_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_Q_ENABLE_CONFIG_03_0) \
+_op_(GPIO_Q_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_Q_INPUT_03_0) \
+_op_(GPIO_Q_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_Q_OUTPUT_VALUE_03_0) \
+_op_(GPIO_Q_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_Q_ENABLE_CONFIG_04_0) \
+_op_(GPIO_Q_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_Q_INPUT_04_0) \
+_op_(GPIO_Q_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_Q_OUTPUT_VALUE_04_0) \
+_op_(GPIO_Q_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_Q_ENABLE_CONFIG_05_0) \
+_op_(GPIO_Q_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_Q_INPUT_05_0) \
+_op_(GPIO_Q_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_Q_OUTPUT_VALUE_05_0) \
+_op_(GPIO_Q_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_Q_ENABLE_CONFIG_06_0) \
+_op_(GPIO_Q_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_Q_INPUT_06_0) \
+_op_(GPIO_Q_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_Q_OUTPUT_VALUE_06_0) \
+_op_(GPIO_Q_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_Q_ENABLE_CONFIG_07_0) \
+_op_(GPIO_Q_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_Q_INPUT_07_0) \
+_op_(GPIO_Q_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_Q_OUTPUT_VALUE_07_0) \
+_op_(GPIO_Q_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_Q_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_Q_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_Q_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_Q_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_Q_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_Q_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_Q_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_Q_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_R_ENABLE_CONFIG_00_0) \
+_op_(GPIO_R_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_R_INPUT_00_0) \
+_op_(GPIO_R_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_R_OUTPUT_VALUE_00_0) \
+_op_(GPIO_R_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_R_ENABLE_CONFIG_01_0) \
+_op_(GPIO_R_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_R_INPUT_01_0) \
+_op_(GPIO_R_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_R_OUTPUT_VALUE_01_0) \
+_op_(GPIO_R_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_R_ENABLE_CONFIG_02_0) \
+_op_(GPIO_R_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_R_INPUT_02_0) \
+_op_(GPIO_R_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_R_OUTPUT_VALUE_02_0) \
+_op_(GPIO_R_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_R_ENABLE_CONFIG_03_0) \
+_op_(GPIO_R_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_R_INPUT_03_0) \
+_op_(GPIO_R_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_R_OUTPUT_VALUE_03_0) \
+_op_(GPIO_R_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_R_ENABLE_CONFIG_04_0) \
+_op_(GPIO_R_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_R_INPUT_04_0) \
+_op_(GPIO_R_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_R_OUTPUT_VALUE_04_0) \
+_op_(GPIO_R_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_R_ENABLE_CONFIG_05_0) \
+_op_(GPIO_R_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_R_INPUT_05_0) \
+_op_(GPIO_R_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_R_OUTPUT_VALUE_05_0) \
+_op_(GPIO_R_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_R_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_R_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_R_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_R_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_R_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_R_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_R_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_R_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_K_ENABLE_CONFIG_00_0) \
+_op_(GPIO_K_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_K_INPUT_00_0) \
+_op_(GPIO_K_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_K_OUTPUT_VALUE_00_0) \
+_op_(GPIO_K_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_K_ENABLE_CONFIG_01_0) \
+_op_(GPIO_K_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_K_INPUT_01_0) \
+_op_(GPIO_K_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_K_OUTPUT_VALUE_01_0) \
+_op_(GPIO_K_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_K_ENABLE_CONFIG_02_0) \
+_op_(GPIO_K_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_K_INPUT_02_0) \
+_op_(GPIO_K_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_K_OUTPUT_VALUE_02_0) \
+_op_(GPIO_K_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_K_ENABLE_CONFIG_03_0) \
+_op_(GPIO_K_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_K_INPUT_03_0) \
+_op_(GPIO_K_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_K_OUTPUT_VALUE_03_0) \
+_op_(GPIO_K_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_K_ENABLE_CONFIG_04_0) \
+_op_(GPIO_K_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_K_INPUT_04_0) \
+_op_(GPIO_K_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_K_OUTPUT_VALUE_04_0) \
+_op_(GPIO_K_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_K_ENABLE_CONFIG_05_0) \
+_op_(GPIO_K_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_K_INPUT_05_0) \
+_op_(GPIO_K_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_K_OUTPUT_VALUE_05_0) \
+_op_(GPIO_K_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_K_ENABLE_CONFIG_06_0) \
+_op_(GPIO_K_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_K_INPUT_06_0) \
+_op_(GPIO_K_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_K_OUTPUT_VALUE_06_0) \
+_op_(GPIO_K_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_K_ENABLE_CONFIG_07_0) \
+_op_(GPIO_K_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_K_INPUT_07_0) \
+_op_(GPIO_K_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_K_OUTPUT_VALUE_07_0) \
+_op_(GPIO_K_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_K_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_K_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_K_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_K_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_K_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_K_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_K_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_K_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_L_ENABLE_CONFIG_00_0) \
+_op_(GPIO_L_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_L_INPUT_00_0) \
+_op_(GPIO_L_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_L_OUTPUT_VALUE_00_0) \
+_op_(GPIO_L_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_L_ENABLE_CONFIG_01_0) \
+_op_(GPIO_L_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_L_INPUT_01_0) \
+_op_(GPIO_L_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_L_OUTPUT_VALUE_01_0) \
+_op_(GPIO_L_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_L_ENABLE_CONFIG_02_0) \
+_op_(GPIO_L_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_L_INPUT_02_0) \
+_op_(GPIO_L_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_L_OUTPUT_VALUE_02_0) \
+_op_(GPIO_L_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_L_ENABLE_CONFIG_03_0) \
+_op_(GPIO_L_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_L_INPUT_03_0) \
+_op_(GPIO_L_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_L_OUTPUT_VALUE_03_0) \
+_op_(GPIO_L_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_L_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_L_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_L_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_L_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_L_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_L_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_L_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_L_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_AG_ENABLE_CONFIG_00_0) \
+_op_(GPIO_AG_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_AG_INPUT_00_0) \
+_op_(GPIO_AG_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_AG_OUTPUT_VALUE_00_0) \
+_op_(GPIO_AG_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_AG_ENABLE_CONFIG_01_0) \
+_op_(GPIO_AG_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_AG_INPUT_01_0) \
+_op_(GPIO_AG_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_AG_OUTPUT_VALUE_01_0) \
+_op_(GPIO_AG_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_AG_ENABLE_CONFIG_02_0) \
+_op_(GPIO_AG_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_AG_INPUT_02_0) \
+_op_(GPIO_AG_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_AG_OUTPUT_VALUE_02_0) \
+_op_(GPIO_AG_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_AG_ENABLE_CONFIG_03_0) \
+_op_(GPIO_AG_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_AG_INPUT_03_0) \
+_op_(GPIO_AG_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_AG_OUTPUT_VALUE_03_0) \
+_op_(GPIO_AG_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_AG_ENABLE_CONFIG_04_0) \
+_op_(GPIO_AG_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_AG_INPUT_04_0) \
+_op_(GPIO_AG_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_AG_OUTPUT_VALUE_04_0) \
+_op_(GPIO_AG_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_AG_ENABLE_CONFIG_05_0) \
+_op_(GPIO_AG_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_AG_INPUT_05_0) \
+_op_(GPIO_AG_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_AG_OUTPUT_VALUE_05_0) \
+_op_(GPIO_AG_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_AG_ENABLE_CONFIG_06_0) \
+_op_(GPIO_AG_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_AG_INPUT_06_0) \
+_op_(GPIO_AG_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_AG_OUTPUT_VALUE_06_0) \
+_op_(GPIO_AG_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_AG_ENABLE_CONFIG_07_0) \
+_op_(GPIO_AG_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_AG_INPUT_07_0) \
+_op_(GPIO_AG_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_AG_OUTPUT_VALUE_07_0) \
+_op_(GPIO_AG_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_AG_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_AG_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_AG_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_AG_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_AG_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_AG_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_AG_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_AG_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_AE_ENABLE_CONFIG_00_0) \
+_op_(GPIO_AE_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_AE_INPUT_00_0) \
+_op_(GPIO_AE_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_AE_OUTPUT_VALUE_00_0) \
+_op_(GPIO_AE_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_AE_ENABLE_CONFIG_01_0) \
+_op_(GPIO_AE_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_AE_INPUT_01_0) \
+_op_(GPIO_AE_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_AE_OUTPUT_VALUE_01_0) \
+_op_(GPIO_AE_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_AE_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_AE_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_AE_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_AE_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_AE_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_AE_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_AE_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_AE_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_AF_ENABLE_CONFIG_00_0) \
+_op_(GPIO_AF_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_AF_INPUT_00_0) \
+_op_(GPIO_AF_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_AF_OUTPUT_VALUE_00_0) \
+_op_(GPIO_AF_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_AF_ENABLE_CONFIG_01_0) \
+_op_(GPIO_AF_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_AF_INPUT_01_0) \
+_op_(GPIO_AF_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_AF_OUTPUT_VALUE_01_0) \
+_op_(GPIO_AF_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_AF_ENABLE_CONFIG_02_0) \
+_op_(GPIO_AF_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_AF_INPUT_02_0) \
+_op_(GPIO_AF_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_AF_OUTPUT_VALUE_02_0) \
+_op_(GPIO_AF_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_AF_ENABLE_CONFIG_03_0) \
+_op_(GPIO_AF_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_AF_INPUT_03_0) \
+_op_(GPIO_AF_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_AF_OUTPUT_VALUE_03_0) \
+_op_(GPIO_AF_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_AF_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_AF_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_AF_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_AF_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_AF_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_AF_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_AF_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_AF_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_G_ENABLE_CONFIG_00_0) \
+_op_(GPIO_G_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_G_INPUT_00_0) \
+_op_(GPIO_G_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_G_OUTPUT_VALUE_00_0) \
+_op_(GPIO_G_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_G_ENABLE_CONFIG_01_0) \
+_op_(GPIO_G_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_G_INPUT_01_0) \
+_op_(GPIO_G_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_G_OUTPUT_VALUE_01_0) \
+_op_(GPIO_G_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_G_ENABLE_CONFIG_02_0) \
+_op_(GPIO_G_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_G_INPUT_02_0) \
+_op_(GPIO_G_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_G_OUTPUT_VALUE_02_0) \
+_op_(GPIO_G_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_G_ENABLE_CONFIG_03_0) \
+_op_(GPIO_G_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_G_INPUT_03_0) \
+_op_(GPIO_G_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_G_OUTPUT_VALUE_03_0) \
+_op_(GPIO_G_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_G_ENABLE_CONFIG_04_0) \
+_op_(GPIO_G_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_G_INPUT_04_0) \
+_op_(GPIO_G_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_G_OUTPUT_VALUE_04_0) \
+_op_(GPIO_G_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_G_ENABLE_CONFIG_05_0) \
+_op_(GPIO_G_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_G_INPUT_05_0) \
+_op_(GPIO_G_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_G_OUTPUT_VALUE_05_0) \
+_op_(GPIO_G_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_G_ENABLE_CONFIG_06_0) \
+_op_(GPIO_G_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_G_INPUT_06_0) \
+_op_(GPIO_G_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_G_OUTPUT_VALUE_06_0) \
+_op_(GPIO_G_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_G_ENABLE_CONFIG_07_0) \
+_op_(GPIO_G_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_G_INPUT_07_0) \
+_op_(GPIO_G_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_G_OUTPUT_VALUE_07_0) \
+_op_(GPIO_G_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_G_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_G_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_G_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_G_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_G_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_G_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_G_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_G_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_H_ENABLE_CONFIG_00_0) \
+_op_(GPIO_H_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_H_INPUT_00_0) \
+_op_(GPIO_H_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_H_OUTPUT_VALUE_00_0) \
+_op_(GPIO_H_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_H_ENABLE_CONFIG_01_0) \
+_op_(GPIO_H_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_H_INPUT_01_0) \
+_op_(GPIO_H_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_H_OUTPUT_VALUE_01_0) \
+_op_(GPIO_H_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_H_ENABLE_CONFIG_02_0) \
+_op_(GPIO_H_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_H_INPUT_02_0) \
+_op_(GPIO_H_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_H_OUTPUT_VALUE_02_0) \
+_op_(GPIO_H_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_H_ENABLE_CONFIG_03_0) \
+_op_(GPIO_H_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_H_INPUT_03_0) \
+_op_(GPIO_H_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_H_OUTPUT_VALUE_03_0) \
+_op_(GPIO_H_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_H_ENABLE_CONFIG_04_0) \
+_op_(GPIO_H_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_H_INPUT_04_0) \
+_op_(GPIO_H_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_H_OUTPUT_VALUE_04_0) \
+_op_(GPIO_H_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_H_ENABLE_CONFIG_05_0) \
+_op_(GPIO_H_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_H_INPUT_05_0) \
+_op_(GPIO_H_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_H_OUTPUT_VALUE_05_0) \
+_op_(GPIO_H_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_H_ENABLE_CONFIG_06_0) \
+_op_(GPIO_H_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_H_INPUT_06_0) \
+_op_(GPIO_H_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_H_OUTPUT_VALUE_06_0) \
+_op_(GPIO_H_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_H_ENABLE_CONFIG_07_0) \
+_op_(GPIO_H_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_H_INPUT_07_0) \
+_op_(GPIO_H_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_H_OUTPUT_VALUE_07_0) \
+_op_(GPIO_H_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_H_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_H_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_H_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_H_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_H_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_H_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_H_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_H_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_I_ENABLE_CONFIG_00_0) \
+_op_(GPIO_I_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_I_INPUT_00_0) \
+_op_(GPIO_I_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_I_OUTPUT_VALUE_00_0) \
+_op_(GPIO_I_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_I_ENABLE_CONFIG_01_0) \
+_op_(GPIO_I_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_I_INPUT_01_0) \
+_op_(GPIO_I_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_I_OUTPUT_VALUE_01_0) \
+_op_(GPIO_I_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_I_ENABLE_CONFIG_02_0) \
+_op_(GPIO_I_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_I_INPUT_02_0) \
+_op_(GPIO_I_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_I_OUTPUT_VALUE_02_0) \
+_op_(GPIO_I_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_I_ENABLE_CONFIG_03_0) \
+_op_(GPIO_I_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_I_INPUT_03_0) \
+_op_(GPIO_I_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_I_OUTPUT_VALUE_03_0) \
+_op_(GPIO_I_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_I_ENABLE_CONFIG_04_0) \
+_op_(GPIO_I_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_I_INPUT_04_0) \
+_op_(GPIO_I_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_I_OUTPUT_VALUE_04_0) \
+_op_(GPIO_I_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_I_ENABLE_CONFIG_05_0) \
+_op_(GPIO_I_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_I_INPUT_05_0) \
+_op_(GPIO_I_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_I_OUTPUT_VALUE_05_0) \
+_op_(GPIO_I_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_I_ENABLE_CONFIG_06_0) \
+_op_(GPIO_I_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_I_INPUT_06_0) \
+_op_(GPIO_I_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_I_OUTPUT_VALUE_06_0) \
+_op_(GPIO_I_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_I_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_I_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_I_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_I_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_I_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_I_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_I_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_I_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_J_ENABLE_CONFIG_00_0) \
+_op_(GPIO_J_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_J_INPUT_00_0) \
+_op_(GPIO_J_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_J_OUTPUT_VALUE_00_0) \
+_op_(GPIO_J_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_J_ENABLE_CONFIG_01_0) \
+_op_(GPIO_J_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_J_INPUT_01_0) \
+_op_(GPIO_J_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_J_OUTPUT_VALUE_01_0) \
+_op_(GPIO_J_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_J_ENABLE_CONFIG_02_0) \
+_op_(GPIO_J_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_J_INPUT_02_0) \
+_op_(GPIO_J_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_J_OUTPUT_VALUE_02_0) \
+_op_(GPIO_J_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_J_ENABLE_CONFIG_03_0) \
+_op_(GPIO_J_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_J_INPUT_03_0) \
+_op_(GPIO_J_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_J_OUTPUT_VALUE_03_0) \
+_op_(GPIO_J_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_J_ENABLE_CONFIG_04_0) \
+_op_(GPIO_J_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_J_INPUT_04_0) \
+_op_(GPIO_J_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_J_OUTPUT_VALUE_04_0) \
+_op_(GPIO_J_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_J_ENABLE_CONFIG_05_0) \
+_op_(GPIO_J_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_J_INPUT_05_0) \
+_op_(GPIO_J_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_J_OUTPUT_VALUE_05_0) \
+_op_(GPIO_J_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_J_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_J_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_J_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_J_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_J_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_J_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_J_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_J_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_C_ENABLE_CONFIG_00_0) \
+_op_(GPIO_C_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_C_INPUT_00_0) \
+_op_(GPIO_C_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_C_OUTPUT_VALUE_00_0) \
+_op_(GPIO_C_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_C_ENABLE_CONFIG_01_0) \
+_op_(GPIO_C_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_C_INPUT_01_0) \
+_op_(GPIO_C_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_C_OUTPUT_VALUE_01_0) \
+_op_(GPIO_C_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_C_ENABLE_CONFIG_02_0) \
+_op_(GPIO_C_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_C_INPUT_02_0) \
+_op_(GPIO_C_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_C_OUTPUT_VALUE_02_0) \
+_op_(GPIO_C_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_C_ENABLE_CONFIG_03_0) \
+_op_(GPIO_C_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_C_INPUT_03_0) \
+_op_(GPIO_C_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_C_OUTPUT_VALUE_03_0) \
+_op_(GPIO_C_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_C_ENABLE_CONFIG_04_0) \
+_op_(GPIO_C_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_C_INPUT_04_0) \
+_op_(GPIO_C_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_C_OUTPUT_VALUE_04_0) \
+_op_(GPIO_C_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_C_ENABLE_CONFIG_05_0) \
+_op_(GPIO_C_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_C_INPUT_05_0) \
+_op_(GPIO_C_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_C_OUTPUT_VALUE_05_0) \
+_op_(GPIO_C_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_C_ENABLE_CONFIG_06_0) \
+_op_(GPIO_C_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_C_INPUT_06_0) \
+_op_(GPIO_C_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_C_OUTPUT_VALUE_06_0) \
+_op_(GPIO_C_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_C_ENABLE_CONFIG_07_0) \
+_op_(GPIO_C_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_C_INPUT_07_0) \
+_op_(GPIO_C_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_C_OUTPUT_VALUE_07_0) \
+_op_(GPIO_C_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_C_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_C_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_C_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_C_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_C_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_C_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_C_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_C_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_D_ENABLE_CONFIG_00_0) \
+_op_(GPIO_D_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_D_INPUT_00_0) \
+_op_(GPIO_D_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_D_OUTPUT_VALUE_00_0) \
+_op_(GPIO_D_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_D_ENABLE_CONFIG_01_0) \
+_op_(GPIO_D_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_D_INPUT_01_0) \
+_op_(GPIO_D_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_D_OUTPUT_VALUE_01_0) \
+_op_(GPIO_D_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_D_ENABLE_CONFIG_02_0) \
+_op_(GPIO_D_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_D_INPUT_02_0) \
+_op_(GPIO_D_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_D_OUTPUT_VALUE_02_0) \
+_op_(GPIO_D_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_D_ENABLE_CONFIG_03_0) \
+_op_(GPIO_D_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_D_INPUT_03_0) \
+_op_(GPIO_D_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_D_OUTPUT_VALUE_03_0) \
+_op_(GPIO_D_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_D_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_D_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_D_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_D_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_D_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_D_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_D_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_D_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_E_ENABLE_CONFIG_00_0) \
+_op_(GPIO_E_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_E_INPUT_00_0) \
+_op_(GPIO_E_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_E_OUTPUT_VALUE_00_0) \
+_op_(GPIO_E_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_E_ENABLE_CONFIG_01_0) \
+_op_(GPIO_E_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_E_INPUT_01_0) \
+_op_(GPIO_E_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_E_OUTPUT_VALUE_01_0) \
+_op_(GPIO_E_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_E_ENABLE_CONFIG_02_0) \
+_op_(GPIO_E_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_E_INPUT_02_0) \
+_op_(GPIO_E_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_E_OUTPUT_VALUE_02_0) \
+_op_(GPIO_E_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_E_ENABLE_CONFIG_03_0) \
+_op_(GPIO_E_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_E_INPUT_03_0) \
+_op_(GPIO_E_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_E_OUTPUT_VALUE_03_0) \
+_op_(GPIO_E_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_E_ENABLE_CONFIG_04_0) \
+_op_(GPIO_E_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_E_INPUT_04_0) \
+_op_(GPIO_E_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_E_OUTPUT_VALUE_04_0) \
+_op_(GPIO_E_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_E_ENABLE_CONFIG_05_0) \
+_op_(GPIO_E_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_E_INPUT_05_0) \
+_op_(GPIO_E_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_E_OUTPUT_VALUE_05_0) \
+_op_(GPIO_E_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_E_ENABLE_CONFIG_06_0) \
+_op_(GPIO_E_DEBOUNCE_THRESHOLD_06_0) \
+_op_(GPIO_E_INPUT_06_0) \
+_op_(GPIO_E_OUTPUT_CONTROL_06_0) \
+_op_(GPIO_E_OUTPUT_VALUE_06_0) \
+_op_(GPIO_E_INTERRUPT_CLEAR_06_0) \
+_op_(GPIO_E_ENABLE_CONFIG_07_0) \
+_op_(GPIO_E_DEBOUNCE_THRESHOLD_07_0) \
+_op_(GPIO_E_INPUT_07_0) \
+_op_(GPIO_E_OUTPUT_CONTROL_07_0) \
+_op_(GPIO_E_OUTPUT_VALUE_07_0) \
+_op_(GPIO_E_INTERRUPT_CLEAR_07_0) \
+_op_(GPIO_E_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_E_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_E_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_E_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_E_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_E_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_E_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_E_INTERRUPT_STATUS_G7_0) \
+_op_(GPIO_F_ENABLE_CONFIG_00_0) \
+_op_(GPIO_F_DEBOUNCE_THRESHOLD_00_0) \
+_op_(GPIO_F_INPUT_00_0) \
+_op_(GPIO_F_OUTPUT_CONTROL_00_0) \
+_op_(GPIO_F_OUTPUT_VALUE_00_0) \
+_op_(GPIO_F_INTERRUPT_CLEAR_00_0) \
+_op_(GPIO_F_ENABLE_CONFIG_01_0) \
+_op_(GPIO_F_DEBOUNCE_THRESHOLD_01_0) \
+_op_(GPIO_F_INPUT_01_0) \
+_op_(GPIO_F_OUTPUT_CONTROL_01_0) \
+_op_(GPIO_F_OUTPUT_VALUE_01_0) \
+_op_(GPIO_F_INTERRUPT_CLEAR_01_0) \
+_op_(GPIO_F_ENABLE_CONFIG_02_0) \
+_op_(GPIO_F_DEBOUNCE_THRESHOLD_02_0) \
+_op_(GPIO_F_INPUT_02_0) \
+_op_(GPIO_F_OUTPUT_CONTROL_02_0) \
+_op_(GPIO_F_OUTPUT_VALUE_02_0) \
+_op_(GPIO_F_INTERRUPT_CLEAR_02_0) \
+_op_(GPIO_F_ENABLE_CONFIG_03_0) \
+_op_(GPIO_F_DEBOUNCE_THRESHOLD_03_0) \
+_op_(GPIO_F_INPUT_03_0) \
+_op_(GPIO_F_OUTPUT_CONTROL_03_0) \
+_op_(GPIO_F_OUTPUT_VALUE_03_0) \
+_op_(GPIO_F_INTERRUPT_CLEAR_03_0) \
+_op_(GPIO_F_ENABLE_CONFIG_04_0) \
+_op_(GPIO_F_DEBOUNCE_THRESHOLD_04_0) \
+_op_(GPIO_F_INPUT_04_0) \
+_op_(GPIO_F_OUTPUT_CONTROL_04_0) \
+_op_(GPIO_F_OUTPUT_VALUE_04_0) \
+_op_(GPIO_F_INTERRUPT_CLEAR_04_0) \
+_op_(GPIO_F_ENABLE_CONFIG_05_0) \
+_op_(GPIO_F_DEBOUNCE_THRESHOLD_05_0) \
+_op_(GPIO_F_INPUT_05_0) \
+_op_(GPIO_F_OUTPUT_CONTROL_05_0) \
+_op_(GPIO_F_OUTPUT_VALUE_05_0) \
+_op_(GPIO_F_INTERRUPT_CLEAR_05_0) \
+_op_(GPIO_F_INTERRUPT_STATUS_G0_0) \
+_op_(GPIO_F_INTERRUPT_STATUS_G1_0) \
+_op_(GPIO_F_INTERRUPT_STATUS_G2_0) \
+_op_(GPIO_F_INTERRUPT_STATUS_G3_0) \
+_op_(GPIO_F_INTERRUPT_STATUS_G4_0) \
+_op_(GPIO_F_INTERRUPT_STATUS_G5_0) \
+_op_(GPIO_F_INTERRUPT_STATUS_G6_0) \
+_op_(GPIO_F_INTERRUPT_STATUS_G7_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_GPIO       0x00000000
+
+//
+// ARGPIO REGISTER BANKS
+//
+
+#define GPIO0_FIRST_REG 0x0000 // GPIO_A_VM_00_0
+#define GPIO0_LAST_REG 0x009c // GPIO_AD_SCR_03_0
+#define GPIO1_FIRST_REG 0x00c0 // GPIO_B_VM_00_0
+#define GPIO1_LAST_REG 0x00c4 // GPIO_B_SCR_00_0
+#define GPIO2_FIRST_REG 0x0800 // GPIO_CTL0_VM_SCR_0
+#define GPIO2_LAST_REG 0x0894 // GPIO_CTL0_SPARE_0
+#define GPIO3_FIRST_REG 0x1000 // GPIO_X_VM_00_0
+#define GPIO3_LAST_REG 0x10bc // GPIO_Z_SCR_07_0
+#define GPIO4_FIRST_REG 0x1800 // GPIO_CTL1_VM_SCR_0
+#define GPIO4_LAST_REG 0x1874 // GPIO_CTL1_SPARE_0
+#define GPIO5_FIRST_REG 0x2000 // GPIO_M_VM_00_0
+#define GPIO5_LAST_REG 0x212c // GPIO_R_SCR_05_0
+#define GPIO6_FIRST_REG 0x2800 // GPIO_CTL2_VM_SCR_0
+#define GPIO6_LAST_REG 0x28b4 // GPIO_CTL2_SPARE_0
+#define GPIO7_FIRST_REG 0x3000 // GPIO_K_VM_00_0
+#define GPIO7_LAST_REG 0x305c // GPIO_L_SCR_03_0
+#define GPIO8_FIRST_REG 0x3080 // GPIO_AG_VM_00_0
+#define GPIO8_LAST_REG 0x30cc // GPIO_AE_SCR_01_0
+#define GPIO9_FIRST_REG 0x3100 // GPIO_AF_VM_00_0
+#define GPIO9_LAST_REG 0x311c // GPIO_AF_SCR_03_0
+#define GPIO10_FIRST_REG 0x3800 // GPIO_CTL3_VM_SCR_0
+#define GPIO10_LAST_REG 0x38b4 // GPIO_CTL3_SPARE_0
+#define GPIO11_FIRST_REG 0x4000 // GPIO_G_VM_00_0
+#define GPIO11_LAST_REG 0x40b4 // GPIO_I_SCR_06_0
+#define GPIO12_FIRST_REG 0x4800 // GPIO_CTL4_VM_SCR_0
+#define GPIO12_LAST_REG 0x4874 // GPIO_CTL4_SPARE_0
+#define GPIO13_FIRST_REG 0x5000 // GPIO_J_VM_00_0
+#define GPIO13_LAST_REG 0x502c // GPIO_J_SCR_05_0
+#define GPIO14_FIRST_REG 0x5040 // GPIO_C_VM_00_0
+#define GPIO14_LAST_REG 0x509c // GPIO_D_SCR_03_0
+#define GPIO15_FIRST_REG 0x50c0 // GPIO_E_VM_00_0
+#define GPIO15_LAST_REG 0x512c // GPIO_F_SCR_05_0
+#define GPIO16_FIRST_REG 0x5800 // GPIO_CTL5_VM_SCR_0
+#define GPIO16_LAST_REG 0x58b4 // GPIO_CTL5_SPARE_0
+#define GPIO17_FIRST_REG 0x10000 // GPIO_A_ENABLE_CONFIG_00_0
+#define GPIO17_LAST_REG 0x10014 // GPIO_A_INTERRUPT_CLEAR_00_0
+#define GPIO18_FIRST_REG 0x10020 // GPIO_A_ENABLE_CONFIG_01_0
+#define GPIO18_LAST_REG 0x10034 // GPIO_A_INTERRUPT_CLEAR_01_0
+#define GPIO19_FIRST_REG 0x10040 // GPIO_A_ENABLE_CONFIG_02_0
+#define GPIO19_LAST_REG 0x10054 // GPIO_A_INTERRUPT_CLEAR_02_0
+#define GPIO20_FIRST_REG 0x10060 // GPIO_A_ENABLE_CONFIG_03_0
+#define GPIO20_LAST_REG 0x10074 // GPIO_A_INTERRUPT_CLEAR_03_0
+#define GPIO21_FIRST_REG 0x10080 // GPIO_A_ENABLE_CONFIG_04_0
+#define GPIO21_LAST_REG 0x10094 // GPIO_A_INTERRUPT_CLEAR_04_0
+#define GPIO22_FIRST_REG 0x100a0 // GPIO_A_ENABLE_CONFIG_05_0
+#define GPIO22_LAST_REG 0x100b4 // GPIO_A_INTERRUPT_CLEAR_05_0
+#define GPIO23_FIRST_REG 0x100c0 // GPIO_A_ENABLE_CONFIG_06_0
+#define GPIO23_LAST_REG 0x100d4 // GPIO_A_INTERRUPT_CLEAR_06_0
+#define GPIO24_FIRST_REG 0x100e0 // GPIO_A_ENABLE_CONFIG_07_0
+#define GPIO24_LAST_REG 0x100f4 // GPIO_A_INTERRUPT_CLEAR_07_0
+#define GPIO25_FIRST_REG 0x10100 // GPIO_A_INTERRUPT_STATUS_G0_0
+#define GPIO25_LAST_REG 0x1011c // GPIO_A_INTERRUPT_STATUS_G7_0
+#define GPIO26_FIRST_REG 0x10200 // GPIO_AC_ENABLE_CONFIG_00_0
+#define GPIO26_LAST_REG 0x10214 // GPIO_AC_INTERRUPT_CLEAR_00_0
+#define GPIO27_FIRST_REG 0x10220 // GPIO_AC_ENABLE_CONFIG_01_0
+#define GPIO27_LAST_REG 0x10234 // GPIO_AC_INTERRUPT_CLEAR_01_0
+#define GPIO28_FIRST_REG 0x10240 // GPIO_AC_ENABLE_CONFIG_02_0
+#define GPIO28_LAST_REG 0x10254 // GPIO_AC_INTERRUPT_CLEAR_02_0
+#define GPIO29_FIRST_REG 0x10260 // GPIO_AC_ENABLE_CONFIG_03_0
+#define GPIO29_LAST_REG 0x10274 // GPIO_AC_INTERRUPT_CLEAR_03_0
+#define GPIO30_FIRST_REG 0x10280 // GPIO_AC_ENABLE_CONFIG_04_0
+#define GPIO30_LAST_REG 0x10294 // GPIO_AC_INTERRUPT_CLEAR_04_0
+#define GPIO31_FIRST_REG 0x102a0 // GPIO_AC_ENABLE_CONFIG_05_0
+#define GPIO31_LAST_REG 0x102b4 // GPIO_AC_INTERRUPT_CLEAR_05_0
+#define GPIO32_FIRST_REG 0x102c0 // GPIO_AC_ENABLE_CONFIG_06_0
+#define GPIO32_LAST_REG 0x102d4 // GPIO_AC_INTERRUPT_CLEAR_06_0
+#define GPIO33_FIRST_REG 0x102e0 // GPIO_AC_ENABLE_CONFIG_07_0
+#define GPIO33_LAST_REG 0x102f4 // GPIO_AC_INTERRUPT_CLEAR_07_0
+#define GPIO34_FIRST_REG 0x10300 // GPIO_AC_INTERRUPT_STATUS_G0_0
+#define GPIO34_LAST_REG 0x1031c // GPIO_AC_INTERRUPT_STATUS_G7_0
+#define GPIO35_FIRST_REG 0x10400 // GPIO_AD_ENABLE_CONFIG_00_0
+#define GPIO35_LAST_REG 0x10414 // GPIO_AD_INTERRUPT_CLEAR_00_0
+#define GPIO36_FIRST_REG 0x10420 // GPIO_AD_ENABLE_CONFIG_01_0
+#define GPIO36_LAST_REG 0x10434 // GPIO_AD_INTERRUPT_CLEAR_01_0
+#define GPIO37_FIRST_REG 0x10440 // GPIO_AD_ENABLE_CONFIG_02_0
+#define GPIO37_LAST_REG 0x10454 // GPIO_AD_INTERRUPT_CLEAR_02_0
+#define GPIO38_FIRST_REG 0x10460 // GPIO_AD_ENABLE_CONFIG_03_0
+#define GPIO38_LAST_REG 0x10474 // GPIO_AD_INTERRUPT_CLEAR_03_0
+#define GPIO39_FIRST_REG 0x10500 // GPIO_AD_INTERRUPT_STATUS_G0_0
+#define GPIO39_LAST_REG 0x1051c // GPIO_AD_INTERRUPT_STATUS_G7_0
+#define GPIO40_FIRST_REG 0x10600 // GPIO_B_ENABLE_CONFIG_00_0
+#define GPIO40_LAST_REG 0x10614 // GPIO_B_INTERRUPT_CLEAR_00_0
+#define GPIO41_FIRST_REG 0x10700 // GPIO_B_INTERRUPT_STATUS_G0_0
+#define GPIO41_LAST_REG 0x1071c // GPIO_B_INTERRUPT_STATUS_G7_0
+#define GPIO42_FIRST_REG 0x11000 // GPIO_X_ENABLE_CONFIG_00_0
+#define GPIO42_LAST_REG 0x11014 // GPIO_X_INTERRUPT_CLEAR_00_0
+#define GPIO43_FIRST_REG 0x11020 // GPIO_X_ENABLE_CONFIG_01_0
+#define GPIO43_LAST_REG 0x11034 // GPIO_X_INTERRUPT_CLEAR_01_0
+#define GPIO44_FIRST_REG 0x11040 // GPIO_X_ENABLE_CONFIG_02_0
+#define GPIO44_LAST_REG 0x11054 // GPIO_X_INTERRUPT_CLEAR_02_0
+#define GPIO45_FIRST_REG 0x11060 // GPIO_X_ENABLE_CONFIG_03_0
+#define GPIO45_LAST_REG 0x11074 // GPIO_X_INTERRUPT_CLEAR_03_0
+#define GPIO46_FIRST_REG 0x11080 // GPIO_X_ENABLE_CONFIG_04_0
+#define GPIO46_LAST_REG 0x11094 // GPIO_X_INTERRUPT_CLEAR_04_0
+#define GPIO47_FIRST_REG 0x110a0 // GPIO_X_ENABLE_CONFIG_05_0
+#define GPIO47_LAST_REG 0x110b4 // GPIO_X_INTERRUPT_CLEAR_05_0
+#define GPIO48_FIRST_REG 0x110c0 // GPIO_X_ENABLE_CONFIG_06_0
+#define GPIO48_LAST_REG 0x110d4 // GPIO_X_INTERRUPT_CLEAR_06_0
+#define GPIO49_FIRST_REG 0x110e0 // GPIO_X_ENABLE_CONFIG_07_0
+#define GPIO49_LAST_REG 0x110f4 // GPIO_X_INTERRUPT_CLEAR_07_0
+#define GPIO50_FIRST_REG 0x11100 // GPIO_X_INTERRUPT_STATUS_G0_0
+#define GPIO50_LAST_REG 0x1111c // GPIO_X_INTERRUPT_STATUS_G7_0
+#define GPIO51_FIRST_REG 0x11200 // GPIO_Y_ENABLE_CONFIG_00_0
+#define GPIO51_LAST_REG 0x11214 // GPIO_Y_INTERRUPT_CLEAR_00_0
+#define GPIO52_FIRST_REG 0x11220 // GPIO_Y_ENABLE_CONFIG_01_0
+#define GPIO52_LAST_REG 0x11234 // GPIO_Y_INTERRUPT_CLEAR_01_0
+#define GPIO53_FIRST_REG 0x11240 // GPIO_Y_ENABLE_CONFIG_02_0
+#define GPIO53_LAST_REG 0x11254 // GPIO_Y_INTERRUPT_CLEAR_02_0
+#define GPIO54_FIRST_REG 0x11260 // GPIO_Y_ENABLE_CONFIG_03_0
+#define GPIO54_LAST_REG 0x11274 // GPIO_Y_INTERRUPT_CLEAR_03_0
+#define GPIO55_FIRST_REG 0x11280 // GPIO_Y_ENABLE_CONFIG_04_0
+#define GPIO55_LAST_REG 0x11294 // GPIO_Y_INTERRUPT_CLEAR_04_0
+#define GPIO56_FIRST_REG 0x112a0 // GPIO_Y_ENABLE_CONFIG_05_0
+#define GPIO56_LAST_REG 0x112b4 // GPIO_Y_INTERRUPT_CLEAR_05_0
+#define GPIO57_FIRST_REG 0x112c0 // GPIO_Y_ENABLE_CONFIG_06_0
+#define GPIO57_LAST_REG 0x112d4 // GPIO_Y_INTERRUPT_CLEAR_06_0
+#define GPIO58_FIRST_REG 0x112e0 // GPIO_Y_ENABLE_CONFIG_07_0
+#define GPIO58_LAST_REG 0x112f4 // GPIO_Y_INTERRUPT_CLEAR_07_0
+#define GPIO59_FIRST_REG 0x11300 // GPIO_Y_INTERRUPT_STATUS_G0_0
+#define GPIO59_LAST_REG 0x1131c // GPIO_Y_INTERRUPT_STATUS_G7_0
+#define GPIO60_FIRST_REG 0x11400 // GPIO_Z_ENABLE_CONFIG_00_0
+#define GPIO60_LAST_REG 0x11414 // GPIO_Z_INTERRUPT_CLEAR_00_0
+#define GPIO61_FIRST_REG 0x11420 // GPIO_Z_ENABLE_CONFIG_01_0
+#define GPIO61_LAST_REG 0x11434 // GPIO_Z_INTERRUPT_CLEAR_01_0
+#define GPIO62_FIRST_REG 0x11440 // GPIO_Z_ENABLE_CONFIG_02_0
+#define GPIO62_LAST_REG 0x11454 // GPIO_Z_INTERRUPT_CLEAR_02_0
+#define GPIO63_FIRST_REG 0x11460 // GPIO_Z_ENABLE_CONFIG_03_0
+#define GPIO63_LAST_REG 0x11474 // GPIO_Z_INTERRUPT_CLEAR_03_0
+#define GPIO64_FIRST_REG 0x11480 // GPIO_Z_ENABLE_CONFIG_04_0
+#define GPIO64_LAST_REG 0x11494 // GPIO_Z_INTERRUPT_CLEAR_04_0
+#define GPIO65_FIRST_REG 0x114a0 // GPIO_Z_ENABLE_CONFIG_05_0
+#define GPIO65_LAST_REG 0x114b4 // GPIO_Z_INTERRUPT_CLEAR_05_0
+#define GPIO66_FIRST_REG 0x114c0 // GPIO_Z_ENABLE_CONFIG_06_0
+#define GPIO66_LAST_REG 0x114d4 // GPIO_Z_INTERRUPT_CLEAR_06_0
+#define GPIO67_FIRST_REG 0x114e0 // GPIO_Z_ENABLE_CONFIG_07_0
+#define GPIO67_LAST_REG 0x114f4 // GPIO_Z_INTERRUPT_CLEAR_07_0
+#define GPIO68_FIRST_REG 0x11500 // GPIO_Z_INTERRUPT_STATUS_G0_0
+#define GPIO68_LAST_REG 0x1151c // GPIO_Z_INTERRUPT_STATUS_G7_0
+#define GPIO69_FIRST_REG 0x12000 // GPIO_M_ENABLE_CONFIG_00_0
+#define GPIO69_LAST_REG 0x12014 // GPIO_M_INTERRUPT_CLEAR_00_0
+#define GPIO70_FIRST_REG 0x12020 // GPIO_M_ENABLE_CONFIG_01_0
+#define GPIO70_LAST_REG 0x12034 // GPIO_M_INTERRUPT_CLEAR_01_0
+#define GPIO71_FIRST_REG 0x12040 // GPIO_M_ENABLE_CONFIG_02_0
+#define GPIO71_LAST_REG 0x12054 // GPIO_M_INTERRUPT_CLEAR_02_0
+#define GPIO72_FIRST_REG 0x12060 // GPIO_M_ENABLE_CONFIG_03_0
+#define GPIO72_LAST_REG 0x12074 // GPIO_M_INTERRUPT_CLEAR_03_0
+#define GPIO73_FIRST_REG 0x12080 // GPIO_M_ENABLE_CONFIG_04_0
+#define GPIO73_LAST_REG 0x12094 // GPIO_M_INTERRUPT_CLEAR_04_0
+#define GPIO74_FIRST_REG 0x120a0 // GPIO_M_ENABLE_CONFIG_05_0
+#define GPIO74_LAST_REG 0x120b4 // GPIO_M_INTERRUPT_CLEAR_05_0
+#define GPIO75_FIRST_REG 0x120c0 // GPIO_M_ENABLE_CONFIG_06_0
+#define GPIO75_LAST_REG 0x120d4 // GPIO_M_INTERRUPT_CLEAR_06_0
+#define GPIO76_FIRST_REG 0x120e0 // GPIO_M_ENABLE_CONFIG_07_0
+#define GPIO76_LAST_REG 0x120f4 // GPIO_M_INTERRUPT_CLEAR_07_0
+#define GPIO77_FIRST_REG 0x12100 // GPIO_M_INTERRUPT_STATUS_G0_0
+#define GPIO77_LAST_REG 0x1211c // GPIO_M_INTERRUPT_STATUS_G7_0
+#define GPIO78_FIRST_REG 0x12200 // GPIO_N_ENABLE_CONFIG_00_0
+#define GPIO78_LAST_REG 0x12214 // GPIO_N_INTERRUPT_CLEAR_00_0
+#define GPIO79_FIRST_REG 0x12220 // GPIO_N_ENABLE_CONFIG_01_0
+#define GPIO79_LAST_REG 0x12234 // GPIO_N_INTERRUPT_CLEAR_01_0
+#define GPIO80_FIRST_REG 0x12240 // GPIO_N_ENABLE_CONFIG_02_0
+#define GPIO80_LAST_REG 0x12254 // GPIO_N_INTERRUPT_CLEAR_02_0
+#define GPIO81_FIRST_REG 0x12260 // GPIO_N_ENABLE_CONFIG_03_0
+#define GPIO81_LAST_REG 0x12274 // GPIO_N_INTERRUPT_CLEAR_03_0
+#define GPIO82_FIRST_REG 0x12280 // GPIO_N_ENABLE_CONFIG_04_0
+#define GPIO82_LAST_REG 0x12294 // GPIO_N_INTERRUPT_CLEAR_04_0
+#define GPIO83_FIRST_REG 0x122a0 // GPIO_N_ENABLE_CONFIG_05_0
+#define GPIO83_LAST_REG 0x122b4 // GPIO_N_INTERRUPT_CLEAR_05_0
+#define GPIO84_FIRST_REG 0x122c0 // GPIO_N_ENABLE_CONFIG_06_0
+#define GPIO84_LAST_REG 0x122d4 // GPIO_N_INTERRUPT_CLEAR_06_0
+#define GPIO85_FIRST_REG 0x122e0 // GPIO_N_ENABLE_CONFIG_07_0
+#define GPIO85_LAST_REG 0x122f4 // GPIO_N_INTERRUPT_CLEAR_07_0
+#define GPIO86_FIRST_REG 0x12300 // GPIO_N_INTERRUPT_STATUS_G0_0
+#define GPIO86_LAST_REG 0x1231c // GPIO_N_INTERRUPT_STATUS_G7_0
+#define GPIO87_FIRST_REG 0x12400 // GPIO_P_ENABLE_CONFIG_00_0
+#define GPIO87_LAST_REG 0x12414 // GPIO_P_INTERRUPT_CLEAR_00_0
+#define GPIO88_FIRST_REG 0x12420 // GPIO_P_ENABLE_CONFIG_01_0
+#define GPIO88_LAST_REG 0x12434 // GPIO_P_INTERRUPT_CLEAR_01_0
+#define GPIO89_FIRST_REG 0x12440 // GPIO_P_ENABLE_CONFIG_02_0
+#define GPIO89_LAST_REG 0x12454 // GPIO_P_INTERRUPT_CLEAR_02_0
+#define GPIO90_FIRST_REG 0x12460 // GPIO_P_ENABLE_CONFIG_03_0
+#define GPIO90_LAST_REG 0x12474 // GPIO_P_INTERRUPT_CLEAR_03_0
+#define GPIO91_FIRST_REG 0x12480 // GPIO_P_ENABLE_CONFIG_04_0
+#define GPIO91_LAST_REG 0x12494 // GPIO_P_INTERRUPT_CLEAR_04_0
+#define GPIO92_FIRST_REG 0x124a0 // GPIO_P_ENABLE_CONFIG_05_0
+#define GPIO92_LAST_REG 0x124b4 // GPIO_P_INTERRUPT_CLEAR_05_0
+#define GPIO93_FIRST_REG 0x124c0 // GPIO_P_ENABLE_CONFIG_06_0
+#define GPIO93_LAST_REG 0x124d4 // GPIO_P_INTERRUPT_CLEAR_06_0
+#define GPIO94_FIRST_REG 0x124e0 // GPIO_P_ENABLE_CONFIG_07_0
+#define GPIO94_LAST_REG 0x124f4 // GPIO_P_INTERRUPT_CLEAR_07_0
+#define GPIO95_FIRST_REG 0x12500 // GPIO_P_INTERRUPT_STATUS_G0_0
+#define GPIO95_LAST_REG 0x1251c // GPIO_P_INTERRUPT_STATUS_G7_0
+#define GPIO96_FIRST_REG 0x12600 // GPIO_Q_ENABLE_CONFIG_00_0
+#define GPIO96_LAST_REG 0x12614 // GPIO_Q_INTERRUPT_CLEAR_00_0
+#define GPIO97_FIRST_REG 0x12620 // GPIO_Q_ENABLE_CONFIG_01_0
+#define GPIO97_LAST_REG 0x12634 // GPIO_Q_INTERRUPT_CLEAR_01_0
+#define GPIO98_FIRST_REG 0x12640 // GPIO_Q_ENABLE_CONFIG_02_0
+#define GPIO98_LAST_REG 0x12654 // GPIO_Q_INTERRUPT_CLEAR_02_0
+#define GPIO99_FIRST_REG 0x12660 // GPIO_Q_ENABLE_CONFIG_03_0
+#define GPIO99_LAST_REG 0x12674 // GPIO_Q_INTERRUPT_CLEAR_03_0
+#define GPIO100_FIRST_REG 0x12680 // GPIO_Q_ENABLE_CONFIG_04_0
+#define GPIO100_LAST_REG 0x12694 // GPIO_Q_INTERRUPT_CLEAR_04_0
+#define GPIO101_FIRST_REG 0x126a0 // GPIO_Q_ENABLE_CONFIG_05_0
+#define GPIO101_LAST_REG 0x126b4 // GPIO_Q_INTERRUPT_CLEAR_05_0
+#define GPIO102_FIRST_REG 0x126c0 // GPIO_Q_ENABLE_CONFIG_06_0
+#define GPIO102_LAST_REG 0x126d4 // GPIO_Q_INTERRUPT_CLEAR_06_0
+#define GPIO103_FIRST_REG 0x126e0 // GPIO_Q_ENABLE_CONFIG_07_0
+#define GPIO103_LAST_REG 0x126f4 // GPIO_Q_INTERRUPT_CLEAR_07_0
+#define GPIO104_FIRST_REG 0x12700 // GPIO_Q_INTERRUPT_STATUS_G0_0
+#define GPIO104_LAST_REG 0x1271c // GPIO_Q_INTERRUPT_STATUS_G7_0
+#define GPIO105_FIRST_REG 0x12800 // GPIO_R_ENABLE_CONFIG_00_0
+#define GPIO105_LAST_REG 0x12814 // GPIO_R_INTERRUPT_CLEAR_00_0
+#define GPIO106_FIRST_REG 0x12820 // GPIO_R_ENABLE_CONFIG_01_0
+#define GPIO106_LAST_REG 0x12834 // GPIO_R_INTERRUPT_CLEAR_01_0
+#define GPIO107_FIRST_REG 0x12840 // GPIO_R_ENABLE_CONFIG_02_0
+#define GPIO107_LAST_REG 0x12854 // GPIO_R_INTERRUPT_CLEAR_02_0
+#define GPIO108_FIRST_REG 0x12860 // GPIO_R_ENABLE_CONFIG_03_0
+#define GPIO108_LAST_REG 0x12874 // GPIO_R_INTERRUPT_CLEAR_03_0
+#define GPIO109_FIRST_REG 0x12880 // GPIO_R_ENABLE_CONFIG_04_0
+#define GPIO109_LAST_REG 0x12894 // GPIO_R_INTERRUPT_CLEAR_04_0
+#define GPIO110_FIRST_REG 0x128a0 // GPIO_R_ENABLE_CONFIG_05_0
+#define GPIO110_LAST_REG 0x128b4 // GPIO_R_INTERRUPT_CLEAR_05_0
+#define GPIO111_FIRST_REG 0x12900 // GPIO_R_INTERRUPT_STATUS_G0_0
+#define GPIO111_LAST_REG 0x1291c // GPIO_R_INTERRUPT_STATUS_G7_0
+#define GPIO112_FIRST_REG 0x13000 // GPIO_K_ENABLE_CONFIG_00_0
+#define GPIO112_LAST_REG 0x13014 // GPIO_K_INTERRUPT_CLEAR_00_0
+#define GPIO113_FIRST_REG 0x13020 // GPIO_K_ENABLE_CONFIG_01_0
+#define GPIO113_LAST_REG 0x13034 // GPIO_K_INTERRUPT_CLEAR_01_0
+#define GPIO114_FIRST_REG 0x13040 // GPIO_K_ENABLE_CONFIG_02_0
+#define GPIO114_LAST_REG 0x13054 // GPIO_K_INTERRUPT_CLEAR_02_0
+#define GPIO115_FIRST_REG 0x13060 // GPIO_K_ENABLE_CONFIG_03_0
+#define GPIO115_LAST_REG 0x13074 // GPIO_K_INTERRUPT_CLEAR_03_0
+#define GPIO116_FIRST_REG 0x13080 // GPIO_K_ENABLE_CONFIG_04_0
+#define GPIO116_LAST_REG 0x13094 // GPIO_K_INTERRUPT_CLEAR_04_0
+#define GPIO117_FIRST_REG 0x130a0 // GPIO_K_ENABLE_CONFIG_05_0
+#define GPIO117_LAST_REG 0x130b4 // GPIO_K_INTERRUPT_CLEAR_05_0
+#define GPIO118_FIRST_REG 0x130c0 // GPIO_K_ENABLE_CONFIG_06_0
+#define GPIO118_LAST_REG 0x130d4 // GPIO_K_INTERRUPT_CLEAR_06_0
+#define GPIO119_FIRST_REG 0x130e0 // GPIO_K_ENABLE_CONFIG_07_0
+#define GPIO119_LAST_REG 0x130f4 // GPIO_K_INTERRUPT_CLEAR_07_0
+#define GPIO120_FIRST_REG 0x13100 // GPIO_K_INTERRUPT_STATUS_G0_0
+#define GPIO120_LAST_REG 0x1311c // GPIO_K_INTERRUPT_STATUS_G7_0
+#define GPIO121_FIRST_REG 0x13200 // GPIO_L_ENABLE_CONFIG_00_0
+#define GPIO121_LAST_REG 0x13214 // GPIO_L_INTERRUPT_CLEAR_00_0
+#define GPIO122_FIRST_REG 0x13220 // GPIO_L_ENABLE_CONFIG_01_0
+#define GPIO122_LAST_REG 0x13234 // GPIO_L_INTERRUPT_CLEAR_01_0
+#define GPIO123_FIRST_REG 0x13240 // GPIO_L_ENABLE_CONFIG_02_0
+#define GPIO123_LAST_REG 0x13254 // GPIO_L_INTERRUPT_CLEAR_02_0
+#define GPIO124_FIRST_REG 0x13260 // GPIO_L_ENABLE_CONFIG_03_0
+#define GPIO124_LAST_REG 0x13274 // GPIO_L_INTERRUPT_CLEAR_03_0
+#define GPIO125_FIRST_REG 0x13300 // GPIO_L_INTERRUPT_STATUS_G0_0
+#define GPIO125_LAST_REG 0x1331c // GPIO_L_INTERRUPT_STATUS_G7_0
+#define GPIO126_FIRST_REG 0x13400 // GPIO_AG_ENABLE_CONFIG_00_0
+#define GPIO126_LAST_REG 0x13414 // GPIO_AG_INTERRUPT_CLEAR_00_0
+#define GPIO127_FIRST_REG 0x13420 // GPIO_AG_ENABLE_CONFIG_01_0
+#define GPIO127_LAST_REG 0x13434 // GPIO_AG_INTERRUPT_CLEAR_01_0
+#define GPIO128_FIRST_REG 0x13440 // GPIO_AG_ENABLE_CONFIG_02_0
+#define GPIO128_LAST_REG 0x13454 // GPIO_AG_INTERRUPT_CLEAR_02_0
+#define GPIO129_FIRST_REG 0x13460 // GPIO_AG_ENABLE_CONFIG_03_0
+#define GPIO129_LAST_REG 0x13474 // GPIO_AG_INTERRUPT_CLEAR_03_0
+#define GPIO130_FIRST_REG 0x13480 // GPIO_AG_ENABLE_CONFIG_04_0
+#define GPIO130_LAST_REG 0x13494 // GPIO_AG_INTERRUPT_CLEAR_04_0
+#define GPIO131_FIRST_REG 0x134a0 // GPIO_AG_ENABLE_CONFIG_05_0
+#define GPIO131_LAST_REG 0x134b4 // GPIO_AG_INTERRUPT_CLEAR_05_0
+#define GPIO132_FIRST_REG 0x134c0 // GPIO_AG_ENABLE_CONFIG_06_0
+#define GPIO132_LAST_REG 0x134d4 // GPIO_AG_INTERRUPT_CLEAR_06_0
+#define GPIO133_FIRST_REG 0x134e0 // GPIO_AG_ENABLE_CONFIG_07_0
+#define GPIO133_LAST_REG 0x134f4 // GPIO_AG_INTERRUPT_CLEAR_07_0
+#define GPIO134_FIRST_REG 0x13500 // GPIO_AG_INTERRUPT_STATUS_G0_0
+#define GPIO134_LAST_REG 0x1351c // GPIO_AG_INTERRUPT_STATUS_G7_0
+#define GPIO135_FIRST_REG 0x13600 // GPIO_AE_ENABLE_CONFIG_00_0
+#define GPIO135_LAST_REG 0x13614 // GPIO_AE_INTERRUPT_CLEAR_00_0
+#define GPIO136_FIRST_REG 0x13620 // GPIO_AE_ENABLE_CONFIG_01_0
+#define GPIO136_LAST_REG 0x13634 // GPIO_AE_INTERRUPT_CLEAR_01_0
+#define GPIO137_FIRST_REG 0x13700 // GPIO_AE_INTERRUPT_STATUS_G0_0
+#define GPIO137_LAST_REG 0x1371c // GPIO_AE_INTERRUPT_STATUS_G7_0
+#define GPIO138_FIRST_REG 0x13800 // GPIO_AF_ENABLE_CONFIG_00_0
+#define GPIO138_LAST_REG 0x13814 // GPIO_AF_INTERRUPT_CLEAR_00_0
+#define GPIO139_FIRST_REG 0x13820 // GPIO_AF_ENABLE_CONFIG_01_0
+#define GPIO139_LAST_REG 0x13834 // GPIO_AF_INTERRUPT_CLEAR_01_0
+#define GPIO140_FIRST_REG 0x13840 // GPIO_AF_ENABLE_CONFIG_02_0
+#define GPIO140_LAST_REG 0x13854 // GPIO_AF_INTERRUPT_CLEAR_02_0
+#define GPIO141_FIRST_REG 0x13860 // GPIO_AF_ENABLE_CONFIG_03_0
+#define GPIO141_LAST_REG 0x13874 // GPIO_AF_INTERRUPT_CLEAR_03_0
+#define GPIO142_FIRST_REG 0x13900 // GPIO_AF_INTERRUPT_STATUS_G0_0
+#define GPIO142_LAST_REG 0x1391c // GPIO_AF_INTERRUPT_STATUS_G7_0
+#define GPIO143_FIRST_REG 0x14000 // GPIO_G_ENABLE_CONFIG_00_0
+#define GPIO143_LAST_REG 0x14014 // GPIO_G_INTERRUPT_CLEAR_00_0
+#define GPIO144_FIRST_REG 0x14020 // GPIO_G_ENABLE_CONFIG_01_0
+#define GPIO144_LAST_REG 0x14034 // GPIO_G_INTERRUPT_CLEAR_01_0
+#define GPIO145_FIRST_REG 0x14040 // GPIO_G_ENABLE_CONFIG_02_0
+#define GPIO145_LAST_REG 0x14054 // GPIO_G_INTERRUPT_CLEAR_02_0
+#define GPIO146_FIRST_REG 0x14060 // GPIO_G_ENABLE_CONFIG_03_0
+#define GPIO146_LAST_REG 0x14074 // GPIO_G_INTERRUPT_CLEAR_03_0
+#define GPIO147_FIRST_REG 0x14080 // GPIO_G_ENABLE_CONFIG_04_0
+#define GPIO147_LAST_REG 0x14094 // GPIO_G_INTERRUPT_CLEAR_04_0
+#define GPIO148_FIRST_REG 0x140a0 // GPIO_G_ENABLE_CONFIG_05_0
+#define GPIO148_LAST_REG 0x140b4 // GPIO_G_INTERRUPT_CLEAR_05_0
+#define GPIO149_FIRST_REG 0x140c0 // GPIO_G_ENABLE_CONFIG_06_0
+#define GPIO149_LAST_REG 0x140d4 // GPIO_G_INTERRUPT_CLEAR_06_0
+#define GPIO150_FIRST_REG 0x140e0 // GPIO_G_ENABLE_CONFIG_07_0
+#define GPIO150_LAST_REG 0x140f4 // GPIO_G_INTERRUPT_CLEAR_07_0
+#define GPIO151_FIRST_REG 0x14100 // GPIO_G_INTERRUPT_STATUS_G0_0
+#define GPIO151_LAST_REG 0x1411c // GPIO_G_INTERRUPT_STATUS_G7_0
+#define GPIO152_FIRST_REG 0x14200 // GPIO_H_ENABLE_CONFIG_00_0
+#define GPIO152_LAST_REG 0x14214 // GPIO_H_INTERRUPT_CLEAR_00_0
+#define GPIO153_FIRST_REG 0x14220 // GPIO_H_ENABLE_CONFIG_01_0
+#define GPIO153_LAST_REG 0x14234 // GPIO_H_INTERRUPT_CLEAR_01_0
+#define GPIO154_FIRST_REG 0x14240 // GPIO_H_ENABLE_CONFIG_02_0
+#define GPIO154_LAST_REG 0x14254 // GPIO_H_INTERRUPT_CLEAR_02_0
+#define GPIO155_FIRST_REG 0x14260 // GPIO_H_ENABLE_CONFIG_03_0
+#define GPIO155_LAST_REG 0x14274 // GPIO_H_INTERRUPT_CLEAR_03_0
+#define GPIO156_FIRST_REG 0x14280 // GPIO_H_ENABLE_CONFIG_04_0
+#define GPIO156_LAST_REG 0x14294 // GPIO_H_INTERRUPT_CLEAR_04_0
+#define GPIO157_FIRST_REG 0x142a0 // GPIO_H_ENABLE_CONFIG_05_0
+#define GPIO157_LAST_REG 0x142b4 // GPIO_H_INTERRUPT_CLEAR_05_0
+#define GPIO158_FIRST_REG 0x142c0 // GPIO_H_ENABLE_CONFIG_06_0
+#define GPIO158_LAST_REG 0x142d4 // GPIO_H_INTERRUPT_CLEAR_06_0
+#define GPIO159_FIRST_REG 0x142e0 // GPIO_H_ENABLE_CONFIG_07_0
+#define GPIO159_LAST_REG 0x142f4 // GPIO_H_INTERRUPT_CLEAR_07_0
+#define GPIO160_FIRST_REG 0x14300 // GPIO_H_INTERRUPT_STATUS_G0_0
+#define GPIO160_LAST_REG 0x1431c // GPIO_H_INTERRUPT_STATUS_G7_0
+#define GPIO161_FIRST_REG 0x14400 // GPIO_I_ENABLE_CONFIG_00_0
+#define GPIO161_LAST_REG 0x14414 // GPIO_I_INTERRUPT_CLEAR_00_0
+#define GPIO162_FIRST_REG 0x14420 // GPIO_I_ENABLE_CONFIG_01_0
+#define GPIO162_LAST_REG 0x14434 // GPIO_I_INTERRUPT_CLEAR_01_0
+#define GPIO163_FIRST_REG 0x14440 // GPIO_I_ENABLE_CONFIG_02_0
+#define GPIO163_LAST_REG 0x14454 // GPIO_I_INTERRUPT_CLEAR_02_0
+#define GPIO164_FIRST_REG 0x14460 // GPIO_I_ENABLE_CONFIG_03_0
+#define GPIO164_LAST_REG 0x14474 // GPIO_I_INTERRUPT_CLEAR_03_0
+#define GPIO165_FIRST_REG 0x14480 // GPIO_I_ENABLE_CONFIG_04_0
+#define GPIO165_LAST_REG 0x14494 // GPIO_I_INTERRUPT_CLEAR_04_0
+#define GPIO166_FIRST_REG 0x144a0 // GPIO_I_ENABLE_CONFIG_05_0
+#define GPIO166_LAST_REG 0x144b4 // GPIO_I_INTERRUPT_CLEAR_05_0
+#define GPIO167_FIRST_REG 0x144c0 // GPIO_I_ENABLE_CONFIG_06_0
+#define GPIO167_LAST_REG 0x144d4 // GPIO_I_INTERRUPT_CLEAR_06_0
+#define GPIO168_FIRST_REG 0x14500 // GPIO_I_INTERRUPT_STATUS_G0_0
+#define GPIO168_LAST_REG 0x1451c // GPIO_I_INTERRUPT_STATUS_G7_0
+#define GPIO169_FIRST_REG 0x15000 // GPIO_J_ENABLE_CONFIG_00_0
+#define GPIO169_LAST_REG 0x15014 // GPIO_J_INTERRUPT_CLEAR_00_0
+#define GPIO170_FIRST_REG 0x15020 // GPIO_J_ENABLE_CONFIG_01_0
+#define GPIO170_LAST_REG 0x15034 // GPIO_J_INTERRUPT_CLEAR_01_0
+#define GPIO171_FIRST_REG 0x15040 // GPIO_J_ENABLE_CONFIG_02_0
+#define GPIO171_LAST_REG 0x15054 // GPIO_J_INTERRUPT_CLEAR_02_0
+#define GPIO172_FIRST_REG 0x15060 // GPIO_J_ENABLE_CONFIG_03_0
+#define GPIO172_LAST_REG 0x15074 // GPIO_J_INTERRUPT_CLEAR_03_0
+#define GPIO173_FIRST_REG 0x15080 // GPIO_J_ENABLE_CONFIG_04_0
+#define GPIO173_LAST_REG 0x15094 // GPIO_J_INTERRUPT_CLEAR_04_0
+#define GPIO174_FIRST_REG 0x150a0 // GPIO_J_ENABLE_CONFIG_05_0
+#define GPIO174_LAST_REG 0x150b4 // GPIO_J_INTERRUPT_CLEAR_05_0
+#define GPIO175_FIRST_REG 0x15100 // GPIO_J_INTERRUPT_STATUS_G0_0
+#define GPIO175_LAST_REG 0x1511c // GPIO_J_INTERRUPT_STATUS_G7_0
+#define GPIO176_FIRST_REG 0x15200 // GPIO_C_ENABLE_CONFIG_00_0
+#define GPIO176_LAST_REG 0x15214 // GPIO_C_INTERRUPT_CLEAR_00_0
+#define GPIO177_FIRST_REG 0x15220 // GPIO_C_ENABLE_CONFIG_01_0
+#define GPIO177_LAST_REG 0x15234 // GPIO_C_INTERRUPT_CLEAR_01_0
+#define GPIO178_FIRST_REG 0x15240 // GPIO_C_ENABLE_CONFIG_02_0
+#define GPIO178_LAST_REG 0x15254 // GPIO_C_INTERRUPT_CLEAR_02_0
+#define GPIO179_FIRST_REG 0x15260 // GPIO_C_ENABLE_CONFIG_03_0
+#define GPIO179_LAST_REG 0x15274 // GPIO_C_INTERRUPT_CLEAR_03_0
+#define GPIO180_FIRST_REG 0x15280 // GPIO_C_ENABLE_CONFIG_04_0
+#define GPIO180_LAST_REG 0x15294 // GPIO_C_INTERRUPT_CLEAR_04_0
+#define GPIO181_FIRST_REG 0x152a0 // GPIO_C_ENABLE_CONFIG_05_0
+#define GPIO181_LAST_REG 0x152b4 // GPIO_C_INTERRUPT_CLEAR_05_0
+#define GPIO182_FIRST_REG 0x152c0 // GPIO_C_ENABLE_CONFIG_06_0
+#define GPIO182_LAST_REG 0x152d4 // GPIO_C_INTERRUPT_CLEAR_06_0
+#define GPIO183_FIRST_REG 0x152e0 // GPIO_C_ENABLE_CONFIG_07_0
+#define GPIO183_LAST_REG 0x152f4 // GPIO_C_INTERRUPT_CLEAR_07_0
+#define GPIO184_FIRST_REG 0x15300 // GPIO_C_INTERRUPT_STATUS_G0_0
+#define GPIO184_LAST_REG 0x1531c // GPIO_C_INTERRUPT_STATUS_G7_0
+#define GPIO185_FIRST_REG 0x15400 // GPIO_D_ENABLE_CONFIG_00_0
+#define GPIO185_LAST_REG 0x15414 // GPIO_D_INTERRUPT_CLEAR_00_0
+#define GPIO186_FIRST_REG 0x15420 // GPIO_D_ENABLE_CONFIG_01_0
+#define GPIO186_LAST_REG 0x15434 // GPIO_D_INTERRUPT_CLEAR_01_0
+#define GPIO187_FIRST_REG 0x15440 // GPIO_D_ENABLE_CONFIG_02_0
+#define GPIO187_LAST_REG 0x15454 // GPIO_D_INTERRUPT_CLEAR_02_0
+#define GPIO188_FIRST_REG 0x15460 // GPIO_D_ENABLE_CONFIG_03_0
+#define GPIO188_LAST_REG 0x15474 // GPIO_D_INTERRUPT_CLEAR_03_0
+#define GPIO189_FIRST_REG 0x15500 // GPIO_D_INTERRUPT_STATUS_G0_0
+#define GPIO189_LAST_REG 0x1551c // GPIO_D_INTERRUPT_STATUS_G7_0
+#define GPIO190_FIRST_REG 0x15600 // GPIO_E_ENABLE_CONFIG_00_0
+#define GPIO190_LAST_REG 0x15614 // GPIO_E_INTERRUPT_CLEAR_00_0
+#define GPIO191_FIRST_REG 0x15620 // GPIO_E_ENABLE_CONFIG_01_0
+#define GPIO191_LAST_REG 0x15634 // GPIO_E_INTERRUPT_CLEAR_01_0
+#define GPIO192_FIRST_REG 0x15640 // GPIO_E_ENABLE_CONFIG_02_0
+#define GPIO192_LAST_REG 0x15654 // GPIO_E_INTERRUPT_CLEAR_02_0
+#define GPIO193_FIRST_REG 0x15660 // GPIO_E_ENABLE_CONFIG_03_0
+#define GPIO193_LAST_REG 0x15674 // GPIO_E_INTERRUPT_CLEAR_03_0
+#define GPIO194_FIRST_REG 0x15680 // GPIO_E_ENABLE_CONFIG_04_0
+#define GPIO194_LAST_REG 0x15694 // GPIO_E_INTERRUPT_CLEAR_04_0
+#define GPIO195_FIRST_REG 0x156a0 // GPIO_E_ENABLE_CONFIG_05_0
+#define GPIO195_LAST_REG 0x156b4 // GPIO_E_INTERRUPT_CLEAR_05_0
+#define GPIO196_FIRST_REG 0x156c0 // GPIO_E_ENABLE_CONFIG_06_0
+#define GPIO196_LAST_REG 0x156d4 // GPIO_E_INTERRUPT_CLEAR_06_0
+#define GPIO197_FIRST_REG 0x156e0 // GPIO_E_ENABLE_CONFIG_07_0
+#define GPIO197_LAST_REG 0x156f4 // GPIO_E_INTERRUPT_CLEAR_07_0
+#define GPIO198_FIRST_REG 0x15700 // GPIO_E_INTERRUPT_STATUS_G0_0
+#define GPIO198_LAST_REG 0x1571c // GPIO_E_INTERRUPT_STATUS_G7_0
+#define GPIO199_FIRST_REG 0x15800 // GPIO_F_ENABLE_CONFIG_00_0
+#define GPIO199_LAST_REG 0x15814 // GPIO_F_INTERRUPT_CLEAR_00_0
+#define GPIO200_FIRST_REG 0x15820 // GPIO_F_ENABLE_CONFIG_01_0
+#define GPIO200_LAST_REG 0x15834 // GPIO_F_INTERRUPT_CLEAR_01_0
+#define GPIO201_FIRST_REG 0x15840 // GPIO_F_ENABLE_CONFIG_02_0
+#define GPIO201_LAST_REG 0x15854 // GPIO_F_INTERRUPT_CLEAR_02_0
+#define GPIO202_FIRST_REG 0x15860 // GPIO_F_ENABLE_CONFIG_03_0
+#define GPIO202_LAST_REG 0x15874 // GPIO_F_INTERRUPT_CLEAR_03_0
+#define GPIO203_FIRST_REG 0x15880 // GPIO_F_ENABLE_CONFIG_04_0
+#define GPIO203_LAST_REG 0x15894 // GPIO_F_INTERRUPT_CLEAR_04_0
+#define GPIO204_FIRST_REG 0x158a0 // GPIO_F_ENABLE_CONFIG_05_0
+#define GPIO204_LAST_REG 0x158b4 // GPIO_F_INTERRUPT_CLEAR_05_0
+#define GPIO205_FIRST_REG 0x15900 // GPIO_F_INTERRUPT_STATUS_G0_0
+#define GPIO205_LAST_REG 0x1591c // GPIO_F_INTERRUPT_STATUS_G7_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARGPIO_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argte_aps.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argte_aps.h
new file mode 100644
index 0000000..a1c8f49
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/argte_aps.h
@@ -0,0 +1,633 @@
+//
+// Copyright (c) 2021-2022 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARGTE_APS_H_INC
+#define ARGTE_APS_H_INC
+#define NV_MOBILE_ARGTE_APS_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARGTE_APS_H_SCRREG_NOMENCLATURE EXACT
+
+
+// Register GTE_APS_TECTRL_0
+#define GTE_APS_TECTRL_0                        MK_ADDR_CONST(0x0)
+#define GTE_APS_TECTRL_0_SECURE                         0x0
+#define GTE_APS_TECTRL_0_DUAL                   0x0
+#define GTE_APS_TECTRL_0_SCR                    TESCR_0
+#define GTE_APS_TECTRL_0_SCRREG                         GTE_APS_SCR_TESCR_0
+#define GTE_APS_TECTRL_0_WORD_COUNT                     0x1
+#define GTE_APS_TECTRL_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_RESET_MASK                     MK_MASK_CONST(0xff37)
+#define GTE_APS_TECTRL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_READ_MASK                      MK_MASK_CONST(0xff37)
+#define GTE_APS_TECTRL_0_WRITE_MASK                     MK_MASK_CONST(0xff37)
+#define GTE_APS_TECTRL_0_ENABLE_SHIFT                   MK_SHIFT_CONST(0)
+#define GTE_APS_TECTRL_0_ENABLE_FIELD                   MK_FIELD_CONST(0x1, GTE_APS_TECTRL_0_ENABLE_SHIFT)
+#define GTE_APS_TECTRL_0_ENABLE_RANGE                   0:0
+#define GTE_APS_TECTRL_0_ENABLE_MSB                     MK_SHIFT_CONST(0)
+#define GTE_APS_TECTRL_0_ENABLE_LSB                     MK_SHIFT_CONST(0)
+#define GTE_APS_TECTRL_0_ENABLE_WOFFSET                 0x0
+#define GTE_APS_TECTRL_0_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define GTE_APS_TECTRL_0_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define GTE_APS_TECTRL_0_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define GTE_APS_TECTRL_0_ENABLE_DISABLE                 MK_ENUM_CONST(0)
+#define GTE_APS_TECTRL_0_ENABLE_ENABLE                  MK_ENUM_CONST(1)
+
+#define GTE_APS_TECTRL_0_INTERRUPTENABLE_SHIFT                  MK_SHIFT_CONST(1)
+#define GTE_APS_TECTRL_0_INTERRUPTENABLE_FIELD                  MK_FIELD_CONST(0x1, GTE_APS_TECTRL_0_INTERRUPTENABLE_SHIFT)
+#define GTE_APS_TECTRL_0_INTERRUPTENABLE_RANGE                  1:1
+#define GTE_APS_TECTRL_0_INTERRUPTENABLE_MSB                    MK_SHIFT_CONST(1)
+#define GTE_APS_TECTRL_0_INTERRUPTENABLE_LSB                    MK_SHIFT_CONST(1)
+#define GTE_APS_TECTRL_0_INTERRUPTENABLE_WOFFSET                        0x0
+#define GTE_APS_TECTRL_0_INTERRUPTENABLE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_INTERRUPTENABLE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GTE_APS_TECTRL_0_INTERRUPTENABLE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_INTERRUPTENABLE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_INTERRUPTENABLE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GTE_APS_TECTRL_0_INTERRUPTENABLE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GTE_APS_TECTRL_0_INTERRUPTENABLE_DISABLE                        MK_ENUM_CONST(0)
+#define GTE_APS_TECTRL_0_INTERRUPTENABLE_ENABLE                 MK_ENUM_CONST(1)
+
+#define GTE_APS_TECTRL_0_AUTOADVENABLE_SHIFT                    MK_SHIFT_CONST(2)
+#define GTE_APS_TECTRL_0_AUTOADVENABLE_FIELD                    MK_FIELD_CONST(0x1, GTE_APS_TECTRL_0_AUTOADVENABLE_SHIFT)
+#define GTE_APS_TECTRL_0_AUTOADVENABLE_RANGE                    2:2
+#define GTE_APS_TECTRL_0_AUTOADVENABLE_MSB                      MK_SHIFT_CONST(2)
+#define GTE_APS_TECTRL_0_AUTOADVENABLE_LSB                      MK_SHIFT_CONST(2)
+#define GTE_APS_TECTRL_0_AUTOADVENABLE_WOFFSET                  0x0
+#define GTE_APS_TECTRL_0_AUTOADVENABLE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_AUTOADVENABLE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define GTE_APS_TECTRL_0_AUTOADVENABLE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_AUTOADVENABLE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_AUTOADVENABLE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define GTE_APS_TECTRL_0_AUTOADVENABLE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define GTE_APS_TECTRL_0_AUTOADVENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define GTE_APS_TECTRL_0_AUTOADVENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define GTE_APS_TECTRL_0_AUTOADVADDR_SHIFT                      MK_SHIFT_CONST(4)
+#define GTE_APS_TECTRL_0_AUTOADVADDR_FIELD                      MK_FIELD_CONST(0x3, GTE_APS_TECTRL_0_AUTOADVADDR_SHIFT)
+#define GTE_APS_TECTRL_0_AUTOADVADDR_RANGE                      5:4
+#define GTE_APS_TECTRL_0_AUTOADVADDR_MSB                        MK_SHIFT_CONST(5)
+#define GTE_APS_TECTRL_0_AUTOADVADDR_LSB                        MK_SHIFT_CONST(4)
+#define GTE_APS_TECTRL_0_AUTOADVADDR_WOFFSET                    0x0
+#define GTE_APS_TECTRL_0_AUTOADVADDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_AUTOADVADDR_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define GTE_APS_TECTRL_0_AUTOADVADDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_AUTOADVADDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_AUTOADVADDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define GTE_APS_TECTRL_0_AUTOADVADDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GTE_APS_TECTRL_0_OCCUPANCYTHRESHOLD_SHIFT                       MK_SHIFT_CONST(8)
+#define GTE_APS_TECTRL_0_OCCUPANCYTHRESHOLD_FIELD                       MK_FIELD_CONST(0xff, GTE_APS_TECTRL_0_OCCUPANCYTHRESHOLD_SHIFT)
+#define GTE_APS_TECTRL_0_OCCUPANCYTHRESHOLD_RANGE                       15:8
+#define GTE_APS_TECTRL_0_OCCUPANCYTHRESHOLD_MSB                 MK_SHIFT_CONST(15)
+#define GTE_APS_TECTRL_0_OCCUPANCYTHRESHOLD_LSB                 MK_SHIFT_CONST(8)
+#define GTE_APS_TECTRL_0_OCCUPANCYTHRESHOLD_WOFFSET                     0x0
+#define GTE_APS_TECTRL_0_OCCUPANCYTHRESHOLD_DEFAULT                     MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_OCCUPANCYTHRESHOLD_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define GTE_APS_TECTRL_0_OCCUPANCYTHRESHOLD_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_OCCUPANCYTHRESHOLD_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GTE_APS_TECTRL_0_OCCUPANCYTHRESHOLD_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GTE_APS_TECTRL_0_OCCUPANCYTHRESHOLD_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GTE_APS_TETSCH_0
+#define GTE_APS_TETSCH_0                        MK_ADDR_CONST(0x4)
+#define GTE_APS_TETSCH_0_SECURE                         0x0
+#define GTE_APS_TETSCH_0_DUAL                   0x0
+#define GTE_APS_TETSCH_0_SCR                    TESCR_0
+#define GTE_APS_TETSCH_0_SCRREG                         GTE_APS_SCR_TESCR_0
+#define GTE_APS_TETSCH_0_WORD_COUNT                     0x1
+#define GTE_APS_TETSCH_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GTE_APS_TETSCH_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
+#define GTE_APS_TETSCH_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GTE_APS_TETSCH_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GTE_APS_TETSCH_0_READ_MASK                      MK_MASK_CONST(0xffffff)
+#define GTE_APS_TETSCH_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define GTE_APS_TETSCH_0_VAL_SHIFT                      MK_SHIFT_CONST(0)
+#define GTE_APS_TETSCH_0_VAL_FIELD                      MK_FIELD_CONST(0xffffff, GTE_APS_TETSCH_0_VAL_SHIFT)
+#define GTE_APS_TETSCH_0_VAL_RANGE                      23:0
+#define GTE_APS_TETSCH_0_VAL_MSB                        MK_SHIFT_CONST(23)
+#define GTE_APS_TETSCH_0_VAL_LSB                        MK_SHIFT_CONST(0)
+#define GTE_APS_TETSCH_0_VAL_WOFFSET                    0x0
+#define GTE_APS_TETSCH_0_VAL_DEFAULT                    MK_MASK_CONST(0x0)
+#define GTE_APS_TETSCH_0_VAL_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
+#define GTE_APS_TETSCH_0_VAL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GTE_APS_TETSCH_0_VAL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GTE_APS_TETSCH_0_VAL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GTE_APS_TETSCH_0_VAL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GTE_APS_TETSCL_0
+#define GTE_APS_TETSCL_0                        MK_ADDR_CONST(0x8)
+#define GTE_APS_TETSCL_0_SECURE                         0x0
+#define GTE_APS_TETSCL_0_DUAL                   0x0
+#define GTE_APS_TETSCL_0_SCR                    TESCR_0
+#define GTE_APS_TETSCL_0_SCRREG                         GTE_APS_SCR_TESCR_0
+#define GTE_APS_TETSCL_0_WORD_COUNT                     0x1
+#define GTE_APS_TETSCL_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GTE_APS_TETSCL_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define GTE_APS_TETSCL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GTE_APS_TETSCL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GTE_APS_TETSCL_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define GTE_APS_TETSCL_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define GTE_APS_TETSCL_0_VAL_SHIFT                      MK_SHIFT_CONST(0)
+#define GTE_APS_TETSCL_0_VAL_FIELD                      MK_FIELD_CONST(0xffffffff, GTE_APS_TETSCL_0_VAL_SHIFT)
+#define GTE_APS_TETSCL_0_VAL_RANGE                      31:0
+#define GTE_APS_TETSCL_0_VAL_MSB                        MK_SHIFT_CONST(31)
+#define GTE_APS_TETSCL_0_VAL_LSB                        MK_SHIFT_CONST(0)
+#define GTE_APS_TETSCL_0_VAL_WOFFSET                    0x0
+#define GTE_APS_TETSCL_0_VAL_DEFAULT                    MK_MASK_CONST(0x0)
+#define GTE_APS_TETSCL_0_VAL_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define GTE_APS_TETSCL_0_VAL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GTE_APS_TETSCL_0_VAL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GTE_APS_TETSCL_0_VAL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GTE_APS_TETSCL_0_VAL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GTE_APS_TESRC_0
+#define GTE_APS_TESRC_0                 MK_ADDR_CONST(0xc)
+#define GTE_APS_TESRC_0_SECURE                  0x0
+#define GTE_APS_TESRC_0_DUAL                    0x0
+#define GTE_APS_TESRC_0_SCR                     TESCR_0
+#define GTE_APS_TESRC_0_SCRREG                  GTE_APS_SCR_TESCR_0
+#define GTE_APS_TESRC_0_WORD_COUNT                      0x1
+#define GTE_APS_TESRC_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GTE_APS_TESRC_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GTE_APS_TESRC_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GTE_APS_TESRC_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GTE_APS_TESRC_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GTE_APS_TESRC_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define GTE_APS_TESRC_0_TAG_SHIFT                       MK_SHIFT_CONST(0)
+#define GTE_APS_TESRC_0_TAG_FIELD                       MK_FIELD_CONST(0xffff, GTE_APS_TESRC_0_TAG_SHIFT)
+#define GTE_APS_TESRC_0_TAG_RANGE                       15:0
+#define GTE_APS_TESRC_0_TAG_MSB                 MK_SHIFT_CONST(15)
+#define GTE_APS_TESRC_0_TAG_LSB                 MK_SHIFT_CONST(0)
+#define GTE_APS_TESRC_0_TAG_WOFFSET                     0x0
+#define GTE_APS_TESRC_0_TAG_DEFAULT                     MK_MASK_CONST(0x0)
+#define GTE_APS_TESRC_0_TAG_DEFAULT_MASK                        MK_MASK_CONST(0xffff)
+#define GTE_APS_TESRC_0_TAG_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GTE_APS_TESRC_0_TAG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GTE_APS_TESRC_0_TAG_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GTE_APS_TESRC_0_TAG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define GTE_APS_TESRC_0_SLICE_SHIFT                     MK_SHIFT_CONST(16)
+#define GTE_APS_TESRC_0_SLICE_FIELD                     MK_FIELD_CONST(0xff, GTE_APS_TESRC_0_SLICE_SHIFT)
+#define GTE_APS_TESRC_0_SLICE_RANGE                     23:16
+#define GTE_APS_TESRC_0_SLICE_MSB                       MK_SHIFT_CONST(23)
+#define GTE_APS_TESRC_0_SLICE_LSB                       MK_SHIFT_CONST(16)
+#define GTE_APS_TESRC_0_SLICE_WOFFSET                   0x0
+#define GTE_APS_TESRC_0_SLICE_DEFAULT                   MK_MASK_CONST(0x0)
+#define GTE_APS_TESRC_0_SLICE_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define GTE_APS_TESRC_0_SLICE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define GTE_APS_TESRC_0_SLICE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define GTE_APS_TESRC_0_SLICE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define GTE_APS_TESRC_0_SLICE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define GTE_APS_TESRC_0_MODULE_SHIFT                    MK_SHIFT_CONST(24)
+#define GTE_APS_TESRC_0_MODULE_FIELD                    MK_FIELD_CONST(0xff, GTE_APS_TESRC_0_MODULE_SHIFT)
+#define GTE_APS_TESRC_0_MODULE_RANGE                    31:24
+#define GTE_APS_TESRC_0_MODULE_MSB                      MK_SHIFT_CONST(31)
+#define GTE_APS_TESRC_0_MODULE_LSB                      MK_SHIFT_CONST(24)
+#define GTE_APS_TESRC_0_MODULE_WOFFSET                  0x0
+#define GTE_APS_TESRC_0_MODULE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GTE_APS_TESRC_0_MODULE_DEFAULT_MASK                     MK_MASK_CONST(0xff)
+#define GTE_APS_TESRC_0_MODULE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GTE_APS_TESRC_0_MODULE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GTE_APS_TESRC_0_MODULE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GTE_APS_TESRC_0_MODULE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register GTE_APS_TECCV_0
+#define GTE_APS_TECCV_0                 MK_ADDR_CONST(0x10)
+#define GTE_APS_TECCV_0_SECURE                  0x0
+#define GTE_APS_TECCV_0_DUAL                    0x0
+#define GTE_APS_TECCV_0_SCR                     TESCR_0
+#define GTE_APS_TECCV_0_SCRREG                  GTE_APS_SCR_TESCR_0
+#define GTE_APS_TECCV_0_WORD_COUNT                      0x1
+#define GTE_APS_TECCV_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GTE_APS_TECCV_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GTE_APS_TECCV_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GTE_APS_TECCV_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GTE_APS_TECCV_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GTE_APS_TECCV_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define GTE_APS_TECCV_0_VAL_SHIFT                       MK_SHIFT_CONST(0)
+#define GTE_APS_TECCV_0_VAL_FIELD                       MK_FIELD_CONST(0xffffffff, GTE_APS_TECCV_0_VAL_SHIFT)
+#define GTE_APS_TECCV_0_VAL_RANGE                       31:0
+#define GTE_APS_TECCV_0_VAL_MSB                 MK_SHIFT_CONST(31)
+#define GTE_APS_TECCV_0_VAL_LSB                 MK_SHIFT_CONST(0)
+#define GTE_APS_TECCV_0_VAL_WOFFSET                     0x0
+#define GTE_APS_TECCV_0_VAL_DEFAULT                     MK_MASK_CONST(0x0)
+#define GTE_APS_TECCV_0_VAL_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GTE_APS_TECCV_0_VAL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GTE_APS_TECCV_0_VAL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GTE_APS_TECCV_0_VAL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GTE_APS_TECCV_0_VAL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GTE_APS_TEPCV_0
+#define GTE_APS_TEPCV_0                 MK_ADDR_CONST(0x14)
+#define GTE_APS_TEPCV_0_SECURE                  0x0
+#define GTE_APS_TEPCV_0_DUAL                    0x0
+#define GTE_APS_TEPCV_0_SCR                     TESCR_0
+#define GTE_APS_TEPCV_0_SCRREG                  GTE_APS_SCR_TESCR_0
+#define GTE_APS_TEPCV_0_WORD_COUNT                      0x1
+#define GTE_APS_TEPCV_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GTE_APS_TEPCV_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GTE_APS_TEPCV_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GTE_APS_TEPCV_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GTE_APS_TEPCV_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GTE_APS_TEPCV_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define GTE_APS_TEPCV_0_VAL_SHIFT                       MK_SHIFT_CONST(0)
+#define GTE_APS_TEPCV_0_VAL_FIELD                       MK_FIELD_CONST(0xffffffff, GTE_APS_TEPCV_0_VAL_SHIFT)
+#define GTE_APS_TEPCV_0_VAL_RANGE                       31:0
+#define GTE_APS_TEPCV_0_VAL_MSB                 MK_SHIFT_CONST(31)
+#define GTE_APS_TEPCV_0_VAL_LSB                 MK_SHIFT_CONST(0)
+#define GTE_APS_TEPCV_0_VAL_WOFFSET                     0x0
+#define GTE_APS_TEPCV_0_VAL_DEFAULT                     MK_MASK_CONST(0x0)
+#define GTE_APS_TEPCV_0_VAL_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GTE_APS_TEPCV_0_VAL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GTE_APS_TEPCV_0_VAL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GTE_APS_TEPCV_0_VAL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define GTE_APS_TEPCV_0_VAL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GTE_APS_TEENCV_0
+#define GTE_APS_TEENCV_0                        MK_ADDR_CONST(0x18)
+#define GTE_APS_TEENCV_0_SECURE                         0x0
+#define GTE_APS_TEENCV_0_DUAL                   0x0
+#define GTE_APS_TEENCV_0_SCR                    TESCR_0
+#define GTE_APS_TEENCV_0_SCRREG                         GTE_APS_SCR_TESCR_0
+#define GTE_APS_TEENCV_0_WORD_COUNT                     0x1
+#define GTE_APS_TEENCV_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_RESET_MASK                     MK_MASK_CONST(0x80011fff)
+#define GTE_APS_TEENCV_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_READ_MASK                      MK_MASK_CONST(0x80011fff)
+#define GTE_APS_TEENCV_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_BITINDEX_SHIFT                 MK_SHIFT_CONST(0)
+#define GTE_APS_TEENCV_0_BITINDEX_FIELD                 MK_FIELD_CONST(0x1f, GTE_APS_TEENCV_0_BITINDEX_SHIFT)
+#define GTE_APS_TEENCV_0_BITINDEX_RANGE                 4:0
+#define GTE_APS_TEENCV_0_BITINDEX_MSB                   MK_SHIFT_CONST(4)
+#define GTE_APS_TEENCV_0_BITINDEX_LSB                   MK_SHIFT_CONST(0)
+#define GTE_APS_TEENCV_0_BITINDEX_WOFFSET                       0x0
+#define GTE_APS_TEENCV_0_BITINDEX_DEFAULT                       MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_BITINDEX_DEFAULT_MASK                  MK_MASK_CONST(0x1f)
+#define GTE_APS_TEENCV_0_BITINDEX_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_BITINDEX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_BITINDEX_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_BITINDEX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define GTE_APS_TEENCV_0_SLICE_SHIFT                    MK_SHIFT_CONST(5)
+#define GTE_APS_TEENCV_0_SLICE_FIELD                    MK_FIELD_CONST(0xff, GTE_APS_TEENCV_0_SLICE_SHIFT)
+#define GTE_APS_TEENCV_0_SLICE_RANGE                    12:5
+#define GTE_APS_TEENCV_0_SLICE_MSB                      MK_SHIFT_CONST(12)
+#define GTE_APS_TEENCV_0_SLICE_LSB                      MK_SHIFT_CONST(5)
+#define GTE_APS_TEENCV_0_SLICE_WOFFSET                  0x0
+#define GTE_APS_TEENCV_0_SLICE_DEFAULT                  MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_SLICE_DEFAULT_MASK                     MK_MASK_CONST(0xff)
+#define GTE_APS_TEENCV_0_SLICE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_SLICE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_SLICE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_SLICE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define GTE_APS_TEENCV_0_FALLING_SHIFT                  MK_SHIFT_CONST(16)
+#define GTE_APS_TEENCV_0_FALLING_FIELD                  MK_FIELD_CONST(0x1, GTE_APS_TEENCV_0_FALLING_SHIFT)
+#define GTE_APS_TEENCV_0_FALLING_RANGE                  16:16
+#define GTE_APS_TEENCV_0_FALLING_MSB                    MK_SHIFT_CONST(16)
+#define GTE_APS_TEENCV_0_FALLING_LSB                    MK_SHIFT_CONST(16)
+#define GTE_APS_TEENCV_0_FALLING_WOFFSET                        0x0
+#define GTE_APS_TEENCV_0_FALLING_DEFAULT                        MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_FALLING_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GTE_APS_TEENCV_0_FALLING_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_FALLING_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_FALLING_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_FALLING_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define GTE_APS_TEENCV_0_INVALID_SHIFT                  MK_SHIFT_CONST(31)
+#define GTE_APS_TEENCV_0_INVALID_FIELD                  MK_FIELD_CONST(0x1, GTE_APS_TEENCV_0_INVALID_SHIFT)
+#define GTE_APS_TEENCV_0_INVALID_RANGE                  31:31
+#define GTE_APS_TEENCV_0_INVALID_MSB                    MK_SHIFT_CONST(31)
+#define GTE_APS_TEENCV_0_INVALID_LSB                    MK_SHIFT_CONST(31)
+#define GTE_APS_TEENCV_0_INVALID_WOFFSET                        0x0
+#define GTE_APS_TEENCV_0_INVALID_DEFAULT                        MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_INVALID_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GTE_APS_TEENCV_0_INVALID_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_INVALID_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_INVALID_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define GTE_APS_TEENCV_0_INVALID_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register GTE_APS_TECMD_0
+#define GTE_APS_TECMD_0                 MK_ADDR_CONST(0x1c)
+#define GTE_APS_TECMD_0_SECURE                  0x0
+#define GTE_APS_TECMD_0_DUAL                    0x0
+#define GTE_APS_TECMD_0_SCR                     TESCR_0
+#define GTE_APS_TECMD_0_SCRREG                  GTE_APS_SCR_TESCR_0
+#define GTE_APS_TECMD_0_WORD_COUNT                      0x1
+#define GTE_APS_TECMD_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GTE_APS_TECMD_0_RESET_MASK                      MK_MASK_CONST(0xf)
+#define GTE_APS_TECMD_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GTE_APS_TECMD_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GTE_APS_TECMD_0_READ_MASK                       MK_MASK_CONST(0xf)
+#define GTE_APS_TECMD_0_WRITE_MASK                      MK_MASK_CONST(0xf)
+#define GTE_APS_TECMD_0_CMD_SHIFT                       MK_SHIFT_CONST(0)
+#define GTE_APS_TECMD_0_CMD_FIELD                       MK_FIELD_CONST(0xf, GTE_APS_TECMD_0_CMD_SHIFT)
+#define GTE_APS_TECMD_0_CMD_RANGE                       3:0
+#define GTE_APS_TECMD_0_CMD_MSB                 MK_SHIFT_CONST(3)
+#define GTE_APS_TECMD_0_CMD_LSB                 MK_SHIFT_CONST(0)
+#define GTE_APS_TECMD_0_CMD_WOFFSET                     0x0
+#define GTE_APS_TECMD_0_CMD_DEFAULT                     MK_MASK_CONST(0x0)
+#define GTE_APS_TECMD_0_CMD_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define GTE_APS_TECMD_0_CMD_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GTE_APS_TECMD_0_CMD_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GTE_APS_TECMD_0_CMD_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GTE_APS_TECMD_0_CMD_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define GTE_APS_TECMD_0_CMD_NOP                 MK_ENUM_CONST(0)
+#define GTE_APS_TECMD_0_CMD_POP                 MK_ENUM_CONST(1)
+
+
+// Register GTE_APS_TESTATUS_0
+#define GTE_APS_TESTATUS_0                      MK_ADDR_CONST(0x20)
+#define GTE_APS_TESTATUS_0_SECURE                       0x0
+#define GTE_APS_TESTATUS_0_DUAL                         0x0
+#define GTE_APS_TESTATUS_0_SCR                  TESCR_0
+#define GTE_APS_TESTATUS_0_SCRREG                       GTE_APS_SCR_TESCR_0
+#define GTE_APS_TESTATUS_0_WORD_COUNT                   0x1
+#define GTE_APS_TESTATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define GTE_APS_TESTATUS_0_RESET_MASK                   MK_MASK_CONST(0xff02)
+#define GTE_APS_TESTATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define GTE_APS_TESTATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GTE_APS_TESTATUS_0_READ_MASK                    MK_MASK_CONST(0xff02)
+#define GTE_APS_TESTATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define GTE_APS_TESTATUS_0_INTERRUPT_SHIFT                      MK_SHIFT_CONST(1)
+#define GTE_APS_TESTATUS_0_INTERRUPT_FIELD                      MK_FIELD_CONST(0x1, GTE_APS_TESTATUS_0_INTERRUPT_SHIFT)
+#define GTE_APS_TESTATUS_0_INTERRUPT_RANGE                      1:1
+#define GTE_APS_TESTATUS_0_INTERRUPT_MSB                        MK_SHIFT_CONST(1)
+#define GTE_APS_TESTATUS_0_INTERRUPT_LSB                        MK_SHIFT_CONST(1)
+#define GTE_APS_TESTATUS_0_INTERRUPT_WOFFSET                    0x0
+#define GTE_APS_TESTATUS_0_INTERRUPT_DEFAULT                    MK_MASK_CONST(0x0)
+#define GTE_APS_TESTATUS_0_INTERRUPT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define GTE_APS_TESTATUS_0_INTERRUPT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GTE_APS_TESTATUS_0_INTERRUPT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GTE_APS_TESTATUS_0_INTERRUPT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GTE_APS_TESTATUS_0_INTERRUPT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define GTE_APS_TESTATUS_0_OCCUPANCY_SHIFT                      MK_SHIFT_CONST(8)
+#define GTE_APS_TESTATUS_0_OCCUPANCY_FIELD                      MK_FIELD_CONST(0xff, GTE_APS_TESTATUS_0_OCCUPANCY_SHIFT)
+#define GTE_APS_TESTATUS_0_OCCUPANCY_RANGE                      15:8
+#define GTE_APS_TESTATUS_0_OCCUPANCY_MSB                        MK_SHIFT_CONST(15)
+#define GTE_APS_TESTATUS_0_OCCUPANCY_LSB                        MK_SHIFT_CONST(8)
+#define GTE_APS_TESTATUS_0_OCCUPANCY_WOFFSET                    0x0
+#define GTE_APS_TESTATUS_0_OCCUPANCY_DEFAULT                    MK_MASK_CONST(0x0)
+#define GTE_APS_TESTATUS_0_OCCUPANCY_DEFAULT_MASK                       MK_MASK_CONST(0xff)
+#define GTE_APS_TESTATUS_0_OCCUPANCY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define GTE_APS_TESTATUS_0_OCCUPANCY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GTE_APS_TESTATUS_0_OCCUPANCY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define GTE_APS_TESTATUS_0_OCCUPANCY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register GTE_APS_CLK_OVR_ON_0
+#define GTE_APS_CLK_OVR_ON_0                    MK_ADDR_CONST(0x24)
+#define GTE_APS_CLK_OVR_ON_0_SECURE                     0x0
+#define GTE_APS_CLK_OVR_ON_0_DUAL                       0x0
+#define GTE_APS_CLK_OVR_ON_0_SCR                        TESCR_0
+#define GTE_APS_CLK_OVR_ON_0_SCRREG                     GTE_APS_SCR_TESCR_0
+#define GTE_APS_CLK_OVR_ON_0_WORD_COUNT                         0x1
+#define GTE_APS_CLK_OVR_ON_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define GTE_APS_CLK_OVR_ON_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define GTE_APS_CLK_OVR_ON_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define GTE_APS_CLK_OVR_ON_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define GTE_APS_CLK_OVR_ON_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define GTE_APS_CLK_OVR_ON_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define GTE_APS_CLK_OVR_ON_0_GTE_SHIFT                  MK_SHIFT_CONST(0)
+#define GTE_APS_CLK_OVR_ON_0_GTE_FIELD                  MK_FIELD_CONST(0x1, GTE_APS_CLK_OVR_ON_0_GTE_SHIFT)
+#define GTE_APS_CLK_OVR_ON_0_GTE_RANGE                  0:0
+#define GTE_APS_CLK_OVR_ON_0_GTE_MSB                    MK_SHIFT_CONST(0)
+#define GTE_APS_CLK_OVR_ON_0_GTE_LSB                    MK_SHIFT_CONST(0)
+#define GTE_APS_CLK_OVR_ON_0_GTE_WOFFSET                        0x0
+#define GTE_APS_CLK_OVR_ON_0_GTE_DEFAULT                        MK_MASK_CONST(0x0)
+#define GTE_APS_CLK_OVR_ON_0_GTE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define GTE_APS_CLK_OVR_ON_0_GTE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define GTE_APS_CLK_OVR_ON_0_GTE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define GTE_APS_CLK_OVR_ON_0_GTE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define GTE_APS_CLK_OVR_ON_0_GTE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define GTE_APS_CLK_OVR_ON_0_GTE_DISABLE                        MK_ENUM_CONST(0)
+#define GTE_APS_CLK_OVR_ON_0_GTE_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register GTE_APS_SLICE0_TETEN_0
+#define GTE_APS_SLICE0_TETEN_0                  MK_ADDR_CONST(0x40)
+#define GTE_APS_SLICE0_TETEN_0_SECURE                   0x0
+#define GTE_APS_SLICE0_TETEN_0_DUAL                     0x0
+#define GTE_APS_SLICE0_TETEN_0_SCR                      TESCR_0
+#define GTE_APS_SLICE0_TETEN_0_SCRREG                   GTE_APS_SCR_TESCR_0
+#define GTE_APS_SLICE0_TETEN_0_WORD_COUNT                       0x1
+#define GTE_APS_SLICE0_TETEN_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE0_TETEN_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GTE_APS_SLICE0_TETEN_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE0_TETEN_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE0_TETEN_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GTE_APS_SLICE0_TETEN_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GTE_APS_SLICE0_TETEN_0_MAP_SHIFT                        MK_SHIFT_CONST(0)
+#define GTE_APS_SLICE0_TETEN_0_MAP_FIELD                        MK_FIELD_CONST(0xffffffff, GTE_APS_SLICE0_TETEN_0_MAP_SHIFT)
+#define GTE_APS_SLICE0_TETEN_0_MAP_RANGE                        31:0
+#define GTE_APS_SLICE0_TETEN_0_MAP_MSB                  MK_SHIFT_CONST(31)
+#define GTE_APS_SLICE0_TETEN_0_MAP_LSB                  MK_SHIFT_CONST(0)
+#define GTE_APS_SLICE0_TETEN_0_MAP_WOFFSET                      0x0
+#define GTE_APS_SLICE0_TETEN_0_MAP_DEFAULT                      MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE0_TETEN_0_MAP_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GTE_APS_SLICE0_TETEN_0_MAP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE0_TETEN_0_MAP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE0_TETEN_0_MAP_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GTE_APS_SLICE0_TETEN_0_MAP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GTE_APS_SLICE0_TETDIS_0
+#define GTE_APS_SLICE0_TETDIS_0                 MK_ADDR_CONST(0x44)
+#define GTE_APS_SLICE0_TETDIS_0_SECURE                  0x0
+#define GTE_APS_SLICE0_TETDIS_0_DUAL                    0x0
+#define GTE_APS_SLICE0_TETDIS_0_SCR                     TEDSCR_0
+#define GTE_APS_SLICE0_TETDIS_0_SCRREG                  GTE_APS_SCR_TEDSCR_0
+#define GTE_APS_SLICE0_TETDIS_0_WORD_COUNT                      0x1
+#define GTE_APS_SLICE0_TETDIS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE0_TETDIS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GTE_APS_SLICE0_TETDIS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE0_TETDIS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE0_TETDIS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GTE_APS_SLICE0_TETDIS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GTE_APS_SLICE0_TETDIS_0_MAP_SHIFT                       MK_SHIFT_CONST(0)
+#define GTE_APS_SLICE0_TETDIS_0_MAP_FIELD                       MK_FIELD_CONST(0xffffffff, GTE_APS_SLICE0_TETDIS_0_MAP_SHIFT)
+#define GTE_APS_SLICE0_TETDIS_0_MAP_RANGE                       31:0
+#define GTE_APS_SLICE0_TETDIS_0_MAP_MSB                 MK_SHIFT_CONST(31)
+#define GTE_APS_SLICE0_TETDIS_0_MAP_LSB                 MK_SHIFT_CONST(0)
+#define GTE_APS_SLICE0_TETDIS_0_MAP_WOFFSET                     0x0
+#define GTE_APS_SLICE0_TETDIS_0_MAP_DEFAULT                     MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE0_TETDIS_0_MAP_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GTE_APS_SLICE0_TETDIS_0_MAP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE0_TETDIS_0_MAP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE0_TETDIS_0_MAP_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GTE_APS_SLICE0_TETDIS_0_MAP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register GTE_APS_SLICE1_TETEN_0
+#define GTE_APS_SLICE1_TETEN_0                  MK_ADDR_CONST(0x60)
+#define GTE_APS_SLICE1_TETEN_0_SECURE                   0x0
+#define GTE_APS_SLICE1_TETEN_0_DUAL                     0x0
+#define GTE_APS_SLICE1_TETEN_0_SCR                      TESCR_0
+#define GTE_APS_SLICE1_TETEN_0_SCRREG                   GTE_APS_SCR_TESCR_0
+#define GTE_APS_SLICE1_TETEN_0_WORD_COUNT                       0x1
+#define GTE_APS_SLICE1_TETEN_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE1_TETEN_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define GTE_APS_SLICE1_TETEN_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE1_TETEN_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE1_TETEN_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define GTE_APS_SLICE1_TETEN_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define GTE_APS_SLICE1_TETEN_0_MAP_SHIFT                        MK_SHIFT_CONST(0)
+#define GTE_APS_SLICE1_TETEN_0_MAP_FIELD                        MK_FIELD_CONST(0xffffffff, GTE_APS_SLICE1_TETEN_0_MAP_SHIFT)
+#define GTE_APS_SLICE1_TETEN_0_MAP_RANGE                        31:0
+#define GTE_APS_SLICE1_TETEN_0_MAP_MSB                  MK_SHIFT_CONST(31)
+#define GTE_APS_SLICE1_TETEN_0_MAP_LSB                  MK_SHIFT_CONST(0)
+#define GTE_APS_SLICE1_TETEN_0_MAP_WOFFSET                      0x0
+#define GTE_APS_SLICE1_TETEN_0_MAP_DEFAULT                      MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE1_TETEN_0_MAP_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define GTE_APS_SLICE1_TETEN_0_MAP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE1_TETEN_0_MAP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE1_TETEN_0_MAP_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define GTE_APS_SLICE1_TETEN_0_MAP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register GTE_APS_SLICE1_TETDIS_0
+#define GTE_APS_SLICE1_TETDIS_0                 MK_ADDR_CONST(0x64)
+#define GTE_APS_SLICE1_TETDIS_0_SECURE                  0x0
+#define GTE_APS_SLICE1_TETDIS_0_DUAL                    0x0
+#define GTE_APS_SLICE1_TETDIS_0_SCR                     TEDSCR_0
+#define GTE_APS_SLICE1_TETDIS_0_SCRREG                  GTE_APS_SCR_TEDSCR_0
+#define GTE_APS_SLICE1_TETDIS_0_WORD_COUNT                      0x1
+#define GTE_APS_SLICE1_TETDIS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE1_TETDIS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define GTE_APS_SLICE1_TETDIS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE1_TETDIS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE1_TETDIS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define GTE_APS_SLICE1_TETDIS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define GTE_APS_SLICE1_TETDIS_0_MAP_SHIFT                       MK_SHIFT_CONST(0)
+#define GTE_APS_SLICE1_TETDIS_0_MAP_FIELD                       MK_FIELD_CONST(0xffffffff, GTE_APS_SLICE1_TETDIS_0_MAP_SHIFT)
+#define GTE_APS_SLICE1_TETDIS_0_MAP_RANGE                       31:0
+#define GTE_APS_SLICE1_TETDIS_0_MAP_MSB                 MK_SHIFT_CONST(31)
+#define GTE_APS_SLICE1_TETDIS_0_MAP_LSB                 MK_SHIFT_CONST(0)
+#define GTE_APS_SLICE1_TETDIS_0_MAP_WOFFSET                     0x0
+#define GTE_APS_SLICE1_TETDIS_0_MAP_DEFAULT                     MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE1_TETDIS_0_MAP_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define GTE_APS_SLICE1_TETDIS_0_MAP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE1_TETDIS_0_MAP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define GTE_APS_SLICE1_TETDIS_0_MAP_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define GTE_APS_SLICE1_TETDIS_0_MAP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARGTE_APS_REGS(_op_) \
+_op_(GTE_APS_TECTRL_0) \
+_op_(GTE_APS_TETSCH_0) \
+_op_(GTE_APS_TETSCL_0) \
+_op_(GTE_APS_TESRC_0) \
+_op_(GTE_APS_TECCV_0) \
+_op_(GTE_APS_TEPCV_0) \
+_op_(GTE_APS_TEENCV_0) \
+_op_(GTE_APS_TECMD_0) \
+_op_(GTE_APS_TESTATUS_0) \
+_op_(GTE_APS_CLK_OVR_ON_0) \
+_op_(GTE_APS_SLICE0_TETEN_0) \
+_op_(GTE_APS_SLICE0_TETDIS_0) \
+_op_(GTE_APS_SLICE1_TETEN_0) \
+_op_(GTE_APS_SLICE1_TETDIS_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_GTE_APS    0x00000000
+#define BASE_ADDRESS_GTE_APS_SLICE0     0x00000040
+#define BASE_ADDRESS_GTE_APS_SLICE1     0x00000060
+
+//
+// ARGTE_APS REGISTER BANKS
+//
+
+#define GTE_APS0_FIRST_REG 0x0000 // GTE_APS_TECTRL_0
+#define GTE_APS0_LAST_REG 0x0024 // GTE_APS_CLK_OVR_ON_0
+#define GTE_APS_SLICE00_FIRST_REG 0x0040 // GTE_APS_SLICE0_TETEN_0
+#define GTE_APS_SLICE00_LAST_REG 0x0044 // GTE_APS_SLICE0_TETDIS_0
+#define GTE_APS_SLICE10_FIRST_REG 0x0060 // GTE_APS_SLICE1_TETEN_0
+#define GTE_APS_SLICE10_LAST_REG 0x0064 // GTE_APS_SLICE1_TETDIS_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARGTE_APS_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arhsp_dbell.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arhsp_dbell.h
new file mode 100644
index 0000000..0cc9635
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arhsp_dbell.h
@@ -0,0 +1,2973 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARHSP_DBELL_H_INC
+#define ARHSP_DBELL_H_INC
+#define NV_MOBILE_ARHSP_DBELL_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARHSP_DBELL_H_SCRREG_NOMENCLATURE EXACT
+
+
+// Register HSP_DBELL_0_TRIGGER_0
+#define HSP_DBELL_0_TRIGGER_0                   MK_ADDR_CONST(0x0)
+#define HSP_DBELL_0_TRIGGER_0_SECURE                    0x0
+#define HSP_DBELL_0_TRIGGER_0_DUAL                      0x0
+#define HSP_DBELL_0_TRIGGER_0_SCR                       0
+#define HSP_DBELL_0_TRIGGER_0_SCRREG                    0
+#define HSP_DBELL_0_TRIGGER_0_WORD_COUNT                        0x1
+#define HSP_DBELL_0_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_0_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_0_TRIGGER_0_DUMMY_SHIFT)
+#define HSP_DBELL_0_TRIGGER_0_DUMMY_RANGE                       31:0
+#define HSP_DBELL_0_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
+#define HSP_DBELL_0_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_0_TRIGGER_0_DUMMY_WOFFSET                     0x0
+#define HSP_DBELL_0_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_0_ENABLE_0
+#define HSP_DBELL_0_ENABLE_0                    MK_ADDR_CONST(0x4)
+#define HSP_DBELL_0_ENABLE_0_SECURE                     0x0
+#define HSP_DBELL_0_ENABLE_0_DUAL                       0x0
+#define HSP_DBELL_0_ENABLE_0_SCR                        DB_0_REG_0
+#define HSP_DBELL_0_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_0_REG_0
+#define HSP_DBELL_0_ENABLE_0_WORD_COUNT                         0x1
+#define HSP_DBELL_0_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_0_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_0_ENABLE_0_MAP1_SHIFT)
+#define HSP_DBELL_0_ENABLE_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_0_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_0_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_0_ENABLE_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_0_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_0_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_0_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_0_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_0_ENABLE_0_MAP0_SHIFT)
+#define HSP_DBELL_0_ENABLE_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_0_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_0_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_0_ENABLE_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_0_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_0_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_0_RAW_0
+#define HSP_DBELL_0_RAW_0                       MK_ADDR_CONST(0x8)
+#define HSP_DBELL_0_RAW_0_SECURE                        0x0
+#define HSP_DBELL_0_RAW_0_DUAL                  0x0
+#define HSP_DBELL_0_RAW_0_SCR                   DB_0_REG_0
+#define HSP_DBELL_0_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_0_REG_0
+#define HSP_DBELL_0_RAW_0_WORD_COUNT                    0x1
+#define HSP_DBELL_0_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_0_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_0_RAW_0_MAP1_SHIFT)
+#define HSP_DBELL_0_RAW_0_MAP1_RANGE                    31:16
+#define HSP_DBELL_0_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
+#define HSP_DBELL_0_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
+#define HSP_DBELL_0_RAW_0_MAP1_WOFFSET                  0x0
+#define HSP_DBELL_0_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_0_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_0_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_0_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_0_RAW_0_MAP0_SHIFT)
+#define HSP_DBELL_0_RAW_0_MAP0_RANGE                    15:0
+#define HSP_DBELL_0_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
+#define HSP_DBELL_0_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
+#define HSP_DBELL_0_RAW_0_MAP0_WOFFSET                  0x0
+#define HSP_DBELL_0_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_0_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_0_PENDING_0
+#define HSP_DBELL_0_PENDING_0                   MK_ADDR_CONST(0xc)
+#define HSP_DBELL_0_PENDING_0_SECURE                    0x0
+#define HSP_DBELL_0_PENDING_0_DUAL                      0x0
+#define HSP_DBELL_0_PENDING_0_SCR                       DB_0_REG_0
+#define HSP_DBELL_0_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_0_REG_0
+#define HSP_DBELL_0_PENDING_0_WORD_COUNT                        0x1
+#define HSP_DBELL_0_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
+#define HSP_DBELL_0_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_0_PENDING_0_MAP1_SHIFT)
+#define HSP_DBELL_0_PENDING_0_MAP1_RANGE                        31:16
+#define HSP_DBELL_0_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
+#define HSP_DBELL_0_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_0_PENDING_0_MAP1_WOFFSET                      0x0
+#define HSP_DBELL_0_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_0_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_0_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
+#define HSP_DBELL_0_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_0_PENDING_0_MAP0_SHIFT)
+#define HSP_DBELL_0_PENDING_0_MAP0_RANGE                        15:0
+#define HSP_DBELL_0_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
+#define HSP_DBELL_0_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_0_PENDING_0_MAP0_WOFFSET                      0x0
+#define HSP_DBELL_0_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_0_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x10
+
+// Reserved address 0x14
+
+// Reserved address 0x18
+
+// Reserved address 0x1c
+
+// Reserved address 0x20
+
+// Register HSP_DBELL_0_ENABLE_SLICE1_0
+#define HSP_DBELL_0_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x24)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_SECURE                      0x0
+#define HSP_DBELL_0_ENABLE_SLICE1_0_DUAL                        0x0
+#define HSP_DBELL_0_ENABLE_SLICE1_0_SCR                         DB_0_REG_0
+#define HSP_DBELL_0_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_0_REG_0
+#define HSP_DBELL_0_ENABLE_SLICE1_0_WORD_COUNT                  0x1
+#define HSP_DBELL_0_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_0_RAW_SLICE1_0
+#define HSP_DBELL_0_RAW_SLICE1_0                        MK_ADDR_CONST(0x28)
+#define HSP_DBELL_0_RAW_SLICE1_0_SECURE                         0x0
+#define HSP_DBELL_0_RAW_SLICE1_0_DUAL                   0x0
+#define HSP_DBELL_0_RAW_SLICE1_0_SCR                    DB_0_REG_0
+#define HSP_DBELL_0_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_0_REG_0
+#define HSP_DBELL_0_RAW_SLICE1_0_WORD_COUNT                     0x1
+#define HSP_DBELL_0_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_0_RAW_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_RANGE                     31:16
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_0_RAW_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_RANGE                     15:0
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_0_PENDING_SLICE1_0
+#define HSP_DBELL_0_PENDING_SLICE1_0                    MK_ADDR_CONST(0x2c)
+#define HSP_DBELL_0_PENDING_SLICE1_0_SECURE                     0x0
+#define HSP_DBELL_0_PENDING_SLICE1_0_DUAL                       0x0
+#define HSP_DBELL_0_PENDING_SLICE1_0_SCR                        DB_0_REG_0
+#define HSP_DBELL_0_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_0_REG_0
+#define HSP_DBELL_0_PENDING_SLICE1_0_WORD_COUNT                         0x1
+#define HSP_DBELL_0_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_0_PENDING_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_0_PENDING_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_0_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_1_TRIGGER_0
+#define HSP_DBELL_1_TRIGGER_0                   MK_ADDR_CONST(0x100)
+#define HSP_DBELL_1_TRIGGER_0_SECURE                    0x0
+#define HSP_DBELL_1_TRIGGER_0_DUAL                      0x0
+#define HSP_DBELL_1_TRIGGER_0_SCR                       0
+#define HSP_DBELL_1_TRIGGER_0_SCRREG                    0
+#define HSP_DBELL_1_TRIGGER_0_WORD_COUNT                        0x1
+#define HSP_DBELL_1_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_1_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_1_TRIGGER_0_DUMMY_SHIFT)
+#define HSP_DBELL_1_TRIGGER_0_DUMMY_RANGE                       31:0
+#define HSP_DBELL_1_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
+#define HSP_DBELL_1_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_1_TRIGGER_0_DUMMY_WOFFSET                     0x0
+#define HSP_DBELL_1_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_1_ENABLE_0
+#define HSP_DBELL_1_ENABLE_0                    MK_ADDR_CONST(0x104)
+#define HSP_DBELL_1_ENABLE_0_SECURE                     0x0
+#define HSP_DBELL_1_ENABLE_0_DUAL                       0x0
+#define HSP_DBELL_1_ENABLE_0_SCR                        DB_1_REG_0
+#define HSP_DBELL_1_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_1_REG_0
+#define HSP_DBELL_1_ENABLE_0_WORD_COUNT                         0x1
+#define HSP_DBELL_1_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_1_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_1_ENABLE_0_MAP1_SHIFT)
+#define HSP_DBELL_1_ENABLE_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_1_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_1_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_1_ENABLE_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_1_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_1_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_1_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_1_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_1_ENABLE_0_MAP0_SHIFT)
+#define HSP_DBELL_1_ENABLE_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_1_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_1_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_1_ENABLE_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_1_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_1_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_1_RAW_0
+#define HSP_DBELL_1_RAW_0                       MK_ADDR_CONST(0x108)
+#define HSP_DBELL_1_RAW_0_SECURE                        0x0
+#define HSP_DBELL_1_RAW_0_DUAL                  0x0
+#define HSP_DBELL_1_RAW_0_SCR                   DB_1_REG_0
+#define HSP_DBELL_1_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_1_REG_0
+#define HSP_DBELL_1_RAW_0_WORD_COUNT                    0x1
+#define HSP_DBELL_1_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_1_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_1_RAW_0_MAP1_SHIFT)
+#define HSP_DBELL_1_RAW_0_MAP1_RANGE                    31:16
+#define HSP_DBELL_1_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
+#define HSP_DBELL_1_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
+#define HSP_DBELL_1_RAW_0_MAP1_WOFFSET                  0x0
+#define HSP_DBELL_1_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_1_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_1_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_1_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_1_RAW_0_MAP0_SHIFT)
+#define HSP_DBELL_1_RAW_0_MAP0_RANGE                    15:0
+#define HSP_DBELL_1_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
+#define HSP_DBELL_1_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
+#define HSP_DBELL_1_RAW_0_MAP0_WOFFSET                  0x0
+#define HSP_DBELL_1_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_1_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_1_PENDING_0
+#define HSP_DBELL_1_PENDING_0                   MK_ADDR_CONST(0x10c)
+#define HSP_DBELL_1_PENDING_0_SECURE                    0x0
+#define HSP_DBELL_1_PENDING_0_DUAL                      0x0
+#define HSP_DBELL_1_PENDING_0_SCR                       DB_1_REG_0
+#define HSP_DBELL_1_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_1_REG_0
+#define HSP_DBELL_1_PENDING_0_WORD_COUNT                        0x1
+#define HSP_DBELL_1_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
+#define HSP_DBELL_1_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_1_PENDING_0_MAP1_SHIFT)
+#define HSP_DBELL_1_PENDING_0_MAP1_RANGE                        31:16
+#define HSP_DBELL_1_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
+#define HSP_DBELL_1_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_1_PENDING_0_MAP1_WOFFSET                      0x0
+#define HSP_DBELL_1_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_1_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_1_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
+#define HSP_DBELL_1_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_1_PENDING_0_MAP0_SHIFT)
+#define HSP_DBELL_1_PENDING_0_MAP0_RANGE                        15:0
+#define HSP_DBELL_1_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
+#define HSP_DBELL_1_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_1_PENDING_0_MAP0_WOFFSET                      0x0
+#define HSP_DBELL_1_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_1_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x110
+
+// Reserved address 0x114
+
+// Reserved address 0x118
+
+// Reserved address 0x11c
+
+// Reserved address 0x120
+
+// Register HSP_DBELL_1_ENABLE_SLICE1_0
+#define HSP_DBELL_1_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x124)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_SECURE                      0x0
+#define HSP_DBELL_1_ENABLE_SLICE1_0_DUAL                        0x0
+#define HSP_DBELL_1_ENABLE_SLICE1_0_SCR                         DB_1_REG_0
+#define HSP_DBELL_1_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_1_REG_0
+#define HSP_DBELL_1_ENABLE_SLICE1_0_WORD_COUNT                  0x1
+#define HSP_DBELL_1_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_1_RAW_SLICE1_0
+#define HSP_DBELL_1_RAW_SLICE1_0                        MK_ADDR_CONST(0x128)
+#define HSP_DBELL_1_RAW_SLICE1_0_SECURE                         0x0
+#define HSP_DBELL_1_RAW_SLICE1_0_DUAL                   0x0
+#define HSP_DBELL_1_RAW_SLICE1_0_SCR                    DB_1_REG_0
+#define HSP_DBELL_1_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_1_REG_0
+#define HSP_DBELL_1_RAW_SLICE1_0_WORD_COUNT                     0x1
+#define HSP_DBELL_1_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_1_RAW_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_RANGE                     31:16
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_1_RAW_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_RANGE                     15:0
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_1_PENDING_SLICE1_0
+#define HSP_DBELL_1_PENDING_SLICE1_0                    MK_ADDR_CONST(0x12c)
+#define HSP_DBELL_1_PENDING_SLICE1_0_SECURE                     0x0
+#define HSP_DBELL_1_PENDING_SLICE1_0_DUAL                       0x0
+#define HSP_DBELL_1_PENDING_SLICE1_0_SCR                        DB_1_REG_0
+#define HSP_DBELL_1_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_1_REG_0
+#define HSP_DBELL_1_PENDING_SLICE1_0_WORD_COUNT                         0x1
+#define HSP_DBELL_1_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_1_PENDING_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_1_PENDING_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_1_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_2_TRIGGER_0
+#define HSP_DBELL_2_TRIGGER_0                   MK_ADDR_CONST(0x200)
+#define HSP_DBELL_2_TRIGGER_0_SECURE                    0x0
+#define HSP_DBELL_2_TRIGGER_0_DUAL                      0x0
+#define HSP_DBELL_2_TRIGGER_0_SCR                       0
+#define HSP_DBELL_2_TRIGGER_0_SCRREG                    0
+#define HSP_DBELL_2_TRIGGER_0_WORD_COUNT                        0x1
+#define HSP_DBELL_2_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_2_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_2_TRIGGER_0_DUMMY_SHIFT)
+#define HSP_DBELL_2_TRIGGER_0_DUMMY_RANGE                       31:0
+#define HSP_DBELL_2_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
+#define HSP_DBELL_2_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_2_TRIGGER_0_DUMMY_WOFFSET                     0x0
+#define HSP_DBELL_2_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_2_ENABLE_0
+#define HSP_DBELL_2_ENABLE_0                    MK_ADDR_CONST(0x204)
+#define HSP_DBELL_2_ENABLE_0_SECURE                     0x0
+#define HSP_DBELL_2_ENABLE_0_DUAL                       0x0
+#define HSP_DBELL_2_ENABLE_0_SCR                        DB_2_REG_0
+#define HSP_DBELL_2_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_2_REG_0
+#define HSP_DBELL_2_ENABLE_0_WORD_COUNT                         0x1
+#define HSP_DBELL_2_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_2_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_2_ENABLE_0_MAP1_SHIFT)
+#define HSP_DBELL_2_ENABLE_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_2_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_2_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_2_ENABLE_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_2_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_2_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_2_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_2_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_2_ENABLE_0_MAP0_SHIFT)
+#define HSP_DBELL_2_ENABLE_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_2_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_2_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_2_ENABLE_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_2_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_2_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_2_RAW_0
+#define HSP_DBELL_2_RAW_0                       MK_ADDR_CONST(0x208)
+#define HSP_DBELL_2_RAW_0_SECURE                        0x0
+#define HSP_DBELL_2_RAW_0_DUAL                  0x0
+#define HSP_DBELL_2_RAW_0_SCR                   DB_2_REG_0
+#define HSP_DBELL_2_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_2_REG_0
+#define HSP_DBELL_2_RAW_0_WORD_COUNT                    0x1
+#define HSP_DBELL_2_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_2_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_2_RAW_0_MAP1_SHIFT)
+#define HSP_DBELL_2_RAW_0_MAP1_RANGE                    31:16
+#define HSP_DBELL_2_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
+#define HSP_DBELL_2_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
+#define HSP_DBELL_2_RAW_0_MAP1_WOFFSET                  0x0
+#define HSP_DBELL_2_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_2_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_2_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_2_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_2_RAW_0_MAP0_SHIFT)
+#define HSP_DBELL_2_RAW_0_MAP0_RANGE                    15:0
+#define HSP_DBELL_2_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
+#define HSP_DBELL_2_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
+#define HSP_DBELL_2_RAW_0_MAP0_WOFFSET                  0x0
+#define HSP_DBELL_2_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_2_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_2_PENDING_0
+#define HSP_DBELL_2_PENDING_0                   MK_ADDR_CONST(0x20c)
+#define HSP_DBELL_2_PENDING_0_SECURE                    0x0
+#define HSP_DBELL_2_PENDING_0_DUAL                      0x0
+#define HSP_DBELL_2_PENDING_0_SCR                       DB_2_REG_0
+#define HSP_DBELL_2_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_2_REG_0
+#define HSP_DBELL_2_PENDING_0_WORD_COUNT                        0x1
+#define HSP_DBELL_2_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
+#define HSP_DBELL_2_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_2_PENDING_0_MAP1_SHIFT)
+#define HSP_DBELL_2_PENDING_0_MAP1_RANGE                        31:16
+#define HSP_DBELL_2_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
+#define HSP_DBELL_2_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_2_PENDING_0_MAP1_WOFFSET                      0x0
+#define HSP_DBELL_2_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_2_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_2_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
+#define HSP_DBELL_2_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_2_PENDING_0_MAP0_SHIFT)
+#define HSP_DBELL_2_PENDING_0_MAP0_RANGE                        15:0
+#define HSP_DBELL_2_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
+#define HSP_DBELL_2_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_2_PENDING_0_MAP0_WOFFSET                      0x0
+#define HSP_DBELL_2_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_2_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x210
+
+// Reserved address 0x214
+
+// Reserved address 0x218
+
+// Reserved address 0x21c
+
+// Reserved address 0x220
+
+// Register HSP_DBELL_2_ENABLE_SLICE1_0
+#define HSP_DBELL_2_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x224)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_SECURE                      0x0
+#define HSP_DBELL_2_ENABLE_SLICE1_0_DUAL                        0x0
+#define HSP_DBELL_2_ENABLE_SLICE1_0_SCR                         DB_2_REG_0
+#define HSP_DBELL_2_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_2_REG_0
+#define HSP_DBELL_2_ENABLE_SLICE1_0_WORD_COUNT                  0x1
+#define HSP_DBELL_2_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_2_RAW_SLICE1_0
+#define HSP_DBELL_2_RAW_SLICE1_0                        MK_ADDR_CONST(0x228)
+#define HSP_DBELL_2_RAW_SLICE1_0_SECURE                         0x0
+#define HSP_DBELL_2_RAW_SLICE1_0_DUAL                   0x0
+#define HSP_DBELL_2_RAW_SLICE1_0_SCR                    DB_2_REG_0
+#define HSP_DBELL_2_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_2_REG_0
+#define HSP_DBELL_2_RAW_SLICE1_0_WORD_COUNT                     0x1
+#define HSP_DBELL_2_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_2_RAW_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_RANGE                     31:16
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_2_RAW_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_RANGE                     15:0
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_2_PENDING_SLICE1_0
+#define HSP_DBELL_2_PENDING_SLICE1_0                    MK_ADDR_CONST(0x22c)
+#define HSP_DBELL_2_PENDING_SLICE1_0_SECURE                     0x0
+#define HSP_DBELL_2_PENDING_SLICE1_0_DUAL                       0x0
+#define HSP_DBELL_2_PENDING_SLICE1_0_SCR                        DB_2_REG_0
+#define HSP_DBELL_2_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_2_REG_0
+#define HSP_DBELL_2_PENDING_SLICE1_0_WORD_COUNT                         0x1
+#define HSP_DBELL_2_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_2_PENDING_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_2_PENDING_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_2_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_3_TRIGGER_0
+#define HSP_DBELL_3_TRIGGER_0                   MK_ADDR_CONST(0x300)
+#define HSP_DBELL_3_TRIGGER_0_SECURE                    0x0
+#define HSP_DBELL_3_TRIGGER_0_DUAL                      0x0
+#define HSP_DBELL_3_TRIGGER_0_SCR                       0
+#define HSP_DBELL_3_TRIGGER_0_SCRREG                    0
+#define HSP_DBELL_3_TRIGGER_0_WORD_COUNT                        0x1
+#define HSP_DBELL_3_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_3_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_3_TRIGGER_0_DUMMY_SHIFT)
+#define HSP_DBELL_3_TRIGGER_0_DUMMY_RANGE                       31:0
+#define HSP_DBELL_3_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
+#define HSP_DBELL_3_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_3_TRIGGER_0_DUMMY_WOFFSET                     0x0
+#define HSP_DBELL_3_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_3_ENABLE_0
+#define HSP_DBELL_3_ENABLE_0                    MK_ADDR_CONST(0x304)
+#define HSP_DBELL_3_ENABLE_0_SECURE                     0x0
+#define HSP_DBELL_3_ENABLE_0_DUAL                       0x0
+#define HSP_DBELL_3_ENABLE_0_SCR                        DB_3_REG_0
+#define HSP_DBELL_3_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_3_REG_0
+#define HSP_DBELL_3_ENABLE_0_WORD_COUNT                         0x1
+#define HSP_DBELL_3_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_3_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_3_ENABLE_0_MAP1_SHIFT)
+#define HSP_DBELL_3_ENABLE_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_3_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_3_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_3_ENABLE_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_3_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_3_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_3_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_3_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_3_ENABLE_0_MAP0_SHIFT)
+#define HSP_DBELL_3_ENABLE_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_3_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_3_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_3_ENABLE_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_3_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_3_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_3_RAW_0
+#define HSP_DBELL_3_RAW_0                       MK_ADDR_CONST(0x308)
+#define HSP_DBELL_3_RAW_0_SECURE                        0x0
+#define HSP_DBELL_3_RAW_0_DUAL                  0x0
+#define HSP_DBELL_3_RAW_0_SCR                   DB_3_REG_0
+#define HSP_DBELL_3_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_3_REG_0
+#define HSP_DBELL_3_RAW_0_WORD_COUNT                    0x1
+#define HSP_DBELL_3_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_3_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_3_RAW_0_MAP1_SHIFT)
+#define HSP_DBELL_3_RAW_0_MAP1_RANGE                    31:16
+#define HSP_DBELL_3_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
+#define HSP_DBELL_3_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
+#define HSP_DBELL_3_RAW_0_MAP1_WOFFSET                  0x0
+#define HSP_DBELL_3_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_3_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_3_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_3_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_3_RAW_0_MAP0_SHIFT)
+#define HSP_DBELL_3_RAW_0_MAP0_RANGE                    15:0
+#define HSP_DBELL_3_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
+#define HSP_DBELL_3_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
+#define HSP_DBELL_3_RAW_0_MAP0_WOFFSET                  0x0
+#define HSP_DBELL_3_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_3_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_3_PENDING_0
+#define HSP_DBELL_3_PENDING_0                   MK_ADDR_CONST(0x30c)
+#define HSP_DBELL_3_PENDING_0_SECURE                    0x0
+#define HSP_DBELL_3_PENDING_0_DUAL                      0x0
+#define HSP_DBELL_3_PENDING_0_SCR                       DB_3_REG_0
+#define HSP_DBELL_3_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_3_REG_0
+#define HSP_DBELL_3_PENDING_0_WORD_COUNT                        0x1
+#define HSP_DBELL_3_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
+#define HSP_DBELL_3_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_3_PENDING_0_MAP1_SHIFT)
+#define HSP_DBELL_3_PENDING_0_MAP1_RANGE                        31:16
+#define HSP_DBELL_3_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
+#define HSP_DBELL_3_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_3_PENDING_0_MAP1_WOFFSET                      0x0
+#define HSP_DBELL_3_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_3_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_3_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
+#define HSP_DBELL_3_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_3_PENDING_0_MAP0_SHIFT)
+#define HSP_DBELL_3_PENDING_0_MAP0_RANGE                        15:0
+#define HSP_DBELL_3_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
+#define HSP_DBELL_3_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_3_PENDING_0_MAP0_WOFFSET                      0x0
+#define HSP_DBELL_3_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_3_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x310
+
+// Reserved address 0x314
+
+// Reserved address 0x318
+
+// Reserved address 0x31c
+
+// Reserved address 0x320
+
+// Register HSP_DBELL_3_ENABLE_SLICE1_0
+#define HSP_DBELL_3_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x324)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_SECURE                      0x0
+#define HSP_DBELL_3_ENABLE_SLICE1_0_DUAL                        0x0
+#define HSP_DBELL_3_ENABLE_SLICE1_0_SCR                         DB_3_REG_0
+#define HSP_DBELL_3_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_3_REG_0
+#define HSP_DBELL_3_ENABLE_SLICE1_0_WORD_COUNT                  0x1
+#define HSP_DBELL_3_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_3_RAW_SLICE1_0
+#define HSP_DBELL_3_RAW_SLICE1_0                        MK_ADDR_CONST(0x328)
+#define HSP_DBELL_3_RAW_SLICE1_0_SECURE                         0x0
+#define HSP_DBELL_3_RAW_SLICE1_0_DUAL                   0x0
+#define HSP_DBELL_3_RAW_SLICE1_0_SCR                    DB_3_REG_0
+#define HSP_DBELL_3_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_3_REG_0
+#define HSP_DBELL_3_RAW_SLICE1_0_WORD_COUNT                     0x1
+#define HSP_DBELL_3_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_3_RAW_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_RANGE                     31:16
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_3_RAW_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_RANGE                     15:0
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_3_PENDING_SLICE1_0
+#define HSP_DBELL_3_PENDING_SLICE1_0                    MK_ADDR_CONST(0x32c)
+#define HSP_DBELL_3_PENDING_SLICE1_0_SECURE                     0x0
+#define HSP_DBELL_3_PENDING_SLICE1_0_DUAL                       0x0
+#define HSP_DBELL_3_PENDING_SLICE1_0_SCR                        DB_3_REG_0
+#define HSP_DBELL_3_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_3_REG_0
+#define HSP_DBELL_3_PENDING_SLICE1_0_WORD_COUNT                         0x1
+#define HSP_DBELL_3_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_3_PENDING_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_3_PENDING_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_3_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_4_TRIGGER_0
+#define HSP_DBELL_4_TRIGGER_0                   MK_ADDR_CONST(0x400)
+#define HSP_DBELL_4_TRIGGER_0_SECURE                    0x0
+#define HSP_DBELL_4_TRIGGER_0_DUAL                      0x0
+#define HSP_DBELL_4_TRIGGER_0_SCR                       0
+#define HSP_DBELL_4_TRIGGER_0_SCRREG                    0
+#define HSP_DBELL_4_TRIGGER_0_WORD_COUNT                        0x1
+#define HSP_DBELL_4_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_4_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_4_TRIGGER_0_DUMMY_SHIFT)
+#define HSP_DBELL_4_TRIGGER_0_DUMMY_RANGE                       31:0
+#define HSP_DBELL_4_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
+#define HSP_DBELL_4_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_4_TRIGGER_0_DUMMY_WOFFSET                     0x0
+#define HSP_DBELL_4_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_4_ENABLE_0
+#define HSP_DBELL_4_ENABLE_0                    MK_ADDR_CONST(0x404)
+#define HSP_DBELL_4_ENABLE_0_SECURE                     0x0
+#define HSP_DBELL_4_ENABLE_0_DUAL                       0x0
+#define HSP_DBELL_4_ENABLE_0_SCR                        DB_4_REG_0
+#define HSP_DBELL_4_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_4_REG_0
+#define HSP_DBELL_4_ENABLE_0_WORD_COUNT                         0x1
+#define HSP_DBELL_4_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_4_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_4_ENABLE_0_MAP1_SHIFT)
+#define HSP_DBELL_4_ENABLE_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_4_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_4_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_4_ENABLE_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_4_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_4_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_4_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_4_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_4_ENABLE_0_MAP0_SHIFT)
+#define HSP_DBELL_4_ENABLE_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_4_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_4_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_4_ENABLE_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_4_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_4_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_4_RAW_0
+#define HSP_DBELL_4_RAW_0                       MK_ADDR_CONST(0x408)
+#define HSP_DBELL_4_RAW_0_SECURE                        0x0
+#define HSP_DBELL_4_RAW_0_DUAL                  0x0
+#define HSP_DBELL_4_RAW_0_SCR                   DB_4_REG_0
+#define HSP_DBELL_4_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_4_REG_0
+#define HSP_DBELL_4_RAW_0_WORD_COUNT                    0x1
+#define HSP_DBELL_4_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_4_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_4_RAW_0_MAP1_SHIFT)
+#define HSP_DBELL_4_RAW_0_MAP1_RANGE                    31:16
+#define HSP_DBELL_4_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
+#define HSP_DBELL_4_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
+#define HSP_DBELL_4_RAW_0_MAP1_WOFFSET                  0x0
+#define HSP_DBELL_4_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_4_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_4_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_4_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_4_RAW_0_MAP0_SHIFT)
+#define HSP_DBELL_4_RAW_0_MAP0_RANGE                    15:0
+#define HSP_DBELL_4_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
+#define HSP_DBELL_4_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
+#define HSP_DBELL_4_RAW_0_MAP0_WOFFSET                  0x0
+#define HSP_DBELL_4_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_4_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_4_PENDING_0
+#define HSP_DBELL_4_PENDING_0                   MK_ADDR_CONST(0x40c)
+#define HSP_DBELL_4_PENDING_0_SECURE                    0x0
+#define HSP_DBELL_4_PENDING_0_DUAL                      0x0
+#define HSP_DBELL_4_PENDING_0_SCR                       DB_4_REG_0
+#define HSP_DBELL_4_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_4_REG_0
+#define HSP_DBELL_4_PENDING_0_WORD_COUNT                        0x1
+#define HSP_DBELL_4_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
+#define HSP_DBELL_4_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_4_PENDING_0_MAP1_SHIFT)
+#define HSP_DBELL_4_PENDING_0_MAP1_RANGE                        31:16
+#define HSP_DBELL_4_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
+#define HSP_DBELL_4_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_4_PENDING_0_MAP1_WOFFSET                      0x0
+#define HSP_DBELL_4_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_4_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_4_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
+#define HSP_DBELL_4_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_4_PENDING_0_MAP0_SHIFT)
+#define HSP_DBELL_4_PENDING_0_MAP0_RANGE                        15:0
+#define HSP_DBELL_4_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
+#define HSP_DBELL_4_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_4_PENDING_0_MAP0_WOFFSET                      0x0
+#define HSP_DBELL_4_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_4_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x410
+
+// Reserved address 0x414
+
+// Reserved address 0x418
+
+// Reserved address 0x41c
+
+// Reserved address 0x420
+
+// Register HSP_DBELL_4_ENABLE_SLICE1_0
+#define HSP_DBELL_4_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x424)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_SECURE                      0x0
+#define HSP_DBELL_4_ENABLE_SLICE1_0_DUAL                        0x0
+#define HSP_DBELL_4_ENABLE_SLICE1_0_SCR                         DB_4_REG_0
+#define HSP_DBELL_4_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_4_REG_0
+#define HSP_DBELL_4_ENABLE_SLICE1_0_WORD_COUNT                  0x1
+#define HSP_DBELL_4_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_4_RAW_SLICE1_0
+#define HSP_DBELL_4_RAW_SLICE1_0                        MK_ADDR_CONST(0x428)
+#define HSP_DBELL_4_RAW_SLICE1_0_SECURE                         0x0
+#define HSP_DBELL_4_RAW_SLICE1_0_DUAL                   0x0
+#define HSP_DBELL_4_RAW_SLICE1_0_SCR                    DB_4_REG_0
+#define HSP_DBELL_4_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_4_REG_0
+#define HSP_DBELL_4_RAW_SLICE1_0_WORD_COUNT                     0x1
+#define HSP_DBELL_4_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_4_RAW_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_RANGE                     31:16
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_4_RAW_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_RANGE                     15:0
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_4_PENDING_SLICE1_0
+#define HSP_DBELL_4_PENDING_SLICE1_0                    MK_ADDR_CONST(0x42c)
+#define HSP_DBELL_4_PENDING_SLICE1_0_SECURE                     0x0
+#define HSP_DBELL_4_PENDING_SLICE1_0_DUAL                       0x0
+#define HSP_DBELL_4_PENDING_SLICE1_0_SCR                        DB_4_REG_0
+#define HSP_DBELL_4_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_4_REG_0
+#define HSP_DBELL_4_PENDING_SLICE1_0_WORD_COUNT                         0x1
+#define HSP_DBELL_4_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_4_PENDING_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_4_PENDING_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_4_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_5_TRIGGER_0
+#define HSP_DBELL_5_TRIGGER_0                   MK_ADDR_CONST(0x500)
+#define HSP_DBELL_5_TRIGGER_0_SECURE                    0x0
+#define HSP_DBELL_5_TRIGGER_0_DUAL                      0x0
+#define HSP_DBELL_5_TRIGGER_0_SCR                       0
+#define HSP_DBELL_5_TRIGGER_0_SCRREG                    0
+#define HSP_DBELL_5_TRIGGER_0_WORD_COUNT                        0x1
+#define HSP_DBELL_5_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_5_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_5_TRIGGER_0_DUMMY_SHIFT)
+#define HSP_DBELL_5_TRIGGER_0_DUMMY_RANGE                       31:0
+#define HSP_DBELL_5_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
+#define HSP_DBELL_5_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_5_TRIGGER_0_DUMMY_WOFFSET                     0x0
+#define HSP_DBELL_5_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_5_ENABLE_0
+#define HSP_DBELL_5_ENABLE_0                    MK_ADDR_CONST(0x504)
+#define HSP_DBELL_5_ENABLE_0_SECURE                     0x0
+#define HSP_DBELL_5_ENABLE_0_DUAL                       0x0
+#define HSP_DBELL_5_ENABLE_0_SCR                        DB_5_REG_0
+#define HSP_DBELL_5_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_5_REG_0
+#define HSP_DBELL_5_ENABLE_0_WORD_COUNT                         0x1
+#define HSP_DBELL_5_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_5_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_5_ENABLE_0_MAP1_SHIFT)
+#define HSP_DBELL_5_ENABLE_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_5_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_5_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_5_ENABLE_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_5_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_5_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_5_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_5_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_5_ENABLE_0_MAP0_SHIFT)
+#define HSP_DBELL_5_ENABLE_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_5_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_5_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_5_ENABLE_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_5_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_5_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_5_RAW_0
+#define HSP_DBELL_5_RAW_0                       MK_ADDR_CONST(0x508)
+#define HSP_DBELL_5_RAW_0_SECURE                        0x0
+#define HSP_DBELL_5_RAW_0_DUAL                  0x0
+#define HSP_DBELL_5_RAW_0_SCR                   DB_5_REG_0
+#define HSP_DBELL_5_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_5_REG_0
+#define HSP_DBELL_5_RAW_0_WORD_COUNT                    0x1
+#define HSP_DBELL_5_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_5_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_5_RAW_0_MAP1_SHIFT)
+#define HSP_DBELL_5_RAW_0_MAP1_RANGE                    31:16
+#define HSP_DBELL_5_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
+#define HSP_DBELL_5_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
+#define HSP_DBELL_5_RAW_0_MAP1_WOFFSET                  0x0
+#define HSP_DBELL_5_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_5_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_5_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_5_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_5_RAW_0_MAP0_SHIFT)
+#define HSP_DBELL_5_RAW_0_MAP0_RANGE                    15:0
+#define HSP_DBELL_5_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
+#define HSP_DBELL_5_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
+#define HSP_DBELL_5_RAW_0_MAP0_WOFFSET                  0x0
+#define HSP_DBELL_5_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_5_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_5_PENDING_0
+#define HSP_DBELL_5_PENDING_0                   MK_ADDR_CONST(0x50c)
+#define HSP_DBELL_5_PENDING_0_SECURE                    0x0
+#define HSP_DBELL_5_PENDING_0_DUAL                      0x0
+#define HSP_DBELL_5_PENDING_0_SCR                       DB_5_REG_0
+#define HSP_DBELL_5_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_5_REG_0
+#define HSP_DBELL_5_PENDING_0_WORD_COUNT                        0x1
+#define HSP_DBELL_5_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
+#define HSP_DBELL_5_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_5_PENDING_0_MAP1_SHIFT)
+#define HSP_DBELL_5_PENDING_0_MAP1_RANGE                        31:16
+#define HSP_DBELL_5_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
+#define HSP_DBELL_5_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_5_PENDING_0_MAP1_WOFFSET                      0x0
+#define HSP_DBELL_5_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_5_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_5_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
+#define HSP_DBELL_5_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_5_PENDING_0_MAP0_SHIFT)
+#define HSP_DBELL_5_PENDING_0_MAP0_RANGE                        15:0
+#define HSP_DBELL_5_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
+#define HSP_DBELL_5_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_5_PENDING_0_MAP0_WOFFSET                      0x0
+#define HSP_DBELL_5_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_5_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x510
+
+// Reserved address 0x514
+
+// Reserved address 0x518
+
+// Reserved address 0x51c
+
+// Reserved address 0x520
+
+// Register HSP_DBELL_5_ENABLE_SLICE1_0
+#define HSP_DBELL_5_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x524)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_SECURE                      0x0
+#define HSP_DBELL_5_ENABLE_SLICE1_0_DUAL                        0x0
+#define HSP_DBELL_5_ENABLE_SLICE1_0_SCR                         DB_5_REG_0
+#define HSP_DBELL_5_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_5_REG_0
+#define HSP_DBELL_5_ENABLE_SLICE1_0_WORD_COUNT                  0x1
+#define HSP_DBELL_5_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_5_RAW_SLICE1_0
+#define HSP_DBELL_5_RAW_SLICE1_0                        MK_ADDR_CONST(0x528)
+#define HSP_DBELL_5_RAW_SLICE1_0_SECURE                         0x0
+#define HSP_DBELL_5_RAW_SLICE1_0_DUAL                   0x0
+#define HSP_DBELL_5_RAW_SLICE1_0_SCR                    DB_5_REG_0
+#define HSP_DBELL_5_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_5_REG_0
+#define HSP_DBELL_5_RAW_SLICE1_0_WORD_COUNT                     0x1
+#define HSP_DBELL_5_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_5_RAW_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_RANGE                     31:16
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_5_RAW_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_RANGE                     15:0
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_5_PENDING_SLICE1_0
+#define HSP_DBELL_5_PENDING_SLICE1_0                    MK_ADDR_CONST(0x52c)
+#define HSP_DBELL_5_PENDING_SLICE1_0_SECURE                     0x0
+#define HSP_DBELL_5_PENDING_SLICE1_0_DUAL                       0x0
+#define HSP_DBELL_5_PENDING_SLICE1_0_SCR                        DB_5_REG_0
+#define HSP_DBELL_5_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_5_REG_0
+#define HSP_DBELL_5_PENDING_SLICE1_0_WORD_COUNT                         0x1
+#define HSP_DBELL_5_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_5_PENDING_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_5_PENDING_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_5_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_6_TRIGGER_0
+#define HSP_DBELL_6_TRIGGER_0                   MK_ADDR_CONST(0x600)
+#define HSP_DBELL_6_TRIGGER_0_SECURE                    0x0
+#define HSP_DBELL_6_TRIGGER_0_DUAL                      0x0
+#define HSP_DBELL_6_TRIGGER_0_SCR                       0
+#define HSP_DBELL_6_TRIGGER_0_SCRREG                    0
+#define HSP_DBELL_6_TRIGGER_0_WORD_COUNT                        0x1
+#define HSP_DBELL_6_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_6_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_6_TRIGGER_0_DUMMY_SHIFT)
+#define HSP_DBELL_6_TRIGGER_0_DUMMY_RANGE                       31:0
+#define HSP_DBELL_6_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
+#define HSP_DBELL_6_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_6_TRIGGER_0_DUMMY_WOFFSET                     0x0
+#define HSP_DBELL_6_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_6_ENABLE_0
+#define HSP_DBELL_6_ENABLE_0                    MK_ADDR_CONST(0x604)
+#define HSP_DBELL_6_ENABLE_0_SECURE                     0x0
+#define HSP_DBELL_6_ENABLE_0_DUAL                       0x0
+#define HSP_DBELL_6_ENABLE_0_SCR                        DB_6_REG_0
+#define HSP_DBELL_6_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_6_REG_0
+#define HSP_DBELL_6_ENABLE_0_WORD_COUNT                         0x1
+#define HSP_DBELL_6_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_6_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_6_ENABLE_0_MAP1_SHIFT)
+#define HSP_DBELL_6_ENABLE_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_6_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_6_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_6_ENABLE_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_6_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_6_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_6_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_6_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_6_ENABLE_0_MAP0_SHIFT)
+#define HSP_DBELL_6_ENABLE_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_6_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_6_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_6_ENABLE_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_6_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_6_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_6_RAW_0
+#define HSP_DBELL_6_RAW_0                       MK_ADDR_CONST(0x608)
+#define HSP_DBELL_6_RAW_0_SECURE                        0x0
+#define HSP_DBELL_6_RAW_0_DUAL                  0x0
+#define HSP_DBELL_6_RAW_0_SCR                   DB_6_REG_0
+#define HSP_DBELL_6_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_6_REG_0
+#define HSP_DBELL_6_RAW_0_WORD_COUNT                    0x1
+#define HSP_DBELL_6_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_6_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_6_RAW_0_MAP1_SHIFT)
+#define HSP_DBELL_6_RAW_0_MAP1_RANGE                    31:16
+#define HSP_DBELL_6_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
+#define HSP_DBELL_6_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
+#define HSP_DBELL_6_RAW_0_MAP1_WOFFSET                  0x0
+#define HSP_DBELL_6_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_6_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_6_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_6_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_6_RAW_0_MAP0_SHIFT)
+#define HSP_DBELL_6_RAW_0_MAP0_RANGE                    15:0
+#define HSP_DBELL_6_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
+#define HSP_DBELL_6_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
+#define HSP_DBELL_6_RAW_0_MAP0_WOFFSET                  0x0
+#define HSP_DBELL_6_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_6_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_6_PENDING_0
+#define HSP_DBELL_6_PENDING_0                   MK_ADDR_CONST(0x60c)
+#define HSP_DBELL_6_PENDING_0_SECURE                    0x0
+#define HSP_DBELL_6_PENDING_0_DUAL                      0x0
+#define HSP_DBELL_6_PENDING_0_SCR                       DB_6_REG_0
+#define HSP_DBELL_6_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_6_REG_0
+#define HSP_DBELL_6_PENDING_0_WORD_COUNT                        0x1
+#define HSP_DBELL_6_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
+#define HSP_DBELL_6_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_6_PENDING_0_MAP1_SHIFT)
+#define HSP_DBELL_6_PENDING_0_MAP1_RANGE                        31:16
+#define HSP_DBELL_6_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
+#define HSP_DBELL_6_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_6_PENDING_0_MAP1_WOFFSET                      0x0
+#define HSP_DBELL_6_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_6_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_6_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
+#define HSP_DBELL_6_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_6_PENDING_0_MAP0_SHIFT)
+#define HSP_DBELL_6_PENDING_0_MAP0_RANGE                        15:0
+#define HSP_DBELL_6_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
+#define HSP_DBELL_6_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_6_PENDING_0_MAP0_WOFFSET                      0x0
+#define HSP_DBELL_6_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_6_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x610
+
+// Reserved address 0x614
+
+// Reserved address 0x618
+
+// Reserved address 0x61c
+
+// Reserved address 0x620
+
+// Register HSP_DBELL_6_ENABLE_SLICE1_0
+#define HSP_DBELL_6_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x624)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_SECURE                      0x0
+#define HSP_DBELL_6_ENABLE_SLICE1_0_DUAL                        0x0
+#define HSP_DBELL_6_ENABLE_SLICE1_0_SCR                         DB_6_REG_0
+#define HSP_DBELL_6_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_6_REG_0
+#define HSP_DBELL_6_ENABLE_SLICE1_0_WORD_COUNT                  0x1
+#define HSP_DBELL_6_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_6_RAW_SLICE1_0
+#define HSP_DBELL_6_RAW_SLICE1_0                        MK_ADDR_CONST(0x628)
+#define HSP_DBELL_6_RAW_SLICE1_0_SECURE                         0x0
+#define HSP_DBELL_6_RAW_SLICE1_0_DUAL                   0x0
+#define HSP_DBELL_6_RAW_SLICE1_0_SCR                    DB_6_REG_0
+#define HSP_DBELL_6_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_6_REG_0
+#define HSP_DBELL_6_RAW_SLICE1_0_WORD_COUNT                     0x1
+#define HSP_DBELL_6_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_6_RAW_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_RANGE                     31:16
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_6_RAW_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_RANGE                     15:0
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_6_PENDING_SLICE1_0
+#define HSP_DBELL_6_PENDING_SLICE1_0                    MK_ADDR_CONST(0x62c)
+#define HSP_DBELL_6_PENDING_SLICE1_0_SECURE                     0x0
+#define HSP_DBELL_6_PENDING_SLICE1_0_DUAL                       0x0
+#define HSP_DBELL_6_PENDING_SLICE1_0_SCR                        DB_6_REG_0
+#define HSP_DBELL_6_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_6_REG_0
+#define HSP_DBELL_6_PENDING_SLICE1_0_WORD_COUNT                         0x1
+#define HSP_DBELL_6_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_6_PENDING_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_6_PENDING_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_6_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_7_TRIGGER_0
+#define HSP_DBELL_7_TRIGGER_0                   MK_ADDR_CONST(0x700)
+#define HSP_DBELL_7_TRIGGER_0_SECURE                    0x0
+#define HSP_DBELL_7_TRIGGER_0_DUAL                      0x0
+#define HSP_DBELL_7_TRIGGER_0_SCR                       0
+#define HSP_DBELL_7_TRIGGER_0_SCRREG                    0
+#define HSP_DBELL_7_TRIGGER_0_WORD_COUNT                        0x1
+#define HSP_DBELL_7_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_7_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_7_TRIGGER_0_DUMMY_SHIFT)
+#define HSP_DBELL_7_TRIGGER_0_DUMMY_RANGE                       31:0
+#define HSP_DBELL_7_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
+#define HSP_DBELL_7_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_7_TRIGGER_0_DUMMY_WOFFSET                     0x0
+#define HSP_DBELL_7_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_7_ENABLE_0
+#define HSP_DBELL_7_ENABLE_0                    MK_ADDR_CONST(0x704)
+#define HSP_DBELL_7_ENABLE_0_SECURE                     0x0
+#define HSP_DBELL_7_ENABLE_0_DUAL                       0x0
+#define HSP_DBELL_7_ENABLE_0_SCR                        DB_7_REG_0
+#define HSP_DBELL_7_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_7_REG_0
+#define HSP_DBELL_7_ENABLE_0_WORD_COUNT                         0x1
+#define HSP_DBELL_7_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_7_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_7_ENABLE_0_MAP1_SHIFT)
+#define HSP_DBELL_7_ENABLE_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_7_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_7_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_7_ENABLE_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_7_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_7_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_7_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_7_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_7_ENABLE_0_MAP0_SHIFT)
+#define HSP_DBELL_7_ENABLE_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_7_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_7_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_7_ENABLE_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_7_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_7_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_7_RAW_0
+#define HSP_DBELL_7_RAW_0                       MK_ADDR_CONST(0x708)
+#define HSP_DBELL_7_RAW_0_SECURE                        0x0
+#define HSP_DBELL_7_RAW_0_DUAL                  0x0
+#define HSP_DBELL_7_RAW_0_SCR                   DB_7_REG_0
+#define HSP_DBELL_7_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_7_REG_0
+#define HSP_DBELL_7_RAW_0_WORD_COUNT                    0x1
+#define HSP_DBELL_7_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_7_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_7_RAW_0_MAP1_SHIFT)
+#define HSP_DBELL_7_RAW_0_MAP1_RANGE                    31:16
+#define HSP_DBELL_7_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
+#define HSP_DBELL_7_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
+#define HSP_DBELL_7_RAW_0_MAP1_WOFFSET                  0x0
+#define HSP_DBELL_7_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_7_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_7_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_7_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_7_RAW_0_MAP0_SHIFT)
+#define HSP_DBELL_7_RAW_0_MAP0_RANGE                    15:0
+#define HSP_DBELL_7_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
+#define HSP_DBELL_7_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
+#define HSP_DBELL_7_RAW_0_MAP0_WOFFSET                  0x0
+#define HSP_DBELL_7_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_7_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_7_PENDING_0
+#define HSP_DBELL_7_PENDING_0                   MK_ADDR_CONST(0x70c)
+#define HSP_DBELL_7_PENDING_0_SECURE                    0x0
+#define HSP_DBELL_7_PENDING_0_DUAL                      0x0
+#define HSP_DBELL_7_PENDING_0_SCR                       DB_7_REG_0
+#define HSP_DBELL_7_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_7_REG_0
+#define HSP_DBELL_7_PENDING_0_WORD_COUNT                        0x1
+#define HSP_DBELL_7_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
+#define HSP_DBELL_7_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_7_PENDING_0_MAP1_SHIFT)
+#define HSP_DBELL_7_PENDING_0_MAP1_RANGE                        31:16
+#define HSP_DBELL_7_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
+#define HSP_DBELL_7_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_7_PENDING_0_MAP1_WOFFSET                      0x0
+#define HSP_DBELL_7_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_7_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_7_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
+#define HSP_DBELL_7_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_7_PENDING_0_MAP0_SHIFT)
+#define HSP_DBELL_7_PENDING_0_MAP0_RANGE                        15:0
+#define HSP_DBELL_7_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
+#define HSP_DBELL_7_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_7_PENDING_0_MAP0_WOFFSET                      0x0
+#define HSP_DBELL_7_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_7_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x710
+
+// Reserved address 0x714
+
+// Reserved address 0x718
+
+// Reserved address 0x71c
+
+// Reserved address 0x720
+
+// Register HSP_DBELL_7_ENABLE_SLICE1_0
+#define HSP_DBELL_7_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x724)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_SECURE                      0x0
+#define HSP_DBELL_7_ENABLE_SLICE1_0_DUAL                        0x0
+#define HSP_DBELL_7_ENABLE_SLICE1_0_SCR                         DB_7_REG_0
+#define HSP_DBELL_7_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_7_REG_0
+#define HSP_DBELL_7_ENABLE_SLICE1_0_WORD_COUNT                  0x1
+#define HSP_DBELL_7_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_7_RAW_SLICE1_0
+#define HSP_DBELL_7_RAW_SLICE1_0                        MK_ADDR_CONST(0x728)
+#define HSP_DBELL_7_RAW_SLICE1_0_SECURE                         0x0
+#define HSP_DBELL_7_RAW_SLICE1_0_DUAL                   0x0
+#define HSP_DBELL_7_RAW_SLICE1_0_SCR                    DB_7_REG_0
+#define HSP_DBELL_7_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_7_REG_0
+#define HSP_DBELL_7_RAW_SLICE1_0_WORD_COUNT                     0x1
+#define HSP_DBELL_7_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_7_RAW_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_RANGE                     31:16
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_7_RAW_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_RANGE                     15:0
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_7_PENDING_SLICE1_0
+#define HSP_DBELL_7_PENDING_SLICE1_0                    MK_ADDR_CONST(0x72c)
+#define HSP_DBELL_7_PENDING_SLICE1_0_SECURE                     0x0
+#define HSP_DBELL_7_PENDING_SLICE1_0_DUAL                       0x0
+#define HSP_DBELL_7_PENDING_SLICE1_0_SCR                        DB_7_REG_0
+#define HSP_DBELL_7_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_7_REG_0
+#define HSP_DBELL_7_PENDING_SLICE1_0_WORD_COUNT                         0x1
+#define HSP_DBELL_7_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_7_PENDING_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_7_PENDING_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_7_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_8_TRIGGER_0
+#define HSP_DBELL_8_TRIGGER_0                   MK_ADDR_CONST(0x800)
+#define HSP_DBELL_8_TRIGGER_0_SECURE                    0x0
+#define HSP_DBELL_8_TRIGGER_0_DUAL                      0x0
+#define HSP_DBELL_8_TRIGGER_0_SCR                       0
+#define HSP_DBELL_8_TRIGGER_0_SCRREG                    0
+#define HSP_DBELL_8_TRIGGER_0_WORD_COUNT                        0x1
+#define HSP_DBELL_8_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_8_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_8_TRIGGER_0_DUMMY_SHIFT)
+#define HSP_DBELL_8_TRIGGER_0_DUMMY_RANGE                       31:0
+#define HSP_DBELL_8_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
+#define HSP_DBELL_8_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_8_TRIGGER_0_DUMMY_WOFFSET                     0x0
+#define HSP_DBELL_8_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_8_ENABLE_0
+#define HSP_DBELL_8_ENABLE_0                    MK_ADDR_CONST(0x804)
+#define HSP_DBELL_8_ENABLE_0_SECURE                     0x0
+#define HSP_DBELL_8_ENABLE_0_DUAL                       0x0
+#define HSP_DBELL_8_ENABLE_0_SCR                        DB_8_REG_0
+#define HSP_DBELL_8_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_8_REG_0
+#define HSP_DBELL_8_ENABLE_0_WORD_COUNT                         0x1
+#define HSP_DBELL_8_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_8_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_8_ENABLE_0_MAP1_SHIFT)
+#define HSP_DBELL_8_ENABLE_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_8_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_8_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_8_ENABLE_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_8_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_8_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_8_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_8_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_8_ENABLE_0_MAP0_SHIFT)
+#define HSP_DBELL_8_ENABLE_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_8_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_8_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_8_ENABLE_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_8_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_8_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_8_RAW_0
+#define HSP_DBELL_8_RAW_0                       MK_ADDR_CONST(0x808)
+#define HSP_DBELL_8_RAW_0_SECURE                        0x0
+#define HSP_DBELL_8_RAW_0_DUAL                  0x0
+#define HSP_DBELL_8_RAW_0_SCR                   DB_8_REG_0
+#define HSP_DBELL_8_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_8_REG_0
+#define HSP_DBELL_8_RAW_0_WORD_COUNT                    0x1
+#define HSP_DBELL_8_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_8_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_8_RAW_0_MAP1_SHIFT)
+#define HSP_DBELL_8_RAW_0_MAP1_RANGE                    31:16
+#define HSP_DBELL_8_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
+#define HSP_DBELL_8_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
+#define HSP_DBELL_8_RAW_0_MAP1_WOFFSET                  0x0
+#define HSP_DBELL_8_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_8_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_8_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_8_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_8_RAW_0_MAP0_SHIFT)
+#define HSP_DBELL_8_RAW_0_MAP0_RANGE                    15:0
+#define HSP_DBELL_8_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
+#define HSP_DBELL_8_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
+#define HSP_DBELL_8_RAW_0_MAP0_WOFFSET                  0x0
+#define HSP_DBELL_8_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_8_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_8_PENDING_0
+#define HSP_DBELL_8_PENDING_0                   MK_ADDR_CONST(0x80c)
+#define HSP_DBELL_8_PENDING_0_SECURE                    0x0
+#define HSP_DBELL_8_PENDING_0_DUAL                      0x0
+#define HSP_DBELL_8_PENDING_0_SCR                       DB_8_REG_0
+#define HSP_DBELL_8_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_8_REG_0
+#define HSP_DBELL_8_PENDING_0_WORD_COUNT                        0x1
+#define HSP_DBELL_8_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
+#define HSP_DBELL_8_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_8_PENDING_0_MAP1_SHIFT)
+#define HSP_DBELL_8_PENDING_0_MAP1_RANGE                        31:16
+#define HSP_DBELL_8_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
+#define HSP_DBELL_8_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_8_PENDING_0_MAP1_WOFFSET                      0x0
+#define HSP_DBELL_8_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_8_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_8_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
+#define HSP_DBELL_8_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_8_PENDING_0_MAP0_SHIFT)
+#define HSP_DBELL_8_PENDING_0_MAP0_RANGE                        15:0
+#define HSP_DBELL_8_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
+#define HSP_DBELL_8_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_8_PENDING_0_MAP0_WOFFSET                      0x0
+#define HSP_DBELL_8_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_8_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x810
+
+// Reserved address 0x814
+
+// Reserved address 0x818
+
+// Reserved address 0x81c
+
+// Reserved address 0x820
+
+// Register HSP_DBELL_8_ENABLE_SLICE1_0
+#define HSP_DBELL_8_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x824)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_SECURE                      0x0
+#define HSP_DBELL_8_ENABLE_SLICE1_0_DUAL                        0x0
+#define HSP_DBELL_8_ENABLE_SLICE1_0_SCR                         DB_8_REG_0
+#define HSP_DBELL_8_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_8_REG_0
+#define HSP_DBELL_8_ENABLE_SLICE1_0_WORD_COUNT                  0x1
+#define HSP_DBELL_8_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_8_RAW_SLICE1_0
+#define HSP_DBELL_8_RAW_SLICE1_0                        MK_ADDR_CONST(0x828)
+#define HSP_DBELL_8_RAW_SLICE1_0_SECURE                         0x0
+#define HSP_DBELL_8_RAW_SLICE1_0_DUAL                   0x0
+#define HSP_DBELL_8_RAW_SLICE1_0_SCR                    DB_8_REG_0
+#define HSP_DBELL_8_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_8_REG_0
+#define HSP_DBELL_8_RAW_SLICE1_0_WORD_COUNT                     0x1
+#define HSP_DBELL_8_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_8_RAW_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_RANGE                     31:16
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_8_RAW_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_RANGE                     15:0
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_8_PENDING_SLICE1_0
+#define HSP_DBELL_8_PENDING_SLICE1_0                    MK_ADDR_CONST(0x82c)
+#define HSP_DBELL_8_PENDING_SLICE1_0_SECURE                     0x0
+#define HSP_DBELL_8_PENDING_SLICE1_0_DUAL                       0x0
+#define HSP_DBELL_8_PENDING_SLICE1_0_SCR                        DB_8_REG_0
+#define HSP_DBELL_8_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_8_REG_0
+#define HSP_DBELL_8_PENDING_SLICE1_0_WORD_COUNT                         0x1
+#define HSP_DBELL_8_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_8_PENDING_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_8_PENDING_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_8_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_9_TRIGGER_0
+#define HSP_DBELL_9_TRIGGER_0                   MK_ADDR_CONST(0x900)
+#define HSP_DBELL_9_TRIGGER_0_SECURE                    0x0
+#define HSP_DBELL_9_TRIGGER_0_DUAL                      0x0
+#define HSP_DBELL_9_TRIGGER_0_SCR                       0
+#define HSP_DBELL_9_TRIGGER_0_SCRREG                    0
+#define HSP_DBELL_9_TRIGGER_0_WORD_COUNT                        0x1
+#define HSP_DBELL_9_TRIGGER_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_TRIGGER_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_TRIGGER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_TRIGGER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_TRIGGER_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_TRIGGER_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_TRIGGER_0_DUMMY_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_9_TRIGGER_0_DUMMY_FIELD                       MK_FIELD_CONST(0xffffffff, HSP_DBELL_9_TRIGGER_0_DUMMY_SHIFT)
+#define HSP_DBELL_9_TRIGGER_0_DUMMY_RANGE                       31:0
+#define HSP_DBELL_9_TRIGGER_0_DUMMY_MSB                 MK_SHIFT_CONST(31)
+#define HSP_DBELL_9_TRIGGER_0_DUMMY_LSB                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_9_TRIGGER_0_DUMMY_WOFFSET                     0x0
+#define HSP_DBELL_9_TRIGGER_0_DUMMY_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_TRIGGER_0_DUMMY_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_TRIGGER_0_DUMMY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_TRIGGER_0_DUMMY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_TRIGGER_0_DUMMY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_TRIGGER_0_DUMMY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_9_ENABLE_0
+#define HSP_DBELL_9_ENABLE_0                    MK_ADDR_CONST(0x904)
+#define HSP_DBELL_9_ENABLE_0_SECURE                     0x0
+#define HSP_DBELL_9_ENABLE_0_DUAL                       0x0
+#define HSP_DBELL_9_ENABLE_0_SCR                        DB_9_REG_0
+#define HSP_DBELL_9_ENABLE_0_SCRREG                     HSP_DBELL_SCR_DB_9_REG_0
+#define HSP_DBELL_9_ENABLE_0_WORD_COUNT                         0x1
+#define HSP_DBELL_9_ENABLE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_ENABLE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_ENABLE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_ENABLE_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_9_ENABLE_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_9_ENABLE_0_MAP1_SHIFT)
+#define HSP_DBELL_9_ENABLE_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_9_ENABLE_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_9_ENABLE_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_9_ENABLE_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_9_ENABLE_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_9_ENABLE_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_9_ENABLE_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_9_ENABLE_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_9_ENABLE_0_MAP0_SHIFT)
+#define HSP_DBELL_9_ENABLE_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_9_ENABLE_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_9_ENABLE_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_9_ENABLE_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_9_ENABLE_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_9_ENABLE_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_9_RAW_0
+#define HSP_DBELL_9_RAW_0                       MK_ADDR_CONST(0x908)
+#define HSP_DBELL_9_RAW_0_SECURE                        0x0
+#define HSP_DBELL_9_RAW_0_DUAL                  0x0
+#define HSP_DBELL_9_RAW_0_SCR                   DB_9_REG_0
+#define HSP_DBELL_9_RAW_0_SCRREG                        HSP_DBELL_SCR_DB_9_REG_0
+#define HSP_DBELL_9_RAW_0_WORD_COUNT                    0x1
+#define HSP_DBELL_9_RAW_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_RAW_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_RAW_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_RAW_0_MAP1_SHIFT                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_9_RAW_0_MAP1_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_9_RAW_0_MAP1_SHIFT)
+#define HSP_DBELL_9_RAW_0_MAP1_RANGE                    31:16
+#define HSP_DBELL_9_RAW_0_MAP1_MSB                      MK_SHIFT_CONST(31)
+#define HSP_DBELL_9_RAW_0_MAP1_LSB                      MK_SHIFT_CONST(16)
+#define HSP_DBELL_9_RAW_0_MAP1_WOFFSET                  0x0
+#define HSP_DBELL_9_RAW_0_MAP1_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_0_MAP1_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_9_RAW_0_MAP1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_0_MAP1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_0_MAP1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_0_MAP1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_9_RAW_0_MAP0_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_9_RAW_0_MAP0_FIELD                    MK_FIELD_CONST(0xffff, HSP_DBELL_9_RAW_0_MAP0_SHIFT)
+#define HSP_DBELL_9_RAW_0_MAP0_RANGE                    15:0
+#define HSP_DBELL_9_RAW_0_MAP0_MSB                      MK_SHIFT_CONST(15)
+#define HSP_DBELL_9_RAW_0_MAP0_LSB                      MK_SHIFT_CONST(0)
+#define HSP_DBELL_9_RAW_0_MAP0_WOFFSET                  0x0
+#define HSP_DBELL_9_RAW_0_MAP0_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_0_MAP0_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define HSP_DBELL_9_RAW_0_MAP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_0_MAP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_0_MAP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_0_MAP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_9_PENDING_0
+#define HSP_DBELL_9_PENDING_0                   MK_ADDR_CONST(0x90c)
+#define HSP_DBELL_9_PENDING_0_SECURE                    0x0
+#define HSP_DBELL_9_PENDING_0_DUAL                      0x0
+#define HSP_DBELL_9_PENDING_0_SCR                       DB_9_REG_0
+#define HSP_DBELL_9_PENDING_0_SCRREG                    HSP_DBELL_SCR_DB_9_REG_0
+#define HSP_DBELL_9_PENDING_0_WORD_COUNT                        0x1
+#define HSP_DBELL_9_PENDING_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_PENDING_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_PENDING_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_PENDING_0_MAP1_SHIFT                        MK_SHIFT_CONST(16)
+#define HSP_DBELL_9_PENDING_0_MAP1_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_9_PENDING_0_MAP1_SHIFT)
+#define HSP_DBELL_9_PENDING_0_MAP1_RANGE                        31:16
+#define HSP_DBELL_9_PENDING_0_MAP1_MSB                  MK_SHIFT_CONST(31)
+#define HSP_DBELL_9_PENDING_0_MAP1_LSB                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_9_PENDING_0_MAP1_WOFFSET                      0x0
+#define HSP_DBELL_9_PENDING_0_MAP1_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_0_MAP1_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_9_PENDING_0_MAP1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_0_MAP1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_0_MAP1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_0_MAP1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_9_PENDING_0_MAP0_SHIFT                        MK_SHIFT_CONST(0)
+#define HSP_DBELL_9_PENDING_0_MAP0_FIELD                        MK_FIELD_CONST(0xffff, HSP_DBELL_9_PENDING_0_MAP0_SHIFT)
+#define HSP_DBELL_9_PENDING_0_MAP0_RANGE                        15:0
+#define HSP_DBELL_9_PENDING_0_MAP0_MSB                  MK_SHIFT_CONST(15)
+#define HSP_DBELL_9_PENDING_0_MAP0_LSB                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_9_PENDING_0_MAP0_WOFFSET                      0x0
+#define HSP_DBELL_9_PENDING_0_MAP0_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_0_MAP0_DEFAULT_MASK                 MK_MASK_CONST(0xffff)
+#define HSP_DBELL_9_PENDING_0_MAP0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_0_MAP0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_0_MAP0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_0_MAP0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x910
+
+// Reserved address 0x914
+
+// Reserved address 0x918
+
+// Reserved address 0x91c
+
+// Reserved address 0x920
+
+// Register HSP_DBELL_9_ENABLE_SLICE1_0
+#define HSP_DBELL_9_ENABLE_SLICE1_0                     MK_ADDR_CONST(0x924)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_SECURE                      0x0
+#define HSP_DBELL_9_ENABLE_SLICE1_0_DUAL                        0x0
+#define HSP_DBELL_9_ENABLE_SLICE1_0_SCR                         DB_9_REG_0
+#define HSP_DBELL_9_ENABLE_SLICE1_0_SCRREG                      HSP_DBELL_SCR_DB_9_REG_0
+#define HSP_DBELL_9_ENABLE_SLICE1_0_WORD_COUNT                  0x1
+#define HSP_DBELL_9_ENABLE_SLICE1_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_SHIFT                  MK_SHIFT_CONST(16)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_RANGE                  31:16
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_MSB                    MK_SHIFT_CONST(31)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_LSB                    MK_SHIFT_CONST(16)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_WOFFSET                        0x0
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_SHIFT                  MK_SHIFT_CONST(0)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_FIELD                  MK_FIELD_CONST(0xffff, HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_RANGE                  15:0
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_MSB                    MK_SHIFT_CONST(15)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_LSB                    MK_SHIFT_CONST(0)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_WOFFSET                        0x0
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_ENABLE_SLICE1_0_MAP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_9_RAW_SLICE1_0
+#define HSP_DBELL_9_RAW_SLICE1_0                        MK_ADDR_CONST(0x928)
+#define HSP_DBELL_9_RAW_SLICE1_0_SECURE                         0x0
+#define HSP_DBELL_9_RAW_SLICE1_0_DUAL                   0x0
+#define HSP_DBELL_9_RAW_SLICE1_0_SCR                    DB_9_REG_0
+#define HSP_DBELL_9_RAW_SLICE1_0_SCRREG                         HSP_DBELL_SCR_DB_9_REG_0
+#define HSP_DBELL_9_RAW_SLICE1_0_WORD_COUNT                     0x1
+#define HSP_DBELL_9_RAW_SLICE1_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_SLICE1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_RAW_SLICE1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_SLICE1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_SLICE1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_RAW_SLICE1_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_SHIFT                     MK_SHIFT_CONST(16)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_9_RAW_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_RANGE                     31:16
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_MSB                       MK_SHIFT_CONST(31)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_LSB                       MK_SHIFT_CONST(16)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_WOFFSET                   0x0
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_FIELD                     MK_FIELD_CONST(0xffff, HSP_DBELL_9_RAW_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_RANGE                     15:0
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_MSB                       MK_SHIFT_CONST(15)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_LSB                       MK_SHIFT_CONST(0)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_WOFFSET                   0x0
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_RAW_SLICE1_0_MAP0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_DBELL_9_PENDING_SLICE1_0
+#define HSP_DBELL_9_PENDING_SLICE1_0                    MK_ADDR_CONST(0x92c)
+#define HSP_DBELL_9_PENDING_SLICE1_0_SECURE                     0x0
+#define HSP_DBELL_9_PENDING_SLICE1_0_DUAL                       0x0
+#define HSP_DBELL_9_PENDING_SLICE1_0_SCR                        DB_9_REG_0
+#define HSP_DBELL_9_PENDING_SLICE1_0_SCRREG                     HSP_DBELL_SCR_DB_9_REG_0
+#define HSP_DBELL_9_PENDING_SLICE1_0_WORD_COUNT                         0x1
+#define HSP_DBELL_9_PENDING_SLICE1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_SLICE1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_PENDING_SLICE1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_SLICE1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_SLICE1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_PENDING_SLICE1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_9_PENDING_SLICE1_0_MAP1_SHIFT)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_RANGE                 31:16
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_MSB                   MK_SHIFT_CONST(31)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_LSB                   MK_SHIFT_CONST(16)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_WOFFSET                       0x0
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_FIELD                 MK_FIELD_CONST(0xffff, HSP_DBELL_9_PENDING_SLICE1_0_MAP0_SHIFT)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_RANGE                 15:0
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_MSB                   MK_SHIFT_CONST(15)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_LSB                   MK_SHIFT_CONST(0)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_WOFFSET                       0x0
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_DBELL_9_PENDING_SLICE1_0_MAP0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARHSP_DBELL_REGS(_op_) \
+_op_(HSP_DBELL_0_TRIGGER_0) \
+_op_(HSP_DBELL_0_ENABLE_0) \
+_op_(HSP_DBELL_0_RAW_0) \
+_op_(HSP_DBELL_0_PENDING_0) \
+_op_(HSP_DBELL_0_ENABLE_SLICE1_0) \
+_op_(HSP_DBELL_0_RAW_SLICE1_0) \
+_op_(HSP_DBELL_0_PENDING_SLICE1_0) \
+_op_(HSP_DBELL_1_TRIGGER_0) \
+_op_(HSP_DBELL_1_ENABLE_0) \
+_op_(HSP_DBELL_1_RAW_0) \
+_op_(HSP_DBELL_1_PENDING_0) \
+_op_(HSP_DBELL_1_ENABLE_SLICE1_0) \
+_op_(HSP_DBELL_1_RAW_SLICE1_0) \
+_op_(HSP_DBELL_1_PENDING_SLICE1_0) \
+_op_(HSP_DBELL_2_TRIGGER_0) \
+_op_(HSP_DBELL_2_ENABLE_0) \
+_op_(HSP_DBELL_2_RAW_0) \
+_op_(HSP_DBELL_2_PENDING_0) \
+_op_(HSP_DBELL_2_ENABLE_SLICE1_0) \
+_op_(HSP_DBELL_2_RAW_SLICE1_0) \
+_op_(HSP_DBELL_2_PENDING_SLICE1_0) \
+_op_(HSP_DBELL_3_TRIGGER_0) \
+_op_(HSP_DBELL_3_ENABLE_0) \
+_op_(HSP_DBELL_3_RAW_0) \
+_op_(HSP_DBELL_3_PENDING_0) \
+_op_(HSP_DBELL_3_ENABLE_SLICE1_0) \
+_op_(HSP_DBELL_3_RAW_SLICE1_0) \
+_op_(HSP_DBELL_3_PENDING_SLICE1_0) \
+_op_(HSP_DBELL_4_TRIGGER_0) \
+_op_(HSP_DBELL_4_ENABLE_0) \
+_op_(HSP_DBELL_4_RAW_0) \
+_op_(HSP_DBELL_4_PENDING_0) \
+_op_(HSP_DBELL_4_ENABLE_SLICE1_0) \
+_op_(HSP_DBELL_4_RAW_SLICE1_0) \
+_op_(HSP_DBELL_4_PENDING_SLICE1_0) \
+_op_(HSP_DBELL_5_TRIGGER_0) \
+_op_(HSP_DBELL_5_ENABLE_0) \
+_op_(HSP_DBELL_5_RAW_0) \
+_op_(HSP_DBELL_5_PENDING_0) \
+_op_(HSP_DBELL_5_ENABLE_SLICE1_0) \
+_op_(HSP_DBELL_5_RAW_SLICE1_0) \
+_op_(HSP_DBELL_5_PENDING_SLICE1_0) \
+_op_(HSP_DBELL_6_TRIGGER_0) \
+_op_(HSP_DBELL_6_ENABLE_0) \
+_op_(HSP_DBELL_6_RAW_0) \
+_op_(HSP_DBELL_6_PENDING_0) \
+_op_(HSP_DBELL_6_ENABLE_SLICE1_0) \
+_op_(HSP_DBELL_6_RAW_SLICE1_0) \
+_op_(HSP_DBELL_6_PENDING_SLICE1_0) \
+_op_(HSP_DBELL_7_TRIGGER_0) \
+_op_(HSP_DBELL_7_ENABLE_0) \
+_op_(HSP_DBELL_7_RAW_0) \
+_op_(HSP_DBELL_7_PENDING_0) \
+_op_(HSP_DBELL_7_ENABLE_SLICE1_0) \
+_op_(HSP_DBELL_7_RAW_SLICE1_0) \
+_op_(HSP_DBELL_7_PENDING_SLICE1_0) \
+_op_(HSP_DBELL_8_TRIGGER_0) \
+_op_(HSP_DBELL_8_ENABLE_0) \
+_op_(HSP_DBELL_8_RAW_0) \
+_op_(HSP_DBELL_8_PENDING_0) \
+_op_(HSP_DBELL_8_ENABLE_SLICE1_0) \
+_op_(HSP_DBELL_8_RAW_SLICE1_0) \
+_op_(HSP_DBELL_8_PENDING_SLICE1_0) \
+_op_(HSP_DBELL_9_TRIGGER_0) \
+_op_(HSP_DBELL_9_ENABLE_0) \
+_op_(HSP_DBELL_9_RAW_0) \
+_op_(HSP_DBELL_9_PENDING_0) \
+_op_(HSP_DBELL_9_ENABLE_SLICE1_0) \
+_op_(HSP_DBELL_9_RAW_SLICE1_0) \
+_op_(HSP_DBELL_9_PENDING_SLICE1_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_HSP        0x00000000
+
+//
+// ARHSP_DBELL REGISTER BANKS
+//
+
+#define HSP0_FIRST_REG 0x0000 // HSP_DBELL_0_TRIGGER_0
+#define HSP0_LAST_REG 0x000c // HSP_DBELL_0_PENDING_0
+#define HSP1_FIRST_REG 0x0024 // HSP_DBELL_0_ENABLE_SLICE1_0
+#define HSP1_LAST_REG 0x002c // HSP_DBELL_0_PENDING_SLICE1_0
+#define HSP2_FIRST_REG 0x0100 // HSP_DBELL_1_TRIGGER_0
+#define HSP2_LAST_REG 0x010c // HSP_DBELL_1_PENDING_0
+#define HSP3_FIRST_REG 0x0124 // HSP_DBELL_1_ENABLE_SLICE1_0
+#define HSP3_LAST_REG 0x012c // HSP_DBELL_1_PENDING_SLICE1_0
+#define HSP4_FIRST_REG 0x0200 // HSP_DBELL_2_TRIGGER_0
+#define HSP4_LAST_REG 0x020c // HSP_DBELL_2_PENDING_0
+#define HSP5_FIRST_REG 0x0224 // HSP_DBELL_2_ENABLE_SLICE1_0
+#define HSP5_LAST_REG 0x022c // HSP_DBELL_2_PENDING_SLICE1_0
+#define HSP6_FIRST_REG 0x0300 // HSP_DBELL_3_TRIGGER_0
+#define HSP6_LAST_REG 0x030c // HSP_DBELL_3_PENDING_0
+#define HSP7_FIRST_REG 0x0324 // HSP_DBELL_3_ENABLE_SLICE1_0
+#define HSP7_LAST_REG 0x032c // HSP_DBELL_3_PENDING_SLICE1_0
+#define HSP8_FIRST_REG 0x0400 // HSP_DBELL_4_TRIGGER_0
+#define HSP8_LAST_REG 0x040c // HSP_DBELL_4_PENDING_0
+#define HSP9_FIRST_REG 0x0424 // HSP_DBELL_4_ENABLE_SLICE1_0
+#define HSP9_LAST_REG 0x042c // HSP_DBELL_4_PENDING_SLICE1_0
+#define HSP10_FIRST_REG 0x0500 // HSP_DBELL_5_TRIGGER_0
+#define HSP10_LAST_REG 0x050c // HSP_DBELL_5_PENDING_0
+#define HSP11_FIRST_REG 0x0524 // HSP_DBELL_5_ENABLE_SLICE1_0
+#define HSP11_LAST_REG 0x052c // HSP_DBELL_5_PENDING_SLICE1_0
+#define HSP12_FIRST_REG 0x0600 // HSP_DBELL_6_TRIGGER_0
+#define HSP12_LAST_REG 0x060c // HSP_DBELL_6_PENDING_0
+#define HSP13_FIRST_REG 0x0624 // HSP_DBELL_6_ENABLE_SLICE1_0
+#define HSP13_LAST_REG 0x062c // HSP_DBELL_6_PENDING_SLICE1_0
+#define HSP14_FIRST_REG 0x0700 // HSP_DBELL_7_TRIGGER_0
+#define HSP14_LAST_REG 0x070c // HSP_DBELL_7_PENDING_0
+#define HSP15_FIRST_REG 0x0724 // HSP_DBELL_7_ENABLE_SLICE1_0
+#define HSP15_LAST_REG 0x072c // HSP_DBELL_7_PENDING_SLICE1_0
+#define HSP16_FIRST_REG 0x0800 // HSP_DBELL_8_TRIGGER_0
+#define HSP16_LAST_REG 0x080c // HSP_DBELL_8_PENDING_0
+#define HSP17_FIRST_REG 0x0824 // HSP_DBELL_8_ENABLE_SLICE1_0
+#define HSP17_LAST_REG 0x082c // HSP_DBELL_8_PENDING_SLICE1_0
+#define HSP18_FIRST_REG 0x0900 // HSP_DBELL_9_TRIGGER_0
+#define HSP18_LAST_REG 0x090c // HSP_DBELL_9_PENDING_0
+#define HSP19_FIRST_REG 0x0924 // HSP_DBELL_9_ENABLE_SLICE1_0
+#define HSP19_LAST_REG 0x092c // HSP_DBELL_9_PENDING_SLICE1_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARHSP_DBELL_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arhsp_int.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arhsp_int.h
new file mode 100644
index 0000000..644bcf1
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arhsp_int.h
@@ -0,0 +1,1193 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARHSP_INT_H_INC
+#define ARHSP_INT_H_INC
+#define NV_MOBILE_ARHSP_INT_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARHSP_INT_H_SCRREG_NOMENCLATURE INFERRED
+
+
+// Register HSP_INT_IE_0
+#define HSP_INT_IE_0                    MK_ADDR_CONST(0x100)
+#define HSP_INT_IE_0_SECURE                     0x0
+#define HSP_INT_IE_0_DUAL                       0x0
+#define HSP_INT_IE_0_SCR                        SCR_C0_REG_0
+#define HSP_INT_IE_0_SCRREG                     HSP_INT_SCR_SCR_C0_REG_0
+#define HSP_INT_IE_0_WORD_COUNT                         0x1
+#define HSP_INT_IE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_0_smp1_gnt_enable_SHIFT                      MK_SHIFT_CONST(30)
+#define HSP_INT_IE_0_smp1_gnt_enable_FIELD                      MK_FIELD_CONST(0x3, HSP_INT_IE_0_smp1_gnt_enable_SHIFT)
+#define HSP_INT_IE_0_smp1_gnt_enable_RANGE                      31:30
+#define HSP_INT_IE_0_smp1_gnt_enable_MSB                        MK_SHIFT_CONST(31)
+#define HSP_INT_IE_0_smp1_gnt_enable_LSB                        MK_SHIFT_CONST(30)
+#define HSP_INT_IE_0_smp1_gnt_enable_WOFFSET                    0x0
+#define HSP_INT_IE_0_smp1_gnt_enable_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_smp1_gnt_enable_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define HSP_INT_IE_0_smp1_gnt_enable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_smp1_gnt_enable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_smp1_gnt_enable_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_smp1_gnt_enable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_0_smp0_gnt_enable_SHIFT                      MK_SHIFT_CONST(28)
+#define HSP_INT_IE_0_smp0_gnt_enable_FIELD                      MK_FIELD_CONST(0x3, HSP_INT_IE_0_smp0_gnt_enable_SHIFT)
+#define HSP_INT_IE_0_smp0_gnt_enable_RANGE                      29:28
+#define HSP_INT_IE_0_smp0_gnt_enable_MSB                        MK_SHIFT_CONST(29)
+#define HSP_INT_IE_0_smp0_gnt_enable_LSB                        MK_SHIFT_CONST(28)
+#define HSP_INT_IE_0_smp0_gnt_enable_WOFFSET                    0x0
+#define HSP_INT_IE_0_smp0_gnt_enable_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_smp0_gnt_enable_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define HSP_INT_IE_0_smp0_gnt_enable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_smp0_gnt_enable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_smp0_gnt_enable_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_smp0_gnt_enable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_0_reserved_SHIFT                     MK_SHIFT_CONST(26)
+#define HSP_INT_IE_0_reserved_FIELD                     MK_FIELD_CONST(0x3, HSP_INT_IE_0_reserved_SHIFT)
+#define HSP_INT_IE_0_reserved_RANGE                     27:26
+#define HSP_INT_IE_0_reserved_MSB                       MK_SHIFT_CONST(27)
+#define HSP_INT_IE_0_reserved_LSB                       MK_SHIFT_CONST(26)
+#define HSP_INT_IE_0_reserved_WOFFSET                   0x0
+#define HSP_INT_IE_0_reserved_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_reserved_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define HSP_INT_IE_0_reserved_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_reserved_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_reserved_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_reserved_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_0_dbell_enable_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_INT_IE_0_dbell_enable_FIELD                 MK_FIELD_CONST(0x3ff, HSP_INT_IE_0_dbell_enable_SHIFT)
+#define HSP_INT_IE_0_dbell_enable_RANGE                 25:16
+#define HSP_INT_IE_0_dbell_enable_MSB                   MK_SHIFT_CONST(25)
+#define HSP_INT_IE_0_dbell_enable_LSB                   MK_SHIFT_CONST(16)
+#define HSP_INT_IE_0_dbell_enable_WOFFSET                       0x0
+#define HSP_INT_IE_0_dbell_enable_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_dbell_enable_DEFAULT_MASK                  MK_MASK_CONST(0x3ff)
+#define HSP_INT_IE_0_dbell_enable_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_dbell_enable_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_dbell_enable_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_dbell_enable_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_0_mbox_full_enable_SHIFT                     MK_SHIFT_CONST(8)
+#define HSP_INT_IE_0_mbox_full_enable_FIELD                     MK_FIELD_CONST(0xff, HSP_INT_IE_0_mbox_full_enable_SHIFT)
+#define HSP_INT_IE_0_mbox_full_enable_RANGE                     15:8
+#define HSP_INT_IE_0_mbox_full_enable_MSB                       MK_SHIFT_CONST(15)
+#define HSP_INT_IE_0_mbox_full_enable_LSB                       MK_SHIFT_CONST(8)
+#define HSP_INT_IE_0_mbox_full_enable_WOFFSET                   0x0
+#define HSP_INT_IE_0_mbox_full_enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_mbox_full_enable_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define HSP_INT_IE_0_mbox_full_enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_mbox_full_enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_mbox_full_enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_mbox_full_enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_0_mbox_empty_enable_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_INT_IE_0_mbox_empty_enable_FIELD                    MK_FIELD_CONST(0xff, HSP_INT_IE_0_mbox_empty_enable_SHIFT)
+#define HSP_INT_IE_0_mbox_empty_enable_RANGE                    7:0
+#define HSP_INT_IE_0_mbox_empty_enable_MSB                      MK_SHIFT_CONST(7)
+#define HSP_INT_IE_0_mbox_empty_enable_LSB                      MK_SHIFT_CONST(0)
+#define HSP_INT_IE_0_mbox_empty_enable_WOFFSET                  0x0
+#define HSP_INT_IE_0_mbox_empty_enable_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_mbox_empty_enable_DEFAULT_MASK                     MK_MASK_CONST(0xff)
+#define HSP_INT_IE_0_mbox_empty_enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_mbox_empty_enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_mbox_empty_enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_0_mbox_empty_enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_INT_IE
+#define HSP_INT_IE                      MK_ADDR_CONST(0x100)
+#define HSP_INT_IE_SECURE                       0x0
+#define HSP_INT_IE_DUAL                         0x0
+#define HSP_INT_IE_SCR                  SCR_C0_REG_0
+#define HSP_INT_IE_SCRREG                       HSP_INT_SCR_SCR_C0_REG_0
+#define HSP_INT_IE_WORD_COUNT                   0x1
+#define HSP_INT_IE_RESET_VAL                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_INT_IE_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_smp1_gnt_enable_SHIFT                        MK_SHIFT_CONST(30)
+#define HSP_INT_IE_smp1_gnt_enable_FIELD                        MK_FIELD_CONST(0x3, HSP_INT_IE_smp1_gnt_enable_SHIFT)
+#define HSP_INT_IE_smp1_gnt_enable_RANGE                        31:30
+#define HSP_INT_IE_smp1_gnt_enable_MSB                  MK_SHIFT_CONST(31)
+#define HSP_INT_IE_smp1_gnt_enable_LSB                  MK_SHIFT_CONST(30)
+#define HSP_INT_IE_smp1_gnt_enable_WOFFSET                      0x0
+#define HSP_INT_IE_smp1_gnt_enable_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_INT_IE_smp1_gnt_enable_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define HSP_INT_IE_smp1_gnt_enable_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_smp1_gnt_enable_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_INT_IE_smp1_gnt_enable_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_smp1_gnt_enable_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_smp0_gnt_enable_SHIFT                        MK_SHIFT_CONST(28)
+#define HSP_INT_IE_smp0_gnt_enable_FIELD                        MK_FIELD_CONST(0x3, HSP_INT_IE_smp0_gnt_enable_SHIFT)
+#define HSP_INT_IE_smp0_gnt_enable_RANGE                        29:28
+#define HSP_INT_IE_smp0_gnt_enable_MSB                  MK_SHIFT_CONST(29)
+#define HSP_INT_IE_smp0_gnt_enable_LSB                  MK_SHIFT_CONST(28)
+#define HSP_INT_IE_smp0_gnt_enable_WOFFSET                      0x0
+#define HSP_INT_IE_smp0_gnt_enable_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_INT_IE_smp0_gnt_enable_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define HSP_INT_IE_smp0_gnt_enable_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_smp0_gnt_enable_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_INT_IE_smp0_gnt_enable_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_smp0_gnt_enable_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_reserved_SHIFT                       MK_SHIFT_CONST(26)
+#define HSP_INT_IE_reserved_FIELD                       MK_FIELD_CONST(0x3, HSP_INT_IE_reserved_SHIFT)
+#define HSP_INT_IE_reserved_RANGE                       27:26
+#define HSP_INT_IE_reserved_MSB                 MK_SHIFT_CONST(27)
+#define HSP_INT_IE_reserved_LSB                 MK_SHIFT_CONST(26)
+#define HSP_INT_IE_reserved_WOFFSET                     0x0
+#define HSP_INT_IE_reserved_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_reserved_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define HSP_INT_IE_reserved_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_reserved_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_reserved_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_reserved_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_dbell_enable_SHIFT                   MK_SHIFT_CONST(16)
+#define HSP_INT_IE_dbell_enable_FIELD                   MK_FIELD_CONST(0x3ff, HSP_INT_IE_dbell_enable_SHIFT)
+#define HSP_INT_IE_dbell_enable_RANGE                   25:16
+#define HSP_INT_IE_dbell_enable_MSB                     MK_SHIFT_CONST(25)
+#define HSP_INT_IE_dbell_enable_LSB                     MK_SHIFT_CONST(16)
+#define HSP_INT_IE_dbell_enable_WOFFSET                 0x0
+#define HSP_INT_IE_dbell_enable_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_dbell_enable_DEFAULT_MASK                    MK_MASK_CONST(0x3ff)
+#define HSP_INT_IE_dbell_enable_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_INT_IE_dbell_enable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_dbell_enable_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_dbell_enable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_mbox_full_enable_SHIFT                       MK_SHIFT_CONST(8)
+#define HSP_INT_IE_mbox_full_enable_FIELD                       MK_FIELD_CONST(0xff, HSP_INT_IE_mbox_full_enable_SHIFT)
+#define HSP_INT_IE_mbox_full_enable_RANGE                       15:8
+#define HSP_INT_IE_mbox_full_enable_MSB                 MK_SHIFT_CONST(15)
+#define HSP_INT_IE_mbox_full_enable_LSB                 MK_SHIFT_CONST(8)
+#define HSP_INT_IE_mbox_full_enable_WOFFSET                     0x0
+#define HSP_INT_IE_mbox_full_enable_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_mbox_full_enable_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define HSP_INT_IE_mbox_full_enable_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_mbox_full_enable_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_mbox_full_enable_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_mbox_full_enable_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_mbox_empty_enable_SHIFT                      MK_SHIFT_CONST(0)
+#define HSP_INT_IE_mbox_empty_enable_FIELD                      MK_FIELD_CONST(0xff, HSP_INT_IE_mbox_empty_enable_SHIFT)
+#define HSP_INT_IE_mbox_empty_enable_RANGE                      7:0
+#define HSP_INT_IE_mbox_empty_enable_MSB                        MK_SHIFT_CONST(7)
+#define HSP_INT_IE_mbox_empty_enable_LSB                        MK_SHIFT_CONST(0)
+#define HSP_INT_IE_mbox_empty_enable_WOFFSET                    0x0
+#define HSP_INT_IE_mbox_empty_enable_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_mbox_empty_enable_DEFAULT_MASK                       MK_MASK_CONST(0xff)
+#define HSP_INT_IE_mbox_empty_enable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_mbox_empty_enable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_mbox_empty_enable_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_mbox_empty_enable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register HSP_INT_IE_1
+#define HSP_INT_IE_1                    MK_ADDR_CONST(0x104)
+#define HSP_INT_IE_1_SECURE                     0x0
+#define HSP_INT_IE_1_DUAL                       0x0
+#define HSP_INT_IE_1_SCR                        SCR_C0_REG_0
+#define HSP_INT_IE_1_SCRREG                     HSP_INT_SCR_SCR_C0_REG_0
+#define HSP_INT_IE_1_WORD_COUNT                         0x1
+#define HSP_INT_IE_1_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_1_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_1_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_1_smp1_gnt_enable_SHIFT                      MK_SHIFT_CONST(30)
+#define HSP_INT_IE_1_smp1_gnt_enable_FIELD                      MK_FIELD_CONST(0x3, HSP_INT_IE_1_smp1_gnt_enable_SHIFT)
+#define HSP_INT_IE_1_smp1_gnt_enable_RANGE                      31:30
+#define HSP_INT_IE_1_smp1_gnt_enable_MSB                        MK_SHIFT_CONST(31)
+#define HSP_INT_IE_1_smp1_gnt_enable_LSB                        MK_SHIFT_CONST(30)
+#define HSP_INT_IE_1_smp1_gnt_enable_WOFFSET                    0x0
+#define HSP_INT_IE_1_smp1_gnt_enable_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_smp1_gnt_enable_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define HSP_INT_IE_1_smp1_gnt_enable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_smp1_gnt_enable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_smp1_gnt_enable_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_smp1_gnt_enable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_1_smp0_gnt_enable_SHIFT                      MK_SHIFT_CONST(28)
+#define HSP_INT_IE_1_smp0_gnt_enable_FIELD                      MK_FIELD_CONST(0x3, HSP_INT_IE_1_smp0_gnt_enable_SHIFT)
+#define HSP_INT_IE_1_smp0_gnt_enable_RANGE                      29:28
+#define HSP_INT_IE_1_smp0_gnt_enable_MSB                        MK_SHIFT_CONST(29)
+#define HSP_INT_IE_1_smp0_gnt_enable_LSB                        MK_SHIFT_CONST(28)
+#define HSP_INT_IE_1_smp0_gnt_enable_WOFFSET                    0x0
+#define HSP_INT_IE_1_smp0_gnt_enable_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_smp0_gnt_enable_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define HSP_INT_IE_1_smp0_gnt_enable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_smp0_gnt_enable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_smp0_gnt_enable_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_smp0_gnt_enable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_1_reserved_SHIFT                     MK_SHIFT_CONST(26)
+#define HSP_INT_IE_1_reserved_FIELD                     MK_FIELD_CONST(0x3, HSP_INT_IE_1_reserved_SHIFT)
+#define HSP_INT_IE_1_reserved_RANGE                     27:26
+#define HSP_INT_IE_1_reserved_MSB                       MK_SHIFT_CONST(27)
+#define HSP_INT_IE_1_reserved_LSB                       MK_SHIFT_CONST(26)
+#define HSP_INT_IE_1_reserved_WOFFSET                   0x0
+#define HSP_INT_IE_1_reserved_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_reserved_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define HSP_INT_IE_1_reserved_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_reserved_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_reserved_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_reserved_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_1_dbell_enable_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_INT_IE_1_dbell_enable_FIELD                 MK_FIELD_CONST(0x3ff, HSP_INT_IE_1_dbell_enable_SHIFT)
+#define HSP_INT_IE_1_dbell_enable_RANGE                 25:16
+#define HSP_INT_IE_1_dbell_enable_MSB                   MK_SHIFT_CONST(25)
+#define HSP_INT_IE_1_dbell_enable_LSB                   MK_SHIFT_CONST(16)
+#define HSP_INT_IE_1_dbell_enable_WOFFSET                       0x0
+#define HSP_INT_IE_1_dbell_enable_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_dbell_enable_DEFAULT_MASK                  MK_MASK_CONST(0x3ff)
+#define HSP_INT_IE_1_dbell_enable_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_dbell_enable_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_dbell_enable_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_dbell_enable_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_1_mbox_full_enable_SHIFT                     MK_SHIFT_CONST(8)
+#define HSP_INT_IE_1_mbox_full_enable_FIELD                     MK_FIELD_CONST(0xff, HSP_INT_IE_1_mbox_full_enable_SHIFT)
+#define HSP_INT_IE_1_mbox_full_enable_RANGE                     15:8
+#define HSP_INT_IE_1_mbox_full_enable_MSB                       MK_SHIFT_CONST(15)
+#define HSP_INT_IE_1_mbox_full_enable_LSB                       MK_SHIFT_CONST(8)
+#define HSP_INT_IE_1_mbox_full_enable_WOFFSET                   0x0
+#define HSP_INT_IE_1_mbox_full_enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_mbox_full_enable_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define HSP_INT_IE_1_mbox_full_enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_mbox_full_enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_mbox_full_enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_mbox_full_enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_1_mbox_empty_enable_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_INT_IE_1_mbox_empty_enable_FIELD                    MK_FIELD_CONST(0xff, HSP_INT_IE_1_mbox_empty_enable_SHIFT)
+#define HSP_INT_IE_1_mbox_empty_enable_RANGE                    7:0
+#define HSP_INT_IE_1_mbox_empty_enable_MSB                      MK_SHIFT_CONST(7)
+#define HSP_INT_IE_1_mbox_empty_enable_LSB                      MK_SHIFT_CONST(0)
+#define HSP_INT_IE_1_mbox_empty_enable_WOFFSET                  0x0
+#define HSP_INT_IE_1_mbox_empty_enable_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_mbox_empty_enable_DEFAULT_MASK                     MK_MASK_CONST(0xff)
+#define HSP_INT_IE_1_mbox_empty_enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_mbox_empty_enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_mbox_empty_enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_1_mbox_empty_enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_INT_IE_2
+#define HSP_INT_IE_2                    MK_ADDR_CONST(0x108)
+#define HSP_INT_IE_2_SECURE                     0x0
+#define HSP_INT_IE_2_DUAL                       0x0
+#define HSP_INT_IE_2_SCR                        SCR_C0_REG_0
+#define HSP_INT_IE_2_SCRREG                     HSP_INT_SCR_SCR_C0_REG_0
+#define HSP_INT_IE_2_WORD_COUNT                         0x1
+#define HSP_INT_IE_2_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_2_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_2_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_2_smp1_gnt_enable_SHIFT                      MK_SHIFT_CONST(30)
+#define HSP_INT_IE_2_smp1_gnt_enable_FIELD                      MK_FIELD_CONST(0x3, HSP_INT_IE_2_smp1_gnt_enable_SHIFT)
+#define HSP_INT_IE_2_smp1_gnt_enable_RANGE                      31:30
+#define HSP_INT_IE_2_smp1_gnt_enable_MSB                        MK_SHIFT_CONST(31)
+#define HSP_INT_IE_2_smp1_gnt_enable_LSB                        MK_SHIFT_CONST(30)
+#define HSP_INT_IE_2_smp1_gnt_enable_WOFFSET                    0x0
+#define HSP_INT_IE_2_smp1_gnt_enable_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_smp1_gnt_enable_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define HSP_INT_IE_2_smp1_gnt_enable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_smp1_gnt_enable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_smp1_gnt_enable_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_smp1_gnt_enable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_2_smp0_gnt_enable_SHIFT                      MK_SHIFT_CONST(28)
+#define HSP_INT_IE_2_smp0_gnt_enable_FIELD                      MK_FIELD_CONST(0x3, HSP_INT_IE_2_smp0_gnt_enable_SHIFT)
+#define HSP_INT_IE_2_smp0_gnt_enable_RANGE                      29:28
+#define HSP_INT_IE_2_smp0_gnt_enable_MSB                        MK_SHIFT_CONST(29)
+#define HSP_INT_IE_2_smp0_gnt_enable_LSB                        MK_SHIFT_CONST(28)
+#define HSP_INT_IE_2_smp0_gnt_enable_WOFFSET                    0x0
+#define HSP_INT_IE_2_smp0_gnt_enable_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_smp0_gnt_enable_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define HSP_INT_IE_2_smp0_gnt_enable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_smp0_gnt_enable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_smp0_gnt_enable_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_smp0_gnt_enable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_2_reserved_SHIFT                     MK_SHIFT_CONST(26)
+#define HSP_INT_IE_2_reserved_FIELD                     MK_FIELD_CONST(0x3, HSP_INT_IE_2_reserved_SHIFT)
+#define HSP_INT_IE_2_reserved_RANGE                     27:26
+#define HSP_INT_IE_2_reserved_MSB                       MK_SHIFT_CONST(27)
+#define HSP_INT_IE_2_reserved_LSB                       MK_SHIFT_CONST(26)
+#define HSP_INT_IE_2_reserved_WOFFSET                   0x0
+#define HSP_INT_IE_2_reserved_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_reserved_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define HSP_INT_IE_2_reserved_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_reserved_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_reserved_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_reserved_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_2_dbell_enable_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_INT_IE_2_dbell_enable_FIELD                 MK_FIELD_CONST(0x3ff, HSP_INT_IE_2_dbell_enable_SHIFT)
+#define HSP_INT_IE_2_dbell_enable_RANGE                 25:16
+#define HSP_INT_IE_2_dbell_enable_MSB                   MK_SHIFT_CONST(25)
+#define HSP_INT_IE_2_dbell_enable_LSB                   MK_SHIFT_CONST(16)
+#define HSP_INT_IE_2_dbell_enable_WOFFSET                       0x0
+#define HSP_INT_IE_2_dbell_enable_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_dbell_enable_DEFAULT_MASK                  MK_MASK_CONST(0x3ff)
+#define HSP_INT_IE_2_dbell_enable_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_dbell_enable_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_dbell_enable_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_dbell_enable_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_2_mbox_full_enable_SHIFT                     MK_SHIFT_CONST(8)
+#define HSP_INT_IE_2_mbox_full_enable_FIELD                     MK_FIELD_CONST(0xff, HSP_INT_IE_2_mbox_full_enable_SHIFT)
+#define HSP_INT_IE_2_mbox_full_enable_RANGE                     15:8
+#define HSP_INT_IE_2_mbox_full_enable_MSB                       MK_SHIFT_CONST(15)
+#define HSP_INT_IE_2_mbox_full_enable_LSB                       MK_SHIFT_CONST(8)
+#define HSP_INT_IE_2_mbox_full_enable_WOFFSET                   0x0
+#define HSP_INT_IE_2_mbox_full_enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_mbox_full_enable_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define HSP_INT_IE_2_mbox_full_enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_mbox_full_enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_mbox_full_enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_mbox_full_enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_2_mbox_empty_enable_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_INT_IE_2_mbox_empty_enable_FIELD                    MK_FIELD_CONST(0xff, HSP_INT_IE_2_mbox_empty_enable_SHIFT)
+#define HSP_INT_IE_2_mbox_empty_enable_RANGE                    7:0
+#define HSP_INT_IE_2_mbox_empty_enable_MSB                      MK_SHIFT_CONST(7)
+#define HSP_INT_IE_2_mbox_empty_enable_LSB                      MK_SHIFT_CONST(0)
+#define HSP_INT_IE_2_mbox_empty_enable_WOFFSET                  0x0
+#define HSP_INT_IE_2_mbox_empty_enable_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_mbox_empty_enable_DEFAULT_MASK                     MK_MASK_CONST(0xff)
+#define HSP_INT_IE_2_mbox_empty_enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_mbox_empty_enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_mbox_empty_enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_2_mbox_empty_enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_INT_IE_3
+#define HSP_INT_IE_3                    MK_ADDR_CONST(0x10c)
+#define HSP_INT_IE_3_SECURE                     0x0
+#define HSP_INT_IE_3_DUAL                       0x0
+#define HSP_INT_IE_3_SCR                        SCR_C0_REG_0
+#define HSP_INT_IE_3_SCRREG                     HSP_INT_SCR_SCR_C0_REG_0
+#define HSP_INT_IE_3_WORD_COUNT                         0x1
+#define HSP_INT_IE_3_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_3_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_3_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_3_smp1_gnt_enable_SHIFT                      MK_SHIFT_CONST(30)
+#define HSP_INT_IE_3_smp1_gnt_enable_FIELD                      MK_FIELD_CONST(0x3, HSP_INT_IE_3_smp1_gnt_enable_SHIFT)
+#define HSP_INT_IE_3_smp1_gnt_enable_RANGE                      31:30
+#define HSP_INT_IE_3_smp1_gnt_enable_MSB                        MK_SHIFT_CONST(31)
+#define HSP_INT_IE_3_smp1_gnt_enable_LSB                        MK_SHIFT_CONST(30)
+#define HSP_INT_IE_3_smp1_gnt_enable_WOFFSET                    0x0
+#define HSP_INT_IE_3_smp1_gnt_enable_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_smp1_gnt_enable_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define HSP_INT_IE_3_smp1_gnt_enable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_smp1_gnt_enable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_smp1_gnt_enable_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_smp1_gnt_enable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_3_smp0_gnt_enable_SHIFT                      MK_SHIFT_CONST(28)
+#define HSP_INT_IE_3_smp0_gnt_enable_FIELD                      MK_FIELD_CONST(0x3, HSP_INT_IE_3_smp0_gnt_enable_SHIFT)
+#define HSP_INT_IE_3_smp0_gnt_enable_RANGE                      29:28
+#define HSP_INT_IE_3_smp0_gnt_enable_MSB                        MK_SHIFT_CONST(29)
+#define HSP_INT_IE_3_smp0_gnt_enable_LSB                        MK_SHIFT_CONST(28)
+#define HSP_INT_IE_3_smp0_gnt_enable_WOFFSET                    0x0
+#define HSP_INT_IE_3_smp0_gnt_enable_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_smp0_gnt_enable_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define HSP_INT_IE_3_smp0_gnt_enable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_smp0_gnt_enable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_smp0_gnt_enable_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_smp0_gnt_enable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_3_reserved_SHIFT                     MK_SHIFT_CONST(26)
+#define HSP_INT_IE_3_reserved_FIELD                     MK_FIELD_CONST(0x3, HSP_INT_IE_3_reserved_SHIFT)
+#define HSP_INT_IE_3_reserved_RANGE                     27:26
+#define HSP_INT_IE_3_reserved_MSB                       MK_SHIFT_CONST(27)
+#define HSP_INT_IE_3_reserved_LSB                       MK_SHIFT_CONST(26)
+#define HSP_INT_IE_3_reserved_WOFFSET                   0x0
+#define HSP_INT_IE_3_reserved_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_reserved_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define HSP_INT_IE_3_reserved_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_reserved_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_reserved_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_reserved_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_3_dbell_enable_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_INT_IE_3_dbell_enable_FIELD                 MK_FIELD_CONST(0x3ff, HSP_INT_IE_3_dbell_enable_SHIFT)
+#define HSP_INT_IE_3_dbell_enable_RANGE                 25:16
+#define HSP_INT_IE_3_dbell_enable_MSB                   MK_SHIFT_CONST(25)
+#define HSP_INT_IE_3_dbell_enable_LSB                   MK_SHIFT_CONST(16)
+#define HSP_INT_IE_3_dbell_enable_WOFFSET                       0x0
+#define HSP_INT_IE_3_dbell_enable_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_dbell_enable_DEFAULT_MASK                  MK_MASK_CONST(0x3ff)
+#define HSP_INT_IE_3_dbell_enable_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_dbell_enable_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_dbell_enable_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_dbell_enable_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_3_mbox_full_enable_SHIFT                     MK_SHIFT_CONST(8)
+#define HSP_INT_IE_3_mbox_full_enable_FIELD                     MK_FIELD_CONST(0xff, HSP_INT_IE_3_mbox_full_enable_SHIFT)
+#define HSP_INT_IE_3_mbox_full_enable_RANGE                     15:8
+#define HSP_INT_IE_3_mbox_full_enable_MSB                       MK_SHIFT_CONST(15)
+#define HSP_INT_IE_3_mbox_full_enable_LSB                       MK_SHIFT_CONST(8)
+#define HSP_INT_IE_3_mbox_full_enable_WOFFSET                   0x0
+#define HSP_INT_IE_3_mbox_full_enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_mbox_full_enable_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define HSP_INT_IE_3_mbox_full_enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_mbox_full_enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_mbox_full_enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_mbox_full_enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_3_mbox_empty_enable_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_INT_IE_3_mbox_empty_enable_FIELD                    MK_FIELD_CONST(0xff, HSP_INT_IE_3_mbox_empty_enable_SHIFT)
+#define HSP_INT_IE_3_mbox_empty_enable_RANGE                    7:0
+#define HSP_INT_IE_3_mbox_empty_enable_MSB                      MK_SHIFT_CONST(7)
+#define HSP_INT_IE_3_mbox_empty_enable_LSB                      MK_SHIFT_CONST(0)
+#define HSP_INT_IE_3_mbox_empty_enable_WOFFSET                  0x0
+#define HSP_INT_IE_3_mbox_empty_enable_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_mbox_empty_enable_DEFAULT_MASK                     MK_MASK_CONST(0xff)
+#define HSP_INT_IE_3_mbox_empty_enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_mbox_empty_enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_mbox_empty_enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_3_mbox_empty_enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_INT_IE_4
+#define HSP_INT_IE_4                    MK_ADDR_CONST(0x110)
+#define HSP_INT_IE_4_SECURE                     0x0
+#define HSP_INT_IE_4_DUAL                       0x0
+#define HSP_INT_IE_4_SCR                        SCR_C0_REG_0
+#define HSP_INT_IE_4_SCRREG                     HSP_INT_SCR_SCR_C0_REG_0
+#define HSP_INT_IE_4_WORD_COUNT                         0x1
+#define HSP_INT_IE_4_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_4_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_4_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_4_smp1_gnt_enable_SHIFT                      MK_SHIFT_CONST(30)
+#define HSP_INT_IE_4_smp1_gnt_enable_FIELD                      MK_FIELD_CONST(0x3, HSP_INT_IE_4_smp1_gnt_enable_SHIFT)
+#define HSP_INT_IE_4_smp1_gnt_enable_RANGE                      31:30
+#define HSP_INT_IE_4_smp1_gnt_enable_MSB                        MK_SHIFT_CONST(31)
+#define HSP_INT_IE_4_smp1_gnt_enable_LSB                        MK_SHIFT_CONST(30)
+#define HSP_INT_IE_4_smp1_gnt_enable_WOFFSET                    0x0
+#define HSP_INT_IE_4_smp1_gnt_enable_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_smp1_gnt_enable_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define HSP_INT_IE_4_smp1_gnt_enable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_smp1_gnt_enable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_smp1_gnt_enable_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_smp1_gnt_enable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_4_smp0_gnt_enable_SHIFT                      MK_SHIFT_CONST(28)
+#define HSP_INT_IE_4_smp0_gnt_enable_FIELD                      MK_FIELD_CONST(0x3, HSP_INT_IE_4_smp0_gnt_enable_SHIFT)
+#define HSP_INT_IE_4_smp0_gnt_enable_RANGE                      29:28
+#define HSP_INT_IE_4_smp0_gnt_enable_MSB                        MK_SHIFT_CONST(29)
+#define HSP_INT_IE_4_smp0_gnt_enable_LSB                        MK_SHIFT_CONST(28)
+#define HSP_INT_IE_4_smp0_gnt_enable_WOFFSET                    0x0
+#define HSP_INT_IE_4_smp0_gnt_enable_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_smp0_gnt_enable_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define HSP_INT_IE_4_smp0_gnt_enable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_smp0_gnt_enable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_smp0_gnt_enable_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_smp0_gnt_enable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_4_reserved_SHIFT                     MK_SHIFT_CONST(26)
+#define HSP_INT_IE_4_reserved_FIELD                     MK_FIELD_CONST(0x3, HSP_INT_IE_4_reserved_SHIFT)
+#define HSP_INT_IE_4_reserved_RANGE                     27:26
+#define HSP_INT_IE_4_reserved_MSB                       MK_SHIFT_CONST(27)
+#define HSP_INT_IE_4_reserved_LSB                       MK_SHIFT_CONST(26)
+#define HSP_INT_IE_4_reserved_WOFFSET                   0x0
+#define HSP_INT_IE_4_reserved_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_reserved_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define HSP_INT_IE_4_reserved_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_reserved_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_reserved_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_reserved_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_4_dbell_enable_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_INT_IE_4_dbell_enable_FIELD                 MK_FIELD_CONST(0x3ff, HSP_INT_IE_4_dbell_enable_SHIFT)
+#define HSP_INT_IE_4_dbell_enable_RANGE                 25:16
+#define HSP_INT_IE_4_dbell_enable_MSB                   MK_SHIFT_CONST(25)
+#define HSP_INT_IE_4_dbell_enable_LSB                   MK_SHIFT_CONST(16)
+#define HSP_INT_IE_4_dbell_enable_WOFFSET                       0x0
+#define HSP_INT_IE_4_dbell_enable_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_dbell_enable_DEFAULT_MASK                  MK_MASK_CONST(0x3ff)
+#define HSP_INT_IE_4_dbell_enable_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_dbell_enable_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_dbell_enable_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_dbell_enable_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_4_mbox_full_enable_SHIFT                     MK_SHIFT_CONST(8)
+#define HSP_INT_IE_4_mbox_full_enable_FIELD                     MK_FIELD_CONST(0xff, HSP_INT_IE_4_mbox_full_enable_SHIFT)
+#define HSP_INT_IE_4_mbox_full_enable_RANGE                     15:8
+#define HSP_INT_IE_4_mbox_full_enable_MSB                       MK_SHIFT_CONST(15)
+#define HSP_INT_IE_4_mbox_full_enable_LSB                       MK_SHIFT_CONST(8)
+#define HSP_INT_IE_4_mbox_full_enable_WOFFSET                   0x0
+#define HSP_INT_IE_4_mbox_full_enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_mbox_full_enable_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define HSP_INT_IE_4_mbox_full_enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_mbox_full_enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_mbox_full_enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_mbox_full_enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_4_mbox_empty_enable_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_INT_IE_4_mbox_empty_enable_FIELD                    MK_FIELD_CONST(0xff, HSP_INT_IE_4_mbox_empty_enable_SHIFT)
+#define HSP_INT_IE_4_mbox_empty_enable_RANGE                    7:0
+#define HSP_INT_IE_4_mbox_empty_enable_MSB                      MK_SHIFT_CONST(7)
+#define HSP_INT_IE_4_mbox_empty_enable_LSB                      MK_SHIFT_CONST(0)
+#define HSP_INT_IE_4_mbox_empty_enable_WOFFSET                  0x0
+#define HSP_INT_IE_4_mbox_empty_enable_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_mbox_empty_enable_DEFAULT_MASK                     MK_MASK_CONST(0xff)
+#define HSP_INT_IE_4_mbox_empty_enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_mbox_empty_enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_mbox_empty_enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_4_mbox_empty_enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_INT_IE_5
+#define HSP_INT_IE_5                    MK_ADDR_CONST(0x114)
+#define HSP_INT_IE_5_SECURE                     0x0
+#define HSP_INT_IE_5_DUAL                       0x0
+#define HSP_INT_IE_5_SCR                        SCR_C0_REG_0
+#define HSP_INT_IE_5_SCRREG                     HSP_INT_SCR_SCR_C0_REG_0
+#define HSP_INT_IE_5_WORD_COUNT                         0x1
+#define HSP_INT_IE_5_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_5_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_5_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_5_smp1_gnt_enable_SHIFT                      MK_SHIFT_CONST(30)
+#define HSP_INT_IE_5_smp1_gnt_enable_FIELD                      MK_FIELD_CONST(0x3, HSP_INT_IE_5_smp1_gnt_enable_SHIFT)
+#define HSP_INT_IE_5_smp1_gnt_enable_RANGE                      31:30
+#define HSP_INT_IE_5_smp1_gnt_enable_MSB                        MK_SHIFT_CONST(31)
+#define HSP_INT_IE_5_smp1_gnt_enable_LSB                        MK_SHIFT_CONST(30)
+#define HSP_INT_IE_5_smp1_gnt_enable_WOFFSET                    0x0
+#define HSP_INT_IE_5_smp1_gnt_enable_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_smp1_gnt_enable_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define HSP_INT_IE_5_smp1_gnt_enable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_smp1_gnt_enable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_smp1_gnt_enable_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_smp1_gnt_enable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_5_smp0_gnt_enable_SHIFT                      MK_SHIFT_CONST(28)
+#define HSP_INT_IE_5_smp0_gnt_enable_FIELD                      MK_FIELD_CONST(0x3, HSP_INT_IE_5_smp0_gnt_enable_SHIFT)
+#define HSP_INT_IE_5_smp0_gnt_enable_RANGE                      29:28
+#define HSP_INT_IE_5_smp0_gnt_enable_MSB                        MK_SHIFT_CONST(29)
+#define HSP_INT_IE_5_smp0_gnt_enable_LSB                        MK_SHIFT_CONST(28)
+#define HSP_INT_IE_5_smp0_gnt_enable_WOFFSET                    0x0
+#define HSP_INT_IE_5_smp0_gnt_enable_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_smp0_gnt_enable_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define HSP_INT_IE_5_smp0_gnt_enable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_smp0_gnt_enable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_smp0_gnt_enable_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_smp0_gnt_enable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_5_reserved_SHIFT                     MK_SHIFT_CONST(26)
+#define HSP_INT_IE_5_reserved_FIELD                     MK_FIELD_CONST(0x3, HSP_INT_IE_5_reserved_SHIFT)
+#define HSP_INT_IE_5_reserved_RANGE                     27:26
+#define HSP_INT_IE_5_reserved_MSB                       MK_SHIFT_CONST(27)
+#define HSP_INT_IE_5_reserved_LSB                       MK_SHIFT_CONST(26)
+#define HSP_INT_IE_5_reserved_WOFFSET                   0x0
+#define HSP_INT_IE_5_reserved_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_reserved_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define HSP_INT_IE_5_reserved_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_reserved_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_reserved_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_reserved_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_5_dbell_enable_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_INT_IE_5_dbell_enable_FIELD                 MK_FIELD_CONST(0x3ff, HSP_INT_IE_5_dbell_enable_SHIFT)
+#define HSP_INT_IE_5_dbell_enable_RANGE                 25:16
+#define HSP_INT_IE_5_dbell_enable_MSB                   MK_SHIFT_CONST(25)
+#define HSP_INT_IE_5_dbell_enable_LSB                   MK_SHIFT_CONST(16)
+#define HSP_INT_IE_5_dbell_enable_WOFFSET                       0x0
+#define HSP_INT_IE_5_dbell_enable_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_dbell_enable_DEFAULT_MASK                  MK_MASK_CONST(0x3ff)
+#define HSP_INT_IE_5_dbell_enable_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_dbell_enable_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_dbell_enable_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_dbell_enable_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_5_mbox_full_enable_SHIFT                     MK_SHIFT_CONST(8)
+#define HSP_INT_IE_5_mbox_full_enable_FIELD                     MK_FIELD_CONST(0xff, HSP_INT_IE_5_mbox_full_enable_SHIFT)
+#define HSP_INT_IE_5_mbox_full_enable_RANGE                     15:8
+#define HSP_INT_IE_5_mbox_full_enable_MSB                       MK_SHIFT_CONST(15)
+#define HSP_INT_IE_5_mbox_full_enable_LSB                       MK_SHIFT_CONST(8)
+#define HSP_INT_IE_5_mbox_full_enable_WOFFSET                   0x0
+#define HSP_INT_IE_5_mbox_full_enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_mbox_full_enable_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define HSP_INT_IE_5_mbox_full_enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_mbox_full_enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_mbox_full_enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_mbox_full_enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_5_mbox_empty_enable_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_INT_IE_5_mbox_empty_enable_FIELD                    MK_FIELD_CONST(0xff, HSP_INT_IE_5_mbox_empty_enable_SHIFT)
+#define HSP_INT_IE_5_mbox_empty_enable_RANGE                    7:0
+#define HSP_INT_IE_5_mbox_empty_enable_MSB                      MK_SHIFT_CONST(7)
+#define HSP_INT_IE_5_mbox_empty_enable_LSB                      MK_SHIFT_CONST(0)
+#define HSP_INT_IE_5_mbox_empty_enable_WOFFSET                  0x0
+#define HSP_INT_IE_5_mbox_empty_enable_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_mbox_empty_enable_DEFAULT_MASK                     MK_MASK_CONST(0xff)
+#define HSP_INT_IE_5_mbox_empty_enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_mbox_empty_enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_mbox_empty_enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_5_mbox_empty_enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_INT_IE_6
+#define HSP_INT_IE_6                    MK_ADDR_CONST(0x118)
+#define HSP_INT_IE_6_SECURE                     0x0
+#define HSP_INT_IE_6_DUAL                       0x0
+#define HSP_INT_IE_6_SCR                        SCR_C0_REG_0
+#define HSP_INT_IE_6_SCRREG                     HSP_INT_SCR_SCR_C0_REG_0
+#define HSP_INT_IE_6_WORD_COUNT                         0x1
+#define HSP_INT_IE_6_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_6_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_6_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_6_smp1_gnt_enable_SHIFT                      MK_SHIFT_CONST(30)
+#define HSP_INT_IE_6_smp1_gnt_enable_FIELD                      MK_FIELD_CONST(0x3, HSP_INT_IE_6_smp1_gnt_enable_SHIFT)
+#define HSP_INT_IE_6_smp1_gnt_enable_RANGE                      31:30
+#define HSP_INT_IE_6_smp1_gnt_enable_MSB                        MK_SHIFT_CONST(31)
+#define HSP_INT_IE_6_smp1_gnt_enable_LSB                        MK_SHIFT_CONST(30)
+#define HSP_INT_IE_6_smp1_gnt_enable_WOFFSET                    0x0
+#define HSP_INT_IE_6_smp1_gnt_enable_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_smp1_gnt_enable_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define HSP_INT_IE_6_smp1_gnt_enable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_smp1_gnt_enable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_smp1_gnt_enable_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_smp1_gnt_enable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_6_smp0_gnt_enable_SHIFT                      MK_SHIFT_CONST(28)
+#define HSP_INT_IE_6_smp0_gnt_enable_FIELD                      MK_FIELD_CONST(0x3, HSP_INT_IE_6_smp0_gnt_enable_SHIFT)
+#define HSP_INT_IE_6_smp0_gnt_enable_RANGE                      29:28
+#define HSP_INT_IE_6_smp0_gnt_enable_MSB                        MK_SHIFT_CONST(29)
+#define HSP_INT_IE_6_smp0_gnt_enable_LSB                        MK_SHIFT_CONST(28)
+#define HSP_INT_IE_6_smp0_gnt_enable_WOFFSET                    0x0
+#define HSP_INT_IE_6_smp0_gnt_enable_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_smp0_gnt_enable_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define HSP_INT_IE_6_smp0_gnt_enable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_smp0_gnt_enable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_smp0_gnt_enable_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_smp0_gnt_enable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_6_reserved_SHIFT                     MK_SHIFT_CONST(26)
+#define HSP_INT_IE_6_reserved_FIELD                     MK_FIELD_CONST(0x3, HSP_INT_IE_6_reserved_SHIFT)
+#define HSP_INT_IE_6_reserved_RANGE                     27:26
+#define HSP_INT_IE_6_reserved_MSB                       MK_SHIFT_CONST(27)
+#define HSP_INT_IE_6_reserved_LSB                       MK_SHIFT_CONST(26)
+#define HSP_INT_IE_6_reserved_WOFFSET                   0x0
+#define HSP_INT_IE_6_reserved_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_reserved_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define HSP_INT_IE_6_reserved_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_reserved_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_reserved_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_reserved_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_6_dbell_enable_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_INT_IE_6_dbell_enable_FIELD                 MK_FIELD_CONST(0x3ff, HSP_INT_IE_6_dbell_enable_SHIFT)
+#define HSP_INT_IE_6_dbell_enable_RANGE                 25:16
+#define HSP_INT_IE_6_dbell_enable_MSB                   MK_SHIFT_CONST(25)
+#define HSP_INT_IE_6_dbell_enable_LSB                   MK_SHIFT_CONST(16)
+#define HSP_INT_IE_6_dbell_enable_WOFFSET                       0x0
+#define HSP_INT_IE_6_dbell_enable_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_dbell_enable_DEFAULT_MASK                  MK_MASK_CONST(0x3ff)
+#define HSP_INT_IE_6_dbell_enable_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_dbell_enable_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_dbell_enable_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_dbell_enable_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_6_mbox_full_enable_SHIFT                     MK_SHIFT_CONST(8)
+#define HSP_INT_IE_6_mbox_full_enable_FIELD                     MK_FIELD_CONST(0xff, HSP_INT_IE_6_mbox_full_enable_SHIFT)
+#define HSP_INT_IE_6_mbox_full_enable_RANGE                     15:8
+#define HSP_INT_IE_6_mbox_full_enable_MSB                       MK_SHIFT_CONST(15)
+#define HSP_INT_IE_6_mbox_full_enable_LSB                       MK_SHIFT_CONST(8)
+#define HSP_INT_IE_6_mbox_full_enable_WOFFSET                   0x0
+#define HSP_INT_IE_6_mbox_full_enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_mbox_full_enable_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define HSP_INT_IE_6_mbox_full_enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_mbox_full_enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_mbox_full_enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_mbox_full_enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_6_mbox_empty_enable_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_INT_IE_6_mbox_empty_enable_FIELD                    MK_FIELD_CONST(0xff, HSP_INT_IE_6_mbox_empty_enable_SHIFT)
+#define HSP_INT_IE_6_mbox_empty_enable_RANGE                    7:0
+#define HSP_INT_IE_6_mbox_empty_enable_MSB                      MK_SHIFT_CONST(7)
+#define HSP_INT_IE_6_mbox_empty_enable_LSB                      MK_SHIFT_CONST(0)
+#define HSP_INT_IE_6_mbox_empty_enable_WOFFSET                  0x0
+#define HSP_INT_IE_6_mbox_empty_enable_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_mbox_empty_enable_DEFAULT_MASK                     MK_MASK_CONST(0xff)
+#define HSP_INT_IE_6_mbox_empty_enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_mbox_empty_enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_mbox_empty_enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_6_mbox_empty_enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_INT_IE_7
+#define HSP_INT_IE_7                    MK_ADDR_CONST(0x11c)
+#define HSP_INT_IE_7_SECURE                     0x0
+#define HSP_INT_IE_7_DUAL                       0x0
+#define HSP_INT_IE_7_SCR                        SCR_C0_REG_0
+#define HSP_INT_IE_7_SCRREG                     HSP_INT_SCR_SCR_C0_REG_0
+#define HSP_INT_IE_7_WORD_COUNT                         0x1
+#define HSP_INT_IE_7_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_7_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_7_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IE_7_smp1_gnt_enable_SHIFT                      MK_SHIFT_CONST(30)
+#define HSP_INT_IE_7_smp1_gnt_enable_FIELD                      MK_FIELD_CONST(0x3, HSP_INT_IE_7_smp1_gnt_enable_SHIFT)
+#define HSP_INT_IE_7_smp1_gnt_enable_RANGE                      31:30
+#define HSP_INT_IE_7_smp1_gnt_enable_MSB                        MK_SHIFT_CONST(31)
+#define HSP_INT_IE_7_smp1_gnt_enable_LSB                        MK_SHIFT_CONST(30)
+#define HSP_INT_IE_7_smp1_gnt_enable_WOFFSET                    0x0
+#define HSP_INT_IE_7_smp1_gnt_enable_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_smp1_gnt_enable_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define HSP_INT_IE_7_smp1_gnt_enable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_smp1_gnt_enable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_smp1_gnt_enable_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_smp1_gnt_enable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_7_smp0_gnt_enable_SHIFT                      MK_SHIFT_CONST(28)
+#define HSP_INT_IE_7_smp0_gnt_enable_FIELD                      MK_FIELD_CONST(0x3, HSP_INT_IE_7_smp0_gnt_enable_SHIFT)
+#define HSP_INT_IE_7_smp0_gnt_enable_RANGE                      29:28
+#define HSP_INT_IE_7_smp0_gnt_enable_MSB                        MK_SHIFT_CONST(29)
+#define HSP_INT_IE_7_smp0_gnt_enable_LSB                        MK_SHIFT_CONST(28)
+#define HSP_INT_IE_7_smp0_gnt_enable_WOFFSET                    0x0
+#define HSP_INT_IE_7_smp0_gnt_enable_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_smp0_gnt_enable_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define HSP_INT_IE_7_smp0_gnt_enable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_smp0_gnt_enable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_smp0_gnt_enable_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_smp0_gnt_enable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_7_reserved_SHIFT                     MK_SHIFT_CONST(26)
+#define HSP_INT_IE_7_reserved_FIELD                     MK_FIELD_CONST(0x3, HSP_INT_IE_7_reserved_SHIFT)
+#define HSP_INT_IE_7_reserved_RANGE                     27:26
+#define HSP_INT_IE_7_reserved_MSB                       MK_SHIFT_CONST(27)
+#define HSP_INT_IE_7_reserved_LSB                       MK_SHIFT_CONST(26)
+#define HSP_INT_IE_7_reserved_WOFFSET                   0x0
+#define HSP_INT_IE_7_reserved_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_reserved_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define HSP_INT_IE_7_reserved_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_reserved_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_reserved_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_reserved_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_7_dbell_enable_SHIFT                 MK_SHIFT_CONST(16)
+#define HSP_INT_IE_7_dbell_enable_FIELD                 MK_FIELD_CONST(0x3ff, HSP_INT_IE_7_dbell_enable_SHIFT)
+#define HSP_INT_IE_7_dbell_enable_RANGE                 25:16
+#define HSP_INT_IE_7_dbell_enable_MSB                   MK_SHIFT_CONST(25)
+#define HSP_INT_IE_7_dbell_enable_LSB                   MK_SHIFT_CONST(16)
+#define HSP_INT_IE_7_dbell_enable_WOFFSET                       0x0
+#define HSP_INT_IE_7_dbell_enable_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_dbell_enable_DEFAULT_MASK                  MK_MASK_CONST(0x3ff)
+#define HSP_INT_IE_7_dbell_enable_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_dbell_enable_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_dbell_enable_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_dbell_enable_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_7_mbox_full_enable_SHIFT                     MK_SHIFT_CONST(8)
+#define HSP_INT_IE_7_mbox_full_enable_FIELD                     MK_FIELD_CONST(0xff, HSP_INT_IE_7_mbox_full_enable_SHIFT)
+#define HSP_INT_IE_7_mbox_full_enable_RANGE                     15:8
+#define HSP_INT_IE_7_mbox_full_enable_MSB                       MK_SHIFT_CONST(15)
+#define HSP_INT_IE_7_mbox_full_enable_LSB                       MK_SHIFT_CONST(8)
+#define HSP_INT_IE_7_mbox_full_enable_WOFFSET                   0x0
+#define HSP_INT_IE_7_mbox_full_enable_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_mbox_full_enable_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define HSP_INT_IE_7_mbox_full_enable_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_mbox_full_enable_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_mbox_full_enable_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_mbox_full_enable_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_INT_IE_7_mbox_empty_enable_SHIFT                    MK_SHIFT_CONST(0)
+#define HSP_INT_IE_7_mbox_empty_enable_FIELD                    MK_FIELD_CONST(0xff, HSP_INT_IE_7_mbox_empty_enable_SHIFT)
+#define HSP_INT_IE_7_mbox_empty_enable_RANGE                    7:0
+#define HSP_INT_IE_7_mbox_empty_enable_MSB                      MK_SHIFT_CONST(7)
+#define HSP_INT_IE_7_mbox_empty_enable_LSB                      MK_SHIFT_CONST(0)
+#define HSP_INT_IE_7_mbox_empty_enable_WOFFSET                  0x0
+#define HSP_INT_IE_7_mbox_empty_enable_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_mbox_empty_enable_DEFAULT_MASK                     MK_MASK_CONST(0xff)
+#define HSP_INT_IE_7_mbox_empty_enable_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_mbox_empty_enable_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_mbox_empty_enable_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_INT_IE_7_mbox_empty_enable_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register HSP_INT_IV_0
+#define HSP_INT_IV_0                    MK_ADDR_CONST(0x300)
+#define HSP_INT_IV_0_SECURE                     0x0
+#define HSP_INT_IV_0_DUAL                       0x0
+#define HSP_INT_IV_0_SCR                        SCR_C0_REG_0
+#define HSP_INT_IV_0_SCRREG                     HSP_INT_SCR_SCR_C0_REG_0
+#define HSP_INT_IV_0_WORD_COUNT                         0x1
+#define HSP_INT_IV_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_INT_IV_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IV_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_INT_IV_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IV_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IV_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define HSP_INT_IV_0_Valid_SHIFT                        MK_SHIFT_CONST(0)
+#define HSP_INT_IV_0_Valid_FIELD                        MK_FIELD_CONST(0xffffffff, HSP_INT_IV_0_Valid_SHIFT)
+#define HSP_INT_IV_0_Valid_RANGE                        31:0
+#define HSP_INT_IV_0_Valid_MSB                  MK_SHIFT_CONST(31)
+#define HSP_INT_IV_0_Valid_LSB                  MK_SHIFT_CONST(0)
+#define HSP_INT_IV_0_Valid_WOFFSET                      0x0
+#define HSP_INT_IV_0_Valid_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_INT_IV_0_Valid_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IV_0_Valid_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IV_0_Valid_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_INT_IV_0_Valid_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_INT_IV_0_Valid_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register HSP_INT_IR_0
+#define HSP_INT_IR_0                    MK_ADDR_CONST(0x304)
+#define HSP_INT_IR_0_SECURE                     0x0
+#define HSP_INT_IR_0_DUAL                       0x0
+#define HSP_INT_IR_0_SCR                        SCR_C0_REG_0
+#define HSP_INT_IR_0_SCRREG                     HSP_INT_SCR_SCR_C0_REG_0
+#define HSP_INT_IR_0_WORD_COUNT                         0x1
+#define HSP_INT_IR_0_RESET_VAL                  MK_MASK_CONST(0xff)
+#define HSP_INT_IR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_INT_IR_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_smp1_gnt_asserted_SHIFT                    MK_SHIFT_CONST(30)
+#define HSP_INT_IR_0_smp1_gnt_asserted_FIELD                    MK_FIELD_CONST(0x3, HSP_INT_IR_0_smp1_gnt_asserted_SHIFT)
+#define HSP_INT_IR_0_smp1_gnt_asserted_RANGE                    31:30
+#define HSP_INT_IR_0_smp1_gnt_asserted_MSB                      MK_SHIFT_CONST(31)
+#define HSP_INT_IR_0_smp1_gnt_asserted_LSB                      MK_SHIFT_CONST(30)
+#define HSP_INT_IR_0_smp1_gnt_asserted_WOFFSET                  0x0
+#define HSP_INT_IR_0_smp1_gnt_asserted_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_smp1_gnt_asserted_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define HSP_INT_IR_0_smp1_gnt_asserted_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_smp1_gnt_asserted_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_smp1_gnt_asserted_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_smp1_gnt_asserted_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_INT_IR_0_smp0_gnt_asserted_SHIFT                    MK_SHIFT_CONST(28)
+#define HSP_INT_IR_0_smp0_gnt_asserted_FIELD                    MK_FIELD_CONST(0x3, HSP_INT_IR_0_smp0_gnt_asserted_SHIFT)
+#define HSP_INT_IR_0_smp0_gnt_asserted_RANGE                    29:28
+#define HSP_INT_IR_0_smp0_gnt_asserted_MSB                      MK_SHIFT_CONST(29)
+#define HSP_INT_IR_0_smp0_gnt_asserted_LSB                      MK_SHIFT_CONST(28)
+#define HSP_INT_IR_0_smp0_gnt_asserted_WOFFSET                  0x0
+#define HSP_INT_IR_0_smp0_gnt_asserted_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_smp0_gnt_asserted_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define HSP_INT_IR_0_smp0_gnt_asserted_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_smp0_gnt_asserted_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_smp0_gnt_asserted_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_smp0_gnt_asserted_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_INT_IR_0_reserved_SHIFT                     MK_SHIFT_CONST(26)
+#define HSP_INT_IR_0_reserved_FIELD                     MK_FIELD_CONST(0x3, HSP_INT_IR_0_reserved_SHIFT)
+#define HSP_INT_IR_0_reserved_RANGE                     27:26
+#define HSP_INT_IR_0_reserved_MSB                       MK_SHIFT_CONST(27)
+#define HSP_INT_IR_0_reserved_LSB                       MK_SHIFT_CONST(26)
+#define HSP_INT_IR_0_reserved_WOFFSET                   0x0
+#define HSP_INT_IR_0_reserved_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_reserved_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define HSP_INT_IR_0_reserved_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_reserved_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_reserved_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_reserved_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define HSP_INT_IR_0_dbell_asserted_SHIFT                       MK_SHIFT_CONST(16)
+#define HSP_INT_IR_0_dbell_asserted_FIELD                       MK_FIELD_CONST(0x3ff, HSP_INT_IR_0_dbell_asserted_SHIFT)
+#define HSP_INT_IR_0_dbell_asserted_RANGE                       25:16
+#define HSP_INT_IR_0_dbell_asserted_MSB                 MK_SHIFT_CONST(25)
+#define HSP_INT_IR_0_dbell_asserted_LSB                 MK_SHIFT_CONST(16)
+#define HSP_INT_IR_0_dbell_asserted_WOFFSET                     0x0
+#define HSP_INT_IR_0_dbell_asserted_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_dbell_asserted_DEFAULT_MASK                        MK_MASK_CONST(0x3ff)
+#define HSP_INT_IR_0_dbell_asserted_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_dbell_asserted_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_dbell_asserted_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_dbell_asserted_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define HSP_INT_IR_0_mbox_full_asserted_SHIFT                   MK_SHIFT_CONST(8)
+#define HSP_INT_IR_0_mbox_full_asserted_FIELD                   MK_FIELD_CONST(0xff, HSP_INT_IR_0_mbox_full_asserted_SHIFT)
+#define HSP_INT_IR_0_mbox_full_asserted_RANGE                   15:8
+#define HSP_INT_IR_0_mbox_full_asserted_MSB                     MK_SHIFT_CONST(15)
+#define HSP_INT_IR_0_mbox_full_asserted_LSB                     MK_SHIFT_CONST(8)
+#define HSP_INT_IR_0_mbox_full_asserted_WOFFSET                 0x0
+#define HSP_INT_IR_0_mbox_full_asserted_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_mbox_full_asserted_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define HSP_INT_IR_0_mbox_full_asserted_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_mbox_full_asserted_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_mbox_full_asserted_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_mbox_full_asserted_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define HSP_INT_IR_0_mbox_empty_asserted_SHIFT                  MK_SHIFT_CONST(0)
+#define HSP_INT_IR_0_mbox_empty_asserted_FIELD                  MK_FIELD_CONST(0xff, HSP_INT_IR_0_mbox_empty_asserted_SHIFT)
+#define HSP_INT_IR_0_mbox_empty_asserted_RANGE                  7:0
+#define HSP_INT_IR_0_mbox_empty_asserted_MSB                    MK_SHIFT_CONST(7)
+#define HSP_INT_IR_0_mbox_empty_asserted_LSB                    MK_SHIFT_CONST(0)
+#define HSP_INT_IR_0_mbox_empty_asserted_WOFFSET                        0x0
+#define HSP_INT_IR_0_mbox_empty_asserted_DEFAULT                        MK_MASK_CONST(0xff)
+#define HSP_INT_IR_0_mbox_empty_asserted_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define HSP_INT_IR_0_mbox_empty_asserted_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_mbox_empty_asserted_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_mbox_empty_asserted_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define HSP_INT_IR_0_mbox_empty_asserted_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register HSP_INT_SPARE_0
+#define HSP_INT_SPARE_0                 MK_ADDR_CONST(0x308)
+#define HSP_INT_SPARE_0_SECURE                  0x0
+#define HSP_INT_SPARE_0_DUAL                    0x0
+#define HSP_INT_SPARE_0_SCR                     0
+#define HSP_INT_SPARE_0_SCRREG                  0
+#define HSP_INT_SPARE_0_WORD_COUNT                      0x1
+#define HSP_INT_SPARE_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define HSP_INT_SPARE_0_RESET_MASK                      MK_MASK_CONST(0xf)
+#define HSP_INT_SPARE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define HSP_INT_SPARE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define HSP_INT_SPARE_0_READ_MASK                       MK_MASK_CONST(0xf)
+#define HSP_INT_SPARE_0_WRITE_MASK                      MK_MASK_CONST(0xf)
+#define HSP_INT_SPARE_0_spare_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_INT_SPARE_0_spare_FIELD                     MK_FIELD_CONST(0xf, HSP_INT_SPARE_0_spare_SHIFT)
+#define HSP_INT_SPARE_0_spare_RANGE                     3:0
+#define HSP_INT_SPARE_0_spare_MSB                       MK_SHIFT_CONST(3)
+#define HSP_INT_SPARE_0_spare_LSB                       MK_SHIFT_CONST(0)
+#define HSP_INT_SPARE_0_spare_WOFFSET                   0x0
+#define HSP_INT_SPARE_0_spare_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_SPARE_0_spare_DEFAULT_MASK                      MK_MASK_CONST(0xf)
+#define HSP_INT_SPARE_0_spare_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_INT_SPARE_0_spare_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_SPARE_0_spare_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_INT_SPARE_0_spare_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_INT_HSP_CLK_OVR_0
+#define HSP_INT_HSP_CLK_OVR_0                   MK_ADDR_CONST(0x30c)
+#define HSP_INT_HSP_CLK_OVR_0_SECURE                    0x0
+#define HSP_INT_HSP_CLK_OVR_0_DUAL                      0x0
+#define HSP_INT_HSP_CLK_OVR_0_SCR                       0
+#define HSP_INT_HSP_CLK_OVR_0_SCRREG                    0
+#define HSP_INT_HSP_CLK_OVR_0_WORD_COUNT                        0x1
+#define HSP_INT_HSP_CLK_OVR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_INT_HSP_CLK_OVR_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define HSP_INT_HSP_CLK_OVR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_INT_HSP_CLK_OVR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_INT_HSP_CLK_OVR_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define HSP_INT_HSP_CLK_OVR_0_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define HSP_INT_HSP_CLK_OVR_0_hsp_clk_ovr_on_SHIFT                      MK_SHIFT_CONST(0)
+#define HSP_INT_HSP_CLK_OVR_0_hsp_clk_ovr_on_FIELD                      MK_FIELD_CONST(0x1, HSP_INT_HSP_CLK_OVR_0_hsp_clk_ovr_on_SHIFT)
+#define HSP_INT_HSP_CLK_OVR_0_hsp_clk_ovr_on_RANGE                      0:0
+#define HSP_INT_HSP_CLK_OVR_0_hsp_clk_ovr_on_MSB                        MK_SHIFT_CONST(0)
+#define HSP_INT_HSP_CLK_OVR_0_hsp_clk_ovr_on_LSB                        MK_SHIFT_CONST(0)
+#define HSP_INT_HSP_CLK_OVR_0_hsp_clk_ovr_on_WOFFSET                    0x0
+#define HSP_INT_HSP_CLK_OVR_0_hsp_clk_ovr_on_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_INT_HSP_CLK_OVR_0_hsp_clk_ovr_on_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define HSP_INT_HSP_CLK_OVR_0_hsp_clk_ovr_on_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_INT_HSP_CLK_OVR_0_hsp_clk_ovr_on_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_INT_HSP_CLK_OVR_0_hsp_clk_ovr_on_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_INT_HSP_CLK_OVR_0_hsp_clk_ovr_on_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register HSP_INT_DIMENSIONING_0
+#define HSP_INT_DIMENSIONING_0                  MK_ADDR_CONST(0x380)
+#define HSP_INT_DIMENSIONING_0_SECURE                   0x0
+#define HSP_INT_DIMENSIONING_0_DUAL                     0x0
+#define HSP_INT_DIMENSIONING_0_SCR                      0
+#define HSP_INT_DIMENSIONING_0_SCRREG                   0
+#define HSP_INT_DIMENSIONING_0_WORD_COUNT                       0x1
+#define HSP_INT_DIMENSIONING_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_RESET_MASK                       MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_READ_MASK                        MK_MASK_CONST(0xfffff)
+#define HSP_INT_DIMENSIONING_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nSI_SHIFT                        MK_SHIFT_CONST(16)
+#define HSP_INT_DIMENSIONING_0_nSI_FIELD                        MK_FIELD_CONST(0xf, HSP_INT_DIMENSIONING_0_nSI_SHIFT)
+#define HSP_INT_DIMENSIONING_0_nSI_RANGE                        19:16
+#define HSP_INT_DIMENSIONING_0_nSI_MSB                  MK_SHIFT_CONST(19)
+#define HSP_INT_DIMENSIONING_0_nSI_LSB                  MK_SHIFT_CONST(16)
+#define HSP_INT_DIMENSIONING_0_nSI_WOFFSET                      0x0
+#define HSP_INT_DIMENSIONING_0_nSI_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nSI_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nSI_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nSI_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nSI_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nSI_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define HSP_INT_DIMENSIONING_0_nDB_SHIFT                        MK_SHIFT_CONST(12)
+#define HSP_INT_DIMENSIONING_0_nDB_FIELD                        MK_FIELD_CONST(0xf, HSP_INT_DIMENSIONING_0_nDB_SHIFT)
+#define HSP_INT_DIMENSIONING_0_nDB_RANGE                        15:12
+#define HSP_INT_DIMENSIONING_0_nDB_MSB                  MK_SHIFT_CONST(15)
+#define HSP_INT_DIMENSIONING_0_nDB_LSB                  MK_SHIFT_CONST(12)
+#define HSP_INT_DIMENSIONING_0_nDB_WOFFSET                      0x0
+#define HSP_INT_DIMENSIONING_0_nDB_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nDB_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nDB_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nDB_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nDB_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nDB_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define HSP_INT_DIMENSIONING_0_nAS_SHIFT                        MK_SHIFT_CONST(8)
+#define HSP_INT_DIMENSIONING_0_nAS_FIELD                        MK_FIELD_CONST(0xf, HSP_INT_DIMENSIONING_0_nAS_SHIFT)
+#define HSP_INT_DIMENSIONING_0_nAS_RANGE                        11:8
+#define HSP_INT_DIMENSIONING_0_nAS_MSB                  MK_SHIFT_CONST(11)
+#define HSP_INT_DIMENSIONING_0_nAS_LSB                  MK_SHIFT_CONST(8)
+#define HSP_INT_DIMENSIONING_0_nAS_WOFFSET                      0x0
+#define HSP_INT_DIMENSIONING_0_nAS_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nAS_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nAS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nAS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nAS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nAS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define HSP_INT_DIMENSIONING_0_nSS_SHIFT                        MK_SHIFT_CONST(4)
+#define HSP_INT_DIMENSIONING_0_nSS_FIELD                        MK_FIELD_CONST(0xf, HSP_INT_DIMENSIONING_0_nSS_SHIFT)
+#define HSP_INT_DIMENSIONING_0_nSS_RANGE                        7:4
+#define HSP_INT_DIMENSIONING_0_nSS_MSB                  MK_SHIFT_CONST(7)
+#define HSP_INT_DIMENSIONING_0_nSS_LSB                  MK_SHIFT_CONST(4)
+#define HSP_INT_DIMENSIONING_0_nSS_WOFFSET                      0x0
+#define HSP_INT_DIMENSIONING_0_nSS_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nSS_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nSS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nSS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nSS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nSS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define HSP_INT_DIMENSIONING_0_nSM_SHIFT                        MK_SHIFT_CONST(0)
+#define HSP_INT_DIMENSIONING_0_nSM_FIELD                        MK_FIELD_CONST(0xf, HSP_INT_DIMENSIONING_0_nSM_SHIFT)
+#define HSP_INT_DIMENSIONING_0_nSM_RANGE                        3:0
+#define HSP_INT_DIMENSIONING_0_nSM_MSB                  MK_SHIFT_CONST(3)
+#define HSP_INT_DIMENSIONING_0_nSM_LSB                  MK_SHIFT_CONST(0)
+#define HSP_INT_DIMENSIONING_0_nSM_WOFFSET                      0x0
+#define HSP_INT_DIMENSIONING_0_nSM_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nSM_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nSM_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nSM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nSM_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define HSP_INT_DIMENSIONING_0_nSM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARHSP_INT_REGS(_op_) \
+_op_(HSP_INT_IE_0) \
+_op_(HSP_INT_IE) \
+_op_(HSP_INT_IE_1) \
+_op_(HSP_INT_IE_2) \
+_op_(HSP_INT_IE_3) \
+_op_(HSP_INT_IE_4) \
+_op_(HSP_INT_IE_5) \
+_op_(HSP_INT_IE_6) \
+_op_(HSP_INT_IE_7) \
+_op_(HSP_INT_IV_0) \
+_op_(HSP_INT_IR_0) \
+_op_(HSP_INT_SPARE_0) \
+_op_(HSP_INT_HSP_CLK_OVR_0) \
+_op_(HSP_INT_DIMENSIONING_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_HSP_INT    0x00000100
+
+//
+// ARHSP_INT REGISTER BANKS
+//
+
+#define HSP_INT0_FIRST_REG 0x0100 // HSP_INT_IE_0
+#define HSP_INT0_LAST_REG 0x011c // HSP_INT_IE_7
+#define HSP_INT1_FIRST_REG 0x0300 // HSP_INT_IV_0
+#define HSP_INT1_LAST_REG 0x030c // HSP_INT_HSP_CLK_OVR_0
+#define HSP_INT2_FIRST_REG 0x0380 // HSP_INT_DIMENSIONING_0
+#define HSP_INT2_LAST_REG 0x0380 // HSP_INT_DIMENSIONING_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARHSP_INT_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arhsp_shrd_mbox.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arhsp_shrd_mbox.h
new file mode 100644
index 0000000..e6b4b31
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arhsp_shrd_mbox.h
@@ -0,0 +1,2157 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARHSP_SHRD_MBOX_H_INC
+#define ARHSP_SHRD_MBOX_H_INC
+#define NV_MOBILE_ARHSP_SHRD_MBOX_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARHSP_SHRD_MBOX_H_SCRREG_NOMENCLATURE INFERRED
+
+
+// Register HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0                        MK_ADDR_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_SECURE                         0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_DUAL                   0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_SCR                    SM_0_REG_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_SCRREG                         HSP_SHRD_MBOX_SCR_SM_0_REG_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_WORD_COUNT                     0x1
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_TAG_SHIFT                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_TAG_FIELD                      MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_TAG_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_TAG_RANGE                      31:31
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_TAG_MSB                        MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_TAG_LSB                        MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_TAG_WOFFSET                    0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_TAG_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_TAG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_TAG_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_TAG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_TAG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_TAG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_DATA_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_DATA_FIELD                     MK_FIELD_CONST(0x7fffffff, HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_DATA_RANGE                     30:0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_DATA_MSB                       MK_SHIFT_CONST(30)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_DATA_LSB                       MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_DATA_WOFFSET                   0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_DATA_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x7fffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0                    MK_ADDR_CONST(0x4)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_SCR                        SM_0_REG_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_0_REG_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_RESET_VAL                  MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_ENABLE_FIELD                       MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_ENABLE_RANGE                       0:0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_ENABLE_MSB                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_ENABLE_LSB                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_ENABLE_WOFFSET                     0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_ENABLE_DEFAULT                     MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0                   MK_ADDR_CONST(0x8)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_SECURE                    0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_DUAL                      0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_SCR                       SM_0_REG_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_SCRREG                    HSP_SHRD_MBOX_SCR_SM_0_REG_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_WORD_COUNT                        0x1
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_RESET_VAL                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_FIELD                      MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_RANGE                      0:0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_MSB                        MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_LSB                        MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_WOFFSET                    0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_DEFAULT                    MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0                      MK_ADDR_CONST(0x40)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_SECURE                       0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_DUAL                         0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_SCR                  SM_0_REG_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_SCRREG                       HSP_SHRD_MBOX_SCR_SM_0_REG_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_WORD_COUNT                   0x1
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_TAG_SHIFT                    MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_TAG_FIELD                    MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_TAG_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_TAG_RANGE                    31:31
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_TAG_MSB                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_TAG_LSB                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_TAG_WOFFSET                  0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_TAG_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_TAG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_TAG_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_TAG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_TAG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_TAG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_RSVD_SHIFT                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_RSVD_FIELD                   MK_FIELD_CONST(0x7fffffff, HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_RSVD_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_RSVD_RANGE                   30:0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_RSVD_MSB                     MK_SHIFT_CONST(30)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_RSVD_LSB                     MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_RSVD_WOFFSET                 0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_RSVD_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_RSVD_DEFAULT_MASK                    MK_MASK_CONST(0x7fffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_RSVD_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_RSVD_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_RSVD_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0_RSVD_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x44
+
+// Register HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0                    MK_ADDR_CONST(0x48)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_SCR                        SM_0_REG_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_0_REG_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0                    MK_ADDR_CONST(0x4c)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_SCR                        SM_0_REG_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_0_REG_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0                    MK_ADDR_CONST(0x50)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_SCR                        SM_0_REG_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_0_REG_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0                    MK_ADDR_CONST(0x54)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_SCR                        SM_0_REG_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_0_REG_0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0                        MK_ADDR_CONST(0x8000)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_SECURE                         0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_DUAL                   0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_SCR                    SM_1_REG_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_SCRREG                         HSP_SHRD_MBOX_SCR_SM_1_REG_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_WORD_COUNT                     0x1
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_TAG_SHIFT                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_TAG_FIELD                      MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_TAG_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_TAG_RANGE                      31:31
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_TAG_MSB                        MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_TAG_LSB                        MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_TAG_WOFFSET                    0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_TAG_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_TAG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_TAG_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_TAG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_TAG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_TAG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_DATA_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_DATA_FIELD                     MK_FIELD_CONST(0x7fffffff, HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_DATA_RANGE                     30:0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_DATA_MSB                       MK_SHIFT_CONST(30)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_DATA_LSB                       MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_DATA_WOFFSET                   0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_DATA_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x7fffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0                    MK_ADDR_CONST(0x8004)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_SCR                        SM_1_REG_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_1_REG_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_RESET_VAL                  MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_ENABLE_FIELD                       MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_ENABLE_RANGE                       0:0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_ENABLE_MSB                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_ENABLE_LSB                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_ENABLE_WOFFSET                     0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_ENABLE_DEFAULT                     MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0                   MK_ADDR_CONST(0x8008)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_SECURE                    0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_DUAL                      0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_SCR                       SM_1_REG_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_SCRREG                    HSP_SHRD_MBOX_SCR_SM_1_REG_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_WORD_COUNT                        0x1
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_RESET_VAL                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_FIELD                      MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_RANGE                      0:0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_MSB                        MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_LSB                        MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_WOFFSET                    0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_DEFAULT                    MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0                      MK_ADDR_CONST(0x8040)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_SECURE                       0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_DUAL                         0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_SCR                  SM_1_REG_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_SCRREG                       HSP_SHRD_MBOX_SCR_SM_1_REG_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_WORD_COUNT                   0x1
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_TAG_SHIFT                    MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_TAG_FIELD                    MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_TAG_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_TAG_RANGE                    31:31
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_TAG_MSB                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_TAG_LSB                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_TAG_WOFFSET                  0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_TAG_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_TAG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_TAG_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_TAG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_TAG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_TAG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_RSVD_SHIFT                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_RSVD_FIELD                   MK_FIELD_CONST(0x7fffffff, HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_RSVD_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_RSVD_RANGE                   30:0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_RSVD_MSB                     MK_SHIFT_CONST(30)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_RSVD_LSB                     MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_RSVD_WOFFSET                 0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_RSVD_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_RSVD_DEFAULT_MASK                    MK_MASK_CONST(0x7fffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_RSVD_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_RSVD_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_RSVD_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0_RSVD_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x8044
+
+// Register HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0                    MK_ADDR_CONST(0x8048)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_SCR                        SM_1_REG_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_1_REG_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0                    MK_ADDR_CONST(0x804c)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_SCR                        SM_1_REG_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_1_REG_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0                    MK_ADDR_CONST(0x8050)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_SCR                        SM_1_REG_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_1_REG_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0                    MK_ADDR_CONST(0x8054)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_SCR                        SM_1_REG_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_1_REG_0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0                        MK_ADDR_CONST(0x10000)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_SECURE                         0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_DUAL                   0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_SCR                    SM_2_REG_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_SCRREG                         HSP_SHRD_MBOX_SCR_SM_2_REG_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_WORD_COUNT                     0x1
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_TAG_SHIFT                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_TAG_FIELD                      MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_TAG_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_TAG_RANGE                      31:31
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_TAG_MSB                        MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_TAG_LSB                        MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_TAG_WOFFSET                    0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_TAG_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_TAG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_TAG_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_TAG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_TAG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_TAG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_DATA_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_DATA_FIELD                     MK_FIELD_CONST(0x7fffffff, HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_DATA_RANGE                     30:0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_DATA_MSB                       MK_SHIFT_CONST(30)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_DATA_LSB                       MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_DATA_WOFFSET                   0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_DATA_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x7fffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0                    MK_ADDR_CONST(0x10004)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_SCR                        SM_2_REG_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_2_REG_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_RESET_VAL                  MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_ENABLE_FIELD                       MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_ENABLE_RANGE                       0:0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_ENABLE_MSB                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_ENABLE_LSB                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_ENABLE_WOFFSET                     0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_ENABLE_DEFAULT                     MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0                   MK_ADDR_CONST(0x10008)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_SECURE                    0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_DUAL                      0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_SCR                       SM_2_REG_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_SCRREG                    HSP_SHRD_MBOX_SCR_SM_2_REG_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_WORD_COUNT                        0x1
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_RESET_VAL                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_FIELD                      MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_RANGE                      0:0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_MSB                        MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_LSB                        MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_WOFFSET                    0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_DEFAULT                    MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0                      MK_ADDR_CONST(0x10040)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_SECURE                       0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_DUAL                         0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_SCR                  SM_2_REG_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_SCRREG                       HSP_SHRD_MBOX_SCR_SM_2_REG_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_WORD_COUNT                   0x1
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_TAG_SHIFT                    MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_TAG_FIELD                    MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_TAG_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_TAG_RANGE                    31:31
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_TAG_MSB                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_TAG_LSB                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_TAG_WOFFSET                  0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_TAG_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_TAG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_TAG_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_TAG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_TAG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_TAG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_RSVD_SHIFT                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_RSVD_FIELD                   MK_FIELD_CONST(0x7fffffff, HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_RSVD_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_RSVD_RANGE                   30:0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_RSVD_MSB                     MK_SHIFT_CONST(30)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_RSVD_LSB                     MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_RSVD_WOFFSET                 0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_RSVD_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_RSVD_DEFAULT_MASK                    MK_MASK_CONST(0x7fffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_RSVD_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_RSVD_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_RSVD_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0_RSVD_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x10044
+
+// Register HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0                    MK_ADDR_CONST(0x10048)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_SCR                        SM_2_REG_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_2_REG_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0                    MK_ADDR_CONST(0x1004c)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_SCR                        SM_2_REG_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_2_REG_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0                    MK_ADDR_CONST(0x10050)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_SCR                        SM_2_REG_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_2_REG_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0                    MK_ADDR_CONST(0x10054)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_SCR                        SM_2_REG_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_2_REG_0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0                        MK_ADDR_CONST(0x18000)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_SECURE                         0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_DUAL                   0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_SCR                    SM_3_REG_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_SCRREG                         HSP_SHRD_MBOX_SCR_SM_3_REG_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_WORD_COUNT                     0x1
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_TAG_SHIFT                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_TAG_FIELD                      MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_TAG_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_TAG_RANGE                      31:31
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_TAG_MSB                        MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_TAG_LSB                        MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_TAG_WOFFSET                    0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_TAG_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_TAG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_TAG_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_TAG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_TAG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_TAG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_DATA_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_DATA_FIELD                     MK_FIELD_CONST(0x7fffffff, HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_DATA_RANGE                     30:0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_DATA_MSB                       MK_SHIFT_CONST(30)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_DATA_LSB                       MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_DATA_WOFFSET                   0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_DATA_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x7fffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0                    MK_ADDR_CONST(0x18004)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_SCR                        SM_3_REG_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_3_REG_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_RESET_VAL                  MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_ENABLE_FIELD                       MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_ENABLE_RANGE                       0:0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_ENABLE_MSB                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_ENABLE_LSB                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_ENABLE_WOFFSET                     0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_ENABLE_DEFAULT                     MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0                   MK_ADDR_CONST(0x18008)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_SECURE                    0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_DUAL                      0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_SCR                       SM_3_REG_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_SCRREG                    HSP_SHRD_MBOX_SCR_SM_3_REG_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_WORD_COUNT                        0x1
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_RESET_VAL                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_FIELD                      MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_RANGE                      0:0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_MSB                        MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_LSB                        MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_WOFFSET                    0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_DEFAULT                    MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0                      MK_ADDR_CONST(0x18040)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_SECURE                       0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_DUAL                         0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_SCR                  SM_3_REG_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_SCRREG                       HSP_SHRD_MBOX_SCR_SM_3_REG_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_WORD_COUNT                   0x1
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_TAG_SHIFT                    MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_TAG_FIELD                    MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_TAG_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_TAG_RANGE                    31:31
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_TAG_MSB                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_TAG_LSB                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_TAG_WOFFSET                  0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_TAG_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_TAG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_TAG_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_TAG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_TAG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_TAG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_RSVD_SHIFT                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_RSVD_FIELD                   MK_FIELD_CONST(0x7fffffff, HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_RSVD_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_RSVD_RANGE                   30:0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_RSVD_MSB                     MK_SHIFT_CONST(30)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_RSVD_LSB                     MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_RSVD_WOFFSET                 0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_RSVD_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_RSVD_DEFAULT_MASK                    MK_MASK_CONST(0x7fffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_RSVD_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_RSVD_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_RSVD_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0_RSVD_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x18044
+
+// Register HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0                    MK_ADDR_CONST(0x18048)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_SCR                        SM_3_REG_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_3_REG_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0                    MK_ADDR_CONST(0x1804c)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_SCR                        SM_3_REG_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_3_REG_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0                    MK_ADDR_CONST(0x18050)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_SCR                        SM_3_REG_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_3_REG_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0                    MK_ADDR_CONST(0x18054)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_SCR                        SM_3_REG_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_3_REG_0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0                        MK_ADDR_CONST(0x20000)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_SECURE                         0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_DUAL                   0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_SCR                    SM_4_REG_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_SCRREG                         HSP_SHRD_MBOX_SCR_SM_4_REG_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_WORD_COUNT                     0x1
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_TAG_SHIFT                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_TAG_FIELD                      MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_TAG_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_TAG_RANGE                      31:31
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_TAG_MSB                        MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_TAG_LSB                        MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_TAG_WOFFSET                    0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_TAG_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_TAG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_TAG_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_TAG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_TAG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_TAG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_DATA_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_DATA_FIELD                     MK_FIELD_CONST(0x7fffffff, HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_DATA_RANGE                     30:0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_DATA_MSB                       MK_SHIFT_CONST(30)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_DATA_LSB                       MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_DATA_WOFFSET                   0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_DATA_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x7fffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0                    MK_ADDR_CONST(0x20004)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_SCR                        SM_4_REG_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_4_REG_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_RESET_VAL                  MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_ENABLE_FIELD                       MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_ENABLE_RANGE                       0:0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_ENABLE_MSB                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_ENABLE_LSB                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_ENABLE_WOFFSET                     0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_ENABLE_DEFAULT                     MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0                   MK_ADDR_CONST(0x20008)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_SECURE                    0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_DUAL                      0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_SCR                       SM_4_REG_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_SCRREG                    HSP_SHRD_MBOX_SCR_SM_4_REG_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_WORD_COUNT                        0x1
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_RESET_VAL                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_FIELD                      MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_RANGE                      0:0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_MSB                        MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_LSB                        MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_WOFFSET                    0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_DEFAULT                    MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0                      MK_ADDR_CONST(0x20040)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_SECURE                       0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_DUAL                         0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_SCR                  SM_4_REG_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_SCRREG                       HSP_SHRD_MBOX_SCR_SM_4_REG_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_WORD_COUNT                   0x1
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_TAG_SHIFT                    MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_TAG_FIELD                    MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_TAG_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_TAG_RANGE                    31:31
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_TAG_MSB                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_TAG_LSB                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_TAG_WOFFSET                  0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_TAG_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_TAG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_TAG_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_TAG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_TAG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_TAG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_RSVD_SHIFT                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_RSVD_FIELD                   MK_FIELD_CONST(0x7fffffff, HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_RSVD_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_RSVD_RANGE                   30:0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_RSVD_MSB                     MK_SHIFT_CONST(30)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_RSVD_LSB                     MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_RSVD_WOFFSET                 0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_RSVD_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_RSVD_DEFAULT_MASK                    MK_MASK_CONST(0x7fffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_RSVD_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_RSVD_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_RSVD_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0_RSVD_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x20044
+
+// Register HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0                    MK_ADDR_CONST(0x20048)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_SCR                        SM_4_REG_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_4_REG_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0                    MK_ADDR_CONST(0x2004c)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_SCR                        SM_4_REG_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_4_REG_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0                    MK_ADDR_CONST(0x20050)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_SCR                        SM_4_REG_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_4_REG_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0                    MK_ADDR_CONST(0x20054)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_SCR                        SM_4_REG_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_4_REG_0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0                        MK_ADDR_CONST(0x28000)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_SECURE                         0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_DUAL                   0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_SCR                    SM_5_REG_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_SCRREG                         HSP_SHRD_MBOX_SCR_SM_5_REG_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_WORD_COUNT                     0x1
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_TAG_SHIFT                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_TAG_FIELD                      MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_TAG_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_TAG_RANGE                      31:31
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_TAG_MSB                        MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_TAG_LSB                        MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_TAG_WOFFSET                    0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_TAG_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_TAG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_TAG_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_TAG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_TAG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_TAG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_DATA_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_DATA_FIELD                     MK_FIELD_CONST(0x7fffffff, HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_DATA_RANGE                     30:0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_DATA_MSB                       MK_SHIFT_CONST(30)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_DATA_LSB                       MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_DATA_WOFFSET                   0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_DATA_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x7fffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0                    MK_ADDR_CONST(0x28004)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_SCR                        SM_5_REG_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_5_REG_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_RESET_VAL                  MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_ENABLE_FIELD                       MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_ENABLE_RANGE                       0:0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_ENABLE_MSB                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_ENABLE_LSB                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_ENABLE_WOFFSET                     0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_ENABLE_DEFAULT                     MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0                   MK_ADDR_CONST(0x28008)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_SECURE                    0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_DUAL                      0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_SCR                       SM_5_REG_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_SCRREG                    HSP_SHRD_MBOX_SCR_SM_5_REG_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_WORD_COUNT                        0x1
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_RESET_VAL                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_FIELD                      MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_RANGE                      0:0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_MSB                        MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_LSB                        MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_WOFFSET                    0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_DEFAULT                    MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0                      MK_ADDR_CONST(0x28040)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_SECURE                       0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_DUAL                         0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_SCR                  SM_5_REG_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_SCRREG                       HSP_SHRD_MBOX_SCR_SM_5_REG_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_WORD_COUNT                   0x1
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_TAG_SHIFT                    MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_TAG_FIELD                    MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_TAG_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_TAG_RANGE                    31:31
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_TAG_MSB                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_TAG_LSB                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_TAG_WOFFSET                  0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_TAG_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_TAG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_TAG_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_TAG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_TAG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_TAG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_RSVD_SHIFT                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_RSVD_FIELD                   MK_FIELD_CONST(0x7fffffff, HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_RSVD_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_RSVD_RANGE                   30:0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_RSVD_MSB                     MK_SHIFT_CONST(30)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_RSVD_LSB                     MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_RSVD_WOFFSET                 0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_RSVD_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_RSVD_DEFAULT_MASK                    MK_MASK_CONST(0x7fffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_RSVD_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_RSVD_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_RSVD_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0_RSVD_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x28044
+
+// Register HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0                    MK_ADDR_CONST(0x28048)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_SCR                        SM_5_REG_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_5_REG_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0                    MK_ADDR_CONST(0x2804c)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_SCR                        SM_5_REG_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_5_REG_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0                    MK_ADDR_CONST(0x28050)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_SCR                        SM_5_REG_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_5_REG_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0                    MK_ADDR_CONST(0x28054)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_SCR                        SM_5_REG_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_5_REG_0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0                        MK_ADDR_CONST(0x30000)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_SECURE                         0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_DUAL                   0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_SCR                    SM_6_REG_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_SCRREG                         HSP_SHRD_MBOX_SCR_SM_6_REG_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_WORD_COUNT                     0x1
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_TAG_SHIFT                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_TAG_FIELD                      MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_TAG_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_TAG_RANGE                      31:31
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_TAG_MSB                        MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_TAG_LSB                        MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_TAG_WOFFSET                    0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_TAG_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_TAG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_TAG_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_TAG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_TAG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_TAG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_DATA_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_DATA_FIELD                     MK_FIELD_CONST(0x7fffffff, HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_DATA_RANGE                     30:0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_DATA_MSB                       MK_SHIFT_CONST(30)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_DATA_LSB                       MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_DATA_WOFFSET                   0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_DATA_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x7fffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0                    MK_ADDR_CONST(0x30004)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_SCR                        SM_6_REG_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_6_REG_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_RESET_VAL                  MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_ENABLE_FIELD                       MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_ENABLE_RANGE                       0:0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_ENABLE_MSB                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_ENABLE_LSB                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_ENABLE_WOFFSET                     0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_ENABLE_DEFAULT                     MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0                   MK_ADDR_CONST(0x30008)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_SECURE                    0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_DUAL                      0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_SCR                       SM_6_REG_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_SCRREG                    HSP_SHRD_MBOX_SCR_SM_6_REG_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_WORD_COUNT                        0x1
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_RESET_VAL                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_FIELD                      MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_RANGE                      0:0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_MSB                        MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_LSB                        MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_WOFFSET                    0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_DEFAULT                    MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0                      MK_ADDR_CONST(0x30040)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_SECURE                       0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_DUAL                         0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_SCR                  SM_6_REG_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_SCRREG                       HSP_SHRD_MBOX_SCR_SM_6_REG_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_WORD_COUNT                   0x1
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_TAG_SHIFT                    MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_TAG_FIELD                    MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_TAG_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_TAG_RANGE                    31:31
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_TAG_MSB                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_TAG_LSB                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_TAG_WOFFSET                  0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_TAG_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_TAG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_TAG_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_TAG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_TAG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_TAG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_RSVD_SHIFT                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_RSVD_FIELD                   MK_FIELD_CONST(0x7fffffff, HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_RSVD_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_RSVD_RANGE                   30:0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_RSVD_MSB                     MK_SHIFT_CONST(30)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_RSVD_LSB                     MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_RSVD_WOFFSET                 0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_RSVD_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_RSVD_DEFAULT_MASK                    MK_MASK_CONST(0x7fffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_RSVD_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_RSVD_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_RSVD_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0_RSVD_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x30044
+
+// Register HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0                    MK_ADDR_CONST(0x30048)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_SCR                        SM_6_REG_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_6_REG_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0                    MK_ADDR_CONST(0x3004c)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_SCR                        SM_6_REG_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_6_REG_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0                    MK_ADDR_CONST(0x30050)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_SCR                        SM_6_REG_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_6_REG_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0                    MK_ADDR_CONST(0x30054)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_SCR                        SM_6_REG_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_6_REG_0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0                        MK_ADDR_CONST(0x38000)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_SECURE                         0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_DUAL                   0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_SCR                    SM_7_REG_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_SCRREG                         HSP_SHRD_MBOX_SCR_SM_7_REG_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_WORD_COUNT                     0x1
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_TAG_SHIFT                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_TAG_FIELD                      MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_TAG_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_TAG_RANGE                      31:31
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_TAG_MSB                        MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_TAG_LSB                        MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_TAG_WOFFSET                    0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_TAG_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_TAG_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_TAG_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_TAG_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_TAG_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_TAG_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_DATA_SHIFT                     MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_DATA_FIELD                     MK_FIELD_CONST(0x7fffffff, HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_DATA_RANGE                     30:0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_DATA_MSB                       MK_SHIFT_CONST(30)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_DATA_LSB                       MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_DATA_WOFFSET                   0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_DATA_DEFAULT                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x7fffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0                    MK_ADDR_CONST(0x38004)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_SCR                        SM_7_REG_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_7_REG_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_RESET_VAL                  MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SHIFT                       MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_ENABLE_FIELD                       MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_ENABLE_RANGE                       0:0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_ENABLE_MSB                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_ENABLE_LSB                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_ENABLE_WOFFSET                     0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_ENABLE_DEFAULT                     MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0                   MK_ADDR_CONST(0x38008)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_SECURE                    0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_DUAL                      0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_SCR                       SM_7_REG_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_SCRREG                    HSP_SHRD_MBOX_SCR_SM_7_REG_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_WORD_COUNT                        0x1
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_RESET_VAL                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_FIELD                      MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_RANGE                      0:0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_MSB                        MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_LSB                        MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_WOFFSET                    0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_DEFAULT                    MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0                      MK_ADDR_CONST(0x38040)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_SECURE                       0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_DUAL                         0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_SCR                  SM_7_REG_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_SCRREG                       HSP_SHRD_MBOX_SCR_SM_7_REG_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_WORD_COUNT                   0x1
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_TAG_SHIFT                    MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_TAG_FIELD                    MK_FIELD_CONST(0x1, HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_TAG_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_TAG_RANGE                    31:31
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_TAG_MSB                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_TAG_LSB                      MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_TAG_WOFFSET                  0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_TAG_DEFAULT                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_TAG_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_TAG_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_TAG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_TAG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_TAG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_RSVD_SHIFT                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_RSVD_FIELD                   MK_FIELD_CONST(0x7fffffff, HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_RSVD_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_RSVD_RANGE                   30:0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_RSVD_MSB                     MK_SHIFT_CONST(30)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_RSVD_LSB                     MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_RSVD_WOFFSET                 0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_RSVD_DEFAULT                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_RSVD_DEFAULT_MASK                    MK_MASK_CONST(0x7fffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_RSVD_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_RSVD_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_RSVD_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0_RSVD_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x38044
+
+// Register HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0                    MK_ADDR_CONST(0x38048)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_SCR                        SM_7_REG_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_7_REG_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0                    MK_ADDR_CONST(0x3804c)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_SCR                        SM_7_REG_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_7_REG_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0                    MK_ADDR_CONST(0x38050)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_SCR                        SM_7_REG_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_7_REG_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0                    MK_ADDR_CONST(0x38054)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_SECURE                     0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_DUAL                       0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_SCR                        SM_7_REG_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_SCRREG                     HSP_SHRD_MBOX_SCR_SM_7_REG_0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_WORD_COUNT                         0x1
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_DATA_SHIFT)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_DATA_RANGE                 31:0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_DATA_WOFFSET                       0x0
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARHSP_SHRD_MBOX_REGS(_op_) \
+_op_(HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0) \
+_op_(HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_FULL_INT_IE_0) \
+_op_(HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0) \
+_op_(HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0) \
+_op_(HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0) \
+_op_(HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA1_0) \
+_op_(HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA2_0) \
+_op_(HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0) \
+_op_(HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0) \
+_op_(HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_FULL_INT_IE_0) \
+_op_(HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0) \
+_op_(HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0) \
+_op_(HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0) \
+_op_(HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA1_0) \
+_op_(HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA2_0) \
+_op_(HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0) \
+_op_(HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0) \
+_op_(HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_FULL_INT_IE_0) \
+_op_(HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0) \
+_op_(HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0) \
+_op_(HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0) \
+_op_(HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA1_0) \
+_op_(HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA2_0) \
+_op_(HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0) \
+_op_(HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0) \
+_op_(HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_FULL_INT_IE_0) \
+_op_(HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0) \
+_op_(HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0) \
+_op_(HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0) \
+_op_(HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA1_0) \
+_op_(HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA2_0) \
+_op_(HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0) \
+_op_(HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0) \
+_op_(HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_FULL_INT_IE_0) \
+_op_(HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0) \
+_op_(HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0) \
+_op_(HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0) \
+_op_(HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA1_0) \
+_op_(HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA2_0) \
+_op_(HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0) \
+_op_(HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0) \
+_op_(HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_FULL_INT_IE_0) \
+_op_(HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0) \
+_op_(HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0) \
+_op_(HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0) \
+_op_(HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA1_0) \
+_op_(HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA2_0) \
+_op_(HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0) \
+_op_(HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0) \
+_op_(HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_FULL_INT_IE_0) \
+_op_(HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0) \
+_op_(HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0) \
+_op_(HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0) \
+_op_(HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA1_0) \
+_op_(HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA2_0) \
+_op_(HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0) \
+_op_(HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0) \
+_op_(HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_FULL_INT_IE_0) \
+_op_(HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0) \
+_op_(HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0) \
+_op_(HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0) \
+_op_(HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA1_0) \
+_op_(HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA2_0) \
+_op_(HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_HSP_SHRD_MBOX      0x00000000
+
+//
+// ARHSP_SHRD_MBOX REGISTER BANKS
+//
+
+#define HSP_SHRD_MBOX0_FIRST_REG 0x0000 // HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_0
+#define HSP_SHRD_MBOX0_LAST_REG 0x0008 // HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_EMPTY_INT_IE_0
+#define HSP_SHRD_MBOX1_FIRST_REG 0x0040 // HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX1_LAST_REG 0x0040 // HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX2_FIRST_REG 0x0048 // HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA0_0
+#define HSP_SHRD_MBOX2_LAST_REG 0x0054 // HSP_SHRD_MBOX_MBOX_0_SHRD_MBOX_TYPE1_DATA3_0
+#define HSP_SHRD_MBOX3_FIRST_REG 0x8000 // HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_0
+#define HSP_SHRD_MBOX3_LAST_REG 0x8008 // HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_EMPTY_INT_IE_0
+#define HSP_SHRD_MBOX4_FIRST_REG 0x8040 // HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX4_LAST_REG 0x8040 // HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX5_FIRST_REG 0x8048 // HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA0_0
+#define HSP_SHRD_MBOX5_LAST_REG 0x8054 // HSP_SHRD_MBOX_MBOX_1_SHRD_MBOX_TYPE1_DATA3_0
+#define HSP_SHRD_MBOX6_FIRST_REG 0x10000 // HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_0
+#define HSP_SHRD_MBOX6_LAST_REG 0x10008 // HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_EMPTY_INT_IE_0
+#define HSP_SHRD_MBOX7_FIRST_REG 0x10040 // HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX7_LAST_REG 0x10040 // HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX8_FIRST_REG 0x10048 // HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA0_0
+#define HSP_SHRD_MBOX8_LAST_REG 0x10054 // HSP_SHRD_MBOX_MBOX_2_SHRD_MBOX_TYPE1_DATA3_0
+#define HSP_SHRD_MBOX9_FIRST_REG 0x18000 // HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_0
+#define HSP_SHRD_MBOX9_LAST_REG 0x18008 // HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_EMPTY_INT_IE_0
+#define HSP_SHRD_MBOX10_FIRST_REG 0x18040 // HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX10_LAST_REG 0x18040 // HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX11_FIRST_REG 0x18048 // HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA0_0
+#define HSP_SHRD_MBOX11_LAST_REG 0x18054 // HSP_SHRD_MBOX_MBOX_3_SHRD_MBOX_TYPE1_DATA3_0
+#define HSP_SHRD_MBOX12_FIRST_REG 0x20000 // HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_0
+#define HSP_SHRD_MBOX12_LAST_REG 0x20008 // HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_EMPTY_INT_IE_0
+#define HSP_SHRD_MBOX13_FIRST_REG 0x20040 // HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX13_LAST_REG 0x20040 // HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX14_FIRST_REG 0x20048 // HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA0_0
+#define HSP_SHRD_MBOX14_LAST_REG 0x20054 // HSP_SHRD_MBOX_MBOX_4_SHRD_MBOX_TYPE1_DATA3_0
+#define HSP_SHRD_MBOX15_FIRST_REG 0x28000 // HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_0
+#define HSP_SHRD_MBOX15_LAST_REG 0x28008 // HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_EMPTY_INT_IE_0
+#define HSP_SHRD_MBOX16_FIRST_REG 0x28040 // HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX16_LAST_REG 0x28040 // HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX17_FIRST_REG 0x28048 // HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA0_0
+#define HSP_SHRD_MBOX17_LAST_REG 0x28054 // HSP_SHRD_MBOX_MBOX_5_SHRD_MBOX_TYPE1_DATA3_0
+#define HSP_SHRD_MBOX18_FIRST_REG 0x30000 // HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_0
+#define HSP_SHRD_MBOX18_LAST_REG 0x30008 // HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_EMPTY_INT_IE_0
+#define HSP_SHRD_MBOX19_FIRST_REG 0x30040 // HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX19_LAST_REG 0x30040 // HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX20_FIRST_REG 0x30048 // HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA0_0
+#define HSP_SHRD_MBOX20_LAST_REG 0x30054 // HSP_SHRD_MBOX_MBOX_6_SHRD_MBOX_TYPE1_DATA3_0
+#define HSP_SHRD_MBOX21_FIRST_REG 0x38000 // HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_0
+#define HSP_SHRD_MBOX21_LAST_REG 0x38008 // HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_EMPTY_INT_IE_0
+#define HSP_SHRD_MBOX22_FIRST_REG 0x38040 // HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX22_LAST_REG 0x38040 // HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_TAG_0
+#define HSP_SHRD_MBOX23_FIRST_REG 0x38048 // HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA0_0
+#define HSP_SHRD_MBOX23_LAST_REG 0x38054 // HSP_SHRD_MBOX_MBOX_7_SHRD_MBOX_TYPE1_DATA3_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARHSP_SHRD_MBOX_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arhsp_shrd_sem.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arhsp_shrd_sem.h
new file mode 100644
index 0000000..18bcb25
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arhsp_shrd_sem.h
@@ -0,0 +1,781 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARHSP_SHRD_SEM_H_INC
+#define ARHSP_SHRD_SEM_H_INC
+#define NV_MOBILE_ARHSP_SHRD_SEM_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARHSP_SHRD_SEM_H_SCRREG_NOMENCLATURE EXACT
+
+
+// Register HSP_SHRD_SEM_0_SHRD_SMP_STA_0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0                   MK_ADDR_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SECURE                    0x0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_DUAL                      0x0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SCR                       SS_0_REG_0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SCRREG                    HSP_SHRD_SEM_SCR_SS_0_REG_0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_WORD_COUNT                        0x1
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_SHIFT)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_RANGE                 31:0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_WOFFSET                       0x0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_0_SMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0                       MK_ADDR_CONST(0x4)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SECURE                        0x0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_DUAL                  0x0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SCR                   SS_0_REG_0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_0_REG_0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_WORD_COUNT                    0x1
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_RANGE                 31:0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_WOFFSET                       0x0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0_SMP_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0                       MK_ADDR_CONST(0x8)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SECURE                        0x0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_DUAL                  0x0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SCR                   SS_0_REG_0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_0_REG_0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_WORD_COUNT                    0x1
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_RANGE                 31:0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_WOFFSET                       0x0
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0_SMP_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_1_SHRD_SMP_STA_0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0                   MK_ADDR_CONST(0x10000)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SECURE                    0x0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_DUAL                      0x0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SCR                       SS_1_REG_0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SCRREG                    HSP_SHRD_SEM_SCR_SS_1_REG_0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_WORD_COUNT                        0x1
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_SHIFT)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_RANGE                 31:0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_WOFFSET                       0x0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_0_SMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0                       MK_ADDR_CONST(0x10004)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SECURE                        0x0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_DUAL                  0x0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SCR                   SS_1_REG_0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_1_REG_0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_WORD_COUNT                    0x1
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_RANGE                 31:0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_WOFFSET                       0x0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0_SMP_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0                       MK_ADDR_CONST(0x10008)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SECURE                        0x0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_DUAL                  0x0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SCR                   SS_1_REG_0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_1_REG_0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_WORD_COUNT                    0x1
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_RANGE                 31:0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_WOFFSET                       0x0
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0_SMP_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_2_SHRD_SMP_STA_0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0                   MK_ADDR_CONST(0x20000)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SECURE                    0x0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_DUAL                      0x0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SCR                       SS_2_REG_0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SCRREG                    HSP_SHRD_SEM_SCR_SS_2_REG_0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_WORD_COUNT                        0x1
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_SHIFT)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_RANGE                 31:0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_WOFFSET                       0x0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_0_SMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0                       MK_ADDR_CONST(0x20004)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SECURE                        0x0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_DUAL                  0x0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SCR                   SS_2_REG_0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_2_REG_0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_WORD_COUNT                    0x1
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_RANGE                 31:0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_WOFFSET                       0x0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0_SMP_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0                       MK_ADDR_CONST(0x20008)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SECURE                        0x0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_DUAL                  0x0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SCR                   SS_2_REG_0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_2_REG_0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_WORD_COUNT                    0x1
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_RANGE                 31:0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_WOFFSET                       0x0
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0_SMP_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_3_SHRD_SMP_STA_0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0                   MK_ADDR_CONST(0x30000)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SECURE                    0x0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_DUAL                      0x0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SCR                       SS_3_REG_0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SCRREG                    HSP_SHRD_SEM_SCR_SS_3_REG_0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_WORD_COUNT                        0x1
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_SHIFT)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_RANGE                 31:0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_WOFFSET                       0x0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_0_SMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0                       MK_ADDR_CONST(0x30004)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SECURE                        0x0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_DUAL                  0x0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SCR                   SS_3_REG_0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_3_REG_0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_WORD_COUNT                    0x1
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_RANGE                 31:0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_WOFFSET                       0x0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0_SMP_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0                       MK_ADDR_CONST(0x30008)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SECURE                        0x0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_DUAL                  0x0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SCR                   SS_3_REG_0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_3_REG_0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_WORD_COUNT                    0x1
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_RANGE                 31:0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_WOFFSET                       0x0
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0_SMP_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_4_SHRD_SMP_STA_0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0                   MK_ADDR_CONST(0x40000)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SECURE                    0x0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_DUAL                      0x0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SCR                       SS_4_REG_0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SCRREG                    HSP_SHRD_SEM_SCR_SS_4_REG_0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_WORD_COUNT                        0x1
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_SHIFT)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_RANGE                 31:0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_WOFFSET                       0x0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_0_SMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0                       MK_ADDR_CONST(0x40004)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SECURE                        0x0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_DUAL                  0x0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SCR                   SS_4_REG_0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_4_REG_0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_WORD_COUNT                    0x1
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_RANGE                 31:0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_WOFFSET                       0x0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0_SMP_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0                       MK_ADDR_CONST(0x40008)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SECURE                        0x0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_DUAL                  0x0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SCR                   SS_4_REG_0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_4_REG_0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_WORD_COUNT                    0x1
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_RANGE                 31:0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_WOFFSET                       0x0
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0_SMP_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_5_SHRD_SMP_STA_0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0                   MK_ADDR_CONST(0x50000)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SECURE                    0x0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_DUAL                      0x0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SCR                       SS_5_REG_0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SCRREG                    HSP_SHRD_SEM_SCR_SS_5_REG_0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_WORD_COUNT                        0x1
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_SHIFT)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_RANGE                 31:0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_WOFFSET                       0x0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_0_SMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0                       MK_ADDR_CONST(0x50004)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SECURE                        0x0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_DUAL                  0x0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SCR                   SS_5_REG_0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_5_REG_0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_WORD_COUNT                    0x1
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_RANGE                 31:0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_WOFFSET                       0x0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0_SMP_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0                       MK_ADDR_CONST(0x50008)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SECURE                        0x0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_DUAL                  0x0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SCR                   SS_5_REG_0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_5_REG_0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_WORD_COUNT                    0x1
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_RANGE                 31:0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_WOFFSET                       0x0
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0_SMP_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_6_SHRD_SMP_STA_0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0                   MK_ADDR_CONST(0x60000)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SECURE                    0x0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_DUAL                      0x0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SCR                       SS_6_REG_0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SCRREG                    HSP_SHRD_SEM_SCR_SS_6_REG_0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_WORD_COUNT                        0x1
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_SHIFT)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_RANGE                 31:0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_WOFFSET                       0x0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_0_SMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0                       MK_ADDR_CONST(0x60004)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SECURE                        0x0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_DUAL                  0x0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SCR                   SS_6_REG_0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_6_REG_0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_WORD_COUNT                    0x1
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_RANGE                 31:0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_WOFFSET                       0x0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0_SMP_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0                       MK_ADDR_CONST(0x60008)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SECURE                        0x0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_DUAL                  0x0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SCR                   SS_6_REG_0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_6_REG_0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_WORD_COUNT                    0x1
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_RANGE                 31:0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_WOFFSET                       0x0
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0_SMP_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_7_SHRD_SMP_STA_0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0                   MK_ADDR_CONST(0x70000)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SECURE                    0x0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_DUAL                      0x0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SCR                       SS_7_REG_0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SCRREG                    HSP_SHRD_SEM_SCR_SS_7_REG_0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_WORD_COUNT                        0x1
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_SHIFT)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_RANGE                 31:0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_WOFFSET                       0x0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_0_SMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0                       MK_ADDR_CONST(0x70004)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SECURE                        0x0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_DUAL                  0x0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SCR                   SS_7_REG_0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_7_REG_0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_WORD_COUNT                    0x1
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_SHIFT)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_RANGE                 31:0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_WOFFSET                       0x0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0_SMP_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0                       MK_ADDR_CONST(0x70008)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SECURE                        0x0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_DUAL                  0x0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SCR                   SS_7_REG_0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SCRREG                        HSP_SHRD_SEM_SCR_SS_7_REG_0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_WORD_COUNT                    0x1
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_SHIFT)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_RANGE                 31:0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_MSB                   MK_SHIFT_CONST(31)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_LSB                   MK_SHIFT_CONST(0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_WOFFSET                       0x0
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0_SMP_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARHSP_SHRD_SEM_REGS(_op_) \
+_op_(HSP_SHRD_SEM_0_SHRD_SMP_STA_0) \
+_op_(HSP_SHRD_SEM_0_SHRD_SMP_STA_SET_0) \
+_op_(HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0) \
+_op_(HSP_SHRD_SEM_1_SHRD_SMP_STA_0) \
+_op_(HSP_SHRD_SEM_1_SHRD_SMP_STA_SET_0) \
+_op_(HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0) \
+_op_(HSP_SHRD_SEM_2_SHRD_SMP_STA_0) \
+_op_(HSP_SHRD_SEM_2_SHRD_SMP_STA_SET_0) \
+_op_(HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0) \
+_op_(HSP_SHRD_SEM_3_SHRD_SMP_STA_0) \
+_op_(HSP_SHRD_SEM_3_SHRD_SMP_STA_SET_0) \
+_op_(HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0) \
+_op_(HSP_SHRD_SEM_4_SHRD_SMP_STA_0) \
+_op_(HSP_SHRD_SEM_4_SHRD_SMP_STA_SET_0) \
+_op_(HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0) \
+_op_(HSP_SHRD_SEM_5_SHRD_SMP_STA_0) \
+_op_(HSP_SHRD_SEM_5_SHRD_SMP_STA_SET_0) \
+_op_(HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0) \
+_op_(HSP_SHRD_SEM_6_SHRD_SMP_STA_0) \
+_op_(HSP_SHRD_SEM_6_SHRD_SMP_STA_SET_0) \
+_op_(HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0) \
+_op_(HSP_SHRD_SEM_7_SHRD_SMP_STA_0) \
+_op_(HSP_SHRD_SEM_7_SHRD_SMP_STA_SET_0) \
+_op_(HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_HSP_SHRD   0x00000000
+
+//
+// ARHSP_SHRD_SEM REGISTER BANKS
+//
+
+#define HSP_SHRD0_FIRST_REG 0x0000 // HSP_SHRD_SEM_0_SHRD_SMP_STA_0
+#define HSP_SHRD0_LAST_REG 0x0008 // HSP_SHRD_SEM_0_SHRD_SMP_STA_CLR_0
+#define HSP_SHRD1_FIRST_REG 0x10000 // HSP_SHRD_SEM_1_SHRD_SMP_STA_0
+#define HSP_SHRD1_LAST_REG 0x10008 // HSP_SHRD_SEM_1_SHRD_SMP_STA_CLR_0
+#define HSP_SHRD2_FIRST_REG 0x20000 // HSP_SHRD_SEM_2_SHRD_SMP_STA_0
+#define HSP_SHRD2_LAST_REG 0x20008 // HSP_SHRD_SEM_2_SHRD_SMP_STA_CLR_0
+#define HSP_SHRD3_FIRST_REG 0x30000 // HSP_SHRD_SEM_3_SHRD_SMP_STA_0
+#define HSP_SHRD3_LAST_REG 0x30008 // HSP_SHRD_SEM_3_SHRD_SMP_STA_CLR_0
+#define HSP_SHRD4_FIRST_REG 0x40000 // HSP_SHRD_SEM_4_SHRD_SMP_STA_0
+#define HSP_SHRD4_LAST_REG 0x40008 // HSP_SHRD_SEM_4_SHRD_SMP_STA_CLR_0
+#define HSP_SHRD5_FIRST_REG 0x50000 // HSP_SHRD_SEM_5_SHRD_SMP_STA_0
+#define HSP_SHRD5_LAST_REG 0x50008 // HSP_SHRD_SEM_5_SHRD_SMP_STA_CLR_0
+#define HSP_SHRD6_FIRST_REG 0x60000 // HSP_SHRD_SEM_6_SHRD_SMP_STA_0
+#define HSP_SHRD6_LAST_REG 0x60008 // HSP_SHRD_SEM_6_SHRD_SMP_STA_CLR_0
+#define HSP_SHRD7_FIRST_REG 0x70000 // HSP_SHRD_SEM_7_SHRD_SMP_STA_0
+#define HSP_SHRD7_LAST_REG 0x70008 // HSP_SHRD_SEM_7_SHRD_SMP_STA_CLR_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARHSP_SHRD_SEM_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/ari2c.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/ari2c.h
new file mode 100644
index 0000000..e8487fd
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/ari2c.h
@@ -0,0 +1,4748 @@
+//
+// Copyright (c) 2022 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARI2C_H_INC
+#define ARI2C_H_INC
+#define NV_MOBILE_ARI2C_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARI2C_H_SCRREG_NOMENCLATURE INFERRED
+
+// Register I2C_I2C_CNFG_0
+#define I2C_I2C_CNFG_0                  MK_ADDR_CONST(0x0)
+#define I2C_I2C_CNFG_0_SECURE                   0x0
+#define I2C_I2C_CNFG_0_DUAL                     0x0
+#define I2C_I2C_CNFG_0_SCR                      0
+#define I2C_I2C_CNFG_0_SCRREG                   0
+#define I2C_I2C_CNFG_0_WORD_COUNT                       0x1
+#define I2C_I2C_CNFG_0_RESET_VAL                        MK_MASK_CONST(0x20800)
+#define I2C_I2C_CNFG_0_RESET_MASK                       MK_MASK_CONST(0x3ffff)
+#define I2C_I2C_CNFG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_READ_MASK                        MK_MASK_CONST(0x3ffff)
+#define I2C_I2C_CNFG_0_WRITE_MASK                       MK_MASK_CONST(0x3f7ff)
+#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_SHIFT                  MK_SHIFT_CONST(17)
+#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_MULTI_MASTER_MODE_SHIFT)
+#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_RANGE                  17:17
+#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_MSB                    MK_SHIFT_CONST(17)
+#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_LSB                    MK_SHIFT_CONST(17)
+#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_WOFFSET                        0x0
+#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_DEFAULT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_INIT_ENUM                      ENABLE
+#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_DISABLE                        MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_MULTI_MASTER_MODE_ENABLE                 MK_ENUM_CONST(1)
+
+#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_SHIFT                     MK_SHIFT_CONST(16)
+#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_SHIFT)
+#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_RANGE                     16:16
+#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_MSB                       MK_SHIFT_CONST(16)
+#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_LSB                       MK_SHIFT_CONST(16)
+#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_WOFFSET                   0x0
+#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_INIT_ENUM                 DISABLE
+#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_DISABLE                   MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_HS_RND_TRIP_DLY_EFFECT_ENABLE                    MK_ENUM_CONST(1)
+
+#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_SHIFT                    MK_SHIFT_CONST(15)
+#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_SHIFT)
+#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_RANGE                    15:15
+#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_MSB                      MK_SHIFT_CONST(15)
+#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_LSB                      MK_SHIFT_CONST(15)
+#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_WOFFSET                  0x0
+#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_MSTR_CLR_BUS_ON_TIMEOUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_SHIFT                       MK_SHIFT_CONST(12)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_FIELD                       MK_FIELD_CONST(0x7, I2C_I2C_CNFG_0_DEBOUNCE_CNT_SHIFT)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_RANGE                       14:12
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_MSB                 MK_SHIFT_CONST(14)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_LSB                 MK_SHIFT_CONST(12)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_DEBOUNCE_CNT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_SHIFT                     MK_SHIFT_CONST(11)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_NEW_MASTER_FSM_SHIFT)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_RANGE                     11:11
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_MSB                       MK_SHIFT_CONST(11)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_LSB                       MK_SHIFT_CONST(11)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_WOFFSET                   0x0
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_DEFAULT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_DISABLE                   MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_NEW_MASTER_FSM_ENABLE                    MK_ENUM_CONST(1)
+
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_SHIFT                     MK_SHIFT_CONST(10)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_PACKET_MODE_EN_SHIFT)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_RANGE                     10:10
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_MSB                       MK_SHIFT_CONST(10)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_LSB                       MK_SHIFT_CONST(10)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_WOFFSET                   0x0
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_NOP                       MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_PACKET_MODE_EN_GO                        MK_ENUM_CONST(1)
+
+#define I2C_I2C_CNFG_0_SEND_SHIFT                       MK_SHIFT_CONST(9)
+#define I2C_I2C_CNFG_0_SEND_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_SEND_SHIFT)
+#define I2C_I2C_CNFG_0_SEND_RANGE                       9:9
+#define I2C_I2C_CNFG_0_SEND_MSB                 MK_SHIFT_CONST(9)
+#define I2C_I2C_CNFG_0_SEND_LSB                 MK_SHIFT_CONST(9)
+#define I2C_I2C_CNFG_0_SEND_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_SEND_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SEND_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_SEND_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SEND_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SEND_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SEND_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_SEND_NOP                 MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_SEND_GO                  MK_ENUM_CONST(1)
+
+#define I2C_I2C_CNFG_0_NOACK_SHIFT                      MK_SHIFT_CONST(8)
+#define I2C_I2C_CNFG_0_NOACK_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_NOACK_SHIFT)
+#define I2C_I2C_CNFG_0_NOACK_RANGE                      8:8
+#define I2C_I2C_CNFG_0_NOACK_MSB                        MK_SHIFT_CONST(8)
+#define I2C_I2C_CNFG_0_NOACK_LSB                        MK_SHIFT_CONST(8)
+#define I2C_I2C_CNFG_0_NOACK_WOFFSET                    0x0
+#define I2C_I2C_CNFG_0_NOACK_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NOACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_NOACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NOACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NOACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_NOACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_NOACK_DISABLE                    MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_NOACK_ENABLE                     MK_ENUM_CONST(1)
+
+#define I2C_I2C_CNFG_0_CMD2_SHIFT                       MK_SHIFT_CONST(7)
+#define I2C_I2C_CNFG_0_CMD2_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_CMD2_SHIFT)
+#define I2C_I2C_CNFG_0_CMD2_RANGE                       7:7
+#define I2C_I2C_CNFG_0_CMD2_MSB                 MK_SHIFT_CONST(7)
+#define I2C_I2C_CNFG_0_CMD2_LSB                 MK_SHIFT_CONST(7)
+#define I2C_I2C_CNFG_0_CMD2_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_CMD2_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_CMD2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_CMD2_DISABLE                     MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_CMD2_ENABLE                      MK_ENUM_CONST(1)
+
+#define I2C_I2C_CNFG_0_CMD1_SHIFT                       MK_SHIFT_CONST(6)
+#define I2C_I2C_CNFG_0_CMD1_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_CMD1_SHIFT)
+#define I2C_I2C_CNFG_0_CMD1_RANGE                       6:6
+#define I2C_I2C_CNFG_0_CMD1_MSB                 MK_SHIFT_CONST(6)
+#define I2C_I2C_CNFG_0_CMD1_LSB                 MK_SHIFT_CONST(6)
+#define I2C_I2C_CNFG_0_CMD1_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_CMD1_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_CMD1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_CMD1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_CMD1_DISABLE                     MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_CMD1_ENABLE                      MK_ENUM_CONST(1)
+
+#define I2C_I2C_CNFG_0_START_SHIFT                      MK_SHIFT_CONST(5)
+#define I2C_I2C_CNFG_0_START_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_START_SHIFT)
+#define I2C_I2C_CNFG_0_START_RANGE                      5:5
+#define I2C_I2C_CNFG_0_START_MSB                        MK_SHIFT_CONST(5)
+#define I2C_I2C_CNFG_0_START_LSB                        MK_SHIFT_CONST(5)
+#define I2C_I2C_CNFG_0_START_WOFFSET                    0x0
+#define I2C_I2C_CNFG_0_START_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_START_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_START_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_START_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_START_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_START_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_START_DISABLE                    MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_START_ENABLE                     MK_ENUM_CONST(1)
+
+#define I2C_I2C_CNFG_0_SLV2_SHIFT                       MK_SHIFT_CONST(4)
+#define I2C_I2C_CNFG_0_SLV2_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_SLV2_SHIFT)
+#define I2C_I2C_CNFG_0_SLV2_RANGE                       4:4
+#define I2C_I2C_CNFG_0_SLV2_MSB                 MK_SHIFT_CONST(4)
+#define I2C_I2C_CNFG_0_SLV2_LSB                 MK_SHIFT_CONST(4)
+#define I2C_I2C_CNFG_0_SLV2_WOFFSET                     0x0
+#define I2C_I2C_CNFG_0_SLV2_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SLV2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_SLV2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SLV2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SLV2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_SLV2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_SLV2_DISABLE                     MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_SLV2_ENABLE                      MK_ENUM_CONST(1)
+
+#define I2C_I2C_CNFG_0_LENGTH_SHIFT                     MK_SHIFT_CONST(1)
+#define I2C_I2C_CNFG_0_LENGTH_FIELD                     MK_FIELD_CONST(0x7, I2C_I2C_CNFG_0_LENGTH_SHIFT)
+#define I2C_I2C_CNFG_0_LENGTH_RANGE                     3:1
+#define I2C_I2C_CNFG_0_LENGTH_MSB                       MK_SHIFT_CONST(3)
+#define I2C_I2C_CNFG_0_LENGTH_LSB                       MK_SHIFT_CONST(1)
+#define I2C_I2C_CNFG_0_LENGTH_WOFFSET                   0x0
+#define I2C_I2C_CNFG_0_LENGTH_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_LENGTH_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define I2C_I2C_CNFG_0_LENGTH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_LENGTH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_LENGTH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_LENGTH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define I2C_I2C_CNFG_0_A_MOD_SHIFT                      MK_SHIFT_CONST(0)
+#define I2C_I2C_CNFG_0_A_MOD_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_CNFG_0_A_MOD_SHIFT)
+#define I2C_I2C_CNFG_0_A_MOD_RANGE                      0:0
+#define I2C_I2C_CNFG_0_A_MOD_MSB                        MK_SHIFT_CONST(0)
+#define I2C_I2C_CNFG_0_A_MOD_LSB                        MK_SHIFT_CONST(0)
+#define I2C_I2C_CNFG_0_A_MOD_WOFFSET                    0x0
+#define I2C_I2C_CNFG_0_A_MOD_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_A_MOD_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_A_MOD_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_A_MOD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_A_MOD_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_CNFG_0_A_MOD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_CNFG_0_A_MOD_SEVEN_BIT_DEVICE_ADDRESS                   MK_ENUM_CONST(0)
+#define I2C_I2C_CNFG_0_A_MOD_TEN_BIT_DEVICE_ADDRESS                     MK_ENUM_CONST(1)
+
+// Register I2C_I2C_CMD_ADDR0_0
+#define I2C_I2C_CMD_ADDR0_0                     MK_ADDR_CONST(0x4)
+#define I2C_I2C_CMD_ADDR0_0_SECURE                      0x0
+#define I2C_I2C_CMD_ADDR0_0_DUAL                        0x0
+#define I2C_I2C_CMD_ADDR0_0_SCR                         0
+#define I2C_I2C_CMD_ADDR0_0_SCRREG                      0
+#define I2C_I2C_CMD_ADDR0_0_WORD_COUNT                  0x1
+#define I2C_I2C_CMD_ADDR0_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_RESET_MASK                  MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_READ_MASK                   MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR0_0_WRITE_MASK                  MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_SHIFT                 MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_FIELD                 MK_FIELD_CONST(0x3ff, I2C_I2C_CMD_ADDR0_0_ADDR0_SHIFT)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_RANGE                 9:0
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_MSB                   MK_SHIFT_CONST(9)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_LSB                   MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_WOFFSET                       0x0
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_DEFAULT_MASK                  MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR0_0_ADDR0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register I2C_I2C_CMD_ADDR1_0
+#define I2C_I2C_CMD_ADDR1_0                     MK_ADDR_CONST(0x8)
+#define I2C_I2C_CMD_ADDR1_0_SECURE                      0x0
+#define I2C_I2C_CMD_ADDR1_0_DUAL                        0x0
+#define I2C_I2C_CMD_ADDR1_0_SCR                         0
+#define I2C_I2C_CMD_ADDR1_0_SCRREG                      0
+#define I2C_I2C_CMD_ADDR1_0_WORD_COUNT                  0x1
+#define I2C_I2C_CMD_ADDR1_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_RESET_MASK                  MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_READ_MASK                   MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR1_0_WRITE_MASK                  MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_SHIFT                 MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_FIELD                 MK_FIELD_CONST(0x3ff, I2C_I2C_CMD_ADDR1_0_ADDR1_SHIFT)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_RANGE                 9:0
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_MSB                   MK_SHIFT_CONST(9)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_LSB                   MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_WOFFSET                       0x0
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_DEFAULT_MASK                  MK_MASK_CONST(0x3ff)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_ADDR1_0_ADDR1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register I2C_I2C_CMD_DATA1_0
+#define I2C_I2C_CMD_DATA1_0                     MK_ADDR_CONST(0xc)
+#define I2C_I2C_CMD_DATA1_0_SECURE                      0x0
+#define I2C_I2C_CMD_DATA1_0_DUAL                        0x0
+#define I2C_I2C_CMD_DATA1_0_SCR                         0
+#define I2C_I2C_CMD_DATA1_0_SCRREG                      0
+#define I2C_I2C_CMD_DATA1_0_WORD_COUNT                  0x1
+#define I2C_I2C_CMD_DATA1_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA1_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA1_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA1_0_DATA4_SHIFT                 MK_SHIFT_CONST(24)
+#define I2C_I2C_CMD_DATA1_0_DATA4_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_CMD_DATA1_0_DATA4_SHIFT)
+#define I2C_I2C_CMD_DATA1_0_DATA4_RANGE                 31:24
+#define I2C_I2C_CMD_DATA1_0_DATA4_MSB                   MK_SHIFT_CONST(31)
+#define I2C_I2C_CMD_DATA1_0_DATA4_LSB                   MK_SHIFT_CONST(24)
+#define I2C_I2C_CMD_DATA1_0_DATA4_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA1_0_DATA4_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA4_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA1_0_DATA4_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA4_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA4_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define I2C_I2C_CMD_DATA1_0_DATA3_SHIFT                 MK_SHIFT_CONST(16)
+#define I2C_I2C_CMD_DATA1_0_DATA3_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_CMD_DATA1_0_DATA3_SHIFT)
+#define I2C_I2C_CMD_DATA1_0_DATA3_RANGE                 23:16
+#define I2C_I2C_CMD_DATA1_0_DATA3_MSB                   MK_SHIFT_CONST(23)
+#define I2C_I2C_CMD_DATA1_0_DATA3_LSB                   MK_SHIFT_CONST(16)
+#define I2C_I2C_CMD_DATA1_0_DATA3_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA1_0_DATA3_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA3_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA1_0_DATA3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA3_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define I2C_I2C_CMD_DATA1_0_DATA2_SHIFT                 MK_SHIFT_CONST(8)
+#define I2C_I2C_CMD_DATA1_0_DATA2_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_CMD_DATA1_0_DATA2_SHIFT)
+#define I2C_I2C_CMD_DATA1_0_DATA2_RANGE                 15:8
+#define I2C_I2C_CMD_DATA1_0_DATA2_MSB                   MK_SHIFT_CONST(15)
+#define I2C_I2C_CMD_DATA1_0_DATA2_LSB                   MK_SHIFT_CONST(8)
+#define I2C_I2C_CMD_DATA1_0_DATA2_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA1_0_DATA2_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA2_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA1_0_DATA2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define I2C_I2C_CMD_DATA1_0_DATA1_SHIFT                 MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_DATA1_0_DATA1_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_CMD_DATA1_0_DATA1_SHIFT)
+#define I2C_I2C_CMD_DATA1_0_DATA1_RANGE                 7:0
+#define I2C_I2C_CMD_DATA1_0_DATA1_MSB                   MK_SHIFT_CONST(7)
+#define I2C_I2C_CMD_DATA1_0_DATA1_LSB                   MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_DATA1_0_DATA1_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA1_0_DATA1_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA1_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA1_0_DATA1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA1_0_DATA1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register I2C_I2C_CMD_DATA2_0
+#define I2C_I2C_CMD_DATA2_0                     MK_ADDR_CONST(0x10)
+#define I2C_I2C_CMD_DATA2_0_SECURE                      0x0
+#define I2C_I2C_CMD_DATA2_0_DUAL                        0x0
+#define I2C_I2C_CMD_DATA2_0_SCR                         0
+#define I2C_I2C_CMD_DATA2_0_SCRREG                      0
+#define I2C_I2C_CMD_DATA2_0_WORD_COUNT                  0x1
+#define I2C_I2C_CMD_DATA2_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA2_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA2_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CMD_DATA2_0_DATA8_SHIFT                 MK_SHIFT_CONST(24)
+#define I2C_I2C_CMD_DATA2_0_DATA8_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_CMD_DATA2_0_DATA8_SHIFT)
+#define I2C_I2C_CMD_DATA2_0_DATA8_RANGE                 31:24
+#define I2C_I2C_CMD_DATA2_0_DATA8_MSB                   MK_SHIFT_CONST(31)
+#define I2C_I2C_CMD_DATA2_0_DATA8_LSB                   MK_SHIFT_CONST(24)
+#define I2C_I2C_CMD_DATA2_0_DATA8_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA2_0_DATA8_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA8_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA2_0_DATA8_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA8_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA8_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA8_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define I2C_I2C_CMD_DATA2_0_DATA7_SHIFT                 MK_SHIFT_CONST(16)
+#define I2C_I2C_CMD_DATA2_0_DATA7_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_CMD_DATA2_0_DATA7_SHIFT)
+#define I2C_I2C_CMD_DATA2_0_DATA7_RANGE                 23:16
+#define I2C_I2C_CMD_DATA2_0_DATA7_MSB                   MK_SHIFT_CONST(23)
+#define I2C_I2C_CMD_DATA2_0_DATA7_LSB                   MK_SHIFT_CONST(16)
+#define I2C_I2C_CMD_DATA2_0_DATA7_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA2_0_DATA7_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA7_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA2_0_DATA7_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA7_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA7_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define I2C_I2C_CMD_DATA2_0_DATA6_SHIFT                 MK_SHIFT_CONST(8)
+#define I2C_I2C_CMD_DATA2_0_DATA6_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_CMD_DATA2_0_DATA6_SHIFT)
+#define I2C_I2C_CMD_DATA2_0_DATA6_RANGE                 15:8
+#define I2C_I2C_CMD_DATA2_0_DATA6_MSB                   MK_SHIFT_CONST(15)
+#define I2C_I2C_CMD_DATA2_0_DATA6_LSB                   MK_SHIFT_CONST(8)
+#define I2C_I2C_CMD_DATA2_0_DATA6_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA2_0_DATA6_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA6_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA2_0_DATA6_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA6_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA6_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define I2C_I2C_CMD_DATA2_0_DATA5_SHIFT                 MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_DATA2_0_DATA5_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_CMD_DATA2_0_DATA5_SHIFT)
+#define I2C_I2C_CMD_DATA2_0_DATA5_RANGE                 7:0
+#define I2C_I2C_CMD_DATA2_0_DATA5_MSB                   MK_SHIFT_CONST(7)
+#define I2C_I2C_CMD_DATA2_0_DATA5_LSB                   MK_SHIFT_CONST(0)
+#define I2C_I2C_CMD_DATA2_0_DATA5_WOFFSET                       0x0
+#define I2C_I2C_CMD_DATA2_0_DATA5_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA5_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define I2C_I2C_CMD_DATA2_0_DATA5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CMD_DATA2_0_DATA5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Reserved address 0x14
+
+// Reserved address 0x18
+
+// Register I2C_I2C_STATUS_0
+#define I2C_I2C_STATUS_0                        MK_ADDR_CONST(0x1c)
+#define I2C_I2C_STATUS_0_SECURE                         0x0
+#define I2C_I2C_STATUS_0_DUAL                   0x0
+#define I2C_I2C_STATUS_0_SCR                    0
+#define I2C_I2C_STATUS_0_SCRREG                         0
+#define I2C_I2C_STATUS_0_WORD_COUNT                     0x1
+#define I2C_I2C_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x1ff)
+#define I2C_I2C_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_READ_MASK                      MK_MASK_CONST(0x1ff)
+#define I2C_I2C_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_BUSY_SHIFT                     MK_SHIFT_CONST(8)
+#define I2C_I2C_STATUS_0_BUSY_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_STATUS_0_BUSY_SHIFT)
+#define I2C_I2C_STATUS_0_BUSY_RANGE                     8:8
+#define I2C_I2C_STATUS_0_BUSY_MSB                       MK_SHIFT_CONST(8)
+#define I2C_I2C_STATUS_0_BUSY_LSB                       MK_SHIFT_CONST(8)
+#define I2C_I2C_STATUS_0_BUSY_WOFFSET                   0x0
+#define I2C_I2C_STATUS_0_BUSY_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_BUSY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_STATUS_0_BUSY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_BUSY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_BUSY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_BUSY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_STATUS_0_BUSY_NOT_BUSY                  MK_ENUM_CONST(0)
+#define I2C_I2C_STATUS_0_BUSY_BUSY                      MK_ENUM_CONST(1)
+
+#define I2C_I2C_STATUS_0_CMD2_STAT_SHIFT                        MK_SHIFT_CONST(4)
+#define I2C_I2C_STATUS_0_CMD2_STAT_FIELD                        MK_FIELD_CONST(0xf, I2C_I2C_STATUS_0_CMD2_STAT_SHIFT)
+#define I2C_I2C_STATUS_0_CMD2_STAT_RANGE                        7:4
+#define I2C_I2C_STATUS_0_CMD2_STAT_MSB                  MK_SHIFT_CONST(7)
+#define I2C_I2C_STATUS_0_CMD2_STAT_LSB                  MK_SHIFT_CONST(4)
+#define I2C_I2C_STATUS_0_CMD2_STAT_WOFFSET                      0x0
+#define I2C_I2C_STATUS_0_CMD2_STAT_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD2_STAT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD2_STAT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD2_STAT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_XFER_SUCCESSFUL                  MK_ENUM_CONST(0)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE1                  MK_ENUM_CONST(1)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE2                  MK_ENUM_CONST(2)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE3                  MK_ENUM_CONST(3)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE4                  MK_ENUM_CONST(4)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE5                  MK_ENUM_CONST(5)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE6                  MK_ENUM_CONST(6)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE7                  MK_ENUM_CONST(7)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE8                  MK_ENUM_CONST(8)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE9                  MK_ENUM_CONST(9)
+#define I2C_I2C_STATUS_0_CMD2_STAT_SL2_NOACK_FOR_BYTE10                 MK_ENUM_CONST(10)
+
+#define I2C_I2C_STATUS_0_CMD1_STAT_SHIFT                        MK_SHIFT_CONST(0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_FIELD                        MK_FIELD_CONST(0xf, I2C_I2C_STATUS_0_CMD1_STAT_SHIFT)
+#define I2C_I2C_STATUS_0_CMD1_STAT_RANGE                        3:0
+#define I2C_I2C_STATUS_0_CMD1_STAT_MSB                  MK_SHIFT_CONST(3)
+#define I2C_I2C_STATUS_0_CMD1_STAT_LSB                  MK_SHIFT_CONST(0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_WOFFSET                      0x0
+#define I2C_I2C_STATUS_0_CMD1_STAT_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_XFER_SUCCESSFUL                  MK_ENUM_CONST(0)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE1                  MK_ENUM_CONST(1)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE2                  MK_ENUM_CONST(2)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE3                  MK_ENUM_CONST(3)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE4                  MK_ENUM_CONST(4)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE5                  MK_ENUM_CONST(5)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE6                  MK_ENUM_CONST(6)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE7                  MK_ENUM_CONST(7)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE8                  MK_ENUM_CONST(8)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE9                  MK_ENUM_CONST(9)
+#define I2C_I2C_STATUS_0_CMD1_STAT_SL1_NOACK_FOR_BYTE10                 MK_ENUM_CONST(10)
+
+#define DIVCLK_SETUP_PERIOD     6
+#define FIFO_DEPTH      128
+#define SLAVE1  0
+#define SLAVE2  1
+#define TLOW_MEXT_CNT_WIDTH     8
+#define TLOW_SEXT_CNT_WIDTH     8
+#define TIMEOUT_CNT_WIDTH       8
+
+// Register I2C_I2C_SL_CNFG_0
+#define I2C_I2C_SL_CNFG_0                       MK_ADDR_CONST(0x20)
+#define I2C_I2C_SL_CNFG_0_SECURE                        0x0
+#define I2C_I2C_SL_CNFG_0_DUAL                  0x0
+#define I2C_I2C_SL_CNFG_0_SCR                   0
+#define I2C_I2C_SL_CNFG_0_SCRREG                        0
+#define I2C_I2C_SL_CNFG_0_WORD_COUNT                    0x1
+#define I2C_I2C_SL_CNFG_0_RESET_VAL                     MK_MASK_CONST(0x4)
+#define I2C_I2C_SL_CNFG_0_RESET_MASK                    MK_MASK_CONST(0x3fffff)
+#define I2C_I2C_SL_CNFG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_READ_MASK                     MK_MASK_CONST(0x3fffff)
+#define I2C_I2C_SL_CNFG_0_WRITE_MASK                    MK_MASK_CONST(0x3ffffb)
+#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_SHIFT                     MK_SHIFT_CONST(21)
+#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_SHIFT)
+#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_RANGE                     21:21
+#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_MSB                       MK_SHIFT_CONST(21)
+#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_LSB                       MK_SHIFT_CONST(21)
+#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_WOFFSET                   0x0
+#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_DISABLE                   MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_SLV_XFER_ERR_CLK_STRETCH_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_SHIFT                    MK_SHIFT_CONST(20)
+#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_SHIFT)
+#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_RANGE                    20:20
+#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_MSB                      MK_SHIFT_CONST(20)
+#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_LSB                      MK_SHIFT_CONST(20)
+#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_WOFFSET                  0x0
+#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_DISABLE                  MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_FIFO_XFER_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_SHIFT                     MK_SHIFT_CONST(8)
+#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_FIELD                     MK_FIELD_CONST(0xfff, I2C_I2C_SL_CNFG_0_BUFFER_SIZE_SHIFT)
+#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_RANGE                     19:8
+#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_MSB                       MK_SHIFT_CONST(19)
+#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_LSB                       MK_SHIFT_CONST(8)
+#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_WOFFSET                   0x0
+#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_DEFAULT_MASK                      MK_MASK_CONST(0xfff)
+#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_BUFFER_SIZE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_SHIFT                     MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_SHIFT)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_RANGE                     7:7
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_MSB                       MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_LSB                       MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_WOFFSET                   0x0
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_DISABLE                   MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_VALID_ENABLE                    MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_SHIFT                   MK_SHIFT_CONST(6)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_SHIFT)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_RANGE                   6:6
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_MSB                     MK_SHIFT_CONST(6)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_LSB                     MK_SHIFT_CONST(6)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_WOFFSET                 0x0
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_DISABLE                 MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_ACK_LAST_BYTE_ENABLE                  MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_SHIFT                 MK_SHIFT_CONST(5)
+#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_SHIFT)
+#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_RANGE                 5:5
+#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_MSB                   MK_SHIFT_CONST(5)
+#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_LSB                   MK_SHIFT_CONST(5)
+#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_WOFFSET                       0x0
+#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_DISABLE                       MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_ACK_WITHHOLD_EN_ENABLE                        MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_SHIFT                     MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_PKT_MODE_EN_SHIFT)
+#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_RANGE                     4:4
+#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_MSB                       MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_LSB                       MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_WOFFSET                   0x0
+#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_DISABLE                   MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_PKT_MODE_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_CNFG_0_ENABLE_SL_SHIFT                       MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_CNFG_0_ENABLE_SL_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_ENABLE_SL_SHIFT)
+#define I2C_I2C_SL_CNFG_0_ENABLE_SL_RANGE                       3:3
+#define I2C_I2C_SL_CNFG_0_ENABLE_SL_MSB                 MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_CNFG_0_ENABLE_SL_LSB                 MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_CNFG_0_ENABLE_SL_WOFFSET                     0x0
+#define I2C_I2C_SL_CNFG_0_ENABLE_SL_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_ENABLE_SL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_ENABLE_SL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_ENABLE_SL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_ENABLE_SL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_ENABLE_SL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_ENABLE_SL_DISABLE                     MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_ENABLE_SL_ENABLE                      MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_CNFG_0_NEWSL_SHIFT                   MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_CNFG_0_NEWSL_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_NEWSL_SHIFT)
+#define I2C_I2C_SL_CNFG_0_NEWSL_RANGE                   2:2
+#define I2C_I2C_SL_CNFG_0_NEWSL_MSB                     MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_CNFG_0_NEWSL_LSB                     MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_CNFG_0_NEWSL_WOFFSET                 0x0
+#define I2C_I2C_SL_CNFG_0_NEWSL_DEFAULT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_NEWSL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_NEWSL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NEWSL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NEWSL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NEWSL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_NEWSL_DISABLE                 MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_NEWSL_ENABLE                  MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_CNFG_0_NACK_SHIFT                    MK_SHIFT_CONST(1)
+#define I2C_I2C_SL_CNFG_0_NACK_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_NACK_SHIFT)
+#define I2C_I2C_SL_CNFG_0_NACK_RANGE                    1:1
+#define I2C_I2C_SL_CNFG_0_NACK_MSB                      MK_SHIFT_CONST(1)
+#define I2C_I2C_SL_CNFG_0_NACK_LSB                      MK_SHIFT_CONST(1)
+#define I2C_I2C_SL_CNFG_0_NACK_WOFFSET                  0x0
+#define I2C_I2C_SL_CNFG_0_NACK_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_NACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_NACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_NACK_DISABLE                  MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_NACK_ENABLE                   MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_CNFG_0_RESP_SHIFT                    MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_CNFG_0_RESP_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_CNFG_0_RESP_SHIFT)
+#define I2C_I2C_SL_CNFG_0_RESP_RANGE                    0:0
+#define I2C_I2C_SL_CNFG_0_RESP_MSB                      MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_CNFG_0_RESP_LSB                      MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_CNFG_0_RESP_WOFFSET                  0x0
+#define I2C_I2C_SL_CNFG_0_RESP_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_RESP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_RESP_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_RESP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_RESP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_CNFG_0_RESP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_CNFG_0_RESP_DISABLE                  MK_ENUM_CONST(0)
+#define I2C_I2C_SL_CNFG_0_RESP_ENABLE                   MK_ENUM_CONST(1)
+
+// Register I2C_I2C_SL_RCVD_0
+#define I2C_I2C_SL_RCVD_0                       MK_ADDR_CONST(0x24)
+#define I2C_I2C_SL_RCVD_0_SECURE                        0x0
+#define I2C_I2C_SL_RCVD_0_DUAL                  0x0
+#define I2C_I2C_SL_RCVD_0_SCR                   0
+#define I2C_I2C_SL_RCVD_0_SCRREG                        0
+#define I2C_I2C_SL_RCVD_0_WORD_COUNT                    0x1
+#define I2C_I2C_SL_RCVD_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_RCVD_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_RCVD_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_SL_RCVD_0_SL_DATA_SHIFT)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_RANGE                 7:0
+#define I2C_I2C_SL_RCVD_0_SL_DATA_MSB                   MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_LSB                   MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_WOFFSET                       0x0
+#define I2C_I2C_SL_RCVD_0_SL_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_RCVD_0_SL_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register I2C_I2C_SL_STATUS_0
+#define I2C_I2C_SL_STATUS_0                     MK_ADDR_CONST(0x28)
+#define I2C_I2C_SL_STATUS_0_SECURE                      0x0
+#define I2C_I2C_SL_STATUS_0_DUAL                        0x0
+#define I2C_I2C_SL_STATUS_0_SCR                         0
+#define I2C_I2C_SL_STATUS_0_SCRREG                      0
+#define I2C_I2C_SL_STATUS_0_WORD_COUNT                  0x1
+#define I2C_I2C_SL_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7fff)
+#define I2C_I2C_SL_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7fff)
+#define I2C_I2C_SL_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0xfd)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_SHIFT                   MK_SHIFT_CONST(8)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_FIELD                   MK_FIELD_CONST(0x7f, I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_SHIFT)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_RANGE                   14:8
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_MSB                     MK_SHIFT_CONST(14)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_LSB                     MK_SHIFT_CONST(8)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_WOFFSET                 0x0
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_DEFAULT_MASK                    MK_MASK_CONST(0x7f)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_ADR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_SHIFT                   MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_SL_STATUS_0_HW_MSTR_INT_SHIFT)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_RANGE                   7:7
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_MSB                     MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_LSB                     MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_WOFFSET                 0x0
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_HW_MSTR_INT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_SHIFT                     MK_SHIFT_CONST(6)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_SL_STATUS_0_REPROG_SL_SHIFT)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_RANGE                     6:6
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_MSB                       MK_SHIFT_CONST(6)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_LSB                       MK_SHIFT_CONST(6)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_WOFFSET                   0x0
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_REPROG_SL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define I2C_I2C_SL_STATUS_0_RST_SL_SHIFT                        MK_SHIFT_CONST(5)
+#define I2C_I2C_SL_STATUS_0_RST_SL_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_SL_STATUS_0_RST_SL_SHIFT)
+#define I2C_I2C_SL_STATUS_0_RST_SL_RANGE                        5:5
+#define I2C_I2C_SL_STATUS_0_RST_SL_MSB                  MK_SHIFT_CONST(5)
+#define I2C_I2C_SL_STATUS_0_RST_SL_LSB                  MK_SHIFT_CONST(5)
+#define I2C_I2C_SL_STATUS_0_RST_SL_WOFFSET                      0x0
+#define I2C_I2C_SL_STATUS_0_RST_SL_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RST_SL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_RST_SL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RST_SL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RST_SL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RST_SL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define I2C_I2C_SL_STATUS_0_END_TRANS_SHIFT                     MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_SL_STATUS_0_END_TRANS_SHIFT)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_RANGE                     4:4
+#define I2C_I2C_SL_STATUS_0_END_TRANS_MSB                       MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_LSB                       MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_WOFFSET                   0x0
+#define I2C_I2C_SL_STATUS_0_END_TRANS_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_END_TRANS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_SHIFT                        MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_SL_STATUS_0_SL_IRQ_SHIFT)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_RANGE                        3:3
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_MSB                  MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_LSB                  MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_WOFFSET                      0x0
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_UNSET                        MK_ENUM_CONST(0)
+#define I2C_I2C_SL_STATUS_0_SL_IRQ_SET                  MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_STATUS_0_RCVD_SHIFT                  MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_STATUS_0_RCVD_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_SL_STATUS_0_RCVD_SHIFT)
+#define I2C_I2C_SL_STATUS_0_RCVD_RANGE                  2:2
+#define I2C_I2C_SL_STATUS_0_RCVD_MSB                    MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_STATUS_0_RCVD_LSB                    MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_STATUS_0_RCVD_WOFFSET                        0x0
+#define I2C_I2C_SL_STATUS_0_RCVD_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RCVD_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_RCVD_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RCVD_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RCVD_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RCVD_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_RCVD_NO_TRANSACTION_OCCURED                 MK_ENUM_CONST(0)
+#define I2C_I2C_SL_STATUS_0_RCVD_TRANSACTION_OCCURED                    MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_STATUS_0_RNW_SHIFT                   MK_SHIFT_CONST(1)
+#define I2C_I2C_SL_STATUS_0_RNW_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_SL_STATUS_0_RNW_SHIFT)
+#define I2C_I2C_SL_STATUS_0_RNW_RANGE                   1:1
+#define I2C_I2C_SL_STATUS_0_RNW_MSB                     MK_SHIFT_CONST(1)
+#define I2C_I2C_SL_STATUS_0_RNW_LSB                     MK_SHIFT_CONST(1)
+#define I2C_I2C_SL_STATUS_0_RNW_WOFFSET                 0x0
+#define I2C_I2C_SL_STATUS_0_RNW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RNW_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_RNW_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RNW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RNW_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_RNW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_RNW_WRITE                   MK_ENUM_CONST(0)
+#define I2C_I2C_SL_STATUS_0_RNW_READ                    MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_STATUS_0_ZA_SHIFT                    MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_STATUS_0_ZA_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_STATUS_0_ZA_SHIFT)
+#define I2C_I2C_SL_STATUS_0_ZA_RANGE                    0:0
+#define I2C_I2C_SL_STATUS_0_ZA_MSB                      MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_STATUS_0_ZA_LSB                      MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_STATUS_0_ZA_WOFFSET                  0x0
+#define I2C_I2C_SL_STATUS_0_ZA_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_ZA_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_ZA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_ZA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_ZA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_STATUS_0_ZA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_STATUS_0_ZA_NO_SLAVE_RESPONSE                        MK_ENUM_CONST(0)
+#define I2C_I2C_SL_STATUS_0_ZA_SLAVE_RESPONSE                   MK_ENUM_CONST(1)
+
+// Register I2C_I2C_SL_ADDR1_0
+#define I2C_I2C_SL_ADDR1_0                      MK_ADDR_CONST(0x2c)
+#define I2C_I2C_SL_ADDR1_0_SECURE                       0x0
+#define I2C_I2C_SL_ADDR1_0_DUAL                         0x0
+#define I2C_I2C_SL_ADDR1_0_SCR                  0
+#define I2C_I2C_SL_ADDR1_0_SCRREG                       0
+#define I2C_I2C_SL_ADDR1_0_WORD_COUNT                   0x1
+#define I2C_I2C_SL_ADDR1_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_RESET_MASK                   MK_MASK_CONST(0xffff)
+#define I2C_I2C_SL_ADDR1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_READ_MASK                    MK_MASK_CONST(0xffff)
+#define I2C_I2C_SL_ADDR1_0_WRITE_MASK                   MK_MASK_CONST(0xffff)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_SHIFT                       MK_SHIFT_CONST(8)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_FIELD                       MK_FIELD_CONST(0xff, I2C_I2C_SL_ADDR1_0_SL_ADDR1_SHIFT)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_RANGE                       15:8
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_MSB                 MK_SHIFT_CONST(15)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_LSB                 MK_SHIFT_CONST(8)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_WOFFSET                     0x0
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_SHIFT                       MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_FIELD                       MK_FIELD_CONST(0xff, I2C_I2C_SL_ADDR1_0_SL_ADDR0_SHIFT)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_RANGE                       7:0
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_MSB                 MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_LSB                 MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_WOFFSET                     0x0
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR1_0_SL_ADDR0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register I2C_I2C_SL_ADDR2_0
+#define I2C_I2C_SL_ADDR2_0                      MK_ADDR_CONST(0x30)
+#define I2C_I2C_SL_ADDR2_0_SECURE                       0x0
+#define I2C_I2C_SL_ADDR2_0_DUAL                         0x0
+#define I2C_I2C_SL_ADDR2_0_SCR                  0
+#define I2C_I2C_SL_ADDR2_0_SCRREG                       0
+#define I2C_I2C_SL_ADDR2_0_WORD_COUNT                   0x1
+#define I2C_I2C_SL_ADDR2_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_RESET_MASK                   MK_MASK_CONST(0x10707)
+#define I2C_I2C_SL_ADDR2_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_READ_MASK                    MK_MASK_CONST(0x10707)
+#define I2C_I2C_SL_ADDR2_0_WRITE_MASK                   MK_MASK_CONST(0x10707)
+#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_SHIFT                   MK_SHIFT_CONST(16)
+#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_SHIFT)
+#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_RANGE                   16:16
+#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_MSB                     MK_SHIFT_CONST(16)
+#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_LSB                     MK_SHIFT_CONST(16)
+#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_WOFFSET                 0x0
+#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SELECT_SLAVE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_SHIFT                    MK_SHIFT_CONST(9)
+#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_FIELD                    MK_FIELD_CONST(0x3, I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_SHIFT)
+#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_RANGE                    10:9
+#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_MSB                      MK_SHIFT_CONST(10)
+#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_LSB                      MK_SHIFT_CONST(9)
+#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_WOFFSET                  0x0
+#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL1_ADDR_HI_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define I2C_I2C_SL_ADDR2_0_SL1_VLD_SHIFT                        MK_SHIFT_CONST(8)
+#define I2C_I2C_SL_ADDR2_0_SL1_VLD_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_SL_ADDR2_0_SL1_VLD_SHIFT)
+#define I2C_I2C_SL_ADDR2_0_SL1_VLD_RANGE                        8:8
+#define I2C_I2C_SL_ADDR2_0_SL1_VLD_MSB                  MK_SHIFT_CONST(8)
+#define I2C_I2C_SL_ADDR2_0_SL1_VLD_LSB                  MK_SHIFT_CONST(8)
+#define I2C_I2C_SL_ADDR2_0_SL1_VLD_WOFFSET                      0x0
+#define I2C_I2C_SL_ADDR2_0_SL1_VLD_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL1_VLD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_ADDR2_0_SL1_VLD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL1_VLD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL1_VLD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL1_VLD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_ADDR2_0_SL1_VLD_SEVEN_BIT_ADDR_MODE                  MK_ENUM_CONST(0)
+#define I2C_I2C_SL_ADDR2_0_SL1_VLD_TEN_BIT_ADDR_MODE                    MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SHIFT                     MK_SHIFT_CONST(1)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_FIELD                     MK_FIELD_CONST(0x3, I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SHIFT)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_RANGE                     2:1
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_MSB                       MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_LSB                       MK_SHIFT_CONST(1)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_WOFFSET                   0x0
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_SL_ADDR_HI_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define I2C_I2C_SL_ADDR2_0_VLD_SHIFT                    MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_ADDR2_0_VLD_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_ADDR2_0_VLD_SHIFT)
+#define I2C_I2C_SL_ADDR2_0_VLD_RANGE                    0:0
+#define I2C_I2C_SL_ADDR2_0_VLD_MSB                      MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_ADDR2_0_VLD_LSB                      MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_ADDR2_0_VLD_WOFFSET                  0x0
+#define I2C_I2C_SL_ADDR2_0_VLD_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_VLD_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_ADDR2_0_VLD_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_VLD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_VLD_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_ADDR2_0_VLD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_ADDR2_0_VLD_SEVEN_BIT_ADDR_MODE                      MK_ENUM_CONST(0)
+#define I2C_I2C_SL_ADDR2_0_VLD_TEN_BIT_ADDR_MODE                        MK_ENUM_CONST(1)
+
+// Register I2C_I2C_TLOW_SEXT_0
+#define I2C_I2C_TLOW_SEXT_0                     MK_ADDR_CONST(0x34)
+#define I2C_I2C_TLOW_SEXT_0_SECURE                      0x0
+#define I2C_I2C_TLOW_SEXT_0_DUAL                        0x0
+#define I2C_I2C_TLOW_SEXT_0_SCR                         0
+#define I2C_I2C_TLOW_SEXT_0_SCRREG                      0
+#define I2C_I2C_TLOW_SEXT_0_WORD_COUNT                  0x1
+#define I2C_I2C_TLOW_SEXT_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_RESET_MASK                  MK_MASK_CONST(0xfffffff)
+#define I2C_I2C_TLOW_SEXT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_READ_MASK                   MK_MASK_CONST(0xfffffff)
+#define I2C_I2C_TLOW_SEXT_0_WRITE_MASK                  MK_MASK_CONST(0xfffffff)
+#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_SHIFT                     MK_SHIFT_CONST(27)
+#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_SHIFT)
+#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_RANGE                     27:27
+#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_MSB                       MK_SHIFT_CONST(27)
+#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_LSB                       MK_SHIFT_CONST(27)
+#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_WOFFSET                   0x0
+#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_RST_SL_ON_TIMEOUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_SHIFT                  MK_SHIFT_CONST(26)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_SHIFT)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_RANGE                  26:26
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_MSB                    MK_SHIFT_CONST(26)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_LSB                    MK_SHIFT_CONST(26)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_WOFFSET                        0x0
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_SHIFT                  MK_SHIFT_CONST(25)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_SHIFT)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_RANGE                  25:25
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_MSB                    MK_SHIFT_CONST(25)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_LSB                    MK_SHIFT_CONST(25)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_WOFFSET                        0x0
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_SHIFT                    MK_SHIFT_CONST(24)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_SHIFT)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_RANGE                    24:24
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_MSB                      MK_SHIFT_CONST(24)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_LSB                      MK_SHIFT_CONST(24)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_WOFFSET                  0x0
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_SHIFT                     MK_SHIFT_CONST(16)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_FIELD                     MK_FIELD_CONST(0xff, I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_SHIFT)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_RANGE                     23:16
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_MSB                       MK_SHIFT_CONST(23)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_LSB                       MK_SHIFT_CONST(16)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_WOFFSET                   0x0
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_MEXT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_SHIFT                     MK_SHIFT_CONST(8)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_FIELD                     MK_FIELD_CONST(0xff, I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_SHIFT)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_RANGE                     15:8
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_MSB                       MK_SHIFT_CONST(15)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_LSB                       MK_SHIFT_CONST(8)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_WOFFSET                   0x0
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TLOW_SEXT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_SHIFT                       MK_SHIFT_CONST(0)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_FIELD                       MK_FIELD_CONST(0xff, I2C_I2C_TLOW_SEXT_0_TIMEOUT_SHIFT)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_RANGE                       7:0
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_MSB                 MK_SHIFT_CONST(7)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_LSB                 MK_SHIFT_CONST(0)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_WOFFSET                     0x0
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_I2C_TLOW_SEXT_0_TIMEOUT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Reserved address 0x38
+
+// Register I2C_I2C_SL_DELAY_COUNT_0
+#define I2C_I2C_SL_DELAY_COUNT_0                        MK_ADDR_CONST(0x3c)
+#define I2C_I2C_SL_DELAY_COUNT_0_SECURE                         0x0
+#define I2C_I2C_SL_DELAY_COUNT_0_DUAL                   0x0
+#define I2C_I2C_SL_DELAY_COUNT_0_SCR                    0
+#define I2C_I2C_SL_DELAY_COUNT_0_SCRREG                         0
+#define I2C_I2C_SL_DELAY_COUNT_0_WORD_COUNT                     0x1
+#define I2C_I2C_SL_DELAY_COUNT_0_RESET_VAL                      MK_MASK_CONST(0x1e)
+#define I2C_I2C_SL_DELAY_COUNT_0_RESET_MASK                     MK_MASK_CONST(0xffff)
+#define I2C_I2C_SL_DELAY_COUNT_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_DELAY_COUNT_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_DELAY_COUNT_0_READ_MASK                      MK_MASK_CONST(0xffff)
+#define I2C_I2C_SL_DELAY_COUNT_0_WRITE_MASK                     MK_MASK_CONST(0xffff)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SHIFT                   MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_FIELD                   MK_FIELD_CONST(0xffff, I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SHIFT)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_RANGE                   15:0
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_MSB                     MK_SHIFT_CONST(15)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_LSB                     MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_WOFFSET                 0x0
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_DEFAULT                 MK_MASK_CONST(0x1e)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_DELAY_COUNT_0_SL_DELAY_COUNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register I2C_I2C_SL_INT_MASK_0
+#define I2C_I2C_SL_INT_MASK_0                   MK_ADDR_CONST(0x40)
+#define I2C_I2C_SL_INT_MASK_0_SECURE                    0x0
+#define I2C_I2C_SL_INT_MASK_0_DUAL                      0x0
+#define I2C_I2C_SL_INT_MASK_0_SCR                       0
+#define I2C_I2C_SL_INT_MASK_0_SCRREG                    0
+#define I2C_I2C_SL_INT_MASK_0_WORD_COUNT                        0x1
+#define I2C_I2C_SL_INT_MASK_0_RESET_VAL                         MK_MASK_CONST(0xfd)
+#define I2C_I2C_SL_INT_MASK_0_RESET_MASK                        MK_MASK_CONST(0xfd)
+#define I2C_I2C_SL_INT_MASK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_READ_MASK                         MK_MASK_CONST(0xfd)
+#define I2C_I2C_SL_INT_MASK_0_WRITE_MASK                        MK_MASK_CONST(0xfd)
+#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_SHIFT                 MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_SHIFT)
+#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_RANGE                 7:7
+#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_MSB                   MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_LSB                   MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_WOFFSET                       0x0
+#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_DEFAULT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_DISABLE                       MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_MASK_0_HW_MSTR_INT_ENABLE                        MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_SHIFT                   MK_SHIFT_CONST(6)
+#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_MASK_0_REPROG_SL_SHIFT)
+#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_RANGE                   6:6
+#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_MSB                     MK_SHIFT_CONST(6)
+#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_LSB                     MK_SHIFT_CONST(6)
+#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_WOFFSET                 0x0
+#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_DEFAULT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_DISABLE                 MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_MASK_0_REPROG_SL_ENABLE                  MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_MASK_0_RST_SL_SHIFT                      MK_SHIFT_CONST(5)
+#define I2C_I2C_SL_INT_MASK_0_RST_SL_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_MASK_0_RST_SL_SHIFT)
+#define I2C_I2C_SL_INT_MASK_0_RST_SL_RANGE                      5:5
+#define I2C_I2C_SL_INT_MASK_0_RST_SL_MSB                        MK_SHIFT_CONST(5)
+#define I2C_I2C_SL_INT_MASK_0_RST_SL_LSB                        MK_SHIFT_CONST(5)
+#define I2C_I2C_SL_INT_MASK_0_RST_SL_WOFFSET                    0x0
+#define I2C_I2C_SL_INT_MASK_0_RST_SL_DEFAULT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_RST_SL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_RST_SL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_RST_SL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_RST_SL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_RST_SL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_RST_SL_DISABLE                    MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_MASK_0_RST_SL_ENABLE                     MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_MASK_0_END_TRANS_SHIFT                   MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_INT_MASK_0_END_TRANS_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_MASK_0_END_TRANS_SHIFT)
+#define I2C_I2C_SL_INT_MASK_0_END_TRANS_RANGE                   4:4
+#define I2C_I2C_SL_INT_MASK_0_END_TRANS_MSB                     MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_INT_MASK_0_END_TRANS_LSB                     MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_INT_MASK_0_END_TRANS_WOFFSET                 0x0
+#define I2C_I2C_SL_INT_MASK_0_END_TRANS_DEFAULT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_END_TRANS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_END_TRANS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_END_TRANS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_END_TRANS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_END_TRANS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_END_TRANS_DISABLE                 MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_MASK_0_END_TRANS_ENABLE                  MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_SHIFT                      MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_MASK_0_SL_IRQ_SHIFT)
+#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_RANGE                      3:3
+#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_MSB                        MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_LSB                        MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_WOFFSET                    0x0
+#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_DEFAULT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_DISABLE                    MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_MASK_0_SL_IRQ_ENABLE                     MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_MASK_0_RCVD_SHIFT                        MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_INT_MASK_0_RCVD_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_MASK_0_RCVD_SHIFT)
+#define I2C_I2C_SL_INT_MASK_0_RCVD_RANGE                        2:2
+#define I2C_I2C_SL_INT_MASK_0_RCVD_MSB                  MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_INT_MASK_0_RCVD_LSB                  MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_INT_MASK_0_RCVD_WOFFSET                      0x0
+#define I2C_I2C_SL_INT_MASK_0_RCVD_DEFAULT                      MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_RCVD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_RCVD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_RCVD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_RCVD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_RCVD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_RCVD_DISABLE                      MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_MASK_0_RCVD_ENABLE                       MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_MASK_0_ZA_SHIFT                  MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_INT_MASK_0_ZA_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_MASK_0_ZA_SHIFT)
+#define I2C_I2C_SL_INT_MASK_0_ZA_RANGE                  0:0
+#define I2C_I2C_SL_INT_MASK_0_ZA_MSB                    MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_INT_MASK_0_ZA_LSB                    MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_INT_MASK_0_ZA_WOFFSET                        0x0
+#define I2C_I2C_SL_INT_MASK_0_ZA_DEFAULT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_ZA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_ZA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_ZA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_ZA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_MASK_0_ZA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_MASK_0_ZA_DISABLE                        MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_MASK_0_ZA_ENABLE                 MK_ENUM_CONST(1)
+
+// Register I2C_I2C_SL_INT_SOURCE_0
+#define I2C_I2C_SL_INT_SOURCE_0                 MK_ADDR_CONST(0x44)
+#define I2C_I2C_SL_INT_SOURCE_0_SECURE                  0x0
+#define I2C_I2C_SL_INT_SOURCE_0_DUAL                    0x0
+#define I2C_I2C_SL_INT_SOURCE_0_SCR                     0
+#define I2C_I2C_SL_INT_SOURCE_0_SCRREG                  0
+#define I2C_I2C_SL_INT_SOURCE_0_WORD_COUNT                      0x1
+#define I2C_I2C_SL_INT_SOURCE_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_RESET_MASK                      MK_MASK_CONST(0xfd)
+#define I2C_I2C_SL_INT_SOURCE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_READ_MASK                       MK_MASK_CONST(0xfd)
+#define I2C_I2C_SL_INT_SOURCE_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_SHIFT                       MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_SHIFT)
+#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_RANGE                       7:7
+#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_MSB                 MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_LSB                 MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_WOFFSET                     0x0
+#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_UNSET                       MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_SOURCE_0_HW_MSTR_INT_SET                 MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_SHIFT                 MK_SHIFT_CONST(6)
+#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_SHIFT)
+#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_RANGE                 6:6
+#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_MSB                   MK_SHIFT_CONST(6)
+#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_LSB                   MK_SHIFT_CONST(6)
+#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_WOFFSET                       0x0
+#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_UNSET                 MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_SOURCE_0_REPROG_SL_SET                   MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_SHIFT                    MK_SHIFT_CONST(5)
+#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SOURCE_0_RST_SL_SHIFT)
+#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_RANGE                    5:5
+#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_MSB                      MK_SHIFT_CONST(5)
+#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_LSB                      MK_SHIFT_CONST(5)
+#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_WOFFSET                  0x0
+#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_UNSET                    MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_SOURCE_0_RST_SL_SET                      MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_SHIFT                 MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SOURCE_0_END_TRANS_SHIFT)
+#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_RANGE                 4:4
+#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_MSB                   MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_LSB                   MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_WOFFSET                       0x0
+#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_UNSET                 MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_SOURCE_0_END_TRANS_SET                   MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_SHIFT                    MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_SHIFT)
+#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_RANGE                    3:3
+#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_MSB                      MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_LSB                      MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_WOFFSET                  0x0
+#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_UNSET                    MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_SOURCE_0_SL_IRQ_SET                      MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_SOURCE_0_RCVD_SHIFT                      MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_INT_SOURCE_0_RCVD_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SOURCE_0_RCVD_SHIFT)
+#define I2C_I2C_SL_INT_SOURCE_0_RCVD_RANGE                      2:2
+#define I2C_I2C_SL_INT_SOURCE_0_RCVD_MSB                        MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_INT_SOURCE_0_RCVD_LSB                        MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_INT_SOURCE_0_RCVD_WOFFSET                    0x0
+#define I2C_I2C_SL_INT_SOURCE_0_RCVD_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_RCVD_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SOURCE_0_RCVD_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_RCVD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_RCVD_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_RCVD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SOURCE_0_RCVD_UNSET                      MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_SOURCE_0_RCVD_SET                        MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_SOURCE_0_ZA_SHIFT                        MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_INT_SOURCE_0_ZA_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SOURCE_0_ZA_SHIFT)
+#define I2C_I2C_SL_INT_SOURCE_0_ZA_RANGE                        0:0
+#define I2C_I2C_SL_INT_SOURCE_0_ZA_MSB                  MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_INT_SOURCE_0_ZA_LSB                  MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_INT_SOURCE_0_ZA_WOFFSET                      0x0
+#define I2C_I2C_SL_INT_SOURCE_0_ZA_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_ZA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SOURCE_0_ZA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_ZA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_ZA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SOURCE_0_ZA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SOURCE_0_ZA_UNSET                        MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_SOURCE_0_ZA_SET                  MK_ENUM_CONST(1)
+
+// Register I2C_I2C_SL_INT_SET_0
+#define I2C_I2C_SL_INT_SET_0                    MK_ADDR_CONST(0x48)
+#define I2C_I2C_SL_INT_SET_0_SECURE                     0x0
+#define I2C_I2C_SL_INT_SET_0_DUAL                       0x0
+#define I2C_I2C_SL_INT_SET_0_SCR                        0
+#define I2C_I2C_SL_INT_SET_0_SCRREG                     0
+#define I2C_I2C_SL_INT_SET_0_WORD_COUNT                         0x1
+#define I2C_I2C_SL_INT_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_RESET_MASK                         MK_MASK_CONST(0xfd)
+#define I2C_I2C_SL_INT_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_READ_MASK                  MK_MASK_CONST(0xfd)
+#define I2C_I2C_SL_INT_SET_0_WRITE_MASK                         MK_MASK_CONST(0xfd)
+#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_SHIFT                  MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_SHIFT)
+#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_RANGE                  7:7
+#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_MSB                    MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_LSB                    MK_SHIFT_CONST(7)
+#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_WOFFSET                        0x0
+#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_UNSET                  MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_SET_0_HW_MSTR_INT_SET                    MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_SET_0_REPROG_SL_SHIFT                    MK_SHIFT_CONST(6)
+#define I2C_I2C_SL_INT_SET_0_REPROG_SL_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SET_0_REPROG_SL_SHIFT)
+#define I2C_I2C_SL_INT_SET_0_REPROG_SL_RANGE                    6:6
+#define I2C_I2C_SL_INT_SET_0_REPROG_SL_MSB                      MK_SHIFT_CONST(6)
+#define I2C_I2C_SL_INT_SET_0_REPROG_SL_LSB                      MK_SHIFT_CONST(6)
+#define I2C_I2C_SL_INT_SET_0_REPROG_SL_WOFFSET                  0x0
+#define I2C_I2C_SL_INT_SET_0_REPROG_SL_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_REPROG_SL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SET_0_REPROG_SL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_REPROG_SL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_REPROG_SL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_REPROG_SL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SET_0_REPROG_SL_UNSET                    MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_SET_0_REPROG_SL_SET                      MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_SET_0_RST_SL_SHIFT                       MK_SHIFT_CONST(5)
+#define I2C_I2C_SL_INT_SET_0_RST_SL_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SET_0_RST_SL_SHIFT)
+#define I2C_I2C_SL_INT_SET_0_RST_SL_RANGE                       5:5
+#define I2C_I2C_SL_INT_SET_0_RST_SL_MSB                 MK_SHIFT_CONST(5)
+#define I2C_I2C_SL_INT_SET_0_RST_SL_LSB                 MK_SHIFT_CONST(5)
+#define I2C_I2C_SL_INT_SET_0_RST_SL_WOFFSET                     0x0
+#define I2C_I2C_SL_INT_SET_0_RST_SL_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_RST_SL_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SET_0_RST_SL_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_RST_SL_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_RST_SL_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_RST_SL_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SET_0_RST_SL_UNSET                       MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_SET_0_RST_SL_SET                 MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_SET_0_END_TRANS_SHIFT                    MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_INT_SET_0_END_TRANS_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SET_0_END_TRANS_SHIFT)
+#define I2C_I2C_SL_INT_SET_0_END_TRANS_RANGE                    4:4
+#define I2C_I2C_SL_INT_SET_0_END_TRANS_MSB                      MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_INT_SET_0_END_TRANS_LSB                      MK_SHIFT_CONST(4)
+#define I2C_I2C_SL_INT_SET_0_END_TRANS_WOFFSET                  0x0
+#define I2C_I2C_SL_INT_SET_0_END_TRANS_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_END_TRANS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SET_0_END_TRANS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_END_TRANS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_END_TRANS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_END_TRANS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SET_0_END_TRANS_UNSET                    MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_SET_0_END_TRANS_SET                      MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_SET_0_SL_IRQ_SHIFT                       MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_INT_SET_0_SL_IRQ_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SET_0_SL_IRQ_SHIFT)
+#define I2C_I2C_SL_INT_SET_0_SL_IRQ_RANGE                       3:3
+#define I2C_I2C_SL_INT_SET_0_SL_IRQ_MSB                 MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_INT_SET_0_SL_IRQ_LSB                 MK_SHIFT_CONST(3)
+#define I2C_I2C_SL_INT_SET_0_SL_IRQ_WOFFSET                     0x0
+#define I2C_I2C_SL_INT_SET_0_SL_IRQ_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_SL_IRQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SET_0_SL_IRQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_SL_IRQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_SL_IRQ_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_SL_IRQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SET_0_SL_IRQ_UNSET                       MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_SET_0_SL_IRQ_SET                 MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_SET_0_RCVD_SHIFT                 MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_INT_SET_0_RCVD_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SET_0_RCVD_SHIFT)
+#define I2C_I2C_SL_INT_SET_0_RCVD_RANGE                 2:2
+#define I2C_I2C_SL_INT_SET_0_RCVD_MSB                   MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_INT_SET_0_RCVD_LSB                   MK_SHIFT_CONST(2)
+#define I2C_I2C_SL_INT_SET_0_RCVD_WOFFSET                       0x0
+#define I2C_I2C_SL_INT_SET_0_RCVD_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_RCVD_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SET_0_RCVD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_RCVD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_RCVD_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_RCVD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SET_0_RCVD_UNSET                 MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_SET_0_RCVD_SET                   MK_ENUM_CONST(1)
+
+#define I2C_I2C_SL_INT_SET_0_ZA_SHIFT                   MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_INT_SET_0_ZA_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_SL_INT_SET_0_ZA_SHIFT)
+#define I2C_I2C_SL_INT_SET_0_ZA_RANGE                   0:0
+#define I2C_I2C_SL_INT_SET_0_ZA_MSB                     MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_INT_SET_0_ZA_LSB                     MK_SHIFT_CONST(0)
+#define I2C_I2C_SL_INT_SET_0_ZA_WOFFSET                 0x0
+#define I2C_I2C_SL_INT_SET_0_ZA_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_ZA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SET_0_ZA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_ZA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_ZA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SL_INT_SET_0_ZA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define I2C_I2C_SL_INT_SET_0_ZA_UNSET                   MK_ENUM_CONST(0)
+#define I2C_I2C_SL_INT_SET_0_ZA_SET                     MK_ENUM_CONST(1)
+
+// Reserved address 0x4c
+
+// Packet I2C_IO_PACKET_HEADER_0
+#define I2C_IO_PACKET_HEADER_0_SIZE 32
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_SHIFT                        MK_SHIFT_CONST(30)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_FIELD                        MK_FIELD_CONST(0x3, I2C_IO_PACKET_HEADER_0_RESERVED0_3_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(30)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_3_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_SHIFT                      MK_SHIFT_CONST(28)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_FIELD                      MK_FIELD_CONST(0x3, I2C_IO_PACKET_HEADER_0_HDRSZ_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_RANGE                      MK_SHIFT_CONST(29):MK_SHIFT_CONST(28)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_ROW                        0
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_ONE                        MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_TWO                        MK_ENUM_CONST(1)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_THREE                      MK_ENUM_CONST(2)
+#define I2C_IO_PACKET_HEADER_0_HDRSZ_FOUR                       MK_ENUM_CONST(3)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_SHIFT                        MK_SHIFT_CONST(26)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_FIELD                        MK_FIELD_CONST(0x3, I2C_IO_PACKET_HEADER_0_RESERVED0_2_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_RANGE                        MK_SHIFT_CONST(27):MK_SHIFT_CONST(26)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_2_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_RESP_PKT_FREQ_SHIFT                      MK_SHIFT_CONST(25)
+#define I2C_IO_PACKET_HEADER_0_RESP_PKT_FREQ_FIELD                      MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_RESP_PKT_FREQ_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESP_PKT_FREQ_RANGE                      MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define I2C_IO_PACKET_HEADER_0_RESP_PKT_FREQ_ROW                        0
+#define I2C_IO_PACKET_HEADER_0_RESP_PKT_FREQ_EOT                        MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_RESP_PKT_FREQ_EACH_PACKET                        MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_RESP_PKT_ENABLE_SHIFT                    MK_SHIFT_CONST(24)
+#define I2C_IO_PACKET_HEADER_0_RESP_PKT_ENABLE_FIELD                    MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_RESP_PKT_ENABLE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESP_PKT_ENABLE_RANGE                    MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define I2C_IO_PACKET_HEADER_0_RESP_PKT_ENABLE_ROW                      0
+#define I2C_IO_PACKET_HEADER_0_RESP_PKT_ENABLE_DISABLE                  MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_RESP_PKT_ENABLE_ENABLE                   MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_PKTID_SHIFT                      MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_PKTID_FIELD                      MK_FIELD_CONST(0xff, I2C_IO_PACKET_HEADER_0_PKTID_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PKTID_RANGE                      MK_SHIFT_CONST(23):MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_PKTID_ROW                        0
+
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_SHIFT                      MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_FIELD                      MK_FIELD_CONST(0xf, I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_RANGE                      MK_SHIFT_CONST(15):MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_ROW                        0
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C1                       MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C2                       MK_ENUM_CONST(1)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_I2C3                       MK_ENUM_CONST(2)
+#define I2C_IO_PACKET_HEADER_0_CONTROLLER_ID_DVC_I2C                    MK_ENUM_CONST(3)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_SHIFT                        MK_SHIFT_CONST(8)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_FIELD                        MK_FIELD_CONST(0xf, I2C_IO_PACKET_HEADER_0_RESERVED0_1_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_RANGE                        MK_SHIFT_CONST(11):MK_SHIFT_CONST(8)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_1_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_SHIFT                   MK_SHIFT_CONST(4)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_FIELD                   MK_FIELD_CONST(0xf, I2C_IO_PACKET_HEADER_0_PROTOCOL_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_RANGE                   MK_SHIFT_CONST(7):MK_SHIFT_CONST(4)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_ROW                     0
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_RESERVED                        MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PROTOCOL_I2C                     MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_SHIFT                        MK_SHIFT_CONST(3)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_FIELD                        MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_RESERVED0_0_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_RANGE                        MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define I2C_IO_PACKET_HEADER_0_RESERVED0_0_ROW                  0
+
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_SHIFT                    MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_FIELD                    MK_FIELD_CONST(0x7, I2C_IO_PACKET_HEADER_0_PKTTYPE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_RANGE                    MK_SHIFT_CONST(2):MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PKTTYPE_ROW                      0
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_SHIFT                        MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_FIELD                        MK_FIELD_CONST(0xffff, I2C_IO_PACKET_HEADER_0_RESERVED1_0_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_RESERVED1_0_ROW                  1
+
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_SHIFT                        MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_FIELD                        MK_FIELD_CONST(0xffff, I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_RANGE                        MK_SHIFT_CONST(15):MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_PAYLOADSIZE_ROW                  1
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_SHIFT                        MK_SHIFT_CONST(23)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_FIELD                        MK_FIELD_CONST(0x1ff, I2C_IO_PACKET_HEADER_0_RESERVED2_0_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(23)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_0_ROW                  2
+
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_SHIFT                    MK_SHIFT_CONST(22)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_FIELD                    MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_HS_MODE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_RANGE                    MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_ROW                      2
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_DISABLE                  MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_HS_MODE_ENABLE                   MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_SHIFT                    MK_SHIFT_CONST(21)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_FIELD                    MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_RANGE                    MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_ROW                      2
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_DISABLE                  MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_CONTUNE_ON_NACK_ENABLE                   MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_SHIFT                    MK_SHIFT_CONST(20)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_FIELD                    MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_RANGE                    MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_ROW                      2
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_DISABLE                  MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_SEND_START_BYTE_ENABLE                   MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_READ_SHIFT                       MK_SHIFT_CONST(19)
+#define I2C_IO_PACKET_HEADER_0_READ_FIELD                       MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_READ_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_READ_RANGE                       MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define I2C_IO_PACKET_HEADER_0_READ_ROW                 2
+#define I2C_IO_PACKET_HEADER_0_READ_WRITE                       MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_READ_READ                        MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_SHIFT                  MK_SHIFT_CONST(18)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_FIELD                  MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_ADDR_MODE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_RANGE                  MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_ROW                    2
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_SEVEN_BIT                      MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_ADDR_MODE_TEN_BIT                        MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_IE_SHIFT                 MK_SHIFT_CONST(17)
+#define I2C_IO_PACKET_HEADER_0_IE_FIELD                 MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_IE_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_IE_RANGE                 MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define I2C_IO_PACKET_HEADER_0_IE_ROW                   2
+#define I2C_IO_PACKET_HEADER_0_IE_DISABLE                       MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_IE_ENABLE                        MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_SHIFT                       MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_FIELD                       MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_REPEAT_START_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_RANGE                       MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_ROW                 2
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_STOP                        MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_REPEAT_START_REPEAT_START                        MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_CONTINUE_XFER_SHIFT                      MK_SHIFT_CONST(15)
+#define I2C_IO_PACKET_HEADER_0_CONTINUE_XFER_FIELD                      MK_FIELD_CONST(0x1, I2C_IO_PACKET_HEADER_0_CONTINUE_XFER_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_CONTINUE_XFER_RANGE                      MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define I2C_IO_PACKET_HEADER_0_CONTINUE_XFER_ROW                        2
+#define I2C_IO_PACKET_HEADER_0_CONTINUE_XFER_DISABLE                    MK_ENUM_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_CONTINUE_XFER_ENABLE                     MK_ENUM_CONST(1)
+
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_SHIFT                     MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_FIELD                     MK_FIELD_CONST(0x7, I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_RANGE                     MK_SHIFT_CONST(14):MK_SHIFT_CONST(12)
+#define I2C_IO_PACKET_HEADER_0_HS_MASTER_ADDR_ROW                       2
+
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_SHIFT                        MK_SHIFT_CONST(10)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_FIELD                        MK_FIELD_CONST(0x3, I2C_IO_PACKET_HEADER_0_RESERVED2_2_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_RANGE                        MK_SHIFT_CONST(11):MK_SHIFT_CONST(10)
+#define I2C_IO_PACKET_HEADER_0_RESERVED2_2_ROW                  2
+
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_SHIFT                 MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_FIELD                 MK_FIELD_CONST(0x3ff, I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_SHIFT)
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_RANGE                 MK_SHIFT_CONST(9):MK_SHIFT_CONST(0)
+#define I2C_IO_PACKET_HEADER_0_SLAVE_ADDR_ROW                   2
+
+// Packet I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SIZE 32
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_3_SHIFT                 MK_SHIFT_CONST(30)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_3_FIELD                 MK_FIELD_CONST(0x3, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_3_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_3_RANGE                 MK_SHIFT_CONST(31):MK_SHIFT_CONST(30)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_3_ROW                   0
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_SHIFT                       MK_SHIFT_CONST(28)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_FIELD                       MK_FIELD_CONST(0x3, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_RANGE                       MK_SHIFT_CONST(29):MK_SHIFT_CONST(28)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_ROW                 0
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_ONE                 MK_ENUM_CONST(0)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_TWO                 MK_ENUM_CONST(1)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_THREE                       MK_ENUM_CONST(2)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HDRSZ_FOUR                        MK_ENUM_CONST(3)
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_2_SHIFT                 MK_SHIFT_CONST(24)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_2_FIELD                 MK_FIELD_CONST(0xf, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_2_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_2_RANGE                 MK_SHIFT_CONST(27):MK_SHIFT_CONST(24)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_2_ROW                   0
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTID_SHIFT                       MK_SHIFT_CONST(16)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTID_FIELD                       MK_FIELD_CONST(0xff, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTID_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTID_RANGE                       MK_SHIFT_CONST(23):MK_SHIFT_CONST(16)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTID_ROW                 0
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_SHIFT                       MK_SHIFT_CONST(12)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_FIELD                       MK_FIELD_CONST(0xf, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_RANGE                       MK_SHIFT_CONST(15):MK_SHIFT_CONST(12)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_ROW                 0
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_I2C1                        MK_ENUM_CONST(0)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_I2C2                        MK_ENUM_CONST(1)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_I2C3                        MK_ENUM_CONST(2)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_CONTROLLER_ID_DVC_I2C                     MK_ENUM_CONST(3)
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_1_SHIFT                 MK_SHIFT_CONST(8)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_1_FIELD                 MK_FIELD_CONST(0xf, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_1_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_1_RANGE                 MK_SHIFT_CONST(11):MK_SHIFT_CONST(8)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_1_ROW                   0
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PROTOCOL_SHIFT                    MK_SHIFT_CONST(4)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PROTOCOL_FIELD                    MK_FIELD_CONST(0xf, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PROTOCOL_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PROTOCOL_RANGE                    MK_SHIFT_CONST(7):MK_SHIFT_CONST(4)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PROTOCOL_ROW                      0
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PROTOCOL_RESERVED                 MK_ENUM_CONST(0)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PROTOCOL_I2C                      MK_ENUM_CONST(1)
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_0_SHIFT                 MK_SHIFT_CONST(3)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_0_FIELD                 MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_0_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_0_RANGE                 MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED0_0_ROW                   0
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTTYPE_SHIFT                     MK_SHIFT_CONST(0)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTTYPE_FIELD                     MK_FIELD_CONST(0x7, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTTYPE_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTTYPE_RANGE                     MK_SHIFT_CONST(2):MK_SHIFT_CONST(0)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PKTTYPE_ROW                       0
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED1_0_SHIFT                 MK_SHIFT_CONST(16)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED1_0_FIELD                 MK_FIELD_CONST(0xffff, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED1_0_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED1_0_RANGE                 MK_SHIFT_CONST(31):MK_SHIFT_CONST(16)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED1_0_ROW                   1
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PAYLOADSIZE_SHIFT                 MK_SHIFT_CONST(0)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PAYLOADSIZE_FIELD                 MK_FIELD_CONST(0xffff, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PAYLOADSIZE_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PAYLOADSIZE_RANGE                 MK_SHIFT_CONST(15):MK_SHIFT_CONST(0)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_PAYLOADSIZE_ROW                   1
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_0_SHIFT                 MK_SHIFT_CONST(27)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_0_FIELD                 MK_FIELD_CONST(0x1f, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_0_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_0_RANGE                 MK_SHIFT_CONST(31):MK_SHIFT_CONST(27)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_0_ROW                   2
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ACK_LAST_BYTE_SHIFT                       MK_SHIFT_CONST(26)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ACK_LAST_BYTE_FIELD                       MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ACK_LAST_BYTE_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ACK_LAST_BYTE_RANGE                       MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ACK_LAST_BYTE_ROW                 2
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ACK_LAST_BYTE_DISABLE                     MK_ENUM_CONST(0)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ACK_LAST_BYTE_ENABLE                      MK_ENUM_CONST(1)
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_FREQ_SHIFT                       MK_SHIFT_CONST(25)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_FREQ_FIELD                       MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_FREQ_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_FREQ_RANGE                       MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_FREQ_ROW                 2
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_FREQ_DISABLE                     MK_ENUM_CONST(0)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_FREQ_ENABLE                      MK_ENUM_CONST(1)
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_ENABLE_SHIFT                     MK_SHIFT_CONST(24)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_ENABLE_FIELD                     MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_ENABLE_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_ENABLE_RANGE                     MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_ENABLE_ROW                       2
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESP_PKT_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_1_SHIFT                 MK_SHIFT_CONST(23)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_1_FIELD                 MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_1_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_1_RANGE                 MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_1_ROW                   2
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HS_MODE_SHIFT                     MK_SHIFT_CONST(22)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HS_MODE_FIELD                     MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HS_MODE_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HS_MODE_RANGE                     MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HS_MODE_ROW                       2
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HS_MODE_DISABLE                   MK_ENUM_CONST(0)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_HS_MODE_ENABLE                    MK_ENUM_CONST(1)
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_2_SHIFT                 MK_SHIFT_CONST(20)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_2_FIELD                 MK_FIELD_CONST(0x3, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_2_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_2_RANGE                 MK_SHIFT_CONST(21):MK_SHIFT_CONST(20)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_2_ROW                   2
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_2_DISABLE                       MK_ENUM_CONST(0)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_2_ENABLE                        MK_ENUM_CONST(1)
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RW_SHIFT                  MK_SHIFT_CONST(19)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RW_FIELD                  MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RW_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RW_RANGE                  MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RW_ROW                    2
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RW_WRITE                  MK_ENUM_CONST(0)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RW_READ                   MK_ENUM_CONST(1)
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ADDR_MODE_SHIFT                   MK_SHIFT_CONST(18)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ADDR_MODE_FIELD                   MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ADDR_MODE_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ADDR_MODE_RANGE                   MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ADDR_MODE_ROW                     2
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ADDR_MODE_SEVEN_BIT                       MK_ENUM_CONST(0)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_ADDR_MODE_TEN_BIT                 MK_ENUM_CONST(1)
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_IE_SHIFT                  MK_SHIFT_CONST(17)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_IE_FIELD                  MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_IE_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_IE_RANGE                  MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_IE_ROW                    2
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_3_SHIFT                 MK_SHIFT_CONST(11)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_3_FIELD                 MK_FIELD_CONST(0x3f, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_3_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_3_RANGE                 MK_SHIFT_CONST(16):MK_SHIFT_CONST(11)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_RESERVED2_3_ROW                   2
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_OVERRIDE_SHIFT                 MK_SHIFT_CONST(10)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_OVERRIDE_FIELD                 MK_FIELD_CONST(0x1, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_OVERRIDE_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_OVERRIDE_RANGE                 MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_OVERRIDE_ROW                   2
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_OVERRIDE_DISABLE                       MK_ENUM_CONST(0)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_OVERRIDE_ENABLE                        MK_ENUM_CONST(1)
+
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_SHIFT                  MK_SHIFT_CONST(0)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_FIELD                  MK_FIELD_CONST(0x3ff, I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_SHIFT)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_RANGE                  MK_SHIFT_CONST(9):MK_SHIFT_CONST(0)
+#define I2C_IO_SLAVE_TRANSMIT_PACKET_HEADER_0_SLAVE_ADDR_ROW                    2
+
+// Packet I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_SIZE 32
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_3_SHIFT                  MK_SHIFT_CONST(23)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_3_FIELD                  MK_FIELD_CONST(0x1ff, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_3_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_3_RANGE                  MK_SHIFT_CONST(31):MK_SHIFT_CONST(23)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_3_ROW                    0
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HS_MODE_SHIFT                      MK_SHIFT_CONST(22)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HS_MODE_FIELD                      MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HS_MODE_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HS_MODE_RANGE                      MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HS_MODE_ROW                        0
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_2_SHIFT                  MK_SHIFT_CONST(19)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_2_FIELD                  MK_FIELD_CONST(0x7, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_2_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_2_RANGE                  MK_SHIFT_CONST(21):MK_SHIFT_CONST(19)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_2_ROW                    0
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ADDR_MODE_SHIFT                    MK_SHIFT_CONST(18)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ADDR_MODE_FIELD                    MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ADDR_MODE_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ADDR_MODE_RANGE                    MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ADDR_MODE_ROW                      0
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_1_SHIFT                  MK_SHIFT_CONST(10)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_1_FIELD                  MK_FIELD_CONST(0xff, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_1_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_1_RANGE                  MK_SHIFT_CONST(17):MK_SHIFT_CONST(10)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED0_1_ROW                    0
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_SLAVE_ADDR_SHIFT                   MK_SHIFT_CONST(0)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_SLAVE_ADDR_FIELD                   MK_FIELD_CONST(0x3ff, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_SLAVE_ADDR_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_SLAVE_ADDR_RANGE                   MK_SHIFT_CONST(9):MK_SHIFT_CONST(0)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_SLAVE_ADDR_ROW                     0
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_0_SHIFT                  MK_SHIFT_CONST(29)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_0_FIELD                  MK_FIELD_CONST(0x7, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_0_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_0_RANGE                  MK_SHIFT_CONST(31):MK_SHIFT_CONST(29)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_0_ROW                    1
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ACK_WITHHELD_SHIFT                 MK_SHIFT_CONST(28)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ACK_WITHHELD_FIELD                 MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ACK_WITHHELD_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ACK_WITHHELD_RANGE                 MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ACK_WITHHELD_ROW                   1
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_XFER_ERR_REASON_SHIFT                      MK_SHIFT_CONST(27)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_XFER_ERR_REASON_FIELD                      MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_XFER_ERR_REASON_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_XFER_ERR_REASON_RANGE                      MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_XFER_ERR_REASON_ROW                        1
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_PKT_XFER_ERR_SHIFT                 MK_SHIFT_CONST(26)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_PKT_XFER_ERR_FIELD                 MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_PKT_XFER_ERR_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_PKT_XFER_ERR_RANGE                 MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_PKT_XFER_ERR_ROW                   1
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TFIFO_OVF_SHIFT                    MK_SHIFT_CONST(25)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TFIFO_OVF_FIELD                    MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TFIFO_OVF_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TFIFO_OVF_RANGE                    MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TFIFO_OVF_ROW                      1
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RFIFO_UNF_SHIFT                    MK_SHIFT_CONST(24)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RFIFO_UNF_FIELD                    MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RFIFO_UNF_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RFIFO_UNF_RANGE                    MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RFIFO_UNF_ROW                      1
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TRANSFER_PKT_ID_SHIFT                      MK_SHIFT_CONST(16)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TRANSFER_PKT_ID_FIELD                      MK_FIELD_CONST(0xff, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TRANSFER_PKT_ID_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TRANSFER_PKT_ID_RANGE                      MK_SHIFT_CONST(23):MK_SHIFT_CONST(16)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_TRANSFER_PKT_ID_ROW                        1
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_1_SHIFT                  MK_SHIFT_CONST(15)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_1_FIELD                  MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_1_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_1_RANGE                  MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_1_ROW                    1
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_ADDR_SHIFT                 MK_SHIFT_CONST(8)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_ADDR_FIELD                 MK_FIELD_CONST(0x7f, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_ADDR_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_ADDR_RANGE                 MK_SHIFT_CONST(14):MK_SHIFT_CONST(8)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_ADDR_ROW                   1
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_2_SHIFT                  MK_SHIFT_CONST(7)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_2_FIELD                  MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_2_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_2_RANGE                  MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_2_ROW                    1
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_IRQ_SHIFT                  MK_SHIFT_CONST(6)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_IRQ_FIELD                  MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_IRQ_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_IRQ_RANGE                  MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_HW_MSTR_IRQ_ROW                    1
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_REPROG_SL_SHIFT                    MK_SHIFT_CONST(5)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_REPROG_SL_FIELD                    MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_REPROG_SL_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_REPROG_SL_RANGE                    MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_REPROG_SL_ROW                      1
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RST_SL_SHIFT                       MK_SHIFT_CONST(4)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RST_SL_FIELD                       MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RST_SL_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RST_SL_RANGE                       MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RST_SL_ROW                 1
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_3_SHIFT                  MK_SHIFT_CONST(2)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_3_FIELD                  MK_FIELD_CONST(0x3, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_3_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_3_RANGE                  MK_SHIFT_CONST(3):MK_SHIFT_CONST(2)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RESERVED1_3_ROW                    1
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RW_SHIFT                   MK_SHIFT_CONST(1)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RW_FIELD                   MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RW_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RW_RANGE                   MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_RW_ROW                     1
+
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ZA_SHIFT                   MK_SHIFT_CONST(0)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ZA_FIELD                   MK_FIELD_CONST(0x1, I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ZA_SHIFT)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ZA_RANGE                   MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define I2C_IO_SLAVE_RECEIVE_PACKET_HEADER_0_ZA_ROW                     1
+
+// Register I2C_I2C_TX_PACKET_FIFO_0
+#define I2C_I2C_TX_PACKET_FIFO_0                        MK_ADDR_CONST(0x50)
+#define I2C_I2C_TX_PACKET_FIFO_0_SECURE                         0x0
+#define I2C_I2C_TX_PACKET_FIFO_0_DUAL                   0x0
+#define I2C_I2C_TX_PACKET_FIFO_0_SCR                    0
+#define I2C_I2C_TX_PACKET_FIFO_0_SCRREG                         0
+#define I2C_I2C_TX_PACKET_FIFO_0_WORD_COUNT                     0x1
+#define I2C_I2C_TX_PACKET_FIFO_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define I2C_I2C_TX_PACKET_FIFO_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_TX_PACKET_FIFO_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define I2C_I2C_TX_PACKET_FIFO_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_TX_PACKET_FIFO_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_TX_PACKET_FIFO_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_SHIFT                        MK_SHIFT_CONST(0)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_FIELD                        MK_FIELD_CONST(0xffffffff, I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_SHIFT)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_RANGE                        31:0
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_MSB                  MK_SHIFT_CONST(31)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_LSB                  MK_SHIFT_CONST(0)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_WOFFSET                      0x0
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_TX_PACKET_FIFO_0_TX_PACKET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register I2C_I2C_RX_FIFO_0
+#define I2C_I2C_RX_FIFO_0                       MK_ADDR_CONST(0x54)
+#define I2C_I2C_RX_FIFO_0_SECURE                        0x0
+#define I2C_I2C_RX_FIFO_0_DUAL                  0x0
+#define I2C_I2C_RX_FIFO_0_SCR                   0
+#define I2C_I2C_RX_FIFO_0_SCRREG                        0
+#define I2C_I2C_RX_FIFO_0_WORD_COUNT                    0x1
+#define I2C_I2C_RX_FIFO_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_RX_FIFO_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_RX_FIFO_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, I2C_I2C_RX_FIFO_0_RD_DATA_SHIFT)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_RANGE                 31:0
+#define I2C_I2C_RX_FIFO_0_RD_DATA_MSB                   MK_SHIFT_CONST(31)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_LSB                   MK_SHIFT_CONST(0)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_WOFFSET                       0x0
+#define I2C_I2C_RX_FIFO_0_RD_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_RX_FIFO_0_RD_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register I2C_PACKET_TRANSFER_STATUS_0
+#define I2C_PACKET_TRANSFER_STATUS_0                    MK_ADDR_CONST(0x58)
+#define I2C_PACKET_TRANSFER_STATUS_0_SECURE                     0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_DUAL                       0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_SCR                        0
+#define I2C_PACKET_TRANSFER_STATUS_0_SCRREG                     0
+#define I2C_PACKET_TRANSFER_STATUS_0_WORD_COUNT                         0x1
+#define I2C_PACKET_TRANSFER_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x1ffffff)
+#define I2C_PACKET_TRANSFER_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_READ_MASK                  MK_MASK_CONST(0x1ffffff)
+#define I2C_PACKET_TRANSFER_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SHIFT                    MK_SHIFT_CONST(24)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_FIELD                    MK_FIELD_CONST(0x1, I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_RANGE                    24:24
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_MSB                      MK_SHIFT_CONST(24)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_LSB                      MK_SHIFT_CONST(24)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_WOFFSET                  0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_UNSET                    MK_ENUM_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_COMPLETE_SET                      MK_ENUM_CONST(1)
+
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SHIFT                      MK_SHIFT_CONST(16)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_FIELD                      MK_FIELD_CONST(0xff, I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_RANGE                      23:16
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_MSB                        MK_SHIFT_CONST(23)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_LSB                        MK_SHIFT_CONST(16)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_WOFFSET                    0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_DEFAULT_MASK                       MK_MASK_CONST(0xff)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_PKT_ID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SHIFT                     MK_SHIFT_CONST(4)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_FIELD                     MK_FIELD_CONST(0xfff, I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_RANGE                     15:4
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_MSB                       MK_SHIFT_CONST(15)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_LSB                       MK_SHIFT_CONST(4)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_WOFFSET                   0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_DEFAULT_MASK                      MK_MASK_CONST(0xfff)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_TRANSFER_BYTENUM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SHIFT                       MK_SHIFT_CONST(3)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_FIELD                       MK_FIELD_CONST(0x1, I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_RANGE                       3:3
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_MSB                 MK_SHIFT_CONST(3)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_LSB                 MK_SHIFT_CONST(3)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_WOFFSET                     0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_UNSET                       MK_ENUM_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_ADDR_SET                 MK_ENUM_CONST(1)
+
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SHIFT                       MK_SHIFT_CONST(2)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_FIELD                       MK_FIELD_CONST(0x1, I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_RANGE                       2:2
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_MSB                 MK_SHIFT_CONST(2)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_LSB                 MK_SHIFT_CONST(2)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_WOFFSET                     0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_UNSET                       MK_ENUM_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_NOACK_FOR_DATA_SET                 MK_ENUM_CONST(1)
+
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SHIFT                     MK_SHIFT_CONST(1)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_FIELD                     MK_FIELD_CONST(0x1, I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_RANGE                     1:1
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_MSB                       MK_SHIFT_CONST(1)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_LSB                       MK_SHIFT_CONST(1)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_WOFFSET                   0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_UNSET                     MK_ENUM_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_ARB_LOST_SET                       MK_ENUM_CONST(1)
+
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SHIFT                      MK_SHIFT_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_FIELD                      MK_FIELD_CONST(0x1, I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SHIFT)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_RANGE                      0:0
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_MSB                        MK_SHIFT_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_LSB                        MK_SHIFT_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_WOFFSET                    0x0
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_UNSET                      MK_ENUM_CONST(0)
+#define I2C_PACKET_TRANSFER_STATUS_0_CONTROLLER_BUSY_SET                        MK_ENUM_CONST(1)
+
+// Register I2C_INTERRUPT_MASK_REGISTER_0
+#define I2C_INTERRUPT_MASK_REGISTER_0                   MK_ADDR_CONST(0x64)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SECURE                    0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_DUAL                      0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_SCR                       0
+#define I2C_INTERRUPT_MASK_REGISTER_0_SCRREG                    0
+#define I2C_INTERRUPT_MASK_REGISTER_0_WORD_COUNT                        0x1
+#define I2C_INTERRUPT_MASK_REGISTER_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RESET_MASK                        MK_MASK_CONST(0x1ff30fff)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_READ_MASK                         MK_MASK_CONST(0x1ff30fff)
+#define I2C_INTERRUPT_MASK_REGISTER_0_WRITE_MASK                        MK_MASK_CONST(0x1ff30fff)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_SHIFT                     MK_SHIFT_CONST(28)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_FIELD                     MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_RANGE                     28:28
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_MSB                       MK_SHIFT_CONST(28)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_LSB                       MK_SHIFT_CONST(28)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_WOFFSET                   0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_DISABLE                   MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_ACK_WITHHELD_INT_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_SHIFT                    MK_SHIFT_CONST(27)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_RANGE                    27:27
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_MSB                      MK_SHIFT_CONST(27)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_LSB                      MK_SHIFT_CONST(27)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_WOFFSET                  0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_DISABLE                  MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RD2WR_INT_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_SHIFT                    MK_SHIFT_CONST(26)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_RANGE                    26:26
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_MSB                      MK_SHIFT_CONST(26)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_LSB                      MK_SHIFT_CONST(26)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_WOFFSET                  0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_DISABLE                  MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_WR2RD_INT_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_SHIFT                     MK_SHIFT_CONST(25)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_FIELD                     MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_RANGE                     25:25
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_MSB                       MK_SHIFT_CONST(25)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_LSB                       MK_SHIFT_CONST(25)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_WOFFSET                   0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_DISABLE                   MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PKT_XFER_ERR_INT_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_SHIFT                    MK_SHIFT_CONST(24)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_RANGE                    24:24
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_MSB                      MK_SHIFT_CONST(24)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_LSB                      MK_SHIFT_CONST(24)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_WOFFSET                  0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_DISABLE                  MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TX_BUFFER_REQ_INT_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_SHIFT                 MK_SHIFT_CONST(23)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_RANGE                 23:23
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_MSB                   MK_SHIFT_CONST(23)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_LSB                   MK_SHIFT_CONST(23)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_WOFFSET                       0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_DISABLE                       MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RX_BUFFER_FILLED_INT_EN_ENABLE                        MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_SHIFT                     MK_SHIFT_CONST(22)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_FIELD                     MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_RANGE                     22:22
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_MSB                       MK_SHIFT_CONST(22)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_LSB                       MK_SHIFT_CONST(22)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_WOFFSET                   0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_DISABLE                   MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_PACKET_XFER_COMPLETE_INT_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_SHIFT                    MK_SHIFT_CONST(21)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_RANGE                    21:21
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_MSB                      MK_SHIFT_CONST(21)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_LSB                      MK_SHIFT_CONST(21)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_WOFFSET                  0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_DISABLE                  MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_OVF_REQ_INT_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_SHIFT                    MK_SHIFT_CONST(20)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_RANGE                    20:20
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_MSB                      MK_SHIFT_CONST(20)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_LSB                      MK_SHIFT_CONST(20)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_WOFFSET                  0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_DISABLE                  MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_UNF_REQ_INT_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_SHIFT                   MK_SHIFT_CONST(17)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_FIELD                   MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_RANGE                   17:17
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_MSB                     MK_SHIFT_CONST(17)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_LSB                     MK_SHIFT_CONST(17)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_WOFFSET                 0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_DISABLE                 MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_TFIFO_DATA_REQ_INT_EN_ENABLE                  MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_SHIFT                   MK_SHIFT_CONST(16)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_FIELD                   MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_RANGE                   16:16
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_MSB                     MK_SHIFT_CONST(16)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_LSB                     MK_SHIFT_CONST(16)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_WOFFSET                 0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_DISABLE                 MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_SLV_RFIFO_DATA_REQ_INT_EN_ENABLE                  MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_SHIFT                       MK_SHIFT_CONST(11)
+#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_FIELD                       MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_RANGE                       11:11
+#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_MSB                 MK_SHIFT_CONST(11)
+#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_LSB                 MK_SHIFT_CONST(11)
+#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_WOFFSET                     0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_DISABLE                     MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_BUS_CLEAR_DONE_INT_EN_ENABLE                      MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_SHIFT                        MK_SHIFT_CONST(10)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_FIELD                        MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_RANGE                        10:10
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_MSB                  MK_SHIFT_CONST(10)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_LSB                  MK_SHIFT_CONST(10)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_WOFFSET                      0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_DISABLE                      MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_MEXT_TIMEOUT_EN_ENABLE                       MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_SHIFT                        MK_SHIFT_CONST(9)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_FIELD                        MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_RANGE                        9:9
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_MSB                  MK_SHIFT_CONST(9)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_LSB                  MK_SHIFT_CONST(9)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_WOFFSET                      0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_DISABLE                      MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TLOW_SEXT_TIMEOUT_EN_ENABLE                       MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_SHIFT                      MK_SHIFT_CONST(8)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_FIELD                      MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_RANGE                      8:8
+#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_MSB                        MK_SHIFT_CONST(8)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_LSB                        MK_SHIFT_CONST(8)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_WOFFSET                    0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_DISABLE                    MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TIMEOUT_INT_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_SHIFT                 MK_SHIFT_CONST(7)
+#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_RANGE                 7:7
+#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_MSB                   MK_SHIFT_CONST(7)
+#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_LSB                   MK_SHIFT_CONST(7)
+#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_WOFFSET                       0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_DISABLE                       MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_PACKET_XFER_COMPLETE_INT_EN_ENABLE                        MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SHIFT                    MK_SHIFT_CONST(6)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_RANGE                    6:6
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_MSB                      MK_SHIFT_CONST(6)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_LSB                      MK_SHIFT_CONST(6)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_WOFFSET                  0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_DISABLE                  MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_INT_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SHIFT                    MK_SHIFT_CONST(5)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_RANGE                    5:5
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_MSB                      MK_SHIFT_CONST(5)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_LSB                      MK_SHIFT_CONST(5)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_WOFFSET                  0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_DISABLE                  MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_OVF_INT_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SHIFT                    MK_SHIFT_CONST(4)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_RANGE                    4:4
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_MSB                      MK_SHIFT_CONST(4)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_LSB                      MK_SHIFT_CONST(4)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_WOFFSET                  0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_DISABLE                  MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_UNF_INT_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SHIFT                        MK_SHIFT_CONST(3)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_FIELD                        MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_RANGE                        3:3
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_MSB                  MK_SHIFT_CONST(3)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_LSB                  MK_SHIFT_CONST(3)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_WOFFSET                      0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_DISABLE                      MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_NOACK_INT_EN_ENABLE                       MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SHIFT                     MK_SHIFT_CONST(2)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_FIELD                     MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_RANGE                     2:2
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_MSB                       MK_SHIFT_CONST(2)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_LSB                       MK_SHIFT_CONST(2)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_WOFFSET                   0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_DISABLE                   MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_ARB_LOST_INT_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SHIFT                       MK_SHIFT_CONST(1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_FIELD                       MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_RANGE                       1:1
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_MSB                 MK_SHIFT_CONST(1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_LSB                 MK_SHIFT_CONST(1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_WOFFSET                     0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_DISABLE                     MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_TFIFO_DATA_REQ_INT_EN_ENABLE                      MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SHIFT                       MK_SHIFT_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_FIELD                       MK_FIELD_CONST(0x1, I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SHIFT)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_RANGE                       0:0
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_MSB                 MK_SHIFT_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_LSB                 MK_SHIFT_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_WOFFSET                     0x0
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_DISABLE                     MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_MASK_REGISTER_0_RFIFO_DATA_REQ_INT_EN_ENABLE                      MK_ENUM_CONST(1)
+
+// Register I2C_INTERRUPT_STATUS_REGISTER_0
+#define I2C_INTERRUPT_STATUS_REGISTER_0                 MK_ADDR_CONST(0x68)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SECURE                  0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_DUAL                    0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SCR                     0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SCRREG                  0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_WORD_COUNT                      0x1
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RESET_MASK                      MK_MASK_CONST(0x1ff30fff)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_READ_MASK                       MK_MASK_CONST(0x1ff30fff)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_WRITE_MASK                      MK_MASK_CONST(0x1ff00ffc)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_SHIFT                  MK_SHIFT_CONST(28)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_FIELD                  MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_RANGE                  28:28
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_MSB                    MK_SHIFT_CONST(28)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_LSB                    MK_SHIFT_CONST(28)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_WOFFSET                        0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_UNSET                  MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_ACK_WITHHELD_SET                    MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_SHIFT                 MK_SHIFT_CONST(27)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_RANGE                 27:27
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_MSB                   MK_SHIFT_CONST(27)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_LSB                   MK_SHIFT_CONST(27)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_WOFFSET                       0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_UNSET                 MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RD2WR_SET                   MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_SHIFT                 MK_SHIFT_CONST(26)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_RANGE                 26:26
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_MSB                   MK_SHIFT_CONST(26)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_LSB                   MK_SHIFT_CONST(26)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_WOFFSET                       0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_UNSET                 MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_WR2RD_SET                   MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_SHIFT                  MK_SHIFT_CONST(25)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_FIELD                  MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_RANGE                  25:25
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_MSB                    MK_SHIFT_CONST(25)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_LSB                    MK_SHIFT_CONST(25)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_WOFFSET                        0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_UNSET                  MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PKT_XFER_ERR_SET                    MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_SHIFT                 MK_SHIFT_CONST(24)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_RANGE                 24:24
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_MSB                   MK_SHIFT_CONST(24)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_LSB                   MK_SHIFT_CONST(24)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_WOFFSET                       0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_UNSET                 MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TX_BUFFER_REQ_SET                   MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_SHIFT                      MK_SHIFT_CONST(23)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_FIELD                      MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_RANGE                      23:23
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_MSB                        MK_SHIFT_CONST(23)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_LSB                        MK_SHIFT_CONST(23)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_WOFFSET                    0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_UNSET                      MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RX_BUFFER_FILLED_SET                        MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SHIFT                  MK_SHIFT_CONST(22)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_FIELD                  MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_RANGE                  22:22
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_MSB                    MK_SHIFT_CONST(22)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_LSB                    MK_SHIFT_CONST(22)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_WOFFSET                        0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_UNSET                  MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SET                    MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_SHIFT                     MK_SHIFT_CONST(21)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_FIELD                     MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_RANGE                     21:21
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_MSB                       MK_SHIFT_CONST(21)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_LSB                       MK_SHIFT_CONST(21)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_WOFFSET                   0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_UNSET                     MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_OVF_SET                       MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_SHIFT                     MK_SHIFT_CONST(20)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_FIELD                     MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_RANGE                     20:20
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_MSB                       MK_SHIFT_CONST(20)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_LSB                       MK_SHIFT_CONST(20)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_WOFFSET                   0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_UNSET                     MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_UNF_SET                       MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_SHIFT                        MK_SHIFT_CONST(17)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_FIELD                        MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_RANGE                        17:17
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_MSB                  MK_SHIFT_CONST(17)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_LSB                  MK_SHIFT_CONST(17)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_WOFFSET                      0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_UNSET                        MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_TFIFO_DATA_REQ_SET                  MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_SHIFT                        MK_SHIFT_CONST(16)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_FIELD                        MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_RANGE                        16:16
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_MSB                  MK_SHIFT_CONST(16)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_LSB                  MK_SHIFT_CONST(16)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_WOFFSET                      0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_UNSET                        MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_SLV_RFIFO_DATA_REQ_SET                  MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_SHIFT                    MK_SHIFT_CONST(11)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_RANGE                    11:11
+#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_MSB                      MK_SHIFT_CONST(11)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_LSB                      MK_SHIFT_CONST(11)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_WOFFSET                  0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_UNSET                    MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_BUS_CLEAR_DONE_SET                      MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_SHIFT                 MK_SHIFT_CONST(10)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_RANGE                 10:10
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_MSB                   MK_SHIFT_CONST(10)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_LSB                   MK_SHIFT_CONST(10)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_WOFFSET                       0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_UNSET                 MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_MEXT_TIMEOUT_SET                   MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_SHIFT                 MK_SHIFT_CONST(9)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_RANGE                 9:9
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_MSB                   MK_SHIFT_CONST(9)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_LSB                   MK_SHIFT_CONST(9)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_WOFFSET                       0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_UNSET                 MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TLOW_SEXT_TIMEOUT_SET                   MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_SHIFT                   MK_SHIFT_CONST(8)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_FIELD                   MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_RANGE                   8:8
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_MSB                     MK_SHIFT_CONST(8)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_LSB                     MK_SHIFT_CONST(8)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_WOFFSET                 0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_UNSET                   MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TIMEOUT_SET                     MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT                      MK_SHIFT_CONST(7)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_FIELD                      MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_RANGE                      7:7
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_MSB                        MK_SHIFT_CONST(7)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_LSB                        MK_SHIFT_CONST(7)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_WOFFSET                    0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_UNSET                      MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_PACKET_XFER_COMPLETE_SET                        MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT                 MK_SHIFT_CONST(6)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_RANGE                 6:6
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_MSB                   MK_SHIFT_CONST(6)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_LSB                   MK_SHIFT_CONST(6)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_WOFFSET                       0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_UNSET                 MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SET                   MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SHIFT                 MK_SHIFT_CONST(5)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_RANGE                 5:5
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_MSB                   MK_SHIFT_CONST(5)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_LSB                   MK_SHIFT_CONST(5)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_WOFFSET                       0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_UNSET                 MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_OVF_SET                   MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SHIFT                 MK_SHIFT_CONST(4)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_FIELD                 MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_RANGE                 4:4
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_MSB                   MK_SHIFT_CONST(4)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_LSB                   MK_SHIFT_CONST(4)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_WOFFSET                       0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_UNSET                 MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_UNF_SET                   MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SHIFT                     MK_SHIFT_CONST(3)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_FIELD                     MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_RANGE                     3:3
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_MSB                       MK_SHIFT_CONST(3)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_LSB                       MK_SHIFT_CONST(3)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_WOFFSET                   0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_UNSET                     MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_NOACK_SET                       MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SHIFT                  MK_SHIFT_CONST(2)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_FIELD                  MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_RANGE                  2:2
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_MSB                    MK_SHIFT_CONST(2)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_LSB                    MK_SHIFT_CONST(2)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_WOFFSET                        0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_UNSET                  MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_ARB_LOST_SET                    MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SHIFT                    MK_SHIFT_CONST(1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_RANGE                    1:1
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_MSB                      MK_SHIFT_CONST(1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_LSB                      MK_SHIFT_CONST(1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_WOFFSET                  0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_UNSET                    MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_TFIFO_DATA_REQ_SET                      MK_ENUM_CONST(1)
+
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SHIFT                    MK_SHIFT_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_FIELD                    MK_FIELD_CONST(0x1, I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SHIFT)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_RANGE                    0:0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_MSB                      MK_SHIFT_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_LSB                      MK_SHIFT_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_WOFFSET                  0x0
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_UNSET                    MK_ENUM_CONST(0)
+#define I2C_INTERRUPT_STATUS_REGISTER_0_RFIFO_DATA_REQ_SET                      MK_ENUM_CONST(1)
+
+// Register I2C_I2C_CLK_DIVISOR_REGISTER_0
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0                  MK_ADDR_CONST(0x6c)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_SECURE                   0x0
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_DUAL                     0x0
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_SCR                      0
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_SCRREG                   0
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_WORD_COUNT                       0x1
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_RESET_VAL                        MK_MASK_CONST(0x190001)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT                      MK_SHIFT_CONST(16)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_FIELD                      MK_FIELD_CONST(0xffff, I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_SHIFT)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_RANGE                      31:16
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_MSB                        MK_SHIFT_CONST(31)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_LSB                        MK_SHIFT_CONST(16)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_WOFFSET                    0x0
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_DEFAULT                    MK_MASK_CONST(0x19)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE__PROD_C_SM                 MK_ENUM_CONST(79)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE__PROD_C_FM                 MK_ENUM_CONST(88)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE__PROD_C_FMPLUS                     MK_ENUM_CONST(36)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_STD_FAST_MODE__PROD_C_HS                 MK_ENUM_CONST(88)
+
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SHIFT                     MK_SHIFT_CONST(0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_FIELD                     MK_FIELD_CONST(0xffff, I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SHIFT)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_RANGE                     15:0
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_MSB                       MK_SHIFT_CONST(15)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_LSB                       MK_SHIFT_CONST(0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_WOFFSET                   0x0
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_DEFAULT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_CLK_DIVISOR_REGISTER_0_I2C_CLK_DIVISOR_HSMODE__PROD_C_HS                        MK_ENUM_CONST(2)
+
+#define REG_OFFSET_WIDTH        16
+#define SLV_HIF_SM_WIDTH        5
+#define SLV_HIF_TXFIFO_SM_WIDTH 3
+
+// Register I2C_I2C_INTERRUPT_SOURCE_REGISTER_0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0                     MK_ADDR_CONST(0x70)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SECURE                      0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_DUAL                        0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SCR                         0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SCRREG                      0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_WORD_COUNT                  0x1
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RESET_MASK                  MK_MASK_CONST(0x1ff30fff)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_READ_MASK                   MK_MASK_CONST(0x1ff30fff)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_SHIFT                      MK_SHIFT_CONST(28)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_RANGE                      28:28
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_MSB                        MK_SHIFT_CONST(28)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_LSB                        MK_SHIFT_CONST(28)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_WOFFSET                    0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_UNSET                      MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_ACK_WITHHELD_SET                        MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_SHIFT                     MK_SHIFT_CONST(27)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_RANGE                     27:27
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_MSB                       MK_SHIFT_CONST(27)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_LSB                       MK_SHIFT_CONST(27)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_WOFFSET                   0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_UNSET                     MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RD2WR_SET                       MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_SHIFT                     MK_SHIFT_CONST(26)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_RANGE                     26:26
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_MSB                       MK_SHIFT_CONST(26)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_LSB                       MK_SHIFT_CONST(26)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_WOFFSET                   0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_UNSET                     MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_WR2RD_SET                       MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_SHIFT                      MK_SHIFT_CONST(25)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_RANGE                      25:25
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_MSB                        MK_SHIFT_CONST(25)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_LSB                        MK_SHIFT_CONST(25)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_WOFFSET                    0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_UNSET                      MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PKT_XFER_ERR_SET                        MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_SHIFT                     MK_SHIFT_CONST(24)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_RANGE                     24:24
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_MSB                       MK_SHIFT_CONST(24)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_LSB                       MK_SHIFT_CONST(24)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_WOFFSET                   0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_UNSET                     MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TX_BUFFER_REQ_SET                       MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_SHIFT                  MK_SHIFT_CONST(23)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_RANGE                  23:23
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_MSB                    MK_SHIFT_CONST(23)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_LSB                    MK_SHIFT_CONST(23)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_WOFFSET                        0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_UNSET                  MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RX_BUFFER_FILLED_SET                    MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SHIFT                      MK_SHIFT_CONST(22)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_RANGE                      22:22
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_MSB                        MK_SHIFT_CONST(22)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_LSB                        MK_SHIFT_CONST(22)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_WOFFSET                    0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_UNSET                      MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SET                        MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_SHIFT                 MK_SHIFT_CONST(21)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_RANGE                 21:21
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_MSB                   MK_SHIFT_CONST(21)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_LSB                   MK_SHIFT_CONST(21)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_WOFFSET                       0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_UNSET                 MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_OVF_SET                   MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_SHIFT                 MK_SHIFT_CONST(20)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_RANGE                 20:20
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_MSB                   MK_SHIFT_CONST(20)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_LSB                   MK_SHIFT_CONST(20)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_WOFFSET                       0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_UNSET                 MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_UNF_SET                   MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_SHIFT                    MK_SHIFT_CONST(17)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_RANGE                    17:17
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_MSB                      MK_SHIFT_CONST(17)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_LSB                      MK_SHIFT_CONST(17)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_WOFFSET                  0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_UNSET                    MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_TFIFO_DATA_REQ_SET                      MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_SHIFT                    MK_SHIFT_CONST(16)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_RANGE                    16:16
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_MSB                      MK_SHIFT_CONST(16)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_LSB                      MK_SHIFT_CONST(16)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_WOFFSET                  0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_UNSET                    MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_SLV_RFIFO_DATA_REQ_SET                      MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_SHIFT                        MK_SHIFT_CONST(11)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_RANGE                        11:11
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_MSB                  MK_SHIFT_CONST(11)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_LSB                  MK_SHIFT_CONST(11)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_WOFFSET                      0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_UNSET                        MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_BUS_CLEAR_DONE_SET                  MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_SHIFT                     MK_SHIFT_CONST(10)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_RANGE                     10:10
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_MSB                       MK_SHIFT_CONST(10)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_LSB                       MK_SHIFT_CONST(10)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_WOFFSET                   0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_UNSET                     MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_MEXT_TIMEOUT_SET                       MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_SHIFT                     MK_SHIFT_CONST(9)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_RANGE                     9:9
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_MSB                       MK_SHIFT_CONST(9)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_LSB                       MK_SHIFT_CONST(9)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_WOFFSET                   0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_UNSET                     MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TLOW_SEXT_TIMEOUT_SET                       MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_SHIFT                       MK_SHIFT_CONST(8)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_FIELD                       MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_RANGE                       8:8
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_MSB                 MK_SHIFT_CONST(8)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_LSB                 MK_SHIFT_CONST(8)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_WOFFSET                     0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_UNSET                       MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TIMEOUT_SET                 MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT                  MK_SHIFT_CONST(7)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_RANGE                  7:7
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_MSB                    MK_SHIFT_CONST(7)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_LSB                    MK_SHIFT_CONST(7)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_WOFFSET                        0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_UNSET                  MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_PACKET_XFER_COMPLETE_SET                    MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT                     MK_SHIFT_CONST(6)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_RANGE                     6:6
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_MSB                       MK_SHIFT_CONST(6)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_LSB                       MK_SHIFT_CONST(6)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_WOFFSET                   0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_UNSET                     MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SET                       MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_SHIFT                     MK_SHIFT_CONST(5)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_RANGE                     5:5
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_MSB                       MK_SHIFT_CONST(5)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_LSB                       MK_SHIFT_CONST(5)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_WOFFSET                   0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_UNSET                     MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_OVF_SET                       MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_SHIFT                     MK_SHIFT_CONST(4)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_RANGE                     4:4
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_MSB                       MK_SHIFT_CONST(4)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_LSB                       MK_SHIFT_CONST(4)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_WOFFSET                   0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_UNSET                     MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_UNF_SET                       MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_SHIFT                 MK_SHIFT_CONST(3)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_RANGE                 3:3
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_MSB                   MK_SHIFT_CONST(3)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_LSB                   MK_SHIFT_CONST(3)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_WOFFSET                       0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_UNSET                 MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_NOACK_SET                   MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_SHIFT                      MK_SHIFT_CONST(2)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_RANGE                      2:2
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_MSB                        MK_SHIFT_CONST(2)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_LSB                        MK_SHIFT_CONST(2)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_WOFFSET                    0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_UNSET                      MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_ARB_LOST_SET                        MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_SHIFT                        MK_SHIFT_CONST(1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_RANGE                        1:1
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_MSB                  MK_SHIFT_CONST(1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_LSB                  MK_SHIFT_CONST(1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_WOFFSET                      0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_UNSET                        MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_TFIFO_DATA_REQ_SET                  MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_SHIFT                        MK_SHIFT_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_SHIFT)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_RANGE                        0:0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_MSB                  MK_SHIFT_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_LSB                  MK_SHIFT_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_WOFFSET                      0x0
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_UNSET                        MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SOURCE_REGISTER_0_RFIFO_DATA_REQ_SET                  MK_ENUM_CONST(1)
+
+// Register I2C_I2C_INTERRUPT_SET_REGISTER_0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0                        MK_ADDR_CONST(0x74)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SECURE                         0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_DUAL                   0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SCR                    0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SCRREG                         0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_WORD_COUNT                     0x1
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RESET_MASK                     MK_MASK_CONST(0x1ff00ffc)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_READ_MASK                      MK_MASK_CONST(0x1ff00ffc)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_WRITE_MASK                     MK_MASK_CONST(0x1ff00ffc)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_SHIFT                 MK_SHIFT_CONST(28)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_RANGE                 28:28
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_MSB                   MK_SHIFT_CONST(28)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_LSB                   MK_SHIFT_CONST(28)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_WOFFSET                       0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_UNSET                 MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_ACK_WITHHELD_SET                   MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_SHIFT                        MK_SHIFT_CONST(27)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_RANGE                        27:27
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_MSB                  MK_SHIFT_CONST(27)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_LSB                  MK_SHIFT_CONST(27)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_WOFFSET                      0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_UNSET                        MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RD2WR_SET                  MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_SHIFT                        MK_SHIFT_CONST(26)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_RANGE                        26:26
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_MSB                  MK_SHIFT_CONST(26)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_LSB                  MK_SHIFT_CONST(26)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_WOFFSET                      0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_UNSET                        MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_WR2RD_SET                  MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_SHIFT                 MK_SHIFT_CONST(25)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_RANGE                 25:25
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_MSB                   MK_SHIFT_CONST(25)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_LSB                   MK_SHIFT_CONST(25)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_WOFFSET                       0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_UNSET                 MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PKT_XFER_ERR_SET                   MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_SHIFT                        MK_SHIFT_CONST(24)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_RANGE                        24:24
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_MSB                  MK_SHIFT_CONST(24)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_LSB                  MK_SHIFT_CONST(24)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_WOFFSET                      0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_UNSET                        MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TX_BUFFER_REQ_SET                  MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_SHIFT                     MK_SHIFT_CONST(23)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_RANGE                     23:23
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_MSB                       MK_SHIFT_CONST(23)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_LSB                       MK_SHIFT_CONST(23)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_WOFFSET                   0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_UNSET                     MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RX_BUFFER_FILLED_SET                       MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SHIFT                 MK_SHIFT_CONST(22)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_RANGE                 22:22
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_MSB                   MK_SHIFT_CONST(22)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_LSB                   MK_SHIFT_CONST(22)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_WOFFSET                       0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_UNSET                 MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_PACKET_XFER_COMPLETE_SET                   MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_SHIFT                    MK_SHIFT_CONST(21)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_RANGE                    21:21
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_MSB                      MK_SHIFT_CONST(21)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_LSB                      MK_SHIFT_CONST(21)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_WOFFSET                  0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_UNSET                    MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_TFIFO_OVF_SET                      MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_SHIFT                    MK_SHIFT_CONST(20)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_RANGE                    20:20
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_MSB                      MK_SHIFT_CONST(20)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_LSB                      MK_SHIFT_CONST(20)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_WOFFSET                  0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_UNSET                    MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_SLV_RFIFO_UNF_SET                      MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_SHIFT                   MK_SHIFT_CONST(11)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_RANGE                   11:11
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_MSB                     MK_SHIFT_CONST(11)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_LSB                     MK_SHIFT_CONST(11)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_WOFFSET                 0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_UNSET                   MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_BUS_CLEAR_DONE_SET                     MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_SHIFT                        MK_SHIFT_CONST(10)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_RANGE                        10:10
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_MSB                  MK_SHIFT_CONST(10)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_LSB                  MK_SHIFT_CONST(10)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_WOFFSET                      0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_UNSET                        MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_MEXT_TIMEOUT_SET                  MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_SHIFT                        MK_SHIFT_CONST(9)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_RANGE                        9:9
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_MSB                  MK_SHIFT_CONST(9)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_LSB                  MK_SHIFT_CONST(9)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_WOFFSET                      0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_UNSET                        MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TLOW_SEXT_TIMEOUT_SET                  MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_SHIFT                  MK_SHIFT_CONST(8)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_RANGE                  8:8
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_MSB                    MK_SHIFT_CONST(8)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_LSB                    MK_SHIFT_CONST(8)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_WOFFSET                        0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_UNSET                  MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TIMEOUT_SET                    MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT                     MK_SHIFT_CONST(7)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_RANGE                     7:7
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_MSB                       MK_SHIFT_CONST(7)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_LSB                       MK_SHIFT_CONST(7)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_WOFFSET                   0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_UNSET                     MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_PACKET_XFER_COMPLETE_SET                       MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT                        MK_SHIFT_CONST(6)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_RANGE                        6:6
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_MSB                  MK_SHIFT_CONST(6)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_LSB                  MK_SHIFT_CONST(6)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_WOFFSET                      0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_UNSET                        MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ALL_PACKETS_XFER_COMPLETE_SET                  MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_SHIFT                        MK_SHIFT_CONST(5)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_RANGE                        5:5
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_MSB                  MK_SHIFT_CONST(5)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_LSB                  MK_SHIFT_CONST(5)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_WOFFSET                      0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_UNSET                        MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_TFIFO_OVF_SET                  MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_SHIFT                        MK_SHIFT_CONST(4)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_FIELD                        MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_RANGE                        4:4
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_MSB                  MK_SHIFT_CONST(4)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_LSB                  MK_SHIFT_CONST(4)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_WOFFSET                      0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_UNSET                        MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_RFIFO_UNF_SET                  MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_SHIFT                    MK_SHIFT_CONST(3)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_RANGE                    3:3
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_MSB                      MK_SHIFT_CONST(3)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_LSB                      MK_SHIFT_CONST(3)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_WOFFSET                  0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_UNSET                    MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_NOACK_SET                      MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_SHIFT                 MK_SHIFT_CONST(2)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_SHIFT)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_RANGE                 2:2
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_MSB                   MK_SHIFT_CONST(2)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_LSB                   MK_SHIFT_CONST(2)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_WOFFSET                       0x0
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_UNSET                 MK_ENUM_CONST(0)
+#define I2C_I2C_INTERRUPT_SET_REGISTER_0_ARB_LOST_SET                   MK_ENUM_CONST(1)
+
+// Register I2C_I2C_SLV_TX_PACKET_FIFO_0
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0                    MK_ADDR_CONST(0x78)
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_SECURE                     0x0
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_DUAL                       0x0
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_SCR                        0
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_SCRREG                     0
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_WORD_COUNT                         0x1
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_SHIFT                    MK_SHIFT_CONST(0)
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_FIELD                    MK_FIELD_CONST(0xffffffff, I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_SHIFT)
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_RANGE                    31:0
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_MSB                      MK_SHIFT_CONST(31)
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_LSB                      MK_SHIFT_CONST(0)
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_WOFFSET                  0x0
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_TX_PACKET_FIFO_0_TX_PACKET_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+// Register I2C_I2C_SLV_RX_FIFO_0
+#define I2C_I2C_SLV_RX_FIFO_0                   MK_ADDR_CONST(0x7c)
+#define I2C_I2C_SLV_RX_FIFO_0_SECURE                    0x0
+#define I2C_I2C_SLV_RX_FIFO_0_DUAL                      0x0
+#define I2C_I2C_SLV_RX_FIFO_0_SCR                       0
+#define I2C_I2C_SLV_RX_FIFO_0_SCRREG                    0
+#define I2C_I2C_SLV_RX_FIFO_0_WORD_COUNT                        0x1
+#define I2C_I2C_SLV_RX_FIFO_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_RX_FIFO_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SLV_RX_FIFO_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_RX_FIFO_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_RX_FIFO_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SLV_RX_FIFO_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_SHIFT                     MK_SHIFT_CONST(0)
+#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_FIELD                     MK_FIELD_CONST(0xffffffff, I2C_I2C_SLV_RX_FIFO_0_RD_DATA_SHIFT)
+#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_RANGE                     31:0
+#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_MSB                       MK_SHIFT_CONST(31)
+#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_LSB                       MK_SHIFT_CONST(0)
+#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_WOFFSET                   0x0
+#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_RX_FIFO_0_RD_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+// Register I2C_I2C_SLV_PACKET_STATUS_0
+#define I2C_I2C_SLV_PACKET_STATUS_0                     MK_ADDR_CONST(0x80)
+#define I2C_I2C_SLV_PACKET_STATUS_0_SECURE                      0x0
+#define I2C_I2C_SLV_PACKET_STATUS_0_DUAL                        0x0
+#define I2C_I2C_SLV_PACKET_STATUS_0_SCR                         0
+#define I2C_I2C_SLV_PACKET_STATUS_0_SCRREG                      0
+#define I2C_I2C_SLV_PACKET_STATUS_0_WORD_COUNT                  0x1
+#define I2C_I2C_SLV_PACKET_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x3ffffff)
+#define I2C_I2C_SLV_PACKET_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_READ_MASK                   MK_MASK_CONST(0x3ffffff)
+#define I2C_I2C_SLV_PACKET_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_SHIFT                  MK_SHIFT_CONST(25)
+#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_SHIFT)
+#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_RANGE                  25:25
+#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_MSB                    MK_SHIFT_CONST(25)
+#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_LSB                    MK_SHIFT_CONST(25)
+#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_WOFFSET                        0x0
+#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_ACK_WITHHELD_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_SHIFT                     MK_SHIFT_CONST(24)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_SHIFT)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_RANGE                     24:24
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_MSB                       MK_SHIFT_CONST(24)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_LSB                       MK_SHIFT_CONST(24)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_WOFFSET                   0x0
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_COMPLETE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_SHIFT                       MK_SHIFT_CONST(16)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_FIELD                       MK_FIELD_CONST(0xff, I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_SHIFT)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_RANGE                       23:16
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_MSB                 MK_SHIFT_CONST(23)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_LSB                 MK_SHIFT_CONST(16)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_WOFFSET                     0x0
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_PKT_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_SHIFT                      MK_SHIFT_CONST(0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_FIELD                      MK_FIELD_CONST(0xffff, I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_SHIFT)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_RANGE                      15:0
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_MSB                        MK_SHIFT_CONST(15)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_LSB                        MK_SHIFT_CONST(0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_WOFFSET                    0x0
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_PACKET_STATUS_0_TRANSFER_BYTENUM_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register I2C_I2C_BUS_CLEAR_CONFIG_0
+#define I2C_I2C_BUS_CLEAR_CONFIG_0                      MK_ADDR_CONST(0x84)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_SECURE                       0x0
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_DUAL                         0x0
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_SCR                  0
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_SCRREG                       0
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_WORD_COUNT                   0x1
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_RESET_VAL                    MK_MASK_CONST(0x90004)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_RESET_MASK                   MK_MASK_CONST(0xff0007)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_READ_MASK                    MK_MASK_CONST(0xff0007)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_WRITE_MASK                   MK_MASK_CONST(0xff0007)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_SHIFT                      MK_SHIFT_CONST(16)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_FIELD                      MK_FIELD_CONST(0xff, I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_SHIFT)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_RANGE                      23:16
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_MSB                        MK_SHIFT_CONST(23)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_LSB                        MK_SHIFT_CONST(16)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_WOFFSET                    0x0
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_DEFAULT                    MK_MASK_CONST(0x9)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_DEFAULT_MASK                       MK_MASK_CONST(0xff)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_SCLK_THRESHOLD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_SHIFT                   MK_SHIFT_CONST(2)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_SHIFT)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_RANGE                   2:2
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_MSB                     MK_SHIFT_CONST(2)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_LSB                     MK_SHIFT_CONST(2)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_WOFFSET                 0x0
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_DEFAULT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_NO_STOP                 MK_ENUM_CONST(0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_STOP_COND_STOP                    MK_ENUM_CONST(1)
+
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_SHIFT                   MK_SHIFT_CONST(1)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_SHIFT)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_RANGE                   1:1
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_MSB                     MK_SHIFT_CONST(1)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_LSB                     MK_SHIFT_CONST(1)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_WOFFSET                 0x0
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_THRESHOLD                       MK_ENUM_CONST(0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_TERMINATE_IMMEDIATE                       MK_ENUM_CONST(1)
+
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_SHIFT                      MK_SHIFT_CONST(0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_SHIFT)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_RANGE                      0:0
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_MSB                        MK_SHIFT_CONST(0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_LSB                        MK_SHIFT_CONST(0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_WOFFSET                    0x0
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_CONFIG_0_BC_ENABLE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register I2C_I2C_BUS_CLEAR_STATUS_0
+#define I2C_I2C_BUS_CLEAR_STATUS_0                      MK_ADDR_CONST(0x88)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_SECURE                       0x0
+#define I2C_I2C_BUS_CLEAR_STATUS_0_DUAL                         0x0
+#define I2C_I2C_BUS_CLEAR_STATUS_0_SCR                  0
+#define I2C_I2C_BUS_CLEAR_STATUS_0_SCRREG                       0
+#define I2C_I2C_BUS_CLEAR_STATUS_0_WORD_COUNT                   0x1
+#define I2C_I2C_BUS_CLEAR_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_SHIFT                      MK_SHIFT_CONST(0)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_SHIFT)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_RANGE                      0:0
+#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_MSB                        MK_SHIFT_CONST(0)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_LSB                        MK_SHIFT_CONST(0)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_WOFFSET                    0x0
+#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_NOT_CLEARED                        MK_ENUM_CONST(0)
+#define I2C_I2C_BUS_CLEAR_STATUS_0_BC_STATUS_CLEARED                    MK_ENUM_CONST(1)
+
+// Register I2C_I2C_CONFIG_LOAD_0
+#define I2C_I2C_CONFIG_LOAD_0                   MK_ADDR_CONST(0x8c)
+#define I2C_I2C_CONFIG_LOAD_0_SECURE                    0x0
+#define I2C_I2C_CONFIG_LOAD_0_DUAL                      0x0
+#define I2C_I2C_CONFIG_LOAD_0_SCR                       0
+#define I2C_I2C_CONFIG_LOAD_0_SCRREG                    0
+#define I2C_I2C_CONFIG_LOAD_0_WORD_COUNT                        0x1
+#define I2C_I2C_CONFIG_LOAD_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define I2C_I2C_CONFIG_LOAD_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define I2C_I2C_CONFIG_LOAD_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CONFIG_LOAD_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CONFIG_LOAD_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define I2C_I2C_CONFIG_LOAD_0_WRITE_MASK                        MK_MASK_CONST(0x7)
+#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_SHIFT                 MK_SHIFT_CONST(2)
+#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_SHIFT)
+#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_RANGE                 2:2
+#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_MSB                   MK_SHIFT_CONST(2)
+#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_LSB                   MK_SHIFT_CONST(2)
+#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_WOFFSET                       0x0
+#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_DISABLE                       MK_ENUM_CONST(0)
+#define I2C_I2C_CONFIG_LOAD_0_TIMEOUT_CONFIG_LOAD_ENABLE                        MK_ENUM_CONST(1)
+
+#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_SHIFT                     MK_SHIFT_CONST(1)
+#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_FIELD                     MK_FIELD_CONST(0x1, I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_SHIFT)
+#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_RANGE                     1:1
+#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_MSB                       MK_SHIFT_CONST(1)
+#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_LSB                       MK_SHIFT_CONST(1)
+#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_WOFFSET                   0x0
+#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_DISABLE                   MK_ENUM_CONST(0)
+#define I2C_I2C_CONFIG_LOAD_0_SLV_CONFIG_LOAD_ENABLE                    MK_ENUM_CONST(1)
+
+#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_SHIFT                    MK_SHIFT_CONST(0)
+#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_SHIFT)
+#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_RANGE                    0:0
+#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_MSB                      MK_SHIFT_CONST(0)
+#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_LSB                      MK_SHIFT_CONST(0)
+#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_WOFFSET                  0x0
+#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_DISABLE                  MK_ENUM_CONST(0)
+#define I2C_I2C_CONFIG_LOAD_0_MSTR_CONFIG_LOAD_ENABLE                   MK_ENUM_CONST(1)
+
+// Register I2C_I2C_CLKEN_OVERRIDE_0
+#define I2C_I2C_CLKEN_OVERRIDE_0                        MK_ADDR_CONST(0x90)
+#define I2C_I2C_CLKEN_OVERRIDE_0_SECURE                         0x0
+#define I2C_I2C_CLKEN_OVERRIDE_0_DUAL                   0x0
+#define I2C_I2C_CLKEN_OVERRIDE_0_SCR                    0
+#define I2C_I2C_CLKEN_OVERRIDE_0_SCRREG                         0
+#define I2C_I2C_CLKEN_OVERRIDE_0_WORD_COUNT                     0x1
+#define I2C_I2C_CLKEN_OVERRIDE_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_RESET_MASK                     MK_MASK_CONST(0x1d)
+#define I2C_I2C_CLKEN_OVERRIDE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_READ_MASK                      MK_MASK_CONST(0x1d)
+#define I2C_I2C_CLKEN_OVERRIDE_0_WRITE_MASK                     MK_MASK_CONST(0x1d)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_SHIFT                   MK_SHIFT_CONST(0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_SHIFT)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_RANGE                   0:0
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_MSB                     MK_SHIFT_CONST(0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_LSB                     MK_SHIFT_CONST(0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_WOFFSET                 0x0
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_INIT_ENUM                       CLK_GATED
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_CLK_GATED                       MK_ENUM_CONST(0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_MST_CORE_CLKEN_OVR_CLK_ALWAYS_ON                   MK_ENUM_CONST(1)
+
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_SHIFT                   MK_SHIFT_CONST(2)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_SHIFT)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_RANGE                   2:2
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_MSB                     MK_SHIFT_CONST(2)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_LSB                     MK_SHIFT_CONST(2)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_WOFFSET                 0x0
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_INIT_ENUM                       CLK_GATED
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_CLK_GATED                       MK_ENUM_CONST(0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_CORE_CLKEN_OVR_CLK_ALWAYS_ON                   MK_ENUM_CONST(1)
+
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_SHIFT                    MK_SHIFT_CONST(3)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_FIELD                    MK_FIELD_CONST(0x1, I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_SHIFT)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_RANGE                    3:3
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_MSB                      MK_SHIFT_CONST(3)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_LSB                      MK_SHIFT_CONST(3)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_WOFFSET                  0x0
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_INIT_ENUM                        CLK_GATED
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_CLK_GATED                        MK_ENUM_CONST(0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_SLV_HIF_CLKEN_OVR_CLK_ALWAYS_ON                    MK_ENUM_CONST(1)
+
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_SHIFT                  MK_SHIFT_CONST(4)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_FIELD                  MK_FIELD_CONST(0x1, I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_SHIFT)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_RANGE                  4:4
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_MSB                    MK_SHIFT_CONST(4)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_LSB                    MK_SHIFT_CONST(4)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_WOFFSET                        0x0
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_INIT_ENUM                      CLK_GATED
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_CLK_GATED                      MK_ENUM_CONST(0)
+#define I2C_I2C_CLKEN_OVERRIDE_0_I2C_BUS_CLEAR_CLKEN_OVR_CLK_ALWAYS_ON                  MK_ENUM_CONST(1)
+
+// Register I2C_I2C_INTERFACE_TIMING_0_0
+#define I2C_I2C_INTERFACE_TIMING_0_0                    MK_ADDR_CONST(0x94)
+#define I2C_I2C_INTERFACE_TIMING_0_0_SECURE                     0x0
+#define I2C_I2C_INTERFACE_TIMING_0_0_DUAL                       0x0
+#define I2C_I2C_INTERFACE_TIMING_0_0_SCR                        0
+#define I2C_I2C_INTERFACE_TIMING_0_0_SCRREG                     0
+#define I2C_I2C_INTERFACE_TIMING_0_0_WORD_COUNT                         0x1
+#define I2C_I2C_INTERFACE_TIMING_0_0_RESET_VAL                  MK_MASK_CONST(0x204)
+#define I2C_I2C_INTERFACE_TIMING_0_0_RESET_MASK                         MK_MASK_CONST(0xffff)
+#define I2C_I2C_INTERFACE_TIMING_0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_0_0_READ_MASK                  MK_MASK_CONST(0xffff)
+#define I2C_I2C_INTERFACE_TIMING_0_0_WRITE_MASK                         MK_MASK_CONST(0xffff)
+#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_SHIFT                        MK_SHIFT_CONST(8)
+#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_FIELD                        MK_FIELD_CONST(0xff, I2C_I2C_INTERFACE_TIMING_0_0_THIGH_SHIFT)
+#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_RANGE                        15:8
+#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_MSB                  MK_SHIFT_CONST(15)
+#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_LSB                  MK_SHIFT_CONST(8)
+#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_WOFFSET                      0x0
+#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_DEFAULT                      MK_MASK_CONST(0x2)
+#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH__PROD_C_SM                   MK_ENUM_CONST(7)
+#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH__PROD_C_FM                   MK_ENUM_CONST(1)
+#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH__PROD_C_FMPLUS                       MK_ENUM_CONST(1)
+#define I2C_I2C_INTERFACE_TIMING_0_0_THIGH__PROD_C_HS                   MK_ENUM_CONST(1)
+
+#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_SHIFT                 MK_SHIFT_CONST(0)
+#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_INTERFACE_TIMING_0_0_TLOW_SHIFT)
+#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_RANGE                 7:0
+#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_MSB                   MK_SHIFT_CONST(7)
+#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_LSB                   MK_SHIFT_CONST(0)
+#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_WOFFSET                       0x0
+#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_DEFAULT                       MK_MASK_CONST(0x4)
+#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW__PROD_C_SM                    MK_ENUM_CONST(8)
+#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW__PROD_C_FM                    MK_ENUM_CONST(1)
+#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW__PROD_C_FMPLUS                        MK_ENUM_CONST(1)
+#define I2C_I2C_INTERFACE_TIMING_0_0_TLOW__PROD_C_HS                    MK_ENUM_CONST(1)
+
+// Register I2C_I2C_INTERFACE_TIMING_1_0
+#define I2C_I2C_INTERFACE_TIMING_1_0                    MK_ADDR_CONST(0x98)
+#define I2C_I2C_INTERFACE_TIMING_1_0_SECURE                     0x0
+#define I2C_I2C_INTERFACE_TIMING_1_0_DUAL                       0x0
+#define I2C_I2C_INTERFACE_TIMING_1_0_SCR                        0
+#define I2C_I2C_INTERFACE_TIMING_1_0_SCRREG                     0
+#define I2C_I2C_INTERFACE_TIMING_1_0_WORD_COUNT                         0x1
+#define I2C_I2C_INTERFACE_TIMING_1_0_RESET_VAL                  MK_MASK_CONST(0x4070404)
+#define I2C_I2C_INTERFACE_TIMING_1_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_INTERFACE_TIMING_1_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_1_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_1_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_INTERFACE_TIMING_1_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_SHIFT                 MK_SHIFT_CONST(24)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_FIELD                 MK_FIELD_CONST(0xff, I2C_I2C_INTERFACE_TIMING_1_0_TBUF_SHIFT)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_RANGE                 31:24
+#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_MSB                   MK_SHIFT_CONST(31)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_LSB                   MK_SHIFT_CONST(24)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_WOFFSET                       0x0
+#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_DEFAULT                       MK_MASK_CONST(0x4)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF__PROD_C_SM                    MK_ENUM_CONST(8)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF__PROD_C_FM                    MK_ENUM_CONST(2)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF__PROD_C_FMPLUS                        MK_ENUM_CONST(2)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TBUF__PROD_C_HS                    MK_ENUM_CONST(2)
+
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_SHIFT                      MK_SHIFT_CONST(16)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_FIELD                      MK_FIELD_CONST(0xff, I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_SHIFT)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_RANGE                      23:16
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_MSB                        MK_SHIFT_CONST(23)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_LSB                        MK_SHIFT_CONST(16)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_WOFFSET                    0x0
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_DEFAULT                    MK_MASK_CONST(0x7)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_DEFAULT_MASK                       MK_MASK_CONST(0xff)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO__PROD_C_SM                 MK_ENUM_CONST(8)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO__PROD_C_FM                 MK_ENUM_CONST(2)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO__PROD_C_FMPLUS                     MK_ENUM_CONST(2)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STO__PROD_C_HS                 MK_ENUM_CONST(2)
+
+#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_SHIFT                      MK_SHIFT_CONST(8)
+#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_FIELD                      MK_FIELD_CONST(0xff, I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_SHIFT)
+#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_RANGE                      15:8
+#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_MSB                        MK_SHIFT_CONST(15)
+#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_LSB                        MK_SHIFT_CONST(8)
+#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_WOFFSET                    0x0
+#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_DEFAULT                    MK_MASK_CONST(0x4)
+#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_DEFAULT_MASK                       MK_MASK_CONST(0xff)
+#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA__PROD_C_SM                 MK_ENUM_CONST(8)
+#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA__PROD_C_FM                 MK_ENUM_CONST(2)
+#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA__PROD_C_FMPLUS                     MK_ENUM_CONST(2)
+#define I2C_I2C_INTERFACE_TIMING_1_0_THD_STA__PROD_C_HS                 MK_ENUM_CONST(2)
+
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_SHIFT                      MK_SHIFT_CONST(0)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_FIELD                      MK_FIELD_CONST(0xff, I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_SHIFT)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_RANGE                      7:0
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_MSB                        MK_SHIFT_CONST(7)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_LSB                        MK_SHIFT_CONST(0)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_WOFFSET                    0x0
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_DEFAULT                    MK_MASK_CONST(0x4)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_DEFAULT_MASK                       MK_MASK_CONST(0xff)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA__PROD_C_SM                 MK_ENUM_CONST(8)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA__PROD_C_FM                 MK_ENUM_CONST(2)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA__PROD_C_FMPLUS                     MK_ENUM_CONST(2)
+#define I2C_I2C_INTERFACE_TIMING_1_0_TSU_STA__PROD_C_HS                 MK_ENUM_CONST(2)
+
+// Register I2C_I2C_HS_INTERFACE_TIMING_0_0
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0                 MK_ADDR_CONST(0x9c)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_SECURE                  0x0
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_DUAL                    0x0
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_SCR                     0
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_SCRREG                  0
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_WORD_COUNT                      0x1
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_RESET_VAL                       MK_MASK_CONST(0x308)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_SHIFT                  MK_SHIFT_CONST(8)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_FIELD                  MK_FIELD_CONST(0xff, I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_SHIFT)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_RANGE                  15:8
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_MSB                    MK_SHIFT_CONST(15)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_LSB                    MK_SHIFT_CONST(8)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_WOFFSET                        0x0
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_DEFAULT                        MK_MASK_CONST(0x3)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_THIGH__PROD                  MK_ENUM_CONST(3)
+
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_SHIFT                   MK_SHIFT_CONST(0)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_FIELD                   MK_FIELD_CONST(0xff, I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_SHIFT)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_RANGE                   7:0
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_MSB                     MK_SHIFT_CONST(7)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_LSB                     MK_SHIFT_CONST(0)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_WOFFSET                 0x0
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_DEFAULT                 MK_MASK_CONST(0x8)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define I2C_I2C_HS_INTERFACE_TIMING_0_0_HS_TLOW__PROD                   MK_ENUM_CONST(8)
+
+// Register I2C_I2C_HS_INTERFACE_TIMING_1_0
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0                 MK_ADDR_CONST(0xa0)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_SECURE                  0x0
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_DUAL                    0x0
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_SCR                     0
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_SCRREG                  0
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_WORD_COUNT                      0x1
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_RESET_VAL                       MK_MASK_CONST(0xb0b0b)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_READ_MASK                       MK_MASK_CONST(0xffffff)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_SHIFT                        MK_SHIFT_CONST(16)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_FIELD                        MK_FIELD_CONST(0xff, I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_SHIFT)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_RANGE                        23:16
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_MSB                  MK_SHIFT_CONST(23)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_LSB                  MK_SHIFT_CONST(16)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_WOFFSET                      0x0
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_DEFAULT                      MK_MASK_CONST(0xb)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STO__PROD_C_HS                   MK_ENUM_CONST(9)
+
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_SHIFT                        MK_SHIFT_CONST(8)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_FIELD                        MK_FIELD_CONST(0xff, I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_SHIFT)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_RANGE                        15:8
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_MSB                  MK_SHIFT_CONST(15)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_LSB                  MK_SHIFT_CONST(8)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_WOFFSET                      0x0
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_DEFAULT                      MK_MASK_CONST(0xb)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_THD_STA__PROD_C_HS                   MK_ENUM_CONST(9)
+
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_SHIFT                        MK_SHIFT_CONST(0)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_FIELD                        MK_FIELD_CONST(0xff, I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_SHIFT)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_RANGE                        7:0
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_MSB                  MK_SHIFT_CONST(7)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_LSB                  MK_SHIFT_CONST(0)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_WOFFSET                      0x0
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_DEFAULT                      MK_MASK_CONST(0xb)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_HS_INTERFACE_TIMING_1_0_HS_TSU_STA__PROD_C_HS                   MK_ENUM_CONST(9)
+
+// Register I2C_I2C_MASTER_RESET_CNTRL_0
+#define I2C_I2C_MASTER_RESET_CNTRL_0                    MK_ADDR_CONST(0xa8)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SECURE                     0x0
+#define I2C_I2C_MASTER_RESET_CNTRL_0_DUAL                       0x0
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SCR                        0
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SCRREG                     0
+#define I2C_I2C_MASTER_RESET_CNTRL_0_WORD_COUNT                         0x1
+#define I2C_I2C_MASTER_RESET_CNTRL_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_SHIFT                   MK_SHIFT_CONST(0)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_FIELD                   MK_FIELD_CONST(0x1, I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_SHIFT)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_RANGE                   0:0
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_MSB                     MK_SHIFT_CONST(0)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_LSB                     MK_SHIFT_CONST(0)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_WOFFSET                 0x0
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_CLEARED                 MK_ENUM_CONST(0)
+#define I2C_I2C_MASTER_RESET_CNTRL_0_SOFT_RESET_ASSERTED                        MK_ENUM_CONST(1)
+
+// Register I2C_I2C_SLV_RESET_CNTRL_0
+#define I2C_I2C_SLV_RESET_CNTRL_0                       MK_ADDR_CONST(0xac)
+#define I2C_I2C_SLV_RESET_CNTRL_0_SECURE                        0x0
+#define I2C_I2C_SLV_RESET_CNTRL_0_DUAL                  0x0
+#define I2C_I2C_SLV_RESET_CNTRL_0_SCR                   0
+#define I2C_I2C_SLV_RESET_CNTRL_0_SCRREG                        0
+#define I2C_I2C_SLV_RESET_CNTRL_0_WORD_COUNT                    0x1
+#define I2C_I2C_SLV_RESET_CNTRL_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_RESET_CNTRL_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_SLV_RESET_CNTRL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_RESET_CNTRL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_RESET_CNTRL_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_SLV_RESET_CNTRL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_SHIFT                      MK_SHIFT_CONST(0)
+#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_SHIFT)
+#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_RANGE                      0:0
+#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_MSB                        MK_SHIFT_CONST(0)
+#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_LSB                        MK_SHIFT_CONST(0)
+#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_WOFFSET                    0x0
+#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_CLEARED                    MK_ENUM_CONST(0)
+#define I2C_I2C_SLV_RESET_CNTRL_0_SOFT_RESET_ASSERTED                   MK_ENUM_CONST(1)
+
+// Register I2C_MST_PACKET_TRANSFER_CNT_STATUS_0
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0                    MK_ADDR_CONST(0xb0)
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_SECURE                     0x0
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_DUAL                       0x0
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_SCR                        0
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_SCRREG                     0
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_WORD_COUNT                         0x1
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_RESET_MASK                         MK_MASK_CONST(0xffff)
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_READ_MASK                  MK_MASK_CONST(0xffff)
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_SHIFT                     MK_SHIFT_CONST(0)
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_FIELD                     MK_FIELD_CONST(0xffff, I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_SHIFT)
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_RANGE                     15:0
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_MSB                       MK_SHIFT_CONST(15)
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_LSB                       MK_SHIFT_CONST(0)
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_WOFFSET                   0x0
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_MST_PACKET_TRANSFER_CNT_STATUS_0_TRANSFER_BYTENUM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+// Register I2C_MST_FIFO_CONTROL_0
+#define I2C_MST_FIFO_CONTROL_0                  MK_ADDR_CONST(0xb4)
+#define I2C_MST_FIFO_CONTROL_0_SECURE                   0x0
+#define I2C_MST_FIFO_CONTROL_0_DUAL                     0x0
+#define I2C_MST_FIFO_CONTROL_0_SCR                      0
+#define I2C_MST_FIFO_CONTROL_0_SCRREG                   0
+#define I2C_MST_FIFO_CONTROL_0_WORD_COUNT                       0x1
+#define I2C_MST_FIFO_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x7f07f3)
+#define I2C_MST_FIFO_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x7f07f3)
+#define I2C_MST_FIFO_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x7f07f3)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_SHIFT                       MK_SHIFT_CONST(16)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_FIELD                       MK_FIELD_CONST(0x7f, I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_SHIFT)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_RANGE                       22:16
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_MSB                 MK_SHIFT_CONST(22)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_LSB                 MK_SHIFT_CONST(16)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_WOFFSET                     0x0
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_TRIG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_SHIFT                       MK_SHIFT_CONST(4)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_FIELD                       MK_FIELD_CONST(0x7f, I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_SHIFT)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_RANGE                       10:4
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_MSB                 MK_SHIFT_CONST(10)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_LSB                 MK_SHIFT_CONST(4)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_WOFFSET                     0x0
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_TRIG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_SHIFT                      MK_SHIFT_CONST(1)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_FIELD                      MK_FIELD_CONST(0x1, I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_SHIFT)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_RANGE                      1:1
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_MSB                        MK_SHIFT_CONST(1)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_LSB                        MK_SHIFT_CONST(1)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_WOFFSET                    0x0
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_UNSET                      MK_ENUM_CONST(0)
+#define I2C_MST_FIFO_CONTROL_0_TX_FIFO_FLUSH_SET                        MK_ENUM_CONST(1)
+
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_SHIFT                      MK_SHIFT_CONST(0)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_FIELD                      MK_FIELD_CONST(0x1, I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_SHIFT)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_RANGE                      0:0
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_MSB                        MK_SHIFT_CONST(0)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_LSB                        MK_SHIFT_CONST(0)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_WOFFSET                    0x0
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_UNSET                      MK_ENUM_CONST(0)
+#define I2C_MST_FIFO_CONTROL_0_RX_FIFO_FLUSH_SET                        MK_ENUM_CONST(1)
+
+// Register I2C_MST_FIFO_STATUS_0
+#define I2C_MST_FIFO_STATUS_0                   MK_ADDR_CONST(0xb8)
+#define I2C_MST_FIFO_STATUS_0_SECURE                    0x0
+#define I2C_MST_FIFO_STATUS_0_DUAL                      0x0
+#define I2C_MST_FIFO_STATUS_0_SCR                       0
+#define I2C_MST_FIFO_STATUS_0_SCRREG                    0
+#define I2C_MST_FIFO_STATUS_0_WORD_COUNT                        0x1
+#define I2C_MST_FIFO_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x800000)
+#define I2C_MST_FIFO_STATUS_0_RESET_MASK                        MK_MASK_CONST(0xff00ff)
+#define I2C_MST_FIFO_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_STATUS_0_READ_MASK                         MK_MASK_CONST(0xff00ff)
+#define I2C_MST_FIFO_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT                   MK_SHIFT_CONST(16)
+#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_FIELD                   MK_FIELD_CONST(0xff, I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT)
+#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_RANGE                   23:16
+#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_MSB                     MK_SHIFT_CONST(23)
+#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_LSB                     MK_SHIFT_CONST(16)
+#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_WOFFSET                 0x0
+#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT                 MK_MASK_CONST(0x80)
+#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SHIFT                    MK_SHIFT_CONST(0)
+#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_FIELD                    MK_FIELD_CONST(0xff, I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SHIFT)
+#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_RANGE                    7:0
+#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_MSB                      MK_SHIFT_CONST(7)
+#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_LSB                      MK_SHIFT_CONST(0)
+#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_WOFFSET                  0x0
+#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT_MASK                     MK_MASK_CONST(0xff)
+#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_MST_FIFO_STATUS_0_RX_FIFO_FULL_CNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+// Register I2C_SLV_PAYLOAD_0
+#define I2C_SLV_PAYLOAD_0                       MK_ADDR_CONST(0xbc)
+#define I2C_SLV_PAYLOAD_0_SECURE                        0x0
+#define I2C_SLV_PAYLOAD_0_DUAL                  0x0
+#define I2C_SLV_PAYLOAD_0_SCR                   0
+#define I2C_SLV_PAYLOAD_0_SCRREG                        0
+#define I2C_SLV_PAYLOAD_0_WORD_COUNT                    0x1
+#define I2C_SLV_PAYLOAD_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define I2C_SLV_PAYLOAD_0_RESET_MASK                    MK_MASK_CONST(0xffff)
+#define I2C_SLV_PAYLOAD_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define I2C_SLV_PAYLOAD_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_SLV_PAYLOAD_0_READ_MASK                     MK_MASK_CONST(0xffff)
+#define I2C_SLV_PAYLOAD_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
+#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_SHIFT                     MK_SHIFT_CONST(0)
+#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_FIELD                     MK_FIELD_CONST(0xffff, I2C_SLV_PAYLOAD_0_BUFFER_SIZE_SHIFT)
+#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_RANGE                     15:0
+#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_MSB                       MK_SHIFT_CONST(15)
+#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_LSB                       MK_SHIFT_CONST(0)
+#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_WOFFSET                   0x0
+#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define I2C_SLV_PAYLOAD_0_BUFFER_SIZE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+// Register I2C_SLV_FIFO_CONTROL_0
+#define I2C_SLV_FIFO_CONTROL_0                  MK_ADDR_CONST(0xc0)
+#define I2C_SLV_FIFO_CONTROL_0_SECURE                   0x0
+#define I2C_SLV_FIFO_CONTROL_0_DUAL                     0x0
+#define I2C_SLV_FIFO_CONTROL_0_SCR                      0
+#define I2C_SLV_FIFO_CONTROL_0_SCRREG                   0
+#define I2C_SLV_FIFO_CONTROL_0_WORD_COUNT                       0x1
+#define I2C_SLV_FIFO_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x7f07f3)
+#define I2C_SLV_FIFO_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x7f07f3)
+#define I2C_SLV_FIFO_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x7f07f3)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_SHIFT                       MK_SHIFT_CONST(16)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_FIELD                       MK_FIELD_CONST(0x7f, I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_SHIFT)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_RANGE                       22:16
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_MSB                 MK_SHIFT_CONST(22)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_LSB                 MK_SHIFT_CONST(16)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_WOFFSET                     0x0
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_TRIG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_SHIFT                       MK_SHIFT_CONST(4)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_FIELD                       MK_FIELD_CONST(0x7f, I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_SHIFT)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_RANGE                       10:4
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_MSB                 MK_SHIFT_CONST(10)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_LSB                 MK_SHIFT_CONST(4)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_WOFFSET                     0x0
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_DEFAULT_MASK                        MK_MASK_CONST(0x7f)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_TRIG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_SHIFT                      MK_SHIFT_CONST(1)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_FIELD                      MK_FIELD_CONST(0x1, I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_SHIFT)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_RANGE                      1:1
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_MSB                        MK_SHIFT_CONST(1)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_LSB                        MK_SHIFT_CONST(1)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_WOFFSET                    0x0
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_UNSET                      MK_ENUM_CONST(0)
+#define I2C_SLV_FIFO_CONTROL_0_TX_FIFO_FLUSH_SET                        MK_ENUM_CONST(1)
+
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_SHIFT                      MK_SHIFT_CONST(0)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_FIELD                      MK_FIELD_CONST(0x1, I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_SHIFT)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_RANGE                      0:0
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_MSB                        MK_SHIFT_CONST(0)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_LSB                        MK_SHIFT_CONST(0)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_WOFFSET                    0x0
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_UNSET                      MK_ENUM_CONST(0)
+#define I2C_SLV_FIFO_CONTROL_0_RX_FIFO_FLUSH_SET                        MK_ENUM_CONST(1)
+
+// Register I2C_SLV_FIFO_STATUS_0
+#define I2C_SLV_FIFO_STATUS_0                   MK_ADDR_CONST(0xc4)
+#define I2C_SLV_FIFO_STATUS_0_SECURE                    0x0
+#define I2C_SLV_FIFO_STATUS_0_DUAL                      0x0
+#define I2C_SLV_FIFO_STATUS_0_SCR                       0
+#define I2C_SLV_FIFO_STATUS_0_SCRREG                    0
+#define I2C_SLV_FIFO_STATUS_0_WORD_COUNT                        0x1
+#define I2C_SLV_FIFO_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x800000)
+#define I2C_SLV_FIFO_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x1ff00ff)
+#define I2C_SLV_FIFO_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_STATUS_0_READ_MASK                         MK_MASK_CONST(0x1ff00ff)
+#define I2C_SLV_FIFO_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_SHIFT                 MK_SHIFT_CONST(24)
+#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_FIELD                 MK_FIELD_CONST(0x1, I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_SHIFT)
+#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_RANGE                 24:24
+#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_MSB                   MK_SHIFT_CONST(24)
+#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_LSB                   MK_SHIFT_CONST(24)
+#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_WOFFSET                       0x0
+#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_STATUS_0_SLV_XFER_ERR_REASON_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT                   MK_SHIFT_CONST(16)
+#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_FIELD                   MK_FIELD_CONST(0xff, I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SHIFT)
+#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_RANGE                   23:16
+#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_MSB                     MK_SHIFT_CONST(23)
+#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_LSB                     MK_SHIFT_CONST(16)
+#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_WOFFSET                 0x0
+#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT                 MK_MASK_CONST(0x80)
+#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_STATUS_0_TX_FIFO_EMPTY_CNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SHIFT                    MK_SHIFT_CONST(0)
+#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_FIELD                    MK_FIELD_CONST(0xff, I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SHIFT)
+#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_RANGE                    7:0
+#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_MSB                      MK_SHIFT_CONST(7)
+#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_LSB                      MK_SHIFT_CONST(0)
+#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_WOFFSET                  0x0
+#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_DEFAULT_MASK                     MK_MASK_CONST(0xff)
+#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_SLV_FIFO_STATUS_0_RX_FIFO_FULL_CNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+// Register I2C_I2C_MST_NM_INT_STATUS_0
+#define I2C_I2C_MST_NM_INT_STATUS_0                     MK_ADDR_CONST(0xc8)
+#define I2C_I2C_MST_NM_INT_STATUS_0_SECURE                      0x0
+#define I2C_I2C_MST_NM_INT_STATUS_0_DUAL                        0x0
+#define I2C_I2C_MST_NM_INT_STATUS_0_SCR                         0
+#define I2C_I2C_MST_NM_INT_STATUS_0_SCRREG                      0
+#define I2C_I2C_MST_NM_INT_STATUS_0_WORD_COUNT                  0x1
+#define I2C_I2C_MST_NM_INT_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define I2C_I2C_MST_NM_INT_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define I2C_I2C_MST_NM_INT_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define I2C_I2C_MST_NM_INT_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_MST_NM_INT_STATUS_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define I2C_I2C_MST_NM_INT_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_SHIFT                      MK_SHIFT_CONST(0)
+#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_FIELD                      MK_FIELD_CONST(0x1, I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_SHIFT)
+#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_RANGE                      0:0
+#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_MSB                        MK_SHIFT_CONST(0)
+#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_LSB                        MK_SHIFT_CONST(0)
+#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_WOFFSET                    0x0
+#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_UNSET                      MK_ENUM_CONST(0)
+#define I2C_I2C_MST_NM_INT_STATUS_0_TXN_DONE_SET                        MK_ENUM_CONST(1)
+
+// Register I2C_I2C_MST_NM_INT_MASK_0
+#define I2C_I2C_MST_NM_INT_MASK_0                       MK_ADDR_CONST(0xcc)
+#define I2C_I2C_MST_NM_INT_MASK_0_SECURE                        0x0
+#define I2C_I2C_MST_NM_INT_MASK_0_DUAL                  0x0
+#define I2C_I2C_MST_NM_INT_MASK_0_SCR                   0
+#define I2C_I2C_MST_NM_INT_MASK_0_SCRREG                        0
+#define I2C_I2C_MST_NM_INT_MASK_0_WORD_COUNT                    0x1
+#define I2C_I2C_MST_NM_INT_MASK_0_RESET_VAL                     MK_MASK_CONST(0x1)
+#define I2C_I2C_MST_NM_INT_MASK_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_MST_NM_INT_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define I2C_I2C_MST_NM_INT_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_MST_NM_INT_MASK_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define I2C_I2C_MST_NM_INT_MASK_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_SHIFT                 MK_SHIFT_CONST(0)
+#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_FIELD                 MK_FIELD_CONST(0x1, I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_SHIFT)
+#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_RANGE                 0:0
+#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_MSB                   MK_SHIFT_CONST(0)
+#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_LSB                   MK_SHIFT_CONST(0)
+#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_WOFFSET                       0x0
+#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_DEFAULT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_DISABLE                       MK_ENUM_CONST(0)
+#define I2C_I2C_MST_NM_INT_MASK_0_TXN_DONE_INT_EN_ENABLE                        MK_ENUM_CONST(1)
+
+// Register I2C_BUS_STATUS_0
+#define I2C_BUS_STATUS_0                        MK_ADDR_CONST(0xd0)
+#define I2C_BUS_STATUS_0_SECURE                         0x0
+#define I2C_BUS_STATUS_0_DUAL                   0x0
+#define I2C_BUS_STATUS_0_SCR                    0
+#define I2C_BUS_STATUS_0_SCRREG                         0
+#define I2C_BUS_STATUS_0_WORD_COUNT                     0x1
+#define I2C_BUS_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
+#define I2C_BUS_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_SCL_SHIFT                      MK_SHIFT_CONST(2)
+#define I2C_BUS_STATUS_0_SCL_FIELD                      MK_FIELD_CONST(0x1, I2C_BUS_STATUS_0_SCL_SHIFT)
+#define I2C_BUS_STATUS_0_SCL_RANGE                      2:2
+#define I2C_BUS_STATUS_0_SCL_MSB                        MK_SHIFT_CONST(2)
+#define I2C_BUS_STATUS_0_SCL_LSB                        MK_SHIFT_CONST(2)
+#define I2C_BUS_STATUS_0_SCL_WOFFSET                    0x0
+#define I2C_BUS_STATUS_0_SCL_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_SCL_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_SCL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_SCL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_SCL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_SCL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define I2C_BUS_STATUS_0_SDA_SHIFT                      MK_SHIFT_CONST(1)
+#define I2C_BUS_STATUS_0_SDA_FIELD                      MK_FIELD_CONST(0x1, I2C_BUS_STATUS_0_SDA_SHIFT)
+#define I2C_BUS_STATUS_0_SDA_RANGE                      1:1
+#define I2C_BUS_STATUS_0_SDA_MSB                        MK_SHIFT_CONST(1)
+#define I2C_BUS_STATUS_0_SDA_LSB                        MK_SHIFT_CONST(1)
+#define I2C_BUS_STATUS_0_SDA_WOFFSET                    0x0
+#define I2C_BUS_STATUS_0_SDA_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_SDA_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_SDA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_SDA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_SDA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_SDA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define I2C_BUS_STATUS_0_BUS_BUSY_SHIFT                 MK_SHIFT_CONST(0)
+#define I2C_BUS_STATUS_0_BUS_BUSY_FIELD                 MK_FIELD_CONST(0x1, I2C_BUS_STATUS_0_BUS_BUSY_SHIFT)
+#define I2C_BUS_STATUS_0_BUS_BUSY_RANGE                 0:0
+#define I2C_BUS_STATUS_0_BUS_BUSY_MSB                   MK_SHIFT_CONST(0)
+#define I2C_BUS_STATUS_0_BUS_BUSY_LSB                   MK_SHIFT_CONST(0)
+#define I2C_BUS_STATUS_0_BUS_BUSY_WOFFSET                       0x0
+#define I2C_BUS_STATUS_0_BUS_BUSY_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_BUS_BUSY_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_BUS_BUSY_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_BUS_BUSY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_BUS_BUSY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define I2C_BUS_STATUS_0_BUS_BUSY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define I2C_BUS_STATUS_0_BUS_BUSY_FREE                  MK_ENUM_CONST(0)
+#define I2C_BUS_STATUS_0_BUS_BUSY_BUSY                  MK_ENUM_CONST(1)
+
+// Register I2C_I2C_INTERFACE_TIMING_2_0
+#define I2C_I2C_INTERFACE_TIMING_2_0                    MK_ADDR_CONST(0xd4)
+#define I2C_I2C_INTERFACE_TIMING_2_0_SECURE                     0x0
+#define I2C_I2C_INTERFACE_TIMING_2_0_DUAL                       0x0
+#define I2C_I2C_INTERFACE_TIMING_2_0_SCR                        0
+#define I2C_I2C_INTERFACE_TIMING_2_0_SCRREG                     0
+#define I2C_I2C_INTERFACE_TIMING_2_0_WORD_COUNT                         0x1
+#define I2C_I2C_INTERFACE_TIMING_2_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_2_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define I2C_I2C_INTERFACE_TIMING_2_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_2_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_2_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define I2C_I2C_INTERFACE_TIMING_2_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_SHIFT                      MK_SHIFT_CONST(0)
+#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_FIELD                      MK_FIELD_CONST(0xff, I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_SHIFT)
+#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_RANGE                      7:0
+#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_MSB                        MK_SHIFT_CONST(7)
+#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_LSB                        MK_SHIFT_CONST(0)
+#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_WOFFSET                    0x0
+#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_DEFAULT                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_DEFAULT_MASK                       MK_MASK_CONST(0xff)
+#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_INTERFACE_TIMING_2_0_THD_DAT__PROD                      MK_ENUM_CONST(0)
+
+// Register I2C_I2C_HS_INTERFACE_TIMING_2_0
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0                 MK_ADDR_CONST(0xd8)
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_SECURE                  0x0
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_DUAL                    0x0
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_SCR                     0
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_SCRREG                  0
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_WORD_COUNT                      0x1
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_RESET_MASK                      MK_MASK_CONST(0xff)
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_READ_MASK                       MK_MASK_CONST(0xff)
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_WRITE_MASK                      MK_MASK_CONST(0xff)
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_SHIFT                        MK_SHIFT_CONST(0)
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_FIELD                        MK_FIELD_CONST(0xff, I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_SHIFT)
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_RANGE                        7:0
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_MSB                  MK_SHIFT_CONST(7)
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_LSB                  MK_SHIFT_CONST(0)
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_WOFFSET                      0x0
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define I2C_I2C_HS_INTERFACE_TIMING_2_0_HS_THD_DAT__PROD                        MK_ENUM_CONST(0)
+
+// Register I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0                      MK_ADDR_CONST(0xdc)
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_SECURE                       0x0
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_DUAL                         0x0
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_SCR                  0
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_SCRREG                       0
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_WORD_COUNT                   0x1
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_RESET_MASK                   MK_MASK_CONST(0xffff)
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_READ_MASK                    MK_MASK_CONST(0xffff)
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_WRITE_MASK                   MK_MASK_CONST(0xffff)
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_SHIFT                   MK_SHIFT_CONST(0)
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_FIELD                   MK_FIELD_CONST(0xffff, I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_SHIFT)
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_RANGE                   15:0
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_MSB                     MK_SHIFT_CONST(15)
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_LSB                     MK_SHIFT_CONST(0)
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_WOFFSET                 0x0
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_DEFAULT                 MK_MASK_CONST(0x1)
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT__PROD                   MK_ENUM_CONST(1)
+
+// Register I2C_I2C_SLV_DATA_CAPTURE_TIMING_0
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0                       MK_ADDR_CONST(0xe0)
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_SECURE                        0x0
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_DUAL                  0x0
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_SCR                   0
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_SCRREG                        0
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_WORD_COUNT                    0x1
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_RESET_VAL                     MK_MASK_CONST(0x2)
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_RESET_MASK                    MK_MASK_CONST(0xffff)
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_READ_MASK                     MK_MASK_CONST(0xffff)
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_WRITE_MASK                    MK_MASK_CONST(0xffff)
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_SHIFT                    MK_SHIFT_CONST(0)
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_FIELD                    MK_FIELD_CONST(0xffff, I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_SHIFT)
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_RANGE                    15:0
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_MSB                      MK_SHIFT_CONST(15)
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_LSB                      MK_SHIFT_CONST(0)
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_WOFFSET                  0x0
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_DEFAULT                  MK_MASK_CONST(0x2)
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define I2C_I2C_SLV_DATA_CAPTURE_TIMING_0_TCAPTURE_DAT__PROD                    MK_ENUM_CONST(2)
+
+// Register I2C_I2C_SPARE_0
+#define I2C_I2C_SPARE_0                 MK_ADDR_CONST(0xe4)
+#define I2C_I2C_SPARE_0_SECURE                  0x0
+#define I2C_I2C_SPARE_0_DUAL                    0x0
+#define I2C_I2C_SPARE_0_SCR                     0
+#define I2C_I2C_SPARE_0_SCRREG                  0
+#define I2C_I2C_SPARE_0_WORD_COUNT                      0x1
+#define I2C_I2C_SPARE_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define I2C_I2C_SPARE_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SPARE_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SPARE_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define I2C_I2C_SPARE_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SPARE_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SPARE_0_ECO_SHIFT                       MK_SHIFT_CONST(0)
+#define I2C_I2C_SPARE_0_ECO_FIELD                       MK_FIELD_CONST(0xffffffff, I2C_I2C_SPARE_0_ECO_SHIFT)
+#define I2C_I2C_SPARE_0_ECO_RANGE                       31:0
+#define I2C_I2C_SPARE_0_ECO_MSB                 MK_SHIFT_CONST(31)
+#define I2C_I2C_SPARE_0_ECO_LSB                 MK_SHIFT_CONST(0)
+#define I2C_I2C_SPARE_0_ECO_WOFFSET                     0x0
+#define I2C_I2C_SPARE_0_ECO_DEFAULT                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SPARE_0_ECO_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define I2C_I2C_SPARE_0_ECO_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define I2C_I2C_SPARE_0_ECO_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define I2C_I2C_SPARE_0_ECO_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define I2C_I2C_SPARE_0_ECO_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+//
+// REGISTER LIST
+//
+#define LIST_ARI2C_REGS(_op_) \
+_op_(I2C_I2C_CNFG_0) \
+_op_(I2C_I2C_CMD_ADDR0_0) \
+_op_(I2C_I2C_CMD_ADDR1_0) \
+_op_(I2C_I2C_CMD_DATA1_0) \
+_op_(I2C_I2C_CMD_DATA2_0) \
+_op_(I2C_I2C_STATUS_0) \
+_op_(I2C_I2C_SL_CNFG_0) \
+_op_(I2C_I2C_SL_RCVD_0) \
+_op_(I2C_I2C_SL_STATUS_0) \
+_op_(I2C_I2C_SL_ADDR1_0) \
+_op_(I2C_I2C_SL_ADDR2_0) \
+_op_(I2C_I2C_TLOW_SEXT_0) \
+_op_(I2C_I2C_SL_DELAY_COUNT_0) \
+_op_(I2C_I2C_SL_INT_MASK_0) \
+_op_(I2C_I2C_SL_INT_SOURCE_0) \
+_op_(I2C_I2C_SL_INT_SET_0) \
+_op_(I2C_I2C_TX_PACKET_FIFO_0) \
+_op_(I2C_I2C_RX_FIFO_0) \
+_op_(I2C_PACKET_TRANSFER_STATUS_0) \
+_op_(I2C_INTERRUPT_MASK_REGISTER_0) \
+_op_(I2C_INTERRUPT_STATUS_REGISTER_0) \
+_op_(I2C_I2C_CLK_DIVISOR_REGISTER_0) \
+_op_(I2C_I2C_INTERRUPT_SOURCE_REGISTER_0) \
+_op_(I2C_I2C_INTERRUPT_SET_REGISTER_0) \
+_op_(I2C_I2C_SLV_TX_PACKET_FIFO_0) \
+_op_(I2C_I2C_SLV_RX_FIFO_0) \
+_op_(I2C_I2C_SLV_PACKET_STATUS_0) \
+_op_(I2C_I2C_BUS_CLEAR_CONFIG_0) \
+_op_(I2C_I2C_BUS_CLEAR_STATUS_0) \
+_op_(I2C_I2C_CONFIG_LOAD_0) \
+_op_(I2C_I2C_CLKEN_OVERRIDE_0) \
+_op_(I2C_I2C_INTERFACE_TIMING_0_0) \
+_op_(I2C_I2C_INTERFACE_TIMING_1_0) \
+_op_(I2C_I2C_HS_INTERFACE_TIMING_0_0) \
+_op_(I2C_I2C_HS_INTERFACE_TIMING_1_0) \
+_op_(I2C_I2C_MASTER_RESET_CNTRL_0) \
+_op_(I2C_I2C_SLV_RESET_CNTRL_0) \
+_op_(I2C_MST_PACKET_TRANSFER_CNT_STATUS_0) \
+_op_(I2C_MST_FIFO_CONTROL_0) \
+_op_(I2C_MST_FIFO_STATUS_0) \
+_op_(I2C_SLV_PAYLOAD_0) \
+_op_(I2C_SLV_FIFO_CONTROL_0) \
+_op_(I2C_SLV_FIFO_STATUS_0) \
+_op_(I2C_I2C_MST_NM_INT_STATUS_0) \
+_op_(I2C_I2C_MST_NM_INT_MASK_0) \
+_op_(I2C_BUS_STATUS_0) \
+_op_(I2C_I2C_INTERFACE_TIMING_2_0) \
+_op_(I2C_I2C_HS_INTERFACE_TIMING_2_0) \
+_op_(I2C_I2C_MSTR_DATA_CAPTURE_TIMING_0) \
+_op_(I2C_I2C_SLV_DATA_CAPTURE_TIMING_0) \
+_op_(I2C_I2C_SPARE_0)
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_I2C        0x00000000
+
+//
+// ARI2C REGISTER BANKS
+//
+
+#define I2C0_FIRST_REG 0x0000 // I2C_I2C_CNFG_0
+#define I2C0_LAST_REG 0x0010 // I2C_I2C_CMD_DATA2_0
+#define I2C1_FIRST_REG 0x001c // I2C_I2C_STATUS_0
+#define I2C1_LAST_REG 0x0034 // I2C_I2C_TLOW_SEXT_0
+#define I2C2_FIRST_REG 0x003c // I2C_I2C_SL_DELAY_COUNT_0
+#define I2C2_LAST_REG 0x0048 // I2C_I2C_SL_INT_SET_0
+#define I2C3_FIRST_REG 0x0050 // I2C_I2C_TX_PACKET_FIFO_0
+#define I2C3_LAST_REG 0x00e4 // I2C_I2C_SPARE_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARI2C_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arintr_ctlr.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arintr_ctlr.h
new file mode 100644
index 0000000..a001c9d
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arintr_ctlr.h
@@ -0,0 +1,73752 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARINTR_CTLR_H_INC
+#define ARINTR_CTLR_H_INC
+#define NV_MOBILE_ARINTR_CTLR_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARINTR_CTLR_H_SCRREG_NOMENCLATURE INFERRED
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x4)
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE0_IER_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0                 MK_ADDR_CONST(0x8)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0                     MK_ADDR_CONST(0xc)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x10)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x14)
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE0_ISR_0
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0                 MK_ADDR_CONST(0x18)
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE0_IDR_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0                 MK_ADDR_CONST(0x1c)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_SCR                     CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x20)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x24)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x40)
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x44)
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE1_IER_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0                 MK_ADDR_CONST(0x48)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x4c)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x50)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x54)
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE1_ISR_0
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0                 MK_ADDR_CONST(0x58)
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE1_IDR_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0                 MK_ADDR_CONST(0x5c)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_SCR                     CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x60)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x64)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x80)
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x84)
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE2_IER_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0                 MK_ADDR_CONST(0x88)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x8c)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x90)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x94)
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE2_ISR_0
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0                 MK_ADDR_CONST(0x98)
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE2_IDR_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0                 MK_ADDR_CONST(0x9c)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_SCR                     CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0xa0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0xa4)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0                        MK_ADDR_CONST(0xc0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0                        MK_ADDR_CONST(0xc4)
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE3_IER_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0                 MK_ADDR_CONST(0xc8)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0                     MK_ADDR_CONST(0xcc)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0xd0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0xd4)
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE3_ISR_0
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0                 MK_ADDR_CONST(0xd8)
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE3_IDR_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0                 MK_ADDR_CONST(0xdc)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_SCR                     CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0xe0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0xe4)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x100)
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x104)
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE4_IER_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0                 MK_ADDR_CONST(0x108)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x10c)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x110)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x114)
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE4_ISR_0
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0                 MK_ADDR_CONST(0x118)
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE4_IDR_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0                 MK_ADDR_CONST(0x11c)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_SCR                     CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x120)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x124)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x140)
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x144)
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE5_IER_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0                 MK_ADDR_CONST(0x148)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x14c)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x150)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x154)
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE5_ISR_0
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0                 MK_ADDR_CONST(0x158)
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE5_IDR_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0                 MK_ADDR_CONST(0x15c)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_SCR                     CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x160)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x164)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x180)
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x184)
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE6_IER_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0                 MK_ADDR_CONST(0x188)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x18c)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x190)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x194)
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE6_ISR_0
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0                 MK_ADDR_CONST(0x198)
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE6_IDR_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0                 MK_ADDR_CONST(0x19c)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_SCR                     CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x1a0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x1a4)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x1c0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x1c4)
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE7_IER_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0                 MK_ADDR_CONST(0x1c8)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x1cc)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x1d0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x1d4)
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE7_ISR_0
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0                 MK_ADDR_CONST(0x1d8)
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE7_IDR_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0                 MK_ADDR_CONST(0x1dc)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_SCR                     CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x1e0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x1e4)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x200)
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x204)
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE8_IER_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0                 MK_ADDR_CONST(0x208)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x20c)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x210)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x214)
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE8_ISR_0
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0                 MK_ADDR_CONST(0x218)
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE8_IDR_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0                 MK_ADDR_CONST(0x21c)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_SCR                     CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x220)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x224)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x240)
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x244)
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE9_IER_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0                 MK_ADDR_CONST(0x248)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x24c)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x250)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_SCR                         CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x254)
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_SCR                       CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE9_ISR_0
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0                 MK_ADDR_CONST(0x258)
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_SCR                     CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE9_IDR_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0                 MK_ADDR_CONST(0x25c)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_SCR                     CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x260)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x264)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_SCR                         CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x280)
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_SCR                   CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x284)
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_SCR                   CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE10_IER_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0                        MK_ADDR_CONST(0x288)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x28c)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_SCR                        CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x290)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_SCR                        CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x294)
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_SCR                      CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE10_ISR_0
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0                        MK_ADDR_CONST(0x298)
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE10_IDR_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0                        MK_ADDR_CONST(0x29c)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_SCR                    CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x2a0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_SCR                        CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x2a4)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_SCR                        CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x2c0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_SCR                   CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x2c4)
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_SCR                   CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE11_IER_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0                        MK_ADDR_CONST(0x2c8)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x2cc)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_SCR                        CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x2d0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_SCR                        CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x2d4)
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_SCR                      CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE11_ISR_0
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0                        MK_ADDR_CONST(0x2d8)
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE11_IDR_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0                        MK_ADDR_CONST(0x2dc)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_SCR                    CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x2e0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_SCR                        CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x2e4)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_SCR                        CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x300)
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_SCR                   CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x304)
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_SCR                   CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE12_IER_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0                        MK_ADDR_CONST(0x308)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x30c)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_SCR                        CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x310)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_SCR                        CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x314)
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_SCR                      CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE12_ISR_0
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0                        MK_ADDR_CONST(0x318)
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE12_IDR_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0                        MK_ADDR_CONST(0x31c)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_SCR                    CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x320)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_SCR                        CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x324)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_SCR                        CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x340)
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_SCR                   CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x344)
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_SCR                   CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE13_IER_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0                        MK_ADDR_CONST(0x348)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x34c)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_SCR                        CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x350)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_SCR                        CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x354)
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_SCR                      CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE13_ISR_0
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0                        MK_ADDR_CONST(0x358)
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE13_IDR_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0                        MK_ADDR_CONST(0x35c)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_SCR                    CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x360)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_SCR                        CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x364)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_SCR                        CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x380)
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_SCR                   CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x384)
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_SCR                   CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE14_IER_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0                        MK_ADDR_CONST(0x388)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x38c)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_SCR                        CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x390)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_SCR                        CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x394)
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_SCR                      CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE14_ISR_0
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0                        MK_ADDR_CONST(0x398)
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE14_IDR_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0                        MK_ADDR_CONST(0x39c)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_SCR                    CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x3a0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_SCR                        CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x3a4)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_SCR                        CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x3c0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_SCR                   CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x3c4)
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_SCR                   CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE15_IER_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0                        MK_ADDR_CONST(0x3c8)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x3cc)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_SCR                        CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x3d0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_SCR                        CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x3d4)
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_SCR                      CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE15_ISR_0
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0                        MK_ADDR_CONST(0x3d8)
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE15_IDR_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0                        MK_ADDR_CONST(0x3dc)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_SCR                    CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x3e0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_SCR                        CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x3e4)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_SCR                        CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x400)
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_SCR                   CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x404)
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_SCR                   CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE16_IER_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0                        MK_ADDR_CONST(0x408)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x40c)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_SCR                        CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x410)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_SCR                        CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x414)
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_SCR                      CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE16_ISR_0
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0                        MK_ADDR_CONST(0x418)
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_SCR                    CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE16_IDR_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0                        MK_ADDR_CONST(0x41c)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_SCR                    CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x420)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_SCR                        CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x424)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_SCR                        CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0                  MK_ADDR_CONST(0x7c0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SCR                      0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0                  MK_ADDR_CONST(0x7c4)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SCR                      0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x800)
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x804)
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE0_IER_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0                 MK_ADDR_CONST(0x808)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x80c)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x810)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x814)
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE0_ISR_0
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0                 MK_ADDR_CONST(0x818)
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE0_IDR_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0                 MK_ADDR_CONST(0x81c)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_SCR                     CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x820)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x824)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x840)
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x844)
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE1_IER_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0                 MK_ADDR_CONST(0x848)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x84c)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x850)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x854)
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE1_ISR_0
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0                 MK_ADDR_CONST(0x858)
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE1_IDR_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0                 MK_ADDR_CONST(0x85c)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_SCR                     CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x860)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x864)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x880)
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x884)
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE2_IER_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0                 MK_ADDR_CONST(0x888)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x88c)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x890)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x894)
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE2_ISR_0
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0                 MK_ADDR_CONST(0x898)
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE2_IDR_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0                 MK_ADDR_CONST(0x89c)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_SCR                     CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x8a0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x8a4)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x8c0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x8c4)
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE3_IER_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0                 MK_ADDR_CONST(0x8c8)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x8cc)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x8d0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x8d4)
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE3_ISR_0
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0                 MK_ADDR_CONST(0x8d8)
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE3_IDR_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0                 MK_ADDR_CONST(0x8dc)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_SCR                     CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x8e0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x8e4)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x900)
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x904)
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE4_IER_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0                 MK_ADDR_CONST(0x908)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x90c)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x910)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x914)
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE4_ISR_0
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0                 MK_ADDR_CONST(0x918)
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE4_IDR_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0                 MK_ADDR_CONST(0x91c)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_SCR                     CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x920)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x924)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x940)
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x944)
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE5_IER_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0                 MK_ADDR_CONST(0x948)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x94c)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x950)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x954)
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE5_ISR_0
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0                 MK_ADDR_CONST(0x958)
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE5_IDR_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0                 MK_ADDR_CONST(0x95c)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_SCR                     CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x960)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x964)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x980)
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x984)
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE6_IER_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0                 MK_ADDR_CONST(0x988)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x98c)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x990)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x994)
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE6_ISR_0
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0                 MK_ADDR_CONST(0x998)
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE6_IDR_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0                 MK_ADDR_CONST(0x99c)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_SCR                     CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x9a0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x9a4)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x9c0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x9c4)
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE7_IER_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0                 MK_ADDR_CONST(0x9c8)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x9cc)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x9d0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x9d4)
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE7_ISR_0
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0                 MK_ADDR_CONST(0x9d8)
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE7_IDR_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0                 MK_ADDR_CONST(0x9dc)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_SCR                     CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x9e0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x9e4)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0                        MK_ADDR_CONST(0xa00)
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0                        MK_ADDR_CONST(0xa04)
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE8_IER_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0                 MK_ADDR_CONST(0xa08)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0                     MK_ADDR_CONST(0xa0c)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0xa10)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0xa14)
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE8_ISR_0
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0                 MK_ADDR_CONST(0xa18)
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE8_IDR_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0                 MK_ADDR_CONST(0xa1c)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_SCR                     CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0xa20)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0xa24)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0                        MK_ADDR_CONST(0xa40)
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0                        MK_ADDR_CONST(0xa44)
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE9_IER_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0                 MK_ADDR_CONST(0xa48)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0                     MK_ADDR_CONST(0xa4c)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0xa50)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_SCR                         CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0xa54)
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_SCR                       CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE9_ISR_0
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0                 MK_ADDR_CONST(0xa58)
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_SCR                     CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE9_IDR_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0                 MK_ADDR_CONST(0xa5c)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_SCR                     CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0xa60)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0xa64)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_SCR                         CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0                       MK_ADDR_CONST(0xa80)
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_SCR                   CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0                       MK_ADDR_CONST(0xa84)
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_SCR                   CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE10_IER_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0                        MK_ADDR_CONST(0xa88)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0                    MK_ADDR_CONST(0xa8c)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_SCR                        CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0xa90)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_SCR                        CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0xa94)
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_SCR                      CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE10_ISR_0
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0                        MK_ADDR_CONST(0xa98)
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE10_IDR_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0                        MK_ADDR_CONST(0xa9c)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_SCR                    CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0xaa0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_SCR                        CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0xaa4)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_SCR                        CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0                       MK_ADDR_CONST(0xac0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_SCR                   CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0                       MK_ADDR_CONST(0xac4)
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_SCR                   CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE11_IER_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0                        MK_ADDR_CONST(0xac8)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0                    MK_ADDR_CONST(0xacc)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_SCR                        CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0xad0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_SCR                        CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0xad4)
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_SCR                      CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE11_ISR_0
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0                        MK_ADDR_CONST(0xad8)
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE11_IDR_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0                        MK_ADDR_CONST(0xadc)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_SCR                    CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0xae0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_SCR                        CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0xae4)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_SCR                        CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0                       MK_ADDR_CONST(0xb00)
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_SCR                   CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0                       MK_ADDR_CONST(0xb04)
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_SCR                   CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE12_IER_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0                        MK_ADDR_CONST(0xb08)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0                    MK_ADDR_CONST(0xb0c)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_SCR                        CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0xb10)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_SCR                        CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0xb14)
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_SCR                      CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE12_ISR_0
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0                        MK_ADDR_CONST(0xb18)
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE12_IDR_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0                        MK_ADDR_CONST(0xb1c)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_SCR                    CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0xb20)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_SCR                        CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0xb24)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_SCR                        CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0                       MK_ADDR_CONST(0xb40)
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_SCR                   CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0                       MK_ADDR_CONST(0xb44)
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_SCR                   CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE13_IER_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0                        MK_ADDR_CONST(0xb48)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0                    MK_ADDR_CONST(0xb4c)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_SCR                        CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0xb50)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_SCR                        CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0xb54)
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_SCR                      CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE13_ISR_0
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0                        MK_ADDR_CONST(0xb58)
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE13_IDR_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0                        MK_ADDR_CONST(0xb5c)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_SCR                    CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0xb60)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_SCR                        CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0xb64)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_SCR                        CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0                       MK_ADDR_CONST(0xb80)
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_SCR                   CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0                       MK_ADDR_CONST(0xb84)
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_SCR                   CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE14_IER_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0                        MK_ADDR_CONST(0xb88)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0                    MK_ADDR_CONST(0xb8c)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_SCR                        CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0xb90)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_SCR                        CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0xb94)
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_SCR                      CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE14_ISR_0
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0                        MK_ADDR_CONST(0xb98)
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE14_IDR_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0                        MK_ADDR_CONST(0xb9c)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_SCR                    CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0xba0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_SCR                        CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0xba4)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_SCR                        CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0                       MK_ADDR_CONST(0xbc0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_SCR                   CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0                       MK_ADDR_CONST(0xbc4)
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_SCR                   CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE15_IER_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0                        MK_ADDR_CONST(0xbc8)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0                    MK_ADDR_CONST(0xbcc)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_SCR                        CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0xbd0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_SCR                        CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0xbd4)
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_SCR                      CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE15_ISR_0
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0                        MK_ADDR_CONST(0xbd8)
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE15_IDR_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0                        MK_ADDR_CONST(0xbdc)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_SCR                    CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0xbe0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_SCR                        CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0xbe4)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_SCR                        CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0                       MK_ADDR_CONST(0xc00)
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_SCR                   CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0                       MK_ADDR_CONST(0xc04)
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_SCR                   CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE16_IER_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0                        MK_ADDR_CONST(0xc08)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0                    MK_ADDR_CONST(0xc0c)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_SCR                        CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0xc10)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_SCR                        CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0xc14)
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_SCR                      CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE16_ISR_0
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0                        MK_ADDR_CONST(0xc18)
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_SCR                    CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE16_IDR_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0                        MK_ADDR_CONST(0xc1c)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_SCR                    CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0xc20)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_SCR                        CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0xc24)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_SCR                        CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0                  MK_ADDR_CONST(0xfc0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SCR                      0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0                  MK_ADDR_CONST(0xfc4)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SCR                      0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x1000)
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x1004)
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE0_IER_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0                 MK_ADDR_CONST(0x1008)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x100c)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x1010)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x1014)
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE0_ISR_0
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0                 MK_ADDR_CONST(0x1018)
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE0_IDR_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0                 MK_ADDR_CONST(0x101c)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_SCR                     CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x1020)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x1024)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x1040)
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x1044)
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE1_IER_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0                 MK_ADDR_CONST(0x1048)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x104c)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x1050)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x1054)
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE1_ISR_0
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0                 MK_ADDR_CONST(0x1058)
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE1_IDR_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0                 MK_ADDR_CONST(0x105c)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_SCR                     CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x1060)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x1064)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x1080)
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x1084)
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE2_IER_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0                 MK_ADDR_CONST(0x1088)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x108c)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x1090)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x1094)
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE2_ISR_0
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0                 MK_ADDR_CONST(0x1098)
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE2_IDR_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0                 MK_ADDR_CONST(0x109c)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_SCR                     CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x10a0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x10a4)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x10c0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x10c4)
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE3_IER_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0                 MK_ADDR_CONST(0x10c8)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x10cc)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x10d0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x10d4)
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE3_ISR_0
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0                 MK_ADDR_CONST(0x10d8)
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE3_IDR_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0                 MK_ADDR_CONST(0x10dc)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_SCR                     CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x10e0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x10e4)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x1100)
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x1104)
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE4_IER_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0                 MK_ADDR_CONST(0x1108)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x110c)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x1110)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x1114)
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE4_ISR_0
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0                 MK_ADDR_CONST(0x1118)
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE4_IDR_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0                 MK_ADDR_CONST(0x111c)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_SCR                     CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x1120)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x1124)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x1140)
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x1144)
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE5_IER_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0                 MK_ADDR_CONST(0x1148)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x114c)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x1150)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x1154)
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE5_ISR_0
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0                 MK_ADDR_CONST(0x1158)
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE5_IDR_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0                 MK_ADDR_CONST(0x115c)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_SCR                     CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x1160)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x1164)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x1180)
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x1184)
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE6_IER_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0                 MK_ADDR_CONST(0x1188)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x118c)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x1190)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x1194)
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE6_ISR_0
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0                 MK_ADDR_CONST(0x1198)
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE6_IDR_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0                 MK_ADDR_CONST(0x119c)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_SCR                     CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x11a0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x11a4)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x11c0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x11c4)
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE7_IER_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0                 MK_ADDR_CONST(0x11c8)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x11cc)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x11d0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x11d4)
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE7_ISR_0
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0                 MK_ADDR_CONST(0x11d8)
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE7_IDR_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0                 MK_ADDR_CONST(0x11dc)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_SCR                     CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x11e0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x11e4)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x1200)
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x1204)
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE8_IER_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0                 MK_ADDR_CONST(0x1208)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x120c)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x1210)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x1214)
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE8_ISR_0
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0                 MK_ADDR_CONST(0x1218)
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE8_IDR_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0                 MK_ADDR_CONST(0x121c)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_SCR                     CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x1220)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x1224)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x1240)
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x1244)
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE9_IER_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0                 MK_ADDR_CONST(0x1248)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x124c)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x1250)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_SCR                         CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x1254)
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_SCR                       CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE9_ISR_0
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0                 MK_ADDR_CONST(0x1258)
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_SCR                     CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE9_IDR_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0                 MK_ADDR_CONST(0x125c)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_SCR                     CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x1260)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x1264)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_SCR                         CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x1280)
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_SCR                   CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x1284)
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_SCR                   CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE10_IER_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0                        MK_ADDR_CONST(0x1288)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x128c)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_SCR                        CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x1290)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_SCR                        CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x1294)
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_SCR                      CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE10_ISR_0
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0                        MK_ADDR_CONST(0x1298)
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE10_IDR_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0                        MK_ADDR_CONST(0x129c)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_SCR                    CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x12a0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_SCR                        CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x12a4)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_SCR                        CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x12c0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_SCR                   CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x12c4)
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_SCR                   CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE11_IER_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0                        MK_ADDR_CONST(0x12c8)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x12cc)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_SCR                        CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x12d0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_SCR                        CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x12d4)
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_SCR                      CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE11_ISR_0
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0                        MK_ADDR_CONST(0x12d8)
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE11_IDR_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0                        MK_ADDR_CONST(0x12dc)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_SCR                    CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x12e0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_SCR                        CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x12e4)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_SCR                        CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x1300)
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_SCR                   CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x1304)
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_SCR                   CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE12_IER_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0                        MK_ADDR_CONST(0x1308)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x130c)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_SCR                        CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x1310)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_SCR                        CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x1314)
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_SCR                      CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE12_ISR_0
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0                        MK_ADDR_CONST(0x1318)
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE12_IDR_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0                        MK_ADDR_CONST(0x131c)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_SCR                    CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x1320)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_SCR                        CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x1324)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_SCR                        CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x1340)
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_SCR                   CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x1344)
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_SCR                   CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE13_IER_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0                        MK_ADDR_CONST(0x1348)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x134c)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_SCR                        CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x1350)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_SCR                        CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x1354)
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_SCR                      CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE13_ISR_0
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0                        MK_ADDR_CONST(0x1358)
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE13_IDR_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0                        MK_ADDR_CONST(0x135c)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_SCR                    CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x1360)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_SCR                        CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x1364)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_SCR                        CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x1380)
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_SCR                   CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x1384)
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_SCR                   CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE14_IER_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0                        MK_ADDR_CONST(0x1388)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x138c)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_SCR                        CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x1390)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_SCR                        CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x1394)
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_SCR                      CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE14_ISR_0
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0                        MK_ADDR_CONST(0x1398)
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE14_IDR_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0                        MK_ADDR_CONST(0x139c)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_SCR                    CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x13a0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_SCR                        CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x13a4)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_SCR                        CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x13c0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_SCR                   CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x13c4)
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_SCR                   CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE15_IER_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0                        MK_ADDR_CONST(0x13c8)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x13cc)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_SCR                        CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x13d0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_SCR                        CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x13d4)
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_SCR                      CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE15_ISR_0
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0                        MK_ADDR_CONST(0x13d8)
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE15_IDR_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0                        MK_ADDR_CONST(0x13dc)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_SCR                    CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x13e0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_SCR                        CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x13e4)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_SCR                        CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x1400)
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_SCR                   CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x1404)
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_SCR                   CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE16_IER_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0                        MK_ADDR_CONST(0x1408)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x140c)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_SCR                        CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x1410)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_SCR                        CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x1414)
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_SCR                      CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE16_ISR_0
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0                        MK_ADDR_CONST(0x1418)
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_SCR                    CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE16_IDR_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0                        MK_ADDR_CONST(0x141c)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_SCR                    CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x1420)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_SCR                        CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x1424)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_SCR                        CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0                  MK_ADDR_CONST(0x17c0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SCR                      0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0                  MK_ADDR_CONST(0x17c4)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SCR                      0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x1800)
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x1804)
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE0_IER_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0                 MK_ADDR_CONST(0x1808)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x180c)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x1810)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x1814)
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE0_ISR_0
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0                 MK_ADDR_CONST(0x1818)
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE0_IDR_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0                 MK_ADDR_CONST(0x181c)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_SCR                     CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x1820)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x1824)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x1840)
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x1844)
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE1_IER_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0                 MK_ADDR_CONST(0x1848)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x184c)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x1850)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x1854)
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE1_ISR_0
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0                 MK_ADDR_CONST(0x1858)
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE1_IDR_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0                 MK_ADDR_CONST(0x185c)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_SCR                     CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x1860)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x1864)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x1880)
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x1884)
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE2_IER_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0                 MK_ADDR_CONST(0x1888)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x188c)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x1890)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x1894)
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE2_ISR_0
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0                 MK_ADDR_CONST(0x1898)
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE2_IDR_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0                 MK_ADDR_CONST(0x189c)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_SCR                     CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x18a0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x18a4)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x18c0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x18c4)
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE3_IER_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0                 MK_ADDR_CONST(0x18c8)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x18cc)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x18d0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x18d4)
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE3_ISR_0
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0                 MK_ADDR_CONST(0x18d8)
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE3_IDR_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0                 MK_ADDR_CONST(0x18dc)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_SCR                     CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x18e0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x18e4)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x1900)
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x1904)
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE4_IER_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0                 MK_ADDR_CONST(0x1908)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x190c)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x1910)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x1914)
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE4_ISR_0
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0                 MK_ADDR_CONST(0x1918)
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE4_IDR_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0                 MK_ADDR_CONST(0x191c)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_SCR                     CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x1920)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x1924)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x1940)
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x1944)
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE5_IER_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0                 MK_ADDR_CONST(0x1948)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x194c)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x1950)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x1954)
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE5_ISR_0
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0                 MK_ADDR_CONST(0x1958)
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE5_IDR_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0                 MK_ADDR_CONST(0x195c)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_SCR                     CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x1960)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x1964)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x1980)
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x1984)
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE6_IER_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0                 MK_ADDR_CONST(0x1988)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x198c)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x1990)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x1994)
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE6_ISR_0
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0                 MK_ADDR_CONST(0x1998)
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE6_IDR_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0                 MK_ADDR_CONST(0x199c)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_SCR                     CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x19a0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x19a4)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x19c0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x19c4)
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE7_IER_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0                 MK_ADDR_CONST(0x19c8)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x19cc)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x19d0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x19d4)
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE7_ISR_0
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0                 MK_ADDR_CONST(0x19d8)
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE7_IDR_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0                 MK_ADDR_CONST(0x19dc)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_SCR                     CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x19e0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x19e4)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x1a00)
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x1a04)
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE8_IER_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0                 MK_ADDR_CONST(0x1a08)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x1a0c)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x1a10)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x1a14)
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE8_ISR_0
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0                 MK_ADDR_CONST(0x1a18)
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE8_IDR_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0                 MK_ADDR_CONST(0x1a1c)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_SCR                     CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x1a20)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x1a24)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x1a40)
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x1a44)
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE9_IER_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0                 MK_ADDR_CONST(0x1a48)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x1a4c)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x1a50)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_SCR                         CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x1a54)
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_SCR                       CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE9_ISR_0
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0                 MK_ADDR_CONST(0x1a58)
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_SCR                     CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE9_IDR_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0                 MK_ADDR_CONST(0x1a5c)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_SCR                     CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x1a60)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x1a64)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_SCR                         CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x1a80)
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_SCR                   CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x1a84)
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_SCR                   CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE10_IER_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0                        MK_ADDR_CONST(0x1a88)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x1a8c)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_SCR                        CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x1a90)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_SCR                        CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x1a94)
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_SCR                      CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE10_ISR_0
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0                        MK_ADDR_CONST(0x1a98)
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE10_IDR_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0                        MK_ADDR_CONST(0x1a9c)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_SCR                    CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x1aa0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_SCR                        CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x1aa4)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_SCR                        CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x1ac0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_SCR                   CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x1ac4)
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_SCR                   CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE11_IER_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0                        MK_ADDR_CONST(0x1ac8)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x1acc)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_SCR                        CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x1ad0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_SCR                        CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x1ad4)
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_SCR                      CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE11_ISR_0
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0                        MK_ADDR_CONST(0x1ad8)
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE11_IDR_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0                        MK_ADDR_CONST(0x1adc)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_SCR                    CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x1ae0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_SCR                        CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x1ae4)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_SCR                        CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x1b00)
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_SCR                   CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x1b04)
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_SCR                   CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE12_IER_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0                        MK_ADDR_CONST(0x1b08)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x1b0c)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_SCR                        CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x1b10)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_SCR                        CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x1b14)
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_SCR                      CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE12_ISR_0
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0                        MK_ADDR_CONST(0x1b18)
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE12_IDR_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0                        MK_ADDR_CONST(0x1b1c)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_SCR                    CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x1b20)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_SCR                        CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x1b24)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_SCR                        CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x1b40)
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_SCR                   CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x1b44)
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_SCR                   CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE13_IER_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0                        MK_ADDR_CONST(0x1b48)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x1b4c)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_SCR                        CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x1b50)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_SCR                        CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x1b54)
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_SCR                      CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE13_ISR_0
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0                        MK_ADDR_CONST(0x1b58)
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE13_IDR_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0                        MK_ADDR_CONST(0x1b5c)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_SCR                    CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x1b60)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_SCR                        CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x1b64)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_SCR                        CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x1b80)
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_SCR                   CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x1b84)
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_SCR                   CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE14_IER_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0                        MK_ADDR_CONST(0x1b88)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x1b8c)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_SCR                        CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x1b90)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_SCR                        CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x1b94)
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_SCR                      CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE14_ISR_0
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0                        MK_ADDR_CONST(0x1b98)
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE14_IDR_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0                        MK_ADDR_CONST(0x1b9c)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_SCR                    CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x1ba0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_SCR                        CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x1ba4)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_SCR                        CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x1bc0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_SCR                   CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x1bc4)
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_SCR                   CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE15_IER_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0                        MK_ADDR_CONST(0x1bc8)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x1bcc)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_SCR                        CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x1bd0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_SCR                        CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x1bd4)
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_SCR                      CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE15_ISR_0
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0                        MK_ADDR_CONST(0x1bd8)
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE15_IDR_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0                        MK_ADDR_CONST(0x1bdc)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_SCR                    CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x1be0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_SCR                        CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x1be4)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_SCR                        CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x1c00)
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_SCR                   CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x1c04)
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_SCR                   CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE16_IER_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0                        MK_ADDR_CONST(0x1c08)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x1c0c)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_SCR                        CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x1c10)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_SCR                        CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x1c14)
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_SCR                      CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE16_ISR_0
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0                        MK_ADDR_CONST(0x1c18)
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_SCR                    CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE16_IDR_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0                        MK_ADDR_CONST(0x1c1c)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_SCR                    CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x1c20)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_SCR                        CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x1c24)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_SCR                        CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0                  MK_ADDR_CONST(0x1fc0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SCR                      0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0                  MK_ADDR_CONST(0x1fc4)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SCR                      0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x2000)
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x2004)
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE0_IER_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0                 MK_ADDR_CONST(0x2008)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x200c)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x2010)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x2014)
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE0_ISR_0
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0                 MK_ADDR_CONST(0x2018)
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE0_IDR_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0                 MK_ADDR_CONST(0x201c)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_SCR                     CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x2020)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x2024)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x2040)
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x2044)
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE1_IER_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0                 MK_ADDR_CONST(0x2048)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x204c)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x2050)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x2054)
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE1_ISR_0
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0                 MK_ADDR_CONST(0x2058)
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE1_IDR_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0                 MK_ADDR_CONST(0x205c)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_SCR                     CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x2060)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x2064)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x2080)
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x2084)
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE2_IER_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0                 MK_ADDR_CONST(0x2088)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x208c)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x2090)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x2094)
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE2_ISR_0
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0                 MK_ADDR_CONST(0x2098)
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE2_IDR_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0                 MK_ADDR_CONST(0x209c)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_SCR                     CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x20a0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x20a4)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x20c0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x20c4)
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE3_IER_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0                 MK_ADDR_CONST(0x20c8)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x20cc)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x20d0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x20d4)
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE3_ISR_0
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0                 MK_ADDR_CONST(0x20d8)
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE3_IDR_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0                 MK_ADDR_CONST(0x20dc)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_SCR                     CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x20e0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x20e4)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x2100)
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x2104)
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE4_IER_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0                 MK_ADDR_CONST(0x2108)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x210c)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x2110)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x2114)
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE4_ISR_0
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0                 MK_ADDR_CONST(0x2118)
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE4_IDR_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0                 MK_ADDR_CONST(0x211c)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_SCR                     CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x2120)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x2124)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x2140)
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x2144)
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE5_IER_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0                 MK_ADDR_CONST(0x2148)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x214c)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x2150)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x2154)
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE5_ISR_0
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0                 MK_ADDR_CONST(0x2158)
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE5_IDR_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0                 MK_ADDR_CONST(0x215c)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_SCR                     CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x2160)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x2164)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x2180)
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x2184)
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE6_IER_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0                 MK_ADDR_CONST(0x2188)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x218c)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x2190)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x2194)
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE6_ISR_0
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0                 MK_ADDR_CONST(0x2198)
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE6_IDR_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0                 MK_ADDR_CONST(0x219c)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_SCR                     CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x21a0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x21a4)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x21c0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x21c4)
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE7_IER_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0                 MK_ADDR_CONST(0x21c8)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x21cc)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x21d0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x21d4)
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE7_ISR_0
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0                 MK_ADDR_CONST(0x21d8)
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE7_IDR_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0                 MK_ADDR_CONST(0x21dc)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_SCR                     CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x21e0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x21e4)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x2200)
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x2204)
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE8_IER_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0                 MK_ADDR_CONST(0x2208)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x220c)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x2210)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x2214)
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE8_ISR_0
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0                 MK_ADDR_CONST(0x2218)
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE8_IDR_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0                 MK_ADDR_CONST(0x221c)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_SCR                     CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x2220)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x2224)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x2240)
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x2244)
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE9_IER_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0                 MK_ADDR_CONST(0x2248)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x224c)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x2250)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_SCR                         CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x2254)
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_SCR                       CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE9_ISR_0
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0                 MK_ADDR_CONST(0x2258)
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_SCR                     CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE9_IDR_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0                 MK_ADDR_CONST(0x225c)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_SCR                     CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x2260)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x2264)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_SCR                         CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x2280)
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_SCR                   CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x2284)
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_SCR                   CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE10_IER_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0                        MK_ADDR_CONST(0x2288)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x228c)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_SCR                        CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x2290)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_SCR                        CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x2294)
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_SCR                      CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE10_ISR_0
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0                        MK_ADDR_CONST(0x2298)
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE10_IDR_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0                        MK_ADDR_CONST(0x229c)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_SCR                    CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x22a0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_SCR                        CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x22a4)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_SCR                        CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x22c0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_SCR                   CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x22c4)
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_SCR                   CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE11_IER_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0                        MK_ADDR_CONST(0x22c8)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x22cc)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_SCR                        CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x22d0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_SCR                        CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x22d4)
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_SCR                      CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE11_ISR_0
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0                        MK_ADDR_CONST(0x22d8)
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE11_IDR_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0                        MK_ADDR_CONST(0x22dc)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_SCR                    CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x22e0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_SCR                        CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x22e4)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_SCR                        CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x2300)
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_SCR                   CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x2304)
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_SCR                   CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE12_IER_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0                        MK_ADDR_CONST(0x2308)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x230c)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_SCR                        CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x2310)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_SCR                        CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x2314)
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_SCR                      CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE12_ISR_0
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0                        MK_ADDR_CONST(0x2318)
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE12_IDR_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0                        MK_ADDR_CONST(0x231c)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_SCR                    CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x2320)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_SCR                        CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x2324)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_SCR                        CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x2340)
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_SCR                   CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x2344)
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_SCR                   CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE13_IER_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0                        MK_ADDR_CONST(0x2348)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x234c)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_SCR                        CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x2350)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_SCR                        CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x2354)
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_SCR                      CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE13_ISR_0
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0                        MK_ADDR_CONST(0x2358)
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE13_IDR_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0                        MK_ADDR_CONST(0x235c)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_SCR                    CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x2360)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_SCR                        CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x2364)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_SCR                        CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x2380)
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_SCR                   CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x2384)
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_SCR                   CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE14_IER_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0                        MK_ADDR_CONST(0x2388)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x238c)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_SCR                        CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x2390)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_SCR                        CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x2394)
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_SCR                      CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE14_ISR_0
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0                        MK_ADDR_CONST(0x2398)
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE14_IDR_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0                        MK_ADDR_CONST(0x239c)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_SCR                    CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x23a0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_SCR                        CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x23a4)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_SCR                        CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x23c0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_SCR                   CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x23c4)
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_SCR                   CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE15_IER_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0                        MK_ADDR_CONST(0x23c8)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x23cc)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_SCR                        CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x23d0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_SCR                        CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x23d4)
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_SCR                      CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE15_ISR_0
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0                        MK_ADDR_CONST(0x23d8)
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE15_IDR_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0                        MK_ADDR_CONST(0x23dc)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_SCR                    CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x23e0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_SCR                        CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x23e4)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_SCR                        CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x2400)
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_SCR                   CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x2404)
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_SCR                   CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE16_IER_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0                        MK_ADDR_CONST(0x2408)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x240c)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_SCR                        CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x2410)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_SCR                        CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x2414)
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_SCR                      CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE16_ISR_0
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0                        MK_ADDR_CONST(0x2418)
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_SCR                    CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE16_IDR_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0                        MK_ADDR_CONST(0x241c)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_SCR                    CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x2420)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_SCR                        CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x2424)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_SCR                        CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0                  MK_ADDR_CONST(0x27c0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SCR                      0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0                  MK_ADDR_CONST(0x27c4)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SCR                      0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x2800)
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x2804)
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE0_IER_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0                 MK_ADDR_CONST(0x2808)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x280c)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x2810)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x2814)
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE0_ISR_0
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0                 MK_ADDR_CONST(0x2818)
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE0_IDR_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0                 MK_ADDR_CONST(0x281c)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_SCR                     CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x2820)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x2824)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x2840)
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x2844)
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE1_IER_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0                 MK_ADDR_CONST(0x2848)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x284c)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x2850)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x2854)
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE1_ISR_0
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0                 MK_ADDR_CONST(0x2858)
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE1_IDR_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0                 MK_ADDR_CONST(0x285c)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_SCR                     CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x2860)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x2864)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x2880)
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x2884)
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE2_IER_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0                 MK_ADDR_CONST(0x2888)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x288c)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x2890)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x2894)
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE2_ISR_0
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0                 MK_ADDR_CONST(0x2898)
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE2_IDR_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0                 MK_ADDR_CONST(0x289c)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_SCR                     CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x28a0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x28a4)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x28c0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x28c4)
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE3_IER_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0                 MK_ADDR_CONST(0x28c8)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x28cc)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x28d0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x28d4)
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE3_ISR_0
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0                 MK_ADDR_CONST(0x28d8)
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE3_IDR_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0                 MK_ADDR_CONST(0x28dc)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_SCR                     CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x28e0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x28e4)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x2900)
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x2904)
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE4_IER_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0                 MK_ADDR_CONST(0x2908)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x290c)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x2910)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x2914)
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE4_ISR_0
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0                 MK_ADDR_CONST(0x2918)
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE4_IDR_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0                 MK_ADDR_CONST(0x291c)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_SCR                     CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x2920)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x2924)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x2940)
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x2944)
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE5_IER_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0                 MK_ADDR_CONST(0x2948)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x294c)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x2950)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x2954)
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE5_ISR_0
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0                 MK_ADDR_CONST(0x2958)
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE5_IDR_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0                 MK_ADDR_CONST(0x295c)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_SCR                     CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x2960)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x2964)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x2980)
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x2984)
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE6_IER_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0                 MK_ADDR_CONST(0x2988)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x298c)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x2990)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x2994)
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE6_ISR_0
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0                 MK_ADDR_CONST(0x2998)
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE6_IDR_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0                 MK_ADDR_CONST(0x299c)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_SCR                     CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x29a0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x29a4)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x29c0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x29c4)
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE7_IER_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0                 MK_ADDR_CONST(0x29c8)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x29cc)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x29d0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x29d4)
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE7_ISR_0
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0                 MK_ADDR_CONST(0x29d8)
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE7_IDR_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0                 MK_ADDR_CONST(0x29dc)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_SCR                     CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x29e0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x29e4)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x2a00)
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x2a04)
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE8_IER_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0                 MK_ADDR_CONST(0x2a08)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x2a0c)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x2a10)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x2a14)
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE8_ISR_0
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0                 MK_ADDR_CONST(0x2a18)
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE8_IDR_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0                 MK_ADDR_CONST(0x2a1c)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_SCR                     CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x2a20)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x2a24)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x2a40)
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x2a44)
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE9_IER_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0                 MK_ADDR_CONST(0x2a48)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x2a4c)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x2a50)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_SCR                         CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x2a54)
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_SCR                       CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE9_ISR_0
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0                 MK_ADDR_CONST(0x2a58)
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_SCR                     CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE9_IDR_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0                 MK_ADDR_CONST(0x2a5c)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_SCR                     CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x2a60)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x2a64)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_SCR                         CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x2a80)
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_SCR                   CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x2a84)
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_SCR                   CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE10_IER_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0                        MK_ADDR_CONST(0x2a88)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x2a8c)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_SCR                        CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x2a90)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_SCR                        CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x2a94)
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_SCR                      CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE10_ISR_0
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0                        MK_ADDR_CONST(0x2a98)
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE10_IDR_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0                        MK_ADDR_CONST(0x2a9c)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_SCR                    CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x2aa0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_SCR                        CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x2aa4)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_SCR                        CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x2ac0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_SCR                   CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x2ac4)
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_SCR                   CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE11_IER_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0                        MK_ADDR_CONST(0x2ac8)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x2acc)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_SCR                        CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x2ad0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_SCR                        CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x2ad4)
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_SCR                      CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE11_ISR_0
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0                        MK_ADDR_CONST(0x2ad8)
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE11_IDR_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0                        MK_ADDR_CONST(0x2adc)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_SCR                    CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x2ae0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_SCR                        CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x2ae4)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_SCR                        CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x2b00)
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_SCR                   CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x2b04)
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_SCR                   CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE12_IER_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0                        MK_ADDR_CONST(0x2b08)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x2b0c)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_SCR                        CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x2b10)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_SCR                        CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x2b14)
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_SCR                      CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE12_ISR_0
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0                        MK_ADDR_CONST(0x2b18)
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE12_IDR_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0                        MK_ADDR_CONST(0x2b1c)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_SCR                    CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x2b20)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_SCR                        CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x2b24)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_SCR                        CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x2b40)
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_SCR                   CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x2b44)
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_SCR                   CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE13_IER_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0                        MK_ADDR_CONST(0x2b48)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x2b4c)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_SCR                        CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x2b50)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_SCR                        CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x2b54)
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_SCR                      CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE13_ISR_0
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0                        MK_ADDR_CONST(0x2b58)
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE13_IDR_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0                        MK_ADDR_CONST(0x2b5c)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_SCR                    CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x2b60)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_SCR                        CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x2b64)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_SCR                        CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x2b80)
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_SCR                   CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x2b84)
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_SCR                   CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE14_IER_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0                        MK_ADDR_CONST(0x2b88)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x2b8c)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_SCR                        CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x2b90)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_SCR                        CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x2b94)
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_SCR                      CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE14_ISR_0
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0                        MK_ADDR_CONST(0x2b98)
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE14_IDR_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0                        MK_ADDR_CONST(0x2b9c)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_SCR                    CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x2ba0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_SCR                        CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x2ba4)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_SCR                        CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x2bc0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_SCR                   CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x2bc4)
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_SCR                   CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE15_IER_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0                        MK_ADDR_CONST(0x2bc8)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x2bcc)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_SCR                        CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x2bd0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_SCR                        CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x2bd4)
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_SCR                      CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE15_ISR_0
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0                        MK_ADDR_CONST(0x2bd8)
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE15_IDR_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0                        MK_ADDR_CONST(0x2bdc)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_SCR                    CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x2be0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_SCR                        CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x2be4)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_SCR                        CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x2c00)
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_SCR                   CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x2c04)
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_SCR                   CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE16_IER_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0                        MK_ADDR_CONST(0x2c08)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x2c0c)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_SCR                        CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x2c10)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_SCR                        CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x2c14)
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_SCR                      CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE16_ISR_0
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0                        MK_ADDR_CONST(0x2c18)
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_SCR                    CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE16_IDR_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0                        MK_ADDR_CONST(0x2c1c)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_SCR                    CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x2c20)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_SCR                        CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x2c24)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_SCR                        CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0                  MK_ADDR_CONST(0x2fc0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SCR                      0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0                  MK_ADDR_CONST(0x2fc4)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SCR                      0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x3000)
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x3004)
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE0_IER_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0                 MK_ADDR_CONST(0x3008)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x300c)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x3010)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x3014)
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE0_ISR_0
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0                 MK_ADDR_CONST(0x3018)
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE0_IDR_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0                 MK_ADDR_CONST(0x301c)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_SCR                     CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x3020)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x3024)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x3040)
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x3044)
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE1_IER_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0                 MK_ADDR_CONST(0x3048)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x304c)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x3050)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x3054)
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE1_ISR_0
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0                 MK_ADDR_CONST(0x3058)
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE1_IDR_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0                 MK_ADDR_CONST(0x305c)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_SCR                     CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x3060)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x3064)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x3080)
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x3084)
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE2_IER_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0                 MK_ADDR_CONST(0x3088)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x308c)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x3090)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x3094)
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE2_ISR_0
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0                 MK_ADDR_CONST(0x3098)
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE2_IDR_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0                 MK_ADDR_CONST(0x309c)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_SCR                     CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x30a0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x30a4)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x30c0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x30c4)
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE3_IER_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0                 MK_ADDR_CONST(0x30c8)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x30cc)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x30d0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x30d4)
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE3_ISR_0
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0                 MK_ADDR_CONST(0x30d8)
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE3_IDR_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0                 MK_ADDR_CONST(0x30dc)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_SCR                     CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x30e0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x30e4)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x3100)
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x3104)
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE4_IER_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0                 MK_ADDR_CONST(0x3108)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x310c)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x3110)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x3114)
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE4_ISR_0
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0                 MK_ADDR_CONST(0x3118)
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE4_IDR_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0                 MK_ADDR_CONST(0x311c)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_SCR                     CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x3120)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x3124)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x3140)
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x3144)
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE5_IER_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0                 MK_ADDR_CONST(0x3148)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x314c)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x3150)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x3154)
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE5_ISR_0
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0                 MK_ADDR_CONST(0x3158)
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE5_IDR_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0                 MK_ADDR_CONST(0x315c)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_SCR                     CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x3160)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x3164)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x3180)
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x3184)
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE6_IER_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0                 MK_ADDR_CONST(0x3188)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x318c)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x3190)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x3194)
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE6_ISR_0
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0                 MK_ADDR_CONST(0x3198)
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE6_IDR_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0                 MK_ADDR_CONST(0x319c)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_SCR                     CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x31a0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x31a4)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x31c0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x31c4)
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE7_IER_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0                 MK_ADDR_CONST(0x31c8)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x31cc)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x31d0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x31d4)
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE7_ISR_0
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0                 MK_ADDR_CONST(0x31d8)
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE7_IDR_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0                 MK_ADDR_CONST(0x31dc)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_SCR                     CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x31e0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x31e4)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x3200)
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x3204)
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE8_IER_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0                 MK_ADDR_CONST(0x3208)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x320c)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x3210)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x3214)
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE8_ISR_0
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0                 MK_ADDR_CONST(0x3218)
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE8_IDR_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0                 MK_ADDR_CONST(0x321c)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_SCR                     CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x3220)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x3224)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x3240)
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x3244)
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE9_IER_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0                 MK_ADDR_CONST(0x3248)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x324c)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x3250)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_SCR                         CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x3254)
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_SCR                       CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE9_ISR_0
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0                 MK_ADDR_CONST(0x3258)
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_SCR                     CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE9_IDR_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0                 MK_ADDR_CONST(0x325c)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_SCR                     CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x3260)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x3264)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_SCR                         CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x3280)
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_SCR                   CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x3284)
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_SCR                   CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE10_IER_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0                        MK_ADDR_CONST(0x3288)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x328c)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_SCR                        CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x3290)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_SCR                        CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x3294)
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_SCR                      CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE10_ISR_0
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0                        MK_ADDR_CONST(0x3298)
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE10_IDR_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0                        MK_ADDR_CONST(0x329c)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_SCR                    CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x32a0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_SCR                        CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x32a4)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_SCR                        CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x32c0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_SCR                   CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x32c4)
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_SCR                   CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE11_IER_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0                        MK_ADDR_CONST(0x32c8)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x32cc)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_SCR                        CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x32d0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_SCR                        CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x32d4)
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_SCR                      CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE11_ISR_0
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0                        MK_ADDR_CONST(0x32d8)
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE11_IDR_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0                        MK_ADDR_CONST(0x32dc)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_SCR                    CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x32e0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_SCR                        CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x32e4)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_SCR                        CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x3300)
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_SCR                   CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x3304)
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_SCR                   CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE12_IER_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0                        MK_ADDR_CONST(0x3308)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x330c)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_SCR                        CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x3310)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_SCR                        CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x3314)
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_SCR                      CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE12_ISR_0
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0                        MK_ADDR_CONST(0x3318)
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE12_IDR_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0                        MK_ADDR_CONST(0x331c)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_SCR                    CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x3320)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_SCR                        CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x3324)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_SCR                        CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x3340)
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_SCR                   CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x3344)
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_SCR                   CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE13_IER_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0                        MK_ADDR_CONST(0x3348)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x334c)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_SCR                        CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x3350)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_SCR                        CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x3354)
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_SCR                      CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE13_ISR_0
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0                        MK_ADDR_CONST(0x3358)
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE13_IDR_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0                        MK_ADDR_CONST(0x335c)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_SCR                    CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x3360)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_SCR                        CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x3364)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_SCR                        CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x3380)
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_SCR                   CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x3384)
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_SCR                   CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE14_IER_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0                        MK_ADDR_CONST(0x3388)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x338c)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_SCR                        CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x3390)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_SCR                        CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x3394)
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_SCR                      CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE14_ISR_0
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0                        MK_ADDR_CONST(0x3398)
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE14_IDR_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0                        MK_ADDR_CONST(0x339c)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_SCR                    CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x33a0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_SCR                        CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x33a4)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_SCR                        CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x33c0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_SCR                   CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x33c4)
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_SCR                   CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE15_IER_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0                        MK_ADDR_CONST(0x33c8)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x33cc)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_SCR                        CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x33d0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_SCR                        CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x33d4)
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_SCR                      CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE15_ISR_0
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0                        MK_ADDR_CONST(0x33d8)
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE15_IDR_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0                        MK_ADDR_CONST(0x33dc)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_SCR                    CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x33e0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_SCR                        CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x33e4)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_SCR                        CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x3400)
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_SCR                   CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x3404)
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_SCR                   CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE16_IER_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0                        MK_ADDR_CONST(0x3408)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x340c)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_SCR                        CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x3410)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_SCR                        CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x3414)
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_SCR                      CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE16_ISR_0
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0                        MK_ADDR_CONST(0x3418)
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_SCR                    CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE16_IDR_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0                        MK_ADDR_CONST(0x341c)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_SCR                    CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x3420)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_SCR                        CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x3424)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_SCR                        CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0                  MK_ADDR_CONST(0x37c0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SCR                      0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0                  MK_ADDR_CONST(0x37c4)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SCR                      0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x3800)
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x3804)
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE0_IER_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0                 MK_ADDR_CONST(0x3808)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x380c)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x3810)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x3814)
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE0_ISR_0
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0                 MK_ADDR_CONST(0x3818)
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE0_IDR_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0                 MK_ADDR_CONST(0x381c)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_SCR                     CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x3820)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x3824)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x3840)
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x3844)
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE1_IER_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0                 MK_ADDR_CONST(0x3848)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x384c)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x3850)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x3854)
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE1_ISR_0
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0                 MK_ADDR_CONST(0x3858)
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE1_IDR_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0                 MK_ADDR_CONST(0x385c)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_SCR                     CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x3860)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x3864)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x3880)
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x3884)
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE2_IER_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0                 MK_ADDR_CONST(0x3888)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x388c)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x3890)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x3894)
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE2_ISR_0
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0                 MK_ADDR_CONST(0x3898)
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE2_IDR_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0                 MK_ADDR_CONST(0x389c)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_SCR                     CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x38a0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x38a4)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x38c0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x38c4)
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE3_IER_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0                 MK_ADDR_CONST(0x38c8)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x38cc)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x38d0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x38d4)
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE3_ISR_0
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0                 MK_ADDR_CONST(0x38d8)
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE3_IDR_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0                 MK_ADDR_CONST(0x38dc)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_SCR                     CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x38e0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x38e4)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x3900)
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x3904)
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE4_IER_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0                 MK_ADDR_CONST(0x3908)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x390c)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x3910)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x3914)
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE4_ISR_0
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0                 MK_ADDR_CONST(0x3918)
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE4_IDR_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0                 MK_ADDR_CONST(0x391c)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_SCR                     CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x3920)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x3924)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x3940)
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x3944)
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE5_IER_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0                 MK_ADDR_CONST(0x3948)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x394c)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x3950)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x3954)
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE5_ISR_0
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0                 MK_ADDR_CONST(0x3958)
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE5_IDR_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0                 MK_ADDR_CONST(0x395c)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_SCR                     CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x3960)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x3964)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x3980)
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x3984)
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE6_IER_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0                 MK_ADDR_CONST(0x3988)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x398c)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x3990)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x3994)
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE6_ISR_0
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0                 MK_ADDR_CONST(0x3998)
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE6_IDR_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0                 MK_ADDR_CONST(0x399c)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_SCR                     CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x39a0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x39a4)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x39c0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x39c4)
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE7_IER_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0                 MK_ADDR_CONST(0x39c8)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x39cc)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x39d0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x39d4)
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE7_ISR_0
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0                 MK_ADDR_CONST(0x39d8)
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE7_IDR_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0                 MK_ADDR_CONST(0x39dc)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_SCR                     CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x39e0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x39e4)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x3a00)
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x3a04)
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE8_IER_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0                 MK_ADDR_CONST(0x3a08)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x3a0c)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x3a10)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x3a14)
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE8_ISR_0
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0                 MK_ADDR_CONST(0x3a18)
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE8_IDR_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0                 MK_ADDR_CONST(0x3a1c)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_SCR                     CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x3a20)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x3a24)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x3a40)
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x3a44)
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE9_IER_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0                 MK_ADDR_CONST(0x3a48)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x3a4c)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x3a50)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_SCR                         CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x3a54)
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_SCR                       CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE9_ISR_0
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0                 MK_ADDR_CONST(0x3a58)
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_SCR                     CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE9_IDR_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0                 MK_ADDR_CONST(0x3a5c)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_SCR                     CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x3a60)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x3a64)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_SCR                         CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x3a80)
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_SCR                   CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x3a84)
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_SCR                   CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE10_IER_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0                        MK_ADDR_CONST(0x3a88)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x3a8c)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_SCR                        CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x3a90)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_SCR                        CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x3a94)
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_SCR                      CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE10_ISR_0
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0                        MK_ADDR_CONST(0x3a98)
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE10_IDR_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0                        MK_ADDR_CONST(0x3a9c)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_SCR                    CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x3aa0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_SCR                        CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x3aa4)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_SCR                        CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x3ac0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_SCR                   CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x3ac4)
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_SCR                   CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE11_IER_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0                        MK_ADDR_CONST(0x3ac8)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x3acc)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_SCR                        CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x3ad0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_SCR                        CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x3ad4)
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_SCR                      CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE11_ISR_0
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0                        MK_ADDR_CONST(0x3ad8)
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE11_IDR_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0                        MK_ADDR_CONST(0x3adc)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_SCR                    CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x3ae0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_SCR                        CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x3ae4)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_SCR                        CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x3b00)
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_SCR                   CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x3b04)
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_SCR                   CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE12_IER_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0                        MK_ADDR_CONST(0x3b08)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x3b0c)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_SCR                        CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x3b10)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_SCR                        CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x3b14)
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_SCR                      CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE12_ISR_0
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0                        MK_ADDR_CONST(0x3b18)
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE12_IDR_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0                        MK_ADDR_CONST(0x3b1c)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_SCR                    CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x3b20)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_SCR                        CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x3b24)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_SCR                        CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x3b40)
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_SCR                   CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x3b44)
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_SCR                   CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE13_IER_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0                        MK_ADDR_CONST(0x3b48)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x3b4c)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_SCR                        CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x3b50)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_SCR                        CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x3b54)
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_SCR                      CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE13_ISR_0
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0                        MK_ADDR_CONST(0x3b58)
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE13_IDR_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0                        MK_ADDR_CONST(0x3b5c)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_SCR                    CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x3b60)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_SCR                        CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x3b64)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_SCR                        CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x3b80)
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_SCR                   CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x3b84)
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_SCR                   CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE14_IER_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0                        MK_ADDR_CONST(0x3b88)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x3b8c)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_SCR                        CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x3b90)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_SCR                        CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x3b94)
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_SCR                      CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE14_ISR_0
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0                        MK_ADDR_CONST(0x3b98)
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE14_IDR_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0                        MK_ADDR_CONST(0x3b9c)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_SCR                    CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x3ba0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_SCR                        CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x3ba4)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_SCR                        CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x3bc0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_SCR                   CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x3bc4)
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_SCR                   CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE15_IER_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0                        MK_ADDR_CONST(0x3bc8)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x3bcc)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_SCR                        CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x3bd0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_SCR                        CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x3bd4)
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_SCR                      CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE15_ISR_0
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0                        MK_ADDR_CONST(0x3bd8)
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE15_IDR_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0                        MK_ADDR_CONST(0x3bdc)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_SCR                    CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x3be0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_SCR                        CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x3be4)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_SCR                        CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x3c00)
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_SCR                   CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x3c04)
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_SCR                   CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE16_IER_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0                        MK_ADDR_CONST(0x3c08)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x3c0c)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_SCR                        CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x3c10)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_SCR                        CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x3c14)
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_SCR                      CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE16_ISR_0
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0                        MK_ADDR_CONST(0x3c18)
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_SCR                    CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE16_IDR_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0                        MK_ADDR_CONST(0x3c1c)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_SCR                    CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x3c20)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_SCR                        CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x3c24)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_SCR                        CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0                  MK_ADDR_CONST(0x3fc0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SCR                      0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0                  MK_ADDR_CONST(0x3fc4)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SCR                      0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x4000)
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x4004)
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE0_IER_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0                 MK_ADDR_CONST(0x4008)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x400c)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x4010)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x4014)
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE0_ISR_0
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0                 MK_ADDR_CONST(0x4018)
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE0_IDR_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0                 MK_ADDR_CONST(0x401c)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_SCR                     CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x4020)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x4024)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x4040)
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x4044)
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE1_IER_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0                 MK_ADDR_CONST(0x4048)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x404c)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x4050)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x4054)
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE1_ISR_0
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0                 MK_ADDR_CONST(0x4058)
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE1_IDR_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0                 MK_ADDR_CONST(0x405c)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_SCR                     CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x4060)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x4064)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x4080)
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x4084)
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE2_IER_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0                 MK_ADDR_CONST(0x4088)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x408c)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x4090)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x4094)
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE2_ISR_0
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0                 MK_ADDR_CONST(0x4098)
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE2_IDR_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0                 MK_ADDR_CONST(0x409c)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_SCR                     CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x40a0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x40a4)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x40c0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x40c4)
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE3_IER_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0                 MK_ADDR_CONST(0x40c8)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x40cc)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x40d0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x40d4)
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE3_ISR_0
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0                 MK_ADDR_CONST(0x40d8)
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE3_IDR_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0                 MK_ADDR_CONST(0x40dc)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_SCR                     CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x40e0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x40e4)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x4100)
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x4104)
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE4_IER_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0                 MK_ADDR_CONST(0x4108)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x410c)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x4110)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x4114)
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE4_ISR_0
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0                 MK_ADDR_CONST(0x4118)
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE4_IDR_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0                 MK_ADDR_CONST(0x411c)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_SCR                     CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x4120)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x4124)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x4140)
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x4144)
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE5_IER_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0                 MK_ADDR_CONST(0x4148)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x414c)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x4150)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x4154)
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE5_ISR_0
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0                 MK_ADDR_CONST(0x4158)
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE5_IDR_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0                 MK_ADDR_CONST(0x415c)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_SCR                     CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x4160)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x4164)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x4180)
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x4184)
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE6_IER_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0                 MK_ADDR_CONST(0x4188)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x418c)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x4190)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x4194)
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE6_ISR_0
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0                 MK_ADDR_CONST(0x4198)
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE6_IDR_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0                 MK_ADDR_CONST(0x419c)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_SCR                     CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x41a0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x41a4)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x41c0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x41c4)
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE7_IER_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0                 MK_ADDR_CONST(0x41c8)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x41cc)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x41d0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x41d4)
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE7_ISR_0
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0                 MK_ADDR_CONST(0x41d8)
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE7_IDR_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0                 MK_ADDR_CONST(0x41dc)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_SCR                     CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x41e0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x41e4)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x4200)
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x4204)
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE8_IER_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0                 MK_ADDR_CONST(0x4208)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x420c)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x4210)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x4214)
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE8_ISR_0
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0                 MK_ADDR_CONST(0x4218)
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE8_IDR_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0                 MK_ADDR_CONST(0x421c)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_SCR                     CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x4220)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x4224)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x4240)
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x4244)
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE9_IER_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0                 MK_ADDR_CONST(0x4248)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x424c)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x4250)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_SCR                         CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x4254)
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_SCR                       CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE9_ISR_0
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0                 MK_ADDR_CONST(0x4258)
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_SCR                     CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE9_IDR_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0                 MK_ADDR_CONST(0x425c)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_SCR                     CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x4260)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x4264)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_SCR                         CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x4280)
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_SCR                   CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x4284)
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_SCR                   CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE10_IER_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0                        MK_ADDR_CONST(0x4288)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x428c)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_SCR                        CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x4290)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_SCR                        CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x4294)
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_SCR                      CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE10_ISR_0
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0                        MK_ADDR_CONST(0x4298)
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE10_IDR_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0                        MK_ADDR_CONST(0x429c)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_SCR                    CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x42a0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_SCR                        CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x42a4)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_SCR                        CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x42c0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_SCR                   CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x42c4)
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_SCR                   CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE11_IER_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0                        MK_ADDR_CONST(0x42c8)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x42cc)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_SCR                        CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x42d0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_SCR                        CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x42d4)
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_SCR                      CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE11_ISR_0
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0                        MK_ADDR_CONST(0x42d8)
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE11_IDR_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0                        MK_ADDR_CONST(0x42dc)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_SCR                    CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x42e0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_SCR                        CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x42e4)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_SCR                        CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x4300)
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_SCR                   CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x4304)
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_SCR                   CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE12_IER_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0                        MK_ADDR_CONST(0x4308)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x430c)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_SCR                        CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x4310)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_SCR                        CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x4314)
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_SCR                      CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE12_ISR_0
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0                        MK_ADDR_CONST(0x4318)
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE12_IDR_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0                        MK_ADDR_CONST(0x431c)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_SCR                    CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x4320)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_SCR                        CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x4324)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_SCR                        CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x4340)
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_SCR                   CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x4344)
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_SCR                   CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE13_IER_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0                        MK_ADDR_CONST(0x4348)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x434c)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_SCR                        CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x4350)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_SCR                        CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x4354)
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_SCR                      CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE13_ISR_0
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0                        MK_ADDR_CONST(0x4358)
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE13_IDR_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0                        MK_ADDR_CONST(0x435c)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_SCR                    CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x4360)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_SCR                        CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x4364)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_SCR                        CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x4380)
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_SCR                   CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x4384)
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_SCR                   CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE14_IER_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0                        MK_ADDR_CONST(0x4388)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x438c)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_SCR                        CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x4390)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_SCR                        CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x4394)
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_SCR                      CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE14_ISR_0
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0                        MK_ADDR_CONST(0x4398)
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE14_IDR_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0                        MK_ADDR_CONST(0x439c)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_SCR                    CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x43a0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_SCR                        CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x43a4)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_SCR                        CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x43c0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_SCR                   CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x43c4)
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_SCR                   CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE15_IER_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0                        MK_ADDR_CONST(0x43c8)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x43cc)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_SCR                        CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x43d0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_SCR                        CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x43d4)
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_SCR                      CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE15_ISR_0
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0                        MK_ADDR_CONST(0x43d8)
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE15_IDR_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0                        MK_ADDR_CONST(0x43dc)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_SCR                    CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x43e0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_SCR                        CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x43e4)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_SCR                        CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x4400)
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_SCR                   CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x4404)
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_SCR                   CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE16_IER_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0                        MK_ADDR_CONST(0x4408)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x440c)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_SCR                        CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x4410)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_SCR                        CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x4414)
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_SCR                      CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE16_ISR_0
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0                        MK_ADDR_CONST(0x4418)
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_SCR                    CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE16_IDR_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0                        MK_ADDR_CONST(0x441c)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_SCR                    CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x4420)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_SCR                        CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x4424)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_SCR                        CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0                  MK_ADDR_CONST(0x47c0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SCR                      0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0                  MK_ADDR_CONST(0x47c4)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SCR                      0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0                        MK_ADDR_CONST(0x4800)
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0                        MK_ADDR_CONST(0x4804)
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE0_IER_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0                 MK_ADDR_CONST(0x4808)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0                     MK_ADDR_CONST(0x480c)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0                     MK_ADDR_CONST(0x4810)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0                   MK_ADDR_CONST(0x4814)
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE0_ISR_0
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0                 MK_ADDR_CONST(0x4818)
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE0_IDR_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0                 MK_ADDR_CONST(0x481c)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_SCR                     CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0                     MK_ADDR_CONST(0x4820)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0                     MK_ADDR_CONST(0x4824)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0                        MK_ADDR_CONST(0x4840)
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0                        MK_ADDR_CONST(0x4844)
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE1_IER_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0                 MK_ADDR_CONST(0x4848)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0                     MK_ADDR_CONST(0x484c)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0                     MK_ADDR_CONST(0x4850)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0                   MK_ADDR_CONST(0x4854)
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE1_ISR_0
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0                 MK_ADDR_CONST(0x4858)
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE1_IDR_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0                 MK_ADDR_CONST(0x485c)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_SCR                     CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0                     MK_ADDR_CONST(0x4860)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0                     MK_ADDR_CONST(0x4864)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0                        MK_ADDR_CONST(0x4880)
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0                        MK_ADDR_CONST(0x4884)
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE2_IER_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0                 MK_ADDR_CONST(0x4888)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0                     MK_ADDR_CONST(0x488c)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0                     MK_ADDR_CONST(0x4890)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0                   MK_ADDR_CONST(0x4894)
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE2_ISR_0
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0                 MK_ADDR_CONST(0x4898)
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE2_IDR_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0                 MK_ADDR_CONST(0x489c)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_SCR                     CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0                     MK_ADDR_CONST(0x48a0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0                     MK_ADDR_CONST(0x48a4)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0                        MK_ADDR_CONST(0x48c0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0                        MK_ADDR_CONST(0x48c4)
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE3_IER_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0                 MK_ADDR_CONST(0x48c8)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0                     MK_ADDR_CONST(0x48cc)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0                     MK_ADDR_CONST(0x48d0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0                   MK_ADDR_CONST(0x48d4)
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE3_ISR_0
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0                 MK_ADDR_CONST(0x48d8)
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE3_IDR_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0                 MK_ADDR_CONST(0x48dc)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_SCR                     CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0                     MK_ADDR_CONST(0x48e0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0                     MK_ADDR_CONST(0x48e4)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0                        MK_ADDR_CONST(0x4900)
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0                        MK_ADDR_CONST(0x4904)
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE4_IER_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0                 MK_ADDR_CONST(0x4908)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0                     MK_ADDR_CONST(0x490c)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0                     MK_ADDR_CONST(0x4910)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0                   MK_ADDR_CONST(0x4914)
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE4_ISR_0
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0                 MK_ADDR_CONST(0x4918)
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE4_IDR_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0                 MK_ADDR_CONST(0x491c)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_SCR                     CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0                     MK_ADDR_CONST(0x4920)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0                     MK_ADDR_CONST(0x4924)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0                        MK_ADDR_CONST(0x4940)
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0                        MK_ADDR_CONST(0x4944)
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE5_IER_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0                 MK_ADDR_CONST(0x4948)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0                     MK_ADDR_CONST(0x494c)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0                     MK_ADDR_CONST(0x4950)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0                   MK_ADDR_CONST(0x4954)
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE5_ISR_0
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0                 MK_ADDR_CONST(0x4958)
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE5_IDR_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0                 MK_ADDR_CONST(0x495c)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_SCR                     CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0                     MK_ADDR_CONST(0x4960)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0                     MK_ADDR_CONST(0x4964)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0                        MK_ADDR_CONST(0x4980)
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0                        MK_ADDR_CONST(0x4984)
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE6_IER_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0                 MK_ADDR_CONST(0x4988)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0                     MK_ADDR_CONST(0x498c)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0                     MK_ADDR_CONST(0x4990)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0                   MK_ADDR_CONST(0x4994)
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE6_ISR_0
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0                 MK_ADDR_CONST(0x4998)
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE6_IDR_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0                 MK_ADDR_CONST(0x499c)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_SCR                     CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0                     MK_ADDR_CONST(0x49a0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0                     MK_ADDR_CONST(0x49a4)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0                        MK_ADDR_CONST(0x49c0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0                        MK_ADDR_CONST(0x49c4)
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE7_IER_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0                 MK_ADDR_CONST(0x49c8)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0                     MK_ADDR_CONST(0x49cc)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0                     MK_ADDR_CONST(0x49d0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0                   MK_ADDR_CONST(0x49d4)
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE7_ISR_0
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0                 MK_ADDR_CONST(0x49d8)
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE7_IDR_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0                 MK_ADDR_CONST(0x49dc)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_SCR                     CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0                     MK_ADDR_CONST(0x49e0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0                     MK_ADDR_CONST(0x49e4)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0                        MK_ADDR_CONST(0x4a00)
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0                        MK_ADDR_CONST(0x4a04)
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE8_IER_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0                 MK_ADDR_CONST(0x4a08)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0                     MK_ADDR_CONST(0x4a0c)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0                     MK_ADDR_CONST(0x4a10)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0                   MK_ADDR_CONST(0x4a14)
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE8_ISR_0
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0                 MK_ADDR_CONST(0x4a18)
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE8_IDR_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0                 MK_ADDR_CONST(0x4a1c)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_SCR                     CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0                     MK_ADDR_CONST(0x4a20)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0                     MK_ADDR_CONST(0x4a24)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0                        MK_ADDR_CONST(0x4a40)
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0                        MK_ADDR_CONST(0x4a44)
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_RESET_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_RANGE                     31:0
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE9_IER_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0                 MK_ADDR_CONST(0x4a48)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0                     MK_ADDR_CONST(0x4a4c)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0                     MK_ADDR_CONST(0x4a50)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_SCR                         CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0                   MK_ADDR_CONST(0x4a54)
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_SCR                       CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_SCRREG                    INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                   31:0
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE9_ISR_0
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0                 MK_ADDR_CONST(0x4a58)
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_SCR                     CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE9_IDR_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0                 MK_ADDR_CONST(0x4a5c)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_SCR                     CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_SCRREG                  INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0                     MK_ADDR_CONST(0x4a60)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0                     MK_ADDR_CONST(0x4a64)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_SCR                         CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_SCRREG                      INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                       31:0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0                       MK_ADDR_CONST(0x4a80)
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_SCR                   CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0                       MK_ADDR_CONST(0x4a84)
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_SCR                   CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE10_IER_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0                        MK_ADDR_CONST(0x4a88)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0                    MK_ADDR_CONST(0x4a8c)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_SCR                        CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0                    MK_ADDR_CONST(0x4a90)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_SCR                        CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0                  MK_ADDR_CONST(0x4a94)
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_SCR                      CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE10_ISR_0
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0                        MK_ADDR_CONST(0x4a98)
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE10_IDR_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0                        MK_ADDR_CONST(0x4a9c)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_SCR                    CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0                    MK_ADDR_CONST(0x4aa0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_SCR                        CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0                    MK_ADDR_CONST(0x4aa4)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_SCR                        CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0                       MK_ADDR_CONST(0x4ac0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_SCR                   CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0                       MK_ADDR_CONST(0x4ac4)
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_SCR                   CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE11_IER_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0                        MK_ADDR_CONST(0x4ac8)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0                    MK_ADDR_CONST(0x4acc)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_SCR                        CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0                    MK_ADDR_CONST(0x4ad0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_SCR                        CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0                  MK_ADDR_CONST(0x4ad4)
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_SCR                      CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE11_ISR_0
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0                        MK_ADDR_CONST(0x4ad8)
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE11_IDR_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0                        MK_ADDR_CONST(0x4adc)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_SCR                    CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0                    MK_ADDR_CONST(0x4ae0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_SCR                        CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0                    MK_ADDR_CONST(0x4ae4)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_SCR                        CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0                       MK_ADDR_CONST(0x4b00)
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_SCR                   CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0                       MK_ADDR_CONST(0x4b04)
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_SCR                   CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE12_IER_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0                        MK_ADDR_CONST(0x4b08)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0                    MK_ADDR_CONST(0x4b0c)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_SCR                        CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0                    MK_ADDR_CONST(0x4b10)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_SCR                        CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0                  MK_ADDR_CONST(0x4b14)
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_SCR                      CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE12_ISR_0
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0                        MK_ADDR_CONST(0x4b18)
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE12_IDR_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0                        MK_ADDR_CONST(0x4b1c)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_SCR                    CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0                    MK_ADDR_CONST(0x4b20)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_SCR                        CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0                    MK_ADDR_CONST(0x4b24)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_SCR                        CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0                       MK_ADDR_CONST(0x4b40)
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_SCR                   CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0                       MK_ADDR_CONST(0x4b44)
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_SCR                   CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE13_IER_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0                        MK_ADDR_CONST(0x4b48)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0                    MK_ADDR_CONST(0x4b4c)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_SCR                        CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0                    MK_ADDR_CONST(0x4b50)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_SCR                        CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0                  MK_ADDR_CONST(0x4b54)
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_SCR                      CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE13_ISR_0
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0                        MK_ADDR_CONST(0x4b58)
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE13_IDR_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0                        MK_ADDR_CONST(0x4b5c)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_SCR                    CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0                    MK_ADDR_CONST(0x4b60)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_SCR                        CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0                    MK_ADDR_CONST(0x4b64)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_SCR                        CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0                       MK_ADDR_CONST(0x4b80)
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_SCR                   CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0                       MK_ADDR_CONST(0x4b84)
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_SCR                   CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE14_IER_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0                        MK_ADDR_CONST(0x4b88)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0                    MK_ADDR_CONST(0x4b8c)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_SCR                        CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0                    MK_ADDR_CONST(0x4b90)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_SCR                        CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0                  MK_ADDR_CONST(0x4b94)
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_SCR                      CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE14_ISR_0
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0                        MK_ADDR_CONST(0x4b98)
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE14_IDR_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0                        MK_ADDR_CONST(0x4b9c)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_SCR                    CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0                    MK_ADDR_CONST(0x4ba0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_SCR                        CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0                    MK_ADDR_CONST(0x4ba4)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_SCR                        CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0                       MK_ADDR_CONST(0x4bc0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_SCR                   CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0                       MK_ADDR_CONST(0x4bc4)
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_SCR                   CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE15_IER_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0                        MK_ADDR_CONST(0x4bc8)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0                    MK_ADDR_CONST(0x4bcc)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_SCR                        CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0                    MK_ADDR_CONST(0x4bd0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_SCR                        CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0                  MK_ADDR_CONST(0x4bd4)
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_SCR                      CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE15_ISR_0
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0                        MK_ADDR_CONST(0x4bd8)
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE15_IDR_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0                        MK_ADDR_CONST(0x4bdc)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_SCR                    CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0                    MK_ADDR_CONST(0x4be0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_SCR                        CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0                    MK_ADDR_CONST(0x4be4)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_SCR                        CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0                       MK_ADDR_CONST(0x4c00)
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_SCR                   CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0                       MK_ADDR_CONST(0x4c04)
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_SCR                   CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE16_IER_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0                        MK_ADDR_CONST(0x4c08)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0                    MK_ADDR_CONST(0x4c0c)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_SCR                        CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0                    MK_ADDR_CONST(0x4c10)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_SCR                        CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0                  MK_ADDR_CONST(0x4c14)
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_SCR                      CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE16_ISR_0
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0                        MK_ADDR_CONST(0x4c18)
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_SCR                    CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE16_IDR_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0                        MK_ADDR_CONST(0x4c1c)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_SCR                    CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_SCRREG                         INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0                    MK_ADDR_CONST(0x4c20)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_SCR                        CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0                    MK_ADDR_CONST(0x4c24)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_SCR                        CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0                  MK_ADDR_CONST(0x4fc0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SCR                      0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0                  MK_ADDR_CONST(0x4fc4)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SCR                      0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SCRREG                   0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_RESET_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_READ_MASK                        MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_WRITE_MASK                       MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_SHIFT                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_RANGE                    29:29
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_MSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_LSB                      MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_SHIFT                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_RANGE                    28:28
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_MSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_LSB                      MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_SHIFT                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_FIELD                    MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_RANGE                    27:27
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_MSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_LSB                      MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_SHIFT                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_FIELD                  MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_RANGE                  26:24
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_MSB                    MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_LSB                    MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_DEFAULT_MASK                   MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_SHIFT                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_RANGE                        23:23
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_MSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_LSB                  MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_SHIFT                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_RANGE                        22:22
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_MSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_LSB                  MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_SHIFT                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_RANGE                        21:21
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_MSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_LSB                  MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_SHIFT                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_RANGE                        20:20
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_MSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_LSB                  MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_SHIFT                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_RANGE                        19:19
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_MSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_LSB                  MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_SHIFT                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_RANGE                        18:18
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_MSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_LSB                  MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_SHIFT                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_RANGE                        17:17
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_MSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_LSB                  MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_SHIFT                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_RANGE                        16:16
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_MSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_LSB                  MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_PR0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_SHIFT                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_RANGE                        15:15
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_MSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_LSB                  MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_SHIFT                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_RANGE                        14:14
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_MSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_LSB                  MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_SHIFT                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_RANGE                        13:13
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_MSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_LSB                  MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_SHIFT                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_RANGE                        12:12
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_MSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_LSB                  MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_SHIFT                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_RANGE                        11:11
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_MSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_LSB                  MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_SHIFT                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_RANGE                        10:10
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_MSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_LSB                  MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_SHIFT                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_RANGE                        9:9
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_MSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_LSB                  MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_SHIFT                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_RANGE                        8:8
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_MSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_LSB                  MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0W_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_SHIFT                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_RANGE                        7:7
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_MSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_LSB                  MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G7R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_SHIFT                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_RANGE                        6:6
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_MSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_LSB                  MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G6R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_SHIFT                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_RANGE                        5:5
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_MSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_LSB                  MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G5R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_SHIFT                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_RANGE                        4:4
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_MSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_LSB                  MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G4R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_SHIFT                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_RANGE                        3:3
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_MSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_LSB                  MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G3R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_SHIFT                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_RANGE                        2:2
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_MSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_LSB                  MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G2R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_SHIFT                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_RANGE                        1:1
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_MSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_LSB                  MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G1R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_FIELD                        MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_RANGE                        0:0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_MSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0_G0R_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0                       MK_ADDR_CONST(0x5000)
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0                       MK_ADDR_CONST(0x5004)
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE0_IER_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0                        MK_ADDR_CONST(0x5008)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0                    MK_ADDR_CONST(0x500c)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0                    MK_ADDR_CONST(0x5010)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0                  MK_ADDR_CONST(0x5014)
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE0_ISR_0
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0                        MK_ADDR_CONST(0x5018)
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE0_IDR_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0                        MK_ADDR_CONST(0x501c)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_SCR                    CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0                    MK_ADDR_CONST(0x5020)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0                    MK_ADDR_CONST(0x5024)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0                       MK_ADDR_CONST(0x5040)
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0                       MK_ADDR_CONST(0x5044)
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE1_IER_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0                        MK_ADDR_CONST(0x5048)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0                    MK_ADDR_CONST(0x504c)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0                    MK_ADDR_CONST(0x5050)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0                  MK_ADDR_CONST(0x5054)
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE1_ISR_0
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0                        MK_ADDR_CONST(0x5058)
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE1_IDR_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0                        MK_ADDR_CONST(0x505c)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_SCR                    CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0                    MK_ADDR_CONST(0x5060)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0                    MK_ADDR_CONST(0x5064)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0                       MK_ADDR_CONST(0x5080)
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0                       MK_ADDR_CONST(0x5084)
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE2_IER_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0                        MK_ADDR_CONST(0x5088)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0                    MK_ADDR_CONST(0x508c)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0                    MK_ADDR_CONST(0x5090)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0                  MK_ADDR_CONST(0x5094)
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE2_ISR_0
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0                        MK_ADDR_CONST(0x5098)
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE2_IDR_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0                        MK_ADDR_CONST(0x509c)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_SCR                    CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0                    MK_ADDR_CONST(0x50a0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0                    MK_ADDR_CONST(0x50a4)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0                       MK_ADDR_CONST(0x50c0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0                       MK_ADDR_CONST(0x50c4)
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE3_IER_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0                        MK_ADDR_CONST(0x50c8)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0                    MK_ADDR_CONST(0x50cc)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0                    MK_ADDR_CONST(0x50d0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0                  MK_ADDR_CONST(0x50d4)
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE3_ISR_0
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0                        MK_ADDR_CONST(0x50d8)
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE3_IDR_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0                        MK_ADDR_CONST(0x50dc)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_SCR                    CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0                    MK_ADDR_CONST(0x50e0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0                    MK_ADDR_CONST(0x50e4)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0                       MK_ADDR_CONST(0x5100)
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0                       MK_ADDR_CONST(0x5104)
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE4_IER_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0                        MK_ADDR_CONST(0x5108)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0                    MK_ADDR_CONST(0x510c)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0                    MK_ADDR_CONST(0x5110)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0                  MK_ADDR_CONST(0x5114)
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE4_ISR_0
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0                        MK_ADDR_CONST(0x5118)
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE4_IDR_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0                        MK_ADDR_CONST(0x511c)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_SCR                    CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0                    MK_ADDR_CONST(0x5120)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0                    MK_ADDR_CONST(0x5124)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0                       MK_ADDR_CONST(0x5140)
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0                       MK_ADDR_CONST(0x5144)
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE5_IER_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0                        MK_ADDR_CONST(0x5148)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0                    MK_ADDR_CONST(0x514c)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0                    MK_ADDR_CONST(0x5150)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0                  MK_ADDR_CONST(0x5154)
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE5_ISR_0
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0                        MK_ADDR_CONST(0x5158)
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE5_IDR_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0                        MK_ADDR_CONST(0x515c)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_SCR                    CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0                    MK_ADDR_CONST(0x5160)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0                    MK_ADDR_CONST(0x5164)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0                       MK_ADDR_CONST(0x5180)
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0                       MK_ADDR_CONST(0x5184)
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE6_IER_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0                        MK_ADDR_CONST(0x5188)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0                    MK_ADDR_CONST(0x518c)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0                    MK_ADDR_CONST(0x5190)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0                  MK_ADDR_CONST(0x5194)
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE6_ISR_0
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0                        MK_ADDR_CONST(0x5198)
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE6_IDR_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0                        MK_ADDR_CONST(0x519c)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_SCR                    CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0                    MK_ADDR_CONST(0x51a0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0                    MK_ADDR_CONST(0x51a4)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0                       MK_ADDR_CONST(0x51c0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0                       MK_ADDR_CONST(0x51c4)
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE7_IER_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0                        MK_ADDR_CONST(0x51c8)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0                    MK_ADDR_CONST(0x51cc)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0                    MK_ADDR_CONST(0x51d0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0                  MK_ADDR_CONST(0x51d4)
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE7_ISR_0
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0                        MK_ADDR_CONST(0x51d8)
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE7_IDR_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0                        MK_ADDR_CONST(0x51dc)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_SCR                    CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0                    MK_ADDR_CONST(0x51e0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0                    MK_ADDR_CONST(0x51e4)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0                       MK_ADDR_CONST(0x5200)
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0                       MK_ADDR_CONST(0x5204)
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE8_IER_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0                        MK_ADDR_CONST(0x5208)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0                    MK_ADDR_CONST(0x520c)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0                    MK_ADDR_CONST(0x5210)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0                  MK_ADDR_CONST(0x5214)
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE8_ISR_0
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0                        MK_ADDR_CONST(0x5218)
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE8_IDR_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0                        MK_ADDR_CONST(0x521c)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_SCR                    CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0                    MK_ADDR_CONST(0x5220)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0                    MK_ADDR_CONST(0x5224)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0                       MK_ADDR_CONST(0x5240)
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0                       MK_ADDR_CONST(0x5244)
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE9_IER_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0                        MK_ADDR_CONST(0x5248)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0                    MK_ADDR_CONST(0x524c)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0                    MK_ADDR_CONST(0x5250)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_SCR                        CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0                  MK_ADDR_CONST(0x5254)
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_SCR                      CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE9_ISR_0
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0                        MK_ADDR_CONST(0x5258)
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_SCR                    CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE9_IDR_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0                        MK_ADDR_CONST(0x525c)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_SCR                    CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_SCRREG                         INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0                    MK_ADDR_CONST(0x5260)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0                    MK_ADDR_CONST(0x5264)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_SCR                        CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0                      MK_ADDR_CONST(0x5280)
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_SCR                  CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0                      MK_ADDR_CONST(0x5284)
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_SCR                  CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE10_IER_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0                       MK_ADDR_CONST(0x5288)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0                   MK_ADDR_CONST(0x528c)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_SCR                       CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0                   MK_ADDR_CONST(0x5290)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_SCR                       CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0                 MK_ADDR_CONST(0x5294)
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_SCR                     CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE10_ISR_0
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0                       MK_ADDR_CONST(0x5298)
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE10_IDR_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0                       MK_ADDR_CONST(0x529c)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_SCR                   CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0                   MK_ADDR_CONST(0x52a0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_SCR                       CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0                   MK_ADDR_CONST(0x52a4)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_SCR                       CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0                      MK_ADDR_CONST(0x52c0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_SCR                  CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0                      MK_ADDR_CONST(0x52c4)
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_SCR                  CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE11_IER_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0                       MK_ADDR_CONST(0x52c8)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0                   MK_ADDR_CONST(0x52cc)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_SCR                       CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0                   MK_ADDR_CONST(0x52d0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_SCR                       CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0                 MK_ADDR_CONST(0x52d4)
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_SCR                     CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE11_ISR_0
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0                       MK_ADDR_CONST(0x52d8)
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE11_IDR_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0                       MK_ADDR_CONST(0x52dc)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_SCR                   CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0                   MK_ADDR_CONST(0x52e0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_SCR                       CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0                   MK_ADDR_CONST(0x52e4)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_SCR                       CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0                      MK_ADDR_CONST(0x5300)
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_SCR                  CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0                      MK_ADDR_CONST(0x5304)
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_SCR                  CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE12_IER_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0                       MK_ADDR_CONST(0x5308)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0                   MK_ADDR_CONST(0x530c)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_SCR                       CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0                   MK_ADDR_CONST(0x5310)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_SCR                       CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0                 MK_ADDR_CONST(0x5314)
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_SCR                     CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE12_ISR_0
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0                       MK_ADDR_CONST(0x5318)
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE12_IDR_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0                       MK_ADDR_CONST(0x531c)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_SCR                   CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0                   MK_ADDR_CONST(0x5320)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_SCR                       CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0                   MK_ADDR_CONST(0x5324)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_SCR                       CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0                      MK_ADDR_CONST(0x5340)
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_SCR                  CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0                      MK_ADDR_CONST(0x5344)
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_SCR                  CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE13_IER_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0                       MK_ADDR_CONST(0x5348)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0                   MK_ADDR_CONST(0x534c)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_SCR                       CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0                   MK_ADDR_CONST(0x5350)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_SCR                       CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0                 MK_ADDR_CONST(0x5354)
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_SCR                     CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE13_ISR_0
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0                       MK_ADDR_CONST(0x5358)
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE13_IDR_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0                       MK_ADDR_CONST(0x535c)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_SCR                   CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0                   MK_ADDR_CONST(0x5360)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_SCR                       CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0                   MK_ADDR_CONST(0x5364)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_SCR                       CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0                      MK_ADDR_CONST(0x5380)
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_SCR                  CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0                      MK_ADDR_CONST(0x5384)
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_SCR                  CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE14_IER_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0                       MK_ADDR_CONST(0x5388)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0                   MK_ADDR_CONST(0x538c)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_SCR                       CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0                   MK_ADDR_CONST(0x5390)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_SCR                       CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0                 MK_ADDR_CONST(0x5394)
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_SCR                     CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE14_ISR_0
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0                       MK_ADDR_CONST(0x5398)
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE14_IDR_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0                       MK_ADDR_CONST(0x539c)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_SCR                   CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0                   MK_ADDR_CONST(0x53a0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_SCR                       CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0                   MK_ADDR_CONST(0x53a4)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_SCR                       CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0                      MK_ADDR_CONST(0x53c0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_SCR                  CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0                      MK_ADDR_CONST(0x53c4)
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_SCR                  CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE15_IER_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0                       MK_ADDR_CONST(0x53c8)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0                   MK_ADDR_CONST(0x53cc)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_SCR                       CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0                   MK_ADDR_CONST(0x53d0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_SCR                       CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0                 MK_ADDR_CONST(0x53d4)
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_SCR                     CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE15_ISR_0
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0                       MK_ADDR_CONST(0x53d8)
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE15_IDR_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0                       MK_ADDR_CONST(0x53dc)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_SCR                   CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0                   MK_ADDR_CONST(0x53e0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_SCR                       CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0                   MK_ADDR_CONST(0x53e4)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_SCR                       CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0                      MK_ADDR_CONST(0x5400)
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_SCR                  CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0                      MK_ADDR_CONST(0x5404)
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_SCR                  CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE16_IER_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0                       MK_ADDR_CONST(0x5408)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0                   MK_ADDR_CONST(0x540c)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_SCR                       CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0                   MK_ADDR_CONST(0x5410)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_SCR                       CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0                 MK_ADDR_CONST(0x5414)
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_SCR                     CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE16_ISR_0
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0                       MK_ADDR_CONST(0x5418)
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_SCR                   CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE16_IDR_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0                       MK_ADDR_CONST(0x541c)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_SCR                   CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_SCRREG                        INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0                   MK_ADDR_CONST(0x5420)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_SCR                       CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0                   MK_ADDR_CONST(0x5424)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_SCR                       CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0                        MK_ADDR_CONST(0x57c0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SCR                    0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SCRREG                         0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_RANGE                  29:29
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_RANGE                  28:28
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_RANGE                  27:27
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_RANGE                        26:24
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_RANGE                      23:23
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_RANGE                      22:22
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_RANGE                      21:21
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_RANGE                      20:20
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_RANGE                      19:19
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_RANGE                      18:18
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_RANGE                      17:17
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_RANGE                      16:16
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_RANGE                      15:15
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_RANGE                      14:14
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_RANGE                      13:13
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_RANGE                      12:12
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_RANGE                      11:11
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_RANGE                      10:10
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_RANGE                      9:9
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_RANGE                      8:8
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_RANGE                      7:7
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_RANGE                      6:6
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_RANGE                      5:5
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_RANGE                      4:4
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_RANGE                      3:3
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_RANGE                      2:2
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_RANGE                      1:1
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_RANGE                      0:0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0                        MK_ADDR_CONST(0x57c4)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SCR                    0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SCRREG                         0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_RANGE                  29:29
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_RANGE                  28:28
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_RANGE                  27:27
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_RANGE                        26:24
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_RANGE                      23:23
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_RANGE                      22:22
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_RANGE                      21:21
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_RANGE                      20:20
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_RANGE                      19:19
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_RANGE                      18:18
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_RANGE                      17:17
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_RANGE                      16:16
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_RANGE                      15:15
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_RANGE                      14:14
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_RANGE                      13:13
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_RANGE                      12:12
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_RANGE                      11:11
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_RANGE                      10:10
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_RANGE                      9:9
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_RANGE                      8:8
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_RANGE                      7:7
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_RANGE                      6:6
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_RANGE                      5:5
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_RANGE                      4:4
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_RANGE                      3:3
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_RANGE                      2:2
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_RANGE                      1:1
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_RANGE                      0:0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0                       MK_ADDR_CONST(0x5800)
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0                       MK_ADDR_CONST(0x5804)
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE0_IER_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0                        MK_ADDR_CONST(0x5808)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0                    MK_ADDR_CONST(0x580c)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0                    MK_ADDR_CONST(0x5810)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0                  MK_ADDR_CONST(0x5814)
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE0_ISR_0
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0                        MK_ADDR_CONST(0x5818)
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE0_IDR_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0                        MK_ADDR_CONST(0x581c)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_SCR                    CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0                    MK_ADDR_CONST(0x5820)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0                    MK_ADDR_CONST(0x5824)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0                       MK_ADDR_CONST(0x5840)
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0                       MK_ADDR_CONST(0x5844)
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE1_IER_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0                        MK_ADDR_CONST(0x5848)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0                    MK_ADDR_CONST(0x584c)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0                    MK_ADDR_CONST(0x5850)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0                  MK_ADDR_CONST(0x5854)
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE1_ISR_0
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0                        MK_ADDR_CONST(0x5858)
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE1_IDR_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0                        MK_ADDR_CONST(0x585c)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_SCR                    CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0                    MK_ADDR_CONST(0x5860)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0                    MK_ADDR_CONST(0x5864)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0                       MK_ADDR_CONST(0x5880)
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0                       MK_ADDR_CONST(0x5884)
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE2_IER_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0                        MK_ADDR_CONST(0x5888)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0                    MK_ADDR_CONST(0x588c)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0                    MK_ADDR_CONST(0x5890)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0                  MK_ADDR_CONST(0x5894)
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE2_ISR_0
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0                        MK_ADDR_CONST(0x5898)
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE2_IDR_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0                        MK_ADDR_CONST(0x589c)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_SCR                    CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0                    MK_ADDR_CONST(0x58a0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0                    MK_ADDR_CONST(0x58a4)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0                       MK_ADDR_CONST(0x58c0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0                       MK_ADDR_CONST(0x58c4)
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE3_IER_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0                        MK_ADDR_CONST(0x58c8)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0                    MK_ADDR_CONST(0x58cc)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0                    MK_ADDR_CONST(0x58d0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0                  MK_ADDR_CONST(0x58d4)
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE3_ISR_0
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0                        MK_ADDR_CONST(0x58d8)
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE3_IDR_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0                        MK_ADDR_CONST(0x58dc)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_SCR                    CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0                    MK_ADDR_CONST(0x58e0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0                    MK_ADDR_CONST(0x58e4)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0                       MK_ADDR_CONST(0x5900)
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0                       MK_ADDR_CONST(0x5904)
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE4_IER_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0                        MK_ADDR_CONST(0x5908)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0                    MK_ADDR_CONST(0x590c)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0                    MK_ADDR_CONST(0x5910)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0                  MK_ADDR_CONST(0x5914)
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE4_ISR_0
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0                        MK_ADDR_CONST(0x5918)
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE4_IDR_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0                        MK_ADDR_CONST(0x591c)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_SCR                    CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0                    MK_ADDR_CONST(0x5920)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0                    MK_ADDR_CONST(0x5924)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0                       MK_ADDR_CONST(0x5940)
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0                       MK_ADDR_CONST(0x5944)
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE5_IER_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0                        MK_ADDR_CONST(0x5948)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0                    MK_ADDR_CONST(0x594c)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0                    MK_ADDR_CONST(0x5950)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0                  MK_ADDR_CONST(0x5954)
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE5_ISR_0
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0                        MK_ADDR_CONST(0x5958)
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE5_IDR_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0                        MK_ADDR_CONST(0x595c)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_SCR                    CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0                    MK_ADDR_CONST(0x5960)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0                    MK_ADDR_CONST(0x5964)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0                       MK_ADDR_CONST(0x5980)
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0                       MK_ADDR_CONST(0x5984)
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE6_IER_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0                        MK_ADDR_CONST(0x5988)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0                    MK_ADDR_CONST(0x598c)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0                    MK_ADDR_CONST(0x5990)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0                  MK_ADDR_CONST(0x5994)
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE6_ISR_0
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0                        MK_ADDR_CONST(0x5998)
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE6_IDR_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0                        MK_ADDR_CONST(0x599c)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_SCR                    CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0                    MK_ADDR_CONST(0x59a0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0                    MK_ADDR_CONST(0x59a4)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0                       MK_ADDR_CONST(0x59c0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0                       MK_ADDR_CONST(0x59c4)
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE7_IER_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0                        MK_ADDR_CONST(0x59c8)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0                    MK_ADDR_CONST(0x59cc)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0                    MK_ADDR_CONST(0x59d0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0                  MK_ADDR_CONST(0x59d4)
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE7_ISR_0
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0                        MK_ADDR_CONST(0x59d8)
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE7_IDR_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0                        MK_ADDR_CONST(0x59dc)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_SCR                    CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0                    MK_ADDR_CONST(0x59e0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0                    MK_ADDR_CONST(0x59e4)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0                       MK_ADDR_CONST(0x5a00)
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0                       MK_ADDR_CONST(0x5a04)
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE8_IER_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0                        MK_ADDR_CONST(0x5a08)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0                    MK_ADDR_CONST(0x5a0c)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0                    MK_ADDR_CONST(0x5a10)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0                  MK_ADDR_CONST(0x5a14)
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE8_ISR_0
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0                        MK_ADDR_CONST(0x5a18)
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE8_IDR_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0                        MK_ADDR_CONST(0x5a1c)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_SCR                    CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0                    MK_ADDR_CONST(0x5a20)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0                    MK_ADDR_CONST(0x5a24)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0                       MK_ADDR_CONST(0x5a40)
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0                       MK_ADDR_CONST(0x5a44)
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_SHIFT                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_FIELD                    MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_RANGE                    31:0
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_MSB                      MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_LSB                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_WOFFSET                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE9_IER_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0                        MK_ADDR_CONST(0x5a48)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_0_IER_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0                    MK_ADDR_CONST(0x5a4c)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0                    MK_ADDR_CONST(0x5a50)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_SCR                        CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0                  MK_ADDR_CONST(0x5a54)
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_SECURE                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_DUAL                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_SCR                      CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_SCRREG                   INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_WORD_COUNT                       0x1
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_FIELD                  MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_RANGE                  31:0
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_MSB                    MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_LSB                    MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE9_ISR_0
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0                        MK_ADDR_CONST(0x5a58)
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_SCR                    CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_ISR_0_ISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE9_IDR_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0                        MK_ADDR_CONST(0x5a5c)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_SCR                    CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_SCRREG                         INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_0_IDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0                    MK_ADDR_CONST(0x5a60)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0                    MK_ADDR_CONST(0x5a64)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_SECURE                     0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_DUAL                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_SCR                        CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_SCRREG                     INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_WORD_COUNT                         0x1
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_RESET_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_RANGE                      31:0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0                      MK_ADDR_CONST(0x5a80)
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_SCR                  CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0                      MK_ADDR_CONST(0x5a84)
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_SCR                  CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE10_IER_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0                       MK_ADDR_CONST(0x5a88)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0                   MK_ADDR_CONST(0x5a8c)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_SCR                       CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0                   MK_ADDR_CONST(0x5a90)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_SCR                       CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0                 MK_ADDR_CONST(0x5a94)
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_SCR                     CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE10_ISR_0
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0                       MK_ADDR_CONST(0x5a98)
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE10_IDR_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0                       MK_ADDR_CONST(0x5a9c)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_SCR                   CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0                   MK_ADDR_CONST(0x5aa0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_SCR                       CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0                   MK_ADDR_CONST(0x5aa4)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_SCR                       CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0                      MK_ADDR_CONST(0x5ac0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_SCR                  CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0                      MK_ADDR_CONST(0x5ac4)
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_SCR                  CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE11_IER_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0                       MK_ADDR_CONST(0x5ac8)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0                   MK_ADDR_CONST(0x5acc)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_SCR                       CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0                   MK_ADDR_CONST(0x5ad0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_SCR                       CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0                 MK_ADDR_CONST(0x5ad4)
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_SCR                     CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE11_ISR_0
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0                       MK_ADDR_CONST(0x5ad8)
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE11_IDR_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0                       MK_ADDR_CONST(0x5adc)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_SCR                   CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0                   MK_ADDR_CONST(0x5ae0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_SCR                       CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0                   MK_ADDR_CONST(0x5ae4)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_SCR                       CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0                      MK_ADDR_CONST(0x5b00)
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_SCR                  CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0                      MK_ADDR_CONST(0x5b04)
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_SCR                  CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE12_IER_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0                       MK_ADDR_CONST(0x5b08)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0                   MK_ADDR_CONST(0x5b0c)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_SCR                       CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0                   MK_ADDR_CONST(0x5b10)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_SCR                       CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0                 MK_ADDR_CONST(0x5b14)
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_SCR                     CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE12_ISR_0
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0                       MK_ADDR_CONST(0x5b18)
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE12_IDR_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0                       MK_ADDR_CONST(0x5b1c)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_SCR                   CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0                   MK_ADDR_CONST(0x5b20)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_SCR                       CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0                   MK_ADDR_CONST(0x5b24)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_SCR                       CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0                      MK_ADDR_CONST(0x5b40)
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_SCR                  CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0                      MK_ADDR_CONST(0x5b44)
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_SCR                  CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE13_IER_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0                       MK_ADDR_CONST(0x5b48)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0                   MK_ADDR_CONST(0x5b4c)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_SCR                       CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0                   MK_ADDR_CONST(0x5b50)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_SCR                       CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0                 MK_ADDR_CONST(0x5b54)
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_SCR                     CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE13_ISR_0
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0                       MK_ADDR_CONST(0x5b58)
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE13_IDR_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0                       MK_ADDR_CONST(0x5b5c)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_SCR                   CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0                   MK_ADDR_CONST(0x5b60)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_SCR                       CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0                   MK_ADDR_CONST(0x5b64)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_SCR                       CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0                      MK_ADDR_CONST(0x5b80)
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_SCR                  CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0                      MK_ADDR_CONST(0x5b84)
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_SCR                  CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE14_IER_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0                       MK_ADDR_CONST(0x5b88)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0                   MK_ADDR_CONST(0x5b8c)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_SCR                       CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0                   MK_ADDR_CONST(0x5b90)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_SCR                       CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0                 MK_ADDR_CONST(0x5b94)
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_SCR                     CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE14_ISR_0
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0                       MK_ADDR_CONST(0x5b98)
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE14_IDR_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0                       MK_ADDR_CONST(0x5b9c)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_SCR                   CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0                   MK_ADDR_CONST(0x5ba0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_SCR                       CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0                   MK_ADDR_CONST(0x5ba4)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_SCR                       CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0                      MK_ADDR_CONST(0x5bc0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_SCR                  CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0                      MK_ADDR_CONST(0x5bc4)
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_SCR                  CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE15_IER_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0                       MK_ADDR_CONST(0x5bc8)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0                   MK_ADDR_CONST(0x5bcc)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_SCR                       CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0                   MK_ADDR_CONST(0x5bd0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_SCR                       CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0                 MK_ADDR_CONST(0x5bd4)
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_SCR                     CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE15_ISR_0
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0                       MK_ADDR_CONST(0x5bd8)
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE15_IDR_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0                       MK_ADDR_CONST(0x5bdc)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_SCR                   CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0                   MK_ADDR_CONST(0x5be0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_SCR                       CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0                   MK_ADDR_CONST(0x5be4)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_SCR                       CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0                      MK_ADDR_CONST(0x5c00)
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_SCR                  CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0_VIRQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0                      MK_ADDR_CONST(0x5c04)
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_SECURE                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_DUAL                         0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_SCR                  CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_SCRREG                       INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_WORD_COUNT                   0x1
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_SHIFT                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_FIELD                   MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_RANGE                   31:0
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_MSB                     MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_LSB                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_WOFFSET                 0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0_VFIQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE16_IER_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0                       MK_ADDR_CONST(0x5c08)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_0_IER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0                   MK_ADDR_CONST(0x5c0c)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_SCR                       CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0_IER_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0                   MK_ADDR_CONST(0x5c10)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_SCR                       CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0_IER_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0                 MK_ADDR_CONST(0x5c14)
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_SECURE                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_DUAL                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_SCR                     CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_SCRREG                  INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_WORD_COUNT                      0x1
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_RANGE                 31:0
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_WOFFSET                       0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0_IEP_CLASS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE16_ISR_0
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0                       MK_ADDR_CONST(0x5c18)
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_SCR                   CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_ISR_0_ISR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE16_IDR_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0                       MK_ADDR_CONST(0x5c1c)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_SECURE                        0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_DUAL                  0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_SCR                   CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_SCRREG                        INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_0_IDR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0                   MK_ADDR_CONST(0x5c20)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_SCR                       CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0_IDR_SET_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0                   MK_ADDR_CONST(0x5c24)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_SECURE                    0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_DUAL                      0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_SCR                       CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_SCRREG                    INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_RESET_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_FIELD                     MK_FIELD_CONST(0xffffffff, INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_SHIFT)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_RANGE                     31:0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_MSB                       MK_SHIFT_CONST(31)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_WOFFSET                   0x0
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0_IDR_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0                        MK_ADDR_CONST(0x5fc0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SCR                    0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SCRREG                         0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_RANGE                  29:29
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_RANGE                  28:28
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_RANGE                  27:27
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_RANGE                        26:24
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_RANGE                      23:23
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_RANGE                      22:22
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_RANGE                      21:21
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_RANGE                      20:20
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_RANGE                      19:19
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_RANGE                      18:18
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_RANGE                      17:17
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_RANGE                      16:16
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_RANGE                      15:15
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_RANGE                      14:14
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_RANGE                      13:13
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_RANGE                      12:12
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_RANGE                      11:11
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_RANGE                      10:10
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_RANGE                      9:9
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_RANGE                      8:8
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_RANGE                      7:7
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_RANGE                      6:6
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_RANGE                      5:5
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_RANGE                      4:4
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_RANGE                      3:3
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_RANGE                      2:2
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_RANGE                      1:1
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_RANGE                      0:0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0                        MK_ADDR_CONST(0x5fc4)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SECURE                         0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_DUAL                   0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SCR                    0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SCRREG                         0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_WORD_COUNT                     0x1
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_RESET_MASK                     MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_READ_MASK                      MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_WRITE_MASK                     MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_SHIFT                  MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_RANGE                  29:29
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_MSB                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_LSB                    MK_SHIFT_CONST(29)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_LCK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_SHIFT                  MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_RANGE                  28:28
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_MSB                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_LSB                    MK_SHIFT_CONST(28)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_WEN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_SHIFT                  MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_FIELD                  MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_RANGE                  27:27
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_MSB                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_LSB                    MK_SHIFT_CONST(27)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_WOFFSET                        0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_REN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_SHIFT                        MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_FIELD                        MK_FIELD_CONST(0x7, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_RANGE                        26:24
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_MSB                  MK_SHIFT_CONST(26)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_LSB                  MK_SHIFT_CONST(24)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_WOFFSET                      0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_SEC_OWNER_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_SHIFT                      MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_RANGE                      23:23
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_MSB                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_LSB                        MK_SHIFT_CONST(23)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR7_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_SHIFT                      MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_RANGE                      22:22
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_MSB                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_LSB                        MK_SHIFT_CONST(22)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR6_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_SHIFT                      MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_RANGE                      21:21
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_MSB                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_LSB                        MK_SHIFT_CONST(21)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR5_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_SHIFT                      MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_RANGE                      20:20
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_MSB                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_LSB                        MK_SHIFT_CONST(20)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_SHIFT                      MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_RANGE                      19:19
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_MSB                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_LSB                        MK_SHIFT_CONST(19)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_SHIFT                      MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_RANGE                      18:18
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_MSB                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_LSB                        MK_SHIFT_CONST(18)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_SHIFT                      MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_RANGE                      17:17
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_MSB                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_LSB                        MK_SHIFT_CONST(17)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_SHIFT                      MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_RANGE                      16:16
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_MSB                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_LSB                        MK_SHIFT_CONST(16)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_PR0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_SHIFT                      MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_RANGE                      15:15
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_MSB                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_LSB                        MK_SHIFT_CONST(15)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_SHIFT                      MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_RANGE                      14:14
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_MSB                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_LSB                        MK_SHIFT_CONST(14)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_SHIFT                      MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_RANGE                      13:13
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_MSB                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_LSB                        MK_SHIFT_CONST(13)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_SHIFT                      MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_RANGE                      12:12
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_MSB                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_LSB                        MK_SHIFT_CONST(12)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_SHIFT                      MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_RANGE                      11:11
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_MSB                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_LSB                        MK_SHIFT_CONST(11)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_SHIFT                      MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_RANGE                      10:10
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_MSB                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_LSB                        MK_SHIFT_CONST(10)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_SHIFT                      MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_RANGE                      9:9
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_MSB                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_LSB                        MK_SHIFT_CONST(9)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_SHIFT                      MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_RANGE                      8:8
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_MSB                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_LSB                        MK_SHIFT_CONST(8)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0W_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_SHIFT                      MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_RANGE                      7:7
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_MSB                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_LSB                        MK_SHIFT_CONST(7)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G7R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_SHIFT                      MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_RANGE                      6:6
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_MSB                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_LSB                        MK_SHIFT_CONST(6)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G6R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_SHIFT                      MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_RANGE                      5:5
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_MSB                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_LSB                        MK_SHIFT_CONST(5)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G5R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_SHIFT                      MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_RANGE                      4:4
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_MSB                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_LSB                        MK_SHIFT_CONST(4)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G4R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_SHIFT                      MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_RANGE                      3:3
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_MSB                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_LSB                        MK_SHIFT_CONST(3)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G3R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_SHIFT                      MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_RANGE                      2:2
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_MSB                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_LSB                        MK_SHIFT_CONST(2)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G2R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_SHIFT                      MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_RANGE                      1:1
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_MSB                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_LSB                        MK_SHIFT_CONST(1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G1R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_FIELD                      MK_FIELD_CONST(0x1, INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_SHIFT)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_RANGE                      0:0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_MSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_WOFFSET                    0x0
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0_G0R_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE0_GISR_0
+#define INTR_CTLR_COMMON_SLICE0_GISR_0                  MK_ADDR_CONST(0xf800)
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE0_FIR_0
+#define INTR_CTLR_COMMON_SLICE0_FIR_0                   MK_ADDR_CONST(0xf804)
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_SECURE                    0x0
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_DUAL                      0x0
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_SCR                       SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE0_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE0_FIR_SET_0
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0                       MK_ADDR_CONST(0xf808)
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE0_FIR_CLR_0
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0                       MK_ADDR_CONST(0xf80c)
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE0_CIDR_0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0                  MK_ADDR_CONST(0xf810)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE0_CIDR_SET_0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0                      MK_ADDR_CONST(0xf814)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0                      MK_ADDR_CONST(0xf818)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE1_GISR_0
+#define INTR_CTLR_COMMON_SLICE1_GISR_0                  MK_ADDR_CONST(0xf840)
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE1_FIR_0
+#define INTR_CTLR_COMMON_SLICE1_FIR_0                   MK_ADDR_CONST(0xf844)
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_SECURE                    0x0
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_DUAL                      0x0
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_SCR                       SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE1_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE1_FIR_SET_0
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0                       MK_ADDR_CONST(0xf848)
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE1_FIR_CLR_0
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0                       MK_ADDR_CONST(0xf84c)
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE1_CIDR_0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0                  MK_ADDR_CONST(0xf850)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE1_CIDR_SET_0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0                      MK_ADDR_CONST(0xf854)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0                      MK_ADDR_CONST(0xf858)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE2_GISR_0
+#define INTR_CTLR_COMMON_SLICE2_GISR_0                  MK_ADDR_CONST(0xf880)
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE2_FIR_0
+#define INTR_CTLR_COMMON_SLICE2_FIR_0                   MK_ADDR_CONST(0xf884)
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_SECURE                    0x0
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_DUAL                      0x0
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_SCR                       SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE2_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE2_FIR_SET_0
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0                       MK_ADDR_CONST(0xf888)
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE2_FIR_CLR_0
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0                       MK_ADDR_CONST(0xf88c)
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE2_CIDR_0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0                  MK_ADDR_CONST(0xf890)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE2_CIDR_SET_0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0                      MK_ADDR_CONST(0xf894)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0                      MK_ADDR_CONST(0xf898)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE3_GISR_0
+#define INTR_CTLR_COMMON_SLICE3_GISR_0                  MK_ADDR_CONST(0xf8c0)
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE3_FIR_0
+#define INTR_CTLR_COMMON_SLICE3_FIR_0                   MK_ADDR_CONST(0xf8c4)
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_SECURE                    0x0
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_DUAL                      0x0
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_SCR                       SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE3_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE3_FIR_SET_0
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0                       MK_ADDR_CONST(0xf8c8)
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE3_FIR_CLR_0
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0                       MK_ADDR_CONST(0xf8cc)
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE3_CIDR_0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0                  MK_ADDR_CONST(0xf8d0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE3_CIDR_SET_0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0                      MK_ADDR_CONST(0xf8d4)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0                      MK_ADDR_CONST(0xf8d8)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE4_GISR_0
+#define INTR_CTLR_COMMON_SLICE4_GISR_0                  MK_ADDR_CONST(0xf900)
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE4_FIR_0
+#define INTR_CTLR_COMMON_SLICE4_FIR_0                   MK_ADDR_CONST(0xf904)
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_SECURE                    0x0
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_DUAL                      0x0
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_SCR                       SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE4_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE4_FIR_SET_0
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0                       MK_ADDR_CONST(0xf908)
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE4_FIR_CLR_0
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0                       MK_ADDR_CONST(0xf90c)
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE4_CIDR_0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0                  MK_ADDR_CONST(0xf910)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE4_CIDR_SET_0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0                      MK_ADDR_CONST(0xf914)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0                      MK_ADDR_CONST(0xf918)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE5_GISR_0
+#define INTR_CTLR_COMMON_SLICE5_GISR_0                  MK_ADDR_CONST(0xf940)
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE5_FIR_0
+#define INTR_CTLR_COMMON_SLICE5_FIR_0                   MK_ADDR_CONST(0xf944)
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_SECURE                    0x0
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_DUAL                      0x0
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_SCR                       SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE5_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE5_FIR_SET_0
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0                       MK_ADDR_CONST(0xf948)
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE5_FIR_CLR_0
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0                       MK_ADDR_CONST(0xf94c)
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE5_CIDR_0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0                  MK_ADDR_CONST(0xf950)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE5_CIDR_SET_0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0                      MK_ADDR_CONST(0xf954)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0                      MK_ADDR_CONST(0xf958)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE6_GISR_0
+#define INTR_CTLR_COMMON_SLICE6_GISR_0                  MK_ADDR_CONST(0xf980)
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE6_FIR_0
+#define INTR_CTLR_COMMON_SLICE6_FIR_0                   MK_ADDR_CONST(0xf984)
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_SECURE                    0x0
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_DUAL                      0x0
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_SCR                       SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE6_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE6_FIR_SET_0
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0                       MK_ADDR_CONST(0xf988)
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE6_FIR_CLR_0
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0                       MK_ADDR_CONST(0xf98c)
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE6_CIDR_0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0                  MK_ADDR_CONST(0xf990)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE6_CIDR_SET_0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0                      MK_ADDR_CONST(0xf994)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0                      MK_ADDR_CONST(0xf998)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE7_GISR_0
+#define INTR_CTLR_COMMON_SLICE7_GISR_0                  MK_ADDR_CONST(0xf9c0)
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE7_FIR_0
+#define INTR_CTLR_COMMON_SLICE7_FIR_0                   MK_ADDR_CONST(0xf9c4)
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_SECURE                    0x0
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_DUAL                      0x0
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_SCR                       SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE7_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE7_FIR_SET_0
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0                       MK_ADDR_CONST(0xf9c8)
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE7_FIR_CLR_0
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0                       MK_ADDR_CONST(0xf9cc)
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE7_CIDR_0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0                  MK_ADDR_CONST(0xf9d0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE7_CIDR_SET_0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0                      MK_ADDR_CONST(0xf9d4)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0                      MK_ADDR_CONST(0xf9d8)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE8_GISR_0
+#define INTR_CTLR_COMMON_SLICE8_GISR_0                  MK_ADDR_CONST(0xfa00)
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE8_FIR_0
+#define INTR_CTLR_COMMON_SLICE8_FIR_0                   MK_ADDR_CONST(0xfa04)
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_SECURE                    0x0
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_DUAL                      0x0
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_SCR                       SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE8_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE8_FIR_SET_0
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0                       MK_ADDR_CONST(0xfa08)
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE8_FIR_CLR_0
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0                       MK_ADDR_CONST(0xfa0c)
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE8_CIDR_0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0                  MK_ADDR_CONST(0xfa10)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE8_CIDR_SET_0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0                      MK_ADDR_CONST(0xfa14)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0                      MK_ADDR_CONST(0xfa18)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE9_GISR_0
+#define INTR_CTLR_COMMON_SLICE9_GISR_0                  MK_ADDR_CONST(0xfa40)
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_RESET_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_GISR_0_GISR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE9_FIR_0
+#define INTR_CTLR_COMMON_SLICE9_FIR_0                   MK_ADDR_CONST(0xfa44)
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_SECURE                    0x0
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_DUAL                      0x0
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_SCR                       SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_SCRREG                    INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_WORD_COUNT                        0x1
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE9_FIR_0_FIR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE9_FIR_SET_0
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0                       MK_ADDR_CONST(0xfa48)
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE9_FIR_CLR_0
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0                       MK_ADDR_CONST(0xfa4c)
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_SCR                   SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_SCRREG                        INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_RESET_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_SHIFT                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_FIELD                 MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_RANGE                 31:0
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_MSB                   MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_LSB                   MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE9_CIDR_0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0                  MK_ADDR_CONST(0xfa50)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_0_CIDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE9_CIDR_SET_0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0                      MK_ADDR_CONST(0xfa54)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0                      MK_ADDR_CONST(0xfa58)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_SHIFT                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_FIELD                       MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_RANGE                       31:0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_MSB                 MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_LSB                 MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE10_GISR_0
+#define INTR_CTLR_COMMON_SLICE10_GISR_0                 MK_ADDR_CONST(0xfa80)
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_SECURE                  0x0
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_DUAL                    0x0
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_SCR                     SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_RESET_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_GISR_0_GISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE10_FIR_0
+#define INTR_CTLR_COMMON_SLICE10_FIR_0                  MK_ADDR_CONST(0xfa84)
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE10_FIR_0_FIR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE10_FIR_SET_0
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0                      MK_ADDR_CONST(0xfa88)
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE10_FIR_CLR_0
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0                      MK_ADDR_CONST(0xfa8c)
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE10_CIDR_0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0                 MK_ADDR_CONST(0xfa90)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_SECURE                  0x0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_DUAL                    0x0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_SCR                     SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_0_CIDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE10_CIDR_SET_0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0                     MK_ADDR_CONST(0xfa94)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_SCR                         SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0                     MK_ADDR_CONST(0xfa98)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_SCR                         SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE11_GISR_0
+#define INTR_CTLR_COMMON_SLICE11_GISR_0                 MK_ADDR_CONST(0xfac0)
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_SECURE                  0x0
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_DUAL                    0x0
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_SCR                     SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_RESET_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_GISR_0_GISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE11_FIR_0
+#define INTR_CTLR_COMMON_SLICE11_FIR_0                  MK_ADDR_CONST(0xfac4)
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE11_FIR_0_FIR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE11_FIR_SET_0
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0                      MK_ADDR_CONST(0xfac8)
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE11_FIR_CLR_0
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0                      MK_ADDR_CONST(0xfacc)
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE11_CIDR_0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0                 MK_ADDR_CONST(0xfad0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_SECURE                  0x0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_DUAL                    0x0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_SCR                     SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_0_CIDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE11_CIDR_SET_0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0                     MK_ADDR_CONST(0xfad4)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_SCR                         SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0                     MK_ADDR_CONST(0xfad8)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_SCR                         SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE12_GISR_0
+#define INTR_CTLR_COMMON_SLICE12_GISR_0                 MK_ADDR_CONST(0xfb00)
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_SECURE                  0x0
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_DUAL                    0x0
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_SCR                     SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_RESET_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_GISR_0_GISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE12_FIR_0
+#define INTR_CTLR_COMMON_SLICE12_FIR_0                  MK_ADDR_CONST(0xfb04)
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE12_FIR_0_FIR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE12_FIR_SET_0
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0                      MK_ADDR_CONST(0xfb08)
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE12_FIR_CLR_0
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0                      MK_ADDR_CONST(0xfb0c)
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE12_CIDR_0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0                 MK_ADDR_CONST(0xfb10)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_SECURE                  0x0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_DUAL                    0x0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_SCR                     SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_0_CIDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE12_CIDR_SET_0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0                     MK_ADDR_CONST(0xfb14)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_SCR                         SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0                     MK_ADDR_CONST(0xfb18)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_SCR                         SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE13_GISR_0
+#define INTR_CTLR_COMMON_SLICE13_GISR_0                 MK_ADDR_CONST(0xfb40)
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_SECURE                  0x0
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_DUAL                    0x0
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_SCR                     SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_RESET_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_GISR_0_GISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE13_FIR_0
+#define INTR_CTLR_COMMON_SLICE13_FIR_0                  MK_ADDR_CONST(0xfb44)
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE13_FIR_0_FIR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE13_FIR_SET_0
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0                      MK_ADDR_CONST(0xfb48)
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE13_FIR_CLR_0
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0                      MK_ADDR_CONST(0xfb4c)
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE13_CIDR_0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0                 MK_ADDR_CONST(0xfb50)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_SECURE                  0x0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_DUAL                    0x0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_SCR                     SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_0_CIDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE13_CIDR_SET_0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0                     MK_ADDR_CONST(0xfb54)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_SCR                         SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0                     MK_ADDR_CONST(0xfb58)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_SCR                         SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE14_GISR_0
+#define INTR_CTLR_COMMON_SLICE14_GISR_0                 MK_ADDR_CONST(0xfb80)
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_SECURE                  0x0
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_DUAL                    0x0
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_SCR                     SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_RESET_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_GISR_0_GISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE14_FIR_0
+#define INTR_CTLR_COMMON_SLICE14_FIR_0                  MK_ADDR_CONST(0xfb84)
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE14_FIR_0_FIR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE14_FIR_SET_0
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0                      MK_ADDR_CONST(0xfb88)
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE14_FIR_CLR_0
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0                      MK_ADDR_CONST(0xfb8c)
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE14_CIDR_0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0                 MK_ADDR_CONST(0xfb90)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_SECURE                  0x0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_DUAL                    0x0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_SCR                     SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_0_CIDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE14_CIDR_SET_0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0                     MK_ADDR_CONST(0xfb94)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_SCR                         SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0                     MK_ADDR_CONST(0xfb98)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_SCR                         SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE15_GISR_0
+#define INTR_CTLR_COMMON_SLICE15_GISR_0                 MK_ADDR_CONST(0xfbc0)
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_SECURE                  0x0
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_DUAL                    0x0
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_SCR                     SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_RESET_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_GISR_0_GISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE15_FIR_0
+#define INTR_CTLR_COMMON_SLICE15_FIR_0                  MK_ADDR_CONST(0xfbc4)
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE15_FIR_0_FIR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE15_FIR_SET_0
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0                      MK_ADDR_CONST(0xfbc8)
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE15_FIR_CLR_0
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0                      MK_ADDR_CONST(0xfbcc)
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE15_CIDR_0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0                 MK_ADDR_CONST(0xfbd0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_SECURE                  0x0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_DUAL                    0x0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_SCR                     SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_0_CIDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE15_CIDR_SET_0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0                     MK_ADDR_CONST(0xfbd4)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_SCR                         SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0                     MK_ADDR_CONST(0xfbd8)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_SCR                         SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE16_GISR_0
+#define INTR_CTLR_COMMON_SLICE16_GISR_0                 MK_ADDR_CONST(0xfc00)
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_SECURE                  0x0
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_DUAL                    0x0
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_SCR                     SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_RESET_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_GISR_0_GISR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE16_FIR_0
+#define INTR_CTLR_COMMON_SLICE16_FIR_0                  MK_ADDR_CONST(0xfc04)
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_SECURE                   0x0
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_DUAL                     0x0
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_SCR                      SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_SCRREG                   INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_WORD_COUNT                       0x1
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE16_FIR_0_FIR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE16_FIR_SET_0
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0                      MK_ADDR_CONST(0xfc08)
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_SET_0_FIR_SET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE16_FIR_CLR_0
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0                      MK_ADDR_CONST(0xfc0c)
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_SECURE                       0x0
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_DUAL                         0x0
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_SCR                  SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_SCRREG                       INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_WORD_COUNT                   0x1
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_RESET_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_SHIFT                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_FIELD                        MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_RANGE                        31:0
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_MSB                  MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_LSB                  MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_WOFFSET                      0x0
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_DEFAULT                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_FIR_CLR_0_FIR_CLR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE16_CIDR_0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0                 MK_ADDR_CONST(0xfc10)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_SECURE                  0x0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_DUAL                    0x0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_SCR                     SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_SCRREG                  INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_WORD_COUNT                      0x1
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_0_CIDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE16_CIDR_SET_0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0                     MK_ADDR_CONST(0xfc14)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_SECURE                      0x0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_DUAL                        0x0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_SCR                         SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_WORD_COUNT                  0x1
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_SHIFT)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_SET_0_CIDR_SET_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0                     MK_ADDR_CONST(0xfc18)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_SECURE                      0x0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_DUAL                        0x0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_SCR                         SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_SCRREG                      INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_WORD_COUNT                  0x1
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_RESET_MASK                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_SHIFT                      MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_FIELD                      MK_FIELD_CONST(0xffffffff, INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_SHIFT)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_RANGE                      31:0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_MSB                        MK_SHIFT_CONST(31)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_LSB                        MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_WOFFSET                    0x0
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0_CIDR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xfc40
+
+// Reserved address 0xfc44
+
+// Reserved address 0xfc48
+
+// Reserved address 0xfc4c
+
+// Reserved address 0xfc50
+
+// Reserved address 0xfc54
+
+// Reserved address 0xfc58
+
+// Reserved address 0xfc5c
+
+// Reserved address 0xfc60
+
+// Reserved address 0xfc64
+
+// Reserved address 0xfc68
+
+// Reserved address 0xfc6c
+
+// Reserved address 0xfc70
+
+// Reserved address 0xfc74
+
+// Reserved address 0xfc78
+
+// Reserved address 0xfc7c
+
+// Reserved address 0xfc80
+
+// Reserved address 0xfc84
+
+// Reserved address 0xfc88
+
+// Reserved address 0xfc8c
+
+// Reserved address 0xfc90
+
+// Reserved address 0xfc94
+
+// Reserved address 0xfc98
+
+// Reserved address 0xfc9c
+
+// Reserved address 0xfca0
+
+// Reserved address 0xfca4
+
+// Reserved address 0xfca8
+
+// Reserved address 0xfcac
+
+// Reserved address 0xfcb0
+
+// Reserved address 0xfcb4
+
+// Reserved address 0xfcb8
+
+// Reserved address 0xfcbc
+
+// Reserved address 0xfcc0
+
+// Reserved address 0xfcc4
+
+// Reserved address 0xfcc8
+
+// Reserved address 0xfccc
+
+// Reserved address 0xfcd0
+
+// Reserved address 0xfcd4
+
+// Reserved address 0xfcd8
+
+// Reserved address 0xfcdc
+
+// Reserved address 0xfce0
+
+// Reserved address 0xfce4
+
+// Reserved address 0xfce8
+
+// Reserved address 0xfcec
+
+// Reserved address 0xfcf0
+
+// Reserved address 0xfcf4
+
+// Reserved address 0xfcf8
+
+// Reserved address 0xfcfc
+
+// Reserved address 0xfd00
+
+// Reserved address 0xfd04
+
+// Reserved address 0xfd08
+
+// Reserved address 0xfd0c
+
+// Reserved address 0xfd10
+
+// Reserved address 0xfd14
+
+// Reserved address 0xfd18
+
+// Reserved address 0xfd1c
+
+// Reserved address 0xfd20
+
+// Reserved address 0xfd24
+
+// Reserved address 0xfd28
+
+// Reserved address 0xfd2c
+
+// Reserved address 0xfd30
+
+// Reserved address 0xfd34
+
+// Reserved address 0xfd38
+
+// Reserved address 0xfd3c
+
+// Reserved address 0xfd40
+
+// Reserved address 0xfd44
+
+// Reserved address 0xfd48
+
+// Reserved address 0xfd4c
+
+// Reserved address 0xfd50
+
+// Reserved address 0xfd54
+
+// Reserved address 0xfd58
+
+// Reserved address 0xfd5c
+
+// Reserved address 0xfd60
+
+// Reserved address 0xfd64
+
+// Reserved address 0xfd68
+
+// Reserved address 0xfd6c
+
+// Reserved address 0xfd70
+
+// Reserved address 0xfd74
+
+// Reserved address 0xfd78
+
+// Reserved address 0xfd7c
+
+// Reserved address 0xfd80
+
+// Reserved address 0xfd84
+
+// Reserved address 0xfd88
+
+// Reserved address 0xfd8c
+
+// Reserved address 0xfd90
+
+// Reserved address 0xfd94
+
+// Reserved address 0xfd98
+
+// Reserved address 0xfd9c
+
+// Reserved address 0xfda0
+
+// Reserved address 0xfda4
+
+// Reserved address 0xfda8
+
+// Reserved address 0xfdac
+
+// Reserved address 0xfdb0
+
+// Reserved address 0xfdb4
+
+// Reserved address 0xfdb8
+
+// Reserved address 0xfdbc
+
+// Reserved address 0xfdc0
+
+// Reserved address 0xfdc4
+
+// Reserved address 0xfdc8
+
+// Reserved address 0xfdcc
+
+// Reserved address 0xfdd0
+
+// Reserved address 0xfdd4
+
+// Reserved address 0xfdd8
+
+// Reserved address 0xfddc
+
+// Reserved address 0xfde0
+
+// Reserved address 0xfde4
+
+// Reserved address 0xfde8
+
+// Reserved address 0xfdec
+
+// Reserved address 0xfdf0
+
+// Reserved address 0xfdf4
+
+// Reserved address 0xfdf8
+
+// Reserved address 0xfdfc
+
+// Reserved address 0xfe00
+
+// Reserved address 0xfe04
+
+// Reserved address 0xfe08
+
+// Reserved address 0xfe0c
+
+// Reserved address 0xfe10
+
+// Reserved address 0xfe14
+
+// Reserved address 0xfe18
+
+// Reserved address 0xfe1c
+
+// Reserved address 0xfe20
+
+// Reserved address 0xfe24
+
+// Reserved address 0xfe28
+
+// Reserved address 0xfe2c
+
+// Reserved address 0xfe30
+
+// Reserved address 0xfe34
+
+// Reserved address 0xfe38
+
+// Reserved address 0xfe3c
+
+// Reserved address 0xfe40
+
+// Reserved address 0xfe44
+
+// Reserved address 0xfe48
+
+// Reserved address 0xfe4c
+
+// Reserved address 0xfe50
+
+// Reserved address 0xfe54
+
+// Reserved address 0xfe58
+
+// Reserved address 0xfe5c
+
+// Reserved address 0xfe60
+
+// Reserved address 0xfe64
+
+// Reserved address 0xfe68
+
+// Reserved address 0xfe6c
+
+// Reserved address 0xfe70
+
+// Reserved address 0xfe74
+
+// Reserved address 0xfe78
+
+// Reserved address 0xfe7c
+
+// Reserved address 0xfe80
+
+// Reserved address 0xfe84
+
+// Reserved address 0xfe88
+
+// Reserved address 0xfe8c
+
+// Reserved address 0xfe90
+
+// Reserved address 0xfe94
+
+// Reserved address 0xfe98
+
+// Reserved address 0xfe9c
+
+// Reserved address 0xfea0
+
+// Reserved address 0xfea4
+
+// Reserved address 0xfea8
+
+// Reserved address 0xfeac
+
+// Reserved address 0xfeb0
+
+// Reserved address 0xfeb4
+
+// Reserved address 0xfeb8
+
+// Reserved address 0xfebc
+
+// Reserved address 0xfec0
+
+// Reserved address 0xfec4
+
+// Reserved address 0xfec8
+
+// Reserved address 0xfecc
+
+// Reserved address 0xfed0
+
+// Reserved address 0xfed4
+
+// Reserved address 0xfed8
+
+// Reserved address 0xfedc
+
+// Reserved address 0xfee0
+
+// Reserved address 0xfee4
+
+// Reserved address 0xfee8
+
+// Reserved address 0xfeec
+
+// Reserved address 0xfef0
+
+// Reserved address 0xfef4
+
+// Reserved address 0xfef8
+
+// Reserved address 0xfefc
+
+// Reserved address 0xff00
+
+// Reserved address 0xff04
+
+// Reserved address 0xff08
+
+// Reserved address 0xff0c
+
+// Reserved address 0xff10
+
+// Reserved address 0xff14
+
+// Reserved address 0xff18
+
+// Reserved address 0xff1c
+
+// Reserved address 0xff20
+
+// Reserved address 0xff24
+
+// Reserved address 0xff28
+
+// Reserved address 0xff2c
+
+// Reserved address 0xff30
+
+// Reserved address 0xff34
+
+// Reserved address 0xff38
+
+// Reserved address 0xff3c
+
+// Reserved address 0xff40
+
+// Reserved address 0xff44
+
+// Reserved address 0xff48
+
+// Reserved address 0xff4c
+
+// Reserved address 0xff50
+
+// Reserved address 0xff54
+
+// Reserved address 0xff58
+
+// Reserved address 0xff5c
+
+// Reserved address 0xff60
+
+// Reserved address 0xff64
+
+// Reserved address 0xff68
+
+// Reserved address 0xff6c
+
+// Reserved address 0xff70
+
+// Reserved address 0xff74
+
+// Reserved address 0xff78
+
+// Reserved address 0xff7c
+
+// Reserved address 0xff80
+
+// Reserved address 0xff84
+
+// Reserved address 0xff88
+
+// Reserved address 0xff8c
+
+// Reserved address 0xff90
+
+// Reserved address 0xff94
+
+// Reserved address 0xff98
+
+// Reserved address 0xff9c
+
+// Reserved address 0xffa0
+
+// Reserved address 0xffa4
+
+// Reserved address 0xffa8
+
+// Reserved address 0xffac
+
+// Reserved address 0xffb0
+
+// Reserved address 0xffb4
+
+// Reserved address 0xffb8
+
+// Reserved address 0xffbc
+
+// Reserved address 0xffc0
+
+// Register INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0                       MK_ADDR_CONST(0xffc4)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SECURE                        0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_DUAL                  0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SCR                   0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SCRREG                        0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_WORD_COUNT                    0x1
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_RESET_MASK                    MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_READ_MASK                     MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_WRITE_MASK                    MK_MASK_CONST(0x3fffffff)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_SHIFT                 MK_SHIFT_CONST(29)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_FIELD                 MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_RANGE                 29:29
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_MSB                   MK_SHIFT_CONST(29)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_LSB                   MK_SHIFT_CONST(29)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_LCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_SHIFT                 MK_SHIFT_CONST(28)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_FIELD                 MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_RANGE                 28:28
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_MSB                   MK_SHIFT_CONST(28)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_LSB                   MK_SHIFT_CONST(28)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_WEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_SHIFT                 MK_SHIFT_CONST(27)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_FIELD                 MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_RANGE                 27:27
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_MSB                   MK_SHIFT_CONST(27)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_LSB                   MK_SHIFT_CONST(27)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_WOFFSET                       0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_DEFAULT                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_REN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_SHIFT                       MK_SHIFT_CONST(24)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_FIELD                       MK_FIELD_CONST(0x7, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_RANGE                       26:24
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_MSB                 MK_SHIFT_CONST(26)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_LSB                 MK_SHIFT_CONST(24)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_WOFFSET                     0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_DEFAULT                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_SEC_OWNER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_SHIFT                     MK_SHIFT_CONST(23)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_RANGE                     23:23
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_MSB                       MK_SHIFT_CONST(23)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_LSB                       MK_SHIFT_CONST(23)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR7_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_SHIFT                     MK_SHIFT_CONST(22)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_RANGE                     22:22
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_MSB                       MK_SHIFT_CONST(22)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_LSB                       MK_SHIFT_CONST(22)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_SHIFT                     MK_SHIFT_CONST(21)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_RANGE                     21:21
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_MSB                       MK_SHIFT_CONST(21)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_LSB                       MK_SHIFT_CONST(21)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_SHIFT                     MK_SHIFT_CONST(20)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_RANGE                     20:20
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_MSB                       MK_SHIFT_CONST(20)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_LSB                       MK_SHIFT_CONST(20)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_SHIFT                     MK_SHIFT_CONST(19)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_RANGE                     19:19
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_MSB                       MK_SHIFT_CONST(19)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_LSB                       MK_SHIFT_CONST(19)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_SHIFT                     MK_SHIFT_CONST(18)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_RANGE                     18:18
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_MSB                       MK_SHIFT_CONST(18)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_LSB                       MK_SHIFT_CONST(18)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_SHIFT                     MK_SHIFT_CONST(17)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_RANGE                     17:17
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_MSB                       MK_SHIFT_CONST(17)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_LSB                       MK_SHIFT_CONST(17)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_SHIFT                     MK_SHIFT_CONST(16)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_RANGE                     16:16
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_MSB                       MK_SHIFT_CONST(16)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_LSB                       MK_SHIFT_CONST(16)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_PR0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_SHIFT                     MK_SHIFT_CONST(15)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_RANGE                     15:15
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_MSB                       MK_SHIFT_CONST(15)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_LSB                       MK_SHIFT_CONST(15)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_SHIFT                     MK_SHIFT_CONST(14)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_RANGE                     14:14
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_MSB                       MK_SHIFT_CONST(14)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_LSB                       MK_SHIFT_CONST(14)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_SHIFT                     MK_SHIFT_CONST(13)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_RANGE                     13:13
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_MSB                       MK_SHIFT_CONST(13)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_LSB                       MK_SHIFT_CONST(13)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_SHIFT                     MK_SHIFT_CONST(12)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_RANGE                     12:12
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_MSB                       MK_SHIFT_CONST(12)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_LSB                       MK_SHIFT_CONST(12)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_SHIFT                     MK_SHIFT_CONST(11)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_RANGE                     11:11
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_MSB                       MK_SHIFT_CONST(11)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_LSB                       MK_SHIFT_CONST(11)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_SHIFT                     MK_SHIFT_CONST(10)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_RANGE                     10:10
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_MSB                       MK_SHIFT_CONST(10)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_LSB                       MK_SHIFT_CONST(10)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_SHIFT                     MK_SHIFT_CONST(9)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_RANGE                     9:9
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_MSB                       MK_SHIFT_CONST(9)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_LSB                       MK_SHIFT_CONST(9)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_SHIFT                     MK_SHIFT_CONST(8)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_RANGE                     8:8
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_MSB                       MK_SHIFT_CONST(8)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_LSB                       MK_SHIFT_CONST(8)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0W_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_SHIFT                     MK_SHIFT_CONST(7)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_RANGE                     7:7
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_MSB                       MK_SHIFT_CONST(7)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_LSB                       MK_SHIFT_CONST(7)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G7R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_SHIFT                     MK_SHIFT_CONST(6)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_RANGE                     6:6
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_MSB                       MK_SHIFT_CONST(6)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_LSB                       MK_SHIFT_CONST(6)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G6R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_SHIFT                     MK_SHIFT_CONST(5)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_RANGE                     5:5
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_MSB                       MK_SHIFT_CONST(5)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_LSB                       MK_SHIFT_CONST(5)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G5R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_SHIFT                     MK_SHIFT_CONST(4)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_RANGE                     4:4
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_MSB                       MK_SHIFT_CONST(4)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_LSB                       MK_SHIFT_CONST(4)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G4R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_SHIFT                     MK_SHIFT_CONST(3)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_RANGE                     3:3
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_MSB                       MK_SHIFT_CONST(3)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_LSB                       MK_SHIFT_CONST(3)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G3R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_SHIFT                     MK_SHIFT_CONST(2)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_RANGE                     2:2
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_MSB                       MK_SHIFT_CONST(2)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_LSB                       MK_SHIFT_CONST(2)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G2R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_SHIFT                     MK_SHIFT_CONST(1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_RANGE                     1:1
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_MSB                       MK_SHIFT_CONST(1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_LSB                       MK_SHIFT_CONST(1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G1R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_SHIFT                     MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_FIELD                     MK_FIELD_CONST(0x1, INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_SHIFT)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_RANGE                     0:0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_MSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_LSB                       MK_SHIFT_CONST(0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_WOFFSET                   0x0
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_DEFAULT                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define INTR_CTLR_COMMON_SCR_SCR_COMMON_0_G0R_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Packet SLICE0_ICTLR_FIELDS_0
+#define SLICE0_ICTLR_FIELDS_0_SIZE 32
+
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_0_SHIFT                    MK_SHIFT_CONST(0)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_0_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_0_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_0_RANGE                    MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_0_ROW                      0
+
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_1_SHIFT                    MK_SHIFT_CONST(1)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_1_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_1_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_1_RANGE                    MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_1_ROW                      0
+
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_2_SHIFT                    MK_SHIFT_CONST(2)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_2_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_2_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_2_RANGE                    MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_2_ROW                      0
+
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_3_SHIFT                    MK_SHIFT_CONST(3)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_3_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_3_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_3_RANGE                    MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_3_ROW                      0
+
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_4_SHIFT                    MK_SHIFT_CONST(4)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_4_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_4_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_4_RANGE                    MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_4_ROW                      0
+
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_5_SHIFT                    MK_SHIFT_CONST(5)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_5_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_5_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_5_RANGE                    MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_5_ROW                      0
+
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_6_SHIFT                    MK_SHIFT_CONST(6)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_6_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_6_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_6_RANGE                    MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_6_ROW                      0
+
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_7_SHIFT                    MK_SHIFT_CONST(7)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_7_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_7_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_7_RANGE                    MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_7_ROW                      0
+
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_8_SHIFT                    MK_SHIFT_CONST(8)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_8_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_8_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_8_RANGE                    MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_8_ROW                      0
+
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_9_SHIFT                    MK_SHIFT_CONST(9)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_9_FIELD                    MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_9_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_9_RANGE                    MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
+#define SLICE0_ICTLR_FIELDS_0_TOP_TKE_SHARED_9_ROW                      0
+
+#define SLICE0_ICTLR_FIELDS_0_RTC_SHIFT                 MK_SHIFT_CONST(10)
+#define SLICE0_ICTLR_FIELDS_0_RTC_FIELD                 MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_RTC_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_RTC_RANGE                 MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define SLICE0_ICTLR_FIELDS_0_RTC_ROW                   0
+
+#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_0_SHIFT                   MK_SHIFT_CONST(11)
+#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_0_FIELD                   MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_LIC_GTE_0_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_0_RANGE                   MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
+#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_0_ROW                     0
+
+#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_1_SHIFT                   MK_SHIFT_CONST(12)
+#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_1_FIELD                   MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_LIC_GTE_1_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_1_RANGE                   MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
+#define SLICE0_ICTLR_FIELDS_0_LIC_GTE_1_ROW                     0
+
+#define SLICE0_ICTLR_FIELDS_0_AON_GTE_SHIFT                     MK_SHIFT_CONST(13)
+#define SLICE0_ICTLR_FIELDS_0_AON_GTE_FIELD                     MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_AON_GTE_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_AON_GTE_RANGE                     MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
+#define SLICE0_ICTLR_FIELDS_0_AON_GTE_ROW                       0
+
+#define SLICE0_ICTLR_FIELDS_0_BPMP_WDT_REMOTE_SHIFT                     MK_SHIFT_CONST(14)
+#define SLICE0_ICTLR_FIELDS_0_BPMP_WDT_REMOTE_FIELD                     MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_BPMP_WDT_REMOTE_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_BPMP_WDT_REMOTE_RANGE                     MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
+#define SLICE0_ICTLR_FIELDS_0_BPMP_WDT_REMOTE_ROW                       0
+
+#define SLICE0_ICTLR_FIELDS_0_SPE_WDT_REMOTE_SHIFT                      MK_SHIFT_CONST(15)
+#define SLICE0_ICTLR_FIELDS_0_SPE_WDT_REMOTE_FIELD                      MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_SPE_WDT_REMOTE_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_SPE_WDT_REMOTE_RANGE                      MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define SLICE0_ICTLR_FIELDS_0_SPE_WDT_REMOTE_ROW                        0
+
+#define SLICE0_ICTLR_FIELDS_0_SCE_WDT_REMOTE_SHIFT                      MK_SHIFT_CONST(16)
+#define SLICE0_ICTLR_FIELDS_0_SCE_WDT_REMOTE_FIELD                      MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_SCE_WDT_REMOTE_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_SCE_WDT_REMOTE_RANGE                      MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define SLICE0_ICTLR_FIELDS_0_SCE_WDT_REMOTE_ROW                        0
+
+#define SLICE0_ICTLR_FIELDS_0_TOP_WDT_REMOTE_SHIFT                      MK_SHIFT_CONST(17)
+#define SLICE0_ICTLR_FIELDS_0_TOP_WDT_REMOTE_FIELD                      MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_TOP_WDT_REMOTE_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_TOP_WDT_REMOTE_RANGE                      MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define SLICE0_ICTLR_FIELDS_0_TOP_WDT_REMOTE_ROW                        0
+
+#define SLICE0_ICTLR_FIELDS_0_AOWDT_REMOTE_SHIFT                        MK_SHIFT_CONST(18)
+#define SLICE0_ICTLR_FIELDS_0_AOWDT_REMOTE_FIELD                        MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_AOWDT_REMOTE_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_AOWDT_REMOTE_RANGE                        MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define SLICE0_ICTLR_FIELDS_0_AOWDT_REMOTE_ROW                  0
+
+#define SLICE0_ICTLR_FIELDS_0_RCE_WDT_REMOTE_SHIFT                      MK_SHIFT_CONST(19)
+#define SLICE0_ICTLR_FIELDS_0_RCE_WDT_REMOTE_FIELD                      MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_RCE_WDT_REMOTE_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_RCE_WDT_REMOTE_RANGE                      MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define SLICE0_ICTLR_FIELDS_0_RCE_WDT_REMOTE_ROW                        0
+
+#define SLICE0_ICTLR_FIELDS_0_APE_WDT_REMOTE_SHIFT                      MK_SHIFT_CONST(20)
+#define SLICE0_ICTLR_FIELDS_0_APE_WDT_REMOTE_FIELD                      MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_APE_WDT_REMOTE_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_APE_WDT_REMOTE_RANGE                      MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define SLICE0_ICTLR_FIELDS_0_APE_WDT_REMOTE_ROW                        0
+
+#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF0_SHIFT                       MK_SHIFT_CONST(21)
+#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF0_FIELD                       MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF0_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF0_RANGE                       MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF0_ROW                 0
+
+#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF1_SHIFT                       MK_SHIFT_CONST(22)
+#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF1_FIELD                       MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF1_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF1_RANGE                       MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF1_ROW                 0
+
+#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF2_SHIFT                       MK_SHIFT_CONST(23)
+#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF2_FIELD                       MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF2_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF2_RANGE                       MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF2_ROW                 0
+
+#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF3_SHIFT                       MK_SHIFT_CONST(24)
+#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF3_FIELD                       MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF3_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF3_RANGE                       MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define SLICE0_ICTLR_FIELDS_0_USB3_HOST_VF3_ROW                 0
+
+#define SLICE0_ICTLR_FIELDS_0_I2C_SHIFT                 MK_SHIFT_CONST(25)
+#define SLICE0_ICTLR_FIELDS_0_I2C_FIELD                 MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_I2C_RANGE                 MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define SLICE0_ICTLR_FIELDS_0_I2C_ROW                   0
+
+#define SLICE0_ICTLR_FIELDS_0_I2C2_SHIFT                        MK_SHIFT_CONST(26)
+#define SLICE0_ICTLR_FIELDS_0_I2C2_FIELD                        MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C2_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_I2C2_RANGE                        MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define SLICE0_ICTLR_FIELDS_0_I2C2_ROW                  0
+
+#define SLICE0_ICTLR_FIELDS_0_I2C3_SHIFT                        MK_SHIFT_CONST(27)
+#define SLICE0_ICTLR_FIELDS_0_I2C3_FIELD                        MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C3_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_I2C3_RANGE                        MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define SLICE0_ICTLR_FIELDS_0_I2C3_ROW                  0
+
+#define SLICE0_ICTLR_FIELDS_0_I2C4_SHIFT                        MK_SHIFT_CONST(28)
+#define SLICE0_ICTLR_FIELDS_0_I2C4_FIELD                        MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C4_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_I2C4_RANGE                        MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define SLICE0_ICTLR_FIELDS_0_I2C4_ROW                  0
+
+#define SLICE0_ICTLR_FIELDS_0_I2C5_SHIFT                        MK_SHIFT_CONST(29)
+#define SLICE0_ICTLR_FIELDS_0_I2C5_FIELD                        MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C5_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_I2C5_RANGE                        MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
+#define SLICE0_ICTLR_FIELDS_0_I2C5_ROW                  0
+
+#define SLICE0_ICTLR_FIELDS_0_I2C6_SHIFT                        MK_SHIFT_CONST(30)
+#define SLICE0_ICTLR_FIELDS_0_I2C6_FIELD                        MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C6_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_I2C6_RANGE                        MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
+#define SLICE0_ICTLR_FIELDS_0_I2C6_ROW                  0
+
+#define SLICE0_ICTLR_FIELDS_0_I2C7_SHIFT                        MK_SHIFT_CONST(31)
+#define SLICE0_ICTLR_FIELDS_0_I2C7_FIELD                        MK_FIELD_CONST(0x1, SLICE0_ICTLR_FIELDS_0_I2C7_SHIFT)
+#define SLICE0_ICTLR_FIELDS_0_I2C7_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
+#define SLICE0_ICTLR_FIELDS_0_I2C7_ROW                  0
+
+
+// Packet SLICE1_ICTLR_FIELDS_0
+#define SLICE1_ICTLR_FIELDS_0_SIZE 32
+
+#define SLICE1_ICTLR_FIELDS_0_I2C8_SHIFT                        MK_SHIFT_CONST(0)
+#define SLICE1_ICTLR_FIELDS_0_I2C8_FIELD                        MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_I2C8_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_I2C8_RANGE                        MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define SLICE1_ICTLR_FIELDS_0_I2C8_ROW                  0
+
+#define SLICE1_ICTLR_FIELDS_0_I2C9_SHIFT                        MK_SHIFT_CONST(1)
+#define SLICE1_ICTLR_FIELDS_0_I2C9_FIELD                        MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_I2C9_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_I2C9_RANGE                        MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define SLICE1_ICTLR_FIELDS_0_I2C9_ROW                  0
+
+#define SLICE1_ICTLR_FIELDS_0_RESERVED_34_SHIFT                 MK_SHIFT_CONST(2)
+#define SLICE1_ICTLR_FIELDS_0_RESERVED_34_FIELD                 MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_RESERVED_34_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_RESERVED_34_RANGE                 MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
+#define SLICE1_ICTLR_FIELDS_0_RESERVED_34_ROW                   0
+
+#define SLICE1_ICTLR_FIELDS_0_QSPI0_SHIFT                       MK_SHIFT_CONST(3)
+#define SLICE1_ICTLR_FIELDS_0_QSPI0_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_QSPI0_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_QSPI0_RANGE                       MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define SLICE1_ICTLR_FIELDS_0_QSPI0_ROW                 0
+
+#define SLICE1_ICTLR_FIELDS_0_SPI1_SHIFT                        MK_SHIFT_CONST(4)
+#define SLICE1_ICTLR_FIELDS_0_SPI1_FIELD                        MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_SPI1_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_SPI1_RANGE                        MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define SLICE1_ICTLR_FIELDS_0_SPI1_ROW                  0
+
+#define SLICE1_ICTLR_FIELDS_0_SPI2_SHIFT                        MK_SHIFT_CONST(5)
+#define SLICE1_ICTLR_FIELDS_0_SPI2_FIELD                        MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_SPI2_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_SPI2_RANGE                        MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define SLICE1_ICTLR_FIELDS_0_SPI2_ROW                  0
+
+#define SLICE1_ICTLR_FIELDS_0_SPI3_SHIFT                        MK_SHIFT_CONST(6)
+#define SLICE1_ICTLR_FIELDS_0_SPI3_FIELD                        MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_SPI3_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_SPI3_RANGE                        MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define SLICE1_ICTLR_FIELDS_0_SPI3_ROW                  0
+
+#define SLICE1_ICTLR_FIELDS_0_QSPI1_SHIFT                       MK_SHIFT_CONST(7)
+#define SLICE1_ICTLR_FIELDS_0_QSPI1_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_QSPI1_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_QSPI1_RANGE                       MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define SLICE1_ICTLR_FIELDS_0_QSPI1_ROW                 0
+
+#define SLICE1_ICTLR_FIELDS_0_CAN1_0_SHIFT                      MK_SHIFT_CONST(8)
+#define SLICE1_ICTLR_FIELDS_0_CAN1_0_FIELD                      MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_CAN1_0_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_CAN1_0_RANGE                      MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
+#define SLICE1_ICTLR_FIELDS_0_CAN1_0_ROW                        0
+
+#define SLICE1_ICTLR_FIELDS_0_CAN1_1_SHIFT                      MK_SHIFT_CONST(9)
+#define SLICE1_ICTLR_FIELDS_0_CAN1_1_FIELD                      MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_CAN1_1_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_CAN1_1_RANGE                      MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
+#define SLICE1_ICTLR_FIELDS_0_CAN1_1_ROW                        0
+
+#define SLICE1_ICTLR_FIELDS_0_CAN2_0_SHIFT                      MK_SHIFT_CONST(10)
+#define SLICE1_ICTLR_FIELDS_0_CAN2_0_FIELD                      MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_CAN2_0_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_CAN2_0_RANGE                      MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define SLICE1_ICTLR_FIELDS_0_CAN2_0_ROW                        0
+
+#define SLICE1_ICTLR_FIELDS_0_CAN2_1_SHIFT                      MK_SHIFT_CONST(11)
+#define SLICE1_ICTLR_FIELDS_0_CAN2_1_FIELD                      MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_CAN2_1_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_CAN2_1_RANGE                      MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
+#define SLICE1_ICTLR_FIELDS_0_CAN2_1_ROW                        0
+
+#define SLICE1_ICTLR_FIELDS_0_UFSHC_C0_SHIFT                    MK_SHIFT_CONST(12)
+#define SLICE1_ICTLR_FIELDS_0_UFSHC_C0_FIELD                    MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_UFSHC_C0_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_UFSHC_C0_RANGE                    MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
+#define SLICE1_ICTLR_FIELDS_0_UFSHC_C0_ROW                      0
+
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_0_SHIFT                       MK_SHIFT_CONST(13)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_0_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_0_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_0_RANGE                       MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_0_ROW                 0
+
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_1_SHIFT                       MK_SHIFT_CONST(14)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_1_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_1_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_1_RANGE                       MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C1_SYS_1_ROW                 0
+
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_0_SHIFT                       MK_SHIFT_CONST(15)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_0_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_0_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_0_RANGE                       MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_0_ROW                 0
+
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_1_SHIFT                       MK_SHIFT_CONST(16)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_1_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_1_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_1_RANGE                       MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C2_SYS_1_ROW                 0
+
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_0_SHIFT                       MK_SHIFT_CONST(17)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_0_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_0_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_0_RANGE                       MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_0_ROW                 0
+
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_1_SHIFT                       MK_SHIFT_CONST(18)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_1_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_1_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_1_RANGE                       MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C3_SYS_1_ROW                 0
+
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_0_SHIFT                       MK_SHIFT_CONST(19)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_0_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_0_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_0_RANGE                       MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_0_ROW                 0
+
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_1_SHIFT                       MK_SHIFT_CONST(20)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_1_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_1_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_1_RANGE                       MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define SLICE1_ICTLR_FIELDS_0_PEX0_C4_SYS_1_ROW                 0
+
+#define SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_0_SHIFT                       MK_SHIFT_CONST(21)
+#define SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_0_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_0_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_0_RANGE                       MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_0_ROW                 0
+
+#define SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_1_SHIFT                       MK_SHIFT_CONST(22)
+#define SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_1_FIELD                       MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_1_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_1_RANGE                       MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define SLICE1_ICTLR_FIELDS_0_PEX1_C5_SYS_1_ROW                 0
+
+#define SLICE1_ICTLR_FIELDS_0_RESERVED_55_SHIFT                 MK_SHIFT_CONST(23)
+#define SLICE1_ICTLR_FIELDS_0_RESERVED_55_FIELD                 MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_RESERVED_55_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_RESERVED_55_RANGE                 MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define SLICE1_ICTLR_FIELDS_0_RESERVED_55_ROW                   0
+
+#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_0_SHIFT                  MK_SHIFT_CONST(24)
+#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_0_FIELD                  MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_AON_GPIO_0_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_0_RANGE                  MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_0_ROW                    0
+
+#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_1_SHIFT                  MK_SHIFT_CONST(25)
+#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_1_FIELD                  MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_AON_GPIO_1_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_1_RANGE                  MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_1_ROW                    0
+
+#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_2_SHIFT                  MK_SHIFT_CONST(26)
+#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_2_FIELD                  MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_AON_GPIO_2_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_2_RANGE                  MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_2_ROW                    0
+
+#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_3_SHIFT                  MK_SHIFT_CONST(27)
+#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_3_FIELD                  MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_AON_GPIO_3_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_3_RANGE                  MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define SLICE1_ICTLR_FIELDS_0_AON_GPIO_3_ROW                    0
+
+#define SLICE1_ICTLR_FIELDS_0_AZA_SHIFT                 MK_SHIFT_CONST(28)
+#define SLICE1_ICTLR_FIELDS_0_AZA_FIELD                 MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_AZA_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_AZA_RANGE                 MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define SLICE1_ICTLR_FIELDS_0_AZA_ROW                   0
+
+#define SLICE1_ICTLR_FIELDS_0_HDACODEC_SHIFT                    MK_SHIFT_CONST(29)
+#define SLICE1_ICTLR_FIELDS_0_HDACODEC_FIELD                    MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_HDACODEC_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_HDACODEC_RANGE                    MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
+#define SLICE1_ICTLR_FIELDS_0_HDACODEC_ROW                      0
+
+#define SLICE1_ICTLR_FIELDS_0_SDMMC1_SHIFT                      MK_SHIFT_CONST(30)
+#define SLICE1_ICTLR_FIELDS_0_SDMMC1_FIELD                      MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_SDMMC1_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_SDMMC1_RANGE                      MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
+#define SLICE1_ICTLR_FIELDS_0_SDMMC1_ROW                        0
+
+#define SLICE1_ICTLR_FIELDS_0_SPI4_SHIFT                        MK_SHIFT_CONST(31)
+#define SLICE1_ICTLR_FIELDS_0_SPI4_FIELD                        MK_FIELD_CONST(0x1, SLICE1_ICTLR_FIELDS_0_SPI4_SHIFT)
+#define SLICE1_ICTLR_FIELDS_0_SPI4_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
+#define SLICE1_ICTLR_FIELDS_0_SPI4_ROW                  0
+
+
+// Packet SLICE2_ICTLR_FIELDS_0
+#define SLICE2_ICTLR_FIELDS_0_SIZE 32
+
+#define SLICE2_ICTLR_FIELDS_0_SPI5_SHIFT                        MK_SHIFT_CONST(0)
+#define SLICE2_ICTLR_FIELDS_0_SPI5_FIELD                        MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_SPI5_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_SPI5_RANGE                        MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define SLICE2_ICTLR_FIELDS_0_SPI5_ROW                  0
+
+#define SLICE2_ICTLR_FIELDS_0_SDMMC4_SHIFT                      MK_SHIFT_CONST(1)
+#define SLICE2_ICTLR_FIELDS_0_SDMMC4_FIELD                      MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_SDMMC4_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_SDMMC4_RANGE                      MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define SLICE2_ICTLR_FIELDS_0_SDMMC4_ROW                        0
+
+#define SLICE2_ICTLR_FIELDS_0_SDMMC1_SYS_SHIFT                  MK_SHIFT_CONST(2)
+#define SLICE2_ICTLR_FIELDS_0_SDMMC1_SYS_FIELD                  MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_SDMMC1_SYS_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_SDMMC1_SYS_RANGE                  MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
+#define SLICE2_ICTLR_FIELDS_0_SDMMC1_SYS_ROW                    0
+
+#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_0_SHIFT                      MK_SHIFT_CONST(3)
+#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_0_FIELD                      MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_0_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_0_RANGE                      MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_0_ROW                        0
+
+#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_1_SHIFT                      MK_SHIFT_CONST(4)
+#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_1_FIELD                      MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_1_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_1_RANGE                      MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_1_ROW                        0
+
+#define SLICE2_ICTLR_FIELDS_0_SDMMC4_SYS_SHIFT                  MK_SHIFT_CONST(5)
+#define SLICE2_ICTLR_FIELDS_0_SDMMC4_SYS_FIELD                  MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_SDMMC4_SYS_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_SDMMC4_SYS_RANGE                  MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define SLICE2_ICTLR_FIELDS_0_SDMMC4_SYS_ROW                    0
+
+#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_2_SHIFT                      MK_SHIFT_CONST(6)
+#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_2_FIELD                      MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_2_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_2_RANGE                      MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_2_ROW                        0
+
+#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_3_SHIFT                      MK_SHIFT_CONST(7)
+#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_3_FIELD                      MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_3_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_3_RANGE                      MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define SLICE2_ICTLR_FIELDS_0_GPU_HOST2SOC_3_ROW                        0
+
+#define SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_0_SHIFT                       MK_SHIFT_CONST(8)
+#define SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_0_FIELD                       MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_0_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_0_RANGE                       MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
+#define SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_0_ROW                 0
+
+#define SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_1_SHIFT                       MK_SHIFT_CONST(9)
+#define SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_1_FIELD                       MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_1_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_1_RANGE                       MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
+#define SLICE2_ICTLR_FIELDS_0_PEX0_C0_SYS_1_ROW                 0
+
+#define SLICE2_ICTLR_FIELDS_0_TSC_IRQ_SHIFT                     MK_SHIFT_CONST(10)
+#define SLICE2_ICTLR_FIELDS_0_TSC_IRQ_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_TSC_IRQ_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_TSC_IRQ_RANGE                     MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define SLICE2_ICTLR_FIELDS_0_TSC_IRQ_ROW                       0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH0_SHIFT                     MK_SHIFT_CONST(11)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH0_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH0_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH0_RANGE                     MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH0_ROW                       0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH1_SHIFT                     MK_SHIFT_CONST(12)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH1_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH1_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH1_RANGE                     MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH1_ROW                       0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH2_SHIFT                     MK_SHIFT_CONST(13)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH2_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH2_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH2_RANGE                     MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH2_ROW                       0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH3_SHIFT                     MK_SHIFT_CONST(14)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH3_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH3_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH3_RANGE                     MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH3_ROW                       0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH4_SHIFT                     MK_SHIFT_CONST(15)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH4_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH4_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH4_RANGE                     MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH4_ROW                       0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH5_SHIFT                     MK_SHIFT_CONST(16)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH5_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH5_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH5_RANGE                     MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH5_ROW                       0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH6_SHIFT                     MK_SHIFT_CONST(17)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH6_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH6_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH6_RANGE                     MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH6_ROW                       0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH7_SHIFT                     MK_SHIFT_CONST(18)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH7_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH7_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH7_RANGE                     MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH7_ROW                       0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH8_SHIFT                     MK_SHIFT_CONST(19)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH8_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH8_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH8_RANGE                     MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH8_ROW                       0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH9_SHIFT                     MK_SHIFT_CONST(20)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH9_FIELD                     MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH9_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH9_RANGE                     MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH9_ROW                       0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH10_SHIFT                    MK_SHIFT_CONST(21)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH10_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH10_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH10_RANGE                    MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH10_ROW                      0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH11_SHIFT                    MK_SHIFT_CONST(22)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH11_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH11_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH11_RANGE                    MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH11_ROW                      0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH12_SHIFT                    MK_SHIFT_CONST(23)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH12_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH12_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH12_RANGE                    MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH12_ROW                      0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH13_SHIFT                    MK_SHIFT_CONST(24)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH13_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH13_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH13_RANGE                    MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH13_ROW                      0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH14_SHIFT                    MK_SHIFT_CONST(25)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH14_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH14_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH14_RANGE                    MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH14_ROW                      0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH15_SHIFT                    MK_SHIFT_CONST(26)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH15_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH15_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH15_RANGE                    MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH15_ROW                      0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH16_SHIFT                    MK_SHIFT_CONST(27)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH16_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH16_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH16_RANGE                    MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH16_ROW                      0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH17_SHIFT                    MK_SHIFT_CONST(28)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH17_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH17_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH17_RANGE                    MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH17_ROW                      0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH18_SHIFT                    MK_SHIFT_CONST(29)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH18_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH18_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH18_RANGE                    MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH18_ROW                      0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH19_SHIFT                    MK_SHIFT_CONST(30)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH19_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH19_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH19_RANGE                    MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH19_ROW                      0
+
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH20_SHIFT                    MK_SHIFT_CONST(31)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH20_FIELD                    MK_FIELD_CONST(0x1, SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH20_SHIFT)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH20_RANGE                    MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
+#define SLICE2_ICTLR_FIELDS_0_CENTRAL_DMA_CH20_ROW                      0
+
+
+// Packet SLICE3_ICTLR_FIELDS_0
+#define SLICE3_ICTLR_FIELDS_0_SIZE 32
+
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH21_SHIFT                    MK_SHIFT_CONST(0)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH21_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH21_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH21_RANGE                    MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH21_ROW                      0
+
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH22_SHIFT                    MK_SHIFT_CONST(1)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH22_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH22_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH22_RANGE                    MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH22_ROW                      0
+
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH23_SHIFT                    MK_SHIFT_CONST(2)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH23_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH23_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH23_RANGE                    MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH23_ROW                      0
+
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH24_SHIFT                    MK_SHIFT_CONST(3)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH24_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH24_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH24_RANGE                    MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH24_ROW                      0
+
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH25_SHIFT                    MK_SHIFT_CONST(4)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH25_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH25_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH25_RANGE                    MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH25_ROW                      0
+
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH26_SHIFT                    MK_SHIFT_CONST(5)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH26_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH26_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH26_RANGE                    MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH26_ROW                      0
+
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH27_SHIFT                    MK_SHIFT_CONST(6)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH27_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH27_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH27_RANGE                    MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH27_ROW                      0
+
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH28_SHIFT                    MK_SHIFT_CONST(7)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH28_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH28_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH28_RANGE                    MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH28_ROW                      0
+
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH29_SHIFT                    MK_SHIFT_CONST(8)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH29_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH29_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH29_RANGE                    MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH29_ROW                      0
+
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH30_SHIFT                    MK_SHIFT_CONST(9)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH30_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH30_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH30_RANGE                    MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH30_ROW                      0
+
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH31_SHIFT                    MK_SHIFT_CONST(10)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH31_FIELD                    MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH31_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH31_RANGE                    MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_CH31_ROW                      0
+
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_COMMON_SHIFT                  MK_SHIFT_CONST(11)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_COMMON_FIELD                  MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_COMMON_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_COMMON_RANGE                  MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
+#define SLICE3_ICTLR_FIELDS_0_CENTRAL_DMA_COMMON_ROW                    0
+
+#define SLICE3_ICTLR_FIELDS_0_PEX2_L4_P2U_SW_SHIFT                      MK_SHIFT_CONST(12)
+#define SLICE3_ICTLR_FIELDS_0_PEX2_L4_P2U_SW_FIELD                      MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_PEX2_L4_P2U_SW_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_PEX2_L4_P2U_SW_RANGE                      MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
+#define SLICE3_ICTLR_FIELDS_0_PEX2_L4_P2U_SW_ROW                        0
+
+#define SLICE3_ICTLR_FIELDS_0_PEX2_L5_P2U_SW_SHIFT                      MK_SHIFT_CONST(13)
+#define SLICE3_ICTLR_FIELDS_0_PEX2_L5_P2U_SW_FIELD                      MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_PEX2_L5_P2U_SW_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_PEX2_L5_P2U_SW_RANGE                      MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
+#define SLICE3_ICTLR_FIELDS_0_PEX2_L5_P2U_SW_ROW                        0
+
+#define SLICE3_ICTLR_FIELDS_0_PEX2_L6_P2U_SW_SHIFT                      MK_SHIFT_CONST(14)
+#define SLICE3_ICTLR_FIELDS_0_PEX2_L6_P2U_SW_FIELD                      MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_PEX2_L6_P2U_SW_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_PEX2_L6_P2U_SW_RANGE                      MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
+#define SLICE3_ICTLR_FIELDS_0_PEX2_L6_P2U_SW_ROW                        0
+
+#define SLICE3_ICTLR_FIELDS_0_PEX2_L7_P2U_SW_SHIFT                      MK_SHIFT_CONST(15)
+#define SLICE3_ICTLR_FIELDS_0_PEX2_L7_P2U_SW_FIELD                      MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_PEX2_L7_P2U_SW_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_PEX2_L7_P2U_SW_RANGE                      MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define SLICE3_ICTLR_FIELDS_0_PEX2_L7_P2U_SW_ROW                        0
+
+#define SLICE3_ICTLR_FIELDS_0_UARTA_SHIFT                       MK_SHIFT_CONST(16)
+#define SLICE3_ICTLR_FIELDS_0_UARTA_FIELD                       MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTA_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_UARTA_RANGE                       MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define SLICE3_ICTLR_FIELDS_0_UARTA_ROW                 0
+
+#define SLICE3_ICTLR_FIELDS_0_UARTB_SHIFT                       MK_SHIFT_CONST(17)
+#define SLICE3_ICTLR_FIELDS_0_UARTB_FIELD                       MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTB_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_UARTB_RANGE                       MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define SLICE3_ICTLR_FIELDS_0_UARTB_ROW                 0
+
+#define SLICE3_ICTLR_FIELDS_0_UARTC_SHIFT                       MK_SHIFT_CONST(18)
+#define SLICE3_ICTLR_FIELDS_0_UARTC_FIELD                       MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTC_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_UARTC_RANGE                       MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define SLICE3_ICTLR_FIELDS_0_UARTC_ROW                 0
+
+#define SLICE3_ICTLR_FIELDS_0_UARTD_SHIFT                       MK_SHIFT_CONST(19)
+#define SLICE3_ICTLR_FIELDS_0_UARTD_FIELD                       MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTD_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_UARTD_RANGE                       MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define SLICE3_ICTLR_FIELDS_0_UARTD_ROW                 0
+
+#define SLICE3_ICTLR_FIELDS_0_UARTE_SHIFT                       MK_SHIFT_CONST(20)
+#define SLICE3_ICTLR_FIELDS_0_UARTE_FIELD                       MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTE_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_UARTE_RANGE                       MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define SLICE3_ICTLR_FIELDS_0_UARTE_ROW                 0
+
+#define SLICE3_ICTLR_FIELDS_0_UARTF_SHIFT                       MK_SHIFT_CONST(21)
+#define SLICE3_ICTLR_FIELDS_0_UARTF_FIELD                       MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_UARTF_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_UARTF_RANGE                       MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define SLICE3_ICTLR_FIELDS_0_UARTF_ROW                 0
+
+#define SLICE3_ICTLR_FIELDS_0_RESERVED_118_SHIFT                        MK_SHIFT_CONST(22)
+#define SLICE3_ICTLR_FIELDS_0_RESERVED_118_FIELD                        MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_RESERVED_118_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_RESERVED_118_RANGE                        MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define SLICE3_ICTLR_FIELDS_0_RESERVED_118_ROW                  0
+
+#define SLICE3_ICTLR_FIELDS_0_NVCSI_SHIFT                       MK_SHIFT_CONST(23)
+#define SLICE3_ICTLR_FIELDS_0_NVCSI_FIELD                       MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_NVCSI_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_NVCSI_RANGE                       MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define SLICE3_ICTLR_FIELDS_0_NVCSI_ROW                 0
+
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_0_SHIFT                   MK_SHIFT_CONST(24)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_0_FIELD                   MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_0_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_0_RANGE                   MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_0_ROW                     0
+
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_1_SHIFT                   MK_SHIFT_CONST(25)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_1_FIELD                   MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_1_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_1_RANGE                   MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_1_ROW                     0
+
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_2_SHIFT                   MK_SHIFT_CONST(26)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_2_FIELD                   MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_2_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_2_RANGE                   MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_2_ROW                     0
+
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_3_SHIFT                   MK_SHIFT_CONST(27)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_3_FIELD                   MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_3_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_3_RANGE                   MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_3_ROW                     0
+
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_4_SHIFT                   MK_SHIFT_CONST(28)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_4_FIELD                   MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_4_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_4_RANGE                   MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_4_ROW                     0
+
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_5_SHIFT                   MK_SHIFT_CONST(29)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_5_FIELD                   MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_5_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_5_RANGE                   MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_5_ROW                     0
+
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_6_SHIFT                   MK_SHIFT_CONST(30)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_6_FIELD                   MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_6_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_6_RANGE                   MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_6_ROW                     0
+
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_7_SHIFT                   MK_SHIFT_CONST(31)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_7_FIELD                   MK_FIELD_CONST(0x1, SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_7_SHIFT)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_7_RANGE                   MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
+#define SLICE3_ICTLR_FIELDS_0_TOP_HSP0_SHARED_7_ROW                     0
+
+
+// Packet SLICE4_ICTLR_FIELDS_0
+#define SLICE4_ICTLR_FIELDS_0_SIZE 32
+
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_0_SHIFT                   MK_SHIFT_CONST(0)
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_0_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_0_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_0_RANGE                   MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_0_ROW                     0
+
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_1_SHIFT                   MK_SHIFT_CONST(1)
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_1_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_1_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_1_RANGE                   MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_1_ROW                     0
+
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_2_SHIFT                   MK_SHIFT_CONST(2)
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_2_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_2_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_2_RANGE                   MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_2_ROW                     0
+
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_3_SHIFT                   MK_SHIFT_CONST(3)
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_3_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_3_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_3_RANGE                   MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_3_ROW                     0
+
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_4_SHIFT                   MK_SHIFT_CONST(4)
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_4_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_4_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_4_RANGE                   MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define SLICE4_ICTLR_FIELDS_0_TOP_HSP1_SHARED_4_ROW                     0
+
+#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_0_SHIFT                      MK_SHIFT_CONST(5)
+#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_0_FIELD                      MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_0_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_0_RANGE                      MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_0_ROW                        0
+
+#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_1_SHIFT                      MK_SHIFT_CONST(6)
+#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_1_FIELD                      MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_1_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_1_RANGE                      MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_1_ROW                        0
+
+#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_2_SHIFT                      MK_SHIFT_CONST(7)
+#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_2_FIELD                      MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_2_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_2_RANGE                      MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_2_ROW                        0
+
+#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_3_SHIFT                      MK_SHIFT_CONST(8)
+#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_3_FIELD                      MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_3_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_3_RANGE                      MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
+#define SLICE4_ICTLR_FIELDS_0_AON_MBOX_OUT_3_ROW                        0
+
+#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_1_SHIFT                   MK_SHIFT_CONST(9)
+#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_1_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_1_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_1_RANGE                   MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
+#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_1_ROW                     0
+
+#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_2_SHIFT                   MK_SHIFT_CONST(10)
+#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_2_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_2_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_2_RANGE                   MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_2_ROW                     0
+
+#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_3_SHIFT                   MK_SHIFT_CONST(11)
+#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_3_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_3_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_3_RANGE                   MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
+#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_3_ROW                     0
+
+#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_4_SHIFT                   MK_SHIFT_CONST(12)
+#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_4_FIELD                   MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_4_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_4_RANGE                   MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
+#define SLICE4_ICTLR_FIELDS_0_BPMP_HSP_SHARED_4_ROW                     0
+
+#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_0_SHIFT                      MK_SHIFT_CONST(13)
+#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_0_FIELD                      MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_0_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_0_RANGE                      MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
+#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_0_ROW                        0
+
+#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_1_SHIFT                      MK_SHIFT_CONST(14)
+#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_1_FIELD                      MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_1_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_1_RANGE                      MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
+#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_1_ROW                        0
+
+#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_2_SHIFT                      MK_SHIFT_CONST(15)
+#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_2_FIELD                      MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_2_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_2_RANGE                      MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_2_ROW                        0
+
+#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_3_SHIFT                      MK_SHIFT_CONST(16)
+#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_3_FIELD                      MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_3_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_3_RANGE                      MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define SLICE4_ICTLR_FIELDS_0_SCE_MBOX_OUT_3_ROW                        0
+
+#define SLICE4_ICTLR_FIELDS_0_APE_IRQ0_SHIFT                    MK_SHIFT_CONST(17)
+#define SLICE4_ICTLR_FIELDS_0_APE_IRQ0_FIELD                    MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_IRQ0_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_APE_IRQ0_RANGE                    MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define SLICE4_ICTLR_FIELDS_0_APE_IRQ0_ROW                      0
+
+#define SLICE4_ICTLR_FIELDS_0_APE_IRQ1_SHIFT                    MK_SHIFT_CONST(18)
+#define SLICE4_ICTLR_FIELDS_0_APE_IRQ1_FIELD                    MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_IRQ1_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_APE_IRQ1_RANGE                    MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define SLICE4_ICTLR_FIELDS_0_APE_IRQ1_ROW                      0
+
+#define SLICE4_ICTLR_FIELDS_0_APE_IRQ2_SHIFT                    MK_SHIFT_CONST(19)
+#define SLICE4_ICTLR_FIELDS_0_APE_IRQ2_FIELD                    MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_IRQ2_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_APE_IRQ2_RANGE                    MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define SLICE4_ICTLR_FIELDS_0_APE_IRQ2_ROW                      0
+
+#define SLICE4_ICTLR_FIELDS_0_APE_IRQ3_SHIFT                    MK_SHIFT_CONST(20)
+#define SLICE4_ICTLR_FIELDS_0_APE_IRQ3_FIELD                    MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_IRQ3_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_APE_IRQ3_RANGE                    MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define SLICE4_ICTLR_FIELDS_0_APE_IRQ3_ROW                      0
+
+#define SLICE4_ICTLR_FIELDS_0_APE_FIQ0_SHIFT                    MK_SHIFT_CONST(21)
+#define SLICE4_ICTLR_FIELDS_0_APE_FIQ0_FIELD                    MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_FIQ0_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_APE_FIQ0_RANGE                    MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define SLICE4_ICTLR_FIELDS_0_APE_FIQ0_ROW                      0
+
+#define SLICE4_ICTLR_FIELDS_0_APE_FIQ1_SHIFT                    MK_SHIFT_CONST(22)
+#define SLICE4_ICTLR_FIELDS_0_APE_FIQ1_FIELD                    MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_FIQ1_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_APE_FIQ1_RANGE                    MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define SLICE4_ICTLR_FIELDS_0_APE_FIQ1_ROW                      0
+
+#define SLICE4_ICTLR_FIELDS_0_APE_FIQ2_SHIFT                    MK_SHIFT_CONST(23)
+#define SLICE4_ICTLR_FIELDS_0_APE_FIQ2_FIELD                    MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_FIQ2_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_APE_FIQ2_RANGE                    MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define SLICE4_ICTLR_FIELDS_0_APE_FIQ2_ROW                      0
+
+#define SLICE4_ICTLR_FIELDS_0_APE_FIQ3_SHIFT                    MK_SHIFT_CONST(24)
+#define SLICE4_ICTLR_FIELDS_0_APE_FIQ3_FIELD                    MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_APE_FIQ3_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_APE_FIQ3_RANGE                    MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define SLICE4_ICTLR_FIELDS_0_APE_FIQ3_ROW                      0
+
+#define SLICE4_ICTLR_FIELDS_0_VI2_THI_SHIFT                     MK_SHIFT_CONST(25)
+#define SLICE4_ICTLR_FIELDS_0_VI2_THI_FIELD                     MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_VI2_THI_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_VI2_THI_RANGE                     MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define SLICE4_ICTLR_FIELDS_0_VI2_THI_ROW                       0
+
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_0_SHIFT                  MK_SHIFT_CONST(26)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_0_FIELD                  MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_VI2_VMID_0_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_0_RANGE                  MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_0_ROW                    0
+
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_1_SHIFT                  MK_SHIFT_CONST(27)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_1_FIELD                  MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_VI2_VMID_1_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_1_RANGE                  MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_1_ROW                    0
+
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_2_SHIFT                  MK_SHIFT_CONST(28)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_2_FIELD                  MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_VI2_VMID_2_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_2_RANGE                  MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_2_ROW                    0
+
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_3_SHIFT                  MK_SHIFT_CONST(29)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_3_FIELD                  MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_VI2_VMID_3_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_3_RANGE                  MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_3_ROW                    0
+
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_4_SHIFT                  MK_SHIFT_CONST(30)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_4_FIELD                  MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_VI2_VMID_4_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_4_RANGE                  MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_4_ROW                    0
+
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_5_SHIFT                  MK_SHIFT_CONST(31)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_5_FIELD                  MK_FIELD_CONST(0x1, SLICE4_ICTLR_FIELDS_0_VI2_VMID_5_SHIFT)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_5_RANGE                  MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
+#define SLICE4_ICTLR_FIELDS_0_VI2_VMID_5_ROW                    0
+
+
+// Packet SLICE5_ICTLR_FIELDS_0
+#define SLICE5_ICTLR_FIELDS_0_SIZE 32
+
+#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_6_SHIFT                  MK_SHIFT_CONST(0)
+#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_6_FIELD                  MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_VI2_VMID_6_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_6_RANGE                  MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_6_ROW                    0
+
+#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_7_SHIFT                  MK_SHIFT_CONST(1)
+#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_7_FIELD                  MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_VI2_VMID_7_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_7_RANGE                  MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_7_ROW                    0
+
+#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_8_SHIFT                  MK_SHIFT_CONST(2)
+#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_8_FIELD                  MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_VI2_VMID_8_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_8_RANGE                  MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
+#define SLICE5_ICTLR_FIELDS_0_VI2_VMID_8_ROW                    0
+
+#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_INT_SHIFT                       MK_SHIFT_CONST(3)
+#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_INT_FIELD                       MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_HOST_INT_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_INT_RANGE                       MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_INT_ROW                 0
+
+#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_SMI_SHIFT                       MK_SHIFT_CONST(4)
+#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_SMI_FIELD                       MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_HOST_SMI_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_SMI_RANGE                       MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_SMI_ROW                 0
+
+#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_PME_SHIFT                       MK_SHIFT_CONST(5)
+#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_PME_FIELD                       MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_HOST_PME_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_PME_RANGE                       MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define SLICE5_ICTLR_FIELDS_0_USB3_HOST_PME_ROW                 0
+
+#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_INT_SHIFT                        MK_SHIFT_CONST(6)
+#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_INT_FIELD                        MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_DEV_INT_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_INT_RANGE                        MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_INT_ROW                  0
+
+#define SLICE5_ICTLR_FIELDS_0_XUSB_PADCTL_SHIFT                 MK_SHIFT_CONST(7)
+#define SLICE5_ICTLR_FIELDS_0_XUSB_PADCTL_FIELD                 MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_XUSB_PADCTL_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_XUSB_PADCTL_RANGE                 MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define SLICE5_ICTLR_FIELDS_0_XUSB_PADCTL_ROW                   0
+
+#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_SMI_SHIFT                        MK_SHIFT_CONST(8)
+#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_SMI_FIELD                        MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_DEV_SMI_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_SMI_RANGE                        MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
+#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_SMI_ROW                  0
+
+#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_PME_SHIFT                        MK_SHIFT_CONST(9)
+#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_PME_FIELD                        MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_USB3_DEV_PME_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_PME_RANGE                        MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
+#define SLICE5_ICTLR_FIELDS_0_USB3_DEV_PME_ROW                  0
+
+#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_NS_SHIFT                    MK_SHIFT_CONST(10)
+#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_NS_FIELD                    MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_NS_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_NS_RANGE                    MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_NS_ROW                      0
+
+#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_S_SHIFT                     MK_SHIFT_CONST(11)
+#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_S_FIELD                     MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_S_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_S_RANGE                     MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
+#define SLICE5_ICTLR_FIELDS_0_SMMU_COMBINED_S_ROW                       0
+
+#define SLICE5_ICTLR_FIELDS_0_SECURE_AON_FABRIC_SHIFT                   MK_SHIFT_CONST(12)
+#define SLICE5_ICTLR_FIELDS_0_SECURE_AON_FABRIC_FIELD                   MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_SECURE_AON_FABRIC_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_SECURE_AON_FABRIC_RANGE                   MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
+#define SLICE5_ICTLR_FIELDS_0_SECURE_AON_FABRIC_ROW                     0
+
+#define SLICE5_ICTLR_FIELDS_0_SECURE_SCE_FABRIC_SHIFT                   MK_SHIFT_CONST(13)
+#define SLICE5_ICTLR_FIELDS_0_SECURE_SCE_FABRIC_FIELD                   MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_SECURE_SCE_FABRIC_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_SECURE_SCE_FABRIC_RANGE                   MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
+#define SLICE5_ICTLR_FIELDS_0_SECURE_SCE_FABRIC_ROW                     0
+
+#define SLICE5_ICTLR_FIELDS_0_SECURE_BPMP_FABRIC_SHIFT                  MK_SHIFT_CONST(14)
+#define SLICE5_ICTLR_FIELDS_0_SECURE_BPMP_FABRIC_FIELD                  MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_SECURE_BPMP_FABRIC_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_SECURE_BPMP_FABRIC_RANGE                  MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
+#define SLICE5_ICTLR_FIELDS_0_SECURE_BPMP_FABRIC_ROW                    0
+
+#define SLICE5_ICTLR_FIELDS_0_SECURE_RCE_FABRIC_SHIFT                   MK_SHIFT_CONST(15)
+#define SLICE5_ICTLR_FIELDS_0_SECURE_RCE_FABRIC_FIELD                   MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_SECURE_RCE_FABRIC_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_SECURE_RCE_FABRIC_RANGE                   MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define SLICE5_ICTLR_FIELDS_0_SECURE_RCE_FABRIC_ROW                     0
+
+#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_NOT_SECURE_SHIFT                  MK_SHIFT_CONST(16)
+#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_NOT_SECURE_FIELD                  MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_NOT_SECURE_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_NOT_SECURE_RANGE                  MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_NOT_SECURE_ROW                    0
+
+#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_SECURE_SHIFT                      MK_SHIFT_CONST(17)
+#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_SECURE_FIELD                      MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_SECURE_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_SECURE_RANGE                      MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define SLICE5_ICTLR_FIELDS_0_DOORBELL_CCPLEX_SECURE_ROW                        0
+
+#define SLICE5_ICTLR_FIELDS_0_RESERVED_178_SHIFT                        MK_SHIFT_CONST(18)
+#define SLICE5_ICTLR_FIELDS_0_RESERVED_178_FIELD                        MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_RESERVED_178_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_RESERVED_178_RANGE                        MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define SLICE5_ICTLR_FIELDS_0_RESERVED_178_ROW                  0
+
+#define SLICE5_ICTLR_FIELDS_0_RESERVED_179_SHIFT                        MK_SHIFT_CONST(19)
+#define SLICE5_ICTLR_FIELDS_0_RESERVED_179_FIELD                        MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_RESERVED_179_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_RESERVED_179_RANGE                        MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define SLICE5_ICTLR_FIELDS_0_RESERVED_179_ROW                  0
+
+#define SLICE5_ICTLR_FIELDS_0_RESERVED_180_SHIFT                        MK_SHIFT_CONST(20)
+#define SLICE5_ICTLR_FIELDS_0_RESERVED_180_FIELD                        MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_RESERVED_180_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_RESERVED_180_RANGE                        MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define SLICE5_ICTLR_FIELDS_0_RESERVED_180_ROW                  0
+
+#define SLICE5_ICTLR_FIELDS_0_RESERVED_181_SHIFT                        MK_SHIFT_CONST(21)
+#define SLICE5_ICTLR_FIELDS_0_RESERVED_181_FIELD                        MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_RESERVED_181_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_RESERVED_181_RANGE                        MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define SLICE5_ICTLR_FIELDS_0_RESERVED_181_ROW                  0
+
+#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_0_SHIFT                      MK_SHIFT_CONST(22)
+#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_0_FIELD                      MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_0_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_0_RANGE                      MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_0_ROW                        0
+
+#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_1_SHIFT                      MK_SHIFT_CONST(23)
+#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_1_FIELD                      MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_1_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_1_RANGE                      MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_1_ROW                        0
+
+#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_2_SHIFT                      MK_SHIFT_CONST(24)
+#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_2_FIELD                      MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_2_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_2_RANGE                      MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_2_ROW                        0
+
+#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_3_SHIFT                      MK_SHIFT_CONST(25)
+#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_3_FIELD                      MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_3_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_3_RANGE                      MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define SLICE5_ICTLR_FIELDS_0_RCE_MBOX_OUT_3_ROW                        0
+
+#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_0_SHIFT                   MK_SHIFT_CONST(26)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_0_FIELD                   MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_VM_0_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_0_RANGE                   MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_0_ROW                     0
+
+#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_1_SHIFT                   MK_SHIFT_CONST(27)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_1_FIELD                   MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_VM_1_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_1_RANGE                   MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_1_ROW                     0
+
+#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_2_SHIFT                   MK_SHIFT_CONST(28)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_2_FIELD                   MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_VM_2_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_2_RANGE                   MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_2_ROW                     0
+
+#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_3_SHIFT                   MK_SHIFT_CONST(29)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_3_FIELD                   MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_VM_3_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_3_RANGE                   MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_VM_3_ROW                     0
+
+#define SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_NON_SECURE_SHIFT                      MK_SHIFT_CONST(30)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_NON_SECURE_FIELD                      MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_NON_SECURE_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_NON_SECURE_RANGE                      MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_NON_SECURE_ROW                        0
+
+#define SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_SECURE_SHIFT                  MK_SHIFT_CONST(31)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_SECURE_FIELD                  MK_FIELD_CONST(0x1, SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_SECURE_SHIFT)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_SECURE_RANGE                  MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
+#define SLICE5_ICTLR_FIELDS_0_EQOS_MACSEC_SECURE_ROW                    0
+
+
+// Packet SLICE6_ICTLR_FIELDS_0
+#define SLICE6_ICTLR_FIELDS_0_SIZE 32
+
+#define SLICE6_ICTLR_FIELDS_0_TACH0_SHIFT                       MK_SHIFT_CONST(0)
+#define SLICE6_ICTLR_FIELDS_0_TACH0_FIELD                       MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_TACH0_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_TACH0_RANGE                       MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define SLICE6_ICTLR_FIELDS_0_TACH0_ROW                 0
+
+#define SLICE6_ICTLR_FIELDS_0_TACH1_SHIFT                       MK_SHIFT_CONST(1)
+#define SLICE6_ICTLR_FIELDS_0_TACH1_FIELD                       MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_TACH1_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_TACH1_RANGE                       MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define SLICE6_ICTLR_FIELDS_0_TACH1_ROW                 0
+
+#define SLICE6_ICTLR_FIELDS_0_EQOS_COMMON_SHIFT                 MK_SHIFT_CONST(2)
+#define SLICE6_ICTLR_FIELDS_0_EQOS_COMMON_FIELD                 MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_EQOS_COMMON_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_EQOS_COMMON_RANGE                 MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
+#define SLICE6_ICTLR_FIELDS_0_EQOS_COMMON_ROW                   0
+
+#define SLICE6_ICTLR_FIELDS_0_I2S7_SHIFT                        MK_SHIFT_CONST(3)
+#define SLICE6_ICTLR_FIELDS_0_I2S7_FIELD                        MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_I2S7_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_I2S7_RANGE                        MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define SLICE6_ICTLR_FIELDS_0_I2S7_ROW                  0
+
+#define SLICE6_ICTLR_FIELDS_0_I2S8_SHIFT                        MK_SHIFT_CONST(4)
+#define SLICE6_ICTLR_FIELDS_0_I2S8_FIELD                        MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_I2S8_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_I2S8_RANGE                        MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define SLICE6_ICTLR_FIELDS_0_I2S8_ROW                  0
+
+#define SLICE6_ICTLR_FIELDS_0_NVJPG1_SHIFT                      MK_SHIFT_CONST(5)
+#define SLICE6_ICTLR_FIELDS_0_NVJPG1_FIELD                      MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_NVJPG1_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_NVJPG1_RANGE                      MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define SLICE6_ICTLR_FIELDS_0_NVJPG1_ROW                        0
+
+#define SLICE6_ICTLR_FIELDS_0_NVJPG_SHIFT                       MK_SHIFT_CONST(6)
+#define SLICE6_ICTLR_FIELDS_0_NVJPG_FIELD                       MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_NVJPG_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_NVJPG_RANGE                       MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define SLICE6_ICTLR_FIELDS_0_NVJPG_ROW                 0
+
+#define SLICE6_ICTLR_FIELDS_0_NVDEC_SHIFT                       MK_SHIFT_CONST(7)
+#define SLICE6_ICTLR_FIELDS_0_NVDEC_FIELD                       MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_NVDEC_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_NVDEC_RANGE                       MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define SLICE6_ICTLR_FIELDS_0_NVDEC_ROW                 0
+
+#define SLICE6_ICTLR_FIELDS_0_NVENC_SHIFT                       MK_SHIFT_CONST(8)
+#define SLICE6_ICTLR_FIELDS_0_NVENC_FIELD                       MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_NVENC_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_NVENC_RANGE                       MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
+#define SLICE6_ICTLR_FIELDS_0_NVENC_ROW                 0
+
+#define SLICE6_ICTLR_FIELDS_0_VI_THI_SHIFT                      MK_SHIFT_CONST(9)
+#define SLICE6_ICTLR_FIELDS_0_VI_THI_FIELD                      MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_VI_THI_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_VI_THI_RANGE                      MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
+#define SLICE6_ICTLR_FIELDS_0_VI_THI_ROW                        0
+
+#define SLICE6_ICTLR_FIELDS_0_RESERVED_202_SHIFT                        MK_SHIFT_CONST(10)
+#define SLICE6_ICTLR_FIELDS_0_RESERVED_202_FIELD                        MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_RESERVED_202_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_RESERVED_202_RANGE                        MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define SLICE6_ICTLR_FIELDS_0_RESERVED_202_ROW                  0
+
+#define SLICE6_ICTLR_FIELDS_0_PEX2_L0_P2U_SW_SHIFT                      MK_SHIFT_CONST(11)
+#define SLICE6_ICTLR_FIELDS_0_PEX2_L0_P2U_SW_FIELD                      MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_PEX2_L0_P2U_SW_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_PEX2_L0_P2U_SW_RANGE                      MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
+#define SLICE6_ICTLR_FIELDS_0_PEX2_L0_P2U_SW_ROW                        0
+
+#define SLICE6_ICTLR_FIELDS_0_ISP_1_SHIFT                       MK_SHIFT_CONST(12)
+#define SLICE6_ICTLR_FIELDS_0_ISP_1_FIELD                       MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_ISP_1_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_ISP_1_RANGE                       MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
+#define SLICE6_ICTLR_FIELDS_0_ISP_1_ROW                 0
+
+#define SLICE6_ICTLR_FIELDS_0_ISP_SHIFT                 MK_SHIFT_CONST(13)
+#define SLICE6_ICTLR_FIELDS_0_ISP_FIELD                 MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_ISP_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_ISP_RANGE                 MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
+#define SLICE6_ICTLR_FIELDS_0_ISP_ROW                   0
+
+#define SLICE6_ICTLR_FIELDS_0_VIC_SHIFT                 MK_SHIFT_CONST(14)
+#define SLICE6_ICTLR_FIELDS_0_VIC_FIELD                 MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_VIC_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_VIC_RANGE                 MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
+#define SLICE6_ICTLR_FIELDS_0_VIC_ROW                   0
+
+#define SLICE6_ICTLR_FIELDS_0_UARTH_SHIFT                       MK_SHIFT_CONST(15)
+#define SLICE6_ICTLR_FIELDS_0_UARTH_FIELD                       MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_UARTH_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_UARTH_RANGE                       MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define SLICE6_ICTLR_FIELDS_0_UARTH_ROW                 0
+
+#define SLICE6_ICTLR_FIELDS_0_CVC_SHIFT                 MK_SHIFT_CONST(16)
+#define SLICE6_ICTLR_FIELDS_0_CVC_FIELD                 MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_CVC_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_CVC_RANGE                 MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define SLICE6_ICTLR_FIELDS_0_CVC_ROW                   0
+
+#define SLICE6_ICTLR_FIELDS_0_PMIC_EXT_SHIFT                    MK_SHIFT_CONST(17)
+#define SLICE6_ICTLR_FIELDS_0_PMIC_EXT_FIELD                    MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_PMIC_EXT_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_PMIC_EXT_RANGE                    MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define SLICE6_ICTLR_FIELDS_0_PMIC_EXT_ROW                      0
+
+#define SLICE6_ICTLR_FIELDS_0_ACTMON_SHIFT                      MK_SHIFT_CONST(18)
+#define SLICE6_ICTLR_FIELDS_0_ACTMON_FIELD                      MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_ACTMON_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_ACTMON_RANGE                      MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define SLICE6_ICTLR_FIELDS_0_ACTMON_ROW                        0
+
+#define SLICE6_ICTLR_FIELDS_0_PMC2LIC_INTR_SHIFT                        MK_SHIFT_CONST(19)
+#define SLICE6_ICTLR_FIELDS_0_PMC2LIC_INTR_FIELD                        MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_PMC2LIC_INTR_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_PMC2LIC_INTR_RANGE                        MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define SLICE6_ICTLR_FIELDS_0_PMC2LIC_INTR_ROW                  0
+
+#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_0_SHIFT                  MK_SHIFT_CONST(20)
+#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_0_FIELD                  MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_AON_WAKE_0_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_0_RANGE                  MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_0_ROW                    0
+
+#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_1_SHIFT                  MK_SHIFT_CONST(21)
+#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_1_FIELD                  MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_AON_WAKE_1_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_1_RANGE                  MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_1_ROW                    0
+
+#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_2_SHIFT                  MK_SHIFT_CONST(22)
+#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_2_FIELD                  MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_AON_WAKE_2_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_2_RANGE                  MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define SLICE6_ICTLR_FIELDS_0_AON_WAKE_2_ROW                    0
+
+#define SLICE6_ICTLR_FIELDS_0_OFA0_SHIFT                        MK_SHIFT_CONST(23)
+#define SLICE6_ICTLR_FIELDS_0_OFA0_FIELD                        MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_OFA0_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_OFA0_RANGE                        MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define SLICE6_ICTLR_FIELDS_0_OFA0_ROW                  0
+
+#define SLICE6_ICTLR_FIELDS_0_AON_PM_SHIFT                      MK_SHIFT_CONST(24)
+#define SLICE6_ICTLR_FIELDS_0_AON_PM_FIELD                      MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_AON_PM_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_AON_PM_RANGE                      MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define SLICE6_ICTLR_FIELDS_0_AON_PM_ROW                        0
+
+#define SLICE6_ICTLR_FIELDS_0_DFD_0_SHIFT                       MK_SHIFT_CONST(25)
+#define SLICE6_ICTLR_FIELDS_0_DFD_0_FIELD                       MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_DFD_0_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_DFD_0_RANGE                       MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define SLICE6_ICTLR_FIELDS_0_DFD_0_ROW                 0
+
+#define SLICE6_ICTLR_FIELDS_0_THERMAL_SHIFT                     MK_SHIFT_CONST(26)
+#define SLICE6_ICTLR_FIELDS_0_THERMAL_FIELD                     MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_THERMAL_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_THERMAL_RANGE                     MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define SLICE6_ICTLR_FIELDS_0_THERMAL_ROW                       0
+
+#define SLICE6_ICTLR_FIELDS_0_EDP_SHIFT                 MK_SHIFT_CONST(27)
+#define SLICE6_ICTLR_FIELDS_0_EDP_FIELD                 MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_EDP_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_EDP_RANGE                 MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define SLICE6_ICTLR_FIELDS_0_EDP_ROW                   0
+
+#define SLICE6_ICTLR_FIELDS_0_PEX2_L1_P2U_SW_SHIFT                      MK_SHIFT_CONST(28)
+#define SLICE6_ICTLR_FIELDS_0_PEX2_L1_P2U_SW_FIELD                      MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_PEX2_L1_P2U_SW_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_PEX2_L1_P2U_SW_RANGE                      MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define SLICE6_ICTLR_FIELDS_0_PEX2_L1_P2U_SW_ROW                        0
+
+#define SLICE6_ICTLR_FIELDS_0_PEX2_L2_P2U_SW_SHIFT                      MK_SHIFT_CONST(29)
+#define SLICE6_ICTLR_FIELDS_0_PEX2_L2_P2U_SW_FIELD                      MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_PEX2_L2_P2U_SW_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_PEX2_L2_P2U_SW_RANGE                      MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
+#define SLICE6_ICTLR_FIELDS_0_PEX2_L2_P2U_SW_ROW                        0
+
+#define SLICE6_ICTLR_FIELDS_0_PEX2_L3_P2U_SW_SHIFT                      MK_SHIFT_CONST(30)
+#define SLICE6_ICTLR_FIELDS_0_PEX2_L3_P2U_SW_FIELD                      MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_PEX2_L3_P2U_SW_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_PEX2_L3_P2U_SW_RANGE                      MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
+#define SLICE6_ICTLR_FIELDS_0_PEX2_L3_P2U_SW_ROW                        0
+
+#define SLICE6_ICTLR_FIELDS_0_MC_SHIFT                  MK_SHIFT_CONST(31)
+#define SLICE6_ICTLR_FIELDS_0_MC_FIELD                  MK_FIELD_CONST(0x1, SLICE6_ICTLR_FIELDS_0_MC_SHIFT)
+#define SLICE6_ICTLR_FIELDS_0_MC_RANGE                  MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
+#define SLICE6_ICTLR_FIELDS_0_MC_ROW                    0
+
+
+// Packet SLICE7_ICTLR_FIELDS_0
+#define SLICE7_ICTLR_FIELDS_0_SIZE 32
+
+#define SLICE7_ICTLR_FIELDS_0_EMC_SHIFT                 MK_SHIFT_CONST(0)
+#define SLICE7_ICTLR_FIELDS_0_EMC_FIELD                 MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_EMC_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_EMC_RANGE                 MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define SLICE7_ICTLR_FIELDS_0_EMC_ROW                   0
+
+#define SLICE7_ICTLR_FIELDS_0_RESERVED_225_SHIFT                        MK_SHIFT_CONST(1)
+#define SLICE7_ICTLR_FIELDS_0_RESERVED_225_FIELD                        MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_RESERVED_225_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_RESERVED_225_RANGE                        MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define SLICE7_ICTLR_FIELDS_0_RESERVED_225_ROW                  0
+
+#define SLICE7_ICTLR_FIELDS_0_AON_CAR_SHIFT                     MK_SHIFT_CONST(2)
+#define SLICE7_ICTLR_FIELDS_0_AON_CAR_FIELD                     MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_AON_CAR_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_AON_CAR_RANGE                     MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
+#define SLICE7_ICTLR_FIELDS_0_AON_CAR_ROW                       0
+
+#define SLICE7_ICTLR_FIELDS_0_EMC_CORR_ECC_ERR_SHIFT                    MK_SHIFT_CONST(3)
+#define SLICE7_ICTLR_FIELDS_0_EMC_CORR_ECC_ERR_FIELD                    MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_EMC_CORR_ECC_ERR_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_EMC_CORR_ECC_ERR_RANGE                    MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define SLICE7_ICTLR_FIELDS_0_EMC_CORR_ECC_ERR_ROW                      0
+
+#define SLICE7_ICTLR_FIELDS_0_TSEC_SHIFT                        MK_SHIFT_CONST(4)
+#define SLICE7_ICTLR_FIELDS_0_TSEC_FIELD                        MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TSEC_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_TSEC_RANGE                        MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define SLICE7_ICTLR_FIELDS_0_TSEC_ROW                  0
+
+#define SLICE7_ICTLR_FIELDS_0_RESERVED_229_SHIFT                        MK_SHIFT_CONST(5)
+#define SLICE7_ICTLR_FIELDS_0_RESERVED_229_FIELD                        MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_RESERVED_229_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_RESERVED_229_RANGE                        MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define SLICE7_ICTLR_FIELDS_0_RESERVED_229_ROW                  0
+
+#define SLICE7_ICTLR_FIELDS_0_RESERVED_230_SHIFT                        MK_SHIFT_CONST(6)
+#define SLICE7_ICTLR_FIELDS_0_RESERVED_230_FIELD                        MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_RESERVED_230_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_RESERVED_230_RANGE                        MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define SLICE7_ICTLR_FIELDS_0_RESERVED_230_ROW                  0
+
+#define SLICE7_ICTLR_FIELDS_0_CBB_SECURE_SHIFT                  MK_SHIFT_CONST(7)
+#define SLICE7_ICTLR_FIELDS_0_CBB_SECURE_FIELD                  MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_CBB_SECURE_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_CBB_SECURE_RANGE                  MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define SLICE7_ICTLR_FIELDS_0_CBB_SECURE_ROW                    0
+
+#define SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_NS_SHIFT                   MK_SHIFT_CONST(8)
+#define SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_NS_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_NS_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_NS_RANGE                   MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
+#define SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_NS_ROW                     0
+
+#define SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_S_SHIFT                    MK_SHIFT_CONST(9)
+#define SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_S_FIELD                    MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_S_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_S_RANGE                    MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
+#define SLICE7_ICTLR_FIELDS_0_SMMU1_COMBINED_S_ROW                      0
+
+#define SLICE7_ICTLR_FIELDS_0_PVA0_SHIFT                        MK_SHIFT_CONST(10)
+#define SLICE7_ICTLR_FIELDS_0_PVA0_FIELD                        MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_PVA0_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_PVA0_RANGE                        MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define SLICE7_ICTLR_FIELDS_0_PVA0_ROW                  0
+
+#define SLICE7_ICTLR_FIELDS_0_RESERVED_235_SHIFT                        MK_SHIFT_CONST(11)
+#define SLICE7_ICTLR_FIELDS_0_RESERVED_235_FIELD                        MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_RESERVED_235_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_RESERVED_235_RANGE                        MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
+#define SLICE7_ICTLR_FIELDS_0_RESERVED_235_ROW                  0
+
+#define SLICE7_ICTLR_FIELDS_0_NVDLA0_SHIFT                      MK_SHIFT_CONST(12)
+#define SLICE7_ICTLR_FIELDS_0_NVDLA0_FIELD                      MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_NVDLA0_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_NVDLA0_RANGE                      MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
+#define SLICE7_ICTLR_FIELDS_0_NVDLA0_ROW                        0
+
+#define SLICE7_ICTLR_FIELDS_0_NVDLA1_SHIFT                      MK_SHIFT_CONST(13)
+#define SLICE7_ICTLR_FIELDS_0_NVDLA1_FIELD                      MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_NVDLA1_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_NVDLA1_RANGE                      MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
+#define SLICE7_ICTLR_FIELDS_0_NVDLA1_ROW                        0
+
+#define SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_NS_SHIFT                   MK_SHIFT_CONST(14)
+#define SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_NS_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_NS_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_NS_RANGE                   MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
+#define SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_NS_ROW                     0
+
+#define SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_S_SHIFT                    MK_SHIFT_CONST(15)
+#define SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_S_FIELD                    MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_S_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_S_RANGE                    MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define SLICE7_ICTLR_FIELDS_0_SMMU3_COMBINED_S_ROW                      0
+
+#define SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_NS_SHIFT                   MK_SHIFT_CONST(16)
+#define SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_NS_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_NS_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_NS_RANGE                   MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_NS_ROW                     0
+
+#define SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_S_SHIFT                    MK_SHIFT_CONST(17)
+#define SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_S_FIELD                    MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_S_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_S_RANGE                    MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define SLICE7_ICTLR_FIELDS_0_SMMU2_COMBINED_S_ROW                      0
+
+#define SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_NS_SHIFT                   MK_SHIFT_CONST(18)
+#define SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_NS_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_NS_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_NS_RANGE                   MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_NS_ROW                     0
+
+#define SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_S_SHIFT                    MK_SHIFT_CONST(19)
+#define SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_S_FIELD                    MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_S_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_S_RANGE                    MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define SLICE7_ICTLR_FIELDS_0_SMMU4_COMBINED_S_ROW                      0
+
+#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_5_SHIFT                   MK_SHIFT_CONST(20)
+#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_5_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_5_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_5_RANGE                   MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_5_ROW                     0
+
+#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_6_SHIFT                   MK_SHIFT_CONST(21)
+#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_6_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_6_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_6_RANGE                   MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_6_ROW                     0
+
+#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_7_SHIFT                   MK_SHIFT_CONST(22)
+#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_7_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_7_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_7_RANGE                   MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define SLICE7_ICTLR_FIELDS_0_TOP_HSP1_SHARED_7_ROW                     0
+
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_0_SHIFT                   MK_SHIFT_CONST(23)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_0_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_0_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_0_RANGE                   MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_0_ROW                     0
+
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_1_SHIFT                   MK_SHIFT_CONST(24)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_1_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_1_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_1_RANGE                   MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_1_ROW                     0
+
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_2_SHIFT                   MK_SHIFT_CONST(25)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_2_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_2_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_2_RANGE                   MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_2_ROW                     0
+
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_3_SHIFT                   MK_SHIFT_CONST(26)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_3_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_3_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_3_RANGE                   MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_3_ROW                     0
+
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_4_SHIFT                   MK_SHIFT_CONST(27)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_4_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_4_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_4_RANGE                   MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_4_ROW                     0
+
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_5_SHIFT                   MK_SHIFT_CONST(28)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_5_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_5_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_5_RANGE                   MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_5_ROW                     0
+
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_6_SHIFT                   MK_SHIFT_CONST(29)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_6_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_6_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_6_RANGE                   MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_6_ROW                     0
+
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_7_SHIFT                   MK_SHIFT_CONST(30)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_7_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_7_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_7_RANGE                   MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_7_ROW                     0
+
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_8_SHIFT                   MK_SHIFT_CONST(31)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_8_FIELD                   MK_FIELD_CONST(0x1, SLICE7_ICTLR_FIELDS_0_VI_VMID_8_SHIFT)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_8_RANGE                   MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
+#define SLICE7_ICTLR_FIELDS_0_VI_VMID_8_ROW                     0
+
+
+// Packet SLICE8_ICTLR_FIELDS_0
+#define SLICE8_ICTLR_FIELDS_0_SIZE 32
+
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_10_SHIFT                   MK_SHIFT_CONST(0)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_10_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_10_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_10_RANGE                   MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_10_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_11_SHIFT                   MK_SHIFT_CONST(1)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_11_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_11_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_11_RANGE                   MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_11_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_12_SHIFT                   MK_SHIFT_CONST(2)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_12_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_12_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_12_RANGE                   MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_12_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_13_SHIFT                   MK_SHIFT_CONST(3)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_13_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_13_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_13_RANGE                   MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_13_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_14_SHIFT                   MK_SHIFT_CONST(4)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_14_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_14_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_14_RANGE                   MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_14_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_15_SHIFT                   MK_SHIFT_CONST(5)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_15_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_15_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_15_RANGE                   MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define SLICE8_ICTLR_FIELDS_0_TOP_TKE_SHARED_15_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_RESERVED_262_SHIFT                        MK_SHIFT_CONST(6)
+#define SLICE8_ICTLR_FIELDS_0_RESERVED_262_FIELD                        MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_RESERVED_262_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_RESERVED_262_RANGE                        MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define SLICE8_ICTLR_FIELDS_0_RESERVED_262_ROW                  0
+
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_CPU_SHIFT                      MK_SHIFT_CONST(7)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_CPU_FIELD                      MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_CPU_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_CPU_RANGE                      MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_CPU_ROW                        0
+
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPU_SHIFT                   MK_SHIFT_CONST(8)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPU_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPU_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPU_RANGE                   MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CPU_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_0_SHIFT                   MK_SHIFT_CONST(9)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_0_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_0_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_0_RANGE                   MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_0_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_1_SHIFT                   MK_SHIFT_CONST(10)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_1_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_1_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_1_RANGE                   MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_1_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_2_SHIFT                   MK_SHIFT_CONST(11)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_2_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_2_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_2_RANGE                   MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_2_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_3_SHIFT                   MK_SHIFT_CONST(12)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_3_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_3_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_3_RANGE                   MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_3_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_4_SHIFT                   MK_SHIFT_CONST(13)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_4_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_4_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_4_RANGE                   MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_4_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_5_SHIFT                   MK_SHIFT_CONST(14)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_5_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_5_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_5_RANGE                   MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_5_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_6_SHIFT                   MK_SHIFT_CONST(15)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_6_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_6_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_6_RANGE                   MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_6_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_7_SHIFT                   MK_SHIFT_CONST(16)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_7_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_7_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_7_RANGE                   MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define SLICE8_ICTLR_FIELDS_0_TOP_HSP2_SHARED_7_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_GEN_CPU_SHIFT                   MK_SHIFT_CONST(17)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_GEN_CPU_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_GEN_CPU_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_GEN_CPU_RANGE                   MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_GEN_CPU_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_SYNCPT_CPU_SHIFT                        MK_SHIFT_CONST(18)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_SYNCPT_CPU_FIELD                        MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_SYNCPT_CPU_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_SYNCPT_CPU_RANGE                        MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_TZ_SYNCPT_CPU_ROW                  0
+
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_BPMP_SHIFT                     MK_SHIFT_CONST(19)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_BPMP_FIELD                     MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_BPMP_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_BPMP_RANGE                     MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_GEN_BPMP_ROW                       0
+
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_0_SHIFT                  MK_SHIFT_CONST(20)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_0_FIELD                  MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_0_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_0_RANGE                  MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_0_ROW                    0
+
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_1_SHIFT                  MK_SHIFT_CONST(21)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_1_FIELD                  MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_1_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_1_RANGE                  MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define SLICE8_ICTLR_FIELDS_0_HOST1X_SYNCPT_CAMERAPROC_1_ROW                    0
+
+#define SLICE8_ICTLR_FIELDS_0_RESERVED_278_SHIFT                        MK_SHIFT_CONST(22)
+#define SLICE8_ICTLR_FIELDS_0_RESERVED_278_FIELD                        MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_RESERVED_278_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_RESERVED_278_RANGE                        MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define SLICE8_ICTLR_FIELDS_0_RESERVED_278_ROW                  0
+
+#define SLICE8_ICTLR_FIELDS_0_CEC_SHIFT                 MK_SHIFT_CONST(23)
+#define SLICE8_ICTLR_FIELDS_0_CEC_FIELD                 MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_CEC_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_CEC_RANGE                 MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define SLICE8_ICTLR_FIELDS_0_CEC_ROW                   0
+
+#define SLICE8_ICTLR_FIELDS_0_VFMON_INTR_SHIFT                  MK_SHIFT_CONST(24)
+#define SLICE8_ICTLR_FIELDS_0_VFMON_INTR_FIELD                  MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_VFMON_INTR_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_VFMON_INTR_RANGE                  MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define SLICE8_ICTLR_FIELDS_0_VFMON_INTR_ROW                    0
+
+#define SLICE8_ICTLR_FIELDS_0_SE_APB_SHIFT                      MK_SHIFT_CONST(25)
+#define SLICE8_ICTLR_FIELDS_0_SE_APB_FIELD                      MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_SE_APB_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_SE_APB_RANGE                      MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define SLICE8_ICTLR_FIELDS_0_SE_APB_ROW                        0
+
+#define SLICE8_ICTLR_FIELDS_0_SE_HOST1X_SHIFT                   MK_SHIFT_CONST(26)
+#define SLICE8_ICTLR_FIELDS_0_SE_HOST1X_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_SE_HOST1X_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_SE_HOST1X_RANGE                   MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define SLICE8_ICTLR_FIELDS_0_SE_HOST1X_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_RESERVED_283_SHIFT                        MK_SHIFT_CONST(27)
+#define SLICE8_ICTLR_FIELDS_0_RESERVED_283_FIELD                        MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_RESERVED_283_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_RESERVED_283_RANGE                        MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define SLICE8_ICTLR_FIELDS_0_RESERVED_283_ROW                  0
+
+#define SLICE8_ICTLR_FIELDS_0_SE_ELPRNG_SHIFT                   MK_SHIFT_CONST(28)
+#define SLICE8_ICTLR_FIELDS_0_SE_ELPRNG_FIELD                   MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_SE_ELPRNG_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_SE_ELPRNG_RANGE                   MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define SLICE8_ICTLR_FIELDS_0_SE_ELPRNG_ROW                     0
+
+#define SLICE8_ICTLR_FIELDS_0_UARTI_SHIFT                       MK_SHIFT_CONST(29)
+#define SLICE8_ICTLR_FIELDS_0_UARTI_FIELD                       MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_UARTI_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_UARTI_RANGE                       MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
+#define SLICE8_ICTLR_FIELDS_0_UARTI_ROW                 0
+
+#define SLICE8_ICTLR_FIELDS_0_UARTJ_SHIFT                       MK_SHIFT_CONST(30)
+#define SLICE8_ICTLR_FIELDS_0_UARTJ_FIELD                       MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_UARTJ_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_UARTJ_RANGE                       MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
+#define SLICE8_ICTLR_FIELDS_0_UARTJ_ROW                 0
+
+#define SLICE8_ICTLR_FIELDS_0_RESERVED_287_SHIFT                        MK_SHIFT_CONST(31)
+#define SLICE8_ICTLR_FIELDS_0_RESERVED_287_FIELD                        MK_FIELD_CONST(0x1, SLICE8_ICTLR_FIELDS_0_RESERVED_287_SHIFT)
+#define SLICE8_ICTLR_FIELDS_0_RESERVED_287_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
+#define SLICE8_ICTLR_FIELDS_0_RESERVED_287_ROW                  0
+
+
+// Packet SLICE9_ICTLR_FIELDS_0
+#define SLICE9_ICTLR_FIELDS_0_SIZE 32
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_0_SHIFT                     MK_SHIFT_CONST(0)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_0_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO0_0_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_0_RANGE                     MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_0_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_1_SHIFT                     MK_SHIFT_CONST(1)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_1_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO0_1_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_1_RANGE                     MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_1_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_2_SHIFT                     MK_SHIFT_CONST(2)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_2_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO0_2_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_2_RANGE                     MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_2_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_3_SHIFT                     MK_SHIFT_CONST(3)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_3_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO0_3_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_3_RANGE                     MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_3_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_4_SHIFT                     MK_SHIFT_CONST(4)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_4_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO0_4_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_4_RANGE                     MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_4_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_5_SHIFT                     MK_SHIFT_CONST(5)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_5_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO0_5_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_5_RANGE                     MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_5_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_6_SHIFT                     MK_SHIFT_CONST(6)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_6_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO0_6_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_6_RANGE                     MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_6_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_7_SHIFT                     MK_SHIFT_CONST(7)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_7_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO0_7_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_7_RANGE                     MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define SLICE9_ICTLR_FIELDS_0_GPIO0_7_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_0_SHIFT                     MK_SHIFT_CONST(8)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_0_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO1_0_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_0_RANGE                     MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_0_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_1_SHIFT                     MK_SHIFT_CONST(9)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_1_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO1_1_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_1_RANGE                     MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_1_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_2_SHIFT                     MK_SHIFT_CONST(10)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_2_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO1_2_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_2_RANGE                     MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_2_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_3_SHIFT                     MK_SHIFT_CONST(11)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_3_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO1_3_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_3_RANGE                     MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_3_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_4_SHIFT                     MK_SHIFT_CONST(12)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_4_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO1_4_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_4_RANGE                     MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_4_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_5_SHIFT                     MK_SHIFT_CONST(13)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_5_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO1_5_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_5_RANGE                     MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_5_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_6_SHIFT                     MK_SHIFT_CONST(14)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_6_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO1_6_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_6_RANGE                     MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_6_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_7_SHIFT                     MK_SHIFT_CONST(15)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_7_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO1_7_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_7_RANGE                     MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define SLICE9_ICTLR_FIELDS_0_GPIO1_7_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_0_SHIFT                     MK_SHIFT_CONST(16)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_0_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO2_0_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_0_RANGE                     MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_0_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_1_SHIFT                     MK_SHIFT_CONST(17)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_1_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO2_1_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_1_RANGE                     MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_1_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_2_SHIFT                     MK_SHIFT_CONST(18)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_2_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO2_2_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_2_RANGE                     MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_2_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_3_SHIFT                     MK_SHIFT_CONST(19)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_3_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO2_3_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_3_RANGE                     MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_3_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_4_SHIFT                     MK_SHIFT_CONST(20)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_4_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO2_4_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_4_RANGE                     MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_4_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_5_SHIFT                     MK_SHIFT_CONST(21)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_5_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO2_5_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_5_RANGE                     MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_5_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_6_SHIFT                     MK_SHIFT_CONST(22)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_6_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO2_6_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_6_RANGE                     MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_6_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_7_SHIFT                     MK_SHIFT_CONST(23)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_7_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO2_7_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_7_RANGE                     MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define SLICE9_ICTLR_FIELDS_0_GPIO2_7_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_0_SHIFT                     MK_SHIFT_CONST(24)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_0_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO3_0_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_0_RANGE                     MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_0_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_1_SHIFT                     MK_SHIFT_CONST(25)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_1_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO3_1_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_1_RANGE                     MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_1_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_2_SHIFT                     MK_SHIFT_CONST(26)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_2_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO3_2_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_2_RANGE                     MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_2_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_3_SHIFT                     MK_SHIFT_CONST(27)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_3_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO3_3_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_3_RANGE                     MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_3_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_4_SHIFT                     MK_SHIFT_CONST(28)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_4_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO3_4_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_4_RANGE                     MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_4_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_5_SHIFT                     MK_SHIFT_CONST(29)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_5_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO3_5_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_5_RANGE                     MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_5_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_6_SHIFT                     MK_SHIFT_CONST(30)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_6_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO3_6_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_6_RANGE                     MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_6_ROW                       0
+
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_7_SHIFT                     MK_SHIFT_CONST(31)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_7_FIELD                     MK_FIELD_CONST(0x1, SLICE9_ICTLR_FIELDS_0_GPIO3_7_SHIFT)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_7_RANGE                     MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
+#define SLICE9_ICTLR_FIELDS_0_GPIO3_7_ROW                       0
+
+
+// Packet SLICE10_ICTLR_FIELDS_0
+#define SLICE10_ICTLR_FIELDS_0_SIZE 32
+
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_0_SHIFT                    MK_SHIFT_CONST(0)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_0_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO4_0_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_0_RANGE                    MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_0_ROW                      0
+
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_1_SHIFT                    MK_SHIFT_CONST(1)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_1_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO4_1_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_1_RANGE                    MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_1_ROW                      0
+
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_2_SHIFT                    MK_SHIFT_CONST(2)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_2_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO4_2_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_2_RANGE                    MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_2_ROW                      0
+
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_3_SHIFT                    MK_SHIFT_CONST(3)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_3_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO4_3_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_3_RANGE                    MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_3_ROW                      0
+
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_4_SHIFT                    MK_SHIFT_CONST(4)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_4_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO4_4_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_4_RANGE                    MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_4_ROW                      0
+
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_5_SHIFT                    MK_SHIFT_CONST(5)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_5_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO4_5_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_5_RANGE                    MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_5_ROW                      0
+
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_6_SHIFT                    MK_SHIFT_CONST(6)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_6_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO4_6_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_6_RANGE                    MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_6_ROW                      0
+
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_7_SHIFT                    MK_SHIFT_CONST(7)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_7_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO4_7_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_7_RANGE                    MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define SLICE10_ICTLR_FIELDS_0_GPIO4_7_ROW                      0
+
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_0_SHIFT                    MK_SHIFT_CONST(8)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_0_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO5_0_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_0_RANGE                    MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_0_ROW                      0
+
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_1_SHIFT                    MK_SHIFT_CONST(9)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_1_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO5_1_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_1_RANGE                    MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_1_ROW                      0
+
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_2_SHIFT                    MK_SHIFT_CONST(10)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_2_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO5_2_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_2_RANGE                    MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_2_ROW                      0
+
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_3_SHIFT                    MK_SHIFT_CONST(11)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_3_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO5_3_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_3_RANGE                    MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_3_ROW                      0
+
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_4_SHIFT                    MK_SHIFT_CONST(12)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_4_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO5_4_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_4_RANGE                    MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_4_ROW                      0
+
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_5_SHIFT                    MK_SHIFT_CONST(13)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_5_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO5_5_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_5_RANGE                    MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_5_ROW                      0
+
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_6_SHIFT                    MK_SHIFT_CONST(14)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_6_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO5_6_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_6_RANGE                    MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_6_ROW                      0
+
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_7_SHIFT                    MK_SHIFT_CONST(15)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_7_FIELD                    MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_GPIO5_7_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_7_RANGE                    MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define SLICE10_ICTLR_FIELDS_0_GPIO5_7_ROW                      0
+
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L0_P2U_SW_SHIFT                     MK_SHIFT_CONST(16)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L0_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX0_L0_P2U_SW_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L0_P2U_SW_RANGE                     MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L0_P2U_SW_ROW                       0
+
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L1_P2U_SW_SHIFT                     MK_SHIFT_CONST(17)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L1_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX0_L1_P2U_SW_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L1_P2U_SW_RANGE                     MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L1_P2U_SW_ROW                       0
+
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L2_P2U_SW_SHIFT                     MK_SHIFT_CONST(18)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L2_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX0_L2_P2U_SW_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L2_P2U_SW_RANGE                     MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L2_P2U_SW_ROW                       0
+
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L3_P2U_SW_SHIFT                     MK_SHIFT_CONST(19)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L3_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX0_L3_P2U_SW_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L3_P2U_SW_RANGE                     MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L3_P2U_SW_ROW                       0
+
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L4_P2U_SW_SHIFT                     MK_SHIFT_CONST(20)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L4_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX0_L4_P2U_SW_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L4_P2U_SW_RANGE                     MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L4_P2U_SW_ROW                       0
+
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L5_P2U_SW_SHIFT                     MK_SHIFT_CONST(21)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L5_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX0_L5_P2U_SW_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L5_P2U_SW_RANGE                     MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L5_P2U_SW_ROW                       0
+
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L6_P2U_SW_SHIFT                     MK_SHIFT_CONST(22)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L6_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX0_L6_P2U_SW_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L6_P2U_SW_RANGE                     MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L6_P2U_SW_ROW                       0
+
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L7_P2U_SW_SHIFT                     MK_SHIFT_CONST(23)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L7_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX0_L7_P2U_SW_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L7_P2U_SW_RANGE                     MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define SLICE10_ICTLR_FIELDS_0_PEX0_L7_P2U_SW_ROW                       0
+
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L0_P2U_SW_SHIFT                     MK_SHIFT_CONST(24)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L0_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX1_L0_P2U_SW_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L0_P2U_SW_RANGE                     MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L0_P2U_SW_ROW                       0
+
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L1_P2U_SW_SHIFT                     MK_SHIFT_CONST(25)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L1_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX1_L1_P2U_SW_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L1_P2U_SW_RANGE                     MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L1_P2U_SW_ROW                       0
+
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L2_P2U_SW_SHIFT                     MK_SHIFT_CONST(26)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L2_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX1_L2_P2U_SW_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L2_P2U_SW_RANGE                     MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L2_P2U_SW_ROW                       0
+
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L3_P2U_SW_SHIFT                     MK_SHIFT_CONST(27)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L3_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX1_L3_P2U_SW_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L3_P2U_SW_RANGE                     MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L3_P2U_SW_ROW                       0
+
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L4_P2U_SW_SHIFT                     MK_SHIFT_CONST(28)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L4_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX1_L4_P2U_SW_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L4_P2U_SW_RANGE                     MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L4_P2U_SW_ROW                       0
+
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L5_P2U_SW_SHIFT                     MK_SHIFT_CONST(29)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L5_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX1_L5_P2U_SW_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L5_P2U_SW_RANGE                     MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L5_P2U_SW_ROW                       0
+
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L6_P2U_SW_SHIFT                     MK_SHIFT_CONST(30)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L6_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX1_L6_P2U_SW_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L6_P2U_SW_RANGE                     MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L6_P2U_SW_ROW                       0
+
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L7_P2U_SW_SHIFT                     MK_SHIFT_CONST(31)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L7_P2U_SW_FIELD                     MK_FIELD_CONST(0x1, SLICE10_ICTLR_FIELDS_0_PEX1_L7_P2U_SW_SHIFT)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L7_P2U_SW_RANGE                     MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
+#define SLICE10_ICTLR_FIELDS_0_PEX1_L7_P2U_SW_ROW                       0
+
+
+// Packet SLICE11_ICTLR_FIELDS_0
+#define SLICE11_ICTLR_FIELDS_0_SIZE 32
+
+#define SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_0_SHIFT                      MK_SHIFT_CONST(0)
+#define SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_0_FIELD                      MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_0_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_0_RANGE                      MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_0_ROW                        0
+
+#define SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_1_SHIFT                      MK_SHIFT_CONST(1)
+#define SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_1_FIELD                      MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_1_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_1_RANGE                      MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define SLICE11_ICTLR_FIELDS_0_PEX1_C6_SYS_1_ROW                        0
+
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_0_SHIFT                      MK_SHIFT_CONST(2)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_0_FIELD                      MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_0_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_0_RANGE                      MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_0_ROW                        0
+
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_1_SHIFT                      MK_SHIFT_CONST(3)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_1_FIELD                      MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_1_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_1_RANGE                      MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C7_SYS_1_ROW                        0
+
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_0_SHIFT                      MK_SHIFT_CONST(4)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_0_FIELD                      MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_0_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_0_RANGE                      MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_0_ROW                        0
+
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_1_SHIFT                      MK_SHIFT_CONST(5)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_1_FIELD                      MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_1_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_1_RANGE                      MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C8_SYS_1_ROW                        0
+
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_0_SHIFT                      MK_SHIFT_CONST(6)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_0_FIELD                      MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_0_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_0_RANGE                      MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_0_ROW                        0
+
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_1_SHIFT                      MK_SHIFT_CONST(7)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_1_FIELD                      MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_1_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_1_RANGE                      MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C9_SYS_1_ROW                        0
+
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_0_SHIFT                     MK_SHIFT_CONST(8)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_0_FIELD                     MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_0_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_0_RANGE                     MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_0_ROW                       0
+
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_1_SHIFT                     MK_SHIFT_CONST(9)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_1_FIELD                     MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_1_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_1_RANGE                     MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
+#define SLICE11_ICTLR_FIELDS_0_PEX2_C10_SYS_1_ROW                       0
+
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB0_SHIFT                    MK_SHIFT_CONST(10)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB0_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB0_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB0_RANGE                    MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB0_ROW                      0
+
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB1_SHIFT                    MK_SHIFT_CONST(11)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB1_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB1_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB1_RANGE                    MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB1_ROW                      0
+
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB2_SHIFT                    MK_SHIFT_CONST(12)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB2_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB2_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB2_RANGE                    MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB2_ROW                      0
+
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB3_SHIFT                    MK_SHIFT_CONST(13)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB3_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB3_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB3_RANGE                    MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB3_ROW                      0
+
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB4_SHIFT                    MK_SHIFT_CONST(14)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB4_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB4_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB4_RANGE                    MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB4_ROW                      0
+
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB5_SHIFT                    MK_SHIFT_CONST(15)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB5_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB5_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB5_RANGE                    MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB5_ROW                      0
+
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB6_SHIFT                    MK_SHIFT_CONST(16)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB6_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB6_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB6_RANGE                    MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB6_ROW                      0
+
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB7_SHIFT                    MK_SHIFT_CONST(17)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB7_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB7_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB7_RANGE                    MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB7_ROW                      0
+
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB8_SHIFT                    MK_SHIFT_CONST(18)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB8_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB8_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB8_RANGE                    MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB8_ROW                      0
+
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB9_SHIFT                    MK_SHIFT_CONST(19)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB9_FIELD                    MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB9_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB9_RANGE                    MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB9_ROW                      0
+
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB10_SHIFT                   MK_SHIFT_CONST(20)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB10_FIELD                   MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB10_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB10_RANGE                   MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB10_ROW                     0
+
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB11_SHIFT                   MK_SHIFT_CONST(21)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB11_FIELD                   MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_PSC_MB11_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB11_RANGE                   MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define SLICE11_ICTLR_FIELDS_0_PSC_MB11_ROW                     0
+
+#define SLICE11_ICTLR_FIELDS_0_RESERVED_374_SHIFT                       MK_SHIFT_CONST(22)
+#define SLICE11_ICTLR_FIELDS_0_RESERVED_374_FIELD                       MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_RESERVED_374_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_RESERVED_374_RANGE                       MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define SLICE11_ICTLR_FIELDS_0_RESERVED_374_ROW                 0
+
+#define SLICE11_ICTLR_FIELDS_0_RESERVED_375_SHIFT                       MK_SHIFT_CONST(23)
+#define SLICE11_ICTLR_FIELDS_0_RESERVED_375_FIELD                       MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_RESERVED_375_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_RESERVED_375_RANGE                       MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define SLICE11_ICTLR_FIELDS_0_RESERVED_375_ROW                 0
+
+#define SLICE11_ICTLR_FIELDS_0_DCE_WDT_REMOTE_SHIFT                     MK_SHIFT_CONST(24)
+#define SLICE11_ICTLR_FIELDS_0_DCE_WDT_REMOTE_FIELD                     MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_DCE_WDT_REMOTE_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_DCE_WDT_REMOTE_RANGE                     MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define SLICE11_ICTLR_FIELDS_0_DCE_WDT_REMOTE_ROW                       0
+
+#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_0_SHIFT                     MK_SHIFT_CONST(25)
+#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_0_FIELD                     MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_0_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_0_RANGE                     MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_0_ROW                       0
+
+#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_1_SHIFT                     MK_SHIFT_CONST(26)
+#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_1_FIELD                     MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_1_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_1_RANGE                     MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_1_ROW                       0
+
+#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_2_SHIFT                     MK_SHIFT_CONST(27)
+#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_2_FIELD                     MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_2_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_2_RANGE                     MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_2_ROW                       0
+
+#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_3_SHIFT                     MK_SHIFT_CONST(28)
+#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_3_FIELD                     MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_3_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_3_RANGE                     MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define SLICE11_ICTLR_FIELDS_0_DCE_MBOX_OUT_3_ROW                       0
+
+#define SLICE11_ICTLR_FIELDS_0_SECURE_DCE_FABRIC_SHIFT                  MK_SHIFT_CONST(29)
+#define SLICE11_ICTLR_FIELDS_0_SECURE_DCE_FABRIC_FIELD                  MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_SECURE_DCE_FABRIC_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_SECURE_DCE_FABRIC_RANGE                  MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
+#define SLICE11_ICTLR_FIELDS_0_SECURE_DCE_FABRIC_ROW                    0
+
+#define SLICE11_ICTLR_FIELDS_0_RESERVED_382_SHIFT                       MK_SHIFT_CONST(30)
+#define SLICE11_ICTLR_FIELDS_0_RESERVED_382_FIELD                       MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_RESERVED_382_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_RESERVED_382_RANGE                       MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
+#define SLICE11_ICTLR_FIELDS_0_RESERVED_382_ROW                 0
+
+#define SLICE11_ICTLR_FIELDS_0_RESERVED_383_SHIFT                       MK_SHIFT_CONST(31)
+#define SLICE11_ICTLR_FIELDS_0_RESERVED_383_FIELD                       MK_FIELD_CONST(0x1, SLICE11_ICTLR_FIELDS_0_RESERVED_383_SHIFT)
+#define SLICE11_ICTLR_FIELDS_0_RESERVED_383_RANGE                       MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
+#define SLICE11_ICTLR_FIELDS_0_RESERVED_383_ROW                 0
+
+
+// Packet SLICE12_ICTLR_FIELDS_0
+#define SLICE12_ICTLR_FIELDS_0_SIZE 32
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_COMMON_SHIFT                       MK_SHIFT_CONST(0)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_COMMON_FIELD                       MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE0_COMMON_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_COMMON_RANGE                       MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_COMMON_ROW                 0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_0_SHIFT                 MK_SHIFT_CONST(1)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_0_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE0_VM_0_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_0_RANGE                 MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_0_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_1_SHIFT                 MK_SHIFT_CONST(2)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_1_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE0_VM_1_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_1_RANGE                 MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_1_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_2_SHIFT                 MK_SHIFT_CONST(3)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_2_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE0_VM_2_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_2_RANGE                 MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_2_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_3_SHIFT                 MK_SHIFT_CONST(4)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_3_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE0_VM_3_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_3_RANGE                 MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_3_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_4_SHIFT                 MK_SHIFT_CONST(5)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_4_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE0_VM_4_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_4_RANGE                 MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_VM_4_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_NON_SECURE_SHIFT                    MK_SHIFT_CONST(6)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_NON_SECURE_FIELD                    MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_NON_SECURE_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_NON_SECURE_RANGE                    MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_NON_SECURE_ROW                      0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_SECURE_SHIFT                        MK_SHIFT_CONST(7)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_SECURE_FIELD                        MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_SECURE_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_SECURE_RANGE                        MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define SLICE12_ICTLR_FIELDS_0_MGBE0_MACSEC_SECURE_ROW                  0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_COMMON_SHIFT                       MK_SHIFT_CONST(8)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_COMMON_FIELD                       MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE1_COMMON_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_COMMON_RANGE                       MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_COMMON_ROW                 0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_0_SHIFT                 MK_SHIFT_CONST(9)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_0_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE1_VM_0_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_0_RANGE                 MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_0_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_1_SHIFT                 MK_SHIFT_CONST(10)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_1_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE1_VM_1_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_1_RANGE                 MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_1_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_2_SHIFT                 MK_SHIFT_CONST(11)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_2_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE1_VM_2_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_2_RANGE                 MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_2_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_3_SHIFT                 MK_SHIFT_CONST(12)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_3_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE1_VM_3_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_3_RANGE                 MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_3_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_4_SHIFT                 MK_SHIFT_CONST(13)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_4_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE1_VM_4_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_4_RANGE                 MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_VM_4_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_NON_SECURE_SHIFT                    MK_SHIFT_CONST(14)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_NON_SECURE_FIELD                    MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_NON_SECURE_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_NON_SECURE_RANGE                    MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_NON_SECURE_ROW                      0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_SECURE_SHIFT                        MK_SHIFT_CONST(15)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_SECURE_FIELD                        MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_SECURE_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_SECURE_RANGE                        MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define SLICE12_ICTLR_FIELDS_0_MGBE1_MACSEC_SECURE_ROW                  0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_COMMON_SHIFT                       MK_SHIFT_CONST(16)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_COMMON_FIELD                       MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE2_COMMON_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_COMMON_RANGE                       MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_COMMON_ROW                 0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_0_SHIFT                 MK_SHIFT_CONST(17)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_0_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE2_VM_0_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_0_RANGE                 MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_0_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_1_SHIFT                 MK_SHIFT_CONST(18)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_1_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE2_VM_1_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_1_RANGE                 MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_1_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_2_SHIFT                 MK_SHIFT_CONST(19)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_2_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE2_VM_2_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_2_RANGE                 MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_2_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_3_SHIFT                 MK_SHIFT_CONST(20)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_3_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE2_VM_3_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_3_RANGE                 MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_3_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_4_SHIFT                 MK_SHIFT_CONST(21)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_4_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE2_VM_4_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_4_RANGE                 MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_VM_4_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_NON_SECURE_SHIFT                    MK_SHIFT_CONST(22)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_NON_SECURE_FIELD                    MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_NON_SECURE_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_NON_SECURE_RANGE                    MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_NON_SECURE_ROW                      0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_SECURE_SHIFT                        MK_SHIFT_CONST(23)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_SECURE_FIELD                        MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_SECURE_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_SECURE_RANGE                        MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define SLICE12_ICTLR_FIELDS_0_MGBE2_MACSEC_SECURE_ROW                  0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_COMMON_SHIFT                       MK_SHIFT_CONST(24)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_COMMON_FIELD                       MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE3_COMMON_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_COMMON_RANGE                       MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_COMMON_ROW                 0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_0_SHIFT                 MK_SHIFT_CONST(25)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_0_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE3_VM_0_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_0_RANGE                 MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_0_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_1_SHIFT                 MK_SHIFT_CONST(26)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_1_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE3_VM_1_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_1_RANGE                 MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_1_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_2_SHIFT                 MK_SHIFT_CONST(27)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_2_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE3_VM_2_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_2_RANGE                 MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_2_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_3_SHIFT                 MK_SHIFT_CONST(28)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_3_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE3_VM_3_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_3_RANGE                 MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_3_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_4_SHIFT                 MK_SHIFT_CONST(29)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_4_FIELD                 MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE3_VM_4_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_4_RANGE                 MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_VM_4_ROW                   0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_NON_SECURE_SHIFT                    MK_SHIFT_CONST(30)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_NON_SECURE_FIELD                    MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_NON_SECURE_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_NON_SECURE_RANGE                    MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_NON_SECURE_ROW                      0
+
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_SECURE_SHIFT                        MK_SHIFT_CONST(31)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_SECURE_FIELD                        MK_FIELD_CONST(0x1, SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_SECURE_SHIFT)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_SECURE_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
+#define SLICE12_ICTLR_FIELDS_0_MGBE3_MACSEC_SECURE_ROW                  0
+
+
+// Packet SLICE13_ICTLR_FIELDS_0
+#define SLICE13_ICTLR_FIELDS_0_SIZE 32
+
+#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2HOST_SHIFT                      MK_SHIFT_CONST(0)
+#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2HOST_FIELD                      MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_DISPLAY_2HOST_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2HOST_RANGE                      MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2HOST_ROW                        0
+
+#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2GSP_SHIFT                       MK_SHIFT_CONST(1)
+#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2GSP_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_DISPLAY_2GSP_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2GSP_RANGE                       MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2GSP_ROW                 0
+
+#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2PMU_SHIFT                       MK_SHIFT_CONST(2)
+#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2PMU_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_DISPLAY_2PMU_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2PMU_RANGE                       MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
+#define SLICE13_ICTLR_FIELDS_0_DISPLAY_2PMU_ROW                 0
+
+#define SLICE13_ICTLR_FIELDS_0_DPAUX0_SHIFT                     MK_SHIFT_CONST(3)
+#define SLICE13_ICTLR_FIELDS_0_DPAUX0_FIELD                     MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_DPAUX0_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_DPAUX0_RANGE                     MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define SLICE13_ICTLR_FIELDS_0_DPAUX0_ROW                       0
+
+#define SLICE13_ICTLR_FIELDS_0_RESERVED_420_SHIFT                       MK_SHIFT_CONST(4)
+#define SLICE13_ICTLR_FIELDS_0_RESERVED_420_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_RESERVED_420_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_RESERVED_420_RANGE                       MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define SLICE13_ICTLR_FIELDS_0_RESERVED_420_ROW                 0
+
+#define SLICE13_ICTLR_FIELDS_0_RESERVED_421_SHIFT                       MK_SHIFT_CONST(5)
+#define SLICE13_ICTLR_FIELDS_0_RESERVED_421_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_RESERVED_421_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_RESERVED_421_RANGE                       MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define SLICE13_ICTLR_FIELDS_0_RESERVED_421_ROW                 0
+
+#define SLICE13_ICTLR_FIELDS_0_RESERVED_422_SHIFT                       MK_SHIFT_CONST(6)
+#define SLICE13_ICTLR_FIELDS_0_RESERVED_422_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_RESERVED_422_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_RESERVED_422_RANGE                       MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define SLICE13_ICTLR_FIELDS_0_RESERVED_422_ROW                 0
+
+#define SLICE13_ICTLR_FIELDS_0_SE1_APB_SHIFT                    MK_SHIFT_CONST(7)
+#define SLICE13_ICTLR_FIELDS_0_SE1_APB_FIELD                    MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_SE1_APB_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_SE1_APB_RANGE                    MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define SLICE13_ICTLR_FIELDS_0_SE1_APB_ROW                      0
+
+#define SLICE13_ICTLR_FIELDS_0_SE1_HOST1X_SHIFT                 MK_SHIFT_CONST(8)
+#define SLICE13_ICTLR_FIELDS_0_SE1_HOST1X_FIELD                 MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_SE1_HOST1X_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_SE1_HOST1X_RANGE                 MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
+#define SLICE13_ICTLR_FIELDS_0_SE1_HOST1X_ROW                   0
+
+#define SLICE13_ICTLR_FIELDS_0_SE1_ELPPKA_SHIFT                 MK_SHIFT_CONST(9)
+#define SLICE13_ICTLR_FIELDS_0_SE1_ELPPKA_FIELD                 MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_SE1_ELPPKA_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_SE1_ELPPKA_RANGE                 MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
+#define SLICE13_ICTLR_FIELDS_0_SE1_ELPPKA_ROW                   0
+
+#define SLICE13_ICTLR_FIELDS_0_SE1_ELPRNG_SHIFT                 MK_SHIFT_CONST(10)
+#define SLICE13_ICTLR_FIELDS_0_SE1_ELPRNG_FIELD                 MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_SE1_ELPRNG_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_SE1_ELPRNG_RANGE                 MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define SLICE13_ICTLR_FIELDS_0_SE1_ELPRNG_ROW                   0
+
+#define SLICE13_ICTLR_FIELDS_0_RESERVED_427_SHIFT                       MK_SHIFT_CONST(11)
+#define SLICE13_ICTLR_FIELDS_0_RESERVED_427_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_RESERVED_427_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_RESERVED_427_RANGE                       MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
+#define SLICE13_ICTLR_FIELDS_0_RESERVED_427_ROW                 0
+
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTA_SHIFT                       MK_SHIFT_CONST(12)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTA_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTA_RANGE                       MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTA_ROW                 0
+
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTB_SHIFT                       MK_SHIFT_CONST(13)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTB_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTB_RANGE                       MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTB_ROW                 0
+
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTC_SHIFT                       MK_SHIFT_CONST(14)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTC_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTC_RANGE                       MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTC_ROW                 0
+
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTD_SHIFT                       MK_SHIFT_CONST(15)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTD_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTD_RANGE                       MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C8_INTD_ROW                 0
+
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_0_SHIFT                  MK_SHIFT_CONST(16)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_0_FIELD                  MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PVA0_VM_0_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_0_RANGE                  MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_0_ROW                    0
+
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_1_SHIFT                  MK_SHIFT_CONST(17)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_1_FIELD                  MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PVA0_VM_1_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_1_RANGE                  MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_1_ROW                    0
+
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_2_SHIFT                  MK_SHIFT_CONST(18)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_2_FIELD                  MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PVA0_VM_2_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_2_RANGE                  MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_2_ROW                    0
+
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_3_SHIFT                  MK_SHIFT_CONST(19)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_3_FIELD                  MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PVA0_VM_3_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_3_RANGE                  MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_3_ROW                    0
+
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_4_SHIFT                  MK_SHIFT_CONST(20)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_4_FIELD                  MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PVA0_VM_4_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_4_RANGE                  MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_4_ROW                    0
+
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_5_SHIFT                  MK_SHIFT_CONST(21)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_5_FIELD                  MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PVA0_VM_5_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_5_RANGE                  MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_5_ROW                    0
+
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_6_SHIFT                  MK_SHIFT_CONST(22)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_6_FIELD                  MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PVA0_VM_6_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_6_RANGE                  MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_6_ROW                    0
+
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_7_SHIFT                  MK_SHIFT_CONST(23)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_7_FIELD                  MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PVA0_VM_7_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_7_RANGE                  MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define SLICE13_ICTLR_FIELDS_0_PVA0_VM_7_ROW                    0
+
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTA_SHIFT                       MK_SHIFT_CONST(24)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTA_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTA_RANGE                       MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTA_ROW                 0
+
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTB_SHIFT                       MK_SHIFT_CONST(25)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTB_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTB_RANGE                       MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTB_ROW                 0
+
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTC_SHIFT                       MK_SHIFT_CONST(26)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTC_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTC_RANGE                       MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTC_ROW                 0
+
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTD_SHIFT                       MK_SHIFT_CONST(27)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTD_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTD_RANGE                       MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C9_INTD_ROW                 0
+
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTA_SHIFT                      MK_SHIFT_CONST(28)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTA_FIELD                      MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTA_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTA_RANGE                      MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTA_ROW                        0
+
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTB_SHIFT                      MK_SHIFT_CONST(29)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTB_FIELD                      MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTB_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTB_RANGE                      MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTB_ROW                        0
+
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTC_SHIFT                      MK_SHIFT_CONST(30)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTC_FIELD                      MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTC_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTC_RANGE                      MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTC_ROW                        0
+
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTD_SHIFT                      MK_SHIFT_CONST(31)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTD_FIELD                      MK_FIELD_CONST(0x1, SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTD_SHIFT)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTD_RANGE                      MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
+#define SLICE13_ICTLR_FIELDS_0_PEX2_C10_INTD_ROW                        0
+
+
+// Packet SLICE14_ICTLR_FIELDS_0
+#define SLICE14_ICTLR_FIELDS_0_SIZE 32
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_0_SYNCPT_SHIFT                        MK_SHIFT_CONST(0)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_0_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_0_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_0_SYNCPT_RANGE                        MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_0_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_1_SYNCPT_SHIFT                        MK_SHIFT_CONST(1)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_1_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_1_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_1_SYNCPT_RANGE                        MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_1_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_2_SYNCPT_SHIFT                        MK_SHIFT_CONST(2)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_2_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_2_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_2_SYNCPT_RANGE                        MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_2_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_3_SYNCPT_SHIFT                        MK_SHIFT_CONST(3)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_3_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_3_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_3_SYNCPT_RANGE                        MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_3_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_4_SYNCPT_SHIFT                        MK_SHIFT_CONST(4)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_4_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_4_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_4_SYNCPT_RANGE                        MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_4_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_5_SYNCPT_SHIFT                        MK_SHIFT_CONST(5)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_5_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_5_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_5_SYNCPT_RANGE                        MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_5_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_6_SYNCPT_SHIFT                        MK_SHIFT_CONST(6)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_6_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_6_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_6_SYNCPT_RANGE                        MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_6_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_7_SYNCPT_SHIFT                        MK_SHIFT_CONST(7)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_7_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_7_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_7_SYNCPT_RANGE                        MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM1_7_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_0_SYNCPT_SHIFT                        MK_SHIFT_CONST(8)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_0_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_0_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_0_SYNCPT_RANGE                        MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_0_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_1_SYNCPT_SHIFT                        MK_SHIFT_CONST(9)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_1_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_1_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_1_SYNCPT_RANGE                        MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_1_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_2_SYNCPT_SHIFT                        MK_SHIFT_CONST(10)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_2_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_2_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_2_SYNCPT_RANGE                        MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_2_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_3_SYNCPT_SHIFT                        MK_SHIFT_CONST(11)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_3_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_3_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_3_SYNCPT_RANGE                        MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_3_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_4_SYNCPT_SHIFT                        MK_SHIFT_CONST(12)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_4_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_4_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_4_SYNCPT_RANGE                        MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_4_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_5_SYNCPT_SHIFT                        MK_SHIFT_CONST(13)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_5_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_5_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_5_SYNCPT_RANGE                        MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_5_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_6_SYNCPT_SHIFT                        MK_SHIFT_CONST(14)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_6_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_6_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_6_SYNCPT_RANGE                        MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_6_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_7_SYNCPT_SHIFT                        MK_SHIFT_CONST(15)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_7_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_7_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_7_SYNCPT_RANGE                        MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM2_7_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_0_SYNCPT_SHIFT                        MK_SHIFT_CONST(16)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_0_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_0_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_0_SYNCPT_RANGE                        MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_0_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_1_SYNCPT_SHIFT                        MK_SHIFT_CONST(17)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_1_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_1_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_1_SYNCPT_RANGE                        MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_1_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_2_SYNCPT_SHIFT                        MK_SHIFT_CONST(18)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_2_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_2_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_2_SYNCPT_RANGE                        MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_2_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_3_SYNCPT_SHIFT                        MK_SHIFT_CONST(19)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_3_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_3_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_3_SYNCPT_RANGE                        MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_3_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_4_SYNCPT_SHIFT                        MK_SHIFT_CONST(20)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_4_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_4_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_4_SYNCPT_RANGE                        MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_4_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_5_SYNCPT_SHIFT                        MK_SHIFT_CONST(21)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_5_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_5_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_5_SYNCPT_RANGE                        MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_5_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_6_SYNCPT_SHIFT                        MK_SHIFT_CONST(22)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_6_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_6_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_6_SYNCPT_RANGE                        MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_6_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_7_SYNCPT_SHIFT                        MK_SHIFT_CONST(23)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_7_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_7_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_7_SYNCPT_RANGE                        MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM3_7_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_0_SYNCPT_SHIFT                        MK_SHIFT_CONST(24)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_0_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_0_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_0_SYNCPT_RANGE                        MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_0_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_1_SYNCPT_SHIFT                        MK_SHIFT_CONST(25)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_1_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_1_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_1_SYNCPT_RANGE                        MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_1_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_2_SYNCPT_SHIFT                        MK_SHIFT_CONST(26)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_2_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_2_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_2_SYNCPT_RANGE                        MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_2_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_3_SYNCPT_SHIFT                        MK_SHIFT_CONST(27)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_3_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_3_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_3_SYNCPT_RANGE                        MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_3_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_4_SYNCPT_SHIFT                        MK_SHIFT_CONST(28)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_4_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_4_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_4_SYNCPT_RANGE                        MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_4_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_5_SYNCPT_SHIFT                        MK_SHIFT_CONST(29)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_5_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_5_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_5_SYNCPT_RANGE                        MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_5_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_6_SYNCPT_SHIFT                        MK_SHIFT_CONST(30)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_6_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_6_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_6_SYNCPT_RANGE                        MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_6_SYNCPT_ROW                  0
+
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_7_SYNCPT_SHIFT                        MK_SHIFT_CONST(31)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_7_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_7_SYNCPT_SHIFT)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_7_SYNCPT_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
+#define SLICE14_ICTLR_FIELDS_0_HOST1X2VM4_7_SYNCPT_ROW                  0
+
+
+// Packet SLICE15_ICTLR_FIELDS_0
+#define SLICE15_ICTLR_FIELDS_0_SIZE 32
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_0_SYNCPT_SHIFT                        MK_SHIFT_CONST(0)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_0_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_0_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_0_SYNCPT_RANGE                        MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_0_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_1_SYNCPT_SHIFT                        MK_SHIFT_CONST(1)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_1_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_1_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_1_SYNCPT_RANGE                        MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_1_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_2_SYNCPT_SHIFT                        MK_SHIFT_CONST(2)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_2_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_2_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_2_SYNCPT_RANGE                        MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_2_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_3_SYNCPT_SHIFT                        MK_SHIFT_CONST(3)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_3_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_3_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_3_SYNCPT_RANGE                        MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_3_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_4_SYNCPT_SHIFT                        MK_SHIFT_CONST(4)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_4_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_4_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_4_SYNCPT_RANGE                        MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_4_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_5_SYNCPT_SHIFT                        MK_SHIFT_CONST(5)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_5_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_5_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_5_SYNCPT_RANGE                        MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_5_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_6_SYNCPT_SHIFT                        MK_SHIFT_CONST(6)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_6_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_6_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_6_SYNCPT_RANGE                        MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_6_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_7_SYNCPT_SHIFT                        MK_SHIFT_CONST(7)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_7_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_7_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_7_SYNCPT_RANGE                        MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM5_7_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_0_SYNCPT_SHIFT                        MK_SHIFT_CONST(8)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_0_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_0_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_0_SYNCPT_RANGE                        MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_0_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_1_SYNCPT_SHIFT                        MK_SHIFT_CONST(9)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_1_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_1_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_1_SYNCPT_RANGE                        MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_1_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_2_SYNCPT_SHIFT                        MK_SHIFT_CONST(10)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_2_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_2_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_2_SYNCPT_RANGE                        MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_2_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_3_SYNCPT_SHIFT                        MK_SHIFT_CONST(11)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_3_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_3_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_3_SYNCPT_RANGE                        MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_3_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_4_SYNCPT_SHIFT                        MK_SHIFT_CONST(12)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_4_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_4_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_4_SYNCPT_RANGE                        MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_4_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_5_SYNCPT_SHIFT                        MK_SHIFT_CONST(13)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_5_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_5_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_5_SYNCPT_RANGE                        MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_5_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_6_SYNCPT_SHIFT                        MK_SHIFT_CONST(14)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_6_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_6_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_6_SYNCPT_RANGE                        MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_6_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_7_SYNCPT_SHIFT                        MK_SHIFT_CONST(15)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_7_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_7_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_7_SYNCPT_RANGE                        MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM6_7_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_0_SYNCPT_SHIFT                        MK_SHIFT_CONST(16)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_0_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_0_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_0_SYNCPT_RANGE                        MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_0_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_1_SYNCPT_SHIFT                        MK_SHIFT_CONST(17)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_1_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_1_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_1_SYNCPT_RANGE                        MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_1_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_2_SYNCPT_SHIFT                        MK_SHIFT_CONST(18)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_2_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_2_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_2_SYNCPT_RANGE                        MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_2_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_3_SYNCPT_SHIFT                        MK_SHIFT_CONST(19)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_3_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_3_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_3_SYNCPT_RANGE                        MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_3_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_4_SYNCPT_SHIFT                        MK_SHIFT_CONST(20)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_4_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_4_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_4_SYNCPT_RANGE                        MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_4_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_5_SYNCPT_SHIFT                        MK_SHIFT_CONST(21)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_5_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_5_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_5_SYNCPT_RANGE                        MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_5_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_6_SYNCPT_SHIFT                        MK_SHIFT_CONST(22)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_6_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_6_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_6_SYNCPT_RANGE                        MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_6_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_7_SYNCPT_SHIFT                        MK_SHIFT_CONST(23)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_7_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_7_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_7_SYNCPT_RANGE                        MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM7_7_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_0_SYNCPT_SHIFT                        MK_SHIFT_CONST(24)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_0_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_0_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_0_SYNCPT_RANGE                        MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_0_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_1_SYNCPT_SHIFT                        MK_SHIFT_CONST(25)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_1_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_1_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_1_SYNCPT_RANGE                        MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_1_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_2_SYNCPT_SHIFT                        MK_SHIFT_CONST(26)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_2_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_2_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_2_SYNCPT_RANGE                        MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_2_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_3_SYNCPT_SHIFT                        MK_SHIFT_CONST(27)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_3_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_3_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_3_SYNCPT_RANGE                        MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_3_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_4_SYNCPT_SHIFT                        MK_SHIFT_CONST(28)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_4_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_4_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_4_SYNCPT_RANGE                        MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_4_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_5_SYNCPT_SHIFT                        MK_SHIFT_CONST(29)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_5_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_5_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_5_SYNCPT_RANGE                        MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_5_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_6_SYNCPT_SHIFT                        MK_SHIFT_CONST(30)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_6_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_6_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_6_SYNCPT_RANGE                        MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_6_SYNCPT_ROW                  0
+
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_7_SYNCPT_SHIFT                        MK_SHIFT_CONST(31)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_7_SYNCPT_FIELD                        MK_FIELD_CONST(0x1, SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_7_SYNCPT_SHIFT)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_7_SYNCPT_RANGE                        MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
+#define SLICE15_ICTLR_FIELDS_0_HOST1X2VM8_7_SYNCPT_ROW                  0
+
+
+// Packet SLICE16_ICTLR_FIELDS_0
+#define SLICE16_ICTLR_FIELDS_0_SIZE 32
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTA_SHIFT                       MK_SHIFT_CONST(0)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTA_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTA_RANGE                       MK_SHIFT_CONST(0):MK_SHIFT_CONST(0)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTA_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTB_SHIFT                       MK_SHIFT_CONST(1)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTB_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTB_RANGE                       MK_SHIFT_CONST(1):MK_SHIFT_CONST(1)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTB_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTC_SHIFT                       MK_SHIFT_CONST(2)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTC_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTC_RANGE                       MK_SHIFT_CONST(2):MK_SHIFT_CONST(2)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTC_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTD_SHIFT                       MK_SHIFT_CONST(3)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTD_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTD_RANGE                       MK_SHIFT_CONST(3):MK_SHIFT_CONST(3)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C0_INTD_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTA_SHIFT                       MK_SHIFT_CONST(4)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTA_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTA_RANGE                       MK_SHIFT_CONST(4):MK_SHIFT_CONST(4)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTA_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTB_SHIFT                       MK_SHIFT_CONST(5)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTB_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTB_RANGE                       MK_SHIFT_CONST(5):MK_SHIFT_CONST(5)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTB_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTC_SHIFT                       MK_SHIFT_CONST(6)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTC_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTC_RANGE                       MK_SHIFT_CONST(6):MK_SHIFT_CONST(6)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTC_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTD_SHIFT                       MK_SHIFT_CONST(7)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTD_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTD_RANGE                       MK_SHIFT_CONST(7):MK_SHIFT_CONST(7)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C1_INTD_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTA_SHIFT                       MK_SHIFT_CONST(8)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTA_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTA_RANGE                       MK_SHIFT_CONST(8):MK_SHIFT_CONST(8)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTA_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTB_SHIFT                       MK_SHIFT_CONST(9)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTB_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTB_RANGE                       MK_SHIFT_CONST(9):MK_SHIFT_CONST(9)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTB_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTC_SHIFT                       MK_SHIFT_CONST(10)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTC_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTC_RANGE                       MK_SHIFT_CONST(10):MK_SHIFT_CONST(10)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTC_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTD_SHIFT                       MK_SHIFT_CONST(11)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTD_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTD_RANGE                       MK_SHIFT_CONST(11):MK_SHIFT_CONST(11)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C2_INTD_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTA_SHIFT                       MK_SHIFT_CONST(12)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTA_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTA_RANGE                       MK_SHIFT_CONST(12):MK_SHIFT_CONST(12)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTA_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTB_SHIFT                       MK_SHIFT_CONST(13)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTB_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTB_RANGE                       MK_SHIFT_CONST(13):MK_SHIFT_CONST(13)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTB_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTC_SHIFT                       MK_SHIFT_CONST(14)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTC_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTC_RANGE                       MK_SHIFT_CONST(14):MK_SHIFT_CONST(14)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTC_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTD_SHIFT                       MK_SHIFT_CONST(15)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTD_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTD_RANGE                       MK_SHIFT_CONST(15):MK_SHIFT_CONST(15)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C3_INTD_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTA_SHIFT                       MK_SHIFT_CONST(16)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTA_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTA_RANGE                       MK_SHIFT_CONST(16):MK_SHIFT_CONST(16)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTA_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTB_SHIFT                       MK_SHIFT_CONST(17)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTB_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTB_RANGE                       MK_SHIFT_CONST(17):MK_SHIFT_CONST(17)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTB_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTC_SHIFT                       MK_SHIFT_CONST(18)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTC_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTC_RANGE                       MK_SHIFT_CONST(18):MK_SHIFT_CONST(18)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTC_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTD_SHIFT                       MK_SHIFT_CONST(19)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTD_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTD_RANGE                       MK_SHIFT_CONST(19):MK_SHIFT_CONST(19)
+#define SLICE16_ICTLR_FIELDS_0_PEX0_C4_INTD_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTA_SHIFT                       MK_SHIFT_CONST(20)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTA_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTA_RANGE                       MK_SHIFT_CONST(20):MK_SHIFT_CONST(20)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTA_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTB_SHIFT                       MK_SHIFT_CONST(21)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTB_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTB_RANGE                       MK_SHIFT_CONST(21):MK_SHIFT_CONST(21)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTB_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTC_SHIFT                       MK_SHIFT_CONST(22)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTC_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTC_RANGE                       MK_SHIFT_CONST(22):MK_SHIFT_CONST(22)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTC_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTD_SHIFT                       MK_SHIFT_CONST(23)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTD_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTD_RANGE                       MK_SHIFT_CONST(23):MK_SHIFT_CONST(23)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C5_INTD_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTA_SHIFT                       MK_SHIFT_CONST(24)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTA_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTA_RANGE                       MK_SHIFT_CONST(24):MK_SHIFT_CONST(24)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTA_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTB_SHIFT                       MK_SHIFT_CONST(25)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTB_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTB_RANGE                       MK_SHIFT_CONST(25):MK_SHIFT_CONST(25)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTB_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTC_SHIFT                       MK_SHIFT_CONST(26)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTC_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTC_RANGE                       MK_SHIFT_CONST(26):MK_SHIFT_CONST(26)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTC_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTD_SHIFT                       MK_SHIFT_CONST(27)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTD_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTD_RANGE                       MK_SHIFT_CONST(27):MK_SHIFT_CONST(27)
+#define SLICE16_ICTLR_FIELDS_0_PEX1_C6_INTD_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTA_SHIFT                       MK_SHIFT_CONST(28)
+#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTA_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTA_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTA_RANGE                       MK_SHIFT_CONST(28):MK_SHIFT_CONST(28)
+#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTA_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTB_SHIFT                       MK_SHIFT_CONST(29)
+#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTB_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTB_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTB_RANGE                       MK_SHIFT_CONST(29):MK_SHIFT_CONST(29)
+#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTB_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTC_SHIFT                       MK_SHIFT_CONST(30)
+#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTC_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTC_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTC_RANGE                       MK_SHIFT_CONST(30):MK_SHIFT_CONST(30)
+#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTC_ROW                 0
+
+#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTD_SHIFT                       MK_SHIFT_CONST(31)
+#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTD_FIELD                       MK_FIELD_CONST(0x1, SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTD_SHIFT)
+#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTD_RANGE                       MK_SHIFT_CONST(31):MK_SHIFT_CONST(31)
+#define SLICE16_ICTLR_FIELDS_0_PEX2_C7_INTD_ROW                 0
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARINTR_CTLR_REGS(_op_) \
+_op_(INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE0_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE0_IER_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE0_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE0_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE0_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE0_ISR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE0_IDR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE0_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE1_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE1_IER_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE1_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE1_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE1_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE1_ISR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE1_IDR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE1_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE2_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE2_IER_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE2_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE2_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE2_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE2_ISR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE2_IDR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE2_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE3_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE3_IER_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE3_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE3_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE3_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE3_ISR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE3_IDR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE3_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE4_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE4_IER_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE4_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE4_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE4_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE4_ISR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE4_IDR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE4_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE5_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE5_IER_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE5_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE5_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE5_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE5_ISR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE5_IDR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE5_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE6_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE6_IER_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE6_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE6_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE6_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE6_ISR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE6_IDR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE6_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE7_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE7_IER_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE7_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE7_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE7_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE7_ISR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE7_IDR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE7_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE8_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE8_IER_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE8_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE8_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE8_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE8_ISR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE8_IDR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE8_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE9_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE9_IER_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE9_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE9_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE9_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE9_ISR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE9_IDR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE9_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE10_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE10_IER_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE10_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE10_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE10_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE10_ISR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE10_IDR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE10_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE11_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE11_IER_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE11_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE11_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE11_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE11_ISR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE11_IDR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE11_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE12_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE12_IER_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE12_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE12_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE12_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE12_ISR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE12_IDR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE12_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE13_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE13_IER_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE13_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE13_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE13_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE13_ISR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE13_IDR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE13_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE14_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE14_IER_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE14_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE14_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE14_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE14_ISR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE14_IDR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE14_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE15_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE15_IER_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE15_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE15_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE15_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE15_ISR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE15_IDR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE15_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE16_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE16_IER_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE16_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE16_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE16_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE16_ISR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE16_IDR_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE16_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0) \
+_op_(INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE0_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE0_IER_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE0_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE0_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE0_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE0_ISR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE0_IDR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE0_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE1_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE1_IER_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE1_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE1_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE1_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE1_ISR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE1_IDR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE1_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE2_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE2_IER_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE2_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE2_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE2_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE2_ISR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE2_IDR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE2_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE3_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE3_IER_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE3_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE3_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE3_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE3_ISR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE3_IDR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE3_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE4_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE4_IER_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE4_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE4_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE4_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE4_ISR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE4_IDR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE4_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE5_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE5_IER_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE5_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE5_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE5_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE5_ISR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE5_IDR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE5_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE6_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE6_IER_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE6_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE6_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE6_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE6_ISR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE6_IDR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE6_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE7_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE7_IER_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE7_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE7_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE7_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE7_ISR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE7_IDR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE7_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE8_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE8_IER_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE8_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE8_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE8_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE8_ISR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE8_IDR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE8_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE9_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE9_IER_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE9_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE9_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE9_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE9_ISR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE9_IDR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE9_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE10_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE10_IER_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE10_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE10_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE10_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE10_ISR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE10_IDR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE10_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE11_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE11_IER_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE11_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE11_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE11_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE11_ISR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE11_IDR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE11_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE12_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE12_IER_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE12_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE12_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE12_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE12_ISR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE12_IDR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE12_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE13_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE13_IER_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE13_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE13_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE13_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE13_ISR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE13_IDR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE13_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE14_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE14_IER_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE14_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE14_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE14_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE14_ISR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE14_IDR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE14_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE15_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE15_IER_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE15_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE15_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE15_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE15_ISR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE15_IDR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE15_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE16_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE16_IER_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE16_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE16_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE16_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE16_ISR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE16_IDR_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE16_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0) \
+_op_(INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE0_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE0_IER_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE0_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE0_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE0_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE0_ISR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE0_IDR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE0_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE1_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE1_IER_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE1_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE1_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE1_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE1_ISR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE1_IDR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE1_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE2_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE2_IER_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE2_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE2_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE2_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE2_ISR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE2_IDR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE2_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE3_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE3_IER_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE3_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE3_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE3_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE3_ISR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE3_IDR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE3_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE4_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE4_IER_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE4_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE4_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE4_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE4_ISR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE4_IDR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE4_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE5_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE5_IER_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE5_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE5_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE5_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE5_ISR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE5_IDR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE5_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE6_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE6_IER_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE6_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE6_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE6_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE6_ISR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE6_IDR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE6_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE7_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE7_IER_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE7_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE7_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE7_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE7_ISR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE7_IDR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE7_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE8_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE8_IER_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE8_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE8_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE8_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE8_ISR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE8_IDR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE8_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE9_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE9_IER_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE9_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE9_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE9_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE9_ISR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE9_IDR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE9_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE10_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE10_IER_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE10_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE10_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE10_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE10_ISR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE10_IDR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE10_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE11_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE11_IER_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE11_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE11_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE11_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE11_ISR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE11_IDR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE11_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE12_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE12_IER_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE12_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE12_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE12_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE12_ISR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE12_IDR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE12_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE13_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE13_IER_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE13_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE13_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE13_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE13_ISR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE13_IDR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE13_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE14_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE14_IER_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE14_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE14_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE14_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE14_ISR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE14_IDR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE14_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE15_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE15_IER_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE15_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE15_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE15_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE15_ISR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE15_IDR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE15_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE16_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE16_IER_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE16_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE16_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE16_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE16_ISR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE16_IDR_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE16_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0) \
+_op_(INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE0_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE0_IER_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE0_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE0_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE0_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE0_ISR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE0_IDR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE0_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE1_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE1_IER_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE1_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE1_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE1_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE1_ISR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE1_IDR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE1_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE2_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE2_IER_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE2_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE2_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE2_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE2_ISR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE2_IDR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE2_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE3_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE3_IER_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE3_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE3_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE3_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE3_ISR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE3_IDR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE3_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE4_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE4_IER_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE4_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE4_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE4_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE4_ISR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE4_IDR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE4_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE5_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE5_IER_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE5_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE5_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE5_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE5_ISR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE5_IDR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE5_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE6_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE6_IER_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE6_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE6_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE6_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE6_ISR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE6_IDR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE6_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE7_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE7_IER_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE7_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE7_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE7_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE7_ISR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE7_IDR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE7_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE8_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE8_IER_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE8_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE8_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE8_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE8_ISR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE8_IDR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE8_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE9_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE9_IER_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE9_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE9_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE9_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE9_ISR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE9_IDR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE9_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE10_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE10_IER_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE10_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE10_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE10_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE10_ISR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE10_IDR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE10_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE11_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE11_IER_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE11_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE11_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE11_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE11_ISR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE11_IDR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE11_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE12_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE12_IER_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE12_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE12_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE12_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE12_ISR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE12_IDR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE12_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE13_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE13_IER_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE13_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE13_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE13_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE13_ISR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE13_IDR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE13_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE14_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE14_IER_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE14_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE14_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE14_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE14_ISR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE14_IDR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE14_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE15_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE15_IER_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE15_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE15_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE15_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE15_ISR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE15_IDR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE15_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE16_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE16_IER_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE16_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE16_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE16_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE16_ISR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE16_IDR_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE16_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0) \
+_op_(INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE0_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE0_IER_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE0_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE0_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE0_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE0_ISR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE0_IDR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE0_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE1_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE1_IER_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE1_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE1_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE1_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE1_ISR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE1_IDR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE1_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE2_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE2_IER_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE2_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE2_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE2_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE2_ISR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE2_IDR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE2_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE3_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE3_IER_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE3_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE3_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE3_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE3_ISR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE3_IDR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE3_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE4_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE4_IER_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE4_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE4_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE4_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE4_ISR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE4_IDR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE4_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE5_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE5_IER_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE5_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE5_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE5_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE5_ISR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE5_IDR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE5_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE6_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE6_IER_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE6_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE6_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE6_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE6_ISR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE6_IDR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE6_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE7_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE7_IER_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE7_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE7_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE7_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE7_ISR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE7_IDR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE7_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE8_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE8_IER_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE8_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE8_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE8_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE8_ISR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE8_IDR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE8_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE9_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE9_IER_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE9_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE9_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE9_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE9_ISR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE9_IDR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE9_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE10_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE10_IER_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE10_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE10_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE10_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE10_ISR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE10_IDR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE10_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE11_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE11_IER_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE11_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE11_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE11_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE11_ISR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE11_IDR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE11_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE12_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE12_IER_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE12_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE12_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE12_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE12_ISR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE12_IDR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE12_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE13_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE13_IER_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE13_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE13_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE13_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE13_ISR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE13_IDR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE13_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE14_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE14_IER_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE14_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE14_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE14_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE14_ISR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE14_IDR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE14_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE15_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE15_IER_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE15_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE15_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE15_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE15_ISR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE15_IDR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE15_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE16_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE16_IER_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE16_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE16_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE16_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE16_ISR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE16_IDR_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE16_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0) \
+_op_(INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE0_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE0_IER_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE0_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE0_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE0_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE0_ISR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE0_IDR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE0_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE1_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE1_IER_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE1_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE1_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE1_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE1_ISR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE1_IDR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE1_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE2_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE2_IER_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE2_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE2_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE2_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE2_ISR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE2_IDR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE2_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE3_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE3_IER_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE3_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE3_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE3_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE3_ISR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE3_IDR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE3_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE4_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE4_IER_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE4_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE4_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE4_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE4_ISR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE4_IDR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE4_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE5_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE5_IER_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE5_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE5_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE5_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE5_ISR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE5_IDR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE5_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE6_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE6_IER_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE6_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE6_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE6_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE6_ISR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE6_IDR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE6_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE7_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE7_IER_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE7_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE7_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE7_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE7_ISR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE7_IDR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE7_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE8_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE8_IER_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE8_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE8_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE8_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE8_ISR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE8_IDR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE8_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE9_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE9_IER_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE9_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE9_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE9_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE9_ISR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE9_IDR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE9_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE10_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE10_IER_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE10_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE10_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE10_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE10_ISR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE10_IDR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE10_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE11_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE11_IER_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE11_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE11_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE11_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE11_ISR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE11_IDR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE11_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE12_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE12_IER_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE12_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE12_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE12_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE12_ISR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE12_IDR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE12_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE13_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE13_IER_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE13_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE13_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE13_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE13_ISR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE13_IDR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE13_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE14_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE14_IER_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE14_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE14_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE14_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE14_ISR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE14_IDR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE14_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE15_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE15_IER_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE15_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE15_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE15_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE15_ISR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE15_IDR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE15_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE16_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE16_IER_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE16_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE16_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE16_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE16_ISR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE16_IDR_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE16_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0) \
+_op_(INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE0_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE0_IER_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE0_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE0_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE0_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE0_ISR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE0_IDR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE0_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE1_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE1_IER_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE1_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE1_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE1_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE1_ISR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE1_IDR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE1_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE2_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE2_IER_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE2_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE2_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE2_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE2_ISR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE2_IDR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE2_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE3_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE3_IER_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE3_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE3_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE3_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE3_ISR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE3_IDR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE3_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE4_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE4_IER_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE4_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE4_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE4_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE4_ISR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE4_IDR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE4_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE5_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE5_IER_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE5_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE5_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE5_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE5_ISR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE5_IDR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE5_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE6_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE6_IER_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE6_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE6_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE6_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE6_ISR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE6_IDR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE6_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE7_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE7_IER_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE7_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE7_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE7_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE7_ISR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE7_IDR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE7_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE8_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE8_IER_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE8_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE8_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE8_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE8_ISR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE8_IDR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE8_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE9_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE9_IER_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE9_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE9_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE9_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE9_ISR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE9_IDR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE9_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE10_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE10_IER_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE10_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE10_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE10_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE10_ISR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE10_IDR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE10_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE11_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE11_IER_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE11_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE11_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE11_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE11_ISR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE11_IDR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE11_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE12_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE12_IER_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE12_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE12_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE12_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE12_ISR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE12_IDR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE12_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE13_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE13_IER_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE13_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE13_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE13_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE13_ISR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE13_IDR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE13_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE14_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE14_IER_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE14_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE14_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE14_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE14_ISR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE14_IDR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE14_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE15_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE15_IER_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE15_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE15_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE15_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE15_ISR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE15_IDR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE15_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE16_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE16_IER_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE16_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE16_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE16_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE16_ISR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE16_IDR_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE16_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0) \
+_op_(INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE0_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE0_IER_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE0_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE0_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE0_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE0_ISR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE0_IDR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE0_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE1_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE1_IER_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE1_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE1_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE1_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE1_ISR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE1_IDR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE1_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE2_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE2_IER_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE2_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE2_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE2_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE2_ISR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE2_IDR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE2_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE3_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE3_IER_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE3_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE3_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE3_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE3_ISR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE3_IDR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE3_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE4_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE4_IER_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE4_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE4_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE4_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE4_ISR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE4_IDR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE4_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE5_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE5_IER_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE5_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE5_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE5_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE5_ISR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE5_IDR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE5_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE6_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE6_IER_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE6_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE6_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE6_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE6_ISR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE6_IDR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE6_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE7_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE7_IER_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE7_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE7_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE7_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE7_ISR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE7_IDR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE7_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE8_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE8_IER_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE8_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE8_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE8_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE8_ISR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE8_IDR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE8_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE9_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE9_IER_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE9_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE9_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE9_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE9_ISR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE9_IDR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE9_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE10_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE10_IER_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE10_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE10_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE10_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE10_ISR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE10_IDR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE10_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE11_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE11_IER_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE11_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE11_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE11_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE11_ISR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE11_IDR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE11_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE12_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE12_IER_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE12_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE12_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE12_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE12_ISR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE12_IDR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE12_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE13_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE13_IER_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE13_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE13_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE13_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE13_ISR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE13_IDR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE13_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE14_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE14_IER_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE14_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE14_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE14_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE14_ISR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE14_IDR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE14_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE15_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE15_IER_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE15_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE15_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE15_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE15_ISR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE15_IDR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE15_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE16_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE16_IER_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE16_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE16_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE16_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE16_ISR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE16_IDR_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE16_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0) \
+_op_(INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE0_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE0_IER_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE0_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE0_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE0_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE0_ISR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE0_IDR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE0_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE1_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE1_IER_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE1_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE1_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE1_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE1_ISR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE1_IDR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE1_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE2_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE2_IER_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE2_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE2_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE2_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE2_ISR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE2_IDR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE2_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE3_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE3_IER_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE3_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE3_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE3_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE3_ISR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE3_IDR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE3_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE4_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE4_IER_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE4_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE4_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE4_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE4_ISR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE4_IDR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE4_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE5_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE5_IER_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE5_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE5_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE5_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE5_ISR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE5_IDR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE5_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE6_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE6_IER_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE6_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE6_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE6_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE6_ISR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE6_IDR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE6_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE7_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE7_IER_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE7_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE7_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE7_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE7_ISR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE7_IDR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE7_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE8_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE8_IER_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE8_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE8_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE8_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE8_ISR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE8_IDR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE8_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE9_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE9_IER_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE9_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE9_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE9_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE9_ISR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE9_IDR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE9_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE10_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE10_IER_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE10_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE10_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE10_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE10_ISR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE10_IDR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE10_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE11_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE11_IER_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE11_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE11_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE11_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE11_ISR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE11_IDR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE11_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE12_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE12_IER_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE12_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE12_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE12_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE12_ISR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE12_IDR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE12_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE13_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE13_IER_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE13_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE13_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE13_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE13_ISR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE13_IDR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE13_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE14_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE14_IER_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE14_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE14_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE14_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE14_ISR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE14_IDR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE14_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE15_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE15_IER_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE15_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE15_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE15_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE15_ISR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE15_IDR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE15_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE16_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE16_IER_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE16_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE16_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE16_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE16_ISR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE16_IDR_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE16_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0) \
+_op_(INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE0_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE0_IER_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE0_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE0_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE0_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE0_ISR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE0_IDR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE0_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE1_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE1_IER_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE1_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE1_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE1_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE1_ISR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE1_IDR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE1_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE2_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE2_IER_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE2_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE2_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE2_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE2_ISR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE2_IDR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE2_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE3_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE3_IER_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE3_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE3_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE3_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE3_ISR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE3_IDR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE3_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE4_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE4_IER_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE4_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE4_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE4_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE4_ISR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE4_IDR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE4_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE5_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE5_IER_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE5_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE5_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE5_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE5_ISR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE5_IDR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE5_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE6_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE6_IER_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE6_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE6_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE6_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE6_ISR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE6_IDR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE6_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE7_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE7_IER_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE7_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE7_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE7_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE7_ISR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE7_IDR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE7_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE8_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE8_IER_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE8_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE8_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE8_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE8_ISR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE8_IDR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE8_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE9_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE9_IER_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE9_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE9_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE9_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE9_ISR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE9_IDR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE9_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE10_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE10_IER_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE10_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE10_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE10_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE10_ISR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE10_IDR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE10_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE11_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE11_IER_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE11_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE11_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE11_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE11_ISR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE11_IDR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE11_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE12_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE12_IER_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE12_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE12_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE12_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE12_ISR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE12_IDR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE12_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE13_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE13_IER_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE13_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE13_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE13_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE13_ISR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE13_IDR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE13_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE14_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE14_IER_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE14_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE14_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE14_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE14_ISR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE14_IDR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE14_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE15_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE15_IER_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE15_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE15_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE15_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE15_ISR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE15_IDR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE15_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE16_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE16_IER_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE16_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE16_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE16_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE16_ISR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE16_IDR_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE16_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0) \
+_op_(INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE0_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE0_IER_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE0_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE0_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE0_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE0_ISR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE0_IDR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE0_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE1_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE1_IER_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE1_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE1_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE1_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE1_ISR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE1_IDR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE1_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE2_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE2_IER_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE2_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE2_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE2_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE2_ISR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE2_IDR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE2_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE3_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE3_IER_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE3_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE3_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE3_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE3_ISR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE3_IDR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE3_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE4_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE4_IER_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE4_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE4_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE4_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE4_ISR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE4_IDR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE4_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE5_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE5_IER_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE5_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE5_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE5_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE5_ISR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE5_IDR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE5_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE6_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE6_IER_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE6_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE6_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE6_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE6_ISR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE6_IDR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE6_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE7_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE7_IER_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE7_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE7_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE7_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE7_ISR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE7_IDR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE7_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE8_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE8_IER_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE8_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE8_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE8_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE8_ISR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE8_IDR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE8_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE9_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE9_IER_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE9_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE9_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE9_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE9_ISR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE9_IDR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE9_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE10_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE10_IER_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE10_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE10_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE10_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE10_ISR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE10_IDR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE10_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE11_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE11_IER_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE11_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE11_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE11_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE11_ISR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE11_IDR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE11_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE12_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE12_IER_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE12_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE12_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE12_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE12_ISR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE12_IDR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE12_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE13_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE13_IER_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE13_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE13_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE13_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE13_ISR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE13_IDR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE13_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE14_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE14_IER_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE14_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE14_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE14_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE14_ISR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE14_IDR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE14_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE15_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE15_IER_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE15_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE15_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE15_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE15_ISR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE15_IDR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE15_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE16_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE16_IER_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE16_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE16_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE16_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE16_ISR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE16_IDR_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE16_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0) \
+_op_(INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE0_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE0_IER_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE0_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE0_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE0_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE0_ISR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE0_IDR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE0_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE1_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE1_IER_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE1_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE1_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE1_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE1_ISR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE1_IDR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE1_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE2_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE2_IER_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE2_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE2_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE2_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE2_ISR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE2_IDR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE2_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE3_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE3_IER_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE3_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE3_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE3_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE3_ISR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE3_IDR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE3_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE4_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE4_IER_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE4_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE4_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE4_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE4_ISR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE4_IDR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE4_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE5_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE5_IER_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE5_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE5_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE5_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE5_ISR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE5_IDR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE5_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE6_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE6_IER_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE6_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE6_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE6_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE6_ISR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE6_IDR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE6_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE7_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE7_IER_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE7_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE7_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE7_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE7_ISR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE7_IDR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE7_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE8_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE8_IER_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE8_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE8_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE8_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE8_ISR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE8_IDR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE8_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE9_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE9_IER_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE9_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE9_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE9_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE9_ISR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE9_IDR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE9_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE10_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE10_IER_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE10_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE10_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE10_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE10_ISR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE10_IDR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE10_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE11_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE11_IER_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE11_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE11_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE11_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE11_ISR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE11_IDR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE11_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE12_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE12_IER_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE12_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE12_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE12_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE12_ISR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE12_IDR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE12_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE13_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE13_IER_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE13_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE13_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE13_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE13_ISR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE13_IDR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE13_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE14_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE14_IER_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE14_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE14_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE14_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE14_ISR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE14_IDR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE14_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE15_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE15_IER_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE15_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE15_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE15_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE15_ISR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE15_IDR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE15_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE16_VFIQ_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE16_IER_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE16_IER_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE16_IER_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE16_IEP_CLASS_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE16_ISR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE16_IDR_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE16_IDR_SET_0) \
+_op_(INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0) \
+_op_(INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0) \
+_op_(INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0) \
+_op_(INTR_CTLR_COMMON_SLICE0_GISR_0) \
+_op_(INTR_CTLR_COMMON_SLICE0_FIR_0) \
+_op_(INTR_CTLR_COMMON_SLICE0_FIR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE0_FIR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE0_CIDR_0) \
+_op_(INTR_CTLR_COMMON_SLICE0_CIDR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE1_GISR_0) \
+_op_(INTR_CTLR_COMMON_SLICE1_FIR_0) \
+_op_(INTR_CTLR_COMMON_SLICE1_FIR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE1_FIR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE1_CIDR_0) \
+_op_(INTR_CTLR_COMMON_SLICE1_CIDR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE2_GISR_0) \
+_op_(INTR_CTLR_COMMON_SLICE2_FIR_0) \
+_op_(INTR_CTLR_COMMON_SLICE2_FIR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE2_FIR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE2_CIDR_0) \
+_op_(INTR_CTLR_COMMON_SLICE2_CIDR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE3_GISR_0) \
+_op_(INTR_CTLR_COMMON_SLICE3_FIR_0) \
+_op_(INTR_CTLR_COMMON_SLICE3_FIR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE3_FIR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE3_CIDR_0) \
+_op_(INTR_CTLR_COMMON_SLICE3_CIDR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE4_GISR_0) \
+_op_(INTR_CTLR_COMMON_SLICE4_FIR_0) \
+_op_(INTR_CTLR_COMMON_SLICE4_FIR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE4_FIR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE4_CIDR_0) \
+_op_(INTR_CTLR_COMMON_SLICE4_CIDR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE5_GISR_0) \
+_op_(INTR_CTLR_COMMON_SLICE5_FIR_0) \
+_op_(INTR_CTLR_COMMON_SLICE5_FIR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE5_FIR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE5_CIDR_0) \
+_op_(INTR_CTLR_COMMON_SLICE5_CIDR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE6_GISR_0) \
+_op_(INTR_CTLR_COMMON_SLICE6_FIR_0) \
+_op_(INTR_CTLR_COMMON_SLICE6_FIR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE6_FIR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE6_CIDR_0) \
+_op_(INTR_CTLR_COMMON_SLICE6_CIDR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE7_GISR_0) \
+_op_(INTR_CTLR_COMMON_SLICE7_FIR_0) \
+_op_(INTR_CTLR_COMMON_SLICE7_FIR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE7_FIR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE7_CIDR_0) \
+_op_(INTR_CTLR_COMMON_SLICE7_CIDR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE8_GISR_0) \
+_op_(INTR_CTLR_COMMON_SLICE8_FIR_0) \
+_op_(INTR_CTLR_COMMON_SLICE8_FIR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE8_FIR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE8_CIDR_0) \
+_op_(INTR_CTLR_COMMON_SLICE8_CIDR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE9_GISR_0) \
+_op_(INTR_CTLR_COMMON_SLICE9_FIR_0) \
+_op_(INTR_CTLR_COMMON_SLICE9_FIR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE9_FIR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE9_CIDR_0) \
+_op_(INTR_CTLR_COMMON_SLICE9_CIDR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE10_GISR_0) \
+_op_(INTR_CTLR_COMMON_SLICE10_FIR_0) \
+_op_(INTR_CTLR_COMMON_SLICE10_FIR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE10_FIR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE10_CIDR_0) \
+_op_(INTR_CTLR_COMMON_SLICE10_CIDR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE11_GISR_0) \
+_op_(INTR_CTLR_COMMON_SLICE11_FIR_0) \
+_op_(INTR_CTLR_COMMON_SLICE11_FIR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE11_FIR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE11_CIDR_0) \
+_op_(INTR_CTLR_COMMON_SLICE11_CIDR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE12_GISR_0) \
+_op_(INTR_CTLR_COMMON_SLICE12_FIR_0) \
+_op_(INTR_CTLR_COMMON_SLICE12_FIR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE12_FIR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE12_CIDR_0) \
+_op_(INTR_CTLR_COMMON_SLICE12_CIDR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE13_GISR_0) \
+_op_(INTR_CTLR_COMMON_SLICE13_FIR_0) \
+_op_(INTR_CTLR_COMMON_SLICE13_FIR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE13_FIR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE13_CIDR_0) \
+_op_(INTR_CTLR_COMMON_SLICE13_CIDR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE14_GISR_0) \
+_op_(INTR_CTLR_COMMON_SLICE14_FIR_0) \
+_op_(INTR_CTLR_COMMON_SLICE14_FIR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE14_FIR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE14_CIDR_0) \
+_op_(INTR_CTLR_COMMON_SLICE14_CIDR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE15_GISR_0) \
+_op_(INTR_CTLR_COMMON_SLICE15_FIR_0) \
+_op_(INTR_CTLR_COMMON_SLICE15_FIR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE15_FIR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE15_CIDR_0) \
+_op_(INTR_CTLR_COMMON_SLICE15_CIDR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE16_GISR_0) \
+_op_(INTR_CTLR_COMMON_SLICE16_FIR_0) \
+_op_(INTR_CTLR_COMMON_SLICE16_FIR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE16_FIR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SLICE16_CIDR_0) \
+_op_(INTR_CTLR_COMMON_SLICE16_CIDR_SET_0) \
+_op_(INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0) \
+_op_(INTR_CTLR_COMMON_SCR_SCR_COMMON_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_INTR_CTLR  0x00000000
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL0 0x00000000
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL0_SCR     0x000007c0
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL1 0x00000800
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL1_SCR     0x00000fc0
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL2 0x00001000
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL2_SCR     0x000017c0
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL3 0x00001800
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL3_SCR     0x00001fc0
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL4 0x00002000
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL4_SCR     0x000027c0
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL5 0x00002800
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL5_SCR     0x00002fc0
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL6 0x00003000
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL6_SCR     0x000037c0
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL7 0x00003800
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL7_SCR     0x00003fc0
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL8 0x00004000
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL8_SCR     0x000047c0
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL9 0x00004800
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL9_SCR     0x00004fc0
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL10        0x00005000
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL10_SCR    0x000057c0
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL11        0x00005800
+#define BASE_ADDRESS_INTR_CTLR_CHANNEL11_SCR    0x00005fc0
+#define BASE_ADDRESS_INTR_CTLR_COMMON   0x0000f800
+#define BASE_ADDRESS_INTR_CTLR_COMMON_SCR       0x0000ffc4
+
+//
+// ARINTR_CTLR REGISTER BANKS
+//
+
+#define INTR_CTLR_CHANNEL0_0_FIRST_REG 0x0000 // INTR_CTLR_CHANNEL0_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL0_0_LAST_REG 0x0024 // INTR_CTLR_CHANNEL0_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_1_FIRST_REG 0x0040 // INTR_CTLR_CHANNEL0_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL0_1_LAST_REG 0x0064 // INTR_CTLR_CHANNEL0_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_2_FIRST_REG 0x0080 // INTR_CTLR_CHANNEL0_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL0_2_LAST_REG 0x00a4 // INTR_CTLR_CHANNEL0_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_3_FIRST_REG 0x00c0 // INTR_CTLR_CHANNEL0_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL0_3_LAST_REG 0x00e4 // INTR_CTLR_CHANNEL0_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_4_FIRST_REG 0x0100 // INTR_CTLR_CHANNEL0_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL0_4_LAST_REG 0x0124 // INTR_CTLR_CHANNEL0_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_5_FIRST_REG 0x0140 // INTR_CTLR_CHANNEL0_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL0_5_LAST_REG 0x0164 // INTR_CTLR_CHANNEL0_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_6_FIRST_REG 0x0180 // INTR_CTLR_CHANNEL0_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL0_6_LAST_REG 0x01a4 // INTR_CTLR_CHANNEL0_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_7_FIRST_REG 0x01c0 // INTR_CTLR_CHANNEL0_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL0_7_LAST_REG 0x01e4 // INTR_CTLR_CHANNEL0_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_8_FIRST_REG 0x0200 // INTR_CTLR_CHANNEL0_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL0_8_LAST_REG 0x0224 // INTR_CTLR_CHANNEL0_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_9_FIRST_REG 0x0240 // INTR_CTLR_CHANNEL0_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL0_9_LAST_REG 0x0264 // INTR_CTLR_CHANNEL0_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_10_FIRST_REG 0x0280 // INTR_CTLR_CHANNEL0_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL0_10_LAST_REG 0x02a4 // INTR_CTLR_CHANNEL0_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_11_FIRST_REG 0x02c0 // INTR_CTLR_CHANNEL0_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL0_11_LAST_REG 0x02e4 // INTR_CTLR_CHANNEL0_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_12_FIRST_REG 0x0300 // INTR_CTLR_CHANNEL0_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL0_12_LAST_REG 0x0324 // INTR_CTLR_CHANNEL0_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_13_FIRST_REG 0x0340 // INTR_CTLR_CHANNEL0_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL0_13_LAST_REG 0x0364 // INTR_CTLR_CHANNEL0_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_14_FIRST_REG 0x0380 // INTR_CTLR_CHANNEL0_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL0_14_LAST_REG 0x03a4 // INTR_CTLR_CHANNEL0_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_15_FIRST_REG 0x03c0 // INTR_CTLR_CHANNEL0_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL0_15_LAST_REG 0x03e4 // INTR_CTLR_CHANNEL0_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_16_FIRST_REG 0x0400 // INTR_CTLR_CHANNEL0_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL0_16_LAST_REG 0x0424 // INTR_CTLR_CHANNEL0_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL0_SCR_0_FIRST_REG 0x07c0 // INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRD_0
+#define INTR_CTLR_CHANNEL0_SCR_0_LAST_REG 0x07c4 // INTR_CTLR_CHANNEL0_SCR_CHANNEL0_SCRE_0
+#define INTR_CTLR_CHANNEL1_0_FIRST_REG 0x0800 // INTR_CTLR_CHANNEL1_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL1_0_LAST_REG 0x0824 // INTR_CTLR_CHANNEL1_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_1_FIRST_REG 0x0840 // INTR_CTLR_CHANNEL1_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL1_1_LAST_REG 0x0864 // INTR_CTLR_CHANNEL1_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_2_FIRST_REG 0x0880 // INTR_CTLR_CHANNEL1_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL1_2_LAST_REG 0x08a4 // INTR_CTLR_CHANNEL1_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_3_FIRST_REG 0x08c0 // INTR_CTLR_CHANNEL1_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL1_3_LAST_REG 0x08e4 // INTR_CTLR_CHANNEL1_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_4_FIRST_REG 0x0900 // INTR_CTLR_CHANNEL1_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL1_4_LAST_REG 0x0924 // INTR_CTLR_CHANNEL1_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_5_FIRST_REG 0x0940 // INTR_CTLR_CHANNEL1_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL1_5_LAST_REG 0x0964 // INTR_CTLR_CHANNEL1_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_6_FIRST_REG 0x0980 // INTR_CTLR_CHANNEL1_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL1_6_LAST_REG 0x09a4 // INTR_CTLR_CHANNEL1_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_7_FIRST_REG 0x09c0 // INTR_CTLR_CHANNEL1_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL1_7_LAST_REG 0x09e4 // INTR_CTLR_CHANNEL1_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_8_FIRST_REG 0x0a00 // INTR_CTLR_CHANNEL1_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL1_8_LAST_REG 0x0a24 // INTR_CTLR_CHANNEL1_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_9_FIRST_REG 0x0a40 // INTR_CTLR_CHANNEL1_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL1_9_LAST_REG 0x0a64 // INTR_CTLR_CHANNEL1_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_10_FIRST_REG 0x0a80 // INTR_CTLR_CHANNEL1_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL1_10_LAST_REG 0x0aa4 // INTR_CTLR_CHANNEL1_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_11_FIRST_REG 0x0ac0 // INTR_CTLR_CHANNEL1_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL1_11_LAST_REG 0x0ae4 // INTR_CTLR_CHANNEL1_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_12_FIRST_REG 0x0b00 // INTR_CTLR_CHANNEL1_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL1_12_LAST_REG 0x0b24 // INTR_CTLR_CHANNEL1_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_13_FIRST_REG 0x0b40 // INTR_CTLR_CHANNEL1_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL1_13_LAST_REG 0x0b64 // INTR_CTLR_CHANNEL1_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_14_FIRST_REG 0x0b80 // INTR_CTLR_CHANNEL1_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL1_14_LAST_REG 0x0ba4 // INTR_CTLR_CHANNEL1_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_15_FIRST_REG 0x0bc0 // INTR_CTLR_CHANNEL1_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL1_15_LAST_REG 0x0be4 // INTR_CTLR_CHANNEL1_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_16_FIRST_REG 0x0c00 // INTR_CTLR_CHANNEL1_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL1_16_LAST_REG 0x0c24 // INTR_CTLR_CHANNEL1_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL1_SCR_0_FIRST_REG 0x0fc0 // INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRD_0
+#define INTR_CTLR_CHANNEL1_SCR_0_LAST_REG 0x0fc4 // INTR_CTLR_CHANNEL1_SCR_CHANNEL1_SCRE_0
+#define INTR_CTLR_CHANNEL2_0_FIRST_REG 0x1000 // INTR_CTLR_CHANNEL2_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL2_0_LAST_REG 0x1024 // INTR_CTLR_CHANNEL2_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_1_FIRST_REG 0x1040 // INTR_CTLR_CHANNEL2_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL2_1_LAST_REG 0x1064 // INTR_CTLR_CHANNEL2_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_2_FIRST_REG 0x1080 // INTR_CTLR_CHANNEL2_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL2_2_LAST_REG 0x10a4 // INTR_CTLR_CHANNEL2_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_3_FIRST_REG 0x10c0 // INTR_CTLR_CHANNEL2_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL2_3_LAST_REG 0x10e4 // INTR_CTLR_CHANNEL2_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_4_FIRST_REG 0x1100 // INTR_CTLR_CHANNEL2_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL2_4_LAST_REG 0x1124 // INTR_CTLR_CHANNEL2_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_5_FIRST_REG 0x1140 // INTR_CTLR_CHANNEL2_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL2_5_LAST_REG 0x1164 // INTR_CTLR_CHANNEL2_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_6_FIRST_REG 0x1180 // INTR_CTLR_CHANNEL2_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL2_6_LAST_REG 0x11a4 // INTR_CTLR_CHANNEL2_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_7_FIRST_REG 0x11c0 // INTR_CTLR_CHANNEL2_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL2_7_LAST_REG 0x11e4 // INTR_CTLR_CHANNEL2_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_8_FIRST_REG 0x1200 // INTR_CTLR_CHANNEL2_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL2_8_LAST_REG 0x1224 // INTR_CTLR_CHANNEL2_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_9_FIRST_REG 0x1240 // INTR_CTLR_CHANNEL2_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL2_9_LAST_REG 0x1264 // INTR_CTLR_CHANNEL2_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_10_FIRST_REG 0x1280 // INTR_CTLR_CHANNEL2_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL2_10_LAST_REG 0x12a4 // INTR_CTLR_CHANNEL2_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_11_FIRST_REG 0x12c0 // INTR_CTLR_CHANNEL2_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL2_11_LAST_REG 0x12e4 // INTR_CTLR_CHANNEL2_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_12_FIRST_REG 0x1300 // INTR_CTLR_CHANNEL2_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL2_12_LAST_REG 0x1324 // INTR_CTLR_CHANNEL2_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_13_FIRST_REG 0x1340 // INTR_CTLR_CHANNEL2_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL2_13_LAST_REG 0x1364 // INTR_CTLR_CHANNEL2_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_14_FIRST_REG 0x1380 // INTR_CTLR_CHANNEL2_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL2_14_LAST_REG 0x13a4 // INTR_CTLR_CHANNEL2_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_15_FIRST_REG 0x13c0 // INTR_CTLR_CHANNEL2_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL2_15_LAST_REG 0x13e4 // INTR_CTLR_CHANNEL2_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_16_FIRST_REG 0x1400 // INTR_CTLR_CHANNEL2_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL2_16_LAST_REG 0x1424 // INTR_CTLR_CHANNEL2_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL2_SCR_0_FIRST_REG 0x17c0 // INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRD_0
+#define INTR_CTLR_CHANNEL2_SCR_0_LAST_REG 0x17c4 // INTR_CTLR_CHANNEL2_SCR_CHANNEL2_SCRE_0
+#define INTR_CTLR_CHANNEL3_0_FIRST_REG 0x1800 // INTR_CTLR_CHANNEL3_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL3_0_LAST_REG 0x1824 // INTR_CTLR_CHANNEL3_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_1_FIRST_REG 0x1840 // INTR_CTLR_CHANNEL3_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL3_1_LAST_REG 0x1864 // INTR_CTLR_CHANNEL3_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_2_FIRST_REG 0x1880 // INTR_CTLR_CHANNEL3_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL3_2_LAST_REG 0x18a4 // INTR_CTLR_CHANNEL3_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_3_FIRST_REG 0x18c0 // INTR_CTLR_CHANNEL3_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL3_3_LAST_REG 0x18e4 // INTR_CTLR_CHANNEL3_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_4_FIRST_REG 0x1900 // INTR_CTLR_CHANNEL3_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL3_4_LAST_REG 0x1924 // INTR_CTLR_CHANNEL3_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_5_FIRST_REG 0x1940 // INTR_CTLR_CHANNEL3_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL3_5_LAST_REG 0x1964 // INTR_CTLR_CHANNEL3_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_6_FIRST_REG 0x1980 // INTR_CTLR_CHANNEL3_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL3_6_LAST_REG 0x19a4 // INTR_CTLR_CHANNEL3_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_7_FIRST_REG 0x19c0 // INTR_CTLR_CHANNEL3_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL3_7_LAST_REG 0x19e4 // INTR_CTLR_CHANNEL3_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_8_FIRST_REG 0x1a00 // INTR_CTLR_CHANNEL3_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL3_8_LAST_REG 0x1a24 // INTR_CTLR_CHANNEL3_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_9_FIRST_REG 0x1a40 // INTR_CTLR_CHANNEL3_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL3_9_LAST_REG 0x1a64 // INTR_CTLR_CHANNEL3_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_10_FIRST_REG 0x1a80 // INTR_CTLR_CHANNEL3_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL3_10_LAST_REG 0x1aa4 // INTR_CTLR_CHANNEL3_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_11_FIRST_REG 0x1ac0 // INTR_CTLR_CHANNEL3_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL3_11_LAST_REG 0x1ae4 // INTR_CTLR_CHANNEL3_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_12_FIRST_REG 0x1b00 // INTR_CTLR_CHANNEL3_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL3_12_LAST_REG 0x1b24 // INTR_CTLR_CHANNEL3_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_13_FIRST_REG 0x1b40 // INTR_CTLR_CHANNEL3_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL3_13_LAST_REG 0x1b64 // INTR_CTLR_CHANNEL3_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_14_FIRST_REG 0x1b80 // INTR_CTLR_CHANNEL3_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL3_14_LAST_REG 0x1ba4 // INTR_CTLR_CHANNEL3_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_15_FIRST_REG 0x1bc0 // INTR_CTLR_CHANNEL3_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL3_15_LAST_REG 0x1be4 // INTR_CTLR_CHANNEL3_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_16_FIRST_REG 0x1c00 // INTR_CTLR_CHANNEL3_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL3_16_LAST_REG 0x1c24 // INTR_CTLR_CHANNEL3_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL3_SCR_0_FIRST_REG 0x1fc0 // INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRD_0
+#define INTR_CTLR_CHANNEL3_SCR_0_LAST_REG 0x1fc4 // INTR_CTLR_CHANNEL3_SCR_CHANNEL3_SCRE_0
+#define INTR_CTLR_CHANNEL4_0_FIRST_REG 0x2000 // INTR_CTLR_CHANNEL4_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL4_0_LAST_REG 0x2024 // INTR_CTLR_CHANNEL4_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_1_FIRST_REG 0x2040 // INTR_CTLR_CHANNEL4_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL4_1_LAST_REG 0x2064 // INTR_CTLR_CHANNEL4_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_2_FIRST_REG 0x2080 // INTR_CTLR_CHANNEL4_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL4_2_LAST_REG 0x20a4 // INTR_CTLR_CHANNEL4_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_3_FIRST_REG 0x20c0 // INTR_CTLR_CHANNEL4_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL4_3_LAST_REG 0x20e4 // INTR_CTLR_CHANNEL4_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_4_FIRST_REG 0x2100 // INTR_CTLR_CHANNEL4_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL4_4_LAST_REG 0x2124 // INTR_CTLR_CHANNEL4_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_5_FIRST_REG 0x2140 // INTR_CTLR_CHANNEL4_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL4_5_LAST_REG 0x2164 // INTR_CTLR_CHANNEL4_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_6_FIRST_REG 0x2180 // INTR_CTLR_CHANNEL4_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL4_6_LAST_REG 0x21a4 // INTR_CTLR_CHANNEL4_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_7_FIRST_REG 0x21c0 // INTR_CTLR_CHANNEL4_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL4_7_LAST_REG 0x21e4 // INTR_CTLR_CHANNEL4_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_8_FIRST_REG 0x2200 // INTR_CTLR_CHANNEL4_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL4_8_LAST_REG 0x2224 // INTR_CTLR_CHANNEL4_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_9_FIRST_REG 0x2240 // INTR_CTLR_CHANNEL4_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL4_9_LAST_REG 0x2264 // INTR_CTLR_CHANNEL4_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_10_FIRST_REG 0x2280 // INTR_CTLR_CHANNEL4_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL4_10_LAST_REG 0x22a4 // INTR_CTLR_CHANNEL4_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_11_FIRST_REG 0x22c0 // INTR_CTLR_CHANNEL4_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL4_11_LAST_REG 0x22e4 // INTR_CTLR_CHANNEL4_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_12_FIRST_REG 0x2300 // INTR_CTLR_CHANNEL4_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL4_12_LAST_REG 0x2324 // INTR_CTLR_CHANNEL4_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_13_FIRST_REG 0x2340 // INTR_CTLR_CHANNEL4_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL4_13_LAST_REG 0x2364 // INTR_CTLR_CHANNEL4_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_14_FIRST_REG 0x2380 // INTR_CTLR_CHANNEL4_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL4_14_LAST_REG 0x23a4 // INTR_CTLR_CHANNEL4_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_15_FIRST_REG 0x23c0 // INTR_CTLR_CHANNEL4_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL4_15_LAST_REG 0x23e4 // INTR_CTLR_CHANNEL4_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_16_FIRST_REG 0x2400 // INTR_CTLR_CHANNEL4_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL4_16_LAST_REG 0x2424 // INTR_CTLR_CHANNEL4_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL4_SCR_0_FIRST_REG 0x27c0 // INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRD_0
+#define INTR_CTLR_CHANNEL4_SCR_0_LAST_REG 0x27c4 // INTR_CTLR_CHANNEL4_SCR_CHANNEL4_SCRE_0
+#define INTR_CTLR_CHANNEL5_0_FIRST_REG 0x2800 // INTR_CTLR_CHANNEL5_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL5_0_LAST_REG 0x2824 // INTR_CTLR_CHANNEL5_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_1_FIRST_REG 0x2840 // INTR_CTLR_CHANNEL5_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL5_1_LAST_REG 0x2864 // INTR_CTLR_CHANNEL5_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_2_FIRST_REG 0x2880 // INTR_CTLR_CHANNEL5_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL5_2_LAST_REG 0x28a4 // INTR_CTLR_CHANNEL5_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_3_FIRST_REG 0x28c0 // INTR_CTLR_CHANNEL5_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL5_3_LAST_REG 0x28e4 // INTR_CTLR_CHANNEL5_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_4_FIRST_REG 0x2900 // INTR_CTLR_CHANNEL5_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL5_4_LAST_REG 0x2924 // INTR_CTLR_CHANNEL5_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_5_FIRST_REG 0x2940 // INTR_CTLR_CHANNEL5_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL5_5_LAST_REG 0x2964 // INTR_CTLR_CHANNEL5_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_6_FIRST_REG 0x2980 // INTR_CTLR_CHANNEL5_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL5_6_LAST_REG 0x29a4 // INTR_CTLR_CHANNEL5_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_7_FIRST_REG 0x29c0 // INTR_CTLR_CHANNEL5_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL5_7_LAST_REG 0x29e4 // INTR_CTLR_CHANNEL5_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_8_FIRST_REG 0x2a00 // INTR_CTLR_CHANNEL5_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL5_8_LAST_REG 0x2a24 // INTR_CTLR_CHANNEL5_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_9_FIRST_REG 0x2a40 // INTR_CTLR_CHANNEL5_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL5_9_LAST_REG 0x2a64 // INTR_CTLR_CHANNEL5_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_10_FIRST_REG 0x2a80 // INTR_CTLR_CHANNEL5_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL5_10_LAST_REG 0x2aa4 // INTR_CTLR_CHANNEL5_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_11_FIRST_REG 0x2ac0 // INTR_CTLR_CHANNEL5_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL5_11_LAST_REG 0x2ae4 // INTR_CTLR_CHANNEL5_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_12_FIRST_REG 0x2b00 // INTR_CTLR_CHANNEL5_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL5_12_LAST_REG 0x2b24 // INTR_CTLR_CHANNEL5_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_13_FIRST_REG 0x2b40 // INTR_CTLR_CHANNEL5_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL5_13_LAST_REG 0x2b64 // INTR_CTLR_CHANNEL5_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_14_FIRST_REG 0x2b80 // INTR_CTLR_CHANNEL5_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL5_14_LAST_REG 0x2ba4 // INTR_CTLR_CHANNEL5_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_15_FIRST_REG 0x2bc0 // INTR_CTLR_CHANNEL5_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL5_15_LAST_REG 0x2be4 // INTR_CTLR_CHANNEL5_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_16_FIRST_REG 0x2c00 // INTR_CTLR_CHANNEL5_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL5_16_LAST_REG 0x2c24 // INTR_CTLR_CHANNEL5_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL5_SCR_0_FIRST_REG 0x2fc0 // INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRD_0
+#define INTR_CTLR_CHANNEL5_SCR_0_LAST_REG 0x2fc4 // INTR_CTLR_CHANNEL5_SCR_CHANNEL5_SCRE_0
+#define INTR_CTLR_CHANNEL6_0_FIRST_REG 0x3000 // INTR_CTLR_CHANNEL6_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL6_0_LAST_REG 0x3024 // INTR_CTLR_CHANNEL6_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_1_FIRST_REG 0x3040 // INTR_CTLR_CHANNEL6_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL6_1_LAST_REG 0x3064 // INTR_CTLR_CHANNEL6_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_2_FIRST_REG 0x3080 // INTR_CTLR_CHANNEL6_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL6_2_LAST_REG 0x30a4 // INTR_CTLR_CHANNEL6_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_3_FIRST_REG 0x30c0 // INTR_CTLR_CHANNEL6_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL6_3_LAST_REG 0x30e4 // INTR_CTLR_CHANNEL6_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_4_FIRST_REG 0x3100 // INTR_CTLR_CHANNEL6_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL6_4_LAST_REG 0x3124 // INTR_CTLR_CHANNEL6_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_5_FIRST_REG 0x3140 // INTR_CTLR_CHANNEL6_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL6_5_LAST_REG 0x3164 // INTR_CTLR_CHANNEL6_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_6_FIRST_REG 0x3180 // INTR_CTLR_CHANNEL6_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL6_6_LAST_REG 0x31a4 // INTR_CTLR_CHANNEL6_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_7_FIRST_REG 0x31c0 // INTR_CTLR_CHANNEL6_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL6_7_LAST_REG 0x31e4 // INTR_CTLR_CHANNEL6_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_8_FIRST_REG 0x3200 // INTR_CTLR_CHANNEL6_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL6_8_LAST_REG 0x3224 // INTR_CTLR_CHANNEL6_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_9_FIRST_REG 0x3240 // INTR_CTLR_CHANNEL6_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL6_9_LAST_REG 0x3264 // INTR_CTLR_CHANNEL6_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_10_FIRST_REG 0x3280 // INTR_CTLR_CHANNEL6_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL6_10_LAST_REG 0x32a4 // INTR_CTLR_CHANNEL6_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_11_FIRST_REG 0x32c0 // INTR_CTLR_CHANNEL6_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL6_11_LAST_REG 0x32e4 // INTR_CTLR_CHANNEL6_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_12_FIRST_REG 0x3300 // INTR_CTLR_CHANNEL6_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL6_12_LAST_REG 0x3324 // INTR_CTLR_CHANNEL6_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_13_FIRST_REG 0x3340 // INTR_CTLR_CHANNEL6_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL6_13_LAST_REG 0x3364 // INTR_CTLR_CHANNEL6_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_14_FIRST_REG 0x3380 // INTR_CTLR_CHANNEL6_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL6_14_LAST_REG 0x33a4 // INTR_CTLR_CHANNEL6_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_15_FIRST_REG 0x33c0 // INTR_CTLR_CHANNEL6_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL6_15_LAST_REG 0x33e4 // INTR_CTLR_CHANNEL6_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_16_FIRST_REG 0x3400 // INTR_CTLR_CHANNEL6_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL6_16_LAST_REG 0x3424 // INTR_CTLR_CHANNEL6_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL6_SCR_0_FIRST_REG 0x37c0 // INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRD_0
+#define INTR_CTLR_CHANNEL6_SCR_0_LAST_REG 0x37c4 // INTR_CTLR_CHANNEL6_SCR_CHANNEL6_SCRE_0
+#define INTR_CTLR_CHANNEL7_0_FIRST_REG 0x3800 // INTR_CTLR_CHANNEL7_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL7_0_LAST_REG 0x3824 // INTR_CTLR_CHANNEL7_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_1_FIRST_REG 0x3840 // INTR_CTLR_CHANNEL7_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL7_1_LAST_REG 0x3864 // INTR_CTLR_CHANNEL7_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_2_FIRST_REG 0x3880 // INTR_CTLR_CHANNEL7_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL7_2_LAST_REG 0x38a4 // INTR_CTLR_CHANNEL7_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_3_FIRST_REG 0x38c0 // INTR_CTLR_CHANNEL7_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL7_3_LAST_REG 0x38e4 // INTR_CTLR_CHANNEL7_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_4_FIRST_REG 0x3900 // INTR_CTLR_CHANNEL7_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL7_4_LAST_REG 0x3924 // INTR_CTLR_CHANNEL7_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_5_FIRST_REG 0x3940 // INTR_CTLR_CHANNEL7_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL7_5_LAST_REG 0x3964 // INTR_CTLR_CHANNEL7_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_6_FIRST_REG 0x3980 // INTR_CTLR_CHANNEL7_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL7_6_LAST_REG 0x39a4 // INTR_CTLR_CHANNEL7_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_7_FIRST_REG 0x39c0 // INTR_CTLR_CHANNEL7_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL7_7_LAST_REG 0x39e4 // INTR_CTLR_CHANNEL7_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_8_FIRST_REG 0x3a00 // INTR_CTLR_CHANNEL7_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL7_8_LAST_REG 0x3a24 // INTR_CTLR_CHANNEL7_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_9_FIRST_REG 0x3a40 // INTR_CTLR_CHANNEL7_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL7_9_LAST_REG 0x3a64 // INTR_CTLR_CHANNEL7_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_10_FIRST_REG 0x3a80 // INTR_CTLR_CHANNEL7_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL7_10_LAST_REG 0x3aa4 // INTR_CTLR_CHANNEL7_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_11_FIRST_REG 0x3ac0 // INTR_CTLR_CHANNEL7_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL7_11_LAST_REG 0x3ae4 // INTR_CTLR_CHANNEL7_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_12_FIRST_REG 0x3b00 // INTR_CTLR_CHANNEL7_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL7_12_LAST_REG 0x3b24 // INTR_CTLR_CHANNEL7_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_13_FIRST_REG 0x3b40 // INTR_CTLR_CHANNEL7_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL7_13_LAST_REG 0x3b64 // INTR_CTLR_CHANNEL7_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_14_FIRST_REG 0x3b80 // INTR_CTLR_CHANNEL7_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL7_14_LAST_REG 0x3ba4 // INTR_CTLR_CHANNEL7_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_15_FIRST_REG 0x3bc0 // INTR_CTLR_CHANNEL7_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL7_15_LAST_REG 0x3be4 // INTR_CTLR_CHANNEL7_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_16_FIRST_REG 0x3c00 // INTR_CTLR_CHANNEL7_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL7_16_LAST_REG 0x3c24 // INTR_CTLR_CHANNEL7_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL7_SCR_0_FIRST_REG 0x3fc0 // INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRD_0
+#define INTR_CTLR_CHANNEL7_SCR_0_LAST_REG 0x3fc4 // INTR_CTLR_CHANNEL7_SCR_CHANNEL7_SCRE_0
+#define INTR_CTLR_CHANNEL8_0_FIRST_REG 0x4000 // INTR_CTLR_CHANNEL8_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL8_0_LAST_REG 0x4024 // INTR_CTLR_CHANNEL8_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_1_FIRST_REG 0x4040 // INTR_CTLR_CHANNEL8_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL8_1_LAST_REG 0x4064 // INTR_CTLR_CHANNEL8_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_2_FIRST_REG 0x4080 // INTR_CTLR_CHANNEL8_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL8_2_LAST_REG 0x40a4 // INTR_CTLR_CHANNEL8_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_3_FIRST_REG 0x40c0 // INTR_CTLR_CHANNEL8_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL8_3_LAST_REG 0x40e4 // INTR_CTLR_CHANNEL8_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_4_FIRST_REG 0x4100 // INTR_CTLR_CHANNEL8_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL8_4_LAST_REG 0x4124 // INTR_CTLR_CHANNEL8_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_5_FIRST_REG 0x4140 // INTR_CTLR_CHANNEL8_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL8_5_LAST_REG 0x4164 // INTR_CTLR_CHANNEL8_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_6_FIRST_REG 0x4180 // INTR_CTLR_CHANNEL8_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL8_6_LAST_REG 0x41a4 // INTR_CTLR_CHANNEL8_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_7_FIRST_REG 0x41c0 // INTR_CTLR_CHANNEL8_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL8_7_LAST_REG 0x41e4 // INTR_CTLR_CHANNEL8_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_8_FIRST_REG 0x4200 // INTR_CTLR_CHANNEL8_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL8_8_LAST_REG 0x4224 // INTR_CTLR_CHANNEL8_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_9_FIRST_REG 0x4240 // INTR_CTLR_CHANNEL8_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL8_9_LAST_REG 0x4264 // INTR_CTLR_CHANNEL8_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_10_FIRST_REG 0x4280 // INTR_CTLR_CHANNEL8_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL8_10_LAST_REG 0x42a4 // INTR_CTLR_CHANNEL8_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_11_FIRST_REG 0x42c0 // INTR_CTLR_CHANNEL8_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL8_11_LAST_REG 0x42e4 // INTR_CTLR_CHANNEL8_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_12_FIRST_REG 0x4300 // INTR_CTLR_CHANNEL8_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL8_12_LAST_REG 0x4324 // INTR_CTLR_CHANNEL8_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_13_FIRST_REG 0x4340 // INTR_CTLR_CHANNEL8_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL8_13_LAST_REG 0x4364 // INTR_CTLR_CHANNEL8_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_14_FIRST_REG 0x4380 // INTR_CTLR_CHANNEL8_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL8_14_LAST_REG 0x43a4 // INTR_CTLR_CHANNEL8_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_15_FIRST_REG 0x43c0 // INTR_CTLR_CHANNEL8_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL8_15_LAST_REG 0x43e4 // INTR_CTLR_CHANNEL8_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_16_FIRST_REG 0x4400 // INTR_CTLR_CHANNEL8_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL8_16_LAST_REG 0x4424 // INTR_CTLR_CHANNEL8_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL8_SCR_0_FIRST_REG 0x47c0 // INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRD_0
+#define INTR_CTLR_CHANNEL8_SCR_0_LAST_REG 0x47c4 // INTR_CTLR_CHANNEL8_SCR_CHANNEL8_SCRE_0
+#define INTR_CTLR_CHANNEL9_0_FIRST_REG 0x4800 // INTR_CTLR_CHANNEL9_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL9_0_LAST_REG 0x4824 // INTR_CTLR_CHANNEL9_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_1_FIRST_REG 0x4840 // INTR_CTLR_CHANNEL9_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL9_1_LAST_REG 0x4864 // INTR_CTLR_CHANNEL9_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_2_FIRST_REG 0x4880 // INTR_CTLR_CHANNEL9_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL9_2_LAST_REG 0x48a4 // INTR_CTLR_CHANNEL9_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_3_FIRST_REG 0x48c0 // INTR_CTLR_CHANNEL9_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL9_3_LAST_REG 0x48e4 // INTR_CTLR_CHANNEL9_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_4_FIRST_REG 0x4900 // INTR_CTLR_CHANNEL9_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL9_4_LAST_REG 0x4924 // INTR_CTLR_CHANNEL9_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_5_FIRST_REG 0x4940 // INTR_CTLR_CHANNEL9_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL9_5_LAST_REG 0x4964 // INTR_CTLR_CHANNEL9_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_6_FIRST_REG 0x4980 // INTR_CTLR_CHANNEL9_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL9_6_LAST_REG 0x49a4 // INTR_CTLR_CHANNEL9_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_7_FIRST_REG 0x49c0 // INTR_CTLR_CHANNEL9_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL9_7_LAST_REG 0x49e4 // INTR_CTLR_CHANNEL9_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_8_FIRST_REG 0x4a00 // INTR_CTLR_CHANNEL9_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL9_8_LAST_REG 0x4a24 // INTR_CTLR_CHANNEL9_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_9_FIRST_REG 0x4a40 // INTR_CTLR_CHANNEL9_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL9_9_LAST_REG 0x4a64 // INTR_CTLR_CHANNEL9_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_10_FIRST_REG 0x4a80 // INTR_CTLR_CHANNEL9_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL9_10_LAST_REG 0x4aa4 // INTR_CTLR_CHANNEL9_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_11_FIRST_REG 0x4ac0 // INTR_CTLR_CHANNEL9_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL9_11_LAST_REG 0x4ae4 // INTR_CTLR_CHANNEL9_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_12_FIRST_REG 0x4b00 // INTR_CTLR_CHANNEL9_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL9_12_LAST_REG 0x4b24 // INTR_CTLR_CHANNEL9_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_13_FIRST_REG 0x4b40 // INTR_CTLR_CHANNEL9_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL9_13_LAST_REG 0x4b64 // INTR_CTLR_CHANNEL9_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_14_FIRST_REG 0x4b80 // INTR_CTLR_CHANNEL9_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL9_14_LAST_REG 0x4ba4 // INTR_CTLR_CHANNEL9_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_15_FIRST_REG 0x4bc0 // INTR_CTLR_CHANNEL9_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL9_15_LAST_REG 0x4be4 // INTR_CTLR_CHANNEL9_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_16_FIRST_REG 0x4c00 // INTR_CTLR_CHANNEL9_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL9_16_LAST_REG 0x4c24 // INTR_CTLR_CHANNEL9_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL9_SCR_0_FIRST_REG 0x4fc0 // INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRD_0
+#define INTR_CTLR_CHANNEL9_SCR_0_LAST_REG 0x4fc4 // INTR_CTLR_CHANNEL9_SCR_CHANNEL9_SCRE_0
+#define INTR_CTLR_CHANNEL10_0_FIRST_REG 0x5000 // INTR_CTLR_CHANNEL10_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL10_0_LAST_REG 0x5024 // INTR_CTLR_CHANNEL10_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_1_FIRST_REG 0x5040 // INTR_CTLR_CHANNEL10_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL10_1_LAST_REG 0x5064 // INTR_CTLR_CHANNEL10_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_2_FIRST_REG 0x5080 // INTR_CTLR_CHANNEL10_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL10_2_LAST_REG 0x50a4 // INTR_CTLR_CHANNEL10_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_3_FIRST_REG 0x50c0 // INTR_CTLR_CHANNEL10_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL10_3_LAST_REG 0x50e4 // INTR_CTLR_CHANNEL10_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_4_FIRST_REG 0x5100 // INTR_CTLR_CHANNEL10_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL10_4_LAST_REG 0x5124 // INTR_CTLR_CHANNEL10_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_5_FIRST_REG 0x5140 // INTR_CTLR_CHANNEL10_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL10_5_LAST_REG 0x5164 // INTR_CTLR_CHANNEL10_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_6_FIRST_REG 0x5180 // INTR_CTLR_CHANNEL10_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL10_6_LAST_REG 0x51a4 // INTR_CTLR_CHANNEL10_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_7_FIRST_REG 0x51c0 // INTR_CTLR_CHANNEL10_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL10_7_LAST_REG 0x51e4 // INTR_CTLR_CHANNEL10_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_8_FIRST_REG 0x5200 // INTR_CTLR_CHANNEL10_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL10_8_LAST_REG 0x5224 // INTR_CTLR_CHANNEL10_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_9_FIRST_REG 0x5240 // INTR_CTLR_CHANNEL10_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL10_9_LAST_REG 0x5264 // INTR_CTLR_CHANNEL10_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_10_FIRST_REG 0x5280 // INTR_CTLR_CHANNEL10_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL10_10_LAST_REG 0x52a4 // INTR_CTLR_CHANNEL10_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_11_FIRST_REG 0x52c0 // INTR_CTLR_CHANNEL10_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL10_11_LAST_REG 0x52e4 // INTR_CTLR_CHANNEL10_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_12_FIRST_REG 0x5300 // INTR_CTLR_CHANNEL10_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL10_12_LAST_REG 0x5324 // INTR_CTLR_CHANNEL10_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_13_FIRST_REG 0x5340 // INTR_CTLR_CHANNEL10_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL10_13_LAST_REG 0x5364 // INTR_CTLR_CHANNEL10_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_14_FIRST_REG 0x5380 // INTR_CTLR_CHANNEL10_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL10_14_LAST_REG 0x53a4 // INTR_CTLR_CHANNEL10_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_15_FIRST_REG 0x53c0 // INTR_CTLR_CHANNEL10_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL10_15_LAST_REG 0x53e4 // INTR_CTLR_CHANNEL10_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_16_FIRST_REG 0x5400 // INTR_CTLR_CHANNEL10_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL10_16_LAST_REG 0x5424 // INTR_CTLR_CHANNEL10_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL10_SCR_0_FIRST_REG 0x57c0 // INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRD_0
+#define INTR_CTLR_CHANNEL10_SCR_0_LAST_REG 0x57c4 // INTR_CTLR_CHANNEL10_SCR_CHANNEL10_SCRE_0
+#define INTR_CTLR_CHANNEL11_0_FIRST_REG 0x5800 // INTR_CTLR_CHANNEL11_SLICE0_VIRQ_0
+#define INTR_CTLR_CHANNEL11_0_LAST_REG 0x5824 // INTR_CTLR_CHANNEL11_SLICE0_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_1_FIRST_REG 0x5840 // INTR_CTLR_CHANNEL11_SLICE1_VIRQ_0
+#define INTR_CTLR_CHANNEL11_1_LAST_REG 0x5864 // INTR_CTLR_CHANNEL11_SLICE1_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_2_FIRST_REG 0x5880 // INTR_CTLR_CHANNEL11_SLICE2_VIRQ_0
+#define INTR_CTLR_CHANNEL11_2_LAST_REG 0x58a4 // INTR_CTLR_CHANNEL11_SLICE2_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_3_FIRST_REG 0x58c0 // INTR_CTLR_CHANNEL11_SLICE3_VIRQ_0
+#define INTR_CTLR_CHANNEL11_3_LAST_REG 0x58e4 // INTR_CTLR_CHANNEL11_SLICE3_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_4_FIRST_REG 0x5900 // INTR_CTLR_CHANNEL11_SLICE4_VIRQ_0
+#define INTR_CTLR_CHANNEL11_4_LAST_REG 0x5924 // INTR_CTLR_CHANNEL11_SLICE4_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_5_FIRST_REG 0x5940 // INTR_CTLR_CHANNEL11_SLICE5_VIRQ_0
+#define INTR_CTLR_CHANNEL11_5_LAST_REG 0x5964 // INTR_CTLR_CHANNEL11_SLICE5_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_6_FIRST_REG 0x5980 // INTR_CTLR_CHANNEL11_SLICE6_VIRQ_0
+#define INTR_CTLR_CHANNEL11_6_LAST_REG 0x59a4 // INTR_CTLR_CHANNEL11_SLICE6_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_7_FIRST_REG 0x59c0 // INTR_CTLR_CHANNEL11_SLICE7_VIRQ_0
+#define INTR_CTLR_CHANNEL11_7_LAST_REG 0x59e4 // INTR_CTLR_CHANNEL11_SLICE7_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_8_FIRST_REG 0x5a00 // INTR_CTLR_CHANNEL11_SLICE8_VIRQ_0
+#define INTR_CTLR_CHANNEL11_8_LAST_REG 0x5a24 // INTR_CTLR_CHANNEL11_SLICE8_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_9_FIRST_REG 0x5a40 // INTR_CTLR_CHANNEL11_SLICE9_VIRQ_0
+#define INTR_CTLR_CHANNEL11_9_LAST_REG 0x5a64 // INTR_CTLR_CHANNEL11_SLICE9_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_10_FIRST_REG 0x5a80 // INTR_CTLR_CHANNEL11_SLICE10_VIRQ_0
+#define INTR_CTLR_CHANNEL11_10_LAST_REG 0x5aa4 // INTR_CTLR_CHANNEL11_SLICE10_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_11_FIRST_REG 0x5ac0 // INTR_CTLR_CHANNEL11_SLICE11_VIRQ_0
+#define INTR_CTLR_CHANNEL11_11_LAST_REG 0x5ae4 // INTR_CTLR_CHANNEL11_SLICE11_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_12_FIRST_REG 0x5b00 // INTR_CTLR_CHANNEL11_SLICE12_VIRQ_0
+#define INTR_CTLR_CHANNEL11_12_LAST_REG 0x5b24 // INTR_CTLR_CHANNEL11_SLICE12_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_13_FIRST_REG 0x5b40 // INTR_CTLR_CHANNEL11_SLICE13_VIRQ_0
+#define INTR_CTLR_CHANNEL11_13_LAST_REG 0x5b64 // INTR_CTLR_CHANNEL11_SLICE13_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_14_FIRST_REG 0x5b80 // INTR_CTLR_CHANNEL11_SLICE14_VIRQ_0
+#define INTR_CTLR_CHANNEL11_14_LAST_REG 0x5ba4 // INTR_CTLR_CHANNEL11_SLICE14_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_15_FIRST_REG 0x5bc0 // INTR_CTLR_CHANNEL11_SLICE15_VIRQ_0
+#define INTR_CTLR_CHANNEL11_15_LAST_REG 0x5be4 // INTR_CTLR_CHANNEL11_SLICE15_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_16_FIRST_REG 0x5c00 // INTR_CTLR_CHANNEL11_SLICE16_VIRQ_0
+#define INTR_CTLR_CHANNEL11_16_LAST_REG 0x5c24 // INTR_CTLR_CHANNEL11_SLICE16_IDR_CLR_0
+#define INTR_CTLR_CHANNEL11_SCR_0_FIRST_REG 0x5fc0 // INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRD_0
+#define INTR_CTLR_CHANNEL11_SCR_0_LAST_REG 0x5fc4 // INTR_CTLR_CHANNEL11_SCR_CHANNEL11_SCRE_0
+#define INTR_CTLR_COMMON_0_FIRST_REG 0xf800 // INTR_CTLR_COMMON_SLICE0_GISR_0
+#define INTR_CTLR_COMMON_0_LAST_REG 0xf818 // INTR_CTLR_COMMON_SLICE0_CIDR_CLR_0
+#define INTR_CTLR_COMMON_1_FIRST_REG 0xf840 // INTR_CTLR_COMMON_SLICE1_GISR_0
+#define INTR_CTLR_COMMON_1_LAST_REG 0xf858 // INTR_CTLR_COMMON_SLICE1_CIDR_CLR_0
+#define INTR_CTLR_COMMON_2_FIRST_REG 0xf880 // INTR_CTLR_COMMON_SLICE2_GISR_0
+#define INTR_CTLR_COMMON_2_LAST_REG 0xf898 // INTR_CTLR_COMMON_SLICE2_CIDR_CLR_0
+#define INTR_CTLR_COMMON_3_FIRST_REG 0xf8c0 // INTR_CTLR_COMMON_SLICE3_GISR_0
+#define INTR_CTLR_COMMON_3_LAST_REG 0xf8d8 // INTR_CTLR_COMMON_SLICE3_CIDR_CLR_0
+#define INTR_CTLR_COMMON_4_FIRST_REG 0xf900 // INTR_CTLR_COMMON_SLICE4_GISR_0
+#define INTR_CTLR_COMMON_4_LAST_REG 0xf918 // INTR_CTLR_COMMON_SLICE4_CIDR_CLR_0
+#define INTR_CTLR_COMMON_5_FIRST_REG 0xf940 // INTR_CTLR_COMMON_SLICE5_GISR_0
+#define INTR_CTLR_COMMON_5_LAST_REG 0xf958 // INTR_CTLR_COMMON_SLICE5_CIDR_CLR_0
+#define INTR_CTLR_COMMON_6_FIRST_REG 0xf980 // INTR_CTLR_COMMON_SLICE6_GISR_0
+#define INTR_CTLR_COMMON_6_LAST_REG 0xf998 // INTR_CTLR_COMMON_SLICE6_CIDR_CLR_0
+#define INTR_CTLR_COMMON_7_FIRST_REG 0xf9c0 // INTR_CTLR_COMMON_SLICE7_GISR_0
+#define INTR_CTLR_COMMON_7_LAST_REG 0xf9d8 // INTR_CTLR_COMMON_SLICE7_CIDR_CLR_0
+#define INTR_CTLR_COMMON_8_FIRST_REG 0xfa00 // INTR_CTLR_COMMON_SLICE8_GISR_0
+#define INTR_CTLR_COMMON_8_LAST_REG 0xfa18 // INTR_CTLR_COMMON_SLICE8_CIDR_CLR_0
+#define INTR_CTLR_COMMON_9_FIRST_REG 0xfa40 // INTR_CTLR_COMMON_SLICE9_GISR_0
+#define INTR_CTLR_COMMON_9_LAST_REG 0xfa58 // INTR_CTLR_COMMON_SLICE9_CIDR_CLR_0
+#define INTR_CTLR_COMMON_10_FIRST_REG 0xfa80 // INTR_CTLR_COMMON_SLICE10_GISR_0
+#define INTR_CTLR_COMMON_10_LAST_REG 0xfa98 // INTR_CTLR_COMMON_SLICE10_CIDR_CLR_0
+#define INTR_CTLR_COMMON_11_FIRST_REG 0xfac0 // INTR_CTLR_COMMON_SLICE11_GISR_0
+#define INTR_CTLR_COMMON_11_LAST_REG 0xfad8 // INTR_CTLR_COMMON_SLICE11_CIDR_CLR_0
+#define INTR_CTLR_COMMON_12_FIRST_REG 0xfb00 // INTR_CTLR_COMMON_SLICE12_GISR_0
+#define INTR_CTLR_COMMON_12_LAST_REG 0xfb18 // INTR_CTLR_COMMON_SLICE12_CIDR_CLR_0
+#define INTR_CTLR_COMMON_13_FIRST_REG 0xfb40 // INTR_CTLR_COMMON_SLICE13_GISR_0
+#define INTR_CTLR_COMMON_13_LAST_REG 0xfb58 // INTR_CTLR_COMMON_SLICE13_CIDR_CLR_0
+#define INTR_CTLR_COMMON_14_FIRST_REG 0xfb80 // INTR_CTLR_COMMON_SLICE14_GISR_0
+#define INTR_CTLR_COMMON_14_LAST_REG 0xfb98 // INTR_CTLR_COMMON_SLICE14_CIDR_CLR_0
+#define INTR_CTLR_COMMON_15_FIRST_REG 0xfbc0 // INTR_CTLR_COMMON_SLICE15_GISR_0
+#define INTR_CTLR_COMMON_15_LAST_REG 0xfbd8 // INTR_CTLR_COMMON_SLICE15_CIDR_CLR_0
+#define INTR_CTLR_COMMON_16_FIRST_REG 0xfc00 // INTR_CTLR_COMMON_SLICE16_GISR_0
+#define INTR_CTLR_COMMON_16_LAST_REG 0xfc18 // INTR_CTLR_COMMON_SLICE16_CIDR_CLR_0
+#define INTR_CTLR_COMMON_SCR_0_FIRST_REG 0xffc4 // INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+#define INTR_CTLR_COMMON_SCR_0_LAST_REG 0xffc4 // INTR_CTLR_COMMON_SCR_SCR_COMMON_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARINTR_CTLR_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arpadctl_AO.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arpadctl_AO.h
new file mode 100644
index 0000000..a6abca6
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arpadctl_AO.h
@@ -0,0 +1,2339 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARPADCTL_AO_H_INC
+#define ARPADCTL_AO_H_INC
+#define NV_MOBILE_ARPADCTL_AO_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARPADCTL_AO_H_SCRREG_NOMENCLATURE INFERRED
+
+
+// Register PADCTL_AO_TOUCH_CLK_0
+#define PADCTL_AO_TOUCH_CLK_0                   MK_ADDR_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_SECURE                    0x0
+#define PADCTL_AO_TOUCH_CLK_0_DUAL                      0x0
+#define PADCTL_AO_TOUCH_CLK_0_SCR                       SCR_TOUCH_CLK_0
+#define PADCTL_AO_TOUCH_CLK_0_SCRREG                    PADCTL_AO_SCR_SCR_TOUCH_CLK_0
+#define PADCTL_AO_TOUCH_CLK_0_WORD_COUNT                        0x1
+#define PADCTL_AO_TOUCH_CLK_0_RESET_VAL                         MK_MASK_CONST(0x430)
+#define PADCTL_AO_TOUCH_CLK_0_RESET_MASK                        MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_TOUCH_CLK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_READ_MASK                         MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_TOUCH_CLK_0_WRITE_MASK                        MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_TOUCH_CLK_0_PM_SHIFT                  MK_SHIFT_CONST(0)
+#define PADCTL_AO_TOUCH_CLK_0_PM_FIELD                  MK_FIELD_CONST(0x3, PADCTL_AO_TOUCH_CLK_0_PM_SHIFT)
+#define PADCTL_AO_TOUCH_CLK_0_PM_RANGE                  1:0
+#define PADCTL_AO_TOUCH_CLK_0_PM_MSB                    MK_SHIFT_CONST(1)
+#define PADCTL_AO_TOUCH_CLK_0_PM_LSB                    MK_SHIFT_CONST(0)
+#define PADCTL_AO_TOUCH_CLK_0_PM_WOFFSET                        0x0
+#define PADCTL_AO_TOUCH_CLK_0_PM_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_PM_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define PADCTL_AO_TOUCH_CLK_0_PM_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_PM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_PM_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_PM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_PM_INIT_ENUM                      GP
+#define PADCTL_AO_TOUCH_CLK_0_PM_GP                     MK_ENUM_CONST(0)
+#define PADCTL_AO_TOUCH_CLK_0_PM_TOUCH                  MK_ENUM_CONST(1)
+#define PADCTL_AO_TOUCH_CLK_0_PM_RSVD2                  MK_ENUM_CONST(2)
+#define PADCTL_AO_TOUCH_CLK_0_PM_RSVD3                  MK_ENUM_CONST(3)
+
+#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_SHIFT                 MK_SHIFT_CONST(10)
+#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_FIELD                 MK_FIELD_CONST(0x1, PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_SHIFT)
+#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_RANGE                 10:10
+#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_MSB                   MK_SHIFT_CONST(10)
+#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_LSB                   MK_SHIFT_CONST(10)
+#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_WOFFSET                       0x0
+#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_DEFAULT                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_INIT_ENUM                     SFIO
+#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_GPIO                  MK_ENUM_CONST(0)
+#define PADCTL_AO_TOUCH_CLK_0_GPIO_SF_SEL_SFIO                  MK_ENUM_CONST(1)
+
+#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_SHIFT                    MK_SHIFT_CONST(4)
+#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_FIELD                    MK_FIELD_CONST(0x1, PADCTL_AO_TOUCH_CLK_0_TRISTATE_SHIFT)
+#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_RANGE                    4:4
+#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_MSB                      MK_SHIFT_CONST(4)
+#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_LSB                      MK_SHIFT_CONST(4)
+#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_WOFFSET                  0x0
+#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_DEFAULT                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_INIT_ENUM                        TRISTATE
+#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_PASSTHROUGH                      MK_ENUM_CONST(0)
+#define PADCTL_AO_TOUCH_CLK_0_TRISTATE_TRISTATE                 MK_ENUM_CONST(1)
+
+#define PADCTL_AO_TOUCH_CLK_0_PUPD_SHIFT                        MK_SHIFT_CONST(2)
+#define PADCTL_AO_TOUCH_CLK_0_PUPD_FIELD                        MK_FIELD_CONST(0x3, PADCTL_AO_TOUCH_CLK_0_PUPD_SHIFT)
+#define PADCTL_AO_TOUCH_CLK_0_PUPD_RANGE                        3:2
+#define PADCTL_AO_TOUCH_CLK_0_PUPD_MSB                  MK_SHIFT_CONST(3)
+#define PADCTL_AO_TOUCH_CLK_0_PUPD_LSB                  MK_SHIFT_CONST(2)
+#define PADCTL_AO_TOUCH_CLK_0_PUPD_WOFFSET                      0x0
+#define PADCTL_AO_TOUCH_CLK_0_PUPD_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_PUPD_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define PADCTL_AO_TOUCH_CLK_0_PUPD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_PUPD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_PUPD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_PUPD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_PUPD_INIT_ENUM                    NONE
+#define PADCTL_AO_TOUCH_CLK_0_PUPD_NONE                 MK_ENUM_CONST(0)
+#define PADCTL_AO_TOUCH_CLK_0_PUPD_PULL_DOWN                    MK_ENUM_CONST(1)
+#define PADCTL_AO_TOUCH_CLK_0_PUPD_PULL_UP                      MK_ENUM_CONST(2)
+#define PADCTL_AO_TOUCH_CLK_0_PUPD_RSVD                 MK_ENUM_CONST(3)
+
+#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_SHIFT                     MK_SHIFT_CONST(6)
+#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_TOUCH_CLK_0_E_INPUT_SHIFT)
+#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_RANGE                     6:6
+#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_MSB                       MK_SHIFT_CONST(6)
+#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_LSB                       MK_SHIFT_CONST(6)
+#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_WOFFSET                   0x0
+#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_INIT_ENUM                 DISABLE
+#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_DISABLE                   MK_ENUM_CONST(0)
+#define PADCTL_AO_TOUCH_CLK_0_E_INPUT_ENABLE                    MK_ENUM_CONST(1)
+
+#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_SHIFT                      MK_SHIFT_CONST(7)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_TOUCH_CLK_0_E_LPBK_SHIFT)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_RANGE                      7:7
+#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_MSB                        MK_SHIFT_CONST(7)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_LSB                        MK_SHIFT_CONST(7)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_WOFFSET                    0x0
+#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_INIT_ENUM                  DISABLE
+#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPBK_ENABLE                     MK_ENUM_CONST(1)
+
+#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_SHIFT                      MK_SHIFT_CONST(8)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_TOUCH_CLK_0_E_LPDR_SHIFT)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_RANGE                      8:8
+#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_MSB                        MK_SHIFT_CONST(8)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_LSB                        MK_SHIFT_CONST(8)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_WOFFSET                    0x0
+#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_INIT_ENUM                  DISABLE
+#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_TOUCH_CLK_0_E_LPDR_ENABLE                     MK_ENUM_CONST(1)
+
+#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_SHIFT                     MK_SHIFT_CONST(5)
+#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_TOUCH_CLK_0_E_IO_HV_SHIFT)
+#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_RANGE                     5:5
+#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_MSB                       MK_SHIFT_CONST(5)
+#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_LSB                       MK_SHIFT_CONST(5)
+#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_WOFFSET                   0x0
+#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_DEFAULT                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_INIT_ENUM                 ENABLE
+#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_DISABLE                   MK_ENUM_CONST(0)
+#define PADCTL_AO_TOUCH_CLK_0_E_IO_HV_ENABLE                    MK_ENUM_CONST(1)
+
+#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_SHIFT                     MK_SHIFT_CONST(12)
+#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_TOUCH_CLK_0_E_SCHMT_SHIFT)
+#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_RANGE                     12:12
+#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_MSB                       MK_SHIFT_CONST(12)
+#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_LSB                       MK_SHIFT_CONST(12)
+#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_WOFFSET                   0x0
+#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_INIT_ENUM                 DISABLE
+#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_DISABLE                   MK_ENUM_CONST(0)
+#define PADCTL_AO_TOUCH_CLK_0_E_SCHMT_ENABLE                    MK_ENUM_CONST(1)
+
+
+// Register PADCTL_AO_CFG2TMC_TOUCH_CLK_0
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0                   MK_ADDR_CONST(0x4)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_SECURE                    0x0
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_DUAL                      0x0
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_SCR                       SCR_TOUCH_CLK_0
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_SCRREG                    PADCTL_AO_SCR_SCR_TOUCH_CLK_0
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_WORD_COUNT                        0x1
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_RESET_MASK                        MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_READ_MASK                         MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_WRITE_MASK                        MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_SHIFT                       MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_FIELD                       MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_SHIFT)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_RANGE                       16:12
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_MSB                 MK_SHIFT_CONST(16)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_LSB                 MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_WOFFSET                     0x0
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_SHIFT                       MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_FIELD                       MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_SHIFT)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_RANGE                       24:20
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_MSB                 MK_SHIFT_CONST(24)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_LSB                 MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_WOFFSET                     0x0
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_TOUCH_CLK_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register PADCTL_AO_UART3_RX_0
+#define PADCTL_AO_UART3_RX_0                    MK_ADDR_CONST(0x8)
+#define PADCTL_AO_UART3_RX_0_SECURE                     0x0
+#define PADCTL_AO_UART3_RX_0_DUAL                       0x0
+#define PADCTL_AO_UART3_RX_0_SCR                        SCR_UART3_RX_0
+#define PADCTL_AO_UART3_RX_0_SCRREG                     PADCTL_AO_SCR_SCR_UART3_RX_0
+#define PADCTL_AO_UART3_RX_0_WORD_COUNT                         0x1
+#define PADCTL_AO_UART3_RX_0_RESET_VAL                  MK_MASK_CONST(0x474)
+#define PADCTL_AO_UART3_RX_0_RESET_MASK                         MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_UART3_RX_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_READ_MASK                  MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_UART3_RX_0_WRITE_MASK                         MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_UART3_RX_0_PM_SHIFT                   MK_SHIFT_CONST(0)
+#define PADCTL_AO_UART3_RX_0_PM_FIELD                   MK_FIELD_CONST(0x3, PADCTL_AO_UART3_RX_0_PM_SHIFT)
+#define PADCTL_AO_UART3_RX_0_PM_RANGE                   1:0
+#define PADCTL_AO_UART3_RX_0_PM_MSB                     MK_SHIFT_CONST(1)
+#define PADCTL_AO_UART3_RX_0_PM_LSB                     MK_SHIFT_CONST(0)
+#define PADCTL_AO_UART3_RX_0_PM_WOFFSET                 0x0
+#define PADCTL_AO_UART3_RX_0_PM_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_PM_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define PADCTL_AO_UART3_RX_0_PM_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_PM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_PM_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_PM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_PM_INIT_ENUM                       UARTC
+#define PADCTL_AO_UART3_RX_0_PM_UARTC                   MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_RX_0_PM_UARTJ                   MK_ENUM_CONST(1)
+#define PADCTL_AO_UART3_RX_0_PM_RSVD2                   MK_ENUM_CONST(2)
+#define PADCTL_AO_UART3_RX_0_PM_RSVD3                   MK_ENUM_CONST(3)
+
+#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_SHIFT                  MK_SHIFT_CONST(10)
+#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_SHIFT)
+#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_RANGE                  10:10
+#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_MSB                    MK_SHIFT_CONST(10)
+#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_LSB                    MK_SHIFT_CONST(10)
+#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_WOFFSET                        0x0
+#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_DEFAULT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_INIT_ENUM                      SFIO
+#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_GPIO                   MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_RX_0_GPIO_SF_SEL_SFIO                   MK_ENUM_CONST(1)
+
+#define PADCTL_AO_UART3_RX_0_TRISTATE_SHIFT                     MK_SHIFT_CONST(4)
+#define PADCTL_AO_UART3_RX_0_TRISTATE_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_UART3_RX_0_TRISTATE_SHIFT)
+#define PADCTL_AO_UART3_RX_0_TRISTATE_RANGE                     4:4
+#define PADCTL_AO_UART3_RX_0_TRISTATE_MSB                       MK_SHIFT_CONST(4)
+#define PADCTL_AO_UART3_RX_0_TRISTATE_LSB                       MK_SHIFT_CONST(4)
+#define PADCTL_AO_UART3_RX_0_TRISTATE_WOFFSET                   0x0
+#define PADCTL_AO_UART3_RX_0_TRISTATE_DEFAULT                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_TRISTATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_TRISTATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_TRISTATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_TRISTATE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_TRISTATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_TRISTATE_INIT_ENUM                 TRISTATE
+#define PADCTL_AO_UART3_RX_0_TRISTATE_PASSTHROUGH                       MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_RX_0_TRISTATE_TRISTATE                  MK_ENUM_CONST(1)
+
+#define PADCTL_AO_UART3_RX_0_PUPD_SHIFT                 MK_SHIFT_CONST(2)
+#define PADCTL_AO_UART3_RX_0_PUPD_FIELD                 MK_FIELD_CONST(0x3, PADCTL_AO_UART3_RX_0_PUPD_SHIFT)
+#define PADCTL_AO_UART3_RX_0_PUPD_RANGE                 3:2
+#define PADCTL_AO_UART3_RX_0_PUPD_MSB                   MK_SHIFT_CONST(3)
+#define PADCTL_AO_UART3_RX_0_PUPD_LSB                   MK_SHIFT_CONST(2)
+#define PADCTL_AO_UART3_RX_0_PUPD_WOFFSET                       0x0
+#define PADCTL_AO_UART3_RX_0_PUPD_DEFAULT                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_PUPD_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PADCTL_AO_UART3_RX_0_PUPD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_PUPD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_PUPD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_PUPD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_PUPD_INIT_ENUM                     PULL_DOWN
+#define PADCTL_AO_UART3_RX_0_PUPD_NONE                  MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_RX_0_PUPD_PULL_DOWN                     MK_ENUM_CONST(1)
+#define PADCTL_AO_UART3_RX_0_PUPD_PULL_UP                       MK_ENUM_CONST(2)
+#define PADCTL_AO_UART3_RX_0_PUPD_RSVD                  MK_ENUM_CONST(3)
+
+#define PADCTL_AO_UART3_RX_0_E_INPUT_SHIFT                      MK_SHIFT_CONST(6)
+#define PADCTL_AO_UART3_RX_0_E_INPUT_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_UART3_RX_0_E_INPUT_SHIFT)
+#define PADCTL_AO_UART3_RX_0_E_INPUT_RANGE                      6:6
+#define PADCTL_AO_UART3_RX_0_E_INPUT_MSB                        MK_SHIFT_CONST(6)
+#define PADCTL_AO_UART3_RX_0_E_INPUT_LSB                        MK_SHIFT_CONST(6)
+#define PADCTL_AO_UART3_RX_0_E_INPUT_WOFFSET                    0x0
+#define PADCTL_AO_UART3_RX_0_E_INPUT_DEFAULT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_E_INPUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_E_INPUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_E_INPUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_E_INPUT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_E_INPUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_E_INPUT_INIT_ENUM                  ENABLE
+#define PADCTL_AO_UART3_RX_0_E_INPUT_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_RX_0_E_INPUT_ENABLE                     MK_ENUM_CONST(1)
+
+#define PADCTL_AO_UART3_RX_0_E_LPBK_SHIFT                       MK_SHIFT_CONST(7)
+#define PADCTL_AO_UART3_RX_0_E_LPBK_FIELD                       MK_FIELD_CONST(0x1, PADCTL_AO_UART3_RX_0_E_LPBK_SHIFT)
+#define PADCTL_AO_UART3_RX_0_E_LPBK_RANGE                       7:7
+#define PADCTL_AO_UART3_RX_0_E_LPBK_MSB                 MK_SHIFT_CONST(7)
+#define PADCTL_AO_UART3_RX_0_E_LPBK_LSB                 MK_SHIFT_CONST(7)
+#define PADCTL_AO_UART3_RX_0_E_LPBK_WOFFSET                     0x0
+#define PADCTL_AO_UART3_RX_0_E_LPBK_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_E_LPBK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_E_LPBK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_E_LPBK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_E_LPBK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_E_LPBK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_E_LPBK_INIT_ENUM                   DISABLE
+#define PADCTL_AO_UART3_RX_0_E_LPBK_DISABLE                     MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_RX_0_E_LPBK_ENABLE                      MK_ENUM_CONST(1)
+
+#define PADCTL_AO_UART3_RX_0_E_LPDR_SHIFT                       MK_SHIFT_CONST(8)
+#define PADCTL_AO_UART3_RX_0_E_LPDR_FIELD                       MK_FIELD_CONST(0x1, PADCTL_AO_UART3_RX_0_E_LPDR_SHIFT)
+#define PADCTL_AO_UART3_RX_0_E_LPDR_RANGE                       8:8
+#define PADCTL_AO_UART3_RX_0_E_LPDR_MSB                 MK_SHIFT_CONST(8)
+#define PADCTL_AO_UART3_RX_0_E_LPDR_LSB                 MK_SHIFT_CONST(8)
+#define PADCTL_AO_UART3_RX_0_E_LPDR_WOFFSET                     0x0
+#define PADCTL_AO_UART3_RX_0_E_LPDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_E_LPDR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_E_LPDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_E_LPDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_E_LPDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_E_LPDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_E_LPDR_INIT_ENUM                   DISABLE
+#define PADCTL_AO_UART3_RX_0_E_LPDR_DISABLE                     MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_RX_0_E_LPDR_ENABLE                      MK_ENUM_CONST(1)
+
+#define PADCTL_AO_UART3_RX_0_E_IO_HV_SHIFT                      MK_SHIFT_CONST(5)
+#define PADCTL_AO_UART3_RX_0_E_IO_HV_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_UART3_RX_0_E_IO_HV_SHIFT)
+#define PADCTL_AO_UART3_RX_0_E_IO_HV_RANGE                      5:5
+#define PADCTL_AO_UART3_RX_0_E_IO_HV_MSB                        MK_SHIFT_CONST(5)
+#define PADCTL_AO_UART3_RX_0_E_IO_HV_LSB                        MK_SHIFT_CONST(5)
+#define PADCTL_AO_UART3_RX_0_E_IO_HV_WOFFSET                    0x0
+#define PADCTL_AO_UART3_RX_0_E_IO_HV_DEFAULT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_E_IO_HV_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_E_IO_HV_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_E_IO_HV_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_E_IO_HV_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_E_IO_HV_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_E_IO_HV_INIT_ENUM                  ENABLE
+#define PADCTL_AO_UART3_RX_0_E_IO_HV_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_RX_0_E_IO_HV_ENABLE                     MK_ENUM_CONST(1)
+
+#define PADCTL_AO_UART3_RX_0_E_SCHMT_SHIFT                      MK_SHIFT_CONST(12)
+#define PADCTL_AO_UART3_RX_0_E_SCHMT_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_UART3_RX_0_E_SCHMT_SHIFT)
+#define PADCTL_AO_UART3_RX_0_E_SCHMT_RANGE                      12:12
+#define PADCTL_AO_UART3_RX_0_E_SCHMT_MSB                        MK_SHIFT_CONST(12)
+#define PADCTL_AO_UART3_RX_0_E_SCHMT_LSB                        MK_SHIFT_CONST(12)
+#define PADCTL_AO_UART3_RX_0_E_SCHMT_WOFFSET                    0x0
+#define PADCTL_AO_UART3_RX_0_E_SCHMT_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_E_SCHMT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_E_SCHMT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_E_SCHMT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_RX_0_E_SCHMT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_E_SCHMT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_RX_0_E_SCHMT_INIT_ENUM                  DISABLE
+#define PADCTL_AO_UART3_RX_0_E_SCHMT_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_RX_0_E_SCHMT_ENABLE                     MK_ENUM_CONST(1)
+
+
+// Register PADCTL_AO_CFG2TMC_UART3_RX_0
+#define PADCTL_AO_CFG2TMC_UART3_RX_0                    MK_ADDR_CONST(0xc)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_SECURE                     0x0
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_DUAL                       0x0
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_SCR                        SCR_UART3_RX_0
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_SCRREG                     PADCTL_AO_SCR_SCR_UART3_RX_0
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_WORD_COUNT                         0x1
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_RESET_MASK                         MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_READ_MASK                  MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_WRITE_MASK                         MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_SHIFT                        MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_FIELD                        MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_SHIFT)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_RANGE                        16:12
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_MSB                  MK_SHIFT_CONST(16)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_LSB                  MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_WOFFSET                      0x0
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_SHIFT                        MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_FIELD                        MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_SHIFT)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_RANGE                        24:20
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_MSB                  MK_SHIFT_CONST(24)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_LSB                  MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_WOFFSET                      0x0
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_UART3_RX_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register PADCTL_AO_UART3_TX_0
+#define PADCTL_AO_UART3_TX_0                    MK_ADDR_CONST(0x10)
+#define PADCTL_AO_UART3_TX_0_SECURE                     0x0
+#define PADCTL_AO_UART3_TX_0_DUAL                       0x0
+#define PADCTL_AO_UART3_TX_0_SCR                        SCR_UART3_TX_0
+#define PADCTL_AO_UART3_TX_0_SCRREG                     PADCTL_AO_SCR_SCR_UART3_TX_0
+#define PADCTL_AO_UART3_TX_0_WORD_COUNT                         0x1
+#define PADCTL_AO_UART3_TX_0_RESET_VAL                  MK_MASK_CONST(0x434)
+#define PADCTL_AO_UART3_TX_0_RESET_MASK                         MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_UART3_TX_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_READ_MASK                  MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_UART3_TX_0_WRITE_MASK                         MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_UART3_TX_0_PM_SHIFT                   MK_SHIFT_CONST(0)
+#define PADCTL_AO_UART3_TX_0_PM_FIELD                   MK_FIELD_CONST(0x3, PADCTL_AO_UART3_TX_0_PM_SHIFT)
+#define PADCTL_AO_UART3_TX_0_PM_RANGE                   1:0
+#define PADCTL_AO_UART3_TX_0_PM_MSB                     MK_SHIFT_CONST(1)
+#define PADCTL_AO_UART3_TX_0_PM_LSB                     MK_SHIFT_CONST(0)
+#define PADCTL_AO_UART3_TX_0_PM_WOFFSET                 0x0
+#define PADCTL_AO_UART3_TX_0_PM_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_PM_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define PADCTL_AO_UART3_TX_0_PM_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_PM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_PM_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_PM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_PM_INIT_ENUM                       UARTC
+#define PADCTL_AO_UART3_TX_0_PM_UARTC                   MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_TX_0_PM_UARTJ                   MK_ENUM_CONST(1)
+#define PADCTL_AO_UART3_TX_0_PM_RSVD2                   MK_ENUM_CONST(2)
+#define PADCTL_AO_UART3_TX_0_PM_RSVD3                   MK_ENUM_CONST(3)
+
+#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_SHIFT                  MK_SHIFT_CONST(10)
+#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_SHIFT)
+#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_RANGE                  10:10
+#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_MSB                    MK_SHIFT_CONST(10)
+#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_LSB                    MK_SHIFT_CONST(10)
+#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_WOFFSET                        0x0
+#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_DEFAULT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_INIT_ENUM                      SFIO
+#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_GPIO                   MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_TX_0_GPIO_SF_SEL_SFIO                   MK_ENUM_CONST(1)
+
+#define PADCTL_AO_UART3_TX_0_TRISTATE_SHIFT                     MK_SHIFT_CONST(4)
+#define PADCTL_AO_UART3_TX_0_TRISTATE_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_UART3_TX_0_TRISTATE_SHIFT)
+#define PADCTL_AO_UART3_TX_0_TRISTATE_RANGE                     4:4
+#define PADCTL_AO_UART3_TX_0_TRISTATE_MSB                       MK_SHIFT_CONST(4)
+#define PADCTL_AO_UART3_TX_0_TRISTATE_LSB                       MK_SHIFT_CONST(4)
+#define PADCTL_AO_UART3_TX_0_TRISTATE_WOFFSET                   0x0
+#define PADCTL_AO_UART3_TX_0_TRISTATE_DEFAULT                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_TRISTATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_TRISTATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_TRISTATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_TRISTATE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_TRISTATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_TRISTATE_INIT_ENUM                 TRISTATE
+#define PADCTL_AO_UART3_TX_0_TRISTATE_PASSTHROUGH                       MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_TX_0_TRISTATE_TRISTATE                  MK_ENUM_CONST(1)
+
+#define PADCTL_AO_UART3_TX_0_PUPD_SHIFT                 MK_SHIFT_CONST(2)
+#define PADCTL_AO_UART3_TX_0_PUPD_FIELD                 MK_FIELD_CONST(0x3, PADCTL_AO_UART3_TX_0_PUPD_SHIFT)
+#define PADCTL_AO_UART3_TX_0_PUPD_RANGE                 3:2
+#define PADCTL_AO_UART3_TX_0_PUPD_MSB                   MK_SHIFT_CONST(3)
+#define PADCTL_AO_UART3_TX_0_PUPD_LSB                   MK_SHIFT_CONST(2)
+#define PADCTL_AO_UART3_TX_0_PUPD_WOFFSET                       0x0
+#define PADCTL_AO_UART3_TX_0_PUPD_DEFAULT                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_PUPD_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PADCTL_AO_UART3_TX_0_PUPD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_PUPD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_PUPD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_PUPD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_PUPD_INIT_ENUM                     PULL_DOWN
+#define PADCTL_AO_UART3_TX_0_PUPD_NONE                  MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_TX_0_PUPD_PULL_DOWN                     MK_ENUM_CONST(1)
+#define PADCTL_AO_UART3_TX_0_PUPD_PULL_UP                       MK_ENUM_CONST(2)
+#define PADCTL_AO_UART3_TX_0_PUPD_RSVD                  MK_ENUM_CONST(3)
+
+#define PADCTL_AO_UART3_TX_0_E_INPUT_SHIFT                      MK_SHIFT_CONST(6)
+#define PADCTL_AO_UART3_TX_0_E_INPUT_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_UART3_TX_0_E_INPUT_SHIFT)
+#define PADCTL_AO_UART3_TX_0_E_INPUT_RANGE                      6:6
+#define PADCTL_AO_UART3_TX_0_E_INPUT_MSB                        MK_SHIFT_CONST(6)
+#define PADCTL_AO_UART3_TX_0_E_INPUT_LSB                        MK_SHIFT_CONST(6)
+#define PADCTL_AO_UART3_TX_0_E_INPUT_WOFFSET                    0x0
+#define PADCTL_AO_UART3_TX_0_E_INPUT_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_E_INPUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_E_INPUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_E_INPUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_E_INPUT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_E_INPUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_E_INPUT_INIT_ENUM                  DISABLE
+#define PADCTL_AO_UART3_TX_0_E_INPUT_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_TX_0_E_INPUT_ENABLE                     MK_ENUM_CONST(1)
+
+#define PADCTL_AO_UART3_TX_0_E_LPBK_SHIFT                       MK_SHIFT_CONST(7)
+#define PADCTL_AO_UART3_TX_0_E_LPBK_FIELD                       MK_FIELD_CONST(0x1, PADCTL_AO_UART3_TX_0_E_LPBK_SHIFT)
+#define PADCTL_AO_UART3_TX_0_E_LPBK_RANGE                       7:7
+#define PADCTL_AO_UART3_TX_0_E_LPBK_MSB                 MK_SHIFT_CONST(7)
+#define PADCTL_AO_UART3_TX_0_E_LPBK_LSB                 MK_SHIFT_CONST(7)
+#define PADCTL_AO_UART3_TX_0_E_LPBK_WOFFSET                     0x0
+#define PADCTL_AO_UART3_TX_0_E_LPBK_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_E_LPBK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_E_LPBK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_E_LPBK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_E_LPBK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_E_LPBK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_E_LPBK_INIT_ENUM                   DISABLE
+#define PADCTL_AO_UART3_TX_0_E_LPBK_DISABLE                     MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_TX_0_E_LPBK_ENABLE                      MK_ENUM_CONST(1)
+
+#define PADCTL_AO_UART3_TX_0_E_LPDR_SHIFT                       MK_SHIFT_CONST(8)
+#define PADCTL_AO_UART3_TX_0_E_LPDR_FIELD                       MK_FIELD_CONST(0x1, PADCTL_AO_UART3_TX_0_E_LPDR_SHIFT)
+#define PADCTL_AO_UART3_TX_0_E_LPDR_RANGE                       8:8
+#define PADCTL_AO_UART3_TX_0_E_LPDR_MSB                 MK_SHIFT_CONST(8)
+#define PADCTL_AO_UART3_TX_0_E_LPDR_LSB                 MK_SHIFT_CONST(8)
+#define PADCTL_AO_UART3_TX_0_E_LPDR_WOFFSET                     0x0
+#define PADCTL_AO_UART3_TX_0_E_LPDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_E_LPDR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_E_LPDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_E_LPDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_E_LPDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_E_LPDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_E_LPDR_INIT_ENUM                   DISABLE
+#define PADCTL_AO_UART3_TX_0_E_LPDR_DISABLE                     MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_TX_0_E_LPDR_ENABLE                      MK_ENUM_CONST(1)
+
+#define PADCTL_AO_UART3_TX_0_E_IO_HV_SHIFT                      MK_SHIFT_CONST(5)
+#define PADCTL_AO_UART3_TX_0_E_IO_HV_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_UART3_TX_0_E_IO_HV_SHIFT)
+#define PADCTL_AO_UART3_TX_0_E_IO_HV_RANGE                      5:5
+#define PADCTL_AO_UART3_TX_0_E_IO_HV_MSB                        MK_SHIFT_CONST(5)
+#define PADCTL_AO_UART3_TX_0_E_IO_HV_LSB                        MK_SHIFT_CONST(5)
+#define PADCTL_AO_UART3_TX_0_E_IO_HV_WOFFSET                    0x0
+#define PADCTL_AO_UART3_TX_0_E_IO_HV_DEFAULT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_E_IO_HV_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_E_IO_HV_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_E_IO_HV_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_E_IO_HV_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_E_IO_HV_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_E_IO_HV_INIT_ENUM                  ENABLE
+#define PADCTL_AO_UART3_TX_0_E_IO_HV_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_TX_0_E_IO_HV_ENABLE                     MK_ENUM_CONST(1)
+
+#define PADCTL_AO_UART3_TX_0_E_SCHMT_SHIFT                      MK_SHIFT_CONST(12)
+#define PADCTL_AO_UART3_TX_0_E_SCHMT_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_UART3_TX_0_E_SCHMT_SHIFT)
+#define PADCTL_AO_UART3_TX_0_E_SCHMT_RANGE                      12:12
+#define PADCTL_AO_UART3_TX_0_E_SCHMT_MSB                        MK_SHIFT_CONST(12)
+#define PADCTL_AO_UART3_TX_0_E_SCHMT_LSB                        MK_SHIFT_CONST(12)
+#define PADCTL_AO_UART3_TX_0_E_SCHMT_WOFFSET                    0x0
+#define PADCTL_AO_UART3_TX_0_E_SCHMT_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_E_SCHMT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_E_SCHMT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_E_SCHMT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_UART3_TX_0_E_SCHMT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_E_SCHMT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_UART3_TX_0_E_SCHMT_INIT_ENUM                  DISABLE
+#define PADCTL_AO_UART3_TX_0_E_SCHMT_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_UART3_TX_0_E_SCHMT_ENABLE                     MK_ENUM_CONST(1)
+
+
+// Register PADCTL_AO_CFG2TMC_UART3_TX_0
+#define PADCTL_AO_CFG2TMC_UART3_TX_0                    MK_ADDR_CONST(0x14)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_SECURE                     0x0
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_DUAL                       0x0
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_SCR                        SCR_UART3_TX_0
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_SCRREG                     PADCTL_AO_SCR_SCR_UART3_TX_0
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_WORD_COUNT                         0x1
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_RESET_MASK                         MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_READ_MASK                  MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_WRITE_MASK                         MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_SHIFT                        MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_FIELD                        MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_SHIFT)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_RANGE                        16:12
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_MSB                  MK_SHIFT_CONST(16)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_LSB                  MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_WOFFSET                      0x0
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_SHIFT                        MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_FIELD                        MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_SHIFT)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_RANGE                        24:20
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_MSB                  MK_SHIFT_CONST(24)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_LSB                  MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_WOFFSET                      0x0
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_UART3_TX_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register PADCTL_AO_GEN8_I2C_SDA_0
+#define PADCTL_AO_GEN8_I2C_SDA_0                        MK_ADDR_CONST(0x18)
+#define PADCTL_AO_GEN8_I2C_SDA_0_SECURE                         0x0
+#define PADCTL_AO_GEN8_I2C_SDA_0_DUAL                   0x0
+#define PADCTL_AO_GEN8_I2C_SDA_0_SCR                    SCR_GEN8_I2C_SDA_0
+#define PADCTL_AO_GEN8_I2C_SDA_0_SCRREG                         PADCTL_AO_SCR_SCR_GEN8_I2C_SDA_0
+#define PADCTL_AO_GEN8_I2C_SDA_0_WORD_COUNT                     0x1
+#define PADCTL_AO_GEN8_I2C_SDA_0_RESET_VAL                      MK_MASK_CONST(0x570)
+#define PADCTL_AO_GEN8_I2C_SDA_0_RESET_MASK                     MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_GEN8_I2C_SDA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_READ_MASK                      MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_GEN8_I2C_SDA_0_WRITE_MASK                     MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PM_SHIFT                       MK_SHIFT_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PM_FIELD                       MK_FIELD_CONST(0x3, PADCTL_AO_GEN8_I2C_SDA_0_PM_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PM_RANGE                       1:0
+#define PADCTL_AO_GEN8_I2C_SDA_0_PM_MSB                 MK_SHIFT_CONST(1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PM_LSB                 MK_SHIFT_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PM_WOFFSET                     0x0
+#define PADCTL_AO_GEN8_I2C_SDA_0_PM_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PM_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PM_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PM_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PM_INIT_ENUM                   I2C8
+#define PADCTL_AO_GEN8_I2C_SDA_0_PM_I2C8                        MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PM_RSVD1                       MK_ENUM_CONST(1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PM_RSVD2                       MK_ENUM_CONST(2)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PM_RSVD3                       MK_ENUM_CONST(3)
+
+#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_SHIFT                      MK_SHIFT_CONST(10)
+#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_RANGE                      10:10
+#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_MSB                        MK_SHIFT_CONST(10)
+#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_LSB                        MK_SHIFT_CONST(10)
+#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_WOFFSET                    0x0
+#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_DEFAULT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
+#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_GPIO                       MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_GPIO_SF_SEL_SFIO                       MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_SHIFT                 MK_SHIFT_CONST(4)
+#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_FIELD                 MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_RANGE                 4:4
+#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_MSB                   MK_SHIFT_CONST(4)
+#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_LSB                   MK_SHIFT_CONST(4)
+#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_WOFFSET                       0x0
+#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_DEFAULT                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_INIT_ENUM                     TRISTATE
+#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_PASSTHROUGH                   MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_TRISTATE_TRISTATE                      MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_SHIFT                     MK_SHIFT_CONST(2)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_FIELD                     MK_FIELD_CONST(0x3, PADCTL_AO_GEN8_I2C_SDA_0_PUPD_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_RANGE                     3:2
+#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_MSB                       MK_SHIFT_CONST(3)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_LSB                       MK_SHIFT_CONST(2)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_WOFFSET                   0x0
+#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_INIT_ENUM                 NONE
+#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_NONE                      MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_PULL_DOWN                 MK_ENUM_CONST(1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_PULL_UP                   MK_ENUM_CONST(2)
+#define PADCTL_AO_GEN8_I2C_SDA_0_PUPD_RSVD                      MK_ENUM_CONST(3)
+
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_SHIFT                  MK_SHIFT_CONST(6)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_RANGE                  6:6
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_MSB                    MK_SHIFT_CONST(6)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_LSB                    MK_SHIFT_CONST(6)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_WOFFSET                        0x0
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_DEFAULT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_INIT_ENUM                      ENABLE
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_DISABLE                        MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_INPUT_ENABLE                 MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_SHIFT                   MK_SHIFT_CONST(7)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_FIELD                   MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_RANGE                   7:7
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_MSB                     MK_SHIFT_CONST(7)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_LSB                     MK_SHIFT_CONST(7)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_WOFFSET                 0x0
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_INIT_ENUM                       DISABLE
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_DISABLE                 MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPBK_ENABLE                  MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_SHIFT                   MK_SHIFT_CONST(8)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_FIELD                   MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_RANGE                   8:8
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_MSB                     MK_SHIFT_CONST(8)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_LSB                     MK_SHIFT_CONST(8)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_WOFFSET                 0x0
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_DEFAULT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_INIT_ENUM                       ENABLE
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_DISABLE                 MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_LPDR_ENABLE                  MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_SHIFT                  MK_SHIFT_CONST(5)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_RANGE                  5:5
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_MSB                    MK_SHIFT_CONST(5)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_LSB                    MK_SHIFT_CONST(5)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_WOFFSET                        0x0
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_DEFAULT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_INIT_ENUM                      ENABLE
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_DISABLE                        MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_IO_HV_ENABLE                 MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_SHIFT                  MK_SHIFT_CONST(12)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_RANGE                  12:12
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_MSB                    MK_SHIFT_CONST(12)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_LSB                    MK_SHIFT_CONST(12)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_WOFFSET                        0x0
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_INIT_ENUM                      DISABLE
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_DISABLE                        MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SDA_0_E_SCHMT_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0                        MK_ADDR_CONST(0x1c)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_SECURE                         0x0
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_DUAL                   0x0
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_SCR                    SCR_GEN8_I2C_SDA_0
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_SCRREG                         PADCTL_AO_SCR_SCR_GEN8_I2C_SDA_0
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_WORD_COUNT                     0x1
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_RESET_MASK                     MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_READ_MASK                      MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_WRITE_MASK                     MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_SHIFT                    MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_FIELD                    MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_SHIFT)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_RANGE                    16:12
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_MSB                      MK_SHIFT_CONST(16)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_LSB                      MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_WOFFSET                  0x0
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_SHIFT                    MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_FIELD                    MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_SHIFT)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_RANGE                    24:20
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_MSB                      MK_SHIFT_CONST(24)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_LSB                      MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_WOFFSET                  0x0
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register PADCTL_AO_GEN8_I2C_SCL_0
+#define PADCTL_AO_GEN8_I2C_SCL_0                        MK_ADDR_CONST(0x20)
+#define PADCTL_AO_GEN8_I2C_SCL_0_SECURE                         0x0
+#define PADCTL_AO_GEN8_I2C_SCL_0_DUAL                   0x0
+#define PADCTL_AO_GEN8_I2C_SCL_0_SCR                    SCR_GEN8_I2C_SCL_0
+#define PADCTL_AO_GEN8_I2C_SCL_0_SCRREG                         PADCTL_AO_SCR_SCR_GEN8_I2C_SCL_0
+#define PADCTL_AO_GEN8_I2C_SCL_0_WORD_COUNT                     0x1
+#define PADCTL_AO_GEN8_I2C_SCL_0_RESET_VAL                      MK_MASK_CONST(0x1570)
+#define PADCTL_AO_GEN8_I2C_SCL_0_RESET_MASK                     MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_GEN8_I2C_SCL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_READ_MASK                      MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_GEN8_I2C_SCL_0_WRITE_MASK                     MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PM_SHIFT                       MK_SHIFT_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PM_FIELD                       MK_FIELD_CONST(0x3, PADCTL_AO_GEN8_I2C_SCL_0_PM_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PM_RANGE                       1:0
+#define PADCTL_AO_GEN8_I2C_SCL_0_PM_MSB                 MK_SHIFT_CONST(1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PM_LSB                 MK_SHIFT_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PM_WOFFSET                     0x0
+#define PADCTL_AO_GEN8_I2C_SCL_0_PM_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PM_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PM_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PM_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PM_INIT_ENUM                   I2C8
+#define PADCTL_AO_GEN8_I2C_SCL_0_PM_I2C8                        MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PM_RSVD1                       MK_ENUM_CONST(1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PM_RSVD2                       MK_ENUM_CONST(2)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PM_RSVD3                       MK_ENUM_CONST(3)
+
+#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_SHIFT                      MK_SHIFT_CONST(10)
+#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_RANGE                      10:10
+#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_MSB                        MK_SHIFT_CONST(10)
+#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_LSB                        MK_SHIFT_CONST(10)
+#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_WOFFSET                    0x0
+#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_DEFAULT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
+#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_GPIO                       MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_GPIO_SF_SEL_SFIO                       MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_SHIFT                 MK_SHIFT_CONST(4)
+#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_FIELD                 MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_RANGE                 4:4
+#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_MSB                   MK_SHIFT_CONST(4)
+#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_LSB                   MK_SHIFT_CONST(4)
+#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_WOFFSET                       0x0
+#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_DEFAULT                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_INIT_ENUM                     TRISTATE
+#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_PASSTHROUGH                   MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_TRISTATE_TRISTATE                      MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_SHIFT                     MK_SHIFT_CONST(2)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_FIELD                     MK_FIELD_CONST(0x3, PADCTL_AO_GEN8_I2C_SCL_0_PUPD_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_RANGE                     3:2
+#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_MSB                       MK_SHIFT_CONST(3)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_LSB                       MK_SHIFT_CONST(2)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_WOFFSET                   0x0
+#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_INIT_ENUM                 NONE
+#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_NONE                      MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_PULL_DOWN                 MK_ENUM_CONST(1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_PULL_UP                   MK_ENUM_CONST(2)
+#define PADCTL_AO_GEN8_I2C_SCL_0_PUPD_RSVD                      MK_ENUM_CONST(3)
+
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_SHIFT                  MK_SHIFT_CONST(6)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_RANGE                  6:6
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_MSB                    MK_SHIFT_CONST(6)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_LSB                    MK_SHIFT_CONST(6)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_WOFFSET                        0x0
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_DEFAULT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_INIT_ENUM                      ENABLE
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_DISABLE                        MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_INPUT_ENABLE                 MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_SHIFT                   MK_SHIFT_CONST(7)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_FIELD                   MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_RANGE                   7:7
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_MSB                     MK_SHIFT_CONST(7)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_LSB                     MK_SHIFT_CONST(7)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_WOFFSET                 0x0
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_INIT_ENUM                       DISABLE
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_DISABLE                 MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPBK_ENABLE                  MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_SHIFT                   MK_SHIFT_CONST(8)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_FIELD                   MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_RANGE                   8:8
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_MSB                     MK_SHIFT_CONST(8)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_LSB                     MK_SHIFT_CONST(8)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_WOFFSET                 0x0
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_DEFAULT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_INIT_ENUM                       ENABLE
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_DISABLE                 MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_LPDR_ENABLE                  MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_SHIFT                  MK_SHIFT_CONST(5)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_RANGE                  5:5
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_MSB                    MK_SHIFT_CONST(5)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_LSB                    MK_SHIFT_CONST(5)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_WOFFSET                        0x0
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_DEFAULT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_INIT_ENUM                      ENABLE
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_DISABLE                        MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_IO_HV_ENABLE                 MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_SHIFT                  MK_SHIFT_CONST(12)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_SHIFT)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_RANGE                  12:12
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_MSB                    MK_SHIFT_CONST(12)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_LSB                    MK_SHIFT_CONST(12)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_WOFFSET                        0x0
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_DEFAULT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_INIT_ENUM                      ENABLE
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_DISABLE                        MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN8_I2C_SCL_0_E_SCHMT_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0                        MK_ADDR_CONST(0x24)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_SECURE                         0x0
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_DUAL                   0x0
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_SCR                    SCR_GEN8_I2C_SCL_0
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_SCRREG                         PADCTL_AO_SCR_SCR_GEN8_I2C_SCL_0
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_WORD_COUNT                     0x1
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_RESET_MASK                     MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_READ_MASK                      MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_WRITE_MASK                     MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_SHIFT                    MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_FIELD                    MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_SHIFT)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_RANGE                    16:12
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_MSB                      MK_SHIFT_CONST(16)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_LSB                      MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_WOFFSET                  0x0
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_SHIFT                    MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_FIELD                    MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_SHIFT)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_RANGE                    24:20
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_MSB                      MK_SHIFT_CONST(24)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_LSB                      MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_WOFFSET                  0x0
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register PADCTL_AO_SPI2_MOSI_0
+#define PADCTL_AO_SPI2_MOSI_0                   MK_ADDR_CONST(0x28)
+#define PADCTL_AO_SPI2_MOSI_0_SECURE                    0x0
+#define PADCTL_AO_SPI2_MOSI_0_DUAL                      0x0
+#define PADCTL_AO_SPI2_MOSI_0_SCR                       SCR_SPI2_MOSI_0
+#define PADCTL_AO_SPI2_MOSI_0_SCRREG                    PADCTL_AO_SCR_SCR_SPI2_MOSI_0
+#define PADCTL_AO_SPI2_MOSI_0_WORD_COUNT                        0x1
+#define PADCTL_AO_SPI2_MOSI_0_RESET_VAL                         MK_MASK_CONST(0x474)
+#define PADCTL_AO_SPI2_MOSI_0_RESET_MASK                        MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_SPI2_MOSI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_READ_MASK                         MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_SPI2_MOSI_0_WRITE_MASK                        MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_SPI2_MOSI_0_PM_SHIFT                  MK_SHIFT_CONST(0)
+#define PADCTL_AO_SPI2_MOSI_0_PM_FIELD                  MK_FIELD_CONST(0x3, PADCTL_AO_SPI2_MOSI_0_PM_SHIFT)
+#define PADCTL_AO_SPI2_MOSI_0_PM_RANGE                  1:0
+#define PADCTL_AO_SPI2_MOSI_0_PM_MSB                    MK_SHIFT_CONST(1)
+#define PADCTL_AO_SPI2_MOSI_0_PM_LSB                    MK_SHIFT_CONST(0)
+#define PADCTL_AO_SPI2_MOSI_0_PM_WOFFSET                        0x0
+#define PADCTL_AO_SPI2_MOSI_0_PM_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_PM_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define PADCTL_AO_SPI2_MOSI_0_PM_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_PM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_PM_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_PM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_PM_INIT_ENUM                      SPI2
+#define PADCTL_AO_SPI2_MOSI_0_PM_SPI2                   MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MOSI_0_PM_RSVD1                  MK_ENUM_CONST(1)
+#define PADCTL_AO_SPI2_MOSI_0_PM_RSVD2                  MK_ENUM_CONST(2)
+#define PADCTL_AO_SPI2_MOSI_0_PM_RSVD3                  MK_ENUM_CONST(3)
+
+#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_SHIFT                 MK_SHIFT_CONST(10)
+#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_FIELD                 MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_SHIFT)
+#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_RANGE                 10:10
+#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_MSB                   MK_SHIFT_CONST(10)
+#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_LSB                   MK_SHIFT_CONST(10)
+#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_WOFFSET                       0x0
+#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_DEFAULT                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_INIT_ENUM                     SFIO
+#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_GPIO                  MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MOSI_0_GPIO_SF_SEL_SFIO                  MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_SHIFT                    MK_SHIFT_CONST(4)
+#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_FIELD                    MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MOSI_0_TRISTATE_SHIFT)
+#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_RANGE                    4:4
+#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_MSB                      MK_SHIFT_CONST(4)
+#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_LSB                      MK_SHIFT_CONST(4)
+#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_WOFFSET                  0x0
+#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_DEFAULT                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_INIT_ENUM                        TRISTATE
+#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_PASSTHROUGH                      MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MOSI_0_TRISTATE_TRISTATE                 MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_MOSI_0_PUPD_SHIFT                        MK_SHIFT_CONST(2)
+#define PADCTL_AO_SPI2_MOSI_0_PUPD_FIELD                        MK_FIELD_CONST(0x3, PADCTL_AO_SPI2_MOSI_0_PUPD_SHIFT)
+#define PADCTL_AO_SPI2_MOSI_0_PUPD_RANGE                        3:2
+#define PADCTL_AO_SPI2_MOSI_0_PUPD_MSB                  MK_SHIFT_CONST(3)
+#define PADCTL_AO_SPI2_MOSI_0_PUPD_LSB                  MK_SHIFT_CONST(2)
+#define PADCTL_AO_SPI2_MOSI_0_PUPD_WOFFSET                      0x0
+#define PADCTL_AO_SPI2_MOSI_0_PUPD_DEFAULT                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_PUPD_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define PADCTL_AO_SPI2_MOSI_0_PUPD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_PUPD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_PUPD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_PUPD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_PUPD_INIT_ENUM                    PULL_DOWN
+#define PADCTL_AO_SPI2_MOSI_0_PUPD_NONE                 MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MOSI_0_PUPD_PULL_DOWN                    MK_ENUM_CONST(1)
+#define PADCTL_AO_SPI2_MOSI_0_PUPD_PULL_UP                      MK_ENUM_CONST(2)
+#define PADCTL_AO_SPI2_MOSI_0_PUPD_RSVD                 MK_ENUM_CONST(3)
+
+#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_SHIFT                     MK_SHIFT_CONST(6)
+#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MOSI_0_E_INPUT_SHIFT)
+#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_RANGE                     6:6
+#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_MSB                       MK_SHIFT_CONST(6)
+#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_LSB                       MK_SHIFT_CONST(6)
+#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_WOFFSET                   0x0
+#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_DEFAULT                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_INIT_ENUM                 ENABLE
+#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_DISABLE                   MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MOSI_0_E_INPUT_ENABLE                    MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_SHIFT                      MK_SHIFT_CONST(7)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MOSI_0_E_LPBK_SHIFT)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_RANGE                      7:7
+#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_MSB                        MK_SHIFT_CONST(7)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_LSB                        MK_SHIFT_CONST(7)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_WOFFSET                    0x0
+#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_INIT_ENUM                  DISABLE
+#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPBK_ENABLE                     MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_SHIFT                      MK_SHIFT_CONST(8)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MOSI_0_E_LPDR_SHIFT)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_RANGE                      8:8
+#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_MSB                        MK_SHIFT_CONST(8)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_LSB                        MK_SHIFT_CONST(8)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_WOFFSET                    0x0
+#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_INIT_ENUM                  DISABLE
+#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MOSI_0_E_LPDR_ENABLE                     MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_SHIFT                     MK_SHIFT_CONST(5)
+#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MOSI_0_E_IO_HV_SHIFT)
+#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_RANGE                     5:5
+#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_MSB                       MK_SHIFT_CONST(5)
+#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_LSB                       MK_SHIFT_CONST(5)
+#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_WOFFSET                   0x0
+#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_DEFAULT                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_INIT_ENUM                 ENABLE
+#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_DISABLE                   MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MOSI_0_E_IO_HV_ENABLE                    MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_SHIFT                     MK_SHIFT_CONST(12)
+#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MOSI_0_E_SCHMT_SHIFT)
+#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_RANGE                     12:12
+#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_MSB                       MK_SHIFT_CONST(12)
+#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_LSB                       MK_SHIFT_CONST(12)
+#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_WOFFSET                   0x0
+#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_INIT_ENUM                 DISABLE
+#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_DISABLE                   MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MOSI_0_E_SCHMT_ENABLE                    MK_ENUM_CONST(1)
+
+
+// Register PADCTL_AO_CFG2TMC_SPI2_MOSI_0
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0                   MK_ADDR_CONST(0x2c)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_SECURE                    0x0
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_DUAL                      0x0
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_SCR                       SCR_SPI2_MOSI_0
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_SCRREG                    PADCTL_AO_SCR_SCR_SPI2_MOSI_0
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_WORD_COUNT                        0x1
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_RESET_MASK                        MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_READ_MASK                         MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_WRITE_MASK                        MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_SHIFT                       MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_FIELD                       MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_SHIFT)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_RANGE                       16:12
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_MSB                 MK_SHIFT_CONST(16)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_LSB                 MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_WOFFSET                     0x0
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_SHIFT                       MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_FIELD                       MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_SHIFT)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_RANGE                       24:20
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_MSB                 MK_SHIFT_CONST(24)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_LSB                 MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_WOFFSET                     0x0
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_SPI2_MOSI_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register PADCTL_AO_GEN2_I2C_SCL_0
+#define PADCTL_AO_GEN2_I2C_SCL_0                        MK_ADDR_CONST(0x30)
+#define PADCTL_AO_GEN2_I2C_SCL_0_SECURE                         0x0
+#define PADCTL_AO_GEN2_I2C_SCL_0_DUAL                   0x0
+#define PADCTL_AO_GEN2_I2C_SCL_0_SCR                    SCR_GEN2_I2C_SCL_0
+#define PADCTL_AO_GEN2_I2C_SCL_0_SCRREG                         PADCTL_AO_SCR_SCR_GEN2_I2C_SCL_0
+#define PADCTL_AO_GEN2_I2C_SCL_0_WORD_COUNT                     0x1
+#define PADCTL_AO_GEN2_I2C_SCL_0_RESET_VAL                      MK_MASK_CONST(0x1570)
+#define PADCTL_AO_GEN2_I2C_SCL_0_RESET_MASK                     MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_GEN2_I2C_SCL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_READ_MASK                      MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_GEN2_I2C_SCL_0_WRITE_MASK                     MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PM_SHIFT                       MK_SHIFT_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PM_FIELD                       MK_FIELD_CONST(0x3, PADCTL_AO_GEN2_I2C_SCL_0_PM_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PM_RANGE                       1:0
+#define PADCTL_AO_GEN2_I2C_SCL_0_PM_MSB                 MK_SHIFT_CONST(1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PM_LSB                 MK_SHIFT_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PM_WOFFSET                     0x0
+#define PADCTL_AO_GEN2_I2C_SCL_0_PM_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PM_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PM_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PM_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PM_INIT_ENUM                   I2C2
+#define PADCTL_AO_GEN2_I2C_SCL_0_PM_I2C2                        MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PM_RSVD1                       MK_ENUM_CONST(1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PM_RSVD2                       MK_ENUM_CONST(2)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PM_RSVD3                       MK_ENUM_CONST(3)
+
+#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_SHIFT                      MK_SHIFT_CONST(10)
+#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_RANGE                      10:10
+#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_MSB                        MK_SHIFT_CONST(10)
+#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_LSB                        MK_SHIFT_CONST(10)
+#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_WOFFSET                    0x0
+#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_DEFAULT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
+#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_GPIO                       MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_GPIO_SF_SEL_SFIO                       MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_SHIFT                 MK_SHIFT_CONST(4)
+#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_FIELD                 MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_RANGE                 4:4
+#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_MSB                   MK_SHIFT_CONST(4)
+#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_LSB                   MK_SHIFT_CONST(4)
+#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_WOFFSET                       0x0
+#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_DEFAULT                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_INIT_ENUM                     TRISTATE
+#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_PASSTHROUGH                   MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_TRISTATE_TRISTATE                      MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_SHIFT                     MK_SHIFT_CONST(2)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_FIELD                     MK_FIELD_CONST(0x3, PADCTL_AO_GEN2_I2C_SCL_0_PUPD_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_RANGE                     3:2
+#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_MSB                       MK_SHIFT_CONST(3)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_LSB                       MK_SHIFT_CONST(2)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_WOFFSET                   0x0
+#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_INIT_ENUM                 NONE
+#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_NONE                      MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_PULL_DOWN                 MK_ENUM_CONST(1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_PULL_UP                   MK_ENUM_CONST(2)
+#define PADCTL_AO_GEN2_I2C_SCL_0_PUPD_RSVD                      MK_ENUM_CONST(3)
+
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_SHIFT                  MK_SHIFT_CONST(6)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_RANGE                  6:6
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_MSB                    MK_SHIFT_CONST(6)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_LSB                    MK_SHIFT_CONST(6)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_WOFFSET                        0x0
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_DEFAULT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_INIT_ENUM                      ENABLE
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_DISABLE                        MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_INPUT_ENABLE                 MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_SHIFT                   MK_SHIFT_CONST(7)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_FIELD                   MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_RANGE                   7:7
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_MSB                     MK_SHIFT_CONST(7)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_LSB                     MK_SHIFT_CONST(7)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_WOFFSET                 0x0
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_INIT_ENUM                       DISABLE
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_DISABLE                 MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPBK_ENABLE                  MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_SHIFT                   MK_SHIFT_CONST(8)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_FIELD                   MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_RANGE                   8:8
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_MSB                     MK_SHIFT_CONST(8)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_LSB                     MK_SHIFT_CONST(8)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_WOFFSET                 0x0
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_DEFAULT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_INIT_ENUM                       ENABLE
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_DISABLE                 MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_LPDR_ENABLE                  MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_SHIFT                  MK_SHIFT_CONST(5)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_RANGE                  5:5
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_MSB                    MK_SHIFT_CONST(5)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_LSB                    MK_SHIFT_CONST(5)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_WOFFSET                        0x0
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_DEFAULT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_INIT_ENUM                      ENABLE
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_DISABLE                        MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_IO_HV_ENABLE                 MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_SHIFT                  MK_SHIFT_CONST(12)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_RANGE                  12:12
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_MSB                    MK_SHIFT_CONST(12)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_LSB                    MK_SHIFT_CONST(12)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_WOFFSET                        0x0
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_DEFAULT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_INIT_ENUM                      ENABLE
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_DISABLE                        MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SCL_0_E_SCHMT_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0                        MK_ADDR_CONST(0x34)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_SECURE                         0x0
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_DUAL                   0x0
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_SCR                    SCR_GEN2_I2C_SCL_0
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_SCRREG                         PADCTL_AO_SCR_SCR_GEN2_I2C_SCL_0
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_WORD_COUNT                     0x1
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_RESET_MASK                     MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_READ_MASK                      MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_WRITE_MASK                     MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_SHIFT                    MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_FIELD                    MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_SHIFT)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_RANGE                    16:12
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_MSB                      MK_SHIFT_CONST(16)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_LSB                      MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_WOFFSET                  0x0
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_SHIFT                    MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_FIELD                    MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_SHIFT)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_RANGE                    24:20
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_MSB                      MK_SHIFT_CONST(24)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_LSB                      MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_WOFFSET                  0x0
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register PADCTL_AO_SPI2_CS0_0
+#define PADCTL_AO_SPI2_CS0_0                    MK_ADDR_CONST(0x38)
+#define PADCTL_AO_SPI2_CS0_0_SECURE                     0x0
+#define PADCTL_AO_SPI2_CS0_0_DUAL                       0x0
+#define PADCTL_AO_SPI2_CS0_0_SCR                        SCR_SPI2_CS0_0
+#define PADCTL_AO_SPI2_CS0_0_SCRREG                     PADCTL_AO_SCR_SCR_SPI2_CS0_0
+#define PADCTL_AO_SPI2_CS0_0_WORD_COUNT                         0x1
+#define PADCTL_AO_SPI2_CS0_0_RESET_VAL                  MK_MASK_CONST(0x470)
+#define PADCTL_AO_SPI2_CS0_0_RESET_MASK                         MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_SPI2_CS0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_READ_MASK                  MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_SPI2_CS0_0_WRITE_MASK                         MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_SPI2_CS0_0_PM_SHIFT                   MK_SHIFT_CONST(0)
+#define PADCTL_AO_SPI2_CS0_0_PM_FIELD                   MK_FIELD_CONST(0x3, PADCTL_AO_SPI2_CS0_0_PM_SHIFT)
+#define PADCTL_AO_SPI2_CS0_0_PM_RANGE                   1:0
+#define PADCTL_AO_SPI2_CS0_0_PM_MSB                     MK_SHIFT_CONST(1)
+#define PADCTL_AO_SPI2_CS0_0_PM_LSB                     MK_SHIFT_CONST(0)
+#define PADCTL_AO_SPI2_CS0_0_PM_WOFFSET                 0x0
+#define PADCTL_AO_SPI2_CS0_0_PM_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_PM_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define PADCTL_AO_SPI2_CS0_0_PM_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_PM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_PM_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_PM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_PM_INIT_ENUM                       SPI2
+#define PADCTL_AO_SPI2_CS0_0_PM_SPI2                    MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_CS0_0_PM_RSVD1                   MK_ENUM_CONST(1)
+#define PADCTL_AO_SPI2_CS0_0_PM_RSVD2                   MK_ENUM_CONST(2)
+#define PADCTL_AO_SPI2_CS0_0_PM_RSVD3                   MK_ENUM_CONST(3)
+
+#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_SHIFT                  MK_SHIFT_CONST(10)
+#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_SHIFT)
+#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_RANGE                  10:10
+#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_MSB                    MK_SHIFT_CONST(10)
+#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_LSB                    MK_SHIFT_CONST(10)
+#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_WOFFSET                        0x0
+#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_DEFAULT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_INIT_ENUM                      SFIO
+#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_GPIO                   MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_CS0_0_GPIO_SF_SEL_SFIO                   MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_CS0_0_TRISTATE_SHIFT                     MK_SHIFT_CONST(4)
+#define PADCTL_AO_SPI2_CS0_0_TRISTATE_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_CS0_0_TRISTATE_SHIFT)
+#define PADCTL_AO_SPI2_CS0_0_TRISTATE_RANGE                     4:4
+#define PADCTL_AO_SPI2_CS0_0_TRISTATE_MSB                       MK_SHIFT_CONST(4)
+#define PADCTL_AO_SPI2_CS0_0_TRISTATE_LSB                       MK_SHIFT_CONST(4)
+#define PADCTL_AO_SPI2_CS0_0_TRISTATE_WOFFSET                   0x0
+#define PADCTL_AO_SPI2_CS0_0_TRISTATE_DEFAULT                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_TRISTATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_TRISTATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_TRISTATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_TRISTATE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_TRISTATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_TRISTATE_INIT_ENUM                 TRISTATE
+#define PADCTL_AO_SPI2_CS0_0_TRISTATE_PASSTHROUGH                       MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_CS0_0_TRISTATE_TRISTATE                  MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_CS0_0_PUPD_SHIFT                 MK_SHIFT_CONST(2)
+#define PADCTL_AO_SPI2_CS0_0_PUPD_FIELD                 MK_FIELD_CONST(0x3, PADCTL_AO_SPI2_CS0_0_PUPD_SHIFT)
+#define PADCTL_AO_SPI2_CS0_0_PUPD_RANGE                 3:2
+#define PADCTL_AO_SPI2_CS0_0_PUPD_MSB                   MK_SHIFT_CONST(3)
+#define PADCTL_AO_SPI2_CS0_0_PUPD_LSB                   MK_SHIFT_CONST(2)
+#define PADCTL_AO_SPI2_CS0_0_PUPD_WOFFSET                       0x0
+#define PADCTL_AO_SPI2_CS0_0_PUPD_DEFAULT                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_PUPD_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PADCTL_AO_SPI2_CS0_0_PUPD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_PUPD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_PUPD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_PUPD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_PUPD_INIT_ENUM                     NONE
+#define PADCTL_AO_SPI2_CS0_0_PUPD_NONE                  MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_CS0_0_PUPD_PULL_DOWN                     MK_ENUM_CONST(1)
+#define PADCTL_AO_SPI2_CS0_0_PUPD_PULL_UP                       MK_ENUM_CONST(2)
+#define PADCTL_AO_SPI2_CS0_0_PUPD_RSVD                  MK_ENUM_CONST(3)
+
+#define PADCTL_AO_SPI2_CS0_0_E_INPUT_SHIFT                      MK_SHIFT_CONST(6)
+#define PADCTL_AO_SPI2_CS0_0_E_INPUT_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_CS0_0_E_INPUT_SHIFT)
+#define PADCTL_AO_SPI2_CS0_0_E_INPUT_RANGE                      6:6
+#define PADCTL_AO_SPI2_CS0_0_E_INPUT_MSB                        MK_SHIFT_CONST(6)
+#define PADCTL_AO_SPI2_CS0_0_E_INPUT_LSB                        MK_SHIFT_CONST(6)
+#define PADCTL_AO_SPI2_CS0_0_E_INPUT_WOFFSET                    0x0
+#define PADCTL_AO_SPI2_CS0_0_E_INPUT_DEFAULT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_E_INPUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_E_INPUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_E_INPUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_E_INPUT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_E_INPUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_E_INPUT_INIT_ENUM                  ENABLE
+#define PADCTL_AO_SPI2_CS0_0_E_INPUT_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_CS0_0_E_INPUT_ENABLE                     MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_CS0_0_E_LPBK_SHIFT                       MK_SHIFT_CONST(7)
+#define PADCTL_AO_SPI2_CS0_0_E_LPBK_FIELD                       MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_CS0_0_E_LPBK_SHIFT)
+#define PADCTL_AO_SPI2_CS0_0_E_LPBK_RANGE                       7:7
+#define PADCTL_AO_SPI2_CS0_0_E_LPBK_MSB                 MK_SHIFT_CONST(7)
+#define PADCTL_AO_SPI2_CS0_0_E_LPBK_LSB                 MK_SHIFT_CONST(7)
+#define PADCTL_AO_SPI2_CS0_0_E_LPBK_WOFFSET                     0x0
+#define PADCTL_AO_SPI2_CS0_0_E_LPBK_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_E_LPBK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_E_LPBK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_E_LPBK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_E_LPBK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_E_LPBK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_E_LPBK_INIT_ENUM                   DISABLE
+#define PADCTL_AO_SPI2_CS0_0_E_LPBK_DISABLE                     MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_CS0_0_E_LPBK_ENABLE                      MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_CS0_0_E_LPDR_SHIFT                       MK_SHIFT_CONST(8)
+#define PADCTL_AO_SPI2_CS0_0_E_LPDR_FIELD                       MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_CS0_0_E_LPDR_SHIFT)
+#define PADCTL_AO_SPI2_CS0_0_E_LPDR_RANGE                       8:8
+#define PADCTL_AO_SPI2_CS0_0_E_LPDR_MSB                 MK_SHIFT_CONST(8)
+#define PADCTL_AO_SPI2_CS0_0_E_LPDR_LSB                 MK_SHIFT_CONST(8)
+#define PADCTL_AO_SPI2_CS0_0_E_LPDR_WOFFSET                     0x0
+#define PADCTL_AO_SPI2_CS0_0_E_LPDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_E_LPDR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_E_LPDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_E_LPDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_E_LPDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_E_LPDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_E_LPDR_INIT_ENUM                   DISABLE
+#define PADCTL_AO_SPI2_CS0_0_E_LPDR_DISABLE                     MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_CS0_0_E_LPDR_ENABLE                      MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_SHIFT                      MK_SHIFT_CONST(5)
+#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_CS0_0_E_IO_HV_SHIFT)
+#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_RANGE                      5:5
+#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_MSB                        MK_SHIFT_CONST(5)
+#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_LSB                        MK_SHIFT_CONST(5)
+#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_WOFFSET                    0x0
+#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_DEFAULT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_INIT_ENUM                  ENABLE
+#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_CS0_0_E_IO_HV_ENABLE                     MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_SHIFT                      MK_SHIFT_CONST(12)
+#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_CS0_0_E_SCHMT_SHIFT)
+#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_RANGE                      12:12
+#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_MSB                        MK_SHIFT_CONST(12)
+#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_LSB                        MK_SHIFT_CONST(12)
+#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_WOFFSET                    0x0
+#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_INIT_ENUM                  DISABLE
+#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_CS0_0_E_SCHMT_ENABLE                     MK_ENUM_CONST(1)
+
+
+// Register PADCTL_AO_CFG2TMC_SPI2_CS0_0
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0                    MK_ADDR_CONST(0x3c)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_SECURE                     0x0
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_DUAL                       0x0
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_SCR                        SCR_SPI2_CS0_0
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_SCRREG                     PADCTL_AO_SCR_SCR_SPI2_CS0_0
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_WORD_COUNT                         0x1
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_RESET_MASK                         MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_READ_MASK                  MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_WRITE_MASK                         MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_SHIFT                        MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_FIELD                        MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_SHIFT)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_RANGE                        16:12
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_MSB                  MK_SHIFT_CONST(16)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_LSB                  MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_WOFFSET                      0x0
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_SHIFT                        MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_FIELD                        MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_SHIFT)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_RANGE                        24:20
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_MSB                  MK_SHIFT_CONST(24)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_LSB                  MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_WOFFSET                      0x0
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_SPI2_CS0_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register PADCTL_AO_GEN2_I2C_SDA_0
+#define PADCTL_AO_GEN2_I2C_SDA_0                        MK_ADDR_CONST(0x40)
+#define PADCTL_AO_GEN2_I2C_SDA_0_SECURE                         0x0
+#define PADCTL_AO_GEN2_I2C_SDA_0_DUAL                   0x0
+#define PADCTL_AO_GEN2_I2C_SDA_0_SCR                    SCR_GEN2_I2C_SDA_0
+#define PADCTL_AO_GEN2_I2C_SDA_0_SCRREG                         PADCTL_AO_SCR_SCR_GEN2_I2C_SDA_0
+#define PADCTL_AO_GEN2_I2C_SDA_0_WORD_COUNT                     0x1
+#define PADCTL_AO_GEN2_I2C_SDA_0_RESET_VAL                      MK_MASK_CONST(0x570)
+#define PADCTL_AO_GEN2_I2C_SDA_0_RESET_MASK                     MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_GEN2_I2C_SDA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_READ_MASK                      MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_GEN2_I2C_SDA_0_WRITE_MASK                     MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PM_SHIFT                       MK_SHIFT_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PM_FIELD                       MK_FIELD_CONST(0x3, PADCTL_AO_GEN2_I2C_SDA_0_PM_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PM_RANGE                       1:0
+#define PADCTL_AO_GEN2_I2C_SDA_0_PM_MSB                 MK_SHIFT_CONST(1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PM_LSB                 MK_SHIFT_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PM_WOFFSET                     0x0
+#define PADCTL_AO_GEN2_I2C_SDA_0_PM_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PM_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PM_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PM_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PM_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PM_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PM_INIT_ENUM                   I2C2
+#define PADCTL_AO_GEN2_I2C_SDA_0_PM_I2C2                        MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PM_RSVD1                       MK_ENUM_CONST(1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PM_RSVD2                       MK_ENUM_CONST(2)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PM_RSVD3                       MK_ENUM_CONST(3)
+
+#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_SHIFT                      MK_SHIFT_CONST(10)
+#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_RANGE                      10:10
+#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_MSB                        MK_SHIFT_CONST(10)
+#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_LSB                        MK_SHIFT_CONST(10)
+#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_WOFFSET                    0x0
+#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_DEFAULT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_INIT_ENUM                  SFIO
+#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_GPIO                       MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_GPIO_SF_SEL_SFIO                       MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_SHIFT                 MK_SHIFT_CONST(4)
+#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_FIELD                 MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_RANGE                 4:4
+#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_MSB                   MK_SHIFT_CONST(4)
+#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_LSB                   MK_SHIFT_CONST(4)
+#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_WOFFSET                       0x0
+#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_DEFAULT                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_INIT_ENUM                     TRISTATE
+#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_PASSTHROUGH                   MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_TRISTATE_TRISTATE                      MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_SHIFT                     MK_SHIFT_CONST(2)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_FIELD                     MK_FIELD_CONST(0x3, PADCTL_AO_GEN2_I2C_SDA_0_PUPD_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_RANGE                     3:2
+#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_MSB                       MK_SHIFT_CONST(3)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_LSB                       MK_SHIFT_CONST(2)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_WOFFSET                   0x0
+#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_INIT_ENUM                 NONE
+#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_NONE                      MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_PULL_DOWN                 MK_ENUM_CONST(1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_PULL_UP                   MK_ENUM_CONST(2)
+#define PADCTL_AO_GEN2_I2C_SDA_0_PUPD_RSVD                      MK_ENUM_CONST(3)
+
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_SHIFT                  MK_SHIFT_CONST(6)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_RANGE                  6:6
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_MSB                    MK_SHIFT_CONST(6)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_LSB                    MK_SHIFT_CONST(6)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_WOFFSET                        0x0
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_DEFAULT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_INIT_ENUM                      ENABLE
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_DISABLE                        MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_INPUT_ENABLE                 MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_SHIFT                   MK_SHIFT_CONST(7)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_FIELD                   MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_RANGE                   7:7
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_MSB                     MK_SHIFT_CONST(7)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_LSB                     MK_SHIFT_CONST(7)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_WOFFSET                 0x0
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_INIT_ENUM                       DISABLE
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_DISABLE                 MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPBK_ENABLE                  MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_SHIFT                   MK_SHIFT_CONST(8)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_FIELD                   MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_RANGE                   8:8
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_MSB                     MK_SHIFT_CONST(8)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_LSB                     MK_SHIFT_CONST(8)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_WOFFSET                 0x0
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_DEFAULT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_INIT_ENUM                       ENABLE
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_DISABLE                 MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_LPDR_ENABLE                  MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_SHIFT                  MK_SHIFT_CONST(5)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_RANGE                  5:5
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_MSB                    MK_SHIFT_CONST(5)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_LSB                    MK_SHIFT_CONST(5)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_WOFFSET                        0x0
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_DEFAULT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_INIT_ENUM                      ENABLE
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_DISABLE                        MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_IO_HV_ENABLE                 MK_ENUM_CONST(1)
+
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_SHIFT                  MK_SHIFT_CONST(12)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_SHIFT)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_RANGE                  12:12
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_MSB                    MK_SHIFT_CONST(12)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_LSB                    MK_SHIFT_CONST(12)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_WOFFSET                        0x0
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_INIT_ENUM                      DISABLE
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_DISABLE                        MK_ENUM_CONST(0)
+#define PADCTL_AO_GEN2_I2C_SDA_0_E_SCHMT_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0                        MK_ADDR_CONST(0x44)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_SECURE                         0x0
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_DUAL                   0x0
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_SCR                    SCR_GEN2_I2C_SDA_0
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_SCRREG                         PADCTL_AO_SCR_SCR_GEN2_I2C_SDA_0
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_WORD_COUNT                     0x1
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_RESET_MASK                     MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_READ_MASK                      MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_WRITE_MASK                     MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_SHIFT                    MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_FIELD                    MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_SHIFT)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_RANGE                    16:12
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_MSB                      MK_SHIFT_CONST(16)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_LSB                      MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_WOFFSET                  0x0
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_SHIFT                    MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_FIELD                    MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_SHIFT)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_RANGE                    24:20
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_MSB                      MK_SHIFT_CONST(24)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_LSB                      MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_WOFFSET                  0x0
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register PADCTL_AO_SPI2_SCK_0
+#define PADCTL_AO_SPI2_SCK_0                    MK_ADDR_CONST(0x48)
+#define PADCTL_AO_SPI2_SCK_0_SECURE                     0x0
+#define PADCTL_AO_SPI2_SCK_0_DUAL                       0x0
+#define PADCTL_AO_SPI2_SCK_0_SCR                        SCR_SPI2_SCK_0
+#define PADCTL_AO_SPI2_SCK_0_SCRREG                     PADCTL_AO_SCR_SCR_SPI2_SCK_0
+#define PADCTL_AO_SPI2_SCK_0_WORD_COUNT                         0x1
+#define PADCTL_AO_SPI2_SCK_0_RESET_VAL                  MK_MASK_CONST(0x1474)
+#define PADCTL_AO_SPI2_SCK_0_RESET_MASK                         MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_SPI2_SCK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_READ_MASK                  MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_SPI2_SCK_0_WRITE_MASK                         MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_SPI2_SCK_0_PM_SHIFT                   MK_SHIFT_CONST(0)
+#define PADCTL_AO_SPI2_SCK_0_PM_FIELD                   MK_FIELD_CONST(0x3, PADCTL_AO_SPI2_SCK_0_PM_SHIFT)
+#define PADCTL_AO_SPI2_SCK_0_PM_RANGE                   1:0
+#define PADCTL_AO_SPI2_SCK_0_PM_MSB                     MK_SHIFT_CONST(1)
+#define PADCTL_AO_SPI2_SCK_0_PM_LSB                     MK_SHIFT_CONST(0)
+#define PADCTL_AO_SPI2_SCK_0_PM_WOFFSET                 0x0
+#define PADCTL_AO_SPI2_SCK_0_PM_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_PM_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define PADCTL_AO_SPI2_SCK_0_PM_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_PM_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_PM_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_PM_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_PM_INIT_ENUM                       SPI2
+#define PADCTL_AO_SPI2_SCK_0_PM_SPI2                    MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_SCK_0_PM_RSVD1                   MK_ENUM_CONST(1)
+#define PADCTL_AO_SPI2_SCK_0_PM_RSVD2                   MK_ENUM_CONST(2)
+#define PADCTL_AO_SPI2_SCK_0_PM_RSVD3                   MK_ENUM_CONST(3)
+
+#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_SHIFT                  MK_SHIFT_CONST(10)
+#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_FIELD                  MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_SHIFT)
+#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_RANGE                  10:10
+#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_MSB                    MK_SHIFT_CONST(10)
+#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_LSB                    MK_SHIFT_CONST(10)
+#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_WOFFSET                        0x0
+#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_DEFAULT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_INIT_ENUM                      SFIO
+#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_GPIO                   MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_SCK_0_GPIO_SF_SEL_SFIO                   MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_SCK_0_TRISTATE_SHIFT                     MK_SHIFT_CONST(4)
+#define PADCTL_AO_SPI2_SCK_0_TRISTATE_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_SCK_0_TRISTATE_SHIFT)
+#define PADCTL_AO_SPI2_SCK_0_TRISTATE_RANGE                     4:4
+#define PADCTL_AO_SPI2_SCK_0_TRISTATE_MSB                       MK_SHIFT_CONST(4)
+#define PADCTL_AO_SPI2_SCK_0_TRISTATE_LSB                       MK_SHIFT_CONST(4)
+#define PADCTL_AO_SPI2_SCK_0_TRISTATE_WOFFSET                   0x0
+#define PADCTL_AO_SPI2_SCK_0_TRISTATE_DEFAULT                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_TRISTATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_TRISTATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_TRISTATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_TRISTATE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_TRISTATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_TRISTATE_INIT_ENUM                 TRISTATE
+#define PADCTL_AO_SPI2_SCK_0_TRISTATE_PASSTHROUGH                       MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_SCK_0_TRISTATE_TRISTATE                  MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_SCK_0_PUPD_SHIFT                 MK_SHIFT_CONST(2)
+#define PADCTL_AO_SPI2_SCK_0_PUPD_FIELD                 MK_FIELD_CONST(0x3, PADCTL_AO_SPI2_SCK_0_PUPD_SHIFT)
+#define PADCTL_AO_SPI2_SCK_0_PUPD_RANGE                 3:2
+#define PADCTL_AO_SPI2_SCK_0_PUPD_MSB                   MK_SHIFT_CONST(3)
+#define PADCTL_AO_SPI2_SCK_0_PUPD_LSB                   MK_SHIFT_CONST(2)
+#define PADCTL_AO_SPI2_SCK_0_PUPD_WOFFSET                       0x0
+#define PADCTL_AO_SPI2_SCK_0_PUPD_DEFAULT                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_PUPD_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PADCTL_AO_SPI2_SCK_0_PUPD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_PUPD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_PUPD_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_PUPD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_PUPD_INIT_ENUM                     PULL_DOWN
+#define PADCTL_AO_SPI2_SCK_0_PUPD_NONE                  MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_SCK_0_PUPD_PULL_DOWN                     MK_ENUM_CONST(1)
+#define PADCTL_AO_SPI2_SCK_0_PUPD_PULL_UP                       MK_ENUM_CONST(2)
+#define PADCTL_AO_SPI2_SCK_0_PUPD_RSVD                  MK_ENUM_CONST(3)
+
+#define PADCTL_AO_SPI2_SCK_0_E_INPUT_SHIFT                      MK_SHIFT_CONST(6)
+#define PADCTL_AO_SPI2_SCK_0_E_INPUT_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_SCK_0_E_INPUT_SHIFT)
+#define PADCTL_AO_SPI2_SCK_0_E_INPUT_RANGE                      6:6
+#define PADCTL_AO_SPI2_SCK_0_E_INPUT_MSB                        MK_SHIFT_CONST(6)
+#define PADCTL_AO_SPI2_SCK_0_E_INPUT_LSB                        MK_SHIFT_CONST(6)
+#define PADCTL_AO_SPI2_SCK_0_E_INPUT_WOFFSET                    0x0
+#define PADCTL_AO_SPI2_SCK_0_E_INPUT_DEFAULT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_INPUT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_INPUT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_E_INPUT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_E_INPUT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_INPUT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_INPUT_INIT_ENUM                  ENABLE
+#define PADCTL_AO_SPI2_SCK_0_E_INPUT_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_SCK_0_E_INPUT_ENABLE                     MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_SCK_0_E_LPBK_SHIFT                       MK_SHIFT_CONST(7)
+#define PADCTL_AO_SPI2_SCK_0_E_LPBK_FIELD                       MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_SCK_0_E_LPBK_SHIFT)
+#define PADCTL_AO_SPI2_SCK_0_E_LPBK_RANGE                       7:7
+#define PADCTL_AO_SPI2_SCK_0_E_LPBK_MSB                 MK_SHIFT_CONST(7)
+#define PADCTL_AO_SPI2_SCK_0_E_LPBK_LSB                 MK_SHIFT_CONST(7)
+#define PADCTL_AO_SPI2_SCK_0_E_LPBK_WOFFSET                     0x0
+#define PADCTL_AO_SPI2_SCK_0_E_LPBK_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_E_LPBK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_LPBK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_E_LPBK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_E_LPBK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_LPBK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_LPBK_INIT_ENUM                   DISABLE
+#define PADCTL_AO_SPI2_SCK_0_E_LPBK_DISABLE                     MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_SCK_0_E_LPBK_ENABLE                      MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_SCK_0_E_LPDR_SHIFT                       MK_SHIFT_CONST(8)
+#define PADCTL_AO_SPI2_SCK_0_E_LPDR_FIELD                       MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_SCK_0_E_LPDR_SHIFT)
+#define PADCTL_AO_SPI2_SCK_0_E_LPDR_RANGE                       8:8
+#define PADCTL_AO_SPI2_SCK_0_E_LPDR_MSB                 MK_SHIFT_CONST(8)
+#define PADCTL_AO_SPI2_SCK_0_E_LPDR_LSB                 MK_SHIFT_CONST(8)
+#define PADCTL_AO_SPI2_SCK_0_E_LPDR_WOFFSET                     0x0
+#define PADCTL_AO_SPI2_SCK_0_E_LPDR_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_E_LPDR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_LPDR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_E_LPDR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_E_LPDR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_LPDR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_LPDR_INIT_ENUM                   DISABLE
+#define PADCTL_AO_SPI2_SCK_0_E_LPDR_DISABLE                     MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_SCK_0_E_LPDR_ENABLE                      MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_SHIFT                      MK_SHIFT_CONST(5)
+#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_SCK_0_E_IO_HV_SHIFT)
+#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_RANGE                      5:5
+#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_MSB                        MK_SHIFT_CONST(5)
+#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_LSB                        MK_SHIFT_CONST(5)
+#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_WOFFSET                    0x0
+#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_DEFAULT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_INIT_ENUM                  ENABLE
+#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_SCK_0_E_IO_HV_ENABLE                     MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_SHIFT                      MK_SHIFT_CONST(12)
+#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_SCK_0_E_SCHMT_SHIFT)
+#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_RANGE                      12:12
+#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_MSB                        MK_SHIFT_CONST(12)
+#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_LSB                        MK_SHIFT_CONST(12)
+#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_WOFFSET                    0x0
+#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_DEFAULT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_INIT_ENUM                  ENABLE
+#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_SCK_0_E_SCHMT_ENABLE                     MK_ENUM_CONST(1)
+
+
+// Register PADCTL_AO_CFG2TMC_SPI2_SCK_0
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0                    MK_ADDR_CONST(0x4c)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_SECURE                     0x0
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_DUAL                       0x0
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_SCR                        SCR_SPI2_SCK_0
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_SCRREG                     PADCTL_AO_SCR_SCR_SPI2_SCK_0
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_WORD_COUNT                         0x1
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_RESET_MASK                         MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_READ_MASK                  MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_WRITE_MASK                         MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_SHIFT                        MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_FIELD                        MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_SHIFT)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_RANGE                        16:12
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_MSB                  MK_SHIFT_CONST(16)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_LSB                  MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_WOFFSET                      0x0
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_SHIFT                        MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_FIELD                        MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_SHIFT)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_RANGE                        24:20
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_MSB                  MK_SHIFT_CONST(24)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_LSB                  MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_WOFFSET                      0x0
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_DEFAULT                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_SPI2_SCK_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register PADCTL_AO_SPI2_MISO_0
+#define PADCTL_AO_SPI2_MISO_0                   MK_ADDR_CONST(0x50)
+#define PADCTL_AO_SPI2_MISO_0_SECURE                    0x0
+#define PADCTL_AO_SPI2_MISO_0_DUAL                      0x0
+#define PADCTL_AO_SPI2_MISO_0_SCR                       SCR_SPI2_MISO_0
+#define PADCTL_AO_SPI2_MISO_0_SCRREG                    PADCTL_AO_SCR_SCR_SPI2_MISO_0
+#define PADCTL_AO_SPI2_MISO_0_WORD_COUNT                        0x1
+#define PADCTL_AO_SPI2_MISO_0_RESET_VAL                         MK_MASK_CONST(0x474)
+#define PADCTL_AO_SPI2_MISO_0_RESET_MASK                        MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_SPI2_MISO_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_READ_MASK                         MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_SPI2_MISO_0_WRITE_MASK                        MK_MASK_CONST(0x15ff)
+#define PADCTL_AO_SPI2_MISO_0_PM_SHIFT                  MK_SHIFT_CONST(0)
+#define PADCTL_AO_SPI2_MISO_0_PM_FIELD                  MK_FIELD_CONST(0x3, PADCTL_AO_SPI2_MISO_0_PM_SHIFT)
+#define PADCTL_AO_SPI2_MISO_0_PM_RANGE                  1:0
+#define PADCTL_AO_SPI2_MISO_0_PM_MSB                    MK_SHIFT_CONST(1)
+#define PADCTL_AO_SPI2_MISO_0_PM_LSB                    MK_SHIFT_CONST(0)
+#define PADCTL_AO_SPI2_MISO_0_PM_WOFFSET                        0x0
+#define PADCTL_AO_SPI2_MISO_0_PM_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_PM_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define PADCTL_AO_SPI2_MISO_0_PM_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_PM_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_PM_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_PM_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_PM_INIT_ENUM                      SPI2
+#define PADCTL_AO_SPI2_MISO_0_PM_SPI2                   MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MISO_0_PM_RSVD1                  MK_ENUM_CONST(1)
+#define PADCTL_AO_SPI2_MISO_0_PM_RSVD2                  MK_ENUM_CONST(2)
+#define PADCTL_AO_SPI2_MISO_0_PM_RSVD3                  MK_ENUM_CONST(3)
+
+#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_SHIFT                 MK_SHIFT_CONST(10)
+#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_FIELD                 MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_SHIFT)
+#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_RANGE                 10:10
+#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_MSB                   MK_SHIFT_CONST(10)
+#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_LSB                   MK_SHIFT_CONST(10)
+#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_WOFFSET                       0x0
+#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_DEFAULT                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_INIT_ENUM                     SFIO
+#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_GPIO                  MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MISO_0_GPIO_SF_SEL_SFIO                  MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_MISO_0_TRISTATE_SHIFT                    MK_SHIFT_CONST(4)
+#define PADCTL_AO_SPI2_MISO_0_TRISTATE_FIELD                    MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MISO_0_TRISTATE_SHIFT)
+#define PADCTL_AO_SPI2_MISO_0_TRISTATE_RANGE                    4:4
+#define PADCTL_AO_SPI2_MISO_0_TRISTATE_MSB                      MK_SHIFT_CONST(4)
+#define PADCTL_AO_SPI2_MISO_0_TRISTATE_LSB                      MK_SHIFT_CONST(4)
+#define PADCTL_AO_SPI2_MISO_0_TRISTATE_WOFFSET                  0x0
+#define PADCTL_AO_SPI2_MISO_0_TRISTATE_DEFAULT                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_TRISTATE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_TRISTATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_TRISTATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_TRISTATE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_TRISTATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_TRISTATE_INIT_ENUM                        TRISTATE
+#define PADCTL_AO_SPI2_MISO_0_TRISTATE_PASSTHROUGH                      MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MISO_0_TRISTATE_TRISTATE                 MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_MISO_0_PUPD_SHIFT                        MK_SHIFT_CONST(2)
+#define PADCTL_AO_SPI2_MISO_0_PUPD_FIELD                        MK_FIELD_CONST(0x3, PADCTL_AO_SPI2_MISO_0_PUPD_SHIFT)
+#define PADCTL_AO_SPI2_MISO_0_PUPD_RANGE                        3:2
+#define PADCTL_AO_SPI2_MISO_0_PUPD_MSB                  MK_SHIFT_CONST(3)
+#define PADCTL_AO_SPI2_MISO_0_PUPD_LSB                  MK_SHIFT_CONST(2)
+#define PADCTL_AO_SPI2_MISO_0_PUPD_WOFFSET                      0x0
+#define PADCTL_AO_SPI2_MISO_0_PUPD_DEFAULT                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_PUPD_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define PADCTL_AO_SPI2_MISO_0_PUPD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_PUPD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_PUPD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_PUPD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_PUPD_INIT_ENUM                    PULL_DOWN
+#define PADCTL_AO_SPI2_MISO_0_PUPD_NONE                 MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MISO_0_PUPD_PULL_DOWN                    MK_ENUM_CONST(1)
+#define PADCTL_AO_SPI2_MISO_0_PUPD_PULL_UP                      MK_ENUM_CONST(2)
+#define PADCTL_AO_SPI2_MISO_0_PUPD_RSVD                 MK_ENUM_CONST(3)
+
+#define PADCTL_AO_SPI2_MISO_0_E_INPUT_SHIFT                     MK_SHIFT_CONST(6)
+#define PADCTL_AO_SPI2_MISO_0_E_INPUT_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MISO_0_E_INPUT_SHIFT)
+#define PADCTL_AO_SPI2_MISO_0_E_INPUT_RANGE                     6:6
+#define PADCTL_AO_SPI2_MISO_0_E_INPUT_MSB                       MK_SHIFT_CONST(6)
+#define PADCTL_AO_SPI2_MISO_0_E_INPUT_LSB                       MK_SHIFT_CONST(6)
+#define PADCTL_AO_SPI2_MISO_0_E_INPUT_WOFFSET                   0x0
+#define PADCTL_AO_SPI2_MISO_0_E_INPUT_DEFAULT                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_E_INPUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_E_INPUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_E_INPUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_E_INPUT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_E_INPUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_E_INPUT_INIT_ENUM                 ENABLE
+#define PADCTL_AO_SPI2_MISO_0_E_INPUT_DISABLE                   MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MISO_0_E_INPUT_ENABLE                    MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_MISO_0_E_LPBK_SHIFT                      MK_SHIFT_CONST(7)
+#define PADCTL_AO_SPI2_MISO_0_E_LPBK_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MISO_0_E_LPBK_SHIFT)
+#define PADCTL_AO_SPI2_MISO_0_E_LPBK_RANGE                      7:7
+#define PADCTL_AO_SPI2_MISO_0_E_LPBK_MSB                        MK_SHIFT_CONST(7)
+#define PADCTL_AO_SPI2_MISO_0_E_LPBK_LSB                        MK_SHIFT_CONST(7)
+#define PADCTL_AO_SPI2_MISO_0_E_LPBK_WOFFSET                    0x0
+#define PADCTL_AO_SPI2_MISO_0_E_LPBK_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_E_LPBK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_E_LPBK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_E_LPBK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_E_LPBK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_E_LPBK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_E_LPBK_INIT_ENUM                  DISABLE
+#define PADCTL_AO_SPI2_MISO_0_E_LPBK_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MISO_0_E_LPBK_ENABLE                     MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_MISO_0_E_LPDR_SHIFT                      MK_SHIFT_CONST(8)
+#define PADCTL_AO_SPI2_MISO_0_E_LPDR_FIELD                      MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MISO_0_E_LPDR_SHIFT)
+#define PADCTL_AO_SPI2_MISO_0_E_LPDR_RANGE                      8:8
+#define PADCTL_AO_SPI2_MISO_0_E_LPDR_MSB                        MK_SHIFT_CONST(8)
+#define PADCTL_AO_SPI2_MISO_0_E_LPDR_LSB                        MK_SHIFT_CONST(8)
+#define PADCTL_AO_SPI2_MISO_0_E_LPDR_WOFFSET                    0x0
+#define PADCTL_AO_SPI2_MISO_0_E_LPDR_DEFAULT                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_E_LPDR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_E_LPDR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_E_LPDR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_E_LPDR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_E_LPDR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_E_LPDR_INIT_ENUM                  DISABLE
+#define PADCTL_AO_SPI2_MISO_0_E_LPDR_DISABLE                    MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MISO_0_E_LPDR_ENABLE                     MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_SHIFT                     MK_SHIFT_CONST(5)
+#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MISO_0_E_IO_HV_SHIFT)
+#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_RANGE                     5:5
+#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_MSB                       MK_SHIFT_CONST(5)
+#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_LSB                       MK_SHIFT_CONST(5)
+#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_WOFFSET                   0x0
+#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_DEFAULT                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_INIT_ENUM                 ENABLE
+#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_DISABLE                   MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MISO_0_E_IO_HV_ENABLE                    MK_ENUM_CONST(1)
+
+#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_SHIFT                     MK_SHIFT_CONST(12)
+#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_FIELD                     MK_FIELD_CONST(0x1, PADCTL_AO_SPI2_MISO_0_E_SCHMT_SHIFT)
+#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_RANGE                     12:12
+#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_MSB                       MK_SHIFT_CONST(12)
+#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_LSB                       MK_SHIFT_CONST(12)
+#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_WOFFSET                   0x0
+#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_DEFAULT                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_INIT_ENUM                 DISABLE
+#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_DISABLE                   MK_ENUM_CONST(0)
+#define PADCTL_AO_SPI2_MISO_0_E_SCHMT_ENABLE                    MK_ENUM_CONST(1)
+
+
+// Register PADCTL_AO_CFG2TMC_SPI2_MISO_0
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0                   MK_ADDR_CONST(0x54)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_SECURE                    0x0
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_DUAL                      0x0
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_SCR                       SCR_SPI2_MISO_0
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_SCRREG                    PADCTL_AO_SCR_SCR_SPI2_MISO_0
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_WORD_COUNT                        0x1
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_RESET_MASK                        MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_READ_MASK                         MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_WRITE_MASK                        MK_MASK_CONST(0x1f1f000)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_SHIFT                       MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_FIELD                       MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_SHIFT)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_RANGE                       16:12
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_MSB                 MK_SHIFT_CONST(16)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_LSB                 MK_SHIFT_CONST(12)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_WOFFSET                     0x0
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVDN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_SHIFT                       MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_FIELD                       MK_FIELD_CONST(0x1f, PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_SHIFT)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_RANGE                       24:20
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_MSB                 MK_SHIFT_CONST(24)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_LSB                 MK_SHIFT_CONST(20)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_WOFFSET                     0x0
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_DEFAULT                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_DEFAULT_MASK                        MK_MASK_CONST(0x1f)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PADCTL_AO_CFG2TMC_SPI2_MISO_0_CFG_CAL_DRVUP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARPADCTL_AO_REGS(_op_) \
+_op_(PADCTL_AO_TOUCH_CLK_0) \
+_op_(PADCTL_AO_CFG2TMC_TOUCH_CLK_0) \
+_op_(PADCTL_AO_UART3_RX_0) \
+_op_(PADCTL_AO_CFG2TMC_UART3_RX_0) \
+_op_(PADCTL_AO_UART3_TX_0) \
+_op_(PADCTL_AO_CFG2TMC_UART3_TX_0) \
+_op_(PADCTL_AO_GEN8_I2C_SDA_0) \
+_op_(PADCTL_AO_CFG2TMC_GEN8_I2C_SDA_0) \
+_op_(PADCTL_AO_GEN8_I2C_SCL_0) \
+_op_(PADCTL_AO_CFG2TMC_GEN8_I2C_SCL_0) \
+_op_(PADCTL_AO_SPI2_MOSI_0) \
+_op_(PADCTL_AO_CFG2TMC_SPI2_MOSI_0) \
+_op_(PADCTL_AO_GEN2_I2C_SCL_0) \
+_op_(PADCTL_AO_CFG2TMC_GEN2_I2C_SCL_0) \
+_op_(PADCTL_AO_SPI2_CS0_0) \
+_op_(PADCTL_AO_CFG2TMC_SPI2_CS0_0) \
+_op_(PADCTL_AO_GEN2_I2C_SDA_0) \
+_op_(PADCTL_AO_CFG2TMC_GEN2_I2C_SDA_0) \
+_op_(PADCTL_AO_SPI2_SCK_0) \
+_op_(PADCTL_AO_CFG2TMC_SPI2_SCK_0) \
+_op_(PADCTL_AO_SPI2_MISO_0) \
+_op_(PADCTL_AO_CFG2TMC_SPI2_MISO_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_PADCTL_AO  0x00000000
+
+//
+// ARPADCTL_AO REGISTER BANKS
+//
+
+#define PADCTL_AO0_FIRST_REG 0x0000 // PADCTL_AO_TOUCH_CLK_0
+#define PADCTL_AO0_LAST_REG 0x0054 // PADCTL_AO_CFG2TMC_SPI2_MISO_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARPADCTL_AO_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arpmc_impl.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arpmc_impl.h
new file mode 100644
index 0000000..9cee228
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arpmc_impl.h
@@ -0,0 +1,26449 @@
+//
+// Copyright (c) 2021-2022 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARPMC_IMPL_H_INC
+#define ARPMC_IMPL_H_INC
+#define NV_MOBILE_ARPMC_IMPL_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARPMC_IMPL_H_SCRREG_NOMENCLATURE INFERRED
+
+
+// Register PMC_IMPL_CNTRL_0
+#define PMC_IMPL_CNTRL_0                        MK_ADDR_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_SECURE                         0x0
+#define PMC_IMPL_CNTRL_0_DUAL                   0x0
+#define PMC_IMPL_CNTRL_0_SCR                    CNTRL_SCR_0
+#define PMC_IMPL_CNTRL_0_SCRREG                         PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_CNTRL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_CNTRL_0_RESET_VAL                      MK_MASK_CONST(0x400a00)
+#define PMC_IMPL_CNTRL_0_RESET_MASK                     MK_MASK_CONST(0x447f9f)
+#define PMC_IMPL_CNTRL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_READ_MASK                      MK_MASK_CONST(0x447f9f)
+#define PMC_IMPL_CNTRL_0_WRITE_MASK                     MK_MASK_CONST(0x447f9f)
+#define PMC_IMPL_CNTRL_0_RESERVED_1_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_CNTRL_0_RESERVED_1_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_RESERVED_1_SHIFT)
+#define PMC_IMPL_CNTRL_0_RESERVED_1_RANGE                       0:0
+#define PMC_IMPL_CNTRL_0_RESERVED_1_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_CNTRL_0_RESERVED_1_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_CNTRL_0_RESERVED_1_WOFFSET                     0x0
+#define PMC_IMPL_CNTRL_0_RESERVED_1_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_RESERVED_1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_RESERVED_1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_RESERVED_1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_RESERVED_1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_RESERVED_1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_RTC_CLK_DIS_SHIFT)
+#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_RANGE                      1:1
+#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_WOFFSET                    0x0
+#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_CNTRL_0_RTC_CLK_DIS_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_CNTRL_0_RTC_RST_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_CNTRL_0_RTC_RST_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_RTC_RST_SHIFT)
+#define PMC_IMPL_CNTRL_0_RTC_RST_RANGE                  2:2
+#define PMC_IMPL_CNTRL_0_RTC_RST_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_CNTRL_0_RTC_RST_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_CNTRL_0_RTC_RST_WOFFSET                        0x0
+#define PMC_IMPL_CNTRL_0_RTC_RST_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_RTC_RST_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_RTC_RST_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_RTC_RST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_RTC_RST_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_RTC_RST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_RTC_RST_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_CNTRL_0_RTC_RST_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_CNTRL_0_RESERVED_2_SHIFT                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_CNTRL_0_RESERVED_2_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_RESERVED_2_SHIFT)
+#define PMC_IMPL_CNTRL_0_RESERVED_2_RANGE                       3:3
+#define PMC_IMPL_CNTRL_0_RESERVED_2_MSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_CNTRL_0_RESERVED_2_LSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_CNTRL_0_RESERVED_2_WOFFSET                     0x0
+#define PMC_IMPL_CNTRL_0_RESERVED_2_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_RESERVED_2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_RESERVED_2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_RESERVED_2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_RESERVED_2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_RESERVED_2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_CNTRL_0_MAIN_RST_SHIFT                 MK_SHIFT_CONST(4)
+#define PMC_IMPL_CNTRL_0_MAIN_RST_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_MAIN_RST_SHIFT)
+#define PMC_IMPL_CNTRL_0_MAIN_RST_RANGE                 4:4
+#define PMC_IMPL_CNTRL_0_MAIN_RST_MSB                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_CNTRL_0_MAIN_RST_LSB                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_CNTRL_0_MAIN_RST_WOFFSET                       0x0
+#define PMC_IMPL_CNTRL_0_MAIN_RST_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_MAIN_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_MAIN_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_MAIN_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_MAIN_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_MAIN_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_MAIN_RST_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_CNTRL_0_MAIN_RST_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_CNTRL_0_BLINK_EN_SHIFT                 MK_SHIFT_CONST(7)
+#define PMC_IMPL_CNTRL_0_BLINK_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_BLINK_EN_SHIFT)
+#define PMC_IMPL_CNTRL_0_BLINK_EN_RANGE                 7:7
+#define PMC_IMPL_CNTRL_0_BLINK_EN_MSB                   MK_SHIFT_CONST(7)
+#define PMC_IMPL_CNTRL_0_BLINK_EN_LSB                   MK_SHIFT_CONST(7)
+#define PMC_IMPL_CNTRL_0_BLINK_EN_WOFFSET                       0x0
+#define PMC_IMPL_CNTRL_0_BLINK_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_BLINK_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_BLINK_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_BLINK_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_BLINK_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_BLINK_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_BLINK_EN_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_CNTRL_0_BLINK_EN_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_SHIFT                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_SHIFT)
+#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_RANGE                  8:8
+#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_MSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_LSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_WOFFSET                        0x0
+#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_NORMAL                 MK_ENUM_CONST(0)
+#define PMC_IMPL_CNTRL_0_PWRREQ_POLARITY_INVERT                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_CNTRL_0_PWRREQ_OE_SHIFT                        MK_SHIFT_CONST(9)
+#define PMC_IMPL_CNTRL_0_PWRREQ_OE_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_PWRREQ_OE_SHIFT)
+#define PMC_IMPL_CNTRL_0_PWRREQ_OE_RANGE                        9:9
+#define PMC_IMPL_CNTRL_0_PWRREQ_OE_MSB                  MK_SHIFT_CONST(9)
+#define PMC_IMPL_CNTRL_0_PWRREQ_OE_LSB                  MK_SHIFT_CONST(9)
+#define PMC_IMPL_CNTRL_0_PWRREQ_OE_WOFFSET                      0x0
+#define PMC_IMPL_CNTRL_0_PWRREQ_OE_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_PWRREQ_OE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_PWRREQ_OE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_PWRREQ_OE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_PWRREQ_OE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_PWRREQ_OE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_PWRREQ_OE_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_CNTRL_0_PWRREQ_OE_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_SHIFT                  MK_SHIFT_CONST(10)
+#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_SHIFT)
+#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_RANGE                  10:10
+#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_MSB                    MK_SHIFT_CONST(10)
+#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_LSB                    MK_SHIFT_CONST(10)
+#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_WOFFSET                        0x0
+#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_NORMAL                 MK_ENUM_CONST(0)
+#define PMC_IMPL_CNTRL_0_SYSCLK_POLARITY_INVERT                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_CNTRL_0_SYSCLK_OE_SHIFT                        MK_SHIFT_CONST(11)
+#define PMC_IMPL_CNTRL_0_SYSCLK_OE_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_SYSCLK_OE_SHIFT)
+#define PMC_IMPL_CNTRL_0_SYSCLK_OE_RANGE                        11:11
+#define PMC_IMPL_CNTRL_0_SYSCLK_OE_MSB                  MK_SHIFT_CONST(11)
+#define PMC_IMPL_CNTRL_0_SYSCLK_OE_LSB                  MK_SHIFT_CONST(11)
+#define PMC_IMPL_CNTRL_0_SYSCLK_OE_WOFFSET                      0x0
+#define PMC_IMPL_CNTRL_0_SYSCLK_OE_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_SYSCLK_OE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_SYSCLK_OE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_SYSCLK_OE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_SYSCLK_OE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_SYSCLK_OE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_SYSCLK_OE_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_CNTRL_0_SYSCLK_OE_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_SHIFT                      MK_SHIFT_CONST(12)
+#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_PWRGATE_DIS_SHIFT)
+#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_RANGE                      12:12
+#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_MSB                        MK_SHIFT_CONST(12)
+#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_LSB                        MK_SHIFT_CONST(12)
+#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_WOFFSET                    0x0
+#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_CNTRL_0_PWRGATE_DIS_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_CNTRL_0_AOINIT_SHIFT                   MK_SHIFT_CONST(13)
+#define PMC_IMPL_CNTRL_0_AOINIT_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_AOINIT_SHIFT)
+#define PMC_IMPL_CNTRL_0_AOINIT_RANGE                   13:13
+#define PMC_IMPL_CNTRL_0_AOINIT_MSB                     MK_SHIFT_CONST(13)
+#define PMC_IMPL_CNTRL_0_AOINIT_LSB                     MK_SHIFT_CONST(13)
+#define PMC_IMPL_CNTRL_0_AOINIT_WOFFSET                 0x0
+#define PMC_IMPL_CNTRL_0_AOINIT_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_AOINIT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_AOINIT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_AOINIT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_AOINIT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_AOINIT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_AOINIT_NOTDONE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_CNTRL_0_AOINIT_DONE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_SHIFT                  MK_SHIFT_CONST(14)
+#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_SHIFT)
+#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_RANGE                  14:14
+#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_MSB                    MK_SHIFT_CONST(14)
+#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_LSB                    MK_SHIFT_CONST(14)
+#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_WOFFSET                        0x0
+#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_CNTRL_0_SIDE_EFFECT_LP0_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_SHIFT                    MK_SHIFT_CONST(18)
+#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_SHIFT)
+#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_RANGE                    18:18
+#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_MSB                      MK_SHIFT_CONST(18)
+#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_LSB                      MK_SHIFT_CONST(18)
+#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_WOFFSET                  0x0
+#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_DISABLE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_CNTRL_0_FUSE_OVERRIDE_ENABLE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_SHIFT                      MK_SHIFT_CONST(22)
+#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL_0_SHUTDOWN_OE_SHIFT)
+#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_RANGE                      22:22
+#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_MSB                        MK_SHIFT_CONST(22)
+#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_LSB                        MK_SHIFT_CONST(22)
+#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_WOFFSET                    0x0
+#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_CNTRL_0_SHUTDOWN_OE_ENABLE                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_SLCG_CTRL_0
+#define PMC_IMPL_SLCG_CTRL_0                    MK_ADDR_CONST(0x4)
+#define PMC_IMPL_SLCG_CTRL_0_SECURE                     0x0
+#define PMC_IMPL_SLCG_CTRL_0_DUAL                       0x0
+#define PMC_IMPL_SLCG_CTRL_0_SCR                        CNTRL_SCR_0
+#define PMC_IMPL_SLCG_CTRL_0_SCRREG                     PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_SLCG_CTRL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_SLCG_CTRL_0_RESET_VAL                  MK_MASK_CONST(0x70000)
+#define PMC_IMPL_SLCG_CTRL_0_RESET_MASK                         MK_MASK_CONST(0xff0703)
+#define PMC_IMPL_SLCG_CTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_READ_MASK                  MK_MASK_CONST(0xff0703)
+#define PMC_IMPL_SLCG_CTRL_0_WRITE_MASK                         MK_MASK_CONST(0xff0703)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_SHIFT)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_RANGE                 0:0
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_WOFFSET                       0x0
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_INIT_ENUM                     DISABLE
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_SLCG_EN_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_SHIFT)
+#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_RANGE                        1:1
+#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_WOFFSET                      0x0
+#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_INIT_ENUM                    DISABLE
+#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_SLCG_CTRL_0_CLK32_SLCG_EN_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_SHIFT                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_SHIFT)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_RANGE                     8:8
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_MSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_LSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_WOFFSET                   0x0
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_INIT_ENUM                 DISABLE
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_SHIFT                      MK_SHIFT_CONST(9)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_SHIFT)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_RANGE                      9:9
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_MSB                        MK_SHIFT_CONST(9)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_LSB                        MK_SHIFT_CONST(9)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_WOFFSET                    0x0
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_INIT_ENUM                  DISABLE
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_PG_SLCG_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_SHIFT                     MK_SHIFT_CONST(10)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_SHIFT)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_RANGE                     10:10
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_MSB                       MK_SHIFT_CONST(10)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_LSB                       MK_SHIFT_CONST(10)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_WOFFSET                   0x0
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_INIT_ENUM                 DISABLE
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_DPD_SLCG_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_SHIFT                  MK_SHIFT_CONST(16)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_FIELD                  MK_FIELD_CONST(0xff, PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_SHIFT)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_RANGE                  23:16
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_MSB                    MK_SHIFT_CONST(23)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_LSB                    MK_SHIFT_CONST(16)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_WOFFSET                        0x0
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_DEFAULT                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SLCG_CTRL_0_PCLK_REG_SLCG_TIMER_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_DPD_PADS_ORIDE_0
+#define PMC_IMPL_DPD_PADS_ORIDE_0                       MK_ADDR_CONST(0x8)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SECURE                        0x0
+#define PMC_IMPL_DPD_PADS_ORIDE_0_DUAL                  0x0
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SCR                   DPD_PADS_ORIDE_SCR_0
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SCRREG                        PMC_IMPL_SCR_DPD_PADS_ORIDE_SCR_0
+#define PMC_IMPL_DPD_PADS_ORIDE_0_WORD_COUNT                    0x1
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESET_VAL                     MK_MASK_CONST(0x200000)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESET_MASK                    MK_MASK_CONST(0xffefffff)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_READ_MASK                     MK_MASK_CONST(0xffefffff)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_WRITE_MASK                    MK_MASK_CONST(0xffefffff)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_FIELD                      MK_FIELD_CONST(0xfffff, PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_SHIFT)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_RANGE                      19:0
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_MSB                        MK_SHIFT_CONST(19)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_WOFFSET                    0x0
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_DEFAULT_MASK                       MK_MASK_CONST(0xfffff)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_SHIFT                 MK_SHIFT_CONST(21)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_SHIFT)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_RANGE                 21:21
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_MSB                   MK_SHIFT_CONST(21)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_LSB                   MK_SHIFT_CONST(21)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_WOFFSET                       0x0
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_SYS_CLK_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_SHIFT                      MK_SHIFT_CONST(22)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_FIELD                      MK_FIELD_CONST(0x3ff, PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_SHIFT)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_RANGE                      31:22
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_LSB                        MK_SHIFT_CONST(22)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_WOFFSET                    0x0
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_DEFAULT_MASK                       MK_MASK_CONST(0x3ff)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_PADS_ORIDE_0_RESERVED_2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xc
+
+// Register PMC_IMPL_DPD_ENABLE_0
+#define PMC_IMPL_DPD_ENABLE_0                   MK_ADDR_CONST(0x10)
+#define PMC_IMPL_DPD_ENABLE_0_SECURE                    0x0
+#define PMC_IMPL_DPD_ENABLE_0_DUAL                      0x0
+#define PMC_IMPL_DPD_ENABLE_0_SCR                       DPD_ENABLE_SCR_0
+#define PMC_IMPL_DPD_ENABLE_0_SCRREG                    PMC_IMPL_SCR_DPD_ENABLE_SCR_0
+#define PMC_IMPL_DPD_ENABLE_0_WORD_COUNT                        0x1
+#define PMC_IMPL_DPD_ENABLE_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_ENABLE_0_RESET_MASK                        MK_MASK_CONST(0x3)
+#define PMC_IMPL_DPD_ENABLE_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_ENABLE_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_ENABLE_0_READ_MASK                         MK_MASK_CONST(0x3)
+#define PMC_IMPL_DPD_ENABLE_0_WRITE_MASK                        MK_MASK_CONST(0x3)
+#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_SHIFT)
+#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_RANGE                 1:1
+#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_WOFFSET                       0x0
+#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_DPD_ENABLE_0_TSC_MULT_EN_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_DPD_ENABLE_0_ON_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_DPD_ENABLE_0_ON_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_DPD_ENABLE_0_ON_SHIFT)
+#define PMC_IMPL_DPD_ENABLE_0_ON_RANGE                  0:0
+#define PMC_IMPL_DPD_ENABLE_0_ON_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_DPD_ENABLE_0_ON_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_DPD_ENABLE_0_ON_WOFFSET                        0x0
+#define PMC_IMPL_DPD_ENABLE_0_ON_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_ENABLE_0_ON_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_DPD_ENABLE_0_ON_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_ENABLE_0_ON_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_ENABLE_0_ON_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_ENABLE_0_ON_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_DPD_ENABLE_0_ON_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_DPD_ENABLE_0_ON_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_SC7_CONFIG_0
+#define PMC_IMPL_SC7_CONFIG_0                   MK_ADDR_CONST(0x14)
+#define PMC_IMPL_SC7_CONFIG_0_SECURE                    0x0
+#define PMC_IMPL_SC7_CONFIG_0_DUAL                      0x0
+#define PMC_IMPL_SC7_CONFIG_0_SCR                       SC78_SCR_0
+#define PMC_IMPL_SC7_CONFIG_0_SCRREG                    PMC_IMPL_SCR_SC78_SCR_0
+#define PMC_IMPL_SC7_CONFIG_0_WORD_COUNT                        0x1
+#define PMC_IMPL_SC7_CONFIG_0_RESET_VAL                         MK_MASK_CONST(0x40400)
+#define PMC_IMPL_SC7_CONFIG_0_RESET_MASK                        MK_MASK_CONST(0xffff03)
+#define PMC_IMPL_SC7_CONFIG_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_CONFIG_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_CONFIG_0_READ_MASK                         MK_MASK_CONST(0xffff03)
+#define PMC_IMPL_SC7_CONFIG_0_WRITE_MASK                        MK_MASK_CONST(0xffff03)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_SHIFT)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_RANGE                  0:0
+#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_WOFFSET                        0x0
+#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_INIT_ENUM                      SC7
+#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_SC7                    MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_TARGET_SC8                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_SHIFT                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_SHIFT)
+#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_RANGE                       1:1
+#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_MSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_LSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_WOFFSET                     0x0
+#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_INIT_ENUM                   OFF
+#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_CONFIG_0_SC8_HW_BYPASS_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_SHIFT                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_FIELD                       MK_FIELD_CONST(0xff, PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_SHIFT)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_RANGE                       15:8
+#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_MSB                 MK_SHIFT_CONST(15)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_LSB                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_WOFFSET                     0x0
+#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_DEFAULT                     MK_MASK_CONST(0x4)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_DPD_TIMER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_SHIFT                       MK_SHIFT_CONST(16)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_FIELD                       MK_FIELD_CONST(0xff, PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_SHIFT)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_RANGE                       23:16
+#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_MSB                 MK_SHIFT_CONST(23)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_LSB                 MK_SHIFT_CONST(16)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_WOFFSET                     0x0
+#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_DEFAULT                     MK_MASK_CONST(0x4)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_CONFIG_0_SC7_RES_TIMER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_SC7_STATUS_0
+#define PMC_IMPL_SC7_STATUS_0                   MK_ADDR_CONST(0x18)
+#define PMC_IMPL_SC7_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_SC7_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_SC7_STATUS_0_SCR                       SC78_SCR_0
+#define PMC_IMPL_SC7_STATUS_0_SCRREG                    PMC_IMPL_SCR_SC78_SCR_0
+#define PMC_IMPL_SC7_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_SC7_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x10)
+#define PMC_IMPL_SC7_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x1f)
+#define PMC_IMPL_SC7_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_READ_MASK                         MK_MASK_CONST(0x1f)
+#define PMC_IMPL_SC7_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_SC_STATE_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC7_STATUS_0_SC_STATE_FIELD                    MK_FIELD_CONST(0x3, PMC_IMPL_SC7_STATUS_0_SC_STATE_SHIFT)
+#define PMC_IMPL_SC7_STATUS_0_SC_STATE_RANGE                    1:0
+#define PMC_IMPL_SC7_STATUS_0_SC_STATE_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_SC7_STATUS_0_SC_STATE_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC7_STATUS_0_SC_STATE_WOFFSET                  0x0
+#define PMC_IMPL_SC7_STATUS_0_SC_STATE_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_SC_STATE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define PMC_IMPL_SC7_STATUS_0_SC_STATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_SC_STATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_SC_STATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_SC_STATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_STATUS_0_SC_STATE_INIT_ENUM                        NONE
+#define PMC_IMPL_SC7_STATUS_0_SC_STATE_NONE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_STATUS_0_SC_STATE_SC7                      MK_ENUM_CONST(1)
+#define PMC_IMPL_SC7_STATUS_0_SC_STATE_SC8                      MK_ENUM_CONST(2)
+
+#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_SHIFT)
+#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_RANGE                        2:2
+#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_WOFFSET                      0x0
+#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_INIT_ENUM                    FALSE
+#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_FALSE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_STATUS_0_SC7_FSM_BUSY_TRUE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_SHIFT                    MK_SHIFT_CONST(3)
+#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_SHIFT)
+#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_RANGE                    3:3
+#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_MSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_LSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_WOFFSET                  0x0
+#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_INIT_ENUM                        FALSE
+#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_FALSE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_STATUS_0_SC7_WAIT_DPD_DIS_TRUE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_SHIFT                 MK_SHIFT_CONST(4)
+#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_SHIFT)
+#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_RANGE                 4:4
+#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_MSB                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_LSB                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_WOFFSET                       0x0
+#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_INIT_ENUM                     TRUE
+#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_FALSE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_STATUS_0_PWRGOOD_ABS_TRUE                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_SC8_FSM_INIT_0
+#define PMC_IMPL_SC8_FSM_INIT_0                 MK_ADDR_CONST(0x1c)
+#define PMC_IMPL_SC8_FSM_INIT_0_SECURE                  0x0
+#define PMC_IMPL_SC8_FSM_INIT_0_DUAL                    0x0
+#define PMC_IMPL_SC8_FSM_INIT_0_SCR                     SC78_SCR_0
+#define PMC_IMPL_SC8_FSM_INIT_0_SCRREG                  PMC_IMPL_SCR_SC78_SCR_0
+#define PMC_IMPL_SC8_FSM_INIT_0_WORD_COUNT                      0x1
+#define PMC_IMPL_SC8_FSM_INIT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_FSM_INIT_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_FSM_INIT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_FSM_INIT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_FSM_INIT_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_FSM_INIT_0_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_SHIFT)
+#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_RANGE                  0:0
+#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_WOFFSET                        0x0
+#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_DONE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_SC8_FSM_INIT_0_FSM_INIT_PENDING                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_SC8_CONTROL_0
+#define PMC_IMPL_SC8_CONTROL_0                  MK_ADDR_CONST(0x20)
+#define PMC_IMPL_SC8_CONTROL_0_SECURE                   0x0
+#define PMC_IMPL_SC8_CONTROL_0_DUAL                     0x0
+#define PMC_IMPL_SC8_CONTROL_0_SCR                      SC78_SCR_0
+#define PMC_IMPL_SC8_CONTROL_0_SCRREG                   PMC_IMPL_SCR_SC78_SCR_0
+#define PMC_IMPL_SC8_CONTROL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_SC8_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1f)
+#define PMC_IMPL_SC8_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1f)
+#define PMC_IMPL_SC8_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1f)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_SHIFT)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_RANGE                       0:0
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_WOFFSET                     0x0
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_DONE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_RESET_PENDING                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_SHIFT                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_SHIFT)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_RANGE                       1:1
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_MSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_LSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_WOFFSET                     0x0
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_DONE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_CLAMP_PENDING                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_SHIFT)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_RANGE                        2:2
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_WOFFSET                      0x0
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_DONE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_EDPD_PENDING                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_SHIFT                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_SHIFT)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_RANGE                      3:3
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_MSB                        MK_SHIFT_CONST(3)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_LSB                        MK_SHIFT_CONST(3)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_WOFFSET                    0x0
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_DONE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SELDPD_PENDING                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_SHIFT                       MK_SHIFT_CONST(4)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_SHIFT)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_RANGE                       4:4
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_MSB                 MK_SHIFT_CONST(4)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_LSB                 MK_SHIFT_CONST(4)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_WOFFSET                     0x0
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_DONE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_SC8_CONTROL_0_REMOVE_SLEEP_PENDING                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_RETENTION_CONTROL_0
+#define PMC_IMPL_RETENTION_CONTROL_0                    MK_ADDR_CONST(0x24)
+#define PMC_IMPL_RETENTION_CONTROL_0_SECURE                     0x0
+#define PMC_IMPL_RETENTION_CONTROL_0_DUAL                       0x0
+#define PMC_IMPL_RETENTION_CONTROL_0_SCR                        SC78_SCR_0
+#define PMC_IMPL_RETENTION_CONTROL_0_SCRREG                     PMC_IMPL_SCR_SC78_SCR_0
+#define PMC_IMPL_RETENTION_CONTROL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_RETENTION_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RETENTION_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x1ff)
+#define PMC_IMPL_RETENTION_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RETENTION_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RETENTION_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x1ff)
+#define PMC_IMPL_RETENTION_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x1ff)
+#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_FIELD                  MK_FIELD_CONST(0xff, PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_SHIFT)
+#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_RANGE                  7:0
+#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_MSB                    MK_SHIFT_CONST(7)
+#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_WOFFSET                        0x0
+#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_RETENTION_CONTROL_0_RAIL_RET_EXIT_DELAY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_SHIFT                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_SHIFT)
+#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_RANGE                       8:8
+#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_MSB                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_LSB                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_WOFFSET                     0x0
+#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_DISABLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_RETENTION_CONTROL_0_GPIO_AO_RET_EN_ENABLE                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_SC7_DEBUG_CTRL_0
+#define PMC_IMPL_SC7_DEBUG_CTRL_0                       MK_ADDR_CONST(0x28)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_SECURE                        0x0
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DUAL                  0x0
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_SCR                   SC7_DEBUG_SCR_0
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_SCRREG                        PMC_IMPL_SCR_SC7_DEBUG_SCR_0
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_MASK                    MK_MASK_CONST(0x1ff)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_READ_MASK                     MK_MASK_CONST(0x1ff)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_WRITE_MASK                    MK_MASK_CONST(0x1ff)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_SHIFT                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_SHIFT)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_RANGE                       8:8
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_MSB                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_LSB                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_WOFFSET                     0x0
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_INIT_ENUM                   DISABLE
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_DISABLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_GLITCH_FREE_CLKEN_ENABLE                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_SHIFT                  MK_SHIFT_CONST(7)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_SHIFT)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_RANGE                  7:7
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_MSB                    MK_SHIFT_CONST(7)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_LSB                    MK_SHIFT_CONST(7)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_WOFFSET                        0x0
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_INIT_ENUM                      DISABLE
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBG_SLEEP_SKIP_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_SHIFT                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_SHIFT)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_RANGE                      6:6
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_MSB                        MK_SHIFT_CONST(6)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_LSB                        MK_SHIFT_CONST(6)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_WOFFSET                    0x0
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DFD_CLAMP_OVERRIDE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_SHIFT                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_SHIFT)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_RANGE                      5:5
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_MSB                        MK_SHIFT_CONST(5)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_LSB                        MK_SHIFT_CONST(5)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_WOFFSET                    0x0
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DBGRST_OVR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_SHIFT                     MK_SHIFT_CONST(4)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_SHIFT)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_RANGE                     4:4
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_MSB                       MK_SHIFT_CONST(4)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_LSB                       MK_SHIFT_CONST(4)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_WOFFSET                   0x0
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_INIT_ENUM                 OFF
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_RESET_DEBUG_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_SHIFT                        MK_SHIFT_CONST(3)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_SHIFT)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_RANGE                        3:3
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_MSB                  MK_SHIFT_CONST(3)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_LSB                  MK_SHIFT_CONST(3)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_WOFFSET                      0x0
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_INIT_ENUM                    OFF
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_DPD_ENABLE_DEBUG_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_SHIFT)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_RANGE                        2:2
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_WOFFSET                      0x0
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_INIT_ENUM                    OFF
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_MAIN_CLAMP_DEBUG_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_FIELD                      MK_FIELD_CONST(0x3, PMC_IMPL_SC7_DEBUG_CTRL_0_OP_SHIFT)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_RANGE                      1:0
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_WOFFSET                    0x0
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_INIT_ENUM                  NONE
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_NONE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_FORCE_ON                   MK_ENUM_CONST(1)
+#define PMC_IMPL_SC7_DEBUG_CTRL_0_OP_FORCE_OFF                  MK_ENUM_CONST(2)
+
+
+// Register PMC_IMPL_PWRGOOD_TIMER_0
+#define PMC_IMPL_PWRGOOD_TIMER_0                        MK_ADDR_CONST(0x2c)
+#define PMC_IMPL_PWRGOOD_TIMER_0_SECURE                         0x0
+#define PMC_IMPL_PWRGOOD_TIMER_0_DUAL                   0x0
+#define PMC_IMPL_PWRGOOD_TIMER_0_SCR                    PWRGOOD_TIMER_SCR_0
+#define PMC_IMPL_PWRGOOD_TIMER_0_SCRREG                         PMC_IMPL_SCR_PWRGOOD_TIMER_SCR_0
+#define PMC_IMPL_PWRGOOD_TIMER_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PWRGOOD_TIMER_0_RESET_VAL                      MK_MASK_CONST(0x3f00007f)
+#define PMC_IMPL_PWRGOOD_TIMER_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_PWRGOOD_TIMER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PWRGOOD_TIMER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PWRGOOD_TIMER_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_PWRGOOD_TIMER_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_FIELD                  MK_FIELD_CONST(0xffff, PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_SHIFT)
+#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_RANGE                  15:0
+#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_MSB                    MK_SHIFT_CONST(15)
+#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_WOFFSET                        0x0
+#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_DEFAULT                        MK_MASK_CONST(0x7f)
+#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_DEFAULT_MASK                   MK_MASK_CONST(0xffff)
+#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PWRGOOD_TIMER_0_PWRGOOD_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_SHIFT                      MK_SHIFT_CONST(16)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_FIELD                      MK_FIELD_CONST(0xff, PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_SHIFT)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_RANGE                      23:16
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_MSB                        MK_SHIFT_CONST(23)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_LSB                        MK_SHIFT_CONST(16)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_WOFFSET                    0x0
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_DEFAULT_MASK                       MK_MASK_CONST(0xff)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_POSTPWR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_SHIFT                       MK_SHIFT_CONST(24)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_FIELD                       MK_FIELD_CONST(0xff, PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_SHIFT)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_RANGE                       31:24
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_MSB                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_LSB                 MK_SHIFT_CONST(24)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_WOFFSET                     0x0
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_DEFAULT                     MK_MASK_CONST(0x3f)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PWRGOOD_TIMER_0_OSC_PREPWR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_BLINK_TIMER_0
+#define PMC_IMPL_BLINK_TIMER_0                  MK_ADDR_CONST(0x30)
+#define PMC_IMPL_BLINK_TIMER_0_SECURE                   0x0
+#define PMC_IMPL_BLINK_TIMER_0_DUAL                     0x0
+#define PMC_IMPL_BLINK_TIMER_0_SCR                      BLINK_TIMER_SCR_0
+#define PMC_IMPL_BLINK_TIMER_0_SCRREG                   PMC_IMPL_SCR_BLINK_TIMER_SCR_0
+#define PMC_IMPL_BLINK_TIMER_0_WORD_COUNT                       0x1
+#define PMC_IMPL_BLINK_TIMER_0_RESET_VAL                        MK_MASK_CONST(0xffff7fff)
+#define PMC_IMPL_BLINK_TIMER_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_BLINK_TIMER_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_BLINK_TIMER_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_BLINK_TIMER_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_BLINK_TIMER_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_FIELD                    MK_FIELD_CONST(0x7fff, PMC_IMPL_BLINK_TIMER_0_DATA_ON_SHIFT)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_RANGE                    14:0
+#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_MSB                      MK_SHIFT_CONST(14)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_WOFFSET                  0x0
+#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_DEFAULT                  MK_MASK_CONST(0x7fff)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_DEFAULT_MASK                     MK_MASK_CONST(0x7fff)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_ON_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_SHIFT                        MK_SHIFT_CONST(15)
+#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_SHIFT)
+#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_RANGE                        15:15
+#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_MSB                  MK_SHIFT_CONST(15)
+#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_LSB                  MK_SHIFT_CONST(15)
+#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_WOFFSET                      0x0
+#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_BLINK_TIMER_0_FORCE_BLINK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_SHIFT                   MK_SHIFT_CONST(16)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_FIELD                   MK_FIELD_CONST(0xffff, PMC_IMPL_BLINK_TIMER_0_DATA_OFF_SHIFT)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_RANGE                   31:16
+#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_MSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_LSB                     MK_SHIFT_CONST(16)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_WOFFSET                 0x0
+#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_DEFAULT                 MK_MASK_CONST(0xffff)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_BLINK_TIMER_0_DATA_OFF_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_NO_IOPOWER_0
+#define PMC_IMPL_NO_IOPOWER_0                   MK_ADDR_CONST(0x34)
+#define PMC_IMPL_NO_IOPOWER_0_SECURE                    0x0
+#define PMC_IMPL_NO_IOPOWER_0_DUAL                      0x0
+#define PMC_IMPL_NO_IOPOWER_0_SCR                       NO_IOPOWER_SCR_0
+#define PMC_IMPL_NO_IOPOWER_0_SCRREG                    PMC_IMPL_SCR_NO_IOPOWER_SCR_0
+#define PMC_IMPL_NO_IOPOWER_0_WORD_COUNT                        0x1
+#define PMC_IMPL_NO_IOPOWER_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_RESET_MASK                        MK_MASK_CONST(0x448467d)
+#define PMC_IMPL_NO_IOPOWER_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_READ_MASK                         MK_MASK_CONST(0x448467d)
+#define PMC_IMPL_NO_IOPOWER_0_WRITE_MASK                        MK_MASK_CONST(0x448467d)
+#define PMC_IMPL_NO_IOPOWER_0_SYS_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_NO_IOPOWER_0_SYS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_SYS_SHIFT)
+#define PMC_IMPL_NO_IOPOWER_0_SYS_RANGE                 0:0
+#define PMC_IMPL_NO_IOPOWER_0_SYS_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_NO_IOPOWER_0_SYS_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_NO_IOPOWER_0_SYS_WOFFSET                       0x0
+#define PMC_IMPL_NO_IOPOWER_0_SYS_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_SYS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_SYS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_SYS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_SYS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_SYS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_SYS_INIT_ENUM                     DISABLE
+#define PMC_IMPL_NO_IOPOWER_0_SYS_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_NO_IOPOWER_0_SYS_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_NO_IOPOWER_0_UART_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_NO_IOPOWER_0_UART_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_UART_SHIFT)
+#define PMC_IMPL_NO_IOPOWER_0_UART_RANGE                        2:2
+#define PMC_IMPL_NO_IOPOWER_0_UART_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_NO_IOPOWER_0_UART_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_NO_IOPOWER_0_UART_WOFFSET                      0x0
+#define PMC_IMPL_NO_IOPOWER_0_UART_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_UART_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_UART_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_UART_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_UART_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_UART_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_UART_INIT_ENUM                    DISABLE
+#define PMC_IMPL_NO_IOPOWER_0_UART_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_NO_IOPOWER_0_UART_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_NO_IOPOWER_0_CONN_SHIFT                        MK_SHIFT_CONST(3)
+#define PMC_IMPL_NO_IOPOWER_0_CONN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_CONN_SHIFT)
+#define PMC_IMPL_NO_IOPOWER_0_CONN_RANGE                        3:3
+#define PMC_IMPL_NO_IOPOWER_0_CONN_MSB                  MK_SHIFT_CONST(3)
+#define PMC_IMPL_NO_IOPOWER_0_CONN_LSB                  MK_SHIFT_CONST(3)
+#define PMC_IMPL_NO_IOPOWER_0_CONN_WOFFSET                      0x0
+#define PMC_IMPL_NO_IOPOWER_0_CONN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_CONN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_CONN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_CONN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_CONN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_CONN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_CONN_INIT_ENUM                    DISABLE
+#define PMC_IMPL_NO_IOPOWER_0_CONN_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_NO_IOPOWER_0_CONN_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_NO_IOPOWER_0_EDP_SHIFT                 MK_SHIFT_CONST(4)
+#define PMC_IMPL_NO_IOPOWER_0_EDP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_EDP_SHIFT)
+#define PMC_IMPL_NO_IOPOWER_0_EDP_RANGE                 4:4
+#define PMC_IMPL_NO_IOPOWER_0_EDP_MSB                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_NO_IOPOWER_0_EDP_LSB                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_NO_IOPOWER_0_EDP_WOFFSET                       0x0
+#define PMC_IMPL_NO_IOPOWER_0_EDP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_EDP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_EDP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_EDP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_EDP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_EDP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_EDP_INIT_ENUM                     DISABLE
+#define PMC_IMPL_NO_IOPOWER_0_EDP_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_NO_IOPOWER_0_EDP_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_NO_IOPOWER_0_AUDIO_SHIFT                       MK_SHIFT_CONST(5)
+#define PMC_IMPL_NO_IOPOWER_0_AUDIO_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_AUDIO_SHIFT)
+#define PMC_IMPL_NO_IOPOWER_0_AUDIO_RANGE                       5:5
+#define PMC_IMPL_NO_IOPOWER_0_AUDIO_MSB                 MK_SHIFT_CONST(5)
+#define PMC_IMPL_NO_IOPOWER_0_AUDIO_LSB                 MK_SHIFT_CONST(5)
+#define PMC_IMPL_NO_IOPOWER_0_AUDIO_WOFFSET                     0x0
+#define PMC_IMPL_NO_IOPOWER_0_AUDIO_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_AUDIO_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_AUDIO_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_AUDIO_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_AUDIO_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_AUDIO_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_AUDIO_INIT_ENUM                   DISABLE
+#define PMC_IMPL_NO_IOPOWER_0_AUDIO_DISABLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_NO_IOPOWER_0_AUDIO_ENABLE                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_NO_IOPOWER_0_UFS_SHIFT                 MK_SHIFT_CONST(6)
+#define PMC_IMPL_NO_IOPOWER_0_UFS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_UFS_SHIFT)
+#define PMC_IMPL_NO_IOPOWER_0_UFS_RANGE                 6:6
+#define PMC_IMPL_NO_IOPOWER_0_UFS_MSB                   MK_SHIFT_CONST(6)
+#define PMC_IMPL_NO_IOPOWER_0_UFS_LSB                   MK_SHIFT_CONST(6)
+#define PMC_IMPL_NO_IOPOWER_0_UFS_WOFFSET                       0x0
+#define PMC_IMPL_NO_IOPOWER_0_UFS_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_UFS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_UFS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_UFS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_UFS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_UFS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_UFS_INIT_ENUM                     DISABLE
+#define PMC_IMPL_NO_IOPOWER_0_UFS_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_NO_IOPOWER_0_UFS_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_NO_IOPOWER_0_MIPI_SHIFT                        MK_SHIFT_CONST(9)
+#define PMC_IMPL_NO_IOPOWER_0_MIPI_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_MIPI_SHIFT)
+#define PMC_IMPL_NO_IOPOWER_0_MIPI_RANGE                        9:9
+#define PMC_IMPL_NO_IOPOWER_0_MIPI_MSB                  MK_SHIFT_CONST(9)
+#define PMC_IMPL_NO_IOPOWER_0_MIPI_LSB                  MK_SHIFT_CONST(9)
+#define PMC_IMPL_NO_IOPOWER_0_MIPI_WOFFSET                      0x0
+#define PMC_IMPL_NO_IOPOWER_0_MIPI_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_MIPI_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_MIPI_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_MIPI_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_MIPI_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_MIPI_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_MIPI_INIT_ENUM                    DISABLE
+#define PMC_IMPL_NO_IOPOWER_0_MIPI_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_NO_IOPOWER_0_MIPI_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_NO_IOPOWER_0_CAM_SHIFT                 MK_SHIFT_CONST(10)
+#define PMC_IMPL_NO_IOPOWER_0_CAM_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_CAM_SHIFT)
+#define PMC_IMPL_NO_IOPOWER_0_CAM_RANGE                 10:10
+#define PMC_IMPL_NO_IOPOWER_0_CAM_MSB                   MK_SHIFT_CONST(10)
+#define PMC_IMPL_NO_IOPOWER_0_CAM_LSB                   MK_SHIFT_CONST(10)
+#define PMC_IMPL_NO_IOPOWER_0_CAM_WOFFSET                       0x0
+#define PMC_IMPL_NO_IOPOWER_0_CAM_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_CAM_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_CAM_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_CAM_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_CAM_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_CAM_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_CAM_INIT_ENUM                     DISABLE
+#define PMC_IMPL_NO_IOPOWER_0_CAM_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_NO_IOPOWER_0_CAM_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_SHIFT                      MK_SHIFT_CONST(14)
+#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_SDMMC4_SHIFT)
+#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_RANGE                      14:14
+#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_MSB                        MK_SHIFT_CONST(14)
+#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_LSB                        MK_SHIFT_CONST(14)
+#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_WOFFSET                    0x0
+#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_INIT_ENUM                  DISABLE
+#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_NO_IOPOWER_0_SDMMC4_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_NO_IOPOWER_0_DBG_SHIFT                 MK_SHIFT_CONST(19)
+#define PMC_IMPL_NO_IOPOWER_0_DBG_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_DBG_SHIFT)
+#define PMC_IMPL_NO_IOPOWER_0_DBG_RANGE                 19:19
+#define PMC_IMPL_NO_IOPOWER_0_DBG_MSB                   MK_SHIFT_CONST(19)
+#define PMC_IMPL_NO_IOPOWER_0_DBG_LSB                   MK_SHIFT_CONST(19)
+#define PMC_IMPL_NO_IOPOWER_0_DBG_WOFFSET                       0x0
+#define PMC_IMPL_NO_IOPOWER_0_DBG_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_DBG_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_DBG_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_DBG_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_DBG_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_DBG_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_DBG_INIT_ENUM                     DISABLE
+#define PMC_IMPL_NO_IOPOWER_0_DBG_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_NO_IOPOWER_0_DBG_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_NO_IOPOWER_0_SPI_SHIFT                 MK_SHIFT_CONST(22)
+#define PMC_IMPL_NO_IOPOWER_0_SPI_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_SPI_SHIFT)
+#define PMC_IMPL_NO_IOPOWER_0_SPI_RANGE                 22:22
+#define PMC_IMPL_NO_IOPOWER_0_SPI_MSB                   MK_SHIFT_CONST(22)
+#define PMC_IMPL_NO_IOPOWER_0_SPI_LSB                   MK_SHIFT_CONST(22)
+#define PMC_IMPL_NO_IOPOWER_0_SPI_WOFFSET                       0x0
+#define PMC_IMPL_NO_IOPOWER_0_SPI_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_SPI_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_SPI_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_SPI_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_SPI_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_SPI_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_SPI_INIT_ENUM                     DISABLE
+#define PMC_IMPL_NO_IOPOWER_0_SPI_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_NO_IOPOWER_0_SPI_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_NO_IOPOWER_0_AO_SHIFT                  MK_SHIFT_CONST(26)
+#define PMC_IMPL_NO_IOPOWER_0_AO_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_NO_IOPOWER_0_AO_SHIFT)
+#define PMC_IMPL_NO_IOPOWER_0_AO_RANGE                  26:26
+#define PMC_IMPL_NO_IOPOWER_0_AO_MSB                    MK_SHIFT_CONST(26)
+#define PMC_IMPL_NO_IOPOWER_0_AO_LSB                    MK_SHIFT_CONST(26)
+#define PMC_IMPL_NO_IOPOWER_0_AO_WOFFSET                        0x0
+#define PMC_IMPL_NO_IOPOWER_0_AO_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_AO_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_AO_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_AO_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_AO_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_NO_IOPOWER_0_AO_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_NO_IOPOWER_0_AO_INIT_ENUM                      DISABLE
+#define PMC_IMPL_NO_IOPOWER_0_AO_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_NO_IOPOWER_0_AO_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Reserved address 0x38
+
+// Register PMC_IMPL_E_18V_PWR_0
+#define PMC_IMPL_E_18V_PWR_0                    MK_ADDR_CONST(0x3c)
+#define PMC_IMPL_E_18V_PWR_0_SECURE                     0x0
+#define PMC_IMPL_E_18V_PWR_0_DUAL                       0x0
+#define PMC_IMPL_E_18V_PWR_0_SCR                        E_18V_PWR_SCR_0
+#define PMC_IMPL_E_18V_PWR_0_SCRREG                     PMC_IMPL_SCR_E_18V_PWR_SCR_0
+#define PMC_IMPL_E_18V_PWR_0_WORD_COUNT                         0x1
+#define PMC_IMPL_E_18V_PWR_0_RESET_VAL                  MK_MASK_CONST(0x70)
+#define PMC_IMPL_E_18V_PWR_0_RESET_MASK                         MK_MASK_CONST(0x72)
+#define PMC_IMPL_E_18V_PWR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_18V_PWR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_18V_PWR_0_READ_MASK                  MK_MASK_CONST(0x72)
+#define PMC_IMPL_E_18V_PWR_0_WRITE_MASK                         MK_MASK_CONST(0x72)
+#define PMC_IMPL_E_18V_PWR_0_UFS_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_E_18V_PWR_0_UFS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_E_18V_PWR_0_UFS_SHIFT)
+#define PMC_IMPL_E_18V_PWR_0_UFS_RANGE                  1:1
+#define PMC_IMPL_E_18V_PWR_0_UFS_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_E_18V_PWR_0_UFS_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_E_18V_PWR_0_UFS_WOFFSET                        0x0
+#define PMC_IMPL_E_18V_PWR_0_UFS_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_18V_PWR_0_UFS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_18V_PWR_0_UFS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_18V_PWR_0_UFS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_18V_PWR_0_UFS_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_18V_PWR_0_UFS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_18V_PWR_0_UFS_INIT_ENUM                      DISABLE
+#define PMC_IMPL_E_18V_PWR_0_UFS_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_E_18V_PWR_0_UFS_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_E_18V_PWR_0_DBG_SHIFT                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_E_18V_PWR_0_DBG_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_E_18V_PWR_0_DBG_SHIFT)
+#define PMC_IMPL_E_18V_PWR_0_DBG_RANGE                  4:4
+#define PMC_IMPL_E_18V_PWR_0_DBG_MSB                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_E_18V_PWR_0_DBG_LSB                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_E_18V_PWR_0_DBG_WOFFSET                        0x0
+#define PMC_IMPL_E_18V_PWR_0_DBG_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_18V_PWR_0_DBG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_18V_PWR_0_DBG_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_18V_PWR_0_DBG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_18V_PWR_0_DBG_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_18V_PWR_0_DBG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_18V_PWR_0_DBG_INIT_ENUM                      ENABLE
+#define PMC_IMPL_E_18V_PWR_0_DBG_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_E_18V_PWR_0_DBG_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_E_18V_PWR_0_SPI_SHIFT                  MK_SHIFT_CONST(5)
+#define PMC_IMPL_E_18V_PWR_0_SPI_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_E_18V_PWR_0_SPI_SHIFT)
+#define PMC_IMPL_E_18V_PWR_0_SPI_RANGE                  5:5
+#define PMC_IMPL_E_18V_PWR_0_SPI_MSB                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_E_18V_PWR_0_SPI_LSB                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_E_18V_PWR_0_SPI_WOFFSET                        0x0
+#define PMC_IMPL_E_18V_PWR_0_SPI_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_18V_PWR_0_SPI_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_18V_PWR_0_SPI_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_18V_PWR_0_SPI_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_18V_PWR_0_SPI_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_18V_PWR_0_SPI_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_18V_PWR_0_SPI_INIT_ENUM                      ENABLE
+#define PMC_IMPL_E_18V_PWR_0_SPI_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_E_18V_PWR_0_SPI_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_E_18V_PWR_0_EQOS_SHIFT                 MK_SHIFT_CONST(6)
+#define PMC_IMPL_E_18V_PWR_0_EQOS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_E_18V_PWR_0_EQOS_SHIFT)
+#define PMC_IMPL_E_18V_PWR_0_EQOS_RANGE                 6:6
+#define PMC_IMPL_E_18V_PWR_0_EQOS_MSB                   MK_SHIFT_CONST(6)
+#define PMC_IMPL_E_18V_PWR_0_EQOS_LSB                   MK_SHIFT_CONST(6)
+#define PMC_IMPL_E_18V_PWR_0_EQOS_WOFFSET                       0x0
+#define PMC_IMPL_E_18V_PWR_0_EQOS_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_18V_PWR_0_EQOS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_18V_PWR_0_EQOS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_18V_PWR_0_EQOS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_18V_PWR_0_EQOS_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_18V_PWR_0_EQOS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_18V_PWR_0_EQOS_INIT_ENUM                     ENABLE
+#define PMC_IMPL_E_18V_PWR_0_EQOS_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_E_18V_PWR_0_EQOS_ENABLE                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_E_33V_PWR_0
+#define PMC_IMPL_E_33V_PWR_0                    MK_ADDR_CONST(0x40)
+#define PMC_IMPL_E_33V_PWR_0_SECURE                     0x0
+#define PMC_IMPL_E_33V_PWR_0_DUAL                       0x0
+#define PMC_IMPL_E_33V_PWR_0_SCR                        E_33V_PWR_SCR_0
+#define PMC_IMPL_E_33V_PWR_0_SCRREG                     PMC_IMPL_SCR_E_33V_PWR_SCR_0
+#define PMC_IMPL_E_33V_PWR_0_WORD_COUNT                         0x1
+#define PMC_IMPL_E_33V_PWR_0_RESET_VAL                  MK_MASK_CONST(0x53)
+#define PMC_IMPL_E_33V_PWR_0_RESET_MASK                         MK_MASK_CONST(0x53)
+#define PMC_IMPL_E_33V_PWR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_33V_PWR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_33V_PWR_0_READ_MASK                  MK_MASK_CONST(0x53)
+#define PMC_IMPL_E_33V_PWR_0_WRITE_MASK                         MK_MASK_CONST(0x53)
+#define PMC_IMPL_E_33V_PWR_0_AO_HV_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_E_33V_PWR_0_AO_HV_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_E_33V_PWR_0_AO_HV_SHIFT)
+#define PMC_IMPL_E_33V_PWR_0_AO_HV_RANGE                        0:0
+#define PMC_IMPL_E_33V_PWR_0_AO_HV_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_E_33V_PWR_0_AO_HV_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_E_33V_PWR_0_AO_HV_WOFFSET                      0x0
+#define PMC_IMPL_E_33V_PWR_0_AO_HV_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_33V_PWR_0_AO_HV_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_33V_PWR_0_AO_HV_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_33V_PWR_0_AO_HV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_33V_PWR_0_AO_HV_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_33V_PWR_0_AO_HV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_33V_PWR_0_AO_HV_INIT_ENUM                    ENABLE
+#define PMC_IMPL_E_33V_PWR_0_AO_HV_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_E_33V_PWR_0_AO_HV_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_E_33V_PWR_0_AUDIO_HV_SHIFT)
+#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_RANGE                     1:1
+#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_WOFFSET                   0x0
+#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_INIT_ENUM                 ENABLE
+#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_E_33V_PWR_0_AUDIO_HV_ENABLE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_SHIFT                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_SHIFT)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_RANGE                    4:4
+#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_MSB                      MK_SHIFT_CONST(4)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_LSB                      MK_SHIFT_CONST(4)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_WOFFSET                  0x0
+#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_INIT_ENUM                        ENABLE
+#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_DISABLE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV_ENABLE                   MK_ENUM_CONST(1)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV__PROD_C_3_3V                     MK_ENUM_CONST(1)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC1_HV__PROD_C_1_8V                     MK_ENUM_CONST(0)
+
+#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_SHIFT                    MK_SHIFT_CONST(6)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_SHIFT)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_RANGE                    6:6
+#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_MSB                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_LSB                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_WOFFSET                  0x0
+#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_INIT_ENUM                        ENABLE
+#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_DISABLE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV_ENABLE                   MK_ENUM_CONST(1)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV__PROD_C_3_3V                     MK_ENUM_CONST(1)
+#define PMC_IMPL_E_33V_PWR_0_SDMMC3_HV__PROD_C_1_8V                     MK_ENUM_CONST(0)
+
+
+// Reserved address 0x44
+
+// Reserved address 0x48
+
+// Reserved address 0x4c
+
+// Reserved address 0x50
+
+// Reserved address 0x54
+
+// Reserved address 0x58
+
+// Reserved address 0x5c
+
+// Register PMC_IMPL_OSC_EDPD_OVER_0
+#define PMC_IMPL_OSC_EDPD_OVER_0                        MK_ADDR_CONST(0x60)
+#define PMC_IMPL_OSC_EDPD_OVER_0_SECURE                         0x0
+#define PMC_IMPL_OSC_EDPD_OVER_0_DUAL                   0x0
+#define PMC_IMPL_OSC_EDPD_OVER_0_SCR                    CNTRL_SCR_0
+#define PMC_IMPL_OSC_EDPD_OVER_0_SCRREG                         PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_OSC_EDPD_OVER_0_WORD_COUNT                     0x1
+#define PMC_IMPL_OSC_EDPD_OVER_0_RESET_VAL                      MK_MASK_CONST(0x2)
+#define PMC_IMPL_OSC_EDPD_OVER_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_OSC_EDPD_OVER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_READ_MASK                      MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_OSC_EDPD_OVER_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_SHIFT                   MK_SHIFT_CONST(23)
+#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_SHIFT)
+#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_RANGE                   23:23
+#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_MSB                     MK_SHIFT_CONST(23)
+#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_LSB                     MK_SHIFT_CONST(23)
+#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_WOFFSET                 0x0
+#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_DISABLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_CLK_OK_ENABLE                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_SHIFT                  MK_SHIFT_CONST(22)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_SHIFT)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_RANGE                  22:22
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_MSB                    MK_SHIFT_CONST(22)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_LSB                    MK_SHIFT_CONST(22)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_WOFFSET                        0x0
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_CAR                    MK_ENUM_CONST(0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSC_CTRL_SELECT_PMC                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_SHIFT                      MK_SHIFT_CONST(20)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_FIELD                      MK_FIELD_CONST(0x3, PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_SHIFT)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_RANGE                      21:20
+#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_MSB                        MK_SHIFT_CONST(21)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_LSB                        MK_SHIFT_CONST(20)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_WOFFSET                    0x0
+#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_DPD                        MK_ENUM_CONST(0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_OFF                        MK_ENUM_CONST(1)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_ON                 MK_ENUM_CONST(2)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XO_LP0_MODE_EXT_REQ                    MK_ENUM_CONST(3)
+
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_SHIFT                      MK_SHIFT_CONST(12)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_FIELD                      MK_FIELD_CONST(0xff, PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_SHIFT)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_RANGE                      19:12
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_MSB                        MK_SHIFT_CONST(19)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_LSB                        MK_SHIFT_CONST(12)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_WOFFSET                    0x0
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_DEFAULT_MASK                       MK_MASK_CONST(0xff)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_OSC_EDPD_OVER_0_OSCFI_SPARE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_SHIFT                     MK_SHIFT_CONST(7)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_FIELD                     MK_FIELD_CONST(0x1f, PMC_IMPL_OSC_EDPD_OVER_0_XODS_SHIFT)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_RANGE                     11:7
+#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_MSB                       MK_SHIFT_CONST(11)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_LSB                       MK_SHIFT_CONST(7)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_WOFFSET                   0x0
+#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_DEFAULT_MASK                      MK_MASK_CONST(0x1f)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XODS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_FIELD                     MK_FIELD_CONST(0x3f, PMC_IMPL_OSC_EDPD_OVER_0_XOFS_SHIFT)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_RANGE                     6:1
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_MSB                       MK_SHIFT_CONST(6)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_WOFFSET                   0x0
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_DEFAULT_MASK                      MK_MASK_CONST(0x3f)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOFS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_OSC_EDPD_OVER_0_XOBP_SHIFT)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_RANGE                     0:0
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_WOFFSET                   0x0
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_OSC_EDPD_OVER_0_XOBP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_CLK_OUT_CNTRL_0
+#define PMC_IMPL_CLK_OUT_CNTRL_0                        MK_ADDR_CONST(0x64)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_SECURE                         0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_DUAL                   0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_SCR                    CNTRL_SCR_0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_SCRREG                         PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_CLK_OUT_CNTRL_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_READ_MASK                      MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_RANGE                  0:0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_WOFFSET                        0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_ACCEPT_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_RANGE                  1:1
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_WOFFSET                        0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_INVERT_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_RANGE                    2:2
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_WOFFSET                  0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_FORCE_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_SHIFT                    MK_SHIFT_CONST(3)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_RANGE                    3:3
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_MSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_LSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_WOFFSET                  0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_RESERVED_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_SHIFT                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_FIELD                  MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_RANGE                  5:4
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_MSB                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_LSB                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_WOFFSET                        0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_LOW                    MK_ENUM_CONST(0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_HIGH                   MK_ENUM_CONST(1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_IDLE_STATE_TRIS                   MK_ENUM_CONST(2)
+
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_SHIFT                     MK_SHIFT_CONST(6)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_RANGE                     7:6
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_MSB                       MK_SHIFT_CONST(7)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_LSB                       MK_SHIFT_CONST(6)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_WOFFSET                   0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_OSC_DIV1                  MK_ENUM_CONST(0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_OSC_DIV2                  MK_ENUM_CONST(1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_OSC_DIV3                  MK_ENUM_CONST(2)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK1_SRC_SEL_CAR                       MK_ENUM_CONST(3)
+
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_SHIFT                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_RANGE                  8:8
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_MSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_LSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_WOFFSET                        0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_ACCEPT_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_SHIFT                  MK_SHIFT_CONST(9)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_RANGE                  9:9
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_MSB                    MK_SHIFT_CONST(9)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_LSB                    MK_SHIFT_CONST(9)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_WOFFSET                        0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_INVERT_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_SHIFT                    MK_SHIFT_CONST(10)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_RANGE                    10:10
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_MSB                      MK_SHIFT_CONST(10)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_LSB                      MK_SHIFT_CONST(10)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_WOFFSET                  0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_FORCE_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_SHIFT                    MK_SHIFT_CONST(11)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_RANGE                    11:11
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_MSB                      MK_SHIFT_CONST(11)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_LSB                      MK_SHIFT_CONST(11)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_WOFFSET                  0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_RESERVED_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_SHIFT                  MK_SHIFT_CONST(12)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_FIELD                  MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_RANGE                  13:12
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_MSB                    MK_SHIFT_CONST(13)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_LSB                    MK_SHIFT_CONST(12)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_WOFFSET                        0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_LOW                    MK_ENUM_CONST(0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_HIGH                   MK_ENUM_CONST(1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_IDLE_STATE_TRIS                   MK_ENUM_CONST(2)
+
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_SHIFT                     MK_SHIFT_CONST(14)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_RANGE                     15:14
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_MSB                       MK_SHIFT_CONST(15)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_LSB                       MK_SHIFT_CONST(14)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_WOFFSET                   0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_OSC_DIV1                  MK_ENUM_CONST(0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_OSC_DIV2                  MK_ENUM_CONST(1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_OSC_DIV3                  MK_ENUM_CONST(2)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK2_SRC_SEL_CAR                       MK_ENUM_CONST(3)
+
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_SHIFT                  MK_SHIFT_CONST(16)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_RANGE                  16:16
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_MSB                    MK_SHIFT_CONST(16)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_LSB                    MK_SHIFT_CONST(16)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_WOFFSET                        0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_ACCEPT_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_SHIFT                  MK_SHIFT_CONST(17)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_RANGE                  17:17
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_MSB                    MK_SHIFT_CONST(17)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_LSB                    MK_SHIFT_CONST(17)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_WOFFSET                        0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_INVERT_REQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_SHIFT                    MK_SHIFT_CONST(18)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_RANGE                    18:18
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_MSB                      MK_SHIFT_CONST(18)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_LSB                      MK_SHIFT_CONST(18)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_WOFFSET                  0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_FORCE_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_SHIFT                    MK_SHIFT_CONST(19)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_RANGE                    19:19
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_MSB                      MK_SHIFT_CONST(19)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_LSB                      MK_SHIFT_CONST(19)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_WOFFSET                  0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_RESERVED_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_SHIFT                  MK_SHIFT_CONST(20)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_FIELD                  MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_RANGE                  21:20
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_MSB                    MK_SHIFT_CONST(21)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_LSB                    MK_SHIFT_CONST(20)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_WOFFSET                        0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_LOW                    MK_ENUM_CONST(0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_HIGH                   MK_ENUM_CONST(1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_IDLE_STATE_TRIS                   MK_ENUM_CONST(2)
+
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_SHIFT                     MK_SHIFT_CONST(22)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_SHIFT)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_RANGE                     23:22
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_MSB                       MK_SHIFT_CONST(23)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_LSB                       MK_SHIFT_CONST(22)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_WOFFSET                   0x0
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_OSC_DIV1                  MK_ENUM_CONST(0)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_OSC_DIV2                  MK_ENUM_CONST(1)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_OSC_DIV3                  MK_ENUM_CONST(2)
+#define PMC_IMPL_CLK_OUT_CNTRL_0_CLK3_SRC_SEL_CAR                       MK_ENUM_CONST(3)
+
+
+// Reserved address 0x68
+
+// Register PMC_IMPL_SENSOR_CTRL_0
+#define PMC_IMPL_SENSOR_CTRL_0                  MK_ADDR_CONST(0x6c)
+#define PMC_IMPL_SENSOR_CTRL_0_SECURE                   0x0
+#define PMC_IMPL_SENSOR_CTRL_0_DUAL                     0x0
+#define PMC_IMPL_SENSOR_CTRL_0_SCR                      CNTRL_SCR_0
+#define PMC_IMPL_SENSOR_CTRL_0_SCRREG                   PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_SENSOR_CTRL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_SENSOR_CTRL_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_RESET_MASK                       MK_MASK_CONST(0xf)
+#define PMC_IMPL_SENSOR_CTRL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_READ_MASK                        MK_MASK_CONST(0xf)
+#define PMC_IMPL_SENSOR_CTRL_0_WRITE_MASK                       MK_MASK_CONST(0xf)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_SHIFT)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_RANGE                  0:0
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_WOFFSET                        0x0
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_PG_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_SHIFT)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_RANGE                 1:1
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_WOFFSET                       0x0
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_RST_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_SHIFT)
+#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_RANGE                        2:2
+#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_WOFFSET                      0x0
+#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SENSOR_CTRL_0_BLOCK_SCRATCH_WRITE_OFF_ON                       MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_SHIFT                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_SHIFT)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_RANGE                     3:3
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_MSB                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_LSB                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_WOFFSET                   0x0
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_SENSOR_CTRL_0_ENABLE_FSI_RST_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_RST_STATUS_0
+#define PMC_IMPL_RST_STATUS_0                   MK_ADDR_CONST(0x70)
+#define PMC_IMPL_RST_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_RST_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_RST_STATUS_0_SCR                       CNTRL_SCR_0
+#define PMC_IMPL_RST_STATUS_0_SCRREG                    PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_RST_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_RST_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_STATUS_0_RESET_MASK                        MK_MASK_CONST(0xff)
+#define PMC_IMPL_RST_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_STATUS_0_READ_MASK                         MK_MASK_CONST(0xff)
+#define PMC_IMPL_RST_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_FIELD                   MK_FIELD_CONST(0x3, PMC_IMPL_RST_STATUS_0_RST_LEVEL_SHIFT)
+#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_RANGE                   1:0
+#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_WOFFSET                 0x0
+#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_INIT_ENUM                       L0
+#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_L0                      MK_ENUM_CONST(0)
+#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_L1                      MK_ENUM_CONST(1)
+#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_L2                      MK_ENUM_CONST(2)
+#define PMC_IMPL_RST_STATUS_0_RST_LEVEL_WARM                    MK_ENUM_CONST(3)
+
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FIELD                  MK_FIELD_CONST(0x3f, PMC_IMPL_RST_STATUS_0_RST_SOURCE_SHIFT)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_RANGE                  7:2
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_MSB                    MK_SHIFT_CONST(7)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_WOFFSET                        0x0
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_DEFAULT_MASK                   MK_MASK_CONST(0x3f)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_INIT_ENUM                      SYS_RESET_N
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SYS_RESET_N                    MK_ENUM_CONST(0)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_AOWDT                  MK_ENUM_CONST(1)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_BCCPLEXWDT                     MK_ENUM_CONST(2)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_BPMPWDT                        MK_ENUM_CONST(3)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SCEWDT                 MK_ENUM_CONST(4)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SPEWDT                 MK_ENUM_CONST(5)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_APEWDT                 MK_ENUM_CONST(6)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_LCCPLEXWDT                     MK_ENUM_CONST(7)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SENSOR                 MK_ENUM_CONST(8)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_AOTAG                  MK_ENUM_CONST(9)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_VFSENSOR                       MK_ENUM_CONST(10)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_MAINSWRST                      MK_ENUM_CONST(11)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SC7                    MK_ENUM_CONST(12)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_HSM                    MK_ENUM_CONST(13)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_CSITE                  MK_ENUM_CONST(14)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_RCEWDT                 MK_ENUM_CONST(15)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_PVA0WDT                        MK_ENUM_CONST(16)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_PVA1WDT                        MK_ENUM_CONST(17)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_L1A_ASYNC                      MK_ENUM_CONST(18)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_BPMPBOOT                       MK_ENUM_CONST(19)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FUSECRC                        MK_ENUM_CONST(20)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_DCEWDT                 MK_ENUM_CONST(21)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_PSCWDT                 MK_ENUM_CONST(22)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_PSC_SW                 MK_ENUM_CONST(23)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_CSITE_SW                       MK_ENUM_CONST(24)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_POD                    MK_ENUM_CONST(25)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_SCPM                   MK_ENUM_CONST(26)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_VREFRO_POWERBAD                        MK_ENUM_CONST(27)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_VMON                   MK_ENUM_CONST(28)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FMON                   MK_ENUM_CONST(29)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FSI_R5WDT                      MK_ENUM_CONST(30)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FSI_THERM                      MK_ENUM_CONST(31)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FSI_R52C0WDT                   MK_ENUM_CONST(32)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FSI_R52C1WDT                   MK_ENUM_CONST(33)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FSI_R52C2WDT                   MK_ENUM_CONST(34)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FSI_R52C3WDT                   MK_ENUM_CONST(35)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FSI_FMON                       MK_ENUM_CONST(36)
+#define PMC_IMPL_RST_STATUS_0_RST_SOURCE_FSI_VMON                       MK_ENUM_CONST(37)
+
+
+// Register PMC_IMPL_IO_DPD_REQ_0
+#define PMC_IMPL_IO_DPD_REQ_0                   MK_ADDR_CONST(0x74)
+#define PMC_IMPL_IO_DPD_REQ_0_SECURE                    0x0
+#define PMC_IMPL_IO_DPD_REQ_0_DUAL                      0x0
+#define PMC_IMPL_IO_DPD_REQ_0_SCR                       0
+#define PMC_IMPL_IO_DPD_REQ_0_SCRREG                    0
+#define PMC_IMPL_IO_DPD_REQ_0_WORD_COUNT                        0x1
+#define PMC_IMPL_IO_DPD_REQ_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_REQ_0_RESET_MASK                        MK_MASK_CONST(0xc0000000)
+#define PMC_IMPL_IO_DPD_REQ_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_REQ_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_REQ_0_READ_MASK                         MK_MASK_CONST(0xc0000000)
+#define PMC_IMPL_IO_DPD_REQ_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_REQ_0_CODE_SHIFT                        MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_DPD_REQ_0_CODE_FIELD                        MK_FIELD_CONST(0x3, PMC_IMPL_IO_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_DPD_REQ_0_CODE_RANGE                        31:30
+#define PMC_IMPL_IO_DPD_REQ_0_CODE_MSB                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_DPD_REQ_0_CODE_LSB                  MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_DPD_REQ_0_CODE_WOFFSET                      0x0
+#define PMC_IMPL_IO_DPD_REQ_0_CODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_REQ_0_CODE_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_DPD_REQ_0_CODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_REQ_0_CODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_REQ_0_CODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_REQ_0_CODE_IDLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_REQ_0_CODE_DPD_OFF                      MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_REQ_0_CODE_DPD_ON                       MK_ENUM_CONST(2)
+
+
+// Reserved address 0x78
+
+// Reserved address 0x7c
+
+// Reserved address 0x80
+
+// Reserved address 0x84
+
+// Reserved address 0x88
+
+// Reserved address 0x8c
+
+// Reserved address 0x90
+
+// Reserved address 0x94
+
+// Reserved address 0x98
+
+// Reserved address 0x9c
+
+// Reserved address 0xa0
+
+// Reserved address 0xa4
+
+// Reserved address 0xa8
+
+// Reserved address 0xac
+
+// Reserved address 0xb0
+
+// Reserved address 0xb4
+
+// Reserved address 0xb8
+
+// Register PMC_IMPL_SEL_DPD_TIM_0
+#define PMC_IMPL_SEL_DPD_TIM_0                  MK_ADDR_CONST(0xbc)
+#define PMC_IMPL_SEL_DPD_TIM_0_SECURE                   0x0
+#define PMC_IMPL_SEL_DPD_TIM_0_DUAL                     0x0
+#define PMC_IMPL_SEL_DPD_TIM_0_SCR                      SEL_DPD_TIM_SCR_0
+#define PMC_IMPL_SEL_DPD_TIM_0_SCRREG                   PMC_IMPL_SCR_SEL_DPD_TIM_SCR_0
+#define PMC_IMPL_SEL_DPD_TIM_0_WORD_COUNT                       0x1
+#define PMC_IMPL_SEL_DPD_TIM_0_RESET_VAL                        MK_MASK_CONST(0x7f)
+#define PMC_IMPL_SEL_DPD_TIM_0_RESET_MASK                       MK_MASK_CONST(0x7f)
+#define PMC_IMPL_SEL_DPD_TIM_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SEL_DPD_TIM_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SEL_DPD_TIM_0_READ_MASK                        MK_MASK_CONST(0x7f)
+#define PMC_IMPL_SEL_DPD_TIM_0_WRITE_MASK                       MK_MASK_CONST(0x7f)
+#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_FIELD                        MK_FIELD_CONST(0x7f, PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_SHIFT)
+#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_RANGE                        6:0
+#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_MSB                  MK_SHIFT_CONST(6)
+#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_WOFFSET                      0x0
+#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_DEFAULT                      MK_MASK_CONST(0x7f)
+#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
+#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SEL_DPD_TIM_0_SEL_DPD_TIM_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Reserved address 0xc0
+
+// Reserved address 0xc4
+
+// Reserved address 0xc8
+
+// Reserved address 0xcc
+
+// Reserved address 0xd0
+
+// Register PMC_IMPL_TSC_MULT_0
+#define PMC_IMPL_TSC_MULT_0                     MK_ADDR_CONST(0xd4)
+#define PMC_IMPL_TSC_MULT_0_SECURE                      0x0
+#define PMC_IMPL_TSC_MULT_0_DUAL                        0x0
+#define PMC_IMPL_TSC_MULT_0_SCR                         0
+#define PMC_IMPL_TSC_MULT_0_SCRREG                      0
+#define PMC_IMPL_TSC_MULT_0_WORD_COUNT                  0x1
+#define PMC_IMPL_TSC_MULT_0_RESET_VAL                   MK_MASK_CONST(0x16e0)
+#define PMC_IMPL_TSC_MULT_0_RESET_MASK                  MK_MASK_CONST(0xeffff)
+#define PMC_IMPL_TSC_MULT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_TSC_MULT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_TSC_MULT_0_READ_MASK                   MK_MASK_CONST(0xfffff)
+#define PMC_IMPL_TSC_MULT_0_WRITE_MASK                  MK_MASK_CONST(0xeffff)
+#define PMC_IMPL_TSC_MULT_0_MULT_VAL_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_TSC_MULT_0_MULT_VAL_FIELD                      MK_FIELD_CONST(0xffff, PMC_IMPL_TSC_MULT_0_MULT_VAL_SHIFT)
+#define PMC_IMPL_TSC_MULT_0_MULT_VAL_RANGE                      15:0
+#define PMC_IMPL_TSC_MULT_0_MULT_VAL_MSB                        MK_SHIFT_CONST(15)
+#define PMC_IMPL_TSC_MULT_0_MULT_VAL_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_TSC_MULT_0_MULT_VAL_WOFFSET                    0x0
+#define PMC_IMPL_TSC_MULT_0_MULT_VAL_DEFAULT                    MK_MASK_CONST(0x16e0)
+#define PMC_IMPL_TSC_MULT_0_MULT_VAL_DEFAULT_MASK                       MK_MASK_CONST(0xffff)
+#define PMC_IMPL_TSC_MULT_0_MULT_VAL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_TSC_MULT_0_MULT_VAL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_TSC_MULT_0_MULT_VAL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_TSC_MULT_0_MULT_VAL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_TSC_MULT_0_FREQ_STS_SHIFT                      MK_SHIFT_CONST(16)
+#define PMC_IMPL_TSC_MULT_0_FREQ_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_TSC_MULT_0_FREQ_STS_SHIFT)
+#define PMC_IMPL_TSC_MULT_0_FREQ_STS_RANGE                      16:16
+#define PMC_IMPL_TSC_MULT_0_FREQ_STS_MSB                        MK_SHIFT_CONST(16)
+#define PMC_IMPL_TSC_MULT_0_FREQ_STS_LSB                        MK_SHIFT_CONST(16)
+#define PMC_IMPL_TSC_MULT_0_FREQ_STS_WOFFSET                    0x0
+#define PMC_IMPL_TSC_MULT_0_FREQ_STS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_TSC_MULT_0_FREQ_STS_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_TSC_MULT_0_FREQ_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_TSC_MULT_0_FREQ_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_TSC_MULT_0_FREQ_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_TSC_MULT_0_FREQ_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_SHIFT                      MK_SHIFT_CONST(17)
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_FIELD                      MK_FIELD_CONST(0x7, PMC_IMPL_TSC_MULT_0_TICK_SEL_SHIFT)
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_RANGE                      19:17
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_MSB                        MK_SHIFT_CONST(19)
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_LSB                        MK_SHIFT_CONST(17)
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_WOFFSET                    0x0
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT0                       MK_ENUM_CONST(0)
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT1                       MK_ENUM_CONST(1)
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT2                       MK_ENUM_CONST(2)
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT3                       MK_ENUM_CONST(3)
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT4                       MK_ENUM_CONST(4)
+#define PMC_IMPL_TSC_MULT_0_TICK_SEL_BIT5                       MK_ENUM_CONST(5)
+
+
+// Register PMC_IMPL_GLB_AMAP_CFG_0
+#define PMC_IMPL_GLB_AMAP_CFG_0                 MK_ADDR_CONST(0xd8)
+#define PMC_IMPL_GLB_AMAP_CFG_0_SECURE                  0x0
+#define PMC_IMPL_GLB_AMAP_CFG_0_DUAL                    0x0
+#define PMC_IMPL_GLB_AMAP_CFG_0_SCR                     AMAP_SCR_0
+#define PMC_IMPL_GLB_AMAP_CFG_0_SCRREG                  PMC_IMPL_SCR_AMAP_SCR_0
+#define PMC_IMPL_GLB_AMAP_CFG_0_WORD_COUNT                      0x1
+#define PMC_IMPL_GLB_AMAP_CFG_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_RESET_MASK                      MK_MASK_CONST(0x1e)
+#define PMC_IMPL_GLB_AMAP_CFG_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_READ_MASK                       MK_MASK_CONST(0x1e)
+#define PMC_IMPL_GLB_AMAP_CFG_0_WRITE_MASK                      MK_MASK_CONST(0x1e)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_SHIFT)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_RANGE                   1:1
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_WOFFSET                 0x0
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_MMIO                    MK_ENUM_CONST(0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A1_DRAM                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_SHIFT)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_RANGE                   2:2
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_WOFFSET                 0x0
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_MMIO                    MK_ENUM_CONST(0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A2_DRAM                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_SHIFT                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_SHIFT)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_RANGE                   3:3
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_MSB                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_LSB                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_WOFFSET                 0x0
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_MMIO                    MK_ENUM_CONST(0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A3_DRAM                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_SHIFT                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_SHIFT)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_RANGE                   4:4
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_MSB                     MK_SHIFT_CONST(4)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_LSB                     MK_SHIFT_CONST(4)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_WOFFSET                 0x0
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_MMIO                    MK_ENUM_CONST(0)
+#define PMC_IMPL_GLB_AMAP_CFG_0_PCIE_A4_DRAM                    MK_ENUM_CONST(1)
+
+
+// Reserved address 0xdc
+
+// Reserved address 0xe0
+
+// Reserved address 0xe4
+
+// Register PMC_IMPL_GPU_RG_CNTRL_0
+#define PMC_IMPL_GPU_RG_CNTRL_0                 MK_ADDR_CONST(0xe8)
+#define PMC_IMPL_GPU_RG_CNTRL_0_SECURE                  0x0
+#define PMC_IMPL_GPU_RG_CNTRL_0_DUAL                    0x0
+#define PMC_IMPL_GPU_RG_CNTRL_0_SCR                     GPU_SCR_0
+#define PMC_IMPL_GPU_RG_CNTRL_0_SCRREG                  PMC_IMPL_SCR_GPU_SCR_0
+#define PMC_IMPL_GPU_RG_CNTRL_0_WORD_COUNT                      0x1
+#define PMC_IMPL_GPU_RG_CNTRL_0_RESET_VAL                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_GPU_RG_CNTRL_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_GPU_RG_CNTRL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_GPU_RG_CNTRL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_GPU_RG_CNTRL_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_GPU_RG_CNTRL_0_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_SHIFT)
+#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_RANGE                        0:0
+#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_WOFFSET                      0x0
+#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_GPU_RG_CNTRL_0_RAIL_CLAMP_ENABLE                       MK_ENUM_CONST(1)
+
+
+// Reserved address 0xec
+
+// Reserved address 0xf0
+
+// Reserved address 0xf4
+
+// Register PMC_IMPL_CNTRL2_0
+#define PMC_IMPL_CNTRL2_0                       MK_ADDR_CONST(0xf8)
+#define PMC_IMPL_CNTRL2_0_SECURE                        0x0
+#define PMC_IMPL_CNTRL2_0_DUAL                  0x0
+#define PMC_IMPL_CNTRL2_0_SCR                   CNTRL_SCR_0
+#define PMC_IMPL_CNTRL2_0_SCRREG                        PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_CNTRL2_0_WORD_COUNT                    0x1
+#define PMC_IMPL_CNTRL2_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_RESET_MASK                    MK_MASK_CONST(0x1c00)
+#define PMC_IMPL_CNTRL2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_READ_MASK                     MK_MASK_CONST(0x1dfe)
+#define PMC_IMPL_CNTRL2_0_WRITE_MASK                    MK_MASK_CONST(0x1dfe)
+#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_SHIFT                 MK_SHIFT_CONST(12)
+#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_SHIFT)
+#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_RANGE                 12:12
+#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_MSB                   MK_SHIFT_CONST(12)
+#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_LSB                   MK_SHIFT_CONST(12)
+#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_WOFFSET                       0x0
+#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_CNTRL2_0_HOLD_CKE_LOW_EN_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_SHIFT                     MK_SHIFT_CONST(11)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL2_0_SYSCLK_DATA_SHIFT)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_RANGE                     11:11
+#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_MSB                       MK_SHIFT_CONST(11)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_LSB                       MK_SHIFT_CONST(11)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_WOFFSET                   0x0
+#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_DATA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_SHIFT                   MK_SHIFT_CONST(10)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_SHIFT)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_RANGE                   10:10
+#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_MSB                     MK_SHIFT_CONST(10)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_LSB                     MK_SHIFT_CONST(10)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_WOFFSET                 0x0
+#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_DISABLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_CNTRL2_0_SYSCLK_ORRIDE_ENABLE                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_CNTRL2_0_RESERVED_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_CNTRL2_0_RESERVED_FIELD                        MK_FIELD_CONST(0xff, PMC_IMPL_CNTRL2_0_RESERVED_SHIFT)
+#define PMC_IMPL_CNTRL2_0_RESERVED_RANGE                        8:1
+#define PMC_IMPL_CNTRL2_0_RESERVED_MSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_CNTRL2_0_RESERVED_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_CNTRL2_0_RESERVED_WOFFSET                      0x0
+#define PMC_IMPL_CNTRL2_0_RESERVED_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_RESERVED_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_RESERVED_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_RESERVED_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_RESERVED_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_CNTRL2_0_RESERVED_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_EVENT_COUNTER_0
+#define PMC_IMPL_EVENT_COUNTER_0                        MK_ADDR_CONST(0xfc)
+#define PMC_IMPL_EVENT_COUNTER_0_SECURE                         0x0
+#define PMC_IMPL_EVENT_COUNTER_0_DUAL                   0x0
+#define PMC_IMPL_EVENT_COUNTER_0_SCR                    EVENT_COUNTER_SCR_0
+#define PMC_IMPL_EVENT_COUNTER_0_SCRREG                         PMC_IMPL_SCR_EVENT_COUNTER_SCR_0
+#define PMC_IMPL_EVENT_COUNTER_0_WORD_COUNT                     0x1
+#define PMC_IMPL_EVENT_COUNTER_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_EVENT_COUNTER_0_RESET_MASK                     MK_MASK_CONST(0x1fffff)
+#define PMC_IMPL_EVENT_COUNTER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_EVENT_COUNTER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_EVENT_COUNTER_0_READ_MASK                      MK_MASK_CONST(0x1fffff)
+#define PMC_IMPL_EVENT_COUNTER_0_WRITE_MASK                     MK_MASK_CONST(0x1fffff)
+#define PMC_IMPL_EVENT_COUNTER_0_COUNT_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_EVENT_COUNTER_0_COUNT_FIELD                    MK_FIELD_CONST(0xffff, PMC_IMPL_EVENT_COUNTER_0_COUNT_SHIFT)
+#define PMC_IMPL_EVENT_COUNTER_0_COUNT_RANGE                    15:0
+#define PMC_IMPL_EVENT_COUNTER_0_COUNT_MSB                      MK_SHIFT_CONST(15)
+#define PMC_IMPL_EVENT_COUNTER_0_COUNT_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_EVENT_COUNTER_0_COUNT_WOFFSET                  0x0
+#define PMC_IMPL_EVENT_COUNTER_0_COUNT_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_EVENT_COUNTER_0_COUNT_DEFAULT_MASK                     MK_MASK_CONST(0xffff)
+#define PMC_IMPL_EVENT_COUNTER_0_COUNT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_EVENT_COUNTER_0_COUNT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_EVENT_COUNTER_0_COUNT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_EVENT_COUNTER_0_COUNT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_EVENT_COUNTER_0_SEL_SHIFT                      MK_SHIFT_CONST(16)
+#define PMC_IMPL_EVENT_COUNTER_0_SEL_FIELD                      MK_FIELD_CONST(0xf, PMC_IMPL_EVENT_COUNTER_0_SEL_SHIFT)
+#define PMC_IMPL_EVENT_COUNTER_0_SEL_RANGE                      19:16
+#define PMC_IMPL_EVENT_COUNTER_0_SEL_MSB                        MK_SHIFT_CONST(19)
+#define PMC_IMPL_EVENT_COUNTER_0_SEL_LSB                        MK_SHIFT_CONST(16)
+#define PMC_IMPL_EVENT_COUNTER_0_SEL_WOFFSET                    0x0
+#define PMC_IMPL_EVENT_COUNTER_0_SEL_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_EVENT_COUNTER_0_SEL_DEFAULT_MASK                       MK_MASK_CONST(0xf)
+#define PMC_IMPL_EVENT_COUNTER_0_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_EVENT_COUNTER_0_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_EVENT_COUNTER_0_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_EVENT_COUNTER_0_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_EVENT_COUNTER_0_SEL_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_EVENT_COUNTER_0_SEL_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_EVENT_COUNTER_0_EN_SHIFT                       MK_SHIFT_CONST(20)
+#define PMC_IMPL_EVENT_COUNTER_0_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_EVENT_COUNTER_0_EN_SHIFT)
+#define PMC_IMPL_EVENT_COUNTER_0_EN_RANGE                       20:20
+#define PMC_IMPL_EVENT_COUNTER_0_EN_MSB                 MK_SHIFT_CONST(20)
+#define PMC_IMPL_EVENT_COUNTER_0_EN_LSB                 MK_SHIFT_CONST(20)
+#define PMC_IMPL_EVENT_COUNTER_0_EN_WOFFSET                     0x0
+#define PMC_IMPL_EVENT_COUNTER_0_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_EVENT_COUNTER_0_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_EVENT_COUNTER_0_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_EVENT_COUNTER_0_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_EVENT_COUNTER_0_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_EVENT_COUNTER_0_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_EVENT_COUNTER_0_EN_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_EVENT_COUNTER_0_EN_ON                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x100
+
+// Register PMC_IMPL_DIRECT_THERMTRIP_CFG_0
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0                 MK_ADDR_CONST(0x104)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SECURE                  0x0
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_DUAL                    0x0
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SCR                     DIRECT_THERMTRIP_CFG_SCR_0
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SCRREG                  PMC_IMPL_SCR_DIRECT_THERMTRIP_CFG_SCR_0
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_WORD_COUNT                      0x1
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_RESET_VAL                       MK_MASK_CONST(0x10)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_RESET_MASK                      MK_MASK_CONST(0x3f)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_READ_MASK                       MK_MASK_CONST(0x3f)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_WRITE_MASK                      MK_MASK_CONST(0x3f)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_SHIFT                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_SHIFT)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_RANGE                    5:5
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_MSB                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_LSB                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_WOFFSET                  0x0
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_DISABLE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_LOCK_ENABLE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_SHIFT                      MK_SHIFT_CONST(4)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_SHIFT)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_RANGE                      4:4
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_MSB                        MK_SHIFT_CONST(4)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_LSB                        MK_SHIFT_CONST(4)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_WOFFSET                    0x0
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_THERMTRIP_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_FIELD                   MK_FIELD_CONST(0xf, PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_SHIFT)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_RANGE                   3:0
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_MSB                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_WOFFSET                 0x0
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_DIRECT_THERMTRIP_CFG_0_SHDN_ASSERT_PULSE_WIDTH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x108
+
+// Register PMC_IMPL_RAMDUMP_CTL_STATUS_0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0                   MK_ADDR_CONST(0x10c)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCR                       RAMDUMP_COM_SCR_0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCRREG                    PMC_IMPL_SCR_RAMDUMP_COM_SCR_0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RESET_MASK                        MK_MASK_CONST(0xffffe403)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_READ_MASK                         MK_MASK_CONST(0xffffe4ff)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x1fffe403)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_SHIFT                      MK_SHIFT_CONST(29)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_FIELD                      MK_FIELD_CONST(0x7, PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_RANGE                      31:29
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_LSB                        MK_SHIFT_CONST(29)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_WOFFSET                    0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_INIT_ENUM                  IDLE
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_IDLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_CACHEFLUSH                 MK_ENUM_CONST(1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_WAIT                       MK_ENUM_CONST(2)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_DRAM_SELF_REFRESH                  MK_ENUM_CONST(3)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_DEBUG_RESET_ACK                    MK_ENUM_CONST(4)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_CSTATE_WAIT_FOR_SW_ACK                    MK_ENUM_CONST(5)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_SHIFT                 MK_SHIFT_CONST(28)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_RANGE                 28:28
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_MSB                   MK_SHIFT_CONST(28)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_LSB                   MK_SHIFT_CONST(28)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_WOFFSET                       0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_HALT_IN_FIQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_SHIFT                     MK_SHIFT_CONST(27)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_RANGE                     27:27
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_MSB                       MK_SHIFT_CONST(27)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_LSB                       MK_SHIFT_CONST(27)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_WOFFSET                   0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT3_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_SHIFT                     MK_SHIFT_CONST(26)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_RANGE                     26:26
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_MSB                       MK_SHIFT_CONST(26)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_LSB                       MK_SHIFT_CONST(26)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_WOFFSET                   0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT2_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_SHIFT                   MK_SHIFT_CONST(25)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_RANGE                   25:25
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_MSB                     MK_SHIFT_CONST(25)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_LSB                     MK_SHIFT_CONST(25)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_WOFFSET                 0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DCE_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_SHIFT                   MK_SHIFT_CONST(24)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_RANGE                   24:24
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_MSB                     MK_SHIFT_CONST(24)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_LSB                     MK_SHIFT_CONST(24)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_WOFFSET                 0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RCE_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_SHIFT                   MK_SHIFT_CONST(23)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_RANGE                   23:23
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_MSB                     MK_SHIFT_CONST(23)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_LSB                     MK_SHIFT_CONST(23)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_WOFFSET                 0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_2ND_BOOT_COMPLETE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_SHIFT                     MK_SHIFT_CONST(22)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_RANGE                     22:22
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_MSB                       MK_SHIFT_CONST(22)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_LSB                       MK_SHIFT_CONST(22)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_WOFFSET                   0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_REMOTE_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_SHIFT                     MK_SHIFT_CONST(21)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_RANGE                     21:21
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_MSB                       MK_SHIFT_CONST(21)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_LSB                       MK_SHIFT_CONST(21)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_WOFFSET                   0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT1_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_SHIFT                     MK_SHIFT_CONST(20)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_RANGE                     20:20
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_MSB                       MK_SHIFT_CONST(20)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_LSB                       MK_SHIFT_CONST(20)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_WOFFSET                   0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER1_WDT0_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_SHIFT                      MK_SHIFT_CONST(19)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_RANGE                      19:19
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_MSB                        MK_SHIFT_CONST(19)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_LSB                        MK_SHIFT_CONST(19)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_WOFFSET                    0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_FSI_CLUSTER0_WDT_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_SHIFT                   MK_SHIFT_CONST(18)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_RANGE                   18:18
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_MSB                     MK_SHIFT_CONST(18)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_LSB                     MK_SHIFT_CONST(18)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_WOFFSET                 0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SCE_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_SHIFT                   MK_SHIFT_CONST(17)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_RANGE                   17:17
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_MSB                     MK_SHIFT_CONST(17)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_LSB                     MK_SHIFT_CONST(17)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_WOFFSET                 0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_APE_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_SHIFT                   MK_SHIFT_CONST(16)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_RANGE                   16:16
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_MSB                     MK_SHIFT_CONST(16)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_LSB                     MK_SHIFT_CONST(16)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_WOFFSET                 0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_SPE_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_SHIFT                  MK_SHIFT_CONST(15)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_RANGE                  15:15
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_MSB                    MK_SHIFT_CONST(15)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_LSB                    MK_SHIFT_CONST(15)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_WOFFSET                        0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_BPMP_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_SHIFT                       MK_SHIFT_CONST(14)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_RANGE                       14:14
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_MSB                 MK_SHIFT_CONST(14)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_LSB                 MK_SHIFT_CONST(14)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_WOFFSET                     0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER1_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_SHIFT                       MK_SHIFT_CONST(13)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_RANGE                       13:13
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_MSB                 MK_SHIFT_CONST(13)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_LSB                 MK_SHIFT_CONST(13)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_WOFFSET                     0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CLUSTER0_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_SHIFT                    MK_SHIFT_CONST(10)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_RANGE                    10:10
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_MSB                      MK_SHIFT_CONST(10)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_LSB                      MK_SHIFT_CONST(10)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_WOFFSET                  0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_STATUS_6_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_SHIFT                   MK_SHIFT_CONST(7)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_RANGE                   7:7
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_MSB                     MK_SHIFT_CONST(7)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_LSB                     MK_SHIFT_CONST(7)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_WOFFSET                 0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_SELF_REFRESH_REQUEST_TIMEOUT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_SHIFT                        MK_SHIFT_CONST(6)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_RANGE                        6:6
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_MSB                  MK_SHIFT_CONST(6)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_LSB                  MK_SHIFT_CONST(6)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_WOFFSET                      0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_DRAM_IN_SELF_REFRESH_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_SHIFT                   MK_SHIFT_CONST(5)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_RANGE                   5:5
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_MSB                     MK_SHIFT_CONST(5)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_LSB                     MK_SHIFT_CONST(5)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_WOFFSET                 0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_REQUEST_TIMEOUT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_SHIFT                      MK_SHIFT_CONST(4)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_RANGE                      4:4
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_MSB                        MK_SHIFT_CONST(4)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_LSB                        MK_SHIFT_CONST(4)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_WOFFSET                    0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHEFLUSH_DONE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_SHIFT                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_RANGE                     3:3
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_MSB                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_LSB                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_WOFFSET                   0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_RANGE                     2:2
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_WOFFSET                   0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_WDT_DFD_RST_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_RANGE                     1:1
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_WOFFSET                   0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_CCPLEX_CACHE_RSTDISABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_RANGE                  0:0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_WOFFSET                        0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS_0_RAMDUMP_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_RAMDUMP_TIMEOUT_0
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0                      MK_ADDR_CONST(0x110)
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_SECURE                       0x0
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_DUAL                         0x0
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_SCR                  RAMDUMP_TIMEOUT_SCR_0
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_SCRREG                       PMC_IMPL_SCR_RAMDUMP_TIMEOUT_SCR_0
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_WORD_COUNT                   0x1
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RESET_VAL                    MK_MASK_CONST(0x7d00)
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_FIELD                        MK_FIELD_CONST(0xffffffff, PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_SHIFT)
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_RANGE                        31:0
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_MSB                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_WOFFSET                      0x0
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_DEFAULT                      MK_MASK_CONST(0x7d00)
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_TIMEOUT_0_RAMDUMP_TIMEOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_RST_REQ_CONFIG_0
+#define PMC_IMPL_RST_REQ_CONFIG_0                       MK_ADDR_CONST(0x114)
+#define PMC_IMPL_RST_REQ_CONFIG_0_SECURE                        0x0
+#define PMC_IMPL_RST_REQ_CONFIG_0_DUAL                  0x0
+#define PMC_IMPL_RST_REQ_CONFIG_0_SCR                   CNTRL_SCR_0
+#define PMC_IMPL_RST_REQ_CONFIG_0_SCRREG                        PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_RST_REQ_CONFIG_0_WORD_COUNT                    0x1
+#define PMC_IMPL_RST_REQ_CONFIG_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_RESET_MASK                    MK_MASK_CONST(0xb)
+#define PMC_IMPL_RST_REQ_CONFIG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_READ_MASK                     MK_MASK_CONST(0xb)
+#define PMC_IMPL_RST_REQ_CONFIG_0_WRITE_MASK                    MK_MASK_CONST(0xb)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_SHIFT)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_RANGE                        0:0
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_WOFFSET                      0x0
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_INIT_ENUM                    DISABLE
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BWDTRST_WDT_OUT_RST_EN_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_SHIFT)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_RANGE                      1:1
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_WOFFSET                    0x0
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_INIT_ENUM                  DISABLE
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1BAOWDTRST_WDT_OUT_RST_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_SHIFT                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_SHIFT)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_RANGE                   3:3
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_MSB                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_LSB                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_WOFFSET                 0x0
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_INIT_ENUM                       DISABLE
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_DISABLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_RST_REQ_CONFIG_0_L1CRST_WDT_OUT_RST_EN_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_RST_REQ_CNTVAL_0
+#define PMC_IMPL_RST_REQ_CNTVAL_0                       MK_ADDR_CONST(0x118)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_SECURE                        0x0
+#define PMC_IMPL_RST_REQ_CNTVAL_0_DUAL                  0x0
+#define PMC_IMPL_RST_REQ_CNTVAL_0_SCR                   CNTRL_SCR_0
+#define PMC_IMPL_RST_REQ_CNTVAL_0_SCRREG                        PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_RST_REQ_CNTVAL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_RST_REQ_CNTVAL_0_RESET_VAL                     MK_MASK_CONST(0x4000000)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_FIELD                  MK_FIELD_CONST(0xff, PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_SHIFT)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_RANGE                  7:0
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_MSB                    MK_SHIFT_CONST(7)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_WOFFSET                        0x0
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1ARST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_SHIFT                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_FIELD                  MK_FIELD_CONST(0xff, PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_SHIFT)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_RANGE                  15:8
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_MSB                    MK_SHIFT_CONST(15)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_LSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_WOFFSET                        0x0
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1BRST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_SHIFT                  MK_SHIFT_CONST(16)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_FIELD                  MK_FIELD_CONST(0xff, PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_SHIFT)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_RANGE                  23:16
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_MSB                    MK_SHIFT_CONST(23)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_LSB                    MK_SHIFT_CONST(16)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_WOFFSET                        0x0
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L1CRST_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_SHIFT                   MK_SHIFT_CONST(24)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_FIELD                   MK_FIELD_CONST(0xff, PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_SHIFT)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_RANGE                   31:24
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_MSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_LSB                     MK_SHIFT_CONST(24)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_WOFFSET                 0x0
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_DEFAULT                 MK_MASK_CONST(0x4)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_RST_REQ_CNTVAL_0_L2RST_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Reserved address 0x11c
+
+// Reserved address 0x120
+
+// Reserved address 0x124
+
+// Reserved address 0x128
+
+// Reserved address 0x12c
+
+// Reserved address 0x130
+
+// Reserved address 0x134
+
+// Reserved address 0x138
+
+// Reserved address 0x13c
+
+// Reserved address 0x140
+
+// Reserved address 0x144
+
+// Reserved address 0x148
+
+// Reserved address 0x14c
+
+// Reserved address 0x150
+
+// Reserved address 0x154
+
+// Reserved address 0x158
+
+// Reserved address 0x15c
+
+// Reserved address 0x160
+
+// Reserved address 0x164
+
+// Reserved address 0x168
+
+// Reserved address 0x16c
+
+// Reserved address 0x170
+
+// Reserved address 0x174
+
+// Reserved address 0x178
+
+// Reserved address 0x17c
+
+// Reserved address 0x180
+
+// Reserved address 0x184
+
+// Reserved address 0x188
+
+// Reserved address 0x18c
+
+// Reserved address 0x190
+
+// Reserved address 0x194
+
+// Reserved address 0x198
+
+// Reserved address 0x19c
+
+// Reserved address 0x1a0
+
+// Reserved address 0x1a4
+
+// Reserved address 0x1a8
+
+// Reserved address 0x1ac
+
+// Reserved address 0x1b0
+
+// Reserved address 0x1b4
+
+// Reserved address 0x1b8
+
+// Reserved address 0x1bc
+
+// Reserved address 0x1c0
+
+// Reserved address 0x1c4
+
+// Reserved address 0x1c8
+
+// Reserved address 0x1cc
+
+// Reserved address 0x1d0
+
+// Register PMC_IMPL_VFMON_ACTION_0
+#define PMC_IMPL_VFMON_ACTION_0                 MK_ADDR_CONST(0x1d4)
+#define PMC_IMPL_VFMON_ACTION_0_SECURE                  0x0
+#define PMC_IMPL_VFMON_ACTION_0_DUAL                    0x0
+#define PMC_IMPL_VFMON_ACTION_0_SCR                     VFMON_CTRL_SCR_0
+#define PMC_IMPL_VFMON_ACTION_0_SCRREG                  PMC_IMPL_SCR_VFMON_CTRL_SCR_0
+#define PMC_IMPL_VFMON_ACTION_0_WORD_COUNT                      0x1
+#define PMC_IMPL_VFMON_ACTION_0_RESET_VAL                       MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_VFMON_ACTION_0_RESET_MASK                      MK_MASK_CONST(0x800fffff)
+#define PMC_IMPL_VFMON_ACTION_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_READ_MASK                       MK_MASK_CONST(0x800fffff)
+#define PMC_IMPL_VFMON_ACTION_0_WRITE_MASK                      MK_MASK_CONST(0x800fffff)
+#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_SHIFT)
+#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_RANGE                 1:0
+#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_WOFFSET                       0x0
+#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_INIT_ENUM                     INTR
+#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_NONE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_ACTION_0_FOSC_FAULT_ACTION_INTR                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_SHIFT)
+#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_RANGE                 3:2
+#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_MSB                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_WOFFSET                       0x0
+#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_INIT_ENUM                     INTR
+#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_NONE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_ACTION_0_F32K_FAULT_ACTION_INTR                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_SHIFT                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_FIELD                  MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_SHIFT)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_RANGE                  5:4
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_MSB                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_LSB                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_WOFFSET                        0x0
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_INIT_ENUM                      NONE
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_NONE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_INTR                   MK_ENUM_CONST(1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MIN_FAULT_ACTION_RST                    MK_ENUM_CONST(2)
+
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_SHIFT                  MK_SHIFT_CONST(6)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_FIELD                  MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_SHIFT)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_RANGE                  7:6
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_MSB                    MK_SHIFT_CONST(7)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_LSB                    MK_SHIFT_CONST(6)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_WOFFSET                        0x0
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_INIT_ENUM                      NONE
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_NONE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_INTR                   MK_ENUM_CONST(1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_SOC_MAX_FAULT_ACTION_RST                    MK_ENUM_CONST(2)
+
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_SHIFT                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_SHIFT)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_RANGE                 9:8
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_MSB                   MK_SHIFT_CONST(9)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_LSB                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_WOFFSET                       0x0
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_INIT_ENUM                     NONE
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_NONE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_INTR                  MK_ENUM_CONST(1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MIN_FAULT_ACTION_RST                   MK_ENUM_CONST(2)
+
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_SHIFT                 MK_SHIFT_CONST(10)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_SHIFT)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_RANGE                 11:10
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_MSB                   MK_SHIFT_CONST(11)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_LSB                   MK_SHIFT_CONST(10)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_WOFFSET                       0x0
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_INIT_ENUM                     NONE
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_NONE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_INTR                  MK_ENUM_CONST(1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU0_MAX_FAULT_ACTION_RST                   MK_ENUM_CONST(2)
+
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_SHIFT                 MK_SHIFT_CONST(12)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_SHIFT)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_RANGE                 13:12
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_MSB                   MK_SHIFT_CONST(13)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_LSB                   MK_SHIFT_CONST(12)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_WOFFSET                       0x0
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_INIT_ENUM                     NONE
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_NONE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_INTR                  MK_ENUM_CONST(1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MIN_FAULT_ACTION_RST                   MK_ENUM_CONST(2)
+
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_SHIFT                 MK_SHIFT_CONST(14)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_SHIFT)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_RANGE                 15:14
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_MSB                   MK_SHIFT_CONST(15)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_LSB                   MK_SHIFT_CONST(14)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_WOFFSET                       0x0
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_INIT_ENUM                     NONE
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_NONE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_INTR                  MK_ENUM_CONST(1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_CPU1_MAX_FAULT_ACTION_RST                   MK_ENUM_CONST(2)
+
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MIN_FAULT_ACTION_SHIFT                  MK_SHIFT_CONST(16)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MIN_FAULT_ACTION_FIELD                  MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MIN_FAULT_ACTION_SHIFT)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MIN_FAULT_ACTION_RANGE                  17:16
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MIN_FAULT_ACTION_MSB                    MK_SHIFT_CONST(17)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MIN_FAULT_ACTION_LSB                    MK_SHIFT_CONST(16)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MIN_FAULT_ACTION_WOFFSET                        0x0
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MIN_FAULT_ACTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MIN_FAULT_ACTION_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MIN_FAULT_ACTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MIN_FAULT_ACTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MIN_FAULT_ACTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MIN_FAULT_ACTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MIN_FAULT_ACTION_INIT_ENUM                      NONE
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MIN_FAULT_ACTION_NONE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MIN_FAULT_ACTION_INTR                   MK_ENUM_CONST(1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MIN_FAULT_ACTION_RST                    MK_ENUM_CONST(2)
+
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MAX_FAULT_ACTION_SHIFT                  MK_SHIFT_CONST(18)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MAX_FAULT_ACTION_FIELD                  MK_FIELD_CONST(0x3, PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MAX_FAULT_ACTION_SHIFT)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MAX_FAULT_ACTION_RANGE                  19:18
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MAX_FAULT_ACTION_MSB                    MK_SHIFT_CONST(19)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MAX_FAULT_ACTION_LSB                    MK_SHIFT_CONST(18)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MAX_FAULT_ACTION_WOFFSET                        0x0
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MAX_FAULT_ACTION_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MAX_FAULT_ACTION_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MAX_FAULT_ACTION_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MAX_FAULT_ACTION_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MAX_FAULT_ACTION_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MAX_FAULT_ACTION_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MAX_FAULT_ACTION_INIT_ENUM                      NONE
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MAX_FAULT_ACTION_NONE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MAX_FAULT_ACTION_INTR                   MK_ENUM_CONST(1)
+#define PMC_IMPL_VFMON_ACTION_0_VDD_FSI_MAX_FAULT_ACTION_RST                    MK_ENUM_CONST(2)
+
+#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_SHIFT                   MK_SHIFT_CONST(31)
+#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_ACTION_0_VMON_EN_SHIFT)
+#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_RANGE                   31:31
+#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_MSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_LSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_WOFFSET                 0x0
+#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_ACTION_0_VMON_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_VFMON_INT_STATUS_0
+#define PMC_IMPL_VFMON_INT_STATUS_0                     MK_ADDR_CONST(0x1d8)
+#define PMC_IMPL_VFMON_INT_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_VFMON_INT_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_VFMON_INT_STATUS_0_SCR                         VFMON_ST_SCR_0
+#define PMC_IMPL_VFMON_INT_STATUS_0_SCRREG                      PMC_IMPL_SCR_VFMON_ST_SCR_0
+#define PMC_IMPL_VFMON_INT_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_VFMON_INT_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x3ff)
+#define PMC_IMPL_VFMON_INT_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_READ_MASK                   MK_MASK_CONST(0x3ff)
+#define PMC_IMPL_VFMON_INT_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x3ff)
+#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_RANGE                    0:0
+#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_WOFFSET                  0x0
+#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_INIT_ENUM                        OFF
+#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_FOSC_FAULT_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_RANGE                    1:1
+#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_WOFFSET                  0x0
+#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_INIT_ENUM                        OFF
+#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_F32K_FAULT_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_RANGE                     2:2
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_WOFFSET                   0x0
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_INIT_ENUM                 OFF
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MIN_FAULT_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_SHIFT                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_RANGE                     3:3
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_MSB                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_LSB                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_WOFFSET                   0x0
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_INIT_ENUM                 OFF
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_SOC_MAX_FAULT_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_SHIFT                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_RANGE                    4:4
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_MSB                      MK_SHIFT_CONST(4)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_LSB                      MK_SHIFT_CONST(4)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_WOFFSET                  0x0
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_INIT_ENUM                        OFF
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MIN_FAULT_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_SHIFT                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_RANGE                    5:5
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_MSB                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_LSB                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_WOFFSET                  0x0
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_INIT_ENUM                        OFF
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU0_MAX_FAULT_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_SHIFT                    MK_SHIFT_CONST(6)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_RANGE                    6:6
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_MSB                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_LSB                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_WOFFSET                  0x0
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_INIT_ENUM                        OFF
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MIN_FAULT_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_SHIFT                    MK_SHIFT_CONST(7)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_RANGE                    7:7
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_MSB                      MK_SHIFT_CONST(7)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_LSB                      MK_SHIFT_CONST(7)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_WOFFSET                  0x0
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_INIT_ENUM                        OFF
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_CPU1_MAX_FAULT_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MIN_FAULT_SHIFT                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MIN_FAULT_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MIN_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MIN_FAULT_RANGE                     8:8
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MIN_FAULT_MSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MIN_FAULT_LSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MIN_FAULT_WOFFSET                   0x0
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MIN_FAULT_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MIN_FAULT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MIN_FAULT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MIN_FAULT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MIN_FAULT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MIN_FAULT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MIN_FAULT_INIT_ENUM                 OFF
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MIN_FAULT_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MIN_FAULT_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MAX_FAULT_SHIFT                     MK_SHIFT_CONST(9)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MAX_FAULT_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MAX_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MAX_FAULT_RANGE                     9:9
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MAX_FAULT_MSB                       MK_SHIFT_CONST(9)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MAX_FAULT_LSB                       MK_SHIFT_CONST(9)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MAX_FAULT_WOFFSET                   0x0
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MAX_FAULT_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MAX_FAULT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MAX_FAULT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MAX_FAULT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MAX_FAULT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MAX_FAULT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MAX_FAULT_INIT_ENUM                 OFF
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MAX_FAULT_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_STATUS_0_VDD_FSI_MAX_FAULT_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_VFMON_INT_MASK_0
+#define PMC_IMPL_VFMON_INT_MASK_0                       MK_ADDR_CONST(0x1dc)
+#define PMC_IMPL_VFMON_INT_MASK_0_SECURE                        0x0
+#define PMC_IMPL_VFMON_INT_MASK_0_DUAL                  0x0
+#define PMC_IMPL_VFMON_INT_MASK_0_SCR                   VFMON_ST_SCR_0
+#define PMC_IMPL_VFMON_INT_MASK_0_SCRREG                        PMC_IMPL_SCR_VFMON_ST_SCR_0
+#define PMC_IMPL_VFMON_INT_MASK_0_WORD_COUNT                    0x1
+#define PMC_IMPL_VFMON_INT_MASK_0_RESET_VAL                     MK_MASK_CONST(0x3ff)
+#define PMC_IMPL_VFMON_INT_MASK_0_RESET_MASK                    MK_MASK_CONST(0x3ff)
+#define PMC_IMPL_VFMON_INT_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_READ_MASK                     MK_MASK_CONST(0x3ff)
+#define PMC_IMPL_VFMON_INT_MASK_0_WRITE_MASK                    MK_MASK_CONST(0x3ff)
+#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_RANGE                      0:0
+#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_WOFFSET                    0x0
+#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_INIT_ENUM                  MASK
+#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_UNMASK                     MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_MASK_0_FOSC_FAULT_MASK                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_RANGE                      1:1
+#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_WOFFSET                    0x0
+#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_INIT_ENUM                  MASK
+#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_UNMASK                     MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_MASK_0_F32K_FAULT_MASK                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_SHIFT                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_RANGE                       2:2
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_MSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_LSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_WOFFSET                     0x0
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_INIT_ENUM                   MASK
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_UNMASK                      MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MIN_FAULT_MASK                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_SHIFT                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_RANGE                       3:3
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_MSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_LSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_WOFFSET                     0x0
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_INIT_ENUM                   MASK
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_UNMASK                      MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_SOC_MAX_FAULT_MASK                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_SHIFT                      MK_SHIFT_CONST(4)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_RANGE                      4:4
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_MSB                        MK_SHIFT_CONST(4)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_LSB                        MK_SHIFT_CONST(4)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_WOFFSET                    0x0
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_INIT_ENUM                  MASK
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_UNMASK                     MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MIN_FAULT_MASK                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_SHIFT                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_RANGE                      5:5
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_MSB                        MK_SHIFT_CONST(5)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_LSB                        MK_SHIFT_CONST(5)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_WOFFSET                    0x0
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_INIT_ENUM                  MASK
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_UNMASK                     MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU0_MAX_FAULT_MASK                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_SHIFT                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_RANGE                      6:6
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_MSB                        MK_SHIFT_CONST(6)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_LSB                        MK_SHIFT_CONST(6)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_WOFFSET                    0x0
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_INIT_ENUM                  MASK
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_UNMASK                     MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MIN_FAULT_MASK                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_SHIFT                      MK_SHIFT_CONST(7)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_RANGE                      7:7
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_MSB                        MK_SHIFT_CONST(7)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_LSB                        MK_SHIFT_CONST(7)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_WOFFSET                    0x0
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_INIT_ENUM                  MASK
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_UNMASK                     MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_CPU1_MAX_FAULT_MASK                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MIN_FAULT_SHIFT                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MIN_FAULT_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MIN_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MIN_FAULT_RANGE                       8:8
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MIN_FAULT_MSB                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MIN_FAULT_LSB                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MIN_FAULT_WOFFSET                     0x0
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MIN_FAULT_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MIN_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MIN_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MIN_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MIN_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MIN_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MIN_FAULT_INIT_ENUM                   MASK
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MIN_FAULT_UNMASK                      MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MIN_FAULT_MASK                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MAX_FAULT_SHIFT                       MK_SHIFT_CONST(9)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MAX_FAULT_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MAX_FAULT_SHIFT)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MAX_FAULT_RANGE                       9:9
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MAX_FAULT_MSB                 MK_SHIFT_CONST(9)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MAX_FAULT_LSB                 MK_SHIFT_CONST(9)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MAX_FAULT_WOFFSET                     0x0
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MAX_FAULT_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MAX_FAULT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MAX_FAULT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MAX_FAULT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MAX_FAULT_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MAX_FAULT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MAX_FAULT_INIT_ENUM                   MASK
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MAX_FAULT_UNMASK                      MK_ENUM_CONST(0)
+#define PMC_IMPL_VFMON_INT_MASK_0_VDD_FSI_MAX_FAULT_MASK                        MK_ENUM_CONST(1)
+
+
+// Reserved address 0x1e0
+
+// Reserved address 0x1e4
+
+// Reserved address 0x1e8
+
+// Register PMC_IMPL_POWER_GATE_TIMERS_0
+#define PMC_IMPL_POWER_GATE_TIMERS_0                    MK_ADDR_CONST(0x1ec)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_SECURE                     0x0
+#define PMC_IMPL_POWER_GATE_TIMERS_0_DUAL                       0x0
+#define PMC_IMPL_POWER_GATE_TIMERS_0_SCR                        PG_COM_SCR_0
+#define PMC_IMPL_POWER_GATE_TIMERS_0_SCRREG                     PMC_IMPL_SCR_PG_COM_SCR_0
+#define PMC_IMPL_POWER_GATE_TIMERS_0_WORD_COUNT                         0x1
+#define PMC_IMPL_POWER_GATE_TIMERS_0_RESET_VAL                  MK_MASK_CONST(0x101)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_RESET_MASK                         MK_MASK_CONST(0xffff)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_READ_MASK                  MK_MASK_CONST(0xffff)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_WRITE_MASK                         MK_MASK_CONST(0xffff)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_FIELD                  MK_FIELD_CONST(0xff, PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_SHIFT)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_RANGE                  7:0
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_MSB                    MK_SHIFT_CONST(7)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_WOFFSET                        0x0
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TZONE2FORCE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_SHIFT                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_FIELD                  MK_FIELD_CONST(0xff, PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_SHIFT)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_RANGE                  15:8
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_MSB                    MK_SHIFT_CONST(15)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_LSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_WOFFSET                        0x0
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_POWER_GATE_TIMERS_0_TFORCE2ZONE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_LOGIC_ZONE_DELAY_0
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0                     MK_ADDR_CONST(0x1f0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_SECURE                      0x0
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_DUAL                        0x0
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_SCR                         PG_COM_SCR_0
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_SCRREG                      PMC_IMPL_SCR_PG_COM_SCR_0
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_WORD_COUNT                  0x1
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_FIELD                  MK_FIELD_CONST(0xf, PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_SHIFT)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_RANGE                  3:0
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_MSB                    MK_SHIFT_CONST(3)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_WOFFSET                        0x0
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_SHIFT                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_FIELD                  MK_FIELD_CONST(0xf, PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_SHIFT)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_RANGE                  7:4
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_MSB                    MK_SHIFT_CONST(7)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_LSB                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_WOFFSET                        0x0
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_SHIFT                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_FIELD                  MK_FIELD_CONST(0xf, PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_SHIFT)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_RANGE                  11:8
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_MSB                    MK_SHIFT_CONST(11)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_LSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_WOFFSET                        0x0
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_SHIFT                  MK_SHIFT_CONST(12)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_FIELD                  MK_FIELD_CONST(0xf, PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_SHIFT)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_RANGE                  15:12
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_MSB                    MK_SHIFT_CONST(15)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_LSB                    MK_SHIFT_CONST(12)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_WOFFSET                        0x0
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_SHIFT                  MK_SHIFT_CONST(16)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_FIELD                  MK_FIELD_CONST(0xf, PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_SHIFT)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_RANGE                  19:16
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_MSB                    MK_SHIFT_CONST(19)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_LSB                    MK_SHIFT_CONST(16)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_WOFFSET                        0x0
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_SHIFT                  MK_SHIFT_CONST(20)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_FIELD                  MK_FIELD_CONST(0xf, PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_SHIFT)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_RANGE                  23:20
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_MSB                    MK_SHIFT_CONST(23)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_LSB                    MK_SHIFT_CONST(20)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_WOFFSET                        0x0
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_SHIFT                  MK_SHIFT_CONST(24)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_FIELD                  MK_FIELD_CONST(0xf, PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_SHIFT)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_RANGE                  27:24
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_MSB                    MK_SHIFT_CONST(27)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_LSB                    MK_SHIFT_CONST(24)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_WOFFSET                        0x0
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_SHIFT                  MK_SHIFT_CONST(28)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_FIELD                  MK_FIELD_CONST(0xf, PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_SHIFT)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_RANGE                  31:28
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_MSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_LSB                    MK_SHIFT_CONST(28)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_WOFFSET                        0x0
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_LOGIC_ZONE_DELAY_0_LZONE_TIMER7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_SRAM_ZONE_DELAY_0
+#define PMC_IMPL_SRAM_ZONE_DELAY_0                      MK_ADDR_CONST(0x1f4)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SECURE                       0x0
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_DUAL                         0x0
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SCR                  PG_COM_SCR_0
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SCRREG                       PMC_IMPL_SCR_PG_COM_SCR_0
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_WORD_COUNT                   0x1
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_FIELD                   MK_FIELD_CONST(0xf, PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_SHIFT)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_RANGE                   3:0
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_MSB                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_WOFFSET                 0x0
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER0_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_SHIFT                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_FIELD                   MK_FIELD_CONST(0xf, PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_SHIFT)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_RANGE                   7:4
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_MSB                     MK_SHIFT_CONST(7)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_LSB                     MK_SHIFT_CONST(4)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_WOFFSET                 0x0
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_SHIFT                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_FIELD                   MK_FIELD_CONST(0xf, PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_SHIFT)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_RANGE                   11:8
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_MSB                     MK_SHIFT_CONST(11)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_LSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_WOFFSET                 0x0
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_SHIFT                   MK_SHIFT_CONST(12)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_FIELD                   MK_FIELD_CONST(0xf, PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_SHIFT)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_RANGE                   15:12
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_MSB                     MK_SHIFT_CONST(15)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_LSB                     MK_SHIFT_CONST(12)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_WOFFSET                 0x0
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER3_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_SHIFT                   MK_SHIFT_CONST(16)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_FIELD                   MK_FIELD_CONST(0xf, PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_SHIFT)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_RANGE                   19:16
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_MSB                     MK_SHIFT_CONST(19)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_LSB                     MK_SHIFT_CONST(16)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_WOFFSET                 0x0
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER4_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_SHIFT                   MK_SHIFT_CONST(20)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_FIELD                   MK_FIELD_CONST(0xf, PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_SHIFT)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_RANGE                   23:20
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_MSB                     MK_SHIFT_CONST(23)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_LSB                     MK_SHIFT_CONST(20)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_WOFFSET                 0x0
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER5_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_SHIFT                   MK_SHIFT_CONST(24)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_FIELD                   MK_FIELD_CONST(0xf, PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_SHIFT)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_RANGE                   27:24
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_MSB                     MK_SHIFT_CONST(27)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_LSB                     MK_SHIFT_CONST(24)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_WOFFSET                 0x0
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER6_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_SHIFT                   MK_SHIFT_CONST(28)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_FIELD                   MK_FIELD_CONST(0xf, PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_SHIFT)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_RANGE                   31:28
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_MSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_LSB                     MK_SHIFT_CONST(28)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_WOFFSET                 0x0
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SRAM_ZONE_DELAY_0_SZONE_TIMER7_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_ZONE_CONFIG_0
+#define PMC_IMPL_ZONE_CONFIG_0                  MK_ADDR_CONST(0x1f8)
+#define PMC_IMPL_ZONE_CONFIG_0_SECURE                   0x0
+#define PMC_IMPL_ZONE_CONFIG_0_DUAL                     0x0
+#define PMC_IMPL_ZONE_CONFIG_0_SCR                      PG_COM_SCR_0
+#define PMC_IMPL_ZONE_CONFIG_0_SCRREG                   PMC_IMPL_SCR_PG_COM_SCR_0
+#define PMC_IMPL_ZONE_CONFIG_0_WORD_COUNT                       0x1
+#define PMC_IMPL_ZONE_CONFIG_0_RESET_VAL                        MK_MASK_CONST(0x3)
+#define PMC_IMPL_ZONE_CONFIG_0_RESET_MASK                       MK_MASK_CONST(0xf)
+#define PMC_IMPL_ZONE_CONFIG_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_ZONE_CONFIG_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_ZONE_CONFIG_0_READ_MASK                        MK_MASK_CONST(0xf)
+#define PMC_IMPL_ZONE_CONFIG_0_WRITE_MASK                       MK_MASK_CONST(0xf)
+#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_SHIFT)
+#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_RANGE                        0:0
+#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_WOFFSET                      0x0
+#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_INIT_ENUM                    ENABLE
+#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_ZONE_CONFIG_0_LOGIC_SLEEP_ZONE_EN_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_SHIFT)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_RANGE                 1:1
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_WOFFSET                       0x0
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_INIT_ENUM                     ENABLE
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_SLEEP_ZONE_EN_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_SHIFT)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_RANGE                        2:2
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_WOFFSET                      0x0
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_INIT_ENUM                    DISABLE
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_UP_ZONE_EN_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_SHIFT                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_SHIFT)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_RANGE                      3:3
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_MSB                        MK_SHIFT_CONST(3)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_LSB                        MK_SHIFT_CONST(3)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_WOFFSET                    0x0
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_INIT_ENUM                  DISABLE
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_ZONE_CONFIG_0_SRAM_PWR_DOWN_ZONE_EN_ENABLE                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_INTER_PARTITION_PG_DELAY_0
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0                     MK_ADDR_CONST(0x1fc)
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_SECURE                      0x0
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_DUAL                        0x0
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_SCR                         PG_COM_SCR_0
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_SCRREG                      PMC_IMPL_SCR_PG_COM_SCR_0
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_WORD_COUNT                  0x1
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_RESET_MASK                  MK_MASK_CONST(0xff)
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_READ_MASK                   MK_MASK_CONST(0xff)
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_WRITE_MASK                  MK_MASK_CONST(0xff)
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_FIELD                      MK_FIELD_CONST(0xff, PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_SHIFT)
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_RANGE                      7:0
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_MSB                        MK_SHIFT_CONST(7)
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_WOFFSET                    0x0
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_DEFAULT_MASK                       MK_MASK_CONST(0xff)
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_INTER_PARTITION_PG_DELAY_0_INTER_PART_DELAY_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_AO_PG_TIMERS_0
+#define PMC_IMPL_AO_PG_TIMERS_0                 MK_ADDR_CONST(0x200)
+#define PMC_IMPL_AO_PG_TIMERS_0_SECURE                  0x0
+#define PMC_IMPL_AO_PG_TIMERS_0_DUAL                    0x0
+#define PMC_IMPL_AO_PG_TIMERS_0_SCR                     PG_COM_SCR_0
+#define PMC_IMPL_AO_PG_TIMERS_0_SCRREG                  PMC_IMPL_SCR_PG_COM_SCR_0
+#define PMC_IMPL_AO_PG_TIMERS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_AO_PG_TIMERS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_AO_PG_TIMERS_0_RESET_MASK                      MK_MASK_CONST(0xffff)
+#define PMC_IMPL_AO_PG_TIMERS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_AO_PG_TIMERS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_AO_PG_TIMERS_0_READ_MASK                       MK_MASK_CONST(0xffff)
+#define PMC_IMPL_AO_PG_TIMERS_0_WRITE_MASK                      MK_MASK_CONST(0xffff)
+#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_FIELD                        MK_FIELD_CONST(0xff, PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_SHIFT)
+#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_RANGE                        7:0
+#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_MSB                  MK_SHIFT_CONST(7)
+#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_WOFFSET                      0x0
+#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_AO_PG_TIMERS_0_CLAMP2LSLEEP_DELAY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_SHIFT                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_FIELD                        MK_FIELD_CONST(0xff, PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_SHIFT)
+#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_RANGE                        15:8
+#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_MSB                  MK_SHIFT_CONST(15)
+#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_LSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_WOFFSET                      0x0
+#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_AO_PG_TIMERS_0_LSLEEP2CLAMP_DELAY_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_PG_STATUS_0
+#define PMC_IMPL_PG_STATUS_0                    MK_ADDR_CONST(0x204)
+#define PMC_IMPL_PG_STATUS_0_SECURE                     0x0
+#define PMC_IMPL_PG_STATUS_0_DUAL                       0x0
+#define PMC_IMPL_PG_STATUS_0_SCR                        PG_COM_SCR_0
+#define PMC_IMPL_PG_STATUS_0_SCRREG                     PMC_IMPL_SCR_PG_COM_SCR_0
+#define PMC_IMPL_PG_STATUS_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PG_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x2)
+#define PMC_IMPL_PG_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x3f)
+#define PMC_IMPL_PG_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_READ_MASK                  MK_MASK_CONST(0x3f)
+#define PMC_IMPL_PG_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_START_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PG_STATUS_0_PENDING_START_SHIFT)
+#define PMC_IMPL_PG_STATUS_0_PENDING_START_RANGE                        0:0
+#define PMC_IMPL_PG_STATUS_0_PENDING_START_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_START_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_START_WOFFSET                      0x0
+#define PMC_IMPL_PG_STATUS_0_PENDING_START_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PG_STATUS_0_PENDING_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PG_STATUS_0_PENDING_START_INIT_ENUM                    DONE
+#define PMC_IMPL_PG_STATUS_0_PENDING_START_DONE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_START_PENDING                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_SHIFT)
+#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_RANGE                    1:1
+#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_WOFFSET                  0x0
+#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_INIT_ENUM                        PENDING
+#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_DONE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_RESET_SLEEP_START_PENDING                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_SHIFT                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_SHIFT)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_RANGE                       2:2
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_MSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_LSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_WOFFSET                     0x0
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_INIT_ENUM                   DONE
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_DONE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_ASSERT_SLEEP_START_PENDING                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_SHIFT                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_SHIFT)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_RANGE                       3:3
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_MSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_LSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_WOFFSET                     0x0
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_INIT_ENUM                   DONE
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_DONE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_SC7_REMOVE_SLEEP_START_PENDING                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_SHIFT                 MK_SHIFT_CONST(4)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_SHIFT)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_RANGE                 4:4
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_MSB                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_LSB                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_WOFFSET                       0x0
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_INIT_ENUM                     DONE
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_DONE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_RET_REQ_START_PENDING                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_SHIFT                       MK_SHIFT_CONST(5)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_SHIFT)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_RANGE                       5:5
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_MSB                 MK_SHIFT_CONST(5)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_LSB                 MK_SHIFT_CONST(5)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_WOFFSET                     0x0
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_INIT_ENUM                   DONE
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_DONE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PG_STATUS_0_PENDING_PM2PMC_UNRET_REQ_START_PENDING                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0                  MK_ADDR_CONST(0x208)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SECURE                   0x0
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_DUAL                     0x0
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SCR                      PG_AUD_SCR_0
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_AUD_SCR_0
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_SHIFT                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_RANGE                      8:8
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_MSB                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_LSB                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_DONE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_START_PENDING                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  ON
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    ON
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0                   MK_ADDR_CONST(0x20c)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SCR                       PG_AUD_SCR_0
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_AUD_SCR_0
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  ON
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 ON
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AUD_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0                       MK_ADDR_CONST(0x210)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_SCR                   PG_AUD_SCR_0
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_AUD_SCR_0
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       ON
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AUD_CLAMP_CONTROL_0_CLAMP_ON                      MK_ENUM_CONST(1)
+
+
+// Reserved address 0x214
+
+// Reserved address 0x218
+
+// Reserved address 0x21c
+
+// Register PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0                 MK_ADDR_CONST(0x220)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SECURE                  0x0
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_DUAL                    0x0
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SCR                     PG_DISP_SCR_0
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_DISP_SCR_0
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                       31:31
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                     0x0
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                   ENABLE
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_SHIFT                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_RANGE                     8:8
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_MSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_LSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_WOFFSET                   0x0
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_INIT_ENUM                 DONE
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_DONE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_START_PENDING                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                     2:2
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                   0x0
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                 ON
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                       1:1
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                     0x0
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                       0:0
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                     0x0
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                   ON
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0                  MK_ADDR_CONST(0x224)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SECURE                   0x0
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_DUAL                     0x0
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SCR                      PG_DISP_SCR_0
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SCRREG                   PMC_IMPL_SCR_PG_DISP_SCR_0
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_READ_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                     2:2
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                   0x0
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                 ON
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                       1:1
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                     0x0
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                    0:0
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                        ON
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_DISP_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0                      MK_ADDR_CONST(0x228)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_SECURE                       0x0
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_DUAL                         0x0
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_SCR                  PG_DISP_SCR_0
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_DISP_SCR_0
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_RANGE                  0:0
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_WOFFSET                        0x0
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                      ON
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DISP_CLAMP_CONTROL_0_CLAMP_ON                     MK_ENUM_CONST(1)
+
+
+// Reserved address 0x22c
+
+// Reserved address 0x230
+
+// Reserved address 0x234
+
+// Reserved address 0x238
+
+// Reserved address 0x23c
+
+// Reserved address 0x240
+
+// Reserved address 0x244
+
+// Reserved address 0x248
+
+// Reserved address 0x24c
+
+// Reserved address 0x250
+
+// Reserved address 0x254
+
+// Reserved address 0x258
+
+// Reserved address 0x25c
+
+// Reserved address 0x260
+
+// Reserved address 0x264
+
+// Reserved address 0x268
+
+// Reserved address 0x26c
+
+// Reserved address 0x270
+
+// Reserved address 0x274
+
+// Reserved address 0x278
+
+// Reserved address 0x27c
+
+// Reserved address 0x280
+
+// Reserved address 0x284
+
+// Reserved address 0x288
+
+// Reserved address 0x28c
+
+// Reserved address 0x290
+
+// Reserved address 0x294
+
+// Register PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0                  MK_ADDR_CONST(0x298)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SECURE                   0x0
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_DUAL                     0x0
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SCR                      PG_VIC_SCR_0
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_VIC_SCR_0
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_SHIFT                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_RANGE                      8:8
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_MSB                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_LSB                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_DONE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_START_PENDING                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  ON
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    ON
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0                   MK_ADDR_CONST(0x29c)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SCR                       PG_VIC_SCR_0
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_VIC_SCR_0
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  ON
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 ON
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_VIC_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0                       MK_ADDR_CONST(0x2a0)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_SCR                   PG_VIC_SCR_0
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_VIC_SCR_0
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       ON
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VIC_CLAMP_CONTROL_0_CLAMP_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x2a4)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SCR                    PG_XUSBA_SCR_0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_XUSBA_SCR_0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_RANGE                    8:8
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x2a8)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SCR                     PG_XUSBA_SCR_0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_XUSBA_SCR_0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x2ac)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_SCR                         PG_XUSBA_SCR_0
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_XUSBA_SCR_0
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     OFF
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x2b0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SCR                    PG_XUSBB_SCR_0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_XUSBB_SCR_0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_RANGE                    8:8
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x2b4)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SCR                     PG_XUSBB_SCR_0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_XUSBB_SCR_0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x2b8)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_SCR                         PG_XUSBB_SCR_0
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_XUSBB_SCR_0
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     OFF
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x2bc)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SCR                    PG_XUSBC_SCR_0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_XUSBC_SCR_0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_RANGE                    8:8
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x2c0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SCR                     PG_XUSBC_SCR_0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_XUSBC_SCR_0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x2c4)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_SCR                         PG_XUSBC_SCR_0
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_XUSBC_SCR_0
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     OFF
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0                      MK_ADDR_CONST(0x2c8)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SECURE                       0x0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_DUAL                         0x0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SCR                  PG_SCRATCH_SCR_0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_SCRATCH_SCR_0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x80000106)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                    31:31
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                        ENABLE
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_SHIFT                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_RANGE                  8:8
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_MSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_LSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_WOFFSET                        0x0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_INIT_ENUM                      DONE
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_DONE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_START_PENDING                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                  2:2
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                    1:1
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                    0:0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                  0x0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0                       MK_ADDR_CONST(0x2cc)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SECURE                        0x0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_DUAL                  0x0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SCR                   PG_SCRATCH_SCR_0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_SCRATCH_SCR_0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                  2:2
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                    1:1
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                 0:0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                       0x0
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                     OFF
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0                   MK_ADDR_CONST(0x2d0)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_SECURE                    0x0
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_DUAL                      0x0
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_SCR                       PG_SCRATCH_SCR_0
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_SCRREG                    PMC_IMPL_SCR_PG_SCRATCH_SCR_0
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_RANGE                       0:0
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_WOFFSET                     0x0
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0_CLAMP_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x2d4)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SCR                    PG_AONPG_SCR_0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_AONPG_SCR_0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000106)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_RANGE                    8:8
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x2d8)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SCR                     PG_AONPG_SCR_0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_AONPG_SCR_0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x2dc)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_SCR                         PG_AONPG_SCR_0
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_AONPG_SCR_0
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     OFF
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)
+
+
+// Reserved address 0x2e0
+
+// Reserved address 0x2e4
+
+// Reserved address 0x2e8
+
+// Reserved address 0x2ec
+
+// Reserved address 0x2f0
+
+// Reserved address 0x2f4
+
+// Reserved address 0x2f8
+
+// Reserved address 0x2fc
+
+// Reserved address 0x300
+
+// Reserved address 0x304
+
+// Reserved address 0x308
+
+// Reserved address 0x30c
+
+// Reserved address 0x310
+
+// Reserved address 0x314
+
+// Reserved address 0x318
+
+// Reserved address 0x31c
+
+// Reserved address 0x320
+
+// Reserved address 0x324
+
+// Reserved address 0x328
+
+// Reserved address 0x32c
+
+// Reserved address 0x330
+
+// Reserved address 0x334
+
+// Reserved address 0x338
+
+// Reserved address 0x33c
+
+// Reserved address 0x340
+
+// Reserved address 0x344
+
+// Reserved address 0x348
+
+// Reserved address 0x34c
+
+// Reserved address 0x350
+
+// Reserved address 0x354
+
+// Reserved address 0x358
+
+// Reserved address 0x35c
+
+// Reserved address 0x360
+
+// Reserved address 0x364
+
+// Reserved address 0x368
+
+// Reserved address 0x36c
+
+// Reserved address 0x370
+
+// Reserved address 0x374
+
+// Reserved address 0x378
+
+// Reserved address 0x37c
+
+// Reserved address 0x380
+
+// Reserved address 0x384
+
+// Register PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x388)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SECURE                     0x0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_DUAL                       0x0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM0_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_TCM0_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_RANGE                        8:8
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x38c)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM0_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_TCM0_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x390)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_SECURE                  0x0
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_DUAL                    0x0
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM0_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_TCM0_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x394)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SECURE                     0x0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_DUAL                       0x0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM1_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_TCM1_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_RANGE                        8:8
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x398)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM1_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_TCM1_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x39c)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_SECURE                  0x0
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_DUAL                    0x0
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM1_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_TCM1_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x3a0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SECURE                     0x0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_DUAL                       0x0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM2_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_TCM2_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_RANGE                        8:8
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x3a4)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM2_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_TCM2_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x3a8)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_SECURE                  0x0
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_DUAL                    0x0
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM2_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_TCM2_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x3ac)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SECURE                     0x0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_DUAL                       0x0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM3_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_TCM3_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_RANGE                        8:8
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x3b0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM3_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_TCM3_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x3b4)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_SECURE                  0x0
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_DUAL                    0x0
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM3_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_TCM3_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x3b8)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SECURE                     0x0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_DUAL                       0x0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM4_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_TCM4_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_RANGE                        8:8
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x3bc)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM4_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_TCM4_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x3c0)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_SECURE                  0x0
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_DUAL                    0x0
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM4_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_TCM4_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x3c4)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SECURE                     0x0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_DUAL                       0x0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM5_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_TCM5_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_RANGE                        8:8
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x3c8)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM5_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_TCM5_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x3cc)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_SECURE                  0x0
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_DUAL                    0x0
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM5_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_TCM5_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x3d0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SECURE                     0x0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_DUAL                       0x0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM6_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_TCM6_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_RANGE                        8:8
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x3d4)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM6_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_TCM6_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x3d8)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_SECURE                  0x0
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_DUAL                    0x0
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM6_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_TCM6_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x3dc)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SECURE                     0x0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_DUAL                       0x0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_TCM7_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_TCM7_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_RANGE                        8:8
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x3e0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SCR                         PG_AOPG_TCM7_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_TCM7_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x3e4)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_SECURE                  0x0
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_DUAL                    0x0
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_SCR                     PG_AOPG_TCM7_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_TCM7_SCR_0
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0                   MK_ADDR_CONST(0x3e8)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SECURE                    0x0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_DUAL                      0x0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SCR                       PG_AOPG_CACHE_SCR_0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SCRREG                    PMC_IMPL_SCR_PG_AOPG_CACHE_SCR_0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_RESET_VAL                         MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_RESET_MASK                        MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_READ_MASK                         MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_WRITE_MASK                        MK_MASK_CONST(0x80000106)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                 31:31
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                   MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                   MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                       0x0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                     ENABLE
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_SHIFT                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_RANGE                       8:8
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_MSB                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_LSB                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_WOFFSET                     0x0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_INIT_ENUM                   DONE
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_DONE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_PENDING                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                       2:2
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                     0x0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                 1:1
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                       0x0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                     OFF
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                 0:0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                       0x0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                     OFF
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0                    MK_ADDR_CONST(0x3ec)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SECURE                     0x0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_DUAL                       0x0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SCR                        PG_AOPG_CACHE_SCR_0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_CACHE_SCR_0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_READ_MASK                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                       2:2
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                     0x0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                 1:1
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                       0x0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                     OFF
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                      0:0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0                        MK_ADDR_CONST(0x3f0)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_SCR                    PG_AOPG_CACHE_SCR_0
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_AOPG_CACHE_SCR_0
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_RANGE                    0:0
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_WOFFSET                  0x0
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0_CLAMP_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x3f4)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SECURE                     0x0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_DUAL                       0x0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_CAN0_SCR_0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_CAN0_SCR_0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_RANGE                        8:8
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x3f8)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SCR                         PG_AOPG_CAN0_SCR_0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_CAN0_SCR_0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x3fc)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_SECURE                  0x0
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_DUAL                    0x0
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_SCR                     PG_AOPG_CAN0_SCR_0
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_CAN0_SCR_0
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0                    MK_ADDR_CONST(0x400)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SECURE                     0x0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_DUAL                       0x0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SCR                        PG_AOPG_CAN1_SCR_0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_AOPG_CAN1_SCR_0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x80000106)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                  31:31
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                      ENABLE
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_SHIFT                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_RANGE                        8:8
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_MSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_LSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_INIT_ENUM                    DONE
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_DONE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_START_PENDING                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                  0:0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0                     MK_ADDR_CONST(0x404)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SCR                         PG_AOPG_CAN1_SCR_0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SCRREG                      PMC_IMPL_SCR_PG_AOPG_CAN1_SCR_0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                        2:2
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                  1:1
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                       0:0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                     0x0
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0                 MK_ADDR_CONST(0x408)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_SECURE                  0x0
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_DUAL                    0x0
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_SCR                     PG_AOPG_CAN1_SCR_0
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_AOPG_CAN1_SCR_0
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_RANGE                     0:0
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_WOFFSET                   0x0
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0_CLAMP_ON                        MK_ENUM_CONST(1)
+
+
+// Reserved address 0x40c
+
+// Reserved address 0x410
+
+// Reserved address 0x414
+
+// Register PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0                  MK_ADDR_CONST(0x418)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SECURE                   0x0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_DUAL                     0x0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SCR                      PG_MSS_SCRATCH_SCR_0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_MSS_SCRATCH_SCR_0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x80000106)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_SHIFT                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_RANGE                      8:8
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_MSB                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_LSB                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_DONE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_START_PENDING                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0                   MK_ADDR_CONST(0x41c)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SCR                       PG_MSS_SCRATCH_SCR_0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_MSS_SCRATCH_SCR_0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0                       MK_ADDR_CONST(0x420)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_SCR                   PG_MSS_SCRATCH_SCR_0
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_MSS_SCRATCH_SCR_0
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0_CLAMP_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0                      MK_ADDR_CONST(0x424)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SCR                  PG_PCIEX8A_SCR_0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX8A_SCR_0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                    31:31
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                        ENABLE
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_SHIFT                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_RANGE                  8:8
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_MSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_LSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_WOFFSET                        0x0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_INIT_ENUM                      DONE
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_DONE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_START_PENDING                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                  2:2
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                      ON
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                    1:1
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                    0:0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                        ON
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0                       MK_ADDR_CONST(0x428)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SECURE                        0x0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_DUAL                  0x0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SCR                   PG_PCIEX8A_SCR_0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_PCIEX8A_SCR_0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                  2:2
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                      ON
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                    1:1
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                 0:0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                     ON
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0                   MK_ADDR_CONST(0x42c)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_SECURE                    0x0
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_DUAL                      0x0
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_SCR                       PG_PCIEX8A_SCR_0
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_SCRREG                    PMC_IMPL_SCR_PG_PCIEX8A_SCR_0
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_RESET_VAL                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_RANGE                       0:0
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_WOFFSET                     0x0
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                   ON
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0_CLAMP_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0                      MK_ADDR_CONST(0x430)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SCR                  PG_PCIEX4A_SCR_0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4A_SCR_0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                    31:31
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                        ENABLE
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_SHIFT                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_RANGE                  8:8
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_MSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_LSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_WOFFSET                        0x0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_INIT_ENUM                      DONE
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_DONE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_START_PENDING                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                  2:2
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                      ON
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                    1:1
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                    0:0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                        ON
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0                       MK_ADDR_CONST(0x434)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SECURE                        0x0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_DUAL                  0x0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SCR                   PG_PCIEX4A_SCR_0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_PCIEX4A_SCR_0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                  2:2
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                      ON
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                    1:1
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                 0:0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                     ON
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0                   MK_ADDR_CONST(0x438)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_SECURE                    0x0
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_DUAL                      0x0
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_SCR                       PG_PCIEX4A_SCR_0
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_SCRREG                    PMC_IMPL_SCR_PG_PCIEX4A_SCR_0
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_RESET_VAL                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_RANGE                       0:0
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_WOFFSET                     0x0
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                   ON
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0_CLAMP_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0                      MK_ADDR_CONST(0x43c)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SCR                  PG_PCIEX1A_SCR_0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX1A_SCR_0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                    31:31
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                        ENABLE
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_SHIFT                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_RANGE                  8:8
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_MSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_LSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_WOFFSET                        0x0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_INIT_ENUM                      DONE
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_DONE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_START_PENDING                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                  2:2
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                      ON
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                    1:1
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                    0:0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                        ON
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0                       MK_ADDR_CONST(0x440)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SECURE                        0x0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_DUAL                  0x0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SCR                   PG_PCIEX1A_SCR_0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_PCIEX1A_SCR_0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                  2:2
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                      ON
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                    1:1
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                 0:0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                     ON
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0                   MK_ADDR_CONST(0x444)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_SECURE                    0x0
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_DUAL                      0x0
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_SCR                       PG_PCIEX1A_SCR_0
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_SCRREG                    PMC_IMPL_SCR_PG_PCIEX1A_SCR_0
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_RESET_VAL                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_RANGE                       0:0
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_WOFFSET                     0x0
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                   ON
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0_CLAMP_ON                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x448
+
+// Reserved address 0x44c
+
+// Reserved address 0x450
+
+// Register PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0                      MK_ADDR_CONST(0x454)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SCR                  PG_PCIEX8B_SCR_0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX8B_SCR_0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                    31:31
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                        ENABLE
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_SHIFT                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_RANGE                  8:8
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_MSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_LSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_WOFFSET                        0x0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_INIT_ENUM                      DONE
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_DONE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_START_PENDING                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                  2:2
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                        0x0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                      ON
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                    1:1
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                    0:0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                        ON
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0                       MK_ADDR_CONST(0x458)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SECURE                        0x0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_DUAL                  0x0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SCR                   PG_PCIEX8B_SCR_0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_PCIEX8B_SCR_0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                  2:2
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                      ON
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                    1:1
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                 0:0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                     ON
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0                   MK_ADDR_CONST(0x45c)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_SECURE                    0x0
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_DUAL                      0x0
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_SCR                       PG_PCIEX8B_SCR_0
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_SCRREG                    PMC_IMPL_SCR_PG_PCIEX8B_SCR_0
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_RESET_VAL                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_RANGE                       0:0
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_WOFFSET                     0x0
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                   ON
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0_CLAMP_ON                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x460
+
+// Reserved address 0x464
+
+// Reserved address 0x468
+
+// Reserved address 0x46c
+
+// Reserved address 0x470
+
+// Reserved address 0x474
+
+// Register PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0                 MK_ADDR_CONST(0x478)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SECURE                  0x0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_DUAL                    0x0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SCR                     PG_DLAA_SCR_0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_DLAA_SCR_0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                       31:31
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                     0x0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                   ENABLE
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_SHIFT                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_RANGE                     8:8
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_MSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_LSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_WOFFSET                   0x0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_INIT_ENUM                 DONE
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_DONE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_START_PENDING                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                     2:2
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                   0x0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                 ON
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                       1:1
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                     0x0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                       0:0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                     0x0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                   ON
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0                  MK_ADDR_CONST(0x47c)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SECURE                   0x0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_DUAL                     0x0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SCR                      PG_DLAA_SCR_0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SCRREG                   PMC_IMPL_SCR_PG_DLAA_SCR_0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_READ_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                     2:2
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                   0x0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                 ON
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                       1:1
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                     0x0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                    0:0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                        ON
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0                      MK_ADDR_CONST(0x480)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_SECURE                       0x0
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_DUAL                         0x0
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_SCR                  PG_DLAA_SCR_0
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_DLAA_SCR_0
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_RANGE                  0:0
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_WOFFSET                        0x0
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                      ON
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0_CLAMP_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0                 MK_ADDR_CONST(0x484)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SECURE                  0x0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_DUAL                    0x0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SCR                     PG_DLAB_SCR_0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_DLAB_SCR_0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                       31:31
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                     0x0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                   ENABLE
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_SHIFT                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_RANGE                     8:8
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_MSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_LSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_WOFFSET                   0x0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_INIT_ENUM                 DONE
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_DONE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_START_PENDING                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                     2:2
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                   0x0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                 ON
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                       1:1
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                     0x0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                       0:0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                     0x0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                   ON
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0                  MK_ADDR_CONST(0x488)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SECURE                   0x0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_DUAL                     0x0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SCR                      PG_DLAB_SCR_0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SCRREG                   PMC_IMPL_SCR_PG_DLAB_SCR_0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_READ_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                     2:2
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                   0x0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                 ON
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                       1:1
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                     0x0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                   OFF
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                    0:0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                        ON
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0                      MK_ADDR_CONST(0x48c)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_SECURE                       0x0
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_DUAL                         0x0
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_SCR                  PG_DLAB_SCR_0
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_DLAB_SCR_0
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_RANGE                  0:0
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_WOFFSET                        0x0
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                      ON
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0_CLAMP_ON                     MK_ENUM_CONST(1)
+
+
+// Reserved address 0x490
+
+// Reserved address 0x494
+
+// Reserved address 0x498
+
+// Reserved address 0x49c
+
+// Reserved address 0x4a0
+
+// Reserved address 0x4a4
+
+// Reserved address 0x4a8
+
+// Reserved address 0x4ac
+
+// Reserved address 0x4b0
+
+// Reserved address 0x4b4
+
+// Reserved address 0x4b8
+
+// Reserved address 0x4bc
+
+// Register PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0                  MK_ADDR_CONST(0x4c0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SECURE                   0x0
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_DUAL                     0x0
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SCR                      PG_ISP_SCR_0
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_ISP_SCR_0
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_SHIFT                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_RANGE                      8:8
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_MSB                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_LSB                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_DONE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_START_PENDING                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  ON
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    ON
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0                   MK_ADDR_CONST(0x4c4)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SCR                       PG_ISP_SCR_0
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_ISP_SCR_0
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  ON
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 ON
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_ISP_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0                       MK_ADDR_CONST(0x4c8)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_SCR                   PG_ISP_SCR_0
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_ISP_SCR_0
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       ON
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_ISP_CLAMP_CONTROL_0_CLAMP_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x4cc)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SCR                    PG_NVDEC_SCR_0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_NVDEC_SCR_0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_RANGE                    8:8
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        ON
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  ON
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x4d0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SCR                     PG_NVDEC_SCR_0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_NVDEC_SCR_0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        ON
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       ON
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x4d4)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_SCR                         PG_NVDEC_SCR_0
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_NVDEC_SCR_0
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     ON
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0                       MK_ADDR_CONST(0x4d8)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SCR                   PG_NVJPGA_SCR_0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_NVJPGA_SCR_0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                     31:31
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                   0x0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                 ENABLE
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_SHIFT                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_RANGE                   8:8
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_MSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_LSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_WOFFSET                 0x0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_INIT_ENUM                       DONE
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_DONE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_START_PENDING                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                   2:2
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                 0x0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                       ON
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                     1:1
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                   0x0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                     0:0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                   0x0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                 ON
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0                        MK_ADDR_CONST(0x4dc)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SECURE                         0x0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_DUAL                   0x0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SCR                    PG_NVJPGA_SCR_0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_NVJPGA_SCR_0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                   2:2
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                       ON
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                     1:1
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                   0x0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                  0:0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                      ON
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0                    MK_ADDR_CONST(0x4e0)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_SECURE                     0x0
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_DUAL                       0x0
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_SCR                        PG_NVJPGA_SCR_0
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_NVJPGA_SCR_0
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_RANGE                        0:0
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_WOFFSET                      0x0
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                    ON
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0_CLAMP_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0                       MK_ADDR_CONST(0x4e4)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SCR                   PG_NVJPGB_SCR_0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_NVJPGB_SCR_0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                     31:31
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                   0x0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                 ENABLE
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_SHIFT                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_RANGE                   8:8
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_MSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_LSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_WOFFSET                 0x0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_INIT_ENUM                       DONE
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_DONE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_START_PENDING                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                   2:2
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                 0x0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                       ON
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                     1:1
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                   0x0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                     0:0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                   0x0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                 ON
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0                        MK_ADDR_CONST(0x4e8)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SECURE                         0x0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_DUAL                   0x0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SCR                    PG_NVJPGB_SCR_0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_NVJPGB_SCR_0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                   2:2
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                       ON
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                     1:1
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                   0x0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                  0:0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                      ON
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0                    MK_ADDR_CONST(0x4ec)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_SECURE                     0x0
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_DUAL                       0x0
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_SCR                        PG_NVJPGB_SCR_0
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_NVJPGB_SCR_0
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_RANGE                        0:0
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_WOFFSET                      0x0
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                    ON
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0_CLAMP_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x4f0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SCR                    PG_NVENC_SCR_0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_NVENC_SCR_0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_RANGE                    8:8
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        ON
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  ON
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x4f4)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SCR                     PG_NVENC_SCR_0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_NVENC_SCR_0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        ON
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       ON
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x4f8)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_SCR                         PG_NVENC_SCR_0
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_NVENC_SCR_0
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     ON
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0                   MK_ADDR_CONST(0x4fc)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SECURE                    0x0
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_DUAL                      0x0
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SCR                       PG_VI_SCR_0
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SCRREG                    PMC_IMPL_SCR_PG_VI_SCR_0
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_RESET_VAL                         MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_RESET_MASK                        MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_READ_MASK                         MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_WRITE_MASK                        MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                 31:31
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                   MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                   MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                       0x0
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                     ENABLE
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_SHIFT                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_RANGE                       8:8
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_MSB                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_LSB                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_WOFFSET                     0x0
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_INIT_ENUM                   DONE
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_DONE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_START_PENDING                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                       2:2
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                     0x0
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                   ON
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                 1:1
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                       0x0
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                     OFF
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                 0:0
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                       0x0
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                     ON
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_VI_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0                    MK_ADDR_CONST(0x500)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SECURE                     0x0
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_DUAL                       0x0
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SCR                        PG_VI_SCR_0
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SCRREG                     PMC_IMPL_SCR_PG_VI_SCR_0
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_READ_MASK                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                       2:2
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                     0x0
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                   ON
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                 1:1
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                       0x0
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                     OFF
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                      0:0
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                  ON
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VI_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_VI_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0                        MK_ADDR_CONST(0x504)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_SCR                    PG_VI_SCR_0
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_VI_SCR_0
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_RANGE                    0:0
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_WOFFSET                  0x0
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                        ON
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_VI_CLAMP_CONTROL_0_CLAMP_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0                     MK_ADDR_CONST(0x508)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SCR                         PG_PCIEX4BA_SCR_0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4BA_SCR_0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                   MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                   31:31
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                       ENABLE
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_SHIFT                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_RANGE                 8:8
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_MSB                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_LSB                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_INIT_ENUM                     DONE
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_DONE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_START_PENDING                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                 2:2
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                     ON
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                   1:1
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                   0:0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                       ON
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0                      MK_ADDR_CONST(0x50c)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SCR                  PG_PCIEX4BA_SCR_0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4BA_SCR_0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                 2:2
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                     ON
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                   1:1
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                        0:0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                    ON
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0                  MK_ADDR_CONST(0x510)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_SECURE                   0x0
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_DUAL                     0x0
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_SCR                      PG_PCIEX4BA_SCR_0
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_PCIEX4BA_SCR_0
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_RANGE                      0:0
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_WOFFSET                    0x0
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                  ON
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0_CLAMP_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0                     MK_ADDR_CONST(0x514)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SCR                         PG_PCIEX4BB_SCR_0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4BB_SCR_0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                   MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                   31:31
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                       ENABLE
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_SHIFT                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_RANGE                 8:8
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_MSB                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_LSB                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_INIT_ENUM                     DONE
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_DONE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_START_PENDING                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                 2:2
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                     ON
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                   1:1
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                   0:0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                       ON
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0                      MK_ADDR_CONST(0x518)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SCR                  PG_PCIEX4BB_SCR_0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4BB_SCR_0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                 2:2
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                     ON
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                   1:1
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                        0:0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                    ON
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0                  MK_ADDR_CONST(0x51c)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_SECURE                   0x0
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_DUAL                     0x0
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_SCR                      PG_PCIEX4BB_SCR_0
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_PCIEX4BB_SCR_0
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_RANGE                      0:0
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_WOFFSET                    0x0
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                  ON
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0_CLAMP_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0                     MK_ADDR_CONST(0x520)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SCR                         PG_PCIEX4CA_SCR_0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4CA_SCR_0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                   MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                   31:31
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                       ENABLE
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_SHIFT                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_RANGE                 8:8
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_MSB                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_LSB                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_INIT_ENUM                     DONE
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_DONE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_START_PENDING                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                 2:2
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                     ON
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                   1:1
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                   0:0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                       ON
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0                      MK_ADDR_CONST(0x524)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SCR                  PG_PCIEX4CA_SCR_0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4CA_SCR_0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                 2:2
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                     ON
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                   1:1
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                        0:0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                    ON
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0                  MK_ADDR_CONST(0x528)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_SECURE                   0x0
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_DUAL                     0x0
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_SCR                      PG_PCIEX4CA_SCR_0
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_PCIEX4CA_SCR_0
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_RANGE                      0:0
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_WOFFSET                    0x0
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                  ON
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0_CLAMP_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0                     MK_ADDR_CONST(0x52c)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SCR                         PG_PCIEX4CB_SCR_0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4CB_SCR_0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                   MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                   31:31
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                       ENABLE
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_SHIFT                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_RANGE                 8:8
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_MSB                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_LSB                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_INIT_ENUM                     DONE
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_DONE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_START_PENDING                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                 2:2
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                     ON
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                   1:1
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                   0:0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                       ON
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0                      MK_ADDR_CONST(0x530)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SCR                  PG_PCIEX4CB_SCR_0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4CB_SCR_0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                 2:2
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                     ON
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                   1:1
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                        0:0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                    ON
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0                  MK_ADDR_CONST(0x534)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_SECURE                   0x0
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_DUAL                     0x0
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_SCR                      PG_PCIEX4CB_SCR_0
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_PCIEX4CB_SCR_0
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_RANGE                      0:0
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_WOFFSET                    0x0
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                  ON
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0_CLAMP_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0                     MK_ADDR_CONST(0x538)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SCR                         PG_PCIEX4CC_SCR_0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4CC_SCR_0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                   MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                   31:31
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                       ENABLE
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_SHIFT                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_RANGE                 8:8
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_MSB                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_LSB                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_INIT_ENUM                     DONE
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_DONE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_START_PENDING                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                 2:2
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                     ON
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                   1:1
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                   0:0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                       ON
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0                      MK_ADDR_CONST(0x53c)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SCR                  PG_PCIEX4CC_SCR_0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4CC_SCR_0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                 2:2
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                     ON
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                   1:1
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                        0:0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                    ON
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0                  MK_ADDR_CONST(0x540)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_SECURE                   0x0
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_DUAL                     0x0
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_SCR                      PG_PCIEX4CC_SCR_0
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_PCIEX4CC_SCR_0
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_RANGE                      0:0
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_WOFFSET                    0x0
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                  ON
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0_CLAMP_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0                  MK_ADDR_CONST(0x544)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SECURE                   0x0
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_DUAL                     0x0
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SCR                      PG_PVA_SCR_0
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_PVA_SCR_0
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_SHIFT                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_RANGE                      8:8
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_MSB                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_LSB                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_DONE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_START_PENDING                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  ON
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    ON
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0                   MK_ADDR_CONST(0x548)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SCR                       PG_PVA_SCR_0
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_PVA_SCR_0
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  ON
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 ON
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_PVA_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0                       MK_ADDR_CONST(0x54c)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_SCR                   PG_PVA_SCR_0
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_PVA_SCR_0
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       ON
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_PVA_CLAMP_CONTROL_0_CLAMP_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0                  MK_ADDR_CONST(0x550)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SECURE                   0x0
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_DUAL                     0x0
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SCR                      PG_OFA_SCR_0
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_OFA_SCR_0
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                        31:31
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                    ENABLE
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_SHIFT                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_RANGE                      8:8
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_MSB                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_LSB                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_WOFFSET                    0x0
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_INIT_ENUM                  DONE
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_DONE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_START_PENDING                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                      2:2
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                  ON
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                        1:1
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                      0x0
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                        0:0
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                      0x0
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                    ON
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0                   MK_ADDR_CONST(0x554)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SCR                       PG_OFA_SCR_0
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_OFA_SCR_0
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                      2:2
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                  ON
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                        1:1
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                      0x0
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                     0:0
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                   0x0
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                 ON
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_OFA_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0                       MK_ADDR_CONST(0x558)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_SCR                   PG_OFA_SCR_0
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_OFA_SCR_0
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_RANGE                   0:0
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_WOFFSET                 0x0
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                       ON
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_OFA_CLAMP_CONTROL_0_CLAMP_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x55c)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SCR                    PG_MGBEA_SCR_0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_MGBEA_SCR_0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_RANGE                    8:8
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        ON
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  ON
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x560)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SCR                     PG_MGBEA_SCR_0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_MGBEA_SCR_0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        ON
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       ON
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x564)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_SCR                         PG_MGBEA_SCR_0
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_MGBEA_SCR_0
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     ON
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0                       MK_ADDR_CONST(0x568)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SCR                   PG_MGBEBA_SCR_0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_MGBEBA_SCR_0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                     31:31
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                   0x0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                 ENABLE
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_SHIFT                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_RANGE                   8:8
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_MSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_LSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_WOFFSET                 0x0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_INIT_ENUM                       DONE
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_DONE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_START_PENDING                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                   2:2
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                 0x0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                       ON
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                     1:1
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                   0x0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                     0:0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                   0x0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                 ON
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0                        MK_ADDR_CONST(0x56c)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SECURE                         0x0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_DUAL                   0x0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SCR                    PG_MGBEBA_SCR_0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_MGBEBA_SCR_0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                   2:2
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                       ON
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                     1:1
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                   0x0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                  0:0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                      ON
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0                    MK_ADDR_CONST(0x570)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_SECURE                     0x0
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_DUAL                       0x0
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_SCR                        PG_MGBEBA_SCR_0
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_MGBEBA_SCR_0
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_RANGE                        0:0
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_WOFFSET                      0x0
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                    ON
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0_CLAMP_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0                       MK_ADDR_CONST(0x574)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SCR                   PG_MGBEBB_SCR_0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_MGBEBB_SCR_0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                     31:31
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                   0x0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                 ENABLE
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_SHIFT                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_RANGE                   8:8
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_MSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_LSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_WOFFSET                 0x0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_INIT_ENUM                       DONE
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_DONE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_START_PENDING                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                   2:2
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                 0x0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                       ON
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                     1:1
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                   0x0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                     0:0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                   0x0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                 ON
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0                        MK_ADDR_CONST(0x578)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SECURE                         0x0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_DUAL                   0x0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SCR                    PG_MGBEBB_SCR_0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_MGBEBB_SCR_0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                   2:2
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                       ON
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                     1:1
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                   0x0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                  0:0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                      ON
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0                    MK_ADDR_CONST(0x57c)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_SECURE                     0x0
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_DUAL                       0x0
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_SCR                        PG_MGBEBB_SCR_0
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_MGBEBB_SCR_0
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_RANGE                        0:0
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_WOFFSET                      0x0
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                    ON
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0_CLAMP_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0                       MK_ADDR_CONST(0x580)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SCR                   PG_MGBEBC_SCR_0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_MGBEBC_SCR_0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                     31:31
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                   0x0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                 ENABLE
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_SHIFT                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_RANGE                   8:8
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_MSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_LSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_WOFFSET                 0x0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_INIT_ENUM                       DONE
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_DONE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_START_PENDING                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                   2:2
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                 0x0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                       ON
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                     1:1
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                   0x0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                     0:0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                   0x0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                 ON
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0                        MK_ADDR_CONST(0x584)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SECURE                         0x0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_DUAL                   0x0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SCR                    PG_MGBEBC_SCR_0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_MGBEBC_SCR_0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                   2:2
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                       ON
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                     1:1
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                   0x0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                  0:0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                      ON
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0                    MK_ADDR_CONST(0x588)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_SECURE                     0x0
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_DUAL                       0x0
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_SCR                        PG_MGBEBC_SCR_0
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_MGBEBC_SCR_0
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_RANGE                        0:0
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_WOFFSET                      0x0
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                    ON
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0_CLAMP_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x58c)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SCR                    PG_EMCAA_SCR_0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_EMCAA_SCR_0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_START_RANGE                    8:8
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        ON
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  ON
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x590)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SCR                     PG_EMCAA_SCR_0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_EMCAA_SCR_0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        ON
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       ON
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x594)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_SCR                         PG_EMCAA_SCR_0
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_EMCAA_SCR_0
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     ON
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x598)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SCR                    PG_EMCAB_SCR_0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_EMCAB_SCR_0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_START_RANGE                    8:8
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        ON
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  ON
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x59c)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SCR                     PG_EMCAB_SCR_0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_EMCAB_SCR_0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        ON
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       ON
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x5a0)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_SCR                         PG_EMCAB_SCR_0
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_EMCAB_SCR_0
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     ON
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x5a4)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SCR                    PG_EMCBA_SCR_0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_EMCBA_SCR_0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_START_RANGE                    8:8
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        ON
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  ON
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x5a8)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SCR                     PG_EMCBA_SCR_0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_EMCBA_SCR_0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        ON
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       ON
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x5ac)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_SCR                         PG_EMCBA_SCR_0
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_EMCBA_SCR_0
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     ON
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x5b0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SCR                    PG_EMCBB_SCR_0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_EMCBB_SCR_0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000005)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000105)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_START_RANGE                    8:8
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        ON
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  ON
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x5b4)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SCR                     PG_EMCBB_SCR_0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_EMCBB_SCR_0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x5)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        ON
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       ON
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x5b8)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_SCR                         PG_EMCBB_SCR_0
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_EMCBB_SCR_0
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     ON
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0                        MK_ADDR_CONST(0x5bc)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SCR                    PG_TZRAM_SCR_0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_TZRAM_SCR_0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x80000102)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                      31:31
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                  ENABLE
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_START_SHIFT                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_START_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_START_RANGE                    8:8
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_START_MSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_START_LSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_START_WOFFSET                  0x0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_START_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_START_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_START_INIT_ENUM                        DONE
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_START_DONE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_START_PENDING                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                    2:2
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                  0x0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                      1:1
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                    0x0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                      0:0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                    0x0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0                 MK_ADDR_CONST(0x5c0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SCR                     PG_TZRAM_SCR_0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_TZRAM_SCR_0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                    2:2
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                  0x0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                        OFF
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                      1:1
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                    0x0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                  OFF
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                   0:0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0                     MK_ADDR_CONST(0x5c4)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_SCR                         PG_TZRAM_SCR_0
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_TZRAM_SCR_0
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_CLAMP_RANGE                 0:0
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_CLAMP_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_CLAMP_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_CLAMP_WOFFSET                       0x0
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_CLAMP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                     OFF
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_CLAMP_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0_CLAMP_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0                       MK_ADDR_CONST(0x5c8)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SCR                   PG_DBBRAM_SCR_0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_DBBRAM_SCR_0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x80000107)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x80000106)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SHIFT)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_RANGE                     31:31
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_LSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_WOFFSET                   0x0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_INIT_ENUM                 ENABLE
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_INTER_PART_DELAY_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_SHIFT                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_SHIFT)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_RANGE                   8:8
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_MSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_LSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_WOFFSET                 0x0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_INIT_ENUM                       DONE
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_DONE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_START_PENDING                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SHIFT)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_RANGE                   2:2
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_WOFFSET                 0x0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_SLEEP_EN_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_SHIFT)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_RANGE                     1:1
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_WOFFSET                   0x0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_SRAM_RET_EN_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SHIFT)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_RANGE                     0:0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_WOFFSET                   0x0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0_LOGIC_SLEEP_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0                        MK_ADDR_CONST(0x5cc)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SECURE                         0x0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_DUAL                   0x0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SCR                    PG_DBBRAM_SCR_0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_DBBRAM_SCR_0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_RANGE                   2:2
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_WOFFSET                 0x0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_INIT_ENUM                       OFF
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_SHIFT)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_RANGE                     1:1
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_WOFFSET                   0x0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_INIT_ENUM                 OFF
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_SRAM_RET_STS_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SHIFT)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_RANGE                  0:0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_WOFFSET                        0x0
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_INIT_ENUM                      OFF
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0_LOGIC_SLEEP_STS_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0                    MK_ADDR_CONST(0x5d0)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_SECURE                     0x0
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_DUAL                       0x0
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_SCR                        PG_DBBRAM_SCR_0
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_SCRREG                     PMC_IMPL_SCR_PG_DBBRAM_SCR_0
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_SHIFT)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_RANGE                        0:0
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_WOFFSET                      0x0
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_INIT_ENUM                    OFF
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0_CLAMP_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0                  MK_ADDR_CONST(0x5d4)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_SECURE                   0x0
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_DUAL                     0x0
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_SCR                      PG_AUD_SCR_0
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_AUD_SCR_0
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_RANGE                        0:0
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                      0x0
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                        MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0                   MK_ADDR_CONST(0x5d8)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_SCR                       PG_AUD_SCR_0
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_AUD_SCR_0
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                     0:0
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                   0x0
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                     MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                     1:1
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                   0x0
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                     MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                     2:2
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                   0x0
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                     MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0                 MK_ADDR_CONST(0x5dc)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_SECURE                  0x0
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_DUAL                    0x0
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_SCR                     PG_DISP_SCR_0
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_DISP_SCR_0
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_RANGE                       0:0
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                     0x0
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                   PWRDWN
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                      MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                       MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0                  MK_ADDR_CONST(0x5e0)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_SECURE                   0x0
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DUAL                     0x0
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_SCR                      PG_DISP_SCR_0
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_SCRREG                   PMC_IMPL_SCR_PG_DISP_SCR_0
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_READ_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                    0:0
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                  0x0
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                        PWRDWN
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                   MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                    MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                    1:1
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                  0x0
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                        PWRDWN
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                   MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                    MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                    2:2
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                  0x0
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                        PWRDWN
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                   MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                    MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0                  MK_ADDR_CONST(0x5e4)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_SECURE                   0x0
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_DUAL                     0x0
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_SCR                      PG_ISP_SCR_0
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_ISP_SCR_0
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_RANGE                        0:0
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                      0x0
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                        MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0                   MK_ADDR_CONST(0x5e8)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_SCR                       PG_ISP_SCR_0
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_ISP_SCR_0
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                     0:0
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                   0x0
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                     MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                     1:1
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                   0x0
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                     MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                     2:2
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                   0x0
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                     MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0                        MK_ADDR_CONST(0x5ec)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_SCR                    PG_NVDEC_SCR_0
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_NVDEC_SCR_0
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_RANGE                      0:0
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                    0x0
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                  PWRDWN
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                     MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                      MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0                 MK_ADDR_CONST(0x5f0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_SCR                     PG_NVDEC_SCR_0
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_NVDEC_SCR_0
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                   0:0
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                   1:1
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                   2:2
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0                       MK_ADDR_CONST(0x5f4)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_SCR                   PG_NVJPGA_SCR_0
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_NVJPGA_SCR_0
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                     0:0
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                   0x0
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                     MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0                        MK_ADDR_CONST(0x5f8)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_SECURE                         0x0
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DUAL                   0x0
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_SCR                    PG_NVJPGA_SCR_0
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_NVJPGA_SCR_0
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                  0:0
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                  1:1
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                  2:2
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0                       MK_ADDR_CONST(0x5fc)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_SCR                   PG_NVJPGB_SCR_0
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_NVJPGB_SCR_0
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_RANGE                     0:0
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                   0x0
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                     MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0                        MK_ADDR_CONST(0x600)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_SECURE                         0x0
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DUAL                   0x0
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_SCR                    PG_NVJPGB_SCR_0
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_NVJPGB_SCR_0
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                  0:0
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                  1:1
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                  2:2
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0                        MK_ADDR_CONST(0x604)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_SCR                    PG_NVENC_SCR_0
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_NVENC_SCR_0
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_RANGE                      0:0
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                    0x0
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                  PWRDWN
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                     MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                      MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0                 MK_ADDR_CONST(0x608)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_SCR                     PG_NVENC_SCR_0
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_NVENC_SCR_0
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                   0:0
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                   1:1
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                   2:2
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0                   MK_ADDR_CONST(0x60c)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_SECURE                    0x0
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_DUAL                      0x0
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_SCR                       PG_VI_SCR_0
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_SCRREG                    PMC_IMPL_SCR_PG_VI_SCR_0
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_RESET_VAL                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_RANGE                 0:0
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                       0x0
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                 MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0                    MK_ADDR_CONST(0x610)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_SECURE                     0x0
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DUAL                       0x0
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_SCR                        PG_VI_SCR_0
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_SCRREG                     PMC_IMPL_SCR_PG_VI_SCR_0
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_WORD_COUNT                         0x1
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_READ_MASK                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                      0:0
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                    0x0
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                  PWRDWN
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                     MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                      MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                      1:1
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                    0x0
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                  PWRDWN
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                     MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                      MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                      2:2
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                    0x0
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                  PWRDWN
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                     MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                      MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0                  MK_ADDR_CONST(0x614)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_SECURE                   0x0
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_DUAL                     0x0
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_SCR                      PG_VIC_SCR_0
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_VIC_SCR_0
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_RANGE                        0:0
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                      0x0
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                        MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0                   MK_ADDR_CONST(0x618)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_SCR                       PG_VIC_SCR_0
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_VIC_SCR_0
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                     0:0
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                   0x0
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                     MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                     1:1
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                   0x0
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                     MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                     2:2
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                   0x0
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                     MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0                        MK_ADDR_CONST(0x61c)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_SCR                    PG_XUSBA_SCR_0
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_XUSBA_SCR_0
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                      0:0
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                    0x0
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                  PWRUP
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                     MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                      MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0                 MK_ADDR_CONST(0x620)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_SCR                     PG_XUSBA_SCR_0
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_XUSBA_SCR_0
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                   0:0
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                       PWRUP
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                   1:1
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                       PWRUP
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                   2:2
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                       PWRUP
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0                        MK_ADDR_CONST(0x624)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_SCR                    PG_XUSBB_SCR_0
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_XUSBB_SCR_0
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_RANGE                      0:0
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                    0x0
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                  PWRUP
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                     MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                      MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0                 MK_ADDR_CONST(0x628)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_SCR                     PG_XUSBB_SCR_0
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_XUSBB_SCR_0
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                   0:0
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                       PWRUP
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                   1:1
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                       PWRUP
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                   2:2
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                       PWRUP
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0                        MK_ADDR_CONST(0x62c)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_SCR                    PG_XUSBC_SCR_0
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_XUSBC_SCR_0
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_RANGE                      0:0
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                    0x0
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                  PWRUP
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                     MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                      MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0                 MK_ADDR_CONST(0x630)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_SCR                     PG_XUSBC_SCR_0
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_XUSBC_SCR_0
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                   0:0
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                       PWRUP
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                   1:1
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                       PWRUP
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                   2:2
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                       PWRUP
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0                      MK_ADDR_CONST(0x634)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_SCR                  PG_PCIEX8A_SCR_0
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX8A_SCR_0
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_RANGE                    0:0
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                        PWRDWN
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                   MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                    MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0                       MK_ADDR_CONST(0x638)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_SECURE                        0x0
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DUAL                  0x0
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_SCR                   PG_PCIEX8A_SCR_0
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_PCIEX8A_SCR_0
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                 0:0
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                 1:1
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                 2:2
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0                      MK_ADDR_CONST(0x63c)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_SCR                  PG_PCIEX4A_SCR_0
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4A_SCR_0
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_RANGE                    0:0
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                        PWRDWN
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                   MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                    MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0                       MK_ADDR_CONST(0x640)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_SECURE                        0x0
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DUAL                  0x0
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_SCR                   PG_PCIEX4A_SCR_0
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_PCIEX4A_SCR_0
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                 0:0
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                 1:1
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                 2:2
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0                     MK_ADDR_CONST(0x644)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_SCR                         PG_PCIEX4BA_SCR_0
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4BA_SCR_0
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                   0:0
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                   MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0                      MK_ADDR_CONST(0x648)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_SCR                  PG_PCIEX4BA_SCR_0
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4BA_SCR_0
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                        0:0
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                        MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                        1:1
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                        MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                        2:2
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                        MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0                     MK_ADDR_CONST(0x64c)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_SCR                         PG_PCIEX4BB_SCR_0
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4BB_SCR_0
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_RANGE                   0:0
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                   MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0                      MK_ADDR_CONST(0x650)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_SCR                  PG_PCIEX4BB_SCR_0
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4BB_SCR_0
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                        0:0
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                        MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                        1:1
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                        MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                        2:2
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                        MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0                     MK_ADDR_CONST(0x654)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_SCR                         PG_PCIEX4CA_SCR_0
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4CA_SCR_0
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                   0:0
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                   MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0                      MK_ADDR_CONST(0x658)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_SCR                  PG_PCIEX4CA_SCR_0
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4CA_SCR_0
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                        0:0
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                        MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                        1:1
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                        MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                        2:2
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                        MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0                     MK_ADDR_CONST(0x65c)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_SCR                         PG_PCIEX4CB_SCR_0
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4CB_SCR_0
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_RANGE                   0:0
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                   MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0                      MK_ADDR_CONST(0x660)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_SCR                  PG_PCIEX4CB_SCR_0
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4CB_SCR_0
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                        0:0
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                        MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                        1:1
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                        MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                        2:2
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                        MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0                     MK_ADDR_CONST(0x664)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_SECURE                      0x0
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_DUAL                        0x0
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_SCR                         PG_PCIEX4CC_SCR_0
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_SCRREG                      PMC_IMPL_SCR_PG_PCIEX4CC_SCR_0
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_RESET_VAL                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_RANGE                   0:0
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                 0x0
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                   MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0                      MK_ADDR_CONST(0x668)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_SCR                  PG_PCIEX4CC_SCR_0
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX4CC_SCR_0
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                        0:0
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                        MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                        1:1
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                        MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                        2:2
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                      0x0
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                        MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0                      MK_ADDR_CONST(0x66c)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_SCR                  PG_PCIEX1A_SCR_0
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX1A_SCR_0
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_RANGE                    0:0
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                        PWRDWN
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                   MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                    MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0                       MK_ADDR_CONST(0x670)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_SECURE                        0x0
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DUAL                  0x0
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_SCR                   PG_PCIEX1A_SCR_0
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_PCIEX1A_SCR_0
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                 0:0
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                 1:1
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                 2:2
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0                      MK_ADDR_CONST(0x674)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_SECURE                       0x0
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_DUAL                         0x0
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_SCR                  PG_PCIEX8B_SCR_0
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_PCIEX8B_SCR_0
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_RANGE                    0:0
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                  0x0
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                        PWRDWN
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                   MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                    MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0                       MK_ADDR_CONST(0x678)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_SECURE                        0x0
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DUAL                  0x0
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_SCR                   PG_PCIEX8B_SCR_0
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_PCIEX8B_SCR_0
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                 0:0
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                 1:1
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                 2:2
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0                  MK_ADDR_CONST(0x67c)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_SECURE                   0x0
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_DUAL                     0x0
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_SCR                      PG_PVA_SCR_0
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_PVA_SCR_0
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                        0:0
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                      0x0
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                        MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0                   MK_ADDR_CONST(0x680)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_SCR                       PG_PVA_SCR_0
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_PVA_SCR_0
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                     0:0
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                   0x0
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                     MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                     1:1
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                   0x0
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                     MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                     2:2
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                   0x0
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                     MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0                 MK_ADDR_CONST(0x684)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_SECURE                  0x0
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_DUAL                    0x0
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_SCR                     PG_DLAA_SCR_0
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_DLAA_SCR_0
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                       0:0
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                     0x0
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                   PWRDWN
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                      MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                       MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0                  MK_ADDR_CONST(0x688)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_SECURE                   0x0
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DUAL                     0x0
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_SCR                      PG_DLAA_SCR_0
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_SCRREG                   PMC_IMPL_SCR_PG_DLAA_SCR_0
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_READ_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                    0:0
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                  0x0
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                        PWRDWN
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                   MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                    MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                    1:1
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                  0x0
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                        PWRDWN
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                   MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                    MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                    2:2
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                  0x0
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                        PWRDWN
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                   MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                    MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0                 MK_ADDR_CONST(0x68c)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_SECURE                  0x0
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_DUAL                    0x0
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_SCR                     PG_DLAB_SCR_0
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_SCRREG                  PMC_IMPL_SCR_PG_DLAB_SCR_0
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_RESET_VAL                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_RANGE                       0:0
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                     0x0
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                   PWRDWN
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                      MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                       MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0                  MK_ADDR_CONST(0x690)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_SECURE                   0x0
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DUAL                     0x0
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_SCR                      PG_DLAB_SCR_0
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_SCRREG                   PMC_IMPL_SCR_PG_DLAB_SCR_0
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_READ_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                    0:0
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                  0x0
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                        PWRDWN
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                   MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                    MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                    1:1
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                  0x0
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                        PWRDWN
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                   MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                    MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                    2:2
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                  0x0
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                        PWRDWN
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                   MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                    MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0                  MK_ADDR_CONST(0x694)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_SECURE                   0x0
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_DUAL                     0x0
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_SCR                      PG_OFA_SCR_0
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_SCRREG                   PMC_IMPL_SCR_PG_OFA_SCR_0
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_RESET_VAL                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                        0:0
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                      0x0
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                    PWRDWN
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                       MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                        MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0                   MK_ADDR_CONST(0x698)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_SCR                       PG_OFA_SCR_0
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_SCRREG                    PMC_IMPL_SCR_PG_OFA_SCR_0
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_READ_MASK                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                     0:0
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                   0x0
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                     MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                     1:1
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                   0x0
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                     MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                     2:2
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                   0x0
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                     MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0                        MK_ADDR_CONST(0x69c)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_SCR                    PG_MGBEA_SCR_0
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_MGBEA_SCR_0
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                      0:0
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                    0x0
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                  PWRDWN
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                     MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                      MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0                 MK_ADDR_CONST(0x6a0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_SCR                     PG_MGBEA_SCR_0
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_MGBEA_SCR_0
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                   0:0
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                   1:1
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                   2:2
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0                       MK_ADDR_CONST(0x6a4)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_SCR                   PG_MGBEBA_SCR_0
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_MGBEBA_SCR_0
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                     0:0
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                   0x0
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                     MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0                        MK_ADDR_CONST(0x6a8)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_SECURE                         0x0
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DUAL                   0x0
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_SCR                    PG_MGBEBA_SCR_0
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_MGBEBA_SCR_0
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                  0:0
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                  1:1
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                  2:2
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0                       MK_ADDR_CONST(0x6ac)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_SCR                   PG_MGBEBB_SCR_0
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_MGBEBB_SCR_0
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_RANGE                     0:0
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                   0x0
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                     MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0                        MK_ADDR_CONST(0x6b0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_SECURE                         0x0
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DUAL                   0x0
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_SCR                    PG_MGBEBB_SCR_0
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_MGBEBB_SCR_0
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                  0:0
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                  1:1
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                  2:2
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0                       MK_ADDR_CONST(0x6b4)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_SCR                   PG_MGBEBC_SCR_0
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_MGBEBC_SCR_0
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_RANGE                     0:0
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                   0x0
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                     MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0                        MK_ADDR_CONST(0x6b8)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_SECURE                         0x0
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DUAL                   0x0
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_SCR                    PG_MGBEBC_SCR_0
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_MGBEBC_SCR_0
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                  0:0
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                  1:1
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                  2:2
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0                        MK_ADDR_CONST(0x6bc)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_SCR                    PG_EMCAA_SCR_0
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_EMCAA_SCR_0
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                      0:0
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                  PWRDWN
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                     MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                      MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0                 MK_ADDR_CONST(0x6c0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_SCR                     PG_EMCAA_SCR_0
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_EMCAA_SCR_0
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                   0:0
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                   1:1
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                   2:2
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0                        MK_ADDR_CONST(0x6c4)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_SCR                    PG_EMCAB_SCR_0
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_EMCAB_SCR_0
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_REQ_RANGE                      0:0
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_REQ_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_REQ_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                  PWRDWN
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                     MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                      MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0                 MK_ADDR_CONST(0x6c8)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_SCR                     PG_EMCAB_SCR_0
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_EMCAB_SCR_0
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                   0:0
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                   1:1
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                   2:2
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0                        MK_ADDR_CONST(0x6cc)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_SCR                    PG_EMCBA_SCR_0
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_EMCBA_SCR_0
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_REQ_RANGE                      0:0
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_REQ_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_REQ_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                  PWRDWN
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                     MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                      MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0                 MK_ADDR_CONST(0x6d0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_SCR                     PG_EMCBA_SCR_0
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_EMCBA_SCR_0
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                   0:0
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                   1:1
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                   2:2
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0                        MK_ADDR_CONST(0x6d4)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_SECURE                         0x0
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_DUAL                   0x0
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_SCR                    PG_EMCBB_SCR_0
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_SCRREG                         PMC_IMPL_SCR_PG_EMCBB_SCR_0
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_RESET_VAL                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_REQ_RANGE                      0:0
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_REQ_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_REQ_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                    0x0
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                  PWRDWN
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                     MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                      MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0                 MK_ADDR_CONST(0x6d8)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_SCR                     PG_EMCBB_SCR_0
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_SCRREG                  PMC_IMPL_SCR_PG_EMCBB_SCR_0
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                   0:0
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                   1:1
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                   2:2
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                 0x0
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                       PWRDWN
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                  MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                   MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_SW_OVERRIDE_CTRL_1_0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0                   MK_ADDR_CONST(0x6dc)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_SECURE                    0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_DUAL                      0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_SCR                       PG_OVERRIDE_SCR_0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_SCRREG                    PMC_IMPL_SCR_PG_OVERRIDE_SCR_0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_WORD_COUNT                        0x1
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_RANGE                   0:0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_WOFFSET                 0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_INIT_ENUM                       DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_ENABLE                  MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_RET_DISABLE                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_RANGE                 2:1
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_WOFFSET                       0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM0_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_SHIFT                        MK_SHIFT_CONST(3)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_RANGE                        3:3
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_MSB                  MK_SHIFT_CONST(3)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_LSB                  MK_SHIFT_CONST(3)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_WOFFSET                      0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_INIT_ENUM                    DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_ENABLE                       MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM0_DISABLE                      MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_SHIFT                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_RANGE                   4:4
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_MSB                     MK_SHIFT_CONST(4)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_LSB                     MK_SHIFT_CONST(4)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_WOFFSET                 0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_INIT_ENUM                       DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_ENABLE                  MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_RET_DISABLE                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_SHIFT                 MK_SHIFT_CONST(5)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_RANGE                 6:5
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_MSB                   MK_SHIFT_CONST(6)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_LSB                   MK_SHIFT_CONST(5)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_WOFFSET                       0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM1_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_SHIFT                        MK_SHIFT_CONST(7)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_RANGE                        7:7
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_MSB                  MK_SHIFT_CONST(7)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_LSB                  MK_SHIFT_CONST(7)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_WOFFSET                      0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_INIT_ENUM                    DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_ENABLE                       MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM1_DISABLE                      MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_SHIFT                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_RANGE                   8:8
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_MSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_LSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_WOFFSET                 0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_INIT_ENUM                       DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_ENABLE                  MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_RET_DISABLE                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_SHIFT                 MK_SHIFT_CONST(9)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_RANGE                 10:9
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_MSB                   MK_SHIFT_CONST(10)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_LSB                   MK_SHIFT_CONST(9)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_WOFFSET                       0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM2_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_SHIFT                        MK_SHIFT_CONST(11)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_RANGE                        11:11
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_MSB                  MK_SHIFT_CONST(11)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_LSB                  MK_SHIFT_CONST(11)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_WOFFSET                      0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_INIT_ENUM                    DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_ENABLE                       MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM2_DISABLE                      MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_SHIFT                   MK_SHIFT_CONST(12)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_RANGE                   12:12
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_MSB                     MK_SHIFT_CONST(12)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_LSB                     MK_SHIFT_CONST(12)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_WOFFSET                 0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_INIT_ENUM                       DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_ENABLE                  MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_RET_DISABLE                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_SHIFT                 MK_SHIFT_CONST(13)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_RANGE                 14:13
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_MSB                   MK_SHIFT_CONST(14)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_LSB                   MK_SHIFT_CONST(13)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_WOFFSET                       0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM3_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_SHIFT                        MK_SHIFT_CONST(15)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_RANGE                        15:15
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_MSB                  MK_SHIFT_CONST(15)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_LSB                  MK_SHIFT_CONST(15)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_WOFFSET                      0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_INIT_ENUM                    DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_ENABLE                       MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM3_DISABLE                      MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_SHIFT                   MK_SHIFT_CONST(16)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_RANGE                   16:16
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_MSB                     MK_SHIFT_CONST(16)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_LSB                     MK_SHIFT_CONST(16)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_WOFFSET                 0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_INIT_ENUM                       DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_ENABLE                  MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_RET_DISABLE                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_SHIFT                 MK_SHIFT_CONST(17)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_RANGE                 18:17
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_MSB                   MK_SHIFT_CONST(18)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_LSB                   MK_SHIFT_CONST(17)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_WOFFSET                       0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM4_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_SHIFT                        MK_SHIFT_CONST(19)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_RANGE                        19:19
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_MSB                  MK_SHIFT_CONST(19)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_LSB                  MK_SHIFT_CONST(19)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_WOFFSET                      0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_INIT_ENUM                    DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_ENABLE                       MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM4_DISABLE                      MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_SHIFT                   MK_SHIFT_CONST(20)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_RANGE                   20:20
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_MSB                     MK_SHIFT_CONST(20)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_LSB                     MK_SHIFT_CONST(20)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_WOFFSET                 0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_INIT_ENUM                       DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_ENABLE                  MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_RET_DISABLE                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_SHIFT                 MK_SHIFT_CONST(21)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_RANGE                 22:21
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_MSB                   MK_SHIFT_CONST(22)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_LSB                   MK_SHIFT_CONST(21)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_WOFFSET                       0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM5_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_SHIFT                        MK_SHIFT_CONST(23)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_RANGE                        23:23
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_MSB                  MK_SHIFT_CONST(23)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_LSB                  MK_SHIFT_CONST(23)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_WOFFSET                      0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_INIT_ENUM                    DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_ENABLE                       MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM5_DISABLE                      MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_SHIFT                   MK_SHIFT_CONST(24)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_RANGE                   24:24
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_MSB                     MK_SHIFT_CONST(24)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_LSB                     MK_SHIFT_CONST(24)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_WOFFSET                 0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_INIT_ENUM                       DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_ENABLE                  MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_RET_DISABLE                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_SHIFT                 MK_SHIFT_CONST(25)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_RANGE                 26:25
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_MSB                   MK_SHIFT_CONST(26)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_LSB                   MK_SHIFT_CONST(25)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_WOFFSET                       0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM6_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_SHIFT                        MK_SHIFT_CONST(27)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_RANGE                        27:27
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_MSB                  MK_SHIFT_CONST(27)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_LSB                  MK_SHIFT_CONST(27)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_WOFFSET                      0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_INIT_ENUM                    DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_ENABLE                       MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM6_DISABLE                      MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_SHIFT                   MK_SHIFT_CONST(28)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_RANGE                   28:28
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_MSB                     MK_SHIFT_CONST(28)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_LSB                     MK_SHIFT_CONST(28)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_WOFFSET                 0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_INIT_ENUM                       DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_ENABLE                  MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_RET_DISABLE                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_SHIFT                 MK_SHIFT_CONST(29)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_RANGE                 30:29
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_MSB                   MK_SHIFT_CONST(30)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_LSB                   MK_SHIFT_CONST(29)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_WOFFSET                       0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_VAL_AOPG_TCM7_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_SHIFT                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_RANGE                        31:31
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_MSB                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_LSB                  MK_SHIFT_CONST(31)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_WOFFSET                      0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_INIT_ENUM                    DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_ENABLE                       MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_1_0_EN_AOPG_TCM7_DISABLE                      MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_SW_OVERRIDE_CTRL_2_0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0                   MK_ADDR_CONST(0x6e0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_SECURE                    0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_DUAL                      0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_SCR                       PG_OVERRIDE_SCR_0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_SCRREG                    PMC_IMPL_SCR_PG_OVERRIDE_SCR_0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_WORD_COUNT                        0x1
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_RESET_MASK                        MK_MASK_CONST(0x1fffff)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_READ_MASK                         MK_MASK_CONST(0x1fffff)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_WRITE_MASK                        MK_MASK_CONST(0x1fffff)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_RANGE                  0:0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_WOFFSET                        0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_INIT_ENUM                      DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_ENABLE                 MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_RET_DISABLE                        MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_FIELD                        MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_RANGE                        2:1
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_WOFFSET                      0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CACHE_SLEEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_SHIFT                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_RANGE                       3:3
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_MSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_LSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_WOFFSET                     0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_INIT_ENUM                   DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_ENABLE                      MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CACHE_DISABLE                     MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_SHIFT                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_RANGE                   4:4
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_MSB                     MK_SHIFT_CONST(4)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_LSB                     MK_SHIFT_CONST(4)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_WOFFSET                 0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_INIT_ENUM                       DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_ENABLE                  MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_RET_DISABLE                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_SHIFT                 MK_SHIFT_CONST(5)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_RANGE                 6:5
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_MSB                   MK_SHIFT_CONST(6)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_LSB                   MK_SHIFT_CONST(5)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_WOFFSET                       0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN0_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_SHIFT                        MK_SHIFT_CONST(7)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_RANGE                        7:7
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_MSB                  MK_SHIFT_CONST(7)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_LSB                  MK_SHIFT_CONST(7)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_WOFFSET                      0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_INIT_ENUM                    DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_ENABLE                       MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN0_DISABLE                      MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_SHIFT                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_RANGE                   8:8
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_MSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_LSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_WOFFSET                 0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_INIT_ENUM                       DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_ENABLE                  MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_RET_DISABLE                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_SHIFT                 MK_SHIFT_CONST(9)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_RANGE                 10:9
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_MSB                   MK_SHIFT_CONST(10)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_LSB                   MK_SHIFT_CONST(9)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_WOFFSET                       0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_AOPG_CAN1_SLEEP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_SHIFT                        MK_SHIFT_CONST(11)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_RANGE                        11:11
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_MSB                  MK_SHIFT_CONST(11)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_LSB                  MK_SHIFT_CONST(11)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_WOFFSET                      0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_INIT_ENUM                    DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_ENABLE                       MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_AOPG_CAN1_DISABLE                      MK_ENUM_CONST(0)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_SHIFT                     MK_SHIFT_CONST(12)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_FIELD                     MK_FIELD_CONST(0xff, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_RANGE                     19:12
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_MSB                       MK_SHIFT_CONST(19)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_LSB                       MK_SHIFT_CONST(12)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_WOFFSET                   0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_VAL_COMMON_ZONE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_SHIFT                      MK_SHIFT_CONST(20)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_SHIFT)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_RANGE                      20:20
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_MSB                        MK_SHIFT_CONST(20)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_LSB                        MK_SHIFT_CONST(20)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_WOFFSET                    0x0
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_INIT_ENUM                  DISABLE
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_ENABLE                     MK_ENUM_CONST(1)
+#define PMC_IMPL_SW_OVERRIDE_CTRL_2_0_EN_COMMON_ZONE_DISABLE                    MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_MISC_CTRL_0
+#define PMC_IMPL_MISC_CTRL_0                    MK_ADDR_CONST(0x6e4)
+#define PMC_IMPL_MISC_CTRL_0_SECURE                     0x0
+#define PMC_IMPL_MISC_CTRL_0_DUAL                       0x0
+#define PMC_IMPL_MISC_CTRL_0_SCR                        PG_MISC_SCR_0
+#define PMC_IMPL_MISC_CTRL_0_SCRREG                     PMC_IMPL_SCR_PG_MISC_SCR_0
+#define PMC_IMPL_MISC_CTRL_0_WORD_COUNT                         0x1
+#define PMC_IMPL_MISC_CTRL_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_MISC_CTRL_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_MISC_CTRL_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_MISC_CTRL_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_MISC_CTRL_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_MISC_CTRL_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_SHIFT)
+#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_RANGE                      0:0
+#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_WOFFSET                    0x0
+#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_INIT_ENUM                  DISABLE
+#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_ENABLE                     MK_ENUM_CONST(1)
+#define PMC_IMPL_MISC_CTRL_0_HW_AOPG_ALLRAMS_DISABLE                    MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0                      MK_ADDR_CONST(0x6e8)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_SECURE                       0x0
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_DUAL                         0x0
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_SCR                  PG_GPURAIL_SCR_0
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_GPURAIL_SCR_0
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_REQ_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_REQ_RANGE                    0:0
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_REQ_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_REQ_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                  0x0
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                        PWRDWN
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                   MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                    MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0                       MK_ADDR_CONST(0x6ec)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_SECURE                        0x0
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_DUAL                  0x0
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_SCR                   PG_GPURAIL_SCR_0
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_GPURAIL_SCR_0
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                 0:0
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                 1:1
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                 2:2
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0                       MK_ADDR_CONST(0x6f0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_SECURE                        0x0
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_DUAL                  0x0
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_SCR                   PG_CVRAIL_SCR_0
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_SCRREG                        PMC_IMPL_SCR_PG_CVRAIL_SCR_0
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_RESET_VAL                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_REQ_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_REQ_RANGE                     0:0
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_REQ_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_REQ_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                   0x0
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                 PWRDWN
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                    MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                     MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0                        MK_ADDR_CONST(0x6f4)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_SECURE                         0x0
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_DUAL                   0x0
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_SCR                    PG_CVRAIL_SCR_0
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_SCRREG                         PMC_IMPL_SCR_PG_CVRAIL_SCR_0
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_WORD_COUNT                     0x1
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_RESET_VAL                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_RESET_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_READ_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                  0:0
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                  1:1
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                  2:2
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                        0x0
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                      PWRDWN
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                 MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                  MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0                      MK_ADDR_CONST(0x6f8)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_SECURE                       0x0
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_DUAL                         0x0
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_SCR                  PG_FSIRAIL_SCR_0
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_SCRREG                       PMC_IMPL_SCR_PG_FSIRAIL_SCR_0
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_WORD_COUNT                   0x1
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_REQ_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_REQ_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_REQ_SHIFT)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_REQ_RANGE                    0:0
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_REQ_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_REQ_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_REQ_WOFFSET                  0x0
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_REQ_INIT_ENUM                        PWRDWN
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_REQ_PWRDWN                   MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0_REQ_PWRUP                    MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0                       MK_ADDR_CONST(0x6fc)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_SECURE                        0x0
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_DUAL                  0x0
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_SCR                   PG_FSIRAIL_SCR_0
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_SCRREG                        PMC_IMPL_SCR_PG_FSIRAIL_SCR_0
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_WORD_COUNT                    0x1
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_SHIFT)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_RANGE                 0:0
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_CBB_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_SHIFT)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_RANGE                 1:1
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_DBB_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_SHIFT)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_RANGE                 2:2
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_WOFFSET                       0x0
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_INIT_ENUM                     PWRDWN
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRDWN                        MK_ENUM_CONST(1)
+#define PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0_H1X_ACK_PWRUP                 MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_PMC2LIC_INTR_STATUS_0
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0                  MK_ADDR_CONST(0x800)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_SECURE                   0x0
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_DUAL                     0x0
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_SCR                      CNTRL_SCR_0
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_SCRREG                   PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x3)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_READ_MASK                        MK_MASK_CONST(0x3)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x3)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SHIFT)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_RANGE                     1:1
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_WOFFSET                   0x0
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_SHIFT)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_RANGE                     0:0
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_WOFFSET                   0x0
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_STATUS_0_UNSUPPORTED_PG_REQUEST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_PMC2LIC_INTR_ENABLE_0
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0                  MK_ADDR_CONST(0x804)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_SECURE                   0x0
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_DUAL                     0x0
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_SCR                      CNTRL_SCR_0
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_SCRREG                   PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_WORD_COUNT                       0x1
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_RESET_MASK                       MK_MASK_CONST(0x3)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_READ_MASK                        MK_MASK_CONST(0x3)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_WRITE_MASK                       MK_MASK_CONST(0x3)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SHIFT)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_RANGE                     1:1
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_WOFFSET                   0x0
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_INIT_ENUM                 DISABLE
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_ILLEGAL_SRAM_LOGIC_POWER_STATE_ENABLE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_SHIFT)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_RANGE                     0:0
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_WOFFSET                   0x0
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_INIT_ENUM                 DISABLE
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_PMC2LIC_INTR_ENABLE_0_UNSUPPORTED_PG_REQUEST_ENABLE                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_AOVC_LOCK_CNTRL_0
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0                      MK_ADDR_CONST(0x808)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SECURE                       0x0
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_DUAL                         0x0
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SCR                  AOVC_LOCK_SCR_0
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SCRREG                       PMC_IMPL_SCR_AOVC_LOCK_SCR_0
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_WORD_COUNT                   0x1
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RESET_MASK                   MK_MASK_CONST(0x71)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_READ_MASK                    MK_MASK_CONST(0x71)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_WRITE_MASK                   MK_MASK_CONST(0x71)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_SHIFT                    MK_SHIFT_CONST(6)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_SHIFT)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_RANGE                    6:6
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_MSB                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_LSB                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_WOFFSET                  0x0
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_SHIFT                 MK_SHIFT_CONST(4)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_FIELD                 MK_FIELD_CONST(0x3, PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_SHIFT)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_RANGE                 5:4
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_MSB                   MK_SHIFT_CONST(5)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_LSB                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_WOFFSET                       0x0
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_DEFAULT_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_INIT_ENUM                     FREE
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_FREE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_AOVC                  MK_ENUM_CONST(1)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_APB_PWR_I2C                   MK_ENUM_CONST(2)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_SW_LOCK_REQ_ID_ILLEGAL                       MK_ENUM_CONST(3)
+
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_SHIFT)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_RANGE                        0:0
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_WOFFSET                      0x0
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_CNTRL_0_RELEASE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_AOVC_LOCK_ID_STATUS_0
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0                  MK_ADDR_CONST(0x80c)
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_SECURE                   0x0
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DUAL                     0x0
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_SCR                      AOVC_LOCK_SCR_0
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_SCRREG                   PMC_IMPL_SCR_AOVC_LOCK_SCR_0
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_WORD_COUNT                       0x1
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_READ_MASK                        MK_MASK_CONST(0x3)
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_FIELD                       MK_FIELD_CONST(0x3, PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_SHIFT)
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_RANGE                       1:0
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_MSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_WOFFSET                     0x0
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_AOVC_LOCK_ID_STATUS_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_TEST_CLK_MUX_SEL_0
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0                     MK_ADDR_CONST(0x810)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SECURE                      0x0
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_DUAL                        0x0
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SCR                         TEST_CLK_MUX_SCR_0
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SCRREG                      PMC_IMPL_SCR_TEST_CLK_MUX_SCR_0
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_WORD_COUNT                  0x1
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_SHIFT)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_RANGE                   0:0
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_WOFFSET                 0x0
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_INIT_ENUM                       DISABLE
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_DISABLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_TEST_CLK_MUX_SEL_0_SEL_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Reserved address 0x814
+
+// Register PMC_IMPL_SC7_FSM_STATUS_0
+#define PMC_IMPL_SC7_FSM_STATUS_0                       MK_ADDR_CONST(0x818)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SECURE                        0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_DUAL                  0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SCR                   0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SCRREG                        0
+#define PMC_IMPL_SC7_FSM_STATUS_0_WORD_COUNT                    0x1
+#define PMC_IMPL_SC7_FSM_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_RESET_MASK                    MK_MASK_CONST(0x7ffff)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_READ_MASK                     MK_MASK_CONST(0x7ffff)
+#define PMC_IMPL_SC7_FSM_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_RANGE                        0:0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_WOFFSET                      0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_INIT_ENUM                    TRUE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_FALSE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_IDLE_TRUE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_RANGE                        1:1
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_WOFFSET                      0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_INIT_ENUM                    FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_FALSE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SLEEP_TRUE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_RANGE                  2:2
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_WOFFSET                        0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_INIT_ENUM                      FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_FALSE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_SEL_TRUE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_SHIFT                    MK_SHIFT_CONST(3)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_RANGE                    3:3
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_MSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_LSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_WOFFSET                  0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_INIT_ENUM                        FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_FALSE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ASSERT_E_TRUE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_SHIFT                 MK_SHIFT_CONST(4)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_RANGE                 4:4
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_MSB                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_LSB                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_WOFFSET                       0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_INIT_ENUM                     FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_FALSE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_EARLY_CLAMP_TRUE                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_SHIFT                  MK_SHIFT_CONST(5)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_RANGE                  5:5
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_MSB                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_LSB                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_WOFFSET                        0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_INIT_ENUM                      FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_FALSE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_MAIN_CLAMP_TRUE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_SHIFT                     MK_SHIFT_CONST(6)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_RANGE                     6:6
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_MSB                       MK_SHIFT_CONST(6)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_LSB                       MK_SHIFT_CONST(6)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_WOFFSET                   0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_INIT_ENUM                 FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_FALSE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_OFF_TRUE                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_SHIFT                  MK_SHIFT_CONST(7)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_RANGE                  7:7
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_MSB                    MK_SHIFT_CONST(7)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_LSB                    MK_SHIFT_CONST(7)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_WOFFSET                        0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_INIT_ENUM                      FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_FALSE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOPG_TRUE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_SHIFT                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_RANGE                     8:8
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_MSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_LSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_WOFFSET                   0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_INIT_ENUM                 FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_FALSE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_OFF_TRUE                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_SHIFT                        MK_SHIFT_CONST(9)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_RANGE                        9:9
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_MSB                  MK_SHIFT_CONST(9)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_LSB                  MK_SHIFT_CONST(9)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_WOFFSET                      0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_INIT_ENUM                    FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_FALSE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_FOR_RET_TRUE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_SHIFT                      MK_SHIFT_CONST(10)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_RANGE                      10:10
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_MSB                        MK_SHIFT_CONST(10)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_LSB                        MK_SHIFT_CONST(10)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_WOFFSET                    0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_INIT_ENUM                  FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_FALSE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_OSC_ON_TRUE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_SHIFT                 MK_SHIFT_CONST(11)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_RANGE                 11:11
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_MSB                   MK_SHIFT_CONST(11)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_LSB                   MK_SHIFT_CONST(11)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_WOFFSET                       0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_INIT_ENUM                     FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_FALSE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_ALLOW_AOUPG_TRUE                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_SHIFT                      MK_SHIFT_CONST(12)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_RANGE                      12:12
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_MSB                        MK_SHIFT_CONST(12)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_LSB                        MK_SHIFT_CONST(12)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_WOFFSET                    0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_INIT_ENUM                  FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_FALSE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_PWR_ON_TRUE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_SHIFT                        MK_SHIFT_CONST(13)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_RANGE                        13:13
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_MSB                  MK_SHIFT_CONST(13)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_LSB                  MK_SHIFT_CONST(13)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_WOFFSET                      0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_INIT_ENUM                    FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_FALSE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_CLAMP_TRUE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_SHIFT                    MK_SHIFT_CONST(14)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_RANGE                    14:14
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_MSB                      MK_SHIFT_CONST(14)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_LSB                      MK_SHIFT_CONST(14)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_WOFFSET                  0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_INIT_ENUM                        FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_FALSE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_E_TRUE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_SHIFT                  MK_SHIFT_CONST(15)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_RANGE                  15:15
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_MSB                    MK_SHIFT_CONST(15)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_LSB                    MK_SHIFT_CONST(15)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_WOFFSET                        0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_INIT_ENUM                      FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_FALSE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SEL_TRUE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_SHIFT                        MK_SHIFT_CONST(16)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_RANGE                        16:16
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_MSB                  MK_SHIFT_CONST(16)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_LSB                  MK_SHIFT_CONST(16)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_WOFFSET                      0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_INIT_ENUM                    FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_FALSE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_RESET_TRUE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_SHIFT                        MK_SHIFT_CONST(17)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_RANGE                        17:17
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_MSB                  MK_SHIFT_CONST(17)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_LSB                  MK_SHIFT_CONST(17)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_WOFFSET                      0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_INIT_ENUM                    FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_FALSE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_REMOVE_SLEEP_TRUE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_SHIFT                        MK_SHIFT_CONST(18)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_SHIFT)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_RANGE                        18:18
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_MSB                  MK_SHIFT_CONST(18)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_LSB                  MK_SHIFT_CONST(18)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_WOFFSET                      0x0
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_INIT_ENUM                    FALSE
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_FALSE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_SC7_FSM_STATUS_0_SC7_WAIT_DPD_DIS_TRUE                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_RAMDUMP_FIQ_EXIT_0
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0                     MK_ADDR_CONST(0x81c)
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_SECURE                      0x0
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_DUAL                        0x0
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_SCR                         RAMDUMP_COM_SCR_0
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_SCRREG                      PMC_IMPL_SCR_RAMDUMP_COM_SCR_0
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_WORD_COUNT                  0x1
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT)
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_RANGE                    0:0
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_WOFFSET                  0x0
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_FIQ_EXIT_0_PVA0_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0                 MK_ADDR_CONST(0x820)
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SECURE                  0x0
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_DUAL                    0x0
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SCR                     RAMDUMP_COM_SCR_0
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SCRREG                  PMC_IMPL_SCR_RAMDUMP_COM_SCR_0
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_WORD_COUNT                      0x1
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_READ_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT)
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_RANGE                    0:0
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_WOFFSET                  0x0
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0_SET_PVA0_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0                 MK_ADDR_CONST(0x824)
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_SECURE                  0x0
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_DUAL                    0x0
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_SCR                     RAMDUMP_COM_SCR_0
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_SCRREG                  PMC_IMPL_SCR_RAMDUMP_COM_SCR_0
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_WORD_COUNT                      0x1
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_READ_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_SHIFT)
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_RANGE                    0:0
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_WOFFSET                  0x0
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0_CLR_PVA0_FIQ_EXITED_GRACEFULLY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0                   MK_ADDR_CONST(0x828)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_SECURE                    0x0
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_DUAL                      0x0
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_SCR                       PMC_CK_SCR_0
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_SCRREG                    PMC_IMPL_SCR_PMC_CK_SCR_0
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_WORD_COUNT                        0x1
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_RESET_VAL                         MK_MASK_CONST(0x950)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_FIELD                       MK_FIELD_CONST(0xffffffff, PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_RANGE                       31:0
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_MSB                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_WOFFSET                     0x0
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_DEFAULT                     MK_MASK_CONST(0x950)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0_FMON_COUNT_THRESH_HIGH_PMC_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0                    MK_ADDR_CONST(0x82c)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_SECURE                     0x0
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_DUAL                       0x0
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_SCR                        PMC_CK_SCR_0
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_SCRREG                     PMC_IMPL_SCR_PMC_CK_SCR_0
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_WORD_COUNT                         0x1
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_RESET_VAL                  MK_MASK_CONST(0x336)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_FIELD                 MK_FIELD_CONST(0xffffffff, PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_RANGE                 31:0
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_MSB                   MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_WOFFSET                       0x0
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_DEFAULT                       MK_MASK_CONST(0x336)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0_FMON_COUNT_THRESH_LOW_PMC_CK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0                 MK_ADDR_CONST(0x830)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_SECURE                  0x0
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_DUAL                    0x0
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_SCR                     PMC_CK_SCR_0
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_SCRREG                  PMC_IMPL_SCR_PMC_CK_SCR_0
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_WORD_COUNT                      0x1
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_RESET_VAL                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_RESET_MASK                      MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_READ_MASK                       MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_WRITE_MASK                      MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_FIELD                      MK_FIELD_CONST(0xffffff, PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_RANGE                      23:0
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_MSB                        MK_SHIFT_CONST(23)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_WOFFSET                    0x0
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_DEFAULT_MASK                       MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0_FMON_REF_WINDOW_COUNT_PMC_CK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0                        MK_ADDR_CONST(0x834)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_SECURE                         0x0
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_DUAL                   0x0
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_SCR                    PMC_CK_SCR_0
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_SCRREG                         PMC_IMPL_SCR_PMC_CK_SCR_0
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_WORD_COUNT                     0x1
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_RESET_VAL                      MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_RESET_MASK                     MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_READ_MASK                      MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_WRITE_MASK                     MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_FIELD                    MK_FIELD_CONST(0xffffff, PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_RANGE                    23:0
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_MSB                      MK_SHIFT_CONST(23)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_WOFFSET                  0x0
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_DEFAULT                  MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0                     MK_ADDR_CONST(0x838)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_SECURE                      0x0
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_DUAL                        0x0
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_SCR                         PMC_CK_SCR_0
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_SCRREG                      PMC_IMPL_SCR_PMC_CK_SCR_0
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_WORD_COUNT                  0x1
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_RESET_MASK                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_READ_MASK                   MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_WRITE_MASK                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_SHIFT                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_RANGE                       2:2
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_MSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_LSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_WOFFSET                     0x0
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_INIT_ENUM                   DISABLE
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_DISABLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_DC_RESET_REQ_PMC_CK_ENABLE                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_SHIFT                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_RANGE                       1:1
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_MSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_LSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_WOFFSET                     0x0
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_INIT_ENUM                   DISABLE
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_DISABLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_FAULT_REPORT_PMC_CK_ENABLE                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_RANGE                  0:0
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_WOFFSET                        0x0
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_INIT_ENUM                      DISABLE
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0_FMON_ACTION_RESET_REQ_PMC_CK_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_FMON_CONFIG_PMC_CK_0
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0                   MK_ADDR_CONST(0x83c)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_SECURE                    0x0
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_DUAL                      0x0
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_SCR                       PMC_CK_SCR_0
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_SCRREG                    PMC_IMPL_SCR_PMC_CK_SCR_0
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_WORD_COUNT                        0x1
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_RESET_VAL                         MK_MASK_CONST(0x7f)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_RESET_MASK                        MK_MASK_CONST(0x7f)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_READ_MASK                         MK_MASK_CONST(0x7f)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_WRITE_MASK                        MK_MASK_CONST(0x7f)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_SHIFT                    MK_SHIFT_CONST(6)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_RANGE                    6:6
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_MSB                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_LSB                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_WOFFSET                  0x0
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_INIT_ENUM                        ENABLE
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_DISABLE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_DC_FAULT_VIOL_PMC_CK_ENABLE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_SHIFT                 MK_SHIFT_CONST(5)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_RANGE                 5:5
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_MSB                   MK_SHIFT_CONST(5)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_LSB                   MK_SHIFT_CONST(5)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_WOFFSET                       0x0
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_INIT_ENUM                     ENABLE
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_PMC_CK_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_SHIFT                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_RANGE                  4:4
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_MSB                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_LSB                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_WOFFSET                        0x0
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_INIT_ENUM                      ENABLE
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_LOW_THRESH_VIOL_PMC_CK_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_SHIFT                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_RANGE                   3:3
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_MSB                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_LSB                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_WOFFSET                 0x0
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_INIT_ENUM                       ENABLE
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_DISABLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REPORT_OVERFLOW_ERROR_PMC_CK_ENABLE                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_SHIFT                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_RANGE                       2:2
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_MSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_LSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_WOFFSET                     0x0
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_INIT_ENUM                   ENABLE
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_DISABLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_REF_CLK_WINDOW_EN_PMC_CK_ENABLE                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_RANGE                     1:1
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_WOFFSET                   0x0
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_INIT_ENUM                 ENABLE
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_FMON_COUNTER_PMC_CK_ENABLE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_RANGE                  0:0
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_WOFFSET                        0x0
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_INIT_ENUM                      ENABLE
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_PMC_CK_0_FMON_ENABLE_PMC_CK_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0                    MK_ADDR_CONST(0x840)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_SECURE                     0x0
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_DUAL                       0x0
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_SCR                        PMC_CK_SCR_0
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_SCRREG                     PMC_IMPL_SCR_PMC_CK_SCR_0
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_WORD_COUNT                         0x1
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_RESET_MASK                         MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_READ_MASK                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_RANGE                   2:2
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_WOFFSET                 0x0
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_INIT_ENUM                       FALSE
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_FALSE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_CLK_STATUS_PMC_CK_TRUE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_SHIFT                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_RANGE                       1:1
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_MSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_LSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_WOFFSET                     0x0
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_INIT_ENUM                   FALSE
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_FALSE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_PMC_CK_TRUE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_RANGE                       0:0
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_WOFFSET                     0x0
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_INIT_ENUM                   FALSE
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_FALSE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_PMC_CK_TRUE                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0                     MK_ADDR_CONST(0x844)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_SECURE                      0x0
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_DUAL                        0x0
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_SCR                         PMC_CK_SCR_0
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_SCRREG                      PMC_IMPL_SCR_PMC_CK_SCR_0
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_WORD_COUNT                  0x1
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_RESET_MASK                  MK_MASK_CONST(0x8000001f)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_READ_MASK                   MK_MASK_CONST(0x8000001f)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_WRITE_MASK                  MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_SHIFT                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_RANGE                       31:31
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_MSB                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_LSB                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_WOFFSET                     0x0
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_INIT_ENUM                   FALSE
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_FALSE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_CLEAR_PMC_CK_TRUE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_SHIFT                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_RANGE                  4:4
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_MSB                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_LSB                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_WOFFSET                        0x0
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_INIT_ENUM                      FALSE
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_FALSE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_FAULT_OUT_STATUS_PMC_CK_TRUE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_SHIFT                    MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_RANGE                    3:3
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_MSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_LSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_WOFFSET                  0x0
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_INIT_ENUM                        FALSE
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_FALSE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_OVERFLOW_ERROR_PMC_CK_TRUE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_RANGE                    2:2
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_WOFFSET                  0x0
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_INIT_ENUM                        FALSE
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_FALSE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_PMC_CK_TRUE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_RANGE                     1:1
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_WOFFSET                   0x0
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_INIT_ENUM                 FALSE
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_FALSE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_PMC_CK_TRUE                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_RANGE                  0:0
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_WOFFSET                        0x0
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_INIT_ENUM                      FALSE
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_FALSE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0_FMON_DC_FAULT_PMC_CK_TRUE                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0                   MK_ADDR_CONST(0x848)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_SECURE                    0x0
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_DUAL                      0x0
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_SCR                       PMC_CK_SCR_0
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_SCRREG                    PMC_IMPL_SCR_PMC_CK_SCR_0
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_WORD_COUNT                        0x1
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_RESET_MASK                        MK_MASK_CONST(0x80000007)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_READ_MASK                         MK_MASK_CONST(0x80000007)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_WRITE_MASK                        MK_MASK_CONST(0x80000007)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_SHIFT                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_RANGE                       31:31
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_MSB                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_LSB                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_WOFFSET                     0x0
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_INIT_ENUM                   DISABLE
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_DISABLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_PMC_CK_ENABLE                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_FIELD                   MK_FIELD_CONST(0x7, PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_RANGE                   2:0
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_WOFFSET                 0x0
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_DEFAULT_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_INIT_ENUM                       DISABLE
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_DISABLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0_FMON_LOAD_DATA_SEL_PMC_CK_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0                       MK_ADDR_CONST(0x84c)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_SECURE                        0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_DUAL                  0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_SCR                   PMC_CK_SCR_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_SCRREG                        PMC_IMPL_SCR_PMC_CK_SCR_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_WORD_COUNT                    0x1
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_RANGE                      0:0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_WOFFSET                    0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_INIT_ENUM                  DISABLE
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0_FMON_LOAD_DATA_DONE_PMC_CK_ENABLE                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0                       MK_ADDR_CONST(0x850)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_SECURE                        0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_DUAL                  0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_SCR                   PMC_CK_SCR_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_SCRREG                        PMC_IMPL_SCR_PMC_CK_SCR_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_WORD_COUNT                    0x1
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_RESET_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_READ_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_FIELD                        MK_FIELD_CONST(0x7, PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_RANGE                        2:0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_WOFFSET                      0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0_FMON_LOAD_DATA_SEL_STATUS_PMC_CK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0                       MK_ADDR_CONST(0x854)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_SECURE                        0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_DUAL                  0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_SCR                   PMC_CK_SCR_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_SCRREG                        PMC_IMPL_SCR_PMC_CK_SCR_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_WORD_COUNT                    0x1
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_FIELD                       MK_FIELD_CONST(0xffffffff, PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_RANGE                       31:0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_MSB                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_WOFFSET                     0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0_FMON_LOAD_DATA_VAL_PMC_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0                    MK_ADDR_CONST(0x858)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_SECURE                     0x0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_DUAL                       0x0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_SCR                        PMC_CK_SCR_0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_SCRREG                     PMC_IMPL_SCR_PMC_CK_SCR_0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_WORD_COUNT                         0x1
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_RESET_MASK                         MK_MASK_CONST(0xf)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_READ_MASK                  MK_MASK_CONST(0xf)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_WRITE_MASK                         MK_MASK_CONST(0xf)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_SHIFT                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_RANGE                       3:3
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_MSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_LSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_WOFFSET                     0x0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_HOLD_COUNT_SAMPLES_PMC_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_SHIFT                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_RANGE                       2:2
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_MSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_LSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_WOFFSET                     0x0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_CLEAR_FMON_COUNTER_PMC_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_RANGE                 1:1
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_WOFFSET                       0x0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_PMC_CK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_RANGE                        0:0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_WOFFSET                      0x0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_PMC_CK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0                     MK_ADDR_CONST(0x85c)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_SECURE                      0x0
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_DUAL                        0x0
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_SCR                         PMC_CK_SCR_0
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_SCRREG                      PMC_IMPL_SCR_PMC_CK_SCR_0
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_WORD_COUNT                  0x1
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_RESET_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_READ_MASK                   MK_MASK_CONST(0x3)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_RANGE                        1:1
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_WOFFSET                      0x0
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_REF_WINDOW_PMC_CK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_RANGE                      0:0
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_WOFFSET                    0x0
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_INIT_ENUM                  DISABLE
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0_FMON_ENABLE_DEBUG_PMC_CK_ENABLE                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0                       MK_ADDR_CONST(0x860)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_SECURE                        0x0
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_DUAL                  0x0
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_SCR                   PMC_CK_SCR_0
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_SCRREG                        PMC_IMPL_SCR_PMC_CK_SCR_0
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_WORD_COUNT                    0x1
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_RESET_VAL                     MK_MASK_CONST(0x8000000c)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_RESET_MASK                    MK_MASK_CONST(0x8000001f)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_READ_MASK                     MK_MASK_CONST(0x8000001f)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_WRITE_MASK                    MK_MASK_CONST(0x8000001f)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_FIELD                    MK_FIELD_CONST(0x1f, PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_RANGE                    4:0
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_MSB                      MK_SHIFT_CONST(4)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_WOFFSET                  0x0
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_DEFAULT                  MK_MASK_CONST(0xc)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_DEFAULT_MASK                     MK_MASK_CONST(0x1f)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_FMON_OVERFLOW_BIT_SEL_PMC_CK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_SHIFT                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_RANGE                       31:31
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_MSB                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_LSB                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_WOFFSET                     0x0
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_INIT_ENUM                   ENABLE
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_DISABLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_PMC_CK_ENABLE                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0                      MK_ADDR_CONST(0x864)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_SECURE                       0x0
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_DUAL                         0x0
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_SCR                  OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_SCRREG                       PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_WORD_COUNT                   0x1
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_RESET_VAL                    MK_MASK_CONST(0x48f)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0xffffffff, PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_RANGE                     31:0
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_WOFFSET                   0x0
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x48f)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0_FMON_COUNT_THRESH_HIGH_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0                       MK_ADDR_CONST(0x868)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_SECURE                        0x0
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_DUAL                  0x0
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_SCR                   OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_SCRREG                        PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_WORD_COUNT                    0x1
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_RESET_VAL                     MK_MASK_CONST(0x1f3)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_FIELD                       MK_FIELD_CONST(0xffffffff, PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_RANGE                       31:0
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_MSB                 MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_WOFFSET                     0x0
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_DEFAULT                     MK_MASK_CONST(0x1f3)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0_FMON_COUNT_THRESH_LOW_OSCnFUSE_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0                    MK_ADDR_CONST(0x86c)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_SECURE                     0x0
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_DUAL                       0x0
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_SCR                        OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_SCRREG                     PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_WORD_COUNT                         0x1
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_RESET_VAL                  MK_MASK_CONST(0x280)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_RESET_MASK                         MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_READ_MASK                  MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_WRITE_MASK                         MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_FIELD                    MK_FIELD_CONST(0xffffff, PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_RANGE                    23:0
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_MSB                      MK_SHIFT_CONST(23)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_WOFFSET                  0x0
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_DEFAULT                  MK_MASK_CONST(0x280)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_DEFAULT_MASK                     MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0                   MK_ADDR_CONST(0x870)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_SECURE                    0x0
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_DUAL                      0x0
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_SCR                       OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_SCRREG                    PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_WORD_COUNT                        0x1
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_RESET_VAL                         MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_RESET_MASK                        MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_READ_MASK                         MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_WRITE_MASK                        MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_FIELD                  MK_FIELD_CONST(0xffffff, PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_RANGE                  23:0
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_MSB                    MK_SHIFT_CONST(23)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_WOFFSET                        0x0
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_DEFAULT                        MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_DEFAULT_MASK                   MK_MASK_CONST(0xffffff)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0                        MK_ADDR_CONST(0x874)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_SECURE                         0x0
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_DUAL                   0x0
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_SCR                    OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_SCRREG                         PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_WORD_COUNT                     0x1
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_RESET_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_READ_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_WRITE_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_RANGE                     2:2
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_WOFFSET                   0x0
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_INIT_ENUM                 DISABLE
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_DC_RESET_REQ_OSCnFUSE_CK_ENABLE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_RANGE                     1:1
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_WOFFSET                   0x0
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_INIT_ENUM                 DISABLE
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_FAULT_REPORT_OSCnFUSE_CK_ENABLE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_RANGE                        0:0
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_WOFFSET                      0x0
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_INIT_ENUM                    DISABLE
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0_FMON_ACTION_RESET_REQ_OSCnFUSE_CK_ENABLE                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0                      MK_ADDR_CONST(0x878)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_SECURE                       0x0
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_DUAL                         0x0
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_SCR                  OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_SCRREG                       PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_WORD_COUNT                   0x1
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_RESET_VAL                    MK_MASK_CONST(0x7f)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_RESET_MASK                   MK_MASK_CONST(0x7f)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_READ_MASK                    MK_MASK_CONST(0x7f)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_WRITE_MASK                   MK_MASK_CONST(0x7f)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_SHIFT                  MK_SHIFT_CONST(6)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_RANGE                  6:6
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_MSB                    MK_SHIFT_CONST(6)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_LSB                    MK_SHIFT_CONST(6)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_WOFFSET                        0x0
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_INIT_ENUM                      ENABLE
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_DC_FAULT_VIOL_OSCnFUSE_CK_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_SHIFT                       MK_SHIFT_CONST(5)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_RANGE                       5:5
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_MSB                 MK_SHIFT_CONST(5)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_LSB                 MK_SHIFT_CONST(5)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_WOFFSET                     0x0
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_INIT_ENUM                   ENABLE
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_DISABLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_HIGH_THRESH_VIOL_OSCnFUSE_CK_ENABLE                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_SHIFT                        MK_SHIFT_CONST(4)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_RANGE                        4:4
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_MSB                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_LSB                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_WOFFSET                      0x0
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_INIT_ENUM                    ENABLE
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_LOW_THRESH_VIOL_OSCnFUSE_CK_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_SHIFT                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_RANGE                 3:3
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_MSB                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_LSB                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_WOFFSET                       0x0
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_INIT_ENUM                     ENABLE
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REPORT_OVERFLOW_ERROR_OSCnFUSE_CK_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_RANGE                     2:2
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_WOFFSET                   0x0
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_INIT_ENUM                 ENABLE
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_REF_CLK_WINDOW_EN_OSCnFUSE_CK_ENABLE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_RANGE                   1:1
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_WOFFSET                 0x0
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_INIT_ENUM                       ENABLE
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_DISABLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_FMON_COUNTER_OSCnFUSE_CK_ENABLE                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_RANGE                        0:0
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_WOFFSET                      0x0
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_INIT_ENUM                    ENABLE
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_OSCnFUSE_CK_ENABLE                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0                       MK_ADDR_CONST(0x87c)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_SECURE                        0x0
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_DUAL                  0x0
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_SCR                   OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_SCRREG                        PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_WORD_COUNT                    0x1
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_RESET_MASK                    MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_READ_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_RANGE                 2:2
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_WOFFSET                       0x0
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_INIT_ENUM                     FALSE
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_FALSE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_CLK_STATUS_OSCnFUSE_CK_TRUE                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_RANGE                     1:1
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_WOFFSET                   0x0
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_INIT_ENUM                 FALSE
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_FALSE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_ERR_CLK_STATUS_OSCnFUSE_CK_TRUE                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_RANGE                     0:0
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_WOFFSET                   0x0
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_INIT_ENUM                 FALSE
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_FALSE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0_FMON_ENABLE_FMON_REF_CLK_STATUS_OSCnFUSE_CK_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0                        MK_ADDR_CONST(0x880)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_SECURE                         0x0
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_DUAL                   0x0
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_SCR                    OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_SCRREG                         PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_WORD_COUNT                     0x1
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_RESET_MASK                     MK_MASK_CONST(0x8000001f)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_READ_MASK                      MK_MASK_CONST(0x8000001f)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_WRITE_MASK                     MK_MASK_CONST(0x80000000)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_RANGE                     31:31
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_WOFFSET                   0x0
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_INIT_ENUM                 FALSE
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_FALSE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_CLEAR_OSCnFUSE_CK_TRUE                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_SHIFT                        MK_SHIFT_CONST(4)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_RANGE                        4:4
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_MSB                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_LSB                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_WOFFSET                      0x0
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_INIT_ENUM                    FALSE
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_FALSE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_FAULT_OUT_STATUS_OSCnFUSE_CK_TRUE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_SHIFT                  MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_RANGE                  3:3
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_MSB                    MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_LSB                    MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_WOFFSET                        0x0
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_INIT_ENUM                      FALSE
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_FALSE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_OVERFLOW_ERROR_OSCnFUSE_CK_TRUE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_RANGE                  2:2
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_WOFFSET                        0x0
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_INIT_ENUM                      FALSE
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_FALSE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_HIGHER_THRESH_HIGH_FAULT_OSCnFUSE_CK_TRUE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_RANGE                   1:1
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_WOFFSET                 0x0
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_INIT_ENUM                       FALSE
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_FALSE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_COUNT_LOWER_THRESH_HIGH_FAULT_OSCnFUSE_CK_TRUE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_RANGE                        0:0
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_WOFFSET                      0x0
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_INIT_ENUM                    FALSE
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_FALSE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0_FMON_DC_FAULT_OSCnFUSE_CK_TRUE                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0                      MK_ADDR_CONST(0x884)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_SECURE                       0x0
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_DUAL                         0x0
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_SCR                  OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_SCRREG                       PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_WORD_COUNT                   0x1
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_RESET_MASK                   MK_MASK_CONST(0x80000007)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_READ_MASK                    MK_MASK_CONST(0x80000007)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_WRITE_MASK                   MK_MASK_CONST(0x80000007)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_RANGE                     31:31
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_WOFFSET                   0x0
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_INIT_ENUM                 DISABLE
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_OSCnFUSE_CK_ENABLE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_FIELD                 MK_FIELD_CONST(0x7, PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_RANGE                 2:0
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_WOFFSET                       0x0
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_INIT_ENUM                     DISABLE
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_OSCnFUSE_CK_ENABLE                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0                  MK_ADDR_CONST(0x888)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_SECURE                   0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_DUAL                     0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_SCR                      OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_SCRREG                   PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_WORD_COUNT                       0x1
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_RANGE                    0:0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_WOFFSET                  0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_INIT_ENUM                        DISABLE
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_DISABLE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0_FMON_LOAD_DATA_DONE_OSCnFUSE_CK_ENABLE                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0                  MK_ADDR_CONST(0x88c)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_SECURE                   0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_DUAL                     0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_SCR                      OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_SCRREG                   PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_WORD_COUNT                       0x1
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_RESET_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_READ_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_FIELD                      MK_FIELD_CONST(0x7, PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_RANGE                      2:0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_WOFFSET                    0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0_FMON_LOAD_DATA_SEL_STATUS_OSCnFUSE_CK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0                  MK_ADDR_CONST(0x890)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_SECURE                   0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_DUAL                     0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_SCR                      OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_SCRREG                   PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_WORD_COUNT                       0x1
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0xffffffff, PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_RANGE                     31:0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_WOFFSET                   0x0
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0_FMON_LOAD_DATA_VAL_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0                       MK_ADDR_CONST(0x894)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_SECURE                        0x0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_DUAL                  0x0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_SCR                   OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_SCRREG                        PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_WORD_COUNT                    0x1
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_RESET_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_READ_MASK                     MK_MASK_CONST(0xf)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_WRITE_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_RANGE                     3:3
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_WOFFSET                   0x0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_HOLD_COUNT_SAMPLES_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_RANGE                     2:2
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_WOFFSET                   0x0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_CLEAR_FMON_COUNTER_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_SHIFT                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_RANGE                       1:1
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_MSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_LSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_WOFFSET                     0x0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MASK_MIN_MAX_COUNT_CLEAR_OSCnFUSE_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_RANGE                      0:0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_WOFFSET                    0x0
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0_FMON_MIN_MAX_LASTN_COUNT_CLEAR_OSCnFUSE_CK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0                        MK_ADDR_CONST(0x898)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_SECURE                         0x0
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_DUAL                   0x0
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_SCR                    OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_SCRREG                         PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_WORD_COUNT                     0x1
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_RESET_MASK                     MK_MASK_CONST(0x3)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_READ_MASK                      MK_MASK_CONST(0x3)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_RANGE                      1:1
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_WOFFSET                    0x0
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_REF_WINDOW_OSCnFUSE_CK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_RANGE                    0:0
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_WOFFSET                  0x0
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_INIT_ENUM                        DISABLE
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_DISABLE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0_FMON_ENABLE_DEBUG_OSCnFUSE_CK_ENABLE                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0                  MK_ADDR_CONST(0x89c)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_SECURE                   0x0
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_DUAL                     0x0
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_SCR                      OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_SCRREG                   PMC_IMPL_SCR_OSCnFUSE_CK_SCR_0
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_WORD_COUNT                       0x1
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_RESET_VAL                        MK_MASK_CONST(0x8000000b)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_RESET_MASK                       MK_MASK_CONST(0x8000001f)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_READ_MASK                        MK_MASK_CONST(0x8000001f)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_WRITE_MASK                       MK_MASK_CONST(0x8000001f)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_FIELD                  MK_FIELD_CONST(0x1f, PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_RANGE                  4:0
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_MSB                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_WOFFSET                        0x0
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_DEFAULT                        MK_MASK_CONST(0xb)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_FMON_OVERFLOW_BIT_SEL_OSCnFUSE_CK_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_SHIFT                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_RANGE                     31:31
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_LSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_WOFFSET                   0x0
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_INIT_ENUM                 ENABLE
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0_USE_CNTR_OVERFLOW_DC_FAULT_OSCnFUSE_CK_ENABLE                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_FMON_DBG_CONFIG_0
+#define PMC_IMPL_FMON_DBG_CONFIG_0                      MK_ADDR_CONST(0x8a0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_SECURE                       0x0
+#define PMC_IMPL_FMON_DBG_CONFIG_0_DUAL                         0x0
+#define PMC_IMPL_FMON_DBG_CONFIG_0_SCR                  FMON_COM_SCR_0
+#define PMC_IMPL_FMON_DBG_CONFIG_0_SCRREG                       PMC_IMPL_SCR_FMON_COM_SCR_0
+#define PMC_IMPL_FMON_DBG_CONFIG_0_WORD_COUNT                   0x1
+#define PMC_IMPL_FMON_DBG_CONFIG_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_RESET_MASK                   MK_MASK_CONST(0xf01)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_READ_MASK                    MK_MASK_CONST(0xf01)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_WRITE_MASK                   MK_MASK_CONST(0xf01)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_SHIFT)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_RANGE                     0:0
+#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_WOFFSET                   0x0
+#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_INIT_ENUM                 DISABLE
+#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_DISABLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_USE_OSC_STABLE_IN_FOSC_FMON_ENABLE_ENABLE                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_SHIFT                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_RANGE                       8:8
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_MSB                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_LSB                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_WOFFSET                     0x0
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_OSCNFUSE_CK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_SHIFT                 MK_SHIFT_CONST(9)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_SHIFT)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_RANGE                 9:9
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_MSB                   MK_SHIFT_CONST(9)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_LSB                   MK_SHIFT_CONST(9)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_WOFFSET                       0x0
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_OSCNFUSE_CK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_SHIFT                    MK_SHIFT_CONST(10)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_RANGE                    10:10
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_MSB                      MK_SHIFT_CONST(10)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_LSB                      MK_SHIFT_CONST(10)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_WOFFSET                  0x0
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_CLEAR2HSM_PMC_CK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_SHIFT                      MK_SHIFT_CONST(11)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_SHIFT)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_RANGE                      11:11
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_MSB                        MK_SHIFT_CONST(11)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_LSB                        MK_SHIFT_CONST(11)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_WOFFSET                    0x0
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_FMON_DBG_CONFIG_0_FMON_FAULT_SET2HSM_PMC_CK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_L0L1A_RST_SOURCE_EN_0
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0                  MK_ADDR_CONST(0x8a4)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SECURE                   0x0
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_DUAL                     0x0
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SCR                      ASYNC_RST_SCR_0
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SCRREG                   PMC_IMPL_SCR_ASYNC_RST_SCR_0
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_WORD_COUNT                       0x1
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_RESET_MASK                       MK_MASK_CONST(0x1f71)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_READ_MASK                        MK_MASK_CONST(0x1f71)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_WRITE_MASK                       MK_MASK_CONST(0x1f71)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_SHIFT)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_RANGE                    0:0
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_WOFFSET                  0x0
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_INIT_ENUM                        DISABLE
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_DISABLE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VREFRORST_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_SHIFT                       MK_SHIFT_CONST(4)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_SHIFT)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_RANGE                       4:4
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_MSB                 MK_SHIFT_CONST(4)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_LSB                 MK_SHIFT_CONST(4)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_WOFFSET                     0x0
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_INIT_ENUM                   DISABLE
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_DISABLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_OSCRSTREQ_ENABLE                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_SHIFT                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_SHIFT)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_RANGE                    5:5
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_MSB                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_LSB                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_WOFFSET                  0x0
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_INIT_ENUM                        DISABLE
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_DISABLE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDSOCRST_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_SHIFT                  MK_SHIFT_CONST(6)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_SHIFT)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_RANGE                  6:6
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_MSB                    MK_SHIFT_CONST(6)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_LSB                    MK_SHIFT_CONST(6)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_WOFFSET                        0x0
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_INIT_ENUM                      DISABLE
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_DISABLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FUSECRC_RSTREQ_ENABLE                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_SHIFT                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_SHIFT)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_RANGE                   8:8
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_MSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_LSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_WOFFSET                 0x0
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_INIT_ENUM                       DISABLE
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_DISABLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU0RST_EN_ENABLE                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_SHIFT                   MK_SHIFT_CONST(9)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_SHIFT)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_RANGE                   9:9
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_MSB                     MK_SHIFT_CONST(9)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_LSB                     MK_SHIFT_CONST(9)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_WOFFSET                 0x0
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_INIT_ENUM                       DISABLE
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_DISABLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDCPU1RST_EN_ENABLE                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_SHIFT                      MK_SHIFT_CONST(10)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_SHIFT)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_RANGE                      10:10
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_MSB                        MK_SHIFT_CONST(10)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_LSB                        MK_SHIFT_CONST(10)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_WOFFSET                    0x0
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_INIT_ENUM                  DISABLE
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_DISABLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_BPMPRST_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FSI_FMON_RST_EN_SHIFT                 MK_SHIFT_CONST(11)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FSI_FMON_RST_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FSI_FMON_RST_EN_SHIFT)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FSI_FMON_RST_EN_RANGE                 11:11
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FSI_FMON_RST_EN_MSB                   MK_SHIFT_CONST(11)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FSI_FMON_RST_EN_LSB                   MK_SHIFT_CONST(11)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FSI_FMON_RST_EN_WOFFSET                       0x0
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FSI_FMON_RST_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FSI_FMON_RST_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FSI_FMON_RST_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FSI_FMON_RST_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FSI_FMON_RST_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FSI_FMON_RST_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FSI_FMON_RST_EN_INIT_ENUM                     DISABLE
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FSI_FMON_RST_EN_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_FSI_FMON_RST_EN_ENABLE                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDFSIRST_EN_SHIFT                    MK_SHIFT_CONST(12)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDFSIRST_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDFSIRST_EN_SHIFT)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDFSIRST_EN_RANGE                    12:12
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDFSIRST_EN_MSB                      MK_SHIFT_CONST(12)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDFSIRST_EN_LSB                      MK_SHIFT_CONST(12)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDFSIRST_EN_WOFFSET                  0x0
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDFSIRST_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDFSIRST_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDFSIRST_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDFSIRST_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDFSIRST_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDFSIRST_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDFSIRST_EN_INIT_ENUM                        DISABLE
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDFSIRST_EN_DISABLE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_L0L1A_RST_SOURCE_EN_0_SW_VDDFSIRST_EN_ENABLE                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_L0L1A_RST_LEVEL_EN_0
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0                   MK_ADDR_CONST(0x8a8)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SECURE                    0x0
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_DUAL                      0x0
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SCR                       ASYNC_RST_SCR_0
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SCRREG                    PMC_IMPL_SCR_ASYNC_RST_SCR_0
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_WORD_COUNT                        0x1
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_RESET_MASK                        MK_MASK_CONST(0x3)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_READ_MASK                         MK_MASK_CONST(0x3)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_WRITE_MASK                        MK_MASK_CONST(0x3)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_SHIFT)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_RANGE                    0:0
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_WOFFSET                  0x0
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_INIT_ENUM                        DISABLE
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_DISABLE                  MK_ENUM_CONST(0)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL0RST_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_SHIFT)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_RANGE                   1:1
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_WOFFSET                 0x0
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_INIT_ENUM                       DISABLE
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_DISABLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_L0L1A_RST_LEVEL_EN_0_SW_ASYNCL1ARST_EN_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_L0L1A_RST_STATUS_0
+#define PMC_IMPL_L0L1A_RST_STATUS_0                     MK_ADDR_CONST(0x8ac)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_L0L1A_RST_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_L0L1A_RST_STATUS_0_SCR                         ASYNC_RST_SCR_0
+#define PMC_IMPL_L0L1A_RST_STATUS_0_SCRREG                      PMC_IMPL_SCR_ASYNC_RST_SCR_0
+#define PMC_IMPL_L0L1A_RST_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_L0L1A_RST_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_READ_MASK                   MK_MASK_CONST(0x3)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_SHIFT)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_RANGE                        0:0
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_WOFFSET                      0x0
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_INIT_ENUM                    DISABLE
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_DISABLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL0RST_ENABLE_ENABLE                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_SHIFT                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_SHIFT)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_RANGE                       1:1
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_MSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_LSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_WOFFSET                     0x0
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_INIT_ENUM                   DISABLE
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_DISABLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_L0L1A_RST_STATUS_0_FUSE_ASYNCL1ARST_ENABLE_ENABLE                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_DVDD_RG_CNTRL_0
+#define PMC_IMPL_DVDD_RG_CNTRL_0                        MK_ADDR_CONST(0x8b0)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_SECURE                         0x0
+#define PMC_IMPL_DVDD_RG_CNTRL_0_DUAL                   0x0
+#define PMC_IMPL_DVDD_RG_CNTRL_0_SCR                    DVDD_SCR_0
+#define PMC_IMPL_DVDD_RG_CNTRL_0_SCRREG                         PMC_IMPL_SCR_DVDD_SCR_0
+#define PMC_IMPL_DVDD_RG_CNTRL_0_WORD_COUNT                     0x1
+#define PMC_IMPL_DVDD_RG_CNTRL_0_RESET_VAL                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_SHIFT)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_RANGE                       0:0
+#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_WOFFSET                     0x0
+#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_DISABLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_DVDD_RG_CNTRL_0_RAIL_CLAMP_ENABLE                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_CV_RG_CNTRL_0
+#define PMC_IMPL_CV_RG_CNTRL_0                  MK_ADDR_CONST(0x8b4)
+#define PMC_IMPL_CV_RG_CNTRL_0_SECURE                   0x0
+#define PMC_IMPL_CV_RG_CNTRL_0_DUAL                     0x0
+#define PMC_IMPL_CV_RG_CNTRL_0_SCR                      CV_SCR_0
+#define PMC_IMPL_CV_RG_CNTRL_0_SCRREG                   PMC_IMPL_SCR_CV_SCR_0
+#define PMC_IMPL_CV_RG_CNTRL_0_WORD_COUNT                       0x1
+#define PMC_IMPL_CV_RG_CNTRL_0_RESET_VAL                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_CV_RG_CNTRL_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_CV_RG_CNTRL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_CV_RG_CNTRL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_CV_RG_CNTRL_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_CV_RG_CNTRL_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_SHIFT)
+#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_RANGE                 0:0
+#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_WOFFSET                       0x0
+#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_DISABLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_CV_RG_CNTRL_0_RAIL_CLAMP_ENABLE                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_SC7_RST_REQ_TIMER_0
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0                    MK_ADDR_CONST(0x8b8)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_SECURE                     0x0
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_DUAL                       0x0
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_SCR                        SC78_SCR_0
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_SCRREG                     PMC_IMPL_SCR_SC78_SCR_0
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_WORD_COUNT                         0x1
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_RESET_VAL                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_RESET_MASK                         MK_MASK_CONST(0xff)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_READ_MASK                  MK_MASK_CONST(0xff)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_WRITE_MASK                         MK_MASK_CONST(0xff)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_FIELD                   MK_FIELD_CONST(0xf, PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_SHIFT)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_RANGE                   3:0
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_MSB                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_WOFFSET                 0x0
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_DEFAULT_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_PRERST_TGT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_SHIFT                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_FIELD                  MK_FIELD_CONST(0xf, PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_SHIFT)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_RANGE                  7:4
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_MSB                    MK_SHIFT_CONST(7)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_LSB                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_WOFFSET                        0x0
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SC7_RST_REQ_TIMER_0_POSTRST_TGT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_RST_REQ_TIMER_0
+#define PMC_IMPL_RST_REQ_TIMER_0                        MK_ADDR_CONST(0x8bc)
+#define PMC_IMPL_RST_REQ_TIMER_0_SECURE                         0x0
+#define PMC_IMPL_RST_REQ_TIMER_0_DUAL                   0x0
+#define PMC_IMPL_RST_REQ_TIMER_0_SCR                    CNTRL_SCR_0
+#define PMC_IMPL_RST_REQ_TIMER_0_SCRREG                         PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_RST_REQ_TIMER_0_WORD_COUNT                     0x1
+#define PMC_IMPL_RST_REQ_TIMER_0_RESET_VAL                      MK_MASK_CONST(0x6)
+#define PMC_IMPL_RST_REQ_TIMER_0_RESET_MASK                     MK_MASK_CONST(0xff)
+#define PMC_IMPL_RST_REQ_TIMER_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_TIMER_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_TIMER_0_READ_MASK                      MK_MASK_CONST(0xff)
+#define PMC_IMPL_RST_REQ_TIMER_0_WRITE_MASK                     MK_MASK_CONST(0xff)
+#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_FIELD                        MK_FIELD_CONST(0xff, PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_SHIFT)
+#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_RANGE                        7:0
+#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_MSB                  MK_SHIFT_CONST(7)
+#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_WOFFSET                      0x0
+#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_DEFAULT                      MK_MASK_CONST(0x6)
+#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_RST_REQ_TIMER_0_WAIT_CLK_STOP_VAL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_ASYNC_RST_SC7_CONFIG_0
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0                 MK_ADDR_CONST(0x8c0)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SECURE                  0x0
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_DUAL                    0x0
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SCR                     ASYNC_RST_SC7_SCR_0
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SCRREG                  PMC_IMPL_SCR_ASYNC_RST_SC7_SCR_0
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_WORD_COUNT                      0x1
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_RESET_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_READ_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_SHIFT)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_RANGE                        0:0
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_WOFFSET                      0x0
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_INIT_ENUM                    UNMASKED
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_UNMASKED                     MK_ENUM_CONST(0)
+#define PMC_IMPL_ASYNC_RST_SC7_CONFIG_0_SW_SC7_DIS_MASKED                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_PMC_RESET_DETECTOR_0
+#define PMC_IMPL_PMC_RESET_DETECTOR_0                   MK_ADDR_CONST(0x8c4)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_SECURE                    0x0
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_DUAL                      0x0
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_SCR                       0
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_SCRREG                    0
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_WORD_COUNT                        0x1
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_RESET_VAL                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_SHIFT)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_RANGE                      0:0
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_WOFFSET                    0x0
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_INIT_ENUM                  DETECTED
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_DETECTED                   MK_ENUM_CONST(1)
+#define PMC_IMPL_PMC_RESET_DETECTOR_0_pmc2dfd_reset_detector_NOT_DETECTED                       MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_LED_BREATHING_CTRL_0
+#define PMC_IMPL_LED_BREATHING_CTRL_0                   MK_ADDR_CONST(0x8c8)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_SECURE                    0x0
+#define PMC_IMPL_LED_BREATHING_CTRL_0_DUAL                      0x0
+#define PMC_IMPL_LED_BREATHING_CTRL_0_SCR                       CNTRL_SCR_0
+#define PMC_IMPL_LED_BREATHING_CTRL_0_SCRREG                    PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_LED_BREATHING_CTRL_0_WORD_COUNT                        0x1
+#define PMC_IMPL_LED_BREATHING_CTRL_0_RESET_VAL                         MK_MASK_CONST(0x2)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_RESET_MASK                        MK_MASK_CONST(0x3)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_READ_MASK                         MK_MASK_CONST(0x3)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_WRITE_MASK                        MK_MASK_CONST(0x3)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_SHIFT)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_RANGE                        0:0
+#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_WOFFSET                      0x0
+#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_BREATHING_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_SHIFT)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_RANGE                 1:1
+#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_WOFFSET                       0x0
+#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_CTRL_0_SHORT_LOW_PERIOD_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_LED_BREATHING_COUNTER0_0
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0                       MK_ADDR_CONST(0x8cc)
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_SECURE                        0x0
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_DUAL                  0x0
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_SCR                   CNTRL_SCR_0
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_SCRREG                        PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_WORD_COUNT                    0x1
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_RESET_VAL                     MK_MASK_CONST(0x4)
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_FIELD                     MK_FIELD_CONST(0xffffffff, PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_SHIFT)
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_RANGE                     31:0
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_WOFFSET                   0x0
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_DEFAULT                   MK_MASK_CONST(0x4)
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER0_0_NO_OF_STEPS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_LED_BREATHING_COUNTER1_0
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0                       MK_ADDR_CONST(0x8d0)
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_SECURE                        0x0
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_DUAL                  0x0
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_SCR                   CNTRL_SCR_0
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_SCRREG                        PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_WORD_COUNT                    0x1
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_RESET_VAL                     MK_MASK_CONST(0x1f)
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_FIELD                   MK_FIELD_CONST(0xffffffff, PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_SHIFT)
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_RANGE                   31:0
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_MSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_WOFFSET                 0x0
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_DEFAULT                 MK_MASK_CONST(0x1f)
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER1_0_PLATEAU_COUNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_LED_BREATHING_COUNTER2_0
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0                       MK_ADDR_CONST(0x8d4)
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SECURE                        0x0
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_DUAL                  0x0
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SCR                   CNTRL_SCR_0
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SCRREG                        PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_WORD_COUNT                    0x1
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_RESET_VAL                     MK_MASK_CONST(0xf)
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_FIELD                  MK_FIELD_CONST(0xffffffff, PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_SHIFT)
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_RANGE                  31:0
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_MSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_WOFFSET                        0x0
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_DEFAULT                        MK_MASK_CONST(0xf)
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER2_0_SHORT_LOW_PERIOD_COUNT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_LED_BREATHING_COUNTER3_0
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0                       MK_ADDR_CONST(0x8d8)
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_SECURE                        0x0
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_DUAL                  0x0
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_SCR                   CNTRL_SCR_0
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_SCRREG                        PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_WORD_COUNT                    0x1
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_RESET_VAL                     MK_MASK_CONST(0x1f)
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_FIELD                   MK_FIELD_CONST(0xffffffff, PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_SHIFT)
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_RANGE                   31:0
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_MSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_WOFFSET                 0x0
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_DEFAULT                 MK_MASK_CONST(0x1f)
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_COUNTER3_0_LONG_LOW_PERIOD_COUNT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_LED_BREATHING_STATUS_0
+#define PMC_IMPL_LED_BREATHING_STATUS_0                 MK_ADDR_CONST(0x8dc)
+#define PMC_IMPL_LED_BREATHING_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_LED_BREATHING_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_LED_BREATHING_STATUS_0_SCR                     CNTRL_SCR_0
+#define PMC_IMPL_LED_BREATHING_STATUS_0_SCRREG                  PMC_IMPL_SCR_CNTRL_SCR_0
+#define PMC_IMPL_LED_BREATHING_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_LED_BREATHING_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_LED_BREATHING_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_FIELD                    MK_FIELD_CONST(0x7, PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_SHIFT)
+#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_RANGE                    2:0
+#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_WOFFSET                  0x0
+#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_LED_BREATHING_STATUS_0_CSTATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_DPD_AUX_CLAMP_0
+#define PMC_IMPL_DPD_AUX_CLAMP_0                        MK_ADDR_CONST(0x8e0)
+#define PMC_IMPL_DPD_AUX_CLAMP_0_SECURE                         0x0
+#define PMC_IMPL_DPD_AUX_CLAMP_0_DUAL                   0x0
+#define PMC_IMPL_DPD_AUX_CLAMP_0_SCR                    AUX_CLAMP_SCR_0
+#define PMC_IMPL_DPD_AUX_CLAMP_0_SCRREG                         PMC_IMPL_SCR_AUX_CLAMP_SCR_0
+#define PMC_IMPL_DPD_AUX_CLAMP_0_WORD_COUNT                     0x1
+#define PMC_IMPL_DPD_AUX_CLAMP_0_RESET_VAL                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_DPD_AUX_CLAMP_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_DPD_AUX_CLAMP_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_AUX_CLAMP_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_AUX_CLAMP_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_DPD_AUX_CLAMP_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_SHIFT)
+#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_RANGE                        0:0
+#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_WOFFSET                      0x0
+#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_DPD_AUX_CLAMP_0_AUX_CLAMP_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_L2_SOURCE_MASK_0
+#define PMC_IMPL_L2_SOURCE_MASK_0                       MK_ADDR_CONST(0x8e4)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SECURE                        0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_DUAL                  0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_SCR                   L2_RST_SRC_SCR_0
+#define PMC_IMPL_L2_SOURCE_MASK_0_SCRREG                        PMC_IMPL_SCR_L2_RST_SRC_SCR_0
+#define PMC_IMPL_L2_SOURCE_MASK_0_WORD_COUNT                    0x1
+#define PMC_IMPL_L2_SOURCE_MASK_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_RESET_MASK                    MK_MASK_CONST(0x1ffff)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_READ_MASK                     MK_MASK_CONST(0x1ffff)
+#define PMC_IMPL_L2_SOURCE_MASK_0_WRITE_MASK                    MK_MASK_CONST(0x1ffff)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BCCPLEXWDT_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BCCPLEXWDT_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_L2_SOURCE_MASK_0_BCCPLEXWDT_SHIFT)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BCCPLEXWDT_RANGE                      0:0
+#define PMC_IMPL_L2_SOURCE_MASK_0_BCCPLEXWDT_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BCCPLEXWDT_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BCCPLEXWDT_WOFFSET                    0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_BCCPLEXWDT_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BCCPLEXWDT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BCCPLEXWDT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BCCPLEXWDT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BCCPLEXWDT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BCCPLEXWDT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BCCPLEXWDT_INIT_ENUM                  UNMASK
+#define PMC_IMPL_L2_SOURCE_MASK_0_BCCPLEXWDT_UNMASK                     MK_ENUM_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BCCPLEXWDT_MASK                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L2_SOURCE_MASK_0_LCCPLEXWDT_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_LCCPLEXWDT_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_L2_SOURCE_MASK_0_LCCPLEXWDT_SHIFT)
+#define PMC_IMPL_L2_SOURCE_MASK_0_LCCPLEXWDT_RANGE                      1:1
+#define PMC_IMPL_L2_SOURCE_MASK_0_LCCPLEXWDT_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_LCCPLEXWDT_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_LCCPLEXWDT_WOFFSET                    0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_LCCPLEXWDT_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_LCCPLEXWDT_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_LCCPLEXWDT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_LCCPLEXWDT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_LCCPLEXWDT_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_LCCPLEXWDT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_LCCPLEXWDT_INIT_ENUM                  UNMASK
+#define PMC_IMPL_L2_SOURCE_MASK_0_LCCPLEXWDT_UNMASK                     MK_ENUM_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_LCCPLEXWDT_MASK                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L2_SOURCE_MASK_0_APEWDT_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_L2_SOURCE_MASK_0_APEWDT_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_L2_SOURCE_MASK_0_APEWDT_SHIFT)
+#define PMC_IMPL_L2_SOURCE_MASK_0_APEWDT_RANGE                  2:2
+#define PMC_IMPL_L2_SOURCE_MASK_0_APEWDT_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_L2_SOURCE_MASK_0_APEWDT_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_L2_SOURCE_MASK_0_APEWDT_WOFFSET                        0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_APEWDT_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_APEWDT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_APEWDT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_APEWDT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_APEWDT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_APEWDT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_APEWDT_INIT_ENUM                      UNMASK
+#define PMC_IMPL_L2_SOURCE_MASK_0_APEWDT_UNMASK                 MK_ENUM_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_APEWDT_MASK                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L2_SOURCE_MASK_0_BPMPWDT_SHIFT                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BPMPWDT_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_L2_SOURCE_MASK_0_BPMPWDT_SHIFT)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BPMPWDT_RANGE                 3:3
+#define PMC_IMPL_L2_SOURCE_MASK_0_BPMPWDT_MSB                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BPMPWDT_LSB                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BPMPWDT_WOFFSET                       0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_BPMPWDT_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BPMPWDT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BPMPWDT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BPMPWDT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BPMPWDT_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BPMPWDT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BPMPWDT_INIT_ENUM                     UNMASK
+#define PMC_IMPL_L2_SOURCE_MASK_0_BPMPWDT_UNMASK                        MK_ENUM_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_BPMPWDT_MASK                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L2_SOURCE_MASK_0_SCEWDT_SHIFT                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SCEWDT_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_L2_SOURCE_MASK_0_SCEWDT_SHIFT)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SCEWDT_RANGE                  4:4
+#define PMC_IMPL_L2_SOURCE_MASK_0_SCEWDT_MSB                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SCEWDT_LSB                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SCEWDT_WOFFSET                        0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_SCEWDT_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SCEWDT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SCEWDT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SCEWDT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SCEWDT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SCEWDT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SCEWDT_INIT_ENUM                      UNMASK
+#define PMC_IMPL_L2_SOURCE_MASK_0_SCEWDT_UNMASK                 MK_ENUM_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SCEWDT_MASK                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L2_SOURCE_MASK_0_SPEWDT_SHIFT                  MK_SHIFT_CONST(5)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SPEWDT_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_L2_SOURCE_MASK_0_SPEWDT_SHIFT)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SPEWDT_RANGE                  5:5
+#define PMC_IMPL_L2_SOURCE_MASK_0_SPEWDT_MSB                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SPEWDT_LSB                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SPEWDT_WOFFSET                        0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_SPEWDT_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SPEWDT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SPEWDT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SPEWDT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SPEWDT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SPEWDT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SPEWDT_INIT_ENUM                      UNMASK
+#define PMC_IMPL_L2_SOURCE_MASK_0_SPEWDT_UNMASK                 MK_ENUM_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_SPEWDT_MASK                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L2_SOURCE_MASK_0_AOWDT_SHIFT                   MK_SHIFT_CONST(6)
+#define PMC_IMPL_L2_SOURCE_MASK_0_AOWDT_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_L2_SOURCE_MASK_0_AOWDT_SHIFT)
+#define PMC_IMPL_L2_SOURCE_MASK_0_AOWDT_RANGE                   6:6
+#define PMC_IMPL_L2_SOURCE_MASK_0_AOWDT_MSB                     MK_SHIFT_CONST(6)
+#define PMC_IMPL_L2_SOURCE_MASK_0_AOWDT_LSB                     MK_SHIFT_CONST(6)
+#define PMC_IMPL_L2_SOURCE_MASK_0_AOWDT_WOFFSET                 0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_AOWDT_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_AOWDT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_AOWDT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_AOWDT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_AOWDT_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_AOWDT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_AOWDT_INIT_ENUM                       UNMASK
+#define PMC_IMPL_L2_SOURCE_MASK_0_AOWDT_UNMASK                  MK_ENUM_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_AOWDT_MASK                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L2_SOURCE_MASK_0_RCEWDT_SHIFT                  MK_SHIFT_CONST(7)
+#define PMC_IMPL_L2_SOURCE_MASK_0_RCEWDT_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_L2_SOURCE_MASK_0_RCEWDT_SHIFT)
+#define PMC_IMPL_L2_SOURCE_MASK_0_RCEWDT_RANGE                  7:7
+#define PMC_IMPL_L2_SOURCE_MASK_0_RCEWDT_MSB                    MK_SHIFT_CONST(7)
+#define PMC_IMPL_L2_SOURCE_MASK_0_RCEWDT_LSB                    MK_SHIFT_CONST(7)
+#define PMC_IMPL_L2_SOURCE_MASK_0_RCEWDT_WOFFSET                        0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_RCEWDT_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_RCEWDT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_RCEWDT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_RCEWDT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_RCEWDT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_RCEWDT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_RCEWDT_INIT_ENUM                      UNMASK
+#define PMC_IMPL_L2_SOURCE_MASK_0_RCEWDT_UNMASK                 MK_ENUM_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_RCEWDT_MASK                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L2_SOURCE_MASK_0_DCEWDT_SHIFT                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_L2_SOURCE_MASK_0_DCEWDT_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_L2_SOURCE_MASK_0_DCEWDT_SHIFT)
+#define PMC_IMPL_L2_SOURCE_MASK_0_DCEWDT_RANGE                  8:8
+#define PMC_IMPL_L2_SOURCE_MASK_0_DCEWDT_MSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_L2_SOURCE_MASK_0_DCEWDT_LSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_L2_SOURCE_MASK_0_DCEWDT_WOFFSET                        0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_DCEWDT_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_DCEWDT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_DCEWDT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_DCEWDT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_DCEWDT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_DCEWDT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_DCEWDT_INIT_ENUM                      UNMASK
+#define PMC_IMPL_L2_SOURCE_MASK_0_DCEWDT_UNMASK                 MK_ENUM_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_DCEWDT_MASK                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L2_SOURCE_MASK_0_PSCWDT_SHIFT                  MK_SHIFT_CONST(9)
+#define PMC_IMPL_L2_SOURCE_MASK_0_PSCWDT_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_L2_SOURCE_MASK_0_PSCWDT_SHIFT)
+#define PMC_IMPL_L2_SOURCE_MASK_0_PSCWDT_RANGE                  9:9
+#define PMC_IMPL_L2_SOURCE_MASK_0_PSCWDT_MSB                    MK_SHIFT_CONST(9)
+#define PMC_IMPL_L2_SOURCE_MASK_0_PSCWDT_LSB                    MK_SHIFT_CONST(9)
+#define PMC_IMPL_L2_SOURCE_MASK_0_PSCWDT_WOFFSET                        0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_PSCWDT_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_PSCWDT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_PSCWDT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_PSCWDT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_PSCWDT_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_PSCWDT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_PSCWDT_INIT_ENUM                      UNMASK
+#define PMC_IMPL_L2_SOURCE_MASK_0_PSCWDT_UNMASK                 MK_ENUM_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_PSCWDT_MASK                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L2_SOURCE_MASK_0_CSITE_SW_SHIFT                        MK_SHIFT_CONST(10)
+#define PMC_IMPL_L2_SOURCE_MASK_0_CSITE_SW_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_L2_SOURCE_MASK_0_CSITE_SW_SHIFT)
+#define PMC_IMPL_L2_SOURCE_MASK_0_CSITE_SW_RANGE                        10:10
+#define PMC_IMPL_L2_SOURCE_MASK_0_CSITE_SW_MSB                  MK_SHIFT_CONST(10)
+#define PMC_IMPL_L2_SOURCE_MASK_0_CSITE_SW_LSB                  MK_SHIFT_CONST(10)
+#define PMC_IMPL_L2_SOURCE_MASK_0_CSITE_SW_WOFFSET                      0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_CSITE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_CSITE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_CSITE_SW_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_CSITE_SW_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_CSITE_SW_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_CSITE_SW_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_CSITE_SW_INIT_ENUM                    UNMASK
+#define PMC_IMPL_L2_SOURCE_MASK_0_CSITE_SW_UNMASK                       MK_ENUM_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_CSITE_SW_MASK                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L2_SOURCE_MASK_0_HSM_SHIFT                     MK_SHIFT_CONST(11)
+#define PMC_IMPL_L2_SOURCE_MASK_0_HSM_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_L2_SOURCE_MASK_0_HSM_SHIFT)
+#define PMC_IMPL_L2_SOURCE_MASK_0_HSM_RANGE                     11:11
+#define PMC_IMPL_L2_SOURCE_MASK_0_HSM_MSB                       MK_SHIFT_CONST(11)
+#define PMC_IMPL_L2_SOURCE_MASK_0_HSM_LSB                       MK_SHIFT_CONST(11)
+#define PMC_IMPL_L2_SOURCE_MASK_0_HSM_WOFFSET                   0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_HSM_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_HSM_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_HSM_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_HSM_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_HSM_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_HSM_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_HSM_INIT_ENUM                 UNMASK
+#define PMC_IMPL_L2_SOURCE_MASK_0_HSM_UNMASK                    MK_ENUM_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_HSM_MASK                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C0WDT_SHIFT                    MK_SHIFT_CONST(12)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C0WDT_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C0WDT_SHIFT)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C0WDT_RANGE                    12:12
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C0WDT_MSB                      MK_SHIFT_CONST(12)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C0WDT_LSB                      MK_SHIFT_CONST(12)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C0WDT_WOFFSET                  0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C0WDT_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C0WDT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C0WDT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C0WDT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C0WDT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C0WDT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C0WDT_INIT_ENUM                        UNMASK
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C0WDT_UNMASK                   MK_ENUM_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C0WDT_MASK                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C1WDT_SHIFT                    MK_SHIFT_CONST(13)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C1WDT_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C1WDT_SHIFT)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C1WDT_RANGE                    13:13
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C1WDT_MSB                      MK_SHIFT_CONST(13)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C1WDT_LSB                      MK_SHIFT_CONST(13)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C1WDT_WOFFSET                  0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C1WDT_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C1WDT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C1WDT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C1WDT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C1WDT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C1WDT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C1WDT_INIT_ENUM                        UNMASK
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C1WDT_UNMASK                   MK_ENUM_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C1WDT_MASK                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C2WDT_SHIFT                    MK_SHIFT_CONST(14)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C2WDT_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C2WDT_SHIFT)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C2WDT_RANGE                    14:14
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C2WDT_MSB                      MK_SHIFT_CONST(14)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C2WDT_LSB                      MK_SHIFT_CONST(14)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C2WDT_WOFFSET                  0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C2WDT_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C2WDT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C2WDT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C2WDT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C2WDT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C2WDT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C2WDT_INIT_ENUM                        UNMASK
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C2WDT_UNMASK                   MK_ENUM_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C2WDT_MASK                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C3WDT_SHIFT                    MK_SHIFT_CONST(15)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C3WDT_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C3WDT_SHIFT)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C3WDT_RANGE                    15:15
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C3WDT_MSB                      MK_SHIFT_CONST(15)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C3WDT_LSB                      MK_SHIFT_CONST(15)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C3WDT_WOFFSET                  0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C3WDT_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C3WDT_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C3WDT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C3WDT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C3WDT_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C3WDT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C3WDT_INIT_ENUM                        UNMASK
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C3WDT_UNMASK                   MK_ENUM_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R52C3WDT_MASK                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R5WDT_SHIFT                       MK_SHIFT_CONST(16)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R5WDT_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_L2_SOURCE_MASK_0_FSI_R5WDT_SHIFT)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R5WDT_RANGE                       16:16
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R5WDT_MSB                 MK_SHIFT_CONST(16)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R5WDT_LSB                 MK_SHIFT_CONST(16)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R5WDT_WOFFSET                     0x0
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R5WDT_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R5WDT_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R5WDT_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R5WDT_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R5WDT_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R5WDT_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R5WDT_INIT_ENUM                   UNMASK
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R5WDT_UNMASK                      MK_ENUM_CONST(0)
+#define PMC_IMPL_L2_SOURCE_MASK_0_FSI_R5WDT_MASK                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_RAMDUMP_CTL_STATUS2_0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0                  MK_ADDR_CONST(0x8e8)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_SECURE                   0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_DUAL                     0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_SCR                      RAMDUMP_COM2_SCR_0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_SCRREG                   PMC_IMPL_SCR_RAMDUMP_COM2_SCR_0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_WORD_COUNT                       0x1
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RAMDUMP_EN_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RAMDUMP_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RAMDUMP_EN_SHIFT)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RAMDUMP_EN_RANGE                 0:0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RAMDUMP_EN_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RAMDUMP_EN_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RAMDUMP_EN_WOFFSET                       0x0
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RAMDUMP_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RAMDUMP_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RAMDUMP_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RAMDUMP_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RAMDUMP_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RAMDUMP_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RAMDUMP_EN_INIT_ENUM                     DISABLE
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RAMDUMP_EN_ENABLE                        MK_ENUM_CONST(1)
+#define PMC_IMPL_RAMDUMP_CTL_STATUS2_0_RAMDUMP_EN_DISABLE                       MK_ENUM_CONST(0)
+
+
+// Register PMC_IMPL_IO_DPD_FSM0_STATUS_0
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0                   MK_ADDR_CONST(0xe000)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_SCR                       0
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_SCRREG                    0
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_FIELD                      MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_RANGE                      2:0
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_WOFFSET                    0x0
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_INIT_ENUM                  IDLE
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_IDLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_ASSERT_WAIT                        MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_ASSERT                     MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_DEASSERT_WAIT                      MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SYS_CSTATE_DEASSERT                   MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_SHIFT                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_FIELD                       MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_RANGE                       5:3
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_MSB                 MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_LSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_WOFFSET                     0x0
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_INIT_ENUM                   IDLE
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_IDLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_ASSERT_WAIT                 MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_ASSERT                      MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_DEASSERT_WAIT                       MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_AO_CSTATE_DEASSERT                    MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_SHIFT                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_FIELD                      MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_RANGE                      8:6
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_MSB                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_LSB                        MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_WOFFSET                    0x0
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_INIT_ENUM                  IDLE
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_IDLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_ASSERT_WAIT                        MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_ASSERT                     MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_DEASSERT_WAIT                      MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_DBG_CSTATE_DEASSERT                   MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_SHIFT                       MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_FIELD                       MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_RANGE                       11:9
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_MSB                 MK_SHIFT_CONST(11)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_LSB                 MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_WOFFSET                     0x0
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_INIT_ENUM                   IDLE
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_IDLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_ASSERT_WAIT                 MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_ASSERT                      MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_DEASSERT_WAIT                       MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G2_CSTATE_DEASSERT                    MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_SHIFT                       MK_SHIFT_CONST(12)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_FIELD                       MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_RANGE                       14:12
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_MSB                 MK_SHIFT_CONST(14)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_LSB                 MK_SHIFT_CONST(12)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_WOFFSET                     0x0
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_INIT_ENUM                   IDLE
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_IDLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_ASSERT_WAIT                 MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_ASSERT                      MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_DEASSERT_WAIT                       MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G3_CSTATE_DEASSERT                    MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_SHIFT                       MK_SHIFT_CONST(15)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_FIELD                       MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_RANGE                       17:15
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_MSB                 MK_SHIFT_CONST(17)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_LSB                 MK_SHIFT_CONST(15)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_WOFFSET                     0x0
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_INIT_ENUM                   IDLE
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_IDLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_ASSERT_WAIT                 MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_ASSERT                      MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_DEASSERT_WAIT                       MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G4_CSTATE_DEASSERT                    MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_SHIFT                       MK_SHIFT_CONST(18)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_FIELD                       MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_RANGE                       20:18
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_MSB                 MK_SHIFT_CONST(20)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_LSB                 MK_SHIFT_CONST(18)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_WOFFSET                     0x0
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_INIT_ENUM                   IDLE
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_IDLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_ASSERT_WAIT                 MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_ASSERT                      MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_DEASSERT_WAIT                       MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_G5_CSTATE_DEASSERT                    MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_SHIFT                        MK_SHIFT_CONST(21)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_FIELD                        MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_RANGE                        23:21
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_MSB                  MK_SHIFT_CONST(23)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_LSB                  MK_SHIFT_CONST(21)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_WOFFSET                      0x0
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_INIT_ENUM                    IDLE
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_IDLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_ASSERT_WAIT                  MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_ASSERT                       MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_DEASSERT_WAIT                        MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_SDMMC1_HV_CSTATE_DEASSERT                     MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_SHIFT                      MK_SHIFT_CONST(24)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_FIELD                      MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_RANGE                      26:24
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_MSB                        MK_SHIFT_CONST(26)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_LSB                        MK_SHIFT_CONST(24)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_WOFFSET                    0x0
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_INIT_ENUM                  IDLE
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_IDLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_ASSERT_WAIT                        MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_ASSERT                     MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_DEASSERT_WAIT                      MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_EDP_CSTATE_DEASSERT                   MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_SHIFT                      MK_SHIFT_CONST(27)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_FIELD                      MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_RANGE                      29:27
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_MSB                        MK_SHIFT_CONST(29)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_LSB                        MK_SHIFT_CONST(27)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_WOFFSET                    0x0
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_INIT_ENUM                  IDLE
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_IDLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_ASSERT_WAIT                        MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_ASSERT                     MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_DEASSERT_WAIT                      MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM0_STATUS_0_DPD_UFS_CSTATE_DEASSERT                   MK_ENUM_CONST(4)
+
+
+// Register PMC_IMPL_IO_DPD_FSM1_STATUS_0
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0                   MK_ADDR_CONST(0xe004)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_SCR                       0
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_SCRREG                    0
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x3fffffff)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_READ_MASK                         MK_MASK_CONST(0x3fffffff)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_FIELD                        MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_RANGE                        2:0
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_WOFFSET                      0x0
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_INIT_ENUM                    IDLE
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_IDLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_ASSERT_WAIT                  MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_ASSERT                       MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_DEASSERT_WAIT                        MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_A_CSTATE_DEASSERT                     MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_SHIFT                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_FIELD                     MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_RANGE                     5:3
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_MSB                       MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_LSB                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_WOFFSET                   0x0
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_INIT_ENUM                 IDLE
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_IDLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_ASSERT_WAIT                       MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_ASSERT                    MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_DEASSERT_WAIT                     MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_QSPI_CSTATE_DEASSERT                  MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_SHIFT                       MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_FIELD                       MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_RANGE                       8:6
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_MSB                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_LSB                 MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_WOFFSET                     0x0
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_INIT_ENUM                   IDLE
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_IDLE                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_ASSERT_WAIT                 MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_ASSERT                      MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_DEASSERT_WAIT                       MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_G7_CSTATE_DEASSERT                    MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_SHIFT                    MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_FIELD                    MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_RANGE                    11:9
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_MSB                      MK_SHIFT_CONST(11)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_LSB                      MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_WOFFSET                  0x0
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_DEFAULT_MASK                     MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_INIT_ENUM                        IDLE
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_IDLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_ASSERT_WAIT                      MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_ASSERT                   MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_DEASSERT_WAIT                    MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_AO_HV_CSTATE_DEASSERT                 MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_SHIFT                     MK_SHIFT_CONST(12)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_FIELD                     MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_RANGE                     14:12
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_MSB                       MK_SHIFT_CONST(14)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_LSB                       MK_SHIFT_CONST(12)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_WOFFSET                   0x0
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_INIT_ENUM                 IDLE
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_IDLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_ASSERT_WAIT                       MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_ASSERT                    MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_DEASSERT_WAIT                     MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_EQOS_CSTATE_DEASSERT                  MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_SHIFT                        MK_SHIFT_CONST(15)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_FIELD                        MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_RANGE                        17:15
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_MSB                  MK_SHIFT_CONST(17)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_LSB                  MK_SHIFT_CONST(15)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_WOFFSET                      0x0
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_INIT_ENUM                    IDLE
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_IDLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_ASSERT_WAIT                  MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_ASSERT                       MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_DEASSERT_WAIT                        MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_B_CSTATE_DEASSERT                     MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_SHIFT                        MK_SHIFT_CONST(18)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_FIELD                        MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_RANGE                        20:18
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_MSB                  MK_SHIFT_CONST(20)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_LSB                  MK_SHIFT_CONST(18)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_WOFFSET                      0x0
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_INIT_ENUM                    IDLE
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_IDLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_ASSERT_WAIT                  MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_ASSERT                       MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_DEASSERT_WAIT                        MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CTL_C_CSTATE_DEASSERT                     MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_SHIFT                        MK_SHIFT_CONST(21)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_FIELD                        MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_RANGE                        23:21
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_MSB                  MK_SHIFT_CONST(23)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_LSB                  MK_SHIFT_CONST(21)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_WOFFSET                      0x0
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_INIT_ENUM                    IDLE
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_IDLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_ASSERT_WAIT                  MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_ASSERT                       MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_DEASSERT_WAIT                        MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_C_CSTATE_DEASSERT                     MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_SHIFT                        MK_SHIFT_CONST(24)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_FIELD                        MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_RANGE                        26:24
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_MSB                  MK_SHIFT_CONST(26)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_LSB                  MK_SHIFT_CONST(24)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_WOFFSET                      0x0
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_INIT_ENUM                    IDLE
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_IDLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_ASSERT_WAIT                  MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_ASSERT                       MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_DEASSERT_WAIT                        MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_A_CSTATE_DEASSERT                     MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_SHIFT                        MK_SHIFT_CONST(27)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_FIELD                        MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_RANGE                        29:27
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_MSB                  MK_SHIFT_CONST(29)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_LSB                  MK_SHIFT_CONST(27)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_WOFFSET                      0x0
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_DEFAULT_MASK                 MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_INIT_ENUM                    IDLE
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_IDLE                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_ASSERT_WAIT                  MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_ASSERT                       MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_DEASSERT_WAIT                        MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM1_STATUS_0_DPD_PEX_CLK_B_CSTATE_DEASSERT                     MK_ENUM_CONST(4)
+
+
+// Register PMC_IMPL_IO_DPD_FSM2_STATUS_0
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0                   MK_ADDR_CONST(0xe008)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_SCR                       0
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_SCRREG                    0
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x1ff)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_READ_MASK                         MK_MASK_CONST(0x1ff)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_FIELD                      MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_RANGE                      2:0
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_WOFFSET                    0x0
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_DEFAULT_MASK                       MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_INIT_ENUM                  IDLE
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_IDLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_ASSERT_WAIT                        MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_ASSERT                     MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_DEASSERT_WAIT                      MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_CSI_CSTATE_DEASSERT                   MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_SHIFT                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_FIELD                     MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_RANGE                     5:3
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_MSB                       MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_LSB                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_WOFFSET                   0x0
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_INIT_ENUM                 IDLE
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_IDLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_ASSERT_WAIT                       MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_ASSERT                    MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_DEASSERT_WAIT                     MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_EMMC_CSTATE_DEASSERT                  MK_ENUM_CONST(4)
+
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_SHIFT                     MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_FIELD                     MK_FIELD_CONST(0x7, PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_SHIFT)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_RANGE                     8:6
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_MSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_LSB                       MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_WOFFSET                   0x0
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_DEFAULT_MASK                      MK_MASK_CONST(0x7)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_INIT_ENUM                 IDLE
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_IDLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_ASSERT_WAIT                       MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_ASSERT                    MK_ENUM_CONST(2)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_DEASSERT_WAIT                     MK_ENUM_CONST(3)
+#define PMC_IMPL_IO_DPD_FSM2_STATUS_0_DPD_DISP_CSTATE_DEASSERT                  MK_ENUM_CONST(4)
+
+
+// Reserved address 0xe00c
+
+// Reserved address 0xe010
+
+// Register PMC_IMPL_IO_SYS_DPD_REQ_0
+#define PMC_IMPL_IO_SYS_DPD_REQ_0                       MK_ADDR_CONST(0xe014)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SECURE                        0x0
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_DUAL                  0x0
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCR                   IO_SYS_SCR_0
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCRREG                        PMC_IMPL_SCR_IO_SYS_SCR_0
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_WORD_COUNT                    0x1
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_RESET_MASK                    MK_MASK_CONST(0xc00001ff)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_READ_MASK                     MK_MASK_CONST(0xc00001ff)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_WRITE_MASK                    MK_MASK_CONST(0xc00001ff)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_SHIFT                    MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_FIELD                    MK_FIELD_CONST(0x3, PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_RANGE                    31:30
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_MSB                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_LSB                      MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_WOFFSET                  0x0
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_IDLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_DPD_OFF                  MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_CODE_DPD_ON                   MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_RANGE                       0:0
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_WOFFSET                     0x0
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SCE_ERROR_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_RANGE                     1:1
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_WOFFSET                   0x0
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_VCOMP_ALERT_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_SHIFT                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_RANGE                      2:2
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_LSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_WOFFSET                    0x0
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO26_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_SHIFT                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_RANGE                      3:3
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_MSB                        MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_LSB                        MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_WOFFSET                    0x0
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_SOC_GPIO27_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_SHIFT                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_RANGE                  4:4
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_MSB                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_LSB                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_WOFFSET                        0x0
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_AO_RETENTION_N_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_SHIFT                 MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_RANGE                 5:5
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_MSB                   MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_LSB                   MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_WOFFSET                       0x0
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BATT_OC_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_SHIFT                     MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_RANGE                     6:6
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_MSB                       MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_LSB                       MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_WOFFSET                   0x0
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_BOOTV_CTL_N_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_SHIFT                        MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_RANGE                        7:7
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_MSB                  MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_LSB                  MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_WOFFSET                      0x0
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_POWER_ON_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_SHIFT                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_RANGE                        8:8
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_MSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_LSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_WOFFSET                      0x0
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_REQ_0_HDMI_CEC_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_SYS_DPD_STATUS_0
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0                    MK_ADDR_CONST(0xe018)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SECURE                     0x0
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_DUAL                       0x0
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCR                        IO_SYS_SCR_0
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCRREG                     PMC_IMPL_SCR_IO_SYS_SCR_0
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_WORD_COUNT                         0x1
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x1ff)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_READ_MASK                  MK_MASK_CONST(0x1ff)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_RANGE                    0:0
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_WOFFSET                  0x0
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SCE_ERROR_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_RANGE                  1:1
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_WOFFSET                        0x0
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_VCOMP_ALERT_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_RANGE                   2:2
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_WOFFSET                 0x0
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO26_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_SHIFT                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_RANGE                   3:3
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_MSB                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_LSB                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_WOFFSET                 0x0
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_SOC_GPIO27_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_SHIFT                       MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_RANGE                       4:4
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_MSB                 MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_LSB                 MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_WOFFSET                     0x0
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_AO_RETENTION_N_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_SHIFT                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_RANGE                      5:5
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_MSB                        MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_LSB                        MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_WOFFSET                    0x0
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BATT_OC_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_SHIFT                  MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_RANGE                  6:6
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_MSB                    MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_LSB                    MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_WOFFSET                        0x0
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_BOOTV_CTL_N_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_SHIFT                     MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_RANGE                     7:7
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_MSB                       MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_LSB                       MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_WOFFSET                   0x0
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_POWER_ON_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_SHIFT                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_RANGE                     8:8
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_MSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_LSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_WOFFSET                   0x0
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_STATUS_0_HDMI_CEC_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_SYS_DPD_OFF_MASK_0
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0                  MK_ADDR_CONST(0xe01c)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SECURE                   0x0
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_DUAL                     0x0
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCR                      IO_SYS_SCR_0
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCRREG                   PMC_IMPL_SCR_IO_SYS_SCR_0
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_WORD_COUNT                       0x1
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_RESET_VAL                        MK_MASK_CONST(0x1ff)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_RESET_MASK                       MK_MASK_CONST(0x1ff)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_READ_MASK                        MK_MASK_CONST(0x1ff)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_WRITE_MASK                       MK_MASK_CONST(0x1ff)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_RANGE                  0:0
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_WOFFSET                        0x0
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SCE_ERROR_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_RANGE                        1:1
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_WOFFSET                      0x0
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_VCOMP_ALERT_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_SHIFT                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_RANGE                 2:2
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_MSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_LSB                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_WOFFSET                       0x0
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO26_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_SHIFT                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_RANGE                 3:3
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_MSB                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_LSB                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_WOFFSET                       0x0
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_SOC_GPIO27_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_SHIFT                     MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_RANGE                     4:4
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_MSB                       MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_LSB                       MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_WOFFSET                   0x0
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_DEFAULT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_AO_RETENTION_N_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_SHIFT                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_RANGE                    5:5
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_MSB                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_LSB                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_WOFFSET                  0x0
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BATT_OC_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_SHIFT                        MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_RANGE                        6:6
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_MSB                  MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_LSB                  MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_WOFFSET                      0x0
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_BOOTV_CTL_N_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_SHIFT                   MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_RANGE                   7:7
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_MSB                     MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_LSB                     MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_WOFFSET                 0x0
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_POWER_ON_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_SHIFT                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_SHIFT)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_RANGE                   8:8
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_MSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_LSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_WOFFSET                 0x0
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SYS_DPD_OFF_MASK_0_HDMI_CEC_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_AO_DPD_REQ_0
+#define PMC_IMPL_IO_AO_DPD_REQ_0                        MK_ADDR_CONST(0xe020)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SECURE                         0x0
+#define PMC_IMPL_IO_AO_DPD_REQ_0_DUAL                   0x0
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SCR                    IO_AO_SCR_0
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SCRREG                         PMC_IMPL_SCR_IO_AO_SCR_0
+#define PMC_IMPL_IO_AO_DPD_REQ_0_WORD_COUNT                     0x1
+#define PMC_IMPL_IO_AO_DPD_REQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_RESET_MASK                     MK_MASK_CONST(0xc00007ff)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_READ_MASK                      MK_MASK_CONST(0xc00007ff)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_WRITE_MASK                     MK_MASK_CONST(0xc00007ff)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_SHIFT                     MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_IO_AO_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_RANGE                     31:30
+#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_LSB                       MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_WOFFSET                   0x0
+#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_IDLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_DPD_OFF                   MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_CODE_DPD_ON                    MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_RANGE                 0:0
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_WOFFSET                       0x0
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_SCK_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_RANGE                        1:1
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_WOFFSET                      0x0
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MISO_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_RANGE                        2:2
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_WOFFSET                      0x0
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_MOSI_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_SHIFT                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_RANGE                 3:3
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_MSB                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_LSB                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_WOFFSET                       0x0
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_SPI2_CS0_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_SHIFT                        MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_RANGE                        4:4
+#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_MSB                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_LSB                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_WOFFSET                      0x0
+#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_TOUCH_CLK_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_SHIFT                 MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_RANGE                 5:5
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_MSB                   MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_LSB                   MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_WOFFSET                       0x0
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_TX_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_SHIFT                 MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_RANGE                 6:6
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_MSB                   MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_LSB                   MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_WOFFSET                       0x0
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_UART3_RX_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_SHIFT                     MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_RANGE                     7:7
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_MSB                       MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_LSB                       MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_WOFFSET                   0x0
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SCL_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_SHIFT                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_RANGE                     8:8
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_MSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_LSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_WOFFSET                   0x0
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN2_I2C_SDA_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_SHIFT                     MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_RANGE                     9:9
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_MSB                       MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_LSB                       MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_WOFFSET                   0x0
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SCL_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_SHIFT                     MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_RANGE                     10:10
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_MSB                       MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_LSB                       MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_WOFFSET                   0x0
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_REQ_0_GEN8_I2C_SDA_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_AO_DPD_STATUS_0
+#define PMC_IMPL_IO_AO_DPD_STATUS_0                     MK_ADDR_CONST(0xe024)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SCR                         IO_AO_SCR_0
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SCRREG                      PMC_IMPL_SCR_IO_AO_SCR_0
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7ff)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7ff)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_RANGE                      0:0
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_WOFFSET                    0x0
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_SCK_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_RANGE                     1:1
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_WOFFSET                   0x0
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MISO_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_RANGE                     2:2
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_WOFFSET                   0x0
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_MOSI_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_SHIFT                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_RANGE                      3:3
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_MSB                        MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_LSB                        MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_WOFFSET                    0x0
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_SPI2_CS0_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_SHIFT                     MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_RANGE                     4:4
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_MSB                       MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_LSB                       MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_WOFFSET                   0x0
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_TOUCH_CLK_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_SHIFT                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_RANGE                      5:5
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_MSB                        MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_LSB                        MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_WOFFSET                    0x0
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_TX_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_SHIFT                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_RANGE                      6:6
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_MSB                        MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_LSB                        MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_WOFFSET                    0x0
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_UART3_RX_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_SHIFT                  MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_RANGE                  7:7
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_MSB                    MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_LSB                    MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_WOFFSET                        0x0
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SCL_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_SHIFT                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_RANGE                  8:8
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_MSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_LSB                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_WOFFSET                        0x0
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN2_I2C_SDA_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_SHIFT                  MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_RANGE                  9:9
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_MSB                    MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_LSB                    MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_WOFFSET                        0x0
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SCL_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_SHIFT                  MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_RANGE                  10:10
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_MSB                    MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_LSB                    MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_WOFFSET                        0x0
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_STATUS_0_GEN8_I2C_SDA_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_AO_DPD_OFF_MASK_0
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0                   MK_ADDR_CONST(0xe028)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SECURE                    0x0
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_DUAL                      0x0
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SCR                       IO_AO_SCR_0
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SCRREG                    PMC_IMPL_SCR_IO_AO_SCR_0
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_WORD_COUNT                        0x1
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_RESET_VAL                         MK_MASK_CONST(0x7ff)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_RESET_MASK                        MK_MASK_CONST(0x7ff)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_READ_MASK                         MK_MASK_CONST(0x7ff)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_WRITE_MASK                        MK_MASK_CONST(0x7ff)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_RANGE                    0:0
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_WOFFSET                  0x0
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_SCK_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_RANGE                   1:1
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_WOFFSET                 0x0
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MISO_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_RANGE                   2:2
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_WOFFSET                 0x0
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_MOSI_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_SHIFT                    MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_RANGE                    3:3
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_MSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_LSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_WOFFSET                  0x0
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_SPI2_CS0_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_SHIFT                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_RANGE                   4:4
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_MSB                     MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_LSB                     MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_WOFFSET                 0x0
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_TOUCH_CLK_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_SHIFT                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_RANGE                    5:5
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_MSB                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_LSB                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_WOFFSET                  0x0
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_TX_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_SHIFT                    MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_RANGE                    6:6
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_MSB                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_LSB                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_WOFFSET                  0x0
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_DEFAULT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_UART3_RX_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_SHIFT                        MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_RANGE                        7:7
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_MSB                  MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_LSB                  MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_WOFFSET                      0x0
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SCL_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_SHIFT                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_RANGE                        8:8
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_MSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_LSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_WOFFSET                      0x0
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN2_I2C_SDA_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_SHIFT                        MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_RANGE                        9:9
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_MSB                  MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_LSB                  MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_WOFFSET                      0x0
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SCL_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_SHIFT                        MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_SHIFT)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_RANGE                        10:10
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_MSB                  MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_LSB                  MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_WOFFSET                      0x0
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_DPD_OFF_MASK_0_GEN8_I2C_SDA_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_DBG_DPD_REQ_0
+#define PMC_IMPL_IO_DBG_DPD_REQ_0                       MK_ADDR_CONST(0xe02c)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SECURE                        0x0
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_DUAL                  0x0
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SCR                   IO_DBG_SCR_0
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SCRREG                        PMC_IMPL_SCR_IO_DBG_SCR_0
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_WORD_COUNT                    0x1
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_RESET_MASK                    MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_READ_MASK                     MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_WRITE_MASK                    MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_SHIFT                    MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_FIELD                    MK_FIELD_CONST(0x3, PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_RANGE                    31:30
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_MSB                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_LSB                      MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_WOFFSET                  0x0
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_IDLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_DPD_OFF                  MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_CODE_DPD_ON                   MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_SHIFT)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_RANGE                      0:0
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_WOFFSET                    0x0
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DBG_DPD_REQ_0_SOC_GPIO08_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_DBG_DPD_STATUS_0
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0                    MK_ADDR_CONST(0xe030)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SECURE                     0x0
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_DUAL                       0x0
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SCR                        IO_DBG_SCR_0
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SCRREG                     PMC_IMPL_SCR_IO_DBG_SCR_0
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_WORD_COUNT                         0x1
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_SHIFT)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_RANGE                   0:0
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_WOFFSET                 0x0
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DBG_DPD_STATUS_0_SOC_GPIO08_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_G2_DPD_REQ_0
+#define PMC_IMPL_IO_G2_DPD_REQ_0                        MK_ADDR_CONST(0xe034)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_SECURE                         0x0
+#define PMC_IMPL_IO_G2_DPD_REQ_0_DUAL                   0x0
+#define PMC_IMPL_IO_G2_DPD_REQ_0_SCR                    IO_G2_SCR_0
+#define PMC_IMPL_IO_G2_DPD_REQ_0_SCRREG                         PMC_IMPL_SCR_IO_G2_SCR_0
+#define PMC_IMPL_IO_G2_DPD_REQ_0_WORD_COUNT                     0x1
+#define PMC_IMPL_IO_G2_DPD_REQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_RESET_MASK                     MK_MASK_CONST(0xc000007f)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_READ_MASK                      MK_MASK_CONST(0xc000007f)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_WRITE_MASK                     MK_MASK_CONST(0xc000007f)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_SHIFT                     MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_IO_G2_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_RANGE                     31:30
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_LSB                       MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_WOFFSET                   0x0
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_IDLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_DPD_OFF                   MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CODE_DPD_ON                    MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_SHIFT)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_RANGE                      0:0
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_WOFFSET                    0x0
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GPU_PWR_REQ_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_SHIFT                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_SHIFT)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_RANGE                       1:1
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_MSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_LSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_WOFFSET                     0x0
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_CV_PWR_REQ_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_SHIFT)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_RANGE                  2:2
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_WOFFSET                        0x0
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM2_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_SHIFT                  MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_SHIFT)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_RANGE                  3:3
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_MSB                    MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_LSB                    MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_WOFFSET                        0x0
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_GP_PWM3_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_SHIFT                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_REQ_0_UART2_SHIFT)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_RANGE                    4:4
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_MSB                      MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_LSB                      MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_WOFFSET                  0x0
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART2_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_SHIFT                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_REQ_0_UART5_SHIFT)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_RANGE                    5:5
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_MSB                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_LSB                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_WOFFSET                  0x0
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_UART5_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_SHIFT                       MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_REQ_0_G2_SHIFT)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_RANGE                       6:6
+#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_MSB                 MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_LSB                 MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_WOFFSET                     0x0
+#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_REQ_0_G2_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_G2_DPD_STATUS_0
+#define PMC_IMPL_IO_G2_DPD_STATUS_0                     MK_ADDR_CONST(0xe038)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_SCR                         IO_G2_SCR_0
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_SCRREG                      PMC_IMPL_SCR_IO_G2_SCR_0
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x7f)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_READ_MASK                   MK_MASK_CONST(0x7f)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_SHIFT)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_RANGE                   0:0
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_WOFFSET                 0x0
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GPU_PWR_REQ_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_SHIFT)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_RANGE                    1:1
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_WOFFSET                  0x0
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_CV_PWR_REQ_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_SHIFT                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_SHIFT)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_RANGE                       2:2
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_MSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_LSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_WOFFSET                     0x0
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM2_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_SHIFT                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_SHIFT)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_RANGE                       3:3
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_MSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_LSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_WOFFSET                     0x0
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_GP_PWM3_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_SHIFT                 MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_SHIFT)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_RANGE                 4:4
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_MSB                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_LSB                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_WOFFSET                       0x0
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART2_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_SHIFT                 MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_SHIFT)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_RANGE                 5:5
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_MSB                   MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_LSB                   MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_WOFFSET                       0x0
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_UART5_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_SHIFT                    MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G2_DPD_STATUS_0_G2_SHIFT)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_RANGE                    6:6
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_MSB                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_LSB                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_WOFFSET                  0x0
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G2_DPD_STATUS_0_G2_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_G3_DPD_REQ_0
+#define PMC_IMPL_IO_G3_DPD_REQ_0                        MK_ADDR_CONST(0xe03c)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SECURE                         0x0
+#define PMC_IMPL_IO_G3_DPD_REQ_0_DUAL                   0x0
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SCR                    IO_G3_SCR_0
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SCRREG                         PMC_IMPL_SCR_IO_G3_SCR_0
+#define PMC_IMPL_IO_G3_DPD_REQ_0_WORD_COUNT                     0x1
+#define PMC_IMPL_IO_G3_DPD_REQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_RESET_MASK                     MK_MASK_CONST(0xc000000f)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_READ_MASK                      MK_MASK_CONST(0xc000000f)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_WRITE_MASK                     MK_MASK_CONST(0xc000000f)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_SHIFT                     MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_IO_G3_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_RANGE                     31:30
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_LSB                       MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_WOFFSET                   0x0
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_IDLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_DPD_OFF                   MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CODE_DPD_ON                    MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_SHIFT)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_RANGE                      0:0
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_WOFFSET                    0x0
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SCL_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_SHIFT)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_RANGE                      1:1
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_WOFFSET                    0x0
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_CAM_I2C_SDA_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_SHIFT                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_SHIFT)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_RANGE                       2:2
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_MSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_LSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_WOFFSET                     0x0
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_SOC_GPIO23_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_SHIFT                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G3_DPD_REQ_0_G3_SHIFT)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_RANGE                       3:3
+#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_MSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_LSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_WOFFSET                     0x0
+#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G3_DPD_REQ_0_G3_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_G3_DPD_STATUS_0
+#define PMC_IMPL_IO_G3_DPD_STATUS_0                     MK_ADDR_CONST(0xe040)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SCR                         IO_G3_SCR_0
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SCRREG                      PMC_IMPL_SCR_IO_G3_SCR_0
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_SHIFT)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_RANGE                   0:0
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_WOFFSET                 0x0
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SCL_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_SHIFT)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_RANGE                   1:1
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_WOFFSET                 0x0
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_CAM_I2C_SDA_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_SHIFT                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_SHIFT)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_RANGE                    2:2
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_MSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_LSB                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_WOFFSET                  0x0
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_SOC_GPIO23_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_SHIFT                    MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G3_DPD_STATUS_0_G3_SHIFT)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_RANGE                    3:3
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_MSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_LSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_WOFFSET                  0x0
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G3_DPD_STATUS_0_G3_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_G4_DPD_REQ_0
+#define PMC_IMPL_IO_G4_DPD_REQ_0                        MK_ADDR_CONST(0xe044)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SECURE                         0x0
+#define PMC_IMPL_IO_G4_DPD_REQ_0_DUAL                   0x0
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SCR                    IO_G4_SCR_0
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SCRREG                         PMC_IMPL_SCR_IO_G4_SCR_0
+#define PMC_IMPL_IO_G4_DPD_REQ_0_WORD_COUNT                     0x1
+#define PMC_IMPL_IO_G4_DPD_REQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_RESET_MASK                     MK_MASK_CONST(0xc000003f)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_READ_MASK                      MK_MASK_CONST(0xc000003f)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_WRITE_MASK                     MK_MASK_CONST(0xc000003f)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_SHIFT                     MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_IO_G4_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_RANGE                     31:30
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_LSB                       MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_WOFFSET                   0x0
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_IDLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_DPD_OFF                   MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CODE_DPD_ON                    MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_SHIFT)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_RANGE                       0:0
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_WOFFSET                     0x0
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_SOC_GPIO14_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_SHIFT)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_RANGE                  1:1
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_WOFFSET                        0x0
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM7_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_SHIFT                      MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_SHIFT)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_RANGE                      2:2
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_MSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_LSB                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_WOFFSET                    0x0
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_CPU_PWR_REQ_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_SHIFT                  MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_SHIFT)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_RANGE                  3:3
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_MSB                    MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_LSB                    MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_WOFFSET                        0x0
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM6_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_SHIFT                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_SHIFT)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_RANGE                  4:4
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_MSB                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_LSB                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_WOFFSET                        0x0
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_GP_PWM5_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_SHIFT                       MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_REQ_0_G4_SHIFT)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_RANGE                       5:5
+#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_MSB                 MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_LSB                 MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_WOFFSET                     0x0
+#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_REQ_0_G4_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_G4_DPD_STATUS_0
+#define PMC_IMPL_IO_G4_DPD_STATUS_0                     MK_ADDR_CONST(0xe048)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SCR                         IO_G4_SCR_0
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SCRREG                      PMC_IMPL_SCR_IO_G4_SCR_0
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x3f)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_READ_MASK                   MK_MASK_CONST(0x3f)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_SHIFT)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_RANGE                    0:0
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_WOFFSET                  0x0
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_SOC_GPIO14_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_SHIFT                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_SHIFT)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_RANGE                       1:1
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_MSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_LSB                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_WOFFSET                     0x0
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM7_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_SHIFT)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_RANGE                   2:2
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_WOFFSET                 0x0
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_CPU_PWR_REQ_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_SHIFT                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_SHIFT)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_RANGE                       3:3
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_MSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_LSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_WOFFSET                     0x0
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM6_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_SHIFT                       MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_SHIFT)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_RANGE                       4:4
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_MSB                 MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_LSB                 MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_WOFFSET                     0x0
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_GP_PWM5_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_SHIFT                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G4_DPD_STATUS_0_G4_SHIFT)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_RANGE                    5:5
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_MSB                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_LSB                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_WOFFSET                  0x0
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G4_DPD_STATUS_0_G4_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_G5_DPD_REQ_0
+#define PMC_IMPL_IO_G5_DPD_REQ_0                        MK_ADDR_CONST(0xe04c)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_SECURE                         0x0
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DUAL                   0x0
+#define PMC_IMPL_IO_G5_DPD_REQ_0_SCR                    IO_G5_SCR_0
+#define PMC_IMPL_IO_G5_DPD_REQ_0_SCRREG                         PMC_IMPL_SCR_IO_G5_SCR_0
+#define PMC_IMPL_IO_G5_DPD_REQ_0_WORD_COUNT                     0x1
+#define PMC_IMPL_IO_G5_DPD_REQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_RESET_MASK                     MK_MASK_CONST(0xc0000003)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_READ_MASK                      MK_MASK_CONST(0xc0000003)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_WRITE_MASK                     MK_MASK_CONST(0xc0000003)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_SHIFT                     MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_IO_G5_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_RANGE                     31:30
+#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_LSB                       MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_WOFFSET                   0x0
+#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_IDLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_DPD_OFF                   MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_CODE_DPD_ON                    MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_SHIFT)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_RANGE                     0:0
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_WOFFSET                   0x0
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP4_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_SHIFT)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_RANGE                     1:1
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_WOFFSET                   0x0
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G5_DPD_REQ_0_DAP6_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_G5_DPD_STATUS_0
+#define PMC_IMPL_IO_G5_DPD_STATUS_0                     MK_ADDR_CONST(0xe050)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_SCR                         IO_G5_SCR_0
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_SCRREG                      PMC_IMPL_SCR_IO_G5_SCR_0
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_RESET_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_READ_MASK                   MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_SHIFT)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_RANGE                  0:0
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_WOFFSET                        0x0
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP4_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_SHIFT)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_RANGE                  1:1
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_WOFFSET                        0x0
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G5_DPD_STATUS_0_DAP6_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0                 MK_ADDR_CONST(0xe054)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SECURE                  0x0
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_DUAL                    0x0
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SCR                     IO_SDMMC1_HV_SCR_0
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SCRREG                  PMC_IMPL_SCR_IO_SDMMC1_HV_SCR_0
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_WORD_COUNT                      0x1
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_RESET_MASK                      MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_READ_MASK                       MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_WRITE_MASK                      MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_SHIFT                      MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_FIELD                      MK_FIELD_CONST(0x3, PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_RANGE                      31:30
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_LSB                        MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_WOFFSET                    0x0
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_IDLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_DPD_OFF                    MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_CODE_DPD_ON                     MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_SHIFT)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_RANGE                    0:0
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_WOFFSET                  0x0
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0_SDMMC1_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0                      MK_ADDR_CONST(0xe058)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SECURE                       0x0
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_DUAL                         0x0
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SCR                  IO_SDMMC1_HV_SCR_0
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SCRREG                       PMC_IMPL_SCR_IO_SDMMC1_HV_SCR_0
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_WORD_COUNT                   0x1
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_SHIFT)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_RANGE                 0:0
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_WOFFSET                       0x0
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0_SDMMC1_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_EDP_DPD_REQ_0
+#define PMC_IMPL_IO_EDP_DPD_REQ_0                       MK_ADDR_CONST(0xe05c)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_SECURE                        0x0
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_DUAL                  0x0
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_SCR                   IO_EDP_SCR_0
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_SCRREG                        PMC_IMPL_SCR_IO_EDP_SCR_0
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_WORD_COUNT                    0x1
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_RESET_MASK                    MK_MASK_CONST(0xc0000003)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_READ_MASK                     MK_MASK_CONST(0xc0000003)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_WRITE_MASK                    MK_MASK_CONST(0xc0000003)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_SHIFT                    MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_FIELD                    MK_FIELD_CONST(0x3, PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_RANGE                    31:30
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_MSB                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_LSB                      MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_WOFFSET                  0x0
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_IDLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_DPD_OFF                  MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_CODE_DPD_ON                   MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_SHIFT)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_RANGE                 0:0
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_WOFFSET                       0x0
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_GP_PWM1_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_SHIFT)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_RANGE                     1:1
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_WOFFSET                   0x0
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_EDP_DPD_REQ_0_EDP_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_EDP_DPD_STATUS_0
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0                    MK_ADDR_CONST(0xe060)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_SECURE                     0x0
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_DUAL                       0x0
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_SCR                        IO_EDP_SCR_0
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_SCRREG                     PMC_IMPL_SCR_IO_EDP_SCR_0
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_WORD_COUNT                         0x1
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_SHIFT)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_RANGE                      0:0
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_WOFFSET                    0x0
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_GP_PWM1_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_SHIFT)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_RANGE                  1:1
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_WOFFSET                        0x0
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_EDP_DPD_STATUS_0_EDP_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_UFS_DPD_REQ_0
+#define PMC_IMPL_IO_UFS_DPD_REQ_0                       MK_ADDR_CONST(0xe064)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_SECURE                        0x0
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_DUAL                  0x0
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_SCR                   IO_UFS_SCR_0
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_SCRREG                        PMC_IMPL_SCR_IO_UFS_SCR_0
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_WORD_COUNT                    0x1
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_RESET_MASK                    MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_READ_MASK                     MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_WRITE_MASK                    MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_SHIFT                    MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_FIELD                    MK_FIELD_CONST(0x3, PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_RANGE                    31:30
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_MSB                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_LSB                      MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_WOFFSET                  0x0
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_IDLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_DPD_OFF                  MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_CODE_DPD_ON                   MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_SHIFT)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_RANGE                     0:0
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_WOFFSET                   0x0
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_UFS_DPD_REQ_0_UFS_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_UFS_DPD_STATUS_0
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0                    MK_ADDR_CONST(0xe068)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_SECURE                     0x0
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_DUAL                       0x0
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_SCR                        IO_UFS_SCR_0
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_SCRREG                     PMC_IMPL_SCR_IO_UFS_SCR_0
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_WORD_COUNT                         0x1
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_SHIFT)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_RANGE                  0:0
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_WOFFSET                        0x0
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_UFS_DPD_STATUS_0_UFS_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0                 MK_ADDR_CONST(0xe06c)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_SECURE                  0x0
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_DUAL                    0x0
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_SCR                     IO_PEX_CTL_A_SCR_0
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_SCRREG                  PMC_IMPL_SCR_IO_PEX_CTL_A_SCR_0
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_WORD_COUNT                      0x1
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_RESET_MASK                      MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_READ_MASK                       MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_WRITE_MASK                      MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_SHIFT                      MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_FIELD                      MK_FIELD_CONST(0x3, PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_RANGE                      31:30
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_LSB                        MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_WOFFSET                    0x0
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_IDLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_DPD_OFF                    MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_CODE_DPD_ON                     MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_SHIFT)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_RANGE                   0:0
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_WOFFSET                 0x0
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0_PEX_CTL_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0                      MK_ADDR_CONST(0xe070)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_SECURE                       0x0
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_DUAL                         0x0
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_SCR                  IO_PEX_CTL_A_SCR_0
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_SCRREG                       PMC_IMPL_SCR_IO_PEX_CTL_A_SCR_0
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_WORD_COUNT                   0x1
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_SHIFT)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_RANGE                        0:0
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_WOFFSET                      0x0
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0_PEX_CTL_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_QSPI_DPD_REQ_0
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0                      MK_ADDR_CONST(0xe074)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_SECURE                       0x0
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_DUAL                         0x0
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_SCR                  IO_QSPI_SCR_0
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_SCRREG                       PMC_IMPL_SCR_IO_QSPI_SCR_0
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_WORD_COUNT                   0x1
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_RESET_MASK                   MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_READ_MASK                    MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_WRITE_MASK                   MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_SHIFT                   MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_FIELD                   MK_FIELD_CONST(0x3, PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_RANGE                   31:30
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_MSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_LSB                     MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_WOFFSET                 0x0
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_IDLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_DPD_OFF                 MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_CODE_DPD_ON                  MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_SHIFT)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_RANGE                   0:0
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_WOFFSET                 0x0
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_QSPI_DPD_REQ_0_QSPI_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_QSPI_DPD_STATUS_0
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0                   MK_ADDR_CONST(0xe078)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_SCR                       IO_QSPI_SCR_0
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_SCRREG                    PMC_IMPL_SCR_IO_QSPI_SCR_0
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_SHIFT)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_RANGE                        0:0
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_WOFFSET                      0x0
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_QSPI_DPD_STATUS_0_QSPI_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_G7_DPD_REQ_0
+#define PMC_IMPL_IO_G7_DPD_REQ_0                        MK_ADDR_CONST(0xe07c)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SECURE                         0x0
+#define PMC_IMPL_IO_G7_DPD_REQ_0_DUAL                   0x0
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SCR                    IO_G7_SCR_0
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SCRREG                         PMC_IMPL_SCR_IO_G7_SCR_0
+#define PMC_IMPL_IO_G7_DPD_REQ_0_WORD_COUNT                     0x1
+#define PMC_IMPL_IO_G7_DPD_REQ_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_RESET_MASK                     MK_MASK_CONST(0xc000000f)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_READ_MASK                      MK_MASK_CONST(0xc000000f)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_WRITE_MASK                     MK_MASK_CONST(0xc000000f)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_SHIFT                     MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_FIELD                     MK_FIELD_CONST(0x3, PMC_IMPL_IO_G7_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_RANGE                     31:30
+#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_MSB                       MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_LSB                       MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_WOFFSET                   0x0
+#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_IDLE                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_DPD_OFF                   MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_CODE_DPD_ON                    MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_SHIFT)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_RANGE                       0:0
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_WOFFSET                     0x0
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SOC_GPIO57_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_SHIFT)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_RANGE                     1:1
+#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_WOFFSET                   0x0
+#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_DAP1_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_SHIFT)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_RANGE                     2:2
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_WOFFSET                   0x0
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_SPI5_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_SHIFT                       MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_G7_DPD_REQ_0_G7_SHIFT)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_RANGE                       3:3
+#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_MSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_LSB                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_WOFFSET                     0x0
+#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G7_DPD_REQ_0_G7_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_G7_DPD_STATUS_0
+#define PMC_IMPL_IO_G7_DPD_STATUS_0                     MK_ADDR_CONST(0xe080)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SECURE                      0x0
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_DUAL                        0x0
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SCR                         IO_G7_SCR_0
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SCRREG                      PMC_IMPL_SCR_IO_G7_SCR_0
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_WORD_COUNT                  0x1
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_RESET_MASK                  MK_MASK_CONST(0xf)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_READ_MASK                   MK_MASK_CONST(0xf)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_SHIFT)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_RANGE                    0:0
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_WOFFSET                  0x0
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SOC_GPIO57_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_SHIFT)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_RANGE                  1:1
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_WOFFSET                        0x0
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_DAP1_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_SHIFT)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_RANGE                  2:2
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_WOFFSET                        0x0
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_SPI5_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_SHIFT                    MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_G7_DPD_STATUS_0_G7_SHIFT)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_RANGE                    3:3
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_MSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_LSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_WOFFSET                  0x0
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_G7_DPD_STATUS_0_G7_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_AO_HV_DPD_REQ_0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0                     MK_ADDR_CONST(0xe084)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SECURE                      0x0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_DUAL                        0x0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SCR                         IO_AO_HV_SCR_0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SCRREG                      PMC_IMPL_SCR_IO_AO_HV_SCR_0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_WORD_COUNT                  0x1
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_RESET_MASK                  MK_MASK_CONST(0xc0000fff)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_READ_MASK                   MK_MASK_CONST(0xc0000fff)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_WRITE_MASK                  MK_MASK_CONST(0xc0000fff)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_SHIFT                  MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_FIELD                  MK_FIELD_CONST(0x3, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_RANGE                  31:30
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_MSB                    MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_LSB                    MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_WOFFSET                        0x0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_DEFAULT_MASK                   MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_IDLE                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_DPD_OFF                        MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CODE_DPD_ON                 MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_RANGE                     0:0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_WOFFSET                   0x0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DOUT_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_RANGE                      1:1
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_WOFFSET                    0x0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_DIN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_SHIFT                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_RANGE                     2:2
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_MSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_LSB                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_WOFFSET                   0x0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DOUT_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_SHIFT                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_RANGE                      3:3
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_MSB                        MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_LSB                        MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_WOFFSET                    0x0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_DIN_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_SHIFT                      MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_RANGE                      4:4
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_MSB                        MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_LSB                        MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_WOFFSET                    0x0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_STB_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_SHIFT                       MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_RANGE                       5:5
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_MSB                 MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_LSB                 MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_WOFFSET                     0x0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_EN_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_SHIFT                    MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_RANGE                    6:6
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_MSB                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_LSB                      MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_WOFFSET                  0x0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO49_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_SHIFT                      MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_RANGE                      7:7
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_MSB                        MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_LSB                        MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_WOFFSET                    0x0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN0_ERR_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_SHIFT                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_RANGE                      8:8
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_MSB                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_LSB                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_WOFFSET                    0x0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_STB_ON                 MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_SHIFT                       MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_RANGE                       9:9
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_MSB                 MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_LSB                 MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_WOFFSET                     0x0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_EN_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_SHIFT                    MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_RANGE                    10:10
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_MSB                      MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_LSB                      MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_WOFFSET                  0x0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_SOC_GPIO50_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_SHIFT                      MK_SHIFT_CONST(11)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_RANGE                      11:11
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_MSB                        MK_SHIFT_CONST(11)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_LSB                        MK_SHIFT_CONST(11)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_WOFFSET                    0x0
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_REQ_0_CAN1_ERR_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_AO_HV_DPD_STATUS_0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0                  MK_ADDR_CONST(0xe088)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SECURE                   0x0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_DUAL                     0x0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SCR                      IO_AO_HV_SCR_0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SCRREG                   PMC_IMPL_SCR_IO_AO_HV_SCR_0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_WORD_COUNT                       0x1
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_RESET_MASK                       MK_MASK_CONST(0xfff)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_READ_MASK                        MK_MASK_CONST(0xfff)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_RANGE                  0:0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_WOFFSET                        0x0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DOUT_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_RANGE                   1:1
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_WOFFSET                 0x0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_DIN_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_RANGE                  2:2
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_WOFFSET                        0x0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DOUT_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_SHIFT                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_RANGE                   3:3
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_MSB                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_LSB                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_WOFFSET                 0x0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_DIN_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_SHIFT                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_RANGE                   4:4
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_MSB                     MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_LSB                     MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_WOFFSET                 0x0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_STB_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_SHIFT                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_RANGE                    5:5
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_MSB                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_LSB                      MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_WOFFSET                  0x0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_SHIFT                 MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_RANGE                 6:6
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_MSB                   MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_LSB                   MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_WOFFSET                       0x0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO49_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_SHIFT                   MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_RANGE                   7:7
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_MSB                     MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_LSB                     MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_WOFFSET                 0x0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN0_ERR_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_SHIFT                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_RANGE                   8:8
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_MSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_LSB                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_WOFFSET                 0x0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_STB_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_SHIFT                    MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_RANGE                    9:9
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_MSB                      MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_LSB                      MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_WOFFSET                  0x0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_EN_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_SHIFT                 MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_RANGE                 10:10
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_MSB                   MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_LSB                   MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_WOFFSET                       0x0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_SOC_GPIO50_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_SHIFT                   MK_SHIFT_CONST(11)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_RANGE                   11:11
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_MSB                     MK_SHIFT_CONST(11)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_LSB                     MK_SHIFT_CONST(11)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_WOFFSET                 0x0
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_STATUS_0_CAN1_ERR_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0                        MK_ADDR_CONST(0xe08c)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SECURE                         0x0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_DUAL                   0x0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SCR                    IO_AO_HV_SCR_0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SCRREG                         PMC_IMPL_SCR_IO_AO_HV_SCR_0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_WORD_COUNT                     0x1
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_RESET_VAL                      MK_MASK_CONST(0xfff)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_RESET_MASK                     MK_MASK_CONST(0xfff)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_READ_MASK                      MK_MASK_CONST(0xfff)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_WRITE_MASK                     MK_MASK_CONST(0xfff)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_RANGE                        0:0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_WOFFSET                      0x0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DOUT_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_RANGE                 1:1
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_WOFFSET                       0x0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_DIN_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_RANGE                        2:2
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_WOFFSET                      0x0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DOUT_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_SHIFT                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_RANGE                 3:3
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_MSB                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_LSB                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_WOFFSET                       0x0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_DIN_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_SHIFT                 MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_RANGE                 4:4
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_MSB                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_LSB                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_WOFFSET                       0x0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_STB_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_SHIFT                  MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_RANGE                  5:5
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_MSB                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_LSB                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_WOFFSET                        0x0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_EN_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_SHIFT                       MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_RANGE                       6:6
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_MSB                 MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_LSB                 MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_WOFFSET                     0x0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO49_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_SHIFT                 MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_RANGE                 7:7
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_MSB                   MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_LSB                   MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_WOFFSET                       0x0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN0_ERR_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_SHIFT                 MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_RANGE                 8:8
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_MSB                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_LSB                   MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_WOFFSET                       0x0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_STB_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_SHIFT                  MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_RANGE                  9:9
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_MSB                    MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_LSB                    MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_WOFFSET                        0x0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_DEFAULT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_EN_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_SHIFT                       MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_RANGE                       10:10
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_MSB                 MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_LSB                 MK_SHIFT_CONST(10)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_WOFFSET                     0x0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_DEFAULT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_SOC_GPIO50_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_SHIFT                 MK_SHIFT_CONST(11)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_SHIFT)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_RANGE                 11:11
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_MSB                   MK_SHIFT_CONST(11)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_LSB                   MK_SHIFT_CONST(11)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_WOFFSET                       0x0
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0_CAN1_ERR_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_EQOS_DPD_REQ_0
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0                      MK_ADDR_CONST(0xe090)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_SECURE                       0x0
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_DUAL                         0x0
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_SCR                  IO_EQOS_SCR_0
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_SCRREG                       PMC_IMPL_SCR_IO_EQOS_SCR_0
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_WORD_COUNT                   0x1
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_RESET_MASK                   MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_READ_MASK                    MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_WRITE_MASK                   MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_SHIFT                   MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_FIELD                   MK_FIELD_CONST(0x3, PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_RANGE                   31:30
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_MSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_LSB                     MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_WOFFSET                 0x0
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_IDLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_DPD_OFF                 MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_CODE_DPD_ON                  MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_SHIFT)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_RANGE                   0:0
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_WOFFSET                 0x0
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_EQOS_DPD_REQ_0_EQOS_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_EQOS_DPD_STATUS_0
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0                   MK_ADDR_CONST(0xe094)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_SCR                       IO_EQOS_SCR_0
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_SCRREG                    PMC_IMPL_SCR_IO_EQOS_SCR_0
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_SHIFT)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_RANGE                        0:0
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_WOFFSET                      0x0
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_EQOS_DPD_STATUS_0_EQOS_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0                 MK_ADDR_CONST(0xe098)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_SECURE                  0x0
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_DUAL                    0x0
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_SCR                     IO_PEX_CTL_B_SCR_0
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_SCRREG                  PMC_IMPL_SCR_IO_PEX_CTL_B_SCR_0
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_WORD_COUNT                      0x1
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_RESET_MASK                      MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_READ_MASK                       MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_WRITE_MASK                      MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_SHIFT                      MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_FIELD                      MK_FIELD_CONST(0x3, PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_RANGE                      31:30
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_LSB                        MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_WOFFSET                    0x0
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_IDLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_DPD_OFF                    MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_CODE_DPD_ON                     MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_SHIFT)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_RANGE                 0:0
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_WOFFSET                       0x0
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0_PEX_CTL_2_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0                      MK_ADDR_CONST(0xe09c)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_SECURE                       0x0
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_DUAL                         0x0
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_SCR                  IO_PEX_CTL_B_SCR_0
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_SCRREG                       PMC_IMPL_SCR_IO_PEX_CTL_B_SCR_0
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_WORD_COUNT                   0x1
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_SHIFT)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_RANGE                      0:0
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_WOFFSET                    0x0
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0_PEX_CTL_2_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0                 MK_ADDR_CONST(0xe0a0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_SECURE                  0x0
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_DUAL                    0x0
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_SCR                     IO_PEX_CTL_C_SCR_0
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_SCRREG                  PMC_IMPL_SCR_IO_PEX_CTL_C_SCR_0
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_WORD_COUNT                      0x1
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_RESET_MASK                      MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_READ_MASK                       MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_WRITE_MASK                      MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_SHIFT                      MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_FIELD                      MK_FIELD_CONST(0x3, PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_RANGE                      31:30
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_LSB                        MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_WOFFSET                    0x0
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_IDLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_DPD_OFF                    MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_CODE_DPD_ON                     MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_SHIFT)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_RANGE                 0:0
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_WOFFSET                       0x0
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0_PEX_CTL_3_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0                      MK_ADDR_CONST(0xe0a4)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_SECURE                       0x0
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_DUAL                         0x0
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_SCR                  IO_PEX_CTL_C_SCR_0
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_SCRREG                       PMC_IMPL_SCR_IO_PEX_CTL_C_SCR_0
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_WORD_COUNT                   0x1
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_READ_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_SHIFT                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_SHIFT)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_RANGE                      0:0
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_MSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_LSB                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_WOFFSET                    0x0
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0_PEX_CTL_3_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0                 MK_ADDR_CONST(0xe0a8)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_SECURE                  0x0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_DUAL                    0x0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_SCR                     IO_PEX_CLK_C_SCR_0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_SCRREG                  PMC_IMPL_SCR_IO_PEX_CLK_C_SCR_0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_WORD_COUNT                      0x1
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_RESET_MASK                      MK_MASK_CONST(0xc000000f)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_READ_MASK                       MK_MASK_CONST(0xc000000f)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_WRITE_MASK                      MK_MASK_CONST(0xc000000f)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_SHIFT                      MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_FIELD                      MK_FIELD_CONST(0x3, PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_RANGE                      31:30
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_LSB                        MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_WOFFSET                    0x0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_IDLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_DPD_OFF                    MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_CODE_DPD_ON                     MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_RANGE                  0:0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_WOFFSET                        0x0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_RANGE                    1:1
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_WOFFSET                  0x0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK2_BIAS0_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_RANGE                  2:2
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_WOFFSET                        0x0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_SHIFT                    MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_RANGE                    3:3
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_MSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_LSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_WOFFSET                  0x0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0_PEX_CLK3_BIAS1_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0                      MK_ADDR_CONST(0xe0ac)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_SECURE                       0x0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_DUAL                         0x0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_SCR                  IO_PEX_CLK_C_SCR_0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_SCRREG                       PMC_IMPL_SCR_IO_PEX_CLK_C_SCR_0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_WORD_COUNT                   0x1
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_RESET_MASK                   MK_MASK_CONST(0xf)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_READ_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_RANGE                       0:0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_WOFFSET                     0x0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_RANGE                 1:1
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_WOFFSET                       0x0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK2_BIAS0_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_SHIFT                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_RANGE                       2:2
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_MSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_LSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_WOFFSET                     0x0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_SHIFT                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_RANGE                 3:3
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_MSB                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_LSB                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_WOFFSET                       0x0
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0_PEX_CLK3_BIAS1_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0                 MK_ADDR_CONST(0xe0b0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_SECURE                  0x0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_DUAL                    0x0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_SCR                     IO_PEX_CLK_A_SCR_0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_SCRREG                  PMC_IMPL_SCR_IO_PEX_CLK_A_SCR_0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_WORD_COUNT                      0x1
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_RESET_MASK                      MK_MASK_CONST(0xc000000f)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_READ_MASK                       MK_MASK_CONST(0xc000000f)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_WRITE_MASK                      MK_MASK_CONST(0xc000000f)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_SHIFT                      MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_FIELD                      MK_FIELD_CONST(0x3, PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_RANGE                      31:30
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_LSB                        MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_WOFFSET                    0x0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_IDLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_DPD_OFF                    MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_CODE_DPD_ON                     MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_RANGE                  0:0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_WOFFSET                        0x0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_SHIFT                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_RANGE                    1:1
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_MSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_LSB                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_WOFFSET                  0x0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK0_BIAS0_ON                       MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_SHIFT                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_RANGE                  2:2
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_MSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_LSB                    MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_WOFFSET                        0x0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_SHIFT                    MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_RANGE                    3:3
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_MSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_LSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_WOFFSET                  0x0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0_PEX_CLK1_BIAS1_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0                      MK_ADDR_CONST(0xe0b4)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_SECURE                       0x0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_DUAL                         0x0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_SCR                  IO_PEX_CLK_A_SCR_0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_SCRREG                       PMC_IMPL_SCR_IO_PEX_CLK_A_SCR_0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_WORD_COUNT                   0x1
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_RESET_MASK                   MK_MASK_CONST(0xf)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_READ_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_RANGE                       0:0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_WOFFSET                     0x0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_RANGE                 1:1
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_WOFFSET                       0x0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK0_BIAS0_ON                    MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_SHIFT                       MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_RANGE                       2:2
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_MSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_LSB                 MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_WOFFSET                     0x0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_SHIFT                 MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_RANGE                 3:3
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_MSB                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_LSB                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_WOFFSET                       0x0
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0_PEX_CLK1_BIAS1_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0                 MK_ADDR_CONST(0xe0b8)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_SECURE                  0x0
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_DUAL                    0x0
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_SCR                     IO_PEX_CLK_B_SCR_0
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_SCRREG                  PMC_IMPL_SCR_IO_PEX_CLK_B_SCR_0
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_WORD_COUNT                      0x1
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_RESET_MASK                      MK_MASK_CONST(0xc0000003)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_READ_MASK                       MK_MASK_CONST(0xc0000003)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_WRITE_MASK                      MK_MASK_CONST(0xc0000003)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_SHIFT                      MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_FIELD                      MK_FIELD_CONST(0x3, PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_RANGE                      31:30
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_LSB                        MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_WOFFSET                    0x0
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_IDLE                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_DPD_OFF                    MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_CODE_DPD_ON                     MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_RANGE                  0:0
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_WOFFSET                        0x0
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_ON                     MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_SHIFT                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_RANGE                     1:1
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_MSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_LSB                       MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_WOFFSET                   0x0
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0_PEX_CLK4_BIAS_ON                        MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0                      MK_ADDR_CONST(0xe0bc)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_SECURE                       0x0
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_DUAL                         0x0
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_SCR                  IO_PEX_CLK_B_SCR_0
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_SCRREG                       PMC_IMPL_SCR_IO_PEX_CLK_B_SCR_0
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_WORD_COUNT                   0x1
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_READ_MASK                    MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_RANGE                       0:0
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_WOFFSET                     0x0
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_ON                  MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_SHIFT                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_SHIFT)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_RANGE                  1:1
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_MSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_LSB                    MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_WOFFSET                        0x0
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_OFF                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0_PEX_CLK4_BIAS_ON                     MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_CSI_DPD_REQ_0
+#define PMC_IMPL_IO_CSI_DPD_REQ_0                       MK_ADDR_CONST(0xe0c0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_SECURE                        0x0
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_DUAL                  0x0
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_SCR                   IO_CSI_SCR_0
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_SCRREG                        PMC_IMPL_SCR_IO_CSI_SCR_0
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_WORD_COUNT                    0x1
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_RESET_MASK                    MK_MASK_CONST(0xc00003ff)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_READ_MASK                     MK_MASK_CONST(0xc00003ff)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_WRITE_MASK                    MK_MASK_CONST(0xc00003ff)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_SHIFT                    MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_FIELD                    MK_FIELD_CONST(0x3, PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_RANGE                    31:30
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_MSB                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_LSB                      MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_WOFFSET                  0x0
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_IDLE                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_DPD_OFF                  MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CODE_DPD_ON                   MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_RANGE                   0:0
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_WOFFSET                 0x0
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_A_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_SHIFT                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_RANGE                   1:1
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_MSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_LSB                     MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_WOFFSET                 0x0
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_B_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_SHIFT                   MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_RANGE                   2:2
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_MSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_LSB                     MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_WOFFSET                 0x0
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_C_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_SHIFT                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_RANGE                   3:3
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_MSB                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_LSB                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_WOFFSET                 0x0
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_D_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_SHIFT                   MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_RANGE                   4:4
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_MSB                     MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_LSB                     MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_WOFFSET                 0x0
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_E_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_SHIFT                   MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_RANGE                   5:5
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_MSB                     MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_LSB                     MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_WOFFSET                 0x0
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_F_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_SHIFT                   MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_RANGE                   6:6
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_MSB                     MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_LSB                     MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_WOFFSET                 0x0
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_G_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_SHIFT                   MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_RANGE                   7:7
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_MSB                     MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_LSB                     MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_WOFFSET                 0x0
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_CSI_H_ON                      MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_SHIFT                        MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_RANGE                        8:8
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_MSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_LSB                  MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_WOFFSET                      0x0
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_BIAS_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_SHIFT                 MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_RANGE                 9:9
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_MSB                   MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_LSB                   MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_WOFFSET                       0x0
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_OFF                   MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_REQ_0_PHY_PLL_ON                    MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_CSI_DPD_STATUS_0
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0                    MK_ADDR_CONST(0xe0c4)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_SECURE                     0x0
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_DUAL                       0x0
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_SCR                        IO_CSI_SCR_0
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_SCRREG                     PMC_IMPL_SCR_IO_CSI_SCR_0
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_WORD_COUNT                         0x1
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_RESET_MASK                         MK_MASK_CONST(0x3ff)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_READ_MASK                  MK_MASK_CONST(0x3ff)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_RANGE                        0:0
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_WOFFSET                      0x0
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_A_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_RANGE                        1:1
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_MSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_WOFFSET                      0x0
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_B_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_RANGE                        2:2
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_WOFFSET                      0x0
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_C_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_SHIFT                        MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_RANGE                        3:3
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_MSB                  MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_LSB                  MK_SHIFT_CONST(3)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_WOFFSET                      0x0
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_D_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_SHIFT                        MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_RANGE                        4:4
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_MSB                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_LSB                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_WOFFSET                      0x0
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_E_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_SHIFT                        MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_RANGE                        5:5
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_MSB                  MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_LSB                  MK_SHIFT_CONST(5)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_WOFFSET                      0x0
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_F_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_SHIFT                        MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_RANGE                        6:6
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_MSB                  MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_LSB                  MK_SHIFT_CONST(6)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_WOFFSET                      0x0
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_G_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_SHIFT                        MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_RANGE                        7:7
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_MSB                  MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_LSB                  MK_SHIFT_CONST(7)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_WOFFSET                      0x0
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_CSI_H_ON                   MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_SHIFT                     MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_RANGE                     8:8
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_MSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_LSB                       MK_SHIFT_CONST(8)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_WOFFSET                   0x0
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_OFF                       MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_BIAS_ON                        MK_ENUM_CONST(1)
+
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_SHIFT                      MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_SHIFT)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_RANGE                      9:9
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_MSB                        MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_LSB                        MK_SHIFT_CONST(9)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_WOFFSET                    0x0
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_OFF                        MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_CSI_DPD_STATUS_0_PHY_PLL_ON                 MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_EMMC_DPD_REQ_0
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0                      MK_ADDR_CONST(0xe0c8)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_SECURE                       0x0
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_DUAL                         0x0
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_SCR                  IO_EMMC_SCR_0
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_SCRREG                       PMC_IMPL_SCR_IO_EMMC_SCR_0
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_WORD_COUNT                   0x1
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_RESET_MASK                   MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_READ_MASK                    MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_WRITE_MASK                   MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_SHIFT                   MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_FIELD                   MK_FIELD_CONST(0x3, PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_RANGE                   31:30
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_MSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_LSB                     MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_WOFFSET                 0x0
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_IDLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_DPD_OFF                 MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_CODE_DPD_ON                  MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_SHIFT)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_RANGE                   0:0
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_WOFFSET                 0x0
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_OFF                     MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_EMMC_DPD_REQ_0_EMMC_ON                      MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_EMMC_DPD_STATUS_0
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0                   MK_ADDR_CONST(0xe0cc)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_SCR                       IO_EMMC_SCR_0
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_SCRREG                    PMC_IMPL_SCR_IO_EMMC_SCR_0
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_SHIFT)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_RANGE                        0:0
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_WOFFSET                      0x0
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_OFF                  MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_EMMC_DPD_STATUS_0_EMMC_ON                   MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_DISP_DPD_REQ_0
+#define PMC_IMPL_IO_DISP_DPD_REQ_0                      MK_ADDR_CONST(0xe0d0)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_SECURE                       0x0
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_DUAL                         0x0
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_SCR                  IO_DISP_SCR_0
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_SCRREG                       PMC_IMPL_SCR_IO_DISP_SCR_0
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_WORD_COUNT                   0x1
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_RESET_MASK                   MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_READ_MASK                    MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_WRITE_MASK                   MK_MASK_CONST(0xc0000001)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_SHIFT                   MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_FIELD                   MK_FIELD_CONST(0x3, PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_SHIFT)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_RANGE                   31:30
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_MSB                     MK_SHIFT_CONST(31)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_LSB                     MK_SHIFT_CONST(30)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_WOFFSET                 0x0
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_IDLE                    MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_DPD_OFF                 MK_ENUM_CONST(1)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_CODE_DPD_ON                  MK_ENUM_CONST(2)
+
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_SHIFT                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_SHIFT)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_RANGE                       0:0
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_MSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_LSB                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_WOFFSET                     0x0
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_OFF                 MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DISP_DPD_REQ_0_HDMI_DP0_ON                  MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_IO_DISP_DPD_STATUS_0
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0                   MK_ADDR_CONST(0xe0d4)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_SECURE                    0x0
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_DUAL                      0x0
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_SCR                       IO_DISP_SCR_0
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_SCRREG                    PMC_IMPL_SCR_IO_DISP_SCR_0
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_WORD_COUNT                        0x1
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_FIELD                    MK_FIELD_CONST(0x1, PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_SHIFT)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_RANGE                    0:0
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_MSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_WOFFSET                  0x0
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_OFF                      MK_ENUM_CONST(0)
+#define PMC_IMPL_IO_DISP_DPD_STATUS_0_HDMI_DP0_ON                       MK_ENUM_CONST(1)
+
+
+// Register PMC_IMPL_POD_SOC_CONFIG_0
+#define PMC_IMPL_POD_SOC_CONFIG_0                       MK_ADDR_CONST(0xf000)
+#define PMC_IMPL_POD_SOC_CONFIG_0_SECURE                        0x0
+#define PMC_IMPL_POD_SOC_CONFIG_0_DUAL                  0x0
+#define PMC_IMPL_POD_SOC_CONFIG_0_SCR                   POD_SCR_0
+#define PMC_IMPL_POD_SOC_CONFIG_0_SCRREG                        PMC_IMPL_SCR_POD_SCR_0
+#define PMC_IMPL_POD_SOC_CONFIG_0_WORD_COUNT                    0x1
+#define PMC_IMPL_POD_SOC_CONFIG_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_SOC_CONFIG_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_SOC_CONFIG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_SOC_CONFIG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_SOC_CONFIG_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_SOC_CONFIG_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_SOC_CONFIG_0_POD_RESET_EN_N_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_POD_SOC_CONFIG_0_POD_RESET_EN_N_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_POD_SOC_CONFIG_0_POD_RESET_EN_N_SHIFT)
+#define PMC_IMPL_POD_SOC_CONFIG_0_POD_RESET_EN_N_RANGE                  0:0
+#define PMC_IMPL_POD_SOC_CONFIG_0_POD_RESET_EN_N_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_POD_SOC_CONFIG_0_POD_RESET_EN_N_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_POD_SOC_CONFIG_0_POD_RESET_EN_N_WOFFSET                        0x0
+#define PMC_IMPL_POD_SOC_CONFIG_0_POD_RESET_EN_N_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_SOC_CONFIG_0_POD_RESET_EN_N_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_SOC_CONFIG_0_POD_RESET_EN_N_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_SOC_CONFIG_0_POD_RESET_EN_N_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_SOC_CONFIG_0_POD_RESET_EN_N_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_SOC_CONFIG_0_POD_RESET_EN_N_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_POD_CV_CONFIG_0
+#define PMC_IMPL_POD_CV_CONFIG_0                        MK_ADDR_CONST(0xf004)
+#define PMC_IMPL_POD_CV_CONFIG_0_SECURE                         0x0
+#define PMC_IMPL_POD_CV_CONFIG_0_DUAL                   0x0
+#define PMC_IMPL_POD_CV_CONFIG_0_SCR                    POD_SCR_0
+#define PMC_IMPL_POD_CV_CONFIG_0_SCRREG                         PMC_IMPL_SCR_POD_SCR_0
+#define PMC_IMPL_POD_CV_CONFIG_0_WORD_COUNT                     0x1
+#define PMC_IMPL_POD_CV_CONFIG_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_CV_CONFIG_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_CV_CONFIG_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_CV_CONFIG_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_CV_CONFIG_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_CV_CONFIG_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_CV_CONFIG_0_POD_RESET_EN_N_SHIFT                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_POD_CV_CONFIG_0_POD_RESET_EN_N_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_POD_CV_CONFIG_0_POD_RESET_EN_N_SHIFT)
+#define PMC_IMPL_POD_CV_CONFIG_0_POD_RESET_EN_N_RANGE                   0:0
+#define PMC_IMPL_POD_CV_CONFIG_0_POD_RESET_EN_N_MSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_POD_CV_CONFIG_0_POD_RESET_EN_N_LSB                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_POD_CV_CONFIG_0_POD_RESET_EN_N_WOFFSET                 0x0
+#define PMC_IMPL_POD_CV_CONFIG_0_POD_RESET_EN_N_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_CV_CONFIG_0_POD_RESET_EN_N_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_CV_CONFIG_0_POD_RESET_EN_N_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_CV_CONFIG_0_POD_RESET_EN_N_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_CV_CONFIG_0_POD_RESET_EN_N_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_CV_CONFIG_0_POD_RESET_EN_N_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_POD_CPU_CONFIG_0
+#define PMC_IMPL_POD_CPU_CONFIG_0                       MK_ADDR_CONST(0xf008)
+#define PMC_IMPL_POD_CPU_CONFIG_0_SECURE                        0x0
+#define PMC_IMPL_POD_CPU_CONFIG_0_DUAL                  0x0
+#define PMC_IMPL_POD_CPU_CONFIG_0_SCR                   POD_SCR_0
+#define PMC_IMPL_POD_CPU_CONFIG_0_SCRREG                        PMC_IMPL_SCR_POD_SCR_0
+#define PMC_IMPL_POD_CPU_CONFIG_0_WORD_COUNT                    0x1
+#define PMC_IMPL_POD_CPU_CONFIG_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_CPU_CONFIG_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_CPU_CONFIG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_CPU_CONFIG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_CPU_CONFIG_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_CPU_CONFIG_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_CPU_CONFIG_0_POD_RESET_EN_N_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_POD_CPU_CONFIG_0_POD_RESET_EN_N_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_POD_CPU_CONFIG_0_POD_RESET_EN_N_SHIFT)
+#define PMC_IMPL_POD_CPU_CONFIG_0_POD_RESET_EN_N_RANGE                  0:0
+#define PMC_IMPL_POD_CPU_CONFIG_0_POD_RESET_EN_N_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_POD_CPU_CONFIG_0_POD_RESET_EN_N_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_POD_CPU_CONFIG_0_POD_RESET_EN_N_WOFFSET                        0x0
+#define PMC_IMPL_POD_CPU_CONFIG_0_POD_RESET_EN_N_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_CPU_CONFIG_0_POD_RESET_EN_N_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_CPU_CONFIG_0_POD_RESET_EN_N_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_CPU_CONFIG_0_POD_RESET_EN_N_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_CPU_CONFIG_0_POD_RESET_EN_N_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_CPU_CONFIG_0_POD_RESET_EN_N_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_POD_GPU_CONFIG_0
+#define PMC_IMPL_POD_GPU_CONFIG_0                       MK_ADDR_CONST(0xf00c)
+#define PMC_IMPL_POD_GPU_CONFIG_0_SECURE                        0x0
+#define PMC_IMPL_POD_GPU_CONFIG_0_DUAL                  0x0
+#define PMC_IMPL_POD_GPU_CONFIG_0_SCR                   POD_SCR_0
+#define PMC_IMPL_POD_GPU_CONFIG_0_SCRREG                        PMC_IMPL_SCR_POD_SCR_0
+#define PMC_IMPL_POD_GPU_CONFIG_0_WORD_COUNT                    0x1
+#define PMC_IMPL_POD_GPU_CONFIG_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_GPU_CONFIG_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_GPU_CONFIG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_GPU_CONFIG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_GPU_CONFIG_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_GPU_CONFIG_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_GPU_CONFIG_0_POD_RESET_EN_N_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_POD_GPU_CONFIG_0_POD_RESET_EN_N_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_POD_GPU_CONFIG_0_POD_RESET_EN_N_SHIFT)
+#define PMC_IMPL_POD_GPU_CONFIG_0_POD_RESET_EN_N_RANGE                  0:0
+#define PMC_IMPL_POD_GPU_CONFIG_0_POD_RESET_EN_N_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_POD_GPU_CONFIG_0_POD_RESET_EN_N_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_POD_GPU_CONFIG_0_POD_RESET_EN_N_WOFFSET                        0x0
+#define PMC_IMPL_POD_GPU_CONFIG_0_POD_RESET_EN_N_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_GPU_CONFIG_0_POD_RESET_EN_N_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_GPU_CONFIG_0_POD_RESET_EN_N_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_GPU_CONFIG_0_POD_RESET_EN_N_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_GPU_CONFIG_0_POD_RESET_EN_N_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_GPU_CONFIG_0_POD_RESET_EN_N_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_POD_FSI_CONFIG_0
+#define PMC_IMPL_POD_FSI_CONFIG_0                       MK_ADDR_CONST(0xf010)
+#define PMC_IMPL_POD_FSI_CONFIG_0_SECURE                        0x0
+#define PMC_IMPL_POD_FSI_CONFIG_0_DUAL                  0x0
+#define PMC_IMPL_POD_FSI_CONFIG_0_SCR                   POD_SCR_0
+#define PMC_IMPL_POD_FSI_CONFIG_0_SCRREG                        PMC_IMPL_SCR_POD_SCR_0
+#define PMC_IMPL_POD_FSI_CONFIG_0_WORD_COUNT                    0x1
+#define PMC_IMPL_POD_FSI_CONFIG_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_FSI_CONFIG_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_FSI_CONFIG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_FSI_CONFIG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_FSI_CONFIG_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_FSI_CONFIG_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_FSI_CONFIG_0_POD_RESET_EN_N_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_POD_FSI_CONFIG_0_POD_RESET_EN_N_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_POD_FSI_CONFIG_0_POD_RESET_EN_N_SHIFT)
+#define PMC_IMPL_POD_FSI_CONFIG_0_POD_RESET_EN_N_RANGE                  0:0
+#define PMC_IMPL_POD_FSI_CONFIG_0_POD_RESET_EN_N_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_POD_FSI_CONFIG_0_POD_RESET_EN_N_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_POD_FSI_CONFIG_0_POD_RESET_EN_N_WOFFSET                        0x0
+#define PMC_IMPL_POD_FSI_CONFIG_0_POD_RESET_EN_N_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_FSI_CONFIG_0_POD_RESET_EN_N_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_FSI_CONFIG_0_POD_RESET_EN_N_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_FSI_CONFIG_0_POD_RESET_EN_N_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_POD_FSI_CONFIG_0_POD_RESET_EN_N_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_POD_FSI_CONFIG_0_POD_RESET_EN_N_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_SCPM_RESET_EN_0
+#define PMC_IMPL_SCPM_RESET_EN_0                        MK_ADDR_CONST(0xf800)
+#define PMC_IMPL_SCPM_RESET_EN_0_SECURE                         0x0
+#define PMC_IMPL_SCPM_RESET_EN_0_DUAL                   0x0
+#define PMC_IMPL_SCPM_RESET_EN_0_SCR                    SCPM_COMM_SCR_0
+#define PMC_IMPL_SCPM_RESET_EN_0_SCRREG                         PMC_IMPL_SCR_SCPM_COMM_SCR_0
+#define PMC_IMPL_SCPM_RESET_EN_0_WORD_COUNT                     0x1
+#define PMC_IMPL_SCPM_RESET_EN_0_RESET_VAL                      MK_MASK_CONST(0x1f)
+#define PMC_IMPL_SCPM_RESET_EN_0_RESET_MASK                     MK_MASK_CONST(0x1f)
+#define PMC_IMPL_SCPM_RESET_EN_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_SCPM_RESET_EN_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SCPM_RESET_EN_0_READ_MASK                      MK_MASK_CONST(0x1f)
+#define PMC_IMPL_SCPM_RESET_EN_0_WRITE_MASK                     MK_MASK_CONST(0x1f)
+#define PMC_IMPL_SCPM_RESET_EN_0_RTC_XTAL_SCPM_RST_OUT_EN_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_SCPM_RESET_EN_0_RTC_XTAL_SCPM_RST_OUT_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_SCPM_RESET_EN_0_RTC_XTAL_SCPM_RST_OUT_EN_SHIFT)
+#define PMC_IMPL_SCPM_RESET_EN_0_RTC_XTAL_SCPM_RST_OUT_EN_RANGE                 0:0
+#define PMC_IMPL_SCPM_RESET_EN_0_RTC_XTAL_SCPM_RST_OUT_EN_MSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_SCPM_RESET_EN_0_RTC_XTAL_SCPM_RST_OUT_EN_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_SCPM_RESET_EN_0_RTC_XTAL_SCPM_RST_OUT_EN_WOFFSET                       0x0
+#define PMC_IMPL_SCPM_RESET_EN_0_RTC_XTAL_SCPM_RST_OUT_EN_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SCPM_RESET_EN_0_RTC_XTAL_SCPM_RST_OUT_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SCPM_RESET_EN_0_RTC_XTAL_SCPM_RST_OUT_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SCPM_RESET_EN_0_RTC_XTAL_SCPM_RST_OUT_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SCPM_RESET_EN_0_RTC_XTAL_SCPM_RST_OUT_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_SCPM_RESET_EN_0_RTC_XTAL_SCPM_RST_OUT_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_XTAL_SCPM_RST_OUT_EN_SHIFT                 MK_SHIFT_CONST(1)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_XTAL_SCPM_RST_OUT_EN_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_SCPM_RESET_EN_0_SOC_XTAL_SCPM_RST_OUT_EN_SHIFT)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_XTAL_SCPM_RST_OUT_EN_RANGE                 1:1
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_XTAL_SCPM_RST_OUT_EN_MSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_XTAL_SCPM_RST_OUT_EN_LSB                   MK_SHIFT_CONST(1)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_XTAL_SCPM_RST_OUT_EN_WOFFSET                       0x0
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_XTAL_SCPM_RST_OUT_EN_DEFAULT                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_XTAL_SCPM_RST_OUT_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_XTAL_SCPM_RST_OUT_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_XTAL_SCPM_RST_OUT_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_XTAL_SCPM_RST_OUT_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_XTAL_SCPM_RST_OUT_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_BPMP_CORE_CLK_SCPM_RST_OUT_EN_SHIFT                        MK_SHIFT_CONST(2)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_BPMP_CORE_CLK_SCPM_RST_OUT_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SCPM_RESET_EN_0_SOC_BPMP_CORE_CLK_SCPM_RST_OUT_EN_SHIFT)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_BPMP_CORE_CLK_SCPM_RST_OUT_EN_RANGE                        2:2
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_BPMP_CORE_CLK_SCPM_RST_OUT_EN_MSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_BPMP_CORE_CLK_SCPM_RST_OUT_EN_LSB                  MK_SHIFT_CONST(2)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_BPMP_CORE_CLK_SCPM_RST_OUT_EN_WOFFSET                      0x0
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_BPMP_CORE_CLK_SCPM_RST_OUT_EN_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_BPMP_CORE_CLK_SCPM_RST_OUT_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_BPMP_CORE_CLK_SCPM_RST_OUT_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_BPMP_CORE_CLK_SCPM_RST_OUT_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_BPMP_CORE_CLK_SCPM_RST_OUT_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_BPMP_CORE_CLK_SCPM_RST_OUT_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_PSC_SE_CLK_SCPM_RST_OUT_EN_SHIFT                   MK_SHIFT_CONST(3)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_PSC_SE_CLK_SCPM_RST_OUT_EN_FIELD                   MK_FIELD_CONST(0x1, PMC_IMPL_SCPM_RESET_EN_0_SOC_PSC_SE_CLK_SCPM_RST_OUT_EN_SHIFT)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_PSC_SE_CLK_SCPM_RST_OUT_EN_RANGE                   3:3
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_PSC_SE_CLK_SCPM_RST_OUT_EN_MSB                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_PSC_SE_CLK_SCPM_RST_OUT_EN_LSB                     MK_SHIFT_CONST(3)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_PSC_SE_CLK_SCPM_RST_OUT_EN_WOFFSET                 0x0
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_PSC_SE_CLK_SCPM_RST_OUT_EN_DEFAULT                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_PSC_SE_CLK_SCPM_RST_OUT_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_PSC_SE_CLK_SCPM_RST_OUT_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_PSC_SE_CLK_SCPM_RST_OUT_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_PSC_SE_CLK_SCPM_RST_OUT_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SCPM_RESET_EN_0_SOC_PSC_SE_CLK_SCPM_RST_OUT_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SCPM_RESET_EN_0_FSI_SCPM_RST_OUT_EN_SHIFT                      MK_SHIFT_CONST(4)
+#define PMC_IMPL_SCPM_RESET_EN_0_FSI_SCPM_RST_OUT_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_SCPM_RESET_EN_0_FSI_SCPM_RST_OUT_EN_SHIFT)
+#define PMC_IMPL_SCPM_RESET_EN_0_FSI_SCPM_RST_OUT_EN_RANGE                      4:4
+#define PMC_IMPL_SCPM_RESET_EN_0_FSI_SCPM_RST_OUT_EN_MSB                        MK_SHIFT_CONST(4)
+#define PMC_IMPL_SCPM_RESET_EN_0_FSI_SCPM_RST_OUT_EN_LSB                        MK_SHIFT_CONST(4)
+#define PMC_IMPL_SCPM_RESET_EN_0_FSI_SCPM_RST_OUT_EN_WOFFSET                    0x0
+#define PMC_IMPL_SCPM_RESET_EN_0_FSI_SCPM_RST_OUT_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SCPM_RESET_EN_0_FSI_SCPM_RST_OUT_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SCPM_RESET_EN_0_FSI_SCPM_RST_OUT_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SCPM_RESET_EN_0_FSI_SCPM_RST_OUT_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SCPM_RESET_EN_0_FSI_SCPM_RST_OUT_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SCPM_RESET_EN_0_FSI_SCPM_RST_OUT_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0                 MK_ADDR_CONST(0xf900)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_SECURE                  0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_DUAL                    0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_SCR                     RTC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_SCRREG                  PMC_IMPL_SCR_RTC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_WORD_COUNT                      0x1
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_RESET_VAL                       MK_MASK_CONST(0x80000001)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_RESET_MASK                      MK_MASK_CONST(0x80000003)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_READ_MASK                       MK_MASK_CONST(0x80000003)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_WRITE_MASK                      MK_MASK_CONST(0x80000003)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_EN_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_EN_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_EN_RANGE                        0:0
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_EN_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_EN_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_EN_WOFFSET                      0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_EN_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_RANGE                      1:1
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_WOFFSET                    0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_SHIFT                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_RANGE                      31:31
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_LSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_WOFFSET                    0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0                     MK_ADDR_CONST(0xf904)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_SECURE                      0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DUAL                        0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_SCR                         RTC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_SCRREG                      PMC_IMPL_SCR_RTC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_WORD_COUNT                  0x1
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_RESET_VAL                   MK_MASK_CONST(0x7777)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_RESET_MASK                  MK_MASK_CONST(0xffff)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_READ_MASK                   MK_MASK_CONST(0xffff)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_WRITE_MASK                  MK_MASK_CONST(0xffff)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_FIELD                    MK_FIELD_CONST(0xf, PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_RANGE                    3:0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_MSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_WOFFSET                  0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_DEFAULT                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_DEFAULT_MASK                     MK_MASK_CONST(0xf)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_SHIFT                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_FIELD                    MK_FIELD_CONST(0xf, PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_RANGE                    7:4
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_MSB                      MK_SHIFT_CONST(7)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_LSB                      MK_SHIFT_CONST(4)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_WOFFSET                  0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_DEFAULT                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_DEFAULT_MASK                     MK_MASK_CONST(0xf)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_SHIFT                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_FIELD                    MK_FIELD_CONST(0xf, PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_RANGE                    11:8
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_MSB                      MK_SHIFT_CONST(11)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_LSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_WOFFSET                  0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_DEFAULT                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_DEFAULT_MASK                     MK_MASK_CONST(0xf)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_SHIFT                    MK_SHIFT_CONST(12)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_FIELD                    MK_FIELD_CONST(0xf, PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_RANGE                    15:12
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_MSB                      MK_SHIFT_CONST(15)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_LSB                      MK_SHIFT_CONST(12)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_WOFFSET                  0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_DEFAULT                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_DEFAULT_MASK                     MK_MASK_CONST(0xf)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0                       MK_ADDR_CONST(0xf908)
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_SECURE                        0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_DUAL                  0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_SCR                   RTC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_SCRREG                        PMC_IMPL_SCR_RTC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_WORD_COUNT                    0x1
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_RESET_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_READ_MASK                     MK_MASK_CONST(0xf)
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_WRITE_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_FIELD                        MK_FIELD_CONST(0xf, PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_RANGE                        3:0
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_MSB                  MK_SHIFT_CONST(3)
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_WOFFSET                      0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0                      MK_ADDR_CONST(0xf90c)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SECURE                       0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DUAL                         0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SCR                  RTC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SCRREG                       PMC_IMPL_SCR_RTC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_WORD_COUNT                   0x1
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_MASK                   MK_MASK_CONST(0xff03ff)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_READ_MASK                    MK_MASK_CONST(0xff03ff)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_WRITE_MASK                   MK_MASK_CONST(0xff03ff)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_RANGE                     0:0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_WOFFSET                   0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_FIELD                        MK_FIELD_CONST(0xf, PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_RANGE                        4:1
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_MSB                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_WOFFSET                      0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_SHIFT                  MK_SHIFT_CONST(5)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_RANGE                  5:5
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_MSB                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_LSB                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_WOFFSET                        0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_SHIFT                  MK_SHIFT_CONST(6)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_FIELD                  MK_FIELD_CONST(0xf, PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_RANGE                  9:6
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_MSB                    MK_SHIFT_CONST(9)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_LSB                    MK_SHIFT_CONST(6)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_WOFFSET                        0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_SHIFT                     MK_SHIFT_CONST(16)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_FIELD                     MK_FIELD_CONST(0xff, PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_RANGE                     23:16
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_MSB                       MK_SHIFT_CONST(23)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_LSB                       MK_SHIFT_CONST(16)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_WOFFSET                   0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_RTC_XTAL_SCPM_STATUS_0
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0                 MK_ADDR_CONST(0xf910)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SCR                     RTC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SCRREG                  PMC_IMPL_SCR_RTC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7e001f)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7e001f)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_RANGE                  0:0
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_WOFFSET                        0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_FIELD                        MK_FIELD_CONST(0xf, PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_RANGE                        4:1
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_MSB                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_WOFFSET                      0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_PHASE_SHIFT                       MK_SHIFT_CONST(17)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_PHASE_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_PHASE_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_PHASE_RANGE                       17:17
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_PHASE_MSB                 MK_SHIFT_CONST(17)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_PHASE_LSB                 MK_SHIFT_CONST(17)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_PHASE_WOFFSET                     0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_PHASE_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_PHASE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_PHASE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_PHASE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_PHASE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_ERROR_PHASE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_SHIFT                 MK_SHIFT_CONST(18)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_RANGE                 18:18
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_MSB                   MK_SHIFT_CONST(18)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_LSB                   MK_SHIFT_CONST(18)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_WOFFSET                       0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_OUTPUT_SHIFT                    MK_SHIFT_CONST(19)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_OUTPUT_FIELD                    MK_FIELD_CONST(0xf, PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_OUTPUT_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_OUTPUT_RANGE                    22:19
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_OUTPUT_MSB                      MK_SHIFT_CONST(22)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_OUTPUT_LSB                      MK_SHIFT_CONST(19)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_OUTPUT_WOFFSET                  0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_OUTPUT_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_OUTPUT_DEFAULT_MASK                     MK_MASK_CONST(0xf)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_OUTPUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_OUTPUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_OUTPUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_STATUS_0_OUTPUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0                       MK_ADDR_CONST(0xf914)
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_SECURE                        0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_DUAL                  0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_SCR                   RTC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_SCRREG                        PMC_IMPL_SCR_RTC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_WORD_COUNT                    0x1
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_RESET_MASK                    MK_MASK_CONST(0xffff)
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_READ_MASK                     MK_MASK_CONST(0xffff)
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_FIELD                 MK_FIELD_CONST(0xffff, PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_SHIFT)
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_RANGE                 15:0
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_MSB                   MK_SHIFT_CONST(15)
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_WOFFSET                       0x0
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0                 MK_ADDR_CONST(0xfa00)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_SECURE                  0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_DUAL                    0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_SCR                     SOC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_SCRREG                  PMC_IMPL_SCR_SOC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_WORD_COUNT                      0x1
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_RESET_VAL                       MK_MASK_CONST(0x80000001)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_RESET_MASK                      MK_MASK_CONST(0x80000003)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_READ_MASK                       MK_MASK_CONST(0x80000003)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_WRITE_MASK                      MK_MASK_CONST(0x80000003)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_EN_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_EN_FIELD                        MK_FIELD_CONST(0x1, PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_EN_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_EN_RANGE                        0:0
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_EN_MSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_EN_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_EN_WOFFSET                      0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_EN_DEFAULT                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_SHIFT                      MK_SHIFT_CONST(1)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_RANGE                      1:1
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_MSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_LSB                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_WOFFSET                    0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_CONFIG_VALID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_SHIFT                      MK_SHIFT_CONST(31)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_FIELD                      MK_FIELD_CONST(0x1, PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_RANGE                      31:31
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_MSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_LSB                        MK_SHIFT_CONST(31)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_WOFFSET                    0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_DEFAULT                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0_HSM_FAULT_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0                     MK_ADDR_CONST(0xfa04)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_SECURE                      0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DUAL                        0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_SCR                         SOC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_SCRREG                      PMC_IMPL_SCR_SOC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_WORD_COUNT                  0x1
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_RESET_VAL                   MK_MASK_CONST(0x7777)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_RESET_MASK                  MK_MASK_CONST(0xffff)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_READ_MASK                   MK_MASK_CONST(0xffff)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_WRITE_MASK                  MK_MASK_CONST(0xffff)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_SHIFT                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_FIELD                    MK_FIELD_CONST(0xf, PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_RANGE                    3:0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_MSB                      MK_SHIFT_CONST(3)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_LSB                      MK_SHIFT_CONST(0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_WOFFSET                  0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_DEFAULT                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_DEFAULT_MASK                     MK_MASK_CONST(0xf)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_SHIFT                    MK_SHIFT_CONST(4)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_FIELD                    MK_FIELD_CONST(0xf, PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_RANGE                    7:4
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_MSB                      MK_SHIFT_CONST(7)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_LSB                      MK_SHIFT_CONST(4)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_WOFFSET                  0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_DEFAULT                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_DEFAULT_MASK                     MK_MASK_CONST(0xf)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_SHIFT                    MK_SHIFT_CONST(8)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_FIELD                    MK_FIELD_CONST(0xf, PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_RANGE                    11:8
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_MSB                      MK_SHIFT_CONST(11)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_LSB                      MK_SHIFT_CONST(8)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_WOFFSET                  0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_DEFAULT                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_DEFAULT_MASK                     MK_MASK_CONST(0xf)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_SHIFT                    MK_SHIFT_CONST(12)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_FIELD                    MK_FIELD_CONST(0xf, PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_RANGE                    15:12
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_MSB                      MK_SHIFT_CONST(15)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_LSB                      MK_SHIFT_CONST(12)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_WOFFSET                  0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_DEFAULT                  MK_MASK_CONST(0x7)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_DEFAULT_MASK                     MK_MASK_CONST(0xf)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0_DATAPATH_DEL_SEL_3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0                       MK_ADDR_CONST(0xfa08)
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_SECURE                        0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_DUAL                  0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_SCR                   SOC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_SCRREG                        PMC_IMPL_SCR_SOC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_WORD_COUNT                    0x1
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_RESET_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_READ_MASK                     MK_MASK_CONST(0xf)
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_WRITE_MASK                    MK_MASK_CONST(0xf)
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_SHIFT                        MK_SHIFT_CONST(0)
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_FIELD                        MK_FIELD_CONST(0xf, PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_RANGE                        3:0
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_MSB                  MK_SHIFT_CONST(3)
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_LSB                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_WOFFSET                      0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0_MASK_TIMING_PATH_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0                      MK_ADDR_CONST(0xfa0c)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SECURE                       0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DUAL                         0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SCR                  SOC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SCRREG                       PMC_IMPL_SCR_SOC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_WORD_COUNT                   0x1
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_MASK                   MK_MASK_CONST(0xff03ff)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_READ_MASK                    MK_MASK_CONST(0xff03ff)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_WRITE_MASK                   MK_MASK_CONST(0xff03ff)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_SHIFT                     MK_SHIFT_CONST(0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_FIELD                     MK_FIELD_CONST(0x1, PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_RANGE                     0:0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_MSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_LSB                       MK_SHIFT_CONST(0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_WOFFSET                   0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RESET_JTAG_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_FIELD                        MK_FIELD_CONST(0xf, PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_RANGE                        4:1
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_MSB                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_WOFFSET                      0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_PATH_ID_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_SHIFT                  MK_SHIFT_CONST(5)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_RANGE                  5:5
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_MSB                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_LSB                    MK_SHIFT_CONST(5)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_WOFFSET                        0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_DELAY_CHAR_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_SHIFT                  MK_SHIFT_CONST(6)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_FIELD                  MK_FIELD_CONST(0xf, PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_RANGE                  9:6
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_MSB                    MK_SHIFT_CONST(9)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_LSB                    MK_SHIFT_CONST(6)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_WOFFSET                        0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_SETUP_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_SHIFT                     MK_SHIFT_CONST(16)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_FIELD                     MK_FIELD_CONST(0xff, PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_RANGE                     23:16
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_MSB                       MK_SHIFT_CONST(23)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_LSB                       MK_SHIFT_CONST(16)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_WOFFSET                   0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0_RO_SAMPLING_PERIOD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_SOC_XTAL_SCPM_STATUS_0
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0                 MK_ADDR_CONST(0xfa10)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SECURE                  0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_DUAL                    0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SCR                     SOC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SCRREG                  PMC_IMPL_SCR_SOC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_WORD_COUNT                      0x1
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_RESET_MASK                      MK_MASK_CONST(0x7e001f)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_READ_MASK                       MK_MASK_CONST(0x7e001f)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_SHIFT                  MK_SHIFT_CONST(0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_FIELD                  MK_FIELD_CONST(0x1, PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_RANGE                  0:0
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_MSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_LSB                    MK_SHIFT_CONST(0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_WOFFSET                        0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_OUT_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_SHIFT                        MK_SHIFT_CONST(1)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_FIELD                        MK_FIELD_CONST(0xf, PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_RANGE                        4:1
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_MSB                  MK_SHIFT_CONST(4)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_LSB                  MK_SHIFT_CONST(1)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_WOFFSET                      0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_PATH_TIMING_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_PHASE_SHIFT                       MK_SHIFT_CONST(17)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_PHASE_FIELD                       MK_FIELD_CONST(0x1, PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_PHASE_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_PHASE_RANGE                       17:17
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_PHASE_MSB                 MK_SHIFT_CONST(17)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_PHASE_LSB                 MK_SHIFT_CONST(17)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_PHASE_WOFFSET                     0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_PHASE_DEFAULT                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_PHASE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_PHASE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_PHASE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_PHASE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_ERROR_PHASE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_SHIFT                 MK_SHIFT_CONST(18)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_FIELD                 MK_FIELD_CONST(0x1, PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_RANGE                 18:18
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_MSB                   MK_SHIFT_CONST(18)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_LSB                   MK_SHIFT_CONST(18)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_WOFFSET                       0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_SAMPLING_COMPLETE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_OUTPUT_SHIFT                    MK_SHIFT_CONST(19)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_OUTPUT_FIELD                    MK_FIELD_CONST(0xf, PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_OUTPUT_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_OUTPUT_RANGE                    22:19
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_OUTPUT_MSB                      MK_SHIFT_CONST(22)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_OUTPUT_LSB                      MK_SHIFT_CONST(19)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_OUTPUT_WOFFSET                  0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_OUTPUT_DEFAULT                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_OUTPUT_DEFAULT_MASK                     MK_MASK_CONST(0xf)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_OUTPUT_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_OUTPUT_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_OUTPUT_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_STATUS_0_OUTPUT_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0                       MK_ADDR_CONST(0xfa14)
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_SECURE                        0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_DUAL                  0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_SCR                   SOC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_SCRREG                        PMC_IMPL_SCR_SOC_XTAL_SCPM_SCR_0
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_WORD_COUNT                    0x1
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_RESET_MASK                    MK_MASK_CONST(0xffff)
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_READ_MASK                     MK_MASK_CONST(0xffff)
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_SHIFT                 MK_SHIFT_CONST(0)
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_FIELD                 MK_FIELD_CONST(0xffff, PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_SHIFT)
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_RANGE                 15:0
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_MSB                   MK_SHIFT_CONST(15)
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_LSB                   MK_SHIFT_CONST(0)
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_WOFFSET                       0x0
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0_RO_COUNT_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARPMC_IMPL_REGS(_op_) \
+_op_(PMC_IMPL_CNTRL_0) \
+_op_(PMC_IMPL_SLCG_CTRL_0) \
+_op_(PMC_IMPL_DPD_PADS_ORIDE_0) \
+_op_(PMC_IMPL_DPD_ENABLE_0) \
+_op_(PMC_IMPL_SC7_CONFIG_0) \
+_op_(PMC_IMPL_SC7_STATUS_0) \
+_op_(PMC_IMPL_SC8_FSM_INIT_0) \
+_op_(PMC_IMPL_SC8_CONTROL_0) \
+_op_(PMC_IMPL_RETENTION_CONTROL_0) \
+_op_(PMC_IMPL_SC7_DEBUG_CTRL_0) \
+_op_(PMC_IMPL_PWRGOOD_TIMER_0) \
+_op_(PMC_IMPL_BLINK_TIMER_0) \
+_op_(PMC_IMPL_NO_IOPOWER_0) \
+_op_(PMC_IMPL_E_18V_PWR_0) \
+_op_(PMC_IMPL_E_33V_PWR_0) \
+_op_(PMC_IMPL_OSC_EDPD_OVER_0) \
+_op_(PMC_IMPL_CLK_OUT_CNTRL_0) \
+_op_(PMC_IMPL_SENSOR_CTRL_0) \
+_op_(PMC_IMPL_RST_STATUS_0) \
+_op_(PMC_IMPL_IO_DPD_REQ_0) \
+_op_(PMC_IMPL_SEL_DPD_TIM_0) \
+_op_(PMC_IMPL_TSC_MULT_0) \
+_op_(PMC_IMPL_GLB_AMAP_CFG_0) \
+_op_(PMC_IMPL_GPU_RG_CNTRL_0) \
+_op_(PMC_IMPL_CNTRL2_0) \
+_op_(PMC_IMPL_EVENT_COUNTER_0) \
+_op_(PMC_IMPL_DIRECT_THERMTRIP_CFG_0) \
+_op_(PMC_IMPL_RAMDUMP_CTL_STATUS_0) \
+_op_(PMC_IMPL_RAMDUMP_TIMEOUT_0) \
+_op_(PMC_IMPL_RST_REQ_CONFIG_0) \
+_op_(PMC_IMPL_RST_REQ_CNTVAL_0) \
+_op_(PMC_IMPL_VFMON_ACTION_0) \
+_op_(PMC_IMPL_VFMON_INT_STATUS_0) \
+_op_(PMC_IMPL_VFMON_INT_MASK_0) \
+_op_(PMC_IMPL_POWER_GATE_TIMERS_0) \
+_op_(PMC_IMPL_LOGIC_ZONE_DELAY_0) \
+_op_(PMC_IMPL_SRAM_ZONE_DELAY_0) \
+_op_(PMC_IMPL_ZONE_CONFIG_0) \
+_op_(PMC_IMPL_INTER_PARTITION_PG_DELAY_0) \
+_op_(PMC_IMPL_AO_PG_TIMERS_0) \
+_op_(PMC_IMPL_PG_STATUS_0) \
+_op_(PMC_IMPL_PART_AUD_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_AUD_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_AUD_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_DISP_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_DISP_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_VIC_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_VIC_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_XUSBA_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_XUSBA_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_XUSBA_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_XUSBB_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_XUSBB_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_XUSBB_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_XUSBC_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_XUSBC_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_XUSBC_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_SCRATCH_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_SCRATCH_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_SCRATCH_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_AONPG_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_AONPG_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM0_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM1_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM1_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM2_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM2_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM3_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM3_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM4_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM4_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM5_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM5_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM6_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM6_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM7_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_AOPG_TCM7_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_CAN0_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_AOPG_CAN0_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_AOPG_CAN1_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_MSS_SCRATCH_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX8A_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX8A_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX8A_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4A_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4A_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX4A_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX1A_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX1A_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX8B_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_DLAA_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_DLAA_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_DLAB_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_DLAB_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_ISP_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_ISP_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_NVDEC_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_NVDEC_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_NVDEC_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_NVJPGA_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_NVJPGA_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_NVJPGA_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_NVJPGB_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_NVJPGB_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_NVJPGB_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_NVENC_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_NVENC_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_NVENC_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_VI_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_VI_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_VI_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4BA_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4BA_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX4BA_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4BB_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4BB_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX4BB_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4CA_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4CA_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX4CA_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4CB_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4CB_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX4CB_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4CC_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4CC_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX4CC_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_PVA_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_PVA_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_PVA_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_OFA_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_OFA_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_OFA_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_MGBEA_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_MGBEA_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_MGBEA_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_MGBEBA_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_MGBEBA_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_MGBEBA_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_MGBEBB_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_MGBEBB_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_MGBEBB_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_MGBEBC_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_MGBEBC_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_MGBEBC_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_EMCAA_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_EMCAA_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_EMCAA_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_EMCAB_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_EMCAB_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_EMCAB_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_EMCBA_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_EMCBA_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_EMCBA_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_EMCBB_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_EMCBB_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_EMCBB_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_TZRAM_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_TZRAM_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_TZRAM_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_DBBRAM_POWER_GATE_CONTROL_0) \
+_op_(PMC_IMPL_PART_DBBRAM_POWER_GATE_STATUS_0) \
+_op_(PMC_IMPL_PART_DBBRAM_CLAMP_CONTROL_0) \
+_op_(PMC_IMPL_PART_AUD_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_AUD_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_DISP_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_DISP_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_ISP_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_ISP_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_NVDEC_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_NVDEC_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_NVJPGA_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_NVJPGA_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_NVJPGB_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_NVJPGB_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_NVENC_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_NVENC_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_VI_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_VI_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_VIC_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_VIC_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_XUSBA_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_XUSBA_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_XUSBB_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_XUSBB_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_XUSBC_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_XUSBC_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX8A_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX8A_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX4A_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4A_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX4BA_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4BA_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX4BB_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4BB_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX4CA_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4CA_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX4CB_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4CB_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX4CC_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX4CC_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX1A_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX1A_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_PCIEX8B_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_PCIEX8B_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_PVA_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_PVA_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_DLAA_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_DLAA_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_DLAB_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_DLAB_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_OFA_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_OFA_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_MGBEA_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_MGBEA_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_MGBEBA_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_MGBEBA_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_MGBEBB_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_MGBEBB_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_MGBEBC_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_MGBEBC_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_EMCAA_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_EMCAA_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_EMCAB_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_EMCAB_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_EMCBA_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_EMCBA_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_EMCBB_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_EMCBB_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_SW_OVERRIDE_CTRL_1_0) \
+_op_(PMC_IMPL_SW_OVERRIDE_CTRL_2_0) \
+_op_(PMC_IMPL_MISC_CTRL_0) \
+_op_(PMC_IMPL_PART_GPURAIL_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_GPURAIL_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_CVRAIL_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_CVRAIL_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PART_FSIRAIL_PWRDWN_REQ_CONTROL_0) \
+_op_(PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0) \
+_op_(PMC_IMPL_PMC2LIC_INTR_STATUS_0) \
+_op_(PMC_IMPL_PMC2LIC_INTR_ENABLE_0) \
+_op_(PMC_IMPL_AOVC_LOCK_CNTRL_0) \
+_op_(PMC_IMPL_AOVC_LOCK_ID_STATUS_0) \
+_op_(PMC_IMPL_TEST_CLK_MUX_SEL_0) \
+_op_(PMC_IMPL_SC7_FSM_STATUS_0) \
+_op_(PMC_IMPL_RAMDUMP_FIQ_EXIT_0) \
+_op_(PMC_IMPL_SET_RAMDUMP_FIQ_EXIT_0) \
+_op_(PMC_IMPL_CLR_RAMDUMP_FIQ_EXIT_0) \
+_op_(PMC_IMPL_FMON_THRESHOLD_HIGH_PMC_CK_0) \
+_op_(PMC_IMPL_FMON_THRESHOLD_LOW_PMC_CK_0) \
+_op_(PMC_IMPL_FMON_REF_WINDOW_COUNT_PMC_CK_0) \
+_op_(PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_PMC_CK_0) \
+_op_(PMC_IMPL_FMON_FAULT_ACTION_PMC_CK_0) \
+_op_(PMC_IMPL_FMON_CONFIG_PMC_CK_0) \
+_op_(PMC_IMPL_FMON_ENABLE_STATUS_PMC_CK_0) \
+_op_(PMC_IMPL_FMON_FAULT_STATUS_PMC_CK_0) \
+_op_(PMC_IMPL_FMON_LOAD_DATA_CTRL_PMC_CK_0) \
+_op_(PMC_IMPL_FMON_LOAD_DATA_STATUS_0_PMC_CK_0) \
+_op_(PMC_IMPL_FMON_LOAD_DATA_STATUS_1_PMC_CK_0) \
+_op_(PMC_IMPL_FMON_LOAD_DATA_STATUS_2_PMC_CK_0) \
+_op_(PMC_IMPL_FMON_CLEAR_COUNTER_PMC_CK_0) \
+_op_(PMC_IMPL_FMON_DEBUG_CONFIG_PMC_CK_0) \
+_op_(PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_PMC_CK_0) \
+_op_(PMC_IMPL_FMON_THRESHOLD_HIGH_OSCnFUSE_CK_0) \
+_op_(PMC_IMPL_FMON_THRESHOLD_LOW_OSCnFUSE_CK_0) \
+_op_(PMC_IMPL_FMON_REF_WINDOW_COUNT_OSCnFUSE_CK_0) \
+_op_(PMC_IMPL_FMON_REF_WINDOW_DC_CHECK_COUNT_OSCnFUSE_CK_0) \
+_op_(PMC_IMPL_FMON_FAULT_ACTION_OSCnFUSE_CK_0) \
+_op_(PMC_IMPL_FMON_CONFIG_OSCnFUSE_CK_0) \
+_op_(PMC_IMPL_FMON_ENABLE_STATUS_OSCnFUSE_CK_0) \
+_op_(PMC_IMPL_FMON_FAULT_STATUS_OSCnFUSE_CK_0) \
+_op_(PMC_IMPL_FMON_LOAD_DATA_CTRL_OSCnFUSE_CK_0) \
+_op_(PMC_IMPL_FMON_LOAD_DATA_STATUS_0_OSCnFUSE_CK_0) \
+_op_(PMC_IMPL_FMON_LOAD_DATA_STATUS_1_OSCnFUSE_CK_0) \
+_op_(PMC_IMPL_FMON_LOAD_DATA_STATUS_2_OSCnFUSE_CK_0) \
+_op_(PMC_IMPL_FMON_CLEAR_COUNTER_OSCnFUSE_CK_0) \
+_op_(PMC_IMPL_FMON_DEBUG_CONFIG_OSCnFUSE_CK_0) \
+_op_(PMC_IMPL_FMON_CNTR_OVERFLOW_CTRL_OSCnFUSE_CK_0) \
+_op_(PMC_IMPL_FMON_DBG_CONFIG_0) \
+_op_(PMC_IMPL_L0L1A_RST_SOURCE_EN_0) \
+_op_(PMC_IMPL_L0L1A_RST_LEVEL_EN_0) \
+_op_(PMC_IMPL_L0L1A_RST_STATUS_0) \
+_op_(PMC_IMPL_DVDD_RG_CNTRL_0) \
+_op_(PMC_IMPL_CV_RG_CNTRL_0) \
+_op_(PMC_IMPL_SC7_RST_REQ_TIMER_0) \
+_op_(PMC_IMPL_RST_REQ_TIMER_0) \
+_op_(PMC_IMPL_ASYNC_RST_SC7_CONFIG_0) \
+_op_(PMC_IMPL_PMC_RESET_DETECTOR_0) \
+_op_(PMC_IMPL_LED_BREATHING_CTRL_0) \
+_op_(PMC_IMPL_LED_BREATHING_COUNTER0_0) \
+_op_(PMC_IMPL_LED_BREATHING_COUNTER1_0) \
+_op_(PMC_IMPL_LED_BREATHING_COUNTER2_0) \
+_op_(PMC_IMPL_LED_BREATHING_COUNTER3_0) \
+_op_(PMC_IMPL_LED_BREATHING_STATUS_0) \
+_op_(PMC_IMPL_DPD_AUX_CLAMP_0) \
+_op_(PMC_IMPL_L2_SOURCE_MASK_0) \
+_op_(PMC_IMPL_RAMDUMP_CTL_STATUS2_0) \
+_op_(PMC_IMPL_IO_DPD_FSM0_STATUS_0) \
+_op_(PMC_IMPL_IO_DPD_FSM1_STATUS_0) \
+_op_(PMC_IMPL_IO_DPD_FSM2_STATUS_0) \
+_op_(PMC_IMPL_IO_SYS_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_SYS_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_SYS_DPD_OFF_MASK_0) \
+_op_(PMC_IMPL_IO_AO_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_AO_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_AO_DPD_OFF_MASK_0) \
+_op_(PMC_IMPL_IO_DBG_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_DBG_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_G2_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_G2_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_G3_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_G3_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_G4_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_G4_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_G5_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_G5_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_SDMMC1_HV_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_SDMMC1_HV_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_EDP_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_EDP_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_UFS_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_UFS_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_PEX_CTL_A_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_PEX_CTL_A_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_QSPI_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_QSPI_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_G7_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_G7_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_AO_HV_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_AO_HV_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_AO_HV_DPD_OFF_MASK_0) \
+_op_(PMC_IMPL_IO_EQOS_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_EQOS_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_PEX_CTL_B_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_PEX_CTL_B_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_PEX_CTL_C_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_PEX_CTL_C_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_PEX_CLK_C_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_PEX_CLK_C_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_PEX_CLK_A_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_PEX_CLK_A_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_PEX_CLK_B_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_PEX_CLK_B_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_CSI_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_CSI_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_EMMC_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_EMMC_DPD_STATUS_0) \
+_op_(PMC_IMPL_IO_DISP_DPD_REQ_0) \
+_op_(PMC_IMPL_IO_DISP_DPD_STATUS_0) \
+_op_(PMC_IMPL_POD_SOC_CONFIG_0) \
+_op_(PMC_IMPL_POD_CV_CONFIG_0) \
+_op_(PMC_IMPL_POD_CPU_CONFIG_0) \
+_op_(PMC_IMPL_POD_GPU_CONFIG_0) \
+_op_(PMC_IMPL_POD_FSI_CONFIG_0) \
+_op_(PMC_IMPL_SCPM_RESET_EN_0) \
+_op_(PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0) \
+_op_(PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0) \
+_op_(PMC_IMPL_RTC_XTAL_SCPM_MASK_TIMING_PATH_0) \
+_op_(PMC_IMPL_RTC_XTAL_SCPM_DATAPATH_DEL_CHAR_0) \
+_op_(PMC_IMPL_RTC_XTAL_SCPM_STATUS_0) \
+_op_(PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0) \
+_op_(PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0) \
+_op_(PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_SEL_0_0) \
+_op_(PMC_IMPL_SOC_XTAL_SCPM_MASK_TIMING_PATH_0) \
+_op_(PMC_IMPL_SOC_XTAL_SCPM_DATAPATH_DEL_CHAR_0) \
+_op_(PMC_IMPL_SOC_XTAL_SCPM_STATUS_0) \
+_op_(PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_PMC_IMPL   0x00000000
+
+//
+// ARPMC_IMPL REGISTER BANKS
+//
+
+#define PMC_IMPL0_FIRST_REG 0x0000 // PMC_IMPL_CNTRL_0
+#define PMC_IMPL0_LAST_REG 0x0008 // PMC_IMPL_DPD_PADS_ORIDE_0
+#define PMC_IMPL1_FIRST_REG 0x0010 // PMC_IMPL_DPD_ENABLE_0
+#define PMC_IMPL1_LAST_REG 0x0034 // PMC_IMPL_NO_IOPOWER_0
+#define PMC_IMPL2_FIRST_REG 0x003c // PMC_IMPL_E_18V_PWR_0
+#define PMC_IMPL2_LAST_REG 0x0040 // PMC_IMPL_E_33V_PWR_0
+#define PMC_IMPL3_FIRST_REG 0x0060 // PMC_IMPL_OSC_EDPD_OVER_0
+#define PMC_IMPL3_LAST_REG 0x0064 // PMC_IMPL_CLK_OUT_CNTRL_0
+#define PMC_IMPL4_FIRST_REG 0x006c // PMC_IMPL_SENSOR_CTRL_0
+#define PMC_IMPL4_LAST_REG 0x0074 // PMC_IMPL_IO_DPD_REQ_0
+#define PMC_IMPL5_FIRST_REG 0x00bc // PMC_IMPL_SEL_DPD_TIM_0
+#define PMC_IMPL5_LAST_REG 0x00bc // PMC_IMPL_SEL_DPD_TIM_0
+#define PMC_IMPL6_FIRST_REG 0x00d4 // PMC_IMPL_TSC_MULT_0
+#define PMC_IMPL6_LAST_REG 0x00d8 // PMC_IMPL_GLB_AMAP_CFG_0
+#define PMC_IMPL7_FIRST_REG 0x00e8 // PMC_IMPL_GPU_RG_CNTRL_0
+#define PMC_IMPL7_LAST_REG 0x00e8 // PMC_IMPL_GPU_RG_CNTRL_0
+#define PMC_IMPL8_FIRST_REG 0x00f8 // PMC_IMPL_CNTRL2_0
+#define PMC_IMPL8_LAST_REG 0x00fc // PMC_IMPL_EVENT_COUNTER_0
+#define PMC_IMPL9_FIRST_REG 0x0104 // PMC_IMPL_DIRECT_THERMTRIP_CFG_0
+#define PMC_IMPL9_LAST_REG 0x0104 // PMC_IMPL_DIRECT_THERMTRIP_CFG_0
+#define PMC_IMPL10_FIRST_REG 0x010c // PMC_IMPL_RAMDUMP_CTL_STATUS_0
+#define PMC_IMPL10_LAST_REG 0x0118 // PMC_IMPL_RST_REQ_CNTVAL_0
+#define PMC_IMPL11_FIRST_REG 0x01d4 // PMC_IMPL_VFMON_ACTION_0
+#define PMC_IMPL11_LAST_REG 0x01dc // PMC_IMPL_VFMON_INT_MASK_0
+#define PMC_IMPL12_FIRST_REG 0x01ec // PMC_IMPL_POWER_GATE_TIMERS_0
+#define PMC_IMPL12_LAST_REG 0x0210 // PMC_IMPL_PART_AUD_CLAMP_CONTROL_0
+#define PMC_IMPL13_FIRST_REG 0x0220 // PMC_IMPL_PART_DISP_POWER_GATE_CONTROL_0
+#define PMC_IMPL13_LAST_REG 0x0228 // PMC_IMPL_PART_DISP_CLAMP_CONTROL_0
+#define PMC_IMPL14_FIRST_REG 0x0298 // PMC_IMPL_PART_VIC_POWER_GATE_CONTROL_0
+#define PMC_IMPL14_LAST_REG 0x02dc // PMC_IMPL_PART_AONPG_CLAMP_CONTROL_0
+#define PMC_IMPL15_FIRST_REG 0x0388 // PMC_IMPL_PART_AOPG_TCM0_POWER_GATE_CONTROL_0
+#define PMC_IMPL15_LAST_REG 0x0408 // PMC_IMPL_PART_AOPG_CAN1_CLAMP_CONTROL_0
+#define PMC_IMPL16_FIRST_REG 0x0418 // PMC_IMPL_PART_MSS_SCRATCH_POWER_GATE_CONTROL_0
+#define PMC_IMPL16_LAST_REG 0x0444 // PMC_IMPL_PART_PCIEX1A_CLAMP_CONTROL_0
+#define PMC_IMPL17_FIRST_REG 0x0454 // PMC_IMPL_PART_PCIEX8B_POWER_GATE_CONTROL_0
+#define PMC_IMPL17_LAST_REG 0x045c // PMC_IMPL_PART_PCIEX8B_CLAMP_CONTROL_0
+#define PMC_IMPL18_FIRST_REG 0x0478 // PMC_IMPL_PART_DLAA_POWER_GATE_CONTROL_0
+#define PMC_IMPL18_LAST_REG 0x048c // PMC_IMPL_PART_DLAB_CLAMP_CONTROL_0
+#define PMC_IMPL19_FIRST_REG 0x04c0 // PMC_IMPL_PART_ISP_POWER_GATE_CONTROL_0
+#define PMC_IMPL19_LAST_REG 0x06fc // PMC_IMPL_PART_FSIRAIL_PWRDWN_ACK_STATUS_0
+#define PMC_IMPL20_FIRST_REG 0x0800 // PMC_IMPL_PMC2LIC_INTR_STATUS_0
+#define PMC_IMPL20_LAST_REG 0x0810 // PMC_IMPL_TEST_CLK_MUX_SEL_0
+#define PMC_IMPL21_FIRST_REG 0x0818 // PMC_IMPL_SC7_FSM_STATUS_0
+#define PMC_IMPL21_LAST_REG 0x08e8 // PMC_IMPL_RAMDUMP_CTL_STATUS2_0
+#define PMC_IMPL22_FIRST_REG 0xe000 // PMC_IMPL_IO_DPD_FSM0_STATUS_0
+#define PMC_IMPL22_LAST_REG 0xe008 // PMC_IMPL_IO_DPD_FSM2_STATUS_0
+#define PMC_IMPL23_FIRST_REG 0xe014 // PMC_IMPL_IO_SYS_DPD_REQ_0
+#define PMC_IMPL23_LAST_REG 0xe0d4 // PMC_IMPL_IO_DISP_DPD_STATUS_0
+#define PMC_IMPL24_FIRST_REG 0xf000 // PMC_IMPL_POD_SOC_CONFIG_0
+#define PMC_IMPL24_LAST_REG 0xf01c // PMC_IMPL_POD_BE_MONITOR_0
+#define PMC_IMPL25_FIRST_REG 0xf800 // PMC_IMPL_SCPM_RESET_EN_0
+#define PMC_IMPL25_LAST_REG 0xf800 // PMC_IMPL_SCPM_RESET_EN_0
+#define PMC_IMPL26_FIRST_REG 0xf900 // PMC_IMPL_RTC_XTAL_SCPM_CONFIG_0
+#define PMC_IMPL26_LAST_REG 0xf914 // PMC_IMPL_RTC_XTAL_SCPM_RO_COUNT_0
+#define PMC_IMPL27_FIRST_REG 0xfa00 // PMC_IMPL_SOC_XTAL_SCPM_CONFIG_0
+#define PMC_IMPL27_LAST_REG 0xfa14 // PMC_IMPL_SOC_XTAL_SCPM_RO_COUNT_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARPMC_IMPL_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arscratch.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arscratch.h
new file mode 100644
index 0000000..b7c855f
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arscratch.h
@@ -0,0 +1,13622 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARSCRATCH_H_INC
+#define ARSCRATCH_H_INC
+#define NV_MOBILE_ARSCRATCH_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARSCRATCH_H_SCRREG_NOMENCLATURE INFERRED
+
+// Register SCRATCH_SECURE_BL_SCRATCH_0
+#define SCRATCH_SECURE_BL_SCRATCH_0                     MK_ADDR_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_0_SECURE                      0x0
+#define SCRATCH_SECURE_BL_SCRATCH_0_DUAL                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_0_SCR                         BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_0_SCRREG                      SCRATCH_SCR_BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_0_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_BL_SCRATCH_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_0_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_0_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_0_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_BL_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_BL_SCRATCH_0_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_BL_SCRATCH_0_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_BL_SCRATCH_0_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_0_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_0_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_0_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_0_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_0_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_0_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_0_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_BL_SCRATCH
+#define SCRATCH_SECURE_BL_SCRATCH                       MK_ADDR_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_SECURE                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_DUAL                  0x0
+#define SCRATCH_SECURE_BL_SCRATCH_SCR                   BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_SCRREG                        SCRATCH_SCR_BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_WORD_COUNT                    0x1
+#define SCRATCH_SECURE_BL_SCRATCH_RESET_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_DATA_SHIFT                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_DATA_FIELD                    MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_BL_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_BL_SCRATCH_DATA_RANGE                    31:0
+#define SCRATCH_SECURE_BL_SCRATCH_DATA_MSB                      MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_BL_SCRATCH_DATA_LSB                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_DATA_WOFFSET                  0x0
+#define SCRATCH_SECURE_BL_SCRATCH_DATA_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_DATA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_DATA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_DATA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_DATA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_DATA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_BL_SCRATCH_1
+#define SCRATCH_SECURE_BL_SCRATCH_1                     MK_ADDR_CONST(0x4)
+#define SCRATCH_SECURE_BL_SCRATCH_1_SECURE                      0x0
+#define SCRATCH_SECURE_BL_SCRATCH_1_DUAL                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_1_SCR                         BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_1_SCRREG                      SCRATCH_SCR_BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_1_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_BL_SCRATCH_1_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_1_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_1_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_1_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_1_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_1_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_1_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_BL_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_BL_SCRATCH_1_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_BL_SCRATCH_1_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_BL_SCRATCH_1_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_1_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_1_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_1_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_1_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_1_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_1_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_1_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_BL_SCRATCH_2
+#define SCRATCH_SECURE_BL_SCRATCH_2                     MK_ADDR_CONST(0x8)
+#define SCRATCH_SECURE_BL_SCRATCH_2_SECURE                      0x0
+#define SCRATCH_SECURE_BL_SCRATCH_2_DUAL                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_2_SCR                         BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_2_SCRREG                      SCRATCH_SCR_BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_2_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_BL_SCRATCH_2_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_2_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_2_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_2_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_2_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_2_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_2_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_BL_SCRATCH_2_DATA_SHIFT)
+#define SCRATCH_SECURE_BL_SCRATCH_2_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_BL_SCRATCH_2_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_BL_SCRATCH_2_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_2_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_2_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_2_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_2_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_2_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_2_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_2_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_BL_SCRATCH_3
+#define SCRATCH_SECURE_BL_SCRATCH_3                     MK_ADDR_CONST(0xc)
+#define SCRATCH_SECURE_BL_SCRATCH_3_SECURE                      0x0
+#define SCRATCH_SECURE_BL_SCRATCH_3_DUAL                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_3_SCR                         BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_3_SCRREG                      SCRATCH_SCR_BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_3_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_BL_SCRATCH_3_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_3_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_3_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_3_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_3_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_3_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_3_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_BL_SCRATCH_3_DATA_SHIFT)
+#define SCRATCH_SECURE_BL_SCRATCH_3_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_BL_SCRATCH_3_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_BL_SCRATCH_3_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_3_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_3_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_3_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_3_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_3_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_3_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_3_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_BL_SCRATCH_4
+#define SCRATCH_SECURE_BL_SCRATCH_4                     MK_ADDR_CONST(0x10)
+#define SCRATCH_SECURE_BL_SCRATCH_4_SECURE                      0x0
+#define SCRATCH_SECURE_BL_SCRATCH_4_DUAL                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_4_SCR                         BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_4_SCRREG                      SCRATCH_SCR_BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_4_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_BL_SCRATCH_4_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_4_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_4_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_4_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_4_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_4_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_4_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_BL_SCRATCH_4_DATA_SHIFT)
+#define SCRATCH_SECURE_BL_SCRATCH_4_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_BL_SCRATCH_4_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_BL_SCRATCH_4_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_4_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_4_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_4_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_4_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_4_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_4_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_4_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_BL_SCRATCH_5
+#define SCRATCH_SECURE_BL_SCRATCH_5                     MK_ADDR_CONST(0x14)
+#define SCRATCH_SECURE_BL_SCRATCH_5_SECURE                      0x0
+#define SCRATCH_SECURE_BL_SCRATCH_5_DUAL                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_5_SCR                         BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_5_SCRREG                      SCRATCH_SCR_BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_5_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_BL_SCRATCH_5_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_5_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_5_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_5_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_5_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_5_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_5_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_BL_SCRATCH_5_DATA_SHIFT)
+#define SCRATCH_SECURE_BL_SCRATCH_5_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_BL_SCRATCH_5_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_BL_SCRATCH_5_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_5_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_5_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_5_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_5_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_5_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_5_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_5_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_BL_SCRATCH_6
+#define SCRATCH_SECURE_BL_SCRATCH_6                     MK_ADDR_CONST(0x18)
+#define SCRATCH_SECURE_BL_SCRATCH_6_SECURE                      0x0
+#define SCRATCH_SECURE_BL_SCRATCH_6_DUAL                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_6_SCR                         BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_6_SCRREG                      SCRATCH_SCR_BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_6_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_BL_SCRATCH_6_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_6_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_6_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_6_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_6_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_6_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_6_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_BL_SCRATCH_6_DATA_SHIFT)
+#define SCRATCH_SECURE_BL_SCRATCH_6_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_BL_SCRATCH_6_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_BL_SCRATCH_6_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_6_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_6_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_6_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_6_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_6_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_6_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_6_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_BL_SCRATCH_7
+#define SCRATCH_SECURE_BL_SCRATCH_7                     MK_ADDR_CONST(0x1c)
+#define SCRATCH_SECURE_BL_SCRATCH_7_SECURE                      0x0
+#define SCRATCH_SECURE_BL_SCRATCH_7_DUAL                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_7_SCR                         BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_7_SCRREG                      SCRATCH_SCR_BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_7_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_BL_SCRATCH_7_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_7_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_7_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_7_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_7_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_7_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_7_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_BL_SCRATCH_7_DATA_SHIFT)
+#define SCRATCH_SECURE_BL_SCRATCH_7_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_BL_SCRATCH_7_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_BL_SCRATCH_7_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_7_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_7_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_7_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_7_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_7_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_7_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_7_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_BL_SCRATCH_8
+#define SCRATCH_SECURE_BL_SCRATCH_8                     MK_ADDR_CONST(0x20)
+#define SCRATCH_SECURE_BL_SCRATCH_8_SECURE                      0x0
+#define SCRATCH_SECURE_BL_SCRATCH_8_DUAL                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_8_SCR                         BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_8_SCRREG                      SCRATCH_SCR_BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_8_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_BL_SCRATCH_8_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_8_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_8_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_8_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_8_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_8_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_8_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_BL_SCRATCH_8_DATA_SHIFT)
+#define SCRATCH_SECURE_BL_SCRATCH_8_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_BL_SCRATCH_8_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_BL_SCRATCH_8_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_8_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_8_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_8_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_8_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_8_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_8_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_8_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_BL_SCRATCH_9
+#define SCRATCH_SECURE_BL_SCRATCH_9                     MK_ADDR_CONST(0x24)
+#define SCRATCH_SECURE_BL_SCRATCH_9_SECURE                      0x0
+#define SCRATCH_SECURE_BL_SCRATCH_9_DUAL                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_9_SCR                         BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_9_SCRREG                      SCRATCH_SCR_BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_9_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_BL_SCRATCH_9_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_9_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_9_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_9_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_9_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_9_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_9_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_9_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_BL_SCRATCH_9_DATA_SHIFT)
+#define SCRATCH_SECURE_BL_SCRATCH_9_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_BL_SCRATCH_9_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_BL_SCRATCH_9_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_9_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_BL_SCRATCH_9_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_9_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_9_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_9_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_9_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_9_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_BL_SCRATCH_10
+#define SCRATCH_SECURE_BL_SCRATCH_10                    MK_ADDR_CONST(0x28)
+#define SCRATCH_SECURE_BL_SCRATCH_10_SECURE                     0x0
+#define SCRATCH_SECURE_BL_SCRATCH_10_DUAL                       0x0
+#define SCRATCH_SECURE_BL_SCRATCH_10_SCR                        BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_10_SCRREG                     SCRATCH_SCR_BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_10_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_BL_SCRATCH_10_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_10_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_10_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_10_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_10_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_10_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_10_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_10_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_BL_SCRATCH_10_DATA_SHIFT)
+#define SCRATCH_SECURE_BL_SCRATCH_10_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_BL_SCRATCH_10_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_BL_SCRATCH_10_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_10_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_BL_SCRATCH_10_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_10_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_10_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_10_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_10_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_10_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_BL_SCRATCH_11
+#define SCRATCH_SECURE_BL_SCRATCH_11                    MK_ADDR_CONST(0x2c)
+#define SCRATCH_SECURE_BL_SCRATCH_11_SECURE                     0x0
+#define SCRATCH_SECURE_BL_SCRATCH_11_DUAL                       0x0
+#define SCRATCH_SECURE_BL_SCRATCH_11_SCR                        BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_11_SCRREG                     SCRATCH_SCR_BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_11_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_BL_SCRATCH_11_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_11_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_11_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_11_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_11_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_11_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_11_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_11_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_BL_SCRATCH_11_DATA_SHIFT)
+#define SCRATCH_SECURE_BL_SCRATCH_11_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_BL_SCRATCH_11_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_BL_SCRATCH_11_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_11_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_BL_SCRATCH_11_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_11_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_11_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_11_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_11_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_11_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_BL_SCRATCH_12
+#define SCRATCH_SECURE_BL_SCRATCH_12                    MK_ADDR_CONST(0x30)
+#define SCRATCH_SECURE_BL_SCRATCH_12_SECURE                     0x0
+#define SCRATCH_SECURE_BL_SCRATCH_12_DUAL                       0x0
+#define SCRATCH_SECURE_BL_SCRATCH_12_SCR                        BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_12_SCRREG                     SCRATCH_SCR_BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_12_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_BL_SCRATCH_12_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_12_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_12_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_12_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_12_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_12_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_12_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_12_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_BL_SCRATCH_12_DATA_SHIFT)
+#define SCRATCH_SECURE_BL_SCRATCH_12_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_BL_SCRATCH_12_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_BL_SCRATCH_12_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_12_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_BL_SCRATCH_12_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_12_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_12_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_12_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_12_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_12_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_BL_SCRATCH_13
+#define SCRATCH_SECURE_BL_SCRATCH_13                    MK_ADDR_CONST(0x34)
+#define SCRATCH_SECURE_BL_SCRATCH_13_SECURE                     0x0
+#define SCRATCH_SECURE_BL_SCRATCH_13_DUAL                       0x0
+#define SCRATCH_SECURE_BL_SCRATCH_13_SCR                        BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_13_SCRREG                     SCRATCH_SCR_BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_13_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_BL_SCRATCH_13_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_13_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_13_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_13_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_13_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_13_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_13_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_13_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_BL_SCRATCH_13_DATA_SHIFT)
+#define SCRATCH_SECURE_BL_SCRATCH_13_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_BL_SCRATCH_13_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_BL_SCRATCH_13_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_13_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_BL_SCRATCH_13_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_13_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_13_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_13_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_13_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_13_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_BL_SCRATCH_14
+#define SCRATCH_SECURE_BL_SCRATCH_14                    MK_ADDR_CONST(0x38)
+#define SCRATCH_SECURE_BL_SCRATCH_14_SECURE                     0x0
+#define SCRATCH_SECURE_BL_SCRATCH_14_DUAL                       0x0
+#define SCRATCH_SECURE_BL_SCRATCH_14_SCR                        BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_14_SCRREG                     SCRATCH_SCR_BL_SCR_0
+#define SCRATCH_SECURE_BL_SCRATCH_14_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_BL_SCRATCH_14_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_14_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_14_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_14_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_14_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_14_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_14_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_14_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_BL_SCRATCH_14_DATA_SHIFT)
+#define SCRATCH_SECURE_BL_SCRATCH_14_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_BL_SCRATCH_14_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_BL_SCRATCH_14_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_BL_SCRATCH_14_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_BL_SCRATCH_14_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_14_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_BL_SCRATCH_14_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_14_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_14_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_BL_SCRATCH_14_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_MTS_SCRATCH_0
+#define SCRATCH_SECURE_MTS_SCRATCH_0                    MK_ADDR_CONST(0x3c)
+#define SCRATCH_SECURE_MTS_SCRATCH_0_SECURE                     0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_0_DUAL                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_0_SCR                        MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_0_SCRREG                     SCRATCH_SCR_MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_0_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_MTS_SCRATCH_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_MTS_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_MTS_SCRATCH_0_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_MTS_SCRATCH_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_MTS_SCRATCH_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_0_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_MTS_SCRATCH
+#define SCRATCH_SECURE_MTS_SCRATCH                      MK_ADDR_CONST(0x3c)
+#define SCRATCH_SECURE_MTS_SCRATCH_SECURE                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_DUAL                         0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_SCR                  MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_SCRREG                       SCRATCH_SCR_MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_WORD_COUNT                   0x1
+#define SCRATCH_SECURE_MTS_SCRATCH_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_MTS_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_MTS_SCRATCH_DATA_RANGE                   31:0
+#define SCRATCH_SECURE_MTS_SCRATCH_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_MTS_SCRATCH_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_DATA_WOFFSET                 0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_MTS_SCRATCH_1
+#define SCRATCH_SECURE_MTS_SCRATCH_1                    MK_ADDR_CONST(0x40)
+#define SCRATCH_SECURE_MTS_SCRATCH_1_SECURE                     0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_1_DUAL                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_1_SCR                        MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_1_SCRREG                     SCRATCH_SCR_MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_1_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_MTS_SCRATCH_1_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_1_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_1_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_1_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_1_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_1_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_1_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_MTS_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_MTS_SCRATCH_1_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_MTS_SCRATCH_1_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_MTS_SCRATCH_1_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_1_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_1_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_1_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_1_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_1_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_1_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_1_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_MTS_SCRATCH_2
+#define SCRATCH_SECURE_MTS_SCRATCH_2                    MK_ADDR_CONST(0x44)
+#define SCRATCH_SECURE_MTS_SCRATCH_2_SECURE                     0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_2_DUAL                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_2_SCR                        MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_2_SCRREG                     SCRATCH_SCR_MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_2_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_MTS_SCRATCH_2_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_2_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_2_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_2_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_2_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_2_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_2_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_MTS_SCRATCH_2_DATA_SHIFT)
+#define SCRATCH_SECURE_MTS_SCRATCH_2_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_MTS_SCRATCH_2_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_MTS_SCRATCH_2_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_2_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_2_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_2_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_2_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_2_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_2_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_2_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_MTS_SCRATCH_3
+#define SCRATCH_SECURE_MTS_SCRATCH_3                    MK_ADDR_CONST(0x48)
+#define SCRATCH_SECURE_MTS_SCRATCH_3_SECURE                     0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_3_DUAL                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_3_SCR                        MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_3_SCRREG                     SCRATCH_SCR_MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_3_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_MTS_SCRATCH_3_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_3_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_3_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_3_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_3_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_3_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_3_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_MTS_SCRATCH_3_DATA_SHIFT)
+#define SCRATCH_SECURE_MTS_SCRATCH_3_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_MTS_SCRATCH_3_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_MTS_SCRATCH_3_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_3_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_3_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_3_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_3_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_3_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_3_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_3_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_MTS_SCRATCH_4
+#define SCRATCH_SECURE_MTS_SCRATCH_4                    MK_ADDR_CONST(0x4c)
+#define SCRATCH_SECURE_MTS_SCRATCH_4_SECURE                     0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_4_DUAL                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_4_SCR                        MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_4_SCRREG                     SCRATCH_SCR_MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_4_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_MTS_SCRATCH_4_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_4_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_4_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_4_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_4_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_4_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_4_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_MTS_SCRATCH_4_DATA_SHIFT)
+#define SCRATCH_SECURE_MTS_SCRATCH_4_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_MTS_SCRATCH_4_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_MTS_SCRATCH_4_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_4_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_4_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_4_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_4_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_4_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_4_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_4_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_MTS_SCRATCH_5
+#define SCRATCH_SECURE_MTS_SCRATCH_5                    MK_ADDR_CONST(0x50)
+#define SCRATCH_SECURE_MTS_SCRATCH_5_SECURE                     0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_5_DUAL                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_5_SCR                        MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_5_SCRREG                     SCRATCH_SCR_MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_5_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_MTS_SCRATCH_5_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_5_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_5_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_5_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_5_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_5_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_5_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_MTS_SCRATCH_5_DATA_SHIFT)
+#define SCRATCH_SECURE_MTS_SCRATCH_5_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_MTS_SCRATCH_5_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_MTS_SCRATCH_5_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_5_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_5_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_5_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_5_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_5_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_5_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_5_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_MTS_SCRATCH_6
+#define SCRATCH_SECURE_MTS_SCRATCH_6                    MK_ADDR_CONST(0x54)
+#define SCRATCH_SECURE_MTS_SCRATCH_6_SECURE                     0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_6_DUAL                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_6_SCR                        MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_6_SCRREG                     SCRATCH_SCR_MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_6_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_MTS_SCRATCH_6_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_6_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_6_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_6_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_6_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_6_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_6_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_MTS_SCRATCH_6_DATA_SHIFT)
+#define SCRATCH_SECURE_MTS_SCRATCH_6_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_MTS_SCRATCH_6_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_MTS_SCRATCH_6_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_6_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_6_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_6_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_6_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_6_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_6_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_6_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_MTS_SCRATCH_7
+#define SCRATCH_SECURE_MTS_SCRATCH_7                    MK_ADDR_CONST(0x58)
+#define SCRATCH_SECURE_MTS_SCRATCH_7_SECURE                     0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_7_DUAL                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_7_SCR                        MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_7_SCRREG                     SCRATCH_SCR_MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_7_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_MTS_SCRATCH_7_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_7_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_7_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_7_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_7_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_7_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_7_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_MTS_SCRATCH_7_DATA_SHIFT)
+#define SCRATCH_SECURE_MTS_SCRATCH_7_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_MTS_SCRATCH_7_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_MTS_SCRATCH_7_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_7_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_7_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_7_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_7_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_7_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_7_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_7_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_MTS_SCRATCH_8
+#define SCRATCH_SECURE_MTS_SCRATCH_8                    MK_ADDR_CONST(0x5c)
+#define SCRATCH_SECURE_MTS_SCRATCH_8_SECURE                     0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_8_DUAL                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_8_SCR                        MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_8_SCRREG                     SCRATCH_SCR_MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_8_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_MTS_SCRATCH_8_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_8_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_8_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_8_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_8_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_8_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_8_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_8_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_MTS_SCRATCH_8_DATA_SHIFT)
+#define SCRATCH_SECURE_MTS_SCRATCH_8_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_MTS_SCRATCH_8_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_MTS_SCRATCH_8_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_8_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_8_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_8_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_8_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_8_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_8_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_8_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_MTS_SCRATCH_9
+#define SCRATCH_SECURE_MTS_SCRATCH_9                    MK_ADDR_CONST(0x60)
+#define SCRATCH_SECURE_MTS_SCRATCH_9_SECURE                     0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_9_DUAL                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_9_SCR                        MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_9_SCRREG                     SCRATCH_SCR_MTS_SCR_0
+#define SCRATCH_SECURE_MTS_SCRATCH_9_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_MTS_SCRATCH_9_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_9_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_9_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_9_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_9_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_9_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_9_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_9_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_MTS_SCRATCH_9_DATA_SHIFT)
+#define SCRATCH_SECURE_MTS_SCRATCH_9_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_MTS_SCRATCH_9_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_MTS_SCRATCH_9_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_MTS_SCRATCH_9_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_MTS_SCRATCH_9_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_9_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_MTS_SCRATCH_9_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_9_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_9_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_MTS_SCRATCH_9_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV0_SCRATCH_0
+#define SCRATCH_SECURE_RSV0_SCRATCH_0                   MK_ADDR_CONST(0x64)
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_SECURE                    0x0
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_DUAL                      0x0
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_SCR                       RSV0_SCR_0
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_SCRREG                    SCRATCH_SCR_RSV0_SCR_0
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV0_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_0_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV0_SCRATCH
+#define SCRATCH_SECURE_RSV0_SCRATCH                     MK_ADDR_CONST(0x64)
+#define SCRATCH_SECURE_RSV0_SCRATCH_SECURE                      0x0
+#define SCRATCH_SECURE_RSV0_SCRATCH_DUAL                        0x0
+#define SCRATCH_SECURE_RSV0_SCRATCH_SCR                         RSV0_SCR_0
+#define SCRATCH_SECURE_RSV0_SCRATCH_SCRREG                      SCRATCH_SCR_RSV0_SCR_0
+#define SCRATCH_SECURE_RSV0_SCRATCH_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_RSV0_SCRATCH_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV0_SCRATCH_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV0_SCRATCH_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV0_SCRATCH_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV0_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV0_SCRATCH_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_RSV0_SCRATCH_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV0_SCRATCH_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_RSV0_SCRATCH_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV0_SCRATCH_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV0_SCRATCH_1
+#define SCRATCH_SECURE_RSV0_SCRATCH_1                   MK_ADDR_CONST(0x68)
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_SECURE                    0x0
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_DUAL                      0x0
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_SCR                       RSV0_SCR_0
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_SCRREG                    SCRATCH_SCR_RSV0_SCR_0
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV0_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV0_SCRATCH_1_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV1_SCRATCH_0
+#define SCRATCH_SECURE_RSV1_SCRATCH_0                   MK_ADDR_CONST(0x6c)
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_SECURE                    0x0
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_DUAL                      0x0
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_SCR                       RSV1_SCR_0
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_SCRREG                    SCRATCH_SCR_RSV1_SCR_0
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV1_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_0_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV1_SCRATCH
+#define SCRATCH_SECURE_RSV1_SCRATCH                     MK_ADDR_CONST(0x6c)
+#define SCRATCH_SECURE_RSV1_SCRATCH_SECURE                      0x0
+#define SCRATCH_SECURE_RSV1_SCRATCH_DUAL                        0x0
+#define SCRATCH_SECURE_RSV1_SCRATCH_SCR                         RSV1_SCR_0
+#define SCRATCH_SECURE_RSV1_SCRATCH_SCRREG                      SCRATCH_SCR_RSV1_SCR_0
+#define SCRATCH_SECURE_RSV1_SCRATCH_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_RSV1_SCRATCH_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV1_SCRATCH_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV1_SCRATCH_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV1_SCRATCH_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV1_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV1_SCRATCH_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_RSV1_SCRATCH_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV1_SCRATCH_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_RSV1_SCRATCH_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV1_SCRATCH_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV1_SCRATCH_1
+#define SCRATCH_SECURE_RSV1_SCRATCH_1                   MK_ADDR_CONST(0x70)
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_SECURE                    0x0
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_DUAL                      0x0
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_SCR                       RSV1_SCR_0
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_SCRREG                    SCRATCH_SCR_RSV1_SCR_0
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV1_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV1_SCRATCH_1_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV2_SCRATCH_0
+#define SCRATCH_SECURE_RSV2_SCRATCH_0                   MK_ADDR_CONST(0x74)
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_SECURE                    0x0
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_DUAL                      0x0
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_SCR                       RSV2_SCR_0
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_SCRREG                    SCRATCH_SCR_RSV2_SCR_0
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV2_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_0_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV2_SCRATCH
+#define SCRATCH_SECURE_RSV2_SCRATCH                     MK_ADDR_CONST(0x74)
+#define SCRATCH_SECURE_RSV2_SCRATCH_SECURE                      0x0
+#define SCRATCH_SECURE_RSV2_SCRATCH_DUAL                        0x0
+#define SCRATCH_SECURE_RSV2_SCRATCH_SCR                         RSV2_SCR_0
+#define SCRATCH_SECURE_RSV2_SCRATCH_SCRREG                      SCRATCH_SCR_RSV2_SCR_0
+#define SCRATCH_SECURE_RSV2_SCRATCH_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_RSV2_SCRATCH_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV2_SCRATCH_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV2_SCRATCH_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV2_SCRATCH_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV2_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV2_SCRATCH_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_RSV2_SCRATCH_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV2_SCRATCH_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_RSV2_SCRATCH_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV2_SCRATCH_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV2_SCRATCH_1
+#define SCRATCH_SECURE_RSV2_SCRATCH_1                   MK_ADDR_CONST(0x78)
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_SECURE                    0x0
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_DUAL                      0x0
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_SCR                       RSV2_SCR_0
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_SCRREG                    SCRATCH_SCR_RSV2_SCR_0
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV2_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV2_SCRATCH_1_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV3_SCRATCH_0
+#define SCRATCH_SECURE_RSV3_SCRATCH_0                   MK_ADDR_CONST(0x7c)
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_SECURE                    0x0
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_DUAL                      0x0
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_SCR                       RSV3_SCR_0
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_SCRREG                    SCRATCH_SCR_RSV3_SCR_0
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV3_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_0_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV3_SCRATCH
+#define SCRATCH_SECURE_RSV3_SCRATCH                     MK_ADDR_CONST(0x7c)
+#define SCRATCH_SECURE_RSV3_SCRATCH_SECURE                      0x0
+#define SCRATCH_SECURE_RSV3_SCRATCH_DUAL                        0x0
+#define SCRATCH_SECURE_RSV3_SCRATCH_SCR                         RSV3_SCR_0
+#define SCRATCH_SECURE_RSV3_SCRATCH_SCRREG                      SCRATCH_SCR_RSV3_SCR_0
+#define SCRATCH_SECURE_RSV3_SCRATCH_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_RSV3_SCRATCH_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV3_SCRATCH_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV3_SCRATCH_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV3_SCRATCH_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV3_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV3_SCRATCH_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_RSV3_SCRATCH_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV3_SCRATCH_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_RSV3_SCRATCH_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV3_SCRATCH_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV3_SCRATCH_1
+#define SCRATCH_SECURE_RSV3_SCRATCH_1                   MK_ADDR_CONST(0x80)
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_SECURE                    0x0
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_DUAL                      0x0
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_SCR                       RSV3_SCR_0
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_SCRREG                    SCRATCH_SCR_RSV3_SCR_0
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV3_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV3_SCRATCH_1_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV4_SCRATCH_0
+#define SCRATCH_SECURE_RSV4_SCRATCH_0                   MK_ADDR_CONST(0x84)
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_SECURE                    0x0
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_DUAL                      0x0
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_SCR                       RSV4_SCR_0
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_SCRREG                    SCRATCH_SCR_RSV4_SCR_0
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV4_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_0_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV4_SCRATCH
+#define SCRATCH_SECURE_RSV4_SCRATCH                     MK_ADDR_CONST(0x84)
+#define SCRATCH_SECURE_RSV4_SCRATCH_SECURE                      0x0
+#define SCRATCH_SECURE_RSV4_SCRATCH_DUAL                        0x0
+#define SCRATCH_SECURE_RSV4_SCRATCH_SCR                         RSV4_SCR_0
+#define SCRATCH_SECURE_RSV4_SCRATCH_SCRREG                      SCRATCH_SCR_RSV4_SCR_0
+#define SCRATCH_SECURE_RSV4_SCRATCH_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_RSV4_SCRATCH_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV4_SCRATCH_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV4_SCRATCH_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV4_SCRATCH_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV4_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV4_SCRATCH_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_RSV4_SCRATCH_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV4_SCRATCH_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_RSV4_SCRATCH_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV4_SCRATCH_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV4_SCRATCH_1
+#define SCRATCH_SECURE_RSV4_SCRATCH_1                   MK_ADDR_CONST(0x88)
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_SECURE                    0x0
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_DUAL                      0x0
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_SCR                       RSV4_SCR_0
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_SCRREG                    SCRATCH_SCR_RSV4_SCR_0
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV4_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV4_SCRATCH_1_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV5_SCRATCH_0
+#define SCRATCH_SECURE_RSV5_SCRATCH_0                   MK_ADDR_CONST(0x8c)
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_SECURE                    0x0
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_DUAL                      0x0
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_SCR                       RSV5_SCR_0
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_SCRREG                    SCRATCH_SCR_RSV5_SCR_0
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV5_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_0_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV5_SCRATCH
+#define SCRATCH_SECURE_RSV5_SCRATCH                     MK_ADDR_CONST(0x8c)
+#define SCRATCH_SECURE_RSV5_SCRATCH_SECURE                      0x0
+#define SCRATCH_SECURE_RSV5_SCRATCH_DUAL                        0x0
+#define SCRATCH_SECURE_RSV5_SCRATCH_SCR                         RSV5_SCR_0
+#define SCRATCH_SECURE_RSV5_SCRATCH_SCRREG                      SCRATCH_SCR_RSV5_SCR_0
+#define SCRATCH_SECURE_RSV5_SCRATCH_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_RSV5_SCRATCH_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV5_SCRATCH_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV5_SCRATCH_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV5_SCRATCH_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV5_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV5_SCRATCH_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_RSV5_SCRATCH_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV5_SCRATCH_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_RSV5_SCRATCH_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV5_SCRATCH_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV5_SCRATCH_1
+#define SCRATCH_SECURE_RSV5_SCRATCH_1                   MK_ADDR_CONST(0x90)
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_SECURE                    0x0
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_DUAL                      0x0
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_SCR                       RSV5_SCR_0
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_SCRREG                    SCRATCH_SCR_RSV5_SCR_0
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV5_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV5_SCRATCH_1_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV6_SCRATCH_0
+#define SCRATCH_SECURE_RSV6_SCRATCH_0                   MK_ADDR_CONST(0x94)
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_SECURE                    0x0
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_DUAL                      0x0
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_SCR                       RSV6_SCR_0
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_SCRREG                    SCRATCH_SCR_RSV6_SCR_0
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV6_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_0_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV6_SCRATCH
+#define SCRATCH_SECURE_RSV6_SCRATCH                     MK_ADDR_CONST(0x94)
+#define SCRATCH_SECURE_RSV6_SCRATCH_SECURE                      0x0
+#define SCRATCH_SECURE_RSV6_SCRATCH_DUAL                        0x0
+#define SCRATCH_SECURE_RSV6_SCRATCH_SCR                         RSV6_SCR_0
+#define SCRATCH_SECURE_RSV6_SCRATCH_SCRREG                      SCRATCH_SCR_RSV6_SCR_0
+#define SCRATCH_SECURE_RSV6_SCRATCH_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_RSV6_SCRATCH_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV6_SCRATCH_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV6_SCRATCH_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV6_SCRATCH_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV6_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV6_SCRATCH_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_RSV6_SCRATCH_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV6_SCRATCH_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_RSV6_SCRATCH_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV6_SCRATCH_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV6_SCRATCH_1
+#define SCRATCH_SECURE_RSV6_SCRATCH_1                   MK_ADDR_CONST(0x98)
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_SECURE                    0x0
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_DUAL                      0x0
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_SCR                       RSV6_SCR_0
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_SCRREG                    SCRATCH_SCR_RSV6_SCR_0
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV6_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV6_SCRATCH_1_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV7_SCRATCH_0
+#define SCRATCH_SECURE_RSV7_SCRATCH_0                   MK_ADDR_CONST(0x9c)
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_SECURE                    0x0
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_DUAL                      0x0
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_SCR                       RSV7_SCR_0
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_SCRREG                    SCRATCH_SCR_RSV7_SCR_0
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV7_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_0_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV7_SCRATCH
+#define SCRATCH_SECURE_RSV7_SCRATCH                     MK_ADDR_CONST(0x9c)
+#define SCRATCH_SECURE_RSV7_SCRATCH_SECURE                      0x0
+#define SCRATCH_SECURE_RSV7_SCRATCH_DUAL                        0x0
+#define SCRATCH_SECURE_RSV7_SCRATCH_SCR                         RSV7_SCR_0
+#define SCRATCH_SECURE_RSV7_SCRATCH_SCRREG                      SCRATCH_SCR_RSV7_SCR_0
+#define SCRATCH_SECURE_RSV7_SCRATCH_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_RSV7_SCRATCH_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV7_SCRATCH_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV7_SCRATCH_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV7_SCRATCH_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV7_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV7_SCRATCH_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_RSV7_SCRATCH_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV7_SCRATCH_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_RSV7_SCRATCH_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV7_SCRATCH_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV7_SCRATCH_1
+#define SCRATCH_SECURE_RSV7_SCRATCH_1                   MK_ADDR_CONST(0xa0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_SECURE                    0x0
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_DUAL                      0x0
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_SCR                       RSV7_SCR_0
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_SCRREG                    SCRATCH_SCR_RSV7_SCR_0
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV7_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV7_SCRATCH_1_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV8_SCRATCH_0
+#define SCRATCH_SECURE_RSV8_SCRATCH_0                   MK_ADDR_CONST(0xa4)
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_SECURE                    0x0
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_DUAL                      0x0
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_SCR                       RSV8_SCR_0
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_SCRREG                    SCRATCH_SCR_RSV8_SCR_0
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV8_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_0_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV8_SCRATCH
+#define SCRATCH_SECURE_RSV8_SCRATCH                     MK_ADDR_CONST(0xa4)
+#define SCRATCH_SECURE_RSV8_SCRATCH_SECURE                      0x0
+#define SCRATCH_SECURE_RSV8_SCRATCH_DUAL                        0x0
+#define SCRATCH_SECURE_RSV8_SCRATCH_SCR                         RSV8_SCR_0
+#define SCRATCH_SECURE_RSV8_SCRATCH_SCRREG                      SCRATCH_SCR_RSV8_SCR_0
+#define SCRATCH_SECURE_RSV8_SCRATCH_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_RSV8_SCRATCH_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV8_SCRATCH_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV8_SCRATCH_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV8_SCRATCH_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV8_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV8_SCRATCH_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_RSV8_SCRATCH_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV8_SCRATCH_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_RSV8_SCRATCH_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV8_SCRATCH_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV8_SCRATCH_1
+#define SCRATCH_SECURE_RSV8_SCRATCH_1                   MK_ADDR_CONST(0xa8)
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_SECURE                    0x0
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_DUAL                      0x0
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_SCR                       RSV8_SCR_0
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_SCRREG                    SCRATCH_SCR_RSV8_SCR_0
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV8_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV8_SCRATCH_1_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV9_SCRATCH_0
+#define SCRATCH_SECURE_RSV9_SCRATCH_0                   MK_ADDR_CONST(0xac)
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_SECURE                    0x0
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_DUAL                      0x0
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_SCR                       RSV9_SCR_0
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_SCRREG                    SCRATCH_SCR_RSV9_SCR_0
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV9_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_0_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV9_SCRATCH
+#define SCRATCH_SECURE_RSV9_SCRATCH                     MK_ADDR_CONST(0xac)
+#define SCRATCH_SECURE_RSV9_SCRATCH_SECURE                      0x0
+#define SCRATCH_SECURE_RSV9_SCRATCH_DUAL                        0x0
+#define SCRATCH_SECURE_RSV9_SCRATCH_SCR                         RSV9_SCR_0
+#define SCRATCH_SECURE_RSV9_SCRATCH_SCRREG                      SCRATCH_SCR_RSV9_SCR_0
+#define SCRATCH_SECURE_RSV9_SCRATCH_WORD_COUNT                  0x1
+#define SCRATCH_SECURE_RSV9_SCRATCH_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV9_SCRATCH_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV9_SCRATCH_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV9_SCRATCH_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV9_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV9_SCRATCH_DATA_RANGE                  31:0
+#define SCRATCH_SECURE_RSV9_SCRATCH_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV9_SCRATCH_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_DATA_WOFFSET                        0x0
+#define SCRATCH_SECURE_RSV9_SCRATCH_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV9_SCRATCH_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV9_SCRATCH_1
+#define SCRATCH_SECURE_RSV9_SCRATCH_1                   MK_ADDR_CONST(0xb0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_SECURE                    0x0
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_DUAL                      0x0
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_SCR                       RSV9_SCR_0
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_SCRREG                    SCRATCH_SCR_RSV9_SCR_0
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV9_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV9_SCRATCH_1_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV10_SCRATCH_0
+#define SCRATCH_SECURE_RSV10_SCRATCH_0                  MK_ADDR_CONST(0xb4)
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_SCR                      RSV10_SCR_0
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV10_SCR_0
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV10_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV10_SCRATCH
+#define SCRATCH_SECURE_RSV10_SCRATCH                    MK_ADDR_CONST(0xb4)
+#define SCRATCH_SECURE_RSV10_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV10_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV10_SCRATCH_SCR                        RSV10_SCR_0
+#define SCRATCH_SECURE_RSV10_SCRATCH_SCRREG                     SCRATCH_SCR_RSV10_SCR_0
+#define SCRATCH_SECURE_RSV10_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV10_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV10_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV10_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV10_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV10_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV10_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV10_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV10_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV10_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV10_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV10_SCRATCH_1
+#define SCRATCH_SECURE_RSV10_SCRATCH_1                  MK_ADDR_CONST(0xb8)
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_SCR                      RSV10_SCR_0
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV10_SCR_0
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV10_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV10_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV11_SCRATCH_0
+#define SCRATCH_SECURE_RSV11_SCRATCH_0                  MK_ADDR_CONST(0xbc)
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_SCR                      RSV11_SCR_0
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV11_SCR_0
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV11_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV11_SCRATCH
+#define SCRATCH_SECURE_RSV11_SCRATCH                    MK_ADDR_CONST(0xbc)
+#define SCRATCH_SECURE_RSV11_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV11_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV11_SCRATCH_SCR                        RSV11_SCR_0
+#define SCRATCH_SECURE_RSV11_SCRATCH_SCRREG                     SCRATCH_SCR_RSV11_SCR_0
+#define SCRATCH_SECURE_RSV11_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV11_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV11_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV11_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV11_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV11_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV11_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV11_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV11_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV11_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV11_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV11_SCRATCH_1
+#define SCRATCH_SECURE_RSV11_SCRATCH_1                  MK_ADDR_CONST(0xc0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_SCR                      RSV11_SCR_0
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV11_SCR_0
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV11_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV11_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV12_SCRATCH_0
+#define SCRATCH_SECURE_RSV12_SCRATCH_0                  MK_ADDR_CONST(0xc4)
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_SCR                      RSV12_SCR_0
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV12_SCR_0
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV12_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV12_SCRATCH
+#define SCRATCH_SECURE_RSV12_SCRATCH                    MK_ADDR_CONST(0xc4)
+#define SCRATCH_SECURE_RSV12_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV12_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV12_SCRATCH_SCR                        RSV12_SCR_0
+#define SCRATCH_SECURE_RSV12_SCRATCH_SCRREG                     SCRATCH_SCR_RSV12_SCR_0
+#define SCRATCH_SECURE_RSV12_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV12_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV12_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV12_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV12_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV12_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV12_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV12_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV12_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV12_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV12_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV12_SCRATCH_1
+#define SCRATCH_SECURE_RSV12_SCRATCH_1                  MK_ADDR_CONST(0xc8)
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_SCR                      RSV12_SCR_0
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV12_SCR_0
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV12_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV12_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV13_SCRATCH_0
+#define SCRATCH_SECURE_RSV13_SCRATCH_0                  MK_ADDR_CONST(0xcc)
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_SCR                      RSV13_SCR_0
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV13_SCR_0
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV13_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV13_SCRATCH
+#define SCRATCH_SECURE_RSV13_SCRATCH                    MK_ADDR_CONST(0xcc)
+#define SCRATCH_SECURE_RSV13_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV13_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV13_SCRATCH_SCR                        RSV13_SCR_0
+#define SCRATCH_SECURE_RSV13_SCRATCH_SCRREG                     SCRATCH_SCR_RSV13_SCR_0
+#define SCRATCH_SECURE_RSV13_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV13_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV13_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV13_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV13_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV13_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV13_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV13_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV13_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV13_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV13_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV13_SCRATCH_1
+#define SCRATCH_SECURE_RSV13_SCRATCH_1                  MK_ADDR_CONST(0xd0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_SCR                      RSV13_SCR_0
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV13_SCR_0
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV13_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV13_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV14_SCRATCH_0
+#define SCRATCH_SECURE_RSV14_SCRATCH_0                  MK_ADDR_CONST(0xd4)
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_SCR                      RSV14_SCR_0
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV14_SCR_0
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV14_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV14_SCRATCH
+#define SCRATCH_SECURE_RSV14_SCRATCH                    MK_ADDR_CONST(0xd4)
+#define SCRATCH_SECURE_RSV14_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV14_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV14_SCRATCH_SCR                        RSV14_SCR_0
+#define SCRATCH_SECURE_RSV14_SCRATCH_SCRREG                     SCRATCH_SCR_RSV14_SCR_0
+#define SCRATCH_SECURE_RSV14_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV14_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV14_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV14_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV14_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV14_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV14_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV14_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV14_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV14_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV14_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV14_SCRATCH_1
+#define SCRATCH_SECURE_RSV14_SCRATCH_1                  MK_ADDR_CONST(0xd8)
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_SCR                      RSV14_SCR_0
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV14_SCR_0
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV14_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV14_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV15_SCRATCH_0
+#define SCRATCH_SECURE_RSV15_SCRATCH_0                  MK_ADDR_CONST(0xdc)
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_SCR                      RSV15_SCR_0
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV15_SCR_0
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV15_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV15_SCRATCH
+#define SCRATCH_SECURE_RSV15_SCRATCH                    MK_ADDR_CONST(0xdc)
+#define SCRATCH_SECURE_RSV15_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV15_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV15_SCRATCH_SCR                        RSV15_SCR_0
+#define SCRATCH_SECURE_RSV15_SCRATCH_SCRREG                     SCRATCH_SCR_RSV15_SCR_0
+#define SCRATCH_SECURE_RSV15_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV15_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV15_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV15_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV15_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV15_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV15_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV15_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV15_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV15_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV15_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV15_SCRATCH_1
+#define SCRATCH_SECURE_RSV15_SCRATCH_1                  MK_ADDR_CONST(0xe0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_SCR                      RSV15_SCR_0
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV15_SCR_0
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV15_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV15_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV16_SCRATCH_0
+#define SCRATCH_SECURE_RSV16_SCRATCH_0                  MK_ADDR_CONST(0xe4)
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_SCR                      RSV16_SCR_0
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV16_SCR_0
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV16_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV16_SCRATCH
+#define SCRATCH_SECURE_RSV16_SCRATCH                    MK_ADDR_CONST(0xe4)
+#define SCRATCH_SECURE_RSV16_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV16_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV16_SCRATCH_SCR                        RSV16_SCR_0
+#define SCRATCH_SECURE_RSV16_SCRATCH_SCRREG                     SCRATCH_SCR_RSV16_SCR_0
+#define SCRATCH_SECURE_RSV16_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV16_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV16_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV16_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV16_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV16_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV16_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV16_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV16_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV16_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV16_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV16_SCRATCH_1
+#define SCRATCH_SECURE_RSV16_SCRATCH_1                  MK_ADDR_CONST(0xe8)
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_SCR                      RSV16_SCR_0
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV16_SCR_0
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV16_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV16_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV17_SCRATCH_0
+#define SCRATCH_SECURE_RSV17_SCRATCH_0                  MK_ADDR_CONST(0xec)
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_SCR                      RSV17_SCR_0
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV17_SCR_0
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV17_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV17_SCRATCH
+#define SCRATCH_SECURE_RSV17_SCRATCH                    MK_ADDR_CONST(0xec)
+#define SCRATCH_SECURE_RSV17_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV17_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV17_SCRATCH_SCR                        RSV17_SCR_0
+#define SCRATCH_SECURE_RSV17_SCRATCH_SCRREG                     SCRATCH_SCR_RSV17_SCR_0
+#define SCRATCH_SECURE_RSV17_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV17_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV17_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV17_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV17_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV17_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV17_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV17_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV17_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV17_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV17_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV17_SCRATCH_1
+#define SCRATCH_SECURE_RSV17_SCRATCH_1                  MK_ADDR_CONST(0xf0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_SCR                      RSV17_SCR_0
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV17_SCR_0
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV17_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV17_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV18_SCRATCH_0
+#define SCRATCH_SECURE_RSV18_SCRATCH_0                  MK_ADDR_CONST(0xf4)
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_SCR                      RSV18_SCR_0
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV18_SCR_0
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV18_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV18_SCRATCH
+#define SCRATCH_SECURE_RSV18_SCRATCH                    MK_ADDR_CONST(0xf4)
+#define SCRATCH_SECURE_RSV18_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV18_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV18_SCRATCH_SCR                        RSV18_SCR_0
+#define SCRATCH_SECURE_RSV18_SCRATCH_SCRREG                     SCRATCH_SCR_RSV18_SCR_0
+#define SCRATCH_SECURE_RSV18_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV18_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV18_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV18_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV18_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV18_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV18_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV18_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV18_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV18_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV18_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV18_SCRATCH_1
+#define SCRATCH_SECURE_RSV18_SCRATCH_1                  MK_ADDR_CONST(0xf8)
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_SCR                      RSV18_SCR_0
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV18_SCR_0
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV18_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV18_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV19_SCRATCH_0
+#define SCRATCH_SECURE_RSV19_SCRATCH_0                  MK_ADDR_CONST(0xfc)
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_SCR                      RSV19_SCR_0
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV19_SCR_0
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV19_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV19_SCRATCH
+#define SCRATCH_SECURE_RSV19_SCRATCH                    MK_ADDR_CONST(0xfc)
+#define SCRATCH_SECURE_RSV19_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV19_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV19_SCRATCH_SCR                        RSV19_SCR_0
+#define SCRATCH_SECURE_RSV19_SCRATCH_SCRREG                     SCRATCH_SCR_RSV19_SCR_0
+#define SCRATCH_SECURE_RSV19_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV19_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV19_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV19_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV19_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV19_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV19_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV19_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV19_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV19_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV19_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV19_SCRATCH_1
+#define SCRATCH_SECURE_RSV19_SCRATCH_1                  MK_ADDR_CONST(0x100)
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_SCR                      RSV19_SCR_0
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV19_SCR_0
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV19_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV19_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV20_SCRATCH_0
+#define SCRATCH_SECURE_RSV20_SCRATCH_0                  MK_ADDR_CONST(0x104)
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_SCR                      RSV20_SCR_0
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV20_SCR_0
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV20_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV20_SCRATCH
+#define SCRATCH_SECURE_RSV20_SCRATCH                    MK_ADDR_CONST(0x104)
+#define SCRATCH_SECURE_RSV20_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV20_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV20_SCRATCH_SCR                        RSV20_SCR_0
+#define SCRATCH_SECURE_RSV20_SCRATCH_SCRREG                     SCRATCH_SCR_RSV20_SCR_0
+#define SCRATCH_SECURE_RSV20_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV20_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV20_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV20_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV20_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV20_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV20_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV20_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV20_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV20_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV20_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV20_SCRATCH_1
+#define SCRATCH_SECURE_RSV20_SCRATCH_1                  MK_ADDR_CONST(0x108)
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_SCR                      RSV20_SCR_0
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV20_SCR_0
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV20_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV20_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV21_SCRATCH_0
+#define SCRATCH_SECURE_RSV21_SCRATCH_0                  MK_ADDR_CONST(0x10c)
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_SCR                      RSV21_SCR_0
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV21_SCR_0
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV21_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV21_SCRATCH
+#define SCRATCH_SECURE_RSV21_SCRATCH                    MK_ADDR_CONST(0x10c)
+#define SCRATCH_SECURE_RSV21_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV21_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV21_SCRATCH_SCR                        RSV21_SCR_0
+#define SCRATCH_SECURE_RSV21_SCRATCH_SCRREG                     SCRATCH_SCR_RSV21_SCR_0
+#define SCRATCH_SECURE_RSV21_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV21_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV21_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV21_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV21_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV21_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV21_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV21_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV21_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV21_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV21_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV21_SCRATCH_1
+#define SCRATCH_SECURE_RSV21_SCRATCH_1                  MK_ADDR_CONST(0x110)
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_SCR                      RSV21_SCR_0
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV21_SCR_0
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV21_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV21_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV22_SCRATCH_0
+#define SCRATCH_SECURE_RSV22_SCRATCH_0                  MK_ADDR_CONST(0x114)
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_SCR                      RSV22_SCR_0
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV22_SCR_0
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV22_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV22_SCRATCH
+#define SCRATCH_SECURE_RSV22_SCRATCH                    MK_ADDR_CONST(0x114)
+#define SCRATCH_SECURE_RSV22_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV22_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV22_SCRATCH_SCR                        RSV22_SCR_0
+#define SCRATCH_SECURE_RSV22_SCRATCH_SCRREG                     SCRATCH_SCR_RSV22_SCR_0
+#define SCRATCH_SECURE_RSV22_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV22_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV22_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV22_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV22_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV22_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV22_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV22_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV22_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV22_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV22_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV22_SCRATCH_1
+#define SCRATCH_SECURE_RSV22_SCRATCH_1                  MK_ADDR_CONST(0x118)
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_SCR                      RSV22_SCR_0
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV22_SCR_0
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV22_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV22_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV23_SCRATCH_0
+#define SCRATCH_SECURE_RSV23_SCRATCH_0                  MK_ADDR_CONST(0x11c)
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_SCR                      RSV23_SCR_0
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV23_SCR_0
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV23_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV23_SCRATCH
+#define SCRATCH_SECURE_RSV23_SCRATCH                    MK_ADDR_CONST(0x11c)
+#define SCRATCH_SECURE_RSV23_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV23_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV23_SCRATCH_SCR                        RSV23_SCR_0
+#define SCRATCH_SECURE_RSV23_SCRATCH_SCRREG                     SCRATCH_SCR_RSV23_SCR_0
+#define SCRATCH_SECURE_RSV23_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV23_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV23_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV23_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV23_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV23_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV23_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV23_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV23_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV23_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV23_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV23_SCRATCH_1
+#define SCRATCH_SECURE_RSV23_SCRATCH_1                  MK_ADDR_CONST(0x120)
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_SCR                      RSV23_SCR_0
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV23_SCR_0
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV23_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV23_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV24_SCRATCH_0
+#define SCRATCH_SECURE_RSV24_SCRATCH_0                  MK_ADDR_CONST(0x124)
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_SCR                      RSV24_SCR_0
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV24_SCR_0
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV24_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV24_SCRATCH
+#define SCRATCH_SECURE_RSV24_SCRATCH                    MK_ADDR_CONST(0x124)
+#define SCRATCH_SECURE_RSV24_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV24_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV24_SCRATCH_SCR                        RSV24_SCR_0
+#define SCRATCH_SECURE_RSV24_SCRATCH_SCRREG                     SCRATCH_SCR_RSV24_SCR_0
+#define SCRATCH_SECURE_RSV24_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV24_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV24_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV24_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV24_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV24_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV24_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV24_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV24_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV24_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV24_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV24_SCRATCH_1
+#define SCRATCH_SECURE_RSV24_SCRATCH_1                  MK_ADDR_CONST(0x128)
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_SCR                      RSV24_SCR_0
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV24_SCR_0
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV24_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV24_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV25_SCRATCH_0
+#define SCRATCH_SECURE_RSV25_SCRATCH_0                  MK_ADDR_CONST(0x12c)
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_SCR                      RSV25_SCR_0
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV25_SCR_0
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV25_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV25_SCRATCH
+#define SCRATCH_SECURE_RSV25_SCRATCH                    MK_ADDR_CONST(0x12c)
+#define SCRATCH_SECURE_RSV25_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV25_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV25_SCRATCH_SCR                        RSV25_SCR_0
+#define SCRATCH_SECURE_RSV25_SCRATCH_SCRREG                     SCRATCH_SCR_RSV25_SCR_0
+#define SCRATCH_SECURE_RSV25_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV25_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV25_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV25_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV25_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV25_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV25_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV25_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV25_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV25_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV25_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV25_SCRATCH_1
+#define SCRATCH_SECURE_RSV25_SCRATCH_1                  MK_ADDR_CONST(0x130)
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_SCR                      RSV25_SCR_0
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV25_SCR_0
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV25_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV25_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV26_SCRATCH_0
+#define SCRATCH_SECURE_RSV26_SCRATCH_0                  MK_ADDR_CONST(0x134)
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_SCR                      RSV26_SCR_0
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV26_SCR_0
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV26_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV26_SCRATCH
+#define SCRATCH_SECURE_RSV26_SCRATCH                    MK_ADDR_CONST(0x134)
+#define SCRATCH_SECURE_RSV26_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV26_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV26_SCRATCH_SCR                        RSV26_SCR_0
+#define SCRATCH_SECURE_RSV26_SCRATCH_SCRREG                     SCRATCH_SCR_RSV26_SCR_0
+#define SCRATCH_SECURE_RSV26_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV26_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV26_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV26_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV26_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV26_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV26_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV26_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV26_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV26_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV26_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV26_SCRATCH_1
+#define SCRATCH_SECURE_RSV26_SCRATCH_1                  MK_ADDR_CONST(0x138)
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_SCR                      RSV26_SCR_0
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV26_SCR_0
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV26_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV26_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV27_SCRATCH_0
+#define SCRATCH_SECURE_RSV27_SCRATCH_0                  MK_ADDR_CONST(0x13c)
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_SCR                      RSV27_SCR_0
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV27_SCR_0
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV27_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV27_SCRATCH
+#define SCRATCH_SECURE_RSV27_SCRATCH                    MK_ADDR_CONST(0x13c)
+#define SCRATCH_SECURE_RSV27_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV27_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV27_SCRATCH_SCR                        RSV27_SCR_0
+#define SCRATCH_SECURE_RSV27_SCRATCH_SCRREG                     SCRATCH_SCR_RSV27_SCR_0
+#define SCRATCH_SECURE_RSV27_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV27_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV27_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV27_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV27_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV27_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV27_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV27_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV27_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV27_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV27_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV27_SCRATCH_1
+#define SCRATCH_SECURE_RSV27_SCRATCH_1                  MK_ADDR_CONST(0x140)
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_SCR                      RSV27_SCR_0
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV27_SCR_0
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV27_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV27_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV28_SCRATCH_0
+#define SCRATCH_SECURE_RSV28_SCRATCH_0                  MK_ADDR_CONST(0x144)
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_SCR                      RSV28_SCR_0
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV28_SCR_0
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV28_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV28_SCRATCH
+#define SCRATCH_SECURE_RSV28_SCRATCH                    MK_ADDR_CONST(0x144)
+#define SCRATCH_SECURE_RSV28_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV28_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV28_SCRATCH_SCR                        RSV28_SCR_0
+#define SCRATCH_SECURE_RSV28_SCRATCH_SCRREG                     SCRATCH_SCR_RSV28_SCR_0
+#define SCRATCH_SECURE_RSV28_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV28_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV28_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV28_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV28_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV28_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV28_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV28_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV28_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV28_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV28_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV28_SCRATCH_1
+#define SCRATCH_SECURE_RSV28_SCRATCH_1                  MK_ADDR_CONST(0x148)
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_SCR                      RSV28_SCR_0
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV28_SCR_0
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV28_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV28_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV29_SCRATCH_0
+#define SCRATCH_SECURE_RSV29_SCRATCH_0                  MK_ADDR_CONST(0x14c)
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_SCR                      RSV29_SCR_0
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV29_SCR_0
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV29_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV29_SCRATCH
+#define SCRATCH_SECURE_RSV29_SCRATCH                    MK_ADDR_CONST(0x14c)
+#define SCRATCH_SECURE_RSV29_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV29_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV29_SCRATCH_SCR                        RSV29_SCR_0
+#define SCRATCH_SECURE_RSV29_SCRATCH_SCRREG                     SCRATCH_SCR_RSV29_SCR_0
+#define SCRATCH_SECURE_RSV29_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV29_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV29_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV29_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV29_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV29_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV29_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV29_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV29_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV29_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV29_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV29_SCRATCH_1
+#define SCRATCH_SECURE_RSV29_SCRATCH_1                  MK_ADDR_CONST(0x150)
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_SCR                      RSV29_SCR_0
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV29_SCR_0
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV29_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV29_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV30_SCRATCH_0
+#define SCRATCH_SECURE_RSV30_SCRATCH_0                  MK_ADDR_CONST(0x154)
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_SCR                      RSV30_SCR_0
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV30_SCR_0
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV30_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV30_SCRATCH
+#define SCRATCH_SECURE_RSV30_SCRATCH                    MK_ADDR_CONST(0x154)
+#define SCRATCH_SECURE_RSV30_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV30_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV30_SCRATCH_SCR                        RSV30_SCR_0
+#define SCRATCH_SECURE_RSV30_SCRATCH_SCRREG                     SCRATCH_SCR_RSV30_SCR_0
+#define SCRATCH_SECURE_RSV30_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV30_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV30_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV30_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV30_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV30_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV30_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV30_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV30_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV30_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV30_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV30_SCRATCH_1
+#define SCRATCH_SECURE_RSV30_SCRATCH_1                  MK_ADDR_CONST(0x158)
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_SCR                      RSV30_SCR_0
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV30_SCR_0
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV30_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV30_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV31_SCRATCH_0
+#define SCRATCH_SECURE_RSV31_SCRATCH_0                  MK_ADDR_CONST(0x15c)
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_SCR                      RSV31_SCR_0
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV31_SCR_0
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV31_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV31_SCRATCH
+#define SCRATCH_SECURE_RSV31_SCRATCH                    MK_ADDR_CONST(0x15c)
+#define SCRATCH_SECURE_RSV31_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV31_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV31_SCRATCH_SCR                        RSV31_SCR_0
+#define SCRATCH_SECURE_RSV31_SCRATCH_SCRREG                     SCRATCH_SCR_RSV31_SCR_0
+#define SCRATCH_SECURE_RSV31_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV31_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV31_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV31_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV31_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV31_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV31_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV31_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV31_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV31_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV31_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV31_SCRATCH_1
+#define SCRATCH_SECURE_RSV31_SCRATCH_1                  MK_ADDR_CONST(0x160)
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_SCR                      RSV31_SCR_0
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV31_SCR_0
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV31_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV31_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV32_SCRATCH_0
+#define SCRATCH_SECURE_RSV32_SCRATCH_0                  MK_ADDR_CONST(0x164)
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_SCR                      RSV32_SCR_0
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV32_SCR_0
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV32_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV32_SCRATCH
+#define SCRATCH_SECURE_RSV32_SCRATCH                    MK_ADDR_CONST(0x164)
+#define SCRATCH_SECURE_RSV32_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV32_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV32_SCRATCH_SCR                        RSV32_SCR_0
+#define SCRATCH_SECURE_RSV32_SCRATCH_SCRREG                     SCRATCH_SCR_RSV32_SCR_0
+#define SCRATCH_SECURE_RSV32_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV32_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV32_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV32_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV32_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV32_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV32_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV32_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV32_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV32_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV32_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV32_SCRATCH_1
+#define SCRATCH_SECURE_RSV32_SCRATCH_1                  MK_ADDR_CONST(0x168)
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_SCR                      RSV32_SCR_0
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV32_SCR_0
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV32_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV32_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV33_SCRATCH_0
+#define SCRATCH_SECURE_RSV33_SCRATCH_0                  MK_ADDR_CONST(0x16c)
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_SCR                      RSV33_SCR_0
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV33_SCR_0
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV33_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV33_SCRATCH
+#define SCRATCH_SECURE_RSV33_SCRATCH                    MK_ADDR_CONST(0x16c)
+#define SCRATCH_SECURE_RSV33_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV33_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV33_SCRATCH_SCR                        RSV33_SCR_0
+#define SCRATCH_SECURE_RSV33_SCRATCH_SCRREG                     SCRATCH_SCR_RSV33_SCR_0
+#define SCRATCH_SECURE_RSV33_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV33_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV33_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV33_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV33_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV33_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV33_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV33_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV33_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV33_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV33_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV33_SCRATCH_1
+#define SCRATCH_SECURE_RSV33_SCRATCH_1                  MK_ADDR_CONST(0x170)
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_SCR                      RSV33_SCR_0
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV33_SCR_0
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV33_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV33_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV34_SCRATCH_0
+#define SCRATCH_SECURE_RSV34_SCRATCH_0                  MK_ADDR_CONST(0x174)
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_SCR                      RSV34_SCR_0
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV34_SCR_0
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV34_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV34_SCRATCH
+#define SCRATCH_SECURE_RSV34_SCRATCH                    MK_ADDR_CONST(0x174)
+#define SCRATCH_SECURE_RSV34_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV34_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV34_SCRATCH_SCR                        RSV34_SCR_0
+#define SCRATCH_SECURE_RSV34_SCRATCH_SCRREG                     SCRATCH_SCR_RSV34_SCR_0
+#define SCRATCH_SECURE_RSV34_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV34_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV34_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV34_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV34_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV34_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV34_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV34_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV34_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV34_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV34_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV34_SCRATCH_1
+#define SCRATCH_SECURE_RSV34_SCRATCH_1                  MK_ADDR_CONST(0x178)
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_SCR                      RSV34_SCR_0
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV34_SCR_0
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV34_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV34_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV35_SCRATCH_0
+#define SCRATCH_SECURE_RSV35_SCRATCH_0                  MK_ADDR_CONST(0x17c)
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_SCR                      RSV35_SCR_0
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV35_SCR_0
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV35_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV35_SCRATCH
+#define SCRATCH_SECURE_RSV35_SCRATCH                    MK_ADDR_CONST(0x17c)
+#define SCRATCH_SECURE_RSV35_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV35_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV35_SCRATCH_SCR                        RSV35_SCR_0
+#define SCRATCH_SECURE_RSV35_SCRATCH_SCRREG                     SCRATCH_SCR_RSV35_SCR_0
+#define SCRATCH_SECURE_RSV35_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV35_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV35_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV35_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV35_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV35_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV35_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV35_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV35_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV35_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV35_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV35_SCRATCH_1
+#define SCRATCH_SECURE_RSV35_SCRATCH_1                  MK_ADDR_CONST(0x180)
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_SCR                      RSV35_SCR_0
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV35_SCR_0
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV35_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV35_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV36_SCRATCH_0
+#define SCRATCH_SECURE_RSV36_SCRATCH_0                  MK_ADDR_CONST(0x184)
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_SCR                      RSV36_SCR_0
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV36_SCR_0
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV36_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV36_SCRATCH
+#define SCRATCH_SECURE_RSV36_SCRATCH                    MK_ADDR_CONST(0x184)
+#define SCRATCH_SECURE_RSV36_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV36_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV36_SCRATCH_SCR                        RSV36_SCR_0
+#define SCRATCH_SECURE_RSV36_SCRATCH_SCRREG                     SCRATCH_SCR_RSV36_SCR_0
+#define SCRATCH_SECURE_RSV36_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV36_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV36_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV36_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV36_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV36_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV36_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV36_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV36_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV36_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV36_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV36_SCRATCH_1
+#define SCRATCH_SECURE_RSV36_SCRATCH_1                  MK_ADDR_CONST(0x188)
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_SCR                      RSV36_SCR_0
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV36_SCR_0
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV36_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV36_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV37_SCRATCH_0
+#define SCRATCH_SECURE_RSV37_SCRATCH_0                  MK_ADDR_CONST(0x18c)
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_SCR                      RSV37_SCR_0
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV37_SCR_0
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV37_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV37_SCRATCH
+#define SCRATCH_SECURE_RSV37_SCRATCH                    MK_ADDR_CONST(0x18c)
+#define SCRATCH_SECURE_RSV37_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV37_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV37_SCRATCH_SCR                        RSV37_SCR_0
+#define SCRATCH_SECURE_RSV37_SCRATCH_SCRREG                     SCRATCH_SCR_RSV37_SCR_0
+#define SCRATCH_SECURE_RSV37_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV37_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV37_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV37_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV37_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV37_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV37_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV37_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV37_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV37_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV37_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV37_SCRATCH_1
+#define SCRATCH_SECURE_RSV37_SCRATCH_1                  MK_ADDR_CONST(0x190)
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_SCR                      RSV37_SCR_0
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV37_SCR_0
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV37_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV37_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV38_SCRATCH_0
+#define SCRATCH_SECURE_RSV38_SCRATCH_0                  MK_ADDR_CONST(0x194)
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_SCR                      RSV38_SCR_0
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV38_SCR_0
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV38_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV38_SCRATCH
+#define SCRATCH_SECURE_RSV38_SCRATCH                    MK_ADDR_CONST(0x194)
+#define SCRATCH_SECURE_RSV38_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV38_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV38_SCRATCH_SCR                        RSV38_SCR_0
+#define SCRATCH_SECURE_RSV38_SCRATCH_SCRREG                     SCRATCH_SCR_RSV38_SCR_0
+#define SCRATCH_SECURE_RSV38_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV38_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV38_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV38_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV38_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV38_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV38_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV38_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV38_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV38_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV38_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV38_SCRATCH_1
+#define SCRATCH_SECURE_RSV38_SCRATCH_1                  MK_ADDR_CONST(0x198)
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_SCR                      RSV38_SCR_0
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV38_SCR_0
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV38_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV38_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV39_SCRATCH_0
+#define SCRATCH_SECURE_RSV39_SCRATCH_0                  MK_ADDR_CONST(0x19c)
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_SCR                      RSV39_SCR_0
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV39_SCR_0
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV39_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV39_SCRATCH
+#define SCRATCH_SECURE_RSV39_SCRATCH                    MK_ADDR_CONST(0x19c)
+#define SCRATCH_SECURE_RSV39_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV39_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV39_SCRATCH_SCR                        RSV39_SCR_0
+#define SCRATCH_SECURE_RSV39_SCRATCH_SCRREG                     SCRATCH_SCR_RSV39_SCR_0
+#define SCRATCH_SECURE_RSV39_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV39_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV39_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV39_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV39_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV39_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV39_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV39_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV39_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV39_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV39_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV39_SCRATCH_1
+#define SCRATCH_SECURE_RSV39_SCRATCH_1                  MK_ADDR_CONST(0x1a0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_SCR                      RSV39_SCR_0
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV39_SCR_0
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV39_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV39_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV40_SCRATCH_0
+#define SCRATCH_SECURE_RSV40_SCRATCH_0                  MK_ADDR_CONST(0x1a4)
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_SCR                      RSV40_SCR_0
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV40_SCR_0
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV40_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV40_SCRATCH
+#define SCRATCH_SECURE_RSV40_SCRATCH                    MK_ADDR_CONST(0x1a4)
+#define SCRATCH_SECURE_RSV40_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV40_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV40_SCRATCH_SCR                        RSV40_SCR_0
+#define SCRATCH_SECURE_RSV40_SCRATCH_SCRREG                     SCRATCH_SCR_RSV40_SCR_0
+#define SCRATCH_SECURE_RSV40_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV40_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV40_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV40_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV40_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV40_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV40_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV40_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV40_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV40_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV40_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV40_SCRATCH_1
+#define SCRATCH_SECURE_RSV40_SCRATCH_1                  MK_ADDR_CONST(0x1a8)
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_SCR                      RSV40_SCR_0
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV40_SCR_0
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV40_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV40_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV41_SCRATCH_0
+#define SCRATCH_SECURE_RSV41_SCRATCH_0                  MK_ADDR_CONST(0x1ac)
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_SCR                      RSV41_SCR_0
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV41_SCR_0
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV41_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV41_SCRATCH
+#define SCRATCH_SECURE_RSV41_SCRATCH                    MK_ADDR_CONST(0x1ac)
+#define SCRATCH_SECURE_RSV41_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV41_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV41_SCRATCH_SCR                        RSV41_SCR_0
+#define SCRATCH_SECURE_RSV41_SCRATCH_SCRREG                     SCRATCH_SCR_RSV41_SCR_0
+#define SCRATCH_SECURE_RSV41_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV41_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV41_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV41_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV41_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV41_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV41_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV41_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV41_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV41_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV41_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV41_SCRATCH_1
+#define SCRATCH_SECURE_RSV41_SCRATCH_1                  MK_ADDR_CONST(0x1b0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_SCR                      RSV41_SCR_0
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV41_SCR_0
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV41_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV41_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV42_SCRATCH_0
+#define SCRATCH_SECURE_RSV42_SCRATCH_0                  MK_ADDR_CONST(0x1b4)
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_SCR                      RSV42_SCR_0
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV42_SCR_0
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV42_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV42_SCRATCH
+#define SCRATCH_SECURE_RSV42_SCRATCH                    MK_ADDR_CONST(0x1b4)
+#define SCRATCH_SECURE_RSV42_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV42_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV42_SCRATCH_SCR                        RSV42_SCR_0
+#define SCRATCH_SECURE_RSV42_SCRATCH_SCRREG                     SCRATCH_SCR_RSV42_SCR_0
+#define SCRATCH_SECURE_RSV42_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV42_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV42_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV42_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV42_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV42_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV42_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV42_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV42_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV42_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV42_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV42_SCRATCH_1
+#define SCRATCH_SECURE_RSV42_SCRATCH_1                  MK_ADDR_CONST(0x1b8)
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_SCR                      RSV42_SCR_0
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV42_SCR_0
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV42_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV42_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV43_SCRATCH_0
+#define SCRATCH_SECURE_RSV43_SCRATCH_0                  MK_ADDR_CONST(0x1bc)
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_SCR                      RSV43_SCR_0
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV43_SCR_0
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV43_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV43_SCRATCH
+#define SCRATCH_SECURE_RSV43_SCRATCH                    MK_ADDR_CONST(0x1bc)
+#define SCRATCH_SECURE_RSV43_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV43_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV43_SCRATCH_SCR                        RSV43_SCR_0
+#define SCRATCH_SECURE_RSV43_SCRATCH_SCRREG                     SCRATCH_SCR_RSV43_SCR_0
+#define SCRATCH_SECURE_RSV43_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV43_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV43_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV43_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV43_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV43_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV43_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV43_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV43_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV43_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV43_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV43_SCRATCH_1
+#define SCRATCH_SECURE_RSV43_SCRATCH_1                  MK_ADDR_CONST(0x1c0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_SCR                      RSV43_SCR_0
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV43_SCR_0
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV43_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV43_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV44_SCRATCH_0
+#define SCRATCH_SECURE_RSV44_SCRATCH_0                  MK_ADDR_CONST(0x1c4)
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_SCR                      RSV44_SCR_0
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV44_SCR_0
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV44_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV44_SCRATCH
+#define SCRATCH_SECURE_RSV44_SCRATCH                    MK_ADDR_CONST(0x1c4)
+#define SCRATCH_SECURE_RSV44_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV44_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV44_SCRATCH_SCR                        RSV44_SCR_0
+#define SCRATCH_SECURE_RSV44_SCRATCH_SCRREG                     SCRATCH_SCR_RSV44_SCR_0
+#define SCRATCH_SECURE_RSV44_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV44_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV44_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV44_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV44_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV44_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV44_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV44_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV44_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV44_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV44_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV44_SCRATCH_1
+#define SCRATCH_SECURE_RSV44_SCRATCH_1                  MK_ADDR_CONST(0x1c8)
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_SCR                      RSV44_SCR_0
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV44_SCR_0
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV44_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV44_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV45_SCRATCH_0
+#define SCRATCH_SECURE_RSV45_SCRATCH_0                  MK_ADDR_CONST(0x1cc)
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_SCR                      RSV45_SCR_0
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV45_SCR_0
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV45_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV45_SCRATCH
+#define SCRATCH_SECURE_RSV45_SCRATCH                    MK_ADDR_CONST(0x1cc)
+#define SCRATCH_SECURE_RSV45_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV45_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV45_SCRATCH_SCR                        RSV45_SCR_0
+#define SCRATCH_SECURE_RSV45_SCRATCH_SCRREG                     SCRATCH_SCR_RSV45_SCR_0
+#define SCRATCH_SECURE_RSV45_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV45_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV45_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV45_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV45_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV45_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV45_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV45_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV45_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV45_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV45_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV45_SCRATCH_1
+#define SCRATCH_SECURE_RSV45_SCRATCH_1                  MK_ADDR_CONST(0x1d0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_SCR                      RSV45_SCR_0
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV45_SCR_0
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV45_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV45_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV46_SCRATCH_0
+#define SCRATCH_SECURE_RSV46_SCRATCH_0                  MK_ADDR_CONST(0x1d4)
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_SCR                      RSV46_SCR_0
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV46_SCR_0
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV46_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV46_SCRATCH
+#define SCRATCH_SECURE_RSV46_SCRATCH                    MK_ADDR_CONST(0x1d4)
+#define SCRATCH_SECURE_RSV46_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV46_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV46_SCRATCH_SCR                        RSV46_SCR_0
+#define SCRATCH_SECURE_RSV46_SCRATCH_SCRREG                     SCRATCH_SCR_RSV46_SCR_0
+#define SCRATCH_SECURE_RSV46_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV46_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV46_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV46_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV46_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV46_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV46_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV46_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV46_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV46_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV46_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV46_SCRATCH_1
+#define SCRATCH_SECURE_RSV46_SCRATCH_1                  MK_ADDR_CONST(0x1d8)
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_SCR                      RSV46_SCR_0
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV46_SCR_0
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV46_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV46_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV47_SCRATCH_0
+#define SCRATCH_SECURE_RSV47_SCRATCH_0                  MK_ADDR_CONST(0x1dc)
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_SCR                      RSV47_SCR_0
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV47_SCR_0
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV47_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV47_SCRATCH
+#define SCRATCH_SECURE_RSV47_SCRATCH                    MK_ADDR_CONST(0x1dc)
+#define SCRATCH_SECURE_RSV47_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV47_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV47_SCRATCH_SCR                        RSV47_SCR_0
+#define SCRATCH_SECURE_RSV47_SCRATCH_SCRREG                     SCRATCH_SCR_RSV47_SCR_0
+#define SCRATCH_SECURE_RSV47_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV47_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV47_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV47_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV47_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV47_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV47_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV47_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV47_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV47_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV47_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV47_SCRATCH_1
+#define SCRATCH_SECURE_RSV47_SCRATCH_1                  MK_ADDR_CONST(0x1e0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_SCR                      RSV47_SCR_0
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV47_SCR_0
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV47_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV47_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV48_SCRATCH_0
+#define SCRATCH_SECURE_RSV48_SCRATCH_0                  MK_ADDR_CONST(0x1e4)
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_SCR                      RSV48_SCR_0
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV48_SCR_0
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV48_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV48_SCRATCH
+#define SCRATCH_SECURE_RSV48_SCRATCH                    MK_ADDR_CONST(0x1e4)
+#define SCRATCH_SECURE_RSV48_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV48_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV48_SCRATCH_SCR                        RSV48_SCR_0
+#define SCRATCH_SECURE_RSV48_SCRATCH_SCRREG                     SCRATCH_SCR_RSV48_SCR_0
+#define SCRATCH_SECURE_RSV48_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV48_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV48_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV48_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV48_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV48_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV48_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV48_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV48_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV48_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV48_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV48_SCRATCH_1
+#define SCRATCH_SECURE_RSV48_SCRATCH_1                  MK_ADDR_CONST(0x1e8)
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_SCR                      RSV48_SCR_0
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV48_SCR_0
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV48_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV48_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV49_SCRATCH_0
+#define SCRATCH_SECURE_RSV49_SCRATCH_0                  MK_ADDR_CONST(0x1ec)
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_SCR                      RSV49_SCR_0
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV49_SCR_0
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV49_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV49_SCRATCH
+#define SCRATCH_SECURE_RSV49_SCRATCH                    MK_ADDR_CONST(0x1ec)
+#define SCRATCH_SECURE_RSV49_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV49_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV49_SCRATCH_SCR                        RSV49_SCR_0
+#define SCRATCH_SECURE_RSV49_SCRATCH_SCRREG                     SCRATCH_SCR_RSV49_SCR_0
+#define SCRATCH_SECURE_RSV49_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV49_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV49_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV49_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV49_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV49_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV49_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV49_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV49_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV49_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV49_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV49_SCRATCH_1
+#define SCRATCH_SECURE_RSV49_SCRATCH_1                  MK_ADDR_CONST(0x1f0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_SCR                      RSV49_SCR_0
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV49_SCR_0
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV49_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV49_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV50_SCRATCH_0
+#define SCRATCH_SECURE_RSV50_SCRATCH_0                  MK_ADDR_CONST(0x1f4)
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_SCR                      RSV50_SCR_0
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV50_SCR_0
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV50_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV50_SCRATCH
+#define SCRATCH_SECURE_RSV50_SCRATCH                    MK_ADDR_CONST(0x1f4)
+#define SCRATCH_SECURE_RSV50_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV50_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV50_SCRATCH_SCR                        RSV50_SCR_0
+#define SCRATCH_SECURE_RSV50_SCRATCH_SCRREG                     SCRATCH_SCR_RSV50_SCR_0
+#define SCRATCH_SECURE_RSV50_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV50_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV50_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV50_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV50_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV50_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV50_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV50_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV50_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV50_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV50_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV50_SCRATCH_1
+#define SCRATCH_SECURE_RSV50_SCRATCH_1                  MK_ADDR_CONST(0x1f8)
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_SCR                      RSV50_SCR_0
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV50_SCR_0
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV50_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV50_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV51_SCRATCH_0
+#define SCRATCH_SECURE_RSV51_SCRATCH_0                  MK_ADDR_CONST(0x1fc)
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_SCR                      RSV51_SCR_0
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV51_SCR_0
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV51_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV51_SCRATCH
+#define SCRATCH_SECURE_RSV51_SCRATCH                    MK_ADDR_CONST(0x1fc)
+#define SCRATCH_SECURE_RSV51_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV51_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV51_SCRATCH_SCR                        RSV51_SCR_0
+#define SCRATCH_SECURE_RSV51_SCRATCH_SCRREG                     SCRATCH_SCR_RSV51_SCR_0
+#define SCRATCH_SECURE_RSV51_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV51_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV51_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV51_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV51_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV51_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV51_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV51_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV51_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV51_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV51_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV51_SCRATCH_1
+#define SCRATCH_SECURE_RSV51_SCRATCH_1                  MK_ADDR_CONST(0x200)
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_SCR                      RSV51_SCR_0
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV51_SCR_0
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV51_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV51_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV52_SCRATCH_0
+#define SCRATCH_SECURE_RSV52_SCRATCH_0                  MK_ADDR_CONST(0x204)
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_SCR                      RSV52_SCR_0
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV52_SCR_0
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV52_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV52_SCRATCH
+#define SCRATCH_SECURE_RSV52_SCRATCH                    MK_ADDR_CONST(0x204)
+#define SCRATCH_SECURE_RSV52_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV52_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV52_SCRATCH_SCR                        RSV52_SCR_0
+#define SCRATCH_SECURE_RSV52_SCRATCH_SCRREG                     SCRATCH_SCR_RSV52_SCR_0
+#define SCRATCH_SECURE_RSV52_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV52_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV52_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV52_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV52_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV52_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV52_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV52_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV52_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV52_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV52_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV52_SCRATCH_1
+#define SCRATCH_SECURE_RSV52_SCRATCH_1                  MK_ADDR_CONST(0x208)
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_SCR                      RSV52_SCR_0
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV52_SCR_0
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV52_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV52_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV53_SCRATCH_0
+#define SCRATCH_SECURE_RSV53_SCRATCH_0                  MK_ADDR_CONST(0x20c)
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_SCR                      RSV53_SCR_0
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV53_SCR_0
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV53_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV53_SCRATCH
+#define SCRATCH_SECURE_RSV53_SCRATCH                    MK_ADDR_CONST(0x20c)
+#define SCRATCH_SECURE_RSV53_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV53_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV53_SCRATCH_SCR                        RSV53_SCR_0
+#define SCRATCH_SECURE_RSV53_SCRATCH_SCRREG                     SCRATCH_SCR_RSV53_SCR_0
+#define SCRATCH_SECURE_RSV53_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV53_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV53_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV53_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV53_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV53_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV53_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV53_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV53_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV53_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV53_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV53_SCRATCH_1
+#define SCRATCH_SECURE_RSV53_SCRATCH_1                  MK_ADDR_CONST(0x210)
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_SCR                      RSV53_SCR_0
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV53_SCR_0
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV53_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV53_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV54_SCRATCH_0
+#define SCRATCH_SECURE_RSV54_SCRATCH_0                  MK_ADDR_CONST(0x214)
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_SCR                      RSV54_SCR_0
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV54_SCR_0
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV54_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV54_SCRATCH
+#define SCRATCH_SECURE_RSV54_SCRATCH                    MK_ADDR_CONST(0x214)
+#define SCRATCH_SECURE_RSV54_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV54_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV54_SCRATCH_SCR                        RSV54_SCR_0
+#define SCRATCH_SECURE_RSV54_SCRATCH_SCRREG                     SCRATCH_SCR_RSV54_SCR_0
+#define SCRATCH_SECURE_RSV54_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV54_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV54_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV54_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV54_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV54_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV54_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV54_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV54_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV54_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV54_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV54_SCRATCH_1
+#define SCRATCH_SECURE_RSV54_SCRATCH_1                  MK_ADDR_CONST(0x218)
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_SCR                      RSV54_SCR_0
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV54_SCR_0
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV54_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV54_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV55_SCRATCH_0
+#define SCRATCH_SECURE_RSV55_SCRATCH_0                  MK_ADDR_CONST(0x21c)
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_SCR                      RSV55_SCR_0
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV55_SCR_0
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV55_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV55_SCRATCH
+#define SCRATCH_SECURE_RSV55_SCRATCH                    MK_ADDR_CONST(0x21c)
+#define SCRATCH_SECURE_RSV55_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV55_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV55_SCRATCH_SCR                        RSV55_SCR_0
+#define SCRATCH_SECURE_RSV55_SCRATCH_SCRREG                     SCRATCH_SCR_RSV55_SCR_0
+#define SCRATCH_SECURE_RSV55_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV55_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV55_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV55_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV55_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV55_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV55_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV55_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV55_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV55_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV55_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV55_SCRATCH_1
+#define SCRATCH_SECURE_RSV55_SCRATCH_1                  MK_ADDR_CONST(0x220)
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_SCR                      RSV55_SCR_0
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV55_SCR_0
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV55_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV55_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV56_SCRATCH_0
+#define SCRATCH_SECURE_RSV56_SCRATCH_0                  MK_ADDR_CONST(0x224)
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_SCR                      RSV56_SCR_0
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV56_SCR_0
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV56_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV56_SCRATCH
+#define SCRATCH_SECURE_RSV56_SCRATCH                    MK_ADDR_CONST(0x224)
+#define SCRATCH_SECURE_RSV56_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV56_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV56_SCRATCH_SCR                        RSV56_SCR_0
+#define SCRATCH_SECURE_RSV56_SCRATCH_SCRREG                     SCRATCH_SCR_RSV56_SCR_0
+#define SCRATCH_SECURE_RSV56_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV56_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV56_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV56_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV56_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV56_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV56_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV56_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV56_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV56_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV56_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV56_SCRATCH_1
+#define SCRATCH_SECURE_RSV56_SCRATCH_1                  MK_ADDR_CONST(0x228)
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_SCR                      RSV56_SCR_0
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV56_SCR_0
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV56_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV56_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV57_SCRATCH_0
+#define SCRATCH_SECURE_RSV57_SCRATCH_0                  MK_ADDR_CONST(0x22c)
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_SCR                      RSV57_SCR_0
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV57_SCR_0
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV57_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV57_SCRATCH
+#define SCRATCH_SECURE_RSV57_SCRATCH                    MK_ADDR_CONST(0x22c)
+#define SCRATCH_SECURE_RSV57_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV57_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV57_SCRATCH_SCR                        RSV57_SCR_0
+#define SCRATCH_SECURE_RSV57_SCRATCH_SCRREG                     SCRATCH_SCR_RSV57_SCR_0
+#define SCRATCH_SECURE_RSV57_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV57_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV57_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV57_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV57_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV57_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV57_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV57_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV57_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV57_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV57_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV57_SCRATCH_1
+#define SCRATCH_SECURE_RSV57_SCRATCH_1                  MK_ADDR_CONST(0x230)
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_SCR                      RSV57_SCR_0
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV57_SCR_0
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV57_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV57_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV58_SCRATCH_0
+#define SCRATCH_SECURE_RSV58_SCRATCH_0                  MK_ADDR_CONST(0x234)
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_SCR                      RSV58_SCR_0
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV58_SCR_0
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV58_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV58_SCRATCH
+#define SCRATCH_SECURE_RSV58_SCRATCH                    MK_ADDR_CONST(0x234)
+#define SCRATCH_SECURE_RSV58_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV58_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV58_SCRATCH_SCR                        RSV58_SCR_0
+#define SCRATCH_SECURE_RSV58_SCRATCH_SCRREG                     SCRATCH_SCR_RSV58_SCR_0
+#define SCRATCH_SECURE_RSV58_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV58_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV58_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV58_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV58_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV58_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV58_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV58_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV58_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV58_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV58_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV58_SCRATCH_1
+#define SCRATCH_SECURE_RSV58_SCRATCH_1                  MK_ADDR_CONST(0x238)
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_SCR                      RSV58_SCR_0
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV58_SCR_0
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV58_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV58_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV59_SCRATCH_0
+#define SCRATCH_SECURE_RSV59_SCRATCH_0                  MK_ADDR_CONST(0x23c)
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_SCR                      RSV59_SCR_0
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV59_SCR_0
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV59_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV59_SCRATCH
+#define SCRATCH_SECURE_RSV59_SCRATCH                    MK_ADDR_CONST(0x23c)
+#define SCRATCH_SECURE_RSV59_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV59_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV59_SCRATCH_SCR                        RSV59_SCR_0
+#define SCRATCH_SECURE_RSV59_SCRATCH_SCRREG                     SCRATCH_SCR_RSV59_SCR_0
+#define SCRATCH_SECURE_RSV59_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV59_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV59_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV59_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV59_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV59_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV59_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV59_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV59_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV59_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV59_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV59_SCRATCH_1
+#define SCRATCH_SECURE_RSV59_SCRATCH_1                  MK_ADDR_CONST(0x240)
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_SCR                      RSV59_SCR_0
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV59_SCR_0
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV59_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV59_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV60_SCRATCH_0
+#define SCRATCH_SECURE_RSV60_SCRATCH_0                  MK_ADDR_CONST(0x244)
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_SCR                      RSV60_SCR_0
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV60_SCR_0
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV60_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV60_SCRATCH
+#define SCRATCH_SECURE_RSV60_SCRATCH                    MK_ADDR_CONST(0x244)
+#define SCRATCH_SECURE_RSV60_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV60_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV60_SCRATCH_SCR                        RSV60_SCR_0
+#define SCRATCH_SECURE_RSV60_SCRATCH_SCRREG                     SCRATCH_SCR_RSV60_SCR_0
+#define SCRATCH_SECURE_RSV60_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV60_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV60_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV60_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV60_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV60_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV60_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV60_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV60_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV60_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV60_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV60_SCRATCH_1
+#define SCRATCH_SECURE_RSV60_SCRATCH_1                  MK_ADDR_CONST(0x248)
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_SCR                      RSV60_SCR_0
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV60_SCR_0
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV60_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV60_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV61_SCRATCH_0
+#define SCRATCH_SECURE_RSV61_SCRATCH_0                  MK_ADDR_CONST(0x24c)
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_SCR                      RSV61_SCR_0
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV61_SCR_0
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV61_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV61_SCRATCH
+#define SCRATCH_SECURE_RSV61_SCRATCH                    MK_ADDR_CONST(0x24c)
+#define SCRATCH_SECURE_RSV61_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV61_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV61_SCRATCH_SCR                        RSV61_SCR_0
+#define SCRATCH_SECURE_RSV61_SCRATCH_SCRREG                     SCRATCH_SCR_RSV61_SCR_0
+#define SCRATCH_SECURE_RSV61_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV61_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV61_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV61_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV61_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV61_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV61_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV61_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV61_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV61_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV61_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV61_SCRATCH_1
+#define SCRATCH_SECURE_RSV61_SCRATCH_1                  MK_ADDR_CONST(0x250)
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_SCR                      RSV61_SCR_0
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV61_SCR_0
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV61_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV61_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV62_SCRATCH_0
+#define SCRATCH_SECURE_RSV62_SCRATCH_0                  MK_ADDR_CONST(0x254)
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_SCR                      RSV62_SCR_0
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV62_SCR_0
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV62_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV62_SCRATCH
+#define SCRATCH_SECURE_RSV62_SCRATCH                    MK_ADDR_CONST(0x254)
+#define SCRATCH_SECURE_RSV62_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV62_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV62_SCRATCH_SCR                        RSV62_SCR_0
+#define SCRATCH_SECURE_RSV62_SCRATCH_SCRREG                     SCRATCH_SCR_RSV62_SCR_0
+#define SCRATCH_SECURE_RSV62_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV62_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV62_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV62_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV62_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV62_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV62_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV62_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV62_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV62_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV62_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV62_SCRATCH_1
+#define SCRATCH_SECURE_RSV62_SCRATCH_1                  MK_ADDR_CONST(0x258)
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_SCR                      RSV62_SCR_0
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV62_SCR_0
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV62_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV62_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV63_SCRATCH_0
+#define SCRATCH_SECURE_RSV63_SCRATCH_0                  MK_ADDR_CONST(0x25c)
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_SCR                      RSV63_SCR_0
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV63_SCR_0
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV63_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV63_SCRATCH
+#define SCRATCH_SECURE_RSV63_SCRATCH                    MK_ADDR_CONST(0x25c)
+#define SCRATCH_SECURE_RSV63_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV63_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV63_SCRATCH_SCR                        RSV63_SCR_0
+#define SCRATCH_SECURE_RSV63_SCRATCH_SCRREG                     SCRATCH_SCR_RSV63_SCR_0
+#define SCRATCH_SECURE_RSV63_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV63_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV63_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV63_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV63_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV63_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV63_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV63_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV63_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV63_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV63_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV63_SCRATCH_1
+#define SCRATCH_SECURE_RSV63_SCRATCH_1                  MK_ADDR_CONST(0x260)
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_SCR                      RSV63_SCR_0
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV63_SCR_0
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV63_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV63_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV64_SCRATCH_0
+#define SCRATCH_SECURE_RSV64_SCRATCH_0                  MK_ADDR_CONST(0x264)
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_SCR                      RSV64_SCR_0
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV64_SCR_0
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV64_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV64_SCRATCH
+#define SCRATCH_SECURE_RSV64_SCRATCH                    MK_ADDR_CONST(0x264)
+#define SCRATCH_SECURE_RSV64_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV64_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV64_SCRATCH_SCR                        RSV64_SCR_0
+#define SCRATCH_SECURE_RSV64_SCRATCH_SCRREG                     SCRATCH_SCR_RSV64_SCR_0
+#define SCRATCH_SECURE_RSV64_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV64_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV64_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV64_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV64_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV64_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV64_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV64_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV64_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV64_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV64_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV64_SCRATCH_1
+#define SCRATCH_SECURE_RSV64_SCRATCH_1                  MK_ADDR_CONST(0x268)
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_SCR                      RSV64_SCR_0
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV64_SCR_0
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV64_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV64_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV65_SCRATCH_0
+#define SCRATCH_SECURE_RSV65_SCRATCH_0                  MK_ADDR_CONST(0x26c)
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_SCR                      RSV65_SCR_0
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV65_SCR_0
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV65_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV65_SCRATCH
+#define SCRATCH_SECURE_RSV65_SCRATCH                    MK_ADDR_CONST(0x26c)
+#define SCRATCH_SECURE_RSV65_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV65_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV65_SCRATCH_SCR                        RSV65_SCR_0
+#define SCRATCH_SECURE_RSV65_SCRATCH_SCRREG                     SCRATCH_SCR_RSV65_SCR_0
+#define SCRATCH_SECURE_RSV65_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV65_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV65_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV65_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV65_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV65_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV65_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV65_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV65_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV65_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV65_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV65_SCRATCH_1
+#define SCRATCH_SECURE_RSV65_SCRATCH_1                  MK_ADDR_CONST(0x270)
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_SCR                      RSV65_SCR_0
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV65_SCR_0
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV65_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV65_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV66_SCRATCH_0
+#define SCRATCH_SECURE_RSV66_SCRATCH_0                  MK_ADDR_CONST(0x274)
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_SCR                      RSV66_SCR_0
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV66_SCR_0
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV66_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV66_SCRATCH
+#define SCRATCH_SECURE_RSV66_SCRATCH                    MK_ADDR_CONST(0x274)
+#define SCRATCH_SECURE_RSV66_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV66_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV66_SCRATCH_SCR                        RSV66_SCR_0
+#define SCRATCH_SECURE_RSV66_SCRATCH_SCRREG                     SCRATCH_SCR_RSV66_SCR_0
+#define SCRATCH_SECURE_RSV66_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV66_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV66_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV66_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV66_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV66_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV66_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV66_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV66_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV66_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV66_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV66_SCRATCH_1
+#define SCRATCH_SECURE_RSV66_SCRATCH_1                  MK_ADDR_CONST(0x278)
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_SCR                      RSV66_SCR_0
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV66_SCR_0
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV66_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV66_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV67_SCRATCH_0
+#define SCRATCH_SECURE_RSV67_SCRATCH_0                  MK_ADDR_CONST(0x27c)
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_SCR                      RSV67_SCR_0
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV67_SCR_0
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV67_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV67_SCRATCH
+#define SCRATCH_SECURE_RSV67_SCRATCH                    MK_ADDR_CONST(0x27c)
+#define SCRATCH_SECURE_RSV67_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV67_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV67_SCRATCH_SCR                        RSV67_SCR_0
+#define SCRATCH_SECURE_RSV67_SCRATCH_SCRREG                     SCRATCH_SCR_RSV67_SCR_0
+#define SCRATCH_SECURE_RSV67_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV67_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV67_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV67_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV67_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV67_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV67_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV67_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV67_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV67_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV67_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV67_SCRATCH_1
+#define SCRATCH_SECURE_RSV67_SCRATCH_1                  MK_ADDR_CONST(0x280)
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_SCR                      RSV67_SCR_0
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV67_SCR_0
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV67_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV67_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV68_SCRATCH_0
+#define SCRATCH_SECURE_RSV68_SCRATCH_0                  MK_ADDR_CONST(0x284)
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_SCR                      RSV68_SCR_0
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV68_SCR_0
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV68_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV68_SCRATCH
+#define SCRATCH_SECURE_RSV68_SCRATCH                    MK_ADDR_CONST(0x284)
+#define SCRATCH_SECURE_RSV68_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV68_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV68_SCRATCH_SCR                        RSV68_SCR_0
+#define SCRATCH_SECURE_RSV68_SCRATCH_SCRREG                     SCRATCH_SCR_RSV68_SCR_0
+#define SCRATCH_SECURE_RSV68_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV68_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV68_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV68_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV68_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV68_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV68_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV68_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV68_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV68_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV68_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV68_SCRATCH_1
+#define SCRATCH_SECURE_RSV68_SCRATCH_1                  MK_ADDR_CONST(0x288)
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_SCR                      RSV68_SCR_0
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV68_SCR_0
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV68_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV68_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV69_SCRATCH_0
+#define SCRATCH_SECURE_RSV69_SCRATCH_0                  MK_ADDR_CONST(0x28c)
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_SCR                      RSV69_SCR_0
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV69_SCR_0
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV69_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV69_SCRATCH
+#define SCRATCH_SECURE_RSV69_SCRATCH                    MK_ADDR_CONST(0x28c)
+#define SCRATCH_SECURE_RSV69_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV69_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV69_SCRATCH_SCR                        RSV69_SCR_0
+#define SCRATCH_SECURE_RSV69_SCRATCH_SCRREG                     SCRATCH_SCR_RSV69_SCR_0
+#define SCRATCH_SECURE_RSV69_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV69_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV69_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV69_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV69_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV69_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV69_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV69_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV69_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV69_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV69_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV69_SCRATCH_1
+#define SCRATCH_SECURE_RSV69_SCRATCH_1                  MK_ADDR_CONST(0x290)
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_SCR                      RSV69_SCR_0
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV69_SCR_0
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV69_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV69_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV70_SCRATCH_0
+#define SCRATCH_SECURE_RSV70_SCRATCH_0                  MK_ADDR_CONST(0x294)
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_SCR                      RSV70_SCR_0
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV70_SCR_0
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV70_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV70_SCRATCH
+#define SCRATCH_SECURE_RSV70_SCRATCH                    MK_ADDR_CONST(0x294)
+#define SCRATCH_SECURE_RSV70_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV70_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV70_SCRATCH_SCR                        RSV70_SCR_0
+#define SCRATCH_SECURE_RSV70_SCRATCH_SCRREG                     SCRATCH_SCR_RSV70_SCR_0
+#define SCRATCH_SECURE_RSV70_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV70_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV70_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV70_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV70_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV70_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV70_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV70_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV70_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV70_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV70_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV70_SCRATCH_1
+#define SCRATCH_SECURE_RSV70_SCRATCH_1                  MK_ADDR_CONST(0x298)
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_SCR                      RSV70_SCR_0
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV70_SCR_0
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV70_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV70_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV71_SCRATCH_0
+#define SCRATCH_SECURE_RSV71_SCRATCH_0                  MK_ADDR_CONST(0x29c)
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_SCR                      RSV71_SCR_0
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV71_SCR_0
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV71_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV71_SCRATCH
+#define SCRATCH_SECURE_RSV71_SCRATCH                    MK_ADDR_CONST(0x29c)
+#define SCRATCH_SECURE_RSV71_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV71_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV71_SCRATCH_SCR                        RSV71_SCR_0
+#define SCRATCH_SECURE_RSV71_SCRATCH_SCRREG                     SCRATCH_SCR_RSV71_SCR_0
+#define SCRATCH_SECURE_RSV71_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV71_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV71_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV71_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV71_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV71_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV71_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV71_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV71_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV71_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV71_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV71_SCRATCH_1
+#define SCRATCH_SECURE_RSV71_SCRATCH_1                  MK_ADDR_CONST(0x2a0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_SCR                      RSV71_SCR_0
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV71_SCR_0
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV71_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV71_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV72_SCRATCH_0
+#define SCRATCH_SECURE_RSV72_SCRATCH_0                  MK_ADDR_CONST(0x2a4)
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_SCR                      RSV72_SCR_0
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV72_SCR_0
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV72_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV72_SCRATCH
+#define SCRATCH_SECURE_RSV72_SCRATCH                    MK_ADDR_CONST(0x2a4)
+#define SCRATCH_SECURE_RSV72_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV72_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV72_SCRATCH_SCR                        RSV72_SCR_0
+#define SCRATCH_SECURE_RSV72_SCRATCH_SCRREG                     SCRATCH_SCR_RSV72_SCR_0
+#define SCRATCH_SECURE_RSV72_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV72_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV72_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV72_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV72_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV72_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV72_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV72_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV72_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV72_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV72_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV72_SCRATCH_1
+#define SCRATCH_SECURE_RSV72_SCRATCH_1                  MK_ADDR_CONST(0x2a8)
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_SCR                      RSV72_SCR_0
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV72_SCR_0
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV72_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV72_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV73_SCRATCH_0
+#define SCRATCH_SECURE_RSV73_SCRATCH_0                  MK_ADDR_CONST(0x2ac)
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_SCR                      RSV73_SCR_0
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV73_SCR_0
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV73_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV73_SCRATCH
+#define SCRATCH_SECURE_RSV73_SCRATCH                    MK_ADDR_CONST(0x2ac)
+#define SCRATCH_SECURE_RSV73_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV73_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV73_SCRATCH_SCR                        RSV73_SCR_0
+#define SCRATCH_SECURE_RSV73_SCRATCH_SCRREG                     SCRATCH_SCR_RSV73_SCR_0
+#define SCRATCH_SECURE_RSV73_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV73_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV73_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV73_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV73_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV73_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV73_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV73_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV73_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV73_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV73_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV73_SCRATCH_1
+#define SCRATCH_SECURE_RSV73_SCRATCH_1                  MK_ADDR_CONST(0x2b0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_SCR                      RSV73_SCR_0
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV73_SCR_0
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV73_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV73_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV74_SCRATCH_0
+#define SCRATCH_SECURE_RSV74_SCRATCH_0                  MK_ADDR_CONST(0x2b4)
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_SCR                      RSV74_SCR_0
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV74_SCR_0
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV74_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV74_SCRATCH
+#define SCRATCH_SECURE_RSV74_SCRATCH                    MK_ADDR_CONST(0x2b4)
+#define SCRATCH_SECURE_RSV74_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV74_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV74_SCRATCH_SCR                        RSV74_SCR_0
+#define SCRATCH_SECURE_RSV74_SCRATCH_SCRREG                     SCRATCH_SCR_RSV74_SCR_0
+#define SCRATCH_SECURE_RSV74_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV74_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV74_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV74_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV74_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV74_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV74_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV74_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV74_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV74_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV74_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV74_SCRATCH_1
+#define SCRATCH_SECURE_RSV74_SCRATCH_1                  MK_ADDR_CONST(0x2b8)
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_SCR                      RSV74_SCR_0
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV74_SCR_0
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV74_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV74_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV75_SCRATCH_0
+#define SCRATCH_SECURE_RSV75_SCRATCH_0                  MK_ADDR_CONST(0x2bc)
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_SCR                      RSV75_SCR_0
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV75_SCR_0
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV75_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV75_SCRATCH
+#define SCRATCH_SECURE_RSV75_SCRATCH                    MK_ADDR_CONST(0x2bc)
+#define SCRATCH_SECURE_RSV75_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV75_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV75_SCRATCH_SCR                        RSV75_SCR_0
+#define SCRATCH_SECURE_RSV75_SCRATCH_SCRREG                     SCRATCH_SCR_RSV75_SCR_0
+#define SCRATCH_SECURE_RSV75_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV75_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV75_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV75_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV75_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV75_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV75_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV75_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV75_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV75_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV75_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV75_SCRATCH_1
+#define SCRATCH_SECURE_RSV75_SCRATCH_1                  MK_ADDR_CONST(0x2c0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_SCR                      RSV75_SCR_0
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV75_SCR_0
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV75_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV75_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV76_SCRATCH_0
+#define SCRATCH_SECURE_RSV76_SCRATCH_0                  MK_ADDR_CONST(0x2c4)
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_SCR                      RSV76_SCR_0
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV76_SCR_0
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV76_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV76_SCRATCH
+#define SCRATCH_SECURE_RSV76_SCRATCH                    MK_ADDR_CONST(0x2c4)
+#define SCRATCH_SECURE_RSV76_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV76_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV76_SCRATCH_SCR                        RSV76_SCR_0
+#define SCRATCH_SECURE_RSV76_SCRATCH_SCRREG                     SCRATCH_SCR_RSV76_SCR_0
+#define SCRATCH_SECURE_RSV76_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV76_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV76_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV76_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV76_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV76_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV76_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV76_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV76_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV76_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV76_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV76_SCRATCH_1
+#define SCRATCH_SECURE_RSV76_SCRATCH_1                  MK_ADDR_CONST(0x2c8)
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_SCR                      RSV76_SCR_0
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV76_SCR_0
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV76_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV76_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV77_SCRATCH_0
+#define SCRATCH_SECURE_RSV77_SCRATCH_0                  MK_ADDR_CONST(0x2cc)
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_SCR                      RSV77_SCR_0
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV77_SCR_0
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV77_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV77_SCRATCH
+#define SCRATCH_SECURE_RSV77_SCRATCH                    MK_ADDR_CONST(0x2cc)
+#define SCRATCH_SECURE_RSV77_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV77_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV77_SCRATCH_SCR                        RSV77_SCR_0
+#define SCRATCH_SECURE_RSV77_SCRATCH_SCRREG                     SCRATCH_SCR_RSV77_SCR_0
+#define SCRATCH_SECURE_RSV77_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV77_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV77_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV77_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV77_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV77_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV77_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV77_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV77_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV77_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV77_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV77_SCRATCH_1
+#define SCRATCH_SECURE_RSV77_SCRATCH_1                  MK_ADDR_CONST(0x2d0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_SCR                      RSV77_SCR_0
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV77_SCR_0
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV77_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV77_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV78_SCRATCH_0
+#define SCRATCH_SECURE_RSV78_SCRATCH_0                  MK_ADDR_CONST(0x2d4)
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_SCR                      RSV78_SCR_0
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV78_SCR_0
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV78_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV78_SCRATCH
+#define SCRATCH_SECURE_RSV78_SCRATCH                    MK_ADDR_CONST(0x2d4)
+#define SCRATCH_SECURE_RSV78_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV78_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV78_SCRATCH_SCR                        RSV78_SCR_0
+#define SCRATCH_SECURE_RSV78_SCRATCH_SCRREG                     SCRATCH_SCR_RSV78_SCR_0
+#define SCRATCH_SECURE_RSV78_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV78_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV78_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV78_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV78_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV78_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV78_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV78_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV78_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV78_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV78_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV78_SCRATCH_1
+#define SCRATCH_SECURE_RSV78_SCRATCH_1                  MK_ADDR_CONST(0x2d8)
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_SCR                      RSV78_SCR_0
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV78_SCR_0
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV78_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV78_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV79_SCRATCH_0
+#define SCRATCH_SECURE_RSV79_SCRATCH_0                  MK_ADDR_CONST(0x2dc)
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_SCR                      RSV79_SCR_0
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV79_SCR_0
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV79_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV79_SCRATCH
+#define SCRATCH_SECURE_RSV79_SCRATCH                    MK_ADDR_CONST(0x2dc)
+#define SCRATCH_SECURE_RSV79_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV79_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV79_SCRATCH_SCR                        RSV79_SCR_0
+#define SCRATCH_SECURE_RSV79_SCRATCH_SCRREG                     SCRATCH_SCR_RSV79_SCR_0
+#define SCRATCH_SECURE_RSV79_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV79_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV79_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV79_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV79_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV79_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV79_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV79_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV79_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV79_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV79_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV79_SCRATCH_1
+#define SCRATCH_SECURE_RSV79_SCRATCH_1                  MK_ADDR_CONST(0x2e0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_SCR                      RSV79_SCR_0
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV79_SCR_0
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV79_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV79_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV80_SCRATCH_0
+#define SCRATCH_SECURE_RSV80_SCRATCH_0                  MK_ADDR_CONST(0x2e4)
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_SCR                      RSV80_SCR_0
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV80_SCR_0
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV80_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV80_SCRATCH
+#define SCRATCH_SECURE_RSV80_SCRATCH                    MK_ADDR_CONST(0x2e4)
+#define SCRATCH_SECURE_RSV80_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV80_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV80_SCRATCH_SCR                        RSV80_SCR_0
+#define SCRATCH_SECURE_RSV80_SCRATCH_SCRREG                     SCRATCH_SCR_RSV80_SCR_0
+#define SCRATCH_SECURE_RSV80_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV80_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV80_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV80_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV80_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV80_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV80_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV80_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV80_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV80_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV80_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV80_SCRATCH_1
+#define SCRATCH_SECURE_RSV80_SCRATCH_1                  MK_ADDR_CONST(0x2e8)
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_SCR                      RSV80_SCR_0
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV80_SCR_0
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV80_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV80_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV81_SCRATCH_0
+#define SCRATCH_SECURE_RSV81_SCRATCH_0                  MK_ADDR_CONST(0x2ec)
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_SCR                      RSV81_SCR_0
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV81_SCR_0
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV81_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV81_SCRATCH
+#define SCRATCH_SECURE_RSV81_SCRATCH                    MK_ADDR_CONST(0x2ec)
+#define SCRATCH_SECURE_RSV81_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV81_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV81_SCRATCH_SCR                        RSV81_SCR_0
+#define SCRATCH_SECURE_RSV81_SCRATCH_SCRREG                     SCRATCH_SCR_RSV81_SCR_0
+#define SCRATCH_SECURE_RSV81_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV81_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV81_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV81_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV81_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV81_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV81_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV81_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV81_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV81_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV81_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV81_SCRATCH_1
+#define SCRATCH_SECURE_RSV81_SCRATCH_1                  MK_ADDR_CONST(0x2f0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_SCR                      RSV81_SCR_0
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV81_SCR_0
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV81_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV81_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV82_SCRATCH_0
+#define SCRATCH_SECURE_RSV82_SCRATCH_0                  MK_ADDR_CONST(0x2f4)
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_SCR                      RSV82_SCR_0
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV82_SCR_0
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV82_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV82_SCRATCH
+#define SCRATCH_SECURE_RSV82_SCRATCH                    MK_ADDR_CONST(0x2f4)
+#define SCRATCH_SECURE_RSV82_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV82_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV82_SCRATCH_SCR                        RSV82_SCR_0
+#define SCRATCH_SECURE_RSV82_SCRATCH_SCRREG                     SCRATCH_SCR_RSV82_SCR_0
+#define SCRATCH_SECURE_RSV82_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV82_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV82_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV82_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV82_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV82_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV82_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV82_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV82_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV82_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV82_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV82_SCRATCH_1
+#define SCRATCH_SECURE_RSV82_SCRATCH_1                  MK_ADDR_CONST(0x2f8)
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_SCR                      RSV82_SCR_0
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV82_SCR_0
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV82_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV82_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV83_SCRATCH_0
+#define SCRATCH_SECURE_RSV83_SCRATCH_0                  MK_ADDR_CONST(0x2fc)
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_SCR                      RSV83_SCR_0
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV83_SCR_0
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV83_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV83_SCRATCH
+#define SCRATCH_SECURE_RSV83_SCRATCH                    MK_ADDR_CONST(0x2fc)
+#define SCRATCH_SECURE_RSV83_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV83_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV83_SCRATCH_SCR                        RSV83_SCR_0
+#define SCRATCH_SECURE_RSV83_SCRATCH_SCRREG                     SCRATCH_SCR_RSV83_SCR_0
+#define SCRATCH_SECURE_RSV83_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV83_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV83_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV83_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV83_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV83_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV83_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV83_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV83_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV83_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV83_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV83_SCRATCH_1
+#define SCRATCH_SECURE_RSV83_SCRATCH_1                  MK_ADDR_CONST(0x300)
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_SCR                      RSV83_SCR_0
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV83_SCR_0
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV83_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV83_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV84_SCRATCH_0
+#define SCRATCH_SECURE_RSV84_SCRATCH_0                  MK_ADDR_CONST(0x304)
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_SCR                      RSV84_SCR_0
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV84_SCR_0
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV84_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV84_SCRATCH
+#define SCRATCH_SECURE_RSV84_SCRATCH                    MK_ADDR_CONST(0x304)
+#define SCRATCH_SECURE_RSV84_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV84_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV84_SCRATCH_SCR                        RSV84_SCR_0
+#define SCRATCH_SECURE_RSV84_SCRATCH_SCRREG                     SCRATCH_SCR_RSV84_SCR_0
+#define SCRATCH_SECURE_RSV84_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV84_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV84_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV84_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV84_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV84_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV84_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV84_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV84_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV84_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV84_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV84_SCRATCH_1
+#define SCRATCH_SECURE_RSV84_SCRATCH_1                  MK_ADDR_CONST(0x308)
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_SCR                      RSV84_SCR_0
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV84_SCR_0
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV84_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV84_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV85_SCRATCH_0
+#define SCRATCH_SECURE_RSV85_SCRATCH_0                  MK_ADDR_CONST(0x30c)
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_SCR                      RSV85_SCR_0
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV85_SCR_0
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV85_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV85_SCRATCH
+#define SCRATCH_SECURE_RSV85_SCRATCH                    MK_ADDR_CONST(0x30c)
+#define SCRATCH_SECURE_RSV85_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV85_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV85_SCRATCH_SCR                        RSV85_SCR_0
+#define SCRATCH_SECURE_RSV85_SCRATCH_SCRREG                     SCRATCH_SCR_RSV85_SCR_0
+#define SCRATCH_SECURE_RSV85_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV85_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV85_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV85_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV85_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV85_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV85_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV85_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV85_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV85_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV85_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV85_SCRATCH_1
+#define SCRATCH_SECURE_RSV85_SCRATCH_1                  MK_ADDR_CONST(0x310)
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_SCR                      RSV85_SCR_0
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV85_SCR_0
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV85_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV85_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV86_SCRATCH_0
+#define SCRATCH_SECURE_RSV86_SCRATCH_0                  MK_ADDR_CONST(0x314)
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_SCR                      RSV86_SCR_0
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV86_SCR_0
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV86_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV86_SCRATCH
+#define SCRATCH_SECURE_RSV86_SCRATCH                    MK_ADDR_CONST(0x314)
+#define SCRATCH_SECURE_RSV86_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV86_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV86_SCRATCH_SCR                        RSV86_SCR_0
+#define SCRATCH_SECURE_RSV86_SCRATCH_SCRREG                     SCRATCH_SCR_RSV86_SCR_0
+#define SCRATCH_SECURE_RSV86_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV86_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV86_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV86_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV86_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV86_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV86_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV86_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV86_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV86_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV86_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV86_SCRATCH_1
+#define SCRATCH_SECURE_RSV86_SCRATCH_1                  MK_ADDR_CONST(0x318)
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_SCR                      RSV86_SCR_0
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV86_SCR_0
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV86_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV86_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV87_SCRATCH_0
+#define SCRATCH_SECURE_RSV87_SCRATCH_0                  MK_ADDR_CONST(0x31c)
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_SCR                      RSV87_SCR_0
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV87_SCR_0
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV87_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV87_SCRATCH
+#define SCRATCH_SECURE_RSV87_SCRATCH                    MK_ADDR_CONST(0x31c)
+#define SCRATCH_SECURE_RSV87_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV87_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV87_SCRATCH_SCR                        RSV87_SCR_0
+#define SCRATCH_SECURE_RSV87_SCRATCH_SCRREG                     SCRATCH_SCR_RSV87_SCR_0
+#define SCRATCH_SECURE_RSV87_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV87_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV87_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV87_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV87_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV87_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV87_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV87_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV87_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV87_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV87_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV87_SCRATCH_1
+#define SCRATCH_SECURE_RSV87_SCRATCH_1                  MK_ADDR_CONST(0x320)
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_SCR                      RSV87_SCR_0
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV87_SCR_0
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV87_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV87_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV88_SCRATCH_0
+#define SCRATCH_SECURE_RSV88_SCRATCH_0                  MK_ADDR_CONST(0x324)
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_SCR                      RSV88_SCR_0
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV88_SCR_0
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV88_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV88_SCRATCH
+#define SCRATCH_SECURE_RSV88_SCRATCH                    MK_ADDR_CONST(0x324)
+#define SCRATCH_SECURE_RSV88_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV88_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV88_SCRATCH_SCR                        RSV88_SCR_0
+#define SCRATCH_SECURE_RSV88_SCRATCH_SCRREG                     SCRATCH_SCR_RSV88_SCR_0
+#define SCRATCH_SECURE_RSV88_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV88_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV88_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV88_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV88_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV88_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV88_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV88_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV88_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV88_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV88_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV88_SCRATCH_1
+#define SCRATCH_SECURE_RSV88_SCRATCH_1                  MK_ADDR_CONST(0x328)
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_SCR                      RSV88_SCR_0
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV88_SCR_0
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV88_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV88_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV89_SCRATCH_0
+#define SCRATCH_SECURE_RSV89_SCRATCH_0                  MK_ADDR_CONST(0x32c)
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_SCR                      RSV89_SCR_0
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV89_SCR_0
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV89_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV89_SCRATCH
+#define SCRATCH_SECURE_RSV89_SCRATCH                    MK_ADDR_CONST(0x32c)
+#define SCRATCH_SECURE_RSV89_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV89_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV89_SCRATCH_SCR                        RSV89_SCR_0
+#define SCRATCH_SECURE_RSV89_SCRATCH_SCRREG                     SCRATCH_SCR_RSV89_SCR_0
+#define SCRATCH_SECURE_RSV89_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV89_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV89_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV89_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV89_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV89_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV89_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV89_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV89_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV89_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV89_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV89_SCRATCH_1
+#define SCRATCH_SECURE_RSV89_SCRATCH_1                  MK_ADDR_CONST(0x330)
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_SCR                      RSV89_SCR_0
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV89_SCR_0
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV89_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV89_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV90_SCRATCH_0
+#define SCRATCH_SECURE_RSV90_SCRATCH_0                  MK_ADDR_CONST(0x334)
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_SCR                      RSV90_SCR_0
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV90_SCR_0
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV90_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV90_SCRATCH
+#define SCRATCH_SECURE_RSV90_SCRATCH                    MK_ADDR_CONST(0x334)
+#define SCRATCH_SECURE_RSV90_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV90_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV90_SCRATCH_SCR                        RSV90_SCR_0
+#define SCRATCH_SECURE_RSV90_SCRATCH_SCRREG                     SCRATCH_SCR_RSV90_SCR_0
+#define SCRATCH_SECURE_RSV90_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV90_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV90_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV90_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV90_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV90_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV90_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV90_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV90_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV90_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV90_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV90_SCRATCH_1
+#define SCRATCH_SECURE_RSV90_SCRATCH_1                  MK_ADDR_CONST(0x338)
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_SCR                      RSV90_SCR_0
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV90_SCR_0
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV90_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV90_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV91_SCRATCH_0
+#define SCRATCH_SECURE_RSV91_SCRATCH_0                  MK_ADDR_CONST(0x33c)
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_SCR                      RSV91_SCR_0
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV91_SCR_0
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV91_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV91_SCRATCH
+#define SCRATCH_SECURE_RSV91_SCRATCH                    MK_ADDR_CONST(0x33c)
+#define SCRATCH_SECURE_RSV91_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV91_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV91_SCRATCH_SCR                        RSV91_SCR_0
+#define SCRATCH_SECURE_RSV91_SCRATCH_SCRREG                     SCRATCH_SCR_RSV91_SCR_0
+#define SCRATCH_SECURE_RSV91_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV91_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV91_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV91_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV91_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV91_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV91_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV91_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV91_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV91_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV91_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV91_SCRATCH_1
+#define SCRATCH_SECURE_RSV91_SCRATCH_1                  MK_ADDR_CONST(0x340)
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_SCR                      RSV91_SCR_0
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV91_SCR_0
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV91_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV91_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV92_SCRATCH_0
+#define SCRATCH_SECURE_RSV92_SCRATCH_0                  MK_ADDR_CONST(0x344)
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_SCR                      RSV92_SCR_0
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV92_SCR_0
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV92_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV92_SCRATCH
+#define SCRATCH_SECURE_RSV92_SCRATCH                    MK_ADDR_CONST(0x344)
+#define SCRATCH_SECURE_RSV92_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV92_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV92_SCRATCH_SCR                        RSV92_SCR_0
+#define SCRATCH_SECURE_RSV92_SCRATCH_SCRREG                     SCRATCH_SCR_RSV92_SCR_0
+#define SCRATCH_SECURE_RSV92_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV92_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV92_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV92_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV92_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV92_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV92_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV92_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV92_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV92_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV92_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV92_SCRATCH_1
+#define SCRATCH_SECURE_RSV92_SCRATCH_1                  MK_ADDR_CONST(0x348)
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_SCR                      RSV92_SCR_0
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV92_SCR_0
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV92_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV92_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV93_SCRATCH_0
+#define SCRATCH_SECURE_RSV93_SCRATCH_0                  MK_ADDR_CONST(0x34c)
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_SCR                      RSV93_SCR_0
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV93_SCR_0
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV93_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV93_SCRATCH
+#define SCRATCH_SECURE_RSV93_SCRATCH                    MK_ADDR_CONST(0x34c)
+#define SCRATCH_SECURE_RSV93_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV93_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV93_SCRATCH_SCR                        RSV93_SCR_0
+#define SCRATCH_SECURE_RSV93_SCRATCH_SCRREG                     SCRATCH_SCR_RSV93_SCR_0
+#define SCRATCH_SECURE_RSV93_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV93_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV93_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV93_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV93_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV93_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV93_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV93_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV93_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV93_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV93_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV93_SCRATCH_1
+#define SCRATCH_SECURE_RSV93_SCRATCH_1                  MK_ADDR_CONST(0x350)
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_SCR                      RSV93_SCR_0
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV93_SCR_0
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV93_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV93_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV94_SCRATCH_0
+#define SCRATCH_SECURE_RSV94_SCRATCH_0                  MK_ADDR_CONST(0x354)
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_SCR                      RSV94_SCR_0
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV94_SCR_0
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV94_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV94_SCRATCH
+#define SCRATCH_SECURE_RSV94_SCRATCH                    MK_ADDR_CONST(0x354)
+#define SCRATCH_SECURE_RSV94_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV94_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV94_SCRATCH_SCR                        RSV94_SCR_0
+#define SCRATCH_SECURE_RSV94_SCRATCH_SCRREG                     SCRATCH_SCR_RSV94_SCR_0
+#define SCRATCH_SECURE_RSV94_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV94_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV94_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV94_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV94_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV94_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV94_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV94_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV94_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV94_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV94_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV94_SCRATCH_1
+#define SCRATCH_SECURE_RSV94_SCRATCH_1                  MK_ADDR_CONST(0x358)
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_SCR                      RSV94_SCR_0
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV94_SCR_0
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV94_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV94_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV95_SCRATCH_0
+#define SCRATCH_SECURE_RSV95_SCRATCH_0                  MK_ADDR_CONST(0x35c)
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_SCR                      RSV95_SCR_0
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV95_SCR_0
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV95_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV95_SCRATCH
+#define SCRATCH_SECURE_RSV95_SCRATCH                    MK_ADDR_CONST(0x35c)
+#define SCRATCH_SECURE_RSV95_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV95_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV95_SCRATCH_SCR                        RSV95_SCR_0
+#define SCRATCH_SECURE_RSV95_SCRATCH_SCRREG                     SCRATCH_SCR_RSV95_SCR_0
+#define SCRATCH_SECURE_RSV95_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV95_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV95_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV95_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV95_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV95_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV95_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV95_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV95_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV95_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV95_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV95_SCRATCH_1
+#define SCRATCH_SECURE_RSV95_SCRATCH_1                  MK_ADDR_CONST(0x360)
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_SCR                      RSV95_SCR_0
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV95_SCR_0
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV95_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV95_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV96_SCRATCH_0
+#define SCRATCH_SECURE_RSV96_SCRATCH_0                  MK_ADDR_CONST(0x364)
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_SCR                      RSV96_SCR_0
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV96_SCR_0
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV96_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV96_SCRATCH
+#define SCRATCH_SECURE_RSV96_SCRATCH                    MK_ADDR_CONST(0x364)
+#define SCRATCH_SECURE_RSV96_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV96_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV96_SCRATCH_SCR                        RSV96_SCR_0
+#define SCRATCH_SECURE_RSV96_SCRATCH_SCRREG                     SCRATCH_SCR_RSV96_SCR_0
+#define SCRATCH_SECURE_RSV96_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV96_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV96_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV96_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV96_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV96_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV96_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV96_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV96_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV96_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV96_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV96_SCRATCH_1
+#define SCRATCH_SECURE_RSV96_SCRATCH_1                  MK_ADDR_CONST(0x368)
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_SCR                      RSV96_SCR_0
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV96_SCR_0
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV96_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV96_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV97_SCRATCH_0
+#define SCRATCH_SECURE_RSV97_SCRATCH_0                  MK_ADDR_CONST(0x36c)
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_SCR                      RSV97_SCR_0
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV97_SCR_0
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV97_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV97_SCRATCH
+#define SCRATCH_SECURE_RSV97_SCRATCH                    MK_ADDR_CONST(0x36c)
+#define SCRATCH_SECURE_RSV97_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV97_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV97_SCRATCH_SCR                        RSV97_SCR_0
+#define SCRATCH_SECURE_RSV97_SCRATCH_SCRREG                     SCRATCH_SCR_RSV97_SCR_0
+#define SCRATCH_SECURE_RSV97_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV97_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV97_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV97_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV97_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV97_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV97_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV97_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV97_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV97_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV97_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV97_SCRATCH_1
+#define SCRATCH_SECURE_RSV97_SCRATCH_1                  MK_ADDR_CONST(0x370)
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_SCR                      RSV97_SCR_0
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV97_SCR_0
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV97_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV97_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV98_SCRATCH_0
+#define SCRATCH_SECURE_RSV98_SCRATCH_0                  MK_ADDR_CONST(0x374)
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_SCR                      RSV98_SCR_0
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV98_SCR_0
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV98_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV98_SCRATCH
+#define SCRATCH_SECURE_RSV98_SCRATCH                    MK_ADDR_CONST(0x374)
+#define SCRATCH_SECURE_RSV98_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV98_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV98_SCRATCH_SCR                        RSV98_SCR_0
+#define SCRATCH_SECURE_RSV98_SCRATCH_SCRREG                     SCRATCH_SCR_RSV98_SCR_0
+#define SCRATCH_SECURE_RSV98_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV98_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV98_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV98_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV98_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV98_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV98_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV98_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV98_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV98_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV98_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV98_SCRATCH_1
+#define SCRATCH_SECURE_RSV98_SCRATCH_1                  MK_ADDR_CONST(0x378)
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_SCR                      RSV98_SCR_0
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV98_SCR_0
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV98_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV98_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV99_SCRATCH_0
+#define SCRATCH_SECURE_RSV99_SCRATCH_0                  MK_ADDR_CONST(0x37c)
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_SECURE                   0x0
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_DUAL                     0x0
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_SCR                      RSV99_SCR_0
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_SCRREG                   SCRATCH_SCR_RSV99_SCR_0
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV99_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_0_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV99_SCRATCH
+#define SCRATCH_SECURE_RSV99_SCRATCH                    MK_ADDR_CONST(0x37c)
+#define SCRATCH_SECURE_RSV99_SCRATCH_SECURE                     0x0
+#define SCRATCH_SECURE_RSV99_SCRATCH_DUAL                       0x0
+#define SCRATCH_SECURE_RSV99_SCRATCH_SCR                        RSV99_SCR_0
+#define SCRATCH_SECURE_RSV99_SCRATCH_SCRREG                     SCRATCH_SCR_RSV99_SCR_0
+#define SCRATCH_SECURE_RSV99_SCRATCH_WORD_COUNT                         0x1
+#define SCRATCH_SECURE_RSV99_SCRATCH_RESET_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV99_SCRATCH_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV99_SCRATCH_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV99_SCRATCH_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV99_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV99_SCRATCH_DATA_RANGE                 31:0
+#define SCRATCH_SECURE_RSV99_SCRATCH_DATA_MSB                   MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV99_SCRATCH_DATA_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_DATA_WOFFSET                       0x0
+#define SCRATCH_SECURE_RSV99_SCRATCH_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV99_SCRATCH_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV99_SCRATCH_1
+#define SCRATCH_SECURE_RSV99_SCRATCH_1                  MK_ADDR_CONST(0x380)
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_SECURE                   0x0
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_DUAL                     0x0
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_SCR                      RSV99_SCR_0
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_SCRREG                   SCRATCH_SCR_RSV99_SCR_0
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_WORD_COUNT                       0x1
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_WRITE_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_DATA_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_DATA_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV99_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_DATA_RANGE                       31:0
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_DATA_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_DATA_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_DATA_WOFFSET                     0x0
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_DATA_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_DATA_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_DATA_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_DATA_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_DATA_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV99_SCRATCH_1_DATA_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV100_SCRATCH_0
+#define SCRATCH_SECURE_RSV100_SCRATCH_0                 MK_ADDR_CONST(0x384)
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_SECURE                  0x0
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_DUAL                    0x0
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_SCR                     RSV100_SCR_0
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_SCRREG                  SCRATCH_SCR_RSV100_SCR_0
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV100_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_0_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV100_SCRATCH
+#define SCRATCH_SECURE_RSV100_SCRATCH                   MK_ADDR_CONST(0x384)
+#define SCRATCH_SECURE_RSV100_SCRATCH_SECURE                    0x0
+#define SCRATCH_SECURE_RSV100_SCRATCH_DUAL                      0x0
+#define SCRATCH_SECURE_RSV100_SCRATCH_SCR                       RSV100_SCR_0
+#define SCRATCH_SECURE_RSV100_SCRATCH_SCRREG                    SCRATCH_SCR_RSV100_SCR_0
+#define SCRATCH_SECURE_RSV100_SCRATCH_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV100_SCRATCH_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV100_SCRATCH_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV100_SCRATCH_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV100_SCRATCH_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV100_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV100_SCRATCH_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV100_SCRATCH_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV100_SCRATCH_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV100_SCRATCH_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV100_SCRATCH_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV100_SCRATCH_1
+#define SCRATCH_SECURE_RSV100_SCRATCH_1                 MK_ADDR_CONST(0x388)
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_SECURE                  0x0
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_DUAL                    0x0
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_SCR                     RSV100_SCR_0
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_SCRREG                  SCRATCH_SCR_RSV100_SCR_0
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV100_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV100_SCRATCH_1_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV101_SCRATCH_0
+#define SCRATCH_SECURE_RSV101_SCRATCH_0                 MK_ADDR_CONST(0x38c)
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_SECURE                  0x0
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_DUAL                    0x0
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_SCR                     RSV101_SCR_0
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_SCRREG                  SCRATCH_SCR_RSV101_SCR_0
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV101_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_0_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV101_SCRATCH
+#define SCRATCH_SECURE_RSV101_SCRATCH                   MK_ADDR_CONST(0x38c)
+#define SCRATCH_SECURE_RSV101_SCRATCH_SECURE                    0x0
+#define SCRATCH_SECURE_RSV101_SCRATCH_DUAL                      0x0
+#define SCRATCH_SECURE_RSV101_SCRATCH_SCR                       RSV101_SCR_0
+#define SCRATCH_SECURE_RSV101_SCRATCH_SCRREG                    SCRATCH_SCR_RSV101_SCR_0
+#define SCRATCH_SECURE_RSV101_SCRATCH_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV101_SCRATCH_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV101_SCRATCH_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV101_SCRATCH_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV101_SCRATCH_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV101_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV101_SCRATCH_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV101_SCRATCH_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV101_SCRATCH_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV101_SCRATCH_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV101_SCRATCH_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV101_SCRATCH_1
+#define SCRATCH_SECURE_RSV101_SCRATCH_1                 MK_ADDR_CONST(0x390)
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_SECURE                  0x0
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_DUAL                    0x0
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_SCR                     RSV101_SCR_0
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_SCRREG                  SCRATCH_SCR_RSV101_SCR_0
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV101_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV101_SCRATCH_1_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV102_SCRATCH_0
+#define SCRATCH_SECURE_RSV102_SCRATCH_0                 MK_ADDR_CONST(0x394)
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_SECURE                  0x0
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_DUAL                    0x0
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_SCR                     RSV102_SCR_0
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_SCRREG                  SCRATCH_SCR_RSV102_SCR_0
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV102_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_0_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV102_SCRATCH
+#define SCRATCH_SECURE_RSV102_SCRATCH                   MK_ADDR_CONST(0x394)
+#define SCRATCH_SECURE_RSV102_SCRATCH_SECURE                    0x0
+#define SCRATCH_SECURE_RSV102_SCRATCH_DUAL                      0x0
+#define SCRATCH_SECURE_RSV102_SCRATCH_SCR                       RSV102_SCR_0
+#define SCRATCH_SECURE_RSV102_SCRATCH_SCRREG                    SCRATCH_SCR_RSV102_SCR_0
+#define SCRATCH_SECURE_RSV102_SCRATCH_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV102_SCRATCH_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV102_SCRATCH_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV102_SCRATCH_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV102_SCRATCH_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV102_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV102_SCRATCH_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV102_SCRATCH_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV102_SCRATCH_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV102_SCRATCH_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV102_SCRATCH_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV102_SCRATCH_1
+#define SCRATCH_SECURE_RSV102_SCRATCH_1                 MK_ADDR_CONST(0x398)
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_SECURE                  0x0
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_DUAL                    0x0
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_SCR                     RSV102_SCR_0
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_SCRREG                  SCRATCH_SCR_RSV102_SCR_0
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV102_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV102_SCRATCH_1_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV103_SCRATCH_0
+#define SCRATCH_SECURE_RSV103_SCRATCH_0                 MK_ADDR_CONST(0x39c)
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_SECURE                  0x0
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_DUAL                    0x0
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_SCR                     RSV103_SCR_0
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_SCRREG                  SCRATCH_SCR_RSV103_SCR_0
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV103_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_0_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV103_SCRATCH
+#define SCRATCH_SECURE_RSV103_SCRATCH                   MK_ADDR_CONST(0x39c)
+#define SCRATCH_SECURE_RSV103_SCRATCH_SECURE                    0x0
+#define SCRATCH_SECURE_RSV103_SCRATCH_DUAL                      0x0
+#define SCRATCH_SECURE_RSV103_SCRATCH_SCR                       RSV103_SCR_0
+#define SCRATCH_SECURE_RSV103_SCRATCH_SCRREG                    SCRATCH_SCR_RSV103_SCR_0
+#define SCRATCH_SECURE_RSV103_SCRATCH_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV103_SCRATCH_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV103_SCRATCH_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV103_SCRATCH_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV103_SCRATCH_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV103_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV103_SCRATCH_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV103_SCRATCH_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV103_SCRATCH_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV103_SCRATCH_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV103_SCRATCH_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV103_SCRATCH_1
+#define SCRATCH_SECURE_RSV103_SCRATCH_1                 MK_ADDR_CONST(0x3a0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_SECURE                  0x0
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_DUAL                    0x0
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_SCR                     RSV103_SCR_0
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_SCRREG                  SCRATCH_SCR_RSV103_SCR_0
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV103_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV103_SCRATCH_1_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV104_SCRATCH_0
+#define SCRATCH_SECURE_RSV104_SCRATCH_0                 MK_ADDR_CONST(0x3a4)
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_SECURE                  0x0
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_DUAL                    0x0
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_SCR                     RSV104_SCR_0
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_SCRREG                  SCRATCH_SCR_RSV104_SCR_0
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV104_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_0_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV104_SCRATCH
+#define SCRATCH_SECURE_RSV104_SCRATCH                   MK_ADDR_CONST(0x3a4)
+#define SCRATCH_SECURE_RSV104_SCRATCH_SECURE                    0x0
+#define SCRATCH_SECURE_RSV104_SCRATCH_DUAL                      0x0
+#define SCRATCH_SECURE_RSV104_SCRATCH_SCR                       RSV104_SCR_0
+#define SCRATCH_SECURE_RSV104_SCRATCH_SCRREG                    SCRATCH_SCR_RSV104_SCR_0
+#define SCRATCH_SECURE_RSV104_SCRATCH_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV104_SCRATCH_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV104_SCRATCH_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV104_SCRATCH_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV104_SCRATCH_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV104_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV104_SCRATCH_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV104_SCRATCH_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV104_SCRATCH_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV104_SCRATCH_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV104_SCRATCH_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV104_SCRATCH_1
+#define SCRATCH_SECURE_RSV104_SCRATCH_1                 MK_ADDR_CONST(0x3a8)
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_SECURE                  0x0
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_DUAL                    0x0
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_SCR                     RSV104_SCR_0
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_SCRREG                  SCRATCH_SCR_RSV104_SCR_0
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV104_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV104_SCRATCH_1_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV105_SCRATCH_0
+#define SCRATCH_SECURE_RSV105_SCRATCH_0                 MK_ADDR_CONST(0x3ac)
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_SECURE                  0x0
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_DUAL                    0x0
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_SCR                     RSV105_SCR_0
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_SCRREG                  SCRATCH_SCR_RSV105_SCR_0
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV105_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_0_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV105_SCRATCH
+#define SCRATCH_SECURE_RSV105_SCRATCH                   MK_ADDR_CONST(0x3ac)
+#define SCRATCH_SECURE_RSV105_SCRATCH_SECURE                    0x0
+#define SCRATCH_SECURE_RSV105_SCRATCH_DUAL                      0x0
+#define SCRATCH_SECURE_RSV105_SCRATCH_SCR                       RSV105_SCR_0
+#define SCRATCH_SECURE_RSV105_SCRATCH_SCRREG                    SCRATCH_SCR_RSV105_SCR_0
+#define SCRATCH_SECURE_RSV105_SCRATCH_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV105_SCRATCH_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV105_SCRATCH_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV105_SCRATCH_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV105_SCRATCH_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV105_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV105_SCRATCH_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV105_SCRATCH_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV105_SCRATCH_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV105_SCRATCH_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV105_SCRATCH_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV105_SCRATCH_1
+#define SCRATCH_SECURE_RSV105_SCRATCH_1                 MK_ADDR_CONST(0x3b0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_SECURE                  0x0
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_DUAL                    0x0
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_SCR                     RSV105_SCR_0
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_SCRREG                  SCRATCH_SCR_RSV105_SCR_0
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV105_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV105_SCRATCH_1_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV106_SCRATCH_0
+#define SCRATCH_SECURE_RSV106_SCRATCH_0                 MK_ADDR_CONST(0x3b4)
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_SECURE                  0x0
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_DUAL                    0x0
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_SCR                     RSV106_SCR_0
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_SCRREG                  SCRATCH_SCR_RSV106_SCR_0
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV106_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_0_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV106_SCRATCH
+#define SCRATCH_SECURE_RSV106_SCRATCH                   MK_ADDR_CONST(0x3b4)
+#define SCRATCH_SECURE_RSV106_SCRATCH_SECURE                    0x0
+#define SCRATCH_SECURE_RSV106_SCRATCH_DUAL                      0x0
+#define SCRATCH_SECURE_RSV106_SCRATCH_SCR                       RSV106_SCR_0
+#define SCRATCH_SECURE_RSV106_SCRATCH_SCRREG                    SCRATCH_SCR_RSV106_SCR_0
+#define SCRATCH_SECURE_RSV106_SCRATCH_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV106_SCRATCH_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV106_SCRATCH_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV106_SCRATCH_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV106_SCRATCH_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV106_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV106_SCRATCH_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV106_SCRATCH_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV106_SCRATCH_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV106_SCRATCH_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV106_SCRATCH_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV106_SCRATCH_1
+#define SCRATCH_SECURE_RSV106_SCRATCH_1                 MK_ADDR_CONST(0x3b8)
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_SECURE                  0x0
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_DUAL                    0x0
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_SCR                     RSV106_SCR_0
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_SCRREG                  SCRATCH_SCR_RSV106_SCR_0
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV106_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV106_SCRATCH_1_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV107_SCRATCH_0
+#define SCRATCH_SECURE_RSV107_SCRATCH_0                 MK_ADDR_CONST(0x3bc)
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_SECURE                  0x0
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_DUAL                    0x0
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_SCR                     RSV107_SCR_0
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_SCRREG                  SCRATCH_SCR_RSV107_SCR_0
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV107_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_0_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV107_SCRATCH
+#define SCRATCH_SECURE_RSV107_SCRATCH                   MK_ADDR_CONST(0x3bc)
+#define SCRATCH_SECURE_RSV107_SCRATCH_SECURE                    0x0
+#define SCRATCH_SECURE_RSV107_SCRATCH_DUAL                      0x0
+#define SCRATCH_SECURE_RSV107_SCRATCH_SCR                       RSV107_SCR_0
+#define SCRATCH_SECURE_RSV107_SCRATCH_SCRREG                    SCRATCH_SCR_RSV107_SCR_0
+#define SCRATCH_SECURE_RSV107_SCRATCH_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV107_SCRATCH_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV107_SCRATCH_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV107_SCRATCH_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV107_SCRATCH_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV107_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV107_SCRATCH_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV107_SCRATCH_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV107_SCRATCH_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV107_SCRATCH_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV107_SCRATCH_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV107_SCRATCH_1
+#define SCRATCH_SECURE_RSV107_SCRATCH_1                 MK_ADDR_CONST(0x3c0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_SECURE                  0x0
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_DUAL                    0x0
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_SCR                     RSV107_SCR_0
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_SCRREG                  SCRATCH_SCR_RSV107_SCR_0
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV107_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV107_SCRATCH_1_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV108_SCRATCH_0
+#define SCRATCH_SECURE_RSV108_SCRATCH_0                 MK_ADDR_CONST(0x3c4)
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_SECURE                  0x0
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_DUAL                    0x0
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_SCR                     RSV108_SCR_0
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_SCRREG                  SCRATCH_SCR_RSV108_SCR_0
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV108_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_0_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV108_SCRATCH
+#define SCRATCH_SECURE_RSV108_SCRATCH                   MK_ADDR_CONST(0x3c4)
+#define SCRATCH_SECURE_RSV108_SCRATCH_SECURE                    0x0
+#define SCRATCH_SECURE_RSV108_SCRATCH_DUAL                      0x0
+#define SCRATCH_SECURE_RSV108_SCRATCH_SCR                       RSV108_SCR_0
+#define SCRATCH_SECURE_RSV108_SCRATCH_SCRREG                    SCRATCH_SCR_RSV108_SCR_0
+#define SCRATCH_SECURE_RSV108_SCRATCH_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV108_SCRATCH_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV108_SCRATCH_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV108_SCRATCH_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV108_SCRATCH_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV108_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV108_SCRATCH_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV108_SCRATCH_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV108_SCRATCH_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV108_SCRATCH_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV108_SCRATCH_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV108_SCRATCH_1
+#define SCRATCH_SECURE_RSV108_SCRATCH_1                 MK_ADDR_CONST(0x3c8)
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_SECURE                  0x0
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_DUAL                    0x0
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_SCR                     RSV108_SCR_0
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_SCRREG                  SCRATCH_SCR_RSV108_SCR_0
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV108_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV108_SCRATCH_1_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV109_SCRATCH_0
+#define SCRATCH_SECURE_RSV109_SCRATCH_0                 MK_ADDR_CONST(0x3cc)
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_SECURE                  0x0
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_DUAL                    0x0
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_SCR                     RSV109_SCR_0
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_SCRREG                  SCRATCH_SCR_RSV109_SCR_0
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV109_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_0_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV109_SCRATCH
+#define SCRATCH_SECURE_RSV109_SCRATCH                   MK_ADDR_CONST(0x3cc)
+#define SCRATCH_SECURE_RSV109_SCRATCH_SECURE                    0x0
+#define SCRATCH_SECURE_RSV109_SCRATCH_DUAL                      0x0
+#define SCRATCH_SECURE_RSV109_SCRATCH_SCR                       RSV109_SCR_0
+#define SCRATCH_SECURE_RSV109_SCRATCH_SCRREG                    SCRATCH_SCR_RSV109_SCR_0
+#define SCRATCH_SECURE_RSV109_SCRATCH_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV109_SCRATCH_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV109_SCRATCH_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV109_SCRATCH_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV109_SCRATCH_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV109_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV109_SCRATCH_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV109_SCRATCH_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV109_SCRATCH_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV109_SCRATCH_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV109_SCRATCH_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV109_SCRATCH_1
+#define SCRATCH_SECURE_RSV109_SCRATCH_1                 MK_ADDR_CONST(0x3d0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_SECURE                  0x0
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_DUAL                    0x0
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_SCR                     RSV109_SCR_0
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_SCRREG                  SCRATCH_SCR_RSV109_SCR_0
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV109_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV109_SCRATCH_1_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV110_SCRATCH_0
+#define SCRATCH_SECURE_RSV110_SCRATCH_0                 MK_ADDR_CONST(0x3d4)
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_SECURE                  0x0
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_DUAL                    0x0
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_SCR                     RSV110_SCR_0
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_SCRREG                  SCRATCH_SCR_RSV110_SCR_0
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV110_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_0_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV110_SCRATCH
+#define SCRATCH_SECURE_RSV110_SCRATCH                   MK_ADDR_CONST(0x3d4)
+#define SCRATCH_SECURE_RSV110_SCRATCH_SECURE                    0x0
+#define SCRATCH_SECURE_RSV110_SCRATCH_DUAL                      0x0
+#define SCRATCH_SECURE_RSV110_SCRATCH_SCR                       RSV110_SCR_0
+#define SCRATCH_SECURE_RSV110_SCRATCH_SCRREG                    SCRATCH_SCR_RSV110_SCR_0
+#define SCRATCH_SECURE_RSV110_SCRATCH_WORD_COUNT                        0x1
+#define SCRATCH_SECURE_RSV110_SCRATCH_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV110_SCRATCH_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV110_SCRATCH_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV110_SCRATCH_DATA_SHIFT                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_DATA_FIELD                        MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV110_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV110_SCRATCH_DATA_RANGE                        31:0
+#define SCRATCH_SECURE_RSV110_SCRATCH_DATA_MSB                  MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV110_SCRATCH_DATA_LSB                  MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_DATA_WOFFSET                      0x0
+#define SCRATCH_SECURE_RSV110_SCRATCH_DATA_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_DATA_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV110_SCRATCH_DATA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_DATA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_DATA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_DATA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SECURE_RSV110_SCRATCH_1
+#define SCRATCH_SECURE_RSV110_SCRATCH_1                 MK_ADDR_CONST(0x3d8)
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_SECURE                  0x0
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_DUAL                    0x0
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_SCR                     RSV110_SCR_0
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_SCRREG                  SCRATCH_SCR_RSV110_SCR_0
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_WORD_COUNT                      0x1
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SECURE_RSV110_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_DATA_RANGE                      31:0
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_DATA_WOFFSET                    0x0
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SECURE_RSV110_SCRATCH_1_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_0
+#define SCRATCH_SCRATCH_0                       MK_ADDR_CONST(0x3dc)
+#define SCRATCH_SCRATCH_0_SECURE                        0x0
+#define SCRATCH_SCRATCH_0_DUAL                  0x0
+#define SCRATCH_SCRATCH_0_SCR                   NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_0_SCRREG                        SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_0_WORD_COUNT                    0x1
+#define SCRATCH_SCRATCH_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_0_DATA_SHIFT                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_0_DATA_FIELD                    MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_0_DATA_SHIFT)
+#define SCRATCH_SCRATCH_0_DATA_RANGE                    31:0
+#define SCRATCH_SCRATCH_0_DATA_MSB                      MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_0_DATA_LSB                      MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_0_DATA_WOFFSET                  0x0
+#define SCRATCH_SCRATCH_0_DATA_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_0_DATA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_0_DATA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_0_DATA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_0_DATA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_0_DATA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH
+#define SCRATCH_SCRATCH                 MK_ADDR_CONST(0x3dc)
+#define SCRATCH_SCRATCH_SECURE                  0x0
+#define SCRATCH_SCRATCH_DUAL                    0x0
+#define SCRATCH_SCRATCH_SCR                     NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_SCRREG                  SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_WORD_COUNT                      0x1
+#define SCRATCH_SCRATCH_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_DATA_SHIFT)
+#define SCRATCH_SCRATCH_DATA_RANGE                      31:0
+#define SCRATCH_SCRATCH_DATA_MSB                        MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_DATA_LSB                        MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_DATA_WOFFSET                    0x0
+#define SCRATCH_SCRATCH_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_1
+#define SCRATCH_SCRATCH_1                       MK_ADDR_CONST(0x3e0)
+#define SCRATCH_SCRATCH_1_SECURE                        0x0
+#define SCRATCH_SCRATCH_1_DUAL                  0x0
+#define SCRATCH_SCRATCH_1_SCR                   NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_1_SCRREG                        SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_1_WORD_COUNT                    0x1
+#define SCRATCH_SCRATCH_1_RESET_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_1_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_1_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_1_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_1_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_1_DATA_SHIFT                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_1_DATA_FIELD                    MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_1_DATA_SHIFT)
+#define SCRATCH_SCRATCH_1_DATA_RANGE                    31:0
+#define SCRATCH_SCRATCH_1_DATA_MSB                      MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_1_DATA_LSB                      MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_1_DATA_WOFFSET                  0x0
+#define SCRATCH_SCRATCH_1_DATA_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_1_DATA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_1_DATA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_1_DATA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_1_DATA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_1_DATA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_2
+#define SCRATCH_SCRATCH_2                       MK_ADDR_CONST(0x3e4)
+#define SCRATCH_SCRATCH_2_SECURE                        0x0
+#define SCRATCH_SCRATCH_2_DUAL                  0x0
+#define SCRATCH_SCRATCH_2_SCR                   NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_2_SCRREG                        SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_2_WORD_COUNT                    0x1
+#define SCRATCH_SCRATCH_2_RESET_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_2_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_2_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_2_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_2_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_2_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_2_DATA_SHIFT                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_2_DATA_FIELD                    MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_2_DATA_SHIFT)
+#define SCRATCH_SCRATCH_2_DATA_RANGE                    31:0
+#define SCRATCH_SCRATCH_2_DATA_MSB                      MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_2_DATA_LSB                      MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_2_DATA_WOFFSET                  0x0
+#define SCRATCH_SCRATCH_2_DATA_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_2_DATA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_2_DATA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_2_DATA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_2_DATA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_2_DATA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_3
+#define SCRATCH_SCRATCH_3                       MK_ADDR_CONST(0x3e8)
+#define SCRATCH_SCRATCH_3_SECURE                        0x0
+#define SCRATCH_SCRATCH_3_DUAL                  0x0
+#define SCRATCH_SCRATCH_3_SCR                   NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_3_SCRREG                        SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_3_WORD_COUNT                    0x1
+#define SCRATCH_SCRATCH_3_RESET_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_3_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_3_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_3_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_3_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_3_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_3_DATA_SHIFT                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_3_DATA_FIELD                    MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_3_DATA_SHIFT)
+#define SCRATCH_SCRATCH_3_DATA_RANGE                    31:0
+#define SCRATCH_SCRATCH_3_DATA_MSB                      MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_3_DATA_LSB                      MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_3_DATA_WOFFSET                  0x0
+#define SCRATCH_SCRATCH_3_DATA_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_3_DATA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_3_DATA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_3_DATA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_3_DATA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_3_DATA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_4
+#define SCRATCH_SCRATCH_4                       MK_ADDR_CONST(0x3ec)
+#define SCRATCH_SCRATCH_4_SECURE                        0x0
+#define SCRATCH_SCRATCH_4_DUAL                  0x0
+#define SCRATCH_SCRATCH_4_SCR                   NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_4_SCRREG                        SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_4_WORD_COUNT                    0x1
+#define SCRATCH_SCRATCH_4_RESET_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_4_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_4_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_4_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_4_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_4_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_4_DATA_SHIFT                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_4_DATA_FIELD                    MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_4_DATA_SHIFT)
+#define SCRATCH_SCRATCH_4_DATA_RANGE                    31:0
+#define SCRATCH_SCRATCH_4_DATA_MSB                      MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_4_DATA_LSB                      MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_4_DATA_WOFFSET                  0x0
+#define SCRATCH_SCRATCH_4_DATA_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_4_DATA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_4_DATA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_4_DATA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_4_DATA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_4_DATA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_5
+#define SCRATCH_SCRATCH_5                       MK_ADDR_CONST(0x3f0)
+#define SCRATCH_SCRATCH_5_SECURE                        0x0
+#define SCRATCH_SCRATCH_5_DUAL                  0x0
+#define SCRATCH_SCRATCH_5_SCR                   NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_5_SCRREG                        SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_5_WORD_COUNT                    0x1
+#define SCRATCH_SCRATCH_5_RESET_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_5_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_5_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_5_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_5_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_5_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_5_DATA_SHIFT                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_5_DATA_FIELD                    MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_5_DATA_SHIFT)
+#define SCRATCH_SCRATCH_5_DATA_RANGE                    31:0
+#define SCRATCH_SCRATCH_5_DATA_MSB                      MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_5_DATA_LSB                      MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_5_DATA_WOFFSET                  0x0
+#define SCRATCH_SCRATCH_5_DATA_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_5_DATA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_5_DATA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_5_DATA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_5_DATA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_5_DATA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_6
+#define SCRATCH_SCRATCH_6                       MK_ADDR_CONST(0x3f4)
+#define SCRATCH_SCRATCH_6_SECURE                        0x0
+#define SCRATCH_SCRATCH_6_DUAL                  0x0
+#define SCRATCH_SCRATCH_6_SCR                   NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_6_SCRREG                        SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_6_WORD_COUNT                    0x1
+#define SCRATCH_SCRATCH_6_RESET_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_6_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_6_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_6_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_6_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_6_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_6_DATA_SHIFT                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_6_DATA_FIELD                    MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_6_DATA_SHIFT)
+#define SCRATCH_SCRATCH_6_DATA_RANGE                    31:0
+#define SCRATCH_SCRATCH_6_DATA_MSB                      MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_6_DATA_LSB                      MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_6_DATA_WOFFSET                  0x0
+#define SCRATCH_SCRATCH_6_DATA_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_6_DATA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_6_DATA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_6_DATA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_6_DATA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_6_DATA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_7
+#define SCRATCH_SCRATCH_7                       MK_ADDR_CONST(0x3f8)
+#define SCRATCH_SCRATCH_7_SECURE                        0x0
+#define SCRATCH_SCRATCH_7_DUAL                  0x0
+#define SCRATCH_SCRATCH_7_SCR                   NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_7_SCRREG                        SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_7_WORD_COUNT                    0x1
+#define SCRATCH_SCRATCH_7_RESET_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_7_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_7_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_7_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_7_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_7_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_7_DATA_SHIFT                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_7_DATA_FIELD                    MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_7_DATA_SHIFT)
+#define SCRATCH_SCRATCH_7_DATA_RANGE                    31:0
+#define SCRATCH_SCRATCH_7_DATA_MSB                      MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_7_DATA_LSB                      MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_7_DATA_WOFFSET                  0x0
+#define SCRATCH_SCRATCH_7_DATA_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_7_DATA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_7_DATA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_7_DATA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_7_DATA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_7_DATA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_8
+#define SCRATCH_SCRATCH_8                       MK_ADDR_CONST(0x3fc)
+#define SCRATCH_SCRATCH_8_SECURE                        0x0
+#define SCRATCH_SCRATCH_8_DUAL                  0x0
+#define SCRATCH_SCRATCH_8_SCR                   NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_8_SCRREG                        SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_8_WORD_COUNT                    0x1
+#define SCRATCH_SCRATCH_8_RESET_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_8_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_8_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_8_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_8_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_8_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_8_DATA_SHIFT                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_8_DATA_FIELD                    MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_8_DATA_SHIFT)
+#define SCRATCH_SCRATCH_8_DATA_RANGE                    31:0
+#define SCRATCH_SCRATCH_8_DATA_MSB                      MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_8_DATA_LSB                      MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_8_DATA_WOFFSET                  0x0
+#define SCRATCH_SCRATCH_8_DATA_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_8_DATA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_8_DATA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_8_DATA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_8_DATA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_8_DATA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_9
+#define SCRATCH_SCRATCH_9                       MK_ADDR_CONST(0x400)
+#define SCRATCH_SCRATCH_9_SECURE                        0x0
+#define SCRATCH_SCRATCH_9_DUAL                  0x0
+#define SCRATCH_SCRATCH_9_SCR                   NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_9_SCRREG                        SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_9_WORD_COUNT                    0x1
+#define SCRATCH_SCRATCH_9_RESET_VAL                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_9_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_9_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_9_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_9_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_9_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_9_DATA_SHIFT                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_9_DATA_FIELD                    MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_9_DATA_SHIFT)
+#define SCRATCH_SCRATCH_9_DATA_RANGE                    31:0
+#define SCRATCH_SCRATCH_9_DATA_MSB                      MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_9_DATA_LSB                      MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_9_DATA_WOFFSET                  0x0
+#define SCRATCH_SCRATCH_9_DATA_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_9_DATA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_9_DATA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_9_DATA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_9_DATA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_9_DATA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_10
+#define SCRATCH_SCRATCH_10                      MK_ADDR_CONST(0x404)
+#define SCRATCH_SCRATCH_10_SECURE                       0x0
+#define SCRATCH_SCRATCH_10_DUAL                         0x0
+#define SCRATCH_SCRATCH_10_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_10_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_10_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_10_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_10_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_10_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_10_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_10_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_10_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_10_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_10_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_10_DATA_SHIFT)
+#define SCRATCH_SCRATCH_10_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_10_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_10_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_10_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_10_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_10_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_10_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_10_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_10_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_10_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_11
+#define SCRATCH_SCRATCH_11                      MK_ADDR_CONST(0x408)
+#define SCRATCH_SCRATCH_11_SECURE                       0x0
+#define SCRATCH_SCRATCH_11_DUAL                         0x0
+#define SCRATCH_SCRATCH_11_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_11_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_11_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_11_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_11_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_11_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_11_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_11_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_11_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_11_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_11_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_11_DATA_SHIFT)
+#define SCRATCH_SCRATCH_11_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_11_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_11_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_11_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_11_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_11_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_11_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_11_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_11_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_11_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_12
+#define SCRATCH_SCRATCH_12                      MK_ADDR_CONST(0x40c)
+#define SCRATCH_SCRATCH_12_SECURE                       0x0
+#define SCRATCH_SCRATCH_12_DUAL                         0x0
+#define SCRATCH_SCRATCH_12_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_12_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_12_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_12_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_12_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_12_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_12_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_12_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_12_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_12_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_12_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_12_DATA_SHIFT)
+#define SCRATCH_SCRATCH_12_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_12_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_12_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_12_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_12_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_12_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_12_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_12_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_12_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_12_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_13
+#define SCRATCH_SCRATCH_13                      MK_ADDR_CONST(0x410)
+#define SCRATCH_SCRATCH_13_SECURE                       0x0
+#define SCRATCH_SCRATCH_13_DUAL                         0x0
+#define SCRATCH_SCRATCH_13_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_13_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_13_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_13_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_13_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_13_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_13_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_13_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_13_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_13_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_13_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_13_DATA_SHIFT)
+#define SCRATCH_SCRATCH_13_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_13_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_13_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_13_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_13_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_13_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_13_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_13_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_13_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_13_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_14
+#define SCRATCH_SCRATCH_14                      MK_ADDR_CONST(0x414)
+#define SCRATCH_SCRATCH_14_SECURE                       0x0
+#define SCRATCH_SCRATCH_14_DUAL                         0x0
+#define SCRATCH_SCRATCH_14_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_14_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_14_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_14_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_14_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_14_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_14_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_14_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_14_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_14_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_14_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_14_DATA_SHIFT)
+#define SCRATCH_SCRATCH_14_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_14_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_14_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_14_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_14_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_14_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_14_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_14_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_14_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_14_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_15
+#define SCRATCH_SCRATCH_15                      MK_ADDR_CONST(0x418)
+#define SCRATCH_SCRATCH_15_SECURE                       0x0
+#define SCRATCH_SCRATCH_15_DUAL                         0x0
+#define SCRATCH_SCRATCH_15_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_15_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_15_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_15_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_15_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_15_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_15_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_15_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_15_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_15_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_15_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_15_DATA_SHIFT)
+#define SCRATCH_SCRATCH_15_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_15_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_15_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_15_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_15_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_15_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_15_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_15_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_15_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_15_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_16
+#define SCRATCH_SCRATCH_16                      MK_ADDR_CONST(0x41c)
+#define SCRATCH_SCRATCH_16_SECURE                       0x0
+#define SCRATCH_SCRATCH_16_DUAL                         0x0
+#define SCRATCH_SCRATCH_16_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_16_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_16_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_16_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_16_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_16_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_16_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_16_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_16_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_16_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_16_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_16_DATA_SHIFT)
+#define SCRATCH_SCRATCH_16_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_16_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_16_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_16_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_16_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_16_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_16_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_16_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_16_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_16_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_17
+#define SCRATCH_SCRATCH_17                      MK_ADDR_CONST(0x420)
+#define SCRATCH_SCRATCH_17_SECURE                       0x0
+#define SCRATCH_SCRATCH_17_DUAL                         0x0
+#define SCRATCH_SCRATCH_17_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_17_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_17_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_17_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_17_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_17_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_17_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_17_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_17_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_17_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_17_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_17_DATA_SHIFT)
+#define SCRATCH_SCRATCH_17_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_17_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_17_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_17_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_17_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_17_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_17_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_17_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_17_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_17_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_18
+#define SCRATCH_SCRATCH_18                      MK_ADDR_CONST(0x424)
+#define SCRATCH_SCRATCH_18_SECURE                       0x0
+#define SCRATCH_SCRATCH_18_DUAL                         0x0
+#define SCRATCH_SCRATCH_18_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_18_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_18_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_18_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_18_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_18_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_18_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_18_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_18_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_18_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_18_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_18_DATA_SHIFT)
+#define SCRATCH_SCRATCH_18_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_18_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_18_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_18_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_18_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_18_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_18_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_18_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_18_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_18_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_19
+#define SCRATCH_SCRATCH_19                      MK_ADDR_CONST(0x428)
+#define SCRATCH_SCRATCH_19_SECURE                       0x0
+#define SCRATCH_SCRATCH_19_DUAL                         0x0
+#define SCRATCH_SCRATCH_19_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_19_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_19_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_19_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_19_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_19_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_19_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_19_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_19_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_19_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_19_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_19_DATA_SHIFT)
+#define SCRATCH_SCRATCH_19_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_19_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_19_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_19_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_19_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_19_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_19_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_19_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_19_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_19_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_20
+#define SCRATCH_SCRATCH_20                      MK_ADDR_CONST(0x42c)
+#define SCRATCH_SCRATCH_20_SECURE                       0x0
+#define SCRATCH_SCRATCH_20_DUAL                         0x0
+#define SCRATCH_SCRATCH_20_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_20_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_20_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_20_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_20_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_20_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_20_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_20_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_20_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_20_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_20_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_20_DATA_SHIFT)
+#define SCRATCH_SCRATCH_20_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_20_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_20_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_20_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_20_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_20_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_20_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_20_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_20_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_20_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_21
+#define SCRATCH_SCRATCH_21                      MK_ADDR_CONST(0x430)
+#define SCRATCH_SCRATCH_21_SECURE                       0x0
+#define SCRATCH_SCRATCH_21_DUAL                         0x0
+#define SCRATCH_SCRATCH_21_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_21_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_21_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_21_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_21_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_21_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_21_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_21_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_21_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_21_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_21_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_21_DATA_SHIFT)
+#define SCRATCH_SCRATCH_21_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_21_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_21_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_21_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_21_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_21_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_21_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_21_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_21_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_21_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_22
+#define SCRATCH_SCRATCH_22                      MK_ADDR_CONST(0x434)
+#define SCRATCH_SCRATCH_22_SECURE                       0x0
+#define SCRATCH_SCRATCH_22_DUAL                         0x0
+#define SCRATCH_SCRATCH_22_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_22_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_22_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_22_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_22_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_22_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_22_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_22_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_22_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_22_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_22_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_22_DATA_SHIFT)
+#define SCRATCH_SCRATCH_22_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_22_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_22_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_22_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_22_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_22_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_22_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_22_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_22_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_22_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_23
+#define SCRATCH_SCRATCH_23                      MK_ADDR_CONST(0x438)
+#define SCRATCH_SCRATCH_23_SECURE                       0x0
+#define SCRATCH_SCRATCH_23_DUAL                         0x0
+#define SCRATCH_SCRATCH_23_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_23_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_23_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_23_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_23_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_23_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_23_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_23_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_23_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_23_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_23_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_23_DATA_SHIFT)
+#define SCRATCH_SCRATCH_23_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_23_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_23_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_23_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_23_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_23_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_23_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_23_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_23_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_23_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_24
+#define SCRATCH_SCRATCH_24                      MK_ADDR_CONST(0x43c)
+#define SCRATCH_SCRATCH_24_SECURE                       0x0
+#define SCRATCH_SCRATCH_24_DUAL                         0x0
+#define SCRATCH_SCRATCH_24_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_24_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_24_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_24_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_24_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_24_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_24_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_24_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_24_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_24_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_24_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_24_DATA_SHIFT)
+#define SCRATCH_SCRATCH_24_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_24_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_24_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_24_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_24_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_24_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_24_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_24_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_24_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_24_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_25
+#define SCRATCH_SCRATCH_25                      MK_ADDR_CONST(0x440)
+#define SCRATCH_SCRATCH_25_SECURE                       0x0
+#define SCRATCH_SCRATCH_25_DUAL                         0x0
+#define SCRATCH_SCRATCH_25_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_25_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_25_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_25_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_25_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_25_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_25_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_25_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_25_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_25_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_25_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_25_DATA_SHIFT)
+#define SCRATCH_SCRATCH_25_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_25_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_25_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_25_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_25_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_25_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_25_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_25_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_25_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_25_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_26
+#define SCRATCH_SCRATCH_26                      MK_ADDR_CONST(0x444)
+#define SCRATCH_SCRATCH_26_SECURE                       0x0
+#define SCRATCH_SCRATCH_26_DUAL                         0x0
+#define SCRATCH_SCRATCH_26_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_26_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_26_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_26_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_26_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_26_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_26_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_26_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_26_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_26_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_26_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_26_DATA_SHIFT)
+#define SCRATCH_SCRATCH_26_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_26_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_26_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_26_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_26_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_26_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_26_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_26_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_26_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_26_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_27
+#define SCRATCH_SCRATCH_27                      MK_ADDR_CONST(0x448)
+#define SCRATCH_SCRATCH_27_SECURE                       0x0
+#define SCRATCH_SCRATCH_27_DUAL                         0x0
+#define SCRATCH_SCRATCH_27_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_27_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_27_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_27_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_27_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_27_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_27_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_27_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_27_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_27_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_27_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_27_DATA_SHIFT)
+#define SCRATCH_SCRATCH_27_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_27_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_27_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_27_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_27_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_27_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_27_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_27_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_27_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_27_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_28
+#define SCRATCH_SCRATCH_28                      MK_ADDR_CONST(0x44c)
+#define SCRATCH_SCRATCH_28_SECURE                       0x0
+#define SCRATCH_SCRATCH_28_DUAL                         0x0
+#define SCRATCH_SCRATCH_28_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_28_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_28_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_28_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_28_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_28_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_28_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_28_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_28_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_28_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_28_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_28_DATA_SHIFT)
+#define SCRATCH_SCRATCH_28_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_28_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_28_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_28_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_28_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_28_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_28_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_28_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_28_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_28_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_29
+#define SCRATCH_SCRATCH_29                      MK_ADDR_CONST(0x450)
+#define SCRATCH_SCRATCH_29_SECURE                       0x0
+#define SCRATCH_SCRATCH_29_DUAL                         0x0
+#define SCRATCH_SCRATCH_29_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_29_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_29_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_29_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_29_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_29_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_29_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_29_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_29_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_29_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_29_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_29_DATA_SHIFT)
+#define SCRATCH_SCRATCH_29_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_29_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_29_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_29_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_29_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_29_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_29_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_29_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_29_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_29_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_30
+#define SCRATCH_SCRATCH_30                      MK_ADDR_CONST(0x454)
+#define SCRATCH_SCRATCH_30_SECURE                       0x0
+#define SCRATCH_SCRATCH_30_DUAL                         0x0
+#define SCRATCH_SCRATCH_30_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_30_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_30_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_30_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_30_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_30_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_30_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_30_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_30_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_30_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_30_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_30_DATA_SHIFT)
+#define SCRATCH_SCRATCH_30_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_30_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_30_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_30_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_30_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_30_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_30_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_30_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_30_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_30_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_31
+#define SCRATCH_SCRATCH_31                      MK_ADDR_CONST(0x458)
+#define SCRATCH_SCRATCH_31_SECURE                       0x0
+#define SCRATCH_SCRATCH_31_DUAL                         0x0
+#define SCRATCH_SCRATCH_31_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_31_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_31_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_31_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_31_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_31_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_31_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_31_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_31_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_31_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_31_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_31_DATA_SHIFT)
+#define SCRATCH_SCRATCH_31_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_31_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_31_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_31_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_31_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_31_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_31_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_31_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_31_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_31_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_32
+#define SCRATCH_SCRATCH_32                      MK_ADDR_CONST(0x45c)
+#define SCRATCH_SCRATCH_32_SECURE                       0x0
+#define SCRATCH_SCRATCH_32_DUAL                         0x0
+#define SCRATCH_SCRATCH_32_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_32_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_32_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_32_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_32_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_32_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_32_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_32_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_32_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_32_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_32_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_32_DATA_SHIFT)
+#define SCRATCH_SCRATCH_32_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_32_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_32_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_32_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_32_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_32_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_32_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_32_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_32_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_32_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_33
+#define SCRATCH_SCRATCH_33                      MK_ADDR_CONST(0x460)
+#define SCRATCH_SCRATCH_33_SECURE                       0x0
+#define SCRATCH_SCRATCH_33_DUAL                         0x0
+#define SCRATCH_SCRATCH_33_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_33_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_33_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_33_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_33_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_33_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_33_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_33_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_33_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_33_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_33_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_33_DATA_SHIFT)
+#define SCRATCH_SCRATCH_33_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_33_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_33_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_33_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_33_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_33_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_33_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_33_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_33_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_33_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_34
+#define SCRATCH_SCRATCH_34                      MK_ADDR_CONST(0x464)
+#define SCRATCH_SCRATCH_34_SECURE                       0x0
+#define SCRATCH_SCRATCH_34_DUAL                         0x0
+#define SCRATCH_SCRATCH_34_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_34_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_34_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_34_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_34_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_34_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_34_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_34_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_34_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_34_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_34_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_34_DATA_SHIFT)
+#define SCRATCH_SCRATCH_34_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_34_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_34_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_34_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_34_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_34_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_34_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_34_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_34_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_34_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_35
+#define SCRATCH_SCRATCH_35                      MK_ADDR_CONST(0x468)
+#define SCRATCH_SCRATCH_35_SECURE                       0x0
+#define SCRATCH_SCRATCH_35_DUAL                         0x0
+#define SCRATCH_SCRATCH_35_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_35_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_35_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_35_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_35_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_35_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_35_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_35_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_35_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_35_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_35_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_35_DATA_SHIFT)
+#define SCRATCH_SCRATCH_35_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_35_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_35_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_35_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_35_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_35_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_35_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_35_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_35_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_35_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_36
+#define SCRATCH_SCRATCH_36                      MK_ADDR_CONST(0x46c)
+#define SCRATCH_SCRATCH_36_SECURE                       0x0
+#define SCRATCH_SCRATCH_36_DUAL                         0x0
+#define SCRATCH_SCRATCH_36_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_36_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_36_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_36_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_36_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_36_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_36_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_36_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_36_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_36_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_36_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_36_DATA_SHIFT)
+#define SCRATCH_SCRATCH_36_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_36_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_36_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_36_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_36_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_36_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_36_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_36_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_36_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_36_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_37
+#define SCRATCH_SCRATCH_37                      MK_ADDR_CONST(0x470)
+#define SCRATCH_SCRATCH_37_SECURE                       0x0
+#define SCRATCH_SCRATCH_37_DUAL                         0x0
+#define SCRATCH_SCRATCH_37_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_37_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_37_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_37_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_37_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_37_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_37_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_37_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_37_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_37_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_37_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_37_DATA_SHIFT)
+#define SCRATCH_SCRATCH_37_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_37_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_37_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_37_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_37_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_37_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_37_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_37_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_37_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_37_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_38
+#define SCRATCH_SCRATCH_38                      MK_ADDR_CONST(0x474)
+#define SCRATCH_SCRATCH_38_SECURE                       0x0
+#define SCRATCH_SCRATCH_38_DUAL                         0x0
+#define SCRATCH_SCRATCH_38_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_38_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_38_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_38_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_38_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_38_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_38_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_38_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_38_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_38_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_38_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_38_DATA_SHIFT)
+#define SCRATCH_SCRATCH_38_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_38_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_38_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_38_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_38_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_38_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_38_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_38_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_38_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_38_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_39
+#define SCRATCH_SCRATCH_39                      MK_ADDR_CONST(0x478)
+#define SCRATCH_SCRATCH_39_SECURE                       0x0
+#define SCRATCH_SCRATCH_39_DUAL                         0x0
+#define SCRATCH_SCRATCH_39_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_39_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_39_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_39_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_39_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_39_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_39_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_39_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_39_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_39_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_39_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_39_DATA_SHIFT)
+#define SCRATCH_SCRATCH_39_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_39_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_39_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_39_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_39_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_39_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_39_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_39_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_39_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_39_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_40
+#define SCRATCH_SCRATCH_40                      MK_ADDR_CONST(0x47c)
+#define SCRATCH_SCRATCH_40_SECURE                       0x0
+#define SCRATCH_SCRATCH_40_DUAL                         0x0
+#define SCRATCH_SCRATCH_40_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_40_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_40_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_40_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_40_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_40_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_40_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_40_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_40_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_40_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_40_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_40_DATA_SHIFT)
+#define SCRATCH_SCRATCH_40_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_40_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_40_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_40_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_40_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_40_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_40_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_40_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_40_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_40_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_41
+#define SCRATCH_SCRATCH_41                      MK_ADDR_CONST(0x480)
+#define SCRATCH_SCRATCH_41_SECURE                       0x0
+#define SCRATCH_SCRATCH_41_DUAL                         0x0
+#define SCRATCH_SCRATCH_41_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_41_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_41_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_41_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_41_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_41_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_41_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_41_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_41_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_41_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_41_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_41_DATA_SHIFT)
+#define SCRATCH_SCRATCH_41_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_41_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_41_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_41_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_41_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_41_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_41_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_41_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_41_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_41_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_42
+#define SCRATCH_SCRATCH_42                      MK_ADDR_CONST(0x484)
+#define SCRATCH_SCRATCH_42_SECURE                       0x0
+#define SCRATCH_SCRATCH_42_DUAL                         0x0
+#define SCRATCH_SCRATCH_42_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_42_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_42_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_42_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_42_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_42_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_42_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_42_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_42_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_42_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_42_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_42_DATA_SHIFT)
+#define SCRATCH_SCRATCH_42_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_42_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_42_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_42_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_42_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_42_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_42_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_42_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_42_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_42_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_43
+#define SCRATCH_SCRATCH_43                      MK_ADDR_CONST(0x488)
+#define SCRATCH_SCRATCH_43_SECURE                       0x0
+#define SCRATCH_SCRATCH_43_DUAL                         0x0
+#define SCRATCH_SCRATCH_43_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_43_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_43_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_43_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_43_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_43_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_43_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_43_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_43_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_43_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_43_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_43_DATA_SHIFT)
+#define SCRATCH_SCRATCH_43_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_43_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_43_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_43_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_43_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_43_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_43_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_43_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_43_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_43_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_44
+#define SCRATCH_SCRATCH_44                      MK_ADDR_CONST(0x48c)
+#define SCRATCH_SCRATCH_44_SECURE                       0x0
+#define SCRATCH_SCRATCH_44_DUAL                         0x0
+#define SCRATCH_SCRATCH_44_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_44_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_44_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_44_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_44_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_44_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_44_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_44_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_44_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_44_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_44_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_44_DATA_SHIFT)
+#define SCRATCH_SCRATCH_44_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_44_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_44_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_44_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_44_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_44_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_44_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_44_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_44_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_44_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_45
+#define SCRATCH_SCRATCH_45                      MK_ADDR_CONST(0x490)
+#define SCRATCH_SCRATCH_45_SECURE                       0x0
+#define SCRATCH_SCRATCH_45_DUAL                         0x0
+#define SCRATCH_SCRATCH_45_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_45_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_45_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_45_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_45_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_45_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_45_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_45_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_45_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_45_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_45_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_45_DATA_SHIFT)
+#define SCRATCH_SCRATCH_45_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_45_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_45_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_45_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_45_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_45_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_45_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_45_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_45_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_45_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_46
+#define SCRATCH_SCRATCH_46                      MK_ADDR_CONST(0x494)
+#define SCRATCH_SCRATCH_46_SECURE                       0x0
+#define SCRATCH_SCRATCH_46_DUAL                         0x0
+#define SCRATCH_SCRATCH_46_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_46_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_46_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_46_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_46_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_46_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_46_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_46_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_46_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_46_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_46_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_46_DATA_SHIFT)
+#define SCRATCH_SCRATCH_46_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_46_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_46_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_46_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_46_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_46_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_46_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_46_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_46_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_46_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_47
+#define SCRATCH_SCRATCH_47                      MK_ADDR_CONST(0x498)
+#define SCRATCH_SCRATCH_47_SECURE                       0x0
+#define SCRATCH_SCRATCH_47_DUAL                         0x0
+#define SCRATCH_SCRATCH_47_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_47_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_47_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_47_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_47_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_47_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_47_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_47_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_47_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_47_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_47_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_47_DATA_SHIFT)
+#define SCRATCH_SCRATCH_47_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_47_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_47_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_47_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_47_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_47_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_47_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_47_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_47_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_47_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_48
+#define SCRATCH_SCRATCH_48                      MK_ADDR_CONST(0x49c)
+#define SCRATCH_SCRATCH_48_SECURE                       0x0
+#define SCRATCH_SCRATCH_48_DUAL                         0x0
+#define SCRATCH_SCRATCH_48_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_48_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_48_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_48_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_48_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_48_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_48_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_48_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_48_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_48_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_48_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_48_DATA_SHIFT)
+#define SCRATCH_SCRATCH_48_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_48_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_48_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_48_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_48_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_48_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_48_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_48_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_48_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_48_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_49
+#define SCRATCH_SCRATCH_49                      MK_ADDR_CONST(0x4a0)
+#define SCRATCH_SCRATCH_49_SECURE                       0x0
+#define SCRATCH_SCRATCH_49_DUAL                         0x0
+#define SCRATCH_SCRATCH_49_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_49_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_49_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_49_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_49_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_49_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_49_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_49_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_49_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_49_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_49_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_49_DATA_SHIFT)
+#define SCRATCH_SCRATCH_49_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_49_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_49_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_49_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_49_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_49_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_49_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_49_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_49_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_49_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_50
+#define SCRATCH_SCRATCH_50                      MK_ADDR_CONST(0x4a4)
+#define SCRATCH_SCRATCH_50_SECURE                       0x0
+#define SCRATCH_SCRATCH_50_DUAL                         0x0
+#define SCRATCH_SCRATCH_50_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_50_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_50_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_50_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_50_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_50_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_50_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_50_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_50_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_50_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_50_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_50_DATA_SHIFT)
+#define SCRATCH_SCRATCH_50_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_50_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_50_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_50_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_50_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_50_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_50_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_50_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_50_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_50_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_51
+#define SCRATCH_SCRATCH_51                      MK_ADDR_CONST(0x4a8)
+#define SCRATCH_SCRATCH_51_SECURE                       0x0
+#define SCRATCH_SCRATCH_51_DUAL                         0x0
+#define SCRATCH_SCRATCH_51_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_51_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_51_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_51_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_51_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_51_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_51_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_51_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_51_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_51_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_51_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_51_DATA_SHIFT)
+#define SCRATCH_SCRATCH_51_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_51_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_51_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_51_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_51_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_51_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_51_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_51_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_51_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_51_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_52
+#define SCRATCH_SCRATCH_52                      MK_ADDR_CONST(0x4ac)
+#define SCRATCH_SCRATCH_52_SECURE                       0x0
+#define SCRATCH_SCRATCH_52_DUAL                         0x0
+#define SCRATCH_SCRATCH_52_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_52_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_52_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_52_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_52_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_52_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_52_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_52_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_52_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_52_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_52_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_52_DATA_SHIFT)
+#define SCRATCH_SCRATCH_52_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_52_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_52_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_52_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_52_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_52_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_52_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_52_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_52_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_52_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_53
+#define SCRATCH_SCRATCH_53                      MK_ADDR_CONST(0x4b0)
+#define SCRATCH_SCRATCH_53_SECURE                       0x0
+#define SCRATCH_SCRATCH_53_DUAL                         0x0
+#define SCRATCH_SCRATCH_53_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_53_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_53_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_53_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_53_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_53_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_53_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_53_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_53_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_53_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_53_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_53_DATA_SHIFT)
+#define SCRATCH_SCRATCH_53_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_53_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_53_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_53_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_53_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_53_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_53_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_53_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_53_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_53_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_54
+#define SCRATCH_SCRATCH_54                      MK_ADDR_CONST(0x4b4)
+#define SCRATCH_SCRATCH_54_SECURE                       0x0
+#define SCRATCH_SCRATCH_54_DUAL                         0x0
+#define SCRATCH_SCRATCH_54_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_54_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_54_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_54_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_54_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_54_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_54_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_54_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_54_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_54_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_54_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_54_DATA_SHIFT)
+#define SCRATCH_SCRATCH_54_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_54_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_54_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_54_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_54_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_54_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_54_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_54_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_54_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_54_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_55
+#define SCRATCH_SCRATCH_55                      MK_ADDR_CONST(0x4b8)
+#define SCRATCH_SCRATCH_55_SECURE                       0x0
+#define SCRATCH_SCRATCH_55_DUAL                         0x0
+#define SCRATCH_SCRATCH_55_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_55_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_55_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_55_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_55_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_55_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_55_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_55_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_55_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_55_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_55_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_55_DATA_SHIFT)
+#define SCRATCH_SCRATCH_55_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_55_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_55_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_55_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_55_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_55_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_55_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_55_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_55_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_55_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_56
+#define SCRATCH_SCRATCH_56                      MK_ADDR_CONST(0x4bc)
+#define SCRATCH_SCRATCH_56_SECURE                       0x0
+#define SCRATCH_SCRATCH_56_DUAL                         0x0
+#define SCRATCH_SCRATCH_56_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_56_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_56_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_56_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_56_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_56_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_56_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_56_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_56_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_56_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_56_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_56_DATA_SHIFT)
+#define SCRATCH_SCRATCH_56_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_56_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_56_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_56_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_56_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_56_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_56_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_56_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_56_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_56_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_57
+#define SCRATCH_SCRATCH_57                      MK_ADDR_CONST(0x4c0)
+#define SCRATCH_SCRATCH_57_SECURE                       0x0
+#define SCRATCH_SCRATCH_57_DUAL                         0x0
+#define SCRATCH_SCRATCH_57_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_57_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_57_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_57_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_57_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_57_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_57_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_57_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_57_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_57_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_57_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_57_DATA_SHIFT)
+#define SCRATCH_SCRATCH_57_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_57_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_57_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_57_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_57_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_57_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_57_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_57_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_57_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_57_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_58
+#define SCRATCH_SCRATCH_58                      MK_ADDR_CONST(0x4c4)
+#define SCRATCH_SCRATCH_58_SECURE                       0x0
+#define SCRATCH_SCRATCH_58_DUAL                         0x0
+#define SCRATCH_SCRATCH_58_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_58_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_58_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_58_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_58_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_58_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_58_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_58_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_58_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_58_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_58_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_58_DATA_SHIFT)
+#define SCRATCH_SCRATCH_58_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_58_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_58_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_58_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_58_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_58_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_58_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_58_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_58_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_58_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_59
+#define SCRATCH_SCRATCH_59                      MK_ADDR_CONST(0x4c8)
+#define SCRATCH_SCRATCH_59_SECURE                       0x0
+#define SCRATCH_SCRATCH_59_DUAL                         0x0
+#define SCRATCH_SCRATCH_59_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_59_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_59_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_59_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_59_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_59_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_59_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_59_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_59_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_59_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_59_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_59_DATA_SHIFT)
+#define SCRATCH_SCRATCH_59_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_59_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_59_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_59_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_59_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_59_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_59_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_59_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_59_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_59_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_60
+#define SCRATCH_SCRATCH_60                      MK_ADDR_CONST(0x4cc)
+#define SCRATCH_SCRATCH_60_SECURE                       0x0
+#define SCRATCH_SCRATCH_60_DUAL                         0x0
+#define SCRATCH_SCRATCH_60_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_60_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_60_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_60_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_60_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_60_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_60_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_60_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_60_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_60_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_60_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_60_DATA_SHIFT)
+#define SCRATCH_SCRATCH_60_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_60_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_60_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_60_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_60_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_60_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_60_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_60_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_60_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_60_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_61
+#define SCRATCH_SCRATCH_61                      MK_ADDR_CONST(0x4d0)
+#define SCRATCH_SCRATCH_61_SECURE                       0x0
+#define SCRATCH_SCRATCH_61_DUAL                         0x0
+#define SCRATCH_SCRATCH_61_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_61_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_61_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_61_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_61_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_61_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_61_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_61_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_61_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_61_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_61_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_61_DATA_SHIFT)
+#define SCRATCH_SCRATCH_61_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_61_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_61_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_61_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_61_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_61_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_61_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_61_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_61_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_61_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_62
+#define SCRATCH_SCRATCH_62                      MK_ADDR_CONST(0x4d4)
+#define SCRATCH_SCRATCH_62_SECURE                       0x0
+#define SCRATCH_SCRATCH_62_DUAL                         0x0
+#define SCRATCH_SCRATCH_62_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_62_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_62_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_62_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_62_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_62_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_62_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_62_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_62_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_62_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_62_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_62_DATA_SHIFT)
+#define SCRATCH_SCRATCH_62_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_62_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_62_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_62_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_62_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_62_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_62_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_62_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_62_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_62_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_63
+#define SCRATCH_SCRATCH_63                      MK_ADDR_CONST(0x4d8)
+#define SCRATCH_SCRATCH_63_SECURE                       0x0
+#define SCRATCH_SCRATCH_63_DUAL                         0x0
+#define SCRATCH_SCRATCH_63_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_63_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_63_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_63_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_63_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_63_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_63_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_63_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_63_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_63_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_63_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_63_DATA_SHIFT)
+#define SCRATCH_SCRATCH_63_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_63_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_63_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_63_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_63_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_63_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_63_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_63_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_63_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_63_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_64
+#define SCRATCH_SCRATCH_64                      MK_ADDR_CONST(0x4dc)
+#define SCRATCH_SCRATCH_64_SECURE                       0x0
+#define SCRATCH_SCRATCH_64_DUAL                         0x0
+#define SCRATCH_SCRATCH_64_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_64_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_64_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_64_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_64_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_64_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_64_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_64_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_64_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_64_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_64_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_64_DATA_SHIFT)
+#define SCRATCH_SCRATCH_64_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_64_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_64_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_64_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_64_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_64_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_64_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_64_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_64_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_64_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_65
+#define SCRATCH_SCRATCH_65                      MK_ADDR_CONST(0x4e0)
+#define SCRATCH_SCRATCH_65_SECURE                       0x0
+#define SCRATCH_SCRATCH_65_DUAL                         0x0
+#define SCRATCH_SCRATCH_65_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_65_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_65_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_65_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_65_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_65_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_65_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_65_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_65_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_65_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_65_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_65_DATA_SHIFT)
+#define SCRATCH_SCRATCH_65_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_65_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_65_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_65_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_65_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_65_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_65_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_65_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_65_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_65_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_66
+#define SCRATCH_SCRATCH_66                      MK_ADDR_CONST(0x4e4)
+#define SCRATCH_SCRATCH_66_SECURE                       0x0
+#define SCRATCH_SCRATCH_66_DUAL                         0x0
+#define SCRATCH_SCRATCH_66_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_66_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_66_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_66_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_66_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_66_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_66_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_66_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_66_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_66_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_66_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_66_DATA_SHIFT)
+#define SCRATCH_SCRATCH_66_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_66_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_66_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_66_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_66_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_66_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_66_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_66_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_66_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_66_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_67
+#define SCRATCH_SCRATCH_67                      MK_ADDR_CONST(0x4e8)
+#define SCRATCH_SCRATCH_67_SECURE                       0x0
+#define SCRATCH_SCRATCH_67_DUAL                         0x0
+#define SCRATCH_SCRATCH_67_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_67_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_67_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_67_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_67_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_67_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_67_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_67_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_67_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_67_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_67_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_67_DATA_SHIFT)
+#define SCRATCH_SCRATCH_67_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_67_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_67_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_67_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_67_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_67_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_67_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_67_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_67_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_67_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_68
+#define SCRATCH_SCRATCH_68                      MK_ADDR_CONST(0x4ec)
+#define SCRATCH_SCRATCH_68_SECURE                       0x0
+#define SCRATCH_SCRATCH_68_DUAL                         0x0
+#define SCRATCH_SCRATCH_68_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_68_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_68_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_68_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_68_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_68_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_68_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_68_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_68_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_68_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_68_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_68_DATA_SHIFT)
+#define SCRATCH_SCRATCH_68_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_68_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_68_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_68_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_68_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_68_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_68_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_68_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_68_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_68_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_69
+#define SCRATCH_SCRATCH_69                      MK_ADDR_CONST(0x4f0)
+#define SCRATCH_SCRATCH_69_SECURE                       0x0
+#define SCRATCH_SCRATCH_69_DUAL                         0x0
+#define SCRATCH_SCRATCH_69_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_69_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_69_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_69_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_69_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_69_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_69_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_69_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_69_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_69_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_69_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_69_DATA_SHIFT)
+#define SCRATCH_SCRATCH_69_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_69_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_69_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_69_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_69_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_69_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_69_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_69_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_69_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_69_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_70
+#define SCRATCH_SCRATCH_70                      MK_ADDR_CONST(0x4f4)
+#define SCRATCH_SCRATCH_70_SECURE                       0x0
+#define SCRATCH_SCRATCH_70_DUAL                         0x0
+#define SCRATCH_SCRATCH_70_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_70_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_70_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_70_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_70_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_70_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_70_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_70_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_70_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_70_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_70_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_70_DATA_SHIFT)
+#define SCRATCH_SCRATCH_70_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_70_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_70_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_70_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_70_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_70_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_70_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_70_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_70_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_70_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_71
+#define SCRATCH_SCRATCH_71                      MK_ADDR_CONST(0x4f8)
+#define SCRATCH_SCRATCH_71_SECURE                       0x0
+#define SCRATCH_SCRATCH_71_DUAL                         0x0
+#define SCRATCH_SCRATCH_71_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_71_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_71_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_71_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_71_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_71_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_71_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_71_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_71_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_71_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_71_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_71_DATA_SHIFT)
+#define SCRATCH_SCRATCH_71_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_71_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_71_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_71_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_71_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_71_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_71_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_71_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_71_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_71_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_72
+#define SCRATCH_SCRATCH_72                      MK_ADDR_CONST(0x4fc)
+#define SCRATCH_SCRATCH_72_SECURE                       0x0
+#define SCRATCH_SCRATCH_72_DUAL                         0x0
+#define SCRATCH_SCRATCH_72_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_72_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_72_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_72_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_72_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_72_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_72_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_72_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_72_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_72_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_72_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_72_DATA_SHIFT)
+#define SCRATCH_SCRATCH_72_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_72_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_72_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_72_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_72_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_72_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_72_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_72_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_72_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_72_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_73
+#define SCRATCH_SCRATCH_73                      MK_ADDR_CONST(0x500)
+#define SCRATCH_SCRATCH_73_SECURE                       0x0
+#define SCRATCH_SCRATCH_73_DUAL                         0x0
+#define SCRATCH_SCRATCH_73_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_73_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_73_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_73_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_73_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_73_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_73_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_73_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_73_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_73_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_73_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_73_DATA_SHIFT)
+#define SCRATCH_SCRATCH_73_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_73_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_73_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_73_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_73_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_73_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_73_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_73_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_73_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_73_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_74
+#define SCRATCH_SCRATCH_74                      MK_ADDR_CONST(0x504)
+#define SCRATCH_SCRATCH_74_SECURE                       0x0
+#define SCRATCH_SCRATCH_74_DUAL                         0x0
+#define SCRATCH_SCRATCH_74_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_74_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_74_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_74_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_74_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_74_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_74_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_74_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_74_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_74_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_74_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_74_DATA_SHIFT)
+#define SCRATCH_SCRATCH_74_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_74_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_74_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_74_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_74_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_74_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_74_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_74_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_74_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_74_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_75
+#define SCRATCH_SCRATCH_75                      MK_ADDR_CONST(0x508)
+#define SCRATCH_SCRATCH_75_SECURE                       0x0
+#define SCRATCH_SCRATCH_75_DUAL                         0x0
+#define SCRATCH_SCRATCH_75_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_75_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_75_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_75_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_75_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_75_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_75_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_75_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_75_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_75_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_75_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_75_DATA_SHIFT)
+#define SCRATCH_SCRATCH_75_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_75_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_75_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_75_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_75_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_75_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_75_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_75_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_75_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_75_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_76
+#define SCRATCH_SCRATCH_76                      MK_ADDR_CONST(0x50c)
+#define SCRATCH_SCRATCH_76_SECURE                       0x0
+#define SCRATCH_SCRATCH_76_DUAL                         0x0
+#define SCRATCH_SCRATCH_76_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_76_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_76_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_76_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_76_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_76_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_76_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_76_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_76_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_76_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_76_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_76_DATA_SHIFT)
+#define SCRATCH_SCRATCH_76_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_76_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_76_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_76_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_76_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_76_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_76_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_76_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_76_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_76_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_77
+#define SCRATCH_SCRATCH_77                      MK_ADDR_CONST(0x510)
+#define SCRATCH_SCRATCH_77_SECURE                       0x0
+#define SCRATCH_SCRATCH_77_DUAL                         0x0
+#define SCRATCH_SCRATCH_77_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_77_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_77_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_77_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_77_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_77_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_77_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_77_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_77_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_77_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_77_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_77_DATA_SHIFT)
+#define SCRATCH_SCRATCH_77_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_77_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_77_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_77_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_77_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_77_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_77_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_77_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_77_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_77_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_78
+#define SCRATCH_SCRATCH_78                      MK_ADDR_CONST(0x514)
+#define SCRATCH_SCRATCH_78_SECURE                       0x0
+#define SCRATCH_SCRATCH_78_DUAL                         0x0
+#define SCRATCH_SCRATCH_78_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_78_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_78_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_78_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_78_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_78_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_78_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_78_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_78_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_78_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_78_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_78_DATA_SHIFT)
+#define SCRATCH_SCRATCH_78_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_78_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_78_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_78_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_78_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_78_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_78_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_78_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_78_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_78_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_79
+#define SCRATCH_SCRATCH_79                      MK_ADDR_CONST(0x518)
+#define SCRATCH_SCRATCH_79_SECURE                       0x0
+#define SCRATCH_SCRATCH_79_DUAL                         0x0
+#define SCRATCH_SCRATCH_79_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_79_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_79_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_79_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_79_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_79_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_79_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_79_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_79_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_79_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_79_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_79_DATA_SHIFT)
+#define SCRATCH_SCRATCH_79_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_79_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_79_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_79_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_79_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_79_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_79_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_79_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_79_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_79_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_80
+#define SCRATCH_SCRATCH_80                      MK_ADDR_CONST(0x51c)
+#define SCRATCH_SCRATCH_80_SECURE                       0x0
+#define SCRATCH_SCRATCH_80_DUAL                         0x0
+#define SCRATCH_SCRATCH_80_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_80_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_80_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_80_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_80_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_80_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_80_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_80_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_80_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_80_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_80_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_80_DATA_SHIFT)
+#define SCRATCH_SCRATCH_80_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_80_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_80_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_80_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_80_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_80_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_80_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_80_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_80_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_80_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_81
+#define SCRATCH_SCRATCH_81                      MK_ADDR_CONST(0x520)
+#define SCRATCH_SCRATCH_81_SECURE                       0x0
+#define SCRATCH_SCRATCH_81_DUAL                         0x0
+#define SCRATCH_SCRATCH_81_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_81_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_81_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_81_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_81_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_81_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_81_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_81_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_81_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_81_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_81_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_81_DATA_SHIFT)
+#define SCRATCH_SCRATCH_81_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_81_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_81_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_81_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_81_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_81_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_81_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_81_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_81_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_81_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_82
+#define SCRATCH_SCRATCH_82                      MK_ADDR_CONST(0x524)
+#define SCRATCH_SCRATCH_82_SECURE                       0x0
+#define SCRATCH_SCRATCH_82_DUAL                         0x0
+#define SCRATCH_SCRATCH_82_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_82_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_82_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_82_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_82_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_82_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_82_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_82_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_82_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_82_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_82_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_82_DATA_SHIFT)
+#define SCRATCH_SCRATCH_82_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_82_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_82_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_82_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_82_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_82_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_82_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_82_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_82_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_82_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_83
+#define SCRATCH_SCRATCH_83                      MK_ADDR_CONST(0x528)
+#define SCRATCH_SCRATCH_83_SECURE                       0x0
+#define SCRATCH_SCRATCH_83_DUAL                         0x0
+#define SCRATCH_SCRATCH_83_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_83_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_83_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_83_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_83_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_83_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_83_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_83_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_83_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_83_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_83_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_83_DATA_SHIFT)
+#define SCRATCH_SCRATCH_83_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_83_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_83_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_83_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_83_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_83_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_83_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_83_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_83_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_83_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_84
+#define SCRATCH_SCRATCH_84                      MK_ADDR_CONST(0x52c)
+#define SCRATCH_SCRATCH_84_SECURE                       0x0
+#define SCRATCH_SCRATCH_84_DUAL                         0x0
+#define SCRATCH_SCRATCH_84_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_84_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_84_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_84_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_84_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_84_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_84_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_84_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_84_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_84_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_84_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_84_DATA_SHIFT)
+#define SCRATCH_SCRATCH_84_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_84_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_84_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_84_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_84_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_84_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_84_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_84_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_84_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_84_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_85
+#define SCRATCH_SCRATCH_85                      MK_ADDR_CONST(0x530)
+#define SCRATCH_SCRATCH_85_SECURE                       0x0
+#define SCRATCH_SCRATCH_85_DUAL                         0x0
+#define SCRATCH_SCRATCH_85_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_85_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_85_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_85_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_85_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_85_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_85_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_85_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_85_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_85_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_85_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_85_DATA_SHIFT)
+#define SCRATCH_SCRATCH_85_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_85_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_85_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_85_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_85_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_85_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_85_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_85_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_85_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_85_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_86
+#define SCRATCH_SCRATCH_86                      MK_ADDR_CONST(0x534)
+#define SCRATCH_SCRATCH_86_SECURE                       0x0
+#define SCRATCH_SCRATCH_86_DUAL                         0x0
+#define SCRATCH_SCRATCH_86_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_86_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_86_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_86_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_86_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_86_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_86_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_86_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_86_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_86_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_86_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_86_DATA_SHIFT)
+#define SCRATCH_SCRATCH_86_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_86_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_86_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_86_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_86_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_86_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_86_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_86_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_86_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_86_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_87
+#define SCRATCH_SCRATCH_87                      MK_ADDR_CONST(0x538)
+#define SCRATCH_SCRATCH_87_SECURE                       0x0
+#define SCRATCH_SCRATCH_87_DUAL                         0x0
+#define SCRATCH_SCRATCH_87_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_87_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_87_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_87_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_87_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_87_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_87_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_87_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_87_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_87_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_87_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_87_DATA_SHIFT)
+#define SCRATCH_SCRATCH_87_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_87_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_87_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_87_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_87_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_87_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_87_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_87_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_87_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_87_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_88
+#define SCRATCH_SCRATCH_88                      MK_ADDR_CONST(0x53c)
+#define SCRATCH_SCRATCH_88_SECURE                       0x0
+#define SCRATCH_SCRATCH_88_DUAL                         0x0
+#define SCRATCH_SCRATCH_88_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_88_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_88_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_88_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_88_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_88_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_88_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_88_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_88_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_88_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_88_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_88_DATA_SHIFT)
+#define SCRATCH_SCRATCH_88_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_88_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_88_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_88_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_88_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_88_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_88_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_88_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_88_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_88_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_89
+#define SCRATCH_SCRATCH_89                      MK_ADDR_CONST(0x540)
+#define SCRATCH_SCRATCH_89_SECURE                       0x0
+#define SCRATCH_SCRATCH_89_DUAL                         0x0
+#define SCRATCH_SCRATCH_89_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_89_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_89_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_89_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_89_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_89_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_89_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_89_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_89_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_89_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_89_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_89_DATA_SHIFT)
+#define SCRATCH_SCRATCH_89_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_89_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_89_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_89_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_89_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_89_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_89_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_89_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_89_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_89_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_90
+#define SCRATCH_SCRATCH_90                      MK_ADDR_CONST(0x544)
+#define SCRATCH_SCRATCH_90_SECURE                       0x0
+#define SCRATCH_SCRATCH_90_DUAL                         0x0
+#define SCRATCH_SCRATCH_90_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_90_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_90_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_90_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_90_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_90_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_90_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_90_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_90_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_90_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_90_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_90_DATA_SHIFT)
+#define SCRATCH_SCRATCH_90_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_90_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_90_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_90_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_90_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_90_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_90_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_90_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_90_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_90_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_91
+#define SCRATCH_SCRATCH_91                      MK_ADDR_CONST(0x548)
+#define SCRATCH_SCRATCH_91_SECURE                       0x0
+#define SCRATCH_SCRATCH_91_DUAL                         0x0
+#define SCRATCH_SCRATCH_91_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_91_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_91_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_91_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_91_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_91_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_91_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_91_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_91_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_91_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_91_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_91_DATA_SHIFT)
+#define SCRATCH_SCRATCH_91_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_91_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_91_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_91_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_91_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_91_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_91_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_91_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_91_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_91_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_92
+#define SCRATCH_SCRATCH_92                      MK_ADDR_CONST(0x54c)
+#define SCRATCH_SCRATCH_92_SECURE                       0x0
+#define SCRATCH_SCRATCH_92_DUAL                         0x0
+#define SCRATCH_SCRATCH_92_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_92_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_92_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_92_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_92_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_92_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_92_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_92_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_92_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_92_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_92_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_92_DATA_SHIFT)
+#define SCRATCH_SCRATCH_92_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_92_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_92_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_92_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_92_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_92_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_92_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_92_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_92_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_92_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_93
+#define SCRATCH_SCRATCH_93                      MK_ADDR_CONST(0x550)
+#define SCRATCH_SCRATCH_93_SECURE                       0x0
+#define SCRATCH_SCRATCH_93_DUAL                         0x0
+#define SCRATCH_SCRATCH_93_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_93_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_93_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_93_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_93_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_93_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_93_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_93_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_93_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_93_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_93_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_93_DATA_SHIFT)
+#define SCRATCH_SCRATCH_93_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_93_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_93_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_93_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_93_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_93_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_93_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_93_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_93_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_93_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_94
+#define SCRATCH_SCRATCH_94                      MK_ADDR_CONST(0x554)
+#define SCRATCH_SCRATCH_94_SECURE                       0x0
+#define SCRATCH_SCRATCH_94_DUAL                         0x0
+#define SCRATCH_SCRATCH_94_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_94_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_94_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_94_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_94_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_94_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_94_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_94_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_94_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_94_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_94_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_94_DATA_SHIFT)
+#define SCRATCH_SCRATCH_94_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_94_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_94_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_94_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_94_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_94_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_94_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_94_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_94_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_94_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_95
+#define SCRATCH_SCRATCH_95                      MK_ADDR_CONST(0x558)
+#define SCRATCH_SCRATCH_95_SECURE                       0x0
+#define SCRATCH_SCRATCH_95_DUAL                         0x0
+#define SCRATCH_SCRATCH_95_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_95_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_95_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_95_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_95_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_95_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_95_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_95_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_95_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_95_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_95_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_95_DATA_SHIFT)
+#define SCRATCH_SCRATCH_95_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_95_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_95_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_95_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_95_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_95_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_95_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_95_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_95_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_95_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_96
+#define SCRATCH_SCRATCH_96                      MK_ADDR_CONST(0x55c)
+#define SCRATCH_SCRATCH_96_SECURE                       0x0
+#define SCRATCH_SCRATCH_96_DUAL                         0x0
+#define SCRATCH_SCRATCH_96_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_96_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_96_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_96_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_96_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_96_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_96_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_96_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_96_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_96_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_96_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_96_DATA_SHIFT)
+#define SCRATCH_SCRATCH_96_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_96_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_96_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_96_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_96_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_96_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_96_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_96_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_96_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_96_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_97
+#define SCRATCH_SCRATCH_97                      MK_ADDR_CONST(0x560)
+#define SCRATCH_SCRATCH_97_SECURE                       0x0
+#define SCRATCH_SCRATCH_97_DUAL                         0x0
+#define SCRATCH_SCRATCH_97_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_97_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_97_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_97_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_97_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_97_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_97_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_97_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_97_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_97_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_97_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_97_DATA_SHIFT)
+#define SCRATCH_SCRATCH_97_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_97_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_97_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_97_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_97_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_97_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_97_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_97_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_97_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_97_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_98
+#define SCRATCH_SCRATCH_98                      MK_ADDR_CONST(0x564)
+#define SCRATCH_SCRATCH_98_SECURE                       0x0
+#define SCRATCH_SCRATCH_98_DUAL                         0x0
+#define SCRATCH_SCRATCH_98_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_98_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_98_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_98_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_98_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_98_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_98_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_98_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_98_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_98_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_98_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_98_DATA_SHIFT)
+#define SCRATCH_SCRATCH_98_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_98_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_98_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_98_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_98_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_98_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_98_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_98_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_98_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_98_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_99
+#define SCRATCH_SCRATCH_99                      MK_ADDR_CONST(0x568)
+#define SCRATCH_SCRATCH_99_SECURE                       0x0
+#define SCRATCH_SCRATCH_99_DUAL                         0x0
+#define SCRATCH_SCRATCH_99_SCR                  NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_99_SCRREG                       SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_99_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH_99_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_99_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_99_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_99_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_99_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_99_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_99_DATA_SHIFT                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_99_DATA_FIELD                   MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_99_DATA_SHIFT)
+#define SCRATCH_SCRATCH_99_DATA_RANGE                   31:0
+#define SCRATCH_SCRATCH_99_DATA_MSB                     MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_99_DATA_LSB                     MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_99_DATA_WOFFSET                 0x0
+#define SCRATCH_SCRATCH_99_DATA_DEFAULT                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_99_DATA_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_99_DATA_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_99_DATA_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_99_DATA_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_99_DATA_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_100
+#define SCRATCH_SCRATCH_100                     MK_ADDR_CONST(0x56c)
+#define SCRATCH_SCRATCH_100_SECURE                      0x0
+#define SCRATCH_SCRATCH_100_DUAL                        0x0
+#define SCRATCH_SCRATCH_100_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_100_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_100_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_100_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_100_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_100_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_100_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_100_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_100_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_100_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_100_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_100_DATA_SHIFT)
+#define SCRATCH_SCRATCH_100_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_100_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_100_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_100_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_100_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_100_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_100_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_100_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_100_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_100_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_101
+#define SCRATCH_SCRATCH_101                     MK_ADDR_CONST(0x570)
+#define SCRATCH_SCRATCH_101_SECURE                      0x0
+#define SCRATCH_SCRATCH_101_DUAL                        0x0
+#define SCRATCH_SCRATCH_101_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_101_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_101_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_101_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_101_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_101_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_101_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_101_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_101_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_101_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_101_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_101_DATA_SHIFT)
+#define SCRATCH_SCRATCH_101_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_101_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_101_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_101_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_101_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_101_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_101_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_101_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_101_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_101_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_102
+#define SCRATCH_SCRATCH_102                     MK_ADDR_CONST(0x574)
+#define SCRATCH_SCRATCH_102_SECURE                      0x0
+#define SCRATCH_SCRATCH_102_DUAL                        0x0
+#define SCRATCH_SCRATCH_102_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_102_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_102_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_102_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_102_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_102_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_102_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_102_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_102_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_102_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_102_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_102_DATA_SHIFT)
+#define SCRATCH_SCRATCH_102_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_102_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_102_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_102_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_102_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_102_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_102_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_102_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_102_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_102_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_103
+#define SCRATCH_SCRATCH_103                     MK_ADDR_CONST(0x578)
+#define SCRATCH_SCRATCH_103_SECURE                      0x0
+#define SCRATCH_SCRATCH_103_DUAL                        0x0
+#define SCRATCH_SCRATCH_103_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_103_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_103_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_103_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_103_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_103_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_103_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_103_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_103_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_103_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_103_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_103_DATA_SHIFT)
+#define SCRATCH_SCRATCH_103_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_103_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_103_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_103_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_103_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_103_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_103_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_103_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_103_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_103_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_104
+#define SCRATCH_SCRATCH_104                     MK_ADDR_CONST(0x57c)
+#define SCRATCH_SCRATCH_104_SECURE                      0x0
+#define SCRATCH_SCRATCH_104_DUAL                        0x0
+#define SCRATCH_SCRATCH_104_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_104_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_104_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_104_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_104_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_104_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_104_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_104_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_104_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_104_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_104_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_104_DATA_SHIFT)
+#define SCRATCH_SCRATCH_104_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_104_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_104_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_104_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_104_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_104_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_104_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_104_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_104_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_104_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_105
+#define SCRATCH_SCRATCH_105                     MK_ADDR_CONST(0x580)
+#define SCRATCH_SCRATCH_105_SECURE                      0x0
+#define SCRATCH_SCRATCH_105_DUAL                        0x0
+#define SCRATCH_SCRATCH_105_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_105_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_105_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_105_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_105_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_105_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_105_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_105_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_105_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_105_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_105_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_105_DATA_SHIFT)
+#define SCRATCH_SCRATCH_105_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_105_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_105_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_105_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_105_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_105_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_105_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_105_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_105_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_105_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_106
+#define SCRATCH_SCRATCH_106                     MK_ADDR_CONST(0x584)
+#define SCRATCH_SCRATCH_106_SECURE                      0x0
+#define SCRATCH_SCRATCH_106_DUAL                        0x0
+#define SCRATCH_SCRATCH_106_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_106_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_106_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_106_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_106_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_106_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_106_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_106_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_106_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_106_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_106_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_106_DATA_SHIFT)
+#define SCRATCH_SCRATCH_106_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_106_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_106_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_106_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_106_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_106_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_106_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_106_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_106_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_106_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_107
+#define SCRATCH_SCRATCH_107                     MK_ADDR_CONST(0x588)
+#define SCRATCH_SCRATCH_107_SECURE                      0x0
+#define SCRATCH_SCRATCH_107_DUAL                        0x0
+#define SCRATCH_SCRATCH_107_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_107_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_107_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_107_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_107_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_107_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_107_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_107_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_107_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_107_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_107_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_107_DATA_SHIFT)
+#define SCRATCH_SCRATCH_107_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_107_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_107_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_107_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_107_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_107_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_107_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_107_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_107_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_107_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_108
+#define SCRATCH_SCRATCH_108                     MK_ADDR_CONST(0x58c)
+#define SCRATCH_SCRATCH_108_SECURE                      0x0
+#define SCRATCH_SCRATCH_108_DUAL                        0x0
+#define SCRATCH_SCRATCH_108_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_108_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_108_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_108_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_108_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_108_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_108_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_108_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_108_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_108_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_108_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_108_DATA_SHIFT)
+#define SCRATCH_SCRATCH_108_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_108_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_108_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_108_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_108_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_108_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_108_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_108_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_108_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_108_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_109
+#define SCRATCH_SCRATCH_109                     MK_ADDR_CONST(0x590)
+#define SCRATCH_SCRATCH_109_SECURE                      0x0
+#define SCRATCH_SCRATCH_109_DUAL                        0x0
+#define SCRATCH_SCRATCH_109_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_109_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_109_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_109_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_109_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_109_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_109_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_109_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_109_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_109_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_109_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_109_DATA_SHIFT)
+#define SCRATCH_SCRATCH_109_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_109_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_109_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_109_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_109_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_109_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_109_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_109_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_109_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_109_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_110
+#define SCRATCH_SCRATCH_110                     MK_ADDR_CONST(0x594)
+#define SCRATCH_SCRATCH_110_SECURE                      0x0
+#define SCRATCH_SCRATCH_110_DUAL                        0x0
+#define SCRATCH_SCRATCH_110_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_110_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_110_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_110_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_110_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_110_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_110_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_110_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_110_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_110_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_110_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_110_DATA_SHIFT)
+#define SCRATCH_SCRATCH_110_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_110_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_110_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_110_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_110_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_110_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_110_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_110_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_110_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_110_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_111
+#define SCRATCH_SCRATCH_111                     MK_ADDR_CONST(0x598)
+#define SCRATCH_SCRATCH_111_SECURE                      0x0
+#define SCRATCH_SCRATCH_111_DUAL                        0x0
+#define SCRATCH_SCRATCH_111_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_111_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_111_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_111_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_111_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_111_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_111_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_111_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_111_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_111_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_111_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_111_DATA_SHIFT)
+#define SCRATCH_SCRATCH_111_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_111_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_111_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_111_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_111_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_111_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_111_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_111_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_111_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_111_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_112
+#define SCRATCH_SCRATCH_112                     MK_ADDR_CONST(0x59c)
+#define SCRATCH_SCRATCH_112_SECURE                      0x0
+#define SCRATCH_SCRATCH_112_DUAL                        0x0
+#define SCRATCH_SCRATCH_112_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_112_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_112_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_112_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_112_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_112_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_112_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_112_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_112_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_112_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_112_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_112_DATA_SHIFT)
+#define SCRATCH_SCRATCH_112_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_112_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_112_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_112_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_112_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_112_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_112_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_112_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_112_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_112_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_113
+#define SCRATCH_SCRATCH_113                     MK_ADDR_CONST(0x5a0)
+#define SCRATCH_SCRATCH_113_SECURE                      0x0
+#define SCRATCH_SCRATCH_113_DUAL                        0x0
+#define SCRATCH_SCRATCH_113_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_113_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_113_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_113_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_113_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_113_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_113_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_113_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_113_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_113_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_113_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_113_DATA_SHIFT)
+#define SCRATCH_SCRATCH_113_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_113_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_113_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_113_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_113_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_113_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_113_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_113_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_113_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_113_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_114
+#define SCRATCH_SCRATCH_114                     MK_ADDR_CONST(0x5a4)
+#define SCRATCH_SCRATCH_114_SECURE                      0x0
+#define SCRATCH_SCRATCH_114_DUAL                        0x0
+#define SCRATCH_SCRATCH_114_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_114_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_114_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_114_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_114_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_114_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_114_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_114_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_114_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_114_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_114_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_114_DATA_SHIFT)
+#define SCRATCH_SCRATCH_114_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_114_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_114_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_114_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_114_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_114_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_114_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_114_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_114_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_114_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_115
+#define SCRATCH_SCRATCH_115                     MK_ADDR_CONST(0x5a8)
+#define SCRATCH_SCRATCH_115_SECURE                      0x0
+#define SCRATCH_SCRATCH_115_DUAL                        0x0
+#define SCRATCH_SCRATCH_115_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_115_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_115_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_115_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_115_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_115_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_115_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_115_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_115_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_115_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_115_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_115_DATA_SHIFT)
+#define SCRATCH_SCRATCH_115_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_115_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_115_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_115_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_115_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_115_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_115_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_115_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_115_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_115_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_116
+#define SCRATCH_SCRATCH_116                     MK_ADDR_CONST(0x5ac)
+#define SCRATCH_SCRATCH_116_SECURE                      0x0
+#define SCRATCH_SCRATCH_116_DUAL                        0x0
+#define SCRATCH_SCRATCH_116_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_116_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_116_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_116_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_116_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_116_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_116_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_116_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_116_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_116_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_116_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_116_DATA_SHIFT)
+#define SCRATCH_SCRATCH_116_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_116_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_116_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_116_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_116_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_116_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_116_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_116_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_116_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_116_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_117
+#define SCRATCH_SCRATCH_117                     MK_ADDR_CONST(0x5b0)
+#define SCRATCH_SCRATCH_117_SECURE                      0x0
+#define SCRATCH_SCRATCH_117_DUAL                        0x0
+#define SCRATCH_SCRATCH_117_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_117_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_117_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_117_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_117_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_117_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_117_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_117_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_117_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_117_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_117_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_117_DATA_SHIFT)
+#define SCRATCH_SCRATCH_117_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_117_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_117_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_117_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_117_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_117_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_117_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_117_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_117_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_117_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_118
+#define SCRATCH_SCRATCH_118                     MK_ADDR_CONST(0x5b4)
+#define SCRATCH_SCRATCH_118_SECURE                      0x0
+#define SCRATCH_SCRATCH_118_DUAL                        0x0
+#define SCRATCH_SCRATCH_118_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_118_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_118_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_118_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_118_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_118_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_118_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_118_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_118_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_118_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_118_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_118_DATA_SHIFT)
+#define SCRATCH_SCRATCH_118_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_118_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_118_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_118_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_118_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_118_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_118_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_118_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_118_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_118_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_119
+#define SCRATCH_SCRATCH_119                     MK_ADDR_CONST(0x5b8)
+#define SCRATCH_SCRATCH_119_SECURE                      0x0
+#define SCRATCH_SCRATCH_119_DUAL                        0x0
+#define SCRATCH_SCRATCH_119_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_119_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_119_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_119_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_119_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_119_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_119_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_119_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_119_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_119_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_119_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_119_DATA_SHIFT)
+#define SCRATCH_SCRATCH_119_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_119_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_119_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_119_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_119_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_119_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_119_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_119_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_119_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_119_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_120
+#define SCRATCH_SCRATCH_120                     MK_ADDR_CONST(0x5bc)
+#define SCRATCH_SCRATCH_120_SECURE                      0x0
+#define SCRATCH_SCRATCH_120_DUAL                        0x0
+#define SCRATCH_SCRATCH_120_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_120_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_120_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_120_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_120_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_120_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_120_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_120_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_120_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_120_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_120_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_120_DATA_SHIFT)
+#define SCRATCH_SCRATCH_120_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_120_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_120_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_120_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_120_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_120_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_120_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_120_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_120_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_120_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_121
+#define SCRATCH_SCRATCH_121                     MK_ADDR_CONST(0x5c0)
+#define SCRATCH_SCRATCH_121_SECURE                      0x0
+#define SCRATCH_SCRATCH_121_DUAL                        0x0
+#define SCRATCH_SCRATCH_121_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_121_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_121_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_121_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_121_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_121_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_121_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_121_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_121_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_121_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_121_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_121_DATA_SHIFT)
+#define SCRATCH_SCRATCH_121_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_121_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_121_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_121_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_121_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_121_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_121_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_121_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_121_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_121_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_122
+#define SCRATCH_SCRATCH_122                     MK_ADDR_CONST(0x5c4)
+#define SCRATCH_SCRATCH_122_SECURE                      0x0
+#define SCRATCH_SCRATCH_122_DUAL                        0x0
+#define SCRATCH_SCRATCH_122_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_122_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_122_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_122_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_122_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_122_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_122_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_122_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_122_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_122_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_122_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_122_DATA_SHIFT)
+#define SCRATCH_SCRATCH_122_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_122_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_122_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_122_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_122_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_122_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_122_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_122_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_122_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_122_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_123
+#define SCRATCH_SCRATCH_123                     MK_ADDR_CONST(0x5c8)
+#define SCRATCH_SCRATCH_123_SECURE                      0x0
+#define SCRATCH_SCRATCH_123_DUAL                        0x0
+#define SCRATCH_SCRATCH_123_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_123_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_123_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_123_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_123_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_123_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_123_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_123_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_123_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_123_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_123_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_123_DATA_SHIFT)
+#define SCRATCH_SCRATCH_123_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_123_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_123_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_123_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_123_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_123_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_123_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_123_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_123_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_123_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_124
+#define SCRATCH_SCRATCH_124                     MK_ADDR_CONST(0x5cc)
+#define SCRATCH_SCRATCH_124_SECURE                      0x0
+#define SCRATCH_SCRATCH_124_DUAL                        0x0
+#define SCRATCH_SCRATCH_124_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_124_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_124_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_124_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_124_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_124_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_124_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_124_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_124_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_124_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_124_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_124_DATA_SHIFT)
+#define SCRATCH_SCRATCH_124_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_124_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_124_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_124_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_124_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_124_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_124_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_124_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_124_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_124_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_125
+#define SCRATCH_SCRATCH_125                     MK_ADDR_CONST(0x5d0)
+#define SCRATCH_SCRATCH_125_SECURE                      0x0
+#define SCRATCH_SCRATCH_125_DUAL                        0x0
+#define SCRATCH_SCRATCH_125_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_125_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_125_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_125_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_125_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_125_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_125_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_125_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_125_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_125_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_125_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_125_DATA_SHIFT)
+#define SCRATCH_SCRATCH_125_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_125_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_125_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_125_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_125_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_125_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_125_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_125_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_125_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_125_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_126
+#define SCRATCH_SCRATCH_126                     MK_ADDR_CONST(0x5d4)
+#define SCRATCH_SCRATCH_126_SECURE                      0x0
+#define SCRATCH_SCRATCH_126_DUAL                        0x0
+#define SCRATCH_SCRATCH_126_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_126_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_126_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_126_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_126_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_126_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_126_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_126_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_126_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_126_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_126_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_126_DATA_SHIFT)
+#define SCRATCH_SCRATCH_126_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_126_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_126_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_126_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_126_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_126_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_126_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_126_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_126_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_126_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_127
+#define SCRATCH_SCRATCH_127                     MK_ADDR_CONST(0x5d8)
+#define SCRATCH_SCRATCH_127_SECURE                      0x0
+#define SCRATCH_SCRATCH_127_DUAL                        0x0
+#define SCRATCH_SCRATCH_127_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_127_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_127_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_127_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_127_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_127_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_127_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_127_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_127_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_127_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_127_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_127_DATA_SHIFT)
+#define SCRATCH_SCRATCH_127_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_127_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_127_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_127_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_127_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_127_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_127_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_127_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_127_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_127_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_128
+#define SCRATCH_SCRATCH_128                     MK_ADDR_CONST(0x5dc)
+#define SCRATCH_SCRATCH_128_SECURE                      0x0
+#define SCRATCH_SCRATCH_128_DUAL                        0x0
+#define SCRATCH_SCRATCH_128_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_128_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_128_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_128_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_128_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_128_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_128_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_128_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_128_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_128_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_128_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_128_DATA_SHIFT)
+#define SCRATCH_SCRATCH_128_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_128_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_128_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_128_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_128_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_128_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_128_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_128_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_128_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_128_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_129
+#define SCRATCH_SCRATCH_129                     MK_ADDR_CONST(0x5e0)
+#define SCRATCH_SCRATCH_129_SECURE                      0x0
+#define SCRATCH_SCRATCH_129_DUAL                        0x0
+#define SCRATCH_SCRATCH_129_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_129_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_129_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_129_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_129_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_129_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_129_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_129_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_129_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_129_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_129_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_129_DATA_SHIFT)
+#define SCRATCH_SCRATCH_129_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_129_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_129_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_129_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_129_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_129_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_129_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_129_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_129_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_129_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_130
+#define SCRATCH_SCRATCH_130                     MK_ADDR_CONST(0x5e4)
+#define SCRATCH_SCRATCH_130_SECURE                      0x0
+#define SCRATCH_SCRATCH_130_DUAL                        0x0
+#define SCRATCH_SCRATCH_130_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_130_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_130_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_130_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_130_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_130_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_130_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_130_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_130_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_130_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_130_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_130_DATA_SHIFT)
+#define SCRATCH_SCRATCH_130_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_130_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_130_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_130_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_130_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_130_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_130_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_130_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_130_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_130_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_131
+#define SCRATCH_SCRATCH_131                     MK_ADDR_CONST(0x5e8)
+#define SCRATCH_SCRATCH_131_SECURE                      0x0
+#define SCRATCH_SCRATCH_131_DUAL                        0x0
+#define SCRATCH_SCRATCH_131_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_131_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_131_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_131_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_131_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_131_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_131_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_131_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_131_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_131_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_131_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_131_DATA_SHIFT)
+#define SCRATCH_SCRATCH_131_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_131_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_131_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_131_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_131_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_131_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_131_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_131_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_131_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_131_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_132
+#define SCRATCH_SCRATCH_132                     MK_ADDR_CONST(0x5ec)
+#define SCRATCH_SCRATCH_132_SECURE                      0x0
+#define SCRATCH_SCRATCH_132_DUAL                        0x0
+#define SCRATCH_SCRATCH_132_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_132_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_132_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_132_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_132_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_132_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_132_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_132_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_132_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_132_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_132_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_132_DATA_SHIFT)
+#define SCRATCH_SCRATCH_132_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_132_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_132_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_132_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_132_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_132_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_132_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_132_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_132_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_132_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_133
+#define SCRATCH_SCRATCH_133                     MK_ADDR_CONST(0x5f0)
+#define SCRATCH_SCRATCH_133_SECURE                      0x0
+#define SCRATCH_SCRATCH_133_DUAL                        0x0
+#define SCRATCH_SCRATCH_133_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_133_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_133_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_133_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_133_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_133_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_133_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_133_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_133_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_133_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_133_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_133_DATA_SHIFT)
+#define SCRATCH_SCRATCH_133_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_133_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_133_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_133_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_133_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_133_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_133_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_133_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_133_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_133_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_134
+#define SCRATCH_SCRATCH_134                     MK_ADDR_CONST(0x5f4)
+#define SCRATCH_SCRATCH_134_SECURE                      0x0
+#define SCRATCH_SCRATCH_134_DUAL                        0x0
+#define SCRATCH_SCRATCH_134_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_134_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_134_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_134_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_134_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_134_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_134_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_134_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_134_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_134_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_134_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_134_DATA_SHIFT)
+#define SCRATCH_SCRATCH_134_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_134_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_134_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_134_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_134_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_134_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_134_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_134_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_134_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_134_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_135
+#define SCRATCH_SCRATCH_135                     MK_ADDR_CONST(0x5f8)
+#define SCRATCH_SCRATCH_135_SECURE                      0x0
+#define SCRATCH_SCRATCH_135_DUAL                        0x0
+#define SCRATCH_SCRATCH_135_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_135_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_135_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_135_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_135_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_135_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_135_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_135_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_135_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_135_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_135_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_135_DATA_SHIFT)
+#define SCRATCH_SCRATCH_135_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_135_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_135_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_135_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_135_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_135_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_135_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_135_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_135_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_135_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_136
+#define SCRATCH_SCRATCH_136                     MK_ADDR_CONST(0x5fc)
+#define SCRATCH_SCRATCH_136_SECURE                      0x0
+#define SCRATCH_SCRATCH_136_DUAL                        0x0
+#define SCRATCH_SCRATCH_136_SCR                         NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_136_SCRREG                      SCRATCH_SCR_NON_SECURE_SCRATCH_SCR_0
+#define SCRATCH_SCRATCH_136_WORD_COUNT                  0x1
+#define SCRATCH_SCRATCH_136_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_136_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_136_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_136_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_136_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_136_WRITE_MASK                  MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_136_DATA_SHIFT                  MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_136_DATA_FIELD                  MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH_136_DATA_SHIFT)
+#define SCRATCH_SCRATCH_136_DATA_RANGE                  31:0
+#define SCRATCH_SCRATCH_136_DATA_MSB                    MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH_136_DATA_LSB                    MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_136_DATA_WOFFSET                        0x0
+#define SCRATCH_SCRATCH_136_DATA_DEFAULT                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_136_DATA_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH_136_DATA_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_136_DATA_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_136_DATA_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_136_DATA_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH0_0
+#define SCRATCH_SCRATCH0_0                      MK_ADDR_CONST(0x2000)
+#define SCRATCH_SCRATCH0_0_SECURE                       0x0
+#define SCRATCH_SCRATCH0_0_DUAL                         0x0
+#define SCRATCH_SCRATCH0_0_SCR                  SCRATCH0_SCR_0
+#define SCRATCH_SCRATCH0_0_SCRREG                       SCRATCH_SCR_SCRATCH0_SCR_0
+#define SCRATCH_SCRATCH0_0_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH0_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH0_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH0_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH0_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH0_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH0_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH0_0_SCRATCH0_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH0_0_SCRATCH0_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH0_0_SCRATCH0_SHIFT)
+#define SCRATCH_SCRATCH0_0_SCRATCH0_RANGE                       31:0
+#define SCRATCH_SCRATCH0_0_SCRATCH0_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH0_0_SCRATCH0_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH0_0_SCRATCH0_WOFFSET                     0x0
+#define SCRATCH_SCRATCH0_0_SCRATCH0_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH0_0_SCRATCH0_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH0_0_SCRATCH0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH0_0_SCRATCH0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH0_0_SCRATCH0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH0_0_SCRATCH0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH1_0
+#define SCRATCH_SCRATCH1_0                      MK_ADDR_CONST(0x2004)
+#define SCRATCH_SCRATCH1_0_SECURE                       0x0
+#define SCRATCH_SCRATCH1_0_DUAL                         0x0
+#define SCRATCH_SCRATCH1_0_SCR                  SCRATCH1_SCR_0
+#define SCRATCH_SCRATCH1_0_SCRREG                       SCRATCH_SCR_SCRATCH1_SCR_0
+#define SCRATCH_SCRATCH1_0_WORD_COUNT                   0x1
+#define SCRATCH_SCRATCH1_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH1_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH1_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH1_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH1_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH1_0_WRITE_MASK                   MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH1_0_SCRATCH1_SHIFT                       MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH1_0_SCRATCH1_FIELD                       MK_FIELD_CONST(0xffffffff, SCRATCH_SCRATCH1_0_SCRATCH1_SHIFT)
+#define SCRATCH_SCRATCH1_0_SCRATCH1_RANGE                       31:0
+#define SCRATCH_SCRATCH1_0_SCRATCH1_MSB                 MK_SHIFT_CONST(31)
+#define SCRATCH_SCRATCH1_0_SCRATCH1_LSB                 MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH1_0_SCRATCH1_WOFFSET                     0x0
+#define SCRATCH_SCRATCH1_0_SCRATCH1_DEFAULT                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH1_0_SCRATCH1_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define SCRATCH_SCRATCH1_0_SCRATCH1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH1_0_SCRATCH1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH1_0_SCRATCH1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH1_0_SCRATCH1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SCRATCH_SCRATCH_SCRUB_STATUS_0
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0                  MK_ADDR_CONST(0x2078)
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_SECURE                   0x0
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_DUAL                     0x0
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_SCR                      0
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_SCRREG                   0
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_WORD_COUNT                       0x1
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_SCRUB_DONE_SHIFT                 MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_SCRUB_DONE_FIELD                 MK_FIELD_CONST(0x1, SCRATCH_SCRATCH_SCRUB_STATUS_0_SCRUB_DONE_SHIFT)
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_SCRUB_DONE_RANGE                 0:0
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_SCRUB_DONE_MSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_SCRUB_DONE_LSB                   MK_SHIFT_CONST(0)
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_SCRUB_DONE_WOFFSET                       0x0
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_SCRUB_DONE_DEFAULT                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_SCRUB_DONE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_SCRUB_DONE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_SCRUB_DONE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_SCRUB_DONE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SCRATCH_SCRATCH_SCRUB_STATUS_0_SCRUB_DONE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+//
+// REGISTER LIST
+//
+#define LIST_ARSCRATCH_REGS(_op_) \
+_op_(SCRATCH_SECURE_BL_SCRATCH_0) \
+_op_(SCRATCH_SECURE_BL_SCRATCH) \
+_op_(SCRATCH_SECURE_BL_SCRATCH_1) \
+_op_(SCRATCH_SECURE_BL_SCRATCH_2) \
+_op_(SCRATCH_SECURE_BL_SCRATCH_3) \
+_op_(SCRATCH_SECURE_BL_SCRATCH_4) \
+_op_(SCRATCH_SECURE_BL_SCRATCH_5) \
+_op_(SCRATCH_SECURE_BL_SCRATCH_6) \
+_op_(SCRATCH_SECURE_BL_SCRATCH_7) \
+_op_(SCRATCH_SECURE_BL_SCRATCH_8) \
+_op_(SCRATCH_SECURE_BL_SCRATCH_9) \
+_op_(SCRATCH_SECURE_BL_SCRATCH_10) \
+_op_(SCRATCH_SECURE_BL_SCRATCH_11) \
+_op_(SCRATCH_SECURE_BL_SCRATCH_12) \
+_op_(SCRATCH_SECURE_BL_SCRATCH_13) \
+_op_(SCRATCH_SECURE_BL_SCRATCH_14) \
+_op_(SCRATCH_SECURE_MTS_SCRATCH_0) \
+_op_(SCRATCH_SECURE_MTS_SCRATCH) \
+_op_(SCRATCH_SECURE_MTS_SCRATCH_1) \
+_op_(SCRATCH_SECURE_MTS_SCRATCH_2) \
+_op_(SCRATCH_SECURE_MTS_SCRATCH_3) \
+_op_(SCRATCH_SECURE_MTS_SCRATCH_4) \
+_op_(SCRATCH_SECURE_MTS_SCRATCH_5) \
+_op_(SCRATCH_SECURE_MTS_SCRATCH_6) \
+_op_(SCRATCH_SECURE_MTS_SCRATCH_7) \
+_op_(SCRATCH_SECURE_MTS_SCRATCH_8) \
+_op_(SCRATCH_SECURE_MTS_SCRATCH_9) \
+_op_(SCRATCH_SECURE_RSV0_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV0_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV0_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV1_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV1_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV1_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV2_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV2_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV2_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV3_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV3_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV3_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV4_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV4_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV4_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV5_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV5_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV5_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV6_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV6_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV6_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV7_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV7_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV7_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV8_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV8_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV8_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV9_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV9_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV9_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV10_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV10_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV10_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV11_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV11_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV11_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV12_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV12_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV12_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV13_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV13_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV13_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV14_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV14_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV14_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV15_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV15_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV15_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV16_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV16_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV16_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV17_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV17_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV17_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV18_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV18_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV18_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV19_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV19_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV19_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV20_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV20_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV20_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV21_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV21_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV21_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV22_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV22_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV22_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV23_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV23_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV23_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV24_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV24_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV24_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV25_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV25_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV25_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV26_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV26_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV26_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV27_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV27_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV27_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV28_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV28_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV28_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV29_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV29_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV29_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV30_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV30_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV30_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV31_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV31_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV31_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV32_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV32_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV32_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV33_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV33_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV33_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV34_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV34_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV34_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV35_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV35_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV35_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV36_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV36_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV36_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV37_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV37_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV37_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV38_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV38_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV38_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV39_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV39_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV39_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV40_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV40_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV40_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV41_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV41_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV41_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV42_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV42_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV42_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV43_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV43_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV43_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV44_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV44_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV44_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV45_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV45_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV45_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV46_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV46_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV46_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV47_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV47_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV47_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV48_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV48_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV48_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV49_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV49_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV49_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV50_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV50_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV50_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV51_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV51_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV51_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV52_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV52_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV52_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV53_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV53_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV53_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV54_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV54_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV54_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV55_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV55_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV55_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV56_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV56_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV56_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV57_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV57_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV57_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV58_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV58_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV58_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV59_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV59_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV59_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV60_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV60_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV60_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV61_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV61_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV61_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV62_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV62_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV62_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV63_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV63_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV63_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV64_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV64_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV64_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV65_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV65_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV65_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV66_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV66_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV66_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV67_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV67_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV67_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV68_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV68_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV68_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV69_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV69_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV69_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV70_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV70_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV70_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV71_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV71_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV71_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV72_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV72_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV72_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV73_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV73_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV73_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV74_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV74_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV74_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV75_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV75_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV75_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV76_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV76_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV76_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV77_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV77_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV77_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV78_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV78_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV78_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV79_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV79_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV79_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV80_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV80_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV80_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV81_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV81_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV81_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV82_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV82_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV82_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV83_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV83_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV83_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV84_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV84_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV84_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV85_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV85_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV85_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV86_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV86_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV86_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV87_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV87_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV87_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV88_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV88_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV88_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV89_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV89_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV89_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV90_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV90_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV90_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV91_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV91_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV91_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV92_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV92_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV92_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV93_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV93_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV93_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV94_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV94_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV94_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV95_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV95_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV95_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV96_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV96_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV96_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV97_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV97_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV97_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV98_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV98_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV98_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV99_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV99_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV99_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV100_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV100_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV100_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV101_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV101_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV101_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV102_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV102_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV102_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV103_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV103_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV103_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV104_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV104_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV104_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV105_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV105_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV105_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV106_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV106_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV106_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV107_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV107_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV107_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV108_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV108_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV108_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV109_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV109_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV109_SCRATCH_1) \
+_op_(SCRATCH_SECURE_RSV110_SCRATCH_0) \
+_op_(SCRATCH_SECURE_RSV110_SCRATCH) \
+_op_(SCRATCH_SECURE_RSV110_SCRATCH_1) \
+_op_(SCRATCH_SCRATCH_0) \
+_op_(SCRATCH_SCRATCH) \
+_op_(SCRATCH_SCRATCH_1) \
+_op_(SCRATCH_SCRATCH_2) \
+_op_(SCRATCH_SCRATCH_3) \
+_op_(SCRATCH_SCRATCH_4) \
+_op_(SCRATCH_SCRATCH_5) \
+_op_(SCRATCH_SCRATCH_6) \
+_op_(SCRATCH_SCRATCH_7) \
+_op_(SCRATCH_SCRATCH_8) \
+_op_(SCRATCH_SCRATCH_9) \
+_op_(SCRATCH_SCRATCH_10) \
+_op_(SCRATCH_SCRATCH_11) \
+_op_(SCRATCH_SCRATCH_12) \
+_op_(SCRATCH_SCRATCH_13) \
+_op_(SCRATCH_SCRATCH_14) \
+_op_(SCRATCH_SCRATCH_15) \
+_op_(SCRATCH_SCRATCH_16) \
+_op_(SCRATCH_SCRATCH_17) \
+_op_(SCRATCH_SCRATCH_18) \
+_op_(SCRATCH_SCRATCH_19) \
+_op_(SCRATCH_SCRATCH_20) \
+_op_(SCRATCH_SCRATCH_21) \
+_op_(SCRATCH_SCRATCH_22) \
+_op_(SCRATCH_SCRATCH_23) \
+_op_(SCRATCH_SCRATCH_24) \
+_op_(SCRATCH_SCRATCH_25) \
+_op_(SCRATCH_SCRATCH_26) \
+_op_(SCRATCH_SCRATCH_27) \
+_op_(SCRATCH_SCRATCH_28) \
+_op_(SCRATCH_SCRATCH_29) \
+_op_(SCRATCH_SCRATCH_30) \
+_op_(SCRATCH_SCRATCH_31) \
+_op_(SCRATCH_SCRATCH_32) \
+_op_(SCRATCH_SCRATCH_33) \
+_op_(SCRATCH_SCRATCH_34) \
+_op_(SCRATCH_SCRATCH_35) \
+_op_(SCRATCH_SCRATCH_36) \
+_op_(SCRATCH_SCRATCH_37) \
+_op_(SCRATCH_SCRATCH_38) \
+_op_(SCRATCH_SCRATCH_39) \
+_op_(SCRATCH_SCRATCH_40) \
+_op_(SCRATCH_SCRATCH_41) \
+_op_(SCRATCH_SCRATCH_42) \
+_op_(SCRATCH_SCRATCH_43) \
+_op_(SCRATCH_SCRATCH_44) \
+_op_(SCRATCH_SCRATCH_45) \
+_op_(SCRATCH_SCRATCH_46) \
+_op_(SCRATCH_SCRATCH_47) \
+_op_(SCRATCH_SCRATCH_48) \
+_op_(SCRATCH_SCRATCH_49) \
+_op_(SCRATCH_SCRATCH_50) \
+_op_(SCRATCH_SCRATCH_51) \
+_op_(SCRATCH_SCRATCH_52) \
+_op_(SCRATCH_SCRATCH_53) \
+_op_(SCRATCH_SCRATCH_54) \
+_op_(SCRATCH_SCRATCH_55) \
+_op_(SCRATCH_SCRATCH_56) \
+_op_(SCRATCH_SCRATCH_57) \
+_op_(SCRATCH_SCRATCH_58) \
+_op_(SCRATCH_SCRATCH_59) \
+_op_(SCRATCH_SCRATCH_60) \
+_op_(SCRATCH_SCRATCH_61) \
+_op_(SCRATCH_SCRATCH_62) \
+_op_(SCRATCH_SCRATCH_63) \
+_op_(SCRATCH_SCRATCH_64) \
+_op_(SCRATCH_SCRATCH_65) \
+_op_(SCRATCH_SCRATCH_66) \
+_op_(SCRATCH_SCRATCH_67) \
+_op_(SCRATCH_SCRATCH_68) \
+_op_(SCRATCH_SCRATCH_69) \
+_op_(SCRATCH_SCRATCH_70) \
+_op_(SCRATCH_SCRATCH_71) \
+_op_(SCRATCH_SCRATCH_72) \
+_op_(SCRATCH_SCRATCH_73) \
+_op_(SCRATCH_SCRATCH_74) \
+_op_(SCRATCH_SCRATCH_75) \
+_op_(SCRATCH_SCRATCH_76) \
+_op_(SCRATCH_SCRATCH_77) \
+_op_(SCRATCH_SCRATCH_78) \
+_op_(SCRATCH_SCRATCH_79) \
+_op_(SCRATCH_SCRATCH_80) \
+_op_(SCRATCH_SCRATCH_81) \
+_op_(SCRATCH_SCRATCH_82) \
+_op_(SCRATCH_SCRATCH_83) \
+_op_(SCRATCH_SCRATCH_84) \
+_op_(SCRATCH_SCRATCH_85) \
+_op_(SCRATCH_SCRATCH_86) \
+_op_(SCRATCH_SCRATCH_87) \
+_op_(SCRATCH_SCRATCH_88) \
+_op_(SCRATCH_SCRATCH_89) \
+_op_(SCRATCH_SCRATCH_90) \
+_op_(SCRATCH_SCRATCH_91) \
+_op_(SCRATCH_SCRATCH_92) \
+_op_(SCRATCH_SCRATCH_93) \
+_op_(SCRATCH_SCRATCH_94) \
+_op_(SCRATCH_SCRATCH_95) \
+_op_(SCRATCH_SCRATCH_96) \
+_op_(SCRATCH_SCRATCH_97) \
+_op_(SCRATCH_SCRATCH_98) \
+_op_(SCRATCH_SCRATCH_99) \
+_op_(SCRATCH_SCRATCH_100) \
+_op_(SCRATCH_SCRATCH_101) \
+_op_(SCRATCH_SCRATCH_102) \
+_op_(SCRATCH_SCRATCH_103) \
+_op_(SCRATCH_SCRATCH_104) \
+_op_(SCRATCH_SCRATCH_105) \
+_op_(SCRATCH_SCRATCH_106) \
+_op_(SCRATCH_SCRATCH_107) \
+_op_(SCRATCH_SCRATCH_108) \
+_op_(SCRATCH_SCRATCH_109) \
+_op_(SCRATCH_SCRATCH_110) \
+_op_(SCRATCH_SCRATCH_111) \
+_op_(SCRATCH_SCRATCH_112) \
+_op_(SCRATCH_SCRATCH_113) \
+_op_(SCRATCH_SCRATCH_114) \
+_op_(SCRATCH_SCRATCH_115) \
+_op_(SCRATCH_SCRATCH_116) \
+_op_(SCRATCH_SCRATCH_117) \
+_op_(SCRATCH_SCRATCH_118) \
+_op_(SCRATCH_SCRATCH_119) \
+_op_(SCRATCH_SCRATCH_120) \
+_op_(SCRATCH_SCRATCH_121) \
+_op_(SCRATCH_SCRATCH_122) \
+_op_(SCRATCH_SCRATCH_123) \
+_op_(SCRATCH_SCRATCH_124) \
+_op_(SCRATCH_SCRATCH_125) \
+_op_(SCRATCH_SCRATCH_126) \
+_op_(SCRATCH_SCRATCH_127) \
+_op_(SCRATCH_SCRATCH_128) \
+_op_(SCRATCH_SCRATCH_129) \
+_op_(SCRATCH_SCRATCH_130) \
+_op_(SCRATCH_SCRATCH_131) \
+_op_(SCRATCH_SCRATCH_132) \
+_op_(SCRATCH_SCRATCH_133) \
+_op_(SCRATCH_SCRATCH_134) \
+_op_(SCRATCH_SCRATCH_135) \
+_op_(SCRATCH_SCRATCH_136) \
+_op_(SCRATCH_SCRATCH0_0) \
+_op_(SCRATCH_SCRATCH1_0) \
+_op_(SCRATCH_SCRATCH_SCRUB_STATUS_0)
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_SCRATCH    0x00000000
+
+//
+// ARSCRATCH REGISTER BANKS
+//
+
+#define SCRATCH0_FIRST_REG 0x0000 // SCRATCH_SECURE_BL_SCRATCH_0
+#define SCRATCH0_LAST_REG 0x05fc // SCRATCH_SCRATCH_136
+#define SCRATCH1_FIRST_REG 0x2000 // SCRATCH_SCRATCH0_0
+#define SCRATCH1_LAST_REG 0x2078 // SCRATCH_SCRATCH_SCRUB_STATUS_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARSCRATCH_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arspi.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arspi.h
new file mode 100644
index 0000000..0bb318b
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arspi.h
@@ -0,0 +1,2048 @@
+//
+// Copyright (c) 2023 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARSPI_H_INC
+#define ARSPI_H_INC
+#define NV_MOBILE_ARSPI_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARSPI_H_SCRREG_NOMENCLATURE INFERRED
+
+// Register SPI_COMMAND_0
+#define SPI_COMMAND_0                   MK_ADDR_CONST(0x0)
+#define SPI_COMMAND_0_SECURE                    0x0
+#define SPI_COMMAND_0_DUAL                      0x0
+#define SPI_COMMAND_0_SCR                       0
+#define SPI_COMMAND_0_SCRREG                    0
+#define SPI_COMMAND_0_WORD_COUNT                        0x1
+#define SPI_COMMAND_0_RESET_VAL                         MK_MASK_CONST(0x43d00000)
+#define SPI_COMMAND_0_RESET_MASK                        MK_MASK_CONST(0xfffff87f)
+#define SPI_COMMAND_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_READ_MASK                         MK_MASK_CONST(0xfffff87f)
+#define SPI_COMMAND_0_WRITE_MASK                        MK_MASK_CONST(0xfffff87f)
+#define SPI_COMMAND_0_PIO_SHIFT                 MK_SHIFT_CONST(31)
+#define SPI_COMMAND_0_PIO_FIELD                 MK_FIELD_CONST(0x1, SPI_COMMAND_0_PIO_SHIFT)
+#define SPI_COMMAND_0_PIO_RANGE                 31:31
+#define SPI_COMMAND_0_PIO_MSB                   MK_SHIFT_CONST(31)
+#define SPI_COMMAND_0_PIO_LSB                   MK_SHIFT_CONST(31)
+#define SPI_COMMAND_0_PIO_WOFFSET                       0x0
+#define SPI_COMMAND_0_PIO_DEFAULT                       MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_PIO_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_PIO_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_PIO_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_PIO_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_PIO_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_PIO_STOP                  MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_PIO_PIO                   MK_ENUM_CONST(1)
+
+#define SPI_COMMAND_0_M_S_SHIFT                 MK_SHIFT_CONST(30)
+#define SPI_COMMAND_0_M_S_FIELD                 MK_FIELD_CONST(0x1, SPI_COMMAND_0_M_S_SHIFT)
+#define SPI_COMMAND_0_M_S_RANGE                 30:30
+#define SPI_COMMAND_0_M_S_MSB                   MK_SHIFT_CONST(30)
+#define SPI_COMMAND_0_M_S_LSB                   MK_SHIFT_CONST(30)
+#define SPI_COMMAND_0_M_S_WOFFSET                       0x0
+#define SPI_COMMAND_0_M_S_DEFAULT                       MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_M_S_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_M_S_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_M_S_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_M_S_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_M_S_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_M_S_SLAVE                 MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_M_S_MASTER                        MK_ENUM_CONST(1)
+
+#define SPI_COMMAND_0_MODE_SHIFT                        MK_SHIFT_CONST(28)
+#define SPI_COMMAND_0_MODE_FIELD                        MK_FIELD_CONST(0x3, SPI_COMMAND_0_MODE_SHIFT)
+#define SPI_COMMAND_0_MODE_RANGE                        29:28
+#define SPI_COMMAND_0_MODE_MSB                  MK_SHIFT_CONST(29)
+#define SPI_COMMAND_0_MODE_LSB                  MK_SHIFT_CONST(28)
+#define SPI_COMMAND_0_MODE_WOFFSET                      0x0
+#define SPI_COMMAND_0_MODE_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_MODE_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define SPI_COMMAND_0_MODE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_MODE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_MODE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_MODE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_MODE_Mode0                        MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_MODE_Mode1                        MK_ENUM_CONST(1)
+#define SPI_COMMAND_0_MODE_Mode2                        MK_ENUM_CONST(2)
+#define SPI_COMMAND_0_MODE_Mode3                        MK_ENUM_CONST(3)
+
+#define SPI_COMMAND_0_CS_SEL_SHIFT                      MK_SHIFT_CONST(26)
+#define SPI_COMMAND_0_CS_SEL_FIELD                      MK_FIELD_CONST(0x3, SPI_COMMAND_0_CS_SEL_SHIFT)
+#define SPI_COMMAND_0_CS_SEL_RANGE                      27:26
+#define SPI_COMMAND_0_CS_SEL_MSB                        MK_SHIFT_CONST(27)
+#define SPI_COMMAND_0_CS_SEL_LSB                        MK_SHIFT_CONST(26)
+#define SPI_COMMAND_0_CS_SEL_WOFFSET                    0x0
+#define SPI_COMMAND_0_CS_SEL_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_SEL_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define SPI_COMMAND_0_CS_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_SEL_CS0                        MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS_SEL_CS1                        MK_ENUM_CONST(1)
+#define SPI_COMMAND_0_CS_SEL_CS2                        MK_ENUM_CONST(2)
+#define SPI_COMMAND_0_CS_SEL_CS3                        MK_ENUM_CONST(3)
+
+#define SPI_COMMAND_0_CS_POL_INACTIVE3_SHIFT                    MK_SHIFT_CONST(25)
+#define SPI_COMMAND_0_CS_POL_INACTIVE3_FIELD                    MK_FIELD_CONST(0x1, SPI_COMMAND_0_CS_POL_INACTIVE3_SHIFT)
+#define SPI_COMMAND_0_CS_POL_INACTIVE3_RANGE                    25:25
+#define SPI_COMMAND_0_CS_POL_INACTIVE3_MSB                      MK_SHIFT_CONST(25)
+#define SPI_COMMAND_0_CS_POL_INACTIVE3_LSB                      MK_SHIFT_CONST(25)
+#define SPI_COMMAND_0_CS_POL_INACTIVE3_WOFFSET                  0x0
+#define SPI_COMMAND_0_CS_POL_INACTIVE3_DEFAULT                  MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_POL_INACTIVE3_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_POL_INACTIVE3_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_INACTIVE3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_INACTIVE3_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_INACTIVE3_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_POL_INACTIVE3_LOW                      MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS_POL_INACTIVE3_HIGH                     MK_ENUM_CONST(1)
+
+#define SPI_COMMAND_0_CS_POL_INACTIVE2_SHIFT                    MK_SHIFT_CONST(24)
+#define SPI_COMMAND_0_CS_POL_INACTIVE2_FIELD                    MK_FIELD_CONST(0x1, SPI_COMMAND_0_CS_POL_INACTIVE2_SHIFT)
+#define SPI_COMMAND_0_CS_POL_INACTIVE2_RANGE                    24:24
+#define SPI_COMMAND_0_CS_POL_INACTIVE2_MSB                      MK_SHIFT_CONST(24)
+#define SPI_COMMAND_0_CS_POL_INACTIVE2_LSB                      MK_SHIFT_CONST(24)
+#define SPI_COMMAND_0_CS_POL_INACTIVE2_WOFFSET                  0x0
+#define SPI_COMMAND_0_CS_POL_INACTIVE2_DEFAULT                  MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_POL_INACTIVE2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_POL_INACTIVE2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_INACTIVE2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_INACTIVE2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_INACTIVE2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_POL_INACTIVE2_LOW                      MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS_POL_INACTIVE2_HIGH                     MK_ENUM_CONST(1)
+
+#define SPI_COMMAND_0_CS_POL_INACTIVE1_SHIFT                    MK_SHIFT_CONST(23)
+#define SPI_COMMAND_0_CS_POL_INACTIVE1_FIELD                    MK_FIELD_CONST(0x1, SPI_COMMAND_0_CS_POL_INACTIVE1_SHIFT)
+#define SPI_COMMAND_0_CS_POL_INACTIVE1_RANGE                    23:23
+#define SPI_COMMAND_0_CS_POL_INACTIVE1_MSB                      MK_SHIFT_CONST(23)
+#define SPI_COMMAND_0_CS_POL_INACTIVE1_LSB                      MK_SHIFT_CONST(23)
+#define SPI_COMMAND_0_CS_POL_INACTIVE1_WOFFSET                  0x0
+#define SPI_COMMAND_0_CS_POL_INACTIVE1_DEFAULT                  MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_POL_INACTIVE1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_POL_INACTIVE1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_INACTIVE1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_INACTIVE1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_INACTIVE1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_POL_INACTIVE1_LOW                      MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS_POL_INACTIVE1_HIGH                     MK_ENUM_CONST(1)
+
+#define SPI_COMMAND_0_CS_POL_INACTIVE0_SHIFT                    MK_SHIFT_CONST(22)
+#define SPI_COMMAND_0_CS_POL_INACTIVE0_FIELD                    MK_FIELD_CONST(0x1, SPI_COMMAND_0_CS_POL_INACTIVE0_SHIFT)
+#define SPI_COMMAND_0_CS_POL_INACTIVE0_RANGE                    22:22
+#define SPI_COMMAND_0_CS_POL_INACTIVE0_MSB                      MK_SHIFT_CONST(22)
+#define SPI_COMMAND_0_CS_POL_INACTIVE0_LSB                      MK_SHIFT_CONST(22)
+#define SPI_COMMAND_0_CS_POL_INACTIVE0_WOFFSET                  0x0
+#define SPI_COMMAND_0_CS_POL_INACTIVE0_DEFAULT                  MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_POL_INACTIVE0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_POL_INACTIVE0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_INACTIVE0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_INACTIVE0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_POL_INACTIVE0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_POL_INACTIVE0_LOW                      MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS_POL_INACTIVE0_HIGH                     MK_ENUM_CONST(1)
+
+#define SPI_COMMAND_0_CS_SW_HW_SHIFT                    MK_SHIFT_CONST(21)
+#define SPI_COMMAND_0_CS_SW_HW_FIELD                    MK_FIELD_CONST(0x1, SPI_COMMAND_0_CS_SW_HW_SHIFT)
+#define SPI_COMMAND_0_CS_SW_HW_RANGE                    21:21
+#define SPI_COMMAND_0_CS_SW_HW_MSB                      MK_SHIFT_CONST(21)
+#define SPI_COMMAND_0_CS_SW_HW_LSB                      MK_SHIFT_CONST(21)
+#define SPI_COMMAND_0_CS_SW_HW_WOFFSET                  0x0
+#define SPI_COMMAND_0_CS_SW_HW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_SW_HW_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_SW_HW_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_SW_HW_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_SW_HW_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_SW_HW_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_SW_HW_HARDWARE                 MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS_SW_HW_SOFTWARE                 MK_ENUM_CONST(1)
+
+#define SPI_COMMAND_0_CS_SW_VAL_SHIFT                   MK_SHIFT_CONST(20)
+#define SPI_COMMAND_0_CS_SW_VAL_FIELD                   MK_FIELD_CONST(0x1, SPI_COMMAND_0_CS_SW_VAL_SHIFT)
+#define SPI_COMMAND_0_CS_SW_VAL_RANGE                   20:20
+#define SPI_COMMAND_0_CS_SW_VAL_MSB                     MK_SHIFT_CONST(20)
+#define SPI_COMMAND_0_CS_SW_VAL_LSB                     MK_SHIFT_CONST(20)
+#define SPI_COMMAND_0_CS_SW_VAL_WOFFSET                 0x0
+#define SPI_COMMAND_0_CS_SW_VAL_DEFAULT                 MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_SW_VAL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_SW_VAL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_SW_VAL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_SW_VAL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_SW_VAL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_SW_VAL_LOW                     MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS_SW_VAL_HIGH                    MK_ENUM_CONST(1)
+
+#define SPI_COMMAND_0_IDLE_SDA_SHIFT                    MK_SHIFT_CONST(18)
+#define SPI_COMMAND_0_IDLE_SDA_FIELD                    MK_FIELD_CONST(0x3, SPI_COMMAND_0_IDLE_SDA_SHIFT)
+#define SPI_COMMAND_0_IDLE_SDA_RANGE                    19:18
+#define SPI_COMMAND_0_IDLE_SDA_MSB                      MK_SHIFT_CONST(19)
+#define SPI_COMMAND_0_IDLE_SDA_LSB                      MK_SHIFT_CONST(18)
+#define SPI_COMMAND_0_IDLE_SDA_WOFFSET                  0x0
+#define SPI_COMMAND_0_IDLE_SDA_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_IDLE_SDA_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define SPI_COMMAND_0_IDLE_SDA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_IDLE_SDA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_IDLE_SDA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_IDLE_SDA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_IDLE_SDA_DRIVE_LOW                        MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_IDLE_SDA_DRIVE_HIGH                       MK_ENUM_CONST(1)
+#define SPI_COMMAND_0_IDLE_SDA_PULL_LOW                 MK_ENUM_CONST(2)
+#define SPI_COMMAND_0_IDLE_SDA_PULL_HIGH                        MK_ENUM_CONST(3)
+
+#define SPI_COMMAND_0_BIDIR_SHIFT                       MK_SHIFT_CONST(17)
+#define SPI_COMMAND_0_BIDIR_FIELD                       MK_FIELD_CONST(0x1, SPI_COMMAND_0_BIDIR_SHIFT)
+#define SPI_COMMAND_0_BIDIR_RANGE                       17:17
+#define SPI_COMMAND_0_BIDIR_MSB                 MK_SHIFT_CONST(17)
+#define SPI_COMMAND_0_BIDIR_LSB                 MK_SHIFT_CONST(17)
+#define SPI_COMMAND_0_BIDIR_WOFFSET                     0x0
+#define SPI_COMMAND_0_BIDIR_DEFAULT                     MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BIDIR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_BIDIR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BIDIR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BIDIR_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BIDIR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_BIDIR_NORMAL                      MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_BIDIR_BIDIR                       MK_ENUM_CONST(1)
+
+#define SPI_COMMAND_0_En_LE_Bit_SHIFT                   MK_SHIFT_CONST(16)
+#define SPI_COMMAND_0_En_LE_Bit_FIELD                   MK_FIELD_CONST(0x1, SPI_COMMAND_0_En_LE_Bit_SHIFT)
+#define SPI_COMMAND_0_En_LE_Bit_RANGE                   16:16
+#define SPI_COMMAND_0_En_LE_Bit_MSB                     MK_SHIFT_CONST(16)
+#define SPI_COMMAND_0_En_LE_Bit_LSB                     MK_SHIFT_CONST(16)
+#define SPI_COMMAND_0_En_LE_Bit_WOFFSET                 0x0
+#define SPI_COMMAND_0_En_LE_Bit_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_En_LE_Bit_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_En_LE_Bit_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_En_LE_Bit_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_En_LE_Bit_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_En_LE_Bit_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_En_LE_Bit_LAST                    MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_En_LE_Bit_FIRST                   MK_ENUM_CONST(1)
+
+#define SPI_COMMAND_0_En_LE_Byte_SHIFT                  MK_SHIFT_CONST(15)
+#define SPI_COMMAND_0_En_LE_Byte_FIELD                  MK_FIELD_CONST(0x1, SPI_COMMAND_0_En_LE_Byte_SHIFT)
+#define SPI_COMMAND_0_En_LE_Byte_RANGE                  15:15
+#define SPI_COMMAND_0_En_LE_Byte_MSB                    MK_SHIFT_CONST(15)
+#define SPI_COMMAND_0_En_LE_Byte_LSB                    MK_SHIFT_CONST(15)
+#define SPI_COMMAND_0_En_LE_Byte_WOFFSET                        0x0
+#define SPI_COMMAND_0_En_LE_Byte_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_En_LE_Byte_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_En_LE_Byte_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_En_LE_Byte_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_En_LE_Byte_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_En_LE_Byte_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_En_LE_Byte_LAST                   MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_En_LE_Byte_FIRST                  MK_ENUM_CONST(1)
+
+#define SPI_COMMAND_0_BOTH_EN_BIT_SHIFT                 MK_SHIFT_CONST(14)
+#define SPI_COMMAND_0_BOTH_EN_BIT_FIELD                 MK_FIELD_CONST(0x1, SPI_COMMAND_0_BOTH_EN_BIT_SHIFT)
+#define SPI_COMMAND_0_BOTH_EN_BIT_RANGE                 14:14
+#define SPI_COMMAND_0_BOTH_EN_BIT_MSB                   MK_SHIFT_CONST(14)
+#define SPI_COMMAND_0_BOTH_EN_BIT_LSB                   MK_SHIFT_CONST(14)
+#define SPI_COMMAND_0_BOTH_EN_BIT_WOFFSET                       0x0
+#define SPI_COMMAND_0_BOTH_EN_BIT_DEFAULT                       MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BOTH_EN_BIT_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_BOTH_EN_BIT_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BOTH_EN_BIT_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BOTH_EN_BIT_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BOTH_EN_BIT_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_BOTH_EN_BIT_DISABLE                       MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_BOTH_EN_BIT_ENABLE                        MK_ENUM_CONST(1)
+
+#define SPI_COMMAND_0_BOTH_EN_BYTE_SHIFT                        MK_SHIFT_CONST(13)
+#define SPI_COMMAND_0_BOTH_EN_BYTE_FIELD                        MK_FIELD_CONST(0x1, SPI_COMMAND_0_BOTH_EN_BYTE_SHIFT)
+#define SPI_COMMAND_0_BOTH_EN_BYTE_RANGE                        13:13
+#define SPI_COMMAND_0_BOTH_EN_BYTE_MSB                  MK_SHIFT_CONST(13)
+#define SPI_COMMAND_0_BOTH_EN_BYTE_LSB                  MK_SHIFT_CONST(13)
+#define SPI_COMMAND_0_BOTH_EN_BYTE_WOFFSET                      0x0
+#define SPI_COMMAND_0_BOTH_EN_BYTE_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BOTH_EN_BYTE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_BOTH_EN_BYTE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BOTH_EN_BYTE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BOTH_EN_BYTE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BOTH_EN_BYTE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_BOTH_EN_BYTE_DISABLE                      MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_BOTH_EN_BYTE_ENABLE                       MK_ENUM_CONST(1)
+
+#define SPI_COMMAND_0_Rx_EN_SHIFT                       MK_SHIFT_CONST(12)
+#define SPI_COMMAND_0_Rx_EN_FIELD                       MK_FIELD_CONST(0x1, SPI_COMMAND_0_Rx_EN_SHIFT)
+#define SPI_COMMAND_0_Rx_EN_RANGE                       12:12
+#define SPI_COMMAND_0_Rx_EN_MSB                 MK_SHIFT_CONST(12)
+#define SPI_COMMAND_0_Rx_EN_LSB                 MK_SHIFT_CONST(12)
+#define SPI_COMMAND_0_Rx_EN_WOFFSET                     0x0
+#define SPI_COMMAND_0_Rx_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_Rx_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_Rx_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_Rx_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_Rx_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_Rx_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_Rx_EN_DISABLE                     MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_Rx_EN_ENABLE                      MK_ENUM_CONST(1)
+
+#define SPI_COMMAND_0_Tx_EN_SHIFT                       MK_SHIFT_CONST(11)
+#define SPI_COMMAND_0_Tx_EN_FIELD                       MK_FIELD_CONST(0x1, SPI_COMMAND_0_Tx_EN_SHIFT)
+#define SPI_COMMAND_0_Tx_EN_RANGE                       11:11
+#define SPI_COMMAND_0_Tx_EN_MSB                 MK_SHIFT_CONST(11)
+#define SPI_COMMAND_0_Tx_EN_LSB                 MK_SHIFT_CONST(11)
+#define SPI_COMMAND_0_Tx_EN_WOFFSET                     0x0
+#define SPI_COMMAND_0_Tx_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_Tx_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_Tx_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_Tx_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_Tx_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_Tx_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_Tx_EN_DISABLE                     MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_Tx_EN_ENABLE                      MK_ENUM_CONST(1)
+
+#define SPI_COMMAND_0_CS_GPIO_SHIFT                     MK_SHIFT_CONST(6)
+#define SPI_COMMAND_0_CS_GPIO_FIELD                     MK_FIELD_CONST(0x1, SPI_COMMAND_0_CS_GPIO_SHIFT)
+#define SPI_COMMAND_0_CS_GPIO_RANGE                     6:6
+#define SPI_COMMAND_0_CS_GPIO_MSB                       MK_SHIFT_CONST(6)
+#define SPI_COMMAND_0_CS_GPIO_LSB                       MK_SHIFT_CONST(6)
+#define SPI_COMMAND_0_CS_GPIO_WOFFSET                   0x0
+#define SPI_COMMAND_0_CS_GPIO_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_GPIO_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_GPIO_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_GPIO_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_GPIO_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_CS_GPIO_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_CS_GPIO_DISABLE                   MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_CS_GPIO_ENABLE                    MK_ENUM_CONST(1)
+
+#define SPI_COMMAND_0_PACKED_SHIFT                      MK_SHIFT_CONST(5)
+#define SPI_COMMAND_0_PACKED_FIELD                      MK_FIELD_CONST(0x1, SPI_COMMAND_0_PACKED_SHIFT)
+#define SPI_COMMAND_0_PACKED_RANGE                      5:5
+#define SPI_COMMAND_0_PACKED_MSB                        MK_SHIFT_CONST(5)
+#define SPI_COMMAND_0_PACKED_LSB                        MK_SHIFT_CONST(5)
+#define SPI_COMMAND_0_PACKED_WOFFSET                    0x0
+#define SPI_COMMAND_0_PACKED_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_PACKED_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_PACKED_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_PACKED_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_PACKED_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_PACKED_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define SPI_COMMAND_0_PACKED_DISABLE                    MK_ENUM_CONST(0)
+#define SPI_COMMAND_0_PACKED_ENABLE                     MK_ENUM_CONST(1)
+
+#define SPI_COMMAND_0_BIT_LENGTH_SHIFT                  MK_SHIFT_CONST(0)
+#define SPI_COMMAND_0_BIT_LENGTH_FIELD                  MK_FIELD_CONST(0x1f, SPI_COMMAND_0_BIT_LENGTH_SHIFT)
+#define SPI_COMMAND_0_BIT_LENGTH_RANGE                  4:0
+#define SPI_COMMAND_0_BIT_LENGTH_MSB                    MK_SHIFT_CONST(4)
+#define SPI_COMMAND_0_BIT_LENGTH_LSB                    MK_SHIFT_CONST(0)
+#define SPI_COMMAND_0_BIT_LENGTH_WOFFSET                        0x0
+#define SPI_COMMAND_0_BIT_LENGTH_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BIT_LENGTH_DEFAULT_MASK                   MK_MASK_CONST(0x1f)
+#define SPI_COMMAND_0_BIT_LENGTH_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BIT_LENGTH_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BIT_LENGTH_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define SPI_COMMAND_0_BIT_LENGTH_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+// Register SPI_COMMAND2_0
+#define SPI_COMMAND2_0                  MK_ADDR_CONST(0x4)
+#define SPI_COMMAND2_0_SECURE                   0x0
+#define SPI_COMMAND2_0_DUAL                     0x0
+#define SPI_COMMAND2_0_SCR                      0
+#define SPI_COMMAND2_0_SCRREG                   0
+#define SPI_COMMAND2_0_WORD_COUNT                       0x1
+#define SPI_COMMAND2_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define SPI_COMMAND2_0_RESET_MASK                       MK_MASK_CONST(0xfff)
+#define SPI_COMMAND2_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define SPI_COMMAND2_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SPI_COMMAND2_0_READ_MASK                        MK_MASK_CONST(0xfff)
+#define SPI_COMMAND2_0_WRITE_MASK                       MK_MASK_CONST(0xfff)
+#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_SHIFT                   MK_SHIFT_CONST(6)
+#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_FIELD                   MK_FIELD_CONST(0x3f, SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_SHIFT)
+#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_RANGE                   11:6
+#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_MSB                     MK_SHIFT_CONST(11)
+#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_LSB                     MK_SHIFT_CONST(6)
+#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_WOFFSET                 0x0
+#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SPI_COMMAND2_0_Tx_Clk_TAP_DELAY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_SHIFT                   MK_SHIFT_CONST(0)
+#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_FIELD                   MK_FIELD_CONST(0x3f, SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_SHIFT)
+#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_RANGE                   5:0
+#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_MSB                     MK_SHIFT_CONST(5)
+#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_LSB                     MK_SHIFT_CONST(0)
+#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_WOFFSET                 0x0
+#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SPI_COMMAND2_0_Rx_Clk_TAP_DELAY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SPI_TIMING_REG1_0
+#define SPI_TIMING_REG1_0                       MK_ADDR_CONST(0x8)
+#define SPI_TIMING_REG1_0_SECURE                        0x0
+#define SPI_TIMING_REG1_0_DUAL                  0x0
+#define SPI_TIMING_REG1_0_SCR                   0
+#define SPI_TIMING_REG1_0_SCRREG                        0
+#define SPI_TIMING_REG1_0_WORD_COUNT                    0x1
+#define SPI_TIMING_REG1_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define SPI_TIMING_REG1_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define SPI_TIMING_REG1_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define SPI_TIMING_REG1_0_CS_SETUP_3_SHIFT                      MK_SHIFT_CONST(28)
+#define SPI_TIMING_REG1_0_CS_SETUP_3_FIELD                      MK_FIELD_CONST(0xf, SPI_TIMING_REG1_0_CS_SETUP_3_SHIFT)
+#define SPI_TIMING_REG1_0_CS_SETUP_3_RANGE                      31:28
+#define SPI_TIMING_REG1_0_CS_SETUP_3_MSB                        MK_SHIFT_CONST(31)
+#define SPI_TIMING_REG1_0_CS_SETUP_3_LSB                        MK_SHIFT_CONST(28)
+#define SPI_TIMING_REG1_0_CS_SETUP_3_WOFFSET                    0x0
+#define SPI_TIMING_REG1_0_CS_SETUP_3_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_SETUP_3_DEFAULT_MASK                       MK_MASK_CONST(0xf)
+#define SPI_TIMING_REG1_0_CS_SETUP_3_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_SETUP_3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_SETUP_3_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_SETUP_3_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define SPI_TIMING_REG1_0_CS_HOLD_3_SHIFT                       MK_SHIFT_CONST(24)
+#define SPI_TIMING_REG1_0_CS_HOLD_3_FIELD                       MK_FIELD_CONST(0xf, SPI_TIMING_REG1_0_CS_HOLD_3_SHIFT)
+#define SPI_TIMING_REG1_0_CS_HOLD_3_RANGE                       27:24
+#define SPI_TIMING_REG1_0_CS_HOLD_3_MSB                 MK_SHIFT_CONST(27)
+#define SPI_TIMING_REG1_0_CS_HOLD_3_LSB                 MK_SHIFT_CONST(24)
+#define SPI_TIMING_REG1_0_CS_HOLD_3_WOFFSET                     0x0
+#define SPI_TIMING_REG1_0_CS_HOLD_3_DEFAULT                     MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_HOLD_3_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define SPI_TIMING_REG1_0_CS_HOLD_3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_HOLD_3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_HOLD_3_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_HOLD_3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define SPI_TIMING_REG1_0_CS_SETUP_2_SHIFT                      MK_SHIFT_CONST(20)
+#define SPI_TIMING_REG1_0_CS_SETUP_2_FIELD                      MK_FIELD_CONST(0xf, SPI_TIMING_REG1_0_CS_SETUP_2_SHIFT)
+#define SPI_TIMING_REG1_0_CS_SETUP_2_RANGE                      23:20
+#define SPI_TIMING_REG1_0_CS_SETUP_2_MSB                        MK_SHIFT_CONST(23)
+#define SPI_TIMING_REG1_0_CS_SETUP_2_LSB                        MK_SHIFT_CONST(20)
+#define SPI_TIMING_REG1_0_CS_SETUP_2_WOFFSET                    0x0
+#define SPI_TIMING_REG1_0_CS_SETUP_2_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_SETUP_2_DEFAULT_MASK                       MK_MASK_CONST(0xf)
+#define SPI_TIMING_REG1_0_CS_SETUP_2_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_SETUP_2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_SETUP_2_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_SETUP_2_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define SPI_TIMING_REG1_0_CS_HOLD_2_SHIFT                       MK_SHIFT_CONST(16)
+#define SPI_TIMING_REG1_0_CS_HOLD_2_FIELD                       MK_FIELD_CONST(0xf, SPI_TIMING_REG1_0_CS_HOLD_2_SHIFT)
+#define SPI_TIMING_REG1_0_CS_HOLD_2_RANGE                       19:16
+#define SPI_TIMING_REG1_0_CS_HOLD_2_MSB                 MK_SHIFT_CONST(19)
+#define SPI_TIMING_REG1_0_CS_HOLD_2_LSB                 MK_SHIFT_CONST(16)
+#define SPI_TIMING_REG1_0_CS_HOLD_2_WOFFSET                     0x0
+#define SPI_TIMING_REG1_0_CS_HOLD_2_DEFAULT                     MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_HOLD_2_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define SPI_TIMING_REG1_0_CS_HOLD_2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_HOLD_2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_HOLD_2_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_HOLD_2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define SPI_TIMING_REG1_0_CS_SETUP_1_SHIFT                      MK_SHIFT_CONST(12)
+#define SPI_TIMING_REG1_0_CS_SETUP_1_FIELD                      MK_FIELD_CONST(0xf, SPI_TIMING_REG1_0_CS_SETUP_1_SHIFT)
+#define SPI_TIMING_REG1_0_CS_SETUP_1_RANGE                      15:12
+#define SPI_TIMING_REG1_0_CS_SETUP_1_MSB                        MK_SHIFT_CONST(15)
+#define SPI_TIMING_REG1_0_CS_SETUP_1_LSB                        MK_SHIFT_CONST(12)
+#define SPI_TIMING_REG1_0_CS_SETUP_1_WOFFSET                    0x0
+#define SPI_TIMING_REG1_0_CS_SETUP_1_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_SETUP_1_DEFAULT_MASK                       MK_MASK_CONST(0xf)
+#define SPI_TIMING_REG1_0_CS_SETUP_1_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_SETUP_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_SETUP_1_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_SETUP_1_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define SPI_TIMING_REG1_0_CS_HOLD_1_SHIFT                       MK_SHIFT_CONST(8)
+#define SPI_TIMING_REG1_0_CS_HOLD_1_FIELD                       MK_FIELD_CONST(0xf, SPI_TIMING_REG1_0_CS_HOLD_1_SHIFT)
+#define SPI_TIMING_REG1_0_CS_HOLD_1_RANGE                       11:8
+#define SPI_TIMING_REG1_0_CS_HOLD_1_MSB                 MK_SHIFT_CONST(11)
+#define SPI_TIMING_REG1_0_CS_HOLD_1_LSB                 MK_SHIFT_CONST(8)
+#define SPI_TIMING_REG1_0_CS_HOLD_1_WOFFSET                     0x0
+#define SPI_TIMING_REG1_0_CS_HOLD_1_DEFAULT                     MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_HOLD_1_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define SPI_TIMING_REG1_0_CS_HOLD_1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_HOLD_1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_HOLD_1_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_HOLD_1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define SPI_TIMING_REG1_0_CS_SETUP_0_SHIFT                      MK_SHIFT_CONST(4)
+#define SPI_TIMING_REG1_0_CS_SETUP_0_FIELD                      MK_FIELD_CONST(0xf, SPI_TIMING_REG1_0_CS_SETUP_0_SHIFT)
+#define SPI_TIMING_REG1_0_CS_SETUP_0_RANGE                      7:4
+#define SPI_TIMING_REG1_0_CS_SETUP_0_MSB                        MK_SHIFT_CONST(7)
+#define SPI_TIMING_REG1_0_CS_SETUP_0_LSB                        MK_SHIFT_CONST(4)
+#define SPI_TIMING_REG1_0_CS_SETUP_0_WOFFSET                    0x0
+#define SPI_TIMING_REG1_0_CS_SETUP_0_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_SETUP_0_DEFAULT_MASK                       MK_MASK_CONST(0xf)
+#define SPI_TIMING_REG1_0_CS_SETUP_0_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_SETUP_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_SETUP_0_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_SETUP_0_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define SPI_TIMING_REG1_0_CS_HOLD_0_SHIFT                       MK_SHIFT_CONST(0)
+#define SPI_TIMING_REG1_0_CS_HOLD_0_FIELD                       MK_FIELD_CONST(0xf, SPI_TIMING_REG1_0_CS_HOLD_0_SHIFT)
+#define SPI_TIMING_REG1_0_CS_HOLD_0_RANGE                       3:0
+#define SPI_TIMING_REG1_0_CS_HOLD_0_MSB                 MK_SHIFT_CONST(3)
+#define SPI_TIMING_REG1_0_CS_HOLD_0_LSB                 MK_SHIFT_CONST(0)
+#define SPI_TIMING_REG1_0_CS_HOLD_0_WOFFSET                     0x0
+#define SPI_TIMING_REG1_0_CS_HOLD_0_DEFAULT                     MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_HOLD_0_DEFAULT_MASK                        MK_MASK_CONST(0xf)
+#define SPI_TIMING_REG1_0_CS_HOLD_0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_HOLD_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_HOLD_0_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG1_0_CS_HOLD_0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+// Register SPI_TIMING_REG2_0
+#define SPI_TIMING_REG2_0                       MK_ADDR_CONST(0xc)
+#define SPI_TIMING_REG2_0_SECURE                        0x0
+#define SPI_TIMING_REG2_0_DUAL                  0x0
+#define SPI_TIMING_REG2_0_SCR                   0
+#define SPI_TIMING_REG2_0_SCRREG                        0
+#define SPI_TIMING_REG2_0_WORD_COUNT                    0x1
+#define SPI_TIMING_REG2_0_RESET_VAL                     MK_MASK_CONST(0x20202020)
+#define SPI_TIMING_REG2_0_RESET_MASK                    MK_MASK_CONST(0x3f3f3f3f)
+#define SPI_TIMING_REG2_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_READ_MASK                     MK_MASK_CONST(0x3f3f3f3f)
+#define SPI_TIMING_REG2_0_WRITE_MASK                    MK_MASK_CONST(0x3f3f3f3f)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_SHIFT                     MK_SHIFT_CONST(29)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_FIELD                     MK_FIELD_CONST(0x1, SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_SHIFT)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_RANGE                     29:29
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_MSB                       MK_SHIFT_CONST(29)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_LSB                       MK_SHIFT_CONST(29)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_WOFFSET                   0x0
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_DEFAULT                   MK_MASK_CONST(0x1)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_SHIFT                        MK_SHIFT_CONST(24)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_FIELD                        MK_FIELD_CONST(0x1f, SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_SHIFT)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_RANGE                        28:24
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_MSB                  MK_SHIFT_CONST(28)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_LSB                  MK_SHIFT_CONST(24)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_WOFFSET                      0x0
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_3_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_SHIFT                     MK_SHIFT_CONST(21)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_FIELD                     MK_FIELD_CONST(0x1, SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_SHIFT)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_RANGE                     21:21
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_MSB                       MK_SHIFT_CONST(21)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_LSB                       MK_SHIFT_CONST(21)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_WOFFSET                   0x0
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_DEFAULT                   MK_MASK_CONST(0x1)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_SHIFT                        MK_SHIFT_CONST(16)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_FIELD                        MK_FIELD_CONST(0x1f, SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_SHIFT)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_RANGE                        20:16
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_MSB                  MK_SHIFT_CONST(20)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_LSB                  MK_SHIFT_CONST(16)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_WOFFSET                      0x0
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_2_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_SHIFT                     MK_SHIFT_CONST(13)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_FIELD                     MK_FIELD_CONST(0x1, SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_SHIFT)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_RANGE                     13:13
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_MSB                       MK_SHIFT_CONST(13)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_LSB                       MK_SHIFT_CONST(13)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_WOFFSET                   0x0
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_DEFAULT                   MK_MASK_CONST(0x1)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_SHIFT                        MK_SHIFT_CONST(8)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_FIELD                        MK_FIELD_CONST(0x1f, SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_SHIFT)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_RANGE                        12:8
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_MSB                  MK_SHIFT_CONST(12)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_LSB                  MK_SHIFT_CONST(8)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_WOFFSET                      0x0
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_1_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_SHIFT                     MK_SHIFT_CONST(5)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_FIELD                     MK_FIELD_CONST(0x1, SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_SHIFT)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_RANGE                     5:5
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_MSB                       MK_SHIFT_CONST(5)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_LSB                       MK_SHIFT_CONST(5)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_WOFFSET                   0x0
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_DEFAULT                   MK_MASK_CONST(0x1)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CS_ACTIVE_BETWEEN_PACKETS_0_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_SHIFT                        MK_SHIFT_CONST(0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_FIELD                        MK_FIELD_CONST(0x1f, SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_SHIFT)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_RANGE                        4:0
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_MSB                  MK_SHIFT_CONST(4)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_LSB                  MK_SHIFT_CONST(0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_WOFFSET                      0x0
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_DEFAULT_MASK                 MK_MASK_CONST(0x1f)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SPI_TIMING_REG2_0_CYCLES_BETWEEN_PACKETS_0_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+// Register SPI_TRANSFER_STATUS_0
+#define SPI_TRANSFER_STATUS_0                   MK_ADDR_CONST(0x10)
+#define SPI_TRANSFER_STATUS_0_SECURE                    0x0
+#define SPI_TRANSFER_STATUS_0_DUAL                      0x0
+#define SPI_TRANSFER_STATUS_0_SCR                       0
+#define SPI_TRANSFER_STATUS_0_SCRREG                    0
+#define SPI_TRANSFER_STATUS_0_WORD_COUNT                        0x1
+#define SPI_TRANSFER_STATUS_0_RESET_VAL                         MK_MASK_CONST(0xff0000)
+#define SPI_TRANSFER_STATUS_0_RESET_MASK                        MK_MASK_CONST(0x40ffffff)
+#define SPI_TRANSFER_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SPI_TRANSFER_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_TRANSFER_STATUS_0_READ_MASK                         MK_MASK_CONST(0x40ffffff)
+#define SPI_TRANSFER_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x40ff0000)
+#define SPI_TRANSFER_STATUS_0_RDY_SHIFT                 MK_SHIFT_CONST(30)
+#define SPI_TRANSFER_STATUS_0_RDY_FIELD                 MK_FIELD_CONST(0x1, SPI_TRANSFER_STATUS_0_RDY_SHIFT)
+#define SPI_TRANSFER_STATUS_0_RDY_RANGE                 30:30
+#define SPI_TRANSFER_STATUS_0_RDY_MSB                   MK_SHIFT_CONST(30)
+#define SPI_TRANSFER_STATUS_0_RDY_LSB                   MK_SHIFT_CONST(30)
+#define SPI_TRANSFER_STATUS_0_RDY_WOFFSET                       0x0
+#define SPI_TRANSFER_STATUS_0_RDY_DEFAULT                       MK_MASK_CONST(0x0)
+#define SPI_TRANSFER_STATUS_0_RDY_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define SPI_TRANSFER_STATUS_0_RDY_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_TRANSFER_STATUS_0_RDY_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SPI_TRANSFER_STATUS_0_RDY_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SPI_TRANSFER_STATUS_0_RDY_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define SPI_TRANSFER_STATUS_0_RDY_NOT_READY                     MK_ENUM_CONST(0)
+#define SPI_TRANSFER_STATUS_0_RDY_READY                 MK_ENUM_CONST(1)
+
+#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_SHIFT                        MK_SHIFT_CONST(16)
+#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_FIELD                        MK_FIELD_CONST(0xff, SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_SHIFT)
+#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_RANGE                        23:16
+#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_MSB                  MK_SHIFT_CONST(23)
+#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_LSB                  MK_SHIFT_CONST(16)
+#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_WOFFSET                      0x0
+#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_DEFAULT                      MK_MASK_CONST(0xff)
+#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SPI_TRANSFER_STATUS_0_SLV_IDLE_CNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define SPI_TRANSFER_STATUS_0_BLK_CNT_SHIFT                     MK_SHIFT_CONST(0)
+#define SPI_TRANSFER_STATUS_0_BLK_CNT_FIELD                     MK_FIELD_CONST(0xffff, SPI_TRANSFER_STATUS_0_BLK_CNT_SHIFT)
+#define SPI_TRANSFER_STATUS_0_BLK_CNT_RANGE                     15:0
+#define SPI_TRANSFER_STATUS_0_BLK_CNT_MSB                       MK_SHIFT_CONST(15)
+#define SPI_TRANSFER_STATUS_0_BLK_CNT_LSB                       MK_SHIFT_CONST(0)
+#define SPI_TRANSFER_STATUS_0_BLK_CNT_WOFFSET                   0x0
+#define SPI_TRANSFER_STATUS_0_BLK_CNT_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_TRANSFER_STATUS_0_BLK_CNT_DEFAULT_MASK                      MK_MASK_CONST(0xffff)
+#define SPI_TRANSFER_STATUS_0_BLK_CNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_TRANSFER_STATUS_0_BLK_CNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_TRANSFER_STATUS_0_BLK_CNT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_TRANSFER_STATUS_0_BLK_CNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+// Register SPI_FIFO_STATUS_0
+#define SPI_FIFO_STATUS_0                       MK_ADDR_CONST(0x14)
+#define SPI_FIFO_STATUS_0_SECURE                        0x0
+#define SPI_FIFO_STATUS_0_DUAL                  0x0
+#define SPI_FIFO_STATUS_0_SCR                   0
+#define SPI_FIFO_STATUS_0_SCRREG                        0
+#define SPI_FIFO_STATUS_0_WORD_COUNT                    0x1
+#define SPI_FIFO_STATUS_0_RESET_VAL                     MK_MASK_CONST(0x400005)
+#define SPI_FIFO_STATUS_0_RESET_MASK                    MK_MASK_CONST(0xffffc3ff)
+#define SPI_FIFO_STATUS_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_READ_MASK                     MK_MASK_CONST(0xffffc3ff)
+#define SPI_FIFO_STATUS_0_WRITE_MASK                    MK_MASK_CONST(0xc000c3f0)
+#define SPI_FIFO_STATUS_0_CS_INACTIVE_SHIFT                     MK_SHIFT_CONST(31)
+#define SPI_FIFO_STATUS_0_CS_INACTIVE_FIELD                     MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_CS_INACTIVE_SHIFT)
+#define SPI_FIFO_STATUS_0_CS_INACTIVE_RANGE                     31:31
+#define SPI_FIFO_STATUS_0_CS_INACTIVE_MSB                       MK_SHIFT_CONST(31)
+#define SPI_FIFO_STATUS_0_CS_INACTIVE_LSB                       MK_SHIFT_CONST(31)
+#define SPI_FIFO_STATUS_0_CS_INACTIVE_WOFFSET                   0x0
+#define SPI_FIFO_STATUS_0_CS_INACTIVE_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_CS_INACTIVE_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_CS_INACTIVE_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_CS_INACTIVE_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_CS_INACTIVE_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_CS_INACTIVE_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define SPI_FIFO_STATUS_0_FRAME_END_SHIFT                       MK_SHIFT_CONST(30)
+#define SPI_FIFO_STATUS_0_FRAME_END_FIELD                       MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_FRAME_END_SHIFT)
+#define SPI_FIFO_STATUS_0_FRAME_END_RANGE                       30:30
+#define SPI_FIFO_STATUS_0_FRAME_END_MSB                 MK_SHIFT_CONST(30)
+#define SPI_FIFO_STATUS_0_FRAME_END_LSB                 MK_SHIFT_CONST(30)
+#define SPI_FIFO_STATUS_0_FRAME_END_WOFFSET                     0x0
+#define SPI_FIFO_STATUS_0_FRAME_END_DEFAULT                     MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_FRAME_END_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_FRAME_END_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_FRAME_END_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_FRAME_END_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_FRAME_END_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_SHIFT                      MK_SHIFT_CONST(23)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_FIELD                      MK_FIELD_CONST(0x7f, SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_SHIFT)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_RANGE                      29:23
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_MSB                        MK_SHIFT_CONST(29)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_LSB                        MK_SHIFT_CONST(23)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_WOFFSET                    0x0
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_DEFAULT_MASK                       MK_MASK_CONST(0x7f)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_COUNT_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_SHIFT                     MK_SHIFT_CONST(16)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_FIELD                     MK_FIELD_CONST(0x7f, SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_SHIFT)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_RANGE                     22:16
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_MSB                       MK_SHIFT_CONST(22)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_LSB                       MK_SHIFT_CONST(16)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_WOFFSET                   0x0
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_DEFAULT                   MK_MASK_CONST(0x40)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_DEFAULT_MASK                      MK_MASK_CONST(0x7f)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_COUNT_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_SHIFT                   MK_SHIFT_CONST(15)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_FIELD                   MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_SHIFT)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_RANGE                   15:15
+#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_MSB                     MK_SHIFT_CONST(15)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_LSB                     MK_SHIFT_CONST(15)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_WOFFSET                 0x0
+#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_NOP                     MK_ENUM_CONST(0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FLUSH_FLUSH                   MK_ENUM_CONST(1)
+
+#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_SHIFT                   MK_SHIFT_CONST(14)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_FIELD                   MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_SHIFT)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_RANGE                   14:14
+#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_MSB                     MK_SHIFT_CONST(14)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_LSB                     MK_SHIFT_CONST(14)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_WOFFSET                 0x0
+#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_NOP                     MK_ENUM_CONST(0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FLUSH_FLUSH                   MK_ENUM_CONST(1)
+
+#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_SHIFT                        MK_SHIFT_CONST(9)
+#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_FIELD                        MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_SHIFT)
+#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_RANGE                        9:9
+#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_MSB                  MK_SHIFT_CONST(9)
+#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_LSB                  MK_SHIFT_CONST(9)
+#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_WOFFSET                      0x0
+#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_CS_BOUNDARY_TIMEOUT_INTR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define SPI_FIFO_STATUS_0_ERR_SHIFT                     MK_SHIFT_CONST(8)
+#define SPI_FIFO_STATUS_0_ERR_FIELD                     MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_ERR_SHIFT)
+#define SPI_FIFO_STATUS_0_ERR_RANGE                     8:8
+#define SPI_FIFO_STATUS_0_ERR_MSB                       MK_SHIFT_CONST(8)
+#define SPI_FIFO_STATUS_0_ERR_LSB                       MK_SHIFT_CONST(8)
+#define SPI_FIFO_STATUS_0_ERR_WOFFSET                   0x0
+#define SPI_FIFO_STATUS_0_ERR_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_ERR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_ERR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_ERR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_ERR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_ERR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_ERR_OK                        MK_ENUM_CONST(0)
+#define SPI_FIFO_STATUS_0_ERR_ERROR                     MK_ENUM_CONST(1)
+
+#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_SHIFT                     MK_SHIFT_CONST(7)
+#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_FIELD                     MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_TX_FIFO_OVF_SHIFT)
+#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_RANGE                     7:7
+#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_MSB                       MK_SHIFT_CONST(7)
+#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_LSB                       MK_SHIFT_CONST(7)
+#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_WOFFSET                   0x0
+#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_OK                        MK_ENUM_CONST(0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_OVF_ERROR                     MK_ENUM_CONST(1)
+
+#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_SHIFT                     MK_SHIFT_CONST(6)
+#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_FIELD                     MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_TX_FIFO_UNF_SHIFT)
+#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_RANGE                     6:6
+#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_MSB                       MK_SHIFT_CONST(6)
+#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_LSB                       MK_SHIFT_CONST(6)
+#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_WOFFSET                   0x0
+#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_OK                        MK_ENUM_CONST(0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_UNF_ERROR                     MK_ENUM_CONST(1)
+
+#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_SHIFT                     MK_SHIFT_CONST(5)
+#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_FIELD                     MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_RX_FIFO_OVF_SHIFT)
+#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_RANGE                     5:5
+#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_MSB                       MK_SHIFT_CONST(5)
+#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_LSB                       MK_SHIFT_CONST(5)
+#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_WOFFSET                   0x0
+#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_OK                        MK_ENUM_CONST(0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_OVF_ERROR                     MK_ENUM_CONST(1)
+
+#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_SHIFT                     MK_SHIFT_CONST(4)
+#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_FIELD                     MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_RX_FIFO_UNF_SHIFT)
+#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_RANGE                     4:4
+#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_MSB                       MK_SHIFT_CONST(4)
+#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_LSB                       MK_SHIFT_CONST(4)
+#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_WOFFSET                   0x0
+#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_OK                        MK_ENUM_CONST(0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_UNF_ERROR                     MK_ENUM_CONST(1)
+
+#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_SHIFT                    MK_SHIFT_CONST(3)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_FIELD                    MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_TX_FIFO_FULL_SHIFT)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_RANGE                    3:3
+#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_MSB                      MK_SHIFT_CONST(3)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_LSB                      MK_SHIFT_CONST(3)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_WOFFSET                  0x0
+#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_NOT_FULL                 MK_ENUM_CONST(0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_FULL_FULL                     MK_ENUM_CONST(1)
+
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_SHIFT                   MK_SHIFT_CONST(2)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_FIELD                   MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_SHIFT)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_RANGE                   2:2
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_MSB                     MK_SHIFT_CONST(2)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_LSB                     MK_SHIFT_CONST(2)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_WOFFSET                 0x0
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_DEFAULT                 MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_NOT_EMPTY                       MK_ENUM_CONST(0)
+#define SPI_FIFO_STATUS_0_TX_FIFO_EMPTY_EMPTY                   MK_ENUM_CONST(1)
+
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_SHIFT                    MK_SHIFT_CONST(1)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_FIELD                    MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_RX_FIFO_FULL_SHIFT)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_RANGE                    1:1
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_MSB                      MK_SHIFT_CONST(1)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_LSB                      MK_SHIFT_CONST(1)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_WOFFSET                  0x0
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_NOT_FULL                 MK_ENUM_CONST(0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_FULL_FULL                     MK_ENUM_CONST(1)
+
+#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_SHIFT                   MK_SHIFT_CONST(0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_FIELD                   MK_FIELD_CONST(0x1, SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_SHIFT)
+#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_RANGE                   0:0
+#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_MSB                     MK_SHIFT_CONST(0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_LSB                     MK_SHIFT_CONST(0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_WOFFSET                 0x0
+#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_DEFAULT                 MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_NOT_EMPTY                       MK_ENUM_CONST(0)
+#define SPI_FIFO_STATUS_0_RX_FIFO_EMPTY_EMPTY                   MK_ENUM_CONST(1)
+
+// Register SPI_TX_DATA_0
+#define SPI_TX_DATA_0                   MK_ADDR_CONST(0x18)
+#define SPI_TX_DATA_0_SECURE                    0x0
+#define SPI_TX_DATA_0_DUAL                      0x0
+#define SPI_TX_DATA_0_SCR                       0
+#define SPI_TX_DATA_0_SCRREG                    0
+#define SPI_TX_DATA_0_WORD_COUNT                        0x1
+#define SPI_TX_DATA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SPI_TX_DATA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SPI_TX_DATA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SPI_TX_DATA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_TX_DATA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SPI_TX_DATA_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define SPI_TX_DATA_0_Tx_BUFFER_SHIFT                   MK_SHIFT_CONST(0)
+#define SPI_TX_DATA_0_Tx_BUFFER_FIELD                   MK_FIELD_CONST(0xffffffff, SPI_TX_DATA_0_Tx_BUFFER_SHIFT)
+#define SPI_TX_DATA_0_Tx_BUFFER_RANGE                   31:0
+#define SPI_TX_DATA_0_Tx_BUFFER_MSB                     MK_SHIFT_CONST(31)
+#define SPI_TX_DATA_0_Tx_BUFFER_LSB                     MK_SHIFT_CONST(0)
+#define SPI_TX_DATA_0_Tx_BUFFER_WOFFSET                 0x0
+#define SPI_TX_DATA_0_Tx_BUFFER_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_TX_DATA_0_Tx_BUFFER_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SPI_TX_DATA_0_Tx_BUFFER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_TX_DATA_0_Tx_BUFFER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SPI_TX_DATA_0_Tx_BUFFER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SPI_TX_DATA_0_Tx_BUFFER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SPI_RX_DATA_0
+#define SPI_RX_DATA_0                   MK_ADDR_CONST(0x1c)
+#define SPI_RX_DATA_0_SECURE                    0x0
+#define SPI_RX_DATA_0_DUAL                      0x0
+#define SPI_RX_DATA_0_SCR                       0
+#define SPI_RX_DATA_0_SCRREG                    0
+#define SPI_RX_DATA_0_WORD_COUNT                        0x1
+#define SPI_RX_DATA_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SPI_RX_DATA_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SPI_RX_DATA_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SPI_RX_DATA_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_RX_DATA_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SPI_RX_DATA_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define SPI_RX_DATA_0_Rx_BUFFER_SHIFT                   MK_SHIFT_CONST(0)
+#define SPI_RX_DATA_0_Rx_BUFFER_FIELD                   MK_FIELD_CONST(0xffffffff, SPI_RX_DATA_0_Rx_BUFFER_SHIFT)
+#define SPI_RX_DATA_0_Rx_BUFFER_RANGE                   31:0
+#define SPI_RX_DATA_0_Rx_BUFFER_MSB                     MK_SHIFT_CONST(31)
+#define SPI_RX_DATA_0_Rx_BUFFER_LSB                     MK_SHIFT_CONST(0)
+#define SPI_RX_DATA_0_Rx_BUFFER_WOFFSET                 0x0
+#define SPI_RX_DATA_0_Rx_BUFFER_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_RX_DATA_0_Rx_BUFFER_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SPI_RX_DATA_0_Rx_BUFFER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_RX_DATA_0_Rx_BUFFER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SPI_RX_DATA_0_Rx_BUFFER_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SPI_RX_DATA_0_Rx_BUFFER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SPI_DMA_CTL_0
+#define SPI_DMA_CTL_0                   MK_ADDR_CONST(0x20)
+#define SPI_DMA_CTL_0_SECURE                    0x0
+#define SPI_DMA_CTL_0_DUAL                      0x0
+#define SPI_DMA_CTL_0_SCR                       0
+#define SPI_DMA_CTL_0_SCRREG                    0
+#define SPI_DMA_CTL_0_WORD_COUNT                        0x1
+#define SPI_DMA_CTL_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_RESET_MASK                        MK_MASK_CONST(0xe0198000)
+#define SPI_DMA_CTL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_READ_MASK                         MK_MASK_CONST(0xe0198000)
+#define SPI_DMA_CTL_0_WRITE_MASK                        MK_MASK_CONST(0xe0198000)
+#define SPI_DMA_CTL_0_DMA_EN_SHIFT                      MK_SHIFT_CONST(31)
+#define SPI_DMA_CTL_0_DMA_EN_FIELD                      MK_FIELD_CONST(0x1, SPI_DMA_CTL_0_DMA_EN_SHIFT)
+#define SPI_DMA_CTL_0_DMA_EN_RANGE                      31:31
+#define SPI_DMA_CTL_0_DMA_EN_MSB                        MK_SHIFT_CONST(31)
+#define SPI_DMA_CTL_0_DMA_EN_LSB                        MK_SHIFT_CONST(31)
+#define SPI_DMA_CTL_0_DMA_EN_WOFFSET                    0x0
+#define SPI_DMA_CTL_0_DMA_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_DMA_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define SPI_DMA_CTL_0_DMA_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_DMA_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_DMA_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_DMA_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define SPI_DMA_CTL_0_DMA_EN_DISABLE                    MK_ENUM_CONST(0)
+#define SPI_DMA_CTL_0_DMA_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define SPI_DMA_CTL_0_CONT_SHIFT                        MK_SHIFT_CONST(30)
+#define SPI_DMA_CTL_0_CONT_FIELD                        MK_FIELD_CONST(0x1, SPI_DMA_CTL_0_CONT_SHIFT)
+#define SPI_DMA_CTL_0_CONT_RANGE                        30:30
+#define SPI_DMA_CTL_0_CONT_MSB                  MK_SHIFT_CONST(30)
+#define SPI_DMA_CTL_0_CONT_LSB                  MK_SHIFT_CONST(30)
+#define SPI_DMA_CTL_0_CONT_WOFFSET                      0x0
+#define SPI_DMA_CTL_0_CONT_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_CONT_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define SPI_DMA_CTL_0_CONT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_CONT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_CONT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_CONT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define SPI_DMA_CTL_0_CONT_DISABLE                      MK_ENUM_CONST(0)
+#define SPI_DMA_CTL_0_CONT_ENABLE                       MK_ENUM_CONST(1)
+
+#define SPI_DMA_CTL_0_PAUSE_SHIFT                       MK_SHIFT_CONST(29)
+#define SPI_DMA_CTL_0_PAUSE_FIELD                       MK_FIELD_CONST(0x1, SPI_DMA_CTL_0_PAUSE_SHIFT)
+#define SPI_DMA_CTL_0_PAUSE_RANGE                       29:29
+#define SPI_DMA_CTL_0_PAUSE_MSB                 MK_SHIFT_CONST(29)
+#define SPI_DMA_CTL_0_PAUSE_LSB                 MK_SHIFT_CONST(29)
+#define SPI_DMA_CTL_0_PAUSE_WOFFSET                     0x0
+#define SPI_DMA_CTL_0_PAUSE_DEFAULT                     MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_PAUSE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define SPI_DMA_CTL_0_PAUSE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_PAUSE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_PAUSE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_PAUSE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define SPI_DMA_CTL_0_PAUSE_DISABLE                     MK_ENUM_CONST(0)
+#define SPI_DMA_CTL_0_PAUSE_ENABLE                      MK_ENUM_CONST(1)
+
+#define SPI_DMA_CTL_0_RX_TRIG_SHIFT                     MK_SHIFT_CONST(19)
+#define SPI_DMA_CTL_0_RX_TRIG_FIELD                     MK_FIELD_CONST(0x3, SPI_DMA_CTL_0_RX_TRIG_SHIFT)
+#define SPI_DMA_CTL_0_RX_TRIG_RANGE                     20:19
+#define SPI_DMA_CTL_0_RX_TRIG_MSB                       MK_SHIFT_CONST(20)
+#define SPI_DMA_CTL_0_RX_TRIG_LSB                       MK_SHIFT_CONST(19)
+#define SPI_DMA_CTL_0_RX_TRIG_WOFFSET                   0x0
+#define SPI_DMA_CTL_0_RX_TRIG_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_RX_TRIG_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define SPI_DMA_CTL_0_RX_TRIG_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_RX_TRIG_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_RX_TRIG_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_RX_TRIG_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_DMA_CTL_0_RX_TRIG_TRIG1                     MK_ENUM_CONST(0)
+#define SPI_DMA_CTL_0_RX_TRIG_TRIG4                     MK_ENUM_CONST(1)
+#define SPI_DMA_CTL_0_RX_TRIG_TRIG8                     MK_ENUM_CONST(2)
+#define SPI_DMA_CTL_0_RX_TRIG_TRIG16                    MK_ENUM_CONST(3)
+
+#define SPI_DMA_CTL_0_TX_TRIG_SHIFT                     MK_SHIFT_CONST(15)
+#define SPI_DMA_CTL_0_TX_TRIG_FIELD                     MK_FIELD_CONST(0x3, SPI_DMA_CTL_0_TX_TRIG_SHIFT)
+#define SPI_DMA_CTL_0_TX_TRIG_RANGE                     16:15
+#define SPI_DMA_CTL_0_TX_TRIG_MSB                       MK_SHIFT_CONST(16)
+#define SPI_DMA_CTL_0_TX_TRIG_LSB                       MK_SHIFT_CONST(15)
+#define SPI_DMA_CTL_0_TX_TRIG_WOFFSET                   0x0
+#define SPI_DMA_CTL_0_TX_TRIG_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_TX_TRIG_DEFAULT_MASK                      MK_MASK_CONST(0x3)
+#define SPI_DMA_CTL_0_TX_TRIG_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_TX_TRIG_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_TX_TRIG_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_DMA_CTL_0_TX_TRIG_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_DMA_CTL_0_TX_TRIG_TRIG1                     MK_ENUM_CONST(0)
+#define SPI_DMA_CTL_0_TX_TRIG_TRIG4                     MK_ENUM_CONST(1)
+#define SPI_DMA_CTL_0_TX_TRIG_TRIG8                     MK_ENUM_CONST(2)
+#define SPI_DMA_CTL_0_TX_TRIG_TRIG16                    MK_ENUM_CONST(3)
+
+// Register SPI_DMA_BLK_SIZE_0
+#define SPI_DMA_BLK_SIZE_0                      MK_ADDR_CONST(0x24)
+#define SPI_DMA_BLK_SIZE_0_SECURE                       0x0
+#define SPI_DMA_BLK_SIZE_0_DUAL                         0x0
+#define SPI_DMA_BLK_SIZE_0_SCR                  0
+#define SPI_DMA_BLK_SIZE_0_SCRREG                       0
+#define SPI_DMA_BLK_SIZE_0_WORD_COUNT                   0x1
+#define SPI_DMA_BLK_SIZE_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define SPI_DMA_BLK_SIZE_0_RESET_MASK                   MK_MASK_CONST(0xffff)
+#define SPI_DMA_BLK_SIZE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SPI_DMA_BLK_SIZE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SPI_DMA_BLK_SIZE_0_READ_MASK                    MK_MASK_CONST(0xffff)
+#define SPI_DMA_BLK_SIZE_0_WRITE_MASK                   MK_MASK_CONST(0xffff)
+#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_SHIFT                 MK_SHIFT_CONST(0)
+#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_FIELD                 MK_FIELD_CONST(0xffff, SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_SHIFT)
+#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_RANGE                 15:0
+#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_MSB                   MK_SHIFT_CONST(15)
+#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_LSB                   MK_SHIFT_CONST(0)
+#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_WOFFSET                       0x0
+#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_DEFAULT                       MK_MASK_CONST(0x0)
+#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_DEFAULT_MASK                  MK_MASK_CONST(0xffff)
+#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SPI_DMA_BLK_SIZE_0_DMA_BLOCK_SIZE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+// Reserved address 0x28
+
+// Reserved address 0x2c
+
+// Reserved address 0x30
+
+// Reserved address 0x34
+
+// Reserved address 0x38
+
+// Reserved address 0x3c
+
+// Reserved address 0x40
+
+// Reserved address 0x44
+
+// Reserved address 0x48
+
+// Reserved address 0x4c
+
+// Reserved address 0x50
+
+// Reserved address 0x54
+
+// Reserved address 0x58
+
+// Reserved address 0x5c
+
+// Reserved address 0x60
+
+// Reserved address 0x64
+
+// Reserved address 0x68
+
+// Reserved address 0x6c
+
+// Reserved address 0x70
+
+// Reserved address 0x74
+
+// Reserved address 0x78
+
+// Reserved address 0x7c
+
+// Reserved address 0x80
+
+// Reserved address 0x84
+
+// Reserved address 0x88
+
+// Reserved address 0x8c
+
+// Reserved address 0x90
+
+// Reserved address 0x94
+
+// Reserved address 0x98
+
+// Reserved address 0x9c
+
+// Reserved address 0xa0
+
+// Reserved address 0xa4
+
+// Reserved address 0xa8
+
+// Reserved address 0xac
+
+// Reserved address 0xb0
+
+// Reserved address 0xb4
+
+// Reserved address 0xb8
+
+// Reserved address 0xbc
+
+// Reserved address 0xc0
+
+// Reserved address 0xc4
+
+// Reserved address 0xc8
+
+// Reserved address 0xcc
+
+// Reserved address 0xd0
+
+// Reserved address 0xd4
+
+// Reserved address 0xd8
+
+// Reserved address 0xdc
+
+// Reserved address 0xe0
+
+// Reserved address 0xe4
+
+// Reserved address 0xe8
+
+// Reserved address 0xec
+
+// Reserved address 0xf0
+
+// Reserved address 0xf4
+
+// Reserved address 0xf8
+
+// Reserved address 0xfc
+
+// Reserved address 0x100
+
+// Reserved address 0x104
+
+// Register SPI_TX_FIFO_0
+#define SPI_TX_FIFO_0                   MK_ADDR_CONST(0x108)
+#define SPI_TX_FIFO_0_SECURE                    0x0
+#define SPI_TX_FIFO_0_DUAL                      0x0
+#define SPI_TX_FIFO_0_SCR                       0
+#define SPI_TX_FIFO_0_SCRREG                    0
+#define SPI_TX_FIFO_0_WORD_COUNT                        0x1
+#define SPI_TX_FIFO_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SPI_TX_FIFO_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SPI_TX_FIFO_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_SHIFT                    MK_SHIFT_CONST(0)
+#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_FIELD                    MK_FIELD_CONST(0xffffffff, SPI_TX_FIFO_0_TX_FIFO_REGISTER_SHIFT)
+#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_RANGE                    31:0
+#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_MSB                      MK_SHIFT_CONST(31)
+#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_LSB                      MK_SHIFT_CONST(0)
+#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_WOFFSET                  0x0
+#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SPI_TX_FIFO_0_TX_FIFO_REGISTER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+// Reserved address 0x10c
+
+// Reserved address 0x110
+
+// Reserved address 0x114
+
+// Reserved address 0x118
+
+// Reserved address 0x11c
+
+// Reserved address 0x120
+
+// Reserved address 0x124
+
+// Reserved address 0x128
+
+// Reserved address 0x12c
+
+// Reserved address 0x130
+
+// Reserved address 0x134
+
+// Reserved address 0x138
+
+// Reserved address 0x13c
+
+// Reserved address 0x140
+
+// Reserved address 0x144
+
+// Reserved address 0x148
+
+// Reserved address 0x14c
+
+// Reserved address 0x150
+
+// Reserved address 0x154
+
+// Reserved address 0x158
+
+// Reserved address 0x15c
+
+// Reserved address 0x160
+
+// Reserved address 0x164
+
+// Reserved address 0x168
+
+// Reserved address 0x16c
+
+// Reserved address 0x170
+
+// Reserved address 0x174
+
+// Reserved address 0x178
+
+// Reserved address 0x17c
+
+// Reserved address 0x180
+
+// Reserved address 0x184
+
+// Register SPI_RX_FIFO_0
+#define SPI_RX_FIFO_0                   MK_ADDR_CONST(0x188)
+#define SPI_RX_FIFO_0_SECURE                    0x0
+#define SPI_RX_FIFO_0_DUAL                      0x0
+#define SPI_RX_FIFO_0_SCR                       0
+#define SPI_RX_FIFO_0_SCRREG                    0
+#define SPI_RX_FIFO_0_WORD_COUNT                        0x1
+#define SPI_RX_FIFO_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SPI_RX_FIFO_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SPI_RX_FIFO_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SPI_RX_FIFO_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_RX_FIFO_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SPI_RX_FIFO_0_WRITE_MASK                        MK_MASK_CONST(0xffffffff)
+#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_SHIFT                    MK_SHIFT_CONST(0)
+#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_FIELD                    MK_FIELD_CONST(0xffffffff, SPI_RX_FIFO_0_RX_FIFO_REGISTER_SHIFT)
+#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_RANGE                    31:0
+#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_MSB                      MK_SHIFT_CONST(31)
+#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_LSB                      MK_SHIFT_CONST(0)
+#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_WOFFSET                  0x0
+#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define SPI_RX_FIFO_0_RX_FIFO_REGISTER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+// Register SPI_INTR_MASK_0
+#define SPI_INTR_MASK_0                 MK_ADDR_CONST(0x18c)
+#define SPI_INTR_MASK_0_SECURE                  0x0
+#define SPI_INTR_MASK_0_DUAL                    0x0
+#define SPI_INTR_MASK_0_SCR                     0
+#define SPI_INTR_MASK_0_SCRREG                  0
+#define SPI_INTR_MASK_0_WORD_COUNT                      0x1
+#define SPI_INTR_MASK_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_RESET_MASK                      MK_MASK_CONST(0xfe000200)
+#define SPI_INTR_MASK_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_READ_MASK                       MK_MASK_CONST(0xfe000200)
+#define SPI_INTR_MASK_0_WRITE_MASK                      MK_MASK_CONST(0xfe000200)
+#define SPI_INTR_MASK_0_CS_INTR_MASK_SHIFT                      MK_SHIFT_CONST(31)
+#define SPI_INTR_MASK_0_CS_INTR_MASK_FIELD                      MK_FIELD_CONST(0x1, SPI_INTR_MASK_0_CS_INTR_MASK_SHIFT)
+#define SPI_INTR_MASK_0_CS_INTR_MASK_RANGE                      31:31
+#define SPI_INTR_MASK_0_CS_INTR_MASK_MSB                        MK_SHIFT_CONST(31)
+#define SPI_INTR_MASK_0_CS_INTR_MASK_LSB                        MK_SHIFT_CONST(31)
+#define SPI_INTR_MASK_0_CS_INTR_MASK_WOFFSET                    0x0
+#define SPI_INTR_MASK_0_CS_INTR_MASK_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_CS_INTR_MASK_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define SPI_INTR_MASK_0_CS_INTR_MASK_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_CS_INTR_MASK_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_CS_INTR_MASK_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_CS_INTR_MASK_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define SPI_INTR_MASK_0_CS_INTR_MASK_DISABLE                    MK_ENUM_CONST(0)
+#define SPI_INTR_MASK_0_CS_INTR_MASK_ENABLE                     MK_ENUM_CONST(1)
+
+#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_SHIFT                       MK_SHIFT_CONST(30)
+#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_FIELD                       MK_FIELD_CONST(0x1, SPI_INTR_MASK_0_FRAME_END_INTR_MASK_SHIFT)
+#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_RANGE                       30:30
+#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_MSB                 MK_SHIFT_CONST(30)
+#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_LSB                 MK_SHIFT_CONST(30)
+#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_WOFFSET                     0x0
+#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_DEFAULT                     MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_DISABLE                     MK_ENUM_CONST(0)
+#define SPI_INTR_MASK_0_FRAME_END_INTR_MASK_ENABLE                      MK_ENUM_CONST(1)
+
+#define SPI_INTR_MASK_0_RDY_INTR_MASK_SHIFT                     MK_SHIFT_CONST(29)
+#define SPI_INTR_MASK_0_RDY_INTR_MASK_FIELD                     MK_FIELD_CONST(0x1, SPI_INTR_MASK_0_RDY_INTR_MASK_SHIFT)
+#define SPI_INTR_MASK_0_RDY_INTR_MASK_RANGE                     29:29
+#define SPI_INTR_MASK_0_RDY_INTR_MASK_MSB                       MK_SHIFT_CONST(29)
+#define SPI_INTR_MASK_0_RDY_INTR_MASK_LSB                       MK_SHIFT_CONST(29)
+#define SPI_INTR_MASK_0_RDY_INTR_MASK_WOFFSET                   0x0
+#define SPI_INTR_MASK_0_RDY_INTR_MASK_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_RDY_INTR_MASK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_INTR_MASK_0_RDY_INTR_MASK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_RDY_INTR_MASK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_RDY_INTR_MASK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_RDY_INTR_MASK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_INTR_MASK_0_RDY_INTR_MASK_DISABLE                   MK_ENUM_CONST(0)
+#define SPI_INTR_MASK_0_RDY_INTR_MASK_ENABLE                    MK_ENUM_CONST(1)
+
+#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_SHIFT                     MK_SHIFT_CONST(28)
+#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_FIELD                     MK_FIELD_CONST(0x1, SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_SHIFT)
+#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_RANGE                     28:28
+#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_MSB                       MK_SHIFT_CONST(28)
+#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_LSB                       MK_SHIFT_CONST(28)
+#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_WOFFSET                   0x0
+#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_DISABLE                   MK_ENUM_CONST(0)
+#define SPI_INTR_MASK_0_TX_FIFO_OVF_INTR_MASK_ENABLE                    MK_ENUM_CONST(1)
+
+#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_SHIFT                     MK_SHIFT_CONST(27)
+#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_FIELD                     MK_FIELD_CONST(0x1, SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_SHIFT)
+#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_RANGE                     27:27
+#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_MSB                       MK_SHIFT_CONST(27)
+#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_LSB                       MK_SHIFT_CONST(27)
+#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_WOFFSET                   0x0
+#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_DISABLE                   MK_ENUM_CONST(0)
+#define SPI_INTR_MASK_0_TX_FIFO_UNF_INTR_MASK_ENABLE                    MK_ENUM_CONST(1)
+
+#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_SHIFT                     MK_SHIFT_CONST(26)
+#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_FIELD                     MK_FIELD_CONST(0x1, SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_SHIFT)
+#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_RANGE                     26:26
+#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_MSB                       MK_SHIFT_CONST(26)
+#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_LSB                       MK_SHIFT_CONST(26)
+#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_WOFFSET                   0x0
+#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_DISABLE                   MK_ENUM_CONST(0)
+#define SPI_INTR_MASK_0_RX_FIFO_OVF_INTR_MASK_ENABLE                    MK_ENUM_CONST(1)
+
+#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_SHIFT                     MK_SHIFT_CONST(25)
+#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_FIELD                     MK_FIELD_CONST(0x1, SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_SHIFT)
+#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_RANGE                     25:25
+#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_MSB                       MK_SHIFT_CONST(25)
+#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_LSB                       MK_SHIFT_CONST(25)
+#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_WOFFSET                   0x0
+#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_DISABLE                   MK_ENUM_CONST(0)
+#define SPI_INTR_MASK_0_RX_FIFO_UNF_INTR_MASK_ENABLE                    MK_ENUM_CONST(1)
+
+#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_SHIFT                     MK_SHIFT_CONST(9)
+#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_FIELD                     MK_FIELD_CONST(0x1, SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_SHIFT)
+#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_RANGE                     9:9
+#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_MSB                       MK_SHIFT_CONST(9)
+#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_LSB                       MK_SHIFT_CONST(9)
+#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_WOFFSET                   0x0
+#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_DISABLE                   MK_ENUM_CONST(0)
+#define SPI_INTR_MASK_0_CS_BOUNDARY_TIMEOUT_INTR_MASK_ENABLE                    MK_ENUM_CONST(1)
+
+// Register SPI_SPARE_CTLR_0
+#define SPI_SPARE_CTLR_0                        MK_ADDR_CONST(0x190)
+#define SPI_SPARE_CTLR_0_SECURE                         0x0
+#define SPI_SPARE_CTLR_0_DUAL                   0x0
+#define SPI_SPARE_CTLR_0_SCR                    0
+#define SPI_SPARE_CTLR_0_SCRREG                         0
+#define SPI_SPARE_CTLR_0_WORD_COUNT                     0x1
+#define SPI_SPARE_CTLR_0_RESET_VAL                      MK_MASK_CONST(0xfff0000)
+#define SPI_SPARE_CTLR_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define SPI_SPARE_CTLR_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define SPI_SPARE_CTLR_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define SPI_SPARE_CTLR_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define SPI_SPARE_CTLR_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_SHIFT                     MK_SHIFT_CONST(24)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_FIELD                     MK_FIELD_CONST(0xff, SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_SHIFT)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_RANGE                     31:24
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_MSB                       MK_SHIFT_CONST(31)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_LSB                       MK_SHIFT_CONST(24)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_WOFFSET                   0x0
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_DEFAULT                   MK_MASK_CONST(0xf)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE4_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_SHIFT                     MK_SHIFT_CONST(16)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_FIELD                     MK_FIELD_CONST(0xff, SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_SHIFT)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_RANGE                     23:16
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_MSB                       MK_SHIFT_CONST(23)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_LSB                       MK_SHIFT_CONST(16)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_WOFFSET                   0x0
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_DEFAULT                   MK_MASK_CONST(0xff)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE3_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_SHIFT                     MK_SHIFT_CONST(8)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_FIELD                     MK_FIELD_CONST(0xff, SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_SHIFT)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_RANGE                     15:8
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_MSB                       MK_SHIFT_CONST(15)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_LSB                       MK_SHIFT_CONST(8)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_WOFFSET                   0x0
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE2_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_SHIFT                     MK_SHIFT_CONST(0)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_FIELD                     MK_FIELD_CONST(0xff, SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_SHIFT)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_RANGE                     7:0
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_MSB                       MK_SHIFT_CONST(7)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_LSB                       MK_SHIFT_CONST(0)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_WOFFSET                   0x0
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_DEFAULT_MASK                      MK_MASK_CONST(0xff)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_SPARE_CTLR_0_SPARE_CONTROL_REGISTER_BYTE1_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+// Register SPI_MISC_0
+#define SPI_MISC_0                      MK_ADDR_CONST(0x194)
+#define SPI_MISC_0_SECURE                       0x0
+#define SPI_MISC_0_DUAL                         0x0
+#define SPI_MISC_0_SCR                  0
+#define SPI_MISC_0_SCRREG                       0
+#define SPI_MISC_0_WORD_COUNT                   0x1
+#define SPI_MISC_0_RESET_VAL                    MK_MASK_CONST(0x80000000)
+#define SPI_MISC_0_RESET_MASK                   MK_MASK_CONST(0xc0000000)
+#define SPI_MISC_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SPI_MISC_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SPI_MISC_0_READ_MASK                    MK_MASK_CONST(0xc0000000)
+#define SPI_MISC_0_WRITE_MASK                   MK_MASK_CONST(0xc0000000)
+#define SPI_MISC_0_CLKEN_OVERRIDE_SHIFT                 MK_SHIFT_CONST(31)
+#define SPI_MISC_0_CLKEN_OVERRIDE_FIELD                 MK_FIELD_CONST(0x1, SPI_MISC_0_CLKEN_OVERRIDE_SHIFT)
+#define SPI_MISC_0_CLKEN_OVERRIDE_RANGE                 31:31
+#define SPI_MISC_0_CLKEN_OVERRIDE_MSB                   MK_SHIFT_CONST(31)
+#define SPI_MISC_0_CLKEN_OVERRIDE_LSB                   MK_SHIFT_CONST(31)
+#define SPI_MISC_0_CLKEN_OVERRIDE_WOFFSET                       0x0
+#define SPI_MISC_0_CLKEN_OVERRIDE_DEFAULT                       MK_MASK_CONST(0x1)
+#define SPI_MISC_0_CLKEN_OVERRIDE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define SPI_MISC_0_CLKEN_OVERRIDE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_MISC_0_CLKEN_OVERRIDE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SPI_MISC_0_CLKEN_OVERRIDE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define SPI_MISC_0_CLKEN_OVERRIDE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define SPI_MISC_0_CLKEN_OVERRIDE__PROD                 MK_ENUM_CONST(0)
+
+#define SPI_MISC_0_EXT_CLK_EN_SHIFT                     MK_SHIFT_CONST(30)
+#define SPI_MISC_0_EXT_CLK_EN_FIELD                     MK_FIELD_CONST(0x1, SPI_MISC_0_EXT_CLK_EN_SHIFT)
+#define SPI_MISC_0_EXT_CLK_EN_RANGE                     30:30
+#define SPI_MISC_0_EXT_CLK_EN_MSB                       MK_SHIFT_CONST(30)
+#define SPI_MISC_0_EXT_CLK_EN_LSB                       MK_SHIFT_CONST(30)
+#define SPI_MISC_0_EXT_CLK_EN_WOFFSET                   0x0
+#define SPI_MISC_0_EXT_CLK_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_MISC_0_EXT_CLK_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_MISC_0_EXT_CLK_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_MISC_0_EXT_CLK_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_MISC_0_EXT_CLK_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_MISC_0_EXT_CLK_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+// Register SPI_FATAL_INTR_EN_0
+#define SPI_FATAL_INTR_EN_0                     MK_ADDR_CONST(0x198)
+#define SPI_FATAL_INTR_EN_0_SECURE                      0x0
+#define SPI_FATAL_INTR_EN_0_DUAL                        0x0
+#define SPI_FATAL_INTR_EN_0_SCR                         0
+#define SPI_FATAL_INTR_EN_0_SCRREG                      0
+#define SPI_FATAL_INTR_EN_0_WORD_COUNT                  0x1
+#define SPI_FATAL_INTR_EN_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_RESET_MASK                  MK_MASK_CONST(0xde000200)
+#define SPI_FATAL_INTR_EN_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_READ_MASK                   MK_MASK_CONST(0xde000200)
+#define SPI_FATAL_INTR_EN_0_WRITE_MASK                  MK_MASK_CONST(0xde000200)
+#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_SHIFT                      MK_SHIFT_CONST(31)
+#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_FIELD                      MK_FIELD_CONST(0x1, SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_SHIFT)
+#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_RANGE                      31:31
+#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_MSB                        MK_SHIFT_CONST(31)
+#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_LSB                        MK_SHIFT_CONST(31)
+#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_WOFFSET                    0x0
+#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_DISABLE                    MK_ENUM_CONST(0)
+#define SPI_FATAL_INTR_EN_0_CS_FATAL_INTR_EN_ENABLE                     MK_ENUM_CONST(1)
+
+#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_SHIFT                       MK_SHIFT_CONST(30)
+#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_FIELD                       MK_FIELD_CONST(0x1, SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_SHIFT)
+#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_RANGE                       30:30
+#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_MSB                 MK_SHIFT_CONST(30)
+#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_LSB                 MK_SHIFT_CONST(30)
+#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_WOFFSET                     0x0
+#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_DISABLE                     MK_ENUM_CONST(0)
+#define SPI_FATAL_INTR_EN_0_FRAME_END_FATAL_INTR_EN_ENABLE                      MK_ENUM_CONST(1)
+
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_SHIFT                     MK_SHIFT_CONST(28)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_FIELD                     MK_FIELD_CONST(0x1, SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_SHIFT)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_RANGE                     28:28
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_MSB                       MK_SHIFT_CONST(28)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_LSB                       MK_SHIFT_CONST(28)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_WOFFSET                   0x0
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_DISABLE                   MK_ENUM_CONST(0)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_OVF_FATAL_INTR_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_SHIFT                     MK_SHIFT_CONST(27)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_FIELD                     MK_FIELD_CONST(0x1, SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_SHIFT)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_RANGE                     27:27
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_MSB                       MK_SHIFT_CONST(27)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_LSB                       MK_SHIFT_CONST(27)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_WOFFSET                   0x0
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_DISABLE                   MK_ENUM_CONST(0)
+#define SPI_FATAL_INTR_EN_0_TX_FIFO_UNF_FATAL_INTR_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_SHIFT                     MK_SHIFT_CONST(26)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_FIELD                     MK_FIELD_CONST(0x1, SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_SHIFT)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_RANGE                     26:26
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_MSB                       MK_SHIFT_CONST(26)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_LSB                       MK_SHIFT_CONST(26)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_WOFFSET                   0x0
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_DISABLE                   MK_ENUM_CONST(0)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_OVF_FATAL_INTR_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_SHIFT                     MK_SHIFT_CONST(25)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_FIELD                     MK_FIELD_CONST(0x1, SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_SHIFT)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_RANGE                     25:25
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_MSB                       MK_SHIFT_CONST(25)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_LSB                       MK_SHIFT_CONST(25)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_WOFFSET                   0x0
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_DISABLE                   MK_ENUM_CONST(0)
+#define SPI_FATAL_INTR_EN_0_RX_FIFO_UNF_FATAL_INTR_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_SHIFT                     MK_SHIFT_CONST(9)
+#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_FIELD                     MK_FIELD_CONST(0x1, SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_SHIFT)
+#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_RANGE                     9:9
+#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_MSB                       MK_SHIFT_CONST(9)
+#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_LSB                       MK_SHIFT_CONST(9)
+#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_WOFFSET                   0x0
+#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_DISABLE                   MK_ENUM_CONST(0)
+#define SPI_FATAL_INTR_EN_0_CS_BOUNDARY_TIMEOUT_FATAL_INTR_EN_ENABLE                    MK_ENUM_CONST(1)
+
+// Register SPI_CS_BOUNDARY_TIMEOUT_0
+#define SPI_CS_BOUNDARY_TIMEOUT_0                       MK_ADDR_CONST(0x19c)
+#define SPI_CS_BOUNDARY_TIMEOUT_0_SECURE                        0x0
+#define SPI_CS_BOUNDARY_TIMEOUT_0_DUAL                  0x0
+#define SPI_CS_BOUNDARY_TIMEOUT_0_SCR                   0
+#define SPI_CS_BOUNDARY_TIMEOUT_0_SCRREG                        0
+#define SPI_CS_BOUNDARY_TIMEOUT_0_WORD_COUNT                    0x1
+#define SPI_CS_BOUNDARY_TIMEOUT_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define SPI_CS_BOUNDARY_TIMEOUT_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define SPI_CS_BOUNDARY_TIMEOUT_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define SPI_CS_BOUNDARY_TIMEOUT_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define SPI_CS_BOUNDARY_TIMEOUT_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define SPI_CS_BOUNDARY_TIMEOUT_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_SHIFT                   MK_SHIFT_CONST(0)
+#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_FIELD                   MK_FIELD_CONST(0xffffffff, SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_SHIFT)
+#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_RANGE                   31:0
+#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_MSB                     MK_SHIFT_CONST(31)
+#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_LSB                     MK_SHIFT_CONST(0)
+#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_WOFFSET                 0x0
+#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_DEFAULT_MASK                    MK_MASK_CONST(0xffffffff)
+#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define SPI_CS_BOUNDARY_TIMEOUT_0_TIMEOUT_VALUE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+// Register SPI_TIMEOUT_BOUNDARY_STATUS_0
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0                   MK_ADDR_CONST(0x1a0)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_SECURE                    0x0
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_DUAL                      0x0
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_SCR                       0
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_SCRREG                    0
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_WORD_COUNT                        0x1
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_SHIFT                        MK_SHIFT_CONST(28)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_FIELD                        MK_FIELD_CONST(0xf, SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_SHIFT)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_RANGE                        31:28
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_MSB                  MK_SHIFT_CONST(31)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_LSB                  MK_SHIFT_CONST(28)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_WOFFSET                      0x0
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_DEFAULT_MASK                 MK_MASK_CONST(0xf)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_PADDED_BYTES_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_SHIFT                      MK_SHIFT_CONST(0)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_FIELD                      MK_FIELD_CONST(0xfffffff, SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_SHIFT)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_RANGE                      27:0
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_MSB                        MK_SHIFT_CONST(27)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_LSB                        MK_SHIFT_CONST(0)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_WOFFSET                    0x0
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_DEFAULT_MASK                       MK_MASK_CONST(0xfffffff)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_STATUS_0_NUM_OF_PACKETS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+// Register SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0                      MK_ADDR_CONST(0x1a4)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_SECURE                       0x0
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_DUAL                         0x0
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_SCR                  0
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_SCRREG                       0
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_WORD_COUNT                   0x1
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_RESET_MASK                   MK_MASK_CONST(0x7f010f)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_READ_MASK                    MK_MASK_CONST(0x7f010f)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_WRITE_MASK                   MK_MASK_CONST(0x10c)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_SHIFT                        MK_SHIFT_CONST(16)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_FIELD                        MK_FIELD_CONST(0x7f, SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_SHIFT)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_RANGE                        22:16
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_MSB                  MK_SHIFT_CONST(22)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_LSB                  MK_SHIFT_CONST(16)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_WOFFSET                      0x0
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_DEFAULT                      MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_DEFAULT_MASK                 MK_MASK_CONST(0x7f)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_COUNT_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_SHIFT                     MK_SHIFT_CONST(8)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_FIELD                     MK_FIELD_CONST(0x1, SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_SHIFT)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_RANGE                     8:8
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_MSB                       MK_SHIFT_CONST(8)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_LSB                       MK_SHIFT_CONST(8)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_WOFFSET                   0x0
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_DEFAULT                   MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_NOP                       MK_ENUM_CONST(0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FLUSH_FLUSH                     MK_ENUM_CONST(1)
+
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_SHIFT                       MK_SHIFT_CONST(3)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_FIELD                       MK_FIELD_CONST(0x1, SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_SHIFT)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_RANGE                       3:3
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_MSB                 MK_SHIFT_CONST(3)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_LSB                 MK_SHIFT_CONST(3)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_WOFFSET                     0x0
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_DEFAULT                     MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_OK                  MK_ENUM_CONST(0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_OVF_ERROR                       MK_ENUM_CONST(1)
+
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_SHIFT                       MK_SHIFT_CONST(2)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_FIELD                       MK_FIELD_CONST(0x1, SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_SHIFT)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_RANGE                       2:2
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_MSB                 MK_SHIFT_CONST(2)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_LSB                 MK_SHIFT_CONST(2)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_WOFFSET                     0x0
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_DEFAULT                     MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_OK                  MK_ENUM_CONST(0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_UNF_ERROR                       MK_ENUM_CONST(1)
+
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_SHIFT                      MK_SHIFT_CONST(1)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_FIELD                      MK_FIELD_CONST(0x1, SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_SHIFT)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_RANGE                      1:1
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_MSB                        MK_SHIFT_CONST(1)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_LSB                        MK_SHIFT_CONST(1)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_WOFFSET                    0x0
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_DEFAULT                    MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_NOT_FULL                   MK_ENUM_CONST(0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_FULL_FULL                       MK_ENUM_CONST(1)
+
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_SHIFT                     MK_SHIFT_CONST(0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_FIELD                     MK_FIELD_CONST(0x1, SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_SHIFT)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_RANGE                     0:0
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_MSB                       MK_SHIFT_CONST(0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_LSB                       MK_SHIFT_CONST(0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_WOFFSET                   0x0
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_DEFAULT                   MK_MASK_CONST(0x1)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_NOT_EMPTY                 MK_ENUM_CONST(0)
+#define SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0_TIMEOUT_FIFO_EMPTY_EMPTY                     MK_ENUM_CONST(1)
+
+// Reserved address 0x1a8
+
+// Reserved address 0x1ac
+
+// Reserved address 0x1b0
+
+// Reserved address 0x1b4
+
+// Reserved address 0x1b8
+
+// Reserved address 0x1bc
+
+// Reserved address 0x1c0
+
+// Reserved address 0x1c4
+
+// Reserved address 0x1c8
+
+// Reserved address 0x1cc
+
+// Reserved address 0x1d0
+
+// Reserved address 0x1d4
+
+// Reserved address 0x1d8
+
+// Reserved address 0x1dc
+
+// Reserved address 0x1e0
+
+// Reserved address 0x1e4
+
+// Reserved address 0x1e8
+
+// Reserved address 0x1ec
+
+// Reserved address 0x1f0
+
+// Reserved address 0x1f4
+
+// Reserved address 0x1f8
+
+// Reserved address 0x1fc
+
+// Reserved address 0x200
+
+// Reserved address 0x204
+
+// Reserved address 0x208
+
+// Reserved address 0x20c
+
+// Reserved address 0x210
+
+// Reserved address 0x214
+
+// Reserved address 0x218
+
+// Reserved address 0x21c
+
+// Reserved address 0x220
+
+// Reserved address 0x224
+
+// Reserved address 0x228
+
+// Reserved address 0x22c
+
+// Reserved address 0x230
+
+// Reserved address 0x234
+
+// Reserved address 0x238
+
+// Reserved address 0x23c
+
+// Reserved address 0x240
+
+// Reserved address 0x244
+
+// Reserved address 0x248
+
+// Reserved address 0x24c
+
+// Reserved address 0x250
+
+// Reserved address 0x254
+
+// Reserved address 0x258
+
+// Reserved address 0x25c
+
+// Reserved address 0x260
+
+// Reserved address 0x264
+
+// Reserved address 0x268
+
+// Reserved address 0x26c
+
+// Reserved address 0x270
+
+// Reserved address 0x274
+
+// Reserved address 0x278
+
+// Reserved address 0x27c
+
+// Reserved address 0x280
+
+// Reserved address 0x284
+
+//
+// REGISTER LIST
+//
+#define LIST_ARSPI_REGS(_op_) \
+_op_(SPI_COMMAND_0) \
+_op_(SPI_COMMAND2_0) \
+_op_(SPI_TIMING_REG1_0) \
+_op_(SPI_TIMING_REG2_0) \
+_op_(SPI_TRANSFER_STATUS_0) \
+_op_(SPI_FIFO_STATUS_0) \
+_op_(SPI_TX_DATA_0) \
+_op_(SPI_RX_DATA_0) \
+_op_(SPI_DMA_CTL_0) \
+_op_(SPI_DMA_BLK_SIZE_0) \
+_op_(SPI_TX_FIFO_0) \
+_op_(SPI_RX_FIFO_0) \
+_op_(SPI_INTR_MASK_0) \
+_op_(SPI_SPARE_CTLR_0) \
+_op_(SPI_MISC_0) \
+_op_(SPI_FATAL_INTR_EN_0) \
+_op_(SPI_CS_BOUNDARY_TIMEOUT_0) \
+_op_(SPI_TIMEOUT_BOUNDARY_STATUS_0) \
+_op_(SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0) \
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_SPI        0x00000000
+
+//
+// ARSPI REGISTER BANKS
+//
+
+#define SPI0_FIRST_REG 0x0000 // SPI_COMMAND_0
+#define SPI0_LAST_REG 0x0024 // SPI_DMA_BLK_SIZE_0
+#define SPI1_FIRST_REG 0x0108 // SPI_TX_FIFO_0
+#define SPI1_LAST_REG 0x0108 // SPI_TX_FIFO_0
+#define SPI2_FIRST_REG 0x0188 // SPI_RX_FIFO_0
+#define SPI2_LAST_REG 0x01a4 // SPI_TIMEOUT_BOUNDARY_FIFO_STATUS_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARSPI_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/artimer.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/artimer.h
new file mode 100644
index 0000000..7931c91
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/artimer.h
@@ -0,0 +1,194 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARTIMER_H_INC
+#define ARTIMER_H_INC
+#define NV_MOBILE_ARTIMER_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARTIMER_H_SCRREG_NOMENCLATURE INFERRED
+
+
+// Register TIMER_TMR_PTV_0
+#define TIMER_TMR_PTV_0                 MK_ADDR_CONST(0x0)
+#define TIMER_TMR_PTV_0_SECURE                  0x0
+#define TIMER_TMR_PTV_0_DUAL                    0x0
+#define TIMER_TMR_PTV_0_SCR                     0
+#define TIMER_TMR_PTV_0_SCRREG                  0
+#define TIMER_TMR_PTV_0_WORD_COUNT                      0x1
+#define TIMER_TMR_PTV_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_RESET_MASK                      MK_MASK_CONST(0xdfffffff)
+#define TIMER_TMR_PTV_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_READ_MASK                       MK_MASK_CONST(0xdfffffff)
+#define TIMER_TMR_PTV_0_WRITE_MASK                      MK_MASK_CONST(0xdfffffff)
+#define TIMER_TMR_PTV_0_EN_SHIFT                        MK_SHIFT_CONST(31)
+#define TIMER_TMR_PTV_0_EN_FIELD                        MK_FIELD_CONST(0x1, TIMER_TMR_PTV_0_EN_SHIFT)
+#define TIMER_TMR_PTV_0_EN_RANGE                        31:31
+#define TIMER_TMR_PTV_0_EN_MSB                  MK_SHIFT_CONST(31)
+#define TIMER_TMR_PTV_0_EN_LSB                  MK_SHIFT_CONST(31)
+#define TIMER_TMR_PTV_0_EN_WOFFSET                      0x0
+#define TIMER_TMR_PTV_0_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define TIMER_TMR_PTV_0_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define TIMER_TMR_PTV_0_EN_DISABLE                      MK_ENUM_CONST(0)
+#define TIMER_TMR_PTV_0_EN_ENABLE                       MK_ENUM_CONST(1)
+
+#define TIMER_TMR_PTV_0_PER_SHIFT                       MK_SHIFT_CONST(30)
+#define TIMER_TMR_PTV_0_PER_FIELD                       MK_FIELD_CONST(0x1, TIMER_TMR_PTV_0_PER_SHIFT)
+#define TIMER_TMR_PTV_0_PER_RANGE                       30:30
+#define TIMER_TMR_PTV_0_PER_MSB                 MK_SHIFT_CONST(30)
+#define TIMER_TMR_PTV_0_PER_LSB                 MK_SHIFT_CONST(30)
+#define TIMER_TMR_PTV_0_PER_WOFFSET                     0x0
+#define TIMER_TMR_PTV_0_PER_DEFAULT                     MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_PER_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TIMER_TMR_PTV_0_PER_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_PER_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_PER_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_PER_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TIMER_TMR_PTV_0_PER_DISABLE                     MK_ENUM_CONST(0)
+#define TIMER_TMR_PTV_0_PER_ENABLE                      MK_ENUM_CONST(1)
+
+#define TIMER_TMR_PTV_0_TMR_PTV_SHIFT                   MK_SHIFT_CONST(0)
+#define TIMER_TMR_PTV_0_TMR_PTV_FIELD                   MK_FIELD_CONST(0x1fffffff, TIMER_TMR_PTV_0_TMR_PTV_SHIFT)
+#define TIMER_TMR_PTV_0_TMR_PTV_RANGE                   28:0
+#define TIMER_TMR_PTV_0_TMR_PTV_MSB                     MK_SHIFT_CONST(28)
+#define TIMER_TMR_PTV_0_TMR_PTV_LSB                     MK_SHIFT_CONST(0)
+#define TIMER_TMR_PTV_0_TMR_PTV_WOFFSET                 0x0
+#define TIMER_TMR_PTV_0_TMR_PTV_DEFAULT                 MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_TMR_PTV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
+#define TIMER_TMR_PTV_0_TMR_PTV_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_TMR_PTV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_TMR_PTV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define TIMER_TMR_PTV_0_TMR_PTV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register TIMER_TMR_PCR_0
+#define TIMER_TMR_PCR_0                 MK_ADDR_CONST(0x4)
+#define TIMER_TMR_PCR_0_SECURE                  0x0
+#define TIMER_TMR_PCR_0_DUAL                    0x0
+#define TIMER_TMR_PCR_0_SCR                     0
+#define TIMER_TMR_PCR_0_SCRREG                  0
+#define TIMER_TMR_PCR_0_WORD_COUNT                      0x1
+#define TIMER_TMR_PCR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_RESET_MASK                      MK_MASK_CONST(0x5fffffff)
+#define TIMER_TMR_PCR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_READ_MASK                       MK_MASK_CONST(0x5fffffff)
+#define TIMER_TMR_PCR_0_WRITE_MASK                      MK_MASK_CONST(0x40000000)
+#define TIMER_TMR_PCR_0_INTR_CLR_SHIFT                  MK_SHIFT_CONST(30)
+#define TIMER_TMR_PCR_0_INTR_CLR_FIELD                  MK_FIELD_CONST(0x1, TIMER_TMR_PCR_0_INTR_CLR_SHIFT)
+#define TIMER_TMR_PCR_0_INTR_CLR_RANGE                  30:30
+#define TIMER_TMR_PCR_0_INTR_CLR_MSB                    MK_SHIFT_CONST(30)
+#define TIMER_TMR_PCR_0_INTR_CLR_LSB                    MK_SHIFT_CONST(30)
+#define TIMER_TMR_PCR_0_INTR_CLR_WOFFSET                        0x0
+#define TIMER_TMR_PCR_0_INTR_CLR_DEFAULT                        MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_INTR_CLR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define TIMER_TMR_PCR_0_INTR_CLR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_INTR_CLR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_INTR_CLR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_INTR_CLR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define TIMER_TMR_PCR_0_TMR_PCV_SHIFT                   MK_SHIFT_CONST(0)
+#define TIMER_TMR_PCR_0_TMR_PCV_FIELD                   MK_FIELD_CONST(0x1fffffff, TIMER_TMR_PCR_0_TMR_PCV_SHIFT)
+#define TIMER_TMR_PCR_0_TMR_PCV_RANGE                   28:0
+#define TIMER_TMR_PCR_0_TMR_PCV_MSB                     MK_SHIFT_CONST(28)
+#define TIMER_TMR_PCR_0_TMR_PCV_LSB                     MK_SHIFT_CONST(0)
+#define TIMER_TMR_PCR_0_TMR_PCV_WOFFSET                 0x0
+#define TIMER_TMR_PCR_0_TMR_PCV_DEFAULT                 MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_TMR_PCV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
+#define TIMER_TMR_PCR_0_TMR_PCV_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_TMR_PCV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_TMR_PCV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define TIMER_TMR_PCR_0_TMR_PCV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARTIMER_REGS(_op_) \
+_op_(TIMER_TMR_PTV_0) \
+_op_(TIMER_TMR_PCR_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_TIMER      0x00000000
+
+//
+// ARTIMER REGISTER BANKS
+//
+
+#define TIMER0_FIRST_REG 0x0000 // TIMER_TMR_PTV_0
+#define TIMER0_LAST_REG 0x0004 // TIMER_TMR_PCR_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARTIMER_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/artke_top.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/artke_top.h
new file mode 100644
index 0000000..cd5847d
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/artke_top.h
@@ -0,0 +1,5156 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARTKE_TOP_H_INC
+#define ARTKE_TOP_H_INC
+#define NV_MOBILE_ARTKE_TOP_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARTKE_TOP_H_SCRREG_NOMENCLATURE EXACT
+
+
+// Register TKE_TOP_SHARED_TKETSC0_0
+#define TKE_TOP_SHARED_TKETSC0_0                        MK_ADDR_CONST(0x0)
+#define TKE_TOP_SHARED_TKETSC0_0_SECURE                         0x0
+#define TKE_TOP_SHARED_TKETSC0_0_DUAL                   0x0
+#define TKE_TOP_SHARED_TKETSC0_0_SCR                    TKESCR_0
+#define TKE_TOP_SHARED_TKETSC0_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKETSC0_0_WORD_COUNT                     0x1
+#define TKE_TOP_SHARED_TKETSC0_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKETSC0_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKETSC0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKETSC0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKETSC0_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKETSC0_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKETSC0_0_CV_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKETSC0_0_CV_FIELD                       MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKETSC0_0_CV_SHIFT)
+#define TKE_TOP_SHARED_TKETSC0_0_CV_RANGE                       31:0
+#define TKE_TOP_SHARED_TKETSC0_0_CV_MSB                 MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKETSC0_0_CV_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKETSC0_0_CV_WOFFSET                     0x0
+#define TKE_TOP_SHARED_TKETSC0_0_CV_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKETSC0_0_CV_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKETSC0_0_CV_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKETSC0_0_CV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKETSC0_0_CV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKETSC0_0_CV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKETSC1_0
+#define TKE_TOP_SHARED_TKETSC1_0                        MK_ADDR_CONST(0x4)
+#define TKE_TOP_SHARED_TKETSC1_0_SECURE                         0x0
+#define TKE_TOP_SHARED_TKETSC1_0_DUAL                   0x0
+#define TKE_TOP_SHARED_TKETSC1_0_SCR                    TKESCR_0
+#define TKE_TOP_SHARED_TKETSC1_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKETSC1_0_WORD_COUNT                     0x1
+#define TKE_TOP_SHARED_TKETSC1_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKETSC1_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKETSC1_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKETSC1_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKETSC1_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKETSC1_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKETSC1_0_CV_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKETSC1_0_CV_FIELD                       MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKETSC1_0_CV_SHIFT)
+#define TKE_TOP_SHARED_TKETSC1_0_CV_RANGE                       31:0
+#define TKE_TOP_SHARED_TKETSC1_0_CV_MSB                 MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKETSC1_0_CV_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKETSC1_0_CV_WOFFSET                     0x0
+#define TKE_TOP_SHARED_TKETSC1_0_CV_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKETSC1_0_CV_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKETSC1_0_CV_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKETSC1_0_CV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKETSC1_0_CV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKETSC1_0_CV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEUSEC_0
+#define TKE_TOP_SHARED_TKEUSEC_0                        MK_ADDR_CONST(0x8)
+#define TKE_TOP_SHARED_TKEUSEC_0_SECURE                         0x0
+#define TKE_TOP_SHARED_TKEUSEC_0_DUAL                   0x0
+#define TKE_TOP_SHARED_TKEUSEC_0_SCR                    TKESCR_0
+#define TKE_TOP_SHARED_TKEUSEC_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEUSEC_0_WORD_COUNT                     0x1
+#define TKE_TOP_SHARED_TKEUSEC_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEUSEC_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEUSEC_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEUSEC_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEUSEC_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEUSEC_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEUSEC_0_CV_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEUSEC_0_CV_FIELD                       MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEUSEC_0_CV_SHIFT)
+#define TKE_TOP_SHARED_TKEUSEC_0_CV_RANGE                       31:0
+#define TKE_TOP_SHARED_TKEUSEC_0_CV_MSB                 MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEUSEC_0_CV_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEUSEC_0_CV_WOFFSET                     0x0
+#define TKE_TOP_SHARED_TKEUSEC_0_CV_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEUSEC_0_CV_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEUSEC_0_CV_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEUSEC_0_CV_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEUSEC_0_CV_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEUSEC_0_CV_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEOSC_0
+#define TKE_TOP_SHARED_TKEOSC_0                 MK_ADDR_CONST(0xc)
+#define TKE_TOP_SHARED_TKEOSC_0_SECURE                  0x0
+#define TKE_TOP_SHARED_TKEOSC_0_DUAL                    0x0
+#define TKE_TOP_SHARED_TKEOSC_0_SCR                     TKESCR_0
+#define TKE_TOP_SHARED_TKEOSC_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEOSC_0_WORD_COUNT                      0x1
+#define TKE_TOP_SHARED_TKEOSC_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEOSC_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEOSC_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEOSC_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEOSC_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEOSC_0_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEOSC_0_CV_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEOSC_0_CV_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEOSC_0_CV_SHIFT)
+#define TKE_TOP_SHARED_TKEOSC_0_CV_RANGE                        31:0
+#define TKE_TOP_SHARED_TKEOSC_0_CV_MSB                  MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEOSC_0_CV_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEOSC_0_CV_WOFFSET                      0x0
+#define TKE_TOP_SHARED_TKEOSC_0_CV_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEOSC_0_CV_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEOSC_0_CV_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEOSC_0_CV_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEOSC_0_CV_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEOSC_0_CV_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKECR_0
+#define TKE_TOP_SHARED_TKECR_0                  MK_ADDR_CONST(0x10)
+#define TKE_TOP_SHARED_TKECR_0_SECURE                   0x0
+#define TKE_TOP_SHARED_TKECR_0_DUAL                     0x0
+#define TKE_TOP_SHARED_TKECR_0_SCR                      TKESCR_0
+#define TKE_TOP_SHARED_TKECR_0_SCRREG                   TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKECR_0_WORD_COUNT                       0x1
+#define TKE_TOP_SHARED_TKECR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKECR_0_RESET_MASK                       MK_MASK_CONST(0xf)
+#define TKE_TOP_SHARED_TKECR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKECR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKECR_0_READ_MASK                        MK_MASK_CONST(0xf)
+#define TKE_TOP_SHARED_TKECR_0_WRITE_MASK                       MK_MASK_CONST(0xf)
+#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_SHARED_TKECR_0_TSC_DIS_SHIFT)
+#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_RANGE                    0:0
+#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_MSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_WOFFSET                  0x0
+#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKECR_0_TSC_DIS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_SHIFT                   MK_SHIFT_CONST(1)
+#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_SHARED_TKECR_0_USEC_DIS_SHIFT)
+#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_RANGE                   1:1
+#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_MSB                     MK_SHIFT_CONST(1)
+#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_LSB                     MK_SHIFT_CONST(1)
+#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_WOFFSET                 0x0
+#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKECR_0_USEC_DIS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_SHIFT                    MK_SHIFT_CONST(2)
+#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_SHARED_TKECR_0_OSC_DIS_SHIFT)
+#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_RANGE                    2:2
+#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_MSB                      MK_SHIFT_CONST(2)
+#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_LSB                      MK_SHIFT_CONST(2)
+#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_WOFFSET                  0x0
+#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKECR_0_OSC_DIS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define TKE_TOP_SHARED_TKECR_0_HDBG_SHIFT                       MK_SHIFT_CONST(3)
+#define TKE_TOP_SHARED_TKECR_0_HDBG_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_SHARED_TKECR_0_HDBG_SHIFT)
+#define TKE_TOP_SHARED_TKECR_0_HDBG_RANGE                       3:3
+#define TKE_TOP_SHARED_TKECR_0_HDBG_MSB                 MK_SHIFT_CONST(3)
+#define TKE_TOP_SHARED_TKECR_0_HDBG_LSB                 MK_SHIFT_CONST(3)
+#define TKE_TOP_SHARED_TKECR_0_HDBG_WOFFSET                     0x0
+#define TKE_TOP_SHARED_TKECR_0_HDBG_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKECR_0_HDBG_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKECR_0_HDBG_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKECR_0_HDBG_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKECR_0_HDBG_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKECR_0_HDBG_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_CLK_OVR_ON_0
+#define TKE_TOP_SHARED_CLK_OVR_ON_0                     MK_ADDR_CONST(0x14)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_SECURE                      0x0
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_DUAL                        0x0
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_SCR                         TKESCR_0
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_SCRREG                      TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_WORD_COUNT                  0x1
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_SHIFT                   MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_SHIFT)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_RANGE                   0:0
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_MSB                     MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_LSB                     MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_WOFFSET                 0x0
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_DISABLE                 MK_ENUM_CONST(0)
+#define TKE_TOP_SHARED_CLK_OVR_ON_0_OSC_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register TKE_TOP_SHARED_TKEIE0_0
+#define TKE_TOP_SHARED_TKEIE0_0                 MK_ADDR_CONST(0x100)
+#define TKE_TOP_SHARED_TKEIE0_0_SECURE                  0x0
+#define TKE_TOP_SHARED_TKEIE0_0_DUAL                    0x0
+#define TKE_TOP_SHARED_TKEIE0_0_SCR                     TKESCR_0
+#define TKE_TOP_SHARED_TKEIE0_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIE0_0_WORD_COUNT                      0x1
+#define TKE_TOP_SHARED_TKEIE0_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE0_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE0_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE0_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE0_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE0_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE0_0_EnableMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_RANGE                 31:0
+#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_WOFFSET                       0x0
+#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKEIE0_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEIE1_0
+#define TKE_TOP_SHARED_TKEIE1_0                 MK_ADDR_CONST(0x104)
+#define TKE_TOP_SHARED_TKEIE1_0_SECURE                  0x0
+#define TKE_TOP_SHARED_TKEIE1_0_DUAL                    0x0
+#define TKE_TOP_SHARED_TKEIE1_0_SCR                     TKESCR_0
+#define TKE_TOP_SHARED_TKEIE1_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIE1_0_WORD_COUNT                      0x1
+#define TKE_TOP_SHARED_TKEIE1_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE1_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE1_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE1_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE1_0_EnableMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_RANGE                 31:0
+#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_WOFFSET                       0x0
+#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKEIE1_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEIE2_0
+#define TKE_TOP_SHARED_TKEIE2_0                 MK_ADDR_CONST(0x108)
+#define TKE_TOP_SHARED_TKEIE2_0_SECURE                  0x0
+#define TKE_TOP_SHARED_TKEIE2_0_DUAL                    0x0
+#define TKE_TOP_SHARED_TKEIE2_0_SCR                     TKESCR_0
+#define TKE_TOP_SHARED_TKEIE2_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIE2_0_WORD_COUNT                      0x1
+#define TKE_TOP_SHARED_TKEIE2_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE2_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE2_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE2_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE2_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE2_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE2_0_EnableMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_RANGE                 31:0
+#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_WOFFSET                       0x0
+#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKEIE2_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEIE3_0
+#define TKE_TOP_SHARED_TKEIE3_0                 MK_ADDR_CONST(0x10c)
+#define TKE_TOP_SHARED_TKEIE3_0_SECURE                  0x0
+#define TKE_TOP_SHARED_TKEIE3_0_DUAL                    0x0
+#define TKE_TOP_SHARED_TKEIE3_0_SCR                     TKESCR_0
+#define TKE_TOP_SHARED_TKEIE3_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIE3_0_WORD_COUNT                      0x1
+#define TKE_TOP_SHARED_TKEIE3_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE3_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE3_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE3_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE3_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE3_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE3_0_EnableMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_RANGE                 31:0
+#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_WOFFSET                       0x0
+#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKEIE3_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEIE4_0
+#define TKE_TOP_SHARED_TKEIE4_0                 MK_ADDR_CONST(0x110)
+#define TKE_TOP_SHARED_TKEIE4_0_SECURE                  0x0
+#define TKE_TOP_SHARED_TKEIE4_0_DUAL                    0x0
+#define TKE_TOP_SHARED_TKEIE4_0_SCR                     TKESCR_0
+#define TKE_TOP_SHARED_TKEIE4_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIE4_0_WORD_COUNT                      0x1
+#define TKE_TOP_SHARED_TKEIE4_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE4_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE4_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE4_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE4_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE4_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE4_0_EnableMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_RANGE                 31:0
+#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_WOFFSET                       0x0
+#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKEIE4_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEIE5_0
+#define TKE_TOP_SHARED_TKEIE5_0                 MK_ADDR_CONST(0x114)
+#define TKE_TOP_SHARED_TKEIE5_0_SECURE                  0x0
+#define TKE_TOP_SHARED_TKEIE5_0_DUAL                    0x0
+#define TKE_TOP_SHARED_TKEIE5_0_SCR                     TKESCR_0
+#define TKE_TOP_SHARED_TKEIE5_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIE5_0_WORD_COUNT                      0x1
+#define TKE_TOP_SHARED_TKEIE5_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE5_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE5_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE5_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE5_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE5_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE5_0_EnableMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_RANGE                 31:0
+#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_WOFFSET                       0x0
+#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKEIE5_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEIE6_0
+#define TKE_TOP_SHARED_TKEIE6_0                 MK_ADDR_CONST(0x118)
+#define TKE_TOP_SHARED_TKEIE6_0_SECURE                  0x0
+#define TKE_TOP_SHARED_TKEIE6_0_DUAL                    0x0
+#define TKE_TOP_SHARED_TKEIE6_0_SCR                     TKESCR_0
+#define TKE_TOP_SHARED_TKEIE6_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIE6_0_WORD_COUNT                      0x1
+#define TKE_TOP_SHARED_TKEIE6_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE6_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE6_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE6_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE6_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE6_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE6_0_EnableMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_RANGE                 31:0
+#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_WOFFSET                       0x0
+#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKEIE6_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEIE7_0
+#define TKE_TOP_SHARED_TKEIE7_0                 MK_ADDR_CONST(0x11c)
+#define TKE_TOP_SHARED_TKEIE7_0_SECURE                  0x0
+#define TKE_TOP_SHARED_TKEIE7_0_DUAL                    0x0
+#define TKE_TOP_SHARED_TKEIE7_0_SCR                     TKESCR_0
+#define TKE_TOP_SHARED_TKEIE7_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIE7_0_WORD_COUNT                      0x1
+#define TKE_TOP_SHARED_TKEIE7_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE7_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE7_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE7_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE7_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE7_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE7_0_EnableMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_RANGE                 31:0
+#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_WOFFSET                       0x0
+#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKEIE7_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEIE8_0
+#define TKE_TOP_SHARED_TKEIE8_0                 MK_ADDR_CONST(0x120)
+#define TKE_TOP_SHARED_TKEIE8_0_SECURE                  0x0
+#define TKE_TOP_SHARED_TKEIE8_0_DUAL                    0x0
+#define TKE_TOP_SHARED_TKEIE8_0_SCR                     TKESCR_0
+#define TKE_TOP_SHARED_TKEIE8_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIE8_0_WORD_COUNT                      0x1
+#define TKE_TOP_SHARED_TKEIE8_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE8_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE8_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE8_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE8_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE8_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE8_0_EnableMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_RANGE                 31:0
+#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_WOFFSET                       0x0
+#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKEIE8_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEIE9_0
+#define TKE_TOP_SHARED_TKEIE9_0                 MK_ADDR_CONST(0x124)
+#define TKE_TOP_SHARED_TKEIE9_0_SECURE                  0x0
+#define TKE_TOP_SHARED_TKEIE9_0_DUAL                    0x0
+#define TKE_TOP_SHARED_TKEIE9_0_SCR                     TKESCR_0
+#define TKE_TOP_SHARED_TKEIE9_0_SCRREG                  TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIE9_0_WORD_COUNT                      0x1
+#define TKE_TOP_SHARED_TKEIE9_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE9_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE9_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE9_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE9_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE9_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_SHIFT                 MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_FIELD                 MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE9_0_EnableMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_RANGE                 31:0
+#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_MSB                   MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_LSB                   MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_WOFFSET                       0x0
+#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKEIE9_0_EnableMap_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEIE10_0
+#define TKE_TOP_SHARED_TKEIE10_0                        MK_ADDR_CONST(0x128)
+#define TKE_TOP_SHARED_TKEIE10_0_SECURE                         0x0
+#define TKE_TOP_SHARED_TKEIE10_0_DUAL                   0x0
+#define TKE_TOP_SHARED_TKEIE10_0_SCR                    TKESCR_0
+#define TKE_TOP_SHARED_TKEIE10_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIE10_0_WORD_COUNT                     0x1
+#define TKE_TOP_SHARED_TKEIE10_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE10_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE10_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE10_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE10_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE10_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE10_0_EnableMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_RANGE                        31:0
+#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_MSB                  MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_WOFFSET                      0x0
+#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKEIE10_0_EnableMap_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEIE11_0
+#define TKE_TOP_SHARED_TKEIE11_0                        MK_ADDR_CONST(0x12c)
+#define TKE_TOP_SHARED_TKEIE11_0_SECURE                         0x0
+#define TKE_TOP_SHARED_TKEIE11_0_DUAL                   0x0
+#define TKE_TOP_SHARED_TKEIE11_0_SCR                    TKESCR_0
+#define TKE_TOP_SHARED_TKEIE11_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIE11_0_WORD_COUNT                     0x1
+#define TKE_TOP_SHARED_TKEIE11_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE11_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE11_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE11_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE11_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE11_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE11_0_EnableMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_RANGE                        31:0
+#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_MSB                  MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_WOFFSET                      0x0
+#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKEIE11_0_EnableMap_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEIE12_0
+#define TKE_TOP_SHARED_TKEIE12_0                        MK_ADDR_CONST(0x130)
+#define TKE_TOP_SHARED_TKEIE12_0_SECURE                         0x0
+#define TKE_TOP_SHARED_TKEIE12_0_DUAL                   0x0
+#define TKE_TOP_SHARED_TKEIE12_0_SCR                    TKESCR_0
+#define TKE_TOP_SHARED_TKEIE12_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIE12_0_WORD_COUNT                     0x1
+#define TKE_TOP_SHARED_TKEIE12_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE12_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE12_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE12_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE12_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE12_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE12_0_EnableMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_RANGE                        31:0
+#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_MSB                  MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_WOFFSET                      0x0
+#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKEIE12_0_EnableMap_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEIE13_0
+#define TKE_TOP_SHARED_TKEIE13_0                        MK_ADDR_CONST(0x134)
+#define TKE_TOP_SHARED_TKEIE13_0_SECURE                         0x0
+#define TKE_TOP_SHARED_TKEIE13_0_DUAL                   0x0
+#define TKE_TOP_SHARED_TKEIE13_0_SCR                    TKESCR_0
+#define TKE_TOP_SHARED_TKEIE13_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIE13_0_WORD_COUNT                     0x1
+#define TKE_TOP_SHARED_TKEIE13_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE13_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE13_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE13_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE13_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE13_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE13_0_EnableMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_RANGE                        31:0
+#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_MSB                  MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_WOFFSET                      0x0
+#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKEIE13_0_EnableMap_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEIE14_0
+#define TKE_TOP_SHARED_TKEIE14_0                        MK_ADDR_CONST(0x138)
+#define TKE_TOP_SHARED_TKEIE14_0_SECURE                         0x0
+#define TKE_TOP_SHARED_TKEIE14_0_DUAL                   0x0
+#define TKE_TOP_SHARED_TKEIE14_0_SCR                    TKESCR_0
+#define TKE_TOP_SHARED_TKEIE14_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIE14_0_WORD_COUNT                     0x1
+#define TKE_TOP_SHARED_TKEIE14_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE14_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE14_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE14_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE14_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE14_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE14_0_EnableMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_RANGE                        31:0
+#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_MSB                  MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_WOFFSET                      0x0
+#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKEIE14_0_EnableMap_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEIE15_0
+#define TKE_TOP_SHARED_TKEIE15_0                        MK_ADDR_CONST(0x13c)
+#define TKE_TOP_SHARED_TKEIE15_0_SECURE                         0x0
+#define TKE_TOP_SHARED_TKEIE15_0_DUAL                   0x0
+#define TKE_TOP_SHARED_TKEIE15_0_SCR                    TKESCR_0
+#define TKE_TOP_SHARED_TKEIE15_0_SCRREG                         TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIE15_0_WORD_COUNT                     0x1
+#define TKE_TOP_SHARED_TKEIE15_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE15_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE15_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE15_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE15_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE15_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIE15_0_EnableMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_RANGE                        31:0
+#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_MSB                  MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_WOFFSET                      0x0
+#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_SHARED_TKEIE15_0_EnableMap_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEIV_0
+#define TKE_TOP_SHARED_TKEIV_0                  MK_ADDR_CONST(0x200)
+#define TKE_TOP_SHARED_TKEIV_0_SECURE                   0x0
+#define TKE_TOP_SHARED_TKEIV_0_DUAL                     0x0
+#define TKE_TOP_SHARED_TKEIV_0_SCR                      TKESCR_0
+#define TKE_TOP_SHARED_TKEIV_0_SCRREG                   TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIV_0_WORD_COUNT                       0x1
+#define TKE_TOP_SHARED_TKEIV_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIV_0_RESET_MASK                       MK_MASK_CONST(0xffff)
+#define TKE_TOP_SHARED_TKEIV_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIV_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIV_0_READ_MASK                        MK_MASK_CONST(0xffff)
+#define TKE_TOP_SHARED_TKEIV_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIV_0_ValidMap_SHIFT                   MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIV_0_ValidMap_FIELD                   MK_FIELD_CONST(0xffff, TKE_TOP_SHARED_TKEIV_0_ValidMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIV_0_ValidMap_RANGE                   15:0
+#define TKE_TOP_SHARED_TKEIV_0_ValidMap_MSB                     MK_SHIFT_CONST(15)
+#define TKE_TOP_SHARED_TKEIV_0_ValidMap_LSB                     MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIV_0_ValidMap_WOFFSET                 0x0
+#define TKE_TOP_SHARED_TKEIV_0_ValidMap_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIV_0_ValidMap_DEFAULT_MASK                    MK_MASK_CONST(0xffff)
+#define TKE_TOP_SHARED_TKEIV_0_ValidMap_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIV_0_ValidMap_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIV_0_ValidMap_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIV_0_ValidMap_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_SHARED_TKEIR_0
+#define TKE_TOP_SHARED_TKEIR_0                  MK_ADDR_CONST(0x204)
+#define TKE_TOP_SHARED_TKEIR_0_SECURE                   0x0
+#define TKE_TOP_SHARED_TKEIR_0_DUAL                     0x0
+#define TKE_TOP_SHARED_TKEIR_0_SCR                      TKESCR_0
+#define TKE_TOP_SHARED_TKEIR_0_SCRREG                   TKE_TOP_SCR_TKESCR_0
+#define TKE_TOP_SHARED_TKEIR_0_WORD_COUNT                       0x1
+#define TKE_TOP_SHARED_TKEIR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIR_0_RESET_MASK                       MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIR_0_READ_MASK                        MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIR_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIR_0_RawMap_SHIFT                     MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIR_0_RawMap_FIELD                     MK_FIELD_CONST(0xffffffff, TKE_TOP_SHARED_TKEIR_0_RawMap_SHIFT)
+#define TKE_TOP_SHARED_TKEIR_0_RawMap_RANGE                     31:0
+#define TKE_TOP_SHARED_TKEIR_0_RawMap_MSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_SHARED_TKEIR_0_RawMap_LSB                       MK_SHIFT_CONST(0)
+#define TKE_TOP_SHARED_TKEIR_0_RawMap_WOFFSET                   0x0
+#define TKE_TOP_SHARED_TKEIR_0_RawMap_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIR_0_RawMap_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_SHARED_TKEIR_0_RawMap_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIR_0_RawMap_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIR_0_RawMap_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define TKE_TOP_SHARED_TKEIR_0_RawMap_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR0_TMRCR_0
+#define TKE_TOP_TIMER_TMR0_TMRCR_0                      MK_ADDR_CONST(0x10000)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_SCR                  TMRSCR0_0
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR0_0
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR0_TMRCR_0_EN_SHIFT)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_RANGE                     31:31
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_WOFFSET                   0x0
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR0_TMRCR_0_PER_SHIFT)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_RANGE                    30:30
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_SHIFT)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR0_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)
+
+
+// Register TKE_TOP_TIMER_TMR0_TMRSR_0
+#define TKE_TOP_TIMER_TMR0_TMRSR_0                      MK_ADDR_CONST(0x10004)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_SCR                  TMRSCR0_0
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR0_0
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_SHIFT)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_RANGE                       30:30
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_SHIFT)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR0_TMRCSSR_0
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0                    MK_ADDR_CONST(0x10008)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SECURE                     0x0
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_DUAL                       0x0
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SCR                        TMRSCR0_0
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR0_0
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_WORD_COUNT                         0x1
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SHIFT)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_RANGE                       1:0
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
+#define TKE_TOP_TIMER_TMR0_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)
+
+
+// Register TKE_TOP_TIMER_TMR0_TMRATR_0
+#define TKE_TOP_TIMER_TMR0_TMRATR_0                     MK_ADDR_CONST(0x1000c)
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_SCR                         TMRSCR0_0
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR0_0
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_SHIFT)
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_RANGE                        29:0
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_WOFFSET                      0x0
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR0_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR1_TMRCR_0
+#define TKE_TOP_TIMER_TMR1_TMRCR_0                      MK_ADDR_CONST(0x20000)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_SCR                  TMRSCR1_0
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR1_0
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR1_TMRCR_0_EN_SHIFT)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_RANGE                     31:31
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_WOFFSET                   0x0
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR1_TMRCR_0_PER_SHIFT)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_RANGE                    30:30
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_SHIFT)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR1_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)
+
+
+// Register TKE_TOP_TIMER_TMR1_TMRSR_0
+#define TKE_TOP_TIMER_TMR1_TMRSR_0                      MK_ADDR_CONST(0x20004)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_SCR                  TMRSCR1_0
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR1_0
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_SHIFT)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_RANGE                       30:30
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_SHIFT)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR1_TMRCSSR_0
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0                    MK_ADDR_CONST(0x20008)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SECURE                     0x0
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_DUAL                       0x0
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SCR                        TMRSCR1_0
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR1_0
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_WORD_COUNT                         0x1
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SHIFT)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_RANGE                       1:0
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
+#define TKE_TOP_TIMER_TMR1_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)
+
+
+// Register TKE_TOP_TIMER_TMR1_TMRATR_0
+#define TKE_TOP_TIMER_TMR1_TMRATR_0                     MK_ADDR_CONST(0x2000c)
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_SCR                         TMRSCR1_0
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR1_0
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_SHIFT)
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_RANGE                        29:0
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_WOFFSET                      0x0
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR1_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR2_TMRCR_0
+#define TKE_TOP_TIMER_TMR2_TMRCR_0                      MK_ADDR_CONST(0x30000)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_SCR                  TMRSCR2_0
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR2_0
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR2_TMRCR_0_EN_SHIFT)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_RANGE                     31:31
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_WOFFSET                   0x0
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR2_TMRCR_0_PER_SHIFT)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_RANGE                    30:30
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_SHIFT)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR2_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)
+
+
+// Register TKE_TOP_TIMER_TMR2_TMRSR_0
+#define TKE_TOP_TIMER_TMR2_TMRSR_0                      MK_ADDR_CONST(0x30004)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_SCR                  TMRSCR2_0
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR2_0
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_SHIFT)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_RANGE                       30:30
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_SHIFT)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR2_TMRCSSR_0
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0                    MK_ADDR_CONST(0x30008)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SECURE                     0x0
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_DUAL                       0x0
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SCR                        TMRSCR2_0
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR2_0
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_WORD_COUNT                         0x1
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SHIFT)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_RANGE                       1:0
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
+#define TKE_TOP_TIMER_TMR2_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)
+
+
+// Register TKE_TOP_TIMER_TMR2_TMRATR_0
+#define TKE_TOP_TIMER_TMR2_TMRATR_0                     MK_ADDR_CONST(0x3000c)
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_SCR                         TMRSCR2_0
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR2_0
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_SHIFT)
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_RANGE                        29:0
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_WOFFSET                      0x0
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR2_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR3_TMRCR_0
+#define TKE_TOP_TIMER_TMR3_TMRCR_0                      MK_ADDR_CONST(0x40000)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_SCR                  TMRSCR3_0
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR3_0
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR3_TMRCR_0_EN_SHIFT)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_RANGE                     31:31
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_WOFFSET                   0x0
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR3_TMRCR_0_PER_SHIFT)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_RANGE                    30:30
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_SHIFT)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR3_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)
+
+
+// Register TKE_TOP_TIMER_TMR3_TMRSR_0
+#define TKE_TOP_TIMER_TMR3_TMRSR_0                      MK_ADDR_CONST(0x40004)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_SCR                  TMRSCR3_0
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR3_0
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_SHIFT)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_RANGE                       30:30
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_SHIFT)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR3_TMRCSSR_0
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0                    MK_ADDR_CONST(0x40008)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SECURE                     0x0
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_DUAL                       0x0
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SCR                        TMRSCR3_0
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR3_0
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_WORD_COUNT                         0x1
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SHIFT)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_RANGE                       1:0
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
+#define TKE_TOP_TIMER_TMR3_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)
+
+
+// Register TKE_TOP_TIMER_TMR3_TMRATR_0
+#define TKE_TOP_TIMER_TMR3_TMRATR_0                     MK_ADDR_CONST(0x4000c)
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_SCR                         TMRSCR3_0
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR3_0
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_SHIFT)
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_RANGE                        29:0
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_WOFFSET                      0x0
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR3_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR4_TMRCR_0
+#define TKE_TOP_TIMER_TMR4_TMRCR_0                      MK_ADDR_CONST(0x50000)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_SCR                  TMRSCR4_0
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR4_0
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR4_TMRCR_0_EN_SHIFT)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_RANGE                     31:31
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_WOFFSET                   0x0
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR4_TMRCR_0_PER_SHIFT)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_RANGE                    30:30
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_SHIFT)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR4_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)
+
+
+// Register TKE_TOP_TIMER_TMR4_TMRSR_0
+#define TKE_TOP_TIMER_TMR4_TMRSR_0                      MK_ADDR_CONST(0x50004)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_SCR                  TMRSCR4_0
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR4_0
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_SHIFT)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_RANGE                       30:30
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_SHIFT)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR4_TMRCSSR_0
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0                    MK_ADDR_CONST(0x50008)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SECURE                     0x0
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_DUAL                       0x0
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SCR                        TMRSCR4_0
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR4_0
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_WORD_COUNT                         0x1
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_SHIFT)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_RANGE                       1:0
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
+#define TKE_TOP_TIMER_TMR4_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)
+
+
+// Register TKE_TOP_TIMER_TMR4_TMRATR_0
+#define TKE_TOP_TIMER_TMR4_TMRATR_0                     MK_ADDR_CONST(0x5000c)
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_SCR                         TMRSCR4_0
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR4_0
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_SHIFT)
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_RANGE                        29:0
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_WOFFSET                      0x0
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR4_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR5_TMRCR_0
+#define TKE_TOP_TIMER_TMR5_TMRCR_0                      MK_ADDR_CONST(0x60000)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_SCR                  TMRSCR5_0
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR5_0
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR5_TMRCR_0_EN_SHIFT)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_RANGE                     31:31
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_WOFFSET                   0x0
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR5_TMRCR_0_PER_SHIFT)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_RANGE                    30:30
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_SHIFT)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR5_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)
+
+
+// Register TKE_TOP_TIMER_TMR5_TMRSR_0
+#define TKE_TOP_TIMER_TMR5_TMRSR_0                      MK_ADDR_CONST(0x60004)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_SCR                  TMRSCR5_0
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR5_0
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_SHIFT)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_RANGE                       30:30
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_SHIFT)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR5_TMRCSSR_0
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0                    MK_ADDR_CONST(0x60008)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SECURE                     0x0
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_DUAL                       0x0
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SCR                        TMRSCR5_0
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR5_0
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_WORD_COUNT                         0x1
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_SHIFT)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_RANGE                       1:0
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
+#define TKE_TOP_TIMER_TMR5_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)
+
+
+// Register TKE_TOP_TIMER_TMR5_TMRATR_0
+#define TKE_TOP_TIMER_TMR5_TMRATR_0                     MK_ADDR_CONST(0x6000c)
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_SCR                         TMRSCR5_0
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR5_0
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_SHIFT)
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_RANGE                        29:0
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_WOFFSET                      0x0
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR5_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR6_TMRCR_0
+#define TKE_TOP_TIMER_TMR6_TMRCR_0                      MK_ADDR_CONST(0x70000)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_SCR                  TMRSCR6_0
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR6_0
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR6_TMRCR_0_EN_SHIFT)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_RANGE                     31:31
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_WOFFSET                   0x0
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR6_TMRCR_0_PER_SHIFT)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_RANGE                    30:30
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_SHIFT)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR6_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)
+
+
+// Register TKE_TOP_TIMER_TMR6_TMRSR_0
+#define TKE_TOP_TIMER_TMR6_TMRSR_0                      MK_ADDR_CONST(0x70004)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_SCR                  TMRSCR6_0
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR6_0
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_SHIFT)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_RANGE                       30:30
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_SHIFT)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR6_TMRCSSR_0
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0                    MK_ADDR_CONST(0x70008)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SECURE                     0x0
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_DUAL                       0x0
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SCR                        TMRSCR6_0
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR6_0
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_WORD_COUNT                         0x1
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_SHIFT)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_RANGE                       1:0
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
+#define TKE_TOP_TIMER_TMR6_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)
+
+
+// Register TKE_TOP_TIMER_TMR6_TMRATR_0
+#define TKE_TOP_TIMER_TMR6_TMRATR_0                     MK_ADDR_CONST(0x7000c)
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_SCR                         TMRSCR6_0
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR6_0
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_SHIFT)
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_RANGE                        29:0
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_WOFFSET                      0x0
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR6_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR7_TMRCR_0
+#define TKE_TOP_TIMER_TMR7_TMRCR_0                      MK_ADDR_CONST(0x80000)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_SCR                  TMRSCR7_0
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR7_0
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR7_TMRCR_0_EN_SHIFT)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_RANGE                     31:31
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_WOFFSET                   0x0
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR7_TMRCR_0_PER_SHIFT)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_RANGE                    30:30
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_SHIFT)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR7_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)
+
+
+// Register TKE_TOP_TIMER_TMR7_TMRSR_0
+#define TKE_TOP_TIMER_TMR7_TMRSR_0                      MK_ADDR_CONST(0x80004)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_SCR                  TMRSCR7_0
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR7_0
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_SHIFT)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_RANGE                       30:30
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_SHIFT)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR7_TMRCSSR_0
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0                    MK_ADDR_CONST(0x80008)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SECURE                     0x0
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_DUAL                       0x0
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SCR                        TMRSCR7_0
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR7_0
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_WORD_COUNT                         0x1
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_SHIFT)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_RANGE                       1:0
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
+#define TKE_TOP_TIMER_TMR7_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)
+
+
+// Register TKE_TOP_TIMER_TMR7_TMRATR_0
+#define TKE_TOP_TIMER_TMR7_TMRATR_0                     MK_ADDR_CONST(0x8000c)
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_SCR                         TMRSCR7_0
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR7_0
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_SHIFT)
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_RANGE                        29:0
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_WOFFSET                      0x0
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR7_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR8_TMRCR_0
+#define TKE_TOP_TIMER_TMR8_TMRCR_0                      MK_ADDR_CONST(0x90000)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_SCR                  TMRSCR8_0
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR8_0
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR8_TMRCR_0_EN_SHIFT)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_RANGE                     31:31
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_WOFFSET                   0x0
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR8_TMRCR_0_PER_SHIFT)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_RANGE                    30:30
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_SHIFT)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR8_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)
+
+
+// Register TKE_TOP_TIMER_TMR8_TMRSR_0
+#define TKE_TOP_TIMER_TMR8_TMRSR_0                      MK_ADDR_CONST(0x90004)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_SCR                  TMRSCR8_0
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR8_0
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_SHIFT)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_RANGE                       30:30
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_SHIFT)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR8_TMRCSSR_0
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0                    MK_ADDR_CONST(0x90008)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SECURE                     0x0
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_DUAL                       0x0
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SCR                        TMRSCR8_0
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR8_0
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_WORD_COUNT                         0x1
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_SHIFT)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_RANGE                       1:0
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
+#define TKE_TOP_TIMER_TMR8_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)
+
+
+// Register TKE_TOP_TIMER_TMR8_TMRATR_0
+#define TKE_TOP_TIMER_TMR8_TMRATR_0                     MK_ADDR_CONST(0x9000c)
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_SCR                         TMRSCR8_0
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR8_0
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_SHIFT)
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_RANGE                        29:0
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_WOFFSET                      0x0
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR8_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR9_TMRCR_0
+#define TKE_TOP_TIMER_TMR9_TMRCR_0                      MK_ADDR_CONST(0xa0000)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_SCR                  TMRSCR9_0
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_SCRREG                       TKE_TOP_SCR_TMRSCR9_0
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_RESET_VAL                    MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_RESET_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_READ_MASK                    MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_WRITE_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_SHIFT                     MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR9_TMRCR_0_EN_SHIFT)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_RANGE                     31:31
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_MSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_LSB                       MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_WOFFSET                   0x0
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_DISABLE                   MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_SHIFT                    MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR9_TMRCR_0_PER_SHIFT)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_RANGE                    30:30
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_MSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_LSB                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_DEFAULT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_DISABLE                  MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PER_ENABLE                   MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_SHIFT)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR9_TMRCR_0_PTV_MAX                      MK_ENUM_CONST(536870911)
+
+
+// Register TKE_TOP_TIMER_TMR9_TMRSR_0
+#define TKE_TOP_TIMER_TMR9_TMRSR_0                      MK_ADDR_CONST(0xa0004)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_SECURE                       0x0
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_DUAL                         0x0
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_SCR                  TMRSCR9_0
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_SCRREG                       TKE_TOP_SCR_TMRSCR9_0
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_WORD_COUNT                   0x1
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_RESET_MASK                   MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_READ_MASK                    MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_WRITE_MASK                   MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_SHIFT                       MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_SHIFT)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_RANGE                       30:30
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_MSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_LSB                 MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_DISABLE                     MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_INTR_CLR_ENABLE                      MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_SHIFT                    MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_FIELD                    MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_SHIFT)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_RANGE                    28:0
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_MSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_LSB                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_DEFAULT_MASK                     MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRSR_0_PCV_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR9_TMRCSSR_0
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0                    MK_ADDR_CONST(0xa0008)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SECURE                     0x0
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_DUAL                       0x0
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SCR                        TMRSCR9_0
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SCRREG                     TKE_TOP_SCR_TMRSCR9_0
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_WORD_COUNT                         0x1
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_RESET_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_READ_MASK                  MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_WRITE_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_FIELD                       MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_SHIFT)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_RANGE                       1:0
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_MSB                 MK_SHIFT_CONST(1)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_DEFAULT_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_SRC_USECCNT                 MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_SRC_OSCCNT                  MK_ENUM_CONST(1)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                     MK_ENUM_CONST(2)
+#define TKE_TOP_TIMER_TMR9_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                    MK_ENUM_CONST(3)
+
+
+// Register TKE_TOP_TIMER_TMR9_TMRATR_0
+#define TKE_TOP_TIMER_TMR9_TMRATR_0                     MK_ADDR_CONST(0xa000c)
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_SCR                         TMRSCR9_0
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_SCRREG                      TKE_TOP_SCR_TMRSCR9_0
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_RESET_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_READ_MASK                   MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_WRITE_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_FIELD                        MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_SHIFT)
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_RANGE                        29:0
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_MSB                  MK_SHIFT_CONST(29)
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_WOFFSET                      0x0
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_DEFAULT_MASK                 MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR9_TMRATR_0_TARGET_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR10_TMRCR_0
+#define TKE_TOP_TIMER_TMR10_TMRCR_0                     MK_ADDR_CONST(0xb0000)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_SCR                         TMRSCR10_0
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_SCRREG                      TKE_TOP_SCR_TMRSCR10_0
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_RESET_VAL                   MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_RESET_MASK                  MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_READ_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_WRITE_MASK                  MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_SHIFT                    MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR10_TMRCR_0_EN_SHIFT)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_RANGE                    31:31
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_MSB                      MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_LSB                      MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_DISABLE                  MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_SHIFT                   MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR10_TMRCR_0_PER_SHIFT)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_RANGE                   30:30
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_MSB                     MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_LSB                     MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_DEFAULT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_DISABLE                 MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PER_ENABLE                  MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_SHIFT                   MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_SHIFT)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_RANGE                   28:0
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_MSB                     MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_LSB                     MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR10_TMRCR_0_PTV_MAX                     MK_ENUM_CONST(536870911)
+
+
+// Register TKE_TOP_TIMER_TMR10_TMRSR_0
+#define TKE_TOP_TIMER_TMR10_TMRSR_0                     MK_ADDR_CONST(0xb0004)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_SCR                         TMRSCR10_0
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_SCRREG                      TKE_TOP_SCR_TMRSCR10_0
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_RESET_MASK                  MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_READ_MASK                   MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_SHIFT                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_SHIFT)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_RANGE                      30:30
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_MSB                        MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_LSB                        MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_WOFFSET                    0x0
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_DISABLE                    MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_INTR_CLR_ENABLE                     MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_SHIFT                   MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_SHIFT)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_RANGE                   28:0
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_MSB                     MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_LSB                     MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRSR_0_PCV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR10_TMRCSSR_0
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0                   MK_ADDR_CONST(0xb0008)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SECURE                    0x0
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_DUAL                      0x0
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SCR                       TMRSCR10_0
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SCRREG                    TKE_TOP_SCR_TMRSCR10_0
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_WORD_COUNT                        0x1
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_RESET_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_READ_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_WRITE_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_SHIFT                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_FIELD                      MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_SHIFT)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_RANGE                      1:0
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_MSB                        MK_SHIFT_CONST(1)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_LSB                        MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_WOFFSET                    0x0
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_SRC_USECCNT                        MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_SRC_OSCCNT                 MK_ENUM_CONST(1)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                    MK_ENUM_CONST(2)
+#define TKE_TOP_TIMER_TMR10_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                   MK_ENUM_CONST(3)
+
+
+// Register TKE_TOP_TIMER_TMR10_TMRATR_0
+#define TKE_TOP_TIMER_TMR10_TMRATR_0                    MK_ADDR_CONST(0xb000c)
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_SECURE                     0x0
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_DUAL                       0x0
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_SCR                        TMRSCR10_0
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_SCRREG                     TKE_TOP_SCR_TMRSCR10_0
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_WORD_COUNT                         0x1
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_FIELD                       MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_SHIFT)
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_RANGE                       29:0
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_MSB                 MK_SHIFT_CONST(29)
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_DEFAULT_MASK                        MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR10_TMRATR_0_TARGET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR11_TMRCR_0
+#define TKE_TOP_TIMER_TMR11_TMRCR_0                     MK_ADDR_CONST(0xc0000)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_SCR                         TMRSCR11_0
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_SCRREG                      TKE_TOP_SCR_TMRSCR11_0
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_RESET_VAL                   MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_RESET_MASK                  MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_READ_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_WRITE_MASK                  MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_SHIFT                    MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR11_TMRCR_0_EN_SHIFT)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_RANGE                    31:31
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_MSB                      MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_LSB                      MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_DISABLE                  MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_SHIFT                   MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR11_TMRCR_0_PER_SHIFT)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_RANGE                   30:30
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_MSB                     MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_LSB                     MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_DEFAULT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_DISABLE                 MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PER_ENABLE                  MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_SHIFT                   MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_SHIFT)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_RANGE                   28:0
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_MSB                     MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_LSB                     MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR11_TMRCR_0_PTV_MAX                     MK_ENUM_CONST(536870911)
+
+
+// Register TKE_TOP_TIMER_TMR11_TMRSR_0
+#define TKE_TOP_TIMER_TMR11_TMRSR_0                     MK_ADDR_CONST(0xc0004)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_SCR                         TMRSCR11_0
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_SCRREG                      TKE_TOP_SCR_TMRSCR11_0
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_RESET_MASK                  MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_READ_MASK                   MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_SHIFT                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_SHIFT)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_RANGE                      30:30
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_MSB                        MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_LSB                        MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_WOFFSET                    0x0
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_DISABLE                    MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_INTR_CLR_ENABLE                     MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_SHIFT                   MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_SHIFT)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_RANGE                   28:0
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_MSB                     MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_LSB                     MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRSR_0_PCV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR11_TMRCSSR_0
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0                   MK_ADDR_CONST(0xc0008)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SECURE                    0x0
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_DUAL                      0x0
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SCR                       TMRSCR11_0
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SCRREG                    TKE_TOP_SCR_TMRSCR11_0
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_WORD_COUNT                        0x1
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_RESET_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_READ_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_WRITE_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_SHIFT                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_FIELD                      MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_SHIFT)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_RANGE                      1:0
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_MSB                        MK_SHIFT_CONST(1)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_LSB                        MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_WOFFSET                    0x0
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_SRC_USECCNT                        MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_SRC_OSCCNT                 MK_ENUM_CONST(1)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                    MK_ENUM_CONST(2)
+#define TKE_TOP_TIMER_TMR11_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                   MK_ENUM_CONST(3)
+
+
+// Register TKE_TOP_TIMER_TMR11_TMRATR_0
+#define TKE_TOP_TIMER_TMR11_TMRATR_0                    MK_ADDR_CONST(0xc000c)
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_SECURE                     0x0
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_DUAL                       0x0
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_SCR                        TMRSCR11_0
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_SCRREG                     TKE_TOP_SCR_TMRSCR11_0
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_WORD_COUNT                         0x1
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_FIELD                       MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_SHIFT)
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_RANGE                       29:0
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_MSB                 MK_SHIFT_CONST(29)
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_DEFAULT_MASK                        MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR11_TMRATR_0_TARGET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR12_TMRCR_0
+#define TKE_TOP_TIMER_TMR12_TMRCR_0                     MK_ADDR_CONST(0xd0000)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_SCR                         TMRSCR12_0
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_SCRREG                      TKE_TOP_SCR_TMRSCR12_0
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_RESET_VAL                   MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_RESET_MASK                  MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_READ_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_WRITE_MASK                  MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_SHIFT                    MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR12_TMRCR_0_EN_SHIFT)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_RANGE                    31:31
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_MSB                      MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_LSB                      MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_DISABLE                  MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_SHIFT                   MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR12_TMRCR_0_PER_SHIFT)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_RANGE                   30:30
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_MSB                     MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_LSB                     MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_DEFAULT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_DISABLE                 MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PER_ENABLE                  MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_SHIFT                   MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_SHIFT)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_RANGE                   28:0
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_MSB                     MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_LSB                     MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR12_TMRCR_0_PTV_MAX                     MK_ENUM_CONST(536870911)
+
+
+// Register TKE_TOP_TIMER_TMR12_TMRSR_0
+#define TKE_TOP_TIMER_TMR12_TMRSR_0                     MK_ADDR_CONST(0xd0004)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_SCR                         TMRSCR12_0
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_SCRREG                      TKE_TOP_SCR_TMRSCR12_0
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_RESET_MASK                  MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_READ_MASK                   MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_SHIFT                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_SHIFT)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_RANGE                      30:30
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_MSB                        MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_LSB                        MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_WOFFSET                    0x0
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_DISABLE                    MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_INTR_CLR_ENABLE                     MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_SHIFT                   MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_SHIFT)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_RANGE                   28:0
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_MSB                     MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_LSB                     MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRSR_0_PCV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR12_TMRCSSR_0
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0                   MK_ADDR_CONST(0xd0008)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SECURE                    0x0
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_DUAL                      0x0
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SCR                       TMRSCR12_0
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SCRREG                    TKE_TOP_SCR_TMRSCR12_0
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_WORD_COUNT                        0x1
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_RESET_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_READ_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_WRITE_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_SHIFT                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_FIELD                      MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_SHIFT)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_RANGE                      1:0
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_MSB                        MK_SHIFT_CONST(1)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_LSB                        MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_WOFFSET                    0x0
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_SRC_USECCNT                        MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_SRC_OSCCNT                 MK_ENUM_CONST(1)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                    MK_ENUM_CONST(2)
+#define TKE_TOP_TIMER_TMR12_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                   MK_ENUM_CONST(3)
+
+
+// Register TKE_TOP_TIMER_TMR12_TMRATR_0
+#define TKE_TOP_TIMER_TMR12_TMRATR_0                    MK_ADDR_CONST(0xd000c)
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_SECURE                     0x0
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_DUAL                       0x0
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_SCR                        TMRSCR12_0
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_SCRREG                     TKE_TOP_SCR_TMRSCR12_0
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_WORD_COUNT                         0x1
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_FIELD                       MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_SHIFT)
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_RANGE                       29:0
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_MSB                 MK_SHIFT_CONST(29)
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_DEFAULT_MASK                        MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR12_TMRATR_0_TARGET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR13_TMRCR_0
+#define TKE_TOP_TIMER_TMR13_TMRCR_0                     MK_ADDR_CONST(0xe0000)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_SCR                         TMRSCR13_0
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_SCRREG                      TKE_TOP_SCR_TMRSCR13_0
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_RESET_VAL                   MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_RESET_MASK                  MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_READ_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_WRITE_MASK                  MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_SHIFT                    MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR13_TMRCR_0_EN_SHIFT)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_RANGE                    31:31
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_MSB                      MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_LSB                      MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_DISABLE                  MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_SHIFT                   MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR13_TMRCR_0_PER_SHIFT)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_RANGE                   30:30
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_MSB                     MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_LSB                     MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_DEFAULT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_DISABLE                 MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PER_ENABLE                  MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_SHIFT                   MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_SHIFT)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_RANGE                   28:0
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_MSB                     MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_LSB                     MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR13_TMRCR_0_PTV_MAX                     MK_ENUM_CONST(536870911)
+
+
+// Register TKE_TOP_TIMER_TMR13_TMRSR_0
+#define TKE_TOP_TIMER_TMR13_TMRSR_0                     MK_ADDR_CONST(0xe0004)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_SCR                         TMRSCR13_0
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_SCRREG                      TKE_TOP_SCR_TMRSCR13_0
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_RESET_MASK                  MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_READ_MASK                   MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_SHIFT                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_SHIFT)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_RANGE                      30:30
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_MSB                        MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_LSB                        MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_WOFFSET                    0x0
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_DISABLE                    MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_INTR_CLR_ENABLE                     MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_SHIFT                   MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_SHIFT)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_RANGE                   28:0
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_MSB                     MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_LSB                     MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRSR_0_PCV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR13_TMRCSSR_0
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0                   MK_ADDR_CONST(0xe0008)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SECURE                    0x0
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_DUAL                      0x0
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SCR                       TMRSCR13_0
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SCRREG                    TKE_TOP_SCR_TMRSCR13_0
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_WORD_COUNT                        0x1
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_RESET_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_READ_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_WRITE_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_SHIFT                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_FIELD                      MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_SHIFT)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_RANGE                      1:0
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_MSB                        MK_SHIFT_CONST(1)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_LSB                        MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_WOFFSET                    0x0
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_SRC_USECCNT                        MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_SRC_OSCCNT                 MK_ENUM_CONST(1)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                    MK_ENUM_CONST(2)
+#define TKE_TOP_TIMER_TMR13_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                   MK_ENUM_CONST(3)
+
+
+// Register TKE_TOP_TIMER_TMR13_TMRATR_0
+#define TKE_TOP_TIMER_TMR13_TMRATR_0                    MK_ADDR_CONST(0xe000c)
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_SECURE                     0x0
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_DUAL                       0x0
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_SCR                        TMRSCR13_0
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_SCRREG                     TKE_TOP_SCR_TMRSCR13_0
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_WORD_COUNT                         0x1
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_FIELD                       MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_SHIFT)
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_RANGE                       29:0
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_MSB                 MK_SHIFT_CONST(29)
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_DEFAULT_MASK                        MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR13_TMRATR_0_TARGET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR14_TMRCR_0
+#define TKE_TOP_TIMER_TMR14_TMRCR_0                     MK_ADDR_CONST(0xf0000)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_SCR                         TMRSCR14_0
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_SCRREG                      TKE_TOP_SCR_TMRSCR14_0
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_RESET_VAL                   MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_RESET_MASK                  MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_READ_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_WRITE_MASK                  MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_SHIFT                    MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR14_TMRCR_0_EN_SHIFT)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_RANGE                    31:31
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_MSB                      MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_LSB                      MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_DISABLE                  MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_SHIFT                   MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR14_TMRCR_0_PER_SHIFT)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_RANGE                   30:30
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_MSB                     MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_LSB                     MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_DEFAULT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_DISABLE                 MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PER_ENABLE                  MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_SHIFT                   MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_SHIFT)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_RANGE                   28:0
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_MSB                     MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_LSB                     MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR14_TMRCR_0_PTV_MAX                     MK_ENUM_CONST(536870911)
+
+
+// Register TKE_TOP_TIMER_TMR14_TMRSR_0
+#define TKE_TOP_TIMER_TMR14_TMRSR_0                     MK_ADDR_CONST(0xf0004)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_SCR                         TMRSCR14_0
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_SCRREG                      TKE_TOP_SCR_TMRSCR14_0
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_RESET_MASK                  MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_READ_MASK                   MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_SHIFT                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_SHIFT)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_RANGE                      30:30
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_MSB                        MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_LSB                        MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_WOFFSET                    0x0
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_DISABLE                    MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_INTR_CLR_ENABLE                     MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_SHIFT                   MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_SHIFT)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_RANGE                   28:0
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_MSB                     MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_LSB                     MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRSR_0_PCV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR14_TMRCSSR_0
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0                   MK_ADDR_CONST(0xf0008)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SECURE                    0x0
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_DUAL                      0x0
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SCR                       TMRSCR14_0
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SCRREG                    TKE_TOP_SCR_TMRSCR14_0
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_WORD_COUNT                        0x1
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_RESET_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_READ_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_WRITE_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_SHIFT                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_FIELD                      MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_SHIFT)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_RANGE                      1:0
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_MSB                        MK_SHIFT_CONST(1)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_LSB                        MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_WOFFSET                    0x0
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_SRC_USECCNT                        MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_SRC_OSCCNT                 MK_ENUM_CONST(1)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                    MK_ENUM_CONST(2)
+#define TKE_TOP_TIMER_TMR14_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                   MK_ENUM_CONST(3)
+
+
+// Register TKE_TOP_TIMER_TMR14_TMRATR_0
+#define TKE_TOP_TIMER_TMR14_TMRATR_0                    MK_ADDR_CONST(0xf000c)
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_SECURE                     0x0
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_DUAL                       0x0
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_SCR                        TMRSCR14_0
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_SCRREG                     TKE_TOP_SCR_TMRSCR14_0
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_WORD_COUNT                         0x1
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_FIELD                       MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_SHIFT)
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_RANGE                       29:0
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_MSB                 MK_SHIFT_CONST(29)
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_DEFAULT_MASK                        MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR14_TMRATR_0_TARGET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR15_TMRCR_0
+#define TKE_TOP_TIMER_TMR15_TMRCR_0                     MK_ADDR_CONST(0x100000)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_SCR                         TMRSCR15_0
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_SCRREG                      TKE_TOP_SCR_TMRSCR15_0
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_RESET_VAL                   MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_RESET_MASK                  MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_READ_MASK                   MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_WRITE_MASK                  MK_MASK_CONST(0xdfffffff)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_SHIFT                    MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR15_TMRCR_0_EN_SHIFT)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_RANGE                    31:31
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_MSB                      MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_LSB                      MK_SHIFT_CONST(31)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_WOFFSET                  0x0
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_DISABLE                  MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_SHIFT                   MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR15_TMRCR_0_PER_SHIFT)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_RANGE                   30:30
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_MSB                     MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_LSB                     MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_DEFAULT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_DISABLE                 MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PER_ENABLE                  MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_SHIFT                   MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_SHIFT)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_RANGE                   28:0
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_MSB                     MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_LSB                     MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR15_TMRCR_0_PTV_MAX                     MK_ENUM_CONST(536870911)
+
+
+// Register TKE_TOP_TIMER_TMR15_TMRSR_0
+#define TKE_TOP_TIMER_TMR15_TMRSR_0                     MK_ADDR_CONST(0x100004)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_SECURE                      0x0
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_DUAL                        0x0
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_SCR                         TMRSCR15_0
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_SCRREG                      TKE_TOP_SCR_TMRSCR15_0
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_WORD_COUNT                  0x1
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_RESET_MASK                  MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_READ_MASK                   MK_MASK_CONST(0x5fffffff)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_WRITE_MASK                  MK_MASK_CONST(0x40000000)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_SHIFT                      MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_SHIFT)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_RANGE                      30:30
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_MSB                        MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_LSB                        MK_SHIFT_CONST(30)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_WOFFSET                    0x0
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_DISABLE                    MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_INTR_CLR_ENABLE                     MK_ENUM_CONST(1)
+
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_SHIFT                   MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_FIELD                   MK_FIELD_CONST(0x1fffffff, TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_SHIFT)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_RANGE                   28:0
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_MSB                     MK_SHIFT_CONST(28)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_LSB                     MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_WOFFSET                 0x0
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_DEFAULT_MASK                    MK_MASK_CONST(0x1fffffff)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRSR_0_PCV_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_TIMER_TMR15_TMRCSSR_0
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0                   MK_ADDR_CONST(0x100008)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SECURE                    0x0
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_DUAL                      0x0
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SCR                       TMRSCR15_0
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SCRREG                    TKE_TOP_SCR_TMRSCR15_0
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_WORD_COUNT                        0x1
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_RESET_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_READ_MASK                         MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_WRITE_MASK                        MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_SHIFT                      MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_FIELD                      MK_FIELD_CONST(0x3, TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_SHIFT)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_RANGE                      1:0
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_MSB                        MK_SHIFT_CONST(1)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_LSB                        MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_WOFFSET                    0x0
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_DEFAULT_MASK                       MK_MASK_CONST(0x3)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_SRC_USECCNT                        MK_ENUM_CONST(0)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_SRC_OSCCNT                 MK_ENUM_CONST(1)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_SRC_TSCCNT_29_0                    MK_ENUM_CONST(2)
+#define TKE_TOP_TIMER_TMR15_TMRCSSR_0_SRC_ID_SRC_TSCCNT_41_12                   MK_ENUM_CONST(3)
+
+
+// Register TKE_TOP_TIMER_TMR15_TMRATR_0
+#define TKE_TOP_TIMER_TMR15_TMRATR_0                    MK_ADDR_CONST(0x10000c)
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_SECURE                     0x0
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_DUAL                       0x0
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_SCR                        TMRSCR15_0
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_SCRREG                     TKE_TOP_SCR_TMRSCR15_0
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_WORD_COUNT                         0x1
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_RESET_MASK                         MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_READ_MASK                  MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_WRITE_MASK                         MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_FIELD                       MK_FIELD_CONST(0x3fffffff, TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_SHIFT)
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_RANGE                       29:0
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_MSB                 MK_SHIFT_CONST(29)
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_WOFFSET                     0x0
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_DEFAULT_MASK                        MK_MASK_CONST(0x3fffffff)
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_TIMER_TMR15_TMRATR_0_TARGET_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_WDT0_WDTCR_0
+#define TKE_TOP_WDT0_WDTCR_0                    MK_ADDR_CONST(0x110000)
+#define TKE_TOP_WDT0_WDTCR_0_SECURE                     0x0
+#define TKE_TOP_WDT0_WDTCR_0_DUAL                       0x0
+#define TKE_TOP_WDT0_WDTCR_0_SCR                        WDTSCR0_0
+#define TKE_TOP_WDT0_WDTCR_0_SCRREG                     TKE_TOP_SCR_WDTSCR0_0
+#define TKE_TOP_WDT0_WDTCR_0_WORD_COUNT                         0x1
+#define TKE_TOP_WDT0_WDTCR_0_RESET_VAL                  MK_MASK_CONST(0x700000)
+#define TKE_TOP_WDT0_WDTCR_0_RESET_MASK                         MK_MASK_CONST(0xf3ffffff)
+#define TKE_TOP_WDT0_WDTCR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_READ_MASK                  MK_MASK_CONST(0xf3ffffff)
+#define TKE_TOP_WDT0_WDTCR_0_WRITE_MASK                         MK_MASK_CONST(0xf3ffffff)
+#define TKE_TOP_WDT0_WDTCR_0_TimerSource_SHIFT                  MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT0_WDTCR_0_TimerSource_FIELD                  MK_FIELD_CONST(0xf, TKE_TOP_WDT0_WDTCR_0_TimerSource_SHIFT)
+#define TKE_TOP_WDT0_WDTCR_0_TimerSource_RANGE                  3:0
+#define TKE_TOP_WDT0_WDTCR_0_TimerSource_MSB                    MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT0_WDTCR_0_TimerSource_LSB                    MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT0_WDTCR_0_TimerSource_WOFFSET                        0x0
+#define TKE_TOP_WDT0_WDTCR_0_TimerSource_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_TimerSource_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define TKE_TOP_WDT0_WDTCR_0_TimerSource_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_TimerSource_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_TimerSource_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_TimerSource_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_TimerSource_TMR0                   MK_ENUM_CONST(0)
+
+#define TKE_TOP_WDT0_WDTCR_0_Period_SHIFT                       MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT0_WDTCR_0_Period_FIELD                       MK_FIELD_CONST(0xff, TKE_TOP_WDT0_WDTCR_0_Period_SHIFT)
+#define TKE_TOP_WDT0_WDTCR_0_Period_RANGE                       11:4
+#define TKE_TOP_WDT0_WDTCR_0_Period_MSB                 MK_SHIFT_CONST(11)
+#define TKE_TOP_WDT0_WDTCR_0_Period_LSB                 MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT0_WDTCR_0_Period_WOFFSET                     0x0
+#define TKE_TOP_WDT0_WDTCR_0_Period_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_Period_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define TKE_TOP_WDT0_WDTCR_0_Period_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_Period_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_Period_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_Period_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_SHIFT                 MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_SHIFT)
+#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_RANGE                 12:12
+#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_MSB                   MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_LSB                   MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_WOFFSET                       0x0
+#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_LocalInterruptEnable_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_SHIFT                       MK_SHIFT_CONST(13)
+#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_SHIFT)
+#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_RANGE                       13:13
+#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_MSB                 MK_SHIFT_CONST(13)
+#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_LSB                 MK_SHIFT_CONST(13)
+#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_WOFFSET                     0x0
+#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_LocalFIQEnable_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_SHIFT                        MK_SHIFT_CONST(14)
+#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_SHIFT)
+#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_RANGE                        14:14
+#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_MSB                  MK_SHIFT_CONST(14)
+#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_LSB                  MK_SHIFT_CONST(14)
+#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_WOFFSET                      0x0
+#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_RemoteInterruptEnable_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_SHIFT                       MK_SHIFT_CONST(15)
+#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_SHIFT)
+#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_RANGE                       15:15
+#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_MSB                 MK_SHIFT_CONST(15)
+#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_LSB                 MK_SHIFT_CONST(15)
+#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_WOFFSET                     0x0
+#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_SystemDebugResetEnable_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_SHIFT                  MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_FIELD                  MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_SHIFT)
+#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_RANGE                  16:16
+#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_MSB                    MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_LSB                    MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_WOFFSET                        0x0
+#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_DISABLE                        MK_ENUM_CONST(0)
+#define TKE_TOP_WDT0_WDTCR_0_SystemPOResetEnable_ENABLE                 MK_ENUM_CONST(1)
+
+#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_SHIFT                      MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_SHIFT)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_RANGE                      17:17
+#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_MSB                        MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_LSB                        MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_WOFFSET                    0x0
+#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedOperationEnable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_SHIFT                      MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_SHIFT)
+#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_RANGE                      18:18
+#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_MSB                        MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_LSB                        MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_WOFFSET                    0x0
+#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_ChallengeResponseEnable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_SHIFT                   MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_SHIFT)
+#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_RANGE                   19:19
+#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_MSB                     MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_LSB                     MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_WOFFSET                 0x0
+#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_TscReferenceEnable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_SHIFT                       MK_SHIFT_CONST(20)
+#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_SHIFT)
+#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_RANGE                       22:20
+#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_MSB                 MK_SHIFT_CONST(22)
+#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_LSB                 MK_SHIFT_CONST(20)
+#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_WOFFSET                     0x0
+#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_DEFAULT                     MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_ErrorThreshold_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_SHIFT                   MK_SHIFT_CONST(23)
+#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_FIELD                   MK_FIELD_CONST(0x3, TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_SHIFT)
+#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_RANGE                   24:23
+#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_MSB                     MK_SHIFT_CONST(24)
+#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_LSB                     MK_SHIFT_CONST(23)
+#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_WOFFSET                 0x0
+#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_NOP                     MK_ENUM_CONST(0)
+#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_JUMP_TO_4                       MK_ENUM_CONST(1)
+#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_JUMP_TO_5                       MK_ENUM_CONST(2)
+#define TKE_TOP_WDT0_WDTCR_0_RestartErrorAction_POR_RESET                       MK_ENUM_CONST(3)
+
+#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_SHIFT                    MK_SHIFT_CONST(25)
+#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_SHIFT)
+#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_RANGE                    25:25
+#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_MSB                      MK_SHIFT_CONST(25)
+#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_LSB                      MK_SHIFT_CONST(25)
+#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_WOFFSET                  0x0
+#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_DisallowWDTFreeze_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_SHIFT                    MK_SHIFT_CONST(28)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_FIELD                    MK_FIELD_CONST(0xf, TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_SHIFT)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_RANGE                    31:28
+#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_MSB                      MK_SHIFT_CONST(31)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_LSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_WOFFSET                  0x0
+#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_DEFAULT_MASK                     MK_MASK_CONST(0xf)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCR_0_WindowedRestartDisableMap_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_WDT0_WDTSR_0
+#define TKE_TOP_WDT0_WDTSR_0                    MK_ADDR_CONST(0x110004)
+#define TKE_TOP_WDT0_WDTSR_0_SECURE                     0x0
+#define TKE_TOP_WDT0_WDTSR_0_DUAL                       0x0
+#define TKE_TOP_WDT0_WDTSR_0_SCR                        WDTSCR0_0
+#define TKE_TOP_WDT0_WDTSR_0_SCRREG                     TKE_TOP_SCR_WDTSCR0_0
+#define TKE_TOP_WDT0_WDTSR_0_WORD_COUNT                         0x1
+#define TKE_TOP_WDT0_WDTSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_RESET_MASK                         MK_MASK_CONST(0xf7fff)
+#define TKE_TOP_WDT0_WDTSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_READ_MASK                  MK_MASK_CONST(0xf7fff)
+#define TKE_TOP_WDT0_WDTSR_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_Enabled_SHIFT                      MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT0_WDTSR_0_Enabled_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTSR_0_Enabled_SHIFT)
+#define TKE_TOP_WDT0_WDTSR_0_Enabled_RANGE                      0:0
+#define TKE_TOP_WDT0_WDTSR_0_Enabled_MSB                        MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT0_WDTSR_0_Enabled_LSB                        MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT0_WDTSR_0_Enabled_WOFFSET                    0x0
+#define TKE_TOP_WDT0_WDTSR_0_Enabled_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_Enabled_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTSR_0_Enabled_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_Enabled_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_Enabled_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_Enabled_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTSR_0_Enabled_DISABLE                    MK_ENUM_CONST(0)
+#define TKE_TOP_WDT0_WDTSR_0_Enabled_ENABLE                     MK_ENUM_CONST(1)
+
+#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_SHIFT                 MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_SHIFT)
+#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_RANGE                 1:1
+#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_MSB                   MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_LSB                   MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_WOFFSET                       0x0
+#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_LocalInterruptStatus_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_SHIFT                       MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_SHIFT)
+#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_RANGE                       2:2
+#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_MSB                 MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_LSB                 MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_WOFFSET                     0x0
+#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_LocalFIQStatus_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_SHIFT                        MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_SHIFT)
+#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_RANGE                        3:3
+#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_MSB                  MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_LSB                  MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_WOFFSET                      0x0
+#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_RemoteInterruptStatus_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_SHIFT                 MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_FIELD                 MK_FIELD_CONST(0xff, TKE_TOP_WDT0_WDTSR_0_CurrentCount_SHIFT)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_RANGE                 11:4
+#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_MSB                   MK_SHIFT_CONST(11)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_LSB                   MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_WOFFSET                       0x0
+#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentCount_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_SHIFT                       MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_SHIFT)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_RANGE                       14:12
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_MSB                 MK_SHIFT_CONST(14)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_LSB                 MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_WOFFSET                     0x0
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_NO_EXPIRY                   MK_ENUM_CONST(0)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_LOCAL_IRQ                   MK_ENUM_CONST(1)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_LOCAL_FIQ                   MK_ENUM_CONST(2)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_REMOTE_IRQ                  MK_ENUM_CONST(3)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_DEBUG_RESET                 MK_ENUM_CONST(4)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentExpirationCount_SYSTEM_RESET                        MK_ENUM_CONST(5)
+
+#define TKE_TOP_WDT0_WDTSR_0_CurrentError_SHIFT                 MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentError_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTSR_0_CurrentError_SHIFT)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentError_RANGE                 16:16
+#define TKE_TOP_WDT0_WDTSR_0_CurrentError_MSB                   MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentError_LSB                   MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentError_WOFFSET                       0x0
+#define TKE_TOP_WDT0_WDTSR_0_CurrentError_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentError_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentError_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentError_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentError_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_CurrentError_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_SHIFT                        MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTSR_0_StickyEnabled_SHIFT)
+#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_RANGE                        17:17
+#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_MSB                  MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_LSB                  MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_WOFFSET                      0x0
+#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_StickyEnabled_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_SHIFT                  MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_FIELD                  MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTSR_0_ErrorForced_SHIFT)
+#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_RANGE                  18:18
+#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_MSB                    MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_LSB                    MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_WOFFSET                        0x0
+#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_ErrorForced_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTSR_0_Frozen_SHIFT                       MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT0_WDTSR_0_Frozen_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTSR_0_Frozen_SHIFT)
+#define TKE_TOP_WDT0_WDTSR_0_Frozen_RANGE                       19:19
+#define TKE_TOP_WDT0_WDTSR_0_Frozen_MSB                 MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT0_WDTSR_0_Frozen_LSB                 MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT0_WDTSR_0_Frozen_WOFFSET                     0x0
+#define TKE_TOP_WDT0_WDTSR_0_Frozen_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_Frozen_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTSR_0_Frozen_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_Frozen_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_Frozen_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSR_0_Frozen_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_WDT0_WDTCMDR_0
+#define TKE_TOP_WDT0_WDTCMDR_0                  MK_ADDR_CONST(0x110008)
+#define TKE_TOP_WDT0_WDTCMDR_0_SECURE                   0x0
+#define TKE_TOP_WDT0_WDTCMDR_0_DUAL                     0x0
+#define TKE_TOP_WDT0_WDTCMDR_0_SCR                      WDTSCR0_0
+#define TKE_TOP_WDT0_WDTCMDR_0_SCRREG                   TKE_TOP_SCR_WDTSCR0_0
+#define TKE_TOP_WDT0_WDTCMDR_0_WORD_COUNT                       0x1
+#define TKE_TOP_WDT0_WDTCMDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCMDR_0_RESET_MASK                       MK_MASK_CONST(0xf)
+#define TKE_TOP_WDT0_WDTCMDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCMDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCMDR_0_READ_MASK                        MK_MASK_CONST(0xf)
+#define TKE_TOP_WDT0_WDTCMDR_0_WRITE_MASK                       MK_MASK_CONST(0xf)
+#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCMDR_0_StartCounter_SHIFT)
+#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_RANGE                       0:0
+#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_MSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_WOFFSET                     0x0
+#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_DISABLE                     MK_ENUM_CONST(0)
+#define TKE_TOP_WDT0_WDTCMDR_0_StartCounter_ENABLE                      MK_ENUM_CONST(1)
+
+#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_SHIFT                     MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_SHIFT)
+#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_RANGE                     1:1
+#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_MSB                       MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_LSB                       MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_WOFFSET                   0x0
+#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_DISABLE                   MK_ENUM_CONST(0)
+#define TKE_TOP_WDT0_WDTCMDR_0_DisableCounter_ENABLE                    MK_ENUM_CONST(1)
+
+#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_SHIFT                        MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCMDR_0_StickyStart_SHIFT)
+#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_RANGE                        2:2
+#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_MSB                  MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_LSB                  MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_WOFFSET                      0x0
+#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCMDR_0_StickyStart_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_SHIFT                 MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT0_WDTCMDR_0_ForceError_SHIFT)
+#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_RANGE                 3:3
+#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_MSB                   MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_LSB                   MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_WOFFSET                       0x0
+#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTCMDR_0_ForceError_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_WDT0_WDTUR_0
+#define TKE_TOP_WDT0_WDTUR_0                    MK_ADDR_CONST(0x11000c)
+#define TKE_TOP_WDT0_WDTUR_0_SECURE                     0x0
+#define TKE_TOP_WDT0_WDTUR_0_DUAL                       0x0
+#define TKE_TOP_WDT0_WDTUR_0_SCR                        WDTSCR0_0
+#define TKE_TOP_WDT0_WDTUR_0_SCRREG                     TKE_TOP_SCR_WDTSCR0_0
+#define TKE_TOP_WDT0_WDTUR_0_WORD_COUNT                         0x1
+#define TKE_TOP_WDT0_WDTUR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTUR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_WDT0_WDTUR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTUR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTUR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_WDT0_WDTUR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_WDT0_WDTUR_0_UnlockPattern_SHIFT)
+#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_RANGE                        31:0
+#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_MSB                  MK_SHIFT_CONST(31)
+#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_WOFFSET                      0x0
+#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTUR_0_UnlockPattern_UNLOCK                       MK_ENUM_CONST(50266)
+
+
+// Register TKE_TOP_WDT0_WDTSCR_0
+#define TKE_TOP_WDT0_WDTSCR_0                   MK_ADDR_CONST(0x110010)
+#define TKE_TOP_WDT0_WDTSCR_0_SECURE                    0x0
+#define TKE_TOP_WDT0_WDTSCR_0_DUAL                      0x0
+#define TKE_TOP_WDT0_WDTSCR_0_SCR                       WDTSCR0_0
+#define TKE_TOP_WDT0_WDTSCR_0_SCRREG                    TKE_TOP_SCR_WDTSCR0_0
+#define TKE_TOP_WDT0_WDTSCR_0_WORD_COUNT                        0x1
+#define TKE_TOP_WDT0_WDTSCR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSCR_0_RESET_MASK                        MK_MASK_CONST(0x7777)
+#define TKE_TOP_WDT0_WDTSCR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSCR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSCR_0_READ_MASK                         MK_MASK_CONST(0x7777)
+#define TKE_TOP_WDT0_WDTSCR_0_WRITE_MASK                        MK_MASK_CONST(0x7777)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip0_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip0_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT0_WDTSCR_0_Skip0_SHIFT)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip0_RANGE                       2:0
+#define TKE_TOP_WDT0_WDTSCR_0_Skip0_MSB                 MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip0_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip0_WOFFSET                     0x0
+#define TKE_TOP_WDT0_WDTSCR_0_Skip0_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip0_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTSCR_0_Skip1_SHIFT                       MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip1_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT0_WDTSCR_0_Skip1_SHIFT)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip1_RANGE                       6:4
+#define TKE_TOP_WDT0_WDTSCR_0_Skip1_MSB                 MK_SHIFT_CONST(6)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip1_LSB                 MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip1_WOFFSET                     0x0
+#define TKE_TOP_WDT0_WDTSCR_0_Skip1_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip1_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTSCR_0_Skip2_SHIFT                       MK_SHIFT_CONST(8)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip2_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT0_WDTSCR_0_Skip2_SHIFT)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip2_RANGE                       10:8
+#define TKE_TOP_WDT0_WDTSCR_0_Skip2_MSB                 MK_SHIFT_CONST(10)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip2_LSB                 MK_SHIFT_CONST(8)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip2_WOFFSET                     0x0
+#define TKE_TOP_WDT0_WDTSCR_0_Skip2_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip2_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTSCR_0_Skip3_SHIFT                       MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip3_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT0_WDTSCR_0_Skip3_SHIFT)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip3_RANGE                       14:12
+#define TKE_TOP_WDT0_WDTSCR_0_Skip3_MSB                 MK_SHIFT_CONST(14)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip3_LSB                 MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip3_WOFFSET                     0x0
+#define TKE_TOP_WDT0_WDTSCR_0_Skip3_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip3_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTSCR_0_Skip3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_WDT0_WDTFWCR_0
+#define TKE_TOP_WDT0_WDTFWCR_0                  MK_ADDR_CONST(0x110014)
+#define TKE_TOP_WDT0_WDTFWCR_0_SECURE                   0x0
+#define TKE_TOP_WDT0_WDTFWCR_0_DUAL                     0x0
+#define TKE_TOP_WDT0_WDTFWCR_0_SCR                      WDTSCR0_0
+#define TKE_TOP_WDT0_WDTFWCR_0_SCRREG                   TKE_TOP_SCR_WDTSCR0_0
+#define TKE_TOP_WDT0_WDTFWCR_0_WORD_COUNT                       0x1
+#define TKE_TOP_WDT0_WDTFWCR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTFWCR_0_RESET_MASK                       MK_MASK_CONST(0x700ff)
+#define TKE_TOP_WDT0_WDTFWCR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTFWCR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTFWCR_0_READ_MASK                        MK_MASK_CONST(0x700ff)
+#define TKE_TOP_WDT0_WDTFWCR_0_WRITE_MASK                       MK_MASK_CONST(0x700ff)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_SHIFT                 MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_FIELD                 MK_FIELD_CONST(0xff, TKE_TOP_WDT0_WDTFWCR_0_StartCount_SHIFT)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_RANGE                 7:0
+#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_MSB                   MK_SHIFT_CONST(7)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_LSB                   MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_WOFFSET                       0x0
+#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartCount_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_SHIFT                 MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_FIELD                 MK_FIELD_CONST(0x7, TKE_TOP_WDT0_WDTFWCR_0_StartLevel_SHIFT)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_RANGE                 18:16
+#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_MSB                   MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_LSB                   MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_WOFFSET                       0x0
+#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT0_WDTFWCR_0_StartLevel_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_WDT1_WDTCR_0
+#define TKE_TOP_WDT1_WDTCR_0                    MK_ADDR_CONST(0x120000)
+#define TKE_TOP_WDT1_WDTCR_0_SECURE                     0x0
+#define TKE_TOP_WDT1_WDTCR_0_DUAL                       0x0
+#define TKE_TOP_WDT1_WDTCR_0_SCR                        WDTSCR1_0
+#define TKE_TOP_WDT1_WDTCR_0_SCRREG                     TKE_TOP_SCR_WDTSCR1_0
+#define TKE_TOP_WDT1_WDTCR_0_WORD_COUNT                         0x1
+#define TKE_TOP_WDT1_WDTCR_0_RESET_VAL                  MK_MASK_CONST(0x700000)
+#define TKE_TOP_WDT1_WDTCR_0_RESET_MASK                         MK_MASK_CONST(0xf3ffffff)
+#define TKE_TOP_WDT1_WDTCR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_READ_MASK                  MK_MASK_CONST(0xf3ffffff)
+#define TKE_TOP_WDT1_WDTCR_0_WRITE_MASK                         MK_MASK_CONST(0xf3ffffff)
+#define TKE_TOP_WDT1_WDTCR_0_TimerSource_SHIFT                  MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT1_WDTCR_0_TimerSource_FIELD                  MK_FIELD_CONST(0xf, TKE_TOP_WDT1_WDTCR_0_TimerSource_SHIFT)
+#define TKE_TOP_WDT1_WDTCR_0_TimerSource_RANGE                  3:0
+#define TKE_TOP_WDT1_WDTCR_0_TimerSource_MSB                    MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT1_WDTCR_0_TimerSource_LSB                    MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT1_WDTCR_0_TimerSource_WOFFSET                        0x0
+#define TKE_TOP_WDT1_WDTCR_0_TimerSource_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_TimerSource_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define TKE_TOP_WDT1_WDTCR_0_TimerSource_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_TimerSource_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_TimerSource_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_TimerSource_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_TimerSource_TMR0                   MK_ENUM_CONST(0)
+
+#define TKE_TOP_WDT1_WDTCR_0_Period_SHIFT                       MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT1_WDTCR_0_Period_FIELD                       MK_FIELD_CONST(0xff, TKE_TOP_WDT1_WDTCR_0_Period_SHIFT)
+#define TKE_TOP_WDT1_WDTCR_0_Period_RANGE                       11:4
+#define TKE_TOP_WDT1_WDTCR_0_Period_MSB                 MK_SHIFT_CONST(11)
+#define TKE_TOP_WDT1_WDTCR_0_Period_LSB                 MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT1_WDTCR_0_Period_WOFFSET                     0x0
+#define TKE_TOP_WDT1_WDTCR_0_Period_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_Period_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define TKE_TOP_WDT1_WDTCR_0_Period_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_Period_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_Period_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_Period_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_SHIFT                 MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_SHIFT)
+#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_RANGE                 12:12
+#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_MSB                   MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_LSB                   MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_WOFFSET                       0x0
+#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_LocalInterruptEnable_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_SHIFT                       MK_SHIFT_CONST(13)
+#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_SHIFT)
+#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_RANGE                       13:13
+#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_MSB                 MK_SHIFT_CONST(13)
+#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_LSB                 MK_SHIFT_CONST(13)
+#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_WOFFSET                     0x0
+#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_LocalFIQEnable_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_SHIFT                        MK_SHIFT_CONST(14)
+#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_SHIFT)
+#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_RANGE                        14:14
+#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_MSB                  MK_SHIFT_CONST(14)
+#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_LSB                  MK_SHIFT_CONST(14)
+#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_WOFFSET                      0x0
+#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_RemoteInterruptEnable_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_SHIFT                       MK_SHIFT_CONST(15)
+#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_SHIFT)
+#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_RANGE                       15:15
+#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_MSB                 MK_SHIFT_CONST(15)
+#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_LSB                 MK_SHIFT_CONST(15)
+#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_WOFFSET                     0x0
+#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_SystemDebugResetEnable_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_SHIFT                  MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_FIELD                  MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_SHIFT)
+#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_RANGE                  16:16
+#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_MSB                    MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_LSB                    MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_WOFFSET                        0x0
+#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_DISABLE                        MK_ENUM_CONST(0)
+#define TKE_TOP_WDT1_WDTCR_0_SystemPOResetEnable_ENABLE                 MK_ENUM_CONST(1)
+
+#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_SHIFT                      MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_SHIFT)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_RANGE                      17:17
+#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_MSB                        MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_LSB                        MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_WOFFSET                    0x0
+#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedOperationEnable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_SHIFT                      MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_SHIFT)
+#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_RANGE                      18:18
+#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_MSB                        MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_LSB                        MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_WOFFSET                    0x0
+#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_ChallengeResponseEnable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_SHIFT                   MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_SHIFT)
+#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_RANGE                   19:19
+#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_MSB                     MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_LSB                     MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_WOFFSET                 0x0
+#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_TscReferenceEnable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_SHIFT                       MK_SHIFT_CONST(20)
+#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_SHIFT)
+#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_RANGE                       22:20
+#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_MSB                 MK_SHIFT_CONST(22)
+#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_LSB                 MK_SHIFT_CONST(20)
+#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_WOFFSET                     0x0
+#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_DEFAULT                     MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_ErrorThreshold_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_SHIFT                   MK_SHIFT_CONST(23)
+#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_FIELD                   MK_FIELD_CONST(0x3, TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_SHIFT)
+#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_RANGE                   24:23
+#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_MSB                     MK_SHIFT_CONST(24)
+#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_LSB                     MK_SHIFT_CONST(23)
+#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_WOFFSET                 0x0
+#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_NOP                     MK_ENUM_CONST(0)
+#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_JUMP_TO_4                       MK_ENUM_CONST(1)
+#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_JUMP_TO_5                       MK_ENUM_CONST(2)
+#define TKE_TOP_WDT1_WDTCR_0_RestartErrorAction_POR_RESET                       MK_ENUM_CONST(3)
+
+#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_SHIFT                    MK_SHIFT_CONST(25)
+#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_SHIFT)
+#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_RANGE                    25:25
+#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_MSB                      MK_SHIFT_CONST(25)
+#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_LSB                      MK_SHIFT_CONST(25)
+#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_WOFFSET                  0x0
+#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_DisallowWDTFreeze_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_SHIFT                    MK_SHIFT_CONST(28)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_FIELD                    MK_FIELD_CONST(0xf, TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_SHIFT)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_RANGE                    31:28
+#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_MSB                      MK_SHIFT_CONST(31)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_LSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_WOFFSET                  0x0
+#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_DEFAULT_MASK                     MK_MASK_CONST(0xf)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCR_0_WindowedRestartDisableMap_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_WDT1_WDTSR_0
+#define TKE_TOP_WDT1_WDTSR_0                    MK_ADDR_CONST(0x120004)
+#define TKE_TOP_WDT1_WDTSR_0_SECURE                     0x0
+#define TKE_TOP_WDT1_WDTSR_0_DUAL                       0x0
+#define TKE_TOP_WDT1_WDTSR_0_SCR                        WDTSCR1_0
+#define TKE_TOP_WDT1_WDTSR_0_SCRREG                     TKE_TOP_SCR_WDTSCR1_0
+#define TKE_TOP_WDT1_WDTSR_0_WORD_COUNT                         0x1
+#define TKE_TOP_WDT1_WDTSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_RESET_MASK                         MK_MASK_CONST(0xf7fff)
+#define TKE_TOP_WDT1_WDTSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_READ_MASK                  MK_MASK_CONST(0xf7fff)
+#define TKE_TOP_WDT1_WDTSR_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_Enabled_SHIFT                      MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT1_WDTSR_0_Enabled_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTSR_0_Enabled_SHIFT)
+#define TKE_TOP_WDT1_WDTSR_0_Enabled_RANGE                      0:0
+#define TKE_TOP_WDT1_WDTSR_0_Enabled_MSB                        MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT1_WDTSR_0_Enabled_LSB                        MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT1_WDTSR_0_Enabled_WOFFSET                    0x0
+#define TKE_TOP_WDT1_WDTSR_0_Enabled_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_Enabled_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTSR_0_Enabled_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_Enabled_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_Enabled_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_Enabled_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTSR_0_Enabled_DISABLE                    MK_ENUM_CONST(0)
+#define TKE_TOP_WDT1_WDTSR_0_Enabled_ENABLE                     MK_ENUM_CONST(1)
+
+#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_SHIFT                 MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_SHIFT)
+#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_RANGE                 1:1
+#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_MSB                   MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_LSB                   MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_WOFFSET                       0x0
+#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_LocalInterruptStatus_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_SHIFT                       MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_SHIFT)
+#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_RANGE                       2:2
+#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_MSB                 MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_LSB                 MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_WOFFSET                     0x0
+#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_LocalFIQStatus_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_SHIFT                        MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_SHIFT)
+#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_RANGE                        3:3
+#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_MSB                  MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_LSB                  MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_WOFFSET                      0x0
+#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_RemoteInterruptStatus_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_SHIFT                 MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_FIELD                 MK_FIELD_CONST(0xff, TKE_TOP_WDT1_WDTSR_0_CurrentCount_SHIFT)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_RANGE                 11:4
+#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_MSB                   MK_SHIFT_CONST(11)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_LSB                   MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_WOFFSET                       0x0
+#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentCount_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_SHIFT                       MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_SHIFT)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_RANGE                       14:12
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_MSB                 MK_SHIFT_CONST(14)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_LSB                 MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_WOFFSET                     0x0
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_NO_EXPIRY                   MK_ENUM_CONST(0)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_LOCAL_IRQ                   MK_ENUM_CONST(1)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_LOCAL_FIQ                   MK_ENUM_CONST(2)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_REMOTE_IRQ                  MK_ENUM_CONST(3)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_DEBUG_RESET                 MK_ENUM_CONST(4)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentExpirationCount_SYSTEM_RESET                        MK_ENUM_CONST(5)
+
+#define TKE_TOP_WDT1_WDTSR_0_CurrentError_SHIFT                 MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentError_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTSR_0_CurrentError_SHIFT)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentError_RANGE                 16:16
+#define TKE_TOP_WDT1_WDTSR_0_CurrentError_MSB                   MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentError_LSB                   MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentError_WOFFSET                       0x0
+#define TKE_TOP_WDT1_WDTSR_0_CurrentError_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentError_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentError_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentError_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentError_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_CurrentError_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_SHIFT                        MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTSR_0_StickyEnabled_SHIFT)
+#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_RANGE                        17:17
+#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_MSB                  MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_LSB                  MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_WOFFSET                      0x0
+#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_StickyEnabled_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_SHIFT                  MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_FIELD                  MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTSR_0_ErrorForced_SHIFT)
+#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_RANGE                  18:18
+#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_MSB                    MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_LSB                    MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_WOFFSET                        0x0
+#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_ErrorForced_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTSR_0_Frozen_SHIFT                       MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT1_WDTSR_0_Frozen_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTSR_0_Frozen_SHIFT)
+#define TKE_TOP_WDT1_WDTSR_0_Frozen_RANGE                       19:19
+#define TKE_TOP_WDT1_WDTSR_0_Frozen_MSB                 MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT1_WDTSR_0_Frozen_LSB                 MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT1_WDTSR_0_Frozen_WOFFSET                     0x0
+#define TKE_TOP_WDT1_WDTSR_0_Frozen_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_Frozen_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTSR_0_Frozen_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_Frozen_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_Frozen_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSR_0_Frozen_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_WDT1_WDTCMDR_0
+#define TKE_TOP_WDT1_WDTCMDR_0                  MK_ADDR_CONST(0x120008)
+#define TKE_TOP_WDT1_WDTCMDR_0_SECURE                   0x0
+#define TKE_TOP_WDT1_WDTCMDR_0_DUAL                     0x0
+#define TKE_TOP_WDT1_WDTCMDR_0_SCR                      WDTSCR1_0
+#define TKE_TOP_WDT1_WDTCMDR_0_SCRREG                   TKE_TOP_SCR_WDTSCR1_0
+#define TKE_TOP_WDT1_WDTCMDR_0_WORD_COUNT                       0x1
+#define TKE_TOP_WDT1_WDTCMDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCMDR_0_RESET_MASK                       MK_MASK_CONST(0xf)
+#define TKE_TOP_WDT1_WDTCMDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCMDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCMDR_0_READ_MASK                        MK_MASK_CONST(0xf)
+#define TKE_TOP_WDT1_WDTCMDR_0_WRITE_MASK                       MK_MASK_CONST(0xf)
+#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCMDR_0_StartCounter_SHIFT)
+#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_RANGE                       0:0
+#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_MSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_WOFFSET                     0x0
+#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_DISABLE                     MK_ENUM_CONST(0)
+#define TKE_TOP_WDT1_WDTCMDR_0_StartCounter_ENABLE                      MK_ENUM_CONST(1)
+
+#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_SHIFT                     MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_SHIFT)
+#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_RANGE                     1:1
+#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_MSB                       MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_LSB                       MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_WOFFSET                   0x0
+#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_DISABLE                   MK_ENUM_CONST(0)
+#define TKE_TOP_WDT1_WDTCMDR_0_DisableCounter_ENABLE                    MK_ENUM_CONST(1)
+
+#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_SHIFT                        MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCMDR_0_StickyStart_SHIFT)
+#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_RANGE                        2:2
+#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_MSB                  MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_LSB                  MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_WOFFSET                      0x0
+#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCMDR_0_StickyStart_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_SHIFT                 MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT1_WDTCMDR_0_ForceError_SHIFT)
+#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_RANGE                 3:3
+#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_MSB                   MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_LSB                   MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_WOFFSET                       0x0
+#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTCMDR_0_ForceError_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_WDT1_WDTUR_0
+#define TKE_TOP_WDT1_WDTUR_0                    MK_ADDR_CONST(0x12000c)
+#define TKE_TOP_WDT1_WDTUR_0_SECURE                     0x0
+#define TKE_TOP_WDT1_WDTUR_0_DUAL                       0x0
+#define TKE_TOP_WDT1_WDTUR_0_SCR                        WDTSCR1_0
+#define TKE_TOP_WDT1_WDTUR_0_SCRREG                     TKE_TOP_SCR_WDTSCR1_0
+#define TKE_TOP_WDT1_WDTUR_0_WORD_COUNT                         0x1
+#define TKE_TOP_WDT1_WDTUR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTUR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_WDT1_WDTUR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTUR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTUR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_WDT1_WDTUR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_WDT1_WDTUR_0_UnlockPattern_SHIFT)
+#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_RANGE                        31:0
+#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_MSB                  MK_SHIFT_CONST(31)
+#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_WOFFSET                      0x0
+#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTUR_0_UnlockPattern_UNLOCK                       MK_ENUM_CONST(50266)
+
+
+// Register TKE_TOP_WDT1_WDTSCR_0
+#define TKE_TOP_WDT1_WDTSCR_0                   MK_ADDR_CONST(0x120010)
+#define TKE_TOP_WDT1_WDTSCR_0_SECURE                    0x0
+#define TKE_TOP_WDT1_WDTSCR_0_DUAL                      0x0
+#define TKE_TOP_WDT1_WDTSCR_0_SCR                       WDTSCR1_0
+#define TKE_TOP_WDT1_WDTSCR_0_SCRREG                    TKE_TOP_SCR_WDTSCR1_0
+#define TKE_TOP_WDT1_WDTSCR_0_WORD_COUNT                        0x1
+#define TKE_TOP_WDT1_WDTSCR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSCR_0_RESET_MASK                        MK_MASK_CONST(0x7777)
+#define TKE_TOP_WDT1_WDTSCR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSCR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSCR_0_READ_MASK                         MK_MASK_CONST(0x7777)
+#define TKE_TOP_WDT1_WDTSCR_0_WRITE_MASK                        MK_MASK_CONST(0x7777)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip0_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip0_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT1_WDTSCR_0_Skip0_SHIFT)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip0_RANGE                       2:0
+#define TKE_TOP_WDT1_WDTSCR_0_Skip0_MSB                 MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip0_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip0_WOFFSET                     0x0
+#define TKE_TOP_WDT1_WDTSCR_0_Skip0_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip0_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTSCR_0_Skip1_SHIFT                       MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip1_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT1_WDTSCR_0_Skip1_SHIFT)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip1_RANGE                       6:4
+#define TKE_TOP_WDT1_WDTSCR_0_Skip1_MSB                 MK_SHIFT_CONST(6)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip1_LSB                 MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip1_WOFFSET                     0x0
+#define TKE_TOP_WDT1_WDTSCR_0_Skip1_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip1_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTSCR_0_Skip2_SHIFT                       MK_SHIFT_CONST(8)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip2_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT1_WDTSCR_0_Skip2_SHIFT)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip2_RANGE                       10:8
+#define TKE_TOP_WDT1_WDTSCR_0_Skip2_MSB                 MK_SHIFT_CONST(10)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip2_LSB                 MK_SHIFT_CONST(8)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip2_WOFFSET                     0x0
+#define TKE_TOP_WDT1_WDTSCR_0_Skip2_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip2_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTSCR_0_Skip3_SHIFT                       MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip3_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT1_WDTSCR_0_Skip3_SHIFT)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip3_RANGE                       14:12
+#define TKE_TOP_WDT1_WDTSCR_0_Skip3_MSB                 MK_SHIFT_CONST(14)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip3_LSB                 MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip3_WOFFSET                     0x0
+#define TKE_TOP_WDT1_WDTSCR_0_Skip3_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip3_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTSCR_0_Skip3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_WDT1_WDTFWCR_0
+#define TKE_TOP_WDT1_WDTFWCR_0                  MK_ADDR_CONST(0x120014)
+#define TKE_TOP_WDT1_WDTFWCR_0_SECURE                   0x0
+#define TKE_TOP_WDT1_WDTFWCR_0_DUAL                     0x0
+#define TKE_TOP_WDT1_WDTFWCR_0_SCR                      WDTSCR1_0
+#define TKE_TOP_WDT1_WDTFWCR_0_SCRREG                   TKE_TOP_SCR_WDTSCR1_0
+#define TKE_TOP_WDT1_WDTFWCR_0_WORD_COUNT                       0x1
+#define TKE_TOP_WDT1_WDTFWCR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTFWCR_0_RESET_MASK                       MK_MASK_CONST(0x700ff)
+#define TKE_TOP_WDT1_WDTFWCR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTFWCR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTFWCR_0_READ_MASK                        MK_MASK_CONST(0x700ff)
+#define TKE_TOP_WDT1_WDTFWCR_0_WRITE_MASK                       MK_MASK_CONST(0x700ff)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_SHIFT                 MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_FIELD                 MK_FIELD_CONST(0xff, TKE_TOP_WDT1_WDTFWCR_0_StartCount_SHIFT)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_RANGE                 7:0
+#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_MSB                   MK_SHIFT_CONST(7)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_LSB                   MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_WOFFSET                       0x0
+#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartCount_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_SHIFT                 MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_FIELD                 MK_FIELD_CONST(0x7, TKE_TOP_WDT1_WDTFWCR_0_StartLevel_SHIFT)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_RANGE                 18:16
+#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_MSB                   MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_LSB                   MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_WOFFSET                       0x0
+#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT1_WDTFWCR_0_StartLevel_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_WDT2_WDTCR_0
+#define TKE_TOP_WDT2_WDTCR_0                    MK_ADDR_CONST(0x130000)
+#define TKE_TOP_WDT2_WDTCR_0_SECURE                     0x0
+#define TKE_TOP_WDT2_WDTCR_0_DUAL                       0x0
+#define TKE_TOP_WDT2_WDTCR_0_SCR                        WDTSCR2_0
+#define TKE_TOP_WDT2_WDTCR_0_SCRREG                     TKE_TOP_SCR_WDTSCR2_0
+#define TKE_TOP_WDT2_WDTCR_0_WORD_COUNT                         0x1
+#define TKE_TOP_WDT2_WDTCR_0_RESET_VAL                  MK_MASK_CONST(0x700000)
+#define TKE_TOP_WDT2_WDTCR_0_RESET_MASK                         MK_MASK_CONST(0xf3ffffff)
+#define TKE_TOP_WDT2_WDTCR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_READ_MASK                  MK_MASK_CONST(0xf3ffffff)
+#define TKE_TOP_WDT2_WDTCR_0_WRITE_MASK                         MK_MASK_CONST(0xf3ffffff)
+#define TKE_TOP_WDT2_WDTCR_0_TimerSource_SHIFT                  MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT2_WDTCR_0_TimerSource_FIELD                  MK_FIELD_CONST(0xf, TKE_TOP_WDT2_WDTCR_0_TimerSource_SHIFT)
+#define TKE_TOP_WDT2_WDTCR_0_TimerSource_RANGE                  3:0
+#define TKE_TOP_WDT2_WDTCR_0_TimerSource_MSB                    MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT2_WDTCR_0_TimerSource_LSB                    MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT2_WDTCR_0_TimerSource_WOFFSET                        0x0
+#define TKE_TOP_WDT2_WDTCR_0_TimerSource_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_TimerSource_DEFAULT_MASK                   MK_MASK_CONST(0xf)
+#define TKE_TOP_WDT2_WDTCR_0_TimerSource_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_TimerSource_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_TimerSource_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_TimerSource_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_TimerSource_TMR0                   MK_ENUM_CONST(0)
+
+#define TKE_TOP_WDT2_WDTCR_0_Period_SHIFT                       MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT2_WDTCR_0_Period_FIELD                       MK_FIELD_CONST(0xff, TKE_TOP_WDT2_WDTCR_0_Period_SHIFT)
+#define TKE_TOP_WDT2_WDTCR_0_Period_RANGE                       11:4
+#define TKE_TOP_WDT2_WDTCR_0_Period_MSB                 MK_SHIFT_CONST(11)
+#define TKE_TOP_WDT2_WDTCR_0_Period_LSB                 MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT2_WDTCR_0_Period_WOFFSET                     0x0
+#define TKE_TOP_WDT2_WDTCR_0_Period_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_Period_DEFAULT_MASK                        MK_MASK_CONST(0xff)
+#define TKE_TOP_WDT2_WDTCR_0_Period_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_Period_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_Period_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_Period_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_SHIFT                 MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_SHIFT)
+#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_RANGE                 12:12
+#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_MSB                   MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_LSB                   MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_WOFFSET                       0x0
+#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_LocalInterruptEnable_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_SHIFT                       MK_SHIFT_CONST(13)
+#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_SHIFT)
+#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_RANGE                       13:13
+#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_MSB                 MK_SHIFT_CONST(13)
+#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_LSB                 MK_SHIFT_CONST(13)
+#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_WOFFSET                     0x0
+#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_LocalFIQEnable_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_SHIFT                        MK_SHIFT_CONST(14)
+#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_SHIFT)
+#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_RANGE                        14:14
+#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_MSB                  MK_SHIFT_CONST(14)
+#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_LSB                  MK_SHIFT_CONST(14)
+#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_WOFFSET                      0x0
+#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_RemoteInterruptEnable_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_SHIFT                       MK_SHIFT_CONST(15)
+#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_SHIFT)
+#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_RANGE                       15:15
+#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_MSB                 MK_SHIFT_CONST(15)
+#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_LSB                 MK_SHIFT_CONST(15)
+#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_WOFFSET                     0x0
+#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_SystemDebugResetEnable_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_SHIFT                  MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_FIELD                  MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_SHIFT)
+#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_RANGE                  16:16
+#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_MSB                    MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_LSB                    MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_WOFFSET                        0x0
+#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_PARITY_PROTECTION                      MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_DISABLE                        MK_ENUM_CONST(0)
+#define TKE_TOP_WDT2_WDTCR_0_SystemPOResetEnable_ENABLE                 MK_ENUM_CONST(1)
+
+#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_SHIFT                      MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_SHIFT)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_RANGE                      17:17
+#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_MSB                        MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_LSB                        MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_WOFFSET                    0x0
+#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedOperationEnable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_SHIFT                      MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_SHIFT)
+#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_RANGE                      18:18
+#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_MSB                        MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_LSB                        MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_WOFFSET                    0x0
+#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_PARITY_PROTECTION                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_ChallengeResponseEnable_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_SHIFT                   MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_FIELD                   MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_SHIFT)
+#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_RANGE                   19:19
+#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_MSB                     MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_LSB                     MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_WOFFSET                 0x0
+#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_TscReferenceEnable_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_SHIFT                       MK_SHIFT_CONST(20)
+#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_SHIFT)
+#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_RANGE                       22:20
+#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_MSB                 MK_SHIFT_CONST(22)
+#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_LSB                 MK_SHIFT_CONST(20)
+#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_WOFFSET                     0x0
+#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_DEFAULT                     MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_ErrorThreshold_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_SHIFT                   MK_SHIFT_CONST(23)
+#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_FIELD                   MK_FIELD_CONST(0x3, TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_SHIFT)
+#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_RANGE                   24:23
+#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_MSB                     MK_SHIFT_CONST(24)
+#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_LSB                     MK_SHIFT_CONST(23)
+#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_WOFFSET                 0x0
+#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_DEFAULT_MASK                    MK_MASK_CONST(0x3)
+#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_PARITY_PROTECTION                       MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_NOP                     MK_ENUM_CONST(0)
+#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_JUMP_TO_4                       MK_ENUM_CONST(1)
+#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_JUMP_TO_5                       MK_ENUM_CONST(2)
+#define TKE_TOP_WDT2_WDTCR_0_RestartErrorAction_POR_RESET                       MK_ENUM_CONST(3)
+
+#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_SHIFT                    MK_SHIFT_CONST(25)
+#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_FIELD                    MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_SHIFT)
+#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_RANGE                    25:25
+#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_MSB                      MK_SHIFT_CONST(25)
+#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_LSB                      MK_SHIFT_CONST(25)
+#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_WOFFSET                  0x0
+#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_DisallowWDTFreeze_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_SHIFT                    MK_SHIFT_CONST(28)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_FIELD                    MK_FIELD_CONST(0xf, TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_SHIFT)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_RANGE                    31:28
+#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_MSB                      MK_SHIFT_CONST(31)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_LSB                      MK_SHIFT_CONST(28)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_WOFFSET                  0x0
+#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_DEFAULT_MASK                     MK_MASK_CONST(0xf)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_PARITY_PROTECTION                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCR_0_WindowedRestartDisableMap_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_WDT2_WDTSR_0
+#define TKE_TOP_WDT2_WDTSR_0                    MK_ADDR_CONST(0x130004)
+#define TKE_TOP_WDT2_WDTSR_0_SECURE                     0x0
+#define TKE_TOP_WDT2_WDTSR_0_DUAL                       0x0
+#define TKE_TOP_WDT2_WDTSR_0_SCR                        WDTSCR2_0
+#define TKE_TOP_WDT2_WDTSR_0_SCRREG                     TKE_TOP_SCR_WDTSCR2_0
+#define TKE_TOP_WDT2_WDTSR_0_WORD_COUNT                         0x1
+#define TKE_TOP_WDT2_WDTSR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_RESET_MASK                         MK_MASK_CONST(0xf7fff)
+#define TKE_TOP_WDT2_WDTSR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_READ_MASK                  MK_MASK_CONST(0xf7fff)
+#define TKE_TOP_WDT2_WDTSR_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_Enabled_SHIFT                      MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT2_WDTSR_0_Enabled_FIELD                      MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTSR_0_Enabled_SHIFT)
+#define TKE_TOP_WDT2_WDTSR_0_Enabled_RANGE                      0:0
+#define TKE_TOP_WDT2_WDTSR_0_Enabled_MSB                        MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT2_WDTSR_0_Enabled_LSB                        MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT2_WDTSR_0_Enabled_WOFFSET                    0x0
+#define TKE_TOP_WDT2_WDTSR_0_Enabled_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_Enabled_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTSR_0_Enabled_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_Enabled_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_Enabled_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_Enabled_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTSR_0_Enabled_DISABLE                    MK_ENUM_CONST(0)
+#define TKE_TOP_WDT2_WDTSR_0_Enabled_ENABLE                     MK_ENUM_CONST(1)
+
+#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_SHIFT                 MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_SHIFT)
+#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_RANGE                 1:1
+#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_MSB                   MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_LSB                   MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_WOFFSET                       0x0
+#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_LocalInterruptStatus_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_SHIFT                       MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_SHIFT)
+#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_RANGE                       2:2
+#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_MSB                 MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_LSB                 MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_WOFFSET                     0x0
+#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_LocalFIQStatus_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_SHIFT                        MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_SHIFT)
+#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_RANGE                        3:3
+#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_MSB                  MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_LSB                  MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_WOFFSET                      0x0
+#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_RemoteInterruptStatus_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_SHIFT                 MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_FIELD                 MK_FIELD_CONST(0xff, TKE_TOP_WDT2_WDTSR_0_CurrentCount_SHIFT)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_RANGE                 11:4
+#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_MSB                   MK_SHIFT_CONST(11)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_LSB                   MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_WOFFSET                       0x0
+#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentCount_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_SHIFT                       MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_SHIFT)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_RANGE                       14:12
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_MSB                 MK_SHIFT_CONST(14)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_LSB                 MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_WOFFSET                     0x0
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_NO_EXPIRY                   MK_ENUM_CONST(0)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_LOCAL_IRQ                   MK_ENUM_CONST(1)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_LOCAL_FIQ                   MK_ENUM_CONST(2)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_REMOTE_IRQ                  MK_ENUM_CONST(3)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_DEBUG_RESET                 MK_ENUM_CONST(4)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentExpirationCount_SYSTEM_RESET                        MK_ENUM_CONST(5)
+
+#define TKE_TOP_WDT2_WDTSR_0_CurrentError_SHIFT                 MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentError_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTSR_0_CurrentError_SHIFT)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentError_RANGE                 16:16
+#define TKE_TOP_WDT2_WDTSR_0_CurrentError_MSB                   MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentError_LSB                   MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentError_WOFFSET                       0x0
+#define TKE_TOP_WDT2_WDTSR_0_CurrentError_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentError_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentError_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentError_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentError_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_CurrentError_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_SHIFT                        MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTSR_0_StickyEnabled_SHIFT)
+#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_RANGE                        17:17
+#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_MSB                  MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_LSB                  MK_SHIFT_CONST(17)
+#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_WOFFSET                      0x0
+#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_StickyEnabled_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_SHIFT                  MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_FIELD                  MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTSR_0_ErrorForced_SHIFT)
+#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_RANGE                  18:18
+#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_MSB                    MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_LSB                    MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_WOFFSET                        0x0
+#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_ErrorForced_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTSR_0_Frozen_SHIFT                       MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT2_WDTSR_0_Frozen_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTSR_0_Frozen_SHIFT)
+#define TKE_TOP_WDT2_WDTSR_0_Frozen_RANGE                       19:19
+#define TKE_TOP_WDT2_WDTSR_0_Frozen_MSB                 MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT2_WDTSR_0_Frozen_LSB                 MK_SHIFT_CONST(19)
+#define TKE_TOP_WDT2_WDTSR_0_Frozen_WOFFSET                     0x0
+#define TKE_TOP_WDT2_WDTSR_0_Frozen_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_Frozen_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTSR_0_Frozen_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_Frozen_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_Frozen_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSR_0_Frozen_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_WDT2_WDTCMDR_0
+#define TKE_TOP_WDT2_WDTCMDR_0                  MK_ADDR_CONST(0x130008)
+#define TKE_TOP_WDT2_WDTCMDR_0_SECURE                   0x0
+#define TKE_TOP_WDT2_WDTCMDR_0_DUAL                     0x0
+#define TKE_TOP_WDT2_WDTCMDR_0_SCR                      WDTSCR2_0
+#define TKE_TOP_WDT2_WDTCMDR_0_SCRREG                   TKE_TOP_SCR_WDTSCR2_0
+#define TKE_TOP_WDT2_WDTCMDR_0_WORD_COUNT                       0x1
+#define TKE_TOP_WDT2_WDTCMDR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCMDR_0_RESET_MASK                       MK_MASK_CONST(0xf)
+#define TKE_TOP_WDT2_WDTCMDR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCMDR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCMDR_0_READ_MASK                        MK_MASK_CONST(0xf)
+#define TKE_TOP_WDT2_WDTCMDR_0_WRITE_MASK                       MK_MASK_CONST(0xf)
+#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_FIELD                       MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCMDR_0_StartCounter_SHIFT)
+#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_RANGE                       0:0
+#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_MSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_WOFFSET                     0x0
+#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_DISABLE                     MK_ENUM_CONST(0)
+#define TKE_TOP_WDT2_WDTCMDR_0_StartCounter_ENABLE                      MK_ENUM_CONST(1)
+
+#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_SHIFT                     MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_FIELD                     MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_SHIFT)
+#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_RANGE                     1:1
+#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_MSB                       MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_LSB                       MK_SHIFT_CONST(1)
+#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_WOFFSET                   0x0
+#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_PARITY_PROTECTION                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_DISABLE                   MK_ENUM_CONST(0)
+#define TKE_TOP_WDT2_WDTCMDR_0_DisableCounter_ENABLE                    MK_ENUM_CONST(1)
+
+#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_SHIFT                        MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_FIELD                        MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCMDR_0_StickyStart_SHIFT)
+#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_RANGE                        2:2
+#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_MSB                  MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_LSB                  MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_WOFFSET                      0x0
+#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCMDR_0_StickyStart_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_SHIFT                 MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_FIELD                 MK_FIELD_CONST(0x1, TKE_TOP_WDT2_WDTCMDR_0_ForceError_SHIFT)
+#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_RANGE                 3:3
+#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_MSB                   MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_LSB                   MK_SHIFT_CONST(3)
+#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_WOFFSET                       0x0
+#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTCMDR_0_ForceError_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_WDT2_WDTUR_0
+#define TKE_TOP_WDT2_WDTUR_0                    MK_ADDR_CONST(0x13000c)
+#define TKE_TOP_WDT2_WDTUR_0_SECURE                     0x0
+#define TKE_TOP_WDT2_WDTUR_0_DUAL                       0x0
+#define TKE_TOP_WDT2_WDTUR_0_SCR                        WDTSCR2_0
+#define TKE_TOP_WDT2_WDTUR_0_SCRREG                     TKE_TOP_SCR_WDTSCR2_0
+#define TKE_TOP_WDT2_WDTUR_0_WORD_COUNT                         0x1
+#define TKE_TOP_WDT2_WDTUR_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTUR_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_WDT2_WDTUR_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTUR_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTUR_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_WDT2_WDTUR_0_WRITE_MASK                         MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_SHIFT                        MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_FIELD                        MK_FIELD_CONST(0xffffffff, TKE_TOP_WDT2_WDTUR_0_UnlockPattern_SHIFT)
+#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_RANGE                        31:0
+#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_MSB                  MK_SHIFT_CONST(31)
+#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_LSB                  MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_WOFFSET                      0x0
+#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_DEFAULT                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_PARITY_PROTECTION                    MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTUR_0_UnlockPattern_UNLOCK                       MK_ENUM_CONST(50266)
+
+
+// Register TKE_TOP_WDT2_WDTSCR_0
+#define TKE_TOP_WDT2_WDTSCR_0                   MK_ADDR_CONST(0x130010)
+#define TKE_TOP_WDT2_WDTSCR_0_SECURE                    0x0
+#define TKE_TOP_WDT2_WDTSCR_0_DUAL                      0x0
+#define TKE_TOP_WDT2_WDTSCR_0_SCR                       WDTSCR2_0
+#define TKE_TOP_WDT2_WDTSCR_0_SCRREG                    TKE_TOP_SCR_WDTSCR2_0
+#define TKE_TOP_WDT2_WDTSCR_0_WORD_COUNT                        0x1
+#define TKE_TOP_WDT2_WDTSCR_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSCR_0_RESET_MASK                        MK_MASK_CONST(0x7777)
+#define TKE_TOP_WDT2_WDTSCR_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSCR_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSCR_0_READ_MASK                         MK_MASK_CONST(0x7777)
+#define TKE_TOP_WDT2_WDTSCR_0_WRITE_MASK                        MK_MASK_CONST(0x7777)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip0_SHIFT                       MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip0_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT2_WDTSCR_0_Skip0_SHIFT)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip0_RANGE                       2:0
+#define TKE_TOP_WDT2_WDTSCR_0_Skip0_MSB                 MK_SHIFT_CONST(2)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip0_LSB                 MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip0_WOFFSET                     0x0
+#define TKE_TOP_WDT2_WDTSCR_0_Skip0_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip0_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip0_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip0_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip0_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTSCR_0_Skip1_SHIFT                       MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip1_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT2_WDTSCR_0_Skip1_SHIFT)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip1_RANGE                       6:4
+#define TKE_TOP_WDT2_WDTSCR_0_Skip1_MSB                 MK_SHIFT_CONST(6)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip1_LSB                 MK_SHIFT_CONST(4)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip1_WOFFSET                     0x0
+#define TKE_TOP_WDT2_WDTSCR_0_Skip1_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip1_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip1_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip1_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip1_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTSCR_0_Skip2_SHIFT                       MK_SHIFT_CONST(8)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip2_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT2_WDTSCR_0_Skip2_SHIFT)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip2_RANGE                       10:8
+#define TKE_TOP_WDT2_WDTSCR_0_Skip2_MSB                 MK_SHIFT_CONST(10)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip2_LSB                 MK_SHIFT_CONST(8)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip2_WOFFSET                     0x0
+#define TKE_TOP_WDT2_WDTSCR_0_Skip2_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip2_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip2_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip2_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip2_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTSCR_0_Skip3_SHIFT                       MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip3_FIELD                       MK_FIELD_CONST(0x7, TKE_TOP_WDT2_WDTSCR_0_Skip3_SHIFT)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip3_RANGE                       14:12
+#define TKE_TOP_WDT2_WDTSCR_0_Skip3_MSB                 MK_SHIFT_CONST(14)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip3_LSB                 MK_SHIFT_CONST(12)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip3_WOFFSET                     0x0
+#define TKE_TOP_WDT2_WDTSCR_0_Skip3_DEFAULT                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip3_DEFAULT_MASK                        MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip3_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip3_PARITY_PROTECTION                   MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTSCR_0_Skip3_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register TKE_TOP_WDT2_WDTFWCR_0
+#define TKE_TOP_WDT2_WDTFWCR_0                  MK_ADDR_CONST(0x130014)
+#define TKE_TOP_WDT2_WDTFWCR_0_SECURE                   0x0
+#define TKE_TOP_WDT2_WDTFWCR_0_DUAL                     0x0
+#define TKE_TOP_WDT2_WDTFWCR_0_SCR                      WDTSCR2_0
+#define TKE_TOP_WDT2_WDTFWCR_0_SCRREG                   TKE_TOP_SCR_WDTSCR2_0
+#define TKE_TOP_WDT2_WDTFWCR_0_WORD_COUNT                       0x1
+#define TKE_TOP_WDT2_WDTFWCR_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTFWCR_0_RESET_MASK                       MK_MASK_CONST(0x700ff)
+#define TKE_TOP_WDT2_WDTFWCR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTFWCR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTFWCR_0_READ_MASK                        MK_MASK_CONST(0x700ff)
+#define TKE_TOP_WDT2_WDTFWCR_0_WRITE_MASK                       MK_MASK_CONST(0x700ff)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_SHIFT                 MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_FIELD                 MK_FIELD_CONST(0xff, TKE_TOP_WDT2_WDTFWCR_0_StartCount_SHIFT)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_RANGE                 7:0
+#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_MSB                   MK_SHIFT_CONST(7)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_LSB                   MK_SHIFT_CONST(0)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_WOFFSET                       0x0
+#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartCount_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_SHIFT                 MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_FIELD                 MK_FIELD_CONST(0x7, TKE_TOP_WDT2_WDTFWCR_0_StartLevel_SHIFT)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_RANGE                 18:16
+#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_MSB                   MK_SHIFT_CONST(18)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_LSB                   MK_SHIFT_CONST(16)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_WOFFSET                       0x0
+#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_DEFAULT                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_DEFAULT_MASK                  MK_MASK_CONST(0x7)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_PARITY_PROTECTION                     MK_MASK_CONST(0x1)
+#define TKE_TOP_WDT2_WDTFWCR_0_StartLevel_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARTKE_TOP_REGS(_op_) \
+_op_(TKE_TOP_SHARED_TKETSC0_0) \
+_op_(TKE_TOP_SHARED_TKETSC1_0) \
+_op_(TKE_TOP_SHARED_TKEUSEC_0) \
+_op_(TKE_TOP_SHARED_TKEOSC_0) \
+_op_(TKE_TOP_SHARED_TKECR_0) \
+_op_(TKE_TOP_SHARED_CLK_OVR_ON_0) \
+_op_(TKE_TOP_SHARED_TKEIE0_0) \
+_op_(TKE_TOP_SHARED_TKEIE1_0) \
+_op_(TKE_TOP_SHARED_TKEIE2_0) \
+_op_(TKE_TOP_SHARED_TKEIE3_0) \
+_op_(TKE_TOP_SHARED_TKEIE4_0) \
+_op_(TKE_TOP_SHARED_TKEIE5_0) \
+_op_(TKE_TOP_SHARED_TKEIE6_0) \
+_op_(TKE_TOP_SHARED_TKEIE7_0) \
+_op_(TKE_TOP_SHARED_TKEIE8_0) \
+_op_(TKE_TOP_SHARED_TKEIE9_0) \
+_op_(TKE_TOP_SHARED_TKEIE10_0) \
+_op_(TKE_TOP_SHARED_TKEIE11_0) \
+_op_(TKE_TOP_SHARED_TKEIE12_0) \
+_op_(TKE_TOP_SHARED_TKEIE13_0) \
+_op_(TKE_TOP_SHARED_TKEIE14_0) \
+_op_(TKE_TOP_SHARED_TKEIE15_0) \
+_op_(TKE_TOP_SHARED_TKEIV_0) \
+_op_(TKE_TOP_SHARED_TKEIR_0) \
+_op_(TKE_TOP_TIMER_TMR0_TMRCR_0) \
+_op_(TKE_TOP_TIMER_TMR0_TMRSR_0) \
+_op_(TKE_TOP_TIMER_TMR0_TMRCSSR_0) \
+_op_(TKE_TOP_TIMER_TMR0_TMRATR_0) \
+_op_(TKE_TOP_TIMER_TMR1_TMRCR_0) \
+_op_(TKE_TOP_TIMER_TMR1_TMRSR_0) \
+_op_(TKE_TOP_TIMER_TMR1_TMRCSSR_0) \
+_op_(TKE_TOP_TIMER_TMR1_TMRATR_0) \
+_op_(TKE_TOP_TIMER_TMR2_TMRCR_0) \
+_op_(TKE_TOP_TIMER_TMR2_TMRSR_0) \
+_op_(TKE_TOP_TIMER_TMR2_TMRCSSR_0) \
+_op_(TKE_TOP_TIMER_TMR2_TMRATR_0) \
+_op_(TKE_TOP_TIMER_TMR3_TMRCR_0) \
+_op_(TKE_TOP_TIMER_TMR3_TMRSR_0) \
+_op_(TKE_TOP_TIMER_TMR3_TMRCSSR_0) \
+_op_(TKE_TOP_TIMER_TMR3_TMRATR_0) \
+_op_(TKE_TOP_TIMER_TMR4_TMRCR_0) \
+_op_(TKE_TOP_TIMER_TMR4_TMRSR_0) \
+_op_(TKE_TOP_TIMER_TMR4_TMRCSSR_0) \
+_op_(TKE_TOP_TIMER_TMR4_TMRATR_0) \
+_op_(TKE_TOP_TIMER_TMR5_TMRCR_0) \
+_op_(TKE_TOP_TIMER_TMR5_TMRSR_0) \
+_op_(TKE_TOP_TIMER_TMR5_TMRCSSR_0) \
+_op_(TKE_TOP_TIMER_TMR5_TMRATR_0) \
+_op_(TKE_TOP_TIMER_TMR6_TMRCR_0) \
+_op_(TKE_TOP_TIMER_TMR6_TMRSR_0) \
+_op_(TKE_TOP_TIMER_TMR6_TMRCSSR_0) \
+_op_(TKE_TOP_TIMER_TMR6_TMRATR_0) \
+_op_(TKE_TOP_TIMER_TMR7_TMRCR_0) \
+_op_(TKE_TOP_TIMER_TMR7_TMRSR_0) \
+_op_(TKE_TOP_TIMER_TMR7_TMRCSSR_0) \
+_op_(TKE_TOP_TIMER_TMR7_TMRATR_0) \
+_op_(TKE_TOP_TIMER_TMR8_TMRCR_0) \
+_op_(TKE_TOP_TIMER_TMR8_TMRSR_0) \
+_op_(TKE_TOP_TIMER_TMR8_TMRCSSR_0) \
+_op_(TKE_TOP_TIMER_TMR8_TMRATR_0) \
+_op_(TKE_TOP_TIMER_TMR9_TMRCR_0) \
+_op_(TKE_TOP_TIMER_TMR9_TMRSR_0) \
+_op_(TKE_TOP_TIMER_TMR9_TMRCSSR_0) \
+_op_(TKE_TOP_TIMER_TMR9_TMRATR_0) \
+_op_(TKE_TOP_TIMER_TMR10_TMRCR_0) \
+_op_(TKE_TOP_TIMER_TMR10_TMRSR_0) \
+_op_(TKE_TOP_TIMER_TMR10_TMRCSSR_0) \
+_op_(TKE_TOP_TIMER_TMR10_TMRATR_0) \
+_op_(TKE_TOP_TIMER_TMR11_TMRCR_0) \
+_op_(TKE_TOP_TIMER_TMR11_TMRSR_0) \
+_op_(TKE_TOP_TIMER_TMR11_TMRCSSR_0) \
+_op_(TKE_TOP_TIMER_TMR11_TMRATR_0) \
+_op_(TKE_TOP_TIMER_TMR12_TMRCR_0) \
+_op_(TKE_TOP_TIMER_TMR12_TMRSR_0) \
+_op_(TKE_TOP_TIMER_TMR12_TMRCSSR_0) \
+_op_(TKE_TOP_TIMER_TMR12_TMRATR_0) \
+_op_(TKE_TOP_TIMER_TMR13_TMRCR_0) \
+_op_(TKE_TOP_TIMER_TMR13_TMRSR_0) \
+_op_(TKE_TOP_TIMER_TMR13_TMRCSSR_0) \
+_op_(TKE_TOP_TIMER_TMR13_TMRATR_0) \
+_op_(TKE_TOP_TIMER_TMR14_TMRCR_0) \
+_op_(TKE_TOP_TIMER_TMR14_TMRSR_0) \
+_op_(TKE_TOP_TIMER_TMR14_TMRCSSR_0) \
+_op_(TKE_TOP_TIMER_TMR14_TMRATR_0) \
+_op_(TKE_TOP_TIMER_TMR15_TMRCR_0) \
+_op_(TKE_TOP_TIMER_TMR15_TMRSR_0) \
+_op_(TKE_TOP_TIMER_TMR15_TMRCSSR_0) \
+_op_(TKE_TOP_TIMER_TMR15_TMRATR_0) \
+_op_(TKE_TOP_WDT0_WDTCR_0) \
+_op_(TKE_TOP_WDT0_WDTSR_0) \
+_op_(TKE_TOP_WDT0_WDTCMDR_0) \
+_op_(TKE_TOP_WDT0_WDTUR_0) \
+_op_(TKE_TOP_WDT0_WDTSCR_0) \
+_op_(TKE_TOP_WDT0_WDTFWCR_0) \
+_op_(TKE_TOP_WDT1_WDTCR_0) \
+_op_(TKE_TOP_WDT1_WDTSR_0) \
+_op_(TKE_TOP_WDT1_WDTCMDR_0) \
+_op_(TKE_TOP_WDT1_WDTUR_0) \
+_op_(TKE_TOP_WDT1_WDTSCR_0) \
+_op_(TKE_TOP_WDT1_WDTFWCR_0) \
+_op_(TKE_TOP_WDT2_WDTCR_0) \
+_op_(TKE_TOP_WDT2_WDTSR_0) \
+_op_(TKE_TOP_WDT2_WDTCMDR_0) \
+_op_(TKE_TOP_WDT2_WDTUR_0) \
+_op_(TKE_TOP_WDT2_WDTSCR_0) \
+_op_(TKE_TOP_WDT2_WDTFWCR_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_TKE_TOP_SHARED     0x00000000
+#define BASE_ADDRESS_TKE_TOP_TIMER_TMR0 0x00010000
+#define BASE_ADDRESS_TKE_TOP_TIMER_TMR1 0x00020000
+#define BASE_ADDRESS_TKE_TOP_TIMER_TMR2 0x00030000
+#define BASE_ADDRESS_TKE_TOP_TIMER_TMR3 0x00040000
+#define BASE_ADDRESS_TKE_TOP_TIMER_TMR4 0x00050000
+#define BASE_ADDRESS_TKE_TOP_TIMER_TMR5 0x00060000
+#define BASE_ADDRESS_TKE_TOP_TIMER_TMR6 0x00070000
+#define BASE_ADDRESS_TKE_TOP_TIMER_TMR7 0x00080000
+#define BASE_ADDRESS_TKE_TOP_TIMER_TMR8 0x00090000
+#define BASE_ADDRESS_TKE_TOP_TIMER_TMR9 0x000a0000
+#define BASE_ADDRESS_TKE_TOP_TIMER_TMR10        0x000b0000
+#define BASE_ADDRESS_TKE_TOP_TIMER_TMR11        0x000c0000
+#define BASE_ADDRESS_TKE_TOP_TIMER_TMR12        0x000d0000
+#define BASE_ADDRESS_TKE_TOP_TIMER_TMR13        0x000e0000
+#define BASE_ADDRESS_TKE_TOP_TIMER_TMR14        0x000f0000
+#define BASE_ADDRESS_TKE_TOP_TIMER_TMR15        0x00100000
+#define BASE_ADDRESS_TKE_TOP_WDT0       0x00110000
+#define BASE_ADDRESS_TKE_TOP_WDT1       0x00120000
+#define BASE_ADDRESS_TKE_TOP_WDT2       0x00130000
+
+//
+// ARTKE_TOP REGISTER BANKS
+//
+
+#define TKE_TOP_SHARED0_FIRST_REG 0x0000 // TKE_TOP_SHARED_TKETSC0_0
+#define TKE_TOP_SHARED0_LAST_REG 0x0014 // TKE_TOP_SHARED_CLK_OVR_ON_0
+#define TKE_TOP_SHARED1_FIRST_REG 0x0100 // TKE_TOP_SHARED_TKEIE0_0
+#define TKE_TOP_SHARED1_LAST_REG 0x013c // TKE_TOP_SHARED_TKEIE15_0
+#define TKE_TOP_SHARED2_FIRST_REG 0x0200 // TKE_TOP_SHARED_TKEIV_0
+#define TKE_TOP_SHARED2_LAST_REG 0x0204 // TKE_TOP_SHARED_TKEIR_0
+#define TKE_TOP_TIMER_TMR00_FIRST_REG 0x10000 // TKE_TOP_TIMER_TMR0_TMRCR_0
+#define TKE_TOP_TIMER_TMR00_LAST_REG 0x1000c // TKE_TOP_TIMER_TMR0_TMRATR_0
+#define TKE_TOP_TIMER_TMR10_FIRST_REG 0x20000 // TKE_TOP_TIMER_TMR1_TMRCR_0
+#define TKE_TOP_TIMER_TMR10_LAST_REG 0x2000c // TKE_TOP_TIMER_TMR1_TMRATR_0
+#define TKE_TOP_TIMER_TMR20_FIRST_REG 0x30000 // TKE_TOP_TIMER_TMR2_TMRCR_0
+#define TKE_TOP_TIMER_TMR20_LAST_REG 0x3000c // TKE_TOP_TIMER_TMR2_TMRATR_0
+#define TKE_TOP_TIMER_TMR30_FIRST_REG 0x40000 // TKE_TOP_TIMER_TMR3_TMRCR_0
+#define TKE_TOP_TIMER_TMR30_LAST_REG 0x4000c // TKE_TOP_TIMER_TMR3_TMRATR_0
+#define TKE_TOP_TIMER_TMR40_FIRST_REG 0x50000 // TKE_TOP_TIMER_TMR4_TMRCR_0
+#define TKE_TOP_TIMER_TMR40_LAST_REG 0x5000c // TKE_TOP_TIMER_TMR4_TMRATR_0
+#define TKE_TOP_TIMER_TMR50_FIRST_REG 0x60000 // TKE_TOP_TIMER_TMR5_TMRCR_0
+#define TKE_TOP_TIMER_TMR50_LAST_REG 0x6000c // TKE_TOP_TIMER_TMR5_TMRATR_0
+#define TKE_TOP_TIMER_TMR60_FIRST_REG 0x70000 // TKE_TOP_TIMER_TMR6_TMRCR_0
+#define TKE_TOP_TIMER_TMR60_LAST_REG 0x7000c // TKE_TOP_TIMER_TMR6_TMRATR_0
+#define TKE_TOP_TIMER_TMR70_FIRST_REG 0x80000 // TKE_TOP_TIMER_TMR7_TMRCR_0
+#define TKE_TOP_TIMER_TMR70_LAST_REG 0x8000c // TKE_TOP_TIMER_TMR7_TMRATR_0
+#define TKE_TOP_TIMER_TMR80_FIRST_REG 0x90000 // TKE_TOP_TIMER_TMR8_TMRCR_0
+#define TKE_TOP_TIMER_TMR80_LAST_REG 0x9000c // TKE_TOP_TIMER_TMR8_TMRATR_0
+#define TKE_TOP_TIMER_TMR90_FIRST_REG 0xa0000 // TKE_TOP_TIMER_TMR9_TMRCR_0
+#define TKE_TOP_TIMER_TMR90_LAST_REG 0xa000c // TKE_TOP_TIMER_TMR9_TMRATR_0
+#define TKE_TOP_TIMER_TMR100_FIRST_REG 0xb0000 // TKE_TOP_TIMER_TMR10_TMRCR_0
+#define TKE_TOP_TIMER_TMR100_LAST_REG 0xb000c // TKE_TOP_TIMER_TMR10_TMRATR_0
+#define TKE_TOP_TIMER_TMR110_FIRST_REG 0xc0000 // TKE_TOP_TIMER_TMR11_TMRCR_0
+#define TKE_TOP_TIMER_TMR110_LAST_REG 0xc000c // TKE_TOP_TIMER_TMR11_TMRATR_0
+#define TKE_TOP_TIMER_TMR120_FIRST_REG 0xd0000 // TKE_TOP_TIMER_TMR12_TMRCR_0
+#define TKE_TOP_TIMER_TMR120_LAST_REG 0xd000c // TKE_TOP_TIMER_TMR12_TMRATR_0
+#define TKE_TOP_TIMER_TMR130_FIRST_REG 0xe0000 // TKE_TOP_TIMER_TMR13_TMRCR_0
+#define TKE_TOP_TIMER_TMR130_LAST_REG 0xe000c // TKE_TOP_TIMER_TMR13_TMRATR_0
+#define TKE_TOP_TIMER_TMR140_FIRST_REG 0xf0000 // TKE_TOP_TIMER_TMR14_TMRCR_0
+#define TKE_TOP_TIMER_TMR140_LAST_REG 0xf000c // TKE_TOP_TIMER_TMR14_TMRATR_0
+#define TKE_TOP_TIMER_TMR150_FIRST_REG 0x100000 // TKE_TOP_TIMER_TMR15_TMRCR_0
+#define TKE_TOP_TIMER_TMR150_LAST_REG 0x10000c // TKE_TOP_TIMER_TMR15_TMRATR_0
+#define TKE_TOP_WDT00_FIRST_REG 0x110000 // TKE_TOP_WDT0_WDTCR_0
+#define TKE_TOP_WDT00_LAST_REG 0x110014 // TKE_TOP_WDT0_WDTFWCR_0
+#define TKE_TOP_WDT10_FIRST_REG 0x120000 // TKE_TOP_WDT1_WDTCR_0
+#define TKE_TOP_WDT10_LAST_REG 0x120014 // TKE_TOP_WDT1_WDTFWCR_0
+#define TKE_TOP_WDT20_FIRST_REG 0x130000 // TKE_TOP_WDT2_WDTCR_0
+#define TKE_TOP_WDT20_LAST_REG 0x130014 // TKE_TOP_WDT2_WDTFWCR_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARTKE_TOP_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/aruart.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/aruart.h
new file mode 100644
index 0000000..10607f6
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/aruart.h
@@ -0,0 +1,1458 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARUART_H_INC
+#define ARUART_H_INC
+#define NV_MOBILE_ARUART_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARUART_H_SCRREG_NOMENCLATURE INFERRED
+
+
+// Register UART_THR_DLAB_0_0
+#define UART_THR_DLAB_0_0                       MK_ADDR_CONST(0x0)
+#define UART_THR_DLAB_0_0_SECURE                        0x0
+#define UART_THR_DLAB_0_0_DUAL                  0x0
+#define UART_THR_DLAB_0_0_SCR                   0
+#define UART_THR_DLAB_0_0_SCRREG                        0
+#define UART_THR_DLAB_0_0_WORD_COUNT                    0x1
+#define UART_THR_DLAB_0_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_RESET_MASK                    MK_MASK_CONST(0xff)
+#define UART_THR_DLAB_0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_READ_MASK                     MK_MASK_CONST(0xff)
+#define UART_THR_DLAB_0_0_WRITE_MASK                    MK_MASK_CONST(0xff)
+#define UART_THR_DLAB_0_0_THR_A_SHIFT                   MK_SHIFT_CONST(0)
+#define UART_THR_DLAB_0_0_THR_A_FIELD                   MK_FIELD_CONST(0xff, UART_THR_DLAB_0_0_THR_A_SHIFT)
+#define UART_THR_DLAB_0_0_THR_A_RANGE                   7:0
+#define UART_THR_DLAB_0_0_THR_A_MSB                     MK_SHIFT_CONST(7)
+#define UART_THR_DLAB_0_0_THR_A_LSB                     MK_SHIFT_CONST(0)
+#define UART_THR_DLAB_0_0_THR_A_WOFFSET                 0x0
+#define UART_THR_DLAB_0_0_THR_A_DEFAULT                 MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_THR_A_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define UART_THR_DLAB_0_0_THR_A_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_THR_A_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_THR_A_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_THR_A_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define UART_THR_DLAB_0_0_RBR_A_SHIFT                   MK_SHIFT_CONST(0)
+#define UART_THR_DLAB_0_0_RBR_A_FIELD                   MK_FIELD_CONST(0xff, UART_THR_DLAB_0_0_RBR_A_SHIFT)
+#define UART_THR_DLAB_0_0_RBR_A_RANGE                   7:0
+#define UART_THR_DLAB_0_0_RBR_A_MSB                     MK_SHIFT_CONST(7)
+#define UART_THR_DLAB_0_0_RBR_A_LSB                     MK_SHIFT_CONST(0)
+#define UART_THR_DLAB_0_0_RBR_A_WOFFSET                 0x0
+#define UART_THR_DLAB_0_0_RBR_A_DEFAULT                 MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_RBR_A_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define UART_THR_DLAB_0_0_RBR_A_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_RBR_A_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_RBR_A_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_RBR_A_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+#define UART_THR_DLAB_0_0_DLL_A_SHIFT                   MK_SHIFT_CONST(0)
+#define UART_THR_DLAB_0_0_DLL_A_FIELD                   MK_FIELD_CONST(0xff, UART_THR_DLAB_0_0_DLL_A_SHIFT)
+#define UART_THR_DLAB_0_0_DLL_A_RANGE                   7:0
+#define UART_THR_DLAB_0_0_DLL_A_MSB                     MK_SHIFT_CONST(7)
+#define UART_THR_DLAB_0_0_DLL_A_LSB                     MK_SHIFT_CONST(0)
+#define UART_THR_DLAB_0_0_DLL_A_WOFFSET                 0x0
+#define UART_THR_DLAB_0_0_DLL_A_DEFAULT                 MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_DLL_A_DEFAULT_MASK                    MK_MASK_CONST(0xff)
+#define UART_THR_DLAB_0_0_DLL_A_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_DLL_A_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_DLL_A_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_THR_DLAB_0_0_DLL_A_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register UART_IER_DLAB_0_0
+#define UART_IER_DLAB_0_0                       MK_ADDR_CONST(0x4)
+#define UART_IER_DLAB_0_0_SECURE                        0x0
+#define UART_IER_DLAB_0_0_DUAL                  0x0
+#define UART_IER_DLAB_0_0_SCR                   0
+#define UART_IER_DLAB_0_0_SCRREG                        0
+#define UART_IER_DLAB_0_0_WORD_COUNT                    0x1
+#define UART_IER_DLAB_0_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_RESET_MASK                    MK_MASK_CONST(0x3f)
+#define UART_IER_DLAB_0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_READ_MASK                     MK_MASK_CONST(0x3f)
+#define UART_IER_DLAB_0_0_WRITE_MASK                    MK_MASK_CONST(0x3f)
+#define UART_IER_DLAB_0_0_IE_EORD_SHIFT                 MK_SHIFT_CONST(5)
+#define UART_IER_DLAB_0_0_IE_EORD_FIELD                 MK_FIELD_CONST(0x1, UART_IER_DLAB_0_0_IE_EORD_SHIFT)
+#define UART_IER_DLAB_0_0_IE_EORD_RANGE                 5:5
+#define UART_IER_DLAB_0_0_IE_EORD_MSB                   MK_SHIFT_CONST(5)
+#define UART_IER_DLAB_0_0_IE_EORD_LSB                   MK_SHIFT_CONST(5)
+#define UART_IER_DLAB_0_0_IE_EORD_WOFFSET                       0x0
+#define UART_IER_DLAB_0_0_IE_EORD_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_EORD_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_EORD_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_EORD_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_EORD_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_EORD_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_EORD_DISABLE                       MK_ENUM_CONST(0)
+#define UART_IER_DLAB_0_0_IE_EORD_ENABLE                        MK_ENUM_CONST(1)
+
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_SHIFT                   MK_SHIFT_CONST(4)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_FIELD                   MK_FIELD_CONST(0x1, UART_IER_DLAB_0_0_IE_RX_TIMEOUT_SHIFT)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_RANGE                   4:4
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_MSB                     MK_SHIFT_CONST(4)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_LSB                     MK_SHIFT_CONST(4)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_WOFFSET                 0x0
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_DEFAULT                 MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_DISABLE                 MK_ENUM_CONST(0)
+#define UART_IER_DLAB_0_0_IE_RX_TIMEOUT_ENABLE                  MK_ENUM_CONST(1)
+
+#define UART_IER_DLAB_0_0_IE_MSI_SHIFT                  MK_SHIFT_CONST(3)
+#define UART_IER_DLAB_0_0_IE_MSI_FIELD                  MK_FIELD_CONST(0x1, UART_IER_DLAB_0_0_IE_MSI_SHIFT)
+#define UART_IER_DLAB_0_0_IE_MSI_RANGE                  3:3
+#define UART_IER_DLAB_0_0_IE_MSI_MSB                    MK_SHIFT_CONST(3)
+#define UART_IER_DLAB_0_0_IE_MSI_LSB                    MK_SHIFT_CONST(3)
+#define UART_IER_DLAB_0_0_IE_MSI_WOFFSET                        0x0
+#define UART_IER_DLAB_0_0_IE_MSI_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_MSI_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_MSI_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_MSI_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_MSI_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_MSI_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_MSI_DISABLE                        MK_ENUM_CONST(0)
+#define UART_IER_DLAB_0_0_IE_MSI_ENABLE                 MK_ENUM_CONST(1)
+
+#define UART_IER_DLAB_0_0_IE_RXS_SHIFT                  MK_SHIFT_CONST(2)
+#define UART_IER_DLAB_0_0_IE_RXS_FIELD                  MK_FIELD_CONST(0x1, UART_IER_DLAB_0_0_IE_RXS_SHIFT)
+#define UART_IER_DLAB_0_0_IE_RXS_RANGE                  2:2
+#define UART_IER_DLAB_0_0_IE_RXS_MSB                    MK_SHIFT_CONST(2)
+#define UART_IER_DLAB_0_0_IE_RXS_LSB                    MK_SHIFT_CONST(2)
+#define UART_IER_DLAB_0_0_IE_RXS_WOFFSET                        0x0
+#define UART_IER_DLAB_0_0_IE_RXS_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RXS_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_RXS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RXS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RXS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RXS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_RXS_DISABLE                        MK_ENUM_CONST(0)
+#define UART_IER_DLAB_0_0_IE_RXS_ENABLE                 MK_ENUM_CONST(1)
+
+#define UART_IER_DLAB_0_0_IE_THR_SHIFT                  MK_SHIFT_CONST(1)
+#define UART_IER_DLAB_0_0_IE_THR_FIELD                  MK_FIELD_CONST(0x1, UART_IER_DLAB_0_0_IE_THR_SHIFT)
+#define UART_IER_DLAB_0_0_IE_THR_RANGE                  1:1
+#define UART_IER_DLAB_0_0_IE_THR_MSB                    MK_SHIFT_CONST(1)
+#define UART_IER_DLAB_0_0_IE_THR_LSB                    MK_SHIFT_CONST(1)
+#define UART_IER_DLAB_0_0_IE_THR_WOFFSET                        0x0
+#define UART_IER_DLAB_0_0_IE_THR_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_THR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_THR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_THR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_THR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_THR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_THR_DISABLE                        MK_ENUM_CONST(0)
+#define UART_IER_DLAB_0_0_IE_THR_ENABLE                 MK_ENUM_CONST(1)
+
+#define UART_IER_DLAB_0_0_IE_RHR_SHIFT                  MK_SHIFT_CONST(0)
+#define UART_IER_DLAB_0_0_IE_RHR_FIELD                  MK_FIELD_CONST(0x1, UART_IER_DLAB_0_0_IE_RHR_SHIFT)
+#define UART_IER_DLAB_0_0_IE_RHR_RANGE                  0:0
+#define UART_IER_DLAB_0_0_IE_RHR_MSB                    MK_SHIFT_CONST(0)
+#define UART_IER_DLAB_0_0_IE_RHR_LSB                    MK_SHIFT_CONST(0)
+#define UART_IER_DLAB_0_0_IE_RHR_WOFFSET                        0x0
+#define UART_IER_DLAB_0_0_IE_RHR_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RHR_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_RHR_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RHR_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RHR_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define UART_IER_DLAB_0_0_IE_RHR_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define UART_IER_DLAB_0_0_IE_RHR_DISABLE                        MK_ENUM_CONST(0)
+#define UART_IER_DLAB_0_0_IE_RHR_ENABLE                 MK_ENUM_CONST(1)
+
+
+// Register UART_IIR_FCR_0
+#define UART_IIR_FCR_0                  MK_ADDR_CONST(0x8)
+#define UART_IIR_FCR_0_SECURE                   0x0
+#define UART_IIR_FCR_0_DUAL                     0x0
+#define UART_IIR_FCR_0_SCR                      0
+#define UART_IIR_FCR_0_SCRREG                   0
+#define UART_IIR_FCR_0_WORD_COUNT                       0x1
+#define UART_IIR_FCR_0_RESET_VAL                        MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_RESET_MASK                       MK_MASK_CONST(0xff)
+#define UART_IIR_FCR_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_READ_MASK                        MK_MASK_CONST(0xcf)
+#define UART_IIR_FCR_0_WRITE_MASK                       MK_MASK_CONST(0xff)
+#define UART_IIR_FCR_0_EN_FIFO_SHIFT                    MK_SHIFT_CONST(6)
+#define UART_IIR_FCR_0_EN_FIFO_FIELD                    MK_FIELD_CONST(0x3, UART_IIR_FCR_0_EN_FIFO_SHIFT)
+#define UART_IIR_FCR_0_EN_FIFO_RANGE                    7:6
+#define UART_IIR_FCR_0_EN_FIFO_MSB                      MK_SHIFT_CONST(7)
+#define UART_IIR_FCR_0_EN_FIFO_LSB                      MK_SHIFT_CONST(6)
+#define UART_IIR_FCR_0_EN_FIFO_WOFFSET                  0x0
+#define UART_IIR_FCR_0_EN_FIFO_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_EN_FIFO_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define UART_IIR_FCR_0_EN_FIFO_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_EN_FIFO_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_EN_FIFO_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_EN_FIFO_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_EN_FIFO_MODE_16550                       MK_ENUM_CONST(1)
+#define UART_IIR_FCR_0_EN_FIFO_MODE_16450                       MK_ENUM_CONST(0)
+
+#define UART_IIR_FCR_0_IS_PRI2_SHIFT                    MK_SHIFT_CONST(3)
+#define UART_IIR_FCR_0_IS_PRI2_FIELD                    MK_FIELD_CONST(0x1, UART_IIR_FCR_0_IS_PRI2_SHIFT)
+#define UART_IIR_FCR_0_IS_PRI2_RANGE                    3:3
+#define UART_IIR_FCR_0_IS_PRI2_MSB                      MK_SHIFT_CONST(3)
+#define UART_IIR_FCR_0_IS_PRI2_LSB                      MK_SHIFT_CONST(3)
+#define UART_IIR_FCR_0_IS_PRI2_WOFFSET                  0x0
+#define UART_IIR_FCR_0_IS_PRI2_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI2_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_IS_PRI2_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI2_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI2_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_IS_PRI2_DISABLE                  MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_IS_PRI2_ENABLE                   MK_ENUM_CONST(1)
+
+#define UART_IIR_FCR_0_IS_PRI1_SHIFT                    MK_SHIFT_CONST(2)
+#define UART_IIR_FCR_0_IS_PRI1_FIELD                    MK_FIELD_CONST(0x1, UART_IIR_FCR_0_IS_PRI1_SHIFT)
+#define UART_IIR_FCR_0_IS_PRI1_RANGE                    2:2
+#define UART_IIR_FCR_0_IS_PRI1_MSB                      MK_SHIFT_CONST(2)
+#define UART_IIR_FCR_0_IS_PRI1_LSB                      MK_SHIFT_CONST(2)
+#define UART_IIR_FCR_0_IS_PRI1_WOFFSET                  0x0
+#define UART_IIR_FCR_0_IS_PRI1_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI1_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_IS_PRI1_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI1_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI1_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_IS_PRI1_DISABLE                  MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_IS_PRI1_ENABLE                   MK_ENUM_CONST(1)
+
+#define UART_IIR_FCR_0_IS_PRI0_SHIFT                    MK_SHIFT_CONST(1)
+#define UART_IIR_FCR_0_IS_PRI0_FIELD                    MK_FIELD_CONST(0x1, UART_IIR_FCR_0_IS_PRI0_SHIFT)
+#define UART_IIR_FCR_0_IS_PRI0_RANGE                    1:1
+#define UART_IIR_FCR_0_IS_PRI0_MSB                      MK_SHIFT_CONST(1)
+#define UART_IIR_FCR_0_IS_PRI0_LSB                      MK_SHIFT_CONST(1)
+#define UART_IIR_FCR_0_IS_PRI0_WOFFSET                  0x0
+#define UART_IIR_FCR_0_IS_PRI0_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI0_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_IS_PRI0_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI0_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_PRI0_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_IS_PRI0_DISABLE                  MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_IS_PRI0_ENABLE                   MK_ENUM_CONST(1)
+
+#define UART_IIR_FCR_0_IS_STA_SHIFT                     MK_SHIFT_CONST(0)
+#define UART_IIR_FCR_0_IS_STA_FIELD                     MK_FIELD_CONST(0x1, UART_IIR_FCR_0_IS_STA_SHIFT)
+#define UART_IIR_FCR_0_IS_STA_RANGE                     0:0
+#define UART_IIR_FCR_0_IS_STA_MSB                       MK_SHIFT_CONST(0)
+#define UART_IIR_FCR_0_IS_STA_LSB                       MK_SHIFT_CONST(0)
+#define UART_IIR_FCR_0_IS_STA_WOFFSET                   0x0
+#define UART_IIR_FCR_0_IS_STA_DEFAULT                   MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_IS_STA_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_IS_STA_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_STA_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_STA_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_IS_STA_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_IS_STA_INTR_PEND                 MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_IS_STA_NO_INTR_PEND                      MK_ENUM_CONST(1)
+
+#define UART_IIR_FCR_0_RX_TRIG_SHIFT                    MK_SHIFT_CONST(6)
+#define UART_IIR_FCR_0_RX_TRIG_FIELD                    MK_FIELD_CONST(0x3, UART_IIR_FCR_0_RX_TRIG_SHIFT)
+#define UART_IIR_FCR_0_RX_TRIG_RANGE                    7:6
+#define UART_IIR_FCR_0_RX_TRIG_MSB                      MK_SHIFT_CONST(7)
+#define UART_IIR_FCR_0_RX_TRIG_LSB                      MK_SHIFT_CONST(6)
+#define UART_IIR_FCR_0_RX_TRIG_WOFFSET                  0x0
+#define UART_IIR_FCR_0_RX_TRIG_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_RX_TRIG_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define UART_IIR_FCR_0_RX_TRIG_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_RX_TRIG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_RX_TRIG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_RX_TRIG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_RX_TRIG_FIFO_COUNT_GREATER_1                     MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_RX_TRIG_FIFO_COUNT_GREATER_4                     MK_ENUM_CONST(1)
+#define UART_IIR_FCR_0_RX_TRIG_FIFO_COUNT_GREATER_8                     MK_ENUM_CONST(2)
+#define UART_IIR_FCR_0_RX_TRIG_FIFO_COUNT_GREATER_16                    MK_ENUM_CONST(3)
+
+#define UART_IIR_FCR_0_TX_TRIG_SHIFT                    MK_SHIFT_CONST(4)
+#define UART_IIR_FCR_0_TX_TRIG_FIELD                    MK_FIELD_CONST(0x3, UART_IIR_FCR_0_TX_TRIG_SHIFT)
+#define UART_IIR_FCR_0_TX_TRIG_RANGE                    5:4
+#define UART_IIR_FCR_0_TX_TRIG_MSB                      MK_SHIFT_CONST(5)
+#define UART_IIR_FCR_0_TX_TRIG_LSB                      MK_SHIFT_CONST(4)
+#define UART_IIR_FCR_0_TX_TRIG_WOFFSET                  0x0
+#define UART_IIR_FCR_0_TX_TRIG_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_TX_TRIG_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define UART_IIR_FCR_0_TX_TRIG_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_TX_TRIG_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_TX_TRIG_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_TX_TRIG_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_TX_TRIG_FIFO_COUNT_GREATER_16                    MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_TX_TRIG_FIFO_COUNT_GREATER_8                     MK_ENUM_CONST(1)
+#define UART_IIR_FCR_0_TX_TRIG_FIFO_COUNT_GREATER_4                     MK_ENUM_CONST(2)
+#define UART_IIR_FCR_0_TX_TRIG_FIFO_COUNT_GREATER_1                     MK_ENUM_CONST(3)
+
+#define UART_IIR_FCR_0_DMA_SHIFT                        MK_SHIFT_CONST(3)
+#define UART_IIR_FCR_0_DMA_FIELD                        MK_FIELD_CONST(0x1, UART_IIR_FCR_0_DMA_SHIFT)
+#define UART_IIR_FCR_0_DMA_RANGE                        3:3
+#define UART_IIR_FCR_0_DMA_MSB                  MK_SHIFT_CONST(3)
+#define UART_IIR_FCR_0_DMA_LSB                  MK_SHIFT_CONST(3)
+#define UART_IIR_FCR_0_DMA_WOFFSET                      0x0
+#define UART_IIR_FCR_0_DMA_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_DMA_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_DMA_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_DMA_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_DMA_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_DMA_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_DMA_NO_CHANGE                    MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_DMA_CHANGE                       MK_ENUM_CONST(1)
+
+#define UART_IIR_FCR_0_TX_CLR_SHIFT                     MK_SHIFT_CONST(2)
+#define UART_IIR_FCR_0_TX_CLR_FIELD                     MK_FIELD_CONST(0x1, UART_IIR_FCR_0_TX_CLR_SHIFT)
+#define UART_IIR_FCR_0_TX_CLR_RANGE                     2:2
+#define UART_IIR_FCR_0_TX_CLR_MSB                       MK_SHIFT_CONST(2)
+#define UART_IIR_FCR_0_TX_CLR_LSB                       MK_SHIFT_CONST(2)
+#define UART_IIR_FCR_0_TX_CLR_WOFFSET                   0x0
+#define UART_IIR_FCR_0_TX_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_TX_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_TX_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_TX_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_TX_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_TX_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_TX_CLR_NO_CLEAR                  MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_TX_CLR_CLEAR                     MK_ENUM_CONST(1)
+
+#define UART_IIR_FCR_0_RX_CLR_SHIFT                     MK_SHIFT_CONST(1)
+#define UART_IIR_FCR_0_RX_CLR_FIELD                     MK_FIELD_CONST(0x1, UART_IIR_FCR_0_RX_CLR_SHIFT)
+#define UART_IIR_FCR_0_RX_CLR_RANGE                     1:1
+#define UART_IIR_FCR_0_RX_CLR_MSB                       MK_SHIFT_CONST(1)
+#define UART_IIR_FCR_0_RX_CLR_LSB                       MK_SHIFT_CONST(1)
+#define UART_IIR_FCR_0_RX_CLR_WOFFSET                   0x0
+#define UART_IIR_FCR_0_RX_CLR_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_RX_CLR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_RX_CLR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_RX_CLR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_RX_CLR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_RX_CLR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_RX_CLR_NO_CLEAR                  MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_RX_CLR_CLEAR                     MK_ENUM_CONST(1)
+
+#define UART_IIR_FCR_0_FCR_EN_FIFO_SHIFT                        MK_SHIFT_CONST(0)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_FIELD                        MK_FIELD_CONST(0x1, UART_IIR_FCR_0_FCR_EN_FIFO_SHIFT)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_RANGE                        0:0
+#define UART_IIR_FCR_0_FCR_EN_FIFO_MSB                  MK_SHIFT_CONST(0)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_LSB                  MK_SHIFT_CONST(0)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_WOFFSET                      0x0
+#define UART_IIR_FCR_0_FCR_EN_FIFO_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_DISABLE                      MK_ENUM_CONST(0)
+#define UART_IIR_FCR_0_FCR_EN_FIFO_ENABLE                       MK_ENUM_CONST(1)
+
+
+// Register UART_LCR_0
+#define UART_LCR_0                      MK_ADDR_CONST(0xc)
+#define UART_LCR_0_SECURE                       0x0
+#define UART_LCR_0_DUAL                         0x0
+#define UART_LCR_0_SCR                  0
+#define UART_LCR_0_SCRREG                       0
+#define UART_LCR_0_WORD_COUNT                   0x1
+#define UART_LCR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define UART_LCR_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define UART_LCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define UART_LCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_LCR_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define UART_LCR_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define UART_LCR_0_DLAB_SHIFT                   MK_SHIFT_CONST(7)
+#define UART_LCR_0_DLAB_FIELD                   MK_FIELD_CONST(0x1, UART_LCR_0_DLAB_SHIFT)
+#define UART_LCR_0_DLAB_RANGE                   7:7
+#define UART_LCR_0_DLAB_MSB                     MK_SHIFT_CONST(7)
+#define UART_LCR_0_DLAB_LSB                     MK_SHIFT_CONST(7)
+#define UART_LCR_0_DLAB_WOFFSET                 0x0
+#define UART_LCR_0_DLAB_DEFAULT                 MK_MASK_CONST(0x0)
+#define UART_LCR_0_DLAB_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define UART_LCR_0_DLAB_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_LCR_0_DLAB_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_LCR_0_DLAB_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_LCR_0_DLAB_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define UART_LCR_0_DLAB_DISABLE                 MK_ENUM_CONST(0)
+#define UART_LCR_0_DLAB_ENABLE                  MK_ENUM_CONST(1)
+
+#define UART_LCR_0_SET_B_SHIFT                  MK_SHIFT_CONST(6)
+#define UART_LCR_0_SET_B_FIELD                  MK_FIELD_CONST(0x1, UART_LCR_0_SET_B_SHIFT)
+#define UART_LCR_0_SET_B_RANGE                  6:6
+#define UART_LCR_0_SET_B_MSB                    MK_SHIFT_CONST(6)
+#define UART_LCR_0_SET_B_LSB                    MK_SHIFT_CONST(6)
+#define UART_LCR_0_SET_B_WOFFSET                        0x0
+#define UART_LCR_0_SET_B_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_LCR_0_SET_B_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define UART_LCR_0_SET_B_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define UART_LCR_0_SET_B_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define UART_LCR_0_SET_B_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define UART_LCR_0_SET_B_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define UART_LCR_0_SET_B_NO_BREAK                       MK_ENUM_CONST(0)
+#define UART_LCR_0_SET_B_BREAK                  MK_ENUM_CONST(1)
+
+#define UART_LCR_0_SET_P_SHIFT                  MK_SHIFT_CONST(5)
+#define UART_LCR_0_SET_P_FIELD                  MK_FIELD_CONST(0x1, UART_LCR_0_SET_P_SHIFT)
+#define UART_LCR_0_SET_P_RANGE                  5:5
+#define UART_LCR_0_SET_P_MSB                    MK_SHIFT_CONST(5)
+#define UART_LCR_0_SET_P_LSB                    MK_SHIFT_CONST(5)
+#define UART_LCR_0_SET_P_WOFFSET                        0x0
+#define UART_LCR_0_SET_P_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_LCR_0_SET_P_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define UART_LCR_0_SET_P_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define UART_LCR_0_SET_P_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define UART_LCR_0_SET_P_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define UART_LCR_0_SET_P_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define UART_LCR_0_SET_P_NO_PARITY                      MK_ENUM_CONST(0)
+#define UART_LCR_0_SET_P_PARITY                 MK_ENUM_CONST(1)
+
+#define UART_LCR_0_EVEN_SHIFT                   MK_SHIFT_CONST(4)
+#define UART_LCR_0_EVEN_FIELD                   MK_FIELD_CONST(0x1, UART_LCR_0_EVEN_SHIFT)
+#define UART_LCR_0_EVEN_RANGE                   4:4
+#define UART_LCR_0_EVEN_MSB                     MK_SHIFT_CONST(4)
+#define UART_LCR_0_EVEN_LSB                     MK_SHIFT_CONST(4)
+#define UART_LCR_0_EVEN_WOFFSET                 0x0
+#define UART_LCR_0_EVEN_DEFAULT                 MK_MASK_CONST(0x0)
+#define UART_LCR_0_EVEN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define UART_LCR_0_EVEN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_LCR_0_EVEN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_LCR_0_EVEN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_LCR_0_EVEN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define UART_LCR_0_EVEN_DISABLE                 MK_ENUM_CONST(0)
+#define UART_LCR_0_EVEN_ENABLE                  MK_ENUM_CONST(1)
+
+#define UART_LCR_0_PAR_SHIFT                    MK_SHIFT_CONST(3)
+#define UART_LCR_0_PAR_FIELD                    MK_FIELD_CONST(0x1, UART_LCR_0_PAR_SHIFT)
+#define UART_LCR_0_PAR_RANGE                    3:3
+#define UART_LCR_0_PAR_MSB                      MK_SHIFT_CONST(3)
+#define UART_LCR_0_PAR_LSB                      MK_SHIFT_CONST(3)
+#define UART_LCR_0_PAR_WOFFSET                  0x0
+#define UART_LCR_0_PAR_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_LCR_0_PAR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define UART_LCR_0_PAR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_LCR_0_PAR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_LCR_0_PAR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_LCR_0_PAR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_LCR_0_PAR_NO_PARITY                        MK_ENUM_CONST(0)
+#define UART_LCR_0_PAR_PARITY                   MK_ENUM_CONST(1)
+
+#define UART_LCR_0_STOP_SHIFT                   MK_SHIFT_CONST(2)
+#define UART_LCR_0_STOP_FIELD                   MK_FIELD_CONST(0x1, UART_LCR_0_STOP_SHIFT)
+#define UART_LCR_0_STOP_RANGE                   2:2
+#define UART_LCR_0_STOP_MSB                     MK_SHIFT_CONST(2)
+#define UART_LCR_0_STOP_LSB                     MK_SHIFT_CONST(2)
+#define UART_LCR_0_STOP_WOFFSET                 0x0
+#define UART_LCR_0_STOP_DEFAULT                 MK_MASK_CONST(0x0)
+#define UART_LCR_0_STOP_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define UART_LCR_0_STOP_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_LCR_0_STOP_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_LCR_0_STOP_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_LCR_0_STOP_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define UART_LCR_0_STOP_DISABLE                 MK_ENUM_CONST(0)
+#define UART_LCR_0_STOP_ENABLE                  MK_ENUM_CONST(1)
+
+#define UART_LCR_0_WD_SIZE_SHIFT                        MK_SHIFT_CONST(0)
+#define UART_LCR_0_WD_SIZE_FIELD                        MK_FIELD_CONST(0x3, UART_LCR_0_WD_SIZE_SHIFT)
+#define UART_LCR_0_WD_SIZE_RANGE                        1:0
+#define UART_LCR_0_WD_SIZE_MSB                  MK_SHIFT_CONST(1)
+#define UART_LCR_0_WD_SIZE_LSB                  MK_SHIFT_CONST(0)
+#define UART_LCR_0_WD_SIZE_WOFFSET                      0x0
+#define UART_LCR_0_WD_SIZE_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_LCR_0_WD_SIZE_DEFAULT_MASK                 MK_MASK_CONST(0x3)
+#define UART_LCR_0_WD_SIZE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_LCR_0_WD_SIZE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_LCR_0_WD_SIZE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define UART_LCR_0_WD_SIZE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define UART_LCR_0_WD_SIZE_WORD_LENGTH_5                        MK_ENUM_CONST(0)
+#define UART_LCR_0_WD_SIZE_WORD_LENGTH_6                        MK_ENUM_CONST(1)
+#define UART_LCR_0_WD_SIZE_WORD_LENGTH_7                        MK_ENUM_CONST(2)
+#define UART_LCR_0_WD_SIZE_WORD_LENGTH_8                        MK_ENUM_CONST(3)
+
+
+// Register UART_MCR_0
+#define UART_MCR_0                      MK_ADDR_CONST(0x10)
+#define UART_MCR_0_SECURE                       0x0
+#define UART_MCR_0_DUAL                         0x0
+#define UART_MCR_0_SCR                  0
+#define UART_MCR_0_SCRREG                       0
+#define UART_MCR_0_WORD_COUNT                   0x1
+#define UART_MCR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define UART_MCR_0_RESET_MASK                   MK_MASK_CONST(0x7ff)
+#define UART_MCR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define UART_MCR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_MCR_0_READ_MASK                    MK_MASK_CONST(0x7ff)
+#define UART_MCR_0_WRITE_MASK                   MK_MASK_CONST(0x7ff)
+#define UART_MCR_0_OLD_SIR_DECODE_SHIFT                 MK_SHIFT_CONST(10)
+#define UART_MCR_0_OLD_SIR_DECODE_FIELD                 MK_FIELD_CONST(0x1, UART_MCR_0_OLD_SIR_DECODE_SHIFT)
+#define UART_MCR_0_OLD_SIR_DECODE_RANGE                 10:10
+#define UART_MCR_0_OLD_SIR_DECODE_MSB                   MK_SHIFT_CONST(10)
+#define UART_MCR_0_OLD_SIR_DECODE_LSB                   MK_SHIFT_CONST(10)
+#define UART_MCR_0_OLD_SIR_DECODE_WOFFSET                       0x0
+#define UART_MCR_0_OLD_SIR_DECODE_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_MCR_0_OLD_SIR_DECODE_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define UART_MCR_0_OLD_SIR_DECODE_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define UART_MCR_0_OLD_SIR_DECODE_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define UART_MCR_0_OLD_SIR_DECODE_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define UART_MCR_0_OLD_SIR_DECODE_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define UART_MCR_0_OLD_SIR_DECODE_DISABLE                       MK_ENUM_CONST(0)
+#define UART_MCR_0_OLD_SIR_DECODE_ENABLE                        MK_ENUM_CONST(1)
+
+#define UART_MCR_0_RI_POLARITY_SHIFT                    MK_SHIFT_CONST(8)
+#define UART_MCR_0_RI_POLARITY_FIELD                    MK_FIELD_CONST(0x3, UART_MCR_0_RI_POLARITY_SHIFT)
+#define UART_MCR_0_RI_POLARITY_RANGE                    9:8
+#define UART_MCR_0_RI_POLARITY_MSB                      MK_SHIFT_CONST(9)
+#define UART_MCR_0_RI_POLARITY_LSB                      MK_SHIFT_CONST(8)
+#define UART_MCR_0_RI_POLARITY_WOFFSET                  0x0
+#define UART_MCR_0_RI_POLARITY_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_MCR_0_RI_POLARITY_DEFAULT_MASK                     MK_MASK_CONST(0x3)
+#define UART_MCR_0_RI_POLARITY_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_MCR_0_RI_POLARITY_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_MCR_0_RI_POLARITY_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_MCR_0_RI_POLARITY_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_MCR_0_RI_POLARITY_LOW_TO_HIGH                      MK_ENUM_CONST(0)
+#define UART_MCR_0_RI_POLARITY_HIGH_TO_LOW                      MK_ENUM_CONST(1)
+#define UART_MCR_0_RI_POLARITY_BOTH_EDGES                       MK_ENUM_CONST(2)
+#define UART_MCR_0_RI_POLARITY_RSVD                     MK_ENUM_CONST(3)
+
+#define UART_MCR_0_DEL_QUAL_CTS_EN_SHIFT                        MK_SHIFT_CONST(7)
+#define UART_MCR_0_DEL_QUAL_CTS_EN_FIELD                        MK_FIELD_CONST(0x1, UART_MCR_0_DEL_QUAL_CTS_EN_SHIFT)
+#define UART_MCR_0_DEL_QUAL_CTS_EN_RANGE                        7:7
+#define UART_MCR_0_DEL_QUAL_CTS_EN_MSB                  MK_SHIFT_CONST(7)
+#define UART_MCR_0_DEL_QUAL_CTS_EN_LSB                  MK_SHIFT_CONST(7)
+#define UART_MCR_0_DEL_QUAL_CTS_EN_WOFFSET                      0x0
+#define UART_MCR_0_DEL_QUAL_CTS_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_MCR_0_DEL_QUAL_CTS_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define UART_MCR_0_DEL_QUAL_CTS_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_MCR_0_DEL_QUAL_CTS_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_MCR_0_DEL_QUAL_CTS_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define UART_MCR_0_DEL_QUAL_CTS_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define UART_MCR_0_DEL_QUAL_CTS_EN_DISABLE                      MK_ENUM_CONST(0)
+#define UART_MCR_0_DEL_QUAL_CTS_EN_ENABLE                       MK_ENUM_CONST(1)
+
+#define UART_MCR_0_RTS_EN_SHIFT                 MK_SHIFT_CONST(6)
+#define UART_MCR_0_RTS_EN_FIELD                 MK_FIELD_CONST(0x1, UART_MCR_0_RTS_EN_SHIFT)
+#define UART_MCR_0_RTS_EN_RANGE                 6:6
+#define UART_MCR_0_RTS_EN_MSB                   MK_SHIFT_CONST(6)
+#define UART_MCR_0_RTS_EN_LSB                   MK_SHIFT_CONST(6)
+#define UART_MCR_0_RTS_EN_WOFFSET                       0x0
+#define UART_MCR_0_RTS_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_MCR_0_RTS_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define UART_MCR_0_RTS_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define UART_MCR_0_RTS_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define UART_MCR_0_RTS_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define UART_MCR_0_RTS_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define UART_MCR_0_RTS_EN_DISABLE                       MK_ENUM_CONST(0)
+#define UART_MCR_0_RTS_EN_ENABLE                        MK_ENUM_CONST(1)
+
+#define UART_MCR_0_CTS_EN_SHIFT                 MK_SHIFT_CONST(5)
+#define UART_MCR_0_CTS_EN_FIELD                 MK_FIELD_CONST(0x1, UART_MCR_0_CTS_EN_SHIFT)
+#define UART_MCR_0_CTS_EN_RANGE                 5:5
+#define UART_MCR_0_CTS_EN_MSB                   MK_SHIFT_CONST(5)
+#define UART_MCR_0_CTS_EN_LSB                   MK_SHIFT_CONST(5)
+#define UART_MCR_0_CTS_EN_WOFFSET                       0x0
+#define UART_MCR_0_CTS_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_MCR_0_CTS_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define UART_MCR_0_CTS_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define UART_MCR_0_CTS_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define UART_MCR_0_CTS_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define UART_MCR_0_CTS_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define UART_MCR_0_CTS_EN_DISABLE                       MK_ENUM_CONST(0)
+#define UART_MCR_0_CTS_EN_ENABLE                        MK_ENUM_CONST(1)
+
+#define UART_MCR_0_LOOPBK_SHIFT                 MK_SHIFT_CONST(4)
+#define UART_MCR_0_LOOPBK_FIELD                 MK_FIELD_CONST(0x1, UART_MCR_0_LOOPBK_SHIFT)
+#define UART_MCR_0_LOOPBK_RANGE                 4:4
+#define UART_MCR_0_LOOPBK_MSB                   MK_SHIFT_CONST(4)
+#define UART_MCR_0_LOOPBK_LSB                   MK_SHIFT_CONST(4)
+#define UART_MCR_0_LOOPBK_WOFFSET                       0x0
+#define UART_MCR_0_LOOPBK_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_MCR_0_LOOPBK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define UART_MCR_0_LOOPBK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define UART_MCR_0_LOOPBK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define UART_MCR_0_LOOPBK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define UART_MCR_0_LOOPBK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define UART_MCR_0_LOOPBK_DISABLE                       MK_ENUM_CONST(0)
+#define UART_MCR_0_LOOPBK_ENABLE                        MK_ENUM_CONST(1)
+
+#define UART_MCR_0_OUT2_SHIFT                   MK_SHIFT_CONST(3)
+#define UART_MCR_0_OUT2_FIELD                   MK_FIELD_CONST(0x1, UART_MCR_0_OUT2_SHIFT)
+#define UART_MCR_0_OUT2_RANGE                   3:3
+#define UART_MCR_0_OUT2_MSB                     MK_SHIFT_CONST(3)
+#define UART_MCR_0_OUT2_LSB                     MK_SHIFT_CONST(3)
+#define UART_MCR_0_OUT2_WOFFSET                 0x0
+#define UART_MCR_0_OUT2_DEFAULT                 MK_MASK_CONST(0x0)
+#define UART_MCR_0_OUT2_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define UART_MCR_0_OUT2_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_MCR_0_OUT2_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_MCR_0_OUT2_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_MCR_0_OUT2_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define UART_MCR_0_OUT2_DISABLE                 MK_ENUM_CONST(0)
+#define UART_MCR_0_OUT2_ENABLE                  MK_ENUM_CONST(1)
+
+#define UART_MCR_0_OUT1_SHIFT                   MK_SHIFT_CONST(2)
+#define UART_MCR_0_OUT1_FIELD                   MK_FIELD_CONST(0x1, UART_MCR_0_OUT1_SHIFT)
+#define UART_MCR_0_OUT1_RANGE                   2:2
+#define UART_MCR_0_OUT1_MSB                     MK_SHIFT_CONST(2)
+#define UART_MCR_0_OUT1_LSB                     MK_SHIFT_CONST(2)
+#define UART_MCR_0_OUT1_WOFFSET                 0x0
+#define UART_MCR_0_OUT1_DEFAULT                 MK_MASK_CONST(0x0)
+#define UART_MCR_0_OUT1_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define UART_MCR_0_OUT1_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_MCR_0_OUT1_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_MCR_0_OUT1_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_MCR_0_OUT1_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define UART_MCR_0_OUT1_DISABLE                 MK_ENUM_CONST(0)
+#define UART_MCR_0_OUT1_ENABLE                  MK_ENUM_CONST(1)
+
+#define UART_MCR_0_RTS_SHIFT                    MK_SHIFT_CONST(1)
+#define UART_MCR_0_RTS_FIELD                    MK_FIELD_CONST(0x1, UART_MCR_0_RTS_SHIFT)
+#define UART_MCR_0_RTS_RANGE                    1:1
+#define UART_MCR_0_RTS_MSB                      MK_SHIFT_CONST(1)
+#define UART_MCR_0_RTS_LSB                      MK_SHIFT_CONST(1)
+#define UART_MCR_0_RTS_WOFFSET                  0x0
+#define UART_MCR_0_RTS_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_MCR_0_RTS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define UART_MCR_0_RTS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_MCR_0_RTS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_MCR_0_RTS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_MCR_0_RTS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_MCR_0_RTS_FORCE_RTS_HI                     MK_ENUM_CONST(0)
+#define UART_MCR_0_RTS_FORCE_RTS_LOW                    MK_ENUM_CONST(1)
+
+#define UART_MCR_0_DTR_SHIFT                    MK_SHIFT_CONST(0)
+#define UART_MCR_0_DTR_FIELD                    MK_FIELD_CONST(0x1, UART_MCR_0_DTR_SHIFT)
+#define UART_MCR_0_DTR_RANGE                    0:0
+#define UART_MCR_0_DTR_MSB                      MK_SHIFT_CONST(0)
+#define UART_MCR_0_DTR_LSB                      MK_SHIFT_CONST(0)
+#define UART_MCR_0_DTR_WOFFSET                  0x0
+#define UART_MCR_0_DTR_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_MCR_0_DTR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define UART_MCR_0_DTR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_MCR_0_DTR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_MCR_0_DTR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_MCR_0_DTR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_MCR_0_DTR_FORCE_DTR_HI                     MK_ENUM_CONST(0)
+#define UART_MCR_0_DTR_FORCE_DTR_LOW                    MK_ENUM_CONST(1)
+
+
+// Register UART_LSR_0
+#define UART_LSR_0                      MK_ADDR_CONST(0x14)
+#define UART_LSR_0_SECURE                       0x0
+#define UART_LSR_0_DUAL                         0x0
+#define UART_LSR_0_SCR                  0
+#define UART_LSR_0_SCRREG                       0
+#define UART_LSR_0_WORD_COUNT                   0x1
+#define UART_LSR_0_RESET_VAL                    MK_MASK_CONST(0x260)
+#define UART_LSR_0_RESET_MASK                   MK_MASK_CONST(0x3ff)
+#define UART_LSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define UART_LSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_LSR_0_READ_MASK                    MK_MASK_CONST(0x3ff)
+#define UART_LSR_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define UART_LSR_0_RX_FIFO_EMPTY_SHIFT                  MK_SHIFT_CONST(9)
+#define UART_LSR_0_RX_FIFO_EMPTY_FIELD                  MK_FIELD_CONST(0x1, UART_LSR_0_RX_FIFO_EMPTY_SHIFT)
+#define UART_LSR_0_RX_FIFO_EMPTY_RANGE                  9:9
+#define UART_LSR_0_RX_FIFO_EMPTY_MSB                    MK_SHIFT_CONST(9)
+#define UART_LSR_0_RX_FIFO_EMPTY_LSB                    MK_SHIFT_CONST(9)
+#define UART_LSR_0_RX_FIFO_EMPTY_WOFFSET                        0x0
+#define UART_LSR_0_RX_FIFO_EMPTY_DEFAULT                        MK_MASK_CONST(0x1)
+#define UART_LSR_0_RX_FIFO_EMPTY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define UART_LSR_0_RX_FIFO_EMPTY_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define UART_LSR_0_RX_FIFO_EMPTY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define UART_LSR_0_RX_FIFO_EMPTY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define UART_LSR_0_RX_FIFO_EMPTY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define UART_LSR_0_RX_FIFO_EMPTY_NOT_EMPTY                      MK_ENUM_CONST(0)
+#define UART_LSR_0_RX_FIFO_EMPTY_EMPTY                  MK_ENUM_CONST(1)
+
+#define UART_LSR_0_TX_FIFO_FULL_SHIFT                   MK_SHIFT_CONST(8)
+#define UART_LSR_0_TX_FIFO_FULL_FIELD                   MK_FIELD_CONST(0x1, UART_LSR_0_TX_FIFO_FULL_SHIFT)
+#define UART_LSR_0_TX_FIFO_FULL_RANGE                   8:8
+#define UART_LSR_0_TX_FIFO_FULL_MSB                     MK_SHIFT_CONST(8)
+#define UART_LSR_0_TX_FIFO_FULL_LSB                     MK_SHIFT_CONST(8)
+#define UART_LSR_0_TX_FIFO_FULL_WOFFSET                 0x0
+#define UART_LSR_0_TX_FIFO_FULL_DEFAULT                 MK_MASK_CONST(0x0)
+#define UART_LSR_0_TX_FIFO_FULL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define UART_LSR_0_TX_FIFO_FULL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_LSR_0_TX_FIFO_FULL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_LSR_0_TX_FIFO_FULL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_LSR_0_TX_FIFO_FULL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define UART_LSR_0_TX_FIFO_FULL_NOT_FULL                        MK_ENUM_CONST(0)
+#define UART_LSR_0_TX_FIFO_FULL_FULL                    MK_ENUM_CONST(1)
+
+#define UART_LSR_0_FIFOE_SHIFT                  MK_SHIFT_CONST(7)
+#define UART_LSR_0_FIFOE_FIELD                  MK_FIELD_CONST(0x1, UART_LSR_0_FIFOE_SHIFT)
+#define UART_LSR_0_FIFOE_RANGE                  7:7
+#define UART_LSR_0_FIFOE_MSB                    MK_SHIFT_CONST(7)
+#define UART_LSR_0_FIFOE_LSB                    MK_SHIFT_CONST(7)
+#define UART_LSR_0_FIFOE_WOFFSET                        0x0
+#define UART_LSR_0_FIFOE_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_LSR_0_FIFOE_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define UART_LSR_0_FIFOE_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define UART_LSR_0_FIFOE_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define UART_LSR_0_FIFOE_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define UART_LSR_0_FIFOE_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define UART_LSR_0_FIFOE_NO_ERR                 MK_ENUM_CONST(0)
+#define UART_LSR_0_FIFOE_ERR                    MK_ENUM_CONST(1)
+
+#define UART_LSR_0_TMTY_SHIFT                   MK_SHIFT_CONST(6)
+#define UART_LSR_0_TMTY_FIELD                   MK_FIELD_CONST(0x1, UART_LSR_0_TMTY_SHIFT)
+#define UART_LSR_0_TMTY_RANGE                   6:6
+#define UART_LSR_0_TMTY_MSB                     MK_SHIFT_CONST(6)
+#define UART_LSR_0_TMTY_LSB                     MK_SHIFT_CONST(6)
+#define UART_LSR_0_TMTY_WOFFSET                 0x0
+#define UART_LSR_0_TMTY_DEFAULT                 MK_MASK_CONST(0x1)
+#define UART_LSR_0_TMTY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define UART_LSR_0_TMTY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_LSR_0_TMTY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_LSR_0_TMTY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_LSR_0_TMTY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define UART_LSR_0_TMTY_NO_EMPTY                        MK_ENUM_CONST(0)
+#define UART_LSR_0_TMTY_EMPTY                   MK_ENUM_CONST(1)
+
+#define UART_LSR_0_THRE_SHIFT                   MK_SHIFT_CONST(5)
+#define UART_LSR_0_THRE_FIELD                   MK_FIELD_CONST(0x1, UART_LSR_0_THRE_SHIFT)
+#define UART_LSR_0_THRE_RANGE                   5:5
+#define UART_LSR_0_THRE_MSB                     MK_SHIFT_CONST(5)
+#define UART_LSR_0_THRE_LSB                     MK_SHIFT_CONST(5)
+#define UART_LSR_0_THRE_WOFFSET                 0x0
+#define UART_LSR_0_THRE_DEFAULT                 MK_MASK_CONST(0x1)
+#define UART_LSR_0_THRE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define UART_LSR_0_THRE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_LSR_0_THRE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_LSR_0_THRE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_LSR_0_THRE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define UART_LSR_0_THRE_FULL                    MK_ENUM_CONST(0)
+#define UART_LSR_0_THRE_EMPTY                   MK_ENUM_CONST(1)
+
+#define UART_LSR_0_BRK_SHIFT                    MK_SHIFT_CONST(4)
+#define UART_LSR_0_BRK_FIELD                    MK_FIELD_CONST(0x1, UART_LSR_0_BRK_SHIFT)
+#define UART_LSR_0_BRK_RANGE                    4:4
+#define UART_LSR_0_BRK_MSB                      MK_SHIFT_CONST(4)
+#define UART_LSR_0_BRK_LSB                      MK_SHIFT_CONST(4)
+#define UART_LSR_0_BRK_WOFFSET                  0x0
+#define UART_LSR_0_BRK_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_LSR_0_BRK_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define UART_LSR_0_BRK_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_LSR_0_BRK_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_LSR_0_BRK_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_LSR_0_BRK_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_LSR_0_BRK_NO_BREAK                 MK_ENUM_CONST(0)
+#define UART_LSR_0_BRK_BREAK                    MK_ENUM_CONST(1)
+
+#define UART_LSR_0_FERR_SHIFT                   MK_SHIFT_CONST(3)
+#define UART_LSR_0_FERR_FIELD                   MK_FIELD_CONST(0x1, UART_LSR_0_FERR_SHIFT)
+#define UART_LSR_0_FERR_RANGE                   3:3
+#define UART_LSR_0_FERR_MSB                     MK_SHIFT_CONST(3)
+#define UART_LSR_0_FERR_LSB                     MK_SHIFT_CONST(3)
+#define UART_LSR_0_FERR_WOFFSET                 0x0
+#define UART_LSR_0_FERR_DEFAULT                 MK_MASK_CONST(0x0)
+#define UART_LSR_0_FERR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define UART_LSR_0_FERR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_LSR_0_FERR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_LSR_0_FERR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_LSR_0_FERR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define UART_LSR_0_FERR_NO_FRAME_ERR                    MK_ENUM_CONST(0)
+#define UART_LSR_0_FERR_FRAME_ERR                       MK_ENUM_CONST(1)
+
+#define UART_LSR_0_PERR_SHIFT                   MK_SHIFT_CONST(2)
+#define UART_LSR_0_PERR_FIELD                   MK_FIELD_CONST(0x1, UART_LSR_0_PERR_SHIFT)
+#define UART_LSR_0_PERR_RANGE                   2:2
+#define UART_LSR_0_PERR_MSB                     MK_SHIFT_CONST(2)
+#define UART_LSR_0_PERR_LSB                     MK_SHIFT_CONST(2)
+#define UART_LSR_0_PERR_WOFFSET                 0x0
+#define UART_LSR_0_PERR_DEFAULT                 MK_MASK_CONST(0x0)
+#define UART_LSR_0_PERR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define UART_LSR_0_PERR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_LSR_0_PERR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_LSR_0_PERR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_LSR_0_PERR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define UART_LSR_0_PERR_NO_PARITY_ERR                   MK_ENUM_CONST(0)
+#define UART_LSR_0_PERR_PARITY_ERR                      MK_ENUM_CONST(1)
+
+#define UART_LSR_0_OVRF_SHIFT                   MK_SHIFT_CONST(1)
+#define UART_LSR_0_OVRF_FIELD                   MK_FIELD_CONST(0x1, UART_LSR_0_OVRF_SHIFT)
+#define UART_LSR_0_OVRF_RANGE                   1:1
+#define UART_LSR_0_OVRF_MSB                     MK_SHIFT_CONST(1)
+#define UART_LSR_0_OVRF_LSB                     MK_SHIFT_CONST(1)
+#define UART_LSR_0_OVRF_WOFFSET                 0x0
+#define UART_LSR_0_OVRF_DEFAULT                 MK_MASK_CONST(0x0)
+#define UART_LSR_0_OVRF_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define UART_LSR_0_OVRF_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_LSR_0_OVRF_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_LSR_0_OVRF_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_LSR_0_OVRF_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define UART_LSR_0_OVRF_NO_OVERRUN_ERROR                        MK_ENUM_CONST(0)
+#define UART_LSR_0_OVRF_OVERRUN_ERROR                   MK_ENUM_CONST(1)
+
+#define UART_LSR_0_RDR_SHIFT                    MK_SHIFT_CONST(0)
+#define UART_LSR_0_RDR_FIELD                    MK_FIELD_CONST(0x1, UART_LSR_0_RDR_SHIFT)
+#define UART_LSR_0_RDR_RANGE                    0:0
+#define UART_LSR_0_RDR_MSB                      MK_SHIFT_CONST(0)
+#define UART_LSR_0_RDR_LSB                      MK_SHIFT_CONST(0)
+#define UART_LSR_0_RDR_WOFFSET                  0x0
+#define UART_LSR_0_RDR_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_LSR_0_RDR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define UART_LSR_0_RDR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_LSR_0_RDR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_LSR_0_RDR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_LSR_0_RDR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_LSR_0_RDR_NO_DATA_IN_FIFO                  MK_ENUM_CONST(0)
+#define UART_LSR_0_RDR_DATA_IN_FIFO                     MK_ENUM_CONST(1)
+
+
+// Register UART_MSR_0
+#define UART_MSR_0                      MK_ADDR_CONST(0x18)
+#define UART_MSR_0_SECURE                       0x0
+#define UART_MSR_0_DUAL                         0x0
+#define UART_MSR_0_SCR                  0
+#define UART_MSR_0_SCRREG                       0
+#define UART_MSR_0_WORD_COUNT                   0x1
+#define UART_MSR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define UART_MSR_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define UART_MSR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define UART_MSR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_MSR_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define UART_MSR_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define UART_MSR_0_CD_SHIFT                     MK_SHIFT_CONST(7)
+#define UART_MSR_0_CD_FIELD                     MK_FIELD_CONST(0x1, UART_MSR_0_CD_SHIFT)
+#define UART_MSR_0_CD_RANGE                     7:7
+#define UART_MSR_0_CD_MSB                       MK_SHIFT_CONST(7)
+#define UART_MSR_0_CD_LSB                       MK_SHIFT_CONST(7)
+#define UART_MSR_0_CD_WOFFSET                   0x0
+#define UART_MSR_0_CD_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_MSR_0_CD_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define UART_MSR_0_CD_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_MSR_0_CD_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define UART_MSR_0_CD_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define UART_MSR_0_CD_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define UART_MSR_0_CD_DISABLE                   MK_ENUM_CONST(0)
+#define UART_MSR_0_CD_ENABLE                    MK_ENUM_CONST(1)
+
+#define UART_MSR_0_RI_SHIFT                     MK_SHIFT_CONST(6)
+#define UART_MSR_0_RI_FIELD                     MK_FIELD_CONST(0x1, UART_MSR_0_RI_SHIFT)
+#define UART_MSR_0_RI_RANGE                     6:6
+#define UART_MSR_0_RI_MSB                       MK_SHIFT_CONST(6)
+#define UART_MSR_0_RI_LSB                       MK_SHIFT_CONST(6)
+#define UART_MSR_0_RI_WOFFSET                   0x0
+#define UART_MSR_0_RI_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_MSR_0_RI_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define UART_MSR_0_RI_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_MSR_0_RI_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define UART_MSR_0_RI_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define UART_MSR_0_RI_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define UART_MSR_0_RI_DISABLE                   MK_ENUM_CONST(0)
+#define UART_MSR_0_RI_ENABLE                    MK_ENUM_CONST(1)
+
+#define UART_MSR_0_DSR_SHIFT                    MK_SHIFT_CONST(5)
+#define UART_MSR_0_DSR_FIELD                    MK_FIELD_CONST(0x1, UART_MSR_0_DSR_SHIFT)
+#define UART_MSR_0_DSR_RANGE                    5:5
+#define UART_MSR_0_DSR_MSB                      MK_SHIFT_CONST(5)
+#define UART_MSR_0_DSR_LSB                      MK_SHIFT_CONST(5)
+#define UART_MSR_0_DSR_WOFFSET                  0x0
+#define UART_MSR_0_DSR_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_MSR_0_DSR_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define UART_MSR_0_DSR_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_MSR_0_DSR_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_MSR_0_DSR_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_MSR_0_DSR_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_MSR_0_DSR_DISABLE                  MK_ENUM_CONST(0)
+#define UART_MSR_0_DSR_ENABLE                   MK_ENUM_CONST(1)
+
+#define UART_MSR_0_CTS_SHIFT                    MK_SHIFT_CONST(4)
+#define UART_MSR_0_CTS_FIELD                    MK_FIELD_CONST(0x1, UART_MSR_0_CTS_SHIFT)
+#define UART_MSR_0_CTS_RANGE                    4:4
+#define UART_MSR_0_CTS_MSB                      MK_SHIFT_CONST(4)
+#define UART_MSR_0_CTS_LSB                      MK_SHIFT_CONST(4)
+#define UART_MSR_0_CTS_WOFFSET                  0x0
+#define UART_MSR_0_CTS_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_MSR_0_CTS_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define UART_MSR_0_CTS_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_MSR_0_CTS_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_MSR_0_CTS_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_MSR_0_CTS_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_MSR_0_CTS_DISABLE                  MK_ENUM_CONST(0)
+#define UART_MSR_0_CTS_ENABLE                   MK_ENUM_CONST(1)
+
+#define UART_MSR_0_DCD_SHIFT                    MK_SHIFT_CONST(3)
+#define UART_MSR_0_DCD_FIELD                    MK_FIELD_CONST(0x1, UART_MSR_0_DCD_SHIFT)
+#define UART_MSR_0_DCD_RANGE                    3:3
+#define UART_MSR_0_DCD_MSB                      MK_SHIFT_CONST(3)
+#define UART_MSR_0_DCD_LSB                      MK_SHIFT_CONST(3)
+#define UART_MSR_0_DCD_WOFFSET                  0x0
+#define UART_MSR_0_DCD_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_MSR_0_DCD_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define UART_MSR_0_DCD_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_MSR_0_DCD_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_MSR_0_DCD_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_MSR_0_DCD_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_MSR_0_DCD_DISABLE                  MK_ENUM_CONST(0)
+#define UART_MSR_0_DCD_ENABLE                   MK_ENUM_CONST(1)
+
+#define UART_MSR_0_DRI_SHIFT                    MK_SHIFT_CONST(2)
+#define UART_MSR_0_DRI_FIELD                    MK_FIELD_CONST(0x1, UART_MSR_0_DRI_SHIFT)
+#define UART_MSR_0_DRI_RANGE                    2:2
+#define UART_MSR_0_DRI_MSB                      MK_SHIFT_CONST(2)
+#define UART_MSR_0_DRI_LSB                      MK_SHIFT_CONST(2)
+#define UART_MSR_0_DRI_WOFFSET                  0x0
+#define UART_MSR_0_DRI_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_MSR_0_DRI_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define UART_MSR_0_DRI_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_MSR_0_DRI_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_MSR_0_DRI_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_MSR_0_DRI_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_MSR_0_DRI_DISABLE                  MK_ENUM_CONST(0)
+#define UART_MSR_0_DRI_ENABLE                   MK_ENUM_CONST(1)
+
+#define UART_MSR_0_DDSR_SHIFT                   MK_SHIFT_CONST(1)
+#define UART_MSR_0_DDSR_FIELD                   MK_FIELD_CONST(0x1, UART_MSR_0_DDSR_SHIFT)
+#define UART_MSR_0_DDSR_RANGE                   1:1
+#define UART_MSR_0_DDSR_MSB                     MK_SHIFT_CONST(1)
+#define UART_MSR_0_DDSR_LSB                     MK_SHIFT_CONST(1)
+#define UART_MSR_0_DDSR_WOFFSET                 0x0
+#define UART_MSR_0_DDSR_DEFAULT                 MK_MASK_CONST(0x0)
+#define UART_MSR_0_DDSR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define UART_MSR_0_DDSR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_MSR_0_DDSR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_MSR_0_DDSR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_MSR_0_DDSR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define UART_MSR_0_DDSR_DISABLE                 MK_ENUM_CONST(0)
+#define UART_MSR_0_DDSR_ENABLE                  MK_ENUM_CONST(1)
+
+#define UART_MSR_0_DCTS_SHIFT                   MK_SHIFT_CONST(0)
+#define UART_MSR_0_DCTS_FIELD                   MK_FIELD_CONST(0x1, UART_MSR_0_DCTS_SHIFT)
+#define UART_MSR_0_DCTS_RANGE                   0:0
+#define UART_MSR_0_DCTS_MSB                     MK_SHIFT_CONST(0)
+#define UART_MSR_0_DCTS_LSB                     MK_SHIFT_CONST(0)
+#define UART_MSR_0_DCTS_WOFFSET                 0x0
+#define UART_MSR_0_DCTS_DEFAULT                 MK_MASK_CONST(0x0)
+#define UART_MSR_0_DCTS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define UART_MSR_0_DCTS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_MSR_0_DCTS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_MSR_0_DCTS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_MSR_0_DCTS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define UART_MSR_0_DCTS_DISABLE                 MK_ENUM_CONST(0)
+#define UART_MSR_0_DCTS_ENABLE                  MK_ENUM_CONST(1)
+
+
+// Register UART_SPR_0
+#define UART_SPR_0                      MK_ADDR_CONST(0x1c)
+#define UART_SPR_0_SECURE                       0x0
+#define UART_SPR_0_DUAL                         0x0
+#define UART_SPR_0_SCR                  0
+#define UART_SPR_0_SCRREG                       0
+#define UART_SPR_0_WORD_COUNT                   0x1
+#define UART_SPR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define UART_SPR_0_RESET_MASK                   MK_MASK_CONST(0xff)
+#define UART_SPR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define UART_SPR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_SPR_0_READ_MASK                    MK_MASK_CONST(0xff)
+#define UART_SPR_0_WRITE_MASK                   MK_MASK_CONST(0xff)
+#define UART_SPR_0_SPR_A_SHIFT                  MK_SHIFT_CONST(0)
+#define UART_SPR_0_SPR_A_FIELD                  MK_FIELD_CONST(0xff, UART_SPR_0_SPR_A_SHIFT)
+#define UART_SPR_0_SPR_A_RANGE                  7:0
+#define UART_SPR_0_SPR_A_MSB                    MK_SHIFT_CONST(7)
+#define UART_SPR_0_SPR_A_LSB                    MK_SHIFT_CONST(0)
+#define UART_SPR_0_SPR_A_WOFFSET                        0x0
+#define UART_SPR_0_SPR_A_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_SPR_0_SPR_A_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define UART_SPR_0_SPR_A_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define UART_SPR_0_SPR_A_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define UART_SPR_0_SPR_A_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define UART_SPR_0_SPR_A_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register UART_IRDA_CSR_0
+#define UART_IRDA_CSR_0                 MK_ADDR_CONST(0x20)
+#define UART_IRDA_CSR_0_SECURE                  0x0
+#define UART_IRDA_CSR_0_DUAL                    0x0
+#define UART_IRDA_CSR_0_SCR                     0
+#define UART_IRDA_CSR_0_SCRREG                  0
+#define UART_IRDA_CSR_0_WORD_COUNT                      0x1
+#define UART_IRDA_CSR_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_RESET_MASK                      MK_MASK_CONST(0xcf)
+#define UART_IRDA_CSR_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_READ_MASK                       MK_MASK_CONST(0xcf)
+#define UART_IRDA_CSR_0_WRITE_MASK                      MK_MASK_CONST(0xcf)
+#define UART_IRDA_CSR_0_SIR_A_SHIFT                     MK_SHIFT_CONST(7)
+#define UART_IRDA_CSR_0_SIR_A_FIELD                     MK_FIELD_CONST(0x1, UART_IRDA_CSR_0_SIR_A_SHIFT)
+#define UART_IRDA_CSR_0_SIR_A_RANGE                     7:7
+#define UART_IRDA_CSR_0_SIR_A_MSB                       MK_SHIFT_CONST(7)
+#define UART_IRDA_CSR_0_SIR_A_LSB                       MK_SHIFT_CONST(7)
+#define UART_IRDA_CSR_0_SIR_A_WOFFSET                   0x0
+#define UART_IRDA_CSR_0_SIR_A_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_SIR_A_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_SIR_A_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_SIR_A_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_SIR_A_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_SIR_A_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_SIR_A_DISABLE                   MK_ENUM_CONST(0)
+#define UART_IRDA_CSR_0_SIR_A_ENABLE                    MK_ENUM_CONST(1)
+
+#define UART_IRDA_CSR_0_PWT_A_SHIFT                     MK_SHIFT_CONST(6)
+#define UART_IRDA_CSR_0_PWT_A_FIELD                     MK_FIELD_CONST(0x1, UART_IRDA_CSR_0_PWT_A_SHIFT)
+#define UART_IRDA_CSR_0_PWT_A_RANGE                     6:6
+#define UART_IRDA_CSR_0_PWT_A_MSB                       MK_SHIFT_CONST(6)
+#define UART_IRDA_CSR_0_PWT_A_LSB                       MK_SHIFT_CONST(6)
+#define UART_IRDA_CSR_0_PWT_A_WOFFSET                   0x0
+#define UART_IRDA_CSR_0_PWT_A_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_PWT_A_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_PWT_A_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_PWT_A_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_PWT_A_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_PWT_A_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_PWT_A_BAUD_PULSE_3_14                   MK_ENUM_CONST(0)
+#define UART_IRDA_CSR_0_PWT_A_BAUD_PULSE_4_14                   MK_ENUM_CONST(1)
+
+#define UART_IRDA_CSR_0_INVERT_RTS_SHIFT                        MK_SHIFT_CONST(3)
+#define UART_IRDA_CSR_0_INVERT_RTS_FIELD                        MK_FIELD_CONST(0x1, UART_IRDA_CSR_0_INVERT_RTS_SHIFT)
+#define UART_IRDA_CSR_0_INVERT_RTS_RANGE                        3:3
+#define UART_IRDA_CSR_0_INVERT_RTS_MSB                  MK_SHIFT_CONST(3)
+#define UART_IRDA_CSR_0_INVERT_RTS_LSB                  MK_SHIFT_CONST(3)
+#define UART_IRDA_CSR_0_INVERT_RTS_WOFFSET                      0x0
+#define UART_IRDA_CSR_0_INVERT_RTS_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_RTS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_INVERT_RTS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_RTS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_RTS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_RTS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_INVERT_RTS_DISABLE                      MK_ENUM_CONST(0)
+#define UART_IRDA_CSR_0_INVERT_RTS_ENABLE                       MK_ENUM_CONST(1)
+
+#define UART_IRDA_CSR_0_INVERT_CTS_SHIFT                        MK_SHIFT_CONST(2)
+#define UART_IRDA_CSR_0_INVERT_CTS_FIELD                        MK_FIELD_CONST(0x1, UART_IRDA_CSR_0_INVERT_CTS_SHIFT)
+#define UART_IRDA_CSR_0_INVERT_CTS_RANGE                        2:2
+#define UART_IRDA_CSR_0_INVERT_CTS_MSB                  MK_SHIFT_CONST(2)
+#define UART_IRDA_CSR_0_INVERT_CTS_LSB                  MK_SHIFT_CONST(2)
+#define UART_IRDA_CSR_0_INVERT_CTS_WOFFSET                      0x0
+#define UART_IRDA_CSR_0_INVERT_CTS_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_CTS_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_INVERT_CTS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_CTS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_CTS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_CTS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_INVERT_CTS_DISABLE                      MK_ENUM_CONST(0)
+#define UART_IRDA_CSR_0_INVERT_CTS_ENABLE                       MK_ENUM_CONST(1)
+
+#define UART_IRDA_CSR_0_INVERT_TXD_SHIFT                        MK_SHIFT_CONST(1)
+#define UART_IRDA_CSR_0_INVERT_TXD_FIELD                        MK_FIELD_CONST(0x1, UART_IRDA_CSR_0_INVERT_TXD_SHIFT)
+#define UART_IRDA_CSR_0_INVERT_TXD_RANGE                        1:1
+#define UART_IRDA_CSR_0_INVERT_TXD_MSB                  MK_SHIFT_CONST(1)
+#define UART_IRDA_CSR_0_INVERT_TXD_LSB                  MK_SHIFT_CONST(1)
+#define UART_IRDA_CSR_0_INVERT_TXD_WOFFSET                      0x0
+#define UART_IRDA_CSR_0_INVERT_TXD_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_TXD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_INVERT_TXD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_TXD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_TXD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_TXD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_INVERT_TXD_DISABLE                      MK_ENUM_CONST(0)
+#define UART_IRDA_CSR_0_INVERT_TXD_ENABLE                       MK_ENUM_CONST(1)
+
+#define UART_IRDA_CSR_0_INVERT_RXD_SHIFT                        MK_SHIFT_CONST(0)
+#define UART_IRDA_CSR_0_INVERT_RXD_FIELD                        MK_FIELD_CONST(0x1, UART_IRDA_CSR_0_INVERT_RXD_SHIFT)
+#define UART_IRDA_CSR_0_INVERT_RXD_RANGE                        0:0
+#define UART_IRDA_CSR_0_INVERT_RXD_MSB                  MK_SHIFT_CONST(0)
+#define UART_IRDA_CSR_0_INVERT_RXD_LSB                  MK_SHIFT_CONST(0)
+#define UART_IRDA_CSR_0_INVERT_RXD_WOFFSET                      0x0
+#define UART_IRDA_CSR_0_INVERT_RXD_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_RXD_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_INVERT_RXD_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_RXD_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_RXD_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define UART_IRDA_CSR_0_INVERT_RXD_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define UART_IRDA_CSR_0_INVERT_RXD_DISABLE                      MK_ENUM_CONST(0)
+#define UART_IRDA_CSR_0_INVERT_RXD_ENABLE                       MK_ENUM_CONST(1)
+
+
+// Register UART_RX_FIFO_CFG_0
+#define UART_RX_FIFO_CFG_0                      MK_ADDR_CONST(0x24)
+#define UART_RX_FIFO_CFG_0_SECURE                       0x0
+#define UART_RX_FIFO_CFG_0_DUAL                         0x0
+#define UART_RX_FIFO_CFG_0_SCR                  0
+#define UART_RX_FIFO_CFG_0_SCRREG                       0
+#define UART_RX_FIFO_CFG_0_WORD_COUNT                   0x1
+#define UART_RX_FIFO_CFG_0_RESET_VAL                    MK_MASK_CONST(0x1)
+#define UART_RX_FIFO_CFG_0_RESET_MASK                   MK_MASK_CONST(0xbf)
+#define UART_RX_FIFO_CFG_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define UART_RX_FIFO_CFG_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_RX_FIFO_CFG_0_READ_MASK                    MK_MASK_CONST(0xbf)
+#define UART_RX_FIFO_CFG_0_WRITE_MASK                   MK_MASK_CONST(0xbf)
+#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_SHIFT                        MK_SHIFT_CONST(7)
+#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_FIELD                        MK_FIELD_CONST(0x1, UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_SHIFT)
+#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_RANGE                        7:7
+#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_MSB                  MK_SHIFT_CONST(7)
+#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_LSB                  MK_SHIFT_CONST(7)
+#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_WOFFSET                      0x0
+#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_DISABLE                      MK_ENUM_CONST(0)
+#define UART_RX_FIFO_CFG_0_EN_RX_FIFO_TRIG_ENABLE                       MK_ENUM_CONST(1)
+
+#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_SHIFT                   MK_SHIFT_CONST(0)
+#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_FIELD                   MK_FIELD_CONST(0x3f, UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_SHIFT)
+#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_RANGE                   5:0
+#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_MSB                     MK_SHIFT_CONST(5)
+#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_LSB                     MK_SHIFT_CONST(0)
+#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_WOFFSET                 0x0
+#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_DEFAULT                 MK_MASK_CONST(0x1)
+#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_RX_FIFO_CFG_0_RX_FIFO_TRIG_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register UART_MIE_0
+#define UART_MIE_0                      MK_ADDR_CONST(0x28)
+#define UART_MIE_0_SECURE                       0x0
+#define UART_MIE_0_DUAL                         0x0
+#define UART_MIE_0_SCR                  0
+#define UART_MIE_0_SCRREG                       0
+#define UART_MIE_0_WORD_COUNT                   0x1
+#define UART_MIE_0_RESET_VAL                    MK_MASK_CONST(0xf)
+#define UART_MIE_0_RESET_MASK                   MK_MASK_CONST(0xf)
+#define UART_MIE_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define UART_MIE_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_MIE_0_READ_MASK                    MK_MASK_CONST(0xf)
+#define UART_MIE_0_WRITE_MASK                   MK_MASK_CONST(0xf)
+#define UART_MIE_0_DCD_INT_EN_SHIFT                     MK_SHIFT_CONST(3)
+#define UART_MIE_0_DCD_INT_EN_FIELD                     MK_FIELD_CONST(0x1, UART_MIE_0_DCD_INT_EN_SHIFT)
+#define UART_MIE_0_DCD_INT_EN_RANGE                     3:3
+#define UART_MIE_0_DCD_INT_EN_MSB                       MK_SHIFT_CONST(3)
+#define UART_MIE_0_DCD_INT_EN_LSB                       MK_SHIFT_CONST(3)
+#define UART_MIE_0_DCD_INT_EN_WOFFSET                   0x0
+#define UART_MIE_0_DCD_INT_EN_DEFAULT                   MK_MASK_CONST(0x1)
+#define UART_MIE_0_DCD_INT_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define UART_MIE_0_DCD_INT_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_MIE_0_DCD_INT_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define UART_MIE_0_DCD_INT_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define UART_MIE_0_DCD_INT_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define UART_MIE_0_DCD_INT_EN_DISABLE                   MK_ENUM_CONST(0)
+#define UART_MIE_0_DCD_INT_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define UART_MIE_0_DRI_INT_EN_SHIFT                     MK_SHIFT_CONST(2)
+#define UART_MIE_0_DRI_INT_EN_FIELD                     MK_FIELD_CONST(0x1, UART_MIE_0_DRI_INT_EN_SHIFT)
+#define UART_MIE_0_DRI_INT_EN_RANGE                     2:2
+#define UART_MIE_0_DRI_INT_EN_MSB                       MK_SHIFT_CONST(2)
+#define UART_MIE_0_DRI_INT_EN_LSB                       MK_SHIFT_CONST(2)
+#define UART_MIE_0_DRI_INT_EN_WOFFSET                   0x0
+#define UART_MIE_0_DRI_INT_EN_DEFAULT                   MK_MASK_CONST(0x1)
+#define UART_MIE_0_DRI_INT_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define UART_MIE_0_DRI_INT_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_MIE_0_DRI_INT_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define UART_MIE_0_DRI_INT_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define UART_MIE_0_DRI_INT_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define UART_MIE_0_DRI_INT_EN_DISABLE                   MK_ENUM_CONST(0)
+#define UART_MIE_0_DRI_INT_EN_ENABLE                    MK_ENUM_CONST(1)
+
+#define UART_MIE_0_DDSR_INT_EN_SHIFT                    MK_SHIFT_CONST(1)
+#define UART_MIE_0_DDSR_INT_EN_FIELD                    MK_FIELD_CONST(0x1, UART_MIE_0_DDSR_INT_EN_SHIFT)
+#define UART_MIE_0_DDSR_INT_EN_RANGE                    1:1
+#define UART_MIE_0_DDSR_INT_EN_MSB                      MK_SHIFT_CONST(1)
+#define UART_MIE_0_DDSR_INT_EN_LSB                      MK_SHIFT_CONST(1)
+#define UART_MIE_0_DDSR_INT_EN_WOFFSET                  0x0
+#define UART_MIE_0_DDSR_INT_EN_DEFAULT                  MK_MASK_CONST(0x1)
+#define UART_MIE_0_DDSR_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define UART_MIE_0_DDSR_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_MIE_0_DDSR_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_MIE_0_DDSR_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_MIE_0_DDSR_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_MIE_0_DDSR_INT_EN_DISABLE                  MK_ENUM_CONST(0)
+#define UART_MIE_0_DDSR_INT_EN_ENABLE                   MK_ENUM_CONST(1)
+
+#define UART_MIE_0_DCTS_INT_EN_SHIFT                    MK_SHIFT_CONST(0)
+#define UART_MIE_0_DCTS_INT_EN_FIELD                    MK_FIELD_CONST(0x1, UART_MIE_0_DCTS_INT_EN_SHIFT)
+#define UART_MIE_0_DCTS_INT_EN_RANGE                    0:0
+#define UART_MIE_0_DCTS_INT_EN_MSB                      MK_SHIFT_CONST(0)
+#define UART_MIE_0_DCTS_INT_EN_LSB                      MK_SHIFT_CONST(0)
+#define UART_MIE_0_DCTS_INT_EN_WOFFSET                  0x0
+#define UART_MIE_0_DCTS_INT_EN_DEFAULT                  MK_MASK_CONST(0x1)
+#define UART_MIE_0_DCTS_INT_EN_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define UART_MIE_0_DCTS_INT_EN_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_MIE_0_DCTS_INT_EN_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_MIE_0_DCTS_INT_EN_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_MIE_0_DCTS_INT_EN_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define UART_MIE_0_DCTS_INT_EN_DISABLE                  MK_ENUM_CONST(0)
+#define UART_MIE_0_DCTS_INT_EN_ENABLE                   MK_ENUM_CONST(1)
+
+
+// Register UART_VENDOR_STATUS_0_0
+#define UART_VENDOR_STATUS_0_0                  MK_ADDR_CONST(0x2c)
+#define UART_VENDOR_STATUS_0_0_SECURE                   0x0
+#define UART_VENDOR_STATUS_0_0_DUAL                     0x0
+#define UART_VENDOR_STATUS_0_0_SCR                      0
+#define UART_VENDOR_STATUS_0_0_SCRREG                   0
+#define UART_VENDOR_STATUS_0_0_WORD_COUNT                       0x1
+#define UART_VENDOR_STATUS_0_0_RESET_VAL                        MK_MASK_CONST(0x3)
+#define UART_VENDOR_STATUS_0_0_RESET_MASK                       MK_MASK_CONST(0x3f3f000f)
+#define UART_VENDOR_STATUS_0_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_READ_MASK                        MK_MASK_CONST(0x3f3f000f)
+#define UART_VENDOR_STATUS_0_0_WRITE_MASK                       MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_SHIFT                    MK_SHIFT_CONST(24)
+#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_FIELD                    MK_FIELD_CONST(0x3f, UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_SHIFT)
+#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_RANGE                    29:24
+#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_MSB                      MK_SHIFT_CONST(29)
+#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_LSB                      MK_SHIFT_CONST(24)
+#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_WOFFSET                  0x0
+#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_DEFAULT_MASK                     MK_MASK_CONST(0x3f)
+#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_TX_FIFO_COUNTER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_SHIFT                    MK_SHIFT_CONST(16)
+#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_FIELD                    MK_FIELD_CONST(0x3f, UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_SHIFT)
+#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_RANGE                    21:16
+#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_MSB                      MK_SHIFT_CONST(21)
+#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_LSB                      MK_SHIFT_CONST(16)
+#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_WOFFSET                  0x0
+#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_DEFAULT_MASK                     MK_MASK_CONST(0x3f)
+#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_RX_FIFO_COUNTER_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_SHIFT                 MK_SHIFT_CONST(3)
+#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_FIELD                 MK_FIELD_CONST(0x1, UART_VENDOR_STATUS_0_0_TX_OVERRUN_SHIFT)
+#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_RANGE                 3:3
+#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_MSB                   MK_SHIFT_CONST(3)
+#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_LSB                   MK_SHIFT_CONST(3)
+#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_WOFFSET                       0x0
+#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_DEFAULT                       MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_NO_OVERRUN                    MK_ENUM_CONST(0)
+#define UART_VENDOR_STATUS_0_0_TX_OVERRUN_OVERRUN                       MK_ENUM_CONST(1)
+
+#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_SHIFT                        MK_SHIFT_CONST(2)
+#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_FIELD                        MK_FIELD_CONST(0x1, UART_VENDOR_STATUS_0_0_RX_UNDERRUN_SHIFT)
+#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_RANGE                        2:2
+#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_MSB                  MK_SHIFT_CONST(2)
+#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_LSB                  MK_SHIFT_CONST(2)
+#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_WOFFSET                      0x0
+#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_NO_UNDERRUN                  MK_ENUM_CONST(0)
+#define UART_VENDOR_STATUS_0_0_RX_UNDERRUN_UNDERRUN                     MK_ENUM_CONST(1)
+
+#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_SHIFT                       MK_SHIFT_CONST(1)
+#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_FIELD                       MK_FIELD_CONST(0x1, UART_VENDOR_STATUS_0_0_UART_RX_IDLE_SHIFT)
+#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_RANGE                       1:1
+#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_MSB                 MK_SHIFT_CONST(1)
+#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_LSB                 MK_SHIFT_CONST(1)
+#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_WOFFSET                     0x0
+#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_DEFAULT                     MK_MASK_CONST(0x1)
+#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_BUSY                        MK_ENUM_CONST(0)
+#define UART_VENDOR_STATUS_0_0_UART_RX_IDLE_IDLE                        MK_ENUM_CONST(1)
+
+#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_SHIFT                       MK_SHIFT_CONST(0)
+#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_FIELD                       MK_FIELD_CONST(0x1, UART_VENDOR_STATUS_0_0_UART_TX_IDLE_SHIFT)
+#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_RANGE                       0:0
+#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_MSB                 MK_SHIFT_CONST(0)
+#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_LSB                 MK_SHIFT_CONST(0)
+#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_WOFFSET                     0x0
+#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_DEFAULT                     MK_MASK_CONST(0x1)
+#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_BUSY                        MK_ENUM_CONST(0)
+#define UART_VENDOR_STATUS_0_0_UART_TX_IDLE_IDLE                        MK_ENUM_CONST(1)
+
+
+// Reserved address 0x30
+
+// Reserved address 0x34
+
+// Reserved address 0x38
+
+// Register UART_ASR_0
+#define UART_ASR_0                      MK_ADDR_CONST(0x3c)
+#define UART_ASR_0_SECURE                       0x0
+#define UART_ASR_0_DUAL                         0x0
+#define UART_ASR_0_SCR                  0
+#define UART_ASR_0_SCRREG                       0
+#define UART_ASR_0_WORD_COUNT                   0x1
+#define UART_ASR_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define UART_ASR_0_RESET_MASK                   MK_MASK_CONST(0xc000ffff)
+#define UART_ASR_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define UART_ASR_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_ASR_0_READ_MASK                    MK_MASK_CONST(0xc000ffff)
+#define UART_ASR_0_WRITE_MASK                   MK_MASK_CONST(0xc000ffff)
+#define UART_ASR_0_VALID_SHIFT                  MK_SHIFT_CONST(31)
+#define UART_ASR_0_VALID_FIELD                  MK_FIELD_CONST(0x1, UART_ASR_0_VALID_SHIFT)
+#define UART_ASR_0_VALID_RANGE                  31:31
+#define UART_ASR_0_VALID_MSB                    MK_SHIFT_CONST(31)
+#define UART_ASR_0_VALID_LSB                    MK_SHIFT_CONST(31)
+#define UART_ASR_0_VALID_WOFFSET                        0x0
+#define UART_ASR_0_VALID_DEFAULT                        MK_MASK_CONST(0x0)
+#define UART_ASR_0_VALID_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define UART_ASR_0_VALID_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define UART_ASR_0_VALID_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define UART_ASR_0_VALID_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define UART_ASR_0_VALID_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define UART_ASR_0_VALID_UN_SET                 MK_ENUM_CONST(0)
+#define UART_ASR_0_VALID_SET                    MK_ENUM_CONST(1)
+
+#define UART_ASR_0_BUSY_SHIFT                   MK_SHIFT_CONST(30)
+#define UART_ASR_0_BUSY_FIELD                   MK_FIELD_CONST(0x1, UART_ASR_0_BUSY_SHIFT)
+#define UART_ASR_0_BUSY_RANGE                   30:30
+#define UART_ASR_0_BUSY_MSB                     MK_SHIFT_CONST(30)
+#define UART_ASR_0_BUSY_LSB                     MK_SHIFT_CONST(30)
+#define UART_ASR_0_BUSY_WOFFSET                 0x0
+#define UART_ASR_0_BUSY_DEFAULT                 MK_MASK_CONST(0x0)
+#define UART_ASR_0_BUSY_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define UART_ASR_0_BUSY_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_ASR_0_BUSY_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define UART_ASR_0_BUSY_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define UART_ASR_0_BUSY_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define UART_ASR_0_BUSY_NO_BUSY                 MK_ENUM_CONST(0)
+#define UART_ASR_0_BUSY_BUSY                    MK_ENUM_CONST(1)
+
+#define UART_ASR_0_RX_RATE_SENSE_H_SHIFT                        MK_SHIFT_CONST(8)
+#define UART_ASR_0_RX_RATE_SENSE_H_FIELD                        MK_FIELD_CONST(0xff, UART_ASR_0_RX_RATE_SENSE_H_SHIFT)
+#define UART_ASR_0_RX_RATE_SENSE_H_RANGE                        15:8
+#define UART_ASR_0_RX_RATE_SENSE_H_MSB                  MK_SHIFT_CONST(15)
+#define UART_ASR_0_RX_RATE_SENSE_H_LSB                  MK_SHIFT_CONST(8)
+#define UART_ASR_0_RX_RATE_SENSE_H_WOFFSET                      0x0
+#define UART_ASR_0_RX_RATE_SENSE_H_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_ASR_0_RX_RATE_SENSE_H_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define UART_ASR_0_RX_RATE_SENSE_H_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_ASR_0_RX_RATE_SENSE_H_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_ASR_0_RX_RATE_SENSE_H_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define UART_ASR_0_RX_RATE_SENSE_H_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+#define UART_ASR_0_RX_RATE_SENSE_L_SHIFT                        MK_SHIFT_CONST(0)
+#define UART_ASR_0_RX_RATE_SENSE_L_FIELD                        MK_FIELD_CONST(0xff, UART_ASR_0_RX_RATE_SENSE_L_SHIFT)
+#define UART_ASR_0_RX_RATE_SENSE_L_RANGE                        7:0
+#define UART_ASR_0_RX_RATE_SENSE_L_MSB                  MK_SHIFT_CONST(7)
+#define UART_ASR_0_RX_RATE_SENSE_L_LSB                  MK_SHIFT_CONST(0)
+#define UART_ASR_0_RX_RATE_SENSE_L_WOFFSET                      0x0
+#define UART_ASR_0_RX_RATE_SENSE_L_DEFAULT                      MK_MASK_CONST(0x0)
+#define UART_ASR_0_RX_RATE_SENSE_L_DEFAULT_MASK                 MK_MASK_CONST(0xff)
+#define UART_ASR_0_RX_RATE_SENSE_L_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define UART_ASR_0_RX_RATE_SENSE_L_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define UART_ASR_0_RX_RATE_SENSE_L_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define UART_ASR_0_RX_RATE_SENSE_L_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARUART_REGS(_op_) \
+_op_(UART_THR_DLAB_0_0) \
+_op_(UART_IER_DLAB_0_0) \
+_op_(UART_IIR_FCR_0) \
+_op_(UART_LCR_0) \
+_op_(UART_MCR_0) \
+_op_(UART_LSR_0) \
+_op_(UART_MSR_0) \
+_op_(UART_SPR_0) \
+_op_(UART_IRDA_CSR_0) \
+_op_(UART_RX_FIFO_CFG_0) \
+_op_(UART_MIE_0) \
+_op_(UART_VENDOR_STATUS_0_0) \
+_op_(UART_ASR_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_UART       0x00000000
+
+//
+// ARUART REGISTER BANKS
+//
+
+#define UART0_FIRST_REG 0x0000 // UART_THR_DLAB_0_0
+#define UART0_LAST_REG 0x002c // UART_VENDOR_STATUS_0_0
+#define UART1_FIRST_REG 0x003c // UART_ASR_0
+#define UART1_LAST_REG 0x003c // UART_ASR_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARUART_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arwake.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arwake.h
new file mode 100644
index 0000000..25bae48
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/arwake.h
@@ -0,0 +1,19300 @@
+//
+// Copyright (c) 2021 NVIDIA Corporation.
+// All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// Neither the name of the NVIDIA Corporation nor the names of its contributors
+// may be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+
+//
+// DO NOT EDIT - generated by simspec!
+//
+
+#ifndef ARWAKE_H_INC
+#define ARWAKE_H_INC
+#define NV_MOBILE_ARWAKE_H_UNIT_OF_OFFSET 1B
+
+#define NV_MOBILE_ARWAKE_H_SCRREG_NOMENCLATURE INFERRED
+
+
+// Register WAKE_AOWAKE_CNTRL_0
+#define WAKE_AOWAKE_CNTRL_0                     MK_ADDR_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_SECURE                      0x0
+#define WAKE_AOWAKE_CNTRL_0_DUAL                        0x0
+#define WAKE_AOWAKE_CNTRL_0_SCR                         EVENT_CNTRL_SCR_0
+#define WAKE_AOWAKE_CNTRL_0_SCRREG                      WAKE_SCR_EVENT_CNTRL_SCR_0
+#define WAKE_AOWAKE_CNTRL_0_WORD_COUNT                  0x1
+#define WAKE_AOWAKE_CNTRL_0_RESET_VAL                   MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_0_RESET_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_READ_MASK                   MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_0_WRITE_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_VAL_SHIFT                  MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_VAL_FIELD                  MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_0_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_VAL_RANGE                  15:8
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_VAL_MSB                    MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_VAL_LSB                    MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_VAL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_VAL_DEFAULT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_0_COAL_EN_SHIFT                       MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_0_COAL_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_0_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_0_COAL_EN_RANGE                       6:6
+#define WAKE_AOWAKE_CNTRL_0_COAL_EN_MSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_0_COAL_EN_LSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_0_COAL_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_0_COAL_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_COAL_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_0_COAL_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_COAL_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_COAL_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_COAL_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_0_COAL_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_0_COAL_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_0_COAL_EN_TRUE                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_0_COAL_GRP_SEL_SHIFT                  MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_0_COAL_GRP_SEL_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_0_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_0_COAL_GRP_SEL_RANGE                  5:5
+#define WAKE_AOWAKE_CNTRL_0_COAL_GRP_SEL_MSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_0_COAL_GRP_SEL_LSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_0_COAL_GRP_SEL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_0_COAL_GRP_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_COAL_GRP_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_0_COAL_GRP_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_COAL_GRP_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_COAL_GRP_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_COAL_GRP_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_0_COAL_GRP_SEL_INIT_ENUM                      GROUP0
+#define WAKE_AOWAKE_CNTRL_0_COAL_GRP_SEL_GROUP0                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_0_COAL_GRP_SEL_GROUP1                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_0_LEVEL_SHIFT                 MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_0_LEVEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_0_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_0_LEVEL_RANGE                 3:3
+#define WAKE_AOWAKE_CNTRL_0_LEVEL_MSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_0_LEVEL_LSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_0_LEVEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_0_LEVEL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_0_LEVEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_0_LEVEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_LEVEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_LEVEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_LEVEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_0_LEVEL_INIT_ENUM                     HIGH
+#define WAKE_AOWAKE_CNTRL_0_LEVEL_LOW                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_0_LEVEL_HIGH                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_EN_SHIFT                   MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_EN_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_0_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_EN_RANGE                   2:2
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_EN_MSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_EN_LSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_EN_WOFFSET                 0x0
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_EN_INIT_ENUM                       FALSE
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_EN_FALSE                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_0_DEBOUNCE_EN_TRUE                    MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_0_SR_CAPTURE_EN_SHIFT                 MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_0_SR_CAPTURE_EN_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_0_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_0_SR_CAPTURE_EN_RANGE                 1:1
+#define WAKE_AOWAKE_CNTRL_0_SR_CAPTURE_EN_MSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_0_SR_CAPTURE_EN_LSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_0_SR_CAPTURE_EN_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_0_SR_CAPTURE_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_SR_CAPTURE_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_0_SR_CAPTURE_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_SR_CAPTURE_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_SR_CAPTURE_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_SR_CAPTURE_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_0_SR_CAPTURE_EN_INIT_ENUM                     FALSE
+#define WAKE_AOWAKE_CNTRL_0_SR_CAPTURE_EN_FALSE                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_0_SR_CAPTURE_EN_TRUE                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_0_DELAY_FILTER_EN_SHIFT                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_0_DELAY_FILTER_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_0_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_0_DELAY_FILTER_EN_RANGE                       0:0
+#define WAKE_AOWAKE_CNTRL_0_DELAY_FILTER_EN_MSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_0_DELAY_FILTER_EN_LSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_0_DELAY_FILTER_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_0_DELAY_FILTER_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_DELAY_FILTER_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_0_DELAY_FILTER_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_DELAY_FILTER_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_DELAY_FILTER_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_0_DELAY_FILTER_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_0_DELAY_FILTER_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_0_DELAY_FILTER_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_0_DELAY_FILTER_EN_TRUE                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL
+#define WAKE_AOWAKE_CNTRL                       MK_ADDR_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_SECURE                        0x0
+#define WAKE_AOWAKE_CNTRL_DUAL                  0x0
+#define WAKE_AOWAKE_CNTRL_SCR                   EVENT_CNTRL_SCR_0
+#define WAKE_AOWAKE_CNTRL_SCRREG                        WAKE_SCR_EVENT_CNTRL_SCR_0
+#define WAKE_AOWAKE_CNTRL_WORD_COUNT                    0x1
+#define WAKE_AOWAKE_CNTRL_RESET_VAL                     MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_RESET_MASK                    MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_READ_MASK                     MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_WRITE_MASK                    MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_VAL_SHIFT                    MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_VAL_FIELD                    MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_VAL_RANGE                    15:8
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_VAL_MSB                      MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_VAL_LSB                      MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_VAL_WOFFSET                  0x0
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_VAL_DEFAULT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_VAL_DEFAULT_MASK                     MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_VAL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_VAL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_VAL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_VAL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_COAL_EN_SHIFT                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_COAL_EN_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_COAL_EN_RANGE                 6:6
+#define WAKE_AOWAKE_CNTRL_COAL_EN_MSB                   MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_COAL_EN_LSB                   MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_COAL_EN_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_COAL_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_COAL_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_COAL_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_COAL_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_COAL_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_COAL_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_COAL_EN_INIT_ENUM                     FALSE
+#define WAKE_AOWAKE_CNTRL_COAL_EN_FALSE                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_COAL_EN_TRUE                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_COAL_GRP_SEL_SHIFT                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_COAL_GRP_SEL_FIELD                    MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_COAL_GRP_SEL_RANGE                    5:5
+#define WAKE_AOWAKE_CNTRL_COAL_GRP_SEL_MSB                      MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_COAL_GRP_SEL_LSB                      MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_COAL_GRP_SEL_WOFFSET                  0x0
+#define WAKE_AOWAKE_CNTRL_COAL_GRP_SEL_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_COAL_GRP_SEL_DEFAULT_MASK                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_COAL_GRP_SEL_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_COAL_GRP_SEL_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_COAL_GRP_SEL_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_COAL_GRP_SEL_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_COAL_GRP_SEL_INIT_ENUM                        GROUP0
+#define WAKE_AOWAKE_CNTRL_COAL_GRP_SEL_GROUP0                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_COAL_GRP_SEL_GROUP1                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_LEVEL_SHIFT                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_LEVEL_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_LEVEL_RANGE                   3:3
+#define WAKE_AOWAKE_CNTRL_LEVEL_MSB                     MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_LEVEL_LSB                     MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_LEVEL_WOFFSET                 0x0
+#define WAKE_AOWAKE_CNTRL_LEVEL_DEFAULT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_LEVEL_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_LEVEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_LEVEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_LEVEL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_LEVEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_LEVEL_INIT_ENUM                       HIGH
+#define WAKE_AOWAKE_CNTRL_LEVEL_LOW                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_LEVEL_HIGH                    MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_EN_SHIFT                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_EN_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_EN_RANGE                     2:2
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_EN_MSB                       MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_EN_LSB                       MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_EN_WOFFSET                   0x0
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_EN_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_EN_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_EN_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_EN_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_EN_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_EN_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_EN_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_EN_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_DEBOUNCE_EN_TRUE                      MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN_SHIFT                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN_RANGE                   1:1
+#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN_MSB                     MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN_LSB                     MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN_WOFFSET                 0x0
+#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN_INIT_ENUM                       FALSE
+#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN_FALSE                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_SR_CAPTURE_EN_TRUE                    MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_DELAY_FILTER_EN_SHIFT                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_DELAY_FILTER_EN_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_DELAY_FILTER_EN_RANGE                 0:0
+#define WAKE_AOWAKE_CNTRL_DELAY_FILTER_EN_MSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_DELAY_FILTER_EN_LSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_DELAY_FILTER_EN_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_DELAY_FILTER_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_DELAY_FILTER_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_DELAY_FILTER_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_DELAY_FILTER_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_DELAY_FILTER_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_DELAY_FILTER_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_DELAY_FILTER_EN_INIT_ENUM                     FALSE
+#define WAKE_AOWAKE_CNTRL_DELAY_FILTER_EN_FALSE                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_DELAY_FILTER_EN_TRUE                  MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_1
+#define WAKE_AOWAKE_CNTRL_1                     MK_ADDR_CONST(0x4)
+#define WAKE_AOWAKE_CNTRL_1_SECURE                      0x0
+#define WAKE_AOWAKE_CNTRL_1_DUAL                        0x0
+#define WAKE_AOWAKE_CNTRL_1_SCR                         EVENT_CNTRL_SCR_1
+#define WAKE_AOWAKE_CNTRL_1_SCRREG                      WAKE_SCR_EVENT_CNTRL_SCR_1
+#define WAKE_AOWAKE_CNTRL_1_WORD_COUNT                  0x1
+#define WAKE_AOWAKE_CNTRL_1_RESET_VAL                   MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_1_RESET_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_1_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_READ_MASK                   MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_1_WRITE_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_VAL_SHIFT                  MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_VAL_FIELD                  MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_1_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_VAL_RANGE                  15:8
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_VAL_MSB                    MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_VAL_LSB                    MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_VAL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_VAL_DEFAULT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_1_COAL_EN_SHIFT                       MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_1_COAL_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_1_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_1_COAL_EN_RANGE                       6:6
+#define WAKE_AOWAKE_CNTRL_1_COAL_EN_MSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_1_COAL_EN_LSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_1_COAL_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_1_COAL_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_COAL_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_1_COAL_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_COAL_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_COAL_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_COAL_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_1_COAL_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_1_COAL_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_1_COAL_EN_TRUE                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_1_COAL_GRP_SEL_SHIFT                  MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_1_COAL_GRP_SEL_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_1_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_1_COAL_GRP_SEL_RANGE                  5:5
+#define WAKE_AOWAKE_CNTRL_1_COAL_GRP_SEL_MSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_1_COAL_GRP_SEL_LSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_1_COAL_GRP_SEL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_1_COAL_GRP_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_COAL_GRP_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_1_COAL_GRP_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_COAL_GRP_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_COAL_GRP_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_COAL_GRP_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_1_COAL_GRP_SEL_INIT_ENUM                      GROUP0
+#define WAKE_AOWAKE_CNTRL_1_COAL_GRP_SEL_GROUP0                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_1_COAL_GRP_SEL_GROUP1                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_1_LEVEL_SHIFT                 MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_1_LEVEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_1_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_1_LEVEL_RANGE                 3:3
+#define WAKE_AOWAKE_CNTRL_1_LEVEL_MSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_1_LEVEL_LSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_1_LEVEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_1_LEVEL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_1_LEVEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_1_LEVEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_LEVEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_LEVEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_LEVEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_1_LEVEL_INIT_ENUM                     HIGH
+#define WAKE_AOWAKE_CNTRL_1_LEVEL_LOW                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_1_LEVEL_HIGH                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_EN_SHIFT                   MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_EN_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_1_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_EN_RANGE                   2:2
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_EN_MSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_EN_LSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_EN_WOFFSET                 0x0
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_EN_INIT_ENUM                       FALSE
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_EN_FALSE                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_1_DEBOUNCE_EN_TRUE                    MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_1_SR_CAPTURE_EN_SHIFT                 MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_1_SR_CAPTURE_EN_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_1_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_1_SR_CAPTURE_EN_RANGE                 1:1
+#define WAKE_AOWAKE_CNTRL_1_SR_CAPTURE_EN_MSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_1_SR_CAPTURE_EN_LSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_1_SR_CAPTURE_EN_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_1_SR_CAPTURE_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_SR_CAPTURE_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_1_SR_CAPTURE_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_SR_CAPTURE_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_SR_CAPTURE_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_SR_CAPTURE_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_1_SR_CAPTURE_EN_INIT_ENUM                     FALSE
+#define WAKE_AOWAKE_CNTRL_1_SR_CAPTURE_EN_FALSE                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_1_SR_CAPTURE_EN_TRUE                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_1_DELAY_FILTER_EN_SHIFT                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_1_DELAY_FILTER_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_1_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_1_DELAY_FILTER_EN_RANGE                       0:0
+#define WAKE_AOWAKE_CNTRL_1_DELAY_FILTER_EN_MSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_1_DELAY_FILTER_EN_LSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_1_DELAY_FILTER_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_1_DELAY_FILTER_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_DELAY_FILTER_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_1_DELAY_FILTER_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_DELAY_FILTER_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_DELAY_FILTER_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_1_DELAY_FILTER_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_1_DELAY_FILTER_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_1_DELAY_FILTER_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_1_DELAY_FILTER_EN_TRUE                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_2
+#define WAKE_AOWAKE_CNTRL_2                     MK_ADDR_CONST(0x8)
+#define WAKE_AOWAKE_CNTRL_2_SECURE                      0x0
+#define WAKE_AOWAKE_CNTRL_2_DUAL                        0x0
+#define WAKE_AOWAKE_CNTRL_2_SCR                         EVENT_CNTRL_SCR_2
+#define WAKE_AOWAKE_CNTRL_2_SCRREG                      WAKE_SCR_EVENT_CNTRL_SCR_2
+#define WAKE_AOWAKE_CNTRL_2_WORD_COUNT                  0x1
+#define WAKE_AOWAKE_CNTRL_2_RESET_VAL                   MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_2_RESET_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_2_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_READ_MASK                   MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_2_WRITE_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_VAL_SHIFT                  MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_VAL_FIELD                  MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_2_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_VAL_RANGE                  15:8
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_VAL_MSB                    MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_VAL_LSB                    MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_VAL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_VAL_DEFAULT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_2_COAL_EN_SHIFT                       MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_2_COAL_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_2_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_2_COAL_EN_RANGE                       6:6
+#define WAKE_AOWAKE_CNTRL_2_COAL_EN_MSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_2_COAL_EN_LSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_2_COAL_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_2_COAL_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_COAL_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_2_COAL_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_COAL_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_COAL_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_COAL_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_2_COAL_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_2_COAL_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_2_COAL_EN_TRUE                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_2_COAL_GRP_SEL_SHIFT                  MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_2_COAL_GRP_SEL_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_2_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_2_COAL_GRP_SEL_RANGE                  5:5
+#define WAKE_AOWAKE_CNTRL_2_COAL_GRP_SEL_MSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_2_COAL_GRP_SEL_LSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_2_COAL_GRP_SEL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_2_COAL_GRP_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_COAL_GRP_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_2_COAL_GRP_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_COAL_GRP_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_COAL_GRP_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_COAL_GRP_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_2_COAL_GRP_SEL_INIT_ENUM                      GROUP0
+#define WAKE_AOWAKE_CNTRL_2_COAL_GRP_SEL_GROUP0                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_2_COAL_GRP_SEL_GROUP1                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_2_LEVEL_SHIFT                 MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_2_LEVEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_2_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_2_LEVEL_RANGE                 3:3
+#define WAKE_AOWAKE_CNTRL_2_LEVEL_MSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_2_LEVEL_LSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_2_LEVEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_2_LEVEL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_2_LEVEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_2_LEVEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_LEVEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_LEVEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_LEVEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_2_LEVEL_INIT_ENUM                     HIGH
+#define WAKE_AOWAKE_CNTRL_2_LEVEL_LOW                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_2_LEVEL_HIGH                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_EN_SHIFT                   MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_EN_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_2_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_EN_RANGE                   2:2
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_EN_MSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_EN_LSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_EN_WOFFSET                 0x0
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_EN_INIT_ENUM                       FALSE
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_EN_FALSE                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_2_DEBOUNCE_EN_TRUE                    MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_2_SR_CAPTURE_EN_SHIFT                 MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_2_SR_CAPTURE_EN_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_2_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_2_SR_CAPTURE_EN_RANGE                 1:1
+#define WAKE_AOWAKE_CNTRL_2_SR_CAPTURE_EN_MSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_2_SR_CAPTURE_EN_LSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_2_SR_CAPTURE_EN_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_2_SR_CAPTURE_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_SR_CAPTURE_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_2_SR_CAPTURE_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_SR_CAPTURE_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_SR_CAPTURE_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_SR_CAPTURE_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_2_SR_CAPTURE_EN_INIT_ENUM                     FALSE
+#define WAKE_AOWAKE_CNTRL_2_SR_CAPTURE_EN_FALSE                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_2_SR_CAPTURE_EN_TRUE                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_2_DELAY_FILTER_EN_SHIFT                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_2_DELAY_FILTER_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_2_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_2_DELAY_FILTER_EN_RANGE                       0:0
+#define WAKE_AOWAKE_CNTRL_2_DELAY_FILTER_EN_MSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_2_DELAY_FILTER_EN_LSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_2_DELAY_FILTER_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_2_DELAY_FILTER_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_DELAY_FILTER_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_2_DELAY_FILTER_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_DELAY_FILTER_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_DELAY_FILTER_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_2_DELAY_FILTER_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_2_DELAY_FILTER_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_2_DELAY_FILTER_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_2_DELAY_FILTER_EN_TRUE                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_3
+#define WAKE_AOWAKE_CNTRL_3                     MK_ADDR_CONST(0xc)
+#define WAKE_AOWAKE_CNTRL_3_SECURE                      0x0
+#define WAKE_AOWAKE_CNTRL_3_DUAL                        0x0
+#define WAKE_AOWAKE_CNTRL_3_SCR                         EVENT_CNTRL_SCR_3
+#define WAKE_AOWAKE_CNTRL_3_SCRREG                      WAKE_SCR_EVENT_CNTRL_SCR_3
+#define WAKE_AOWAKE_CNTRL_3_WORD_COUNT                  0x1
+#define WAKE_AOWAKE_CNTRL_3_RESET_VAL                   MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_3_RESET_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_3_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_READ_MASK                   MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_3_WRITE_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_VAL_SHIFT                  MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_VAL_FIELD                  MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_3_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_VAL_RANGE                  15:8
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_VAL_MSB                    MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_VAL_LSB                    MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_VAL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_VAL_DEFAULT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_3_COAL_EN_SHIFT                       MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_3_COAL_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_3_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_3_COAL_EN_RANGE                       6:6
+#define WAKE_AOWAKE_CNTRL_3_COAL_EN_MSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_3_COAL_EN_LSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_3_COAL_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_3_COAL_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_COAL_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_3_COAL_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_COAL_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_COAL_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_COAL_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_3_COAL_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_3_COAL_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_3_COAL_EN_TRUE                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_3_COAL_GRP_SEL_SHIFT                  MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_3_COAL_GRP_SEL_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_3_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_3_COAL_GRP_SEL_RANGE                  5:5
+#define WAKE_AOWAKE_CNTRL_3_COAL_GRP_SEL_MSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_3_COAL_GRP_SEL_LSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_3_COAL_GRP_SEL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_3_COAL_GRP_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_COAL_GRP_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_3_COAL_GRP_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_COAL_GRP_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_COAL_GRP_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_COAL_GRP_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_3_COAL_GRP_SEL_INIT_ENUM                      GROUP0
+#define WAKE_AOWAKE_CNTRL_3_COAL_GRP_SEL_GROUP0                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_3_COAL_GRP_SEL_GROUP1                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_3_LEVEL_SHIFT                 MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_3_LEVEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_3_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_3_LEVEL_RANGE                 3:3
+#define WAKE_AOWAKE_CNTRL_3_LEVEL_MSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_3_LEVEL_LSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_3_LEVEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_3_LEVEL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_3_LEVEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_3_LEVEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_LEVEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_LEVEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_LEVEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_3_LEVEL_INIT_ENUM                     HIGH
+#define WAKE_AOWAKE_CNTRL_3_LEVEL_LOW                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_3_LEVEL_HIGH                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_EN_SHIFT                   MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_EN_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_3_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_EN_RANGE                   2:2
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_EN_MSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_EN_LSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_EN_WOFFSET                 0x0
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_EN_INIT_ENUM                       FALSE
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_EN_FALSE                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_3_DEBOUNCE_EN_TRUE                    MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_3_SR_CAPTURE_EN_SHIFT                 MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_3_SR_CAPTURE_EN_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_3_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_3_SR_CAPTURE_EN_RANGE                 1:1
+#define WAKE_AOWAKE_CNTRL_3_SR_CAPTURE_EN_MSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_3_SR_CAPTURE_EN_LSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_3_SR_CAPTURE_EN_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_3_SR_CAPTURE_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_SR_CAPTURE_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_3_SR_CAPTURE_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_SR_CAPTURE_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_SR_CAPTURE_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_SR_CAPTURE_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_3_SR_CAPTURE_EN_INIT_ENUM                     FALSE
+#define WAKE_AOWAKE_CNTRL_3_SR_CAPTURE_EN_FALSE                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_3_SR_CAPTURE_EN_TRUE                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_3_DELAY_FILTER_EN_SHIFT                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_3_DELAY_FILTER_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_3_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_3_DELAY_FILTER_EN_RANGE                       0:0
+#define WAKE_AOWAKE_CNTRL_3_DELAY_FILTER_EN_MSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_3_DELAY_FILTER_EN_LSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_3_DELAY_FILTER_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_3_DELAY_FILTER_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_DELAY_FILTER_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_3_DELAY_FILTER_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_DELAY_FILTER_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_DELAY_FILTER_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_3_DELAY_FILTER_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_3_DELAY_FILTER_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_3_DELAY_FILTER_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_3_DELAY_FILTER_EN_TRUE                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_4
+#define WAKE_AOWAKE_CNTRL_4                     MK_ADDR_CONST(0x10)
+#define WAKE_AOWAKE_CNTRL_4_SECURE                      0x0
+#define WAKE_AOWAKE_CNTRL_4_DUAL                        0x0
+#define WAKE_AOWAKE_CNTRL_4_SCR                         EVENT_CNTRL_SCR_4
+#define WAKE_AOWAKE_CNTRL_4_SCRREG                      WAKE_SCR_EVENT_CNTRL_SCR_4
+#define WAKE_AOWAKE_CNTRL_4_WORD_COUNT                  0x1
+#define WAKE_AOWAKE_CNTRL_4_RESET_VAL                   MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_4_RESET_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_4_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_READ_MASK                   MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_4_WRITE_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_VAL_SHIFT                  MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_VAL_FIELD                  MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_4_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_VAL_RANGE                  15:8
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_VAL_MSB                    MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_VAL_LSB                    MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_VAL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_VAL_DEFAULT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_4_COAL_EN_SHIFT                       MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_4_COAL_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_4_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_4_COAL_EN_RANGE                       6:6
+#define WAKE_AOWAKE_CNTRL_4_COAL_EN_MSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_4_COAL_EN_LSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_4_COAL_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_4_COAL_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_COAL_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_4_COAL_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_COAL_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_COAL_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_COAL_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_4_COAL_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_4_COAL_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_4_COAL_EN_TRUE                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_4_COAL_GRP_SEL_SHIFT                  MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_4_COAL_GRP_SEL_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_4_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_4_COAL_GRP_SEL_RANGE                  5:5
+#define WAKE_AOWAKE_CNTRL_4_COAL_GRP_SEL_MSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_4_COAL_GRP_SEL_LSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_4_COAL_GRP_SEL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_4_COAL_GRP_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_COAL_GRP_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_4_COAL_GRP_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_COAL_GRP_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_COAL_GRP_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_COAL_GRP_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_4_COAL_GRP_SEL_INIT_ENUM                      GROUP0
+#define WAKE_AOWAKE_CNTRL_4_COAL_GRP_SEL_GROUP0                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_4_COAL_GRP_SEL_GROUP1                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_4_LEVEL_SHIFT                 MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_4_LEVEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_4_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_4_LEVEL_RANGE                 3:3
+#define WAKE_AOWAKE_CNTRL_4_LEVEL_MSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_4_LEVEL_LSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_4_LEVEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_4_LEVEL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_4_LEVEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_4_LEVEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_LEVEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_LEVEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_LEVEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_4_LEVEL_INIT_ENUM                     HIGH
+#define WAKE_AOWAKE_CNTRL_4_LEVEL_LOW                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_4_LEVEL_HIGH                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_EN_SHIFT                   MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_EN_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_4_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_EN_RANGE                   2:2
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_EN_MSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_EN_LSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_EN_WOFFSET                 0x0
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_EN_INIT_ENUM                       FALSE
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_EN_FALSE                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_4_DEBOUNCE_EN_TRUE                    MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_4_SR_CAPTURE_EN_SHIFT                 MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_4_SR_CAPTURE_EN_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_4_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_4_SR_CAPTURE_EN_RANGE                 1:1
+#define WAKE_AOWAKE_CNTRL_4_SR_CAPTURE_EN_MSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_4_SR_CAPTURE_EN_LSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_4_SR_CAPTURE_EN_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_4_SR_CAPTURE_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_SR_CAPTURE_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_4_SR_CAPTURE_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_SR_CAPTURE_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_SR_CAPTURE_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_SR_CAPTURE_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_4_SR_CAPTURE_EN_INIT_ENUM                     FALSE
+#define WAKE_AOWAKE_CNTRL_4_SR_CAPTURE_EN_FALSE                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_4_SR_CAPTURE_EN_TRUE                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_4_DELAY_FILTER_EN_SHIFT                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_4_DELAY_FILTER_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_4_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_4_DELAY_FILTER_EN_RANGE                       0:0
+#define WAKE_AOWAKE_CNTRL_4_DELAY_FILTER_EN_MSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_4_DELAY_FILTER_EN_LSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_4_DELAY_FILTER_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_4_DELAY_FILTER_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_DELAY_FILTER_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_4_DELAY_FILTER_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_DELAY_FILTER_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_DELAY_FILTER_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_4_DELAY_FILTER_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_4_DELAY_FILTER_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_4_DELAY_FILTER_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_4_DELAY_FILTER_EN_TRUE                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_5
+#define WAKE_AOWAKE_CNTRL_5                     MK_ADDR_CONST(0x14)
+#define WAKE_AOWAKE_CNTRL_5_SECURE                      0x0
+#define WAKE_AOWAKE_CNTRL_5_DUAL                        0x0
+#define WAKE_AOWAKE_CNTRL_5_SCR                         EVENT_CNTRL_SCR_5
+#define WAKE_AOWAKE_CNTRL_5_SCRREG                      WAKE_SCR_EVENT_CNTRL_SCR_5
+#define WAKE_AOWAKE_CNTRL_5_WORD_COUNT                  0x1
+#define WAKE_AOWAKE_CNTRL_5_RESET_VAL                   MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_5_RESET_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_5_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_READ_MASK                   MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_5_WRITE_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_VAL_SHIFT                  MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_VAL_FIELD                  MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_5_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_VAL_RANGE                  15:8
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_VAL_MSB                    MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_VAL_LSB                    MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_VAL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_VAL_DEFAULT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_5_COAL_EN_SHIFT                       MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_5_COAL_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_5_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_5_COAL_EN_RANGE                       6:6
+#define WAKE_AOWAKE_CNTRL_5_COAL_EN_MSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_5_COAL_EN_LSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_5_COAL_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_5_COAL_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_COAL_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_5_COAL_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_COAL_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_COAL_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_COAL_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_5_COAL_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_5_COAL_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_5_COAL_EN_TRUE                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_5_COAL_GRP_SEL_SHIFT                  MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_5_COAL_GRP_SEL_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_5_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_5_COAL_GRP_SEL_RANGE                  5:5
+#define WAKE_AOWAKE_CNTRL_5_COAL_GRP_SEL_MSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_5_COAL_GRP_SEL_LSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_5_COAL_GRP_SEL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_5_COAL_GRP_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_COAL_GRP_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_5_COAL_GRP_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_COAL_GRP_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_COAL_GRP_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_COAL_GRP_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_5_COAL_GRP_SEL_INIT_ENUM                      GROUP0
+#define WAKE_AOWAKE_CNTRL_5_COAL_GRP_SEL_GROUP0                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_5_COAL_GRP_SEL_GROUP1                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_5_LEVEL_SHIFT                 MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_5_LEVEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_5_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_5_LEVEL_RANGE                 3:3
+#define WAKE_AOWAKE_CNTRL_5_LEVEL_MSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_5_LEVEL_LSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_5_LEVEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_5_LEVEL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_5_LEVEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_5_LEVEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_LEVEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_LEVEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_LEVEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_5_LEVEL_INIT_ENUM                     HIGH
+#define WAKE_AOWAKE_CNTRL_5_LEVEL_LOW                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_5_LEVEL_HIGH                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_EN_SHIFT                   MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_EN_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_5_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_EN_RANGE                   2:2
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_EN_MSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_EN_LSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_EN_WOFFSET                 0x0
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_EN_INIT_ENUM                       FALSE
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_EN_FALSE                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_5_DEBOUNCE_EN_TRUE                    MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_5_SR_CAPTURE_EN_SHIFT                 MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_5_SR_CAPTURE_EN_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_5_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_5_SR_CAPTURE_EN_RANGE                 1:1
+#define WAKE_AOWAKE_CNTRL_5_SR_CAPTURE_EN_MSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_5_SR_CAPTURE_EN_LSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_5_SR_CAPTURE_EN_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_5_SR_CAPTURE_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_SR_CAPTURE_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_5_SR_CAPTURE_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_SR_CAPTURE_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_SR_CAPTURE_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_SR_CAPTURE_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_5_SR_CAPTURE_EN_INIT_ENUM                     FALSE
+#define WAKE_AOWAKE_CNTRL_5_SR_CAPTURE_EN_FALSE                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_5_SR_CAPTURE_EN_TRUE                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_5_DELAY_FILTER_EN_SHIFT                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_5_DELAY_FILTER_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_5_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_5_DELAY_FILTER_EN_RANGE                       0:0
+#define WAKE_AOWAKE_CNTRL_5_DELAY_FILTER_EN_MSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_5_DELAY_FILTER_EN_LSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_5_DELAY_FILTER_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_5_DELAY_FILTER_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_DELAY_FILTER_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_5_DELAY_FILTER_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_DELAY_FILTER_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_DELAY_FILTER_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_5_DELAY_FILTER_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_5_DELAY_FILTER_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_5_DELAY_FILTER_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_5_DELAY_FILTER_EN_TRUE                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_6
+#define WAKE_AOWAKE_CNTRL_6                     MK_ADDR_CONST(0x18)
+#define WAKE_AOWAKE_CNTRL_6_SECURE                      0x0
+#define WAKE_AOWAKE_CNTRL_6_DUAL                        0x0
+#define WAKE_AOWAKE_CNTRL_6_SCR                         EVENT_CNTRL_SCR_6
+#define WAKE_AOWAKE_CNTRL_6_SCRREG                      WAKE_SCR_EVENT_CNTRL_SCR_6
+#define WAKE_AOWAKE_CNTRL_6_WORD_COUNT                  0x1
+#define WAKE_AOWAKE_CNTRL_6_RESET_VAL                   MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_6_RESET_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_6_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_READ_MASK                   MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_6_WRITE_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_VAL_SHIFT                  MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_VAL_FIELD                  MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_6_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_VAL_RANGE                  15:8
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_VAL_MSB                    MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_VAL_LSB                    MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_VAL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_VAL_DEFAULT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_6_COAL_EN_SHIFT                       MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_6_COAL_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_6_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_6_COAL_EN_RANGE                       6:6
+#define WAKE_AOWAKE_CNTRL_6_COAL_EN_MSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_6_COAL_EN_LSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_6_COAL_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_6_COAL_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_COAL_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_6_COAL_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_COAL_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_COAL_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_COAL_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_6_COAL_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_6_COAL_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_6_COAL_EN_TRUE                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_6_COAL_GRP_SEL_SHIFT                  MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_6_COAL_GRP_SEL_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_6_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_6_COAL_GRP_SEL_RANGE                  5:5
+#define WAKE_AOWAKE_CNTRL_6_COAL_GRP_SEL_MSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_6_COAL_GRP_SEL_LSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_6_COAL_GRP_SEL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_6_COAL_GRP_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_COAL_GRP_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_6_COAL_GRP_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_COAL_GRP_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_COAL_GRP_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_COAL_GRP_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_6_COAL_GRP_SEL_INIT_ENUM                      GROUP0
+#define WAKE_AOWAKE_CNTRL_6_COAL_GRP_SEL_GROUP0                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_6_COAL_GRP_SEL_GROUP1                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_6_LEVEL_SHIFT                 MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_6_LEVEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_6_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_6_LEVEL_RANGE                 3:3
+#define WAKE_AOWAKE_CNTRL_6_LEVEL_MSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_6_LEVEL_LSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_6_LEVEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_6_LEVEL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_6_LEVEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_6_LEVEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_LEVEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_LEVEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_LEVEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_6_LEVEL_INIT_ENUM                     HIGH
+#define WAKE_AOWAKE_CNTRL_6_LEVEL_LOW                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_6_LEVEL_HIGH                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_EN_SHIFT                   MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_EN_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_6_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_EN_RANGE                   2:2
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_EN_MSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_EN_LSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_EN_WOFFSET                 0x0
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_EN_INIT_ENUM                       FALSE
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_EN_FALSE                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_6_DEBOUNCE_EN_TRUE                    MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_6_SR_CAPTURE_EN_SHIFT                 MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_6_SR_CAPTURE_EN_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_6_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_6_SR_CAPTURE_EN_RANGE                 1:1
+#define WAKE_AOWAKE_CNTRL_6_SR_CAPTURE_EN_MSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_6_SR_CAPTURE_EN_LSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_6_SR_CAPTURE_EN_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_6_SR_CAPTURE_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_SR_CAPTURE_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_6_SR_CAPTURE_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_SR_CAPTURE_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_SR_CAPTURE_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_SR_CAPTURE_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_6_SR_CAPTURE_EN_INIT_ENUM                     FALSE
+#define WAKE_AOWAKE_CNTRL_6_SR_CAPTURE_EN_FALSE                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_6_SR_CAPTURE_EN_TRUE                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_6_DELAY_FILTER_EN_SHIFT                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_6_DELAY_FILTER_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_6_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_6_DELAY_FILTER_EN_RANGE                       0:0
+#define WAKE_AOWAKE_CNTRL_6_DELAY_FILTER_EN_MSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_6_DELAY_FILTER_EN_LSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_6_DELAY_FILTER_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_6_DELAY_FILTER_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_DELAY_FILTER_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_6_DELAY_FILTER_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_DELAY_FILTER_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_DELAY_FILTER_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_6_DELAY_FILTER_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_6_DELAY_FILTER_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_6_DELAY_FILTER_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_6_DELAY_FILTER_EN_TRUE                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_7
+#define WAKE_AOWAKE_CNTRL_7                     MK_ADDR_CONST(0x1c)
+#define WAKE_AOWAKE_CNTRL_7_SECURE                      0x0
+#define WAKE_AOWAKE_CNTRL_7_DUAL                        0x0
+#define WAKE_AOWAKE_CNTRL_7_SCR                         EVENT_CNTRL_SCR_7
+#define WAKE_AOWAKE_CNTRL_7_SCRREG                      WAKE_SCR_EVENT_CNTRL_SCR_7
+#define WAKE_AOWAKE_CNTRL_7_WORD_COUNT                  0x1
+#define WAKE_AOWAKE_CNTRL_7_RESET_VAL                   MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_7_RESET_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_7_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_READ_MASK                   MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_7_WRITE_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_VAL_SHIFT                  MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_VAL_FIELD                  MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_7_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_VAL_RANGE                  15:8
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_VAL_MSB                    MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_VAL_LSB                    MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_VAL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_VAL_DEFAULT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_7_COAL_EN_SHIFT                       MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_7_COAL_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_7_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_7_COAL_EN_RANGE                       6:6
+#define WAKE_AOWAKE_CNTRL_7_COAL_EN_MSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_7_COAL_EN_LSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_7_COAL_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_7_COAL_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_COAL_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_7_COAL_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_COAL_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_COAL_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_COAL_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_7_COAL_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_7_COAL_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_7_COAL_EN_TRUE                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_7_COAL_GRP_SEL_SHIFT                  MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_7_COAL_GRP_SEL_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_7_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_7_COAL_GRP_SEL_RANGE                  5:5
+#define WAKE_AOWAKE_CNTRL_7_COAL_GRP_SEL_MSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_7_COAL_GRP_SEL_LSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_7_COAL_GRP_SEL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_7_COAL_GRP_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_COAL_GRP_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_7_COAL_GRP_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_COAL_GRP_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_COAL_GRP_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_COAL_GRP_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_7_COAL_GRP_SEL_INIT_ENUM                      GROUP0
+#define WAKE_AOWAKE_CNTRL_7_COAL_GRP_SEL_GROUP0                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_7_COAL_GRP_SEL_GROUP1                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_7_LEVEL_SHIFT                 MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_7_LEVEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_7_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_7_LEVEL_RANGE                 3:3
+#define WAKE_AOWAKE_CNTRL_7_LEVEL_MSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_7_LEVEL_LSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_7_LEVEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_7_LEVEL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_7_LEVEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_7_LEVEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_LEVEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_LEVEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_LEVEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_7_LEVEL_INIT_ENUM                     HIGH
+#define WAKE_AOWAKE_CNTRL_7_LEVEL_LOW                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_7_LEVEL_HIGH                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_EN_SHIFT                   MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_EN_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_7_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_EN_RANGE                   2:2
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_EN_MSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_EN_LSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_EN_WOFFSET                 0x0
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_EN_INIT_ENUM                       FALSE
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_EN_FALSE                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_7_DEBOUNCE_EN_TRUE                    MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_7_SR_CAPTURE_EN_SHIFT                 MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_7_SR_CAPTURE_EN_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_7_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_7_SR_CAPTURE_EN_RANGE                 1:1
+#define WAKE_AOWAKE_CNTRL_7_SR_CAPTURE_EN_MSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_7_SR_CAPTURE_EN_LSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_7_SR_CAPTURE_EN_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_7_SR_CAPTURE_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_SR_CAPTURE_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_7_SR_CAPTURE_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_SR_CAPTURE_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_SR_CAPTURE_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_SR_CAPTURE_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_7_SR_CAPTURE_EN_INIT_ENUM                     FALSE
+#define WAKE_AOWAKE_CNTRL_7_SR_CAPTURE_EN_FALSE                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_7_SR_CAPTURE_EN_TRUE                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_7_DELAY_FILTER_EN_SHIFT                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_7_DELAY_FILTER_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_7_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_7_DELAY_FILTER_EN_RANGE                       0:0
+#define WAKE_AOWAKE_CNTRL_7_DELAY_FILTER_EN_MSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_7_DELAY_FILTER_EN_LSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_7_DELAY_FILTER_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_7_DELAY_FILTER_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_DELAY_FILTER_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_7_DELAY_FILTER_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_DELAY_FILTER_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_DELAY_FILTER_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_7_DELAY_FILTER_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_7_DELAY_FILTER_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_7_DELAY_FILTER_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_7_DELAY_FILTER_EN_TRUE                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_8
+#define WAKE_AOWAKE_CNTRL_8                     MK_ADDR_CONST(0x20)
+#define WAKE_AOWAKE_CNTRL_8_SECURE                      0x0
+#define WAKE_AOWAKE_CNTRL_8_DUAL                        0x0
+#define WAKE_AOWAKE_CNTRL_8_SCR                         EVENT_CNTRL_SCR_8
+#define WAKE_AOWAKE_CNTRL_8_SCRREG                      WAKE_SCR_EVENT_CNTRL_SCR_8
+#define WAKE_AOWAKE_CNTRL_8_WORD_COUNT                  0x1
+#define WAKE_AOWAKE_CNTRL_8_RESET_VAL                   MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_8_RESET_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_8_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_READ_MASK                   MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_8_WRITE_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_VAL_SHIFT                  MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_VAL_FIELD                  MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_8_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_VAL_RANGE                  15:8
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_VAL_MSB                    MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_VAL_LSB                    MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_VAL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_VAL_DEFAULT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_8_COAL_EN_SHIFT                       MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_8_COAL_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_8_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_8_COAL_EN_RANGE                       6:6
+#define WAKE_AOWAKE_CNTRL_8_COAL_EN_MSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_8_COAL_EN_LSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_8_COAL_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_8_COAL_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_COAL_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_8_COAL_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_COAL_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_COAL_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_COAL_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_8_COAL_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_8_COAL_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_8_COAL_EN_TRUE                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_8_COAL_GRP_SEL_SHIFT                  MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_8_COAL_GRP_SEL_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_8_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_8_COAL_GRP_SEL_RANGE                  5:5
+#define WAKE_AOWAKE_CNTRL_8_COAL_GRP_SEL_MSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_8_COAL_GRP_SEL_LSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_8_COAL_GRP_SEL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_8_COAL_GRP_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_COAL_GRP_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_8_COAL_GRP_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_COAL_GRP_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_COAL_GRP_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_COAL_GRP_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_8_COAL_GRP_SEL_INIT_ENUM                      GROUP0
+#define WAKE_AOWAKE_CNTRL_8_COAL_GRP_SEL_GROUP0                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_8_COAL_GRP_SEL_GROUP1                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_8_LEVEL_SHIFT                 MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_8_LEVEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_8_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_8_LEVEL_RANGE                 3:3
+#define WAKE_AOWAKE_CNTRL_8_LEVEL_MSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_8_LEVEL_LSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_8_LEVEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_8_LEVEL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_8_LEVEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_8_LEVEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_LEVEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_LEVEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_LEVEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_8_LEVEL_INIT_ENUM                     HIGH
+#define WAKE_AOWAKE_CNTRL_8_LEVEL_LOW                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_8_LEVEL_HIGH                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_EN_SHIFT                   MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_EN_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_8_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_EN_RANGE                   2:2
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_EN_MSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_EN_LSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_EN_WOFFSET                 0x0
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_EN_INIT_ENUM                       FALSE
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_EN_FALSE                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_8_DEBOUNCE_EN_TRUE                    MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_8_SR_CAPTURE_EN_SHIFT                 MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_8_SR_CAPTURE_EN_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_8_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_8_SR_CAPTURE_EN_RANGE                 1:1
+#define WAKE_AOWAKE_CNTRL_8_SR_CAPTURE_EN_MSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_8_SR_CAPTURE_EN_LSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_8_SR_CAPTURE_EN_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_8_SR_CAPTURE_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_SR_CAPTURE_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_8_SR_CAPTURE_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_SR_CAPTURE_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_SR_CAPTURE_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_SR_CAPTURE_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_8_SR_CAPTURE_EN_INIT_ENUM                     FALSE
+#define WAKE_AOWAKE_CNTRL_8_SR_CAPTURE_EN_FALSE                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_8_SR_CAPTURE_EN_TRUE                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_8_DELAY_FILTER_EN_SHIFT                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_8_DELAY_FILTER_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_8_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_8_DELAY_FILTER_EN_RANGE                       0:0
+#define WAKE_AOWAKE_CNTRL_8_DELAY_FILTER_EN_MSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_8_DELAY_FILTER_EN_LSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_8_DELAY_FILTER_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_8_DELAY_FILTER_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_DELAY_FILTER_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_8_DELAY_FILTER_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_DELAY_FILTER_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_DELAY_FILTER_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_8_DELAY_FILTER_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_8_DELAY_FILTER_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_8_DELAY_FILTER_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_8_DELAY_FILTER_EN_TRUE                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_9
+#define WAKE_AOWAKE_CNTRL_9                     MK_ADDR_CONST(0x24)
+#define WAKE_AOWAKE_CNTRL_9_SECURE                      0x0
+#define WAKE_AOWAKE_CNTRL_9_DUAL                        0x0
+#define WAKE_AOWAKE_CNTRL_9_SCR                         EVENT_CNTRL_SCR_9
+#define WAKE_AOWAKE_CNTRL_9_SCRREG                      WAKE_SCR_EVENT_CNTRL_SCR_9
+#define WAKE_AOWAKE_CNTRL_9_WORD_COUNT                  0x1
+#define WAKE_AOWAKE_CNTRL_9_RESET_VAL                   MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_9_RESET_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_9_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_READ_MASK                   MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_9_WRITE_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_VAL_SHIFT                  MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_VAL_FIELD                  MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_9_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_VAL_RANGE                  15:8
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_VAL_MSB                    MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_VAL_LSB                    MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_VAL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_VAL_DEFAULT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_VAL_DEFAULT_MASK                   MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_VAL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_VAL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_VAL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_VAL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_9_COAL_EN_SHIFT                       MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_9_COAL_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_9_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_9_COAL_EN_RANGE                       6:6
+#define WAKE_AOWAKE_CNTRL_9_COAL_EN_MSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_9_COAL_EN_LSB                 MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_9_COAL_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_9_COAL_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_COAL_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_9_COAL_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_COAL_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_COAL_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_COAL_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_9_COAL_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_9_COAL_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_9_COAL_EN_TRUE                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_9_COAL_GRP_SEL_SHIFT                  MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_9_COAL_GRP_SEL_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_9_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_9_COAL_GRP_SEL_RANGE                  5:5
+#define WAKE_AOWAKE_CNTRL_9_COAL_GRP_SEL_MSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_9_COAL_GRP_SEL_LSB                    MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_9_COAL_GRP_SEL_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_9_COAL_GRP_SEL_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_COAL_GRP_SEL_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_9_COAL_GRP_SEL_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_COAL_GRP_SEL_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_COAL_GRP_SEL_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_COAL_GRP_SEL_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_9_COAL_GRP_SEL_INIT_ENUM                      GROUP0
+#define WAKE_AOWAKE_CNTRL_9_COAL_GRP_SEL_GROUP0                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_9_COAL_GRP_SEL_GROUP1                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_9_LEVEL_SHIFT                 MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_9_LEVEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_9_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_9_LEVEL_RANGE                 3:3
+#define WAKE_AOWAKE_CNTRL_9_LEVEL_MSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_9_LEVEL_LSB                   MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_9_LEVEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_9_LEVEL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_9_LEVEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_9_LEVEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_LEVEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_LEVEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_LEVEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_9_LEVEL_INIT_ENUM                     HIGH
+#define WAKE_AOWAKE_CNTRL_9_LEVEL_LOW                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_9_LEVEL_HIGH                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_EN_SHIFT                   MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_EN_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_9_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_EN_RANGE                   2:2
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_EN_MSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_EN_LSB                     MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_EN_WOFFSET                 0x0
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_EN_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_EN_INIT_ENUM                       FALSE
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_EN_FALSE                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_9_DEBOUNCE_EN_TRUE                    MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_9_SR_CAPTURE_EN_SHIFT                 MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_9_SR_CAPTURE_EN_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_9_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_9_SR_CAPTURE_EN_RANGE                 1:1
+#define WAKE_AOWAKE_CNTRL_9_SR_CAPTURE_EN_MSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_9_SR_CAPTURE_EN_LSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_9_SR_CAPTURE_EN_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_9_SR_CAPTURE_EN_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_SR_CAPTURE_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_9_SR_CAPTURE_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_SR_CAPTURE_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_SR_CAPTURE_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_SR_CAPTURE_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_9_SR_CAPTURE_EN_INIT_ENUM                     FALSE
+#define WAKE_AOWAKE_CNTRL_9_SR_CAPTURE_EN_FALSE                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_9_SR_CAPTURE_EN_TRUE                  MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_9_DELAY_FILTER_EN_SHIFT                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_9_DELAY_FILTER_EN_FIELD                       MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_9_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_9_DELAY_FILTER_EN_RANGE                       0:0
+#define WAKE_AOWAKE_CNTRL_9_DELAY_FILTER_EN_MSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_9_DELAY_FILTER_EN_LSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_9_DELAY_FILTER_EN_WOFFSET                     0x0
+#define WAKE_AOWAKE_CNTRL_9_DELAY_FILTER_EN_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_DELAY_FILTER_EN_DEFAULT_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_9_DELAY_FILTER_EN_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_DELAY_FILTER_EN_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_DELAY_FILTER_EN_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_9_DELAY_FILTER_EN_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_9_DELAY_FILTER_EN_INIT_ENUM                   FALSE
+#define WAKE_AOWAKE_CNTRL_9_DELAY_FILTER_EN_FALSE                       MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_9_DELAY_FILTER_EN_TRUE                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_10
+#define WAKE_AOWAKE_CNTRL_10                    MK_ADDR_CONST(0x28)
+#define WAKE_AOWAKE_CNTRL_10_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_10_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_10_SCR                        EVENT_CNTRL_SCR_10
+#define WAKE_AOWAKE_CNTRL_10_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_10
+#define WAKE_AOWAKE_CNTRL_10_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_10_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_10_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_10_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_10_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_10_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_10_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_10_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_10_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_10_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_10_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_10_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_10_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_10_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_10_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_10_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_10_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_10_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_10_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_10_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_10_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_10_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_10_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_10_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_10_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_10_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_10_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_10_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_10_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_10_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_10_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_10_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_10_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_10_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_10_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_10_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_10_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_10_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_10_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_10_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_10_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_10_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_10_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_10_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_10_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_10_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_10_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_10_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_10_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_10_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_10_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_10_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_10_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_10_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_10_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_10_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_10_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_10_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_10_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_10_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_10_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_10_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_10_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_10_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_10_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_10_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_10_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_10_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_10_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_10_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_11
+#define WAKE_AOWAKE_CNTRL_11                    MK_ADDR_CONST(0x2c)
+#define WAKE_AOWAKE_CNTRL_11_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_11_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_11_SCR                        EVENT_CNTRL_SCR_11
+#define WAKE_AOWAKE_CNTRL_11_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_11
+#define WAKE_AOWAKE_CNTRL_11_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_11_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_11_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_11_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_11_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_11_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_11_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_11_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_11_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_11_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_11_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_11_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_11_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_11_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_11_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_11_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_11_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_11_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_11_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_11_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_11_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_11_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_11_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_11_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_11_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_11_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_11_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_11_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_11_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_11_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_11_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_11_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_11_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_11_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_11_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_11_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_11_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_11_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_11_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_11_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_11_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_11_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_11_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_11_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_11_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_11_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_11_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_11_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_11_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_11_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_11_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_11_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_11_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_11_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_11_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_11_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_11_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_11_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_11_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_11_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_11_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_11_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_11_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_11_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_11_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_11_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_11_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_11_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_11_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_11_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_12
+#define WAKE_AOWAKE_CNTRL_12                    MK_ADDR_CONST(0x30)
+#define WAKE_AOWAKE_CNTRL_12_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_12_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_12_SCR                        EVENT_CNTRL_SCR_12
+#define WAKE_AOWAKE_CNTRL_12_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_12
+#define WAKE_AOWAKE_CNTRL_12_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_12_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_12_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_12_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_12_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_12_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_12_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_12_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_12_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_12_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_12_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_12_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_12_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_12_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_12_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_12_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_12_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_12_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_12_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_12_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_12_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_12_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_12_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_12_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_12_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_12_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_12_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_12_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_12_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_12_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_12_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_12_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_12_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_12_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_12_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_12_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_12_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_12_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_12_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_12_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_12_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_12_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_12_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_12_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_12_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_12_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_12_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_12_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_12_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_12_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_12_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_12_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_12_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_12_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_12_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_12_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_12_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_12_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_12_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_12_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_12_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_12_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_12_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_12_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_12_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_12_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_12_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_12_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_12_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_12_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_13
+#define WAKE_AOWAKE_CNTRL_13                    MK_ADDR_CONST(0x34)
+#define WAKE_AOWAKE_CNTRL_13_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_13_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_13_SCR                        EVENT_CNTRL_SCR_13
+#define WAKE_AOWAKE_CNTRL_13_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_13
+#define WAKE_AOWAKE_CNTRL_13_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_13_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_13_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_13_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_13_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_13_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_13_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_13_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_13_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_13_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_13_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_13_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_13_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_13_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_13_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_13_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_13_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_13_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_13_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_13_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_13_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_13_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_13_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_13_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_13_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_13_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_13_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_13_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_13_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_13_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_13_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_13_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_13_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_13_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_13_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_13_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_13_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_13_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_13_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_13_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_13_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_13_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_13_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_13_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_13_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_13_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_13_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_13_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_13_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_13_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_13_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_13_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_13_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_13_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_13_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_13_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_13_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_13_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_13_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_13_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_13_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_13_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_13_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_13_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_13_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_13_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_13_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_13_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_13_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_13_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_14
+#define WAKE_AOWAKE_CNTRL_14                    MK_ADDR_CONST(0x38)
+#define WAKE_AOWAKE_CNTRL_14_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_14_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_14_SCR                        EVENT_CNTRL_SCR_14
+#define WAKE_AOWAKE_CNTRL_14_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_14
+#define WAKE_AOWAKE_CNTRL_14_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_14_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_14_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_14_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_14_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_14_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_14_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_14_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_14_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_14_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_14_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_14_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_14_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_14_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_14_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_14_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_14_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_14_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_14_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_14_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_14_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_14_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_14_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_14_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_14_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_14_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_14_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_14_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_14_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_14_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_14_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_14_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_14_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_14_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_14_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_14_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_14_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_14_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_14_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_14_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_14_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_14_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_14_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_14_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_14_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_14_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_14_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_14_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_14_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_14_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_14_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_14_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_14_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_14_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_14_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_14_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_14_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_14_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_14_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_14_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_14_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_14_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_14_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_14_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_14_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_14_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_14_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_14_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_14_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_14_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_15
+#define WAKE_AOWAKE_CNTRL_15                    MK_ADDR_CONST(0x3c)
+#define WAKE_AOWAKE_CNTRL_15_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_15_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_15_SCR                        EVENT_CNTRL_SCR_15
+#define WAKE_AOWAKE_CNTRL_15_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_15
+#define WAKE_AOWAKE_CNTRL_15_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_15_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_15_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_15_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_15_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_15_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_15_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_15_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_15_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_15_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_15_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_15_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_15_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_15_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_15_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_15_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_15_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_15_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_15_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_15_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_15_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_15_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_15_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_15_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_15_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_15_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_15_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_15_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_15_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_15_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_15_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_15_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_15_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_15_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_15_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_15_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_15_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_15_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_15_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_15_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_15_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_15_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_15_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_15_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_15_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_15_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_15_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_15_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_15_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_15_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_15_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_15_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_15_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_15_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_15_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_15_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_15_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_15_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_15_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_15_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_15_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_15_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_15_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_15_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_15_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_15_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_15_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_15_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_15_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_15_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_16
+#define WAKE_AOWAKE_CNTRL_16                    MK_ADDR_CONST(0x40)
+#define WAKE_AOWAKE_CNTRL_16_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_16_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_16_SCR                        EVENT_CNTRL_SCR_16
+#define WAKE_AOWAKE_CNTRL_16_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_16
+#define WAKE_AOWAKE_CNTRL_16_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_16_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_16_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_16_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_16_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_16_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_16_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_16_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_16_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_16_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_16_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_16_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_16_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_16_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_16_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_16_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_16_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_16_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_16_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_16_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_16_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_16_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_16_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_16_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_16_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_16_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_16_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_16_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_16_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_16_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_16_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_16_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_16_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_16_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_16_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_16_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_16_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_16_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_16_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_16_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_16_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_16_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_16_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_16_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_16_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_16_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_16_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_16_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_16_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_16_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_16_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_16_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_16_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_16_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_16_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_16_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_16_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_16_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_16_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_16_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_16_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_16_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_16_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_16_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_16_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_16_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_16_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_16_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_16_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_16_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_17
+#define WAKE_AOWAKE_CNTRL_17                    MK_ADDR_CONST(0x44)
+#define WAKE_AOWAKE_CNTRL_17_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_17_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_17_SCR                        EVENT_CNTRL_SCR_17
+#define WAKE_AOWAKE_CNTRL_17_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_17
+#define WAKE_AOWAKE_CNTRL_17_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_17_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_17_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_17_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_17_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_17_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_17_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_17_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_17_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_17_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_17_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_17_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_17_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_17_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_17_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_17_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_17_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_17_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_17_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_17_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_17_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_17_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_17_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_17_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_17_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_17_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_17_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_17_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_17_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_17_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_17_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_17_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_17_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_17_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_17_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_17_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_17_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_17_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_17_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_17_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_17_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_17_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_17_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_17_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_17_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_17_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_17_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_17_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_17_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_17_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_17_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_17_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_17_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_17_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_17_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_17_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_17_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_17_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_17_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_17_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_17_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_17_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_17_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_17_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_17_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_17_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_17_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_17_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_17_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_17_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_18
+#define WAKE_AOWAKE_CNTRL_18                    MK_ADDR_CONST(0x48)
+#define WAKE_AOWAKE_CNTRL_18_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_18_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_18_SCR                        EVENT_CNTRL_SCR_18
+#define WAKE_AOWAKE_CNTRL_18_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_18
+#define WAKE_AOWAKE_CNTRL_18_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_18_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_18_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_18_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_18_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_18_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_18_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_18_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_18_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_18_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_18_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_18_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_18_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_18_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_18_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_18_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_18_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_18_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_18_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_18_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_18_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_18_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_18_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_18_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_18_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_18_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_18_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_18_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_18_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_18_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_18_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_18_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_18_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_18_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_18_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_18_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_18_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_18_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_18_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_18_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_18_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_18_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_18_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_18_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_18_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_18_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_18_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_18_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_18_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_18_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_18_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_18_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_18_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_18_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_18_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_18_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_18_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_18_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_18_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_18_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_18_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_18_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_18_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_18_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_18_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_18_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_18_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_18_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_18_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_18_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_19
+#define WAKE_AOWAKE_CNTRL_19                    MK_ADDR_CONST(0x4c)
+#define WAKE_AOWAKE_CNTRL_19_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_19_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_19_SCR                        EVENT_CNTRL_SCR_19
+#define WAKE_AOWAKE_CNTRL_19_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_19
+#define WAKE_AOWAKE_CNTRL_19_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_19_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_19_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_19_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_19_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_19_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_19_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_19_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_19_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_19_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_19_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_19_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_19_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_19_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_19_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_19_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_19_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_19_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_19_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_19_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_19_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_19_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_19_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_19_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_19_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_19_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_19_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_19_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_19_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_19_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_19_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_19_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_19_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_19_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_19_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_19_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_19_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_19_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_19_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_19_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_19_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_19_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_19_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_19_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_19_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_19_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_19_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_19_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_19_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_19_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_19_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_19_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_19_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_19_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_19_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_19_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_19_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_19_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_19_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_19_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_19_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_19_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_19_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_19_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_19_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_19_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_19_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_19_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_19_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_19_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_20
+#define WAKE_AOWAKE_CNTRL_20                    MK_ADDR_CONST(0x50)
+#define WAKE_AOWAKE_CNTRL_20_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_20_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_20_SCR                        EVENT_CNTRL_SCR_20
+#define WAKE_AOWAKE_CNTRL_20_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_20
+#define WAKE_AOWAKE_CNTRL_20_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_20_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_20_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_20_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_20_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_20_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_20_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_20_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_20_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_20_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_20_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_20_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_20_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_20_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_20_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_20_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_20_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_20_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_20_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_20_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_20_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_20_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_20_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_20_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_20_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_20_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_20_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_20_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_20_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_20_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_20_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_20_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_20_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_20_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_20_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_20_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_20_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_20_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_20_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_20_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_20_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_20_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_20_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_20_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_20_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_20_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_20_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_20_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_20_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_20_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_20_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_20_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_20_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_20_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_20_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_20_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_20_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_20_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_20_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_20_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_20_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_20_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_20_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_20_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_20_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_20_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_20_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_20_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_20_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_20_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_21
+#define WAKE_AOWAKE_CNTRL_21                    MK_ADDR_CONST(0x54)
+#define WAKE_AOWAKE_CNTRL_21_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_21_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_21_SCR                        EVENT_CNTRL_SCR_21
+#define WAKE_AOWAKE_CNTRL_21_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_21
+#define WAKE_AOWAKE_CNTRL_21_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_21_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_21_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_21_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_21_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_21_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_21_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_21_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_21_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_21_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_21_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_21_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_21_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_21_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_21_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_21_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_21_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_21_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_21_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_21_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_21_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_21_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_21_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_21_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_21_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_21_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_21_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_21_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_21_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_21_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_21_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_21_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_21_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_21_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_21_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_21_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_21_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_21_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_21_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_21_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_21_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_21_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_21_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_21_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_21_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_21_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_21_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_21_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_21_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_21_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_21_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_21_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_21_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_21_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_21_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_21_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_21_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_21_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_21_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_21_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_21_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_21_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_21_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_21_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_21_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_21_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_21_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_21_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_21_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_21_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_22
+#define WAKE_AOWAKE_CNTRL_22                    MK_ADDR_CONST(0x58)
+#define WAKE_AOWAKE_CNTRL_22_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_22_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_22_SCR                        EVENT_CNTRL_SCR_22
+#define WAKE_AOWAKE_CNTRL_22_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_22
+#define WAKE_AOWAKE_CNTRL_22_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_22_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_22_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_22_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_22_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_22_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_22_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_22_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_22_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_22_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_22_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_22_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_22_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_22_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_22_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_22_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_22_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_22_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_22_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_22_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_22_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_22_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_22_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_22_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_22_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_22_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_22_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_22_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_22_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_22_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_22_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_22_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_22_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_22_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_22_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_22_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_22_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_22_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_22_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_22_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_22_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_22_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_22_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_22_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_22_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_22_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_22_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_22_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_22_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_22_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_22_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_22_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_22_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_22_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_22_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_22_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_22_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_22_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_22_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_22_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_22_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_22_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_22_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_22_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_22_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_22_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_22_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_22_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_22_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_22_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_23
+#define WAKE_AOWAKE_CNTRL_23                    MK_ADDR_CONST(0x5c)
+#define WAKE_AOWAKE_CNTRL_23_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_23_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_23_SCR                        EVENT_CNTRL_SCR_23
+#define WAKE_AOWAKE_CNTRL_23_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_23
+#define WAKE_AOWAKE_CNTRL_23_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_23_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_23_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_23_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_23_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_23_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_23_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_23_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_23_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_23_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_23_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_23_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_23_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_23_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_23_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_23_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_23_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_23_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_23_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_23_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_23_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_23_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_23_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_23_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_23_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_23_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_23_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_23_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_23_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_23_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_23_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_23_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_23_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_23_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_23_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_23_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_23_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_23_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_23_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_23_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_23_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_23_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_23_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_23_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_23_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_23_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_23_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_23_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_23_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_23_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_23_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_23_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_23_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_23_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_23_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_23_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_23_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_23_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_23_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_23_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_23_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_23_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_23_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_23_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_23_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_23_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_23_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_23_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_23_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_23_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_24
+#define WAKE_AOWAKE_CNTRL_24                    MK_ADDR_CONST(0x60)
+#define WAKE_AOWAKE_CNTRL_24_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_24_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_24_SCR                        EVENT_CNTRL_SCR_24
+#define WAKE_AOWAKE_CNTRL_24_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_24
+#define WAKE_AOWAKE_CNTRL_24_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_24_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_24_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_24_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_24_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_24_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_24_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_24_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_24_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_24_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_24_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_24_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_24_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_24_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_24_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_24_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_24_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_24_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_24_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_24_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_24_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_24_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_24_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_24_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_24_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_24_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_24_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_24_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_24_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_24_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_24_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_24_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_24_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_24_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_24_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_24_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_24_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_24_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_24_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_24_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_24_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_24_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_24_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_24_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_24_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_24_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_24_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_24_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_24_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_24_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_24_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_24_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_24_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_24_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_24_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_24_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_24_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_24_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_24_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_24_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_24_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_24_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_24_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_24_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_24_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_24_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_24_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_24_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_24_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_24_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_25
+#define WAKE_AOWAKE_CNTRL_25                    MK_ADDR_CONST(0x64)
+#define WAKE_AOWAKE_CNTRL_25_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_25_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_25_SCR                        EVENT_CNTRL_SCR_25
+#define WAKE_AOWAKE_CNTRL_25_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_25
+#define WAKE_AOWAKE_CNTRL_25_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_25_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_25_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_25_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_25_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_25_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_25_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_25_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_25_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_25_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_25_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_25_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_25_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_25_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_25_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_25_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_25_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_25_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_25_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_25_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_25_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_25_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_25_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_25_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_25_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_25_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_25_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_25_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_25_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_25_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_25_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_25_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_25_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_25_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_25_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_25_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_25_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_25_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_25_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_25_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_25_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_25_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_25_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_25_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_25_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_25_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_25_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_25_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_25_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_25_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_25_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_25_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_25_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_25_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_25_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_25_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_25_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_25_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_25_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_25_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_25_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_25_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_25_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_25_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_25_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_25_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_25_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_25_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_25_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_25_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_26
+#define WAKE_AOWAKE_CNTRL_26                    MK_ADDR_CONST(0x68)
+#define WAKE_AOWAKE_CNTRL_26_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_26_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_26_SCR                        EVENT_CNTRL_SCR_26
+#define WAKE_AOWAKE_CNTRL_26_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_26
+#define WAKE_AOWAKE_CNTRL_26_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_26_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_26_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_26_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_26_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_26_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_26_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_26_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_26_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_26_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_26_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_26_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_26_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_26_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_26_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_26_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_26_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_26_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_26_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_26_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_26_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_26_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_26_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_26_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_26_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_26_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_26_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_26_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_26_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_26_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_26_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_26_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_26_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_26_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_26_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_26_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_26_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_26_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_26_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_26_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_26_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_26_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_26_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_26_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_26_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_26_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_26_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_26_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_26_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_26_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_26_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_26_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_26_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_26_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_26_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_26_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_26_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_26_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_26_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_26_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_26_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_26_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_26_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_26_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_26_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_26_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_26_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_26_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_26_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_26_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_27
+#define WAKE_AOWAKE_CNTRL_27                    MK_ADDR_CONST(0x6c)
+#define WAKE_AOWAKE_CNTRL_27_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_27_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_27_SCR                        EVENT_CNTRL_SCR_27
+#define WAKE_AOWAKE_CNTRL_27_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_27
+#define WAKE_AOWAKE_CNTRL_27_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_27_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_27_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_27_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_27_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_27_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_27_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_27_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_27_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_27_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_27_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_27_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_27_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_27_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_27_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_27_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_27_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_27_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_27_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_27_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_27_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_27_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_27_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_27_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_27_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_27_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_27_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_27_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_27_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_27_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_27_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_27_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_27_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_27_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_27_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_27_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_27_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_27_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_27_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_27_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_27_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_27_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_27_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_27_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_27_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_27_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_27_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_27_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_27_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_27_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_27_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_27_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_27_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_27_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_27_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_27_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_27_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_27_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_27_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_27_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_27_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_27_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_27_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_27_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_27_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_27_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_27_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_27_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_27_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_27_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_28
+#define WAKE_AOWAKE_CNTRL_28                    MK_ADDR_CONST(0x70)
+#define WAKE_AOWAKE_CNTRL_28_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_28_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_28_SCR                        EVENT_CNTRL_SCR_28
+#define WAKE_AOWAKE_CNTRL_28_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_28
+#define WAKE_AOWAKE_CNTRL_28_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_28_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_28_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_28_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_28_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_28_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_28_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_28_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_28_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_28_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_28_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_28_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_28_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_28_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_28_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_28_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_28_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_28_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_28_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_28_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_28_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_28_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_28_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_28_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_28_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_28_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_28_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_28_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_28_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_28_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_28_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_28_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_28_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_28_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_28_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_28_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_28_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_28_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_28_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_28_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_28_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_28_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_28_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_28_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_28_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_28_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_28_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_28_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_28_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_28_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_28_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_28_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_28_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_28_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_28_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_28_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_28_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_28_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_28_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_28_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_28_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_28_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_28_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_28_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_28_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_28_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_28_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_28_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_28_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_28_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_29
+#define WAKE_AOWAKE_CNTRL_29                    MK_ADDR_CONST(0x74)
+#define WAKE_AOWAKE_CNTRL_29_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_29_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_29_SCR                        EVENT_CNTRL_SCR_29
+#define WAKE_AOWAKE_CNTRL_29_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_29
+#define WAKE_AOWAKE_CNTRL_29_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_29_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_29_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_29_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_29_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_29_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_29_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_29_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_29_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_29_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_29_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_29_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_29_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_29_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_29_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_29_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_29_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_29_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_29_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_29_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_29_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_29_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_29_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_29_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_29_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_29_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_29_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_29_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_29_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_29_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_29_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_29_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_29_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_29_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_29_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_29_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_29_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_29_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_29_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_29_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_29_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_29_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_29_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_29_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_29_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_29_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_29_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_29_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_29_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_29_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_29_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_29_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_29_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_29_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_29_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_29_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_29_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_29_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_29_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_29_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_29_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_29_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_29_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_29_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_29_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_29_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_29_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_29_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_29_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_29_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_30
+#define WAKE_AOWAKE_CNTRL_30                    MK_ADDR_CONST(0x78)
+#define WAKE_AOWAKE_CNTRL_30_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_30_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_30_SCR                        EVENT_CNTRL_SCR_30
+#define WAKE_AOWAKE_CNTRL_30_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_30
+#define WAKE_AOWAKE_CNTRL_30_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_30_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_30_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_30_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_30_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_30_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_30_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_30_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_30_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_30_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_30_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_30_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_30_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_30_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_30_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_30_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_30_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_30_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_30_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_30_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_30_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_30_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_30_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_30_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_30_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_30_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_30_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_30_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_30_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_30_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_30_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_30_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_30_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_30_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_30_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_30_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_30_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_30_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_30_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_30_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_30_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_30_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_30_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_30_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_30_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_30_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_30_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_30_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_30_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_30_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_30_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_30_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_30_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_30_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_30_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_30_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_30_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_30_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_30_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_30_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_30_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_30_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_30_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_30_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_30_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_30_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_30_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_30_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_30_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_30_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_31
+#define WAKE_AOWAKE_CNTRL_31                    MK_ADDR_CONST(0x7c)
+#define WAKE_AOWAKE_CNTRL_31_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_31_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_31_SCR                        EVENT_CNTRL_SCR_31
+#define WAKE_AOWAKE_CNTRL_31_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_31
+#define WAKE_AOWAKE_CNTRL_31_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_31_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_31_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_31_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_31_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_31_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_31_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_31_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_31_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_31_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_31_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_31_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_31_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_31_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_31_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_31_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_31_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_31_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_31_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_31_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_31_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_31_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_31_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_31_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_31_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_31_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_31_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_31_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_31_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_31_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_31_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_31_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_31_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_31_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_31_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_31_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_31_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_31_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_31_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_31_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_31_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_31_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_31_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_31_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_31_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_31_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_31_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_31_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_31_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_31_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_31_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_31_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_31_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_31_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_31_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_31_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_31_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_31_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_31_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_31_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_31_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_31_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_31_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_31_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_31_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_31_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_31_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_31_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_31_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_31_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_32
+#define WAKE_AOWAKE_CNTRL_32                    MK_ADDR_CONST(0x80)
+#define WAKE_AOWAKE_CNTRL_32_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_32_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_32_SCR                        EVENT_CNTRL_SCR_32
+#define WAKE_AOWAKE_CNTRL_32_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_32
+#define WAKE_AOWAKE_CNTRL_32_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_32_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_32_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_32_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_32_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_32_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_32_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_32_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_32_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_32_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_32_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_32_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_32_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_32_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_32_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_32_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_32_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_32_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_32_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_32_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_32_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_32_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_32_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_32_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_32_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_32_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_32_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_32_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_32_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_32_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_32_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_32_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_32_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_32_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_32_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_32_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_32_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_32_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_32_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_32_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_32_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_32_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_32_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_32_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_32_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_32_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_32_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_32_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_32_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_32_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_32_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_32_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_32_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_32_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_32_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_32_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_32_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_32_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_32_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_32_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_32_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_32_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_32_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_32_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_32_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_32_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_32_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_32_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_32_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_32_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_33
+#define WAKE_AOWAKE_CNTRL_33                    MK_ADDR_CONST(0x84)
+#define WAKE_AOWAKE_CNTRL_33_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_33_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_33_SCR                        EVENT_CNTRL_SCR_33
+#define WAKE_AOWAKE_CNTRL_33_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_33
+#define WAKE_AOWAKE_CNTRL_33_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_33_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_33_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_33_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_33_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_33_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_33_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_33_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_33_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_33_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_33_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_33_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_33_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_33_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_33_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_33_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_33_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_33_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_33_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_33_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_33_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_33_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_33_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_33_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_33_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_33_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_33_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_33_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_33_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_33_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_33_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_33_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_33_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_33_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_33_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_33_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_33_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_33_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_33_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_33_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_33_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_33_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_33_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_33_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_33_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_33_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_33_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_33_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_33_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_33_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_33_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_33_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_33_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_33_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_33_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_33_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_33_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_33_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_33_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_33_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_33_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_33_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_33_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_33_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_33_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_33_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_33_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_33_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_33_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_33_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_34
+#define WAKE_AOWAKE_CNTRL_34                    MK_ADDR_CONST(0x88)
+#define WAKE_AOWAKE_CNTRL_34_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_34_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_34_SCR                        EVENT_CNTRL_SCR_34
+#define WAKE_AOWAKE_CNTRL_34_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_34
+#define WAKE_AOWAKE_CNTRL_34_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_34_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_34_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_34_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_34_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_34_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_34_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_34_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_34_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_34_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_34_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_34_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_34_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_34_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_34_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_34_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_34_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_34_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_34_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_34_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_34_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_34_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_34_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_34_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_34_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_34_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_34_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_34_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_34_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_34_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_34_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_34_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_34_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_34_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_34_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_34_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_34_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_34_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_34_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_34_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_34_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_34_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_34_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_34_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_34_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_34_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_34_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_34_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_34_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_34_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_34_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_34_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_34_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_34_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_34_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_34_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_34_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_34_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_34_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_34_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_34_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_34_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_34_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_34_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_34_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_34_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_34_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_34_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_34_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_34_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_35
+#define WAKE_AOWAKE_CNTRL_35                    MK_ADDR_CONST(0x8c)
+#define WAKE_AOWAKE_CNTRL_35_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_35_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_35_SCR                        EVENT_CNTRL_SCR_35
+#define WAKE_AOWAKE_CNTRL_35_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_35
+#define WAKE_AOWAKE_CNTRL_35_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_35_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_35_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_35_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_35_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_35_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_35_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_35_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_35_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_35_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_35_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_35_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_35_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_35_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_35_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_35_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_35_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_35_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_35_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_35_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_35_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_35_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_35_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_35_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_35_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_35_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_35_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_35_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_35_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_35_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_35_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_35_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_35_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_35_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_35_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_35_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_35_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_35_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_35_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_35_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_35_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_35_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_35_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_35_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_35_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_35_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_35_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_35_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_35_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_35_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_35_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_35_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_35_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_35_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_35_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_35_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_35_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_35_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_35_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_35_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_35_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_35_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_35_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_35_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_35_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_35_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_35_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_35_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_35_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_35_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_36
+#define WAKE_AOWAKE_CNTRL_36                    MK_ADDR_CONST(0x90)
+#define WAKE_AOWAKE_CNTRL_36_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_36_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_36_SCR                        EVENT_CNTRL_SCR_36
+#define WAKE_AOWAKE_CNTRL_36_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_36
+#define WAKE_AOWAKE_CNTRL_36_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_36_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_36_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_36_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_36_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_36_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_36_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_36_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_36_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_36_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_36_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_36_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_36_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_36_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_36_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_36_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_36_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_36_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_36_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_36_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_36_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_36_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_36_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_36_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_36_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_36_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_36_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_36_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_36_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_36_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_36_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_36_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_36_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_36_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_36_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_36_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_36_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_36_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_36_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_36_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_36_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_36_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_36_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_36_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_36_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_36_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_36_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_36_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_36_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_36_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_36_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_36_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_36_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_36_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_36_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_36_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_36_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_36_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_36_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_36_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_36_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_36_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_36_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_36_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_36_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_36_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_36_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_36_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_36_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_36_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_37
+#define WAKE_AOWAKE_CNTRL_37                    MK_ADDR_CONST(0x94)
+#define WAKE_AOWAKE_CNTRL_37_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_37_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_37_SCR                        EVENT_CNTRL_SCR_37
+#define WAKE_AOWAKE_CNTRL_37_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_37
+#define WAKE_AOWAKE_CNTRL_37_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_37_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_37_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_37_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_37_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_37_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_37_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_37_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_37_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_37_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_37_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_37_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_37_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_37_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_37_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_37_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_37_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_37_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_37_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_37_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_37_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_37_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_37_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_37_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_37_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_37_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_37_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_37_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_37_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_37_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_37_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_37_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_37_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_37_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_37_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_37_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_37_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_37_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_37_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_37_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_37_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_37_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_37_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_37_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_37_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_37_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_37_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_37_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_37_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_37_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_37_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_37_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_37_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_37_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_37_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_37_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_37_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_37_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_37_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_37_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_37_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_37_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_37_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_37_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_37_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_37_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_37_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_37_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_37_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_37_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_38
+#define WAKE_AOWAKE_CNTRL_38                    MK_ADDR_CONST(0x98)
+#define WAKE_AOWAKE_CNTRL_38_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_38_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_38_SCR                        EVENT_CNTRL_SCR_38
+#define WAKE_AOWAKE_CNTRL_38_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_38
+#define WAKE_AOWAKE_CNTRL_38_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_38_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_38_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_38_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_38_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_38_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_38_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_38_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_38_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_38_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_38_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_38_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_38_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_38_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_38_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_38_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_38_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_38_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_38_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_38_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_38_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_38_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_38_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_38_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_38_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_38_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_38_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_38_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_38_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_38_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_38_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_38_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_38_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_38_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_38_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_38_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_38_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_38_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_38_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_38_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_38_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_38_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_38_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_38_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_38_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_38_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_38_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_38_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_38_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_38_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_38_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_38_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_38_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_38_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_38_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_38_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_38_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_38_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_38_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_38_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_38_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_38_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_38_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_38_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_38_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_38_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_38_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_38_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_38_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_38_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_39
+#define WAKE_AOWAKE_CNTRL_39                    MK_ADDR_CONST(0x9c)
+#define WAKE_AOWAKE_CNTRL_39_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_39_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_39_SCR                        EVENT_CNTRL_SCR_39
+#define WAKE_AOWAKE_CNTRL_39_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_39
+#define WAKE_AOWAKE_CNTRL_39_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_39_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_39_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_39_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_39_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_39_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_39_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_39_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_39_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_39_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_39_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_39_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_39_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_39_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_39_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_39_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_39_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_39_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_39_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_39_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_39_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_39_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_39_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_39_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_39_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_39_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_39_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_39_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_39_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_39_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_39_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_39_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_39_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_39_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_39_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_39_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_39_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_39_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_39_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_39_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_39_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_39_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_39_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_39_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_39_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_39_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_39_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_39_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_39_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_39_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_39_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_39_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_39_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_39_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_39_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_39_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_39_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_39_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_39_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_39_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_39_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_39_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_39_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_39_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_39_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_39_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_39_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_39_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_39_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_39_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_40
+#define WAKE_AOWAKE_CNTRL_40                    MK_ADDR_CONST(0xa0)
+#define WAKE_AOWAKE_CNTRL_40_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_40_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_40_SCR                        EVENT_CNTRL_SCR_40
+#define WAKE_AOWAKE_CNTRL_40_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_40
+#define WAKE_AOWAKE_CNTRL_40_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_40_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_40_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_40_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_40_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_40_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_40_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_40_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_40_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_40_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_40_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_40_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_40_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_40_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_40_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_40_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_40_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_40_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_40_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_40_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_40_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_40_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_40_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_40_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_40_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_40_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_40_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_40_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_40_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_40_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_40_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_40_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_40_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_40_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_40_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_40_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_40_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_40_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_40_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_40_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_40_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_40_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_40_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_40_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_40_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_40_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_40_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_40_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_40_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_40_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_40_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_40_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_40_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_40_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_40_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_40_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_40_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_40_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_40_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_40_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_40_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_40_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_40_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_40_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_40_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_40_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_40_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_40_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_40_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_40_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_41
+#define WAKE_AOWAKE_CNTRL_41                    MK_ADDR_CONST(0xa4)
+#define WAKE_AOWAKE_CNTRL_41_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_41_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_41_SCR                        EVENT_CNTRL_SCR_41
+#define WAKE_AOWAKE_CNTRL_41_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_41
+#define WAKE_AOWAKE_CNTRL_41_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_41_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_41_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_41_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_41_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_41_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_41_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_41_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_41_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_41_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_41_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_41_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_41_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_41_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_41_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_41_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_41_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_41_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_41_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_41_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_41_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_41_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_41_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_41_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_41_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_41_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_41_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_41_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_41_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_41_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_41_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_41_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_41_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_41_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_41_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_41_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_41_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_41_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_41_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_41_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_41_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_41_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_41_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_41_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_41_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_41_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_41_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_41_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_41_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_41_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_41_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_41_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_41_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_41_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_41_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_41_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_41_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_41_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_41_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_41_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_41_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_41_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_41_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_41_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_41_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_41_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_41_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_41_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_41_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_41_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_42
+#define WAKE_AOWAKE_CNTRL_42                    MK_ADDR_CONST(0xa8)
+#define WAKE_AOWAKE_CNTRL_42_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_42_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_42_SCR                        EVENT_CNTRL_SCR_42
+#define WAKE_AOWAKE_CNTRL_42_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_42
+#define WAKE_AOWAKE_CNTRL_42_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_42_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_42_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_42_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_42_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_42_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_42_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_42_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_42_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_42_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_42_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_42_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_42_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_42_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_42_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_42_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_42_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_42_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_42_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_42_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_42_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_42_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_42_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_42_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_42_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_42_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_42_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_42_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_42_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_42_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_42_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_42_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_42_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_42_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_42_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_42_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_42_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_42_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_42_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_42_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_42_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_42_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_42_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_42_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_42_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_42_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_42_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_42_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_42_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_42_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_42_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_42_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_42_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_42_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_42_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_42_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_42_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_42_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_42_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_42_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_42_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_42_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_42_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_42_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_42_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_42_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_42_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_42_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_42_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_42_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_43
+#define WAKE_AOWAKE_CNTRL_43                    MK_ADDR_CONST(0xac)
+#define WAKE_AOWAKE_CNTRL_43_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_43_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_43_SCR                        EVENT_CNTRL_SCR_43
+#define WAKE_AOWAKE_CNTRL_43_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_43
+#define WAKE_AOWAKE_CNTRL_43_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_43_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_43_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_43_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_43_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_43_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_43_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_43_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_43_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_43_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_43_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_43_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_43_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_43_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_43_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_43_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_43_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_43_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_43_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_43_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_43_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_43_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_43_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_43_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_43_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_43_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_43_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_43_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_43_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_43_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_43_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_43_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_43_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_43_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_43_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_43_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_43_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_43_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_43_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_43_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_43_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_43_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_43_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_43_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_43_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_43_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_43_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_43_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_43_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_43_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_43_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_43_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_43_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_43_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_43_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_43_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_43_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_43_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_43_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_43_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_43_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_43_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_43_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_43_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_43_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_43_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_43_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_43_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_43_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_43_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_44
+#define WAKE_AOWAKE_CNTRL_44                    MK_ADDR_CONST(0xb0)
+#define WAKE_AOWAKE_CNTRL_44_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_44_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_44_SCR                        EVENT_CNTRL_SCR_44
+#define WAKE_AOWAKE_CNTRL_44_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_44
+#define WAKE_AOWAKE_CNTRL_44_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_44_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_44_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_44_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_44_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_44_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_44_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_44_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_44_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_44_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_44_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_44_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_44_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_44_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_44_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_44_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_44_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_44_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_44_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_44_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_44_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_44_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_44_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_44_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_44_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_44_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_44_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_44_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_44_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_44_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_44_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_44_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_44_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_44_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_44_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_44_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_44_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_44_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_44_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_44_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_44_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_44_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_44_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_44_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_44_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_44_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_44_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_44_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_44_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_44_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_44_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_44_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_44_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_44_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_44_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_44_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_44_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_44_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_44_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_44_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_44_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_44_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_44_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_44_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_44_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_44_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_44_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_44_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_44_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_44_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_45
+#define WAKE_AOWAKE_CNTRL_45                    MK_ADDR_CONST(0xb4)
+#define WAKE_AOWAKE_CNTRL_45_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_45_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_45_SCR                        EVENT_CNTRL_SCR_45
+#define WAKE_AOWAKE_CNTRL_45_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_45
+#define WAKE_AOWAKE_CNTRL_45_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_45_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_45_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_45_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_45_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_45_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_45_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_45_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_45_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_45_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_45_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_45_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_45_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_45_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_45_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_45_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_45_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_45_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_45_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_45_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_45_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_45_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_45_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_45_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_45_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_45_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_45_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_45_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_45_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_45_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_45_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_45_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_45_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_45_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_45_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_45_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_45_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_45_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_45_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_45_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_45_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_45_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_45_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_45_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_45_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_45_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_45_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_45_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_45_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_45_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_45_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_45_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_45_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_45_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_45_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_45_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_45_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_45_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_45_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_45_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_45_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_45_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_45_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_45_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_45_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_45_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_45_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_45_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_45_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_45_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_46
+#define WAKE_AOWAKE_CNTRL_46                    MK_ADDR_CONST(0xb8)
+#define WAKE_AOWAKE_CNTRL_46_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_46_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_46_SCR                        EVENT_CNTRL_SCR_46
+#define WAKE_AOWAKE_CNTRL_46_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_46
+#define WAKE_AOWAKE_CNTRL_46_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_46_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_46_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_46_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_46_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_46_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_46_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_46_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_46_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_46_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_46_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_46_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_46_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_46_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_46_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_46_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_46_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_46_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_46_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_46_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_46_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_46_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_46_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_46_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_46_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_46_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_46_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_46_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_46_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_46_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_46_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_46_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_46_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_46_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_46_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_46_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_46_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_46_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_46_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_46_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_46_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_46_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_46_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_46_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_46_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_46_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_46_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_46_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_46_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_46_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_46_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_46_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_46_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_46_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_46_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_46_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_46_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_46_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_46_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_46_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_46_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_46_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_46_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_46_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_46_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_46_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_46_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_46_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_46_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_46_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_47
+#define WAKE_AOWAKE_CNTRL_47                    MK_ADDR_CONST(0xbc)
+#define WAKE_AOWAKE_CNTRL_47_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_47_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_47_SCR                        EVENT_CNTRL_SCR_47
+#define WAKE_AOWAKE_CNTRL_47_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_47
+#define WAKE_AOWAKE_CNTRL_47_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_47_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_47_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_47_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_47_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_47_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_47_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_47_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_47_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_47_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_47_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_47_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_47_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_47_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_47_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_47_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_47_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_47_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_47_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_47_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_47_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_47_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_47_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_47_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_47_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_47_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_47_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_47_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_47_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_47_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_47_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_47_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_47_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_47_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_47_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_47_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_47_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_47_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_47_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_47_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_47_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_47_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_47_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_47_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_47_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_47_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_47_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_47_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_47_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_47_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_47_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_47_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_47_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_47_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_47_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_47_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_47_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_47_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_47_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_47_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_47_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_47_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_47_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_47_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_47_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_47_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_47_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_47_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_47_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_47_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_48
+#define WAKE_AOWAKE_CNTRL_48                    MK_ADDR_CONST(0xc0)
+#define WAKE_AOWAKE_CNTRL_48_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_48_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_48_SCR                        EVENT_CNTRL_SCR_48
+#define WAKE_AOWAKE_CNTRL_48_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_48
+#define WAKE_AOWAKE_CNTRL_48_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_48_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_48_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_48_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_48_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_48_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_48_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_48_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_48_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_48_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_48_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_48_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_48_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_48_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_48_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_48_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_48_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_48_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_48_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_48_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_48_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_48_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_48_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_48_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_48_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_48_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_48_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_48_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_48_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_48_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_48_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_48_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_48_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_48_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_48_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_48_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_48_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_48_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_48_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_48_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_48_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_48_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_48_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_48_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_48_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_48_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_48_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_48_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_48_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_48_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_48_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_48_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_48_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_48_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_48_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_48_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_48_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_48_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_48_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_48_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_48_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_48_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_48_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_48_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_48_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_48_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_48_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_48_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_48_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_48_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_49
+#define WAKE_AOWAKE_CNTRL_49                    MK_ADDR_CONST(0xc4)
+#define WAKE_AOWAKE_CNTRL_49_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_49_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_49_SCR                        EVENT_CNTRL_SCR_49
+#define WAKE_AOWAKE_CNTRL_49_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_49
+#define WAKE_AOWAKE_CNTRL_49_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_49_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_49_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_49_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_49_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_49_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_49_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_49_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_49_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_49_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_49_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_49_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_49_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_49_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_49_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_49_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_49_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_49_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_49_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_49_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_49_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_49_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_49_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_49_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_49_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_49_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_49_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_49_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_49_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_49_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_49_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_49_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_49_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_49_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_49_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_49_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_49_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_49_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_49_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_49_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_49_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_49_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_49_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_49_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_49_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_49_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_49_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_49_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_49_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_49_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_49_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_49_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_49_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_49_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_49_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_49_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_49_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_49_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_49_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_49_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_49_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_49_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_49_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_49_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_49_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_49_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_49_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_49_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_49_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_49_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_50
+#define WAKE_AOWAKE_CNTRL_50                    MK_ADDR_CONST(0xc8)
+#define WAKE_AOWAKE_CNTRL_50_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_50_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_50_SCR                        EVENT_CNTRL_SCR_50
+#define WAKE_AOWAKE_CNTRL_50_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_50
+#define WAKE_AOWAKE_CNTRL_50_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_50_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_50_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_50_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_50_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_50_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_50_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_50_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_50_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_50_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_50_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_50_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_50_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_50_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_50_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_50_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_50_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_50_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_50_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_50_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_50_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_50_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_50_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_50_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_50_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_50_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_50_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_50_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_50_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_50_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_50_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_50_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_50_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_50_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_50_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_50_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_50_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_50_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_50_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_50_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_50_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_50_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_50_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_50_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_50_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_50_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_50_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_50_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_50_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_50_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_50_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_50_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_50_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_50_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_50_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_50_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_50_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_50_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_50_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_50_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_50_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_50_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_50_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_50_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_50_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_50_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_50_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_50_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_50_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_50_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_51
+#define WAKE_AOWAKE_CNTRL_51                    MK_ADDR_CONST(0xcc)
+#define WAKE_AOWAKE_CNTRL_51_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_51_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_51_SCR                        EVENT_CNTRL_SCR_51
+#define WAKE_AOWAKE_CNTRL_51_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_51
+#define WAKE_AOWAKE_CNTRL_51_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_51_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_51_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_51_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_51_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_51_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_51_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_51_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_51_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_51_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_51_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_51_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_51_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_51_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_51_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_51_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_51_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_51_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_51_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_51_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_51_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_51_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_51_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_51_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_51_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_51_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_51_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_51_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_51_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_51_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_51_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_51_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_51_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_51_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_51_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_51_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_51_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_51_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_51_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_51_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_51_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_51_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_51_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_51_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_51_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_51_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_51_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_51_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_51_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_51_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_51_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_51_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_51_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_51_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_51_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_51_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_51_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_51_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_51_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_51_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_51_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_51_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_51_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_51_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_51_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_51_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_51_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_51_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_51_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_51_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_52
+#define WAKE_AOWAKE_CNTRL_52                    MK_ADDR_CONST(0xd0)
+#define WAKE_AOWAKE_CNTRL_52_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_52_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_52_SCR                        EVENT_CNTRL_SCR_52
+#define WAKE_AOWAKE_CNTRL_52_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_52
+#define WAKE_AOWAKE_CNTRL_52_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_52_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_52_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_52_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_52_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_52_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_52_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_52_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_52_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_52_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_52_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_52_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_52_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_52_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_52_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_52_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_52_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_52_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_52_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_52_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_52_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_52_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_52_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_52_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_52_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_52_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_52_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_52_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_52_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_52_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_52_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_52_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_52_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_52_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_52_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_52_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_52_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_52_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_52_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_52_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_52_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_52_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_52_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_52_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_52_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_52_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_52_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_52_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_52_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_52_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_52_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_52_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_52_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_52_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_52_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_52_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_52_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_52_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_52_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_52_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_52_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_52_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_52_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_52_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_52_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_52_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_52_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_52_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_52_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_52_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_53
+#define WAKE_AOWAKE_CNTRL_53                    MK_ADDR_CONST(0xd4)
+#define WAKE_AOWAKE_CNTRL_53_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_53_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_53_SCR                        EVENT_CNTRL_SCR_53
+#define WAKE_AOWAKE_CNTRL_53_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_53
+#define WAKE_AOWAKE_CNTRL_53_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_53_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_53_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_53_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_53_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_53_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_53_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_53_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_53_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_53_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_53_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_53_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_53_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_53_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_53_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_53_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_53_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_53_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_53_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_53_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_53_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_53_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_53_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_53_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_53_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_53_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_53_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_53_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_53_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_53_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_53_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_53_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_53_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_53_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_53_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_53_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_53_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_53_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_53_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_53_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_53_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_53_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_53_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_53_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_53_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_53_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_53_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_53_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_53_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_53_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_53_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_53_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_53_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_53_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_53_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_53_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_53_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_53_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_53_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_53_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_53_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_53_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_53_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_53_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_53_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_53_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_53_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_53_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_53_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_53_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_54
+#define WAKE_AOWAKE_CNTRL_54                    MK_ADDR_CONST(0xd8)
+#define WAKE_AOWAKE_CNTRL_54_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_54_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_54_SCR                        EVENT_CNTRL_SCR_54
+#define WAKE_AOWAKE_CNTRL_54_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_54
+#define WAKE_AOWAKE_CNTRL_54_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_54_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_54_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_54_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_54_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_54_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_54_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_54_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_54_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_54_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_54_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_54_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_54_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_54_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_54_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_54_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_54_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_54_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_54_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_54_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_54_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_54_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_54_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_54_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_54_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_54_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_54_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_54_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_54_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_54_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_54_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_54_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_54_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_54_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_54_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_54_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_54_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_54_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_54_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_54_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_54_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_54_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_54_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_54_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_54_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_54_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_54_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_54_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_54_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_54_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_54_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_54_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_54_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_54_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_54_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_54_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_54_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_54_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_54_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_54_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_54_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_54_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_54_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_54_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_54_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_54_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_54_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_54_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_54_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_54_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_55
+#define WAKE_AOWAKE_CNTRL_55                    MK_ADDR_CONST(0xdc)
+#define WAKE_AOWAKE_CNTRL_55_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_55_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_55_SCR                        EVENT_CNTRL_SCR_55
+#define WAKE_AOWAKE_CNTRL_55_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_55
+#define WAKE_AOWAKE_CNTRL_55_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_55_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_55_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_55_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_55_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_55_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_55_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_55_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_55_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_55_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_55_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_55_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_55_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_55_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_55_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_55_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_55_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_55_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_55_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_55_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_55_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_55_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_55_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_55_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_55_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_55_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_55_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_55_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_55_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_55_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_55_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_55_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_55_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_55_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_55_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_55_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_55_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_55_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_55_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_55_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_55_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_55_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_55_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_55_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_55_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_55_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_55_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_55_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_55_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_55_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_55_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_55_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_55_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_55_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_55_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_55_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_55_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_55_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_55_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_55_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_55_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_55_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_55_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_55_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_55_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_55_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_55_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_55_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_55_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_55_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_56
+#define WAKE_AOWAKE_CNTRL_56                    MK_ADDR_CONST(0xe0)
+#define WAKE_AOWAKE_CNTRL_56_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_56_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_56_SCR                        EVENT_CNTRL_SCR_56
+#define WAKE_AOWAKE_CNTRL_56_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_56
+#define WAKE_AOWAKE_CNTRL_56_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_56_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_56_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_56_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_56_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_56_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_56_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_56_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_56_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_56_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_56_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_56_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_56_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_56_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_56_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_56_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_56_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_56_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_56_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_56_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_56_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_56_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_56_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_56_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_56_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_56_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_56_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_56_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_56_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_56_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_56_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_56_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_56_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_56_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_56_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_56_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_56_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_56_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_56_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_56_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_56_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_56_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_56_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_56_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_56_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_56_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_56_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_56_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_56_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_56_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_56_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_56_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_56_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_56_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_56_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_56_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_56_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_56_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_56_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_56_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_56_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_56_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_56_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_56_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_56_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_56_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_56_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_56_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_56_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_56_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_57
+#define WAKE_AOWAKE_CNTRL_57                    MK_ADDR_CONST(0xe4)
+#define WAKE_AOWAKE_CNTRL_57_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_57_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_57_SCR                        EVENT_CNTRL_SCR_57
+#define WAKE_AOWAKE_CNTRL_57_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_57
+#define WAKE_AOWAKE_CNTRL_57_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_57_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_57_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_57_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_57_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_57_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_57_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_57_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_57_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_57_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_57_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_57_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_57_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_57_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_57_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_57_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_57_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_57_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_57_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_57_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_57_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_57_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_57_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_57_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_57_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_57_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_57_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_57_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_57_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_57_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_57_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_57_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_57_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_57_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_57_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_57_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_57_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_57_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_57_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_57_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_57_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_57_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_57_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_57_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_57_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_57_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_57_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_57_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_57_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_57_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_57_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_57_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_57_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_57_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_57_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_57_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_57_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_57_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_57_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_57_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_57_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_57_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_57_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_57_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_57_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_57_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_57_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_57_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_57_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_57_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_58
+#define WAKE_AOWAKE_CNTRL_58                    MK_ADDR_CONST(0xe8)
+#define WAKE_AOWAKE_CNTRL_58_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_58_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_58_SCR                        EVENT_CNTRL_SCR_58
+#define WAKE_AOWAKE_CNTRL_58_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_58
+#define WAKE_AOWAKE_CNTRL_58_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_58_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_58_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_58_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_58_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_58_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_58_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_58_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_58_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_58_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_58_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_58_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_58_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_58_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_58_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_58_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_58_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_58_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_58_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_58_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_58_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_58_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_58_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_58_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_58_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_58_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_58_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_58_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_58_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_58_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_58_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_58_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_58_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_58_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_58_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_58_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_58_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_58_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_58_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_58_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_58_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_58_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_58_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_58_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_58_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_58_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_58_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_58_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_58_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_58_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_58_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_58_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_58_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_58_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_58_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_58_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_58_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_58_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_58_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_58_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_58_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_58_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_58_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_58_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_58_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_58_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_58_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_58_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_58_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_58_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_59
+#define WAKE_AOWAKE_CNTRL_59                    MK_ADDR_CONST(0xec)
+#define WAKE_AOWAKE_CNTRL_59_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_59_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_59_SCR                        EVENT_CNTRL_SCR_59
+#define WAKE_AOWAKE_CNTRL_59_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_59
+#define WAKE_AOWAKE_CNTRL_59_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_59_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_59_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_59_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_59_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_59_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_59_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_59_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_59_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_59_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_59_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_59_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_59_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_59_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_59_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_59_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_59_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_59_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_59_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_59_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_59_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_59_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_59_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_59_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_59_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_59_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_59_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_59_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_59_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_59_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_59_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_59_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_59_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_59_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_59_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_59_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_59_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_59_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_59_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_59_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_59_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_59_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_59_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_59_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_59_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_59_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_59_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_59_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_59_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_59_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_59_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_59_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_59_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_59_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_59_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_59_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_59_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_59_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_59_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_59_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_59_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_59_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_59_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_59_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_59_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_59_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_59_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_59_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_59_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_59_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_60
+#define WAKE_AOWAKE_CNTRL_60                    MK_ADDR_CONST(0xf0)
+#define WAKE_AOWAKE_CNTRL_60_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_60_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_60_SCR                        EVENT_CNTRL_SCR_60
+#define WAKE_AOWAKE_CNTRL_60_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_60
+#define WAKE_AOWAKE_CNTRL_60_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_60_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_60_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_60_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_60_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_60_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_60_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_60_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_60_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_60_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_60_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_60_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_60_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_60_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_60_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_60_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_60_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_60_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_60_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_60_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_60_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_60_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_60_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_60_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_60_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_60_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_60_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_60_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_60_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_60_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_60_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_60_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_60_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_60_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_60_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_60_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_60_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_60_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_60_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_60_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_60_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_60_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_60_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_60_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_60_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_60_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_60_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_60_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_60_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_60_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_60_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_60_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_60_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_60_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_60_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_60_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_60_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_60_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_60_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_60_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_60_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_60_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_60_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_60_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_60_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_60_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_60_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_60_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_60_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_60_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_61
+#define WAKE_AOWAKE_CNTRL_61                    MK_ADDR_CONST(0xf4)
+#define WAKE_AOWAKE_CNTRL_61_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_61_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_61_SCR                        EVENT_CNTRL_SCR_61
+#define WAKE_AOWAKE_CNTRL_61_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_61
+#define WAKE_AOWAKE_CNTRL_61_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_61_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_61_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_61_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_61_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_61_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_61_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_61_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_61_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_61_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_61_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_61_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_61_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_61_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_61_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_61_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_61_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_61_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_61_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_61_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_61_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_61_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_61_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_61_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_61_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_61_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_61_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_61_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_61_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_61_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_61_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_61_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_61_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_61_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_61_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_61_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_61_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_61_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_61_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_61_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_61_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_61_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_61_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_61_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_61_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_61_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_61_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_61_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_61_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_61_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_61_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_61_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_61_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_61_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_61_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_61_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_61_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_61_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_61_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_61_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_61_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_61_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_61_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_61_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_61_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_61_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_61_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_61_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_61_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_61_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_62
+#define WAKE_AOWAKE_CNTRL_62                    MK_ADDR_CONST(0xf8)
+#define WAKE_AOWAKE_CNTRL_62_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_62_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_62_SCR                        EVENT_CNTRL_SCR_62
+#define WAKE_AOWAKE_CNTRL_62_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_62
+#define WAKE_AOWAKE_CNTRL_62_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_62_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_62_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_62_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_62_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_62_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_62_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_62_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_62_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_62_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_62_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_62_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_62_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_62_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_62_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_62_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_62_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_62_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_62_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_62_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_62_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_62_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_62_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_62_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_62_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_62_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_62_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_62_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_62_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_62_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_62_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_62_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_62_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_62_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_62_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_62_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_62_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_62_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_62_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_62_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_62_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_62_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_62_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_62_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_62_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_62_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_62_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_62_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_62_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_62_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_62_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_62_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_62_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_62_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_62_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_62_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_62_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_62_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_62_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_62_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_62_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_62_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_62_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_62_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_62_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_62_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_62_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_62_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_62_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_62_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_63
+#define WAKE_AOWAKE_CNTRL_63                    MK_ADDR_CONST(0xfc)
+#define WAKE_AOWAKE_CNTRL_63_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_63_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_63_SCR                        EVENT_CNTRL_SCR_63
+#define WAKE_AOWAKE_CNTRL_63_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_63
+#define WAKE_AOWAKE_CNTRL_63_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_63_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_63_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_63_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_63_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_63_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_63_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_63_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_63_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_63_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_63_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_63_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_63_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_63_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_63_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_63_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_63_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_63_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_63_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_63_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_63_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_63_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_63_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_63_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_63_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_63_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_63_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_63_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_63_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_63_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_63_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_63_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_63_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_63_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_63_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_63_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_63_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_63_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_63_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_63_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_63_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_63_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_63_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_63_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_63_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_63_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_63_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_63_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_63_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_63_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_63_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_63_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_63_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_63_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_63_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_63_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_63_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_63_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_63_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_63_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_63_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_63_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_63_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_63_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_63_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_63_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_63_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_63_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_63_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_63_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_64
+#define WAKE_AOWAKE_CNTRL_64                    MK_ADDR_CONST(0x100)
+#define WAKE_AOWAKE_CNTRL_64_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_64_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_64_SCR                        EVENT_CNTRL_SCR_64
+#define WAKE_AOWAKE_CNTRL_64_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_64
+#define WAKE_AOWAKE_CNTRL_64_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_64_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_64_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_64_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_64_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_64_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_64_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_64_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_64_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_64_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_64_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_64_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_64_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_64_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_64_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_64_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_64_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_64_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_64_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_64_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_64_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_64_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_64_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_64_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_64_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_64_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_64_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_64_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_64_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_64_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_64_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_64_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_64_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_64_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_64_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_64_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_64_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_64_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_64_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_64_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_64_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_64_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_64_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_64_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_64_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_64_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_64_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_64_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_64_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_64_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_64_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_64_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_64_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_64_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_64_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_64_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_64_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_64_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_64_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_64_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_64_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_64_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_64_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_64_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_64_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_64_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_64_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_64_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_64_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_64_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_65
+#define WAKE_AOWAKE_CNTRL_65                    MK_ADDR_CONST(0x104)
+#define WAKE_AOWAKE_CNTRL_65_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_65_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_65_SCR                        EVENT_CNTRL_SCR_65
+#define WAKE_AOWAKE_CNTRL_65_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_65
+#define WAKE_AOWAKE_CNTRL_65_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_65_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_65_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_65_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_65_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_65_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_65_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_65_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_65_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_65_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_65_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_65_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_65_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_65_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_65_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_65_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_65_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_65_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_65_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_65_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_65_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_65_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_65_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_65_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_65_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_65_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_65_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_65_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_65_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_65_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_65_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_65_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_65_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_65_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_65_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_65_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_65_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_65_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_65_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_65_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_65_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_65_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_65_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_65_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_65_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_65_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_65_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_65_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_65_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_65_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_65_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_65_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_65_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_65_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_65_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_65_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_65_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_65_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_65_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_65_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_65_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_65_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_65_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_65_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_65_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_65_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_65_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_65_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_65_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_65_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_66
+#define WAKE_AOWAKE_CNTRL_66                    MK_ADDR_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_66_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_66_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_66_SCR                        EVENT_CNTRL_SCR_66
+#define WAKE_AOWAKE_CNTRL_66_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_66
+#define WAKE_AOWAKE_CNTRL_66_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_66_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_66_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_66_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_66_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_66_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_66_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_66_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_66_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_66_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_66_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_66_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_66_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_66_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_66_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_66_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_66_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_66_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_66_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_66_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_66_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_66_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_66_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_66_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_66_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_66_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_66_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_66_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_66_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_66_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_66_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_66_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_66_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_66_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_66_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_66_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_66_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_66_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_66_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_66_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_66_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_66_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_66_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_66_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_66_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_66_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_66_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_66_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_66_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_66_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_66_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_66_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_66_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_66_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_66_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_66_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_66_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_66_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_66_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_66_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_66_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_66_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_66_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_66_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_66_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_66_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_66_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_66_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_66_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_66_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_67
+#define WAKE_AOWAKE_CNTRL_67                    MK_ADDR_CONST(0x10c)
+#define WAKE_AOWAKE_CNTRL_67_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_67_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_67_SCR                        EVENT_CNTRL_SCR_67
+#define WAKE_AOWAKE_CNTRL_67_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_67
+#define WAKE_AOWAKE_CNTRL_67_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_67_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_67_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_67_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_67_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_67_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_67_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_67_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_67_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_67_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_67_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_67_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_67_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_67_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_67_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_67_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_67_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_67_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_67_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_67_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_67_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_67_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_67_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_67_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_67_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_67_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_67_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_67_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_67_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_67_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_67_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_67_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_67_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_67_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_67_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_67_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_67_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_67_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_67_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_67_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_67_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_67_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_67_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_67_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_67_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_67_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_67_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_67_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_67_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_67_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_67_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_67_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_67_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_67_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_67_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_67_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_67_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_67_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_67_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_67_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_67_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_67_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_67_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_67_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_67_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_67_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_67_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_67_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_67_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_67_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_68
+#define WAKE_AOWAKE_CNTRL_68                    MK_ADDR_CONST(0x110)
+#define WAKE_AOWAKE_CNTRL_68_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_68_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_68_SCR                        EVENT_CNTRL_SCR_68
+#define WAKE_AOWAKE_CNTRL_68_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_68
+#define WAKE_AOWAKE_CNTRL_68_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_68_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_68_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_68_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_68_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_68_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_68_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_68_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_68_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_68_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_68_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_68_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_68_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_68_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_68_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_68_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_68_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_68_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_68_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_68_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_68_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_68_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_68_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_68_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_68_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_68_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_68_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_68_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_68_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_68_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_68_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_68_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_68_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_68_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_68_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_68_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_68_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_68_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_68_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_68_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_68_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_68_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_68_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_68_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_68_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_68_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_68_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_68_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_68_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_68_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_68_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_68_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_68_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_68_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_68_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_68_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_68_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_68_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_68_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_68_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_68_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_68_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_68_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_68_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_68_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_68_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_68_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_68_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_68_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_68_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_69
+#define WAKE_AOWAKE_CNTRL_69                    MK_ADDR_CONST(0x114)
+#define WAKE_AOWAKE_CNTRL_69_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_69_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_69_SCR                        EVENT_CNTRL_SCR_69
+#define WAKE_AOWAKE_CNTRL_69_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_69
+#define WAKE_AOWAKE_CNTRL_69_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_69_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_69_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_69_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_69_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_69_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_69_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_69_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_69_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_69_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_69_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_69_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_69_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_69_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_69_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_69_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_69_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_69_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_69_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_69_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_69_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_69_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_69_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_69_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_69_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_69_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_69_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_69_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_69_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_69_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_69_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_69_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_69_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_69_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_69_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_69_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_69_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_69_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_69_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_69_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_69_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_69_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_69_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_69_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_69_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_69_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_69_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_69_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_69_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_69_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_69_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_69_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_69_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_69_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_69_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_69_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_69_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_69_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_69_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_69_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_69_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_69_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_69_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_69_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_69_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_69_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_69_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_69_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_69_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_69_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_70
+#define WAKE_AOWAKE_CNTRL_70                    MK_ADDR_CONST(0x118)
+#define WAKE_AOWAKE_CNTRL_70_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_70_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_70_SCR                        EVENT_CNTRL_SCR_70
+#define WAKE_AOWAKE_CNTRL_70_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_70
+#define WAKE_AOWAKE_CNTRL_70_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_70_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_70_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_70_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_70_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_70_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_70_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_70_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_70_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_70_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_70_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_70_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_70_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_70_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_70_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_70_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_70_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_70_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_70_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_70_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_70_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_70_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_70_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_70_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_70_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_70_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_70_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_70_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_70_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_70_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_70_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_70_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_70_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_70_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_70_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_70_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_70_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_70_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_70_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_70_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_70_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_70_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_70_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_70_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_70_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_70_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_70_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_70_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_70_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_70_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_70_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_70_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_70_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_70_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_70_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_70_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_70_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_70_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_70_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_70_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_70_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_70_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_70_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_70_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_70_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_70_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_70_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_70_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_70_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_70_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_71
+#define WAKE_AOWAKE_CNTRL_71                    MK_ADDR_CONST(0x11c)
+#define WAKE_AOWAKE_CNTRL_71_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_71_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_71_SCR                        EVENT_CNTRL_SCR_71
+#define WAKE_AOWAKE_CNTRL_71_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_71
+#define WAKE_AOWAKE_CNTRL_71_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_71_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_71_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_71_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_71_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_71_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_71_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_71_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_71_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_71_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_71_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_71_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_71_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_71_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_71_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_71_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_71_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_71_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_71_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_71_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_71_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_71_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_71_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_71_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_71_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_71_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_71_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_71_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_71_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_71_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_71_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_71_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_71_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_71_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_71_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_71_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_71_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_71_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_71_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_71_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_71_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_71_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_71_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_71_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_71_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_71_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_71_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_71_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_71_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_71_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_71_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_71_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_71_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_71_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_71_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_71_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_71_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_71_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_71_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_71_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_71_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_71_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_71_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_71_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_71_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_71_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_71_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_71_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_71_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_71_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_72
+#define WAKE_AOWAKE_CNTRL_72                    MK_ADDR_CONST(0x120)
+#define WAKE_AOWAKE_CNTRL_72_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_72_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_72_SCR                        EVENT_CNTRL_SCR_72
+#define WAKE_AOWAKE_CNTRL_72_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_72
+#define WAKE_AOWAKE_CNTRL_72_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_72_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_72_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_72_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_72_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_72_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_72_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_72_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_72_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_72_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_72_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_72_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_72_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_72_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_72_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_72_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_72_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_72_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_72_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_72_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_72_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_72_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_72_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_72_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_72_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_72_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_72_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_72_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_72_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_72_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_72_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_72_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_72_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_72_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_72_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_72_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_72_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_72_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_72_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_72_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_72_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_72_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_72_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_72_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_72_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_72_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_72_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_72_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_72_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_72_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_72_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_72_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_72_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_72_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_72_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_72_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_72_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_72_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_72_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_72_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_72_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_72_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_72_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_72_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_72_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_72_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_72_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_72_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_72_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_72_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_73
+#define WAKE_AOWAKE_CNTRL_73                    MK_ADDR_CONST(0x124)
+#define WAKE_AOWAKE_CNTRL_73_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_73_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_73_SCR                        EVENT_CNTRL_SCR_73
+#define WAKE_AOWAKE_CNTRL_73_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_73
+#define WAKE_AOWAKE_CNTRL_73_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_73_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_73_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_73_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_73_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_73_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_73_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_73_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_73_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_73_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_73_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_73_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_73_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_73_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_73_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_73_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_73_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_73_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_73_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_73_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_73_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_73_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_73_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_73_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_73_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_73_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_73_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_73_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_73_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_73_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_73_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_73_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_73_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_73_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_73_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_73_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_73_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_73_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_73_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_73_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_73_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_73_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_73_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_73_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_73_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_73_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_73_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_73_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_73_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_73_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_73_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_73_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_73_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_73_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_73_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_73_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_73_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_73_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_73_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_73_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_73_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_73_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_73_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_73_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_73_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_73_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_73_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_73_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_73_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_73_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_74
+#define WAKE_AOWAKE_CNTRL_74                    MK_ADDR_CONST(0x128)
+#define WAKE_AOWAKE_CNTRL_74_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_74_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_74_SCR                        EVENT_CNTRL_SCR_74
+#define WAKE_AOWAKE_CNTRL_74_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_74
+#define WAKE_AOWAKE_CNTRL_74_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_74_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_74_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_74_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_74_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_74_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_74_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_74_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_74_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_74_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_74_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_74_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_74_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_74_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_74_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_74_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_74_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_74_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_74_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_74_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_74_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_74_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_74_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_74_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_74_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_74_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_74_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_74_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_74_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_74_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_74_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_74_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_74_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_74_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_74_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_74_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_74_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_74_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_74_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_74_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_74_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_74_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_74_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_74_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_74_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_74_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_74_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_74_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_74_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_74_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_74_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_74_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_74_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_74_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_74_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_74_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_74_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_74_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_74_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_74_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_74_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_74_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_74_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_74_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_74_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_74_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_74_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_74_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_74_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_74_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_75
+#define WAKE_AOWAKE_CNTRL_75                    MK_ADDR_CONST(0x12c)
+#define WAKE_AOWAKE_CNTRL_75_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_75_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_75_SCR                        EVENT_CNTRL_SCR_75
+#define WAKE_AOWAKE_CNTRL_75_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_75
+#define WAKE_AOWAKE_CNTRL_75_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_75_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_75_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_75_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_75_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_75_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_75_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_75_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_75_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_75_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_75_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_75_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_75_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_75_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_75_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_75_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_75_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_75_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_75_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_75_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_75_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_75_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_75_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_75_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_75_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_75_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_75_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_75_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_75_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_75_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_75_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_75_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_75_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_75_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_75_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_75_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_75_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_75_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_75_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_75_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_75_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_75_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_75_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_75_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_75_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_75_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_75_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_75_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_75_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_75_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_75_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_75_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_75_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_75_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_75_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_75_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_75_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_75_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_75_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_75_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_75_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_75_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_75_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_75_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_75_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_75_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_75_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_75_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_75_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_75_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_76
+#define WAKE_AOWAKE_CNTRL_76                    MK_ADDR_CONST(0x130)
+#define WAKE_AOWAKE_CNTRL_76_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_76_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_76_SCR                        EVENT_CNTRL_SCR_76
+#define WAKE_AOWAKE_CNTRL_76_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_76
+#define WAKE_AOWAKE_CNTRL_76_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_76_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_76_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_76_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_76_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_76_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_76_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_76_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_76_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_76_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_76_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_76_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_76_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_76_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_76_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_76_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_76_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_76_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_76_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_76_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_76_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_76_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_76_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_76_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_76_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_76_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_76_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_76_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_76_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_76_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_76_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_76_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_76_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_76_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_76_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_76_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_76_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_76_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_76_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_76_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_76_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_76_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_76_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_76_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_76_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_76_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_76_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_76_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_76_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_76_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_76_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_76_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_76_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_76_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_76_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_76_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_76_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_76_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_76_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_76_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_76_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_76_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_76_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_76_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_76_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_76_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_76_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_76_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_76_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_76_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_77
+#define WAKE_AOWAKE_CNTRL_77                    MK_ADDR_CONST(0x134)
+#define WAKE_AOWAKE_CNTRL_77_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_77_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_77_SCR                        EVENT_CNTRL_SCR_77
+#define WAKE_AOWAKE_CNTRL_77_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_77
+#define WAKE_AOWAKE_CNTRL_77_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_77_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_77_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_77_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_77_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_77_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_77_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_77_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_77_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_77_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_77_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_77_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_77_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_77_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_77_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_77_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_77_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_77_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_77_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_77_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_77_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_77_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_77_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_77_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_77_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_77_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_77_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_77_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_77_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_77_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_77_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_77_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_77_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_77_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_77_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_77_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_77_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_77_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_77_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_77_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_77_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_77_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_77_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_77_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_77_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_77_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_77_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_77_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_77_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_77_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_77_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_77_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_77_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_77_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_77_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_77_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_77_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_77_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_77_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_77_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_77_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_77_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_77_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_77_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_77_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_77_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_77_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_77_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_77_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_77_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_78
+#define WAKE_AOWAKE_CNTRL_78                    MK_ADDR_CONST(0x138)
+#define WAKE_AOWAKE_CNTRL_78_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_78_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_78_SCR                        EVENT_CNTRL_SCR_78
+#define WAKE_AOWAKE_CNTRL_78_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_78
+#define WAKE_AOWAKE_CNTRL_78_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_78_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_78_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_78_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_78_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_78_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_78_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_78_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_78_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_78_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_78_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_78_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_78_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_78_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_78_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_78_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_78_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_78_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_78_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_78_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_78_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_78_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_78_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_78_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_78_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_78_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_78_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_78_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_78_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_78_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_78_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_78_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_78_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_78_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_78_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_78_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_78_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_78_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_78_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_78_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_78_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_78_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_78_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_78_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_78_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_78_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_78_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_78_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_78_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_78_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_78_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_78_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_78_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_78_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_78_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_78_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_78_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_78_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_78_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_78_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_78_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_78_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_78_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_78_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_78_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_78_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_78_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_78_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_78_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_78_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_79
+#define WAKE_AOWAKE_CNTRL_79                    MK_ADDR_CONST(0x13c)
+#define WAKE_AOWAKE_CNTRL_79_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_79_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_79_SCR                        EVENT_CNTRL_SCR_79
+#define WAKE_AOWAKE_CNTRL_79_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_79
+#define WAKE_AOWAKE_CNTRL_79_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_79_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_79_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_79_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_79_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_79_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_79_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_79_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_79_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_79_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_79_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_79_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_79_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_79_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_79_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_79_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_79_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_79_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_79_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_79_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_79_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_79_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_79_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_79_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_79_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_79_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_79_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_79_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_79_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_79_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_79_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_79_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_79_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_79_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_79_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_79_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_79_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_79_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_79_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_79_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_79_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_79_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_79_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_79_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_79_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_79_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_79_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_79_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_79_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_79_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_79_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_79_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_79_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_79_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_79_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_79_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_79_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_79_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_79_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_79_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_79_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_79_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_79_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_79_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_79_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_79_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_79_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_79_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_79_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_79_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_80
+#define WAKE_AOWAKE_CNTRL_80                    MK_ADDR_CONST(0x140)
+#define WAKE_AOWAKE_CNTRL_80_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_80_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_80_SCR                        EVENT_CNTRL_SCR_80
+#define WAKE_AOWAKE_CNTRL_80_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_80
+#define WAKE_AOWAKE_CNTRL_80_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_80_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_80_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_80_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_80_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_80_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_80_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_80_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_80_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_80_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_80_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_80_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_80_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_80_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_80_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_80_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_80_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_80_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_80_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_80_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_80_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_80_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_80_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_80_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_80_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_80_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_80_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_80_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_80_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_80_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_80_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_80_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_80_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_80_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_80_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_80_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_80_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_80_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_80_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_80_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_80_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_80_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_80_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_80_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_80_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_80_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_80_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_80_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_80_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_80_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_80_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_80_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_80_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_80_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_80_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_80_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_80_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_80_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_80_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_80_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_80_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_80_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_80_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_80_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_80_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_80_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_80_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_80_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_80_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_80_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_81
+#define WAKE_AOWAKE_CNTRL_81                    MK_ADDR_CONST(0x144)
+#define WAKE_AOWAKE_CNTRL_81_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_81_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_81_SCR                        EVENT_CNTRL_SCR_81
+#define WAKE_AOWAKE_CNTRL_81_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_81
+#define WAKE_AOWAKE_CNTRL_81_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_81_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_81_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_81_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_81_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_81_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_81_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_81_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_81_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_81_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_81_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_81_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_81_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_81_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_81_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_81_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_81_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_81_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_81_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_81_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_81_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_81_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_81_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_81_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_81_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_81_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_81_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_81_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_81_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_81_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_81_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_81_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_81_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_81_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_81_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_81_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_81_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_81_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_81_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_81_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_81_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_81_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_81_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_81_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_81_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_81_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_81_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_81_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_81_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_81_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_81_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_81_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_81_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_81_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_81_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_81_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_81_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_81_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_81_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_81_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_81_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_81_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_81_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_81_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_81_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_81_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_81_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_81_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_81_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_81_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_82
+#define WAKE_AOWAKE_CNTRL_82                    MK_ADDR_CONST(0x148)
+#define WAKE_AOWAKE_CNTRL_82_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_82_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_82_SCR                        EVENT_CNTRL_SCR_82
+#define WAKE_AOWAKE_CNTRL_82_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_82
+#define WAKE_AOWAKE_CNTRL_82_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_82_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_82_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_82_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_82_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_82_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_82_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_82_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_82_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_82_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_82_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_82_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_82_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_82_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_82_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_82_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_82_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_82_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_82_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_82_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_82_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_82_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_82_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_82_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_82_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_82_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_82_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_82_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_82_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_82_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_82_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_82_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_82_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_82_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_82_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_82_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_82_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_82_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_82_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_82_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_82_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_82_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_82_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_82_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_82_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_82_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_82_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_82_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_82_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_82_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_82_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_82_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_82_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_82_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_82_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_82_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_82_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_82_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_82_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_82_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_82_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_82_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_82_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_82_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_82_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_82_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_82_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_82_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_82_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_82_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_83
+#define WAKE_AOWAKE_CNTRL_83                    MK_ADDR_CONST(0x14c)
+#define WAKE_AOWAKE_CNTRL_83_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_83_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_83_SCR                        EVENT_CNTRL_SCR_83
+#define WAKE_AOWAKE_CNTRL_83_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_83
+#define WAKE_AOWAKE_CNTRL_83_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_83_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_83_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_83_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_83_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_83_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_83_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_83_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_83_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_83_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_83_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_83_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_83_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_83_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_83_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_83_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_83_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_83_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_83_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_83_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_83_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_83_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_83_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_83_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_83_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_83_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_83_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_83_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_83_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_83_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_83_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_83_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_83_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_83_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_83_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_83_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_83_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_83_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_83_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_83_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_83_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_83_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_83_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_83_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_83_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_83_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_83_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_83_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_83_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_83_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_83_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_83_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_83_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_83_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_83_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_83_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_83_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_83_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_83_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_83_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_83_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_83_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_83_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_83_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_83_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_83_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_83_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_83_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_83_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_83_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_84
+#define WAKE_AOWAKE_CNTRL_84                    MK_ADDR_CONST(0x150)
+#define WAKE_AOWAKE_CNTRL_84_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_84_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_84_SCR                        EVENT_CNTRL_SCR_84
+#define WAKE_AOWAKE_CNTRL_84_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_84
+#define WAKE_AOWAKE_CNTRL_84_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_84_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_84_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_84_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_84_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_84_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_84_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_84_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_84_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_84_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_84_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_84_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_84_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_84_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_84_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_84_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_84_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_84_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_84_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_84_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_84_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_84_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_84_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_84_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_84_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_84_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_84_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_84_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_84_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_84_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_84_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_84_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_84_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_84_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_84_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_84_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_84_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_84_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_84_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_84_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_84_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_84_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_84_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_84_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_84_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_84_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_84_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_84_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_84_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_84_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_84_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_84_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_84_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_84_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_84_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_84_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_84_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_84_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_84_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_84_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_84_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_84_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_84_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_84_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_84_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_84_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_84_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_84_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_84_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_84_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_85
+#define WAKE_AOWAKE_CNTRL_85                    MK_ADDR_CONST(0x154)
+#define WAKE_AOWAKE_CNTRL_85_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_85_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_85_SCR                        EVENT_CNTRL_SCR_85
+#define WAKE_AOWAKE_CNTRL_85_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_85
+#define WAKE_AOWAKE_CNTRL_85_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_85_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_85_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_85_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_85_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_85_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_85_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_85_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_85_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_85_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_85_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_85_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_85_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_85_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_85_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_85_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_85_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_85_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_85_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_85_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_85_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_85_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_85_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_85_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_85_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_85_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_85_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_85_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_85_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_85_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_85_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_85_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_85_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_85_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_85_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_85_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_85_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_85_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_85_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_85_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_85_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_85_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_85_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_85_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_85_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_85_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_85_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_85_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_85_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_85_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_85_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_85_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_85_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_85_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_85_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_85_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_85_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_85_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_85_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_85_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_85_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_85_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_85_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_85_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_85_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_85_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_85_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_85_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_85_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_85_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_86
+#define WAKE_AOWAKE_CNTRL_86                    MK_ADDR_CONST(0x158)
+#define WAKE_AOWAKE_CNTRL_86_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_86_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_86_SCR                        EVENT_CNTRL_SCR_86
+#define WAKE_AOWAKE_CNTRL_86_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_86
+#define WAKE_AOWAKE_CNTRL_86_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_86_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_86_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_86_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_86_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_86_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_86_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_86_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_86_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_86_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_86_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_86_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_86_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_86_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_86_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_86_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_86_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_86_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_86_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_86_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_86_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_86_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_86_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_86_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_86_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_86_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_86_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_86_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_86_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_86_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_86_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_86_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_86_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_86_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_86_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_86_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_86_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_86_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_86_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_86_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_86_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_86_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_86_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_86_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_86_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_86_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_86_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_86_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_86_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_86_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_86_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_86_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_86_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_86_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_86_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_86_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_86_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_86_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_86_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_86_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_86_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_86_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_86_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_86_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_86_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_86_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_86_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_86_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_86_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_86_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_87
+#define WAKE_AOWAKE_CNTRL_87                    MK_ADDR_CONST(0x15c)
+#define WAKE_AOWAKE_CNTRL_87_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_87_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_87_SCR                        EVENT_CNTRL_SCR_87
+#define WAKE_AOWAKE_CNTRL_87_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_87
+#define WAKE_AOWAKE_CNTRL_87_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_87_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_87_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_87_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_87_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_87_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_87_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_87_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_87_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_87_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_87_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_87_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_87_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_87_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_87_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_87_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_87_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_87_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_87_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_87_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_87_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_87_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_87_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_87_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_87_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_87_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_87_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_87_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_87_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_87_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_87_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_87_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_87_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_87_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_87_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_87_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_87_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_87_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_87_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_87_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_87_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_87_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_87_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_87_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_87_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_87_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_87_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_87_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_87_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_87_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_87_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_87_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_87_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_87_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_87_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_87_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_87_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_87_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_87_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_87_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_87_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_87_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_87_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_87_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_87_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_87_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_87_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_87_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_87_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_87_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_88
+#define WAKE_AOWAKE_CNTRL_88                    MK_ADDR_CONST(0x160)
+#define WAKE_AOWAKE_CNTRL_88_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_88_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_88_SCR                        EVENT_CNTRL_SCR_88
+#define WAKE_AOWAKE_CNTRL_88_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_88
+#define WAKE_AOWAKE_CNTRL_88_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_88_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_88_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_88_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_88_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_88_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_88_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_88_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_88_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_88_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_88_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_88_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_88_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_88_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_88_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_88_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_88_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_88_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_88_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_88_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_88_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_88_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_88_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_88_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_88_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_88_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_88_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_88_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_88_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_88_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_88_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_88_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_88_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_88_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_88_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_88_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_88_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_88_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_88_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_88_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_88_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_88_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_88_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_88_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_88_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_88_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_88_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_88_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_88_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_88_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_88_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_88_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_88_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_88_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_88_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_88_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_88_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_88_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_88_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_88_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_88_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_88_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_88_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_88_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_88_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_88_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_88_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_88_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_88_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_88_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_89
+#define WAKE_AOWAKE_CNTRL_89                    MK_ADDR_CONST(0x164)
+#define WAKE_AOWAKE_CNTRL_89_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_89_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_89_SCR                        EVENT_CNTRL_SCR_89
+#define WAKE_AOWAKE_CNTRL_89_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_89
+#define WAKE_AOWAKE_CNTRL_89_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_89_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_89_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_89_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_89_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_89_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_89_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_89_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_89_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_89_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_89_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_89_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_89_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_89_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_89_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_89_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_89_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_89_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_89_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_89_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_89_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_89_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_89_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_89_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_89_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_89_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_89_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_89_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_89_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_89_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_89_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_89_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_89_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_89_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_89_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_89_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_89_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_89_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_89_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_89_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_89_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_89_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_89_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_89_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_89_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_89_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_89_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_89_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_89_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_89_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_89_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_89_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_89_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_89_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_89_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_89_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_89_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_89_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_89_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_89_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_89_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_89_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_89_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_89_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_89_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_89_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_89_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_89_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_89_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_89_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_90
+#define WAKE_AOWAKE_CNTRL_90                    MK_ADDR_CONST(0x168)
+#define WAKE_AOWAKE_CNTRL_90_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_90_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_90_SCR                        EVENT_CNTRL_SCR_90
+#define WAKE_AOWAKE_CNTRL_90_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_90
+#define WAKE_AOWAKE_CNTRL_90_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_90_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_90_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_90_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_90_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_90_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_90_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_90_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_90_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_90_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_90_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_90_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_90_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_90_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_90_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_90_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_90_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_90_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_90_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_90_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_90_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_90_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_90_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_90_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_90_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_90_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_90_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_90_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_90_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_90_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_90_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_90_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_90_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_90_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_90_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_90_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_90_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_90_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_90_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_90_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_90_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_90_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_90_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_90_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_90_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_90_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_90_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_90_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_90_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_90_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_90_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_90_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_90_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_90_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_90_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_90_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_90_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_90_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_90_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_90_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_90_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_90_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_90_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_90_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_90_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_90_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_90_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_90_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_90_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_90_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_91
+#define WAKE_AOWAKE_CNTRL_91                    MK_ADDR_CONST(0x16c)
+#define WAKE_AOWAKE_CNTRL_91_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_91_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_91_SCR                        EVENT_CNTRL_SCR_91
+#define WAKE_AOWAKE_CNTRL_91_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_91
+#define WAKE_AOWAKE_CNTRL_91_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_91_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_91_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_91_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_91_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_91_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_91_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_91_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_91_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_91_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_91_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_91_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_91_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_91_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_91_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_91_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_91_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_91_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_91_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_91_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_91_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_91_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_91_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_91_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_91_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_91_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_91_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_91_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_91_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_91_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_91_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_91_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_91_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_91_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_91_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_91_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_91_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_91_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_91_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_91_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_91_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_91_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_91_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_91_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_91_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_91_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_91_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_91_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_91_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_91_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_91_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_91_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_91_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_91_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_91_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_91_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_91_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_91_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_91_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_91_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_91_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_91_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_91_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_91_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_91_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_91_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_91_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_91_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_91_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_91_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_92
+#define WAKE_AOWAKE_CNTRL_92                    MK_ADDR_CONST(0x170)
+#define WAKE_AOWAKE_CNTRL_92_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_92_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_92_SCR                        EVENT_CNTRL_SCR_92
+#define WAKE_AOWAKE_CNTRL_92_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_92
+#define WAKE_AOWAKE_CNTRL_92_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_92_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_92_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_92_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_92_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_92_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_92_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_92_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_92_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_92_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_92_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_92_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_92_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_92_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_92_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_92_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_92_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_92_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_92_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_92_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_92_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_92_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_92_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_92_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_92_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_92_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_92_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_92_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_92_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_92_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_92_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_92_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_92_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_92_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_92_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_92_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_92_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_92_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_92_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_92_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_92_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_92_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_92_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_92_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_92_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_92_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_92_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_92_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_92_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_92_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_92_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_92_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_92_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_92_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_92_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_92_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_92_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_92_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_92_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_92_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_92_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_92_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_92_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_92_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_92_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_92_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_92_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_92_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_92_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_92_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_93
+#define WAKE_AOWAKE_CNTRL_93                    MK_ADDR_CONST(0x174)
+#define WAKE_AOWAKE_CNTRL_93_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_93_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_93_SCR                        EVENT_CNTRL_SCR_93
+#define WAKE_AOWAKE_CNTRL_93_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_93
+#define WAKE_AOWAKE_CNTRL_93_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_93_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_93_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_93_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_93_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_93_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_93_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_93_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_93_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_93_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_93_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_93_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_93_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_93_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_93_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_93_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_93_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_93_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_93_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_93_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_93_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_93_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_93_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_93_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_93_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_93_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_93_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_93_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_93_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_93_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_93_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_93_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_93_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_93_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_93_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_93_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_93_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_93_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_93_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_93_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_93_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_93_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_93_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_93_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_93_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_93_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_93_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_93_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_93_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_93_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_93_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_93_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_93_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_93_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_93_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_93_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_93_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_93_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_93_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_93_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_93_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_93_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_93_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_93_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_93_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_93_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_93_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_93_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_93_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_93_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_94
+#define WAKE_AOWAKE_CNTRL_94                    MK_ADDR_CONST(0x178)
+#define WAKE_AOWAKE_CNTRL_94_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_94_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_94_SCR                        EVENT_CNTRL_SCR_94
+#define WAKE_AOWAKE_CNTRL_94_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_94
+#define WAKE_AOWAKE_CNTRL_94_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_94_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_94_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_94_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_94_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_94_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_94_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_94_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_94_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_94_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_94_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_94_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_94_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_94_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_94_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_94_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_94_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_94_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_94_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_94_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_94_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_94_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_94_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_94_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_94_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_94_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_94_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_94_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_94_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_94_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_94_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_94_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_94_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_94_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_94_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_94_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_94_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_94_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_94_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_94_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_94_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_94_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_94_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_94_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_94_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_94_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_94_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_94_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_94_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_94_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_94_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_94_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_94_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_94_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_94_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_94_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_94_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_94_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_94_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_94_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_94_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_94_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_94_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_94_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_94_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_94_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_94_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_94_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_94_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_94_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CNTRL_95
+#define WAKE_AOWAKE_CNTRL_95                    MK_ADDR_CONST(0x17c)
+#define WAKE_AOWAKE_CNTRL_95_SECURE                     0x0
+#define WAKE_AOWAKE_CNTRL_95_DUAL                       0x0
+#define WAKE_AOWAKE_CNTRL_95_SCR                        EVENT_CNTRL_SCR_95
+#define WAKE_AOWAKE_CNTRL_95_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_95
+#define WAKE_AOWAKE_CNTRL_95_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_CNTRL_95_RESET_VAL                  MK_MASK_CONST(0x108)
+#define WAKE_AOWAKE_CNTRL_95_RESET_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_95_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_READ_MASK                  MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_95_WRITE_MASK                         MK_MASK_CONST(0xff6f)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_VAL_SHIFT                 MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_VAL_FIELD                 MK_FIELD_CONST(0xff, WAKE_AOWAKE_CNTRL_95_DEBOUNCE_VAL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_VAL_RANGE                 15:8
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_VAL_MSB                   MK_SHIFT_CONST(15)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_VAL_LSB                   MK_SHIFT_CONST(8)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_VAL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_VAL_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_VAL_DEFAULT_MASK                  MK_MASK_CONST(0xff)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_VAL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_VAL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_VAL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_VAL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+#define WAKE_AOWAKE_CNTRL_95_COAL_EN_SHIFT                      MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_95_COAL_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_95_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_95_COAL_EN_RANGE                      6:6
+#define WAKE_AOWAKE_CNTRL_95_COAL_EN_MSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_95_COAL_EN_LSB                        MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_CNTRL_95_COAL_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_95_COAL_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_COAL_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_95_COAL_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_COAL_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_COAL_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_COAL_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_95_COAL_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_95_COAL_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_95_COAL_EN_TRUE                       MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_95_COAL_GRP_SEL_SHIFT                 MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_95_COAL_GRP_SEL_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_95_COAL_GRP_SEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_95_COAL_GRP_SEL_RANGE                 5:5
+#define WAKE_AOWAKE_CNTRL_95_COAL_GRP_SEL_MSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_95_COAL_GRP_SEL_LSB                   MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_CNTRL_95_COAL_GRP_SEL_WOFFSET                       0x0
+#define WAKE_AOWAKE_CNTRL_95_COAL_GRP_SEL_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_COAL_GRP_SEL_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_95_COAL_GRP_SEL_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_COAL_GRP_SEL_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_COAL_GRP_SEL_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_COAL_GRP_SEL_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_95_COAL_GRP_SEL_INIT_ENUM                     GROUP0
+#define WAKE_AOWAKE_CNTRL_95_COAL_GRP_SEL_GROUP0                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_95_COAL_GRP_SEL_GROUP1                        MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_95_LEVEL_SHIFT                        MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_95_LEVEL_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_95_LEVEL_SHIFT)
+#define WAKE_AOWAKE_CNTRL_95_LEVEL_RANGE                        3:3
+#define WAKE_AOWAKE_CNTRL_95_LEVEL_MSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_95_LEVEL_LSB                  MK_SHIFT_CONST(3)
+#define WAKE_AOWAKE_CNTRL_95_LEVEL_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_95_LEVEL_DEFAULT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_95_LEVEL_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_95_LEVEL_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_LEVEL_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_LEVEL_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_LEVEL_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_95_LEVEL_INIT_ENUM                    HIGH
+#define WAKE_AOWAKE_CNTRL_95_LEVEL_LOW                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_95_LEVEL_HIGH                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_EN_SHIFT                  MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_EN_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_95_DEBOUNCE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_EN_RANGE                  2:2
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_EN_MSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_EN_LSB                    MK_SHIFT_CONST(2)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_EN_WOFFSET                        0x0
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_EN_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_EN_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_EN_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_EN_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_EN_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_EN_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_EN_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_EN_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_95_DEBOUNCE_EN_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_95_SR_CAPTURE_EN_SHIFT                        MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_95_SR_CAPTURE_EN_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_95_SR_CAPTURE_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_95_SR_CAPTURE_EN_RANGE                        1:1
+#define WAKE_AOWAKE_CNTRL_95_SR_CAPTURE_EN_MSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_95_SR_CAPTURE_EN_LSB                  MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CNTRL_95_SR_CAPTURE_EN_WOFFSET                      0x0
+#define WAKE_AOWAKE_CNTRL_95_SR_CAPTURE_EN_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_SR_CAPTURE_EN_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_95_SR_CAPTURE_EN_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_SR_CAPTURE_EN_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_SR_CAPTURE_EN_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_SR_CAPTURE_EN_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_95_SR_CAPTURE_EN_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_CNTRL_95_SR_CAPTURE_EN_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_95_SR_CAPTURE_EN_TRUE                 MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CNTRL_95_DELAY_FILTER_EN_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_95_DELAY_FILTER_EN_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_CNTRL_95_DELAY_FILTER_EN_SHIFT)
+#define WAKE_AOWAKE_CNTRL_95_DELAY_FILTER_EN_RANGE                      0:0
+#define WAKE_AOWAKE_CNTRL_95_DELAY_FILTER_EN_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_95_DELAY_FILTER_EN_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CNTRL_95_DELAY_FILTER_EN_WOFFSET                    0x0
+#define WAKE_AOWAKE_CNTRL_95_DELAY_FILTER_EN_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_DELAY_FILTER_EN_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_95_DELAY_FILTER_EN_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_DELAY_FILTER_EN_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_DELAY_FILTER_EN_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CNTRL_95_DELAY_FILTER_EN_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CNTRL_95_DELAY_FILTER_EN_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_CNTRL_95_DELAY_FILTER_EN_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CNTRL_95_DELAY_FILTER_EN_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_0
+#define WAKE_AOWAKE_MASK_W_0                    MK_ADDR_CONST(0x180)
+#define WAKE_AOWAKE_MASK_W_0_SECURE                     0x0
+#define WAKE_AOWAKE_MASK_W_0_DUAL                       0x0
+#define WAKE_AOWAKE_MASK_W_0_SCR                        EVENT_CNTRL_SCR_0
+#define WAKE_AOWAKE_MASK_W_0_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_0
+#define WAKE_AOWAKE_MASK_W_0_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_MASK_W_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_0_READ_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_0_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_0_MASK_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_0_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_0_MASK_RANGE                 0:0
+#define WAKE_AOWAKE_MASK_W_0_MASK_MSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_0_MASK_LSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_0_MASK_WOFFSET                       0x0
+#define WAKE_AOWAKE_MASK_W_0_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_0_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_0_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_0_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_0_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_0_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_0_MASK_INIT_ENUM                     MASK
+#define WAKE_AOWAKE_MASK_W_0_MASK_MASK                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_0_MASK_UNMASK                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W
+#define WAKE_AOWAKE_MASK_W                      MK_ADDR_CONST(0x180)
+#define WAKE_AOWAKE_MASK_W_SECURE                       0x0
+#define WAKE_AOWAKE_MASK_W_DUAL                         0x0
+#define WAKE_AOWAKE_MASK_W_SCR                  EVENT_CNTRL_SCR_0
+#define WAKE_AOWAKE_MASK_W_SCRREG                       WAKE_SCR_EVENT_CNTRL_SCR_0
+#define WAKE_AOWAKE_MASK_W_WORD_COUNT                   0x1
+#define WAKE_AOWAKE_MASK_W_RESET_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_RESET_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_READ_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_WRITE_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_MASK_SHIFT                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_MASK_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_MASK_RANGE                   0:0
+#define WAKE_AOWAKE_MASK_W_MASK_MSB                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_MASK_LSB                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_MASK_WOFFSET                 0x0
+#define WAKE_AOWAKE_MASK_W_MASK_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_MASK_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_MASK_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_MASK_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_MASK_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_MASK_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_MASK_INIT_ENUM                       MASK
+#define WAKE_AOWAKE_MASK_W_MASK_MASK                    MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_MASK_UNMASK                  MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_1
+#define WAKE_AOWAKE_MASK_W_1                    MK_ADDR_CONST(0x184)
+#define WAKE_AOWAKE_MASK_W_1_SECURE                     0x0
+#define WAKE_AOWAKE_MASK_W_1_DUAL                       0x0
+#define WAKE_AOWAKE_MASK_W_1_SCR                        EVENT_CNTRL_SCR_1
+#define WAKE_AOWAKE_MASK_W_1_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_1
+#define WAKE_AOWAKE_MASK_W_1_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_MASK_W_1_RESET_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_1_RESET_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_1_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_1_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_1_READ_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_1_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_1_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_1_MASK_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_1_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_1_MASK_RANGE                 0:0
+#define WAKE_AOWAKE_MASK_W_1_MASK_MSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_1_MASK_LSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_1_MASK_WOFFSET                       0x0
+#define WAKE_AOWAKE_MASK_W_1_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_1_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_1_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_1_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_1_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_1_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_1_MASK_INIT_ENUM                     MASK
+#define WAKE_AOWAKE_MASK_W_1_MASK_MASK                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_1_MASK_UNMASK                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_2
+#define WAKE_AOWAKE_MASK_W_2                    MK_ADDR_CONST(0x188)
+#define WAKE_AOWAKE_MASK_W_2_SECURE                     0x0
+#define WAKE_AOWAKE_MASK_W_2_DUAL                       0x0
+#define WAKE_AOWAKE_MASK_W_2_SCR                        EVENT_CNTRL_SCR_2
+#define WAKE_AOWAKE_MASK_W_2_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_2
+#define WAKE_AOWAKE_MASK_W_2_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_MASK_W_2_RESET_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_2_RESET_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_2_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_2_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_2_READ_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_2_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_2_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_2_MASK_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_2_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_2_MASK_RANGE                 0:0
+#define WAKE_AOWAKE_MASK_W_2_MASK_MSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_2_MASK_LSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_2_MASK_WOFFSET                       0x0
+#define WAKE_AOWAKE_MASK_W_2_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_2_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_2_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_2_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_2_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_2_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_2_MASK_INIT_ENUM                     MASK
+#define WAKE_AOWAKE_MASK_W_2_MASK_MASK                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_2_MASK_UNMASK                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_3
+#define WAKE_AOWAKE_MASK_W_3                    MK_ADDR_CONST(0x18c)
+#define WAKE_AOWAKE_MASK_W_3_SECURE                     0x0
+#define WAKE_AOWAKE_MASK_W_3_DUAL                       0x0
+#define WAKE_AOWAKE_MASK_W_3_SCR                        EVENT_CNTRL_SCR_3
+#define WAKE_AOWAKE_MASK_W_3_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_3
+#define WAKE_AOWAKE_MASK_W_3_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_MASK_W_3_RESET_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_3_RESET_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_3_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_3_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_3_READ_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_3_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_3_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_3_MASK_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_3_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_3_MASK_RANGE                 0:0
+#define WAKE_AOWAKE_MASK_W_3_MASK_MSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_3_MASK_LSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_3_MASK_WOFFSET                       0x0
+#define WAKE_AOWAKE_MASK_W_3_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_3_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_3_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_3_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_3_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_3_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_3_MASK_INIT_ENUM                     MASK
+#define WAKE_AOWAKE_MASK_W_3_MASK_MASK                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_3_MASK_UNMASK                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_4
+#define WAKE_AOWAKE_MASK_W_4                    MK_ADDR_CONST(0x190)
+#define WAKE_AOWAKE_MASK_W_4_SECURE                     0x0
+#define WAKE_AOWAKE_MASK_W_4_DUAL                       0x0
+#define WAKE_AOWAKE_MASK_W_4_SCR                        EVENT_CNTRL_SCR_4
+#define WAKE_AOWAKE_MASK_W_4_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_4
+#define WAKE_AOWAKE_MASK_W_4_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_MASK_W_4_RESET_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_4_RESET_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_4_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_4_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_4_READ_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_4_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_4_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_4_MASK_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_4_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_4_MASK_RANGE                 0:0
+#define WAKE_AOWAKE_MASK_W_4_MASK_MSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_4_MASK_LSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_4_MASK_WOFFSET                       0x0
+#define WAKE_AOWAKE_MASK_W_4_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_4_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_4_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_4_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_4_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_4_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_4_MASK_INIT_ENUM                     MASK
+#define WAKE_AOWAKE_MASK_W_4_MASK_MASK                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_4_MASK_UNMASK                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_5
+#define WAKE_AOWAKE_MASK_W_5                    MK_ADDR_CONST(0x194)
+#define WAKE_AOWAKE_MASK_W_5_SECURE                     0x0
+#define WAKE_AOWAKE_MASK_W_5_DUAL                       0x0
+#define WAKE_AOWAKE_MASK_W_5_SCR                        EVENT_CNTRL_SCR_5
+#define WAKE_AOWAKE_MASK_W_5_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_5
+#define WAKE_AOWAKE_MASK_W_5_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_MASK_W_5_RESET_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_5_RESET_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_5_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_5_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_5_READ_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_5_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_5_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_5_MASK_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_5_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_5_MASK_RANGE                 0:0
+#define WAKE_AOWAKE_MASK_W_5_MASK_MSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_5_MASK_LSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_5_MASK_WOFFSET                       0x0
+#define WAKE_AOWAKE_MASK_W_5_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_5_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_5_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_5_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_5_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_5_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_5_MASK_INIT_ENUM                     MASK
+#define WAKE_AOWAKE_MASK_W_5_MASK_MASK                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_5_MASK_UNMASK                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_6
+#define WAKE_AOWAKE_MASK_W_6                    MK_ADDR_CONST(0x198)
+#define WAKE_AOWAKE_MASK_W_6_SECURE                     0x0
+#define WAKE_AOWAKE_MASK_W_6_DUAL                       0x0
+#define WAKE_AOWAKE_MASK_W_6_SCR                        EVENT_CNTRL_SCR_6
+#define WAKE_AOWAKE_MASK_W_6_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_6
+#define WAKE_AOWAKE_MASK_W_6_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_MASK_W_6_RESET_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_6_RESET_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_6_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_6_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_6_READ_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_6_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_6_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_6_MASK_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_6_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_6_MASK_RANGE                 0:0
+#define WAKE_AOWAKE_MASK_W_6_MASK_MSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_6_MASK_LSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_6_MASK_WOFFSET                       0x0
+#define WAKE_AOWAKE_MASK_W_6_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_6_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_6_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_6_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_6_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_6_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_6_MASK_INIT_ENUM                     MASK
+#define WAKE_AOWAKE_MASK_W_6_MASK_MASK                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_6_MASK_UNMASK                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_7
+#define WAKE_AOWAKE_MASK_W_7                    MK_ADDR_CONST(0x19c)
+#define WAKE_AOWAKE_MASK_W_7_SECURE                     0x0
+#define WAKE_AOWAKE_MASK_W_7_DUAL                       0x0
+#define WAKE_AOWAKE_MASK_W_7_SCR                        EVENT_CNTRL_SCR_7
+#define WAKE_AOWAKE_MASK_W_7_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_7
+#define WAKE_AOWAKE_MASK_W_7_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_MASK_W_7_RESET_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_7_RESET_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_7_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_7_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_7_READ_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_7_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_7_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_7_MASK_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_7_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_7_MASK_RANGE                 0:0
+#define WAKE_AOWAKE_MASK_W_7_MASK_MSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_7_MASK_LSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_7_MASK_WOFFSET                       0x0
+#define WAKE_AOWAKE_MASK_W_7_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_7_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_7_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_7_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_7_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_7_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_7_MASK_INIT_ENUM                     MASK
+#define WAKE_AOWAKE_MASK_W_7_MASK_MASK                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_7_MASK_UNMASK                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_8
+#define WAKE_AOWAKE_MASK_W_8                    MK_ADDR_CONST(0x1a0)
+#define WAKE_AOWAKE_MASK_W_8_SECURE                     0x0
+#define WAKE_AOWAKE_MASK_W_8_DUAL                       0x0
+#define WAKE_AOWAKE_MASK_W_8_SCR                        EVENT_CNTRL_SCR_8
+#define WAKE_AOWAKE_MASK_W_8_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_8
+#define WAKE_AOWAKE_MASK_W_8_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_MASK_W_8_RESET_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_8_RESET_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_8_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_8_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_8_READ_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_8_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_8_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_8_MASK_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_8_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_8_MASK_RANGE                 0:0
+#define WAKE_AOWAKE_MASK_W_8_MASK_MSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_8_MASK_LSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_8_MASK_WOFFSET                       0x0
+#define WAKE_AOWAKE_MASK_W_8_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_8_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_8_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_8_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_8_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_8_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_8_MASK_INIT_ENUM                     MASK
+#define WAKE_AOWAKE_MASK_W_8_MASK_MASK                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_8_MASK_UNMASK                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_9
+#define WAKE_AOWAKE_MASK_W_9                    MK_ADDR_CONST(0x1a4)
+#define WAKE_AOWAKE_MASK_W_9_SECURE                     0x0
+#define WAKE_AOWAKE_MASK_W_9_DUAL                       0x0
+#define WAKE_AOWAKE_MASK_W_9_SCR                        EVENT_CNTRL_SCR_9
+#define WAKE_AOWAKE_MASK_W_9_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_9
+#define WAKE_AOWAKE_MASK_W_9_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_MASK_W_9_RESET_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_9_RESET_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_9_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_9_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_9_READ_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_9_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_9_MASK_SHIFT                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_9_MASK_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_9_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_9_MASK_RANGE                 0:0
+#define WAKE_AOWAKE_MASK_W_9_MASK_MSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_9_MASK_LSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_9_MASK_WOFFSET                       0x0
+#define WAKE_AOWAKE_MASK_W_9_MASK_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_9_MASK_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_9_MASK_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_9_MASK_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_9_MASK_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_9_MASK_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_9_MASK_INIT_ENUM                     MASK
+#define WAKE_AOWAKE_MASK_W_9_MASK_MASK                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_9_MASK_UNMASK                        MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_10
+#define WAKE_AOWAKE_MASK_W_10                   MK_ADDR_CONST(0x1a8)
+#define WAKE_AOWAKE_MASK_W_10_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_10_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_10_SCR                       EVENT_CNTRL_SCR_10
+#define WAKE_AOWAKE_MASK_W_10_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_10
+#define WAKE_AOWAKE_MASK_W_10_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_10_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_10_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_10_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_10_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_10_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_10_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_10_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_10_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_10_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_10_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_10_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_10_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_10_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_10_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_10_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_10_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_10_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_10_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_10_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_10_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_10_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_10_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_11
+#define WAKE_AOWAKE_MASK_W_11                   MK_ADDR_CONST(0x1ac)
+#define WAKE_AOWAKE_MASK_W_11_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_11_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_11_SCR                       EVENT_CNTRL_SCR_11
+#define WAKE_AOWAKE_MASK_W_11_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_11
+#define WAKE_AOWAKE_MASK_W_11_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_11_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_11_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_11_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_11_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_11_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_11_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_11_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_11_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_11_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_11_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_11_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_11_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_11_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_11_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_11_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_11_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_11_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_11_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_11_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_11_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_11_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_11_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_12
+#define WAKE_AOWAKE_MASK_W_12                   MK_ADDR_CONST(0x1b0)
+#define WAKE_AOWAKE_MASK_W_12_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_12_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_12_SCR                       EVENT_CNTRL_SCR_12
+#define WAKE_AOWAKE_MASK_W_12_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_12
+#define WAKE_AOWAKE_MASK_W_12_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_12_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_12_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_12_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_12_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_12_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_12_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_12_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_12_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_12_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_12_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_12_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_12_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_12_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_12_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_12_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_12_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_12_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_12_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_12_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_12_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_12_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_12_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_13
+#define WAKE_AOWAKE_MASK_W_13                   MK_ADDR_CONST(0x1b4)
+#define WAKE_AOWAKE_MASK_W_13_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_13_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_13_SCR                       EVENT_CNTRL_SCR_13
+#define WAKE_AOWAKE_MASK_W_13_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_13
+#define WAKE_AOWAKE_MASK_W_13_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_13_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_13_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_13_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_13_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_13_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_13_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_13_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_13_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_13_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_13_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_13_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_13_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_13_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_13_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_13_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_13_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_13_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_13_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_13_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_13_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_13_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_13_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_14
+#define WAKE_AOWAKE_MASK_W_14                   MK_ADDR_CONST(0x1b8)
+#define WAKE_AOWAKE_MASK_W_14_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_14_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_14_SCR                       EVENT_CNTRL_SCR_14
+#define WAKE_AOWAKE_MASK_W_14_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_14
+#define WAKE_AOWAKE_MASK_W_14_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_14_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_14_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_14_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_14_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_14_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_14_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_14_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_14_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_14_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_14_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_14_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_14_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_14_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_14_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_14_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_14_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_14_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_14_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_14_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_14_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_14_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_14_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_15
+#define WAKE_AOWAKE_MASK_W_15                   MK_ADDR_CONST(0x1bc)
+#define WAKE_AOWAKE_MASK_W_15_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_15_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_15_SCR                       EVENT_CNTRL_SCR_15
+#define WAKE_AOWAKE_MASK_W_15_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_15
+#define WAKE_AOWAKE_MASK_W_15_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_15_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_15_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_15_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_15_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_15_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_15_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_15_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_15_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_15_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_15_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_15_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_15_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_15_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_15_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_15_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_15_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_15_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_15_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_15_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_15_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_15_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_15_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_16
+#define WAKE_AOWAKE_MASK_W_16                   MK_ADDR_CONST(0x1c0)
+#define WAKE_AOWAKE_MASK_W_16_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_16_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_16_SCR                       EVENT_CNTRL_SCR_16
+#define WAKE_AOWAKE_MASK_W_16_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_16
+#define WAKE_AOWAKE_MASK_W_16_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_16_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_16_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_16_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_16_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_16_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_16_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_16_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_16_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_16_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_16_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_16_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_16_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_16_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_16_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_16_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_16_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_16_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_16_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_16_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_16_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_16_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_16_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_17
+#define WAKE_AOWAKE_MASK_W_17                   MK_ADDR_CONST(0x1c4)
+#define WAKE_AOWAKE_MASK_W_17_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_17_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_17_SCR                       EVENT_CNTRL_SCR_17
+#define WAKE_AOWAKE_MASK_W_17_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_17
+#define WAKE_AOWAKE_MASK_W_17_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_17_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_17_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_17_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_17_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_17_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_17_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_17_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_17_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_17_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_17_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_17_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_17_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_17_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_17_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_17_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_17_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_17_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_17_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_17_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_17_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_17_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_17_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_18
+#define WAKE_AOWAKE_MASK_W_18                   MK_ADDR_CONST(0x1c8)
+#define WAKE_AOWAKE_MASK_W_18_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_18_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_18_SCR                       EVENT_CNTRL_SCR_18
+#define WAKE_AOWAKE_MASK_W_18_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_18
+#define WAKE_AOWAKE_MASK_W_18_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_18_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_18_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_18_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_18_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_18_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_18_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_18_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_18_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_18_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_18_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_18_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_18_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_18_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_18_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_18_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_18_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_18_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_18_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_18_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_18_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_18_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_18_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_19
+#define WAKE_AOWAKE_MASK_W_19                   MK_ADDR_CONST(0x1cc)
+#define WAKE_AOWAKE_MASK_W_19_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_19_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_19_SCR                       EVENT_CNTRL_SCR_19
+#define WAKE_AOWAKE_MASK_W_19_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_19
+#define WAKE_AOWAKE_MASK_W_19_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_19_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_19_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_19_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_19_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_19_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_19_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_19_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_19_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_19_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_19_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_19_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_19_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_19_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_19_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_19_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_19_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_19_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_19_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_19_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_19_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_19_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_19_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_20
+#define WAKE_AOWAKE_MASK_W_20                   MK_ADDR_CONST(0x1d0)
+#define WAKE_AOWAKE_MASK_W_20_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_20_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_20_SCR                       EVENT_CNTRL_SCR_20
+#define WAKE_AOWAKE_MASK_W_20_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_20
+#define WAKE_AOWAKE_MASK_W_20_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_20_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_20_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_20_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_20_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_20_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_20_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_20_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_20_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_20_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_20_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_20_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_20_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_20_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_20_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_20_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_20_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_20_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_20_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_20_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_20_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_20_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_20_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_21
+#define WAKE_AOWAKE_MASK_W_21                   MK_ADDR_CONST(0x1d4)
+#define WAKE_AOWAKE_MASK_W_21_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_21_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_21_SCR                       EVENT_CNTRL_SCR_21
+#define WAKE_AOWAKE_MASK_W_21_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_21
+#define WAKE_AOWAKE_MASK_W_21_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_21_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_21_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_21_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_21_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_21_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_21_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_21_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_21_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_21_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_21_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_21_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_21_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_21_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_21_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_21_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_21_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_21_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_21_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_21_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_21_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_21_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_21_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_22
+#define WAKE_AOWAKE_MASK_W_22                   MK_ADDR_CONST(0x1d8)
+#define WAKE_AOWAKE_MASK_W_22_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_22_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_22_SCR                       EVENT_CNTRL_SCR_22
+#define WAKE_AOWAKE_MASK_W_22_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_22
+#define WAKE_AOWAKE_MASK_W_22_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_22_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_22_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_22_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_22_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_22_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_22_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_22_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_22_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_22_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_22_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_22_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_22_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_22_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_22_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_22_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_22_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_22_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_22_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_22_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_22_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_22_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_22_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_23
+#define WAKE_AOWAKE_MASK_W_23                   MK_ADDR_CONST(0x1dc)
+#define WAKE_AOWAKE_MASK_W_23_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_23_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_23_SCR                       EVENT_CNTRL_SCR_23
+#define WAKE_AOWAKE_MASK_W_23_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_23
+#define WAKE_AOWAKE_MASK_W_23_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_23_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_23_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_23_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_23_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_23_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_23_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_23_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_23_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_23_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_23_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_23_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_23_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_23_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_23_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_23_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_23_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_23_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_23_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_23_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_23_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_23_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_23_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_24
+#define WAKE_AOWAKE_MASK_W_24                   MK_ADDR_CONST(0x1e0)
+#define WAKE_AOWAKE_MASK_W_24_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_24_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_24_SCR                       EVENT_CNTRL_SCR_24
+#define WAKE_AOWAKE_MASK_W_24_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_24
+#define WAKE_AOWAKE_MASK_W_24_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_24_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_24_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_24_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_24_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_24_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_24_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_24_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_24_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_24_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_24_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_24_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_24_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_24_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_24_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_24_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_24_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_24_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_24_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_24_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_24_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_24_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_24_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_25
+#define WAKE_AOWAKE_MASK_W_25                   MK_ADDR_CONST(0x1e4)
+#define WAKE_AOWAKE_MASK_W_25_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_25_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_25_SCR                       EVENT_CNTRL_SCR_25
+#define WAKE_AOWAKE_MASK_W_25_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_25
+#define WAKE_AOWAKE_MASK_W_25_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_25_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_25_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_25_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_25_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_25_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_25_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_25_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_25_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_25_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_25_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_25_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_25_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_25_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_25_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_25_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_25_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_25_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_25_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_25_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_25_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_25_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_25_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_26
+#define WAKE_AOWAKE_MASK_W_26                   MK_ADDR_CONST(0x1e8)
+#define WAKE_AOWAKE_MASK_W_26_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_26_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_26_SCR                       EVENT_CNTRL_SCR_26
+#define WAKE_AOWAKE_MASK_W_26_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_26
+#define WAKE_AOWAKE_MASK_W_26_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_26_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_26_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_26_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_26_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_26_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_26_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_26_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_26_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_26_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_26_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_26_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_26_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_26_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_26_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_26_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_26_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_26_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_26_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_26_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_26_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_26_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_26_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_27
+#define WAKE_AOWAKE_MASK_W_27                   MK_ADDR_CONST(0x1ec)
+#define WAKE_AOWAKE_MASK_W_27_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_27_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_27_SCR                       EVENT_CNTRL_SCR_27
+#define WAKE_AOWAKE_MASK_W_27_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_27
+#define WAKE_AOWAKE_MASK_W_27_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_27_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_27_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_27_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_27_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_27_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_27_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_27_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_27_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_27_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_27_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_27_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_27_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_27_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_27_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_27_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_27_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_27_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_27_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_27_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_27_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_27_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_27_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_28
+#define WAKE_AOWAKE_MASK_W_28                   MK_ADDR_CONST(0x1f0)
+#define WAKE_AOWAKE_MASK_W_28_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_28_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_28_SCR                       EVENT_CNTRL_SCR_28
+#define WAKE_AOWAKE_MASK_W_28_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_28
+#define WAKE_AOWAKE_MASK_W_28_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_28_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_28_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_28_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_28_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_28_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_28_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_28_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_28_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_28_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_28_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_28_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_28_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_28_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_28_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_28_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_28_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_28_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_28_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_28_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_28_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_28_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_28_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_29
+#define WAKE_AOWAKE_MASK_W_29                   MK_ADDR_CONST(0x1f4)
+#define WAKE_AOWAKE_MASK_W_29_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_29_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_29_SCR                       EVENT_CNTRL_SCR_29
+#define WAKE_AOWAKE_MASK_W_29_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_29
+#define WAKE_AOWAKE_MASK_W_29_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_29_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_29_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_29_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_29_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_29_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_29_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_29_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_29_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_29_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_29_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_29_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_29_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_29_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_29_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_29_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_29_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_29_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_29_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_29_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_29_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_29_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_29_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_30
+#define WAKE_AOWAKE_MASK_W_30                   MK_ADDR_CONST(0x1f8)
+#define WAKE_AOWAKE_MASK_W_30_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_30_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_30_SCR                       EVENT_CNTRL_SCR_30
+#define WAKE_AOWAKE_MASK_W_30_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_30
+#define WAKE_AOWAKE_MASK_W_30_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_30_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_30_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_30_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_30_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_30_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_30_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_30_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_30_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_30_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_30_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_30_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_30_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_30_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_30_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_30_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_30_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_30_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_30_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_30_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_30_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_30_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_30_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_31
+#define WAKE_AOWAKE_MASK_W_31                   MK_ADDR_CONST(0x1fc)
+#define WAKE_AOWAKE_MASK_W_31_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_31_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_31_SCR                       EVENT_CNTRL_SCR_31
+#define WAKE_AOWAKE_MASK_W_31_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_31
+#define WAKE_AOWAKE_MASK_W_31_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_31_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_31_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_31_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_31_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_31_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_31_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_31_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_31_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_31_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_31_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_31_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_31_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_31_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_31_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_31_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_31_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_31_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_31_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_31_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_31_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_31_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_31_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_32
+#define WAKE_AOWAKE_MASK_W_32                   MK_ADDR_CONST(0x200)
+#define WAKE_AOWAKE_MASK_W_32_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_32_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_32_SCR                       EVENT_CNTRL_SCR_32
+#define WAKE_AOWAKE_MASK_W_32_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_32
+#define WAKE_AOWAKE_MASK_W_32_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_32_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_32_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_32_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_32_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_32_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_32_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_32_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_32_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_32_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_32_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_32_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_32_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_32_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_32_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_32_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_32_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_32_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_32_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_32_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_32_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_32_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_32_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_33
+#define WAKE_AOWAKE_MASK_W_33                   MK_ADDR_CONST(0x204)
+#define WAKE_AOWAKE_MASK_W_33_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_33_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_33_SCR                       EVENT_CNTRL_SCR_33
+#define WAKE_AOWAKE_MASK_W_33_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_33
+#define WAKE_AOWAKE_MASK_W_33_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_33_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_33_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_33_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_33_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_33_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_33_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_33_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_33_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_33_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_33_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_33_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_33_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_33_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_33_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_33_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_33_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_33_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_33_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_33_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_33_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_33_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_33_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_34
+#define WAKE_AOWAKE_MASK_W_34                   MK_ADDR_CONST(0x208)
+#define WAKE_AOWAKE_MASK_W_34_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_34_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_34_SCR                       EVENT_CNTRL_SCR_34
+#define WAKE_AOWAKE_MASK_W_34_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_34
+#define WAKE_AOWAKE_MASK_W_34_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_34_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_34_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_34_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_34_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_34_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_34_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_34_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_34_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_34_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_34_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_34_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_34_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_34_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_34_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_34_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_34_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_34_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_34_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_34_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_34_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_34_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_34_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_35
+#define WAKE_AOWAKE_MASK_W_35                   MK_ADDR_CONST(0x20c)
+#define WAKE_AOWAKE_MASK_W_35_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_35_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_35_SCR                       EVENT_CNTRL_SCR_35
+#define WAKE_AOWAKE_MASK_W_35_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_35
+#define WAKE_AOWAKE_MASK_W_35_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_35_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_35_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_35_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_35_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_35_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_35_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_35_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_35_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_35_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_35_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_35_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_35_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_35_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_35_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_35_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_35_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_35_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_35_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_35_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_35_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_35_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_35_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_36
+#define WAKE_AOWAKE_MASK_W_36                   MK_ADDR_CONST(0x210)
+#define WAKE_AOWAKE_MASK_W_36_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_36_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_36_SCR                       EVENT_CNTRL_SCR_36
+#define WAKE_AOWAKE_MASK_W_36_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_36
+#define WAKE_AOWAKE_MASK_W_36_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_36_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_36_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_36_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_36_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_36_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_36_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_36_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_36_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_36_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_36_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_36_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_36_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_36_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_36_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_36_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_36_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_36_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_36_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_36_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_36_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_36_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_36_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_37
+#define WAKE_AOWAKE_MASK_W_37                   MK_ADDR_CONST(0x214)
+#define WAKE_AOWAKE_MASK_W_37_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_37_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_37_SCR                       EVENT_CNTRL_SCR_37
+#define WAKE_AOWAKE_MASK_W_37_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_37
+#define WAKE_AOWAKE_MASK_W_37_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_37_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_37_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_37_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_37_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_37_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_37_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_37_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_37_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_37_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_37_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_37_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_37_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_37_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_37_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_37_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_37_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_37_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_37_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_37_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_37_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_37_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_37_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_38
+#define WAKE_AOWAKE_MASK_W_38                   MK_ADDR_CONST(0x218)
+#define WAKE_AOWAKE_MASK_W_38_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_38_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_38_SCR                       EVENT_CNTRL_SCR_38
+#define WAKE_AOWAKE_MASK_W_38_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_38
+#define WAKE_AOWAKE_MASK_W_38_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_38_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_38_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_38_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_38_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_38_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_38_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_38_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_38_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_38_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_38_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_38_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_38_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_38_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_38_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_38_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_38_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_38_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_38_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_38_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_38_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_38_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_38_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_39
+#define WAKE_AOWAKE_MASK_W_39                   MK_ADDR_CONST(0x21c)
+#define WAKE_AOWAKE_MASK_W_39_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_39_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_39_SCR                       EVENT_CNTRL_SCR_39
+#define WAKE_AOWAKE_MASK_W_39_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_39
+#define WAKE_AOWAKE_MASK_W_39_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_39_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_39_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_39_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_39_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_39_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_39_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_39_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_39_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_39_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_39_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_39_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_39_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_39_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_39_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_39_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_39_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_39_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_39_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_39_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_39_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_39_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_39_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_40
+#define WAKE_AOWAKE_MASK_W_40                   MK_ADDR_CONST(0x220)
+#define WAKE_AOWAKE_MASK_W_40_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_40_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_40_SCR                       EVENT_CNTRL_SCR_40
+#define WAKE_AOWAKE_MASK_W_40_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_40
+#define WAKE_AOWAKE_MASK_W_40_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_40_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_40_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_40_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_40_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_40_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_40_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_40_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_40_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_40_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_40_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_40_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_40_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_40_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_40_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_40_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_40_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_40_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_40_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_40_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_40_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_40_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_40_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_41
+#define WAKE_AOWAKE_MASK_W_41                   MK_ADDR_CONST(0x224)
+#define WAKE_AOWAKE_MASK_W_41_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_41_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_41_SCR                       EVENT_CNTRL_SCR_41
+#define WAKE_AOWAKE_MASK_W_41_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_41
+#define WAKE_AOWAKE_MASK_W_41_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_41_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_41_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_41_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_41_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_41_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_41_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_41_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_41_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_41_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_41_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_41_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_41_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_41_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_41_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_41_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_41_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_41_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_41_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_41_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_41_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_41_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_41_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_42
+#define WAKE_AOWAKE_MASK_W_42                   MK_ADDR_CONST(0x228)
+#define WAKE_AOWAKE_MASK_W_42_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_42_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_42_SCR                       EVENT_CNTRL_SCR_42
+#define WAKE_AOWAKE_MASK_W_42_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_42
+#define WAKE_AOWAKE_MASK_W_42_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_42_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_42_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_42_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_42_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_42_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_42_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_42_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_42_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_42_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_42_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_42_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_42_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_42_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_42_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_42_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_42_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_42_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_42_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_42_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_42_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_42_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_42_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_43
+#define WAKE_AOWAKE_MASK_W_43                   MK_ADDR_CONST(0x22c)
+#define WAKE_AOWAKE_MASK_W_43_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_43_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_43_SCR                       EVENT_CNTRL_SCR_43
+#define WAKE_AOWAKE_MASK_W_43_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_43
+#define WAKE_AOWAKE_MASK_W_43_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_43_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_43_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_43_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_43_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_43_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_43_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_43_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_43_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_43_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_43_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_43_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_43_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_43_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_43_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_43_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_43_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_43_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_43_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_43_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_43_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_43_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_43_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_44
+#define WAKE_AOWAKE_MASK_W_44                   MK_ADDR_CONST(0x230)
+#define WAKE_AOWAKE_MASK_W_44_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_44_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_44_SCR                       EVENT_CNTRL_SCR_44
+#define WAKE_AOWAKE_MASK_W_44_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_44
+#define WAKE_AOWAKE_MASK_W_44_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_44_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_44_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_44_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_44_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_44_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_44_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_44_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_44_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_44_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_44_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_44_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_44_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_44_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_44_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_44_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_44_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_44_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_44_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_44_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_44_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_44_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_44_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_45
+#define WAKE_AOWAKE_MASK_W_45                   MK_ADDR_CONST(0x234)
+#define WAKE_AOWAKE_MASK_W_45_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_45_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_45_SCR                       EVENT_CNTRL_SCR_45
+#define WAKE_AOWAKE_MASK_W_45_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_45
+#define WAKE_AOWAKE_MASK_W_45_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_45_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_45_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_45_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_45_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_45_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_45_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_45_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_45_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_45_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_45_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_45_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_45_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_45_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_45_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_45_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_45_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_45_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_45_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_45_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_45_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_45_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_45_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_46
+#define WAKE_AOWAKE_MASK_W_46                   MK_ADDR_CONST(0x238)
+#define WAKE_AOWAKE_MASK_W_46_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_46_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_46_SCR                       EVENT_CNTRL_SCR_46
+#define WAKE_AOWAKE_MASK_W_46_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_46
+#define WAKE_AOWAKE_MASK_W_46_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_46_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_46_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_46_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_46_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_46_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_46_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_46_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_46_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_46_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_46_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_46_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_46_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_46_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_46_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_46_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_46_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_46_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_46_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_46_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_46_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_46_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_46_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_47
+#define WAKE_AOWAKE_MASK_W_47                   MK_ADDR_CONST(0x23c)
+#define WAKE_AOWAKE_MASK_W_47_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_47_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_47_SCR                       EVENT_CNTRL_SCR_47
+#define WAKE_AOWAKE_MASK_W_47_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_47
+#define WAKE_AOWAKE_MASK_W_47_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_47_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_47_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_47_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_47_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_47_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_47_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_47_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_47_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_47_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_47_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_47_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_47_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_47_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_47_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_47_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_47_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_47_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_47_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_47_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_47_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_47_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_47_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_48
+#define WAKE_AOWAKE_MASK_W_48                   MK_ADDR_CONST(0x240)
+#define WAKE_AOWAKE_MASK_W_48_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_48_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_48_SCR                       EVENT_CNTRL_SCR_48
+#define WAKE_AOWAKE_MASK_W_48_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_48
+#define WAKE_AOWAKE_MASK_W_48_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_48_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_48_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_48_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_48_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_48_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_48_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_48_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_48_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_48_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_48_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_48_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_48_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_48_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_48_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_48_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_48_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_48_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_48_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_48_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_48_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_48_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_48_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_49
+#define WAKE_AOWAKE_MASK_W_49                   MK_ADDR_CONST(0x244)
+#define WAKE_AOWAKE_MASK_W_49_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_49_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_49_SCR                       EVENT_CNTRL_SCR_49
+#define WAKE_AOWAKE_MASK_W_49_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_49
+#define WAKE_AOWAKE_MASK_W_49_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_49_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_49_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_49_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_49_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_49_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_49_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_49_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_49_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_49_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_49_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_49_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_49_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_49_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_49_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_49_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_49_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_49_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_49_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_49_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_49_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_49_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_49_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_50
+#define WAKE_AOWAKE_MASK_W_50                   MK_ADDR_CONST(0x248)
+#define WAKE_AOWAKE_MASK_W_50_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_50_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_50_SCR                       EVENT_CNTRL_SCR_50
+#define WAKE_AOWAKE_MASK_W_50_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_50
+#define WAKE_AOWAKE_MASK_W_50_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_50_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_50_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_50_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_50_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_50_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_50_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_50_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_50_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_50_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_50_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_50_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_50_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_50_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_50_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_50_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_50_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_50_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_50_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_50_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_50_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_50_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_50_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_51
+#define WAKE_AOWAKE_MASK_W_51                   MK_ADDR_CONST(0x24c)
+#define WAKE_AOWAKE_MASK_W_51_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_51_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_51_SCR                       EVENT_CNTRL_SCR_51
+#define WAKE_AOWAKE_MASK_W_51_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_51
+#define WAKE_AOWAKE_MASK_W_51_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_51_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_51_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_51_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_51_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_51_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_51_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_51_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_51_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_51_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_51_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_51_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_51_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_51_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_51_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_51_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_51_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_51_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_51_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_51_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_51_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_51_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_51_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_52
+#define WAKE_AOWAKE_MASK_W_52                   MK_ADDR_CONST(0x250)
+#define WAKE_AOWAKE_MASK_W_52_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_52_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_52_SCR                       EVENT_CNTRL_SCR_52
+#define WAKE_AOWAKE_MASK_W_52_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_52
+#define WAKE_AOWAKE_MASK_W_52_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_52_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_52_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_52_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_52_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_52_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_52_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_52_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_52_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_52_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_52_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_52_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_52_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_52_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_52_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_52_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_52_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_52_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_52_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_52_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_52_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_52_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_52_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_53
+#define WAKE_AOWAKE_MASK_W_53                   MK_ADDR_CONST(0x254)
+#define WAKE_AOWAKE_MASK_W_53_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_53_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_53_SCR                       EVENT_CNTRL_SCR_53
+#define WAKE_AOWAKE_MASK_W_53_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_53
+#define WAKE_AOWAKE_MASK_W_53_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_53_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_53_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_53_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_53_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_53_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_53_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_53_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_53_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_53_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_53_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_53_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_53_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_53_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_53_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_53_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_53_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_53_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_53_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_53_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_53_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_53_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_53_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_54
+#define WAKE_AOWAKE_MASK_W_54                   MK_ADDR_CONST(0x258)
+#define WAKE_AOWAKE_MASK_W_54_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_54_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_54_SCR                       EVENT_CNTRL_SCR_54
+#define WAKE_AOWAKE_MASK_W_54_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_54
+#define WAKE_AOWAKE_MASK_W_54_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_54_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_54_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_54_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_54_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_54_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_54_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_54_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_54_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_54_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_54_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_54_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_54_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_54_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_54_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_54_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_54_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_54_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_54_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_54_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_54_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_54_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_54_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_55
+#define WAKE_AOWAKE_MASK_W_55                   MK_ADDR_CONST(0x25c)
+#define WAKE_AOWAKE_MASK_W_55_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_55_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_55_SCR                       EVENT_CNTRL_SCR_55
+#define WAKE_AOWAKE_MASK_W_55_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_55
+#define WAKE_AOWAKE_MASK_W_55_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_55_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_55_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_55_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_55_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_55_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_55_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_55_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_55_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_55_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_55_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_55_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_55_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_55_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_55_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_55_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_55_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_55_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_55_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_55_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_55_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_55_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_55_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_56
+#define WAKE_AOWAKE_MASK_W_56                   MK_ADDR_CONST(0x260)
+#define WAKE_AOWAKE_MASK_W_56_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_56_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_56_SCR                       EVENT_CNTRL_SCR_56
+#define WAKE_AOWAKE_MASK_W_56_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_56
+#define WAKE_AOWAKE_MASK_W_56_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_56_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_56_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_56_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_56_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_56_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_56_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_56_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_56_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_56_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_56_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_56_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_56_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_56_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_56_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_56_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_56_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_56_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_56_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_56_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_56_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_56_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_56_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_57
+#define WAKE_AOWAKE_MASK_W_57                   MK_ADDR_CONST(0x264)
+#define WAKE_AOWAKE_MASK_W_57_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_57_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_57_SCR                       EVENT_CNTRL_SCR_57
+#define WAKE_AOWAKE_MASK_W_57_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_57
+#define WAKE_AOWAKE_MASK_W_57_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_57_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_57_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_57_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_57_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_57_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_57_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_57_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_57_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_57_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_57_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_57_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_57_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_57_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_57_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_57_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_57_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_57_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_57_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_57_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_57_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_57_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_57_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_58
+#define WAKE_AOWAKE_MASK_W_58                   MK_ADDR_CONST(0x268)
+#define WAKE_AOWAKE_MASK_W_58_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_58_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_58_SCR                       EVENT_CNTRL_SCR_58
+#define WAKE_AOWAKE_MASK_W_58_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_58
+#define WAKE_AOWAKE_MASK_W_58_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_58_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_58_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_58_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_58_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_58_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_58_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_58_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_58_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_58_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_58_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_58_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_58_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_58_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_58_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_58_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_58_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_58_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_58_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_58_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_58_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_58_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_58_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_59
+#define WAKE_AOWAKE_MASK_W_59                   MK_ADDR_CONST(0x26c)
+#define WAKE_AOWAKE_MASK_W_59_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_59_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_59_SCR                       EVENT_CNTRL_SCR_59
+#define WAKE_AOWAKE_MASK_W_59_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_59
+#define WAKE_AOWAKE_MASK_W_59_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_59_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_59_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_59_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_59_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_59_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_59_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_59_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_59_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_59_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_59_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_59_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_59_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_59_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_59_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_59_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_59_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_59_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_59_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_59_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_59_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_59_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_59_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_60
+#define WAKE_AOWAKE_MASK_W_60                   MK_ADDR_CONST(0x270)
+#define WAKE_AOWAKE_MASK_W_60_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_60_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_60_SCR                       EVENT_CNTRL_SCR_60
+#define WAKE_AOWAKE_MASK_W_60_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_60
+#define WAKE_AOWAKE_MASK_W_60_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_60_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_60_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_60_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_60_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_60_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_60_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_60_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_60_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_60_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_60_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_60_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_60_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_60_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_60_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_60_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_60_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_60_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_60_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_60_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_60_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_60_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_60_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_61
+#define WAKE_AOWAKE_MASK_W_61                   MK_ADDR_CONST(0x274)
+#define WAKE_AOWAKE_MASK_W_61_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_61_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_61_SCR                       EVENT_CNTRL_SCR_61
+#define WAKE_AOWAKE_MASK_W_61_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_61
+#define WAKE_AOWAKE_MASK_W_61_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_61_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_61_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_61_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_61_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_61_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_61_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_61_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_61_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_61_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_61_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_61_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_61_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_61_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_61_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_61_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_61_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_61_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_61_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_61_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_61_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_61_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_61_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_62
+#define WAKE_AOWAKE_MASK_W_62                   MK_ADDR_CONST(0x278)
+#define WAKE_AOWAKE_MASK_W_62_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_62_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_62_SCR                       EVENT_CNTRL_SCR_62
+#define WAKE_AOWAKE_MASK_W_62_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_62
+#define WAKE_AOWAKE_MASK_W_62_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_62_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_62_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_62_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_62_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_62_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_62_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_62_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_62_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_62_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_62_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_62_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_62_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_62_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_62_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_62_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_62_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_62_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_62_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_62_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_62_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_62_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_62_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_63
+#define WAKE_AOWAKE_MASK_W_63                   MK_ADDR_CONST(0x27c)
+#define WAKE_AOWAKE_MASK_W_63_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_63_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_63_SCR                       EVENT_CNTRL_SCR_63
+#define WAKE_AOWAKE_MASK_W_63_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_63
+#define WAKE_AOWAKE_MASK_W_63_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_63_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_63_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_63_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_63_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_63_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_63_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_63_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_63_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_63_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_63_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_63_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_63_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_63_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_63_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_63_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_63_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_63_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_63_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_63_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_63_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_63_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_63_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_64
+#define WAKE_AOWAKE_MASK_W_64                   MK_ADDR_CONST(0x280)
+#define WAKE_AOWAKE_MASK_W_64_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_64_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_64_SCR                       EVENT_CNTRL_SCR_64
+#define WAKE_AOWAKE_MASK_W_64_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_64
+#define WAKE_AOWAKE_MASK_W_64_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_64_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_64_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_64_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_64_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_64_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_64_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_64_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_64_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_64_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_64_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_64_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_64_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_64_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_64_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_64_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_64_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_64_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_64_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_64_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_64_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_64_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_64_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_65
+#define WAKE_AOWAKE_MASK_W_65                   MK_ADDR_CONST(0x284)
+#define WAKE_AOWAKE_MASK_W_65_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_65_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_65_SCR                       EVENT_CNTRL_SCR_65
+#define WAKE_AOWAKE_MASK_W_65_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_65
+#define WAKE_AOWAKE_MASK_W_65_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_65_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_65_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_65_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_65_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_65_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_65_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_65_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_65_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_65_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_65_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_65_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_65_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_65_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_65_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_65_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_65_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_65_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_65_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_65_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_65_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_65_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_65_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_66
+#define WAKE_AOWAKE_MASK_W_66                   MK_ADDR_CONST(0x288)
+#define WAKE_AOWAKE_MASK_W_66_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_66_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_66_SCR                       EVENT_CNTRL_SCR_66
+#define WAKE_AOWAKE_MASK_W_66_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_66
+#define WAKE_AOWAKE_MASK_W_66_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_66_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_66_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_66_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_66_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_66_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_66_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_66_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_66_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_66_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_66_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_66_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_66_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_66_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_66_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_66_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_66_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_66_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_66_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_66_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_66_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_66_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_66_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_67
+#define WAKE_AOWAKE_MASK_W_67                   MK_ADDR_CONST(0x28c)
+#define WAKE_AOWAKE_MASK_W_67_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_67_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_67_SCR                       EVENT_CNTRL_SCR_67
+#define WAKE_AOWAKE_MASK_W_67_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_67
+#define WAKE_AOWAKE_MASK_W_67_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_67_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_67_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_67_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_67_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_67_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_67_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_67_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_67_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_67_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_67_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_67_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_67_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_67_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_67_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_67_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_67_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_67_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_67_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_67_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_67_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_67_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_67_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_68
+#define WAKE_AOWAKE_MASK_W_68                   MK_ADDR_CONST(0x290)
+#define WAKE_AOWAKE_MASK_W_68_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_68_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_68_SCR                       EVENT_CNTRL_SCR_68
+#define WAKE_AOWAKE_MASK_W_68_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_68
+#define WAKE_AOWAKE_MASK_W_68_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_68_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_68_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_68_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_68_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_68_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_68_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_68_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_68_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_68_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_68_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_68_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_68_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_68_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_68_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_68_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_68_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_68_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_68_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_68_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_68_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_68_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_68_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_69
+#define WAKE_AOWAKE_MASK_W_69                   MK_ADDR_CONST(0x294)
+#define WAKE_AOWAKE_MASK_W_69_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_69_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_69_SCR                       EVENT_CNTRL_SCR_69
+#define WAKE_AOWAKE_MASK_W_69_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_69
+#define WAKE_AOWAKE_MASK_W_69_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_69_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_69_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_69_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_69_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_69_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_69_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_69_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_69_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_69_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_69_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_69_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_69_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_69_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_69_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_69_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_69_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_69_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_69_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_69_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_69_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_69_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_69_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_70
+#define WAKE_AOWAKE_MASK_W_70                   MK_ADDR_CONST(0x298)
+#define WAKE_AOWAKE_MASK_W_70_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_70_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_70_SCR                       EVENT_CNTRL_SCR_70
+#define WAKE_AOWAKE_MASK_W_70_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_70
+#define WAKE_AOWAKE_MASK_W_70_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_70_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_70_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_70_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_70_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_70_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_70_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_70_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_70_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_70_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_70_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_70_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_70_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_70_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_70_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_70_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_70_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_70_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_70_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_70_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_70_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_70_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_70_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_71
+#define WAKE_AOWAKE_MASK_W_71                   MK_ADDR_CONST(0x29c)
+#define WAKE_AOWAKE_MASK_W_71_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_71_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_71_SCR                       EVENT_CNTRL_SCR_71
+#define WAKE_AOWAKE_MASK_W_71_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_71
+#define WAKE_AOWAKE_MASK_W_71_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_71_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_71_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_71_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_71_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_71_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_71_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_71_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_71_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_71_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_71_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_71_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_71_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_71_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_71_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_71_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_71_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_71_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_71_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_71_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_71_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_71_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_71_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_72
+#define WAKE_AOWAKE_MASK_W_72                   MK_ADDR_CONST(0x2a0)
+#define WAKE_AOWAKE_MASK_W_72_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_72_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_72_SCR                       EVENT_CNTRL_SCR_72
+#define WAKE_AOWAKE_MASK_W_72_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_72
+#define WAKE_AOWAKE_MASK_W_72_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_72_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_72_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_72_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_72_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_72_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_72_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_72_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_72_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_72_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_72_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_72_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_72_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_72_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_72_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_72_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_72_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_72_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_72_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_72_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_72_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_72_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_72_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_73
+#define WAKE_AOWAKE_MASK_W_73                   MK_ADDR_CONST(0x2a4)
+#define WAKE_AOWAKE_MASK_W_73_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_73_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_73_SCR                       EVENT_CNTRL_SCR_73
+#define WAKE_AOWAKE_MASK_W_73_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_73
+#define WAKE_AOWAKE_MASK_W_73_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_73_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_73_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_73_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_73_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_73_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_73_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_73_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_73_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_73_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_73_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_73_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_73_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_73_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_73_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_73_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_73_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_73_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_73_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_73_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_73_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_73_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_73_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_74
+#define WAKE_AOWAKE_MASK_W_74                   MK_ADDR_CONST(0x2a8)
+#define WAKE_AOWAKE_MASK_W_74_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_74_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_74_SCR                       EVENT_CNTRL_SCR_74
+#define WAKE_AOWAKE_MASK_W_74_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_74
+#define WAKE_AOWAKE_MASK_W_74_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_74_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_74_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_74_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_74_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_74_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_74_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_74_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_74_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_74_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_74_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_74_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_74_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_74_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_74_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_74_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_74_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_74_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_74_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_74_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_74_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_74_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_74_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_75
+#define WAKE_AOWAKE_MASK_W_75                   MK_ADDR_CONST(0x2ac)
+#define WAKE_AOWAKE_MASK_W_75_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_75_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_75_SCR                       EVENT_CNTRL_SCR_75
+#define WAKE_AOWAKE_MASK_W_75_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_75
+#define WAKE_AOWAKE_MASK_W_75_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_75_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_75_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_75_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_75_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_75_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_75_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_75_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_75_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_75_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_75_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_75_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_75_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_75_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_75_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_75_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_75_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_75_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_75_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_75_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_75_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_75_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_75_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_76
+#define WAKE_AOWAKE_MASK_W_76                   MK_ADDR_CONST(0x2b0)
+#define WAKE_AOWAKE_MASK_W_76_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_76_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_76_SCR                       EVENT_CNTRL_SCR_76
+#define WAKE_AOWAKE_MASK_W_76_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_76
+#define WAKE_AOWAKE_MASK_W_76_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_76_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_76_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_76_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_76_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_76_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_76_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_76_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_76_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_76_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_76_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_76_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_76_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_76_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_76_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_76_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_76_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_76_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_76_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_76_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_76_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_76_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_76_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_77
+#define WAKE_AOWAKE_MASK_W_77                   MK_ADDR_CONST(0x2b4)
+#define WAKE_AOWAKE_MASK_W_77_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_77_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_77_SCR                       EVENT_CNTRL_SCR_77
+#define WAKE_AOWAKE_MASK_W_77_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_77
+#define WAKE_AOWAKE_MASK_W_77_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_77_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_77_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_77_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_77_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_77_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_77_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_77_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_77_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_77_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_77_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_77_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_77_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_77_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_77_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_77_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_77_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_77_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_77_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_77_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_77_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_77_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_77_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_78
+#define WAKE_AOWAKE_MASK_W_78                   MK_ADDR_CONST(0x2b8)
+#define WAKE_AOWAKE_MASK_W_78_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_78_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_78_SCR                       EVENT_CNTRL_SCR_78
+#define WAKE_AOWAKE_MASK_W_78_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_78
+#define WAKE_AOWAKE_MASK_W_78_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_78_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_78_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_78_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_78_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_78_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_78_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_78_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_78_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_78_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_78_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_78_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_78_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_78_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_78_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_78_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_78_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_78_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_78_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_78_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_78_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_78_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_78_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_79
+#define WAKE_AOWAKE_MASK_W_79                   MK_ADDR_CONST(0x2bc)
+#define WAKE_AOWAKE_MASK_W_79_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_79_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_79_SCR                       EVENT_CNTRL_SCR_79
+#define WAKE_AOWAKE_MASK_W_79_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_79
+#define WAKE_AOWAKE_MASK_W_79_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_79_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_79_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_79_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_79_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_79_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_79_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_79_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_79_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_79_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_79_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_79_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_79_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_79_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_79_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_79_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_79_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_79_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_79_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_79_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_79_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_79_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_79_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_80
+#define WAKE_AOWAKE_MASK_W_80                   MK_ADDR_CONST(0x2c0)
+#define WAKE_AOWAKE_MASK_W_80_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_80_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_80_SCR                       EVENT_CNTRL_SCR_80
+#define WAKE_AOWAKE_MASK_W_80_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_80
+#define WAKE_AOWAKE_MASK_W_80_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_80_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_80_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_80_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_80_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_80_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_80_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_80_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_80_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_80_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_80_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_80_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_80_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_80_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_80_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_80_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_80_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_80_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_80_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_80_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_80_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_80_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_80_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_81
+#define WAKE_AOWAKE_MASK_W_81                   MK_ADDR_CONST(0x2c4)
+#define WAKE_AOWAKE_MASK_W_81_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_81_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_81_SCR                       EVENT_CNTRL_SCR_81
+#define WAKE_AOWAKE_MASK_W_81_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_81
+#define WAKE_AOWAKE_MASK_W_81_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_81_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_81_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_81_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_81_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_81_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_81_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_81_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_81_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_81_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_81_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_81_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_81_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_81_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_81_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_81_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_81_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_81_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_81_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_81_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_81_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_81_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_81_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_82
+#define WAKE_AOWAKE_MASK_W_82                   MK_ADDR_CONST(0x2c8)
+#define WAKE_AOWAKE_MASK_W_82_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_82_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_82_SCR                       EVENT_CNTRL_SCR_82
+#define WAKE_AOWAKE_MASK_W_82_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_82
+#define WAKE_AOWAKE_MASK_W_82_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_82_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_82_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_82_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_82_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_82_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_82_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_82_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_82_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_82_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_82_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_82_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_82_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_82_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_82_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_82_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_82_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_82_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_82_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_82_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_82_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_82_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_82_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_83
+#define WAKE_AOWAKE_MASK_W_83                   MK_ADDR_CONST(0x2cc)
+#define WAKE_AOWAKE_MASK_W_83_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_83_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_83_SCR                       EVENT_CNTRL_SCR_83
+#define WAKE_AOWAKE_MASK_W_83_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_83
+#define WAKE_AOWAKE_MASK_W_83_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_83_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_83_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_83_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_83_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_83_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_83_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_83_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_83_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_83_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_83_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_83_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_83_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_83_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_83_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_83_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_83_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_83_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_83_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_83_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_83_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_83_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_83_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_84
+#define WAKE_AOWAKE_MASK_W_84                   MK_ADDR_CONST(0x2d0)
+#define WAKE_AOWAKE_MASK_W_84_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_84_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_84_SCR                       EVENT_CNTRL_SCR_84
+#define WAKE_AOWAKE_MASK_W_84_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_84
+#define WAKE_AOWAKE_MASK_W_84_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_84_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_84_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_84_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_84_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_84_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_84_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_84_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_84_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_84_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_84_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_84_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_84_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_84_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_84_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_84_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_84_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_84_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_84_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_84_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_84_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_84_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_84_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_85
+#define WAKE_AOWAKE_MASK_W_85                   MK_ADDR_CONST(0x2d4)
+#define WAKE_AOWAKE_MASK_W_85_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_85_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_85_SCR                       EVENT_CNTRL_SCR_85
+#define WAKE_AOWAKE_MASK_W_85_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_85
+#define WAKE_AOWAKE_MASK_W_85_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_85_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_85_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_85_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_85_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_85_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_85_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_85_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_85_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_85_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_85_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_85_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_85_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_85_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_85_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_85_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_85_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_85_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_85_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_85_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_85_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_85_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_85_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_86
+#define WAKE_AOWAKE_MASK_W_86                   MK_ADDR_CONST(0x2d8)
+#define WAKE_AOWAKE_MASK_W_86_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_86_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_86_SCR                       EVENT_CNTRL_SCR_86
+#define WAKE_AOWAKE_MASK_W_86_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_86
+#define WAKE_AOWAKE_MASK_W_86_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_86_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_86_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_86_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_86_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_86_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_86_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_86_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_86_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_86_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_86_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_86_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_86_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_86_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_86_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_86_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_86_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_86_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_86_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_86_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_86_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_86_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_86_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_87
+#define WAKE_AOWAKE_MASK_W_87                   MK_ADDR_CONST(0x2dc)
+#define WAKE_AOWAKE_MASK_W_87_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_87_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_87_SCR                       EVENT_CNTRL_SCR_87
+#define WAKE_AOWAKE_MASK_W_87_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_87
+#define WAKE_AOWAKE_MASK_W_87_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_87_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_87_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_87_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_87_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_87_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_87_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_87_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_87_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_87_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_87_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_87_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_87_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_87_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_87_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_87_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_87_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_87_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_87_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_87_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_87_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_87_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_87_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_88
+#define WAKE_AOWAKE_MASK_W_88                   MK_ADDR_CONST(0x2e0)
+#define WAKE_AOWAKE_MASK_W_88_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_88_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_88_SCR                       EVENT_CNTRL_SCR_88
+#define WAKE_AOWAKE_MASK_W_88_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_88
+#define WAKE_AOWAKE_MASK_W_88_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_88_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_88_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_88_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_88_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_88_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_88_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_88_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_88_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_88_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_88_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_88_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_88_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_88_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_88_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_88_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_88_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_88_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_88_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_88_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_88_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_88_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_88_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_89
+#define WAKE_AOWAKE_MASK_W_89                   MK_ADDR_CONST(0x2e4)
+#define WAKE_AOWAKE_MASK_W_89_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_89_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_89_SCR                       EVENT_CNTRL_SCR_89
+#define WAKE_AOWAKE_MASK_W_89_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_89
+#define WAKE_AOWAKE_MASK_W_89_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_89_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_89_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_89_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_89_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_89_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_89_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_89_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_89_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_89_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_89_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_89_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_89_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_89_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_89_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_89_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_89_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_89_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_89_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_89_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_89_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_89_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_89_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_90
+#define WAKE_AOWAKE_MASK_W_90                   MK_ADDR_CONST(0x2e8)
+#define WAKE_AOWAKE_MASK_W_90_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_90_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_90_SCR                       EVENT_CNTRL_SCR_90
+#define WAKE_AOWAKE_MASK_W_90_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_90
+#define WAKE_AOWAKE_MASK_W_90_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_90_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_90_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_90_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_90_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_90_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_90_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_90_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_90_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_90_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_90_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_90_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_90_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_90_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_90_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_90_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_90_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_90_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_90_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_90_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_90_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_90_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_90_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_91
+#define WAKE_AOWAKE_MASK_W_91                   MK_ADDR_CONST(0x2ec)
+#define WAKE_AOWAKE_MASK_W_91_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_91_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_91_SCR                       EVENT_CNTRL_SCR_91
+#define WAKE_AOWAKE_MASK_W_91_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_91
+#define WAKE_AOWAKE_MASK_W_91_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_91_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_91_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_91_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_91_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_91_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_91_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_91_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_91_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_91_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_91_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_91_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_91_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_91_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_91_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_91_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_91_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_91_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_91_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_91_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_91_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_91_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_91_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_92
+#define WAKE_AOWAKE_MASK_W_92                   MK_ADDR_CONST(0x2f0)
+#define WAKE_AOWAKE_MASK_W_92_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_92_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_92_SCR                       EVENT_CNTRL_SCR_92
+#define WAKE_AOWAKE_MASK_W_92_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_92
+#define WAKE_AOWAKE_MASK_W_92_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_92_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_92_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_92_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_92_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_92_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_92_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_92_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_92_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_92_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_92_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_92_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_92_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_92_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_92_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_92_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_92_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_92_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_92_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_92_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_92_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_92_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_92_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_93
+#define WAKE_AOWAKE_MASK_W_93                   MK_ADDR_CONST(0x2f4)
+#define WAKE_AOWAKE_MASK_W_93_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_93_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_93_SCR                       EVENT_CNTRL_SCR_93
+#define WAKE_AOWAKE_MASK_W_93_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_93
+#define WAKE_AOWAKE_MASK_W_93_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_93_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_93_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_93_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_93_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_93_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_93_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_93_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_93_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_93_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_93_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_93_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_93_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_93_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_93_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_93_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_93_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_93_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_93_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_93_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_93_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_93_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_93_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_94
+#define WAKE_AOWAKE_MASK_W_94                   MK_ADDR_CONST(0x2f8)
+#define WAKE_AOWAKE_MASK_W_94_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_94_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_94_SCR                       EVENT_CNTRL_SCR_94
+#define WAKE_AOWAKE_MASK_W_94_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_94
+#define WAKE_AOWAKE_MASK_W_94_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_94_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_94_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_94_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_94_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_94_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_94_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_94_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_94_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_94_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_94_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_94_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_94_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_94_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_94_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_94_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_94_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_94_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_94_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_94_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_94_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_94_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_94_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_W_95
+#define WAKE_AOWAKE_MASK_W_95                   MK_ADDR_CONST(0x2fc)
+#define WAKE_AOWAKE_MASK_W_95_SECURE                    0x0
+#define WAKE_AOWAKE_MASK_W_95_DUAL                      0x0
+#define WAKE_AOWAKE_MASK_W_95_SCR                       EVENT_CNTRL_SCR_95
+#define WAKE_AOWAKE_MASK_W_95_SCRREG                    WAKE_SCR_EVENT_CNTRL_SCR_95
+#define WAKE_AOWAKE_MASK_W_95_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_MASK_W_95_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_95_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_95_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_95_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_95_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_95_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_95_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_95_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_MASK_W_95_MASK_SHIFT)
+#define WAKE_AOWAKE_MASK_W_95_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_MASK_W_95_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_95_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_W_95_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_MASK_W_95_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_95_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_95_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_95_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_95_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_W_95_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_MASK_W_95_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_MASK_W_95_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_MASK_W_95_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_MASK_R_31_0_0
+#define WAKE_AOWAKE_MASK_R_31_0_0                       MK_ADDR_CONST(0x300)
+#define WAKE_AOWAKE_MASK_R_31_0_0_SECURE                        0x0
+#define WAKE_AOWAKE_MASK_R_31_0_0_DUAL                  0x0
+#define WAKE_AOWAKE_MASK_R_31_0_0_SCR                   0
+#define WAKE_AOWAKE_MASK_R_31_0_0_SCRREG                        0
+#define WAKE_AOWAKE_MASK_R_31_0_0_WORD_COUNT                    0x1
+#define WAKE_AOWAKE_MASK_R_31_0_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_31_0_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_MASK_R_31_0_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_31_0_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_31_0_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_MASK_R_31_0_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_31_0_0_STATUS_SHIFT                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_R_31_0_0_STATUS_FIELD                  MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_MASK_R_31_0_0_STATUS_SHIFT)
+#define WAKE_AOWAKE_MASK_R_31_0_0_STATUS_RANGE                  31:0
+#define WAKE_AOWAKE_MASK_R_31_0_0_STATUS_MSB                    MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_MASK_R_31_0_0_STATUS_LSB                    MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_R_31_0_0_STATUS_WOFFSET                        0x0
+#define WAKE_AOWAKE_MASK_R_31_0_0_STATUS_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_31_0_0_STATUS_DEFAULT_MASK                   MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_MASK_R_31_0_0_STATUS_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_31_0_0_STATUS_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_31_0_0_STATUS_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_31_0_0_STATUS_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_MASK_R_63_32_0
+#define WAKE_AOWAKE_MASK_R_63_32_0                      MK_ADDR_CONST(0x304)
+#define WAKE_AOWAKE_MASK_R_63_32_0_SECURE                       0x0
+#define WAKE_AOWAKE_MASK_R_63_32_0_DUAL                         0x0
+#define WAKE_AOWAKE_MASK_R_63_32_0_SCR                  0
+#define WAKE_AOWAKE_MASK_R_63_32_0_SCRREG                       0
+#define WAKE_AOWAKE_MASK_R_63_32_0_WORD_COUNT                   0x1
+#define WAKE_AOWAKE_MASK_R_63_32_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_63_32_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_MASK_R_63_32_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_63_32_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_63_32_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_MASK_R_63_32_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_63_32_0_STATUS_SHIFT                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_R_63_32_0_STATUS_FIELD                 MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_MASK_R_63_32_0_STATUS_SHIFT)
+#define WAKE_AOWAKE_MASK_R_63_32_0_STATUS_RANGE                 31:0
+#define WAKE_AOWAKE_MASK_R_63_32_0_STATUS_MSB                   MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_MASK_R_63_32_0_STATUS_LSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_R_63_32_0_STATUS_WOFFSET                       0x0
+#define WAKE_AOWAKE_MASK_R_63_32_0_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_63_32_0_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_MASK_R_63_32_0_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_63_32_0_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_63_32_0_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_63_32_0_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_MASK_R_95_64_0
+#define WAKE_AOWAKE_MASK_R_95_64_0                      MK_ADDR_CONST(0x308)
+#define WAKE_AOWAKE_MASK_R_95_64_0_SECURE                       0x0
+#define WAKE_AOWAKE_MASK_R_95_64_0_DUAL                         0x0
+#define WAKE_AOWAKE_MASK_R_95_64_0_SCR                  0
+#define WAKE_AOWAKE_MASK_R_95_64_0_SCRREG                       0
+#define WAKE_AOWAKE_MASK_R_95_64_0_WORD_COUNT                   0x1
+#define WAKE_AOWAKE_MASK_R_95_64_0_RESET_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_95_64_0_RESET_MASK                   MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_MASK_R_95_64_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_95_64_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_95_64_0_READ_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_MASK_R_95_64_0_WRITE_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_95_64_0_STATUS_SHIFT                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_R_95_64_0_STATUS_FIELD                 MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_MASK_R_95_64_0_STATUS_SHIFT)
+#define WAKE_AOWAKE_MASK_R_95_64_0_STATUS_RANGE                 31:0
+#define WAKE_AOWAKE_MASK_R_95_64_0_STATUS_MSB                   MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_MASK_R_95_64_0_STATUS_LSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_MASK_R_95_64_0_STATUS_WOFFSET                       0x0
+#define WAKE_AOWAKE_MASK_R_95_64_0_STATUS_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_95_64_0_STATUS_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_MASK_R_95_64_0_STATUS_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_95_64_0_STATUS_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_95_64_0_STATUS_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_MASK_R_95_64_0_STATUS_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_0
+#define WAKE_AOWAKE_STATUS_W_0                  MK_ADDR_CONST(0x30c)
+#define WAKE_AOWAKE_STATUS_W_0_SECURE                   0x0
+#define WAKE_AOWAKE_STATUS_W_0_DUAL                     0x0
+#define WAKE_AOWAKE_STATUS_W_0_SCR                      EVENT_CNTRL_SCR_0
+#define WAKE_AOWAKE_STATUS_W_0_SCRREG                   WAKE_SCR_EVENT_CNTRL_SCR_0
+#define WAKE_AOWAKE_STATUS_W_0_WORD_COUNT                       0x1
+#define WAKE_AOWAKE_STATUS_W_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_0_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_0_CLEAR_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_0_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_0_CLEAR_RANGE                      0:0
+#define WAKE_AOWAKE_STATUS_W_0_CLEAR_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_0_CLEAR_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_0_CLEAR_WOFFSET                    0x0
+#define WAKE_AOWAKE_STATUS_W_0_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_0_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_0_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_0_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_0_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_0_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_0_CLEAR_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_STATUS_W_0_CLEAR_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_0_CLEAR_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W
+#define WAKE_AOWAKE_STATUS_W                    MK_ADDR_CONST(0x30c)
+#define WAKE_AOWAKE_STATUS_W_SECURE                     0x0
+#define WAKE_AOWAKE_STATUS_W_DUAL                       0x0
+#define WAKE_AOWAKE_STATUS_W_SCR                        EVENT_CNTRL_SCR_0
+#define WAKE_AOWAKE_STATUS_W_SCRREG                     WAKE_SCR_EVENT_CNTRL_SCR_0
+#define WAKE_AOWAKE_STATUS_W_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_STATUS_W_RESET_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_RESET_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_READ_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_CLEAR_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_CLEAR_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_CLEAR_RANGE                        0:0
+#define WAKE_AOWAKE_STATUS_W_CLEAR_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_CLEAR_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_CLEAR_WOFFSET                      0x0
+#define WAKE_AOWAKE_STATUS_W_CLEAR_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_CLEAR_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_CLEAR_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_CLEAR_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_CLEAR_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_CLEAR_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_CLEAR_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_STATUS_W_CLEAR_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_CLEAR_TRUE                 MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_1
+#define WAKE_AOWAKE_STATUS_W_1                  MK_ADDR_CONST(0x310)
+#define WAKE_AOWAKE_STATUS_W_1_SECURE                   0x0
+#define WAKE_AOWAKE_STATUS_W_1_DUAL                     0x0
+#define WAKE_AOWAKE_STATUS_W_1_SCR                      EVENT_CNTRL_SCR_1
+#define WAKE_AOWAKE_STATUS_W_1_SCRREG                   WAKE_SCR_EVENT_CNTRL_SCR_1
+#define WAKE_AOWAKE_STATUS_W_1_WORD_COUNT                       0x1
+#define WAKE_AOWAKE_STATUS_W_1_RESET_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_1_RESET_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_1_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_1_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_1_READ_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_1_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_1_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_1_CLEAR_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_1_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_1_CLEAR_RANGE                      0:0
+#define WAKE_AOWAKE_STATUS_W_1_CLEAR_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_1_CLEAR_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_1_CLEAR_WOFFSET                    0x0
+#define WAKE_AOWAKE_STATUS_W_1_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_1_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_1_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_1_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_1_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_1_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_1_CLEAR_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_STATUS_W_1_CLEAR_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_1_CLEAR_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_2
+#define WAKE_AOWAKE_STATUS_W_2                  MK_ADDR_CONST(0x314)
+#define WAKE_AOWAKE_STATUS_W_2_SECURE                   0x0
+#define WAKE_AOWAKE_STATUS_W_2_DUAL                     0x0
+#define WAKE_AOWAKE_STATUS_W_2_SCR                      EVENT_CNTRL_SCR_2
+#define WAKE_AOWAKE_STATUS_W_2_SCRREG                   WAKE_SCR_EVENT_CNTRL_SCR_2
+#define WAKE_AOWAKE_STATUS_W_2_WORD_COUNT                       0x1
+#define WAKE_AOWAKE_STATUS_W_2_RESET_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_2_RESET_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_2_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_2_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_2_READ_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_2_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_2_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_2_CLEAR_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_2_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_2_CLEAR_RANGE                      0:0
+#define WAKE_AOWAKE_STATUS_W_2_CLEAR_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_2_CLEAR_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_2_CLEAR_WOFFSET                    0x0
+#define WAKE_AOWAKE_STATUS_W_2_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_2_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_2_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_2_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_2_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_2_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_2_CLEAR_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_STATUS_W_2_CLEAR_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_2_CLEAR_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_3
+#define WAKE_AOWAKE_STATUS_W_3                  MK_ADDR_CONST(0x318)
+#define WAKE_AOWAKE_STATUS_W_3_SECURE                   0x0
+#define WAKE_AOWAKE_STATUS_W_3_DUAL                     0x0
+#define WAKE_AOWAKE_STATUS_W_3_SCR                      EVENT_CNTRL_SCR_3
+#define WAKE_AOWAKE_STATUS_W_3_SCRREG                   WAKE_SCR_EVENT_CNTRL_SCR_3
+#define WAKE_AOWAKE_STATUS_W_3_WORD_COUNT                       0x1
+#define WAKE_AOWAKE_STATUS_W_3_RESET_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_3_RESET_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_3_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_3_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_3_READ_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_3_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_3_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_3_CLEAR_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_3_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_3_CLEAR_RANGE                      0:0
+#define WAKE_AOWAKE_STATUS_W_3_CLEAR_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_3_CLEAR_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_3_CLEAR_WOFFSET                    0x0
+#define WAKE_AOWAKE_STATUS_W_3_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_3_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_3_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_3_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_3_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_3_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_3_CLEAR_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_STATUS_W_3_CLEAR_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_3_CLEAR_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_4
+#define WAKE_AOWAKE_STATUS_W_4                  MK_ADDR_CONST(0x31c)
+#define WAKE_AOWAKE_STATUS_W_4_SECURE                   0x0
+#define WAKE_AOWAKE_STATUS_W_4_DUAL                     0x0
+#define WAKE_AOWAKE_STATUS_W_4_SCR                      EVENT_CNTRL_SCR_4
+#define WAKE_AOWAKE_STATUS_W_4_SCRREG                   WAKE_SCR_EVENT_CNTRL_SCR_4
+#define WAKE_AOWAKE_STATUS_W_4_WORD_COUNT                       0x1
+#define WAKE_AOWAKE_STATUS_W_4_RESET_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_4_RESET_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_4_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_4_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_4_READ_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_4_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_4_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_4_CLEAR_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_4_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_4_CLEAR_RANGE                      0:0
+#define WAKE_AOWAKE_STATUS_W_4_CLEAR_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_4_CLEAR_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_4_CLEAR_WOFFSET                    0x0
+#define WAKE_AOWAKE_STATUS_W_4_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_4_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_4_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_4_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_4_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_4_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_4_CLEAR_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_STATUS_W_4_CLEAR_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_4_CLEAR_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_5
+#define WAKE_AOWAKE_STATUS_W_5                  MK_ADDR_CONST(0x320)
+#define WAKE_AOWAKE_STATUS_W_5_SECURE                   0x0
+#define WAKE_AOWAKE_STATUS_W_5_DUAL                     0x0
+#define WAKE_AOWAKE_STATUS_W_5_SCR                      EVENT_CNTRL_SCR_5
+#define WAKE_AOWAKE_STATUS_W_5_SCRREG                   WAKE_SCR_EVENT_CNTRL_SCR_5
+#define WAKE_AOWAKE_STATUS_W_5_WORD_COUNT                       0x1
+#define WAKE_AOWAKE_STATUS_W_5_RESET_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_5_RESET_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_5_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_5_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_5_READ_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_5_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_5_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_5_CLEAR_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_5_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_5_CLEAR_RANGE                      0:0
+#define WAKE_AOWAKE_STATUS_W_5_CLEAR_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_5_CLEAR_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_5_CLEAR_WOFFSET                    0x0
+#define WAKE_AOWAKE_STATUS_W_5_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_5_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_5_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_5_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_5_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_5_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_5_CLEAR_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_STATUS_W_5_CLEAR_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_5_CLEAR_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_6
+#define WAKE_AOWAKE_STATUS_W_6                  MK_ADDR_CONST(0x324)
+#define WAKE_AOWAKE_STATUS_W_6_SECURE                   0x0
+#define WAKE_AOWAKE_STATUS_W_6_DUAL                     0x0
+#define WAKE_AOWAKE_STATUS_W_6_SCR                      EVENT_CNTRL_SCR_6
+#define WAKE_AOWAKE_STATUS_W_6_SCRREG                   WAKE_SCR_EVENT_CNTRL_SCR_6
+#define WAKE_AOWAKE_STATUS_W_6_WORD_COUNT                       0x1
+#define WAKE_AOWAKE_STATUS_W_6_RESET_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_6_RESET_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_6_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_6_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_6_READ_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_6_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_6_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_6_CLEAR_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_6_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_6_CLEAR_RANGE                      0:0
+#define WAKE_AOWAKE_STATUS_W_6_CLEAR_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_6_CLEAR_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_6_CLEAR_WOFFSET                    0x0
+#define WAKE_AOWAKE_STATUS_W_6_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_6_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_6_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_6_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_6_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_6_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_6_CLEAR_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_STATUS_W_6_CLEAR_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_6_CLEAR_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_7
+#define WAKE_AOWAKE_STATUS_W_7                  MK_ADDR_CONST(0x328)
+#define WAKE_AOWAKE_STATUS_W_7_SECURE                   0x0
+#define WAKE_AOWAKE_STATUS_W_7_DUAL                     0x0
+#define WAKE_AOWAKE_STATUS_W_7_SCR                      EVENT_CNTRL_SCR_7
+#define WAKE_AOWAKE_STATUS_W_7_SCRREG                   WAKE_SCR_EVENT_CNTRL_SCR_7
+#define WAKE_AOWAKE_STATUS_W_7_WORD_COUNT                       0x1
+#define WAKE_AOWAKE_STATUS_W_7_RESET_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_7_RESET_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_7_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_7_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_7_READ_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_7_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_7_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_7_CLEAR_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_7_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_7_CLEAR_RANGE                      0:0
+#define WAKE_AOWAKE_STATUS_W_7_CLEAR_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_7_CLEAR_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_7_CLEAR_WOFFSET                    0x0
+#define WAKE_AOWAKE_STATUS_W_7_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_7_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_7_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_7_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_7_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_7_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_7_CLEAR_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_STATUS_W_7_CLEAR_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_7_CLEAR_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_8
+#define WAKE_AOWAKE_STATUS_W_8                  MK_ADDR_CONST(0x32c)
+#define WAKE_AOWAKE_STATUS_W_8_SECURE                   0x0
+#define WAKE_AOWAKE_STATUS_W_8_DUAL                     0x0
+#define WAKE_AOWAKE_STATUS_W_8_SCR                      EVENT_CNTRL_SCR_8
+#define WAKE_AOWAKE_STATUS_W_8_SCRREG                   WAKE_SCR_EVENT_CNTRL_SCR_8
+#define WAKE_AOWAKE_STATUS_W_8_WORD_COUNT                       0x1
+#define WAKE_AOWAKE_STATUS_W_8_RESET_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_8_RESET_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_8_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_8_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_8_READ_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_8_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_8_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_8_CLEAR_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_8_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_8_CLEAR_RANGE                      0:0
+#define WAKE_AOWAKE_STATUS_W_8_CLEAR_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_8_CLEAR_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_8_CLEAR_WOFFSET                    0x0
+#define WAKE_AOWAKE_STATUS_W_8_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_8_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_8_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_8_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_8_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_8_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_8_CLEAR_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_STATUS_W_8_CLEAR_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_8_CLEAR_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_9
+#define WAKE_AOWAKE_STATUS_W_9                  MK_ADDR_CONST(0x330)
+#define WAKE_AOWAKE_STATUS_W_9_SECURE                   0x0
+#define WAKE_AOWAKE_STATUS_W_9_DUAL                     0x0
+#define WAKE_AOWAKE_STATUS_W_9_SCR                      EVENT_CNTRL_SCR_9
+#define WAKE_AOWAKE_STATUS_W_9_SCRREG                   WAKE_SCR_EVENT_CNTRL_SCR_9
+#define WAKE_AOWAKE_STATUS_W_9_WORD_COUNT                       0x1
+#define WAKE_AOWAKE_STATUS_W_9_RESET_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_9_RESET_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_9_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_9_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_9_READ_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_9_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_9_CLEAR_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_9_CLEAR_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_9_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_9_CLEAR_RANGE                      0:0
+#define WAKE_AOWAKE_STATUS_W_9_CLEAR_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_9_CLEAR_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_9_CLEAR_WOFFSET                    0x0
+#define WAKE_AOWAKE_STATUS_W_9_CLEAR_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_9_CLEAR_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_9_CLEAR_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_9_CLEAR_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_9_CLEAR_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_9_CLEAR_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_9_CLEAR_INIT_ENUM                  FALSE
+#define WAKE_AOWAKE_STATUS_W_9_CLEAR_FALSE                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_9_CLEAR_TRUE                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_10
+#define WAKE_AOWAKE_STATUS_W_10                 MK_ADDR_CONST(0x334)
+#define WAKE_AOWAKE_STATUS_W_10_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_10_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_10_SCR                     EVENT_CNTRL_SCR_10
+#define WAKE_AOWAKE_STATUS_W_10_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_10
+#define WAKE_AOWAKE_STATUS_W_10_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_10_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_10_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_10_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_10_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_10_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_10_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_10_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_10_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_10_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_10_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_10_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_10_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_10_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_10_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_10_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_10_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_10_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_10_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_10_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_10_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_10_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_10_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_11
+#define WAKE_AOWAKE_STATUS_W_11                 MK_ADDR_CONST(0x338)
+#define WAKE_AOWAKE_STATUS_W_11_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_11_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_11_SCR                     EVENT_CNTRL_SCR_11
+#define WAKE_AOWAKE_STATUS_W_11_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_11
+#define WAKE_AOWAKE_STATUS_W_11_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_11_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_11_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_11_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_11_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_11_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_11_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_11_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_11_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_11_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_11_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_11_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_11_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_11_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_11_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_11_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_11_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_11_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_11_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_11_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_11_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_11_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_11_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_12
+#define WAKE_AOWAKE_STATUS_W_12                 MK_ADDR_CONST(0x33c)
+#define WAKE_AOWAKE_STATUS_W_12_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_12_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_12_SCR                     EVENT_CNTRL_SCR_12
+#define WAKE_AOWAKE_STATUS_W_12_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_12
+#define WAKE_AOWAKE_STATUS_W_12_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_12_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_12_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_12_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_12_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_12_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_12_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_12_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_12_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_12_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_12_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_12_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_12_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_12_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_12_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_12_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_12_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_12_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_12_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_12_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_12_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_12_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_12_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_13
+#define WAKE_AOWAKE_STATUS_W_13                 MK_ADDR_CONST(0x340)
+#define WAKE_AOWAKE_STATUS_W_13_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_13_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_13_SCR                     EVENT_CNTRL_SCR_13
+#define WAKE_AOWAKE_STATUS_W_13_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_13
+#define WAKE_AOWAKE_STATUS_W_13_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_13_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_13_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_13_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_13_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_13_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_13_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_13_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_13_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_13_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_13_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_13_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_13_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_13_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_13_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_13_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_13_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_13_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_13_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_13_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_13_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_13_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_13_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_14
+#define WAKE_AOWAKE_STATUS_W_14                 MK_ADDR_CONST(0x344)
+#define WAKE_AOWAKE_STATUS_W_14_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_14_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_14_SCR                     EVENT_CNTRL_SCR_14
+#define WAKE_AOWAKE_STATUS_W_14_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_14
+#define WAKE_AOWAKE_STATUS_W_14_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_14_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_14_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_14_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_14_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_14_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_14_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_14_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_14_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_14_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_14_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_14_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_14_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_14_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_14_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_14_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_14_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_14_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_14_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_14_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_14_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_14_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_14_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_15
+#define WAKE_AOWAKE_STATUS_W_15                 MK_ADDR_CONST(0x348)
+#define WAKE_AOWAKE_STATUS_W_15_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_15_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_15_SCR                     EVENT_CNTRL_SCR_15
+#define WAKE_AOWAKE_STATUS_W_15_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_15
+#define WAKE_AOWAKE_STATUS_W_15_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_15_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_15_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_15_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_15_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_15_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_15_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_15_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_15_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_15_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_15_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_15_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_15_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_15_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_15_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_15_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_15_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_15_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_15_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_15_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_15_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_15_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_15_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_16
+#define WAKE_AOWAKE_STATUS_W_16                 MK_ADDR_CONST(0x34c)
+#define WAKE_AOWAKE_STATUS_W_16_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_16_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_16_SCR                     EVENT_CNTRL_SCR_16
+#define WAKE_AOWAKE_STATUS_W_16_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_16
+#define WAKE_AOWAKE_STATUS_W_16_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_16_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_16_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_16_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_16_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_16_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_16_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_16_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_16_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_16_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_16_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_16_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_16_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_16_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_16_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_16_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_16_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_16_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_16_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_16_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_16_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_16_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_16_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_17
+#define WAKE_AOWAKE_STATUS_W_17                 MK_ADDR_CONST(0x350)
+#define WAKE_AOWAKE_STATUS_W_17_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_17_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_17_SCR                     EVENT_CNTRL_SCR_17
+#define WAKE_AOWAKE_STATUS_W_17_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_17
+#define WAKE_AOWAKE_STATUS_W_17_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_17_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_17_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_17_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_17_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_17_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_17_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_17_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_17_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_17_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_17_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_17_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_17_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_17_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_17_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_17_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_17_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_17_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_17_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_17_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_17_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_17_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_17_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_18
+#define WAKE_AOWAKE_STATUS_W_18                 MK_ADDR_CONST(0x354)
+#define WAKE_AOWAKE_STATUS_W_18_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_18_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_18_SCR                     EVENT_CNTRL_SCR_18
+#define WAKE_AOWAKE_STATUS_W_18_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_18
+#define WAKE_AOWAKE_STATUS_W_18_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_18_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_18_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_18_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_18_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_18_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_18_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_18_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_18_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_18_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_18_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_18_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_18_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_18_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_18_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_18_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_18_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_18_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_18_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_18_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_18_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_18_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_18_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_19
+#define WAKE_AOWAKE_STATUS_W_19                 MK_ADDR_CONST(0x358)
+#define WAKE_AOWAKE_STATUS_W_19_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_19_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_19_SCR                     EVENT_CNTRL_SCR_19
+#define WAKE_AOWAKE_STATUS_W_19_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_19
+#define WAKE_AOWAKE_STATUS_W_19_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_19_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_19_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_19_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_19_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_19_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_19_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_19_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_19_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_19_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_19_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_19_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_19_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_19_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_19_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_19_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_19_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_19_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_19_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_19_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_19_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_19_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_19_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_20
+#define WAKE_AOWAKE_STATUS_W_20                 MK_ADDR_CONST(0x35c)
+#define WAKE_AOWAKE_STATUS_W_20_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_20_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_20_SCR                     EVENT_CNTRL_SCR_20
+#define WAKE_AOWAKE_STATUS_W_20_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_20
+#define WAKE_AOWAKE_STATUS_W_20_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_20_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_20_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_20_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_20_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_20_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_20_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_20_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_20_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_20_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_20_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_20_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_20_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_20_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_20_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_20_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_20_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_20_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_20_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_20_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_20_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_20_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_20_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_21
+#define WAKE_AOWAKE_STATUS_W_21                 MK_ADDR_CONST(0x360)
+#define WAKE_AOWAKE_STATUS_W_21_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_21_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_21_SCR                     EVENT_CNTRL_SCR_21
+#define WAKE_AOWAKE_STATUS_W_21_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_21
+#define WAKE_AOWAKE_STATUS_W_21_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_21_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_21_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_21_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_21_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_21_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_21_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_21_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_21_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_21_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_21_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_21_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_21_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_21_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_21_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_21_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_21_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_21_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_21_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_21_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_21_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_21_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_21_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_22
+#define WAKE_AOWAKE_STATUS_W_22                 MK_ADDR_CONST(0x364)
+#define WAKE_AOWAKE_STATUS_W_22_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_22_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_22_SCR                     EVENT_CNTRL_SCR_22
+#define WAKE_AOWAKE_STATUS_W_22_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_22
+#define WAKE_AOWAKE_STATUS_W_22_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_22_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_22_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_22_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_22_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_22_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_22_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_22_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_22_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_22_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_22_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_22_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_22_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_22_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_22_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_22_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_22_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_22_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_22_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_22_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_22_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_22_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_22_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_23
+#define WAKE_AOWAKE_STATUS_W_23                 MK_ADDR_CONST(0x368)
+#define WAKE_AOWAKE_STATUS_W_23_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_23_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_23_SCR                     EVENT_CNTRL_SCR_23
+#define WAKE_AOWAKE_STATUS_W_23_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_23
+#define WAKE_AOWAKE_STATUS_W_23_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_23_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_23_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_23_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_23_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_23_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_23_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_23_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_23_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_23_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_23_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_23_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_23_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_23_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_23_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_23_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_23_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_23_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_23_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_23_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_23_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_23_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_23_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_24
+#define WAKE_AOWAKE_STATUS_W_24                 MK_ADDR_CONST(0x36c)
+#define WAKE_AOWAKE_STATUS_W_24_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_24_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_24_SCR                     EVENT_CNTRL_SCR_24
+#define WAKE_AOWAKE_STATUS_W_24_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_24
+#define WAKE_AOWAKE_STATUS_W_24_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_24_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_24_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_24_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_24_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_24_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_24_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_24_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_24_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_24_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_24_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_24_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_24_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_24_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_24_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_24_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_24_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_24_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_24_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_24_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_24_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_24_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_24_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_25
+#define WAKE_AOWAKE_STATUS_W_25                 MK_ADDR_CONST(0x370)
+#define WAKE_AOWAKE_STATUS_W_25_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_25_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_25_SCR                     EVENT_CNTRL_SCR_25
+#define WAKE_AOWAKE_STATUS_W_25_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_25
+#define WAKE_AOWAKE_STATUS_W_25_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_25_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_25_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_25_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_25_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_25_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_25_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_25_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_25_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_25_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_25_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_25_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_25_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_25_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_25_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_25_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_25_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_25_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_25_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_25_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_25_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_25_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_25_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_26
+#define WAKE_AOWAKE_STATUS_W_26                 MK_ADDR_CONST(0x374)
+#define WAKE_AOWAKE_STATUS_W_26_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_26_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_26_SCR                     EVENT_CNTRL_SCR_26
+#define WAKE_AOWAKE_STATUS_W_26_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_26
+#define WAKE_AOWAKE_STATUS_W_26_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_26_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_26_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_26_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_26_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_26_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_26_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_26_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_26_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_26_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_26_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_26_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_26_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_26_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_26_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_26_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_26_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_26_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_26_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_26_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_26_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_26_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_26_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_27
+#define WAKE_AOWAKE_STATUS_W_27                 MK_ADDR_CONST(0x378)
+#define WAKE_AOWAKE_STATUS_W_27_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_27_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_27_SCR                     EVENT_CNTRL_SCR_27
+#define WAKE_AOWAKE_STATUS_W_27_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_27
+#define WAKE_AOWAKE_STATUS_W_27_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_27_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_27_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_27_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_27_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_27_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_27_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_27_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_27_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_27_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_27_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_27_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_27_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_27_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_27_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_27_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_27_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_27_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_27_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_27_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_27_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_27_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_27_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_28
+#define WAKE_AOWAKE_STATUS_W_28                 MK_ADDR_CONST(0x37c)
+#define WAKE_AOWAKE_STATUS_W_28_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_28_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_28_SCR                     EVENT_CNTRL_SCR_28
+#define WAKE_AOWAKE_STATUS_W_28_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_28
+#define WAKE_AOWAKE_STATUS_W_28_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_28_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_28_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_28_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_28_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_28_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_28_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_28_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_28_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_28_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_28_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_28_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_28_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_28_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_28_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_28_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_28_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_28_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_28_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_28_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_28_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_28_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_28_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_29
+#define WAKE_AOWAKE_STATUS_W_29                 MK_ADDR_CONST(0x380)
+#define WAKE_AOWAKE_STATUS_W_29_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_29_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_29_SCR                     EVENT_CNTRL_SCR_29
+#define WAKE_AOWAKE_STATUS_W_29_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_29
+#define WAKE_AOWAKE_STATUS_W_29_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_29_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_29_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_29_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_29_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_29_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_29_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_29_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_29_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_29_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_29_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_29_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_29_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_29_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_29_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_29_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_29_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_29_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_29_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_29_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_29_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_29_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_29_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_30
+#define WAKE_AOWAKE_STATUS_W_30                 MK_ADDR_CONST(0x384)
+#define WAKE_AOWAKE_STATUS_W_30_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_30_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_30_SCR                     EVENT_CNTRL_SCR_30
+#define WAKE_AOWAKE_STATUS_W_30_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_30
+#define WAKE_AOWAKE_STATUS_W_30_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_30_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_30_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_30_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_30_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_30_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_30_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_30_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_30_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_30_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_30_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_30_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_30_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_30_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_30_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_30_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_30_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_30_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_30_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_30_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_30_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_30_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_30_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_31
+#define WAKE_AOWAKE_STATUS_W_31                 MK_ADDR_CONST(0x388)
+#define WAKE_AOWAKE_STATUS_W_31_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_31_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_31_SCR                     EVENT_CNTRL_SCR_31
+#define WAKE_AOWAKE_STATUS_W_31_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_31
+#define WAKE_AOWAKE_STATUS_W_31_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_31_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_31_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_31_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_31_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_31_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_31_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_31_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_31_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_31_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_31_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_31_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_31_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_31_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_31_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_31_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_31_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_31_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_31_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_31_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_31_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_31_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_31_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_32
+#define WAKE_AOWAKE_STATUS_W_32                 MK_ADDR_CONST(0x38c)
+#define WAKE_AOWAKE_STATUS_W_32_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_32_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_32_SCR                     EVENT_CNTRL_SCR_32
+#define WAKE_AOWAKE_STATUS_W_32_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_32
+#define WAKE_AOWAKE_STATUS_W_32_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_32_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_32_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_32_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_32_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_32_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_32_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_32_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_32_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_32_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_32_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_32_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_32_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_32_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_32_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_32_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_32_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_32_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_32_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_32_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_32_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_32_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_32_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_33
+#define WAKE_AOWAKE_STATUS_W_33                 MK_ADDR_CONST(0x390)
+#define WAKE_AOWAKE_STATUS_W_33_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_33_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_33_SCR                     EVENT_CNTRL_SCR_33
+#define WAKE_AOWAKE_STATUS_W_33_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_33
+#define WAKE_AOWAKE_STATUS_W_33_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_33_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_33_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_33_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_33_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_33_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_33_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_33_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_33_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_33_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_33_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_33_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_33_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_33_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_33_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_33_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_33_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_33_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_33_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_33_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_33_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_33_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_33_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_34
+#define WAKE_AOWAKE_STATUS_W_34                 MK_ADDR_CONST(0x394)
+#define WAKE_AOWAKE_STATUS_W_34_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_34_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_34_SCR                     EVENT_CNTRL_SCR_34
+#define WAKE_AOWAKE_STATUS_W_34_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_34
+#define WAKE_AOWAKE_STATUS_W_34_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_34_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_34_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_34_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_34_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_34_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_34_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_34_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_34_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_34_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_34_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_34_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_34_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_34_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_34_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_34_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_34_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_34_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_34_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_34_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_34_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_34_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_34_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_35
+#define WAKE_AOWAKE_STATUS_W_35                 MK_ADDR_CONST(0x398)
+#define WAKE_AOWAKE_STATUS_W_35_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_35_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_35_SCR                     EVENT_CNTRL_SCR_35
+#define WAKE_AOWAKE_STATUS_W_35_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_35
+#define WAKE_AOWAKE_STATUS_W_35_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_35_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_35_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_35_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_35_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_35_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_35_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_35_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_35_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_35_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_35_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_35_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_35_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_35_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_35_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_35_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_35_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_35_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_35_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_35_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_35_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_35_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_35_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_36
+#define WAKE_AOWAKE_STATUS_W_36                 MK_ADDR_CONST(0x39c)
+#define WAKE_AOWAKE_STATUS_W_36_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_36_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_36_SCR                     EVENT_CNTRL_SCR_36
+#define WAKE_AOWAKE_STATUS_W_36_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_36
+#define WAKE_AOWAKE_STATUS_W_36_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_36_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_36_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_36_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_36_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_36_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_36_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_36_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_36_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_36_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_36_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_36_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_36_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_36_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_36_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_36_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_36_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_36_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_36_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_36_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_36_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_36_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_36_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_37
+#define WAKE_AOWAKE_STATUS_W_37                 MK_ADDR_CONST(0x3a0)
+#define WAKE_AOWAKE_STATUS_W_37_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_37_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_37_SCR                     EVENT_CNTRL_SCR_37
+#define WAKE_AOWAKE_STATUS_W_37_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_37
+#define WAKE_AOWAKE_STATUS_W_37_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_37_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_37_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_37_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_37_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_37_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_37_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_37_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_37_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_37_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_37_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_37_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_37_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_37_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_37_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_37_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_37_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_37_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_37_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_37_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_37_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_37_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_37_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_38
+#define WAKE_AOWAKE_STATUS_W_38                 MK_ADDR_CONST(0x3a4)
+#define WAKE_AOWAKE_STATUS_W_38_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_38_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_38_SCR                     EVENT_CNTRL_SCR_38
+#define WAKE_AOWAKE_STATUS_W_38_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_38
+#define WAKE_AOWAKE_STATUS_W_38_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_38_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_38_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_38_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_38_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_38_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_38_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_38_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_38_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_38_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_38_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_38_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_38_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_38_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_38_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_38_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_38_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_38_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_38_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_38_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_38_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_38_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_38_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_39
+#define WAKE_AOWAKE_STATUS_W_39                 MK_ADDR_CONST(0x3a8)
+#define WAKE_AOWAKE_STATUS_W_39_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_39_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_39_SCR                     EVENT_CNTRL_SCR_39
+#define WAKE_AOWAKE_STATUS_W_39_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_39
+#define WAKE_AOWAKE_STATUS_W_39_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_39_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_39_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_39_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_39_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_39_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_39_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_39_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_39_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_39_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_39_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_39_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_39_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_39_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_39_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_39_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_39_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_39_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_39_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_39_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_39_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_39_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_39_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_40
+#define WAKE_AOWAKE_STATUS_W_40                 MK_ADDR_CONST(0x3ac)
+#define WAKE_AOWAKE_STATUS_W_40_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_40_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_40_SCR                     EVENT_CNTRL_SCR_40
+#define WAKE_AOWAKE_STATUS_W_40_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_40
+#define WAKE_AOWAKE_STATUS_W_40_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_40_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_40_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_40_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_40_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_40_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_40_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_40_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_40_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_40_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_40_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_40_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_40_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_40_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_40_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_40_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_40_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_40_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_40_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_40_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_40_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_40_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_40_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_41
+#define WAKE_AOWAKE_STATUS_W_41                 MK_ADDR_CONST(0x3b0)
+#define WAKE_AOWAKE_STATUS_W_41_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_41_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_41_SCR                     EVENT_CNTRL_SCR_41
+#define WAKE_AOWAKE_STATUS_W_41_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_41
+#define WAKE_AOWAKE_STATUS_W_41_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_41_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_41_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_41_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_41_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_41_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_41_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_41_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_41_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_41_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_41_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_41_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_41_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_41_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_41_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_41_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_41_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_41_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_41_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_41_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_41_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_41_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_41_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_42
+#define WAKE_AOWAKE_STATUS_W_42                 MK_ADDR_CONST(0x3b4)
+#define WAKE_AOWAKE_STATUS_W_42_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_42_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_42_SCR                     EVENT_CNTRL_SCR_42
+#define WAKE_AOWAKE_STATUS_W_42_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_42
+#define WAKE_AOWAKE_STATUS_W_42_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_42_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_42_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_42_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_42_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_42_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_42_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_42_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_42_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_42_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_42_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_42_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_42_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_42_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_42_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_42_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_42_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_42_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_42_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_42_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_42_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_42_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_42_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_43
+#define WAKE_AOWAKE_STATUS_W_43                 MK_ADDR_CONST(0x3b8)
+#define WAKE_AOWAKE_STATUS_W_43_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_43_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_43_SCR                     EVENT_CNTRL_SCR_43
+#define WAKE_AOWAKE_STATUS_W_43_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_43
+#define WAKE_AOWAKE_STATUS_W_43_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_43_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_43_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_43_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_43_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_43_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_43_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_43_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_43_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_43_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_43_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_43_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_43_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_43_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_43_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_43_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_43_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_43_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_43_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_43_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_43_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_43_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_43_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_44
+#define WAKE_AOWAKE_STATUS_W_44                 MK_ADDR_CONST(0x3bc)
+#define WAKE_AOWAKE_STATUS_W_44_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_44_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_44_SCR                     EVENT_CNTRL_SCR_44
+#define WAKE_AOWAKE_STATUS_W_44_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_44
+#define WAKE_AOWAKE_STATUS_W_44_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_44_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_44_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_44_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_44_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_44_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_44_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_44_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_44_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_44_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_44_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_44_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_44_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_44_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_44_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_44_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_44_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_44_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_44_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_44_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_44_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_44_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_44_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_45
+#define WAKE_AOWAKE_STATUS_W_45                 MK_ADDR_CONST(0x3c0)
+#define WAKE_AOWAKE_STATUS_W_45_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_45_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_45_SCR                     EVENT_CNTRL_SCR_45
+#define WAKE_AOWAKE_STATUS_W_45_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_45
+#define WAKE_AOWAKE_STATUS_W_45_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_45_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_45_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_45_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_45_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_45_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_45_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_45_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_45_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_45_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_45_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_45_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_45_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_45_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_45_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_45_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_45_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_45_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_45_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_45_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_45_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_45_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_45_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_46
+#define WAKE_AOWAKE_STATUS_W_46                 MK_ADDR_CONST(0x3c4)
+#define WAKE_AOWAKE_STATUS_W_46_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_46_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_46_SCR                     EVENT_CNTRL_SCR_46
+#define WAKE_AOWAKE_STATUS_W_46_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_46
+#define WAKE_AOWAKE_STATUS_W_46_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_46_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_46_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_46_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_46_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_46_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_46_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_46_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_46_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_46_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_46_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_46_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_46_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_46_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_46_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_46_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_46_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_46_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_46_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_46_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_46_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_46_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_46_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_47
+#define WAKE_AOWAKE_STATUS_W_47                 MK_ADDR_CONST(0x3c8)
+#define WAKE_AOWAKE_STATUS_W_47_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_47_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_47_SCR                     EVENT_CNTRL_SCR_47
+#define WAKE_AOWAKE_STATUS_W_47_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_47
+#define WAKE_AOWAKE_STATUS_W_47_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_47_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_47_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_47_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_47_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_47_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_47_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_47_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_47_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_47_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_47_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_47_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_47_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_47_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_47_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_47_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_47_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_47_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_47_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_47_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_47_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_47_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_47_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_48
+#define WAKE_AOWAKE_STATUS_W_48                 MK_ADDR_CONST(0x3cc)
+#define WAKE_AOWAKE_STATUS_W_48_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_48_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_48_SCR                     EVENT_CNTRL_SCR_48
+#define WAKE_AOWAKE_STATUS_W_48_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_48
+#define WAKE_AOWAKE_STATUS_W_48_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_48_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_48_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_48_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_48_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_48_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_48_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_48_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_48_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_48_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_48_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_48_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_48_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_48_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_48_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_48_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_48_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_48_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_48_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_48_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_48_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_48_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_48_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_49
+#define WAKE_AOWAKE_STATUS_W_49                 MK_ADDR_CONST(0x3d0)
+#define WAKE_AOWAKE_STATUS_W_49_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_49_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_49_SCR                     EVENT_CNTRL_SCR_49
+#define WAKE_AOWAKE_STATUS_W_49_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_49
+#define WAKE_AOWAKE_STATUS_W_49_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_49_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_49_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_49_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_49_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_49_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_49_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_49_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_49_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_49_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_49_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_49_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_49_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_49_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_49_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_49_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_49_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_49_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_49_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_49_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_49_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_49_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_49_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_50
+#define WAKE_AOWAKE_STATUS_W_50                 MK_ADDR_CONST(0x3d4)
+#define WAKE_AOWAKE_STATUS_W_50_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_50_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_50_SCR                     EVENT_CNTRL_SCR_50
+#define WAKE_AOWAKE_STATUS_W_50_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_50
+#define WAKE_AOWAKE_STATUS_W_50_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_50_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_50_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_50_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_50_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_50_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_50_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_50_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_50_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_50_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_50_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_50_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_50_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_50_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_50_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_50_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_50_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_50_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_50_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_50_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_50_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_50_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_50_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_51
+#define WAKE_AOWAKE_STATUS_W_51                 MK_ADDR_CONST(0x3d8)
+#define WAKE_AOWAKE_STATUS_W_51_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_51_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_51_SCR                     EVENT_CNTRL_SCR_51
+#define WAKE_AOWAKE_STATUS_W_51_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_51
+#define WAKE_AOWAKE_STATUS_W_51_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_51_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_51_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_51_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_51_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_51_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_51_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_51_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_51_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_51_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_51_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_51_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_51_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_51_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_51_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_51_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_51_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_51_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_51_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_51_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_51_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_51_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_51_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_52
+#define WAKE_AOWAKE_STATUS_W_52                 MK_ADDR_CONST(0x3dc)
+#define WAKE_AOWAKE_STATUS_W_52_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_52_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_52_SCR                     EVENT_CNTRL_SCR_52
+#define WAKE_AOWAKE_STATUS_W_52_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_52
+#define WAKE_AOWAKE_STATUS_W_52_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_52_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_52_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_52_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_52_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_52_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_52_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_52_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_52_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_52_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_52_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_52_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_52_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_52_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_52_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_52_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_52_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_52_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_52_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_52_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_52_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_52_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_52_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_53
+#define WAKE_AOWAKE_STATUS_W_53                 MK_ADDR_CONST(0x3e0)
+#define WAKE_AOWAKE_STATUS_W_53_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_53_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_53_SCR                     EVENT_CNTRL_SCR_53
+#define WAKE_AOWAKE_STATUS_W_53_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_53
+#define WAKE_AOWAKE_STATUS_W_53_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_53_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_53_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_53_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_53_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_53_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_53_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_53_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_53_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_53_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_53_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_53_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_53_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_53_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_53_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_53_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_53_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_53_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_53_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_53_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_53_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_53_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_53_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_54
+#define WAKE_AOWAKE_STATUS_W_54                 MK_ADDR_CONST(0x3e4)
+#define WAKE_AOWAKE_STATUS_W_54_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_54_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_54_SCR                     EVENT_CNTRL_SCR_54
+#define WAKE_AOWAKE_STATUS_W_54_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_54
+#define WAKE_AOWAKE_STATUS_W_54_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_54_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_54_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_54_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_54_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_54_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_54_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_54_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_54_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_54_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_54_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_54_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_54_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_54_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_54_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_54_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_54_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_54_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_54_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_54_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_54_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_54_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_54_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_55
+#define WAKE_AOWAKE_STATUS_W_55                 MK_ADDR_CONST(0x3e8)
+#define WAKE_AOWAKE_STATUS_W_55_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_55_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_55_SCR                     EVENT_CNTRL_SCR_55
+#define WAKE_AOWAKE_STATUS_W_55_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_55
+#define WAKE_AOWAKE_STATUS_W_55_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_55_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_55_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_55_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_55_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_55_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_55_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_55_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_55_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_55_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_55_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_55_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_55_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_55_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_55_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_55_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_55_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_55_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_55_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_55_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_55_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_55_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_55_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_56
+#define WAKE_AOWAKE_STATUS_W_56                 MK_ADDR_CONST(0x3ec)
+#define WAKE_AOWAKE_STATUS_W_56_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_56_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_56_SCR                     EVENT_CNTRL_SCR_56
+#define WAKE_AOWAKE_STATUS_W_56_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_56
+#define WAKE_AOWAKE_STATUS_W_56_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_56_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_56_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_56_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_56_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_56_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_56_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_56_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_56_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_56_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_56_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_56_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_56_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_56_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_56_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_56_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_56_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_56_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_56_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_56_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_56_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_56_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_56_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_57
+#define WAKE_AOWAKE_STATUS_W_57                 MK_ADDR_CONST(0x3f0)
+#define WAKE_AOWAKE_STATUS_W_57_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_57_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_57_SCR                     EVENT_CNTRL_SCR_57
+#define WAKE_AOWAKE_STATUS_W_57_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_57
+#define WAKE_AOWAKE_STATUS_W_57_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_57_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_57_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_57_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_57_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_57_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_57_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_57_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_57_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_57_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_57_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_57_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_57_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_57_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_57_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_57_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_57_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_57_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_57_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_57_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_57_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_57_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_57_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_58
+#define WAKE_AOWAKE_STATUS_W_58                 MK_ADDR_CONST(0x3f4)
+#define WAKE_AOWAKE_STATUS_W_58_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_58_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_58_SCR                     EVENT_CNTRL_SCR_58
+#define WAKE_AOWAKE_STATUS_W_58_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_58
+#define WAKE_AOWAKE_STATUS_W_58_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_58_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_58_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_58_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_58_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_58_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_58_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_58_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_58_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_58_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_58_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_58_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_58_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_58_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_58_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_58_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_58_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_58_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_58_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_58_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_58_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_58_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_58_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_59
+#define WAKE_AOWAKE_STATUS_W_59                 MK_ADDR_CONST(0x3f8)
+#define WAKE_AOWAKE_STATUS_W_59_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_59_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_59_SCR                     EVENT_CNTRL_SCR_59
+#define WAKE_AOWAKE_STATUS_W_59_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_59
+#define WAKE_AOWAKE_STATUS_W_59_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_59_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_59_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_59_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_59_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_59_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_59_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_59_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_59_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_59_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_59_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_59_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_59_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_59_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_59_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_59_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_59_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_59_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_59_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_59_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_59_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_59_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_59_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_60
+#define WAKE_AOWAKE_STATUS_W_60                 MK_ADDR_CONST(0x3fc)
+#define WAKE_AOWAKE_STATUS_W_60_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_60_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_60_SCR                     EVENT_CNTRL_SCR_60
+#define WAKE_AOWAKE_STATUS_W_60_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_60
+#define WAKE_AOWAKE_STATUS_W_60_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_60_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_60_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_60_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_60_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_60_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_60_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_60_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_60_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_60_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_60_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_60_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_60_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_60_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_60_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_60_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_60_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_60_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_60_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_60_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_60_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_60_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_60_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_61
+#define WAKE_AOWAKE_STATUS_W_61                 MK_ADDR_CONST(0x400)
+#define WAKE_AOWAKE_STATUS_W_61_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_61_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_61_SCR                     EVENT_CNTRL_SCR_61
+#define WAKE_AOWAKE_STATUS_W_61_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_61
+#define WAKE_AOWAKE_STATUS_W_61_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_61_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_61_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_61_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_61_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_61_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_61_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_61_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_61_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_61_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_61_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_61_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_61_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_61_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_61_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_61_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_61_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_61_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_61_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_61_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_61_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_61_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_61_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_62
+#define WAKE_AOWAKE_STATUS_W_62                 MK_ADDR_CONST(0x404)
+#define WAKE_AOWAKE_STATUS_W_62_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_62_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_62_SCR                     EVENT_CNTRL_SCR_62
+#define WAKE_AOWAKE_STATUS_W_62_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_62
+#define WAKE_AOWAKE_STATUS_W_62_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_62_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_62_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_62_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_62_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_62_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_62_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_62_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_62_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_62_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_62_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_62_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_62_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_62_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_62_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_62_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_62_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_62_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_62_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_62_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_62_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_62_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_62_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_63
+#define WAKE_AOWAKE_STATUS_W_63                 MK_ADDR_CONST(0x408)
+#define WAKE_AOWAKE_STATUS_W_63_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_63_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_63_SCR                     EVENT_CNTRL_SCR_63
+#define WAKE_AOWAKE_STATUS_W_63_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_63
+#define WAKE_AOWAKE_STATUS_W_63_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_63_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_63_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_63_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_63_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_63_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_63_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_63_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_63_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_63_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_63_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_63_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_63_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_63_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_63_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_63_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_63_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_63_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_63_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_63_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_63_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_63_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_63_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_64
+#define WAKE_AOWAKE_STATUS_W_64                 MK_ADDR_CONST(0x40c)
+#define WAKE_AOWAKE_STATUS_W_64_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_64_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_64_SCR                     EVENT_CNTRL_SCR_64
+#define WAKE_AOWAKE_STATUS_W_64_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_64
+#define WAKE_AOWAKE_STATUS_W_64_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_64_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_64_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_64_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_64_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_64_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_64_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_64_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_64_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_64_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_64_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_64_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_64_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_64_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_64_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_64_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_64_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_64_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_64_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_64_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_64_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_64_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_64_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_65
+#define WAKE_AOWAKE_STATUS_W_65                 MK_ADDR_CONST(0x410)
+#define WAKE_AOWAKE_STATUS_W_65_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_65_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_65_SCR                     EVENT_CNTRL_SCR_65
+#define WAKE_AOWAKE_STATUS_W_65_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_65
+#define WAKE_AOWAKE_STATUS_W_65_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_65_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_65_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_65_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_65_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_65_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_65_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_65_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_65_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_65_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_65_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_65_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_65_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_65_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_65_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_65_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_65_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_65_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_65_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_65_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_65_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_65_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_65_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_66
+#define WAKE_AOWAKE_STATUS_W_66                 MK_ADDR_CONST(0x414)
+#define WAKE_AOWAKE_STATUS_W_66_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_66_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_66_SCR                     EVENT_CNTRL_SCR_66
+#define WAKE_AOWAKE_STATUS_W_66_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_66
+#define WAKE_AOWAKE_STATUS_W_66_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_66_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_66_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_66_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_66_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_66_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_66_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_66_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_66_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_66_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_66_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_66_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_66_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_66_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_66_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_66_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_66_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_66_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_66_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_66_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_66_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_66_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_66_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_67
+#define WAKE_AOWAKE_STATUS_W_67                 MK_ADDR_CONST(0x418)
+#define WAKE_AOWAKE_STATUS_W_67_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_67_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_67_SCR                     EVENT_CNTRL_SCR_67
+#define WAKE_AOWAKE_STATUS_W_67_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_67
+#define WAKE_AOWAKE_STATUS_W_67_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_67_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_67_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_67_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_67_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_67_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_67_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_67_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_67_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_67_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_67_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_67_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_67_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_67_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_67_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_67_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_67_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_67_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_67_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_67_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_67_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_67_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_67_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_68
+#define WAKE_AOWAKE_STATUS_W_68                 MK_ADDR_CONST(0x41c)
+#define WAKE_AOWAKE_STATUS_W_68_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_68_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_68_SCR                     EVENT_CNTRL_SCR_68
+#define WAKE_AOWAKE_STATUS_W_68_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_68
+#define WAKE_AOWAKE_STATUS_W_68_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_68_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_68_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_68_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_68_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_68_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_68_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_68_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_68_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_68_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_68_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_68_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_68_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_68_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_68_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_68_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_68_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_68_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_68_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_68_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_68_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_68_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_68_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_69
+#define WAKE_AOWAKE_STATUS_W_69                 MK_ADDR_CONST(0x420)
+#define WAKE_AOWAKE_STATUS_W_69_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_69_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_69_SCR                     EVENT_CNTRL_SCR_69
+#define WAKE_AOWAKE_STATUS_W_69_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_69
+#define WAKE_AOWAKE_STATUS_W_69_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_69_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_69_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_69_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_69_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_69_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_69_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_69_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_69_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_69_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_69_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_69_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_69_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_69_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_69_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_69_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_69_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_69_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_69_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_69_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_69_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_69_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_69_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_70
+#define WAKE_AOWAKE_STATUS_W_70                 MK_ADDR_CONST(0x424)
+#define WAKE_AOWAKE_STATUS_W_70_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_70_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_70_SCR                     EVENT_CNTRL_SCR_70
+#define WAKE_AOWAKE_STATUS_W_70_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_70
+#define WAKE_AOWAKE_STATUS_W_70_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_70_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_70_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_70_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_70_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_70_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_70_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_70_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_70_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_70_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_70_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_70_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_70_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_70_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_70_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_70_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_70_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_70_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_70_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_70_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_70_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_70_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_70_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_71
+#define WAKE_AOWAKE_STATUS_W_71                 MK_ADDR_CONST(0x428)
+#define WAKE_AOWAKE_STATUS_W_71_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_71_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_71_SCR                     EVENT_CNTRL_SCR_71
+#define WAKE_AOWAKE_STATUS_W_71_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_71
+#define WAKE_AOWAKE_STATUS_W_71_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_71_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_71_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_71_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_71_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_71_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_71_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_71_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_71_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_71_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_71_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_71_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_71_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_71_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_71_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_71_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_71_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_71_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_71_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_71_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_71_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_71_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_71_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_72
+#define WAKE_AOWAKE_STATUS_W_72                 MK_ADDR_CONST(0x42c)
+#define WAKE_AOWAKE_STATUS_W_72_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_72_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_72_SCR                     EVENT_CNTRL_SCR_72
+#define WAKE_AOWAKE_STATUS_W_72_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_72
+#define WAKE_AOWAKE_STATUS_W_72_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_72_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_72_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_72_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_72_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_72_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_72_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_72_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_72_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_72_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_72_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_72_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_72_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_72_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_72_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_72_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_72_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_72_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_72_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_72_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_72_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_72_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_72_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_73
+#define WAKE_AOWAKE_STATUS_W_73                 MK_ADDR_CONST(0x430)
+#define WAKE_AOWAKE_STATUS_W_73_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_73_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_73_SCR                     EVENT_CNTRL_SCR_73
+#define WAKE_AOWAKE_STATUS_W_73_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_73
+#define WAKE_AOWAKE_STATUS_W_73_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_73_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_73_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_73_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_73_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_73_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_73_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_73_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_73_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_73_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_73_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_73_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_73_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_73_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_73_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_73_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_73_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_73_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_73_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_73_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_73_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_73_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_73_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_74
+#define WAKE_AOWAKE_STATUS_W_74                 MK_ADDR_CONST(0x434)
+#define WAKE_AOWAKE_STATUS_W_74_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_74_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_74_SCR                     EVENT_CNTRL_SCR_74
+#define WAKE_AOWAKE_STATUS_W_74_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_74
+#define WAKE_AOWAKE_STATUS_W_74_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_74_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_74_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_74_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_74_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_74_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_74_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_74_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_74_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_74_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_74_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_74_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_74_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_74_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_74_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_74_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_74_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_74_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_74_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_74_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_74_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_74_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_74_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_75
+#define WAKE_AOWAKE_STATUS_W_75                 MK_ADDR_CONST(0x438)
+#define WAKE_AOWAKE_STATUS_W_75_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_75_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_75_SCR                     EVENT_CNTRL_SCR_75
+#define WAKE_AOWAKE_STATUS_W_75_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_75
+#define WAKE_AOWAKE_STATUS_W_75_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_75_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_75_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_75_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_75_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_75_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_75_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_75_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_75_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_75_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_75_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_75_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_75_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_75_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_75_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_75_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_75_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_75_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_75_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_75_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_75_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_75_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_75_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_76
+#define WAKE_AOWAKE_STATUS_W_76                 MK_ADDR_CONST(0x43c)
+#define WAKE_AOWAKE_STATUS_W_76_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_76_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_76_SCR                     EVENT_CNTRL_SCR_76
+#define WAKE_AOWAKE_STATUS_W_76_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_76
+#define WAKE_AOWAKE_STATUS_W_76_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_76_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_76_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_76_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_76_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_76_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_76_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_76_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_76_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_76_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_76_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_76_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_76_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_76_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_76_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_76_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_76_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_76_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_76_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_76_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_76_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_76_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_76_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_77
+#define WAKE_AOWAKE_STATUS_W_77                 MK_ADDR_CONST(0x440)
+#define WAKE_AOWAKE_STATUS_W_77_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_77_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_77_SCR                     EVENT_CNTRL_SCR_77
+#define WAKE_AOWAKE_STATUS_W_77_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_77
+#define WAKE_AOWAKE_STATUS_W_77_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_77_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_77_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_77_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_77_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_77_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_77_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_77_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_77_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_77_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_77_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_77_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_77_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_77_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_77_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_77_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_77_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_77_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_77_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_77_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_77_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_77_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_77_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_78
+#define WAKE_AOWAKE_STATUS_W_78                 MK_ADDR_CONST(0x444)
+#define WAKE_AOWAKE_STATUS_W_78_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_78_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_78_SCR                     EVENT_CNTRL_SCR_78
+#define WAKE_AOWAKE_STATUS_W_78_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_78
+#define WAKE_AOWAKE_STATUS_W_78_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_78_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_78_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_78_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_78_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_78_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_78_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_78_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_78_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_78_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_78_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_78_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_78_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_78_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_78_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_78_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_78_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_78_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_78_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_78_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_78_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_78_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_78_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_79
+#define WAKE_AOWAKE_STATUS_W_79                 MK_ADDR_CONST(0x448)
+#define WAKE_AOWAKE_STATUS_W_79_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_79_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_79_SCR                     EVENT_CNTRL_SCR_79
+#define WAKE_AOWAKE_STATUS_W_79_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_79
+#define WAKE_AOWAKE_STATUS_W_79_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_79_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_79_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_79_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_79_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_79_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_79_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_79_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_79_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_79_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_79_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_79_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_79_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_79_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_79_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_79_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_79_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_79_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_79_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_79_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_79_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_79_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_79_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_80
+#define WAKE_AOWAKE_STATUS_W_80                 MK_ADDR_CONST(0x44c)
+#define WAKE_AOWAKE_STATUS_W_80_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_80_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_80_SCR                     EVENT_CNTRL_SCR_80
+#define WAKE_AOWAKE_STATUS_W_80_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_80
+#define WAKE_AOWAKE_STATUS_W_80_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_80_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_80_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_80_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_80_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_80_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_80_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_80_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_80_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_80_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_80_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_80_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_80_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_80_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_80_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_80_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_80_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_80_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_80_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_80_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_80_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_80_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_80_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_81
+#define WAKE_AOWAKE_STATUS_W_81                 MK_ADDR_CONST(0x450)
+#define WAKE_AOWAKE_STATUS_W_81_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_81_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_81_SCR                     EVENT_CNTRL_SCR_81
+#define WAKE_AOWAKE_STATUS_W_81_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_81
+#define WAKE_AOWAKE_STATUS_W_81_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_81_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_81_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_81_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_81_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_81_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_81_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_81_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_81_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_81_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_81_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_81_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_81_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_81_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_81_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_81_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_81_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_81_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_81_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_81_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_81_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_81_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_81_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_82
+#define WAKE_AOWAKE_STATUS_W_82                 MK_ADDR_CONST(0x454)
+#define WAKE_AOWAKE_STATUS_W_82_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_82_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_82_SCR                     EVENT_CNTRL_SCR_82
+#define WAKE_AOWAKE_STATUS_W_82_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_82
+#define WAKE_AOWAKE_STATUS_W_82_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_82_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_82_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_82_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_82_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_82_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_82_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_82_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_82_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_82_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_82_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_82_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_82_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_82_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_82_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_82_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_82_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_82_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_82_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_82_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_82_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_82_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_82_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_83
+#define WAKE_AOWAKE_STATUS_W_83                 MK_ADDR_CONST(0x458)
+#define WAKE_AOWAKE_STATUS_W_83_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_83_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_83_SCR                     EVENT_CNTRL_SCR_83
+#define WAKE_AOWAKE_STATUS_W_83_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_83
+#define WAKE_AOWAKE_STATUS_W_83_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_83_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_83_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_83_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_83_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_83_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_83_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_83_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_83_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_83_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_83_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_83_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_83_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_83_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_83_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_83_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_83_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_83_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_83_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_83_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_83_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_83_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_83_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_84
+#define WAKE_AOWAKE_STATUS_W_84                 MK_ADDR_CONST(0x45c)
+#define WAKE_AOWAKE_STATUS_W_84_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_84_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_84_SCR                     EVENT_CNTRL_SCR_84
+#define WAKE_AOWAKE_STATUS_W_84_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_84
+#define WAKE_AOWAKE_STATUS_W_84_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_84_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_84_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_84_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_84_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_84_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_84_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_84_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_84_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_84_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_84_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_84_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_84_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_84_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_84_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_84_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_84_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_84_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_84_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_84_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_84_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_84_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_84_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_85
+#define WAKE_AOWAKE_STATUS_W_85                 MK_ADDR_CONST(0x460)
+#define WAKE_AOWAKE_STATUS_W_85_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_85_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_85_SCR                     EVENT_CNTRL_SCR_85
+#define WAKE_AOWAKE_STATUS_W_85_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_85
+#define WAKE_AOWAKE_STATUS_W_85_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_85_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_85_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_85_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_85_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_85_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_85_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_85_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_85_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_85_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_85_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_85_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_85_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_85_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_85_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_85_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_85_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_85_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_85_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_85_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_85_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_85_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_85_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_86
+#define WAKE_AOWAKE_STATUS_W_86                 MK_ADDR_CONST(0x464)
+#define WAKE_AOWAKE_STATUS_W_86_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_86_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_86_SCR                     EVENT_CNTRL_SCR_86
+#define WAKE_AOWAKE_STATUS_W_86_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_86
+#define WAKE_AOWAKE_STATUS_W_86_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_86_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_86_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_86_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_86_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_86_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_86_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_86_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_86_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_86_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_86_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_86_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_86_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_86_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_86_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_86_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_86_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_86_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_86_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_86_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_86_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_86_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_86_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_87
+#define WAKE_AOWAKE_STATUS_W_87                 MK_ADDR_CONST(0x468)
+#define WAKE_AOWAKE_STATUS_W_87_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_87_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_87_SCR                     EVENT_CNTRL_SCR_87
+#define WAKE_AOWAKE_STATUS_W_87_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_87
+#define WAKE_AOWAKE_STATUS_W_87_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_87_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_87_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_87_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_87_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_87_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_87_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_87_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_87_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_87_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_87_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_87_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_87_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_87_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_87_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_87_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_87_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_87_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_87_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_87_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_87_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_87_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_87_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_88
+#define WAKE_AOWAKE_STATUS_W_88                 MK_ADDR_CONST(0x46c)
+#define WAKE_AOWAKE_STATUS_W_88_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_88_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_88_SCR                     EVENT_CNTRL_SCR_88
+#define WAKE_AOWAKE_STATUS_W_88_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_88
+#define WAKE_AOWAKE_STATUS_W_88_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_88_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_88_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_88_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_88_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_88_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_88_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_88_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_88_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_88_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_88_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_88_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_88_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_88_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_88_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_88_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_88_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_88_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_88_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_88_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_88_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_88_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_88_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_89
+#define WAKE_AOWAKE_STATUS_W_89                 MK_ADDR_CONST(0x470)
+#define WAKE_AOWAKE_STATUS_W_89_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_89_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_89_SCR                     EVENT_CNTRL_SCR_89
+#define WAKE_AOWAKE_STATUS_W_89_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_89
+#define WAKE_AOWAKE_STATUS_W_89_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_89_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_89_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_89_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_89_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_89_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_89_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_89_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_89_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_89_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_89_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_89_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_89_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_89_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_89_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_89_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_89_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_89_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_89_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_89_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_89_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_89_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_89_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_90
+#define WAKE_AOWAKE_STATUS_W_90                 MK_ADDR_CONST(0x474)
+#define WAKE_AOWAKE_STATUS_W_90_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_90_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_90_SCR                     EVENT_CNTRL_SCR_90
+#define WAKE_AOWAKE_STATUS_W_90_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_90
+#define WAKE_AOWAKE_STATUS_W_90_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_90_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_90_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_90_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_90_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_90_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_90_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_90_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_90_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_90_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_90_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_90_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_90_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_90_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_90_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_90_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_90_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_90_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_90_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_90_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_90_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_90_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_90_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_91
+#define WAKE_AOWAKE_STATUS_W_91                 MK_ADDR_CONST(0x478)
+#define WAKE_AOWAKE_STATUS_W_91_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_91_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_91_SCR                     EVENT_CNTRL_SCR_91
+#define WAKE_AOWAKE_STATUS_W_91_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_91
+#define WAKE_AOWAKE_STATUS_W_91_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_91_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_91_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_91_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_91_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_91_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_91_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_91_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_91_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_91_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_91_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_91_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_91_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_91_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_91_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_91_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_91_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_91_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_91_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_91_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_91_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_91_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_91_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_92
+#define WAKE_AOWAKE_STATUS_W_92                 MK_ADDR_CONST(0x47c)
+#define WAKE_AOWAKE_STATUS_W_92_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_92_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_92_SCR                     EVENT_CNTRL_SCR_92
+#define WAKE_AOWAKE_STATUS_W_92_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_92
+#define WAKE_AOWAKE_STATUS_W_92_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_92_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_92_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_92_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_92_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_92_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_92_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_92_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_92_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_92_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_92_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_92_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_92_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_92_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_92_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_92_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_92_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_92_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_92_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_92_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_92_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_92_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_92_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_93
+#define WAKE_AOWAKE_STATUS_W_93                 MK_ADDR_CONST(0x480)
+#define WAKE_AOWAKE_STATUS_W_93_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_93_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_93_SCR                     EVENT_CNTRL_SCR_93
+#define WAKE_AOWAKE_STATUS_W_93_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_93
+#define WAKE_AOWAKE_STATUS_W_93_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_93_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_93_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_93_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_93_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_93_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_93_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_93_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_93_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_93_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_93_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_93_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_93_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_93_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_93_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_93_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_93_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_93_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_93_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_93_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_93_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_93_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_93_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_94
+#define WAKE_AOWAKE_STATUS_W_94                 MK_ADDR_CONST(0x484)
+#define WAKE_AOWAKE_STATUS_W_94_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_94_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_94_SCR                     EVENT_CNTRL_SCR_94
+#define WAKE_AOWAKE_STATUS_W_94_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_94
+#define WAKE_AOWAKE_STATUS_W_94_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_94_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_94_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_94_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_94_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_94_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_94_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_94_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_94_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_94_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_94_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_94_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_94_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_94_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_94_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_94_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_94_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_94_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_94_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_94_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_94_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_94_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_94_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_W_95
+#define WAKE_AOWAKE_STATUS_W_95                 MK_ADDR_CONST(0x488)
+#define WAKE_AOWAKE_STATUS_W_95_SECURE                  0x0
+#define WAKE_AOWAKE_STATUS_W_95_DUAL                    0x0
+#define WAKE_AOWAKE_STATUS_W_95_SCR                     EVENT_CNTRL_SCR_95
+#define WAKE_AOWAKE_STATUS_W_95_SCRREG                  WAKE_SCR_EVENT_CNTRL_SCR_95
+#define WAKE_AOWAKE_STATUS_W_95_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_STATUS_W_95_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_95_RESET_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_95_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_95_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_95_READ_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_95_WRITE_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_95_CLEAR_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_95_CLEAR_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_STATUS_W_95_CLEAR_SHIFT)
+#define WAKE_AOWAKE_STATUS_W_95_CLEAR_RANGE                     0:0
+#define WAKE_AOWAKE_STATUS_W_95_CLEAR_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_95_CLEAR_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_95_CLEAR_WOFFSET                   0x0
+#define WAKE_AOWAKE_STATUS_W_95_CLEAR_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_95_CLEAR_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_95_CLEAR_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_95_CLEAR_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_95_CLEAR_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_W_95_CLEAR_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_STATUS_W_95_CLEAR_INIT_ENUM                 FALSE
+#define WAKE_AOWAKE_STATUS_W_95_CLEAR_FALSE                     MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_STATUS_W_95_CLEAR_TRUE                      MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_STATUS_R_31_0_0
+#define WAKE_AOWAKE_STATUS_R_31_0_0                     MK_ADDR_CONST(0x48c)
+#define WAKE_AOWAKE_STATUS_R_31_0_0_SECURE                      0x0
+#define WAKE_AOWAKE_STATUS_R_31_0_0_DUAL                        0x0
+#define WAKE_AOWAKE_STATUS_R_31_0_0_SCR                         0
+#define WAKE_AOWAKE_STATUS_R_31_0_0_SCRREG                      0
+#define WAKE_AOWAKE_STATUS_R_31_0_0_WORD_COUNT                  0x1
+#define WAKE_AOWAKE_STATUS_R_31_0_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_31_0_0_RESET_MASK                  MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_STATUS_R_31_0_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_31_0_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_31_0_0_READ_MASK                   MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_STATUS_R_31_0_0_WRITE_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_31_0_0_STATUS_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_R_31_0_0_STATUS_FIELD                        MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_STATUS_R_31_0_0_STATUS_SHIFT)
+#define WAKE_AOWAKE_STATUS_R_31_0_0_STATUS_RANGE                        31:0
+#define WAKE_AOWAKE_STATUS_R_31_0_0_STATUS_MSB                  MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_STATUS_R_31_0_0_STATUS_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_R_31_0_0_STATUS_WOFFSET                      0x0
+#define WAKE_AOWAKE_STATUS_R_31_0_0_STATUS_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_31_0_0_STATUS_DEFAULT_MASK                 MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_STATUS_R_31_0_0_STATUS_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_31_0_0_STATUS_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_31_0_0_STATUS_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_31_0_0_STATUS_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_STATUS_R_63_32_0
+#define WAKE_AOWAKE_STATUS_R_63_32_0                    MK_ADDR_CONST(0x490)
+#define WAKE_AOWAKE_STATUS_R_63_32_0_SECURE                     0x0
+#define WAKE_AOWAKE_STATUS_R_63_32_0_DUAL                       0x0
+#define WAKE_AOWAKE_STATUS_R_63_32_0_SCR                        0
+#define WAKE_AOWAKE_STATUS_R_63_32_0_SCRREG                     0
+#define WAKE_AOWAKE_STATUS_R_63_32_0_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_STATUS_R_63_32_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_63_32_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_STATUS_R_63_32_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_63_32_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_63_32_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_STATUS_R_63_32_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_63_32_0_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_R_63_32_0_STATUS_FIELD                       MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_STATUS_R_63_32_0_STATUS_SHIFT)
+#define WAKE_AOWAKE_STATUS_R_63_32_0_STATUS_RANGE                       31:0
+#define WAKE_AOWAKE_STATUS_R_63_32_0_STATUS_MSB                 MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_STATUS_R_63_32_0_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_R_63_32_0_STATUS_WOFFSET                     0x0
+#define WAKE_AOWAKE_STATUS_R_63_32_0_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_63_32_0_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_STATUS_R_63_32_0_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_63_32_0_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_63_32_0_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_63_32_0_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_STATUS_R_95_64_0
+#define WAKE_AOWAKE_STATUS_R_95_64_0                    MK_ADDR_CONST(0x494)
+#define WAKE_AOWAKE_STATUS_R_95_64_0_SECURE                     0x0
+#define WAKE_AOWAKE_STATUS_R_95_64_0_DUAL                       0x0
+#define WAKE_AOWAKE_STATUS_R_95_64_0_SCR                        0
+#define WAKE_AOWAKE_STATUS_R_95_64_0_SCRREG                     0
+#define WAKE_AOWAKE_STATUS_R_95_64_0_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_STATUS_R_95_64_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_95_64_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_STATUS_R_95_64_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_95_64_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_95_64_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_STATUS_R_95_64_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_95_64_0_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_R_95_64_0_STATUS_FIELD                       MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_STATUS_R_95_64_0_STATUS_SHIFT)
+#define WAKE_AOWAKE_STATUS_R_95_64_0_STATUS_RANGE                       31:0
+#define WAKE_AOWAKE_STATUS_R_95_64_0_STATUS_MSB                 MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_STATUS_R_95_64_0_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_STATUS_R_95_64_0_STATUS_WOFFSET                     0x0
+#define WAKE_AOWAKE_STATUS_R_95_64_0_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_95_64_0_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_STATUS_R_95_64_0_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_95_64_0_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_95_64_0_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_STATUS_R_95_64_0_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_LATCH_SW_0
+#define WAKE_AOWAKE_LATCH_SW_0                  MK_ADDR_CONST(0x498)
+#define WAKE_AOWAKE_LATCH_SW_0_SECURE                   0x0
+#define WAKE_AOWAKE_LATCH_SW_0_DUAL                     0x0
+#define WAKE_AOWAKE_LATCH_SW_0_SCR                      SW_CNTRL_SCR_0
+#define WAKE_AOWAKE_LATCH_SW_0_SCRREG                   WAKE_SCR_SW_CNTRL_SCR_0
+#define WAKE_AOWAKE_LATCH_SW_0_WORD_COUNT                       0x1
+#define WAKE_AOWAKE_LATCH_SW_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_LATCH_SW_0_RESET_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_LATCH_SW_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_LATCH_SW_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_LATCH_SW_0_READ_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_LATCH_SW_0_WRITE_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_LATCH_SW_0_LATCH_SWEN_SHIFT                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_LATCH_SW_0_LATCH_SWEN_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_LATCH_SW_0_LATCH_SWEN_SHIFT)
+#define WAKE_AOWAKE_LATCH_SW_0_LATCH_SWEN_RANGE                 0:0
+#define WAKE_AOWAKE_LATCH_SW_0_LATCH_SWEN_MSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_LATCH_SW_0_LATCH_SWEN_LSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_LATCH_SW_0_LATCH_SWEN_WOFFSET                       0x0
+#define WAKE_AOWAKE_LATCH_SW_0_LATCH_SWEN_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_LATCH_SW_0_LATCH_SWEN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_LATCH_SW_0_LATCH_SWEN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_LATCH_SW_0_LATCH_SWEN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_LATCH_SW_0_LATCH_SWEN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_LATCH_SW_0_LATCH_SWEN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_LATCH_SW_0_LATCH_SWEN_INIT_ENUM                     FALSE
+#define WAKE_AOWAKE_LATCH_SW_0_LATCH_SWEN_FALSE                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_LATCH_SW_0_LATCH_SWEN_TRUE                  MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_SW_STATUS_W_0
+#define WAKE_AOWAKE_SW_STATUS_W_0                       MK_ADDR_CONST(0x49c)
+#define WAKE_AOWAKE_SW_STATUS_W_0_SECURE                        0x0
+#define WAKE_AOWAKE_SW_STATUS_W_0_DUAL                  0x0
+#define WAKE_AOWAKE_SW_STATUS_W_0_SCR                   SW_CNTRL_SCR_0
+#define WAKE_AOWAKE_SW_STATUS_W_0_SCRREG                        WAKE_SCR_SW_CNTRL_SCR_0
+#define WAKE_AOWAKE_SW_STATUS_W_0_WORD_COUNT                    0x1
+#define WAKE_AOWAKE_SW_STATUS_W_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_W_0_RESET_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_SW_STATUS_W_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_W_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_W_0_READ_MASK                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_SW_STATUS_W_0_WRITE_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_SW_STATUS_W_0_CLEAR_SHIFT                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SW_STATUS_W_0_CLEAR_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_SW_STATUS_W_0_CLEAR_SHIFT)
+#define WAKE_AOWAKE_SW_STATUS_W_0_CLEAR_RANGE                   0:0
+#define WAKE_AOWAKE_SW_STATUS_W_0_CLEAR_MSB                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SW_STATUS_W_0_CLEAR_LSB                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SW_STATUS_W_0_CLEAR_WOFFSET                 0x0
+#define WAKE_AOWAKE_SW_STATUS_W_0_CLEAR_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_W_0_CLEAR_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_SW_STATUS_W_0_CLEAR_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_W_0_CLEAR_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_W_0_CLEAR_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_W_0_CLEAR_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_SW_STATUS_W_0_CLEAR_INIT_ENUM                       FALSE
+#define WAKE_AOWAKE_SW_STATUS_W_0_CLEAR_FALSE                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_SW_STATUS_W_0_CLEAR_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_SW_STATUS_31_0_0
+#define WAKE_AOWAKE_SW_STATUS_31_0_0                    MK_ADDR_CONST(0x4a0)
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_SECURE                     0x0
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_DUAL                       0x0
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_SCR                        0
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_SCRREG                     0
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_STATUS_SHIFT                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_STATUS_FIELD                       MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_SW_STATUS_31_0_0_STATUS_SHIFT)
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_STATUS_RANGE                       31:0
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_STATUS_MSB                 MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_STATUS_LSB                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_STATUS_WOFFSET                     0x0
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_STATUS_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_STATUS_DEFAULT_MASK                        MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_STATUS_SW_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_STATUS_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_STATUS_PARITY_PROTECTION                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_31_0_0_STATUS_PLATFORM_DEPENDENT                  MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_SW_STATUS_63_32_0
+#define WAKE_AOWAKE_SW_STATUS_63_32_0                   MK_ADDR_CONST(0x4a4)
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_SECURE                    0x0
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_DUAL                      0x0
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_SCR                       0
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_SCRREG                    0
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_STATUS_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_STATUS_FIELD                      MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_SW_STATUS_63_32_0_STATUS_SHIFT)
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_STATUS_RANGE                      31:0
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_STATUS_MSB                        MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_STATUS_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_STATUS_WOFFSET                    0x0
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_63_32_0_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_SW_STATUS_95_64_0
+#define WAKE_AOWAKE_SW_STATUS_95_64_0                   MK_ADDR_CONST(0x4a8)
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_SECURE                    0x0
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_DUAL                      0x0
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_SCR                       0
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_SCRREG                    0
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_RESET_MASK                        MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_READ_MASK                         MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_STATUS_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_STATUS_FIELD                      MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_SW_STATUS_95_64_0_STATUS_SHIFT)
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_STATUS_RANGE                      31:0
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_STATUS_MSB                        MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_STATUS_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_STATUS_WOFFSET                    0x0
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_STATUS_95_64_0_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_TIER1_CTRL_0
+#define WAKE_AOWAKE_TIER1_CTRL_0                        MK_ADDR_CONST(0x4ac)
+#define WAKE_AOWAKE_TIER1_CTRL_0_SECURE                         0x0
+#define WAKE_AOWAKE_TIER1_CTRL_0_DUAL                   0x0
+#define WAKE_AOWAKE_TIER1_CTRL_0_SCR                    TIER_INT_CTRL_SCR_0
+#define WAKE_AOWAKE_TIER1_CTRL_0_SCRREG                         WAKE_SCR_TIER_INT_CTRL_SCR_0
+#define WAKE_AOWAKE_TIER1_CTRL_0_WORD_COUNT                     0x1
+#define WAKE_AOWAKE_TIER1_CTRL_0_RESET_VAL                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_TIER1_CTRL_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_TIER1_CTRL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_CTRL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_CTRL_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_TIER1_CTRL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_TIER1_CTRL_0_INT_EN_SHIFT                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER1_CTRL_0_INT_EN_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_TIER1_CTRL_0_INT_EN_SHIFT)
+#define WAKE_AOWAKE_TIER1_CTRL_0_INT_EN_RANGE                   0:0
+#define WAKE_AOWAKE_TIER1_CTRL_0_INT_EN_MSB                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER1_CTRL_0_INT_EN_LSB                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER1_CTRL_0_INT_EN_WOFFSET                 0x0
+#define WAKE_AOWAKE_TIER1_CTRL_0_INT_EN_DEFAULT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_TIER1_CTRL_0_INT_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_TIER1_CTRL_0_INT_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_CTRL_0_INT_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_CTRL_0_INT_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_CTRL_0_INT_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_TIER1_CTRL_0_INT_EN_INIT_ENUM                       TRUE
+#define WAKE_AOWAKE_TIER1_CTRL_0_INT_EN_FALSE                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_TIER1_CTRL_0_INT_EN_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_TIER2_CTRL_0
+#define WAKE_AOWAKE_TIER2_CTRL_0                        MK_ADDR_CONST(0x4b0)
+#define WAKE_AOWAKE_TIER2_CTRL_0_SECURE                         0x0
+#define WAKE_AOWAKE_TIER2_CTRL_0_DUAL                   0x0
+#define WAKE_AOWAKE_TIER2_CTRL_0_SCR                    TIER_INT_CTRL_SCR_0
+#define WAKE_AOWAKE_TIER2_CTRL_0_SCRREG                         WAKE_SCR_TIER_INT_CTRL_SCR_0
+#define WAKE_AOWAKE_TIER2_CTRL_0_WORD_COUNT                     0x1
+#define WAKE_AOWAKE_TIER2_CTRL_0_RESET_VAL                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_TIER2_CTRL_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_TIER2_CTRL_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_CTRL_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_CTRL_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_TIER2_CTRL_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_TIER2_CTRL_0_INT_EN_SHIFT                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER2_CTRL_0_INT_EN_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_TIER2_CTRL_0_INT_EN_SHIFT)
+#define WAKE_AOWAKE_TIER2_CTRL_0_INT_EN_RANGE                   0:0
+#define WAKE_AOWAKE_TIER2_CTRL_0_INT_EN_MSB                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER2_CTRL_0_INT_EN_LSB                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER2_CTRL_0_INT_EN_WOFFSET                 0x0
+#define WAKE_AOWAKE_TIER2_CTRL_0_INT_EN_DEFAULT                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_TIER2_CTRL_0_INT_EN_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_TIER2_CTRL_0_INT_EN_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_CTRL_0_INT_EN_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_CTRL_0_INT_EN_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_CTRL_0_INT_EN_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_TIER2_CTRL_0_INT_EN_INIT_ENUM                       TRUE
+#define WAKE_AOWAKE_TIER2_CTRL_0_INT_EN_FALSE                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_TIER2_CTRL_0_INT_EN_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_TIER0_ROUTING_31_0_0
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0                        MK_ADDR_CONST(0x4b4)
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SECURE                         0x0
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_DUAL                   0x0
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SCR                    TIER0_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SCRREG                         WAKE_SCR_TIER0_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_WORD_COUNT                     0x1
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SEL_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SEL_FIELD                      MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SEL_SHIFT)
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SEL_RANGE                      31:0
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SEL_MSB                        MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SEL_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SEL_WOFFSET                    0x0
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SEL_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SEL_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_31_0_0_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_TIER0_ROUTING_63_32_0
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0                       MK_ADDR_CONST(0x4b8)
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SECURE                        0x0
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_DUAL                  0x0
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SCR                   TIER0_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SCRREG                        WAKE_SCR_TIER0_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_WORD_COUNT                    0x1
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SEL_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SEL_FIELD                     MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SEL_SHIFT)
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SEL_RANGE                     31:0
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SEL_MSB                       MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SEL_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SEL_WOFFSET                   0x0
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SEL_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SEL_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_63_32_0_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_TIER0_ROUTING_95_64_0
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0                       MK_ADDR_CONST(0x4bc)
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SECURE                        0x0
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_DUAL                  0x0
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SCR                   TIER0_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SCRREG                        WAKE_SCR_TIER0_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_WORD_COUNT                    0x1
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SEL_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SEL_FIELD                     MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SEL_SHIFT)
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SEL_RANGE                     31:0
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SEL_MSB                       MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SEL_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SEL_WOFFSET                   0x0
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SEL_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SEL_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER0_ROUTING_95_64_0_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_TIER1_ROUTING_31_0_0
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0                        MK_ADDR_CONST(0x4c0)
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SECURE                         0x0
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_DUAL                   0x0
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SCR                    TIER1_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SCRREG                         WAKE_SCR_TIER1_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_WORD_COUNT                     0x1
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SEL_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SEL_FIELD                      MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SEL_SHIFT)
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SEL_RANGE                      31:0
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SEL_MSB                        MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SEL_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SEL_WOFFSET                    0x0
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SEL_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SEL_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_31_0_0_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_TIER1_ROUTING_63_32_0
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0                       MK_ADDR_CONST(0x4c4)
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SECURE                        0x0
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_DUAL                  0x0
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SCR                   TIER1_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SCRREG                        WAKE_SCR_TIER1_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_WORD_COUNT                    0x1
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SEL_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SEL_FIELD                     MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SEL_SHIFT)
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SEL_RANGE                     31:0
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SEL_MSB                       MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SEL_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SEL_WOFFSET                   0x0
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SEL_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SEL_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_63_32_0_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_TIER1_ROUTING_95_64_0
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0                       MK_ADDR_CONST(0x4c8)
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SECURE                        0x0
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_DUAL                  0x0
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SCR                   TIER1_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SCRREG                        WAKE_SCR_TIER1_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_WORD_COUNT                    0x1
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SEL_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SEL_FIELD                     MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SEL_SHIFT)
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SEL_RANGE                     31:0
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SEL_MSB                       MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SEL_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SEL_WOFFSET                   0x0
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SEL_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SEL_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER1_ROUTING_95_64_0_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_TIER2_ROUTING_31_0_0
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0                        MK_ADDR_CONST(0x4cc)
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SECURE                         0x0
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_DUAL                   0x0
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SCR                    TIER2_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SCRREG                         WAKE_SCR_TIER2_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_WORD_COUNT                     0x1
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_RESET_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_READ_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_WRITE_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SEL_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SEL_FIELD                      MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SEL_SHIFT)
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SEL_RANGE                      31:0
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SEL_MSB                        MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SEL_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SEL_WOFFSET                    0x0
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SEL_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SEL_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SEL_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SEL_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SEL_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_31_0_0_SEL_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_TIER2_ROUTING_63_32_0
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0                       MK_ADDR_CONST(0x4d0)
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SECURE                        0x0
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_DUAL                  0x0
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SCR                   TIER2_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SCRREG                        WAKE_SCR_TIER2_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_WORD_COUNT                    0x1
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SEL_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SEL_FIELD                     MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SEL_SHIFT)
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SEL_RANGE                     31:0
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SEL_MSB                       MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SEL_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SEL_WOFFSET                   0x0
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SEL_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SEL_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_63_32_0_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_TIER2_ROUTING_95_64_0
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0                       MK_ADDR_CONST(0x4d4)
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SECURE                        0x0
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_DUAL                  0x0
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SCR                   TIER2_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SCRREG                        WAKE_SCR_TIER2_ROUTING_SCR_0
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_WORD_COUNT                    0x1
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SEL_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SEL_FIELD                     MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SEL_SHIFT)
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SEL_RANGE                     31:0
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SEL_MSB                       MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SEL_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SEL_WOFFSET                   0x0
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SEL_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SEL_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SEL_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SEL_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SEL_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TIER2_ROUTING_95_64_0_SEL_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0                     MK_ADDR_CONST(0x4d8)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_SECURE                      0x0
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_DUAL                        0x0
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_SCR                         SW_CNTRL_SCR_0
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_SCRREG                      WAKE_SCR_SW_CNTRL_SCR_0
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_WORD_COUNT                  0x1
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_RESET_VAL                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_RESET_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_SW_DEFAULT_VAL                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_SW_DEFAULT_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_READ_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_WRITE_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_ENABLE_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_ENABLE_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_ENABLE_SHIFT)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_ENABLE_RANGE                        0:0
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_ENABLE_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_ENABLE_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_ENABLE_WOFFSET                      0x0
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_ENABLE_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_ENABLE_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_ENABLE_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_ENABLE_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_ENABLE_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_ENABLE_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_ENABLE_INIT_ENUM                    FALSE
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_ENABLE_FALSE                        MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0_ENABLE_TRUE                 MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_COAL_GRP0_0
+#define WAKE_AOWAKE_COAL_GRP0_0                 MK_ADDR_CONST(0x4dc)
+#define WAKE_AOWAKE_COAL_GRP0_0_SECURE                  0x0
+#define WAKE_AOWAKE_COAL_GRP0_0_DUAL                    0x0
+#define WAKE_AOWAKE_COAL_GRP0_0_SCR                     COAL_SCR_0
+#define WAKE_AOWAKE_COAL_GRP0_0_SCRREG                  WAKE_SCR_COAL_SCR_0
+#define WAKE_AOWAKE_COAL_GRP0_0_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_COAL_GRP0_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_COAL_GRP0_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_COAL_GRP0_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_COAL_GRP0_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_COAL_GRP0_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_COAL_GRP0_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_COAL_GRP0_0_TIMER_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_COAL_GRP0_0_TIMER_FIELD                     MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_COAL_GRP0_0_TIMER_SHIFT)
+#define WAKE_AOWAKE_COAL_GRP0_0_TIMER_RANGE                     31:0
+#define WAKE_AOWAKE_COAL_GRP0_0_TIMER_MSB                       MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_COAL_GRP0_0_TIMER_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_COAL_GRP0_0_TIMER_WOFFSET                   0x0
+#define WAKE_AOWAKE_COAL_GRP0_0_TIMER_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_COAL_GRP0_0_TIMER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_COAL_GRP0_0_TIMER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_COAL_GRP0_0_TIMER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_COAL_GRP0_0_TIMER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_COAL_GRP0_0_TIMER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_COAL_GRP1_0
+#define WAKE_AOWAKE_COAL_GRP1_0                 MK_ADDR_CONST(0x4e0)
+#define WAKE_AOWAKE_COAL_GRP1_0_SECURE                  0x0
+#define WAKE_AOWAKE_COAL_GRP1_0_DUAL                    0x0
+#define WAKE_AOWAKE_COAL_GRP1_0_SCR                     COAL_SCR_0
+#define WAKE_AOWAKE_COAL_GRP1_0_SCRREG                  WAKE_SCR_COAL_SCR_0
+#define WAKE_AOWAKE_COAL_GRP1_0_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_COAL_GRP1_0_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_COAL_GRP1_0_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_COAL_GRP1_0_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_COAL_GRP1_0_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_COAL_GRP1_0_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_COAL_GRP1_0_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_COAL_GRP1_0_TIMER_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_COAL_GRP1_0_TIMER_FIELD                     MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_COAL_GRP1_0_TIMER_SHIFT)
+#define WAKE_AOWAKE_COAL_GRP1_0_TIMER_RANGE                     31:0
+#define WAKE_AOWAKE_COAL_GRP1_0_TIMER_MSB                       MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_COAL_GRP1_0_TIMER_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_COAL_GRP1_0_TIMER_WOFFSET                   0x0
+#define WAKE_AOWAKE_COAL_GRP1_0_TIMER_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_COAL_GRP1_0_TIMER_DEFAULT_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_COAL_GRP1_0_TIMER_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_COAL_GRP1_0_TIMER_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_COAL_GRP1_0_TIMER_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_COAL_GRP1_0_TIMER_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_TSC_CTRL_0
+#define WAKE_AOWAKE_TSC_CTRL_0                  MK_ADDR_CONST(0x4e4)
+#define WAKE_AOWAKE_TSC_CTRL_0_SECURE                   0x0
+#define WAKE_AOWAKE_TSC_CTRL_0_DUAL                     0x0
+#define WAKE_AOWAKE_TSC_CTRL_0_SCR                      TSC_CNTRL_SCR_0
+#define WAKE_AOWAKE_TSC_CTRL_0_SCRREG                   WAKE_SCR_TSC_CNTRL_SCR_0
+#define WAKE_AOWAKE_TSC_CTRL_0_WORD_COUNT                       0x1
+#define WAKE_AOWAKE_TSC_CTRL_0_RESET_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TSC_CTRL_0_RESET_MASK                       MK_MASK_CONST(0x7f)
+#define WAKE_AOWAKE_TSC_CTRL_0_SW_DEFAULT_VAL                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TSC_CTRL_0_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TSC_CTRL_0_READ_MASK                        MK_MASK_CONST(0x7f)
+#define WAKE_AOWAKE_TSC_CTRL_0_WRITE_MASK                       MK_MASK_CONST(0x7f)
+#define WAKE_AOWAKE_TSC_CTRL_0_WAKE_INDEX_SHIFT                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TSC_CTRL_0_WAKE_INDEX_FIELD                 MK_FIELD_CONST(0x7f, WAKE_AOWAKE_TSC_CTRL_0_WAKE_INDEX_SHIFT)
+#define WAKE_AOWAKE_TSC_CTRL_0_WAKE_INDEX_RANGE                 6:0
+#define WAKE_AOWAKE_TSC_CTRL_0_WAKE_INDEX_MSB                   MK_SHIFT_CONST(6)
+#define WAKE_AOWAKE_TSC_CTRL_0_WAKE_INDEX_LSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TSC_CTRL_0_WAKE_INDEX_WOFFSET                       0x0
+#define WAKE_AOWAKE_TSC_CTRL_0_WAKE_INDEX_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TSC_CTRL_0_WAKE_INDEX_DEFAULT_MASK                  MK_MASK_CONST(0x7f)
+#define WAKE_AOWAKE_TSC_CTRL_0_WAKE_INDEX_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TSC_CTRL_0_WAKE_INDEX_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TSC_CTRL_0_WAKE_INDEX_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TSC_CTRL_0_WAKE_INDEX_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_TSC_SNAP_VALUE_0
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0                    MK_ADDR_CONST(0x4e8)
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_SECURE                     0x0
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_DUAL                       0x0
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_SCR                        0
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_SCRREG                     0
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_RESET_MASK                         MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_READ_MASK                  MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_WRITE_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_DATA_SHIFT                 MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_DATA_FIELD                 MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_TSC_SNAP_VALUE_0_DATA_SHIFT)
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_DATA_RANGE                 31:0
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_DATA_MSB                   MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_DATA_LSB                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_DATA_WOFFSET                       0x0
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_DATA_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_DATA_DEFAULT_MASK                  MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_DATA_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_DATA_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_DATA_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_TSC_SNAP_VALUE_0_DATA_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_DELAY_CELL_CTRL_0
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0                   MK_ADDR_CONST(0x4ec)
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_SECURE                    0x0
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_DUAL                      0x0
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_SCR                       GLB_CNTRL_SCR_0
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_SCRREG                    WAKE_SCR_GLB_CNTRL_SCR_0
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_RESET_VAL                         MK_MASK_CONST(0x22)
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_RESET_MASK                        MK_MASK_CONST(0x3f)
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_READ_MASK                         MK_MASK_CONST(0x3f)
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_WRITE_MASK                        MK_MASK_CONST(0x3f)
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_SIG_DELAY_BUF_SEL_SHIFT                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_SIG_DELAY_BUF_SEL_FIELD                   MK_FIELD_CONST(0x3f, WAKE_AOWAKE_DELAY_CELL_CTRL_0_SIG_DELAY_BUF_SEL_SHIFT)
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_SIG_DELAY_BUF_SEL_RANGE                   5:0
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_SIG_DELAY_BUF_SEL_MSB                     MK_SHIFT_CONST(5)
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_SIG_DELAY_BUF_SEL_LSB                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_SIG_DELAY_BUF_SEL_WOFFSET                 0x0
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_SIG_DELAY_BUF_SEL_DEFAULT                 MK_MASK_CONST(0x22)
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_SIG_DELAY_BUF_SEL_DEFAULT_MASK                    MK_MASK_CONST(0x3f)
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_SIG_DELAY_BUF_SEL_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_SIG_DELAY_BUF_SEL_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_SIG_DELAY_BUF_SEL_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DELAY_CELL_CTRL_0_SIG_DELAY_BUF_SEL_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_DET_EN_0
+#define WAKE_AOWAKE_DET_EN_0                    MK_ADDR_CONST(0x4f0)
+#define WAKE_AOWAKE_DET_EN_0_SECURE                     0x0
+#define WAKE_AOWAKE_DET_EN_0_DUAL                       0x0
+#define WAKE_AOWAKE_DET_EN_0_SCR                        GLB_CNTRL_SCR_0
+#define WAKE_AOWAKE_DET_EN_0_SCRREG                     WAKE_SCR_GLB_CNTRL_SCR_0
+#define WAKE_AOWAKE_DET_EN_0_WORD_COUNT                         0x1
+#define WAKE_AOWAKE_DET_EN_0_RESET_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DET_EN_0_RESET_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_DET_EN_0_SW_DEFAULT_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DET_EN_0_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DET_EN_0_READ_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_DET_EN_0_WRITE_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_DET_EN_0_DET_ENABLE_SHIFT                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_DET_EN_0_DET_ENABLE_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_DET_EN_0_DET_ENABLE_SHIFT)
+#define WAKE_AOWAKE_DET_EN_0_DET_ENABLE_RANGE                   0:0
+#define WAKE_AOWAKE_DET_EN_0_DET_ENABLE_MSB                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_DET_EN_0_DET_ENABLE_LSB                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_DET_EN_0_DET_ENABLE_WOFFSET                 0x0
+#define WAKE_AOWAKE_DET_EN_0_DET_ENABLE_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DET_EN_0_DET_ENABLE_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_DET_EN_0_DET_ENABLE_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DET_EN_0_DET_ENABLE_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DET_EN_0_DET_ENABLE_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DET_EN_0_DET_ENABLE_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_DET_EN_0_DET_ENABLE_INIT_ENUM                       FALSE
+#define WAKE_AOWAKE_DET_EN_0_DET_ENABLE_FALSE                   MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_DET_EN_0_DET_ENABLE_TRUE                    MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CTRL_0
+#define WAKE_AOWAKE_CTRL_0                      MK_ADDR_CONST(0x4f4)
+#define WAKE_AOWAKE_CTRL_0_SECURE                       0x0
+#define WAKE_AOWAKE_CTRL_0_DUAL                         0x0
+#define WAKE_AOWAKE_CTRL_0_SCR                  GLB_CNTRL_SCR_0
+#define WAKE_AOWAKE_CTRL_0_SCRREG                       WAKE_SCR_GLB_CNTRL_SCR_0
+#define WAKE_AOWAKE_CTRL_0_WORD_COUNT                   0x1
+#define WAKE_AOWAKE_CTRL_0_RESET_VAL                    MK_MASK_CONST(0x2)
+#define WAKE_AOWAKE_CTRL_0_RESET_MASK                   MK_MASK_CONST(0x3)
+#define WAKE_AOWAKE_CTRL_0_SW_DEFAULT_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CTRL_0_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CTRL_0_READ_MASK                    MK_MASK_CONST(0x3)
+#define WAKE_AOWAKE_CTRL_0_WRITE_MASK                   MK_MASK_CONST(0x3)
+#define WAKE_AOWAKE_CTRL_0_INTR_POLARITY_SHIFT                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CTRL_0_INTR_POLARITY_FIELD                  MK_FIELD_CONST(0x1, WAKE_AOWAKE_CTRL_0_INTR_POLARITY_SHIFT)
+#define WAKE_AOWAKE_CTRL_0_INTR_POLARITY_RANGE                  0:0
+#define WAKE_AOWAKE_CTRL_0_INTR_POLARITY_MSB                    MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CTRL_0_INTR_POLARITY_LSB                    MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CTRL_0_INTR_POLARITY_WOFFSET                        0x0
+#define WAKE_AOWAKE_CTRL_0_INTR_POLARITY_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CTRL_0_INTR_POLARITY_DEFAULT_MASK                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CTRL_0_INTR_POLARITY_SW_DEFAULT                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CTRL_0_INTR_POLARITY_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CTRL_0_INTR_POLARITY_PARITY_PROTECTION                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CTRL_0_INTR_POLARITY_PLATFORM_DEPENDENT                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CTRL_0_INTR_POLARITY_INIT_ENUM                      FALSE
+#define WAKE_AOWAKE_CTRL_0_INTR_POLARITY_FALSE                  MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CTRL_0_INTR_POLARITY_TRUE                   MK_ENUM_CONST(1)
+
+#define WAKE_AOWAKE_CTRL_0_GLOBAL_COAL_EN_SHIFT                 MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CTRL_0_GLOBAL_COAL_EN_FIELD                 MK_FIELD_CONST(0x1, WAKE_AOWAKE_CTRL_0_GLOBAL_COAL_EN_SHIFT)
+#define WAKE_AOWAKE_CTRL_0_GLOBAL_COAL_EN_RANGE                 1:1
+#define WAKE_AOWAKE_CTRL_0_GLOBAL_COAL_EN_MSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CTRL_0_GLOBAL_COAL_EN_LSB                   MK_SHIFT_CONST(1)
+#define WAKE_AOWAKE_CTRL_0_GLOBAL_COAL_EN_WOFFSET                       0x0
+#define WAKE_AOWAKE_CTRL_0_GLOBAL_COAL_EN_DEFAULT                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CTRL_0_GLOBAL_COAL_EN_DEFAULT_MASK                  MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CTRL_0_GLOBAL_COAL_EN_SW_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CTRL_0_GLOBAL_COAL_EN_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CTRL_0_GLOBAL_COAL_EN_PARITY_PROTECTION                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CTRL_0_GLOBAL_COAL_EN_PLATFORM_DEPENDENT                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_CTRL_0_GLOBAL_COAL_EN_INIT_ENUM                     TRUE
+#define WAKE_AOWAKE_CTRL_0_GLOBAL_COAL_EN_FALSE                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_CTRL_0_GLOBAL_COAL_EN_TRUE                  MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_CYA_0
+#define WAKE_AOWAKE_CYA_0                       MK_ADDR_CONST(0x4f8)
+#define WAKE_AOWAKE_CYA_0_SECURE                        0x0
+#define WAKE_AOWAKE_CYA_0_DUAL                  0x0
+#define WAKE_AOWAKE_CYA_0_SCR                   0
+#define WAKE_AOWAKE_CYA_0_SCRREG                        0
+#define WAKE_AOWAKE_CYA_0_WORD_COUNT                    0x1
+#define WAKE_AOWAKE_CYA_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_CYA_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_CYA_0_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_CYA_0_DATA_SHIFT                    MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CYA_0_DATA_FIELD                    MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_CYA_0_DATA_SHIFT)
+#define WAKE_AOWAKE_CYA_0_DATA_RANGE                    31:0
+#define WAKE_AOWAKE_CYA_0_DATA_MSB                      MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_CYA_0_DATA_LSB                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CYA_0_DATA_WOFFSET                  0x0
+#define WAKE_AOWAKE_CYA_0_DATA_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_0_DATA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_CYA_0_DATA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_0_DATA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_0_DATA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_0_DATA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_CYA
+#define WAKE_AOWAKE_CYA                 MK_ADDR_CONST(0x4f8)
+#define WAKE_AOWAKE_CYA_SECURE                  0x0
+#define WAKE_AOWAKE_CYA_DUAL                    0x0
+#define WAKE_AOWAKE_CYA_SCR                     0
+#define WAKE_AOWAKE_CYA_SCRREG                  0
+#define WAKE_AOWAKE_CYA_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_CYA_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_CYA_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_CYA_WRITE_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_CYA_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CYA_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_CYA_DATA_SHIFT)
+#define WAKE_AOWAKE_CYA_DATA_RANGE                      31:0
+#define WAKE_AOWAKE_CYA_DATA_MSB                        MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_CYA_DATA_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CYA_DATA_WOFFSET                    0x0
+#define WAKE_AOWAKE_CYA_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_CYA_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_CYA_1
+#define WAKE_AOWAKE_CYA_1                       MK_ADDR_CONST(0x4fc)
+#define WAKE_AOWAKE_CYA_1_SECURE                        0x0
+#define WAKE_AOWAKE_CYA_1_DUAL                  0x0
+#define WAKE_AOWAKE_CYA_1_SCR                   0
+#define WAKE_AOWAKE_CYA_1_SCRREG                        0
+#define WAKE_AOWAKE_CYA_1_WORD_COUNT                    0x1
+#define WAKE_AOWAKE_CYA_1_RESET_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_1_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_CYA_1_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_1_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_CYA_1_WRITE_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_CYA_1_DATA_SHIFT                    MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CYA_1_DATA_FIELD                    MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_CYA_1_DATA_SHIFT)
+#define WAKE_AOWAKE_CYA_1_DATA_RANGE                    31:0
+#define WAKE_AOWAKE_CYA_1_DATA_MSB                      MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_CYA_1_DATA_LSB                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_CYA_1_DATA_WOFFSET                  0x0
+#define WAKE_AOWAKE_CYA_1_DATA_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_1_DATA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_CYA_1_DATA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_1_DATA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_1_DATA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_CYA_1_DATA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_DBG_0
+#define WAKE_AOWAKE_DBG_0                       MK_ADDR_CONST(0x500)
+#define WAKE_AOWAKE_DBG_0_SECURE                        0x0
+#define WAKE_AOWAKE_DBG_0_DUAL                  0x0
+#define WAKE_AOWAKE_DBG_0_SCR                   0
+#define WAKE_AOWAKE_DBG_0_SCRREG                        0
+#define WAKE_AOWAKE_DBG_0_WORD_COUNT                    0x1
+#define WAKE_AOWAKE_DBG_0_RESET_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_0_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_DBG_0_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_0_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_0_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_DBG_0_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_0_DATA_SHIFT                    MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_DBG_0_DATA_FIELD                    MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_DBG_0_DATA_SHIFT)
+#define WAKE_AOWAKE_DBG_0_DATA_RANGE                    31:0
+#define WAKE_AOWAKE_DBG_0_DATA_MSB                      MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_DBG_0_DATA_LSB                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_DBG_0_DATA_WOFFSET                  0x0
+#define WAKE_AOWAKE_DBG_0_DATA_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_0_DATA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_DBG_0_DATA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_0_DATA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_0_DATA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_0_DATA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_DBG
+#define WAKE_AOWAKE_DBG                 MK_ADDR_CONST(0x500)
+#define WAKE_AOWAKE_DBG_SECURE                  0x0
+#define WAKE_AOWAKE_DBG_DUAL                    0x0
+#define WAKE_AOWAKE_DBG_SCR                     0
+#define WAKE_AOWAKE_DBG_SCRREG                  0
+#define WAKE_AOWAKE_DBG_WORD_COUNT                      0x1
+#define WAKE_AOWAKE_DBG_RESET_VAL                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_RESET_MASK                      MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_DBG_SW_DEFAULT_VAL                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_SW_DEFAULT_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_READ_MASK                       MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_DBG_WRITE_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_DATA_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_DBG_DATA_FIELD                      MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_DBG_DATA_SHIFT)
+#define WAKE_AOWAKE_DBG_DATA_RANGE                      31:0
+#define WAKE_AOWAKE_DBG_DATA_MSB                        MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_DBG_DATA_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_DBG_DATA_WOFFSET                    0x0
+#define WAKE_AOWAKE_DBG_DATA_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_DATA_DEFAULT_MASK                       MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_DBG_DATA_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_DATA_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_DATA_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_DATA_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_DBG_1
+#define WAKE_AOWAKE_DBG_1                       MK_ADDR_CONST(0x504)
+#define WAKE_AOWAKE_DBG_1_SECURE                        0x0
+#define WAKE_AOWAKE_DBG_1_DUAL                  0x0
+#define WAKE_AOWAKE_DBG_1_SCR                   0
+#define WAKE_AOWAKE_DBG_1_SCRREG                        0
+#define WAKE_AOWAKE_DBG_1_WORD_COUNT                    0x1
+#define WAKE_AOWAKE_DBG_1_RESET_VAL                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_1_RESET_MASK                    MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_DBG_1_SW_DEFAULT_VAL                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_1_SW_DEFAULT_MASK                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_1_READ_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_DBG_1_WRITE_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_1_DATA_SHIFT                    MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_DBG_1_DATA_FIELD                    MK_FIELD_CONST(0xffffffff, WAKE_AOWAKE_DBG_1_DATA_SHIFT)
+#define WAKE_AOWAKE_DBG_1_DATA_RANGE                    31:0
+#define WAKE_AOWAKE_DBG_1_DATA_MSB                      MK_SHIFT_CONST(31)
+#define WAKE_AOWAKE_DBG_1_DATA_LSB                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_DBG_1_DATA_WOFFSET                  0x0
+#define WAKE_AOWAKE_DBG_1_DATA_DEFAULT                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_1_DATA_DEFAULT_MASK                     MK_MASK_CONST(0xffffffff)
+#define WAKE_AOWAKE_DBG_1_DATA_SW_DEFAULT                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_1_DATA_SW_DEFAULT_MASK                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_1_DATA_PARITY_PROTECTION                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_DBG_1_DATA_PLATFORM_DEPENDENT                       MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_SPE_AUTO_MASK_W_0
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0                   MK_ADDR_CONST(0x508)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_SECURE                    0x0
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_DUAL                      0x0
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_SCR                       SPE_AUTO_MASK_SCR_0
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_SCRREG                    WAKE_SCR_SPE_AUTO_MASK_SCR_0
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_READ_MASK                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_WRITE_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_MASK_SHIFT                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_MASK_FIELD                        MK_FIELD_CONST(0x1, WAKE_AOWAKE_SPE_AUTO_MASK_W_0_MASK_SHIFT)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_MASK_RANGE                        0:0
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_MASK_MSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_MASK_LSB                  MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_MASK_WOFFSET                      0x0
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_MASK_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_MASK_DEFAULT_MASK                 MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_MASK_SW_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_MASK_SW_DEFAULT_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_MASK_PARITY_PROTECTION                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_MASK_PLATFORM_DEPENDENT                   MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_MASK_INIT_ENUM                    MASK
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_MASK_MASK                 MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_W_0_MASK_UNMASK                       MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_SPE_AUTO_MASK_R_0
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0                   MK_ADDR_CONST(0x50c)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_SECURE                    0x0
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_DUAL                      0x0
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_SCR                       0
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_SCRREG                    0
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_WORD_COUNT                        0x1
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_RESET_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_RESET_MASK                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_SW_DEFAULT_VAL                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_READ_MASK                         MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_WRITE_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_STATUS_SHIFT                      MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_STATUS_FIELD                      MK_FIELD_CONST(0x1, WAKE_AOWAKE_SPE_AUTO_MASK_R_0_STATUS_SHIFT)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_STATUS_RANGE                      0:0
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_STATUS_MSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_STATUS_LSB                        MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_STATUS_WOFFSET                    0x0
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_STATUS_DEFAULT                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_STATUS_DEFAULT_MASK                       MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_STATUS_SW_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_STATUS_SW_DEFAULT_MASK                    MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_STATUS_PARITY_PROTECTION                  MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_SPE_AUTO_MASK_R_0_STATUS_PLATFORM_DEPENDENT                 MK_MASK_CONST(0x1)
+
+
+// Register WAKE_AOWAKE_HSP_MASK_W_0
+#define WAKE_AOWAKE_HSP_MASK_W_0                        MK_ADDR_CONST(0x510)
+#define WAKE_AOWAKE_HSP_MASK_W_0_SECURE                         0x0
+#define WAKE_AOWAKE_HSP_MASK_W_0_DUAL                   0x0
+#define WAKE_AOWAKE_HSP_MASK_W_0_SCR                    HSP_MASK_SCR_0
+#define WAKE_AOWAKE_HSP_MASK_W_0_SCRREG                         WAKE_SCR_HSP_MASK_SCR_0
+#define WAKE_AOWAKE_HSP_MASK_W_0_WORD_COUNT                     0x1
+#define WAKE_AOWAKE_HSP_MASK_W_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_HSP_MASK_W_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_HSP_MASK_W_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_HSP_MASK_W_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_HSP_MASK_W_0_READ_MASK                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_HSP_MASK_W_0_WRITE_MASK                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_HSP_MASK_W_0_MASK_SHIFT                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_HSP_MASK_W_0_MASK_FIELD                     MK_FIELD_CONST(0x1, WAKE_AOWAKE_HSP_MASK_W_0_MASK_SHIFT)
+#define WAKE_AOWAKE_HSP_MASK_W_0_MASK_RANGE                     0:0
+#define WAKE_AOWAKE_HSP_MASK_W_0_MASK_MSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_HSP_MASK_W_0_MASK_LSB                       MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_HSP_MASK_W_0_MASK_WOFFSET                   0x0
+#define WAKE_AOWAKE_HSP_MASK_W_0_MASK_DEFAULT                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_HSP_MASK_W_0_MASK_DEFAULT_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_HSP_MASK_W_0_MASK_SW_DEFAULT                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_HSP_MASK_W_0_MASK_SW_DEFAULT_MASK                   MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_HSP_MASK_W_0_MASK_PARITY_PROTECTION                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_HSP_MASK_W_0_MASK_PLATFORM_DEPENDENT                        MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_HSP_MASK_W_0_MASK_INIT_ENUM                 MASK
+#define WAKE_AOWAKE_HSP_MASK_W_0_MASK_MASK                      MK_ENUM_CONST(0)
+#define WAKE_AOWAKE_HSP_MASK_W_0_MASK_UNMASK                    MK_ENUM_CONST(1)
+
+
+// Register WAKE_AOWAKE_HSP_MASK_R_0
+#define WAKE_AOWAKE_HSP_MASK_R_0                        MK_ADDR_CONST(0x514)
+#define WAKE_AOWAKE_HSP_MASK_R_0_SECURE                         0x0
+#define WAKE_AOWAKE_HSP_MASK_R_0_DUAL                   0x0
+#define WAKE_AOWAKE_HSP_MASK_R_0_SCR                    0
+#define WAKE_AOWAKE_HSP_MASK_R_0_SCRREG                         0
+#define WAKE_AOWAKE_HSP_MASK_R_0_WORD_COUNT                     0x1
+#define WAKE_AOWAKE_HSP_MASK_R_0_RESET_VAL                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_HSP_MASK_R_0_RESET_MASK                     MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_HSP_MASK_R_0_SW_DEFAULT_VAL                         MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_HSP_MASK_R_0_SW_DEFAULT_MASK                        MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_HSP_MASK_R_0_READ_MASK                      MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_HSP_MASK_R_0_WRITE_MASK                     MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_HSP_MASK_R_0_STATUS_SHIFT                   MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_HSP_MASK_R_0_STATUS_FIELD                   MK_FIELD_CONST(0x1, WAKE_AOWAKE_HSP_MASK_R_0_STATUS_SHIFT)
+#define WAKE_AOWAKE_HSP_MASK_R_0_STATUS_RANGE                   0:0
+#define WAKE_AOWAKE_HSP_MASK_R_0_STATUS_MSB                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_HSP_MASK_R_0_STATUS_LSB                     MK_SHIFT_CONST(0)
+#define WAKE_AOWAKE_HSP_MASK_R_0_STATUS_WOFFSET                 0x0
+#define WAKE_AOWAKE_HSP_MASK_R_0_STATUS_DEFAULT                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_HSP_MASK_R_0_STATUS_DEFAULT_MASK                    MK_MASK_CONST(0x1)
+#define WAKE_AOWAKE_HSP_MASK_R_0_STATUS_SW_DEFAULT                      MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_HSP_MASK_R_0_STATUS_SW_DEFAULT_MASK                 MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_HSP_MASK_R_0_STATUS_PARITY_PROTECTION                       MK_MASK_CONST(0x0)
+#define WAKE_AOWAKE_HSP_MASK_R_0_STATUS_PLATFORM_DEPENDENT                      MK_MASK_CONST(0x1)
+
+
+//
+// REGISTER LIST
+//
+#define LIST_ARWAKE_REGS(_op_) \
+_op_(WAKE_AOWAKE_CNTRL_0) \
+_op_(WAKE_AOWAKE_CNTRL) \
+_op_(WAKE_AOWAKE_CNTRL_1) \
+_op_(WAKE_AOWAKE_CNTRL_2) \
+_op_(WAKE_AOWAKE_CNTRL_3) \
+_op_(WAKE_AOWAKE_CNTRL_4) \
+_op_(WAKE_AOWAKE_CNTRL_5) \
+_op_(WAKE_AOWAKE_CNTRL_6) \
+_op_(WAKE_AOWAKE_CNTRL_7) \
+_op_(WAKE_AOWAKE_CNTRL_8) \
+_op_(WAKE_AOWAKE_CNTRL_9) \
+_op_(WAKE_AOWAKE_CNTRL_10) \
+_op_(WAKE_AOWAKE_CNTRL_11) \
+_op_(WAKE_AOWAKE_CNTRL_12) \
+_op_(WAKE_AOWAKE_CNTRL_13) \
+_op_(WAKE_AOWAKE_CNTRL_14) \
+_op_(WAKE_AOWAKE_CNTRL_15) \
+_op_(WAKE_AOWAKE_CNTRL_16) \
+_op_(WAKE_AOWAKE_CNTRL_17) \
+_op_(WAKE_AOWAKE_CNTRL_18) \
+_op_(WAKE_AOWAKE_CNTRL_19) \
+_op_(WAKE_AOWAKE_CNTRL_20) \
+_op_(WAKE_AOWAKE_CNTRL_21) \
+_op_(WAKE_AOWAKE_CNTRL_22) \
+_op_(WAKE_AOWAKE_CNTRL_23) \
+_op_(WAKE_AOWAKE_CNTRL_24) \
+_op_(WAKE_AOWAKE_CNTRL_25) \
+_op_(WAKE_AOWAKE_CNTRL_26) \
+_op_(WAKE_AOWAKE_CNTRL_27) \
+_op_(WAKE_AOWAKE_CNTRL_28) \
+_op_(WAKE_AOWAKE_CNTRL_29) \
+_op_(WAKE_AOWAKE_CNTRL_30) \
+_op_(WAKE_AOWAKE_CNTRL_31) \
+_op_(WAKE_AOWAKE_CNTRL_32) \
+_op_(WAKE_AOWAKE_CNTRL_33) \
+_op_(WAKE_AOWAKE_CNTRL_34) \
+_op_(WAKE_AOWAKE_CNTRL_35) \
+_op_(WAKE_AOWAKE_CNTRL_36) \
+_op_(WAKE_AOWAKE_CNTRL_37) \
+_op_(WAKE_AOWAKE_CNTRL_38) \
+_op_(WAKE_AOWAKE_CNTRL_39) \
+_op_(WAKE_AOWAKE_CNTRL_40) \
+_op_(WAKE_AOWAKE_CNTRL_41) \
+_op_(WAKE_AOWAKE_CNTRL_42) \
+_op_(WAKE_AOWAKE_CNTRL_43) \
+_op_(WAKE_AOWAKE_CNTRL_44) \
+_op_(WAKE_AOWAKE_CNTRL_45) \
+_op_(WAKE_AOWAKE_CNTRL_46) \
+_op_(WAKE_AOWAKE_CNTRL_47) \
+_op_(WAKE_AOWAKE_CNTRL_48) \
+_op_(WAKE_AOWAKE_CNTRL_49) \
+_op_(WAKE_AOWAKE_CNTRL_50) \
+_op_(WAKE_AOWAKE_CNTRL_51) \
+_op_(WAKE_AOWAKE_CNTRL_52) \
+_op_(WAKE_AOWAKE_CNTRL_53) \
+_op_(WAKE_AOWAKE_CNTRL_54) \
+_op_(WAKE_AOWAKE_CNTRL_55) \
+_op_(WAKE_AOWAKE_CNTRL_56) \
+_op_(WAKE_AOWAKE_CNTRL_57) \
+_op_(WAKE_AOWAKE_CNTRL_58) \
+_op_(WAKE_AOWAKE_CNTRL_59) \
+_op_(WAKE_AOWAKE_CNTRL_60) \
+_op_(WAKE_AOWAKE_CNTRL_61) \
+_op_(WAKE_AOWAKE_CNTRL_62) \
+_op_(WAKE_AOWAKE_CNTRL_63) \
+_op_(WAKE_AOWAKE_CNTRL_64) \
+_op_(WAKE_AOWAKE_CNTRL_65) \
+_op_(WAKE_AOWAKE_CNTRL_66) \
+_op_(WAKE_AOWAKE_CNTRL_67) \
+_op_(WAKE_AOWAKE_CNTRL_68) \
+_op_(WAKE_AOWAKE_CNTRL_69) \
+_op_(WAKE_AOWAKE_CNTRL_70) \
+_op_(WAKE_AOWAKE_CNTRL_71) \
+_op_(WAKE_AOWAKE_CNTRL_72) \
+_op_(WAKE_AOWAKE_CNTRL_73) \
+_op_(WAKE_AOWAKE_CNTRL_74) \
+_op_(WAKE_AOWAKE_CNTRL_75) \
+_op_(WAKE_AOWAKE_CNTRL_76) \
+_op_(WAKE_AOWAKE_CNTRL_77) \
+_op_(WAKE_AOWAKE_CNTRL_78) \
+_op_(WAKE_AOWAKE_CNTRL_79) \
+_op_(WAKE_AOWAKE_CNTRL_80) \
+_op_(WAKE_AOWAKE_CNTRL_81) \
+_op_(WAKE_AOWAKE_CNTRL_82) \
+_op_(WAKE_AOWAKE_CNTRL_83) \
+_op_(WAKE_AOWAKE_CNTRL_84) \
+_op_(WAKE_AOWAKE_CNTRL_85) \
+_op_(WAKE_AOWAKE_CNTRL_86) \
+_op_(WAKE_AOWAKE_CNTRL_87) \
+_op_(WAKE_AOWAKE_CNTRL_88) \
+_op_(WAKE_AOWAKE_CNTRL_89) \
+_op_(WAKE_AOWAKE_CNTRL_90) \
+_op_(WAKE_AOWAKE_CNTRL_91) \
+_op_(WAKE_AOWAKE_CNTRL_92) \
+_op_(WAKE_AOWAKE_CNTRL_93) \
+_op_(WAKE_AOWAKE_CNTRL_94) \
+_op_(WAKE_AOWAKE_CNTRL_95) \
+_op_(WAKE_AOWAKE_MASK_W_0) \
+_op_(WAKE_AOWAKE_MASK_W) \
+_op_(WAKE_AOWAKE_MASK_W_1) \
+_op_(WAKE_AOWAKE_MASK_W_2) \
+_op_(WAKE_AOWAKE_MASK_W_3) \
+_op_(WAKE_AOWAKE_MASK_W_4) \
+_op_(WAKE_AOWAKE_MASK_W_5) \
+_op_(WAKE_AOWAKE_MASK_W_6) \
+_op_(WAKE_AOWAKE_MASK_W_7) \
+_op_(WAKE_AOWAKE_MASK_W_8) \
+_op_(WAKE_AOWAKE_MASK_W_9) \
+_op_(WAKE_AOWAKE_MASK_W_10) \
+_op_(WAKE_AOWAKE_MASK_W_11) \
+_op_(WAKE_AOWAKE_MASK_W_12) \
+_op_(WAKE_AOWAKE_MASK_W_13) \
+_op_(WAKE_AOWAKE_MASK_W_14) \
+_op_(WAKE_AOWAKE_MASK_W_15) \
+_op_(WAKE_AOWAKE_MASK_W_16) \
+_op_(WAKE_AOWAKE_MASK_W_17) \
+_op_(WAKE_AOWAKE_MASK_W_18) \
+_op_(WAKE_AOWAKE_MASK_W_19) \
+_op_(WAKE_AOWAKE_MASK_W_20) \
+_op_(WAKE_AOWAKE_MASK_W_21) \
+_op_(WAKE_AOWAKE_MASK_W_22) \
+_op_(WAKE_AOWAKE_MASK_W_23) \
+_op_(WAKE_AOWAKE_MASK_W_24) \
+_op_(WAKE_AOWAKE_MASK_W_25) \
+_op_(WAKE_AOWAKE_MASK_W_26) \
+_op_(WAKE_AOWAKE_MASK_W_27) \
+_op_(WAKE_AOWAKE_MASK_W_28) \
+_op_(WAKE_AOWAKE_MASK_W_29) \
+_op_(WAKE_AOWAKE_MASK_W_30) \
+_op_(WAKE_AOWAKE_MASK_W_31) \
+_op_(WAKE_AOWAKE_MASK_W_32) \
+_op_(WAKE_AOWAKE_MASK_W_33) \
+_op_(WAKE_AOWAKE_MASK_W_34) \
+_op_(WAKE_AOWAKE_MASK_W_35) \
+_op_(WAKE_AOWAKE_MASK_W_36) \
+_op_(WAKE_AOWAKE_MASK_W_37) \
+_op_(WAKE_AOWAKE_MASK_W_38) \
+_op_(WAKE_AOWAKE_MASK_W_39) \
+_op_(WAKE_AOWAKE_MASK_W_40) \
+_op_(WAKE_AOWAKE_MASK_W_41) \
+_op_(WAKE_AOWAKE_MASK_W_42) \
+_op_(WAKE_AOWAKE_MASK_W_43) \
+_op_(WAKE_AOWAKE_MASK_W_44) \
+_op_(WAKE_AOWAKE_MASK_W_45) \
+_op_(WAKE_AOWAKE_MASK_W_46) \
+_op_(WAKE_AOWAKE_MASK_W_47) \
+_op_(WAKE_AOWAKE_MASK_W_48) \
+_op_(WAKE_AOWAKE_MASK_W_49) \
+_op_(WAKE_AOWAKE_MASK_W_50) \
+_op_(WAKE_AOWAKE_MASK_W_51) \
+_op_(WAKE_AOWAKE_MASK_W_52) \
+_op_(WAKE_AOWAKE_MASK_W_53) \
+_op_(WAKE_AOWAKE_MASK_W_54) \
+_op_(WAKE_AOWAKE_MASK_W_55) \
+_op_(WAKE_AOWAKE_MASK_W_56) \
+_op_(WAKE_AOWAKE_MASK_W_57) \
+_op_(WAKE_AOWAKE_MASK_W_58) \
+_op_(WAKE_AOWAKE_MASK_W_59) \
+_op_(WAKE_AOWAKE_MASK_W_60) \
+_op_(WAKE_AOWAKE_MASK_W_61) \
+_op_(WAKE_AOWAKE_MASK_W_62) \
+_op_(WAKE_AOWAKE_MASK_W_63) \
+_op_(WAKE_AOWAKE_MASK_W_64) \
+_op_(WAKE_AOWAKE_MASK_W_65) \
+_op_(WAKE_AOWAKE_MASK_W_66) \
+_op_(WAKE_AOWAKE_MASK_W_67) \
+_op_(WAKE_AOWAKE_MASK_W_68) \
+_op_(WAKE_AOWAKE_MASK_W_69) \
+_op_(WAKE_AOWAKE_MASK_W_70) \
+_op_(WAKE_AOWAKE_MASK_W_71) \
+_op_(WAKE_AOWAKE_MASK_W_72) \
+_op_(WAKE_AOWAKE_MASK_W_73) \
+_op_(WAKE_AOWAKE_MASK_W_74) \
+_op_(WAKE_AOWAKE_MASK_W_75) \
+_op_(WAKE_AOWAKE_MASK_W_76) \
+_op_(WAKE_AOWAKE_MASK_W_77) \
+_op_(WAKE_AOWAKE_MASK_W_78) \
+_op_(WAKE_AOWAKE_MASK_W_79) \
+_op_(WAKE_AOWAKE_MASK_W_80) \
+_op_(WAKE_AOWAKE_MASK_W_81) \
+_op_(WAKE_AOWAKE_MASK_W_82) \
+_op_(WAKE_AOWAKE_MASK_W_83) \
+_op_(WAKE_AOWAKE_MASK_W_84) \
+_op_(WAKE_AOWAKE_MASK_W_85) \
+_op_(WAKE_AOWAKE_MASK_W_86) \
+_op_(WAKE_AOWAKE_MASK_W_87) \
+_op_(WAKE_AOWAKE_MASK_W_88) \
+_op_(WAKE_AOWAKE_MASK_W_89) \
+_op_(WAKE_AOWAKE_MASK_W_90) \
+_op_(WAKE_AOWAKE_MASK_W_91) \
+_op_(WAKE_AOWAKE_MASK_W_92) \
+_op_(WAKE_AOWAKE_MASK_W_93) \
+_op_(WAKE_AOWAKE_MASK_W_94) \
+_op_(WAKE_AOWAKE_MASK_W_95) \
+_op_(WAKE_AOWAKE_MASK_R_31_0_0) \
+_op_(WAKE_AOWAKE_MASK_R_63_32_0) \
+_op_(WAKE_AOWAKE_MASK_R_95_64_0) \
+_op_(WAKE_AOWAKE_STATUS_W_0) \
+_op_(WAKE_AOWAKE_STATUS_W) \
+_op_(WAKE_AOWAKE_STATUS_W_1) \
+_op_(WAKE_AOWAKE_STATUS_W_2) \
+_op_(WAKE_AOWAKE_STATUS_W_3) \
+_op_(WAKE_AOWAKE_STATUS_W_4) \
+_op_(WAKE_AOWAKE_STATUS_W_5) \
+_op_(WAKE_AOWAKE_STATUS_W_6) \
+_op_(WAKE_AOWAKE_STATUS_W_7) \
+_op_(WAKE_AOWAKE_STATUS_W_8) \
+_op_(WAKE_AOWAKE_STATUS_W_9) \
+_op_(WAKE_AOWAKE_STATUS_W_10) \
+_op_(WAKE_AOWAKE_STATUS_W_11) \
+_op_(WAKE_AOWAKE_STATUS_W_12) \
+_op_(WAKE_AOWAKE_STATUS_W_13) \
+_op_(WAKE_AOWAKE_STATUS_W_14) \
+_op_(WAKE_AOWAKE_STATUS_W_15) \
+_op_(WAKE_AOWAKE_STATUS_W_16) \
+_op_(WAKE_AOWAKE_STATUS_W_17) \
+_op_(WAKE_AOWAKE_STATUS_W_18) \
+_op_(WAKE_AOWAKE_STATUS_W_19) \
+_op_(WAKE_AOWAKE_STATUS_W_20) \
+_op_(WAKE_AOWAKE_STATUS_W_21) \
+_op_(WAKE_AOWAKE_STATUS_W_22) \
+_op_(WAKE_AOWAKE_STATUS_W_23) \
+_op_(WAKE_AOWAKE_STATUS_W_24) \
+_op_(WAKE_AOWAKE_STATUS_W_25) \
+_op_(WAKE_AOWAKE_STATUS_W_26) \
+_op_(WAKE_AOWAKE_STATUS_W_27) \
+_op_(WAKE_AOWAKE_STATUS_W_28) \
+_op_(WAKE_AOWAKE_STATUS_W_29) \
+_op_(WAKE_AOWAKE_STATUS_W_30) \
+_op_(WAKE_AOWAKE_STATUS_W_31) \
+_op_(WAKE_AOWAKE_STATUS_W_32) \
+_op_(WAKE_AOWAKE_STATUS_W_33) \
+_op_(WAKE_AOWAKE_STATUS_W_34) \
+_op_(WAKE_AOWAKE_STATUS_W_35) \
+_op_(WAKE_AOWAKE_STATUS_W_36) \
+_op_(WAKE_AOWAKE_STATUS_W_37) \
+_op_(WAKE_AOWAKE_STATUS_W_38) \
+_op_(WAKE_AOWAKE_STATUS_W_39) \
+_op_(WAKE_AOWAKE_STATUS_W_40) \
+_op_(WAKE_AOWAKE_STATUS_W_41) \
+_op_(WAKE_AOWAKE_STATUS_W_42) \
+_op_(WAKE_AOWAKE_STATUS_W_43) \
+_op_(WAKE_AOWAKE_STATUS_W_44) \
+_op_(WAKE_AOWAKE_STATUS_W_45) \
+_op_(WAKE_AOWAKE_STATUS_W_46) \
+_op_(WAKE_AOWAKE_STATUS_W_47) \
+_op_(WAKE_AOWAKE_STATUS_W_48) \
+_op_(WAKE_AOWAKE_STATUS_W_49) \
+_op_(WAKE_AOWAKE_STATUS_W_50) \
+_op_(WAKE_AOWAKE_STATUS_W_51) \
+_op_(WAKE_AOWAKE_STATUS_W_52) \
+_op_(WAKE_AOWAKE_STATUS_W_53) \
+_op_(WAKE_AOWAKE_STATUS_W_54) \
+_op_(WAKE_AOWAKE_STATUS_W_55) \
+_op_(WAKE_AOWAKE_STATUS_W_56) \
+_op_(WAKE_AOWAKE_STATUS_W_57) \
+_op_(WAKE_AOWAKE_STATUS_W_58) \
+_op_(WAKE_AOWAKE_STATUS_W_59) \
+_op_(WAKE_AOWAKE_STATUS_W_60) \
+_op_(WAKE_AOWAKE_STATUS_W_61) \
+_op_(WAKE_AOWAKE_STATUS_W_62) \
+_op_(WAKE_AOWAKE_STATUS_W_63) \
+_op_(WAKE_AOWAKE_STATUS_W_64) \
+_op_(WAKE_AOWAKE_STATUS_W_65) \
+_op_(WAKE_AOWAKE_STATUS_W_66) \
+_op_(WAKE_AOWAKE_STATUS_W_67) \
+_op_(WAKE_AOWAKE_STATUS_W_68) \
+_op_(WAKE_AOWAKE_STATUS_W_69) \
+_op_(WAKE_AOWAKE_STATUS_W_70) \
+_op_(WAKE_AOWAKE_STATUS_W_71) \
+_op_(WAKE_AOWAKE_STATUS_W_72) \
+_op_(WAKE_AOWAKE_STATUS_W_73) \
+_op_(WAKE_AOWAKE_STATUS_W_74) \
+_op_(WAKE_AOWAKE_STATUS_W_75) \
+_op_(WAKE_AOWAKE_STATUS_W_76) \
+_op_(WAKE_AOWAKE_STATUS_W_77) \
+_op_(WAKE_AOWAKE_STATUS_W_78) \
+_op_(WAKE_AOWAKE_STATUS_W_79) \
+_op_(WAKE_AOWAKE_STATUS_W_80) \
+_op_(WAKE_AOWAKE_STATUS_W_81) \
+_op_(WAKE_AOWAKE_STATUS_W_82) \
+_op_(WAKE_AOWAKE_STATUS_W_83) \
+_op_(WAKE_AOWAKE_STATUS_W_84) \
+_op_(WAKE_AOWAKE_STATUS_W_85) \
+_op_(WAKE_AOWAKE_STATUS_W_86) \
+_op_(WAKE_AOWAKE_STATUS_W_87) \
+_op_(WAKE_AOWAKE_STATUS_W_88) \
+_op_(WAKE_AOWAKE_STATUS_W_89) \
+_op_(WAKE_AOWAKE_STATUS_W_90) \
+_op_(WAKE_AOWAKE_STATUS_W_91) \
+_op_(WAKE_AOWAKE_STATUS_W_92) \
+_op_(WAKE_AOWAKE_STATUS_W_93) \
+_op_(WAKE_AOWAKE_STATUS_W_94) \
+_op_(WAKE_AOWAKE_STATUS_W_95) \
+_op_(WAKE_AOWAKE_STATUS_R_31_0_0) \
+_op_(WAKE_AOWAKE_STATUS_R_63_32_0) \
+_op_(WAKE_AOWAKE_STATUS_R_95_64_0) \
+_op_(WAKE_AOWAKE_LATCH_SW_0) \
+_op_(WAKE_AOWAKE_SW_STATUS_W_0) \
+_op_(WAKE_AOWAKE_SW_STATUS_31_0_0) \
+_op_(WAKE_AOWAKE_SW_STATUS_63_32_0) \
+_op_(WAKE_AOWAKE_SW_STATUS_95_64_0) \
+_op_(WAKE_AOWAKE_TIER1_CTRL_0) \
+_op_(WAKE_AOWAKE_TIER2_CTRL_0) \
+_op_(WAKE_AOWAKE_TIER0_ROUTING_31_0_0) \
+_op_(WAKE_AOWAKE_TIER0_ROUTING_63_32_0) \
+_op_(WAKE_AOWAKE_TIER0_ROUTING_95_64_0) \
+_op_(WAKE_AOWAKE_TIER1_ROUTING_31_0_0) \
+_op_(WAKE_AOWAKE_TIER1_ROUTING_63_32_0) \
+_op_(WAKE_AOWAKE_TIER1_ROUTING_95_64_0) \
+_op_(WAKE_AOWAKE_TIER2_ROUTING_31_0_0) \
+_op_(WAKE_AOWAKE_TIER2_ROUTING_63_32_0) \
+_op_(WAKE_AOWAKE_TIER2_ROUTING_95_64_0) \
+_op_(WAKE_AOWAKE_SW_WAKE_TIER0_TRIGGER_0) \
+_op_(WAKE_AOWAKE_COAL_GRP0_0) \
+_op_(WAKE_AOWAKE_COAL_GRP1_0) \
+_op_(WAKE_AOWAKE_TSC_CTRL_0) \
+_op_(WAKE_AOWAKE_TSC_SNAP_VALUE_0) \
+_op_(WAKE_AOWAKE_DELAY_CELL_CTRL_0) \
+_op_(WAKE_AOWAKE_DET_EN_0) \
+_op_(WAKE_AOWAKE_CTRL_0) \
+_op_(WAKE_AOWAKE_CYA_0) \
+_op_(WAKE_AOWAKE_CYA) \
+_op_(WAKE_AOWAKE_CYA_1) \
+_op_(WAKE_AOWAKE_DBG_0) \
+_op_(WAKE_AOWAKE_DBG) \
+_op_(WAKE_AOWAKE_DBG_1) \
+_op_(WAKE_AOWAKE_SPE_AUTO_MASK_W_0) \
+_op_(WAKE_AOWAKE_SPE_AUTO_MASK_R_0) \
+_op_(WAKE_AOWAKE_HSP_MASK_W_0) \
+_op_(WAKE_AOWAKE_HSP_MASK_R_0)
+
+
+//
+// ADDRESS SPACES
+//
+
+#define BASE_ADDRESS_WAKE       0x00000000
+
+//
+// ARWAKE REGISTER BANKS
+//
+
+#define WAKE0_FIRST_REG 0x0000 // WAKE_AOWAKE_CNTRL_0
+#define WAKE0_LAST_REG 0x0514 // WAKE_AOWAKE_HSP_MASK_R_0
+
+// To satisfy various compilers and platforms,
+// we let users control the types and syntax of certain constants, using macros.
+#ifndef MK_SHIFT_CONST
+  #define MK_SHIFT_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST
+  #define MK_MASK_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ENUM_CONST
+  #define MK_ENUM_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_ADDR_CONST
+  #define MK_ADDR_CONST(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST
+  #define MK_FIELD_CONST(_mask_, _shift_) (MK_MASK_CONST(_mask_) <<  _shift_)
+#endif
+#ifndef MK_SHIFT_CONST_64
+  #define MK_SHIFT_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_MASK_CONST_64
+  #define MK_MASK_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ENUM_CONST_64
+  #define MK_ENUM_CONST_64(_constant_) (_constant_ ## UL)
+#endif
+#ifndef MK_ADDR_CONST_64
+  #define MK_ADDR_CONST_64(_constant_) (_constant_ ## U)
+#endif
+#ifndef MK_FIELD_CONST_64
+  #define MK_FIELD_CONST_64(_mask_, _shift_) (MK_MASK_CONST_64(_mask_) <<  _shift_)
+#endif
+
+#endif // ifndef ARWAKE_H_INC
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/gpio-aon.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/gpio-aon.h
new file mode 100644
index 0000000..1eed4ac
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/gpio-aon.h
@@ -0,0 +1,47 @@
+/* Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _GPIO_AON_T23X_H
+#define _GPIO_AON_T23X_H
+
+#include <processor/tegra-gpio-hw.h>
+
+#define TEGRA_AON_GPIO_CHIP_ID 0
+#define TEGRA_AON_GPIO_ID(bank, gpio) \
+		gpio_global_id(TEGRA_AON_GPIO_CHIP_ID, TEGRA_GPIO(bank, gpio))
+
+#ifdef ENABLE_SPE_FOR_ORIN_NANO
+#define GPIO_APP_OUT TEGRA_AON_GPIO_ID(DD, 1) /* GPIO_DD 1, pin 5, J12 */
+#define GPIO_APP_IN  TEGRA_AON_GPIO_ID(DD, 2) /* GPIO_DD 2, pin 3, J12 */
+
+#else /* SPE for AGX Orin */
+
+#define GPIO_APP_OUT TEGRA_AON_GPIO_ID(BB, 1) /* GPIO_BB 1, pin 16, J30 */
+#define GPIO_APP_IN  TEGRA_AON_GPIO_ID(BB, 0) /* GPIO_BB 0, pin 32, J30 */
+#endif /* ENABLE_SPE_FOR_ORIN_NANO */
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/gte-app.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/gte-app.h
new file mode 100644
index 0000000..1b92364
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/gte-app.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __GTE_APP_H
+#define __GTE_APP_H
+
+#ifdef ENABLE_SPE_FOR_ORIN_NANO
+#define GTE_SLICE_IRQ_GPIO NV_AON_GTE_SLICE2_IRQ_GPIO_12
+
+#else /*SPE for AGX Orin */
+
+#define GTE_SLICE_IRQ_GPIO NV_AON_GTE_SLICE2_IRQ_GPIO_3
+#endif /* ENABLE_SPE_FOR_ORIN_NANO */
+
+void gte_app_init(void);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/gte-tegra-hw.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/gte-tegra-hw.h
new file mode 100644
index 0000000..28e1989
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/gte-tegra-hw.h
@@ -0,0 +1,124 @@
+/*
+ * Copyright (c) 2016-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _GTE_TEGRA_HW_H_
+#define _GTE_TEGRA_HW_H_
+
+extern struct tegra_gte_id tegra_gte_id_aon;
+
+//GTE Interrupt connections. For slice 0
+#define NV_AON_GTE_SLICE0_IRQ_GPIO_44 0
+#define NV_AON_GTE_SLICE0_IRQ_GPIO_45 1
+#define NV_AON_GTE_SLICE0_IRQ_TIMER0  2
+#define NV_AON_GTE_SLICE0_IRQ_TIMER1  3
+#define NV_AON_GTE_SLICE0_IRQ_TIMER2  4
+#define NV_AON_GTE_SLICE0_IRQ_TIMER3  5
+#define NV_AON_GTE_SLICE0_IRQ_MBOX    6
+#define NV_AON_GTE_SLICE0_IRQ_GPIO_46 7
+#define NV_AON_GTE_SLICE0_IRQ_PMU     8
+#define NV_AON_GTE_SLICE0_IRQ_DMA0    9
+#define NV_AON_GTE_SLICE0_IRQ_DMA1    10
+#define NV_AON_GTE_SLICE0_IRQ_DMA2    11
+#define NV_AON_GTE_SLICE0_IRQ_DMA3    12
+#define NV_AON_GTE_SLICE0_IRQ_DMA4    13
+#define NV_AON_GTE_SLICE0_IRQ_DMA5    14
+#define NV_AON_GTE_SLICE0_IRQ_DMA6    15
+#define NV_AON_GTE_SLICE0_IRQ_DMA7    16
+#define NV_AON_GTE_SLICE0_IRQ_I2C1    17
+#define NV_AON_GTE_SLICE0_IRQ_I2C2    18
+#define NV_AON_GTE_SLICE0_IRQ_I2C3    19
+#define NV_AON_GTE_SLICE0_IRQ_SPI     20
+#define NV_AON_GTE_SLICE0_IRQ_ACTMON  21
+#define NV_AON_GTE_SLICE0_IRQ_UART_1  22
+#define NV_AON_GTE_SLICE0_IRQ_UART_2  23
+#define NV_AON_GTE_SLICE0_IRQ_CAN1_0  24
+#define NV_AON_GTE_SLICE0_IRQ_CAN1_1  25
+#define NV_AON_GTE_SLICE0_IRQ_CAN2_0  26
+#define NV_AON_GTE_SLICE0_IRQ_CAN2_1  27
+
+//GTE Interrupt connections. For slice 1
+#define NV_AON_GTE_SLICE1_IRQ_LIC0   0
+#define NV_AON_GTE_SLICE1_IRQ_LIC1   1
+#define NV_AON_GTE_SLICE1_IRQ_LIC2   2
+#define NV_AON_GTE_SLICE1_IRQ_LIC3   3
+#define NV_AON_GTE_SLICE1_IRQ_NOC_ERR 4
+#define NV_AON_GTE_SLICE1_IRQ_GPIO   5
+#define NV_AON_GTE_SLICE1_IRQ_WAKE0  6
+#define NV_AON_GTE_SLICE1_IRQ_PMC    7
+#define NV_AON_GTE_SLICE1_IRQ_DMIC   8
+#define NV_AON_GTE_SLICE1_IRQ_PM     9
+#define NV_AON_GTE_SLICE1_IRQ_FPUINT 10
+#define NV_AON_GTE_SLICE1_IRQ_AOVC   11
+#define NV_AON_GTE_SLICE1_IRQ_GPIO_28 12
+#define NV_AON_GTE_SLICE1_IRQ_GPIO_29 13
+#define NV_AON_GTE_SLICE1_IRQ_GPIO_30 14
+#define NV_AON_GTE_SLICE1_IRQ_GPIO_31 15
+#define NV_AON_GTE_SLICE1_IRQ_GPIO_32 16
+#define NV_AON_GTE_SLICE1_IRQ_GPIO_33 17
+#define NV_AON_GTE_SLICE1_IRQ_GPIO_34 18
+#define NV_AON_GTE_SLICE1_IRQ_GPIO_35 19
+#define NV_AON_GTE_SLICE1_IRQ_GPIO_36 20
+#define NV_AON_GTE_SLICE1_IRQ_GPIO_37 21
+#define NV_AON_GTE_SLICE1_IRQ_GPIO_38 22
+#define NV_AON_GTE_SLICE1_IRQ_GPIO_39 23
+#define NV_AON_GTE_SLICE1_IRQ_GPIO_40 24
+#define NV_AON_GTE_SLICE1_IRQ_GPIO_41 25
+#define NV_AON_GTE_SLICE1_IRQ_GPIO_42 26
+#define NV_AON_GTE_SLICE1_IRQ_GPIO_43 27
+
+//GTE Interrupt connections. For slice 2
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_0 0
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_1 1
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_2 2
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_3 3
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_4 4
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_5 5
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_6 6
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_7 7
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_8 8
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_9 9
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_10 10
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_11 11
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_12 12
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_13 13
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_14 14
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_15 15
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_16 16
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_17 17
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_18 18
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_19 19
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_20 20
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_21 21
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_22 22
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_23 23
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_24 24
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_25 25
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_26 26
+#define NV_AON_GTE_SLICE2_IRQ_GPIO_27 27
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/ivc-config.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/ivc-config.h
new file mode 100644
index 0000000..df56d2b
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/ivc-config.h
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _IVC_CONFIG_
+#define _IVC_CONFIG_
+
+#define AST_IVC_REGION		1UL
+#define AST_MIN_CARVEOUT_SIZE	(1 << 12)
+
+#define AON_STREAMID	0x1UL
+
+/* Shared Semaphore Index for the IVC Carveout base and size */
+#define IVC_CARVEOUT_BASE_SS_INDEX	0
+#define IVC_CARVEOUT_SIZE_SS_INDEX	1
+
+#define CCPLEX_CARVEOUT_BASE	0x80000000
+
+#define TEGRA_IVC_ALIGN	64
+
+#define IVC_NUM_CCPLEX_CHS	1
+
+#define SMBOX_IVC_CHAN_SHIFT	16
+#define SMBOX_IVC_NOTIFY_MASK	0xFFFF
+
+#define IVC_CH_HDRS_SIZE	(TEGRA_IVC_ALIGN * 2)
+
+#define IVC_CH_SIZE(nframes, frame_size) \
+	(IVC_CH_HDRS_SIZE + (nframes * frame_size))
+
+#define SMBOX_IVC_READY_MSG	0x2AAA5555
+#define	SMBOX_IVC_NOTIFY	0x0000AABB
+
+#define IVC_ECHO_TX_OFFSET	0x100
+#define IVC_ECHO_RX_OFFSET	0x10100
+#define IVC_ECHO_CH_ID		1
+#define IVC_ECHO_WRITE_HEADER	(CCPLEX_CARVEOUT_BASE + IVC_ECHO_TX_OFFSET)
+#define IVC_ECHO_READ_HEADER	(CCPLEX_CARVEOUT_BASE + IVC_ECHO_RX_OFFSET)
+#define IVC_ECHO_CH_NFRAMES	16
+#define IVC_ECHO_CH_FRAME_SIZE	(TEGRA_IVC_ALIGN * 1)
+#define IVC_ECHO_CH_SIZE	IVC_CH_SIZE(IVC_ECHO_CH_NFRAMES, \
+					IVC_ECHO_CH_FRAME_SIZE)
+#define IVC_ECHO_CH_AFTER	IVC_ECHO_CH_SIZE
+
+#define IVC_NOTIFY_TX_SS        2
+
+#define AON_CCPLEX_IVC_HSP_ID     &tegra_hsp_id_top1
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/mbox-aon.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/mbox-aon.h
new file mode 100644
index 0000000..88e40a4
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/mbox-aon.h
@@ -0,0 +1,64 @@
+/* Copyright (c) 2015-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _MBOX_AON_H
+#define _MBOX_AON_H
+
+/* BPMP Mailbox */
+#define MBOX_BPMP_BPMP			0
+#define MBOX_BPMP_UART			1
+#define MBOX_AON_BPMP			0
+#define MBOX_AON_BPMP_UART		6
+
+/* CCPLEX Mailbox */
+#define MBOX_AON_CCPLEX_UART	1
+#define MBOX_AON_CCPLEX_IVC_TX	4
+#define MBOX_AON_CCPLEX_IVC_RX	5
+
+/* PSC Mailbox */
+#define MBOX_AON_PSC_UART		2
+
+/* DCE Mailbox */
+#define MBOX_AON_DCE_UART		3
+
+/* SCE Mailbox */
+#define MBOX_AON_SCE_UART		4
+#define MBOX_SCE_UART			4
+
+/* RCE Mailbox */
+#define MBOX_AON_RCE_UART		5
+
+/* TZ Mailbox */
+#define MBOX_AON_TZ_UART		7
+
+/* FSI Mailbox */
+#define MBOX_TX_FSI_UART		7
+#define MBOX_FSI_UART			7
+
+#define MBOX_TAG_BIT			(1 << 31)
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/spe-clk.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/spe-clk.h
new file mode 100644
index 0000000..ed3b8eb
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/spe-clk.h
@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SPE_CLK_H_
+#define _SPE_CLK_H_
+
+#include <stdint.h>
+
+#define AON_CPU_MAX_RATE 408000
+#define AON_APB_MAX_RATE 200000
+
+#define CAR_REG(x)              (NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_##x##_0)
+#define CLKEN_REG(reg)          CAR_REG(CLK_OUT_ENB_##reg)
+#define CAR_FIELD(reg, field)   CLK_RST_CONTROLLER_##reg##_0_##field##_FIELD
+#define CAR_SHIFT(reg, field)   CLK_RST_CONTROLLER_##reg##_0_##field##_SHIFT
+
+#define CAR_DRF_NUM(r, f, n)    NV_DRF_NUM(CLK_RST_CONTROLLER, r, f, n)
+#define CAR_DRF_DEF(r, f, c)    NV_DRF_DEF(CLK_RST_CONTROLLER, r, f, c)
+#define CAR_DRF_VAL(r, f, v)    NV_DRF_VAL(CLK_RST_CONTROLLER, r, f, v)
+#define CAR_DRF_MASK(r, f)      NV_DRF_MASK(CLK_RST_CONTROLLER, r, f)
+
+#define CAR_FLD_SET_DRF_DEF(r, f, c, v)     NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, r, f, c, v)
+#define CAR_FLD_SET_DRF_NUM(r, f, n, v)     NV_FLD_SET_DRF_NUM(CLK_RST_CONTROLLER, r, f, n, v)
+
+#define CLK_SRC(clk)            CAR_REG(CLK_SOURCE_##clk)
+#define CLK_SRC_IDX(reg, src)   CLK_RST_CONTROLLER_CLK_SOURCE_##reg##_0_##reg##_CLK_SRC_##src
+
+#define CLK_SRC_PLLAON 0
+#define CLK_SRC_PLLP 1
+#define CLK_SRC_OSC_UNDIV 2
+#define CLK_SRC_CLK_S 3
+#define CLK_SRC_MAX 4
+
+#define CLK_ID_AON_CPU_NIC_ACTIVE           0
+#define CLK_ID_AON_CPU_NIC_ACTIVE_IRQFIQ    1
+#define CLK_ID_AON_CPU_NIC_IDLE_SHALLOW     2
+#define CLK_ID_AON_CPU_NIC_IDLE_DEEP        3
+#define CLK_ID_AON_CPU_NIC_STBY_SHALLOW     4
+#define CLK_ID_AON_CPU_NIC_STBY_DEEP        5
+#define CLK_ID_AON_CPU_NIC_DORMANT_SHALLOW  6
+#define CLK_ID_AON_CPU_NIC_DORMANT_DEEP     7
+#define CLK_ID_AON_APB_ACTIVE               8
+#define CLK_ID_AON_APB_ACTIVE_IRQFIQ        9
+#define CLK_ID_AON_APB_IDLE_SHALLOW         10
+#define CLK_ID_AON_APB_IDLE_DEEP            11
+#define CLK_ID_AON_APB_STBY_SHALLOW         12
+#define CLK_ID_AON_APB_STBY_DEEP            13
+#define CLK_ID_AON_APB_DORMANT_SHALLOW      14
+#define CLK_ID_AON_APB_DORMANT_DEEP         15
+#define CLK_ID_AON_CPU_NIC                  16
+#define CLK_ID_AON_APB                      17
+#define CLK_ID_MAX                          18
+
+void spe_clk_init(void);
+int spe_clk_set_clk_freq(int clk_id, int clk_src, uint32_t freq_khz);
+int spe_clk_set_clk_no_div(int clk_id, int clk_src);
+void spe_clk_trigger_switch_fsm(void);
+
+void spe_clk_setup_cpu_nic(uint32_t clk_src);
+void spe_clk_setup_apb(uint32_t clk_src);
+
+void disable_pllaon(void);
+void enable_pllaon(void);
+
+void set_pllaon_state(bool enable);
+bool is_pllaon_enabled(void);
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/spe-map.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/spe-map.h
new file mode 100644
index 0000000..7711858
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/spe-map.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _SPE_MAP_H
+#define _SPE_MAP_H
+
+
+#define RUN_ADDR  0x0c480000
+#define LOAD_ADDR 0x70000000
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/tcu-priv.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/tcu-priv.h
new file mode 100644
index 0000000..024eaef
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/tcu-priv.h
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef TCU_PRIV_H
+#define TCU_PRIV_H
+
+#include <stdint.h>
+
+#define rtos_task_define_s(_t_, _fn_, _name_, _prio_, _params_,_stack_depth_) \
+    static const rtosTaskParameters _t_##_params = \
+    {                                              \
+        .pvTaskCode         = & _fn_,              \
+        .pcTaskName         = _name_,              \
+        .uxPriority         = _prio_,              \
+        .pvParameters       = _params_,            \
+        .uxStackDepthBytes  = _stack_depth_        \
+    }
+
+#define TCU_ID_CCPLEX           (0U)
+#define TCU_ID_SCE              (1U)
+#define TCU_ID_TZ               (2U)
+#define TCU_ID_BPMP             (3U)
+#define TCU_ID_RCE              (4U)
+#define TCU_ID_FSI              (5U)
+#define TCU_ID_PSC              (6U)
+#define TCU_ID_DCE              (7U)
+
+#define TCU_TAG_MIN             (0xe1U)
+#define TCU_TAG_CCPLEX          (0xe1U)
+#define TCU_TAG_BPMP            (0xe2U)
+#define TCU_TAG_SCE             (0xe3U)
+#define TCU_TAG_TZ              (0xe4U)
+#define TCU_TAG_RCE             (0xe5U)
+#define TCU_TAG_FSI             (0xe6U)
+#define TCU_TAG_PSC             (0xe7U)
+#define TCU_TAG_DCE             (0xe8U)
+#define TCU_TAG_MAX             (0xe8U)
+
+#define SPE_NUM_MSGS            (16UL)
+#define SPE_MSG_SIZE            (128UL)
+#define EXT_CLIENT_MSG_SIZE     (256UL)
+#define EXT_CLIENT_RX_BUF_SIZE  (256UL)
+
+#endif
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/wake-tegra-hw.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/wake-tegra-hw.h
new file mode 100644
index 0000000..a2238df
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/wake-tegra-hw.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef WAKE_TEGRA_HW_H
+#define WAKE_TEGRA_HW_H
+
+#include <address_map_new.h>
+
+/*
+ * wake event defined in
+ * //hw/nvmobile/ip/socip/pmc/5.0/defs/public/registers/
+ */
+#define TEGRA_WAKE_EVENT_RTC		73
+#define TEGRA_WAKE_EVENT_SW_TRIGGER	83
+
+enum tegra_wake_tier {
+	TEGRA_WAKE_TIER0,
+	TEGRA_WAKE_TIER1,
+	TEGRA_WAKE_TIER2,
+};
+
+/*
+ * We cheat and use the HW register address instead of the address of a config
+ * structure as the WAKE ID for now. We still need a dummy definition of the
+ * struct to do that though; this is it.
+ */
+struct tegra_wake_id {
+	uint32_t dummy;
+};
+
+/*
+ * We intend: &tegra_wake_id == NV_ADDRESS_MAP_WAKE_BASE. This avoids
+ * having to allocate a struct to hold the value NV_ADDRESS_MAP_WAKE_BASE.
+ * If we ever need to store more configuration than just the register address,
+ * this can be converted to a struct at that time.
+ */
+#define tegra_wake_id_wake (*(struct tegra_wake_id *)NV_ADDRESS_MAP_WAKE_BASE)
+
+#endif
\ No newline at end of file
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/wake-tegra.h b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/wake-tegra.h
new file mode 100644
index 0000000..49f9b5c
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/include/wake-tegra.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef WAKE_TEGRA_H
+#define WAKE_TEGRA_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+struct tegra_wake_id;
+
+/*
+ * To use this driver:
+ *
+ * 1. Call tegra_wake_route_event to route wake event into desired tier level
+ * 2. Call tegra_wake_enable_irq to enable the irq of the selected wake event
+ * 2. Call tegra_wake_enable to enable wake event detection
+ */
+
+/*
+ * Route wake event into selected tier
+ *
+ * Parameters:
+ * id:		    The ID structure for the WAKE module
+ * wake_event:	The wake event to be routed
+ * tier:	    The wake event will be routed into this tier
+ * sel:		    0: Remove wake event from desired tier level
+ *		        1: Select wake event into desired tier level
+ */
+void tegra_wake_route_event(struct tegra_wake_id *id, uint32_t wake_event,
+				  uint32_t tier, bool sel);
+
+/*
+ * Enable selected wake event
+ *
+ * Parameters:
+ * id:		    The ID structure for the WAKE module
+ * wake_event:	The wake event is going to be enabled
+ */
+void tegra_wake_enable_event(struct tegra_wake_id *id, uint32_t wake_event);
+
+/*
+ * Disable selected wake event
+ *
+ * Parameters:
+ * id:		    The ID structure for the WAKE module
+ * wake_event:	The wake event is going to be disabled
+ */
+void tegra_wake_disable_event(struct tegra_wake_id *id, uint32_t wake_event);
+
+/*
+ * Enable wake event detection
+ *
+ * Parameters:
+ * id:		The ID structure for the WAKE module
+ */
+void tegra_wake_enable(struct tegra_wake_id *id);
+
+/*
+ * Disable wake event detection
+ *
+ * Parameters:
+ * id:		The ID structure for the WAKE module
+ */
+void tegra_wake_disable(struct tegra_wake_id *id);
+
+/*
+ * Clear wake interrupt status
+ *
+ * Parameters:
+ * id:		    The ID structure for the WAKE module.
+ * wake_event:	The wake event status to be clear
+ */
+void tegra_wake_clear_irq(struct tegra_wake_id *id, uint32_t wake_event);
+
+/*
+ * Trigger a wake event
+ *
+ * Parameters:
+ * id:		The ID structure for the WAKE module.
+ */
+void tegra_wake_trigger_wake_event(struct tegra_wake_id *id);
+
+#endif
\ No newline at end of file
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/spe.ld.in b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/spe.ld.in
new file mode 100644
index 0000000..933e574
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/spe.ld.in
@@ -0,0 +1,100 @@
+/* Copyright (c) 2021-2024, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*
+ * Override macros defined in address_map_new.h to avoid syntax error for
+ * NV_ADDRESS_MAP_AON_BTCM_* defines
+ */
+#define MK_U32_CONST(_constant_) (_constant_)
+#define MK_ADDR_CONST(_constant_) (_constant_)
+#include "address_map_new.h"
+#include <spe-map.h>
+
+MEMORY
+{
+  btcm : ORIGIN = RUN_ADDR, LENGTH = NV_ADDRESS_MAP_AON_BTCM_SIZE
+}
+
+FIQ_SIZE = 0x300;
+IRQ_SIZE = 0x300;
+ABT_SIZE = 0x100;
+UND_SIZE = 0x100;
+SVC_SIZE = 0x300;
+
+_estack = RUN_ADDR + NV_ADDRESS_MAP_AON_BTCM_SIZE;
+_fiqstack = _estack;
+_irqstack = _fiqstack - FIQ_SIZE;
+_abtstack = _irqstack - IRQ_SIZE;
+_undstack = _abtstack - ABT_SIZE;
+_svcstack = _undstack - UND_SIZE;
+_sstack =  _svcstack - SVC_SIZE;
+
+_heap_end = _sstack;
+
+PHDRS
+{
+  /* FLAGS(5) = rx, FLAGS(6) = rw */
+  text PT_LOAD FLAGS(5);
+  data PT_LOAD FLAGS(6);
+  bss PT_LOAD FLAGS(6);
+}
+
+SECTIONS
+{
+    .text :
+    {
+        . = ALIGN(4);
+	_stext = .;
+	KEEP(*(.vectors .vectors.*))
+        . = ALIGN(4);
+        *(.text .text.*)
+        *(.rodata .rodata*)
+        . = ALIGN(4);
+        _etext = .;
+    } > btcm :text
+
+    .data :
+    {
+        _sdata = .;
+        *(.data .data.*);
+        . = ALIGN(4);
+        _edata = .;
+    } > btcm :data
+
+    .bss :
+    {
+        _sbss = . ;
+        *(.bss .bss.*)
+        *(COMMON)
+        . = ALIGN(4);
+        _ebss = . ;
+    } > btcm :bss
+    _end = . ;
+
+    . = ALIGN(4);
+    _heap_start = .;
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/boot.S b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/boot.S
new file mode 100644
index 0000000..01a0573
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/boot.S
@@ -0,0 +1,203 @@
+@ Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+@
+@ Redistribution and use in source and binary forms, with or without
+@ modification, are permitted provided that the following conditions
+@ are met:
+@  * Redistributions of source code must retain the above copyright
+@    notice, this list of conditions and the following disclaimer.
+@  * Redistributions in binary form must reproduce the above copyright
+@    notice, this list of conditions and the following disclaimer in the
+@    documentation and/or other materials provided with the distribution.
+@  * Neither the name of NVIDIA CORPORATION nor the names of its
+@    contributors may be used to endorse or promote products derived
+@    from this software without specific prior written permission.
+@
+@ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+@ EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+@ IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+@ PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+@ CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+@ EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+@ PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+@ PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+@ OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+@ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include <soc-common/hw-const.h>
+#include <address_map_new.h>
+#include <arclk_rst.h>
+#include <araoncluster_evp.h>
+#include <arclk_rst.h>
+#include <spe-map.h>
+
+.extern main
+.extern _Undefined_Instruction_Handler
+.extern _Data_Abort_Handler
+.extern _Prefetch_Abort_Handler
+.extern vPortYieldProcessor
+.extern cache_enable
+
+.extern _svcstack
+.extern _fiqstack
+.extern _irqstack
+.extern _abtstack
+.extern _undstack
+
+.section .vectors
+    B   _reset_handler                 @Reset
+    B   _Undefined_Instruction_Handler @Undefined_Handler
+    B   vPortYieldProcessor            @SVC_Handler
+    B   _Prefetch_Abort_Handler        @Prefetch_Handler
+    B   _Data_Abort_Handler            @Abort_Handler
+    B   _dummy_handler                 @Reserved
+    B   _irq_handler                   @IRQ_Handler
+    B   _irq_handler      	       @FIQ_Handler
+
+.section .text
+@ SCTLR.VE should be set to 1 and should not get here
+_irq_handler:
+    B  _irq_handler
+
+_dummy_handler:
+    B  _dummy_handler
+
+_reset_handler:
+@==================================================================
+@ Copy TCM overlay area to BTCM using DMA. This also zero initializes
+@ the TCM BSS sections and zero-fills the rest of the TCM with zero.
+@
+@ relocate_memcpy_dma(btcm_base, mem_base, tcm_size);
+@==================================================================
+    LDR     R0, =RUN_ADDR
+    LDR     R1, =LOAD_ADDR
+    LDR     R2, =NV_ADDRESS_MAP_AON_BTCM_SIZE
+    BL      relocate_memcpy_dma
+
+@==================================================================
+@ Execution continues here after DMA relocation is complete. This
+@ code transitions execution from the LOAD_ADDR space to the
+@ RUN_ADDR space.  R0 is loaded with address in the RUN_ADDR space.
+@ After setting PC=R0 execution continues at the run-address.
+@==================================================================
+    MOVW    R0, #:lower16:relocation_label
+    MOVT    R0, #:upper16:relocation_label
+    MOV     PC, R0
+
+@==================================================================
+@ Disable MPU and cache in case it was left enabled from an earlier run
+@ This does not need to be done from a cold reset
+@==================================================================
+relocation_label:
+    MRC     p15, 0, r0, c1, c0, 0       @ Read CP15 Control Register
+    BIC     r0, r0, #0x05               @ Disable MPU (M bit) and data cache (C bit)
+    BIC     r0, r0, #0x1000             @ Disable instruction cache (I bit)
+    DSB                                 @ Ensure all previous loads/stores have completed
+    MCR     p15, 0, r0, c1, c0, 0       @ Write CP15 Control Register
+    ISB                                 @ Ensure subsequent insts execute wrt new MPU settings
+
+@==================================================================
+@ Setup the various exception vectors
+@
+@ Only the reset vector is set up by the bootloader
+@==================================================================
+	LDR	R1, =NV_ADDRESS_MAP_AON_ATCM_CFG_EVP_BASE
+	LDR	R0, =_Undefined_Instruction_Handler
+	STR	R0, [R1, #AONCLUSTER_EVP_UNDEF_ADDR_0]
+	LDR	R0, =vPortYieldProcessor
+	STR	R0, [R1, #AONCLUSTER_EVP_SWI_ADDR_0]
+	LDR	R0, =_Prefetch_Abort_Handler
+	STR	R0, [R1, #AONCLUSTER_EVP_PREFETCH_ABORT_ADDR_0]
+	LDR	R0, =_Data_Abort_Handler
+	STR	R0, [R1, #AONCLUSTER_EVP_DATA_ABORT_ADDR_0]
+	LDR	R0, =_irq_handler
+	STR	R0, [R1, #AONCLUSTER_EVP_IRQ_ADDR_0]
+	LDR	R0, =_irq_handler
+	STR	R0, [R1, #AONCLUSTER_EVP_FIQ_ADDR_0]
+
+@==================================================================
+@ Init Stack pointer
+@==================================================================
+    MSR     cpsr_c, #0xD1       @FIQ
+    LDR     sp, =_fiqstack
+    MSR     cpsr_c, #0xD2       @IRQ
+    LDR     sp, =_irqstack
+    MSR     cpsr_c, #0xD7       @ABT
+    LDR     sp, =_abtstack
+    MSR     cpsr_c, #0xDB       @UND
+    LDR     sp, =_undstack
+    MSR     cpsr_c, #0xD3       @SVC
+    LDR     sp, =_svcstack
+
+@==================================================================
+@ Setup Frame Pointers. Zero out ARM and Thumb frame pointers.
+@==================================================================
+    MOV     a2, #0
+    MOV     fp, a2
+    MOV     r7, a2
+
+@==================================================================
+@ Enable Branch prediction
+@==================================================================
+
+    MRC     p15, 0, r0, c1, c0, 1       @ Read ACTLR
+    BIC     r0, r0, #(0x1 << 17)        @ Clear RSDIS bit 17 to enable return stack
+    BIC     r0, r0, #(0x1 << 16)        @ Clear BP bit 15 and BP bit 16:
+    BIC     r0, r0, #(0x1 << 15)        @ Normal operation, BP is taken from the global history table.
+    MCR     p15, 0, r0, c1, c0, 1       @ Write ACTLR
+
+@==================================================================
+@ Enable VFP
+@==================================================================
+
+    MRC     p15, 0, r0, c1, c0, 2
+    ORR     r0, r0, #(0xF << 20)
+    MCR     p15, 0, r0, c1, c0, 2
+    ISB
+    MOV     r0, #0x40000000
+    VMSR    FPEXC, r0
+
+@==================================================================
+@ Configure VIC to provide handler addr for IRQ
+@==================================================================
+    MRC     p15, 0, r0, c1, c0, 0       @ read CP15 register 1
+    ORR     r0, r0, #(0x1 << 24)        @ Configure VIC to provide handler addr for IRQ
+    MCR     p15, 0, r0, c1, c0, 0       @ write CP15 register 1
+
+@==================================================================
+@ Enable asynchronous aborts
+@==================================================================
+    CPSIE A
+
+@==================================================================
+@ Enable Caches
+@==================================================================
+    BL      cache_enable
+
+@==================================================================
+@ Clear BSS
+@==================================================================
+    LDR	    R1, _sbss_val
+    LDR	    R2, _ebss_val
+    SUBS    R2, R2, R1 /* END-START = LENGTH */
+    BEQ	    _clear_bss_end
+    MOV	    R0, #0
+_clear_bss_loop:
+    STR	    R0, [R1], #4
+    SUBS    R2, R2, #4
+    BGT	    _clear_bss_loop
+_clear_bss_end:
+
+@==================================================================
+@ Jump to Reset Handler
+@==================================================================
+    BLX     main
+
+_loop:
+   B	    _loop
+
+_sbss_val:
+	.word	_sbss
+_ebss_val:
+	.word	_ebss
+
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/clk.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/clk.c
new file mode 100644
index 0000000..5f77384
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/clk.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "clk.h"
+
+void clk_init_hw()
+{
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/i2c-app-priv.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/i2c-app-priv.c
new file mode 100644
index 0000000..760ce3f
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/i2c-app-priv.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2019-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <string.h>
+#include <misc/bitops.h>
+#include <i2c/i2c.h>
+#include <i2c/i2c-tegra.h>
+#include "config.h"
+#include "i2c-app-priv.h"
+
+#define I2C_TEST_CLIENT_DEV_ID	0xd1
+#define I2C_TEST_CLIENT_ID_REG	0x0
+#define I2C_TEST_CLIENT_ADDR	0x68
+
+#define I2C_XFER_TIMEOUT	500000
+
+void i2c_test(struct i2c_handle *hi2c)
+{
+	error_t ret;
+	uint8_t id_reg = I2C_TEST_CLIENT_ID_REG;
+	uint8_t data = 0;
+
+	struct i2c_xfer_msg xfers[] = {
+		{
+			.dev_addr = I2C_TEST_CLIENT_ADDR,
+			.xfer_flags = 0,
+			.pwbuf = &id_reg,
+			.buf_len = sizeof(id_reg),
+		},
+		{
+			.dev_addr = I2C_TEST_CLIENT_ADDR,
+			.xfer_flags = I2C_XFER_FLAG_RD,
+			.prbuf = &data,
+			.buf_len = sizeof(data),
+		},
+	};
+	ret = i2c_do_transfer(hi2c, xfers, ARRAY_SIZE(xfers), I2C_XFER_TIMEOUT);
+
+	if (ret == E_SUCCESS) {
+		if (data == I2C_TEST_CLIENT_DEV_ID){
+			printf("I2C test successful\r\n");
+			return;
+		}
+	}
+	printf("I2C failed reading id reg\r\n");
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/init_padctrl.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/init_padctrl.c
new file mode 100644
index 0000000..716c45b
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/init_padctrl.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "init_padctrl.h"
+
+void init_padctrl(void)
+{
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/interrupt.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/interrupt.c
new file mode 100644
index 0000000..974ce02
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/interrupt.c
@@ -0,0 +1,136 @@
+/* Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <osa/rtos-task.h>
+#include <err-hook.h>
+#include <irq/safe-irqs.h>
+#include <vic/vic-errors.h>
+#include <spe-lic.h>
+
+#include <irq/safe-irqs.h>
+#include <cpu/arm-vic.h>
+#include <hw-config/vic-irqs.h>
+#include <processor/irqs-lic.h>
+#include <vic/tegra-vic.h>
+#include <vic/vic-errors.h>
+#include <spe-lic.h>
+
+#define IRQS_PER_VIC    32U
+#define MAX_VIC_IRQS    (MAX_VIC_CONTROLLER * 32U)
+#define MAX_IRQS        AON_LIC_IRQ_MAX
+
+struct irq_handler {
+	void (*handler)(void*);
+	void *data;
+};
+
+static struct irq_handler irq_handlers[MAX_IRQS];
+
+void irq_handler(uint32_t irq)
+{
+	struct irq_handler *h;
+
+	if (irq >= MAX_IRQS) {
+		error_hook("Recieved invalid interrupt!");
+		return;
+	}
+
+	h = &irq_handlers[irq];
+	if (h->handler) {
+		h->handler(h->data);
+	} else {
+		warning_hook("Spurious interrupt!");
+	}
+}
+
+error_t irq_safe_set_handler(uint32_t irq, irq_callback_fn routine, void *data)
+{
+	struct irq_handler *h;
+	error_t err = E_SUCCESS;
+
+	if (irq >= MAX_IRQS) {
+		error_hook("Trying to set invalid interrupt!");
+		err = E_VIC_INVALID_VECTOR;
+		goto out;
+	}
+
+	h = &irq_handlers[irq];
+	rtosTaskEnterCritical();
+	h->handler = routine;
+	h->data = data;
+	rtosTaskExitCritical();
+out:
+	return err;
+}
+
+error_t irq_safe_enable(const uint32_t vector)
+{
+    uint32_t vic;
+    uint32_t irq;
+    error_t ret = E_SUCCESS;
+
+    if (vector < MAX_VIC_IRQS) {
+        vic = TEGRA_INTERRUPT_TO_VIC(vector);
+        irq = TEGRA_INTERRUPT_TO_IRQ(vector);
+        arm_vic_enable(vic_base_addr[vic], irq);
+    } else {
+        if (vector < MAX_IRQS) {
+            spe_lic_enable(vector);
+            goto out;
+        }
+        error_hookf("invalid irq(%lu) for irq_safe_enable()\r\n", vector);
+        ret = E_VIC_INVALID_VECTOR;
+    }
+
+out:
+    return ret;
+}
+
+error_t irq_safe_disable(const uint32_t vector)
+{
+    uint32_t vic;
+    uint32_t irq;
+    error_t ret = E_SUCCESS;
+
+    if (vector < MAX_VIC_IRQS) {
+        vic = TEGRA_INTERRUPT_TO_VIC(vector);
+        irq = TEGRA_INTERRUPT_TO_IRQ(vector);
+        arm_vic_disable(vic_base_addr[vic], irq);
+    } else {
+        if (vector < MAX_IRQS) {
+            spe_lic_disable(vector);
+            goto out;
+        }
+        error_hookf("invalid irq(%lu) for irq_safe_disable()\r\n", vector);
+        ret = E_VIC_INVALID_VECTOR;
+    }
+
+out:
+    return ret;
+}
+
+
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/late-init.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/late-init.c
new file mode 100644
index 0000000..5ea5315
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/late-init.c
@@ -0,0 +1,91 @@
+/*
+ * Copyright (c) 2021-2023, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <address_map_new.h>
+#include <stdbool.h>
+#include <late-init.h>
+#include <spe-clk.h>
+#include <spe-pm.h>
+#include <processor/hsp-tegra-hw.h>
+#include <hsp/hsp-tegra.h>
+#include <reg-access/reg-access.h>
+#include <address_map_new.h>
+#include <araopm.h>
+#include <misc/nvrm_drf.h>
+#include <chipid/chip-id.h>
+#include "config.h"
+#include "main.h"
+#include <osa/rtos-task.h>
+#include <err-hook.h>
+
+#define AOPM_AON_BLOCK_REG (NV_ADDRESS_MAP_AON_PM_IMPL_BASE + AOPM_AON_BLOCK_0)
+
+static const rtosTaskParameters main_task_params = {
+	.pvTaskCode = &main_task,
+	.pcTaskName = (char *)"main_task",
+	.uxPriority = configMAX_PRIORITIES - 1,
+	.pvParameters = NULL,
+	.uxStackDepthBytes = 256,
+};
+
+static bool spe_can_access_soc(void)
+{
+	uint32_t val;
+	uint32_t aon2snic_req;
+
+	val = readl(AOPM_AON_BLOCK_REG);
+	aon2snic_req = NV_DRF_VAL(AOPM, AON_BLOCK, AON2SNIC_REQ, val);
+
+	return (aon2snic_req == 0UL);
+}
+
+error_t spe_late_init(void)
+{
+	/* check if SPE access to SOC is unblocked */
+	if (tegra_platform_is_silicon()) {
+		if (!spe_can_access_soc())
+		{
+			printf("spe waiting on blocked SOC access...!\r\n");
+			while (!spe_can_access_soc())
+				;
+		}
+	}
+
+	spe_clk_setup_cpu_nic(CLK_SRC_PLLP);
+	spe_clk_setup_apb(CLK_SRC_PLLP);
+
+	spe_pm_init();
+	tegra_hsp_init(&tegra_hsp_id_bpmp);
+	tegra_hsp_init(&tegra_hsp_id_top1);
+
+	if (rtosTaskCreate(&main_task_params, NULL) != rtosPASS)
+		error_hook("Couldn't create main_task");
+
+	return 0;
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/lic-map.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/lic-map.c
new file mode 100644
index 0000000..9792596
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/lic-map.c
@@ -0,0 +1,70 @@
+/*
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+
+#include <address_map_new.h>
+
+#include <error/common-errors.h>
+#include <lic/lic-tegra.h>
+#include <processor/irqs-lic.h>
+#include <hw-config/vic-irqs.h>
+
+#include <lic-map.h>
+#include <spe-errors.h>
+
+#define LIC_IRQ_OFFSET(_irq)  (AON_LIC_IRQ_ ## _irq - AON_LIC_IRQ_BASE)
+
+#define LIC_IRQ_MAPPING(_local_irq, _global_irq, _irq_line) \
+    [LIC_IRQ_OFFSET(_local_irq)] = TEGRA_LIC_INTERRUPT(_irq_line, _global_irq)
+
+#define LIC_IRQ_MAPPING_H(_local_irq, _global_irq, _irq_line, _isr, _isr_data) \
+    [LIC_IRQ_OFFSET(_local_irq)] = \
+            TEGRA_LIC_INTERRUPT_H(_irq_line, _global_irq, _isr, _isr_data)
+
+static const lic_irq_t aon_lic_map[] = {
+    LIC_IRQ_MAPPING(TOP_HSP1, TOP_HSP1_SHARED_4, INTERRUPT_LIC0),
+};
+
+error_t
+get_aon_lic_map(const lic_irq_t **lic_map,
+                uint32_t *lic_map_size)
+{
+    error_t ret = E_SUCCESS;
+
+    if (lic_map == NULL || lic_map_size == NULL) {
+        ret = E_SPE_ERR_NULL_PTR;
+        goto out;
+    }
+
+    *lic_map = aon_lic_map;
+    *lic_map_size = ARRAY_SIZE(aon_lic_map);
+
+out:
+    return ret;
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/relocate-dma.S b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/relocate-dma.S
new file mode 100644
index 0000000..670059f
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/relocate-dma.S
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <soc-common/hw-const.h>
+#include <asm/asm.h>
+#include <address_map_new.h>
+#include <argpcdma_flv_8ch_non_safe.h>
+
+.syntax unified
+.arm
+.align 2
+
+/**
+ * Copy a region of memory with DMA.
+ *
+ * This function must not use stack since it is used from very early boot to
+ * copy the TCM region from DRAM. It is also set to use 16-word burst size
+ * so it should only be used to copy regions that are aligned to 64 bytes.
+ *   - R0 = Destination address
+ *   - R1 = Source address
+ *   - R2 = Number of bytes
+ *
+ * void relocate_memcpy_dma(void *dst, const void *src, size_t size);
+ */
+
+#define CH_REG(_reg_) (GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ ## _reg_ ##_0 - GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0)
+#define CH_DRF_NUM(_r, _f, _v) (_v << GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ ## _r ## _0_ ## _f ## _SHIFT)
+#define CH_DRF_DEF(_r, _f, _v) CH_DRF_NUM(_r, _f, GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ ## _r ## _0_ ## _f ## _ ## _v)
+#define CH_DRF_FIELD(_r, _f) GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_ ## _r ## _0_ ## _f ##_FIELD
+
+FUNCTION(relocate_memcpy_dma)
+
+    r_dst   .req r0
+    r_src   .req r1
+    r_size  .req r2
+
+    /* Copy TCM overlay from DRAM using channel 0 */
+    r_ch0   .req r3
+
+	/* Disable virtualization */
+	ldr	r4, =0x0
+	ldr	r3, =(NV_ADDRESS_MAP_AON_DMA_BASE + \
+		      GPCDMA_FLV_8CH_NON_SAFE_COMMON_DMA_CHAN_VIRTUALIZATION_ENABLE_0)
+	str	r4, [r3]
+
+    /* load ch0 CSR into r3 */
+    ldr     r_ch0, gpcdma_ch0_base
+
+    /* check for BCOUNT word aligned (word_count - 1) */
+    lsrs r_size, r_size, #2
+    bxeq lr
+    sub  r_size, r_size, #1
+
+    /* Set destination address */
+    str r_dst, [r_ch0, #CH_REG(DST_PTR)]
+
+	/* clear error status */
+	ldr	r4, =0xffffffff
+	str	r4, [r_ch0, #CH_REG(ERR_STA)]
+
+    /* Set source address */
+    str r_src, [r_ch0, #CH_REG(SRC_PTR)]
+
+    /* Clear the high addresses */
+    mov r4, #0
+    str r4, [r_ch0, #CH_REG(HI_ADR_PTR)]
+
+    /* Write settings suitable for MEM2MEM in MC_SEQ */
+    ldr r4, ch0_mc_seq
+    str r4, [r_ch0, #CH_REG(MC_SEQ)]
+
+    /* Set BCOUNT */
+    str r_size, [r_ch0, #CH_REG(WCOUNT)]
+
+    /* Write MEM2MEM transfer settings and enable */
+    ldr r4, ch0_csr
+    str r4, [r_ch0, #CH_REG(CSR)]
+
+    /* spin waiting for the DMA to complete */
+wait_dma:
+    /* Load channel status register value */
+    ldr r4, [r_ch0, #CH_REG(STA)]
+    /* Compare busy field value against active flag */
+    and r4, #CH_DRF_FIELD(STA, BSY)
+    cmp r4, #0
+    bne wait_dma
+
+    .unreq r_ch0
+
+    /* Done */
+    bx  lr
+
+.ltorg
+END_FUNCTION(relocate_memcpy_dma)
+
+gpcdma_ch0_base:
+    .word NV_ADDRESS_MAP_AON_DMA_BASE + GPCDMA_FLV_8CH_NON_SAFE_CHANNEL_CH0_CSR_0
+ch0_csr:
+    .word CH_DRF_DEF(CSR, ENB, ENABLE) | \
+        CH_DRF_DEF(CSR, ONCE, SINGLE_BLOCK) | \
+        CH_DRF_DEF(CSR, IE_EOC, DISABLE) | \
+        CH_DRF_DEF(CSR, DMA_MODE, MEM2MEM) | \
+        CH_DRF_DEF(CSR, FC_MODE, NO_MMIO) | \
+        CH_DRF_DEF(CSR, IRQ_MASK, ENABLE) | \
+        CH_DRF_NUM(CSR, WEIGHT, 1)
+ch0_mc_seq:
+    .word CH_DRF_DEF(MC_SEQ, MC_DATA_SWAP, DISABLE) | \
+        CH_DRF_NUM(MC_SEQ, MC_REQ_CNT, 1) | \
+        CH_DRF_DEF(MC_SEQ, MC_BURST, DMA_BURST_16WORDS) | \
+        CH_DRF_DEF(MC_SEQ, MC_ADDR_WRAP0, NO_WRAP) | \
+        CH_DRF_DEF(MC_SEQ, MC_ADDR_WRAP1, NO_WRAP)
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/spe-clk.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/spe-clk.c
new file mode 100644
index 0000000..be752df
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/spe-clk.c
@@ -0,0 +1,548 @@
+/*
+ * Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdbool.h>
+#include <osa/osa-task.h>
+
+#include <address_map_new.h>
+#include <arclk_rst.h>
+
+#include <misc/nvrm_drf.h>
+#include <error/common-errors.h>
+#include <clk/clk-tegra.h>
+#include <soc-common/clk-tegra-hw.h>
+#include <delay/delay.h>
+#include <err-hook.h>
+#include <misc/bitops.h>
+#include <misc/macros.h>
+#include <reg-access/reg-access.h>
+
+#include <spe-clk.h>
+
+/* All frequencies are in kHz */
+
+/* Not exact, but doesn't really matter */
+#define CLK_S_RATE 33
+#define PLLP_RATE 408000
+
+#define DIV_MAX 254
+
+#define ACTIVE_MODE_IDX 0
+#define ACTIVE_IRQFIQ_MODE_IDX 1
+
+#define PLLAON 0
+#define PLLP 1
+
+#define NFRAC_DIV (1 << 16)
+
+#define PLLAON_TIMEOUT_US 300
+
+struct pll {
+	uint32_t base;
+	uint32_t misc1;
+	bool has_n_frac;
+};
+
+struct clk_src_data {
+	uint32_t freq;
+	uint32_t src_idx;
+	struct pll *pll;
+};
+
+static uint32_t osc_freq;
+
+static struct pll plls[] = {
+    [PLLAON] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_PLLAON_BASE_0,
+	.misc1 = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_PLLAON_MISC_1_0,
+	.has_n_frac = true,
+    },
+    [PLLP] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_PLLP_BASE_0,
+	.has_n_frac = false,
+    },
+};
+
+static struct clk_src_data clk_srcs[] = {
+    [CLK_SRC_PLLAON] = {
+	.src_idx = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_AON_CPU_NIC,
+			      AON_CPU_NIC_CLK_SRC, pllAON_out),
+	.pll = &plls[PLLAON],
+    },
+    [CLK_SRC_PLLP] = {
+	.freq = PLLP_RATE,
+	.src_idx = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_AON_CPU_NIC, AON_CPU_NIC_CLK_SRC, PLLP_OUT0),
+	.pll = &plls[PLLP],
+    },
+    [CLK_SRC_OSC_UNDIV] = {
+	.src_idx = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_AON_CPU_NIC, AON_CPU_NIC_CLK_SRC, OSC_UNDIV),
+    },
+    [CLK_SRC_CLK_S] = {
+	.freq = CLK_S_RATE,
+	.src_idx = NV_DRF_DEF(CLK_RST_CONTROLLER, CLK_SOURCE_AON_CPU_NIC, AON_CPU_NIC_CLK_SRC, CLK_S),
+    },
+};
+
+struct clk
+{
+	uint32_t base;
+	uint32_t max_freq;
+	uint32_t freq;
+	uint32_t parent_freq;
+	int src;
+};
+
+static struct clk clk_ids[] = {
+    [CLK_ID_AON_CPU_NIC_ACTIVE] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE +
+		CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_0,
+	.max_freq = AON_CPU_MAX_RATE,
+    },
+    [CLK_ID_AON_CPU_NIC_ACTIVE_IRQFIQ] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_ACTIVE_IRQFIQ_0,
+	.max_freq = AON_CPU_MAX_RATE,
+    },
+    [CLK_ID_AON_CPU_NIC_IDLE_SHALLOW] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_SHALLOW_0,
+	.max_freq = AON_CPU_MAX_RATE,
+    },
+    [CLK_ID_AON_CPU_NIC_IDLE_DEEP] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_IDLE_DEEP_0,
+	.max_freq = AON_CPU_MAX_RATE,
+    },
+    [CLK_ID_AON_CPU_NIC_STBY_SHALLOW] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_SHALLOW_0,
+	.max_freq = AON_CPU_MAX_RATE,
+    },
+    [CLK_ID_AON_CPU_NIC_STBY_DEEP] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_STBY_DEEP_0,
+	.max_freq = AON_CPU_MAX_RATE,
+    },
+    [CLK_ID_AON_CPU_NIC_DORMANT_SHALLOW] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_SHALLOW_0,
+	.max_freq = AON_CPU_MAX_RATE,
+    },
+    [CLK_ID_AON_CPU_NIC_DORMANT_DEEP] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_TGT_DORMANT_DEEP_0,
+	.max_freq = AON_CPU_MAX_RATE,
+    },
+    [CLK_ID_AON_APB_ACTIVE] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_0,
+	.max_freq = AON_APB_MAX_RATE,
+    },
+    [CLK_ID_AON_APB_ACTIVE_IRQFIQ] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_ACTIVE_IRQFIQ_0,
+	.max_freq = AON_APB_MAX_RATE,
+    },
+    [CLK_ID_AON_APB_IDLE_SHALLOW] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_SHALLOW_0,
+	.max_freq = AON_APB_MAX_RATE,
+    },
+    [CLK_ID_AON_APB_IDLE_DEEP] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_IDLE_DEEP_0,
+	.max_freq = AON_APB_MAX_RATE,
+    },
+    [CLK_ID_AON_APB_STBY_SHALLOW] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_SHALLOW_0,
+	.max_freq = AON_APB_MAX_RATE,
+    },
+    [CLK_ID_AON_APB_STBY_DEEP] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_STBY_DEEP_0,
+	.max_freq = AON_APB_MAX_RATE,
+    },
+    [CLK_ID_AON_APB_DORMANT_SHALLOW] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_SHALLOW_0,
+	.max_freq = AON_APB_MAX_RATE,
+    },
+    [CLK_ID_AON_APB_DORMANT_DEEP] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_TGT_DORMANT_DEEP_0,
+	.max_freq = AON_APB_MAX_RATE,
+    },
+    [CLK_ID_AON_CPU_NIC] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC_0,
+	.max_freq = AON_CPU_MAX_RATE,
+    },
+    [CLK_ID_AON_APB] = {
+	.base = NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB_0,
+	.max_freq = AON_APB_MAX_RATE,
+    },
+};
+
+static uint32_t read_pll_freq(struct pll *pll)
+{
+	int32_t m, n, p, freq, n_frac;
+	uint32_t val;
+
+	val = readl(pll->base);
+	p = NV_DRF_VAL(CLK_RST_CONTROLLER, PLLAON_BASE, PLLAON_DIVP, val);
+	n = NV_DRF_VAL(CLK_RST_CONTROLLER, PLLAON_MISC_1, PLLAON_DIVN, val);
+	m = NV_DRF_VAL(CLK_RST_CONTROLLER, PLLAON_BASE, PLLAON_DIVM, val);
+
+	if (pll->has_n_frac) {
+		val = readl(pll->misc1);
+		val = NV_DRF_VAL(CLK_RST_CONTROLLER, PLLAON_MISC_1, PLLAON_DIVN_FRAC, val);
+		/* sign extend from 16 to 32 bits */
+		if (val & (1 << 15))
+			n_frac = val | 0xffff0000;
+		else
+			n_frac = val;
+	}
+	else {
+		n_frac = 0;
+	}
+
+	freq = (((int32_t)osc_freq * n) + (((int32_t)osc_freq * n_frac) /
+					   NFRAC_DIV)) /
+	       (m * p);
+
+	return (uint32_t)freq;
+}
+
+void spe_clk_init(void)
+{
+	uint32_t val;
+	uint32_t pll_aon_freq;
+
+	val = readl(NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_OSC_CTRL_0);
+	val = NV_DRF_VAL(CLK_RST_CONTROLLER, OSC_CTRL, OSC_FREQ, val);
+
+	switch (val) {
+	case CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC12:
+		osc_freq = 12000;
+		break;
+	case CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC13:
+		osc_freq = 13000;
+		break;
+	case CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC16P8:
+		osc_freq = 16800;
+		break;
+	case CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC19P2:
+		osc_freq = 19200;
+		break;
+	case CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC26:
+		osc_freq = 26000;
+		break;
+	case CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC38P4:
+		osc_freq = 38400;
+		break;
+	case CLK_RST_CONTROLLER_OSC_CTRL_0_OSC_FREQ_OSC48:
+		osc_freq = 48000;
+		break;
+	default:
+		error_hook("Unsupported OSC frequency. Halting.");
+		while (1)
+			;
+	}
+
+	clk_srcs[CLK_SRC_OSC_UNDIV].freq = osc_freq;
+
+	pll_aon_freq = read_pll_freq(clk_srcs[CLK_SRC_PLLAON].pll);
+	clk_srcs[CLK_SRC_PLLAON].freq = pll_aon_freq;
+	tegra_parent_clk_set_rate(&tegra_parent_clk_pll_aon, pll_aon_freq);
+}
+
+int spe_clk_set_clk_freq(int clk_id, int clk_src, uint32_t freq)
+{
+	uint32_t parent_freq, src_idx;
+	uint32_t div, val;
+	struct clk *id;
+
+	if (freq == 0UL)
+		return -1;
+
+	if (clk_id >= CLK_ID_MAX || clk_id < 0)
+		return -1;
+
+	if (clk_src >= CLK_SRC_MAX || clk_src < 0)
+		return -1;
+
+	id = &clk_ids[clk_id];
+	parent_freq = clk_srcs[clk_src].freq;
+	src_idx = clk_srcs[clk_src].src_idx;
+
+	if (parent_freq == 0UL)
+		return -1;
+
+	if (freq == id->freq && clk_src == id->src &&
+	    parent_freq == id->parent_freq)
+		return -1;
+
+	freq = (freq > parent_freq) ? parent_freq : freq;
+	freq = (freq > id->max_freq) ? id->max_freq : freq;
+
+	if (freq < (parent_freq / ((DIV_MAX >> 1) + 1)))
+		return -1;
+
+	/* Round the actual frequency down */
+	div = (parent_freq + freq - 1) / freq;
+
+	/* The actual divisor is (N/2)+1, where N is the programmed value */
+	div = (div - 1) << 1;
+
+	div = (div > DIV_MAX) ? DIV_MAX : div;
+
+	id->freq = parent_freq / ((div >> 1) + 1);
+	id->src = clk_src;
+	id->parent_freq = parent_freq;
+
+	val = NV_DRF_NUM(CLK_RST_CONTROLLER, CLK_SOURCE_AON_CPU_NIC,
+			 AON_CPU_NIC_CLK_DIVISOR, div) |
+	      src_idx;
+
+	writel(val, id->base);
+	return 0;
+}
+
+int spe_clk_set_clk_no_div(int clk_id, int clk_src)
+{
+	uint32_t freq;
+
+	if (clk_src >= CLK_SRC_MAX || clk_src < 0)
+		return -1;
+
+	freq = clk_srcs[clk_src].freq;
+
+	return spe_clk_set_clk_freq(clk_id, clk_src, freq);
+}
+
+void spe_clk_trigger_switch_fsm(void)
+{
+	uint32_t val;
+
+	/* Switch current clock to ACTIVE_IRQFIQ clock */
+	do {
+		val = readl(NV_ADDRESS_MAP_CAR_BASE +
+			    CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0);
+		val = NV_DRF_VAL(CLK_RST_CONTROLLER, AON_SEQ_SW_INTERFACE_CTL,
+				 AON_SW_TGT_ACK, val);
+	} while (val);
+	val = NV_DRF_NUM(CLK_RST_CONTROLLER, AON_SEQ_SW_INTERFACE_CTL,
+			 AON_SW_TGT_STATE, ACTIVE_IRQFIQ_MODE_IDX) |
+	      NV_DRF_NUM(CLK_RST_CONTROLLER, AON_SEQ_SW_INTERFACE_CTL,
+			 AON_SW_TGT_REQ, 1);
+	writel(val, NV_ADDRESS_MAP_CAR_BASE +
+			CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0);
+	do {
+		val = readl(NV_ADDRESS_MAP_CAR_BASE +
+			    CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0);
+		val = NV_DRF_VAL(CLK_RST_CONTROLLER, AON_SEQ_SW_INTERFACE_CTL,
+				 AON_SW_TGT_ACK, val);
+	} while (!val);
+	val = NV_DRF_NUM(CLK_RST_CONTROLLER, AON_SEQ_SW_INTERFACE_CTL,
+			 AON_SW_TGT_STATE, ACTIVE_IRQFIQ_MODE_IDX);
+	writel(val, NV_ADDRESS_MAP_CAR_BASE +
+			CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0);
+	do {
+		val = readl(NV_ADDRESS_MAP_CAR_BASE +
+			    CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0);
+		val = NV_DRF_VAL(CLK_RST_CONTROLLER, AON_SEQ_SW_INTERFACE_CTL,
+				 AON_SW_TGT_ACK, val);
+	} while (val);
+	/* Switch current clock back to ACTIVE clock */
+	val = NV_DRF_NUM(CLK_RST_CONTROLLER, AON_SEQ_SW_INTERFACE_CTL,
+			 AON_SW_TGT_STATE, ACTIVE_MODE_IDX) |
+	      NV_DRF_NUM(CLK_RST_CONTROLLER, AON_SEQ_SW_INTERFACE_CTL,
+			 AON_SW_TGT_REQ, 1);
+	writel(val, NV_ADDRESS_MAP_CAR_BASE +
+			CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0);
+	do {
+		val = readl(NV_ADDRESS_MAP_CAR_BASE +
+			    CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0);
+		val = NV_DRF_VAL(CLK_RST_CONTROLLER, AON_SEQ_SW_INTERFACE_CTL,
+				 AON_SW_TGT_ACK, val);
+	} while (!val);
+	val = NV_DRF_NUM(CLK_RST_CONTROLLER, AON_SEQ_SW_INTERFACE_CTL,
+			 AON_SW_TGT_STATE, ACTIVE_MODE_IDX);
+	writel(val, NV_ADDRESS_MAP_CAR_BASE +
+			CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0);
+	do {
+		val = readl(NV_ADDRESS_MAP_CAR_BASE +
+			    CLK_RST_CONTROLLER_AON_SEQ_SW_INTERFACE_CTL_0);
+		val = NV_DRF_VAL(CLK_RST_CONTROLLER, AON_SEQ_SW_INTERFACE_CTL,
+				 AON_SW_TGT_ACK, val);
+	} while (val);
+}
+
+static int wait_for_bit_set(uint32_t reg, uint32_t bit)
+{
+	uint64_t t_begin = get_time_ticks();
+	uint32_t val;
+
+	do {
+		val = readl(reg);
+		if (val & bit)
+			return 0;
+		udelay(1);
+
+	} while (get_time_delta_us(t_begin) < PLLAON_TIMEOUT_US);
+
+	return -1;
+}
+
+static int wait_for_pllaon_fll_lock(void)
+{
+	return wait_for_bit_set(NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_PLLAON_BASE_0,
+				1 << CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_FREQ_LOCK_SHIFT);
+}
+
+static int wait_for_pllaon_pll_lock(void)
+{
+	return wait_for_bit_set(NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_PLLAON_BASE_0,
+				1 << CLK_RST_CONTROLLER_PLLAON_BASE_0_PLLAON_LOCK_SHIFT);
+}
+
+void disable_pllaon(void)
+{
+	uint32_t val;
+
+	val = readl(NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_PLLAON_BASE_0);
+	val = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, PLLAON_BASE, PLLAON_ENABLE,
+				 DISABLE, val);
+	writel(val, NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_PLLAON_BASE_0);
+
+	val = readl(NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_PLLAON_MISC_1_0);
+	val = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, PLLAON_MISC_1, PLLAON_IDDQ,
+				 ON, val);
+	writel(val, NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_PLLAON_MISC_1_0);
+}
+
+void enable_pllaon(void)
+{
+	uint32_t val;
+
+	val = readl(NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_PLLAON_MISC_1_0);
+	val = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, PLLAON_MISC_1, PLLAON_IDDQ,
+				 OFF, val);
+	writel(val, NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_PLLAON_MISC_1_0);
+
+	udelay(2);
+
+	val = readl(NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_PLLAON_BASE_0);
+	val = NV_FLD_SET_DRF_DEF(CLK_RST_CONTROLLER, PLLAON_BASE, PLLAON_ENABLE,
+				 ENABLE, val);
+	writel(val, NV_ADDRESS_MAP_CAR_BASE + CLK_RST_CONTROLLER_PLLAON_BASE_0);
+
+	/* wait for lock */
+	if (wait_for_pllaon_fll_lock()) {
+		error_hook("Fatal: pll_aon did not lock!");
+		rtosTaskEnterCritical();
+		while (1)
+			;
+	}
+
+	/* wait for lock */
+	if (wait_for_pllaon_pll_lock()) {
+		error_hook("Fatal: pll_aon did not lock!");
+		rtosTaskEnterCritical();
+		while (1)
+			;
+	}
+}
+
+void spe_clk_setup_apb(uint32_t clk_src)
+{
+	uint32_t reg;
+	uint32_t val;
+
+	reg = CLK_SRC(AON_APB);
+	val = readl(reg);
+
+	switch (clk_src) {
+	case CLK_SRC_PLLP:
+		val = CAR_FLD_SET_DRF_DEF(CLK_SOURCE_AON_APB,
+					  AON_APB_CLK_SRC,
+					  PLLP_OUT0, val);
+		/**
+		 * AON_APB is capped at 204Mhz. To avoid DVS unachievable
+		 * constraint on AON_APB, divide the PLLP_OUT0 by 2 to get
+		 * 204Mhz.
+		 */
+		val = CAR_FLD_SET_DRF_NUM(CLK_SOURCE_AON_APB,
+					  AON_APB_CLK_DIVISOR,
+					  2, val);
+		break;
+	case CLK_SRC_PLLAON:
+		val = CAR_FLD_SET_DRF_DEF(CLK_SOURCE_AON_APB,
+					  AON_APB_CLK_SRC,
+					  pllAON_out, val);
+		break;
+	case CLK_SRC_OSC_UNDIV:
+		val = CAR_FLD_SET_DRF_DEF(CLK_SOURCE_AON_APB,
+					  AON_APB_CLK_SRC,
+					  OSC_UNDIV, val);
+		break;
+	default:
+		error_hook("incorrect apb clk src! Selecting OSC_UNDIV\r\n");
+		val = CAR_FLD_SET_DRF_DEF(CLK_SOURCE_AON_APB,
+					  AON_APB_CLK_SRC,
+					  OSC_UNDIV, val);
+		break;
+	}
+
+	writel(val, reg);
+}
+
+void spe_clk_setup_cpu_nic(uint32_t clk_src)
+{
+	uint32_t reg;
+	uint32_t val;
+
+	reg = CLK_SRC(AON_CPU_NIC);
+	val = readl(reg);
+
+	switch (clk_src) {
+	case CLK_SRC_PLLP:
+		val = CAR_FLD_SET_DRF_DEF(CLK_SOURCE_AON_CPU_NIC,
+					  AON_CPU_NIC_CLK_SRC,
+					  PLLP_OUT0, val);
+		val = CAR_FLD_SET_DRF_NUM(CLK_SOURCE_AON_CPU_NIC,
+					  AON_CPU_NIC_CLK_DIVISOR,
+					  2, val);
+		break;
+	case CLK_SRC_PLLAON:
+		val = CAR_FLD_SET_DRF_DEF(CLK_SOURCE_AON_CPU_NIC,
+					  AON_CPU_NIC_CLK_SRC,
+					  pllAON_out, val);
+		break;
+	case CLK_SRC_OSC_UNDIV:
+		val = CAR_FLD_SET_DRF_DEF(CLK_SOURCE_AON_CPU_NIC,
+					  AON_CPU_NIC_CLK_SRC,
+					  OSC_UNDIV, val);
+		break;
+	default:
+		error_hook("incorrect cpu_nic clk src! Selecting OSC_UNDIV\r\n");
+		val = CAR_FLD_SET_DRF_DEF(CLK_SOURCE_AON_CPU_NIC,
+					  AON_CPU_NIC_CLK_SRC,
+					  OSC_UNDIV, val);
+		break;
+	}
+
+	writel(val, reg);
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/spe-lic.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/spe-lic.c
new file mode 100644
index 0000000..7c522a4
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/spe-lic.c
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+
+#include <error/common-errors.h>
+#include <lic/lic-tegra.h>
+#include <processor/irqs-lic.h>
+#include <debug/print.h>
+
+#include <spe-lic.h>
+#include <lic-map.h>
+#include <err-hook.h>
+
+void
+spe_lic_enable(const uint32_t irq)
+{
+    error_t ret;
+
+    ret = tegra_lic_irq_enable(&tegra_lic_id_aon, irq);
+    if (ret != E_SUCCESS) {
+        error_hookf("spe_lic_enable(%u) failed!\r\n", (unsigned int)irq);
+    }
+}
+
+void
+spe_lic_disable(const uint32_t irq)
+{
+    error_t ret;
+
+    ret = tegra_lic_irq_disable(&tegra_lic_id_aon, irq);
+    if (ret != E_SUCCESS) {
+        error_hookf("spe_lic_disable(%u) failed!\r\n", (unsigned int)irq);
+    }
+}
+
+error_t
+spe_lic_init(void)
+{
+    const lic_irq_t *lic_map;
+    uint32_t        lic_map_size;
+    error_t         ret;
+
+    ret = get_aon_lic_map(&lic_map, &lic_map_size);
+    if (ret != E_SUCCESS) {
+        error_hook("get_aon_lic_map() failed!\r\n");
+        goto out;
+    }
+
+    ret = tegra_lic_init(&tegra_lic_id_aon,
+                         lic_map,
+                         lic_map_size);
+
+out:
+    return ret;
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/spe-pm-sequencer.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/spe-pm-sequencer.c
new file mode 100644
index 0000000..77b14a4
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/spe-pm-sequencer.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdio.h>
+#include <stdint.h>
+#include <osa/rtos-task.h>
+
+#include <address_map_new.h>
+#include <arclk_rst.h>
+#include <araopm.h>
+#include <argpio_aon_sw.h>
+#include <arpmc_impl.h>
+#include <arwake.h>
+#include <arscratch.h>
+
+#include <misc/nvrm_drf.h>
+#include <debug/print.h>
+#include <delay/delay.h>
+#include <misc/macros.h>
+#include <reg-access/reg-access.h>
+#include <hsp/hsp-tegra.h>
+#include <processor/hsp-tegra-hw.h>
+
+#include <bpmp-ipc.h>
+#include <bpmp-ipc-protocol.h>
+#include <spe-clk.h>
+#include <spe-pm.h>
+#include <spe-vic.h>
+
+#define RAM_PG_CTRL_OFFSET 0
+#define RAM_PG_STATUS_OFFSET (PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0 - \
+			      PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0)
+#define RAM_CLAMP_CTRL_OFFSET (PMC_IMPL_PART_AOPG_CACHE_CLAMP_CONTROL_0 - \
+			       PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0)
+
+#define aopm_addr(offset) (NV_ADDRESS_MAP_AON_PM_BASE + offset)
+
+static enum pm_ram_pg_status cache_pg_state = PM_RAM_ON;
+
+static bool pllaon_disabled = true;
+
+static struct tegra_hsp_suspend_ctx top_hsp_ctx;
+
+void set_pllaon_state(bool enable)
+{
+	rtosTaskEnterCritical();
+	pllaon_disabled = !enable;
+	rtosTaskExitCritical();
+}
+
+bool is_pllaon_enabled(void)
+{
+	return !pllaon_disabled;
+}
+
+static enum pm_ram_pg_status pm_ram_powergate(uint32_t base)
+{
+	uint32_t val;
+
+	/* Start PG */
+	val = NV_DRF_DEF(PMC_IMPL, PART_AOPG_CACHE_POWER_GATE_CONTROL,
+			 INTER_PART_DELAY_EN, ENABLE);
+	val = NV_FLD_SET_DRF_DEF(PMC_IMPL, PART_AOPG_CACHE_POWER_GATE_CONTROL,
+				 SRAM_SLEEP_EN, ON, val);
+	val = NV_FLD_SET_DRF_DEF(PMC_IMPL, PART_AOPG_CACHE_POWER_GATE_CONTROL,
+				 LOGIC_SLEEP, ON, val);
+	val = NV_FLD_SET_DRF_DEF(PMC_IMPL, PART_AOPG_CACHE_POWER_GATE_CONTROL,
+				 START, PENDING, val);
+	writel(val, base + RAM_PG_CTRL_OFFSET);
+
+	/* Wait until PG is done */
+	do {
+		val = readl(base + RAM_PG_CTRL_OFFSET);
+		val = NV_DRF_VAL(PMC_IMPL, PART_AOPG_CACHE_POWER_GATE_CONTROL,
+				 START, val);
+	} while (val != PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_DONE);
+
+	/* Verify status */
+	val = readl(base + RAM_PG_STATUS_OFFSET);
+	val = NV_DRF_VAL(PMC_IMPL, PART_AOPG_CACHE_POWER_GATE_STATUS,
+			 SRAM_SLEEP_STS, val);
+	if (val == PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_ON)
+		return PM_RAM_OFF;
+	else
+		return PM_RAM_ERROR;
+}
+
+static enum pm_ram_pg_status pm_ram_unpowergate(uint32_t base)
+{
+	uint32_t val;
+
+	/* Start un-PG */
+	val = NV_DRF_DEF(PMC_IMPL, PART_AOPG_CACHE_POWER_GATE_CONTROL,
+			 INTER_PART_DELAY_EN, ENABLE);
+	val = NV_FLD_SET_DRF_DEF(PMC_IMPL, PART_AOPG_CACHE_POWER_GATE_CONTROL,
+				 START, PENDING, val);
+	writel(val, base + RAM_PG_CTRL_OFFSET);
+
+	/* Wait until un-PG is done */
+	do {
+		val = readl(base + RAM_PG_CTRL_OFFSET);
+		val = NV_DRF_VAL(PMC_IMPL, PART_AOPG_CACHE_POWER_GATE_CONTROL,
+				 START, val);
+	} while (val != PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0_START_DONE);
+
+	/* Verify status */
+	val = readl(base + RAM_PG_STATUS_OFFSET);
+	val = NV_DRF_VAL(PMC_IMPL, PART_AOPG_CACHE_POWER_GATE_STATUS,
+			 SRAM_SLEEP_STS, val);
+	if (val != PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_STATUS_0_SRAM_SLEEP_STS_OFF)
+		return PM_RAM_ERROR;
+
+	return PM_RAM_ON;
+}
+
+void pm_hw_init(void)
+{
+}
+
+void pm_turn_off_caches(void)
+{
+	if (cache_pg_state != PM_RAM_ON)
+		return;
+
+	cache_pg_state = pm_ram_powergate(NV_ADDRESS_MAP_PMC_IMPL_BASE +
+					  PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0);
+}
+
+void pm_turn_on_caches(void)
+{
+	if (cache_pg_state != PM_RAM_OFF)
+		return;
+
+	cache_pg_state = pm_ram_unpowergate(NV_ADDRESS_MAP_PMC_IMPL_BASE +
+					    PMC_IMPL_PART_AOPG_CACHE_POWER_GATE_CONTROL_0);
+}
+
+enum pm_ram_pg_status get_cache_power_status(void)
+{
+	return cache_pg_state;
+}
+
+static void suspend_soc_drivers(void)
+{
+    if (tegra_hsp_suspend(&tegra_hsp_id_top1, &top_hsp_ctx)) {
+        pr_error("Couldn't suspend HSP doorbells!");
+    }
+}
+
+static void resume_soc_drivers(void)
+{
+    tegra_hsp_resume(&tegra_hsp_id_top1, &top_hsp_ctx);
+}
+
+void pm_suspend_sc7(void)
+{
+	suspend_soc_drivers();
+	spe_clk_setup_cpu_nic(CLK_SRC_OSC_UNDIV);
+	spe_clk_setup_apb(CLK_SRC_OSC_UNDIV);
+}
+
+void pm_resume_sc7(void)
+{
+	resume_soc_drivers();
+	if (!pllaon_disabled) {
+		disable_pllaon();
+	}
+	spe_clk_setup_cpu_nic(CLK_SRC_PLLP);
+	spe_clk_setup_apb(CLK_SRC_PLLP);
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/tcu-ids.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/tcu-ids.c
new file mode 100644
index 0000000..3eabe56
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/tcu-ids.c
@@ -0,0 +1,279 @@
+/*
+ * Copyright (c) 2016-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <osa/osa-task.h>
+#include <osa/osa-errors.h>
+
+#include <address_map_new.h>
+#include <arfuse.h>
+
+#include <misc/attributes.h>
+#include <misc/bitops.h>
+#include <processor/hsp-tegra-hw.h>
+#include <reg-access/reg-access.h>
+
+#include <mbox-aon.h>
+#include <tcu.h>
+#include <tcu-priv.h>
+
+extern void tcu_tx_task(void *param);
+extern void tcu_rx_task(void *param);
+
+static bool fsi_enable_check(void);
+
+static tcu_client_t ext_clients[] = {
+    [TCU_ID_CCPLEX] = {
+        .id            = TCU_ID_CCPLEX,
+        .tag           = TCU_TAG_CCPLEX,
+        .hsp_id        = &tegra_hsp_id_top0,
+        .recv_mbox     = MBOX_AON_CCPLEX_UART,
+        .send_mbox     = 0,
+        .enabled       = true,
+        .aon_sm_for_tx = true,
+        .enable_check  = NULL,
+    },
+    [TCU_ID_BPMP] = {
+        .id            = TCU_ID_BPMP,
+        .tag           = TCU_TAG_BPMP,
+        .hsp_id        = &tegra_hsp_id_bpmp,
+        .recv_mbox     = MBOX_AON_BPMP_UART,
+        .send_mbox     = MBOX_BPMP_UART,
+        .enabled       = true,
+        .aon_sm_for_tx = true,
+        .enable_check  = NULL,
+    },
+    [TCU_ID_SCE]  = {
+        .id            = TCU_ID_SCE,
+        .tag           = TCU_TAG_SCE,
+        .recv_mbox     = MBOX_AON_SCE_UART,
+        .send_mbox     = 0,
+        .enabled       = true,
+        .aon_sm_for_tx = true,
+        .enable_check  = NULL,
+    },
+    [TCU_ID_TZ]  = {
+        .id            = TCU_ID_TZ,
+        .tag           = TCU_TAG_TZ,
+        .recv_mbox     = MBOX_AON_TZ_UART,
+        .enabled       = true,
+        .aon_sm_for_tx = true,
+        .enable_check  = NULL,
+    },
+    [TCU_ID_RCE]  = {
+        .id            = TCU_ID_RCE,
+        .tag           = TCU_TAG_RCE,
+        .recv_mbox     = MBOX_AON_RCE_UART,
+        .enabled       = true,
+        .aon_sm_for_tx = true,
+        .enable_check  = NULL,
+    },
+    [TCU_ID_FSI]  = {
+        .id            = TCU_ID_FSI,
+        .tag           = TCU_TAG_FSI,
+        .hsp_tx_id     = &tegra_hsp_id_top1,
+        .hsp_id        = &tegra_hsp_id_fsi,
+        .recv_mbox     = MBOX_TX_FSI_UART,
+        .send_mbox     = MBOX_FSI_UART,
+        .enabled       = true,
+        .aon_sm_for_tx = false,
+        .enable_check  = &fsi_enable_check,
+    },
+    [TCU_ID_PSC]  = {
+        .id            = TCU_ID_PSC,
+        .tag           = TCU_TAG_PSC,
+        .recv_mbox     = MBOX_AON_PSC_UART,
+        .enabled       = true,
+        .aon_sm_for_tx = true,
+        .enable_check  = NULL,
+    },
+    [TCU_ID_DCE]  = {
+        .id            = TCU_ID_DCE,
+        .tag           = TCU_TAG_DCE,
+        .recv_mbox     = MBOX_AON_DCE_UART,
+        .enabled       = true,
+        .aon_sm_for_tx = true,
+        .enable_check  = NULL,
+    },
+};
+
+static tcu_client_t *tag_to_ext_client[] = {
+    [TCU_TAG_CCPLEX - TCU_TAG_MIN] = &ext_clients[TCU_ID_CCPLEX],
+    [TCU_TAG_BPMP - TCU_TAG_MIN] = &ext_clients[TCU_ID_BPMP],
+    [TCU_TAG_SCE - TCU_TAG_MIN] = &ext_clients[TCU_ID_SCE],
+    [TCU_TAG_TZ - TCU_TAG_MIN] = &ext_clients[TCU_ID_TZ],
+    [TCU_TAG_RCE - TCU_TAG_MIN] = &ext_clients[TCU_ID_RCE],
+    [TCU_TAG_FSI - TCU_TAG_MIN] = &ext_clients[TCU_ID_FSI],
+    [TCU_TAG_PSC - TCU_TAG_MIN] = &ext_clients[TCU_ID_PSC],
+    [TCU_TAG_DCE - TCU_TAG_MIN] = &ext_clients[TCU_ID_DCE],
+};
+
+rtos_task_define_s(tcu_tx_task_ccplex,
+                   tcu_tx_task,
+                   (char *)"tcu_tx_ccplex",
+                   configMAX_PRIORITIES - 5,
+                   &ext_clients[TCU_ID_CCPLEX],
+                   configMINIMAL_STACK_SIZE);
+
+rtos_task_define_s(tcu_rx_task_ccplex,
+                   tcu_rx_task,
+                   (char *)"tcu_rx_ccplex",
+                   configMAX_PRIORITIES - 6,
+                   &ext_clients[TCU_ID_CCPLEX],
+                   configMINIMAL_STACK_SIZE);
+
+
+rtos_task_define_s(tcu_tx_task_bpmp,
+                   tcu_tx_task,
+                   (char *)"tcu_tx_bpmp",
+                   configMAX_PRIORITIES - 5,
+                   &ext_clients[TCU_ID_BPMP],
+                   configMINIMAL_STACK_SIZE);
+
+rtos_task_define_s(tcu_rx_task_bpmp,
+                   tcu_rx_task,
+                   (char *)"tcu_rx_bpmp",
+                   configMAX_PRIORITIES - 6,
+                   &ext_clients[TCU_ID_BPMP],
+                   configMINIMAL_STACK_SIZE);
+
+rtos_task_define_s(tcu_tx_task_sce,
+                   tcu_tx_task,
+                   (char *)"tcu_tx_sce",
+                   configMAX_PRIORITIES - 5,
+                   &ext_clients[TCU_ID_SCE],
+                   configMINIMAL_STACK_SIZE);
+
+rtos_task_define_s(tcu_tx_task_tz,
+                   tcu_tx_task,
+                   (char *)"tcu_tx_tz",
+                   configMAX_PRIORITIES - 5,
+                   &ext_clients[TCU_ID_TZ],
+                   configMINIMAL_STACK_SIZE);
+
+rtos_task_define_s(tcu_tx_task_rce,
+                   tcu_tx_task,
+                   (char *)"tcu_tx_rce",
+                   configMAX_PRIORITIES - 5,
+                   &ext_clients[TCU_ID_RCE],
+                   configMINIMAL_STACK_SIZE);
+
+rtos_task_define_s(tcu_tx_task_fsi,
+                   tcu_tx_task,
+                   (char *)"tcu_tx_fsi",
+                   configMAX_PRIORITIES - 5,
+                   &ext_clients[TCU_ID_FSI],
+                   configMINIMAL_STACK_SIZE);
+
+rtos_task_define_s(tcu_rx_task_fsi,
+                   tcu_rx_task,
+                   (char *)"tcu_rx_fsi",
+                   configMAX_PRIORITIES - 6,
+                   &ext_clients[TCU_ID_FSI],
+                   configMINIMAL_STACK_SIZE);
+
+rtos_task_define_s(tcu_tx_task_psc,
+				   tcu_tx_task,
+				   (char *)"tcu_tx_fsi",
+                   configMAX_PRIORITIES - 5,
+                   &ext_clients[TCU_ID_PSC],
+				   configMINIMAL_STACK_SIZE);
+
+rtos_task_define_s(tcu_tx_task_dce,
+                   tcu_tx_task,
+                   (char *)"tcu_tx_dce",
+                   configMAX_PRIORITIES - 5,
+                   &ext_clients[TCU_ID_DCE],
+                   configMINIMAL_STACK_SIZE);
+
+static const rtosTaskParameters* tcu_clients_tx_task_params[] = {
+    [TCU_ID_CCPLEX] = &tcu_tx_task_ccplex_params,
+    [TCU_ID_BPMP]   = &tcu_tx_task_bpmp_params,
+    [TCU_ID_SCE]    = &tcu_tx_task_sce_params,
+    [TCU_ID_TZ]     = &tcu_tx_task_tz_params,
+    [TCU_ID_RCE]    = &tcu_tx_task_rce_params,
+    [TCU_ID_FSI]    = &tcu_tx_task_fsi_params,
+    [TCU_ID_PSC]    = &tcu_tx_task_psc_params,
+    [TCU_ID_DCE]    = &tcu_tx_task_dce_params,
+};
+
+static const rtosTaskParameters* tcu_clients_rx_task_params[] = {
+    [TCU_ID_CCPLEX] = &tcu_rx_task_ccplex_params,
+    [TCU_ID_BPMP]   = &tcu_rx_task_bpmp_params,
+    [TCU_ID_SCE]    = NULL,
+    [TCU_ID_TZ]     = NULL,
+    [TCU_ID_RCE]    = NULL,
+    [TCU_ID_FSI]    = &tcu_rx_task_fsi_params,
+    [TCU_ID_PSC]    = NULL,
+    [TCU_ID_DCE]    = NULL,
+};
+
+static bool fsi_enable_check(void)
+{
+    uint32_t fsi_en;
+
+    fsi_en = readl(NV_ADDRESS_MAP_FUSE_BASE + FUSE_OPT_FSI_DISABLE_0);
+
+    return (fsi_en == 0UL);
+}
+
+uint32_t get_tcu_client_count(void)
+{
+    return ARRAY_SIZE(ext_clients);
+}
+
+tcu_client_t* get_tcu_clients_handle(void)
+{
+    return ext_clients;
+}
+
+tcu_client_t* get_tcu_client_id(char tag)
+{
+    tcu_client_t *dest_id = &ext_clients[TCU_ID_CCPLEX];
+    uint8_t      t = (uint8_t)tag;
+
+    if (t >= TCU_TAG_MIN && t <= TCU_TAG_MAX) {
+        dest_id = tag_to_ext_client[t - TCU_TAG_MIN];
+    }
+
+    return dest_id;
+}
+
+const rtosTaskParameters* get_tcu_client_tx_task_params(uint8_t client_id)
+{
+    return (client_id > ARRAY_SIZE(ext_clients)) ?
+           NULL : tcu_clients_tx_task_params[client_id];
+}
+
+const rtosTaskParameters* get_tcu_client_rx_task_params(uint8_t client_id)
+{
+    return (client_id > ARRAY_SIZE(ext_clients)) ?
+           NULL : tcu_clients_rx_task_params[client_id];
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/tegra-lic.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/tegra-lic.c
new file mode 100644
index 0000000..ef03db3
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/tegra-lic.c
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2022, NVIDIA CORPORATION. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "tegra-lic.h"
+#include <spe-lic.h>
+
+void lic_init(void)
+{
+	spe_lic_init();
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/uart-t234.c b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/uart-t234.c
new file mode 100644
index 0000000..7d7c2e7
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/src/uart-t234.c
@@ -0,0 +1,131 @@
+/*
+ * Copyright (c) 2021-2022, NVIDIA CORPORATION.  All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *  * Neither the name of NVIDIA CORPORATION nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+ * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+ * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+ * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* Compiler headers */
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+
+/* local os headers */
+
+/* Early FSP headers */
+
+/* Hardware headers */
+
+/* Late FSP headers */
+#include <misc/macros.h>
+#include <processor/debug-hw.h>
+#include <uart/uart.h>
+
+/* local headers */
+#include <spe-uart.h>
+#include <uart-tegra.h>
+
+#define TEGRA234_UART_PORT_A (0UL)
+#define TEGRA234_UART_PORT_B (1UL)
+#define TEGRA234_UART_PORT_C (2UL)
+#define TEGRA234_UART_PORT_D (3UL)
+#define TEGRA234_UART_PORT_E (4UL)
+#define TEGRA234_UART_PORT_F (5UL)
+
+/* Default to UARTC */
+static uint32_t uart_port = TEGRA234_UART_PORT_C;
+
+static const struct tegra_uart_conf uart_t234_conf = {
+    .parity     = TEGRA_UART_NO_PARITY,
+    .stop_bits  = TEGRA_UART_STOP_BITS_1,
+    .data_bits  = TEGRA_UART_DATA_BITS_8,
+    .baud       = 115200UL,
+};
+
+static const struct spe_uart_ops legacy_ops = {
+    .init           = &tegra_uart_init,
+    .init_3rdparty  = &tegra_uart_3rdparty_init,
+    .write_now      = &tegra_uart_write_now,
+    .write          = &tegra_uart_write,
+    .flush          = &tegra_uart_flush_tx_fifo,
+    .flush_hw       = &tegra_uart_flush_tx_hw_fifo,
+    .read           = &tegra_uart_read,
+    .suspend        = &tegra_uart_suspend,
+    .resume         = &tegra_uart_resume,
+};
+
+static struct spe_uart spe_uart_t234[] = {
+    [TEGRA234_UART_PORT_A] = {
+        .ctlr       = NULL,
+        .conf       = NULL,
+        .ops        = NULL,
+    },
+    [TEGRA234_UART_PORT_B] = {
+        .ctlr       = NULL,
+        .conf       = NULL,
+        .ops        = NULL,
+    },
+    [TEGRA234_UART_PORT_C] = {
+        .ctlr       = &tegra_uart_ctlr_uartc,
+        .conf       = &uart_t234_conf,
+        .ops        = &legacy_ops,
+    },
+    [TEGRA234_UART_PORT_D] = {
+        .ctlr       = NULL,
+        .conf       = NULL,
+        .ops        = NULL,
+    },
+    [TEGRA234_UART_PORT_E] = {
+        .ctlr       = NULL,
+        .conf       = NULL,
+        .ops        = NULL,
+    },
+    [TEGRA234_UART_PORT_F] = {
+        .ctlr       = NULL,
+        .conf       = NULL,
+        .ops        = NULL,
+    },
+};
+
+struct spe_uart *spe_uart_get(const uint32_t port_id)
+{
+    struct spe_uart *uart = NULL;
+
+    if (port_id > ARRAY_SIZE(spe_uart_t234)) {
+        goto out;
+    }
+
+    uart = &spe_uart_t234[port_id];
+    uart_port = port_id;
+
+out:
+    return uart;
+}
+
+void spe_uart_write_now(const char *buf, uint32_t count)
+{
+    struct spe_uart *uart = &spe_uart_t234[uart_port];
+
+    uart->ops->write_now(uart->ctlr, buf, count);
+}
diff --git a/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/target_specific.mk b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/target_specific.mk
new file mode 100644
index 0000000..0c4162e
--- /dev/null
+++ b/spe-freertos-bsp/rt-aux-cpu-demo-fsp/soc/t23x/target_specific.mk
@@ -0,0 +1,123 @@
+# Copyright (c) 2021-2024, NVIDIA CORPORATION. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#  * Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+#  * Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+#  * Neither the name of NVIDIA CORPORATION nor the names of its
+#    contributors may be used to endorse or promote products derived
+#    from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ``AS IS'' AND ANY
+# EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+# PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR
+# CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+# EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+# PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
+# OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+
+TARGET_INCLUDES := \
+	$(SPE_TARGET_DIR)/include/ \
+	$(SPE_TARGET_DIR)/config/ \
+	$(FSP_SRC_DIR)/include/soc/t234/aon/ \
+	$(FSP_SRC_DIR)/include/soc/t234/
+
+TARGET_SRCS := \
+	$(SPE_TARGET_DIR)/src/clk.c \
+	$(SPE_TARGET_DIR)/src/init_padctrl.c \
+	$(SPE_TARGET_DIR)/src/spe-clk.c \
+	$(SPE_TARGET_DIR)/src/spe-pm-sequencer.c \
+	$(SPE_TARGET_DIR)/src/late-init.c \
+	$(SPE_TARGET_DIR)/src/relocate-dma.S \
+	$(SPE_TARGET_DIR)/src/boot.S \
+	$(SPE_TARGET_DIR)/src/lic-map.c \
+	$(SPE_TARGET_DIR)/src/spe-lic.c \
+	$(SPE_TARGET_DIR)/src/interrupt.c \
+	$(SPE_TARGET_DIR)/src/tegra-lic.c \
+	$(FSP_SRC_DIR)/drivers/lic/lic-tegra.c \
+	$(SPE_TARGET_DIR)/src/uart-t234.c \
+	$(SPE_TARGET_DIR)/src/tcu-ids.c \
+	$(FSP_SRC_DIR)/drivers/hsp/hsp-tegra-sm-128.c  \
+	$(FSP_SRC_DIR)/soc/t234/ids/aon/uart-tegra-ids.c \
+	$(FSP_SRC_DIR)/soc/t234/ids/aon/hsp-tegra-ids.c \
+	$(FSP_SRC_DIR)/soc/t234/ids/aon/tke-tegra-ids.c \
+	$(FSP_SRC_DIR)/soc/t234/ids/aon/ast-tegra-ids.c \
+	$(FSP_SRC_DIR)/soc/t234/ids/aon/irqapi-vic-ids.c \
+	$(FSP_SRC_DIR)/soc/t234/ids/aon/lic-tegra-ids.c \
+	$(FSP_SRC_DIR)/soc/t234/ids/soc-common/clk-tegra.c
+
+# Enable = 1/Disable = 0 GPCDMA functionality
+ENABLE_GPCDMA_FUNC := 0
+
+# Enable = 1/Disable = 0 AODMIC sample app
+ENABLE_AODMIC_APP := 0
+
+# Enable = 1/Disable = 0 SPI sample app
+ENABLE_SPI_APP := 0
+ifeq ($(ENABLE_SPI_APP), 1)
+	ENABLE_GPCDMA_FUNC := 1
+	TARGET_SRCS += \
+		$(FSP_SRC_DIR)/soc/t234/ids/aon/spi-ids.c \
+		$(FSP_SRC_DIR)/soc/t234/port/aon/spi-port.c
+endif
+
+ENABLE_SPI_SLV_APP := 0
+ifeq ($(ENABLE_SPI_SLV_APP), 1)
+	ENABLE_GPCDMA_FUNC := 1
+	TARGET_SRCS += \
+		$(FSP_SRC_DIR)/soc/t234/ids/aon/spi-ids.c \
+		$(FSP_SRC_DIR)/soc/t234/port/aon/spi-port.c
+endif
+
+ifeq ($(ENABLE_AODMIC_APP), 1)
+	ENABLE_GPCDMA_FUNC := 1
+	TARGET_SRCS += \
+		$(FSP_SRC_DIR)/soc/t234/port/aon/aodmic-port.c \
+		$(FSP_SRC_DIR)/soc/t234/ids/aon/aodmic-tegra-ids.c
+endif
+
+ifeq ($(ENABLE_GPCDMA_FUNC), 1)
+	TARGET_SRCS += \
+		$(FSP_SRC_DIR)/soc/t234/ids/aon/gpcdma-ids.c \
+		$(FSP_SRC_DIR)/soc/t234/port/aon/gpcdma-port.c
+endif
+
+# Enable = 1/Disable = 0 timer sample app
+ENABLE_TIMER_APP := 0
+
+# Enable = 1/Disable = 0 GPIO sample app
+ENABLE_GPIO_APP := 0
+
+# Enable = 1/Disable = 0 GTE sample app
+ENABLE_GTE_APP := 0
+
+# GTE app requires GPIO app to be compiled as well
+ifeq ($(ENABLE_GTE_APP), 1)
+	ENABLE_GPIO_APP := 1
+endif
+
+ifeq ($(ENABLE_GPIO_APP), 1)
+	TARGET_SRCS += \
+		$(FSP_SRC_DIR)/soc/t234/ids/aon/gpio-aon-tegra-ids.c \
+		$(FSP_SRC_DIR)/soc/t234/ids/aon/gpio-main-tegra-ids.c \
+		$(FSP_SRC_DIR)/soc/t234/ids/aon/gpio-tegra-ids.c
+endif
+
+# Enable = 1/Disable = 0 I2C sample app
+ENABLE_I2C_APP := 0
+ifeq ($(ENABLE_I2C_APP), 1)
+	TARGET_SRCS += \
+		$(FSP_SRC_DIR)/soc/t234/ids/aon/i2c-tegra-ids.c
+endif
+
+# 0 Builds for AGX Orin; 1 Builds for Orin Nano
+ENABLE_SPE_FOR_ORIN_NANO := 0